Patent Description:
The present disclosure generally relates to the field of processors. More particularly, some embodiments relate to the applications and/or methods for register file prefetch.

Generally, a register file of a processor includes a plurality of processor registers. In most modern processors, Static Random-Access Memory (SRAM) is used to implement a register file.

Since processor operations rely on register files to store data for various processor operations, implementation of a register file can have a direct impact on processor performance.

<CIT> discloses a method for expanding preload capabilities of a memory to encompass a register file. The method comprises predicting an address of a memory location containing data to be accessed by a first memory operation instruction that has not yet executed, prior to the first memory operation instruction executing moving the data in the memory location to an unassigned register file entry, and causing a renaming register to assign the register file entry to an architectural register. Responsive to the renaming register assigning the register file entry to the architectural register, the method further comprises permitting a second instruction to execute using the data moved to the register file, wherein the second instruction is dependent on the first memory operation instruction.

<CIT> discloses an apparatus and method for controlling use of a register cache. The apparatus has execution circuitry for executing instructions to process data values, and a register file comprising a plurality of registers in which to store the data values for access by the execution circuitry. A register cache is also provided that has a plurality of entries and is arranged to cache a subset of the data values for access by the execution circuitry. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry then performs prefetch operations to prefetch data values from the register file into the register cache. Timing indication storage is used to store, for each data value to be generated as a result of instructions being executed within the execution circuitry, a register identifier for that data value, and timing information indicating when that data value will be generated by the execution circuitry. Cache usage control circuitry is then responsive to receipt of a plurality of register identifiers associated with source data values for a pending instruction yet to be executed by the execution circuitry, to generate, with reference to the timing information in the timing indication storage, a timing control signal to control timing of at least one prefetch operation performed by the prefetch circuitry.

<CIT> discloses: systems, apparatuses, and methods for implementing a non-shifting reservation station. A dispatch unit may write an operation into any entry of a reservation station. The reservation station may include an age matrix for determining the relative ages of the operations stored in the entries of the reservation station. The reservation station may include selection logic which is configured to pick the oldest ready operation from the reservation station based on the values stored in the age matrix. The selection logic may utilize control logic to mask off columns of an age matrix corresponding to non-ready operation so as to determine which operation is the oldest ready operation in the reservation station. Also, the reservation station may be configured to dequeue operations early when these operations do not have load dependency.

<NPL>, discloses a pipeline prefetching technique that achieves state-of-the-art performance and data reuse without additional data storage, data movement, or validation overheads by adding address tags to the register file.

The detailed description is provided with reference to the accompanying figures.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments. Further, various aspects of embodiments may be performed using various means, such as integrated semiconductor circuits ("hardware"), computer-readable instructions organized into one or more programs ("software"), or some combination of hardware and software. For the purposes of this disclosure reference to "logic" shall mean either hardware (such as logic circuitry or more generally circuitry or circuit), software, firmware, or some combination thereof.

As mentioned above, implementation of a register file can have a direct impact on processor performance. Generally, prefetching data can be used to reduce the effective latency of load operations. However, most of the prefetching work has only been focused on memory to cache prefetching.

To this end, some embodiments provide techniques for Register File Prefetch (RFP). In an embodiment, a prefetch operation is performed from a Level <NUM> (L1) cache (also referred to herein interchangeably as a Data Cache Unit (DCU)) to a Register File ("RF" which is sometimes also referred to as a Physical Register File (PRF)). This register file prefetch operation (referred to herein sometimes as "RFP") may effectively reduce/hide the L1 cache latency by prefetching load data into a register file, in turn, potentially providing a significant Instructions Per Cycle (IPC) improvement. As discussed herein, a "register file" generally refers to a plurality of registers. Further, the plurality of registers, forming a register file, do not necessarily need to include a contiguous block of registers.

In an embodiment, the RFP operation is performed using a predicted address and the corresponding load operation, upon execution, checks whether the predicted address matches the load address. If there is a match, the prefetched data is supplied to the dependent operation(s), and the load operation effectively bypasses the caches. Otherwise, if there is a mismatch during execution between the predicted address and the load address, the load operation proceeds with an Out-Of-Order (OOO) processor pipeline cache access and supplies the load data to the dependent operation(s).

Moreover, since L1 and PRF bandwidths are at a premium in processors, an RFP request may need to be smartly issued to not affect L1/PRF bandwidth. To achieve this goal, two solutions may be utilized in various embodiments:.

<FIG> illustrates some components of an OOO processor core <NUM> to support an RFP operation, according to an embodiment. Further details of a sample architecture for a register file are discussed with reference to <FIG>. <FIG> provides some details about both an exemplary in-order processor core pipeline and an exemplary register renaming, out-of-order issue/execution processor core pipeline. <FIG> provides some details about both an exemplary embodiment of an in-order architecture processor core and an exemplary register renaming, out-of-order issue/execution architecture processor core. Moreover, one or more components of the core <NUM> may be the same or similar to components having the same names discussed with reference to <FIG>, <FIG>.

Referring to <FIG>, the OOO processor core <NUM> includes a front-end <NUM> with fetch and decode logic (see, e.g., the discussion of pipeline <NUM> of <FIG> and/or the front end <NUM> of <FIG>). The front-end <NUM> also includes an instruction queue <NUM>.

In an embodiment, the RFP request is issued as soon as a load operation allocation occurs for OOO allocation. In one embodiment, the RFP operation is performed after a rename stage <NUM> in the OOO execution engine <NUM> where the OOO execution engine <NUM> includes one or more execution units <NUM> (see, e.g., renaming stage <NUM> of <FIG> and/or the rename/allocator circuitry <NUM> of <FIG> occurring after allocation). For example, the RFP request causes a look up in a prefetch table <NUM> with the Program Counter (PC) <NUM> of the load operation. In various embodiments, constant and/or stride prefetching may be allowed. The prefetch table <NUM> then issues a prefetch operation for a predicted address <NUM> and this prefetch operation causes a writeback to the same PRF entry that was assigned to the load operation in the register file <NUM>.

When the load operation is issued, it wakes up its dependent operation in the next cycle. In an Address Generation Unit (AGU), the load address is checked with the prefetch address. If the two addresses match, the load operation is simply dropped and the prefetched value is supplied to the dependent operation. If the addresses do not match, the dependent operation is restarted, and waits for the original load operation (like the baseline) to execute. One or more embodiments result in approximately a <NUM>% Geomean on server workloads.

Referring back to <FIG>, "RFP" can provide a mechanism for prefetching data (e.g., using a prefetch packet <NUM> generated after the rename stage <NUM> and sent to the L1/data cache <NUM> and Load Store Queue (LSQ) <NUM>) from the L1 cache or DCU <NUM> into the physical register file <NUM>. By doing so, the original load operation need not go to the L1 cache <NUM> to obtain data but it may simply gain access to the data from the register file <NUM> (as long as the RFP address and load address match; otherwise, the load operation has to perform an L1 cache access). Therefore, a successful RFP shortens the latency of a load operation from approximately five cycles to one cycle in some implementations, which would significantly improve the system performance.

Further, in some embodiments, there are at least two ways in which a register prefetch may be executed:.

By contrast, some ISA instructions may only support transfer of data between the cache levels and no prefetch data movement into the register file.

Furthermore, one or more instructions/ISAs discussed herein may comply with instruction formats detailed herein, e.g., with reference to <FIG> et seq.

RFP may be tracked using simple micro-benchmarks to test the latency of the L1 cache. These are variations of the classic Load Latency benchmark. One such benchmark is shown below:
<IMG>.

The runtime of the above is relatively easy to ascertain given the L1 cache latency versus in the presence of prefetching.

Moreover, in an embodiment, RFP provides a method of bringing load data from the L1 cache into the register file in anticipation of a future use. The load operation can use the data from the register file and save a trip to the L1 cache. This reduces a load operation's execution latency which, in turn, improves processor core performance.

Some compilers can identify loops in the program easily. Take the following example:
<IMG>.

In the above loop, the load addresses are incrementing by one every iteration.

In the above code too, the load address is dependent on the iteration variable and has strided patterns.

In one embodiment, a compiler is configured to identify such loops where the load operation is dependent on the iteration variable. The compiler then inserts a hint along with the load operation. The x86 ISA already contains software prefetch instructions like Prefetch T0, Prefetch T1, etc., which can bring data to a specific cache level. Another prefetch instruction (e.g., Prefetch R) can be added, which brings data for the PRF. The modified code from example may look as follows:
<IMG>.

In an embodiment, this "Prefetch R" instruction may be used as a hint for opportunistic fetching of data and, as such, does not modify any architectural state.

Details of RFP hardware logic are discussed with reference to <FIG> above as well as below through the following operations: (<NUM>) address prediction of the concerned load operation; (<NUM>) launching a prefetch; (<NUM>) load pipeline in the presence of RFP; and/or (<NUM>) handling store-load forwarding, memory disambiguation and clears.

RFP may guess the address of a load operation ahead of time so as to launch a prefetch request while the load operation waits for its own execution. To do this, RFP may utilize an address predictor logic (e.g., prefetch table <NUM> of <FIG>) which predicts the load address at OOO allocation. The address predictor logic can be designed to track constant and/or strided addresses. When a load causes a writeback, the predictor logic snoops its address and records it in a table (e.g., prefetch table <NUM> of <FIG>).

In an embodiment, on every load writeback (e.g., at operation <NUM> of <FIG>), the predictor logic checks if the address is constant or has a fixed stride. If so, the predictor logic increments a confidence indicator for a corresponding table entry. Otherwise, the predictor logic resets the confidence following which the entry eventually is evicted from the table. Once sufficient confidence is achieved on the address pattern, the address predictor logic marks the load PC as "RFP prefetch-able".

At OOO allocation, the address predictor logic marks a load operation for RFP based on its confidence on the load PC. For the marked load, a prefetch packet (e.g., prefetch packet <NUM> of <FIG>) is created which contains the predicted address and the load operation's register file Identifier (ID). The prefetch packet is sent to a Memory Execution Unit (MEU) (not shown) where it arbitrates with other loads/RFP's for access to the L1 cache. In an embodiment, the LSQ <NUM> is a part of the MEU and holds all the loads/stores in the current OOO execution window and is used to ensure their ordering. Once the RFP gets access, it takes a few cycles (e.g., approximately five cycles), e.g., due to L1 latency, for the prefetch to bring data from the L1 cache (<NUM>) into the register file (<NUM>). After the prefetch is complete, a flag may be set informing the original load micro-op/operation that the prefetched data is successfully deposited in the register file.

In an embodiment, L1 cache misses arising from RFP requests are disallowed to proceed. Therefore, if an RFP request misses in the L1 cache, the prefetch may be canceled. This is to prevent unnecessary bandwidth hogging by RFP requests.

In one embodiment, the load pipeline is modified to support the following three RFP scenarios:.

When the RFP is issued at load allocation, it is possible that there are older stores which are yet to execute or are inflight. These stores could potentially modify the data at the load's memory address. Therefore, the RFP request needs to account for all such stores which can potentially modify the data.

When an RFP is launched to the MEU, it scans all stores older than itself (starting from the youngest older store) and matches its address against the store's address. If there is a match, it waits for the store to complete and writes the store data into the register file.

If a store's address is unavailable (implying the store is yet to execute), the Memory Disambiguation (MD) mechanism may be relied on to decide whether the RFP needs to wait on the store or skip it. Based on the MD prediction, the RFP request proceeds accordingly and obtains the most updated data from an older store or the L1 cache. If the MD prediction was wrong, the entire machine may be flushed and execution restarted from the load instruction.

Lastly, if there are any Jump Execution Clears (JEClears), nukes, exceptions, etc. in the pipeline caused by instructions older than the RFP load, the prefetched data is removed.

Referring to <FIG>, in one embodiment, a Reservation Station (RS) <NUM> tracks the progress of the RFP based on one or more RFP-Inflight bits. And, when an RFP request is issued at load allocation in the RS <NUM>, there may be older stores in a Reorder Buffer (ROB) <NUM> that are yet to execute or are inflight. To this end, in at least one embodiment, when an RFP request is launched to the L1 cache <NUM> and LSQ <NUM>, all older stores (in a youngest-first order) in the ROB <NUM> are scanned and their addresses matched against the store's address. As discussed above, on a match, RFP waits for the store to complete and uses the stored data instead of the cached data for the prefetch.

<FIG> illustrates a flowchart of a method <NUM> for an RFP operation and interaction with a load pipeline, according to an embodiment. One or more operations of method <NUM> may be performed by the components discussed with reference to <FIG> and <FIG>.

Referring to <FIG> and <FIG>, at an operation <NUM>, a load operation is allocated (e.g., in the RS <NUM>). At an operation <NUM>, it is determined whether operands of the load operation are ready. Subsequently, at an operation <NUM>, the load operation is dispatched to the execution unit (e.g., OOO execution unit <NUM>). At an operation <NUM>, it is determined whether an RFP is issued for the load operation and, if so, an operation <NUM> determines whether the predicted address of the RFP matches the load address. If there is a match, the prefetched data is supplied to the dependent operation(s) at an operation <NUM>, and the load operation effectively bypasses the caches. Otherwise, if an RFP request is not issued or if there is a mismatch at operation <NUM> between the predicted address and the load address, the load operation proceeds with an Out-Of-Order (OOO) processor pipeline cache access (e.g., via the MEU) at an operation <NUM> to supply the load data to the dependent operation(s). After operations <NUM> or <NUM>, method <NUM> continues with a load operation writeback at an operation <NUM>, which causes an indication/signal to be transmitted to one or more dependent operations of the load operation to indicate that the load data is ready to be consumed from the load's PRF entry. Moreover, the actual data write operation to the load's PRF entry may have occurred well before any of the <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> operations when the corresponding RFP request completes. After operation <NUM>, method <NUM> proceeds to an operation <NUM> to continue predictor training.

After the load operation allocation (<NUM>), an operation <NUM> determines whether there is corresponding a high confidence for the load operation in the prefetch table <NUM> and, if not, method <NUM> proceeds to the operation <NUM> to continue training the predictor. Otherwise, if there is high confidence for the load operation present, an operation <NUM>, an RFP prefetch packet is transmitted to the MEU and L1 cache <NUM> access arbitration is performed at an operation <NUM>. After the PRF request wins the L1 cache access arbitration at operation <NUM>, an operation <NUM> determines whether an older matching store is present (e.g., in the ROB <NUM>). If so, an operation <NUM> performs store-load forwarding; otherwise, method <NUM> continues at an operation <NUM> to access the L1 cache <NUM>. After operations <NUM> or <NUM>, an operation <NUM> performs an RFP writeback to inform the load operation and RFP data is communicated to the load pipeline.

<FIG> illustrates a sample graph <NUM> of IPC gains from RFP over a baseline, according to an embodiment.

As shown in <FIG>, RFP may deliver approximately <NUM>% Geometric mean (Geomean) performance on a server configuration. Important applications like cloud demonstrate significantly high gains of approximately <NUM>% from RFP. In <FIG>, "HPC" refers to High Performance Computing.

As detailed herein, Register File Prefetch is a novel mechanism for solving the fundamental issue of memory latency plaguing modern superscalar processors. By virtually eliminating the trip to L1 cache, RFP saves crucial cycles from the critical path of the program and thus achieves significant performance improvement. As such, this technology is of high importance to current and future generation of processors.

Additionally, some embodiments may be applied in computing systems that include one or more processors (e.g., where the one or more processors may include one or more processor cores), such as those discussed with reference to <FIG> et seq. , including for example a desktop computer, a workstation, a computer server, a server blade, or a mobile computing device. The mobile computing device may include a smartphone, tablet, UMPC (Ultra-Mobile Personal Computer), laptop computer, Ultrabook™ computing device, wearable devices (such as a smart watch, smart ring, smart bracelet, or smart glasses), etc..

An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. A set of SIMD extensions referred to as the Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) coding scheme has been released and/or published (e.g., see Intel® <NUM> and IA-<NUM> Architectures Software Developer's Manual, September <NUM>; and see Intel® Advanced Vector Extensions Programming Reference, October <NUM>).

Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

While embodiments will be described in which the vector friendly instruction format supports the following: a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte) or <NUM> bit (<NUM> byte) data element widths (or sizes) (and thus, a <NUM> byte vector consists of either <NUM> doubleword-size elements or alternatively, <NUM> quadword-size elements); a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte) or <NUM> bit (<NUM> byte) data element widths (or sizes); a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), or <NUM> bit (<NUM> byte) data element widths (or sizes); and a <NUM> byte vector operand length (or size) with <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), <NUM> bit (<NUM> byte), or <NUM> bit (<NUM> byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., <NUM> byte vector operands) with more, less, or different data element widths (e.g., <NUM> bit (<NUM> byte) data element widths).

<FIG> is a block diagram illustrating an exemplary instruction format according to embodiments. <FIG> shows an instruction format <NUM> that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The instruction format <NUM> may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R/M field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions.

EVEX Prefix (Bytes <NUM>-<NUM>) <NUM> - is encoded in a four-byte form.

Format Field <NUM> (EVEX Byte <NUM>, bits [<NUM>:<NUM>]) - the first byte (EVEX Byte <NUM>) is the format field <NUM> and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment).

The second-fourth bytes (EVEX Bytes <NUM>-<NUM>) include a number of bit fields providing specific capability.

REX field <NUM> (EVEX Byte <NUM>, bits [<NUM>-<NUM>]) - consists of a EVEX. R bit field (EVEX Byte <NUM>, bit [<NUM>] - R), EVEX. X bit field (EVEX byte <NUM>, bit [<NUM>] - X), and 357BEX byte <NUM>, bit[<NUM>] - B). X, and EVEX. B bit fields provide the same functionality as the corresponding VEX bit fields, and are encoded using <NUM> complement form, i.e., ZMM0 is encoded as 411B, ZMM15 is encoded as 0000B. Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding EVEX. X, and EVEX.

REX' field QAc10 - this is the EVEX. R' bit field (EVEX Byte <NUM>, bit [<NUM>] - R') that is used to encode either the upper <NUM> or lower <NUM> of the extended <NUM> register set. In one embodiment, this bit, along with others as indicated below, is stored in bit inverted format to distinguish (in the well-known x86 <NUM>-bit mode) from the BOUND instruction, whose real opcode byte is <NUM>, but does not accept in the MOD R/M field (described below) the value of <NUM> in the MOD field; alternative embodiments do not store this and the other indicated bits below in the inverted format. A value of <NUM> is used to encode the lower <NUM> registers. In other words, R'Rrrr is formed by combining EVEX. R, and the other RRR from other fields.

Opcode map field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>] - mmmm) - its content encodes an implied leading opcode byte (0F, 0F <NUM>, or 0F <NUM>).

Data element width field <NUM> (EVEX byte <NUM>, bit [<NUM>] - W) - is represented by the notation EVEX. W is used to define the granularity (size) of the datatype (either <NUM>-bit data elements or <NUM>-bit data elements). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes.

vvvv <NUM> (EVEX Byte <NUM>, bits [<NUM>:<NUM>]-vvvv)- the role of EVEX. vvvv may include the following: <NUM>) EVEX. vvvv encodes the first source register operand, specified in inverted (<NUM> complement) form and is valid for instructions with <NUM> or more source operands; <NUM>) EVEX. vvvv encodes the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) EVEX. vvvv does not encode any operand, the field is reserved and should contain 411b. Thus, EVEX. vvvv field <NUM> encodes the <NUM> low-order bits of the first source register specifier stored in inverted (<NUM> complement) form. Depending on the instruction, an extra different EVEX bit field is used to extend the specifier size to <NUM> registers.

U <NUM> Class field (EVEX byte <NUM>, bit [<NUM>]-U) - If EVEX. U = <NUM>, it indicates class A (support merging-writemasking) or EVEX. U0; if EVEX. U = <NUM>, it indicates class B (support zeroing and merging-writemasking)or EVEX.

Prefix encoding field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]-pp) - provides additional bits for the base operation field. In addition to providing support for the legacy SSE instructions in the EVEX prefix format, this also has the benefit of compacting the SIMD prefix (rather than requiring a byte to express the SIMD prefix, the EVEX prefix requires only <NUM> bits). In one embodiment, to support legacy SSE instructions that use a SIMD prefix (<NUM>, F2H, F3H) in both the legacy format and in the EVEX prefix format, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and at runtime are expanded into the legacy SIMD prefix prior to being provided to the decoder's PLA (so the PLA can execute both the legacy and EVEX format of these legacy instructions without modification). Although newer instructions could use the EVEX prefix encoding field's content directly as an opcode extension, certain embodiments expand in a similar fashion for consistency but allow for different meanings to be specified by these legacy SIMD prefixes. An alternative embodiment may redesign the PLA to support the <NUM> bit SIMD prefix encodings, and thus not require the expansion.

Alpha field <NUM> (EVEX byte <NUM>, bit [<NUM>] - EH; also known as EVEX. writemask control, and EVEX. N; also illustrated with α) - its content distinguishes which one of the different augmentation operation types are to be performed.

Beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]-SSS, also known as EVEX. s2-<NUM>, EVEX. r2-<NUM>, EVEX. LLB; also illustrated with βββ) - distinguishes which of the operations of a specified type are to be performed.

REX' field <NUM> - this is the remainder of the REX' field and is the EVEX. V' bit field (EVEX Byte <NUM>, bit [<NUM>] - V') that may be used to encode either the upper <NUM> or lower <NUM> of the extended <NUM> register set. This bit is stored in bit inverted format. A value of <NUM> is used to encode the lower <NUM> registers. In other words, V'VVVV is formed by combining EVEX.

Writemask field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]-kkk) - its content specifies the index of a register in the writemask registers. In one embodiment, the specific value EVEX. kkk=<NUM> has a special behavior implying no writemask is used for the particular instruction (this may be implemented in a variety of ways including the use of a writemask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a <NUM>. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to <NUM> when the corresponding mask bit has a <NUM> value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the writemask field <NUM> allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments are described in which the writemask field's <NUM> content selects one of a number of writemask registers that contains the writemask to be used (and thus the writemask field's <NUM> content indirectly identifies that masking to be performed), alternative embodiments instead or additionally allow the mask write field's <NUM> content to directly specify the masking to be performed.

Real Opcode Field <NUM> (Byte <NUM>) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field <NUM> (Byte <NUM>) includes MOD field <NUM>, register index field <NUM>, and R/M field <NUM>. The MOD field's <NUM> content distinguishes between memory access and non-memory access operations. The role of register index field <NUM> can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The content of register index field <NUM>, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory. These include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 7x128, 32x1024, 64x1024) register file. While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support more or less sources and destination registers (e.g., may support up to two sources where one of these sources also acts as the destination, may support up to three sources where one of these sources also acts as the destination, may support up to two sources and one destination).

The role of R/M field <NUM> may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte <NUM>) - The scale field's <NUM> content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale * index + base). xxx <NUM> and SIB. bbb <NUM> - the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field 363A (Bytes <NUM>-<NUM>) - when MOD field <NUM> contains <NUM>, bytes <NUM>-<NUM> are the displacement field 363A, and it works the same as the legacy <NUM>-bit displacement (disp32) and works at byte granularity. This may be used as part of memory address generation (e.g., for address generation that uses 2scale * index + base + displacement).

Displacement factor field 363B (Byte <NUM>) - when MOD field <NUM> contains <NUM>, byte <NUM> is the displacement factor field 363B. The location of this field is that same as that of the legacy x86 instruction set <NUM>-bit displacement (disp8), which works at byte granularity. Since disp8 is sign extended, it can only address between -<NUM> and <NUM> bytes offsets; in terms of <NUM> byte cache lines, disp8 uses <NUM> bits that can be set to only four really useful values -<NUM>, -<NUM>, <NUM>, and <NUM>; since a greater range is often needed, disp32 is used; however, disp32 requires <NUM> bytes. In contrast to disp8 and disp32, the displacement factor field 363B is a reinterpretation of disp8; when using displacement factor field 363B, the actual displacement is determined by the content of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8*N. This reduces the average instruction length (a single byte of used for the displacement but with a much greater range). Such compressed displacement is based on the assumption that the effective displacement is multiple of the granularity of the memory access, and hence, the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 363B substitutes the legacy x86 instruction set <NUM>-bit displacement. Thus, the displacement factor field 363B is encoded the same way as an x86 instruction set <NUM>-bit displacement (so no changes in the ModRM/SIB encoding rules) with the only exception that disp8 is overloaded to disp8*N. In other words, there are no changes in the encoding rules or encoding lengths but only in the interpretation of the displacement value by hardware (which needs to scale the displacement by the size of the memory operand to obtain a byte-wise address offset).

Immediate field <NUM> allows for the specification of an immediate. This field is optional in the sense that is it not present in an implementation of the generic vector friendly format that does not support immediate and it is not present in instructions that do not use an immediate.

<FIG> is a block diagram illustrating the fields of the instruction format <NUM> that make up the full opcode field <NUM> according to one embodiment. Specifically, the full opcode field <NUM> includes the format field <NUM>, the base operation field <NUM>, and the data element width (W) field <NUM>. The base operation field <NUM> includes the prefix encoding field <NUM>, the opcode map field <NUM>, and the real opcode field <NUM>.

<FIG> is a block diagram illustrating the fields of the format <NUM> that make up the register index field <NUM> according to one embodiment. Specifically, the register index field <NUM> includes the REX field <NUM>, the REX' field <NUM>, the MODR/M. reg field <NUM>, the MODR/M. r/m field <NUM>, the VVVV field <NUM>, xxx field <NUM>, and the bbb field <NUM>.

<FIG> is a block diagram illustrating the fields of the instruction format <NUM> that make up an augmentation operation field according to one embodiment. When the class (U) field <NUM> contains <NUM>, it signifies EVEX. U0 (class A 368A); when it contains <NUM>, it signifies EVEX. U1 (class B 368B). When U=<NUM> and the MOD field <NUM> contains <NUM> (signifying a no memory access operation), the alpha field <NUM> (EVEX byte <NUM>, bit [<NUM>] - EH) is interpreted as the rs field 353A. When the rs field 353A contains a <NUM> (round 353A. <NUM>), the beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]- SSS) is interpreted as the round control field 355A. The round control field 355A includes a one bit SAE field <NUM> and a two bit round operation field <NUM>. When the rs field 353A contains a <NUM> (data transform 353A. <NUM>), the beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]- SSS) is interpreted as a three bit data transform field 355B. When U=<NUM> and the MOD field <NUM> contains <NUM>, <NUM>, or <NUM> (signifying a memory access operation), the alpha field <NUM> (EVEX byte <NUM>, bit [<NUM>] - EH) is interpreted as the eviction hint (EH) field 353B and the beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]- SSS) is interpreted as a three bit data manipulation field 355C.

When U=<NUM>, the alpha field <NUM> (EVEX byte <NUM>, bit [<NUM>] - EH) is interpreted as the writemask control (Z) field 353C. When U=<NUM> and the MOD field <NUM> contains <NUM> (signifying a no memory access operation), part of the beta field <NUM> (EVEX byte <NUM>, bit [<NUM>]- S0) is interpreted as the RL field 357A; when it contains a <NUM> (round 357A. <NUM>) the rest of the beta field <NUM> (EVEX byte <NUM>, bit [<NUM>-<NUM>]- S2-<NUM>) is interpreted as the round operation field 359A, while when the RL field 357A contains a <NUM> (VSIZE <NUM>. A2) the rest of the beta field <NUM> (EVEX byte <NUM>, bit [<NUM>-<NUM>]- S2-<NUM>) is interpreted as the vector length field 359B (EVEX byte <NUM>, bit [<NUM>-<NUM>]- L1-<NUM>). When U=<NUM> and the MOD field <NUM> contains <NUM>, <NUM>, or <NUM> (signifying a memory access operation), the beta field <NUM> (EVEX byte <NUM>, bits [<NUM>:<NUM>]- SSS) is interpreted as the vector length field 359B (EVEX byte <NUM>, bit [<NUM>-<NUM>]- L1-<NUM>) and the broadcast field 357B (EVEX byte <NUM>, bit [<NUM>]- B).

<FIG> is a block diagram of a register architecture <NUM> according to one embodiment. In the embodiment illustrated, there are <NUM> vector registers <NUM> that are <NUM> bits wide; these registers are referenced as ZMM0 through ZMM31. The lower order <NUM> bits of the lower <NUM> ZMM registers are overlaid on registers YMM0-<NUM>. The lower order <NUM> bits of the lower <NUM> ZMM registers (the lower order <NUM> bits of the YMM registers) are overlaid on registers XMM0-<NUM>. In other words, the vector length field 459B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field 459B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the instruction format <NUM> operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in a ZMM/YMM/XMM register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Writemask registers <NUM> - in the embodiment illustrated, there are <NUM> writemask registers (k0 through k7), each <NUM> bits in size. In an alternate embodiment, the writemask registers <NUM> are <NUM> bits in size. In some embodiments, the vector mask register k0 cannot be used as a writemask; when the encoding that would normally indicate k0 is used for a writemask, it selects a hardwired writemask of 0xFFFF, effectively disabling writemasking for that instruction.

General-purpose registers <NUM> - in the embodiment illustrated, there are sixteen <NUM>-bit general-purpose registers that are used along with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) <NUM>, on which is aliased the MMX packed integer flat register file <NUM> - in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on <NUM>/<NUM>/<NUM>-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on <NUM>-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

Alternative embodiments may use wider or narrower registers. Additionally, alternative embodiments may use more, less, or different register files and registers.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high-performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU (Central Processing Unit) including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

The execution engine unit <NUM> includes the rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) <NUM> is coupled to the physical register file(s) unit(s) <NUM>. Each of the physical register file(s) units <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit <NUM> comprises a vector registers unit, a writemask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access units <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

<FIG> illustrates a block diagram of an SOC package in accordance with an embodiment. As illustrated in <FIG>, SOC <NUM> includes one or more Central Processing Unit (CPU) cores <NUM>, one or more Graphics Processor Unit (GPU) cores <NUM>, an Input/Output (I/O) interface <NUM>, and a memory controller <NUM>. Various components of the SOC package <NUM> may be coupled to an interconnect or bus such as discussed herein with reference to the other figures. Also, the SOC package <NUM> may include more or less components, such as those discussed herein with reference to the other figures. Further, each component of the SOC package <NUM> may include one or more other components, e.g., as discussed with reference to the other figures herein. In one embodiment, SOC package <NUM> (and its components) is provided on one or more Integrated Circuit (IC) die, e.g., which are packaged into a single semiconductor device.

As illustrated in <FIG>, SOC package <NUM> is coupled to a memory <NUM> via the memory controller <NUM>. In an embodiment, the memory <NUM> (or a portion of it) can be integrated on the SOC package <NUM>.

The I/O interface <NUM> may be coupled to one or more I/O devices <NUM>, e.g., via an interconnect and/or bus such as discussed herein with reference to other figures. I/O device(s) <NUM> may include one or more of a keyboard, a mouse, a touchpad, a display, an image/video capture device (such as a camera or camcorder/video recorder), a touch screen, a speaker, or the like.

<FIG> is a block diagram of a processing system <NUM>, according to an embodiment. In various embodiments the system <NUM> includes one or more processors <NUM> and one or more graphics processors <NUM>, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors <NUM> or processor cores <NUM>. In on embodiment, the system <NUM> is a processing platform incorporated within a system-on-a-chip (SoC or SOC) integrated circuit for use in mobile, handheld, or embedded devices.

An embodiment of system <NUM> can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments system <NUM> is a mobile phone, smart phone, tablet computing device or mobile Internet device. Data processing system <NUM> can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, data processing system <NUM> is a television or set top box device having one or more processors <NUM> and a graphical interface generated by one or more graphics processors <NUM>.

In some embodiments, processor <NUM> is coupled to a processor bus <NUM> to transmit communication signals such as address, data, or control signals between processor <NUM> and other components in system <NUM>. In one embodiment the system <NUM> uses an exemplary 'hub' system architecture, including a memory controller hub <NUM> and an Input Output (I/O) controller hub <NUM>. A memory controller hub <NUM> facilitates communication between a memory device and other components of system <NUM>, while an I/O Controller Hub (ICH) <NUM> provides connections to I/O devices via a local I/O bus. In one embodiment, the logic of the memory controller hub <NUM> is integrated within the processor.

Memory device <NUM> can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device <NUM> can operate as system memory for the system <NUM>, to store data <NUM> and instructions <NUM> for use when the one or more processors <NUM> executes an application or process. Memory controller hub <NUM> also couples with an optional external graphics processor <NUM>, which may communicate with the one or more graphics processors <NUM> in processors <NUM> to perform graphics and media operations.

In some embodiments, ICH <NUM> enables peripherals to connect to memory device <NUM> and processor <NUM> via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller <NUM>, a firmware interface <NUM>, a wireless transceiver <NUM> (e.g., Wi-Fi, Bluetooth), a data storage device <NUM> (e.g., hard disk drive, flash memory, etc.), and a legacy I/O controller <NUM> for coupling legacy (e.g., Personal System <NUM> (PS/<NUM>)) devices to the system. One or more Universal Serial Bus (USB) controllers <NUM> connect input devices, such as keyboard and mouse <NUM> combinations. A network controller <NUM> may also couple to ICH <NUM>. In some embodiments, a high-performance network controller (not shown) couples to processor bus <NUM>. It will be appreciated that the system <NUM> shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, the I/O controller hub <NUM> may be integrated within the one or more processor <NUM>, or the memory controller hub <NUM> and I/O controller hub <NUM> may be integrated into a discreet external graphics processor, such as the external graphics processor <NUM>.

<FIG> is a block diagram of an embodiment of a processor <NUM> having one or more processor cores 802A to 802N, an integrated memory controller <NUM>, and an integrated graphics processor <NUM>. Those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor <NUM> can include additional cores up to and including additional core 802N represented by the dashed lined boxes. Each of processor cores 802A to 802N includes one or more internal cache units 804A to 804N. In some embodiments each processor core also has access to one or more shared cached units <NUM>.

The internal cache units 804A to 804N and shared cache units <NUM> represent a cache memory hierarchy within the processor <NUM>. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level <NUM> (L2), Level <NUM> (L3), Level <NUM> (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units <NUM> and 804A to 804N.

In some embodiments, processor <NUM> may also include a set of one or more bus controller units <NUM> and a system agent core <NUM>. The one or more bus controller units <NUM> manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). System agent core <NUM> provides management functionality for the various processor components. In some embodiments, system agent core <NUM> includes one or more integrated memory controllers <NUM> to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 802A to 802N include support for simultaneous multi-threading. In such embodiment, the system agent core <NUM> includes components for coordinating and operating cores 802A to 802N during multi-threaded processing. System agent core <NUM> may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores 802A to 802N and graphics processor <NUM>.

In some embodiments, processor <NUM> additionally includes graphics processor <NUM> to execute graphics processing operations. In some embodiments, the graphics processor <NUM> couples with the set of shared cache units <NUM>, and the system agent core <NUM>, including the one or more integrated memory controllers <NUM>. In some embodiments, a display controller <NUM> is coupled with the graphics processor <NUM> to drive graphics processor output to one or more coupled displays. In some embodiments, display controller <NUM> may be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor <NUM> or system agent core <NUM>.

In some embodiments, a ring-based interconnect unit <NUM> is used to couple the internal components of the processor <NUM>. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor <NUM> couples with the ring interconnect <NUM> via an I/O link <NUM>.

The exemplary I/O link <NUM> represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module <NUM>, such as an eDRAM (or embedded DRAM) module. In some embodiments, each of the processor cores <NUM> to 802N and graphics processor <NUM> use embedded memory modules <NUM> as a shared Last Level Cache.

In some embodiments, processor cores 802A to 802N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores 802A to 802N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 802A to 802N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment processor cores 802A to 802N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processor <NUM> can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

<FIG> is a block diagram of a graphics processor <NUM>, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor <NUM> includes a memory interface <NUM> to access memory. Memory interface <NUM> can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In some embodiments, graphics processor <NUM> also includes a display controller <NUM> to drive display output data to a display device <NUM>. Display controller <NUM> includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. In some embodiments, graphics processor <NUM> includes a video codec engine <NUM> to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-<NUM>, Advanced Video Coding (AVC) formats such as H. <NUM>/MPEG-<NUM> AVC, as well as the Society of Motion Picture & Television Engineers (SMPTE) <NUM>/VC-<NUM>, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor <NUM> includes a block image transfer (BLIT) engine <NUM> to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 3D graphics operations are performed using one or more components of graphics processing engine (GPE) <NUM>. In some embodiments, graphics processing engine <NUM> is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In some embodiments, GPE <NUM> includes a 3D pipeline <NUM> for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline <NUM> includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system <NUM>. While 3D pipeline <NUM> can be used to perform media operations, an embodiment of GPE <NUM> also includes a media pipeline <NUM> that is specifically used to perform media operations, such as video post-processing and image enhancement.

In some embodiments, media pipeline <NUM> includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine <NUM>. In some embodiments, media pipeline <NUM> additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system <NUM>. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system <NUM>.

In some embodiments, 3D/Media subsystem <NUM> includes logic for executing threads spawned by 3D pipeline <NUM> and media pipeline <NUM>. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem <NUM>, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem <NUM> includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

In this description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the present embodiments.

In various embodiments, one or more operations discussed with reference to <FIG> et seq. may be performed by one or more components (interchangeably referred to herein as "logic") discussed with reference to any of the figures.

In various embodiments, the operations discussed herein, e.g., with reference to <FIG> et seq. , may be implemented as hardware (e.g., logic circuitry), software, firmware, or combinations thereof, which may be provided as a computer program product, e.g., including one or more tangible (e.g., non-transitory) machine-readable or computer-readable media having stored thereon instructions (or software procedures) used to program a computer to perform a process discussed herein. The machine-readable medium may include a storage device such as those discussed with respect to the figures.

Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals provided in a carrier wave or other propagation medium via a communication link (e.g., a bus, a modem, or a network connection).

Further, while various embodiments described herein may use the term System-on-a-Chip or System-on-Chip ("SoC" or "SOC") to describe a device or system having a processor and associated circuitry (e.g., Input/Output ("I/O") circuitry, power delivery circuitry, memory circuitry, etc.) integrated monolithically into a single Integrated Circuit ("IC") die, or chip, the present disclosure is not limited in that respect. For example, in various embodiments of the present disclosure, a device or system may have one or more processors (e.g., one or more processor cores) and associated circuitry (e.g., I/O circuitry, power delivery circuitry, etc.) arranged in a disaggregated collection of discrete dies, tiles, and/or chiplets (e.g., one or more discrete processor core die arranged adjacent to one or more other die such as a memory die, I/O die, etc.). In such disaggregated devices and systems, the various dies, tiles, and/or chiplets may be physically and/or electrically coupled together by a package structure including, for example, various packaging substrates, interposers, active interposers, photonic interposers, interconnect bridges, and the like. The disaggregated collection of discrete dies, tiles, and/or chiplets may also be part of a System-on-Package ("SoP").

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, and/or characteristic described in connection with the embodiment may be included in at least an implementation. The appearances of the phrase "in one embodiment" in various places in the specification may or may not be all referring to the same embodiment.

Also, in the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

Claim 1:
An apparatus comprising:
a register file (<NUM>), to be formed by a plurality of registers, wherein the register file (<NUM>) comprises a plurality of register file entries; and
execution circuitry (<NUM>) to cause issuance of a prefetch request to cause data to be prefetched from a data cache unit (<NUM>) into an entry of the register file (<NUM>),
wherein the prefetch request is to be issued in response to allocation of a load operation, and
wherein the execution circuitry (<NUM>) is to store an indication of whether a prefetch operation is to be performed for the prefetch request in a prefetch table (<NUM>),
characterized in that the indication is to be updated based on a hint provided by one of: an instruction, a compiler, a software application, an operating system,
wherein the hint is included in one or more bits in an operand of a load instruction corresponding to the load operation.