Patent Description:
For the conventional insulated gate bipolar transistor (IGBT) device, if the device wants to obtain a lower on-state voltage drop Von, the carrier implantation efficiency thereof needs to be enhanced. However, the size of a safety operating area (SOA) of the device may be reduced, meanwhile, the increased carrier concentration may lower the switching speed when the device is switched, and may result in a tail current, thereby making the turn-off loss high.

<CIT> discloses a bipolar transistor including a substrate and a first well in the substrate having a first dopant type. The bipolar transistor further includes a split collector region in the first well including a highly doped central region having a second dopant type opposite the first dopant type and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region.

<CIT> discloses a bipolar semiconductor switch having a semiconductor body including a first p-type semiconductor region, a second p-type semiconductor region, and a first n-type semiconductor region forming a first pn-junction with the first p-type semiconductor region and a second pn-junction with the second p-type semiconductor region.

<CIT> discloses a latch-preventing N type silicon on insulator transverse isolated gate bipolar transistor which comprises an N type substrate provided with buried oxide, the buried oxide is provided with an N type epitaxial layer internally provided with an N type buffering trap and a P type body region. The N type buffering trap is internally provided with a P type positive region provided with an N type negative region and a P type body contact region, and the surface of the N type epitaxial layer is provided with a gate oxide layer and a field oxide layer. The surfaces of the N type negative region and the P type body contact region are provided with shallow P type trap regions, the surface of the gate oxide layer is provided with a polysilicon gate, and the surfaces of the field oxide layer, the P type body contact region, the N type negative region, the polysilicon gate and the P type positive region are provided with a passivation layer respectively. Further, the positive inferior of the shallow P type trap region is also provided with a deep P type trap region arranged under the shallow P type trap region, which shares one photoetching plate together with the shallow P type trap region and is formed by injection of high energy ions.

Accordingly, it is necessary to provide an insulated gate bipolar transistor with low on-state voltage drop and large safe operating area.

An insulated gate bipolar transistor includes: a drift region of a first conductivity type; a body region of a second conductivity type disposed on the drift region; a cathode first conductivity-type region and a cathode second conductivity-type region both disposed within the body region; an anode first conductivity-type region disposed on the drift region; and an anode second conductivity-type region disposed on the drift region. The anode first conductivity-type region includes a first region and a second region; and the anode second conductivity-type region includes a third region and a fourth region. A dopant concentration of the first region is less than a dopant concentration of the second region; and a dopant concentration of the third region is less than a dopant concentration of the fourth region. The third region is disposed between the fourth region and the body region. The first region is disposed below the fourth region. The second region is disposed below the third region and disposed between the first region and the body region. The first conductivity type is opposite to the second conductivity type.

The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, purposes and advantages of present disclosure will become apparent from the description, drawings and claims.

In order to better describe and explain the embodiments and/or examples of the present disclosure herein, one or more drawings can be referred to. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any one of the disclosed inventions, the described embodiments and/or examples, and the preferred embodiments of the present disclosure.

For the convenience of understanding the present disclosure, a more comprehensive description of the present disclosure will be made by referring the accompanying drawings below. A preferred embodiment of the present disclosure is given in the accompanying drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those persons skilled in the art. The terms used in the description of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. The term "and/or" used herein should include any one of and all of the combinations of one or more relevant listed items.

It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" other elements or layers, it can be directly on, directly adjacent to, directly connected to, or directly coupled to the other elements or layers, or there may be a intervening element or layer therebetween. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer therebetween. It should be understood that although the terms such as first, second, third, and the like can be used to describe various elements, components, regions, layers and/or portions, these elements, components, regions, layers and/or portions should not be limited by these terms. These terms are only used to distinguish an element, a component, a region, a layer or a portion from another element, another component, another region, another layer or another portion. Therefore, a first element, a first component, a first region, a first layer or a first portion discussed hereinafter can be represented as a second element, a second component, a second region, a second layer or a second portion, respectively, without departing from the teachings of the present disclosure.

For the convenience of description, the spatial relationship terms such as "under", "below", "beneath", "above", "over", "on" and the like are used herein to describe the relationship between an element or a feature and other elements or features shown in the figures. It should be understood that, in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of devices in use and operation. For example, if a device in the figures is reversed, an element or a feature, which is described as being "below", "under", or "beneath" other elements, can be oriented as being "over", "above", or "on" the other elements or features. Therefore, the exemplary terms such as "under", "below", "beneath" can include both an upward orientation and a downward orientation, respectively. The device can be otherwise oriented (rotated by <NUM> degrees or other orientations) and the spatial relationship terms used herein are interpreted accordingly.

The purpose of the terms used herein is only to describe specific embodiments and not as a limitation of the present disclosure. The singular form articles "a" "an", and "the", when used herein, are intended to include plural forms, unless the context clearly indicates a specific form. It should also be understood that the terms "comprise", and/or "include", when used herein, are intended to determine the existence of a feature, an integer, a step, an operation, an element and/or a component, but not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components, and/or a combination thereof. The term "and/or", when used herein, includes any one of and all combinations of related listed items.

The various embodiments of the present disclosure are described herein with reference to a cross-sectional view which is a schematic view of referred embodiments (including an intermediate structure) of the present disclosure. In this way, any changes from the shown shape due to, for example, the manufacturing technology and/or tolerances can be expected. Therefore, the various embodiments of the present disclosure should not be limited to specific shapes in areas shown in the figures, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle generally has a rounded feature or curved feature at its edge and/or has an implanted concentration gradient, rather than has a binary change from an implanted region to a non-implanted region. Likewise, since a buried region is formed by a performing process, there may be an implantation in a certain region between surfaces through which the implantation is performed when performing the implanting process and forming the buried region. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device, and are not intended to limit the scope of the present disclosure.

The semiconductor field of terms used herein are common technical terms used by a person skilled in the art, for example, as to a P type impurity and an N type impurity, in order to a distinguish dopant concentration, the P+ type is simply represented as a P type with heavily dopant concentration, the P type is represented as a P type with normal dopant concentration, the P- type is represented as a P type with lightly dopant concentration, the N+ type is simply represented as a N type with heavily dopant concentration, the N type is represented as a N type with normal dopant concentration, and the N- type is represented as a N type with lightly dopant concentration.

In order to obtain a low on-state voltage drop and a large safe operating area of an insulated gate bipolar transistor (IGBT), the anode implantation of minority carriers needs to be enhanced when the IGBT is in an on-state, and to be weakened or ideally eliminated during a turn-off or short-circuit switching. Those have been achieved in the dynamic N-buffer insulated gate bipolar transistor (DB-IGBT) and the double trench insulated gate bipolar transistor (DT-IGBT). However, both of the devices require two gates, and during a turn-off process and a short-circuit switching process, the time phases of switching signals of the two gates needs to be accurately controlled to obtain the ideal performance, which makes the drive circuit therefor complicated.

<FIG> is a schematic cross-sectional view of an insulated gate bipolar transistor (IGBT) in an embodiment. The IGBT includes a drift region <NUM>, a body region <NUM>, a cathode first conductivity-type region <NUM>, a cathode second conductivity-type region <NUM>, an anode first conductivity-type region (including a first region <NUM> and a second region <NUM>), and an anode second conductivity-type region (including a third region <NUM> and a fourth region <NUM>).

The body region <NUM> of the second conductivity type is disposed on the drift region <NUM> of the first conductivity type. The cathode first conductivity-type region <NUM> and the cathode second conductivity-type region <NUM> are disposed within the body region <NUM>. The anode first conductivity-type region and the anode second conductivity-type region are disposed on the drift region <NUM>. In the embodiment shown in <FIG>, the first conductivity type is an N type, and the second conductivity type is a P type. In another embodiment, the first conductivity type is a P type, and the second conductivity type is an N type.

A dopant concentration of the first region <NUM> is less than a dopant concentration of the second region <NUM>, and a dopant concentration of the third region <NUM> is less than a dopant concentration of the fourth region <NUM>. The third region <NUM> is disposed between the fourth region <NUM> and the body region <NUM>, and the first region <NUM> is disposed below the fourth region <NUM>. The second region <NUM> is disposed below the third region <NUM> and disposed between the first region <NUM> and the body region <NUM>. In the embodiment shown in <FIG>, a distance between the third region <NUM> and the body region <NUM> is less than a distance between the fourth region <NUM> and the body region <NUM>, and a distance between the second region <NUM> and the body region <NUM> is less than a distance between the first region <NUM> and the body region <NUM>.

In the embodiment shown in <FIG>, the IGBT further includes a buffer layer <NUM> of the first conductivity type. The anode first conductivity-type region and the anode second conductivity-type region are disposed within the buffer layer <NUM>. In an embodiment, a dopant concentration of the buffer layer <NUM> is less than the dopant concentration of the second region <NUM> and greater than the dopant concentration of the first region <NUM>. Further, the dopant concentration of the buffer layer <NUM> is lower than the dopant concentration of the second region <NUM> by an order of magnitude, and is higher than the dopant concentration of the first region <NUM> by an order of magnitude. In the embodiment shown in <FIG>, the buffer layer <NUM> is an N type buffer layer.

In the embodiment shown in <FIG>, a dopant concentration of the body region <NUM> is lower than a dopant concentration of the cathode second conductivity-type region <NUM>. Further, the dopant concentration of the body region <NUM> is lower than the dopant concentration of the cathode second conductivity-type region <NUM> by an order of magnitude.

In the embodiment shown in <FIG>, the first region <NUM> is a N- type region, the second region <NUM> is a N+ type region, the third region <NUM> is a P- type region, the fourth region <NUM> is a P+ type region, the body region <NUM> is a P type body region, the cathode first conductivity-type region <NUM> is a N+ type region, and the cathode second conductivity-type region <NUM> is a P+ type region.

<FIG> is an equivalent circuit diagram of the IGBT shown in <FIG>. The insulated gate bipolar transistor is equivalent to a transistor having a first triode PNP1 and a second triode PNP2. A collector of the first triode PNP1 includes the body region <NUM>. A base thereof includes the drift region <NUM>, the buffer layer <NUM>, and the first region <NUM>. An emitter thereof includes the fourth region <NUM>. A collector of the second triode PNP2 includes the body region <NUM>. A base thereof includes the drift region <NUM>, the buffer layer <NUM> and the second region <NUM>. An emitter thereof includes the third region <NUM>.

In the above-mentioned insulated gate bipolar transistor, the anode second conductivity-type region is divided into the lightly doped third region <NUM> and the heavily doped fourth region <NUM>, and the anode first conductivity-type region is disposed below the anode second conductivity-type region and includes the lightly doped first region <NUM> below the fourth region <NUM> and the heavily doped second region <NUM> below the third region <NUM>. Due to the introduction of the additional first region <NUM>, when the anode is implanted by holes from the fourth region <NUM>, in order to achieve a charge balance, the hole implantation efficiency of the fourth region <NUM> may increase. Due to the introduction of the additional second region <NUM> and the third region <NUM>, and since the dopant concentration of the second region <NUM> is greater than the dopant concentration of the first region <NUM>, the hole implantation efficiency of the third region <NUM> will be lower than the hole implantation efficiency of the fourth region <NUM>. The above-mentioned insulated gate bipolar transistor is equivalent to the transistor having two triodes: the first triode PNP1 formed by the fourth region <NUM>, the first region <NUM>/the buffer layer <NUM>/the drift region <NUM>, and the body region <NUM>, and the second triode PNP2 formed by the third region <NUM>, the second region <NUM>/the buffer layer <NUM>/the drift region <NUM>, and the body region <NUM>. (<NUM>) When the anode voltage is small (the device works in a linear current area), the electron current, which acts as the driving current of the bases of the two triodes, prompts holes to be implanted into the first region <NUM> and the second region <NUM> from the third region <NUM> and the fourth region <NUM> of the anode. Therefore, the implanted holes form the current of emitters the two triodes. Since the first region <NUM> is N- type, the emitter area needs to contribute more electrons. When the electron current flows to the collector, the collector area attracts more holes to be implanted. Since the implantation efficiency of the second triode PNP2 is lower than the implantation efficiency of the first triode PNP1, the anode current mainly flows through the first triode PNP1. Since the hole concentration of the first region <NUM> is low, and the hole implantation efficiency of the fourth region <NUM> is higher than the hole implantation efficiency of the conventional structure, the on-state voltage of the structure of the present disclosure is low. (<NUM>) As the anode current and voltage increase (the device works in a saturation current area), the hole implantation efficiency of the first triode PNP1 decreases, and more current flows through the second triode PNP2, and the hole implantation efficiency of the second triode PNP2 is low, such that the saturation current of the device is suppressed. As shown in <FIG>, the linear current of the structure of the present disclosure is greater than the linear current of the conventional structure, and the saturation current thereof is lower than the saturation current of the conventional structure. In summary, the above-mentioned insulated gate bipolar transistor can improve the hole implantation efficiency in the linear current area and obtain a lower on-state voltage drop, and can reduce the saturation current in the saturation current area to obtain a larger safe operating area.

In the embodiment shown in <FIG>, the insulated gate bipolar transistor further includes substrate <NUM> of the second conductivity type and a buried oxide layer BOX on the substrate <NUM>. The drift region <NUM> is disposed on the buried oxide layer BOX. Specifically, the substrate <NUM> can be a P type substrate.

In the embodiment shown in <FIG>, the insulated gate bipolar transistor further includes a field oxide layer <NUM> disposed between the body region <NUM> and the anode second conductivity-type region. Specifically, a side of the field oxide layer <NUM> can extend to an edge of the third region <NUM> and an edge of the second region <NUM>, and can cover a portion of the buffer layer <NUM>.

In the embodiment shown in <FIG>, the insulated gate bipolar transistor further includes a first polysilicon <NUM> and a second polysilicon <NUM>. The second polysilicon <NUM> is disposed on the field oxide layer <NUM>, and the first polysilicon <NUM> extends from the field oxide layer <NUM> to the cathode first conductivity-type region <NUM>. In the embodiment shown in <FIG>, a dielectric layer (not labeled in <FIG>) is disposed below a portion of the first polysilicon <NUM> located outside the field oxide layer <NUM>, that is, the dielectric layer is disposed at a region between the field oxide layer <NUM> and the cathode first conductivity-type region <NUM> and on the drift region <NUM> and the body region <NUM>. The first polysilicon <NUM> is disposed on the dielectric layer.

In the embodiment shown in <FIG>, an insulating layer <NUM> is further disposed on a surface of the insulated gate bipolar transistor. A first electrode 12a and a second electrode 13a are disposed on the insulating layer <NUM>. The first electrode 12a is electrically connected and leads to the cathode first conductivity-type region <NUM> and the cathode second conductivity-type region <NUM> through a first contact hole <NUM> which is filled with a conductive material (such as metal or alloy). The second electrode 13a is electrically connected and leads to the second polysilicon <NUM> through a contact hole <NUM>, and is electrically connected and leads to the third region <NUM> and the fourth region <NUM> through another contact hole <NUM>.

Claim 1:
An insulated gate bipolar transistor, comprising:
a drift region (<NUM>) of a first conductivity type;
a body region (<NUM>) of a second conductivity type disposed on the drift region (<NUM>);
a cathode first conductivity-type region (<NUM>) disposed within the body region (<NUM>);
a cathode second conductivity-type region (<NUM>) disposed within the body region (<NUM>);
an anode first conductivity-type region disposed on the drift region, and comprising a first region (<NUM>) and a second region (<NUM>); and
an anode second conductivity-type region disposed on the drift region, and comprising a third region (<NUM>) and a fourth region (<NUM>);
wherein a dopant concentration of the first region (<NUM>) is less than a dopant concentration of the second region (<NUM>); a dopant concentration of the third region (<NUM>) is less than a dopant concentration of the fourth region (<NUM>); the third region (<NUM>) is disposed between the fourth region (<NUM>) and the body region (<NUM>); the first region (<NUM>) is disposed below the fourth region (<NUM>); the second region (<NUM>) is disposed below the third region (<NUM>) and between the first region (<NUM>) and the body region (<NUM>); and the first conductivity type is opposite to the second conductivity type.