Patent Description:
Multi-level NAND-type flash memory ("NAND memory") may be organized into multiple cells, with each cell containing multiple bits of data and being accessible through an array of bit lines (columns) and word lines (rows). In such a case, the number of bits per cell may depend on how many distinct voltage levels can be achieved during program operation(s). For example, to support two bits per cell, four voltage levels may be called for in order to distinguish between the four possible combinations of ones and zeros (<NUM>, <NUM>, <NUM>, <NUM>). Additionally, the threshold voltage (Vt) of a given cell may be indicative of the data that is stored in the cell. As the number of different read levels increases to, for example, penta-level cell (PLC) encoding (e.g., covering thirty-two voltage levels in a 5V range), even a slight threshold voltage shift can result in the wrong level being read. Moreover, in current reading schemes, the threshold voltage of neighboring bitlines can significantly affect the apparent threshold voltage of the selected bitline. As a result, read errors may be encountered, which has a negative impact on performance.

<CIT> discloses a sensing method for a flash memory to improve read time of separate sensing in each bit line pair. The sensing method improves read time of even/odd BL separate sensing by, for example, charge time saving for sensing each of the bit lines during reading. In the method, both of the even bit line and the odd bit line are charged to a charge level. The voltage level of the odd bit line is maintained at the charge level and memory cells associated with the even bit line are sensed for reading data stored in the memory cells. The voltage level of the even bit line is discharged to ground, and the voltage level of the odd bit line is maintained at the charge level and sensed for reading data stored in the memory cells associated with the odd bit line.

<CIT> discloses a semiconductor memory device and a scrambling method which are capable of realizing a balance between a data scrambling function and an accessible time. The semiconductor memory device of the invention includes a page buffer/sense circuit with the data scrambling function. During a programming operation, the page buffer/sense circuit holds data to be programmed, performs a scrambling process on the held data and programs the scrambled data to a selected page of a memory array. During a reading operation, the page buffer/sense circuit holds data read from the selected page and performs a descrambling process on the held data.

<CIT> discloses a method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes pre-charging the bit line, setting the memory cell string in a ground voltage state, coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string, and coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.

<CIT> discloses a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into <NUM> periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period.

A memory chip controller according to the invention and a corresponding method are defined in the appended independent claims <NUM> and <NUM>.

Turning now to <FIG>, sensing circuitry <NUM> and a conventional active bitline (ABL, also referred to as all bitline) signaling scheme <NUM> is shown for a bitline (BL) that is coupled to a string <NUM> of NAND memory cells. In the illustrated example, a bitline clamp ("BLClamp") transistor <NUM> and a first pre-charge ("Pre1") transistor <NUM> are activated at time t<NUM>, which causes current to flow from Vcc through the first pre-charge transistor <NUM> and the bitline clamp transistor <NUM> and precharge the bitline. At time t<NUM>, a second pre-charge ("Pre2") transistor <NUM> and an isolation ("ISO") transistor <NUM> are activated to precharge a sensing capacitor <NUM> and continue to prechage the bitline. The second pre-charge transistor <NUM> may be deactivated at time t<NUM>, along with the application of a boost voltage to the sensing capacitor <NUM>. The operation to precharge the bitline will continue until time t<NUM> so that the BL voltage is substantially stable and the current through the BL is equal to the cell current (ICell).

In the illustrated example, the first pre-charge transistor <NUM> is deactivated at time t<NUM>, which begins a sense time period (tsense) for a comparator <NUM>. Thus, depending on the threshold voltage of the selected NAND memory cell in the string <NUM>, the cell may sink current from the sensing capacitor <NUM> during the sense time period. Additionally, if the voltage at a node <NUM> drops too low during the sense time period, the illustrated first precharge transistor <NUM> will turn on to minimize the drop in the BL voltage and coupling to neighboring bitlines. At time t<NUM>, the isolation transistor <NUM> may be deactivated and the comparator <NUM> may determine the difference between the voltage across sensing capacitor <NUM> and a reference voltage (Vref). Because the voltage across the sensing capacitor <NUM> is proportional to the amount of current sinked from the sensing capacitor <NUM>, the illustrated comparator <NUM> is able to determine whether the value of the cell is a zero or a one.

In the illustrated example, all bitlines are pre-charged simultaneously and sensing occurs at the same time on all bitlines. As will be discussed in greater detail, the threshold voltage of neighboring bitlines can significantly affect the apparent threshold voltage of the selected bitline in the illustrated solution. Indeed, as the number of different read levels increases to, for example, PLC encoding (e.g., covering thirty-two voltage levels in a 5V range), even a slight threshold voltage shift can result in the wrong level being read. As a result, read errors may be encountered, which has a negative impact on performance.

<FIG> shows a conventional solution in which a set of page buffers (PBs) <NUM> (e.g., including sensing circuitry, latches, etc.) receive a single set of pre-charge and isolation control signals that are applied to all bitlines <NUM>. By contrast, an enhanced solution <NUM> applies a first set of control signals <NUM> (38a, 38b) to even bitlines in NAND memory and a second set of control signals <NUM> (40a, 40b) to odd bitlines in the NAND memory. In an embodiment, the second set of control signals <NUM> are applied after expiration of a stagger time period ("t", representing the amount of staggering applied) between the even sensing time period and the odd sensing time period. In one example, application of the second set of control signals <NUM> after expiration of the stagger time period reduces noise in the even bitlines and the odd bitlines. The stagger time period may also significantly reduce the read time relative to shielded active bitline (ABL) sensing.

More particularly, the first set of control signals <NUM> may include an even precharge signal 38a that is shared by even pre-charge transistors and an even isolation signal 38b that is shared by even isolation transistors. In the illustrated example, the even precharge signal 38a deactivates the even pre-charge transistors (e.g., causing cell current to be sinked from even sensing capacitors) and the even isolation signal 38b deactivates the even isolation transistors after the even pre-charge transistors have been deactivated (e.g., causing the even sensing capacitors to be isolated from the memory cells). Additionally, the second set of control signals <NUM> may include an odd pre-charge signal 40a that is shared by odd pre-charge transistors and an odd isolation signal 40b that is shared by odd isolation transistors. In an embodiment, the odd pre-charge signal 40a deactivates the odd precharge transistors and the odd isolation signal 40b deactivates the odd isolation transistors after the odd pre-charge transistors have been deactivated. The illustrated enhanced solution <NUM> is advantageous relative to shielded ABL sensing because the entire signaling scheme <NUM> (<FIG>) does not need to be repeated a second time for the odd bitlines. Rather, the negligible stagger time period is inserted between the even sensing time period and the odd sensing time period.

<FIG> shows an alternative signaling approach in which an even pre-charge signal 50a of a first set of control signals <NUM> (50a, 50b) activates even pre-charge transistors at time t<NUM> before a second set of control signals <NUM> (52a, 52b) are applied to odd bitlines. The illustrated solution eliminates any mismatch that may be present between the sensing of the even bitlines and the odd bitlines. More particularly, an odd pre-charge signal 52a is high during the even sensing period <NUM> and the even pre-charge signal 50a is high during the odd sensing period <NUM>. Such an approach may further enhanced performance through more accurate read operations.

<FIG> shows a conventional set <NUM> (60a-60c) of voltage waveforms and an enhanced set <NUM> (62a-62c) of voltage waveforms. In the illustrated conventional set <NUM>, sensing-related fluctuations in a first voltage waveform 60a (corresponding to BL+<NUM>) and a third voltage waveform 60c (corresponding to BL-<NUM>) causes noise in a second voltage waveform 60b. For example, the second voltage waveform 60b fluctuates from an expected level <NUM> to an actual level <NUM>. By contrast, the enhanced set <NUM> includes a first voltage waveform 62a (corresponding to an even BL) and a third voltage waveform 62c (corresponding to an even BL) having sensing-related fluctuations that do not cause a second voltage waveform 62b to fluctuate from an expected level <NUM> during an even sensing period <NUM>. Similarly, a sensing-related fluctuation in the second voltage waveform 62b does not cause the first voltage waveform 62a or the third voltage waveform 62c to fluctuate from expected levels <NUM>, <NUM> during an odd sensing period <NUM>.

<FIG> shows a method <NUM> of operating a memory chip controller. The method <NUM> may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed-functionality hardware logic using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

Illustrated processing block <NUM> applies a first set of control signals to even bitlines in NAND memory. In an embodiment, the first set of control signals include an even pre-charge signal that is shared by even pre-charge transistors and an even isolation signal that is shared by even isolation transistors. Moreover, the even pre-charge signal may deactivate the even pre-charge transistors and the even isolation signal may deactivate the even isolation transistors after the even pre-charge transistors have been deactivated. Block <NUM> may sense voltage levels of the even bitlines during an even sensing time period.

In one example, block <NUM> applies a second set of control signals to odd bitlines in the NAND memory. In an embodiment, the second set of control signals include an odd pre-charge signal that is shared by odd pre-charge transistors and an odd isolation signal that is shared by odd isolation transistors. In such a case, the odd pre-charge signal may deactivate the odd pre-charge transistors and the odd isolation signal may deactivate the odd isolation transistors after the odd pre-charge transistors have been deactivated. Block <NUM> may sense voltage levels of the odd bitlines during an odd sensing time period. In the illustrated example, the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period. As already noted, application of the second set of control signals after expiration of the stabilization period reduces noise in the even bitlines and the odd bitlines.

Thus, the illustrated method <NUM> enhances performance at least to the extent that reduced neighboring bitline interference reduces read errors. Additionally, the even precharge signal may activate the even pre-charge transistors before the second set of control signals are applied to the odd bitlines. Such an approach eliminates any mismatch that may be present between the sensing of the even bitlines and the odd bitlines.

Turning now to <FIG>, a performance-enhanced computing system <NUM> is shown. In the illustrated example, a solid state drive (SSD) <NUM> includes a device controller apparatus <NUM> that is coupled to a NAND <NUM>. The illustrated NAND <NUM> includes a set of NVM cells <NUM> (e.g., quad-level cell/QLC, PLC) and a chip controller apparatus <NUM> that includes a substrate <NUM> (e.g., silicon, sapphire, gallium arsenide) and logic <NUM> (e.g., transistor array and other integrated circuit/IC components) coupled to the substrate <NUM>. The logic <NUM>, which may include one or more of configurable or fixed-functionality hardware, may be configured to perform one or more aspects of the method <NUM> (<FIG>), already discussed.

Thus, the logic <NUM> may apply a first set of control signals to NVM cells <NUM> (e.g., NAND memory) and sense voltage levels of the even bitlines during an even sensing time period. The logic <NUM> may also apply a second set of control signals to odd bitlines in the NVM cells <NUM>. In an embodiment, the logic <NUM> senses voltage levels of the odd bitlines during an odd sensing time period. The second set of control signals may be applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period. Although even bitlines are described herein as being read before odd bitlines for ease of discussion, the even/odd ordering may be reversed (e.g., odd bitlines may be read before even bitlines). In one example, the application of the second set of control signals after expiration of the stagger time period reduces noise in the even bitlines and the odd bitlines. The system <NUM> is therefore considered performance-enhanced at least to the extent that reduced neighboring bitline interference reduces read errors.

The illustrated system <NUM> also includes a system on chip (SoC) <NUM> having a host processor <NUM> (e.g., central processing unit/CPU) and an input/output (IO) module <NUM>. The host processor <NUM> may include an integrated memory controller <NUM> (IMC) that communicates with system memory <NUM> (e.g., RAM dual inline memory modules/DIMMs). The illustrated IO module <NUM> is coupled to the SSD <NUM> as well as other system components such as a network controller <NUM>.

In one example, the logic <NUM> includes transistor channel regions that are positioned (e.g., embedded) within the substrate <NUM>. Thus, the interface between the logic <NUM> and the substrate <NUM> may not be an abrupt junction. The logic <NUM> may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate <NUM>.

Technology described herein therefore removes noise caused by neighboring BLs and improves the accuracy of Vt read operations. For example, the total read time for each level might be ~<NUM> depending on the level and tSense may be ~<NUM>, which is negligible compared to the total read time. Thus, even though sensing on neighboring BLs is staggered, the tRead penalty is negligible compared to shielded ABL.

Embodiments are applicable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The term "coupled" may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms "first", "second", etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.

Claim 1:
A memory chip controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
apply a first set of control signals (<NUM>) to even bitlines in NAND memory, wherein the first set of control signals (<NUM>) comprise a pre-charge signal (50a) to activate or deactivate pre-charge transistors coupled to the even bitlines;
sense voltage levels of the even bitlines during an even sensing time period (<NUM>) in which the pre-charge transistors are deactivated;
apply a second set of control signals (<NUM>) to odd bitlines in the NAND memory; and
sense voltage levels of the odd bitlines during an odd sensing time period (<NUM>), wherein the second set of control signals (<NUM>) are applied after expiration of a stagger time period between the even sensing time period (<NUM>) and the odd sensing time period (<NUM>), and wherein the pre-charge transistors are activated at a time within the stagger time period.