Patent Description:
Phase-change materials are materials which can switch, under the effect of heat, between a crystalline phase and an amorphous phase, or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. Since the electric resistance of an amorphous material is significantly greater than the electric resistance of a crystalline phase of the same material, such a phenomenon is used to define two memory states, for example, <NUM> and <NUM>, differentiated by the resistance measured through the phase-change material.

As is known, phase change memory devices use phase change materials for electronic memory application. The state of the phase change materials is also non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until changed by another programming event, as that value represents a phase or physical state of the material (e.g., crystalline or amorphous). The state is unaffected by removing electrical power.

At present, alloys of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenide materials, can advantageously be used in phase change cells as phase change materials. The most promising chalcogenide is formed by a Ge, Sb and Te alloy (Ge2 Sb2 Te5 ), also called GST, which is currently widely used for storing information in overwritable disks.

In chalcogenides, the resistivity varies by two or more magnitude orders when the material passes from the amorphous phase (more resistive) to the crystalline phase (more conductive) and vice versa.

Phase change may be obtained by locally increasing the temperature. Below <NUM> all phases are stable. Above <NUM> (temperature of start of nucleation), fast nucleation of the crystallites takes place, and, if the material is kept at the crystallization temperature for a sufficient length of time, it changes its phase and becomes crystalline (so-called set state). To bring the chalcogenide back into the amorphous state (reset state), it is necessary to raise the temperature above the melting temperature (approximately <NUM>) and then to cool the chalcogenide off rapidly. Intermediate phases may be obtained applying suitable temperatures for different times, which cause the formation of amorphous "spots" or "bubbles" of different dimensions in contact with the heater.

From the electrical standpoint, it is possible to cause the chalcogenide material to change state by causing a current to flow through a resistive element, called a heater, which heats the chalcogenide material by the Joule effect.

The basic structure of a PCM element <NUM> which operates according to the principles described above is shown in <FIG> and comprises a heater element <NUM> and a memory element <NUM> of chalcogenide material. A portion of the memory element <NUM> (generally crystalline or polycrystalline) is in thermal contact with the heater <NUM> and is subject to phase change between amorphous and crystalline (i.e., the memory element <NUM> can assume a crystalline state, or an amorphous state, or even one or more intermediate states between the crystalline and the amorphous states). <FIG> shows a PCM element in an intermediate state, wherein the portion that has not changed phase and enables a good flow of current is referred to as crystalline portion <NUM> and the portion that has changed state is referred to as amorphous portion <NUM>. The dimensions of the amorphous portion <NUM> define the overall resistivity of the memory region <NUM> and thus of the PCM element <NUM>. Thus, different resistance levels may be associated with different bits and may be obtained by generating appropriate program currents that cause the amorphous portion <NUM> to assume different dimensions.

A conductive layer <NUM> (having a predefined electrical resistance, and therefore also named in the following "resistive layer") is interposed between the memory element <NUM> and the heater <NUM>, as well as between the memory element <NUM> and an insulating, or dielectric, layer <NUM>, which laterally surrounds the heater <NUM>. In other words the resistive layer <NUM> is formed and rests both on the upper surface of the dielectric layer <NUM> and on the upper surface of the heater <NUM>, the resistive layer <NUM> being in electrical contact with the heater <NUM>. The memory element <NUM> is formed and rests on the upper surface of the resistive layer <NUM>. The resistive layer <NUM> is for example made of any refractory metal and/or refractory metal nitride, such as TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), or W (tungsten).

Reference is also made to <FIG>, showing the PCM element <NUM> of <FIG> in different programming conditions, obtained using progressively higher programming currents. In <FIG>, the same reference numbers have been used as in <FIG>, while number <NUM> represents the layer of insulating or dielectric material that surrounds the heater <NUM>.

As visible in <FIG>, the amorphous portions <NUM> have different dimensions (radiuses). In detail, in <FIG>, where a lower programming current ip was used (e.g., ip = <NUM>-<NUM>µA), the phase change portion <NUM> extends just a little beyond the edge of the heater <NUM>, while in <FIG> (obtained with progressively higher programming currents ip - up to <NUM>-<NUM>µA) the protruding portion of the phase change portion <NUM> is gradually bigger.

The current path from the heater <NUM> to the crystalline portion <NUM> is influenced by the high resistive amorphous portion <NUM>; therefore the current path resistance is very high in all four conditions. Thus, the difference in resistance among the four conditions is small, compared with its absolute value.

Moreover, the programmed resistance is entirely associated to the high resistivity of the amorphized portion.

Patent <CIT> discusses a multilevel architecture for PCM. Resistance of intermediate states between two programming states (also known as SET and RESET) is (geometrically) controlled by the volume of the amorphous portion <NUM>.

During reading, the electrical current flows through two parallel paths (not shown) so as to circumvent the amorphous portion <NUM>. That is to say that a read current flows in the resistive layer <NUM> instead of the amorphous portion <NUM>. Each one of these two paths includes one respective of the two branches of the resistive layer <NUM> that extend in an opposite direction from the upper surface of the heater <NUM>, and are covered by the amorphous portion <NUM> (each branch having a resistance RL). The amorphous volume of portion <NUM> only determines the length of the resistive layer <NUM> through which the reading current flows (and so the electrical resistance seen by the current) for a certain programmed state SET / RESET.

Benefits of this approach include that temperature dependence, drift and <NUM>/f noise are drastically mitigated. However, a gap between the resistance values of the two states SET / RESET is reduced by the fact that, for every amorphous volume configuration, there exist two identical current paths in parallel (due to the symmetry of the layout of the resistive layer <NUM>). For example, by defining: the resistance in the SET state as RSET=RH; the resistance in the RESET state as RRESET=RH+RL/<NUM> (where RL/<NUM> is the equivalent resistance of the portion of the resistive layer <NUM> through which the current flows during reading of the memory element <NUM> when programmed in the RESET state).

The ratio between RRESET and RSET represents the window W, or the gap, between the resistance values of the two states SET / RESET: <MAT>.

The higher the window W, the easier the detection of the respective state SET/RESET during reading.

Documents <CIT> and <CIT> relate generally to phase-change memory cells and are aimed at improving the existing phase-change memory cells in order to reliably achieve a number of memory states higher than two.

Document <CIT> generally relates to phase change memory devices, and more particularly to phase change memory devices having a phase change region with a mushroom shape.

Document <CIT> relates to phase change memory including a heater and a resistive liner in direct contact with a sidewall of the heater.

Document <CIT> relates to a semiconductor structure including a heater surrounded by a second dielectric, a projection liner on top of the second dielectric and a phase change material above the projection liner.

However, the above-mentioned issues are not solved.

The aim of the invention is thus to provide a phase-change memory cell, a memory device including the phase-change memory cell, and a method for manufacturing the phase-change memory cell, having an improved behavior and overcoming the above-mentioned drawbacks.

According to the present invention, there are provided a phase-change memory cell, a memory device including the phase-change memory cell, and a method for manufacturing the phase-change memory cell, as defined respectively in the annexed claims.

The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:
For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:.

Like features are designated by like references in the various figures.

For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, the memory cells comprise elements which are not detailed, such as selection elements (transistors, for example) or electric connections.

<FIG> is a simplified perspective view of a memory cell <NUM>, which is part of a phase-change memory (PCM) device <NUM> (only a portion of which is represented), the phase-change memory device <NUM> comprising a plurality of memory cells <NUM>. <FIG> show the memory cell <NUM> in a triaxial system of mutually orthogonal axes X, Y, Z (Cartesian system).

Phase-change memory cells, such as memory cells <NUM> depicted in <FIG>, are typically embedded in non-volatile memory (NVM) devices such as electrically erasable programmable read-only memories (EEPROM). The programming of each memory cell in such memory devices is usually performed upon manufacturing of the memory devices and can afterwards be modified several times, particularly during their use.

The memory cells <NUM> of the memory device <NUM> are arranged in a grid-like or matrix pattern. In other words, the memory device <NUM> is composed of an array of memory cells <NUM>. Each memory cell <NUM> is located at the intersection of a row and a column of the array.

The columns, which are parallel to each other, are also referred to as "bit lines" (BL). The rows, which are parallel to each other and perpendicular to the bit lines, are also referred to as "word lines" (WL).

Each phase-change memory cell <NUM> of the memory device <NUM> comprises a heater <NUM> or resistive element. In the example of <FIG>, the heater <NUM> has an L-shaped cross-section (therefore having a vertical portion extending along the Z axis and a horizontal portion extending along the X axis). However, other shapes are possible, such as a "I" shaped cross-section (where only the vertical portion is present).

The heater <NUM> is generally surrounded by one or more insulating or dielectric layers (only one layer <NUM> is represented in <FIG>), typically composed of nitrate (e.g. SiN) and/or oxide (e.g. SiO<NUM>).

The upper surface 102c of the vertical portion of the heater <NUM> is coplanar with the upper surface 104a of the insulating layer <NUM>. As better explained later, the thickness t<NUM> along Z axis of this insulating layer <NUM> is such that, at one side 102a of the heater <NUM>, is less than the thickness t<NUM> of the insulating layer <NUM> at the opposite side 102b (along X axis) of the heater <NUM>. The thickness t<NUM> is reduced with respect to thickness t<NUM> due to the presence of an electrically conductive layer <NUM> having a resistive characteristic (in the following, also referred to as "resistive lamina <NUM>"). The resistive lamina <NUM> has a main extensions along the X, and extends (or protrudes) from side 102a of the heater <NUM> away from the heater <NUM>. The upper surface 104a' of the insulating layer <NUM> extending at the side 102a of the heater <NUM> is coplanar with the lower surface of the resistive lamina <NUM>.

Each memory cell <NUM> further comprises an own memory region <NUM>, which is separated from other memory regions <NUM> by an interposed dielectric or insulating layer. This memory region <NUM> is made of a phase-change material. The memory region <NUM> is for example made of a chalcogenide material such as an alloy that belongs at the Tellurium-based chalcogenide alloys family, in particular an alloy including germanium (Ge), antimony (Sb) and tellurium (Te). Such alloy is known as "GST". There are others chalcogenide alloys families (selenium-based and sulfur-based) that can be used for manufacturing the memory region <NUM>. In any case, the present invention is not limited to a specific material of the memory region <NUM>.

The memory region <NUM> is configured to switch between a crystalline phase (or state) and an amorphous phase (or state), and can be permanently set in one of such phases (or states). Therefore, during use the memory region <NUM> can be set in a crystalline state, or an amorphous state, or even one or more intermediate states between the crystalline state and the amorphous state.

Typically, a crystalline phase of the memory region <NUM> is native (that is to say after manufacturing/fabricating the memory cell <NUM> and before the beginning of writing/programming operations, memory region <NUM> is in a wholly crystalline state/phase). Accordingly, in the following description, the memory region <NUM> can also be referred to as "crystalline layer <NUM>".

The crystalline layer <NUM> is formed and rests both on the upper surface 104a of the insulating layer <NUM> and on the upper surface 102c of the vertical portion of the heater <NUM>. The heater <NUM> is in electrical and thermal contact with the crystalline layer <NUM> through the vertical portion of the heater <NUM>.

The heater <NUM> is, in the embodiment shown in <FIG>, centered with respect to an axis of symmetry (parallel to the Z axis and orthogonal to the X axis) of the memory cell <NUM>.

According to an aspect of the present invention, the resistive lamina <NUM>, already mentioned, is interposed between a portion of the insulating layer <NUM> and a respective portion of the crystalline layer <NUM>, laterally to the heater <NUM>. The heater <NUM> is in electrical contact with the resistive lamina <NUM>, in particular in direct electrical contact with the resistive lamina <NUM>. In particular, the resistive lamina <NUM> is laterally connected to the heater <NUM> (i.e., it is connected to the heater <NUM> at the side 102a of the heater <NUM>).

The resistive lamina <NUM> has an own upper surface that is coplanar with the upper surface 102c of the heater <NUM> (on plane XY in the drawings). In other words, the upper surface of the resistive lamina <NUM> extends as a continuation of the upper surface 102c of the heater <NUM> and lies on the same plane XY as the upper surface 102c.

A conductive metallic layer <NUM> extends on top of the crystalline layer <NUM>. This conductive layer <NUM> typically forms an electrode of the memory cell <NUM>. Conductive vias (not shown) may be provided for connecting each electrode <NUM>, e.g. to a metallization level located above the memory cells <NUM> of the memory device <NUM>.

The conductive layer <NUM> forms an electrode (to be connected to the bit line) of the memory cell <NUM>, while the heater <NUM> forms another electrode (to be connected to the word line) of the memory cell <NUM>. The two electrodes are also referred to here as a "top" electrode <NUM> and a "bottom" electrode <NUM>, though no limitation is implied as to memory cell <NUM> orientation in operation.

The heater <NUM> of the memory cell <NUM> is typically connected, by its foot 102d (that is to say a bottom surface of its horizontal portion), to a bottom contact, or pillar, <NUM>, which is of conductive material such as doped polysilicon or metal. This bottom contact <NUM> extends vertically through an insulating layer <NUM> and is connected to a substrate <NUM> that extends below the insulating layer <NUM>.

The substrate <NUM> can have a multilayer structure, for example composed of three layers: a first layer 114a made of a thin silicon film, to which the bottom contacts <NUM> are connected; a second layer 114b made of a thin buried oxide; and a third layer 114c composed of a material suitable for providing mechanical support, also called "handle substrate".

The bottom contact <NUM> of each memory cell <NUM> is connected to one terminal of a selection element <NUM>. The selection element <NUM>, often termed selector or access device, provides the ability to address/select individually each memory cell <NUM> of the memory device <NUM>.

In the example of <FIG>, the selector <NUM> is a BJT device, with an emitter terminal electrically coupled to the bottom contact <NUM>, a collector terminal electrically coupled to a common reference potential, typically a ground potential, and a base terminal that, in use, receives a bias voltage.

The crystalline phase of the memory region <NUM> corresponds, for example, to the logic value "<NUM>". Data storage inside the phase-change memory <NUM> is then carried out by writing/programming some of its memory cells <NUM>, while other of its memory cells <NUM> are left in their native state (that is to say in a crystalline state).

For writing, or programming, into a given phase-change memory cell <NUM> of memory <NUM>, this memory cell <NUM> is first selected by applying an appropriate voltage bias to the base terminal of the BJT. An electrical current then flows through the crystalline layer <NUM>. The electrical potential or the intensity of this electric current is tuned so as to sufficiently increase the temperature of the heater <NUM> to heat, by Joule heating, an area of the crystalline layer <NUM> in contact with the upper end 102c of the heater <NUM>. This causes at least part of the phase-change material to melt. When the potential pulse is abrupt, the electric current flow rapidly ends and, consequently, the local temperature of the phase-change material rapidly decreases, quenching the glassy structure of the melted part of the phase-change material. As a result, the electrical pulse has transformed a part of the phase-change material from a low resistive crystalline phase to a highly resistive amorphous state. It is assumed, for example, that this amorphous state corresponds to the logic value "<NUM>".

For reading a given phase-change memory cell <NUM>, this memory cell <NUM> is first selected by applying an appropriate voltage bias to the base terminal of the BJT. A current, whose value is low enough to avoid any inadvertent phase change, is then flown through the cell <NUM> by applying an appropriate electrical potential by activating the selector element. An electrical resistance, between the electrode <NUM> and the heater <NUM>, can then be measured. This electrical resistance reflects the value "<NUM>" or "<NUM>" that was previously stored in the memory cell <NUM>.

The material of resistive lamina <NUM> may be selected as a trade-off between programming current and an ability to discern intermediate programming states represented by different resistance levels. The electrical resistance of the resistive lamina <NUM> is chosen according to the needs, for example about the value of the electrical resistance of the heater <NUM>, and / or less than the electrical resistance of the amorphous region of the layer <NUM>. More particularly, the resistivity value of lamina <NUM> is between the respective resistivity values of the crystalline and amorphous states of the phase change material of the crystalline layer <NUM>. The resistivity of the lamina <NUM> can be significantly lower than the resistivity of the amorphous state of the phase change material. For example, resistivity of lamina <NUM> can be between about <NUM>/<NUM> times and <NUM>/<NUM> times the resistivity of the amorphous state of the phase change material of layer <NUM>. At the same time, the resistivity of the lamina <NUM> is higher than the resistivity of the crystalline state of the phase change material. In an embodiment, lamina <NUM> may be selected to have a resistivity in the range of about 1mΩ·cm - <NUM>. Example materials that may be utilized for lamina <NUM> may include, but are not limited to, carbon (C) and metallic compounds such as TiSiN, TiAlN, and SiC. Other materials traditionally used for resistors in the integrated circuit industry can also be employed. For example, the resistive lamina <NUM> can also be made of any refractory metal and/or refractory metal nitride, such as TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), or W (tungsten).

The resistive lamina <NUM> has a thickness, along the Z axis, lower than <NUM>, preferably comprised between <NUM> and <NUM>, most preferably of <NUM>-<NUM>.

According to the present invention, the resistive lamina <NUM> has an extension t<NUM>, along the X axis in the cross section view of <FIG>, which is greater at one side of the heater <NUM> with respect to the opposite side of the heater <NUM>.

In particular, in the embodiment of <FIG>, the resistive lamina <NUM> extends only at the side 102a of the heater <NUM> (the right-hand side in the <FIG>), in electrical contact with the heater <NUM> at the side 102a (in particular, in direct electrical contact). At the opposite side 102b of the heater <NUM> (the left-hand side in the <FIG>), the resistive lamina <NUM> is absent.

According to a further embodiment, illustrated in <FIG>, the resistive lamina <NUM> also extends at the second side 102b of the heater <NUM>, and is in electrical contact with the heater <NUM> at both sides 102a and 102b (in particular, in direct electrical contact). In any case, as said above, a length t<NUM> (along X axis) of the portion of the resistive lamina <NUM> at the second side 102b of the heater <NUM> is less than the length t<NUM> (along X axis) of the portion of the resistive lamina <NUM> at the first side 102a of the heater <NUM>. In particular, the length t<NUM> corresponds, along the X axis and at the side 102a of the heater <NUM>, to the whole length of the crystalline layer <NUM> extending at the side 102a (i.e. the length of the layer <NUM> measured along X axis starting from side 102a until the end of the layer <NUM> of the memory cell <NUM> considered). The length t<NUM> corresponds, along the X axis and at the side 102b of the heater <NUM>, to a fraction of the length of the crystalline layer <NUM> extending at the side 102b (i.e. the length of the layer <NUM> measured along X axis starting from side 102b until the end of the layer <NUM> of the memory cell <NUM> considered).

In a further embodiment, shown in <FIG>, the resistive lamina <NUM> is integral with the heater <NUM> and extends with continuity from the heater <NUM>, in particular from side 102a of the heater <NUM>. Therefore, in this embodiment, the resistive lamina <NUM> is of the same material of the heater <NUM> and is formed during the same step of forming the heater <NUM>.

As discussed with reference to <FIG>, also in the embodiment of <FIG> the resistive lamina <NUM> has an extension t<NUM>, along the X axis in the cross section view of <FIG>, which is greater on one side (here, side 102a) of the heater <NUM> with respect to the opposite side (here, side 102b) of the heater <NUM>. In particular, in the embodiment of <FIG>, the resistive lamina <NUM> is present only at the side 102a and is absent at the side 102b.

In the embodiment of <FIG>, which is based on the embodiment of <FIG>, the resistive lamina <NUM> is integral with the heater <NUM> and also extends at the side 102b of the heater <NUM>. The length t<NUM> of the portion of the resistive lamina <NUM> at the side 102b is less than the length t<NUM> (along X axis) of the portion of the resistive lamina <NUM> at the first side 102a.

As shown in <FIG>, according to a further embodiment of the present invention, the heater <NUM> (in particular the vertical portion of the heater <NUM>) is not centered with respect to the axis of symmetry of the memory cell <NUM> (represented in <FIG> and identified as SZ) , but staggered, or offset, with respect to such axis of symmetry; in other words, the heater <NUM> and the pillar <NUM> are shifted either to the left-hand side or to the right-hand side with respect to the axis of symmetry SZ. Even though <FIG> shows the case where the resistive lamina <NUM> is not integral with the heater <NUM> (embodiments of <FIG>), the teaching of <FIG> applies to the embodiment in which the resistive lamina <NUM> is integral with the heater <NUM> (as in <FIG>).

Furthermore, also in the embodiment of <FIG> the resistive lamina <NUM> has an extension, along the X axis in cross section view, which is greater on side 102a of the heater <NUM> with respect to the opposite side 102b of the heater <NUM>. In particular, the resistive lamina <NUM> may be present only at the side 102a and be absent at the second side 102b; or the resistive lamina <NUM> also extends at the second side 102b of the heater <NUM>, wherein the length of the portion of the resistive lamina <NUM> at the second side 102b is less than the length (along X axis) of the portion of the resistive lamina <NUM> at the first side 102a.

As shown in <FIG>, according to a further embodiment of the present invention, the selector <NUM> is a MOSFET device, having one conduction terminal (source or drain) electrically coupled to the bottom contact <NUM>, the opposite conduction terminal (drain or source) electrically coupled to a common reference potential, typically a ground potential, and the gate that, in use, receives a bias voltage. According to its value, this bias voltage allows to enable or disable a current flow through the selector. In the example of <FIG>, the select transistors of memory cells <NUM> belonging to a given word line or row share the same gate. In the memory device, the gates extend longitudinally along the WL direction (to the front and to the back, in <FIG>). All the select transistors of memory cells of a given word line are consequently connected to a same gate. Both the conductive layers <NUM> and the gates hence form a matrix or grid-like pattern, in which each intersection is roughly vertically aligned with a memory cell <NUM>.

When MOSFET devices are used as selector devices, dummy heaters (not shown) may be implemented to account for dimensions and electrical connections of the gates.

<FIG> is based on <FIG>; however, a MOSFET as selector device <NUM> can be implemented to the embodiments of <FIG> as well.

<FIG> show respective embodiments where the resistive lamina <NUM> has a greater length (along the X axis) at the right-hand side 102a of the heater <NUM> with respect to the left-hand side 102b (where the lamina <NUM> can even be absent). However, the teaching of the present description applies analogously to embodiments (not shown) where the resistive lamina <NUM> extends only from the left-hand side 102b of the heater <NUM>, or has a greater length (along the X axis) from the left-hand side 102b of the heater <NUM> with respect to the right-hand side 102a. Analogously, a memory device <NUM> may comprise a plurality of memory cells <NUM>, wherein one or more (but not all) of such memory cells <NUM> include one respective resistive lamina <NUM> extending only from the right-hand side 102a of the respective heater <NUM>, or have a greater length (along the X axis) from the right-hand side 102a of the heater <NUM> with respect to the left-hand side 102b; the remaining one or more memory cells <NUM> of such memory device <NUM> extend only from the left-hand side 102b of the heater <NUM>, or have a greater length (along the X axis) from the left-hand side 102b of the heater <NUM> with respect to the right-hand side 102a. See for example <FIG>, where a portion of a device <NUM> is shown, including some heaters <NUM> with a respective resistive lamina <NUM> extending from the right-hand side 102a and other heaters <NUM> with a respective resistive lamina <NUM> extending from the left-hand side 102b of the heater <NUM>.

Writing operations are discussed with reference to <FIG>, where only a portion of the phase-change memory <NUM> of <FIG> is shown (in particular, a detail of the phase-change cell <NUM>). For writing in the memory cell <NUM>, a voltage is applied between the top electrode <NUM> (conductive layer) and the bottom electrode, or heater <NUM>. This voltage gives rise to an electric current flowing through the layer <NUM>, which is initially wholly made of the crystalline phase. The memory cell <NUM> is thus heated, by the heater <NUM>, up to a temperature sufficient to amorphize at least part 105a of the crystalline layer <NUM>.

In the view of <FIG>, Joule heating due to the electric current flowing through the memory cell <NUM> makes a bigger part 105b of the layer <NUM> change phase, thereby forming a greater amorphous region above the upper surface 102c of the heater <NUM>. The amorphous region forms a dome which is vertically aligned with the upper surface 102c of the vertical portion of the heater <NUM>.

In the view of <FIG>, increased heating, obtained with proper increased electric current flowing through the memory cell <NUM>, makes a still bigger part 105c of the layer <NUM> change phase, thereby forming a still greater amorphous region above the upper surface 102c of the heater <NUM>. The process during which crystalline GST is turned into amorphous GST can lead to a situation where the upper surface of the resistive lamina <NUM> is fully covered by amorphous GST.

In the amorphous region located directly above the heater <NUM>, the GST of which the layer <NUM> is made of has changed/switched phase, due to heating, from a crystalline phase to an amorphous state. The layout of the resistive lamina <NUM>, which in this example extends only at one side of the heater <NUM>, has no impact on the formation of the amorphous regions 105a-105c. The shape and location of the amorphous region is, in fact, a function of the arrangement of the heater <NUM>. If a memory cell, like the memory cell <NUM> as depicted in <FIG>, is selected for reading and if the appropriate voltage bias is applied between the top electrode <NUM> and the bottom electrode (or heater <NUM>), the electrical reading current flows through the layer <NUM>, to reach the resistive lamina <NUM> present at one side of the heater <NUM>.

The memory cell <NUM> enables multilevel programming, as shown in <FIG>. In this case, it is assumed that the voltage, applied between the top electrode <NUM> and the bottom electrode during the writing (programming) operation, is raised in order to increase the intensity of the electric current flowing through the layer <NUM>. This results in a temperature rise inside the layer <NUM>, thus causing the phase change to carry on within the crystalline phase around the already amorphized region. More and more of the crystalline GST, contained inside the crystalline region, is therefore progressively converted into amorphous GST which results in a progressively extended amorphous region as the programming current progressively increases.

Consistently, the extent of the part of the resistive lamina <NUM> covered by the amorphous region also enlarges (as shown progressively in <FIG>) and its resistance increases, roughly proportionally to a length of the surface of the lamina <NUM> that is covered by the amorphous region. Therefore, the reading resistance of the cell <NUM> also increases.

With the above-described embodiments of the present invention, the resistive lamina <NUM> is asymmetric at least along one axis (here, the X axis). In particular, introducing an asymmetry with the resistive lamina <NUM> forces the reading current to flow only in a specific direction, namely where the resistive lamina <NUM> is present. With this solution, the window W, or gap, between the resistance values of two states SET / RESET (as well as intermediate programmed states as in a multi-states memory for multibit storage) is increased with respect to the known solutions. In particular, if the resistance in the SET state is RSET=RH, the resistance in the RESET state is RRESET=RH+RL (where RL is the resistance of the portion of the resistive lamina <NUM> through which the current flows during reading).

The ratio between RRESET and RSET that defines the window W is: <MAT> which is increased by a factor <NUM> with respect to the solution of the known art.

<FIG> show, in cross section view, steps for manufacturing the phase-change memory device <NUM>, according to one embodiment of the present invention.

With reference to <FIG>, a wafer <NUM> is provided, which has already been subject to manufacturing steps known in the art and therefore not further detailed. In particular, the wafer <NUM> includes the substrate <NUM> with selector devices <NUM> (here, BJTs), over which the insulating layer <NUM> has been formed. The insulating layer <NUM> is for example is Silicon Oxide, or other insulating or dielectric material. Through the insulating layer <NUM> a plurality of the bottom contacts, or pillars, <NUM> (of conductive material such as metal or doped polysilicon) extends. The pillars <NUM> are for example formed by etching trenches in the insulating layer <NUM> and then filling such trenches with conductive material. The bottom contacts <NUM> extends through the insulating layer <NUM> for the entire thickness of the insulating layer <NUM>.

With reference to <FIG>, a step of depositing a further insulating or dielectric layer <NUM> on the insulating layer <NUM> is carried out; the insulating layer <NUM> is, in this embodiment, of Silicon Nitride (SiN). Then a step is carried out to form (e.g. by deposition), on the insulating layer <NUM>, a resistive layer <NUM>. Here, at this step of process, the resistive layer <NUM> is a continuous strip or sheet of conductive material, extending on the entire surface of the insulating layer <NUM>. In further steps of manufacturing, described later, the resistive layer <NUM> will form the already described resistive lamina <NUM>. On the resistive layer <NUM>, a further insulating layer <NUM> is formed by depositing, for example, the same material of the insulating layer <NUM>. Therefore, the resistive layer <NUM> is actually buried between two dielectric layers. On the insulating layer <NUM>, a masking layer <NUM> is formed, for example by depositing TEOS.

Then, <FIG>, the masking layer <NUM> is patterned to form an etching mask that is used to remove selective portions of the underlying layers, i.e. of the two dielectric layers <NUM>, <NUM> and of the buried resistive layer <NUM>. This etching step removes unmasked portions of such layers until respective surface regions of the insulating layer <NUM> are exposed. In detail, the mask <NUM> and the etching step are designed so that the remaining portions of the two dielectric layers <NUM>, <NUM> and of the buried resistive layer <NUM> (masked stack <NUM>) extend in a strip-like fashion along the Y axis in top-plan view (on the XY plane) and are separated from one another along the X axis by the spaces left by the removed portions. Each one of the masked stacks <NUM> extends, along the X axis, from one pillar <NUM> to another immediately subsequent pillar <NUM>, only partially covering the surface of such two pillars. Two immediately subsequent pillars <NUM> along the X axis are partially covered by only one respective masked stacks <NUM>.

A shown in <FIG>, a step of depositing a continuous layer of resistive material <NUM> is carried out. The layer of resistive material <NUM> covers the masked stacks <NUM>, the exposed surface of the pillars <NUM> and the exposed surface of the insulating layer <NUM> between the pillars <NUM>. This layer of resistive material <NUM> will form, in subsequent steps, the plurality of heaters <NUM>. Therefore, the material of layer <NUM> as well as its thickness are chosen according to the needs and/or design requirements for the heaters <NUM>. For example, the material is TiSiN and the thickness is in the range <NUM> - <NUM>.

Then, <FIG>, an insulating layer <NUM> (e.g. of Silicon Nitride) is deposited to cover the masked stacks <NUM> and the spaces between the masked stacks <NUM>. A masked etching step is then carried out to remove selective portions of the insulating layer <NUM> above the masked stacks <NUM> and between the masked stacks <NUM>. The portion of the insulating layer <NUM> that is removed between each couple of masked stacks <NUM> has an extension d<NUM>, along the X axis, which is less than the distance d<NUM>, along the X axis, between such masked stacks <NUM>. The etching of the insulating layer <NUM> is carried out for the entire thickness of the insulating layer <NUM>, exposing respective surfaces of the underlying resistive layer <NUM>. The resistive layer <NUM> has, during the etching of the insulating layer <NUM>, the function of an etch-stop layer. Then, a further etching step is carried out to remove the portions of the exposed resistive layer <NUM> through its entire thickness. This etching step can be unmasked due to the etching selectivity of the materials of the resistive layer <NUM> and the insulating layer <NUM>.

Then, <FIG>, a further step of filling the gaps between the masked stacks <NUM> is carried out, to fill with insulating material <NUM> the openings left by the etching steps described with reference to <FIG>.

A step is then carried out to remove the mask <NUM> from each masked stack <NUM> and to remove the insulating layer <NUM>, until the resistive layer <NUM> is exposed. This step can be carried out by means of etching chemicals that selectively remove the layers <NUM> and <NUM>, or through a CMP step configured to land on the resistive layer <NUM> without damaging or excessively removing the resistive layer <NUM>.

Then, <FIG>, steps of forming the memory regions are carried out. To this end, the crystalline layer <NUM> is deposited; the crystalline layer <NUM> is of a phase-change material, in particular of a chalcogenide material, such as GST alloy. A sealing layer <NUM>, e.g. of Silicon Nitride, is deposited on the crystalline layer <NUM> and is used as a mask for the subsequent step of <FIG>.

<FIG> shows the wafer <NUM> in a cross section taken along the Y axis, to better appreciate the etching step that is used to define grid-like or matrix pattern of the memory cells <NUM>. With this step, the crystalline layer <NUM> and the underlying resistive and insulating layers <NUM>, <NUM>, are patterned along the Y axis, to form a plurality of memory regions (identified with the same reference numeral <NUM>) physically separated from one another and coupled each one to a respective resistive lamina <NUM> (layer <NUM>) and a respective heater <NUM> (which is not represented in the cross section of Figure H).

<FIG> shows the wafer <NUM> in cross section view along the XZ plane, to appreciate that each memory region <NUM> is coupled to one respective heater <NUM> and to one respective resistive lamina <NUM>, which departs from one side only of the heater <NUM>, leaving the other, opposite, side free from remains of the resistive layer <NUM>.

The manufacturing of the memory device <NUM> can then be completed by forming the conductive metallic layer <NUM> on top of the crystalline layer <NUM>, and filling the apertures with dielectric or insulating layer (s) (not shown). Proper electrical connection can then be formed. These steps are not, per se, part of the present invention and are therefore not further discussed.

Insulating layers <NUM> and <NUM> form the insulating layer <NUM> previously described.

<FIG> show steps for manufacturing a memory device <NUM> wherein the selector <NUM> is a MOSFET device (as discussed with reference to <FIG>).

Only some manufacturing steps are shown and described, since the manufacturing process is in part analogous to that of <FIG>, already discussed.

With reference to <FIG>, a wafer <NUM> is provided, already processed as described with reference to <FIG>. The masking layer <NUM> is patterned to form an etching mask that is used to remove selective portions of the underlying layers, i.e. of the two dielectric layers <NUM>, <NUM> and of the buried resistive layer <NUM>. This etching step removes unmasked portions of such layers until respective surface regions of the insulating layer <NUM> are exposed. In detail, the mask <NUM> and the etching step are designed so that the remaining portions of the two dielectric layers <NUM>, <NUM> and of the buried resistive layer <NUM> (masked stack <NUM>) extend in a strip-like fashion along the Y axis in top-plan view (on the XY plane) and are separated from one another along the X axis by the spaces left by the removed portions, as in the <FIG>. However, here, each one of the masked stacks <NUM> extends, along the X axis, from one pillar <NUM> (only partially covering the surface of such pillar <NUM>) to another immediately subsequent pillar <NUM>, fully covering the surface of such subsequent pillar <NUM>.

A shown in <FIG>, a step of depositing a continuous layer of resistive material <NUM> is carried out, analogously to <FIG>. This layer forms, in further steps, the heater <NUM>.

The steps described with reference to <FIG> are carried out analogously for manufacturing the memory device of <FIG> and therefore are not further described nor shown in detail.

After steps analogous to those described with reference to <FIG>, the embodiment of <FIG> is obtained, where dummy heaters <NUM> are present alternated, along X axis, to proper heaters <NUM> (the dummy heaters <NUM> are not working, since they are not electrically connected to pillars <NUM>).

The manufacturing of the memory device <NUM> can then be completed by forming the conductive metallic layer <NUM> on top of the crystalline layer <NUM>, and filling the apertures with dielectric or insulating layer(s) (i.e., completing the formation of insulating layer <NUM>). Proper electrical connection can then be formed. These steps are not, per se, part of the present invention and are therefore not further discussed.

<FIG> show steps for manufacturing the memory device of <FIG>, where the resistive lamina <NUM> extends from the heater <NUM> as an integral part of the heater <NUM>.

With reference to <FIG>, a wafer <NUM> is provided, which has already been subject to manufacturing steps known in the art and therefore not further detailed. In particular, the wafer <NUM> has been processed to form, in the substrate <NUM>, the selectors <NUM> (here, BJT selector devices <NUM>); over the substrate <NUM>, the insulating layer <NUM> has been formed. The insulating layer <NUM> is for example is Silicon Oxide, or other insulating or dielectric material. Through the insulating layer <NUM> a plurality of the bottom contacts, or pillars extending in respective trenches, <NUM> (of conductive material such as metal or doped polysilicon) are formed. The bottom contacts <NUM> extends through the insulating layer <NUM> for the entire thickness of the insulating layer <NUM>.

A step of depositing a further insulating or dielectric layer <NUM> on the insulating layer <NUM> is carried out; the insulating layer <NUM> is, in this embodiment, of Silicon Nitride (SiN).

Then, <FIG>, the insulating layer <NUM> is patterned (e.g. by photolitographic and etching processes). The etching step removes unmasked portions of the insulating layer <NUM> until respective surface regions of the insulating layer <NUM> are exposed. In detail, the patterning is designed so that the remaining portions of the dielectric layer <NUM> extend in a strip-like fashion along the Y axis in top-plan view (on the XY plane) and are separated from one another along the X axis by the spaces left by the removed portions. Each one of the remaining portions of the dielectric layer <NUM> extends, along the X axis, from one pillar <NUM> to another immediately subsequent pillar <NUM>, only partially covering the surface of such two pillars. Two immediately subsequent pillars <NUM> along the X axis are partially covered by only one respective remaining portion of the dielectric layer <NUM>.

As shown in <FIG>, a step of depositing a continuous layer of resistive material <NUM> is carried out. The layer of resistive material <NUM> covers the portions of the dielectric layer <NUM>, the exposed surface of the pillars <NUM> and the exposed surface of the insulating layer <NUM> between the pillars <NUM>. This layer of resistive material <NUM> will form, in subsequent steps, the plurality of heaters <NUM> as well as the resistive laminas <NUM>. Therefore, the material of layer <NUM> as well as its thickness are chosen according to the needs and/or design requirements for the heaters <NUM> and of the resistive laminas <NUM>. For example, the material is TiSiN and the thickness is in the range <NUM> - <NUM>.

Then, <FIG>, a protection layer <NUM> (e.g. of Silicon Nitride) is deposited to cover the layer of resistive material <NUM>. Then, a further step of depositing a filling layer <NUM> is carried out, filling the gaps between the portions of the dielectric layer <NUM> and covering the portions of the dielectric layer <NUM>.

A step is then carried out, <FIG>, to remove selective portions of the filling layer <NUM> above the portions of the dielectric layer <NUM>, exposing the resistive layer <NUM> resting on top of such portions of the dielectric layer <NUM>. The filling layer <NUM> remains between such portions of the dielectric layer <NUM>. This step can be carried out by means of a masked etching process (e.g., a lithographic process), or through a CMP step configured to land on the resistive layer <NUM> without damaging or excessively removing the resistive layer <NUM> on top of the portions of the dielectric layer <NUM>.

<FIG> shows the wafer <NUM> in a cross section taken along the Y axis, to better appreciate the etching step that is used to define grid-like or matrix pattern of the memory cells <NUM>. With this step, the crystalline layer <NUM> and the underlying resistive and insulating layers <NUM>, <NUM>, are patterned along the Y axis, to form a plurality of memory regions (identified with the same reference numeral <NUM>) physically separated from one another and coupled each one to a respective heater <NUM>.

<FIG> shows the wafer <NUM> along the X axis, to appreciate that each memory region <NUM> is coupled to one respective heater <NUM> and to one respective resistive lamina <NUM>, which departs from one side only of the heater <NUM> and is integral with the heater <NUM>, leaving the other, opposite, side free from remains of the resistive layer <NUM> running along the X axis.

Layers <NUM>, <NUM> and <NUM> will form, as a whole, the insulating layer <NUM> already mentioned.

The manufacturing of the memory device <NUM> can then be completed by forming the conductive metallic layer <NUM> on top of the crystalline layer <NUM>, and filling the apertures with dielectric or insulating layer(s), thus completing the formation of the insulating layer <NUM>. Proper electrical connection can then be formed. These steps are not, per se, part of the present invention and are therefore not further discussed.

<FIG> show steps for manufacturing a memory device <NUM> where the resistive lamina <NUM> extends from the heater <NUM> as an integral part of the heater <NUM>, but the selector devices <NUM> are MOSFET.

Only some manufacturing steps are shown and described, since the manufacturing process are analogous to that of <FIG>, already discussed.

With reference to <FIG>, a wafer <NUM> is provided, which has already been subject to manufacturing steps known in the art and therefore not further detailed. In particular, the wafer <NUM> includes the substrate <NUM>, over which the insulating layer <NUM> extends. The insulating layer <NUM> is for example is Silicon Oxide, or other insulating or dielectric material. Through the insulating layer <NUM> a plurality of the bottom contacts, or pillars, <NUM> (of conductive material such as metal or doped polysilicon) extends. The bottom contacts <NUM> extends through the insulating layer <NUM> for the entire thickness of the insulating layer <NUM>.

A step of depositing a further insulating or dielectric layer <NUM> on the insulating layer <NUM> is carried out; the insulating layer <NUM> is, in this embodiment, of Silicon Nitride (SiN).

Then, the insulating layer <NUM> is patterned (e.g. by photolitographic and etching processes). The etching step removes selective portions of the insulating layer <NUM> until respective surface regions of the insulating layer <NUM> are exposed. In detail, the patterning is designed so that the remaining portions of the dielectric layer <NUM> extend in a strip-like fashion along the Y axis in top-plan view (on the XY plane) and are separated from one another along the X axis by the spaces left by the removed portions. Each one of the remaining portions of the dielectric layer <NUM> extends, along the X axis, from one pillar <NUM> (only partially covering the surface of such pillar <NUM>) to another immediately subsequent pillar <NUM>, fully covering the surface of such subsequent pillar <NUM>.

A shown in <FIG>, a step of depositing a continuous layer of resistive material <NUM> is carried out. The layer of resistive material <NUM> covers the portions of the dielectric layer <NUM>, the exposed surface of the pillars <NUM> and the exposed surface of the insulating layer <NUM> between the pillars <NUM>. This layer of resistive material <NUM> will form, in subsequent steps, the plurality of heaters <NUM> as well as the resistive laminas <NUM>. Therefore, the material of layer <NUM> as well as its thickness are chosen according to the needs and/or design requirements for the heaters <NUM> and of the resistive laminas <NUM>. For example, the material is TiSiN and the thickness is in the range <NUM>-<NUM>.

Then, the manufacturing process continues analogously to what already described with reference to <FIG>.

The manufacturing of the memory device <NUM> can then be completed by forming the conductive metallic layer <NUM> on top of the crystalline layer <NUM>, and filling the apertures with dielectric or insulating layer(s). Proper electrical connection can then be formed. These steps are not, per se, part of the present invention and are therefore not further discussed.

<FIG> schematically shows an embodiment of a memory <NUM>. The memory <NUM> comprises: one or a plurality of memory devices, such as devices comprising memory cells <NUM> previously described in relation to each of the embodiments disclosed, and shown in <FIG> by a block <NUM> (NVM); a data processing unit, represented by a block <NUM> (PU), for example, a microprocessor; one or a plurality of memory devices, represented by a block <NUM> (MEM), and which may be memory devices different from those of block <NUM>; a block <NUM> (FCT) comprising other electronic functions, for example, sensors, load control circuits, etc.; and a data bus <NUM> enabling to transfer data between the different components.

The block <NUM> preferably includes a circuit for addressing the array of memory cells <NUM>.

It is possible, for the memory devices of the block <NUM>, not to be phase-change memory devices but to be RAMs, reprogrammable volatile memories (EEPROM, flash, etc.).

As an alternative, the block <NUM> may be omitted. The memory devices of the memory <NUM> are then only memory devices such as memory devices comprising memory cells <NUM>. The memory is then entirely a non-volatile memory.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art.

Claim 1:
A phase-change memory cell (<NUM>), comprising:
a heater (<NUM>) having a first lateral side (102a) and a second lateral side (102b) opposite to one another along a first axis (X), and a top side (102c) and a bottom side (102d) opposite to one another along a second axis (Z) orthogonal to the first axis (X); and
a memory region (<NUM>), of a phase-change material, electrically and thermally coupled to the top side (102c) of the heater (<NUM>),
further comprising an electrically conductive element (<NUM>) having a resistive characteristic, extending parallel to the first axis (X) at the first lateral side (102a), adjacent to and in physical contact with the first lateral side (102a) of said heater (<NUM>) and to said memory region (<NUM>),
characterized in that said electrically conductive element (<NUM>) extends within a first portion of an insulating region (<NUM>; <NUM>), below said memory region (<NUM>) and, at said first portion, physically separates the insulating region (<NUM>; <NUM>) from the memory region (<NUM>),
and in that the insulating region (<NUM>) further comprises a second portion at the second side (102b) of the heater (<NUM>), the second portion of the insulating region (<NUM>) being at least in part in direct contact with said memory region (<NUM>).