Patent Description:
Document <CIT> discloses an interlinked system for carrying out a method for producing a power electronic switching device with the following method steps: Providing a substrate with an insulating material body with conductor tracks, with a power semiconductor component being arranged on the first conductor track and this being electrically conductively connected to the second conductor track with an internal connecting device; applying a dam of a first material to an edge region of a first major surface of the substrate, thereby forming a filling region of the substrate surrounded by the dam; introducing a light-induced crosslinking second material into the filling area; initiation of the crosslinking of the second material by irradiation with UV light by means of a UV exposure device having a plurality of UV LEDs; waiting for a waiting period; rotation of the switching device perpendicular to its normal direction; Arrangement of the switching device in a housing or partial housing.

Power semiconductor module arrangements often include a substrate within a housing. The substrate usually comprises a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer and, optionally, a second metallization layer deposited on a second side of the substrate layer. A semiconductor arrangement including one or more controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) may be arranged on the substrate. One or more terminal elements (contact elements), which allow for contacting such a semiconductor arrangement from outside the housing, are usually provided. Power semiconductor modules are known, where the terminal elements are arranged on the substrate and protrude in a direction that is essentially perpendicular to the main surface of the substrate through a cover of the housing. The section of the contact elements which protrudes out of the housing may be mechanically and electrically coupled to a printed circuit board. The housing may be glued to the substrate in order to remain in a desired position until the substrate is permanently attached to a base plate or heat sink by means of additional connecting elements. Gluing the housing to the substrate, however, requires additional pretreatment steps (e.g., a plasma treatment of the substrate), a step in which the glue is applied to the substrate, as well as a hardening step in which the originally viscous glue is hardened, thereby attaching the housing to the substrate. Each additional step during the assembly process requires additional process time and increases the overall cost of the power semiconductor module arrangement.

There is a need for a power semiconductor module arrangement that may be assembled in an effective and cost-efficient way.

In the following detailed description, reference is made to the accompanying drawings. The drawings show specific examples in which the invention may be practiced. It is to be understood that the features and principles described with respect to the various examples may be combined with each other, unless specifically noted otherwise. In the description as well as in the claims, designations of certain elements as "first element", "second element", "third element" etc. are not to be understood as enumerative. Instead, such designations serve solely to address different "elements". That is, e.g., the existence of a "third element" does not require the existence of a "first element" and a "second element". A semiconductor body as described herein may be made from (doped) semiconductor material and may be a semiconductor chip or may be included in a semiconductor chip. A semiconductor body has electrically connecting pads and includes at least one semiconductor element with electrodes.

Referring to <FIG>, a cross-sectional view of a power semiconductor module arrangement <NUM> is illustrated. The power semiconductor module arrangement <NUM> includes a housing <NUM> and a substrate <NUM>. The substrate <NUM> includes a dielectric insulation layer <NUM>, a (structured) first metallization layer <NUM> attached to the dielectric insulation layer <NUM>, and a (structured) second metallization layer <NUM> attached to the dielectric insulation layer <NUM>. The dielectric insulation layer <NUM> is disposed between the first and second metallization layers <NUM>, <NUM>.

Each of the first and second metallization layers <NUM>, <NUM> may consist of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains solid during the operation of the power semiconductor module arrangement. The substrate <NUM> may be a ceramic substrate, that is, a substrate in which the dielectric insulation layer <NUM> is a ceramic, e.g., a thin ceramic layer. The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. Alternatively, the dielectric insulation layer <NUM> may consist of an organic compound and include one or more of the following materials: Al<NUM>O<NUM>, AIN, SiC, BeO, BN, or Si<NUM>N<NUM>. For instance, the substrate <NUM> may, e.g., be a Direct Copper Bonding (DCB) substrate, a Direct Aluminum Bonding (DAB) substrate, or an Active Metal Brazing (AMB) substrate. Further, the substrate <NUM> may be an Insulated Metal Substrate (IMS). An Insulated Metal Substrate generally comprises a dielectric insulation layer <NUM> comprising (filled) materials such as epoxy resin or polyimide, for example. The material of the dielectric insulation layer <NUM> may be filled with ceramic particles, for example. Such particles may comprise, e.g., SiO<NUM>, Al<NUM>O<NUM>, AIN, SiN or BN and may have a diameter of between about <NUM> and about <NUM>. The substrate <NUM> may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulation layer <NUM>. For instance, a non-ceramic dielectric insulation layer <NUM> may consist of or include a cured resin.

The substrate <NUM> is arranged in a housing <NUM>. In the example illustrated in <FIG>, the substrate <NUM> forms a base surface of the housing <NUM>, while the housing <NUM> itself solely comprises sidewalls and, optionally, a cover. In some power semiconductor module arrangements <NUM>, more than one substrate <NUM> is arranged within the same housing <NUM>.

One or more semiconductor bodies <NUM> may be arranged on the at least one substrate <NUM>. Each of the semiconductor bodies <NUM> arranged on the at least one substrate <NUM> may include a diode, an IGBT (Insulated-Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High-Electron-Mobility Transistor), or any other suitable semiconductor element.

The one or more semiconductor bodies <NUM> may form a semiconductor arrangement on the substrate <NUM>. In <FIG>, only two semiconductor bodies <NUM> are exemplarily illustrated. The second metallization layer <NUM> of the substrate <NUM> in <FIG> is a continuous layer. According to another example, the second metallization layer <NUM> may be a structured layer. According to other examples, the second metallization layer <NUM> may be omitted altogether. The first metallization layer <NUM> is a structured layer in the example illustrated in <FIG>. "Structured layer" in this context means that the respective metallization layer is not a continuous layer, but includes recesses between different sections of the layer. Such recesses are schematically illustrated in <FIG>. The first metallization layer <NUM> in this example includes three different sections. Different semiconductor bodies <NUM> may be mounted to the same or to different sections of the first metallization layer <NUM>. Different sections of the first metallization layer may have no electrical connection or may be electrically connected to one or more other sections using electrical connections <NUM> such as, e.g., bonding wires. Semiconductor bodies <NUM> may be electrically connected to each other or to the first metallization layer <NUM> using electrical connections <NUM>, for example. Electrical connections <NUM>, instead of bonding wires, may also include bonding ribbons, connection plates or conductor rails, for example, to name just a few examples. The one or more semiconductor bodies <NUM> may be electrically and mechanically connected to the substrate <NUM> by an electrically conductive connection layer <NUM>. Such an electrically conductive connection layer <NUM> may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver (Ag) powder, for example.

The power semiconductor module arrangement <NUM> illustrated in <FIG> further includes terminal elements <NUM>. The terminal elements <NUM> are mechanically and electrically connected to the substrate <NUM> (e.g., to the first metallization layer <NUM>) and provide an electrical connection between the inside and the outside of the housing <NUM>. The terminal elements <NUM> may be mechanically and electrically connected to the first metallization layer <NUM> with a first end <NUM>, while a second end <NUM> of the terminal elements <NUM> protrudes out of the housing <NUM>. The terminal elements <NUM> may be electrically contacted from the outside at their second end <NUM>. The housing <NUM> may optionally be provided with a cover comprising a plurality of through holes <NUM> through which each of the plurality of terminal elements <NUM> vertically protrudes.

In addition to or instead of the terminal elements <NUM> described with respect to <FIG>, the components inside the housing <NUM> may also be electrically contacted from outside the housing <NUM> in any other suitable way. For example, additional terminal elements <NUM> may be arranged closer to or adjacent to the sidewalls of the housing <NUM>. It is also possible that terminal elements <NUM> protrude vertically or horizontally through the sidewalls of the housing <NUM>. The first end <NUM> of a terminal element <NUM> may be electrically and mechanically connected to the substrate <NUM> by an electrically conductive connection layer, for example (not explicitly illustrated in <FIG>). Such an electrically conductive connection layer may be a solder layer, a layer of an electrically conductive adhesive, or a layer of a sintered metal powder, e.g., a sintered silver (Ag) powder, for example. The first end <NUM> of a terminal element <NUM> may also be electrically coupled to the substrate <NUM> via one or more electrical connections <NUM>, for example.

Power semiconductor module arrangements <NUM> further include an encapsulant <NUM>. The encapsulant <NUM> may consist of or include a silicone gel or may be a rigid molding compound, for example. The encapsulant <NUM> may at least partly fill the interior of the housing <NUM>, thereby covering the components and electrical connections that are arranged on the substrate <NUM>. The terminal elements <NUM> may be partly embedded in the encapsulant <NUM>. At least their second ends <NUM>, however, are not covered by the encapsulant <NUM> and protrude from the encapsulant <NUM> through the housing <NUM> to the outside of the housing <NUM>. The encapsulant <NUM> is configured to protect the components and electrical connections of the power semiconductor module arrangement <NUM>, in particular the components arranged on the substrate <NUM> inside the housing <NUM>, from certain environmental conditions and mechanical damage.

The housing <NUM> may be glued to the substrate <NUM> in order to remain in a desired position until the substrate <NUM> is permanently attached to a base plate or heat sink by means of additional connecting elements. In particular, the housing <NUM> may be glued to the substrate <NUM> before filling a potting material <NUM> into the housing <NUM> which, after performing a hardening step, forms the encapsulant <NUM>. The power semiconductor module arrangement <NUM> with the housing <NUM> glued to the substrate <NUM> and the encapsulant <NUM> arranged inside the housing <NUM> may then be shipped to a customer who then mounts the power semiconductor module arrangement <NUM> to a support structure such as a base plate or heat sink, for example. The power semiconductor module arrangement <NUM> may be mounted on a support structure (e.g., base plate or heat sink) by means of screws or bolts, for example, which serve to hold the substrate <NUM> in place and to force its lower surface into contact with the support structure. The glued joint between the housing <NUM> and the substrate <NUM> is therefore generally not needed to hold the housing <NUM> in its desired position with regard to the substrate <NUM> during operation of the power semiconductor module arrangement <NUM>. The main purposes of the glued joint are to prevent the potting material <NUM> forming the encapsulant <NUM> from leaking out of the housing before being sufficiently hardened and to hold the housing <NUM> in its desired position with regard to the substrate <NUM> when shipping the power semiconductor module arrangement <NUM> to an end customer. Gluing the housing <NUM> to the substrate <NUM>, however, requires additional pretreatment steps (e.g., a plasma treatment of the substrate <NUM>), a step in which the glue is applied to the substrate <NUM>, as well as a hardening step in which the originally viscous glue is hardened, thereby attaching the housing <NUM> to the substrate <NUM>. Each additional step during the assembly process requires additional process time and increases the overall cost of the power semiconductor module arrangement <NUM>.

In the following, methods for forming a power semiconductor module arrangement <NUM> according to embodiments of the disclosure will be described in which gluing the housing <NUM> to the substrate <NUM> is not required. That is, fewer steps are required for the methods described in the following, as compared to conventional methods. In this way, power semiconductor module arrangements can be assembled in a very effective and cost-efficient way. This is, because each additional step of the conventional methods requires time and adds to the overall production costs of a power semiconductor module arrangement <NUM>.

A method for forming a power semiconductor module arrangement <NUM> according to embodiments of the disclosure, falling under the scope of the claims, comprises arranging a housing <NUM> on a substrate <NUM>. The housing <NUM> may be attached to the substrate <NUM> in any suitable way without a glued joint between the sidewalls of the housing <NUM> and the substrate <NUM>. For example, the housing <NUM> may be attached to the substrate <NUM> solely by means of a mechanical connection. Such a mechanical connection may be implemented in any suitable way. The mechanical connection may be sufficient to attach the housing to the substrate <NUM> while forming the encapsulant <NUM> and when shipping the power semiconductor module arrangement <NUM> to an end customer. For example, the power semiconductor module arrangement <NUM> may comprise specific holding pins that are arranged on the substrate <NUM> and extend from the substrate <NUM> in a vertical direction y towards the cover of the housing <NUM>. The cover of the housing <NUM> may comprise holding elements (e.g., sleeves) that are configured to receive a free end of the holding pins, thereby forming a force-fitting connection. Additionally or alternatively it is also possible, for example, that one or more of the terminal elements <NUM> comprise a holding element arranged between the first end <NUM> and the second end <NUM> that is arranged inside a through hole in the cover of the housing <NUM>, wherein each holding element exerts a force on the housing, thereby holding the housing in a desired position with regard to the substrate <NUM>. Additionally or alternatively, a simple removable clamping mechanism could be used to hold the assembly together. Such mechanical connections, however, are only examples. A mechanical connection between the housing <NUM> and the substrate <NUM> may also be formed in any other suitable way.

As there is no glue between the housing <NUM> and the substrate <NUM>, the sidewalls of the housing <NUM> (i.e. the lower surfaces of the sidewalls facing the substrate <NUM>) are arranged on the substrate <NUM> to directly adjoin the substrate <NUM> (i.e. a top surface of the substrate <NUM>, wherein the top surface of the substrate <NUM> may be a top surface of the dielectric insulation layer <NUM> or a top surface of the first metallization layer <NUM>, wherein the top surface of the dielectric insulation layer <NUM> is a surface facing the first metallization layer <NUM>, and the top surface of the first metallization layer <NUM> is a surface the semiconductor bodies <NUM> and any other elements of the power semiconductor module arrangement <NUM> are mounted to). However, when mounting the housing <NUM> to the substrate <NUM> without a glued joint between the housing <NUM> and the substrate <NUM>, there is a risk that a potting material <NUM> that is filled into the housing <NUM> to form the encapsulant leaks out of the housing <NUM>. Small gaps may be present at an interface between the housing <NUM> and the substrate <NUM>. The potting material <NUM> that is filled into the housing <NUM> to form the encapsulant <NUM> is liquid, viscous or semi-liquid before it is hardened to form the encapsulant <NUM>. The potting material <NUM> at least partly fills the housing <NUM> and covers the substrate <NUM> and most components mounted thereon, as is schematically illustrated in <FIG>. As has been described above, the terminal elements <NUM>, for example, are generally not entirely covered by the potting material <NUM> and the encapsulant <NUM>, respectively. The step of filling the potting material <NUM> into the housing <NUM>, e.g., by means of a dispensing equipment <NUM>, is schematically illustrated in <FIG>. According to some embodiments of the disclosure, the dispensing equipment <NUM> may be arranged centrally above the substrate <NUM>. That is, the potting material <NUM> is dispensed centrally on the substrate <NUM> and, from there, spreads towards the edges of the substrate <NUM>.

The potting material <NUM> is a UV-curable material. UV-curable materials typically include a photoinitiator which, when exposed to UV (ultraviolet) light, initiates cross-linking of the UV-curable material <NUM>, causing it to harden. UV curable materials typically cure significantly more quickly than non-UV-curable materials. After dispensing the potting material <NUM> into the module housing <NUM> as shown in <FIG>, a UV light source <NUM> may be arranged above the module as shown in <FIG>, thereby irradiating the UV-curable potting material <NUM> inside the housing <NUM> and causing it harden rapidly. This part of the process is typically performed with no lid on top of the housing <NUM>, of course, so that the UV light is able to reach the UV-curable potting material <NUM>.

The UV-curable potting material <NUM> has a defined viscosity. The viscosity generally depends on the specific potting material <NUM> that is used to form the encapsulant <NUM>. Such materials may, for example, take the form of epoxy resins or silicone gels. A liquid, viscous or semi-liquid UV-curable potting material that is suited to form the encapsulant <NUM> may have a viscosity of at least <NUM> mPa*s, for example. Some UV-curable potting materials <NUM> may have a viscosity of <NUM> mPa*s, others may have a viscosity of <NUM> mPa*s, and some may have a viscosity of <NUM> mPa*s, for example. Any other viscosity is generally possible. The higher the viscosity of the potting material <NUM>, the lower its fluidity. Viscosity generally is the resistance of a material to a change in shape, or movement of neighboring portions relative to one another. Viscosity denotes opposition to flow. The reciprocal of the viscosity is called the fluidity, a measure of the ease of flow. A potting material <NUM> having a lower viscosity will leak out of the housing <NUM> faster than a potting material <NUM> having a higher viscosity. Generally, there may be significant leakage already within a very short timeframe, e.g., within several tens of seconds, one minute, or two minutes, for example, even when relatively fast-curing UV-curable potting materials are used.

In order to prevent the UV-curable potting material <NUM> from leaking out of the housing <NUM>, at least parts of the power semiconductor module arrangement <NUM> are irradiated with ultraviolet light, thereby triggering a cross-linking of the potting material <NUM>. In particular, a first portion of the potting material <NUM> is irradiated in areas of the potting material <NUM> near an interface between the substrate <NUM> and the sidewalls of the housing <NUM> so as to seal any gaps between the substrate <NUM> and the sidewalls of the housing <NUM>. "Near" in this respect refers to any portion of the potting material <NUM> within a radius of, e.g., up to <NUM> (millimeters), up to <NUM>, up to <NUM>, or even up to <NUM>, around the interface between the substrate <NUM> and the sidewalls of the housing <NUM>. This is schematically illustrated in <FIG>. At least an edge region (first portion indicated in dashed circles in <FIG>) of the substrate <NUM> is irradiated with ultraviolet light, such that a cross-linking of the potting material <NUM> is triggered primarily in areas of the potting material <NUM> that are closest to the sidewalls of the housing <NUM>. The areas closest to where the sidewalls of the housing <NUM> contact the substrate <NUM> are the areas where the potting material <NUM> may potentially leak out of the housing <NUM>. By starting the cross-linking process specifically in these areas, the cross-linked potting material <NUM> itself forms a barrier, seals any gaps between the substrate <NUM> and the sidewalls of the housing <NUM>, and prevents any potting material <NUM> that has not yet been cross-linked from leaking out of the housing <NUM>. The viscosity of the potting material <NUM> increases rapidly once the cross-linking has been triggered by means of the ultraviolet light. The potting material <NUM> may change from a liquid, viscous or semi-liquid state to a cured, pasty, hardened or solid state when the cross-linking takes place. The method further comprises irradiating a second portion of the potting material <NUM> farther away from the interface between the substrate <NUM> and the sidewalls of the housing <NUM> than the first portion of the potting material <NUM> to form an encapsulant <NUM>, wherein irradiation of the first and second portions of the potting material takes place at different times and/or via different radiation sources.

The encapsulant <NUM> is formed by sufficiently hardening the first and second portion of the potting material <NUM>. This may be achieved solely by irradiating the potting material <NUM> with ultraviolet light. It is, however, also possible that additional hardening steps follow an initial cross-linking process. An additional hardening process may comprise an additional irradiating step, wherein the additional irradiating step comprises irradiating the entire power semiconductor module arrangement <NUM> with ultraviolet light. It is, however, also possible that the power semiconductor module arrangement <NUM> is exposed to humidity during an additional hardening process.

Irradiating the power semiconductor module arrangement <NUM> (e.g., the first portion and/or the second portion of the potting material <NUM>) may comprise irradiating the power semiconductor module arrangement <NUM> by means of an ultraviolet light source <NUM> arranged on a side of the substrate <NUM> that faces the housing <NUM> (UV light source <NUM> arranged above the power semiconductor module arrangement <NUM> in <FIG>). In this case, it may be advantageous to first dispense only a thin layer of potting material <NUM> on the substrate <NUM>, sufficient to cover the interface between the housing <NUM> and substrate <NUM>, then to irradiate this thin layer near the edges of the substrate <NUM> to harden the potting material <NUM> and seal the interface. Then the housing <NUM> can be filled with potting material <NUM> to a final desired level before irradiating the remaining potting material to rapidly cure it. Alternatively or additionally, irradiating the power semiconductor module arrangement <NUM> (e.g., the first portion and/or the second portion of the potting material <NUM>) may comprise irradiating the power semiconductor module arrangement <NUM> by means of an ultraviolet light source <NUM> arranged on a side of the substrate <NUM> that faces away from the housing <NUM> (UV light source <NUM> arranged below the power semiconductor module arrangement <NUM> in <FIG>). It is generally possible that the entire power semiconductor module arrangement <NUM> is equally irradiated by the ultraviolet light. It is, however, generally sufficient to at least irradiate those areas that are closest to the edges of the substrate <NUM>, in order to form a barrier and seal the housing before any potting material <NUM> can leak out of the housing <NUM>. For example, at least areas within a defined distance or radius d1 from or around the edges of the substrate <NUM> may be irradiated. The defined distance d1 may be, e.g., up to <NUM>, up to <NUM> or up to <NUM>. The housing <NUM> may contact the substrate <NUM> within this defined distance d1. Once the cross-linking of the potting material <NUM> has been triggered, any gaps between the housing <NUM> and the substrate <NUM> are sealed solely by means of the resulting encapsulant <NUM> formed by cross-linking the potting material <NUM>.

A time that passes between the step of filling the potting material <NUM> into the housing <NUM> (filling the potting material <NUM> into the housing <NUM> has been completed) and the step of irradiating the first portion of the potting material <NUM> may depend on the fluidity (or viscosity) of the potting material <NUM>. That is, if the fluidity is high (viscosity is low) the time that passes between filling the potting material <NUM> into the housing <NUM> and irradiating the first portion of the potting material <NUM> may be comparably short, as the potting material <NUM> may leak out of the housing <NUM> comparably fast. If, on the other hand, the fluidity is low (viscosity is high) the time that passes between filling the potting material <NUM> into the housing <NUM> and irradiating the first portion of the potting material <NUM> may be comparably long, as the potting material <NUM> may not leak out of the housing <NUM> very fast. Generally, the time that passes between filling the potting material <NUM> into the housing <NUM> and irradiating the first portion of the potting material <NUM> may be zero seconds, up to <NUM> (seconds), up to one minute or in few cases even up to several minutes, depending on the fluidity of the respective potting material <NUM>. For example, the time that passes between filling the potting material <NUM> into the housing <NUM> and irradiating the first portion of the potting material <NUM> may be less than five minutes. However, this irradiation step generally takes significantly less time than the gluing and glue curing steps associated with conventional assembly processes, even when low fluidity gels are used.

Irradiating the exterior of the semiconductor module housing <NUM> and of the UV-curable potting material <NUM> inside the housing <NUM> takes place simultaneously. Because the volume of the material <NUM> inside the housing <NUM> is far greater than the volume of potting material <NUM> emerging at the interface between the housing <NUM> and substrate <NUM>, however, curing at the interface (first portion of potting material <NUM>) will complete more rapidly at the external locations. The semiconductor module may be irradiated by a UV light source <NUM> beneath the module and by a further UV light source <NUM> above the module, for example. Once curing is complete at the interface between the housing <NUM> and substrate <NUM>, the UV light source <NUM> beneath the module may be switched off, while the UV light source <NUM> above the housing may remain on until the UV-curable potting material <NUM> inside the housing <NUM> (second portion of potting material <NUM>) is fully cured.

The method for forming a power semiconductor module arrangement according to the embodiments described above requires less manufacturing steps than conventional methods. The method, therefore, requires less manufacturing time and is therefore very cost-effective. Any thermal stress which may arise during the step of hardening a glue that attaches the housing <NUM> to the substrate <NUM> is entirely avoided by the methods described herein. Methods for forming a power semiconductor module arrangement <NUM> comprising a housing <NUM> have been described with respect to <FIG> above. It is, however, also possible to form a power semiconductor module arrangement <NUM> without a housing <NUM> similar to what has been described above.

Now referring to <FIG>, methods for forming a power semiconductor module arrangement <NUM> without a housing <NUM> according to examples not falling under the scope of the claims will be described in more detail. The power semiconductor module arrangement <NUM> as illustrated in <FIG> comprises a substrate <NUM> with semiconductor bodies <NUM> and additional elements (e.g., terminal elements <NUM>, or electrical connections <NUM>) arranged thereon. An encapsulant <NUM> is formed on the substrate <NUM> by applying a UV-curable potting material <NUM> to the substrate <NUM>, similar to what has been described above (e.g., by means of a dispensing equipment <NUM>). According to some embodiments of the disclosure, the dispensing equipment <NUM> may be arranged centrally above the substrate <NUM>. That is, the potting material <NUM> is dispensed centrally on the substrate <NUM> and, from there, spreads towards the edges of the substrate <NUM>. The exterior sections along the edges of the substrate <NUM> are irradiated with ultraviolet light (e.g., by means of one or more ultraviolet light sources <NUM>) such that a cross-linking of the UV-curable potting material <NUM> is triggered as soon as it reaches the edges of the substrate <NUM>. In this way, a barrier or dam <NUM> is formed that extends circumferentially along the edges of the substrate <NUM> which prevents the still liquid, viscous or semi-liquid UV-curable potting material <NUM> in the central areas of the substrate <NUM> (inside the volume defined by the dam <NUM>) from flowing off the substrate <NUM>. The central areas of the substrate <NUM>, however, are not initially irradiated with ultraviolet light such that the potting material <NUM> inside the dam <NUM> can still freely flow inside the volume defined by the dam <NUM>, forming an even layer of potting material <NUM> within the dam <NUM>. The dam <NUM> may be formed to have a thickness d2 in a horizontal direction of between <NUM> and <NUM>, or between <NUM> and <NUM>, for example.

A shading tool or masking tool <NUM> may be arranged above the substrate <NUM> (e.g., on a side of the substrate <NUM> from where the potting material <NUM> is applied), in order to prevent any ultraviolet light from reaching the central area of the substrate <NUM>. One or more ultraviolet light sources <NUM> may be arranged on the same side of the substrate <NUM> as the shading or masking tool <NUM>, wherein the shading or masking tool <NUM> is arranged between the one or more light sources <NUM> and the substrate <NUM>.

When the dam <NUM> formed by the cross-linked potting material <NUM> along the edges of the substrate <NUM> has been formed and has a desired height h2 (e.g., up to several centimeters) in a vertical direction y, and the volume inside of the dam <NUM> has been filled with further UV-curable potting material <NUM>, the remaining areas of the substrate <NUM> may be irradiated with ultraviolet light, thereby triggering a cross-linking of the remaining potting material <NUM>, and forming the encapsulant <NUM>.

According to some embodiments, a housing is arranged on the substrate <NUM> once the encapsulant <NUM> has been formed. It is, however, also possible that no housing <NUM> is mounted to the substrate <NUM>. If, for example, the encapsulant <NUM> is sufficiently hard (e.g., rigid molding compound), the encapsulant <NUM> alone may be sufficient in order to protect the substrate <NUM> and the components mounted thereon from any mechanical damage and any environmental conditions.

Summarizing the above, a method for forming a power semiconductor module arrangement <NUM> according to examples not falling under the scope of the claims comprises applying a liquid, viscous or semi-liquid UV-curable potting material <NUM> to a substrate <NUM>, irradiating exterior sections along the edges of the substrate <NUM> with ultraviolet light, thereby triggering a cross-linking of the potting material <NUM> along the edges of the substrate <NUM> and forming a dam <NUM> extending circumferentially along the edges of the substrate <NUM>, filling a volume defined by the dam <NUM> with UV-curable potting material <NUM>, and, after forming the dam <NUM> and filling a volume defined by the dam <NUM> with potting material <NUM>, irradiating the volume of UV-curable potting material <NUM> with ultraviolet light, thereby triggering a cross-linking process of the remaining potting material <NUM> and forming an encapsulant <NUM> covering the substrate <NUM>.

Claim 1:
A method for forming a power semiconductor module arrangement (<NUM>), the method comprising:
arranging a housing (<NUM>) on a substrate (<NUM>), wherein the housing (<NUM>) comprises sidewalls and is arranged to directly adjoin the substrate (<NUM>) such that the substrate (<NUM>) forms a base surface of the housing (<NUM>);
filling a liquid, viscous or semi-liquid UV-curable potting material (<NUM>) into the housing (<NUM>), thereby covering the substrate (<NUM>) with the potting material (<NUM>);
irradiating, with ultraviolet light, a first portion of the potting material (<NUM>) in areas of the potting material (<NUM>) near an interface between the substrate (<NUM>) and the sidewalls of the housing (<NUM>), thereby triggering a cross-linking of the first portion of the potting material (<NUM>) so as to seal any gaps between the substrate (<NUM>) and the sidewalls of the housing (<NUM>), and
irradiating, with ultraviolet light, a second portion of the potting material (<NUM>) farther away from the interface between the substrate (<NUM>) and the sidewalls of the housing (<NUM>) than the first portion of the potting material (<NUM>), thereby triggering a cross-linking of the second portion of the potting material (<NUM>) to form an encapsulant (<NUM>), wherein:
the step of irradiating the first portion takes place before the step of irradiating the second portion of the potting material and/or the steps of irradiating the first portion and irradiating the second portion take place via different radiation sources.