Patent Description:
Silicon carbide and group III nitrides, such as gallium nitride, are desirable semiconductors for signal processing and quantum applications. These materials have wide bandgaps greater than <NUM> eV and greater nonlinear optical coefficients as compared to other material such as silicon, silica, and silicon nitride materials currently used for low-loss photonics and on-chip nonlinear optics.

Silicon carbide (SiC) is a semiconductor material containing silicon and carbon. Silicon carbide can be used in devices for quantum information processing as well as for other purposes. For example, color centers in silicon carbide structures can be used to provide an optical readout indicative of their electron spin state. Each color center is a qubit in quantum computing. A state of the qubit can be a logic "<NUM>", a logic "<NUM>", or a superposition of the two states. For example, the color centers can be incorporated in photonic devices such as micro-cavities for waveguide elements.

Fabricating devices on silicon carbide structures can be challenging. For example, the devices formed using thin-films with silicon carbide and group III nitrides can be more difficult to fabricate than desired as compared to other materials such as silicon. A thin-film device includes one or more thin-film layers in which a thin-film layer can be from fractions of a nanometer to several micrometers in thickness.

The quality of thin-film devices using silicon carbide and group III nitrides formed on a wafer may not be as great as desired as compared to materials such as silicon. For example, it would be desirable to have a method and apparatus that overcome a technical problem with forming silicon carbide and group III nitride structures having a desired quality.

An example of a device based on wide bandgap III-V semiconductor materials can be found in <CIT>, which discloses a method for manufacturing a display panel comprising light emitting device including micro LEDs. The method includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region.

According to an aspect, there is provided a method as defined in claim <NUM>. A set of group III nitride layers is formed on a silicon carbide substrate. The silicon carbide substrate includes a doped layer and a silicon carbide device layer. The doped layer has a doping level such that the doped layer is etched using a photo-electrochemical etching process and other portions of the silicon carbide substrate remain unetched. A first oxide layer is formed on the set of group III nitride layers. The set of group III nitride layers is located between the first oxide layer and the silicon carbide substrate. The first oxide layer is bonded to a second oxide layer on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate is ground. The grinding is stopped when a part of the doped layer in the silicon carbide substrate is reached exposed. The silicon carbide substrate is etched using the photo-electrochemical etching such that the doped layer is removed and a silicon carbide device layer in the silicon carbide substrate remains unetched when the part of the doped layer in the silicon carbide substrate is exposed. The semiconductor structure is formed using the silicon carbide device layer and the set of group III nitride layers.

It is possible to provide a product management system comprising fabrication equipment and a control system. The control system controls the fabrication equipment to bond a first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate to a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process. A doping level of the doped layer is such that the doped layer is removed and a silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the set of group III nitride layers.

Further details can be seen with reference to the following description and drawings.

The illustrative embodiments recognize and take into account one or more different considerations. For example, the illustrative embodiments recognize and take into account that currently used techniques can yield polycrystalline films of non-uniform silicon carbide across a wafer. Further, the illustrative embodiments recognize and take into account that when using current techniques to obtain a desired thickness for thin-film devices, material damage can occur in a silicon carbide film, thus leading to undesired optical absorption or scattering.

Further, the illustrative embodiments recognize and take into account that current techniques for fabricating silicon carbide (SiC) nano-photonics have primarily been restricted to 3C-SiC (cubic crystal structure) that is epitaxially grown on silicon (Si). The illustrative embodiments recognize and take into account that while 3C-SiC is simple to undercut on Si or silicon dioxide (SiO2) because of the chemical etch selectivity between SiC and Si/Si02, 3C-SiC devices can suffer from undesired optical losses that arise from dislocations, residual doping, high film strain, and interfacial defects at the Si-SiC growth interface.

The illustrative embodiments recognize and take into account that in order to mitigate interfacial defects, the 3C-SiC can be transferred to another substrate and a previous interface can be etched away. However, the illustrative embodiments recognize and take into account that the 3C-SiC contains a high inhomogeneous strain because of lattice mismatch with the Si substrate. In contrast to 3C-SiC films grown on Si substrates, the illustrative embodiments recognize and take into account that a single crystalline bulk and homoepitaxially grown <NUM>-SiC and <NUM>-SiC (hexagonal crystal structure) contain lower crystal strain and lower residual doping from growth. Therefore, the illustrative embodiments recognize and take into account that a <NUM>-SiC platform has great potential for photonics and other related fields. The illustrative embodiments recognize and take into account that the hexagonal SiC polytypes of silicon carbide, for example, <NUM>-, have also been pursued for photonics since the homoepitaxial growth of <NUM>-SiC on silicon carbide substrates yields crystalline material with very few lattice defects. The illustrative embodiments recognize and take into account that existing methods for isolating thin-films of <NUM>-SiC are limited given the material is grown on a bulk <NUM>-SiC substrate, such that currently used chemical etching of the base substrate is not possible.

The illustrative embodiments recognize and take into account that thin-films of hexagonal silicon carbide are suitable for photonics applications while allowing flexible pattern design and stacked layers. Thus, a method, apparatus, and system for forming structures using silicon carbide and group III nitrides can be provided, with a desired level of uniformity in film thickness while reducing damage or defects. In one illustrative example, a method forms a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer located on a carrier substrate to form an oxide layer located between a carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process, wherein a doping level of the doped layer is such that the doped layer is removed and a silicon carbide layer in the silicon carbide substrate remains unetched. The semiconductor structure can be formed using the silicon carbide layer and the set of group III nitride layers.

One or more illustrative examples enable fabricating semiconductor structures using silicon carbide as a platform to provide photonic functions. The semiconductor structures include at least one of an optical waveguide and an optical resonator. Functions of these structures include being a splitter, a directional coupler, a grating coupler, a micro-ring for a filter, a micro-disc for a filter, a non-linear optical frequency converter, a light emitter, and other types of functions. The illustrative examples enable fabricating these and other types of structures using wafer scale silicon carbide thin-films while preserving low optical loss.

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that structures and methods may be foreseen in various forms.

Further, the figures are not necessarily to scale, as some features may be exaggerated to show details of particular components. Structural and functional details disclosed herein are to be interpreted as as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure.

The processes, steps, and structures described below do not form a complete process flow for manufacturing integrated circuits. The disclosure can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as necessary for an understanding of the different examples of the present disclosure. The figures represent cross-sections of a portion of an integrated circuit during fabrication and are not drawn to scale, but instead are drawn so as to illustrate different illustrative features of the disclosure.

In the illustrative examples, processes for manufacturing semiconductor structures can utilize two or more layers of silicon carbide having different doping types. The silicon carbide layers are epitaxially grown on a base silicon carbide substrate in the form of a wafer in the illustrative example. One or more of the silicon carbide layers can be doped by implantation. The silicon carbide layers with the base silicon carbide substrate can be referred to collectively as a silicon carbide substrate. Further, a layer of epitaxial group III nitride can be grown above the top-most silicon carbide layer in the silicon carbide substrate.

Further, one or more optional layers of epitaxial group III nitride layers can be present or grown on the first group III nitride layer. Examples of group III nitride layers that can be used include, for example, aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), and other group III nitrides.

In the illustrative example, features can be at least one of patterned and etched into the group III nitride layers or deposited on the group III nitride layers. The top of this structure can be covered with a lower-refractive-index insulator such as an oxide layer formed from silicon dioxide. The oxide layer is a layer of silicon dioxide that can be deposited on a carrier substrate also in the form of a wafer. Both wafers are bonded together in the illustrative example.

In the illustrative example, an initial base silicon carbide substrate can be removed, at least partially, by grinding. In these depicted examples, the grinding can be at least one of mechanical grinding, polishing, or chemical-mechanical polishing (CMP). Mechanical grinding of the silicon carbide substrate can result in a silicon carbide layer that may have non-uniform thickness. The uniformity can become lower when the grinding is performed over distances measured in centimeters.

Afterwards, photo-electrochemical (PEC) etching can be performed to selectively remove the exposed, non-uniform silicon carbide layer until an etch-stop silicon carbide layer is reached. The photo-electrochemical etching can be performed from either a carbon-face or a silicon-face of the silicon carbide substrate in this example. A silicon carbide is a crystalline material and can have a silicon-face or a carbon-face, depending on the orientation. This silicon carbide layer functions as an etch-stop and can be at least one of semiinsulating or a different doping polarity as compared to the silicon carbide material being removed using photo-electrochemical (PEC) etching.

In the illustrative example, the resulting set of silicon carbide layers on the set of group III nitride layers can be made thinner than <NUM> and, in some cases, can be thinner than <NUM> using the techniques in the illustrative examples.

In the illustrative example, additional planarization steps can be used. For example, mechanical polishing or chemical-mechanical polishing may be performed after at least one of material growth or photo-electrochemical (PEC) etching of the silicon carbide layer substrate. These processes can be performed to reduce roughness at various interfaces.

With reference now to <FIG>, illustrations of cross-sections in a process to form a semiconductor structure are depicted in accordance with an illustrative embodiment. In <FIG>, an illustration of a cross-sectional view of a silicon carbide substrate is depicted in accordance with an illustrative embodiment. As depicted, silicon carbide (SiC) substrate <NUM> can be in the form of a wafer. For example, silicon carbide substrate <NUM> can be a hexagonal silicon carbide wafer. The silicon carbide material can be, for example, a <NUM> or <NUM> crystal polytype in this example. As depicted, in this example, the silicon carbide material has a crystalline structure that is non-centrosymmetric and polar. As depicted, the wafer can, for example, have an area of <NUM> square centimeters or greater.

In this illustrative example, silicon carbide substrate <NUM> has bond face <NUM> and etch face <NUM>. More specifically, etch face <NUM> can be either a carbon-face or a silicon-face of silicon carbide substrate <NUM>. In this example, bond face <NUM> is the surface on which additional materials for a semiconductor structure are formed.

Additionally, silicon carbide substrate <NUM> has doped layer <NUM>. The doping to form doped layer <NUM> can be performed using any currently available doping techniques including at least one of diffusion or ion implantation. Doped layer <NUM> can be a layer from about <NUM> nanometers to tens of micrometers in thickness.

In this illustrative example, doped layer <NUM> can be a p-type layer or an n-type silicon carbide layer. The doping concentration is such that doped layer <NUM> can be etched using a photo-electrochemical etching process. In this illustrative example, the doping is such that doped layer <NUM> is etched by the photo-electrochemical etching process while other portions of silicon carbide substrate <NUM> under doped layer <NUM> and in direct contact with doped layer <NUM> remain unetched.

Turning next to <FIG>, an illustration of a cross-sectional view of a set of group III nitride layers on a silicon carbide substrate is depicted in accordance with an illustrative embodiment. In the illustrative examples, the same reference numeral may be used in more than one figure. This reuse of a reference numeral in different figures represents the same element in the different figures.

As depicted, in this example, a set of group III nitride layers <NUM> are grown on bond face <NUM> of silicon carbide substrate <NUM>. The set of group III nitride layers <NUM> can be grown using currently available techniques for forming nitride layers.

As used herein, "a set of," when used with reference to items, means one or more items. For example, "a set of group III nitride layers <NUM>" is one or more of group III nitride layers <NUM>. As depicted, the set of group III nitride layers <NUM> can be thin-film layers in which each of these thin-film layers is from fractions of a nanometer to several micrometers in thickness. For example, a thin-film layer can be less than one micrometer.

In this illustrative example, the set of group III nitride layers <NUM> comprises at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium aluminum gallium nitride (InAlGaN), or other suitable group III nitrides. In this example, the set of group III nitride layers <NUM> comprises an AlN layer that is at least <NUM> nanometers thick. Additional AlN, GaN, or AlxGa<NUM>-xN layers can be optionally grown on top of this layer. These additional layers can be, for example, nanometers to several hundreds of microns thick. The number 'x' represents the Al:Ga ratio for the material's stoichiometry and 'x' can have a value between <NUM> and <NUM> in this example.

Turning next to <FIG>, an illustration of a cross-sectional view of structures formed using a set of group III nitride layers is depicted in accordance with an illustrative embodiment. As depicted, first metal <NUM> and second metal <NUM> are formed on a set of group III nitride layers <NUM>. First metal <NUM> and second metal <NUM> can be formed using currently known techniques including industry-standard lithography and deposition techniques.

Additionally, the set of group III nitride layers <NUM> can be patterned and etched using currently known techniques such as defining a hard mask, etching the group III nitride material, and removing the hard mask. In this example, the patterning in etching forms first opening <NUM> and second opening <NUM> in the set of group III nitride layers <NUM> to expose bond face <NUM>.

With reference now to <FIG>, an illustration of a cross-sectional view of silicon dioxide deposited on a silicon carbide substrate covering structures formed on a bond face of the silicon carbide substrate is depicted in accordance with an illustrative embodiment. In this illustrative example, first oxide layer <NUM> is silicon dioxide that is deposited on first metal <NUM>, second metal <NUM>, a set of group III nitride layers <NUM>, and bond face <NUM> exposed in first opening <NUM> and second opening <NUM> of the set of group III nitride layers <NUM>. The deposition of silicon dioxide to form first oxide layer <NUM> can be performed using known techniques such as plasma enhanced chemical vapor deposition, sputtering, or another suitable, known technique for forming first oxide layer <NUM>.

As depicted, first oxide layer <NUM> has first surface <NUM>. In this example, first surface <NUM> can be processed using chemical-mechanical polishing (CMP) to improve planarity and reduce surface roughness. Further, first surface <NUM> of first oxide layer <NUM> can be treated or activated to be a hydrophilic surface.

Turning now to <FIG>, an illustration of a cross-sectional view of a carrier substrate is depicted in accordance with an illustrative embodiment. In this illustrative example, carrier substrate <NUM> can take a number of different forms. For example, carrier substrate <NUM> can be one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silica substrate, an aluminum nitride substrate, a gallium nitride substrate, and other suitable substrates.

As depicted, carrier substrate <NUM> has second oxide layer <NUM> with second surface <NUM>. Second oxide layer <NUM> is comprised of silicon dioxide in this example. Second surface <NUM> can also be chemical-mechanically polished and treated or activated to be a hydrophilic surface.

In the illustrative example, silicon carbide substrate <NUM> in <FIG> and carrier substrate <NUM> in <FIG> can be bonded to each other. In this illustrative example, carrier substrate <NUM> is a substrate for the semiconductor structure. On the other hand, silicon carbide substrate <NUM> includes silicon carbide material that becomes a set of silicon carbide device layers used to form the semiconductor structure.

As depicted, first surface <NUM> of first oxide layer <NUM> on bond face <NUM> on silicon carbide substrate <NUM> in <FIG> can be placed into contact with second surface <NUM> of second oxide layer <NUM> in <FIG>. The bonding by van der Waals forces occurs through contact between first surface <NUM> of first oxide layer <NUM> and second surface <NUM> of second oxide layer <NUM>. These substrates bonded to each other through the oxide layers can be annealed. The annealing can be performed at a temperature of at least <NUM> degrees C to strengthen the bond formed between the oxide layers of these two substrates.

With reference now to <FIG>, an illustration of a cross-sectional view of a silicon carbide substrate bonded to a carrier substrate is depicted in accordance with an illustrative embodiment. In this illustrative example, bonding of silicon carbide substrate <NUM> and carrier substrate <NUM> to each other forms oxide layer <NUM>. Carrier substrate <NUM> is the substrate for the semiconductor structure that is to be formed. Oxide layer <NUM> is a dielectric layer for the semiconductor structure. In other illustrative examples, other types of dielectrics may be used to form a dielectric layer in addition to or in place of oxide layer <NUM>.

With reference now to <FIG>, an illustration of a cross-sectional view showing removal of a portion of a silicon carbide substrate is depicted in accordance with an illustrative embodiment. As depicted, silicon carbide substrate <NUM> is thinned. This thinning can occur in stages. For example, silicon carbide substrate <NUM> can be ground starting from etch face <NUM> until doped layer <NUM> in silicon carbide substrate <NUM> is reached. In this depicted example, the grinding is a mechanical grinding that removes most of silicon carbide substrate <NUM> down to doped layer <NUM>. In this illustrative example, the grinding can stop at or extend into doped layer <NUM>.

With reference now to <FIG>, an illustration of a cross-sectional view of a silicon carbide device layer is depicted in accordance with an illustrative embodiment. When doped layer <NUM> is reached, additional thinning can be performed using a photo-electrochemical (PEC) etching process. As depicted, photo-electrochemical (PEC) etching is performed on the side of silicon carbide substrate <NUM> that has etch face <NUM>, which is not performed using currently available techniques.

This process can be used to remove doped layer <NUM>. The doping is selected such that other portions of silicon carbide substrate <NUM> under doped layer <NUM> are not removed by the photo-electrochemical etching process. Thus, doped layer <NUM> in silicon carbide substrate <NUM> functions as a sacrificial layer.

The portion of silicon carbide substrate <NUM> under doped layer <NUM> remains as silicon carbide device layer <NUM>. Silicon carbide device layer <NUM> is an example of a set of silicon carbide layers. In other illustrative examples, multiple silicon carbide layers can be present for use in forming the semiconductor structure. These additional semiconductor carbide layers may have different doping levels that distinguish the layers.

In this illustrative example, silicon carbide device layer <NUM> is a thin-film layer. In this illustrative example, silicon carbide device layer <NUM> has a thickness that is from about <NUM> nanometers to several micrometers. In some illustrative examples, silicon carbide device layer <NUM> is between about <NUM> nanometers and about <NUM> nanometers. Further, processing can be performed to fabricate one or more semiconductor structures using a workpiece comprising silicon carbide device layer <NUM>, a set of group III nitride layers <NUM>, and oxide layer <NUM> on carrier substrate <NUM>.

With the use of doped layer <NUM> and the photo-electrochemical etching process, silicon carbide device layer <NUM> can have a higher level of quality as compared to other currently used techniques. For example, silicon carbide device layer <NUM> can be a polycrystalline film having a desired uniformity across a wafer. Further, silicon carbide device layer <NUM> can have reduced inconsistencies or defects that result in reducing undesired optical absorption or scattering. Further, the process in the illustrative example can result in desired epitaxial growth of a desired quality in addition to a desired level of uniformity in film thickness. For example, a thickness variation of less than <NUM> can occur across a <NUM> wafer using the steps in the illustrative example.

The illustrations of the process of forming a semiconductor structure in <FIG> are an example of one manner in which an illustrative embodiment can be implemented. The example presented in these figures is not meant to limit the manner in which other illustrative examples can be implemented. For example, in another illustrative example, at least one of the set of group III nitride layers <NUM>, first metal <NUM>, or second metal <NUM> can be omitted.

Turning next to <FIG>, illustrations of cross-sections in a process to form a semiconductor structure are depicted in accordance with an illustrative embodiment. With reference first to <FIG>, an illustration of a cross-sectional view of a substrate is depicted in accordance with an illustrative embodiment. As depicted, silicon carbide substrate <NUM> is comprised of base substrate <NUM>, doped layer <NUM>, and silicon carbide device layer <NUM>.

As depicted, base substrate <NUM> is a bulk <NUM>-SiC wafer that has a wafer normal miscut of <NUM> degrees or other small angle off-axis from the (<NUM>) crystal direction. Doped layer <NUM> is a first layer grown as an epitaxial layer of <NUM>-SiC that is doped and is a sacrificial portion of silicon carbide substrate <NUM>. In this example, <NUM>-SiC is deposited with the desired specifications of thickness and doping to form silicon carbide device layer <NUM> in silicon carbide substrate <NUM>.

Further, a set of group III nitride layers, aluminum nitride (AlN) layer <NUM> and gallium nitride (GaN) layer <NUM>, are grown on silicon carbide device layer <NUM>. In this example, aluminum nitride layer <NUM> is an undoped AlN buffer layer that is epitaxially grown. Gallium nitride layer <NUM> can be formed to desired specifications using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The doping of gallium nitride layer <NUM> can be chosen at the growth stage depending on the application.

As depicted, first oxide layer <NUM> is deposited on gallium nitride layer <NUM>. In this example, silicon dioxide (SiO2) can be deposited to form first oxide layer <NUM> using a process such as plasma-enhanced chemical vapor deposition (PECVD), sputtering, or atomic layer deposition. In this illustrative example, the growth of various layers is in the direction of arrow <NUM>. These different layers form workpiece <NUM>.

With reference now to <FIG>, an illustration of a cross-sectional view for bonding a workpiece to a carrier substrate is depicted in accordance with an illustrative embodiment. As depicted, workpiece <NUM> is flipped as compared to the view of workpiece <NUM> in <FIG>. Workpiece <NUM> can then be bonded to carrier substrate <NUM> which has second oxide layer <NUM>. In this example, bond face <NUM> and etch face <NUM> are shown. As depicted, etch face <NUM> can be a silicon-face or a carbon-face of silicon carbide substrate <NUM>.

In this illustrative example, carrier substrate <NUM> can be silicon carbide, silicon, silica, aluminum oxide, or other suitable materials. As depicted, second oxide layer <NUM> is formed using thermal oxidation, plasma enhanced chemical vapor deposition (PEVCD), sputtering, atomic level deposition, or other suitable processes.

In this illustrative example, the bonding can be performed by contact between the oxide layers. The contact is followed by annealing at a temperature of about <NUM> degrees C in this example.

In <FIG>, an illustration of a cross-sectional view of removal of a silicon carbide material from a silicon carbide substrate is depicted in accordance with an illustrative embodiment. In this figure, bonding of first oxide layer <NUM> and second oxide layer <NUM> to each other forms oxide layer <NUM>.

As depicted, silicon carbide substrate <NUM> is thinned by mechanical grinding and can be polished with chemical-mechanical polishing (CMP) as shown by section <NUM>. Section <NUM> indicates the silicon carbide material that has been removed. As shown, in this example, the removal extends into doped layer <NUM>.

In this example, mechanical polishing is used to remove a portion and not all of doped layer <NUM>. Mechanical grinding and polishing may be suitable in some cases such as over length scales from micrometers to millimeters. However, as larger length scales are present and thin-film thicknesses are desired across the entire wafer, and moreover the forces and stresses with this type of removal of material may introduce undesired inconsistencies such as lattice defects, dislocations, and crystal strain.

In this illustrative example, the mechanical grinding is stopped when the grinding extends into doped layer <NUM>. For example, the mechanical grinding can stop when doped layer <NUM> is still about a few micrometers thick.

Turning to <FIG>, an illustration of a cross-sectional view of a silicon carbide material etched to reach a silicon carbide device layer is depicted in accordance with an illustrative embodiment. As depicted, in this cross-sectional view, a photo-electrochemical etching process is used to remove the remaining portion of doped layer <NUM> as shown in section <NUM>. This etching exposes silicon carbide device layer <NUM> without removing material from silicon carbide device layer <NUM>. The dopant and doping level in doped layer <NUM> are selected such that doped layer <NUM> can be etched without removing material from silicon carbide device layer <NUM>.

With photo-electrochemical etching, dopant type selected etching can be performed in which doped layer <NUM> is removed to expose silicon carbide device layer <NUM>. In this illustrative example, silicon carbide device layer <NUM> can have desired properties such as a clean crystalline surface with a lower level of defect density as compared to using mechanical grinding.

In this illustrative example, the photo-electrochemical etching process can be performed while doped layer <NUM> is in contact with a solution such as a diluted potassium hydroxide or hydrofluoric acid and water.

Further, illumination of carrier substrate <NUM> with the different layers can be performed using the illumination with a wavelength of light corresponding to a photon energy that is above the bandgap of silicon carbide. In this depicted example, a light source contains wavelengths shorter than <NUM> for <NUM>-SiC due to its bandgap of about <NUM> eV. A voltage bias can be applied between a contact on one of the sample's doped layers and a platinum electrode in the aqueous solution. The etch selectivity of p-type, n-type, and intrinsic material can be adjusted and optimized by controlling the direct current voltage bias magnitude and direction. Since the photo-electrochemical etching involves wet chemistry and is selective depending on the doping-type, the final result of thin-films of silicon carbide and group III nitrides have a desired level of uniformity and planarity across the wafer. This result is in contrast to currently available techniques such as smart-cut, which uses ion implantation to create an amorphous layer at a defined depth. The photo-electrochemical etching in the illustrative example avoids introducing new point defects or dopants into the silicon carbide and group III nitride thin-films.

Next, <FIG> are cross-sectional views of a workpiece etched using photo-electrochemical etching in accordance with an illustrative embodiment. With reference to <FIG>, an illustration of a cross-sectional view of a workpiece is depicted in accordance with an illustrative embodiment. As depicted, workpiece <NUM> is a result of bonding a silicon carbide substrate to a carrier substrate in which a bond is formed between oxide layers on the two substrates.

In this illustrative example, workpiece <NUM> comprises silicon substrate <NUM>, which includes doped layer <NUM>, doped silicon carbide device layer <NUM>, silicon carbide device layer <NUM>, aluminum nitride (AlN) layer <NUM>, gallium nitride (GaN) layer <NUM>, oxide layer <NUM>, and carrier substrate <NUM>. In this example, doped layer <NUM> is a top layer and not located in other layers in silicon substrate <NUM> as depicted in other prior examples. Workpiece <NUM> has bond face <NUM> and etch face <NUM>. As depicted, etch face <NUM> can be a silicon-face or a carbon-face.

As depicted, doped layer <NUM> is an n-type layer. In other illustrative examples, doped layer <NUM> can be a p-type layer. The doping differentials are selected to avoid etching of doped silicon carbide device layer <NUM>. In other words, the doping level and doping type can be selected for doped silicon carbide device layer <NUM> such that this layer functions as an etch-stop for the photo-electrochemical etching process.

In this depicted example, doped layer <NUM> is a sacrificial layer that can be etched using a photo-electrochemical etching process. The doping level of doped layer <NUM> is of a sufficiently different doping type, density, or both from doped silicon carbide device layer <NUM>, which has a doping type and level to define an etch-stop. In this example, the etch selectivity can be maximized when doped layer <NUM> is doped with a concentration that is greater than <NUM>×<NUM><NUM> cm-<NUM>, and doped silicon carbide device layer <NUM> has a doping concentration of at least <NUM>×<NUM><NUM> cm-<NUM> and an opposite dopant type to that of doped layer <NUM>.

In this illustrative example, the type of dopant for doped layer <NUM> is an n-type while the type of dopant for doped silicon carbide device layer <NUM> is a p-type. If a different type of dopant is desired for doped silicon carbide device layer <NUM>, such as a p-type dopant, then the type of dopant used in doped layer <NUM> can be changed to an n-type dopant.

In another illustrative example, the sacrificial layer, doped layer <NUM>, and the etch-stop layer, doped silicon carbide device layer <NUM>, are doped to a concentration of about <NUM>×<NUM><NUM> cm-<NUM> concentration or greater. At doping levels of <NUM>×<NUM><NUM> cm-<NUM> and above, the etch rate of silicon carbide can depend on voltage bias present during the photo-electrochemical etching. The etch rate begins to vary more heavily with the doping concentration and is a factor that gives photo-electrochemical etching selectivity based on doping type.

Further, doped silicon carbide device layer <NUM> can be, for example, about <NUM> nanometers or thicker. Silicon device layers below doped silicon carbide device layer <NUM> can be any desired thickness formed from growth. For example, the thickness of these layers can be from about <NUM> nanometers to <NUM> microns thick with customizable doping concentrations. Nitride layers, such as a AlN layer and a GaN layer, can each have a thicknesses suitable for particular semiconductor devices.

In this illustrative example, a voltage bias can be applied through ohmic contacts to the surface of doped layer <NUM>. Further, the surface of the silicon carbide layer is in contact with an aqueous potassium hydroxide solution and is exposed to light that is above bandgap energy. The light can have wavelengths shorter than <NUM> nanometers in this example.

Turning to <FIG>, an illustration of a cross-sectional view of removal of a silicon carbide material is depicted in accordance with an illustrative embodiment. In this illustrative example, substrate thinning is performed by grinding and polishing to remove silicon carbide material from doped layer <NUM> as seen by section <NUM> that represents the removed silicon carbide material. This polishing can be mechanical polishing, chemical-mechanical polishing, or a combination of the two. As can be seen in this example, a portion of doped layer <NUM> remains after the grinding and chemical mechanical polishing.

In <FIG>, an illustration of a cross-sectional view of a doped layer in reach of a silicon carbide device layer is depicted in accordance with an illustrative embodiment. In this illustrative example, doped layer <NUM> is etched using a photo-electrochemical etching process to reach doped silicon carbide device layer <NUM>, which is an etch-stop layer in this example. Section <NUM> shows the removed silicon carbide material.

Thus, the processes illustrated in <FIG> enable forming silicon carbide layers for use in devices with desired properties. For example, silicon carbide device layers can be formed on a scale of the size of a wafer to have a desired level of uniformity in the thickness of the layer. Additionally, the silicon carbide device layers can be formed with reduced levels of material damage such that undesired optical absorption or scattering can be avoided. With these processes, desired quality for the silicon carbide layers using devices can be obtained on larger sizes such as a wafer as compared to current techniques.

Turning next to <FIG>, an illustration of a waveguide coupled optical resonator and filter is depicted in accordance with an illustrative example. As depicted, waveguide coupled optical resonator and filter <NUM> is a semiconductor device formed on carrier substrate <NUM> having oxide layer <NUM>, aluminum nitride layer <NUM>, and silicon carbide layer <NUM>. Carrier substrate <NUM> with oxide layer <NUM>, aluminum nitride layer <NUM>, and silicon carbide layer <NUM> can be formed using the processes illustrated in <FIG>, <FIG>, and <FIG>.

In this illustrative example, aluminum nitride layer <NUM> is in direct contact with silicon carbide layer <NUM>. In other examples, one or more other layers can be located between aluminum nitride layer <NUM> and silicon carbide layer <NUM>.

In this example, waveguide coupled optical resonator and filter <NUM> has three components. As depicted, waveguide coupled optical resonator and filter <NUM> is comprised of linear waveguide <NUM>, linear waveguide <NUM>, and ring waveguide <NUM>. In this example, waveguide coupled optical resonator and filter <NUM> can filter selected wavelengths of light. For example, light traveling through linear waveguide <NUM> can be passed into ring waveguide <NUM>. Ring waveguide <NUM> can pass a selected wavelength or selected wavelengths of light to linear waveguide <NUM>, acting as a filter as to what light is passed from linear waveguide <NUM> to linear waveguide <NUM>.

With reference to <FIG>, an illustration of a cross-sectional view of a waveguide coupled optical resonator and filter is depicted in accordance with an illustrative embodiment. In this figure, a cross-sectional view of waveguide coupled optical resonator and filter <NUM> is shown taken along line <NUM>-<NUM> in <FIG>. In this example, oxide layers are bonded to form oxide layer <NUM>. Thereafter, aluminum nitride layer <NUM> and silicon carbide layer <NUM> can be etched to form the structures that form linear waveguide <NUM>, linear waveguide <NUM>, and ring waveguide <NUM>.

With reference to <FIG>, an illustration of an integrated optical waveguide containing a quantum memory is depicted in accordance with an illustrative example. As depicted, quantum memory device <NUM> is a semiconductor device formed on carrier substrate <NUM> having oxide layer <NUM>, aluminum nitride region <NUM>, and silicon carbide region <NUM>. In this example, carrier substrate <NUM> with oxide layer <NUM>, aluminum nitride region <NUM>, and silicon carbide region <NUM> can be formed using the processes illustrated in <FIG>, <FIG>, and <FIG>.

As depicted, aluminum nitride region <NUM> has side <NUM> and side <NUM>. Silicon carbide region <NUM> has side <NUM> and side <NUM>.

In this example, quantum memory device <NUM> includes quantum memory <NUM> and integrated optical waveguide <NUM>. Quantum memory <NUM> is coupled to integrated optical waveguide <NUM>. Quantum memory <NUM> can be formed from a defect in the silicon carbide material in silicon carbide region <NUM>. The defect can be, for example, a point defect selected from a divacancy, a silicon monovacancy, other vacancy complex, a transition metal ion, or a rare earth ion in silicon carbide region <NUM>. Quantum memory <NUM> can emit photon <NUM> depending on the electron spin associated with that defect or color center, and the state of the photon can be entangled to the electron spin state. Photon <NUM> emitted from quantum memory <NUM> can travel into integrated optical waveguide <NUM>.

With reference to <FIG>, an illustration of a cross-sectional view of an integrated optical waveguide containing a quantum memory is depicted in accordance with an illustrative embodiment. In this figure, a cross-sectional view of quantum memory device <NUM> is shown taken along line <NUM>-<NUM> in <FIG>.

Turning to <FIG>, illustrations of waveguide structures fabricated are depicted in accordance with one or more illustrative embodiments. These depicted waveguide structures can be formed using the processes illustrated in <FIG>, <FIG>, and <FIG>. These waveguides also could be used instead of the optical wave-guiding structures depicted in <FIG> and <FIG> and whose cross-sections are illustrated in <FIG> and <FIG>.

With reference to <FIG>, a cross-sectional view of a waveguide is depicted in accordance with an illustrative embodiment. As illustrated, waveguide <NUM> is an example of a strip waveguide that can be formed in the illustrative examples.

In this depicted example, waveguide <NUM> is formed on carrier substrate <NUM>. Oxide layer <NUM> is located on carrier substrate <NUM>. Aluminum nitride layer <NUM> is on oxide layer <NUM>, and silicon carbide region <NUM> is located on aluminum nitride layer <NUM>. As shown in this figure, silicon carbide region <NUM> has been patterned and etched to form waveguide <NUM>.

As used herein, a region is a layer that does not extend without limit. A region has defined sides in this example. As depicted, silicon carbide region <NUM> has side <NUM> and side <NUM>.

Cladding <NUM> covers silicon carbide region <NUM> and aluminum nitride layer <NUM>. In this example, cladding <NUM> is in direct contact with silicon carbide region <NUM> and aluminum nitride layer <NUM>. Cladding <NUM> can be comprised of a material selected from at least one of an air, a vacuum, a resist, a polymer, a silicon nitride, a silicon dioxide, or some other material. In other words, cladding <NUM> can be comprised of more than one type of material in some illustrative examples. In this example, cladding <NUM> has a lower refractive index than the refractive index for silicon carbide region <NUM>.

In this illustrative example, carrier substrate <NUM> has a thickness that is from about <NUM>. Oxide layer <NUM> has a thickness of about <NUM> in this example. Aluminum nitride layer <NUM> has a thickness of about <NUM>, and silicon carbide region <NUM> has a thickness of about <NUM> and a width of about <NUM>. Cladding <NUM> has a thickness of about <NUM> to about <NUM>.

In this illustrative example, a silicon carbide layer can be etched to form silicon carbide region <NUM> while aluminum nitride layer <NUM> is not etched. This etching can be performed after bonding.

The cross-section of the structure depicted for waveguide <NUM> in <FIG> can be used to form components for a semiconductor structure. For example, silicon carbide region <NUM> can be duplicated to form four regions. The two outer regions can each be part of a linear waveguide and the two inner regions can be for a ring waveguide.

Turning next to <FIG>, another cross-sectional view of a waveguide is depicted in accordance with an illustrative embodiment. As depicted, waveguide <NUM> is an example of a rib waveguide that can be formed in the illustrative examples.

In this illustrative example, waveguide <NUM> is formed on carrier substrate <NUM>. Oxide layer <NUM> is located on carrier substrate <NUM>. Aluminum nitride layer <NUM> is on oxide layer <NUM>, and silicon carbide layer <NUM> is located on aluminum nitride layer <NUM>. Further, rib region <NUM> is a region of silicon carbide that extends from silicon carbide layer <NUM>. As shown in this figure, silicon carbide layer <NUM> has been patterned and etched to form waveguide <NUM> in the form of a rib waveguide having rib region <NUM>.

Waveguide <NUM> also has cladding <NUM> that covers silicon carbide layer <NUM> and rib region <NUM>. In this example, cladding <NUM> is in direct contact with these components. Cladding <NUM> has a refractive index that is lower than silicon carbide layer <NUM> and rib region <NUM>.

In this illustrative example, carrier substrate <NUM> has a thickness that is from about <NUM>. Oxide layer <NUM> has a thickness of about <NUM> in this example.

Aluminum nitride layer <NUM> has a thickness of about <NUM>. Silicon carbide layer <NUM> has a thickness of about <NUM>. Rib region <NUM> extending from silicon carbide layer <NUM> has a thickness of about <NUM> and a width of about <NUM>. Cladding <NUM> has a thickness of about <NUM> to about <NUM>.

In <FIG>, yet another cross-sectional view of a waveguide is depicted in accordance with an illustrative embodiment. As illustrated, waveguide <NUM> is an example of a buried ridge waveguide structure.

In this depicted example, waveguide <NUM> is formed on carrier substrate <NUM>. Oxide layer <NUM> is located on carrier substrate <NUM>. Gallium nitride region <NUM> is located on oxide layer <NUM> in cavity <NUM> in oxide layer <NUM>. Aluminum nitride region <NUM> is located on gallium nitride region <NUM> in cavity <NUM> in oxide layer <NUM>. Aluminum nitride region <NUM> and gallium nitride region <NUM> are an example of a set of group III nitride regions that may be buried in cavity <NUM>.

Regions are layers that have defined sides and can be located within another material. In this example, gallium nitride region <NUM> has side <NUM> and side <NUM> in cavity <NUM> in oxide layer <NUM>. Aluminum nitride region <NUM> has side <NUM> and side <NUM> in cavity <NUM> in oxide layer <NUM>.

In this example, silicon carbide layer <NUM> is located on oxide layer <NUM> and aluminum nitride region <NUM>. As shown in this figure, silicon carbide layer <NUM>, aluminum nitride region <NUM>, and gallium nitride region <NUM> in cavity <NUM> of oxide layer <NUM> form waveguide <NUM>. Aluminum nitride region <NUM> and gallium nitride region <NUM> form ridge <NUM> buried in oxide layer <NUM>. The refractive index of at least one of aluminum nitride region <NUM> or gallium nitride region <NUM> is higher than the refractive index of oxide layer <NUM>.

As depicted, waveguide <NUM> has cladding <NUM> that covers silicon carbide layer <NUM>. In this illustrative example, cladding <NUM> is in direct contact with silicon carbide layer <NUM>. Cladding <NUM> has a refractive index that is lower than the refractive index of silicon carbide layer <NUM>.

In this illustrative example, carrier substrate <NUM> has a thickness about <NUM>. Oxide layer <NUM> has a thickness of about <NUM> in this example. Aluminum nitride layer <NUM> has a thickness of about <NUM>, and gallium nitride layer <NUM> has a thickness of about <NUM>. These two layers in cavity <NUM> have a width of about <NUM>. As depicted, silicon carbide layer <NUM> has a thickness of about <NUM>. Cladding <NUM> has a thickness of about <NUM> to about <NUM>.

In this example, an aluminum nitride layer and a gallium nitride region are etched to form aluminum nitride region <NUM> and gallium nitride region <NUM>. A first oxide layer is formed to bury aluminum nitride region <NUM> and gallium nitride region <NUM>. This first oxide layer is then bonded to a second oxide layer on carrier substrate <NUM>. The first oxide layer and the second oxide layer can then be bonded to form oxide layer <NUM>.

In this illustrative example, the semiconductor structure depicted in <FIG> can be fabricated using operations depicted in the illustrative examples. For example, group III nitride layers can be patterned and etched before depositing oxide and wafer bonding. The waveguide structures can be integrated with lateral (horizontal) diodes and doping for active electronics and depletion layers in silicon carbide layer <NUM>. The doped regions could be fabricated either by masked implantation followed by annealing, or substrate (SiC and GaN) doping during growth followed by patterning and etching, or a combination thereof. Applying electric fields in these materials across p-n junctions or between metal contacts could be used to tune the resonance frequency of an optical resonator or optical emission frequency of embedded single photon emitters.

With reference now to <FIG>, still another cross-sectional view of a waveguide is depicted in accordance with an illustrative embodiment. As illustrated, waveguide <NUM> is another example of a buried optical waveguide structure.

In this depicted example, waveguide <NUM> is formed on carrier substrate <NUM>. Oxide layer <NUM> is located on carrier substrate <NUM>. Gallium nitride region <NUM> is located on oxide layer <NUM> in cavity <NUM> in oxide layer <NUM>. Aluminum nitride region <NUM> is located on gallium nitride region <NUM> in cavity <NUM> in oxide layer <NUM>. Aluminum nitride region <NUM> has side <NUM> and side <NUM>. Gallium nitride region <NUM> has side <NUM> and side <NUM>. As depicted, aluminum nitride region <NUM> and gallium nitride region <NUM> form ridge <NUM> that is buried in cavity <NUM> in oxide layer <NUM>.

In this example, silicon carbide layer <NUM> is located on oxide layer <NUM> and aluminum nitride region <NUM>. Further, rib region <NUM> extends from silicon carbide layer <NUM>. As shown in this figure, rib region <NUM> is a portion of silicon carbide that extends from silicon carbide layer <NUM> and can be referred to as a silicon carbide region. As depicted, silicon carbide layer <NUM>, rib region <NUM>, aluminum nitride region <NUM>, and gallium nitride region <NUM> in cavity <NUM> of oxide layer <NUM> form waveguide <NUM>.

As depicted, waveguide <NUM> has cladding <NUM> that covers silicon carbide layer <NUM> and rib region <NUM>. As depicted, cladding <NUM> is in direct contact with silicon carbide layer <NUM> and rib region <NUM>. Cladding <NUM> has a refractive index that is lower than silicon carbide layer <NUM> and rib region <NUM>.

In this illustrative example, carrier substrate <NUM> has a thickness that is from about <NUM>. Oxide layer <NUM> has a thickness of about <NUM> in this example. Aluminum nitride region <NUM> has a thickness of about <NUM>, and gallium nitride region <NUM> has a thickness of about <NUM>. These two regions in cavity <NUM> have a width of about <NUM>. As depicted, silicon carbide layer <NUM> has a thickness of about <NUM>. Rib region <NUM> has a width of about <NUM> and a thickness of about <NUM>. Cladding <NUM> has a thickness of about <NUM> to about <NUM>.

The illustrations of waveguide structures in <FIG> are provided as an example of one type of semiconductor structure that can be fabricated in accordance with one or more illustrative examples. These illustrations are not meant to limit the manner in which other illustrative examples can be implemented.

For example, the thicknesses illustrated for these layers and regions are examples of thicknesses that can be used for thin-film implementations. These thicknesses are not meant to limit the thicknesses that can be used in other illustrative examples.

Further, the number and types of group III nitride layers and regions can vary from those illustrated in <FIG>. For example, an indium nitride (InN) layer and an indium aluminum gallium nitride (InAlGaN)layer can be used in addition to or in place of the aluminum nitride (AlN) and gallium nitride (GaN) layers depicted.

As another example, other types of semiconductor structures can be fabricated in addition to or in place of waveguide structures. For example, a semiconductor structure can include at least one of a superconducting single photon detector, an optical emitter, a quantum memory using a point defect within the silicon carbide device layer, or other suitable types of components in the semiconductor structure.

Additional examples of semiconductor structures with one or more silicon carbide device layers and one or more group III nitride layers that can be fabricated using operations in one or more illustrative examples comprise micro-electromechanical systems and photonic components including waveguide-coupled four-port and two-port ring resonators or filters. In still other illustrative examples, superconducting materials can be deposited in a manner that allows for the operation of superconducting nanowire single photon detectors and logical components at cryogenic temperatures alongside the photonic, electrical, and mechanical components.

As another example, with slot waveguides, the optical mode can be selected for a lower refractive index cladding or vacuum outside the substrate by etching two ridges closely spaced together. The spacing can be, for example, less than a few hundred nanometers. As another example, suspended waveguides can be fabricated from similar material stacks as those depicted in these figures by lithographically patterning and then chemically etching away oxide (SiO2) in selective areas, which would yield an optical spatial mode that extends more into air or vacuum instead of into the oxide layer.

With reference next to <FIG>, another example of a silicon carbide substrate with a set of group III nitride layers is depicted in accordance with an illustrative embodiment. In this illustrative example, workpiece <NUM> is an example of layers that can be formed and bonded to a carrier substrate such as carrier substrate <NUM> in <FIG>.

In this example, silicon carbide substrate <NUM> in workpiece <NUM> comprises base substrate <NUM>, p-type silicon carbide layer <NUM>, n-type silicon carbide layer <NUM>, undoped silicon carbide layer <NUM>, and p-type silicon carbide layer <NUM>. As depicted, p-type silicon carbide layer <NUM> is a sacrificial layer for performing photo-electrochemical etching. The other silicon carbide layers are examples of silicon carbide device layers that can be used in forming semiconductor structures. In this example, n-type silicon carbide layer <NUM> can function as an etch-stop in addition to being a device layer.

In this illustrative example, base substrate <NUM> has a thickness of about <NUM>. As depicted, the sacrificial layer, p-type silicon carbide layer <NUM>, has a thickness of about <NUM>. In this example, n-type silicon carbide layer <NUM> has a thickness of about <NUM>; undoped silicon carbide layer <NUM> has a thickness of about <NUM>; and p-type silicon carbide layer <NUM> has a thickness of about <NUM>.

As depicted, group III nitride layers are grown on p-type silicon carbide layer <NUM> in silicon carbide substrate <NUM>. These group III nitride layers comprise undoped aluminum nitride layer <NUM> and undoped gallium nitride layer <NUM>. In this illustrative example, undoped aluminum nitride layer <NUM> has a thickness of about <NUM>, and undoped gallium nitride layer <NUM> has a thickness of about <NUM>.

In this depicted example, oxide layer <NUM> is deposited on undoped gallium nitride layer <NUM>. Oxide layer <NUM> has a thickness of about <NUM> in this example.

With workpiece <NUM>, thin-films of silicon carbide and group III nitrides can be stacked on top of a material with a lower index of refraction (n) such as SiO2 such as n being about <NUM> for SiO2, <NUM>/<NUM> for monocrystalline AlN/GaN, and <NUM> for <NUM>-SiC, respectively. As a result, optical modes in a photonic device can stay within at least one of the silicon carbide or group III nitrides layers without radiating or losing optical energy into the bulk substrate material below.

Further, the silicon carbide layers in the group III nitride layers depicted in workpiece <NUM> can be used to create a p-i-n junction within the silicon carbide material. In this example, the use of undoped aluminum nitride layer <NUM> can be beneficial and can result in fewer un-passivated interface states (especially at cryogenic temperatures) compared to an exposed surface of SiC or a direct interface between silicon carbide and an oxide. The use of one or more additional group III nitride layers are optional in the illustrative examples.

The illustration of workpiece <NUM> is provided as an example of one manner in which a silicon carbide substrate with a set of group III nitride layers can be implemented. This illustration is not meant to limit the manner in which other illustrative examples can be implemented.

For example, other illustrative examples can have other numbers of layers with the silicon carbide substrate. In some illustrative examples, the layer adjacent to the sacrificial layer can be an undoped layer rather than a layer with an opposite type of doping from the sacrificial layer. In yet another illustrative example, three, five, or some other number of group III nitride layers can be employed. Further, the example thicknesses for the layers are provided as examples of thicknesses that can be used with thin-film layers. Other thicknesses can be used in other examples.

Turning next to <FIG>, an illustration of a flowchart of a process for forming a semiconductor structure is depicted in accordance with an illustrative embodiment. The process begins by bonding a first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate to a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers (operation <NUM>). The silicon carbide substrate has a doped layer.

The process etches the silicon carbide substrate having the doped layer using a photo-electrochemical etching process (operation <NUM>). A doping level of the doped layer is such that the doped layer is removed and a silicon carbide device layer in the silicon carbide substrate remains unetched. In operation <NUM>, the doped layer is a sacrificial layer enabling forming the silicon carbide device layer on a substrate such as a wafer with at least one of a desired uniformity in a thickness of the silicon carbide device layer or a desired level of optical performance. In operation <NUM>, the photo-electrochemical etching is performed on an etch face which can be the silicon-face or, for this example, is a carbon-face of the silicon carbide material. The photo-electrochemical etching also can be performed on an etch face that is a silicon-face of the silicon carbide material.

The process forms a semiconductor structure using the silicon carbide device layer and the set of group III nitride layers (operation <NUM>). The process terminates thereafter. In this example, the silicon carbide device layer and the set of group III nitride layers can be thin-film layers. The semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, a photon emitting quantum memory using a point defect within the silicon carbide device layer, or some other suitable structure. A semiconductor structure can include multiple components. For example, the semiconductor structure can include multiple waveguides of the same type or of different types. As another example, the semiconductor structure can include one or more waveguides and a quantum memory. These and other components can be selected to provide a desired function or functions for the semiconductor structure.

With reference next to <FIG>, an illustration of a flowchart of a process for forming a semiconductor structure is depicted in accordance with an illustrative embodiment. The process begins by forming a set of group III nitride layers on a silicon carbide substrate (operation <NUM>). The silicon carbide substrate includes a doped layer. The doped layer has a doping level such that the doped layer is etched using a photo-electrochemical etching process while other portions of the silicon carbide substrate remain unetched. In other illustrative examples, forming of the set of group III nitride layers can include etching the set of group III nitride layers to form structures.

The process forms a first oxide layer on the set of group III nitride layers, wherein the set of group III nitride layers is located between the first oxide layer and the silicon carbide substrate (operation <NUM>). The process bonds the first oxide layer to a second oxide layer on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers (operation <NUM>).

The process grinds the silicon carbide substrate (operation <NUM>). The process stops the grinding when a part of the doped layer in the silicon carbide substrate is exposed (operation <NUM>). In operation <NUM>, the part of the doped exposed layer can be the top portion of the doped layer or some portion within the doped layer.

The process etches the silicon carbide substrate using photo-electrochemical etching such that the doped layer is removed and a silicon carbide device layer in the silicon carbide substrate remains when the part of the doped layer in the silicon carbide substrate is exposed (operation <NUM>).

The process forms a semiconductor structure using the silicon carbide device layer and the set of group III nitride layers (operation <NUM>). The process terminates thereafter.

Turning next to <FIG>, an illustration of bonding components is depicted in accordance with an illustrative embodiment. The flowchart in <FIG> is an example of one implementation for performing operation <NUM> in <FIG> and operation <NUM> in <FIG>.

The process begins by contacting a first surface of a first oxide layer to a second surface of a second oxide layer (operation <NUM>). In operation <NUM>, intermolecular interactions occur between the first oxide layer and the second oxide layer. These intermolecular interactions include, for example, at least one of Van der Waals forces, hydrogen bonds, or strong covalent bonds.

The process anneals the first oxide layer and the second oxide layer while the first surface is in direct contact with the second surface to form an oxide layer located between a carrier substrate and a set of group III nitride layers (operation <NUM>). In this example, annealing in operation <NUM> is optional. The process terminates thereafter.

Turning to <FIG>, an illustration of a flowchart of a process for forming a semiconductor structure is depicted in accordance with an illustrative embodiment. The process begins by bonding a first oxide layer located on a silicon carbide substrate to a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the silicon carbide substrate (operation <NUM>).

In operation <NUM>, the silicon carbide substrate has a doped layer. Further, the first oxide layer is in direct contact with the silicon carbide substrate in one illustrative example. In another illustrative example, a set of intervening layers, such as a set of group III nitride layers, is located between the first silicon layer and the silicon carbide substrate.

The process etches the silicon carbide substrate having a doped layer using a photo-electrochemical etching process (operation <NUM>). In operation <NUM>, a doping level of the doped layer is such that the doped layer is removed and a silicon carbide device layer in the silicon carbide substrate remains unetched.

The process forms a semiconductor structure using a silicon carbide device layer (operation <NUM>). In operation <NUM>, other materials can also be used to form the semiconductor structure. For example, the set of group III layers or regions can be formed in this operation. Also, at least one of a cladding, a metal layer, or a metal region can also be formed in operation <NUM> to form the semiconductor structure.

The flowcharts and block diagrams in the different depicted embodiments illustrate the architecture, functionality, and operation of some possible implementations of apparatuses and methods in an illustrative embodiment. In this regard, each block in the flowcharts or block diagrams can represent at least one of a module, a segment, a function, or a portion of an operation or step. For example, one or more of the blocks can be implemented as instructions in program code, hardware, or a combination of the program code and hardware to control fabrication equipment for manufacturing semiconductor structures. When implemented in hardware, the hardware can, for example, take the form of integrated circuits that are manufactured or configured to perform one or more operations in the flowcharts or block diagrams. When implemented as a combination of program code and hardware, the implementation may take the form of firmware. Each block in the flowcharts or the block diagrams can be implemented using special purpose hardware systems that perform the different operations or combinations of special purpose hardware and program code run by the special purpose hardware to operate fabrication equipment to manufacture semiconductor structures.

In some alternative implementations of an illustrative embodiment, the function or functions noted in the blocks may occur out of the order noted in the figures. For example, in some cases, two blocks shown in succession may be performed substantially concurrently, or the blocks may sometimes be performed in the reverse order, depending upon the functionality involved. Also, other blocks may be added in addition to the illustrated blocks in a flowchart or block diagram.

For example, the bonding performed in operation <NUM> is shown as being performed prior to etching the silicon carbide substrate in operation <NUM>. In other illustrative examples, the bonding in operation <NUM> can be performed after etching occurs in operation <NUM>. As another example, other dielectrics having desired properties, such as a desired dielectric constant, can be used in place of or in addition to the silicon dioxide shown and described for the figures.

Turning now to <FIG>, an illustration of a block diagram of a product management system is depicted. Product management system <NUM> is a physical hardware system. In this illustrative example, product management system <NUM> includes at least one of manufacturing system <NUM> or maintenance system <NUM>.

Manufacturing system <NUM> is configured to manufacture products. As depicted, manufacturing system <NUM> includes manufacturing equipment <NUM>. Manufacturing equipment <NUM> includes at least one of fabrication equipment <NUM> or assembly equipment <NUM>.

Fabrication equipment <NUM> is equipment that used to fabricate components for parts used to form a product. Fabrication equipment <NUM> can be used to fabricate at least one of metal parts, composite parts, semiconductors, circuits, fasteners, ribs, skin panels, spars, antennas, or other suitable types of parts.

For example, fabrication equipment <NUM> can include machines and tools. These machines and tools can be at least one of a drill, a hydraulic press, a furnace, a mold, a composite tape laying machine, a vacuum system, a lathe, or other suitable types of equipment.

With respect to fabricating semiconductor components, fabrication equipment <NUM> can comprise at least one of an epitaxial reactor, an oxidation system, a diffusion system, an etching machine, a cleaning machine, a bonding machine, a dicing machine, a wafer saw, an ion implantation machine, a physical vapor deposition system, a chemical vapor deposition system, a photolithography system, an electron-beam lithography system, a plasma etcher, a die attachment machine, a wire bonder, a die overcoat system, molding equipment, a hermetic sealer, an electrical tester, a burn-in oven, a retention bake oven, a UV erase machine, or other suitable types of equipment that can be used to manufacture semiconductor structures.

Assembly equipment <NUM> is equipment used to assemble parts to form a product such as a chip, an integrated circuit, a computer, an aircraft, or some other product. Assembly equipment <NUM> also can include machines and tools. These machines and tools may be at least one of a robotic arm, a crawler, a fastener installation system, a rail-based drilling system, or a robot.

The maintenance system <NUM> includes maintenance equipment <NUM>. Maintenance equipment <NUM> can include any equipment needed to perform maintenance on a product. Maintenance equipment <NUM> may include tools for performing different operations on parts on a product. These operations can include at least one of disassembling parts, refurbishing parts, inspecting parts, reworking parts, manufacturing replacement parts, or other operations for performing maintenance on the product. These operations can be for routine maintenance, inspections, upgrades, refurbishment, or other types of maintenance operations.

The maintenance equipment <NUM> may include ultrasonic inspection devices, x-ray imaging systems, vision systems, drills, crawlers, and other suitable devices. In some cases, maintenance equipment <NUM> can include fabrication equipment <NUM>, assembly equipment <NUM>, or both to produce and assemble parts that needed for maintenance.

Product management system <NUM> also includes control system <NUM>. Control system <NUM> is a hardware system and may also include software or other types of components. Control system <NUM> is configured to control the operation of at least one of manufacturing system <NUM> or maintenance system <NUM>. In particular, control system <NUM> can control the operation of at least one of fabrication equipment <NUM>, assembly equipment <NUM>, or maintenance equipment <NUM>.

The hardware in control system <NUM> can be implemented using hardware that may include computers, circuits, networks, and other types of equipment. The control may take the form of direct control of manufacturing equipment <NUM>. For example, robots, computer-controlled machines, and other equipment can be controlled by control system <NUM>. The control ^system <NUM> can manage operations performed by human operators <NUM> in manufacturing or performing maintenance on a product. For example, control system <NUM> can assign tasks, provide instructions, display models, or perform other operations to manage operations performed by human operators <NUM>. In these illustrative examples, the different steps described and illustrated for fabricating semiconductor structures using silicon carbide and group III nitride layers can be implemented using control system <NUM>.

The human operators <NUM> can operate or interact with at least one of manufacturing equipment <NUM>, maintenance equipment <NUM>, or control system <NUM>. This interaction can occur to manufacture semiconductor structures and other components for products such as semiconductor devices or components for use in products such as aircraft, spacecraft, communications systems, micro-electromechanical systems, photonic devices, or superconducting single photon detectors.

The semiconductor structure is formed using the silicon carbide layer and the set of group III nitride layers.

Further, the processes in the illustrative examples are suitable for processing large-area wafers such as those that with an area of <NUM> cm2 or greater. The illustrative examples are compatible with currently used processes for these types of wafers to produce low-loss, high-thickness-uniformity silicon carbide and group III nitride-based crystalline structures on low-refractive-index insulators. This enables the production of active and passive integrated photonics and electronics in silicon carbide and group III nitrides.

For example, the illustrative example can include a combination of wafer bonding and then grinding/polishing or chemical-mechanical polishing for thinning the silicon carbide substrate, followed by photo-electrochemical etching from the carbon-face of the silicon carbide substrate. By making use of its material-selective etching property, the photo-electrochemical etching used in the listed example planarizes the silicon carbide layer into a clean crystal interface, resulting in a uniform silicon carbide film thickness.

To facilitate the photo-electrochemical etching, an electrode can be attached to another doped layer of the silicon carbide layer located beneath the surface being etched or the doped layer being etched and a second electrode can be located in the etching fluid. Applying photo-electrochemical etching in this way offers a different process for producing silicon carbide on insulator films compared to currently used techniques. Furthermore, the process in the illustrative example can be used to produce sub-micron thick films of silicon carbide and group III nitrides in a manner that preserves doped layers (e.g. p-i-n junctions) and structures beneath the exposed silicon carbide surface.

The resulting restructure can take many different forms in the illustrative examples. For example, without limitation, the semiconductor structure can be selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory using a point defect within the silicon carbide device layer. In other words, the semiconductor structure can include one or more of these devices and can include multiple devices of the same type.

The description of the different illustrative embodiments has been presented for purposes of illustration and description and is not intended to be exhaustive.

Claim 1:
A method for forming a semiconductor structure, the method comprising:
forming (<NUM>) a set of group III nitride layers (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) on a silicon carbide substrate (<NUM>, <NUM>), wherein the silicon carbide substrate (<NUM>, <NUM>) includes a doped layer (<NUM>, <NUM>, <NUM>) and a silicon carbide device layer (<NUM>, <NUM>) and wherein the doped layer (<NUM>, <NUM>, <NUM>) has a doping level such that the doped layer (<NUM>, <NUM>, <NUM>) is etched using a photo-electrochemical etching process while the silicon carbide substrate (<NUM>, <NUM>) remains unetched;
forming (<NUM>) a first oxide layer (<NUM>, <NUM>) on the set of group III nitride layers (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), wherein the set of group III nitride layers (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) is located between the first oxide layer (<NUM>, <NUM>) and the silicon carbide substrate (<NUM>, <NUM>);
bonding (<NUM>) the first oxide layer (<NUM>, <NUM>) to a second oxide layer (<NUM>, <NUM>) on a carrier substrate (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) to form an oxide layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) located between the carrier substrate (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) and the set of group III nitride layers (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>);
grinding (<NUM>) the silicon carbide substrate (<NUM>, <NUM>);
stopping (<NUM>) the grinding when a part of the doped layer (<NUM>, <NUM>, <NUM>) in the silicon carbide substrate (<NUM>, <NUM>) is reached;
etching (<NUM>) the silicon carbide substrate (<NUM>, <NUM>) using the photo-electrochemical etching process such that the doped layer (<NUM>, <NUM>, <NUM>) is removed and the silicon carbide device layer (<NUM>, <NUM>) in the silicon carbide substrate (<NUM>, <NUM>) remains when the part of the doped layer (<NUM>, <NUM>, <NUM>) in the silicon carbide substrate (<NUM>, <NUM>) is exposed; and
forming (<NUM>) the semiconductor structure using the silicon carbide device layer (<NUM>, <NUM>) and the set of group III nitride layers (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>).