Patent Description:
In a quantum computer, microwave output signals from a qubit are extremely weak, and a low-noise amplifier is used to amplify the microwave output signals with low noise. Noise characteristics of a transistor used in the amplifier are highly dependent on gate capacitance, and it is preferable to reduce the gate capacitance by shortening the gate length. However, even if the gate length is shortened to reduce the intrinsic capacitance, a semiconductor layer with a high dielectric constant is present under the electrode pad, which is connected to the gate electrode for signal supply from external wiring, and as a result, relatively large parasitic capacitance of the electrode pad remains as capacitance of the gate electrode. Since the area of the electrode pad is several um squared, much larger than the gate length of several tens of nanometers, the parasitic capacitance due to the electrode pad is a major impediment to noise reduction in the amplifier. The electrode pad provided for electrical connection requires a minimum of certain size area, so there appears to be a limit to reducing parasitic capacitance by reducing the size of the electrode pad.

In view of the above, it may be desirable to configure a semiconductor device with reduced parasitic capacitance of an electrode pad connected to a gate electrode.

A semiconductor device includes a substrate; a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode and the drain electrode being formed on the substrate; a plurality of nonconductive nanowires formed two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate; an electrode pad formed at upper ends of the plurality of nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nanowires; and an extraction electrode connecting the electrode pad and the gate electrode.

According to at least one embodiment of the present disclosure, a semiconductor device is configured to have reduced parasitic capacitance of an electrode pad connected to a gate electrode.

In the following, embodiments of the invention will be described with reference to the accompanying drawings.

<FIG> is a diagram illustrating an example of a configuration of a quantum computer. The quantum computer illustrated in <FIG> includes a cryogenic dilution refrigerator <NUM>, a microwave pulse generator <NUM>, a qubit chip <NUM>, a low-noise amplifier <NUM>, and a demodulator <NUM>.

The cryogenic dilution refrigerator <NUM> uses helium-<NUM> and helium-<NUM>, which are isotopes of helium, to cool, for example, the inside of a cylindrical casing to cryogenic temperatures on an order of several mK. The microwave pulse generator <NUM> placed in an external room-temperature environment generates microwave pulses and inputs the generated microwave pulses to the qubit chip <NUM>, which is set to cryogenic temperatures of approximately <NUM> mK. The qubit chip <NUM> performs quantum operations based on the qubits according to the input microwave pulses and outputs microwaves according to the state of the qubits after the operations. The low-noise amplifier <NUM> brought to a cryogenic state of approximately <NUM> amplifies the output microwaves with low noise, and supplies the amplified microwaves to the demodulator <NUM> placed in the external room-temperature environment. The demodulator <NUM> demodulates the amplified microwaves.

<FIG> is a diagram illustrating an example of a configuration of the low-noise amplifier <NUM>. The low-noise amplifier <NUM> includes a number of cascaded amplifying devices <NUM>-<NUM> to <NUM>-n. The output signal from the qubit chip <NUM> illustrated in <FIG> is input to a first-stage amplifying device <NUM>-<NUM>, and the output signal from the i-stage (i = <NUM> to n-<NUM>) amplifying device <NUM>-<NUM> is input to an (i+<NUM>)-stage amplifying device <NUM>-<NUM>. The output signal of an n-stage amplifying device <NUM>-<NUM> is supplied to the demodulator <NUM> illustrated in <FIG> as the output of the low-noise amplifier <NUM>.

<FIG> is a diagram illustrating an example of a configuration of one amplifying device. The amplifying device illustrated in <FIG> may be used as each of the amplifying devices <NUM>-<NUM> to <NUM>-n.

The amplifying device illustrated in <FIG> includes a first matching circuit <NUM>, a transistor <NUM>, a second matching circuit <NUM>, capacitive elements <NUM> to <NUM>, and resistive elements <NUM> and <NUM>. The input signal to the amplifying device is applied to a gate electrode of the transistor <NUM> via the capacitive element <NUM> and the first matching circuit <NUM>. The first matching circuit <NUM> performs impedance matching between the input side and the transistor <NUM> side. The transistor <NUM> amplifies the input signal applied to the gate electrode. The amplified signal is output to the outside via the second matching circuit <NUM> and the capacitive element <NUM>. The second matching circuit <NUM> performs impedance matching between the transistor <NUM> side and the output side.

To apply an input signal to the gate electrode of the transistor <NUM>, a signal line supplying the input signal is connected to an electrode pad connected to the gate electrode. To achieve amplification operation with low noise by the transistor <NUM>, the parasitic capacitance between the electrode pad and the source or drain electrode via the substrate needs to be reduced.

<FIG> is a top view illustrating an example of a configuration of a semiconductor device in which parasitic capacitance of the electrode pad is reduced. <FIG> is a cross-sectional view illustrating a cross section taken along a line A-A' of the semiconductor device illustrated in <FIG>.

The semiconductor device illustrated in <FIG> and <FIG> includes a dielectric substrate <NUM>, an active region <NUM>, a source electrode <NUM>, a drain electrode <NUM>, a gate electrode <NUM>, an extraction electrode <NUM>, an electrode pad <NUM>, and multiple nonconductive nanowires <NUM>. The semiconductor device illustrated in <FIG> and <FIG> is a compound semiconductor in which the active region <NUM> is formed on the substrate <NUM>. The substrate <NUM> functions as an element isolation region.

The gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> are arranged on the substrate <NUM> (more specifically, on an upper surface of the active region <NUM>). The multiple nonconductive nanowires <NUM> are arranged two-dimensionally on the upper surface of the substrate <NUM> so as to extend perpendicularly to the upper surface of the substrate <NUM>. The electrode pad <NUM> is positioned at upper ends of the multiple nanowires <NUM> so as to have a gap between the electrode pad and the substrate <NUM>, and is supported by the multiple nanowires <NUM>. The extraction electrode <NUM> electrically connects the electrode pad <NUM> to the gate electrode <NUM>.

Examples of preferred materials for the multiple nanowires <NUM> include AlGaAs, InAlAs, AlAs, InP, InAlP, GaP, AlGaP, InAsP, GaAsSP, GaSb, AlSb, AlGaSb, GaAsSb, and AlAsSb. Further examples of this material include GaN, AlN, AlGaN, InAlN, Si, Ge, SiGe, and C (diamond).

With the above configuration in which the electrode pad <NUM> is supported in an unfilled space by the multiple nanowires <NUM> an empty space is provided between the electrode pad <NUM> and the dielectric substrate <NUM>. Therefore, parasitic capacitance generated by the substrate <NUM>, a semiconductor with high dielectric constant, under the electrode pad <NUM> can be greatly reduced. Therefore, noise in the signal input to the transistor can be reduced.

In the semiconductor device illustrated in <FIG>, the gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> are formed on the upper surface of the active region <NUM>, and the active region <NUM> includes a channel layer and an electron supply layer, as described later. With the transistor having a HEMT (High Electron Mobility Transistor) structure, noise in the transistor can be further reduced.

<FIG> is a cross-sectional view illustrating a configuration of a gate electrode in a typical compound semiconductor. Unlike the configuration illustrated in <FIG>, in the typical compound semiconductor, an electrode pad <NUM> integrated with a gate electrode is formed so as to directly contact an upper surface of a substrate <NUM>. Therefore, relatively large capacitance is generated between the electrode pad <NUM> and the source electrode (not illustrated) or the drain electrode (not illustrated) via the dielectric substrate <NUM>.

In contrast, in the configuration illustrated in <FIG>, the capacitance between the electrode pad <NUM> and the source electrode <NUM> or the drain electrode <NUM> is reduced because a gap is provided between the electrode pad <NUM> and the substrate <NUM>. In addition, the electrode pad <NUM> is supported by the multiple nanowires <NUM>, so that the necessary and sufficient mechanical strength can be maintained. Accordingly, bonding wires and bumps can be easily formed on the electrode pad <NUM>. Also, in the configuration illustrated in <FIG>, the extraction electrode <NUM> is arranged so as to overlap the upper surface of the gate electrode <NUM>, which is equivalent to an increase in a cross-sectional area of the gate electrode when both are considered together. Since this configuration can reduce the gate resistance, the effect of further noise reduction can be obtained.

<FIG> is a top view illustrating an example of a configuration of the semiconductor device according to the first embodiment. <FIG> is a cross-sectional view illustrating a cross section taken along a line B-B' of the semiconductor device illustrated in <FIG>.

The semiconductor device illustrated in <FIG> includes a semi-insulating InP substrate <NUM>, an i-InAlAs buffer layer <NUM>, an i-GaAs layer <NUM>, a SiO<NUM> layer <NUM>, an i-InGaAs channel layer <NUM>, and an n-InAlAs supply layer <NUM>. The semiconductor device further includes a source electrode <NUM>, a drain electrode <NUM>, a gate electrode <NUM>, an extraction electrode <NUM>, an electrode pad <NUM>, and multiple nonconductive nanowires <NUM>. The source electrode <NUM>, the drain electrode <NUM>, and the gate electrode <NUM> may all be Ti/Pt/Au. Although not illustrated, n-InGaAs may be provided directly beneath the source electrode <NUM> and the drain electrode <NUM> for a non-alloyed ohmic connection.

The semiconductor device according to the first embodiment illustrated in <FIG> has basically the same configuration as the semiconductor device illustrated in <FIG>. That is, the gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> are arranged on (above) the substrate (InP substrate <NUM>, i-InAlAs buffer layer <NUM>, i-GaAs layer <NUM>, and SiO<NUM> layer <NUM>). The multiple nonconductive nanowires <NUM> are arranged two-dimensionally on the upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate. The electrode pad <NUM> is arranged at upper ends of the multiple nanowires <NUM> so as to have a gap between the electrode pad and the substrate, and is supported by the multiple nanowires <NUM>. The extraction electrode <NUM> electrically connects the electrode pad <NUM> to the gate electrode <NUM>.

In the semiconductor device according to the first embodiment illustrated in <FIG>, the i-InGaAs channel layer <NUM> and the n-InAlAs supply layer <NUM> correspond to the active region. The gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> are formed on the upper surface of the active region. The n-InAlAs supply layer <NUM> functions as an electron supply layer that supplies electrons, and the i-InGaAs channel layer <NUM> functions as an electron transport layer that transports electrons from the source electrode side to the drain electrode side. Thus, the semiconductor device according to the first embodiment has a HEMT structure.

The multiple nanowires <NUM> are formed by crystal growth of non-doped GaAs (i-GaAs). The nanowires <NUM> have substantially circular cross sections in a horizontal direction (more specifically, a prismatic shape according to a crystal structure), and the diameter is on the order of nanometers. The diameter of the nanowires <NUM> is, for example, preferably <NUM> or more and <NUM> or less, and more preferably <NUM> or more and <NUM> or less. The nanowires being thinner than <NUM> may have strength problems, and the nanowires being thicker than <NUM> may lose the capacitance reduction effect. Also, when the diameter is smaller than <NUM> or larger than <NUM>, it becomes difficult to grow multiple nanowires <NUM> into desired shapes.

The spacing between the multiple nanowires <NUM> is, for example, preferably <NUM> or more and <NUM> or less, and more preferably approximately <NUM>. When the spacing is narrower than <NUM> and the number of nanowires increases, the effect of capacitance reduction becomes small, and when the spacing is wider than <NUM> and the number of nanowires decreases, the strength problem occurs. When the spacing is narrower than <NUM> or wider than <NUM>, the crystal growth of multiple nanowires <NUM> into the desired shape becomes difficult.

In the semiconductor device according to the first embodiment, the substrate includes a first layer (i-GaAs layer <NUM>) made of the same material as the material (i-GaAs) used for the multiple nanowires <NUM>, and lower ends of the multiple nanowires <NUM> are in contact with the first layer (i-GaAs layer <NUM>). By providing the i-GaAs layer <NUM>, the i-GaAs layer <NUM> is made to function as a basis for crystal growth, enabling crystal growth of the multiple nanowires <NUM>. By using the i-GaAs layer <NUM> having an upper surface being a (<NUM>)B-plane, i.e., using the i-GaAs layer having a (<NUM>)B-plane orientation, the multiple nanowires <NUM> can grow in a vertical direction. The (<NUM>)B-plane orientation of the i-GaAs layer <NUM> is implemented by using the InP substrate <NUM> with the (<NUM>)B-plane orientation.

In the semiconductor device illustrated in <FIG>, the i-InGaAs channel layer <NUM> and the n-InAlAs supply layer <NUM> are separated by mesa etching. The i-InGaAs channel layer <NUM> is shorter than the n-InAlAs supply layer <NUM> in a lateral direction in the figures. This configuration is to prevent the gate electrode <NUM> formed on the sides as well as on the upper surface of the active region from being electrically short-circuited with the i-InGaAs channel layer <NUM>.

In the following, a method of manufacturing the semiconductor device according to the first embodiment illustrated in <FIG> is described in detail.

As illustrated in <FIG>, an i-InAlAs buffer layer <NUM>, an i-GaAs layer <NUM>, an i-InGaAs layer 44A, and an n-InAlAs layer 45A are sequentially grown on an InP substrate <NUM> having a.

(<NUM>)B-plane orientation. The thickness of each layer is, for example, <NUM> for the i-InAlAs buffer layer <NUM>, <NUM> for the i-GaAs layer <NUM>, <NUM> for the i-InGaAs layer 44A, and <NUM> for the n-InAlAs layer 45A. The doping concentration of the n-InAlAs layer 45A may, for example, be 1e19 cm-<NUM>.

In <FIG>, a resist <NUM> covering an active region is formed by photolithography, and the InGaAs layer 44A and the n-InAlAs layer 45A are wet etched to form a mesa-structured element separation. That is, the i-InGaAs layer 44A and the n-InAlAs layer 45A are scraped by wet etching to form an InGaAs layer 44B and an n-InAlAs supply layer <NUM>.

As illustrated in <FIG>, an i-InGaAs channel layer <NUM> is formed by selectively etching the InGaAs layer 44B to slightly make its horizontal width narrower than that of the n-InAlAs supply layer <NUM>. The resist <NUM> is then removed.

As illustrated in <FIG>, an entire structure in <FIG> obtained by chemical vapor deposition is covered with a SiO<NUM> film 43A.

As illustrated in <FIG>, a resist (not illustrated) is formed covering a region other than a nanowire formation region by electron beam lithography, and multiple openings are formed in the SiO<NUM> film 43A by dry etching. After the openings are formed, the resist is removed. The diameter of the openings is approximately <NUM> to <NUM>, and the number and arrangement positions of the openings match the number and arrangement positions of the multiple nanowires <NUM>. In order to facilitate the growth of the multiple nanowires <NUM>, Au catalyst (approximately <NUM> thick) may be deposited and a lift-off process is performed to form a film of Au catalyst at the opening positions.

As illustrated in <FIG>, i-GaAs nanowires <NUM> are grown at the opening positions using an organometallic vapor deposition method. Specifically, when the substrate temperature is heated from <NUM> to <NUM> degrees Celsius, and triethylgallium (TEGa) and arsine (AsH<NUM>) are supplied as the source gases, the source gases decompose and chemically react on the substrate surface, which allows the nanowires to grow by inheriting the crystal information of the base (i-GaAs layer <NUM>). The height of the multiple nanowires <NUM> may be greater than or equal to the height of a mesa, and may be approximately <NUM>, for example.

As illustrated in <FIG>, a resist <NUM> covering a region other than a gate electrode region is formed by photolithography, and the SiO<NUM> film 43A is dry etched. This forms the SiO<NUM> layer <NUM>.

As illustrated in <FIG>, a gate electrode <NUM> (Ti/Pt/Au) is deposited and a lift-off process is performed. At this time, since a gap is formed between the gate electrode <NUM> and the i-InGaAs channel layer <NUM>, an electrical short-circuit between the gate electrode <NUM> and the i-InGaAs channel layer <NUM> can be avoided. Note that the source electrode <NUM> (Ti/Pt/Au) and the drain electrode <NUM> (Ti/Pt/Au) are formed before the gate electrode <NUM> is formed at positions other than those illustrated in the cross-sectional view of <FIG>.

As illustrated in <FIG>, an entire upper side of the structure obtained in <FIG> is covered with a filler <NUM> such as PMGI (polydimethylglutamide), for example.

As illustrated in <FIG>, the filler <NUM> is subjected to etch back by dry etching to expose an upper surface of the gate electrode <NUM> and tips of the multiple nanowires <NUM>.

As illustrated in <FIG>, an extraction electrode <NUM> made of Ti/Au and an electrode pad <NUM> are disposed on the upper surfaces of the gate electrode <NUM>, the filler <NUM>, and the multiple nanowires <NUM>. Specifically, resist formation by photolithography, electrode material formation by deposition, and a lift-off process are performed sequentially.

As illustrated in <FIG>, the filler <NUM> is all removed by dissolving the filler <NUM> with a solvent, including the filler <NUM> present in the region where the multiple nanowires <NUM> are arranged directly beneath the electrode pad <NUM>. This configuration forms a gap between the electrode pad <NUM> and the substrate, leaving only the thin multiple nanowires <NUM> between the electrode pad <NUM> and the substrate.

The above-described processes form a semiconductor device with a HEMT structure according to the first embodiment.

<FIG> is a diagram illustrating device parameters of a HEMT device. Key parameters include source resistance Rs, gate resistance Rg, gate-source capacitance Cgs, gate-drain capacitance Cgd, and intrinsic transconductance gmint (simply illustrated as gm in <FIG>). Based on these parameters, the minimum noise figure Fmin is represented by the following equation (<NUM>):
[Equation <NUM>] <MAT> where K is the fitting coefficient, f is the frequency, and fT is the cutoff frequency. This fT is represented by the following equation (<NUM>) using device parameters:
[Equation <NUM>] <MAT>.

The equation (<NUM>) illustrates that fT increases when the gate-source capacitance Cgs is reduced. Furthermore, the equation (<NUM>) illustrates that Fmin can be reduced when fT is increased. Therefore, it is effective to reduce the gate capacitance to reduce the noise of the amplifying device.

In the following, the noise figure represented by the equation (<NUM>) above is evaluated for the configuration in which the electrode pad is directly mounted on the substrate (e.g., the configuration illustrated in <FIG>), and for the configuration in which the electrode pad is supported in an unfilled space by the multiple nanowires (the configurations illustrated in <FIG>, <FIG>, <FIG>, etc.).

Table <NUM> below illustrates that a "conventional pad" corresponds to a configuration in which the electrode pad is directly mounted on the substrate, and a "nanowire pad" corresponds to a configuration in which the electrode pad is supported in an unfilled space by multiple nanowires.

The gate electrode can be roughly divided into finger and pad sections. In the measured transistor structure of the conventional pad, a gate finger width of the finger section was <NUM>, and the pad was square with a side length of <NUM>. In the dependence of the measured gate capacitance Cgs on the gate length Lg, assuming that Lg was <NUM>, a value of <NUM> fF/mm was obtained for the gate capacitance Cgs. This value of <NUM> fF/mm corresponds to the pad parasitic capacitance in the absence of a gate finger. The overall gate capacitance measured was <NUM> fF/mm. Therefore, subtracting the above amount of pad parasitic capacitance, <NUM> (= <NUM> - <NUM>) fF/mm is the capacitance of the gate finger.

Assuming that a total of <NUM> nanowires with a diameter of <NUM> are arranged in <NUM> rows and <NUM> columns at a pitch of <NUM>, the cross-sectional area of the nanowires is <NUM> (= <NUM> × <NUM> × <NUM> × <NUM>) µm<NUM>. Since the area of a <NUM> × <NUM> pad is <NUM><NUM>, the parasitic capacitance of the nanowire pad calculated by the area ratio is approximately <NUM> (= <NUM> × <NUM>/<NUM>) fF/mm. That is, as illustrated in Table <NUM>, when focusing on the gate-to-source capacitance Cgs, the <NUM> fF/mm of the nanowire pad with respect to the <NUM> fF/mm of the conventional pad is reduced to <NUM>%.

Using these values and estimating the fT for the nanowire pad based on the fT = <NUM> measured for the transistor in the conventional pad case, the fT = <NUM> is obtained as illustrated in Table <NUM>. That is, fT = <NUM> for the nanowire pad is calculated by taking the gate-to-source capacitance Cgs as <NUM> fF/mm, which is the sum of <NUM> fF/mm of the nanowire pad and <NUM> fF/mm of the finger section capacitance, and putting the gate-to-drain capacitance Cgd (<NUM> fF/mm) and intrinsic transconductance gmint (<NUM>) into the equation (<NUM>).

Furthermore, by inputting the values of the gate-to-source capacitance Cgs and the cutoff frequency fT obtained above, and other parameters into the equation (<NUM>), the noise figure Fmin can be obtained for the conventional pad and for the nanowire pad. Specifically, at a measurement frequency of <NUM>, the noise figure Fmin = <NUM> for the conventional pad and Fmin = <NUM> for the nanowire pad at room temperature are calculated as illustrated in Table <NUM>. Furthermore, the noise temperature calculated by (Fmin-<NUM>) ·K as a value at <NUM> is illustrated in Table <NUM>. As can be seen from Table <NUM>, the noise temperature of the nanowire pad with respect to that of the conventional pad is reduced to <NUM>%.

Table <NUM> illustrates the calculated values of the area coverage when nanowire columns are formed on a <NUM> × <NUM> pad. The nanowire pitches of <NUM>, <NUM>, and <NUM> are illustrated, respectively.

When the outermost nanowires are to be formed at the four corners and edges of the pad, the number of nanowires in each nanowire pitch is automatically determined to be <NUM>, <NUM>, and <NUM>, based on a <NUM> x <NUM> square region being targeted as a pad region. When the diameter of the nanowires is <NUM> as a larger value, the coverage is <NUM>% in the case of a pitch of <NUM>. In this calculation, the coverage is estimated by assuming a larger value for the nanowire diameter. However, because the preferred nanowire diameter is as small as <NUM> to <NUM> as described above, the coverage is smaller than that illustrated in Table <NUM>. In general, the coverage calculated as the total area of the nanowires relative to the area of the electrode pad is preferably <NUM>% or less.

<FIG> is a top view illustrating an example of a configuration of a semiconductor device according to a second embodiment. <FIG> is a cross-sectional view illustrating a cross section taken along a line C-C' of the semiconductor device illustrated in <FIG>.

The semiconductor device illustrated in <FIG> includes a semi-insulating GaAs substrate <NUM>, an i-GaAs buffer layer <NUM>, a SiO<NUM> layer <NUM>, an i-InAlGaAs buffer layer <NUM>, an i-InGaAs channel layer <NUM>, and an n-InAlAs supply layer <NUM>. The semiconductor device further includes a source electrode <NUM>, a drain electrode <NUM>, a gate electrode <NUM>, an extraction electrode <NUM>, an electrode pad <NUM>, and multiple nonconductive nanowires <NUM>. The source electrode <NUM>, the drain electrode <NUM>, and the gate electrode <NUM> may all be Ti/Pt/Au. Although not illustrated, n-InGaAs may be provided directly beneath the source electrode <NUM> and the drain electrode <NUM> for a non-alloyed ohmic connection.

The semiconductor device according to the second embodiment illustrated in <FIG> has basically the same configuration as the semiconductor device illustrated in <FIG>. That is, the gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> are arranged on (above) the substrate (GaAs substrate <NUM>, i-GaAs buffer layer <NUM>, and SiO<NUM> layer <NUM>). The multiple nonconductive nanowires <NUM> are arranged two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate. The electrode pad <NUM> is arranged at the upper ends of the multiple nanowires <NUM> so as to have a gap between the electrode pad and the substrate, and is supported by the multiple nanowires <NUM>. The extraction electrode <NUM> electrically connects the electrode pad <NUM> to the gate electrode <NUM>.

In the semiconductor device according to the second embodiment illustrated in <FIG>, the i-InGaAs channel layer <NUM> and the n-InAlAs supply layer <NUM> correspond to the active region. The gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> are formed on the upper surface of the active region. The n-InAlAs supply layer <NUM> functions as an electron supply layer that supplies electrons, and the i-InGaAs channel layer <NUM> functions as an electron transport layer that transports electrons from the source electrode side to the drain electrode side. Thus, the semiconductor device according to the second embodiment has a HEMT structure.

The multiple nanowires <NUM> are formed by crystal growth of non-doped GaAs (i-GaAs). The nanowires <NUM> have substantially circular cross sections in a horizontal direction (more specifically, a prismatic shape according to a crystal structure) and the diameter is on the order of nanometers. The preferred diameter and pitch of the nanowires <NUM> are the same as in the first embodiment.

In the semiconductor device according to second embodiment, the substrate includes a first layer (i-GaAs buffer layer <NUM>) made of the same material as the material (i-GaAs) used for the multiple nanowires <NUM>, and lower ends of the multiple nanowires <NUM> are in contact with the first layer (i-GaAs buffer layer <NUM>). By providing the i-GaAs buffer layer <NUM>, the i-GaAs buffer layer <NUM> functions as a basis for crystal growth, enabling crystal growth of the multiple nanowires <NUM>. By using an i-GaAs layer having an upper surface being a (<NUM>)B-plane, i.e., using an i-GaAs layer having a (<NUM>)B-plane orientation, the multiple nanowires <NUM> can grow in a vertical direction. The (<NUM>)B-plane orientation of the i-GaAs buffer layer <NUM> is implemented by using a GaAs substrate <NUM> with (<NUM>)B-plane orientation as the semi-insulating GaAs substrate <NUM>.

In the semiconductor devices illustrated in <FIG>, the i-InAlGaAs buffer layer <NUM>, the i-InGaAs channel layer <NUM>, and the n-InAlAs supply layer <NUM> are separated by mesa etching. The i-InGaAs channel layer <NUM> is shorter than the n-InAlAs supply layer <NUM> in a lateral direction of the figures. This configuration is to prevent the gate electrode <NUM> formed on the sides as well as the upper surface of the active region from being electrically short-circuited with the i-InGaAs channel layer <NUM>.

Note that the crystal of the i-GaAs buffer layer <NUM> and the crystal of the i-InGaAs channel layer <NUM> exhibit mismatched lattice constants. Therefore, when the i-InGaAs channel layer <NUM> is directly formed on the upper surface of the i-GaAs buffer layer <NUM>, it is difficult to stably grow crystals of i-InGaAs channel layer <NUM> with low strain. To mitigate this lattice constant mismatch, the i-InAlGaAs buffer layer <NUM> is formed.

<FIG> is a diagram illustrating an example of a configuration of the i-InAlGaAs buffer layer <NUM>. As illustrated in <FIG>, the i-InAlGaAs buffer layer <NUM> has a gradually varying composition along its thickness direction. That is, when the composition of the i-InAlGaAs buffer layer <NUM> is i-InxAlyGa<NUM>-x-yAs, values of x and y are gradually changed along the thickness direction of the layer. Specifically, the values of x and y are gradually changed along the thickness direction of the layer so that x and y are close to <NUM> on the i-GaAs buffer layer <NUM> side, and x is close to <NUM> and y is close to <NUM> on the i-InGaAs channel layer <NUM> side. By providing such an i-InAlGaAs buffer layer <NUM>, crystal defects are less likely to occur in the i-InGaAs channel layer <NUM>, and the i-InGaAs channel layer <NUM> can grow stably.

A method of manufacturing the semiconductor device according to the second embodiment illustrated in <FIG> is described in detail below.

As illustrated in <FIG>, an i-GaAs buffer layer <NUM>, an i-InAlGaAs layer 63A, an i-InGaAs layer 64A, and an n-InAlAs layer 65A are sequentially grown on the semi-insulating GaAs substrate <NUM> with a (<NUM>)B-plane orientation. The thickness of each layer is, for example, <NUM> for the i-GaAs buffer layer <NUM>, <NUM> for the i-InAlGaAs layer 63A, <NUM> for the i-InGaAs layer 64A, and <NUM> for the n-InAlAs layer 65A. The doping concentration of the n-InAlAs layer 65A may be, for example, 1e19 cm-<NUM>.

In <FIG>, a resist <NUM> covering an active region is formed by photolithography, and the i-InAlGaAs layer 63A, the i-InGaAs layer 64A, and the n-InAlAs layer 65A are wet etched to form a mesa-structured element separation. That is, the i-InAlGaAs layer 63A, the i-InGaAs layer 64A, and the n-InAlAs layer 65A are wet etched to form an i-InAlGaAs buffer layer <NUM>, an i-InGaAs layer 64B, and an n-InAlAs supply layer <NUM>.

As illustrated in <FIG>, the i-InGaAs channel layer <NUM> is formed by selectively etching the i-InGaAs layer 64B to slightly make its horizontal width narrower than that of the n-InAlAs supply layer <NUM>. The resist <NUM> is then removed.

As illustrated in <FIG>, an entire structure in <FIG> obtained by chemical vapor deposition is covered with a SiO<NUM> film 62A.

As illustrated in <FIG>, a resist (not illustrated) is formed covering a region other than a nanowire formation region by electron beam lithography, and multiple openings are formed in the SiO<NUM> film 62A by dry etching. After the openings are formed, the resist is removed. The diameter of the openings is approximately <NUM> to <NUM>, and the number and arrangement positions of the openings match the number and arrangement positions of the multiple nanowires <NUM>. In order to facilitate the growth of the multiple nanowires <NUM>, Au catalyst (approximately <NUM> thick) may be deposited and a lift-off process is performed to form a film of Au catalyst at the opening positions.

As illustrated in <FIG>, i-GaAs nanowires <NUM> are grown at opening positions using an organometallic vapor deposition method. Specifically, when the substrate temperature is heated from <NUM> to <NUM> degrees Celsius, and triethylgallium (TEGa) and arsine (AsH<NUM>) are supplied as the source gases, the source gases decompose and chemically react on the substrate surface, which allows the nanowires to grow by inheriting the crystal information of the base (i-GaAs buffer layer <NUM>). The height of the multiple nanowires <NUM> may be greater than or equal to the height of a mesa, and may be, for example, approximately <NUM>.

As illustrated in <FIG>, a resist <NUM> covering a region other than a gate electrode region is formed by photolithography, and the SiO<NUM> film 62A is dry etched. This forms the SiO<NUM> layer <NUM>.

As illustrated in <FIG>, an entire upper side of the structure obtained in <FIG> is covered with a filler <NUM> such as PMGI, for example.

As illustrated in <FIG>, an extraction electrode <NUM> made of Ti/Au and an electrode pad <NUM> are disposed on upper surfaces of the gate electrode <NUM>, the filler <NUM>, and the multiple nanowires <NUM>. Specifically, resist formation by photolithography, electrode material formation by deposition, and a lift-off process are performed sequentially.

The above-described processes form a semiconductor device with a HEMT structure according to the second embodiment.

<FIG> is a top view illustrating an example of a configuration of a semiconductor device according to a third embodiment. <FIG> is a cross-sectional view illustrating a cross section taken along a line D-D' of the semiconductor device illustrated in <FIG>.

The semiconductor device according to the third embodiment illustrated in <FIG> and <FIG> differs from the semiconductor device according to the first embodiment illustrated in <FIG> only in that the multiple nanowires <NUM> are replaced with multiple nanowires 51A. Other configurations are identical between the first and third embodiments.

The material for the multiple nanowires <NUM> in the first embodiment is impurity-free i-GaAs, while the material for the multiple nanowires 51A in the third embodiment is GaAs, which is conductivity type-independent (i.e., it may include impurities). However, in order to remove the conductivity of the multiple nanowires 51A resulting from impurities, defects are introduced into the nanowires by performing an ion implantation process on the multiple nanowires 51A, as schematically illustrated by multiple arrows in <FIG>. Carriers resulting from impurities contained in GaAs can be trapped by these defects to make the multiple nanowires 51A nonconductive.

As described above, in the third embodiment, the multiple nanowires 51A are made of semiconductors deactivated by introducing defects. Therefore, when an inspection reveals that the multiple nanowires 51A are conductive in a manufactured semiconductor device, an ion implantation process can be incorporated into a manufacturing process to ensure that the nanowires are nonconductive in the semiconductor device to be manufactured thereafter.

A method of manufacturing the semiconductor device according to the third embodiment illustrated in <FIG> and <FIG> will be described in detail below.

In the manufacturing process of the third embodiment, the same manufacturing process as that of the first embodiment illustrated in <FIG> is performed first.

Then, as illustrated in <FIG>, nanowires 51A of, for example, n-GaAs (5e17 cm-<NUM>) are grown at opening positions using an organometallic vapor deposition method. The height of the multiple nanowires 51A may be higher than the mesa, and may be, for example, approximately <NUM>.

As illustrated in <FIG>, a resist <NUM> covering a region other than a gate electrode region is formed by photolithography.

As illustrated in <FIG>, by implanting oxygen ions into the nanowires 51A at an angle to the vertical direction, defects are introduced into the nanowires 51A to compensate the carriers. After the ion implantation process, the resist <NUM> is removed.

Then, the semiconductor device according to the third embodiment is completed by executing the same manufacturing process as that of the first embodiment illustrated in <FIG>.

<FIG> is a top view illustrating an example of a configuration of a semiconductor device according to a fourth embodiment. <FIG> is a cross-sectional view illustrating a cross section taken along a line E-E' of the semiconductor device illustrated in <FIG>.

The semiconductor device according to the fourth embodiment illustrated in <FIG> differs from the semiconductor device according to the first embodiment illustrated in <FIG> only in that an interlayer insulating film <NUM> is provided. Other configurations are identical between the first and fourth embodiments.

The semiconductor device according to the fourth embodiment includes an insulating film disposed over a substrate (more specifically, on a substrate, a transistor, and an electrode pad, etc.). By using this insulating film as an interlayer insulating film, an additional circuit can be formed on an upper surface of an interlayer insulating film. Also, because an insulating film <NUM> has a gap at positions of the multiple nanowires <NUM>, at least some of the multiple nanowires <NUM> are not in contact with the insulating film <NUM>. This makes it possible to provide an empty space between the electrode pad <NUM> and the dielectric substrate, while the interlayer insulating film is still provided, thereby reducing the parasitic capacitance generated by the substrate made of a semiconductor with a high dielectric constant, which is present under the electrode pad <NUM>. Therefore, noise in the signal input to the transistor can be reduced.

A method of manufacturing the semiconductor device according to the fourth embodiment illustrated in <FIG> will be described in detail below.

In the manufacturing process of the fourth embodiment, the same manufacturing process as that of the first embodiment illustrated in <FIG> is performed first.

The filler <NUM> (see <FIG>) is then removed by dry etching, as illustrated in <FIG>. At this time, the filler <NUM> remains only directly beneath the electrode pad <NUM>. A resist covering the position of the electrode pad <NUM> may be formed by photolithography to ensure that the filler <NUM> remains directly beneath the electrode pad <NUM>, and the resist may be removed thereafter.

As illustrated in <FIG>, an insulating film <NUM> made of, for example, BCB (benzocyclobutene) is formed to cover an entire upper side of the structure obtained in <FIG>. This enables the insulating film <NUM> to cover each member such as the gate electrode <NUM>, the extraction electrode <NUM>, and the electrode pad <NUM>, including the filler <NUM> remaining to surround the multiple nanowires <NUM>.

As illustrated in <FIG>, the filler <NUM> present in a region where the multiple nanowires <NUM> are arranged directly beneath the electrode pad <NUM> is removed by dissolving the filler <NUM> with a solvent. Specifically, holes are formed from the upper surface of the insulating film <NUM> to reach the filler <NUM>, and the filler <NUM> is dissolved and removed by pouring a solvent into the holes. As a result, a gap is formed between the electrode pad <NUM> and the substrate, and only the thin nanowires <NUM> exist between the electrode pad <NUM> and the substrate.

<FIG> is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to a fifth embodiment.

The semiconductor device according to the fifth embodiment illustrated in <FIG> differs from the semiconductor device according to the first embodiment only in that the multiple nanowires <NUM> are replaced with multiple nanowires <NUM>, the i-GaAs layer <NUM> is removed, and an AlO<NUM> layer <NUM> is provided instead of the SiO<NUM> layer <NUM>. Other configurations are identical between the first embodiment and the fifth embodiment.

In the semiconductor device according to the fifth embodiment, the multiple nanowires <NUM> are made of insulators. That is, the multiple nanowires <NUM> are not made of semiconductors such as i-GaAs but are made of insulating materials. The material for the multiple nanowires <NUM> may be BCB, for example, and may be formed by dry etching. In order to enable selective etching, an AlO<NUM> layer <NUM> is provided as a protective film in place of the SiO<NUM> layer <NUM>. This configuration does not require the i-GaAs layer <NUM>, which is provided in the semiconductor device according to the first embodiment, because the i-GaAs nanowires do not need to be grown.

Also, in the fifth embodiment, the nonconductive nanowires <NUM>, which are made of insulators, are arranged two-dimensionally on the upper surface of the substrate such that the nanowires extend perpendicularly to the upper surface of the substrate. The electrode pad <NUM> is arranged at upper ends of the nanowires <NUM> so as to have a gap between the electrode pad and the substrate, and is supported by the nanowires <NUM>. Therefore, parasitic capacitances generated by the substrate made of a semiconductor with high dielectric constant, which is present under the electrode pad <NUM>, can be greatly reduced. Therefore, noise in the signal input to the transistor can be reduced.

Claim 1:
A semiconductor device, comprising:
a substrate;
a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode and the drain electrode being formed on the substrate;
a plurality of nonconductive nanowires formed two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate;
an electrode pad formed at upper ends of the plurality of nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nanowires; and
an extraction electrode connecting the electrode pad and the gate electrode.