Patent Description:
Generally, the wafer material applied in the production of the semiconductor chip is mainly single crystal epitaxial wafer and single crystal polished wafer. The epitaxial wafer is obtained through forming an epitaxial layer on the single crystal polished wafer serving as the substrate layer, wherein the substrate layer is for supporting and the epitaxial layer is applied in producing the semiconductor chip. The high-voltage semiconductor chip requires a higher epitaxial layer thickness. With the increase of the epitaxial layer thickness, not only the cost greatly increases, but also the defect density increases, so that it is failed to meet the production requirements of the high-voltage large-power semiconductor chip, and the substrate layer limits the performance of the semiconductor chip.

The semiconductor material which is represented by silicon is hard and crisp. The single crystal epitaxial wafer and the single crystal polished wafer require certain thickness, so as to increase the strength thereof. During the production process of the semiconductor chip, backgrinding is necessary for removing the excess thickness, causing the high cost and the high technical difficulty.

With higher and higher requirements on energy saving and cost reducing, the requirements on the voltage and power consumption of the semiconductor device becomes high and higher. The requirement on the working voltage of the semiconductor device gradually increases to <NUM> V and even higher, while the voltage of the semiconductor device, which is produced based on the epitaxial wafer, is generally not higher than <NUM> V. The limitation of the epitaxial wafer is obvious, and because of being limited by the inherent characteristics of the conventional semiconductor wafer material, the power consumption bottleneck of the semiconductor device is not effectively and greatly reduced. Moreover, the power semiconductor production gradually enters the high-integration-level submicron complementary metal-oxide-semiconductor (CMOS) age. However, based on the conventional semiconductor wafer material, the submicron CMOS production process is radically not compatible with the three-dimensional deep-PN-junction structure required by the high-voltage large-power device, which becomes the key bottleneck of the continuous development of the high-performance power semiconductor.

Document <CIT> discloses a substrate having n-type impurities provided with trenches in which p-type pillars are formed by means of epitaxy thus forming a superjunction structure. According to an example, said substrate can also be bonded to a SOI substrate. A back side of the SOI substrate is removed together with a buried insulating layer thus forming a thin, n-type device layer on top of the superjunction layer.

Document <CIT> discloses a method of manufacturing semiconductor device. The method includes etching grooves in a first and a second semiconductor substrates having n-type and p-type conductivity types respectively. The areas of grooves in the first semiconductor substrate correspond to the areas without grooves in the second semiconductor substrate.

Two semiconductor substrates are directly bonded together so that the grooves in the first semiconductor substrate are filled with the grooves in the second semiconductor substrate thus forming a superjunction structure.

An object of the present invention is to provide a three-dimensional semiconductor wafer as defined in claim <NUM>, so as to solve problems in prior arts. According to the present invention, at least one connection layer and a conduction layer are arranged on a semiconductor wafer unit, so as to improve semiconductor performance. The preferred embodiment is defined in claim <NUM>.

In order to accomplish the above object, the present invention adopts following technical solutions.

A three-dimensional semiconductor wafer is defined in claim <NUM> and comprises a semiconductor wafer unit, at least one connection layer, a conduction layer and a protection layer, wherein: the protection layer is arranged on the conduction layer; and, the connection layer and the conduction layer are arranged on the semiconductor wafer unit at a bottom surface of the semiconductor wafer unit.

Preferably, the semiconductor wafer unit is cylindrical.

Through adopting the above technical solutions, the present invention and not claimed examples useful for understanding the present invention have following beneficial effects.

Through arranging the connection layer and the conduction layer on the semiconductor wafer unit, a semiconductor performance is increased. The three-dimensional semiconductor wafer provided by the present invention not only replaces two-dimensional semiconductor wafer materials such as a single crystal epitaxial wafer, but also provides a design basis for a semiconductor device.

According to a not claimed example being useful for understanding the invention, firstly, a three-dimensional deep-junction structure namely the connection layer, for withstanding a high voltage, is formed on the semiconductor wafer unit, which solves a process contradiction between a submicron complementary metal-oxide-semiconductor (CMOS) process and a deep-PN-junction structure of a power semiconductor chip, simplifies a production process of the power semiconductor chip, and reduces a production difficulty of the power semiconductor chip.

Secondly, the present invention effectively increases a current density of the semiconductor chip. Compared with a conventional semiconductor chip, a power loss of the semiconductor chip based on the present invention is decreased by more than <NUM>%.

Thirdly, the present invention reduces a defect density of a high resistance area of the semiconductor wafer and greatly decreases a leak current of the semiconductor chip. Compared with the conventional semiconductor chip, the leak current of the semiconductor chip based on the present invention can be decreased by <NUM>-<NUM> magnitudes.

Fourthly, the present invention increases a secondary breakdown tolerance of the power semiconductor. Compared with the conventional semiconductor chip, the secondary breakdown tolerance of the semiconductor chip based on the present invention is increased by more than <NUM>%, so that an anti-burn ability of the device is radically improved.

Fifthly, because of an effect of the connection layer, an ultrathin requirement on the semiconductor wafer is greatly reduced, which solves a processing technology difficulty of an ultrathin sheet when backside metalizing based on the conventional semiconductor wafer.

Sixthly, the three-dimensional structure of the present invention is able to greatly decrease a thermal stress of the semiconductor wafer, so that the semiconductor wafer is more flat and has more toughness, and is difficult to be broken during the production process of the semiconductor chip.

Seventhly, each parameter of the three-dimensional semiconductor wafer has a good controllability. An electrical resistivity is selectable in a range of <NUM>-<NUM>Ω·cm, a difference of the electrical resistivity is controlled in ±<NUM>%, and an in-plane electrical resistivity nonuniformity is controlled in <NUM>%; a total thickness is selectable in a range of <NUM>-<NUM>; a thickness of the high resistance area of the semiconductor wafer is customizable in a range of <NUM>-<NUM>, and a thickness difference of the high resistance area of the semiconductor wafer is controlled in ±<NUM>.

Eighthly, the semiconductor device produced based on the present invention is able to realize a working voltage of <NUM> V, <NUM> V, <NUM> V and even higher, namely the present invention is applicable in producing various semiconductor devices with a working voltage from several volts to over ten thousand volts.

The present invention has a high practicability, an easy operation, a rigorous, coordinated and effective control plan, a smart design and an easy implementation, which greatly improves the semiconductor performance and meanwhile brings the convenience to the use of the customer. In the following parts of the description the terms and expressions "embodiment" and "preferred embodiment of the present invention" are used. Irrespective of these terms and expressions, only the preferred embodiments as shown in <FIG> and <FIG> fall under the scope of the independent claim <NUM> and therefore they form part of the invention.

Embodiments shown in <FIG> and <FIG> correspond to not claimed examples useful for understanding the present invention.

In the drawings: <NUM>: semiconductor wafer unit; <NUM> connection part; <NUM>: conduction layer; and <NUM>: protection layer.

The present invention is illustrated in detail with the following preferred embodiments. An object of disclosing the present invention is to protect all modifications encompassed within the scope of the present invention as defined by the appended claims.

Referring to <FIG>, a three-dimensional semiconductor wafer comprises a semiconductor wafer unit <NUM>, at least one connection layer, a conduction layer <NUM> and a protection layer <NUM>, wherein: the protection layer <NUM> is arranged on the conduction layer <NUM>; the connection layer and the conduction layer <NUM> are arranged on the semiconductor wafer unit <NUM> at any surface of the semiconductor wafer unit <NUM>; the semiconductor wafer unit <NUM> is cylindrical; the connection layer is arranged on a bottom surface of the semiconductor wafer unit <NUM>; the connection layer comprises a plurality of connection parts <NUM>; a first end of each connection part <NUM> is inserted into the semiconductor wafer unit <NUM>, and a second end of each connection part <NUM> is level with the bottom surface of the semiconductor wafer unit <NUM>; the connection parts <NUM> are prismatic, cylindrical, circular or elliptic; the connection parts <NUM> are arranged inside the semiconductor wafer unit <NUM> in a form of array; the conduction layer <NUM> is arranged on the bottom surface of the semiconductor wafer unit <NUM>; and the protection layer <NUM> is arranged on an outer surface of the conduction layer <NUM>.

For the three-dimensional semiconductor wafer, according to types of semiconductors of different power, a conduction type of the three-dimensional semiconductor wafer unit <NUM>, the connection layer, and the conduction layer <NUM> can be respectively selected as N-type or P-type, wherein the bottom surface of the semiconductor wafer unit <NUM> can be produced according to requirements of a chip.

First preferred embodiment: (N-/N+/N+)-typed three-dimensional semiconductor wafer.

Referring to <FIG>, the semiconductor wafer unit <NUM> is a high resistance area with the conduction type of N-type, namely an N- area; the connection layer is a high concentration area with the conduction type of N-type, namely an N+ area; for the array-distributed connection parts <NUM>, the first ends are inserted into the semiconductor wafer unit <NUM>, and the second ends are connected to each other on the bottom surface of the semiconductor wafer unit <NUM> through the conduction layer <NUM>; the conduction layer <NUM> is a high concentration area with the conduction type of N-type, namely the N+ area; and the protection layer <NUM> is arranged on the conduction layer <NUM> at the bottom surface of the semiconductor wafer unit <NUM>. The above three-dimensional semiconductor wafer is mainly applicable in production of metal-oxide-semiconductor field-effect transistor (MOSFET) and fast recovery diode (FRD). Through a design and an implementation of the unique three-dimensional connection parts, a MOSFET chip has an increased current density and a power loss decreased by more than <NUM>%, so that a layout area of the chip is effectively decreased and a composite cost of the chip is reduced. Moreover, a softness factor of a FRD chip is increased.

Second preferred embodiment: (N-/P+/P+)-typed three-dimensional semiconductor wafer, not forming part of the present invention but useful for its understanding.

Referring to <FIG>, the semiconductor wafer unit <NUM> is a high resistance area with the conduction type of N-type, namely an N- area; the connection layer is a high concentration area with the conduction type of P-type, namely a P+ area; for the array-distributed connection parts <NUM>, the first ends are inserted into the semiconductor wafer unit <NUM>, and the second ends are connected to each other on the bottom surface of the semiconductor wafer unit <NUM> through the conduction layer <NUM>; the conduction layer <NUM> is a high concentration area with the conduction type of P-type, namely the P+ area; and the protection layer <NUM> is arranged on the conduction layer <NUM> at the bottom surface of the semiconductor wafer unit <NUM>. The above three-dimensional semiconductor wafer is mainly applicable in production of insulated gate bipolar transistor (IGBT). Through adopting the three-dimensional semiconductor wafer to produce an IGBT chip, complex technological processes such as wafer backgrinding and P+ injection, before backside metallization, in a conventional IGBT chip production process is reduced, and a production process of the IGBT chip is completely same as a production process of a vertical double-diffused metal-oxide-semiconductor (VDMOS), so that the production of the IGBT chip is simplified, optimized and easily realized. That is to say, a production line having a production capacity of the VDMOS chip is able to produce the IGBT chip, so that a capital investment of a dedicated IGBT production line is reduced and a finished product rate of the chip is increased, which is more beneficial to development and widespread application of the IGBT.

Third preferred embodiment: (N-/N+/P+)-typed three-dimensional semiconductor wafer, not forming part of the present invention but useful for its understanding.

Referring to <FIG>, the semiconductor wafer unit <NUM> is a high resistance area with the conduction type of N-type, namely an N- area; the connection layer is a high concentration area with the conduction type of N-type, namely an N+ area; for the array-distributed connection parts <NUM>, the first ends are inserted into the semiconductor wafer unit <NUM>, and the second ends are connected to each other on the bottom surface of the semiconductor wafer unit <NUM> through the conduction layer <NUM>; the conduction layer <NUM> is a high concentration area with the conduction type of P-type, namely a P+ area; and the protection layer <NUM> is arranged on the conduction layer <NUM> at the bottom surface of the semiconductor wafer unit <NUM>. The above three-dimensional semiconductor wafer is mainly applicable in production of IGBT with anodes in parallel. The IGBT with the anodes in parallel, which is produced through adopting the three-dimensional semiconductor wafer, has an excellent high-speed switch function with a switch frequency of <NUM>, a lower power loss and a higher efficiency.

Fourth preferred embodiment: (N-/P+/N+)-typed three-dimensional semiconductor wafer, not forming part of the present invention but useful for its understanding.

Referring to <FIG>, the semiconductor wafer unit <NUM> is a high resistance area with the conduction type of N-type, namely an N- area; the connection layer is a high concentration area with the conduction type of P-type, namely a P+ area; for the array-distributed connection parts <NUM>, the first ends are inserted into the semiconductor wafer unit <NUM>, and the second ends are connected to each other on the bottom surface of the semiconductor wafer unit <NUM> through the conduction layer <NUM>; the conduction layer <NUM> is a high concentration area with the conduction type of N-type, namely an N+ area; and the protection layer <NUM> is arranged on the conduction layer <NUM> at the bottom surface of the semiconductor wafer unit <NUM>. The above three-dimensional semiconductor wafer is mainly applicable in production of N-channel enhancement mode MOSFET and FRD chip. An N-channel enhancement mode MOSFET chip, which is produced through adopting the three-dimensional semiconductor wafer, has a power loss decreased by more than <NUM>% and a secondary breakdown tolerance increased by more than <NUM>%.

Fifth preferred embodiment: (P-/P+/P+)-typed three-dimensional semiconductor wafer, not forming part of the present invention but useful for its understanding.

Referring to <FIG>, the semiconductor wafer unit <NUM> is a high resistance area with the conduction type of P-type, namely a P- area; the connection layer is a high concentration area with the conduction type of P-type, namely a P+ area; for the array-distributed connection parts <NUM>, the first ends are inserted into the semiconductor wafer unit <NUM>, and the second ends are connected to each other on the bottom surface of the semiconductor wafer unit <NUM> through the conduction layer <NUM>; the conduction layer <NUM> is a high concentration area with the conduction type of P-type, namely the P+ area; and the protection layer <NUM> is arranged on the conduction layer <NUM> at the bottom surface of the semiconductor wafer unit <NUM>. The above three-dimensional semiconductor wafer is mainly applicable in production of P-channel enhancement mode MOSFET and giant transistor (GTR).

Sixth preferred embodiment: (P-/N+/N+)-typed three-dimensional semiconductor wafer, not forming part of the present invention but useful for its understanding.

Referring to <FIG>, the semiconductor wafer unit <NUM> is a high resistance area with the conduction type of P-type, namely a P- area; the connection layer is a high concentration area with the conduction type of N-type, namely an N+ area; for the array-distributed connection parts <NUM>, the first ends are inserted into the semiconductor wafer unit <NUM>, and the second ends are connected to each other on the bottom surface of the semiconductor wafer unit <NUM> through the conduction layer <NUM>; the conduction layer <NUM> is a high concentration area with the conduction type of N-type, namely the N+ area; and the protection layer <NUM> is arranged on the conduction layer <NUM> at the bottom surface of the semiconductor wafer unit <NUM>. The above three-dimensional semiconductor wafer is mainly applicable in production of Cool metal-oxide-semiconductor (MOS). Compared with conventional Power MOS, an on-resistance of the Cool MOS is decreased by <NUM>-<NUM> times. However, the production of the Cool MOS is complex that more than <NUM> times of ion injection and epitaxy are required, a technical difficulty is high and a cost is high. Through adopting the three-dimensional semiconductor wafer to produce a Cool MOS chip, an array-distributed three-dimensional structure withstanding a high voltage is directly formed, which simplifies the complex production process of the Cool MOS chip and reduces a production difficulty thereof, so that a technical breakthrough of Cool MOS production is realized.

Seventh preferred embodiment: (N-/P+ top surface/N+)-typed three-dimensional semiconductor wafer, not forming part of the present invention but useful for its understanding.

Referring to <FIG>, the semiconductor wafer unit <NUM> is a high resistance area with the conduction type of N-type, namely an N- area; the connection layer is a high concentration area with the conduction type of P-type, namely a P+ area; for the array-distributed connection parts <NUM>, the first ends are inserted into the semiconductor wafer unit <NUM>, and the second ends are level with a top surface of the semiconductor wafer unit <NUM>; the conduction layer <NUM> is a high concentration area with the conduction type of N-type, namely an N+ area; and the protection layer <NUM> is arranged on the conduction layer <NUM> at the bottom surface of the semiconductor wafer unit <NUM>. The above three-dimensional semiconductor wafer is mainly applicable in production of Cool MOS. Through adopting the customized three-dimensional semiconductor wafer to produce a Cool MOS chip, a production difficulty is reduced, a chip cost is greatly decreased, and a better cost performance at an application client is achieved.

Eighth preferred embodiment: (N-/P+ top surface/N+ bottom surface/N+)-typed three-dimensional semiconductor wafer.

Claim 1:
A three-dimensional semiconductor wafer, comprising a semiconductor wafer unit (<NUM>), a connection layer, a conduction layer (<NUM>) and a protection layer (<NUM>), wherein the protection layer is arranged on the conduction layer; and, the connection layer and the conduction layer are arranged on the semiconductor wafer unit at a bottom surface of the semiconductor wafer unit, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO2 layer, wherein the connection layer comprises a plurality of three-dimensional connection parts (<NUM>); a first end of each connection part is inserted into the semiconductor wafer unit, and a second end of each connection part is level with the bottom surface of the semiconductor wafer unit; and the connection parts are arranged inside the semiconductor wafer unit in a form of array, the semiconductor wafer unit is defined as an N- area which has a conduction type of N-type; the connection layer is defined as an N+ area which has the conduction type of N-type; for array-distributed connection parts, first ends are inserted into the semiconductor wafer unit, and second ends are connected to each other on the bottom surface of the semiconductor wafer unit through the conduction layer; the conduction layer is defined as the N+ area which has the conduction type of N-type; and the protection layer is arranged on the conduction layer at the bottom surface of the semiconductor wafer unit.