Patent Description:
Many types of integrated circuit (IC) devices, such as programable logic IC devices and microprocessor IC devices, communicate with one or more external memory IC devices. The memory IC devices may be in the same package, or coupled to the same circuit board, as the programmable logic or microprocessor IC device. IC devices that communicate with external memory devices typically contain memory interfaces that contain input/output pads and related circuitry. Different memory interfaces in the same IC device may require different power supply voltages. Therefore, input/output (IO) pads are often arranged in input/output (IO) banks in order to support the different memory interfaces. Each IO bank may have its own power supply voltage that is independent of the other IO banks in the IC device. IO buffers within the same IO bank may share the same power supply voltage.

<CIT> describes an integrated circuit in a physical layer of a receiver. The integrated circuit comprises a multi-lane interface, a lane selection circuit and N sampling circuits. The multi-lane interface has N lanes. N is an integer greater than one. The lane selection circuit, coupled to the multi-lane interface, is configured to select M of the N lanes as M clock lanes, and output M signals on the M clock lanes respectively. M is a positive integer less than N. Remaining (N-M) lanes serve as (N-M) data lanes. The receiver is configured to communicate with each of transmitters TX[<NUM>]-TX[K-l] through a communication link therebetween. Each of lanes LA[<NUM>]-LA[<NUM>] in the multi-lane interface can be implemented using a two-wire lane, which is a differential lane including a pair of signal pins and an amplifier.

<CIT> describes input/output (I/O) bank architectures for use within an integrated circuit.

<CIT> describes address mapping including generic bits.

The problems of the related art are solved by the present invention in the aspects of an integrated circuit and a method having the features of the independent claims.

One or more specific examples are described below. In an effort to provide a concise description of these examples, not all features of an actual implementation are described in the specification.

An integrated circuit (IC) can only have a limited number of input/output (IO) banks, because of the limitations of the size and the floorplan of the IC die. In the design of each IC, there is often a tradeoff between the number of IO banks in the IC that are used for external memory interfaces, the number of other types of external interfaces, and the cost and die size of the IC. The limited number of input/output banks in an IC die has to satisfy customer requirements for the number and type of external memory interfaces and test features in the IC. In previously known IC dies, each IO bank could only be part of one external memory interface. The external memory interfaces could not be shared to maximize the usage of the external memory interfaces in the IC. Because only one external memory interface could be used for each IO bank, a user of the IC would not be able to support multiple external memory interfaces within a single IO bank. As a result, an IC die could support a fewer number of external memory interfaces.

According to some examples disclosed herein, systems and methods are provided for integrated circuits (ICs) having input/output (IO) banks and sub-banks that support sharing between two or more different external interfaces. An IC may have one or more IO banks. Each of the IO banks may include external IO terminals (e.g., IO pads) and related circuitry coupled to each of the external IO terminals, such as input and output driver circuits. Each of the IO banks in the IC may include two or more sub-banks. Each of the sub-banks may include two or more lanes. Each of the lanes may include a subset of the external IO terminals and the related circuitry in the IO bank. Each of the sub-banks in an IO bank may be part of two or more different external interfaces. As an example, one or more lanes in sub-bank may be used as part of a first external interface to exchange signals with one external device, and one or more other lanes in the same sub-bank may be used as part of a second external interface to exchange signals with a second external device. Because each of the sub-banks in an IO bank can be part of multiple external interfaces, the IC can support more external interfaces with the same number of IO banks. These features allow an IC to have more flexibility and versatility, because the IO banks in the IC can be configured to support different external interfaces for different types of external devices. An IC that allows a sub-bank to be shared with multiple different external interfaces may allow the IC die size to be reduced, may allow more external interfaces to be supported, and may allow for more compact designs of circuit boards, reducing the overall system footprint and cost.

<FIG> is a diagram that illustrates an example of an input/output (IO) bank <NUM> that can be shared between multiple different external interfaces. IO bank <NUM> shown in Figure (<FIG> includes <NUM> groups <NUM>-<NUM> of external terminals, <NUM> groups of input/output (IO) driver circuits <NUM>-<NUM>, <NUM> input/output (IO) phase-locked loop (PLL) circuits <NUM>-<NUM>, and two clock phase alignment (CPA) circuits <NUM>-<NUM>. The IO driver circuits <NUM>-<NUM> are coupled to and in communication with the adjacent external terminals in groups <NUM>-<NUM>, respectively. Each of the groups of the IO driver circuits <NUM>-<NUM> exchange input and output signals with a respective group of the external terminals <NUM>-<NUM>. Each of the external terminals may be, for example, an IO pad or pin. Each group of external terminals and an adjacent group of IO driver circuits forms an IO lane. As examples, group <NUM> of external terminals and IO driver circuits <NUM> form a first IO lane, and group <NUM> of external terminals and IO driver circuits <NUM> form a second IO lane. Groups <NUM>-<NUM> of external terminals and the adjacent groups <NUM>-<NUM> of IO driver circuits, respectively, form <NUM> IO lanes in IO bank <NUM>.

IO bank <NUM> may, for example, be fabricated in an integrated circuit (IC) die, such as a programmable logic IC, a microprocessor IC, and graphics processing unit (IC), etc. An IC die may, for example, include two or more of the IO banks <NUM>. As a more specific example, an IC die may include <NUM> IO banks <NUM>. As other examples, an IC die may include 10IO banks, 12IO banks, 14IO banks, etc..

The circuitry in IO bank <NUM> is arranged into two sub-banks. The first sub-bank in IO bank <NUM> includes external terminal groups <NUM>-<NUM>, IO driver circuits <NUM>-<NUM>, IO PLL circuit <NUM>, and CPA circuit <NUM>. IO PLL circuit <NUM> generates one or more periodic clock signals CLK1 that are provided to CPA circuit <NUM>. CPA circuit <NUM> provides the clock signals CLK1 to the IO driver circuits <NUM>-<NUM> in the first sub-bank through clock networks. CPA circuit <NUM> generates phase shifts in the clock signals CLK1 that cause each of the IO driver circuits <NUM>-<NUM> to receive the same delay in the clock signals CLK1. The IO driver circuits <NUM>-<NUM> use the clock signals CLK1 to send and/or receive input/output signals to/from the external terminals in groups <NUM>-<NUM>, respectively. The second sub-bank in IO bank <NUM> includes groups <NUM>-<NUM> of external terminals, IO driver circuits <NUM>-<NUM>, IO PLL circuit <NUM>, and CPA circuit <NUM>. IO PLL circuit <NUM> generates one or more periodic clock signals CLK2 that are provided to the CPA circuit <NUM>. CPA circuit <NUM> provides the clock signals CLK2 to the IO driver circuits <NUM>-<NUM> in the second sub-bank through clock networks. CPA circuit <NUM> generates phase shifts in the clock signals CLK2 that cause each of the IO driver circuits <NUM>-<NUM> to receive the same delay in the clock signals CLK2. The IO driver circuits <NUM>-<NUM> use the clock signals CLK2 to send and/or receive input/output signals to/from the external IO terminals in groups <NUM>-<NUM>, respectively.

<FIG> is a diagram that illustrates examples of the <NUM> groups <NUM>-<NUM> of external terminals shown in <FIG> that are part of IO bank <NUM>. In the example of <FIG>, each of the groups <NUM>-<NUM> of external terminals shown in <FIG> includes <NUM> external terminals, such as <NUM> input/output (IO) pads or pins. Thus, the groups <NUM>-<NUM> have a total of <NUM> external terminals (i.e., <NUM> IO terminals) that are numbered <NUM>-<NUM> in <FIG>, as an example. Although <NUM> external terminals are shown in each of the groups <NUM>-<NUM> of external terminals as an example, it should be understood that each of the groups <NUM>-<NUM> shown in <FIG> may include any suitable number of external terminals.

IO lane <NUM> includes external terminals <NUM>-<NUM>. IO lane <NUM> includes external terminals <NUM>-<NUM>. IO lane <NUM> includes external terminals <NUM>-<NUM>. IO lane <NUM> includes external terminals <NUM>-<NUM>. IO lane <NUM> includes external terminals <NUM>-<NUM>. IO lane <NUM> includes external terminals <NUM>-<NUM>. IO lane <NUM> includes external terminals <NUM>-<NUM>. IO lane <NUM> includes external terminals <NUM>-<NUM>. Each of the external terminals in each of the IO lanes <NUM>-<NUM> may, for example, be coupled to an input driver circuit and/or an output driver circuit in a respective one of the IO drivers <NUM>-<NUM> shown in <FIG>. Each of the external terminals <NUM>-<NUM> may be used to transmit and/or receive one or more signals between the IC containing IO bank <NUM> and one or more external devices.

<FIG> is a diagram that illustrates examples of two input/output (IO) banks having sub-banks that can be shared between two or more external interfaces. The first IO bank of <FIG> includes sub-bank <NUM> and sub-bank <NUM>. The second IO bank of <FIG> includes sub-bank <NUM> and sub-bank <NUM>. Each of the sub-banks <NUM>-<NUM> shown in <FIG> may, for example, include <NUM> IO lanes, such as the IO lanes shown in <FIG>. In the example of <FIG>, sub-bank <NUM> includes <NUM> IO lanes 302A-302D. Each of the IO lanes 302A-302D may include <NUM> external terminals, as shown for example, in <FIG>, or any other number of external terminals.

Any of the sub-banks <NUM>-<NUM> can be part of one, two, three, or more different external interfaces. In the example of <FIG>, the external terminals and the IO driver circuits in each of the <NUM> IO lanes in the sub-bank <NUM> are part of a first double data rate external memory interface (referred to herein as DDRO) that supports the transmission of data signals with a first external memory device <NUM>. The external terminals and the IO driver circuits in IO lane 302A in sub-bank <NUM> are also part of the first DDR external memory interface DDR0. Thus, <NUM> IO lanes in the IO bank that includes sub-banks <NUM>-<NUM> are part of the first DDR0 external memory interface in the example of <FIG>. The DDR0 external memory interface of <FIG> may include, for example, a total of <NUM> external terminals in sub-bank <NUM> and in IO lane 302A (e.g., <NUM> pads or pins).

Also, in the example of <FIG>, the external terminals and the IO driver circuits in each of the IO lanes in sub-banks <NUM> and <NUM> are part of a second double data rate external memory interface (referred to herein as DDR1) that supports the transmission of data signals with a second external memory device <NUM>. The external terminals and the IO driver circuits in three IO lanes 302B, 302C, and 302D in sub-bank <NUM> are also part of the second DDR1 external memory interface. Thus, <NUM> lanes in sub-bank <NUM>, <NUM> IO lanes in sub-bank <NUM>, and <NUM> IO lanes 302B-302D in sub-bank <NUM>, for a total of <NUM> IO lanes, are part of the DDR1 external memory interface in the example of <FIG>. The DDR1 external memory interface of <FIG> may include a total of <NUM> external terminals in sub-banks <NUM>-<NUM> and in IO lanes 302B-302D (e.g., <NUM> pads or pins), with <NUM> external terminals in each IO lane, as shown for example, in <FIG>.

According to specific examples, one or both of the DDR0 external interface and/or the DDR1 external interface of <FIG> may be a Double Data Rate <NUM> Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) interface. According to other specific examples, one or both of the DDR0 external interface and/or the DDR1 external interface of <FIG> may be a Double Data Rate <NUM> Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) interface. A sub-bank in an IO bank may include one or more IO lanes that are part of a DDR4 external memory interface and one or more IO lanes that are part of a DDR5 external memory interface. Thus, a single sub-bank of an IO bank may be shared between a DDR4 external memory interface and a DDR5 external memory interface. According to other examples, a sub-bank in an IO bank may be shared between two or more external interfaces that may implement any of the following data transmission protocols, such as low-voltage differential signaling (LVDS), DDR4 x72 (compact or non-compact), DDR4 x64, DDR4 x40, DDR x16, DDR x8, and/or any type of DDR5.

<FIG> is a diagram that illustrates other examples of input/output (IO) banks having sub-banks that can be shared between two or more external interfaces. In the example of <FIG>, a first IO bank (shown by arrow <NUM>) includes IO lanes 401A-<NUM> and phase-locked loop (PLL) circuits 403A-403B, and a second IO bank (shown by arrow <NUM>) includes IO lanes 402A-<NUM> and PLL circuits 404A-404B. The first IO bank <NUM> includes a first sub-bank that comprises IO lanes 401A-401D and a second sub-bank that comprises IO lanes 401E-<NUM>. The second IO bank <NUM> includes a first sub-bank that comprises IO lanes 402A-402D and a second sub-bank that comprises IO lanes 402E-<NUM>.

Any of the sub-banks in IO banks <NUM>-<NUM> can be part of one, two, three, or more different external interfaces. In the example of <FIG>, the external terminals and the IO driver circuits in each of the <NUM> IO lanes 401A-<NUM> and 402A-402C are used as part of a first external interface, and the IO lane 402D in bank <NUM> is used as part of a second external interface. As an example, the IO lanes 401A-<NUM> and 402A-402C may be part of a double data rate (DDR) external memory interface that supports the transmission of data signals with an external memory device. IO lanes <NUM>, 401A, 401B, 401C, 401D, 402A, 402B, and 402C are used to exchange data signals Data0, Data1, Data2, Data3, Data4, Data5, Data6, and Data7, respectively, with the external device. IO lanes 401E, 401F, and <NUM> are used to exchange command signals CMD0, CMD1, and CMD2, respectively, with the external device. The IO lane 402D may be part of a different external interface that has external terminals and associated IO driver circuits that are used to exchange general purpose input/output (IO) signals (GPIO) with a different external device.

The PLL circuit 403A may be used to generate a clock signal for the IO driver circuits in IO lanes 401A-401D. The PLL circuit 403B may be used to generate a clock signal for the IO driver circuits in IO lanes 401E-<NUM>. The PLL circuit 404A may be used to generate a clock signal for the IO driver circuits in IO lanes 402A-402D. The PLL circuit 404B may be used to generate a clock signal for the IO driver circuits in IO lanes 402E-<NUM>.

The sub-bank sharing of external interfaces as disclosed herein can be migrated from one IC die to another IC die. For various design reasons, it may be desirable to substitute a smaller IC die with a larger IC die in an IC package. The sharing of a sub-bank between multiple external interfaces as disclosed herein can be migrated from a smaller IC die to a larger IC die in the same IC package. In an exemplary scenario, sub-bank sharing may be useful to enable optimal DDR memory interfaces.

<FIG> is a diagram that illustrates an example of a unified fabric interface (UFI) logic circuit <NUM>. <FIG> shows the groups <NUM>-<NUM> of external terminals and the groups <NUM>-<NUM> of the IO driver circuits in the <NUM> IO lanes of IO bank <NUM>. The IO driver circuits in groups <NUM>-<NUM> may receive data input signals from one or more external devices through the external terminals in groups <NUM>-<NUM>, respectively. IO driver circuits <NUM>-<NUM> may receive clock signals CLK1 from CPA circuit <NUM>, and IO driver circuits <NUM>-<NUM> may receive clock signals CLK2 from CPA circuit <NUM>, as described above.

The UFI logic circuit <NUM> of <FIG> is an interface between IO bank <NUM> and the core logic circuits <NUM> in the integrated circuit (IC). Data and clock signals may be transmitted from the IO lanes in IO bank <NUM> to the UFI logic circuit <NUM>. As shown in <FIG>, data and clock signals Clk1/Data1, Clk2/Data2, Clk3/Data3, Clk4/Data4, Clk5/Data5, Clk6/Data6, Clk7/Data7, and Clk8/Data8 may be transmitted from groups <NUM>-<NUM> of IO driver circuits, respectively, to inputs of UFI logic circuit <NUM>. UFI logic circuit <NUM> can phase shift the clock signal from each of the IO lanes to align the clock signal with the data signals from the same IO lane. For example, UFI logic circuit <NUM> may contain registers that delay clock signals Clk1, Clk2, Clk3, Clk4, Clk5, Clk6 Clk7, and Clk8 to be phase aligned with data signals Data1, Data2, Data3, Data4, Data5, Data6, Data7, and Data <NUM>, respectively. UFI logic circuit <NUM> then transmits the data signals Data1-<NUM> and the phase aligned clock signals Clk1-<NUM> to core logic circuits <NUM>. Core logic circuits <NUM> may include, for example, programmable logic circuits, memory circuits, and/or digital signal processing (DSP) circuits.

UFI logic circuit <NUM> handles two-way transfers of data and clock signals between the IO lanes in IO bank <NUM> and the core logic circuits <NUM>. Data signals Data1-<NUM> and clock signals Clk1-<NUM> may be transmitted from the core logic circuits <NUM> to UFI logic circuit <NUM>. UFI logic circuit <NUM> can phase shift the clock signal to be transmitted to each of the IO lanes to align with the data signals to be transmitted to the same IO lane. For example, UFI logic circuit <NUM> may contain registers that delay clock signals Clk1, Clk2, Clk3, Clk4, Clk5, Clk6 Clk7, and Clk8 to be phase aligned with data signals Data1, Data2, Data3, Data4, Data5, Data6, Data7, and Data <NUM>, respectively. UFI logic circuit <NUM> transmits the data signals Data1-<NUM> and phase aligned clock signals Clk1-<NUM> to the <NUM> groups <NUM>-<NUM> of IO driver circuits as signals Clk1/Data1, Clk2/Data2, Clk3/Data3, Clk4/Data4, Clk5/Data5, Clk6/Data6, Clk7/Data7, and Clk8/Data8, respectively. The IO driver circuits in groups <NUM>-<NUM> may transmit the data and/or clock signals received from UFI logic circuit <NUM> to one or more external devices through external terminals in groups <NUM>-<NUM>, respectively.

<FIG> is a diagram that illustrates an example of a selector circuit <NUM> that can interface between IO lanes in one or more IO banks and the unified fabric interface (UFI) logic circuit <NUM> of <FIG>. <FIG> illustrates <NUM> IO lanes <NUM>-<NUM> that may be part of one or more IO banks. IO lanes <NUM>-<NUM> are part of a first sub-bank <NUM> of an IO bank. IO lanes <NUM>-<NUM> are part of a second sub-bank <NUM> of an IO bank. IO lanes <NUM>-<NUM> generate <NUM> sets of clock and data signals Clk1/Data1, Clk2/Data2, Clk3/Data3, Clk4/Data4, Clk5/Data5, Clk6/Data6, Clk7/Data7, and Clk8/Data8, respectively, that are transmitted to inputs of selector circuit <NUM>. Selector circuit <NUM> receives Select signals, for example, from a controller circuit or from software. Selector circuit <NUM> may be configured as a multiplexer by the Select signals to transmit the clock signals Clk1-<NUM> and data signals Data1-<NUM> to UFI logic circuit <NUM> through selected bus lines. The Select signals may cause the selector circuit <NUM> to transmit signals from the IO lanes that are part of an external interface to the UFI circuit <NUM> through bus lines designated for the external interface. For example, if IO lanes <NUM>-<NUM> are part of a first external interface (e.g., a DDR memory interface), and IO lanes <NUM>-<NUM> are part of a second external interface (e.g., a GPIO interface), then the selector circuit <NUM> may be configured to transmit signals Clk1/Data1-Clk2/Data6 to UFI circuit <NUM> through bus lines designated for the first external interface, and selector circuit <NUM> may be configured to transmit signals Clk7/Data7-Clk8/Data8 to UFI circuit <NUM> through bus lines designated for the second external interface. UFI logic circuit <NUM> transmits the phase aligned clock signals Clk1-<NUM> and data signals Data1-<NUM> to core logic circuits <NUM>.

Data signals and clock signals Clk1-<NUM>/Data1-<NUM> may be transmitted from the core logic circuits <NUM> to selector circuit <NUM> through the UFI logic circuit <NUM> for the IO lanes in sub-banks <NUM>-<NUM>. Selector circuit <NUM> may be configured as a demultiplexer by the Select signals to transmit the clock signals and data signals for an external interface from UFI logic circuit <NUM> to the IO lanes in sub-banks <NUM>-<NUM> that are part of that external interface. For example, if IO lanes <NUM>-<NUM> are part of a first external interface, then selector circuit <NUM> may be configured to transmit clock and data signals Clk3/Data3-Clk7/Data7 for the first external interface from UFI circuit <NUM> to IO lanes <NUM>-<NUM>, respectively. If IO lanes <NUM>-<NUM> are part of a second external interface, then selector circuit <NUM> may be configured to transmit clock and data signals Clk1/Data1-Clk2/Data2 for the second external interface from UFI circuit <NUM> to IO lanes <NUM>-<NUM>, respectively. If IO lane <NUM> is part of a third external interface, then selector circuit <NUM> may be configured to transmit clock and data signals Clk8/Data8 for the third external interface from UFI circuit <NUM> to IO lane <NUM>.

<FIG> is a diagram that illustrates examples of clock networks that are used to transmit clock signals to IO lanes in sub-banks. <FIG> illustrates the <NUM> IO lanes <NUM>-<NUM> in sub-bank <NUM> and the <NUM> IO lanes <NUM>-<NUM> in sub-bank <NUM> that are shown in <FIG>. In the example of <FIG>, IO lanes <NUM>-<NUM> are part of a first external interface (e.g., a DDR memory interface) that supports sharing between sub-banks <NUM>-<NUM>, and IO lanes <NUM>-<NUM> are part of a second external interface (e.g., a GPIO interface). IO lane <NUM> outputs a first clock signal CLKA that is transmitted through a first balanced clock network <NUM> to each of the IO lanes <NUM>-<NUM> in the first external interface. IO lane <NUM> may, for example, generate clock signal CLKA with a clock data recovery circuit, a phase-locked loop circuit, or a buffer or driver circuit. Because the first clock network <NUM> is balanced, each of the IO lanes <NUM>-<NUM> receives the clock signal CLKA having the same delay.

IO lanes <NUM>-<NUM> may have a different configuration for a different external interface that supports sharing between sub-banks <NUM>-<NUM>. In another configuration, IO lane <NUM> outputs a second clock signal CLKB that is transmitted through a second balanced clock network <NUM> to IO lanes <NUM>-<NUM> in another external interface. IO lane <NUM> may, for example, generate the clock signal CLKB with a clock data recovery circuit, a phase-locked loop circuit, or an buffer or driver circuit. Because the second clock network <NUM> is balanced, each of the IO lanes <NUM>-<NUM> receives the clock signal CLKB having the same delay. Each of the clock networks <NUM>-<NUM> may include circuits that are configurable to cause the clock networks <NUM>-<NUM> to be balanced for the IO lanes in an external interface in order to provide the same delay to the clock signals as received at the IO lanes.

An illustrative programmable logic integrated circuit (IC) <NUM> is shown in <FIG>. As shown in <FIG>, programmable logic integrated circuit <NUM> may have input/output (IO) circuitry <NUM> for driving signals off of IC <NUM> and for receiving signals from other devices via input-output pads <NUM>. IO circuitry <NUM> may include any of the IO banks, sub-banks, and IO lanes disclosed herein. Each of the IO banks may receive supply current from a separate supply voltage. Interconnection resources <NUM> such as global, regional, and local vertical and horizontal conductive lines and buses may be used to route signals on IC <NUM>. Interconnection resources <NUM> include fixed interconnects (conductive lines) and programmable interconnects (i.e., programmable connections between respective fixed interconnects). Programmable logic circuitry <NUM> may include combinational and sequential logic circuitry. The programmable logic circuitry <NUM> may be configured to perform custom logic functions.

Programmable logic IC <NUM> contains memory elements <NUM> that can be loaded with configuration data (also called programming data) using pads <NUM> and input-output circuitry <NUM>. Once loaded, the memory elements <NUM> may each provide a corresponding static control output signal that controls the state of an associated logic component in programmable logic circuitry <NUM>. Typically, the memory element output signals are used to control the gates of metal-oxide-semiconductor (MOS) transistors.

In general, software and data for performing any of the functions disclosed herein may be stored in non-transitory computer readable storage media. Non-transitory computer readable storage media is tangible computer readable storage media that stores data for a significant period of time, as opposed to media that only transmits propagating electrical signals (e.g., wires). The software code may sometimes be referred to as software, data, program instructions, instructions, or code. The non-transitory computer readable storage media may include computer memory chips, non-volatile memory such as non-volatile random-access memory (NVRAM), one or more hard drives (e.g., magnetic drives or solid state drives), one or more removable flash drives or other removable media, compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs (BDs), other optical media, and floppy diskettes, tapes, or any other suitable memory or storage device(s).

Additional examples are now described. Example <NUM> is an integrated circuit as claimed in independent apparatus claim <NUM>.

In Example <NUM>, the integrated circuit of Example <NUM> may further comprise: a third input/output lane comprising third external terminals and third driver circuits, wherein the third driver circuits exchange signals with the second external device through the third external terminals as part of the second external interface, and wherein the third input/output lane is part of the first sub-bank in the first input/output bank.

In Example <NUM>, the integrated circuit of Example <NUM> may further comprise: a fourth input/output lane comprising fourth external terminals and fourth driver circuits, wherein the fourth driver circuits exchange signals with the first external device through the fourth external terminals as part of the first external interface, and wherein the fourth input/output lane is part of the first sub-bank in the first input/output bank.

In Example <NUM>, the integrated circuit of Example <NUM> may further comprise: a third input/output lane comprising third external terminals and third driver circuits, wherein the third driver circuits exchange signals with the second external device through the third external terminals as part of the second external interface, and wherein the third input/output lane is part of a second sub-bank in a second input/output bank.

In Example <NUM>, the integrated circuit of any one of Examples <NUM>-<NUM> may optionally include, wherein the first and the second external interfaces are memory interfaces, and wherein the first and the second external devices are memory devices.

In Example <NUM>, the integrated circuit of any one of Examples <NUM>-<NUM> may further comprise: a unified fabric interface circuit that phase aligns a clock signal received from the first input/output lane with a data signal received from the first input/output lane.

In Example <NUM>, the integrated circuit of any one of Examples <NUM>-<NUM> may further comprise: logic circuits in a core logic region of the integrated circuit; and a selector circuit that is configurable to provide signals from the first and the second input/output lanes to the logic circuits.

In Example <NUM>, the integrated circuit of Example <NUM> may optionally include, wherein the selector circuit is configurable to provide signals from the logic circuits to the first and the second input/output lanes.

In Example <NUM>, the integrated circuit of Example <NUM> may further comprise: a clock network that provides a clock signal from the second input/output lane to each of the second and the third input/output lanes.

Example <NUM> is a method for sharing a first sub-bank in a first input/output bank with first and second external interfaces, as claimed in independent method claim <NUM>.

In Example <NUM>, the method of Example <NUM> may further comprise: implementing a third input/output lane in the first sub-bank as at least a part of the second external interface to exchange signals with the second external device through third external terminals using third driver circuits in the third input/output lane.

In Example <NUM>, the method of Example <NUM> may further comprise: implementing a fourth input/output lane in the first sub-bank as at least a part of the first external interface to exchange signals with the first external device through fourth external terminals using fourth driver circuits in the fourth input/output lane.

In Example <NUM>, the method of Example <NUM> may further comprise: implementing a third input/output lane as at least a part of the second external interface to exchange signals with the second external device through third external terminals using third driver circuits in the third input/output lane, wherein the third input/output lane is part of a second sub-bank in a second input/output bank, and wherein the second input/output bank is in the integrated circuit.

In Example <NUM>, the method of any one of Examples <NUM>-<NUM> may further comprise: phase aligning a clock signal received from the first input/output lane with a data signal received from the first input/output lane at a unified fabric interface circuit.

In Example <NUM>, the method of any one of Examples <NUM>-<NUM> may further comprise: configuring a selector circuit to provide signals from the first and the second input/output lanes to logic circuits in a core logic region of the integrated circuit.

In Example <NUM>, the method of Example <NUM> may further comprise: configuring the selector circuit to provide signals from the logic circuits to the first and the second input/output lanes.

In Example <NUM>, the method of Example <NUM> may further comprise: configuring a clock network to provide a clock signal from the second input/output lane to each of the second and the third input/output lanes.

In Example <NUM>, the method of any one of Examples <NUM>-<NUM> may further include: providing supply current to each of the first input/output lane and the second input/output lane from a supply voltage.

Example <NUM> is an integrated circuit package comprising: first and second integrated circuits; and a third integrated circuit comprising a first input/output lane comprising first external terminals and first driver circuits, wherein the first input/output lane is part of a sub-bank in an input/output bank, wherein the first input/output lane implements at least a part of a first external interface, wherein the first driver circuits exchange signals with the first integrated circuit through the first external terminals, wherein the third integrated circuit further comprises a second input/output lane comprising second external terminals and second driver circuits, wherein the second input/output lane is part of the sub-bank in the input/output bank, wherein the second input/output lane implements at least a part of a second external interface, and wherein the second driver circuits exchange signals with the second integrated circuit through the second external terminals.

In Example <NUM>, the integrated circuit package of Example <NUM> may optionally include, wherein the third integrated circuit further comprises a third input/output lane comprising third external terminals and third driver circuits, wherein the third input/output lane is part of the sub-bank in the input/output bank, and wherein the third driver circuits exchange signals with the second integrated circuit through the third external terminals as part of the second external interface.

Claim 1:
An integrated circuit comprising:
a first input/output lane (<NUM>) comprising first external terminals (<NUM>) and first driver circuits (<NUM>), wherein the first driver circuits (<NUM>) exchange signals with a first external memory device through the first external terminals (<NUM>) as part of a first external memory interface, and wherein the first input/output lane (<NUM>) is part of a first sub-bank that implements at least a part of the first external memory interface in a first input/output bank (<NUM>), wherein supply current is provided to the first input/output lane (<NUM>) from a supply voltage; and
a second input/output lane (<NUM>) comprising second external terminals (<NUM>) and second driver circuits (<NUM>), wherein the second driver circuits (<NUM>) exchange signals with the first external memory device through the second external terminals (<NUM>) as part of the first external memory interface in a first configuration, wherein the second driver circuits (<NUM>) exchange signals with a second external memory device through the second external terminals (<NUM>) as part of a second external memory interface in a second configuration, and wherein the second input/output lane (<NUM>) is part of the first sub-bank that implements at least a part of the second external memory interface in the first input/output bank (<NUM>), wherein supply current is provided to the second input/output lane (<NUM>) from the supply voltage.