Patent Description:
This disclosure relates generally to semiconductor devices, and more specifically, to via opening of semiconductor devices.

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device and each interconnect becomes increasingly significant.

<CIT> discloses fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects. An AB<NUM> triblock copolymer layer comprises a first segregated block component disposed over the dielectric lines of the lower metallization layer. The triblock copolymer layer includes alternating second and third segregated block components disposed over the metal lines of the lower metallization layer. Further, a segregated triblock BCP may be partitioned along axis by portions.

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. An example via opening is a contact hole. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via. The via may be a plating through via, blind via (e.g., a via connecting the outermost circuit of a printed circuit board (PCB) and the adjacent inner layer), buried via (e.g., a via connecting circuit layers of a PCB but not passing to the outer layer of the PCB), or other types of vias.

In the past, the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of the size of the vias is the critical dimension (e.g., a diameter or some other transverse cross-sectional dimension) of the via opening. One measure of the spacing of the vias is the via pitch, representing the center-to-center distance between the closest adjacent vias.

When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment.

Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. Via opening rectification technologies exist to reduce the critical dimensions of the via openings. However, the reduced amount tends to be limited by the minimum via pitch, as well as by the ability of the via opening rectification process to be sufficiently optical proximity correction (OPC) neutral, and to not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU). Yet another such challenge is that the LWR and/or CDU characteristics of photoresists generally need to improve as the critical dimensions of the via openings decrease to maintain the same overall fraction of the critical dimension budget. However, currently the LWR and/or CDU characteristics of most photoresists are not improving as rapidly as the critical dimensions of the via openings are decreasing.

A further such challenge is that the extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners. As a result, commonly two, three, or more different lithographic masks may be used, which tend to increase the costs. At some point, if pitches continue to decrease, it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners. Even though EUV defined via openings offer a lot of design flexibility and helps save number of masks, EUV defined via openings show a lot of variability in LWR and/or CDU due to stochastic nature of the process. The variability increases with decreasing critical dimensions. Additionally, the via opening critical dimensions needed are beyond what EUV can do currently.

Present state of the art method to reduce the critical dimension of EUV holes is to print a relatively large hole and then taper it down to final dimension using etch. Any variability in the starting hole dimension persists post taper and, in some cases, results in missing holes. DSA based via opening rectification approach has been used to scale the CD to final dimension without etch tapering as well as reduce the variation in CD. DSA based via opening rectification has been demonstrated in the past using cylindrical diblock copolymers. Cylindrical diblock copolymers form cylinders (or holes) but fail to form elongated via openings. One problem with the cylindrical structure is that it restricts design flexibility. The other problem is that diblock copolymers are not able to rectify variations in CD nonuniformity as well due to limitations in their flexibility (expansion and contraction). As a result, the variations are not rectified enough.

Therefore, improved technology for rectifying via openings is needed.

The present invention is directed to an IC device according to claim <NUM>. The device includes a first layer and a second layer. The second layer adjoins the first layer. The second layer includes lamellar structures. An individual lamellar structure includes a via between two lamellae. The two lamellae are electrically insulating, and the via includes an electrically conductive material. The two lamellae may be two different blocks of a triblock copolymer. The two lamellae may include the same polymer. The via includes a conductive material. The via may be a through via, a blind via, or a buried via. In some embodiments, the first layer includes a grating pattern, which is an alternative pattern of first section and second sections. The second sections include a different material from the first section. The via is in a portion of the second layer that adjoins a first section of the first layer. The present invention also is directed to a method of forming openings for an IC device according to claim <NUM>.

Embodiments of the present invention also relate to rectifying via openings by using triblock copolymers that form lamellar phase ("lamellar triblock copolymers"). Compared with diblock copolymers, lamellar triblock copolymers show a higher degree of flexibility in terms of compression and expansion. Also, lamellar triblock copolymers can form elongated via openings that are desirable for IC devices. Compared with diblock copolymers, lamellar triblock copolymers show a much wider process window for incoming pattern variations and can rectify via openings with a large variation in the CD. Additionally, lamellar triblock copolymers offer much more flexibility in terms of via opening shape and size. In various embodiments, a triblock copolymer molecule includes two blocks of a first polymer and a block of a second polymer that is different from the first polymer. The block of the second polymer is between the blocks of the first polymer. The lamellar phase of the triblock copolymer molecule includes three lamellae: two lamellae of the first polymer and a lamella of the second polymer between the two lamellae of the first polymer. The lamellar triblock copolymer may be self-assembled on a surface of a semiconductor layer and elongates in a direction perpendicular to the surface of the semiconductor layer. The self-assembly of the lamellar triblock copolymer may be based on graphoepitaxy, chemoepitaxy, or a combination of both. The lamella of the second polymer can be removed from the lamellar triblock copolymer to form via openings. The dimensions of the via openings are based at least in part on the dimensions of the lamella of the second polymer. In some embodiments, the first polymer is more rigid than the second polymer to control uniformity of the dimensions of the via openings. Via openings rectified by using such a lamellar triblock copolymer can have better CDU, compared with via openings rectified by using diblock copolymers.

Further embodiments not forming part of the present invention relate to rectifying via openings by using polymer nanocomposites. In various embodiments, a polymer nanocomposite molecule includes a nanoparticle and a polymer (e.g., a block copolymer). The polymer chain is attached to the nanoparticle. The nanoparticle may be surrounded by the polymer in multiple dimensions. An embodiment of the polymer nanocomposite forms a cylindrical phase, phase not forming part of the invention, in which the nanoparticle is a cylinder, and the polymer is a hollow cylinder enclosing the nanoparticle cylinder. The nanoparticle cylinder may be removed from the polymer nanocomposite molecules to form via openings. As the dimensions of the via openings are based on the dimensions of the nanoparticle, the via openings can have the same or similar dimensions as long as the dimensions of the nanoparticles of the polymer nanocomposite molecules are consistent. Accordingly, the via openings can be independent of CD variations and can give one CD distribution. The shape of the polymer defines the CD.

Further embodiments of the present invention relate to rectifying via openings by using a mixed epitaxy approach. The mixed epitaxy approach is a combination of graphoepitaxy and chemoepitaxy. In some embodiments, graphoepitaxy is used to form a topographical guiding pattern that includes walls and openings between the walls. Further, chemoepitaxy is used to form a chemical guiding pattern in an individual opening. Accordingly, the mixed epitaxy approach provides a mixed guiding pattern that include the topographical guiding pattern and chemical guiding patterns within the topographical guiding pattern. The mixed guiding pattern may be used for DSA of diblock copolymers, triblock copolymers, or polymer nano composites not forming part of the invention, Such an approach may rectify any EPE (edge placement error) that may occur during the placement of the vias and can steer the vias to the desired via design. Compared with via opening rectification that is based on graphoepitaxy alone, the mixed epitaxy approach can have a much wider process window and can tolerate and rectify much larger variations in the CD nonuniformity of the via openings. This approach can also offer more flexibility in via opening design.

Various IC devices with one or more via openings rectified by using a lamellar triblock copolymer, a polymer nanocomposite not forming part of the invention, or mixed epitaxy as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

In some embodiments, via openings rectified by using a lamellar triblock copolymer, a polymer nanocomposite, or mixed epitaxy as described herein may be used to form conductive vias of a metallization stack of an IC device. A term "metallization stack" (also sometimes referred to as an "interconnect stack") may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip. A term "interconnect" may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the "interconnect" may refer to both conductive lines/wires (also sometimes referred to as "lines" or "metal lines" or "trenches") and conductive vias (also sometimes referred to as "vias" or "metal vias"). In general, the term "conductive line" may be used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such conductive lines are typically stacked into several levels, or several layers of metallization stacks. On the other hand, the term "conductive via" may be used to describe an electrically conductive element that interconnects two or more trench contacts of different levels. To that end, a via may be provided substantially perpendicularly to the plane of an IC chip and may interconnect two conductive lines in adjacent levels or two conductive lines in not adjacent levels.

For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well known features are omitted or simplified in order not to obscure the illustrative implementations.

Further, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present appended claims.

The drawings are intended to show relative arrangements of the elements therein, and the device assemblies of these figures may include other elements that are not specifically illustrated (e.g., various interfacial layers). Similarly, although particular arrangements of materials are discussed with reference to the drawings, intermediate materials may be included in the devices and assemblies of these drawings. Still further, although some elements of the various device views are illustrated in the drawings as being planar rectangles or formed of rectangular solids and although some schematic illustrations of example structures are shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so "ideal" when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., physical failure analysis (PFA) would allow determination of presence of one or more transistor arrangements fabricated using a placeholder for backside contact formation as described herein.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed or described operations may be omitted in additional embodiments.

For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.

The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. The terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side" to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

For example, some descriptions may refer to a particular source or drain region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because under certain operating conditions, designations of source and drain are often interchangeable. Therefore, descriptions provided herein may use the term of a "S/D region/contact" to indicate that the region/contact can be either a source region/contact, or a drain region/contact.

In another example, if used, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die," the term "insulating" means "electrically insulating," the term "conducting" means "electrically conducting," unless otherwise specified. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, "an electrically conductive material" may include one or more electrically conductive materials.

In another example, if used, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

In yet another example, the term "connected" may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term "coupled" may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>-<NUM>% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between the elements, generally refer to being within +/- <NUM>-<NUM>% of a target value based on the context of a particular value as described herein or as known in the art.

In addition, the terms "comprise," "comprising," "include," "including," "have," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, process, device, or system that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such method, process, device, or system. Also, the term "or" refers to an inclusive "or" and not to an exclusive "or.

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

<FIG> illustrates a triblock copolymer in lamellar phase, in accordance with some embodiments. The triblock copolymer in lamellar phase is also referred to as a lamellar triblock copolymer. The lamellar triblock copolymer can be used to rectify via openings (such as contact holes) through DSA based on graphoepitaxy, chemoepitaxy, or mixed epitaxy. <FIG> shows a molecule <NUM> of the triblock copolymer ("triblock copolymer molecule <NUM>"), in accordance with some embodiments. <FIG> shows a lamellar structure <NUM> of the triblock copolymer, in accordance with some embodiments.

The triblock copolymer molecule <NUM> is a polymeric molecule formed of a chain of covalently bonded monomers. In the triblock copolymer, there are at least two different types of monomers, and these different types of monomers are primarily included within different blocks or contiguous sequences of monomers. As shown in <FIG>, the triblock copolymer molecule <NUM> includes two blocks of polymer A <NUM> and a block of polymer B <NUM>. The block of polymer B <NUM> is between the two blocks of polymer A <NUM>. The block of polymer A <NUM> and the block of polymer B <NUM> are covalently bonded together. The block of polymer A and the block of polymer B may be of approximately equal length, or one block may be significantly longer than the other. An individual block of polymer A <NUM> includes predominantly a chain of covalently linked monomer A (e.g., A-A-A-A-A. ), whereas the block of polymer B <NUM> includes predominantly a chain of covalently linked monomer B (e.g., B-B-B-B-B. The monomers A and B may represent any of the different types of monomers used in block copolymers known in the arts. Examples of the polymer A <NUM> and polymer B <NUM> include polyethylene, polystyrene, polyvinylchloride, polytetrafluorethylene, polydimethylsiloxane, some polyesters, some polyurethanes, acrylics, epoxies, P(t-Buytl Acrylate), polyacrylic acid, polyacrylamide, maleic anhydride polymers, polyethylene, polypropylene, polyacrylonitrile, polybutadiene, polyvinyl acetate, polyacetic acid, polybutyl acrylate, polylactic acid, polycaprolactone, poly(ethylene glycol), polyisoprene, and so on. In other embodiments, the polymer A <NUM> or polymer B <NUM> may be other polymers.

Even though the triblock copolymer molecule <NUM> in <FIG> includes two blocks of polymer A <NUM> and a block of polymer B <NUM>, other embodiments of the triblock copolymer molecule <NUM> may include a block of polymer A <NUM>, a block of polymer B <NUM>, and a block of polymer C, with the block of polymer B <NUM> between the block of polymer A <NUM> and the block of polymer C. Polymer C is a different polymer from polymer A <NUM> and polymer B <NUM>. Also, an individual block may include different types of monomers. For example, the individual block may itself be a copolymer of two or more types of monomers.

In some embodiments, the block of polymer A <NUM> and the block of polymer B <NUM> have different chemical properties. As one example, one of the blocks may be relatively more hydrophobic (e.g., water disliking) and the other may be relatively more hydrophilic (water liking). As another example, one of the blocks may be relatively more similar to oil and the other block may be relatively more similar to water. Such differences in chemical properties between the different blocks of polymers, whether a hydrophilic-hydrophobic difference or otherwise, may cause the triblock copolymer molecule <NUM> to self-assemble. For example, the self-assembly may be based on microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water which are generally immiscible. Similarly, differences in hydrophilicity between the polymer blocks (e.g., one block is relatively hydrophobic and the other block is relatively hydrophilic), may cause a roughly analogous microphase separation where the different polymer blocks try to separate from each other due to chemical dislike for the other.

However, because the polymer blocks are covalently bonded to one another, they cannot be completely separated on a macroscopic scale. Rather, polymer blocks of a given type may tend to segregate or conglomerate with polymer blocks of the same type of other molecules. Self-assembly of the triblock copolymer molecule <NUM>, whether based on hydrophobic-hydrophilic differences or otherwise, may be used to form extremely small periodic structures (e.g., precisely spaced nanoscale structures). In some embodiments, the triblock copolymer is used to form nanoscale lamellar structures (e.g., a lamellar structure including three lamellae formed from the three polymer blocks) or other nanoscale structures that can be used to rectify via openings. The dimensions of the lamellae are dependent at least in part upon the lengths of the polymer blocks. The triblock copolymer may self-assemble into nanostructures of other shapes, such as hexagonally packed cylinders, body-centered cubic spheres, etc..

In the embodiment of <FIG>, self-assembly of the triblock copolymer molecule <NUM> forms a lamellar structure <NUM>. As will be explained further below, the lamellar structure <NUM> may be formed by using graphoepitaxy, chemoepitaxy, or mixed epitaxy. The lamellar structure <NUM> includes two polymer A lamellae <NUM> and <NUM> and a polymer B lamella <NUM>. The polymer B lamella <NUM> is between the two polymer A lamellae <NUM> and <NUM>. The lamellar structure <NUM> may be formed in via openings of an IC device to rectify the via openings. The polymer B lamella <NUM> can be removed to form the rectified via openings in the IC device. Accordingly, the dimensions of the polymer B lamella <NUM> at least partially define the dimensions of the via openings.

In some embodiments, polymer A <NUM> and polymer B <NUM> have different mechanical properties. For example, polymer A <NUM> are more rigid than polymer B <NUM>. Accordingly, the polymer A lamellae <NUM> and <NUM> are more rigid than the polymer B lamella <NUM>. In an embodiment, the polymer A lamellae <NUM> and <NUM> of the lamellar structure <NUM> has a rigidity above a first threshold and the polymer B lamella <NUM> has a rigidity below a second threshold that is lower than the first threshold. As polymer B <NUM> is more flexible, the block of polymer B <NUM> can be more easily stretched or compressed between the blocks of polymer A <NUM> when the triblock copolymer molecule <NUM> forms the lamellar structure <NUM>. In an embodiment, the block of polymer B <NUM> folds onto itself during the self-assembly of the triblock copolymer molecule <NUM>. The higher rigidity of the polymer A lamellae <NUM> and <NUM> help ensure a uniform size of the polymer B lamella <NUM> and consequently, help ensure a uniform size of the rectified via openings. Also, as the polymer B lamella <NUM> is relatively flexible, the polymer B lamella <NUM> can be removed through an etching process that does not or barely etch the polymer A lamellae <NUM> and <NUM>, which further ensures a uniform size of the rectified via openings. Therefore, compared with the method of rectifying via openings with cylindrical deblock copolymer, via opening rectification using lamellar triblock copolymer provides better CDU.

In some embodiments, the lamellar structure <NUM> is formed on a surface of a layer <NUM>. As shown in <FIG>, the lamellar structure <NUM> has an orientation along the Y axis, which is perpendicular to the surface of the layer <NUM>. The layer <NUM> may be a semiconductor substrate. In some embodiments, the layer <NUM> includes a grating pattern, e.g., an alternative pattern of first sections and second sections. The first sections include a different material from the second section. The lamellar structure <NUM> may be formed in accordance with the grating pattern. More details regarding forming lamellar structure in accordance with a grating pattern is described below in conjunction with <FIG>.

<FIG> illustrate a process of forming via openings <NUM> by using graphoepitaxy-based DSA of a lamella triblock copolymer, in accordance with some embodiments. An embodiment of the lamella triblock copolymer is the lamellar triblock copolymer described above in conjunction with <FIG>.

<FIG> shows an IC device <NUM> that includes an intermediate layer <NUM> over (e.g., attached on) a substrate <NUM>. The substrate <NUM> may include a semiconductor material. Examples of the semiconductor material include, for example, single crystal silicon, polycrystalline silicon, silicon on insulator (SOI), other suitable semiconductor material, or some combination thereof. The substrate <NUM> may also include other materials, such as metal, dielectric, dopant, and so on. In some embodiments, the substrate <NUM> may include various IC components, such as transistors, etc. In some embodiments, the substrate <NUM> is a general workpiece object used to manufacture integrated circuits.

The intermediate layer <NUM> may include a dielectric or insulating material. Examples of the dielectric material include, for example, oxides of silicon (e.g., silicon dioxide (SiO)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The dielectric layer may be formed by conventional techniques, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or by other deposition methods. In an embodiment, the intermediate layer <NUM> includes a grating pattern that guides self-assembly of the lamellar triblock copolymer. More information regarding the grating pattern is described below in conjunction with <FIG>.

<FIG> shows an IC device <NUM>. The IC device <NUM> is fabricated by forming a guiding pattern layer <NUM> on the IC device <NUM>, e.g., on a surface of the intermediate layer <NUM>. The guiding pattern layer <NUM> includes a topographical guiding pattern. The topographical guiding pattern directs self-assembly of the lamellar triblock copolymer. In some embodiments, the topographical guiding pattern directs self-assembly of the lamellar triblock copolymer through mechanisms such as commensurability, lateral ordering, confinement effects, etc..

In <FIG>, the topographical guiding pattern is an alternative pattern of openings <NUM> (individually referred to as "opening <NUM>") and guiding walls <NUM> (individually referred to as "guiding wall <NUM>"). Each opening <NUM> is between two guiding walls <NUM> that defines the opening <NUM>. The guiding pattern layer <NUM> can be formed by using various lithography technologies, such as EUV, immersion lithography (e.g., by using ultraviolet (UV) light at <NUM> wavelength), deep UV lithography (e.g., dry <NUM> photolithography), and so on. An opening <NUM> may be a via opening. However, due to the technical challenges of the lithographical technologies that are described above, the via openings lack sufficient CDU. The sizes of the via openings may vary more significantly than desired. Therefore, the via openings need to be rectified, e.g., through DSA of the lamellar triblock copolymer.

In some embodiments, the guiding pattern layer <NUM> may be physically tailored or chemically modified to impose different affinity to different polymer blocks of the lamellar triblock copolymer to enforce the orientation of the lamellar triblock copolymer, which is perpendicular to the intermediate layer <NUM>. In other embodiments, a surface treatment may be performed to modify the guiding pattern layer <NUM>. The surface treatment may make portions of the guiding pattern layer <NUM> (e.g., surfaces of the openings <NUM>) chemically neutral, or at least relatively more neutral, to different polymer blocks of the triblock copolymer. A non-neutral surface may have a greater interaction tendency (e.g., repulsive or attractive) with one polymer block than with another, then the non-neutral surface would tend to influence the self-assembly of the triblock copolymer in a way that may not be desired. In some embodiments, the surface treatment may be an application of a coating having a chemical property (e.g., a hydrophilic/hydrophobic property) that is intermediate between the different polymer blocks of the triblock copolymer. In some embodiments, the coating may be applied by spin coating, spray coating, dipping coating, immersion coating, or otherwise depositing or applying a relatively thin coating of a material that has a chemical property (e.g., a hydrophilicity) that is approximately between corresponding chemical properties of the different polymer blocks. An example material of the coating is a copolymer that has alternating monomers of the different block copolymers. For example, for a triblock copolymer including blocks of polymer A and a block of polymer B, the coating may include a copolymer of A and B where the monomers A and B are highly mixed within the copolymer (e.g., A-B-A-B-A-B-AB-A-B, A-A-B-B-B-A-B-B-A-A-A, etc.). Additionally or alternatively, other types of surface treatments (e.g., oxidizing or de-oxidizing) may be used to modify the guiding pattern layer <NUM>.

<FIG> shows an IC device <NUM> formed by filling the openings <NUM> of the IC device <NUM> with the lamellar triblock copolymer. In some embodiments, the openings <NUM> are filled with melts of the triblock copolymer. The triblock copolymer self-assembles, e.g., through microphase separation of the three blocks in the triblock copolymer, as directed by the guiding pattern and forms the lamellar triblock copolymer. In an embodiment, the self-assembly of the triblock copolymer occurs through rearrangement or repositioning of the different polymer blocks of the triblock copolymer molecules. The self-assembly of the triblock copolymer is directed by the topographical guiding pattern. In an embodiment, the self-assembly of the triblock copolymer may be drive by surface force, e.g., tension, applied by the guiding walls <NUM>. During the self-assembly process, the lamellar structure <NUM> is aligned relative to the guiding walls <NUM>, which achieves a better alignment compared with lithographical alignment and therefore, can be used to form very small via openings (e.g., nanoscale).

In some embodiments, an annealing treatment may be applied to the triblock copolymer in order to initiate, accelerate, or otherwise promote the self-assembly. In some embodiments, the annealing treatment may be a solvent annealing treatment that happens in an atmosphere of solvent vapor. The solvent vapor may be a vapor of acetone, tetrahydrofuran, or other types of organic solvent. The solvent annealing treatment can propose diffusion and self-assembly kinetics of larger polymers, such as triblock copolymers. In other embodiments, the annealing treatment may include a treatment that is operable to increase a temperature of the triblock copolymer. One example of such a treatment is heating the IC device <NUM> (e.g., in an oven or under a thermal lamp), applying infrared radiation to the triblock copolymer, or otherwise applying heat to or increasing the temperature of the triblock copolymer. The heating may help to provide energy to the molecules of the triblock copolymer molecules to make them more mobile/flexible in order to increase the rate of the microphase separation. The annealing is performed at a temperature that is high enough to increase the rate of microphase separation but low enough to avoid damaging the triblock copolymer or other components of the IC device <NUM>. In some embodiments, the annealing temperature is in a range from <NUM> to <NUM>.

As shown in <FIG>, lamellar structures <NUM> (individually referred to as "lamellar structure <NUM>") have filled the openings <NUM> and are present between the guiding walls <NUM>. An embodiment of a lamellar structure <NUM> is the lamellar structure <NUM> in <FIG>. In the embodiment of <FIG>, an individual opening <NUM> is filled with one triblock copolymer molecule, e.g., the triblock copolymer molecule <NUM> in <FIG>, that forms one lamellar structure <NUM>. In other embodiments, an individual opening <NUM> may be filled with multiple triblock copolymer molecules that form multiple lamellar structures.

The lamellar structure <NUM> includes a first lamella <NUM>, a second lamella <NUM>, and a third lamella <NUM>, which are formed from the three blocks of the triblock copolymer. The second lamella <NUM> is between the first and third lamellae <NUM> and <NUM> and has a different polymer from the first and third lamellae <NUM> and <NUM>. An embodiment of the first lamella <NUM> is the polymer A lamella <NUM> in <FIG>. An embodiment of the second lamella <NUM> is the polymer B lamella <NUM> in <FIG>. An embodiment of the third lamella <NUM> is the polymer A lamella <NUM> in <FIG>. Other embodiments of the lamellar structure <NUM> may include different lamellae. For instance, the first lamella <NUM> may include a different polymer from the third lamella <NUM>. The first, second, and third lamellae <NUM>, <NUM>, and <NUM> elongates along the Y axis as shown in <FIG>, which is perpendicular to the intermediate layer <NUM>. In <FIG>, the length of the lamellar structure <NUM> along the Y axis is smaller than the length of the openings <NUM>. In other embodiments, the length of the lamellar structure <NUM> may be the same as the length of the openings <NUM>. The first, second, and third lamellae <NUM>, <NUM>, and <NUM> may have a same or different widths along the X or Z axis.

The self-assembly of the triblock copolymer molecule may cause the lamellar structure <NUM> to be substantially centered in the corresponding opening <NUM>, e.g., in the X dimension and Z dimension. Dimensions (such as a width along the X axis or a length along the Z axis) of the first lamella <NUM>, second lamella <NUM>, or third lamella <NUM> may be based at least in part upon the length of the corresponding block of the triblock copolymer. In embodiments where the polymer blocks for the first and third lamellae <NUM> and <NUM> have same or similar lengths, the second lamella <NUM> can be located at the center, or close to the center, of the opening <NUM>. In various embodiments, the first and third lamellae <NUM> and <NUM> are more rigid than the second lamella <NUM> and can define a space where the second lamella <NUM> is formed. In an embodiment where the space is big, the polymer block forming the second lamella <NUM> may stretch to fill up the space. In another embodiment where the space is small, the polymer block forming the second lamella <NUM> may be compressed to fit in the space. For example, the polymer block forming the second lamella <NUM> may fold onto itself to fit in the space. By using such a triblock copolymer, the dimensions of the second lamella <NUM> can be controlled by controlling the length of the polymer blocks forming the first and third lamellae <NUM>.

<FIG> shows an IC device <NUM> including a via opening layer <NUM>, in which via openings <NUM> (individually referred to as "via opening <NUM>") are formed. A via opening <NUM> is formed by removing the second lamella <NUM> from the corresponding lamellar structure <NUM>. The via opening <NUM> is defined by one or more the via opening walls <NUM> (individually referred to as "via opening wall <NUM>") and the guiding wall <NUM>. The via opening walls <NUM> include the first and third lamellae <NUM> and <NUM> of the corresponding lamellar structure <NUM> and one or more portions of the guiding wall <NUM>.

In some embodiments, the second lamella <NUM> is removed by performing an etching process (e.g., a selective etching process) on the lamellar structures <NUM>. The second lamella <NUM> is etched at a higher rate than the first and third lamellae <NUM> and <NUM>. The first and third lamellae <NUM> and <NUM> remain completely or substantially unetched after the etching process. In an embodiment, the etching process includes an isotropic chemically selective etch. In another embodiment, the etching process includes placing a hard mask on top of the lamellar structure <NUM>. The hard mask includes a hole corresponding to the second lamella <NUM> so that the second lamella <NUM> is exposed to the etching but the first and third lamellae <NUM> and <NUM> are not exposed. The higher rigidity of the first and third lamellae <NUM> and <NUM> also helps to eliminate or reduce etching of the first and third lamellae <NUM> and <NUM>.

In some embodiments, the ratio of the length of the lamellar structures <NUM> along the Y axis to the length of the via openings <NUM> along the Y axis is in a range from <NUM> to <NUM>. In an embodiment, the ratio of the length of the lamellar structures <NUM> to the length of the via openings <NUM> is in a range from <NUM> to <NUM>. The embodiment of <FIG> removes the second lamella <NUM> from all the lamellar structures <NUM>. In other embodiments, the second lamella <NUM> is removed from a subset of the lamellar structures <NUM>. <FIG> shows removal of the whole second lamella <NUM>. In other embodiments, a via opening <NUM> may be formed by removing a portion of the second lamella <NUM>. As shown in <FIG>, the via openings <NUM> have rectangular cross-sections. In other embodiments, the cross-sections of the via openings <NUM> can have other shapes, e.g., square, a curved shape, etc..

<FIG> shows a top view of an IC device <NUM> including vias <NUM>. In some embodiments, a via opening <NUM> is partially or completed filled with an electrically conductive material, such as a metal or an alloy, to form the corresponding via <NUM>. A via <NUM> can be a through via, blind via, or buried via. the ratio of the length of the lamellar structures <NUM> along the Y axis to the length of the via <NUM> along the Y axis may be in a range from <NUM> to <NUM>.

<FIG> illustrate a polymer nanocomposite, nanocomposite not forming part of the invention, in accordance with some embodiments. <FIG> shows a molecule <NUM> of the polymer nanocomposite ("polymer nanocomposite molecule <NUM>"). The polymer nanocomposite molecule <NUM> includes a polymer <NUM> surrounding a nanoparticle <NUM> in the X and Y dimensions. One or more chains of the polymer <NUM> are attached on the nanoparticle <NUM>. The polymer <NUM> may be polyethylene, polystyrene, polyvinylchloride, polytetrafluorethylene, polydimethylsiloxane, some polyesters, some polyurethanes, acrylics, epoxies, P(t-Buytl Acrylate), polyacrylic acid, polyacrylamide, maleic anhydride polymers, polyethylene, polypropylene, polyacrylonitrile, polybutadiene, polyvinyl acetate, polyacetic acid, polybutyl acrylate, polylactic acid, polycaprolactone, poly(ethylene glycol), polyisoprene, and so on. The nanoparticle <NUM> has a nanoscale size. For example, the size of the nanoparticle <NUM> in the X, Y, or Z dimension is in a range from <NUM> to <NUM> nanometers. The nanoparticle <NUM> may be made from an inorganic material. Example materials of the nanoparticle <NUM> include SiO<NUM>, Ag, Au, CdSe, Fe<NUM>O<NUM>, graphene, TiOx, SnOx, ZrOx, silsesquioxanes, and so on.

<FIG> shows a cylindrical structure <NUM> formed by the polymer nanocomposite molecule <NUM> on a surface of a layer <NUM>. In other embodiments, the cylindrical structure <NUM> may be formed by multiple polymer nanocomposite molecules <NUM>. The cylindrical structure <NUM> elongates along the Y axis, which is perpendicular to the surface of the layer <NUM>. The cylindrical structure <NUM> includes a polymer cylinder <NUM> formed from the polymer <NUM> and a nanoparticle cylinder <NUM> formed from the nanoparticle <NUM>. The polymer cylinder <NUM> is hollow and encloses the nanoparticle cylinder <NUM> in the X dimension and Y dimension. Accordingly, the inner diameter of the polymer cylinder <NUM> is the same as the diameter of the nanoparticle cylinder <NUM>, and the outer diameter of the polymer cylinder <NUM> is larger than the diameter of the nanoparticle cylinder <NUM>. A length of the polymer cylinder <NUM> along the Z axis is the same as the length of the nanoparticle cylinder <NUM> along the Z axis. In other embodiments, the length of the polymer cylinder <NUM> may be shorter or longer than the length of the nanoparticle cylinder <NUM>.

The layer <NUM> may be a semiconductor substrate. In some embodiments, the layer <NUM> includes a grating pattern, e.g., an alternative pattern of first sections and second sections. The first sections include a different material from the second section. The cylindrical structure <NUM> may be formed in accordance with the grating pattern.

<FIG> illustrate a process of forming via openings <NUM> by using the polymer nanocomposite not forming part of the invention, in accordance with some embodiments. <FIG> shows an IC device <NUM>. The IC device <NUM> includes a substrate <NUM>, an intermediate layer <NUM> over (e.g., attached on) the substrate <NUM>, and a guiding pattern layer <NUM> over the intermediate layer <NUM>. In other embodiments, the IC device <NUM> may include different components. For instance, the IC device <NUM> may not include the intermediate layer <NUM> and the guiding pattern layer <NUM> is formed on the substrate <NUM>.

The substrate <NUM> may include a semiconductor material. Examples of the semiconductor material include, for example, single crystal silicon, polycrystalline silicon, SOI, other suitable semiconductor material, or some combination thereof. The substrate <NUM> may also include other materials, such as metal, dielectric, dopant, and so on. In some embodiments, the substrate <NUM> may include various IC components, such as transistors, etc. In some embodiments, the substrate <NUM> is a general workpiece object used to manufacture integrated circuits.

The intermediate layer <NUM> includes a dielectric or insulating material. Examples of the dielectric material include, for example, oxides of silicon (e.g., silicon dioxide (SiO)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The dielectric layer may be formed by conventional techniques, such as, for example, CVD, plasma enhanced CVD, PVD, ALD (atomic layer deposition), plasma enhanced ALD, spinning on, annealing, or by other deposition methods. In an embodiment, the intermediate layer <NUM> includes a grating pattern that guides self-assembly of the lamellar triblock copolymer.

The guiding pattern layer <NUM> includes a topographical guiding pattern. In <FIG>, the topographical guiding pattern is an alternative pattern of guiding walls <NUM> (individually referred to as "guiding wall <NUM>") and openings <NUM> (individually referred to as "opening <NUM>"). Each opening <NUM> is between two guiding walls <NUM> that defines the opening <NUM>. In some embodiments, the guiding pattern layer <NUM> is formed by using EUV, immersion lithography (e.g., by using UV light at <NUM> wavelength), deep UV lithography (e.g., dry <NUM> photolithography), other types of lithography techniques. The topographical guiding pattern is three-dimensional.

<FIG> shows an IC device <NUM> formed by filling the openings <NUM> of the IC device <NUM> with cylindrical structures <NUM> (individually referred to as "cylindrical structure <NUM>"). An embodiment of the cylindrical structure <NUM> is the cylindrical structure <NUM> in <FIG> As shown in <FIG>, the cylindrical structure <NUM> is present between the guiding walls <NUM>. The cylindrical structures <NUM> are formed by applying a polymer nanocomposite on the guiding pattern layer <NUM>, e.g., into the openings <NUM> of the guiding pattern layer <NUM>.

A cylindrical structure <NUM> is formed from a polymer nanocomposite molecule, e.g., the polymer nanocomposite molecule <NUM> in <FIG>. The cylindrical structure <NUM> includes a polymer cylinder <NUM> and a nanoparticle cylinder <NUM>. The polymer cylinder <NUM> is hollow and at least partially encloses the nanoparticle cylinder <NUM> in the X dimension and Z dimension. In an embodiment, the polymer cylinder <NUM> is formed by the polymer <NUM> in <FIG> and the nanoparticle cylinder <NUM> is formed by the nanoparticle <NUM>. The cylindrical structure <NUM> elongates along the Y axis as shown in <FIG>, which is perpendicular to the intermediate layer <NUM>. In <FIG>, the length of the cylindrical structure <NUM> along the Y axis is smaller than the length of the openings <NUM>. In other embodiments, the length of the cylindrical structure <NUM> may be the same as the length of the openings <NUM>. The polymer cylinder <NUM> may expand or contract to occupy the space inside the via opening as efficiently as possible.

The topographical guiding pattern in the guiding pattern layer <NUM> directs the polymer nanocomposite molecules to form the cylindrical structures <NUM>. In some embodiments, the topographical guiding pattern directs formation of the cylindrical structures <NUM> through mechanisms such as commensurability, lateral ordering, confinement effects, etc. The formation of the cylindrical structures <NUM> may be drive by surface force, e.g., tension, applied by the guiding walls <NUM>. During the formation process, the cylindrical structures <NUM> are aligned relative to the guiding walls <NUM>, which achieves a better alignment compared with lithographical alignment and therefore, can be used to form very small via openings (e.g., nanoscale). Also, as the nanoparticle is surrounded by the polymer (e.g., as shown in <FIG>), the nanoparticle cylinder <NUM> can be centered or substantially centered in the corresponding opening <NUM>, e.g., in the X dimension and Z dimension. The dimensions (e.g., outer diameter or length) of the polymer cylinder <NUM> may be based at least in part upon the relative length of the chain of the polymer forming the polymer cylinder <NUM>. The dimensions (e.g., diameter or length) of the nanoparticle cylinder <NUM> may be based at least in part upon the dimensions of the nanoparticle forming the nanoparticle cylinder <NUM>. The polymer in the polymer nanocomposite molecule may be designed so that diameters of the polymer cylinder <NUM> and the nanoparticle cylinder <NUM> as well as the pitch of the polymer cylinder <NUM> and the nanoparticle cylinder <NUM> (center-to-center spacing between closest adjacent cylindrical structures <NUM>) is appropriate for the predetermined pitch.

In some embodiments, an annealing treatment may be applied to the cylindrical structure <NUM> in order to initiate, accelerate, or otherwise promote the formation of the polymer cylinders <NUM> or nanoparticle cylinders <NUM>. In some embodiments, the annealing treatment may be a solvent annealing treatment that happens in an atmosphere of solvent vapor. The solvent vapor may be a vapor of acetone, tetrahydrofuran, or other types of organic solvent. The solvent annealing treatment can propose diffusion and self-assembly kinetics of larger polymers, such as triblock copolymers. In other embodiments, the annealing treatment may include a treatment that is operable to increase a temperature of the cylindrical structure <NUM>. One example of such a treatment is heating the IC device <NUM> (e.g., in an oven or under a thermal lamp), applying infrared radiation to the cylindrical structure <NUM>, or otherwise applying heat to or increasing the temperature of the cylindrical structure <NUM>. The annealing is performed at a temperature that is high enough to increase the rate of self-assembly but low enough to avoid damaging the cylindrical structure <NUM> or other components of the IC device <NUM>.

In some embodiments, the guiding pattern layer <NUM> may be physically tailored or chemically modified to impose different affinity to the polymer and nanoparticle in the polymer nanocomposite to enforce the orientation of the polymer cylinders <NUM> and nanoparticle cylinders <NUM>, which is perpendicular to the intermediate layer <NUM>. In other embodiments, a surface treatment may be performed to modify the guiding pattern layer <NUM>. The surface treatment may make portions of the guiding pattern layer <NUM> (e.g., surfaces of the openings <NUM>) chemically neutral, or at least relatively more neutral, to the polymer and nanoparticle. A non-neutral surface may have a greater interaction tendency (e.g., repulsive or attractive) with the polymer than the nanocomposite, then the non-neutral surface would tend to influence the formation of the cylindrical structure <NUM> in a way that may not be desired. In some embodiments, the surface treatment may be an application of a coating having a chemical property (e.g., a hydrophilic/hydrophobic property) that is intermediate between the polymer and nanocomposite. In some embodiments, the coating may be applied by spin coating, spray coating, dipping coating, immersion coating, or otherwise depositing or applying a relatively thin coating of a material that has a chemical property (e.g., a hydrophilicity) that is approximately between corresponding chemical properties of the polymer and nanocomposite. Additionally or alternatively, other types of surface treatments (e.g., oxidizing or de-oxidizing) may be used to modify the guiding pattern layer <NUM>.

<FIG> shows an IC device <NUM> including a via opening layer <NUM>, in which via openings <NUM> (individually referred to as "via opening <NUM>") are formed. <FIG> shows a top view of the IC device <NUM>. A via opening <NUM> is formed by removing the nanoparticle cylinder <NUM> from the cylindrical structure <NUM>. The via opening <NUM> is defined by the corresponding via opening wall <NUM>. The via opening wall <NUM> is the polymer cylinder <NUM>. The embodiment of <FIG> removes the nanoparticle cylinder <NUM> from all the cylindrical structures <NUM>. In other embodiments, the nanoparticle cylinder <NUM> is removed from a subset of the cylindrical structures <NUM>. <FIG> shows removal of the whole nanoparticle cylinder <NUM>. In other embodiments, a via opening <NUM> may be formed by removing a portion of the nanoparticle cylinder <NUM>. In some embodiments, the ratio of the length of the cylindrical structures <NUM> along the Y axis to the length of the via openings <NUM> along the Y axis is in a range from <NUM> to <NUM>. In some embodiments, some or all of the via openings <NUM> may be partially or completely filled with an electrically conductive material to form vias.

In some embodiments, the nanoparticle cylinder <NUM> is removed by performing an etching process (e.g., a selective etching process) on the cylindrical structures <NUM>. The nanoparticle cylinder <NUM> is etched at a higher rate than the polymer cylinder <NUM>. The polymer cylinder <NUM> may remain substantially unetched after the etching process. In an embodiment, the etching process includes an isotropic chemically selective etch. As shown in <FIG>, the via openings <NUM> have circular cross-sections. In other embodiments, the cross-sections of the via openings <NUM> can have other shapes, e.g., square, rectangular, etc..

<FIG> illustrates a process of forming via openings <NUM> by using chemoepitaxy, in accordance with some embodiments. The via opening formation may use a triblock copolymer (e.g., the triblock copolymer described above in conjunction with <FIG>) or a polymer nanocomposite (e.g., the polymer nanocomposite described above in conjunction with <FIG>).

<FIG> shows an IC device <NUM> that includes an intermediate layer <NUM> over a substrate <NUM>. The substrate <NUM> may include a semiconductor material. Examples of the semiconductor material include, for example, single crystal silicon, polycrystalline silicon, SOI, other suitable semiconductor material, or some combination thereof. The substrate <NUM> may also include other materials, such as metal, dielectric, dopant, and so on. In some embodiments, the substrate <NUM> may include various IC components, such as transistors, etc. In some embodiments, the substrate <NUM> is a general workpiece object used to manufacture integrated circuits.

The intermediate layer <NUM> includes a dielectric or insulating material. Examples of the dielectric material include, for example, oxides of silicon (e.g., silicon dioxide (SiO)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The dielectric layer may be formed by conventional techniques, such as, for example, CVD, PVD, or by other deposition methods. In an embodiment, the intermediate layer <NUM> includes a grating pattern that guides self-assembly of the lamellar triblock copolymer.

<FIG> shows an IC device <NUM>. The IC device <NUM> is formed by generating a guiding pattern layer <NUM> on the IC device <NUM>, e.g., on a surface of the intermediate layer <NUM>. The guiding pattern layer <NUM> includes a chemical guiding pattern. In <FIG>, the chemical guiding pattern is an alternative pattern of first sections <NUM> (individually referred to as "first section <NUM>") and second sections <NUM> (individually referred to as "second section <NUM>"). Each second section <NUM> is between two first sections <NUM> that defines the second section <NUM>. The first sections <NUM> have different chemical properties from the second sections <NUM>. In embodiments where a triblock copolymer is used, the first section <NUM> or second section <NUM> has different chemical affinity to different polymer blocks of the triblock copolymer to enforce the orientation of the lamellar triblock copolymer, which is perpendicular to the intermediate layer <NUM>. In embodiments where the polymer nanocomposite is used, the first section <NUM> or second section <NUM> has different chemical affinity to the polymer and the nanocomposite in the polymer nanocomposite. Accordingly, the chemical guiding pattern can guide self-assembly of the triblock copolymer and the polymer nanocomposite. In an embodiment, the first sections <NUM> include a different material from the second sections <NUM>.

<FIG> shows an IC device <NUM> generated by forming a repetitive structure layer <NUM> over the guiding pattern layer <NUM>. The repetitive structure layer <NUM> includes a plurality of structures <NUM> (individually referred to as "structure <NUM>"). A structure <NUM> includes a first element <NUM> and second element <NUM>, with the second material being at least partially enclosed by the first element <NUM>. The structures <NUM> may be formed by applying a triblock copolymer or a polymer nanocomposite on the guiding pattern layer <NUM>.

In some embodiments, the repetitive structure layer <NUM> is formed by using the triblock copolymer. A structure <NUM> is a lamellar structure, e.g., the lamellar structure <NUM> in <FIG>. The first element <NUM> includes two lamellae of the lamellar structure, e.g., the polymer A lamellae <NUM> and <NUM> in <FIG>. The second element <NUM> may be the polymer B lamella <NUM> in <FIG>. In an embodiment, the triblock copolymer is deposited on the guiding pattern layer <NUM>. The chemical guiding pattern of the guiding pattern layer <NUM> guides microphase separation of the triblock copolymer. In an embodiment, the second section <NUM> (or the first section <NUM>) of the guiding pattern layer <NUM> has a differentiated chemical affinity to different polymers in the triblock copolymer. For example, the second section <NUM> has a stronger chemical affinity to polymer A than polymer B. Accordingly, lamellae of polymer A will be formed over the second sections <NUM> at a rate faster than lamellae of polymer B. Accordingly, the triblock copolymer self-assembles and forms lamellar structures based on the chemical guiding pattern. The self-assembly of the triblock copolymer is drive by the differentiated chemical affinity of the second sections <NUM>. During the self-assembly process, the lamellar structures are aligned relative to the second sections <NUM>, which achieves a better alignment compared with lithographical alignment and therefore, can be used to form very small via openings (e.g., nanoscale). In some embodiments, an annealing treatment may be applied to the triblock copolymer in order to initiate, accelerate, or otherwise promote the self-assembly. The annealing treatment may include a treatment that is operable to increase a temperature of the triblock copolymer. The annealing is performed at a temperature that is high enough to increase the rate of microphase separation but low enough to avoid damaging the triblock copolymer or other components of the IC device <NUM>.

In other embodiments, the repetitive structure layer <NUM> may be formed by using the polymer nanocomposite. A structure <NUM> is a cylindrical structure, e.g., the cylindrical structure <NUM> in <FIG>. The first element <NUM> may be the polymer cylinder <NUM> and the second element <NUM> may be the nanoparticle cylinder <NUM> in <FIG>. The chemical guiding pattern of the guiding pattern layer <NUM> guides the formation of the cylindrical structures. In an embodiment, the second section <NUM> (or the first section <NUM>) of the guiding pattern layer <NUM> has a differentiated chemical affinity to the polymer and nanoparticle in the polymer nanocomposite. For example, the second section <NUM> has a stronger chemical affinity to the polymer than the nanoparticle. Accordingly, polymer cylinders will be formed over the second sections <NUM> at a rate faster than nanoparticle cylinders. The cylindrical structures are aligned relative to the second sections <NUM>, which achieves a better alignment compared with lithographical alignment and therefore, can be used to form very small via openings (e.g., nanoscale). In some embodiments, an annealing treatment may be applied to the polymer nanocomposite in order to initiate, accelerate, or otherwise promote the formation of the cylindrical structures. The annealing treatment may include a treatment that is operable to increase a temperature of the polymer nanocomposite.

<FIG> shows an IC device <NUM> including a via opening layer <NUM>, in which via openings <NUM> (individually referred to as "via opening <NUM>") are formed. A via opening <NUM> is formed by removing the second element <NUM> from a structure <NUM>. The via openings <NUM> are defined by the corresponding via opening wall <NUM>. The via opening wall <NUM> includes the first element <NUM> of the structure <NUM>. The embodiment of <FIG> removes the second element <NUM> from all the structures <NUM>. In other embodiments, the second element <NUM> is removed from a subset of the structures <NUM>. <FIG> shows removal of the whole second element <NUM>. In other embodiments, a via opening <NUM> may be formed by removing a portion of the second element <NUM>. In some embodiments, the ratio of the length of the structures <NUM> along the Y axis to the length of the via openings <NUM> along the Y axis is in a range from <NUM> to <NUM>. In some embodiments, some or all of the via openings <NUM> may be partially or completely filled with an electrically conductive material to form vias.

In some embodiments, the second element <NUM> is removed by performing an etching process (e.g., a selective etching process) on the repetitive structure layer <NUM>. The second element <NUM> is etched at a higher rate than the first element <NUM>. The first element 1430may remain substantially unetched after the etching process. In an embodiment, the etching process includes an isotropic chemically selective etch.

<FIG> illustrates a process of forming via openings <NUM> based on a grating pattern of a grating layer <NUM>, in accordance with some embodiments. <FIG> is a perspective view of the grating layer <NUM>. The grating layer <NUM> includes first grating sections <NUM> (individually referred to as "first grating section <NUM>") and second grating sections <NUM> (individually referred to as "second grating section <NUM>"). The first grating sections <NUM> and second grating sections <NUM> form a grating pattern, which is an alternative pattern. For instance, each second grating section <NUM> is between two first grating sections <NUM>. The grating pattern limits where the via openings <NUM> are formed. In the embodiment of <FIG>, the via openings <NUM> are formed over the first grating sections <NUM> and no via openings <NUM> are formed over the second grating sections <NUM>. The grating layer <NUM> may be an embodiment of the intermediate layer <NUM>, <NUM>, or <NUM>.

The first grating sections <NUM> include a different material from the second grating sections <NUM>. In an embodiment, the first grating sections <NUM> include a dielectric material and the second grating sections <NUM> include a non-dielectric material, such as a metal or alloy. Examples of the dielectric material include silicon oxides, doped silicon oxides, fluorinated silicon oxides, carbon doped oxides, and so on. The second grating sections <NUM> are metallic sections that include a metal or metal compound, such as Cobalt (Co), aluminum (Al), copper (Cu), Al-doped Cu, Ruthenium (Ru), Molybdenum (Mo), Titanium (Ti), Titanium nitride (TiN), Aluminum oxide (AlOx), Hafnium oxide (HfOx), Zirconium oxide (ZrOx), Titanium oxide (TiOx), Tungsten (W), and so on. In another embodiment, the first grating sections <NUM> include a dielectric material (e.g., the examples listed above) and the second grating sections <NUM> include a different dielectric material, such as metal oxide (e.g., alumina, etc.), carbon nitride, carbide, and so on. In yet another embodiment, the first grating sections <NUM> include a resist material and the second grating sections <NUM> include a non-resist material. In yet another embodiment, the first grating sections <NUM> include a positive photoresist material and the second grating sections <NUM> include a negative photoresist material.

<FIG> shows forming a guiding pattern layer <NUM> over the grating layer <NUM>. The guiding pattern layer <NUM> has a guiding pattern formed based on the grating pattern of the grating layer <NUM>. The guiding pattern layer <NUM> may be formed by changing a part of the grating layer <NUM>. Alternatively, the guiding pattern layer <NUM> is a coating formed on top of the grating layer <NUM>. The guiding pattern is an alternative pattern of a first material <NUM> and second material <NUM>. As shown in <FIG>, the first material <NUM> is over the first grating sections <NUM> and the second material <NUM> is over the second grating sections <NUM>. The guiding pattern layer <NUM> may be the chemical guiding pattern described above in conjunction with <FIG>.

In some embodiments, the guiding pattern layer <NUM> is formed through a surface treatment of the grating layer <NUM>, e.g., by optionally applying a surface treatment to the first grating sections <NUM> or second grating sections <NUM> of the grating layer <NUM>. In an embodiment, polymers may be grated to the grating layer <NUM>, e.g., by using end groups. Examples of the end groups include polyethylene, polystyrene, polyvinylchloride, polytetrafluorethylene, polydimethylsiloxane, some polyesters, some polyurethanes, acrylics, epoxies, P(t-Buytl Acrylate), polyacrylic acid, polyacrylamide, maleic anhydride polymers, polyethylene, polypropylene, polyacrylonitrile, polybutadiene, polyvinyl acetate, polyacetic acid, polybutyl acrylate, polylactic acid, polycaprolactone, poly(ethylene glycol), polyisoprene, and so on. Polymers may be grafted selectively to the first grating sections <NUM> or second grating sections <NUM>.

In some embodiments, a mask may be placed on the grating layer <NUM> to cover the second grating sections <NUM> but expose the first grating sections <NUM> (or vice versa). The surface treatment is performed after the placement of the mask so that the first grating sections <NUM> are treated but the second grating sections <NUM> are not treated. The surface treatment may change the chemical affinity of the first grating sections <NUM> or the second grating sections <NUM> to different materials. Taking the second grating sections <NUM> as an example, the second material <NUM> over the second grating sections <NUM> may have a stronger chemical affinity to blocks of polymer A in the triblock copolymer than the block of polymer B. As another example, the second material <NUM> may have a stronger chemical affinity to the polymer in the polymer nanocomposite than the nanoparticle in the polymer nanocomposite.

<FIG> shows forming a repetitive structure layer <NUM> over the grating layer <NUM> based on the guiding pattern. The repetitive structure layer <NUM> has a repetitive structure including a first element <NUM> and second element <NUM>. The repetitive structure corresponds to the guiding pattern in the guiding pattern layer <NUM>. As shown in <FIG>, the second element <NUM> is formed on the first material <NUM> and not on the second material <NUM>, e.g., due to a stronger chemical affinity of the second element <NUM> to the first material <NUM>.

The repetitive structure layer <NUM> may be the repetitive structure layer <NUM> described above in conjunction with <FIG>. In an embodiment, the repetitive structure is the lamellar structure <NUM>, the first element <NUM> is lamellae <NUM> and <NUM> of polymer A, and the second element <NUM> is lamella <NUM> of polymer B. In another embodiment, the repetitive structure is the cylindrical structure <NUM>, the first element <NUM> is the polymer cylinder <NUM>, and the second element <NUM> is the nanoparticle cylinder <NUM>.

<FIG> shows forming a via opening layer <NUM> from the repetitive structure layer <NUM>. <FIG> is a top view of the via opening layer <NUM>. In <FIG>, the second element <NUM> is removed from the repetitive structure layer <NUM> to form via openings <NUM>. The via openings <NUM> are defined by via opening wall <NUM> which includes the first element <NUM>. As the second element <NUM> is over the first material <NUM>, which is over the first grating section <NUM>, the via openings are formed over the first grating section <NUM>, not over the second grating section <NUM>, which is shown in <FIG>. Accordingly, the grating pattern in the grating layer <NUM> defines locations of the via openings <NUM>. In some embodiments, some or all of the via openings <NUM> may be partially or completely filled with an electrically conductive material to form vias, so that the locations of the vias are also defined by the grating pattern.

<FIG> illustrate a process of forming via openings <NUM> by using mixed epitaxy, in accordance with some embodiments. Mixed epitaxy is a combination of graphoepitaxy and chemoepitaxy. <FIG> shows an IC device <NUM>. The IC device <NUM> includes a substrate <NUM>, an intermediate layer <NUM> over (e.g., attached on) the substrate <NUM>, and a guiding pattern layer <NUM> over the intermediate layer <NUM>. In other embodiments, the IC device <NUM> may include different components. For instance, the IC device <NUM> may not include the intermediate layer <NUM> and the guiding pattern layer <NUM> is formed on the substrate <NUM>.

The guiding pattern layer <NUM> includes a topographical guiding pattern. The topographical guiding pattern directs self-assembly of a lamellar triblock copolymer or formation of a cylindrical polymer composite. In some embodiments, the topographical guiding pattern directs self-assembly of the lamellar triblock copolymer or formation of the cylindrical polymer composite through mechanisms such as commensurability, lateral ordering, confinement effects, etc. In <FIG>, the topographical guiding pattern is an alternative pattern of guiding walls <NUM> (individually referred to as "guiding wall <NUM>") and openings <NUM> (individually referred to as "opening <NUM>"). Each opening <NUM> is between two guiding walls <NUM> that defines the opening <NUM>. In some embodiments, the guiding pattern layer <NUM> is formed by using EUV, immersion lithography (e.g., by using UV light at <NUM> wavelength), deep UV lithography (e.g., dry <NUM> photolithography), other types of lithography techniques. The topographical guiding pattern is three-dimensional. The openings <NUM> provide space for DSA of the lamellar triblock copolymer. In some embodiments, the guiding pattern layer <NUM> may be physically tailored or chemically modified to impose different affinity to different polymer blocks of the lamellar triblock copolymer to enforce the orientation of the lamellar triblock copolymer, which is perpendicular to the intermediate layer <NUM>.

<FIG> shows an IC device <NUM> including a mixed guiding pattern layer <NUM>. The mixed guiding pattern layer <NUM> is formed by forming a chemical guiding pattern in each of the openings <NUM> of the IC device <NUM>. In <FIG>, the chemical guiding pattern is an alternative pattern of first sections <NUM> (individually referred to as "first section <NUM>") and second sections <NUM> (individually referred to as "second section <NUM>"). Each second section <NUM> is between two first sections <NUM> that defines the second section <NUM>. The first sections <NUM> have different chemical properties from the second sections <NUM>. In embodiments where a triblock copolymer is used, the first section <NUM> or second section <NUM> has different chemical affinity to different polymer blocks of the triblock copolymer to enforce the orientation of the lamellar triblock copolymer, which is perpendicular to the intermediate layer <NUM>. In embodiments where the polymer nanocomposite is used, the first section <NUM> or second section <NUM> has different chemical affinity to the polymer and the nanocomposite in the polymer nanocomposite. Accordingly, the chemical guiding pattern can guide self-assembly of the triblock copolymer and the polymer nanocomposite. In an embodiment, the first sections <NUM> include a different material from the second sections <NUM>.

<FIG> shows an IC device <NUM> generated by forming a repetitive structure layer <NUM> based on the mixed guiding pattern. The repetitive structure layer <NUM> includes a plurality of structures <NUM> (individually referred to as "structure <NUM>") formed in the openings <NUM>. The structures <NUM> may be formed by applying a triblock copolymer or a polymer nanocomposite in the openings <NUM> with the chemical guiding pattern. In <FIG>, each opening <NUM> is filled with three structures <NUM>. In other embodiments, an opening <NUM> may be filled with a different number of structures <NUM>. A structure <NUM> includes a first element <NUM> and second element <NUM>.

In some embodiments, the repetitive structure layer <NUM> is formed by using the triblock copolymer. For instance, the triblock copolymer is deposited in the openings <NUM> of the mixed guiding pattern layer <NUM>. The topographical and chemical guiding patterns of the mixed guiding pattern layer <NUM> guide microphase separation of the triblock copolymer. The self-assembly of the triblock copolymer may be drive by the guiding walls <NUM> and the differentiated chemical affinity of the first sections <NUM> or second sections <NUM>. In other embodiments, the repetitive structure layer <NUM> may be formed by using the polymer nanocomposite. A structure <NUM> is a cylindrical structure, e.g., the cylindrical structure <NUM> in <FIG>. The first element <NUM> may be the polymer cylinder <NUM> and the second element <NUM> may be the nanoparticle cylinder <NUM> in <FIG>. The topographical and chemical guiding patterns of the mixed guiding pattern layer <NUM>. The cylindrical structures are aligned relative to the guiding walls <NUM> and the second sections <NUM>, which achieves a better alignment compared with lithographical alignment and therefore, can be used to form very small via openings (e.g., nanoscale).

The alignment of the structures <NUM> is based on both the topographical guiding pattern and chemical guiding pattern and therefore, can be better than an alignment based on the topographical guiding pattern or chemical guiding pattern alone. In some embodiments, an annealing treatment may be applied to the triblock copolymer or polymer nanocomposite in order to initiate, accelerate, or otherwise promote the formation of the structures <NUM>. The annealing treatment may include a treatment that is operable to increase a temperature of the polymer nanocomposite.

<FIG> shows an IC device <NUM> including a via opening layer <NUM>, in which via openings <NUM> (individually referred to as "via opening <NUM>") are formed. The via openings <NUM> are defined by the via opening walls <NUM> (individually referred to as "via opening wall <NUM>"). A via opening <NUM> is formed by removing the second element <NUM> from a structure <NUM>. The via opening walls <NUM> of the via opening <NUM> are the first element <NUM> of the structure <NUM>. The embodiment of <FIG> removes the second element <NUM> from all the structures <NUM>. In other embodiments, the second element <NUM> is removed from a subset of the structures <NUM>. <FIG> shows removal of the whole second element <NUM>. In other embodiments, a via opening <NUM> may be formed by removing a portion of the second element <NUM>. In some embodiments, the ratio of the length of the structures <NUM> along the Y axis to the length of the via openings <NUM> along the Y axis is in a range from <NUM> to <NUM>. In some embodiments, some or all of the via openings <NUM> may be partially or completely filled with an electrically conductive material to form vias.

In some embodiments, the second element <NUM> is removed by performing an etching process (e.g., a selective etching process) on the repetitive structure layer <NUM>. The second element <NUM> is etched at a higher rate than the first element <NUM>. The first element 2330may remain substantially unetched after the etching process. In an embodiment, the etching process includes an isotropic chemically selective etch.

<FIG> is a flowchart illustrating a process <NUM> of using a lamellar triblock copolymer to rectify via openings, in accordance with various embodiments. The process <NUM> includes forming <NUM> a guiding pattern on a surface of a layer of the IC device. The process also includes forming <NUM> a plurality of lamellar structures based on the guiding pattern by applying a triblock copolymer in a lamellar phase to the surface of the layer. An individual one of the plurality of lamellar structures includes a first lamella, a second lamella, and a third lamella. The second lamella is between the first lamella and the third lamella. The process further includes forming <NUM> the via openings (such as contact holes) by removing the second lamella from at least some (e.g., all) of the lamellar structures.

<FIG> is a flowchart illustrating a process <NUM> of using a polymer nanocomposite to rectify via openings, in accordance with various embodiments. The process <NUM> includes forming <NUM> a guiding pattern on a surface of a layer of the IC device. The process <NUM> also includes forming <NUM> a plurality of structures based at least on the guiding pattern by applying a polymer nanocomposite material on the surface of the layer. The polymer nanocomposite material includes a nanoparticle and polymer chains attached on the nanoparticle. The process <NUM> further includes forming <NUM> via openings (such as contact holes) by removing the nanoparticle from the structures.

<FIG> is a flowchart illustrating a process <NUM> of using mixed epitaxy to rectify via openings, in accordance with various embodiments. The process <NUM> includes forming <NUM> a topographical guiding pattern on a surface of a first layer of the IC device, the topographical guiding pattern comprising a plurality of openings (the topographical guiding pattern may further include a plurality of guiding walls defining the openings). The process <NUM> also includes forming <NUM> a chemical guiding pattern in individual ones of the openings of the topographical guiding pattern (e.g., the chemical guiding pattern comprising a plurality of first sections and a plurality of second sections, wherein the first sections include a first material, and the second sections include a second material that is different from the first material). The process <NUM> also includes forming <NUM> a second layer (e.g., forming the second layer on the first layer) by applying a block copolymer in the openings with the chemical guiding pattern. The process <NUM> further includes forming <NUM> the via openings (such as contact holes) in the second layer by removing portions of the block copolymer from the second layer.

<FIG> are top views of a wafer <NUM> and dies <NUM> that may include one or more via openings in accordance with any of the embodiments disclosed herein. In some embodiments, the dies <NUM> may be included in an IC package, in accordance with any of the embodiments disclosed herein. For example, any of the dies <NUM> may serve as any of the dies <NUM> in an IC package <NUM> shown in <FIG>. The wafer <NUM> may be composed of semiconductor material and may include one or more dies <NUM> having IC structures formed on a surface of the wafer <NUM>. Each of the dies <NUM> may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more via openings as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more via openings as described herein, e.g., after manufacture of any embodiment of the IC devices described herein), the wafer <NUM> may undergo a singulation process in which each of the dies <NUM> is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more via openings as disclosed herein may take the form of the wafer <NUM> (e.g., not singulated) or the form of the die <NUM> (e.g., singulated). The die <NUM> may include one or more diodes, one or more transistors as well as, optionally, supporting circuitry to route electrical signals to the diodes and transistors, as well as any other IC components. In some embodiments, the wafer <NUM> or the die <NUM> may implement an ESD protection device, an RF FE device, a memory device (e.g., a static random-access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die <NUM>.

<FIG> is a side, cross-sectional view of an example IC package <NUM> that may include one or more IC devices having one or more via openings in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package <NUM> may be a system-in-package (SiP).

As shown in <FIG>, the IC package <NUM> may include a package substrate <NUM>. The package substrate <NUM> may be formed of a dielectric material (e.g., a ceramic, a glass, a combination of organic and inorganic materials, a buildup film, an epoxy film having filler particles therein, etc., and may have embedded portions having different materials), and may have conductive pathways extending through the dielectric material between the face <NUM> and the face <NUM>, or between different locations on the face <NUM>, and/or between different locations on the face <NUM>.

The package substrate <NUM> may include conductive contacts <NUM> that are coupled to conductive pathways <NUM> through the package substrate <NUM>, allowing circuitry within the dies <NUM> and/or the interposer <NUM> to electrically couple to various ones of the conductive contacts <NUM> (or to other devices included in the package substrate <NUM>, not shown).

The IC package <NUM> may include an interposer <NUM> coupled to the package substrate <NUM> via conductive contacts <NUM> of the interposer <NUM>, first-level interconnects <NUM>, and the conductive contacts <NUM> of the package substrate <NUM>. The first-level interconnects <NUM> illustrated in <FIG> are solder bumps, but any suitable first-level interconnects <NUM> may be used. In some embodiments, no interposer <NUM> may be included in the IC package <NUM>; instead, the dies <NUM> may be coupled directly to the conductive contacts <NUM> at the face <NUM> by first-level interconnects <NUM>.

The IC package <NUM> may include one or more dies <NUM> coupled to the interposer <NUM> via conductive contacts <NUM> of the dies <NUM>, first-level interconnects <NUM>, and conductive contacts <NUM> of the interposer <NUM>. The conductive contacts <NUM> may be coupled to conductive pathways (not shown) through the interposer <NUM>, allowing circuitry within the dies <NUM> to electrically couple to various ones of the conductive contacts <NUM> (or to other devices included in the interposer <NUM>, not shown). The first-level interconnects <NUM> illustrated in <FIG> are solder bumps, but any suitable first-level interconnects <NUM> may be used. As used herein, a "conductive contact" may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

In some embodiments, an underfill material <NUM> may be disposed between the package substrate <NUM> and the interposer <NUM> around the first-level interconnects <NUM>, and a mold compound <NUM> may be disposed around the dies <NUM> and the interposer <NUM> and in contact with the package substrate <NUM>. In some embodiments, the underfill material <NUM> may be the same as the mold compound <NUM>. Example materials that may be used for the underfill material <NUM> and the mold compound <NUM> are epoxy mold materials, as suitable. Second-level interconnects <NUM> may be coupled to the conductive contacts <NUM>. The second-level interconnects <NUM> illustrated in <FIG> are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects <NUM> may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects <NUM> may be used to couple the IC package <NUM> to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to <FIG>.

The dies <NUM> may take the form of any of the embodiments of the die <NUM> discussed herein and may include any of the embodiments of an IC device having one or more via openings, e.g., any of the IC devices described herein. In embodiments in which the IC package <NUM> includes multiple dies <NUM>, the IC package <NUM> may be referred to as a multi-chip package. Importantly, even in such embodiments of an MCP implementation of the IC package <NUM>, one or more via openings may be provided in a single chip, in accordance with any of the embodiments described herein. The dies <NUM> may include circuitry to perform any desired functionality. For example, one or more of the dies <NUM> may be ESD protection dies, including one or more via openings as described herein, one or more of the dies <NUM> may be logic dies (e.g., silicon-based dies), one or more of the dies <NUM> may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, any of the dies <NUM> may include one or more via openings, e.g., as discussed above; in some embodiments, at least some of the dies <NUM> may not include any via openings.

The IC package <NUM> illustrated in <FIG> may be a flip chip package, although other package architectures may be used. For example, the IC package <NUM> may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package <NUM> may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies <NUM> are illustrated in the IC package <NUM> of <FIG>, an IC package <NUM> may include any desired number of the dies <NUM>. An IC package <NUM> may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face <NUM> or the second face <NUM> of the package substrate <NUM>, or on either face of the interposer <NUM>. More generally, an IC package <NUM> may include any other active or passive components known in the art.

<FIG> is a cross-sectional side view of an IC device assembly <NUM> that may include components having one or more IC devices implementing one or more via openings in accordance with any of the embodiments disclosed herein. The IC device assembly <NUM> includes a number of components disposed on a circuit board <NUM> (which may be, e.g., a motherboard). The IC device assembly <NUM> includes components disposed on a first face <NUM> of the circuit board <NUM> and an opposing second face <NUM> of the circuit board <NUM>; generally, components may be disposed on one or both faces <NUM> and <NUM>. In particular, any suitable ones of the components of the IC device assembly <NUM> may include any of the IC devices implementing one or more via openings in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above with reference to <FIG> (e.g., may include one or more via openings in a die <NUM>).

In some embodiments, the circuit board <NUM> may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board <NUM>. In other embodiments, the circuit board <NUM> may be a non-PCB substrate.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-interposer structure <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may electrically and mechanically couple the package-on-interposer structure <NUM> to the circuit board <NUM>, and may include solder balls (e.g., as shown in <FIG>), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure <NUM> may include an IC package <NUM> coupled to an interposer <NUM> by coupling components <NUM>. The coupling components <NUM> may take any suitable form for the application, such as the forms discussed above with reference to the coupling components <NUM>. The IC package <NUM> may be or include, for example, a die (the die <NUM> of <FIG>), an IC device (e.g., the IC devices described above), or any other suitable component. In particular, the IC package <NUM> may include one or more via openings as described herein. Although a single IC package <NUM> is shown in <FIG>, multiple IC packages may be coupled to the interposer <NUM>; indeed, additional interposers may be coupled to the interposer <NUM>. The interposer <NUM> may provide an intervening substrate used to bridge the circuit board <NUM> and the IC package <NUM>. Generally, the interposer <NUM> may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer <NUM> may couple the IC package <NUM> (e.g., a die) to a BGA of the coupling components <NUM> for coupling to the circuit board <NUM>. In the embodiment illustrated in <FIG>, the IC package <NUM> and the circuit board <NUM> are attached to opposing sides of the interposer <NUM>; in other embodiments, the IC package <NUM> and the circuit board <NUM> may be attached to a same side of the interposer <NUM>. In some embodiments, three or more components may be interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices such as further RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer <NUM>. In some embodiments, the IC devices implementing one or more via openings as described herein may also be implemented in/on the interposer <NUM>. The package-on-interposer structure <NUM> may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly <NUM> may include an IC package <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may take the form of any of the embodiments discussed above with reference to the coupling components <NUM>, and the IC package <NUM> may take the form of any of the embodiments discussed above with reference to the IC package <NUM>.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-package structure <NUM> coupled to the second face <NUM> of the circuit board <NUM> by coupling components <NUM>. The package-on-package structure <NUM> may include an IC package <NUM> and an IC package <NUM> coupled together by coupling components <NUM> such that the IC package <NUM> is disposed between the circuit board <NUM> and the IC package <NUM>. The coupling components <NUM> and <NUM> may take the form of any of the embodiments of the coupling components <NUM> discussed above, and the IC packages <NUM> and <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above. The package-on-package structure <NUM> may be configured in accordance with any of the package-on-package structures known in the art.

<FIG> is a block diagram of an example computing device <NUM> that may include one or more components with one or more transistor arrangements fabricated using placeholders for backside contact formation in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device <NUM> may include a die (e.g., the die <NUM> of <FIG>) including one or more via openings in accordance with any of the embodiments disclosed herein. Any of the components of the computing device <NUM> may include an IC device (e.g., any embodiment of the IC devices of <FIG>) and/or an IC package (e.g., the IC package <NUM> of <FIG>). Any of the components of the computing device <NUM> may include an IC device assembly (e.g., the IC device assembly <NUM> of <FIG>). A number of components are illustrated in <FIG> as included in the computing device <NUM>, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device <NUM> may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system on a chip (SoC) die.

Additionally, in various embodiments, the computing device <NUM> may not include one or more of the components illustrated in <FIG>, but the computing device <NUM> may include interface circuitry for coupling to the one or more components. For example, the computing device <NUM> may not include a display device <NUM>, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device <NUM> may be coupled. In another set of examples, the computing device <NUM> may not include an audio input device <NUM> or an audio output device <NUM>, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device <NUM> or audio output device <NUM> may be coupled.

The computing device <NUM> may include a processing device <NUM> (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device <NUM> may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device <NUM> may include a memory <NUM>, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory <NUM> may include memory that shares a die with the processing device <NUM>.

In some embodiments, the computing device <NUM> may include a communication chip <NUM> (e.g., one or more communication chips). For example, the communication chip <NUM> may be configured for managing wireless communications for the transfer of data to and from the computing device <NUM>. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium.

The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication chip <NUM> may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip <NUM> may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication chip <NUM> may operate in accordance with other wireless protocols in other embodiments. The computing device <NUM> may include an antenna <NUM> to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip <NUM> may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip <NUM> may include multiple communication chips. For instance, a first communication chip <NUM> may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip <NUM> may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip <NUM> may be dedicated to wireless communications, and a second communication chip <NUM> may be dedicated to wired communications.

The computing device <NUM> may include battery/power circuitry <NUM>. The battery/power circuitry <NUM> may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device <NUM> to an energy source separate from the computing device <NUM> (e.g., AC line power).

The computing device <NUM> may include a display device <NUM> (or corresponding interface circuitry, as discussed above). The display device <NUM> may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device <NUM> may include an audio output device <NUM> (or corresponding interface circuitry, as discussed above). The audio output device <NUM> may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device <NUM> may include an audio input device <NUM> (or corresponding interface circuitry, as discussed above). The audio input device <NUM> may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device <NUM> may include a GPS device <NUM> (or corresponding interface circuitry, as discussed above). The GPS device <NUM> may be in communication with a satellite-based system and may receive a location of the computing device <NUM>, as known in the art.

The computing device <NUM> may include an other output device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other output device <NUM> may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device <NUM> may include an other input device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other input device <NUM> may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

Claim 1:
An integrated circuit, IC, device, comprising:
a first layer (<NUM>);
an intermediate layer (<NUM>) formed on the first layer (<NUM>);
a guiding pattern layer (<NUM>) formed on the intermediate layer (<NUM>), the guiding pattern layer (<NUM>) comprising openings (<NUM>) and guiding walls (<NUM>), each opening (<NUM>) is between two guiding walls (<NUM>) to define the opening <NUM>; J Z and
a second layer adjoining the intermediate layer (<NUM>), the second layer arranged within the openings (<NUM>) of the guiding pattern layer (<NUM>), the second layer comprising a plurality of lamellar structures (<NUM>) arranged within the openings (<NUM>) of the guiding pattern layer (<NUM>),
wherein an individual one of the lamellar structures comprises a first lamella (<NUM>) comprising a first block of a triblock copolymer, a second lamella (<NUM>) comprising a second block of the triblock copolymer, and a via (<NUM>) between the first (<NUM>) and second lamellae (<NUM>),
wherein the first (<NUM>) and second lamellae (<NUM>) are electrically insulating, and the via (<NUM>) includes an electrically conductive material.