Patent Description:
Mobile communication devices may include a variety of components including circuit boards, integrated circuit (IC) devices and/or System-on-Chip (SoC) devices. The components may include processing devices, user interface components, storage and other peripheral components that communicate through a shared data communication bus, which may include a multi-drop serial bus or a parallel bus. General-purpose serial interfaces known in the industry include the Inter-Integrated Circuit (I2C or I<NUM>C) serial interface and its derivatives and alternatives.

The Mobile Industry Processor Interface (MIPI) Alliance defines standards for the Improved Inter-Integrated Circuit (I3C) serial interface, the Radio Frequency Front-End (RFFE) interface, the System Power Management Interface (SPMI) and other interfaces. These interfaces may be used to connect processors, sensors and other peripherals, for example. In some interfaces, multiple bus masters are coupled to the serial bus such that two or more devices can serve as bus master for different types of messages transmitted on the serial bus. SPMI protocols define a hardware interface that may be implemented between baseband or application processors and peripheral components. In some instances, SPMI protocols are implemented to support power management operations within a device.

The RFFE interface provides a communication interface that may be used for controlling various radio frequency (RF) front-end devices, including power amplifier (PA), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, and the like. These devices may be collocated in a single IC device or provided in multiple IC devices. In a mobile communication device, multiple antennas and radio transceivers may be provided to support multiple concurrent RF links. In some instances, a serial bus may enable one device to trigger an action in another device at a precise time.

There is an ongoing need to support accurate and reliable triggers, initiated, enabled or managed through serial buses.

<CIT> discloses a device for activating trigger data having a serial bus interface and a processing circuit coupled to the serial bus interface. The processing circuit is configured to receive a plurality of trigger data via a serial bus, receive a plurality of activation data via the serial bus, detect an activation scheme for activating a respective trigger data of the plurality of trigger data based on activation data corresponding to the respective trigger data, and activate the respective trigger data according to the detected activation scheme. If activated, each one of the plurality of trigger data respectively enables a corresponding operation to be performed at the device. Each one of the plurality of activation data respectively correspond to each one of the plurality of trigger data.

Preferred embodiments are according to the dependent claims. Certain aspects of the disclosure relate to systems, apparatus, methods and techniques that can improve synchronization of triggers that are configured and/or initiated through transmissions over a serial bus. In one aspect of the disclosure, complexity of trigger timing can be reduced by disabling counters or timers until counters or timers for a set of triggers have been loaded with count values. In one aspect of the disclosure, counters may be enabled to begin counting clock pulses when a bus park condition is detected or until all counters associated with a group of triggers have been loaded with count values.

In various aspects of the disclosure, a method for managing triggering in a device coupled to a serial bus includes receiving a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to a plurality of counters, configuring each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, causing each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values, and actuating a trigger when a counter associated with the trigger has counted to zero.

In various aspects of the disclosure, a data communication apparatus has an interface circuit adapted to couple the data communication apparatus to a serial bus and configured to receive a clock signal from the serial bus, a plurality of counters configured to count pulses in the clock signal, and a controller configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

In various aspects of the disclosure, a processor-readable storage medium has one or more instructions stored thereon which, when executed by at least one processor of a processing circuit in a receiver, cause the at least one processor to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to a plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero.

In various aspects of the disclosure, a data communication apparatus has means for receiving a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to a plurality of counters, means for controlling a plurality of counters, each of the plurality of counters being configured with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, and means for actuating a trigger when a counter associated with the trigger has counted to zero. The means for controlling the plurality of counters may be configured to cause each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values.

Several aspects of the invention will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements").

Devices that include application-specific IC (ASIC) devices, SoCs and/or other IC devices often employ a shared communication interface that may include a serial bus or other data communication link to connect processors with modems and other peripherals. The serial bus or other data communication link may be operated in accordance with multiple standards or protocols defined. For example, the serial bus may be operated in accordance with an I2C, I3C, SPMI, and/or RFFE protocol, or other protocols including a protocol that may be configured for half-duplex operation. Increased utilization of serial buses, and/or the imposition of more stringent timing constraints in support of applications, peripherals and sensors can result in demand for reduced transmission latencies. Transmission latency may include the time required to terminate a transaction in process on the serial bus, bus turnaround (between transmit mode and receive mode), bus arbitration and/or command transmissions specified by protocol.

Certain operations in a radio frequency IC (RFIC) require very low-latency communications. For example, configuration and reconfiguration of circuits used to drive multiple antennas may generate large volumes of messages, commands and signaling directed to multiple RF components. In many instances, the messages may include configuration parameters that are to be applied at a time determined by a controlling device. In some instances, triggers may be sent to activate a configuration defined by previously provided configuration parameters. In one example, triggers may be sent to initiate or actuate a sequence of configurations or actions in a radio frequency device according to a defined timeline.

Certain aspects disclosed herein relate to timing issues that can arise when triggers are preconfigured and actuated based on timers or counters. For example, triggers may be implemented by transmitting trigger configuration information before the desired trigger actuation time and initiating one or more timers to define a time of actuation, whereby the triggers are actuated when the timers expire. In conventional systems, the timers may be implemented using a counter clocked by a clock signal provided by the bus master. The counters are loaded with count values and the triggers are activated, actuated or fired when the counters reach zero or overflow. The bus master provides the clock signal during idle periods and while a transaction is being conducted through the serial bus.

According to the invention, a method for managing triggering in a device coupled to a serial bus includes receiving a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to a plurality of counters, configuring each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, causing each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values, and actuating a trigger when a counter associated with the trigger has counted to zero.

Certain aspects disclosed herein may be applicable to a serial bus operated in accordance with an I2C, I3C, SPMI, and/or RFFE protocol, or other protocol. Certain aspects are applicable to a serial bus operated in half-duplex mode or full-duplex mode. Certain aspects are applicable to point-to-point interfaces including UART-based interfaces, line multiplexed UART (LM-UART) interfaces, and virtual GPIO (VGI) and messaging interfaces. Certain aspects are applicable to multipoint interfaces and/or interfaces when operated in point-to-point mode.

According to certain aspects of this disclosure, a serial data link may be used to interconnect electronic devices that are subcomponents of an apparatus such as a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a smart home device, intelligent lighting, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multicopter, or any other similarly functioning device.

<FIG> illustrates an example of an apparatus <NUM> that employs at least one data communication link. The apparatus <NUM> may include a processing circuit <NUM> that has multiple circuits or devices <NUM>, <NUM> and/or <NUM> and that may be implemented in one or more ASICs or in an SoC. In one example, the apparatus <NUM> may be a communication device and the processing circuit <NUM> may include a processing device provided in an ASIC <NUM>, one or more peripheral devices <NUM>, and a transceiver <NUM> that enables the apparatus to communicate through an antenna <NUM> with a radio access network, a core access network, the Internet and/or another network.

The ASIC <NUM> may have one or more processors <NUM>, one or more modems <NUM>, on-board memory <NUM>, a bus interface circuit <NUM> and/or other logic circuits. The processing circuit <NUM> may be controlled by an operating system that may provide an application programming interface (API) layer that enables the one or more processors <NUM> to execute software modules residing in the on-board memory <NUM> or other processor-readable storage <NUM> provided on the processing circuit <NUM>. The software modules may include instructions and data stored in the on-board memory <NUM> or in the processor-readable storage <NUM>. The ASIC <NUM> may access its on-board memory <NUM>, the processor-readable storage <NUM>, and/or storage external to the processing circuit <NUM>. The on-board memory <NUM> and/or the processor-readable storage <NUM> may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The processing circuit <NUM> may include, implement, or have access to a local database or other parameter storage that can maintain operational parameters and other information used to configure and operate the apparatus <NUM> and/or the processing circuit <NUM>. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, soft or hard disk, or the like. The processing circuit <NUM> may also be operably coupled to external devices such as the antenna <NUM>, a display <NUM>, operator controls, such as switches or buttons <NUM>, <NUM> and/or an integrated or external keypad <NUM>, among other components. A user interface module may be configured to operate with the display <NUM>, external keypad <NUM>, etc. through a dedicated communication link or through one or more serial data interconnects.

The processing circuit <NUM> may provide or be coupled to one or more buses 118a, 118b, <NUM> that enable communication between certain devices <NUM>, <NUM>, and/or <NUM>. In one example, the ASIC <NUM> may include a bus interface circuit <NUM> that is implemented using a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, the bus interface circuit <NUM> may be configured to operate in accordance with standards-defined communication specifications or protocols. The processing circuit <NUM> may include or control a power management function that configures and manages the operation of the apparatus <NUM>.

<FIG> illustrates certain aspects of an apparatus <NUM> that includes multiple devices <NUM>, and <NUM><NUM>-<NUM>N coupled to a serial bus <NUM>. The devices <NUM> and <NUM><NUM>-<NUM>N may be implemented in one or more semiconductor IC devices, such as an application processor, SoC or ASIC. In various implementations, the devices <NUM> and <NUM><NUM>-<NUM>N may include, support or operate as a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, and/or other such components or devices. In some examples, one or more of the slave devices <NUM><NUM>-<NUM>N may be used to control, manage or monitor a sensor device. Communication between devices <NUM> and <NUM><NUM>-<NUM>N over the serial bus <NUM> is controlled by a bus master device <NUM>. Certain types of bus can support multiple bus master devices <NUM>.

In one example, a bus master device <NUM> may include an interface controller <NUM> that manages access to the serial bus, configures dynamic addresses for slave devices <NUM><NUM>-<NUM>N and/or generates a clock signal <NUM> to be transmitted on a clock line <NUM> of the serial bus <NUM>. The bus master device <NUM> may include configuration registers <NUM> or other storage <NUM>, and other control logic <NUM> configured to handle protocols and/or higher-level functions. The control logic <NUM> may include a processing circuit having a processing device such as a state machine, sequencer, signal processor or general-purpose processor. The bus master device <NUM> includes a transceiver <NUM> and line drivers/receivers 214a and 214b. The transceiver <NUM> may include receiver circuits, transmitter circuits and common circuits, where the common circuits may include timing, logic and storage circuits and/or devices. In one example, the transmitter circuits encode and transmit data based on timing in the clock signal <NUM> provided by a clock generation circuit <NUM>. Other timing clock signals <NUM> may be used by the control logic <NUM> and other functions, circuits or modules.

At least one device <NUM><NUM>-<NUM>N may be configured to operate as a slave device on the serial bus <NUM> and may include circuits and modules that support a display, an image sensor, and/or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. In one example, a slave device <NUM><NUM> may provide a control function, module or circuit <NUM> that includes circuits and modules to support a display, an image sensor, and/or circuits and modules that control and communicate with one or more sensors that measure environmental conditions. The slave device <NUM><NUM> may include configuration registers <NUM> or other storage <NUM>, control logic <NUM>, a transceiver <NUM> and line drivers/receivers 244a and 244b. The control logic <NUM> may include a processing circuit that has a processing device such as a state machine, sequencer, signal processor or general-purpose processor. The transceiver <NUM> may include receiver circuits, transmitter circuits and common circuits, where the common circuits may include timing, logic and storage circuits and/or devices. In one example, the transmitter circuits encode and transmit data based on timing in a clock signal <NUM> provided by clock generation and/or recovery circuits <NUM>. The clock signal <NUM> may be derived from a signal received from the clock line <NUM>. Other timing clock signals <NUM> may be used by the control logic <NUM> and other functions, circuits or modules.

The serial bus <NUM> may be operated in accordance with RFFE, I2C, I3C, SPMI, or other protocol. In some instances, two or more devices <NUM>, <NUM><NUM>-<NUM>N may be configured to operate as a bus master device on the serial bus <NUM>.

<FIG> illustrates certain aspects of an apparatus <NUM> that includes multiple RFFE buses <NUM>, <NUM>, <NUM> configured coupled to various RF front-end devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. A modem <NUM> includes an RFFE interface <NUM> that couples the modem <NUM> to a first RFFE bus <NUM>. The modem <NUM> may communicate with a baseband processor <NUM> and a Radio-Frequency IC (RFIC <NUM>) through one or more communication links <NUM>, <NUM>. The illustrated apparatus <NUM> may be embodied in one or more of a mobile communication device, a mobile telephone, a mobile computing system, a mobile telephone, a notebook computer, a tablet computing device, a media player, a gaming device, a wearable computing and/or communications device, an appliance, or the like.

In various examples, the apparatus <NUM> may be implemented with one or more baseband processors <NUM>, modems <NUM>, RFICs <NUM>, multiple communications links <NUM>, <NUM>, multiple RFFE buses <NUM>, <NUM>, <NUM> and/or other types of buses. The apparatus <NUM> may include other processors, circuits, modules and may be configured for various operations and/or for a variety of functionalities. In the example illustrated in <FIG>, the modem <NUM> is coupled to an RF tuner <NUM> through its RFFE interface <NUM> and the first RFFE bus <NUM>. The RFIC <NUM> may include one or more RFFE interfaces <NUM>, <NUM>, controllers, state machines and/or processors that can configure and control certain aspects of the RF front-end. The RFIC <NUM> may communicate with a PA <NUM> and a power tracking module <NUM> through a first of its RFFE interfaces <NUM> and the second RFFE bus <NUM>. The RFIC <NUM> may communicate with a switch <NUM> and one or more LNAs <NUM>, <NUM>.

Bus latency can affect the ability of a serial bus to handle high-priority, real-time and/or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may relate to sensor status, device-generated real-time events and virtualized general-purpose input/output (GPIO). In one example, bus latency may be measured as the time elapsed between a message becoming available for transmission and the delivery of the message or, in some instances, commencement of transmission of the message. Other measures of bus latency may be employed. Bus latency typically includes delays incurred while higher priority messages are transmitted, interrupt processing, the time required to terminate a datagram in process on the serial bus, the time to transmit commands causing bus turnaround between transmit mode and receive mode, bus arbitration and/or command transmissions specified by protocol.

In certain examples, latency-sensitive messages can include coexistence messages. Coexistence messages are transmitted in a multisystem platform to prevent or reduce instances of certain device types impinging on each other, including for example, switches <NUM>, LNAs <NUM>, <NUM>, PAs <NUM> and other types of device that operate concurrently in a manner that can generate inter-device interference, or that could potentially cause damage to one or more active devices through high-power electromagnetic interference. Devices that may interfere with one another may exchange coexistence management (CxM) messages to permit each device to signal imminent actions that may result in interference or conflict. CxM messages may be used to manage operation of shared components including a switch <NUM>, LNA <NUM>, <NUM>, PA <NUM> and/or an antenna.

Multi-drop interfaces such as interfaces governed by RFFE, SPMI, I3C, and similar protocols can reduce the number of physical input/output (I/O) pins used to communicate between multiple devices. Protocols that support communication over a multi-drop serial bus define a datagram structure used to transmit command, control and data payloads. Datagram structures for different protocols define certain common features, including addressing used to select devices to receive or transmit data, clock generation and management, interrupt processing and device priorities. The example of RFFE protocols may be employed to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

<FIG> illustrates examples of datagram structures <NUM>, <NUM> that are consistent with structures defined by RFFE protocols. The datagram structures <NUM>, <NUM> are also consistent with, or similar to datagram structures defined by other protocols and may be adapted for use in accordance with certain aspects disclosed herein. The datagram structures <NUM>, <NUM> commence with transmission of a two-bit start sequence condition (the SSC <NUM> or <NUM>) followed by a four-bit device identifier (the Device ID <NUM> or <NUM>). A nine-bit command field <NUM>, <NUM> is transmitted next. In the Register Write command datagram structure <NUM>, the nine-bit command field <NUM> includes a three-bit command code <NUM>, a five-bit address field <NUM> and a parity bit. In the Extended Register Write command datagram structure <NUM>, the nine-bit command field <NUM> is occupied by an eight-bit command code and a parity bit and followed by an address field <NUM> that carries an eight-bit register address and a parity bit. In the Register Write command datagram structure <NUM>, a data field <NUM> carries a single data byte, while in the Extended Register Write command datagram structure <NUM> the data field <NUM> carries up to <NUM> data bytes. Each data byte is transmitted with a parity bit. Bus park signaling <NUM>, <NUM> terminates the datagram structures <NUM>, <NUM>.

<FIG> includes timing diagrams <NUM>, <NUM> that illustrate signaling that is transmitted to delineate the boundaries of SPMI or RFFE datagrams. The timing diagrams <NUM>, <NUM> show the relative timing of signals transmitted on SCLK <NUM> and SDATA <NUM>. The first timing diagram <NUM> illustrates timing of an SSC <NUM> that is transmitted to signal the start of a datagram <NUM>. The SSC <NUM> is transmitted when the serial bus is in an idle state <NUM>. In the idle state <NUM>, SCLK <NUM> is driven at full strength by a bus master while slave devices coupled to the serial bus present a high impedance to SCLK <NUM>. SCLK <NUM> is held in the low signaling state (here, at zero volts) by the bus master. In the idle state <NUM>, SDATA <NUM> is weakly driven by the bus master and held or maintained in the weakly driven low signaling state <NUM>. The weakly driven low signaling state <NUM> can easily be overcome by another line driver that can drive SDATA <NUM> at full strength.

In a conventional master-driven SSC <NUM>, the bus master commences transmission of the SSC <NUM> at a first point in time <NUM> when it begins to drive SDATA <NUM> at full strength, initially at the low signaling state. The bus master then provides a pulse <NUM> on SDATA <NUM> while continuing to drive SCLK <NUM> to the low signaling state. The pulse <NUM> has duration of at least one cycle of a clock signal provided on SCLK <NUM> during transmission of a datagram <NUM>. At a second point in time <NUM>, the bus master commences transmission of clock pulses on SCLK <NUM>, thereby providing the clock signal used to control or indicate timing of a datagram <NUM> transmitted on SDATA <NUM>.

The second timing diagram <NUM> illustrates timing of a bus park cycle (the BPC <NUM>) that may be transmitted to signal the termination of a datagram <NUM>, for example. The BPC <NUM> is transmitted by providing a falling edge <NUM> on SDATA <NUM> while SCLK <NUM> is in a high signaling state <NUM>. Transitions on SDATA <NUM> are permitted in the low portion of the clock signal during transmission of the datagram <NUM>, and the falling edge <NUM> in <FIG> is clearly recognizable as BPC <NUM> signaling. The falling edge <NUM> is provided by the bus master driving SDATA <NUM> low at full strength. The bus master then drives SCLK <NUM> low and continues to drive SCLK <NUM> at full strength through subsequent bus idle intervals <NUM>, <NUM>. After driving SCLK <NUM> low, the bus master initiates a bus idle interval <NUM> at a time <NUM> when the bus master causes SDATA <NUM> to enter the weakly driven low signaling state <NUM>. The BPC <NUM> is terminated and the serial bus enters a bus idle interval <NUM> until the next datagram is ready for transmission.

Triggers provide a mechanism for RF front-end control, and triggers may be used to coordinate activities of different front-end components. For example, triggers can be used for a variety of purposes including beam steering or beamforming, gain setting, antenna path multiplexer control, etc. In some devices, triggers can be configured, activated and/or actuated over a serial bus operated in accordance with RFFE protocols. Trigger actuation may also be referred to as trigger firing. In one example, a trigger in a first device is actuated or fired after expiration of a timer, which may be configured and initiated by a second device. Actuation or firing of the trigger may initiate or cause an action to be taken in a circuit of the first device or by an application or function executed at the first device. In some examples, the trigger may be considered to have been actuated or fired when it causes an interrupt, signals an event, generates a message sets a flag, changes a register setting and/or enables one or more devices or circuits through an enable signal.

In some examples, a Bus Owner Master (BoM) may transmit a command that includes a trigger configuration and an action associated with the configured trigger, such that receipt of the command causes the trigger to be actuated or otherwise take effect or be applied. A trigger configured by the command may be referred to as a self-actuating trigger.

Advances in RF technology and the introduction of increased capabilities in communication devices increase pressure on latency times. For example, the deployment of radio access technologies such as the <NUM> New Radio technology defined by the 3rd Generation Partnership Project (3GPP) and the <NUM>. 11ax WLAN standard defined by the Institute of Electrical and Electronics Engineers (IEEE) <NUM> Working Group can require a <NUM>% reduction in latency at conventional bus clock frequencies, and necessitate increased complexity of RFFE bus architectures and may increase the potential for traffic congestion on the bus. RFFE bus congestion and timing bottlenecks may be expected to exacerbate coexistence issues. For example, increased bus activity may increase bus contention issues where RFFE bus timing is complicated. In these and other scenarios, a BoM may be prevented from sending triggers at the exact time needed by slave devices to meet the RF protocol timing.

In some systems, delayed triggers may be used to avoid bus congestion and timing bottlenecks and to ensure timely actuation of triggers. A BoM may configure one or more triggers and corresponding timers that control the actual timing of the configured triggers. For example, the BoM may define an action associated with the configured triggers and may configure or activate one or more counters or timers cause the triggers to be actuated at the desired time. Actuating a trigger causes or initiates the action associated with the trigger. The counter or timer may define the time of actuation as a number of clock cycles in the clock signal transmitted by the BoM to control timing on the serial bus.

<FIG> illustrates an example of a trigger actuation circuit <NUM> that may be used to configure, activate and actuate triggers. In the illustrated example, configuration information is received as a plurality of data bytes <NUM>, which may be stored in trigger configuration registers <NUM>. The trigger configuration registers <NUM> may be written through a configuration transaction conducted over a serial bus. The serial bus may be operated in accordance with an RFFE protocol, for example. The contents of the trigger configuration registers <NUM> may be forwarded to a target address, register or device in accordance with a trigger actuation signal <NUM> provided by a corresponding timer or counter. In one example, the timer or counter may be provided in a controlling circuit that is configured based on information provided by the BoM.

Trigger activation logic <NUM> may be configured to enable the contents of the trigger configuration registers <NUM> to be transferred to respective target devices in response to a trigger command or trigger actuation signal <NUM> provided by the controlling circuit. The trigger elements <NUM> may include switches <NUM>, LNAs <NUM>, <NUM>, PAs <NUM> and other types of device in an RF front-end. In one example, a BoM may configure a mask or gating logic that determines which trigger elements <NUM> are to receive data from the trigger configuration registers <NUM> during actuation initiated by a single trigger actuation signal <NUM>. In another example, the mask or gating logic may determine the trigger elements <NUM> that are to receive data from the trigger configuration registers <NUM> during actuation initiated by corresponding trigger actuation signals <NUM>.

Certain aspects disclosed herein provide mechanisms that enable a BoM to configure triggers with reliable delayed actuation. The triggers can be configured before the time defined for actuation, and a slave device may wait for a defined period of time before actuating the trigger. In one example, the BoM can send triggers ahead of time and when bus traffic conditions allow. A slave device may include configurable counters or timers that provide trigger actuation signals <NUM> based on timing provided by a clock signal transmitted over the serial bus by the BoM.

<FIG> illustrates an example of a system <NUM> configured in accordance with certain aspects disclosed herein. In one example, the system <NUM> includes a serial bus <NUM> that may be operated in accordance with an RFFE protocol. A BoM <NUM> and up to <NUM> slave devices <NUM><NUM>-<NUM><NUM> may be coupled to the serial bus <NUM>. The serial bus <NUM> includes a first line (SCLK <NUM>) that carries a clock signal and a second line (SDATA <NUM>) that carries a data signal. A first slave device <NUM><NUM>, for example, includes or incorporates the trigger actuation circuit <NUM> of <FIG>. The first slave device <NUM><NUM> also includes a counter <NUM> that may be configured to provide an actuation signal <NUM>. In one example, the counter <NUM> may be initially configured with a count value that is calculated to provide a desired or identified countdown period when the counter <NUM> is clocked by the clock signal transmitted on SCLK <NUM>. The counter <NUM> may be configured to decrement in response to each pulse received from the clock signal, and may be further configured to provide the actuation signal <NUM> that causes an intended trigger to be fired when the count value reaches zero.

The BoM <NUM> may initiate or activate the intended trigger, and may be configured to provide clock pulses in a clock signal until the counter value has reached zero. The timing accuracy of the actuation signal <NUM> typically relies on the pulses being provided in the clock signal at a fixed rate or frequency. The BoM <NUM> may be configured to provide clock pulses in the clock signal while a transaction is conducted over the serial bus <NUM>. For example, the BoM <NUM> provides clock pulses in the clock signal that define the timing of bits transmitted in a datagram transmitted over the serial bus <NUM>. The BoM <NUM> continues to provide clock pulses in the clock signal when transmission of the datagram has been completed and when no further datagrams are available for transmission. The BoM <NUM> may idle SDATA <NUM> while continuing to drive the clock signal on SCLK <NUM>. The pulses in the clock signal are provided at the same frequency as pulses provided during transmission of a datagram. The resulting clock signal causes the counter <NUM> to be decremented while the data signal is idle.

Certain RFFE protocols define a time-triggered architecture that corresponds to the trigger mechanisms described in relation to <FIG> and <FIG>. In many examples, a counter associated with a trigger begins to count down as soon as a countdown value is loaded. In a system that supports multiple triggers, two or more trigger counter are loaded using a common datagram. Each counter is loaded at a different point in time and the countdown operation begins at different times for each counter.

<FIG> illustrates an example of trigger timing <NUM> in a system operated according to RFFE protocols. The trigger timing <NUM> is derived from a datagram that includes trigger information used to configure multiple triggers. A portion of the payload of the datagram is illustrated. The payload is transmitted on SDATA <NUM> in accordance with timing provided in a clock signal transmitted on SCLK <NUM>. In the illustrated example, the payload includes five frames, each frame including an <NUM>-bit data byte 822a-822e and an associated parity bit. The value of the data byte 822a-822e in each of the frames may be multiplied by <NUM> (i.e., shifted one bit) before being loaded into a corresponding counter.

In one example, a first-received frame is transmitted using <NUM> cycles <NUM> of the clock signal transmitted on SCLK <NUM>. The data byte 822a may be multiplied by <NUM> and loaded into a first counter after a valid parity bit <NUM> is received. In the illustrated example, the first counter is loaded on the first falling edge <NUM> in the clock signal after the valid parity bit <NUM> is received. According to RFFE protocols, the counter begins a timeline <NUM> in which it counts down on each subsequent falling edge in the clock signal, including the next falling edge <NUM>.

Each of the other data bytes 822b-822e is loaded into corresponding counters after their respective valid parity bit is received, and each counter begins counting down one clock cycle after being loaded. The timelines <NUM>, <NUM>, <NUM>, <NUM>, <NUM> have different start points and span different durations, while being expected to end at one or more points in time defined by an application or the BoM. In one example, an application may define a sequence of triggers to be actuated or fired commencing at a first point in time and ending at a second point in time, where each trigger is provided at a designated point in time that can be accurately measured relative to the first point in time or to the second point in time.

Timing accuracy may also be compromised by the use of timing offsets, since the use of multiplied values as counter values can introduce a one clock period variance in triggers initiated by pairs of counters. In one example, the first counter and the second counter in <FIG> may be used to initiate triggers at some point in time measured as N clock cycles after the second counter is loaded. The timeline <NUM> for the second counter starts <NUM> clock cycles before the timeline <NUM> for the third counter. The BoM may configure the values of the data bytes 822b and 822c to accommodate the offset between start times of the counters used to provide timing for delayed triggers. The first counter is loaded with a value N+M, while the second counter is loaded with a value N. The value of M is selected to account for the <NUM>-cycle offset in timing between the start of counting by the two counters. The BoM can define the content of the data byte for the first counter as N/<NUM> + <NUM> or N/<NUM> + <NUM>, to obtain a counter of value (after multiplication by <NUM>) of N + <NUM> or N + <NUM>. The value of N + <NUM> is unobtainable under the described scheme.

In many systems, the overhead in calculating offsets for trigger timing may be further complicated when groups of triggers are defined. An application or BoM may define different groups of triggers, where each group of triggers is to be actuated or fired at the same point in time or with reference to the same point in time. Depending on trigger-grouping, the RFFE defined trigger procedures can result in a wide variation in the values to be loaded into the first-loaded counter. The variability in initial counter value can substantially increase procedural complexity for a single grouping within a set of triggers. Complexity increases further when multiple groups of triggers are defined and multiple initial values must be calculated for the first-loaded counters and/or when a timing relationship is defined between the groups of triggers.

<FIG> and <FIG> illustrate variability in first-loaded counter values. <FIG> illustrates a first example of group trigger timing <NUM> in a system operated according to RFFE protocols. In this example, triggers <NUM> and <NUM> are grouped. <FIG> illustrates a second example of group trigger timing <NUM> in a system operated according to RFFE protocols. In this example, triggers <NUM> and <NUM> are grouped.

Trigger timing <NUM>, <NUM> is derived from a datagram that includes trigger information used to configure at least two triggers. A portion of the payload of the datagram is illustrated. The payload is transmitted on SDATA <NUM>, <NUM> in accordance with timing provided in a clock signal transmitted on SCLK <NUM>, <NUM>. In the illustrated examples, the payload includes five frames, each frame including an <NUM>-bit data byte and an associated parity bit. The value of the data byte in each of the frames may be multiplied by <NUM> (i.e., shifted one bit) before being loaded into a corresponding counter.

A first-received frame is transmitted using <NUM> cycles <NUM>, <NUM> of the clock signal transmitted on SCLK <NUM>, <NUM>. The data byte <NUM>, <NUM> carried by the first-received frame may be multiplied by <NUM> and loaded into a first counter after a valid parity bit <NUM>, <NUM> is received. The first counter is loaded on the first falling edge <NUM>, <NUM> in the clock signal after the valid parity bit <NUM>, <NUM> is received. According to RFFE protocol, the counter begins a timeline <NUM>, <NUM> in which it counts down on each subsequent falling edge in the clock signal, including the next falling edge <NUM>, <NUM>.

One or more other data bytes are loaded into corresponding counters after their respective valid parity bit is received. In the example illustrated in <FIG>, the next counter loaded is the second counter, which is used to fire a trigger that is grouped with the trigger fired by the first counter. The second counter begins counting down one clock after being loaded. The timelines <NUM> and <NUM> have different start points separated in time by a <NUM>-clock cycle offset <NUM>, and both timelines <NUM> and <NUM> are expected to end at the same point in time. In the example illustrated in <FIG>, the fourth counter loaded is used to fire a trigger that is grouped with the trigger fired by the first counter. The fourth counter begins counting down one clock after being loaded. The timelines <NUM> and <NUM> have different start points separated in time by a <NUM>-clock cycle offset <NUM>, and both timelines <NUM> and <NUM> are expected to end at the same point in time.

Calculation of counter values can become complex when different sequences of triggers may be requested and/or when the combination of counters used can vary between trigger requests. The BoM may first configure a counter value for each trigger and may then calculate offsets for each trigger based on a knowledge of the sequence in which registers are to be written. The relative start-point for count down operation can vary based on the number of counters to be loaded using one datagram.

Certain aspects of this disclosure provide trigger timing mechanisms that can remove or reduce the burden of computation and that can decrease hardware complexity needed to support the use of counters that are loaded with variable offset-adjusted values when one or more groups of triggers are defined.

In one aspect, trigger timing is controlled using BPC detection to gate counter operation. <FIG> illustrates a first example of group trigger timing <NUM> in a system configured in accordance with certain aspects of this disclosure. Trigger timing <NUM> is derived from a datagram that includes trigger information used to configure at least two triggers. A portion of the payload of the datagram is illustrated. The payload is transmitted on SDATA <NUM> in accordance with timing provided in a clock signal transmitted on SCLK <NUM>. In the illustrated example, the payload includes five frames, each frame including an <NUM>-bit data byte and an associated parity bit. The value of the data byte in each of the frames may be multiplied by <NUM> (i.e., shifted one bit) before being loaded into a corresponding counter.

A first-received frame is transmitted using <NUM> cycles <NUM> of the clock signal transmitted on SCLK <NUM>. The data byte <NUM> carried by the first-received frame may be multiplied by <NUM> and loaded into a first counter after a valid parity bit <NUM> is received. The first counter is loaded on the first falling edge <NUM> in the clock signal after the valid parity bit <NUM> is received. One or more data bytes are loaded into corresponding counters after their respective valid parity bit is received. The counters are prevented from counting until a BPC <NUM> is detected <NUM> at the end of the datagram. In the illustrated example, all counters begin counting down at the falling edge <NUM> of the clock cycle following the BPC <NUM>.

The use of BPC timing to initiate countdown for all counters removes the need for the BoM to calculate offsets based on datagram configuration. All counters begin counting at the same time, and the countdown value represents the number of clock cycles between the BPC <NUM> and the desired point at which the triggers are to be fired. Two or more counters may be configured with a common value when their corresponding triggers are to be fired at the same point in time.

<FIG> also illustrates a conceptual gating circuit <NUM> that may be used in a system configured in accordance with certain aspects of this disclosure. Here, an AND gate blocks the clock signal received from SCLK <NUM> while a BPC detect signal <NUM> indicates that the BPC for the current datagram has not yet been detected. When the BPC for the current datagram is detected, the AND gate provides the clock signal received from SCLK <NUM> to one or more counters <NUM>. In one example, the AND gate provides the clock signal received from SCLK <NUM> to all counters <NUM> that were loaded with count values carried in the current datagram. In another example, the AND gate provides the clock signal received from SCLK <NUM> to all counters <NUM> used to provide timing for a predefined or preconfigured group of triggers. In another example, the AND gate provides the clock signal received from SCLK <NUM> to all counters <NUM> in a block of counters. In some examples, the BPC detect signal <NUM> may be latched or maintained until all of the counters <NUM> have reached an end value, which may be a zero value in some implementations.

In one aspect, trigger timing is controlled based on detection of completion of group counter loading. <FIG> illustrates an example of a group trigger timing counter <NUM> in a system configured in accordance with certain aspects of this disclosure. A group trigger timing counter <NUM> may be provided for each trigger supported by a device, such as an RFFE device or modem. RFFE protocols provide that each device may support up to <NUM> of the timed-triggers <NUM>, including "Block-A" timed triggers <NUM> and "Block-B" timed triggers <NUM>. Time-trigger operations are not supported for power mode triggers <NUM>.

In one example, the group trigger timing counter <NUM> includes a trigger group association register (the TGA register <NUM>) that provides up to <NUM> bits for mapping counters that are associated with a first group of triggers. These mapped counters are to be loaded when the first group of triggers is being configured. The device may include a counter-load detection register (the CLD register <NUM>) that identifies counters that have been loaded while the current datagram is being received. In one example, a CLD register <NUM> may be shared by multiple group trigger timing counters <NUM>. In another example, a CLD register <NUM> is provided for each group trigger timing counter <NUM>.

The group trigger timing counter <NUM> includes a counter <NUM> that is mapped to a trigger in the triggers <NUM>, <NUM> that may be referred to as the trigger-of-interest. A comparator <NUM> may be configured to determine when all counters associated with a group of triggers have been loaded based on bit settings in the TGA register <NUM> and the CLD register <NUM>. In one example, each bit in the TGA register <NUM> is mapped to a counter, and a bit that is set to logic <NUM> may be referred to as an active bit that represents a counter associated with a trigger belonging to the group of triggers that includes the trigger-of-interest. Each bit in the CLD register <NUM> is mapped to a counter and each bit in the CLD register <NUM> corresponds to a bit in the TGA register <NUM>. A bit in the CLD register <NUM> may be set to logic <NUM> when its associated counter has been loaded. A bit in the CLD register <NUM> set to logic <NUM> may be referred to as an active bit that represents a loaded counter. The comparator <NUM> provides an output signal <NUM> that is set to logic <NUM> when each bit in the CLD register <NUM> corresponding to an active bit in the TGA register <NUM> is active.

The output signal <NUM> is provided to an AND gate <NUM> that gates the clock signal transmitted on SCLK <NUM>. The AND gate <NUM> passes the clock signal to the counter <NUM> when the output signal <NUM> is set to logic <NUM> causing the counter to count down until it reaches zero count value when the counter <NUM> drives an output signal <NUM> that fires the trigger-of-interest. All bits in the CLD register <NUM> may be cleared when the trigger-of-interest is fired.

The use of group trigger timing counter <NUM> enables the synchronization of multiple trigger activations and may enable the trigger activations to be fired without waiting for a BPC, thereby enabling the triggers to be fired in fewer clock ticks. Countdown commences at the same time for all counters associated with a group of triggers and the BoM need not calculate offsets based on datagram configuration. In various examples, two or more counters may be configured with a common value when their corresponding triggers are part of the same trigger group and are to be fired at the same point in time.

<FIG> illustrates an example of the use of the group trigger timing counter <NUM> of <FIG> in a system <NUM> configured in accordance with certain aspects of this disclosure. Here, three triggers are grouped: Triggers T3, T7 and T16 are configured in a trigger group that is represented in the TGA registers <NUM>, <NUM>, <NUM> used to control the counters <NUM>, <NUM>, <NUM> associated with Triggers T3, T7 and T16. In each of the TGA registers <NUM>, <NUM>, <NUM>, the bit positions <NUM>, <NUM>, <NUM> associated with Triggers T3, T7 and T16 are set to logic <NUM>. The CLD registers <NUM>, <NUM>, <NUM> are initially cleared and the outputs <NUM>, <NUM>, <NUM> of the comparators <NUM>, <NUM>, <NUM> are consequently at logic zero, gating the counters <NUM>, <NUM>, <NUM>. In some instances, one or more CLD registers may be shared by the comparators <NUM>, <NUM>, <NUM>.

The counters <NUM>, <NUM>, <NUM> are loaded at different times, based on configuration or ordering of the datagram that carries counter values. <FIG> illustrates timing <NUM> related to an example of the comparators <NUM>, <NUM>, <NUM>. In this example, the counters <NUM>, <NUM>, <NUM> are loaded in order of the Triggers T3, T7 and T16. Other configurations of datagram, or RFFE interface addresses associated with the counters <NUM>, <NUM>, <NUM> may enable different sequences of loading. In the illustrated example, the counter <NUM> for T7 is loaded <NUM> clock cycles after the counter <NUM> for T1, and the counter <NUM> for T16 is loaded <NUM> clock cycles after the counter <NUM> for T7. Each of the counters <NUM>, <NUM>, <NUM> may be loaded with identical count values. The count values include no offsets associated with configuration or ordering of the datagram.

The clock signal transmitted on SCLK <NUM> may be used for clocking the counters <NUM>, <NUM>, <NUM> remains gated until all counters <NUM>, <NUM>, <NUM> have been loaded. Countdown operation begins when all counters <NUM>, <NUM>, <NUM> have been loaded, and the firing of Triggers T3, T7 and T16 is synchronized based on the values loaded in the counters <NUM>, <NUM>, <NUM>. All bits of the CLD registers <NUM>, <NUM>, <NUM> are automatically cleared when Triggers T3, T7 and T16 have been fired. The outputs <NUM>, <NUM>, <NUM> of the counters <NUM>, <NUM>, <NUM> are provided to activation circuits and may be used to activate, fire or actuate corresponding triggers.

In some implementations, a device may include one TGA register and one CLD register in order to support a single group of triggers. The single group of triggers may be provided to set gain, control antenna path multiplexers, adjust phase shifters and support other functions associated with beam steering or beamforming. In some implementations, multiple TGA registers may be used with multiple CLD registers to support multiple trigger groups that have greater timing flexibility. In some implementations, multiple TGA registers may be used with one CLD register to support multiple trigger groups with certain restrictions on trigger timing. For example, the use of a single CLD register can limit variations in timing between trigger groups since the CLD register is cleared after all triggers have been fired. In other implementations, flexibility can be provided in single-CLD register configurations using masking and/or using a CLD register in which bit settings can be cleared independently based on individual trigger firing.

<FIG> is a diagram illustrating an example of a hardware implementation for an apparatus <NUM>. In some examples, the apparatus <NUM> may perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using a processing circuit <NUM>. The processing circuit <NUM> may include one or more processors <NUM> that are controlled by some combination of hardware and software modules. Examples of processors <NUM> include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors <NUM> may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules <NUM>. The one or more processors <NUM> may be configured through a combination of software modules <NUM> loaded during initialization, and further configured by loading or unloading one or more software modules <NUM> during operation.

In the illustrated example, the processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including the one or more processors <NUM>, and storage <NUM>. Storage <NUM> may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. The bus <NUM> may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface <NUM> may provide an interface between the bus <NUM> and one or more transceivers or interfaces 1512a, 1512b. A transceiver or interface 1512a, 1512b may be provided for each networking technology supported by the processing circuit <NUM>. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver or interface 1512a, 1512b. Each transceiver or interface 1512a, 1512b provides a means for communicating with various other apparatus over a transmission medium. In one example, a transceiver or interface 1512a may be used to couple the apparatus <NUM> to a multi-wire bus. In another example, a transceiver or interface 1512b may be used to connect the apparatus <NUM> to a radio access network. Depending upon the nature of the apparatus <NUM>, a user interface <NUM> (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus <NUM> directly or through the bus interface <NUM>.

In this respect, the processing circuit <NUM> may be used to implement any of the methods, functions and techniques disclosed herein.

One or more processors <NUM> in the processing circuit <NUM> may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage <NUM> or in an external computer-readable medium. The external computer-readable medium and/or storage <NUM> may include a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a "flash drive," a card, a stick, or a key drive), RAM, ROM, a programmable read-only memory (PROM), an erasable PROM (EPROM) including EEPROM, a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or storage <NUM> may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Computer-readable media and/or the storage <NUM> may reside in the processing circuit <NUM>, in the processor <NUM>, external to the processing circuit <NUM>, or be distributed across multiple entities including the processing circuit <NUM>. The computer-readable medium and/or storage <NUM> may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The storage <NUM> may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules <NUM>. Each of the software modules <NUM> may include instructions and data that, when installed or loaded on the processing circuit <NUM> and executed by the one or more processors <NUM>, contribute to a run-time image <NUM> that controls the operation of the one or more processors <NUM>. When executed, certain instructions may cause the processing circuit <NUM> to perform functions in accordance with certain methods, algorithms and processes described herein.

Some of the software modules <NUM> may be loaded during initialization of the processing circuit <NUM>, and these software modules <NUM> may configure the processing circuit <NUM> to enable performance of the various functions disclosed herein. For example, some software modules <NUM> may configure internal devices and/or logic circuits <NUM> of the processor <NUM>, and may manage access to external devices such as a transceiver or interface 1512a, 1512b, the bus interface <NUM>, the user interface <NUM>, timers, mathematical coprocessors, and so on. The software modules <NUM> may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit <NUM>. The resources may include memory, processing time, access to a transceiver or interface 1512a, 1512b, the user interface <NUM>, and so on.

The one or more processors <NUM> may additionally be adapted to manage background tasks initiated in response to inputs from the user interface <NUM>, the transceiver or interface 1512a, 1512b, and device drivers, for example. When a task has control of the one or more processors <NUM>, the processing circuit <NUM> is effectively specialized for the purposes addressed by the function associated with the controlling task.

<FIG> is a flowchart <NUM> of a method for managing triggering that may be performed by a device coupled to a serial bus. In one example, the serial bus may be operated in accordance with an RFFE protocol. At block <NUM>, the device receives a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to a plurality of counters. At block <NUM>, the device configures each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram. At block <NUM>, the device causes each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values. At block <NUM>, the device actuates a trigger when a counter associated with the trigger has counted to zero.

In various examples, the plurality of data bytes defines a timing sequence for a plurality of triggers. Each trigger in the plurality of triggers is actuated when an associated counter in the plurality of counters has counted to zero. The timing sequence may be configured to cause two or more triggers in the plurality of triggers to be actuated at the same time. In one example, the device may enable each of the plurality of counters to begin counting at the same time. Two or more data bytes in the plurality of data bytes have the same value.

In one example, the device may detect a BPC on the serial bus, and may enable each of the plurality of counters to count when the BPC is detected.

In some examples, the device may populate a first register with a bit pattern that identifies the members of a group of triggers. Each counter in the plurality of counters may be associated with a trigger identified as a member of the group of triggers, The device may provide a second register that indicates which counters in the plurality of counters have been configured and control state of an enable signal provided to each of the plurality of counters based on a comparison of the first register and the second register. The second register may be cleared after each trigger identified as a member of the group of triggers has been actuated.

<FIG> is a diagram illustrating a simplified example of a hardware implementation for an apparatus <NUM> employing a processing circuit <NUM>. The processing circuit <NUM> typically has a controller or processor <NUM> that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers and/or state machines. The processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including one or more processors and/or hardware modules, represented by the controller or processor <NUM>, the modules or circuits <NUM>, <NUM> and <NUM> and the processor-readable storage medium <NUM>. One or more physical layer circuits and/or modules <NUM> may be provided to support communications over a communication link implemented using a serial bus <NUM>, through an antenna or antenna array <NUM> (to a radio access network for example), and so on. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processor <NUM> is responsible for general processing, including the execution of software, code and/or instructions stored on the processor-readable storage medium <NUM>. The processor-readable storage medium <NUM> may be implemented using a non-transitory storage medium. The software, when executed by the processor <NUM>, causes the processing circuit <NUM> to perform the various functions described supra for any particular apparatus. The processor-readable storage medium <NUM> may be used for storing data that is manipulated by the processor <NUM> when executing software. The processing circuit <NUM> further includes at least one of the modules <NUM>, <NUM> and <NUM>. The modules <NUM>, <NUM> and <NUM> may be software modules running in the processor <NUM>, resident/stored in the processor-readable storage medium <NUM>, one or more hardware modules coupled to the processor <NUM>, or some combination thereof. The modules <NUM>, <NUM> and <NUM> may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, the apparatus <NUM> includes modules and/or circuits <NUM> adapted to maintain configuration information relating to trigger groupings and status of counters that are used for implementing delays in corresponding triggers. The apparatus <NUM> may include modules and/or circuits <NUM> adapted to fire, actuate or activate triggers. The apparatus <NUM> may include modules and/or circuits <NUM> adapted to configure, manage, enable and otherwise control operation of the counters that are used for implementing delays in corresponding triggers.

In one example, the apparatus <NUM> includes physical layer circuits and/or modules <NUM> that implement an interface circuit adapted to couple the apparatus <NUM> to a serial bus <NUM> and that are configured to receive a clock signal from the serial bus <NUM>. The apparatus <NUM> may have a controller and a plurality of counters configured to count pulses in the clock signal. The controller is configured to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to the plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero. The datagram may be configured in accordance with RFFE protocols, for example.

In one example, the plurality of data bytes defines a timing sequence for a plurality of triggers. In various examples, each trigger in the plurality of triggers is actuated when an associated counter in the plurality of counters has counted to zero. The timing sequence may be configured to cause two or more triggers in the plurality of triggers to be actuated at the same time. The controller may be further configured to enable each of the plurality of counters to begin counting at the same time.

In one example, the interface circuit is further configured to detect a BPC on the serial bus. The controller may be further configured to enable each of the plurality of counters to count when the BPC is detected.

In certain examples, the apparatus <NUM> includes a first register populated with a bit pattern that identifies the members of a group of triggers, and a second register configured to indicate which counters in the plurality of counters have been configured. Each counter in the plurality of counters may be associated with a trigger identified as a member of the group of triggers. The apparatus <NUM> may include a comparator configured to compare the first register and the second register and to control state of an enable signal provided to each of the plurality of counters based on a comparison of the first register and the second register. The second register may be cleared after each trigger identified as a member of the group of triggers has been actuated. In some instances, two or more data bytes in the plurality of data bytes have the same value.

The processor-readable storage medium <NUM> includes instructions that cause the processing circuit <NUM> to receive a datagram from the serial bus, the datagram including a plurality of data bytes corresponding to a plurality of counters, configure each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram, cause each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values, and actuate a trigger when a counter associated with the trigger has counted to zero. The datagram may be configured in accordance with RFFE protocols, for example.

In one example, the plurality of data bytes defines a timing sequence for a plurality of triggers. In various examples, each trigger in the plurality of triggers is actuated when an associated counter in the plurality of counters has counted to zero. The timing sequence may be configured to cause two or more triggers in the plurality of triggers to be actuated at the same time. In some examples, the processor-readable storage medium <NUM> includes further instructions that cause the processing circuit <NUM> to enable each of the plurality of counters to begin counting at the same time.

In one example, the processor-readable storage medium <NUM> includes further instructions that cause the processing circuit <NUM> to detect a BPC on the serial bus, and to enable each of the plurality of counters to count when the BPC is detected.

In some examples, the processor-readable storage medium <NUM> includes further instructions that cause the processing circuit <NUM> to populate a first register with a bit pattern that identifies the members of a group of triggers. Each counter in the plurality of counters may be associated with a trigger identified as a member of the group of triggers. The processor-readable storage medium <NUM> may include further instructions that cause the processing circuit <NUM> to provide a second register that indicates which counters in the plurality of counters have been configured, and control state of an enable signal provided to each of the plurality of counters based on a comparison of the first register and the second register. The second register may be cleared after each trigger identified as a member of the group of triggers has been actuated. Two or more data bytes in the plurality of data bytes may have the same value.

It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Further, some steps may be combined. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

Claim 1:
A method (<NUM>) for managing triggering in a device (<NUM>, 220_0-222_N, 708_1-708_15) coupled to a serial bus (<NUM>, <NUM>), comprising:
receiving (<NUM>) a datagram (<NUM>, <NUM>, <NUM>, <NUM>) from the serial bus (<NUM>, <NUM>), the datagram (<NUM>, <NUM>, <NUM>, <NUM>) including a plurality of data bytes (<NUM>, <NUM>, <NUM>, 822a-e) corresponding to a plurality of counters;
configuring (<NUM>) each of the plurality of counters with a count value based on content of a corresponding data byte when the corresponding data byte is received from the datagram (<NUM>, <NUM>, <NUM>, <NUM>);
causing (<NUM>) each of the plurality of counters to refrain from counting until all of the plurality of counters have been configured with count values; and
actuating (<NUM>) a trigger when a counter associated with the trigger has counted to zero.