Patent Description:
Planar semiconductor devices, such as memory cells, are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the semiconductor devices approach a lower limit, planar process and fabrication techniques become challenging and costly. A three-dimensional (3D) device architecture can address the density limitation in some planar semiconductor devices, for example, flash memory devices. The <CIT> describes a parallelogram cell design for high speed vertical channel 3d nand memory. The <CIT> describes a semiconductor memory device. The <CIT> describes a 3d memory device. The <CIT> describes a nonvolatile semiconductor memory device. <CIT> discloses a string selection structure of three-dimensional semiconductor device.

Embodiments of 3D memory devices are disclosed herein.

One aspect relates to a 3D memory device according to claim <NUM>.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

As used herein, the terms "over" and "above" are employed to describe the spatial relationship between bit lines and memory strings. In some embodiments, the description of "a bit line over a memory string" or similar refers to the spatial relationship of which the bit line is loosely over the memory string, and the orthogonal projections of the bit line and the memory string may or may not have overlaps on a lateral plane. In some embodiments, the description of "a bit line above a memory string" or similar refers to the spatial relationship of which the orthogonal projections of the bit line and the memory string have at least partial overlaps on a lateral plane.

As used herein, the x-direction (or the x-axis) and the y-direction (or the y-axis) represent two orthogonal lateral directions. As used herein the z-direction (or the z-axis) represents a direction/axis that is perpendicular to the x-direction and the y-direction.

In the present disclosure, plan views are employed to depict the electrical and spatial relationship between components (e.g., bit lines and memory strings). In some embodiments, as shown in <FIG>, the connection between a bit line and a memory string is shown as the connection between an upper portion (e.g., the drain) of the memory string and the bit line in the plan view.

In a 3D memory device, GLSs divide an array region into multiple memory regions (e.g., fingers) for data access and storage. memory strings, often arranged as an array, are distributed in a memory region, forming memory cells for various data operations such as read, write, and erase. A memory string often includes a channel structure, a drain at an upper portion of the memory string over the channel structure, and a source at a lower portion of the memory string below the channel structure. The source is part of or electrically connected to an array common source (ACS) of the memory strings in the memory region. Bit lines are arranged in parallel over the channel structures and across the GLSs. The drain is electrically connected to one of the bit lines. A memory region often includes a top select gate cut (TSG cut, often includes a dielectric material) that divides a memory region into two even sub-regions (e.g., pages). A bit line is electrically connected to a memory string in one page and another memory string in the other page so a data operation can be performed in the memory cells of one page at a time. In a plan view, often four bit lines are arranged in a channel pitch (e.g., a lateral distance between adjacent channel structures or between adjacent memory strings) in each page so a bit line pitch (e.g., a lateral distance between two adjacent bit lines) is nominally equal to ¼ of a channel pitch.

<FIG> illustrates a plan view of a 3D memory device <NUM>, not falling under the scope of the present invention, but useful for understanding it. As shown in <FIG>, in 3D memory device <NUM>, a plurality of memory strings <NUM> (e.g., <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) is distributed as an array extending along a first lateral direction (e.g., the x-direction) and a second lateral direction (e.g., the y-direction) in memory region <NUM> (e.g., memory finger). Memory strings <NUM> extend vertically and laterally in a memory stack <NUM> of interleaved conductor layers and insulating layers. GLSs <NUM> extend along the first lateral direction and separate memory region <NUM> from other devices/regions. TSG cut <NUM> extends along the first lateral direction and divides memory region <NUM> into pages <NUM>-<NUM> and <NUM>-<NUM>. Each page <NUM>-<NUM>/<NUM>-<NUM> includes four string rows (e.g., rows of memory strings <NUM>) extending along the first lateral direction. In a plan view, TSG cut <NUM> overlaps with a string row (e.g., including memory string <NUM>-<NUM>) between pages <NUM>-<NUM> and <NUM>-<NUM>. A plurality of bit lines <NUM> extend along the second lateral direction across memory region <NUM>. Each bit line <NUM> is electrically connected to a memory string <NUM> in page <NUM>-<NUM> and another memory string <NUM> in page <NUM>-<NUM>. For example, bit line <NUM>-<NUM> is electrically connected in memory string <NUM>-<NUM> in page <NUM>-<NUM> and memory string <NUM>-<NUM> in page <NUM>-<NUM>.

As shown in <FIG>, a channel pitch CP refers to the lateral distance between two adjacent memory strings <NUM> along a lateral direction (e.g., the first lateral direction). A bit line pitch P0 refers to the lateral distance between two adjacent bit lines <NUM> along a lateral direction (e.g., the first lateral direction). In a plan view, as shown in <FIG>, four bit lines <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are arranged in a channel pitch CP, electrically connected to four memory strings in each page <NUM>-<NUM>/<NUM>-<NUM>. Bit line pitch P0 is nominally equal to ¼ of channel pitch CP.

3D memory device <NUM> can have some drawbacks. For example, the number of functional memory strings <NUM> (or functional memory cells) between GLSs <NUM> can be limited by the area occupied by TSG cut <NUM> and the number of string rows in each page <NUM>-<NUM>/<NUM>-<NUM>. As shown in <FIG>, TSG cut <NUM> is located between pages <NUM>-<NUM> and <NUM>-<NUM>, resulting in a non-functional string row (e.g., the string row that memory string <NUM>-<NUM> is located in) between pages <NUM>-<NUM> and <NUM>-<NUM>. At a given time, four memory strings <NUM> in a channel pitch CP of one page (e.g., <NUM>-<NUM> or <NUM>-<NUM>) can be accessed. A page size (e.g., data capacity) of page <NUM>-<NUM>/<NUM>-<NUM> is limited by bit line pitch P0, which is nominally ¼ of channel pitch CP. One way to increase the page size is to increase the number of memory strings <NUM> along the first lateral direction. However, this approach can increase the dimension of the conductor layers along the first lateral direction, causing increased read time and program time of the 3D memory device.

Various embodiments in accordance with the present disclosure provide architectures of 3D memory devices that have reduced bit line pitches and increased bit densities, thus an increased number of bit lines in the memory region. Bit density is herein defined as the number of data bits (or data capacity) per unit area. In some embodiments, each bit line arranged in a channel pitch is electrically connected to a single memory string in the memory region, and no TSG cut needs to be formed in the memory region. The respective 3D memory devices may function without any TSG cuts, increasing the bit density of the memory region. In a plan view, at least six bit lines are arranged in a channel pitch, allowing at least six memory strings to be formed in the channel pitch. This architecture can also desirably reduce the dimension of conductor layers along the first lateral direction, thus reducing RC time constant of the conductor layers and resulting in faster read and program operations. More memory strings (or memory cells) can be accessed at a given time, increasing page size and data throughput.

In some embodiments, a 3D memory device includes one or more TSG cuts between GLSs and an increased number of bit lines arranged in each channel pitch. The TSG cuts can divide the memory region into two or more pages. As an example, one TSG cut is formed between GLSs to form two pages in the memory region, and six or more bit lines can be arranged in a channel pitch. Each bit line may be electrically connected to one memory string in one page and another memory string in the other page. This architecture allows six or more string rows to be accessed at a given time in the respective page, increasing bit density and page size. Similarly, dimension of conductor layers along the first lateral direction can be reduced, resulting faster read and program operations.

<FIG> illustrates a plan view of an exemplary 3D memory device <NUM>, according to some embodiments of the present disclosure, not falling under the scope of the present invention, but useful for understanding it. 3D memory device <NUM> may include a memory stack <NUM> that has a memory region <NUM> (e.g., a finger), one or more slit structures <NUM> (e.g., GLSs) along a boundary of memory region <NUM>, a plurality of memory strings <NUM> (such as NAND memory strings) distributed in memory region <NUM>, and a plurality of bit lines <NUM> arranged in parallel over memory strings <NUM> along the second lateral direction. At least one of bit lines <NUM> is electrically connected to a single memory string <NUM>. In some embodiments, each bit line <NUM> is electrically to a single different memory string <NUM>. In some embodiments, no TSG cut is formed in memory region <NUM> (e.g., no TSG cut overlaps with any memory strings <NUM> in the plan view). Memory string <NUM> may include a channel structure, a drain at an upper portion of memory string <NUM> and over the channel structure, and a source at a lower portion of memory string <NUM> and below the channel structure. The source is part of or electrically connected to an ACS of memory strings <NUM> in the memory region. The drain is electrically connected to a respective bit line <NUM>. Without further illustration, memory strings <NUM> and <NUM> depicted in <FIG> and <FIG> have similar or same structures.

As shown in <FIG>, memory strings <NUM> may be arranged in an array extending along the first lateral direction and the second lateral direction. Memory strings <NUM> may be arranged in a plurality of string rows along the second lateral direction and a plurality of string columns along the first lateral direction. Bit lines <NUM> may extend along the second lateral direction over memory strings <NUM>. In some embodiments, a channel pitch CP includes N memory strings, arranged in N string rows along the second lateral direction. Memory strings <NUM> in adjacent string rows may be arranged in a staggered pattern, as shown in <FIG>. In some embodiments, in a plan view, N bit lines are arranged in channel pitch CP between slit structures <NUM>. Each of the N bit lines is electrically connected to a single different memory string <NUM>. The N bit lines are evenly spaced in channel pitch CP. In some embodiments, a bit line pitch P1 is nominally equal to <NUM>/N of channel pitch CP. 3D memory device <NUM> may allow memory strings <NUM> in memory region <NUM> to be accessed at the same time during a data operation. Compared to 3D memory device <NUM>, the lateral dimension of bit line <NUM> along the first lateral direction is reduced, the number of bit lines in a channel pitch doubles, and data throughput and page size each also doubles. Because no TSG cut is formed in memory region <NUM>, bit density of 3D memory device <NUM> may be increased by about <NUM>% in one example.

For example, in the plan view, eight bit lines (e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) may be arranged in channel pitch CP, over and connected to eight memory strings (e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>). In some embodiments, each bit line <NUM> is electrically connected to a single different memory string <NUM>. As shown in <FIG>, bit line <NUM>-<NUM> is electrically connected to memory string <NUM>-<NUM>, bit line <NUM>-<NUM> is electrically connected to memory string <NUM>-<NUM>,. , bit line <NUM>-<NUM> is electrically connected to memory string <NUM>-<NUM>. Bit lines <NUM>-<NUM>,. , <NUM>-<NUM> may be evenly spaced, and bit line pitch P1 may be nominally equal to <NUM>/<NUM> of channel pitch CP.

In some embodiments, four bit lines <NUM> are arranged above each memory string <NUM>. In the present disclosure, a bit line being above a memory string can refer to the orthogonal projections of the bit line the memory string being at least partially overlapping with one another in the lateral plane (e.g., the x-y plane). For example, bit lines <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> may be above each of memory strings <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>; and bit lines <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> may be above each of memory strings <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. In some embodiments, bit lines <NUM> are formed by a multi-patterning process. In some embodiments, the number of bit lines <NUM> arranged in channel pitch CP is determined based on design and fabrication processes. The number of bit lines <NUM> arranged in channel pitch CP may be even or odd. In some embodiments, the number is an even integer of at least <NUM>. By forming more bit lines <NUM> in channel pitch CP, more memory strings <NUM> can be accessed at a given time, increasing page size of the 3D memory device.

The formation of TSG cuts is optional in this architecture. When no TSG cut is formed, finger width W1 (e.g., lateral distance between GLSs along the second lateral direction) is reduced. At a given page size, less area in memory region <NUM> may be used for forming memory strings <NUM>, resulting in a reduced finger length L1 (e.g., lateral distance of a finger along the first lateral direction). Accordingly, the dimension of conductor layers of memory stack <NUM> along the first lateral dimension can be reduced, causing reduced RC time constant of the conductor layers. The device response time (e.g., response time for data operations such as read and program operations) can be reduced.

<FIG> illustrates a plan view of another 3D memory device <NUM>, according to some embodiments of the present disclosure, not falling under the scope of the present invention, but useful for understanding it. 3D memory device <NUM> may include a memory stack <NUM> that has a memory region <NUM> (e.g., a finger), one or more slit structures <NUM> (e.g., GLSs) <NUM> along a boundary of memory region <NUM>, a plurality of memory strings <NUM> (or memory strings <NUM>) distributed in memory region <NUM>, and a plurality of bit lines <NUM> arranged in parallel over memory strings <NUM> along the second lateral direction. At least one of bit lines <NUM> is electrically connected to a single memory string <NUM>. In some embodiments, each bit line <NUM> is electrically to a single different memory string <NUM>. In some embodiments, no TSG cut is formed in memory region <NUM> (e.g., no TSG cut overlaps with any memory strings <NUM> in the plan view).

Different from 3D memory device <NUM>, in the plan view, six bit lines <NUM> (e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) may be arranged in a channel pitch CP, over and electrically connected to six memory strings <NUM> (e.g., <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>). For example, bit line <NUM>-<NUM> is electrically connected to memory string <NUM>-<NUM>, bit line <NUM>-<NUM> is electrically connected to memory string <NUM>-<NUM>,. , bit line <NUM>-<NUM> is electrically connected to memory string <NUM>-<NUM>. Bit lines <NUM>-<NUM>,. , <NUM>-<NUM> may be evenly spaced, and a bit line pitch P2 may be nominally equal to <NUM>/<NUM> of channel pitch CP. In some embodiments, three bit lines <NUM> are arranged above each memory string <NUM>. For example, bit lines <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> may be above each of memory strings <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>; and bit lines <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> may be above each of memory strings <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. In some embodiments, bit lines <NUM> are formed by a multi-patterning process.

Compared to 3D memory device <NUM>, bit line pitch P2 is reduced to <NUM>/<NUM> of channel pitch CP and no TSG cut is formed in memory region <NUM>. Finger length L2 and finger width W2 of memory region <NUM> may both be reduced. Page size and data throughout may each be increased by about <NUM>%. Given the same page size, the RC time constant of conductor layers may be reduced by at least <NUM>%. In some embodiments, bit density of 3D memory device <NUM> is similar to 3D memory device <NUM>.

In some embodiments, no TSG cuts are formed in memory regions (e.g., fingers) <NUM> and <NUM>, and conductor layers extend continuously along the x-direction and/or the y-direction. That is, at least the first conductor layer (e.g., the conductor on the topmost portion of the conductor layers) may extend continuously along a lateral direction it extends. In some embodiments, the first conductor layer extends continuously along a lateral direction it extends. In some embodiments, one or more conductor layers under the first conductor layer extend continuously along a lateral direction they extend. In some embodiments, all conductor layers extend continuously along a lateral direction they extend.

<FIG> illustrates a plan view of another 3D memory device <NUM>, according to the invention. 3D memory device <NUM> includes a memory stack <NUM> that has a memory region <NUM>, one or more slit structures (or GLSs) <NUM> along a boundary of memory region <NUM>, a plurality of memory strings <NUM> (or memory strings <NUM>) distributed in memory region <NUM>, a TSG cut <NUM> (or cut structure) extending along the first lateral direction, and a plurality of bit lines <NUM> arranged in parallel over memory strings <NUM> along the second lateral direction. TSG cut <NUM> divides memory region <NUM> into memory sub-regions (<NUM>-<NUM> and <NUM>-<NUM> (e.g., memory pages)), each including a portion of the array of memory strings <NUM>. In the plan view, TSG cut <NUM> overlaps with a string row along the second lateral direction and divides the array of memory strings <NUM> into two even portions (e.g., two portions with the same number of memory strings <NUM> and/or same/symmetric arrangement of memory strings <NUM>).

In the plan view, each bit line <NUM> is electrically connected to one memory string <NUM> in memory sub-region <NUM>-<NUM> and another memory string <NUM> in memory sub-region <NUM>-<NUM>. Each memory string <NUM> in the same memory sub-region <NUM>-<NUM>/<NUM>-<NUM> is electrically connected to a different bit line <NUM>. In the plan view, N bit lines are arranged in channel pitch CP. The number of memory strings <NUM> arranged in channel pitch in each memory sub-region <NUM>-<NUM>/<NUM>-<NUM> (e.g., between GLS <NUM> and TSG cut <NUM>) may be equal to N. N may be at least <NUM>. In some embodiments, the N bit lines are evenly arranged in channel pitch CP, and a bit line pitch P3 is nominally equal to <NUM>/N of channel pitch CP. In some embodiments, memory region <NUM> includes <NUM> string rows, and each of memory sub-regions <NUM>-<NUM> and <NUM>-<NUM> includes six string rows extending along the second lateral direction. In some embodiments, <NUM> bit lines are above each memory string <NUM> in the plan view.

For example, as shown in <FIG>, bit lines <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> may be arranged in channel pitch CP and over memory strings <NUM>-<NUM>, <NUM>-<NUM>,. , and <NUM>-<NUM> in memory sub-region <NUM>-<NUM> and memory strings <NUM>-<NUM>, <NUM>-<NUM>,. , and <NUM>-<NUM> in memory sub-region <NUM>-<NUM>. Bit line <NUM>-<NUM> is electrically connected to memory strings <NUM>-<NUM> and <NUM>-<NUM>, bit line <NUM>-<NUM> is electrically connected to memory strings <NUM>-<NUM> and <NUM>-<NUM>, bit line <NUM>-<NUM> is electrically connected to memory strings <NUM>-<NUM> and <NUM>-<NUM>, bit line <NUM>-<NUM> is electrically connected to memory strings <NUM>-<NUM> and <NUM>-<NUM>, bit line <NUM>-<NUM> is electrically connected to memory strings <NUM>-<NUM> and <NUM>-<NUM>, and bit line <NUM>-<NUM> is electrically connected to memory strings <NUM>-<NUM> and <NUM>-<NUM>. Bit lines <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are above each of memory strings <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. Bit lines <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are above each of memory strings <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>.

Compared to 3D memory device <NUM>, bit line pitch P3 is reduced to <NUM>/<NUM> of channel pitch CP and TSG cut is formed in memory region <NUM>. Page size and data throughout may each be increased by about <NUM>%. In some embodiments, bit density of 3D memory device <NUM> is increased by about <NUM>% compared to 3D memory device <NUM>.

<FIG> illustrate cross-sectional views of a 3D memory device at various stages of an exemplary fabrication process, according to some embodiments of the present disclosure. <FIG> is a flowchart describing fabrication method <NUM> that forms a 3D memory device. The specific order and fabrication methods of operations <NUM>-<NUM> are subjected to different designs and fabrication requirements, and should not be limited by the embodiments of the present disclosure. <FIG> is an exemplary system <NUM> (e.g., a bonded semiconductor device) that includes a 3D memory device described in the present disclosure.

It is noted that x and y axes/directions are included in <FIG> and <FIG> to further illustrate the spatial relationship of the components in 3D memory device having a substrate <NUM> and system <NUM> having a substrate <NUM>. Substrate <NUM> and substrate <NUM> each includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device or bonded semiconductor device) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM> or substrate <NUM>) in the y-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationship is applied throughout the present disclosure.

Referring to <FIG>, method <NUM> includes operation <NUM>, in which a dielectric stack is formed on a substrate. The substrate which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials. The dielectric stack can include a plurality of dielectric/sacrificial layer pairs.

As illustrated in <FIG>, pairs of a first dielectric layer <NUM> and a second dielectric layer (known as a "sacrificial layer") <NUM> (together referred to herein as "dielectric layer pairs") are formed over a substrate <NUM>. The stacked dielectric layer pairs can form a dielectric stack <NUM>. In some embodiments, an isolation layer <NUM>, such as a silicon oxide film, is formed between substrate <NUM> and dielectric stack <NUM>. Dielectric stack <NUM> can include an alternating stack of sacrificial layer <NUM> and dielectric layer <NUM> that is different from sacrificial layer <NUM>. In some embodiments, each dielectric layer pair includes a layer of silicon nitride and a layer of silicon oxide. In some embodiments, sacrificial layers <NUM> can each have the same thickness or have different thicknesses. Similarly, dielectric layers <NUM> can each have the same thickness or have different thicknesses. Isolation layer <NUM> and dielectric stack <NUM> can be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a plurality of memory strings each extending vertically through the dielectric stack are formed. As illustrated in <FIG>, memory strings <NUM> are formed on substrate <NUM>, each of which extends vertically through dielectric stack <NUM> and above substrate <NUM>. In some embodiments, each memory string <NUM> can include a lower semiconductor plug <NUM> and an upper semiconductor plug <NUM> at its lower portion and upper portion, respectively. Lower semiconductor plug <NUM> can be at least part of the source of memory string <NUM> (e.g., ACS of the memory strings in the respective memory region). In some embodiments, fabrication processes to form memory string <NUM> include etching a channel hole through dielectric stack <NUM> and forming lower semiconductor plug <NUM> at the lower portion of the channel hole. The channel hole can be formed by dry etching and/or wet etching, such as deep reactive ion etching (RIE), and lower semiconductor plug <NUM> can be epitaxially grown from substrate <NUM> into the lower portion of the channel hole.

In some embodiments, fabrication processes to form memory string <NUM> also include forming a memory film <NUM> along the sidewalls of the channel hole. Memory film <NUM> can be a combination of multiple dielectric layers including, but not limited to, a tunneling layer, a storage layer, and a blocking layer. Tunneling layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Storage layer can include materials for storing charge for memory operation. The storage layer materials can include, but not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. The blocking layer can include dielectric materials including, but not limited to, silicon oxide or a combination of silicon oxide/silicon oxynitride/silicon oxide (ONO). The blocking layer can further include a high-k dielectric layer, such as an aluminum oxide layer.

In some embodiments, fabrication processes to form memory string <NUM> also include forming a semiconductor channel <NUM> over memory film <NUM> and forming a filling layer <NUM> over semiconductor channel <NUM> to partially or fully fill the remaining space of the channel hole. Semiconductor channel <NUM> can include semiconductor materials, such as polysilicon. Filling layer <NUM> can include dielectric materials, such as silicon oxide. Filling layer <NUM>, semiconductor channel <NUM>, and memory film <NUM> can be formed by processes such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

The upper semiconductor plug <NUM> is formed at the upper portion of memory string <NUM> as the drain of memory string <NUM>. Upper semiconductor plug <NUM> is formed by etching back the upper portion of memory string <NUM> by dry etching and/or wet etching, followed by one or more deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to deposit a semiconductor material, such as polysilicon, into the recess formed by the etching-back process.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a memory stack is formed from the dielectric stack and slit structure is formed in the memory stack. As illustrated in <FIG>, a slit structure <NUM> is formed to extend vertically in a memory stack <NUM> formed from dielectric stack <NUM>. Slit structure <NUM>, corresponding to the slit structures <NUM>, <NUM>, and <NUM> depicted in <FIG>, may include a dielectric structure <NUM> and a source contact <NUM> in dielectric structure <NUM>. Source contact <NUM> may extend to substrate <NUM> and be electrically connected to the ACS of memory strings <NUM>. In some embodiments, dielectric stack <NUM> is repetitively etched to form a staircase structure of dielectric/sacrificial layer pairs. A slit opening may be formed in the staircase structure, exposing substrate <NUM>. The slit opening may correspond to slit structure <NUM>. The etched sacrificial layers may then be replaced, with a plurality of conductor layers, in the dielectric/sacrificial layer pairs through the slit opening to form a plurality of conductor/dielectric layer pairs (e.g., <NUM>-<NUM>/<NUM>-<NUM>). The conductor layers <NUM>-<NUM> may include any suitable conductive material such as tungsten, copper, aluminum, and/or cobalt. In some embodiments, the slit opening is filled with a dielectric material, and a conductive material is formed in the dielectric material, forming dielectric structure <NUM> and source contact <NUM>. Source contact may be electrically connected to the ACS of memory strings <NUM>. The dielectric structure may include any suitable dielectric materials such as silicon oxide, silicon nitride, and/or silicon oxynitride. The source contact may be made of any suitable conductive material such as tungsten, copper, cobalt, aluminum, silicon, and/or silicides. In some embodiments, word line via contacts (or via contacts) that are electrically connected to conductor layers <NUM>-<NUM> are formed.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a plurality of bit lines are formed over the memory strings. In some embodiments, at least one of the plurality of bit lines is electrically connected to a single one of the plurality of memory strings. In some embodiments, at least three bit lines are above one memory string. An array interconnect layer, including a plurality of interconnects in one or more inter-layer dielectric (ILD) layers, may be formed. As illustrated in <FIG>, an array interconnect layer <NUM> can be formed above dielectric stack <NUM> and memory strings <NUM>. Array interconnect layer <NUM> can include interconnects, such as bit lines <NUM>, in one or more ILD layers for transferring electrical signals to and from memory strings <NUM>. In some embodiments, bit line contacts <NUM> can be formed in an ILD layer formed above memory stack <NUM> prior to forming array interconnect layer <NUM>, such that each bit line contact <NUM> is above and in contact with upper semiconductor plug <NUM> (the source) of corresponding memory string <NUM> and is below and in contact with corresponding bit line <NUM>. In some embodiments, the arrangement and layout of bit line <NUM> may be referred to the description of bit lines <NUM>, <NUM>, and <NUM> in <FIG> and is not repeated herein.

In some embodiments, array interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, bit lines <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Fabrication processes to form bit lines <NUM> can also include photolithography, chemical mechanical polishing (CMP), wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as an "interconnect layer" (e.g., array interconnect layer <NUM>).

The formed memory stack may be coupled with other parts of a memory system for operations such as read, write, and erase. <FIG> illustrates a cross-sectional view of a system <NUM> that includes the 3D memory device formed by fabrication method <NUM>. System <NUM> may include a bonded semiconductor device.

System <NUM> represents an example of a memory system that includes a 3D memory device, according to embodiments of the present disclosure. System <NUM> can include a substrate <NUM>, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials. System <NUM> can include two semiconductor structures, i.e., a memory array device chip <NUM> that includes a 3D memory device described in any of <FIG> and a peripheral device chip <NUM> bonded on top of memory array device chip <NUM> in a face-to-face manner at a bonding interface <NUM>. It should be noted that peripheral device chip <NUM> is used herein merely as an example for illustration of components of the system. In some embodiments, peripheral devices are formed on the same substrate as the 3D memory device, either stack above or below the 3D memory device or on the side of the 3D memory device. In some embodiments, bonding interface <NUM> is disposed between memory array device chip <NUM> and peripheral device chip <NUM> as a result of hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface <NUM> is the place at which memory array device chip <NUM> and peripheral device chip <NUM> are met and bonded. In practice, bonding interface <NUM> can be a layer with a certain thickness that includes the top surface of memory array device chip <NUM> and the bottom surface of peripheral device chip <NUM>.

In some embodiments, memory array device chip <NUM> is a NAND Flash memory device in which memory cells are provided in the form of an array of memory strings <NUM> (e.g., NAND memory strings) in a memory array device layer <NUM>. Memory array device layer <NUM> can be disposed on substrate <NUM>. In some embodiments, each memory string <NUM> extends vertically through a plurality of pairs each including a conductor layer and a dielectric layer (referred to herein as "conductor/dielectric layer pairs"). The stacked conductor/dielectric layer pairs are collectively referred to herein as a memory stack <NUM> in memory array device layer <NUM>. The conductor layers and dielectric layers in memory stack <NUM> can stack alternatingly in the vertical direction. Each memory string <NUM> can include a semiconductor channel and a composite dielectric layer (also known as a "memory film") including a tunneling layer, a storage layer (also known as a "charge trap/storage layer"), and a blocking layer (not shown). The structure of memory strings <NUM> may be the same as or similar to memory strings <NUM> described in FIG. <NUM>, and the lateral arrangement of memory strings <NUM> may be referred to the lateral arrangement of semiconductor channels/memory strings (e.g., <NUM>, <NUM>, and <NUM>) described in <FIG>. In some embodiments, memory array device layer <NUM> further includes a gate line slit ("GLS") or slit structure <NUM> that extends vertically through memory stack <NUM>. GLS <NUM> can be used to form the conductor/dielectric layer pairs in memory stack <NUM> by a gate replacement process and can be filled with conductive materials for electrically connecting ACS of memory strings <NUM>.

In some embodiments, memory array device chip <NUM> also includes an array interconnect layer <NUM> above memory array device layer <NUM> for transferring electrical signals to and from memory strings <NUM>. As shown in <FIG>, array interconnect layer <NUM> can include a plurality of interconnects (also referred to herein as "contacts"), including vertical interconnect access (via) contacts <NUM> and lateral interconnect lines <NUM>. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Array interconnect layer <NUM> can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which bit lines <NUM>, bit line contacts <NUM>, interconnect lines <NUM>, and via contacts <NUM> can form. Bit line contact <NUM> may be positioned between bit line <NUM> and memory string <NUM>. Bit line contact <NUM> may be electrically connected to bit line <NUM> and an upper portion of memory string <NUM> (e.g., drain of memory string <NUM>) to transmit signals/data between bit line <NUM> and memory string <NUM>. Detailed description of bit lines <NUM> may be referred to the description of bit lines in <FIG> and is not repeated herein.

As shown in <FIG>, memory array device chip <NUM> can further include a bonding layer <NUM> at bonding interface <NUM> and above array interconnect layer <NUM> and memory array device layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

Peripheral device chip <NUM> can include a plurality of transistors <NUM> in a peripheral device layer <NUM> disposed below a semiconductor layer <NUM>, such as a thinned substrate. In some embodiments, peripheral device layer <NUM> can include any suitable digital, analog, and/or mixed-signal peripheral devices used for facilitating the operation of system <NUM>. For example, the peripheral devices can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). The peripheral devices in peripheral device layer <NUM> can be electrically connected to memory strings <NUM> through one or more layers of interconnects.

Similar to memory array device chip <NUM>, peripheral device chip <NUM> can also include a peripheral interconnect layer <NUM> disposed below peripheral device layer <NUM> for transferring electrical signals to and from transistors <NUM>. Peripheral interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines <NUM> and via contacts <NUM> in one or more ILD layers. In some embodiments, peripheral device chip <NUM> also includes via contacts <NUM> (e.g., through silicon vias (TSVs) if semiconductor layer <NUM> is a thinned silicon substrate) extending vertically through semiconductor layer <NUM>. In some embodiments, peripheral device chip <NUM> further includes a BEOL interconnect layer (not shown) above transistors <NUM> and semiconductor layer <NUM>. In some embodiments, the BEOL interconnect layer includes any suitable BEOL interconnects and contact pads that can transfer electrical signals between system <NUM> and external circuits.

As shown in <FIG>, peripheral device chip <NUM> can further include a bonding layer <NUM> at bonding interface <NUM> and below peripheral interconnect layer <NUM> and peripheral device layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional 3D, memory device (<NUM>), comprising:
a substrate;
a plurality of memory strings (<NUM>, <NUM>) arranged along a first lateral direction (X) and a second lateral direction (Y) in a plan view, wherein each of the plurality of memory strings (<NUM>, <NUM>) extending vertically above the substrate (<NUM>, <NUM>) in a memory region (<NUM>);
a plurality of bit lines (<NUM>, <NUM>) extending along the second lateral direction over the plurality of memory strings (<NUM>, <NUM>), the plurality of bit lines (<NUM>, <NUM>) being parallel with one another; and
a cut structure (<NUM>) overlapping with at least one of the plurality of memory strings (<NUM>, <NUM>) in the plan view and dividing the plurality of memory strings into a first portion (<NUM>-<NUM>) and a second portion (<NUM>-<NUM>) along the second lateral direction, wherein a number of bit lines above at least one of the plurality of memory strings is at least three,
wherein the first portion (<NUM>-<NUM>) and the second portion (<NUM>-<NUM>) of the plurality of memory strings (<NUM>, <NUM>) comprise a same number of string rows along the second lateral direction (Y) and a same number of string columns along the first lateral direction (X); and
each one of the plurality of bit lines (<NUM>, <NUM>) is electrically connected to one memory string in the first portion (<NUM>-<NUM>) and another memory string in the second portion (<NUM>-<NUM>); and
the first portion (<NUM>-<NUM>) and the second portion (<NUM>-<NUM>) of the plurality of memory strings have the same arrangement of memory strings, an upper semiconductor plug (<NUM>) formed at an upper portion of memory string (<NUM>, <NUM>) as drain of the memory string, wherein the upper semiconductor plug (<NUM>) is recessed back into the memory string.