Patent Description:
Measuring current in a power supply is an important consideration in the design and implementation of modern power supplies. A current sense function may be used for fault detection and/or protection, for current-mode controlled voltage regulation, and for current control, among other uses. Over the years, a variety of systems have been used to measure current in a power supply, including, for example, discrete resistors, use of a resistance inherent to traces of printed circuit boards, use of resistance inherent to an integrated circuit lead frame, use of inductors, magnetic sensing devices including coils, transformers and Hall effect sensors, and use of a drain-source resistance of a power metal oxide semiconductor field effect transistor (MOSFET).

One of the leading systems to measure current in a power supply uses a dedicated field effect transistor (FET) known as or referred to as a "sense-FET. " Generally, a sense-FET is small a FET, separate from the main power FET, referred to herein as the "main-FET. " Generally, a sense-FET is configured to produce a voltage corresponding to the current in the main-FET. The "current sense ratio" (CSR) is a figure of merit of the implementation of the sense-FET. The current sense ratio is a ratio of current in the main-FET to current in the sense-FET, e.g., Imain / Isense. A higher current sense ratio is generally desirable, so that the range of current sensing is extended over many decades of current in the main-FET. However, increasing CSR has been a challenge due to, for example, complex interactions between sense-FET structures and main-FET structures.

Conventional approaches to design and implementation of sense-FETs have not been found to be applicable to Split Gate Charge Balanced (SGCB) trench MOSFETs. A split gate device includes multiple layers of polysilicon in the trenches with different electrical voltages, and it has a special structure and layout to establish the proper charge balance. For example, the trenches are spaced a certain distance apart to establish a charge balance, and furthermore, any active body junction in the device must be properly surrounded by polysilicon shields that establish the charge balance.

Published <CIT> discloses an integrated circuit having a semiconductor portion with a power transistor that includes first gate trenches which cross a first region and a sense transistor including second gate trenches that cross a second region. Each gate trench extends in a longitudinal direction and comprises a gate electrode and a field electrode. The first and second regions are arranged along the longitudinal direction. A first termination trench intersects at least the second gate trenches in a third region between the first and second regions. The first termination trench includes a first conductive structure that is electrically connected to the field electrodes in the second gate trenches.

Published <CIT> discloses a technique for improving current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. The inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. The depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. A p-type semiconductor region is provided at a lower portion of each trench and the p-type semiconductor region is formed so as to contact the semiconductor substrate.

Published <CIT> discloses a semiconductor device that includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical isolation structure that surrounds the main FET is configured to electrically isolate source and body regions of the main FET from source and body regions of the sense FET. A sense FET source pad is located at an edge of the main FET and spaced apart from the transistor portion of the sense FET. The sense FET source pad is connected to the transistor portion of the sense FET by a sense FET probe metal. The isolation structure is configured such that the transistor portion of the sense FET and the sense FET source pad are located outside an active area of the main FET.

Therefore, what is needed are systems and methods for vertical sense devices in vertical trench metal oxide semiconductor field effect transistors (MOSFETs). An additional need exists for systems and methods for vertical sense devices in vertical trench MOSFETs that are integral to the main-FET. What is further needed are systems and methods for current sense MOSFETs in vertical trench MOSFETs including an isolation region between the sense-FET and the main-FET that preserves charge balance in the main-FET. A yet further need exists for a sensing diode to sense temperature and/or gate voltage of the main-FET. A still further need exists for systems and methods for vertical sense devices in vertical trench MOSFETs that are compatible and complementary with existing systems and methods of integrated circuit design, manufacturing and test. Embodiments of the present technology provide these advantages. The invention is set out in the appended set of claims <NUM>-<NUM>.

In accordance with an embodiment of the present technology, not being part of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for controlling currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. In some embodiments, a current sense ratio of the current sensing FET is at least <NUM> thousand and may be greater than <NUM> thousand.

In accordance with another embodiment of the present technology, useful to understand the present invention, a power semiconductor device includes a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET). The main-MOSFET includes a plurality of parallel main trenches, wherein the main trenches include a first electrode coupled to a gate of the main-MOSFET and a plurality of main mesas between the main trenches, wherein the main mesas include a main source and a main body of the main-MOSFET. The power semiconductor device also includes a current sense field effect transistor (sense-FET). The sense-FET includes a plurality of sense-FET trenches, wherein each of the sense-FET trenches includes a portion of one of the main trenches and a plurality of source-FET mesas between the source-FET trenches, wherein the source-FET mesas include a sense-FET source that is electrically isolated from the main source of the main-MOSFET.

In accordance with a further embodiment of the present technology, useful to understand the present invention, a semiconductor device includes a main-FET including a main-FET source region and a current sensing FET (sense-FET) configured to produce a voltage corresponding to a drain source current of a the main-FET. A gate and a drain of the sense-FET are coupled to a gate and a drain of the main-FET. The sense-FET includes a plurality of first trenches formed in a first horizontal dimension configured to isolate a sense-FET source region from the main-FET source region. Each of the trenches includes multiple alternating layers of conductors and dielectrics in a vertical dimension. The semiconductor device further includes at least one second trench in a perpendicular horizontal dimension located between the sense-FET source region and the main-FET source region and configured to isolate the sense-FET source region from the main-FET source region, and a buffer region separating sense-FET source region and the main-FET source region.

In accordance with still another embodiment of the present technology, useful to understand the present invention, a power semiconductor device includes a vertical trench main MOSFET (main-FET) configured to control a drain source current, a vertical trench current sensing FET (sense-FET) configured to produce a voltage corresponding to the drain source current, and an isolation trench configured to isolate the main-FET from the sense-FET. The isolation trench is formed at an angle to, and intersects a plurality of trenches of the main-FET.

In a still further embodiment in accordance with the present technology, useful to understand the present invention, a power semiconductor device includes a substrate and a split gate vertical trench main MOSFET (main-FET), formed in the substrate, configured to control a drain source current. The main-FET includes a main-FET source metal, disposed on the surface of the substrate, configured to couple a plurality of main-FET source regions to one another and to a plurality of main-FET source terminals. The power semiconductor device also includes a vertical trench current sensing FET (sense-FET), formed in the substrate, configured to produce a voltage corresponding to the drain source current. The sense-FET is surrounded on at least three sides by the main-FET source metal. The substrate may include epitaxially grown material.

In a still further yet embodiment in accordance with the present technology, useful to understand the present invention, a power semiconductor device includes a substrate and a split gate vertical trench main MOSFET (main-FET), formed in the substrate, configured to control a drain source current. The power semiconductor device also includes a vertical trench current sensing FET (sense-FET), formed in the substrate, configured to produce a voltage corresponding to the drain source current. The sense-FET and the main-FET include common gate and drain terminals. The sense-FET may include portions of trenches forming the main-FET. The substrate may include epitaxially grown material.

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the technology and, together with the description, serve to explain the principles of the technology. Unless otherwise noted, the drawings are not drawn to scale.

Reference will now be made in detail to various embodiments of the technology, examples of which are illustrated in the accompanying drawings. While the technology will be described in conjunction with these embodiments, it is understood that they are not intended to limit the technology to these embodiments. On the contrary, the technology is intended to cover alternatives, modifications and equivalents, which are included within the scope of the technology as defined by the appended claims. Furthermore, in the following detailed description of the technology, numerous specific details are set forth in order to provide a thorough understanding of the technology. However, it will be recognized by one of ordinary skill in the art that the technology may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the technology.

The figures are not drawn to scale, and only portions of the structures, as well as the various layers that form those structures, may be shown in the figures. Furthermore, fabrication processes and operations may be performed along with the processes and operations discussed herein; that is, there may be a number of process operations before, in between and/or after the operations shown and described herein. Importantly, embodiments in accordance with the present technology can be implemented in conjunction with these other (perhaps conventional) processes and operations without significantly perturbing them. Generally speaking, embodiments in accordance with the present technology may replace and/or supplement portions of a conventional process without significantly affecting peripheral processes and operations.

The term "MOSFET" is generally understood to be synonymous with the term insulated-gate field-effect transistor (IGFET), as many modern MOSFETs comprise a non-metal gate and/or a non-oxide gate insulator. As used herein, the term "MOSFET" does not necessarily imply or require FETs that include metal gates and/or oxide gate insulators. Rather, the term "MOSFET" includes devices commonly known as or referred to as MOSFETs.

As used herein, the letter "n" refers to an n-type dopant and the letter "p" refers to a p-type dopant. A plus sign "+" or a minus sign "-" is used to represent, respectively, a relatively high or relatively low concentration of such dopant(s).

The term "channel" is used herein in the accepted manner. That is, current moves within a FET in a channel, from the source connection to the drain connection. A channel can be made of either n-type or p-type semiconductor material; accordingly, a FET is specified as either an n-channel or p-channel device. Some of the figures are discussed in the context of an n-channel device, more specifically an n-channel vertical MOSFET; however, embodiments according to the present technology are not so limited. That is, the features described herein may be utilized in a p-channel device. The discussion of an n-channel device can be readily mapped to a p-channel device by substituting p-type dopant and materials for corresponding n-type dopant and materials, and vice versa.

The term "trench" has acquired two different, but related meanings within the semiconductor arts. Generally, when referring to a process, e.g., etching, the term trench is used to mean or refer to a void of material, e.g., a hole or ditch. Generally, the length of such a hole is much greater than its width or depth. However, when referring to a semiconductor structure or device, the term trench is used to mean or refer to a solid vertically-aligned structure, disposed beneath a primary surface of a substrate, having a complex composition, different from that of the substrate, and usually adjacent to a channel of a field effect transistor (FET). The structure comprises, for example, a gate of the FET. Accordingly, a trench semiconductor device generally comprises a mesa structure, which is not a trench, and portions, e.g., one half, of two adjacent structural "trenches.

It is to be appreciated that although the semiconductor structure commonly referred to as a "trench" may be formed by etching a trench and then filling the trench, the use of the structural term herein in regards to embodiments of the present technology does not imply, and is not limited to such processes.

A charge balanced split gate vertical trench metal oxide semiconductor field effect transistor (MOSFET) generally comprises trenches that extend into one or more epitaxial layers that are grown on top of a heavily doped substrate. The trenches are etched deep enough, typically a few micrometers, to be able to contain several layers of oxide and polysilicon. The lower layer of the polysilicon ("poly <NUM>"), which is closest to the trench bottom, is usually tied to the source electrical potential and is an essential part of establishing the charge balance condition that results in a desirable low "on" resistance for a given breakdown voltage. The upper layer of the polysilicon ("poly <NUM>") is usually used as the gate of the device. Both layers are well inside the trench and separated from the epitaxial regions by different thicknesses of dielectric layers, for example, silicon dioxide.

In accordance with embodiments of the present technology, a relatively small sense-FET is established proximate the top body of a relatively larger split gate MOSFET, known as the "main-FET. " A sense-FET should be able to deliver a current in the sense-FET that is a small fraction of the current passing through the main-FET. For example, the sense-FET should be characterized as having a large current sense ratio (CSR).

In general, a current sense ratio (CSR) may be a property of both device geometry and temperature. For example, temperature differences between a sense-FET and portions of a main-FET may deleteriously change a CSR during operation.

In accordance with embodiments of the present technology, not being part of the present invention, a sense-FET may be positioned in an area of a main-FET where a sense-FET can sense a high temperature of the die. The sense-FET may be surrounded on at least three sides by portions of the main-FET. In accordance with embodiments of the present technology, multiple sense-FETs, e.g., sharing a common sense-FET source, may be positioned in a plurality of locations throughout a main-FET. Such multiple locations may improve current sensing corresponding to thermal distribution across a large die, for example.

<FIG> illustrates a plan view of an exemplary current sense MOSFET (sense-FET) <NUM> in a power semiconductor device <NUM>, in accordance with embodiments of the present technology. A principal function of power semiconductor device <NUM> is to function as a power MOSFET, e.g., to control a drain source current through the power MOSFET. Power semiconductor device <NUM> comprises large areas of main-FET <NUM>. For example, main-FET <NUM> comprises numerous trenches comprising gate and shield electrodes, and mesas in-between the trenches comprising source and body regions. The main-FET <NUM> comprises a gate coupled to a gate terminal <NUM>, for example, a bond pad. The main-FET <NUM> comprises a source coupled to a main-FET source terminal <NUM>. The drain of the main-FET <NUM> is outside, e.g., below, the plane of <FIG>.

Power semiconductor device <NUM> comprises a sense-FET <NUM>, formed within a region of the main-FET <NUM>, in accordance with embodiments of the present technology. It is appreciated that die area of main-FET <NUM> is very much greater than die area of sense-FET <NUM>. The gate and drain of the sense-FET <NUM> are in common, e.g., in parallel, with the gate and drain of the main-FET <NUM>. The source of the sense-FET <NUM> is coupled to a sense source terminal <NUM>, e.g., a bond pad. The sense-FET outputs a voltage corresponding to current in the main-FET <NUM>. The node Kelvin may be coupled to a terminal <NUM> for use off the die of power semiconductor device <NUM>, in some embodiments not forming part of the present invention. The voltage Kelvin may also, or alternatively, be used by circuitry (not shown) on the die of power semiconductor device <NUM>, for example, to turn main-FET <NUM> off for over-current protection.

<FIG> illustrates an exemplary schematic symbol for power semiconductor device <NUM>, in accordance with embodiments of the present technology.

<FIG> illustrates an exemplary enlarged plan view of a portion of power semiconductor device <NUM> around and including sense-FET <NUM>, in accordance with embodiments of the present technology. Power semiconductor device <NUM> comprises a plurality of primary trenches <NUM>, illustrated horizontally in <FIG>. The majority of primary trenches <NUM> are utilized by the main-FET <NUM>.

Power semiconductor device <NUM> comprises four isolation trenches <NUM>, <NUM>, <NUM> and <NUM>, in accordance with embodiments of the present technology. The isolation trenches <NUM>-<NUM> are part of a group of isolation structures to isolate sense-FET <NUM> from the main-FET <NUM>. The isolation trenches <NUM>-<NUM> are perpendicular to the primary trenches <NUM>, in accordance with embodiments of the present technology. Sense-FET <NUM> comprises a sense-FET source <NUM>. Sense-FET source <NUM> is bounded by two isolation trenches, isolation trenches <NUM> and <NUM>, and portions of two primary trenches <NUM>, primary trenches 210A and 210B. Overlying and coupling sense-FET source <NUM> is sense-FET source metal <NUM>. Sense-FET source metal <NUM> overlaps the isolation trenches <NUM> and <NUM>. Sense-FET source metal <NUM> may extend off the top of the <FIG> for coupling to sense source terminal <NUM> (<FIG>), for example, in some embodiments. In accordance with other embodiments of the present technology, the source of main-FET <NUM> may be coupled in a different manner, e.g., out of the plane of <FIG>. In such a case, the surface isolation region <NUM> would form a square annulus around the sense-FET <NUM> (<FIG>), in accordance with embodiments of the present technology.

A surface isolation region <NUM> is formed outside of sense-FET <NUM>, in accordance with embodiments of the present technology. In the exemplary embodiment of <FIG>, surface isolation region <NUM> is generally "U" shaped. Surface isolation region <NUM> is formed between isolation trenches <NUM> and <NUM>, between isolation trenches <NUM> and <NUM>, and between primary trenches 210B and 210C. In general, portions of multiple primary trenches <NUM> should be used to isolate a sense-FET <NUM> from a main-FET <NUM>, in order to maintain charge balance. P-type materials in the mesas of surface isolation region <NUM> are left floating. The surface of surface isolation region <NUM> may be covered with an insulator, for example, borophosphosilicate glass (BPSG).

Outside of surface isolation region <NUM>, e.g., to the left, right and below surface isolation region <NUM> in the view of <FIG>, are regions of main-FET <NUM>. For example, p-type material in mesas between primary trenches <NUM> is coupled to the main-FET source terminal <NUM> (<FIG>), and such regions are overlaid with main-FET source metal (not shown).

<FIG> illustrates an exemplary cross-sectional view of a portion of power semiconductor device <NUM>, in accordance with embodiments of the present technology. <FIG> corresponds to cross section AA of <FIG>. The view of <FIG> is taken along a mesa, e.g., between primary trenches <NUM> (<FIG>), cutting an active region of sense-FET <NUM> (<FIG>). Power semiconductor device <NUM> comprises an epitaxial layer <NUM>, e.g., N-, formed on an N+ substrate (not shown). A metallic drain contact (not shown) is typically formed on the bottom the substrate. Isolation trenches <NUM>, <NUM>, <NUM> and <NUM> are formed in epitaxial layer <NUM>. As illustrated, isolation trenches <NUM>, <NUM>, <NUM> and <NUM> are perpendicular to the primary trenches <NUM>. However, a wide variety of angles between isolation trenches <NUM>-<NUM> and primary trenches <NUM>, e.g., from about <NUM> degrees to <NUM> degrees, are well suited to embodiments in accordance with the present technology.

Primary trenches <NUM> are above and below the plane of <FIG>. The isolation trenches <NUM>-<NUM> should be deeper than the drain-body PN junction, and may be about the same depth as the primary trenches <NUM>. Such a depth establishes a physical barrier between the source of the sense-FET <NUM> and the source of the main-FET <NUM>. Thus, in accordance with embodiments of the present technology, the body implant may be performed without a mask, hence making the manufacturing process more cost effective.

Within each trench <NUM>-<NUM> there are two polysilicon electrodes, poly <NUM> (<NUM>) and poly <NUM> (<NUM>), separated by oxide, e.g., silicon dioxide. The top electrode, poly <NUM> (<NUM>), is coupled to the gate terminal, and the bottom electrode, poly <NUM> (<NUM>), is coupled to the source terminal. Power semiconductor device <NUM> additionally comprises a body implant <NUM>, e.g., P+ doping, typically at a depth below the surface of epitaxial layer <NUM>. The implant region <NUM> between isolation trenches <NUM> and <NUM>, and between isolation trenches <NUM> and <NUM> is left floating to create a buffer region between the body region <NUM> of the sense-FET and the electrically separate body region of the main-FET <NUM>, thus improving the electrical isolation of the two FETs with minimal distance separating the two body regions <NUM> and <NUM>.

The region between isolation trenches <NUM> and <NUM>, and between isolation trenches <NUM> and <NUM> is a part of surface isolation region <NUM> (<FIG>). Surface isolation region <NUM> is covered with an insulator, for example, borophosphosilicate glass (BPSG) <NUM>. There is generally a layer <NUM> of low temperature oxide (LTO) underneath BPSG <NUM>. The BPSG <NUM> isolates both sense-FET source metal <NUM> and main-FET source metal from one another and from the floating body implant <NUM>.

Sense-FET source metal <NUM> couples the sources of the sense-FET <NUM> (not shown) and the sense-FET body <NUM> to a sense-FET source terminal of power semiconductor device <NUM>, e.g., sense-FET source terminal <NUM> (<FIG>).

<FIG> illustrates an exemplary cross-sectional view of a portion of power semiconductor device <NUM>, in accordance with embodiments of the present technology. <FIG> corresponds to cross section BB of <FIG>. The view of <FIG> is taken through an active region of sense-FET <NUM> (<FIG>), perpendicular to primary trenches <NUM>. Portions of several primary trenches <NUM>, e.g., under surface isolation region <NUM> and BPSG <NUM>, are utilized as isolation trenches <NUM>. The top electrode, poly <NUM> (<NUM>), is coupled to the gate electrode, and the bottom electrode, poly <NUM> (<NUM>), is coupled to the source of the main-FET. Portions of different primary trenches <NUM> are used as trenches <NUM> to form sense-FET <NUM>. It is to be appreciated <FIG> illustrates only two trenches as part of a sense-FET <NUM> for clarity. There would typically be many more trenches <NUM> within a sense-FET <NUM>.

Sense-FET <NUM> comprises a sense-FET source <NUM>, which is typically an N+ implant at or near the top of epitaxial layer <NUM>. Sense-FET <NUM> also comprises a sense-FET source-body contact <NUM>. Also illustrated in <FIG> is a sense-FET source metal extension <NUM>, for example, used to route sense-FET source metal extension to a sense-FET source contact, e.g., sense-FET source terminal <NUM> of <FIG>.

<FIG> illustrates a graph <NUM> of experimental measurements taken on prototype devices constructed in accordance with embodiments of the present technology. Graph <NUM> illustrates a current sense ratio (CSR), e.g., a ratio of Imain/Isense, on the left abscissa, across a range of drain-source currents, Ids, of the main-FET, also known as Imain, from <NUM> amps to <NUM> amps (ordinate). The ratio is at least <NUM> x <NUM><NUM>, e.g., at <NUM> amps, and may be as high as <NUM> x <NUM><NUM>, e.g., at <NUM> amps. In contrast, the highest claimed CSR under the conventional art known to applicants at this time is approximately <NUM> x <NUM><NUM>.

Graph <NUM> of <FIG> also illustrates a percentage mismatch across the full main current range on the right abscissa. The mismatch describes the accuracy of the ratio of Imain/Isense. The mismatch is very small, e.g., within a range of +/- <NUM> percent across a range of Ids from <NUM> amps to <NUM> amps. Thus, the prototype very accurately indicates Ids of the main-FET.

In accordance with embodiments of the present technology, a current sense MOSFET in a vertical trench MOSFET may be formed without additional process steps or additional mask layers in comparison to process steps and mask layers required to produce a corresponding vertical trench MOSFET by itself. For example, the perpendicular isolation trenches, e.g., isolation trenches <NUM>-<NUM> of <FIG>, may be formed utilizing the same process steps and masks that form the primary trenches <NUM> of <FIG>. It is appreciated that several masks, including, for example, a trench mask and metallization masks, will be different between embodiments in accordance with the present technology and the conventional art. For example, a single mask for forming FET trenches, e.g., primary trenches <NUM> (<FIG>) and perpendicular isolation trenches, e.g., isolation trenches <NUM>-<NUM> (<FIG>), is novel and unique, in accordance with embodiments of the present technology. However, the processes and numbers of masks may be the same.

<FIG> illustrates an exemplary process flow <NUM> for constructing a current sense MOSFET in a vertical trench MOSFET, for example, power semiconductor device <NUM> of <FIG>, in accordance with embodiments of the presentt technology, being not part of , but useful to understand the present invention, In <NUM>, a plurality of trenches are etched with a hard mask to a depth, e.g., of typically a few micrometers. The trenches include, for example, primary trenches, e.g., primary trenches <NUM> (<FIG>) and isolation trenches, e.g., isolation trenches <NUM>-<NUM>, formed at an angle to the primary trenches. The primary trenches and isolation trenches may be etched to about the same depth, but that is not required.

In another embodiment, the vertical trenches are made slightly wider than primary trenches <NUM> such that when both trenches are etched (at the same process step) the vertical trenches are somewhat deeper than the primary trenches.

In <NUM>, thermal oxide is grown followed by a deposited oxide inside the trench. In <NUM>, first polysilicon, e.g., poly <NUM> (<NUM>) of <FIG>, is deposited inside the trench. The first polysilicon may be doped with a high concentration of Phosphorus. In <NUM>, the first polysilicon is recessed back to a desired depth, typically on the order of <NUM> micrometer. In <NUM>, a second oxide layer is grown or deposited over and above the first polysilicon. In <NUM>, a selective oxide etch is performed to etch the active region where the gate oxide is grown.

In <NUM>, second polysilicon, e.g., poly <NUM> (<NUM>) of <FIG>, is deposited. In <NUM>, the second polysilicon is recessed in the active area to allow a layer of deposited oxide the fill the top of the trenches by a fill and etch back process. The body and source implants should be introduced consecutively. In <NUM>, a layer of silicon nitride and doped oxide is used to cover the surface before contacts are etched to silicon, first polysilicon and second polysilicon.

In <NUM> a layer of metal is deposited and etched forming the gate and source contacts. It is appreciated that the source metal patterns of embodiments in accordance with the present technology differ from a conventional vertical MOSFET, for example, to accommodate the separate sense source of the novel sense-FET. In addition, there is no source metal in an isolation region around the sense-FET.

In <NUM> a passivation layer of oxide and nitride are deposited over the metallization and etched. In <NUM> a metal layer is deposited forming the backside drain contact.

In accordance with embodiments of the present technology, not being part of the present invention, a sense diode may be established proximate the top body of a relatively larger split gate MOSFET, known as the "main-FET. " Such a sense diode may be used to indicate temperature of the main-FET, in some embodiments. Temperature of a main-FET may be used for numerous purposes, e.g., to shut down a device responsive to an over-temperature condition. A sense diode may also be used to measure gate voltage of the main-FET, in some embodiments. Measuring gate voltage of a main-FET may be desirable when the gate terminal of a main-FET is not exposed, e.g., in packaged, high function devices such as driver MOS ("DrMOS") devices.

<FIG> illustrates a plan view of an exemplary sense diode <NUM> in a power semiconductor device <NUM>, in accordance with embodiments of the present technology, not being part of the present invention. A principal function of power semiconductor device <NUM> is to function as a power MOSFET, e.g., to control a drain source current through the power MOSFET. Power semiconductor device <NUM> comprises large areas of main-FET <NUM>. For example, main-FET <NUM> comprises numerous trenches comprising gate and shield electrodes, and mesas in-between the trenches comprising source and body regions. The main-FET <NUM> comprises a gate coupled to a gate terminal <NUM>, for example, a bond pad. The main-FET <NUM> comprises a source coupled to a main-FET source terminal <NUM>. The drain of the MOSFET <NUM> is outside, e.g., below, the plane of <FIG>. The function and structure of main-FET <NUM>, main source <NUM> and gate <NUM> are generally equivalent to the comparable structures of device <NUM>, as illustrated in <FIG>.

Power semiconductor device <NUM> comprises a sense-diode <NUM>, formed within a region of the main-FET <NUM>, in accordance with embodiments of the present technology, not being part of the present invention. It is appreciated that die area of main-FET <NUM> is very much greater than die area of sense-diode <NUM>. The cathode terminal of sense-diode <NUM> is in common with the drain terminal of main-FET <NUM>, outside the plane of <FIG>. The anode terminal of sense-diode <NUM> is coupled to anode terminal <NUM>. , e.g., a bond pad.

<FIG> illustrates an exemplary schematic symbol for power semiconductor device <NUM>, in accordance with embodiments of the present technology, not being part of the present invention.

It is to be appreciated that sense-diode <NUM> is structurally very similar to sense-FET <NUM> of <FIG>, <FIG>, <FIG> and <FIG>. The isolation trenches that isolate sense-diode <NUM> are equivalent to the isolation trenches that isolate sense-FET <NUM>. The salient differences between sense-FET <NUM> and sense-diode <NUM> are that sense-diode <NUM> may lack a source implant <NUM> and a source-body contact <NUM> (<FIG>), and the two poly layers within the trenches are connected differently.

<FIG> illustrates an exemplary cross-sectional view of a portion of power semiconductor device <NUM>, in accordance with embodiments of the present technology, not being part of the present invention. <FIG> is generally equivalent to the cross section illustration of <FIG>. The view of <FIG> is taken through an active region of sense-diode <NUM> (<FIG>), perpendicular to primary trenches of main-FET <NUM>. Portions of several primary trenches, e.g., under surface isolation regions and BPSG <NUM>, are utilized as isolation trenches <NUM>. The top electrode, poly <NUM> (<NUM>), is coupled to the gate electrode, and the bottom electrode, poly <NUM> (<NUM>), is coupled to the source of the main-FET. Portions of different primary trenches are used as trenches <NUM> to form sense-diode <NUM>. It is to be appreciated <FIG> illustrates only two trenches as part of a sense-diode <NUM> for clarity. There would typically be many more trenches <NUM> within a sense-diode <NUM>.

Sense diode <NUM> comprises a sense-diode anode <NUM>. Optionally, sense diode <NUM> may comprise a sense-diode anode contact <NUM>, similar to a source-body contact of a MOSFET, e.g., sense-FET source-body contact <NUM> of <FIG>. Also illustrated in <FIG> is a sense-FET source metal extension <NUM>, for example, used to route sense-FET source metal extension to a sense-FET source contact, e.g., sense-FET anode contact <NUM> of <FIG>.

In accordance with embodiments of the present technology, not being part of the present invention, sense-diode <NUM> may be used to sense temperature of the device, e.g., a temperature of main-FET <NUM> and/or to indicate the voltage of gate <NUM>.

To measure temperature, in accordance with embodiments of the present technology, not being part of the present invention, the first field plate, poly <NUM> (<NUM>), should be electrically coupled to the anode of the sense-diode <NUM>, which has a separate terminal distinct from the source of the main-FET <NUM> (or a sense-FET, if present). The second field plate, poly <NUM> (<NUM>), uses the gate structure and should be electrically coupled to the anode (not to the gate terminal <NUM> of the main-FET <NUM>). The cathode side of the diode is common to the drain of the main-FET <NUM> (and a sense-FET, if present). In this embodiment, the diode is not affected by the main-FET <NUM> gate voltage and exhibits good diode characteristics that can be calibrated as a function of temperature for temperature sensing. Accordingly, this novel structure of a vertical MOS diode within a vertical trench MOSFET may be used to sense temperature of the device via well known methods.

To indicate gate voltage, in accordance with embodiments of the present technology, not being part of the present invention, the second field plate, poly <NUM> (<NUM>), should be electrically coupled to the gate terminal of the main-FET <NUM>. In this embodiment, the sense-diode <NUM> characteristics change as a function of the gate voltage. For example, the sense-diode <NUM> current-voltage relation depends on gate terminal voltage if the second field plate, poly <NUM> (<NUM>), is electrically coupled to the gate terminal. In this embodiment, the sense-diode <NUM> current-voltage characteristic may be used to indicate the gate voltage, at a given temperature, by calibrating the sense-diode <NUM> voltage at a given current to the gate voltage. This can be useful if there is no gate terminal exposed to the outside, for example, as is the case of a Driver-MOS ("DrMOS") package. <FIG>, below, illustrates exemplary characteristics of the sense-diode <NUM> as a function of the gate voltage, to facilitate determining gate voltage.

<FIG> illustrates exemplary characteristics <NUM> of an exemplary sense-diode <NUM> as a function of gate voltage, in accordance with embodiments of the present technology, not being part of the present invention. Characteristics <NUM> may be used to determine gate voltage based on diode current and anode voltage. The modulation of the current - voltage characteristics of the sense-diode <NUM> is seen here depending on the gate voltage, as applied to the second field plate, poly <NUM> (<NUM>) as illustrated in <FIG>. When Vgs = <NUM> volts, the channel is off, and the sense-diode <NUM> is working in a "pure diode mode. " As Vgs increases, the sense-diode <NUM> is modulated by the parasitic MOSFET. For example, when Vgs = <NUM> volts, the channel is on and channel current dominates the characteristics. The sense-diode <NUM> in this mode of operation can basically "detect the gate voltage" by calibrating the current flowing through the diode, for example, at <NUM>µa of drain-source current, to the following Table <NUM>:.

It is to be appreciated that embodiments in accordance with the present technology are well suited to the formation and use of both a sense-FET, e.g., sense-FET <NUM> of <FIG>, and a sense-diode, e.g., sense-diode <NUM> of <FIG>.

<FIG> illustrates a plan view of an exemplary current sense MOSFET (sense-FET) <NUM> and an exemplary sense diode <NUM> in a power semiconductor device <NUM>, in accordance with embodiments of the present technology. A principal function of power semiconductor device <NUM> is to function as a power MOSFET, e.g., to control a drain source current through the power MOSFET. Power semiconductor device <NUM> comprises large areas of main-FET <NUM>. For example, main-FET <NUM> comprises numerous trenches comprising gate and shield electrodes, and mesas in-between the trenches comprising source and body regions. The main-FET <NUM> comprises a gate coupled to a gate terminal <NUM>, for example, a bond pad. The main-FET <NUM> comprises a source coupled to a main-FET source terminal <NUM>. The drain of the MOSFET <NUM> is outside, e.g., below, the plane of <FIG>.

Power semiconductor device <NUM> comprises a sense-FET <NUM>, formed within a region of the main-FET <NUM>, in accordance with embodiments of the present technology. It is appreciated that die area of main-FET <NUM> is very much greater than die area of sense-FET <NUM>. The gate and drain of the sense-FET <NUM> are in common, e.g., in parallel, with the gate and drain of the main-FET <NUM>. The source of the sense-FET <NUM> is coupled to a sense source terminal <NUM>, e.g., a bond pad. The sense-FET outputs a voltage corresponding to current in the main-FET <NUM>. The node Kelvin may be coupled to a terminal <NUM> for use off the die of power semiconductor device <NUM>, in some embodiments. The voltage Kelvin may also, or alternatively, be used by circuitry (not shown) on the die of power semiconductor device <NUM>, for example, to turn main-FET <NUM> off for over-current protection.

Power semiconductor device <NUM> further comprises a sense-diode <NUM>, formed within a region of the main-FET <NUM>, in accordance with embodiments of the present technology. It is appreciated that die area of main-FET <NUM> is very much greater than die area of sense-diode <NUM>. The cathode of the sense-diode <NUM> is in common with the drain of the main-FET <NUM>. The anode of sense-diode <NUM> is coupled to an anode terminal, e.g., a bond pad <NUM>. The sense-diode <NUM> may be used to measure temperature of the device and/or gate voltage, as previously described. A power MOSFET device comprising at least two sense-diodes is envisioned, and is considered within the scope of the present technology. For example, multiple sense diodes may be configured to measure temperature in different regions of a MOSFET. In another embodiment, at least one sense diode may be configured to indicate gate voltage in conjunction with one or more sense diodes configured to measure temperature.

Similarly, a power MOSFET device comprising at least two sense-FETs is envisioned, and is considered within the scope of the present technology, in accordance with the present invention. For example, due to temperature and manufacturing process variations across a large die of a power MOSFET, current within the MOSFET may not be uniformly distributed. Accordingly, it may be advantageous to measure current via multiple sense-FETs at different locations throughout such a device. As a beneficial result of the novel high current sense ratio afforded by embodiments of the present technology, small variations in current may be observed in this manner.

It is to be appreciated that no additional masks or manufacturing process steps are required to form sense-FET <NUM> and/or sense-diode <NUM>. Both sense-FET <NUM> and sense-diode <NUM> utilize structures common to a main-FET, e.g., trenches and poly layers, for their function, and further utilize structures common to a main-FET, e.g., trenches and BPSG, for isolation. Accordingly, the benefits of a sense-FET <NUM> and/or sense-diode <NUM> may be realized with no additional manufacturing cost in comparison to a trench MOSFET.

Embodiments in accordance with the present technology are well suited to a variety of trench MOSFETs, including, for example, single gate trench MOSFETs, split gate charge balanced trench MOSFETs, Hybrid Split Gate MOSFETs, and dual trench MOSFETs, for example, as described in the publication: "<NPL>.

Embodiments in accordance with the present technology provide systems and methods for current sense metal oxide semiconductor field effect transistors (MOSFETs) in vertical trench MOSFETs. In addition, embodiments in accordance with the present technology provide systems and methods for current sense MOSFETs in vertical trench MOSFETs that are integral to the main-FET. Further, embodiments in accordance with the present technology provide systems and methods for current sense MOSFETs in vertical trench MOSFETs that are integral to the main-FET. Yet further embodiments in accordance with the present technology, not being part of the present invention. provide systems and methods for a sensing diode to sense temperature and/or gate voltage of the main-FET. Still further, embodiments in accordance with the present technology provide systems and methods for systems and methods for current sense MOSFETs and/or sense diodes in vertical trench MOSFETs that are compatible and complementary with existing systems and methods of integrated circuit design, manufacturing and test.

Various embodiments of the invention are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the invention should not be construed as limited by such embodiments, but rather construed according to the below claims.

Claim 1:
A semiconductor device (<NUM>) comprising:
a main-MOSFET (<NUM>) comprising a main-MOSFET source region, the device comprising:
a plurality of parallel main trenches (<NUM>), wherein said main trenches comprise a first electrode (<NUM>) coupled to a gate (<NUM>) of said main-MOSFET; and
a plurality of main mesas between said main trenches, wherein said main mesas comprise the source region and a main body (<NUM>) of said main-MOSFET; and
a current sensing FET, sense-FET, (<NUM>), configured to produce a signal corresponding to a drain source current of said main-MOSFET,
wherein a gate and a drain of said sense-FET are coupled to a gate (<NUM>) and a drain of said main-MOSFET, respectively, wherein sections of a subset of said plurality of main trenches (<NUM>) are used as trenches (<NUM>) to form said sense-FET (<NUM>), said sense-FET comprising:
a plurality of first isolation trenches (<NUM>, <NUM>, <NUM>, <NUM>) formed in a first horizontal dimension and configured to isolate a sense-FET source region from said main-MOSFET source region, and
a plurality of second isolation trenches (210B, 210C,210A, <NUM>) formed in a second horizontal dimension perpendicular to the first horizonal dimension, the plurality of second isolation trenches located between said sense-FET source region and said main-MOSFET source region and configured to isolate said sense-FET source region from said main-FET source region;
wherein each of said plurality of main trenches, each of said plurality of first isolation trenches and each of said plurality of second isolation trenches comprises multiple alternating layers of conductors (<NUM>, <NUM>) and dielectrics in a vertical dimension;
a buffer region (<NUM>) separating said sense-FET source region and said main-FET source region,
wherein said buffer region is formed as square annulus around the sense-FET and between two sets of two first isolation trenches (<NUM>, <NUM>, <NUM>, <NUM>), located on two opposite sides of the sense-FET in the first horizontal dimension perpendicular to the main trenches (<NUM>), and between two sets of at least two second isolation trenches (210B, 210C, 210A, <NUM>), located on two opposite sides of the sense-FET in the second horizontal dimension, the buffer region configured to electrically isolate said main-MOSFET from said sense-FET.