Patent Description:
Previous studies have utilized active metal layers, particularly high front side metal layers to create on-chip antenna. This may require using valuable active layer area to be occupied by the antenna. Alternatively, the prior art has used off chip antennas, which require a large area. In addition, space may be needed between the antenna and active layer to isolate cross talk.

<CIT> describes a semiconductor device comprising a semiconductor chip comprising a semiconductor substrate and an element formation layer which is formed on a first main surface of the semiconductor substrate and has a semiconductor element; and a passive circuit electrically connected to the semiconductor element, wherein the passive circuit is disposed on the side of a second main surface opposite to the first main surface of the semiconductor substrate and the passive circuit is electrically connected to the semiconductor element by a through electrode extending through the semiconductor chip.

<CIT> describes an integrated communication device having a substrate layer of substantially electrically nonconductive material with two substantially parallel surfaces, an antenna element disposed on one of the surfaces, a ground layer of substantially electrically conductive material disposed on the other surface and having an opening formed therethrough opposite from the antenna element, and a transceiver device mounted to the ground layer to transmit and/or receive electromagnetic energy through the opening.

The dependent claims recite selected optional features.

Illustrative embodiments of the present invention are described in detail below with reference to the attached drawing figures, wherein:.

The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments of the invention set forth in the claims encompass equivalents of those claims. Embodiments of the invention may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without intending to limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed.

As used herein, a patch antenna element is generally a flat rectangular sheet or "patch" of metal, mounted over a sheet of metal called a ground plane or reflector. In one embodiment, the ground plane or reflector is generally larger than the patch antenna element. A dielectric layer may be present between the patches and reflector. Generally, the two edges of the patches that are connected to, and opposite from the feed connection provide the antenna radiation.

As used herein, a through- silicon via (TSV) is an electrical connection passing through a silicon wafer or die. Generally, the TSV's pass through the die in the direction perpendicular to the plane of the substrate and the active circuit layers, which direction is called the "vertical" direction herein. TSVs may be used as feed lines to the patches of the antenna as described herein.

As used herein, integrated circuit die may comprise a substrate having an active layer, and a backside. The active layer may comprise a plurality of metal layers, and this layer may be where amplifying, rectifying, light emitting, or other dynamic action occurs in a semiconductor die. Generally, the active layer may overlay the substrate. Generally, the backside is the inactive layer of the die.

A three-dimensional (3D) chip is a type of chip packaging in which two or more semiconductor active layers are integrated both vertically and horizontally into a single circuit. In a monolithic <NUM>-D chip, electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. In wafer-on-wafer <NUM>-D technology, circuits are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D integrated circuits. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These "through-silicon vias" (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Die- on-wafer 3D integrated circuits are created by using two wafers. One wafer is diced, and dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on- wafer method, thinning and TSV creation are performed either before or after bonding. Additional dice may be added to the stacks before dicing. In die-on-die <NUM>-D IC's electronic components are built on multiple die, which are then aligned and bonded. 3D packaging may also comprise a flip chip, also known as controlled collapse chip connection or its acronym, C4, for interconnecting the die. Die are flipped and positioned so that the active layer of a die is connected to the circuitry of the other die. Various embodiments of the invention may utilize any of these integrated circuit types and many others.

A Redistribution Layer (RDL) is a metal layer on a chip that permits the input/output connection pads to be relocated to different places than they are located as a result of the circuit design. The RDL may be considered to be a method to create distributed conductive metal lines on a surface of a semiconductor die. RDL may involve adding another conductive layer over a substrate, patterned and metallized to provide new bond pads at new locations. This layer may be electrically isolated from the substrate, except for connections at the original bond pads or to metal runs.

<FIG> is an on-chip antenna according to an illustrative embodiment <NUM>. The patch antenna comprises a die <NUM> having a substrate <NUM> and patches <NUM> that may be fabricated using the redistribution layer (RDL) <NUM> at the backside <NUM> of the substrate <NUM>. Through silicon vias (TSV) <NUM> may be utilized as feed lines from the active layer <NUM> comprising radio frequency (RF) transmitters and receivers <NUM> (<FIG>) to the antenna patches <NUM>. In an embodiment, the on-chip antenna may be packaged as a 3D stack where the top die <NUM> is mounted on a flip chip package, that is, it is flipped and positioned on top of the second die <NUM>. The antenna patches fabricated using RDL on the backside of the top die are now top side which ensures that the radiating antenna array is pointing towards the air. The antenna patches may be planar and rectangular, and configured to operate as a phase array antenna system.

<FIG> shows a top view of an on-chip antenna in accordance with an illustrative embodiment <NUM>. The die comprises a substrate <NUM>, a metal patch <NUM>, and TSV <NUM>. A dielectric layer may be deposited between the patch <NUM> and the substrate <NUM>. The substrate <NUM> is configured as a reflector (ground plane). Although one TSV <NUM> is shown connected to the patch, there may be a plurality of TSV's connected to a patch.

<FIG> is a cross-sectional view of an on-chip antenna <NUM> in accordance with an illustrative embodiment formed on the backside of a die <NUM>. On-chip antenna may include a backside silicon substrate <NUM>, a dielectric layer <NUM> deposited on the backside of the substrate <NUM>, and an RDL patch <NUM> formed on the dielectric layer <NUM>. In this embodiment, dielectric <NUM> may be silicon dioxide, and the reflector may be silicon substrate <NUM>. Die <NUM> may also include active side circuits <NUM>, including routing and wiring <NUM>. Dielectric layer <NUM> may comprise silicon dioxide (Si02). In an embodiment, the substrate <NUM> may have a dielectric constant (er) of <NUM>. Since the reflector needs to be highly conductive, such low resistive substrate aids the on-chip antenna. The substrate may comprise silicon but may be a material such as silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide (GaAs), an alloy of silicon and germanium, or indium phosphide (InP), or combinations thereof. In another embodiment, TSV <NUM> may connect the RDL patch <NUM> with the active layer circuits <NUM>.

<FIG> is a cross-sectional view of an on-chip antenna <NUM> in accordance with an example. The die <NUM> may comprise a metal layer <NUM> deposited on the backside <NUM> of the active layer <NUM>, a dielectric layer <NUM>, which may be Si02, and an RDL patch antenna <NUM> formed on the dielectric362. Metal layer <NUM> may be formed by RDL. The active layer <NUM> may comprise active circuits, including routing and wiring <NUM>. The substrate may be silicon but may be a material such as silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide (GaAs), an alloy of silicon and germanium, or indium phosphide (InP), or combinations thereof. TSV <NUM> may connect the RDL patch <NUM> with the active layer circuits <NUM>. In this configuration, the metal layer <NUM> is configured as the reflector, and the layer <NUM> is configured as a dielectric. In other words, two different RDL layers are fabricated to create a metal patch (RDL) <NUM>- Si02 dielectric <NUM> - metal ground plane (RDL) <NUM> on the backside.

<FIG> is a cross-sectional view of an on-chip antenna <NUM> in accordance with another example. The die <NUM> comprises an RDL patch <NUM> formed on the backside substrate <NUM>, and active layer <NUM> containing filler cells <NUM> and at least one metal layer <NUM>. One of the metal layers <NUM> that is one of active layers of the die, may be configured as a reflector (ground plane). In this configuration, the backside substrate <NUM> may operate as the dielectric. A separate dielectric layer may not be required. TSV <NUM> connects the RDL patches <NUM> with the active layer <NUM> including routing and wiring <NUM>.

<FIG> shows an antenna system comprising an on-chip antenna and circuitry in accordance with an illustrative embodiment <NUM>. The system may comprise an antenna array <NUM> an array of transceivers <NUM> an array of baseband signal processors <NUM>. Each separate antenna <NUM> may be connected to its own transceiver <NUM>, and signal processors <NUM>. In an embodiment, the antenna patches are formed utilizing RDL in the backside of a substrate <NUM>, <NUM>; transceiver <NUM> and signal processors <NUM> are present in the active layer <NUM>, <NUM> of the die. TSVs <NUM>, <NUM> feed the antenna patches from the active layer. Optionally, the transceiver, signal processors or other circuitry may be fabricated in a separate die as components of a 3D stack. In this configuration, the die comprising the antenna patches is flipped and connected to the transceiver or other circuitry die through the flip chip method as described above in <FIG>. Interaction between the active layer and the antenna patches is minimized and the location and amount of feeds can be selected for the proper impedance, and to create a current distribution that results in the desired polarization of the radiated/received wave. Space consuming quarter- wavelength lines or inset feeds are not required.

<FIG> is a flow chart showing the fabrication of the on-chip antenna in accordance with an illustrative embodiment. A substrate is provided <NUM>, a dielectric layer preferably Si0 <NUM> is deposited on the backside of the substrate that is preferably silicon <NUM>. A RDL may then be formed on the dielectric layer to form a plurality of antenna patches <NUM>. Various deposition techniques may be used including physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others may be used. The various layers may be connected by the TSV. Optionally, the on-chip antenna is packaged as a 3D stack <NUM>.

<FIG> is a flow chart showing the fabrication of the on-chip antenna in accordance with an example. A substrate is provided <NUM>, and a first RDL is formed on the backside of a substrate <NUM>. A dielectric layer, preferably silicon dioxide, is deposited on the first RDL layer <NUM>. A second RDL forming antenna patches is formed on the dielectric layer <NUM>. The various layers may be connected by the TSV. In this example, the first RDL is configured as the ground plane. Optionally, the on-chip antenna is packaged as a 3D stack <NUM>.

In another example, <FIG> is a flow chart showing the fabrication of the on-chip antenna. A substrate is provided <NUM>, and a RDL is formed on the backside of a substrate forming a plurality of antenna patches <NUM>. A metal layer is deposited on the active layer of the substrate <NUM>. Filler cells may be added between the substrate and the metal layer for connecting the gaps created during fabrication or may be added to improve substrate biasing. The various layers may be connected by the TSV. Optionally, the on-chip antenna is packaged as a 3D stack <NUM>.

The on-chip antenna fabricated according to <FIG>, may be packaged as a 3D stack. In this configuration, the die comprising the on-chip antenna may be flipped such that the active layer of the die is connected to other die. Since the antenna patches are on the backside, flipping the die causes the patches to be exposed to the air while packaged in a 3D stack.

<FIG> shows a cross-sectional view of an on-chip antenna to define the dimensional terminology in accordance with an illustrative embodiment. The die <NUM> comprises a RDL patch <NUM> formed on the backside of a substrate <NUM>, and a ground plane <NUM>. The RDL patch <NUM> comprises a width <NUM>, a length <NUM>. The substrate <NUM> has a thickness <NUM>. The direction of the magnetic field is shown in <NUM>.

Tests were undertaken to determine the dimensions of the patches relative to dielectric thickness, dielectric constant, and signal frequency. Generally, the lateral dimension of a patch element is proportional to the wavelength/<NUM> divided by the square root of the dielectric constant of the dielectric layer. The dimensions of the patches and the dielectric layers of some exemplary embodiments of the on-chip antenna are shown in Table <NUM>.

These measurements show that when the thickness of the dielectric layer increases, it may be possible to reduce the patch size. Consistent with these measurements, in an embodiment, a die of <NUM> width by <NUM> length may have an array of about <NUM> antenna patches, where a single patch has a length of <NUM> and a width of <NUM>. In addition, since the antenna is formed on the backside of the die, the risk of interference with the circuits in the active layer is low. Similarly, the entire backside of the die may be available for forming the patches due to low risk of interference with circuitry.

It should be understood that the particular embodiments shown in the drawings and described within this specification are for purposes of example and should not be construed to limit the invention, which will be described in the claims below. Further, it is evident that those skilled in the art may now make numerous uses and modifications of the specific embodiment described, without departing from the inventive concepts. Equivalent structures and processes may be substituted for the various structures and processes described; the subprocesses of the inventive method may, in some instances, be performed in a different order; or a variety of different materials and elements may be used. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in and/or possessed by the system and method described.

In an example, an on-chip antenna (<NUM>) comprises an integrated circuit chip (<NUM>) having an active side (<NUM>) and a backside (<NUM>); a ground plane (<NUM>); a dielectric formed on the ground plane (<NUM>); and a redistribution layer formed on the dielectric layer (<NUM>), the distribution layer including an one or more on-chip antenna elements (<NUM>). Optionally, the backside includes a high conducting backside substrate (<NUM>) and the ground plane comprises the high conducting backside substrate (<NUM>). Optionally, the dielectric layer (<NUM>) comprises a silicon dioxide layer formed on the backside substrate (<NUM>). Optionally, the backside (<NUM>) includes a backside substrate (<NUM>) and the dielectric comprises the backside substrate. Optionally, the active side (<NUM>) includes a metal layer (<NUM>) and the ground plane comprises the active side metal layer (<NUM>). Optionally, the one or more on-chip antenna patch elements comprise a phased array (<NUM>).

In another example, an on-chip antenna system comprises an integrated circuit die (<NUM>) having an active side (<NUM>) and a backside (<NUM>); a ground plane (<NUM>); a dielectric formed on the ground plane (<NUM>); a redistribution layer formed on said dielectric layer (<NUM>), the distribution layer including an one or more on-chip antenna elements (<NUM>); and wherein said active side comprises a transceiver (<NUM>) and baseband signal processing circuit (<NUM>). Optionally, said integrated circuit die (<NUM>) is mounted on a flip chip package in a flip chip configuration <NUM>. Optionally, through silicon via structures (<NUM>, <NUM>, <NUM>) connect the on-chip antenna elements (<NUM>, <NUM>) and the transceiver (<NUM>) and baseband signal processing circuits (<NUM>). Optionally, there are a plurality of the on-chip antenna elements (<NUM>) and a plurality of the transceiver (<NUM>) and baseband signal processing circuits (<NUM>); one of the transceiver and baseband signal processing circuits is electrically connected to each of the plurality of on-chip antenna elements by at least one of the through silicon via structures (<NUM>); and the on-chip antenna system comprises a phased array (<NUM>). Optionally, the backside (<NUM>) includes a highly conductive backside substrate (<NUM>) and the ground plane (<NUM>) comprises the highly conductive backside substrate (<NUM>). Optionally, the backside includes a backside substrate (<NUM>) and the dielectric comprises the backside silicon substrate (<NUM>). Optionally, there is a plurality of the redistribution layers (<NUM>), the one or more patch elements are formed by a first one of the redistribution layers, and said ground plane is formed by a second one of the redistribution layers (<NUM>). Optionally, the operating frequency of said system is from <NUM> to <NUM>. Optionally, the operating frequency of said system is from <NUM> and <NUM>, the length of each of the patches (<NUM>) is from <NUM> to <NUM>, and the width (<NUM>) is from <NUM> to <NUM>.

In another example, an integrated circuit comprising: an integrated circuit die (<NUM>) having an active side (<NUM>) and a backside (<NUM>); a ground plane (<NUM>); a dielectric formed on the ground plane (<NUM>); a redistribution layer formed on the dielectric layer (<NUM>), the redistribution layer being formed on the backside of the integrated circuit die (<NUM>) and including an one or more on-chip antenna elements (<NUM>). Optionally, the backside (<NUM>) includes a highly conductive backside substrate (<NUM>) and the ground plane (<NUM>) comprises the highly conductive backside substrate. Optionally, the backside (<NUM>) includes a backside substrate (<NUM>) and the dielectric (<NUM>) comprises the backside silicon substrate (<NUM>).

Claim 1:
A patch antenna system comprising:
an integrated circuit die (<NUM>) comprising active side circuits (<NUM>) including routing and wiring (<NUM>), and a backside silicon substrate (<NUM>), wherein the backside silicon substrate is a reflector;
a dielectric layer (<NUM>) formed on said backside substrate (<NUM>); and
a redistribution layer (<NUM>) formed on said dielectric layer (<NUM>), said redistribution layer including one or more patch antenna elements (<NUM>);
wherein said active side (<NUM>) comprises a transceiver (<NUM>) and baseband signal processing circuit (<NUM>).