Patent Description:
With the development of semiconductor technologies, there are a higher integration level of the semiconductor structure (such as the memory), a smaller spacing between devices in the semiconductor structure and a smaller spacing between adjacent conductive devices (such as bit lines (BLs)) in the semiconductor structure. A parasitic capacitance arising from adjacent conductive devices and the insulating material between the conductive devices is directly proportional to a dielectric constant of the insulating material, while inversely proportional to a spacing between the two conductive devices. While the spacing between the BLs is decreased, an increasingly larger parasitic capacitance is generated to cause a resistor capacitor (RC) delay of the semiconductor structure, to affect working efficiency of the semiconductor structure.

D1 (<CIT>) discloses vertical-channel semiconductor device.

D2 (<CIT>) discloses method for forming buried bit line, semiconductor device having the same, and fabricating method thereof.

In view of the above problem, embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, to reduce the parasitic capacitance of the semiconductor structure and improve the working efficiency of the semiconductor structure.

A manufacturing method of a semiconductor structure according to the invention is set forth in the appended claims.

The semiconductor structure provided by the embodiment of the present disclosure at least has the following advantages:
According to the semiconductor structure provided by the embodiment of the present disclosure, the BLS extend along the first direction, the first trenches are formed between adjacent two of the BLS, the protective layer is provided in the first trenches, the air gaps are formed between the protective layer and the bottoms of the first trenches, and parts of the side surfaces of the BLS are exposed in the air gaps. As the air has a dielectric constant of about <NUM>, the dielectric constant of the structure between the BLs is reduced, thus reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.

An embodiment of the present disclosure provides a manufacturing method of a semiconductor structure. Air gaps are formed between BLs, and parts of side surfaces of the BLs are exposed in the air gaps. As the air has a dielectric constant of about <NUM>, the dielectric constant of the structure between the BLs is reduced, thus reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.

In order to make the objectives, features and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure are described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the disclosure without creative efforts shall fall within the protection scope of the present disclosure.

Referring <FIG>, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, including the following steps:
Step S101: Provide a substrate, a plurality of spaced first trenches being formed in the substrate, and the first trenches extending along a first direction.

<FIG> is a top view of a semiconductor structure according to an embodiment of the present disclosure. Referring to <FIG>, word lines (WLs) <NUM> and BLs <NUM> are formed in the semiconductor structure. The BLs <NUM> extend along the first direction, while the WLs <NUM> extend along the second direction. There is an included angle between the first direction and the second direction. For example, the first direction may be perpendicular to the second direction. Specifically, as shown in <FIG>, the BLs <NUM> extend along a vertical direction (Y direction), while the WLs <NUM> extend along a horizontal direction (X direction). Gate structures are formed in the WLs <NUM>. The WLs <NUM> or the BLs <NUM> may be straight lines, and may also be fold lines.

<FIG> shows sections at different positions. Specifically, the section A-A is parallel to the extension direction of the BLs <NUM> and located on the BLs <NUM>, and the section B-B is parallel to the extension direction of the BLs <NUM> and located between adjacent BLs <NUM>. The section C-C is parallel to the extension direction of the WLs <NUM> and located on the WLs <NUM>, and the section D-D is parallel to the extension direction of the WLs <NUM> and located between adjacent WLs <NUM>.

Referring to <FIG>, the substrate <NUM> may be a semiconductor substrate. The semiconductor substrate may include a silicon element. For example, the substrate may be a silicon substrate, a silicon-germanium substrate or a silicon on insulator (SOI) substrate. For convenience, detailed descriptions will be made by taking the silicon substrate as the substrate <NUM> for example in the embodiment of the present disclosure and the following embodiments.

Referring to <FIG>, a plurality of first trenches <NUM> are formed in the substrate <NUM>. The first trenches <NUM> extend along the first direction and are spaced apart. Exemplarily, the substrate <NUM> is etched to form the first trenches <NUM> in the substrate <NUM>. Specifically, the first trenches <NUM> are formed by self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) to increase the density of the first trenches <NUM>.

Step S102: Form a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer.

Referring to <FIG>, bottoms of the first trenches <NUM> are filled with the sacrificial layer <NUM>, and remaining parts of the first trenches <NUM> are filled with the first protective layer <NUM>. The sacrificial layer <NUM> and the first protective layer <NUM> are made of different materials. For example, the sacrificial layer <NUM> has a larger etch selectivity than the first protective layer <NUM>, which makes the first protective layer <NUM> less etched in subsequent removal of the sacrificial layer <NUM>. Exemplarily, the material of the first protective layer <NUM> may be silicon oxide, while the material of the sacrificial layer <NUM> may be silicon nitride.

Referring to <FIG>, the first protective layer <NUM> spaced by the first trenches <NUM> is provided with etching holes <NUM>. The etching holes <NUM> penetrate through the first protective layer <NUM>. The etching holes <NUM> expose the sacrificial layer <NUM>. Based on a plane parallel to the substrate <NUM>, sections of the etching holes <NUM> each may be of a circular shape, an elliptical shape, a square shape, a rectangular shape or other polygonal shapes. As shown in <FIG>, parts of walls of the etching holes <NUM> may further be sidewalls of the first trenches <NUM>. The etching holes <NUM> may be formed in edges of the first trenches <NUM> and away from regions for forming the WLS <NUM>. There are one or more etching holes <NUM> in each first trench <NUM>. For example, two ends of the first trench <NUM> are respectively provided with one etching hole <NUM>.

In order to increase a surface area of the sacrificial layer <NUM> exposed in the etching holes <NUM> and remove the sacrificial layer subsequently, the etching holes <NUM> extend to the sacrificial layer <NUM>, as shown in <FIG> Exemplarily, bottoms of the etching holes <NUM> are located in the sacrificial layer <NUM>, or the etching holes <NUM> penetrate through the sacrificial layer <NUM>.

In a possible example, referring to <FIG>, the step of forming a sacrificial layer <NUM> in the first trenches <NUM> and a first protective layer <NUM> on the sacrificial layer <NUM>, the sacrificial layer <NUM> and the first protective layer <NUM> filling up the first trenches <NUM>, and the first protective layer <NUM> in the first trenches <NUM> being provided with etching holes <NUM> penetrating through the first protective layer <NUM> may include:
Step S1021: Deposit the sacrificial layer in the first trenches, the sacrificial layer filling the bottoms of the first trenches.

Referring to <FIG>, the sacrificial layer <NUM> is formed in the first trenches <NUM> by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). The thickness direction of the sacrificial layer <NUM> and the depth direction of the first trench <NUM> are the same and both are a direction perpendicular to the substrate <NUM> (Z direction shown in <FIG>).

Step S1022: Deposit the first protective layer on the sacrificial layer, the first protective layer leveling off the first trenches.

Referring to <FIG>, the first protective layer <NUM> is deposited on the sacrificial layer <NUM> and the substrate <NUM>. The first protective layer <NUM> fills the first trenches <NUM> and covers a top surface of the substrate <NUM>. As shown in <FIG>, the top surface of the substrate <NUM> refers to an upper surface of the substrate <NUM>. The first protective layer <NUM> on the top surface of the substrate <NUM> is removed to expose the substrate <NUM>. Exemplarily, the first protective layer <NUM> on the top surface of the substrate <NUM> is removed by chemical mechanical polishing (CMP). After the first protective layer <NUM> is removed, the top surface of the substrate <NUM> is exposed.

Step S1023: Etch the first protective layer at edges of the first trenches to form the etching holes.

As shown in <FIG>, in some possible examples, a mask plate is deposited on the substrate <NUM> and the first protective layer <NUM>. With the mask plate as a mask, the first protective layer <NUM> is removed by dry etching or wet etching to form the etching holes <NUM> shown in <FIG>. The mask plate is then removed.

Step S103: Remove the sacrificial layer with the etching holes to form air gaps.

Referring to <FIG>, the sacrificial layer <NUM> is removed with an etching gas or an etching solution in the etching holes <NUM>. After the sacrificial layer <NUM> in the first trenches is removed, air gaps <NUM> are formed in the first trenches. As shown in <FIG>, the air gap <NUM> is located under the etching hole <NUM>, and communicates with the etching hole <NUM>.

Step S104: Carry out a silicidation reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches, thereby forming, in the substrate, BLs extending along the first direction, parts of side surfaces of the BLs being exposed in the air gaps.

Referring to <FIG>, the BLs <NUM> are formed in the substrate <NUM>. The BLs <NUM> extend along the first direction. The BLs <NUM> are located between adjacent first trenches, and close to the bottoms of the first trenches. The BLS <NUM> are as wide as the substrate <NUM> between adjacent first trenches, such that parts of side surfaces of the BLs <NUM> are exposed in the air gaps <NUM>. As shown in <FIG>, lower parts of the side surfaces of the BLS <NUM> are exposed in the air gaps <NUM>, while upper parts of the side surfaces of the BLS <NUM> contact the first protective layer <NUM>.

The BLs <NUM> may be formed by the silicidation reaction. A material of the BLs <NUM> includes metal silicide, such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide or nickel silicide, to reduce resistances of the BLs <NUM>. Exemplarily, as shown in <FIG>, the step of carrying out a silicidation reaction on the substrate <NUM> between adjacent ones of the first trenches <NUM> and close to bottoms of the first trenches <NUM>, thereby forming, in the substrate <NUM>, BLs <NUM> extending along the first direction, parts of side surfaces of the BLS <NUM> being exposed in the air gaps <NUM> includes:
Step S1041: Etch the substrate and the first protective layer to form a plurality of spaced second trenches, the second trenches extending along a second direction and not communicating with the air gaps.

Referring to <FIG>, the substrate <NUM> and the first protective layer <NUM> are etched to form a plurality of second trenches <NUM>. The second trenches <NUM> are spaced apart and extend along the second direction. The second trenches <NUM> do not communicate with the air gaps <NUM>, namely bottoms of the second trenches <NUM> are located in the substrate <NUM> and the first protective layer <NUM>, without penetrating through the first protective layer <NUM>. Therefore, the remaining first protective layer <NUM> seals tops of the air gaps <NUM>, which prevents other materials from falling into the air gaps <NUM> in subsequent manufacture and reduces the parasitic capacitances through the air gaps <NUM>. Step S1042: Form a second protective layer on sidewalls of the second trenches, the second protective layer in the second trenches enclosing third trenches.

Referring to <FIG>, a second protective layer <NUM> is formed on sidewalls of the second trenches <NUM>. The second protective layer <NUM> covers the sidewalls of the second trenches <NUM>. The second protective layer <NUM> in the second trenches <NUM> encloses third trenches <NUM>. The third trenches <NUM> exposes parts of the bottoms of the second trenches <NUM>. The first protective layer <NUM> and the second protective layer <NUM> may be made of a same material, such that the first protective layer <NUM> and the second protective layer <NUM> are formed into a whole.

In a possible embodiment, a second initial protective layer is deposited on the sidewalls and bottoms of the second trenches <NUM>, the substrate <NUM> and the first protective layer <NUM>, the second initial protective layer in the second trenches <NUM> enclosing the third trenches <NUM>. The second initial protective layer is etched along the third trenches <NUM> to remove the second initial protective layer on the bottoms of the second trenches <NUM>, the remaining second initial protective layer being formed into the second protective layer <NUM>.

In another possible embodiment, referring to <FIG>, a third protective layer <NUM> is further deposited on the substrate <NUM> and the first protective layer <NUM>, namely the third protective layer <NUM> covers the top surface of the substrate <NUM>. The third protective layer <NUM>, the second protective layer <NUM> and the first protective layer <NUM> may be made of a same material to form a whole.

Referring to <FIG>, a second initial protective layer is deposited on the sidewalls and bottoms of the second trenches <NUM> and on the third protective layer <NUM>. The second initial protective layer on the third protective layer <NUM> and the second initial protective layer on the bottoms of the second trenches <NUM> are removed to expose the bottoms of the second trenches <NUM>, the remaining second initial protective layer forming the second protective layer <NUM>.

It is to be understood that when the second initial protective layer is etched along the third trenches <NUM> by anisotropic etching to remove the second initial protective layer on the bottoms of the second trenches <NUM>, the second initial protective layer on the third protective layer <NUM> is etched inevitably. With the third protective layer <NUM>, only the substrate <NUM> in the second trenches <NUM>, rather than the top surface of the substrate <NUM>, is exposed to ensure forming positions of the BLs <NUM>.

As shown in <FIG>, a plurality of pillars are formed on an upper part of the substrate <NUM>. The second protective layer <NUM> covers outer peripheral surfaces of the pillars. The third protective layer <NUM> covers top surfaces of the pillars. The substrate <NUM> on bottoms of the third trenches <NUM> is exposed. For convenience, the case where the third protective layer <NUM> is formed on the substrate <NUM> is used as an example for detailed descriptions in the embodiment of the present disclosure and the following embodiments.

It is to be noted that the step of depositing a third protective layer <NUM> on the substrate <NUM> and the first protective layer <NUM> may be executed before the step of etching the substrate <NUM> and the first protective layer <NUM> to form a plurality of spaced second trenches <NUM>, the second trenches <NUM> extending along a second direction and not communicating with the air gaps <NUM> (Step S1041), namely the step is executed before Step S104. Specifically, the step may be executed after Step S1022, may also be executed after Step S1023, and may further be executed after Step S103.

Preferably, after the step of depositing the first protective layer <NUM> on the sacrificial layer <NUM>, the first protective layer <NUM> leveling off the first trenches <NUM> (Step S1023), the third protective layer <NUM> is deposited on the substrate <NUM> and the first protective layer <NUM>. The above arrangement facilitates the manufacture and reduces the manufacturing difficulty of the third protective layer <NUM>, and can further prevent the third protective layer <NUM> from falling into the etching holes <NUM> or the air gaps <NUM> to improve the performance of the semiconductor structure.

Correspondingly, the step of etching the substrate <NUM> and the first protective layer <NUM> to form a plurality of spaced second trenches <NUM>, the second trenches <NUM> extending along a second direction and not communicating with the air gaps <NUM> (Step S1041) includes: Etch the substrate <NUM>, the first protective layer <NUM> and the third protective layer <NUM> to form the plurality of spaced second trenches <NUM>, and remain the third protective layer <NUM> between adjacent ones of the second trenches <NUM>.

Step S1043: Deposit metal on bottoms of the third trenches, and carry out the silicidation reaction by annealing to form the BLs.

Referring to <FIG>, the metal may be one of cobalt, titanium, tantalum, nickel and tungsten, and may also be refractory metal. The metal reacts with the substrate <NUM> to form metal silicide, and the substrate <NUM> between adjacent first trenches is silicided completely. The metal silicide is connected along the first direction to form the BLs <NUM>. Parts of top surfaces of the BLs <NUM> are exposed in the third trenches <NUM>, and parts of side surfaces of the BLs <NUM> are exposed in the air gaps <NUM>.

The annealing includes rapid thermal annealing (RTA). The annealing temperature is matched with the material of the metal and the material of the substrate <NUM>. For example, when the substrate <NUM> is made of silicon and the metal is the cobalt, the annealing temperature may be <NUM>-<NUM>.

According to the manufacturing method of a semiconductor structure provided by the embodiment of the present disclosure, the sacrificial layer <NUM> is removed to form the air gaps <NUM> between the BLs <NUM> extending along the first direction, and parts of side surfaces of the BLs <NUM> are exposed in the air gaps <NUM>. As the air has a dielectric constant of about <NUM>, the dielectric constant of the structure between the BLs <NUM> is reduced, thus reducing the parasitic capacitance of the semiconductor structure and improving the working efficiency of the semiconductor structure.

It is to be noted that, before the step of forming a second protective layer <NUM> on sidewalls of the second trenches <NUM>, the second protective layer <NUM> in the second trenches <NUM> enclosing third trenches <NUM>, the manufacturing method of a semiconductor structure further includes: Form active regions <NUM> in the substrate <NUM> away from the bottoms of the first trenches <NUM>, where the active regions <NUM> each include a source region, a drain region and a channel region; and the source region, the channel region and the drain region are arranged sequentially along a direction perpendicular to the bottoms of the first trenches <NUM>.

Before the BLs <NUM> are formed, a plurality of spaced active regions are formed in the substrate <NUM>. The active regions each include a source region, a drain region and a channel region. The channel region is located between the source region and the drain region. In the embodiment of the present disclosure, the source region, the channel region and the drain region are arranged vertically, namely arranged sequentially along the direction perpendicular to the bottoms of the first trenches <NUM> to form a vertical transistor. The source regions or the drain regions are close to the bottoms of the first trenches <NUM>. The source regions or the drain regions close to the bottoms of the first trenches <NUM> are electrically connected to the subsequently formed BLS <NUM>, namely the source regions or the drain regions are electrically connected to the BLS <NUM>. In this way, under the same area of the substrate <NUM>, the channel regions can be effectively lengthened by increasing heights of the active regions, thus reducing or preventing the short channel effect and improving the performance of the semiconductor structure.

In some possible embodiments of the present disclosure, after the step of etching the substrate <NUM> and the first protective layer <NUM> to form a plurality of spaced second trenches <NUM>, the second trenches <NUM> extending along a second direction and not communicating with the air gaps <NUM> (Step S1041), the first trenches <NUM> and the second trenches <NUM> isolate the substrate <NUM> into a plurality of spaced pillar structures. The pillar structures are doped to form the source regions and the drain regions in the pillar structures. The active regions are formed in the substrate <NUM> away from the bottoms of the first trenches <NUM>.

In other possible embodiments of the present disclosure, after the step of providing a substrate <NUM>, a plurality of spaced first trenches <NUM> being formed in the substrate <NUM>, and the first trenches <NUM> extending along a first direction (Step S101), the substrate <NUM> between adjacent first trenches <NUM> is doped to form the active regions, namely the active regions are of a strip shape, and extend along the first direction. After the second trenches <NUM> are formed, the second trenches <NUM> cut off the active regions to form a plurality of spaced pillar active regions.

It is to be noted that, referring to <FIG>, after the step of depositing metal on bottoms of the third trenches <NUM>, and carrying out the silicidation reaction by annealing to form the BLs <NUM>, the manufacturing method of a semiconductor structure further includes:
Step a: Form first insulating layers in the third trenches, the first insulating layers filling the third trenches.

Referring to <FIG>, the first insulating layers <NUM> are formed in the third trenches <NUM> by deposition. The first insulating layers <NUM> extend along the second direction. The first insulating layers <NUM> fill up the third trenches <NUM>. For example, the first insulating layers <NUM> level off the third trenches <NUM>. As shown in <FIG>, the third protective layer <NUM> on the substrate <NUM> is removed to expose the substrate <NUM>. Surfaces of the first insulating layers <NUM> away from the air gaps <NUM> are flush with the substrate <NUM>, or top surfaces of the first insulating layers <NUM> are flush with the top surface of the substrate <NUM>. The first insulating layers <NUM> and the substrate <NUM> are formed into a regular surface to manufacture other structures conveniently.

The material of the first insulating layers <NUM> is different from that of the second protective layer <NUM> and that of the first protective layer <NUM>, so as to remove the second protective layer <NUM> or the first protective layer <NUM> individually. Exemplarily, the material of the first insulating layers <NUM> may be silicon nitride, and the material of the first protective layer <NUM> and/or the second protective layer <NUM> may be silicon oxide.

Step b: Remove, along a direction perpendicular to the substrate, the first protective layer and the second protective layer to a preset depth to form filling spaces, the filling spaces exposing side surfaces of the active regions.

Referring to <FIG>, a part of the first protective layer <NUM> and a part of the second protective layer <NUM> are removed by etching. The part of the first protective layer <NUM> and the part of the second protective layer <NUM> are removed along the direction perpendicular to the substrate <NUM>, to form recesses having a preset depth in the substrate <NUM>. The recesses each include a filling space <NUM>. The filling spaces <NUM> expose the side surfaces of the active regions. Specifically, the filling spaces <NUM> expose at least parts of the channel regions.

In some possible embodiments, as shown in <FIG>, the step of removing, along a direction perpendicular to the substrate <NUM>, the first protective layer <NUM> and the second protective layer <NUM> to a preset depth to form filling spaces <NUM>, the filling spaces <NUM> exposing side surfaces of the active regions <NUM> includes:
Etch the second protective layer <NUM> and the first protective layer <NUM> to an initial depth to form filling channels <NUM>. Referring to <FIG>, the first protective layer <NUM> and the second protective layer <NUM> are etched along the direction perpendicular to the substrate <NUM> to form filling channels <NUM> having an initial depth. The higher one of the source region and the drain region is opposite to the filling channel <NUM>. There are a plurality of filling trenches <NUM>, the filling channels <NUM> are isolated by the first insulating layers <NUM>.

After the filling channels <NUM> are formed, a second insulating layer <NUM> is deposited in the filling channels <NUM>. The second insulating layer <NUM> fills up the filling channels <NUM> between the substrate <NUM> and the first insulating layers <NUM>. Referring to <FIG>, the second insulating layer <NUM> is deposited in the filling channels <NUM>, and the second insulating layer <NUM> fills up the filling channels <NUM> between the substrate <NUM> and the first insulating layers <NUM>. Specifically, the second insulating layer <NUM> is formed on sidewalls of the filling channels <NUM>. The second insulating layer <NUM> blocks off the filling channels <NUM> between the active regions and the first insulating layers <NUM>. After the second insulating layer <NUM> is formed, the filling channels <NUM> are isolated into a plurality of spaced openings.

After depositing the second insulating layer <NUM>, the remaining first protective layer <NUM> and the remaining second protective layer <NUM> are etched to a preset depth to form filling spaces <NUM>. Referring to <FIG>, the first protective layer <NUM> and the second protective layer <NUM> are etched continuously to the preset depth through the remaining filling channels <NUM>. A part of the remaining first protective layer <NUM> and a part of the remaining second protective layer <NUM> are removed to form the filling spaces <NUM>. The filling spaces <NUM> are located under the filling channels <NUM> and communicate with the filling channels <NUM>.

Step c: Form gate structures in the filling spaces, the gate structures extending along the second direction and surrounding the active regions.

Exemplarily, referring to <FIG>, the step of forming gate structures <NUM> in the filling spaces <NUM>, the gate structures <NUM> extending along the second direction and surrounding the active regions includes:
Form oxide layers <NUM> on inner surfaces of the filling spaces <NUM>. Referring to <FIG>, the oxide layers <NUM> are deposited on the inner surfaces of the filling spaces <NUM>. The oxide layers <NUM> cover exposed outer peripheral surfaces of the active regions, parts of side surfaces of the first insulating layers <NUM> and a bottom surface of the second insulating layer <NUM>. The oxide layers <NUM> annularly provided on the outer peripheral surfaces of the active regions are formed into gate oxide layers of vertical transistors. The oxide layers <NUM> may be silicon oxide layers.

Then, conductive layers <NUM> are formed in the filling spaces <NUM> after the oxide layers <NUM> are formed. The conductive layers <NUM> are opposite to at least parts of the channel regions. Referring to <FIG>, the conductive layers <NUM> are deposited in the filling spaces <NUM> and etched back. The conductive layers <NUM> fill at least parts of filling spaces <NUM>. The oxide layers <NUM> and the conductive layers <NUM> are formed into the gate structures <NUM>. The gate structures <NUM> extend along the second direction and surround the active regions. The gate structures <NUM> are formed in the WLs <NUM>, namely the gate structures <NUM> are constituted as parts of the WLs <NUM>.

It is to be noted that, after the step of forming gate structures <NUM> in the filling spaces <NUM>, the gate structures <NUM> extending along the second direction and surrounding the active regions, the manufacturing method of a semiconductor structure further includes: Deposit a third insulating layer <NUM> on the gate structures <NUM>, the third insulating layer <NUM> covering the gate structures <NUM> and filling up the remaining filling channels <NUM>.

Referring to <FIG>, the third insulating layer <NUM> is deposited in the remaining filling channels <NUM>. The third insulating layer <NUM> fills up the filling channels <NUM>. By covering the gate structures <NUM> with the third insulating layer <NUM>, the gate structures <NUM> are insulated. The third insulating layer <NUM>, the second insulating layer <NUM> and the first insulating layers <NUM> may be made of a same material to form into a whole, thus implementing electrical isolation for the gate structures <NUM>. Referring to <FIG> and <FIG>, after the third insulating layer <NUM> is formed, contact nodes <NUM> and capacitors <NUM> are formed on the substrate <NUM>. The vertical transistors are electrically connected to the capacitors <NUM> through the contact nodes <NUM>.

Referring to <FIG>, and <FIG> to <FIG>, an embodiment of the present disclosure further provides a semiconductor structure, including a substrate <NUM>. The substrate <NUM> may be a silicon-containing substrate, such as a silicon substrate, a silicon-germanium substrate or an SOI substrate. A plurality of spaced BLs <NUM> are formed in the substrate <NUM>. The BLs <NUM> extend along a first direction. First trenches are formed between adjacent two of the BLs <NUM>, namely the first trenches also extend along the first direction. As shown in <FIG>, the first direction is the Y direction. A material of the BLs <NUM> includes metal silicide, such as cobalt silicide, tungsten silicide, titanium silicide, platinum silicide or nickel silicide, to reduce resistances of the BLs <NUM>.

The BLs <NUM> each are provided thereon with at least an active region <NUM>. The active region <NUM> includes a source region, a channel region and a drain region that are stacked sequentially, namely the source region, the channel region and the drain region are arranged vertically. One of the source region and the drain region is electrically connected to the BL <NUM>. For example, the source region is located on the channel region, the drain region is located under the channel region, and the drain region is electrically connected to the BL <NUM>.

A protective layer (including a first protective layer <NUM> and a second protective layer <NUM>) is provided in the first trenches. Air gaps <NUM> are formed between the protective layer and bottoms of the first trenches. Parts of side surfaces of the BLs <NUM> are exposed in the air gaps <NUM>. As shown in <FIG>, lower parts of the side surfaces of the BLs <NUM> are exposed in the air gaps <NUM>, while upper parts of the side surfaces of the BLs <NUM> contact the protective layer.

The protective layer is further filled between adjacent ones of the active regions. As shown in <FIG>, a top surface of the protective layer is higher than top surfaces of the BLs <NUM>. The top surface refers to a surface away from the bottom of the first trench. A plurality of spaced first insulating layers <NUM> are arranged on the protective layer. The first insulating layers <NUM> extend along a second direction (X direction in <FIG>). The active regions <NUM> in the second direction are formed into rows. The first insulating layers <NUM> are arranged between adjacent two rows of the active regions <NUM>, and spaced apart from the active regions <NUM>. The first insulating layers <NUM> isolate adjacent two rows of the active regions <NUM>, such that one row of the active regions <NUM> along the second direction is connected to one of gate structures <NUM>.

The gate structures <NUM> are provided between the first insulating layers <NUM> and the active regions <NUM>. The gate structures <NUM> extend along the second direction, and surround the active regions <NUM>. The gate structures <NUM> correspond to at least parts of the channel regions. The gate structures <NUM> each include an oxide layer and a conductive layer <NUM>. The oxide layer covers an outer surface of the conductive layer <NUM>. As shown in <FIG>, the oxide layer <NUM> covers a side surface, a bottom surface and a part of a top surface of the conductive layer <NUM>.

A second insulating layer <NUM> and a third insulating layer <NUM> further cover the gate structures <NUM>. As shown in <FIG>, the second insulating layer <NUM> is opposite to edge regions of the gate structures <NUM>, and the third insulating layer <NUM> is opposite to middle regions of the gate structures <NUM>. The second insulating layer <NUM> and the third insulating layer <NUM> are formed into a whole layer to cover the gate structures <NUM>. The first insulating layers <NUM>, the second insulating layer <NUM> and the third insulating layer <NUM> may be made of a same material such as silicon nitride, such that they are formed into a whole to implement electrical insulation on the gate structures <NUM>.

Referring to <FIG> and <FIG>, a contact node <NUM> is further provided on each of the active regions <NUM>. A capacitor <NUM> is provided on the contact node <NUM>. The capacitor <NUM> is electrically connected to the active region <NUM> through the contact node <NUM>. One of the source region and the drain region contacts the contact node <NUM>, for example, the source region contacts the contact node. The contact node <NUM> may be polycrystalline silicon. The capacitor <NUM> is configured to store data information.

According to the semiconductor structure provided by the embodiment of the present disclosure, the BLs <NUM> extend along the first direction, the first trenches <NUM> are formed between adjacent two of the BLs <NUM>, the protective layer is provided in the first trenches <NUM>, the air gaps <NUM> are formed between the protective layer and the bottoms of the first trenches <NUM>, and parts of the side surfaces of the BLs <NUM> are exposed in the air gaps <NUM>. As the air has a dielectric constant of about <NUM>, the dielectric constant of the structure between the BLs <NUM> is reduced, thus reducing the parasitic capacitance <NUM> of the semiconductor structure and improving the working efficiency of the semiconductor structure.

The embodiments or implementations of this specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments. The same or similar parts between the embodiments may refer to each other. In the descriptions of this specification, a description with reference to the term "one implementation", "some implementations", "an exemplary implementation", "an example", "a specific example", "some examples", or the like means that a specific feature, structure, material, or characteristic described in combination with the implementation(s) or example(s) is included in at least one implementation or example of the present disclosure.

Claim 1:
A manufacturing method of a semiconductor structure, comprising:
providing a substrate (<NUM>), a plurality of spaced first trenches (<NUM>) being formed in the substrate (<NUM>), and the first trenches (<NUM>) extending along a first direction;
forming a sacrificial layer (<NUM>) in the first trenches (<NUM>) and a first protective layer (<NUM>) on the sacrificial layer (<NUM>), the sacrificial layer (<NUM>) and the first protective layer (<NUM>) filling up the first trenches (<NUM>), and the first protective layer (<NUM>) in the first trenches (<NUM>) being provided with etching holes (<NUM>) penetrating through the first protective layer (<NUM>);
removing the sacrificial layer (<NUM>) via the etching holes (<NUM>) to form air gaps (<NUM>); and
carrying out a silicidation reaction on the substrate (<NUM>) between adjacent ones of the first trenches (<NUM>) and close to bottoms of the first trenches (<NUM>), so as to form, in the substrate (<NUM>), bit lines, BLs, (<NUM>) extending along the first direction, parts of side surfaces of the BLs (<NUM>) being exposed in the air gaps (<NUM>);
characterized in that, the carrying out a silicidation reaction on the substrate (<NUM>) between adjacent ones of the first trenches (<NUM>) and close to bottoms of the first trenches (<NUM>), so as to form, in the substrate (<NUM>), BLs (<NUM>) extending along the first direction, parts of side surfaces of the BLs (<NUM>) being exposed in the air gaps (<NUM>), comprises:
etching the substrate (<NUM>) and the first protective layer (<NUM>) to form a plurality of spaced second trenches (<NUM>), the second trenches (<NUM>) extending along a second direction and not communicating with the air gaps (<NUM>);
forming a second protective layer (<NUM>) on sidewalls of the second trenches (<NUM>), the second protective layer (<NUM>) in the second trenches (<NUM>) enclosing third trenches (<NUM>); and
depositing metal on bottoms of the third trenches (<NUM>), and carrying out the silicidation reaction by annealing to form the BLs (<NUM>).