Patent Description:
Document <CIT> shows a electrical power conversion system with a power electronic converter device comprising: (i) a converter circuit including an input side with input terminals, a three phase output side with output terminals, a first converter and three second converters, each of them connected in series with the first converter with respect to a respective phase, each of said second converters comprising a floating cell with a capacitive element in a DC intermediate circuit and semiconductor devices, and (ii) a control device for driving semiconductor devices of at least one of the converters via pulse-like signals. In detail the converter circuit consists of the first converter being a main converter and <NUM> auxiliary floating cells, one for each phase. In such a converter circuit the number of floating cells per phase is not fixed and more floating cells can be accommodated. The complete dc-to-ac conversion circuit therefore takes the form of a main power converter provided by the first converter, the auxiliary switching cells of the second converter, and passive filter circuits. The main converter is shown as a <NUM>-level neutral point clamped converter using IGCTs but other topologies and semiconductor types are possible. By means of the floating cells a DC voltage can be added to or subtracted from a DC voltage of the first converter with the help of the semiconductor devices.

Each of documents <CIT> and <CIT> describes a quite similar electrical power conversion system with a power electronic converter device.

<CIT> describes a power electronics circuit with an NPC converter and floating cells connected to the AC outputs of the NPC converter. A third harmonic is mixed to a reference oscillation for the power electronics circuit. It is possible to avoid energy feedback from the floating cells, and the efficiency of the entire system is increased. The switching losses could thus be kept extremely low. A voltage source providing energy to the cells via a diode rectifier is present. A special control in order to keep the cells voltage constant is not necessary. The only constraint is to keep the energy flow positive, because of the diode rectifier.

<NPL>, describes control of converters, in which several control schemes are mentioned, such as optimized pulse patterns and pulse width modulation.

<CIT> relates to converter control with optimized pulse patterns, where the optimized pulse patterns are adapted for minimizing a difference between a converter flux reference and a converter flux estimate.

It is an object of the present invention to provide means for enabling a stable operation of the power electronic converter device.

This object is achieved by the subject-matter of the independent claims. Advantageous embodiments are given in the dependent claims, in the further description as well as in the figures, wherein the described embodiments can, alone or in any combination of the respective embodiments, provide a feature of the present invention unless not clearly excluded.

An aspect of the invention relates to a method for operating a power electronic converter device for an electrical power conversion system.

The power electronic converter device comprises a converter circuit including an input side with input terminals, which may be DC terminals, and an output side with at least one AC output terminal, such as three AC output terminals. The converter circuit comprises a first and/or main converter with semiconductor devices, the first converter connected to the input terminals and providing at least one AC output (such as three AC outputs). The converter circuit furthermore comprises at least one second converter connected between an AC output of the first converter and the respective AC output terminal. The converter circuit may comprise a second converter for each output phase. The or each second converter comprises at least one floating cell or a series-connection of floating cells, wherein the or each floating cell comprises a DC intermediate circuit and semiconductor devices. The DC intermediate circuit may also be called DC link and/or may comprise at least one capacitor.

The power electronic converter device furthermore may comprise a controller, which is configured for performing the method.

According to the invention, the method comprises: switching the semiconductor devices of the floating cell at switching instants determined with optimized pulse patterns or carrier based pulse width modulation. Also the semiconductor devices of the first converter may be switched in this way. It has to be noted that everything described with respect to a second converter with one floating cell also may refer to a second converter with a series connection of floating cells.

According to the invention, the method further comprises: determining a (desired) fundamental voltage component for the floating cell, which fundamental voltage component depends on a difference between an actual voltage VC AF of the DC intermediate circuit of the floating cell and a reference value VC AF* for the voltage of the DC intermediate circuit. The desired voltage component is used for balancing the floating cell, its DC intermediate circuit and in particular the capacitor there. The (desired) fundamental voltage component may be a signal, which is generated in the controller, for example by a PI controller or a hysteresis controller, such as will be described below. From this (desired) fundamental voltage component, modified switching instants are determined, which, when applied to the semiconductor devices of the floating cell, result in a (real) fundamental voltage component in the actual voltage generated by the floating cell.

According to the invention, the method further comprises: generating the fundamental voltage component in the actual voltage of the DC intermediate circuit of the floating cell by modifying the switching instants, such that a voltage VC AF of the DC intermediate circuit is lying in a given reference voltage range, in particular for balancing the DC intermediate circuit of the floating cell. The (desired) fundamental voltage component is input into a further controller part, which modifies the switching instants determined with optimized pulse patterns and/or carrier bases pulse width modulation.

According to an embodiment of the invention, the fundamental voltage component is generated in the actual voltage of the floating cell, such that the respective voltage VC AF of the DC intermediate circuit is kept at a reverence value VC AF*. In particular, the fundamental voltage component is zero when the DC intermediate circuit, and in particular the capacitor, of the floating cell is balanced and/or is at its reference value.

According to an embodiment of the invention, the fundamental voltage component is generated by a PI controller, whose input is the difference between the actual voltage VC AF of the corresponding DC intermediate circuit and its reference value VC AF*. It is also possible that a hysteresis controller is used in such a way.

According to an embodiment of the invention, a variable gain of the PI controller is adjusted in dependence of a fundamental component of a phase current flowing through the floating cell. The proportional variable gain of the PI controller may be multiplied with the inverse of the amplitude of a fundamental load current î<NUM> L.

According to an embodiment of the invention, the fundamental voltage component has a phase angle relative to a fundamental component of a phase current flowing through the floating cell in a range of -<NUM>°. +<NUM>°, in particular, when charging of the cell is desired. When discharging is desired the angle is <NUM> to <NUM> degrees.

According to an embodiment of the invention, the fundamental voltage component is in phase with said fundamental component of the phase current, in particular, when charging of the cell is desired. When discharging is desired the angle is <NUM> degrees.

According to the invention, the method further comprises: switching the semiconductor devices of the first converter at switching instants determined with optimized pulse patterns or carrier based pulse width modulation; and generating and/or modifying a fundamental voltage component in a voltage, which is output by the first converter, by modifying the switching instants applied to the first converter, wherein the fundamental voltage component in the actual voltage, which is output by the first converter, is determined in dependence of the (desired) fundamental voltage component determined for the floating cell.

According to the invention, the fundamental voltage component of the voltage at the first converter is generated and/or modified, such that the fundamental component of the voltage at the output terminals is kept constant.

According to the invention, the fundamental voltage component generated by the floating cell is balanced and/or cancelled out by the fundamental voltage component generated by the first converter. In other words, their sum may be zero. In this way, the one or more floating cells may be balanced without changing an output of the overall system.

According to an embodiment of the invention, the switching instants for the floating cell are modified by adjusting switching angles of the optimized pulse patterns. An adjustment of the switching angles of the semiconductor devices of the floating cell may be based on a sign of the corresponding switching transition. An adjustment of the switching angles of the semiconductor devices of the floating cell may be based on appropriate gains related to the nominal switching angles of the optimized pulse patterns.

According to an embodiment of the invention, when the floating cell is switched with carrier based pulse width modulation, the switching instants are modified by adding a sinusoidal signal at the fundamental frequency to a reference of carrier based pulse width modulation.

According to an embodiment of the invention" when both the first converter and the at least one floating cell are switched with optimized pulse patterns, the optimized pulse patterns of the first converter and the at least one floating cell are selected such that the weighted total harmonic distortion of the sum of the voltages of the DC intermediate circuit and the output voltage of the first converter is minimized.

A further embodiment of the invention relates to a method for operating a converter device for an electrical power conversion system, the power electronic converter device comprising: (i) a converter circuit including an input side with input terminals, an output side with output terminals, a first converter with semiconductor devices and at least one second converter connected in series with the first converter, said second converter comprising a floating cell with a DC intermediate circuit and semiconductor devices or a series connection of a plurality of floating cells each with a DC intermediate circuit and semiconductor devices, and (ii) a control device for driving the semiconductor devices of at least one of the converters via pulse-like signals. According to several embodiments of the invention the control device drives the semiconductor devices of the at least one floating cell by use of optimized pulse patterns (OPPs) and/or carrier-based pulse width modulation (CB-PWM) signals such that a respective voltage of the DC intermediate circuit or the DC intermediate circuits is/are lying in a given reference voltage range. By means of the floating cells a DC voltage can be added to or subtracted from a DC voltage of the first converter with the help of the semiconductor devices to generate a sufficiently harmonics-free desired output voltage and current. Basic prerequisite for stable operation are relatively similar voltages of the individual floating cells or their intermediate circuits. In the following, the voltage of the intermediate circuit is also referred to as the voltage of the floating cell.

According to an embodiment of the invention, the control device drives the semiconductor devices such that the voltage(s) of the DC intermediate circuit(s) is/are kept at their reference value. This is preferably done by use of a balancing routine.

The pulse patterns of the two converters may be selected such that the - preferably weighted - total harmonic distortion (THD) of the sum of the voltages of the DC intermediate circuit(s) and the output voltage of the first converter is minimized.

According to an embodiment of the invention, each fundamental voltage component of the floating cells for the balancing has a phase angle relative to the fundamental component of the phase current in a range of - <NUM>°. +<NUM>° and is preferably in phase with said fundamental component of the phase current, in particular, when charging of the cell is required. For discharging an angle from <NUM>° to <NUM>° may be used, preferably <NUM>°.

According to an embodiment of the invention, the fundamental component for the balancing is generated by a PI controller unit and/or a hysteresis controller unit, whose input is the difference between the (filtered) actual voltage of the corresponding DC intermediate circuits and its reference.

The fundamental component of the voltage at the first converter may be modified such that the total fundamental component of the voltage at the output terminals is kept constant.

According to an embodiment of the invention, the converter device comprises:.

The embodiments mentioned in connection with the method for operating a power electronic converter device shall apply mutatis mutandis also to the corresponding power electronic converter device and vice versa.

According to an embodiment of the invention, the control device is arranged to drive the semiconductor devices such that the voltage(s) of the floating cell(s) is/are kept at their reference value. This is preferably done by use of a balancing routine.

The pulse patterns of the two converters may be selected such that the weighted total harmonic distortion (THD) of the sum of the voltages of the DC intermediate circuit(s) and the output voltage of the first converter is minimized.

According to an embodiment of the converter device according to the invention, for each floating cell a fundamental floating voltage component is in phase or <NUM> degrees out of phase with the corresponding phase current.

The power electronic-converter device, especially the controller of said converter device comprises a controller unit, especially a PI controller unit, wherein the fundamental component for the balancing is generated by said controller unit, whose input is the difference between the actual voltage of the corresponding floating cells and the reference voltage.

According to an embodiment of the converter device according to the invention, the fundamental component of the voltage at the first converter is modified such that the fundamental component of the voltage at the output terminals is kept constant.

A further aspect of the invention relates to a computer program product comprising computer-executable program code portions having program code instructions configured to execute the method as described above and below, when loaded into a computer based control device.

A further aspect of the invention relates to a computer-readable medium, in which such a computer program product is stored.

A further aspect of the invention relates to a power electronic converter device for an electrical power conversion system, the power electronic converter device comprising: a converter circuit including an input side with input terminals, an output side with at least one output terminal, a first converter with semiconductor devices connected to the input terminals and at least one second converter connected between an AC output of the first converter and the AC output terminal, said second converter comprising at least one floating cell with a DC intermediate circuit and semiconductor devices, and a control device for driving the semiconductor devices of the at least one floating cell and optionally of the first converter, wherein the control device is configured for performing the method as described above and below. Further features of the invention are apparent from the claims, the figures and the description of the figures. All the features and feature combinations mentioned above in the description as well as the features and feature combinations mentioned below in the description of the figure and/or shown in the figure alone are usable not only in the respectively specified combination, but also in other combinations or alone.

Now, the invention is explained in more detail based on a preferred embodiment as well as with reference to the attached drawings.

Individual features disclosed in the embodiments can constitute alone or in combination an aspect of the present invention. Features of the different embodiments can be carried over from one embodiment to another embodiment.

<FIG> shows a schematic diagram of a converter circuit <NUM>. The converter circuit <NUM> shows one-phase of a three-phase converter device, which comprises an input side <NUM> with input terminals <NUM>, an output side <NUM> with an output terminal <NUM>, a first converter <NUM> and a second converter <NUM> connected in series with the first converter <NUM>. The first converter <NUM> is a neutral-point clamped (NPC) converter or an active neutral-point clamped (ANPC) converter. It could be another type of three-level converter, a two level converter or a converter with more than three levels. The first (main) converter <NUM> comprises capacitive elements <NUM> (depicted as capacitors) and semiconductor devices <NUM>. The second converter <NUM> comprises a series connection of a plurality of floating cells <NUM>. These floating cells <NUM> function as active filters (AF) and are therefore also called "AF cells" or "H-bridge AF cells". Each floating cell <NUM> comprises two pairs of semiconductor devices <NUM> and a DC intermediate circuit <NUM> with a capacitive element <NUM> (depicted as capacitor) interconnected between the two pairs of semiconductor devices <NUM>. The capacitive element <NUM> has a capacitance CAF leading to a corresponding voltage VC AF at the DC intermediate circuit <NUM>.

The basic AF control objective is to compensate the three phase (<NUM>) (A)NPC output waveform harmonics while maintaining the average value of each AF cell capacitor voltage VC AF at its reference (AF balancing). The balancing control concept should also enable the use of the floating cells <NUM> as an add-on to existing converters. An additional control requirement is its suitability to modular concepts to ensure it can be easily adjusted to higher DC-link voltages and higher capacitor voltages as well as a higher number of floating cells <NUM>.

<FIG> shows a power electronic converter device <NUM> according to a first embodiment and a load <NUM> connected to the output side <NUM> of the converter device <NUM>. The converter device <NUM> comprises the converter circuit <NUM> and a control device <NUM> for driving the semiconductor devices <NUM>, <NUM> of at least one of the converters <NUM>, <NUM> via pulse-like signals. The control device <NUM> drives the semiconductor devices <NUM>, <NUM> by use of OPPs or CB-PWM such that a respective voltage VC AF of the DC intermediate circuits <NUM> is balanced , which means that it is lying in a given reference voltage range.

In the example the first converter <NUM> and the floating cells <NUM> are modulated by OPPs for a three-phase load <NUM>. The steps of the switching transitions of the <NUM>(A)NPC are higher than the ones of the AF switching transitions. The pulse patterns of the two converters <NUM>, <NUM> must be computed in such a way that the weighted total harmonic distortion (weighted THD) of the sum of the voltages <NUM>, <NUM> of the first converter <NUM> and the cell(s) <NUM> of the second converter <NUM> is minimized. Other objective functions can also be considered. Furthermore, the fundamental voltage component must be generated only by the first converter <NUM> (the <NUM>(A)NPC converter), the fundamental voltage component of the floating cell(s) <NUM> is zero since it can't provide active power. The resulting voltage <NUM> at the load <NUM> is depicted as a <NUM>-phase voltage course.

The OPP-modulated floating cells <NUM> need a balancing mechanism that ensures that the average voltage of the capacitive element <NUM> (functioning as an intermediate floating capacitor) remains constant and close to its reference. The present invention proposes two balancing approaches.

The approach is based on the injection of a fundamental AF voltage component preferably in phase with the load current, when charging is desired. For discharging the preferable angle is <NUM>°. The necessary AF fundamental component for the balancing is preferably generated by a PI controller unit <NUM> whose input is the difference between the (filtered) actual voltage of the AF capacitor VC AF and the average value reference VC AF* as shown in <FIG>. The proportional gain of the PI controller unit <NUM> can be multiplied with the inverse of the amplitude of the fundamental load current î<NUM> in order to keep the gain of the balancing loop constant and independent of the load current. For low currents the gain can be limited to certain values in order to avoid very big changes in the nominal switching angles. The output of the PI controller unit <NUM> gives the amplitude of the desired AF fundamental component v̂<NUM> for the corresponding floating cell <NUM>. Each phase should have one such controller and the control of the AF capacitor voltage in each phase is independent of the other phases.

Besides modifying the AF fundamental voltage component, the <NUM>(A)NPC fundamental component must be modified accordingly in order to keep the fundamental component of the voltage at the load terminals the same. The calculation of the desired fundamental <NUM>(A)NPC phase voltage component is carried out with the help of the phasors of the fundamental voltage components of the <NUM>(A)NPC and the AF as illustrated in <FIG>. With the help of the phasor diagram the desired <NUM>(A)NPC phasor V<NUM><NUM>L can be calculated from the fundamental component of the nominal OPP
V<NUM> <NUM>Lnom for a given AF fundamental component phasor V<NUM> AF: <MAT>.

From the above equation we can calculate the amplitude |V<NUM><NUM>L| and phase θ of the desired <NUM>(A)NPC fundamental component. From the former we can calculate the necessary change in the amplitude of the fundamental <NUM>(A)NPC voltage <MAT>.

The next sections describe how the nominal switching angles are modified in order to generate the necessary <NUM>(A)NPC and AF fundamental components in each phase.

By appropriately modifying the switching angles of the original <NUM>(A)NPC pulse pattern over <NUM>π, αNPC i, where the index i refers to the ith switching transition ΔuNPC i, the desired <NUM>(A)NPC fundamental component can be generated. Different approaches can be used for this modification. In this specific implementation it is done in two steps, one to get the desired amplitude and one to get the desired phase:.

<NUM>) In a first step the amplitude of the fundamental component is modified via addition of an angle ΔαNPCi to each <NUM>(A)NPC switching angle: <MAT>
where <MAT>.

The total dc-link voltage of the first converter (especially <NUM>(A)NPC converter) <NUM> is 2Vdc, which is also visible in <FIG>. The sign of k depends on the half period of the fundamental component of the nominal pulse pattern the switching angle lies in. This is exemplified in <FIG>. The gNPC · ΔmNPC part of equation (<NUM>) is independent of the actual nominal switching angle, which means that the absolute value of the change is the same for all switching angles, only the sign is switching angle dependent. The gain gNPC defines how big this change should be in order to achieve the desired change in the modulation index. When we have only one switching angle within a quarter wave period and the OPP has both half wave and quarter wave symmetry the necessary gain can be calculated analytically <MAT>.

For higher number of switching angles the gain gNPC is calculated as a function of the modulation index and stored in the OPP. It is calculated by changing the nominal <NUM>(A)NPC switching angles by ΔαNPCi = k · sign(ΔuNPCi) · ΔαNPC and calculating the change ΔmNPC that it causes to the modulation index of the <NUM>(A)NPC: <MAT>.

<NUM>) Subsequently, the previously calculated angle Θ is added to each <NUM>(A)NPC nominal switching angle in order to obtain the desired phase of the <NUM>(A)NPC fundamental voltage. The modified <NUM>(A)NPC switching angles will then be: <MAT>.

For a three phase load with a phase difference of ± <NUM>π/<NUM> for phases b and c the modified <NUM>(A)NPC switching angles in each phase can be expressed as: <MAT>.

The desired AF modulation index can be achieved via small modifications of the original AF switching angles (for which the AF modulation index is zero) of the corresponding phase. Before these modifications are done, the angle defined previously is added to the nominal switching angles of the AF in order to avoid mismatches between the pulse patterns of the first and second converter <NUM>, <NUM> (<NUM>(A)NPC and the AF): <MAT>
where αAFi nom is the ith nominal AF switching angle.

Different approaches can be the used for the injection of a fundamental component, for example a modification of the switching angles based on the following formula is preferable: <MAT>
where ΔuAFi is the switching transition corresponding to the ith switching angle αAFi , and ϕAF is the desired phase of the AF fundamental component. Preferably we set ϕAF equal to the phase difference between the fundamental components of the load voltage and the load current, which is denoted as ϕL in <FIG>. This way the injected AF voltage component is in phase with the load current and we can charge or discharge the AF capacitor more effectively.

For a desired AF modulation index mAF one must select the quantity ΔαAFmax accordingly. This is done by multiplying mAF with a gain, which is OPP-specific and approximately constant for relatively small changes of the nominal switching angles: <MAT>.

It can be precomputed for each pulse pattern as a function of ϕAF and then stored with each OPP of the AF. Often, the influence of ϕAF on the ratio ΔαAFmax / mAF is negligible and it suffices to store one ratio for each AF pulse pattern (that corresponds to a specific modulation index of the main converter). If the influence of ϕAF is not negligible, the ratio ΔαAFmax / mAF as a function of ϕAF must be computed stored.

The calculated angle difference ΔαAFi is added to α'AFi nom in order to calculate the modified AF switching angle which is going to be used for the AF modulation <MAT>.

By switching at the modified switching angles we generate the necessary AF fundamental component, which has both the desired amplitude v̂<NUM> AF and phase ϕAF.

For a three phase load with a phase difference of ± <NUM>π/<NUM> for phases b and c the AF switching angles modifications in each phase can be expressed as: <MAT>.

A simplified diagram of a balancing control unit <NUM> and an OPP modulator unit <NUM> is shown in <FIG>. The control unit <NUM> should compensate only the average capacitor voltage and not the voltage ripple. This can be done by either filtering the measured capacitor voltage fed to the PI control unit <NUM> with a moving average filter over a suitably selected time window (e.g. half the fundamental period) or by appropriately selecting the bandwidth of the PI control unit <NUM>. Module <NUM> represents the calculation of the necessary fundamental components of the first converter <NUM>. When calculating the second converter <NUM> floating cell <NUM> switching angle changes (represented by module <NUM>) and first converter <NUM> switching angle changes (represented by module <NUM>) some restrictions have to be considered, which are not described in detail in this document. For example, the modified switching angle can't be higher than the next nominal switching angle. Constraints in the relation between the switching angles of different phases can be also considered if necessary. The calculated first converter switching angle changes are provided to a modulator module <NUM> for the first converter <NUM> and the calculated second converter switching angle changes are provided to a modulator module <NUM> for the second converter <NUM>. Both modulator modules <NUM>, <NUM> are OPP modulator modules in the example of <FIG>.

In the above approach different fundamental components are considered for each phase, since the voltage of the capacitors of the floating cells can be a bit different in each phase. In a variation of the balancing approach the voltages of the capacitors of the floating cells of the different phases are brought to the same value with the help of a common mode (CM) component considered in the modulation of the floating cells. The CM component is preferably generated either via appropriate modification of the nominal switching angles of the floating cells in all three phases or by using the three-phase redundant switching vectors of the floating cells. In the former case an additional term Δαi,CM is added to the AF switching angles, which is calculated by ΔαAF, i = FmaxCM · sign(ΔuAFi)·.

As previously for the fundamental component, for a desired CM component mAF, CM one must select the quantity ΔαAFmax CM accordingly. This is done by multiplying mAF, CM with a gain, which is OPP-specific and approximately constant for relatively small changes of the nominal switching angles:
<MAT>.

The term calculated by (<NUM>) is added to the term considered in (<NUM>), so that the total modification of the switching angles of the floating cells is given by <MAT>.

If redundant vectors are used alternative combinations of the switching states are considered that generate the same differential voltage but different CM voltage. For example instead of the combination [uAFi,a,uAFi,b, uAFi,c] = [<NUM>, <NUM>, <NUM>] one can select [uAFi,a, uAFi,b, uAFi,c ] = [<NUM>, <NUM>, -<NUM>]. The difference between two phases remains the same, but the sum of the three phases is different. The selection of a redundant vector or not is based on the prediction of the evolution of the capacitor voltages after one sampling interval in the three phases using the capacitor transfer function and the measured phase current.

However, the use of redundant vectors will increase the switching frequency of the semiconductors of the floating cells. The switching frequency can be optimized by selecting a suitably long horizon (more than one sampling interval) and include penalization of the number of the necessary switching actions that take place when selecting redundant vectors which will bring the three capacitor voltages close to each other in the considered horizon. The (equal) voltage of the capacitors of the three phases is then brought to the desired reference value by the switching angle modifications described in (<NUM>)-(<NUM>). Since the voltages in each phase are considered equal the necessary fundamental components for the main converter and the floating cells (shown by phasors in <FIG>) are the same for all three phases. Only a phase displacement of -2π/<NUM> and +2π/<NUM> compared to phase a will be present in phases b and c respectively.

A special case that must be carefully treated is when one or more switching angles of the main converter are the same with one or more switching angles of the floating cells. Then only the remaining AF switching angles (which are not the same with any switching angles of the main converter) are used for the generation of the fundamental component of the floating cells. Furthermore, in such a case the modification of the switching angles of the main converter generates a fundamental component also in the floating cells. This must be compensated with the afore mentioned remaining switching angles of the floating cells. The AF fundamental voltage component generated by the modification of the switching angles of the main converter is given by <MAT>
where rAF is the ratio between the voltage of the floating cell and half the dc-link voltage of the main converter. The compensation term for the remaining switching angles of the floating cells is then calculated by: <MAT>.

The same principle applies when the switching angles of the main converter are modified to balance the neutral point, e.g. when the main converter is a <NUM>(A)NPC. The CM component that will appear in the floating cells due to some simultaneous switchings with the main converter must be compensated by the remaining switching angles of the floating cells.

If CB-PWM is used for the H-bridge cell(s) <NUM>, the previously discussed modifications are applied only to the switching angles of the first converter <NUM> (modules <NUM>, <NUM>, <NUM>). The necessary modifications of the AF switching instants are made by simply adding a suitable sinusoidal signal (generated by function generator <NUM>) at the fundamental frequency to the CB-PWM reference of the AF (provided to corresponding modulator module <NUM>). The amplitude of this signal is equal to v̂<NUM> AF divided by the AF voltage and its phase preferably equal to the phase of the load current ϕL as shown in <FIG>. In this case the nominal switching instants of the AF are computed by comparing a reference signal equal to the difference between the <NUM>(A)NPC reference signal and the <NUM>(A)NPC output switching states with the carrier signals. The above mentioned "nominal" reference signal is in essence equal to the sum of the <NUM>(A)NPC output voltage harmonics.

If CB-PWM is used for the first converter <NUM>, the previously discussed modifications are applied only to the switching angles of the AF. The necessary modifications of the <NUM>(A)NPC switching instants are made by suitably modifying its CB-PWM reference as shown in <FIG>. The amplitude of the sinusoidal reference is equal to mNPC nom+ΔmNPC and its phase equal to θ. CM components can also be added to this sinusoidal reference if it is desirable. The proposed balancing schemes facilitate the balancing of the AF cell capacitor voltages when the AF cells and /or the main converter are modulated by OPPs. With OPP modulation we can achieve, in many cases, an improved output voltage quality compared to CB-PWM or other modulation approaches.

The control algorithm can be implemented on any computational hardware including DSPs, FPGAs, microcontrollers, CPUs, GPUs, multicore platforms, and combinations thereof.

In the invention description the first converter <NUM> is a <NUM>(A)NPC converter, but the same methods can be applied to other types of three-level converters, including neutral point piloted <NUM> converter. The invention can also be applied to main converters with two levels or to main converters with more than three levels.

Claim 1:
A method for operating a power electronic converter device (<NUM>) for an electrical power conversion system, the power electronic converter device (<NUM>) comprising a converter circuit (<NUM>) including an input side (<NUM>) with input terminals (<NUM>), an output side (<NUM>) with at least one AC output terminal (<NUM>), a first converter (<NUM>) with semiconductor devices (<NUM>) connected to the input terminals (<NUM>) and at least one second converter (<NUM>) connected between an AC output of the first converter (<NUM>) and the AC output terminal, said second converter (<NUM>) comprising at least one floating cell (<NUM>) with a DC intermediate circuit (<NUM>) and semiconductor devices (<NUM>);
the method comprising:
switching the semiconductor devices (<NUM>) of the floating cell (<NUM>) at switching instants determined with optimized pulse patterns or carrier based pulse width modulation;
determining a fundamental voltage component for the floating cell, which fundamental voltage component depends on a difference between an actual voltage VC AF of the DC intermediate circuit of the floating cell and a reference value VC AF* for the voltage of the DC intermediate circuit;
generating the fundamental voltage component in the actual voltage of the floating cell by modifying the switching instants, such that a voltage VC AF of the DC intermediate circuit (<NUM>) is lying in a given reference voltage range;
switching the semiconductor devices (<NUM>) of the first converter (<NUM>) at switching instants determined with optimized pulse patterns or carrier based pulse width modulation;
generating a fundamental voltage component in a voltage output by the first converter by modifying the switching instants applied to the first converter, wherein the fundamental voltage component in the actual voltage output by the first converter is determined in dependence of the fundamental voltage component determined for the floating cell;
wherein the fundamental voltage component of the voltage at the first converter (<NUM>) is modified, such that the fundamental component of the voltage at the output terminals (<NUM>) is kept constant; and
wherein the fundamental voltage component generated by the floating cell is cancelled out by the fundamental voltage component generated by the first converter.