Patent Description:
Technology advances, capacity demands, and higher frequency operation have led to a rise in the number of base station receive antennas and radio-near processing. Receiver antenna arrays are partitioned into subarrays, each with their own independent and dedicated processing circuitry.

<CIT> discloses a method for decoding, comprising decoding signals iteratively, mutually exchanging extrinsic information, calculating APP LLRS for both systematic and parity bits and making a hard decision after a plurality of iterations is completed based on accumulated soft information.

<CIT> discloses methods for reducing the impact of cross talk interference in multi-carrier data transmission systems.

Aspects of the invention are set out in the independent claims appended hereto. In various embodiments described herein, processing architecture and algorithms for a receiver with multiple subarrays is described with parts of the processing occurring at each subarray, and another part occurring downstream fed by the subarrays. A "Zigzag" scheme, which exchanges messages between decoders fed by different subarray signals results in overall receiver performance that approaches that of a full array with unrestricted processing.

Constrained processing per subarray can result in performance loss compared to unconstrained processing with the full array, which may prevent the array investment being fully exploited.

Various embodiments described herein propose a process for subarray cooperation via channel decoding. The receiver architecture limits the information available for processing in each subarray. In some embodiments, a "zigzag" scheme is provided which exchanges messages between decoders fed by different subarray signals. In some examples, the overall receiver performance using the zigzag scheme approaches that of a full array with unrestricted processing. The subarrays produce outcomes including appropriate information, and those outcomes are then further processed together downstream.

Some embodiments do not violate the constrained architecture, in the sense that some embodiments do not require any direct communication among subarrays or any feedback to the subarrays. The zigzag scheme operates downstream from the subarray processing, with its message exchange between decoders being fed by signals from different subarrays. This results in good performance within the constraints of the architecture. The constrained processing structure is shown in <FIG>. In this example, two subarrays (subarray A 210a and subarray B 210b) each receive a signal (rA and rB respectively). Each of subarrays 210a, 210b are associated with upstream processing circuitry (upstream processing A 220a and upstream processing B 220b respectively), which process the received signal into soft values 222a-b (referred to as <MAT> and <MAT> in <FIG>). A downstream processing circuitry <NUM> determines a decoded received signal <NUM> based on the soft values 222a-b using a zigzag decoding scheme.

<FIG> is a block diagram illustrating elements of a communication device UE <NUM> (also referred to as a mobile terminal, a mobile communication terminal, a wireless device, a wireless communication device, a wireless terminal, mobile device, a wireless communication terminal, user equipment, UE, a user equipment node/terminal/device, etc.) configured to provide wireless communication according to embodiments of inventive concepts. As shown, communication device UE may include an antenna <NUM>, and transceiver circuitry <NUM> including a transmitter and a receiver configured to provide uplink and downlink radio communications with a base station(s), also referred to as a RAN node) of a radio access network. Communication device UE may also include processing circuitry <NUM> coupled to the transceiver circuitry, and memory circuitry <NUM> (also referred to as memory) coupled to the processing circuitry. The memory circuitry <NUM> may include computer readable program code that when executed by the processing circuitry <NUM> causes the processing circuitry to perform operations according to embodiments disclosed herein. According to other embodiments, processing circuitry <NUM> may be defined to include memory so that separate memory circuitry is not required. Communication device UE may also include an interface (such as a user interface) coupled with processing circuitry <NUM>, and/or communication device UE may be incorporated in a vehicle.

As discussed herein, operations of communication device UE may be performed by processing circuitry <NUM> and/or transceiver circuitry <NUM>. For example, processing circuitry <NUM> may control transceiver circuitry <NUM> to transmit communications through transceiver circuitry <NUM> over a radio interface to a radio access network node (also referred to as a base station) and/or to receive communications through transceiver circuitry <NUM> from a RAN node over a radio interface. Moreover, modules may be stored in memory circuitry <NUM>, and these modules may provide instructions so that when instructions of a module are executed by processing circuitry <NUM>, processing circuitry <NUM> performs respective operations.

<FIG> is a block diagram illustrating elements of a radio access network RAN node <NUM> (also referred to as a network node, base station, eNodeB/eNB (Evolved Node B), gNodeB/gNB, etc.) of a Radio Access Network (RAN) configured to provide cellular communication according to embodiments of inventive concepts. As shown, the RAN node may include transceiver circuitry <NUM> (also referred to as a transceiver) including a transmitter and a receiver configured to provide uplink and downlink radio communications with mobile terminals. The RAN node may include network interface circuitry <NUM> (also referred to as a network interface) configured to provide communications with other nodes (e.g., with other base stations) of the RAN and/or core network CN. The network node may also include processing circuitry <NUM> (also referred to as a processor, e.g., corresponding to processing circuitry <NUM>) coupled to the transceiver circuitry, and memory circuitry <NUM> (also referred to as memory) coupled to the processing circuitry. The memory circuitry <NUM> may include computer readable program code that when executed by the processing circuitry <NUM> causes the processing circuitry to perform operations according to embodiments disclosed herein. According to other embodiments, processing circuitry <NUM> may be defined to include memory so that a separate memory circuitry is not required.

As discussed herein, operations of the RAN node may be performed by processing circuitry <NUM>, network interface <NUM>, and/or transceiver <NUM>. For example, processing circuitry <NUM> may control transceiver <NUM> to transmit downlink communications through transceiver <NUM> over a radio interface to one or more mobile terminals UEs and/or to receive uplink communications through transceiver <NUM> from one or more mobile terminals UEs over a radio interface. Similarly, processing circuitry <NUM> may control network interface <NUM> to transmit communications through network interface <NUM> to one or more other network nodes and/or to receive communications through network interface from one or more other network nodes. Moreover, modules may be stored in memory <NUM>, and these modules may provide instructions so that when instructions of a module are executed by processing circuitry <NUM>, processing circuitry <NUM> performs respective operations.

According to some other embodiments, a network node may be implemented as a core network CN node without a wireless transceiver. In such embodiments, transmission to a wireless communication device UE may be initiated by the network node so that transmission to the wireless communication device UE is provided through a network node including a transceiver (e.g., through a base station or RAN node). According to embodiments where the network node is a RAN node including a transceiver, initiating transmission may include transmitting through the transceiver.

<FIG> is a block diagram illustrating elements of a core network CN node <NUM> (e.g., an Session Management Function ("SMF") node, an Access and Mobility Management Function ("AMF") node, etc.) of a communication network configured to provide cellular communication according to embodiments of inventive concepts. As shown, the CN node may include network interface circuitry <NUM> (also referred to as a network interface) configured to provide communications with other nodes of the core network and/or the radio access network RAN. The CN node may also include a processing circuitry <NUM> (also referred to as a processor) coupled to the network interface circuitry, and memory circuitry <NUM> (also referred to as memory) coupled to the processing circuitry. The memory circuitry <NUM> may include computer readable program code that when executed by the processing circuitry <NUM> causes the processing circuitry to perform operations according to embodiments disclosed herein. According to other embodiments, processing circuitry <NUM> may be defined to include memory so that a separate memory circuitry is not required.

As discussed herein, operations of the CN node may be performed by processing circuitry <NUM> and/or network interface circuitry <NUM>. For example, processing circuitry <NUM> may control network interface circuitry <NUM> to transmit communications through network interface circuitry <NUM> to one or more other network nodes and/or to receive communications through network interface circuitry from one or more other network nodes. Moreover, modules may be stored in memory <NUM>, and these modules may provide instructions so that when instructions of a module are executed by processing circuitry <NUM>, processing circuitry <NUM> performs respective operations.

<FIG> is a block diagram illustrating elements of another radio access network, RAN, node <NUM> (also referred to as a network node, base station, eNodeB/eNB, gNodeB/gNB, etc.) of a Radio Access Network (RAN) configured to provide cellular communication according to embodiments of inventive concepts. As shown, the RAN node may include transceiver circuitry <NUM> (also referred to as a transceiver) including a transmitter and a receiver configured to provide uplink and downlink radio communications with mobile terminals. Here, transceiver <NUM> is depicted as including a pair up receivers <NUM>, <NUM> each with their own upstream processing circuitry <NUM>, <NUM> (also referred to as upstream processors) and corresponding memory circuitry <NUM>, <NUM> (also referred to as memory). The memory circuitry <NUM>, <NUM> may include computer readable program code that when executed by the upstream processing circuitry <NUM>, <NUM> causes the upstream processing circuitry to perform operations according to embodiments disclosed herein. For example, upstream processing circuitry <NUM>, <NUM> may transform receive signal domain representations of signals received via antenna subarrays 1030a, 1030b into transmit domain representations. According to other embodiments, upstream processing circuitry <NUM>, <NUM> may be defined to include memory so that a separate memory circuitry is not required. The RAN node <NUM> may include or be coupled to an array of antenna that are made up of one or more antenna subarrays. Here, receiver <NUM> is associated with antenna subarray 1030a and receiver <NUM> is associated with antenna subarray 1030b.

The RAN node may include network interface circuitry <NUM> (also referred to as a network interface) configured to provide communications with other nodes (e.g., with other base stations) of the RAN and/or core network CN. The network node may also include downstream processing circuitry <NUM> (also referred to as a processor, e.g., corresponding to processing circuitry <NUM>) coupled to the transceiver circuitry, and memory circuitry <NUM> (also referred to as memory) coupled to the processing circuitry. The memory circuitry <NUM> may include computer readable program code that when executed by the downstream processing circuitry <NUM> causes the downstream processing circuitry <NUM> to perform operations according to embodiments disclosed herein. For example, downstream processing circuitry may combine outputs from receivers <NUM>, <NUM>. According to other embodiments, downstream processing circuitry <NUM> may be defined to include memory so that a separate memory circuitry is not required. Modules may be stored in memory <NUM>, and these modules may provide instructions so that when instructions of a module are executed by processing circuitry <NUM>, <NUM>, <NUM>, processing circuitry <NUM>, <NUM>, <NUM>, performs respective operations. In additional or alternative embodiments, another network node (e.g., a UE or a CN node) may have multiple receivers similar to receiver <NUM>, <NUM> that are each associated with an antenna subarray and a downstream processor for performing similar operations as RAN node <NUM>.

In some embodiments, a MIMO system is provided in which the transmitter sends M streams and the receiver has N antennas. In some examples, linear receiver techniques are used which assume that N ≥ M. Furthermore, since the antennas are split into subsets, the size of each subset ≥ M. The following disclosure describes embodiments in which the array is split into two subsets of equal size (N/<NUM>) and that N/<NUM> ≥ M. However, the subarrays may be of inequal size and the array may be divided into any number of subarrays.

In some embodiments, a system equation for describing a vector, r, of received symbols is given by <MAT> where s is a vector of M symbols from a modulation constellation (e.g., QAM) and H is a channel matrix of size N×M. In some examples, the channels have an average energy of one. The total noise, w, can include an interference signal plus a white noise signal, <MAT>.

The total noise covariance of size N×N can be written as <MAT> where Ei and Ev are the interference and white noise energy, respectively. Channel parameters can be estimated from the received signal, aided by pilots symbols embedded in transmitted signals.

A maximum likelihood (ML) demodulator can search for a candidate vector ŝ for s that minimizes the metric: <MAT>.

This may require a full search, which can become infeasible for a large constellation or a large number of streams.

Incorporating the interference into the metric enables the receiver to suppress interference. This can greatly enhance performance in scenarios with large interference with high strong color (as reflected in large values of non-diagonal elements in Rw). In some embodiments, another version of this demodulator ignores interference by approximating Rw as a diagonal matrix. Then fewer parameters need to be estimated and also the complexity of matrix operations such as inverses would be reduced.

In some embodiments, the ML demodulator is implemented as a sphere decoder (SD). In additional or alternative embodiments, any demodulator capable of producing modem soft values may be used. A SD can search among the candidate transmit signals s̃ within a progressively shrinking sphere centered at an initial guess s̃. Overall, the SD can be computationally efficient while remaining equivalent to the ML demodulator. Various shortcuts can further speed up the SD, with corresponding performance penalties.

A receive signal domain representation can be transformed to a transmit domain representation using a left inverse F of H, of size M×N, given by: <MAT>.

The received signal, r, can be transformed into <MAT> where s̃ is the ML estimate of s, if s were a Gaussian vector. Since s belongs to a discrete set, s̃ can be an initial guess for s. The candidates ŝ for the transmitted symbol vector can be searched in the neighborhood of of s̃ for the final answer. s̃ can be written as <MAT> where x = Fw with covariance: <MAT> of size M×M, which can be written as <MAT>.

In some embodiments, given s̃, the SD finds the best candidate using a modified metric given by: <MAT>.

The SD can exploit the Hermitian (complex symmetric) property of the covariance matrix. It can perform a Cholesky decomposition, which computes a triangular "root" matrix K such that: <MAT>.

The triangular property can enable the solution of linear systems by back substitution. It is also an ingredient in facilitating the restriction of the search to a sphere. Finding the best candidate using n(ŝ) under the sphere restriction can be referred to as the sphere restricted search.

In some embodiments, in addition to the modulation symbols, a demapper can use the metrics of the SD to produce hard and soft values for the modem bits that map into the modulation symbols. The hard or soft bit values can be fed to the channel decoder.

The baseline demodulation process is shown in <FIG> that includes parameter estimation <NUM>, the parameter transform <NUM> to obtain F and Rx, the signal transform <NUM> from the receive domain to the transmit domain, and a search unit <NUM>, which outputs a decoded received signal <NUM>.

In some embodiments, the receive antennas can be split into two subsets, A and B, of equal size N/<NUM>, which represent two subarrays. Without loss of generality, the subsets can be assumed to be contiguous in the vector notation. The received signal and the channel can be split accordingly: <MAT> <MAT> <MAT>.

The individual subarray receivers observe their own partial received signals: <MAT> <MAT>.

The total covariance can be rewritten as <MAT> where RwA and RwB are the separate covariances of wA and wB respectively, and QwAB is the cross covariance of wA and wB.

Subarray receivers for A and B following the same approach as before, with a transform to the signal domain. That is, A observes rA and produces <MAT> where the previous notation has been modified to refer to subarray A. The covariance of xA can be written as <MAT>.

<FIG> illustrates the demodulator structure of subarray A. The signal, rA, received by subarray A can be input to a parameter estimation module <NUM> and a signal transform module <NUM>. The parameter estimation module <NUM> can output HA and RwA to a parameter transform module <NUM>, which can output FA to the signal transform module <NUM> and RxA to the search unit <NUM>. The signal transform module <NUM> can then output s̃A to the search unit <NUM>. The search unit <NUM> can search (e.g., sphere restricted search) for the best candidate around s̃A with the appropriate parameters. The output of the search unit <NUM> includes modulation symbols as well as modem bit soft values denoted <MAT> to be fed to a first downstream decoder (e.g., Decoder A 640a of <FIG>) of the downstream processing circuitry.

Similarly, B observes rB and goes through the same steps to produce <MAT> using the matrices FB and RxB (just replacing subscript A with B). The structure of the subarray processing is shown in <FIG> for subarray B. The signal, rB, received by subarray B can be input to a parameter estimation module <NUM> and a signal transform module <NUM>. The parameter estimation module <NUM> can output HB and RwB to a parameter transform module <NUM>, which can output FB to the signal transform module <NUM> and RxB to the search unit <NUM>. The signal transform module <NUM> can then output s̃B to the search unit <NUM>. The search unit <NUM> can search (e.g., sphere restricted search) around s̃B with the appropriate parameters. The output of the search unit <NUM> includes modulation symbols as well as modem bit soft values denoted <MAT> to be fed to a second downstream decoder (e.g., Decoder B 640b of <FIG>) of the downstream processing circuitry.

The performance of the individual subarray demodulators will be limited by the constraints, since each has only access to its own subarray signal. Various embodiments herein describe how to use feedback from the decoder in downstream processing. <FIG> illustrates an example in which demodulators 510a, 510b of subarrays A and B provide signals to demappers 520a, 520b respectively, which output modem soft values. The modem soft values from the demappers 520a, 520b of are fed to separate decoders 540a, 540b, and there is information exchange between the decoders.

In some embodiments, the information exchange between decoders in downstream processing circuitry is considered a "Zigzag" structure, where in each stage, Decoder A operates first, then Decoder B. <FIG> illustrates stage i of a zigzag processing between two decoders 640a, 640b of two upstream-processed signals from two independent subarrays.

For Decoder A 640a, <MAT> represents its output soft values from stage i - <NUM>, and <MAT> represents the message from Decoder B 640b at Stage i - <NUM>. The input to Decoder A 640a is <MAT>.

The output soft values are represented by <MAT>. The message to Decoder B 640b is given by <MAT>.

For Decoder B 640b, <MAT> represents its output soft values from stage i - <NUM>, and the input is <MAT>.

The output soft values are represented by <MAT>. The message to Decoder A 640a at Stage i + <NUM> is given by <MAT>.

The Zigzag scheme is initialized at stage <NUM> with <MAT> and <MAT> set to the modem bit soft values from their respective SD. In addition, the message <MAT> from Decoder B 640b is set to <NUM>.

In some embodiments, the number of stages v of the Zigzag scheme can be fixed to achieve a desired tradeoff of complexity and performance, e.g. v = <NUM>. In the last stage, <MAT> can be considered to be the output of the Zigzag scheme and <MAT> may not be computed since there is no upcoming stage v + <NUM>.

In additional or alternative embodiments, an alternative to a fixed number of stages is used to stop the Zigzag scheme based on the outcome. In one example if the encoding scheme includes a parity check code, e.g. a CRC, then the Zigzag scheme stops if in some stage i the hard values based on <MAT> out of Decoder B satisfy the parity check. The process can be stopped and v can be set to i. In additional or alternative examples, the Zigzag scheme can be stopped based on whether the outcome stops changing from stage to stage. In particular, if <MAT> out of Decoder B is very close to <MAT> from the previous stage. Then the process can be stopped and v set to i.

The Zigzag scheme improves performance by exchanging messages between decoders. The rationale for the subtraction of <MAT> at the output of Decoder A 640a is to match its addition at the input and to prevent accumulation over multiple stages (similarly for the subtraction of <MAT>).

In some embodiments, the soft values <MAT> and <MAT> are jointly processed downstream in a decoding scheme.

Various embodiments herein describe how to use feedback from the decoder in downstream processing. From the example in <FIG>, the modem soft values from the demappers 520a, 520b of subarrays A and B are fed to separate decoders 540a, 540b, and there is information exchange between the decoders, as shown in <FIG>. The Zigzag scheme assumes that the component decoders accept and produce modem bit soft values. Most modern channel codes have decoders capable of accepting modem bit soft values as input. This includes convolutional codes, turbo codes, LDPC codes, polar codes etc. Those decoders produce modem bit soft values during their normal internal process, or can produce them as a byproduct with some further computations.

Operations of a network node will now be discussed with reference to the flow charts of <FIG> according to some embodiments of inventive concepts. <FIG> will be described below as being performed by RAN node <NUM> (implemented using the structure of the block diagram of <FIG>). For example, modules may be stored in memory <NUM> of <FIG>, and these modules may provide instructions so that when the instructions of a module are executed by respective RAN node processing circuitry <NUM>, processing circuitry <NUM> performs respective operations of the flow charts. However, the at least a portion of the operations may be performed by any downstream processing circuitry, downstream receiver, or network node.

<FIG> illustrates examples of operations performed by a RAN node <NUM> in accordance with some embodiments.

At block <NUM>, first upstream processing circuitry <NUM> receives, via antenna subarray 1030a, a first version of an original signal. In some embodiments, the first version of the original signal is a first receive signal domain representation of the original signal.

At block <NUM>, first upstream processing circuitry <NUM> determines a first upstream-processed signal based on the first version of the original signal. In some embodiments, the first upstream-processed signal is a transmit domain representation of a first receive signal domain version of the original signal received at a first receiver <NUM> in the network node <NUM>. In additional or alternative embodiments, determining the first processed signal includes transforming the first receive signal domain representation of the original signal to a first transmit domain representation of the original signal.

At block <NUM>, second upstream processing circuitry <NUM> receives, via antenna subarray 1030b, a second version of the original signal. In some embodiments, the second version of the original signal is a second receive signal domain representation of the original signal.

At block <NUM>, second upstream processing circuitry <NUM> determines a second upstream-processed signal based on the second version of the original signal. In some embodiments, the second upstream-processed signal is a transmit domain representation of a second receive signal domain version of the original signal received at a second receiver <NUM> in the network node <NUM>. In additional or alternative embodiments, determining the second processed signal includes transforming a second receive signal domain representation of the original signal to a second transmit domain representation of the original signal.

At block <NUM>, first decoder 1040a, receives the first upstream-processed signal. In some embodiments, receiving the first upstream-processed signal includes receiving the first upstream-processed signal from the first upstream processing circuitry <NUM>, which is part of a first receiver <NUM> of the network node <NUM>. In additional or alternative embodiments, receiving the first upstream-processed signal includes receiving the first upstream-processed signal from a remote receiver in another network node.

At block <NUM>, second decoder 1040b, receives the second upstream-processed signal. In some embodiments, receiving the second upstream-processed signal includes receiving the second upstream-processed signal from the second upstream processing circuitry <NUM>, which is part of a second receiver <NUM> of the network node <NUM>. In additional or alternative embodiments, receiving the second upstream-processed signal includes receiving the second upstream-processed signal from a remote receiver in another network node.

At block <NUM>, first decoder 1040a determines a first downstream-processed signal based on the first upstream-processed signal. In some embodiments, the first decoder is a maximum likelihood process decoder. Determining the first downstream-processed signal can include performing, by the first decoder, a maximum likelihood process on the first upstream-processed signal.

At block <NUM>, first decoder 1040a outputs the first downstream-processed signal. At block <NUM>, second decoder 1040b determines a second downstream-processed signal based on the second upstream-processed signal and the first downstream-processed signal. Determining the second downstream-processed signal can include decoding, by the second decoder, an input based on the second upstream-processed signal and the first downstream-processed signal. At block <NUM>, second decoder 1040b outputs the second downstream-processed signal.

At block <NUM>, first decoder 1040a determines a first revised downstream-processed signal based on the first downstream-processed signal and the second downstream-processed signal. At block <NUM>, first decoder 1040a outputs the first revised downstream-processed signal.

At block <NUM>, downstream processing circuitry <NUM> determines a decoded received signal based on outputs from the first decoder and the second decoder. In some embodiments, determining the decoded received signal based on outputs from the first decoder and the second decoder includes iteratively determining the decoded received signal by responsive to a change in an output of the second decoder, outputting, by the first decoder, a revised first downstream-processed signal based on the output of the first decoder and the output of the second decoder; and responsive to a change in an output of the second decoder, outputting, by the second decoder, a revised second downstream-processed signal based on the output of the second decoder and the output of the first decoder.

In some embodiments, the communication network is a new radio, NR, network. Various operations of <FIG> may be optional with respect to some embodiments of network nodes and related methods.

Claim 1:
A method of operating a network node of a communication network, the method comprising:
receiving (<NUM>), by a first decoder of the network node, a first upstream-processed signal associated with an original signal;
receiving (<NUM>), by a second decoder of the network node, a second upstream-processed signal, associated with the original signal;
determining (<NUM>), by the first decoder of the network node, a first downstream-processed signal based on the first upstream-processed signal;
responsive to determining the first downstream-processed signal, outputting (<NUM>), by the first decoder, the first downstream-processed signal;
responsive to the first decoder outputting the first downstream-processed signal, determining (<NUM>), by the second decoder of the network node, a second downstream-processed signal based on the second upstream-processed signal and the first downstream-processed signal;
responsive to determining the second downstream-processed signal, outputting (<NUM>), by the second decoder, the second downstream-processed signal;
responsive to the second decoder outputting the second downstream-processed signal, determining (<NUM>), by the first decoder, a first revised downstream-processed signal based on the first downstream-processed signal and second downstream-processed signal;
responsive to determining (<NUM>) the first revised downstream-processed signal, outputting, by the first decoder, the first revised downstream-processed signal; and
determining (<NUM>) a decoded received signal based on outputs from the first decoder and the second decoder.