Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuits for facilitating operations of the memory array. For example, <CIT> discloses a 3D memory device with a storage stack structure on a substrate and a storage channel structure that penetrates the storage stack structure, a selection stack structure stacked on the storage stack structure and a selection channel structure that penetrates the selection stack structure and is connected to the storage channel structure. As another example, <CIT> discloses a 3D memory device including an alternating stack of insulating layers and word-line-level conductive layers on a substrate, and a vertical layer stack on the alternating stack, which includes an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer.

The present invention defines a memory device according to claim <NUM>; a corresponding manufacturing method is defined according to claim <NUM>. In one aspect, a memory device is disclosed. The memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

In another aspect, a memory system is disclosed. The memory system includes a memory device configured to store data. The memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, a dielectric layer over the channel structure, the dielectric layer having a first material, and a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material. The memory system also includes a memory controller coupled to the memory device and configured to control operations of the channel structure.

In still another aspect, a method for forming a memory device is disclosed. The method includes forming a stack structure over a substrate, forming a channel structure extending in the stack structure, depositing a first material to form a dielectric layer over the channel structure, and patterning the dielectric layer and the stack structure to form an opening, the opening through the dielectric layer and in contact with a conductive layer in a top portion of the stack structure. The method may also include depositing a second material into the opening to form a DSG cut structure. The second material is different from the first material. The method may further include forming a contact in the dielectric layer and in contact with the channel structure.

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present discloses.

The apparatus may be otherwise oriented (rotated <NUM> degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In some 3D memory devices, such as 3D NAND memory devices, memory cells are formed in functional channel structures that extend in a stack structure of interleaved stack conductive layers and stack dielectric layers. As the demand for higher capacity continues to rise, channel structures now have a more compact lateral arrangement to increase the number/density of memory cells, and thus the capacity of the 3D memory device. One way to increase the capacity is to allocate more functional channel structures in a memory block of a 3D memory device. For example, instead of <NUM> rows, <NUM> rows or <NUM> rows of functional channel structures can be arranged in a memory block. Another way, additionally or alternatively, is to reduce the number of dummy channel structures to form more functional channel structures in a memory block. Often, no memory cells are formed in dummy channel structures.

To operate a 3D memory device, the memory cells are divided into memory blocks, which are further divided into strings. For example, a drain-select gate (DSG) cut structure is often formed between adjacent strings in a memory block to disconnect DSGs in different strings. The strings can then be selected through the respective DSGs in various operations. A DSG cut structure is often formed above a dummy channel structure. To reduce the number of dummy channel structures, the dummy channel structures are not formed, and the DSG cut structures are formed between the strings while above a functional channel structure. A DSG cut structure is in contact with a row of functional channel structures and one or more DSGs of a string such that DSGs of the adjacent strings are disconnected. Vertically, the DSG cut structure partially overlaps with the channel structure, e.g., the drain of the channel structure.

After a DSG cut structure is formed in the stack structure, a contact, e.g., channel contact, is formed above and in contact with the functional channel structure. The contact can apply a drain voltage on the functional channel structure during operations. The contact is often formed in a dielectric layer over the functional channel structure. The dielectric layer and the DSG cut structure, in contact with the functional channel structure, often have the same dielectric material, such as silicon oxide. To form the contact, an opening is first formed in the dielectric layer to expose the underlying drain of the functional channel structure, and a conductive material is deposited in the opening. Vertically, the opening often partially overlaps with the DSG cut structure. Because the dielectric layer and the DSG cut structure have the same material, the etchant for forming the opening often over etches the DSG cut structure, resulting in an undesirable etched area in the functional channel structure. The conductive material may then be deposited in the undesirable etched area, causing issues such as short circuits and/or leakage.

The present disclosure provides a 3D memory device with a DSG cut structure containing an etch-stop material and the fabrication process to form the DSG cut structure. The etch-stop material is a different material than the dielectric layer over the channel structure. For example, the dielectric layer includes silicon oxide, and the etch-stop material includes silicon nitride. In some implementations, the etch-stop material consists of silicon nitride. In some implementations, the etch-stop material includes silicon nitride, silicon oxide, and/or an air gap. During the formation of the opening in which a contact is formed, the etch rate of the etch-stop material is desirably lower than that of the dielectric layer. The bottom surface of the opening can thus stop on the DSG cut structure, instead of extending into the channel structure. The channel structure, in contact with the DSG cut structure, is thus less susceptible to over-etch in the formation of the contact. Short circuits and/or leakage are thus less likely to happen in the 3D memory devices disclosed herein.

<FIG> illustrates a top view of a 3D memory device <NUM>, according to some aspects of the present disclosure. <FIG> illustrates a cross-sectional view of 3D memory device <NUM> along the A-A' direction, according to some aspects of the present disclosure. For illustrative purposes, only part of the 3D memory device is depicted in <FIG>. <FIG> and <FIG> are described together.

3D memory device <NUM> may include a substrate <NUM>, which may include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. In some implementations, substrate <NUM> is a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. It is noted that x-, y-, and z- axes are included in <FIG> and <FIG> to further illustrate the spatial relationship of the components in 3D memory device <NUM>. Substrate <NUM> of 3D memory device <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction and y-direction (i.e., the lateral directions). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a 3D memory device (e.g., 3D memory device <NUM>) is determined relative to the substrate of the 3D memory device (e.g., substrate <NUM>) in the z-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the 3D memory device in the y-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

3D memory device <NUM> may be part of a monolithic 3D memory device. The term "monolithic" means that the components (e.g., the peripheral device and memory array device) of the 3D memory device are formed on a single substrate. For monolithic 3D memory devices, the fabrication encounters additional restrictions due to the convolution of the peripheral device processing and the memory array device processing. For example, the fabrication of the memory array device (e.g., NAND memory strings) is constrained by the thermal budget associated with the peripheral devices that have been formed or to be formed on the same substrate.

Alternatively, 3D memory device <NUM> may be part of a non-monolithic 3D memory device, in which components (e.g., the peripheral device and memory array device) may be formed separately on different substrates and then bonded, for example, in a face-to-face manner. In some implementations, the memory array device substrate (e.g., substrate <NUM> remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral device (e.g., including any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>, such as page buffers, decoders, and latches; not shown) is flipped and faces down toward the memory array device (e.g., NAND memory strings) for hybrid bonding. It is understood that in some implementations, the memory array device substrate (e.g., substrate <NUM>) is flipped and faces down toward the peripheral device (not shown) for hybrid bonding, so that in the bonded non-monolithic 3D memory device, the memory array device is above the peripheral device. The memory array device substrate (e.g., substrate <NUM>) may be a thinned substrate (which is not the substrate of the bonded non-monolithic 3D memory device), and the back-end-of-line (BEOL) interconnects of the non-monolithic 3D memory device may be formed on the backside of the thinned memory array device substrate.

In some implementations, 3D memory device <NUM> is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings, e.g., channel structures, each extending vertically above substrate <NUM>. <FIG> illustrates the plan view of part of a memory block <NUM> in 3D memory device <NUM>, according to some aspects of the present disclosure. Memory block <NUM> may include a plurality of memory cells (not shown) arranged between a pair of slit structures <NUM>. The memory cells, arranged in an array, are formed in a plurality of channel structures <NUM> between slit structures <NUM>. 3D memory device <NUM> may also include one or more DSG cut structures <NUM> each between a pair of adjacent strings <NUM>.

As shown in <FIG>, 3D memory device <NUM> may include a stack structure <NUM>, and a plurality of channel structures <NUM> extending vertically through stack structure <NUM> in the z-direction. Stack structure <NUM> may include interleaved stack conductive layers and stack dielectric layers <NUM> above substrate <NUM>. The stack conductive layers may include one or more DSG lines <NUM>, e.g., on a top portion of stack structure <NUM>, and a plurality of control gate lines (e.g., word lines) <NUM>. For example, DSG lines <NUM> may be the top stack conductive layers, and the number of DSG lines may be <NUM>, <NUM>, <NUM>, <NUM>, etc. The number of the stack conductive layers may be any suitable positive number such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. The stack conductive layers (DSG lines <NUM> and word lines <NUM>) may have conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. Stack dielectric layers <NUM> may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

The intersection of a control gate line <NUM> and a channel structure <NUM> forms a memory cell. 3D memory device <NUM> may include a plurality, e.g., an array, of channel structures <NUM> located between slit structures <NUM> in the y-direction. In some implementations, channel structures <NUM> may be arranged in rows each extending in the x-direction, and the plurality of rows are arranged in the y-direction. In some implementations, memory block <NUM> includes <NUM>×M rows of channel structures <NUM> arranged in the y-direction, M being a positive integer. For example, memory block <NUM> may include <NUM> rows, <NUM> rows, <NUM> rows, etc. In some implementations, as shown in <FIG>, memory block <NUM> includes <NUM> rows of channel structures <NUM>.

Channel structure <NUM> may include a channel hole filled with semiconductor materials (e.g., as a semiconductor channel) and dielectric materials (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some implementations, the memory film is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. In some implementations, the remaining space of channel structure <NUM> may be partially or fully filled with a filling layer including dielectric materials, such as silicon oxide. Channel structure <NUM> may have a cylinder shape (e.g., a pillar shape). The filling layer, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center toward the outer surface of the pillar in this order, according to some implementations. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO).

In some implementations, channel structure <NUM> may further include a semiconductor plug, in a lower portion (e.g., at the lower end) of channel structure <NUM>. As used herein, the "upper end" of a component (e.g., channel structure <NUM>) is the end farther away from substrate <NUM> in the z-direction, and the "lower end" of the component (e.g., channel structure <NUM>) is the end closer to substrate <NUM> in the z-direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>. The semiconductor plug may include a semiconductor material, such as silicon, which can be epitaxially grown from substrate <NUM> in any suitable directions or deposited over substrate <NUM>. It is understood that in some implementations, the semiconductor plug includes single crystalline silicon, the same material as substrate <NUM>. In other words, the semiconductor plug may include an epitaxially-grown semiconductor layer that is the same as the material of substrate <NUM>. In some implementations, part of the semiconductor plug is above the top surface of substrate <NUM> and in contact with the semiconductor channel. The semiconductor plug may function as a channel controlled by a source select gate of channel structure <NUM>. It is understood that in some implementations, 3D memory device <NUM> does not include the semiconductor plug, as shown in <FIG>.

In some implementations, channel structure <NUM> further includes a channel plug in an upper portion (e.g., at the upper end) of channel structure <NUM>. The channel plug may be in contact with the upper end of the semiconductor channel. The channel plug may include semiconductor materials (e.g., polysilicon). By covering the upper end of channel structure <NUM> during the fabrication of 3D memory device <NUM>, the channel plug may function as an etch stop layer to prevent etching of dielectrics filled in channel structure <NUM>, such as silicon oxide and silicon nitride. In some implementations, the channel plug also functions as the drain of channel structure <NUM>.

Slit structures <NUM> may each extend vertically (e.g., in the z-direction) and laterally (e.g., in the x-direction) in stack structure <NUM>. Slit structures <NUM> may also be referred to as the gate-line slits. In some implementations, a source contact structure, as part of array common sources (ACS) that apply a source voltage on channel structures <NUM>, can be formed. Slit structures <NUM> may be in contact with substrate <NUM>. In some implementations, the source contact structures in slit structures <NUM> may each include a dielectric spacer and a source contact in the dielectric spacer. The source contact may be conductively connected to substrate <NUM>. The source contact may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. The dielectric spacer may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

3D memory device <NUM> further includes a dielectric layer <NUM> over and in contact with channel structure <NUM> (e.g., the channel plug of channel structure <NUM>), and a contact <NUM> in dielectric layer <NUM>. Contact <NUM> is in contact with channel structure <NUM> (e.g., the channel plug/drain of channel structure <NUM>). Dielectric layer <NUM> may include a single layer or multiple layers, and may include one or more dielectric materials. In some implementations, dielectric layer <NUM> may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. For example, dielectric layer <NUM> may include a silicon nitride layer sandwiched by a pair of silicon oxide layers. In some implementations, the channel plug (e.g., drain) of channel structure <NUM> is in contact with a silicon oxide layer. In some implementations, contact <NUM> may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. Contact <NUM> may apply a drain voltage on channel structure <NUM> during operations.

One or more DSG cut structures <NUM> may each extend vertically (e.g., in the z-direction) and laterally (e.g., in the x-direction) in stack structure <NUM>. DSG cut structures <NUM> may each be positioned between adjacent strings <NUM> of memory block <NUM>. For example, memory block <NUM> may include <NUM> rows of channel structures <NUM> that are divided into four strings <NUM> by three DSG cut structures <NUM>. As shown in <FIG> and <FIG>, DSG cut structure <NUM> may be in contact with a plurality of channel structures <NUM> in the first row of each string <NUM>. Channel structures <NUM>, in contact with DSG cut structures <NUM>, may be functional channel structures in which memory cells are formed. DSG cut structures <NUM> may also be in contact with one or more stack conductive layers in one of the adjacent strings <NUM> such that these stack conductive layers are disconnected/insulated from one string <NUM> to another string <NUM>. The stack conductive layers, in contact with DSG cut structures <NUM>, may be referred to as DSG lines <NUM>. The portion of DSG lines <NUM> in each string <NUM> may form the DSGs of the respective string <NUM>, and a gate-selective voltage may be applied on the DSGs for selecting the respective string <NUM> in operations. In some implementations, depending on the designs, the number of DSG lines <NUM> may be <NUM>, <NUM>, <NUM>, <NUM>, or other suitable positive numbers. In some implementations, the DSGs in each string <NUM> may be positioned at the top portion of stack structure <NUM> and may be referred to as the top select gates (TSGs). In some implementations, as shown in <FIG>, DSG cut structure <NUM> is in contact with two adjacent rows of channel structures <NUM>. For ease of illustration, in the present disclosure, a DSG cut structure is depicted in contact with one channel structure in <FIG> and <FIG> as an example.

DSG cut structures <NUM> include a different material than dielectric layer <NUM>. In some implementations, DSG cut structure <NUM> may include a dielectric material that can function as the etch-stop layer in the formation of contact <NUM>. In some implementations, the etchant used to form the opening, in which contact <NUM> is located, has a higher etch rate on dielectric layer <NUM> than DSG cut structure <NUM>. For example, the etch selectivity of dielectric layer <NUM> over DSG cut structure <NUM> may be greater than <NUM>. In some implementations, dielectric layer <NUM> includes silicon oxide, and DSG cut structure <NUM> includes silicon nitride.

<FIG> each illustrates a structure of DSG cut structure <NUM>, according to some aspects of the present disclosure. In one example, as shown in <FIG>, DSG cut structure <NUM> may include silicon nitride. In some implementations, DSG cut structure <NUM> consists of an etch-stop layer, such as a silicon nitride layer. In another example, as shown in <FIG>, DSG cut structure <NUM> may include a liner layer <NUM>-<NUM> and an etch-stop layer <NUM>-<NUM> surrounded by and in contact with liner layer <NUM>-<NUM>. Liner layer <NUM>-<NUM> may be in contact with channel structure <NUM> and DSG lines <NUM>. The top surface of etch-stop layer <NUM>-<NUM> may be coplanar with the top surface of dielectric layer <NUM>. In some implementations, liner layer <NUM>-<NUM> includes silicon oxide, and etch-stop layer <NUM>-<NUM> includes silicon nitride. In a further example, as shown in <FIG>, DSG cut structure <NUM> may include a liner layer <NUM>-<NUM>, an etch-stop layer <NUM>-<NUM> surrounded by and in contact with liner layer <NUM>-<NUM>, and a filler layer <NUM>-<NUM> surrounded by and in contact with (e.g., in) etch-stop layer <NUM>-<NUM>. The material of filler layer <NUM>-<NUM> may be different from that of etch-stop layer <NUM>-<NUM>. For example, filler layer <NUM>-<NUM> may include silicon oxide, silicon oxynitride, or an airgap. In some implementations, filler layer <NUM>-<NUM> includes an airgap. In the examples shown in <FIG> and <FIG>, a thickness of liner layer <NUM>-<NUM> may range between <NUM> to <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>). For example, the thickness of liner layer <NUM>-<NUM> may be about <NUM>.

<FIG> illustrate cross-sections of a 3D memory device <NUM> at different stages of a manufacturing process, according to some aspects of the present disclosure. <FIG> illustrates a flowchart of an exemplary method <NUM> for forming 3D memory device <NUM>, according to some aspects of the present disclosure. 3D memory device <NUM> may be an example of 3D memory device <NUM>. For illustrative purposes, <FIG> and method <NUM> will be discussed together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG> and <FIG>.

Method <NUM> starts at operation <NUM>, in which a stack structure is formed over a substrate, and a channel structure is formed in the stack structure. <FIG> illustrates a corresponding structure.

As shown in <FIG>, a stack structure <NUM> is formed over a substrate (not shown), and a channel structure <NUM> may be formed extending vertically in stack structure <NUM>. Stack structure <NUM> may include a plurality of stack conductive layers (e.g., DSG lines <NUM> and control gate lines <NUM>) interleaved with a plurality of stack dielectric layers <NUM>.

To form stack structure <NUM>, a plurality of first material layers and a plurality of second material layers are deposited on a substrate to stack above a substrate. In a "gate-last" process, a dielectric stack (not shown) having a plurality of alternating stack dielectric layers and stack sacrificial layers may be formed above a substrate. The stack dielectric layers and stack sacrificial layers may form a plurality of stack dielectric/sacrificial layer pairs over the substrate. A gate replacement process may be performed subsequently to form the stack conductive layers in stack structure <NUM>. In some implementations, the substrate may include a silicon substrate. The stack dielectric layers and the stack sacrificial layers may include different materials. In some implementations, each stack dielectric layer may include a layer of silicon oxide, and each stack sacrificial layer may include a layer of silicon nitride. The dielectric stack may be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some implementations, a pad oxide layer (not shown) is formed between the substrate and the dielectric stack by depositing dielectric materials, such as silicon oxide, on the substrate.

In a "gate-first" process, a stack of interleaved stack conductive layers and stack dielectric layers may be formed over a substrate, and no gate replacement process is needed. The stack conductive layers may each include a layer of polysilicon, and the stack dielectric layers may each include a layer of silicon oxide. The stack may be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, the interleaved first material layers and the second material layers may undergo a trimming process, in which the first material layers and the second material layers are patterned repeatedly to form a staircase structure on one or more sides of stack structure <NUM>. The trimming process may include photolithography and etching processes (e.g., wet etch and/or dry etch).

A channel structure <NUM> may be formed extending through stack structure <NUM> (e.g., a dielectric stack) in the z-direction. Channel structure <NUM> may include a channel plug <NUM> (e.g., the drain of channel structure <NUM>) at the top portion of channel structure <NUM> (or stack structure <NUM>). Channel plug <NUM> may include polysilicon and/or metal, and may be subsequently conductively connected to a contact that applies a drain voltage on channel structure <NUM>. In some implementations, an etch process may be performed to form a plurality of channel holes extending vertically through the interleaved stack dielectric/sacrificial layer pairs. In some implementations, fabrication processes for forming the channel holes may include wet etching and/or dry etching, such as deep reactive ion etching (DRIE). In some implementations, the channel holes may extend further into the top portion of the substrate. After the formation of the channel holes, in some implementations, an epitaxial operation, e.g., a selective epitaxial growth operation, may be performed to form the semiconductor plugs at the bottom of a channel hole. The memory film, including a tunneling layer, a storage layer, a blocking layer, and a semiconductor channel can be formed in the channel hole. Optionally, a filling layer may be formed in the channel hole. In some implementations, channel structures <NUM> may not include a semiconductor plug. The deposition of the memory film, the semiconductor channel, and the filling layer may include any suitable thin-filmed deposition processes such as CVD, PVD, ALD, or any combination thereof. The deposition of channel plug <NUM> may include CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

A plurality of gate line slits (not shown) may be formed extending through stack structure <NUM> in the z-direction. The gate line slits, in which the source contact structures are formed, may extend laterally in the x-direction, referring back to <FIG>. The gate line slits may be in contact or extend into the top portion of the substrate. In some implementations, fabrication processes for forming the gate line slits may include wet etching and/or dry etching, such as deep reactive ion etching (DRIE).

In a gate-last process, anisotropic etching process may be performed to remove the stack sacrificial layers and form a plurality of lateral recesses. One or more thin filmed deposition processes such as CVD, PVD, and/or ALD may be performed to form a plurality of stack conductive layers in the lateral recesses. In some implementations, the stack conductive layers include W.

A source contact structure (e.g., referring back to source contact structure <NUM>) may then be formed in each gate line slit. The source contact structure may include a dielectric spacer (e.g., silicon oxide) and a source contact (e.g., W) in the dielectric spacer. The formation of the dielectric spacer may include one or more thin filmed deposition processes such as CVD, PVD, and/or ALD. The formation of the source contact may include CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, in which a first material is deposited to form a dielectric layer over the channel structure. <FIG> illustrates a corresponding structure.

A shown in <FIG>, after stack structure <NUM> and channel structure <NUM> are formed, a dielectric layer <NUM> is formed over and in contact with channel structure <NUM>. The formation of dielectric layer <NUM> may include deposition of a first material, e.g., silicon oxide. In some implementations, dielectric layer <NUM>, having a single layer or multiple layers, includes silicon oxide, silicon nitride, and/or silicon oxynitride. In some implementations, dielectric layer <NUM> includes a silicon nitride layer sandwiched by a pair of silicon oxide layers. In some implementations, channel structure <NUM> (e.g., the drain of channel structure <NUM>) is in contact with a layer of silicon oxide, which is part of dielectric layer <NUM>. The formation of dielectric layer <NUM> may include one or more thin filmed deposition processes such as CVD, PVD, and/or ALD.

Method <NUM> proceeds to operation <NUM>, in which the dielectric layer and the stack structure are patterned to form an opening, the opening being through the dielectric layer and in contact with one or more stack conductive layers at a top portion of the stack structure. <FIG> illustrates a corresponding structure.

As shown in <FIG>, after the formation of dielectric layer <NUM>, an opening <NUM> is formed through dielectric layer <NUM> and into stack structure <NUM>. Opening <NUM> may be in contact with a top portion of channel structure <NUM> and one or more stack conductive layers at the top portion of stack structure <NUM>. For example, in the x-y plane, opening <NUM> may partially overlap with channel structure <NUM> and the one or more stack conductive layers. Opening <NUM> may disconnect the one or more stack conductive layers from channel structure <NUM>. At least a portion of channel plug <NUM> is retained intact for subsequent conductive connection to a contact. In some implementations, opening <NUM> is positioned between channel structure <NUM> and the one or more stack conductive layers, and a bottom surface of opening <NUM> may be below the bottom surfaces of the one or more stack conductive layers. The number of stack conductive layers disconnected by opening <NUM> may be <NUM>, <NUM>, <NUM>, <NUM>, etc. The disconnected stack conductive layers may form DSG lines <NUM>, and the stack conductive layers below DSG lines <NUM> may include control gate lines <NUM>. In some implementations, the formation of an opening <NUM> includes a photolithography process and an etching process (e.g., wet etch and/or dry etch).

Method <NUM> proceeds to operation <NUM>, in which a second material is deposited into the opening to form a DSG cut structure. <FIG> illustrate corresponding structures.

After the formation of opening <NUM>, a second material may be deposited into opening <NUM> to form a DSG cut structure. The second material may include silicon nitride, which can function as an etch-stop material in the subsequent etching of dielectric layer <NUM>. In some implementations, the second material also includes other non-conductive materials such as other dielectric materials and/or an air gap. In some implementations, the second material consists of silicon nitride, and the deposition of the second material may include one or more thin filmed deposition processes such as CVD, PVD, and/or ALD. A planarization process, such as chemical-mechanical polishing (CMP) and/or recess etching, is performed after the deposition to remove any excess deposited material over dielectric layer <NUM>.

As an example, <FIG> illustrate a structure in which the second material includes silicon nitride and silicon oxide. As shown in <FIG>, a liner material layer <NUM> of a suitable material, e.g., silicon oxide, may be deposited into opening <NUM>. In some implementations, liner material layer <NUM> has a thickness of <NUM> to <NUM>, such as <NUM>, and can be deposited using ALD. Liner material layer <NUM> may cover the bottom surface and side surface of opening <NUM>. As shown in <FIG>, an etch-stop material layer <NUM> may be deposited over liner material layer <NUM> to fill up opening <NUM>. The deposition of etch-stop material layer <NUM> may include one or more thin filmed deposition processes such as CVD, PVD, and/or ALD. In some implementations, an air gap (not shown) is formed in etch-stop material layer <NUM>. The formation of the air gap may include any suitable fabrication process, such as rapid thermal sealing. The air gap may be surrounded, e.g., sealed, by etch-stop material layer <NUM>.

As shown in <FIG>, a planarization process, such as CMP and/or recess etching, is performed after the deposition of etch-stop material layer <NUM> to remove any excess deposited material over dielectric layer <NUM>. A DSG cut structure <NUM>, having a liner layer <NUM> (e.g., silicon oxide) and an etch-stop layer <NUM> (e.g., silicon nitride), may be formed. Liner layer <NUM> may surround etch-stop layer <NUM> at the bottom surface and side surfaces of etch-stop layer <NUM>. In some implementations, a top surface of DSG cut structure <NUM> may be coplanar with dielectric layer <NUM>.

Method <NUM> proceeds to operation <NUM>, in which a contact is formed in the dielectric layer, the contact being in contact with the channel structure. <FIG> illustrate corresponding structures.

As shown in <FIG>, after the formation of DSG cut structure <NUM>, a cap layer <NUM> may be formed over dielectric layer <NUM> and DSG cut structure <NUM>. Cap layer <NUM> may cover at least DSG cut structure <NUM> and channel structure <NUM>. In some implementations, cap layer <NUM> includes a dielectric material such as silicon oxide, and can be deposited using one or more thin filmed deposition processes such as CVD, PVD, and/or ALD.

As shown in <FIG>, an opening <NUM> may be formed in cap layer <NUM> and dielectric layer <NUM>. Opening <NUM> may extend through dielectric layer <NUM> and be in contact with channel structure <NUM> (e.g., channel plug <NUM>). In some implementations, opening <NUM> may be in contact with DSG cut structure <NUM>, e.g., partially landed on DSG cut structure <NUM>, as shown in <FIG>. At least a top surface of etch-stop layer <NUM> may be exposed by the etching to form opening <NUM>. Part of liner layer <NUM> in contact with opening <NUM> may or may not be partially removed by the etching process that forms opening <NUM>. In some implementations, linear layer <NUM> may be fully or partially retained on the etch-stop layer <NUM> in opening <NUM>. For example, when linear layer <NUM> is fully or partially removed in opening <NUM>, the side surface etch-stop layer <NUM> may be exposed in opening <NUM>. In another example, when linear layer <NUM> is fully retained, the side surface of etch-stop layer <NUM> is covered by linear layer <NUM> in opening <NUM>. In some implementations, because the thickness of liner layer <NUM> is desirably thin, etch-stop layer <NUM> still prevents the etching of channel structure <NUM>. Channel structure <NUM> is thus less susceptible to damages during the formation of opening <NUM>. In some implementations, the formation of opening <NUM> includes a photolithography process and an etching process (e.g., dry etch and/or wet etch).

As shown in <FIG>, a conductive material is deposited to fill opening <NUM>, and a contact <NUM> is formed. Contact <NUM> may extend in cap layer <NUM>, through dielectric layer <NUM>, and in contact with channel plug <NUM> of channel structure <NUM>. In some implementations, if linear layer <NUM> is partially or fully removed in opening <NUM>, contact <NUM> is in contact with the side surface and the top surface of etch-stop layer <NUM>. In some implementations, if linear layer <NUM> is fully retained on the side surface of etch-stop layer <NUM>, contact <NUM> is in contact with etch-stop layer <NUM> on the top surface but not the side surface. In some implementations, the conductive material includes tungsten (W), and the deposition includes CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. In some implementations, an adhesive layer, e.g., titanium nitride (TiN), is deposited on the side surfaces of opening <NUM> before the deposition of tungsten. In some implementations, the deposition of the adhesive layer includes CVD, PVD, ALD, or any combination thereof.

<FIG> illustrates a block diagram of an exemplary system <NUM> having a memory device, according to some aspects of the present disclosure. System <NUM> can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in <FIG>, system <NUM> can include a host <NUM> and a memory system <NUM> having one or more memory devices <NUM> and a memory controller <NUM>. Host <NUM> can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host <NUM> can be configured to send or receive data to or from memory devices <NUM>.

Memory device <NUM> can be any memory device disclosed in the present disclosure. As disclosed above in detail, memory device <NUM>, such as a NAND Flash memory device, may have one or more DSG cut structures having an etch-stop material. Memory controller <NUM> is coupled to memory device <NUM> and host <NUM> and is configured to control memory device <NUM>, according to some implementations. Memory controller <NUM> can manage the data stored in memory device <NUM> and communicate with host <NUM>. For example, memory controller <NUM> may be coupled to memory device <NUM>, such as 3D memory device <NUM> described above, and memory controller <NUM> may be configured to control operations of channel structure <NUM> of 3D memory device <NUM> through the DSG lines <NUM>.

In some implementations, memory controller <NUM> is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller <NUM> is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller <NUM> can be configured to control operations of memory device <NUM>, such as read, erase, and program operations. Memory controller <NUM> can also be configured to manage various functions with respect to the data stored or to be stored in memory device <NUM> including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller <NUM> is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device <NUM>. Any other suitable functions may be performed by memory controller <NUM> as well, for example, formatting memory device <NUM>. Memory controller <NUM> can communicate with an external device (e.g., host <NUM>) according to a particular communication protocol. For example, memory controller <NUM> may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc..

Memory controller <NUM> and one or more memory devices <NUM> can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system <NUM> can be implemented and packaged into different types of end electronic products. In one example as shown in <FIG>, memory controller <NUM> and a single memory device <NUM> may be integrated into a memory card <NUM>. Memory card <NUM> can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card <NUM> can further include a memory card connector <NUM> coupling memory card <NUM> with a host (e.g., host <NUM> in <FIG>). In another example as shown in <FIG>, memory controller <NUM> and multiple memory devices <NUM> may be integrated into an SSD <NUM>. SSD <NUM> can further include an SSD connector <NUM> coupling SSD <NUM> with a host (e.g., host <NUM> in <FIG>). In some implementations, the storage capacity and/or the operation speed of SSD <NUM> is greater than those of memory card <NUM>.

According to one aspect of the present disclosure, a memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

In some implementations, the DSG cut structure is in contact with the channel structure and a DSG in the plurality of conductive layers.

In some implementations, an etching selectivity of the first material over the second material is greater than <NUM>.

In some implementations, the first and second materials each includes a respective dielectric material.

In some implementations, the first material includes silicon oxide, and the second material includes silicon nitride.

In some implementations, the DSG cut structure does not include silicon oxide.

In some implementations, the DSG cut structure includes silicon nitride.

In some implementations, the DSG cut structure includes a liner silicon oxide layer and a silicon nitride layer surrounded by the liner silicon oxide layer.

In some implementations, a thickness of the liner silicon oxide layer is in a range of <NUM> to <NUM>.

In some implementations, the DSG cut structure includes a silicon nitride layer surrounded by the liner silicon oxide layer, and an air gap surrounded by the silicon nitride layer.

In some implementations, the memory device further includes a pair of source contact structures extending in a lateral direction and a memory block between the pair of source contact structures. The memory block includes a plurality of memory cells in a plurality of channel structures between the source contact structures. The memory block includes a pair of strings adjacent to each other. Each of the strings includes a plurality of rows of channel structures in the lateral direction. The DSG cut structure, extending in the lateral direction, is between the pair of strings and is in contact with one of the rows of the channel structures.

In some implementations, each of the strings includes four rows of channel structures.

In some implementations, the memory block includes four strings. Each of the four strings includes four rows of channel structures extending in the lateral direction.

According to another aspect of the present disclosure, a memory system includes a memory device configured to store data. The memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, a dielectric layer over the channel structure, the dielectric layer having a first material, and a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material. The memory system also includes a memory controller coupled to the memory device and configured to control operations of the channel structure.

According to another aspect of the present disclosure, a method for forming a memory device includes forming a stack structure over a substrate, forming a channel structure extending in the stack structure, depositing a first material to form a dielectric layer over the channel structure, and patterning the dielectric layer and the stack structure to form an opening, the opening through the dielectric layer and in contact with a conductive layer in a top portion of the stack structure. The method may also include depositing a second material into the opening to form a DSG cut structure. The second material is different from the first material. The method may further include forming a contact in the dielectric layer and in contact with the channel structure.

In some implementations, the opening is in contact with the channel structure.

In some implementations, depositing the first material includes depositing silicon oxide.

In some implementations, depositing the second material to form the DSG cut structure includes depositing silicon nitride.

In some implementations, depositing the second material to form the DSG cut structure includes depositing the silicon nitride to fill the opening.

In some implementations, depositing the second material to form the DSG cut structure includes depositing a liner oxide layer in the opening, the liner oxide layer in contact with surfaces of the opening, and depositing a silicon nitride layer to fill the opening.

In some implementations, the deposition of the liner oxide layer includes an ALD.

In some implementations, depositing the second material to form the DSG cut structure includes depositing a liner oxide layer in the opening. The liner oxide layer is in contact with surfaces of the opening. Depositing the second material may also include depositing a silicon nitride layer over the liner oxide layer, and forming an air gap in the silicon nitride layer during the deposition of the silicon nitride layer.

In some implementations, forming the contact in the dielectric layer includes etching the dielectric layer to form another opening in contact with the channel structure and the DSG cut structure, and depositing a conductive material to fill the other opening.

In some implementations, the DSG cut structure is an etch-stop layer of the etching of the dielectric layer.

In some implementations, an etch rate on the second material is lower than an etch rate on the first material in the etching of the dielectric layer.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

Claim 1:
A memory device (<NUM>, <NUM>), comprising:
a stack structure (<NUM>, <NUM>) over a substrate (<NUM>);
a channel structure (<NUM>, <NUM>) extending in the stack structure (<NUM>, <NUM>);
a dielectric layer (<NUM>, <NUM>) over the channel structure (<NUM>, <NUM>), the dielectric layer (<NUM>, <NUM>) comprising a first material;
a drain-select gate (DSG) cut structure (<NUM>, <NUM>) extending through the dielectric layer (<NUM>, <NUM>), characterized in that the DSG cut structure (<NUM>, <NUM>) comprises a second material different from the first material;
further comprising a contact (<NUM>,<NUM>) above and in contact with the channel structure (<NUM>, <NUM>), wherein the contact (<NUM>, <NUM>) is in the dielectric layer (<NUM>, <NUM>) and is in contact with the DSG cut structure (<NUM>, <NUM>), wherein the contact is formed of a conductive material.