Patent Description:
Moore's law, that sets the footprint area of a transistor to scale by a factor <NUM>, i.e. the transistor gate length L to scale by a factor √<NUM>, every <NUM> years, has been the driving force of the electronic industry, scaling the length of a transistor to its limits. Today, the minimal distance between the gate of two subsequent transistors, a measure known as contacted poly pitch (CPP) or gate pitch (CGP), has been scaled to approximately <NUM>. Device parameters limiting further CPP scaling include gate length, source/drain contact area and gate spacer width.

A forksheet device architecture is described by<NPL>]. Specifically, according to the aforementioned document, there are provided nanosheets extending along an insulating wall, a gate structure is provided thus defining channel regions in said nanosheets. Furthermore, epitaxial source/drain regions are provided on both sides of the gate structure. The nanosheets extend beyond the gate region, and the epitaxial source/drain regions wrap around said extensions. The epitaxial source/drain regions comprise therefore common bodies and extending portions (i.e. prongs) extending from the respective common bodies towards the insulating wall and disposed between the nanosheets. The epitaxial source/drain regions and the gate structure are both provided on same vertical sides of the nanosheets. The insulating wall is provided on opposite vertical sides of the nanosheets.

An objective of the present inventive concept is to provide a method for forming a semiconductor device, in particular a FET device, with a novel design which may enable further CPP scaling. Additional and alternative objectives may be understood from the following.

According to an aspect, there is provided a method for forming a FET device, the method comprising:.

The method of the present aspect enables fabrication of a FET device comprising a common gate body portion and common source and drain body portions wherein the common gate body portion is located on opposite sides (i.e. laterally opposite sides) with respect to the common source and drain body portions. In other words, the common gate body portion may be laterally / horizontally offset with respect to the common source and drain body portions. Meanwhile, the gate prongs may be offset vertically with respect to the source and drain prongs. In other words, the source and drain prongs and the gate prongs may be located at different vertical levels (e.g. above an underlying substrate). In a conventional FET, the source/drain terminals and the gate terminal are separated by a spacer of a certain minimum length Ls, in order to sufficiently electrically separate the gate from the source/drain, that appears twice in the CPP of a conventional FET device. This separation may be reduced or even omitted in a device formed in accordance with the method according to the present aspect.

The opposite-side arrangement of the source/drain and gate body portions is facilitated by removing the dummy material and forming the source/drain bodies while masking the fin structure from the second side, and by forming the gate cavities and the gate body while masking the fin structure from the first side. Deposition of source/drain body material at the second side and of gate material at the first side may accordingly be counteracted.

As used herein, the wording "masking the fin structure from a first/second side" is to be understood as covering the fin structure from the first/second side such that the processing may be applied selectively to the opposite side (e.g. second/first) of the fin structure, e.g. such that etching from, forming of a source/drain or gate body, or material deposition at the opposite side is counteracted or prevented.

During the etching of the first and second fin parts to form the source and drain cavities the third fin part may be masked from both the first and second sides. During the removing of the dummy material and the forming of the source and drain bodies, the third fin part may be masked from both the first and second sides. During the etching of the third fin part, and the forming of the gate body, the first and second fin parts may be masked from both the first and second sides.

The method may comprise forming a first mask structure for masking the fin structure, the masking structure covering the third fin part from the first and the second side, and defining openings exposing each of the first and second fin parts from each of the first and second sides. The method may subsequently comprise, while masking the fin structure using the first mask structure, conducting said etching of each of the first and second fin parts to form the source and drain cavities. The first and second fin parts may accordingly be laterally etched back from the first and second sides through the openings in the first mask structure.

The method may comprise forming a second mask structure for masking the fin structure, the masking structure covering the first, second and third fin parts from the second side, the third fin part from the first side, and defining openings exposing the first and second fin parts from the first side. The method may subsequently comprise, while masking the fin structure using the second mask structure, conducting said removing of the dummy material, and conducting said forming of the source body and drain body. The dummy material in the source/drain cavities of the first and second fin parts may accordingly be laterally etched back from the first side through the openings in the second mask structure. Correspondingly, the respective common body portions of the source and drain bodies may be formed along the first side of the first and second fin parts.

The method may comprise forming a third mask structure for masking the fin structure, the masking structure covering the first, second and third fin parts from the first side, the first and second fin parts from the second side, and defining an opening exposing the third fin part from the second side. The method may subsequently comprise, while masking the fin structure using the second mask structure, conducting said etching of the third fin part, and conducting said forming of the gate body. The third fin part may accordingly be laterally etched back from the second side through the opening in the third mask structure. Correspondingly, the common gate body portion may be formed along the second side of the third fin part.

To facilitate the lateral processing (e.g. etching) of the fin parts, each of the first, second and third mask structures may further cover the fin structure (e.g. each of the first, second and third fin parts) from above.

The mask structures may be provided in various ways:
According to some embodiments, the first mask structure may be provided by depositing a cover material deposited along the first and second sides of the fin structure and defining openings or trenches therein to expose the first and second fin parts from each of the first and second sides. For example, the cover material may be a conformally deposited material, e.g. forming a liner layer. The cover material may also be an insulating material or a process material deposited to embed the fin structure. As used herein the term "trench" is to be understood as an opening or hole formed in a deposited material, e.g. the cover material.

According to some embodiments, the second mask structure may be provided by depositing a cover material deposited along the first and second sides of the fin structure and defining openings or trenches therein to expose the first and second fin parts from the first side. For example, the cover material may be a conformally deposited material, e.g. forming a liner layer. The cover material may also be an insulating material or a process material deposited to embed the fin structure.

According to some embodiments, the third mask structure may be provided by depositing a cover material deposited along the first and second sides of the fin structure and defining a trench therein to expose the third part from the second side. For example, the cover material may be an insulating material or a process material deposited to embed the fin structure.

The fin structure may further comprise a capping layer of a hardmask material (e.g. a top-most layer of the layer stack). The capping layer may accordingly mask the fin structure from above during each of the processing steps. The capping layer may e.g. form part of any of the mask structures mentioned herein.

By laterally etching a fin part from the first and/or second side, cavities extending through (e.g. completely through along a width dimension of the fin structure) and across the fin part may be formed. A "lateral" etching is hereby to be understood as an etching oriented within a plane of extension of the layers of the stack.

As may be appreciated, a lateral etching may typically be achieved by an isotropic etching process. An isotropic etching may have a tendency to cause a curved or rounded etch front of a layer being etched. Consequently, a dimension of an isotropically etched cavity may vary along a width dimension of the fin structure. According to the method, the first and the second fin parts are etched laterally from each of the first and second sides, e.g. simultaneously. A variation of the dimension of the source and drain cavities may hence be reduced compared to a one-sided cavity etch. This may in turn facilitate control of channel length in the finished FET device.

By further filling the source and drain cavities with a dummy material, and, while masking the fin structure (e.g. the first, second and third fin parts) from the second side, removing the dummy material by etching from the first side and subsequently forming the source and drain bodies, the merits of the two-sided etching of the first and second fin parts may be preserved while counteracting forming of the source and drain bodies along the second side.

The method of the present aspect may be used to form a FET device of either a first type or a second type. To form the first type of FET device, the non-channel layers may comprise first non-channel layers and second non-channel layers alternating the first non-channel layers, wherein the first set of layers (in which the source and drain cavities are formed) may be defined by the first non-channel layers, and the second set of layers (in which the gate cavities are formed) may be defined by the second non-channel layers. To form the second type of FET device, the first set of layers (in which the source and drain cavities are formed) may be defined by the channel layers, and the second set of layers (in which the gate cavities are formed) may be defined by the non-channel layers. Various embodiments of forming the first and second types of FET devices will be set out in the following.

As used herein, the term "horizontal" indicates an orientation or a direction in a horizontal plane, i.e. parallel to (a main plane of extension) of a substrate on which the fin structure is formed. The term "vertical" is used to refer to a direction along a height direction of the fin, e.g. corresponding to the stacking direction of the layers of the layer stack, or equivalently normal to a (main plane of extension of) the substrate.

The wording "first/second sides of the fin structure" is to be understood to indicate the opposite lateral sides of the fin structure, i.e. extending along a longitudinal dimension of the fin structure.

As used herein, the term "source / drain prong" refers to a portion (e.g. layer-shaped) of the source / drain body protruding from the common source / drain body portion to a respective free end. The term "gate prong" correspondingly refers to a portion (e.g. layer-shaped) of the gate body protruding from the common gate body portion to a respective free end.

When reference is made to a pair of a source prong and a drain prong (or shorter, a pair of source and drain prongs), reference is made to a source prong and a drain prong arranged in abutment with a same channel layer. The pair of source and drain prongs may in particular refer to source and drain prongs arranged at a same level over the substrate.

According to embodiments, the method may further comprise, subsequent to the filling of the source and drain cavities with the dummy material:.

The method may subsequently comprise conducting the removing of the dummy material and the forming of the source and drain bodies via the openings in the second cover material.

This allows exposing respective side surface portions of each of the first and second fin parts from only the first side, while the opposite side surface portions of the first and second fin parts remain covered, as well as opposite side surface portions of the third fin part.

The cover material may be conformally deposited. The second cover material may form a liner layer, covering the fin structure from the first and second sides and defining openings only along the first side, more specifically along the side surface portions of each of the first and second fin parts.

According to embodiments, the method may further comprise forming a gate trench along the third fin part to expose the third fin part from only the second side, wherein the gate trench is formed in an insulating material deposited along the first and second sides of the fin structure. The etching of the third fin part and the forming of the gate body may subsequently be conducted via the gate trench.

The forming of a gate trench allows the third fin part to be selectively accessed and etched to form the gate cavities from only the second side of the fin structure. The gate trench further facilitates forming of the gate body in that one or more gate materials may be deposited in the gate cavities and in the gate trench.

According to embodiments, the etching of the third fin part and the forming of the gate body may be conducted subsequent to forming the source and drain bodies, and wherein the method may comprise depositing the insulating material to embed the fin structure and the source and drain bodies.

According to embodiments, forming the source and drain bodies may comprise epitaxially growing a source/drain material in the set of source cavities and the set of drain cavities to form prongs therein, and further growing the source/drain material on the prongs such that the source/drain material merges to form a respective common body portion of the source and drain bodies. The common source and drain body portions may hence be formed as merged epitaxial semiconductor bodies.

According to embodiments, the method may further comprise subjecting the first and second fin parts to an ion implantation process while masking the third fin part from the ion implantation process. Doping of the third fin part may hence be counteracted while doping of the first and second parts may be allowed. Forming the set of source cavities and the set of drain cavities may accordingly comprises selectively etching doped material of the first set of layers of the layer stack.

By virtue of the ion implantation process, a longitudinal etch contrast / etch selectivity may be introduced in the layers. Thereby, a tendency of an isotropic etching of the various layers of the layer stack causing a curved or rounded etch front may be reduced. More specifically, the variable doping concentrations enables a reduced etch rate of the un-doped versus doped portions, or vice versa during the cavity etches.

According to embodiments for forming the first type of FET device, the channel layers may be of a channel material and the non-channel layers may be alternatingly first non-channel layers of a first layer material and second non-channel layers of a second layer material. The channel material, the first layer material and the second layer material hereby refers to different materials.

Accordingly, the etching of the first fin part and the second fin part to form the source and drain cavities may comprise selectively etching the first layer material (e.g. etching the first layer material selectively to the second layer material and the channel material). Further, the etching of the third fin part to form the gate cavities may comprise selectively etching the second layer material (e.g. etching the second layer material selectively to the first layer material and the channel material).

The source and drain prongs may thus be offset vertically from both the gate prongs and the channel layers. Accordingly, the gate prongs may be formed at first levels corresponding to the levels of the first non-channel layers, the source and drain prongs may be formed at second levels corresponding to the levels of the second non-channel layers, wherein the channel layers are located at levels intermediate the first and second levels.

The first layer material may be a first dielectric material. A (dielectric) first non-channel layer may hence be provided between each respective pair of source and drain prong. A dielectric first non-channel layer may also be denoted "first dielectric layer".

According to embodiments, forming the fin structure may comprise:.

The sacrificial material hereby refers to a semiconductor material different from each of the channel material, the first layer material, the second layer material and the channel material.

Replacing the sacrificial layers with the first non-channel layers may comprise:.

According to some embodiments, forming the support structure may comprise: depositing a process material embedding the preliminary fin structure; and forming a trench in the process material, alongside the preliminary fin structure. The sacrificial layers may subsequently be removed from the preliminary fin structure by selectively etching (e.g. laterally) the sacrificial material from the trench in the process material, thereby forming the gaps in the preliminary fin structure.

The second layer material may be a second semiconductor material different from the channel material. The second semiconductor material may further be different from the above-mentioned sacrificial material. The preliminary fin structure may hence comprise a stack of semiconductor layers.

According to embodiments, the method may further comprise, prior to forming the source and drain cavities:.

Each gate prong may hence be formed at a location in the fin structure between a respective pair of second dielectric layers. Each second dielectric layer may provide (electric) insulation between mutually opposite surface portions of neighboring channel layers abutting different pairs of source and drain prongs.

During the etching of the first and second fin parts to form the second cavities, the third fin part may be masked from both the first and second sides.

The method may comprise forming a fourth mask structure for masking the fin structure, the masking structure covering the third fin part from the first and the second side, and defining openings exposing each of the first and second fin parts from each of the first and second sides. The method may subsequently comprise, while masking the fin structure using the fourth mask structure, conducting said etching of each of the first and second fin parts to form the second cavities. The first and second fin parts may accordingly be laterally etched back from the first and second sides through the openings in the fourth mask structure.

According to some embodiments, the etching of the third fin part to form the gate cavities may comprise selectively etching the second layer material from the second side to remove the second layer material remaining between the second dielectric layers.

As the second cavities are formed in a double-sided cavity etch (see above discussion regarding isotropic etching), a variation of the dimension of gate cavities along the width dimension of the fin structure may be reduced compared to a one-sided cavity etch, although the gate cavities are formed using a one-sided cavity etch. This may further facilitate control of channel length in the finished FET device.

According to some embodiments, the source and drain cavities may be etched to extend partly into the third fin part and/or the gate cavities may be etched to extend partly into the first and second fin parts.

Thereby, that the source cavities and the gate cavities may be formed to present a partial overlap as viewed along a vertical direction, and such that drain source cavities and the gate cavities present a partial overlap as viewed along the vertical direction.

This facilitates forming the gate prongs and source/drain prongs to, in a pairwise manner, overlap a first/second common region of each channel layer. The gate body may hence, in use of the FET device, be configured to, when the FET device is switched to an active state, induce, in each channel layer, an electrostatic doping in the first and second common regions and a channel region extending therebetween. This may be referred to as a "dynamic doping". The first and second common regions may have a respective first doping level when the FET device is inactive, and a respective electrostatically increased second doping level when the FET device is active. Thereby, the doping concentration in the first and second common regions of each channel layer may be effectively increased. A further function of the spacer in a conventional FET is to limit the amount of dopant diffusion into the channel region. The "dynamic doping" allows reducing chemical source and drain doping concentration, further reducing the need for a spacer. In other words, a lower (chemical) doping level of the first and second common regions of each channel layer may hence be used than for the (typically highly chemically doped) source and drain regions of the conventional FET. This may in turn reduce the degradation of the sub-threshold-swing (SS) as the gate length scales down. Moreover, a channel region may be induced to extend completely between the first and second common regions, thereby enabling a reduced short-channel effect (SCE) when down-scaling.

According to embodiments, the method may further comprise subjecting the first and second fin parts to an ion implantation process while masking the third fin part from the ion implantation process. Doping of the third fin part may hence be counteracted while doping of the first and second parts may be allowed. Forming the set of source cavities and the set of drain cavities may accordingly comprises selectively etching doped first layer material. Correspondingly, forming the set of gate cavities may comprise selectively etching non-doped second layer material.

By virtue of the ion implantation process, a longitudinal etch contrast / etch selectivity may be introduced in the layers. Thereby, a tendency of an isotropic etching of the first non-channel layers causing a curved or rounded etch front may be reduced. More specifically, the variable doping concentrations enables a reduced etch rate of the un-doped versus doped portions, or vice versa during the cavity etches.

Correspondingly, according to embodiments comprising forming second cavities in the first and second fin parts, as set out above, the forming of the second cavities may comprise selectively etching doped second layer material of the first and second fin parts.

According to embodiments for forming the second type of FET device, the non-channel layers may be of a first layer material and the channel layers may be of a channel material.

Accordingly, the etching of the first fin part and the second fin part to form the source and drain cavities may comprise selectively etching the channel material (e.g. etching the channel material selectively to the first layer material). Forming the set of gate cavities may comprise selectively etching the first layer material (e.g. etching the first layer material selectively to the channel material).

The first layer material may be a first dielectric material. Each gate prong may hence be formed between a respective pair of (dielectric) first layer portions.

The sacrificial material hereby refers to a semiconductor material different from each of the channel material and the first dielectric material.

Replacing the sacrificial layers with the non-channel layers may comprise:.

According to embodiments, the method may further comprise subjecting the first and second fin parts to an ion implantation process while masking the third fin part from the ion implantation process. Doping of the third fin part may hence be counteracted while doping of the first and second parts may be allowed. Forming the set of source cavities and the set of drain cavities may accordingly comprise selectively etching doped channel material. Correspondingly, forming the set of gate cavities may comprise selectively etching non-doped portions of the first layer material (e.g. the first dielectric).

By virtue of the ion implantation process, a longitudinal etch contrast / etch selectivity may be introduced in the layers. Thereby, a tendency of an isotropic etching of the second sacrificial layers causing a curved or rounded etch front may be reduced. More specifically, the variable doping concentrations enables a reduced etch rate of the un-doped versus doped portions, or vice versa during the cavity etches.

In the following, embodiments of methods for forming a FET device of either of a first or second type will be described with reference to the drawings. More specifically, method embodiments for forming a FET device of the first type will be described with reference to <FIG> through <FIG>. Method embodiments for forming a FET device of the second type will be described with reference to <FIG> through <FIG>.

<FIG> shows in a schematic perspective view a FET device <NUM> of the first type. The FET device <NUM> comprises a substrate <NUM>, a source body <NUM>, a drain body <NUM>, and a set of vertically spaced apart semiconductor channel layers, e.g. in the shape of nanosheets, commonly referenced <NUM>. The channel layers <NUM> are stacked above each other. The channel layers <NUM> extend between the source body <NUM> and the drain body <NUM> in a first horizontal direction (denoted X in the figures) along the substrate <NUM>. The first horizontal direction X corresponds to a channel direction of the FET device <NUM>, i.e. a direction along which current flows between the source and drain bodies <NUM>, <NUM> when the FET device <NUM> is in an active state.

The substrate <NUM> may be a semiconductor substrate, i.e. a substrate comprising at least one semiconductor layer, e.g. of Si, SiGe or Ge. The substrate <NUM> may be a single-layered semiconductor substrate, for instance formed by a bulk substrate. A multi-layered / composite substrate <NUM> is however also possible, an epitaxially grown semiconductor layer on a bulk substrate, or a semiconductor-on-insulator (SOI) substrate. The substrate <NUM> of <FIG> is covered by an insulating layer <NUM> (e.g. silicon oxide or other conventional inter-layer dielectric material) which however may be omitted if the top surface of substrate <NUM> already is insulating.

The source body <NUM> comprises a common source body portion <NUM> and a set of vertically spaced apart source prongs <NUM> (vertical direction denoted Z in the figures) protruding from the common source body portion <NUM> in a second horizontal direction (denoted Y in the figures) transverse to the first horizontal direction X. The drain body <NUM> comprises a common drain body portion <NUM> and a set of vertically spaced apart drain layer prongs <NUM> protruding from the common drain body portion <NUM> in the second horizontal direction Y. The gate body <NUM> comprises a common gate body portion <NUM> and a set of vertically spaced apart gate prongs <NUM>. Each gate prong <NUM> protrudes from the common gate body portion <NUM> in a third horizontal direction (opposite/negative Y) into a space above or underneath a respective one of the channel layers <NUM>.

The common source body portion <NUM> and the common drain body portion <NUM> are both arranged at a first lateral side of the set of channel layers <NUM>. The common gate body portion <NUM> is arranged at a second lateral side of the set of channel layers <NUM>, opposite the first lateral side. <FIG> indicates a geometrical plane A. The plane A is a vertically oriented plane (i.e. parallel to the XZ-plane) and extends through the set of channel layers <NUM> along the first horizontal / channel direction X. The common source and drain body portions <NUM>, <NUM> and the common gate body portion <NUM> are accordingly arranged at mutually opposite sides of the plane A, thereby establishing a lateral / horizontal offset between the common source and drain body portions <NUM>, <NUM> and the common gate body portion <NUM>.

Each channel layer <NUM> is arranged in abutment with and extends in the X direction between a respective pair of a source prong <NUM> and a drain prong <NUM>, e.g. the source and drain prong <NUM>, <NUM> being arranged at a same vertical level over the substrate <NUM>. Each channel layer <NUM> comprises a first side arranged in abutment with the respective pair of source and drain prongs <NUM>, <NUM>, and a second side opposite the first side and facing a respective gate prong <NUM>. More specifically, each channel layer <NUM> may as shown either be arranged with the first side (e.g. an underside of the channel layer) in abutment with a respective topside of a pair of source and drain prongs <NUM>, <NUM>, or with the first side (e.g. a topside of the channel layer) in abutment with a respective underside of a pair of source and drain prongs <NUM>, <NUM>. As may be appreciated from <FIG>, a topside of a source or drain prong <NUM>, <NUM>, or a channel layer <NUM> may refer to a side of a prong / channel layer facing away from the substrate <NUM> while an underside may refer to a side of a prong / channel layer facing the substrate <NUM>.

The source and drain bodies <NUM>, <NUM> may be semiconductor bodies, e.g. comprising semiconductor common body portions <NUM>, <NUM> and semiconductor source/drain prongs <NUM>, <NUM>. Epitaxially grown group IV (e.g. Si, Ge, SiGe) and group III-V (e.g. InP, InAs, GaAs, GaN) semiconductors are a few possible examples. The source and drain bodies <NUM>, <NUM> may alternatively be metal bodies wherein the common source and drain body potions <NUM>, <NUM> may be formed of metal and the source and drain prongs <NUM>, <NUM> may be formed of metal. Example metals include W, Al, Ru, Mo or Co. The source and drain bodies <NUM>, <NUM> may in this case additionally comprise a barrier metal layer, e.g. Ta, TiN or TaN, enclosing a bulk material of the respective bodies <NUM>, <NUM> (such as any of the afore-mentioned metals). The source and drain bodies <NUM>, <NUM> may also be combined metal and semiconductor bodies, e.g. comprising metal and semiconductor common body portions <NUM>, <NUM> and semiconductor source and drain prongs <NUM>, <NUM> (e.g. epitaxially grown). Such a configuration is depicted in <FIG> wherein the common source body portion <NUM> is shown to abut and enclose faceted (dashed lines) ends of the semiconductor source prongs <NUM>. The shape of the facets is merely exemplary and will generally depend on the lattice structure of the semiconductor material and growth conditions of the epitaxy. As may be appreciated, semiconductor source and drain bodies <NUM>, <NUM> may be obtained by continuing the growth such that the growth fronts of the source prongs <NUM> and drain prongs <NUM>, respectively, merge to form the common source and drain body portions <NUM>, <NUM>. The source and drain prongs <NUM>, <NUM> (and the common source and drain bodies <NUM>, <NUM> if made of semiconductor material) may each be doped (e.g. in-situ during epitaxy) with a dopant appropriate for the intended type of the device (e.g. n-type FET or p-type FET).

The thickness of the source and drain prongs <NUM>, <NUM> may for example be in the range of <NUM> to <NUM>. As may be appreciated, thinner prongs may enable stacking of more channel layers <NUM>, which may be advantageous as the total height of the full device stack typically is constrained. Conversely, thicker prongs may reduce resistance which means that the thickness of the prongs tend to be a trade-off.

The channel layers <NUM> may be formed as thin-film layers. Each channel layer may be formed by a 2D material such as a transition metal dichalcogenide (MX<NUM>) or IGZO. However, channel layers of semiconductor materials such as semiconductors of group IV (e.g. Si, Ge, SiGe) or group III-V (e.g. InP, InAs, GaAs, GaN) are also possible.

The gate body <NUM> may be a metal body. The common gate body <NUM> and the gate prongs <NUM> may be formed of metal. Example metals include one or more gate work function metal (WFM) layers and/or a gate electrode fill layer. Examples of gate WFM material include conventional n-type and p-type effect WFM metals, such as TiN, TaN, TiAl, TiAIC or WCN, or combinations thereof. Examples of gate fill material gate include W and Al. A gate dielectric layer <NUM> is provided, separating the gate body <NUM> from the channel layers <NUM> and the source and drain layer prongs <NUM>, <NUM>. The gate dielectric layer <NUM> may be a conventional gate dielectric of a high-k, such as HfO<NUM>, LaO, AIO and ZrO.

As further shown in <FIG>, a distal end 144e of each gate prong <NUM> may be separated from a respective side surface / sidewall surface <NUM>, <NUM> of the common source and drain body portions <NUM>, <NUM> by at least the thickness of the gate dielectric layer <NUM>. Further separation may be provided by a further (not shown) dielectric spacer. The thickness (along the Y direction) of the dielectric material may by way of example be about <NUM> or greater. Meanwhile, a distal end 124e of each source prong <NUM> (and correspondingly the distal end of each drain prong <NUM>) may be separated from a respective sidewall surface of the common gate body portion <NUM> by at least the gate dielectric <NUM> and possibly a further dielectric spacer. To accommodate for the respective dielectric separation, a horizontal separation, along the Y direction, between the common gate body portion <NUM> and the common source and drain body portions <NUM>, <NUM> may exceed a respective length of the gate prongs <NUM> and source/drain layer prongs <NUM>, <NUM>.

<FIG> additionally shows an insulating layer <NUM> or "insulating wall" separating the source body <NUM> from the drain body <NUM> along the X direction.

<FIG> additionally shows an insulating layer <NUM> delimiting a length dimension of the gate body <NUM> along the X direction. The insulating layer <NUM> may separate the gate body <NUM> from the gate body of a further FET device provided after and aligned with the device <NUM>, as viewed along the first horizontal direction X. A corresponding insulating layer may be provided at the source side. Accordingly, first and second dielectric layer portions (formed by the layer <NUM>) may be arranged in the spaces between the source and drain layer prongs <NUM>, <NUM> such that each gate prong <NUM> is arranged intermediate a respective pair of first and second dielectric layer portions (see portions 164a, b in <FIG>). The insulating layers <NUM> and <NUM> may each be formed of an oxide or nitride, such as SiO<NUM>, SiN, SiCBN, SiCON or SiCO.

<FIG> shows in a schematic perspective view a FET device <NUM> of the second type. The definition of the axes X, Y and Z indicated in <FIG> correspond to those provided in <FIG>. Although omitted from <FIG>, the FET device <NUM> may comprise a substrate similar to any of the examples of substrates provided in connection with <FIG>.

The device <NUM> comprises a source body <NUM>. The source body <NUM> comprises a common source body portion <NUM> and a set of vertically spaced apart source prongs <NUM> protruding from the common source body portion <NUM> along the Y direction. The device <NUM> further comprises a drain body <NUM>. The drain body <NUM> comprises a common drain body portion <NUM> and a set of vertically spaced apart drain prongs <NUM> protruding from the common drain body portion <NUM> along the Y direction. The source and drain prongs <NUM>, <NUM> may each be formed of semiconductor material, e.g. epitaxially grown semiconductor material, such as of Si or SiGe, and doped with n-type or p-type dopants, in accordance with the conductivity type of the device <NUM>. The common source and drain body portions <NUM>, <NUM> may each comprise or be formed of semiconductor material. The common source and drain body portions <NUM>, <NUM> may e.g. be formed as respective epitaxial semiconductor body portions, such as of a same material as the source and drain layer prongs <NUM>, <NUM>. The common source and drain body portions <NUM>, <NUM> may alternatively be formed as metal-comprising body portions, in contact with and merging the source and drain prongs <NUM>, <NUM>, respectively. The common body portions <NUM>, <NUM> may for example be formed of W, Al, Ru, Mo or Co. The common body portions <NUM>, <NUM> may further comprise a barrier metal layer, e.g. Ta or TaN.

The device <NUM> comprises a set of vertically spaced apart channel layers <NUM>. Each channel layer <NUM> extends horizontally (along the Y direction) between a respective pair of source and drain prongs <NUM>, <NUM>. The source and drain prongs <NUM>, <NUM> and the channel layers <NUM> may each be formed with a nanosheet-shape. The channel layers <NUM> may be formed of a semiconductor, such as a Si-comprising semiconductor. The channel layer <NUM> may for example be formed Si or SiGe layers. These materials are however only examples and it is contemplated that also other semiconductors may be used, such as Ge.

The device <NUM> further comprises a gate body <NUM> comprising a common gate body portion <NUM> and a set of vertically spaced apart gate prongs <NUM>. The gate prongs <NUM> protrude from the common gate body portion <NUM> in a direction opposite to the source and drain prongs <NUM>, <NUM>, i.e. along the negative Y direction. The gate prongs <NUM> extend to overlap the channel layers <NUM> such that the channel layer portions <NUM> are arranged in spaces between the gate prongs <NUM>.

Dielectric layer portions <NUM>, <NUM> are arranged in the spaces between the source and drain prongs <NUM>, <NUM>, respectively. Each gate prong <NUM> is thus formed (horizontally) intermediate a respective pair of dielectric layer portions <NUM>, <NUM>. The dielectric layer portions <NUM>, <NUM> may comprise an oxide or a nitride material, such as SiGeOx, SiO<NUM>, SiN or SiCO.

As shown in <FIG>, the common source and drain body portions <NUM>, <NUM> and the common gate body portion <NUM> are accordingly arranged at mutually opposite sides of a geometrical vertical plane P, wherein the plane P is defined to extend through the channel layers <NUM> and source and drain prongs <NUM>, <NUM>. Accordingly, the first type of FET device <NUM> and the second type of FET device <NUM> have as a common feature a common gate body portion <NUM>/<NUM> arranged at a laterally opposite side to the common source and drain body portions <NUM>/<NUM>, <NUM>/<NUM>. Additionally, the gate prongs <NUM>, <NUM> are offset vertically with respect to the source and drain prongs <NUM>/<NUM>, <NUM>/<NUM>. As discussed above, this design enables further CPP scaling (the CPP of device <NUM> being indicated in <FIG>). The CPP of the devices <NUM>, <NUM> may by way of example be in the range of <NUM> to <NUM>.

However, while the source and drain prongs <NUM>, <NUM> of the FET device <NUM> are level with the channel layers <NUM>, the source and drain prongs <NUM>, <NUM> of the FET device <NUM> are offset vertically from both the gate prongs <NUM> and the channel layers <NUM>. This facilitates a device design wherein a gate prong <NUM> and a source or drain prong <NUM>, <NUM> may be arranged to overlap with a common region of a channel layer such that the first common region is located vertically between the source or drain prong and the gate prong. Such an overlap may be more readily seen in <FIG> which is a cross-sectional view of the device <NUM>, showing a portion of a section taken along plane A and comprising a pair of source and drain prongs 124a, 134a and a pair of channel layers 150a, 150b. The pair of channel layers 150a, 150b are arranged in abutment / direct contact with the pair of source and drain prongs 124a, 134a from mutually opposite sides, such that the pair of prongs 124a, 134a are sandwiched between the pair of channel layers 150a, 150b. The pair of source and drain prongs 124a, 134a and the pair of channel layers 150a, 150b are in turn arranged in a space between a pair of gate prongs 144a, 144b.

The channel layer 150a (representing a lower channel layer of the pair) comprises a first side 150aa (e.g. forming a topside of the channel layer 150a) arranged in abutment with an underside 124aa of the source prong 124a and an underside 134aa of the drain prong 134a. The channel layer 150a comprises a second side 150ab (e.g. forming an underside of the channel layer 150a), oppositely oriented with respect to the first side 150aa, and facing a gate prong 144a. The gate prong 144a extends along the second side 150ab, i.e. in the X direction. The gate dielectric layer 146a is sandwiched between the gate prong 144a and the channel layer 150a. Correspondingly, the channel layer 150b comprises a first side 150ba (e.g. forming an underside of the channel layer 150b), arranged in abutment with a topside 124ab of the source prong 124a and a topside 134ab of the drain prong 134a. The channel layer 150b comprises a second side 150bb (e.g. forming a topside of the channel layer 150b), oppositely oriented with respect to the first side 150ba, and facing a gate prong 144b. The gate prong 144b extends along the second side 150bb, i.e. in the X direction. The gate dielectric layer 146b is sandwiched between the gate prong 144b and the channel layer 150b. Further shown in <FIG> is a spacer layer <NUM> arranged level with and between the pair of source and drain prongs 124a, 134a. The spacer layer <NUM> may be formed as an insulating layer such that the channel layers 150a, 150b may be electrically insulated from each other along the length of their respective channel regions 150ac, 150bc.

As indicated by the dashed line boxes in <FIG>, the gate prong 144a and the source prong 124a may be arranged to overlap with a first common region 150as of the channel layer 150a such that the first common region 150as is located vertically between the source prong 124a and the gate prong 144a. Moreover, the gate prong 144a and the drain prong 134a may as shown be arranged to overlap with a second common region 150ad of the channel layer 150a, such that that the second common region 150ad is located vertically between the drain prong 134a and the gate prong 144a. Lov (also shown in <FIG>) indicates the length of the common overlap regions 150as, 150ad, as seen along the X direction. The common overlap regions 150as, 150ad allows dynamic doping of the channel layers 150a, 150b during operation of the device <NUM>, as described above. A corresponding configuration applies to the channel layer 150b wherein the gate prong 144b and the source prong 124a (drain prong 134a) are arranged to overlap with a first (second) common region of the channel layer 150b such that the first (second) common region is located vertically between the source prong 124a (drain prong 134a) and the gate prong 144a. Accordingly, also the channel layer 150b may like the channel layer 150a be dynamically doped during operation of the device <NUM>.

The channel layers <NUM> may be formed with a uniform intrinsic doping level. Doping diffusion which may result during chemical doping may hence be mitigated. However, the channel layers <NUM> abutting the source and drain prongs <NUM>, <NUM> may also be chemically doped to enable even greater source/drain doping concentrations in the active state and reduced contact resistance (e.g. with respect to the common source/drain body portions <NUM>, <NUM>).

As an example, an intrinsic doping level of the channel layers <NUM> may be <NUM><NUM> cm-<NUM> to <NUM><NUM> cm-<NUM>, while a chemical (i.e. non-electrostatic) doping may e.g. be in the magnitude of <NUM><NUM> cm-<NUM>. The thickness (i.e. as seen along the vertical Z direction) of the channel layers <NUM> may, depending e.g. on the material selection, be about <NUM> or less. For example, a thickness in the range from <NUM> to <NUM> may be used for Si-, SiGe- or Ge- channel layers <NUM>, while <NUM> or less may be appropriate for thin-film layers. If the thickness of the channel layers <NUM> is sufficiently low, the gate <NUM> may induce a channel though the entire thickness of the channel layers <NUM>.

In <FIG>, the overlap length Lov is the same on the source and the drain side, and also for the channel layers 150a and 150b, but it is contemplated that the lengths Lov of the common overlap regions may be different from each other, e.g. due to process variations etc..

The overlap length Lov may for example be in the range from <NUM> (or less) to <NUM> (or greater). However, a zero overlap length (Lov = <NUM>) is also envisaged. Such a configuration may be used e.g. in case dynamic doping is not desired or necessary, or in case a sufficiently strong dynamic doping is induced already by a fringing electrical field of the gate body. Regardless of the particular value of the overlap length Lov, the design of the device <NUM> allows a reduced CPP (indicated in <FIG>) compared to conventional finFET and nanosheet-based devices.

Embodiments of methods for forming a FET device of the first type, e.g. the FET device <NUM>, will now be described with reference to <FIG> through <FIG>.

<FIG> through <FIG> depict method steps for forming a fin structure which may be used as a precursor for the subsequent method steps for completing the FET device, as depicted in <FIG> through <FIG>.

Reference will in the following be made to a first fin part <NUM>, a second fin part 1010d and a third fin part 1010c of a fin structure <NUM>, intermediate the first and second fin parts <NUM>, 1010d (e.g. <FIG>). The first fin part <NUM> corresponds to a part of the fin structure <NUM> located in a source region of the FET device to be formed. The second fin part 1010d corresponds to a part of the fin structure <NUM> located in a drain region of the FET device to be formed. The third fin part 1010c corresponds to a part of the fin structure <NUM> located in a gate region of the FET device to be formed.

The following description will mainly refer to processing steps applied to one set of such first, second and third fin parts <NUM>, 1010d, 1010c, to enable forming of one FET device along a fin structure <NUM>. However, corresponding processing steps may be applied to a number of such sets of fin parts along the fin structure <NUM> to allow forming of a number of corresponding FET devices along a same fin structure <NUM>.

As will be described in further detail, the method comprises etching each of the first and the second fin part <NUM>, 1010d of the fin structure <NUM> laterally from a first side 1010a and second side 1010b such that a set of source cavities and a set of drain cavities <NUM> are formed in the first fin part <NUM> and the second fin part 1010d, respectively (e.g. <FIG> through 17a-b). The cavities <NUM> are filled with a dummy material <NUM> (e.g. <FIG> through <FIG>). The dummy material <NUM> is then removed from the cavities <NUM> while masking the fin structure from the second side 1010b (e.g. <FIG>). Subsequently, a source body <NUM> and a drain body 1120d are formed, each comprising a respective common body portion <NUM> along the first side 1010a and a set of prongs <NUM> protruding from the respective common body portion into the source and drain cavities <NUM>, respectively (e.g. <FIG>). The method further comprises etching the third fin part 1010c laterally from the second side 1010b such that a set of gate cavities <NUM> is formed in the third fin part 1010c (e.g. <FIG>). Subsequently, a gate body <NUM> is formed comprising a common gate body portion <NUM> along the second side and a set of gate prongs <NUM> protruding from the common gate body portion into the gate cavities <NUM> (e.g. <FIG>).

<FIG> depict cross sections of a layer stack <NUM> along respective vertical planes C-C' and A-A'. The layer stack <NUM> is formed on a substrate <NUM>. The substrate <NUM> may e.g. be a substrate in accordance with any of the examples provided in connection with substrate <NUM> of <FIG>. The layer stack <NUM> comprises an alternating sequence of sacrificial layers <NUM>, <NUM> and channel layers <NUM>, wherein the sacrificial layers <NUM>, <NUM> are alternatingly first sacrificial layers <NUM> and second sacrificial layers <NUM>. The second sacrificial layers <NUM> may also be denoted "second non-channel layers".

Each layer <NUM>, <NUM>, <NUM> may be formed as a layer of epitaxial (i.e. epitaxially grown/formed/deposited) semiconductor material. The layers <NUM>, <NUM>, <NUM> may be grown on the substrate <NUM> in an epitaxy process, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).

According to the illustrated example, each first sacrificial layer <NUM> is formed of a first semiconductor material, each second sacrificial layer <NUM> is formed of a second semiconductor material, and each channel layer <NUM> is formed of a third semiconductor material. The first through third semiconductor materials hereby refers to different semiconductor materials, e.g. different epitaxial semiconductor materials. The first semiconductor material may also be denoted "sacrificial semiconductor material". The second semiconductor material may also be denoted "second layer material". The third semiconductor material may also be denoted "channel material".

The first through third semiconductor materials may be chosen to provide an etch contrast between the layers <NUM>, <NUM>, <NUM>. The materials may in particular be chosen to facilitate selective removal of the first sacrificial layers <NUM> to the channel layers <NUM> and the second sacrificial layers <NUM>, and subsequently selective removal of the second sacrificial layers <NUM> to the channel layers <NUM>. The term "selective" in connection with "removal" or "etching" of a layer or a material is herein to be understood as a removal of the layer or the material by a selective etching process, wherein a removal rate / etch rate of the layer or the material to be selectively removed / etched exceeds a removal rate / etch rate of at least one other layer or material exposed to the etching process.

According to some examples, the channel layers <NUM> may be formed of SiGex, the second sacrificial layers <NUM> may be formed of SiGey and the first sacrificial layers <NUM> may be formed of SiGez, with <NUM> ≤ x < y < z. The compositions of the first and second sacrificial layers <NUM>, <NUM> may more specifically be y = x + d<NUM> and z = y + d<NUM> with d<NUM>, d<NUM> ≥ <NUM>. These relative proportions of Ge content may facilitate an efficient selective removal. According to some examples, the channel layers <NUM> may be formed of Si (i.e. SiGex=<NUM>), the second sacrificial layers <NUM> may be formed of SiGe<NUM> and the first sacrificial layers <NUM> may be formed of SiGe<NUM>. More generally, the layers <NUM>, <NUM>, <NUM> may be formed of any combination of semiconductor materials compatible with the subsequent selective processing steps to be described. For example, the first and second sacrificial layers <NUM>, <NUM> may be SiGe layers as set out above while the channel layers <NUM> may be thin-film layers, e.g. formed by a 2D material such as a transition metal dichalcogenide (MX<NUM>) or IGZO. Such a stack may be formed using e.g. CVD or layer transfer techniques as per se is known in the art. According to a further example, the layers <NUM>, <NUM>, <NUM> may be formed of different group III-V semiconductor material.

The number of layers of the depicted layer stack <NUM> is merely an example and the number may be smaller or greater than depicted. As may be appreciated from the following, the number of layers of the layer stack <NUM> may be selected in accordance with the number of layers, source/drain prongs and gate prongs desired in the finished FET device (c. e.g. channel layers <NUM>, source/drain prongs <NUM>/<NUM> and gate prongs <NUM> of the device <NUM>).

According to some examples, the layer stack <NUM> may comprise, e.g. one or more units of (in the illustrated example one such unit), a consecutive sequence of a (lower) second sacrificial layer <NUM>, a (lower) channel layer <NUM>, a first sacrificial layer <NUM>, a(n) (upper) channel layer <NUM> and a(n) (upper) second sacrificial layer <NUM>. This facilitates forming a FET device comprising a pair of gate prongs, and between the gate prongs, a pair of source and drain prongs and a pair of channel layers in abutment with the pair of source and drain prongs.

In <FIG> the layer stack <NUM> has been patterned to form a number of fin structures <NUM>. A longitudinal dimension, a width dimension, and a height dimension of each fin structure <NUM> is respectively oriented along a first horizontal direction X, a second horizontal direction Y and a vertical direction Z, in relation to the substrate <NUM>. Each fin structure <NUM> comprises a fin-shaped layer stack comprising an alternating sequence of layers corresponding to the alternating sequence of the layer stack <NUM>. That is, each fin structure <NUM> comprises an alternating sequence of sacrificial layers <NUM>, <NUM> and channel layers <NUM>, wherein the sacrificial layers <NUM>, <NUM> are alternatingly first sacrificial layers <NUM> and second sacrificial layers <NUM>. The layers <NUM>, <NUM>, <NUM> may be patterned to define corresponding nanosheets of each fin structure <NUM>, and may accordingly be referred to as sacrificial nanosheets <NUM>, <NUM> and channel nanosheets <NUM>. Reference signs 1010a and 1010b denote respectively a first side of the fin structure <NUM> and a laterally opposite second side of the fin structure <NUM>. Reference may in the following also be made to a first/second side surface of the fin structure, which term is to be understood as a (physical) surface of the first/second side 1010a/1010b of the fin structure <NUM>. For convenience, reference signs 1010a, 1010b may be used to refer to either the first/second sides or the first/second side surfaces of the fin structure <NUM>, in accordance with the context.

The layer stack <NUM> may as shown be patterned by etching the layer stack <NUM> while using a mask <NUM> (which may be denoted "fin patterning mask <NUM>" and also is shown in <FIG>) as an etch mask. Example etching processes for the fin patterning include anisotropic etching (top-down) like reactive ion etching (RIE). The etching of the layer stack <NUM> may as shown extend into the substrate <NUM>. The substrate <NUM> may thus be recessed adjacent the fin structures <NUM> such that a base portion of each fin structure <NUM> is formed in the substrate <NUM>. Recessing the substrate <NUM> in this manner may accommodate for a thicker bottom isolation underneath the source, drain and gate bodies.

The mask <NUM> may be formed by a mask material deposited on the layer stack <NUM> and then patterned. Example mask materials include nitride materials such as SiN, or another conventional hard mask material suitable for fin patterning, e.g. SiO<NUM> or a-Si. Example patterning techniques for the mask <NUM> include single-patterning techniques, e.g. lithography and etching, and multiple patterning techniques, e.g. self-aligned double or quadruple patterning (SADP or SAQP).

The figures depict the mask <NUM> as comprising two mask portions, commonly referenced <NUM>, such that two fin structures <NUM> may be formed. The two fin structures <NUM> may for example be used to form a complementary pair of FET devices, e.g. an n-type FET and a p-type FET as depicted in <FIG>. As may be appreciated, mask portions may however be formed in a number corresponding to the number of fin structures <NUM> to be formed. In any case, a mask portion <NUM> may remain on each fin structure <NUM> as a capping during subsequent stages of the method.

Reference will in the following mainly be made to one fin structure <NUM> however the following description applies correspondingly to any further fin structures.

In <FIG> a cover material has been deposited to form a liner <NUM> along the first and second sides 1010a, 1010b of the fin structure <NUM>, in particular on the first and second side surfaces 1010a, 1010b of the fin structure <NUM>. A fill layer <NUM> has further been formed, embedding the fin structure <NUM>. The fill layer <NUM> may also be denoted "process layer". The liner <NUM> may be formed of a dielectric material, e.g. an oxide such as SiO<NUM>, or a nitride such as SiN or another low-k dielectric such as SiCO. The liner <NUM> may be conformally deposited, e.g. using atomic layer deposition (ALD). The liner <NUM> may among others mask the fin structure <NUM> from subsequent process steps, such as the formation of the fill layer <NUM>. The fill layer <NUM> may be formed of a fill or process material in the form of a dielectric, e.g. an oxide such as SiO<NUM>. The fill layer <NUM> may be deposited over the substrate <NUM>, e.g. using CVD, to embed the fin structure <NUM>. For example, the fill layer <NUM> may be formed of flowable CVD (FCVD) SiO<NUM>. After the deposition the fill layer <NUM> may be planarized, e.g. using Chemical Mechanical Planarization (CMP). As shown in <FIG>, the fill layer <NUM> may further be recessed (e.g. by CMP or etch-back) to become flush with an upper surface of the mask portion <NUM>, or alternatively an upper surface of the fin structure <NUM> if the mask portion <NUM> is removed. According to some examples, a further recessing may however be omitted such that the fin structure <NUM> (and mask portion <NUM>) remains completely covered by the fill layer <NUM>. According to some examples, the fill layer <NUM> may also be formed by a self-planarizing spin-on layer, e.g. an organic spin-on layer such as spin-on-carbon (SOC), thus obviating the need for a CMP step after deposition.

In <FIG> a trench <NUM> has been formed alongside the fin structure <NUM> to expose the fin structure <NUM> from the second side 1010b. In particular, the trench <NUM> is formed selectively along the second side 1010b of the fin structure <NUM>, i.e. along the second side 1010b but not along the directly opposite first side 1010a of the fin structure <NUM>. As shown, the trench <NUM> may be formed by etching the fill layer <NUM> through an opening in a mask <NUM> (a "trench etch mask <NUM>") formed over the fill layer <NUM> and the fin structure <NUM>. More specifically, the opening may be defined to extend over and along the second side 1010b but not the first side 1010a of the fin structure <NUM>. The mask <NUM> may for example be formed by a suitable hard mask material (e.g. oxide or nitride), wherein the opening may be defined by lithography and etching. Example etching processes for forming the trench <NUM> include anisotropic etching (top-down) like RIE as well as isotropic (wet or dry) etching.

Depending on an etch contrast between the liner <NUM> and the fill layer <NUM> the liner <NUM> may be removed from the second side surface 1010b during the etching of the fill layer <NUM>, or thereafter using a separate dedicated (e.g. isotropic) etch step.

The trench <NUM> allows the first sacrificial layers <NUM> to be accessed from the trench <NUM> and etched laterally and selectively to the second sacrificial layers <NUM> and the channel layers <NUM>. This is reflected in <FIG> wherein the first sacrificial layers <NUM> have been removed from the fin structure <NUM> to form a set of longitudinal gaps or cavities <NUM> in the fin structure <NUM> at locations previously occupied by the first sacrificial layers <NUM>. The first sacrificial layers <NUM> may e.g. be removed from the fin structure <NUM> by selective etching of the first semiconductor material to the second and third semiconductor material. A (wet or dry) isotropic etching process may be used. For example, selective etching of SiGe, to SiGex and SiGey (with <NUM> <= x < y < z) may be achieved using an HCl-based dry etch, wherein a greater difference in Ge-content among the layers <NUM>, <NUM>, <NUM> may confer an increased etch contrast. A further example is selective etching using an ammonia-peroxide mixture (APM). However, other etching processes allowing selective etching of higher Ge-content SiGe-material to lower Ge-content SiGe layers (and Si-layers) are per se known in the art and may also be employed for this purpose.

To facilitate removal of the first sacrificial layers <NUM> along its full length the trench <NUM> may be formed to expose the side surface 1018b of the fin structure <NUM> along the full longitudinal dimension thereof.

The liner <NUM> and the fill layer <NUM> may form a support structure supporting or tethering the fin structure <NUM>, thus counteracting collapse of the fin structure <NUM> during and after the removal of the first sacrificial layers <NUM>. As shown in <FIG>, the mask <NUM> may remain when forming the gaps <NUM>. However, according to alternative examples the mask <NUM> may be removed, wherein the liner <NUM> and the fill layer <NUM> on their own may support the fin structure <NUM> during removal of the first sacrificial layers <NUM>.

The trench <NUM> may as shown be formed at a position between the pair of fin structures <NUM> to expose the mutually facing side surfaces thereof. The sacrificial layers <NUM> may hence be removed from two adjacent fin structures <NUM> using a same trench <NUM>.

In <FIG> first dielectric layers <NUM> (e.g. also in the shape of nanosheets) have been formed in the gaps <NUM> by filling the cavities with a dielectric material. The first dielectric layers <NUM> may also be denoted "first non-channel layers". The dielectric material may e.g. be an oxide or a nitride material, such as SiO<NUM> or SiN or (low-k). Further examples include SiCO, SiOCN, SiCN, SiON, SiBCN and SiBCNO. To facilitate subsequent selective processing steps, to be described below, the first dielectric layers <NUM> may be formed of a different material than the liner <NUM>. For example, the liner <NUM> may be formed of a nitride (e.g. SiN) and the first dielectric layers <NUM> may be formed of an oxide (e.g. SiO<NUM>). The dielectric material may be conformally deposited, e.g. using atomic layer deposition (ALD), such that the gaps <NUM> are completely filled with the dielectric material. The deposition may be followed by an etch step (wet or dry, isotropic or anisotropic top-down) to remove dielectric material deposited outside the gaps <NUM>.

After forming the first dielectric layers <NUM> the cover material of the liner <NUM> may as shown be re-deposited along the second side 1010b (e.g. by ALD). The mask <NUM> may for example be removed prior to forming the first dielectric layers <NUM>, or subsequent thereto and prior to re-depositing the liner <NUM>.

After removing the mask <NUM>, the fill layer <NUM> may be etched back to expose the liner <NUM> along the first side 1010a, thus arriving at the structure shown in <FIG>. According to some examples, the fill layer <NUM> may instead be completely removed / etched-back and a dielectric material (e.g. SiO<NUM>) may be (re-deposited) to serve as a bottom dielectric layer.

As may be appreciated from the following, the first dielectric layers <NUM> may be used to form dielectric spacers between pairs of source and drain prongs and additionally passivate surfaces of the channel layers <NUM> of the finished FET device. Replacing the first (semiconductor) sacrificial layers <NUM> by the first dielectric layers <NUM> may additionally enable an increased etch selectivity among the layers of the fin structure <NUM>, thus facilitating subsequent process steps.

<FIG> and <FIG> and <FIG> depict process steps which may be performed to additionally introduce a longitudinal etch contrast / etch selectivity in the layers <NUM>, <NUM>, <NUM> by using an ion implantation process to introduce variable etch properties along the longitudinal dimension. More specifically, as will be set out below the ion implantation process may be adapted to introduce an increased concentration of dopants in each of the first fin part <NUM> and the second fin part 1010d, compared to the third fin part 1010c.

In <FIG> an ion implantation mask <NUM> has been formed across the fin structure(s) <NUM> to alternatingly define masked regions <NUM> and non-masked regions <NUM> along the fin structure <NUM>. The extension of the non-masked regions <NUM> are indicated by dashed bounding boxes. As indicated in <FIG>, one of the masked regions <NUM> is defined to overlap / comprise the third fin part 1010c, while a pair of the non-masked regions <NUM> are defined to overlap / comprise the first and second fin parts <NUM>, 1010d.

The masked regions <NUM> correspond to source/drain regions of the FET to be formed, i.e. regions in which source/drain bodies will be formed. The masked regions <NUM> correspond to the gate regions of the FET to be formed, i.e. regions in which gate bodies will be formed. Owing to this correspondence, each region <NUM> may in the following be denoted "gate region <NUM>", and each region <NUM> may be denoted "source/drain region <NUM>". In other words, the ion implantation mask <NUM> is defined to mask each gate region <NUM> and expose each source/drain region <NUM>.

As depicted in the figures, the mask <NUM> may comprise a number of mask portions, commonly referenced <NUM>, to define a number of masked and non-masked regions <NUM> such that ion implantation may be counteracted in a number of regions or fin parts like 1010c. The mask <NUM> may be formed of one or more layers of a hardmask material, for example a nitride-comprising hardmask such as SiN or a-Si. However, any conventional material suitable to form part of an ion implantation mask may be used. The mask <NUM> may be patterned using single- or multi-patterning techniques.

In <FIG> the fin structure <NUM> has been subjected to an ion implantation process (schematically indicated "I") wherein the first dielectric layers <NUM>, the second sacrificial layers <NUM> and the channel layers <NUM> have been provided with an increased concentration of dopants in the non-masked (source/drain) regions <NUM> compared to the masked (gate) regions <NUM>. Accordingly, the first and second fin parts <NUM>, 1010d have been provided with an increased concentration of dopants compared to the third fin part 1010c. Any type of ion implant affecting the etch rate in the intended manner may be used.

<FIG> depict a cross section of the fin structure(s) <NUM> along the vertical plane B-B' indicated in <FIG> after the liner <NUM> has been partially opened to expose each of the first and second fin parts <NUM>, 1010d from each of the first and second sides 1010a, 1010b. The third fin part 1010c remains covered from each of the first and second sides 1010a, 1010b. As shown, the liner <NUM> may be etched while using the mask <NUM> extending across the fin structure <NUM> as an etch mask. The side surfaces 1010a, 1010b of the fin structure <NUM> may thus be exposed in regions <NUM> not covered by the mask <NUM>. The liner <NUM> may be removed using an isotropic etching process, wet or dry. The cross section of <FIG> shows the second fin part 1010d but is representative also for the first fin part <NUM>.

In <FIG>, the "ion implantation mask" <NUM> is used also as an etch mask while removing the liner <NUM>. However, the mask <NUM> may according to other examples be removed after the ion implantation process and a new dedicated liner opening mask extending across the fin structure(s) <NUM> may be formed. The mask <NUM>, or the liner opening mask, may as shown be removed after opening the liner <NUM>. However the mask <NUM> may alternatively remain also during the subsequent etching of the second sacrificial layers <NUM> described below, to be removed thereafter.

The partially opened liner <NUM> may accordingly together with the capping <NUM> define a mask structure covering the fin structure <NUM> from both sides 1010a, 1010b in the gate regions <NUM> (e.g. the third fin part 1010c), and defining openings exposing the fin structure <NUM> from both sides 1010a, 1010b in the source/drain regions <NUM> (e.g. the first and second fin parts <NUM>, 1010d). The mask structure thus allows the second sacrificial layers <NUM> to be accessed and etched laterally and selectively to form cavities <NUM> in the source/drain regions <NUM>, e.g. in the first and second fin parts <NUM>, 1010d. This is reflected in <FIG> wherein portions of each second sacrificial layer <NUM> have been removed in regions <NUM> to form the cavities <NUM> by etching the second sacrificial layers <NUM> from both sides 1010a, 1010b. The cavities <NUM> may as shown extend completely through the fin structure <NUM>, along the Y direction. Portions of the channel layers <NUM> and first dielectric layers <NUM> may remain in the regions <NUM>, e.g. in the first and second fin parts <NUM>, 1010d. The liner <NUM> remaining in the regions <NUM> may provide additional support to the fin structure <NUM> during and after the forming of the cavities <NUM>. The second sacrificial layers <NUM> may be etched selectively to the first dielectric layers <NUM> and the channel layers (e.g. by selective etching of the second semiconductor material to the first dielectric material and the third semiconductor material). A (wet or dry) isotropic etching process may be used. For example, selective etching of SiGey to SiGex<y, SiO<NUM> and SiN may be achieved using an HCl-based dry etch or APM.

In <FIG>, second dielectric layers <NUM> (e.g. also in the shape of nanosheets) have been formed in the cavities <NUM> by filling the cavities <NUM> with a second dielectric material. The second dielectric material may e.g. be an oxide or a nitride material, such as any of the examples mentioned in connection with the liner <NUM>. The second dielectric layers <NUM> may in particular be formed of a same material as the liner <NUM>. To facilitate subsequent selective processing steps, to be described below, the second dielectric layers <NUM> may be formed of a different material than the first dielectric layers <NUM>. The (second) dielectric material may be conformally deposited, e.g. using ALD, such that the cavities <NUM> are completely filled with the dielectric material. Although not reflected in <FIG>, the deposition may be followed by an etch step (wet or dry, isotropic or anisotropic top-down) to remove dielectric material deposited outside the cavities <NUM>. If the second dielectric layers are formed of different material than the liner <NUM>, the liner <NUM> may be re-deposited along the sides of the fin structure <NUM>, e.g. using a separate ALD step.

<FIG> illustrate process steps for forming a respective source/drain body along each source/drain region <NUM> of the fin structure <NUM> (e.g. along the first and second fin parts <NUM>, 1010d). Each source/drain body may form either a source body <NUM> (e.g. corresponding to source body <NUM> of device <NUM>) or a drain body 1120d (e.g. corresponding to drain body <NUM> of device <NUM>). <FIG> includes the individual designations <NUM> and 1120d while subsequent figures for illustrational clarity include only the common designation <NUM>. Each source/drain body <NUM> may comprise a common semiconductor source/drain body portion <NUM> arranged at the first side 1010a of the fin structure <NUM>, and a set of vertically spaced apart semiconductor source/drain layer portions or prongs <NUM> protruding from the common source body portion <NUM> in the Y direction. In <FIG>, <FIG> and onwards the dashed bounding boxes indicating regions <NUM> have been omitted to not obscure the figures.

In <FIG> the liner <NUM> has been removed to expose the fin structure <NUM> from both sides 1010a, 1010b, along the entire longitudinal dimension of the fin structure <NUM>. The liner <NUM> may e.g. be removed using a wet or dry isotropic etch.

In <FIG> a cover material is deposited along the first and second sides 1010a, 1010b of the fin structure <NUM>, thereby forming mask layer or cover layer <NUM> embedding the fin structure <NUM>. The cover layer <NUM> may be formed by a suitable cover material, such as a self-planarizing spin-on layer, e.g. an organic spin-on layer such as SOC. An opening or trench <NUM> (e.g. "source/drain trench") is formed in the cover layer <NUM>, in each source/drain region <NUM> of the fin structure <NUM>, along each of the first side 1010a and the directly opposite second side 1010b of the fin structure <NUM>. Openings or trenches <NUM> have accordingly been formed in the cover material, along the first and second fin parts <NUM>, 1010d, to expose each of the first and second fin parts <NUM>, 1010d from both the first and second sides 1010a, 1010b.

The trenches <NUM> may be formed by etching the cover layer <NUM> through a respective opening in a mask (a "source/drain trench etch mask", not shown) formed over the cover layer <NUM> and the fin structure <NUM>. Each opening may be defined to extend over and across the fin structure and thus along the first side 1010a and second side 1010b. The mask may for example be formed by a suitable hard mask material (e.g. oxide or nitride), wherein the opening may be defined by lithography and etching. Example etching processes for forming the trench <NUM> include anisotropic etching (top-down) like RIE. By etching the cover layer <NUM> selectively to the capping <NUM> the trench <NUM> may be etched self-aligned with respect to the side surfaces 1010a, 1010b of the fin structure <NUM>.

The cover layer <NUM> may accordingly together with the capping <NUM> define a mask structure covering the fin structure <NUM> from the first and second sides 1010a, 1010b in the gate regions <NUM> (e.g. the third fin part 1010c), and defining openings exposing the fin structure <NUM> from the first and second sides 1010a, 1010b in the source/drain regions <NUM> (e.g. the first and second fin parts <NUM>, 1010d). The mask structure thus allows the portions of the first dielectric layers <NUM> to be accessed and etched laterally and selectively to form cavities <NUM> (e.g. "source/drain cavities") in the source/drain regions <NUM> along the fin structure <NUM>, e.g. in the first and second fin parts <NUM>, 1010d, as shown in <FIG>. The opposite side surface portions of the first dielectric layers <NUM> exposed in the trenches <NUM> may be laterally etched back (along the Y direction and -Y direction) from the trenches <NUM>. The first dielectric layers <NUM> may be etched such that the cavities <NUM> extend completely through the fin structure <NUM>, e.g. until the etch front progressing from the first side 1010a meets the etch front progressing from the second side 1010b. The first dielectric layers <NUM> may accordingly be etched such that portions of the first dielectric layers <NUM> remain in the gate regions <NUM> on opposite sides of the cavities <NUM>, e.g. in the third fin part 1010c. The first dielectric layers <NUM> may be etched selectively to the second dielectric layers <NUM> and the channel layers <NUM> (e.g. by selective etching of the first dielectric material to the second dielectric material and the third semiconductor material). A (wet or dry) isotropic etching process may be used.

In <FIG> and <FIG> the cavities <NUM> are filled with a dummy material <NUM>. The dummy material <NUM> may e.g. be a same material as the cover layer <NUM>, wherein the dummy material <NUM> may be deposited to fil the cavities <NUM> and the openings <NUM>. However, it is also possible to remove the cover layer <NUM> prior to depositing the dummy material <NUM>. The dummy material <NUM> is subsequently etched back top-down (along -Z direction), e.g. using an anisotropic etch, to remove dummy material deposited outside the cavities <NUM>. The liner <NUM> is subsequently re-deposited to cover the fin structure <NUM> along both sides 1010a, 1010b.

In <FIG> a cover material is deposited along the first and second sides 1010a, 1010b of the fin structure <NUM>, thereby forming a mask layer or cover layer <NUM> embedding the fin structure <NUM>. The cover layer <NUM> may be formed by a suitable cover material, such as any of the example materials discussed in connection with the cover layer <NUM>. An opening or trench <NUM> (e.g. "dummy removal trench") is formed in the cover layer <NUM>, in each source/drain region <NUM> of the fin structure <NUM>, along the first side 1010a but not along the directly opposite second side 1010b of the fin structure <NUM>. Openings or trenches <NUM> have accordingly been formed in the cover material, along the first and second fin parts <NUM>, 1010d, to expose each of the first and second fin parts <NUM>, 1010d from only the first side 1010a.

The trenches <NUM> may be formed by etching the cover layer <NUM> through a respective opening in a mask (a "dummy removal trench etch mask", not shown) formed over the cover layer <NUM> and the fin structure <NUM>. Each opening may be defined to extend over and along the first side 1010a but not the second side 1010b of the fin structure <NUM>. The mask may for example be formed by a suitable hard mask material (e.g. oxide or nitride), wherein the opening may be defined by lithography and etching. Example etching processes for forming the trench <NUM> include anisotropic etching (top-down) like RIE. By etching the cover layer <NUM> selectively to the capping <NUM> (and/or liner <NUM> which may be formed on the capping <NUM>) the trench <NUM> may be etched self-aligned with respect to the liner <NUM> on the side surface 1010a of the fin structure <NUM>.

After forming the trenches <NUM>, portions of the liner <NUM> exposed in each trench <NUM> may be removed from the first side surface 1010a of the first and second fin parts <NUM>, 1010d of the fin structure <NUM>. The portions of the liner <NUM> may be etched using a suitable isotropic etching process (wet or dry).

The partially opened liner <NUM> may accordingly together with the capping <NUM> and the cover layer <NUM> (if not removed) define a mask structure covering the fin structure <NUM> from the second side 1010b in the source/drain regions <NUM> and gate regions <NUM> (e.g. the first, second and third fin parts <NUM>, 1010d, 1010c), and defining openings exposing the fin structure <NUM> from the first side 1010a in the source/drain regions <NUM> (e.g. the first and second fin parts <NUM>, 1010d). The mask structure thus allows the dummy material <NUM> to be accessed and etched laterally and selectively and accordingly be removed from the cavities <NUM>, as shown in <FIG>. The dummy material <NUM> may be laterally etched back (along the Y direction) from the trenches <NUM>. The dummy material <NUM> may be removed completely from the cavities <NUM>. The dummy material <NUM> may be etched selectively to the second dielectric layers <NUM> and the channel layers <NUM> (e.g. by selective etching of the dummy material to the second dielectric material and the third semiconductor material). A (wet or dry) isotropic etching process may be used.

As set out above, the cavities <NUM> as well as the cavities <NUM> may be formed by etching the second sacrificial layers <NUM> and the first dielectric layers <NUM>, respectively, from both sides 1010a, 1010b. A double-sided etching may facilitate control of the etching profile between the portions of the layer portions being removed those being preserved. This may be better understood from the schematic illustrations in <FIG>.

<FIG> is a schematic top-down view of a cavity formed in a layer, e.g. layer <NUM> or <NUM>. The cavity is formed by isotropic etching from a single-side of the layer <NUM>/<NUM> through from an opening e.g. in liner <NUM> (the other side being masked by the liner <NUM>). Due to the isotropic etching an inner wall of the cavity is curved. CD represents the width dimension of the layer <NUM>/<NUM> (along the Y direction). L1D indicates an estimated maximum length dimension of the cavity (along the X direction) for an opening of longitudinal dimension A (along the X direction) assuming the etching is stopped after the etch front reaches the opposite side of the layer <NUM>/<NUM>. V1D indicates an estimated minimum length dimension of the cavity obtained at the side opposite the opening. Accordingly, a variation of longitudinal dimension of the cavity becomes 2CD. In contrast, as illustrated in <FIG>, by etching the layer <NUM>/<NUM> from both sides as described above, a variation of a longitudinal dimension of the cavity may be reduced to CD.

By additionally introducing a longitudinal etch contrast / etch selectivity in the second sacrificial layers <NUM> using the aforementioned ion implantation process, a tendency of an isotropic etching of the layers <NUM>/<NUM> causing a curved or rounded etch front may be reduced. Moreover, the longitudinal etch contrast may facilitate localizing the forming of the cavities <NUM>/<NUM> to the regions <NUM> (e.g. to the first and second fin parts <NUM>, 1010d) by providing a reduced etch rate of the un-doped portions of the layers <NUM>/<NUM> in the regions <NUM> (e.g. the third fin part 1010c) compared to the doped portions of the layers <NUM>/<NUM> in the regions <NUM> (e.g. the first and second fin parts <NUM>, 1010d). Accordingly, the selective etching may further be adapted to etch the doped second semiconductor material/first dielectric material of the first and second fin parts <NUM>, 1010d selectively to the un-doped second semiconductor material/first dielectric material of the third fin part 1010c.

It is further to be noted that by using an isotropic etching process to form the cavities <NUM>/<NUM>, a longitudinal dimension of the openings in the liner <NUM>/the mask <NUM> (along the X direction) may be smaller than a longitudinal dimension of the source/drain regions <NUM>. In other words, the openings need not be coextensive with the regions <NUM> (along the X direction).

With reference to <FIG>, subsequent to removing the dummy material <NUM> from the cavities <NUM>, source/drain material may be deposited to form the source/drain bodies <NUM>. During the source/drain material deposition the cover layer <NUM> and/or the liner <NUM> may mask the fin structure <NUM> from the second side 1010b. The cover layer <NUM> may be removed prior to or subsequent to the source/drain material deposition.

The source/drain bodies <NUM> may be formed by epitaxy of a semiconductor source/drain material. The epitaxy may seed from top and bottom surface portions of the channel layers <NUM> exposed in the cavities <NUM>. The material deposited in the cavities <NUM> may form prongs <NUM> in contact / abutment with the channel layers <NUM>. The epitaxy may as shown be continued until the source/drain material protrudes from the cavities <NUM> to form body portions along the first side <NUM>. The epitaxay may subsequently be further continued such that the (individual) body portions merges to define the common body portions <NUM> along the first side 1010a. For example, Si or SiGe may be epitaxially grown in contact with Si or SiGe channel layers <NUM>, e.g. using selective area epitaxy. The epitaxy may comprise an initial sub-step of depositing a seed layer on the channel layers <NUM> in the cavities, to facilitate growth of a remainder of the source/drain bodies <NUM>. The source/drain material may be doped, e.g. by in-situ doping, with an n- or p-type dopant, to form doped source/drain bodies, in contact with the channel layers.

After the epitaxy, a contact etch stop layer (CESL) may be deposited (e.g. by ALD) on the source/drain bodies <NUM>. In the illustrated example, the CESL is formed of a same material as the liner <NUM>, and hence depicted as continuous with the liner <NUM> and indicated with the same reference sign. However, the CESL may also be formed of a different suitable dielectric hard mask material. The CESL may serve as a mask for the source/drain bodies <NUM> during subsequent process steps.

As shown in <FIG>, the process steps shown in <FIG>through <FIG> may be repeated at further fin structures, such as the second fin structure <NUM> (the rightmost fin structure in <FIG>), to form corresponding source/drain bodies <NUM> along the second fin structure. The source/drain bodies <NUM> along the second fin structure <NUM> may e.g. be formed with an opposite doping to the source/drain bodies <NUM> along the first fin structure <NUM>.

After depositing the source/drain material, the fin structure <NUM> may be embedded in a dielectric layer <NUM>, e.g. an oxide such as CVD or FCVD SiO<NUM>. The dielectric layer <NUM> may be recessed (e.g. by CMP and/or etch back) to bring its upper surface flush with an upper surface of the capping <NUM> or (as shown) the liner <NUM> / CESL thereon.

<FIG> and <FIG> illustrate process steps for forming a gate body <NUM> in each gate region <NUM>, e.g. along the third fin part 1010c. The gate body <NUM> comprises a common gate body portion <NUM> arranged at the second side 1010b of the fin structure <NUM>, and a set of vertically spaced apart gate prongs <NUM>. Each gate prong <NUM> protrudes from the common gate body portion <NUM> in the opposite direction to the prongs <NUM> (along the -Y direction) into a space above or underneath a respective channel layer <NUM>. In the illustrated example, the prongs <NUM> in particular extend into a space between a respective pair of channel layers <NUM>.

In <FIG>, a trench <NUM> (e.g. "gate trench") has been formed alongside the fin structure <NUM> in each gate region <NUM>, along the second side 1010b thereof. An opening or trench <NUM> has accordingly been formed in the dielectric layer <NUM> along the third fin part 1010c, to expose the third fin part 1010c from only the second side 1010b.

The trench <NUM> may as shown be formed by etching the dielectric layer <NUM> through an opening in a mask <NUM> (a "gate trench etch mask <NUM>") formed over the dielectric layer <NUM> and the fin structure <NUM>. More specifically, the opening may be defined to extend over and along the second side 1010b but not the first side 1010a of the fin structure <NUM>. The mask <NUM> and trench <NUM> may be formed and etched respectively in a same manner as the source/drain trench etch mask and the source/drain trench <NUM>, respectively.

Depending on an etch contrast between the liner <NUM> and the dielectric layer <NUM> the liner <NUM> may be removed from the second side surface 1010b during the etching of the dielectric layer <NUM>, or thereafter using a separate dedicated (e.g. isotropic) etch step.

The partially opened liner <NUM> may accordingly together with the capping <NUM>, the dielectric layer <NUM> and the gate trench etch mask <NUM> (if not removed) define a mask structure covering the fin structure <NUM> from the first side 1010b in the source/drain regions <NUM> and gate regions <NUM> (e.g. the first, second and third fin parts <NUM>, 1010d, 1010c), and defining openings exposing the fin structure <NUM> from the second side 1010b in the gate regions <NUM> (e.g. the third fin part 1010c). The mask structure thus allows the portions of the second sacrificial layers <NUM> remaining in the gate regions <NUM> (e.g. the third fin part 1010c) to be accessed from the trench <NUM> and etched laterally and selectively form cavities <NUM> (e.g. "gate cavities") in the gate regions <NUM>, e.g. the third fin part 1010c. The side surfaces of the portions of the second sacrificial layers <NUM> exposed in the trench <NUM> may be laterally etched back (along the -Y direction) from the trench <NUM>. The portions of the second sacrificial layers <NUM> may be etched such that the cavities <NUM> extend completely through the fin structure <NUM>, along the -Y direction. The etch may continue until the portions of the second sacrificial layers <NUM> are removed from the fin structure <NUM> (i.e. completely).

As may be appreciated from the above, the remaining portions of the second sacrificial/non-channel layers <NUM> correspond to portions of the second sacrificial layers <NUM> which have not been replaced by second dielectric layers <NUM> and may hence be of the second semiconductor material, and in particular be undoped. The portions <NUM> may hence be removed from the fin structure <NUM> by selective etching of the second semiconductor material (e.g. being un-doped) to the first dielectric material and the third semiconductor material.

As the portions of the second sacrificial layers <NUM> remaining prior to forming the cavities <NUM> are surrounded by the second dielectric layers <NUM> on either side (as viewed along the longitudinal direction of the fin structure <NUM>, i.e. the X direction) the cavity etch may be confined to the regions <NUM>, e.g. the third fin part 1010c. The second semiconductor material may hence further be etched selectively to the second dielectric material such that the second dielectric layers <NUM> may be used as etch stop layers along the longitudinal direction X of the fin structure <NUM>. A (wet or dry) isotropic etching process may be used. For example, selective etching of SiGey to SiGex (with <NUM> ≤ x < y) may as discussed above be achieved e.g. using an HCl-based dry etch.

In <FIG> the gate body <NUM> has been formed, comprising the set of gate prongs <NUM> in the cavities <NUM>, and the common gate body portion <NUM> in the trench <NUM>, merging the gate prongs <NUM>. The gate body <NUM> is for illustrational clarity depicted as a single piece-body, however may be formed by depositing a stack of gate materials (a "gate stack") comprising a gate dielectric layer, and one or more gate metals. The gate dielectric layer may be a conventional gate dielectric of a high-k, such as HfO<NUM>, LaO, AlO and ZrO. Examples of gate metals include conventional work function metals, such as TiN, TaN, TiAl, TiAIC or WCN, or combinations thereof, and gate fill materials such as W and Al. At least the gate dielectric layer and the WFM layer(s) may be conformally deposited, e.g. by ALD, to facilitate deposition within the cavities <NUM>. During the gate formation, the fin structure <NUM> is masked from the first side 1010a by the dielectric layer <NUM>, such that the common gate body portion <NUM> is formed selectively along the second side 1010b.

The gate metal(s) may be recessed using e.g. CMP and/or a metal etch back process to form recessed gates <NUM>. The gates <NUM> may as shown be recessed to bring its upper surface flush with an upper surface of the dielectric layer <NUM>. According to other examples, the gates <NUM> may be recessed to a level below the upper surface of the dielectric layer <NUM> and then then be covered by a dielectric to restore the dielectric layer <NUM> over the gates <NUM>.

As shown in <FIG>, the trench <NUM> may be formed at a position between the pair of fin structures <NUM> to expose the mutually facing side surfaces thereof. Cavities <NUM> may hence be formed in two adjacent fin structures <NUM> using a same trench <NUM> wherein the gate body <NUM> may be shared by the adjacent fin structures <NUM>.

As discussed with reference to the FET device <NUM>, the gate prongs <NUM> and source/drain prongs <NUM>/<NUM> may be arranged to overlap respective common regions 150as/150ad of each channel layer 150a. According to the example process, such a configuration may be facilitated by forming the cavities <NUM> to extend into the gate regions <NUM> / the third fin part 1010c and/or the cavities <NUM> to extend into the source/drain regions <NUM> / the first and second fin parts <NUM>, 1010d. As schematically indicated by the dashed lines in <FIG> and <FIG>, the cavities <NUM> may be extended by etching the first dielectric layers <NUM> by an additional amount Lov1 along the X and -X directions, thereby enabling forming of correspondingly extended/elongated source/drain prongs <NUM>, as shown in <FIG>. Correspondingly, as schematically indicated by the dashed lines in <FIG>, the cavities <NUM> may be extended by partially etching the second dielectric layers <NUM> by an additional amount Lov2 along the X and -X directions, thereby enabling forming of correspondingly extended/elongated gate prongs <NUM>, as shown in <FIG> schematically indicates the combined length Lov = Lov1 + Lov2 of the common overlap regions which may be obtained in this manner. As discussed above, the isotropic nature of these etching processes may result in rounded profiles of the cavities <NUM>, <NUM>. Hence, the overlap lengths Lov, Lov1 and/or Lov2 may each be understood as denoting maximum overlap lengths within the fin structure <NUM>, and that the precise overlap lengths may vary along the width direction Y of the fin structure <NUM>.

In <FIG> source/drain contacts <NUM> have been formed on the source/drain bodies <NUM>. The contacts <NUM> may as shown be formed as wrap-around contacts, i.e. wrapping around the common body portions <NUM>. Source/drain contact trenches may be patterned in the dielectric layer <NUM> and the liner <NUM> / CESL may be opened along the first side 1010a (e.g. using lithography and etching) and one or more contact metals may be deposited therein to form the source/drain contacts <NUM>. Examples of contact metals include W, Al, Ru, Mo and Co. The contact metal(s) may be recessed using a metal etch back process to form recessed contacts <NUM>. The recessed contacts <NUM> may then be covered by a dielectric to restore the dielectric layer <NUM> over the source/drain contacts <NUM>. CMP may be applied to the dielectric layer <NUM>. The dielectric layer <NUM> may as shown be recessed (e.g. by CMP and/or etch back) to bring its upper surface flush with an upper surface of the capping <NUM>.

In the above a process for forming a FET device of the first type, e.g. FET device <NUM>, has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible.

For example, the epitaxy of the source/drain bodies <NUM> discussed with reference to <FIG> may be stopped before forming merged common semiconductor body portions <NUM>. In this case, the (metal) source/drain contacts <NUM> may define common (metal) body portions <NUM>, wrapping around ends of the prongs <NUM>. Also in a case where merged common semiconductor body portion <NUM> are formed, the contacts <NUM> may be considered to form part of the common body portions <NUM>, wherein the common body portions <NUM> may be formed as combined semiconductor-metal common body portions.

According to a further example, instead of epitaxial source/drain body portions and/or prongs, metal source/drain bodies <NUM> comprising metal source/drain prongs <NUM> and metal source/drain body portions <NUM> may be formed, e.g. by depositing metal in the cavities <NUM> and trenches <NUM>. Metal source/drain prongs <NUM> may for example be combined with channel layers formed by thin-film or 2D materials, such as a transition metal dichalcogenide (MX<NUM>) or IGZO.

According to a further example, an ion implantation process may be omitted. This may result in an overall reduction of process complexity, albeit at a cost of less precise control during e.g. the etching of the cavities <NUM>, <NUM> and <NUM>. The method may according to such an example proceed directly from the stage depicted in <FIG> to the stage depicted in <FIG> wherein the liner <NUM> has been partially opened. The liner <NUM> may in this case be opened using the above discussed dedicated liner opening mask defined for the purpose of opening the liner <NUM> to expose each of the first and second fin parts <NUM>, 1010d in a respective source/drain region <NUM> on opposite sides of a gate region <NUM>. The method may then proceed as further outlined above in connection with <FIG> and onwards with the difference that there will be no difference in doping concentrations between the first, second and third parts <NUM>, 1010d, 1010c.

According to an alternative to the process steps discussed with reference to <FIG> and <FIG>, comprising replacing the first sacrificial layers <NUM> of the first semiconductor material with the first dielectric layers <NUM> of the first dielectric material shown, a fin structure <NUM> with the layer structure shown in <FIG> may instead be formed by patterning such a fin structure in a multi-layered SOI structure formed by epitaxy and/or layer transfer techniques (e.g. Si/SiO<NUM>/Si/SiGe/SiO<NUM>/Si/SiGe.

According to an alternative to the process steps discussed with reference to <FIG> and onwards, a dielectric cover layer corresponding to layer <NUM> may be formed instead of the cover layer <NUM>. Trenches corresponding to trenches <NUM> may then be formed in the dielectric cover layer, the dummy material <NUM> may be removed and source/drain bodies <NUM> may be formed in the cavities <NUM> and the trenches. The trenches may be filled with dielectric to restore the cover layer. Contact trenches may subsequently be formed and source/drain contacts may be formed therein (e.g. after repeating the processing at further fin structures).

Embodiments of methods for forming a FET device of the second type, e.g. the FET device <NUM>, will now be described with reference to <FIG> through <FIG>. In the following figures, elements are numbered 2NNN, respectively, wherein the last three digits NNN corresponds to an element 1NNN discussed in connection with <FIG>. To avoid undue repetition, a description of like elements will not be repeated.

As discussed above, the FET device <NUM> differs from the FET device <NUM> among others in that while the source and drain prongs <NUM>, <NUM> of the FET device <NUM> are level with the channel layers <NUM>, the source and drain prongs <NUM>, <NUM> of the FET device <NUM> are offset vertically from both the gate prongs <NUM> and the channel layers <NUM>. In view of this, the FET device <NUM> may be formed by applying many of the process steps discussed with reference to the FET device <NUM> to a fin structure <NUM> comprising a layer stack of an alternative composition. The layer stack may comprise channel layers <NUM> (e.g. corresponding to channel layers <NUM>) and non-channel layers <NUM> (e.g. corresponding to the first dielectric layers <NUM>) alternating the channel layers <NUM>, wherein each non-channel layer <NUM> is formed of a same first layer material, e.g. a first dielectric material.

With reference to <FIG> and <FIG>, such a fin structure <NUM> may be formed by patterning a preliminary fin structure <NUM> in a layer stack <NUM> formed on a substrate <NUM> (e.g. corresponding to substrate <NUM>) and comprising an alternating sequence of sacrificial layers <NUM> and channel layers <NUM>. The sacrificial layers <NUM> may be formed of a sacrificial semiconductor material different from a channel material of the channel layers <NUM> and the first layer material of the non-channel layers <NUM> to be formed. The sacrificial layers and channel layers <NUM>, <NUM> may similar to the first sacrificial layers <NUM> and the channel layers <NUM> be formed of epitaxial semiconductor material, e.g. SiGey and SiGex, respectively, wherein <NUM> ≤ x < y, for example y = x + d with d ≥ <NUM>.

The sacrificial layers <NUM> may subsequently be replaced with the non-channel layers <NUM> by applying process steps to the fin structure <NUM> corresponding to the process steps described above in connection with <FIG> and <FIG> for replacing the sacrificial layers <NUM> with the first dielectric layers <NUM>: depositing a process material embedding the preliminary fin structure <NUM>, forming a trench in the process material, alongside the preliminary fin structure <NUM>, removing the sacrificial layers <NUM> by selectively laterally etching the sacrificial material from the trench to form longitudinal gaps in the fin structure <NUM>, and subsequently filling the gaps with the first layer/dielectric material to form the non-channel layers <NUM> alternatingly with the channel layers <NUM>. A resulting fin structure <NUM> is shown in <FIG>, wherein additionally a liner <NUM> (e.g. corresponding to liner <NUM>) has been formed along the first and second sides 2010a, 2010b of the fin structure <NUM>. A fill layer <NUM> (e.g. corresponding to fill layer <NUM>) has further been formed, embedding the fin structure <NUM>.

After an optional ion implantation step as described in connection with <FIG>, the method may subsequently proceed with:.

Claim 1:
A method for forming a field-effect transistor device (<NUM>; <NUM>), the method comprising:
forming a fin structure (<NUM>; <NUM>) comprising a layer stack comprising channel layers (<NUM>; <NUM>) and non-channel layers (<NUM>, <NUM>; <NUM>) alternating the channel layers (<NUM>; <NUM>), the fin structure (<NUM>; <NUM>) comprising a first fin part (<NUM>; <NUM>), a second fin part (1010d; 2010d) and a third fin part (1010c; 2010c) intermediate the first and second fin parts;
etching each of the first and second fin parts (<NUM>, 1010d; <NUM>, 2010d) laterally from each of first and second opposite sides (1010a, 1010b; 2010a, 2010b) of the fin structure (<NUM>; <NUM>) such that a set of source cavities (<NUM>; <NUM>) extending through the first fin part is formed in a first set of layers of the layer stack, and such that a set of drain cavities (<NUM>; <NUM>) extending through the second fin part is formed in the first set of layers of the layer stack;
filling the source and drain cavities (<NUM>; <NUM>) with a dummy material (<NUM>);
while masking the fin structure from the second side (1010b; 2010b):
- removing the dummy material from the source and drain cavities by etching from the first side (1010a; 2010a), and
- subsequently, forming a source body and a drain body (<NUM>, 1120d; <NUM>, 2120d), each comprising a respective common body portion (<NUM>) along the first side (1010a; 2010a) and a set of prongs (<NUM>) protruding from the respective common body portion into the source and drain cavities, respectively, and abutting the channel layers (<NUM>; <NUM>); and
while masking the fin structure from the first side (1010a; 2010a):
- etching the third fin part (1010c; 2010c) laterally from the second side (1010b; 2010b) such that a set of gate cavities (<NUM>; <NUM>) extending through the third fin part is formed in a second set of layers defined by non-channel layers of the layer stack, the second set of layers being different from the first set of layers, and
- subsequently, forming a gate body (<NUM>; <NUM>) comprising a common gate body portion (<NUM>; <NUM>) along the second side and a set of gate prongs (<NUM>; <NUM>) protruding from the common gate body portion into the gate cavities (<NUM>; <NUM>).