Patent Description:
In many electronics applications, an analog input signal is converted to a digital output signal (e.g., for further digital signal processing). For instance, in precision measurement systems, electronics are provided with one or more sensors to make measurements, and these sensors may generate an analog signal. The analog signal would then be provided to an ADC as input to generate a digital output signal for further processing. In another instance, an antenna generates an analog signal based on the electromagnetic waves carrying information/signals in the air. The analog signal generated by the antenna is then provided as input to an ADC to generate a digital output signal for further processing.

ADCs can be found in many places such as broadband communication systems, audio systems, receiver systems, etc. ADCs can translate analog electrical signals representing real-world phenomena, e.g., light, sound, temperature or pressure for data processing purposes. ADCs are used in a broad range of applications including Communications, Energy, Healthcare, Instrumentation and Measurement, Motor and Power Control, Industrial Automation and Aerospace/Defense. Designing an ADC is a non-trivial task because each application may have different needs in speed, performance, power, cost, and size. As the applications needing ADCs grow, the need for accurate and reliable conversion performance also grows.

ADCs are electronic devices that convert a continuous physical quantity carried by an analog signal to a digital number that represents the quantity's amplitude (or to a digital signal carrying that digital number). The conversion involves quantization of the analog input signal, so it would introduce a small amount of error. Typically the quantization occurs through periodic sampling of the analog input signal. The result is a sequence of digital values (i.e., a digital signal) that has converted a CT and continuous-amplitude analog input signal to a discrete-time and discrete-amplitude digital signal. An ADC can be defined by the following application requirements: its bandwidth (the range of frequencies of analog signals it can properly convert to a digital signal) and its resolution (the number of discrete levels the maximum analog signal can be divided into and represented in the digital signal). An ADC also has various specifications for quantifying ADC dynamic performance, including signal-to-noise- and-distortion ratio (SINAD), effective number of bits (ENOB), signal to noise ratio (SNR), signal to quantization noise ratio (SQNR), noise spectral density (NSD), total harmonic distortion (THD), total harmonic distortion plus noise (THD+N), and spurious free dynamic range (SFDR). ADCs have many different designs, which can be chosen based on the application requirements and performance specifications.

<CIT> discloses a voltage-controlled-oscillator based continuous-time pipelined ADCs of the prior art.

The publication "<NPL> also discloses a VCO-based continuous-time pipelined ADC.

The present invention concerns a pipelined analog-to-digital converter according to independent claim <NUM> and a corresponding method for pipelined analog-to-digital conversion according to independent method claim <NUM>.

VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC. Moreover, implementing the continuous-time pipelined ADC is not trivial. For instance, a unique digital signal reconstruction filter is implemented and programmed to combine digital signals of the continuous-time residue generation front end and the VCO ADC back end and generate a final digital output.

A VCO ADC is a (mostly-digital) CT ADC. A VCO ADC comprises, in series: a ring oscillator, a phase-to-digital converter, and a differentiator. An analog input signal drives a ring oscillator, and the differentiator outputs a digital signal that is quantized version of the analog input signal.

The ring oscillator can include a voltage-controlled ring oscillator. For example, the ring oscillator can be implemented with an odd number of inverters connected in a ring. Each inverter can have a transition delay that depends on an input voltage to the ring oscillator. The ring oscillator can generate phase information of the analog input signal to the VCO ADC. In some cases, the voltage-controlled ring oscillator is implemented using a voltage-to-current converter followed by a current-controlled ring oscillator. The voltage-to-current converter converts an analog input voltage signal to into a current signal. Then, the current signal drives the current-controlled ring oscillator. The current-controlled ring oscillator can include an odd number of current-starved inverters in a ring.

The outputs of the inverters, which has phase information of the analog input signal to the VCO ADC, can be observed to derive the voltage of the analog input signal. Specifically, it is possible to extract the voltage of the analog input signal based on how the phase changes from one cycle to another cycle. The phase-to-digital converter can sample and quantize the phase of the VCO (e.g., the phase of the analog input signal to the VCO ADC). For instance, the phase-to-digital converter can include a ring sampler to sample the outputs of the inverters (e.g., observe transitions of the inverters), and a phase decoder to decode or map the outputs of the ring sampler into a phase number. The phase decoder generates a digital phase signal representative of the phase of the VCO. The digital phase signal is provided to a (digital) differentiator, which can have a transfer function of <NUM> - z-<NUM>. The differentiator differentiates the digital phase signal and outputs a digital signal that is quantized version of the analog input signal to the VCO ADC.

The VCO ADC is low-power and compact-in-area, due to its simple circuit design. The ring oscillator is the analog circuit of the VCO ADC, whereas, other components which follow the ring oscillator are digital blocks. The resulting circuit of the VCO ADC, is compact since many analog circuits commonly-found in other ADCs such as flash ADCs, digital-to-analog converters (DACs), and amplifiers are not present in a VCO ADC. Instead, the VCO ADC only requires a ring oscillator, which can be implemented with simple, small complementary metal-oxide-semiconductor (CMOS) inverters. The digital blocks implemented in CMOS processes can be very compact, especially when the VCO ADC is implemented in smaller process nodes.

The VCO ADC can be considered as a type of CT ADC, because the analog input signal to the VCO ADC drives a ring oscillator that only has CT circuitry. In other words, the analog input signal to the VCO ADC is not sampled by samplers, i.e., the ring oscillator does not have switched-capacitor circuits which sample an input signal onto capacitor(s).

The VCO ADC, due to differentiation being used to derive the voltage of the analog input signal to the VCO ADC, has first-order noise shaping. This means that it is possible to implement a high resolution VCO ADC at or near DC (DC stands for direct current, where signal frequency is zero). However, the resolution is limited towards the sampling frequency of the VCO ADC, since the signal is difficult to observe at the sampling frequency.

Moreover, the ring oscillator has inherent and systematic non-linearity, even if the circuits in the ring oscillator is ideal. Specifically, converting an analog input signal into frequency to obtain phase information is a very non-linear process, and hurts the linearity of the entire VCO ADC. Accordingly, digital non-linearity correction is implemented to address the non-linearities. However, even with digital non-linearity correction, the achievable NSD, SNR, and SQNR are still limited for a VCO ADC.

Accordingly, the VCO ADC is usually applicable in applications where: (<NUM>) up to limited frequency (e.g., <NUM> bandwidth), (<NUM>) NSD is > -150dBFS/Hz, and/or (<NUM>) HD2 (second-order harmonics) or HD3 (third-order harmonics) > -80dBFS. Many high speed, wide bandwidth applications cannot use a VCO ADC.

CT pipelined ADC has N number of stages in cascade. For stage-<NUM> to stage-N-<NUM>, each stage has a coarse ADC to generate a digital output signal, and circuitry to generate an amplified residue signal (which is an amplified difference between the analog input signal to the stage and a reconstructed analog input signal of the stage) to be processed by the following stage. Stage-N has an ADC, e.g., a flash ADC comprising a bank of comparators, to generate the last digital output signal. The digital output signals of all the stages are combined by a digital signal reconstruction filter to generate a final digital output signal. The stages have CT circuitry, and do not include samplers (e.g., switched-capacitor circuits).

When a large number of cascaded stages are implemented, e.g., N > <NUM>, the CT pipelined ADC can achieve low noise (e.g., NSD < -160dBFS/Hz) and low distortion. It is common to implement <NUM> or more stages to achieve target performance. However, when the continuous-time pipelined ADC has a large number of cascaded stages, the circuitry can take up a significantly large amount of area in silicon, and consume a high amount of power. Moreover, a large number of cascaded stages can result in a complex digital signal reconstruction filter, if perfect signal reconstruction is to be achieved. For N stages in a CT pipelined ADC, N-<NUM> finite impulse response (FIR) filters are typically implemented in a digital signal reconstruction filter. Accordingly, the more stages the CT pipelined ADC has, the more FIR filters are needed in the digital signal reconstruction filter.

When a CT pipelined ADC is implemented with a CT residue generation front end and a CT VCO ADC back end (referred herein as a VCO-based CT pipelined ADC), limitations of a VCO ADC and a CT pipelined ADC having many cascaded stages are alleviated. A VCO-based CT pipelined ADC differs from a CT pipelined ADC in that the back end of the VCO-based CT pipelined ADC is not implemented with a flash ADC, or a successive-approximation-register ADC. A VCO-based CT pipelined ADC implementing the CT residue generation front end and a CT VCO ADC back end unexpected benefits, advantages which are not present in a VCO ADC or in a CT pipelined ADC. Moreover, unique challenges arise when a CT residue generation front end is combined with a CT VCO ADC back end.

<FIG> is an illustrative system diagram of a VCO-based CT pipelined ADC <NUM> having a CT residue generation front end and a CT VCO ADC back end, according to some embodiments of the disclosure. The VCO-based CT pipelined ADC <NUM> includes: a CT residue generation front end <NUM>, a CT VCO ADC back end <NUM>, and a digital signal reconstruction filter <NUM>. The CT residue generation front end <NUM> quantizes or digitizes an analog input signal vin and generate a first digital signal D<NUM> and an amplified residue signal va_res. The CT VCO ADC back end <NUM> quantizes or digitizes the amplified residue signal and generate a second digital signal DVCOADC. The digital signal reconstruction filter <NUM> filters the first digital signal D<NUM> and the second digital signal DVCOADC to generate a final digital signal DOUT.

Optionally, the CT VCO ADC back end <NUM> includes a digital non-linearity correction block <NUM>, to correct non-linearities of the CT VCO ADC back end <NUM> (or more specifically the VCO ADC <NUM>). The digital non-linearity correction block <NUM> provides a corrected output as the second digital signal DVCOADC to the digital signal reconstruction filter <NUM>.

First, the limitations such as non-linearity and noise of the CT VCO ADC back end <NUM> are alleviated by gain or amplification implemented in the CT residue generation front end <NUM>. Specifically, the NSD of the CT VCO ADC back end <NUM> is suppressed by the gain of the CT residue generation front end <NUM>. Note that the CT residue generation front end <NUM> cancels out a fundamental component of a large signal by generating a residue signal and providing an amplified residue signal va_res to the CT VCO ADC back end <NUM>. As a result, the distortion introduced by the CT VCO ADC back end <NUM> processing the amplified residue signal va_res is limited or reduced. Therefore, the VCO-based CT pipelined ADC <NUM> can be designed so that the NSD of the CT residue generation front end <NUM> dominates the overall NSD. This means that the VCO-based CT pipelined ADC <NUM> can achieve a same NSD as a CT pipeline ADC, and the poor NSD of a VCO ADC by itself would not be a limiting factor in the design of the VCO-based CT pipelined ADC <NUM>.

Second, using a CT VCO ADC back end <NUM>, which can have relatively high resolution compared to a stage-N of a CT pipelined ADC, means that the number of stages and design complexity in the VCO-based CT pipelined ADC <NUM> can be reduced while still be able to achieve the same resolution as a CT pipelined ADC. As a result, limitations associated with a CT pipelined ADC having many stages, such as area overhead, digital signal reconstruction filter complexity, and higher power consumption, are alleviated by implementing a VCO-based CT pipelined ADC <NUM> that has fewer pipelined stages for the same target resolution, and simpler circuitry due to the smaller and simpler circuit design of the CT VCO ADC back end <NUM>. Put simply, the VCO-based CT pipelined ADC <NUM>, when compared to a CT pipelined ADC with the same target resolution, can have lower power, smaller silicon area, and less-complicated digital signal processing (i.e., processing in the digital signal reconstruction filter).

Third, the CT VCO ADC back end <NUM> provides a sinc response, whereas a flash ADC of at the end of a CT pipeline ADC does not have a sinc response. The sinc response of the CT VCO ADC back end <NUM> can provide additional anti-aliasing benefits.

The VCO-based pipelined ADC <NUM> and other embodiments herein have additional benefits over other ADC architectures, which will be explained in greater detail herein.

<FIG> shows an exemplary implementation of a VCO-based CT pipelined ADC <NUM> having a CT residue generation front end <NUM> and a CT VCO ADC back end <NUM>, according to some embodiments of the disclosure. The CT residue generation front end <NUM> can include a quantizer <NUM>, a DAC <NUM>, a delay circuit <NUM>, node <NUM>, and a residue amplifier <NUM>. The CT VCO ADC back end <NUM> can include a VCO ADC <NUM>. The VCO ADC <NUM> optionally includes a digital non-linearity correction block <NUM>. The digital signal reconstruction filter <NUM> can include a first filter <NUM>, a second filter <NUM>, and a node <NUM>.

The quantizer <NUM> receives the analog input signal vin and generates the first digital signal D<NUM> by performing analog-to-digital conversion. The quantizer <NUM> can be an ADC, such as a flash ADC comprising a bank of comparators to compare the analog input signal vin against a plurality of reference voltages. The first digital signal D<NUM> is provided to digital signal reconstruction filter <NUM>.

The DAC <NUM> receives the first digital signal D<NUM> and generate a first reconstructed analog signal at an output of DAC <NUM> by performing digital-to-analog conversion. The DAC <NUM> reconstructs the analog input signal vin by generating the first reconstructed analog signal based on the first digital signal D<NUM>. DAC <NUM> can be a current-mode DAC generating a current signal, or a voltage-mode DAC generating a voltage signal.

The delay circuit <NUM> delays a first analog input signal to the quantizer <NUM>, e.g., the analog input signal vin, and generates a first delayed analog input signal. A response of the delay circuit <NUM> preferably matches a response of a signal path having the quantizer <NUM> and the DAC <NUM>. Details and illustrative examples of the delay circuit <NUM> are provided in <FIG> and <FIG>, and the passages that describe <FIG> and <FIG>.

Node <NUM> can perform subtraction/differencing to output a residue signal representing a difference between the first delayed analog input signal from the delay circuit <NUM> and the first reconstructed analog signal from DAC <NUM>. The first residue signal ideally represents a quantization error of quantizer <NUM>. Node <NUM> can perform voltage-mode subtraction or current-mode subtraction.

The residue amplifier <NUM> amplifies the residue signal from node <NUM> and generate the amplified residue signal va_res. The residue amplifier <NUM> can apply a gain that is greater than <NUM> to the first residue signal generated by node <NUM>. In some cases, the residue amplifier <NUM> is a filter having a filtering response, e.g., the residue amplifier <NUM> can have dynamic characteristics. This means that the amplified residue signal va_res can be a filtered residue signal. In some cases, the gain being applied may not be exactly the same or may not be uniform across frequencies. Accordingly, the residue amplifier <NUM> perform a filtering function (in addition to applying gain the first residue signal generated by node <NUM>). In some embodiments, the residue amplifier <NUM> has a low pass response. In some embodiments, the residue amplifier <NUM> has a high-pass response. In some embodiments, the residue amplifier <NUM> has a bandpass response. In some embodiments, the residue amplifier <NUM> has a first-order response. In some embodiments, the residue amplifier <NUM> has a second-order or higher-order response.

VCO ADC <NUM> receives and processes the amplified residue signal va_res. VCO ADC <NUM> can quantize the amplified residue signal va_res. The (optional) digital non-linearity correction block <NUM> can correct non-linearities of the VCO ADC <NUM>. The digital non-linearity correction block <NUM> provides a corrected output as the second digital signal DVCOADC to the digital signal reconstruction filter <NUM>.

The first filter <NUM> (shown as G<NUM>) of the digital signal reconstruction filter <NUM> can filter the first digital signal D<NUM>. The second filter <NUM> (shown as G<NUM>) of the digital signal reconstruction filter <NUM> can filter the second digital signal DVCOADC. Node <NUM> can combine outputs of the first filter <NUM> and the second filter <NUM> to generate the digital signal DOUT. Details and illustrative examples of the digital signal reconstruction filter <NUM> are provided in <FIG> and the passages that describe <FIG>.

The digital signal reconstruction filter <NUM> is unique to the VCO-based CT pipelined ADC. Moreover, the digital signal reconstruction filter <NUM> is not trivial, because the implementation and behavior of CT circuitry in the VCO-based CT pipelined ADC can complicate digital signal reconstruction. The behavior or response of the CT circuitry is hidden.

One technical task of the digital signal reconstruction filter <NUM> is to remove the quantization noise introduced by the CT residue generation front end <NUM>, specifically, the quantization noise introduced by quantizer <NUM>. When the digital signal reconstruction filter <NUM> is programmed appropriately, the quantization noise introduced in the CT residue generation front end <NUM> can be cancelled out in the final digital signal DOUT.

The signal processing in the digital signal reconstruction filter <NUM> in <FIG>, can be characterized as follows: <MAT>.

Also, D<NUM> and DVCOADC can be characterized by the transfer functions mentioned above, as follows: <MAT> <MAT>.

Plugging in Equations <NUM> and <NUM> into Equation <NUM> results in: <MAT> <MAT>.

Note that the terms having the quantization noise qCTRES (introduced by the CT residue generation front end <NUM>) can be cancelled out (or goes to zero) if: <MAT>.

This means that if the ratio of the first filter <NUM> (i.e., the transfer function G<NUM>) and the second filter <NUM> (i.e., the transfer function G<NUM>) corresponds to (<NUM>) a signal transfer function STFRA of a residue amplifier generating the amplified residue signal, (<NUM>) a signal transfer function STFVCOADC of the VCO ADC back end, and (<NUM>) a noise transfer function NTFCTRES of the CT residue generation front end <NUM>, terms having the quantization noise qCTRES would be cancelled out in the final digital output DOUT. Specifically, if the ratio <MAT> satisfied Equation <NUM>, then terms having the quantization noise qCTRES would be cancelled out and not appear in the final digital output DOUT.

Within the disclosure, "a ratio corresponds to {multiple functions}" means that X has a correspondence to, matches, or is associated with one or more of: {multiple functions}. The correspondence may not be exact. The correspondence may be an approximation. In some cases, the ratio can be composed of one or more of: {multiple functions}, in some form, or in a suitable combination.

The design of the digital signal reconstruction filter <NUM>, according to Equation <NUM>, thus sets a constraint on the ratio: G<NUM>/G<NUM>, however, the design does not prescribe the specific responses of the first filter and the second filter (i.e., G<NUM> and G<NUM>). Several possible solutions exist for G<NUM> and G<NUM> that would satisfy Equation <NUM>.

In some cases, G<NUM> = STFRA · STFVCOADC and G<NUM> = NTFCTRES,.

In some cases, G<NUM> = NTFCTRES and <MAT>.

Note that because of the architecture of the CT residue generation front end <NUM>, there is no noise shaping in the CT residue generation front end <NUM>. Accordingly, NTFCTRES=<NUM>, or the noise transfer function NTFCTRES of the CT residue generation front end <NUM> can be approximated as <NUM> (e.g., the noise transfer function NTFCTRES of the CT residue generation front end <NUM> has a flat frequency response). Equation <NUM> thus becomes: <MAT>.

In some cases, G<NUM> = STFRA · STFVCOADC and G<NUM> = <NUM>.

In some cases, G<NUM> = <NUM> and <MAT>.

This means that if the ratio of the first filter <NUM> (i.e., the transfer function G<NUM>) and the second filter <NUM> (i.e., the transfer function G<NUM>) corresponds to (<NUM>) a signal transfer function STFRA of a residue amplifier generating the amplified residue signal, and (<NUM>) a signal transfer function STFVCOADC of the VCO ADC back end.

Another technical task is that the digital signal reconstruction filter <NUM> can ensure that the first digital signal D<NUM> does not contribute to the final digital output DOUT. That means that the digital signal reconstruction filter <NUM> can reconstruct the analog input signal vin and form the final converter final digital signal DOUT based on the digital signals (e.g., first digital signal D<NUM> and second digital signal DVCOADC), in a manner such that the final digital signal DOUT is accurately represents the analog input signal vin.

In some embodiments, the digital signal reconstruction filter <NUM> can enable equal and opposite signal paths for the first digital signal D<NUM> towards the final digital output DOUT. The digital signal reconstruction filter <NUM> can ensure that the contribution from the first digital signal D<NUM> is cancelled out in the final digital output DOUT when the results from the equal and opposite signal paths are summed. The first filter <NUM>, which has a transfer function G<NUM>, provides a first signal path for the first digital signal D<NUM> towards the final digital output DOUT. The second filter <NUM>, which has a transfer function G<NUM>, is a part of a second and opposite signal path for the first digital signal D<NUM> towards the final digital output DOUT. Specifically, the second and opposite signal path includes DAC <NUM>, the residue amplifier <NUM>, the CT VCO ADC back end <NUM>, and the second filter <NUM>. Suppose the transfer function relating the first digital signal D<NUM> and the second digital signal DVCOADC is characterized by G<NUM>/G<NUM>, then the transfer function of the second and opposite signal path for the first digital signal D<NUM> towards the final digital output DOUT is a combination of G<NUM>/G<NUM> and -G<NUM> (the negative sign originates from the subtraction in node <NUM>), i.e., {G<NUM>/G<NUM>}·-G<NUM>=- G<NUM>. That means that the transfer function the first signal path is equal and opposite of the transfer function of the second and opposite signal path, i.e., G<NUM> is equal and opposite of -G<NUM>. Accordingly, the contribution from first digital signal D<NUM> is cancelled out and removed from the final digital output DOUT after the outputs of the first filter <NUM> and the second filter <NUM> are combined at node <NUM>. Phrased differently, the first digital signal D<NUM> does not contribute to the reconstructed final digital output DOUT. It can be appreciated that the transfer function relating the first digital signal D<NUM> and the second digital signal DVCOADC can be characterized by G<NUM>/G<NUM>, e.g., when G<NUM> = STFVCOADC · STFRA and G<NUM> = <NUM>. The first digital signal D<NUM> and the second digital signal DVCOADC are connected by a signal path having the DAC <NUM>, the residue amplifier <NUM>, and the CT VCO ADC back end <NUM>. Accordingly, the transfer function relating the first digital signal D<NUM> and the second digital signal DVCOADC can be represented by a combination of a signal transfer function STFRA of the residue amplifier <NUM> and a signal transfer function STFVCOADC of the CT VCO ADC back end <NUM>.

In practice, the first filter <NUM> (having the transfer function G<NUM>) and the second filter <NUM> (having the transfer function G<NUM>) are digital filters which are programmed using digital, approximate versions of the actual transfer functions. Determining the digital versions of the transfer functions is not a trivial task for VCO-based CT pipelined ADCs, since the transfer functions of CT circuitry are hidden and may not be well-characterized. Moreover, if the digital versions of the actual transfer functions do not accurately match with the actual versions of the transfer functions, quantization noise leakage can occur: <MAT>.

Note that the terms with the quantization noise qCTRES of the CT residue generation front end <NUM> do not cancel out if DSTFVCOADC ≠ STFVCOADC, DSTFRA ≠ STFRA, and DNTFCTRES ≠ NTFCTRES,.

<FIG> illustrates an exemplary digital signal reconstruction filter <NUM> and a scheme for programming the digital signal reconstruction filter <NUM>, according to some embodiments of the disclosure. The technical task of programming the first filter <NUM> (and/or the second filter <NUM>) is to determine digital filters, which can efficiently process the first digital signal D<NUM> and the second digital signal DVCOADC in the digital domain. In the example shown, the first filter <NUM> (i.e., the transfer function G<NUM>) can correspond to the digital version of the digital version of the signal transfer function of the residue amplifier <NUM> (DSTFRA) and the digital version of the signal transfer function of the CT VCO ADC back end <NUM> (DSTFVCOADC): <MAT>.

The second filter <NUM> (i.e., the transfer function G<NUM>) can correspond to a digital version of the noise transfer function of the CT residue generation front end <NUM> (DNTFCTRES): <MAT>.

The signal transfer functions of the VCO-based CT pipelined ADC <NUM> as seen in Equation <NUM> are not always well defined, and can change over time during operation or can vary from one integrated circuit to another. To determine the digital version of the signal transfer function of the residue amplifier and the digital version of the signal transfer function of the CT VCO ADC back end <NUM>, i.e., DSTFRA and DSTFVCOADC, and a known signal or dither can be injected at the input of the residue amplifier <NUM>. The known signal or dither can be removed from the second digital signal DVCOADC in the digital domain. Information about the signal transfer functions can be extracted by observing how the known signal is affected by the signal path.

For example, the known signal or dither can be a maximum length linear feedback shift registers (LFSR) sequence, whose cross-correlation approaches an impulse response. Direct cross-correlation between the injected maximum length LFSR sequence and the second digital signal DVCOADC can be performed in the background to estimate the signal transfer function of the residue amplifier <NUM> and the signal transfer function of the CT VCO ADC back end <NUM> and obtain DSTFRA and DSTFVCOADC.

Cross-correlation, as used herein, refers to a measurement of similarity between a pair of signals: <MAT>.

L indicates lag, and n is the time index. Accordingly, the cross-correlation is the accumulation of signal multiplications in time, equivalent to the convolution of x[n] with y[-n], or multiplication rxy[l] = <IMG>{X[k] · Y*[k]} where k is frequency. Cross-correlation is a sliding dot product or sliding inner-product of the two digital signals.

One-bit dither generated through a maximum length LFSR sequence can be injected at an input of the residue amplifier <NUM>. Referring to <FIG>, the dither LFSR can be injected in the DAC <NUM> (e.g., by adding the dither to the output of the DAC <NUM>, or by modifying input bits to the DAC <NUM> based on the dither to cause the dither to be added to the output of the DAC <NUM>). The dither LFSR can be removed in the digital domain, e.g., from the second digital signal DVCOADC.

The CT pipelined ADC <NUM> further includes a correlator <NUM> to cross-correlate the dither and the second digital signal DVCOADC to extract (<NUM>) a signal transfer function of a residue amplifier <NUM> generating the amplified residue signal, and (<NUM>) a signal transfer function of the CT VCO ADC back end <NUM>. Specifically, the result of cross-correlation by correlator <NUM> can yield estimates or approximations of the signal transfer function of the residue amplifier <NUM> and the CT VCO ADC back end <NUM>, i.e., DSTFRA · DSTFVCOADC. The estimates/approximations corresponding to DSTFVCOADC · DSTFRA, can be used to program the first filter <NUM> and/or the second filter <NUM>. The estimates/approximations includes information to program coefficients for taps of a FIR filter in the digital signal reconstruction filter <NUM>.

Note that the digital signal reconstruction filter <NUM> in <FIG> can be realized with just a single FIR filter (e.g., when one of the first filter <NUM> and the second filter <NUM> has a response of <NUM>). This means that the digital signal reconstruction filter <NUM> can be implemented efficiently. For instance, one of the first filter <NUM> and the second filter <NUM> can be a <NUM>-tap FIR filter.

By taking into account the signal transfer function (e.g., sinc response) of the CT VCO ADC back end <NUM> in the digital signal reconstruction filter <NUM>, a significant amount of distortion is removed in the final digital output DOUT.

Other types of signals can be used as the known signal or dither, and other mechanisms (depending on the type of signal being used) can be implemented to extract the signal transfer function. For instance, a pseudo-random signal, such as a pseudo-random <NUM>-bit sequence, can be used as the known signal or dither. The known signal or dither can be white noise over a range of frequencies, such as one or more Nyquist zones of converter. The known signal can include tones sweeping over a range of frequencies, such as one or more Nyquist zones of the converter. Preferably, the known signal or dither has energy or information content over a range of frequencies (e.g., a wideband signal). Using a known signal with wideband energy or information content can ensure that the signal transfer function over a frequency range of interest can be extracted. In some cases, the behavior of the signal path can be more critical in lower frequencies, and accordingly, the known signal or dither may have more energy or information content in the lower frequencies of the frequency range of interest, so that the signal transfer function being extracted has more information about the behavior of signal path in the lower frequencies.

Cross-correlation represents one exemplary signal transfer function extraction scheme. Other extraction schemes suitable for a particular kind of known signal being injected can be used to extract the signal transfer function(s) of interest. For instance, if the known signal comprises tones sweeping over a range of frequencies, magnitude and phase information corresponding to various frequencies, extracted from the digital outputs generated as a result of tones at various frequencies, can be used to form the signal transfer function(s) of interest.

The residue signal at the input of the residue amplifier <NUM> represents a difference between the analog input signal vin and the reconstructed analog input signal from DAC <NUM>. To ensure that the residue signal generated by node <NUM> accurately represents a difference between the analog input signal vin and the reconstructed analog output signal at the output of DAC <NUM>, the analog input signal vin is at least delayed by a same amount of time it takes for the analog input signal vin to propagate and be processed by the quantizer <NUM> and DAC <NUM>. Accordingly, the delay circuit <NUM> of <FIG> and <FIG>, delays the analog input signal vin (the input to the quantizer <NUM>), and generates a delayed analog input signal. The delay would match a propagation delay of the signal path having the quantizer <NUM> and DAC <NUM>.

Besides matching the delay, the delay circuit <NUM> preferably also matches the response (e.g., frequency response) of the signal path having the input the quantizer <NUM> and DAC <NUM> forms a signal path from the analog input signal vin. For instance, the delay circuit <NUM> can match the magnitude and/or phase of the signal path. To achieve matching of magnitude, phase, and/or any other desirable response characteristics, the delay circuit <NUM> can be implemented using a variety of analog/CT circuits. <FIG> shows an exemplary implementation of a VCO-based CT pipelined ADC <NUM> having a CT residue generation front end <NUM> and a CT VCO ADC back end <NUM>, according to some embodiments of the disclosure. The delay circuit <NUM> in the CT residue generation front end <NUM> comprises a resistor-capacitor lattice circuit.

<FIG> illustrates various exemplary implementations of the delay circuit <NUM>. <FIG> shows a delay circuit implemented based on resistors and transmission lines (e.g., a conductor). <FIG> shows a delay circuit comprising a resistor-capacitor lattice, as seen in <FIG>. <FIG> illustrate variations on the resistor-capacitor lattice circuit. <FIG> shows a delay circuit comprising an inductor-capacitor lattice. <FIG> shows a delay circuit comprising cascaded inductor-capacitor lattices. Different circuit implementations of the delay circuit can implement different (filtering) responses (i.e., magnitude and phase can differ depending on the circuit and the values of the circuit components). The specific implementation of the delay circuit <NUM> can depend on the implementations of the signal path having the quantizer <NUM> and DAC <NUM>, and the desired level of matching between the delay circuit <NUM> and the signal path. In some cases, the magnitude matching between the delay circuit <NUM> and the signal path having the quantizer <NUM> and DAC <NUM> is provided by implementing a delay circuit <NUM> that has a low pass filtering response.

<FIG> illustrates various implementations of CT delay lines, according to some embodiments of the disclosure. The construction and design of the delay circuit <NUM> can be modular, and the parts of the delay circuit <NUM> can be selected to optimize the matching of the delay circuit <NUM> with the signal path having the quantizer <NUM> and DAC <NUM>. Specifically, the parts of the delay circuit <NUM> can be chosen for factors such as: filter response, optimal phase matching, and optimal magnitude matching. The delay circuit <NUM> can include a cascade of X sub-circuits or X series-connected sub-circuits <NUM><NUM>, <NUM><NUM>,. By choosing or selected an appropriate analog filter for the sub-circuits, the delay circuit <NUM> can achieve a specific filtering response. Each sub-circuit can be implemented in different ways, as exemplified in the FIGURE. In a first example, an analog filter for a given sub-circuit can include a resistor in each differential signal path, as seen in analog filter <NUM>. In a second example, an analog filter for a given sub-circuit can include an inductor in each differential signal path, as seen in analog filter <NUM>. In a third example, an analog filter for a given sub-circuit can include a resistor-capacitor lattice, as seen in analog filter <NUM>. In a fourth example, an analog filter for a given sub-circuit can include an inductor-capacitor lattice, as seen in analog filter <NUM>. In a fifth example, an analog filter can include grounded capacitors on each differential signal paths, as seen in analog filter <NUM>. In a sixth example, an analog filter can include a capacitor coupled across the differential signal paths, as seen in analog filter <NUM>.

<FIG> illustrates one exemplary implementation of a CT delay line <NUM>, according to some embodiments of the disclosure. The implementation shown in the <FIG>, includes a cascade of sub-circuits or series-connected sub-circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Specifically, sub-circuit <NUM>, sub-circuit <NUM>, and sub-circuit <NUM>, can be implemented using the analog filter <NUM> seen in <FIG>. Sub-circuit <NUM> can be implemented using the analog filter <NUM> seen in <FIG>. Sub-circuit <NUM> can be implemented using the analog filter <NUM> seen in <FIG>. The selection of analog filters illustrated in <FIG> for CT delay line <NUM> can provide better phase matching and magnitude matching.

Matching of the delay circuit <NUM> with the signal path having the quantizer <NUM> and DAC <NUM> can mean that the VCO-based CT pipelined ADC can be used in wide bandwidth applications, especially when the delay circuit <NUM> can achieve the desired response (e.g., group delay) over a wide range of frequencies.

The CT residue generation front end <NUM>, specifically, the delay circuit <NUM> and quantizer <NUM>, has continuous-time circuitry and no samplers. Without samplers, the CT residue generation front end <NUM> does not suffer from aliasing issues typically associated with ADC front ends that have samplers. A signal chain having the VCO-based CT pipelined ADC <NUM> can have a much simpler anti-aliasing filter or the anti-aliasing filter can be eliminated altogether. As a result, components of the signal chain can be more easily integrated together in the signal chain, and promotes higher level of integration in the signal chain.

Additionally, the CT residue generation front end <NUM>, specifically, the delay circuit <NUM> and quantizer <NUM>, has a resistive input structure. The resistive input structure can provide resistive input impedance. Advantageously, the resistive input structure can reduce peak driving current, and also reduce power consumption of the circuits driving the VCO-based CT pipelined ADC.

Referring to <FIG>, the residue amplifier <NUM> in the example has a second-order frequency response, which is provided by two cascaded amplifiers and feedback signal paths. More generally, the residue amplifier <NUM> can be implemented to have a desirable frequency response to provide features such as anti-aliasing. In some embodiments, the residue amplifier <NUM> can have a low pass filter response. In some embodiments, the residue amplifier <NUM> can have a bandpass filter response. In some embodiments, the residue amplifier <NUM> can have a first-order frequency response. In some embodiments, the residue amplifier <NUM> can have a second-order or higher-order frequency response. In some embodiments, the residue amplifier <NUM> can have a notch near the sampling frequency fs, which can provide additional anti-aliasing.

One challenge in CT residue generation front end <NUM> is that the DAC <NUM> can have strong images in the output spectrum. The strong images can result in a residue signal that has a high amplitude. To address this issue, the residue signal can be minimized by (<NUM>) selecting and implementing a specific transfer function in the signal path involving the delay circuit <NUM>, and (<NUM>) upsampling the first digital signal D<NUM> and processing the upsampled signal by a discrete-time transfer function.

<FIG> shows an exemplary implementation of a CT residue generation front end <NUM> with digital-to-analog converter pulse shaping, according to some embodiments of the disclosure. The CT residue generation front end <NUM> has a signal path with the delay circuit <NUM>. The continuous-time transfer function of the signal path can be C(s). The quantizer <NUM> generates first digital signal D<NUM> at a rate of fck. The first digital signal D<NUM> is upsampled by an upsampling block <NUM> times. L is the upsampling factor of the upsampling block <NUM>. Accordingly, the output of the upsampling block <NUM> has a rate of L · fck. The upsampling block <NUM> can interpolate the first digital signal D<NUM> by inserting (L-<NUM>) zeros between every two samples. The output of the upsampling block <NUM> is filtered by a digital filter <NUM> having a discrete-time transfer function F(z). The output of the digital filter <NUM> drives the DAC <NUM> clocked at a rate of L · fck (rate of the quantizer <NUM> multiplied by the upsampling factor of the upsampling block <NUM>), and is converted into analog form. The DAC <NUM> generates the reconstructed analog signal based on the output of the digital filter <NUM>. Node <NUM> can perform subtraction of the delayed analog input signal from delay circuit <NUM> and the reconstructed analog input signal from DAC <NUM> to generate the residue signal. By selecting and implementing C(s) and F(z) appropriately, the residue signal generated at node <NUM> can be minimized to mostly or entirely the in-band quantization error of the quantizer <NUM>. For a given C(s), F(z) (i.e., the digital filter <NUM>) can be programmed accordingly to minimize the residue signal. For instance, F(z) can programmed to have a discrete-time transfer function that can to reduce or suppress images in the output spectrum of DAC <NUM>. For a given F(z), C(s) can be implemented (e.g., by implementing the appropriate delay circuit <NUM>) accordingly to minimize the residue signal.

Non-linearities of a VCO ADC <NUM> can be corrected by a digital non-linearity correction block <NUM>. To correct for the non-linearities, the CT VCO ADC back end <NUM> extracts the non-linearities, determines coefficients which can correct the non-linearities, and programs the digital non-linearity correction block <NUM> to correct non-linearities of the VCO ADC <NUM>. The calibration process can operate in the background, and can update the coefficients periodically or from time to time to provide adaptive calibration.

<FIG> illustrates a digital non-linearity calibration block <NUM> and a scheme programming the digital non-linearity calibration block <NUM>, according to some embodiments of the disclosure. The CT VCO ADC back end <NUM> includes a replica VCO ADC <NUM> to process a known signal. The replica VCO ADC <NUM> comprises a signal path (and circuitry) that is identical to the VCO ADC <NUM>. However, the replica VCO ADC <NUM> does not have a digital non-linear calibration block. The replica VCO ADC <NUM> receives the known signal generated by a signal generator <NUM>, and converts the known signal (e.g., a known analog signal) into a digital output. Furthermore, the CT VCO ADC back end <NUM> includes a calibration unit <NUM> to derive coefficients of the digital non-linearity correction block <NUM> based on the digital output of the replica VCO ADC <NUM> and the known signal.

The replica VCO ADC <NUM> can receive a differential input voltage of zero (e.g., a constant, midscale input signal), and the signal generator <NUM> can be a DAC (receiving a known signal sequence) to inject a known signal into the replica VCO ADC <NUM>. The known signal can include a calibration sequence that can be used to extract the non-linearities of the VCO ADC <NUM>.

In some embodiments, the calibration sequence can include a sum of independent, zero-mean, pseudo-random sequences. The digital output of the VCO ADC <NUM> can be correlated with the pseudo-random sequences to extract the non-linearities of the system. In some embodiments, the calibration sequence includes a sum of three pseudo-random sequences: k<NUM>[n] + k<NUM>[n] + k<NUM>[n], and the digital output of the VCO ADC <NUM> is correlated (separately) with k<NUM>[n], k<NUM>[n] · k<NUM>[n], and k<NUM>[n] · k<NUM>[n] · k<NUM>[n]. The result of the correlations yields coefficients that can be used to correct second-order, third-order, and other higher-order non-linearities. The calibration unit <NUM> can use the coefficients to compute a corrected digital output values into look-up table of the digital non-linearity calibration block <NUM>, where the look-up table maps possible values of the digital output of VCO ADC <NUM> to respective corrected digital output values.

In some embodiments, the calibration unit <NUM> can determine measure the VCO center frequency so that the VCO center frequency of the VCO ADC <NUM> can be tuned accordingly.

Calibration using a replica VCO ADC <NUM> can be limited, since the calibrations depend on how well the replica VCO ADC <NUM> matches the VCO ADC <NUM>. If calibration using a replica VCO ADC <NUM> is insufficient to address even-order non-linearities (e.g., second-order non-linearities), it is possible to implement the VCO ADC <NUM> in a pseudo-differential manner to suppress the even-order non-linearities (at the cost of higher area and power consumption).

<FIG> shows an exemplary implementation of a CT VCO ADC back end <NUM> having two pseudo-differential signal paths and a replica signal path, according to some embodiments of the disclosure. Specifically, the VCO ADC <NUM> has two pseudo-differential signal paths, and the replica VCO ADC <NUM> has a replica signal path.

The two pseudo-differential signal paths share a (same) first voltage-to-current converter <NUM>, where the first voltage-to-current converter <NUM> receives the amplified residue signal va_res from the CT residue generation front end <NUM>. The amplified residue signal Va_res is a differential signal having a positive signal and a negative signal. A first pseudo-differential signal path has a first ring oscillator <NUM> to process the positive signal from the first voltage-to-current converter <NUM>. The first ring oscillator <NUM> of the first pseudo-differential signal path is followed by a ring sampler and phase decoder, shown as DFFs <NUM>. The DFFs <NUM> is followed by a differentiator <NUM>. The differentiator is <NUM> is followed by a digital non-linearity calibration block <NUM>. A second pseudo-differential signal path has a second ring oscillator <NUM> to process the negative signal from the first voltage-to-current converter <NUM>. The second ring oscillator <NUM> of the second pseudo-differential signal path is followed by a ring sampler and phase decoder, shown as DFFs <NUM>. The DFFs <NUM> is followed by a differentiator <NUM>. The differentiator is <NUM> is followed by a digital non-linearity calibration block <NUM>. The outputs of the first pseudo-differential signal path and the second pseudo-differential signal path (e.g., outputs of the digital non-linearity calibration block <NUM> and digital non-linearity calibration block <NUM>) are combined at a first node <NUM>. Specifically, the output of the first pseudo-differential signal path is subtracted by the output of the second pseudo-differential signal path to form a final output of the VCO ADC <NUM>. The subtraction or differencing can suppress even-order non-linearities, because components that are common to both pseudo-differential signal paths would be cancelled out.

The replica VCO ADC <NUM> with the replica signal path has the same/identical circuitry as the pseudo-differential signal paths (except for the replica signal path does not have a digital non-linearity calibration block). The replica VCO ADC <NUM> has a voltage-to-current converter <NUM> receiving a differentially zero input. The signal generator <NUM> can inject a (current) signal to the output of the voltage-to-current converter <NUM>. The replica signal path includes a ring oscillator <NUM>, DFFs <NUM>, and differentiator <NUM>. The output of the differentiator <NUM> is provided to calibration unit <NUM> to perform calibration operations as described in relation to <FIG>.

Quantization noise can significantly degrade the performance of the CT VCO ADC back end <NUM>. The degradation in performance, in the form of spurious tones correlated with the input signal, is particularly serious for low amplitude signals. Dithering the input signal with a sequence that is white and uniformly distributed over a range of frequencies that is uncorrelated with the input signal can spread the tones into the noise floor and ameliorate the input signal dependent distortions. However, injection of a dither to a VCO ADC can degrade signal-band SNR because the dither is not subject to the noise transfer function of a VCO ADC. To address the degradation in signal-band SNR, a self-cancelling dither scheme is used. A dither is added to the input of one pair of pseudo-differential signal paths, and the same dither is subtracted from the input of another pair of pseudo-differential signal paths. The outputs of the pairs of pseudo-differential signal paths are summed. The undesirable components that are introduced by the dither have equal magnitudes and opposite polarities. When the outputs of the pairs of pseudo-differential signal paths are summed, the undesirable components introduced by the dither are cancelled, the signal components add in amplitude, and the noise components add in power. Accordingly, the SNR is improved significantly through the self-dithering scheme.

<FIG> shows an exemplary implementation of a CT VCO ADC back end <NUM> having two pairs of pseudo-differential signal paths, according to some embodiments of the disclosure. A first pair of pseudo-differential signal paths follow the first voltage-to-current converter <NUM>. The first and second pseudo-differential signal paths process a positive signal from the voltage-to-current converter <NUM> and a negative signal from the voltage-to-current converter <NUM>, respectively. The outputs from the first and second pseudo-differential signal paths are differenced at node <NUM>. A second pair of pseudo-differential signal paths follow a second voltage-to-current converter <NUM>. The second voltage-to-current converter <NUM> receives the amplified residue signal va_res from the CT residue generation front end <NUM>. A third pseudo-differential signal path has a third ring oscillator <NUM> to process the positive signal from the second voltage-to-current converter <NUM>. The third ring oscillator <NUM> of the third pseudo-differential signal path is followed by a ring sampler and phase decoder, shown as DFFs <NUM>. The DFFs <NUM> is followed by a differentiator <NUM>. The differentiator is <NUM> is followed by a digital non-linearity calibration block <NUM>. The fourth pseudo-differential signal path has a fourth ring oscillator <NUM> to process the negative signal from the second voltage-to-current converter <NUM>. The fourth ring oscillator <NUM> of the fourth pseudo-differential signal path is followed by a ring sampler and phase decoder, shown as DFFs <NUM>. The DFFs <NUM> is followed by a differentiator <NUM>. The differentiator is <NUM> is followed by a digital non-linearity calibration block <NUM>. The outputs of the third pseudo-differential signal path and the fourth pseudo-differential signal path (e.g., outputs of the digital non-linearity calibration block <NUM> and digital non-linearity calibration block <NUM>) are combined at a second node <NUM>. Specifically, the output of the third pseudo-differential signal path is subtracted by the output of the fourth pseudo-differential signal path. The subtraction or differencing can suppress even-order non-linearities, because components that are common to both pseudo-differential signal paths would be cancelled out.

The outputs of the first node <NUM> and the output of the second node <NUM> are combined by a third node <NUM>. Specifically, the outputs of the first pair of pseudo-differential signal paths and the second pair of pseudo-differential signal paths are summed at the third node <NUM>. To inject self-cancelling dither, the VCO ADC <NUM> further includes first circuitry <NUM> to inject dither having a first polarity to the first pseudo-differential signal path and the second pseudo-differential signal path, and second circuitry <NUM> to inject dither having a second polarity opposite to the first polarity to the third pseudo-differential signal path and the fourth pseudo-differential signal path. The first circuitry <NUM> can be a signal generator (e.g., a DAC receiving a dither sequence and outputting the dither having the first polarity) to add a dither to the inputs of the first pair of pseudo-differential signal paths. The second circuitry <NUM> can be a signal generator (e.g., a DAC receiving a same dither sequence but outputting the dither having the second polarity) to remove the same dither at the inputs of the second pair of pseudo-differential signal paths.

A SQNR over a signal bandwidth of a VCO ADC increases with a number of quantization levels and an oversampling ratio. A VCO ADC's number of quantization levels is determined by a minimum delay through each one of the delay elements. To decrease the minimum delay and improve SQNR, the ring oscillator can be modified to include two interpolated ring oscillators, e.g., two ring oscillators injection locked together, or two phase shifted ring oscillators. <FIG> shows an exemplary phase interpolated ring oscillator, according to some embodiments of the disclosure. A ring oscillator in a VCO ADC signal path can include a first injection locked ring oscillator <NUM> and a second injection locked ring oscillator <NUM>. In the example shown, the first injection locked ring oscillator <NUM> has <NUM> delay elements, and the second injection locked ring oscillator <NUM> has <NUM> delay elements. The first injection locked ring oscillator <NUM> and the second injection locked ring oscillator <NUM> are quadrature-coupled together via a resistor network <NUM> to lock the first injection locked ring oscillator <NUM> and the second injection locked ring oscillator <NUM><NUM>° out of phase with each other. The result is a phase interpolated ring oscillator having <NUM> delay elements, with half the minimum delay. Accordingly, the SQNR and bandwidth is significantly improved. Having a high bandwidth, phase interpolated, CT VCO ADC back end <NUM> can benefit the overall wide bandwidth response of the VCO-based pipelined ADC.

The architecture of the VCO-based CT pipelined ADC allows for the CT residue generation front end <NUM> and the VCO ADC back end <NUM> to have different sampling rates. Oversampling ratio and sampling rate of a VCO ADC can affect the SQNR of a VCO ADC. To further improve SQNR, the CT VCO ADC back end <NUM> is clocked by a doubled or higher (e.g., 2x, 4x, 6x, 8x, etc.) clock frequency or tuned/locked to doubled or higher (e.g., 2x, 4x, 6x, 8x, etc.) clock frequency with respect to the clock frequency driving the CT residue generation front end <NUM>. <FIG> shows an exemplary implementation of a VCO-based CT pipelined ADC <NUM> having a CT residue generation front end <NUM> and an oversampling VCO ADC back end <NUM>, according to some embodiments of the disclosure. The CT residue generation front end <NUM> is driven by a first clock signal having a first clock frequency fck. For instance, the quantizer <NUM> is driven by fck. The DAC <NUM> can be driven by fck, or a suitable multiple of fck if DAC pulse shaping (as illustrated in <FIG>) is implemented. The CT VCO ADC back end <NUM> is driven by a second clock signal having a second clock frequency K · fck that is K times the first clock frequency, where K is at least two, or an integer multiple of <NUM>. When the CT VCO ADC back end <NUM> is driven by the higher, second clock frequency, the CT VCO ADC back end <NUM> includes a decimation filter <NUM> to reduce the sample rate to match the sample rate of the CT residue generation front end <NUM>, and an anti-aliasing filter (e.g., a low pass filter) to remove unwanted images in the output spectrum. Tuning/locking to a doubled or higher (e.g., 2x, 4x, 6x, 8x, etc.) clock frequency can improve linearity of the CT VCO ADC back end <NUM>. Additionally, an integer multiple of the clock frequency maximizes the range of phase detection of the CT VCO ADC back end <NUM>.

In some embodiments, the CT VCO ADC back end <NUM> can be modified to implement a higher-order structure to extend noise shaping benefits of the CT VCO ADC back end <NUM>. <FIG> shows an exemplary implementation of a higher-order CT VCO ADC back end <NUM>, according to some embodiments of the disclosure. Specifically, the CT VCO ADC implements third-order noise shaping. The CT VCO ADC back end <NUM> comprises multiple oscillators (in this example, three oscillators) and one or more feedback path(s) to implement multi-order noise shaping. In the example shown, the CT VCO ADC back end <NUM> includes a first VCO <NUM>, an up-down counter <NUM>, a digitally-controlled-oscillator (DCO) <NUM>, an up-down counter <NUM>, a DCO <NUM>, and sampling register <NUM>. The second digital output DVCOADC generated by the sampling register <NUM> is provided to up-down counter <NUM>, up-down counter <NUM>, and up-down counter <NUM> as feedback. Additionally, the second digital output DVCOADC generated by the sampling register <NUM> is provided to node <NUM> as feedback with a gain of g. The overall feedback of the second digital output DVCOADC to selected locations, as illustrated by the FIGURE, implements higher-order noise shaping.

The VCO-based CT pipelined ADC can be implemented with no feedback. This is in contrast to delta-sigma ADCs or successive-approximation-register ADCs which has feedback paths. In other words, the CT residue generation front end <NUM> and the CT VCO ADC back end <NUM> only has feedforward paths. There is no overall feedback from the output of the CT VCO ADC back end <NUM> back to the input of the CT residue generation front end <NUM>. This architecture has several benefits. Not having feedback means that it is more practical and easier to include signal processing that has a signal latency. The signal processing includes digital signal processing of digital signals of the CT residue generation front end <NUM> and the CT VCO ADC back end <NUM>. The signal processing, often used with VCO ADCs, can include digital non-linearity correction, and over-range correction. Moreover, feedback paths can dramatically change the stability and transfer function of an ADC. In some cases, feedback paths can limit the bandwidth of the ADC. Also, having no feedback paths guarantees the stability of the VCO-based CT pipelined ADC.

Not having feedback also means that the VCO-based CT pipelined ADC is modular. An ADC architecture with feedback paths cannot be modified easily without significant redesign of the ADC. The modularity also allows for re-configurability of the VCO-based CT pipelined ADC. <FIG> shows an exemplary implementation of a VCO-based CT pipelined ADC <NUM> having a re-configurable CT residue generation front end <NUM> and a CT VCO ADC back end <NUM>, according to some embodiments of the disclosure. The CT residue generation front end <NUM> is cascaded and followed by the CT VCO ADC back end <NUM>. The CT residue generation front end <NUM> generates an amplified residue signal va_res. The CT residue generation front end <NUM> can include N cascaded CT residue generation stages <NUM><NUM>,. The CT residue generation front end <NUM> quantizes an analog input signal vin and generates digital signals D<NUM>,. DN and the amplified residue signal va_res. Each CT residue generation stage can include a quantizer, a DAC, a delay circuit, node, and a residue amplifier. The respective quantizers in the CT residue generation stage generates respective digital signals D<NUM>,. The respective residue amplifiers in the CT residue generation stage generates respective amplified residue signals. The CT VCO ADC back end <NUM> quantizes the amplified residue signal va_res and generates digital signal DVCOADC. The digital signal reconstruction filter <NUM> filters digital signals D<NUM>,. DN from the residue generating stages and the second digital signal DVCOADC, and generates a final digital signal DOUT. The digital signal reconstruction filter <NUM> can be programmed in a manner as previously described with <FIG> (with some differences).

Since there are no feedback paths within or between the cascaded CT residue generation stages <NUM><NUM>,. <NUM>N, and there is no overall feedback from the CT VCO ADC back end <NUM> to the CT residue generation front end <NUM>, the number of cascaded CT residue generation stages and the parameters for each cascaded CT residue generation stage can be modified easily. For instance, a circuit designer can change the number of cascaded CT residue generation stages and the parameters for each cascaded CT residue generation stage based on target performance metrics such as: power consumption, noise, distortion, silicon area, and digital signal processing complexity. In other words, stages can be added or removed easily to achieve certain target performance metrics. Increasing the number of cascaded CT residue generation stages can provide better anti-aliasing, better SNR, better NSD by impedance scaling.

Additionally, modularity allows for re-configurability on-chip. This means that an integrated circuit can include N residue generation stages in the CT residue generation front end <NUM>, and switches or a switching network (e.g., transistors) can be provided to the inputs and/or outputs of the N residue generation stages to configure or re-configure the signal chain in the CT residue generation front end <NUM> and change the number of residue generation stages <NUM><NUM>,. <NUM>N being used, in cascade, to quantize the analog input signal vin and to generate the amplified residue signal va_res. Configurable/controllable/programmable routing that is internal and/or external to silicon die or integrated circuit package in which the VCO-based CT pipelined ADC <NUM> can be used to configure or re-configure the number of residue generation stages <NUM><NUM>,. <NUM>N being used to quantize the analog input signal vin and to generate the amplified residue signal va_res. Controller <NUM> can control such circuitry that can control the number of residue generation stages being used, and thus re-configure the architecture of the VCO-based CT pipelined ADC <NUM>. In some embodiments, the controller <NUM> can re-configure connections for the residue generation stages to change a number of cascaded CT residue generation stages <NUM><NUM>,. <NUM>N being used to generate the amplified residue signal va_res.

<FIG> is a flow diagram illustrating a method for pipelined analog-to-digital conversion, according to some embodiments of the disclosure. In <NUM>, a CT front end (e.g., a CT residue generation front end <NUM>) generates a first digital signal (e.g., D<NUM>) representing an analog input signal (e.g., vin), and a residue signal representing a difference between a delayed version of the analog input signal and a reconstructed analog signal generated from the first digital signal. In <NUM>, a residue amplifier amplifies the residue signal to generate an amplified residue signal (e.g., va_res). In <NUM>, a VCO ADC back end (e.g., CT VCO ADC back end <NUM>) samples phase of the amplified residue signal, and generates a second digital signal (e.g., DVCOADC) based on the phase of the amplified residue signal. In <NUM>, a digital signal reconstruction filter (e.g., a digital signal reconstruction filter <NUM>) filters the first digital signal and the second digital signal. In <NUM>, the digital signal reconstruction filter combines filtered versions of the first digital signal and the second digital signal to generate a final digital output.

In some embodiments, the method further includes delaying, by a delay circuit (e.g., delay circuit <NUM>), the analog input signal. The response of the delay circuit matches a response of a signal path having a quantizer and a digital-to-analog-converter. Examples of such embodiments are illustrated in <FIG>, <FIG>, and <FIG>.

In some embodiments, the method further includes injecting a dither (e.g., LFSR of <FIG>) at an input of a residue amplifier amplifying the residue signal. The method can further include extracting, based on the dither and the second digital signal, a signal transfer function of the residue amplifier, and a signal transfer function of the VCO ADC back end. The method can further include programming a first filter to filter the first digital signal and/or a second filter to filter the second digital signal based on a signal transfer function of a residue amplifier amplifying the residue signal, and a signal transfer function of the VCO ADC back end. An example of such embodiments is illustrated in <FIG>.

In some embodiments, the method further comprises driving the CT front end with a first clock signal having a first clock frequency, and driving the VCO ADC back end with a second clock signal having a second clock frequency that is at least two times the first clock frequency. The method can further include decimating a digital output of the VCO ADC back end, and filtering a decimated version of the digital output of the VCO ADC back end by an anti-aliasing filter to generate the second digital signal. An example of such embodiments is illustrated in <FIG>.

In some embodiments, the method further comprises adjusting a number of residue generation stages being used in the continuous-time front end to generate the amplified residue signal. An example of such embodiments is illustrated in <FIG>.

Example <NUM> is a pipelined analog-to-digital converter (ADC), comprising: a continuous-time residue generation front end to quantize an analog input signal and generate a first digital signal and an amplified residue signal; a voltage-controlled-oscillator (VCO) ADC back end to quantize the amplified residue signal and generate a second digital signal; and a digital signal reconstruction filter to filter the first digital signal and the second digital signal and to generate a final digital signal.

In Example <NUM>, the pipelined ADC of Example <NUM> can optionally include the continuous-time residue generation front end comprising: a quantizer to generate the first digital signal; a digital-to-analog converter to receive the first digital signal and generate a first reconstructed analog signal; and a delay circuit to delay a first analog input signal to the quantizer and generate a first delayed analog input signal, wherein a response of the delay circuit matches a response of a signal path having the quantizer and the digital-to-analog-converter.

In Example <NUM>, the pipelined ADC of Example <NUM> can optionally include the delay circuit matching magnitude and phase of the signal path.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the delay circuit comprising a resistor-capacitor lattice.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the delay circuit comprising one or more inductor-capacitor lattices.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the continuous-time residue generation front end further comprising: a node to output a first residue signal representing a difference between the first delayed analog input signal and the first reconstructed analog signal.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the continuous-time residue generation front end comprising: a residue amplifier to amplify a residue signal and to generate the amplified residue signal.

In Example <NUM>, the pipelined ADC of Example <NUM> can optionally include the residue amplifier comprising has a second or higher-order frequency response.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the digital signal reconstruction filter comprising: a first filter to filter the first digital signal; a second filter to filter the second digital signal; and a node to combine outputs of the first filter and the second filter to generate the final digital signal.

In Example <NUM>, the pipelined ADC of Example <NUM> can optionally include a ratio of the first filter and the second filter corresponding to (<NUM>) a signal transfer function of a residue amplifier generating the amplified residue signal, and (<NUM>) a signal transfer function of the VCO ADC back end.

In Example <NUM>, the pipelined ADC of Example <NUM> or <NUM> can optionally include a ratio of the first filter and the second filter corresponding to (<NUM>) a signal transfer function of a residue amplifier generating the amplified residue signal, (<NUM>) a signal transfer function of the VCO ADC back end, (<NUM>) a noise transfer function of the CT residue generation front end.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the continuous-time residue generation front end comprising: a residue amplifier to amplify a residue signal and to generate the amplified residue signal; and circuitry to inject a dither at an input of the residue amplifier; and the pipelined ADC further comprising: a correlator to cross-correlate the dither and the second digital signal to extract (<NUM>) a signal transfer function of a residue amplifier generating the amplified residue signal, and (<NUM>) a signal transfer function of the VCO ADC back end.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the continuous-time residue generation front end comprising: a quantizer to generate the first digital signal; an upsampling block to upsample the first digital signal; a filter to filter an output of the upsampling block; and a digital-to-analog converter to receive an output of the filter and generate a first reconstructed analog signal.

In Example <NUM>, the pipelined ADC of Example <NUM> can optionally include: the quantizer operates at a first rate; the digital-to-analog converter operates at a second rate; and the second rate is the first rate multiplied an upsampling factor of the upsampling block.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the VCO ADC back end comprising: a digital non-linearity correction block to correct non-linearities of the VCO ADC back end.

In Example <NUM>, the pipelined ADC of Example <NUM>, can optionally include the VCO ADC back end comprising: a replica VCO ADC to process a known signal; and a calibration unit to derive coefficients of the digital non-linearity correction filter based on a digital output of the replica VCO ADC and the known signal.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the VCO ADC back end comprising: (<NUM>) a first voltage-to-current converter to receive the amplified residue signal; (<NUM>) a first signal path having a first ring oscillator to process a positive signal from the first voltage-to-current converter; (<NUM>) a second signal path having a second ring oscillator to process a negative signal from the first voltage-to-current converter; and (<NUM>) a first node to combine outputs of the first signal path and the second signal path.

In Example <NUM>, the pipelined ADC of Example <NUM> can optionally include the VCO ADC back end further comprising: (<NUM>) a second voltage-to-current converter to receive the amplified residue signal; (<NUM>) a third signal path having a third ring oscillator to process the positive signal from the second voltage-to-current converter; (<NUM>) a fourth signal path having a fourth ring oscillator to process the negative signal from the second voltage-to-current converter; and (<NUM>) a second node to combine outputs of the third signal path and the fourth signal path; and (<NUM>) a third node to combine outputs of the first node and the second node.

In Example <NUM>, the pipelined ADC of Example <NUM> can optionally include the VCO ADC back end further comprising: (<NUM>) first circuitry to inject dither having a first polarity to the first signal path and the second signal path, and (<NUM>) second circuitry to inject dither having a second polarity opposite to the first polarity to the third signal path and the fourth signal path.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the VCO ADC back end comprising two injection locked ring oscillators.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the continuous-time residue generation front end is driven by a first clock signal having a first clock frequency; and the VCO ADC back end is driven by a second clock signal having a second clock frequency that is at least two times the first clock frequency.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the VCO ADC comprising a decimation filter and an anti-aliasing filter.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the VCO ADC back end comprising multiple oscillators and one or more feedback path(s) to implement multi-order noise shaping.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the continuous-time residue generation front end comprising cascaded continuous-time residue generation stages.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include a number of residue generation stages being used to quantize the analog input signal and to generate the amplified residue signal is configurable by a controller.

In Example <NUM>, the pipelined ADC of any one of Examples <NUM>-<NUM> can optionally include the VCO ADC back end comprises the following in series: a ring oscillator, a phase-to-digital converter, and a differentiator.

Example <NUM>, a method for pipelined analog-to-digital conversion, comprising: generating, by continuous-time front end, a first digital signal representing an analog input signal, and a residue signal representing a difference between a delayed version of the analog input signal and a reconstructed analog signal generated from the first digital signal; amplifying the residue signal to generate an amplified residue signal; sampling, by voltage-controlled-oscillator (VCO) analog-to-digital converter (ADC) back end, phase of the amplified residue signal; generating, by the VCO ADC back end, a second digital signal based on the phase of the amplified residue signal; filtering the first digital signal and the second digital signal; and combining filtered versions of the first digital signal and the second digital signal to generate a final digital output.

In Example <NUM>, the method of Example <NUM> can optionally include delaying, by a delay circuit, the analog input signal, wherein a response of the delay circuit matches a response of a signal path having a quantizer and a digital-to-analog-converter.

In Example <NUM>, the method of Example <NUM> or <NUM> can optionally include injecting a dither at an input of a residue amplifier amplifying the residue signal.

In Example <NUM>, the method of Example <NUM> can optionally include extracting, based on the dither and the second digital signal a signal transfer function of the residue amplifier, and a signal transfer function of the VCO ADC back end.

In Example <NUM>, the method of any one of Examples <NUM>-<NUM> can optionally include: programming a first filter to filter the first digital signal and/or a second filter to filter the second digital signal based on a signal transfer function of a residue amplifier amplifying the residue signal, and a signal transfer function of the VCO ADC back end.

In Example <NUM>, the method of any one of Examples <NUM>-<NUM> can optionally include: driving the continuous-time front end with a first clock signal having a first clock frequency; and driving the VCO ADC back end with a second clock signal having a second clock frequency that is at least two times the first clock frequency.

In Example <NUM>, the method of Example <NUM> can optionally include: decimating a digital output of the VCO ADC back end; and filtering a decimated version of the digital output of the VCO ADC back end by an anti-aliasing filter to generate the second digital signal.

In Example <NUM>, the method of any one of Examples <NUM>-<NUM> can optionally include: adjusting a number of residue generation stages being used in the continuous-time front end to generate the amplified residue signal.

Example <NUM> is a modular pipelined ADC, comprising: a continuous-time residue generation front end to generate an amplified residue signal, wherein the continuous-time residue generation front end comprises a plurality of residue generating stages in cascade; a voltage-controlled-oscillator (VCO) ADC back end to quantize the amplified residue signal and generate a second digital signal; and a digital signal reconstruction filter to filter digital signals from the residue generating stages and the second digital signal, and to generate a final digital signal.

In Example <NUM>, the modular pipelined ADC of Example <NUM> can optionally include the continuous-time residue generation front end is to quantize an analog input signal and generate a plurality of digital signals and the amplified residue signal.

In Example <NUM>, the modular pipelined ADC of Example <NUM> or <NUM> can optionally include a controller to re-configure connections for the residue generation stages to change a number of residue generation stages being used to generate the amplified residue signal.

Example A is an apparatus comprising means for implementing and/or carrying out the methods of any one of Examples <NUM>-<NUM> and/or any of the functionalities described herein.

The present architecture for a VCO-based CT pipelined ADC are particularly suitable for high speed, high precision applications. Applications which can greatly benefit from the architecture include: instrumentation, testing, spectral analyzers, military purposes, radar, wired or wireless communications, mobile telephones (especially because standards continue to push for higher speed communications), and base stations.

In some embodiments, VCO-based CT pipelined ADC can be implemented with an on-chip microprocessor (i.e., on-chip with the ADC, executing instructions/firmware provided to the on-chip microprocessor) and/or dedicated on-chip digital hardware, to carry out digital signal processing functions. In various other embodiments, the digital filters or digital functionalities may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor architectures.

All of the specifications, dimensions, and relationships outlined herein (e.g., the number of processors, logic operations, etc.) have only been offered for purposes of example and teaching only. Such information may be varied considerably without departing from the scope of the appended claims. The specifications apply only to one non-limiting example and, accordingly, they should be construed as such. In the foregoing description, example embodiments have been described with reference to particular processor and/or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.

Note that in this Specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment", "example embodiment", "an embodiment", "another embodiment", "some embodiments", "various embodiments", "other embodiments", "alternative embodiment", and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.

The functions related to pipelined analog-to-digital conversion, such as the processes illustrated by <FIG>, illustrate only some of the possible functions that may be executed by, or within, the circuits illustrated in the FIGURES or circuits coupled to the systems illustrated in the FIGURES (e.g., digital circuitry or an on-chip microprocessor). Some of these operations may be deleted or removed where appropriate, or these operations may be modified or changed considerably without departing from the scope of the present disclosure. In addition, the timing of these operations may be altered considerably. The preceding operational flows have been offered for purposes of example and discussion. Substantial flexibility is provided by embodiments described herein in that any suitable arrangements, chronologies, configurations, and timing mechanisms may be provided without departing from the teachings of the present disclosure.

Claim 1:
A pipelined analog-to-digital converter, ADC, (<NUM>) comprising:
a continuous-time, CT, residue generation front end (<NUM>) to quantize an analog input signal and generate a first digital signal and an amplified residue signal, wherein the CT residue generation front end is driven by a first clock frequency fck and comprises:
a quantizer (<NUM>) to generate the first digital signal, the quantizer being driven by the first clock frequency fck, and further being a flash analog-to-digital converter, ADC;
a digital-to-analog converter (<NUM>) to receive the first digital signal and generate a first reconstructed analog signal;
a delay circuit (<NUM>) for delaying the analog input signal to generate a first delayed analog input signal, wherein a response of the delay circuit matches a response of a signal path having the quantizer and the digital-to-analog converter;
a node (<NUM>) to output a first residue signal representing a difference between the first delayed analog input signal and the first reconstructed analog signal; and
a residue amplifier (<NUM>) to amplify the first residue signal to generate the amplified residue signal;
the pipelined analog-to-digital converter (<NUM>) further comprising:
a voltage-controlled-oscillator, VCO, ADC back end (<NUM>) to quantize the amplified residue signal and generate a second digital signal, wherein the VCO ADC back end is driven by a second clock frequency K·fck, wherein K is an integer of <NUM> or more; and
a digital signal reconstruction filter (<NUM>) to filter the first digital signal and the second digital signal and to generate a final digital signal.