Patent Description:
An FPA module typically includes a Read Out Integrated Circuit (ROIC) and a detector hybridized to the ROIC to make a Sensor Chip Assembly (SCA). The SCA is mounted onto a pedestal. A motherboard with cabling and capacitors is also mounted to the pedestal and surrounds the SCA. The SCA is electrically connected to the motherboard by wire bonds.

In greater detail, the FPA module can include a relatively thick substrate with an upper surface and a recess formed in a central region of the upper surface. The recess can be characterized with a bottom surface and sidewalls extending vertically upwardly from the bottom surface to the upper surface. An integrated circuit (IC) layer sits on the bottom surface within the recess and has an upper IC layer surface disposed above the upper surface of the substrate. Sidewalls of the IC layer are displaced from the sidewalls of the recess such that a width of the recess exceeds a width of the IC layer. A detector layer is disposed above the IC layer and is communicative with the IC layer by way of connectors arrayed on the lower surface of the IC layer and corresponding connectors arrayed on the upper surface of the IC layer. Capacitors to support operations of the IC layer are operably disposed on the upper surface of the substrate outside of the recess and are connected to the IC layer by wire bonds extending curvi-linearly from the capacitors, across the space between the sidewalls of the recess and the sidewalls of the IC layer and to the IC layer.

The capacitors are typically long-lead capacitors and can be expensive. They are also typically installed by hand and the wire bonds are susceptible to damage caused by handling. In order to provide space for the capacitors, a size of the substrate must be increased and an overall size of the FPA module is correspondingly increased. This results in a physically large overall size and a substantially increased heat load module. In addition, in some cases, additional capacitors are installed in FPA modules to compensate for capacitor wire bond inductance. These additional capacitors can exacerbate the issues laid out herein.

<CIT> discloses a focal plane array having a plurality of detectors, a plurality of unit cell sections, each section being fed by charge produced by a corresponding detector for producing a sequence of frames; and a plurality of sets of storage sections, each section being coupled to a corresponding one of the unit cells. <CIT> B <NUM> discloses a photodiode array defined in a semiconductor detector chip, and an array of pixel circuits defined in a semiconductor read-out integrated circuit (ROIC) substrate, wherein the detector chip and the ROIC substrate are bonded in a monolithic assembly.

The present invention provides a three-dimensional (3D) stack as recited in claim <NUM>. Optional features are recited in the dependent claims.

The present invention also provides a method of assembling a three-dimensionally (3D) stacked focal plane array (FPA) module as recited in claim <NUM>. Optional features are recited in the dependent claim.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.

As will be described below, a three-dimensionally (3D) stacked read-out integrated circuit (IC) (ROIC) wafer is provided with a bypass capacitor wafer layer. The 3D stacked ROIC wafer includes commercial off the shelf capacitors and requires no capacitor procurement. In addition, the 3D stacked ROIC wafer has a structure which does not include wire bonding and does not exhibit capacitor interference with its detection window. The 3D stacked wafer provides for improved reliability and improved signal quality.

With reference to <FIG>, a 3D stacked sensor <NUM> is provided and is configured as an FPA module with a reduced size, thermal weight and footprint. The 3D stacked sensor <NUM> includes a detector layer <NUM>, a capacitor layer <NUM> and an IC layer <NUM>. The IC layer <NUM> is vertically stacked between the detector layer <NUM> and the capacitor layer <NUM>. As will be described below, a lower surface of the detector layer <NUM> and an upper surface of the IC layer <NUM> are each hybridized to one another and an upper surface of the capacitor layer <NUM> and a lower surface of the IC layer <NUM> are each hybridized to one another. As such, the detector layer <NUM> is communicative with the IC layer <NUM> and the capacitor layer <NUM> is communicative with the IC layer <NUM>. The 3D stacked sensor <NUM> can further include a first layer of one or more adhesives <NUM>, which is vertically interposed between the detector layer <NUM> and the IC layer <NUM>, and a second layer of one or more adhesives <NUM>, which is vertically interposed between the IC layer <NUM> and the capacitor layer <NUM>.

As shown in <FIG>, the detector <NUM> includes a detector body <NUM>, a first upper (major) surface <NUM> that is receptive of incident electro-magnetic (EM) signals, a first lower (major) surface <NUM> opposite the first upper surface <NUM> and first connectors <NUM>. The detector layer <NUM> can be provided as a detector array with an array of detector elements <NUM> suspended within a support element <NUM> that can be formed of dielectric material for example. The first connectors <NUM>, which can be provided as an array of connectors or pads, are arrayed along the first lower surface <NUM>.

As shown in <FIG> and <FIG>, the capacitor layer <NUM> includes a capacitor layer body <NUM>, a second upper (major) surface <NUM>, capacitors <NUM> and second connectors <NUM>. The capacitors <NUM> are suspended within a support structure <NUM> of the capacitor layer body <NUM>, which is formed of dielectric material. The second connectors <NUM> can be provided as an array of connectors or pads, are respectively communicative with corresponding capacitors <NUM> and are arrayed along the second upper surface <NUM>.

The capacitors <NUM> can be provided as commercial off the shelf (COTS) capacitors. In any case, an upper surface <NUM> of each of the capacitors <NUM> is substantially coplanar with the second upper surface <NUM>. In some cases, each of the capacitors <NUM> is substantially a same size and shape as all of the other capacitors <NUM>.

As shown in <FIG> and <FIG>, the IC layer <NUM> includes an IC layer body <NUM>, a third upper (major) surface <NUM>, a second lower (major) surface <NUM>, third connectors <NUM> and fourth connectors <NUM>. The third connectors <NUM> can be provided as an array of connectors or pads, are respectively communicative with corresponding first connectors <NUM> within the first layer of adhesive <NUM> and are arrayed along the third upper surface <NUM>. The fourth connectors <NUM> can be provided as an array of connectors or pads, are respectively communicative with corresponding second connectors <NUM> within the second layer of adhesive <NUM> and are arrayed along the second lower surface <NUM>.

In accordance with embodiments, the IC layer body <NUM> can include a dielectric layer <NUM>, which can be formed of dielectric material, a ROIC <NUM> that is disposed underneath the dielectric layer <NUM> and extends along the second lower surface <NUM> and contact vias <NUM>. The contact vias <NUM> extend from the second lower surface <NUM> to the third upper surface <NUM> through the ROIC <NUM> and the dielectric layer <NUM> and are respectively communicative with corresponding third connectors <NUM> and fourth connectors <NUM>.

The detector layer <NUM>, the capacitor layer <NUM> and the IC layer <NUM> are stacked vertically with the IC layer vertically interposed between the detector layer <NUM> and the capacitor layer <NUM>. In some cases, the detector layer <NUM> can include detector layer sidewalls <NUM> (see <FIG>), the capacitor layer <NUM> can include capacitor layer sidewalls <NUM> (see <FIG>) and the IC layer <NUM> can include IC layer sidewalls <NUM> (see <FIG>) with the detector layer sidewalls <NUM>, the capacitor layer sidewalls <NUM> and the IC layer sidewalls <NUM> being substantially coplanar with one another. In some cases, a footprint FP (see <FIG>, <FIG>) or a width W (see <FIG>) of each of the detector layer <NUM>, the capacitor layer <NUM> and the IC layer <NUM> is substantially common to the detector layer <NUM>, the capacitor layer <NUM> and the IC layer <NUM>.

As shown in <FIG>, <FIG>, to the extent that the detector layer <NUM> includes an array of detector elements <NUM>, the array of detector elements <NUM> can be arranged in a formation with a detector footprint DFP. The detector footprint DFP can be smaller in one or more dimensions than the footprint FP. In addition, the capacitors <NUM> of the capacitor layer <NUM> and the contact vias <NUM> of the IC layer <NUM> can be arranged in respective formations that are encompassed within the detector footprint DFP.

In accordance with embodiments and as shown in <FIG>, connector-component and connector-connector connections do not require perfect alignments. That is, the second connectors <NUM> are respectively communicative with and aligned or partially misaligned relative to the corresponding capacitors <NUM>, the third connectors <NUM> are respectively communicative with and aligned or partially misaligned relative to the corresponding first connectors <NUM> and corresponding contact vias <NUM> and the fourth connectors <NUM> are respectively communicative with and aligned or partially misaligned relative to corresponding second connectors <NUM>.

In accordance with further embodiments and with reference to <FIG>, a method of assembling a three-dimensionally (3D) stacked focal plane array (FPA) module is provided. The method includes forming a detector layer that includes a detector array (<NUM>), forming a capacitor layer that includes capacitors (<NUM>) and vertically stacking an integrated circuit (IC) layer between the capacitor layer and the detector layer (<NUM>). The method further includes hybridizing each of the detector layer and the IC layer to one another to enable communication between the detector array and the IC layer (<NUM>) and hybridizing each of the capacitor layer and the IC layer to one another to enable communication between the capacitors and the IC layer (<NUM>).

Technical effects and benefits of the present invention are the lowered overall cost of an FPA design, a lowered schedule time for an FPA design, increased reliability and yield. In addition, the present invention does not require procurement of discrete capacitors and eliminates the need for touch-labor in the connection between wire bonds and capacitors.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed.

The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claim 1:
A three-dimensional, 3D, stack (<NUM>), comprising:
a capacitor layer (<NUM>) comprising capacitors (<NUM>) and capacitor layer connectors (<NUM>) respectively communicative with corresponding capacitors (<NUM>); and
an integrated circuit, IC, layer (<NUM>) stacked vertically between the capacitor layer and a detector layer (<NUM>), and hybridized to the detector layer (<NUM>),
the IC layer (<NUM>) comprising IC layer connectors (<NUM>) respectively communicative with corresponding capacitor layer connectors (<NUM>); characterized in that:
the capacitor layer (<NUM>) comprises a capacitor layer body (<NUM>) and an upper surface (<NUM>), and the capacitors are suspended within a support structure (<NUM>) of the capacitor layer body (<NUM>) which is formed of dielectric material, and an upper surface (<NUM>) of each of the capacitors (<NUM>) is coplanar with the upper surface (<NUM>) of the support structure (<NUM>).