Patent Description:
Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others.

Memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, for example, MP3 players, and movie players, among other electronic devices. Data, such as program code, user data, and/or system data, such as a basic input/output system (BIOS), are typically stored in non-volatile memory devices.

Resistance variable memory such as PCRAM includes resistance variable memory cells that can store data based on the resistance of a storage element (e.g., a storage element having a variable resistance). As such, resistance variable memory cells can be programmed to store data corresponding to a target state by varying the resistance level of the resistance variable storage element. Resistance variable memory cells can be programmed to a target state corresponding to a particular resistance, by applying sources of an electrical field or energy, such as positive or negative electrical signals (e.g., positive or negative voltage or current signals) to the cells.

One of a number of states (e.g., resistance states) can be set for a resistance variable memory cell. For example, a single level cell (SLC) may be programmed to one of two states (e.g., logic <NUM> or <NUM>), which can depend on whether the cell is programmed to a resistance above or below a particular level. As an additional example, various resistance variable memory cells can be programmed to one of multiple different states corresponding to respective digit patterns (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.). Such cells may be referred to as multi state cells, multi-digit cells, and/or multilevel cells (MLCs).

The state of the resistance variable memory cell can be determined (e.g., read), for example, by sensing current through the cell responsive to an applied interrogation voltage. The sensed current, which varies based on the resistance of the cell, can indicate the state of the cell (e.g., the binary data stored by the cell). However, the resistance of a programmed resistance variable memory cell can drift (e.g., shift) over time. Resistance drift can result in erroneous sensing of a resistance variable memory cell (e.g., a determination that the cell is in a state other than that to which it was programmed), among other issues.

<CIT> discloses a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data.

In a first aspect of the present invention according to claim <NUM>, an apparatus capable of data state synchronization is provided. In a second aspect of the present invention according to claim <NUM>, a method of providing data state synchronization is provided.

The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

Embodiments of the present disclosure can provide benefits such as reducing erroneous reading of resistance variable memory cells, whose resistance level can drift over time (e.g., after being programmed to a target state). Accordingly, embodiments can improve data reliability and/or data integrity as compared to previous approaches. For example, various previous approaches associated with correcting for resistance drift include tracking resistance drift (e.g., in the background in real time) and "refreshing" cells (e.g., setting the cells back to their target state) based on the amount of time the cells have been in a particular state and/or adjusting sensing threshold voltage levels to accommodate for the drift. Such an approach can require constantly maintaining information regarding drift time and/or can require a constant power supply, which may not be available for various applications such as mobile applications, for example.

Another prior approach can involve always writing all cells of a particular group (e.g., a page of cells) such that all the cells are "set" or "reset" at the same time. Such an approach can be costly in terms of energy consumption by requiring programming of cells that may not require programming pulses, for instance. In contrast, a number of embodiments of the present disclosure can provide data state synchronization in a manner that reduces erroneous reads due to cell resistance drift, while reducing energy consumption as compared to prior approaches. Additionally, various embodiments can provide data state synchronization without tracking drift time, which can provide benefits such as not requiring a constant power supply (e.g., battery power), among other benefits.

In some other prior approaches, data state synchronization may be provided by circuitry located external to the memory device, for example, by circuitry located on a host device and/or by control circuitry located external to the memory device. In such approaches, a status of a physical block address may be updated to a free status prior to writing data to the physical block address. In addition, in such approaches, commands and/or data may be transferred off of the memory device to perform data state synchronization.

In contrast, embodiments herein may allow for data state synchronization to be performed using circuitry located on or within the memory device, which may allow for reduced time and/or processing power in comparison to approaches in which data state synchronization is coordinated or performed by circuitry external to the memory device. Further, embodiments herein may allow for a status of a physical block address to be switched between an invalid status and a valid status without updating the status of the physical block address to a free status, which may simplify data state synchronization. In addition, embodiments herein may allow for data state synchronization to be performed on small managed units (SMUs) as well as large managed units (LMUs). As used herein, LMUs are managed units on the order of <NUM> kilobytes, while SMUs are managed units on the order of <NUM> bytes.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure.

As used herein, designators such as "N" and "M", particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an", and "the" can include both singular and plural referents, unless the context clearly dictates otherwise. In addition, "a number of", "at least one", and "one or more" (e.g., a number of memory cells) can refer to one or more memory cells, whereas a "plurality of" is intended to refer to more than one of such things. Furthermore, the words "can" and "may" are used throughout this application in a permissive sense (e.g., having the potential to, being able to), not in a mandatory sense (e.g., required to).

<FIG> is a block diagram of an apparatus in the form of a computing system <NUM> including a memory system <NUM> capable of providing data state synchronization in accordance with a number of embodiments of the present disclosure. As used herein, a memory system <NUM>, a controller <NUM>, or a memory device <NUM> might also be separately considered an "apparatus. " The memory system <NUM> can be a solid state drive (SSD), for example, and can include a host interface <NUM>, a controller <NUM> (e.g., a sequencer and/or other control circuitry), and a number of memory devices <NUM>, which can serve as a memory for system <NUM> and can be referred to as memory <NUM>.

The controller <NUM> can be coupled to the host <NUM> via host interface <NUM> and to the memory <NUM> via memory interface <NUM>, and can be used to transfer data between the memory system <NUM> and a host <NUM>. The host interface <NUM> can be in the form of a standardized interface. For example, when the memory system <NUM> is used for data storage in a computing system <NUM>, the interface <NUM> can be a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe), or a universal serial bus (USB), among other connectors and interfaces. In general, the memory system <NUM> and the host <NUM> that are coupled to each other via the host interface <NUM> may each have a compatible receptor for passing control, address, data, and other signals via the host interface <NUM>. Similarly, the controller <NUM> and the memory <NUM> may each have a receptor compatible with the memory interface <NUM>. The interface <NUM> may support various standards and/or comply with various interface types (e.g., DDR, ONFI, NVMe, etc.).

Host <NUM> can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host <NUM> can include a system motherboard and/or backplane and can include a number of memory access devices (e.g., a number of processors). Host <NUM> can also be a memory controller, such as where memory system <NUM> is a memory device (e.g., a memory device having an on-die controller).

The controller <NUM> can communicate with the memory <NUM> (which in some embodiments can be a number of memory arrays on a single die) to control data read, write, and erase operations, among other operations. As an example, the controller <NUM> can be on a same die or a different die than a die or dice corresponding to memory <NUM>.

As described above, the controller <NUM> can be coupled to the memory interface <NUM> coupling the controller <NUM> to the memory <NUM>. The controller <NUM> can include, for example, a number of components in the form of hardware and/or firmware (e.g., one or more integrated circuits) and/or software for controlling access to the memory <NUM> and/or for facilitating data transfer between the host <NUM> and memory <NUM>.

The controller <NUM> can include a management component <NUM>. The management component <NUM> can provide and manage information (e.g., data) that can be used to locate data stored in the memory <NUM> and identify the frequency at which addresses (e.g., logical addresses) corresponding to data stored in the memory <NUM> has been accessed (e.g., during program operations). This information can be stored in a table <NUM> (e.g., logical to physical (L2P) address table). For example, the table <NUM> can include logical to physical address mappings and can indicate the frequency at which the physical addresses have been accessed during program operations. In a number of embodiments, the controller <NUM> is configured to select a group of memory cells (e.g., a page) independently of a particular logical address associated with a command (e.g., write command), and locate data associated with the write command in the memory <NUM> by updating and maintaining the logical to physical address table <NUM>.

The memory <NUM> can include a number of memory arrays (not shown), a memory controller <NUM>, error correction code (ECC) circuitry <NUM>, and/or inversion circuitry <NUM>. The ECC circuitry <NUM> and/or the inversion circuitry <NUM> can be located internal to the memory <NUM> and can perform error correction and/or inversion operation, respectively, on data received by the memory <NUM>, as described in more detail in connection with <FIG>, <FIG>, and <FIG>, herein.

The ECC circuitry <NUM> can be configured to generate and/or decode parity bits as part of an error correction operation on data stored by the memory <NUM>. In some embodiments, the ECC circuitry <NUM> may include logic and/or hardware configured to provide error correction functionality to the memory <NUM>. Similarly, the inversion circuitry <NUM> may include logic and/or hardware configured to provide data inversion logic functionality to the memory <NUM>. For example, the inversion circuitry <NUM> may be configured to perform inversion operations as described in more detail herein.

By including the ECC circuitry <NUM> and/or the inversion logic <NUM> on or within the memory <NUM>, some embodiments may allow for parallelization of error correction, data inversion, and/or data state synchronization, as described in more detail in connection with <FIG>, herein. This may allow for write operations performed using the memory <NUM> to be optimized and/or improved in comparison to approaches in which data state synchronization, error correction, and/or data inversion are performed using circuitry external to the memory <NUM>. In addition, by including the ECC circuitry <NUM> and/or the inversion logic <NUM> on or within the memory <NUM>, some embodiments may further allow for on-die read retry functionality, which may improve error signaling to the memory system <NUM> and/or host <NUM>, as described in more detail in connection with <FIG>, herein.

The memory controller <NUM>, ECC circuitry <NUM>, and/or inversion circuitry <NUM> may be configured to provide data state synchronization to the memory <NUM>. Accordingly, in some embodiments, the memory <NUM> may be configured to perform data state synchronization operations without encumbering the host <NUM>. Stated alternatively, in some embodiments, the memory <NUM> may be configured to perform on-die data state synchronization.

The memory controller <NUM> can be located internal to the memory <NUM>, and can receive commands (e.g., write commands, read commands, refresh commands, etc.) from the controller <NUM> via the memory interface <NUM>. As described further below, in a number of embodiments, the memory controller <NUM> can be configured to manage cell resistance drift by providing data state synchronization for memory <NUM> independently from the controller <NUM> and/or host <NUM> (e.g., without assistance from external controller <NUM> or host <NUM>).

The memory array(s) of memory <NUM> can comprise, for example, non-volatile resistance variable memory cells each having an associated select element and a storage element. The select elements in each resistance variable memory cells can be operated (e.g., turned on/off) to select the memory cells in order to perform operations such as data programming and/or data reading operations on the resistance variable memory cells.

In some embodiments, the memory cells may be organized into pages of memory cells, such as user pages. In a non-limiting example, the memory cells may be organized into pages that include <NUM> bits (e.g., <NUM> bytes), <NUM> parity bits for performance of a triple-error correcting code, an inversion bit (e.g., a one-bit inversion flag), and/or one or more additional bits. In this example, a user page size may include <NUM> bits (e.g., <NUM> bytes).

As used herein, a storage element refers to a programmable portion of a resistance variable memory cell. For example, in PCRAM and RRAM cells, a storage element can include the portion of the memory cell having a resistance that is programmable to data states responsive to applied programming signals (e.g., voltage and/or current pulses), for example. The storage element can include a resistance variable material such as a phase change material (e.g., phase change chalcogenide alloy) such as an indium(In)-antimony(Sb)-tellurium(Te) (IST) material, e.g., In<NUM>Sb<NUM>Te<NUM>, In<NUM>Sb<NUM>Te<NUM>, In<NUM>Sb<NUM>Te<NUM>, etc., or a germanium-antimony-tellurium (GST) material, e.g., a Ge-Sb-Te material such as Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, etc. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. Other phase change materials can include GeTe, In-Se, Sb<NUM>Te<NUM>, GaSb, InSb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn-Pt, among various other phase change materials.

The select element can also be a chalcogenide material such as those described above. While the select element and the storage element can comprise different chalcogenide materials, embodiments are not so limited. For example, each cell can comprise a material (e.g., a chalcogenide material) that can serve as both the storage element and the select element (e.g., a switch and storage material (SSM).

Resistance variable memory cells are rewritable as compared to floating gate cells of NAND memory array. For example, a particular data pattern can be programmed to a group of resistance variable memory cells without necessarily erasing data previously stored in the group.

Resistance memory cells can experience resistance drift (e.g., toward higher resistance) during a time between application of, for example, two operation signals (e.g., programming and/or reset signals). That is, the resistance level of the resistance memory cells can shift over time. Such resistance drift can be due to a spontaneous increase of the resistance of the resistance level of the cell after programming, for example, due to structural relaxation of an amorphous portion of the storage element (e.g., phase change material).

In operation, data can be written to and/or read from memory <NUM> as a page of data, for example. As such, a page of data can be referred to as a data transfer size of the memory system. Data can be sent to/from a host (e.g., host <NUM>) in data segments referred to as sectors (e.g., host sectors). As such, a sector of data can be referred to as a data transfer size of the host. In a number of embodiments, the memory <NUM> can store managed units in respective groups (e.g., physical pages) of memory cells (e.g., resistance variable memory cells). Although embodiments are not so limited, a managed unit may correspond to a logical page size (e.g., e.g., a data transfer size of a host such as host <NUM>) and/or a data management size of a memory system (e.g., system <NUM>), which can be, for example 4KB, <NUM>, etc. Embodiments are not so limited, however, and the page size may correspond to a user page size of around <NUM> bits, as described above. As an example, a managed unit can be mapped (e.g., via controller <NUM>) to a physical page of memory cells. However, a number of managed units (e.g., large managed units (LMUs) and/or small managed units (SMUs)) might be mapped to a physical page.

<FIG> illustrates a group of resistance variable memory cells <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> (referred to collectively as cells <NUM>) experiencing resistance drift. Although embodiments are not so limited, resistance distribution <NUM> corresponds to a reset state (e.g., a binary data value of "<NUM>"), and a resistance distribution <NUM> corresponds to a set state (e.g., binary data value of "<NUM>"). As shown in <FIG>, a reset state (e.g., distribution <NUM>) corresponds to a higher resistance level than the set state (e.g., distribution <NUM>). Resistance distribution <NUM> corresponds to cells programmed to distribution <NUM> but whose threshold voltage has drifted upward over time subsequent to being programmed.

In <FIG>, <NUM>-<NUM> represents a data pattern stored in the group of memory cells <NUM> (e.g., each of cells <NUM> are programmed to the reset state such that each cell is storing a binary value of "<NUM>"). Arrow <NUM> represents a write operation performed on the group and which results in a different data pattern <NUM>-<NUM> being stored in the group of cells <NUM>. In this example, the write operation <NUM> involves programming cells <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> to the set state.

Arrow <NUM> represents a subsequent write operation performed on the group of memory cells <NUM> such that a different data pattern <NUM>-<NUM> is stored in the group of cells. As shown in <FIG>, the subsequent write operation <NUM> involves programming memory cells <NUM>-<NUM> and <NUM>-<NUM> from the set state (e.g., "<NUM>") back to the reset state (e.g., "<NUM>"). Write operation <NUM> also includes programming cells <NUM>-<NUM> and <NUM>-<NUM> from the reset state to the set state, while cells <NUM>-<NUM> and <NUM>-<NUM> remain in the set state and cells <NUM>-<NUM> and <NUM>-<NUM> remain in the reset state during the write operation <NUM>.

Turning to <FIG>, during a time between the write operation <NUM> and the subsequent write operation <NUM> (e.g., referred to as a drift time), the group of memory cells <NUM> experience a resistance drift. Over the drift time, for example, resistance levels of those memory cells) programmed to the set state (e.g., distribution <NUM>) during the write operation <NUM> (e.g., memory cells <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) are drifted to resistance distribution <NUM> (e.g., nearer to resistance distribution <NUM>), while resistance levels of those memory cells programmed to the reset state (e.g., distribution <NUM>) during the subsequent write operation <NUM> (e.g., cells <NUM>-<NUM> and <NUM>-<NUM>) are returned to reset distribution <NUM>. As result, the data pattern <NUM>-<NUM> (e.g., subsequent to write operation <NUM>) includes cells belonging to resistance distribution <NUM> (e.g., cells <NUM>-<NUM> and <NUM>-<NUM>) coexisting with cells belonging to resistance distribution <NUM> (e.g., cells <NUM>-<NUM> and <NUM>-<NUM>). As such, a sensing voltage <NUM> used to read the group <NUM> (e.g., to distinguish between cells storing "<NUM>" and "<NUM>") may not be capable of accurately determining the states of cells belonging to the overlapping distributions <NUM> and <NUM>, which may result in read errors.

Previous approaches to account for drift might involve always programming all of a page of cells (e.g., applying programming pulses to both those cells whose state is to be changed and those cells whose state is to remain the same) , and/or tracking the drift time associated with the cells and adjusting the sensing threshold voltage (e.g., <NUM>) as needed. However, such approaches may require a constant power source and/or can provide increased power consumption as compared to various embodiments of the present disclosure.

Other previous approaches are associated with keeping the gap between resistance levels of memory cells storing different data units. For example, those memory cells having a drifted resistance level above and/or below a certain threshold may be adjusted based on a tracked drift time. However, this previous approach may not be applicable when absolute time information is not available such that a drift time is no longer being tracked. This can be particularly problematic when power supply (e.g., required to track the drift time) is often not available to, for example, a memory system (e.g., a smartphone or any other mobile system).

Embodiments of the present disclosure can provide benefits such as energy-efficiently reducing erroneous data read on resistance variable memory cells (e.g., caused by a resistance drift of the resistance variable memory cells) without tracking a drift time associated with programmed states of resistance variable memory cells. For example, embodiments can provide data state synchronization that eliminates of a risk having a drifted set state (e.g., a resistance distribution <NUM> drifted near to, or overlapping with, a resistance distribution <NUM>) that is indistinguishable from a newly-programmed reset state (e.g., a resistance distribution <NUM>) in the absence of information associated with the drift time.

<FIG> illustrates a flow diagram <NUM> associated with providing data state synchronization in accordance with a number of embodiments of the present disclosure. As described in connection with <FIG>, managed units can correspond to a particular data size and can be mapped to particular groups of memory cells (e.g., pages of resistance variable memory cells).

The flow diagram <NUM> illustrates an example of status transitions of managed units according to some approaches. The example shown in <FIG> illustrates a "free" status <NUM>, a "valid" status <NUM>, and an "invalid" status <NUM> of managed units. The status of managed units can be tracked, for example, by a controller such as controller <NUM> shown in <FIG>. In a number of embodiments, the status transitions illustrated in flow diagram <NUM> may be experienced by managed units associated with a memory device (e.g., memory <NUM>) comprising a resistance variable memory cells in association with providing data state synchronization in accordance with a number of embodiments of the present disclosure. The resistance variable memory cells can be programmable, for example, to one of two resistance states (e.g., a set state which may correspond to a logical "<NUM>" and a reset state which may correspond to a logical "<NUM>"). Although embodiments are not so limited, the reset state can correspond to a higher resistance level than the set state.

A free status <NUM> can refer to a managed unit that has experienced a "cleaning" operation and is ready to have a new data pattern programmed thereto. A cleaning operation can involve resetting of all of the memory cells of a corresponding managed unit (e.g., placing all of the cells in a "<NUM>" state). A valid status <NUM> can refer to a managed unit storing valid data (e.g., data currently in use by a system and having an up to date L2P mapping entry). An invalid status <NUM> can refer to a managed unit storing invalid data (e.g., data corresponding to a stale L2P mapping entry).

In <FIG>, arrow <NUM> represents a status transition of a managed unit from a free status <NUM> to a valid status <NUM> responsive to a write operation to store a particular data pattern in a group of cells corresponding to a selected managed unit. Responsive to the write operation, the status of the selected managed unit, which is mapped by controller <NUM>, is updated (e.g., from free to valid) to reflect that the selected managed unit now stores valid data. As an example, in response to a received write command (e.g., a write command received from host <NUM> to controller <NUM>), a particular managed unit from among a number of managed units having free status can be selected to have host data (e.g., a data pattern received from a host) programmed thereto.

Arrow <NUM> represents a status transition of a managed unit from a valid status <NUM> to an invalid status <NUM> responsive to being invalidated (e.g., such that its corresponding mapping entry is no longer up to date). For example, the status of the managed unit can be updated from valid to invalid responsive to a trimming command received from the host which can result in logical erasure (e.g., such that the data is not physically erased from the corresponding page of cells).

Arrow <NUM> represents a transition of a selected managed unit from an invalid status <NUM> to a free status <NUM> responsive to experiencing a cleaning operation in which the cells corresponding to the managed unit are all placed in a same state (e.g., reset state). The cleaning operation can provide data state synchronization for a subsequent write operation performed on the group of cells corresponding to the managed unit. For instance, by placing all of the variable resistance memory cells of the group in a same state (e.g., reset state) prior to executing a subsequent write command to store another (e.g., different) data pattern in the group, the method of <FIG> can reduce read errors by eliminating the occurrence of cell threshold voltage distribution overlap such as that described in <FIG>. Updating of the status of a managed unit to the free status responsive to the cleaning operation can return the managed unit to a pool of managed units available for a next write operation. In a number of embodiments, the cleaning operation can be provided as a background operation to reduce latency associated with performing, for example, host commands on the group memory cells.

In a number of embodiments, a cleaning operation can include application of a reset signal only to those cells of the group not already in the reset state. As such, those cells that are not already in the reset state are programmed to the reset state at the same time (e.g., simultaneously). This synchronization prevents a drifted set state (e.g., a resistance distribution <NUM> corresponding to a set state that is drifted) from coexistence with a newly programmed reset state (e.g., a resistance distribution <NUM> corresponding to a reset state that is adjusted), which can cause an erroneous data read (e.g., by reducing a gap between those two states) as illustrated in connection with <FIG>.

Further, since memory cells that are already programmed to a reset state (e.g., prior to cleaning) need not be reprogrammed to the reset state, the cleaning operation can be performed in an energy efficient manner by preventing reset pulses from being applied to cells already in the reset state. Even though, memory cells having drifted reset states coexist with memory cells having newly programmed reset state, those distributions may not result in erroneous data reads since the controller (e.g., controller <NUM> and/or <NUM>) knows that the memory cells are always placed in a reset state prior to being programmed to a different data pattern. As such, a drift adjustment need not be performed, and therefore, a drift time need not be tracked.

In some approaches, providing data state synchronization in association with the flow diagram <NUM> can include determining whether the host data pattern includes a threshold quantity of data units (e.g., more than half) having a particular data value (e.g., a data value "<NUM>"), and, responsive to determining that the host data pattern includes at least the threshold quantity of data units having the particular data value, performing pattern inversion prior to storing the data pattern in the group of resistance variable memory cells. For example, performing the pattern inversion can include flipping the data units (e.g., bits) of the host data pattern such that all data units corresponding to a data value of "<NUM>" are flipped to a data value "<NUM>" and all data units) corresponding to a data value of "<NUM>" are flipped to a data value "0_" Pattern inversion will be further described in connection with <FIG> and <FIG>.

Performing the pattern inversion can provide benefits such as reducing a quantity of cells of the group programmed to the lower resistance state (e.g., corresponding to a set state) as compared to a quantity of cells of the group that would be programmed to the lower resistance state (e.g., corresponding to a set state) in the absence of the pattern inversion. Performing the pattern inversion will be further described in connection with <FIG> and <FIG>.

<FIG> illustrates another flow diagram associated with providing data state synchronization for a write operation in accordance with a number of embodiments of the present disclosure. In <FIG>, arrow <NUM> represents a status transition of a managed unit from a valid status <NUM> to an invalid status <NUM> responsive to being invalidated (e.g., such that its corresponding mapping entry is no longer up to date). For example, the status of the managed unit can be updated from valid to invalid responsive to a trimming command received from the host, which can result in logical erasure (e.g., such that the data is not physically erased from the corresponding page of cells).

Arrow <NUM> represents a transition of a selected managed unit from an invalid status <NUM> to a valid status <NUM> responsive to experiencing a write operation. In contrast to the example illustrated in <FIG>, as shown in <FIG>, managed units may be transferred from the valid status <NUM> to the invalid status <NUM> (and vice versa) without requiring the managed unit to be placed in a free status state. In some embodiments, this may allow for fewer operations to be performed by the memory device in comparison to some approaches, which may result in reduced time in performing memory operations and/or reduced power consumption by the memory device.

In some embodiments, as discussed above in connection with <FIG>, a cleaning operation in which the cells corresponding to the managed unit are all placed in a same state (e.g., reset state) may be performed. The cleaning operation can provide data state synchronization for a subsequent write operation performed on the group of cells corresponding to the managed unit. For instance, by placing all of the variable resistance memory cells of the group in a same state (e.g., reset state) prior to executing a subsequent write command to store another (e.g., different) data pattern in the group, the method of <FIG> can reduce read errors by eliminating the occurrence of cell threshold voltage distribution overlap such as that described in <FIG>. Updating of the status of a managed unit to the free status responsive to the cleaning operation can return the managed unit to a pool of managed units available for a next write operation. In a number of embodiments, the cleaning operation can be provided as a background operation to reduce latency associated with performing, for example, host commands on the group memory cells.

In some approaches, providing data state synchronization in association with the flow diagram <NUM> can include determining whether the host data pattern includes a threshold quantity of data units (e.g., more than half) having a particular data value (e.g., a data value "<NUM>"), and, responsive to determining that the host data pattern includes at least the threshold quantity of data units having the particular data value, performing pattern inversion prior to storing the data pattern in the group of resistance variable memory cells. For example, performing the pattern inversion can include flipping the data units (e.g., bits) of the host data pattern such that all data units corresponding to a data value of "<NUM>" are flipped to a data value "<NUM>" and all data units) corresponding to a data value of "<NUM>" are flipped to a data value "<NUM>. " Pattern inversion will be further described in connection with <FIG> and <FIG>.

<FIG> illustrates a status of a managed unit <NUM> associated with providing data state synchronization in accordance with a number of embodiments of the present disclosure. As described above, the managed unit <NUM> may be a large managed unit (LMU) or a small managed unit (SMU). In some embodiments, a LMU may be a managed unit on the order of the <NUM> bytes, while a SMU may be on the order of <NUM> bytes.

In the example of <FIG>, the memory <NUM> comprises a plurality of managed units corresponding to respective groups of resistance variable memory cells that are programmable to a reset state and a set state, although only one managed unit (e.g., managed unit <NUM>) is shown in <FIG>. As illustrated in connection with <FIG>, the reset state can correspond to a binary data value of "<NUM>," and have a higher resistance level than that of the set state. Similarly, the set state can correspond to a binary data value of "<NUM>," although embodiments are not so limited.

As shown in <FIG>, a memory system (e.g., memory system <NUM>) comprising the memory <NUM> receives a host data pattern <NUM> from a host (e.g., host <NUM>), and writes the host data pattern <NUM> in accordance with a number of embodiments of the present disclosure. Prior to being programmed to store the host data pattern <NUM>, a managed unit <NUM> is in a free status (e.g., as shown at <NUM>-<NUM>), in which all resistance variable memory cells <NUM>-<NUM>,. , <NUM>-<NUM> are in a same state (e.g., reset state). In a number of embodiments, a managed unit may comprise a flag (e.g., <NUM>-<NUM>,. , <NUM>-<NUM>) that indicates whether a data pattern stored in the managed unit is inverted or not. Prior to being programmed to the host data pattern <NUM>, the flag <NUM>-<NUM> may also be in a reset state (e.g., having a binary data value of "<NUM>"). The flag may be a particular bit in the managed unit, although embodiments are not so limited.

Responsive to receiving a write command associated with host data pattern <NUM>, a controller (e.g., controller <NUM>) is configured to perform pattern inversion prior to storing the data pattern to the managed unit responsive to determining that the host data pattern <NUM> includes at least a threshold quantity of data units (e.g., more than half) having a particular data value. For example, as shown in <FIG>, the host data pattern <NUM> comprises five data units <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> having a binary data value of "<NUM>. " When the threshold quantity is determined (e.g., predetermined) to be <NUM>% such that the host data pattern <NUM> meets the threshold quantity (five data units out of eight data units have a binary data value of "<NUM>"), the pattern inversion is performed on the host data pattern <NUM>. In this example, the pattern inversion performed on the host data pattern <NUM> (e.g., having a binary data pattern of "<NUM>") results in an inverted host data pattern (e.g., having a binary data pattern of "<NUM>).

Subsequent to performing the pattern inversion, the controller is configured to perform a write operation <NUM> to store the inverted host data pattern <NUM> to the managed unit <NUM>, set a flag indicating that the managed unit <NUM> stores an inverted host data pattern, and update a status of the managed unit <NUM> from a free status to a valid status. As a result, the managed unit <NUM> at <NUM>-<NUM> (e.g., illustrating a status of the managed unit <NUM> subsequent to being programmed to the inverted host data pattern) includes resistance variable memory cells <NUM>-<NUM>,. , <NUM>-<NUM> programmed to a binary data pattern "<NUM>," and a flag <NUM>-<NUM> set to a binary data value of "<NUM>" (e.g., indicating that the data pattern stored in the managed unit <NUM> at <NUM>-<NUM> is inverted).

Performing the pattern inversion provides benefits such as reducing energy consumption associated with flipping bits stored in memory cells having a binary value of "<NUM>. " Consider the host data pattern <NUM> comprising five data units having a binary data value of "<NUM>. " In this example, when the host data pattern <NUM> is written to the managed unit <NUM> without being inverted, a controller (e.g., controller <NUM>) is required to flip five bits (e.g., stored in respective memory cells of the managed unit <NUM>) during a cleaning operation. In contrast, the controller is merely required to flip three bits (e.g., stored in respective memory cells of the managed units <NUM>) during the cleaning operation when the inverse of the host data pattern (e.g., including only three data units having a binary data value of "<NUM>") is written to the managed unit <NUM>. As such, performing the pattern inversion reduces a quantity of cells of the managed unit programmed to the set state as compared to a quantity of cells of the managed unit that would be programmed to the set state in the absence of pattern inversion, which reduces latency associated with flipping bits (e.g., having a binary value of "<NUM>") stored in respective cells of the managed unit (e.g., managed unit <NUM>).

At some point (e.g., <NUM>), the controller is configured to invalidate (e.g., updating a status to an invalid status) the managed unit <NUM> such that the data pattern stored in the managed unit <NUM> at <NUM>-<NUM> is logically erased. As a result, the data pattern stored in the managed unit <NUM> at <NUM>-<NUM> (e.g., illustrating the managed unit <NUM> subsequent to being invalidated) is no longer tracked by, for example, a host (e.g., host <NUM>), while physical remaining in the managed unit <NUM> at <NUM>-<NUM>. The flag <NUM>-<NUM> is also invalidated responsive to the managed unit <NUM> being invalidated.

Responsive to determining that the managed unit <NUM> at <NUM>-<NUM> is in the invalid status, the controller <NUM> is configured to provide data state synchronization by performing a cleaning operation <NUM> that places, for example, only those resistance variable memory cells in a set state to a reset state. In this example, the cleaning operation <NUM> places the memory cells <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> in a reset state such that all of the resistance variable memory cells <NUM>-<NUM>,. , <NUM>-<NUM> are placed in a reset state. As a result, the managed unit <NUM> at <NUM>-<NUM> (e.g., illustrating a status of the managed unit <NUM> subsequent to performing the cleaning operation <NUM>) includes a binary data pattern of "<NUM>. " Similarly, the flag <NUM> is set to a reset state (e.g., as shown by a flag <NUM>-<NUM>). As such, a subsequent write operation can be performed on the managed unit <NUM>, in which all of the resistance variable memory cells that were previously set to a set state have a synchronized reset time (e.g., a time at which memory cells are placed in a reset state).

In a number of embodiments, the cleaning operation <NUM> can be performed in the background. For example, subsequent to invalidating a plurality of managed unit including the managed unit <NUM> (e.g., as shown by managed unit <NUM> at <NUM>-<NUM>), the controller can be configured to perform the cleaning operation <NUM> on those managed units determined to have an invalid status during idle time (e.g., when the controller <NUM> is not executing host commands). Performing the cleaning operation as a background operation can provide benefits such as preventing such operations from negatively affecting latency, among others.

In a number of embodiments, the data state synchronization can be implemented via a controller (e.g., controller <NUM>) that is located external to the memory <NUM>. In this example, the controller is able to track respective statuses of a plurality of managed units of the memory <NUM>, for example, via a logical to physical address table (e.g., logical to physical address table <NUM>). As such, the controller (e.g., that can utilize information provided by the logical to physical address table) can be configured to maintain a pointer to a physical address corresponding to a particular one of a plurality of managed units (e.g., managed unit <NUM>) designated for a subsequent write command and having a free status, and update the status of the particular managed unit to an invalid status subsequent to performing the write command (e.g., such that a subsequent write command is not performed on the same managed unit). Subsequently, the controller can be configured to further update the pointer to a next available managed unit (e.g., that is in a free status) such that each managed unit is prevented from being exceedingly overwritten, which can potentially reduce the reliability and/or useful life of the cell.

<FIG> illustrates another status of a managed unit <NUM> associated with providing data state synchronization in accordance with a number of embodiments of the present disclosure. In this example, the memory <NUM> comprises a plurality of managed units including a managed unit <NUM> corresponding to a group of resistance variable memory cells <NUM>-<NUM>,. , <NUM>-<NUM> that are programmable to a reset state and a set state. As described above, the managed unit <NUM> may be a large managed unit (LMU) or a small managed unit (SMU). In some embodiments, a LMU may be a managed unit on the order of the <NUM> bytes, while a SMU may be on the order of <NUM> bytes. As illustrated in connection with <FIG>, the reset state can correspond to a binary data value of "<NUM>," and have a higher resistance level than that of the set state. Similarly, the set state can correspond to a binary data value of "<NUM>," although embodiments are not so limited. Although only one managed unit is illustrated in <FIG>, the memory <NUM> can include a plurality of managed units corresponding to respective groups of resistance variable memory cells.

As shown in <FIG>, the memory <NUM> receives a command to write a host data pattern <NUM> having a binary data pattern of "<NUM>. " Responsive to receiving the command, a controller <NUM> (e.g., memory controller <NUM>) that is located internal to the memory <NUM> can be configured to perform a read operation (not shown in <FIG>) on the managed unit <NUM> to determine current states of resistance variable memory cells <NUM>-<NUM>,. , <NUM>-<NUM> and a data polarity corresponding to the memory cells <NUM>-<NUM>. , <NUM>-<NUM>. As a result of the read operation, the controller <NUM> determines that the resistance variable memory cells includes a binary data pattern of "<NUM><NUM>" (e.g., as shown in a managed unit <NUM> at <NUM>-<NUM>), and the data pattern stored in the managed unit <NUM> is inverted (e.g., since an inversion flag <NUM> having a binary data value of "<NUM>" indicates that the data pattern stored in the managed unit <NUM> is an inverted data pattern). Embodiments are not so limited, however, and in some embodiments the above operations (e.g., a cleaning operation, etc.) may be performed on a binary data pattern in the absence of performing a read operation on the managed unit <NUM>. For example, the above operations may be performed on data that stored in the memory cells <NUM>-<NUM>,. , <NUM>-<NUM> (e.g., "old" data) without performing a read operation.

Subsequent to performing the read operation, the controller <NUM> is configured to perform a cleaning operation <NUM> on the managed unit <NUM> to place all of the resistance variable memory cells <NUM>-<NUM>,. , <NUM>-<NUM> in a reset state. As such, the managed unit <NUM> at <NUM>-<NUM> (e.g., illustrating a status of the managed unit <NUM> subsequent to performing the cleaning operation <NUM>) includes the cells each having a binary data value of "<NUM>. " In a number of embodiments, performing the cleaning operation <NUM> can include applying a cleaning signal (e.g., reset signal) to only those memory cells (e.g., memory cells <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) determined to be currently (e.g., at <NUM>-<NUM>) programmed to a set state. Performing data state synchronization via the controller (e.g., controller <NUM>) located internal to the memory <NUM> provides benefits such as reducing latency associated with tracking and/or updating statuses of respective managed units as compared to performing the same via the controller (e.g., controller <NUM>) located external to the memory <NUM> and utilizing information provided from a logical to physical address table (e.g., table <NUM>). As described above, embodiments are not so limited, and the controller <NUM> can be configured to perform the cleaning operation <NUM> on "old" data that is stored on the managed unit <NUM> without first performing a read operation. For example, the controller <NUM> may be configured to perform the cleaning operation <NUM> at any time it is determined that memory cells (e.g., memory cells <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) are programmed to a set state.

Subsequent to performing the cleaning operation <NUM>, the controller <NUM> can be configured to write (e.g., performing a write operation) one of the host data pattern <NUM> and an inverse of the host data pattern <NUM> to the managed unit <NUM> based on a characteristic of the host data pattern. As described in connection with <FIG>, the controller <NUM> can be configured to write the inverse of the host data pattern <NUM> responsive to determining that the host data pattern <NUM> includes at least a threshold quantity (e.g., <NUM>%) of data units having, for example, a binary data value of "<NUM>. " In this example, the host data pattern <NUM> includes six (e.g., out often) data units <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> having a binary data value of "<NUM>. " As such, the controller <NUM> writes the inverse of the host data pattern (e.g., host data pattern <NUM>) to the managed unit <NUM> such that the managed unit <NUM> at <NUM>-<NUM> (e.g., illustrating a status of the managed unit <NUM> subsequent to being programmed) includes a data pattern (e.g., a binary data pattern "<NUM>) corresponding to the inverse of the host data pattern (e.g., host data pattern <NUM>).

<FIG> illustrates a flow diagram <NUM> associated with providing data state synchronization for write operations on a device page in accordance with a number of embodiments of the present disclosure. The data state synchronization for the write operation shown in flow diagram <NUM> may be performed in an embedded fashion, as described above. For example, the operations shown in flow diagram <NUM> may be performed using circuitry (e.g., controller <NUM>, ECC circuitry <NUM>, and/or inversion circuitry <NUM> illustrated in <FIG>) that is deployed on the memory device. Accordingly, in some embodiments, data state synchronization for write operations may be performed without transferring commands to and/or from the memory device such that the host (e.g., host <NUM> illustrated in <FIG>) is not encumbered during performance of the data state synchronization operation(s).

At block <NUM>, new data (e.g., host data) may be received by the memory device. The new data may comprise user data and may, for example, be a page of data. As described above, the page of data may be a page of data on the order of <NUM> bits. For example, the page of data may include <NUM> data bits, <NUM> parity bits, one inversion bit, and one or more additional bits.

At block <NUM>, an inversion operation may be performed on the new data to write the inverse of the new data pattern responsive to determining that the host data pattern includes at least a threshold quantity (e.g., <NUM>%) of data units having, for example, a binary data value of "<NUM>," as described above in connection with <FIG> and <FIG>. In some embodiments, the inversion operation may be performed by the inversion circuitry <NUM> illustrated in <FIG>.

As block <NUM>, ECC parity bits may be generated. Generation of the ECC parity bits may be performed by the ECC circuitry <NUM> shown in <FIG>. The ECC parity bits may be utilized as part of an error correction operation performed on data, such as the new data received at block <NUM>, by the memory device.

In some embodiments, a cleaning operation may also be performed, as shown at block <NUM>. As shown in <FIG>, the cleaning operation at block <NUM>, the inversion operation <NUM>, and/or generation of the ECC parity bits may be performed concurrently.

At block <NUM>, a write operation to write data and/or an inversion bit may be performed as described in connection with <FIG> and <FIG>, herein. For example, the data to be written to the memory device may include inverted data if the inversion operation performed at block <NUM> included writing the inverse of the new data. The data may be written to a data <NUM> portion of a physical block address, while the inversion bit may be written to an inversion bit portion <NUM> of the logical block address of the memory device.

At block <NUM>, a write operation to write one or more parity bits may be performed. In some embodiments, the parity bits are ECC parity bits generated as part of the ECC parity generation shown at block <NUM>. The ECC parity bits may include parity bits that have had an inversion operation performed thereon. For example, the ECC parity bits may be computed, for example, at block <NUM>, and may have an inversion operation performed thereon as shown at block <NUM>. Once the ECC parity bits are computed and/or inverted, they may be written to a parity <NUM> portion of the physical block address of the memory device.

<FIG> illustrates a flow diagram associated with providing data state synchronization for read operations in accordance with a number of embodiments of the present disclosure. The data state synchronization for the read operation shown in flow diagram <NUM> may be performed in an embedded fashion, as described above. For example, the operations shown in flow diagram <NUM> may be performed using circuitry (e.g., controller <NUM>, ECC circuitry <NUM>, and/or inversion circuitry <NUM> illustrated in <FIG>) that is deployed on the memory device. Accordingly, in some embodiments, data state synchronization for write operations may be performed without transferring commands to and/or from the memory device such that the host (e.g., host <NUM> illustrated in <FIG>) is not encumbered during performance of the data state synchronization operation(s).

As shown in <FIG>, a logical block address may include data <NUM>, an inversion bit(s) <NUM>, and/or parity bit(s) <NUM>. The data <NUM>, inversion bit(s) <NUM>, and/or the parity bit(s) <NUM> may be stored in a memory device. At block <NUM>, the logical block may be read by the memory device. For example, the data <NUM>, inversion bit(s) <NUM>, and/or parity bit(s) <NUM> may be read using a discrete read signal (e.g., a read signal with a discrete voltage value associated therewith).

Subsequent to reading the data <NUM>, inversion bit(s) <NUM>, and/or parity bit(s) <NUM>, at block <NUM>, ECC decoding may be performed on the logical block. In some embodiments, the ECC decoding may be performed by ECC circuitry such as ECC circuitry <NUM> illustrated in <FIG>. For example, the ECC decoding may be performed on the memory device without transferring the data to circuitry external to the memory device to perform the ECC decoding.

At block <NUM>, a determination as to whether ECC decoding was successful may be made. For example, circuitry deployed on the memory device (e.g., the controller <NUM>, the ECC circuitry <NUM>, and/or the inversion circuitry <NUM>) can be configured to determine if the decoding operation performed at block <NUM> was successful. If it is determined that the ECC decoding operation was not successful, at block <NUM>, the memory device may be configured to generate an error signal and/or send the error signal to the memory system and/or a host device coupled to the memory system. In some embodiments, the error signal may be generated using the circuitry discussed above that is located on or within the memory device such that the error signal is generated on-die and/or without transferring commands to or from the memory device.

If it is determined that the ECC decoding operation performed at block <NUM> was successful, at block <NUM>, an inversion operation may be performed on the data <NUM>, the inversion bit(s) <NUM>, and or the parity bit(s) <NUM>. The inversion operation may be performed as described above in connection with <FIG> and <FIG>, for example. In some embodiments, the inversion operation may be performed using circuitry that is located on or within the memory device such as the inversion circuitry <NUM> illustrated in <FIG>, herein.

Following performance of the inversion operation at block <NUM>, corrected data <NUM> may be generated, provided, and/or stored by the memory device. For example, the corrected data may be stored in the memory device in one or more pages of the memory device, such as a small managed unit, as described above.

<FIG> illustrates another flow diagram associated with providing data state synchronization for read operations in accordance with a number of embodiments of the present disclosure. The data state synchronization for the read operation shown in flow diagram <NUM> may be performed in an embedded fashion, as described above. For example, the operations shown in flow diagram <NUM> may be performed using circuitry (e.g., controller <NUM>, ECC circuitry <NUM>, and/or inversion circuitry <NUM> illustrated in <FIG>) that is deployed on the memory device. Accordingly, in some embodiments, data state synchronization for write operations may be performed without transferring commands to and/or from the memory device such that the host (e.g., host <NUM> illustrated in <FIG>) is not encumbered during performance of the data state synchronization operation(s).

At block <NUM>, a determination as to whether ECC decoding was successful may be made. For example, circuitry deployed on the memory device (e.g., the controller <NUM>, the ECC circuitry <NUM>, and/or the inversion circuitry <NUM>) can be configured to determine if the decoding operation performed at block <NUM> was successful. If it is determined that the ECC decoding operation was not successful, at block <NUM>, a determination as to whether a discrete read signal having a different voltage value associated therewith may be used to retry the read operation described at block <NUM>. If there is another discrete read signal available (e.g., if it is determined that the read operation may be retried using a discrete read signal having a different voltage value associated therewith), the read operation may be retried at block <NUM>. In some embodiments, the determination may be made using circuitry provided on or within the memory device, as described above.

If it is determined at block <NUM> that there is not another discrete read signal to try to perform the read operation with, at block at block <NUM>, the memory device may be configured to generate an error signal and/or send the error signal to the memory system and/or a host device coupled to the memory system. In some embodiments, the error signal may be generated using the circuitry discussed above that is located on or within the memory device such that the error signal is generated on-die and/or without transferring commands to or from the memory device.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of a number of embodiments of the present disclosure. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of a number of embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of a number of embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claim 1:
An apparatus, comprising:
a memory (<NUM>, <NUM>) comprising a plurality of managed units (<NUM>) corresponding to respective groups of resistance variable memory cells (<NUM>); and
a controller (<NUM>, <NUM>) coupled to the memory (<NUM>, <NUM>) and configured to cause:
performance (<NUM>) of a cleaning operation on a selected group of memory cells (<NUM>) corresponding to a selected managed unit (<NUM>) of the plurality of managed units (<NUM>) to place the memory cells of the selected group of memory cells (<NUM>) in a same state;
generation of error correction code, ECC, parity data (<NUM>, <NUM>); and
performance of a write operation on the selected group of memory cells (<NUM>) to:
write an inverted state of at least one data value to the selected group of memory cells (<NUM>); and
write an inverted state of at least one of the ECC parity data (<NUM>, <NUM>) to the selected group of memory cells (<NUM>); and
performance of an operation to update a status associated with the selected managed unit from an invalid status state to a valid status state in response to performance of the write operation.