Patent Description:
A wide variety of electronic systems operate based on timing of clock signals. For instance, examples of electronic circuitry that operate based on clock signal timing include, but are not limited to, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), data communication links, amplifiers, digital circuits, and/or voltage regulators. <CIT> discloses a clock pulse generator (CPG) in a microprocessor circuit. comprising external pins EXTAL, XTAL, CKEXT and CKRATE, an oscillator XOSC and a first multiplexer MUX1 which has two input signals: a first input signal corresponding to the output of the oscillator XOSC and a second input signal corresponding to the input from EXTAL which supplies a low frequency oscillation pulse, where the operation of the MUX1 is controlled by CKEXT.

Apparatus and methods for controlling a clock signal are provided. According to the claimed invention, a semiconductor die includes a plurality of pins comprising a supply pin configured, in use, to receive a supply voltage from a power supply, and a first clock interface pin; and a clock interface circuit configured to output a clock signal, the clock interface circuit coupled to the supply pin and the first clock interface pin, wherein the clock interface circuit comprises: an oscillator configured to generate an oscillator signal; and a first comparator configured to control operation of the clock interface circuit in a selected clock control mode chosen from two or more clock control modes based on comparing an electrical characteristic of the first clock interface pin to a comparison threshold, the clock interface circuit being configured to generate the comparison threshold based on a voltage level of the supply voltage, VDD, wherein the two or more clock control modes includes a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on the clock interface pin, and a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal. Accordingly, the clock interface circuit provides flexibility in controlling the clock signal provided to the core circuit.

In one aspect, a semiconductor die with clock control is provided according to claim <NUM>.

In another aspect, a method of clock control in an electronic system is provided according to claim <NUM>.

Further advantageous features are defined in dependent claims <NUM> to <NUM> and <NUM> to <NUM>.

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale.

Apparatus and methods for controlling a clock signal are provided. According to the claimed invention, there is provided a semiconductor die with clock control, the semiconductor die including a plurality of pins comprising a supply pin configured, in use, to receive a supply voltage from a power supply, and a first clock interface pin; and a clock interface circuit configured to output a clock signal, the clock interface circuit coupled to the supply pin and the first clock interface pin, wherein the clock interface circuit comprises: an oscillator configured to generate an oscillator signal; and a first comparator configured to control operation of the clock interface circuit in a selected clock control mode chosen from two or more clock control modes based on comparing an electrical characteristic of the first clock interface pin to a comparison threshold, the clock interface circuit being configured to generate the comparison threshold based on a voltage level of the supply voltage, VDD, wherein the two or more clock control modes includes a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on the clock interface pin, and a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal.

Accordingly, the clock interface circuit provides flexibility in controlling the clock signal provided to the core circuit.

For example, using the first clock control mode, the semiconductor die can be deployed in a first application in which it is desirable for the core circuit to be clocked using an input clock signal provided to the clock interface pin. For instance, the core circuit can communicate with another circuit external to the semiconductor die (for instance, a data converter), and a common clock signal can be used to control timing of both the core circuit and the external circuit to avoid intermodulation-distortion and/or aliasing. When operating in the first clock control mode, the frequency of the input clock signal can be changed as needed, and/or stopped and resumed as desired.

Furthermore, using the second clock control mode, the semiconductor die can further be deployed in a second application in which the clock interface circuit's oscillator generates the clock signal for the core circuit. For instance, in certain use cases a default oscillation frequency of the oscillator may be suitable for clocking the core circuit, thereby reducing cost by avoiding a need for an external clock source.

Accordingly, the clock interface circuit provides enhanced flexibility to enable the same semiconductor die to be used in a wide range of applications. Thus, a need to manufacture many different types of semiconductor dies each with a custom clock design is avoided.

As defined in the claimed invention, the comparison threshold of the comparator is generated based on a voltage level of the supply voltage pin. For example, the clock interface circuit can include a bias voltage source that shifts the supply voltage to generate a reference voltage for serving as the comparison threshold.

Implementing the clock interface circuit in this manner provides a number of advantages, including an ability to operate the clock interface circuit in the second clock control mode by tying the clock interface pin to the supply voltage pin, either directly or through an impedance (for instance, an external resistor).

In certain implementations, when operating in the second clock control mode, the voltage level of the clock interface pin is used to tune an oscillation frequency of the oscillator. In such implementations, flexibility is further enhanced by providing a mechanism for the clock interface circuit's oscillator to be tuned.

The voltage level of the clock interface pin can be set to a desired voltage level in a wide variety of ways, such as by connecting a resistor of a particular resistance between the supply voltage pin and the clock interface pin, thereby setting the voltage level of the clock interface pin to a particular voltage level corresponding to the desired oscillation frequency. In another example, a digital-to-analog convert (DAC) or other external control circuit sets the tuning voltage, which can be changed over time to achieve a desired oscillation frequency.

In certain implementations, the clock interface circuit includes multiple clock interface pins, for instance, a pair of clock interface pins that are implemented differentially. For example, using a pair of differential clock interface pins allows a differential input clock signal to be supplied in the first clock control mode, which provides the advantage of lower clock noise and/or reduced jitter relative to a single-ended configuration.

In the embodiments described above, the core circuit is integrated on the same semiconductor die as the clock interface circuit. However, other configurations are possible. In another embodiment, the clock interface circuit and the core circuit are on separate semiconductor dies, which can be co-packaged in a module. In yet another embodiment, the core circuit is integrated on-chip with the clock interface circuit, but the clock signal is also provided off-chip for an external component, which can be, for example, a core circuit of another semiconductor die.

<FIG> is a schematic diagram of a semiconductor die <NUM> according to one embodiment. The semiconductor die <NUM> includes a clock interface circuit <NUM>, a core circuit <NUM>, a supply voltage pin <NUM> (SUPPLY), and a clock interface pin <NUM> (SYNC). A semiconductor die, such as the semiconductor die <NUM> of <FIG>, is also referred to herein as a semiconductor chip or integrated circuit (IC).

The supply voltage pin <NUM> and the clock interface pin <NUM> correspond to pins (for instance, bond pads) of the semiconductor die <NUM>. Although depicted as including only two pins, the semiconductor die <NUM> typically includes additional pins as well as additional circuitry for achieving desired operation or functionality. Such details have been omitted from <FIG> for clarity.

As shown in <FIG>, the semiconductor die <NUM> includes the core circuit <NUM>, which has timing controlled by a clock signal CLK provided by the clock interface circuit <NUM>. The performance of the core circuit <NUM> is impacted by a number of operational parameters of the clock signal CLK, including, but not limited to, frequency, phase, and/or noise.

The core circuit <NUM> can correspond to a wide variety of circuits. For instance, examples of circuitry that can included in the core circuit <NUM> includes data converters, digital circuits, amplifiers, frequency synthesizers, voltage regulators, and/or data communication circuits. The clock interface circuits herein can provide a clock signal to a wide variety of types of circuits.

The desired properties of the clock signal CLK (such as frequency) can vary from one application to another. Furthermore, it is desirable for the semiconductor die <NUM> to be used across a wide range of applications, without needing to custom-design the semiconductor die <NUM> to have clock signal characteristics suitable for one particular application.

To provide flexibility in controlling the clock signal CLK, the semiconductor die <NUM> includes the clock interface circuit <NUM>, which is coupled to the supply voltage pin <NUM> and the clock interface pin <NUM>, in this embodiment. The clock interface circuit <NUM> senses an electrical characteristic of the clock interface pin <NUM>, and chooses a clock control mode for controlling the clock signal CLK based on the sensed characteristic.

The clock interface circuit <NUM> of <FIG> includes a comparator <NUM>, which compares an electrical characteristic (for instance, a voltage level) of the clock interface pin <NUM> to a comparison threshold. Additionally, the result of the comparison is used to set the clock interface circuit <NUM> in the selected clock control mode. The comparison threshold of the comparator <NUM> is generated based on a voltage level of the supply voltage pin <NUM>. The supply voltage pin <NUM> can correspond to any supply voltage pin, including a positive supply voltage pin, a negative supply voltage pin, or a ground pin.

With continuing reference to <FIG>, the clock interface circuit <NUM> further includes an oscillator <NUM>, which generates an internal oscillator signal when enabled.

The clock interface circuit <NUM> of <FIG> is operable in two or more clock control modes, including at least a first clock control mode in which the clock interface circuit <NUM> generates the clock signal CLK based on an input clock signal received on the clock interface pin <NUM>, and a second clock control mode in which the clock interface circuit <NUM> generates the clock signal CLK based on the oscillator signal from the oscillator <NUM>. The selected clock control mode is chosen based on the comparison of the comparator <NUM>.

In certain implementations, when operating in the second clock control mode, the voltage level of the clock interface pin <NUM> is used to tune an oscillation frequency of the oscillator <NUM>. In such implementations, flexibility is further enhanced by providing a mechanism for the clock interface circuit's oscillator <NUM> to be tuned.

<FIG> is a schematic diagram depicting one example of a first clock control mode <NUM> of the semiconductor die <NUM> of <FIG>. As shown in <FIG>, a supply voltage Vsup has been supplied to the supply voltage pin <NUM>, and an external clock source <NUM> has provided an input clock signal to clock interface pin <NUM>.

The clock interface control circuit <NUM> operates in the first clock control mode in this configuration. Thus, the input clock signal provided to the clock interface pin <NUM> is used to generate the clock signal CLK for the core circuit <NUM>. In certain implementations, when operating the first clock control mode, the clock signal CLK corresponds to a buffered version of input clock signal, and thus has the same frequency.

The comparator <NUM> compares a voltage level of the clock interface pin <NUM> to a threshold voltage, and sets the selected clock control mode based on a result of the comparison. Additionally, the clock source <NUM> controls a voltage level of the input clock signal, including both when the input clock signal is at a peak amplitude level and a minimum amplitude level, to be below or above the threshold voltage of the comparator <NUM> such that the output of the comparator <NUM> does not change as the input clock signal toggles.

Thus, the clock source <NUM> sets a voltage level of the clock interface pin <NUM> to inform the clock interface circuit <NUM> to operate in the first clock control mode. Additionally, the clock source <NUM> provides the input clock signal to the clock interface circuit <NUM>, which is used by the clock interface circuit <NUM> to generate the clock signal CLK for the core circuit <NUM>.

When operating in the first clock control mode, the frequency of the input clock signal can be changed as needed, and/or stopped and resumed as desired. Thus, the clock source <NUM> need not generate the input clock signal to be of fixed frequency. Moreover, the clock source <NUM> can enable or disable the input clock signal as desired.

<FIG> is a schematic diagram depicting one example of a second clock control mode <NUM> of the semiconductor die <NUM> of <FIG>. As shown in <FIG>, a supply voltage Vsup has been supplied to the supply voltage pin <NUM>, and an external resistor <NUM> has been connected between the supply voltage pin <NUM> and the clock interface pin <NUM>.

The clock interface control circuit <NUM> operates in the second clock control mode in this configuration. Thus, an internal oscillator signal from the oscillator <NUM> is used to generate the clock signal CLK for the core circuit <NUM>.

In certain implementations, when operating in the second clock control mode, a voltage VEXT at the clock interface pin <NUM> is used to set an oscillation frequency of the internal oscillator signal, and thus the frequency of the clock signal CLK.

In such implementations, a resistor value corresponding to a desired oscillation frequency of the oscillator <NUM> can be chosen for connecting between the supply pin <NUM> and the clock interface pin <NUM>. Thus, by simply choosing a resistor of a particular resistance, the end-user can instruct the clock interface circuit <NUM> to use the oscillator <NUM> to generate the clock signal CLK, with the resistance value used to set VEXT and thus the oscillation frequency of the oscillator <NUM>.

<FIG> is a schematic diagram depicting another example of the second clock control mode <NUM> of the semiconductor die <NUM> of <FIG>. In comparison to the example of <FIG>, a DAC <NUM> is used to set the voltage level VEXT of the clock interface pin <NUM> rather than a resistor.

A wide range of external control circuits can be used to set the voltage level VEXT of the clock interface pin <NUM>. Thus, although examples using a resistor and a DAC have been depicted in <FIG>, the second clock control mode can be set in other ways.

In the illustrated embodiment, the DAC <NUM> provides enhanced flexibility in tuning or adjusting the oscillation frequency of the oscillator <NUM>. Thus, the DAC <NUM> can be suitable for applications in which it is desirable to dynamically change the oscillation frequency of the oscillator <NUM>, for instance, in applications in which the operational frequency changes over time and/or in applications in which the oscillation frequency is adjusted to account for variation in operating conditions, such as temperature and/or supply voltage.

<FIG> is a schematic diagram of a semiconductor die <NUM> including clock interface circuitry according to another embodiment. The semiconductor die <NUM> includes a clock interface circuit <NUM>, a core circuit <NUM>, a power high supply pin VDD, a power low supply pin VSS, a first clock interface pin SYNCP, and a second clock interface pin SYNCN.

In the illustrated embodiment, the clock interface circuit <NUM> includes a first hysteretic comparator <NUM>, a second hysteretic comparator <NUM>, a digital logic circuit <NUM>, a clock buffer <NUM>, an oscillator <NUM>, a multiplexer <NUM>, and a reference voltage source <NUM>.

As shown in <FIG>, the reference voltage source <NUM> generates a reference voltage for the first hysteretic comparator <NUM> and the second hysteretic comparator <NUM> based on shifting the supply voltage received on the power high supply pin VDD. For example, in certain implementations, the reference voltage corresponds to VDD - VB, where VDD is the voltage level of the power high supply pin VDD and VB is the voltage of the reference voltage source <NUM>.

The first hysteretic comparator <NUM> generates a first comparison signal COMPP based on comparing the voltage level of the first clock interface pin SYNCP to the reference voltage, while the second hysteretic comparator <NUM> generates a second comparison signal COMPN based on comparing the voltage level of the second clock interface pin SYNCN to the reference voltage.

With continuing reference to <FIG>, the digital logic circuit <NUM> processes the first comparison signal COMPP and the second comparison signal COMPN to generate an oscillator enable signal OSCEN, which is used to both enable the oscillator <NUM> and to control selection of the multiplexer <NUM>.

The clock buffer <NUM> includes a differential input connected to the first clock interface pin SYNCP and the second clock interface pin SYNCN. The clock buffer <NUM> further includes an output that provides a synchronized clock signal VSYNC to a first signal input of the multiplexer <NUM>. When enabled, the oscillator <NUM> provides an oscillator signal Vosc to a second signal input of the multiplexer <NUM>. The multiplexer <NUM> outputs a clock signal VCLK to the core circuit <NUM>.

In the illustrated embodiment, the first hysteretic comparator <NUM> and the second hysteretic comparator <NUM> compare the reference voltage from the reference voltage source <NUM> to the voltage level of the first clock interface pin SYNCP and the second clock interface pin SYNCN, respectively. Using hysteretic comparators provides a number of advantages, such as providing hysteresis to inhibit noise from inadvertently changing the result of the comparisons during operation.

Based on the result of the comparisons, the digital logic circuit <NUM> sets the clock interface circuit <NUM> in either a first clock control mode or a second clock control mode. Thus, the voltage levels of the first clock interface pin SYNCP and the second clock interface pin SYNC relative to the reference voltage used for comparison determine whether the clock interface circuit <NUM> operates in the first clock control mode or the second clock control mode. In certain implementations, the second clock control mode is chosen when the voltage levels of the clock interface pins are both greater than the reference voltage, otherwise the first clock control mode is chosen.

In the illustrated embodiment, when operating in the first clock control mode, the oscillator <NUM> is disabled, and the synchronized clock signal VSYNC is selected by the multiplexer <NUM> to serve as the clock signal VCLK for the core circuit <NUM>. Aside from a delay of the clock buffer <NUM>, the synchronized clock signal VSYNC is synchronized to a differential input clock signal received between the first clock interface pin SYNCP and the second clock interface pin SYNCN. Using a pair of differential clock interface pins allows a differential input clock signal to be supplied in the first clock control mode, which provides the advantage of lower clock noise and/or reduced jitter relative to a single-ended configuration.

With continuing reference to <FIG>, when operating in the second clock control mode, the oscillator <NUM> is enabled, and the oscillator signal Vosc is selected by the multiplexer <NUM> to serve as the clock signal VCLK for the core circuit <NUM>. In this embodiment, the frequency of the oscillator <NUM> is not tuned by the voltage level(s) of the clock interface pins.

<FIG> is a schematic diagram of a semiconductor die <NUM> including clock interface circuitry according to another embodiment. The semiconductor die <NUM> includes a clock interface circuit <NUM>, a core circuit <NUM>, a power high supply pin VDD, a power low supply pin VSS, and a clock interface pin SYNCP. The clock interface circuit <NUM> includes a hysteretic comparator <NUM>, a digital logic circuit <NUM>, a clock buffer <NUM>, an oscillator <NUM>, a multiplexer <NUM>, a first reference voltage source <NUM>, and a second reference voltage source <NUM>.

In comparison to the semiconductor die <NUM> of <FIG>, the semiconductor die <NUM> of <FIG> omits the second clock interface pin SYNCN and the second hysteretic comparator <NUM>. Additionally, the clock interface circuit <NUM> of <FIG> includes the second reference voltage source <NUM> for generating a clock buffer reference voltage for the clock buffer <NUM>.

As shown in <FIG>, the second reference voltage source <NUM> generates the clock buffer reference voltage based on shifting the supply voltage received on the power low supply pin VSS. For example, in certain implementations, the clock buffer reference voltage corresponds to Vss + VBN, where Vss is the voltage level of the power low supply pin VSS and VBN is the voltage of the second reference voltage source <NUM>.

When operating in the first clock control mode, the synchronized clock signal VSYNC corresponds to a buffered version of a single-ended input clock signal received on the clock interface pin VSYNCP. In comparison to the semiconductor die <NUM> of <FIG>, the semiconductor die <NUM> has fewer clock interface pins but is more susceptible to noise in the first clock control mode.

<FIG> is a schematic diagram of a semiconductor die <NUM> including clock interface circuitry according to another embodiment. The semiconductor die <NUM> includes a clock interface circuit <NUM>, a core circuit <NUM>, a power high supply pin VDD, a power low supply pin VSS, a first clock interface pin SYNCP, and a second clock interface pin SYNCN. The clock interface circuit <NUM> includes a first hysteretic comparator <NUM>, a second hysteretic comparator <NUM>, a digital logic circuit <NUM>, a clock buffer <NUM>, a multiplexer <NUM>, a reference voltage source <NUM>, a voltage-to-current converter <NUM>, an oscillator <NUM>, and a current source IREF. In the illustrated embodiment, the voltage-to-current converter <NUM> include an amplifier <NUM>, a reference resistor <NUM> (with resistance RREF), and a transistor <NUM>.

In comparison to the clock interface circuit <NUM> of <FIG>, the clock interface circuit <NUM> of <FIG> further includes the voltage-to-current converter <NUM> and the current source IREF. When operating in the second clock control mode, the current source IREF is enabled and the voltage-to-current converter <NUM> generates a control current Iosc_ctri that changes in relation to the voltage level of the first clock interface pin SYNCP. The control current IOSC_Ctrl is used to tune the oscillation frequency of the oscillator <NUM>.

Thus, when operating in the second clock control mode, the voltage level of the first clock interface pin SYNCP is used to tune the frequency of the oscillator <NUM> and thus the frequency of the clock signal VCLK provided to the core circuit <NUM>. Thus, flexibility is enhanced by providing a mechanism for oscillator frequency control.

For example, one expression for the control current Iosc_ctri is IREF*REXT/RREF, and thus the control current IOSC_Ctrl increases with the external resistor's resistance.

In the illustrated embodiment, the voltage level of the first clock interface pin SYNCP is set using an external resistor REXT. However, other implementations of setting of the voltage level of the first clock interface pin SYNCP are possible.

<FIG> is one example of a graph depicting operation of the semiconductor die <NUM> of <FIG>.

The graph depicts a first time period depicting operation in the first clock control mode with the input clock signal toggling. Additionally, the graph depicts a second time period depicting operation in the first clock control mode with the input clock signal not toggling. As shown in <FIG>, when operating in the first clock control mode, the frequency of the input clock signal can be changed as needed, and/or the input clock signal can be stopped and resumed as desired.

With continuing reference to <FIG>, the graph further includes a third time period depicting operation in the second clock control mode with a small resistance value REXT. Furthermore, the graph further includes a fourth time period depicting operation in the second clock control mode with a large resistance value REXT. As shown in <FIG>, when operating in the second clock control mode, the frequency of clock interface control circuit's oscillator can be tuned based on a resistance value selected for an external resistor.

<FIG> is a schematic diagram of a semiconductor die <NUM> including clock interface circuitry according to another embodiment. The semiconductor die <NUM> includes a clock interface circuit <NUM>, a core circuit <NUM>, a power high supply pin VDD, a power low supply pin VSS, a first clock interface pin SYNCP, and a second clock interface pin SYNCN. The clock interface circuit <NUM> includes a first hysteretic comparator <NUM>, a second hysteretic comparator <NUM>, a digital logic circuit <NUM>, a clock buffer <NUM>, a multiplexer <NUM>, a reference voltage source <NUM>, a voltage-to-current converter <NUM>, a current source IREF, an oscillator <NUM>, and an ADC <NUM>.

The clock interface circuit <NUM> of <FIG> is similar to the clock interface circuit <NUM> of <FIG>, except that the clock interface circuit <NUM> further includes an ADC <NUM> for digitizing the controllable current from the current-to-voltage converter <NUM>. Additionally, the ADC <NUM> provides a digital tuning signal to the oscillator <NUM>.

Accordingly, digital tuning of the oscillator <NUM> is provided. Using digital tuning provides a number of advantages, including, but not limited to, flexibility in digitally processing the digital control signal using any desired processing, such as shaping, compensation for variation, and/or other processing.

<FIG> depict various examples of core circuits receiving a clock signal from a clock interface circuit. Although various applications of clock interface circuits are depicted, clock interface circuits can be used to generate a clock signal for a wide variety of core circuits. Accordingly, other implementations are possible.

<FIG> is a schematic diagram of another embodiment of a semiconductor die <NUM>. The semiconductor die <NUM> includes a clock interface circuit <NUM> and a chopper amplifier <NUM>. Pins coupled to the clock interface circuit <NUM> and components of the clock interface circuit <NUM> are not depicted in <FIG> for clarity of the figure. However, the clock interface circuit <NUM> can be implemented in accordance with any of the embodiments herein.

In the illustrated embodiment, the chopper amplifier <NUM> includes an input chopping circuit <NUM>, an amplification circuit <NUM>, and an output chopping circuit <NUM> electrically connected along a differential signal path between a pair of input terminals (VIN+, VIN-) and a pair of output terminals (VOUT+, VOUT-).

As shown in <FIG>, the clock interface circuit <NUM> generates a clock signal CLK, which is used to control chopping operations of the input chopping circuit <NUM> and the output chopping circuit <NUM>.

When operating in the first clock control mode, the input chopping circuit <NUM> can be controlled by an input clock signal that is synchronized with external components (for instance, an ADC that digitizes an output voltage of the chopper amplifier <NUM>), thereby avoiding aliasing. Additionally, when operating in the first clock control mode, the input clock signal can be stopped as desired to provide continuous amplification without chopping, and then resumed when chopping is desired.

Moreover, when operating in the second clock control mode, an oscillator of the clock interface circuit <NUM> generates the clock signal CLK. Thus, chopping can be controlled using an internal self-clock, which can be tunable to a user-selected frequency by setting a voltage level of a clock interface pin.

<FIG> is a schematic diagram of another embodiment of a semiconductor die <NUM>. The semiconductor die <NUM> includes a clock interface circuit <NUM> and an ADC <NUM>. Pins coupled to the clock interface circuit <NUM> and components of the clock interface circuit <NUM> are not depicted in <FIG> for clarity of the figure. However, the clock interface circuit <NUM> can be implemented in accordance with any of the embodiments herein.

In the illustrated embodiment, the ADC <NUM> receives an input signal IN and generates a digital output signal DOUT. Timing of data conversion operations of the ADC <NUM> is controlled by the clock signal CLK from the clock interface circuit <NUM>.

<FIG> is a schematic diagram of another embodiment of a semiconductor die <NUM>. The semiconductor die <NUM> includes a clock interface circuit <NUM> and a DAC <NUM>. Pins coupled to the clock interface circuit <NUM> and components of the clock interface circuit <NUM> are not depicted in <FIG> for clarity of the figure. However, the clock interface circuit <NUM> can be implemented in accordance with any of the embodiments herein.

In the illustrated embodiment, the DAC <NUM> receives a digital input signal DIN and generates an output signal OUT. Timing of data conversion operations of the DAC <NUM> is controlled by the clock signal CLK from the clock interface circuit <NUM>.

<FIG> is a schematic diagram of another embodiment of a semiconductor die <NUM>. The semiconductor die <NUM> includes a clock interface circuit <NUM> and a switching regulator <NUM>. Pins coupled to the clock interface circuit <NUM> and components of the clock interface circuit <NUM> are not depicted in <FIG> for clarity of the figure. However, the clock interface circuit <NUM> can be implemented in accordance with any of the embodiments herein.

In the illustrated embodiment, the switching regulator <NUM> generates a regulated voltage VREG based on timing of the clock signal CLK from the clock interface circuit <NUM>. Thus, switches of the switching regulator <NUM> can be opened or closed to control regulation. For example, the switching regulator <NUM> can correspond to a buck converter or boost converter having switches used to control a current delivered to an inductor.

<FIG> is a schematic diagram of an electronic system <NUM> according to another embodiment. The electronic system <NUM> includes a first semiconductor die <NUM> and a second semiconductor die <NUM>.

The first semiconductor die <NUM> is similar to the semiconductor die <NUM> of <FIG>, except that the semiconductor die <NUM> of <FIG> also outputs the clock signal CLK on a clock output pin. As shown in <FIG>, the clock signal CLK is provided from the first semiconductor die <NUM> to a core circuit <NUM> of the second semiconductor die <NUM>. In certain implementations, the first semiconductor die <NUM> and the second semiconductor die <NUM> are co-packaged on a module.

The first semiconductor die <NUM> of <FIG> is similar to the first semiconductor die <NUM> of <FIG>, except that the semiconductor die <NUM> of <FIG> omits the core circuit <NUM>. Thus, the first semiconductor die <NUM> does not include the core circuit <NUM>, but rather outputs the clock signal CLK on a clock output pin to provide the core circuit <NUM> of the second semiconductor die <NUM>.

Devices employing the above described schemes can be implemented into various electronic devices. Examples of electronic devices include, but are not limited to, consumer electronic products, electronic test equipment, communication systems, data converters, etc..

The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

Claim 1:
A semiconductor die (<NUM>) with clock control (<NUM>), the semiconductor die comprising:
a plurality of pins (<NUM>,<NUM>) comprising a supply pin (<NUM>) configured, in use, to receive a supply voltage from a power supply, and a first clock interface pin (<NUM>); and
a clock interface circuit (<NUM>) configured to output a clock signal, the clock interface circuit coupled to the supply pin (<NUM>) and the first clock interface pin (<NUM>), wherein the clock interface circuit (<NUM>) comprises:
an oscillator (<NUM>) configured to generate an oscillator signal; and
a first comparator (<NUM>) configured to control operation of the clock interface circuit (<NUM>) in a selected clock control mode chosen from two or more clock control modes based on comparing an electrical characteristic of the first clock interface pin (<NUM>) to a comparison threshold, the clock interface circuit being configured to generate the comparison threshold based on a voltage level of the supply voltage, VDD,
wherein the two or more clock control modes includes a first clock control mode in which the clock interface circuit (<NUM>) generates the clock signal based on an input clock signal received on the clock interface pin (<NUM>), and a second clock control mode in which the clock interface circuit (<NUM>) generates the clock signal based on the oscillator signal.