Patent Description:
Resistance of an interconnect metallization line can be reduced if the cross-sectional area is increased. For a given line thickness, cross-sectional area may be increased by increasing line width. However, increasing line width typically reduces the density of lines within a given interconnect metallization level. Fabrication techniques and interconnect structures including metallization lines that change the relationship between line width and line density so that wider lines can be formed at a without losing as much line density would therefore be commercially advantageous over alternative techniques and structures.

The document <CIT> discloses techniques related to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

The document <CIT> Al relates to a contact structure with insulating cap and a method for forming the same. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:.

An integrated circuit, IC, interconnect structure is disclosed as recited in claim <NUM>.

A method of fabricating an interconnect structure is disclosed as recited in claim <NUM>.

A computer platform that comprises the IC structure of any one of claims <NUM> - <NUM> is disclosed as recited in claim <NUM>.

Embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause and effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or layer disposed over or under another may be directly in contact or may have one or more intervening materials or layers. Moreover, one material disposed between two materials or layers may be directly in contact with the two materials/layers or may have one or more intervening materials/layers. In contrast, a first material or layer "on" a second material or layer is in direct contact with that second material/layer. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Described below are examples of integrated circuit interconnect structures in which a metallization line between two metallization lines is vertically spaced apart within an interconnect line metallization level. For such vertically spaced metallization lines, combinations of upper and lower metallization lines within one interconnect metallization level may be designed to control resistance/capacitance (R/C) of integrated circuit interconnect and/or increase effective line pattern density, or "fill factor. " With a vertical separation, or space, between adjacent lines, lower metallization lines may be self-aligned to upper metallization lines, or vice versa, so that a lower metallization line may occupy substantially the entire space between adjacent upper metallization lines. Hence, rather than being spaced laterally some distance from the adjacent metallization lines by an intervening dielectric material, adjacent lines of a given metallization level have vertical separation.

Whereas two different levels of interconnect metallization are independently patterned, both upper and lower lines of a same interconnect metallization level are fabricated from one line pattern. Following the fabrication of one of the upper or lower metallization lines, a self-aligned etch or self-aligned deposition process is employed to fabricate the other of the upper or lower metallization lines. Hence, the upper and lower metallization lines may be referred to herein as "self-aligned" to each other. Although vertically separated, the upper and lower metallization lines are best considered to be lines of a single interconnect level since the routes and dimensions of lower/upper metallization lines are dictated by the routes and dimensions of upper/lower metallization lines. Vertically spaced adjacent upper and lower metallization lines are referred to herein "intra-level" interconnect metallization lines to more clearly distinguish them from metallization lines of two different interconnect levels where one metallization line may be stacked over the another metallization line in any arbitrary manner as a function of two substantially independent wiring level patterns.

As further described below, vertically spaced intra-level metallization lines of a given interconnect metallization level may be routed to a different level of interconnect metallization through via metallization. Because adjacent intra-level lines may have no lateral separation between them, via metallization coupled to a lower intra-level line that passes through the plane of upper intra-level lines (to an overlying interconnect level), and that is to be electrically isolated from the upper-level interconnect lines, is limited to a diameter smaller than a width of the lower intra-level line so that the via is laterally separated from the upper intra-level line. Via metallization coupling a lower intra-level line to an underlying interconnect level is not similarly restricted and may have any diameter (smaller, equal to, or larger than the width of the lower intra-level line). Likewise, the diameter of via metallization coupled to an upper intra-level line that passes through the plane of lower intra-level lines (to an underlying interconnect level) is limited to being smaller than a width of the upper intra-level line while the diameter of via metallization coupling the upper intra-level line to an overlying interconnect level is unrestricted.

Although upper/lower intra-level metallization lines are fabricated so as to permit them to be electrically isolated, they may also be interconnected to each other, as needed. For example, via metallization coupled to an upper intra-level line that passes through the plane of lower intra-level lines (to an underlying interconnect level) that is to be electrically coupled to an adjacent lower intra-level interconnect line may merely have a larger diameter (e.g., at least equal to a width of the upper intra-level line) so that the via metallization has no lateral separation from the lower intra-level line and makes contact with a sidewall of the lower intra-level line. Likewise, via metallization coupled to a lower intra-level line that passes through the plane of upper intra-level lines (to an overlying interconnect level) that is to be electrically coupled to an adjacent upper intra-level interconnect line may merely have a larger diameter (e.g., at least equal to a width of the lower intra-level line) so that the via metallization has no lateral separation from the upper intra-level line and makes contact with a sidewall of the upper level line. In other embodiments, adjacent upper and lower interconnect lines may be electrically coupled merely by partially masking a recess etch employed to vertically separate the intra-level lines.

As also described further below, dielectric material between two metallization lines may be recessed or deposited selectively to first intra-level lines, and in a self-aligned manner. Supplemental metallization may then be deposited and planarized to form the second intra-level lines. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.

<FIG> is a flow chart of methods <NUM> for vertically separating intra-level metallization lines, in accordance with some embodiments. <FIG> illustrate a plan view of a portion of an interconnect structure <NUM> evolving as methods <NUM> are practiced, in accordance with some embodiments. <FIG> illustrate a cross-sectional view of interconnect structure <NUM> along the B-B' line depicted in <FIG>, respectively.

Referring first to <FIG>, methods <NUM> begin at input <NUM> where a workpiece having co-planar metallization lines planarized with a surrounding dielectric material, is received. In some embodiments, the workpiece includes a semiconductor wafer, such as a large format (e.g., <NUM>-<NUM>) wafer. The wafer may include a Group IV semiconductor material layer (e.g., Si, Ge, SiGe, GeSn, etc.), or a Group III-V semiconductor material layer, or a Group II-VI semiconductor material layers, for example. The workpiece may include one or more underlying device layers including the semiconductor material layer, and may also have one or more interconnect levels interconnecting the devices (e.g. transistors). As received, the work surface of the workpiece is advantageously planar and comprises a thickness of dielectric material over any number of underlying device or interconnect metallization levels. Metallization lines over, or embedded within, this dielectric material are to become upper intra-level metallization lines.

In the example shown in <FIG>, a metallization line <NUM> is illustrated as having a longitudinal line length L1 and a transverse line width W1. As shown, various metallization lines <NUM> may have various longitudinal lengths with ends located as determined by a wiring mask pattern for the metallization level. Metallization lines <NUM> have a transverse line width W1, which may be fixed to a constant for all metallization lines <NUM> or it may vary across different metallization lines <NUM>. In exemplary embodiments, line length L1 is significantly (e.g., 3x) larger than line width W1. Between adjacent metallization lines <NUM> there is a spacing S1. Spacing S1 may be substantially the same between all metallization lines <NUM>, or spacing S1 may also vary between different metallization lines. Spacing S1 may be approximately equal to line width W1, or it may be smaller or larger than line width W1.

As shown in <FIG>, a lower interconnect level (e.g., M1) includes metallization lines <NUM> embedded within dielectric material <NUM>. In other embodiments, there may be no lower interconnect level, and instead only a device level. In the illustrated example, metallization lines <NUM> are designated as a M1 interconnect plane while metallization lines <NUM>, being the upper lines of a second interconnect level, are designated as a M2B level. Via metallization <NUM> extends through a dielectric material <NUM> between one of the metallization lines <NUM> and one of the metallization lines <NUM>. Via metallization <NUM> has a maximum lateral diameter D0, which may vary with implementation, but is generally significantly smaller than the length of the line metallization (e.g., D0 is significantly smaller than line length L1). In the illustrated example, diameter D0 is also smaller than line width W1. In other embodiments, as noted further below, diameter D0 may in some instances be larger than line width W1 and/or via metallization <NUM> may otherwise extend beyond an edge or sidewall of metallization line <NUM>. Via metallization <NUM> is designated as V1B because it is coupled to metallization lines <NUM> in the M2B level, which are only the first metallization lines of the second interconnect level.

In addition to via metallization <NUM>, a via dielectric <NUM> is further illustrated to emphasize that that via metallization may entail more than one patterning iteration and/or more than one via fill iteration. Via dielectric <NUM> is located where there are no metallization lines <NUM>. In this example, all V1 patterning has been completed prior to fabricating metallization lines <NUM> and via dielectric <NUM> serves as a placeholder for additional V1 via metallization that is to be subsequently formed. As such, via dielectric <NUM> similarly has a maximum diameter D0 that may vary. In alternative embodiments, via metallization <NUM> may be everywhere via dielectric <NUM> is depicted in <FIG>. In still other embodiments, for example as further described elsewhere herein, additional V1 openings may be formed only after trenches for additional M2 metallization lines are formed.

Metallization via <NUM> (and dielectric via <NUM>) has a height substantially equal to a thickness T1 of dielectric material <NUM>. Thickness T1 may vary with implementation, but in some exemplary embodiments is <NUM>-<NUM>. Dielectric material <NUM> is substantially coplanar with a top of metallization via <NUM>. Dielectric material <NUM> has a thickness T2 over the top of vias <NUM>, <NUM>, and over dielectric material <NUM>. Thickness T2 may also vary with implementation, but in some exemplary embodiments is <NUM>-<NUM>. Dielectric materials <NUM>, <NUM> and <NUM> may have any composition suitable for electrical isolation of integrated circuitry. Dielectric materials <NUM>, <NUM> and <NUM> may have substantially the same composition, and may all be a low-k dielectric material (e.g., SiOC) having a relative permittivity below <NUM>, for example. In other examples, dielectric materials <NUM>, <NUM> and <NUM> may be any of SiO, SiON, hydrogen silsesquioxane, methyl silsesquioxane, polyimide, polynorbornenes, benzocyclobutene, or the like. Dielectric materials <NUM>, <NUM> and <NUM> may be deposited as a flowable oxide, for example, and have substantially planar top surfaces. If present, dielectric via <NUM> may comprise any dielectric material that may be removed selectively dielectric material <NUM>. For example, dielectric via <NUM> may comprise a carbonaceous material (e.g., diamond-like carbon).

Metallization lines <NUM> and <NUM>, as well as metallization via <NUM> may be any metallic composition suitable for electrical routing within integrated circuitry. Metallization lines <NUM> and <NUM>, as well as metallization via <NUM> may all comprise substantially the same metal (e.g., predominantly one of Cu, Ru, W, Mo, Co, or Al), for example.

As further shown in <FIG>, interconnect structure <NUM> is over a portion of an underlying substrate that includes a device layer <NUM>. Within device layer <NUM> there are a plurality of devices <NUM>. In exemplary embodiments, devices <NUM> are metal-oxide-semiconductor (MOS) structures, however devices <NUM> may also be other transistor types, such as, but not limited to, other FET architectures (TFET, TFT), bipolar junction transistors, or other devices including one or more semiconductor junctions (e.g., diodes, etc.).

Returning to <FIG>, methods <NUM> continue at block <NUM> where the dielectric material between the metallization lines is recessed, for example, with an anisotropic etch process. The recess etch at block <NUM> defines locations where lower intra-level metallization lines are to be located. The recess etch is at least partially self-aligned to the metallization lines with the metallization lines masking the dielectric etch. The recess etch performed at block <NUM> may be further masked by a patterned mask material (not depicted) such that dielectric material within some regions between adjacent metallization lines is retained (not recessed).

In the example further illustrated in <FIG>, an anisotropic etch has formed trenches <NUM> in interconnect structure <NUM>. The anisotropic etch may include any plasma/RIE etch process suitable for dielectric material <NUM> (e.g., based on a CxFy plasma chemistry) as embodiments are not limited in this respect. Although trenches <NUM> are depicted with ideal profiles having substantially vertical (e.g., z-dimension) sidewalls, it is appreciated that trenches <NUM> may instead have other profiles, for example with tapered sidewall slopes and a top width being slightly larger than a bottom width, etc. As illustrated, in the absence of an additional patterned mask layer <NUM>, trenches <NUM> span the line length L1. The width of trenches <NUM> is substantially equal to spacing S1 between adjacent metallization lines <NUM>. Trenches <NUM> are therefore at least partially self-aligned to metallization lines <NUM> and patterned mask layer <NUM> may provide for end-to-end spaces between trenches <NUM>.

Trenches <NUM> may be recessed to any predetermined depth D1 below a bottom of metallization lines <NUM> either by practicing a timed dielectric etch, or by incorporating an etch stop layer (not depicted) within dielectric material <NUM>. Depth D1 is less than dielectric thickness T1 so that metallization lines <NUM> are not exposed in the bottom of trenches <NUM>. In some examples, recess etch depth D1 is <NUM>-<NUM>. Trenches <NUM> may however expose vias within dielectric material <NUM>. In the illustrated example, via metallization <NUM> is not exposed by trenches <NUM> because of its smaller maximum diameter D0. For alternative embodiments where via metallization <NUM> has a sufficiently large maximum diameter D0 that it extends beyond an edge of metallization lines <NUM>, trenches <NUM> would expose some portion of via metallization <NUM>.

As further illustrated, the dielectric recess etch exposes via dielectric <NUM> within trenches <NUM>. Via dielectric <NUM> may also be recessed at some finite rate as a function of the selectivity of the etch process (with via dielectric <NUM> etching either faster or slower than dielectric material <NUM>). Any via dielectric <NUM> remaining after the formation of trenches <NUM> may be removed with another etch process that is selective to dielectric material <NUM>. For embodiments where via dielectric <NUM> is instead via metallization <NUM>, high etch selectivity may result in pillars of via metallization within trenches <NUM>. The pillars may be retained as a permanent component of interconnect structure <NUM>.

Returning to <FIG>, methods <NUM> continue at block <NUM> where additional metallization is deposited over the workpiece, filling any openings (e.g., trench and via) that were patterned into the dielectric material. Following metal deposition, the workpiece surface is planarized, for example with a CMP process, so that a top surface of the deposited metal is co-planar with adjacent metallization lines. Any metallization process may be employed at block <NUM> to deposit any metal suitable for IC interconnect lines. A damascene-type process where the metallization is deposited into a trench and then planarized facilitates vertical separation of intra-level metallization lines. In some exemplary embodiments, the metallization deposited at block <NUM> can be chemically etched more readily than Cu-based metallizations. The metallization deposited at block <NUM> also advantageously has a different composition than adjacent metallization lines within the same interconnect level.

In the example further illustrated in <FIG>, metallization <NUM> has been deposited into the trenches between metallization lines <NUM>. Metallization <NUM> has been planarized so that its top surface is substantially co-planar with a top surface of metallization lines <NUM> and any portion of dielectric material <NUM> that was protected from the trench etch. At this point, metallization <NUM> is in contact with metallization lines <NUM> (i.e., electrically shorted). As further illustrated, metallization <NUM> also forms a via metallization V1A, the second via metallization (along with V1B) contacting metallization lines <NUM> of interconnect level M1. Metallization <NUM> may include one or more layer of metal or metal alloy suitable for electrical routing within integrated circuitry. Metallization <NUM> advantageously has a different composition than metallization lines <NUM> so that metallization <NUM> can be subsequently etched back selectively to metallization lines <NUM>. In some embodiments where metallization lines <NUM> comprise predominantly Cu, metallization <NUM> is other than Cu. For example, metallization <NUM> may comprise predominantly one of Ru, W, Mo, Co, or Al. In some other embodiments where metallization lines <NUM> is instead predominantly a first of Ru, W, Mo, Co, or Al, metallization <NUM> is predominantly a second of Ru, W, Mo, Co, or Al.

Returning to <FIG>, methods <NUM> continue at block <NUM> where the metallization deposited at block <NUM> is recessed selectively relative to the adjacent metallization lines (i.e., the adjacent metallization lines etch less rapidly). At block <NUM>, a mask material (e.g., a photosensitive material) may first be patterned to define plugs where the metallization will be protected from etch and therefore not recessed. Such a metal plug will maintain electrical interconnection between the metallization and adjacent metallization lines on two sides of the plug. In regions exposed to the etch process, the top surface of the metallization that was deposited at block <NUM> is recessed to a depth below a bottom of the adjacent metallization lines. The metal recess etch performed at block <NUM> vertically separates second metallization lines from the adjacent first metallization lines. The etch process performed at block <NUM> may be conducted for a predetermined time to reach a desired vertical depth. Any etch process suitable for the chosen metallization may be practiced at block <NUM>. In some embodiments, the etch process is a plasma/RIE etch. However, in other embodiments a wet chemical etch is performed. The etch process may be isotropic to the extent that any desired plug pattern can still be maintained.

In the example further illustrated in <FIG>, a top surface of metallization <NUM> has been etched back, or recessed, sufficiently to generate separate metallization lines <NUM>. Metallization lines <NUM> are at a bottom of a trench <NUM>, which has some depth D2 of dielectric material <NUM> between a top of metallization lines <NUM> and a bottom of metallization lines <NUM>. Metallization lines <NUM> therefore have a thickness T2 that is substantially equal to a difference between the trench depth D1 (<FIG>) minus the depth D2 (<FIG>). Because metallization lines <NUM> occupy a trench formed with an etch that was self-aligned to metallization lines <NUM>, a centerline CL of width W1 of each metallization line <NUM> is coincident with the centerline CL of the space between adjacent metallization lines <NUM>. Likewise, a centerline of CL of each metallization line <NUM> is coincident with the centerline CL of the space S1 between adjacent metallization lines <NUM>. This will be true even if there are differences in pitch between metallization lines <NUM> and <NUM>, for example as a result of a dimensional bias in the formation of metallization lines <NUM>. As shown in <FIG>, there is substantially no lateral separation between metallization lines <NUM> and <NUM> with metallization lines <NUM> having a width substantially equal to spacing S1 between metallization lines <NUM>. In other words, metallization line sidewall <NUM> has zero lateral offset from metallization lines sidewall <NUM>. As further shown in <FIG>, the fill factor of metallization lines <NUM> and <NUM> is <NUM>% within interconnect structure <NUM>. As further shown in <FIG>, metallization lines <NUM> are lower lines (e.g., M2A) within interconnect level M2 while metallization lines <NUM> are upper lines (e.g., M2B) within interconnect level M2. Hence, although such high line fill factor might otherwise be electrically shorted or suffer unacceptably high parasitic capacitance, the vertical separation (e.g., z-dimension) between metallization lines <NUM> and <NUM> provides electrical isolation and significantly reduces adjacent line parasitics. Hence, vertical separation of the intra-level (M2A-M2B) metallization lines can reduce electrical resistance and increase line density by increasing the line fill factor while controlling intra-level parasitic capacitance.

As further illustrated in <FIG>, because via metallization <NUM> has a smaller diameter than the line width of an overlying one of metallization <NUM> lines, metallization lines <NUM> are laterally separated from via metallization <NUM> by dielectric material <NUM>. Metallization lines <NUM> are therefore electrically isolated from via metallization <NUM>. For embodiments where via metallization is either offset from an edge of metallization lines <NUM>, or of sufficiently large maximum diameter D0 to be exposed during the dielectric recess etch, a nearest one of metallization lines <NUM> would be in direct contact with via metallization <NUM>.

Returning to <FIG>, methods <NUM> continue at block <NUM> where the trenches formed over the lower metallization lines (and between the upper metallization lines) are at least partially backfilled with dielectric material. The backfilling may proceed according to one or more deposition techniques, such as, but not limited to (flowable) chemical vapor deposition (CVD), etc. The dielectric deposited may have any composition known to be suitable for IC interconnect isolation. Following deposition, a top surface of the dielectric may be planarized, for example with any CMP process, so that the top surface of the upper metallization lines is again coplanar with a top surface of dielectric material. At this point methods <NUM> are substantially complete with the interconnect structure now ready for an additional level of interconnect metallization, which may be formed according to any technique(s). In exemplary embodiments, methods <NUM> end at output <NUM> following the formation of an additional level of interconnect metallization that includes via metallization to both the upper (first) and lower (second) metallization lines.

In the example further illustrated in <FIG>, interconnect structure <NUM> includes a dielectric material <NUM> that has a top surface substantially co-planar with a top of metallization lines <NUM>. Metallization lines <NUM> are below dielectric material <NUM>, and are therefore in a lower plane (M2A) of interconnect level M2. Metallization lines <NUM>, being over metallization lines <NUM> are therefore in an upper plane (M2B) of interconnect level M2.

<FIG> is a flow chart of methods <NUM> for vertically spacing self-aligned intra-level metallization lines, in accordance with some alternative embodiments. Methods <NUM> are well suited to vertically spacing self-aligned intra-level metallization lines that have substantially the same composition. <FIG> illustrate a plan view of a portion of an interconnect structure <NUM> evolving as methods <NUM> are practiced, in accordance with some embodiments. <FIG> illustrate a cross-sectional view of interconnect structure <NUM> along the B-B' line depicted in <FIG>, respectively. For <FIG>, a feature retaining the reference label of a feature introduced above in the context of <FIG> may have any of the attributes previously described for that feature.

Referring first to <FIG>, methods again begin at input <NUM> where a workpiece having a first metallization lines and dielectric material between the first metallization lines is received. The workpiece may include one or more underlying device layers including the semiconductor material layer, and may also have one or more interconnect levels interconnecting the devices (e.g. transistors). As received, the work surface of the workpiece is advantageously planar and comprises a thickness of dielectric material over any number of underlying device or interconnect metallization levels. Metallization lines over, or embedded within, this dielectric material are again to become upper intra-level metallization lines.

Methods <NUM> continue at block <NUM> where the dielectric material between adjacent pairs of the metallization lines is recessed, for example selectively to the metallization lines. The dielectric recess etch at block <NUM> defines locations where lower intra-level metallization lines are to be located. This etch is at least partially self-aligned to the metallization lines masking the dielectric etch. The recess etch performed at block <NUM> may be further masked by a patterned mask material (not depicted) so that dielectric material within some regions between adjacent metallization lines may be retained (not recessed).

At block <NUM>, methods <NUM> deviate from methods <NUM> (<FIG>) with the deposition of a dielectric liner material into the trenches formed at block <NUM>, and over the metallization lines adjacent to the trenches. The dielectric material is advantageously a thin film having at thickness of <NUM>-<NUM>, for example. The dielectric liner material is advantageously deposited with a substantially conformal deposition process so that the film thickness varies by less than <<NUM>% between surfaces parallel to a plane of the workpiece and surfaces substantially orthogonal to the plane of the workpiece).

In the example further illustrated in <FIG>, an interconnect structure <NUM>, when received as a starting material, has many of the same structures of interconnect structure <NUM>. In the example shown in <FIG>, metallization lines <NUM> again have a line length L1 that is significantly larger than line width W1. There is a spacing S1 between adjacent metallization lines <NUM>. Via metallization <NUM> interconnects one of the metallization lines <NUM> to metallization line <NUM> of an underlying metallization level M1. In this example, interconnect structure <NUM> lacks any dielectric vias. Mask material layer <NUM> may be optionally present to protect various regions.

<FIG> illustrate interconnect structure <NUM> following a recess etch of dielectric materials <NUM> and <NUM> to form trenches <NUM> aligned to a sidewall of metallization lines <NUM>. In the absence of an additional patterned mask layer, trenches <NUM> span the line length L1. The width of trenches <NUM> is substantially equal to spacing S1 between adjacent metallization lines <NUM>. Trenches <NUM> may be recessed to any predetermined depth D1 below a bottom of metallization lines <NUM>. As further shown by <FIG>, a dielectric liner material <NUM> has been deposited into trenches <NUM> and over metallization lines <NUM>. Dielectric liner material <NUM> has a substantially conformal thickness T3, for example of less than <NUM>. Dielectric liner material <NUM> may have any composition, such as any of those described for dielectric material <NUM>, or one having a higher relative permittivity (e.g., HfO2, ZrO, Al2O3).

Returning to <FIG>, methods <NUM> continue at block <NUM> where via openings are formed within the trench recesses. Methods <NUM> are therefore one example of a double via patterning technique that may be employed as an alternative to the technique described for methods <NUM>. Any masking and etch process may be employed at block <NUM> to form additional vias down to underlying metallization lines.

In the example further illustrated in <FIG>, a sacrificial material <NUM> has been planarized over the workpiece. Sacrificial material <NUM> may have any composition that is amenable to anisotropic etching, such as, but not limited to, carbonaceous materials like DLC. A mask material <NUM> is patterned over sacrificial material <NUM>. Mask material <NUM> may be a photosensitive material (e.g., resist) in which a via pattern has been exposed and developed, or mask material <NUM> may be a hardmask material that has been etched according to via pattern. As further illustrated, vias <NUM> are etched through sacrificial material <NUM>, and through dielectric liner material <NUM>. As further illustrated in <FIG>, vias <NUM> are further etched through dielectric material <NUM> to expose metallization lines <NUM>. Sacrificial material <NUM> and mask material <NUM> may be removed during and/or following delineation of vias <NUM>. Following via etch, dielectric liner material <NUM> remains over a top surface of metallization lines <NUM>.

Returning to <FIG>, methods <NUM> continue at block <NUM> where metallization is deposited within the trenches (and vias), and the metallization is planarized with the adjacent metallization lines. Any metallization process may be employed at block <NUM> to deposit any metal suitable for IC interconnect lines. In some exemplary embodiments, the metallization deposited at block <NUM> can be chemically etched more readily than Cu-based metallizations. The metallization deposited at block <NUM> may advantageously have substantially the same composition as the adjacent metallization lines. However, the metallization deposited at block <NUM> may also have a different composition than the adjacent metallization lines.

In the example further illustrated in <FIG>, metallization <NUM> has been deposited into the trenches between metallization lines <NUM> Metallization <NUM> has been planarized so that its top surface is substantially co-planar with a top surface of metallization lines <NUM> and any portion of dielectric material <NUM> that was protected during the otherwise self-aligned trench etch. At this point, metallization <NUM> is laterally separated from metallization lines <NUM> by dielectric liner material <NUM>. As further illustrated, metallization <NUM> also provides another via metallization V1A contacting metallization lines <NUM> of interconnect level M1. Metallization <NUM> may include one or more layers of metal or metal alloy suitable for electrical routing within integrated circuitry. Metallization <NUM> may have the same composition as metallization lines <NUM> because portions of dielectric liner material <NUM> that remain over metallization <NUM> can mask/protect metallization <NUM> while metallization <NUM> is subsequently etched back selectively to dielectric liner material <NUM>. In some embodiments where metallization lines <NUM> is predominantly one of Ru, W, Mo, or Al, metallization <NUM> is also predominantly the same one of Ru, W, Mo, Co, or Al.

Returning to <FIG>, methods <NUM> continue at block <NUM> where the metallization deposited at block <NUM> is recessed below the adjacent metallization lines to form additional metallization lines at a lower plane of the interconnect level. During the metallization etchback process, the top surface of the metallization is recessed to a depth below a bottom of the adjacent metallization lines. The etch process performed at block <NUM> may be conducted for a predetermined time to reach a desired vertical depth/separation between the adjacent lines. Any etch process suitable for the chosen metallization may be practiced at block <NUM>. In some embodiments, the etch process is a plasma/RIE etch. However, in other embodiments a wet chemical etch is performed.

In the example illustrated in <FIG>, metallization <NUM> has been recessed to form metallization lines <NUM>. A top surface of metallization <NUM> has been recessed as a bottom of a trench <NUM>, which has some depth D2 of dielectric material <NUM> between a top of metallization lines <NUM> and a bottom of metallization lines <NUM>. Metallization lines <NUM> therefore have a thickness T2. Because metallization lines <NUM> again occupy a trench formed with an etch that was self-aligned to metallization lines <NUM>, a centerline CL of width W1 of each metallization line <NUM> is again coincident with the centerline CL of the space between adjacent metallization lines <NUM>. Likewise, a centerline of CL of each metallization line <NUM> is coincident with the centerline CL of the space S1 between adjacent metallization lines <NUM>. This will be true even if there are differences in pitch between metallization lines <NUM> and <NUM>, for example as a result of a dimensional bias in the formation of metallization lines <NUM> resulting by the non-zero thickness of dielectric liner material <NUM>. As shown in <FIG>, a minimal thickness of dielectric liner material <NUM> lateral separates metallization lines <NUM> and <NUM>. Metallization lines <NUM> therefore have a width approximately equal to spacing S1 less twice the thickness T3 of dielectric liner material <NUM>. Metallization line sidewall <NUM> has nearly a zero lateral offset from metallization line sidewall <NUM>. Metallization lines <NUM> and <NUM> thus may have nearly a <NUM>% fill factor. While such minimal spacing between adjacent metallization lines might otherwise suffer unacceptably high parasitic capacitance, the vertical separation (e.g., z-dimension) between metallization lines <NUM> and <NUM> will significantly reduce adjacent line parasitics. Hence, vertical separation of the intra-level (M2A-M2B) metallization lines can reduce electrical resistance and increase line density by increasing the line fill factor, as well as control intra-level parasitic capacitance.

With the intra-level lines fabricated, methods <NUM> continue through blocks <NUM> and <NUM> where the remaining non-planarity between the intra-level metallization lines is eliminated by backfilling a dielectric material and planarizing that dielectric material with a top surface of the upper metallization lines. The processes performed at blocks <NUM> and <NUM> may be substantially as described above, for example, to arrive at the interconnect structure <NUM> as illustrated in <FIG>. Dielectric liner material <NUM> may remain over metallization lines <NUM> (e.g., as a polish stop layer), as shown, or it may be removed during the planarization process so that a top surface of metallization lines <NUM> are exposed. At this point, interconnect structure <NUM> shares many of the structural attributes of interconnect structure <NUM>(e.g., <FIG>). Methods <NUM> (<FIG>) may therefore be completed at output <NUM> in substantially the same manner described above. For example, upper interconnect level vias may be made to various ones of the intra-level metallization lines, as needed, and any additional levels of metallization may be fabricated to complete the integrated circuitry.

While methods <NUM> and <NUM> illustrated exemplary "top-down" approaches to fabricating self-aligned intra-level metallization lines, "bottom-up" approaches may also be practiced. <FIG> is a flow chart of methods <NUM> for vertically spacing intra-level metallization lines, in accordance with some "bottom-up" embodiments. <FIG> illustrate a plan view of a portion of an interconnect structure <NUM> evolving as methods <NUM> are practiced, in accordance with some embodiments. <FIG> illustrate a cross-sectional view of interconnect structure <NUM> along the B-B' line depicted in <FIG>, respectively. For <FIG>, a feature retaining the reference label of a feature introduced above in the context of <FIG> may have any of the attributes previously described for that feature.

Referring first to <FIG>, methods again begin at input <NUM> where a workpiece having a metallization lines and dielectric material between the metallization lines is received. The workpiece may include one or more underlying device layers including the semiconductor material layer, and may also have one or more interconnect levels interconnecting the devices (e.g. transistors). As received, the work surface of the workpiece is advantageously planar and comprises a thickness of dielectric material over any number of underlying device or interconnect metallization levels. Metallization lines over, or embedded within, this dielectric material are in this embodiment to become lower intra-level metallization lines.

In the example further illustrated in <FIG>, an interconnect structure <NUM>, when received as a starting material, has many of the same structures of interconnect structures <NUM> and/or <NUM>. In the example shown in <FIG>, metallization lines <NUM> again have a line length L1 that is significantly larger than line width W1. There is a spacing S1 between adjacent metallization lines <NUM>. Via metallization <NUM> interconnects one of the metallization lines <NUM> to metallization line <NUM> of an underlying metallization level M1. In this example, dielectric material <NUM> has a thickness T1 that may be less than for interconnect structures <NUM> or <NUM> because metallization lines <NUM> are to become lower metallization lines of a self-aligned intra-level metallization lines.

Returning to <FIG>, methods <NUM> continue at block <NUM> where dielectric material is selectively formed over the metallization lines present in the starting material. Selective dielectric material formation may proceed in a number of manners. As one example, directed self-assembly (DSA) is employed as a means of distinguishing between surfaces of the metallization lines and the adjacent dielectric material. Any of the DSA techniques known to be suitable for forming a self-assembled monolayer (SAM), or the like may be practiced at block <NUM>. For example, a diblock copolymer (DCP) may be deposited over a surface of the workpiece with a phase separation in the DCP occurring in a manner sensitive to different surface polarity of the heterogeneous (e.g., hydrophilic/hydrophobic, etc.) workpiece surface. Methods <NUM> then continue at block <NUM> where a dielectric material is formed between lines of DSA/SAM material. This dielectric material may be deposited selectively over dielectric material relative to the DSA/SAM material, or may be deposited unselectively and then planarized/etched back to expose the DSA/SAM material. In advantageous embodiments the thickness of the dielectric material deposited at block <NUM> is less than the height/thickness of the DSA/SAM material. If needed, the dielectric material deposited between the lines of DSA/SAM material may be recessed after deposition, for example with etch process that is selective to the dielectric material over the DSA/SAM material.

In the example illustrated in <FIG>, a DSA/SAM material <NUM> remains over metallization <NUM>, for example following dissolution of the phase of a DCP that formed over dielectric material <NUM>. Dielectric material <NUM> has been deposited between DSA/SAM material <NUM>, and on to dielectric material <NUM>. Dielectric material <NUM> may have any composition, such as any of those described elsewhere herein for dielectric materials <NUM>, <NUM>, or <NUM>. Following deposition, and potentially a planarization and etchback, dielectric material <NUM> has a thickness T4 that is significantly less than a height H3 of DSA/SAM material <NUM>. Trenches <NUM> between DSA/SAM material <NUM> are therefore self-aligned to spaces S1 between metallization lines <NUM>. Trenches <NUM> are vertically separated from metallization lines <NUM> by the thickness of dielectric material <NUM>.

Returning to <FIG>, methods <NUM> continue at block <NUM> where metallization is deposited within the trenches defined by the lines of DSA/SAM material. The metallization may then be planarized to expose DSA/SAM material and delineate the second (upper) metallization lines of the interconnect level. If the DSA/SAM material is sacrificial, it is removed and replaced with any suitable dielectric material at block <NUM>. At block <NUM>, that dielectric material may be further planarized with the metallization lines that were formed at block <NUM>. Alternatively, where the DSA/SAM material is a suitable dielectric material to permanently retain within the interconnect structure, blocks <NUM> and <NUM> may be skipped. Methods <NUM> may then be completed at the output <NUM>, for example with the formation of vias of the next interconnect level contacting various ones of the metallization lines fabricated thus far.

In the example illustrated in <FIG>, a metallization has been planarized into metallization lines <NUM> that occupy trenches between DSA/SAM material <NUM>. Metallization lines <NUM> and metallization lines <NUM> may each comprise any metal(s) suitable for integrated circuitry. Metallization lines <NUM> may have the same composition as metallization lines <NUM>, or may have a different composition. Because CMP may be relied upon to fully pattern both metallization lines <NUM> and metallization lines <NUM>, the both may comprise predominantly Cu, if desired. Alternatively, other metals more amenable to chemical etch may be employed for either, or both, of metallization lines <NUM> and <NUM>. For example, either, or both of metallization lines <NUM> and <NUM> may comprise any of Cu, Ru, W, Mo, Co, or Al.

In the example further illustrated in <FIG>, DSA/SAM material <NUM> has been replaced with a dielectric material <NUM>, which may, for example, have any of the compositions described elsewhere herein for dielectric materials <NUM>, <NUM>, <NUM>, or <NUM>. Interconnect structure <NUM> is now ready for the further fabrication of any additional interconnect levels desired. As shown, dielectric material <NUM> that has a top surface substantially co-planar with a top of metallization lines <NUM>. Metallization lines <NUM> are above dielectric material <NUM>, and are therefore in a upper plane (M2B) of interconnect level M2. Metallization lines <NUM>, being under metallization lines <NUM>, are therefore in a lower plane (M2A) of interconnect level M2. Because metallization lines <NUM> are formed through deposition(s) self-aligned to metallization lines <NUM>, a centerline CL of width W1 of each metallization line <NUM> is coincident with the centerline CL of the space between adjacent metallization lines <NUM>. Likewise, a centerline of CL of each metallization line <NUM> is coincident with the centerline CL of the space S1 between adjacent metallization lines <NUM>. This will be true even if there are differences in pitch between metallization lines <NUM> and <NUM>, for example as a result of a dimensional bias in the formation of metallization lines <NUM>. As shown in <FIG>, there is substantially no lateral separation between metallization lines <NUM> and <NUM> with metallization lines <NUM> having a width substantially equal to spacing S1 between metallization lines <NUM>. In other words, metallization line sidewall <NUM> has zero lateral offset from metallization lines sidewall <NUM>. The fill factor of metallization lines <NUM> and <NUM> is therefore also substantially <NUM>% within interconnect structure <NUM>. While such high line fill factor might result in electrical shorts or otherwise induce unacceptably high parasitic capacitance, the vertical separation (e.g., z-dimension) between metallization lines <NUM> and <NUM> ensures electrical isolation and reduces adjacent line parasitics. Hence, vertical separation of the intra-level (M2A-M2B) metallization lines can reduce electrical resistance and increase line density by increasing the line fill factor, as well as reduce intra-level parasitic capacitance.

The various exemplary methods of vertically spacing intra-level metallization lines, and there resulting structures may be further interconnected through a via metallization process that ensures at least the deeper vias which pass through a plane of the upper metallization lines have a smaller diameter than the lower metallization line widths. Shallower vias to the upper metallization level and deeper vias to the lower metallization level may be formed according to any known techniques of etching via openings and fill those openings with metallization. Single or double via patterning techniques may be employed, as embodiments herein are not limited in this respect.

<FIG> is a flow chart of methods <NUM> for fabricating vias to intra-level metallization lines that are vertically spaced, in accordance with some alternative embodiments. Methods <NUM> are an example of a spacer-based process that leverages non-planarity between the intra-level metallization lines to at least partially self-align via metallization to the lower metallization lines. <FIG> illustrate a plan view of a portion of an interconnect structure <NUM> evolving as methods <NUM> are practiced, in accordance with some embodiments. <FIG> illustrate a cross-sectional view of interconnect structure <NUM> along the B-B' line depicted in <FIG>, respectively. For <FIG>, a feature retaining the reference label of a feature introduced above in the context of <FIG> may have any of the attributes previously described for that feature.

Referring first to <FIG>, methods <NUM> begin at block <NUM> where a workpiece is received with upper and lower metallization lines within an IC interconnect level. In exemplary embodiments, the workpiece received at block <NUM> is any of interconnect structures <NUM>, <NUM> or <NUM> following the practice of methods <NUM>, <NUM> or <NUM>, respectively. In some examples, methods <NUM> are performed prior to block <NUM> in methods <NUM>, <NUM> or <NUM> at which point the upper level of metallization lines not yet planarized with a dielectric material.

Methods <NUM> continue at block <NUM> where a dielectric liner material is deposited between the upper metallization lines and over the lower metallization lines. A topography dependent process is then employed at block <NUM> to further form a cap or helmet structure over the portion of the dielectric liner material that is on the upper metallization lines. This helmet structure is then employed as an etch mask during an anisotropic "spacer" etch of the dielectric liner material at block <NUM>. Spacers of the dielectric liner material adjacent to the upper metallization lines then facilitate the formation of a partially self-aligned narrow via between the upper metallization lines.

In the example illustrated in <FIG>, interconnect structure <NUM> includes interconnect structure <NUM> following the deposition of dielectric liner material <NUM> over metallization lines <NUM> and <NUM>. Dielectric liner material <NUM> may be any suitable dielectric material (e.g., such as any of those described for dielectric materials <NUM> or <NUM>, etc.). As shown, a substantially conformal deposition process has been employed to deposit dielectric liner material <NUM> to a thickness less than half of the spacing S1. As further illustrated, a cap/helmet structure <NUM> is in contact with liner material <NUM> in regions over metallization lines <NUM>. Helmet structure <NUM> can be selectively formed according to a number of techniques known in the art, for example through catalytic deposition processes and/or non-conformal deposition processes. The interested reader is referred to <CIT> (commonly assigned) for a further description of techniques suitable for forming helmet structure <NUM>. As further illustrated in <FIG>, liner material <NUM> has been anisotropically etched to form trenches <NUM>, which expose a top of metallization lines <NUM> without exposing a sidewall of metallization lines <NUM>.

Returning to <FIG>, methods <NUM> continue at block <NUM> where a dielectric material having a composition distinct from that of the dielectric liner material is deposited into the trenches formed at block <NUM>, and planarized to some thickness suitable for an inter-level dielectric (ILD). Deep and shallow via openings are then patterned and etched in the dielectric material at block <NUM> with the deep via openings being restricted to a small diameter as a result of selectivity of the via etch. Via metallization may then be deposited into the deep and shallow vias. Methods <NUM> are then completed at output <NUM> following the completion of one or more additional levels of interconnect line metallization.

In the example illustrated in <FIG>, a dielectric material <NUM> has been planarized over metallization lines <NUM>. Although helmet structure <NUM> has been removed in this example, it may also be retained as a permanent feature of interconnect structure <NUM>.

As further illustrated in <FIG>, shallow via opening <NUM> and deep via opening <NUM> have been concurrently etched through dielectric material <NUM>. As illustrated, both via openings <NUM> and <NUM> have the maximum diameter D0 in a dimension parallel to a length of metallization lines <NUM> (e.g., y-dimension). However, within a dimension perpendicular to line length L1 (e.g., x-dimension), dielectric liner material <NUM> self-aligns via opening <NUM> down to a minimum diameter of Dmin, which is smaller than maximum diameter D0.

In the example shown in <FIG>, via metallization <NUM> has been deposited into shallow and deep vias, and planarized with dielectric material <NUM>. Interconnect structure <NUM> is then ready for a next level of line metallization. Although methods <NUM> have been described and illustrated in the context of forming narrow vias to lower metallization lines of one interconnect level, substantially the same technique may be applied to form narrow vias from upper metallization lines of an interconnect level to an underlying interconnect level. For example, methods <NUM> may be performed as part of block <NUM> in methods <NUM> (<FIG>).

<FIG> illustrates a mobile computing platform <NUM> and a data server machine <NUM> employing an IC including interconnect structures with vertically spaced intra-level line metallization, for example as described elsewhere herein. The server machine <NUM> may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing. In some exemplary embodiments server machine <NUM> includes a microprocessor <NUM> with vertically spaced intra-level line metallization, for example as described elsewhere herein. The mobile computing platform <NUM> may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform <NUM> may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system <NUM>, and a battery <NUM>.

At least one IC of chip-level or package-level integrated system <NUM> includes vertically spaced intra-level line metallization, for example as described elsewhere herein. In the illustrated example, integrated system <NUM> includes microprocessor <NUM> having vertically spaced intra-level line metallization, for example as described elsewhere herein. Microprocessor <NUM> may be further coupled to a board <NUM>, a substrate, or an interposer, one or more of a microcontroller <NUM>, a power management integrated circuit (PMIC) <NUM>, or an RF (wireless) integrated circuit (RFIC) <NUM> including a wideband RF (wireless) transmitter and/or receiver (TX/RX).

Functionally, PMIC <NUM> may perform battery power regulation, DC-to-DC conversion, etc., and has an input coupled to battery <NUM> and with an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, RFIC <NUM> has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond.

<FIG> is a functional block diagram of an electronic computing device <NUM>, in accordance with an embodiment of the present invention. Computing device <NUM> may be found inside platform <NUM> or server machine <NUM>, for example. Device <NUM> further includes a motherboard <NUM> hosting a number of components, such as, but not limited to, a processor <NUM> (e.g., an applications processor). Processor <NUM> may be physically and/or electrically coupled to motherboard <NUM>. In some examples, processor <NUM> includes self-aligned intra-level line metallization, for example as described elsewhere herein, for example as described elsewhere herein. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips <NUM> may also be physically and/or electrically coupled to the motherboard <NUM>. In further implementations, communication chips <NUM> may be part of processor <NUM>. Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to motherboard <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM <NUM>), non-volatile memory (e.g., ROM <NUM>), flash memory (e.g., NAND or NOR), magnetic memory (MRAM <NUM>), a graphics processor <NUM>, a digital signal processor, a crypto processor, a chipset <NUM>, an antenna <NUM>, touchscreen display <NUM>, touchscreen controller <NUM>, battery <NUM>, audio codec, video codec, power amplifier <NUM>, global positioning system (GPS) device <NUM>, compass <NUM>, accelerometer, gyroscope, speaker <NUM>, camera <NUM>, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips <NUM> may enable wireless communications for the transfer of data to and from the computing device <NUM>. Communication chips <NUM> may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device <NUM> may include a plurality of communication chips <NUM>. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The following examples are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

In first examples, an integrated circuit (IC) interconnect structure comprises a first interconnect level comprising a first metallization line co-planar with an adjacent second metallization line, a third metallization line out of a plane of the first and second metallization lines, the third metallization line having a centerline coincident with a centerline of a space between the first and second metallization lines. The IC interconnect structure further comprises a second interconnect level above or below the first interconnect level, the second interconnect level comprising one or more metallization lines interconnected to one or more of the first, second, or third metallization lines by via metallization.

In second examples, for any of the first examples the third metallization line has a width no smaller than the space between the first and second metallization lines.

In third examples, for any of the first through second examples a top surface of the third metallization line is below bottom surface of the first and second metallization lines.

In fourth examples, for any of the first through third examples the first and second metallization lines have a first metal composition, and the third metallization line has a second metal composition, different than the first.

In fifth examples, for any of the first through fourth examples the first metal composition comprises predominantly one of Cu, Ru, W, Mo, Co, or Al, and the second metal composition comprises predominantly one of Cu, Ru, W, Mo, Co, or Al.

In sixth examples, for any of the first through first examples the IC interconnect structure further comprises a liner dielectric material in contact with a sidewall of at least the third metallization, wherein the third metallization line has a width substantially equal to space between the first and second metallization lines minus twice a thickness of the liner dielectric material.

In seventh examples, for any of the sixth examples a top surface of the third metallization line is below bottom surface of the first and second metallization lines. The first, second, and third metallization lines all have substantially the same composition.

In eighth examples, for any of the first through seventh examples the via metallization comprises a first via metallization in contact the first line metallization, a second via metallization in contact with the third line metallization, and the first via metallization has a diameter smaller than the width of the first line metallization, or the second via metallization has a diameter smaller than a width of the third line metallization.

In ninth examples, for any of the eighth examples a top surface of the third metallization line is below the bottom surface of the first and second metallization lines, and the first via metallization has a minimum diameter, which is larger than the minimum diameter, perpendicular to a length of the first and second metallization lines, of the second via metallization. Alternatively, a top surface of the first metallization line and the second metallization line is below the bottom surface of the third metallization line, and the second via metallization has a minimum diameter, which is larger than the minimum diameter, perpendicular to a length of the first and second metallization lines, of the first via metallization.

In tenth examples, for any of the ninth examples the top surface of the third metallization line is below the bottom surface of the first and second metallization lines, and the first via metallization has a maximum diameter, which is substantially equal to the maximum diameter, parallel to a length of the first and second metallization lines, of the second via metallization. Alternatively, a top surface of the first metallization line and the second metallization line is below the bottom surface of the third metallization line, and the second via metallization has a maximum diameter, which is substantially equal to the maximum diameter, parallel to a length of the first and second metallization lines, of the first via metallization.

In eleventh examples, an integrated circuit (IC), comprises a device layer comprising a plurality of transistors comprising one or more semiconductor materials. The IC comprises a plurality of interconnect levels over the device layer. The interconnect levels further comprise a first interconnect level comprising a first metallization line co-planar with an adjacent second metallization line, a third metallization line out of a plane of the first and second metallization lines, the third metallization line having a centerline coincident with a centerline of a space between the first and second metallization lines. The interconnect levels further comprise a second interconnect level above or below the first interconnect level, the second interconnect level comprising one or more metallization lines interconnected to one or more of the first, second, or third metallization lines by via metallization.

In twelfth examples, for any of the eleventh examples the third metallization line has a width no smaller than the space between the first and second metallization lines.

In thirteenth examples, a computer platform comprises a power supply, and the IC of example eleven or twelve coupled to the power supply.

In fourteenth examples, a method of fabricating an interconnect structure comprises receiving a workpiece comprising a first metallization line co-planar with an adjacent second metallization line, with a first dielectric material in a space between the first and second metallization lines. The method comprises etching a trench into the first dielectric material as masked by the first and second metallization lines. The method comprises depositing metal into the trench. The method comprises forming a third line metallization between the first and second line metallizations by recessing a top surface of the metal to below a bottom of the first line metallization and a bottom of the second line metallization.

In fifteenth examples, for any of the fourteenth examples recessing the top surface of the metal further comprises etching the metal selectively to the first and second line metallizations.

In sixteenth examples, for any of the fourteenth through fifteenth examples the method further comprises depositing a dielectric liner material over a sidewall of the trench, and wherein recessing the top surface of the metal further comprises etching the metal selectively to the dielectric liner material.

In seventeenth examples, for any of the fourteenth through sixteenth examples the method further comprises depositing a second dielectric material over the first, second and third line metallizations. The method comprises forming a first via metallization through the second dielectric material to the first line metallization, and forming a second via metallization through the second dielectric material to the third line metallization.

In eighteenth examples, for any of the seventeenth examples the method further comprises forming a dielectric liner material adjacent to the first line metallization and adjacent to the second line metallization, and wherein forming the second via metallization further comprising etch through the second dielectric material selectively to the dielectric liner material.

In nineteenth examples, a method of fabricating an interconnect structure comprises receiving a workpiece comprising a first metallization line co-planar with an adjacent second metallization line, and a first dielectric material in a space between the first and second metallization lines. The method comprises forming a trench over the first dielectric material by selectively forming a second dielectric material over the first and second metallization lines. The method comprises depositing a third dielectric material over the first dielectric material and within a bottom of the trench. The method comprises depositing metal over the third dielectric material and within a top of the trench. The method comprises forming a third metallization line by planarizing the metal with the second dielectric material. The method comprises depositing a fourth dielectric material over the first, second and third metallization lines. The method comprises forming first via metallization to the first metallization line, and forming second via metallization to the third metallization line.

In twentieth examples, for any of the nineteenth examples selectively forming a second dielectric material over the first and second metallization lines further comprises a directed self assembly (DSA) of the second dielectric material.

Claim 1:
An integrated circuit, IC, interconnect structure (<NUM>; <NUM>; <NUM>), comprising:
a first interconnect level comprising:
a first metallization line co-planar with an adjacent second metallization line (<NUM>);
a third metallization line (<NUM>; <NUM>) out of a plane of the first and second metallization lines (<NUM>), the third metallization line (<NUM>; <NUM>) between and vertically separated from the first and second metallization lines (<NUM>), the third metallization line (<NUM>; <NUM>) having a centerline (CL) coincident with a centerline (CL) of a space (S1) between the first and second metallization lines (<NUM>); and
a second interconnect level above or below the first interconnect level, the second interconnect level comprising one or more metallization lines (<NUM>) interconnected to one or more of the first, second, or third metallization lines (<NUM>, <NUM>; <NUM>) by via metallization (<NUM>).