Patent Description:
The disclosure may hence relate to the technical field of (pulse-triggered) level shifter circuits and DC-DC converters.

Level shifter circuits are circuits that shift (translate) signals from one voltage domain to another voltage domain. In general, these voltage domains, as well as expected signal voltage swings, correspond to different supplies, not necessarily having any common reference potential. In context of present document, a level shifter circuit may shift logic signals between a low voltage supply domain of control logic and a supply domain of an actuator in presence of high voltage difference between their reference potentials.

Level shifter circuits are often applied in DC-DC converters which convert a source of direct current from one voltage domain to another, e.g. in a power management applications. In particular high-frequency synchronous DC-DC converters, dealing with high-voltage conversions, require command and feedback signals which are exchanged with delays in the (sub) nano-second (nS) scale between the low voltage supply domain of logic and the high voltage domain of a high-side switch gate driver, which is referenced either to the highest potential in the converter or to the converter switching node, transiting between low and high voltage during converter operation.

A drawback of conventional level shift circuits may be speed reduction at an increased voltage difference between. This issue is solved by applying a pulse-triggered level shifter circuit, known in the art. A pulse-triggered level shifter requires an additional pulse generator circuit to generate short pulses of currents, which pass between the low voltage domain of logic and the high voltage domain of the actuator, thereby toggling the output signal of a level shifter with respect to input signal. Due to a reduced voltage swing (when switching) in nodes of a pulse-triggered level shifter, comparing to the conventional level shifter, issues regarding signal propagation delays at an increase of the voltage difference between the low voltage domain of logic and the high voltage domain of actuator may be solved. The duration of pulses set by the additional pulse generator circuits is hereby selected to guaranty (by design) a state change (in particular of a latch circuit of the level shifter) of the output signal of the level shifter with respect to the input signal.

<FIG> shows a conventional example of a pulse-triggered level shifter pair <NUM>. Shown is an example of a conventional pulse-triggered level shifter pair to control a high-side switch of a DC-DC converter. The level shifter pair <NUM> comprises a command level shifter circuit <NUM> and a feedback level shifter circuit <NUM>. Each level shifter circuit <NUM>, <NUM> comprises a set path (low to high signal transition) and a reset path (high to low signal transition). The command level shifter circuit <NUM> comprises a first pulse generator <NUM> in a low voltage domain, and a first latch circuit <NUM> in a high voltage domain. A command input signal <NUM> is received via the first pulse generator <NUM> and an output signal <NUM> may be used as a feedback input signal <NUM>. The feedback level shifter circuit <NUM> comprises a second pulse generator <NUM> in a high voltage domain, and a second latch circuit <NUM> in a low voltage domain. A feedback output signal <NUM> can be used to build break-before-make operation of a synchronous low-side switch of said DC-DC converter (not shown). The duration of pulses (generated by the pulse generators <NUM>, <NUM>) is selected to guaranty (by design) state change of the latch circuits <NUM>, <NUM> and of the output signals with respect to input signals.

However, pulse generators also cause drawbacks: if the pulse duration is selected too short, the output state might not change during the pulse duration or the state change remains undetected by feedback, which might cause incorrect operation of DC-DC converter or complete malfunction due to cross-conduction condition on its output. If the pulse duration is set too long, the power consumption is unnecessarily increased.

United States patent application, publication number <CIT> discloses a high-speed level shifter circuit with reduced skew and method for level shifting, in which in general, the level shift circuit adds a pulse generator, a feedback transistor and a latch to a conventional cross-coupled level shift circuit configuration.

United States patent application, publication number <CIT> discloses a signal potential circuit of A. ramp, in which a first P-channel MOS transistor for charging a first node is connected in parallel with the second P-channel MOS transistor and the second P-channel MOS transistor is turned on in a pulsed manner in response to rising edge of an input signal. Further, the P-channel MOS transistor has its current drive ability defined to be approximately one tenth of that of an N channel MOS transistor for discharging the first node. Accordingly, each of the first node and a second node can be charged and discharged quickly to enable conversion of the signal potential to be accomplished speedily.

There may be a need to provide an accurate, energy-efficient, and robust (pulse-triggered) level shifter circuit, in particular for a DC-DC converter.

A level shifter circuit, and a DC-DC converter are provided.

According to an aspect of the present invention, there is provided a pulse-triggered level shifter circuit as defined in claim <NUM>.

According to a further aspect of the present disclosure, a DC-DC converter (in particular a synchronous DC-DC converter) is described, which comprises at least one pulse-triggered level shifter circuit as discussed above.

In the context of the present document, the term "pulse generator circuit" may in particular refer to an electronic circuit used to generate a pulse signal, e.g. a rectangular pulse. A pulse generator circuit is conventionally crucial for providing the pulses of a pulse-triggered level shifter circuit. Therefore, a dedicated pulse generator circuit is required for the pulse-triggered level shifter circuits of the prior art (e.g. <CIT>). The described pulse generator circuit of the prior art is a circuit which is presented in both, the command level shifter circuit and the feedback level shifter circuit. The duration of generated pulse should be selected to guaranty (by design) output signal change with respect to the input signal. When the duration is selected too short, the output signal might not change, causing incorrect operation or even damage of circuit using this prior art level shifter. If the pulse duration is set too long, the power consumption is unnecessarily increased.

In safety (human life) related applications, such as automotive, as example, and not necessarily related to power conversion, maloperation of level shifter might cause serious safety risk, which should be mitigated at any cost. Robust state change of shifted signal and feedback level shifter, allowing detection of command level shifter maloperation, are necessary countermeasures against potential incident.

According to an embodiment, the disclosure may be based on the idea that an accurate, energy efficient, and robust (pulse-triggered) level shifter circuit, in particular for a DC-DC converter, can be provided, when a command (level shifter) circuit and a feedback (level shifter) circuit are integrated into one single level shifter circuit. While conventionally a separate command level shifter circuit and a separate feedback level shifter circuit are applied (see e.g. <FIG> above), each having its own pulse generator with the above described disadvantages, in the presented disclosure two pulse-triggered level shifters may be combined and looped in one single (level shifter) circuit.

According to the invention, the command circuit and the feedback circuit are coupled via one or more connection elements, so that temporally limited current pulses are set in the command circuit and in the feedback circuit without using an additional pulse generator circuit (see definition above). Said temporally limited (the duration of command and feedback current pulses may be limited, but kept enough to guaranty proper functionality, e.g. state change) current pulses may be self-aligned and last until a command signal propagates and feeds back through both, the command circuit and the feedback circuit, of the one integrated pulse triggered level shifter.

In the described level shifter circuit, the duration of the current pulses may be always long enough (without using additional pulse generators and a selection of pulse duration) to guaranty proper function (in particular a state change of memory elements, see below). As a consequence, the described level shifter circuit may be more reliable and robust in comparison with prior art level shifters, in which pulse duration has to be selected in design to guaranty proper function (in particular state change) regardless of process, voltage and temperature variations.

In an embodiment, two of the described level shifter circuits are combined in a break-before-make circuit of a synchronous DC-DC converter. Furthermore, even three pulse-triggered level shifter circuits may be integrated in the described manner in one single circuit, thereby providing at the same time break-before-make control and over-current protection, e.g. in a synchronous DC-DC converter.

According to an embodiment, the level shifter circuit is free of a (dedicated) pulse generator circuit. This may provide that drawbacks caused by pulse generators are efficiently overcome, while material costs and energy can be saved. Said drawbacks may include that, if the pulse duration is selected too short and the output state is not changed during pulse duration, the state change remains undetected, and the pulse is not prolongated or repeated. If the pulse duration is set too long, the power consumption is increased.

According to a further embodiment, the level shifter circuit comprises at least one connection element (e.g. an AND-gate), wherein the command circuit and the feedback circuit are coupled via the at least one connection element, so that at least one temporally limited current pulse (in particular a command current pulse) is set by the at least one connection element after the command input signal is received (e.g. as an input signal to the connection element), and wherein the at least one current pulse lasts until the command output signal and the feedback output signal have been provided. This may provide that accurate and reliable pulses (the duration is always enough) are set without the need of an additional pulse generator circuit. Thereby, the reliability is increased, while material and energy costs are decreased.

According to a further embodiment, the command circuit comprises i) a set command path for low to high signal transition, wherein the set command path is triggered by a first temporally limited current pulse set by a first connection element (of the at least one connection element). In particular, a corresponding set feedback path may be established that is triggered by a first feedback current pulse set by a first further connection element.

Additionally or alternatively, the command circuit comprises ii) a reset command path for high to low signal transition, wherein the reset command path is triggered by a second temporally limited current pulse set by a second connection element (of the at least one connection element). In particular, a corresponding reset feedback path may be established that is triggered by a second feedback current pulse set by a second further connection element.

This may provide that the level shifter circuit can be applied in a flexible manner that allows different transitions without interfering with each other.

According to a further embodiment, the command input stage and the feedback output stage are coupled to an input terminal of the connection element (in particular an AND-gate), wherein an input to the at least one connection element comprises the command input signal and the feedback output signal, and wherein an output of the connection element comprises a temporally limited (command) current pulse. In particular an output terminal of the at least one connection element is coupled to a set pulse element (in particular a MOSFET). This may provide that the connection element may be realized in a straightforward and practical manner.

According to a further embodiment, the level shifter circuit further comprises at least one further connection element (in particular a MOSFET), wherein the command output stage and the feedback input stage are coupled to the at least one further connection element, wherein an input to the at least one further connection element comprises the feedback input signal and the command output signal, and wherein an output of the at least one further connection element comprises a temporally limited (feedback) current pulse. This may provide that the further connection element may be realized in a straightforward and practical manner.

According to a further embodiment, the level shifter circuit comprises two voltage domains. Hereby, i) the at least one connection element is arranged in the first voltage domain, and/or ii) the at least one further connection element is arranged in the second voltage domain. In this manner, the connection element design may be directly implemented into existing level shifter designs.

According to a further embodiment, the command circuit comprises a first memory element (in particular a first latch circuit), arranged in the first voltage domain, wherein the first memory element is coupled to the command output stage, and wherein the first memory element is configured to perform a first state change. Additionally or alternatively, the feedback circuit comprises a second memory element (in particular a second latch circuit), arranged in the second voltage domain, wherein the second memory element is coupled to the command circuit, and wherein the second memory element is configured to perform a second state change. In the described manner, an established a reliable electronic element can be provided in order to implement a state change. In an embodiment, the memory element is a latch circuit, e.g. a R/S latch, that changes state upon a specific voltage level.

According to a further embodiment the at least one connection element is configured to set the temporally limited current pulse long enough, so that the first state change and/or the second state change is enabled (in particular guaranteed) before the feedback output signal is provided. This may provide that the described level shifter circuit functions accurately and reliably.

According to a further embodiment, the second memory element is split into a first transition memory element for low to high signal transition and a second transition memory element for high to low signal transition. The level shifter circuit further comprises a further memory element, in particular a further latch circuit, coupled to the feedback circuit output stage. In the described manner, malfunctions within the feedback circuit may be efficiently overcome.

According to a further embodiment, the level shifter circuit further comprises an over-current protection circuit coupled within the feedback circuit, so that the command circuit, the feedback circuit, and the over-current protection circuit are integrated into one single level shifter circuit. In the described manner, it may be possible to even integrate an over-current protection mechanism into the already integrated level shifter circuit. Accordingly, in comparison to prior art examples, only one single level shifter circuit is applied instead of three separate level-shifter circuits.

In many cases, low-side and high-side switches, e.g. of synchronous DC-DC converter or of any other high voltage supply actuator, comprise integrated current sensors and/or over-current protection. Therefore, an over-current protection feedback signal may be passed using an additional level shifter circuit to the low voltage (control logic) domain to execute the protection mechanism. An over-current protection is generally time-spaced with respect to a turn-on process of either the low-side switch or the high-side switch. Some blanking time-out is generally recommended between turn-on and start of over-current detection to bypass noise created by power stage switching event. Accordingly, upon over-current detection, the corresponding switch should be turned off.

According to an embodiment, the described level shifter circuit is applied in (the power stage of) a DC-DC converter. In the context of the present document, the term "DC (-to-) DC converter" may in particular denote an electronic circuit or electromechanical device that converts a source of direct current (DC) from one voltage level to another. Power levels may range from very low (small batteries) to very high (high-voltage power transmission). A synchronous DC-DC converter may comprise a high-side switch and a low-side switch and require synchronous operation of said switches.

According to a further embodiment, the DC-DC converter comprises: a controller, (and a power stage comprising) a high-side switch (in particular comprising a level shifter circuit as described above), a low-side switch (in particular comprising a level shifter circuit as described above). Further, the DC-DC converter comprises a break-before-make circuit coupled between the controller, the high-side switch and the low-side switch. This may provide that the DC-DC converter can be operated in a robust and save manner. The break-before-make mechanism protects power stage of the converter from cross conduction at minimum value of dead time, which, when long, causes efficiency reduction in high-power converters.

A synchronous DC-DC converter may comprise a high-side switch and a low-side switch and require synchronous operation of said switches. In particular, one switch may not be allowed for being switched-on until the other switch is switched off. The time gap between these two instants of i) switching-off and then ii) switching-on, is called dead time, which may be traded-off to avoid cross conduction at too short or negative dead times and to reduce dead time dependent losses such as forward conduction and reverse-recovery at too long dead time. While there are approaches to control, regulate or adapt dead time in the prior art, except their complexity, such sophisticated approaches might not be robust and appreciated for applications working in noisy electrical environment, such as automotive, for instance. In this case, more straightforward and robust implementation such as "break-before-make" may be applied.

In the context of the present document, the term "break-before-make" may refer to a circuit, which comprises at least two switches. When the first switch is turned off (break), the break-before-make circuit may ensure that the first and the second switch are both off. Then, the second switch only is turned on (make). This may prevent two voltage domains (e.g. a high-side switch and a low-side switch) from being short-circuited during the changeover between said two switches.

The high-side switch and the low-side switch may comprise an integrated pulse-triggered level shifter circuit as described above. However, it is also possible that only the high-side switch or only the low-side switch comprises said level shifter circuit.

According to a further embodiment of the DC-DC converter, i) the high-side switch comprises a high-side command circuit and a high-side feedback circuit, ii) the low-side switch comprises a low-side command circuit and a low-side feedback circuit, iii) a high-side output (in particular the state of a high-side gate driver) of the high-side feedback circuit is used as a low-side input for the low-side command circuit (via the break-before-make circuit), and iv) a low-side output (in particular the state of a low-side gate driver) of the low-side feedback circuit is used as a high-side input for the high-side command circuit (via the break-before-make circuit). This may provide that the DC-DC converter can be operated especially robust and save.

The aspects defined above and further aspects of the disclosure are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment. The disclosure will be described in more detail hereinafter with reference to examples of embodiment.

Before, referring to the drawings, embodiments will be described in further detail, some basic considerations will be summarized based on which embodiments of the disclosure have been developed.

According to an embodiment, two different pulse-triggered level shifters are arranged into one single circuit, in which the duration of command current pulses and feedback current pulses is always enough (without dedicated pulse generators and selection of pulse duration) to guaranty state change (e.g. of respective latch circuits). In this manner, the described level shifter design is more reliable and robust in comparison with two independent pulse-triggered level shifters of the prior art, in which pulse duration has to be selected in design to guaranty proper state change regardless of process, voltage and temperature variations. In an embodiment, the integrated level shifter circuit is further enhanced to pass, without noticeable circuitry overhead, an additional over-current feedback signal, for which conventionally a third level shifter circuit would have been necessary.

According to an embodiment, it is a basic idea to combine a command level shifter circuit with a further feedback level shifter circuit into one pulse-triggered level shifter circuit so that pulse duration is bounded by signal propagation between the first and the second level shifter (i.e. command circuit and feedback circuit). Hence, the described new level shifter circuit does not require dedicated pulse generators and selection of pulse duration. Any malfunction in signal propagation and return could be easily detected in safety related applications. Moreover, the feedback circuit could be further re-used for yet another feedback signal propagation, such as over-current protection, thus excluding any need for a third level shifter.

<FIG> shows a pulse-triggered level shifter circuit <NUM> according to an embodiment. In contrast to the conventional example shown in <FIG> (see above), there is no pair of two separate level shifter circuits. Instead, there is only one single integrated pulse-triggered level shifter circuit <NUM> which comprises a command circuit <NUM> and a feedback circuit <NUM>. Furthermore, the pulse-triggered level shifter circuit <NUM> shown is free of a (dedicated) pulse generator.

The command circuit <NUM> comprises a set command path (low to high signal transition) <NUM> and a reset command path (high to low signal transition) <NUM>. The feedback circuit <NUM> in turn comprises a set feedback path <NUM> (corresponding to the set command path <NUM>) and a reset feedback path <NUM> (corresponding to the reset command path <NUM>). In the following, for the sake of clarity, the set command path <NUM> and the set feedback path <NUM> only are discussed in detail. The same description holds, however, true also for the reset command path <NUM> and the reset feedback path <NUM>. In the example shown, a pulse-triggered level shifter circuit <NUM> of a high-side switch <NUM> of a synchronous DC-DC converter <NUM> (see <FIG>) is shown.

The command circuit <NUM> comprises a command input stage <NUM> and connection elements 130a, 130b in a low voltage domain <NUM>, as well as a command output stage <NUM> and a first memory element <NUM> in a high voltage domain <NUM>. A command input signal <NUM> is received by command input stage <NUM> and is forwarded to a first connection element 130a in the set command path <NUM> or to a second connection element 130b in the reset command path <NUM>. In the example shown, the connection elements 130a, 130b are realized as AND-gates which receive the command input signal <NUM> and a feedback output signal <NUM> (see discussion below) as an input. The first connection element 130a controls (sets a first temporally limited (command) current pulse 116a) the set command path <NUM>, while the second connection element 130b controls (sets a second temporally limited (command) current pulse) the reset command path <NUM>. Hereby, the state of the first memory element <NUM> is controlled (changed). In the example shown, the first memory element <NUM> is realized as an R/S latch circuit and the set command path <NUM> comprises a set pulse element (MOSFET) <NUM> that is connected via a first current mirror <NUM> to the first memory element <NUM>. The set command path <NUM> is further coupled (in the example via the current mirror <NUM>) to a further connection element 140a. The further connection element 140a is implemented as a MOSFET that is coupled to a feedback input stage <NUM> and a set feedback path <NUM> (see discussion below). The state of the first memory element <NUM> controls the command output stage <NUM> that provides the command output signal <NUM>. Hereby, the voltage domain of the command output signal <NUM> is shifted with respect to the voltage domain of the command input signal <NUM>.

The feedback circuit <NUM> comprises the feedback input stage <NUM> and the further connection elements 140a, 140b in the high voltage domain <NUM>, and the feedback output stage <NUM> and a second memory element <NUM> in the low voltage domain <NUM>. The command output signal <NUM> is received by the feedback input stage <NUM> as a feedback input signal <NUM> and is forwarded to the first further connection element 140a in the set feedback path <NUM> or to the second further connection element 140b in the reset feedback path <NUM>. As described above, the further connection elements 140a, 140b are implemented as MOSFETs, wherein the source is connected to the set command path <NUM> (in particular the current mirror <NUM>), the drain is connected to the set feedback path <NUM>, and the gate is controlled by the feedback input signal <NUM>. The first further connection element 140a controls (sets a first feedback current pulse) the set feedback path <NUM>, and the second further connection element 140b controls (sets a second feedback current pulse) the reset feedback path <NUM>. Hereby, the state of the second memory element <NUM> is controlled (changed). In the example shown, the second memory element <NUM> is realized as an R/S latch circuit and the set feedback command path <NUM> is connected via a second current mirror <NUM> to the second memory element <NUM>. The set feedback path <NUM> is further coupled to the first connection element 130a. The second memory element <NUM> is further connected to the feedback output stage <NUM> which provides a feedback output signal <NUM>. Hereby, the voltage domain of the feedback output signal <NUM> is shifted with respect to the voltage domain of the feedback input signal <NUM>. The feedback output signal <NUM> can be used as an input for a low-side switch <NUM> via a break-before-make circuit <NUM> (see <FIG>).

The command circuit <NUM> serves as an initiator of switching. In case of low to high signal transition, the command chain sets the first command current pulse 116a in the set command path <NUM>. This current pulse 116a triggers a state change of the first memory element <NUM> located in the high voltage domain <NUM>. Then, the command output signal <NUM> is i) received by a high-side switch <NUM> (see <FIG>) and ii) returns back as feedback input signal <NUM>. The feedback input signal <NUM> confirms the state change by setting the first feedback current pulse 156a through the set feedback path <NUM>. In other words, the feedback current pulse 156a triggers state change of the second memory element <NUM> located in the low-voltage domain <NUM>. The corresponding feedback output signal <NUM> can be forwarded to a break-before-make circuit <NUM> (see <FIG>). A state change of the second memory element <NUM> discontinues both current pulses <NUM>, <NUM> in set command path <NUM> and set feedback path <NUM>.

In a similar manner, the described level shifter circuit <NUM> operates at high to low signal transition by setting the second command current pulse 116b in the reset command path <NUM> and the second feedback current pulse 156b in the reset feedback path <NUM>.

<FIG> illustrates a further pulse-triggered level shifter circuit <NUM> according to a further embodiment. With respect to the design shown in <FIG>, a severe failure in the feedback signal return path may lock the level shifter circuit <NUM>. For instance, the circuit <NUM> could remain in a state that corresponds to on-state of a high-side switch, while the feedback reports its state corresponding to off-state of said high-side switch, which may cause e.g. cross conduction collision. Such condition can be prevented by the circuit modification shown in <FIG>.

Hereby, the second memory element <NUM> is split into a modified first transition memory element 255a for low to high signal transition and a modified second transition memory element 255b for high to low signal transition. The level shifter circuit <NUM> further comprises a further memory element (realized as a RS-latch circuit with NAND gates) <NUM> coupled to the feedback output stage <NUM> for feedback output signal <NUM> formation. In presence of the feedback signal, any malfunction in signal propagation could be easily detected in control logic by comparing command and feedback signals in safety related applications. It should be also noticed, that is common for pulse-triggered level shifters, that their command and feedback (RS) latch(es) should be set in proper state by reset circuitry. Even, if by some reason states in low voltage domain and high voltage domain mismatch, their proper correspondence will be auto-recovered after at least a complete cycle of state changing.

<FIG> illustrates a further pulse-triggered level shifter circuit <NUM> according to another embodiment. In this example, an over-current protection circuit is coupled within the feedback circuit <NUM>, so that the command circuit <NUM>, the feedback circuit <NUM>, and the over-current protection circuit are integrated into one single level shifter circuit <NUM>. The described integrated level shifter circuit <NUM> is enabled to pass over-current fault feedback to control logic, while the conventional need to provide a third level shifter circuit is excluded.

An over-current fault feedback signal is passed by initiating over-current pulses (see over-current input stage <NUM>, over-current pulse elements 362a,b, and over-current and feedback connection elements 363a,b) in the set feedback path <NUM> and the reset feedback path <NUM>. Generally, over-current pulse elements 362a,b should be large (big size) high-voltage switches, in particular the same as the further connection elements 140a,b of level-shifter circuit <NUM>. In this embodiment, over-current and feedback connection elements 363a,b require only two instead of four high-voltage switches, "cascades" (isolates from high-voltage) low-voltage pulse elements 362a,b and low-voltage further connection elements of feedback paths. The over-current fault feedback signals are then detected with a corresponding (low voltage domain) over-current fault receiver circuitry <NUM> and reported as an over-current fault signal via an over-current output stage <NUM> to logic circuitry. In order to avoid interferences with the feedback and its memory element <NUM> (255a,b), the over-current signal is gated by MOSEFTs (see over-current gates 361a, b). In the example shown (which is based on <FIG>), the first transition memory element 255a ("set pulse RS latch") is gated by switch for events other than a set pulse generation. The second transition memory element 255b ("reset pulse RS latch") is gated by switch for over-current fault events.

As a consequence, an over-current fault leads logic to turn-off the switch, which caused the over-current fault, and initiates a turn-off signal propagation through the reset command path <NUM>. When an over-current fault is released in the high voltage domain <NUM> immediately by turn-off command, current pulses in reset command path <NUM> and reset feedback path <NUM> discontinue, and over-current fault is released in the receiver circuitry <NUM> which unlocks, via gates 361a,b, the transition memory elements 255a/b. So feedback signal <NUM>, which comes with delay in respect to release of the over-current signal due to signal propagation in gate driver, initiates a regular, in terms of circuit <NUM> and <NUM>, turn-off process utilizing currents in reset command path <NUM> and set feedback path <NUM>.

<FIG> illustrates a DC-DC converter <NUM> with a level shifter circuit <NUM> as described above according to an embodiment. Shown is the power stage (output filter is not shown) of a synchronized step-down DC-DC converter <NUM>, having a bootstrapped high-side n-channel power MOSFET switch. The DC-DC converter <NUM> comprises: a controller <NUM>, a high-side switch <NUM> (in particular comprising a level shifter circuit <NUM> as described above), a low-side switch <NUM> (in particular comprising a level shifter circuit <NUM> as described above). Further, the DC-DC converter <NUM> comprises a break-before-make circuit <NUM> coupled between the controller <NUM>, the high-side switch <NUM>, and the low-side switch <NUM>. The break-before-make mechanism excludes risk of cross conduction condition, when high-side switch <NUM> might be turned-on before low-side switch <NUM> is turned-off and vice versa. A high-side output of the high-side feedback circuit <NUM> is used as a low-side input for the low-side command circuit <NUM> via the break-before-make circuit <NUM>. Further, a low-side output of the low-side feedback circuit is used as a high-side input for the high-side command circuit via the break-before-make circuit. The high-side switch <NUM> comprises a high-side gate drive <NUM> coupled to a high-side switch <NUM>, and the low-side switch <NUM> comprises a low-side gate driver <NUM> coupled to a low-side switch <NUM>.

<FIG> illustrates a simulation of a level shifter circuit <NUM> according to <FIG> in the power stage of a DC-DC converter <NUM>. The level shifter circuit <NUM> was designed to translate a first swing input command signal into a second swing output across a voltage difference. Shown is low-to-high state propagation waveforms of key signals, such as command input signal <NUM>, command output signal <NUM>/feedback input signal <NUM>, feedback output signal <NUM>, set pulse 116a, and currents in set command path <NUM> and set feedback path <NUM>. The designed circuit (w/o fine optimization) shows <NUM> pS/<NUM> nS propagation delays of the command signal, from which <NUM> pS/<NUM> pS are delays of command signal propagation through command output's buffer.

<FIG> illustrates a simulation of a level shifter circuit <NUM> according to <FIG> in the power stage of a DC-DC converter <NUM>. The level shifter circuit <NUM> has been simulated in condition of severe short circuit of power stage's output to ground. Shown is over-current signal and corresponding high-to-low state propagation waveforms of key signals at over-current fault protection, such as over-current fault signal on the over-current input <NUM> and on the over-current output <NUM>, command input signal <NUM>, command output signal <NUM>/feedback input signal <NUM>, feedback output signal <NUM>, set pulse 116b, and currents in reset command path <NUM> and reset feedback path <NUM>.

Claim 1:
A pulse-triggered level shifter circuit (<NUM>) comprising:
a command circuit (<NUM>) configured to shift a command input signal (<NUM>) of a first voltage domain to a command output signal (<NUM>) of a second voltage domain, wherein the command circuit (<NUM>) comprises:
a command input stage (<NUM>) for receiving the command input signal (<NUM>),
a command output stage (<NUM>) for providing the command output signal (<NUM>);
a feedback circuit (<NUM>), coupled to the command circuit (<NUM>), and configured to shift a feedback input signal (<NUM>) of the second voltage domain to a feedback output signal (<NUM>) of the first voltage domain, wherein the feedback circuit (<NUM>) comprises:
a feedback input stage (<NUM>) for receiving the command output signal (<NUM>) as the feedback input signal (<NUM>), and
a feedback output stage (<NUM>) for providing the feedback output signal (<NUM>); wherein the command circuit (<NUM>) and the feedback circuit (<NUM>) are integrated into one single level shifter circuit (<NUM>); and .
at least one connection element (130a, 130b) arranged in the first voltage domain (<NUM>), wherein the command circuit (<NUM>) and the feedback circuit (<NUM>) are coupled via the at least one connection element (130a, 130b),
so that at least one temporally limited current pulse (116a, 116b) is set by the at least one connection element (130a, 130b) after the command input signal (<NUM>) is received, and wherein the at least one current pulse (116a, 116b) lasts until the command output signal (<NUM>) and the feedback output signal (<NUM>) have been provided;
at least one further connection element (140a, 140b) arranged in the second voltage domain (<NUM>),
wherein the command output stage (<NUM>) and the feedback input stage (<NUM>) are coupled to the at least one further connection element (140a, 140b),
wherein an input to the at least one further connection element (140a, 140b) comprises the feedback input signal (<NUM>) and the command output signal (<NUM>), and
wherein an output of the at least one further connection element (140a, 140b) is a temporally limited feedback current pulse (156a, 156b).