Patent Description:
Various applications, such as automotive in-car communication systems, certain industrial communication systems and smart-home systems, require communication at high data rates over relatively small distances. Several types of protocols and communication media have been proposed for such applications. For example, Ethernet communication over twisted-pair copper wire media is specified in "<NPL>; in "<NPL>; in "<NPL>; and in "<NPL>.

The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application. <CIT> discloses a method of determining crosstalk in a multiple-input-multiple output (MIMO) system. The method includes receiving, from at least one first remote node, upstream pilots on an upstream channel, determining upstream channel coefficients based on the received pilots, transmitting, to the at least one first remote node, downstream pilots on a downstream channel, receiving, from the at least one first remote node, loopback pilots on the upstream channel, the loopback pilots being loopback signals of the downstream pilots, and determining downstream channel coefficients based on the received downstream pilots.

It is the object of the present invention to enable an improved communication between Ethernet physical layer transceivers.

The object is solved by the subject matter of the independent claims which define the present invention.

An embodiment that is described herein provides an Ethernet physical layer (PHY) transceiver including a transmitter and a receiver. The transmitter is configured to precode a first data stream by summing two or more mutually-delayed replicas of the first data stream, and to transmit the precoded first data stream over a full-duplex wired channel to a peer Ethernet PHY transceiver. The receiver is configured to receive a second data stream from the peer Ethernet PHY transceiver over the full-duplex wired channel, and to decode the received second data stream while the transmitter concurrently is transmitting the precoded first data stream.

In an embodiment, the transmitter is configured to precode the first data stream by (i) delaying the first data stream so as to produce a delayed replica, and (ii) summing the first data stream and the delayed replica. In another embodiment, the transmitter is configured to precode the first data stream by (i) delaying the first data stream so as to produce a delayed replica, and (ii) subtracting the delayed replica from the first data stream, or the first data stream from the delayed replica.

In disclosed embodiments, the transmitter is configured to transmit the first data stream at a first data rate, and the receiver is configured to receive the second data stream at a second data rate, higher than the first data rate. In an example embodiment, the receiver is configured to receive and decode the precoded second data stream without concurrently cancelling echoes of the first data stream. In an embodiment, the transmitter and the receiver are configured to communicate the first data stream and the second data stream between electronic units in a vehicle.

There is additionally provided, in accordance with an embodiment that is described herein, an Ethernet PHY transceiver including a receiver and a transmitter. The receiver is configured to receive a first data stream from a peer Ethernet PHY transceiver over a full-duplex wired channel, wherein the first data stream is precoded using a precoding scheme that sums two or more mutually-delayed replicas of the first data stream, and to decode the received first data stream, the decoding including applying to the first data stream a decoding scheme that reverses the precoding scheme. The transmitter is configured to transmit a second data stream over the full-duplex wired channel to the peer Ethernet PHY transceiver while the receiver concurrently is receiving and decoding the first data stream.

In an embodiment, the receiver is configured to decode the first data stream by (i) delaying the first data stream by a delay element, so as to produce a delayed replica, (ii) feeding the delayed replica from an output of the delay element back to an input of the delay element, and (iii) subtracting the delayed replica from the first data stream, or the first data stream from the delayed replica. In another embodiment, the receiver is configured to decode the first data stream by (i) delaying the first data stream by a delay element, so as to produce a delayed replica, (ii) feeding the delayed replica from an output of the delay element back to an input of the delay element, and (iii) summing the delayed replica and the first data stream.

In disclosed embodiments, the receiver is configured to receive the first data stream at a first data rate, and the transmitter is configured to transmit the second data stream at a second data rate, higher than the first data rate. In an embodiment, the receiver is configured to receive and decode the precoded first data stream without concurrently cancelling echoes of the second data stream. In an example embodiment, the transmitter and the receiver are configured to communicate the first data stream and the second data stream between electronic units in a vehicle.

There is also provided, in accordance with an embodiment that is described herein, an Ethernet PHY communication method, including precoding a first data stream by summing two or more mutually-delayed replicas of the first data stream, and transmitting the precoded first data stream over a full-duplex wired channel. A second data stream is received over the full-duplex channel. The received second data stream is decoded while the precoded first data stream concurrently is transmitted.

There is further provided, in accordance with an embodiment that is described herein, an Ethernet PHY communication method, including receiving a first data stream over a full-duplex wired channel, wherein the first data stream is precoded using a precoding scheme that sums two or more mutually-delayed replicas of the first data stream. The received first data stream is decoded, the decoding including applying to the first data stream a decoding scheme that reverses the precoding scheme. A second data stream is transmitted over the full-duplex channel while the first data stream concurrently is received and decoded.

The present disclosure will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:.

Embodiments that are described herein provide improved Ethernet physical layer (PHY) transceivers and associated methods, for communication over full-duplex two-way channels, e.g., twisted-pair copper wire links. The embodiments described herein refer mainly to asymmetric links, in which the transmission bit rates differ between the two directions of the two-way link.

The asymmetric PHY transceivers described herein are useful, for example, in automotive applications, e.g., systems that collect data from sensors within a vehicle and also control and configure the sensors. The disclosed techniques are generally applicable, however, in various other applications that involve asymmetric links, for example in industrial and/or smart-home networks, as well as in video distribution systems. Certain aspects of bidirectional asymmetric Ethernet communication in such environments are addressed in <CIT>, entitled "Asymmetric Energy Efficient Ethernet"; and in <CIT>, entitled "Managing Bidirectional Communication in Constrained Environments" which are assigned to the assignee of the present patent application and whose disclosures are incorporated herein by reference.

Consider a pair of Ethernet PHY transceivers that communicate with one another in full-duplex over a single twisted-pair link. One PHY transceiver transmits at a bit rate referred to as "low speed" (LS) and receives at a bit rate referred to as "high speed" (HS). The other PHY transceiver transmits at the LS bit rate and receives at the HS bit rate. In a typical example the HS bit rate is <NUM> bits per second (10Gbps), and the LS bit rate is 100Mbps or 10Mbps.

In a full-duplex scenario, the signals transmitted by both PHY transceivers ae present simultaneously on the twisted-pair link. Transmission of each signal therefore is likely to interfere with reception of the other signal. This effect is referred to as an "echo". In the present context, an echo means a signal that is transmitted from a transmitter of a PHY transceiver and interferes with the receiver of the same PHY transceiver. In a given PHY transceiver, echoes may propagate from the transmitter to the receiver on various paths and a result of various leakage or reflection mechanisms.

It is possible in principle to reduce such interference using echo cancellation techniques, but echo cancellation is generally complex and increases the cost, size and power consumption of the PHY transceivers. Another possibility is to assign each direction of the link a separate frequency band, with suitable spectral separation between the bands and suitable filtering. Such a solution is complex and costly, as well, and also reduces the achievable data throughput.

The embodiments described herein obviate the need for interference cancellation or intensive filtering, and instead reduce the interference using transmitter-side precoding and receiver-side decoding. The term "precoding" means arithmetic manipulation of the input data stream at the bits level, before modulation. Typically, a precoding operation comprises summing, bit-by-bit, two or more mutually-delayed replicas of the input data stream. For example, in a precoding scheme denoted "<NUM>+D", the transmitter delays the input data by one bit to produce a delayed replica, and sums the input data and the delayed replica. In another precoding scheme, denoted "<NUM>-D", the transmitter delays the input data by one bit to produce a delayed replica, and subtracts the delayed replica from the input data (or the input data from the delayed replica). As will be shown below, an appropriately chosen precoding scheme has a spectral shaping effect similar to low-pass filtering or high-pass filtering, and therefore can be effective in interference suppression.

In some embodiments, the precoding schemes in the disclosed PHY transceivers are chosen based on the power spectra of the LS and HS signals. As such, the PHY transceiver that transmits the LS signal may use a different precoding scheme than the PHY transceiver that transmits the HS signal. In an example embodiment, the PHY transceiver that transmits the LS signal (and receives the HS signal) applies (<NUM>+D) precoding. The (<NUM>+D) precoding scheme has a Low-Pass Filtering effect on the spectrum of the transmitted LS signal, and therefore reduces interference (e.g., local echoes) that might interfere with reception of the HS signal in the PHY transceiver. In another example embodiment, the PHY transceiver that transmits the HS signal (and receives the LS signal) applies (<NUM>-D) precoding. The (<NUM>-D) precoding operation has a High-Pass Filtering effect on the spectrum of the transmitted HS signal, and therefore reduces interference that might interfere with reception of the LS signal in the PHY transceiver. Simulated examples of signal spectra can be seen in <CIT>, cited above, which is incorporated herein by reference in its entirety.

In summary, the disclosed techniques reduce interference in full-duplex two-way Ethernet links with low cost, size and power consumption, and with minimal performance degradation. Example PHY device implementations are described. A hybrid configuration, in which transmitter-side precoding is used only in the LS transmitter, and echo cancellation is applied in the LS receiver, is also described. In this configuration the echo cancellation operations are performed at the LS rate, and therefore incur only modest overhead.

<FIG> is a block diagram that schematically illustrates an automotive communication system <NUM>, in accordance with an embodiment that is described herein. System <NUM> is installed in a vehicle <NUM>, and comprises multiple sensors <NUM>, an Ethernet switch <NUM>, multiple microcontrollers (µC) <NUM>, a central controller (CC) <NUM>, multiple Ethernet physical layer (PHY) transceivers <NUM> of a first type (denoted PHY1), and multiple Ethernet PHY transceivers <NUM> of a second type (denoted PHY1).

In various embodiments, sensors <NUM> may comprise any suitable types of sensors. Several non-limiting examples of sensors comprise video cameras, velocity sensors, accelerometers, audio sensors, infra-red sensors, radar sensors, lidar sensors, ultrasonic sensors, rangefinders or other proximity sensors, and the like.

In the present example, each sensor <NUM> is connected to a respective microcontroller <NUM>, which is in turn connected to a respective PHY transceiver <NUM>. The PHY transceiver <NUM> of each sensor <NUM> is connected by a link <NUM> to a peer PHY transceiver <NUM> coupled to a port of switch <NUM>. On the sensor side of a given link, microcontroller <NUM> serves as a Medium Access Control (MAC) controller. On the switch side of a given link, MAC functions are carried out by switch <NUM>.

Automotive communication system <NUM> is an example use-case suitable for asymmetric Ethernet communication. Typically, sensors <NUM> generate large amounts of data that is sent to central computer (CC) <NUM> for analysis. In the opposite direction, the data typically comprises low-rate control and configuration data from CC <NUM> to sensors <NUM>. In such a scenario, asymmetric communication provides better utilization of Ethernet links <NUM>.

In the embodiment of <FIG>, PHY transceivers <NUM> (denoted PHY1) transmit at a bit rate referred to as "low speed" (LS) and receive at a bit rate referred to as "high speed" (HS). PHY transceivers <NUM> (denoted PHY2) transmit at the "high speed" (HS) bit rate and receive at the "low speed" (LS) bit rate. Pairs of PHY transceivers <NUM> and <NUM> communicate with one another over twisted-pair copper links <NUM>, which serve as full-duplex wire channels. As seen in the figure, the pairs of PHY transceivers <NUM> and <NUM> are arranged so that transmission from sensors <NUM> to CC <NUM> is performed at the HS bit rate, and transmission from CC <NUM> to sensors <NUM> is performed at the LS bit rate, in an embodiment.

In one embodiment, the HS bit rate is <NUM> bits per second (10Gbps) in accordance with IEEE <NUM>. 3ch, and the LS bit rate is 100Mbps in accordance with IEEE <NUM>. In another embodiment, the HS bit rate is 10Gbps in accordance with IEEE <NUM>. 3ch, and the LS bit rate is 10Mbps in accordance with IEEE <NUM>. 3cg(10Base-T1s). In alternative embodiments, the LS bit rate and the HS bit rate may be chosen to be any other suitable bit rates. The link between PHY transceivers <NUM> and <NUM> may comprise any other two-way medium suitable for full-duplex communication.

<FIG> is a block diagram that schematically illustrates a pair of asymmetric Ethernet physical layer (PHY) transceivers <NUM> and <NUM> of system <NUM>, communicating over a full-duplex two-way link <NUM>, in accordance with an embodiment that is described herein. The term "asymmetric" in the present context means that the transmission bit rates differ between the two directions of the two-way link. As noted above, PHY transceiver <NUM>, denoted PHY1, transmits at the "low speed" (LS) bit rate and receives at the "high speed" (HS) bit rate. PHY transceiver <NUM>, denoted PHY2, transmits at the "high speed" (HS) bit rate and receives at the "low speed" (LS) bit rate.

In the disclosed embodiments, the LS communication (PHY1 to PHY2, left-to-right in <FIG>) and the HS communication (PHY2 to PHY1, right-to-left in <FIG>) are conducted simultaneously over the same twisted-pair link <NUM>. In the frequency domain, the Power Spectral Density (PSD) of the LS signal is concentrated between baseband and <NUM> (for a 100Mbps signal) or between baseband and <NUM> (for a 10Mbps signal). The PSD of the 10Gbps HS signal is concentrated between baseband and <NUM>. Thus, the spectra of the HS and LS signal overlap at the bottom of the spectrum, and may interfere with one another. As will be shown below, this mutual interference is mitigated by using precoding in the transmitter and decoding in the peer receiver, at least in one direction of the link.

In the embodiment of <FIG>, PHY transceiver <NUM> comprises a LS transmitter (LS TX) <NUM> that is configured to generate and transmit the LS signal over link <NUM>, and PHY transceiver <NUM> comprises a LS receiver (LS RX) <NUM> that is configured to receive the LS signal. PHY transceiver <NUM> comprises a HS transmitter (HS TX) <NUM> that is configured to generate and transmit the HS signal over link <NUM>, and PHY transceiver <NUM> comprises a HS receiver (HS RX) <NUM> that is configured to receive the HS signal.

In an embodiment, LS TX <NUM> receives input LS data ("LS DATA IN"), typically from an Ethernet Medium Access Control (MAC) device (not shown in the figure for clarity) that is coupled to PHY transceiver <NUM>. LS TX <NUM> comprises a LS precoder <NUM> that precodes the input LS data ("LS DATA IN"), and a TX driver <NUM> that transmits the precoded LS data over link <NUM>. In the present example, LS precoder <NUM> applies a (<NUM>+D) precoding scheme, i.e., delays the input data by one bit using a delay element (D) to produce a delayed replica, and sums the input data and the delayed replica using an adder. The input data values are assumed, without loss of generality, to be ±<NUM>.

LS RX <NUM> comprises an input filter <NUM>, in the present example comprising a combination of a Low-Pass Filter (LPF) and a High-Pass Filter (HPF), which filters the signal received from link <NUM>. In alternative embodiments, other suitable types of filters can be used. LS RX <NUM> further comprises an Analog-to-Digital Converter (ADC) <NUM> that digitizes (samples) the filtered signal, an equalizer <NUM> that equalizes the digitized signal, and a slicer <NUM> that slices the signal at the equalizer output, i.e., makes bit decisions. In the absence of errors, the bit stream at the output of slicer <NUM> is identical to the precoded data produced by LS precoder <NUM>. In an embodiment, the output of slicer <NUM> is fed back to a Digital timing Loop (DTL) <NUM>, which adjusts the sampling clock of ADC <NUM>.

In the embodiment of <FIG>, LS RX <NUM> further comprises a LS decoder <NUM>, which recovers the original input data ("LS DATA IN") from the output of slicer <NUM> (i.e., from the precoded data). LS decoder <NUM> applies a decoding scheme that is the inverse of (i.e., that reverses) the precoding scheme used by LS precoder <NUM>. In the present example LS decoder <NUM> applies a (<NUM>/(<NUM>+D)) decoding scheme by (i) delaying the precoded data by one bit using a delay element (D) so as to produce a delayed replica, (ii) feeding the delayed replica from the output of the delay element back to the input, and (iii) subtracting the delayed replica of the precoded data from the precoded data (or alternatively subtract the precoded data from the delayed replica of the precoded data).

In the absence of errors, the bit stream at the output of LS decoder <NUM> ("LS DATA OUT") is identical to the original input data ("LS DATA IN"). The "LS DATA OUT" bit stream is provided as the output of LS RX <NUM>, and of PHY transceiver <NUM> as a whole. The "LS DATA OUT" bit stream is typically delivered to an Ethernet MAC device (not shown in the figure for clarity) that is coupled to PHY transceiver <NUM>.

The (<NUM>+D) precoding operation in LS TX <NUM> has a Low-Pass Filtering effect that reduces the PSD of the LS signal at high frequencies. One simulated example PSD can be seen in <CIT>, cited above. As such, the precoding operation reduces interference (e.g., echoes) that might interfere with reception of the HS signal by HS RX <NUM>. At the same time, the precoding operation of LS TX <NUM> is fully recoverable by the inverse decoding operation of LS RX <NUM>.

In an embodiment, HS TX <NUM> is provided with input HS data ("HS DATA IN"), typically from an Ethernet MAC device (not shown in the figure) that is coupled to PHY transceiver <NUM>. HS TX <NUM> comprises a HS precoder <NUM> that precodes the input HS data ("HS DATA IN"), and a TX driver <NUM> that transmits the precoded HS data over link <NUM>. In the present example, HS precoder <NUM> applies a (<NUM>-D) precoding scheme, i.e., delays the input data by one bit using a delay element (D) to produce a delayed replica, and subtracts the delayed replica from the input data (or the input data from the delayed replica) using an adder. The input data values are again assumed, without loss of generality, to be ±<NUM>.

HS RX <NUM> comprises an input filter <NUM>, in the present example comprising a combination of a LPF and a HPF, which filters the signal received from link <NUM>. HS RX <NUM> further comprises an ADC <NUM> that digitizes (samples) the filtered signal, an equalizer <NUM> that equalizes the digitized signal, and a slicer <NUM> that slices the signal at the equalizer output, i.e., makes bit decisions. In the absence of errors, the bit stream at the output of slicer <NUM> is identical to the precoded data produced by HS precoder <NUM>. In an embodiment, the output of slicer <NUM> is fed back to a DTL <NUM> that adjusts the sampling clock of ADC <NUM>.

In the embodiment of <FIG>, HS RX <NUM> further comprises a HS decoder <NUM>, which recovers the original input data ("HS DATA IN") from the output of slicer <NUM> (i.e., from the precoded data). HS decoder <NUM> applies a decoding scheme that is the inverse of (i.e., that reverses) the precoding scheme used by HS precoder <NUM>. In the present example HS decoder <NUM> applies a (<NUM>/(<NUM>-D)) decoding scheme by (i) delaying the precoded data by one bit using a delay element (D) so as to produce a delayed replica, (ii) feeding the delayed replica from the output of the delay element back to the input, and (iii) summing the precoded data and the fed-back delayed replica of the precoded data.

In the absence of errors, the bit stream at the output of HS decoder <NUM> ("HS DATA OUT") is identical to the original input data ("HS DATA IN"). The "HS DATA OUT" bit stream is provided as the output of HS RX <NUM>, and of PHY transceiver <NUM> as a whole. The "HS DATA OUT" bit stream is typically delivered to an Ethernet MAC device (not shown in the figure) that is coupled to PHY transceiver <NUM>.

The (<NUM>-D) precoding operation in HS TX <NUM> has a High-Pass Filtering effect that reduces the PSD of the HS signal at low frequencies, near baseband. A simulated example PSD can be seen in <CIT>, cited above. As such, the precoding operation reduces interference (e.g., local echoes) that might interfere with reception of the LS signal by LS RX <NUM>. At the same time, the precoding operation of HS TX <NUM> is fully recoverable by the inverse decoding operation of HS RX <NUM>.

In the example of <FIG>, precoding is applied both in the LS transmission and in the HS transmission. Consequently, obviating the need for echo cancellation in both PHY transceivers. In alternative embodiments, precoding may be applied only in one direction, with one of the PHY transceivers still performing echo cancellation. An embodiment of this sort is shown in <FIG> below.

<FIG> is a flow chart that schematically illustrates a method for communication between asymmetric Ethernet PHY transceivers <NUM> and <NUM> of <FIG>, in accordance with an embodiment that is described herein. The method is described in the context of one direction, e.g., LS transmission from LS TX <NUM> to LS RX <NUM>, or HS transmission from HS TX <NUM> to HS RX <NUM>.

The method begins with the precoder of the TX (precoder <NUM> or <NUM> as appropriate) precoding input data, at a precoding operation <NUM>. In the example of <FIG>, the precoding scheme is (<NUM>+D) for LS transmission and (<NUM>-D) for HS transmission. At a transmission operation <NUM>, the TX driver (TX driver <NUM> or <NUM> as appropriate) modulates the precoded data and transmits the resulting signal over link <NUM>.

At a reception operation <NUM>, the receiver (LS RX <NUM> or HS RX <NUM> as appropriate) receives the signal from link <NUM>. At a receiver-side processing operation <NUM>, the receiver filters, digitizes, equalizes and slices the received signal, as described above. At a decoding operation <NUM>, the decoder of the receiver (decoder <NUM> or <NUM> as appropriate) decodes the precoded data provided by the slicer. In the example of <FIG>, the decoding scheme is (<NUM>/(<NUM>+D)) for LS transmission and (<NUM>/(<NUM>-D)) for HS transmission. The decoded data is provided as output.

<FIG> is a block diagram that schematically illustrates an asymmetric Ethernet PHY transceiver <NUM>, in accordance with an alternative embodiment that is described herein. In this example, precoding is applied only in the LS TX (of the peer PHY transceiver) and not in the HS TX (of PHY transceiver <NUM>), and thus decoding is applied only in the LS RX (of PHY transceiver <NUM>) and not in the HS RX (of the peer PHY transceiver). Typically, although not necessarily, the precoding scheme is (<NUM>+D) and the decoding scheme is (<NUM>/(<NUM>+D)).

In addition, the PHY device comprising the LS RX performs echo cancellation, for suppressing echoes of the transmitted HS signal that may interfere with the reception of the LS signal. Typically, cancellation of echoes of the HS signal in the LS RX (interference from the signal transmitted by HS TX <NUM> to reception of the LS signal by LS RX <NUM>, all locally in PHY transceiver <NUM>) incurs only modest computational complexity, since the cancellation is performed at the LS bit rate. Echo cancellation in the opposite direction, i.e., cancellation of echoes of the LS signal in the HS RX, is considerably more complex to implement. Therefore, it is highly desirable to use precoding in the LS transmission.

In the example of <FIG>, PHY transceiver <NUM> comprises a HS TX <NUM> and a LS RX <NUM>. As in the configuration of <FIG>, the HS bit rate may be <NUM> bits per second (10Gbps), and the LS bit rate may be 100Mbps or 10Mbps.

As seen, HS TX <NUM> of PHY transceiver <NUM> comprises a TX driver <NUM>, but no precoder. TX driver <NUM> therefore transmits the "HS DATA IN" bit stream directly over link <NUM>, without precoding. The HS RX in the peer PHY transceiver (not shown in the figure) does not perform decoding of the received HS DATA IN bit stream.

LS RX <NUM> of PHY transceiver <NUM> is similar to LS RX <NUM> (<FIG>), with the addition of echo cancellation circuitry that is configured to cancel echoes of the HS signal that interfere with reception of the LS signal. Similarly to LS RX <NUM> of <FIG>, LS RX <NUM> receives a precoded LS signal, and applies decoding using LS decoder <NUM>.

In an embodiment, the echo cancellation circuitry in LS RX <NUM> comprises a LPF/decimation filter <NUM>, an echo cancellation filter <NUM> and an adder <NUM>. LPF/decimation filter <NUM> receives a replica of the "HS DATA IN" bit stream from HS TX <NUM> and performs two functions - (i) low-pass filtering the bit stream, and (ii) reducing the rate of the bit stream from the HS bit rate to the LS bit rate. Echo cancellation filter <NUM> adjusts the gain and phase of the decimated HS signal, so as to match the gain and phase of the echo of the HS signal at the output of ADC <NUM>. Adder <NUM> subtracts the output of filter <NUM> from the output of ADC <NUM>, thereby canceling the echo. The signal provided to equalizer <NUM> therefore has a reduced level of echo from the HS signal.

In some embodiments, it is sufficient to implement echo cancellation filter <NUM> with a relatively small number of taps (coefficients), e.g., on the order of sixteen taps, to cancel echoes of the HS signal. The small number of taps also simplifies the coefficient calculation process. For example, for a LS rate of 100Mbps, two-level pulse-amplitude modulation (PAM2), and a <NUM>-meter long twisted-pair link, as would be suitable for use in a typical automotive network, a <NUM>-tap filter was shown to be sufficient.

The configurations of PHY transceivers <NUM>, <NUM> and <NUM> and their components, such the internal structures of the various LS TXs, LS RXs, HS TXs and HS RXs, as shown in <FIG>, <FIG> and <FIG>, are example configurations that are depicted solely for the sake of clarity. In alternative embodiments, any other suitable configurations can be used. For example, the (<NUM>+D) and (<NUM>-D) precoding schemes described above have been chosen purely by way of example. Alternatively, any other suitable precoding schemes can be used. Generally, the precoding operation can be implemented by summing two or more mutually-delayed replicas of the input data stream. The term "mutually-delayed" does not necessarily mean that all of the replicas are delayed; in each of the (<NUM>+D) and (<NUM>-D) schemes, for example, one replica is delayed and the other replica is not.

The different elements of PHY transceivers <NUM>, <NUM> and <NUM> and their components may be implemented using dedicated hardware or firmware, such as using hardwired or programmable logic, e.g., in an Application-Specific Integrated Circuit (ASIC) or Field-Programmable Gate Array (FPGA). Additionally or alternatively, some functions of PHY transceivers <NUM>, <NUM> and <NUM>, e.g., functions of LS precoder <NUM>, LS decoder <NUM>, HS precoder <NUM> and/or HS decoder <NUM>, may be implemented in software and/or using a combination of hardware and software elements. Elements that are not mandatory for understanding of the disclosed techniques have been omitted from the figure for the sake of clarity. For example, each PHY transceiver typically comprises a Media Dependent Interface (MDI) for coupling the transmitter and receiver to link <NUM>.

Claim 1:
An Ethernet physical layer, PHY, transceiver (<NUM>), comprising:
a transmitter (<NUM>), configured to generate and transmit a first signal carrying a first data stream over an asymmetric full-duplex wired channel (<NUM>) to a peer Ethernet PHY transceiver (<NUM>);
a receiver (<NUM>), configured to receive a second signal carrying a second data stream from the peer Ethernet PHY transceiver (<NUM>) over the asymmetric full-duplex wired channel (<NUM>), the second signal containing an echo component from the first signal, and to decode the received second data stream ; and
a precoder (<NUM>), which is configured, in generating the first signal for transmission, to apply precoding to the first data stream, the precoding reducing the echo component from the first signal in the second data stream decoded by the receiver (<NUM>).