Patent Description:
Advances in microfabrication techniques has allowed a continued scaling of important device parameters of integrated circuits such as line pitch, transistor gate length and contacted poly pitch (CPP), thus enabling circuits with improved device performance and area efficiency.

The self-aligned contact (SAC) process enables CPP scaling as well as an improved overlay (OVL) process window in horizontal channel transistor device fabrication, such as FinFET and nanosheet-FET (NSHFET) device fabrication. A typical conventional SAC process comprises etching source/drain contact openings in an interlayer dielectric, self-aligned to a gate hard mask and gate sidewall spacer. A challenge with the SAC process is however that the etching, while selective to the interlayer dielectric, still may attack the gate hard mask and sidewall spacer, in particular during etching of contact openings with high aspect ratio. Additional challenges include the risk of attack on the epitaxial source/drain bodies and the gate spacer during opening of the contact etch stop layer (CESL) which typically is formed on the source/drain bodies prior to the interlayer dielectric deposition.

<CIT> discloses a related method in which the source/drain interconnects are initially formed as a continuous layer that is later etched to define discrete structures.

<CIT> discloses a method of fabricating a semiconductor device having a buried buried conductive wiring. The buried conductive wiring and the source/drain regions are contact by filling a contact structure into a via hole in an interlayer insulation layer.

In light of the above, it is an objective to provide a method for forming source/drain contacts which overcome or at least mitigate one or more of the afore-mentioned challenges. Further and alternative objectives may be understood from the following.

According to an aspect there is provided a method for forming a semiconductor device according to claim <NUM>.

The present method hence enables self-aligned source/drain contact formation by a direct etching of a metal layer formed over the source/drain bodies. Compared to the mask used for etching the contact trenches in the conventional SAC process, the etching of the metal layer may employ a mask with a reversed or inverse tone.

Typical metals suitable for source/drain contacts (e.g. Ru or Mo) may provide an advantageous etch contrast with respect to both oxide- and nitride-based hard mask and gate spacers.

Additionally, the source/drain bodies may be reliably masked during the etching of the metal layer and the need for a CESL on the source/drain bodies, like in the conventional SAC process, is be obviated. The absence of a CESL additionally allows the source/drain contacts to be formed closer to the channel and with an increased width dimension, to the benefit of the electrical perfermance of the device.

The method is also more robust against loss of gate hard mask and gate spacer, since the cut area (tip to tip area) will be filled with interlayer dielectric (and not metal), which counteracts gate-to-contact shorting.

The term "fin structure" as used herein refers to a fin-shaped structure with a longitudinal dimension oriented in a horizontal direction (e.g. a "first" horizontal direction) along the substrate and protruding vertically therefrom.

Each channel region may comprise at least one channel layer or channel layer portion. Each channel region may comprise a single channel layer integrally formed with the fin structure (wherein the fin structure may be a single fin-shaped semiconductor body). The fin structure may however also comprise one or more horizontally oriented channel layers stacked over a base portion of the fin structure protruding from the substrate.

Relative spatial terms such as "vertical", "upper", "lower", "top", "bottom", "above", "under", "below", are herein to be understood as denoting locations or orientations within a frame of reference of the substrate. In particular, the terms may be understood as locations or orientations along a normal direction to the substrate (i.e. a main plane of extension of the substrate). Correspondingly, terms such as "lateral" and "horizontal" are to be understood as locations or orientations parallel to the substrate (i.e. parallel to the main plane of extension of the substrate).

In some embodiments, forming the metal layer may comprise depositing metal over the device structure to cover and surround the gate structure and the source/drain bodies, and recessing the deposited metal to expose an upper surface of the gate structure.

By the term "recessing" is hereby meant a process adapted to reduce a thickness of the layer or feature being recessed, e.g. the deposited metal. Recessing may comprise polishing and/or etch back (e.g. of the deposited metal). Polishing may comprise chemical mechanical polishing (CMP).

The metal layer may comprise a metal liner sub-layer and a metal fill sub-layer over (e.g. on) the metal liner sub-layer.

In some embodiments, the method may further comprise:.

Source/drain contacts may hence be provided with a desired height and be capped and hence masked prior to subsequent device processing steps.

In some embodiments, the gate structure may comprise a sacrificial gate and the method may further comprise, subsequent to forming the interlayer dielectric, removing the sacrificial gate to form a gate trench and forming a replacement metal gate in the gate trench.

The process steps for the source/drain contact formation may hence be supplemented with replacement metal gate (RMG) processing.

According to the invention, the device structure further comprises a buried wiring line formed in a trench extending alongside the fin structure and capped by an insulating wiring capping layer, wherein the method further comprises: forming a via hole in the wiring capping layer to expose an upper surface of the buried wiring line, and subsequently forming the metal layer, wherein the metal layer fills the via hole and wherein the metal layer is etched such that a first one of the source/drain contacts is formed in contact with the buried wiring line and one of the source/drain bodies.

The direct-metal etch approach of the method is hence applied for interconnecting a buried wiring line and a source/drain body.

Buried wiring lines is a device interconnect which may be used in advanced technology nodes for improved area and power efficiency. A buried wiring line may be formed in a trench in the substrate, such that the wiring line may be located at a level below the active physical devices. Burying wiring lines enables the cross-section of the wiring lines to be increased (for example reducing the line resistance) without occupying valuable space in the back-end-of-line interconnect structure. Additionally, buried wiring lines may facilitate design of reduced track height standard cells by allowing neighbouring circuit cells to share a common (e.g. increased cross-section) buried wiring line. A buried wiring line and a source/drain body of an adjacent horizontal channel transistor (e.g. a finFET, or a nanosheet- or nanowire-FET) may be interconnected by forming a via-like metal contact extending from the source/drain body and landing on the buried wiring line. One example of a buried wiring line is the buried power rail (BPR). In the case of a BPR, this interconnect is also known as a via-to-BPR (VBPR). The method is however applicable to also other types of buried wiring lines.

Forming a VBPR typically involves etching of a high aspect ratio through interlayer dielectric, liner layers and/or capping layers within narrow contact trenches between gates, with entailing challenges during metal filling. The further aggressive scaling and drive towards high aspect ratio device structures make these issues increasingly challenging.

In contrast, by applying the present direct-metal etch approach to form a source/drain contact in contact with the buried wiring line (e.g. BPR) and one of the source/drain bodies (the first), these challenges may be mitigated. Firstly, a thickness of dielectric material which needs to be opened to expose the buried wiring line may be limited to the thickness of the insulating wiring capping layer, which is sufficiently less than the combined thickness of the interlayer dielectrics, liner layers and capping layers of the conventional approach. Secondly, as a CESL on the source/drain bodies may be omitted, a greater contact interface, and thus lower resistance, between the buried wiring line and the source/drain body is enabled.

In some embodiments, forming the via hole may comprise:.

Using a temporary process layer to form the via hole may facilitate the via hole formation since the material of the temporary process layer may be selected with regard to its etching and masking properties and with less regard to its suitability as a layer in the final device, e.g. its insulating properties. The temporary process layer may in particular be formed on (in direct contact with) the insulating capping layer and the source/drain bodies.

In some embodiments, the via opening may be formed to be displaced (horizontally) relative the first source/drain body such that the first source/drain body is separated from the via opening by a remaining portion of the temporary process layer.

The temporary process layer may be an organic material layer, such as an organic planarizing layer (e.g. an organic spin-on-layer). An organic / carbon-based material may be etched with a high selectivity to interlayer dielectrics typically used for capping buried wiring lines, and materials used for gate spacers and gate (hardmask) caps.

In some embodiments the device structure comprises a plurality of parallel fin structures, each fin structure comprising a number of pairs of source/drain bodies and a channel region between each pair of source/drain bodies, the device structure further comprising a plurality of parallel gate structures spaced apart by gaps and extending transverse to and across the fin structures such that each channel region is overlapped by a respective one of the gate structures;
wherein the metal layer is formed to fill the gaps between the gate structures and subsequently etched to define source/drain contacts on the source/drain bodies in each gap.

A plurality of source/drain contacts may hence be formed in parallel by directly etching the metal layer in the gaps between the gate structures.

Forming the metal layer may comprise depositing metal over the device structure to completely fill the gaps between the gate structures, and recessing the deposited metal to expose an upper surface of the gate structure.

The above, as well as additional objects, features and advantages, may be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings.

Hereinafter follows a detailed description of embodiments of a method for forming a semiconductor device, more specifically for forming source/drain contacts on source/drain bodies of a FET transistor device. The FET transistor device may comprise at least one horizontally oriented channel layer. Examples of applicable FET devices include the finFET device (e.g. wherein each channel region comprises a single fin-shaped channel layer) and the horizontal/lateral nanowire- or nanosheet-channel FET device (e.g. wherein each channel region comprises a number of vertically stacked nanowires or nanosheets).

By means of introduction, a brief description of a SAC process will first be provided with reference to <FIG> as a comparative example.

<FIG> schematically depicts a top-down view of a device structure <NUM> after forming source/drain bodies <NUM> on semiconductor fins and depositing a CESL <NUM>. Gate structures comprising a gate body <NUM> and a gate spacer <NUM> extend across the semiconductor fins. While <FIG> schematically shows the CESL <NUM> only along the gate structures, it is to be noted the CESL <NUM> may cover also the source/drain bodies <NUM>. In <FIG>, an ILD <NUM> has been deposited and planarized, e.g. by chemical mechanical polishing (CMP), to bring the ILD surface planar with an upper surface of the gate structures (e.g. an upper surface of a gate cap/hardmask). In case the gate bodies <NUM> are sacrificial, RMG processing may then be performed to replace the sacrificial gate bodies with functional gate stacks <NUM>'. In <FIG>, source/drain contact trenches <NUM> have subsequently been patterned in the ILD <NUM>, over the source/drain bodies <NUM>. In <FIG>, the trenches <NUM> have been filled with metal (comprising e.g. metal liner <NUM> and metal fill <NUM>) which then may be subjected to CMP to complete the source/drain contacts <NUM> (inset D).

<FIG> further shows the corresponding SAC process in combination with VBPR formation. <FIG> schematically depicts a cross-section of the device structure <NUM> extending through a source/drain body <NUM> formed on a pair of fin structures <NUM> protruding from a substrate <NUM>. The device structure <NUM> comprises a BPR <NUM> (or more generally a buried wiring line) capped by an insulating capping layer <NUM>. The capping layer <NUM> and the source/drain body <NUM> have been covered by CESL <NUM> and ILD <NUM>. A source/drain contact opening <NUM> has been formed in the ILD <NUM> to expose a portion of the CESL <NUM> on the source/drain body <NUM>, thus corresponding to the stage of the process depicted in <FIG>.

In <FIG>, the device structure <NUM> has been covered by a mask layer <NUM> (e.g. a photo resist or a lithographic layer stack for instance of spin-on glass and spin-on-carbon) and a via opening <NUM> has been patterned in the mask layer <NUM> and subsequently transferred into the capping layer <NUM>, e.g. stopping on the CESL <NUM>. In <FIG>, the mask layer <NUM> has been removed and the CESL <NUM> has been opened to expose a portion of the BPR <NUM> and the source/drain body <NUM> in the source/drain contact opening <NUM>. In <FIG> the contact opening <NUM> has been filled with contact metal (e.g. metal liner <NUM> and metal fill <NUM> like in <FIG>) to form the source/drain contact <NUM> and a VBPR interconnecting the source/drain body <NUM> and the BPR <NUM>.

A method for forming a semiconductor device comprising a direct metal etch approach will now be disclosed with reference to <FIG>, each schematically depicting a top-down view of a device structure <NUM> at various stages of the method.

With reference to <FIG>, the device structure <NUM> is formed on a substrate <NUM>. The X- and Y-directions indicated in the figures designate first and second horizontal directions, mutually perpendicular to each other and parallel to a main plane of the substrate <NUM>.

The substrate <NUM> may be a conventional semiconductor substrate suitable for CMOS processing. The substrate <NUM> may be a single-layered semiconductor substrate, for instance formed by a bulk substrate such as a Si substrate, a germanium (Ge) substrate or a silicon-germanium (SiGe) substrate. A multi-layered / composite substrate is however also possible, such as an epitaxially grown semiconductor layer on a bulk substrate, or a semiconductor-on-insulator (SOI) substrate, such as a Si-on-insulator substrate, a Ge-on-insulator substrate, or a SiGe-on-insulator substrate.

The device structure <NUM> comprises a number of fin structures <NUM> extending in parallel in the X-direction. Pairs of source/drain bodies <NUM> (i.e. source/drain regions) have been formed on the fin structures <NUM>, on either side of respective channel regions <NUM>. The device structure <NUM> further comprises gate structures <NUM> extending in the Y-direction across a respective channel region <NUM>.

The fin structures <NUM> may be formed e.g. by etching trenches in a semiconductor layer of a channel material (e.g. for forming a finFET device), or in a semiconductor layer stack of sacrificial layers of a sacrificial material and channel layers of a channel material, arranged alternatingly with each other (e.g. for forming a nanowire- or nanosheet-channel FET device). After forming the fin structures <NUM>, the fin structures <NUM> may be surrounded by shallow-trench isolation (STI), e.g. by filling the trenches with insulating material (e.g. an ILD such as SiO<NUM>) and etching back the same to a desired height. Techniques for fin patterning and STI formation are per se well known in the art and will hence not be further discussed herein.

The gate structures <NUM> may be sacrificial gate structures <NUM> and may comprise a sacrificial gate or sacrificial gate body formed by depositing a sacrificial gate layer, e.g. of a-Si, and then patterning the sacrificial gate body therein using single- or multiple-patterning techniques, as per se is known in the art. Each gate structure <NUM> may further be provided with a gate spacer <NUM> (e.g. an conformally deposited nitride such as SiN deposited by atomic layer deposition, ALD) formed to extend along sidewalls of each sacrificial gate body, and further a gate cap (e.g. of a hard mask material) on top of the sacrificial gate body. Further details of forming sacrificial gate structures is per se well known in the art and will hence not be further discussed herein.

The source/drain bodies <NUM> may be formed by epitaxy at either side of each gate structure <NUM> and channel region <NUM>. The source/drain bodies <NUM> may be doped in accordance with the intended conductivity type of the FET devices to be formed, e.g. using in-situ doping techniques. Each source/drain body <NUM> may be formed on, i.e. in contact with, the one or more channel layer of a respective fin structure <NUM>. While not shown in <FIG>, source/drain bodies <NUM> on neighboring pairs of fin structures <NUM> may be formed to merge to form common source/drain bodies.

Prior to the epitaxy, the fin structures <NUM> may be recessed by etching back the fin structures <NUM> in a top-down direction (e.g. negative Z) at either side of each sacrificial gate structure, while using the sacrificial gate structure <NUM> (e.g. with the gate spacer <NUM> thereon) as an etch mask. Each fin structure <NUM> may thereby be partitioned into a plurality of fin structure portions, each comprising a channel region <NUM> comprising one or more channel layer portions preserved in the channel region underneath each sacrificial gate structure <NUM>. The etch back may thus define end surfaces of the (respective) channel layer(s) at either side of each sacrificial gate structure <NUM> on which the source/drain bodies <NUM> may be grown. As per se is known in the art, fin recess and source/drain epitaxy may be performed separately for n-type and p-type devices using an additional lithographic mask.

In <FIG>, a metal layer <NUM> has been formed over the source/drain bodies/regions <NUM> by depositing one or more metals over the device structure <NUM> to cover and surround the gate structures <NUM> and the source/drain bodies <NUM>. The metal layer may comprise a stack of a metal liner sub-layer (e.g. TiN) and a metal fill sub-layer on the metal liner sub-layer (e.g. W, Al, Ru, Mo or Co) respectively deposited using e.g. ALD, CVD or physical vapor deposition (PVD). The deposition of metal layer may be preceded by forming a contact silicide on the source/drain bodies <NUM>. Silicide formation may be done using conventional techniques, e.g. by depositing a suitable metal (such as TiN) followed by anneal to trigger silicidation. After anneal, non-silicided metal may be removed by a metal etch (e.g. isotropic, wet or dry).

In <FIG>, the metal layer <NUM> has been recessed (e.g. CMP and/or etched back top-down) to expose an upper surface of the gate structures <NUM> (e.g. of the gate cap) and subsequently etched to define respective source/drain contacts <NUM> on the source/drain bodies <NUM>. Each source/drain contact <NUM> may as shown comprise a remaining portion of metal liner (sub-layer) <NUM> and metal fill (sub-layer) <NUM>. The source/drain contacts <NUM> may be formed in a lithography-and-etching process, e.g. comprising forming a lithographic layer stack comprising a resist layer, lithographically defining a contact pattern in the resist layer, and transferring the contact pattern into lower layers of the lithographic layer stack, e.g. comprising a hard mask and optionally further an organic planarizing layer (e.g. spin-on-carbon) and a spin-on-glass layer. The contact pattern may subsequently be transferred into the metal layer <NUM> to define the source/drain contacts <NUM>. Any suitable conventional combination of etching processes (e.g. wet and/or dry) and etching chemistries may be used to etch the metal layer <NUM>. For example, Ru can be etched using O<NUM>/Cl<NUM>, W can be etched using Cl<NUM> or SF<NUM>/CF<NUM>, Mo can be etched using O<NUM>/Cl<NUM> or SF<NUM>/CF<NUM>, Al can be etched using Cl<NUM>/BCl<NUM>, and TiN can be etched using Cl<NUM> or SF<NUM>.

In <FIG>, an ILD layer <NUM> has been deposited over the gate structures <NUM> and the source/drain contacts <NUM>, thus embedding the same.

The ILD layer <NUM> may be formed by a layer of insulating material such as an oxide (e.g. SiO<NUM> deposited by CVD), but may also be a composite layer structure of two or more insulating layers of different materials such as a dielectric liner (e.g. a nitride such as SiN) followed by a layer of oxide (e.g. SiO<NUM>). The ILD layer <NUM> may further be subjected to CMP to planarize an upper surface of the ILD layer <NUM> and expose an upper surface of the source/drain contacts <NUM> and the gate structures <NUM>.

The source/drain contact formation is then completed and the method may proceed with further processing steps for completing the device structure <NUM>. For example, the method may further comprise etching back the source/drain contacts <NUM> to form recessed source/drain contacts, and forming an insulating contact capping layer on the recessed source/drain contacts <NUM>. The source/drain contacts <NUM> may thus be capped with insulating material (e.g. an oxide such as SiO<NUM> or a nitride such as SiN). The insulating material may be deposited and then planarized, e.g. by CMP.

Additionally, an RMG process may be performed to replace sacrificial gate structures <NUM> with functional gate stacks in each channel region <NUM>.

An RMG process may proceed in accordance with a conventional flow, comprising removing the sacrificial gate structures <NUM> (e.g. the gate cap and the sacrificial gate body) by etching, thereby forming gate trenches in the ILD layer <NUM>, extending across and exposing the fin structures <NUM> in the respective channel regions <NUM>. A functional gate stack may then be deposited in the gate trenches, to overlap the respective channel regions. A gate stack may comprise a gate dielectric layer and a gate metal stack comprising one or more effective a work function metal (WFM) layers and a gate fill metal. The gate dielectric layer may be formed of a conventional a high-k dielectric e.g. HfO<NUM>, HfSiO, LaO, AlO or ZrO. The WFM layer may be formed of one or more effective WFMs (e.g. an n-type WFM such as TiAl or TiAlC and/or a p-type WFM such as TiN or TaN). The gate fill metal may be formed of conventional gate fill metals e.g. W, Al, Co or Ru. The gate dielectric layer and the first WFM may be deposited by ALD. The gate fill metal may for instance be deposited by CVD or PVD. The gate stack may after deposition be recessed using a metal etch-back process to provide the functional gate stacks with a desired vertical dimension and then be covered by a gate cap, e.g. of a nitride such as SiN. The RMG process may be performed at a reduced thermal budget, e.g. <NUM> or below, to limit degradation of the (semiconductor) source/drain body-(metal) contact interface.

As will be appreciated by a skilled person, an overall method for forming a FET device may include additional process steps in dependence on particular type of device that is to be formed. For instance, a method for forming a horizontal/lateral nanowire- or nanosheet-channel FET device (e.g. comprising a number of vertically stacked nanowires or nanosheets) with a wrap-around gate or gate-all-around may additionally comprise a "channel release process". In a channel release process, sacrificial layers arranged alternatingly with channel layers of each fin structure <NUM> may be removed in the channel regions <NUM> by etching, within the gate trenches, the sacrificial material selectively to the channel material. Thereby the channel layers may be "released", such that the functional gate stack may be subsequently deposited in each gate trench to surround the channel layers.

Furthermore, to facilitate among the "channel release", process steps may be performed for forming so-called "inner spacers" on end surfaces of the sacrificial layers, after fin recess and prior to source/drain body epitaxy. Inner spacer formation generally comprises, as per se is known in the art, laterally recessing (i.e. etching back along the +X and -X directions) the sacrificial layers from both sides of each sacrificial gate structure <NUM> using an isotropic etching process selective to the sacrificial material, and filling the recesses with an inner spacer material (e.g. an ALD-deposited oxide, nitride or carbide). Spacer material deposited outside the recesses may be removed by a subsequent etch step. The inner spacers may thus, among others, act as an etch mask for the source/drain bodies <NUM> during the channel release.

A method using the direct metal etch approach shown in <FIG> to form a source/drain contact <NUM>' interconnected with a BPR <NUM> will now be disclosed with reference to <FIG> and <FIG>. While the illustrated embodiment refers to a buried wiring line in the form of a BPR, it is to noted that the method is applicable to also other types of buried wiring lines, such as buried interconnect lines, buried routing lines, or buried inter-cell signal lines for memory or logic applications.

<FIG> each schematically depict a cross-section of a device structure <NUM>'. <FIG> is a top-down view of the device structure <NUM>' shown in <FIG> wherein some elements of <FIG> have been omitted for illustrational clarity (e.g. wiring capping layer <NUM> and process layer <NUM>). The device structure <NUM>' corresponds to the device structure <NUM> and like references signs refer to like elements and a discussion of those elements will hence not be repeated. The X- and Y-directions indicated in the figures correspond to the X- an Y-directions indicated in <FIG>. The Z-direction indicates a vertical direction, normal to a main plane of extension of the substrate <NUM>. The cross-sections are hence parallel to the YZ-plane, and accordingly extend across and transverse to the fin structures <NUM>, e.g. along line A-A'.

The BPR <NUM> is as shown formed in a trench extending alongside a fin structure <NUM> in the X-direction. The BPR <NUM> may be formed by etching the trench through STI <NUM> (e.g. an oxide such as SiO<NUM>, or another low-k interlayer dielectric material, surrounding a lower portion of the fins <NUM>) and into the substrate <NUM>. The BPR <NUM> may then be formed in the trench by filling the trench with one or more metals (e.g. a barrier metal and a fill metal) and thereafter etching back the metal to form the BPR <NUM> with a desired height (along the Z-direction) in the trench. The BPR <NUM> may then be capped by an insulating wiring capping layer <NUM> (or insulating layer structure) comprising one or more insulating layers, for instance a nitride liner (e.g. SiN) and an interlayer dielectric (e.g. SiO<NUM>). While in the illustrated embodiment, the BPR <NUM> is formed with a height such that the BPR <NUM> protrudes into a lower thickness portion of the STI <NUM>, this is merely an example and it is also possible to form the BPR <NUM> with a smaller height such that the BPR <NUM> is embedded only within a thickness portion of the substrate <NUM>.

In the following, reference will mainly be made to a single source/drain body <NUM>, source/drain contact <NUM>' and BPR <NUM>. The following description is however applicable to forming any number of source/drain contacts interconnected with a BPR. For example, additional BPRs may be formed in parallel to the BPR <NUM> , alongside another fin structure of the device structure <NUM>'.

As further shown in <FIG>, a temporary process layer <NUM> has been formed over the source/drain body <NUM> and the wiring capping layer <NUM>. The temporary process layer <NUM> may more specifically cover the source/drain bodies <NUM> of the device structure <NUM>', and completely fill the gaps between the gate structures <NUM> (visible in <FIG>). The temporary process layer <NUM> may be an organic material layer such as an organic planarizing layer deposited by CVD or by spin-on-deposition (e.g. a spin-on-carbon layer). More generally, the temporary process layer <NUM> may however be formed by any material facilitating the patterning process to be described below and presenting a sufficient etch contrast with respect to the materials of the wiring capping layer <NUM>.

A via opening <NUM> has been etched in the process layer <NUM>. The via opening <NUM> may be formed in a lithography-and-etching process, e.g. comprising lithographically defining a via opening pattern in a resist layer of a lithographic layer stack (omitted from the figures for illustrational clarity) formed over the process layer <NUM>, and transferring the pattern into the process layer <NUM> to form the via opening <NUM>. The lithographic layer stack may be of a conventional type and comprise a hard mask and a spin-on-glass layer between the resist layer and the process layer <NUM>.

In <FIG> the via opening <NUM> (i.e. pattern of via openings) in the process layer <NUM> has been subsequently transferred into the wiring capping layer <NUM> by etching, thereby forming a via hole <NUM>. The etching may be stopped on the upper surface of the BPR <NUM>. The via opening <NUM> and the via hole <NUM> may be formed using an anisotropic etching process, for instance a dry etching process such as reactive ion etching (RIE). As may be appreciated, the etching process may comprise a sequence of etch steps with different etching chemistries suitable for etching the different materials of e.g. the temporary process layer <NUM> and the wiring capping layer <NUM> (e.g. oxide and/or nitride materials). After forming the via opening <NUM> the temporary process layer <NUM> may be removed, e.g. using a suitable etching chemistry.

In <FIG> a metal layer <NUM> has been formed over the source/drain body <NUM> by depositing one or more metals (e.g. a stack of a metal liner sub-layer and a metal fill sub-layer on the metal liner sub-layer) over the device structure <NUM>' to cover and surround the gate structures (e.g. corresponding to the gate structures <NUM> in <FIG>) and the source/drain body <NUM>. The metal layer <NUM> additionally fills the via hole <NUM> and is thus formed in contact with the upper surface of the BPR <NUM>. Reference is made to the above discussion of the metal layer <NUM> in conjunction with <FIG>. As discussed in connection with <FIG>, the metal layer <NUM> may further be recessed (e.g. by CMP and/or etched back top-down) to expose an upper surface of the gate structures <NUM> (e.g. of the gate cap).

In <FIG> a mask layer has been formed over the metal layer <NUM> and patterned to define a contact pattern mask <NUM>. In <FIG>, the metal layer <NUM> has subsequently been etched while using the contact pattern mask <NUM> as an etch mask to form a source/drain contact <NUM>'. The mask layer and contact pattern mask may be provided in the form of a lithographic layer stack with a composition as discussed above in connection with <FIG>. In contrast to the unclaimed example in <FIG>, however, the metal layer <NUM> is (as shown in <FIG>) etched such that the source/drain contact <NUM>' is formed in contact with both the BPR <NUM> and the source/drain body <NUM>. The source/drain contact <NUM>' thus extends from the source/drain body <NUM> (along the Y-direction) to overlap a position of the BPR <NUM>. The source/drain contact <NUM>' accordingly comprises a VBPR portion 118a' (i.e. a via portion) formed in the via hole <NUM> and interconnecting the source/drain body <NUM> and the BPR <NUM>. The interconnection is enabled by patterning the mask layer such that the contact pattern mask <NUM> (i.e. a continuous pattern portion thereof) overlaps the source/drain body <NUM> and the via hole <NUM>. As may be appreciated, a corresponding via hole <NUM> and a corresponding source/drain contact comprising a VBPR portion may be formed at each position of the device structure <NUM>' where a connection between a source/drain body and a BPR is desired. Additionally, a combination of source/drain contacts <NUM> like in <FIG> (i.e. not comprising any VBPR portion) and source/drain contacts <NUM>' like in <FIG> (i.e. comprising a VBPR portion 118a') may be patterned simultaneously in the metal layer <NUM>.

In <FIG>, an ILD layer <NUM> has been deposited over the source/drain contact(s) <NUM>' (and any further source/drain contacts) to embed the same. The ILD layer <NUM> may further be subjected to CMP to planarize an upper surface of the ILD layer <NUM> and expose an upper surface of the source/drain contact(s) <NUM>' and gate structures. Reference is made to the above discussion of the ILD layer <NUM> in conjunction with <FIG>. As indicated by the dashed horizontal line in <FIG>, the method may further comprise etching back the source/drain contact <NUM>' in a top-down direction to form a recessed source/drain contact <NUM>' which may be capped by an insulating contact capping layer <NUM> (e.g. formed by depositing and then planarizing an oxide such as SiO<NUM> or a nitride such as SiN).

Claim 1:
A method for forming a semiconductor device (<NUM>'),
the method comprising:
forming a device structure on a substrate (<NUM>), the device structure
comprising a fin structure comprising a pair of source/drain bodies (<NUM>) and a channel region between the pair of source/drain bodies, the channel region comprising at least one channel layer, and the device structure further comprising a gate structure extending across the channel region of the fin structure, wherein the device structure further comprises a buried wiring line (<NUM>)
formed in a trench extending alongside the fin structure and capped by an insulating wiring capping layer (<NUM>);
forming a metal layer (<NUM>) over the source/drain bodies; etching the metal layer to define respective source/drain contacts (<NUM>') on
the source/drain bodies; and
depositing an interlayer dielectric layer (<NUM>) over the gate structure and the source/drain contacts,
wherein the method further comprises forming a via hole (<NUM>) in the wiring
capping layer to expose an upper surface of the buried wiring line, and subsequently forming the metal layer, wherein the metal layer fills the via hole and wherein the metal layer is etched such that a first one of the source/drain contacts is formed in contact with the buried wiring line and one of the source/drain bodies.