Patent Description:
Conventional laser driver circuits may provide signals (e.g., specific currents and/or voltages) to a laser light-emitting device (e.g., a laser diode). In turn, the laser light-emitting device may emit constant or pulsed laser light. However, operating conventional laser driver circuits with short pulse lengths and/or at high frequency or repetition rates may produce ringing, instability, or other unwanted effects.

For example, in a conventional laser pulser circuit, ringing may be a result of an LC tank formed by a parasitic inductance, a fixed capacitor, and a parasitic capacitance of the switching field effect transistor. Increasing the value of the fixed capacitor may reduce the ringing, but pulse recovery may also be slower. Japanese patent publication <CIT> presents a drive circuit for a semiconductor laser. "<NPL>, presents a high-current, nanosecond-pulse generator which utilizes step recovery diodes.

The present disclosure generally relates to laser systems and laser driver circuits configured to provide pulses of laser light. The invention is defined in the claims.

In a first aspect, a system is provided. The system includes a trigger source, a laser diode, a first field effect transistor, and a second field effect transistor. The laser diode is coupled to a supply voltage and a drain terminal of the first field effect transistor. A source terminal of the first field effect transistor is coupled to ground. A gate terminal of the first field effect transistor is coupled to the trigger source. A drain terminal of the second field effect transistor is coupled to the supply voltage. A source terminal of the second field effect transistor and a gate terminal of the second field effect transistor are coupled to ground.

Other aspects, embodiments, and implementations will become apparent to those of ordinary skill in the art by reading the following detailed description, with reference where appropriate to the accompanying drawings.

Example methods, devices, and systems are described herein. It should be understood that the words "example" and "exemplary" are used herein to mean "serving as an example, instance, or illustration. " Any embodiment or feature described herein as being an "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or features. Other embodiments can be utilized, and other changes can be made, without departing from the scope of the subject matter presented herein as long as they fall under the scope of protection as defined by the appended claims.

Thus, the example embodiments described herein are not meant to be limiting. Aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are contemplated herein as long as they fall under the scope of protection as defined by the appended claims.

Further, unless context suggests otherwise, the features illustrated in each of the figures may be used in combination with one another as long as they fall under the scope of protection as defined by the appended claims.

A laser pulser circuit may include a laser diode coupled to a supply voltage and a drain terminal of a first field effect transistor (FET). The source terminal of the first FET is coupled to ground. A gate terminal of the first FET may be coupled to a waveform generator or another type of trigger source. The laser pulser circuit may also include a second FET whose drain terminal is connected to the supply voltage and whose source terminal and gate terminal is connected to the ground.

In an example embodiment, the laser diode may be configured to provide laser light over very short pulse lengths, e.g., <NUM> nanoseconds. In some embodiments, the first and second FETs may include GaN (e.g., GaNFET) or SiC (e.g., SiCFET). Other types of high-voltage (<NUM>+ volts) fast-switching transistors are contemplated. For example, the FETs may be configured for use in microwave applications. In some embodiments, the FETs may be flip-chip or surface-mount devices.

The second FET reduces oscillations (e.g., ringing) that may occur at such short pulse lengths due to parasitic inductance and capacitance in the laser pulser circuit. Furthermore, the second FET may reduce or eliminate the development of a negative voltage between supply voltage and ground common in other RLC circuit designs.

In an example embodiment, a body diode may be formed by a p-n junction that connects the source and drain terminals of the second FET. In other words, the body diode may act as a very fast parallel shunt diode, which may provide a path for reverse drain current (e.g., free-wheeling current) under some operating conditions of the laser pulser circuit. Furthermore, under some operating conditions, the second FET may act as a capacitor with capacitance that scales inversely with bias. For example, with a GaNFET, the capacitance of the transistor may be higher after a pulse compared to the capacitance while energy is being discharged through the laser diode.

<FIG> illustrates a schematic diagram of system <NUM>, according to an example embodiment. System <NUM> includes a trigger source <NUM>, a transistor arrangement <NUM>, a laser diode <NUM>, and a power supply <NUM>. In some embodiments, system <NUM> may include an optional controller <NUM>.

The trigger source <NUM> may include a waveform generator, a pulse signal generator, or another type of device configured to provide a trigger pulse or trigger signal.

The laser diode <NUM> is coupled to a supply voltage, which may be provided, at least in part, by the power supply <NUM>. In an example embodiment, the supply voltage may be greater than <NUM> volts. However, other values for the supply voltage are possible.

The transistor arrangement <NUM> includes a first FET <NUM> and a second FET <NUM>. In an example embodiment, the first FET <NUM> and the second FET <NUM> could be NMOS, enhancement-mode, surface mount transistors. In such a scenario, the laser diode <NUM> may be coupled to a drain terminal of the first FET <NUM>. A source terminal of the first FET <NUM> is coupled to a ground terminal. A gate terminal of the first FET <NUM> is coupled to the trigger source <NUM>.

A drain terminal of the second FET <NUM> is coupled to the supply voltage (e.g., power supply <NUM>). A source terminal of the second FET <NUM> and a gate terminal of the second FET <NUM> are coupled to ground.

The controller <NUM> may include at least one processor and a memory. In such a scenario, the at least one processor may execute instructions stored in the memory so as to carry out various operations described herein. As an example, the controller <NUM> may cause system <NUM> to produce laser light via one or more laser pulses.

In an example embodiment, the controller <NUM> may cause the trigger source <NUM> to provide a trigger pulse signal so as to cause the laser diode <NUM> to emit a laser pulse. That is, the controller <NUM> may be configured to trigger, adjust, and/or control the emission of laser light from the laser diode <NUM>.

In some embodiments, the laser pulse or pulses may include a pulse width of less than <NUM> nanoseconds. However, other pulse widths are possible and contemplated herein.

In an example embodiment, the first FET <NUM> and the second FET <NUM> may include gallium nitride (GaN). That is, in such examples, the first FET <NUM> and the second FET <NUM> may be GaNFET devices.

Additionally or alternatively, the first FET <NUM> and the second FET <NUM> may include silicon carbide (SiC). That is, the first FET <NUM> and the second FET <NUM> could be SiCFET devices.

Yet further, the first FET <NUM> and/or the second FET <NUM> may include a high electron mobility transistor (HEMT).

The first FET <NUM> and/or the second FET <NUM> could be in the form of a surface-mount device. However, other form factors for the first FET <NUM> and/or the second FET <NUM> are contemplated.

The second FET <NUM> is configured to reduce oscillations in the system. In particular, the second FET <NUM> may be configured to reduce or eliminate a negative voltage between a drain terminal and a source terminal of the first FET <NUM>. In an example embodiment, under some operating conditions of the system <NUM>, the second FET <NUM> may include a body diode, which may be formed by a p-n junction that connects the drain and drain terminals of the second FET. As such, the body diode may act as a parallel shunt diode, which may provide a path for reverse drain current (e.g., free-wheeling current). As described elsewhere herein, the second FET acts as a capacitor having a capacitance that scales inversely with bias. For example, a GaNFET may include a capacitance that is higher after a pulse compared to the capacitance while energy is being discharged through the laser diode <NUM>.

In one embodiment, system <NUM> may include a return diode connected between the drain terminal of the first FET <NUM> and the supply voltage <NUM>.

It is to be understood that other arrangements of the elements of system <NUM> are possible and contemplated herein. Specifically, while embodiments herein may relate to enhancement-mode NMOS FETs, one of ordinary skill in the art would understand that many other variations of circuit <NUM> are possible to provide a fast switching capability and/or provide sub-<NUM> nanosecond laser light pulse widths. For example, the system <NUM> could be modified to accommodate the first FET <NUM> and/or the second FET <NUM> as being PMOS-type and/or depletion mode FETs. All such variations are contemplated within the scope of the present disclosure.

The controller <NUM> may include one or more processors <NUM> and a memory <NUM>. The one or more processors <NUM> may be a general-purpose processor or a special-purpose processor (e.g., digital signal processors, application specific integrated circuits, etc.). The one or more processors <NUM> may be configured to execute computer-readable program instructions that are stored in the memory <NUM>. As such, the one or more processors <NUM> may execute the program instructions to provide at least some of the functionality and operations described herein.

The memory <NUM> may include or take the form of one or more computer-readable storage media that may be read or accessed by the one or more processors <NUM>. The one or more computer-readable storage media can include volatile and/or non-volatile storage components, such as optical, magnetic, organic or other memory or disc storage, which may be integrated in whole or in part with at least one of the one or more processors <NUM>. In some embodiments, the memory <NUM> may be implemented using a single physical device (e.g., one optical, magnetic, organic or other memory or disc storage unit), while in other embodiments, the memory <NUM> can be implemented using two or more physical devices.

As noted, the memory <NUM> may include computer-readable program instructions that relate to operations of system <NUM>. As such, the memory <NUM> may include program instructions to perform or facilitate some or all of the functionality described herein.

<FIG> illustrates a circuit <NUM>, according to an example embodiment. Circuit <NUM> may be similar or identical to system <NUM> as illustrated and described with regard to <FIG>. Some or all of the elements of circuit <NUM> may be similar or identical to corresponding elements of system <NUM>.

Circuit <NUM> includes a laser diode <NUM>, a first FET <NUM>, and a second FET <NUM>. The circuit <NUM> may also include a voltage source <NUM>, a trigger source <NUM>, and a controller <NUM>.

In an example embodiment, the laser diode <NUM> is coupled to a supply voltage <NUM>, which may be provided, at least in part, by the voltage source <NUM>. The laser diode <NUM> is also coupled to a drain terminal <NUM> of the first FET <NUM>. A source terminal <NUM> of the first FET <NUM> is coupled to a ground terminal <NUM>. In some embodiments, the supply voltage may be greater than <NUM> volts.

Furthermore, a drain terminal <NUM> of the second FET <NUM> is coupled to the supply voltage <NUM>. A source terminal <NUM> and a gate terminal <NUM> of the second FET <NUM> are coupled to ground terminal <NUM>. As a result, source terminal <NUM>, gate terminal <NUM>, and ground terminal <NUM> are all at substantially the same voltage.

Without the second FET <NUM>, at short pulse widths (e.g., less than <NUM> ns) and/or high repetition rates, a parasitic inductance <NUM> may provide undesirable circuit behavior such as ringing or other effects. However, by coupling the source terminal <NUM> and the gate terminal <NUM> to ground, the second FET <NUM> operates as a fixed or variable capacitor. The capacitance value of the second FET <NUM> provides compensation for the parasitic inductance <NUM>.

In some embodiments, a gate terminal <NUM> of the first FET <NUM> may be coupled to the trigger source <NUM>. In such a scenario, the trigger source <NUM> may be coupled to the controller <NUM>. The trigger source <NUM> may be a signal generator, such as a Tektronix <NUM> Arbitrary Waveform Generator. However, the trigger source <NUM> could additionally or alternatively be any other device or custom circuit (e.g., an Application-Specific Integrated Circuit, ASIC or Field-Programmable Gate Array, FPGA) configured to provide a continuous or pulsed voltage signal to gate <NUM>. As an example, the trigger source <NUM> may include a Peregrine Semiconductor PE29100 high-speed FET driver.

In an example embodiment, the first FET <NUM> may be an NMOS enhancement mode FET. That is, when the trigger source <NUM> provides a signal such that a "high" gate-source voltage (e.g., a voltage between the gate <NUM> and the drain <NUM>) is greater than zero, the first FET <NUM> may substantially operate as being "ON" or like a closed switch. When the trigger source <NUM> provides a "low" gate-source voltage (e.g., zero volts between the gate <NUM> and the drain <NUM>), the first FET <NUM> may operate as being "OFF" or like an open switch.

In such a scenario, the trigger source <NUM> is operable to provide a trigger pulse to gate <NUM>, turning the first FET <NUM> "ON" and causing the laser diode <NUM> to emit a laser light pulse <NUM>. In an example embodiment, the laser light pulse <NUM> may have a pulse width of less than <NUM> nanoseconds. Furthermore, the trigger source <NUM> may be operable to provide a pulse train of trigger pulses so as to cause the laser diode <NUM> to emit a laser pulse train of laser light pulses <NUM>, each laser pulse of the pulse train having a pulse width of less than <NUM> nanoseconds.

One of ordinary skill in the art would understand that many other variations of circuit <NUM> are possible to provide a fast switching capability and/or provide sub-<NUM> nanosecond laser light pulse widths. For example, the circuit <NUM> could be modified to accommodate the first FET <NUM> and/or the second FET <NUM> as being PMOS-type and/or depletion mode FETs. All such variations are contemplated within the scope of the present disclosure. It will be understood that other circuitry <NUM> may be included in circuit <NUM>. In such scenarios, other circuitry <NUM> could include, for example, circuitry that may operate over a slower time scale than that of the second FET <NUM> and/or the laser diode <NUM>.

Optionally, at least one of the first FET <NUM> or the second FET <NUM> may be a high electron mobility transistor (HEMT). Namely, the HEMT could include a semiconductor heterostructure (e.g., GaAs/AlGaAs, AlGaN/AlN/GaN, etc.). Additionally or alternatively, the first FET <NUM> or the second FET <NUM> may be a high-speed high-power transistor. Furthermore, as described elsewhere herein, the first FET <NUM> and/or the second FET <NUM> could include GaN, such as an Efficient Power Conversion Corporation EPC2010C NMOS surface mount GaN enhancement mode power transistor. Additionally or alternatively, the first FET <NUM> and/or the second FET <NUM> could include SiC. For example, the first FET <NUM> and/or the second FET <NUM> could be a Wolfspeed/Cree C3M0120090J-TR SiC N-channel surface mount FET. Other FET device types and materials are contemplated herein.

<FIG> illustrates a circuit <NUM>, according to an example embodiment. The elements of circuit <NUM> may be similar or identical to corresponding elements of circuit <NUM>, as illustrated and described with regard to <FIG>. Circuit <NUM> may include a return diode <NUM> that could be a semiconductor diode device, such as a Central Semiconductor CMPD914TR surface mount switching diode.

<FIG> illustrates a lumped circuit <NUM>, according to an example embodiment. The elements of lumped circuit <NUM> may be lumped circuit model representations of various elements of circuits <NUM> and <NUM>, as illustrated and described with regard to <FIG> and <FIG>, respectively. For example, lumped circuit <NUM> may be a schematic representation of the circuit <NUM> while first FET <NUM> is "on" and the laser diode <NUM> is emitting light <NUM>. In such a scenario, the lumped circuit <NUM> may include a parasitic inductance <NUM>, a characteristic capacitance <NUM>, and a characteristic body diode <NUM>. The characteristic capacitance <NUM> may be based on the second FET <NUM>. In such scenarios, the energy stored in the characteristic capacitance <NUM> may provide current to the laser diode during the nanosecond time scale of the pulse width. The power supply may recharge the characteristic capacitance <NUM> over a much slower time scale. The value of characteristic capacitance <NUM> may vary, based on, for example, the voltage across the laser diode <NUM>. In some embodiments, a combination of the parasitic inductance <NUM> and the characteristic capacitance <NUM> may provide a RLC circuit configured to provide sub-<NUM> nanosecond laser pulse widths. As such, the charge within the lumped circuit <NUM> may "free-wheel" rather than oscillate within the circuit.

Furthermore, after the initial pulse and once the current through the laser diode starts to decrease, the second FET <NUM> may include a characteristic body diode <NUM> that may prevent a drain-to-source voltage inversion. By preventing such a voltage inversion, ringing may be reduced or eliminated. In other words, the second FET <NUM> may reduce or eliminate the development of a negative voltage between the supply voltage <NUM> and ground when switching the first FET at high speed.

As such, the second FET <NUM> and its associated characteristic capacitance <NUM> and characteristic body diode <NUM> may reduce or eliminate ringing associated with driving the first FET <NUM> and the laser diode <NUM> at short pulse widths and/or at a high repetition rates.

While second field effect transistor <NUM> and second FET <NUM> are characterized as field effect transistors, it will be understood that another electrical device with the same characteristics of second field effect transistor <NUM> and second FET <NUM> could be substituted within the scope of the present disclosure. That is, another type of circuit element, such as a p-n diode, a Schottky diode, a flyback diode, or a freewheeling diode, among other possibilities, may be used in place of second field effect transistor <NUM> or second FET <NUM> to reduce or eliminate ringing in laser pulser circuits.

<FIG> illustrates voltage waveforms <NUM> and <NUM>, according to example embodiments. Namely, voltage waveforms <NUM> and <NUM> may represent a voltage across the laser diode <NUM> during a single laser pulse operation without, and with, the second FET <NUM>, respectively.

For instance, voltage waveform <NUM> may relate to an example in which circuit <NUM> does not include the second FET <NUM>. In such a scenario, waveform <NUM> includes a desired pulse <NUM> but may also include ringing oscillations <NUM>. Such oscillations <NUM> may reduce the operating lifetime of the laser diode <NUM>, cause unwanted laser light emission, and/or limit a maximum possible laser repetition rate.

The inclusion of the second FET <NUM> into the circuit <NUM> may provide better device operation characteristics. For example, a laser pulse <NUM> may have a full-width half maximum (FWHM) <NUM> of less than <NUM> nanoseconds. It is understood that a laser pulse width may be measured in other ways (e.g., <NUM>% = rising edge, <NUM>% = falling edge, etc.). Furthermore, voltage waveform <NUM> may exhibit reduced or eliminated ringing oscillations. As such, the laser diode <NUM> may have a longer operating lifetime, unwanted laser light emission may be reduced, and the maximum possible laser repetition rate may be increased compared to the scenario without the second FET <NUM>.

The particular arrangements shown in the Figures should not be viewed as limiting. It should be understood that other embodiments may include more or less of each element shown in a given Figure. Further, some of the illustrated elements may be combined or omitted.

A step or block that represents a processing of information can correspond to circuitry that can be configured to perform the specific logical functions of a herein-described method or technique. Alternatively or additionally, a step or block that represents a processing of information can correspond to a module, a segment, or a portion of program code (including related data). The program code can include one or more instructions executable by a processor for implementing specific logical functions or actions in the method or technique. The program code and/or related data can be stored on any type of computer readable medium such as a storage device including a disk, hard drive, or other storage medium.

The computer readable medium can also include non-transitory computer readable media such as computer-readable media that store data for short periods of time like register memory, processor cache, and random access memory (RAM). The computer readable media can also include non-transitory computer readable media that store program code and/or data for longer periods of time. Thus, the computer readable media may include secondary or persistent long term storage, like read only memory (ROM), optical or magnetic disks, compact-disc read only memory (CD-ROM), for example. The computer readable media can also be any other volatile or non-volatile storage systems. A computer readable medium can be considered a computer readable storage medium, for example, or a tangible storage device.

Claim 1:
A system comprising:
a trigger source (<NUM>);
a laser diode (<NUM>);
a first field effect transistor (<NUM>), wherein the laser diode is coupled to a supply voltage and a drain terminal (<NUM>) of the first field effect transistor, wherein a source terminal (<NUM>) of the first field effect transistor is coupled to ground, wherein a gate terminal (<NUM>) of the first field effect transistor is coupled to the trigger source, wherein the first field effect transistor is coupled in series between the laser diode and ground; and
a second field effect transistor (<NUM>), wherein a drain terminal (<NUM>) of the second field effect transistor is coupled to the supply voltage, wherein a source terminal (<NUM>) of the second field effect transistor and a gate terminal (<NUM>) of the second field effect transistor are coupled to ground;
wherein a continuous or pulsed signal of the trigger source (<NUM>) results in turning on the first field effect transistor (<NUM>) thereby causing the laser diode (<NUM>) to emit a laser light pulse;
wherein the laser diode is configured to emit a laser light pulse based on a current through the first field effect transistor;
wherein the second field effect transistor is coupled in parallel with the laser diode and the first field effect transistor; and
wherein the second field effect transistor is configured to operate as a capacitor to provide a current to the laser diode with the capacitance value of the second field effect transistor providing compensation for a parasitic inductance of the system.