Patent Description:
In described examples, a multi-threshold CMOS sequential circuit includes a first latch circuit, which includes transfer gates and inverters powered from a switchable voltage node and is formed of transistors having threshold voltages in a first range to provide a primary data path storing at least one data bit during active mode operation of the sequential circuit. The first switching circuit selectively decouples the switchable voltage node from a continuous voltage node when a switching control signal is in a first state for low-power retention mode operation of the sequential circuit, and the first switching circuit couples the switchable voltage node to the continuous voltage node when the switching control signal is in a second state for active mode operation of the sequential circuit. A second latch circuit includes inverters formed of transistors selectively powered from the continuous voltage node and having threshold voltages in a second range higher than the first range. In low-power retention mode operation, the inverters of the second latch circuit selectively latch the data bit transferred from the first latch circuit. The second latch circuit further includes a transfer gate formed of transistors having threshold voltages in the second range, which provides a data transfer path between the first and second latch circuits during transitions from active to low-power retention mode and vice versa. The transmission gate disconnects the first and second latch circuits from one another during both active mode and low-power retention mode operation. A second switching circuit selectively disconnects the inverters of the second latch circuit from the continuous voltage node during active mode operation of the sequential circuit. All transistors in the first latch circuit have threshold voltages in the first range and all transistors in the second latch circuit have threshold voltages in the second range.

In some examples, a first latch is a slave latch, and a master latch circuit is provided to form a flip-flop, with the master latch providing a flip-flop input and the slave latch providing a flip-flop data output. A second latch provides a shadow latch or balloon latch to save the flip-flop data bit during low-power retention mode operation. In other examples, the sequential circuit is a clock gating cell, which receives a clock enable signal, along with an AND gate powered from the switchable voltage node, with a first input receiving the clock signal, a second input coupled with latch node of the first latch circuit, and an output providing a clock output signal. The second latch circuit stores the clock data state in the low-power retention mode.

In certain examples, a control circuit selectively operates in a first mode for low-power retention mode operation or in a second mode for active mode operation of the sequential circuit. The control circuit provides separate retention, power switching control, and transfer signals to implement a power down sequence to transition from the low-power retention mode to the active mode, as well as a power up sequence to transition from active mode operation to low-power retention mode operation. The transfer gate of the second latch circuit connects the first and second latches during only the transitional power up and power down sequences.

In at least one example, a forward bias circuit applies a forward bias voltage to one or more transistors of the sequential circuit according to a bias control signal, with the control circuit selectively providing the bias control signal for application of the forward bias voltage for active mode operation and discontinuing the application of the forward bias voltage for low-power retention mode operation.

The drawings are not necessarily drawn to scale. In described examples, sequential circuits include a latch circuit built from transistors with threshold voltages in a first range for high-speed active mode operation, along with a second latch formed of transistors with threshold voltages in a second (higher) range for retaining data during low-power retention mode operation. The second latch includes inverters and transfer gates, as well as power switching circuitry to decouple the inverters from power connections during active mode operation, such that all operating transistors during active mode operation are implemented in SVT or LVT transistors with threshold voltages in the first range. The second latch is disconnected from the first latch during both active mode and low-power retention mode to mitigate leakage current. A transfer gate connecting the first and second latches is turned on during transitions from active to low-power retention mode and vice versa. Moreover, the primary data path in the first latch (and any additional latch in a master-slave latch configuration for flip-flop applications) does not include any HVT transistors. Performance parameters (such as set up-time, hold-time, clock-to-output delay and minimum clock pulse widths) can be unaffected by the isolated HVT transistors during active mode operation, while leakage in the low-power retention mode is unaffected by the SVT and/or LVT circuitry. The described examples may be advantageously employed for flip-flops, integrated clock-gating cells (ICGs) or other sequential circuits for high active mode performance and low leakage in the low-power retention mode.

<FIG> illustrates an MTCMOS sequential circuit <NUM> implementing a master-slave latch configuration in an integrated circuit (IC) with a master latch circuit <NUM> and a slave latch circuit <NUM> operating as a D flip-flop sequential circuit receiving a data input "D" and providing a data output "Q" under control of a clock signal CLK provided via a clock network <NUM> from a clock source <NUM>. The master and slave latches <NUM>, <NUM> are formed of PMOS and NMOS transistors MP and MN, respectively, having threshold voltages in a first range. In certain embodiments, the latches <NUM> and <NUM> include transistors formed at a standard or nominal threshold voltage level or range (SVT), although other embodiments are contemplated in which lower threshold voltage (LVT) transistors are used to form the master and/or slave circuits <NUM>, <NUM>, or one or both of the latch circuits <NUM>, <NUM> may be constructed using a combination of SVT and LVT transistors of different threshold voltage values or ranges, where the collective ranges of such SVT and/or LVT transistors are referred to herein as being within a first threshold voltage range. The sequential circuit <NUM> further includes a balloon latch or shadow latch <NUM> with inverters and a transfer gate formed using HVT transistors (indicated generally as HMP and HMN) of a second, higher threshold voltage range. In the illustrated circuitry <NUM>, moreover, all the transistors of the master and slave latches <NUM> and <NUM> that are operational in active or normal mode are SVT or LVT transistors having threshold voltages in the first range. This advantageously facilitates high speeds during active mode operation.

As shown in <FIG>, a power management control circuit <NUM> provides various signals including a switching control signal PONINZ provided to the gate of a PMOS high threshold voltage transistor HMP4 forming a first switching circuit to selectively connect or disconnect a switchable voltage node VDDs to or from a continuous voltage node VDDC, such as <NUM> V in one non-limiting example. In this regard, the inverters of the master and slave latches <NUM> and <NUM> are selectively (e.g., switchably) powered by the switchable voltage node VDDs, and inverters of the balloon latch circuit <NUM> are powered from the continuous voltage node VDDC as shown. In certain embodiments, the control circuit or controller <NUM> provides the switching control signal PONINZ in a first state (high) for low-power retention mode operation with the switchable voltage node VDDs disconnected from VDDC (e.g., master and slave latches <NUM>, <NUM> powered down), and provides the signal PONINZ in a second (low) state for active mode operation with the master and slave latch circuits <NUM> and <NUM> powered. The control circuit <NUM> further provides a retention signal RET in a first state (high) for low-power retention mode operation and in a second state (low) for active mode operation of the sequential circuit <NUM>. Also, the control circuit <NUM> provides a separate transfer signal TSFRZ in a first (hi) state during normal active mode and low-power retention modes and in a second (low) state only during transitions between low-power retention mode and active mode, and is in a second (high) state otherwise as described further below in connection with <FIG>.

As shown in <FIG>, the control circuit <NUM> provides the retention signal RET to an input <NUM> of an inverter <NUM> to create an inverted retention signal RETZ at an inverter output <NUM>, and the control circuit <NUM> provides the transfer signal TSFRZ to an input <NUM> of an inverter <NUM> having an output <NUM> providing an inverted transfer signal TSFR, where the inverters <NUM> and <NUM> in certain embodiments are formed using SVT and/or LVT transistors with threshold voltages in the first range and are powered from the switchable voltage node VDDs, although not a strict requirement of all possible embodiments. However, the connection of the inverters <NUM> and <NUM> to the switchable voltage node VDDs advantageously saves leakage of two inverter circuits during low-power retention mode, with the outputs RETZ and TSFR from the inverter <NUM> and <NUM> will be driven to a low or "<NUM>" state at appropriate times by the operation of the power management controller <NUM> and will remain in the states when the corresponding inverter <NUM>, <NUM> is powered down by operation of the power control transformer HMP4 when PONINZ is brought low by the controller <NUM> during low-power retention mode. As further described below in connection with <FIG>, moreover, the controller <NUM> implements power up and power down sequences in certain embodiments for transitioning between normal and low-power retention modes.

The clock distribution network or "clock-tree" <NUM> in <FIG> and <FIG> distributes the clock signal throughout the integrated circuit in which the sequential circuit <NUM> is implemented, where the clock network <NUM> is powered by the switchable voltage node VDDs in the illustrated embodiment. When powered, the clock network <NUM> provides a clock signal CLK to an input <NUM> of an inverter <NUM> (also formed using SVT/LVT transistors and powered from the VDDs node in this example), with the inverter output <NUM> providing an inverted clock signal CLKZ. The control circuit <NUM> can be any suitable logic circuitry, whether programmable or otherwise, configured or otherwise operative when powered to provide control signals RET, TSFRZ, PONINZ and other signals (e.g., VFB as illustrated and described below in connection with <FIG>) as described herein, where the control circuit <NUM> in certain embodiments is powered by the continuous voltage node (e.g., VDDC) to continuously operate during both active mode, low-power retention mode as well as in power up or power down transition sequences therebetween as described further below.

Referring also to <FIG>, the latch circuits <NUM>, <NUM> and <NUM> each include one or more transfer gates, for example formed as shown in <FIG> by parallel connection of a PMOS transistor and an NMOS transistor with the lower NMOS transistor receiving a control signal generated by the control circuit <NUM> or the clock source <NUM>, and the upper PMOS transistor receiving an inverse of the control signal. The latches <NUM>, <NUM> and <NUM> also include inverter circuits which can be formed using any suitable CMOS inverter circuitry, for example as shown in <FIG> including an upper PMOS transistor connected between an upper power connection and an output node along with an NMOS transistor connected from the output node to a ground connection, with the transistor gates connected to one another to form an inverter input. In the illustrated sequential circuit <NUM>, the transfer gates and inverters of the master latch circuit <NUM> and the slave latch circuit <NUM> are constructed using MOS transistors having threshold voltages in the first range, whereas the transfer gate <NUM>, the inverters <NUM> and <NUM>, and the power control switching circuit transistors MP15, MP16, MP17 and MN15 of the balloon latch circuit <NUM> are formed using SVT and/or LVT transistors with threshold voltages in the first range in the illustrated embodiments, although not a strict requirement of all implementations. Moreover, as shown in <FIG> and <FIG>, the inverter circuits <NUM>, <NUM>, <NUM>, <NUM> and <NUM> of the master and slave latch circuits <NUM>, <NUM> are powered from VDDs, whereas the inverters <NUM> and <NUM> of the balloon latch circuit <NUM> are selectively powered from the continuous voltage node VDDC.

In the illustrated flip-flop sequential circuit embodiment <NUM>, the slave latch <NUM> includes transfer gates <NUM>, <NUM> and <NUM> as well as inverters <NUM>, <NUM> and <NUM> connected as shown to provide a primary data path storing at least one data bit during active mode operation, with the output inverter <NUM> providing a "Q" flip-flop data output based on a previously received "D" flip-flop data input received by the master latch circuit <NUM> in a proceeding clock cycle (e.g., cycle of CLK signal). The first transfer gate <NUM> operates according to the CLK and CLKZ signals to selectively couple a first latch input node <NUM> with a first latch node <NUM> when CLK is high, thereby transferring data from the master latch <NUM> to the slave latch <NUM>, and the transfer gate <NUM> decouples the nodes <NUM> and <NUM> from one another when the clock signal CLK is low. The first latch node <NUM> is connected as an input to a first inverter <NUM> whose output <NUM> is connected as an input to a second inverter <NUM>. In certain embodiments, the second inverter <NUM> may be replaced by a logic gate such as a NAND gate 34a, for example, as shown in <FIG> below. The output <NUM> of the second inverter <NUM> in <FIG> and <FIG> is selectively connected back to the first latch node <NUM> to form a latch circuit with the first inverter <NUM> via transfer gates <NUM> and <NUM> operated respectively according to inverted CLK and RET signals from the control circuit <NUM> as shown. In the illustrated example, the transfer gate <NUM> selectively connects the inverter output <NUM> with a second latch node <NUM> when CLK is low, and decouples the output of the second inverter <NUM> from the node <NUM> when CLK is high. Moreover, the third transfer gate <NUM> selectively couples the first and second latch nodes <NUM>, <NUM> to one another when RET is low and decouples the nodes <NUM>, <NUM> when RET is high. During active mode operation with RET low, the slave latch <NUM> operates to clock data in from the master latch <NUM> according to the CLK signal and temporarily stores a data bit as a voltage at the first latch node <NUM>, which is inverted by the inverter <NUM> to form the flip-flop Q output state (e.g., voltage level) at the output node <NUM>.

When activated, the balloon latch circuit <NUM> receives the data bit from the slave latch circuit <NUM> via a fourth transfer gate <NUM> formed of HVT transistors HMP5 and HMN2 when activated with the transfer signal TSFRZ in a low state to couple the first latch node <NUM> of the slave latch <NUM> with a fourth latch node <NUM> of the balloon latch <NUM>, and a third inverter <NUM> receives the signal at the node <NUM> as an input. When the inverter <NUM> is powered via MP15 and MP16 via a low signal RETZ from the inverter <NUM> or a low signal TSFRZ, an inverted output is provided to an input <NUM> of a fourth inverter <NUM>, which is powered from VDDC when RETZ is low via MP17 and RET is high via MN <NUM> to provide an inverted output to the fourth latch node <NUM>, thereby storing the data bit transferred from the slave latch <NUM>.

In the D flip-flop circuit <NUM> of <FIG> and <FIG>, the master latch <NUM> initially clocks in the data from the D input via a fifth transfer gate <NUM> according to the CLKZ signal (e.g., when CLK is low) to couple the D input with a master latch node <NUM> connected to provide an input to a fifth inverter <NUM>. In certain embodiments, the inverter <NUM> may be replaced by a logic gate, such as a NAND gate 13a as shown in <FIG> below. The output of the inverter <NUM> in <FIG> and <FIG> is coupled to an input <NUM> of a sixth transfer gate <NUM> operative when RET is low during active mode operation to couple the output of the inverter <NUM> with the first latch input node <NUM> and with an input of a sixth inverter <NUM> whose output <NUM> is provided to a seventh transfer gate <NUM> operated according to the CLK signal to provide a signal from the output of the inverter <NUM> to the master latch input node <NUM>. In this manner, the inverters <NUM> and <NUM> of the master latch <NUM> operate during active mode to latch the data received at the flip-flop input D according to the clock signal CLK.

As shown in <FIG>, the master latch <NUM> and the slave latch <NUM> are formed of LVT and/or SVT transistors MP (PMOS), MN (NMOS) including PMOS transistors MP1, MP2, MP3, MP4 and MP5 and NMOS transistors MN1, MN2, MN3, MN4 and MN5 of the master latch circuit <NUM>, as well as PMOS transistors MP6, MP7, MP8, MP9, MP10 and MP11 and NMOS transistors MN6, MN7, MN8, MN9, MN10 and MN11 of the slave latch circuit <NUM>. Moreover, the PMOS transistors of the inverters <NUM>, <NUM>, <NUM>, <NUM> and <NUM> include source terminals powered by connection to the switchable voltage node VDDs as shown in <FIG> for selective disconnection from power for low-power retention mode operation. In the illustrated embodiment, the source terminals of the LVT and/or SVT NMOS transistors in the inverters <NUM>, <NUM>, <NUM>, <NUM> and <NUM> are connected to a circuit ground GND (as are the HVT transistors of the balloon latch circuit <NUM> in the illustrated embodiment). The HVT power switch control circuit HMP4 provides high-side disconnection for low-power retention mode operation. In another possible embodiment, low-side disconnection may be provided, with suitable connection of the LVT and/or SVT transistors of the latch circuits <NUM>, <NUM> with the ground terminal GND through one or more HVT power disconnect transistors (e.g., NMOS HVT transistor, not shown), for example according to a switching control signal (e.g., PONIN) from the power management control circuit <NUM>. Other implementations are possible, in which both high-side and low-side power decoupling can be provided to implement low-power retention mode operation of the sequential circuit <NUM>.

Referring also to <FIG> illustrates a table <NUM> showing signal states for active mode operation ("ACTIVE") and low-power retention mode operation ("LPR"), along with a power down sequence PD1, PD2 and PD3 to transition the sequential circuit <NUM> from the active mode to the low-power retention mode, and a power up sequence PU2, PU3 and PU4 for transitioning from the low-power retention mode to the active mode. Also, <FIG> shows a graph <NUM> including waveforms <NUM>, <NUM> and <NUM> respectively showing the RET, TSFRZ and PONINZ signal waveforms in the sequential circuit <NUM> of <FIG> and <FIG>.

Beginning in active mode operation at T1 in <FIG>, the controller <NUM> provides low signals (e.g., "<NUM>" in table <NUM> of <FIG>) for RET and PONINZ and high signal TSFRZ. In this condition, the sequential circuit <NUM> can operate according to the clock signal CLK for high-speed operation with no HVT transistors affecting the circuit operation. In this manner, none of the logic circuitry with a floating input is powered, and the floating latch node <NUM> in the balloon latch circuit <NUM> is not connected to any powered input.

The controller <NUM> begins a power down sequence at T1 with a first power down phase PD1 in which the TSFRZ signal is provided in a low state ("<NUM>" in <FIG>) while the RET and PONINZ signals remain low. As shown in <FIG>, this activates the transfer gate <NUM> of the balloon latch circuit <NUM> to connect the first latch node <NUM> with the fourth latch node <NUM> to provide a data transfer path from the slave latch <NUM> to the balloon latch <NUM>. Also, this causes the transistor MP16 to turn ON, thereby connecting the balloon latch inverter <NUM> to the continuous voltage node VDDC, to power up the inverter <NUM>.

In a subsequent second power down phase PD2 beginning at T2, the control circuit <NUM> provides the retention signal RET in a high state while maintaining the PONINZ signal and the TSFRZ signal low. This assertion of the RET signal in phase PD2 turns off the transfer gate <NUM> in the master latch <NUM> as well as the transfer gate <NUM> in the slave latch <NUM>, while providing power and ground connections for the balloon latch inverter <NUM> via transistors MP17 and MN15.

Thereafter at T3, the controller <NUM> implements a third power down phase PD3 in which the control circuit <NUM> provides high signals RET and PONINZ, and low signal TSFRZ. This assertion of PONINZ acts to disconnect VDDs from VDDC via transistor HMP4 with the transferred data from the slave latch <NUM> now stored in the balloon latch circuit <NUM>.

The power down sequence is completed at T4 with the control circuit <NUM> bringing TSFRZ high again to decouple the first latch node <NUM> of the slave latch <NUM> from the balloon latch node <NUM>. Moreover, the continued assertion of the RET signal maintains the provision of power to the balloon latch inverter <NUM> via the transistor MP15.

With the balloon latch transfer gate <NUM> off, and with the master and slave latch circuitry and the clock source <NUM> powered down, the low-power retention (LPR) mode from T4 through T7 provides for clock-independent saving of the latch data in the balloon latch circuit <NUM> with no SVT or LVT leakage path since the SVT and LVT transistors of the latch circuits <NUM> and <NUM> are powered down and the balloon latch transfer gate <NUM> is off. Moreover, unlike certain conventional MTCMOS sequential circuits, the illustrated circuitry <NUM> does not require a separate latch for clock state retention, and allows for the chip level clock tree to be powered down via the PONINZ signal from the control circuit <NUM> and the transistor HMP4 to turn off the clock source <NUM>, thereby facilitating further power savings. Moreover, the illustrated circuitry does not need to retain the clock state inside the flip-flop circuit <NUM> as subsequent restoration operation ensures that the slave latch <NUM> is always successfully restored (written), and if CLK is high ("<NUM>"), the master latch circuit <NUM> also is written during restoration. Thus, the illustrated design provides significant advantages over conventional MTCMOS sequential circuits.

Continuing at T6 in <FIG>, the control circuit implements a power up sequence PU2, PU3 and PU4 to transition from the low-power retention mode operation to the active mode operation of the sequential circuit <NUM>. The power up sequence begins at PU2 with the control circuit <NUM> again asserting the TSFRZ signal to a low state at T7 to turn on the transfer gate <NUM> of the balloon latch circuit <NUM>, thereby coupling the slave latch node <NUM> with the balloon latch node <NUM>.

At T8, the control circuit <NUM> implements a third power up phase PU3 by changing the PONINZ signal to the low state to power up the inverters <NUM>, <NUM>, <NUM>, <NUM> and <NUM> of the master latch circuit <NUM> and the slave latch circuit <NUM> via transistor HMP4, and the fourth power up phase PU4 begins at T9 with the control circuit <NUM> bringing the RET signal low. This powers down the balloon latch inverter <NUM> and turns on the LVT or SVT transfer gates <NUM> and <NUM> in the master and slave latches <NUM> and <NUM>, respectively.

Thereafter at T10, the control circuit <NUM> returns to active mode operation by bringing the transfer signal TSFRZ high to again turn off the balloon latch transfer gate <NUM> and to power down the HVT inverters <NUM> and <NUM>. Regardless of the clock state during this restore operation, the buffered data is successfully transferred from the balloon latch <NUM> to the slave latch <NUM>, and subsequent cycles of the clock signal CLK will resume transfer of input data into the master latch circuit <NUM> and data from the master latch to the slave latch <NUM> to ensure the proper state of the flip-flop output data Q at the output node <NUM>. In this regard, the illustrated circuitry does not require a separate balloon or shadow latch for preserving clock state during low-power retention mode.

Referring to <FIG> and <FIG>, another MTCMOS sequential circuit <NUM> is illustrated including a first latch <NUM> generally similar to the slave latch <NUM> of <FIG> and <FIG> described above, without the output inverter <NUM>, where the circuit <NUM> implements an integrated clock gating cell (ICG) with an input receiving a clock enable signal CLK_EN at the first latch input node <NUM>. The latch <NUM> in this case includes transfer gates <NUM>, <NUM> and <NUM> operated according to the clock and retention signals CLK and RET as described above, as well as inverters <NUM> and <NUM> powered from the switchable voltage node VDDs and formed using SVT and/or LVT transistors with threshold voltages in the first range. In the first latch <NUM> of <FIG> and <FIG>, moreover, the transfer gates <NUM> and <NUM> are operated in inverse fashion relative to the slave latch <NUM> of <FIG> and <FIG>, with the transfer gate <NUM> in <FIG> and <FIG> being turned on (conductive) to connect the nodes <NUM> and <NUM> when the CLK signal is low (CLKZ is high), and the transfer gate <NUM> being on (conductive) when CLK is high (CLKZ is low). Also, the clock gating cell sequential circuit <NUM> includes an AND gate <NUM> with a first input <NUM> receiving the CLK signal from the clock source <NUM> (<FIG> and <FIG> above) and a second input coupled with the first latch node <NUM>. The AND gate <NUM> in this embodiment is implemented using transistors with threshold voltages in the first range, and includes a gate output <NUM> providing a clock output signal CLKOUT.

In operation, the control circuit <NUM> provides the control signals RET, TSFRZ and PONINZ as illustrated and described above in connection with <FIG> to operate the clock gating cell circuit <NUM> of <FIG> and <FIG>. While the above embodiments illustrate implementation of the first latch <NUM>, <NUM> and the balloon latch circuit <NUM> in the context of a flip-flop sequential circuit <NUM> (<FIG> and <FIG>) and a clock gating cell circuit <NUM> (<FIG> and <FIG>), other embodiments are possible implementing other forms of sequential circuits using the concepts of the present disclosure.

Referring to <FIG>, <FIG> illustrates another D flip-flop sequential circuit <NUM> including a master latch circuit <NUM>, a slave latch circuit <NUM>, a balloon latch circuit <NUM> and various control circuitry as described above. Also, the power management control circuit <NUM> in this embodiment selectively provides a forward bias control signal VFB for enhanced high-speed active mode operation. <FIG> is a sectional side elevation view showing a portion of an MTCMOS integrated circuit (IC) <NUM> implementing the sequential circuit <NUM> of <FIG>, and illustrating P-well and N-well taps for selectively adjusting a bias voltage applied to wells for improving operation of one, some or all of the NMOS and/or PMOS transistors in the sequential circuit <NUM>. As shown in <FIG>, the integrated circuit <NUM> is constructed using a P-substrate <NUM> in which an NMOS transistor is formed in and/or on a P-well <NUM> within a deep N-well (DN-well) <NUM>, and a PMOS transistor is formed in and/or on an N-well <NUM>. A forward bias circuit <NUM>, <NUM> is provided in the integrated circuit <NUM> to selectively apply a non-zero forward biased to the P-well <NUM> via a P-tap according to the VFB signal from the control circuit <NUM>, where asserting the signal VFB in a first state (e.g., high) connects the P-tap to a positive terminal of a bias voltage source <NUM> as shown, thereby raising the bias to the NMOS transistor(s) relative to ground for faster switching. In the illustrated embodiment, moreover, asserting the VFB signal connects the N-tap to a negative terminal of a bias voltage source <NUM> to selectively reduce the voltage at the N-well <NUM> from VDDC to a lower voltage to improve switching operation of the PMOS transistor(s). In this embodiment, the forward biasing circuitry <NUM>, <NUM>, <NUM> and <NUM> can be used to modify LVT, SVT and/or HVT NMOS and PMOS transistors in the latch circuits <NUM>, <NUM> and/or <NUM>, with the control circuit <NUM> selectively disabling the biasing by bringing VFB low during the low-power retention mode operation to further reduce power consumption. In this regard, turning off the forward biasing during the low-power retention mode conserved power by reducing leakage that would otherwise result from application of the forward bias, and also the power required to generate the body-biases (e.g., the power from the voltage sources <NUM> and <NUM> in <FIG>). Moreover, separate biasing control can be provided for different wells for individualized biasing in certain embodiments. By this technique, the P-well <NUM> is connected through the switch <NUM> and the P-tap to the ground terminal GND, while the N-well <NUM> is connected to VDDC through the N-tap and the switch <NUM> during the low-power retention mode. While the illustrated example provides the VFB signal from the power management controller <NUM>, such a forward bias control signal can be provided by other control circuitry within the integrated circuit, for example, separate from the power management controller <NUM>.

Operation of this embodiment is further illustrated in the table <NUM> of <FIG> and the graph <NUM> of <FIG>. In general, the control circuit <NUM> operates in similar fashion to that described above in connection with <FIG> to provide the control signals RET, TSFRZ and PONINZ (waveforms <NUM>, <NUM> and <NUM> in the graph <NUM> of <FIG>) for active mode operation ("ACTIVE"), low-power retention mode ("LPR"), as well as for a power down sequence PD1, PD2, PD3 and PD4 and a power up sequence PU1, PU2, PU3 and PU4. Beginning in active mode operation at T1 in <FIG>, the controller <NUM> provides low signals (e.g., "<NUM>" in table <NUM> of <FIG>) for RET and PONINZ while TSFRZ and a forward bias control signal VFB are held high, with the sequential circuit <NUM> operating according to the clock signal CLK for high-speed operation with no HVT transistors affecting the circuit operation. The controller <NUM> begins the power down sequence at T1 with a first power down phase PD1 in which the TSFRZ, RET and PONINZ signals are provided in a low state while VFB remains high. This activates the transfer gate <NUM> of the balloon latch circuit <NUM> to connect the first latch node <NUM> with the fourth latch node <NUM> to provide a data transfer path from the slave latch <NUM> to the balloon latch <NUM> and TSFRZ going low connects the balloon latch inverter <NUM> to the continuous voltage node VDDC via transistor MP16 to power up the inverter <NUM>. In the second power down phase PD2 beginning at T2, the control circuit <NUM> provides the retention signal RET and the VFB signal in a high state while the PONINZ and TSFRZ signals are low, which turns off the transfer gate <NUM> in the master latch <NUM> as well as the transfer gate <NUM> in the slave latch <NUM>, while providing power and ground connections for the balloon latch inverter <NUM> via transistors MP17 and MN15.

At T3, the controller <NUM> implements phase PD3 by providing high signals VFB, RET, and PONINZ while maintaining TSFRZ low to disconnect VDDs from VDDC via transistor HMP4 with the transferred data from the slave latch <NUM> now stored in the balloon latch circuit <NUM>. The power down sequence is completed at T4 in this example with a fourth power down phase PD4 in which the control circuit <NUM> brings TSFRZ high again to decouple the first latch node <NUM> of the slave latch <NUM> from the balloon latch node <NUM>. Moreover, the continued assertion of the RET signal in PD4 maintains the provision of power to the balloon latch inverter <NUM> via the transistor MP15.

At T5, the control circuit <NUM> sets the VFB signal low to remove any forward biasing. With transfer gate <NUM> off and with the master and slave latch circuitry and the clock network <NUM> powered down, the low-power retention (LPR) mode from T5 through T6 provides for clock-independent saving of the latch data in the balloon latch circuit <NUM> with no SVT or LVT leakage path since the SVT and LVT transistors of the latch circuits <NUM> and <NUM> are powered down along with the inverters <NUM>, <NUM> and <NUM>, and the balloon latch transfer gate <NUM> is off. Moreover, unlike certain conventional MTCMOS sequential circuits, no separate latch is required for clock state retention, and thus the chip level clock tree can be powered down via the PONINZ signal from the control circuit <NUM> thereby facilitating further power savings. Furthermore, the illustrated circuitry does not need to retain the clock state inside the flip-flop circuit <NUM> as subsequent restoration operation ensures that the slave latch <NUM> is always successfully restored (written), and if CLK is high ("<NUM>"), the master latch circuit <NUM> also is written during restoration.

At T6, the control circuit <NUM> implements a power up sequence PU1, PU2, PU3 and PU4 to transition from the low-power retention mode operation to the active mode operation of the sequential circuit <NUM>. Beginning with reassertion of the VFB signal high in phase PU1 at T6, the control circuit <NUM> again takes the TSFRZ signal low at T7 in the subsequent second power up phase PU2 to turn on the transfer gate <NUM> of the balloon latch circuit <NUM>, thereby coupling the slave latch node <NUM> with the balloon latch node <NUM>. At T8, the control circuit <NUM> implements a third power up phase PU3 by changing the PONINZ signal to the low state to power up the inverters <NUM>, <NUM>, <NUM>, <NUM> and <NUM> of the master latch circuit <NUM> and the slave latch circuit <NUM> via transistor HMP4, and the fourth power up phase PU4 begins at T9 with the control circuit <NUM> bringing the RET signal low to power down the balloon latch inverter <NUM> and turn on the LVT or SVT transfer gates <NUM> and <NUM> in the master and slave latches <NUM> and <NUM>, respectively. At T10, the control circuit <NUM> returns to active mode operation by bringing the transfer signal TSFRZ high to again turn off the balloon latch transfer gate <NUM> and to power down the HVT inverters <NUM> and <NUM>. As with the above embodiments, the buffered data is successfully transferred from the balloon latch <NUM> to the slave latch <NUM> independent of the clock state during the restore operation, and subsequent cycles of the clock signal CLK will resume transfer of input data into the master latch circuit <NUM> and data from the master latch to the slave latch <NUM> to ensure the proper state of the flip-flop output data Q at the output node <NUM>.

As discussed above, the control circuit <NUM> provides the VFB signal to the switches <NUM> and <NUM> in a high or active state (e.g., "<NUM>" in the table <NUM> of <FIG>) during the during the active mode operation and the power down and power up sequences to facilitate high-speed operation by application of the forward biasing via the sources <NUM> and <NUM> to forward bias the NMOS and PMOS transistors of the sequential circuit <NUM>. During these time periods, using a <NUM> V VDDC example, and assuming a <NUM> V biasing for both the P-well via source <NUM> and the N-well via source <NUM>, the N-well voltage VNWELL curve <NUM> is at approximately <NUM> V to forward bias the PMOS transistors for fast switching, and the P-well voltage VPWELL curve <NUM> in <FIG> is at approximately <NUM> V to forward bias the NMOS transistors for fast switching. The N-well and P-well bias levels provided by the voltage sources <NUM> and <NUM> need not be the same, and any suitable values can be used in various embodiments. Moreover, in certain embodiments, different biasing is applied with respect to LVT, SVT and/or HVT transistors in the sequential circuit <NUM>. During the low-power retention mode from T5 through T6 in <FIG>, however, the control circuit <NUM> removes the forward biasing by changing the VFB signal to a low ("<NUM>") state, thereby connecting the P-well <NUM> to ground and connecting the N-well <NUM> to VDDC for further power conservation.

<FIG> illustrates another possible sequential circuit embodiment <NUM>, again implementing a D flip-flop similar to the embodiment described above in connection with <FIG> and <FIG>, additionally providing a reset or clear function via a CLRZ input. In this example, the master latch circuit <NUM> includes a NAND gate 13a in place of the inverter <NUM> used in the embodiment of <FIG> and <FIG>, and the slave latch circuit <NUM> includes a NAND gate 34a implemented in place of the inverter <NUM> shown in <FIG> and <FIG>. In the illustrated example, moreover, the NAND gates 13a and 34a are formed using LVT and/or SVT transistors having threshold voltages in the first range. As shown in <FIG>, the NAND gate 13a receives a first input from the master latch node <NUM> and receives the CLRZ signal as a second input, while providing an output to the transfer gate <NUM> at node <NUM>. Also, the NAND gate 34a of the slave latch circuit <NUM> receives a first input from the output of the inverter <NUM> at node <NUM> and receives the CLRZ signal as a second input, while providing an output at node <NUM> to the transfer gate <NUM>.

<FIG> illustrates another non-limiting flip-flop MTCMOS sequential circuit embodiment with master and slave latch circuits <NUM> and <NUM> and a balloon latch circuit <NUM> similar to the circuit <NUM> of <FIG>, where the inverters <NUM> and <NUM> are replaced with NAND gates 17a and 30a in the master and slave latches <NUM> and <NUM>, respectively. The NAND gates 17a and 30a have first inputs connected to the nodes <NUM> and <NUM>, respectively, as well as second inputs connected to an inverted preset control signal PREZ as shown. This further option allows presetting of the flip-flop state, with the NAND gates 17a and 30a being powered from VDDs and formed of SVT and/or LVT transistors having threshold voltages in the first range to facilitate high-speed operation. And connecting them to another input (e.g., PREZ) achieves a presetable version. This embodiment provides clear or reset as well as preset functionality while providing the above-described advantages with respect to power savings in low-power retention mode along with high-speed operation during normal mode.

Many other alternate forms of sequential circuits may be provided in different embodiments, wherein the illustrated examples present only a few non-limiting implementations to illustrate the various concepts of the present disclosure. In this regard, the provision of a HVT transfer gate <NUM> in the second latch circuit <NUM> provide significant advantages over conventional MTCMOS sequential circuits, and the novel architectures provide for timely resumption of normal operation without the need for separate balloon latch storage of a clock state. The presently disclosed concepts thus provide multi-threshold voltage CMOS sequential circuitry in which all the transistors involved in active mode operation are SVT and/or LVT transistors, and the data state is retained during low-power retention mode in the shadow or balloon latch circuit <NUM> having a transfer gate <NUM> formed using HVT transistors. Also, the balloon latch <NUM> is completely disconnected from the master and slave latches <NUM>, <NUM> by HVT transmission during both active mode and low-power retention mode to save leakage power via the balloon latch transfer gate <NUM> which is turned on only during mode transitions. The disclosed embodiments, moreover, ensure that performance parameters such as setup-time, hold-time, clock-to-output delay and minimum clock-pulse width are not affected by the HVT transistors, while the leakage in the low-power retention mode is not affected by SVT or LVT transistors. Accordingly, the resulting sequential circuitry can advantageously facilitate high performance in active mode and low-leakage in the low-power retention mode.

Claim 1:
A multi-threshold CMOS sequential circuit (<NUM>), comprising:
a first latch circuit (<NUM>) formed of transistors having threshold voltages in a first range and powered from a switchable voltage node to provide a primary data path storing at least one data bit during active mode operation of the sequential circuit (<NUM>); and
a second latch circuit (<NUM>), including: inverters (<NUM>, <NUM>) formed of transistors selectively powered from the continuous voltage node and having threshold voltages in a second range higher than the first range, the inverters of the second latch circuit (<NUM>) selectively operative for low-power retention mode operation of the sequential circuit (<NUM>) to latch the at least one data bit transferred from the first latch circuit (<NUM>); a transfer gate (<NUM>) formed of transistors having threshold voltages in the second range and providing a data transfer path between the first and second latch circuits (<NUM>, <NUM>) during transitions from active to low-power retention mode and vice versa, the transmission gate (<NUM>) operative to disconnect the first and second latch circuits (<NUM>, <NUM>) from one another during both active mode and low-power retention mode operation of the sequential circuit (<NUM>); and a second switching circuit selectively operative to disconnect the inverters of the second latch circuit (<NUM>) from the continuous voltage node during active mode operation of the sequential circuit (<NUM>);
wherein all transistors in the first latch circuit (<NUM>) having threshold voltages in the first range and characterized in that all transistors in the second latch circuit (<NUM>) having threshold voltages in the second range.