Patent Description:
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance DRAM interface and vertically stacked DRAM. A typical HBM stack of four DRAM chips (e.g., core chips) has two <NUM>-bit channels per chip for a total of eight input/output channels and a width of <NUM> bits in total. An interface (I/F) chip of the HBM provides an interface with the eight input/output channels, which function independently of each other. For example, a clock frequency, a command sequence, and data can be independently provided for each channel Thus, the eight input/output channels are not necessarily synchronous to each other.

There are several types of tests which may be performed for the HBM. For example, a type of test can be performed using a memory Built-In Self Test (mBIST) circuit that may be provided on the I/F chip. The mBIST circuit is provided for verifying failures resulting from stacking the chip. The mBIST circuit may include a memory to store defect information called an error-catch memory (ECM). Using the defect information, for example, hard repair such as blowing fuse to disconnect rows and columns with faulty bits and replacing them with redundant rows or columns may be performed.

The HBM has a post package repair function performed by using the mBIST circuit The post package repair function uses redundancy cells for repair and these redundancy cells are normally formed in memory matrices of the core. However, the post package repair function may not be able to repair defects if the number of defective cells is freater than a number of repairable cells by providing redundancy cells. Furthermore, it may be difficult to repair one or more defective cells which are redundancy cells.

<CIT> B discloses an integrated circuit comprising: a memory module that stores at least one of data and code; a memory repair database that stores data relating to defective memory addresses; a memory control module that communicates with the memory module and the memory repair database, that detects defective memory locations in the memory module, that locates redundant memory elements in the memory module, that stores information that associates memory addresses of the defective memory locations with the redundant memory elements in the memory repair database, and that outputs the information, wherein said memory control module includes a plurality of electrical fuses and storing said information includes electrically altering at least one of said plurality or electrical fuses; a redundant memory decoder module that receives the information and physically remaps the memory addresses to the redundant memory locations.

<CIT> discloses a semiconductor device, adjustment method thereof and data processing system.

<CIT> discloses an an integrated circuit device having a memory cell array including error checking and correcting circuitry and/or column redundancy, and techniques for programming, configuring, controlling and/or operating such device.

The invention is defined in independent apparatus claim <NUM>. Embodiments are defined in dependent claims <NUM> - <NUM>.

Various embodiments of present invention will be explained below in detail with reference to the accompanying drawings. The following detatted description refers to the accompanying drawings that show, by way of illustration, specific aspects and enibodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

<FIG> is a schematic diagram of an interface (I/F) chip and a plurality of core chips in a semiconductor device in accordance with an embodiment of the present disclosure. For example, the semiconductor device <NUM> may be a 3D memory device, such as an HBM, an HMC, a Wide-IO DRAM etc. The semiconductor device is formed by stacking chips verticailly,as shown in <FIG>. The stacked chips may include an inerface chip <NUM> and core chips <NUM>. In this example, each core chip <NUM> may be a memory chip which includes two channels. Each channel may include a plurality of memory cells and circuitries accessing the memory cells. For example, the memory cells may be DRAM memory cells.

<FIG> is a schematic diagram of a memory system including the semiconductor device that includes the interface (I/F) chip and the plurality of core chips in accordance with an embodiment of the present disclosure. The memory system <NUM> may include a memory controller <NUM> and the 3D memory device <NUM>. In this example, the core chips 22a, 22b, 22c and 22d include channels A and C, channels B and D, channels E and G, and channels F and H, respectively. As shown in <FIG>, the channels A, B, C, D, E, F, G and H of the core chips <NUM> may be coupled to the I/F chip <NUM> via different signal lines 23a, <NUM> b, 23c, 23d, 23e, 23f, <NUM>, and <NUM>, respectively. The I/F chip <NUM> may include test control terminals <NUM>, data terminals <NUM> and access signal terminals <NUM> which receive corresponding signals from a memory controller <NUM>. For example, the test control terminals <NUM> may receive test control signals. The data terminals <NUM> may receive write data from the memory controller <NUM> or may transmit read data to the memory controller <NUM>. The access signal terminals <NUM> may receive access signals from the memory controller <NUM>. The access signals may include an operation command (e.g., a read command, a write command) and address information corresponding to the operation command.

<FIG> is a block diagram of an inteface circuit on the I/F chip <NUM> in the semiconductor device in accordance with an embodiment of the present disclosure. An interface circuit is provided on the I/F chip <NUM>. The interface circuit <NUM> may include channel interface blocks CIF_A 32a, CIF_B 32b,. and CIF_H <NUM> which are coupled to corresponding channels, channel A, channel B,. and channel H of the core chip <NUM> in <FIG>. Furthermore, the interface circuit <NUM> may include a plurality of data through substrate vias, TSVDs <NUM> and access through substrate vias TSVAs <NUM>. The TSVDs <NUM> and TSVAs <NUM> are configured to couple the channel interface blocks CIF_A 32a, CIF_B 32b,. and CIF_H <NUM> to the channels, channel A, channel B,. and channel H of the core chip <NUM> in <FIG>, respectively. In one embodiment, each signal line <NUM> in <FIG> may include the corresponding TSVD <NUM> and TSVA <NUM> for each channel. Each channel interface block of the channel interface blocks CIF_A 32a, CIF_B 32b,. and CIF_H <NUM> may include a data input/output circuit DI/O <NUM> and an access signal output circuit ASO <NUM>. Each DI/O <NUM> may receive data from the coupled channel via the corresponding TSVD <NUM>. The DI/O <NUM> may be further coupled to data terminals DT <NUM>. The data terminals DT <NUM> may be the data terminals <NUM> in <FIG>. The ASO <NUM> may be coupled to access signal terminals AT <NUM>. The access signal terminals AT <NUM> may receive access signals including access requests provided externally (e.g., from the memory controller <NUM> of <FIG>). Each access reqest may include a command including an operation requested (e.g., a read request, a write request, etc.) and an address where the operation requested by the command is operated. The access signal terminals AT <NUM> may be the access signal terminals <NUM> in <FIG>. Each ASO <NUM> may provide the access requests as command signals and address signals, for example, to the coupled channel via the corresponding TSVA <NUM>. In a normal read operation, a read request and corresponding address information are externally provided to the ASO <NUM> via the AT <NUM>. The ASO <NUM> may provide the read request and the corresponding address information to the coupled channel via the TSVA <NUM>, responsive to the read request. The coupled channel may provide the data to the DI/O <NUM> via the TSVD <NUM> in response to the read and the corresponding address information. The DI/O <NUM> may provide the data via the DT <NUM>. Similarly, in a normal write operation. a write request and corresponding address information are externally provided to the ASO <NUM> via the AT <NUM>. The ASO <NUM> may provide the write request and the corresponding address information to the coupled channel via the TSVA <NUM>, responsive to the write request. At the same time, the DI/O <NUM> may receive write data from the DT <NUM> and provide the write data to the coupled channel via the TSVD <NUM> responsive to the write request and the corresponding address information. Each of the channel interface blocks CIF_A 32a, CIF_B 32b,. and CIF_H <NUM> may further include a data comparator circuit DCMP <NUM> and an access signal comparator circuit ACMP <NUM>. Functionalities of the DCMP <NUM> and the ACMP <NUM> will be provided later in detail.

The interface circuit <NUM> may further include a memory built-in self-test block mBIST <NUM>. The mBIST <NUM> may provide test signals to the channel interface blocks CIF_A 32a, CIF_B 32b,. and CIF_H <NUM> via a multiplexer MUX <NUM> in order to perform test operations on each channel responsive to test control signals TCTL. The TCTL are externally provided via test control terminals TCT <NUM>. The TCT <NUM> may be the test control terminals <NUM> in <FIG>. The mBIST <NUM> may perform defective cell detection and repair functions during an initialization operation and a normal operation following the initialization operation, such as read and write operations, as well as during a test operation. Functionalities of the mBIST <NUM> will be provided later in detail. The interface circuit <NUM> may further include a power detection circuit PD <NUM>. The PD <NUM> may provide a power on signal PON to the mBIST <NUM> responsive to power supply PS externally provided via a power terminal PT <NUM>. The mBIST <NUM> may start the initialization operation in response to the PON. The interface circuit <NUM> may further include test terminals TT <NUM> and test pads TP <NUM>. The TT <NUM> may be coupled to a socket or the like in order to couple an external tester (not shown) to the interface circuit <NUM>. The TP <NUM> may couple an external tester (not shown) having a probe card interface, for example, to the interface circuit <NUM>. The TP <NUM> may be used for a test during wafer process. The MUX <NUM> may select one of the TT <NUM>, the TP <NUM> and the mBIST <NUM> as a source of the test signals and provide the test signals to the chatnnel interface blocks CIF_A 32a, CIF_B 32b,. and CIF_H <NUM>.

In <FIG>, the terminals, such as the DT <NUM>, the AT <NUM>, the TCT <NUM>, the PT <NUM> and the TT <NUM> represented by circles may be formed by micro bump electrodes, for example. The test pad TP <NUM> may be formed by a pad electrode, for example. Each of the DT <NUM>, the AT <NUM>, the TCT <NUM>, the PT <NUM> and the TT <NUM> may include one or more terminals. The TP <NUM> may include one or more pads.

<FIG> is a block diagram of the interface circuit <NUM> in <FIG> including the memory Built-In Self Test (mBIST) circuit <NUM> in the semiconductor device in accordance with an embodiment of the present disclosure. <FIG> shows a connection between mBIST <NUM> of <FIG> and one of the channel interface blocks CIF_A 32a, CIF_B 32b,. and CIF_H <NUM> of <FIG> as an example. The other channel interface blocks may be coupled to the mBIST <NUM> similarly as shown in <FIG>. The interface chip may include a plurality of TSVD[n:<NUM>] <NUM> and corresponding DI/O[n:<NUM>] <NUM>, DT[n:<NUM>] <NUM> and DCEM[n:<NUM>] 39provided with a single channel. Similarly, the interface chip may include a pluratity of TSVA[m:<NUM>] <NUM>, ASO[m:<NUM>] <NUM>, AT[m:<NUM>] <NUM> and ACMP[m:<NUM>] 40provided with a single channel. In <FIG>, "m" is a number of bits for command/address signals and "n" is a number of bits for data signals, and "m" and "n" may be different from each other. The mBIST <NUM> includes an mBIST logic circuit mBISTL <NUM> and a storage area MEM <NUM>. The mBISTL <NUM> may be a control circuit, such as an algorithmic pattern generator (APG), which may control operations of the mBIST <NUM>. The MEM <NUM> may be a single memory circuit. Alternatively, the MEM <NUM> may be a plurality of memory circuits, each of which may perform independent functions individually. For example, the MEM <NUM> may include error catch memories (ECMs) and microcode memories (MCMs). For example, each of the ECMs and the MCMs may include static random access memories (SRAMs). The MCMs may store microcodes. The microcodes may represent test patterns for testing the memory cells of the core chips. The mBISTL <NUM> may perform test operations in accordance with the microcodes. The ECMs may store defective address information during the test operations. For example, the MEM <NUM>, such as the ECMSs and/or the MCMs, can be used as spare cells for repairing defective memory cells in the core chips <NUM> as described later in detail. In some embodiments, the I/F chip <NUM> may further include a read only memory (ROM) to store the microcodes. In another embodiment, initial states of the MCMs in the MEM <NUM> may represent the microcodes.

The mBIST operates during the test operations. The mBIST <NUM> may further operate during the initialization operation and the normal operation. In particular, the mBIST <NUM> detects one or more defective cells among memory cells of core chips <NUM>. Upon detection of the one or more defective cells, the mBIST <NUM> stores address information for the defective cells in one portion of the MEM <NUM>, for example the ECMs and/or MCMs, during the initilization operation. Furthermore, in the normal operation, the mBIST <NUM> uses an other portion of the MEM <NUM>, for example, the ECMs and/or MCMs, to replace the defective cells with the other portion of the MEM <NUM> which serves as spare memory. In other words, the mBIST <NUM> redirects access to the defective cells of the core chips <NUM> to the other portion of the MEM <NUM>,.

In some embodiments, each of the core chips <NUM> may further include a defective address storing circuit, such as anti-fuses and spare memory cells. When the core chips <NUM> include the defective address storing circuit, the other portion of the MEM <NUM> of the I/F chip <NUM> and the spare memory cells of the core chips <NUM> may be used for repairing different defective cells from cach other. In some embodiments, the other portion of the MEM <NUM> of the I/F chip <NUM> may replace the defective cells of the spare memory cells of the core chips <NUM>. The detailed operation of the mBIST <NUM> and the channel interface block <NUM> during each of the test operation, the initialization operation and the normal operation including a read operation or a write operation are described below.

<FIG> is a simplified flow diagram of a test operation process by the mBIS in <FIG> in the semiconductor device in accordance with an embodiment of the present disclosure. For example, the test operation process may be performed by the mBIST before shipping.

In an operation block <NUM>, the mBIST <NUM> may receive the test control signals TCTL externally provided through the test control terminals TCT <NUM>. The test control signals may include a test instruction. In response to the TCTL, the mBISTL <NUM> may execute the microcodes to perform a test operation. In some embodiments, the microcodes may be prestored on the MCMs or a ROM of the I/F chip <NUM> as their initial states. In other embodiments, the MCMs may store the microcodes externally provided. The mBISTL <NUM> may provide test enable signal TEST to the DI/O[n:<NUM>] <NUM> and the ASO[n:<NUM>] <NUM>. The DI/O[n:<NUM>] <NUM> may couple in response to the TEST, the TSVD[n:<NUM>] <NUM> to a BISTDATA node coupled to the DCMP[n:<NUM>] <NUM> and the mBIST <NUM> while decoupling the external data terminal DT[n:<NUM>] <NUM> from the DCMP[n:<NUM>] <NUM> and the mBIST <NUM>. Similarly, the ASO[m:<NUM>] <NUM> may couple, in response to the TEST, the TSVA[m:<NUM>] <NUM> to a BIST command and address node BISTC/A coupled to the ACMP[m:<NUM>] <NUM> and the mBIST <NUM> while decoupling the external access terminal AT[m:<NUM>] <NUM> from the ACMP[m:<NUM>] <NUM> and the mBIST <NUM>. The detailed description of the DI/O[n:<NUM>] <NUM> and the ASO[m:<NUM>] <NUM> will be provided later referring to <FIG> and <FIG>.

In an operation block <NUM>, the mBISTL <NUM> may provide test write data TWDATA[n:<NUM>] to the DI/O[n:<NUM>] <NUM>. The mBISTL <NUM> may provide a test command/address signal TC/A[m:<NUM>] including test write commands and test address information to the ASO[m:<NUM>] <NUM>. Accordingly, the DI/O[n:<NUM>] <NUM> and the ASO[m:<NUM>] <NUM> may perform test write operations on the respective channel. For example, the DI/O[n:<NUM>] may provide the TWDATA[n:<NUM>] as core data COREDATA[n:<NUM>] to the TSVD[n:<NUM>] <NUM>. The ASO[m:<NUM>] <NUM> may provide the TC/A[m:<NUM>] as a core command and address signal COREC/A[m:<NUM>] to the TSVA[m:<NUM>] <NUM>.

After the COREDATA[n:<NUM>] are stored in memory cells designated by the COREC/A[m:<NUM>] in the respective channel of the core chips <NUM>, the mBISTL <NUM> may provide the test command/address signal TC/A[m:<NUM>] test including read commands and test address information to the ASO[m:<NUM>] <NUM> to perform test read operations in an operation block <NUM>. The mBISTL <NUM> may provide a memory control signal MEMCTL including the test address information TA to the MEM <NUM>. Accordingly, the ASO[m:<NUM>] <NUM> may provide the COREC/A[m:<NUM>] including the test read commands and the test address information to the respective channel via the TSVA[m:<NUM>] <NUM>. The respective channel may provide the COREDATA[n:<NUM>] including test read data to the TSVD[n:<NUM>] <NUM> responsive to the COREC/A[m:<NUM>]. The DI/O[n:<NUM>] <NUM> may receive the test read data and provide the test read data to the DCMP[n:<NUM>] <NUM>.

In an operation block <NUM>, the DCMP[n:<NUM><NUM> may compare the test read data with the expected data EXP[n:<NUM>] that is the corresponding test write data provided from the mBISTL <NUM>. The DCMP[n:<NUM>] <NUM> may provide a comparison result DCMR[n:<NUM>] to an error detection circuit PFD <NUM>. If at least one DCMR[n:<NUM>] is indicative of data discrepancy between the test read data and the EXP[n:<NUM>], the PFD <NUM> may provide an active fail detection signal P/F (e.g., at a logic high level) in an operation block <NUM>. If there is no data discrepancy between the test read date and the EXP[n:<NUM>] for all the DCMR[n:<NUM>], the PFD <NUM> may provide inactive P/F (e.g., at a logic low level). In response to the active P/F, the MEM <NUM> may store the corresponding test address information as defective address information in an operation block <NUM>.

After testing the memory cells of the respective channel, determined defective address information stored in the MEM <NUM> may be programed into a defective address storing circuit, for example anti-fuses, of the core chips <NUM> in an operation block <NUM>. The determined defective address information may be read out from the MEM <NUM> to an external tester or an external controller (not shown) before programming in an operation block <NUM>. The programing of the defective address information may be performed by mBISTL <NUM> or eatemally by the tester or the controller.

<FIG> is a simplified flow diagram of a test operation as a part of an initialization operation process performed by the mBIST in the semiconductor device in accordance with an embodiment of the present disclosure. The test operation as the part of the initialization operation process is similar to the test operation before shipping described above except a power on sequence. In an operation block <NUM>, the mBISTL <NUM> may respond to a power on signal PON instead of the TCTL in order to initiate testing of the mamory cells. In some embodiments, the TCTL may be used to initiate testing in an operational block <NUM> that is similar to the operation block <NUM> in <FIG>. In the test operation as the part of the initialization operation process, the programming of the determined defective address information into the defective address storing circuit of the core chips <NUM> may be skipped. Instead, the determined defective address information may be stored in the MEM <NUM> of the I/F chip <NUM> in an operation block <NUM>, after executing the test write in an operation block <NUM>', similar to the operationblock <NUM>, the test read in an operation block <NUM>' similar to the operation block <NUM> and the comparison of the test read data and the expected data EXP[n:<NUM>] in an operation block <NUM>' that is similar to the operation block <NUM>. In an operation block <NUM>, the normal access operation, including a write operation and a read operation, may follow the initialization operation.

In the normal operation, the TEST may be inactive (e.g., at a logic low level). The DI/O[n:<NUM>] <NUM> may couple the TSVD[n:<NUM>] <NUM> to the DT[n:<NUM>] <NUM> until hit signals Hit_R/W beome active (e.g., at a logic high level). The detailed description of the DI/O[n:<NUM>] <NUM> will be provided later referring to <FIG>. An external memory controller (e.g., the memory controller <NUM> of <FIG>) may provide external data signals EXDATA[n:<NUM>] including write data to the DT[n:<NUM>] <NUM>. The external memory controller may also provide an EXC/A[m:<NUM>] signal including a write command and access address information (e.g., write address information) to the AT[m:<NUM>] <NUM>. The ASO[m:<NUM>] <NUM> may provide the EXC/A[m:<NUM>] as the COREC/A[m:<NUM>] to the respective channel. In this embodiment, the ASO[m:<NUM>] <NUM> may further provide the EXC/A[m:<NUM>] on the BISTC/A node to the ACMP[m:<NUM>] <NUM>. The ACMP[m:<NUM>] <NUM> may compare the access address information on the BISTC/A node with the defective address information DEFAIF[m:<NUM>] provided from the MEM <NUM>. The ACMP[m:<NUM>] <NUM> may provide a comparison result ACMR[m:<NUM>] to a hit detection circuit HITD <NUM>. When all ACMR[m:<NUM>] are indicative of a match between the access address information and the DEFAIF[m:<NUM>], the HITD <NUM> may provide a HIT signal to the mBISTL <NUM>. In some embodiments, the MEM <NUM> may provide the DEFAIF[m:<NUM>] to the ACMP[m:<NUM>] <NUM>. The ACMP[m:<NUM>] <NUM> may include latch circuits, for example, which may hold the DEFAIF[m:<NUM>] at least during the normal operation (e.g., the write operation or the read operation). The HIT signal may indicate that the provided address information corresponds to the defective address information. The HIT signal may also indicate a type of the operation (e.g., the write operation). In response to the HIT, the mBIST <NUM> may provide a HIT_W signal to the DI/O[n:<NUM>] <NUM>. Responsive to the HIT_W signal, the DI/O[n:<NUM>] <NUM> provides the EXDATA[n:<NUM>] on the BISTDATA node to the MEM <NUM>. The mBISTL <NUM> may perform the write operation on the MEM <NUM> to store the write date into the MEM. In some embodiments, the mBISTL <NUM> may stop performing a write operation on the respective channel on the core chip <NUM> while the repair operation, such as redirecting the access to the MEM <NUM>, is being performed. When the address information on the BISTC/A node does not correspond to the DEFAIF[m:<NUM>], the DI/O[n:<NUM>] <NUM> may provide the EXDATA[n:<NUM>] to the channel as the COREDATA[n:<NUM>] and the COREDATA[n:<NUM>] are written into the corresponding memory cells of the core chip <NUM>.

The normal read operation is similar to the normal write operation described above except a reading sequence. In the read operation, the mBISTL <NUM> may provide the HIT_R signal in response to the HIT signal provided from the HITD <NUM> when any ACMR[m:<NUM>] is indicative of a match between the access address information (e.g., read address information) and the DEFAIF[m:<NUM>]. Responsive to the HIT_R signal, the DI/O[n:<NUM>] <NUM> may couple the DT[n:<NUM>] <NUM> to the MEM <NUM> through the BISTDATA node. The mBISTL may farther perform the read operation on the MEM <NUM> to provide requested read data from the MEM <NUM>. In some embodiments, the mBISTL <NUM> may control a read latency for the read data. The read data retrieved from the MEM <NUM> may be provided to the DI/O[n:<NUM>] <NUM> via the BISTDATA node The DI/O[n:<NUM>] <NUM> may selectively couple the BISTDATA node to the EXDATA node responsive to the active HIT_R signal, thus the DI/O[n:<NUM>] <NUM> may provide the read data to the DT[n:<NUM>] <NUM>. In some embodiments, the mBISTL <NUM> may stop performing a read operation on the respective channel on the core chip <NUM> while the repair operation, such as redirecting the access to the MEM <NUM> for reading, is being performed. When the address information on the BISTC/A node does not correspond to the DEFAIR[m:<NUM>], the data may be retreived from the memory cells of the respective shannel of core chip <NUM> to the DT[n:<NUM>] <NUM>.

<FIG> is a schematic diagram of the data input/output circuit (DI/O) <NUM> of <FIG>, in accordance with an embodiment of the present disclosure. The DI/O <NUM> is coupled to the EXDATA node. The DI/O <NUM> may include a receiver buffer Rx <NUM>. The receiver buffer Rx <NUM> receives the EXDATA from the DT <NUM> and may further provide the EXDATA to one input node of a selector <NUM>. The selector <NUM> may further receive BISTDATAout on the BISDATA node from the DCMP <NUM> at another input node. The selector <NUM> may further receive the TEST from the mBIST <NUM> at a select node after inversion. The TEST may be active in the test operation and inactive in the normal operation (e.g., a write operation, a read operation, etc.). If the TEST is inactive, the selector <NUM> may provide the EXDATA to a buffer circuit <NUM>. If the TEST is active, the selector <NUM> may provide the BISTDATAout from the BISTDATA node to the buffer circuit <NUM>. For example, the buffer circuit <NUM> may be a tristate buffer. An input node of the buffer circuit <NUM> may receive a signal from the selector <NUM>. An enable input node of the buffer circuit <NUM> may receive a write enable signal CORE_W, indicative of enabling writing data to the core chips <NUM>. For example, the CORE_W may be provided as a portion of the COREC/A by the ASO <NUM> in response to a write command. The buffer circuit <NUM> may provide the signal from the selector <NUM> as the COREDATA when the CORE_W is active (e.g., a logic high level). The DI/O <NUM> may include a selector <NUM> and a NAND circuit 56a coupled to one input node of the selector <NUM>. The NAND circuit 56a may receive a HIT_W signal and the signal from the selector <NUM>. The NAND circuit 56a may provide the signal from the selector <NUM> to the one input node of the selector <NUM> responsive to the active HIT_W signal. The selector <NUM> may have another input node that may receive the output signal of the buffer circuit <NUM> provided as the COREDATA. The selector <NUM> may further receive the TEST from the mBIST <NUM> at a select node after inversion. When the TEST is active, the selector <NUM> may provide the signals in parallel from the selector <NUM> via the buffer circuit <NUM>, the same data as the COREDATA as BISTDATAin through the BISTDATA node to the DCMP <NUM>. When the HIT_W is active while the TEST is inactive, the selector <NUM> may provide the EXDATA as the BISTDATAin through the BISTDATA node to the BCMP <NUM>. In the normal write operation without defective address information, the TEST and the HIT_W both are inactive. Thus, no data may be provided from the selector <NUM>. Thus, merely the EXDATA may be provided as the COREDATA through the selector <NUM> and the buffer circuit <NUM>.

A selector <NUM> may receive the BISTDATAout and the COREDATA. The selector <NUM> may further receive the HIT_R at a select node from the mBIST <NUM>. The selector <NUM> may provide the BISTDATAout if the HIT_R is active. The selector <NUM> may further provide the COREDATA if the HIT_R is inactive. A transmitter buffer <NUM> may provide the output signal in series as the EXDATA.

<FIG> is a schematic diagram of the access signal output circuit (ASO) <NUM> of <FIG>, in accordance with an embodiment of the present disclosure. The ASO <NUM> may include a receive buffer Rx <NUM>. The receiver buffer Rx <NUM> receives the EXC/A from the AT <NUM>. The selector <NUM> may further receive the TC/A from the mBIST <NUM> at another input node. The selector <NUM> may further receive the TEST from the mMBIST <NUM> at a select node. The TEST may be active in the test operation and inactive in the normal operation. If the TEST is inactive, the selector <NUM> may provide the EXC/A as the COREC/A. If the TEST is active, the selector <NUM> may provide the TC/A as the COREC/A. An AND circuit <NUM> may receive output signals of the selector <NUM>. The AND circuit <NUM> may further receive the TEST from the mBIST <NUM> after inversion. The TEST after the inversion become inactive responsive to the active TEST, and the BISTC/A node becomes inactive. The AND circuit <NUM> may provide the EXC/A received from the selector <NUM> responsive to the inactive TEST to the BISTC/A.

<FIG> are schematic diagrams of a portion of the storage area MEM <NUM> of <FIG>, in accordance with an embodiment of the present disclosure. For example, the MEM <NUM> may include error catch memories (ECMs) <NUM>. In the test operation, the ECMs <NUM> may receive test address information TA included in the MEMCTL and the fail signal P/F. The ECMs <NUM> may store the TA as failure information including defective address information, responsive to the active fail signal P/F. In the normal operation, the ECMs <NUM> may have a plurality of portions, including a portion 71a and a portion 71b. The portion 71a of the plurality of portions of ECMs <NUM> may store the failure information. The failure information may be detected and stored during the initialization operation, as earlier described. The defective address information DEFAIF may be provided from the portion 71a to a corresponding ACMP <NUM>. The portion 71b of the plurality of portions of ECMs <NUM> may include spare memory cells that may replace defective memory cells of the core chips <NUM> addressed by the failure information. The portion 71b of the plurality of portions of ECMs <NUM> may receive a control signal R/WCTL in the MEMCTL indicative of the read operation or the write operation. The portion 71b may include one or more spare memory cells that may store data from the BISTRATA node responsive to the TA and the R/WCTL indicative of the write operation, in the write operation. The portion 71b may provide data from the one or more spare memory cells to the BISTDATA node responsive to the TA and the R/WCLTL indicative of the read operation, in the read operation.

<FIG> is a schematic diagram of a portion of the MEM of <FIG>, in accordance with an embodiment of the present disclosure. In this embodiment, the ECMs <NUM> may further include a page buffer PB <NUM>, which may buffer data between the spare memory cells in the portion 71b and the DI/O <NUM>. The PB <NUM> may include a plurality of flip-flops, for example, which may provide access speed higher than access speed of the ECMs <NUM>.

<FIG> is a schematic diagram of a portion of the MEM of <FIG>, in accordance with an embodiment of the presunt disclosure. In this embodiment, thie ECMs <NUM> may further include anti-fuses AF <NUM> to permanently store the failure information.

<FIG> is a block diagram of the I/F chip <NUM> including a memory Built-In Self Test (mBIST) circuit <NUM> in the semiconductor device in accordance with an embodiment of the present disclosure. Description of components corresponding to components included in and previously described with reference to <FIG> will not be repeated. Unlike the I/F chip of <FIG>, the HITD <NUM>' may control read and write operations on the MEM <NUM>' instead of the mBISTL <NUM>'. The HITD <NUM>' may provide a portion of the MEMCTL signals, such as the TA and the R/WCTL to the MEM <NUM>', when all ACMR[m:<NUM>] are indicative of a match between the access address information (e.g., read address information) and the DEFAIF[m:<NUM>]. In this example, the HITD <NUM>' may directly provide the HIT_R and the HIT_W to the DI/O[n:<NUM>] <NUM>' instead of providing the HIT to the mBISTL <NUM>' and having the mBISTL <NUM>' providing the HIT_R and the HIT_W.

<FIG> is a schematic diagram of one core chip of the plurality of core chips <NUM> in the semiconductor device in accordance with an embodiment of the present disclosure. The one core chip may include an access control circuit AC <NUM>, a memory cell array MA <NUM>, a spare memory cell array SMA <NUM> and a defective address storing circuit AF <NUM>. For example, the defective address storing circuit AF <NUM> may include anti fuses. In some embodiments, memory cells in the MA <NUM> and memory cells in the SMA <NUM> may be different in type from the memory cells in the MEM <NUM> of the I/F chip <NUM>. For example, the memory cells in the MA <NUM> and the memory cells in the SMA <NUM> may be DRAM memory cells. The SMA may include a plurality of spare memory cells to replace the defective memory cells in the memory cell array as described earlier. The AF <NUM> may store failure information, including defective address information. As described above, the MEM <NUM> of the I/F chip <NUM> may also store defective address information. The defective address information stored in the MEM <NUM> of the I/F chip <NUM> and the defective address information stored in the AF <NUM> of each core chip <NUM> may be different from each other. In some embodiments, the defective address information detected during a test operation may be stored into the AF <NUM> of each core chip <NUM> while the defective address information detected during an initialization operation may be stored into the MEM <NUM> of the I/F chip <NUM>. In some embodiments, the AF <NUM> may store the defective address information for memory cells in the MA <NUM> on the same core chip <NUM>, while the MEM <NUM> of the I/F chip <NUM> may store the defective address information for cells placed in any core chip <NUM> in the semiconductordevice. The AC <NUM> may perform read and write operations on the MA <NUM> in response to the COREC/A via the TSVA <NUM> and the COREDATA via the TSVD <NUM>. The AC <NUM> may access memory cells in SMA <NUM> when the COREC/A includes the access address information that corresponds with one or more addresses included of the defective address information in DEFADDC provided from the AF <NUM>.

<FIG> is a block diagram of the I/F chip including a memory Built-In Self Test (mBIST) circuit in the semiconductor device in accordance with an embodiment of the present disclosure. The I/F chip <NUM> may include a command decoder <NUM>, which may be included in the access signal output circuit ASO <NUM> in <FIG>. The command decoder <NUM> may receive command/address signals CA via an input buffer Rx, and may further provide write command information (WriteCom), read command information (ReadCom) and an address to one or more core chips <NUM> through a signal line <NUM> implemented as a through substrate via (TSV) (e.g., TSVA <NUM> in <FIG>). The I/F chip <NUM> may include a controller circuit <NUM> and an mBIST cinuit <NUM>' which includes an mBIST logic circuit <NUM>' and a storage are a MEM <NUM>'. The MEM <NUM>' may include a plurality of memory circuits <NUM> and <NUM>. For example, the plurality of memory circuits <NUM> and <NUM> may be static random access memories (SRAMs) and one memory circuit <NUM> of the plurality of memory circuits <NUM> and <NUM> may include a CAM memory that may function in a contents-addressable-memory (CAM) mode. The controller circuit <NUM> may control the memory circuit <NUM> through a flag memory <NUM>. The controller circuit <NUM> may receive the WriteCom and the ReadCom. The controller circuit <NUM> may also receive HIT signal from a storage area MEM <NUM>'. The controller circuit <NUM> may also receive flag information from a flag memory <NUM>. For example. the flag information include in-use flag information and locked flag information. The in-use flag information may indicate that an area with the CAM mode corresponding to a particular adress provided in thee memory circuit <NUM> is already in use. The locked flag information may indicate that an area in the CAM mode corresponding to a particular address provided in the memory circuit <NUM> is locked and unmodifiable (e.g., already storing the defective address information). The memory circuit <NUM> may provide data stored on the memory circuit <NUM> on a RAMDAT node (e.g., the BISTDATA node in <FIG>). A multiplexer MUX <NUM> and a multiplexer MUX <NUM>, which may function as the DI/O[n:<NUM>] <NUM> in <FIG>, receive the data from the RAMDAT node. <NUM> may receive data read from the core chip <NUM> via a TSV <NUM> (e.g., TSVD <NUM> in <FIG>) via a ReadData node. The MUX <NUM> provides an output signal to a data queue DQ node via an output buffer Tx, responsive to the HIT signal from the memory circuit <NUM>. If the HIT signal is active (e.g., a logic high level) indicative that the RAMDAT is to be provided, the MUX <NUM> may provide the data from the RAMDAT node. The MUX <NUM> may provide the read out data from the core chip <NUM> via the ReadData node if the HIT signal is inactive (e.g., a logic low level) and no replacement data is stored in the MEM <NUM>' for the particular address. The MUX <NUM> receives the data from the RAMDAT node as well as test data from the mBIST logic circuit <NUM>' and provides either the data from the RAMDAT node or the test data as expected data on an EXPDAT (e.g., the EXP in <FIG>) node to a comparator <NUM>, responsive to whether the data is to be matched with the data from the MEM <NUM>' or the test data from the mBIST logic circuit <NUM>' (e.g., the test write data TWDATA in <FIG>). The comparator <NUM> (e.g., the DCMP <NUM> in <FIG>) compares the expected data the EXPDAT node and the ReadData and provides comparison result signal CMPRSLT (e.g., the P/F in <FIG>) to the controller circuit <NUM> and the mBIST logic circuit <NUM>'. Either the controller circuit <NUM> or the mBIST logic circuit <NUM>' may send control signals: (Ctrl) to set the in-use flag information and the locked flag information in the flag memory <NUM>.

In write operations, the controller circuit <NUM> may write an adress provided along with the WriteCom into the memory circuit <NUM> in response to the WriteCom, the in-use flag information, the locked flag information and the HIT signal. For example, the memory circuit <NUM> may store the address in the CAM memory and may further provide an inactive HIT signal to the memory circuit <NUM> and the controller circuit <NUM>, if the address is not stored in the CAM memory in the memory circuit <NUM>. The memory circuit <NUM> may provide an active HIT signal to the memory circuit <NUM> and the controller circuit <NUM>, if the adress is already stored in tie CAM memory in the memory circuit <NUM>. The memory circuit <NUM> may store data provided from the data queue DQ node via an input buffer Rx on a WriteData node, responsive to the HIT signal. For example, the memory circuit <NUM> may store data on the WriteData node in an area addressed by a newly allocated address, if the HIT signal is inactive. The memory circuit <NUM> may store the data on the WriteData node in an area already allocated corresponding to the address, if the HIT signal is active. Data on the WriteData node may be also provided to respective memory cells of the core chip <NUM>. In some embodiments, data on the WriteData node may not be provided to the respective memory cells of the core chip <NUM> if the corresponding address have been held and locked in the CAM memory. The controller circuit <NUM> may prevent writing the address if then in-use flag information or the locked flag information for all addresses in the memory circuit <NUM> may indicate that all of the CAM memory in the memory circuit <NUM> is already in-use or locked and thus unavailable.

<FIG> is a simplified flow diagram of a write operation I/F chip of <FIG>, in accordance with an embodiment of the present disclosure. Upon receiving a write command at the command decoder <NUM> (S1100), the controller circuit <NUM> may provide the address along with the WriteCom to the flag memory <NUM> and the flag memory <NUM> may provide the address to the memory circuit <NUM> on a CAMWE signal. The memory circuit <NUM> may determine whether the address is already stored in the CAM memory and may further provide the HIT signal to the controller circuit <NUM> and the memory circuit <NUM>. The memory circuit <NUM> may check whether the HIT signal is active (S1101) and may further store the data on the WriteData node if the HIT signal is active (S1106). If the HIT signal is not active "N", the controller circuit <NUM> may check the in-use flag information and the locked flag information (S1102). If the in-use flag information and the locked flag information are indicative that all the CAM memory is used (CAM overflow), the controller circuit <NUM> may skip writing the address in the CAM memory in the memory circuit <NUM> and may end the writing operation (S1107).

Optionally, the controller circuit <NUM> may skip writing the address in the CAM memory in the memory circuit if the address is related to system defined conditions (S1103). For example, the system defined conditions may include an address sampling. The address sampling condition may include random sampling, the addresses which tend to be accessed frequently, the addresses in a same area (e.g., the same core, the same channel, etc.) having a frequent repair history and thus a higher deficiency rate than other area, or the adresses in a predetermined range due to system configuration (e.g. having a small margin). Alternatively, it is possible to have an. additional counter having a count of the additional counter may be changed at a predetermined interval to point a next address in the core dies to be stored for checking the deficiency. Alternatively, it is possible to write the address to overwrite an oldest address stored in the CAM memory (after skipping the step S1102). Depending on the steps S1102 and S1103, the controller circuit <NUM> may write the address to the CAM memory (S1105) and set in-use flag information of the address. The memory circuit <NUM> stores the data on the WriteData node along with the adress and the WriteCom (S1106) if the HIT signal is active or if the controller circuit <NUM> writes the adress to the CAM memory and the write operation is completed (S1107).

In read operations, the memory circuit <NUM> may compare the address provided along with the ReadCom with addresses stored in the CAM memory. The memory circuit <NUM> may provide the active HIT signal to the memory circuit <NUM> if the address is found in the addresses in the CAM memory. The multiplexer MUX <NUM> may provide either the data on the RAMDAT node or ReadData from the core chip <NUM> via the TSV <NUM> to the data queue DQ via an output buffer Tx, responsive to the active HIT signal. As described earlier, the comparator <NUM> may compare the ReadData with the data on the RAMDAT node and may further provide the CMPRSLT signal The controller <NUM> may control the flag memory <NUM> to change the in-use flag information of the address inactive (e.g., "<NUM>''). if the CMPRSLT signal indicates that the data on the RAMDAT node match the ReadData. Thus, the CAM memory which has stored the address is freed and becomes available to store a new address. If the CMPRSLT signal indicates that the data on the RAMDAT node do not match the ReadData, locked flag information of the adress active (e.g., "<NUM>") to prevent the CAM memory of the adress from overwriting a new adress. As a result, the CAM memory may store the adress as the defect adress information and the read/write operation of the adress in the core chip <NUM> may be redirected permanently to the memory circuit <NUM> in the MEM <NUM>'.

<FIG> is a simplified flow diagram of a read operation in the I/F chip of <FIG>, in accordance with an embodiment of the present disclosure. Upon receiving a read command at the command decoder <NUM> (<NUM>), the controller circuit <NUM> may provide the address along with the ReadCom to the flag memory <NUM> and the flag memory <NUM> may provide the address to the memory circuit <NUM> on a CAMWE signal. The memory circuit <NUM> may determine whether the adress is already stored in the CAM memory and may further provide the <NUM> sipal to the controler sing <NUM>, the memory circuit <NUM> and the multiplexer MUX <NUM>. The MUX <NUM> may check whether the HIT signal is active (S1111) and may further provide the ReadData from the core chip <NUM> via the TSV <NUM>, if the HIT signal is inactive "N" (S1112) and the write operation is completed (S1118). If the HIT signal is active "Y", the MUX <NUM> may provide the data on the RAMDAT node to the data queue DQ (S1113). The comparator <NUM> may compare the ReadData with the data on the RAMDAT node with and may further provide the CMPRSLT signal (S <NUM>). The controller <NUM> may controll the flag memory <NUM> to change the in-use flag information of the adress inactive (e. g, "<NUM>"), if the CMPRSLT signal indicate that the data on the RAMDAT node match the ReadData (S1116) and the read operation is completed (S1118). Thus, the CAM memory which has stored the address is freed and becomes available to store a new address. If the CMPRSLT signal indicates that the data on the RAMDAT node do not match the ReadData, the flag memory <NUM> may set locked flag information of the address active (e.g., "<NUM>") to prevent the CAM memory of the address from overwriting a new address (S <NUM>) and the read operation is completed (S1118).

<FIG> is a block diagram of the I/F chip in the semiconductor device in accordance with an embodiment of the present disclosure. Description of components corresponding to components included in and previously described with reference to <FIG> will not be repeated. The I/F chip <NUM> may include a storage area MEM <NUM> including a plurality of memory circuits <NUM> and <NUM>. For example, the plurality of memory circuits <NUM> and <NUM> may be static random access memories (SRAMs) and one memory circuit <NUM> of the plurality of memory circuits <NUM> and <NUM> may include a CAM memory that may function in a contents-addressable-memory (CAM) mode. The controller circuit <NUM> may control the memory circuit <NUM> through a flag memory <NUM>. The controller circuit <NUM> may receive a WriteCom and a ReadCom. The controller circuit <NUM> may also receive HIT signal from a storage area MEM <NUM>. The controller circuit <NUM> may also receive flag infonnation from a flag memory <NUM>. For example, the flag information may include in-use flag information and locked flag information. The in-use flag information may indicate that an area with the CAM mode corresponding to a particular address provided in the memory circuit <NUM> is already in use. The locked flag information may indicate that an area in the CAM mode corresponding to a particular address provided in the memory circuit <NUM> is locked and unmodifiable (e.g., already storing the defective address information). The memory circuit <NUM> may provide data stored on the memory circuit <NUM> on a RAMDAT node (e.g., the BISTDATA node in <FIG>). A multiplexer MUX <NUM> and a multiplexer MUX <NUM>, which may function as the DI/O[n:<NUM>] <NUM> in <FIG>, receive the data from the RAMDAT node. The MUX <NUM> may receive data read from the core chip <NUM> via a TSV <NUM> (e.g., TSVD <NUM> in <FIG>) via a ReadData node. The MUX <NUM> provides an output signal to a data queue DQ node via an output buffer Tx, responsive to the HIT signal from the memory circuit <NUM>. If the HIT signal is active (e.g., a logic high level) indicative that data on the RAMDAT node is to be provided, the MUX <NUM> may provide the data from the RAMDAT node. The MUX <NUM> may provide the read out data from the core chip <NUM> via the ReadData node if the HIT signal is inactive (e.g., a logic low level) and no replacement data is stored in the memory circuit <NUM> from the particular adress. The MUX <NUM> receives the data from RAMDAT node as well as test data from the memory circuit <NUM> and provides either the data from the RAMDAT node or the test data as expected data on an EXPDAT (e.g., the EXP in <FIG>) node to a comparator <NUM>, responsive to whether the data is to be matched with the test data from the memory circuit <NUM>. The comparator <NUM> (e.g., the DCMP <NUM> in <FIG>) compares the expected data the EXPDAT node and data read from the core chip <NUM> on the ReadData node and provides comparison result signal CMPRSLT (e.g., the P/F in <FIG>) to the controller circuit <NUM>. The controller circuit <NUM> may send control signals (Ctrl) to set the in-use flag information and the locked flag information in the flag memory <NUM>.

An I/F chip may include an error correction code (ECC) function. <FIG> is a block diagram of the I/F chip in the semiconductor device in accordance with an embodiment of the present disclosure. Description of components corresponding to components included in and previously described with reference to <FIG> will not be repeated. The I/F chip <NUM> may include a storage area MEM <NUM> including a plurality of memory circuits <NUM> and <NUM>. For example, the plurality of memory circuits <NUM> and <NUM> may be static random acces memories (SRAMs) and one mmemory circuit <NUM> of the plurality of memory circuit <NUM> and <NUM> may include a CAM memory that may function in a contents-addressable-memory (CAM) mode. The memory circuit <NUM> may include two ports Portl <NUM> and Port2 <NUM>. The port Port1 <NUM> may receive an address from a command decoder <NUM> for accessing the CAM memory. The port Port2 <NUM> may receive a control signal CAMWE and an error address signal ERRADD. The memory circuit <NUM> may include two ports Port1 <NUM> and Port2 <NUM>. The port Port1 <NUM> may receive a WriteCom from the command decoder <NUM> and may further receive data on a WriteData node from a data queue DQ node in a write operation. The port Port1 <NUM> may receive a ReadCom from the command decoder <NUM>. The port Port2 <NUM> may receive the control signal CAMWE and a read data signal REDDAT. The controller circuit <NUM> may provide a control signal Ctrl to control the memory circuit <NUM> through a flag memory <NUM>. The flag memory <NUM> may provide the control signal CAMWE to the port Port2 <NUM> of the memory circuit <NUM> and the plurality of memory circuit <NUM> and <NUM>. The controller circuit <NUM> may receive HIT signal from the storage area MEM <NUM>. The controller circuit <NUM> may also receive flag information from the flag memory <NUM>. For example, the flag information may include in-use flag information and locked flag information. The in-ue flag information may indicate that a are with the: CAM mode corresponding to a particular address provided. in the memory circuit <NUM> is already in use. The locked flag information may indicate that an area in the CAM mode corresponding to a particular address provided in the memory circuit <NUM> is locked and unmodifiable (e.g., already storing the defective address information). The memory circuit <NUM> may provide data stored on the memory circuit <NUM> on a RAMDAT node (e.g., the BISTDATA node in <FIG>) through the port Port1 <NUM>. A multiplexer MUX <NUM>, which may function as the DI/O[n:<NUM>] <NUM> in <FIG>, receive the data from the RAMDAT node.

The I/F die <NUM> may include a write error correction circuit (WECC) <NUM> which may generate a Write error correction code (WriteECC) based on data on the WriteData node during a write operation and provide the ECC on a WriteECC node to the core chip <NUM> with the data on the WriteData node. The I/F die <NUM> may include read error correction circuit (RECC) <NUM> that may receive the data on the ReadData node and a Read error correction code (ReadECC) from the core chip <NUM> via a TSV <NUM> (e.g., TSVD <NUM> in <FIG>), check if there is an error based on the ReadECC and the data read from the core chip <NUM> on the ReadData node, and may further correct the error, if any during read operations. The RECC <NUM> circuit may activate an ERR signal if there is the error, regardless of whether error is correctable or uncorrectable.

The MUX <NUM> may receive data REDDAT which is a data signal from the RECC <NUM> and the data on the RAMDAT node. The MUX <NUM> provides an output signal to the data queue DQ node via an output buffer Tx, responsive to the HIT signal from the memory circuit <NUM>. If the HIT signal is active (e.g., a logic high level) indicative that data on the RAMDAT node is to be provided, the MUX <NUM> may provide the data from the RAMDAT node. The MUX <NUM> may provide the read out data REDDAT which may be after the error correction at the RECC <NUM>, if the HIT signal is inactive (e.g., a logic low level) and no replacement data is stored in the memory circuit <NUM> for the particular address. The I/F die <NUM> may also include a first-in-first-out memory (FIFO) <NUM> which may receive the adress and store the address during read operations responsive to the ReadCom. The FIFO <NUM> provides the address on an ERRADD node to the port Port2 <NUM> of the memory circuit <NUM> responsive to the ERR signal.

<FIG> is a simplified flow diagram of a write operation in the I/F chip of <FIG>, in accordance with an embodiment of the present disclosure. Upon receiving a write command at the command decoder <NUM> (S140), the controller circuit <NUM> may provide the address along with the WriteCom to the flag memory <NUM> and the flag memory <NUM> may provide the address to the plurailty of the memory circuits <NUM> on the CAMWE signal. The memory circuit <NUM> may determine whether the address is already stored in the CAM memory and may further provide the HIT signal to the controller circuit <NUM>, the memory circuit <NUM>. The memory circuit <NUM> may check whether the HIT signal is active (S1401) and may further store the data on the WriteData node if the HIT signal is active (S1402) and end the writing opergdon (S1403), If the HIT signal is not active "N", the controller circuit <NUM> may skip writing the data and end the writing operation (S1403).

<FIG> is a simplified flow diagram of a read operation in the I/F chip of <FIG>, in accordance with an embodiment of the present disclosure. Upon receiving a read command at the command decoder <NUM> (S1410), the controller circuit <NUM> may provide the address along with the ReadCom to the flag memory <NUM> and the flag memory <NUM> may provide the address to the memory circuit <NUM> on the CAMWE signal. The memory circuit <NUM> may determine whether the address is already stored in the CAM memory and may further provide the HIT signal to the controller circuit <NUM>, the memory circuit <NUM> and the multiplexer MUX <NUM>. The MUX <NUM> may check whether the HIT signal is active (S1411). If the HIT signal is active "Y", the MUX <NUM> may provide the data on the RAMDAT node to the data queue DQ (S1412). and the read operation is completed (S1417). The MUX <NUM> may provide the data on the REDDAT node from the RECC <NUM> to the data queue DQ (S1413), if the HIT signal is inactive "N". The controller circuit <NUM> may check whether the ERR signal from the RECC <NUM> is active (S1414). If the ERR signal from the RECC <NUM> is not active "N", the read operation is completed (S1417). If the ERR signal is active "Y", the controller circuit <NUM> may check the in-use flag information and the locked flag information, responsive to the ERR signal (S1415). If the in-use flag information and the locked flag information are indicative that all the CAM memory is used (CAM overflow-"Y"), the controller circuit <NUM> may skip writing the address in the CAM memory in the memory circuit <NUM> and may end the writing operation (S1417). If the CAM memory is available (CAM overflow ="N"), the controller circuit <NUM> may control the plurality of memory circuits <NUM> and <NUM> by providing the CAMWE signal. The memory circuit <NUM> may write the address to the CAM memory from the FIFO <NUM> via the ERRADD node (S1416), responsive to the CAMWE signal. The memory circuit <NUM> may store the data on the REDDAT node (S1416). The controller circuit <NUM> may further set in-use flag information of the address (S1416). After the step in S1416, the read operation is completed (S1417). Thus, it is possible to provide remedy with the CAM memory based on the result of ECC function.

Logic levels of signals used in the embodiments described the above are merely examples. However, in other embodiments, combinations of the logic levels of signals other than those specifically described in the present disclosure may be used without departing from the scope of the present disclosure.

Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications to those embodiments. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substitued for one another within the scope of the invention as defined in the appended claims.

Claim 1:
An apparatus comprising:
at least one memory chip (<NUM>) comprising a plurality of first memory cells; and
an interface chip (<NUM>) coupled to the at least one memory chip (<NUM>) and comprising a control circuit (<NUM>) and a storage area (<NUM>),
wherein the control circuit (<NUM>) is configured to detect one or more defective memory cells of the plurality of first memory cells of the at least one memory chip (<NUM>) and to store first defective address information of the one or more defective memory cells of the plurality of first memory cells into a portion of the storage area (<NUM>) during a test operation of the interface chip (<NUM>),
characterised in that
wherein an other portion of the storage area (<NUM>) serves as spare memory to replace the one or more defective memory cells during a normal operation of the interface chip and
wherein the interface chip (<NUM>) is configured to access the other portion of the storage area (<NUM>) in place of the at least one memory chip (<NUM>) responsive, at least in part, to an access request, when the access request has been provided with the first defective address information with respect to the one or more defective memory cells of the plurality of first memory cells.