Patent Description:
There is known a light receiving element that is configured to convert received light into an electric signal by photoelectric conversion to output the electric signal. As one of such light receiving elements, a single photon avalanche diode (hereinafter, referred to as SPAD) is known that is configured to obtain a large current in response to incidence of one photon by avalanche multiplication. Use of this characteristic of the SPAD makes it possible to detect incidence of one photon with high sensitivity.

The outline of a photon detection operation by the SPAD will be described. For example, a current source to which power supply voltage Vdd is supplied and whose output current is controlled on the basis of reference voltage Vref is connected to a cathode of the SPAD. An anode of the SPAD gives a large negative voltage (-Vbd) at which the avalanche multiplication occurs. When the photon is incident on the SPAD in this state, the avalanche multiplication begins, a current flows from the cathode of the SPAD toward the anode, a voltage drop occurs in the SPAD with the current flow, and the avalanche multiplication is stopped when an anode-cathode voltage drops to the voltage (-Vbd) (quenching operation). Then, the SPAD is charged with a current (referred to as a recharge current Id) from the current source, and the SPAD returns to the state before incidence of the photon (recharging operation).

Patent Literature <NUM>: <CIT> <CIT> discloses a photo detecting circuit including an avalanche photodiode and noise elimination method. A sampling circuit performs binary sampling so as to decide the signal by using two decision values. The reverse-bias signal is slightly delayed relatively to the reverse-bias-pulse timing signal due to a circuit delay inside the power supply circuit.

<CIT> discloses an Integrated receiving circuit for radiofrequency signals. A transistor is utilized to perform active recharge after an avalanche has been detected by an avalanche detection circuit.

<CIT> discloses a distance measuring apparatus for improving precision of ranging. The light-receiving section is of the avalanche type.

<CIT> discloses a solid state image sensor. A CMOS image sensor has a stack structure that stacks the pixel array unit and the circuit sections.

There is known active quenching/recharging for forcibly performing the quenching operation and the recharging operation of the SPAD according to control. In the active quenching/recharging, delay amounts of the quenching operation and the recharging operation to voltage drop generation timing of the SPAD can be determined by adjusting a drive force or load capacity of an inverter chain.

The drive force and the load capacity of the inverter chain are analog elements and susceptible to process/voltage/temperature (PVT) variation, external noise, or the like.

An object of the present disclosure is to provide a measurement device, a distance measurement device, an electronic device, and a measurement method that are configured to more stably control an operation of a light receiving element.

For solving the problem described above, a measurement device according to one aspect of the present disclosure has a light receiving element that has flow of current caused by an avalanche multiplication caused according to a photon incidence while being charged to a predetermined potential and is returned to the charged state by a recharge current; a detection unit that is configured to detect the current and invert an output signal of the measurement device when the current crosses a threshold value; a delay unit that is configured to delay timing of the inversion detected by the detection unit, according to a clock; and a control unit that is configured to control an operation of the light receiving element, based on the timing of the inversion delayed by the delay unit.

Preferred embodiments thereof are defined in the dependent claims. Other aspects are defined in independent claims <NUM> to <NUM>.

Embodiments of the present disclosure will be described in detail below with reference to the drawings. Note that in the following embodiments, the same portions are denoted by the same reference numerals and symbols, and redundant description thereof will be omitted.

The present disclosure is suitable for use in a technology detecting a photon. Prior to the description of the embodiments of the present disclosure, for ease of understanding, as one of technologies applicable to the embodiments, a technology performing distance measurement by detecting the photon will be described. As a distance measurement method in this case, a direct time of flight (ToF) method is applied. The direct ToF method is a method of measuring a distance on the basis of a time difference between light emission timing and light reception timing, in which light emitted by a light source is reflected from an object to be measured and the reflected light is received by a light receiving element.

The distance measurement by the direct ToF method will be schematically described with reference to <FIG> is a diagram schematically illustrating the distance measurement by the direct ToF method applicable to the embodiments. A distance measurement device <NUM> includes a light source unit <NUM> and a light receiving unit <NUM>. The light source unit <NUM> is, for example, a laser diode, and is driven to emit pulsed laser light. Light emitted from the light source unit <NUM> is reflected from an object <NUM> to be measured and the reflected light is received by the light receiving unit <NUM>. The light receiving unit <NUM> includes a light receiving element configured to convert light into an electric signal by photoelectric conversion, and outputs a signal according to the received light.

Here, the time (light emission timing) at which the light source unit <NUM> emits light is defined as time tem, and the time (light reception timing) at which the light receiving unit <NUM> receives the reflected light obtained by reflecting the light emitted by the light source unit <NUM> from the object <NUM> to be measured is defined as time tre. Assuming that a constant c is light velocity (<NUM> × <NUM><NUM> [m/sec]), a distance D between the distance measurement device <NUM> and the object <NUM> to be measured is calculated by the following formula (<NUM>).

The distance measurement device <NUM> repeatedly performs the process described above a plurality of times. The light receiving unit <NUM> may include a plurality of light receiving elements to calculate the distances D on the basis of light reception timing at which the reflected light is received by the light receiving elements. The distance measurement device <NUM> classifies time periods tm (referred to as light receiving time periods tm) from the time tem indicating the light emission timing to the light reception timing at which the light is received by the light receiving unit <NUM>, on the basis of intervals (bins) and generates a histogram.

Note that the light received by the light receiving unit <NUM> during the light receiving time period tm is not limited to the reflected light obtained by reflecting the light emitted from the light source unit <NUM> by the object to be measured. For example, ambient light around the distance measurement device <NUM> (light receiving unit <NUM>) is also received by the light receiving unit <NUM>.

<FIG> is a diagram illustrating an example of a histogram based on the light receiving time of the light receiving unit <NUM> applicable to the embodiments. In <FIG>, the horizontal axis represents bins and the vertical axis represents the frequency in each bin. The bin is obtained by classifying the light receiving time periods tm into predetermined unit time intervals d. Specifically, bin #<NUM> is <NUM> ≤ tm < d, bin #<NUM> is d ≤ tm < <NUM> × d, bin #<NUM> is <NUM> × d ≤ tm < <NUM> × d,. , bin #(N - <NUM>) is (N - <NUM>) × d ≤ tm < (N - <NUM>) × d. When an exposure time of the light receiving unit <NUM> is time tep, tep = N × d.

The distance measurement device <NUM> counts the number of the light receiving time periods tm acquired, on the basis of each bin, obtains a frequency <NUM> in each bin, and generates the histogram. Here, the light receiving unit <NUM> also receives light other than the reflected light obtained by reflecting the light emitted by the light source unit <NUM>. An example of such light other than the reflected light as a target includes the ambient light described above. In the histogram, a portion indicated by a range <NUM> includes an ambient light component of the ambient light. The ambient light is light incident on the light receiving unit <NUM> at random, and becomes noise to the reflected light as the target.

Meanwhile, the reflected light as the target is light that is received according to a specific distance, and shown as an active light component <NUM> in the histogram. A bin corresponding to the peak frequency in the active light component <NUM> is a bin corresponding to the distance D to the object <NUM> to be measured. Acquiring a representative time of the bin (e.g., a time at the center of the bin), as the time tre described above, the distance measurement device <NUM> is configured to calculate the distance D to the object <NUM> to be measured according to formula (<NUM>) described above. In this manner, use of a plurality of light reception results makes it possible to perform appropriate distance measurement against random noise.

<FIG> is a block diagram illustrating an example of a configuration of an electronic device using the distance measurement device according to the embodiments. In <FIG>, an electronic device <NUM> includes a distance measurement device <NUM>, a light source unit <NUM>, a storage unit <NUM>, a control unit <NUM>, and an optical system <NUM>.

The light source unit <NUM> corresponds to the light source unit <NUM> described above, has a laser diode, and is driven to emit, for example, pulsed laser light. To the light source unit <NUM>, a vertical cavity surface emitting laser (VCSEL) that emits laser light as an area light source is applicable. In addition to this, a configuration using an array in which laser diodes are arranged on a line to scan laser light emitted from the laser diode array in a direction perpendicular to the line may be applied to the light source unit <NUM>. Furthermore, a configuration using a laser diode as a single light source to scan laser light emitted from the laser diode in a horizontal and vertical directions may be applied.

The distance measurement device <NUM> includes a plurality of light receiving elements corresponding to the light receiving unit <NUM> described above. The plurality of light receiving elements is arranged, for example, into a two-dimensional lattice to form a light receiving surface. The optical system <NUM> guides light incident from the outside to the light receiving surface included in the distance measurement device <NUM>.

The control unit <NUM> controls the overall operations of the electronic device <NUM>. For example, the control unit <NUM> supplies a light emission trigger that triggers light emission of the light source unit <NUM>, to the distance measurement device <NUM>. The distance measurement device <NUM> causes the light source unit <NUM> to emit light at timing based on the light emission trigger, and stores the time tem indicating the light emission timing. Furthermore, the control unit <NUM> sets a pattern for distance measurement for the distance measurement device <NUM>, for example, in response to an instruction from the outside.

The distance measurement device <NUM> counts the number of time information (light receiving time periods tm) acquired that indicates timing at which light is received on the light receiving surface, within a predetermined time range, obtains the frequency in each bin, and generates the histogram described above. The distance measurement device <NUM> further calculates the distance D to the object to be measured, on the basis of the generated histogram. Information indicating the calculated distance D is stored in the storage unit <NUM>.

<FIG> is a block diagram illustrating an example of a more detailed configuration of the distance measurement device <NUM> applicable to the embodiments. In <FIG>, the distance measurement device <NUM> includes a pixel array unit <NUM>, a distance measurement processing unit <NUM>, a pixel control unit <NUM>, a general control unit <NUM>, a clock generation unit <NUM>, a light emission timing control unit <NUM>, and an interface (I/F) <NUM>. The pixel array unit <NUM>, the distance measurement processing unit <NUM>, the pixel control unit <NUM>, the general control unit <NUM>, the clock generation unit <NUM>, the light emission timing control unit <NUM>, and the interface (I/F) <NUM> are configured to be arranged on one semiconductor chip.

In addition to this, the distance measurement device <NUM> may have a configuration in which a first semiconductor chip and a second semiconductor chip are stacked. In this configuration, for example, it is considered that part (such as the light receiving unit) of the pixel array unit <NUM> is arranged on the first semiconductor chip and the other part included in the distance measurement device <NUM> is arranged on the second semiconductor chip.

In <FIG>, the general control unit <NUM> controls the overall operations of the distance measurement device <NUM>, for example, according to a program incorporated in advance. Furthermore, the general control unit <NUM> is also configured to execute control according to an external control signal supplied from the outside. The clock generation unit <NUM> generates one or more clock signals used in the distance measurement device <NUM>, on the basis of a reference clock signal supplied from the outside. The light emission timing control unit <NUM> generates a light emission control signal indicating the light emission timing according to a light emission trigger signal supplied from the outside. The light emission control signal is supplied to the light source unit <NUM> and also supplied to the distance measurement processing unit <NUM>.

The pixel array unit <NUM> includes a plurality of pixels <NUM>, <NUM>,. arranged into a two-dimensional lattice and each including the light receiving element. The operation of each pixel <NUM> is controlled by the pixel control unit <NUM> in response to an instruction from the general control unit <NUM>. For example, the pixel control unit <NUM> is configured to control reading of a pixel signal from each pixel <NUM>, for each block including (p × q) pixels <NUM> of p pixels in the row direction and q pixels in the column direction. Furthermore, the pixel control unit <NUM> is configured to scan each pixel <NUM> in the row direction and further in the column direction, and read the pixel signal from each pixel <NUM> for each block. In addition to this, the pixel control unit <NUM> is configured to control the pixels <NUM> independently. Furthermore, the pixel control unit <NUM> is configured to set the pixels <NUM> included in the target region being a predetermined region of the pixel array unit <NUM>, as target pixels <NUM> from which the pixel signal is to be read. Furthermore, the pixel control unit <NUM> is also configured to scan a plurality of rows (a plurality of lines) collectively, further scan the rows in the column direction, and read the pixel signals from the pixels <NUM>.

Note that, in the following description, scanning refers to processing in which the light source unit <NUM> (see <FIG>) is caused to emit light, and reading of a signal Vpls according to light received from each pixel <NUM> is continuously performed for the respective pixels <NUM> designated as a scanning target in one scan area. Light emission and reading can be performed a plurality of times in a single scan.

The pixel signal read from each pixel <NUM> is supplied to the distance measurement processing unit <NUM>. The distance measurement processing unit <NUM> includes a conversion unit <NUM>, a generation unit <NUM>, and a signal processing unit <NUM>.

The pixel signal read from each pixel <NUM> and output from the pixel array unit <NUM> is supplied to the conversion unit <NUM>. Here, the pixel signals are asynchronously read from the pixels <NUM> and supplied to the conversion unit <NUM>. In other words, the pixel signal is read and output from the light receiving element according to timing at which light is received in each pixel <NUM>.

The conversion unit <NUM> converts each pixel signal supplied from the pixel array unit <NUM> into digital information. In other words, each pixel signal supplied from the pixel array unit <NUM> is output corresponding to timing at which light is received by the light receiving element included in a pixel <NUM> corresponding to the pixel signal. The conversion unit <NUM> converts the supplied pixel signal into the time information indicating the timing.

The generation unit <NUM> generates the histogram on the basis of the time information obtained by converting the pixel signal by the conversion unit <NUM>. Here, the generation unit <NUM> counts the time information on the basis of each unit time interval d set by a setting unit <NUM> and generates the histogram. The histogram generation processing by the generation unit <NUM> will be described in detail later.

The signal processing unit <NUM> performs predetermined arithmetic processing on the basis of data in the histogram generated by the generation unit <NUM>, and calculates, for example, distance information. For example, the signal processing unit <NUM> creates a curve approximation for the histogram on the basis of the data in the histogram generated by the generation unit <NUM>. The signal processing unit <NUM> is configured to detect a peak of the curve obtained by approximation of the histogram to obtain the distance D on the basis of the detected peak.

The signal processing unit <NUM> is configured to perform filter processing on the curve obtained by the approximation of the histogram, when performing the curve approximation of the histogram. For example, the signal processing unit <NUM> is configured to perform low-pass filter processing on the curve obtained by the approximation of the histogram, suppressing a noise component.

The distance information obtained by the signal processing unit <NUM> is supplied to an interface <NUM>. The interface <NUM> outputs, as output data, the distance information supplied from the signal processing unit <NUM> to the outside. For the interface <NUM>, for example, Mobile Industry Processor Interface (MIPI) can be applied.

Note that, in the above description, the distance information obtained by the signal processing unit <NUM> is output to the outside via the interface <NUM>, but the present disclosure is not limited to this example. In other words, histogram data being the data in the histogram generated by the generation unit <NUM> may be output to the outside from the interface <NUM>. In this configuration, information indicating a filter coefficient can be omitted from distance measurement condition information set by the setting unit <NUM>. The histogram data output from the interface <NUM> is supplied to, for example, an external information processing device and processed appropriately.

<FIG> is a diagram illustrating a basic configuration example of the pixel <NUM> applicable to the embodiments. In <FIG>, the pixel <NUM> includes a light receiving element <NUM>, a transistor <NUM> that is a P-channel MOS transistor, and an inverter <NUM>.

The light receiving element <NUM> photoelectrically converts incident light into the electric signal and outputs the electric signal. In each embodiment, the light receiving element <NUM> photoelectrically converts an incident photon (photon) into the electric signal, and outputs a pulse corresponding to the incidence of the photon. In each embodiment, a single photon avalanche diode is used for the light receiving element <NUM>. Hereinafter, the single photon avalanche diode is referred to as SPAD. The SPAD has a characteristic that when a large negative voltage to cause an avalanche multiplication is applied to a cathode, electrons generated in response to incidence of one photon cause the avalanche multiplication, and a large current flows. Use of this characteristic of the SPAD makes it possible to detect incidence of one photon with high sensitivity.

In <FIG>, in the light receiving element <NUM> being the SPAD, the cathode is connected to a drain of the transistor <NUM>, and an anode is connected to a voltage source of negative voltage (-Vbd) corresponding to a breakdown voltage of the light receiving element <NUM>. The transistor <NUM> has a source that is connected to a voltage Ve. The transistor <NUM> has a gate to which a reference voltage Vref is input. The transistor <NUM> is a current source configured to output a current according to the voltage Ve and the reference voltage Vref, from the drain. Such a configuration applies a reverse bias voltage to the light receiving element <NUM>. In addition, a photocurrent flows in a direction from the cathode toward the anode of the light receiving element <NUM>.

More specifically, in the light receiving element <NUM>, when the photon is incident while the voltage (-Vbd) is applied to the anode and charged with a potential (-Vdb), the avalanche multiplication begins, a current flows in a direction from the cathode toward the anode, and a voltage drop occurs with the current flow in the light receiving element <NUM>. Owing to this voltage drop, when an anode-cathode voltage of the light receiving element <NUM> drops to the voltage (-Vbd), the avalanche multiplication is stopped (quenching operation). Thereafter, the light receiving element <NUM> is charged with the current (recharge current) from the transistor <NUM> as the current source, and the light receiving element <NUM> returns to the state before photon incidence (recharging operation).

Here, the quenching operation and the recharging operation are passive operations performed without external control.

A voltage Vs extracted from a connection point between the drain of the transistor <NUM> and the cathode of the light receiving element <NUM> is input to the inverter <NUM>. The inverter <NUM> performs, for example, threshold determination on the input voltage Vs, and inverts an output signal Voiv every time the voltage Vs exceeds a threshold voltage Vth in a positive direction or negative direction.

More specifically, the inverter <NUM> inverts the output signal Voiv at the first timing when the voltage Vs crosses the threshold voltage Vth, in the voltage drop due to the avalanche multiplication in response to the incidence of the photon on the light receiving element <NUM>. Next, the light receiving element <NUM> is charged by the recharging operation, and the voltage Vs increases. The inverter <NUM> inverts the output signal Voiv again at the second timing when the increasing voltage Vs crosses the threshold voltage Vth. A width in a time direction between the first timing and the second timing is an output pulse in response to the incidence of the photon on the light receiving element <NUM>.

This output pulse corresponds to each of the pixel signals asynchronously output from the pixel array unit <NUM> described with reference to <FIG>. In <FIG>, the conversion unit <NUM> converts the output pulse into time information indicating the timing of supply of the output pulse and transmits the time information to the generation unit <NUM>. The generation unit <NUM> generates the histogram on the basis of the time information.

<FIG> is a schematic diagram illustrating an example of a configuration of a device applicable to the distance measurement device <NUM> according to the embodiments. In <FIG>, the distance measurement device <NUM> is configured by stacking a light receiving chip <NUM> and a logic chip <NUM> each including a semiconductor chip. Note that in <FIG>, for the sake of description, the light receiving chip <NUM> and the logic chip <NUM> are separated.

In the light receiving chip <NUM>, the light receiving elements <NUM> included in the plurality of pixels <NUM> are arranged into a two-dimensional lattice in the region of the pixel array unit <NUM>. Furthermore, in each of the pixels <NUM>, the transistor <NUM> and the inverter <NUM> are formed on the logic chip <NUM>. Both ends of the light receiving element <NUM> are connected between the light receiving chip <NUM> and the logic chip <NUM> via a coupling portion <NUM> using copper-copper connection (CCC).

The logic chip <NUM> is provided with a logic array unit <NUM> that includes a signal processing unit configured to process a signal acquired by the light receiving element <NUM>. The logic chip <NUM> can be provided with a signal processing circuit unit <NUM> configured to process the signal acquired by the light receiving element <NUM>, and a device control unit <NUM> configured to control an operation as the distance measurement device <NUM>, in the vicinity of the logic array unit <NUM>.

For example, the signal processing circuit unit <NUM> can include the distance measurement processing unit <NUM> described above. Furthermore, the device control unit <NUM> can include the pixel control unit <NUM>, the general control unit <NUM>, the clock generation unit <NUM>, the light emission timing control unit <NUM>, and the interface <NUM> which are described above.

Note that the configurations on the light receiving chip <NUM> and logic chip <NUM> are not limited to this example. Furthermore, the device control unit <NUM> is configured to be arranged, for example, in the vicinity of the light receiving elements <NUM> for the purpose of drive or control of other component elements, in addition to the control of the logic array unit <NUM>. In addition to the arrangement illustrated in <FIG>, the device control unit <NUM> is configured to be provided in any region of the light receiving chip <NUM> and logic chip <NUM> so as to have any function.

Next, prior to the description of the present disclosure, control of the light receiving element <NUM> according to an existing technology will be described. <FIG> is a diagram schematically illustrating an example of a configuration for controlling the light receiving element <NUM> by using active quenching/recharging according to the existing technology.

In <FIG>, an element control unit <NUM> includes delay means. When the photon is incident on the light receiving element <NUM> and a current flows due to the avalanche multiplication, the element control unit <NUM> provides a first delay by using the delay means to timing at which the output signal Voiv of the inverter <NUM> is inverted first to control quenching means <NUM>, performing the quenching operation. After performing the quenching operation, the element control unit <NUM> further provides a second delay by using the delay means to control recharging means <NUM>, performing the recharging operation.

Here, as described with reference to <FIG>, an interval (inversion timing interval) between the first timing relating to the quenching operation and the second timing relating to the recharging operation of the output signal Voiv of the inverter <NUM> with respect to the voltage Vs is the width of the output pulse indicating the incidence of the photon on the light receiving element <NUM>. A charging speed at which the light receiving element <NUM> is charged by the recharging operation can be increased by increasing the amount of current supplied by the transistor <NUM> as the current source. Meanwhile, increasing the speed of charging by the recharging operation more than necessary may prevent the current flowing through the light receiving element <NUM> in response to the incidence of the photon from stopping even if the quenching operation is performed.

Therefore, in the active quenching/recharging, it is necessary to appropriately control the first timing and the second timing by the delay means in the element control unit <NUM>.

<FIG> are diagrams illustrating examples of the delay means included in the element control unit <NUM> according to the existing technology. <FIG> illustrates an example of the delay means constituted by an inverter chain having a plurality of inverters <NUM> connected in series. <FIG> illustrates an example of the delay means in which adjustment of a load capacity <NUM> of each inverter <NUM> enables setting of the delay amount in output of each inverter <NUM>, in the inverter chain illustrated in <FIG> is an example of the delay means in which adjustment of a current source <NUM> configured to supply the current to each inverter <NUM> enables setting of the delay amount in output of each inverter <NUM>, in the inverter chain illustrated in <FIG> illustrates an example of the delay means in which adjustment of the current source <NUM> and the capacity <NUM> that are provided on the input side of the inverter <NUM> sets the delay amount of a signal output from the inverter <NUM>.

The above delay means illustrated in <FIG> each generate a delay by analog signal processing. Therefore, it is difficult to avoid variations in a delay time to be generated, due to variations in characteristics or the like of the elements. In addition, the configurations in which the delay amount is adjustable, illustrated in <FIG>, include analog elements such as the capacities <NUM> and the current sources <NUM>. Therefore, the delay means is susceptible to process/voltage/temperature (PVT) variation, external noise, or the like.

For example, when the output pulses output from the pixels <NUM> have variations in width due to variations in delay time, a subsequent circuit (the conversion unit <NUM>, generation unit <NUM>, or the like) needs to be designed according to the maximum width in the output pulses. Therefore, it is difficult to improve the dynamic range (saturated count rate).

Next, a first embodiment of the present disclosure will be described. In the first embodiment, the quenching operation and the recharging operation are controlled on the basis of a clock having a predetermined period, in the active quenching/recharging.

<FIG> is a diagram schematically illustrating an example of a configuration for controlling a light receiving element <NUM> by using the active quenching/recharging according to the first embodiment. In the example of <FIG>, an element control unit 200a configured to control the quenching operation and the recharging operation of the light receiving element <NUM> includes a logic circuit 201a, delay circuits <NUM><NUM> and <NUM><NUM>, the quenching means <NUM>, and the recharging means <NUM>. In the example of <FIG>, each of the delay circuits <NUM><NUM> and <NUM><NUM> uses a D-flip-flop (FF) circuit that latches an input signal according to a clock signal ck providing a clock having a predetermined period.

In the element control unit 200a, the delay circuits <NUM><NUM> and <NUM><NUM> have clock input terminals to which the clock signal ck is input in common. The delay circuit <NUM><NUM> has a delay input terminal to which the output signal Voiv output from the inverter <NUM> is input. The delay circuit <NUM><NUM> delays the output signal Voiv input to the delay input terminal and outputs the delayed output signal Voiv as an output signal Vo<NUM>. The output signal Vo<NUM> output from the delay circuit <NUM><NUM> is input to a delay input terminal of the delay circuit <NUM><NUM>. The delay circuit <NUM><NUM> further delays the output signal Vo<NUM> input to the delay input terminal and outputs the delayed output signal Vo<NUM> as an output signal Vo<NUM>.

Furthermore, the output signal Vo<NUM> output from the delay circuit <NUM><NUM> and the output signal Vo<NUM> output from the delay circuit <NUM><NUM> are input to the logic circuit 201a.

The logic circuit 201a controls the quenching means <NUM> and the recharging means <NUM> on the basis of the output signal Vo<NUM> supplied from the delay circuit <NUM><NUM> and the output signal Vo<NUM> supplied from the delay circuit <NUM><NUM>. As described above, the element control unit <NUM> according to the first embodiment controls the quenching operation by the quenching means <NUM> and the recharging operation by the recharging means <NUM>, on the basis of the synchronized clock signal ck.

Therefore, according to the first embodiment, the delay amount to each of the quenching operation and the recharging operation is determined on the basis of the clock signal ck, and thus, the variations in the delay amount between the pixels <NUM> can be suppressed. In addition, the delay amount is determined on the basis of the clock signal ck, and thus, influence of the PVT variation, external noise, or the like in each element on the delay amount can be suppressed. Therefore, application of the first embodiment makes it possible to stably control the operation of the light receiving element <NUM>.

<FIG> is a diagram illustrating a more detailed example of the configuration according to the first embodiment. In <FIG>, the logic circuit 201a includes AND circuits <NUM> and <NUM>. The AND circuit <NUM> has one input terminal that is an inverting input terminal configured to invert an input signal. The output signal Vo<NUM> output from the delay circuit <NUM><NUM> is input to one input terminal (the inverting input terminal) of the AND circuit <NUM> and one input terminal of the AND circuit <NUM>. Furthermore, the output signal Vo<NUM> output from the delay circuit <NUM><NUM> is input to the other input terminal (the non-inverting input terminal) of the AND circuit <NUM> and the other input terminal of the AND circuit <NUM>.

The AND circuit <NUM> outputs an AND of the output signal Vo<NUM> inverted and input to one input terminal and the output signal Vo<NUM> input to the other input terminal, as a control signal en_q controlling the operation of the quenching means <NUM>. Furthermore, the AND circuit <NUM> outputs an AND of the output signals Vo<NUM> and Vo<NUM> input to one and the other input terminals, as a control signal en_r controlling the recharging means <NUM>.

In the example of <FIG>, the quenching means <NUM> includes a transistor <NUM> that is an N-channel metal oxide semiconductor (MOS) transistor. The transistor <NUM> has a drain that is connected to a connection point where the cathode of the light receiving element <NUM> and the drain of the transistor <NUM> are connected. The transistor <NUM> has a source that is connected to the ground voltage. The transistor <NUM> has a gate to which the control signal en_q is input.

Furthermore, in the example of <FIG>, the recharging means <NUM> includes a transistor <NUM> that is a P-channel MOS transistor and a transistor <NUM> that is an N-channel MOS transistor. The transistor <NUM> has a source to which a predetermined bias voltage Vbp is supplied. A drain of the transistor <NUM> is connected to a drain of the transistor <NUM>, and the gate of the transistor <NUM> is connected to a connection point where the drain of the transistor <NUM> is connected to the drain of the transistor <NUM>. The transistor <NUM> has a source that is connected to the ground voltage. The transistors <NUM> and <NUM> have gates to which the control signal en_r is input.

<FIG> is a timing chart illustrating an example of operations performed by the configuration of <FIG>, according to the first embodiment. In <FIG>, the horizontal axis represents time, and in the vertical direction, the clock signal ck, the voltage Vs, the output signals Voiv, Vo<NUM>, and Vo<NUM>, and the control signals en_q and en_r are represented.

As illustrated in <FIG>, in an initial state before a photon is incident on the light receiving element <NUM> at a time t<NUM>, the voltage Vs being in a high state is inverted by the inverter <NUM>, the output signal Voiv of the inverter <NUM> is in a low state, and the output signals Vo<NUM> and Vo<NUM> of the delay circuits <NUM><NUM> and <NUM><NUM> are each in a low state. The output signal Vo<NUM> input to the other input terminal is in the low state, and thus, the control signal en_q is in a low state. In addition, the output signals Vo<NUM> and Vo<NUM> are each in the low state, and thus, the control signal en_r is in a low state.

In <FIG>, when the photon is incident on the light receiving element <NUM> at the time t<NUM>, a current flows through the light receiving element <NUM> due to the avalanche multiplication, and the voltage Vs drops with the current flow. When the voltage Vs crosses the threshold voltage Vth in the inverter <NUM> at a time t<NUM>, the inverter <NUM> inverts the output signal Voiv into a high state. The high state of the output signal Voiv is latched in the delay circuit <NUM><NUM> at the next rising timing (time t<NUM>) of the clock signal ck, and the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into a high state. In other words, the delay circuit <NUM><NUM> delays the output signal Voiv output from the inverter <NUM> according to the clock signal ck.

The output signal Vo<NUM> of the delay circuit <NUM><NUM> is latched in the delay circuit <NUM><NUM> at the next rising timing (time t<NUM>) of the clock signal ck, and the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into a high state. In other words, the delay circuit <NUM><NUM> further delays the output signal Voiv of the inverter <NUM> having been delayed according to the clock signal ck in the delay circuit <NUM><NUM>, according to the clock signal ck.

Here, in a period from the time t<NUM> to the time t<NUM>, the output signal Vo<NUM> of the delay circuit <NUM><NUM> is in the high state, and the output signal Vo<NUM> of the delay circuit <NUM><NUM> is in the low state. Therefore, the control signal en_r output from the AND circuit <NUM> is maintained in the low state, while the control signal en_q output from the AND circuit <NUM> is brought into a high state. Therefore, the transistor <NUM> is on, the cathode of the light receiving element <NUM> is connected to the ground voltage (gnd), and the quenching operation (Quench) is performed.

When the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the high state at the time t<NUM>, the output signals Vo<NUM> and Vo<NUM> are each brought into the high state. Therefore, the control signal en_q output from the AND circuit <NUM> is brought into the low state, and the transistor <NUM> is brought into an off state in the quenching means <NUM>. Meanwhile, at the time t<NUM>, the control signal en_r output from the AND circuit <NUM> is brought into a high state, and in the recharging means <NUM>, the transistor <NUM> is brought into an off state and the transistor <NUM> is brought into an on state. Thus, the gate of the transistor <NUM> is brought into a low state, the transistor <NUM> is brought into an on state, and at the time t<NUM>, the recharging operation (Recharge) is performed to charge the light receiving element <NUM> with the voltage Ve.

When charge of the light receiving element <NUM> is started by the recharging operation, the voltage Vs increases according to the charge amount. When the voltage Vs crosses the threshold voltage Vth (time t<NUM>), the inverter <NUM> inverts the output signal Voiv into the low state. In the example of <FIG>, the time t<NUM> at which the output signal Voiv is inverted is the timing after the time t<NUM> at which the recharging operation is started.

At the next rising timing (time t<NUM>) of the clock signal ck, the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the low state. Meanwhile, the output signal Vo<NUM> of the delay circuit <NUM><NUM> is in the high state at the time t<NUM>, and thus, the control signal en_r output from the AND circuit <NUM> is brought into the low state. In other words, at the time t<NUM>, the control signals en_q and en_r are brought into the low state, and the transistors <NUM>, <NUM>, and <NUM> are brought into the initial state (Reset).

At the next rising timing (time t<NUM>) of the clock signal ck, the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the low state.

Note that, in the above description, at the time t<NUM> at which the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the low state, each of the transistors <NUM>, <NUM>, and <NUM> is in, but is not limited to, the initial state. In other words, the timing to bring each of the transistors <NUM>, <NUM>, and <NUM> into the initial state may differ depending on a settling time for the voltage Vs. In an example, it is considered to perform initialization of the transistors <NUM>, <NUM>, and <NUM> at the time t<NUM>, in a case where the recharging operation is completed during a period from the time t<NUM> to the time t<NUM> at which the next clock signal ck rises. In this case, the logic circuit 201a is changed to have a corresponding configuration.

<FIG> is a flowchart illustrating an example of controlling the light receiving element according to the first embodiment. Prior to performance of the process according to the flowchart of <FIG>, each unit of the element control unit 200a is in the initial state illustrated in <FIG>.

In Step S10, the inverter <NUM> detects a current flowing through the light receiving element <NUM>. In the next Step S11, the inverter <NUM> determines whether the current detected in Step S10 crosses a threshold value. When determining that the detected current does not cross the threshold value (Step S11, "No"), the inverter <NUM> returns to Step S10 and continues the detection of the current. Meanwhile, when determining that the current detected in Step S10 crosses the threshold value (Step S11, "Yes", time t<NUM> in <FIG>), the inverter <NUM> proceeds to Step S12.

Note that, in Step S10, actually, the inverter <NUM> detects the voltage Vs in the light receiving element <NUM> generated due to the current flowing through the light receiving element <NUM>. In Step S11, the inverter <NUM> determines whether the voltage Vs crosses the threshold voltage Vth.

In Step S12, the inverter <NUM> inverts the output signal Voiv. In the next Step S13, the logic circuit 201a delays the timing at which the output signal Voiv is inverted by the inverter <NUM> in Step S12, according to the clock signal ck (time t<NUM> in <FIG>).

In the next Step S14, the logic circuit 201a controls the light receiving element <NUM> according to the timing delayed in Step S13. More specifically, in Step S14, the logic circuit 201a controls the quenching means <NUM> and the recharging means <NUM> according to the timing and causes the light receiving element <NUM> to perform the quenching operation and the recharging operation. In practice, as described above, the logic circuit 201a starts the recharging operation of the light receiving element <NUM>, at the next rising timing (time t<NUM> in <FIG>) of the clock signal ck after controlling the quenching means <NUM> (time t<NUM> in <FIG>).

After completion of the recharging operation, each unit of the element control unit 200a is brought into the initial state according to the clock signal ck (time points t<NUM> and t<NUM> in <FIG>).

Next, a first modification of the first embodiment will be described below. In the first embodiment described above, the output signal Voiv output from the inverter <NUM> is delayed using the two delay circuits <NUM><NUM> and <NUM><NUM>. The delaying of the output signal Voiv is not limited to this example, and three or more delay circuits that synchronize with the clock signal ck may be used to delay the output signal Voiv output from the inverter <NUM>.

<FIG> is a diagram illustrating an example of a configuration of an element control unit according to the first modification of the first embodiment. In the example of <FIG>, three or more delay circuits <NUM><NUM>, <NUM><NUM>, <NUM><NUM>,. are illustrated in which an element control unit 200c according to the first modification of the first embodiment operates in synchronization with the same clock signal ck. <FIG> is a timing chart illustrating an example of timing of each of output signals Vo<NUM>, Vo<NUM>, and Vo<NUM>,. of the delay circuits <NUM><NUM>, <NUM><NUM>, and <NUM><NUM>,. in the element control unit 200c according to the first modification of the first embodiment illustrated in <FIG>.

In the configuration of <FIG>, the delay circuit <NUM><NUM> latches the transition of the output signal Voiv output from the inverter <NUM> to the high state, at the rising timing of the clock signal ck at a time t<NUM>, and brings the output signal Vo<NUM> into the high state. The delay circuit <NUM><NUM> latches the transition of the output signal Vo<NUM> to the high state at the next rising timing (time t<NUM>) of the clock signal ck and brings the output signal Vo<NUM> into the high state. The delay circuit <NUM><NUM> latches the transition of the output signal Vo<NUM> to the high state at the next rising timing (time t<NUM>) of the clock signal ck, and brings the output signal Vo<NUM> into the high state.

Thereafter, when the delay circuits are further connected in series, each of the delay circuits sequentially latches the transition of the output signal of the previous delay circuit to the high state, at the rising timing of the clock signal ck, and transitions its own output voltage to the high state. As described above, in a case where a plurality of delay circuits that each use the D-FF circuit and operates in synchronization with the common clock signal ck is connected in series, the output signal of each delay circuit is taken over to the subsequent delay circuit, according to the period of the clock signal ck.

<FIG> is a diagram illustrating an example of a configuration of a logic circuit 201c according to the first modification of the first embodiment. As in the logic circuit 201a described with reference to <FIG>, the logic circuit 201c includes the AND circuit <NUM> that has one input terminal being the inverting input terminal and the other input terminal being the non-inverting input terminal, and the AND circuit <NUM> that has one and the other input terminals both being the non-inverting input terminal. The logic circuit 201c further includes a selector <NUM>.

In the example of <FIG>, the output signal Vo<NUM> of the delay circuit <NUM><NUM> is input to the other input terminals of the AND circuits <NUM> and <NUM>, as in the example of <FIG>. An output of the selector <NUM> is input to one input terminal of each of the AND circuits <NUM> and <NUM>. The selector <NUM> has selection input terminals to which the output signals Vo<NUM>, Vo<NUM>,. of the delay circuits <NUM><NUM>, <NUM><NUM>,. The selector <NUM> selects one of the output signals Vo<NUM>, Vo<NUM>,. input to the selection input terminals and inputs the selected output signal to one input terminal of each of the AND circuits <NUM> and <NUM>.

The AND circuits <NUM> and <NUM> output the control signals en_q and en_r, on the basis of output voltage, selected from the output signals Vo<NUM>, Vo<NUM>,. by the selector <NUM> and input to one input terminal of each of the AND circuits <NUM> and <NUM>, and the output signal Vo<NUM>, output from the delay circuit <NUM><NUM>. The quenching means <NUM> and the recharging means <NUM> are controlled according to the control signals en_q and en_r, as described with reference to <FIG> and <FIG>. Note that the configuration described with reference to <FIG> is applicable to the configurations of the quenching means <NUM> and the recharging means <NUM> without change.

As described above, the serial connection of three or more delay means makes it possible to adjust the delay time of the recharging operation with respect to the quenching operation in periods of the clock signal ck.

Next, a second modification of the first embodiment will be described. In the first embodiment described above, the operations of the delay circuits <NUM><NUM> and <NUM><NUM> are synchronized with the rising timing of the clock signal ck. Meanwhile, in the second modification of the first embodiment, the delay circuits <NUM><NUM> and <NUM><NUM> are operated by further using the falling timing of the clock signal ck.

<FIG> is a diagram illustrating an example of a configuration of an element control unit according to the second modification of the first embodiment. The element control unit 200d illustrated in <FIG> is an example in which a delay circuit <NUM><NUM>' that has the clock input terminal being the inverting input terminal is used in place of the delay circuit <NUM><NUM> included in the element control unit 200a described with reference to <FIG>. The delay circuit <NUM><NUM>' operates in synchronization with the falling timing of the clock signal ck. In addition, a logic circuit 201d has the same configuration as the logic circuit 201a described with reference to <FIG>.

Note that to portions other than the delay circuit <NUM><NUM>' illustrated in <FIG>, the same configuration as that in <FIG> is applicable, and thus, detailed description thereof is omitted here.

<FIG> is a timing chart illustrating an example of an operation according to the second modification of the first embodiment. As in the above description of <FIG>, in <FIG>, the horizontal axis represents time, and in the vertical direction, the clock signal ck, the voltage Vs, the output signals Voiv, Vo<NUM>, and Vo<NUM>, and the control signals en_q and en_r are represented. In an initial state before the photon is incident on the light receiving element <NUM> at a time t<NUM>, the voltage Vs is in the high state, the output signal Voiv of the inverter <NUM> is in the low state, and the output signals Vo<NUM> and Vo<NUM> of the delay circuits <NUM><NUM> and <NUM><NUM> are in the low state. Furthermore, in the initial state, each of the control signals en_q and en_r are each in the low state.

In <FIG>, when the photon is incident on the light receiving element <NUM> at the time t<NUM>, a current flows through the light receiving element <NUM> due to the avalanche multiplication, and the voltage Vs drops with the current flow. When the voltage Vs crosses the threshold voltage Vth in the inverter <NUM> at a time t<NUM>, the inverter <NUM> inverts the output signal Voiv into the high state. The high state of the output signal Voiv is latched in the delay circuit <NUM><NUM> at the next rising timing (time t<NUM>) of the clock signal ck, and the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the high state. In other words, the delay circuit <NUM><NUM> delays the output signal Voiv output from the inverter <NUM> according to the clock signal ck.

The output signal Vo<NUM> of the delay circuit <NUM><NUM> is latched in the delay circuit <NUM><NUM> at the next falling timing (time t<NUM>) of the clock signal ck, and the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the high state. In other words, the delay circuit <NUM><NUM> further delays the output signal Voiv of the inverter <NUM> having been delayed according to the clock signal ck in the delay circuit <NUM><NUM>, according to the clock signal ck.

In a period from the time t<NUM> to the time t<NUM>, the output signal Vo<NUM> of the delay circuit <NUM><NUM> is in the high state, and the output signal Vo<NUM> of the delay circuit <NUM><NUM> is in the low state. Therefore, the control signal en_r output from the AND circuit <NUM> is maintained in the low state, while the control signal en_q output from the AND circuit <NUM> is brought into a high state. Therefore, the transistor <NUM> is on, the cathode of the light receiving element <NUM> is connected to the ground voltage (gnd), and the quenching operation (Quench) is performed.

When the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the high state at the time t<NUM>, the output signals Vo<NUM> and Vo<NUM> are each brought into the high state. Therefore, the control signal en_q output from the AND circuit <NUM> is brought into the low state, and the transistor <NUM> is brought into an off state in the quenching means <NUM>. Meanwhile, the control signal en_r output from the AND circuit <NUM> is brought into the high state, and in the recharging means <NUM>, the transistor <NUM> is brought into the off state, and the transistor <NUM> is brought into the on state. Thus, the gate of the transistor <NUM> is brought into the low state, the transistor <NUM> is brought into the on state, and at the time t<NUM> as the falling timing of the clock signal ck, the recharging operation (Recharge) is performed to charge the light receiving element <NUM> with the voltage Ve.

In the first embodiment described above, as described with reference to <FIG>, a time period from the performance of the quenching operation at the time t<NUM> to the start of the recharging operation at the time t<NUM> corresponds to one period of the clock signal ck. Meanwhile, in the second modification of the first embodiment, the falling timing of the clock signal ck is further used. Therefore, the time period from the performance of the quenching operation at the time t<NUM> to the start of the recharging operation at the time t<NUM> corresponds to <NUM>/<NUM> of the period of the clock signal ck.

Therefore, an interval at which the output signal Voiv is inverted by the inverter <NUM> can be reduced for faster operation. Furthermore, for example, in a case where each processing is performed at a time interval similar to that of <FIG> described above, the frequency required for the clock signals ck is only <NUM>/<NUM> of that of <FIG>, and power consumption relating to generation of the clock signals ck can be reduced.

Furthermore, according to the second modification of the first embodiment, as in the first embodiment described above, the delay amount to each of the quenching operation and the recharging operation is determined on the basis of the clock signal ck, and thus, the variations in the delay amount between the pixels <NUM> can be suppressed. In addition, the delay amount is determined on the basis of the clock signal ck, and thus, influence of the PVT variation, external noise, or the like in each element on the delay amount can be suppressed. Therefore, application of the second modification of the first embodiment makes it possible to stably control the operation of the light receiving element <NUM>.

At the next falling timing (time t<NUM>) of the clock signal ck, the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the low state.

Note that, in the above description, at the time t<NUM> at which the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the low state, each of the transistors <NUM>, <NUM>, and <NUM> relating to the quenching operation and the recharging operation is in, but is not limited to, the initial state. In other words, the timing to bring each of the transistors <NUM>, <NUM>, and <NUM> into the initial state may differ depending on the settling time for the voltage Vs. In an example, it is considered to perform initialization of the transistors <NUM>, <NUM>, and <NUM> at the time t<NUM>, in a case where the recharging operation is completed from the time t<NUM> until the time t<NUM> at which the next clock signal ck rises. In this case, the logic circuit 201d is changed to have a corresponding configuration.

Next, a third modification of the first embodiment will be described. The first embodiment and the first and second modifications of the first embodiment which are described above each have a configuration in which the voltage Vs is read from the cathode of the light receiving element <NUM> and supplied to the inverter <NUM>. Meanwhile, the third modification of the first embodiment has a configuration in which the voltage Vs is read from the anode of the light receiving element <NUM> and supplied to the inverter <NUM>.

<FIG> is a diagram illustrating an example of a configuration of an element control unit according to the third modification of the first embodiment. The configuration illustrated in <FIG> corresponds to the configuration according to the second modification of the first embodiment illustrated in <FIG>.

In <FIG>, a pixel <NUM>' includes a light receiving element <NUM>, a transistor <NUM> that is an N-channel MOS transistor, and the inverter <NUM>. The light receiving element <NUM> corresponds to the light receiving element <NUM> described above, and has a cathode that is connected to a voltage (Vbd + Ve) obtained by adding the voltage Ve to a positive voltage Vbd whose absolute value corresponds to the negative voltage (-Vbd) described above. The light receiving element <NUM> has an anode that is connected to a drain of the transistor <NUM>. The transistor <NUM> has a source that is connected to a predetermined voltage VSS. The voltage VSS may be, for example, a ground voltage.

The voltage Vs extracted from a connection point where the transistor <NUM> and the anode of the light receiving element <NUM> are connected is input to the inverter <NUM>. The inverter <NUM> performs threshold determination on the voltage Vs by using the threshold voltage Vth, and inverts the output signal Voiv when determining that the voltage Vs crosses the threshold voltage Vth.

An element control unit 200e includes a logic circuit 201e, the delay circuits <NUM><NUM> and <NUM><NUM>', quenching means <NUM>', and recharging means <NUM>'.

The output signal Voiv output from the inverter <NUM> is input to the delay circuit <NUM><NUM>. The delay circuit <NUM><NUM> is a D-FF circuit that latches the input signal at the rising timing of the clock signal ck. The output signal Vo<NUM> output from the delay circuit <NUM><NUM> is input to the delay circuit <NUM><NUM>'. The delay circuit <NUM><NUM>' is a D-FF circuit that has the clock input terminal being the inverting input terminal and is configured to latch the input signal at the falling timing of the clock signal ck.

The output signals Vo<NUM> and Vo<NUM> output from the delay circuits <NUM><NUM> and <NUM><NUM>' are input to the logic circuit 201e. The logic circuit 201e includes NAND circuits <NUM> and <NUM>. The NAND circuit <NUM> has one input terminal that is the inverting input terminal configured to invert the input signal. The output signal Vo<NUM> output from the delay circuit <NUM><NUM> is input to one input terminal (the inverting input terminal) of the NAND circuit <NUM> and one input terminal of the NAND circuit <NUM>. Furthermore, the output signal Vo<NUM> output from the delay circuit <NUM><NUM> is input to the other input terminal (the non-inverting input terminal) of the NAND circuit <NUM> and the other input terminal of the NAND circuit <NUM>.

The NAND circuit <NUM> outputs a negative AND of the output signal Vo<NUM> inverted and input to one input terminal and the output signal Vo<NUM> input to the other input terminal, as a control signal xen_q controlling the operation of the quenching means <NUM>'. Furthermore, the NAND circuit <NUM> outputs a negative AND of the output signals Vo<NUM> and Vo<NUM> input to one and the other input terminals, as a control signal xen_r controlling the recharging means <NUM>'.

In the example of <FIG>, the quenching means <NUM>' includes a transistor <NUM> that is a P-channel MOS transistor. The transistor <NUM> has a drain that is connected to a connection point where the anode of the light receiving element <NUM> and the drain of the transistor <NUM> are connected. The transistor <NUM> has a source that is connected to the voltage Ve. The transistor <NUM> has a gate to which the control signal xen_q is input.

Furthermore, in the example of <FIG>, the recharging means <NUM>' includes a transistor <NUM> that is a P-channel MOS transistor and a transistor <NUM> that is an N-channel MOS transistor. The transistor <NUM> has a source to which a predetermined bias voltage Vbn is supplied. A drain of the transistor <NUM> is connected to a drain of the transistor <NUM>, and a gate of the transistor <NUM> is connected to a connection point where the drain of the transistor <NUM> is connected to the drain of the transistor <NUM>. The transistor <NUM> has a source that is connected to the voltage Ve. The transistors <NUM> and <NUM> have gates to which the control signal xen_r is input.

The operation in the configuration illustrated in <FIG> is similar to the operation in the configuration of <FIG> corresponding to the configuration of <FIG>. Therefore, to the operation of <FIG>, the operation described using the timing chart of <FIG> corresponding to the configuration of <FIG> is applicable, and thus the description thereof is omitted here. As described above, the technology of the present disclosure is also applicable to a configuration in which the voltage Vs is read from the anode of the light receiving element <NUM>.

In the third modification of the first embodiment as well, as in the first embodiment described above, the delay amount to each of the quenching operation and the recharging operation is determined on the basis of the clock signal ck, and thus, the variations in the delay amount between the pixels <NUM>' can be suppressed. In addition, the delay amount is determined on the basis of the clock signal ck, and thus, influence of the PVT variation, external noise, or the like in each element on the delay amount can be suppressed. Therefore, application of the third modification of the first embodiment makes it possible to stably control the operation of the light receiving element <NUM>.

Next, a second embodiment of the present disclosure will be described. In the first embodiment and the modifications thereof described above, the quenching operation and the recharging operation are each performed by the active method synchronized with the clock signal ck. Meanwhile, in the second embodiment, the quenching operation is performed by a passive method, and the recharging operation is performed by the active method synchronized with the clock signal ck.

<FIG> is a diagram illustrating an example of a configuration of an element control unit according to the second embodiment. The configuration illustrated in <FIG> is obtained, for example, by omitting the configuration relating to the quenching operation by the active method from the configuration according to the first embodiment illustrated in <FIG>. More specifically, the element control unit 200f illustrated in <FIG> is obtained by omitting the quenching means <NUM> (the transistor <NUM>) from the configuration of <FIG>.

Furthermore, a logic circuit 201f is obtained by omitting the AND circuit <NUM> for outputting the control signal en_q controlling the quenching means <NUM>, from the logic circuit 201a of <FIG>. The output signal Vo2 output from the delay circuit <NUM> is input to one input terminal of the AND circuit <NUM>. In addition, the output signal Vo1 output from the delay circuit <NUM> is input to the other input terminal of the AND circuit <NUM>. The output of the AND circuit <NUM> is input to each of the gates of the transistors <NUM> and <NUM> included in the recharging means <NUM>.

<FIG> is a timing chart illustrating an example of operations performed by the configuration of <FIG>, according to the first embodiment. In <FIG>, the horizontal axis represents time, and in the vertical direction, the clock signal ck, the voltage Vs, the output signals Voiv, Vo<NUM>, and Vo<NUM>, and the control signal en_r are represented.

As illustrated in <FIG>, in an initial state before a photon is incident on the light receiving element <NUM> at a time t<NUM>, the voltage Vs being in a high state is inverted by the inverter <NUM>, the output signal Voiv of the inverter <NUM> is in a low state, and the output signals Vo<NUM> and Vo<NUM> of the delay circuits <NUM><NUM> and <NUM><NUM> are each in a low state. The output signals Vo<NUM> and Vo<NUM> are each in the low state, and thus, the control signal en_r is in a low state.

The output signal Vo<NUM> of the delay circuit <NUM><NUM> is latched in the delay circuit <NUM><NUM> at the next rising timing (time t<NUM>) of the clock signal ck, and the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the high state. In other words, the delay circuit <NUM><NUM> further delays the output signal Voiv of the inverter <NUM> having been delayed according to the clock signal ck in the delay circuit <NUM><NUM>, according to the clock signal ck.

Here, according to the current flowing through the transistor <NUM> due to the avalanche multiplication in the light receiving element <NUM>, a voltage drop occurs due to the source-drain resistance of the transistor <NUM>. This voltage drop causes a decrease in voltage applied to the light receiving element <NUM> to the voltage (-Vdb), and the quenching operation by the passive method is performed.

When the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the high state at the time t<NUM>, the output signals Vo<NUM> and Vo<NUM> are each brought into the high state. Therefore, the control signal en_r output from the AND circuit <NUM> is brought into the high state, and in the recharging means <NUM>, the transistor <NUM> is brought into the off state, and the transistor <NUM> is brought into the on state. Thus, the gate of the transistor <NUM> is brought into the low state, the transistor <NUM> is brought into the on state, and at the time t<NUM>, the recharging operation (Recharge) is performed to charge the light receiving element <NUM> with the voltage Ve.

Note that, in the above description, at the time t<NUM> at which the output signal Vo<NUM> of the delay circuit <NUM><NUM> is brought into the low state, each of the transistors <NUM> and <NUM> relating to a reset operation is in, but is not limited to, the initial state. In other words, the timing to bring each of the transistors <NUM> and <NUM> into the initial state may differ depending on the settling time for the voltage Vs. In an example, it is considered to perform initialization of the transistors <NUM> and <NUM> at the time t<NUM>, in a case where the recharging operation is completed from the time t<NUM> until the time t<NUM> at which the next clock signal ck rises. In this case, the logic circuit 201f is changed to have a corresponding configuration.

In the configuration according to the second embodiment, no forcible quenching operation synchronized with the clock signal ck is performed, and thus, the quenching operation requires time as compared with the configuration according to the first embodiment described above. Therefore, in the configuration according to the second embodiment, a time required for completion of the recharging operation after the photon is incident on the light receiving element <NUM> is shorter than that required for performance of the recharging operation by the passive method but is longer than that in the configuration according to the first embodiment described above.

Meanwhile, in the configuration according to the second embodiment, the configuration for performing the quenching operation by the active method (e.g., the transistor <NUM> and the AND circuit <NUM> in <FIG>) can be omitted. Therefore, the configuration according to the second embodiment can be achieved by a simpler configuration than the configuration according to the first embodiment described above. Thus, the area of the circuit upon implementation can be further reduced as compared with that of the configuration according to the first embodiment.

Furthermore, in the second embodiment as well, as in the first embodiment and the like described above, the delay amount to the recharging operation is determined on the basis of the clock signal ck, and thus, the variations in the delay amount between the pixels <NUM> can be suppressed. In addition, the delay amount is determined on the basis of the clock signal ck, and thus, influence of the PVT variation, external noise, or the like in each element on the delay amount can be suppressed. Therefore, application of the second embodiment makes it possible to stably control the operation of the light receiving element <NUM>.

Next, a third embodiment of the present disclosure will be described. The third embodiment is an example in which the element control unit according to the present disclosure is shared between a plurality of pixels <NUM>. <FIG> is a diagram illustrating an example of a configuration according to the third embodiment. <FIG> illustrates the example in which the element control unit 200a described in the first embodiment is applied to the third embodiment.

In <FIG>, each output signal Voiv output from the inverter <NUM> of each pixel <NUM> is input to an OR circuit <NUM>. An output of the OR circuit <NUM> is input to an input terminal of the delay circuit <NUM><NUM> of the element control unit 200a. The delay circuit <NUM><NUM> latches the output signal Voiv input from the OR circuit <NUM> at the rising timing of the clock signal ck, and outputs the output signal Vo<NUM> at the next rising timing of the clock signal ck. The output signal Vo<NUM> is input to the input terminal of the delay circuit <NUM><NUM>. The delay circuit <NUM><NUM> latches the input output signal Vo<NUM> and outputs the output signal Vo<NUM> at the next rising timing of the clock signal ck.

The output signal Vo<NUM> output from the delay circuit <NUM><NUM> and the output signal Vo<NUM> output from the delay circuit <NUM><NUM> are input to the logic circuit 201a. As described with reference to <FIG> and <FIG> and the like, the logic circuit 201a generates the control signal en_q for controlling the quenching operation and the control signal en_r for controlling the recharging operation, on the basis of the output signals Vo1 and Vo2, and supplies the generated control signals to each pixel <NUM>.

Note that, in the example of <FIG>, for the sake of explanation, the control signal en_q is omitted and the control signal en_r is represented as a signal RCHG.

The signal RCHG is supplied to the pixels <NUM> in common. In each of the pixels <NUM>, the operation of the transistor <NUM> is controlled by the recharging means <NUM>, which is not illustrated, according to the signal RCHG, and the recharging operation for each light receiving element <NUM> is performed.

In the configuration illustrated in <FIG>, the OR circuit <NUM> outputs an output signal Voiv output from an inverter <NUM> of a pixel <NUM> on which the photon is incident first in time, of the pixels <NUM>. Therefore, for the respective pixels <NUM> that are configured to input the output signal Voiv of the inverters <NUM> to the OR circuit <NUM>, the quenching operation and the recharging operation are performed in synchronization with a pixel <NUM> on which the photon is incident first in time, of the pixels <NUM>.

As described above, sharing the control signals for controlling the quenching operation and the recharging operation between the plurality of pixels <NUM> makes it possible to reduce the number of the element control units 200a and reduce the area of the circuit upon implementation.

Note that, in each pixel <NUM> illustrated in <FIG>, the light receiving element <NUM> is configured to be separated from the other elements (e.g., the transistor <NUM> and the inverter <NUM>) included in the pixel <NUM> via a coupling portion <NUM>. <FIG> is a diagram illustrating an example of a configuration, applicable to the third embodiment, in which when the control signals for controlling the quenching operation and the recharging operation are shared between four pixels <NUM> of two pixels by two pixels, the pixels <NUM> are separated into the light receiving chip <NUM> and the logic chip <NUM> (see <FIG>).

In the example of <FIG>, as in the example of <FIG> described above, a lower surface of the light receiving chip <NUM> and an upper surface of the logic chip <NUM> are bonded to each other. The light receiving elements <NUM> are arranged so that a surface of each light receiving element <NUM> on which the photon is incident is located on the upper surface of the light receiving chip <NUM>. Meanwhile, for example, the element control unit 200a, the transistor <NUM> and the inverter <NUM> that are included in each pixel <NUM>, the quenching means <NUM>, and the recharging means <NUM> are arranged in a circuit unit <NUM> on the logic chip <NUM>.

The cathode and the anode of the light receiving element <NUM> are connected to the circuit unit <NUM> via connection portions <NUM> and <NUM> for interchip connection <NUM>. At this time, the connection portion <NUM> that connects the cathode of the light receiving element <NUM> to the circuit unit <NUM> corresponds to the coupling portion <NUM> described above. For example, it is preferable to apply copper-copper connection (CCC) to the coupling portion <NUM>.

In such a configuration, sharing the control signals for controlling the quenching operation and the recharging operation between the plurality of pixels <NUM> makes it possible to for example, eliminate the need for arranging the element control unit 200a in regions in the circuit unit <NUM> on the logic chip <NUM> corresponding one-to-one to arrangement positions of the light receiving elements <NUM> on the light receiving chip <NUM>. This makes it possible to have a sufficient space in layout in the circuit unit <NUM>. This facilitates layout design and the like in the logic chip <NUM>, for example, in a case where the area of the light receiving surface of each light receiving element <NUM> is reduced enabling high-density arrangement of the light receiving elements <NUM>.

Next, a fourth embodiment of the present disclosure will be described. The fourth embodiment is an example in which the distance measurement device <NUM> to which the technology of the present disclosure is applied, described with reference to, for example, <FIG> is formed on a single-layer semiconductor chip. <FIG> is a diagram illustrating an example of a light receiving integrated circuit (IC) that is applicable to the distance measurement device according to the fourth embodiment.

In <FIG>, a light receiving IC <NUM> according to the fourth embodiment corresponds to, for example, the light receiving unit <NUM> of <FIG>, and includes the configuration of the distance measurement device <NUM> described with reference to <FIG> and <FIG>. The light receiving IC <NUM> is configured by arranging the pixel array unit <NUM>, a peripheral circuit unit <NUM>, a logic unit <NUM>, and an input/output (I/O) unit <NUM> on the single-layer semiconductor chip.

As described above, the pixel array unit <NUM> includes the plurality of pixels <NUM> arranged in a matrix. In the example of <FIG>, for example, each pixel <NUM>, including the element control unit 200a, the quenching means <NUM>, and the recharging means <NUM>, is included in the pixel array unit <NUM>. The element control unit 200a may be provided in each pixel <NUM> or one element control unit 200a may be provided for a plurality of pixels <NUM>.

The logic unit <NUM> corresponds to, for example, the distance measurement processing unit <NUM> in <FIG>. For example, the logic unit <NUM> converts, for example, each output signal Vo<NUM> supplied from each pixel <NUM> of the pixel array unit <NUM>, into the time information indicating the timing at which light is received by the light receiving element <NUM> included in the pixel <NUM>. The logic unit <NUM> further generates the histogram on the basis of the time information obtained by converting each output signal Vo<NUM>, performs predetermined calculation on the basis of data in the generated histogram, and calculates, for example, the distance information. The distance information calculated by the logic unit <NUM> is output as output data to the outside of the light receiving IC <NUM>, for example, via the I/O unit <NUM> corresponding to the I/F <NUM> in <FIG>.

In <FIG>, the peripheral circuit unit <NUM> includes a clock generation unit <NUM> corresponding to the clock generation unit <NUM> illustrated in <FIG>. The clock generation unit <NUM> generates the clock signal ck described above, and supplies the generated clock signal ck to each unit of the light receiving IC <NUM> via a path <NUM>. Furthermore, the peripheral circuit unit <NUM> includes, for example, the pixel control unit <NUM>, the general control unit <NUM>, and the light emission timing control unit <NUM> which are illustrated in <FIG>. The peripheral circuit unit <NUM> including the clock generation unit <NUM> and the pixel control unit <NUM>, the general control unit <NUM>, and the light emission timing control unit <NUM> which are illustrated in <FIG>, is laid out on the light receiving IC <NUM>.

As described above, in the fourth embodiment, the clock generation unit <NUM> and the pixel array unit <NUM> are arranged on the light receiving IC <NUM>, and the clock signal ck generated by the clock generation unit <NUM> is supplied to the pixel array unit <NUM>. In the pixel array unit <NUM>, the clock signal ck is supplied to each element control unit 200a corresponding to each pixel <NUM>.

In each pixel <NUM>, the quenching operation and the recharging operation of the light receiving element <NUM> are controlled on the basis of the clock signal ck. Therefore, as compared with the quenching operation and the recharging operation that are delayed by analog elements, there is no need for a configuration such as countermeasures against the PVT variations affecting the delay amount of the analog delay. In addition, the influence of the external noise is also suppressed, and, for example, it is thus possible to suppress variations in the dynamic range of the voltage Vs extracted from the light receiving element <NUM>. Therefore, application of the fourth embodiment makes it possible to stably control the operation of the light receiving element <NUM>, enabling the distance measurement with higher accuracy.

Next, as a fifth embodiment of the present disclosure, application examples of the first embodiment and modifications thereof, the second embodiment, the third embodiment, and the fourth embodiment of the present disclosure will be described. <FIG> is a diagram illustrating use examples of the distance measurement device <NUM> according to the fifth embodiment to which the first embodiment and the modifications thereof, the second embodiment, the third embodiment, and the fourth embodiment are applicable.

The distance measurement device <NUM> described above is available for, for example, various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays, as described below.

The technology according to the present disclosure may be further applied to devices mounted on various moving bodies, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility vehicles, airplanes, drones, ships, and robots.

<FIG> is a block diagram illustrating a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure is applicable.

A vehicle control system <NUM> includes a plurality of electronic control units connected via a communication network <NUM>. In the example illustrated in <FIG>, the vehicle control system <NUM> includes a drive system control unit <NUM>, a body system control unit <NUM>, a vehicle external information detection unit <NUM>, a vehicle internal information detection unit <NUM>, and an integrated control unit <NUM>. Furthermore, as a functional configuration of the integrated control unit <NUM>, a microcomputer <NUM>, an audio/visual output unit <NUM>, and an in-vehicle network interface (I/F) <NUM> are illustrated.

The drive system control unit <NUM> controls the operation of devices relating to the drive system of the vehicle according to various programs. For example, the drive system control unit <NUM> functions as a control device for a drive force generation device configured to generate a drive force of the vehicle such as an internal combustion engine or a driving motor, a drive force transmission mechanism configured to transmit the drive force to wheels, a steering mechanism configured to adjust a steering angle of the vehicle, a braking device configured to generate a braking force of the vehicle, and the like.

The body system control unit <NUM> controls operations of various devices mounted on the vehicle body according to various programs. For example, the body system control unit <NUM> functions as a control device for a keyless entry system, smart key system, power window device, or various lamps such as a headlamp, back lamp, brake lamp, blinker, or fog lamp. In this case, the body system control unit <NUM> is configured to receive input of radio waves transmitted from a portable device substituting for a key, or signals of various switches. The body system control unit <NUM> receives the input of these radio waves or signals and controls a door lock device, a power window device, a lamp, and the like of the vehicle.

The vehicle external information detection unit <NUM> detects information outside the vehicle on which the vehicle control system <NUM> is mounted. For example, an imaging unit <NUM> is connected to the vehicle external information detection unit <NUM>. The vehicle external information detection unit <NUM> causes the imaging unit <NUM> to capture an image outside the vehicle and receives the captured image. The vehicle external information detection unit <NUM> may perform object detection processing or distance detection processing for a person, vehicle, obstacle, sign, character on a road surface, or the like on the basis of the received image. For example, the vehicle external information detection unit <NUM> performs image processing on the received image, and performs object detection processing or distance detection processing on the basis of a result of the image processing.

The imaging unit <NUM> is an optical sensor configured to receive light and output an electric signal corresponding to the amount of light received. The imaging unit <NUM> is operable to output the electric signal as an image or to output the electric signal as distance measurement information. Furthermore, the light received by the imaging unit <NUM> may be visible light or invisible light such as infrared light.

The vehicle internal information detection unit <NUM> detects information inside the vehicle. For example, a driver state detection unit <NUM> configured to detect the state of the driver is connected to the vehicle internal information detection unit <NUM>. The driver state detection unit <NUM> may include, for example, a camera to image the driver, and the vehicle internal information detection unit <NUM> may calculate the degree of fatigue or degree of concentration of the driver or may determine whether the driver is dozing off, on the basis of detected information input from the driver state detection unit <NUM>.

The microcomputer <NUM> is configured to calculate a control target value for the drive force generation device, steering mechanism, or braking device on the basis of the information inside and outside the vehicle acquired by the vehicle external information detection unit <NUM> or the vehicle internal information detection unit <NUM>, and output a control command to the drive system control unit <NUM>. Specifically, for example, the microcomputer <NUM> is configured to execute cooperative control to achieve the function of advanced driver assistance system (ADAS), including vehicle collision avoidance or impact mitigation, following on the basis of a distance between vehicles, driving while maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, and the like.

Furthermore, the microcomputer <NUM> controls the drive force generation device, the steering mechanism, the braking device, or the like on the basis of information around the vehicle acquired by the vehicle external information detection unit <NUM> or the vehicle internal information detection unit <NUM>, for the cooperative control to achieve autonomous driving or the like without depending on the driver's operation.

Furthermore, the microcomputer <NUM> is configured to output a control command to the body system control unit <NUM>, on the basis of the information outside the vehicle acquired by the vehicle external information detection unit <NUM>. For example, the microcomputer <NUM> is configured to execute the cooperative control for antidazzle such as by controlling the headlamps according to the position of a preceding vehicle or oncoming vehicle detected by the vehicle external information detection unit <NUM> and switching the headlamps from a high beam to a low beam.

The audio/visual output unit <NUM> transmits an output signal of at least one of voice or an image to an output device configured to visually or audibly notifying an occupant of the vehicle or the outside of the vehicle of information. In the example of <FIG>, an audio speaker <NUM>, a display unit <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display unit <NUM> may include, for example, at least one of an on-board display and a head-up display.

<FIG> is a diagram illustrating an example of installation positions of the imaging unit <NUM>. In <FIG>, a vehicle <NUM> includes imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> as the imaging unit <NUM>.

The imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are provided on the vehicle <NUM>, at positions, such as a front nose, side mirrors, a rear bumper, a back door, and the upper side of a windshield on a side of a vehicle interior. The imaging unit <NUM> that is provided at the front nose and the imaging unit <NUM> that is provided at the upper side of the windshield on the side of the vehicle interior each mainly acquire an image of an area in front of the vehicle <NUM>. The imaging units <NUM> and <NUM> that are provided at the side mirrors each mainly acquire an image captured from a side of the vehicle <NUM>. The imaging unit <NUM> that is provided at the rear bumper or the back door mainly acquires an image of an area in back of the vehicle <NUM>. The images of the areas in front of the vehicle <NUM> that are acquired by the imaging units <NUM> and <NUM> are mainly used to detect the preceding vehicle, the pedestrian, the obstacle, a traffic light, the traffic sign, a lane, or the like.

Note that <FIG> illustrates an example of imaging ranges of the imaging units <NUM> to <NUM>. An imaging range <NUM> indicates an imaging range of the imaging unit <NUM> provided at the front nose, imaging ranges <NUM> and <NUM> indicate imaging ranges of the imaging units <NUM> and <NUM> provided at the respective side mirrors, and an imaging range <NUM> indicates an imaging range of the imaging unit <NUM> provided at the rear bumper or back door. For example, image data captured by the imaging units <NUM> to <NUM> are superposed on each other, and an overhead view image of the vehicle <NUM> as viewed from above is obtained.

At least one of the imaging units <NUM> to <NUM> may have a function of acquiring distance information. For example, at least one of the imaging units <NUM> to <NUM> may be a stereo camera including a plurality of imaging elements, or may be an imaging element having a pixel for phase difference detection.

For example, the microcomputer <NUM> is configured to obtain a distance to each three-dimensional object in the imaging ranges <NUM> to <NUM> and a temporal change in the distance (relative speed with respect to the vehicle <NUM>) on the basis of the distance information obtained from the imaging units <NUM> to <NUM>, and extract, in particular, a three-dimensional object nearest on a travel path of the vehicle <NUM> and traveling at a predetermined speed (e.g., <NUM>/h or more) in substantially the same direction as the vehicle <NUM>, as the preceding vehicle. Furthermore, the microcomputer <NUM> is configured to set a distance between the vehicles to be secured in advance with respect to the preceding vehicle, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), and the like. As described above, it is possible to perform cooperative control for the autonomous driving or the like without depending on the operation of the driver.

For example, on the basis of the distance information obtained from the imaging units <NUM> to <NUM>, the microcomputer <NUM> classifies three-dimensional object data about the three-dimensional objects into a two-wheeled motorcycle, ordinary motor vehicle, large-sized motor vehicle, pedestrian, power pole, and the other three-dimensional objects, extracts the classified three-dimensional object data, for use in automatic obstacle avoidance. For example, the microcomputer <NUM> identifies the obstacles around the vehicle <NUM> between an obstacle that is visible to a driver of the vehicle <NUM> and an obstacle which is difficult for the driver to see. Then the microcomputer <NUM> determines a collision risk that indicates the degree of risk of collision with each obstacle, and in a case where the risk of collision has a value equal to or more than a set value and there is a possibility of collision, the microcomputer <NUM> outputs warning to the driver via the audio speaker <NUM> or the display unit <NUM>, or performs forced deceleration or evasive steering via the drive system control unit <NUM>, performing driving assistance for collision avoidance.

At least one of the imaging units <NUM> to <NUM> may be an infrared camera detecting infrared light. For example, the microcomputer <NUM> is configured to recognize the pedestrian by determining whether the pedestrian is shown in an image captured by the imaging units <NUM> to <NUM>. Such pedestrian recognition is performed, for example, according to a procedure for extracting feature points in the images captured by the imaging units <NUM> to <NUM> as the infrared cameras, and a procedure for determining whether a sequence of the feature points indicating a contour of an object is the pedestrian by performing pattern matching. When the microcomputer <NUM> determines that the pedestrian is shown in the images captured by the imaging units <NUM> to <NUM> and recognizes the pedestrian, the audio/visual output unit <NUM> controls the display unit <NUM> to display a rectangular contour line superimposed on the recognized pedestrian to emphasize the recognized pedestrian. Furthermore, the audio/visual output unit <NUM> may control the display unit <NUM> to display an icon or the like indicating the pedestrian, at a desired position.

An example of the vehicle control system to which the technology according to the present disclosure is applicable has been described above. The technology according to the present disclosure is applicable to, for example, the imaging unit <NUM> of the configurations described above. Specifically, it is possible to apply the distance measurement device <NUM> to which the first embodiment and modifications thereof, the second embodiment, the third embodiment, and the fourth embodiment which are described above are applicable, to the imaging unit <NUM>. Application of the technology according to the present disclosure to the imaging unit <NUM> makes it possible to more stably perform distance measurement.

Claim 1:
A measurement device (<NUM>) comprising:
a light receiving element (<NUM>) that has flow of current caused by an avalanche multiplication caused according to a photon incidence while being charged to a predetermined potential and is returned to the charged state by a recharge current;
a detection unit (<NUM>) that is configured to detect the current and invert an output signal (Voiv) of the measurement device (<NUM>) when the current crosses a threshold value;
a delay unit (<NUM><NUM>, <NUM><NUM>) that is configured to delay timing of the inversion detected by the detection unit (<NUM>), according to a clock (ck); and
a control unit (200a) that is configured to control an operation of the light receiving element (<NUM>), based on the timing of the inversion delayed by the delay unit (<NUM><NUM>, <NUM><NUM>).