Patent Description:
A photodetector device in which a plurality of avalanche photodiodes are two-dimensionally arranged is known (for example, Patent Literature <NUM>). The plurality of avalanche photodiodes is arranged to operate in a Geiger mode. The plurality of avalanche photodiodes are formed on a semiconductor substrate formed from compound semiconductor.

Patent Literature <NUM> discloses a light detection device having a semiconductor light detection element having a semiconductor substrate, and a mounting substrate arranged as opposed to the semiconductor light detection element.

Patent Literature <NUM> discloses a system and method providing for the detection of an input signal, either optical or electrical, by using a single independent discrete amplifier or by distributing the input signal into independent signal components that are independently amplified.

Patent Literature <NUM> discloses a stacked SPAD image sensor with a CMOS Chip and an imaging chip bonded together, to improve the fill factor of the SPAD image sensor, and an associated method of formation.

Patent Literature <NUM> discloses devices for detecting photons, including avalanche photon detectors, arrays of such detectors, and circuits including such arrays.

Patent Literature <NUM> discloses a photodiode array including quenching resistors which are connected in series to respective avalanche photodiodes, a peripheral wiring which surrounds a region in which the plurality of avalanche photodiodes are formed, and a plurality of relay wirings which are electrically connected to the peripheral wiring, so as to respectively connect at least two places of the peripheral wiring.

In a case where a plurality of avalanche photodiodes formed on the semiconductor substrate formed from the compound semiconductor is arranged to operate in the Geiger mode, a dark pulse and an after pulse increase in correspondence with a temperature variation. When a noise increases due to the dark pulse and the after pulse, there is a concern that a signal from the avalanche photodiodes may not be appropriately detected.

There is known a configuration in which passive quenching elements are arranged in series to the avalanche photodiodes to quench avalanche multiplication in a case where the avalanche photodiodes is arranged to operate in the Geiger mode. Whether or not an avalanche multiplication process that occurs inside the avalanche photodiodes connected to the passive quenching element is appropriately quenched is determined depending on a resistance value of the passive quenching element. When the resistance value of the quenching elements is not sufficient, there is a concern that appropriate quenching is not realized due to occurrence of a latching current or the like. It is necessary to select a sufficient resistance value of the quenching elements for appropriate quenching.

As the resistance value of the passive quenching elements is larger, time necessary for quenching of the avalanche photodiodes which are connected to the passive quenching elements in series increases. As the time necessary for the quenching increases, dead time for which light cannot be detected by the avalanche photodiodes increases. As described above, there is a demand for a circuit design including passive quenching elements having an optimal resistance value to make appropriate quenching and reduction of the dead time compatible with each other and to secure photodetection sensitivity and photodetection time resolution.

Since a parasitic capacitance in the passive quenching elements also has an influence on a pulse signal, and thus removal of the parasitic capacitance is also demanded. It is also demanded to improve a peak value of the pulse signal to further improve the photodetection time resolution. It is very difficult to design a device in which the plurality of avalanche photodiodes formed on the semiconductor substrate formed from the compound semiconductor are arranged to operate in the Geiger mode so as to satisfy all of the above-described desired conditions.

An object of an aspect of the invention is to provide a photodetector device in which photodetection sensitivity and an improvement of photodetection time resolution are compatible in a configuration in which a plurality of avalanche photodiodes are formed on a semiconductor substrate formed from compound semiconductor.

According to an aspect of the invention, there is provided a photodetector device as defined in appended claim <NUM>.

In one aspect, the plurality of output units including the passive quenching element and the capacitative element are provided in the circuit substrate different from the avalanche photodiode array substrate. According to this, a space capable of forming the plurality of output units can be further expanded in comparison to a case where the plurality of output units are arranged in the avalanche photodiode array substrate. When the output units are provided in the circuit substrate separate from the avalanche photodiode array substrate, a parasitic capacitance that occurs between a configuration of the avalanche photodiodes and the output units can be reduced. In this case, a manufacturing process different from that of the avalanche diode array substrate can also be used. Accordingly, the design of the plurality of output units becomes easy. The capacitative element provided in the photodetector device is connected in series to at least one of the avalanche photodiodes and is connected in parallel to the passive quenching element. According to this, a peak value of a pulse signal transmitted from the avalanche photodiode that is connected in series to the capacitative element can be improved due to the electrostatic capacitance of the capacitative element. Accordingly, a pulse signal transmitted from the plurality of avalanche photodiodes is easily detected, and light detection resolution can be further improved.

According to the aspect of the invention, there is provided a photodetector device capable of securing photodetection accuracy with a simple design in a configuration in which a plurality of avalanche photodiodes are formed on a semiconductor substrate formed from compound semiconductor.

Unless explicitly indicated as "embodiment according to the claimed invention", any embodiment in the description may include some but not all features as literally defined in the claims and are present for illustration purposes only. Hereinafter, an embodiment of the invention will be described in detail with reference to the accompanying drawings. Note that, in description, the same reference numeral will be given to the same elements or elements having the same function, and redundant description thereof will be omitted.

First, a whole configuration of a photodetector device according to this embodiment will be described with reference to <FIG>. <FIG> is a perspective view of the photodetector device according to this embodiment. <FIG> is a view illustrating a cross-sectional configuration of the photodetector device according to this embodiment. In <FIG>, hatching is omitted to improve visibility. <FIG> a plan view of a circuit substrate. <FIG> is a plan view illustrating a part of an avalanche photodiode array substrate. <FIG> is a view illustrating a circuit configuration capable of being used in the photodetector device according to this embodiment. <FIG> is a plan view illustrating a part of the circuit substrate.

As illustrated in <FIG>, a photodetector device <NUM> includes an avalanche photodiode array substrate <NUM> and a circuit substrate <NUM>. Hereinafter, "avalanche photodiode" is referred to as "APD". "Avalanche photodiode array substrate" is referred to as "APD array substrate". The circuit substrate <NUM> is disposed to face the APD array substrate <NUM>. The APD array substrate <NUM> and the circuit substrate <NUM> have a rectangular shape in plan view.

The APD array substrate <NUM> includes a main surface 10A and a main surface 10B which are opposite to each other, and a side surface 10C. The circuit substrate <NUM> includes a main surface 50A and a main surface 50B which are opposite to each other, and a side surface 50C. The main surface 10B of the APD array substrate <NUM> faces the main surface 50A of the circuit substrate <NUM>. A plan parallel to the respective main surfaces of the APD array substrate <NUM> and the circuit substrate <NUM> is an XY-axis plan, and a direction orthogonal to the respective main surface is a Z-axis direction.

The side surface 50C of the circuit substrate <NUM> is located on an outer side in the XY-axis plane direction in comparison to the side surface 10C of the APD array substrate <NUM>. That is, in plan view, an area of the circuit substrate <NUM> is greater than an area of the APD array substrate <NUM>. The side surface 10C of the APD array substrate <NUM> and the side surface 50C of the circuit substrate <NUM> may be flush with each other. In this case, in plan view, an outer edge of the APD array substrate <NUM> and an outer edge of the circuit substrate <NUM> match each other.

A glass substrate may be disposed on the main surface 10A of the APD array substrate <NUM>. The glass substrate and the APD array substrate <NUM> are optically connected to each other by an optical adhesive. The glass substrate may be directly formed on the APD array substrate <NUM>. The side surface 10C of the APD array substrate <NUM> and a side surface of the glass substrate may be flush with each other. In this case, in plan view, the outer edge of the APD array substrate <NUM> and the outer edge of the glass substrate match each other. In addition, the side surface 10C of the APD array substrate <NUM>, the side surface 50C of the circuit substrate <NUM>, and the side surface of the glass substrate may be flush with each other. In this case, in plan view, the outer edge of the APD array substrate <NUM>, the outer edge of the circuit substrate <NUM>, and the outer edge of the glass substrate match each other.

The APD array substrate <NUM> is mounted on the circuit substrate <NUM>. As illustrated in <FIG>, the APD array substrate <NUM> and the circuit substrate <NUM> are connected to each other by the bump electrode <NUM>. Specifically, as illustrated in <FIG>, the APD array substrate <NUM> is connected to the bump electrode <NUM> over a mounting region α disposed at the center of the circuit substrate <NUM> when viewed from a thickness direction of the APD array substrate <NUM>. In this embodiment, the mounting region α has a rectangular shape.

The circuit substrate <NUM> includes a ground line <NUM>, a cathode line <NUM>, and an anode line <NUM> at the periphery of the mounting region α. The ground line <NUM>, the cathode line <NUM>, and the anode line <NUM> extend from the mounting region α. The ground line <NUM> is connected to a ground electrode <NUM> to be described later. The cathode line <NUM> is electrically connected to the APD array substrate <NUM> mounted in the mounting region α, and can be used for application of a voltage to the APD array substrate <NUM>. The anode line <NUM> is connected to metal layers <NUM> and <NUM> to be described later, and is used in read-out of a signal transmitted from the APD array substrate <NUM>.

The APD array substrate <NUM> includes a plurality of APDs <NUM> which is arranged to operate in a Geiger mode. As illustrated in <FIG>, the plurality of APDs <NUM> are two-dimensionally arranged in a photodetection region β of the semiconductor substrate <NUM> when viewed from the thickness direction of the APD array substrate <NUM>. The photodetection region β has a rectangular shape, and overlaps the mounting region α of the circuit substrate <NUM> when viewed from the thickness direction of the APD array substrate <NUM>.

The APD array substrate <NUM> includes an N-type semiconductor substrate <NUM> formed from compound semiconductor. The semiconductor substrate <NUM> includes a substrate <NUM> formed from InP that forms the main surface 10A. A buffer layer <NUM> formed from InP, an absorption layer <NUM> formed from InGaAsP, an electric field relaxing layer <NUM> formed from InGaAsP, a multiplication layer <NUM> formed from InP are formed on the substrate <NUM> in this order from the main surface 10A side to the main surface 10B side. The absorption layer <NUM> may be formed from InGaAs. The semiconductor substrate <NUM> may be formed from GaAs, InGaAs, AlGaAs, InAlGaAs, CdTe, HgCdTe, or the like.

As illustrated in <FIG> and <FIG>, each of the APDs <NUM> is surrounded by an insulating portion <NUM> when viewed from the thickness direction of the APD array substrate <NUM>. The APD <NUM> includes a P-type active area <NUM> that is formed by doping the multiplication layer <NUM> with impurities from the main surface 10B side. Examples of the doping impurities include zinc (Zn). For example, the insulating portion <NUM> is provided by forming a polyimide film in a trench formed through wet etching or dry etching. The active area <NUM> formed in a circular shape when viewed from the thickness direction, and the insulating portion <NUM> is formed in an annular shape along an edge of the active area <NUM>. The insulating portion <NUM> reaches the substrate <NUM> from the main surface 10B side of the semiconductor substrate <NUM> in the thickness direction of the APD array substrate <NUM>.

<FIG> is a view illustrating a part of an avalanche photodiode array substrate capable of being used in photodetector device according to a modification example of this embodiment. As illustrated in <FIG>, the active area <NUM> may be formed in an approximately rectangular shape when viewed from the thickness direction. Here, the approximately rectangular shape is a rectangular shape with rounded corners. According to this, concentration of an electric field to the corners of the active area <NUM> is suppressed. In this case, the insulating portion <NUM> is formed in an annular shape along an edge of the active area <NUM> having an approximately rectangular shape.

The APD array substrate <NUM> includes an insulating layer <NUM> and a plurality of electrode pads <NUM>. The insulating layer <NUM> covers the semiconductor substrate <NUM> on the main surface 10B side. Each of the electrode pads <NUM> is formed on the semiconductor substrate <NUM> on the main surface 10B side for every APD <NUM>, and is in contact with the active area <NUM>. The electrode pad <NUM> is exposed from the insulating layer <NUM>, and is connected to the circuit substrate <NUM> through the bump electrode <NUM>.

As illustrated in <FIG>, the circuit substrate <NUM> is connected to the APD array substrate <NUM> on the main surface 50A side through the bump electrode <NUM>. The circuit substrate <NUM> includes a plurality of output unit <NUM>. As illustrated in <FIG>, the plurality of output units <NUM> are connected to each other in parallel, and forms one channel <NUM>. Each of the plurality of output units <NUM> is connected in series to each of the APDs <NUM> provided in the APD array substrate <NUM>. The output unit <NUM> includes a passive quenching element <NUM> and a capacitative element <NUM> which are connected to each other in parallel. Any of the passive quenching element <NUM> and the capacitative element <NUM> is connected in series to the APD <NUM>.

<FIG> is a view illustrating a circuit configuration capable of being used in a photodetector device according to a modification example of this embodiment. As illustrated in <FIG>, a plurality of channels <NUM> may be formed in the circuit substrate <NUM>. In this case, each of the channels <NUM> is formed by a plurality of output units <NUM> connected to each other in parallel. At least one of the plurality of channels <NUM> may be formed by the plurality of output units <NUM> connected to each other in parallel.

The circuit substrate <NUM> includes a silicon substrate <NUM>, and a wiring layer <NUM> stacked on the silicon substrate <NUM>. As illustrated in <FIG>, the silicon substrate <NUM> includes a P+ layer <NUM>, a P- layer <NUM>, and a P+ layer <NUM> in this order from the main surface 50B side to the main surface 50A side. The P+ layer <NUM> is provided by doping the P- layer <NUM> with impurities. The P+ layer <NUM> is provided by doping the P- layer <NUM> with impurities. Examples of the doping impurities in the P- layer <NUM> include boron. For example, an oxide film layer <NUM> formed in an element isolation process by thermal oxidation is provided between the silicon substrate <NUM> and the wiring layer <NUM>. The P+ layer <NUM> is exposed from the oxide film layer <NUM>, and is in contact with the wiring layer <NUM>.

The wiring layer <NUM> includes an insulating layer <NUM>, a ground electrode <NUM>, an electrode pad <NUM>, metal layers <NUM> and <NUM>, vias <NUM>, <NUM>, <NUM>, and <NUM>, polysilicon layers <NUM>, <NUM>, and <NUM>, and a dielectric layer <NUM>. The ground electrode <NUM>, the electrode pad <NUM>, the metal layers <NUM> and <NUM>, the vias <NUM>, <NUM>, <NUM>, and <NUM>, the polysilicon layers <NUM>, <NUM>, and <NUM>, and the dielectric layer <NUM> are provided for every APD <NUM>. The ground electrode <NUM>, the electrode pad <NUM>, and the metal layers <NUM> and <NUM> are formed in the same layer. In other words, the ground electrode <NUM>, the electrode pad <NUM>, and the metal layers <NUM> and <NUM> are formed at the same height in the thickness direction of the circuit substrate <NUM>.

For example, the insulating layer <NUM> is formed from SiO<NUM>. For example, the ground electrode <NUM>, the electrode pad <NUM>, and the metal layers <NUM> and <NUM> are formed from Al, AlCu, AlSiCu, or the like. The ground electrode <NUM>, the electrode pad <NUM>, and the metal layers <NUM> and <NUM> may be formed from the same material. For example, the vias <NUM>, <NUM>, <NUM>, and <NUM> is formed from tungsten (W). For example, the dielectric layer <NUM> is formed from SiO<NUM> or Si<NUM>N<NUM>.

The wiring layer <NUM> is covered with the insulating layer <NUM>. The P+ layer <NUM> of the silicon substrate <NUM> is connected to the via <NUM> exposed from the insulating layer <NUM> of the wiring layer <NUM> to the silicon substrate <NUM> side. The P+ layer <NUM> is connected to the ground electrode <NUM> through the via <NUM>. The ground electrode <NUM> is disposed with respect to the electrode pad <NUM> and the metal layers <NUM> and <NUM> through the insulating layer <NUM> at an arrangement height of the ground electrode <NUM> in the thickness direction of the circuit substrate <NUM>. The ground electrode <NUM> is not directly connected to the electrode pad <NUM> and the metal layers <NUM> and <NUM>.

The electrode pad <NUM> is exposed from the insulating layer <NUM> and is connected to the APD <NUM> through the bump electrode <NUM>. As illustrated in <FIG>, a plurality of the electrode pads <NUM> are two-dimensionally arranged on the main surface 50A side. Each of the electrode pads <NUM> is connected to the polysilicon layer <NUM> through the via <NUM>. The polysilicon layer <NUM> is connected to the metal layer <NUM> through the via <NUM>. The electrode pad <NUM> is disposed with respect to the metal layers <NUM> and <NUM> through the insulating layer <NUM> at an arrangement height of the electrode pad <NUM> in the thickness direction of the circuit substrate <NUM>. The electrode pad <NUM> is not directly connected to the metal layers <NUM> and <NUM>. The polysilicon layer <NUM> is included in a first polysilicon layer.

The polysilicon layer <NUM> constitutes the passive quenching element <NUM>. According to the above-described configuration, the passive quenching element <NUM> is connected in series to the APD <NUM> through the bump electrode <NUM>, the electrode pad <NUM>, and the via <NUM>. That is, a pulse signal transmitted from the APD <NUM> is input to the passive quenching element <NUM> through the bump electrode <NUM>, the electrode pad <NUM>, and the via <NUM>. The pulse signal input to the passive quenching element <NUM> is output from the channel <NUM> through the passive quenching element <NUM>, the via <NUM> and the metal layer <NUM>.

The electrode pad <NUM> is connected to the metal layer <NUM> at the arrangement height of the electrode pad <NUM> in the thickness direction of the circuit substrate <NUM>. The metal layer <NUM> is connected to the polysilicon layer <NUM> through the via <NUM>. The polysilicon layer <NUM> is stacked on the dielectric layer <NUM>. The dielectric layer <NUM> is stacked on the polysilicon layer <NUM>. The polysilicon layer <NUM> is connected to the metal layer <NUM> through a via (not illustrated). The polysilicon layer <NUM> and the polysilicon layer <NUM> are formed at the same height in the thickness direction of the circuit substrate <NUM>. The polysilicon layer <NUM> and the polysilicon layer <NUM> may be formed at the same height in the thickness direction of the circuit substrate <NUM>. The polysilicon layer <NUM> is included in a third polysilicon layer. The polysilicon layer <NUM> is included in a second polysilicon layer.

The polysilicon layer <NUM>, the dielectric layer <NUM>, and the polysilicon layer <NUM> constitute the capacitative element <NUM>. According to the above-described configuration, the capacitative element <NUM> is connected in series to the APD <NUM> through the bump electrode <NUM>, the electrode pad <NUM>, and the via <NUM>. That is, a pulse signal transmitted from the APD <NUM> is input to the polysilicon layer <NUM> of the capacitative element <NUM> through the bump electrode <NUM>, the electrode pad <NUM> and the via <NUM>. A pulse signal is output from the polysilicon layer <NUM> of the capacitative element <NUM> in correspondence with input of the pulse signal to the polysilicon layer <NUM> of the capacitative element <NUM>. The pulse signal output from the capacitative element <NUM> is output from the channel <NUM> through a via (not illustrated) and the metal layer <NUM>.

Both the passive quenching element <NUM> and the capacitative element <NUM> are electrically connected to the electrode pad <NUM> and the metal layer <NUM>. Accordingly, the passive quenching element <NUM> and the capacitative element <NUM> are connected to each other in parallel.

Next, an operational effect of the photodetector device <NUM> will be described with reference to <FIG>. <FIG> illustrates a pulse signal output from the APD <NUM>. As illustrated in <FIG>, a pulse signal <NUM> from the APD <NUM> is classified into a fast pulse <NUM> and a recharge pulse <NUM>. The fast pulse <NUM> is a pulse component having a peak value of the pulse signal. The recharge pulse <NUM> is a component that is detected after detection of the fast pulse <NUM> and has a pulse width longer than that of the fast pulse <NUM>.

<FIG> illustrates a waveform of a pulse signal output from the APD <NUM> in a state in which the capacitative element <NUM> is excluded from the output unit <NUM> and a resistance value of the passive quenching element <NUM> is set as a parameter. <FIG> is an integer graph in which a unit of the vertical axis is set as a current (A) and a unit of the horizontal axis is set as time (s). Each of a plurality of pieces of data a, b, c, and d is data of the pulse signal in a case where a passive quenching element <NUM> having a different resistance value is provided in the output unit <NUM>. In the order of the plurality of pieces of data a, b, c, and d, the passive quenching element <NUM> having a higher resistance value is provided.

As illustrated in <FIG>, the smaller the resistance value of the passive quenching element <NUM> is, the steeper an inclination of the recharge pulse <NUM> is. The steeper the inclination of the recharge pulse <NUM>, the shorter time necessary for quenching is, and the shorter dead time for which light is not detected by the APD <NUM> is. When using the passive quenching element <NUM> with a great resistance value, it is possible to realize appropriate quenching in which occurrence of a latching current or the like is suppressed. However, the greater the resistance value is, the further the dead time increases.

A pulse width of the pulse signal from the APD <NUM> connected to the passive quenching element <NUM> varies in response to the resistance value of the passive quenching element <NUM>. As illustrated in <FIG>, the greater the resistance value of the passive quenching element <NUM> is, the further the dead time of the APD <NUM> connected in series to the passive quenching element <NUM> increases. Accordingly, there is a demand for a circuit design including the passive quenching element <NUM> having an optimal resistance value to make appropriate quenching and a reduction of the dead time compatible with each other and to secure photodetection sensitivity and photodetection time resolution.

In the photodetector device <NUM>, a plurality of the output units <NUM> including the passive quenching element <NUM> and the capacitative element <NUM> are provided in the circuit substrate <NUM> separate from the APD array substrate <NUM>. According to this, a space capable of forming the plurality of output units <NUM> can be further expanded in comparison to a case where the plurality of output units <NUM> are arranged in the APD array substrate <NUM>. Accordingly, the design of the plurality of output units <NUM> becomes easy.

Since the plurality of output units <NUM> are provided in the circuit substrate <NUM> separate from the APD array substrate <NUM>, a parasitic capacitance that occurs between the configuration of the APD <NUM> and the output units <NUM> can be reduced. A manufacturing process different from that of the APD array substrate <NUM> can also be used. Since manufacturing processes which are respectively appropriate for the APD array substrate <NUM> and the circuit substrate <NUM> can be used, design of the plurality of output units <NUM> becomes easy.

<FIG> illustrates a waveform of a pulse signal output from the APD <NUM> in a state in which the passive quenching element <NUM> is set to a constant value, and an electrostatic capacitance of the capacitative element <NUM> is set as a parameter. <FIG> is a univariate graph in which a unit of the vertical axis is current (A) and a unit of the horizontal axis is time (s). Data a is data of a pulse signal in a case where the capacitative element <NUM> is excluded from the output unit <NUM>. Each of a plurality of pieces of data b, c, and d is data of a pulse signal in a case where a capacitative element <NUM> having a different electrostatic capacitance is provided in the output unit <NUM>. In the order of the plurality of pieces of data b, c, and d, the capacitative element <NUM> having a higher electrostatic capacitance is provided.

As illustrated in <FIG>, when the capacitative element <NUM> is provided, a peak value of the fast pulse <NUM> is improved. The higher the electrostatic capacitance of the capacitative element <NUM> is, the greater the peak value of the fast pulse <NUM> is. Accordingly, when providing the capacitative element <NUM>, time resolution of a pulse signal from the plurality of APDs <NUM> is improved. The greater the peak value of the fast pulse <NUM> is, the more easily the pulse signal from the plurality of APD <NUM> is detected.

In the photodetector device <NUM>, the capacitative element <NUM> that is connected in series to at least one of the APDs <NUM>, and is connected in parallel to the passive quenching element <NUM>. According to the configuration, the peak value of the pulse signal from the APD <NUM> that is connected in series to the capacitative element <NUM> can be improved based on the electrostatic capacitance of the capacitative element <NUM> due to the characteristics described with reference to <FIG>. Accordingly, the pulse signal from the plurality of APDs <NUM> is easily detected, and the photodetection time resolution can be improved. The photodetector device <NUM> can count the number of incident photons while realizing desired photodetection sensitivity and photodetection time resolution.

In a configuration in which the plurality of APDs <NUM> operate in the Geiger mode in the APD array substrate <NUM> formed from the compound semiconductor, electric field strength applied to the APDs <NUM> is reduced, and thus an influence of a noise can be suppressed.

The photodetector device <NUM> includes the polysilicon layers <NUM> and <NUM> provided on the circuit substrate <NUM>, the dielectric layer <NUM> provided on the polysilicon layer <NUM>, and the polysilicon layer <NUM> provided on the dielectric layer <NUM>. The passive quenching element <NUM> is formed by the polysilicon layer <NUM>, and the capacitative element <NUM> is formed by the polysilicon layer <NUM>, the dielectric layer <NUM>, and the polysilicon layer <NUM>. The polysilicon layer <NUM> is formed at the same height as in the polysilicon layer <NUM> or the polysilicon layer <NUM> in the thickness direction of the circuit substrate <NUM>. In this case, the plurality of output units <NUM> can be formed in a simple manufacturing process.

In an embodiment according to the claimed invention, the passive quenching element <NUM> is formed by a metal thin film instead of the polysilicon layer <NUM>. The capacitative element <NUM> is formed by two metal layers instead of the polysilicon layers <NUM> and <NUM>. In this case, the capacitative element <NUM> has a configuration in which two parallel metal layers sandwich the dielectric layer <NUM>.

Claim 1:
A photodetector device (<NUM>) comprising:
a first substrate (<NUM>) in which a plurality of avalanche photodiodes (<NUM>) arranged to operate in a Geiger mode are two-dimensionally arranged, the first substrate being formed from compound semiconductor; and
a second substrate (<NUM>) including a plurality of output units (<NUM>) connected to each other in parallel to form at least one channel (<NUM>), overlapping the first substrate, and being formed from silicon,
wherein:
each of the output units includes a passive quenching element (<NUM>) connected in series to at least one of the plurality of avalanche photodiodes,
the second substrate includes a capacitative element (<NUM>) connected in series to at least one of the avalanche photodiodes and connected in parallel to the passive quenching element,
the passive quenching element is formed by a metal thin film provided in the second substrate,
the capacitative element is formed by a second metal layer provided in the second substrate, a dielectric layer (<NUM>) stacked on the second metal layer, and a third metal layer stacked on the dielectric layer, and
the metal thin film is formed at the same height as the second metal layer or the third metal layer in a thickness direction of the second layer.