Patent Description:
The present disclosure relates to digital counter circuits and methods of operating a digital counter circuit and, in particular, a method and apparatus for determining a voltage level output from the digital counter circuit.

Traditional digital in-pixel read-out integrated circuits (DROICs) include an analog-to-digital converter (ADC) to convert the residual or remaining accumulated charge stored in an integration capacitor (sometimes referred to as a well capacitor) into a digital signal representing a binary value. This DROIC architecture offers improved photo-charge capacity even as the desired size of unit cells continues to shrink. A traditional DROIC design includes a quantizing analog front end circuit which accumulates charge on the integration capacitor and is reset (i.e., discharged) each time the charge on the integration capacitor reaches a charge threshold. The pattern of charging (i.e., the trigger) and then resetting is repeated as the photo-current integrates. Each trigger event is recorded, i.e., "counted", using a digital counter circuit. Upon completion of each frame, a snapshot is taken by copying the digital counter contents to a snapshot register and the residual charge remaining on the integration capacitor is measured by an ADC. The total charge accumulated in the DROIC is then determined based on the recorded counts and any residual voltage stored on the integration capacitor. The effect is to exponentially increase charge capacity while maintaining low signal capability with a relatively small unit pixel cell size.

For further background, <CIT> describes an image sensor that includes a plurality of self-resetting pixels including: a mechanism converting detected electromagnetic energy into a proportional electric current; an integrating capacitor including a mechanism for fast charging to a first electric level and for controlled discharging to a second electric level; a mechanism for comparing the controlled discharge; a loop back mechanism, allowing automatic repetition of fast charging and controlled discharging cycles and counting of number of cycles occurring during a determined integration time; a mechanism measuring a residual electric charge present in the integrating capacitor on completion of the integration period; and a calibration mechanism using the measurement mechanism to measure and compensate for operating and production dispersions specific to each pixel.

<CIT> describes a digital unit cell comprising an integrator circuit, a dynamic comparator configured to compare an integration voltage of the integrator circuit with a reference voltage, provide a first pulse signal each time the integration voltage is less than the reference voltage, and provide a second pulse signal each time the integration voltage exceeds the reference voltage, a multiplexer configured to receive a count direction control signal, and a counter element configured to increment a count value each time the first pulse signal or the second pulse signal is received, wherein the multiplexer is configured to couple a first output of the dynamic comparator to the counter element when the count direction control signal is in a first state, and to couple a second output of the dynamic comparator to the counter element when the count direction control signal is in a second state.

<CIT> describes an imaging system that includes an array of pixel cells and a plurality of digital memory elements disposed physically separate from and coupled to the array of pixel cells. Each of the pixel cells includes a photodetector, an electrical storage device coupled to the photodetector, and quantization circuitry coupled to the electrical storage device. The photodetector is configured to generate a photo-current in response to light impinging thereon. The electrical storage device is configured to accumulate an electrical charge from the photocurrent. The quantization circuitry is configured to convert the electrical charge into an analog quantization event signal. Each of the digital memory elements is in electrical communication with at least one of the pixel cells and is configured to store a digital value in response to receiving the analog quantization event signal from the at least one of the pixel cells.

There is provided a unit cell included in a digital pixel circuit according to claim <NUM> and a digital pixel circuit according to claim <NUM>.

There is also provided a method of operating a unit cell according to claim <NUM>.

The subject matter which is regarded as the disclosure is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the disclosure are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:.

The DROIC needs a calibration method for each pixel to align the digital counter with the ADC at the point where the digital counter is incremented. Referring to <FIG>, the threshold for a digital count event is set by the reference voltage (Vref) for that given pixel and must be determined to maintain the linearity as shown in <FIG> at higher signal levels. The complexity of calibrating each pixel is lengthy and requires finding the threshold at which the point the digital counter is triggered at least once. The proposed technique is achieved using a single frame of video thereby allowing the counter to trigger only once and disallowing any more charge accumulation on the integration capacitor, and at the end of the frame time use the ADC to sample the charge on the integration capacitor which triggered the counter event.

During operation, the DROIC aims to measure the residual charge at the end of a frame period on the integration capacitor using the ADC. According to a first non-limiting embodiment shown in <FIG>, the repeated charging and resetting of the integration capacitor may result in one or more overshoot events during which the integration capacitor briefly charges above the charge threshold and an exact quanta of charge is subtracted from the integration capacitor.

According to a second non-limiting embodiment shown in <FIG>, the DROIC always resets to the same reference. For example, the signal charges integration capacitor (Cint), and the comparator triggers a reset based on the voltage charge of the capacitor, i.e., Cint (Q=CV). In response to the trigger event, the digital counter is incremented, and the charge is dumped from the integration capacitor (Cint). The operation is repeated until the end of the frame, while the ADC samples the remaining charge of the integration capacitor (Cint).

In either architecture described above, the overshoot events are signal and sampling rate dependent resulting in increased temporal noise.

To compensate for the aforementioned residue phenomena, a calibration is necessary between the residue and the counter. However, calibration of the DROIC is proven difficult and challenging using conventional calibration techniques. One known calibration technique, for example, attempts to calibrate the DROIC based on a comparator and comparator threshold. This technique, however, requires a controlled environment so that the integration time can be adjusted to capture a residual value prior to triggering the counter. Another known technique aims to adjust the flux level with a fixed integration time to determine the point where the non-linear response meets the flux. However, this technique is extremely time consuming and requires a controlled environment.

Various non-limiting embodiments described herein provide a DROIC circuit, which includes a disable circuit capable of invoking a calibration mode to dynamically determine the output of the ADC at the time the counter is triggered (i.e., at the integration capacitor charge threshold). The calibration technique described herein takes advantage of the fact the ADC dynamic range contains the charge threshold at which the counter triggers and uses the time at which the counter triggers (i.e., the charge threshold) as a voltage reference (Vref) used for the calibration. The calibration mode facilities the calibration technique by preventing the immediate reset of the integration capacitor and allowing utilization of the ADC output to measure the current charge in in response to triggering the counter. In other words, the disable circuit prevents the immediate reset of the integration capacitor, thereby allowing the integration capacitor to hold its charge until the end of the frame period. Accordingly, a more precise measurement of the charge on the integration capacitor can be obtained by analyzing the output of the ADC at the end of the frame time. Thus, a relationship is established between the residue and the counter trigger time (i.e., Vref) which provides the DROIC calibration.

Turning now to <FIG>, a block diagram illustrating an image capture device <NUM> that may be used to capture images according to aspects described herein. For example, device <NUM> may be a digital camera, video camera, or other photographic and/or image capturing equipment. Image capture device <NUM> comprises an image sensor <NUM> and an image processing unit <NUM>. The image sensor <NUM> may be an Active Pixel Sensor (APS) or other suitable light sensing device that can capture images. The image processing unit <NUM> may be a combination of hardware, software, and/or firmware that is operable to receive signal information from the image sensor <NUM> and convert the signal information into a digital image.

The image sensor <NUM> includes an array <NUM> of unit cells <NUM>. Each unit cell <NUM> accumulates charge proportional to the light intensity at that location in the field of view and provides an indication of the intensity of light at that location to the image processing unit <NUM>. Each unit cell <NUM> may correspond to a pixel in the captured electronic image.

A particular method for image capture using image capture device <NUM> is referred to as ripple read. Ripple read is a method that processes each row of unit cells from image sensor <NUM> in order. Ripple read may process the top row of unit cells of image sensor <NUM>, followed by the second row, followed by the third row, and so forth until the last row of unit cells of image sensor <NUM> is processed. A ripple reset operation to reset the rows of unit cells of image sensor <NUM> may be performed similarly.

These methods may be performed on consecutive rows. For example, a ripple capture operation may begin with the first row of image sensor <NUM>. As the ripple capture operation moves to the second row, a ripple read operation may begin on the first row of image sensor <NUM>. After the ripple capture operation moves to the third row, the ripple read operation may begin on the second row and a ripple reset operation may begin on the first row. This may continue until the last row is processed. Once the last row is processed, the image may be processed, stored, and/or transmitted by the image processing unit <NUM>.

Turning to <FIG>, a block diagram illustrating a digital pixel circuit <NUM> according to aspects described herein. The digital pixel circuit <NUM> includes one of the unit cells <NUM> and the image processing unit <NUM>. The unit cell <NUM> includes an image detector <NUM> and a DROIC <NUM>.

The image detector <NUM> includes a light sensor <NUM>, an energy storage device <NUM> coupled to the light sensor <NUM>, and other components, as discussed above. The image detector <NUM> is coupled to a corresponding DROIC <NUM>. The energy storage device <NUM> includes, for example, an integration capacitor <NUM>, and the light sensor <NUM> includes, for example, a photodiode <NUM>. The DROIC <NUM> is coupled to the image processing unit <NUM>. Although the DROIC <NUM> and the imaging processing unit <NUM> are shown as separate components, it should be appreciated that other embodiments allow for a DROIC <NUM> that can perform the functions of the image processing unit <NUM> described above.

The image processing unit <NUM> is coupled to an external system video electronics module <NUM> via an interface <NUM>. According to at least one embodiment, the digital pixel circuit <NUM> also includes a cryo-electronics module <NUM> that is configured to control the temperature of the DROIC <NUM>. In other embodiments, however, the cryo-electronics module <NUM> may not be included.

Turning now to <FIG>, a schematic diagram of a DROIC unit cell <NUM> (referred to herein as a DROIC pixel) is illustrated according to a non-limiting embodiment. The DROIC pixel <NUM> includes a detector circuit <NUM>, a disable circuit <NUM>, and a sample and hold (SH) circuit <NUM>. The detector circuit <NUM> includes a photodiode <NUM>, an integration capacitor <NUM>, a comparator <NUM>, and a deactivation transistor <NUM>. The photodiode <NUM> is configured to detect a light signal <NUM> (e.g., light photons <NUM>), and the integration capacitor <NUM> is configured to store an electrical charge induced in response to the impinging light signal <NUM> (e.g., light photons <NUM>) upon the photodiode <NUM>.

The disable circuit <NUM> is configured to invoke a normal mode and a calibration mode of the DROIC pixel <NUM>. When the disable circuit <NUM> is invoked in the normal mode (e.g., a "<NUM>" bit signal is applied to the calibration mode input (Cal)), the photodiode <NUM> accumulates an electric charge that is proportional to the intensity of the received light photons <NUM>. As charge accumulates on the photodiode <NUM>, the voltage across the integration capacitor <NUM> increases until reaching a charge threshold (Vref). In response to reaching the charge threshold (Vref), a counter trigger event occurs and the integrating capacitor <NUM> is discharged (the accumulated charge is dumped) effectively resetting the integrating capacitor <NUM>. In turn, the voltage on the Cint terminal of the comparator <NUM> drops below a voltage reference (Vref), thereby changing the value of the comparator output. The changed output is recorded as a reset event <NUM> by the reset counter <NUM>. The integration capacitor <NUM> again charges and the process described above is repeated until the last frame is completed.

When the disable circuit <NUM> is invoked in the calibration mode (e.g., a "<NUM>" bit signal is applied to the calibration mode input (Cal)), the detector circuit <NUM> is disconnected via the deactivation transistor <NUM>, while the reset disabling transistor <NUM> is switched on. The reset disabling transistor <NUM> is connected in parallel with the integration capacitor <NUM>. Accordingly, switching on the reset disabling transistor <NUM> maintains a bias voltage (Vbias) across the integrating capacitor <NUM> rather than allowing the integrating capacitor <NUM> to reset and dump its accumulated charge. The SH circuit <NUM> is then able to output the existent charge on the integrating capacitor <NUM> to an ADC, which can then obtain a more precise measurement of the accumulated charge. Once the ADC measurement is obtained, the disable circuit <NUM> can be transitioned back into the normal mode and the process described above can be repeated.

<FIG>is a block diagram illustrating operation of the digital pixel circuit <NUM> with respect to an input light signal <NUM> (including background and modulated light) incident on the detector <NUM>, a count enable signal <NUM> transmitted from the image processing unit <NUM> to the DROIC <NUM>, and DROIC <NUM> total reset count values <NUM>. <FIG> and <FIG> are graphs <NUM> illustrating a trace <NUM> representing voltage across the integration capacitor <NUM> of the detector <NUM> as the input light signal <NUM> is incident on the detector <NUM>.

The detector <NUM> is arranged to receive light from a desired scene. The light received from the scene may include background light from the scene and/or pulsed light from a modulated light source in the scene. The background and modulated light from the scene are received by the detector <NUM> as an input light signal <NUM> including both the background and the modulated (i.e., pulsed) light. In one embodiment, the input light signal <NUM> has a frequency of <NUM>-<NUM>; however, in other embodiments, the input light signal <NUM> may have different characteristics. As the input light signal <NUM> (including background and modulated light) is incident on the detector <NUM> (e.g., via a lens adjacent the detector <NUM>), the detector <NUM> accumulates an electric charge (e.g. generated by its photodiode <NUM> and stored in its integration capacitor <NUM>) proportional to the intensity of the light incident on the detector <NUM>. As charge accumulates on the detector <NUM> (i.e., on the integration capacitor <NUM> of the detector <NUM>), the voltage <NUM> across the integration capacitor <NUM> increases (e.g., as shown in the graphs <NUM> of <FIG> and <FIG>) until reaching the charge threshold (Vref). In response to reaching the charge threshold (Vref), a counter trigger event <NUM> occurs and the integration capacitor <NUM> is discharged (the accumulated charge is dumped) such that the voltage <NUM> drops (e.g., returns to Vrst).

When the detector <NUM> begins to integrate the input light signal <NUM>, the image processing unit <NUM> transmits a high count enable signal <NUM> to the DROIC <NUM>. The high count enable signal <NUM> activates an integration reset counting feature of the DROIC <NUM> (see <FIG> and <FIG>). More specifically, when the count enable signal <NUM> is high, the DROIC <NUM> actively counts reset events of the detector <NUM>. For example, as shown in graphs <NUM> of <FIG> and <FIG>, when the voltage <NUM> across the integration capacitor <NUM> reaches a predefined integration threshold (Vref) <NUM> and the count enable signal <NUM> is high, the detector <NUM> discharges the capacitor and the DROIC <NUM> increments a reset counter <NUM>. Assuming light is still incident on the detector <NUM>, the detector <NUM> again accumulates charge. When the voltage <NUM> across the integration capacitor <NUM> again reaches the predefined integration threshold <NUM> and the count enable signal <NUM> is still high, the detector <NUM> discharges the integration capacitor <NUM> and the DROIC <NUM> again increments the reset counter <NUM>. As shown in the graphs <NUM> of <FIG> and <FIG>, this cycle may continue until the entire input light signal <NUM> has been integrated, i.e., from the frame start to the frame end. According to one non-limiting embodiment, the DROIC <NUM> increments the reset counter <NUM> at a rate of at least <NUM>. In other embodiments, however, the DROIC <NUM> can increment the reset counter <NUM> at some other frequency. Following completion of the integrated signals, a voltage residue <NUM> is present which has a value that falls in between Vref and Vrst.

The image processing unit <NUM> monitors the rate at which the DROIC <NUM> increments the reset counter <NUM> (i.e., the count rate of the DROIC <NUM>). If the count rate of the DROIC <NUM> does not exceed a count rate threshold, the image processing unit <NUM> maintains the count enable signal <NUM> in a high state. When the count enable signal <NUM> is maintained at a high state, the DROIC <NUM> actively counts reset events (i.e., increments the reset counter <NUM>) of the detector <NUM>. If the count rate of the DROIC <NUM> exceeds the count rate threshold, the image processing unit <NUM> transmits a low count enable signal <NUM> to the DROIC <NUM>. The low count enable signal <NUM> deactivates the integration reset counting feature of the DROIC <NUM>. More specifically, when the count enable signal <NUM> is low, the DROIC <NUM> ignores (i.e., does not count) reset events of the detector <NUM>. For example, when the voltage <NUM> across the integration capacitor <NUM> reaches a predefined integration threshold <NUM> and the count enable signal <NUM> is low, the detector <NUM> discharges the capacitor <NUM>, but the DROIC <NUM> does not increment the reset counter <NUM>. When the count rate of the DROIC <NUM> again drops below the count rate threshold, the image processing unit <NUM> again transmits a high count enable signal <NUM> to the DROIC <NUM> and the DROIC <NUM> again counts reset events of the detector <NUM>.

Periodically (e.g., once per frame), the image processing unit <NUM> retrieves the value <NUM> of the DROIC's <NUM> reset counter <NUM> (i.e., the number of times that the DROIC <NUM> has counted a reset event of the detector <NUM>). As shown in <FIG>, the image processing unit <NUM> is coupled to the single DROIC <NUM> (of the single unit cell <NUM>). However, where the image processing unit <NUM> is coupled to each unit cell <NUM> in the array <NUM> of unit cells <NUM> (i.e., to the DROIC <NUM> and corresponding detector <NUM> of each unit cell <NUM>), the image processing unit <NUM> is configured to periodically retrieve reset counter values from each DROIC <NUM> in the array <NUM>. The image processing unit <NUM> processes the retrieved reset counter values from each DROIC <NUM> in the array <NUM> to generate image information (e.g., a digital image) based on the reset counter value(s). The image processing unit <NUM> may transmit the image information to an external system video electronics module <NUM>. The external system video electronics module <NUM> may further process the image information and/or transmit the image information to an end user <NUM>. The end user may be an individual user or a system that is configured to analyze and/or further process the image information (e.g., via advanced algorithms).

<FIG> is a graph <NUM> illustrating a signal trace <NUM> representing voltage across the integration capacitor <NUM> when invoking a calibration mode of a DROIC <NUM> according to a non-limiting embodiment. As shown in <FIG>, a counter trigger event <NUM> occurs in response to the voltage <NUM> reaching the charge threshold (VRef). In response to triggering the counter <NUM>, the detector <NUM> is disconnected. Accordingly, although the counter <NUM> has effectively been triggered, the integration capacitor <NUM> is not "reset" and instead maintains its charge. The charge on the integration capacitor <NUM> can be defined as ΔQ, i.e., the difference between the charge threshold (Vref) of the integration capacitor <NUM> and the reset voltage (Vrst), e.g., the capacitor's minimum voltage capacity. Once the frame completes, the output of the ADC is obtained which indicates the existent charge on the integration capacitor <NUM>. Because the integration capacitor <NUM> is prevented from being reset, the ADC output measures the existent charge on the capacitor <NUM>, as opposed to the voltage residue <NUM> that may be measured during the normal operating mode (see <FIG> and <FIG>). By preventing occurrence of the residue <NUM>, the ADC obtains a more precise measurement of the charge on the integration capacitor <NUM>. In effect, the "residue" output (R') would be viewed as being equal to the actual measured ADC output (A') indicative of the existent charge on the integration capacitor, thereby achieving a proper calibration.

It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.

Claim 1:
A unit cell (<NUM>) included in a digital pixel circuit, the unit cell (<NUM>) comprising:
an image detector (<NUM>) that includes a light sensor (<NUM>) configured to detect a light signal and an energy storage device (<NUM>) configured to accumulate an electrical charge during a frame; and
a digital readout integrated circuit, DROIC, including a disable circuit (<NUM>) in signal communication with the image detector (<NUM>), the disable circuit (<NUM>) configured to selectively invoke a first mode configured to determine a total electrical charge of the DROIC based on a plurality of accumulated electrical charges obtained over a plurality of frames, and a second mode configured to calibrate the DROIC based on a single accumulated charge obtained during a single frame among the plurality of frames,
wherein the disable circuit (<NUM>) is configured to connect the light sensor (<NUM>) to the energy storage device (<NUM>) in response to invoking the first mode, and to disconnect the light sensor (<NUM>) from the energy storage device (<NUM>) in response to invoking the second mode;
wherein the disable circuit (<NUM>) is configured to allow the energy storage device (<NUM>) to discharge in response to the electrical charge reaching a charge threshold level while operating in the first mode;
wherein the disable circuit (<NUM>) includes a switch (<NUM>) connected in parallel with the energy storage device (<NUM>), and
wherein the switch (<NUM>) is activated in response to invoking the second mode such that the switch (<NUM>) delivers a bias voltage across the energy storage device (<NUM>) to prevent the energy storage device (<NUM>) from discharging.