Patent Description:
High bandwidth input/output (I/O) requirements drive increases in the number of high-speed I/O lanes, which results in more pins on I/O connectors. Vertical I/O connectors (e.g., X4, X8, and X16 Peripheral Component Interconnect (PCI) Card Edge Mechanical (CEM) connectors) have electrical lines/traces between the connector pins of the same length. However, non-vertical (e.g., orthogonal) I/O connectors have different length lines/traces between the connectors pins as certain of the traces must traverse a longer distance versus others. As a result, electrical performance between the different lines/traces of the connector may vary, especially with wider connectors having more I/O lanes.

<CIT> discloses a modular, high speed and high density electrical connector with separately shielded signal conductor pairs. The connector may be assembled from modules, each containing a pair of signal conductors with surrounding partially or fully conductive material. Modules of different sizes may be assembled into wafers, which are then assembled into a connector. Wafers may include lossy material. In some embodiments, shielding members of two mating connectors may each have compliant members along their distal portions, such that, the shielding members engage at points of contact at multiple locations, some of which are adjacent the mating edge of each of the mating shielding members.

<CIT> discloses a pin-rematched PCI-E flexible riser card, provided with pins whose positions are defined and ordered by a PCIe interface. The pins are re-matched according to the matching principle of a high-speed differential signal, and the pins may be matched with such flexible material as a wire arrangement, a side-by-side wire arrangement, and a flexible circuit board. Thus, in physical terms, many problems such as PCI-E flexible riser card transmission obstruction caused by the absence remaining from a PCIe interface, or a signal being incomplete, are resolved.

<CIT> discloses an electrical connector with electrically shielded terminals. The electrical connector includes a housing and a lead frame held by the housing. The lead frame includes a terminal extending along a length between a mating end portion and a mounting end portion. The terminal is at least partially surrounded by a dielectric core extending a length along at least a portion of the length of the terminal. The dielectric core is metallized such that the core is at least partially surrounded by an electrically conductive shell.

<CIT> discloses a Gen3 PCIe Riser consisting of four PCIe x16 slots, a PCIe switch, external power, a remote programming interface, and a PCIe edge connector. The PCIe switch is programmed to allow any PCIe device installed in a PCIe slot to communicate directly through the switch with another PCIe device installed in another PCIe slot on the Riser without using the processing power of a Central Processing Unit thereby increasing system efficiency. In alternative embodiments, two Gen3 PCIe Risers are cross-connected to allow for more direct communication between any PCIe devices installed in the system. External power is connected when the PCIe devices require more power than available from a standard PCIe slot. The external programming interface allows for the configuration of the PCIe switch to be modified to meet system demands.

Advantageous embodiments are described by the dependent claims.

In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present disclosure. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven't been described in detail in order to avoid unnecessarily obscuring the present disclosure.

Higher bandwidth requirements are driving an increase in the number of high-speed lanes for I/O connectors, resulting in more pins on the I/O connectors, such as Peripheral Component Interconnect Express (PCIe) Card Edge Mechanical (CEM) connector (including x4, x8, and x16 PCIe CEM connectors). Vertical I/O card connectors may have the same pin lengths across the connector, so increasing the number of lanes makes little difference on the connector's electrical performance (since the comparative lengths of the lines/traces of the connector do not change as the number of lanes increases).

However, some implementations call for non-vertical (e.g., orthogonal) I/O connectors, which may have different length lines/traces between the connectors pins as certain of the traces must traverse a longer distance versus others. As a result, electrical performance between the different lines/traces of the connector may vary, especially with wider connectors having more I/O lanes.

<FIG> illustrates an example system <NUM> that includes an input/output (I/O) connector <NUM> in accordance with embodiments of the present disclosure. The example system <NUM> includes a system-on-chip (SoC) <NUM> coupled to a motherboard <NUM>, and also includes an I/O device <NUM> coupled to the motherboard <NUM> through the I/O connector <NUM>. The I/O connector <NUM> connects to the motherboard <NUM> through an edge connector socket <NUM> on the motherboard. The motherboard <NUM> includes a trace <NUM> that connects the SoC <NUM> to the I/O device <NUM> through the edge connector socket <NUM> and I/O connector <NUM>. The I/O device <NUM> includes an edge connector that inserts into the I/O connector <NUM> (e.g., into a socket of the connector configured similarly to the socket <NUM>), and the I/O connector <NUM> connects to the edge connector socket <NUM> using an edge connector mechanism similar to the edge connector of the I/O device <NUM>. In some instances, the edge connector/connector sockets may be PCIe-compatible edge connectors/connector sockets (e.g., x4, x8, or x16 PCIe connectors), which may be used by PCIe devices as well as Compute Express Link (CXL) devices.

The I/O connector <NUM> of the system <NUM> may be configured in a similar manner to any of the I/O connectors described herein. For example, the I/O connector <NUM> may include high speed cabling that connects each side of the I/O connector <NUM>, i.e., the side that couples to the I/O device <NUM> and the side that couples to the edge connector socket <NUM>. The high-speed cabling may be shielded differential cabling, and may include twinaxial cabling, coaxial cabling, twisted pair cabling, or any other suitable high speed cabling mechanism. The high-speed cabling of the I/O connector <NUM> may provide one or more benefits including improved electrical performance, over traditional I/O connectors that include direct pin-to-pin wiring, e.g., a "paddle card" connection mechanism that utilizes traces (of unequal length) on a printed circuit board (PCB) that is connected between each edge connector of the I/O device <NUM>.

<FIG> illustrates a perspective view of an example input/output (I/O) connector <NUM> in accordance with embodiments of the present disclosure. The example I/O connector <NUM> includes four PCIe-compatible edge connector sockets <NUM> as well as four edge connectors <NUM>, with each edge connector socket <NUM> corresponding to a respective edge connector <NUM>. The example I/O connector <NUM> is an orthogonal connector, similar to the I/O connector <NUM> of <FIG>.

An orthogonal connector such as the I/O connector <NUM> may provide benefits in a rack mounted server chassis, for example, where cards can be placed into bays within the system to provide better serviceability and more efficient cooling. However, there are a few challenges with orthogonal connectors. As one example, the orthogonal connector will have different pin lengths across the edge connectors. For instance, as shown in <FIG>, the connection between the first connector pins toward the bottom portion of the I/O connector <NUM> (the shorter radius portion) may have a length L1 that is much shorter than the length Ln of the n-th connection between the connector pins at the top portion of the I/O connector <NUM> (the larger radius portion). As a result, some connections between pins may be extremely long, especially in wider connectors, which can result in different electrical performance across the connector for certain pins, e.g. worse loss, cross talk, impedance mis-match, etc. This mismatched electrical performance can limit the data rate, in some instances, to below what is needed to match a required bandwidth (e.g., a bandwidth required for high-speed memory devices).

<FIG> illustrates an example orthogonal I/O connector <NUM> with fixed lines between pins. The example I/O connector <NUM> includes a first connector <NUM> and a second connector <NUM> connected by lines <NUM>. The example I/O connector <NUM> may be implemented with direct pin connections, where each pins of the connectors <NUM>, <NUM> is embedded in the housing of the connector <NUM> and connected via wires (<NUM>), or may be implemented with a paddle card connection, where both connectors <NUM>, <NUM> have a straddle-mounted connector soldered onto a middle paddle card, which includes a PCB with traces (<NUM>) connecting the pins of the connectors <NUM>, <NUM>. As shown, the length of the line 303N is much longer than that of line 303A, and accordingly, has much worse electrical performance as described above. In addition, connectors with direct pins connections may be difficult to manufacture as more lanes are added, and every lane added makes the electrical performance for those added lanes worse. Moreover, crosstalk is another concern with these devices. Furthermore, connectors with paddle card connections use a PCB for interconnecting the connector pins, and each connector transition may result in larger loss. The PCB may also be lossy at high-speed data rates.

Another challenge is that CXL-based memory devices may require a PCIe-compatible x8 connector to meet the current generation (DDR5) memory bandwidth. The larger x8 connector will make the pin lengths longer than the x4 connector, which will further degrade electrical performance and further limit the bandwidth.

<FIG> illustrates an example I/O device <NUM> in accordance with embodiments of the present disclosure. The example I/O device <NUM> includes bridge circuitry <NUM>, voltage regulator circuitry <NUM>, device circuitry <NUM>, and an edge connector <NUM> for coupling the I/O device <NUM> to an edge connector socket (e.g., one of the sockets <NUM> of the I/O device <NUM> of <FIG>). In the example shown, the edge connector <NUM> is a PCIe-compatible x8 connector.

In some embodiments, the I/O device <NUM> may be a CXL-based memory device that includes volatile memory (e.g., dynamic random-access memory (DRAM) modules) or non-volatile memory as part of the device circuitry <NUM>. Through the use of a connector in accordance with the present disclosure, the CXL interface may be able to match the bandwidth required by DRAM modules. The bridge circuitry <NUM> may convert a native interface for the device circuitry <NUM> to the I/O interface. For example, the bridge circuitry <NUM> may convert a native memory interface to CXL and/or additional circuitry to support the memory or bridge.

<FIG> illustrate example I/O connectors <NUM>, <NUM> with internal cable connections between pins in accordance with embodiments of the present disclosure. The example connector <NUM> is orthogonal I/O connector, while the example connector <NUM> is a vertical connector. The I/O connector includes a first connector <NUM>, <NUM> and a second connector <NUM>, <NUM> coupled to a rigid housing <NUM>, <NUM>. In the example shown, the first connector <NUM>, <NUM> is an edge connector to connect the I/O device to an edge connector socket of a motherboard, while the second connector <NUM>, <NUM> is an edge connector socket to receive an edge connector of an I/O device.

In the examples shown, the signal pins (e.g., <NUM>) of the first and second connectors of the I/O devices <NUM>, <NUM> are connected together via high-speed shielded differential cables503, <NUM>-that is, pairs of pins of the first connector are connected with respective pairs of pins of the second connector through the high-speed cables <NUM>, <NUM>. The high-speed cables may be twinaxial, coaxial, twisted pair, or another type of high-speed different cable. In certain embodiments, the high-speed cables <NUM>, <NUM> may be directly soldered onto the high speed differential pins <NUM>, <NUM>. In addition, the I/O connectors <NUM>, <NUM> also include a ground bar (e.g., <NUM>) in each of the connectors <NUM>, <NUM>, <NUM>, <NUM> to connect the ground pins together, and in certain instances, also connect to the ground shield layer of the cables <NUM>, <NUM> to provide a common ground.

High-speed cables have much lower loss, better impedance control, and less crosstalk than traces on a PCB, so the I/O connectors <NUM>, <NUM> will have much better SI performance than the connector <NUM> of <FIG>. In addition, since the high-speed cables are fully shielded, there will be little to no crosstalk inside the housing <NUM>, <NUM>. Thus, the whole connector may see significant crosstalk reduction, compared to a traditional orthogonal connector. The lower crosstalk and less insertion loss seen on a connector such as <NUM>, <NUM> can be used to extend motherboard routing or PCB layer count reduction or cheaper PCB material, which will drive the system performance improvement and costs down.

Table <NUM> below shows a loss comparison between PCB and high-speed cables, such as the ones that would be incorporated into embodiments of the present disclosure. In particular, Table <NUM> shows a comparison of losses in dB/inch for a <NUM> AWG twinaxial or coaxial cable against medium loss (ML) and low loss (LL) stripline and ML/LL microstrip lines for a <NUM> signal. As shown, the <NUM> AWG cable only has <NUM>% of the loss of LL PCB microstrip. Thus, a connector with a ~<NUM> inch length will save ~<NUM> dB in the whole channel for a PCIe Gen5 implementation.

<FIG> illustrate example simulation results for an I/O connector in accordance with embodiments of the present disclosure as compared with a current I/O connector design. In particular, <FIG> illustrates link simulation results for a CXL <NUM> connection speed of <NUM> Gbps, and <FIG> illustrates link simulation results for a PCIe <NUM> connection speed of 64Gbps with PAM4 signaling. The vertical dashed red lines in each of <FIG>, <FIG> represent the eye mask requirements at the respective data rates. The link simulation is for a topology similar to the one shown in <FIG>, with a <NUM> inch motherboard trace and a <NUM> inch I/O device board trace, with the "<FIG>" bars representing a connector design similar to the connector <NUM> of <FIG> having a pedal card containing <NUM> inch low loss microstrip line and the "<FIG>" bars representing a connector design similar the connector <NUM> of <FIG>, having shielded <NUM> inch AWG <NUM> cables between the connectors as described above. The full link simulation was performed for both scenarios at CXL <NUM> speed (32Gbps), shown in <FIG>, and at PCIe <NUM> speed (<NUM> Gbps, PAM4 signaling), shown in <FIG>.

As shown in <FIG>, at <NUM> Gbps, using the high-speed cabling significantly improves the link performance by ~<NUM> mV in eye height and ~ <NUM> UI in eye width. This improvement comes at least from: <NUM>) the loss advantage of using internal cabling, and <NUM>) the crosstalk advantage of a well-shielded cable. With the pedal card simulation, the full channel loss is about <NUM> dB @<NUM>. , while with the AWG30 cable simulation, the total loss is <NUM> dB, which is <NUM> dB less. At the CXL <NUM> speed (32Gbps), the performance advantage of the connector with high-speed cabling as described herein may allow for longer channel reach or more choices on interconnect components.

As the data rate increases, the loss and crosstalk advantages become more and more beneficial. As shown in <FIG>, the eye size when the link is running at PCIe <NUM> speed (64Gbps, PAM4) is much improved with the high-speed cabled connector as described herein. For instance, with the pedal card simulation, there is almost no open eye (EH < <NUM> mV, EW < <NUM> UI), while with the high-speed cable simulation, the eye height and eye width still be are able to meet the PCIe <NUM> requirements (i.e., eye height > <NUM> mV, eye width > <NUM> UI). Therefore, a connector with internal high-speed cabling as described herein may also provide scalability for the next generation(s) of CXL speeds.

<FIG> illustrate example interconnect embodiments in which aspects of the present disclosure may be incorporated. Referring to <FIG>, an embodiment of a fabric composed of point-to-point Links that interconnect a set of components is illustrated. System <NUM> includes processor <NUM> and system memory <NUM> coupled to controller hub <NUM>. Processor <NUM> includes any processing element, such as a microprocessor, a host processor, an embedded processor, a co-processor, or other processor. Processor <NUM> is coupled to controller hub <NUM> through front-side bus (FSB) <NUM>. In one embodiment, FSB <NUM> is a serial point-to-point interconnect as described below. In another embodiment, link <NUM> includes a serial, differential interconnect architecture that is compliant with different interconnect standard. In some implementations, the system may include logic to implement multiple protocol stacks and further logic to negotiation alternate protocols to be run on top of a common physical layer, among other example features.

System memory <NUM> includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system <NUM>. System memory <NUM> is coupled to controller hub <NUM> through memory interface <NUM>. Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

In one embodiment, controller hub <NUM> is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnection hierarchy. Examples of controller hub <NUM> include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processor <NUM>, while controller <NUM> is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex <NUM>.

Here, controller hub <NUM> is coupled to switch/bridge <NUM> through serial link <NUM>. Input/output modules <NUM> and <NUM>, which may also be referred to as interfaces/ports <NUM> and <NUM>, include/implement a layered protocol stack to provide communication between controller hub <NUM> and switch <NUM>. In one embodiment, multiple devices are capable of being coupled to switch <NUM>.

Switch/bridge <NUM> routes packets/messages from device <NUM> upstream, i.e. up a hierarchy towards a root complex, to controller hub <NUM> and downstream, i.e. down a hierarchy away from a root controller, from processor <NUM> or system memory <NUM> to device <NUM>. Switch <NUM>, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device <NUM> includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices. Often in the PCIe vernacular, such as device, is referred to as an endpoint. Although not specifically shown, device <NUM> may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices. Endpoint devices in PCIe are often classified as legacy, PCIe, or root complex integrated endpoints.

Graphics accelerator <NUM> is also coupled to controller hub <NUM> through serial link <NUM>. In one embodiment, graphics accelerator <NUM> is coupled to an MCH, which is coupled to an ICH. Switch <NUM>, and accordingly I/O device <NUM>, is then coupled to the ICH. I/O modules <NUM> and <NUM> are also to implement a layered protocol stack to communicate between graphics accelerator <NUM> and controller hub <NUM>. Similar to the MCH discussion above, a graphics controller or the graphics accelerator <NUM> itself may be integrated in processor <NUM>. Further, one or more links (e.g., <NUM>) of the system can include one or more extension devices (e.g., <NUM>), such as retimers, repeaters, etc..

Turning to <FIG> an embodiment of a layered protocol stack is illustrated. Layered protocol stack <NUM> includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the discussion below relates to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack <NUM> is a PCIe protocol stack including transaction layer <NUM>, link layer <NUM>, and physical layer <NUM>. An interface, such as interfaces <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>, may be represented as communication protocol stack <NUM>. Representation as a communication protocol stack may also be referred to as a module or interface implementing/including a protocol stack.

PCI Express uses packets to communicate information between components. Packets are formed in the Transaction Layer <NUM> and Data Link Layer <NUM> to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their Physical Layer <NUM> representation to the Data Link Layer <NUM> representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer <NUM> of the receiving device.

In one embodiment, transaction layer <NUM> is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer <NUM> and physical layer <NUM>. In this regard, a primary responsibility of the transaction layer <NUM> is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The translation layer <NUM> typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e., transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.

In addition, PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of the receive buffers in Transaction Layer <NUM>. An external device at the opposite end of the link, such as controller hub <NUM> in <FIG>, counts the number of credits consumed by each TLP. A transaction may be transmitted if the transaction does not exceed a credit limit. Upon receiving a response an amount of credit is restored. An advantage of a credit scheme is that the latency of credit return does not affect performance, provided that the credit limit is not encountered.

In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a <NUM>-bit address, or a long address format, such as <NUM>-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message space transactions (or, simply messages) are defined to support in-band communication between PCIe agents.

Therefore, in one embodiment, transaction layer <NUM> assembles packet header/payload <NUM>. Format for current packet headers/payloads may be found in the PCIe specification at the PCIe specification website.

Link layer <NUM>, also referred to as data link layer <NUM>, acts as an intermediate stage between transaction layer <NUM> and the physical layer <NUM>. In one embodiment, a responsibility of the data link layer <NUM> is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components a link. One side of the Data Link Layer <NUM> accepts TLPs assembled by the Transaction Layer <NUM>, applies packet sequence identifier <NUM>, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC <NUM>, and submits the modified TLPs to the Physical Layer <NUM> for transmission across a physical to an external device.

In one embodiment, physical layer <NUM> includes logical sub block <NUM> and electrical sub-block <NUM> to physically transmit a packet to an external device. Here, logical sub-block <NUM> is responsible for the "digital" functions of Physical Layer <NUM>. In this regard, the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block <NUM>, and a receiver section to identify and prepare received information before passing it to the Link Layer <NUM>.

Physical block <NUM> includes a transmitter and a receiver. The transmitter is supplied by logical sub-block <NUM> with symbols, which the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized and supplied to logical sub-block <NUM>. In one embodiment, an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames <NUM>. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

As stated above, although transaction layer <NUM>, link layer <NUM>, and physical layer <NUM> are discussed in reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented. As an example, a port/interface that is represented as a layered protocol includes: (<NUM>) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.

A variety of other interconnect architectures and protocols may utilize the concepts discussed herein. In one example, Compute Express Link (CXL) may be used. CXL maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost, among other example advantages. CXL enables communication between host processors (e.g., CPUs) and a set of workload accelerators (e.g., graphics processing units (GPUs), field programmable gate array (FPGA) devices, tensor and vector processor units, machine learning accelerators, purpose-built accelerator solutions, among other examples).

A CXL link may be a low-latency, high-bandwidth discrete or on-package link that supports dynamic protocol multiplexing of coherency, memory access, and input/output (I/O) protocols. Among other applications, a CXL link may enable an accelerator to access system memory as a caching agent and/or host system memory, among other examples. CXL is a dynamic multi-protocol technology designed to support a vast spectrum of accelerators. CXL provides a rich set of protocols that include I/O semantics similar to PCIe (CXL. io), caching protocol semantics (CXL. cache), and memory access semantics (CXL. mem) over a discrete or on-package link. Based on the particular accelerator usage model, all of the CXL protocols or only a subset of the protocols may be enabled. In some implementations, CXL may be built upon the well-established, widely adopted PCIe infrastructure (e.g., PCIe <NUM>), leveraging the PCIe physical and electrical interface to provide advanced protocol in areas include I/O, memory protocol (e.g., allowing a host processor to share memory with an accelerator device), and coherency interface.

Turning to <FIG>, a simplified block diagram <NUM> is shown illustrating an example system utilizing a CXL link <NUM>. For instance, the link <NUM> may interconnect a host processor <NUM> (e.g., CPU) to an accelerator device <NUM>. In this example, the host processor <NUM> includes one or more processor cores (e.g., 915a-b) and one or more I/O devices (e.g., <NUM>). Host memory (e.g., <NUM>) may be provided with the host processor (e.g., on the same package or die). The accelerator device <NUM> may include accelerator logic <NUM> and, in some implementations, may include its own memory (e.g., accelerator memory <NUM>). In this example, the host processor <NUM> may include circuitry to implement coherence/cache logic <NUM> and interconnect logic (e.g., PCIe logic <NUM>). CXL multiplexing logic (e.g., 955a-b) may also be provided to enable multiplexing of CXL protocols (e.g., I/O protocol 935a-b (e.g., CXL. io), caching protocol 940a-b (e.g., CXL. cache), and memory access protocol 945a-b (CXL. mem)), thereby enabling data of any one of the supported protocols (e.g., 935a-b, 940a-b, 945a-b) to be sent, in a multiplexed manner, over the link <NUM> between host processor <NUM> and accelerator device <NUM>.

In some implementations, a Flex BusTM port may be utilized in concert with CXL-compliant links to flexibly adapt a device to interconnect with a wide variety of other devices (e.g., other processor devices, accelerators, switches, memory devices, etc.). A Flex Bus port is a flexible high-speed port that is statically configured to support either a PCIe or CXL link (and potentially also links of other protocols and architectures). A Flex Bus port allows designs to choose between providing native PCIe protocol or CXL over a high-bandwidth, off-package link. Selection of the protocol applied at the port may happen during boot time via auto negotiation and be based on the device that is plugged into the slot. Flex Bus uses PCIe electricals, making it compatible with PCIe retimers, and adheres to standard PCIe form factors for an add-in card.

<FIG> illustrates a simplified block diagram illustrating an example port architecture <NUM> (e.g., Flex Bus) utilized to implement CXL links. For instance, Flex Bus architecture may be organized as multiple layers to implement the multiple protocols supported by the port. For instance, the port may include transaction layer logic (e.g., <NUM>), link layer logic (e.g., <NUM>), and physical layer logic (e.g., <NUM>) (e.g., implemented all or in-part in circuitry). For instance, a transaction (or protocol) layer (e.g., <NUM>) may be subdivided into transaction layer logic <NUM> that implements a PCIe transaction layer <NUM> and CXL transaction layer enhancements <NUM> (for CXL. io) of a base PCIe transaction layer <NUM>, and logic <NUM> to implement cache (e.g., CXL. cache) and memory (e.g., CXL. mem) protocols for a CXL link. Similarly, link layer logic <NUM> may be provided to implement a base PCIe data link layer <NUM> and a CXL link layer (for CXl. io) representing an enhanced version of the PCIe data link layer <NUM>. A CXL link layer <NUM> may also include cache and memory link layer enhancement logic <NUM> (e.g., for CXL. cache and CXL.

Continuing with the example of <FIG>, a CXL link layer logic <NUM> may interface with CXL arbitration/multiplexing (ARB/MUX) logic <NUM>, which interleaves the traffic from the two logic streams (e.g., PCIe/CXL. io and CXL. mem), among other example implementations. During link training, the transaction and link layers are configured to operate in either PCIe mode or CXL mode. In some instances, a host CPU may support implementation of either PCIe or CXL mode, while other devices, such as accelerators, may only support CXL mode, among other examples. In some implementations, the port (e.g., a Flex Bus port) may utilize a physical layer <NUM> based on a PCIe physical layer (e.g., PCIe electrical PHY <NUM>). For instance, a Flex Bus physical layer may be implemented as a converged logical physical layer <NUM> that can operate in either PCIe mode or CXL mode based on results of alternate mode negotiation during the link training process. In some implementations, the physical layer may support multiple signaling rates (e.g., <NUM> GT/s, <NUM> GT/s, <NUM> GT/s, etc.) and multiple link widths (e.g., x16, x8, x4, x2, x1, etc.). In PCIe mode, links implemented by the port <NUM> may be fully compliant with native PCIe features (e.g., as defined in the PCIe specification), while in CXL mode, the link supports all features defined for CXL. Accordingly, a Flex Bus port may provide a point-to-point interconnect that can transmit native PCIe protocol data or dynamic multi-protocol CXL data to provide I/O, coherency, and memory protocols, over PCIe electricals, among other examples.

The CXL I/O protocol, CXL. io, provides a non-coherent load/store interface for I/O devices. Transaction types, transaction packet formatting, credit-based flow control, virtual channel management, and transaction ordering rules in CXL. io may follow all or a portion of the PCIe definition. CXL cache coherency protocol, CXL. cache, defines the interactions between the device and host as a number of requests that each have at least one associated response message and sometimes a data transfer. The interface consists of three channels in each direction: Request, Response, and Data.

The CXL memory protocol, CXL. mem, is a transactional interface between the processor and memory and uses the physical and link layers of CXL when communicating across dies. mem can be used for multiple different memory attach options including when a memory controller is located in the host CPU, when the memory controller is within an accelerator device, or when the memory controller is moved to a memory buffer chip, among other examples. mem may be applied to transaction involving different memory types (e.g., volatile, persistent, etc.) and configurations (e.g., flat, hierarchical, etc.), among other example features. In some implementations, a coherency engine of the host processor may interface with memory using CXL. mem requests and responses. In this configuration, the CPU coherency engine is regarded as the CXL. mem Master and the Mem device is regarded as the CXL. mem Subordinate. mem Master is the agent which is responsible for sourcing CXL. mem requests (e.g., reads, writes, etc.) and a CXL. mem Subordinate is the agent which is responsible for responding to CXL. mem requests (e.g., data, completions, etc.). When the Subordinate is an accelerator, CXL. mem protocol assumes the presence of a device coherency engine (DCOH). This agent is assumed to be responsible for implementing coherency related functions such as snooping of device caches based on CXL. mem commands and update of metadata fields. In implementations, where metadata is supported by device-attached memory, it can be used by the host to implement a coarse snoop filter for CPU sockets, among other example uses.

<FIG> below provide some example computing devices/systems/environments and associated hardware that may be used in the context of embodiments as described herein.

Referring to <FIG>, an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor <NUM> includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor <NUM>, in one embodiment, includes at least two cores-core <NUM> and <NUM>, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor <NUM> may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.

Physical processor <NUM>, as illustrated in <FIG>, includes two cores-core <NUM> and <NUM>. Here, core <NUM> and <NUM> are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core <NUM> includes an out-of-order processor core, while core <NUM> includes an in-order processor core. However, cores <NUM> and <NUM> may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core <NUM> are described in further detail below, as the units in core <NUM> operate in a similar manner in the depicted embodiment.

As depicted, core <NUM> includes two hardware threads 1101a and 1101b, which may also be referred to as hardware thread slots 1101a and 1101b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor <NUM> as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 1101a, a second thread is associated with architecture state registers 1101b, a third thread may be associated with architecture state registers 1102a, and a fourth thread may be associated with architecture state registers 1102b. Here, each of the architecture state registers (1101a, 1101b, 1102a, and 1102b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 1101a are replicated in architecture state registers 1101b, so individual architecture states/contexts are capable of being stored for logical processor 1101a and logical processor 1101b. In core <NUM>, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block <NUM> may also be replicated for threads 1101a and 1101b. Some resources, such as re-order buffers in reorder/retirement unit <NUM>, ILTB <NUM>, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB <NUM>, execution unit(s) <NUM>, and portions of out-of-order unit <NUM> are potentially fully shared.

Processor <NUM> often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In <FIG>, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core <NUM> includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer <NUM> to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) <NUM> to store address translation entries for instructions.

Core <NUM> further includes decode module <NUM> coupled to fetch unit <NUM> to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1101a, 1101b, respectively. Usually core <NUM> is associated with a first ISA, which defines/specifies instructions executable on processor <NUM>. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic <NUM> includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders <NUM>, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders <NUM>, the architecture or core <NUM> takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new sor old instructions. Note decoders <NUM>, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders <NUM> recognize a second ISA (either a subset of the first ISA or a distinct ISA).

In one example, allocator and renamer block <NUM> includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 1101a and 1101b are potentially capable of out-of-order execution, where allocator and renamer block <NUM> also reserves other resources, such as reorder buffers to track instruction results. Unit <NUM> may also include a register renamer to rename program/instruction reference registers to other registers internal to processor <NUM>. Reorder/retirement unit <NUM> includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

Scheduler and execution unit(s) block <NUM>, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

Lower level data cache and data translation buffer (D-TLB) <NUM> are coupled to execution unit(s) <NUM>. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.

Here, cores <NUM> and <NUM> share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface <NUM>. Note that higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s). In one embodiment, higher-level cache is a last-level data cache-last cache in the memory hierarchy on processor <NUM>-such as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache-a type of instruction cache-instead may be coupled after decoder <NUM> to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).

In the depicted configuration, processor <NUM> also includes on-chip interface module <NUM>. Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor <NUM>. In this scenario, on-chip interface <NUM> is to communicate with devices external to processor <NUM>, such as system memory <NUM>, a chipset (often including a memory controller hub to connect to memory <NUM> and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus <NUM> may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

Memory <NUM> may be dedicated to processor <NUM> or shared with other devices in a system. Common examples of types of memory <NUM> include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device <NUM> may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor <NUM>. For example in one embodiment, a memory controller hub is on the same package and/or die with processor <NUM>. Here, a portion of the core (an on-core portion) <NUM> includes one or more controller(s) for interfacing with other devices such as memory <NUM> or a graphics device <NUM>. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface <NUM> includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link <NUM> for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory <NUM>, graphics processor <NUM>, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

In one embodiment, processor <NUM> is capable of executing a compiler, optimization, and/or translator code <NUM> to compile, translate, and/or optimize application code <NUM> to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

Larger compilers often include multiple phases, but most often these phases are included within two general phases: (<NUM>) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (<NUM>) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.

Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (<NUM>) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (<NUM>) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (<NUM>) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (<NUM>) a combination thereof.

Referring now to <FIG>, shown is a block diagram of another system <NUM> in accordance with an embodiment of the present disclosure. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. Each of processors <NUM> and <NUM> may be some version of a processor. In one embodiment, <NUM> and <NUM> are part of a serial, point-to-point coherent interconnect fabric, such as a high-performance architecture. As a result, certain embodiments may be implemented within the QPI architecture.

While shown with only two processors <NUM>, <NUM>, it is to be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

Processors <NUM> and <NUM> are shown including integrated memory controller units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> also exchanges information with a high-performance graphics circuit <NUM> via an interface circuit <NUM> along a high-performance graphics interconnect <NUM>.

A shared cache (not shown) may be included in either processor or outside of both processors; yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

In one embodiment, first bus <NUM> may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown in <FIG>, various I/O devices <NUM> are coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, second bus <NUM> includes a low pin count (LPC) bus. Various devices are coupled to second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which often includes instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> is shown coupled to second bus <NUM>. Note that other architectures are possible, where the included components and interconnect architectures vary. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

The foregoing disclosure has presented a number of example mechanisms for delivering power to PCIe add-in cards through additional edge finger tabs. It should be appreciated that other mechanisms may be provided in addition to those identified above without departing from the more generalized principles contained within this disclosure. For instance, while some of the example power delivery mechanisms discussed herein were described with reference to PCIe or PCIe-based protocols, it should be appreciated that similar, corresponding enhancements may be made to other interconnect protocols, such OpenCAPI™, Gen-Z™, UPI, Universal Serial Bus, (USB), Cache Coherent Interconnect for Accelerators (CCIX™), Advanced Micro Device™'s (AMD™) Infinity™, Common Communication Interface (CCI), or Qualcomm™'s Centriq™ interconnect, among others.

While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom.

A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

Use of the phrase 'configured to,' in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still 'configured to' perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a <NUM> or a <NUM> during operation. But a logic gate 'configured to' provide an enable signal to a clock does not include every potential logic gate that may provide a <NUM> or <NUM>. Instead, the logic gate is one coupled in some manner that during operation the <NUM> or <NUM> output is to enable the clock. Note once again that use of the term 'configured to' does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.

Furthermore, use of the phrases 'to,' 'capable of/to,' and or 'operable to,' in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.

A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as <NUM>'s and <NUM>'s, which simply represents binary logic states. For example, a <NUM> refers to a high logic level and <NUM> refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of <NUM> and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.

Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.

The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.

Instructions used to program logic to perform certain embodiments may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

The following example embodiments pertain to embodiments in accordance with this Specification.

Example embodiment <NUM> includes an apparatus comprising: a rigid housing; a first connector coupled to the housing, the first connector being configured to receive an edge connector of an input/output, I/O, device; and a second connector coupled to the housing, the second connector being configured to couple to an edge connector socket; wherein pairs of electrical connection pins of the first connector are coupled to respective pairs of electrical connection pins of the second connector via shielded differential cables inside the housing, wherein the apparatus comprises a first set of electrical connection pins of the first connector coupled to a first set of electrical connection pins of the second connector via shielded differential cables inside the housing, and a second set of electrical connection pins of the first connector coupled to a second set of electrical connection pins of the second connector via printed circuit board, PCB, stripline wiring.

Example embodiment <NUM> includes the subject matter of Example embodiment <NUM>, wherein the shielded differential cables are twinaxial cables or coaxial cables.

Example embodiment <NUM> includes the subject matter of Example embodiment <NUM> or <NUM>, wherein the first and second connectors each comprise a ground bar coupling a set of electrical connection pins of the connectors other than the pairs connected to the shielded differential cables.

Example embodiment <NUM> includes the subject matter of Example embodiment <NUM>, wherein the ground bar is connected to the shielding of each shielded differential cable inside the housing.

Example embodiment <NUM> includes the subject matter of any one of Example embodiments <NUM>-<NUM>, wherein the first connector housing is oriented orthogonally to the second connector housing.

Example embodiment <NUM> includes the subject matter of any one of Example embodiments <NUM>-<NUM>, wherein the first connector is configured to receive a Peripheral Component Interconnect Express, PCIe,-compatible I/O device, and the second connector is configured to couple to a PCIe-compatible edge connector socket.

Example embodiment <NUM> includes the subject matter of any one of Example embodiments <NUM>-<NUM>, further comprising: a fourth connector coupled to the housing, the fourth connector being configured to receive an edge connector of an input/output, I/O, device; a fifth connector coupled to the housing, the fifth connector being configured to couple to an edge connector socket; wherein pairs of electrical connection pins of the fourth connector are coupled to respective pairs of electrical connection pins of the fifth connector via shielded differential cables inside the housing.

Example embodiment <NUM> includes a system comprising: a motherboard; a system-on-chip, SoC, comprising a processor, the SoC coupled to the motherboard; and the apparatus of any one of Example embodiments <NUM> to <NUM>; wherein the apparatus is coupled to the motherboard and is electrically coupled to the SoC through the motherboard, and the second connector of the apparatus is coupled to an edge connector socket of the motherboard.

Example embodiment <NUM> includes the subject matter of any one of Example embodiments <NUM>-<NUM>, wherein the ground bar is connected to the shielding of each shielded differential cable inside the housing.

Example embodiment <NUM> includes the subject matter of any one of Example embodiments <NUM>-<NUM>, further comprising an I/O device coupled to the first connector.

Example embodiment <NUM> includes the subject matter of any one of Example embodiments <NUM>-<NUM>, wherein the first connector is configured to receive an edge connector of a first I/O device, the second connector is coupled to a first edge connector socket of the motherboard, and the I/O device connector further comprises: a fourth connector coupled to the housing, the fourth connector being configured to receive an edge connector of a second I/O device; a fifth connector coupled to the housing, the fifth connector coupled to a second edge connector socket of the mother board; wherein pairs of electrical connection pins of the fourth connector are coupled to respective pairs of electrical connection pins of the fifth connector via shielded differential cables inside the housing.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure.

In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. The specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense.

Claim 1:
An apparatus comprising:
a rigid housing (<NUM>, <NUM>);
a first connector (<NUM>, <NUM>, <NUM>) coupled to the housing (<NUM>, <NUM>), the first connector (<NUM>, <NUM>, <NUM>) being configured to receive an edge connector (<NUM>, <NUM>) of an input/output, I/O, device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>); and a second connector (<NUM>, <NUM>, <NUM>) coupled to the housing (<NUM>, <NUM>), the second connector (<NUM>, <NUM>, <NUM>) being configured to couple to an edge connector socket (<NUM>, <NUM>, <NUM>);
wherein pairs of electrical connection pins of the first connector (<NUM>, <NUM>, <NUM>) are coupled to respective pairs of electrical connection pins of the second connector (<NUM>, <NUM>, <NUM>) via shielded differential cables inside the housing (<NUM>, <NUM>),
characterized in that
the apparatus comprises a first set of electrical connection pins of the first connector (<NUM>, <NUM>, <NUM>) coupled to a first set of electrical connection pins of the second connector (<NUM>, <NUM>, <NUM>) via shielded differential cables inside the housing (<NUM>, <NUM>), and a second set of electrical connection pins of the first connector (<NUM>, <NUM>, <NUM>) coupled to a second set of electrical connection pins of the second connector (<NUM>, <NUM>, <NUM>) via printed circuit board, PCB, stripline wiring.