Patent Description:
Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, Ultrabooks™, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).

<CIT> discloses a method for managing power in a data processing system having multiple components, including determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components.

<CIT> discloses methods and systems for managing current consumption in a portable computing device. A duration of time associated with a maximum allowable current consumption through a voltage regulator is divided into a plurality of N sub-durations. The current consumption for each sub-duration is monitored and a moving sum of current consumption is calculated for a plurality of past sub-durations. Using the sum of current consumption, a current budget for a next sub-duration or next set of consecutive sub-durations may be determined.

In various embodiments, a processor is configured to dynamically determine independently controllable maximum current consumption capabilities for each of multiple processing circuits of the processor. For example, the processor may be a multicore processor or other system on chip (SoC) including a variety of different processing circuits including general-purpose processing cores, graphics processors and so forth. With embodiments herein, a power controller may dynamically determine independent current consumption limits for each of the processing circuits based at least in part on information received from a software entity, such as an operating system or other scheduler, or an application itself. Such information may identify relative priority or importance of the different processing circuits for a given workload, such that dynamic, independent and controllable current consumption values can be provided on a per core (or other processing circuit) basis.

In this way, when a power excursion is encountered during operation, throttling of individual processing circuits may be performed independently so as to have as limited effect on a workload in execution as possible. In contrast, conventional throttling of processing circuits occurs with predefined static amounts of throttling when a power excursion occurs. Such static arrangement is set to satisfy an entire spectrum of workload behavior and is not optimal for any given case. Instead with embodiments, by dynamically configuring allowable current consumption by individual processing circuits, an optimal throttling behavior may be realized for any given workload in execution.

As high level examples, consider a first workload case that is core-centric and has a minor amount of graphics processing. Consider a second workload case where the cores are not heavily used, and the graphics processor is highly used. With appropriate hint information provided by a software entity, dynamic and controllable determination of maximum current consumption levels by these different processing circuits can be provided and enforced. As such, for the first workload, where the cores may be performing work that impacts workload responsiveness, such cores may not be throttled to the extent that the graphics processors are throttled. Instead for the second workload case where the graphics processors may be performing user-visible work, higher levels of throttling may occur as to cores than for the graphics processors. As such, different processing circuits may be throttled differently based on different workloads that may be in execution.

With embodiments, a software interface enables a software entity, such as runtime software, driver, firmware or other software entity to provide dynamic programming of throttling information, to optimize current sharing between disparate processing circuits of a processor. In this way, performance may be improved in current constrained scenarios.

Although the following embodiments are described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or processors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer systems. That is, disclosed embodiments can be used in many different system types, ranging from server computers (e.g., tower, rack, blade, micro-server and so forth), communications systems, storage systems, desktop computers of any configuration, laptop, notebook, and tablet computers (including <NUM>:<NUM> tablets, phablets and so forth), and may be also used in other devices, such as handheld devices, systems on chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones such as smartphones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may typically include a microcontroller, a digital signal processor (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system that can perform the functions and operations taught below. More so, embodiments may be implemented in mobile terminals having standard voice functionality such as mobile phones, smartphones and phablets, and/or in non-mobile terminals without a standard wireless voice function communication capability, such as many wearables, tablets, notebooks, desktops, micro-servers, servers and so forth. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatuses, and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a 'green technology' future, such as for power conservation and energy efficiency in products that encompass a large portion of the US economy.

Referring now to <FIG>, shown is a block diagram of a portion of a system in accordance with an embodiment of the present invention. As shown in <FIG>, system <NUM> may include various components, including a processor <NUM> which as shown is a multicore processor. Processor <NUM> may be coupled to a power supply <NUM> via an external voltage regulator <NUM>, which may perform a first voltage conversion to provide a primary regulated voltage to processor <NUM>.

As seen, processor <NUM> may be a single die processor including multiple cores <NUM>a-<NUM>n. In addition, each core may be associated with an integrated voltage regulator (IVR) <NUM>a-<NUM>n which receives the primary regulated voltage and generates an operating voltage to be provided to one or more agents of the processor associated with the IVR. Accordingly, an IVR implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual core. As such, each core can operate at an independent voltage and frequency, enabling great flexibility and affording wide opportunities for balancing power consumption with performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated and supplied by the IVR to only those components in the group. During power management, a given power plane of one IVR may be powered down or off when the processor is placed into a certain low power state, while another power plane of another IVR remains active, or fully powered.

Still referring to <FIG>, additional components may be present within the processor including an input/output interface <NUM>, another interface <NUM>, and an integrated memory controller <NUM>. As seen, each of these components may be powered by another integrated voltage regulator <NUM>x. In one embodiment, interface <NUM> may be enable operation for an Intel®. Quick Path Interconnect (QPI) interconnect, which provides for point-to-point (PtP) links in a cache coherent protocol that includes multiple layers including a physical layer, a link layer and a protocol layer. In turn, interface <NUM> may communicate via a Peripheral Component Interconnect Express (PCIe™) protocol.

Also shown is a power control unit (PCU) <NUM>, which may include hardware, software and/or firmware to perform power management operations with regard to processor <NUM>. As seen, PCU <NUM> provides control information to external voltage regulator <NUM> via a digital interface to cause the voltage regulator to generate the appropriate regulated voltage. PCU <NUM> also provides control information to IVRs <NUM> via another digital interface to control the operating voltage generated (or to cause a corresponding IVR to be disabled in a low power mode). In various embodiments, PCU <NUM> may include a variety of power management logic units to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or management power management source or system software).

Furthermore, while <FIG> shows an implementation in which PCU <NUM> is a separate processing engine (which may be implemented as a microcontroller), understand that in some cases in addition to or instead of a dedicated power controller, each core may include or be associated with a power control agent to more autonomously control power consumption independently. In some cases a hierarchical power management architecture may be provided, with PCU <NUM> in communication with corresponding power management agents associated with each of cores <NUM>.

One power management logic included in PCU <NUM> may be a dynamic current sharing control circuit that is configured to dynamically determine independent maximum current consumption values for each core <NUM> and/or additional processing circuits. As will be described further herein this control circuitry may provide a dynamically configurable maximum current consumption value to each of cores <NUM> to enable each core <NUM> to operate according to this constraint. As such, when PCU <NUM> identifies a condition that triggers a throttle event, a throttle signal may be sent to the cores <NUM>. In turn, each core <NUM> may limit its operation to its dynamically identified maximum current consumption value. In this way, different cores may operate at asymmetric performance states, particularly when a throttle event is identified, such that a minimal impact to user-facing workloads occurs.

While not shown for ease of illustration, understand that additional components may be present within processor <NUM> such as additional control circuitry, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth. Furthermore, while shown in the implementation of <FIG> with an integrated voltage regulator, embodiments are not so limited.

Note that the power management techniques described herein may be independent of and complementary to an operating system (OS)-based power management (OSPM) mechanism. According to one example OSPM technique, a processor can operate at various performance states or levels, so-called P-states, namely from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that can be requested by an OS. Embodiments described herein may enable dynamic changes to the guaranteed frequency of the P1 performance state, based on a variety of inputs and processor operating parameters. In addition to this P1 state, the OS can further request a higher performance state, namely a P0 state. This P0 state may thus be an opportunistic or turbo mode state in which, when power and/or thermal budget is available, processor hardware can configure the processor or at least portions thereof to operate at a higher than guaranteed frequency. In many implementations a processor can include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, exceeding to a maximum peak frequency of the particular processor, as fused or otherwise written into the processor during manufacture. In addition, according to one OSPM mechanism, a processor can operate at various power states or levels. With regard to power states, an OSPM mechanism may specify different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states), with each C-state being at a lower power consumption level (such that C6 is a deeper low power state than C1, and so forth).

Understand that many different types of power management techniques may be used individually or in combination in different embodiments. As representative examples, a power controller may control the processor to be power managed by some form of dynamic voltage frequency scaling (DVFS) in which an operating voltage and/or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In an example, DVFS may be performed using Enhanced Intel SpeedStep™ technology available from Intel Corporation, Santa Clara, Calif. , to provide optimal performance at a lowest power consumption level. In another example, DVFS may be performed using Intel TurboBoost™ technology to enable one or more cores or other compute engines to operate at a higher than guaranteed operating frequency based on conditions (e.g., workload and availability).

Another power management technique that may be used in certain examples is dynamic swapping of workloads between different compute engines. For example, the processor may include asymmetric cores or other processing engines that operate at different power consumption levels, such that in a power constrained situation, one or more workloads can be dynamically switched to execute on a lower power core or other compute engine. Another exemplary power management technique is hardware duty cycling (HDC), which may cause cores and/or other compute engines to be periodically enabled and disabled according to a duty cycle, such that one or more cores may be made inactive during an inactive period of the duty cycle and made active during an active period of the duty cycle. Although described with these particular examples, understand that many other power management techniques may be used in particular embodiments.

Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to <FIG>, shown is a block diagram of a processor in accordance with an embodiment of the present invention. As shown in <FIG>, processor <NUM> may be a multicore processor including a plurality of cores <NUM>a-<NUM>n. In one embodiment, each such core may be of an independent power domain and can be configured to enter and exit active states and/or maximum performance states based on workload. The various cores may be coupled via an interconnect <NUM> to a system agent <NUM> that includes various components. As seen, system agent <NUM> may include a shared cache <NUM> which may be a last level cache. In addition, the system agent may include an integrated memory controller <NUM> to communicate with a system memory (not shown in <FIG>), e.g., via a memory bus. System agent <NUM> also includes various interfaces <NUM> and a power control unit <NUM>, which may include logic to perform the power management techniques described herein. In the embodiment shown, power control unit <NUM> includes a dynamic current sharing control circuit <NUM> that may dynamically determine, based at least in part on software-provided hint information, dynamic current consumption values for each of cores <NUM>. Dynamic current sharing control circuit <NUM> may communicate such dynamic current consumption values to cores <NUM> for their storage and internal use to control their current consumption independently, particularly when a throttle event is identified.

In addition, by interfaces 250a-250n, connection can be made to various off-chip components such as peripheral devices, mass storage and so forth. While shown with this particular implementation in the embodiment of <FIG>, the scope of the present invention is not limited in this regard.

Referring now to <FIG>, shown is a block diagram of a multi-domain processor in accordance with another embodiment of the present invention. As shown in the embodiment of <FIG>, processor <NUM> includes multiple domains. Specifically, a core domain <NUM> can include a plurality of cores <NUM><NUM>-<NUM>n, a graphics domain <NUM> can include one or more graphics engines, and a system agent domain <NUM> may further be present. In some embodiments, system agent domain <NUM> may execute at an independent frequency than the core domain and may remain powered on at all times to handle power control events and power management such that domains <NUM> and <NUM> can be controlled to dynamically enter into and exit high power and low power states. Each of domains <NUM> and <NUM> may operate at different voltage and/or power. Note that while only shown with three domains, understand the scope of the present invention is not limited in this regard and additional domains can be present in other embodiments. For example, multiple core domains may be present each including at least one core.

In general, each core <NUM> may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) <NUM><NUM>-<NUM>n. In various embodiments, LLC <NUM> may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect <NUM> thus couples the cores together, and provides interconnection between the cores, graphics domain <NUM> and system agent circuitry <NUM>. In one embodiment, interconnect <NUM> can be part of the core domain. However in other embodiments the ring interconnect can be of its own domain.

As further seen, system agent domain <NUM> may include display controller <NUM> which may provide control of and an interface to an associated display. As further seen, system agent domain <NUM> may include a power control unit <NUM> which can include logic to perform the power management techniques described herein. In the embodiment shown, power control unit <NUM> includes a dynamic current sharing control circuit <NUM>, which dynamically determines a maximum current consumption level independently for each core <NUM> and graphics engine <NUM> based at least in part on hint information provided by software, as described herein.

As further seen in <FIG>, processor <NUM> can further include an integrated memory controller (IMC) <NUM> that can provide for an interface to a system memory, such as a dynamic random access memory (DRAM). Multiple interfaces <NUM><NUM>-<NUM>n may be present to enable interconnection between the processor and other circuitry. For example, in one embodiment at least one direct media interface (DMI) interface may be provided as well as one or more PCIe™ interfaces. Still further, to provide for communications between other agents such as additional processors or other circuitry, one or more QPI interfaces may also be provided. Although shown at this high level in the embodiment of <FIG>, understand the scope of the present invention is not limited in this regard.

Referring to <FIG>, an embodiment of a processor including multiple cores is illustrated. Processor <NUM> includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SoC), or other device to execute code. Processor <NUM>, in one embodiment, includes at least two cores -- cores <NUM> and <NUM>, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor <NUM> may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.

Physical processor <NUM>, as illustrated in <FIG>, includes two cores, cores <NUM> and <NUM>. Here, cores <NUM> and <NUM> are considered symmetric cores, i.e., cores with the same configurations, functional units, and/or logic. In another embodiment, core <NUM> includes an out-of-order processor core, while core <NUM> includes an in-order processor core. However, cores <NUM> and <NUM> may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated ISA, a co-designed core, or other known core. Yet to further the discussion, the functional units illustrated in core <NUM> are described in further detail below, as the units in core <NUM> operate in a similar manner.

As depicted, core <NUM> includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor <NUM> as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 401a, a second thread is associated with architecture state registers 401b, a third thread may be associated with architecture state registers 402a, and a fourth thread may be associated with architecture state registers 402b. Here, each of the architecture state registers (401a, 401b, 402a, and 402b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 401a are replicated in architecture state registers 401b, so individual architecture states/contexts are capable of being stored for logical processor 401a and logical processor 401b. In core <NUM>, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block <NUM> may also be replicated for threads 401a and 401b. Some resources, such as re-order buffers in reorder/retirement unit <NUM>, ILTB <NUM>, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB <NUM>, execution unit(s) <NUM>, and portions of out-of-order unit <NUM> are potentially fully shared.

Processor <NUM> often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In <FIG>, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core <NUM> includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer <NUM> to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) <NUM> to store address translation entries for instructions.

Core <NUM> further includes decode module <NUM> coupled to fetch unit <NUM> to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 401a, 401b, respectively. Usually core <NUM> is associated with a first ISA, which defines/specifies instructions executable on processor <NUM>. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic <NUM> includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, decoders <NUM>, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders <NUM>, the architecture or core <NUM> takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.

In one example, allocator and renamer block <NUM> includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 401a and 401b are potentially capable of out-of-order execution, where allocator and renamer block <NUM> also reserves other resources, such as reorder buffers to track instruction results. Unit <NUM> may also include a register renamer to rename program/instruction reference registers to other registers internal to processor <NUM>. Reorder/retirement unit <NUM> includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

Scheduler and execution unit(s) block <NUM>, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

Lower level data cache and data translation buffer (D-TLB) <NUM> are coupled to execution unit(s) <NUM>. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.

Here, cores <NUM> and <NUM> share access to higher-level or further-out cache <NUM>, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache <NUM> is a last-level data cache - last cache in the memory hierarchy on processor <NUM> - such as a second or third level data cache. However, higher level cache <NUM> is not so limited, as it may be associated with or includes an instruction cache. A trace cache - a type of instruction cache - instead may be coupled after decoder <NUM> to store recently decoded traces.

In the depicted configuration, processor <NUM> also includes bus interface module <NUM> and a power controller <NUM>, which may perform power management in accordance with an embodiment of the present invention. In this scenario, bus interface <NUM> is to communicate with devices external to processor <NUM>, such as system memory and other components.

A memory controller <NUM> may interface with other devices such as one or many memories. In an example, bus interface <NUM> includes a ring interconnect with a memory controller for interfacing with a memory and a graphics controller for interfacing with a graphics processor. In an SoC environment, even more devices, such as a network interface, coprocessors, memory, graphics processor, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

Referring now to <FIG>, shown is a block diagram of a micro-architecture of a processor core in accordance with one embodiment of the present invention. As shown in <FIG>, processor core <NUM> may be a multi-stage pipelined out-of-order processor. Core <NUM> may operate at various voltages based on a received operating voltage, which may be received from an integrated voltage regulator or external voltage regulator.

As seen in <FIG>, core <NUM> includes front end units <NUM>, which may be used to fetch instructions to be executed and prepare them for use later in the processor pipeline. For example, front end units <NUM> may include a fetch unit <NUM>, an instruction cache <NUM>, and an instruction decoder <NUM>. In some implementations, front end units <NUM> may further include a trace cache, along with microcode storage as well as a micro-operation storage. Fetch unit <NUM> may fetch macro-instructions, e.g., from memory or instruction cache <NUM>, and feed them to instruction decoder <NUM> to decode them into primitives, i.e., micro-operations for execution by the processor.

Coupled between front end units <NUM> and execution units <NUM> is an out-of-order (OOO) engine <NUM> that may be used to receive the micro-instructions and prepare them for execution. More specifically OOO engine <NUM> may include various buffers to re-order micro-instruction flow and allocate various resources needed for execution, as well as to provide renaming of logical registers onto storage locations within various register files such as register file <NUM> and extended register file <NUM>. Register file <NUM> may include separate register files for integer and floating point operations. Extended register file <NUM> may provide storage for vector-sized units, e.g., <NUM> or <NUM> bits per register. For purposes of configuration, control, and additional operations, a set of machine specific registers (MSRs) <NUM> may also be present and accessible to various logic within core <NUM> (and external to the core).

Various resources may be present in execution units <NUM>, including, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware. For example, such execution units may include one or more arithmetic logic units (ALUs) <NUM> and one or more vector execution units <NUM>, among other such execution units.

Results from the execution units may be provided to retirement logic, namely a reorder buffer (ROB) <NUM>. More specifically, ROB <NUM> may include various arrays and logic to receive information associated with instructions that are executed. This information is then examined by ROB <NUM> to determine whether the instructions can be validly retired and result data committed to the architectural state of the processor, or whether one or more exceptions occurred that prevent a proper retirement of the instructions. Of course, ROB <NUM> may handle other operations associated with retirement.

As shown in <FIG>, ROB <NUM> is coupled to a cache <NUM> which, in one embodiment may be a low level cache (e.g., an L1 cache) although the scope of the present invention is not limited in this regard. Also, execution units <NUM> can be directly coupled to cache <NUM>. From cache <NUM>, data communication may occur with higher level caches, system memory and so forth. While shown with this high level in the embodiment of <FIG>, understand the scope of the present invention is not limited in this regard. For example, while the implementation of <FIG> is with regard to an out-of-order machine such as of an Intel® x86 instruction set architecture (ISA), the scope of the present invention is not limited in this regard. That is, other embodiments may be implemented in an in-order processor, a reduced instruction set computing (RISC) processor such as an ARM-based processor, or a processor of another type of ISA that can emulate instructions and operations of a different ISA via an emulation engine and associated logic circuitry.

Referring now to <FIG>, shown is a block diagram of a micro-architecture of a processor core in accordance with another embodiment. In the embodiment of <FIG>, core <NUM> may be a low power core of a different micro-architecture, such as an Intel®. Atom™-based processor having a relatively limited pipeline depth designed to reduce power consumption. As seen, core <NUM> includes an instruction cache <NUM> coupled to provide instructions to an instruction decoder <NUM>. A branch predictor <NUM> may be coupled to instruction cache <NUM>. Note that instruction cache <NUM> may further be coupled to another level of a cache memory, such as an L2 cache (not shown for ease of illustration in <FIG>). In turn, instruction decoder <NUM> provides decoded instructions to an issue queue <NUM> for storage and delivery to a given execution pipeline. A microcode ROM <NUM> is coupled to instruction decoder <NUM>.

A floating point pipeline <NUM> includes a floating point register file <NUM> which may include a plurality of architectural registers of a given bit with such as <NUM>, <NUM> or <NUM> bits. Pipeline <NUM> includes a floating point scheduler <NUM> to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU <NUM>, a shuffle unit <NUM>, and a floating point adder <NUM>. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file <NUM>. Of course understand while shown with these few example execution units, additional or different floating point execution units may be present in another embodiment.

An integer pipeline <NUM> also may be provided. In the embodiment shown, pipeline <NUM> includes an integer register file <NUM> which may include a plurality of architectural registers of a given bit with such as <NUM> or <NUM> bits. Pipeline <NUM> includes an integer scheduler <NUM> to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU <NUM>, a shifter unit <NUM>, and a jump execution unit <NUM>. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file <NUM>. Of course understand while shown with these few example execution units, additional or different integer execution units may be present in another embodiment.

A memory execution scheduler <NUM> may schedule memory operations for execution in an address generation unit <NUM>, which is also coupled to a TLB <NUM>. As seen, these structures may couple to a data cache <NUM>, which may be a L0 and/or L1 data cache that in turn couples to additional levels of a cache memory hierarchy, including an L2 cache memory.

To provide support for out-of-order execution, an allocator/renamer <NUM> may be provided, in addition to a reorder buffer <NUM>, which is configured to reorder instructions executed out of order for retirement in order. Although shown with this particular pipeline architecture in the illustration of <FIG>, understand that many variations and alternatives are possible.

Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of <FIG> and <FIG>, workloads may be dynamically swapped between the cores for power management reasons, as these cores, although having different pipeline designs and depths, may be of the same or related ISA. Such dynamic core swapping may be performed in a manner transparent to a user application (and possibly kernel also).

Referring to <FIG>, shown is a block diagram of a micro-architecture of a processor core in accordance with yet another embodiment. As illustrated in <FIG>, a core <NUM> may include a multi-staged in-order pipeline to execute at very low power consumption levels. As one such example, processor <NUM> may have a micro-architecture in accordance with an ARM Cortex A53 design available from ARM Holdings, LTD. , Sunnyvale, Calif. In an implementation, an <NUM>-stage pipeline may be provided that is configured to execute both <NUM>-bit and <NUM>-bit code. Core <NUM> includes a fetch unit <NUM> that is configured to fetch instructions and provide them to a decode unit <NUM>, which may decode the instructions, e.g., macro-instructions of a given ISA such as an ARMv8 ISA. Note further that a queue <NUM> may couple to decode unit <NUM> to store decoded instructions. Decoded instructions are provided to an issue logic <NUM>, where the decoded instructions may be issued to a given one of multiple execution units.

With further reference to <FIG>, issue logic <NUM> may issue instructions to one of multiple execution units. In the embodiment shown, these execution units include an integer unit <NUM>, a multiply unit <NUM>, a floating point/vector unit <NUM>, a dual issue unit <NUM>, and a load/store unit <NUM>. The results of these different execution units may be provided to a writeback unit <NUM>. Understand that while a single writeback unit is shown for ease of illustration, in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in <FIG> is represented at a high level, a particular implementation may include more or different structures. A processor designed using one or more cores having a pipeline as in <FIG> may be implemented in many different end products, extending from mobile devices to server systems.

Referring to <FIG>, shown is a block diagram of a micro-architecture of a processor core in accordance with a still further embodiment. As illustrated in <FIG>, a core <NUM> may include a multi-stage multi-issue out-of-order pipeline to execute at very high performance levels (which may occur at higher power consumption levels than core <NUM> of <FIG>). As one such example, processor <NUM> may have a microarchitecture in accordance with an ARM Cortex A57 design. In an implementation, a <NUM> (or greater)-stage pipeline may be provided that is configured to execute both <NUM>-bit and <NUM>-bit code. In addition, the pipeline may provide for <NUM> (or greater)-wide and <NUM> (or greater)-issue operation. Core <NUM> includes a fetch unit <NUM> that is configured to fetch instructions and provide them to a decoder/renamer/dispatcher <NUM>, which may decode the instructions, e.g., macro-instructions of an ARMv8 instruction set architecture, rename register references within the instructions, and dispatch the instructions (eventually) to a selected execution unit. Decoded instructions may be stored in a queue <NUM>. Note that while a single queue structure is shown for ease of illustration in <FIG>, understand that separate queues may be provided for each of the multiple different types of execution units.

Also shown in <FIG> is an issue logic <NUM> from which decoded instructions stored in queue <NUM> may be issued to a selected execution unit. Issue logic <NUM> also may be implemented in a particular embodiment with a separate issue logic for each of the multiple different types of execution units to which issue logic <NUM> couples.

Decoded instructions may be issued to a given one of multiple execution units. In the embodiment shown, these execution units include one or more integer units <NUM>, a multiply unit <NUM>, a floating point/vector unit <NUM>, a branch unit <NUM>, and a load/store unit <NUM>. In an embodiment, floating point/vector unit <NUM> may be configured to handle SIMD or vector data of <NUM> or <NUM> bits. Still further, floating point/vector execution unit <NUM> may perform IEEE-<NUM> double precision floating-point operations. The results of these different execution units may be provided to a writeback unit <NUM>. Note that in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in <FIG> is represented at a high level, a particular implementation may include more or different structures.

Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of <FIG> and <FIG>, workloads may be dynamically swapped for power management reasons, as these cores, although having different pipeline designs and depths, may be of the same or related ISA. Such dynamic core swapping may be performed in a manner transparent to a user application (and possibly kernel also).

A processor designed using one or more cores having pipelines as in any one or more of <FIG> may be implemented in many different end products, extending from mobile devices to server systems. Referring now to <FIG>, shown is a block diagram of a processor in accordance with another embodiment of the present invention. In the embodiment of <FIG>, processor <NUM> may be a SoC including multiple domains, each of which may be controlled to operate at an independent operating voltage and operating frequency. As a specific illustrative example, processor <NUM> may be an Intel® Architecture Core™-based processor such as an i3, i5, i7 or another such processor available from Intel Corporation. However, other low power processors such as available from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, Calif. , an ARM-based design from ARM Holdings, Ltd. or licensee thereof or a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, Calif. , or their licensees or adopters may instead be present in other embodiments such as an Apple A7 processor, a Qualcomm Snapdragon processor, or Texas Instruments OMAP processor. Such SoC may be used in a low power system such as a smartphone, tablet computer, phablet computer, Ultrabook™ computer or other portable computing device or connected device.

In the high level view shown in <FIG>, processor <NUM> includes a plurality of core units <NUM><NUM>-<NUM>n. Each core unit may include one or more processor cores, one or more cache memories and other circuitry. Each core unit <NUM> may support one or more instructions sets (e.g., an x86 instruction set (with some extensions that have been added with newer versions); a MIPS instruction set; an ARM instruction set (with optional additional extensions such as NEON)) or other instruction set or combinations thereof. Note that some of the core units may be heterogeneous resources (e.g., of a different design). In addition, each such core may be coupled to a cache memory (not shown) which in an embodiment may be a shared level (L2) cache memory. A non-volatile storage <NUM> may be used to store various program and other data. For example, this storage may be used to store at least portions of microcode, boot information such as a BIOS, other system software or so forth.

Each core unit <NUM> may also include an interface such as a bus interface unit to enable interconnection to additional circuitry of the processor. In an embodiment, each core unit <NUM> couples to a coherent fabric that may act as a primary cache coherent on-die interconnect that in turn couples to a memory controller <NUM>. In turn, memory controller <NUM> controls communications with a memory such as a DRAM (not shown for ease of illustration in <FIG>).

In addition to core units, additional processing engines are present within the processor, including at least one graphics unit <NUM> which may include one or more graphics processing units (GPUs) to perform graphics processing as well as to possibly execute general purpose operations on the graphics processor (so-called GPGPU operation). In addition, at least one image signal processor <NUM> may be present. Signal processor <NUM> may be configured to process incoming image data received from one or more capture devices, either internal to the SoC or off-chip.

Other accelerators also may be present. In the illustration of <FIG>, a video coder <NUM> may perform coding operations including encoding and decoding for video information, e.g., providing hardware acceleration support for high definition video content. A display controller <NUM> further may be provided to accelerate display operations including providing support for internal and external displays of a system. In addition, a security processor <NUM> may be present to perform security operations such as secure boot operations, various cryptography operations and so forth.

Each of the units may have its power consumption controlled via a power manager <NUM>, which may include control logic to perform the various power management techniques described herein.

In some embodiments, SoC <NUM> may further include a non-coherent fabric coupled to the coherent fabric to which various peripheral devices may couple. One or more interfaces 960a-960d enable communication with one or more off-chip devices. Such communications may be via a variety of communication protocols such as PCIe™, GPIO, USB, I<NUM>C, UART, MIPI, SDIO, DDR, SPI, HDMI, among other types of communication protocols. Although shown at this high level in the embodiment of <FIG>, understand the scope of the present invention is not limited in this regard.

Referring now to <FIG>, shown is a block diagram of a representative SoC. In the embodiment shown, SoC <NUM> may be a multi-core SoC configured for low power operation to be optimized for incorporation into a smartphone or other low power device such as a tablet computer or other portable computing device. As an example, SoC <NUM> may be implemented using asymmetric or different types of cores, such as combinations of higher power and/or low power cores, e.g., out-of-order cores and in-order cores. In different embodiments, these cores may be based on an Intel® Architecture™ core design or an ARM architecture design. In yet other embodiments, a mix of Intel® and ARM cores may be implemented in a given SoC.

As seen in <FIG>, SoC <NUM> includes a first core domain <NUM> having a plurality of first cores <NUM><NUM>-<NUM><NUM>. In an example, these cores may be low power cores such as in-order cores. In one embodiment these first cores may be implemented as ARM Cortex A53 cores. In turn, these cores couple to a cache memory <NUM> of core domain <NUM>. In addition, SoC <NUM> includes a second core domain <NUM>. In the illustration of <FIG>, second core domain <NUM> has a plurality of second cores <NUM><NUM>-<NUM><NUM>. In an example, these cores may be higher power-consuming cores than first cores <NUM>. In an embodiment, the second cores may be out-of-order cores, which may be implemented as ARM Cortex A57 cores. In turn, these cores couple to a cache memory <NUM> of core domain <NUM>. Note that while the example shown in <FIG> includes <NUM> cores in each domain, understand that more or fewer cores may be present in a given domain in other examples.

With further reference to <FIG>, a graphics domain <NUM> also is provided, which may include one or more graphics processing units (GPUs) configured to independently execute graphics workloads, e.g., provided by one or more cores of core domains <NUM> and <NUM>. As an example, GPU domain <NUM> may be used to provide display support for a variety of screen sizes, in addition to providing graphics and display rendering operations.

As seen, the various domains couple to a coherent interconnect <NUM>, which in an embodiment may be a cache coherent interconnect fabric that in turn couples to an integrated memory controller <NUM>. Coherent interconnect <NUM> may include a shared cache memory, such as an L3 cache, in some examples. In an embodiment, memory controller <NUM> may be a direct memory controller to provide for multiple channels of communication with an off-chip memory, such as multiple channels of a DRAM (not shown for ease of illustration in <FIG>).

In different examples, the number of the core domains may vary. For example, for a low power SoC suitable for incorporation into a mobile computing device, a limited number of core domains such as shown in <FIG> may be present. Still further, in such low power SoCs, core domain <NUM> including higher power cores may have fewer numbers of such cores. For example, in one implementation two cores <NUM> may be provided to enable operation at reduced power consumption levels. In addition, the different core domains may also be coupled to an interrupt controller to enable dynamic swapping of workloads between the different domains.

In yet other embodiments, a greater number of core domains, as well as additional optional IP logic may be present, in that an SoC can be scaled to higher performance (and power) levels for incorporation into other computing devices, such as desktops, servers, high performance computing systems, base stations forth. As one such example, <NUM> core domains each having a given number of out-of-order cores may be provided. Still further, in addition to optional GPU support (which as an example may take the form of a GPGPU), one or more accelerators to provide optimized hardware support for particular functions (e.g. web serving, network processing, switching or so forth) also may be provided. In addition, an input/output interface may be present to couple such accelerators to off-chip components.

Referring now to <FIG>, shown is a block diagram of another example SoC. In the embodiment of <FIG>, SoC <NUM> may include various circuitry to enable high performance for multimedia applications, communications and other functions. As such, SoC <NUM> is suitable for incorporation into a wide variety of portable and other devices, such as smartphones, tablet computers, smart TVs and so forth. In the example shown, SoC <NUM> includes a central processor unit (CPU) domain <NUM>. In an embodiment, a plurality of individual processor cores may be present in CPU domain <NUM>. As one example, CPU domain <NUM> may be a quad core processor having <NUM> multithreaded cores. Such processors may be homogeneous or heterogeneous processors, e.g., a mix of low power and high power processor cores.

In turn, a GPU domain <NUM> is provided to perform advanced graphics processing in one or more GPUs to handle graphics and compute APIs. A DSP unit <NUM> may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth, in addition to advanced calculations that may occur during execution of multimedia instructions. In turn, a communication unit <NUM> may include various components to provide connectivity via various wireless protocols, such as cellular communications (including <NUM>/<NUM> LTE), wireless local area protocols such as Bluetooth™, IEEE <NUM>, and so forth.

Still further, a multimedia processor <NUM> may be used to perform capture and playback of high definition video and audio content, including processing of user gestures. A sensor unit <NUM> may include a plurality of sensors and/or a sensor controller to interface to various off-chip sensors present in a given platform. An image signal processor <NUM> may be provided with one or more separate ISPs to perform image processing with regard to captured content from one or more cameras of a platform, including still and video cameras.

A display processor <NUM> may provide support for connection to a high definition display of a given pixel density, including the ability to wirelessly communicate content for playback on such display. Still further, a location unit <NUM> may include a GPS receiver with support for multiple GPS constellations to provide applications highly accurate positioning information obtained using as such GPS receiver. Understand that while shown with this particular set of components in the example of <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a block diagram of an example system with which embodiments can be used. As seen, system <NUM> may be a smartphone or other wireless communicator. A baseband processor <NUM> is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor <NUM> is coupled to an application processor <NUM>, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor <NUM> may further be configured to perform a variety of other computing operations for the device and perform the power management techniques described herein.

In turn, application processor <NUM> can couple to a user interface/display <NUM>, e.g., a touch screen display. In addition, application processor <NUM> may couple to a memory system including a non-volatile memory, namely a flash memory <NUM> and a system memory, namely a dynamic random access memory (DRAM) <NUM>. As further seen, application processor <NUM> further couples to a capture device <NUM> such as one or more image capture devices that can record video and/or still images.

Still referring to <FIG>, a universal integrated circuit card (UICC) <NUM> comprising a subscriber identity module and possibly a secure storage and cryptoprocessor is also coupled to application processor <NUM>. System <NUM> may further include a security processor <NUM> that may couple to application processor <NUM>. A plurality of sensors <NUM> may couple to application processor <NUM> to enable input of a variety of sensed information such as accelerometer and other environmental information. An audio output device <NUM> may provide an interface to output sound, e.g., in the form of voice communications, played or streaming audio data and so forth.

As further illustrated, a near field communication (NFC) contactless interface <NUM> is provided that communicates in a NFC near field via an NFC antenna <NUM>. While separate antennae are shown in <FIG>, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionality.

A PMIC <NUM> couples to application processor <NUM> to perform platform level power management. To this end, PMIC <NUM> may issue power management requests to application processor <NUM> to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC <NUM> may also control the power level of other components of system <NUM>.

To enable communications to be transmitted and received, various circuitry may be coupled between baseband processor <NUM> and an antenna <NUM>. Specifically, a radio frequency (RF) transceiver <NUM> and a wireless local area network (WLAN) transceiver <NUM> may be present. In general, RF transceiver <NUM> may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as <NUM> or <NUM> wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor <NUM> may be present. Other wireless communications such as receipt or transmission of radio signals, e.g., AM/FM and other signals may also be provided. In addition, via WLAN transceiver <NUM>, local wireless communications can also be realized.

Referring now to <FIG>, shown is a block diagram of another example system with which embodiments may be used. In the illustration of <FIG>, system <NUM> may be mobile low-power system such as a tablet computer, <NUM>:<NUM> tablet, phablet or other convertible or standalone tablet system. As illustrated, a SoC <NUM> is present and may be configured to operate as an application processor for the device and perform the power management techniques described herein.

A variety of devices may couple to SoC <NUM>. In the illustration shown, a memory subsystem includes a flash memory <NUM> and a DRAM <NUM> coupled to SoC <NUM>. In addition, a touch panel <NUM> is coupled to the SoC <NUM> to provide display capability and user input via touch, including provision of a virtual keyboard on a display of touch panel <NUM>. To provide wired network connectivity, SoC <NUM> couples to an Ethernet interface <NUM>. A peripheral hub <NUM> is coupled to SoC <NUM> to enable interfacing with various peripheral devices, such as may be coupled to system <NUM> by any of various ports or other connectors.

In addition to internal power management circuitry and functionality within SoC <NUM>, a PMIC <NUM> is coupled to SoC <NUM> to provide platform-based power management, e.g., based on whether the system is powered by a battery <NUM> or AC power via an AC adapter <NUM>. In addition to this power source-based power management, PMIC <NUM> may further perform platform power management activities based on environmental and usage conditions. Still further, PMIC <NUM> may communicate control and status information to SoC <NUM> to cause various power management actions within SoC <NUM>.

Still referring to <FIG>, to provide for wireless capabilities, a WLAN unit <NUM> is coupled to SoC <NUM> and in turn to an antenna <NUM>. In various implementations, WLAN unit <NUM> may provide for communication according to one or more wireless protocols.

As further illustrated, a plurality of sensors <NUM> may couple to SoC <NUM>. These sensors may include various accelerometer, environmental and other sensors, including user gesture sensors. Finally, an audio codec <NUM> is coupled to SoC <NUM> to provide an interface to an audio output device <NUM>. Of course understand that while shown with this particular implementation in <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a block diagram of a representative computer system such as notebook, Ultrabook™ or other small form factor system. A processor <NUM>, in one embodiment, includes a microprocessor, multi-core processor, multithreaded processor, an ultra low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, processor <NUM> acts as a main processing unit and central hub for communication with many of the various components of the system <NUM>. As one example, processor <NUM> is implemented as a SoC.

Processor <NUM>, in one embodiment, communicates with a system memory <NUM>. As an illustrative example, the system memory <NUM> is implemented via multiple memory devices or modules to provide for a given amount of system memory.

To provide for persistent storage of information such as data, applications, one or more operating systems and so forth, a mass storage <NUM> may also couple to processor <NUM>. In various embodiments, to enable a thinner and lighter system design as well as to improve system responsiveness, this mass storage may be implemented via a SSD or the mass storage may primarily be implemented using a hard disk drive (HDD) with a smaller amount of SSD storage to act as a SSD cache to enable non-volatile storage of context state and other such information during power down events so that a fast power up can occur on re-initiation of system activities. Also shown in <FIG>, a flash device <NUM> may be coupled to processor <NUM>, e.g., via a serial peripheral interface (SPI). This flash device may provide for non-volatile storage of system software, including a basic input/output software (BIOS) as well as other firmware of the system.

Various input/output (I/O) devices may be present within system <NUM>. Specifically shown in the embodiment of <FIG> is a display <NUM> which may be a high definition LCD or LED panel that further provides for a touch screen <NUM>. In one embodiment, display <NUM> may be coupled to processor <NUM> via a display interconnect that can be implemented as a high performance graphics interconnect. Touch screen <NUM> may be coupled to processor <NUM> via another interconnect, which in an embodiment can be an I<NUM>C interconnect. As further shown in <FIG>, in addition to touch screen <NUM>, user input by way of touch can also occur via a touch pad <NUM> which may be configured within the chassis and may also be coupled to the same I<NUM>C interconnect as touch screen <NUM>.

For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor <NUM> in different manners. Certain inertial and environmental sensors may couple to processor <NUM> through a sensor hub <NUM>, e.g., via an I2C interconnect. In the embodiment shown in <FIG>, these sensors may include an accelerometer <NUM>, an ambient light sensor (ALS) <NUM>, a compass <NUM> and a gyroscope <NUM>. Other environmental sensors may include one or more thermal sensors <NUM> which in some embodiments couple to processor <NUM> via a system management bus (SMBus) bus.

Also seen in <FIG>, various peripheral devices may couple to processor <NUM> via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller <NUM>. Such components can include a keyboard <NUM> (e.g., coupled via a PS2 interface), a fan <NUM>, and a thermal sensor <NUM>. In some embodiments, touch pad <NUM> may also couple to EC <NUM> via a PS2 interface. In addition, a security processor such as a trusted platform module (TPM) <NUM> may also couple to processor <NUM> via this LPC interconnect.

System <NUM> can communicate with external devices in a variety of manners, including wirelessly. In the embodiment shown in <FIG>, various wireless modules, each of which can correspond to a radio configured for a particular wireless communication protocol, are present. One manner for wireless communication in a short range such as a near field may be via a NFC unit <NUM> which may communicate, in one embodiment with processor <NUM> via an SMBus. Note that via this NFC unit <NUM>, devices in close proximity to each other can communicate.

As further seen in <FIG>, additional wireless units can include other short range wireless engines including a WLAN unit <NUM> and a Bluetooth unit <NUM>. Using WLAN unit <NUM>, Wi-Fi™ communications can be realized, while via Bluetooth unit <NUM>, short range Bluetooth™ communications can occur. These units may communicate with processor <NUM> via a given link.

In addition, wireless wide area communications, e.g., according to a cellular or other wireless wide area protocol, can occur via a WWAN unit <NUM> which in turn may couple to a subscriber identity module (SIM) <NUM>. In addition, to enable receipt and use of location information, a GPS module <NUM> may also be present. Note that in the embodiment shown in <FIG>, WWAN unit <NUM> and an integrated capture device such as a camera module <NUM> may communicate via a given link.

An integrated camera module <NUM> can be incorporated in the lid. To provide for audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP) <NUM>, which may couple to processor <NUM> via a high definition audio (HDA) link. Similarly, DSP <NUM> may communicate with an integrated coder/decoder (CODEC) and amplifier <NUM> that in turn may couple to output speakers <NUM> which may be implemented within the chassis. Similarly, amplifier and CODEC <NUM> can be coupled to receive audio inputs from a microphone <NUM> which in an embodiment can be implemented via dual array microphones (such as a digital microphone array) to provide for high quality audio inputs to enable voice-activated control of various operations within the system. Note also that audio outputs can be provided from amplifier/CODEC <NUM> to a headphone jack <NUM>. Although shown with these particular components in the embodiment of <FIG>, understand the scope of the present invention is not limited in this regard.

Embodiments may be implemented in many different system types. Referring now to <FIG>, shown is a block diagram of a system in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. As shown in <FIG>, each of processors <NUM> and <NUM> may be multicore processors, including first and second processor cores (i.e., processors 1574a and 1574b and processor cores 1584a and 1584b), although potentially many more cores may be present in the processors. In addition, each of processors <NUM> and <NUM> also may include a graphics processor unit (GPU) <NUM>, <NUM> to perform graphics operations. And with software-provided hint information, e.g., as to priority of processing levels for given workloads between the cores and the GPU, dynamic maximum current determinations and control as described herein may be performed. To this end, each of the processors can include a PCU <NUM>, <NUM> to perform processor-based power management, including dynamic current to dynamically determine a maximum current consumption level individually for each core and GPU based at least in part on hint information provided by software, as described herein.

Still referring to <FIG>, first processor <NUM> further includes a memory controller hub (MCH) <NUM> and point-to-point (P-P) interfaces <NUM> and <NUM>. Similarly, second processor <NUM> includes a MCH <NUM> and P-P interfaces <NUM> and <NUM>. As shown in <FIG>, MCH's <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of system memory (e.g., DRAM) locally attached to the respective processors. First processor <NUM> and second processor <NUM> may be coupled to a chipset <NUM> via P-P interconnects <NUM> and <NUM>, respectively. As shown in <FIG>, chipset <NUM> includes P-P interfaces <NUM> and <NUM>.

Furthermore, chipset <NUM> includes an interface <NUM> to couple chipset <NUM> with a high performance graphics engine <NUM>, by a P-P interconnect <NUM>. In turn, chipset <NUM> may be coupled to a first bus <NUM> via an interface <NUM>. As shown in <FIG>, various input/output (I/O) devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. Various devices may be coupled to second bus <NUM> including, for example, a keyboard/mouse <NUM>, communication devices <NUM> and a data storage unit <NUM> such as a disk drive or other mass storage device which may include code <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to second bus <NUM>. Embodiments can be incorporated into other types of systems including mobile devices such as a smart cellular telephone, tablet computer, netbook, Ultrabook™, or so forth.

<FIG> is a block diagram illustrating an IP core development system <NUM> that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system <NUM> may be used to generate modular, reusable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SoC integrated circuit). A design facility <NUM> can generate a software simulation <NUM> of an IP core design in a high level programming language (e.g., C/C++). The software simulation <NUM> can be used to design, test, and verify the behavior of the IP core. A register transfer level (RTL) design can then be created or synthesized from the simulation model. The RTL design <NUM> is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design <NUM>, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

The RTL design <NUM> or equivalent may be further synthesized by the design facility into a hardware model <NUM>, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a third party fabrication facility <NUM> using non-volatile memory <NUM> (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternately, the IP core design may be transmitted (e.g., via the Internet) over a wired connection <NUM> or wireless connection <NUM>. The fabrication facility <NUM> may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

Referring now to <FIG>, shown is a block diagram of a computing system in accordance with an embodiment of the present invention. As shown in <FIG>, system <NUM> may be any type of computing system, ranging from a small portable device such as smartphone, tablet computer or so forth to larger devices, including laptop computers, desktop computers, server computers and so forth.

In any event, in the high level shown in <FIG>, system <NUM> includes a system on chip (SoC) <NUM> that may be implemented as a multicore processor or any other type of SoC. Included within SoC <NUM> are a plurality of intellectual property (IP) circuits <NUM><NUM> - <NUM><NUM>. In embodiments, each IP circuit <NUM> may be a processing core, graphics processor or any other types of homogeneous or heterogeneous processing circuit such as specialized processing units, fixed function units and so forth. In one particular embodiment, assume that IP circuits <NUM><NUM>,<NUM> are general-purpose processing cores, and IP circuit <NUM><NUM> is a graphics processor, which in some cases may be formed of multiple individual graphics processing units.

Depending on particular workloads being executed within SoC <NUM>, certain processing circuits may be more significant for the workload than others. As such, with embodiments herein the different IP circuits can be allowed a controllable amount of current consumption based at least in part on hint information received from a software <NUM>, which may provide the workload for execution. By providing this workload, software <NUM> has an a priori and greater understanding of the nature of the workload and the significance and likely relative current consumption of different IP circuits. As such, embodiments include an interface <NUM> to provide current consumption information based on runtime heuristics from software <NUM> to a power control unit (PCU) <NUM>.

In various embodiments, PCU <NUM> may be implemented as a dedicated hardware circuit, one of multiple cores, a microcontroller or any other hardware circuitry. In the embodiment shown, PCU <NUM> includes a plurality of configuration registers <NUM><NUM> - <NUM><NUM>. In embodiments, a given configuration register <NUM> may be associated with a corresponding IP circuit <NUM> to store current throttle information received from software <NUM> for the corresponding IP circuit. Note that this information may take different forms in different embodiments. In some cases, such information may be based on priority information and may include a relative priority level, e.g., in terms of percentage, for each IP circuit. In other cases, software <NUM> may provide an actual maximum current value to be enforced for the IP circuit in a throttling situation. In yet other embodiments, this information may take other forms.

Still with reference to <FIG>, PCU <NUM> further includes a dynamic current sharing control circuit <NUM>. In embodiments herein, dynamic current sharing control circuit <NUM> may determine resolved maximum current values for each individual IP circuit based at least in part on the information stored in configuration registers <NUM>. In addition, control circuit <NUM> may determine these resolved maximum current values further based on die-specific information, including, as examples, leakage information, process variation information, voltage/frequency curves, and so forth. In this way, dynamic current sharing control circuit <NUM> may update the values written by software <NUM> based on such information to generate resolved values, from which throttling control values may be determined. These throttling control values may be sent to corresponding IP circuits <NUM>. As illustrated in <FIG>, each of processing circuits <NUM> includes a configuration storage <NUM> to store a corresponding throttling control value. Note that the throttling control value itself may take different forms in different embodiments. In some cases, this throttling control value may be implemented as a duty cycle value. In other cases, the throttling control value may be an allowed maximum current consumption or allowed maximum operating frequency for the IP circuit, or so forth. As described herein, IP circuit <NUM> may dynamically control its own operation in a throttling situation based at least in part on this throttling control value stored in configuration storage <NUM>.

Note that further in the illustration of <FIG>, a voltage regulator <NUM>, external to SoC <NUM> is present. Voltage regulator (VR) <NUM> may provide power to all of the IP circuits <NUM><NUM>-<NUM> illustrated in <FIG>, as well as other circuitry of SoC <NUM>. However, understand that in other cases, the control and current sharing realized in embodiments may be performed on a per voltage rail basis. That is, voltage regulator <NUM> or additional voltage regulators may be present that provide power by way of multiple independent voltage rails, each coupled to one or more IP circuits and other logic of the processor. In such cases, dynamic current sharing control circuit <NUM> may dynamically determine current sharing throttling control values for each collection of IP circuits associated with a given voltage rail.

Still with reference to <FIG>, assume an implementation in which IP circuits <NUM> (also referred to herein as IP1-IP3) respectively draw maximum currents of: maximum IP1. iccmax; Ip2. iccmax; and IP3. Also assume VR <NUM> can provide a total max current of: VR1. In high current VRs such as VR <NUM>, the VR1. iccmax < IP1. iccmax + IP2. iccmax + IP3. This undersizing is done to limit the cost of the VR. To ensure correctness, PCU <NUM> may trigger throttling when it detects that a maximum current capacity of voltage regulator <NUM> is about to be exceeded. Such throttling may be performed proactively based on a threshold somewhat lower than the actual configured maximum current capability. Understand that while different implementations are possible, in an embodiment throttling can be implemented by gating IP clocks with some duty cycle. The duty cycle of such schemes can be configured by PCU <NUM>.

In one embodiment, PCU <NUM>, by way of interface <NUM>, may receive specific iccmax values to which the IP circuit should be throttled to when an iccmax violation is detected, namely: IP0_ICCMAX_WHEN_THROTTLED; IP1_ICCMAX_WHEN_THROTTLED; IP2_ICCMAX_WHEN_THROTTLED; values to be stored in configuration registers <NUM>. Software can populate these values based on runtime heuristics, and may ensure that the currents written here are not larger than the VR1. iccmax value.

In turn, PCU <NUM>, and more specifically dynamic current sharing control circuit <NUM>, may use die-specific information (e.g., leakage, process variation, V/F curves) to update the values written by software. For this example, assume PCU <NUM> considers the software input and the die-specific information, to determine resolved values of: RESOLVED_IP0_ICCMAX_WHEN_THROTTLED, RESOLVED_IP1_ICCMAX_WHEN_THROTTLED; and RESOLVED_IP2_ICCMAX_WHEN_THROTTLED. Dynamic current sharing control circuit <NUM> then may calculate a duty cycle value for throttling the IP circuits based on these final resolved values and configured maximum current values (iccmax). The duty cycle in this case can be calculated as: duty_cycle_ip_n = RESOLVED_IPn_ICCMAX_WHEN_THROTTLED/IPN. For IP0, this results in a duty_cycle_ip_0 = RESOLVED_IP0_ICCMAX_WHEN_THROTTLED/IP0.

PCU <NUM> can then program the duty cycles for throttling within configuration registers <NUM>. Depending on platform/SoC level heuristics, the IP_N_ICCMAX_WHEN_THROTTLED value can be changed to get optimal runtime behavior.

As one particular example, assume a graphics-intensive workload, in which IP circuit <NUM><NUM> is a graphics processor and IP circuits <NUM><NUM>, <NUM> are general-purpose processors. In this arrangement, a graphics driver may, via interface <NUM>, provide hint information to indicate that the graphics processor (and interconnect circuitry) should be provided their maximum configured current consumption, while cores can be throttled. To this end, the graphics driver may provide configured maximum current consumption values for the graphics processor and interconnect, and a remaining current budget can be allocated to the cores. In this way, when a maximum current consumption limit is hit, the cores may be throttled but the graphics processor and interconnect may continue to run unconstrained, improving graphics workloads.

In another case with a core compute-intensive workload, the opposite behavior can occur by allocating maximum current consumption values for the cores and interconnect and remaining current consumption budget to graphics processors. In this way, when a power spike is identified, a graphics processor can be throttled, but cores and interconnect may still operate unconstrained, improving core-based workloads. In one embodiment, software may leverage utilization information to identify core or graphics-bound workloads. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with an embodiment of the present invention. As shown in <FIG>, method <NUM> is a method for performing dynamic current sharing between multiple IP circuits based at least in part on software-based information regarding workloads being executed. More specifically, method <NUM> may be performed in concert between various agents, including software having a workload to be executed and corresponding hardware, including a hardware-based power controller and one or more IP circuits on which at least portions of the workload may execute. As such, method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof.

As illustrated, in method <NUM> a software agent <NUM> may have a workload to execute and may determine (block <NUM>) based on heuristics a per IP circuit maximum current budget (and/or a maximum current priority) for each such IP circuit. As illustrated, software <NUM> may provide this information via an interface to a power controller <NUM>, which may store this information in corresponding configuration registers, namely current throttling configuration registers. In turn, PCU <NUM>, and more particularly a dynamic current sharing control circuit <NUM>, may read this information, and based on this information and die parameters and characteristics, determine a maximum current budget per IP circuit. Power controller <NUM> may then send this information for programming corresponding configuration registers of IP circuits <NUM>. Then, during operation of the workload, when power controller <NUM> proactively identifies a maximum current situation, it sends a throttling signal to IP circuits <NUM>. In turn, IP circuits <NUM> may throttle operation to remain within the maximum current budget identified in its configuration registers. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with one embodiment of the present invention. As shown in <FIG>, method <NUM> is a method for interfacing between a power controller and a software entity that has a priori knowledge of workload to be executed. Method <NUM> in <FIG> is from the view of the power controller, and as such, method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof.

As shown in <FIG>, method <NUM> begins by receiving current throttle hint information regarding a workload (block <NUM>). More specifically, the power controller may receive this hint information from a software entity via an interface. Although different embodiments are possible, in one embodiment the interface that may be a mailbox interface of the power controller to which the software entity may write. In another embodiment, a software entity may perform a configuration register write, such as a write to machine specific register (MSR) operation to provide this current throttle hint information. Note that the current throttle hint information may take various forms, including priority information for different processing circuits, such as in the form of percentages or so forth.

At block <NUM>, the power controller stores this current throttle hint information into a set of configuration registers of the power controller. Next at block <NUM> the power controller may determine resolved throttle values for the processing circuits. More specifically, these resolved throttle values may be based on the current throttle hint information and various parameters of the processor, including die-based parameters and characteristics of operation, such as voltage/frequency curves and so forth. In some cases, the power controller may overwrite the current throttle hint information present in the configuration registers with these resolved throttle values. In other cases, the resolved throttle values may be stored in another location.

In any event, control next passes to block <NUM> where a dynamic maximum current budget may be calculated for each processing circuit. Such calculated current budget may be based on the resolved throttle value for a given processing circuit and a configured maximum current budget for the processor. To this end, the power controller may include or may be associated with another set of configuration registers that store a maximum current budget for each processing circuit. Note that this configured maximum current information may be stored during a pre-boot environment, such as by a given firmware.

Still referring to <FIG>, at block <NUM> the dynamic maximum current budgets can be sent to the processing circuits. Understand that in response to receipt of a given maximum dynamic maximum current budget, a processing circuit may store such value in a configuration register, and may control operation to be maintained equal to or lower than this dynamic maximum current budget, when a throttle condition is identified. Note that these dynamic maximum current budgets are relevant only during throttle events. That is, a given processing circuit may be allowed to exceed its programmed maximum current budget during normal operation, but obey the limit during a throttling condition.

Still referring to <FIG>, during normal operation of the processor, the power controller may receive various telemetry or sensor information. Specifically, as illustrated in block <NUM> such information may regard voltage, current, power and thermal conditions of the processor. As part of its power control operations, the power controller may determine, at diamond <NUM>, whether the total current consumption of the processor exceeds a given threshold. Note that this threshold may be set at a value lower than a configured maximum current consumption of the processor, so that proactive control of current consumption may occur.

If it is determined that the total current exceeds this threshold value, control passes to block <NUM> where a throttle signal may be sent to the processing circuits. In response to receipt of this throttle signal, processing circuits may control their operation to ensure that their current consumption does not exceed the dynamic maximum current budget. In this way, each of the processing circuits may operate with an independent and a dynamically controllable current consumption level, to improve workload execution, even when the throttle condition is identified. This is so, as by independently controlling current consumption levels dynamically based on relative priority of given processing circuits, processing circuits integral to a particular workload may not be throttled at all, or at minimum, may be throttled less than other (less integral) processing circuits, during such workload execution. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with another embodiment of the present invention. As shown in <FIG>, method <NUM> is a method for dynamically controlling current consumption within a processing circuit based on a dynamic current budget. As such, method <NUM> may be performed by hardware circuitry such as a processing core, graphics processor or other processing circuit, or firmware, software and/or combinations thereof that execute on such circuitry.

Method <NUM> begins by receiving a dynamic current budget from a power controller (block <NUM>). Note that this dynamic current budget may take different forms in various implementations including in the form of duty cycle information, as described herein. Regardless of the form, at block <NUM> the processing circuit stores this dynamic current budget in a maximum current configuration register. Thereafter, the processing circuit may begin (or continue) operation at a configured performance state (block <NUM>). For example, the processing circuit may be configured under control of a power controller or other control circuitry to operate at a performance state having a given operating frequency and operating voltage. During operation at this configured performance state, it may be determined at diamond <NUM> whether a throttle signal is received from the power controller.

In this condition, control passes to block <NUM> where the processing circuit may throttle its operation. More specifically, the processing circuit may control its operation to maintain its current consumption to be no greater than the dynamic current budget. In some cases, a processing circuit may include an internal power control logic that may determine operating parameter changes to effect this current consumption maintenance. As one example, the processing circuit may throttle operation by squashing some number of clock signals, such that operation is slowed, and thus current consumption is reduced by operating at a squashed clock, rather than a configured operating frequency. For example, every other clock cycle may be squashed, or other duty cycle control or diminishment in clock cycles can occur.

Note that in certain circumstances where other processing circuits do not consume their full current consumption levels, it is possible that the processing circuit may receive an opportunistic current budget from the power controller. Thus at diamond <NUM> it is determined whether an opportunistic current budget has been received. If not, the processing circuit may continue to operate in a throttle condition until it receives a release of the throttle signal (as determined at diamond <NUM>).

Instead if an opportunistic current budget is received, control passes to block <NUM> where the processing circuit may increase its operation. For example, the processing circuit may terminate clock squashing to consume the opportunistic current budget. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

In some situations, some cores or other processing circuits may operate with high current consumption. In an arrangement in which all cores or other processing circuits are allocated equal amounts of an overall package current budget, a performance loss may inhere, as any core operating above an allocated current limit would be throttled, via internal or local control operation. Yet at the same time with one or more other cores or processing circuits operating at levels below their allocated current limits, current headroom is left unused.

To avoid this concern, embodiments may provide performance optimizations within a platform having a constrained power delivery solution. To this end, embodiments may implement control techniques with global current control such that one or more cores or other processing circuits are allowed to exceed their individual threshold level, so long as an overall current limit for the package is not exceeded. In this way, embodiments may enhance performance, as some cores or other processing circuits may operate at higher (than configured) current consumption levels while the overall processor maintains operation within limits.

To this end, embodiments may perform fast current sensing on a load side (e.g., as implemented within integrated voltage regulators) to provide a high speed measure of actual current consumption. This measure of current consumption may be output from the integrated voltage regulators as a digital output. In turn, the individual current values from multiple voltage regulators may then be summed. This summed value next may be subjected to digital filtering. In turn, the resulting filtered value is compared to a threshold. Assuming the overall current consumption represented by this filtered value is less than this threshold, no throttling may occur. Should the overall current consumption represented by the filtered value exceed the threshold, one or more domains may be throttled to stay within the limit. Note that this throttling may be performed independently in each domain (or not) based on each domain's actual current consumption and its individual configured limit, as described herein. And as further discussed above, each domain may perform different throttle operations such as clock squashing or otherwise controlling operating frequency, operating voltage or so forth.

With embodiments, actual current consumption may be detected without maintaining a detailed model. As a result, multiple domains may be scaled and a time constant may be adapted to minimize unnecessary throttling. Still further, embodiments enable such performance optimization without any run time adaptation of the system. Further as described herein, embodiments may be extended to multiple external voltage regulators by converting current to power and summing the results of the contribution of such multiple voltage regulators. Embodiments also may be used for more complicated power delivery limitations such as suppression of energy in resonant frequencies to improve minimal operating voltage performance.

Referring now to <FIG>, shown is a block diagram of a processor in accordance with an embodiment of the present invention. As shown in <FIG>, processor <NUM> is a multicore processor including a plurality of cores <NUM><NUM>-<NUM>n. Additional processing engines may be present, including a graphics engine <NUM>. An interconnect <NUM> such as a ring interconnect may be present and used to couple cores <NUM> and other components together. As shown in the embodiment of <FIG>, each of these domains may receive power from a given integrated voltage regulator <NUM><NUM> - <NUM>x. Based on the load presented by these domains, voltage regulators <NUM> may measure a real time digital current (using a circuit that operates at high speed (e.g. <NUM>)). In turn, each integrated voltage regulator <NUM> provides a digital current value to a summation circuit <NUM>, which sums these values into a total current value. Note that in some embodiments, summation circuit <NUM> may be implemented in a distributed manner.

Still referring to <FIG>, this total current value is provided to a current controller <NUM>. In different embodiments, controller <NUM> may be implemented as a dedicated circuit, separate from both cores <NUM> and a power controller of the processor (not shown for ease of illustration in <FIG>). In other cases, controller <NUM> may be implemented within the power controller. In any case, as illustrated controller <NUM> provides the received total current value to a filter <NUM>, which in an embodiment may be implemented as a low pass filter to perform digital filtering of this total current value. This filter operation may be performed according to an average time window stored in a window storage <NUM>. In one embodiment, this time value causes low pass filter <NUM> to operate as a <NUM> nanosecond low pass filter. The filtered current value is provided to a digital comparator <NUM>, which performs a comparison to a threshold current value stored in a threshold storage <NUM>. If it is determined that the filtered measured current value exceeds the threshold value, a throttle situation is thus identified and is communicated to a pulse lengthening circuit <NUM>, which may issue a throttle signal to the various domains according to a throttle window duration provided by a throttle window storage <NUM>. In other cases, the low pass filters may be replaced with band pass filters to reduce energy in resonant frequency bands.

In embodiments, pulse lengthening circuit <NUM> may be configured to reduce ringing or hysteresis of the control mechanism. That is, pulse lengthening circuit <NUM> may cause the throttle signal to be active for a given throttle window duration following a detection of a throttle event (identified when the filtered measured current value exceeds the threshold value). Even when throttling begins according to this event and then the measured current falls below the threshold value (as a result of throttle operation occurring in one or more cores or other processing circuits), pulse lengthening circuit <NUM> maintains the active throttle signal for at least the length of the throttle window duration to avoid hysteresis or ringing. In different embodiments, the length of this throttle window duration may be programmable, and in some embodiments, pulse lengthening circuit <NUM> may be an optional component. That is, in other cases, a hysteresis or other control scheme may be applied to the throttle signal. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

As discussed above, multiple instantiations of a current controller as in <FIG> may be provided for each of multiple voltage regulators and in turn, the multiple instantiations may be coupled to a power controller. Such power controller may perform power control for a power supply that provides power to the multiple voltage regulators. That is, in a given computing platform a single power supply may be present to power multiple external voltage regulators such as multiple voltage regulators present on a motherboard, each of which provides a given regulated voltage to be used by on-chip and off-chip components. As with the above discussion, it is possible for these individual voltage regulators to operate at higher levels when one or more other of these voltage regulators are performing at a lower level. This is so, as the single power supply that provides power to these individual voltage regulators has sufficient capability to do so, assuming that not all of the voltage regulators exceed their individual threshold levels.

Referring now to <FIG>, shown is a block diagram of a control arrangement in accordance with another embodiment of the present invention. As shown in <FIG>, multiple current controllers <NUM> are provided, each associated with a given voltage regulator. More specifically as shown a first current controller <NUM><NUM> is associated with a first voltage regulator (not shown) that provides a first voltage level (e.g., VCC) and a second current controller <NUM><NUM> is associated with a second voltage regulator (not shown) that provides a second (e.g., auxiliary) voltage level (e.g., VAux). Note that controllers <NUM> are shown at a high level to include a corresponding low pass filter <NUM>, a digital comparator <NUM>, and a down sampler <NUM>, but understand that these controllers may be configured as shown in <FIG>. Note that down sampler <NUM> may be optional in some embodiments. At a high level, when the received measured current exceeds a threshold level, a corresponding throttle signal is provided to the individual domains powered by this voltage regulator, as discussed above.

In addition, current controller <NUM>, via down sampler <NUM>, performs a down sampling of the measured current consumption, which is provided in turn to a power controller <NUM>. Power controller <NUM> may be implemented as a dedicated circuit or within a power controller of the processor. In any event, power controller <NUM> converts the multiple incoming digital current values into power values via converters <NUM><NUM>-<NUM>, which perform a current-to-power conversion via a multiplication operation according to a voltage delivered by a given voltage regulator (namely the regulated voltage minus any delivery loss (e.g., I<NUM>R<NUM>)) to provide a digital power value to a summer <NUM>, which sums the digital power values. Note that in other embodiments, power controller <NUM> may receive current values directly without inclusion of current controller <NUM>.

In turn, this summed power value is provided to a low pass filter <NUM>, which may operate at a longer time window duration, according to an average time window stored in a window storage <NUM>. In turn this filtered power value is provided to a digital comparator <NUM>, which compares it to a threshold value received from a threshold storage <NUM>. When it is determined in digital comparator <NUM> that the filtered measured power value exceeds the threshold value, a throttle event is indicated, and is communicated to a pulse lengthening circuit <NUM>. In general, pulse lengthening circuit <NUM> may operate the same as pulse lengthening circuit <NUM> discussed above, albeit at different throttle window duration, according to a value stored in a throttle window storage <NUM>. As such, pulse lengthening circuit <NUM>, based at least in part on the comparison output of digital comparator <NUM>, sends a throttle signal to the powered domains, to cause them to take appropriate throttling activity. Understand while shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

Referring now to <FIG>, shown is a flow diagram of a method in accordance with an embodiment of the present invention. More specifically as shown in <FIG>, method <NUM> is a method for performing dynamic current consumption control as described herein. As such, method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof, such as may be implemented using dedicated hardware circuitry of a processor and/or in connection with power control circuitry.

As illustrated, method <NUM> begins by receiving a plurality of digital current values for a plurality of processing circuits (block <NUM>). More specifically, a summation circuit may receive these digital current values from corresponding integrated voltage regulators, where each voltage regulator is associated with a processing circuit such as core, graphic unit, interconnect circuitry or so forth. Understand that in other cases, there may be fewer integrated voltage regulators than processing circuits, such that one or more of the integrated voltage regulators may provide a digital current value for multiple circuits.

In any case, at block <NUM> the summation circuit sums these multiple digital current values to obtain a total current value. Next, control passes to block <NUM> where this total current value may be filtered. As an example, a low pass filter such as implemented in a power controller as described herein may perform filtering of this total current value according to a programmable time constant. Next, it is determined at diamond <NUM> whether this filtered total current value exceeds a threshold value. If not, no further operation occurs in this iteration of the control loop, and method <NUM> may continue to operate to ensure that current consumption of a processor is maintained within appropriate levels.

Still with reference to <FIG> instead if it is determined that the filtered total current value exceeds the threshold value, control passes to block <NUM> where a throttle signal is sent to the processing circuits. Understand that in response to this throttle signal, at least one and likely multiple ones of the processing circuits may throttle their operation accordingly. For example, each processing circuit may be configured with a configured maximum current consumption value. In response to a throttle signal, a processing circuit may throttle its operation to ensure that its current consumption falls below this configured maximum current consumption value. With an arrangement as described herein, so long as the filtered total current value is less than the threshold value, processor operation may continue unthrottled. In this situation, one or more processing circuits may operate at current consumption levels exceeding their configured maximum current consumption values, while one or more other processing circuits are in operation below their configured maximum current consumption values. While shown at this high level in the embodiment of <FIG>, many variations and alternatives are possible.

Understand that fast current information obtained herein further may be used to perform additional power control techniques, such as to control level of a power supply that powers multiple voltage regulators of a platform. Referring now to <FIG>, shown is a flow diagram of a method in accordance with another embodiment of the present invention. More specifically as shown in <FIG>, method <NUM> is another method for performing dynamic current consumption control as described herein. As such, method <NUM> may be performed by hardware circuitry, firmware, software and/or combinations thereof, such as may be implemented using dedicated hardware circuitry of a processor and/or in connection with power control circuitry.

As illustrated, method <NUM> begins by receiving filtered total current values from current controllers associated with multiple voltage regulators (block <NUM>). Next, control passes to block <NUM> where these filtered total current values can be converted into power values. Then the power values may be summed (block <NUM>). After summing the power values into a summed power value, control passes to block <NUM>, where this summed power value is filtered, e.g., according to a different time constant than the filtering of current values described above.

Still referring to <FIG>, next it is determined at diamond <NUM> whether this filtered power value exceeds a threshold value. If not, no further operation occurs in this iteration of the control loop, and method <NUM> may continue to operate to ensure that current consumption of a processor is maintained within appropriate levels. Instead if it is determined that the filtered power value exceeds the threshold value, control passes to <NUM> where a throttle signal is sent to the powered domains, e.g., the processing circuits themselves (or at least a subset of such circuits associated with a given one of the voltage regulators). Understand that in response to this throttle signal, the powered domains may throttle operation accordingly, such as by reducing their operating parameters, to cause current demand to decrease.

Note that the terms "circuit" and "circuitry" are used interchangeably herein. As used herein, these terms and the term "logic" are used to refer to alone or in any combination, analog circuitry, digital circuitry, hard wired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry and/or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.

Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Embodiments also may be implemented in data and may be stored on a non-transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. Still further embodiments may be implemented in a computer readable storage medium including information that, when manufactured into a SoC or other processor, is to configure the SoC or other processor to perform one or more operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Claim 1:
An apparatus comprising:
a plurality of intellectual property, IP, circuits (<NUM>), each of the plurality of IP circuits (<NUM>) including a configuration register (<NUM>) to store a dynamic current budget; and
a power controller (<NUM>) coupled to the plurality of IP circuits (<NUM>), the power controller (<NUM>) including a dynamic current sharing control circuit (<NUM>) configured to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits (<NUM>), said current throttling hint information including priority information for the IP circuits (<NUM>); determine resolved throttle values for the IP circuits (<NUM>), based on the throttling hint information; generate a dynamic maximum current budget for each of the plurality of IP circuits (<NUM>) based at least in part on the respective resolved throttle value; and send the dynamic maximum current budgets to the IP circuits (<NUM>);
wherein each of the IP circuits (<NUM>) is configured to control its operation independent of its respective dynamic maximum current budget, and is further configured to control its operation to be maintained equal to or lower than its respective dynamic maximum current budget when a throttle condition is identified, wherein identifying the throttle condition comprises the power controller (<NUM>) determining that a total current consumption of a processor of the apparatus exceeds a given threshold, and sending a throttle signal to the IP circuits.