Patent Description:
Cache coherency is the uniformity of shared resource data that ends up stored in multiple local caches. Cache coherency is a concern when a first electronic device and a second electronic device share specific data. For example, when the first electronic device and the second electronic device support the cache coherency, specific data stored in the second electronic device are also modified when the first electronic device modifies the specific data.

The cache coherency may be required when a plurality of processors (or processor cores) process data in a state where the data are shared by the processors. Since electronic devices using multiple cores are widely used, research on how to support the cache coherency continues.

<CIT> discloses an accelerator device that shares the same coherent domain as hardware elements in a host computing device. The embodiments herein describe a mix of hardware and software coherency which reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. In one embodiment, an accelerator application executing on the host identifies a data set it wishes to transfer to the accelerator device to be processed. The accelerator application transfers ownership from a home agent in the host to the accelerator device. A slave agent can then take ownership of the data. As a result, any memory operation requests received from a requesting agent in the accelerator device can gain access to the data set in local memory via the slave agent without the slave agent obtaining permission from the home agent in the host.

<CIT> discloses the following: In one embodiment, a processor includes: one or more cores to execute instructions; at least one cache memory; and a coherence circuit coupled to the at least one cache memory. The coherence circuit may have a direct memory access circuit to receive a write request, and based at least in part on an address of the write request, to directly send the write request to a device coupled to the processor via a first bus, to cause the device to store data of the write request to a device-attached memory. Other embodiments are described and claimed.

Embodiments of the present disclosure provide an operating method of an electronic device capable of partially blocking cache coherency such that an independent operation is possible, together with supporting the cache coherency.

According to an embodiment of the present disclosure, there is provided an operating method of an electronic device which includes a processor and a memory, the method including: accessing, using the processor, the memory without control of an external host device in a first bias mode; sending, from the processor, information of the memory to the external host device when the first bias mode ends; and accessing, using the processor, the memory under control of the external host device in a second bias mode.

According to an embodiment of the present disclosure, there is provided an operating method of an electronic device which includes a processor and a memory, the method including: not intervening, with the processor, in an access of an external electronic device to a memory of the external electronic device, in a first bias mode; receiving, at the processor, information of the memory of the external electronic device from the external electronic device when the first bias mode ends; and controlling, using the processor, the access of the external electronic device to the memory of the external electronic device, in a second bias mode.

According to an embodiment of the present disclosure, there is provided an operating method of an electronic device which includes a host device and an accelerator, the method including: maintaining, using the host device, a coherency of a memory of the accelerator and a memory of the host device while the accelerator does not perform an operation; blocking, using the host device, the coherency of the memory of the accelerator and the memory of the host device while the accelerator performs an operation; and recovering, using the host device, the coherency of the memory of the accelerator and the memory of the host device after the accelerator completes the operation.

The above and other features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings.

<FIG> illustrates an electronic device <NUM> according to an embodiment of the present disclosure. Referring to <FIG>, the electronic device <NUM> may include a coherency host <NUM>, a first coherency device <NUM>, and a second coherency device <NUM>.

In an embodiment of the present disclosure, the coherency host <NUM> may be implemented with a central processing unit (CPU) (or a central processing unit core) or an application processor (AP) (or an application processor core). Each of the first coherency device <NUM> and the second coherency device <NUM> may be implemented with a graphic processing unit (or graphic processing core), a neural processor (or neural processor core), a neuromorphic processor (or neuromorphic processor core), a digital signal processor (or digital signal processor core), an image signal processor (or image signal processor core), etc..

In an embodiment of the present disclosure, the coherency host <NUM> may be implemented as a host device that controls the first coherency device <NUM> and the second coherency device <NUM>. Each of the first coherency device <NUM> and the second coherency device <NUM> may be implemented with an accelerator that supports an operation of the coherency host <NUM>.

The coherency host <NUM>, the first coherency device <NUM>, and the second coherency device <NUM> may be implemented with one semiconductor device or may be implemented with two or more independent semiconductor devices. The coherency host <NUM>, the first coherency device <NUM>, and the second coherency device <NUM> may be components of the electronic device <NUM>; however, each of the coherency host <NUM>, the first coherency device <NUM>, and the second coherency device <NUM> may be referred to as an "electronic device".

The coherency host <NUM>, the first coherency device <NUM>, and the second coherency device <NUM> may support the cache coherency. Each of the coherency host <NUM>, the first coherency device <NUM>, and the second coherency device <NUM> may include a memory that is used as a cache memory. In the case where the cache coherency is supported, when data of a cache memory included in one of the coherency host <NUM>, the first coherency device <NUM>, and the second coherency device <NUM> are updated, the same update may be performed on the remaining cache memories (under the condition that the same data are stored in the remaining cache memories).

The coherency host <NUM> may include a coherency host processor <NUM>, a host coherency memory <NUM>, and a host memory <NUM>. The coherency host processor <NUM> may support the cache coherency by using the host coherency memory <NUM> and may use the host memory <NUM> as a local memory.

The coherency host processor <NUM> may include a host processor core <NUM>, a coherency controller <NUM>, and a memory controller <NUM>. The host processor core <NUM> may execute an operating system of the electronic device <NUM>. The host processor core <NUM> may allocate or request a task to or from the first coherency device <NUM> and/or the second coherency device <NUM>.

An embodiment in which the electronic device <NUM> includes the coherency host <NUM>, the first coherency device <NUM>, and the second coherency device <NUM> is described, but the electronic device <NUM> may further include additional other components. For example, the electronic device <NUM> may include a third coherency device. The host processor core <NUM> may control the additional other components.

The coherency controller <NUM> may perform an operation associated with the cache coherency. The coherency controller <NUM> may support two or more modes associated with the cache coherency. The two or more modes may include a mode in which the cache coherency is partially supported, a mode in which the cache coherency is supported (e.g., fully supported), and a mode in which the cache coherency is not supported.

In the mode in which the cache coherency is partially supported, the coherency controller <NUM> may partially control accesses to memories associated with the coherency from among all memories associated with the cache coherency, for example, from among memories of the coherency host <NUM>, the first coherency device <NUM>, and/or the second coherency device <NUM>.

In the mode in which the cache coherency is supported, the coherency controller <NUM> may control accesses to the memories associated with the coherency from among all the memories associated with the cache coherency, for example, from among the memories of the coherency host <NUM>, the first coherency device <NUM>, and/or the second coherency device <NUM>.

The coherency controller <NUM> may control a switch between the two or more modes. The coherency controller <NUM> may perform a mode control in a <NUM>:<NUM> manner with each of the first coherency device <NUM> and the second coherency device <NUM>.

The coherency controller <NUM> may access the host coherency memory <NUM> through the memory controller <NUM> in response to a request of the host processor core <NUM>. When the cache coherency with the first coherency device <NUM> and/or the second coherency device <NUM> is supported and data of the host coherency memory <NUM> are modified, the coherency controller <NUM> may request the first coherency device <NUM> and/or the second coherency device <NUM> to perform the same modification on the same data stored in a cache coherency-related memory of the first coherency device <NUM> and/or the second coherency device <NUM> (immediately or after a specific time passes). For example, the coherency controller <NUM> may request the first coherency device <NUM> and/or the second coherency device <NUM> to perform the same modification on the same data stored in a device coherency memory <NUM> of the first coherency device <NUM> and/or a device coherency memory <NUM> of the second coherency device <NUM>.

When the cache coherency with the first coherency device <NUM> and/or the second coherency device <NUM> is supported and specific data of a cache coherency-related memory of the first coherency device <NUM> are modified, the coherency controller <NUM> may request the memory controller <NUM> or the second coherency device <NUM> to perform the same modification on the same data stored in a cache coherency-related memory of the host coherency memory <NUM> and/or the second coherency device <NUM> (immediately or after a specific time passes). For example, the same modification may be performed on the same data stored in the device coherency memory <NUM> of the second coherency device <NUM>.

Likewise, when the cache coherency with the first coherency device <NUM> and/or the second coherency device <NUM> is supported and specific data of a cache coherency-related memory of the second coherency device <NUM> are modified, the coherency controller <NUM> may request the memory controller <NUM> or the first coherency device <NUM> to perform the same modification on the same data stored in a cache coherency-related memory of the host coherency memory <NUM> and/or the first coherency device <NUM> (immediately or after a specific time passes). For example, the same modification may be performed on the same data stored in the device coherency memory <NUM> of the first coherency device <NUM>.

The memory controller <NUM> may access the host coherency memory <NUM> and the host memory <NUM>. For example, the memory controller <NUM> may access the host coherency memory <NUM> depending on a request of the coherency controller <NUM> and may access the host memory <NUM> depending on a request of the host processor core <NUM>.

In an embodiment of the present disclosure, the memory controller <NUM> may include a first controller for the host coherency memory <NUM> and a second controller for the host memory <NUM>.

The first coherency device <NUM> may include a coherency device processor <NUM>, the device coherency memory <NUM>, and a device memory <NUM>. The coherency device processor <NUM> may support the cache coherency by using the device coherency memory <NUM> and may use the device memory <NUM> as a local memory.

The coherency device processor <NUM> may include a device processor core <NUM>, a coherency engine <NUM>, and a memory controller <NUM>. The device processor core <NUM> may execute firmware of the first coherency device <NUM> or codes loaded by the coherency host <NUM>. The device processor core <NUM> may perform a task allocated or requested by the coherency host <NUM> by using the device coherency memory <NUM> or the device memory <NUM>.

For example, the device processor core <NUM> may process data (e.g., shared data) stored in the device coherency memory <NUM>. The device processor core <NUM> may use the device coherency memory <NUM> and/or the device memory <NUM> as a working memory for data processing. The device processor core <NUM> may update at least a portion of data of the device coherency memory <NUM> based on a processing result.

The coherency engine <NUM> may perform an operation associated with the cache coherency. The coherency engine <NUM> may support two or more modes associated with the cache coherency. The two or more modes may include a mode in which the cache coherency is partially supported, a mode in which the cache coherency is supported (e.g., fully supported), and a mode in which the cache coherency is not supported.

In the mode in which the cache coherency is partially supported, the coherency engine <NUM> may partially perform an access to a cache coherency-related memory, for example, the device coherency memory <NUM> under control of the coherency controller <NUM>. In the mode in which the cache coherency is supported, the coherency engine <NUM> may perform an access to the device coherency memory <NUM> under control of the coherency controller <NUM>. The coherency engine <NUM> may perform a switch between the two or more modes under control of the coherency controller <NUM>.

The coherency engine <NUM> may access the device coherency memory <NUM> through the memory controller <NUM> in response to a request of the coherency controller <NUM> and/or the device processor core <NUM>. When the cache coherency with the coherency host <NUM> is supported and data of the device coherency memory <NUM> are modified by the device processor core <NUM>, the coherency engine <NUM> may provide modification information (e.g., an address or a tag) and/or modified data to the coherency controller <NUM> (e.g., depending on a request of the coherency controller <NUM> or automatically in response to the modification being made).

The memory controller <NUM> may access the device coherency memory <NUM> and the device memory <NUM>. For example, the memory controller <NUM> may access the device coherency memory <NUM> depending on a request of the coherency engine <NUM> and may access the device memory <NUM> depending on a request of the device processor core <NUM>. In an embodiment of the present disclosure, the memory controller <NUM> may include a first controller for the device coherency memory <NUM> and a second controller for the device memory <NUM>.

The second coherency device <NUM> may include a coherency device processor <NUM>, the device coherency memory <NUM>, and a device memory <NUM>. The coherency device processor <NUM> may include a device processor core <NUM>, a coherency engine <NUM>, and a memory controller <NUM>.

Configurations, features, and functions of the coherency device processor <NUM>, the device coherency memory <NUM>, the device memory <NUM>, the device processor core <NUM>, the coherency engine <NUM>, and the memory controller <NUM> may respectively correspond to the configurations, features, and functions of the coherency device processor <NUM>, the device coherency memory <NUM>, the device memory <NUM>, the device processor core <NUM>, the coherency engine <NUM>, and the memory controller <NUM>. For example, the memory controller <NUM> may access the device coherency memory <NUM> depending on a request of the coherency engine <NUM> and may access the device memory <NUM> depending on a request of the device processor core <NUM>. Thus, additional description will be omitted to avoid redundancy.

In the embodiment of <FIG>, the cache coherency-related memories may include the host coherency memory <NUM>, the device coherency memory <NUM>, and the device coherency memory <NUM>. In an embodiment of the present disclosure, the communication for cache coherency between the host coherency memory <NUM>, the device coherency memory <NUM>, and the device coherency memory <NUM> may be based on the Compute Express Link™ (CXL™).

<FIG> illustrates an example of an operating method of the electronic device <NUM> according to an embodiment of the present disclosure. For brevity of description, an example of an operation between the coherency host <NUM> and the first coherency device <NUM> will be described with reference to <FIG> and <FIG>. However, the same operation may be performed between the coherency host <NUM> and the second coherency device <NUM>.

Referring to <FIG> and <FIG>, in operation S110, the electronic device <NUM> may determine a bias mode. For example, the coherency host <NUM> may determine the bias mode. As another example, the coherency host <NUM> may determine the bias mode depending on a request of the first coherency device <NUM>. As another example, the first coherency device <NUM> may determine the bias mode and may request the determined mode from the coherency host <NUM>. As yet another example, the coherency host <NUM> may determine the bias mode depending on a request of the second coherency device <NUM>.

When a first bias mode is determined, operation S121 to operation S123 may be performed. For example, the first bias mode may be a delayed host bias mode. In operation S121, the coherency host <NUM> and the first coherency device <NUM> may enter the delayed host bias mode.

The delayed host bias mode may partially support the cache coherency. While the first coherency device <NUM> operates in the delayed host bias mode together with the coherency host <NUM>, the coherency host <NUM> may ignore the cache coherency with the first coherency device <NUM> and may not intervene in the access of the first coherency device <NUM> to the device coherency memory <NUM>. The first coherency device <NUM> may access the device coherency memory <NUM> without the intervention of the coherency controller <NUM>. In other words, the first coherency device <NUM> may access the device coherency memory <NUM> independent of the coherency controller <NUM>.

The first coherency device <NUM> may access the device coherency memory <NUM> without the intervention or control of the coherency controller <NUM>. Accordingly, a speed at which the first coherency device <NUM> accesses the device coherency memory <NUM> may be improved compared to the case when the device coherency memory <NUM> is accessed through the coherency controller <NUM>.

The first coherency device <NUM> may ignore the cache coherency until a wanted point in time, for example, until a task allocated or requested by the coherency host <NUM> is completely processed. Accordingly, the atomicity and isolation may be secured in the operation of the first coherency device <NUM>.

While the delayed host bias mode is maintained, in operation S122, the first coherency device <NUM> may access the device coherency memory <NUM> quickly (e.g., without the control of the coherency controller <NUM>) and safely (e.g., with the atomicity and isolation maintained).

When the delayed host bias mode ends (e.g., when entering a host bias mode), the coherency host <NUM> and the first coherency device <NUM> may recover the cache coherency. For example, in operation S123, the first coherency device <NUM> may provide the coherency host <NUM> with information (e.g., an address or a tag) about modified data of data of the device coherency memory <NUM> and/or the modified data. The coherency host <NUM> may recover the cache coherency based on the received information and/or the received data.

When a second bias mode is determined in operation S110, operation S131 and operation S132 may be performed. For example, the second bias mode may be a host bias mode of the CXL™. In operation S131, the coherency host <NUM> and the first coherency device <NUM> may enter the host bias mode.

While the host bias mode is maintained, in operation S132, the first coherency device <NUM> may access the device coherency memory <NUM> under the control of the coherency controller <NUM>. Because the cache coherency is maintained in the host bias mode, an additional operation (e.g., the above coherency recovery) associated with the cache coherency is not required when the host bias mode ends.

When a third bias mode is determined in operation S110, operation S141 to operation S143 may be performed. For example, the third bias mode may be a device bias mode of the CXL™. In operation S141, the coherency host <NUM> and the first coherency device <NUM> may enter the device bias mode.

While the device bias mode is maintained, in operation S142, the coherency host <NUM> may not require the first coherency device <NUM> to maintain the cache coherency. The coherency host <NUM> may release a storage space (e.g., a cache memory space) in the host coherency memory <NUM> allocated for the first coherency device <NUM>. The first coherency device <NUM> may access the device coherency memory <NUM> without the control of the coherency controller <NUM>.

A process in which the coherency host <NUM> and the first coherency device <NUM> terminate the device bias mode may be selectively performed. For example, when the recovery of the cache coherency is required, operation S143 may be performed. In operation S143, the coherency host <NUM> may allocate a storage space (e.g., a cache memory space) for the first coherency device <NUM> to the host coherency memory <NUM>. The coherency host <NUM> may perform a cache fill operation in which data of the device coherency memory <NUM> of the first coherency device <NUM> are filled in the allocated storage space. As another example, when the recovery of the cache coherency is not required, operation S143 may not be performed.

<FIG> illustrates an example of a process in which the coherency host <NUM> and the first coherency device <NUM> enter the first bias mode from the second bias mode. For example, a process of switching a bias mode may be called a "bias flip".

Referring to <FIG> and <FIG>, in operation S210, the coherency host <NUM> may request the first coherency device <NUM> to perform the bias flip from the second bias mode to the first bias mode, or the first coherency device <NUM> may request the coherency host <NUM> to perform the bias flip from the second bias mode to the first bias mode.

In operation S220, the coherency host <NUM> may detect first modified data. For example, the coherency host <NUM> may detect, as the first modified data, data that are modified (or updated) only in the host coherency memory <NUM> after being stored in common in the host coherency memory <NUM> and the device coherency memory <NUM> of the first coherency device <NUM>.

For example, the host coherency memory <NUM> may be used as a cache memory including a plurality of cache lines, and the detection of the first modified data may be performed in units of at least one cache line. In operation S230, the coherency host <NUM> may send the first modified data corresponding to at least one cache line to the first coherency device <NUM>.

The first modified data may be sent together with information (e.g., an address or a tag) of the first modified data. The first coherency device <NUM> may update the device coherency memory <NUM> by using the information of the first modified data and the first modified data. For example, the first coherency device <NUM> may update (or replace) data of the device coherency memory <NUM>, which correspond to the information about the first modified data, with the first modified data.

When additional data necessary for the first coherency device <NUM> (e.g., data necessary for processing) are present in addition to the first modified data, the coherency host <NUM> may send the additional data and information (e.g., an address or a tag) of the additional data, as a portion of the first modified data and the information of the first modified data or together with the first modified data and the information of the first modified data. The first coherency device <NUM> may store the additional data and the information of the additional data in the device coherency memory <NUM>.

The transmitted data may be checked in operation S240 to operation S260. For example, in operation S240, the first coherency device <NUM> may again send, to the coherency host <NUM>, the first modified data and/or the information of the first modified data received from the coherency host <NUM>.

In operation S250, the coherency host <NUM> may compare the transmitted data and/or the information of the transmitted data provided to the first coherency device <NUM> with the received data and/or the information of the received data provided from the first coherency device <NUM>. When a comparison result indicates "matched", in operation S260, the coherency host <NUM> may send an acknowledgement message to the first coherency device <NUM>. When the comparison result indicates "mismatched", operation S230 to operation S260 may again be performed.

After the acknowledgement message is sent from the coherency host <NUM> to the first coherency device <NUM> in operation S260, in operation S270, the coherency host <NUM> and the first coherency device <NUM> may enter the first bias mode from the second bias mode. After the coherency host <NUM> and the first coherency device <NUM> enter the first bias mode, in operation S280, the coherency host <NUM> may maintain a storage space (e.g., a cache memory space) in the host coherency memory <NUM> allocated for the first coherency device <NUM> without release.

In an embodiment of the present disclosure, operation S240 to operation S260 marked by a dotted line may be selectively performed. In the case where operation S240 to operation S260 are omitted, after the first modified data are sent from the coherency host <NUM> to the first coherency device <NUM>, the coherency host <NUM> and the first coherency device <NUM> may enter the first bias mode from the second bias mode.

<FIG> illustrates an example of a process in which the coherency host <NUM> and the first coherency device <NUM> enter the second bias mode from the first bias mode. For example, a process of switching a bias mode may be called a "bias flip".

Referring to <FIG> and <FIG>, in operation S310, the coherency host <NUM> may request the first coherency device <NUM> to perform the bias flip from the first bias mode to the second bias mode, or the first coherency device <NUM> may request the coherency host <NUM> to perform the bias flip from the first bias mode to the second bias mode. In other words, either the coherency host <NUM> or the first coherency device <NUM> may initiate the bias flip request.

In operation S320, the first coherency device <NUM> may send information (e.g., an address or a tag) of modified data to the coherency host <NUM>. For example, the first coherency device <NUM> may send information of data (e.g., second modified data), which are modified (or updated) after entering the first bias mode, from among data stored in the device coherency memory <NUM> to the coherency host <NUM>.

In operation S330, based on the received information, the coherency host <NUM> may invalidate data, which correspond to the second modified data modified (or updated) by the first coherency device <NUM> during the first bias mode, from among the data stored in the host coherency memory <NUM>. The invalidation of data may be performed in units of at least one cache line. The invalidated cache line may be released from allocation. In other words, the data of the invalidated cache line may be deleted.

In an embodiment of the present disclosure, after the second modified data are provided from the first coherency device <NUM> to the coherency host <NUM>, as in the above description given with reference to operation S240 to operation S260 of <FIG>, the process of checking whether the second modified data are correctly transmitted may be selectively performed.

In operation S340, the coherency host <NUM> and the first coherency device <NUM> may enter the second bias mode from the first bias mode. Afterwards, the second modified data may be requested by the coherency host <NUM>. For example, the host processor core <NUM> of the coherency host <NUM> or the second coherency device <NUM> may require the second modified data.

Because data corresponding to the second modified data are absent from the host coherency memory <NUM> (due to the invalidation), a cache miss may occur. In operation S350, the coherency host <NUM> may request the second modified data from the first coherency device <NUM>. In response to the request, in operation S360, the first coherency device <NUM> may provide the second modified data and/or the information of the second modified data to the coherency host <NUM>.

In operation S370, the coherency host <NUM> may update the data of the host coherency memory <NUM> by storing the second modified data and/or the information of the second modified data in the host coherency memory <NUM>.

As described above, when the recovery of the cache coherency is required, the coherency host <NUM> and the first coherency device <NUM> may be configured to recover the cache coherency based on invalidation of data corresponding to the second modified data and a cache miss.

<FIG> illustrates another example of a process in which the coherency host <NUM> and the first coherency device <NUM> enter the second bias mode from the first bias mode. For example, a process of switching a bias mode may be called a "bias flip".

Referring to <FIG> and <FIG>, in operation S410, the coherency host <NUM> may request the first coherency device <NUM> to perform the bias flip from the first bias mode to the second bias mode, or the first coherency device <NUM> may request the coherency host <NUM> to perform the bias flip from the first bias mode to the second bias mode.

In operation S420, the first coherency device <NUM> may send the second modified data and/or the information (e.g., an address or a tag) of the second modified data to the coherency host <NUM>. For example, the first coherency device <NUM> may send, to the coherency host <NUM>, the second modified data, which are modified (or updated) after entering the first bias mode, from among data stored in the device coherency memory <NUM> and information of the second modified data.

In operation S430, the coherency host <NUM> may update the data of the host coherency memory <NUM> by storing the second modified data and/or the information of the second modified data in the host coherency memory <NUM>. In other words, the coherency host <NUM> may update a cache line in the host coherency memory <NUM>. In an embodiment of the present disclosure, after the second modified data and/or the information of the second modified data are provided from the first coherency device <NUM> to the coherency host <NUM>, as in the above description given with reference to operation S240 to operation S260 of <FIG>, the process of checking whether the second modified data are correctly transmitted may be selectively performed.

In operation S440, the coherency host <NUM> and the first coherency device <NUM> may enter the second bias mode from the first bias mode. Compared to the operating method of <FIG>, the first coherency device <NUM> sends the second modified data and/or the information of the second modified data to the coherency host <NUM> before entering the second bias mode. The coherency host <NUM> updates the data of the host coherency memory <NUM> by using the second modified data. In other words, after the cache coherency is completely recovered, the coherency host <NUM> and the first coherency device <NUM> may enter the second bias mode.

<FIG> illustrates an example corresponding to the case where the electronic device <NUM> is in the second bias mode before entering the first bias mode. Referring to <FIG>, the device coherency memory <NUM> of the first coherency device <NUM> may store input data for processing of the device processor core <NUM>. The device coherency memory <NUM> of the second coherency device <NUM> may store input data for processing of the device processor core <NUM>.

The cache coherency may be maintained between data of the device coherency memory <NUM> of the first coherency device <NUM>, data of the device coherency memory <NUM> of the second coherency device <NUM>, and the host coherency memory <NUM> of the coherency host <NUM>. In other words, the input data of the device processor core <NUM> and the input data of the device processor core <NUM> may be prepared based on the cache coherency. Like that shown in <FIG>, in <FIG>, the coherency engine <NUM> may communicate directly with the coherency controller <NUM> and the coherency engine <NUM> may communicate directly with the coherency controller <NUM>.

<FIG> illustrates an example corresponding to the case where the electronic device <NUM> operates in the first bias mode. Referring to <FIG>, the cache coherency may be blocked between data of the device coherency memory <NUM> of the first coherency device <NUM>, data of the device coherency memory <NUM> of the second coherency device <NUM>, and the host coherency memory <NUM> of the coherency host <NUM>. For example, unlike that shown in <FIG>, the coherency engine <NUM> may not be linked with the coherency controller <NUM> and the coherency engine <NUM> may not be linked with the coherency controller <NUM>.

The device coherency memory <NUM> of the first coherency device <NUM> may store input data for processing of the device processor core <NUM>. The device processor core <NUM> may perform processing based on the data stored in the device coherency memory <NUM> without the control of the coherency controller <NUM> through the coherency engine <NUM>. Accordingly, the processing of the device processor core <NUM> may be performed quickly.

The device processor core <NUM> may store a processing result in the device coherency memory <NUM>. Because the cache coherency (between the first coherency device <NUM> and the coherency host <NUM>) is blocked, the processing operation of the device processor core <NUM> is not notified to the coherency host <NUM>. Because the processing of the device processor core <NUM> is not exposed and the atomicity and isolation are secured, the device processor core <NUM> may safely access the device coherency memory <NUM>.

The device coherency memory <NUM> of the second coherency device <NUM> may store input data for processing of the device processor core <NUM>. The device processor core <NUM> may perform processing based on the data stored in the device coherency memory <NUM> without the control of the coherency controller <NUM> through the coherency engine <NUM>. Accordingly, the processing of the device processor core <NUM> may be performed quickly.

The device processor core <NUM> may store a processing result in the device coherency memory <NUM>. Because the cache coherency (between the second coherency device <NUM> and the coherency host <NUM>) is blocked, the processing operation of the device processor core <NUM> is not notified to the coherency host <NUM>. Because the processing of the device processor core <NUM> is not exposed and the atomicity and isolation are secured, the device processor core <NUM> may safely access the device coherency memory <NUM>.

<FIG> illustrates an example corresponding to the case where the electronic device <NUM> completes processing in the first bias mode and enters the second bias mode. Referring to <FIG>, the device coherency memory <NUM> of the first coherency device <NUM> may store output data corresponding to a processing result of the device processor core <NUM>. The device coherency memory <NUM> of the second coherency device <NUM> may store output data corresponding to a processing result of the device processor core <NUM>.

As the electronic device <NUM> enters the second bias mode, the cache coherency of the coherency host <NUM>, the first coherency device <NUM>, and the second coherency device <NUM> may be recovered. Data modified by the processing of the first coherency device <NUM> may be shared by the coherency host <NUM> and/or the second coherency device <NUM>. Data modified by the processing of the second coherency device <NUM> may be shared by the coherency host <NUM> and/or the first coherency device <NUM>.

As described above, the electronic device <NUM> according to an embodiment of the present disclosure blocks the cache coherency while the first coherency device <NUM> and/or the second coherency device <NUM> performs an operation. When the operation of the first coherency device <NUM> and/or the second coherency device <NUM> is completed, the cache coherency is recovered. In other words, the cache coherency may be delayed until the operation of the first coherency device <NUM> and/or the second coherency device <NUM> is completed.

While the cache coherency is delayed, the first coherency device <NUM> and/or the second coherency device <NUM> may access the device coherency memory <NUM> and/or the device coherency memory <NUM> in a fast, safe manner and may perform an operation. When the cache coherency is recovered, only data modified by the first coherency device <NUM> and/or the second coherency device <NUM> may be shared, and thus, a time and resource necessary to recover the cache coherency may decrease.

In particular, in the case of a database server, most processing is performed on previously stored data, and a result of the processing causes the update of the previously stored data. The methods according to an embodiment of the present disclosure, which support fast and safe operations by synchronizing input data and output data through the cache coherency before and after the operations and delaying the cache coherency during the operations, may show optimum performance in an environment such as the database server.

<FIG> is a diagram of a system <NUM> to which a storage device is applied, according to an embodiment of the present disclosure. The system <NUM> of <FIG> may be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of things (IOT) device. However, the system <NUM> of <FIG> is not necessarily limited to the mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (e.g., a navigation device).

Referring to <FIG>, the system <NUM> may include a main processor <NUM>, memories (e.g., 1200a and 1200b), and storage devices (e.g., 1300a and 1300b). In addition, the system <NUM> may include at least one of an image capturing device <NUM>, a user input device <NUM>, a sensor <NUM>, a communication device <NUM>, a display <NUM>, a speaker <NUM>, a power supplying device <NUM>, and a connecting interface <NUM>.

The main processor <NUM> may control all operations of the system <NUM>, more specifically, operations of other components included in the system <NUM>. The main processor <NUM> may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor <NUM> may include at least one CPU core <NUM> and further include a controller <NUM> configured to control the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. In some embodiments of the present disclosure, the main processor <NUM> may further include an accelerator <NUM>, which is a dedicated circuit for a high-speed data operation, such as an artificial intelligence (AI) data operation. The accelerator <NUM> may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and be implemented as a chip that is physically separate from the other components of the main processor <NUM>.

The memories 1200a and 1200b may be used as main memory devices of the system <NUM>. Although each of the memories 1200a and 1200b may include a volatile memory, such as static random access memory (SRAM) and/or dynamic RAM (DRAM), each of the memories 1200a and 1200b may include non-volatile memory, such as a flash memory, phase-change RAM (PRAM) and/or resistive RAM (RRAM). The memories 1200a and 1200b may be implemented in the same package as the main processor <NUM>.

The storage devices 1300a and 1300b may serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may respectively include storage controllers (STRG CTRL) 1310a and 1310b and Non-Volatile Memorys (NVMs) 1320a and 1320b configured to store data under the control of the storage controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and/or RRAM.

The storage devices 1300a and 1300b may be physically separated from the main processor <NUM> and included in the system <NUM> or implemented in the same package as the main processor <NUM>. In addition, the storage devices 1300a and 1300b may have types of solid-state devices (SSDs) or memory cards and be removably combined with other components of the system <NUM> through an interface, such as the connecting interface <NUM> that will be described below. The storage devices 1300a and 1300b may be devices to which a standard protocol, such as a universal flash storage (UFS), an embedded multi-media card (eMMC), or a non-volatile memory express (NVMe), is applied, without being limited thereto.

The image capturing device <NUM> may capture still images or moving images. The image capturing device <NUM> may include a camera, a camcorder, and/or a webcam.

The user input device <NUM> may receive various types of data input by a user of the system <NUM> and include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor <NUM> may detect various types of physical quantities, which may be obtained from the outside of the system <NUM>, and convert the detected physical quantities into electric signals. The sensor <NUM> may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device <NUM> may transmit and receive signals between other devices outside the system <NUM> according to various communication protocols. The communication device <NUM> may include an antenna, a transceiver, and/or a modem.

The power supplying device <NUM> may convert power supplied from a battery embedded in the system <NUM> and/or an external power source, and supply the converted power to each of components of the system <NUM>.

The connecting interface <NUM> may provide connection between the system <NUM> and an external device, which is connected to the system <NUM> and capable of transmitting and receiving data to and from the system <NUM>. The connecting interface <NUM> may be implemented by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE <NUM>, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

In an embodiment of the present disclosure, the coherency host <NUM> described with reference to <FIG> may be implemented to correspond to the CPU core <NUM>. The first coherency device <NUM> and/or the second coherency device <NUM> described with reference to <FIG> may be implemented to correspond to the accelerator <NUM>. As another example, the coherency host <NUM> described with reference to <FIG> may be implemented to correspond to the main processor <NUM>. The first coherency device <NUM> and/or the second coherency device <NUM> described with reference to <FIG> may be implemented with a separate sub-processor (e.g., an accelerator processor) assisting the main processor <NUM>.

In the above embodiments, components according to the present disclosure are described by using the terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. do not involve an order or a numerical meaning of any form.

In the above embodiments, components according to embodiments of the present disclosure are referenced by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit (IC), an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. In addition, the blocks may include circuits implemented with semiconductor elements in an integrated circuit, or circuits enrolled as an intellectual property (IP).

Claim 1:
An operating method of an electronic device (<NUM>) which includes a processor (<NUM>, <NUM>) and a memory (<NUM>, <NUM>), the method comprising:
accessing (S122), using the processor (<NUM>, <NUM>), the memory (<NUM>, <NUM>) without control of an external host device in a first bias mode;
sending (S123), from the processor (<NUM>, <NUM>), information of the memory (<NUM>, <NUM>) to the external host device when the first bias mode ends;
accessing (S132), using the processor (<NUM>, <NUM>), the memory (<NUM>, <NUM>) under control of the external host device in a second bias mode; and
entering (S270) the first bias mode from the second bias mode;
wherein the entering (S270) of the first bias mode from the second bias mode includes:
receiving (S230), at the processor (<NUM>, <NUM>), data from the external host device;
updating, using the processor (<NUM>, <NUM>), the memory (<NUM>, <NUM>) with the received data;
the method further characterised by sending (S240), from the processor (<NUM>, <NUM>), the received data to the external host device; and
entering (S270) the first bias mode in response to an acknowledgement message received (S260) from the external host device, wherein the acknowledgement message is sent from the external host device in response to a comparison (S250) of the data, which are sent from the external host device and received at the processor (<NUM>, <NUM>), and the received data, which are sent from the processor (<NUM>, <NUM>) and received at the external host device, indicating a match.