Patent Description:
Capacitor structures for deep sub-micron CMOS can be constructed with two flat parallel plates separated by a thin dielectric layer. The plates are formed by layers of conductive material, such as metal or polysilicon. The capacitor structure is usually isolated from the substrate by an underlying dielectric layer. To achieve high capacitance density in these structures, additional chip areas are required to introduce extra plates. As critical dimensions of 3D-NAND devices in integrated circuits shrink to achieve greater storage capacity, the capacitor structures cannot meet the scaling requirement that requires smaller dimension and higher capacitance density.

Each of <CIT>, <CIT>, <CIT> and <CIT> discloses a vertical type capacitor structure comprising a substrate, at least two conductive plates and an insulating structure in between, which are formed in the substrate and extend from a first main surface to a second main surface of the substrate.

The concepts relate to a novel capacitor structure, and more particularly, to a vertical-type capacitor structure in which the plates extend from a top surface of a substrate to an opposing bottom surface of the substrate. The plates are concentrically disposed in the substrate to achieve high capacitance density in a reduced chip area to meet the scaling requirement. This capacitor structure is not forming part of the claimed invention.

As 3D NAND technology migrates towards high density and high capacity, especially from <NUM> to <NUM> architecture, the number of devices, the number of metal lines has increased significantly, and the chip area has remained basically unchanged. So the space for introducing other electronic components, such as capacitors and bond pads, is getting smaller and smaller. Metal-oxide-silicon (MOS)/metal-oxide-metal (MOM) capacitors typically require a large silicon area. Moreover, a large MOS capacitor area could increase the time-dependent dielectric breakdown (TDDB) failure rate. Therefore, a new capacitor structure is needed to meet the circuit requirements (e.g., high capacitance density) without occupying too much space.

In the present disclosure, a novel capacitor structure is introduced. This structure is not forming part of the claimed invention. According to an aspect of the disclosure, an integrated circuit (IC) chip is provided. The IC chip includes a substrate that has opposing first and second main surfaces. A plurality of transistors are formed at a first location in the first main surface of the substrate and a capacitor is formed at a second location of the substrate. The capacitor further includes a first conductive plate that is formed in the substrate and extends from the first main surface to the second main surface of the substrate, a second conductive plate that is formed in the substrate and extends from the first main surface to the second main surface, and an insulating structure that is formed between the first conductive plate and the second conductive plate and extends from the first main surface to the second main surface.

In some embodiments, the first conductive plate, the second conductive plate, and the insulating structure are close-shaped (such as ring-shaped) and are concentrically arranged in the substrate so that the insulating structure is disposed between the first plate and the second plate. For example, the first conductive plate, the second conductive plate, and the insulating structure can be concentrically arranged in the substrate and have a square profile, a circle profile, a triangle profile, a rectangle profile, an oval profile, a diamond profile, an trapezium profile, a pentagon profile, a hexagon profile, a parallelogram profile, or a star profile.

In an embodiment, the first conductive plate and the second conductive plates are made of doped silicon or metal. The first conductive plate can be electrically coupled with a first polarity, and the second conductive plate can be electrically coupled with a second polarity.

The capacitor structure of the disclosure can further include a dielectric layer formed over the first main surface of the substrate and a plurality of contacts formed in the insulating layer. The plurality of contacts can extend into the first and second conductive plates and be electrically coupled with the first and second conductive plates.

According to another aspect of the disclosure, a method for manufacturing the capacitor structure is provided. This method is forming part of the claimed invention.

In the disclosed method, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. A plurality of contacts are formed in the insulating layer. The plurality of contacts further extend into the doped region. Subsequently, a portion of the substrate is removed from a second main surface of the substrate. A plurality of trenches and conductive lines are created in the doped region of the substrate through etching the substrate from the second main surface on which a patterned mask is formed. The trenches pass through the substrate to expose the insulating layer, the conductive lines are spaced apart from each other by the trenches, and the contacts are in direct contact with the conductive lines. The plurality of trenches are subsequently filled with a dielectric material.

According to yet another aspect of the disclosure, which is not forming part of the claimed invention, a semiconductor device is provided. The semiconductor device can include a substrate that has opposing first and second main surfaces. A memory cell region is formed in the first main surface of the substrate, and a capacitor structure is formed adjacent to the memory cell region. The capacitor structure includes a first conductive plate in the substrate that extends from the first main surface to the second main surface, a second conductive plate in the substrate that extends from the first main surface to the second main surface, and an isolation structure that is disposed between the first conductive plate and the second conductive plate and extends from the first main surface to the second main surface.

In some embodiments, the memory cell region of the semiconductor device disclosed in the present disclosure includes a DRAM memory cell, a NAND memory cell, a three dimensional NAND memory cell, a phase change memory cell, or a magnetoresistive random-access memory (MRAM) cell.

According to the disclosure, a vertical-style capacitor structure can be formed in the substrate. The capacitor structure has a silicon-dielectric-silicon configuration where the plates of the capacitor structure are made of portions of substrate. The capacitor structure can be formed in a spare area of the silicon substrate. The plates of the capacitor structure extend from a top surface to a bottom surface of the substrate, and have a concentric profile that provides high capacitance density. The plates of the capacitor structure are spaced apart by an insulating structure that extends from the top surface to the bottom surface of the substrate. The insulating structure further separates the capacitor structure and adjacent active memory cells from any electrical interference. The capacitor structure of the present disclosure provides high capacitance density, occupies less chip area, prevents electric failure, and meets the scaling requirement.

The method disclosed in <FIG> and <FIG> relate to the claimed invention. The capacitor structures disclosed in <FIG> and <FIG> do not form part of the claimed invention, but are useful for the understanding of the invention.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed features may be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

<FIG> is a cross-sectional view of a capacitor structure <NUM>, and <FIG> is a top down view of the capacitor structure <NUM>. The cross-sectional view of the capacitor structure <NUM> in <FIG> is obtained from a plane same as the vertical plane containing line A-A' in <FIG>.

As shown, the capacitor structure <NUM> includes a substrate <NUM> having a top surface (or first main surface) 102a and a bottom surface (or second main surface) 102b. The capacitor structure <NUM> can further include a plurality of first conductive plates and a plurality of second conductive plates that are formed in the substrate <NUM>, and extend from the top surface 102a to the bottom surface 102b. For example, two first conductive plates 108a/108c, and two second conductive palates 108b/108d are included in the capacitor structure <NUM> as shown in <FIG>. It should be noted that <FIG> are merely examples, and the capacitor structure <NUM> can include more than two first conductive plates, and more than two second conductive plates based on technology requirements. The first and second conductive plates can have a top critical dimension (CD) CD1, a bottom CD CD2, and a height T1. The CD1 and CD2 are defined based on the desired capacitance value and larger than <NUM>. The T1 can be in a range from <NUM> to <NUM>.

In <FIG>, the first conductive plates 108a/108c and the second conductive plates 108b/108d are shown as close-shaped (such as ring-shaped) and concentrically arranged in the substrate <NUM>. The first conductive plates 108a/108c and the second conductive plates 108b/108d are alternatively disposed and spaced apart by a plurality of insulating structure 104a-104d. In alternative embodiments, the first conductive plate, the second conductive plate, and the insulating structure can be concentrically arranged in the substrate and have a square profile, a circle profile, a triangle profile, a rectangle profile, an oval profile, a diamond profile, an trapezium profile, a pentagon profile, a hexagon profile, a parallelogram profile, or a star profile.

The substrate <NUM> may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate <NUM> may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. In an embodiment of <FIG>, the substrate <NUM> is a Group IV semiconductor that may include Si, Ge, or SiGe. The substrate <NUM> may be a bulk wafer or an epitaxial layer.

The first conductive plates 108a/108c and the second conductive plates 108b/108d can be silicon doped with P-type dopant via an ion implantation process. For example, the first conductive plates 108a/108c and the second conductive plates 108b/108d can be doped with boron at a dopant concentration from 4e15 cm-<NUM> to 8e15 cm-<NUM>. In another example, the first conductive plates 108a/108c and the second conductive plates 108b/108d can be silicon doped with N-type dopant via the ion implantation, such as doping Arsenic with a dopant concentration from 5e15 cm-<NUM> to 8e15 cm-<NUM>. As shown in <FIG>, a dopant region <NUM> can be formed during the ion implantation in the substrate <NUM>. In yet another example, the first and second conductive plates can be made of metal, such as tungsten, copper or aluminum. The first conductive plates can be electrically coupled with a first polarity, and the second conductive plates can be electrically coupled with a second polarity. In some examples, the first polarity is positive and the second polarity is negative. In other examples, the first polarity is negative and the second polarity is positive depending on the circuit requirements.

Still referring to <FIG>, the insulating structures <NUM> extend from the top surface 102a to the bottom surface 102b of the substrate <NUM>. The insulating structures <NUM> can also be ring-shaped and concentrically arranged in the substrate <NUM>. The insulating structures <NUM> are disposed between the first plates 108a/108c and the second plates 108b/108d and function as insulating layers of capacitors. The insulating structures <NUM> can be made of SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, or high K material. The insulating structures <NUM> can have a top critical dimension (CD) D3 in a range from <NUM> to <NUM>, a bottom CD D4 between <NUM> and <NUM>, and a height T1 between <NUM> and <NUM>.

Various capacitors can be formed based on the capacitor structure <NUM>. For example, the first conductive plate 108a, the insulating structure 104b, and the second conductive plate 108b can form a first capacitor when the first conductive plate 108a is electrically coupled with the first polarity and the second conductive plate 108b is electrically coupled with the second polarity. Similarly, in another example, the first conductive plate 108c, the insulating structure 104d, and the second conductive plate 108d can form a second capacitor. In yet another example, the first conductive plate 108c, the insulating structure 104c, and the second conductive plate 108b can form a third capacitor, depending on the circuit requirements.

The capacitor structure <NUM> further includes a dielectric layer <NUM> formed over the top surface 102a of the substrate <NUM>. The dielectric layer <NUM> can include SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, or high K material. The dielectric layer <NUM> can have a thickness in a range from <NUM> to <NUM>. A plurality of contacts <NUM> can further be formed in the dielectric layer <NUM> and extend into the first and second conductive plates <NUM>. The contacts <NUM> can have a top CD D5 in a range from <NUM> to <NUM>, a bottom CD D6 in a range from <NUM> to <NUM>, and a height T2 between <NUM> to <NUM>. The contacts <NUM> can be made of tungsten, copper or aluminum. The contacts <NUM> can extend into the first and second conductive plates <NUM> with a depth between <NUM> and <NUM> and electrically coupled with the first and second conductive plates <NUM>. It should be noted that the contacts <NUM> are drawn with dashed lines in <FIG> to indicate a perspective view of the contacts <NUM>.

<FIG> illustrate the intermediate stages in the formation of a capacitor structure <NUM>. Each of the figure number of <FIG> includes letter "A" and "B", where letter "A" indicates a cross-sectional view and "B" indicates a top down view. The cross-sectional view is obtained from a plane same as the vertical plane containing line A-A' in the top down view.

As shown in <FIG>, a substrate <NUM> is prepared. Subsequently, a doped region <NUM> is formed through an ion implantation process, an in situ doped epitaxial growth, a plasma doping process (PLAD), or other method as known in the art. In an embodiment, the doped region <NUM> can be doped with N-type dopant that includes arsenic, phosphorous, antimony, or other N-type donor material. In another embodiment, the doped region <NUM> can be doped with P-type dopant that includes boron, aluminum, gallium, indium, or other P-type acceptor material. The depth T3 of the doped region <NUM> can be in a range from <NUM> to <NUM>. In an embodiment of <FIG>, the doped region <NUM> is doped with boron and has a dopant concentration between 4e15 cm-<NUM> and 8e15 cm-<NUM>.

The substrate <NUM> may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate <NUM> may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The substrate <NUM> may be a bulk wafer or an epitaxial layer. In the embodiment of <FIG>, substrate <NUM> is a Group IV semiconductor that may include Si, Ge, or SiGe.

In <FIG>, a dielectric layer <NUM> formed over the top surface 102a of the substrate <NUM>. The dielectric layer <NUM> can include SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, or high K material. The dielectric layer <NUM> can have a thickness in a range from <NUM> to <NUM>. Any suitable deposition process can be applied to form the dielectric layer <NUM>, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof.

<FIG> illustrate that a plurality of contacts <NUM> are formed in the dielectric layer <NUM>. In order to form the contacts <NUM>, a patterned mask stack (not shown) can be formed over the dielectric layer <NUM>. The mask stack can include one or more hard mask layers and a photoresist layer. The mask stack can be patterned according to any suitable technique, such as a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), and the like. When the patterned mask stack is formed, an etching process, such as a wet etching or a dry etching, can be applied. The etching process etches through the dielectric layer <NUM> and transfers the patterns of the mask stack into the dielectric layer <NUM> to form a plurality of contact openings (not shown in <FIG>). The contact openings can have a tapered profile. The contact openings further extend into the substrate <NUM> by recessing a portion of the substrate with a depth between <NUM> and <NUM>. When the etching process is completed, a subsequent plasma ashing and a wet clean can be applied to remove the remaining mask stack. The contact openings can be ring-shaped and concentrically disposed in the doped region <NUM>.

A conductive layer (not shown in <FIG>) can be formed in the contact openings. The conductive layer can further cover a top surface of the dielectric layer <NUM>. The conductive layer may include cobalt (Co), tungsten (W), ruthenium (Ru), aluminum (Al), copper (Cu), or other suitable conductors, and be deposited by a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, e-beam evaporation, or any combination thereof. Alternatively, the conductive layer may include copper (Cu), copper magnesium (CuMn), copper aluminum (CuAl), and the like, and an electrochemical plating (ECP) process may be applied. In some embodiments, a barrier layer (not shown in <FIG>), such as Ti, TiN, Ta, TaN, or other suitable materials, is formed before the conductive layer. The barrier layer can be formed by using physical vapor deposition (PVD), CVD, ALD, or other well-known deposition techniques.

When the conductive layer is formed in the contact openings, a subsequent surface planarization process, such as a chemical mechanical polishing (CMP), is performed to remove excessive conductive layer over the top surface of dielectric layer <NUM>, and the remaining conductive layer in the contact openings forms the contacts <NUM>. As shown in <FIG>, the contacts <NUM> are ring-shaped and concentrically disposed in the doped region <NUM>. The contacts <NUM> further extend into the doped region <NUM> with a depth of between <NUM> and <NUM>. The contacts <NUM> have a tapered profile with a top CD in a range from <NUM> to <NUM>, a bottom CD in a range from <NUM> to <NUM>, and a height between <NUM> to <NUM>.

<FIG> illustrates a flipping process where the substrate <NUM> is flipped upside down and the bottom surface 102b is exposed for a subsequent substrate thinning process.

In <FIG>, a thinning process is introduced to remove a bottom portion of the substrate <NUM> from the bottom surface 102b. In some embodiments, the bottom portion of the substrate <NUM> that has not been doped is removed. Any suitable process can be applied to thin down the substrate <NUM>, such as chemical mechanical polishing (CMP), etching back, or any combination thereof. After the thinning process, the substrate <NUM> has a thickness of T1 that is in a range from <NUM> to <NUM>. It should be noted that the contacts <NUM> are drawn with dashed lines in <FIG> and <FIG> to indicate a perspective view of the contacts <NUM>.

In <FIG>, a plurality of trenches <NUM> and conductive lines <NUM> are formed. In order to form the trenches <NUM> and conductive lines <NUM>, a patterned mask stack (not shown) can be formed over the bottom surface 102b of the substrate <NUM> in the doped region <NUM>. The mask stack can include one or more hard mask layers and a photoresist layer. The mask stack can be patterned according to any suitable technique, such as a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), and the like.

When the patterned mask stack is formed, an etching process, such as a wet etching or a dry etching, can be applied. The etching process etches through the substrate <NUM> and transfers the patterns of the mask stack into the substrate <NUM>. Portions of the substrate that are exposed by the patterned mask stack are removed to form a plurality of trenches 114a-114d and portions of the substrate that are protected by patterned mask stack remains to form a plurality of conductive lines 116a-116d in the doped region <NUM>. The trenches <NUM> expose the dielectric layer <NUM>. The trenches <NUM> can have a top CD D3 in a range from <NUM> to <NUM>, a bottom CD D4 between <NUM> and <NUM>, and a height T1 from <NUM> to <NUM>. The trenches <NUM> and the conductive lines <NUM> are ring-shaped and alternatively disposed in the substrate <NUM>. Moreover, the contacts <NUM> are aligned to land on the conductive lines <NUM> by the patterned mask stack.

In <FIG>, an insulating layer (not shown) is formed to fill the trenches <NUM>. The insulating layer further covers the bottom surface 102b of the substrate <NUM>. The insulating layer can include SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, or high K material. The insulating layer can be formed by a chemical vapor deposition (CVD), a physical vapor deposition (PVD), an atomic layer deposition (ALD), a diffusion process, or any combination thereof. When the insulating layer is formed, a subsequent surface planarization process, such as a CMP process or an etching back process, can be performed to remove excessive insulating layer over the bottom surface 102b.

Upon the completion of the surface planarization, the remaining insulating layer in the trenches <NUM> forms the insulating structures <NUM>, and the conductive lines <NUM> becomes the conductive plates <NUM> of the capacitor structure that are separated from each other by the insulating structure <NUM>. The conductive plates <NUM> includes a first plates 108a/108c that is electrically coupled with a first polarity, and a second plates 108b/108d that is electrically coupled with a second polarity. The first conductive plates 108a/108c and the second conductive plates 108b/108d are ring-shaped and concentrically disposed in the substrate <NUM>. The first conductive plates 108a/108c and the second conductive plates 108b/108d further extend from the top surface 102a to the bottom surface 102b. The insulating structures <NUM> extend from the bottom surface 102b to the top surface 102a of the substrate. The insulating structures <NUM> are ring-shaped and concentrically disposed between the first and the second conductive plates. A plurality of contacts <NUM> are formed in the dielectric layer <NUM>. The contacts <NUM> pass through the dielectric layer <NUM> and further land on the first and second conductive plates. As shown in <FIG>, a complete capacitor structure <NUM> is formed that is identical to the capacitor structure <NUM> illustrated in <FIG>.

<FIG> illustrates an integrated circuit chip <NUM> in accordance with an embodiment of the present disclosure, which is not forming part of the claimed invention. The integrated circuit chip <NUM> has a boundary <NUM>, and a memory cell region <NUM> that is located at a first location of the integrated circuit chip <NUM>. The memory cell region <NUM> can include a plurality of memory cells, such as DRAM memory cells, NAND memory cells, three dimensional (3D)-NAND memory cells, phase change memory cells, or magnetoresistive random-access memory (MRAM) cells. The integrated circuit chip <NUM> further includes one or more capacitor structures <NUM> that are adjacent to the memory cell region <NUM> and located at a second location of the integrated circuit chip <NUM>. The capacitor structures are identical to the capacitor structure <NUM> illustrated in <FIG> and <FIG>. Each of the capacitor structures <NUM> and the memory cell region <NUM> are separated by the respective insulating structure 104a to prevent electrical interference.

<FIG> is a flowchart of a process <NUM> for manufacturing a capacitor structure in accordance with some embodiments of the present disclosure. The process <NUM> begins at step <NUM> where a doped region is formed in the substrate. The doped region can be doped with a N-type dopant or a P-type dopant. The doped region can be formed via an ion implantation process, an in situ doped epitaxial growth, a plasma doping process (PLAD), or other suitable techniques. In some embodiments, step <NUM> can be performed as illustrated with reference to <FIG>.

The process <NUM> then proceeds to step <NUM> where a dielectric layer is formed over the doped region. The dielectric layer can include SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, or high K material. The dielectric layer can have a thickness in a range from <NUM> to <NUM>. In some embodiment, step <NUM> can be performed as illustrated with reference to <FIG>.

In step <NUM> of the process <NUM>, a plurality of contacts can further be formed in the dielectric layer and extends into the doped region. The contacts can have a tapered profile with a top CD in a range from <NUM> to <NUM>, a bottom CD in a range from <NUM> to <NUM>, and a height between <NUM> to <NUM>. The contacts can be made of tungsten, copper or aluminum. The contacts are ring-shaped and concentrically disposed in the doped region. In some embodiment, step <NUM> can be performed as illustrated with reference to <FIG>.

The process <NUM> then proceeds to step <NUM> where the substrate is thinned down from the bottom surface. In some embodiments, the substrate can be flipped upside down to expose the bottom surface for a thinning process. A bottom portion of the substrate that has not been doped can be removed by a CMP process, an etching back process, or a combination thereof. In some embodiment, step <NUM> can be performed as illustrated with reference to <FIG>.

In step <NUM> of the process <NUM>, a plurality of trenches and conductive plates can be formed in the doped region through a combination of a photolithographic process and an etching process. A patterned mask stack can be formed over the bottom surface of the substrate in the doped region. A subsequent etching processing is introduced to etch through the substrate to transfer the pattern of the mask stack into the substrate. Portions of the substrate that are exposed by the patterned mask stack are removed to form trenches. Portions of the substrate in the doped region that are protected by the patterned mask stack remains to function as the conductive plates. The trenches and the conductive plates are ring-shaped, alternatively disposed, and concentrically arranged in the doped region. In some embodiment, step <NUM> can be performed as illustrated with reference to <FIG>.

The process <NUM> then proceeds to step <NUM> where an insulating layer is formed to fill the trenches. The insulating layer further covers the bottom surface of the substrate. A subsequent surface planarization process, such as a CMP process or an etching back process, can be performed to remove excessive insulating layer over the bottom surface. Upon the completion of the surface planarization, the remaining insulating layer in the trenches forms the insulating structures, and the final capacitor structure is completed.

The final capacitor structure includes a plurality of first conductive plates that is electrically coupled with a first polarity, and a plurality of second conductive plates that is electrically coupled with a second polarity. The first conductive plates and the second conductive plates are ring-shaped and concentrically disposed in the doped region of the substrate. The first conductive plates and the second conductive plates further extend from the top surface to the bottom surface of the substrate. The insulating structures extend from the bottom surface to the top surface of the substrate. The insulating structures are ring-shaped and concentrically disposed between the first and the second plates. A plurality of contacts are formed in the dielectric layer. The contacts pass through the dielectric layer and further extend into the first and second conductive plates. In some embodiment, step <NUM> can be performed as illustrated with reference to <FIG>.

It should be noted that additional steps can be provided before, during, and after the process <NUM>, and some of the steps described can be replaced, eliminated, or performed in different order for additional embodiments of the process <NUM>. In subsequent process steps, various additional interconnect structures (e.g., metallization layers having conductive lines and/or vias) may be formed over the semiconductor device <NUM>. Such interconnect structures electrically connect the semiconductor device <NUM> with other contact structures and/or active devices to form functional circuits. Additional device features such as passivation layers, input/output structures, and the like may also be formed.

The various embodiments described herein offer several advantages over related examples. For example, the conventional metal-oxide-silicon (MOS) /metal-oxide-metal (MOM) capacitors typically require a large silicon area. A large MOS capacitor area could increase the time-dependent dielectric breakdown (TDDB) failure rate. In the present disclosure, a vertical-style capacitor structure is formed in the substrate. The capacitor structure has a silicon-dielectric-silicon configuration where the plates of the capacitor structure are made of portions of substrate. The capacitor structure can be formed in a spare region of the silicon substrate. The plates of the capacitor structure extend from a top surface to a bottom surface of the substrate, and have a concentric profile that provides high capacitance density and occupy less chip area. The plates of the capacitor structure are spaced apart by an insulating structure that extends from the top surface to the bottom surface of the substrate. The insulating structure further separates the capacitor structure from adjacent active memory cells to prevent electrical interference. The capacitor structure of the present disclosure provides high capacitance density, occupies less chip area, prevents electrical failure, and meets the scaling requirement.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.

Claim 1:
A method for forming a capacitor structure comprising:
forming a doped region (<NUM>) in a substrate (<NUM>) from a first main surface (102a), the doped region being doped with first dopants at a first dopant concentration;
forming a dielectric layer (<NUM>) over the first main surface and the doped region (<NUM>) of the substrate (<NUM>);
forming a plurality of contacts (<NUM>) in the dielectric layer, the plurality of contacts (<NUM>) extending into the doped region (<NUM>),
removing a portion of the substrate (<NUM>) from a second main surface (102b);
forming a plurality of trenches (<NUM>, 114a, 114b, 114c, 114d) and conductive lines (<NUM>, 116a, 116b, 116c, 116d) in the doped region (<NUM>) of the substrate (<NUM>) through etching the doped region of the substrate (<NUM>) from the second main surface (102b), wherein the trenches (<NUM>, 114a, 114b, 114c, 114d) pass through the substrate (<NUM>) to expose the dielectric layer, the conductive lines (<NUM>, 116a, 116b, 116c, 116d) are spaced apart from each other by the trenches (<NUM>, 114a, 114b, 114c, 114d), and formed from the doped region that is doped with the first dopants at the first dopant concentration, and the contacts (<NUM>) are in direct contact with the conductive lines (<NUM>, 116a, 116b, 116c, 116d); and
filling the plurality of trenches (<NUM>, 114a, 114b, 114c, 114d) with a dielectric material so as to form an insulating structure (<NUM>, 104a, 104b, 104c, 104d) between the conductive plates (<NUM>, 108a, 108b, 108c, 108d).