Patent Description:
The present disclosure relates generally to the field of semiconductor packaging. In particular, the present disclosure relates to a cost-effective chip on RDL on substrate (CRoS) package and fabrication methods thereof. More particularly, the present invention relates to a semiconductor package according to the pre-characterizing part of the independent claim. Such a semiconductor package is disclosed in documents <CIT> and <CIT>. A similar semiconductor package is disclosed in documents <CIT>, <CIT>, <CIT>, <CIT>, <CIT> and <CIT>.

Document <CIT> discloses encapsulating a component and its solder balls.

Emerging markets are always driving demand for higher performance, higher bandwidth, lower power consumption as well as increasing functionality in mobile applications. Packaging technology has become more challenging and complicated than ever before, driving advance silicon nodes, finer bump pitch as well as finer line width and spacing substrate manufacturing capabilities to satisfy the increasing requirements in semiconductor industry.

Although emerging markets are driving advanced technologies in high performance mobile devices, assembly cost is still the major issue to be addressed. As the substrate cost is always the significant factor in a flip chip package, flip chip assembly with a low cost substrate has become a hot topic in the industry.

A prior art method for forming a semiconductor package generally involves the following steps. First, multiple cored substrate components are mounted on a carrier. Each of the cored substrate components has a plurality of copper pillars disposed on a chip side thereof. Subsequently, the multiple cored substrate components are over-molded and the end surface of each of the plurality of copper pillars is exposed by grinding or polishing. A re-distribution layer (RDL) is then fabricated on the top surface of the molding compound and is electrically coupled to the cored substrate component through the plurality of pillars. Thereafter, multiple integrated circuit (IC) dies are mounted on the RDL.

The above-described prior art has several drawbacks. For example, to compensate the thickness variation of the cored substrate components, an adequate height (><NUM>) of the plurality of copper posts is required. However, the tall copper pillars may reduce latency and incur high cost of copper plating. The diameter size of the copper pillars is constrained because of the shear force demand. Further, the design rule of routing is constrained by the positions of the plurality of copper posts and the dimension of each copper post. The RDL may suffer from package warping due to the over-molding process.

It is an object of the invention to provide an improved semiconductor package with chip on RDL on substrate (CRoS) configuration in order to solve the above-mentioned prior art problems or shortcomings. A semiconductor package according to the invention is defined in the independent claim. The dependent claims define preferred embodiments thereof.

One aspect of the invention provides a semiconductor package including a substrate component comprising a first surface, a second surface opposite to the first surface, and a sidewall surface extending between the first surface and the second surface; a re-distribution layer (RDL) structure disposed on the first surface and electrically connected to the first surface through first connecting elements comprising solder bumps or balls; a plurality of ball grid array (BGA) balls mounted on the second surface of the substrate component; and at least one integrated circuit die mounted on the RDL structure through second connecting elements.

Preferably, the first surface, the second surface, and the sidewall surface of the substrate component are not covered with an encapsulant.

Preferably, a gap is disposed between the RDL structure and the substrate component.

Preferably, the gap has a standoff height h<NUM> that is smaller than <NUM>.

Preferably, the gap is filled with an underfill and the connecting elements are surrounded by the underfill.

Preferably, the underfill comprises a non-conductive paste or a non-conductive film.

Preferably, the gap is not filled with an underfill and the first connecting elements are at least partially exposed.

Preferably, the RDL structure comprises dielectric layers, traces in the dielectric layers, bonding pads at a substrate-side surface of the RDL structure for connecting with the substrate component, and re-distributed bonding pads disposed at a chip-side surface of the RDL structure for connecting with the at least one integrated circuit die.

Preferably, the first connecting elements are directly connected to the bonding pads, respectively.

Preferably, the RDL structure has an RDL pitch of line/space (L/S) ≤ <NUM>/<NUM>.

A sidewall surface of the RDL structure is aligned with the sidewall surface of the substrate component along a vertical direction.

Another aspect useful to understand the invention provides a semiconductor package including a substrate component comprising a first surface, a second surface opposite to the first surface, and a sidewall surface extending between the first surface and the second surface; an encapsulant covering the second surface and the sidewall surface, wherein the first surface is flush with an upper surface of the encapsulant; a re-distribution layer (RDL) structure disposed directly on the first surface of the substrate component and on the upper surface of the encapsulant; a plurality of ball grid array (BGA) balls mounted on the second surface of the substrate component; and at least one integrated circuit die mounted on the RDL structure through a plurality of connecting elements.

Preferably, the encapsulant is in direct contact with an upper portion of each of the BGA balls.

Preferably, the RDL structure comprises dielectric layers, traces in the dielectric layers, and re-distributed bonding pads disposed at a chip-side surface of the RDL structure for connecting with the at least one integrated circuit die.

Another aspect useful to understand the invention provides a semiconductor package including a substrate component comprising a first surface, a second surface opposite to the first surface, and a sidewall surface extending between the first surface and the second surface; an encapsulant covering the first surface, the second surface and the sidewall surface; a re-distribution layer (RDL) structure disposed on an upper surface of the encapsulant and electrically connected to the first surface through first connecting elements comprising solder bumps or balls; a plurality of ball grid array (BGA) balls mounted on the second surface of the substrate component; and at least one integrated circuit die mounted on the RDL structure through a plurality of second connecting elements.

Preferably, the first surface is not flush with an upper surface of the encapsulant.

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. In the drawings:.

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. The abbreviation "BGA" stands for "ball grid array".

Packaging of an integrated circuit (IC) chip can involve attaching the IC chip to a substrate (a packaging substrate) which, among other things, provides mechanical support and electrical connections between the chip and other electronic components of a device. Substrate types include, for example, cored substrates, including thin core, thick core (laminate BT (bismaleimide-triazine resin) or FR-<NUM> type fibrous board material), and laminate core, as well as coreless substrates. Cored package substrates, for example, can be built up layer by layer around a central core, with layers of conductive material (usually copper) separated by layers of insulating dielectric, with interlayer connections being formed with through holes or microvias (vias).

The present disclosure pertains to a chip on RDL on substrate (CRoS) package with fine RDL line/space (e.g., L/S ≤ <NUM>/<NUM>; i.e. both of line width and space smaller than or equal to <NUM>) integrated on a substrate component. In some embodiments, the substrate component may be a buried, over-molded substrate component. The layer count of the substrate component can be reduced so as to improve the production yield of the substrate component, and the cost of the final package can be reduced. Further, heterogeneous integration with multi-functional devices, passive components or memory can be implemented in one package without preliminary packaging process, e.g., fan-out packaging processes or chip-on-wafer (CoW) processes.

Please refer to <FIG> are schematic, cross-sectional diagrams showing an exemplary method for fabricating a semiconductor package with a buried substrate component according to one embodiment useful to understand the invention, wherein <FIG> shows a cross section of an individual semiconductor package after singulation and de-carrier.

As shown in <FIG>, a carrier <NUM> is provided. For example, the carrier <NUM> may comprise a base substrate <NUM> such as a glass substrate, a metal substrate, or a plastic substrate in a panel form or a wafer form, but is not limited thereto. Preferably, the carrier <NUM> may comprise a flexible film <NUM>, such as a resin film or an adhesive film, laminated on an upper surface of the base substrate <NUM>. Preferably, for example, the flexible film <NUM> may have a thickness of about <NUM>-<NUM>.

Preferably, a plurality of cored substrate components <NUM> is distributed on the flexible film <NUM>. Only two cored substrate components 100a and 100b are demonstrated for the sake of simplicity. For example, the cored substrate component 100a may have a thickness that is smaller than that of the cored substrate component 100b due to the process variation. Each of the cored substrates <NUM> has a first surface S<NUM> for electrically coupling with at least one chip or electronic device thereon, a second surface S<NUM> for electrically coupling with an external circuitry such as a printed circuit board or a system board, and a sidewall surface SW extending between the first surface S<NUM> and the second surface S<NUM>. Each of the cored substrates <NUM> may comprise a core layer <NUM>, which is composed of a material such as bismaleimide-triazine (BT) resin or the like, and build-up interconnect structure BL<NUM> and BL<NUM> disposed on two opposite surfaces of the core layer <NUM>, respectively.

Preferably, a plurality of bonding pads BP<NUM> is disposed on the first surface S<NUM> of the cored substrates <NUM>. Preferably, a plurality of solder ball bonding pads BP<NUM> is disposed on the second surface S<NUM> of the cored substrates <NUM> such that solder balls (or BGA balls) <NUM> can be mounted on the solder ball bonding pads BP<NUM>, respectively, for electrically connecting an external electronic device such as a printed circuit board (not shown). Preferably, at least part of each of the solder balls <NUM> sinks and is buried into the flexible film <NUM>.

By controlling the proportion of the solder balls <NUM> embedded in the flexible film <NUM>, the first surfaces S<NUM> of the two exemplary cored substrate components 100a and 100b can be coplanar. Preferably, a standoff height h<NUM> between the cored substrate component 100a and a top surface of the flexible film <NUM> is greater than a standoff height h<NUM> between the cored substrate component 100b and the top surface of the flexible film <NUM>.

As shown in <FIG>, subsequently, the plurality of cored substrate components <NUM> is over-molded by an encapsulant <NUM> by performing a molding process. For example, the molding process may be compression molding. Preferably, the molding process may be performed by dispensing, but is not limited thereto. Preferably, the encapsulant <NUM> may comprise an engineered molding compound comprising an epoxy or a resin, but is not limited thereto. Preferably, the encapsulant <NUM> may surround each of the cored substrate components <NUM> and may fill into the gap <NUM> between each of the cored substrate components <NUM> and the carrier <NUM>. Therefore, the encapsulant <NUM> may cover the second surface S<NUM> and the sidewall surface SW.

After the molding process is completed, a polishing process or a grinding process is performed to remove excess encapsulant <NUM> from the first surface S<NUM> of each of the plurality of cored substrate components <NUM>, thereby revealing the plurality of flip-chip bonding pads BP<NUM>. At this point, the first surface S<NUM> of each of the plurality of cored substrate components <NUM> is approximately flush with an upper surface 120a of the encapsulant <NUM>.

As shown in <FIG>, a re-distribution layer (RDL) structure <NUM> is then formed directly on the exposed first surface S<NUM> of each of the plurality of cored substrate components <NUM> and on the upper surface 120a of the encapsulant <NUM>. A portion of the RDL structure <NUM> protrudes beyond the sidewall surface SW of the cored substrate component <NUM>. Preferably, the formation of the RDL structure <NUM> may generally involve the steps of dielectric deposition, metal (e.g., copper) plating, lithography, etching, and/or chemical mechanical polishing (CMP), etc. The RDL structure <NUM> may comprise dielectric layers <NUM>, traces <NUM> in the dielectric layers <NUM>, and re-distributed bonding pads RBP for connecting with an integrated circuit chip or die.

The dielectric layers <NUM> may comprise silicon oxide, silicon oxy-nitride, silicon nitride, and/or low-k dielectric layers, but is not limited thereto. It is noteworthy that no copper post or copper pillar is formed between the RDL structure <NUM> and the plurality of cored substrate components <NUM>. Therefore, the cost of the package can be reduced and the performance of the package can be improved.

After the RDL structure <NUM> is completed, at least one integrated circuit die is mounted on the RDL structure <NUM>. As shown in <FIG>, for example, functional chips or dies <NUM> may be mounted on the RDL structure <NUM> through the connecting elements <NUM> such as metal bumps, solder bumps, solder-capped metal bumps, micro-bumps, C4 bumps, metal pillars, or the like. The functional dies <NUM> may comprise a first die 300a and a second die 300b, for example, for each package. The first die 300a may have a function different from that of the second die 300b so as to achieve heterogeneous integration. For example, the first die 300a may be a system on a chip (SoC) and the second die 300b may be a memory die, but is not limited thereto. It is to be understood that various functional dies such as passive components, antenna components, or the like may also be employed.

Preferably, prior to the placement of the functional chips or dies <NUM>, a circuit test for the RDL structure <NUM> may be performed. If the RDL structure <NUM> of a particular package fails the test, dummy dies may be mounted on the RDL structure that fails the test, instead of the functional dies.

Subsequently, a de-carrier process may be performed to detach the carrier <NUM> and a dicing process or a cutting process may be performed to singulate the individual semiconductor package, as shown in <FIG>.

Preferably, as shown in <FIG>, the semiconductor package <NUM> may be a multi-die package and comprises the cored substrate component <NUM> having a core layer <NUM>, which is composed of a material such as bismaleimide-triazine resin or the like, and build-up interconnect structure BL<NUM> and BL<NUM> disposed on two opposite surfaces of the core layer <NUM>, respectively. A plurality of plated through holes (PTHs) 101p may be provided in the core layer <NUM> for electrically connecting the build-up interconnect structure BL<NUM> with the build-up interconnect structure BL<NUM>. For example, preferably, the cored substrate component <NUM> may be a <NUM>-layer, <NUM>-layer, or <NUM>-layer substrate, but is not limited thereto.

The cored substrate component <NUM> is surrounded by the encapsulant <NUM>. The cored substrate component <NUM> has the first surface S<NUM> for mounting at least one chip or electronic device thereon, the second surface S<NUM> for electrically coupling with an external circuitry such as a printed circuit board or a system board, and a sidewall surface SW extending between the first surface S<NUM> and the second surface S<NUM>. The solder balls <NUM> are mounted on the solder ball bonding pads BP<NUM>, respectively, on the second surface S<NUM>. Preferably, the sidewall surface SW is covered by the encapsulant <NUM>. Preferably, the second surface S<NUM> is at least partially covered by the encapsulant <NUM>. Preferably, the encapsulant <NUM> is in direct contact with an upper portion of each of the solder balls <NUM>.

The first surface S<NUM> of the cored substrate component <NUM> is flush with the upper surface 120a of the encapsulant <NUM>. The RDL structure <NUM> is formed on the first surface S<NUM> of the cored substrate component <NUM> and on the upper surface 120a of the encapsulant <NUM>. Preferably, the RDL structure <NUM> comprises dielectric layers <NUM>, traces <NUM> in the dielectric layers <NUM>, and re-distributed bonding pads RBP for connecting with an integrated circuit chip or die. The dielectric layers <NUM> may comprise silicon oxide, silicon oxy-nitride, silicon nitride, and/or low-k dielectric layers, but is not limited thereto. Preferably, the RDL structure <NUM> can have a tighter RDL pitch (i.e., L/S ≤ <NUM>/<NUM>).

It is noteworthy that no copper post or copper pillar is formed between the RDL structure <NUM> and the cored substrate component <NUM> since the RDL structure <NUM> is fabricated directly on the first surface S<NUM> of the substrate component <NUM> and on the upper surface 120a of the encapsulant <NUM>. Therefore, the cost of the package can be reduced and the performance of the package can be improved.

Preferably, the semiconductor package <NUM> further comprises the first die 300a and the second die 300b mounted on the RDL structure <NUM> through the connecting elements <NUM>. The connecting elements <NUM> may comprise metal bumps, solder bumps, solder-capped metal bumps, micro-bumps, C4 bumps, metal pillars, or the like. Preferably, the first die 300a may have a function different from that of the second die 300b so as to achieve heterogeneous integration. For example, the first die 300a may be a system on a chip (SoC) and the second die 300b may be a memory die, but is not limited thereto. It is to be understood that various functional dies such as passive components, antenna components, or the like may also be employed.

Please refer to <FIG> are schematic, cross-sectional diagrams showing an exemplary "RDL-first" method for fabricating a semiconductor package with a buried substrate component according to another embodiment useful to understand the invention, wherein like layers, regions, or elements are designated by like numeral numbers or labels. <FIG> shows a cross section of an individual semiconductor package after singulation and de-carrier.

As shown in <FIG>, likewise, a carrier <NUM> is provided. For example, the carrier <NUM> may comprise a base substrate <NUM> such as a glass substrate, a metal substrate, or a plastic substrate in a panel form or a wafer form, but is not limited thereto. Preferably, the carrier <NUM> may comprise a flexible film <NUM>, such as a resin film, a release film, or an adhesive film, laminated on an upper surface of the base substrate <NUM>.

An RDL structure <NUM> is then formed on the flexible film <NUM>. Preferably, the formation of the RDL structure <NUM> may generally involve the steps of dielectric deposition, metal (e.g., copper) plating, lithography, etching, and/or CMP, etc. The RDL structure <NUM> may comprise dielectric layers <NUM>, traces <NUM> in the dielectric layers <NUM>, bonding pads <NUM> at an upper surface of the RDL structure <NUM> for connecting with a substrate component, and re-distributed bonding pads RBP at a lower surface of the RDL structure <NUM> for connecting with an integrated circuit chip or die. Preferably, the dielectric layers <NUM> may comprise silicon oxide, silicon oxy-nitride, silicon nitride, and/or low-k dielectric layers, but is not limited thereto.

As shown in <FIG>, a plurality of cored substrate components (or substrate components) <NUM> is distributed on the RDL structure <NUM>. For the sake of simplicity, only two cored substrate components 100a and 100b are demonstrated. For example, the cored substrate component 100a may have a thickness that is smaller than that of the cored substrate component 100b due to the process variation. Each of the cored substrates <NUM> has a first surface S<NUM> for electrically coupling with at least one chip or electronic device thereon, a second surface S<NUM> for electrically coupling with an external circuitry such as a printed circuit board or a system board, and a sidewall surface SW extending between the first surface S<NUM> and the second surface S<NUM>. Each of the cored substrates <NUM> may comprise a core layer <NUM>, which is composed of a material such as bismaleimide-triazine (BT) resin or the like, and build-up interconnect structure BL<NUM> and BL<NUM> disposed on two opposite surfaces of the core layer <NUM>, respectively.

Preferably, the cored substrate component 100a and the cored substrate component 100b are mounted to the RDL structure <NUM> through a plurality of connecting elements <NUM> such as solder bumps or solder balls. Preferably, the second surface S<NUM> of the cored substrate component 100a may be not leveled with the second surface S<NUM> of the cored substrate component 100b. Preferably, a plurality of bonding pads BP<NUM> is disposed on the first surface S<NUM> of the cored substrates <NUM>. Preferably, a plurality of solder ball bonding pads BP<NUM> is disposed on the second surface S<NUM> of the cored substrates <NUM>.

Subsequently, the cored substrate components 100a and 100b are over-molded by an encapsulant <NUM> by performing a molding process. For example, the molding process may be compression molding. Preferably, the molding process may be performed by dispensing, but is not limited thereto. Preferably, the encapsulant <NUM> may comprise a molding compound comprising an epoxy or a resin, but is not limited thereto. Preferably, the encapsulant <NUM> may surround each of the cored substrate components <NUM> and may fill into the gap between each of the cored substrate components <NUM> and the carrier <NUM>. Preferably, the second surface S<NUM> that faces upwardly at this point is also covered with the encapsulant <NUM>.

As shown in <FIG>, via holes 120v are formed in the encapsulant <NUM> to expose the solder ball bonding pads BP<NUM> on the second surface S<NUM> of the cored substrates <NUM>, respectively. Preferably, the via holes 120v may be formed by laser drilling processes, but is not limited thereto.

As shown in <FIG>, subsequently, a plurality of solder balls <NUM> can be disposed on the solder ball bonding pads BP<NUM> within the via holes 120v, respectively, for electrically connecting an external electronic device such as a printed circuit board (not shown).

As shown in <FIG>, another carrier <NUM> is attached to the upper surface 120a of the encapsulant <NUM>. Preferably, the carrier <NUM> may comprise a base substrate <NUM> such as a glass substrate, a metal substrate, or a plastic substrate in a panel form or a wafer form, but is not limited thereto. Preferably, the carrier <NUM> may comprise a flexible film <NUM>, such as a resin film or an adhesive film, laminated on an upper surface of the base substrate <NUM>.

Preferably, the solder balls <NUM> may be at least partially buried in the flexible film <NUM>. Subsequently, a de-bonding process may be performed to remove the carrier <NUM> from a lower surface of the RDL structure <NUM>. At this point, the re-distributed bonding pads RBP for connecting with an integrated circuit chip or die are revealed.

As shown in <FIG>, the carrier <NUM> with the components mounted thereon is flipped <NUM> degrees. Subsequently, functional chips or dies <NUM> are mounted on the RDL structure <NUM> through the connecting elements <NUM> such as metal bumps, solder bumps, solder-capped metal bumps, micro-bumps, C4 bumps, metal pillars, or the like. The functional dies <NUM> may comprise a first die 300a and a second die 300b, for example, for each package. The first die 300a may have a function different from that of the second die 300b so as to achieve heterogeneous integration. For example, the first die 300a may be a system on a chip (SoC) and the second die 300b may be a memory die, but is not limited thereto. It is to be understood that various functional dies such as passive components, antenna components, or the like may also be employed.

Preferably, as shown in <FIG>, the semiconductor package <NUM> may be a multi-die package and comprises the cored substrate component <NUM> having a core layer <NUM>, which is composed of a material such as bismaleimide-triazine resin or the like, and build-up interconnect structure BL<NUM> and BL<NUM> disposed on two opposite surfaces of the core layer <NUM>, respectively. Likewise, a plurality of plated through holes (PTHs) 101p may be provided in the core layer <NUM>. For example, preferably, the cored substrate component <NUM> may be a <NUM>-layer, <NUM>-layer, or <NUM>-layer substrate.

Preferably, the first surface S<NUM> is at least partially covered by the encapsulant <NUM>. Therefore, the first surface S<NUM> of the cored substrate component <NUM> is not flush with the upper surface 120a of the encapsulant <NUM>. The connecting elements <NUM> are disposed on the bonding pads BP<NUM> for further connection, respectively. The connecting elements <NUM> are surrounded by the encapsulant <NUM>.

The RDL structure <NUM> is formed on the upper surface 120a of the encapsulant <NUM>. Preferably, the RDL structure <NUM> comprises dielectric layers <NUM>, traces <NUM> in the dielectric layers <NUM>, and re-distributed bonding pads RBP for connecting with an integrated circuit chip or die. The dielectric layers <NUM> may comprise silicon oxide, silicon oxy-nitride, silicon nitride, and/or low-k dielectric layers, but is not limited thereto. Preferably, the RDL structure <NUM> can have a tighter RDL pitch (i.e., L/S ≤ <NUM>/<NUM>).

It is noteworthy that no copper post or copper pillar is formed between the RDL structure <NUM> and the cored substrate component <NUM>. Therefore, the cost of the package can be reduced and the performance of the package can be improved. Further, since the RDL structure <NUM> is formed first on the carrier <NUM>, the production yield of the package can be improved.

Preferably, the semiconductor package <NUM> further comprises the first die 300a and the second die 300b mounted on the RDL structure <NUM> through the connecting elements <NUM>. The connecting elements <NUM> may comprise metal bumps, solder bumps, solder-capped metal bumps, micro-bumps, C4 bumps, metal pillars, or the like. Preferably, the first die 300a may have a function different from that of the second die 300b so as to achieve heterogeneous integration. For example, the first die 300a may be a SoC and the second die 300b may be a memory die, but is not limited thereto. It is to be understood that various functional dies such as passive components, antenna components, or the like may also be employed.

Please refer to <FIG> are schematic, cross-sectional diagrams showing an exemplary "RDL-first" method for fabricating a semiconductor package with a buried substrate component according to another embodiment useful to understand the invention, wherein like layers, regions, or elements are designated by like numeral numbers or labels. <FIG> shows a cross section of an individual semiconductor package after functional die placement.

An RDL structure <NUM> is then formed on the flexible film <NUM>. Preferably, the formation of the RDL structure <NUM> may generally involve the steps of dielectric deposition, metal (e.g., copper) plating, lithography, etching, and/or CMP, etc. The RDL structure <NUM> may comprise dielectric layers <NUM>, traces <NUM> in the dielectric layers <NUM>, bonding pads <NUM> at an upper surface of the RDL structure <NUM> for connecting with a substrate component, and re-distributed bonding pads RBP at a lower surface of the RDL structure <NUM> for connecting with an integrated circuit chip or die. Preferably, the dielectric layers <NUM> may comprise silicon oxide, silicon oxy-nitride, silicon nitride, and/or low-k dielectric layers, but is not limited thereto. Preferably, the RDL structure <NUM> can have a tighter RDL pitch (i.e., L/S ≤ <NUM>/<NUM>).

As shown in <FIG>, a plurality of cored substrate components (or BGA substrate components) <NUM> is distributed on the RDL structure <NUM>. For the sake of simplicity, only two cored substrate components 100a and 100b are demonstrated. For example, the cored substrate component 100a may have a thickness that is smaller than that of the cored substrate component 100b due to the process variation. Each of the cored substrates <NUM> has a first surface S<NUM> for electrically coupling with at least one chip or electronic device thereon and a second surface S<NUM> for electrically coupling with an external circuitry such as a printed circuit board or a system board. Each of the cored substrates <NUM> may comprise a core layer <NUM>, which is composed of a material such as bismaleimide-triazine resin or the like, and build-up interconnect structure BL<NUM> and BL<NUM> disposed on two opposite surfaces of the core layer <NUM>, respectively.

Preferably, the cored substrate component 100a and the cored substrate component 100b are mounted to the RDL structure <NUM> through a plurality of connecting elements <NUM> such as solder bumps or solder balls. Preferably, the second surface S<NUM> of the cored substrate component 100a may be not leveled with the second surface S<NUM> of the cored substrate component 100b. Preferably, a plurality of bonding pads BP<NUM> is disposed on the first surface S<NUM> of the cored substrates <NUM>. Preferably, a plurality of solder ball bonding pads BP<NUM> is disposed on the second surface S<NUM> of the cored substrates <NUM>. Solder balls (or BGA balls) <NUM> are provided on the solder ball bonding pads BP<NUM>, respectively.

As shown in <FIG>, subsequently, the cored substrate components 100a and 100b are over-molded by an encapsulant <NUM> by performing a molding process. For example, the molding process may be compression molding. Preferably, the molding process may be performed by dispensing, but is not limited thereto. Preferably, the encapsulant <NUM> may comprise a molding compound comprising an epoxy or a resin, but is not limited thereto. Preferably, the encapsulant <NUM> may surround each of the cored substrate components <NUM> and may fill into the gap between each of the cored substrate components <NUM> and the carrier <NUM>. Preferably, the second surface S<NUM> that faces upwardly at this point is also covered with the encapsulant <NUM> and each of the solder balls <NUM> is at least partially revealed.

As shown in <FIG>, a de-carrier process may be performed to detach the carrier <NUM> and a dicing process or a cutting process may be performed to singulate the individual package <NUM>'.

As shown in <FIG>, subsequently, functional chips or dies <NUM> are mounted on the RDL structure <NUM> through the connecting elements <NUM> such as metal bumps, solder bumps, solder-capped metal bumps, micro-bumps, C4 bumps, metal pillars, or the like, thereby forming the semiconductor package <NUM>. The functional dies <NUM> may comprise a first die 300a and a second die 300b, for example, for each package. The first die 300a may have a function different from that of the second die 300b so as to achieve heterogeneous integration. For example, the first die 300a may be a SoC and the second die 300b may be a memory die, but is not limited thereto. It is to be understood that various functional dies such as passive components, antenna components, or the like may also be employed.

Please refer to <FIG>. <FIG> and <FIG> are schematic, cross-sectional diagrams showing an exemplary "RDL-first" method for fabricating a semiconductor package with a buried substrate component according to another embodiment useful to understand the invention. <FIG> and <FIG> are schematic, cross-sectional diagrams showing an exemplary "RDL-first" method for fabricating a semiconductor package with a buried substrate component according to an embodiment of the invention, wherein a sidewall surface of an RDL structure is aligned with a sidewall surface of a cored substrate component along a vertical direction. In <FIG>, like layers, regions, or elements are designated by like numeral numbers or labels. <FIG> shows a cross section of an individual semiconductor package after functional die placement.

An RDL structure <NUM> is then formed on the flexible film <NUM>. Preferably, the formation of the RDL structure <NUM> may generally involve the steps of dielectric deposition, metal (e.g., copper) plating, lithography, etching, and/or CMP, etc. The RDL structure <NUM> may comprise dielectric layers <NUM>, traces <NUM> in the dielectric layers <NUM>, bonding pads <NUM> at an upper surface (or a substrate-side surface) of the RDL structure <NUM> for connecting with a substrate component, and re-distributed bonding pads RBP at a lower surface (or a chip-side surface) of the RDL structure <NUM> for connecting with an integrated circuit chip or die. Preferably, the dielectric layers <NUM> may comprise silicon oxide, silicon oxy-nitride, silicon nitride, and/or low-k dielectric layers, but is not limited thereto. Preferably, the RDL structure <NUM> can have a tighter RDL pitch (i.e., L/S ≤ <NUM>/<NUM>).

Preferably, a gap <NUM> is disposed between the RDL structure <NUM> and the cored substrate component <NUM>. Preferably, optionally, the gap <NUM> between the first surface S<NUM> and the RDL structure <NUM> may be filled with an underfill <NUM> and the connecting elements <NUM> are surrounded by the underfill <NUM>. The gap <NUM> may have a standoff height h<NUM> that is smaller than <NUM>. Preferably, the standoff height h<NUM> may be smaller than <NUM>. Preferably, the underfill <NUM> may comprise a non-conductive paste or a non-conductive film, but is not limited thereto.

As shown in <FIG>, a de-carrier process may be performed to detach the carrier <NUM> and a dicing process or a cutting process may be performed to singulate the individual package <NUM>'. A sidewall surface <NUM> of the RDL structure is aligned with the sidewall surface SW of the cored substrate component <NUM> along a vertical direction D<NUM>.

As shown in <FIG>, subsequently, at least one integrated circuit chip or die such as functional chips or dies <NUM> are mounted on the RDL structure <NUM> through the connecting elements <NUM> such as metal bumps, solder bumps, solder-capped metal bumps, micro-bumps, C4 bumps, metal pillars, or the like, thereby forming the semiconductor package <NUM>. The functional dies <NUM> may comprise a first die 300a and a second die 300b, for example, for each package. The first die 300a may have a function different from that of the second die 300b so as to achieve heterogeneous integration. For example, the first die 300a may be a SoC and the second die 300b may be a memory die, but is not limited thereto. It is to be understood that various functional dies such as passive components, antenna components, or the like may also be employed.

In this embodiment, a molding process is omitted. That is, the first surface S<NUM>, the second surface S<NUM>, and the sidewall surface SW of the cored substrate component <NUM> are not covered with an encapsulant. Therefore, the warpage problem of the semiconductor package <NUM> can be improved.

<FIG> is a cross-sectional diagram showing a semiconductor package without underfill according to another embodiment of the invention, wherein like layers, regions, or elements are designated by like numeral numbers or labels. As shown in <FIG>, the semiconductor package <NUM> is similar to the semiconductor package <NUM> as shown in <FIG>. The difference between the semiconductor package <NUM> and the semiconductor package <NUM> is that the semiconductor package <NUM> does not include an underfill between the RDL structure <NUM> and the cored substrate component <NUM>. That is, a gap <NUM> between the RDL structure <NUM> and the cored substrate component <NUM> is not filled with an underfill and the connecting elements <NUM> are at least partially exposed. The gap <NUM> has a standoff height h<NUM> that is smaller than <NUM>. Preferably, the standoff height h<NUM> is smaller than <NUM>.

Claim 1:
A semiconductor package (<NUM>; <NUM>), comprising:
a substrate component (<NUM>) comprising a first surface (S<NUM>), a second surface (S<NUM>) opposite to said first surface (S<NUM>), and a sidewall surface (SW) extending between said first surface (S<NUM>) and said second surface (S<NUM>);
a re-distribution layer, in the following also referred to as RDL, structure (<NUM>) disposed on said first surface (S<NUM>) and electrically connected to said first surface (S<NUM>) through first connecting elements (<NUM>) comprising solder bumps or balls;
a plurality of ball grid array, in the following also referred to as BGA, balls (<NUM>) mounted on said second surface (S<NUM>) of said substrate component (<NUM>); and
at least one integrated circuit die (<NUM>) mounted on said RDL structure (<NUM>) through second connecting elements (<NUM>);
characterized in that
a sidewall surface of said RDL structure (<NUM>) is aligned with said sidewall surface (SW) of said substrate component (<NUM>) along a vertical direction.