Patent Description:
A magnetoresistive random access memory (MRAM) is a kind of non-volatile memory that has drawn a lot of attention in this technology field recently regarding its potentials of incorporating advantages of other kinds of memories. For example, an MRAM device may have an operation speed comparable to SRAMs, the non-volatile feature and low power consumption comparable to flash, the high integrity and durability comparable to DRAM. More important, the process for forming an MRAM device may be conveniently incorporated into existing semiconductor manufacturing processes. Document <CIT> discloses a memory device with a logic area, an NVM cell area, an intermediate layer, metal features, a MIM structure, a spacer, a second stop layer, an IMD layer, a contact and a top electrode contact.

A typical MRAM cell structure usually comprises a memory stack structure comprising magnetic tunnel junction (MTJ) disposed between the lower and upper interconnecting structures. Unlike conventional memories that store data by electric charge or current flow, an MRAM cell stores data by applying external magnetic fields to control the magnetic polarity and tunneling magnetoresistance (TMR) of the MTJ.

However, the manufacturing of MRAM devices is still confronted with challenges. The memory stack structure is usually covered by an insulating layer for protection and passivation. Improper thickness of the insulating layer on the top surface of the memory stack structure may cause difficulty for forming the top vias of the upper interconnecting structure. For example, when the insulating layer on the top surface of the memory stack structure is too thick, it may cause etching stop and insufficient contacting area between the top via and the top electrode of the memory stack structure. On the other hand, when the insulating layer on the top surface of the memory stack structure is too thin, it may be insufficient to protect the top electrode from being damaged by the etching process. Both of the situations may obstruct the MRAM to.

<CIT> relates to a magnetic random access memory structure and manufacturing method thereof.

<CIT> relates to a semiconductor memory device and production method thereof. <CIT> relates to a semiconductor device that includes a first conductive wiring, at least one first dielectric layer, at least one second dielectric layer and a second conductive wiring. The at least one first dielectric layer is over the first conductive wiring. The at least one second dielectric layer is over the at least one first dielectric layer. The second conductive wiring is over the at least one second dielectric layer. The dielectric constant of the at least one second dielectric layer is higher than the dielectric constant of the at least one first dielectric layer.

In light of the above, the present invention is directed to provide a semiconductor structure and method for forming the same by which the thickness of the insulating layer on the top surface of the memory stack structure may be better controlled and the aforesaid problems caused by improper thickness of the insulating layer may be reduced.

An objective of the present invention is to provide a semiconductor structure, which includes a substrate having a substrate having a memory device region and a logic device region; a first dielectric layer on the substrate; a plurality of memory stack structures on the first dielectric layer on the memory device region; a single insulating layer continuously and conformally covering the memory stack structures and the first dielectric layer, wherein the single insulating layer directly contacts top surfaces and sidewalls of the memory stack structures, and a thickness of the single insulating layer on top surfaces of the memory stack structures is smaller than a thickness of the single insulating layer on sidewalls of the memory stack structures; a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures; a third dielectric layer on the second dielectric layer; and a plurality of top vias formed in the third dielectric layer and respectively aligned to one of the memory stack structures, wherein the top vias penetrate the insulating layer on the top surfaces of the memory stack structures to directly contacting the memory stack structures.

To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

Please refer to <FIG>, which are schematic diagrams illustrating the steps of forming a semiconductor structure according to the example. As shown in <FIG>, a substrate <NUM> having a logic device region <NUM> and a memory device region <NUM> is provided. The substrate <NUM> may include multiple layers, such as a semiconductor substrate <NUM> and an interlayer dielectric layer <NUM> on the semiconductor substrate <NUM>. The semiconductor substrate <NUM> may be a silicon substrate, a silicon-on-insulator (SOI) substrate, or a Group III-V semiconductor substrate, but not limited thereto. The substrate <NUM> may comprise semiconductor structures formed therein. For example, active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers and dielectric layers such as interlayer dielectric layers, which are not shown in the diagrams for the sake of simplification, may be formed in the substrate <NUM>. The interlayer dielectric layer <NUM> may comprise dielectric materials such as silicon oxide (SiO<NUM>) or low-k dielectric materials such as fluorinated silica glass (FSG), silicon oxycarbide (SiCOH), spin on glass, porous low-k dielectric material, organic dielectric polymers, or a combination thereof, but not limited thereto. A plurality of interconnecting structures <NUM> and <NUM> may be formed in the interlayer dielectric layer <NUM> on the logic device region <NUM> and on the memory device region <NUM>. For the sake of simplification, only one interconnecting structure <NUM> is shown in the logic device region <NUM> and only two interconnecting structures <NUM> are shown in the memory device region <NUM>. The interconnecting structure <NUM> and the interconnecting structures <NUM> may comprise metal such as tungsten (W), copper (Cu), aluminum (Al), or other suitable metals, but not limited thereto. According to an embodiment, the interconnecting structures <NUM> and <NUM> comprise copper. The logic device region <NUM> and the memory device region <NUM> may occupy different areas of the substrate <NUM>. According to an embodiment, the area of the memory device region <NUM> is smaller than the area of the logic device region <NUM>. In some cases, the area of the memory device region <NUM> may be several times smaller than the area of the logic device region <NUM>.

Please still refer to <FIG>. A first dielectric layer <NUM> is formed on the interlayer dielectric layer <NUM> and completely covers the logic device region <NUM> and the memory device region <NUM>. According to an embodiment, the first dielectric layer <NUM> may comprise multiple layers, such as an etching stop layer <NUM> and a first dielectric material layer <NUM> on the etching stop layer <NUM>. The etching stop layer <NUM> and the first dielectric material layer <NUM> may include dielectric materials. For example, the etching stop layer <NUM> may comprise silicon nitride (SiN), silicon carbon nitride (SiCN) or silicon oxynitride (SiON), or a combination thereof, but not limited thereto. The first dielectric material layer <NUM> may comprise silicon oxide (SiO<NUM>) or low-k dielectric materials, but not limited thereto. A plurality of vias <NUM> (bottom vias) are formed in the first dielectric layer <NUM> on the memory device region <NUM>. The vias <NUM> penetrate through the first dielectric material layer <NUM> and the etching stop layer <NUM> and are in direct contact with and electrically coupled to the interconnecting structures <NUM>. According to an embodiment, the vias <NUM> may comprise metal such as tungsten (W), copper (Cu), aluminum (Al), or other suitable metals, but not limited thereto. According to an embodiment, the vias <NUM> comprise copper.

Please still refer to <FIG>. A memory stack layer <NUM> is formed on the first dielectric layer <NUM> and completely covers the logic device region <NUM> and the memory device region <NUM>. According to an embodiment, the memory stack layer <NUM> may comprise multiple layers including, from bottom to top, a bottom electrode layer <NUM>, a magnetic tunneling junction (MTJ) stack layer <NUM>, a capping layer <NUM> and a top electrode layer <NUM>. The bottom electrode layer <NUM> and the top electrode layer <NUM> may comprise conductive material such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but not limited thereto. The bottom electrode layer <NUM> and the top electrode layer <NUM> may comprise the same or different conductive materials. The capping layer <NUM> may comprise metal or metal oxide, such as aluminum (Al), magnesium (Mg), tantalum (Ta), ruthenium (Ru), tungsten dioxide (WO<NUM>), nickel oxide (NiO), magnesium oxide (MgO), aluminum oxide (Al<NUM>O<NUM>), tantalum oxide (Ta<NUM>O<NUM>), molybdenum dioxide (MoO<NUM>), titanium oxide (TiO<NUM>), gadolinium oxide (GdO), or manganese oxide (MnO), or a combination thereof, but not limited thereto. The MTJ stack layer <NUM> may comprise multiple layers including, from bottom to top, a pinning layer <NUM>, a pinned layer <NUM>, a tunneling layer <NUM> and a free layer <NUM>. The pinning layer <NUM> may comprise anti-ferromagnetic (AFM) material such as PtMn, IrMn, PtIr or the like, but not limited thereto. The pinning layer <NUM> is used to pin or fix nearby ferromagnetic layers to a particular magnetic polarity. The pinned layer <NUM> and the free layer <NUM> respectively comprise the same or different ferromagnetic material such as Fe, Co, Ni, FeNi, FeCo, CoNi, FeB, FePt, FePd, CoFeB, or the like. The magnetic polarity of the pinned layer <NUM> is pinned (anti-ferromagnetic coupled) by the pinning layer <NUM>, while the magnetic polarity of the free layer <NUM> may be changed by an external magnetic field. The tunneling layer <NUM> is sandwiched between the pinned layer <NUM> and the free layer <NUM> and may comprise insulating material such as MgO, Al<NUM>O<NUM>, NiO, GdO, Ta<NUM>O<NUM>, MoO<NUM>, TiO<NUM>, tungsten oxide (WO<NUM>), or a combination thereof, but not limited thereto. The pinning layer <NUM>, the pinned layer <NUM>, the tunneling layer <NUM> and the free layer <NUM> may respectively comprise single or multiple layers having a thickness ranges from several angstroms to dozens of nanometers.

Please refer to <FIG>. Subsequently, a patterning process is performed to pattern the memory stack layer <NUM> to form a plurality of memory stack structures <NUM> on the memory device region <NUM> and remove the memory stack layer <NUM> on the logic device region <NUM>. For the sake of simplification, only two memory stack structures <NUM> are shown in the memory device region <NUM>. According to an embodiment, the patterning process may include the following steps. First, a patterned hard mask layer (not shown), such as a patterned silicon oxide layer or a patterned silicon nitride layer, is formed on the top electrode layer <NUM>. A first stage of etching, such as a reactive ion etching (RIE) process, using the patterned hard mask layer as an etching mask is performed to etch the top electrode layer <NUM>, thereby transferring the pattern of the patterned hard mask layer to the top electrode layer <NUM>. Afterward, a second stage of etching, such as an ion beam etching (IBE) process, using the patterned top electrode layer <NUM> as an etching mask is performed to etch the capping layer <NUM>, the MTJ stack layer <NUM> and the bottom electrode layer <NUM>, thereby transferring the pattern of the patterned top electrode layer <NUM> to the capping layer <NUM>, the MTJ stack layer <NUM> and the bottom electrode layer <NUM> and the memory stack structures <NUM> as shown in <FIG> are obtained. According to an embodiment, the first dielectric material layer <NUM> exposed from the memory stack structures <NUM> on the memory device region <NUM> and the first dielectric material layer <NUM> on the logic device region <NUM> may be over-etched by the second stage of etching (the IBE process) to ensure unnecessary memory stack layer <NUM> being removed. Accordingly, the first dielectric material layer <NUM> may have a recessed top surface 204a.

Please still refer to <FIG>. Subsequently, an insulating layer <NUM> is formed on the substrate <NUM> and conformally covers top surfaces 330a and sidewalls 330b of the memory stack structures <NUM> and the recessed top surface 204a of the first dielectric layer <NUM>. The insulating layer <NUM> may comprise insulating material such as silicon nitride (SiN), silicon carbon nitride (SiCN) or silicon oxynitride (SiON) and may be formed by chemical vapor deposition (CVD) process, but not limited thereto. According to an embodiment, the insulating layer <NUM> is formed in-situ after the second stage of etching, i.e. the IBE process to prevent the exposed sidewalls 330b of the memory stack structures <NUM> from being oxidized or absorbing contamination. As shown in <FIG>, the portion of the insulating layer <NUM> covering the recessed top surface 204a of the first dielectric layer <NUM> has a first thickness T1. The portion of the insulating layer <NUM> covering the top surfaces 330a of the memory stack structures <NUM> has a second thickness T2. The portion of the insulating layer <NUM> covering the sidewalls 330b of the memory stack structures <NUM> has a third thickness T3. According to an embodiment, the first thickness T1 and the second thickness T2 are approximately the same. The third thickness T3 is smaller than the first thickness T1 and the second thickness T2. The third thickness T3 may be about <NUM>% to <NUM>% of the first thickness T1 or the second thickness T2. According to an embodiment, the first thickness T1, the second thickness T2 and the third thickness T3 may range from <NUM>Å to <NUM>Å, but not limited thereto.

Please refer to <FIG>. Subsequently, an anisotropic etching back process E1, such as a reactive ion etching (RIE) process, is performed to remove a portion of the insulating layer <NUM>. None of the memory stack structures <NUM> and the first dielectric material layer <NUM> is exposed from the insulating layer <NUM> after the etching back process E1. The removal amount of the insulating layer <NUM> on the recessed top surface 204a of the first dielectric layer <NUM> and on the top surfaces 330a of the memory stack structures <NUM> is larger than the removal amount of the insulating layer <NUM> on the sidewalls 330b of the memory stack structures <NUM> during the etching back process E1. As shown in <FIG>, after the etching back process E1, the portion of the insulating layer <NUM> covering the recessed top surface 204a of the first dielectric layer <NUM> has a fourth thickness T4. The portion of the insulating layer <NUM> covering the top surfaces 330a of the memory stack structures <NUM> has a fifth thickness T5. The portion of the insulating layer <NUM> covering the sidewalls 330b of the memory stack structures <NUM> has a sixth thickness T6. Preferably, the fourth thickness T4 and the fifth thickness T5 are approximately the same, and the sixth thickness T6 is larger than the fourth thickness T4 and the fifth thickness T5. According to an embodiment, the fourth thickness T4 and the fifth thickness T5 may range from <NUM>Å to <NUM>Å, and the sixth thickness T6 approximately equals to or is smaller than the third thickness T3 and may range from <NUM>Å to <NUM>Å.

Please refer to <FIG>. A second dielectric layer <NUM>, such as a low-k dielectric layer, is then formed on the insulating layer <NUM>, completely covers the logic device region <NUM> and the memory device region <NUM> and fills the spaces between the memory stack structures <NUM>. The memory stack structures <NUM> are completely covered by the insulating layer <NUM> and are not in direct contact with the second dielectric layer <NUM>. Subsequently, the second dielectric layer <NUM> is subjected to a planarization process, such as a first chemical mechanical process P1 until a planar top surface of the second dielectric layer <NUM> is obtained which does not expose any portion of the insulating layer <NUM>. According to an embodiment, the first chemical mechanical process P1 uses polishing slurries in preference for removing the second dielectric layer <NUM> and may have a removal rate for the second dielectric layer <NUM> approximately between <NUM> to <NUM> angstroms per second (Å/s). As shown in <FIG>, after the first chemical mechanical process P1, the second dielectric layer <NUM> directly over the top surfaces 330a of the memory stack structures <NUM> has a seventh thickness T7. According to an embodiment, the seventh thickness T7 may range from <NUM>Å to <NUM>Å. The insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM> is not exposed to the first chemical mechanical process P1 and therefore still has the fifth thickness T5.

Please refer to <FIG>. After planarizing the second dielectric layer <NUM>, a patterning process is performed to define an opening <NUM> in the second dielectric layer <NUM> on the logic device region <NUM>. A conductive material <NUM> is then formed on the second dielectric layer <NUM> to fill up the opening <NUM>. According to an embodiment, the opening <NUM> may include a via hole 503a in the lower portion and a trench 503b in the upper portion of the opening <NUM>, wherein the via hole 503a and the trench 503b are connected to each other and penetrate the second dielectric layer <NUM>, the insulating layer <NUM>, the first dielectric material layer <NUM> and the etching stop layer <NUM> to expose the interconnecting structure <NUM> in the logic device region <NUM> of the substrate <NUM>. The conductive material <NUM> may comprise metal such as tungsten (W), copper (Cu), aluminum (Al), or other suitable metals, but not limited thereto. According to an embodiment, the conductive material <NUM> comprises copper.

Please refer to <FIG>. Following, a second chemical mechanical process P2 is performed to remove the conductive material <NUM> outside the opening <NUM> thereby forming an interconnecting structure <NUM> in the opening <NUM>. The interconnecting structure <NUM> comprises a via portion 504a in the via hole 503a and a wiring portion 504b in the trench 503b. The bottom of the via portion 504a is in direct contact and electrically coupled to the interconnecting structure <NUM> in the substrate <NUM>. The top surface of the wiring portion 504b is exposed from the second dielectric layer <NUM> for being electrically coupled to the interconnecting structure <NUM> (shown in <FIG>) formed in later processes. In the embodiment, the second chemical mechanical process P2 may remove a portion of the second dielectric layer <NUM> but not expose the insulating layer <NUM> to ensure unnecessary conductive material <NUM> outside the opening <NUM> being completely removed. As shown in <FIG>, after the second chemical mechanical process P2, the second dielectric layer <NUM> directly over the top surfaces 330a of the memory stack structures <NUM> has an eighth thickness T8. The eighth thickness T8 is smaller than the seventh thickness T7 and may range between <NUM>Å to 200Å.

Please refer to <FIG>. Following, a third dielectric layer <NUM> is formed on the second dielectric layer <NUM> and completely covering the logic device region <NUM> and the memory device region <NUM>. The interconnecting structure <NUM> and interconnecting structures <NUM> are then formed respectively in the third dielectric layer <NUM> on the logic device region <NUM> and the memory device region <NUM>. According to an embodiment, the third dielectric layer <NUM> may comprise multiple layers, such as an etching stop layer <NUM> and a third dielectric material layer <NUM> on the etching stop layer <NUM>. The etching stop layer <NUM> may include dielectric materials such as silicon nitride (SiN), silicon carbon nitride (SiCN) or silicon oxynitride (SiON), or a combination thereof, but not limited thereto. The third dielectric material layer <NUM> may include dielectric materials such as silicon oxide (SiO<NUM>) or low-k dielectric materials. According to an embodiment, the etching stop layer <NUM> and the etching stop layer <NUM> may comprise the same material, such as silicon carbon nitride (SiCN); the third dielectric material layer <NUM>, the second dielectric layer <NUM> and the interlayer dielectric layer <NUM> may comprise the same material, such as low-k dielectric material; the first dielectric material layer <NUM> may comprise silicon oxide (SiO<NUM>).

The interconnecting structures <NUM> and <NUM> may be made by similar processes for forming the interconnecting structure <NUM> as previously illustrated and would not be repeated. According to an embodiment, the interconnecting structure <NUM> in the logic device region <NUM> may comprise a lower via portion 604a and an upper wiring portion 604b connecting the via portion 604a, wherein the bottom of the via portion 604a directly contacts and is electrically coupled to the wiring portion 504b of the interconnecting structure <NUM>, and the top surface of the wiring portion 604b is exposed from the third dielectric material layer <NUM> for further electrical interconnection. The interconnecting structures <NUM> in the memory device region <NUM> may respectively comprise a lower via portion 606a and an upper wiring portion 606b on the via portion 606a and connecting to the via portion 606a, wherein the via portion 606a (also referred as top via) is aligned to one of the memory stack structures <NUM> and penetrates through the second dielectric layer <NUM> and the insulating layer <NUM> on the top surface 330a of the memory stack structure <NUM> to electrically connect to the top electrode <NUM>. The wiring portion 606b is exposed from the third dielectric material layer <NUM> for further electrical connection.

As previously illustrated, the first chemical mechanical process P1 does not expose and remove any portion of the insulating layer <NUM> and the portion of the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM> still has the fifth thickness T5 which may be better-controlled to have desired thickness and uniformity by the deposition process of the insulating layer <NUM> and the following etching back process E1. The degradation of thickness uniformity of the insulating layer <NUM> caused by loading effect of the first chemical mechanical process P1 may be avoided. In this way, it may be better guaranteed that the etching process for defining the via holes (not shown) of the via portions 606a of the interconnecting structures <NUM> may etch through the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM>. Problems of etching stop or damages due to thickness variation of the insulating layer <NUM> may be reduced.

Please refer to <FIG> and <FIG>, which are schematic diagrams illustrating a modification of the example as shown in <FIG>. As shown in <FIG>, after the etching back process E1 illustrated in <FIG>, a patterned photoresist layer (not shown) may be formed on the substrate <NUM> to cover the memory device region <NUM>. Afterward, using the patterned photoresist layer as an etching mask, the insulating layer <NUM> and the first dielectric material layer <NUM> on the logic device region <NUM> are removed and the etching stop layer <NUM> on the logic device region <NUM> is exposed. Following, process steps as illustrated in <FIG> are performed, including forming the second dielectric layer <NUM>, performing the first chemical mechanical process P1, forming the interconnecting structure <NUM>, forming the third dielectric layer <NUM> and forming the interconnecting structures <NUM> and <NUM>, thereby obtaining the structure as shown in <FIG>. In the modification, the second dielectric layer <NUM> is in direct contact with the etching stop layer <NUM> on the logic device region <NUM>. By selectively removing the insulating layer <NUM> and the first dielectric material layer <NUM> that may have materials different from the material of the second dielectric layer <NUM>, the etching process for defining the opening <NUM> of the interconnecting structure <NUM> may be facilitated. As shown in <FIG>, in the modification, the via portions 606a of the interconnecting structures <NUM> penetrates through the second dielectric layer <NUM> and the insulating layer <NUM> on the top surface 330a of one of the memory stack structure <NUM> to electrically connect to the top electrode <NUM> of memory stack structure <NUM>.

Please refer to <FIG> and <FIG>, which are schematic diagrams illustrating the steps of forming a semiconductor structure according to an embodiment of the present invention. The step shown in <FIG> corresponds to the step shown in <FIG>. The step shown in <FIG> corresponds to the step shown in <FIG>. Details of the steps shown in <FIG> have been illustrated previously and would not be repeated herein. The major difference between the example and the embodiment is that, as shown in <FIG>, after the second chemical mechanical process P2, the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM> is exposed and has a ninth thickness T9. Because the second chemical mechanical process P2 uses polishing slurries in preference for removing metals, i.e. the conductive material <NUM> rather than removing dielectric materials, it may have slower removal rate and smaller loading effect for the insulating layer <NUM> with respect to the removal rate for the insulating layer <NUM> by the first chemical mechanical process P1. For example, the first chemical mechanical process P1 may have a removal rate between 45Å/s and 65Å/s for the insulating layer <NUM>. The second chemical mechanical process P2 may have a removal rate between 10Å/s and 20Å/s for the insulating layer <NUM>. Accordingly, in the second embodiment, although the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM> is exposed to the second chemical mechanical process P2, the uniformity of the insulating layer <NUM> may be maintained without being degraded by the second chemical mechanical process P2. According to an embodiment, the ninth thickness T9 approximately equals to or is smaller than the fifth thickness T5. For example, the ninth thickness T9 may range from <NUM>Å to <NUM>Å. After the second chemical mechanical process P2,as shown in <FIG>, a third dielectric layer <NUM> is formed on the second dielectric layer <NUM> and the interconnecting structures <NUM> and <NUM> are formed in the third dielectric layer <NUM> on the logic device region <NUM> and the memory device region <NUM>, respectively. In the second embodiment, the etching stop layer <NUM> is in direct contact with the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM>. The via portions 606a of the interconnecting structures <NUM> are respectively aligned to one of the memory stack structures <NUM> and penetrate through the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM> to electrically connect to the top electrodes <NUM> of memory stack structures <NUM>.

Please refer to <FIG>, which is a schematic diagram illustrating a modification of the embodiment. As shown in <FIG>, after the etching back process E1 as illustrated in <FIG>, the insulating layer <NUM> and the first dielectric material layer <NUM> on the logic device region <NUM> are selectively removed and the etching stop layer <NUM> on the logic device region <NUM> is exposed. Process steps as illustrated in <FIG>, <FIG> and <FIG> are then performed, including forming the second dielectric layer <NUM>, performing the first chemical mechanical process P1, forming the interconnecting structure <NUM>, forming the third dielectric layer <NUM> and forming the interconnecting structures <NUM> and <NUM>, thereby obtaining the structure as shown in <FIG>. The etching stop layer <NUM> is in direct contact with the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM>. The via portions 606a of each interconnecting structures <NUM> are respectively aligned to one of the memory stack structures <NUM> and penetrate through the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM> to electrically connect to the top electrodes <NUM> of memory stack structures <NUM>.

One feature of the method provided by the present invention is that the first chemical mechanical process P1 stops on the second dielectric layer <NUM> without exposing any portion of the insulating layer <NUM>. The insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM> remains the fifth thickness T5 which may be better-controlled to have desired thickness and uniformity by the deposition process of the insulating layer <NUM> and the following etching back process E1. In this way, it may be better guaranteed that the etching process for forming the via portions 606a of the interconnecting structures <NUM> may etch through the insulating layer <NUM> on the top surfaces 330a of the memory stack structures <NUM>. Etching stop or damages due to thickness variation of the insulating layer <NUM> may be reduced and the quality of the electrical connections between the via portions 606a and the top electrodes <NUM> of the memory stack structures <NUM> may be improved.

Claim 1:
A semiconductor structure, comprising:
a substrate (<NUM>) having a memory device region (<NUM>) and a logic device region (<NUM>);
a first dielectric layer (<NUM>) on the substrate (<NUM>);
a plurality of memory stack structures (<NUM>) on the first dielectric layer (<NUM>) on the memory device region (<NUM>);
a single insulating layer (<NUM>) continuously and conformally covering the memory stack structures (<NUM>) and the first dielectric layer (<NUM>), wherein the single insulating layer (<NUM>) directly contacts top surfaces (330a) and sidewalls (330b) of the memory stack structures (<NUM>), and a thickness (T5) of the single insulating layer (<NUM>) on top surfaces (330a) of the memory stack structures (<NUM>) is smaller than a thickness (T6) of the single insulating layer (<NUM>) on sidewalls (330b) of the memory stack structures (<NUM>);
a second dielectric layer (<NUM>) on the insulating layer (<NUM>) and completely filling the spaces between the memory stack structures (<NUM>);
an interconnecting structure formed in the second dielectric layer (<NUM>) on the logic device region (<NUM>),
wherein a top surface of the second dielectric layer (<NUM>) on the memory device region (<NUM>) and the logic region (<NUM>) are coplanar,
wherein the top surface of the second dielectric layer (<NUM>) is flush with a top surface of the interconnecting structure (<NUM>) and a top surface of the insulating layer (<NUM>), and the top surface of the interconnecting structure (<NUM>) is higher than top surfaces of the memory stack structures (<NUM>).