Patent Description:
Time-of-flight systems are used to measure distance to a target. There are two general classifications of time-of-flight systems, namely direct and indirect. As an example, with direct time-of-flight systems, an emitter such as a laser diode (typically infrared) is driven with a pulsed drive current to cause it to emit a short laser pulse in a given direction. This laser pulse is reflected by an object present in that given direction, and a receiver with a detector receives and senses the reflected laser pulse. The receiver, with a proper timing reference, measures the elapsed time between emitting of the laser pulse and receipt of the reflected laser pulse. From this elapsed time, the distance to the object can be evaluated. Through the use of an array of receiving elements in the receiver, a three-dimensional map of the object can therefore be formed. This three-dimensional map of the object may be a map of a human face, for example, and may be used to identify authorized users of an electronic device such as a smartphone or tablet into which the time-of-flight system is incorporated.

<CIT> relates to a reconfigurable topology for switching and charge pump negative polarity regulators.

<CIT> relates to a wireless power receiver configurable for LDO or buck operation.

<CIT> relates to an integrated circuit with configurable control and power switches.

A sample known receiver <NUM> for use in a time-of-flight (TOF) system <NUM> is shown in <FIG> and includes a single photon avalanche diode (SPAD) <NUM> having its cathode coupled to a high voltage VHV generated by high voltage (HV) generation circuitry <NUM> and its anode coupled to ground through a quench resistor <NUM>. The high voltage VHV biases the SPAD <NUM> above its breakdown voltage. When the SPAD <NUM> is struck by an incoming photon, an output pulse is sourced from the anode of the SPAD <NUM>, which may then be detected by a readout amplifier <NUM> and interpreted to provide detection data for use in calculating time-of-flight.

The higher a SPAD is biased above its breakdown voltage, the more photosensitive the SPAD becomes in operation; the breakdown voltage of a SPAD increases as the temperature of the SPAD increases. Therefore, it is desirable for the high voltage generation circuit <NUM> to regulate the high voltage VHV over temperature so that the differential between VHV and the breakdown voltage of the SPAD remains the same over temperature change, thereby maintaining the desired level of photosensitivity of the SPAD.

A sample real world implementation of the time-of-flight system <NUM> is now described with reference to <FIG>. The TOF system <NUM> includes the high voltage generation circuitry <NUM> and a package <NUM>, with a flex section <NUM> (i.e. flexible substrate) carrying the electrical connections therebetween.

The HV generation circuitry <NUM> includes a boost converter <NUM> that alternatingly creates a connection that transfers energy from the battery VBAT to an inductor L and disrupts that connection to thereby create a ripple current that is used to generate the high voltage (VHV). In particular, a boost circuit <NUM> within the boost converter <NUM> includes the components that facilitate the selective alternating connection between the inductor L and ground, and a boost controller <NUM> controls the boost circuit <NUM> to perform this operation to thereby generate VHV. When enabled by an enable signal EN received from the package <NUM>, the boost controller <NUM> generates a pulse width modulation (PWM) signal that controls the boost circuit <NUM> so as to cause generation and regulation of the high voltage VHV at a level set by an adjustment signal ADJ received from the package <NUM>, with the boost controller <NUM> receiving a feedback signal FBK from the boost circuit <NUM> during operation.

The package <NUM> includes a system-on-a-chip (SOC) <NUM> that generates the enable signal EN and the adjustment signal ADJ, one or more single photon avalanche diodes (SPADs) <NUM>, and time-of-flight circuitry that generates time-of-flight data based upon output from the SPADs <NUM>.

This TOF system <NUM> of <FIG> is effective at performing desired functionality. However, the high voltage generation circuitry <NUM> being external to the package <NUM> means that the TOF system <NUM> occupies more space than desired, and in certain applications, space is at a premium. Still further, the TOF system <NUM> may be relatively costly to manufacture due to the high voltage generation circuitry <NUM> being external to the package <NUM>.

To address this, in another sample real world implementation of the time-of-flight system <NUM>' shown in <FIG>, the boost controller <NUM> is incorporated within the SOC <NUM>', with the boost circuit <NUM> and inductor L being incorporated within the package <NUM>'. This provides for a TOF system <NUM>' within a single package <NUM>', saving space and cost.

Consider now though that the SOC <NUM>' of the implementation of <FIG> is different than the SOC <NUM> of the implementation of <FIG>. This means that if a manufacturer of the SOC <NUM> intends on supporting both implementations, it manufactures two separate SOCs, one for each implementation. This is inefficient, as two production lines are utilized, driving up the overall cost of the SOCs. This also adds to the complexity of the manufacturer needing to accurately estimate the proper amount of each different SOC to manufacture. Given this, it would be highly desirable if a manufacturer could manufacture a single SOC that supports both implementations described above. As such, further development remains necessary.

The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the invention as defined in the appended claims.

Do note that in the below description, any described resistor or resistance is a discrete device unless the contrary is stated, and is not simply an electrical lead between two points. Thus, any described resistor or resistance coupled between two points has a greater resistance than a lead between those two points would have, and such resistor or resistance cannot be interpreted to be a lead. Similarly, any described capacitor or capacitance is a discrete device unless the contrary is stated, and is not a parasitic unless the contrary is stated. Moreover, any described inductor or inductance is a discrete device unless the contrary is stated, and is not a parasitic unless the contrary is stated.

Disclosed herein is a system-on-a-chip (SOC) <NUM> that includes a reconfigurable high voltage (VHV) controller <NUM> that enables the SOC <NUM> to be used with either external high voltage generation circuitry <NUM> (<FIG>) or high voltage generation circuitry <NUM>' integrated together with the SOC <NUM> into a single package <NUM>' (<FIG>), to form a time-of-flight system <NUM>. Specifics of the SOC <NUM> will be given in detail below, however, first, specific details of the embodiments of <FIG> will be given so that the full system functionality provided by the SOC <NUM> can be appreciated.

Referring now to <FIG>, the high voltage generation circuitry <NUM> includes the inductor L having a first terminal connected to the battery voltage VBAT and a second terminal connected to the DC-DC boost converter <NUM>. The high voltage VHV is generated at the output of the DC-DC boost converter <NUM>. Feedback resistors Rb1, Rb2 are connected in series between the output of the DC-DC boost converter <NUM> and ground to form a voltage divider circuit, with a feedback voltage VFB is generated at the tap node Nfb of the voltage divider circuit between the feedback resistors Rb1, Rb2.

The DC-DC boost converter <NUM> includes a boost circuit <NUM> and a boost controller <NUM>. The boost circuit <NUM> is comprised of a switch (illustratively the n-channel transistor MN) connected between the second terminal of the inductor L and ground, and controlled by the PWM signal from the boost controller <NUM>. The boost circuit <NUM> further includes a boost diode Db having an anode connected to the second terminal of the inductor L and a cathode connected to the output of the DC-DC boost converter <NUM>, and a boost capacitor Cb connected between the output of the DC-DC boost converter <NUM> and ground.

When enabled by assertion of enable signal EN by the reconfigurable VHV controller <NUM> of the SOC <NUM>, the boost circuit <NUM> operates to generate the high voltage VHV as being higher than the battery voltage VBAT. The high voltage VHV is generated across the capacitor Cb. In particular, when switch MN is closed by the assertion of the PWM signal by the boost controller <NUM>, current flows from the battery VBAT into the inductor L, generating a magnetic field and thereby storing energy in the inductor L. At this point, the first terminal of the inductor L is positive with respect to the second terminal of the inductor L. When the switch MN is opened by the deassertion of the PWM signal by the boost controller <NUM>, the sudden drop in current through the inductor L causes generation of a back-EMF opposite in polarity to the voltage across the inductor L to keep the current flowing. This results in two voltages, the battery voltage VBAT and the back EMF voltage across L1, in series with one another. This higher voltage, due to the lack of a current path through the switch MN, forward biases the diode Db, and the resulting current flow charges Cb to VHV (i.e. VBAT+VL minus the forward voltage drop across Db).

During this operation, the boost controller <NUM> operates the boost circuit <NUM> to regulate VHV such that the feedback voltage VFB remains equal to a reference voltage. A current IDAC is sourced by the reconfigurable VHV controller <NUM> to the tap Nfb between the feedback resistors Rb1 and Rb2, and is used by the reconfigurable VHV controller <NUM> to set the level of VHV. By sourcing the current IDAC to the tap Nfb between resistors Rb1 and Rb2, the feedback voltage VFB increases. This has the effect of causing the boost controller <NUM> to reduce VHV to thereby lower VFB to be equal to the reference voltage. Therefore, through the changing of the magnitude of the current IDAC, as well as the setting of the resistance values of the resistors Rb1 and Rb2, the voltage VHV can be set to a desired level.

Referring now to <FIG>, the boost circuit <NUM> remains the same as in <FIG>, while the functionality of the boost controller (as well as the circuitry generating the feedback voltage) is performed by the reconfigurable VHV controller <NUM> of the SOC <NUM>. Operation remains the same, keeping in mind that the functionality of the boost controller and circuitry generating the feedback voltage is, as stated, performed by the configurable VHV controller <NUM>. Further details of the implementation of the boost controller and feedback circuitry into a single package with the SOC <NUM> may be found in <CIT>, which was commonly owned at the time of conception as the invention of the instant disclosure and remains commonly owned at the time of filing of the instant disclosure.

The SOC <NUM> is now described with reference to <FIG>. The SOC <NUM> includes a bandgap reference generator <NUM> that generates a bandgap voltage VREF (e.g., a temperature independent reference voltage) and a reference current Iref (e.g., a temperature independent reference current). A first switch S1, under control of an external operation mode signal EN_EXT_VHV, selectively couples the reference current Iref to the input of a current DAC <NUM> (e.g., a programmable current generator). A second switch S2, under control of an internal operation mode signal EN_INT_VHV, selectively couples the output of a matching block <NUM> to the input of the current DAC <NUM>. The current DAC <NUM> generates a current IDAC at its output. A third switch S3, under control of the internal operation mode signal EN_INT_VHV, selectively couples the reference voltage VREF to the input of the matching block <NUM>. A fourth switch S4, under control of the internal operation mode signal EN_INT_VHV, selectively couples the current IDAC to an input of the overvoltage/undervoltage detection circuit <NUM>. A fifth switch S5, under control of the external operation mode signal EN_EXT_VHV, selectively couples the current IDAC to a pad PAD1.

A pulse width modulation (PWM) feedback controller <NUM> has an input connected to a resistive ladder within the overvoltage/undervoltage detection circuit <NUM> to receive a feedback signal VFB1. The PWM feedback controller <NUM> also receives as input the reference voltage VREF, as well as the internal operation mode signal EN_INT_VHV, and generates a PWM command voltage PWM_CMD as output. A multiplexer <NUM> selectively passes either the PWM command voltage PWM_CMD or a boost enable signal BOOST_EN as its output to a pad PAD2, under control of an INT/EXT selection signal.

A sixth switch S6, under control of the internal operation mode signal EN_INT_VHV, selectively connects the pad PAD1 to the output of the PWM feedback controller <NUM>.

An array of SPADs <NUM> is connected to a pad PAD3 and receives the high voltage VHV. The overvoltage/undervoltage detection circuit <NUM> receives the high voltage VHV as input and generates a detection signal OV or UV, and its ladder generates the feedback voltage VFB1 as output.

A control circuit <NUM> generates the INT/EXT selection signal, as well as the internal operation mode signal EN_INT_VHV, the external operation mode signal EN_EXT_VHV, a boost enable signal BOOST_EN, and a SET signal. The SET signal is received by the current DAC <NUM>, and the magnitude of the current IDAC is set by the current DAC <NUM> based upon the SET signal. Keeping in mind the above description of the magnitude of the current IDAC setting the voltage VHV, it should be appreciated that the SET signal may be continuously changed by the control circuitry <NUM> during operation to dynamically change VHV as the temperature of the SOC <NUM> changes.

The switches S1, S2, S3, S4, S5, S6 described above may be implemented as standard transmission gates.

The overvoltage/undervoltage detection circuit <NUM> is now described in detail with additional reference to <FIG>. The overvoltage/undervoltage detection circuit <NUM> includes a ladder formed by resistors R1, R2, R3, R4, R5 connected in series between the high voltage VHV and ground. The tap between resistors R2, R3 is connected to switch S4. A feedback voltage VFB1 is produced tap between resistors R3, R4.

A comparator 104a has a non-inverting input terminal connected to receiver a lower threshold voltage VREF_UV and an inverting input terminal connected to the tap between resistors R2, R3, with an undervoltage signal UV being generated at the output terminal of the comparator 104a. A comparator 104c has an inverting input terminal connected to receive an upper threshold voltage VREF_OV and a non-inverting input terminal connected to the tap between resistors R4, R5, with an overvoltage signal OV being generated at the output terminal of the comparator 104c. A comparator 104b has a non-inverting input terminal connected to a sawtooth reference PWM signal VREF_PWM (having a frequency equal to the switching frequency of the boost circuit <NUM>) and an inverting input terminal connected to the tap between resistors R3, R4 to receive the feedback voltage VFB1, with the PWM comparison signal PWM_CP being generated at the output terminal of the comparator 104b.

In operation, the overvoltage/undervoltage detection circuit <NUM> serves to detect whether the high voltage VHV either exceeds an upper threshold VREF_OV (e.g., indicating whether an overvoltage condition is present) and falls below a lower threshold VREF_UV (e.g., indicating whether an undervoltage condition is present). Referring to <FIG>, when the voltage at the tap between nodes R4, R5 exceeds the upper threshold VREF_OV, the comparator 104c asserts its output, thereby asserting the overvoltage signal OV to indicate the overvoltage condition; conversely, when the voltage at the tap between the nodes R2, R3 falls below the lower threshold VREF_UV, the comparator 104a asserts its output, thereby asserting the undervoltage signal UV to indicate the undervoltage condition. Assertion of either OV or UV may be an indication of malfunction, indicating that the control circuit <NUM> is to cease operation of the boost circuit <NUM>.

As explained, the SOC <NUM> may be operated in either an external generation mode (<FIG>) or an in-package generation mode (<FIG>), permitting the same SOC <NUM> to be universal to the two different configurations.

The external generation mode will now be described with additional reference to <FIG>. In the external generation mode, the high voltage generation circuitry <NUM> is located externally to the package <NUM> (in which the SOC <NUM> resides). To begin the external generation mode, the control circuitry <NUM> sets the INT/EXT selection signal at the appropriate logic level so as to select the external generation mode, asserts the external operation mode signal EN_EXT_VHV signal, and deasserts the internal operation mode signal EN_INT_VHV, while asserting the boost enable signal BOOST_EN to activate the boost converter <NUM>. Still further, the control circuitry <NUM> generates the SET signal to have a digital value that sets the magnitude of the current IDAC to a level that sets the high voltage VHV to a desired level.

This output by the control circuitry <NUM> has the effect of closing switches S1 and S5, while opening switches S2, S3, and S4. As a result, the bandgap reference generator <NUM> provides the temperature independent reference current Iref to the current DAC <NUM>, which generates the current IDAC therefrom. The current IDAC is sourced to the tap Nfb between the resistors Rb1, Rb2 (which here may be high precision resistors, varying by <NUM>% or so) and, as explained in detail, ultimately serves to set the level of the high voltage VHV. The INT/EXT selection signal being at the logic level to select the external generation mode causes the multiplexer <NUM> to output the enable signal EN to the pad PAD2.

As a result, the boost converter <NUM> operates as described above to generate the high voltage VHV at the pad Pad3, with VHV being used to bias the SPAD array <NUM> in performing time-of-flight operations.

The internal generation mode will now be described with additional reference to <FIG>.

In the internal generation mode, the high voltage generation circuitry <NUM>' is located internally to the package <NUM>' (in which the SOC <NUM> resides). To begin the internal generation mode, the control circuitry <NUM> sets the INT/EXT selection signal at the appropriate logic level so as to select the internal generation mode, asserts the internal operation mode signal EN_IN_VHV signal, and deasserts the external operation mode signal EN_EXT_VHV, while deasserting the boost enable signal BOOST_EN. Still further, the control circuitry <NUM> generates the SET signal to have a digital value that sets the magnitude of the current IDAC to a level that sets the high voltage VHV to a desired level.

This output by the control circuitry <NUM> has the effect of closing switches S3, S4, and S6, while opening switches S1 and S5. As a result, the bandgap reference generator <NUM> provides the temperature independent reference voltage Vref to the matching block <NUM>, which generates a matched input current Iref_match for use by the current IDAC <NUM> in generating the current IDAC, which as explained in detail, ultimately serves to set the level of the high voltage VHV.

The resistance values of the resistors, R1, R2, R3, R4, R5 are matched (but not necessarily equal in absolute value), but in reality may vary by up to <NUM>% or so because they are not high-precision. Therefore, the matching block <NUM> includes a resistor R6 that has a resistance value equal to the combined resistance values of R1, R2, R3, R4, R5. As shown in <FIG>, the matching block <NUM> includes an amplifier 123a in a unity gain configuration receiving the temperature independent reference voltage VREF at its non-inverting input terminal, and providing its output to resistor R6, with a matched reference current Iref_match therefore flowing through resistor R6. The use of the resistor R6 being matched in resistance to the combined resistance of R1, R2, R3, R4, R5 and being formed by the same process as R6 provides for the matched reference current Iref_match, providing for the generation of IDAC and therefore VHV as being independent of process corner and stable over temperature. To state it differently, Iref_match will vary as the resistances of R1, R2, R3, R4, R5 vary.

The current IDAC is sourced to the tap between the resistors R2, R3 of the overvoltage/undervoltage detection circuit <NUM>, and the feedback voltage VFB1 is generated at the tap between the resistors R3, R4 - appreciate here, therefore, that the ladder formed by resistors R1, R2, R3, R4, R5 is acting as the feedback ladder for the generation and regulation of the high voltage VHV, as well as for overvoltage/undervoltage condition determination. The INT/EXT selection signal being at the logic level to select the internal generation mode causes the multiplexer <NUM> to output the PWM command signal PWM_CMD to the pad Pad2 for use by the boost circuit <NUM> as the PWM signal.

The PWM feedback controller <NUM> acts as the boost controller described above, adjusting the generation of PWM_CMD (and therefore PWM) to operate the boost circuit <NUM> such that the feedback voltage VFB1 matches the reference voltage VREF. Notice that in this internal generation mode, the PWM signal is provided at both Pad1 as well as at Pad2, and both pads are used to drive the boost circuit <NUM>. This is because the transistor within the boost circuit <NUM> is a large component, and the driving thereof involves a large drive strength.

As explained, the SOC <NUM> design permits use with either external high voltage generation circuitry <NUM> (<FIG>) or high voltage generation circuitry <NUM>' integrated together with the SOC <NUM> into a single package <NUM>' (<FIG>), keeping cost down as one production line and one SKU can service both configurations. The SOC <NUM> design also keeps the amount of space occupied by unused components of the SOC <NUM> to a small amount, as the highest area consuming components (the current DAC <NUM>, voltage ladder R1-R5, and comparators 104a-104c) are used in both configurations.

It is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of this disclosure, as defined in the annexed claims. based upon the feedback voltage; and.

Claim 1:
An electronic device comprising a system-on-a-chip , SOC, within a package, the SOC having, formed therein, at least:
a reference generator (<NUM>);
a matching circuit (<NUM>);
a programmable current generator (<NUM>) configured to generate a programmed current;
a pulse width modulation controller (<NUM>);
an overvoltage/undervoltage detection circuit (<NUM>) configured to receive a high voltage from a third output pad (Pad3);
a multiplexer (<NUM>) configured to selectively pass an input signal to a second output pad (Pad2); at least one single photon avalanche diode, SPAD, having an anode coupled to receive the high voltage; and
switching circuitry (S1, S2, S3, S4, S5, S6); wherein the switching circuitry is configured to, in an internal generation mode:
connect an output of the reference generator to the matching circuit such that the matching circuit receives a temperature independent reference voltage generated by the reference generator in the internal generation mode;
connect an output of the matching circuit to the programmable current generator so that the programmable current generator receives a matched temperature independent reference current generated by the matching circuit in the internal generation mode;
connect the programmed current to the overvoltage/undervoltage detection circuit, with a feedback voltage being generated by components of the overvoltage/undervoltage detection circuit in the internal generation mode;
cause the multiplexer to pass a pulse width modulation, PWM, signal at its input to the second output pad, the PWM signal being generated by the pulse width modulation controller based upon the feedback voltage, in the internal generation mode; and
couple the PWM signal to a first output pad (Pad1).