Patent Description:
A processor, a system on a chip (SoC), and an application specific integrated circuit (ASIC) can include multiple cores for performing compute operations such as processing digital signals, performing cryptography, executing software applications, rendering graphics, and the like. In some examples, the cores may transmit data between each other when performing the compute operations. Typically, transferring data between cores requires the data to pass through a core-to-core interface that adds latency and is an inefficient use of memory.

<CIT> describes an integrated circuit having a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and reconfigurable logic that includes one or more connections to the switch.

The scope of protection in accordance to claim <NUM> defines a data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core having compute circuitry and a stall circuit coupled to the compute circuitry; a memory module comprising random access memory, RAM, banks, memory interfaces coupled to the RAM banks, wherein a memory interface is coupled to a memory connection of the compute circuitry, and wherein another memory interface is coupled to a memory connection to a respective at least one more of the other DPEs of the DPE array; and arbitration logic configured to control which memory interface has access to which RAM bank, and to forward, to the stall circuit, a signal indicative of a memory collision; direct memory access (DMA) circuitry coupled to the RAM banks; and a DPE interconnect. The DPE interconnect includes a streaming interconnect comprising a stream switch coupled to the DMA circuitry and the core, the stream switch being configured to route data streams through the stream switch based on configuration data stored in configuration registers in the stream switch; and a memory-mapped interconnect comprising a memory-mapped switch coupled to the core and the RAM banks, the memory-mapped switch being configured to route address transactions based on a memory address. The stall circuit is configured to assert a stall signal to stall the compute circuitry in case of a memory collision.

In some embodiments, the support circuitry may further include debug circuitry coupled to the core and the memory.

In some embodiments, the hardware synchronization circuitry may be configured to lock access to the one or more RAM banks by the core, a core in another DPE in the DPE array, and the DMA circuitry.

In some embodiments, the hardware synchronization circuitry may be configured to provide synchronization between the core and at least one other core in at least one other DPE in the DPE array.

In some embodiments, the DPE may further include a plurality of registers coupled to the memory-mapped interconnect.

In some embodiments, the streaming interconnect may include a stream switch having at least one connection to at least one additional DPE in the DPE array.

In some embodiments, the stream switch may include a connection to the core.

In some embodiments, the streaming interconnect may include a plurality of stream switches each having at least one connection to a different DPE in the DPE array in a different direction.

In some embodiments, the memory-mapped interconnect may include a memory-mapped switch having at least one connection to at least one additional DPE in the DPE array.

In some embodiments, the core may include a cascading interface to another core disposed in another DPE in the DPE array.

In some embodiments, the core may include a plurality of registers coupled to the memory-mapped interconnect.

In some embodiments, the core may include a very long instruction word (VLIW) processor, a single instruction, multiple data (SIMD) processor, or a VLIW SIMD processor.

In some embodiments, the program memory may be disposed in the core and may further include a memory module having the data memory and the support circuitry.

In some embodiments, the memory module may include at least one interface configured to be shared by at least one additional DPE in the DPE array.

In some embodiments, the DMA circuitry may include a first DMA circuit having an output coupled to the streaming interconnect and an input coupled to the data memory, and a second DMA circuit having an input coupled to the streaming interconnect and an output coupled to the data memory.

These and other aspects may be understood with reference to the following detailed description.

So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations.

It is contemplated that elements of one example may be beneficially incorporated in other examples.

<FIG> is a block diagram of a device <NUM> that includes a data processing engine (DPE) array <NUM>, according to an example. In examples, device <NUM> is a System-on-Chip (SoC) type of device. In general, an SoC refers to an IC that includes two or more subsystems capable of interacting with one another. As an example, an SoC may include a processor that executes program code and one or more other circuits. The other circuits may be implemented as hardwired circuitry, programmable circuitry, other subsystems, and/or any combination thereof. The circuits may operate cooperatively with one another and/or with the processor. The DPE array <NUM> includes a plurality of data processing engines (DPEs) <NUM> that may be arranged in a grid, cluster, or checkerboard pattern in the device <NUM>. Although <FIG> illustrates arranging the DPEs <NUM> in a 2D array with rows and columns, the examples are not limited to this arrangement. Further, the array <NUM> can be any size and have any number of rows and columns formed by the DPEs <NUM>.

In one embodiment, the DPEs <NUM> are identical. That is, each of the DPEs <NUM> (also referred to as tiles or blocks) may have the same hardware components or circuitry. Further, the examples herein are not limited to DPEs <NUM>. Instead, the device <NUM> can include an array of any kind of processing elements or data processing engines. Moreover, the DPEs <NUM> could be cryptographic engines or other specialized hardware for performing one or more specialized tasks. As such, the DPEs <NUM> can be referred to generally as data processing engines.

In <FIG>, the array <NUM> includes DPEs <NUM> that are all the same type (e.g., a homogeneous array). However, in another embodiment, the array <NUM> may include different types of engines. For example, the array <NUM> may include DPEs <NUM>, cryptographic engines, forward error correction (FEC) engines, and the like. Regardless if the array <NUM> is homogenous or heterogeneous, the DPEs <NUM> can include connections to memory modules in neighboring DPEs <NUM> which permit the DPEs <NUM> to share the memory modules as described in more detail below.

In one embodiment, the DPEs <NUM> are formed from non-programmable logic - i.e., are hardened. One advantage of doing so is that the DPEs <NUM> may take up less space in the device <NUM> relative to using programmable logic to form the hardware elements in the DPEs <NUM>. That is, using hardened or non-programmable logic circuitry to form the hardware elements in the DPEs <NUM> such as program memories, an instruction fetch/decode unit, fixed-point vector units, floating-point vector units, arithmetic logic units (ALUs), multiply accumulators (MAC), and the like can significantly reduce the footprint of the array <NUM> in the device <NUM>. Although the DPEs <NUM> may be hardened, this does not mean the DPEs <NUM> are not programmable. That is, the DPEs <NUM> can be configured when the device <NUM> is powered on or rebooted to perform different functions or tasks.

The DPE array <NUM> also includes an SoC interface block <NUM> that serves as a communication interface between the DPEs <NUM> and other hardware components in the device <NUM>. In this example, the device <NUM> includes a network on chip (NoC) <NUM> that is communicatively coupled to the SoC interface block <NUM>. Although not shown, the NoC <NUM> may extend throughout the device <NUM> to permit the various components in the device <NUM> to communicate with each other. For example, in a physical implementation, the DPE array <NUM> may be disposed in an upper right portion of the integrated circuit forming the device <NUM>. However, using the NoC <NUM>, the array <NUM> can nonetheless communicate with various subsystems, for example, programmable logic (PL) <NUM>, a processor subsystem (PS) <NUM> or input/output (I/O) <NUM> which may disposed at different locations throughout the device <NUM>.

In addition to providing an interface between the DPEs <NUM> and the NoC <NUM>, the SoC interface block <NUM> may also provide a connection directly to a communication fabric in the PL <NUM>. In one embodiment, the SoC interface block <NUM> includes separate hardware components for communicatively coupling the DPEs <NUM> to the NoC <NUM> and to the PL <NUM> that is disposed near the array <NUM> in the device <NUM>.

Although <FIG> illustrates one block of PL <NUM>, the device <NUM> may include multiple blocks of PL <NUM> (also referred to as configuration logic blocks) that can be disposed at different locations in the device <NUM>. For example, the device <NUM> may include hardware elements that form a field programmable gate array (FPGA). However, in other embodiments, the device <NUM> may not include any PL <NUM> - e.g., the device <NUM> is an ASIC.

<FIG> is a block diagram depicting a DPE <NUM> according to an example. The DPE <NUM> can be used to implement a DPE in a DPE array as discussed above and shown in <FIG>. The DPE <NUM> includes a core <NUM>, memory <NUM>, DPE interconnect <NUM>, and support circuitry <NUM>. The DPE interconnect <NUM> includes streaming interconnect <NUM> and memory-mapped (MM) interconnect <NUM>. In an example, the support circuitry <NUM> includes debug/trace/profile circuitry <NUM>, hardware (HW) synchronization circuitry ("HW locks <NUM>"), and direct memory access (DMA) circuitry ("DMA <NUM>"). The memory <NUM> includes program memory ("PM <NUM>") and data memory ("DM <NUM>").

The core <NUM> includes one or more compute units for processing data according to instruction(s) stored in the PM <NUM>. In an example, the core <NUM> includes a very-long instruction word (VLIW) processor, a single instruction, multiple data (SIMD) or vector processor, or a VLIW SIMD/vector processor. In an example, the PM <NUM> is private to the core <NUM> (e.g., the PM <NUM> stores instruction(s) only for use by the core <NUM> in the DPE <NUM>). In an example, the PM <NUM> comprises a single-ported random access memory (RAM). The PM <NUM> can be coupled to the MM interconnect <NUM> for configuration and loading of instructions. In an example, the PM <NUM> supports parity, error-correcting code (ECC) protection and reporting, or both parity and ECC. For example, the PM <NUM> can support <NUM>-bit ECC and be able to correct a <NUM>-bit error or <NUM>-bit errors in a program instruction (e.g., <NUM> bits).

The core <NUM> can be directly coupled to the streaming interconnect <NUM> to receive input stream(s) and/or provide output stream(s). In addition, the core <NUM> can read and write data to the DM <NUM> in the DPE <NUM>. As discussed further below, the core <NUM> in the DPE <NUM> can also access the DM in one or more neighboring tile circuits (e.g., north, south, east, and west neighboring tile circuits). In an example, as discussed further below, the core <NUM> can also include a direct connection with the data processing engine in one or more neighboring tiles for forwarding accumulator output (e.g., input and output cascading connection(s)). In an example, the core <NUM> sees the DM <NUM> in the DPE <NUM> and other DM(s) in neighboring tile(s) as one contiguous block of memory. The core <NUM> can also include an interface to the HW locks <NUM> and an interface to the debug/trace/profile circuitry <NUM>. The debug/trace/profile circuitry <NUM> can include trace, debug, and/or profile circuitry.

The MM interconnect <NUM> can be an AXI memory-mapped interconnect or the like configured for transmission of data using address transactions between components. In an example, the MM interconnect <NUM> is used for configuration, control, and debugging functionality for the DPE <NUM>. The MM interconnect <NUM> includes one or more switches that route transactions based on address. Circuitry can use the MM interconnect <NUM> to access the memory <NUM>, the core <NUM>, the DMA <NUM>, and configuration registers in the DPE <NUM>.

The streaming interconnect <NUM> can be an Advanced eXtensible Interconnect (AXI) streaming interconnect or the like configured for transmission of streaming data between components. The streaming interconnect <NUM> is used for transferring data between the DPE <NUM> and external circuits. The streaming interconnect <NUM> can support both circuit switching and packet switching mechanisms for both data and control.

In an example, as described further below, the DM <NUM> can include one or more memory banks (e.g., random access memory (RAM) banks). The DMA <NUM> is coupled between the streaming interconnect <NUM> and the DM <NUM>. The DMA <NUM> is configured to move data from the streaming interconnect <NUM> to the DM <NUM> and move data from the DM <NUM> to the streaming interconnect <NUM>. In this manner, an external circuit (e.g., a circuit configured in programmable logic or a circuit in an embedded processing system of the IC) can read data from and write data to the DM <NUM> through the streaming interconnect <NUM> using DMA. The DMA <NUM> can be controlled through the MM interconnect <NUM> and/or the streaming interconnect <NUM>. In an example, the DM <NUM> supports parity, error-correcting code (ECC) protection and reporting, or both parity and ECC. For example, the DM <NUM> can support <NUM>-bit ECC (e.g., <NUM>-bits data).

The HW locks <NUM> could be used to lock particular memory banks of the DM <NUM> for access by the core <NUM>, another data processing engine in another tile, or the DMA <NUM>. The HW locks <NUM> provide synchronization between neighboring data processing engines in neighboring tiles, between the core <NUM> and the DMA <NUM>, and between the core <NUM> and an external circuit (e.g., an external processor). The HW locks <NUM> can also be used to lock a particular buffer in the DM <NUM>, which may be stored in one or more memory banks or in a portion of a single memory bank. The debug/trace/profile circuitry <NUM> is configured to provide debug, trace, and profile functions. The debug/trace/profile circuitry <NUM> can trace events generated by circuits in the DPE <NUM>. The debug/trace/profile circuitry <NUM> can provide profile functionality, for example, configurable performance counters.

<FIG> is a block diagram depicting the DPE <NUM> in more detail according to an example. In the example, the DPE <NUM> includes core <NUM>, a memory module <NUM>, and DPE interconnect <NUM>. The core <NUM> includes the compute circuitry <NUM> and the PM <NUM>. The memory module <NUM> includes memory interfaces 302N, <NUM>, 302E, and 302W (collectively memory interfaces or individually "mem IF"), RAM banks <NUM>, the HW locks <NUM>, registers ("regs <NUM>"), a DMA interface 204A, and a DMA interface 220B. The compute circuitry <NUM> includes registers ("regs <NUM>"). The DPE interconnect <NUM> includes the MM interconnect <NUM> and the streaming interconnect <NUM> (shown in <FIG>). Both the MM interconnect <NUM> and the streaming interconnect <NUM> can access the RAM banks <NUM>. The RAM banks <NUM> include arbitration logic <NUM> per bank. The arbitration logic <NUM> is configured to control which interface (N, S, E, W, DMA, external PS, etc.) has access to which bank. Further details of the DPE interconnect <NUM> are discussed below with respect to the example of <FIG>.

The DPE interconnect <NUM> includes a streaming connection 314W to a west tile, a streaming connection 314E to an east tile, a streaming connection 314N to a north tile, and a streaming connection <NUM> to a south tile. Each streaming connection <NUM> includes one or more independent streaming interfaces (e.g., busses), each having a specific bit width. The DPE interconnect <NUM> also includes a memory-mapped connection <NUM> from a south tile and a memory-mapped connection 312N to a north tile. Although only north and south MM connections are shown, it is to be understood that the DPE interconnect <NUM> can include other configurations for the MM interconnect (e.g., east-to-west, west-to-east, north-to-south, and the like). It is to be understood that the DPE interconnect <NUM> can include other arrangements of streaming and memory-mapped connections than shown in the example of <FIG>. In general, the DPE interconnect <NUM> includes at least one streaming connection <NUM> and at least one memory-mapped connection <NUM>.

The compute circuitry <NUM> includes a connection 308W to memory circuitry in a west tile, a connection <NUM> to memory circuitry in a south tile, a connection 308N to memory circuitry in a north tile, and a connection 308E to the memory module <NUM>. The compute circuitry <NUM> include a streamlining interface to the DPE interconnect <NUM>. The compute circuitry <NUM> also includes a connection 310A from a core in the west tile and a connection 310B to a core in the east tile (e.g., cascading connections). It is to be understood that the DPE can include other arrangements of memory and cascading connections than shown in the example of <FIG>. In general, the compute circuitry <NUM> includes at least one memory connection and can include at least one cascading connection.

The mem IF 302W is coupled to the memory connection 308E of the compute circuitry <NUM>. The mem IF 302N is coupled to a memory connection of the data processing engine in the north tile. The mem IF 302E is coupled to a memory connection of the data processing engine in the east tile. The mem IF <NUM> is coupled to a memory connection of the data processing engine in the south tile. The mem IF 302W, 302N, 302E, and <NUM> are coupled to the RAM banks <NUM>. The DMA 220A includes an output coupled to the DPE interconnect <NUM> for handling memory to interconnect streams. The DMA 220B includes an input coupled to the DPE interconnect <NUM> for handling interconnect to memory streams. The regs <NUM> and the regs <NUM> are coupled to the DPE interconnect <NUM> to receive configuration data therefrom (e.g., using the memory-mapped interconnect).

<FIG> is a block diagram depicting the DPE interconnect <NUM> according to an example. The DPE interconnect <NUM> includes a stream switch <NUM> and an MM switch <NUM>. The stream switch <NUM> is coupled to a west stream interface 406W, a north stream interface 406N, an east stream interface 406E, and a south stream interface <NUM>. The west stream interface 406W receives and provides streams to the DPE interconnect of a west tile. The north stream interface 406N receives and provides streams to the DPE interconnect of a north tile. The west stream interface 406W receives and provides streams to the DPE interconnect of a west tile. The south stream interface <NUM> receives and provides streams to the DPE interconnect of a south tile. The MM switch <NUM> is coupled to a north MM interface 408N and a south MM interface <NUM>. The north MM interface 408N is coupled to the DPE interconnect in the north tile. The south MM interface <NUM> is coupled to the DPE interconnect in the south tile.

The stream switch <NUM> includes first-in-first-out (FIFO) circuits (FIFOs <NUM>) and registers (regs <NUM>). The FIFOs <NUM> are configured to buffer streams passing through the stream switch <NUM>. The regs <NUM> store configuration data for the stream switch <NUM> that controls the routing of streams through the stream switch. The regs <NUM> can receive configuration data from the MM switch <NUM>. The stream switch <NUM> can include an additional interface to the compute circuitry <NUM> and an additional interface to the DMA circuitry <NUM>. The stream switch <NUM> can send and receive control streams and receive trace streams (e.g., from the debug/trace/profile circuitry <NUM>).

<FIG> is a block diagram depicting the core <NUM> according to another example. Elements in <FIG> that are the same or similar to those discussed above are designated with identical reference numerals. The core <NUM> further includes a stall circuit <NUM>. <FIG> is a flow diagram depicting operation of the stall circuit <NUM> according to an example.

Referring to <FIG> and <FIG>, the stall circuit <NUM> is coupled to the compute circuitry <NUM> and is configured to provide a stall signal. The stall circuit <NUM> also provides the stall signal to the memory module <NUM>. The stall circuit <NUM> can assert the stall signal to stall the compute circuitry <NUM> (e.g., suspend operation of the compute circuitry <NUM> so that it does not process data). When the stall signal is de-asserted, the compute circuitry <NUM> is not stalled and processes data. The stall circuit <NUM> sets the state of the stall signal according to various inputs from circuits in the DPE <NUM> or circuits external to the DPE <NUM>. In addition, once the stall circuit <NUM> stops the compute circuitry <NUM>, the stall circuit <NUM> can stop other components of the DPE <NUM>. For example, the stall circuit <NUM> can stop specific blocks in the memory module <NUM> that provide data to the compute circuitry <NUM>. That is, since the compute circuitry <NUM> is stopped, data "in-flight" from the memory module <NUM> can be stalled to avoid data loss. In another example, the stall circuit <NUM> can perform a similar function for the program memory <NUM>. That is, since the compute circuitry <NUM> is stopped, instructions "in-flight" from the program memory <NUM> can be stalled to avoid instruction loss.

In an example, the stall circuit <NUM> includes inputs <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. The input <NUM> is coupled to the arbitration logic <NUM> and is configured to receive a signal indicative of a memory collision (step <NUM>). For example, another data processing engine can be accessing a particular RAM bank <NUM> in the DPE <NUM>, which would then be inaccessible to the compute circuitry <NUM>. The arbitration logic <NUM> signals the stall circuit <NUM>, which asserts the stall signal to stall the compute circuitry <NUM> and prevent the compute circuitry <NUM> from accessing the RAM bank <NUM> under contention.

The input <NUM> is coupled to the PS <NUM> and is configured to receive a control signal used to stall the compute circuitry <NUM> (step <NUM>). For example, software executing on the PS <NUM> can stall the compute circuitry <NUM> and resume the compute circuitry <NUM> on demand.

The input <NUM> is coupled to the stream switch <NUM> and is configured to receive a signal indicative of an empty or full condition of the FIFOs <NUM> (step <NUM>). For example, if the FIFOs <NUM> are full, the FIFOs <NUM> cannot store additional data output from the compute circuitry <NUM>. Thus, the compute circuitry <NUM> is stalled to prevent overflow of the FIFOs <NUM>. Once the FIFOs <NUM> are no longer full (e.g., at the empty condition), the compute circuitry <NUM> can be resumed.

The input <NUM> is coupled to a register <NUM> and is configured to receive a signal indicative of stall or resume (step <NUM>). In an example, the register <NUM> can be programmed through the MM interconnect <NUM> and allows for the user to program a stall or resume of the compute circuitry <NUM> through configuration of the array.

The input <NUM> is coupled to the debug/trace/profile circuitry <NUM> and is configured to receive a signal indicative of one or more events that require a stall of the compute circuitry <NUM> (step <NUM>). Event actions can include enable, disable single-step debug, and the like and can be configured to be triggered whenever a specific event occurs.

The input <NUM> is coupled to the HW locks <NUM> and is configured to receive a signal indicative of whether a RAM bank <NUM> has been locked for access by another circuit (e.g., another data processing engine) (step <NUM>). In such case, the compute circuitry <NUM> is stalled until the particular RAM bank <NUM> being accessed becomes free.

At step <NUM>, the stall circuit <NUM> de-asserts the stall signal in response to resolution of all conditions that caused assertion of the stall signal. That is, when each condition that causes assertion of the stall signal is resolved, the stall circuit <NUM> de-asserts the stall signal to resume full operation of the DPE.

<FIG> is a block diagram depicting the core <NUM> according to an example. The core <NUM> includes register files <NUM>, the compute circuitry <NUM>, and support circuitry <NUM>. The register files <NUM> include scalar register files <NUM> and vector register files <NUM>. The scalar register files <NUM> include general purpose registers, pointer registers, modifier registers, configuration registers, and the like. The vector register files <NUM> include high-width registers (as compared to the scalar registers) that support SIMD instructions for a vector data path. The vector register files <NUM> can include vector registers, accumulator registers, and the like. The register files <NUM> can include other types of registers, such as a program counter, stack pointer, link register, various configuration, control and status registers, and the like.

The compute circuitry <NUM> includes a scalar processor <NUM> and a vector processor <NUM>. The scalar processor <NUM> is configured to perform scalar arithmetic, including signed and unsigned multiplication, add/subtract, shifts, compares, and logical operations, elementary functions, such as square-root, sine/cosine, and the like. The vector processor <NUM> is configured to perform vector arithmetic, including permute functions, pre-addition functions, multiplication functions, post-addition functions, accumulation functions, shift, round and saturate functions, upshift functions, and the like. The vector processor <NUM> supports multiple precisions for complex and real operands. The vector processor <NUM> can include both fixed-point and floating-point data paths.

The support circuitry <NUM> includes a memory interface <NUM>, address generators <NUM>, instruction fetch and decode circuitry <NUM>, and one or more additional interfaces <NUM>. The instruction fetch and decode circuitry <NUM> is configured to fetch instructions from the PM <NUM>, decode the fetched instructions, and provide control signals to the processor <NUM> to control operation thereof according the decoded instructions. The address generators <NUM> are configured to generate addresses for data memory to load data from or store data to the data memory. The memory interface <NUM> is configured to communicate with data memory to send data to and receive data from data memory according to the decoded instructions and the addresses generated by the address generators <NUM>. The other interfaces <NUM> can include an interface to the HW locks <NUM>, an interface to the streaming interconnect <NUM>, an interface to receive cascade stream(s) from other data processing engines, an interface to the debug/trace/profile circuitry <NUM>, and the like.

<FIG> is a block diagram depicting a pipeline <NUM> in the vector processor <NUM> according to an example. The pipeline <NUM> is configured to perform fixed-point vector processing and includes a multiply-accumulate (MAC) path <NUM> and an upshift path <NUM>. The MAC path <NUM> reads values from vector registers, permutes them in a user-controllable fashion, performs optional pre-adding, multiplies them after some post-adding, and accumulates them to the previous value of the accumulation register. The upshift path <NUM> operates in parallel to the MAC path <NUM> and is configured to read vectors, upshift them, and feed the result into the accumulator. The pipeline <NUM> further includes a control circuit <NUM> configured to control the various circuits in the MAC path <NUM> and the upshift path <NUM>, as discussed further below.

<FIG> is a table <NUM> showing an example configuration of vector register files <NUM> according to an example. As shown in the table <NUM>, the core <NUM> includes three separate vector register files denoted R, C, and D, with an additional prefix specifying their width. In the example, the underlying hardware registers are each <NUM>-bits wide. The hardware registers are prefixed with the letter "V" (for vector). Two "V" registers can be grouped together to form a <NUM>-bit register, which is prefixed with a "W" (for wide vector). Furthermore, the WR, VC, and WD registers can be grouped pairwise to form a <NUM>-bit wide register (XA, XB, XC, and XD). Finally, the registers XA and XB together form a <NUM>-bit wide YA register, whereas XD and XB form a partially overlapping <NUM>-bit wide YD register. In YD, the XD register is the LSB part and the XB register is the MSB part.

The vector registers in the vector register files <NUM> can store data in different formats. For example, the <NUM>-bit registers can be used to represent <NUM> lanes of <NUM>-bit signed data (v16int8), <NUM> lines of <NUM>-bit unsigned real data (v16uint8), <NUM> lanes of <NUM>-bit signed data (v8int16), <NUM> lanes of <NUM>-bit complex data (v4cint16), and <NUM> lanes of <NUM>-bit complex data (v2cint32).

The table <NUM> shown in <FIG> depicts just one possible configuration of the vector register files <NUM>. For example, the vector register files <NUM> can include less or more than <NUM> hardware registers, which can have any bit width, and which can be grouped into larger registers also having different bit widths than shown. Various register files can be combined to provide a smaller number of larger registers, for example. Alternatively, various registers can be divided into a larger number of smaller registers.

Returning to <FIG>, the pipeline <NUM> includes a register file <NUM> (formed from a concatenation of XA and XB), a register file <NUM> (XC), and a register file <NUM> (XD). In the example of <FIG>, the register file <NUM> includes eight <NUM>-bit hardware registers, the register file <NUM> includes four <NUM>-bit hardware registers, and the register file <NUM> includes four <NUM>-bit hardware registers. In other examples, the register files <NUM>, <NUM>, and <NUM> can include other numbers of registers having different bit-widths. The configuration of register files <NUM>, <NUM>, and <NUM> is one example. In another example, the register files <NUM>, <NUM>, and <NUM> can be unified into a single register file. In other examples, the pipeline <NUM> can include more than three register files.

The pipeline <NUM> further includes the MAC path <NUM> having a permute circuit <NUM> (PMXL), a permute circuit <NUM> (PMXR), a permute circuit <NUM> (PMC), a pre-adder <NUM>, a special operation circuit <NUM> (YMX), a multiplier <NUM> (MPY), a post-adder <NUM>, an accumulator <NUM> (ACC), and an accumulation register file <NUM> (AM). In an example, the post-adder <NUM> includes two separate stages, i.e., a post-adder <NUM> and a post-adder <NUM>. The pipeline <NUM> includes the upshift path <NUM> having a multiplexer <NUM> (MUX), an upshift circuit <NUM> (UPS), and an accumulator multiplexer <NUM> (ACM). While three permute circuits <NUM>, <NUM>, and <NUM> are shown in the example, in other examples, the pipeline <NUM> can include a single permute circuit that incorporates the functionality of the permute circuits <NUM>, <NUM>, and <NUM>.

An input of the permute circuit <NUM> is coupled to outputs of the register file <NUM>, an input of the permute circuit <NUM> is coupled to the outputs of the register file <NUM>, and inputs of the permute circuit <NUM> is coupled to outputs of the register file <NUM>. A first input of the pre-adder <NUM> is coupled to an output of the permute circuit <NUM> and a second input of the pre-adder <NUM> is coupled to an output of the permute circuit <NUM>. A first input of the special operation circuit <NUM> is coupled to the output of the permute circuit <NUM>, and a second input of the special operation circuit <NUM> is coupled to an output of the permute circuit <NUM>. Outputs of the pre-adder <NUM> and the special operation circuit <NUM> are coupled to inputs of the multiplier <NUM>. An output of the multiplier <NUM> is coupled to an input of the post-adder <NUM>. An output of the post-adder <NUM> is coupled to an input of the post-adder <NUM>. An output of the post-adder <NUM> is coupled to an input of the accumulator <NUM>. An output of the accumulator <NUM> is coupled to an input of the register file <NUM>.

In an example, the register file <NUM> contains a <NUM>-bit vector (e.g., a concatenation of XA::XB, each of which is <NUM>-bits). An input (pmxA) to the permute circuits <NUM> and <NUM> can be <NUM> bits. Likewise, another input (pmxB) to the permute circuits <NUM> and <NUM> can be <NUM> bits. Thus, each permute circuit <NUM> and <NUM> receives a concatenation of pmxA::pmxB from the register file <NUM> (e.g., <NUM> bits).

The permute circuit <NUM> is configured to permute the data from the register file <NUM> for the "left" input of the pre-adder <NUM>. The permute circuit <NUM> is configured to permute the data from the register file <NUM> for the "right" input of the pre-adder <NUM> or alternatively for the first input of the special operation circuit <NUM>. The permute circuit <NUM> is configured to permute the data from the register file <NUM> for input to the special operation circuit <NUM>. In an example, the permute circuits <NUM> and <NUM> are functionally identical. Operation of the permute circuits <NUM>, <NUM>, and <NUM> as a data selection network for the vector processor <NUM> is discussed further below. The permute circuit <NUM> includes an output (praXL), which can be <NUM>-bits. The permute circuit <NUM> includes an output (praXR), which can also be <NUM>-bits. The permute circuit <NUM> includes an output pmcR, which can also be <NUM>-bits. Each of the permute circuits <NUM>, <NUM>, and <NUM> can receive a control signal from the control circuit <NUM> for operation, as discussed below.

The pre-adder <NUM> can operate in multiple modes based on a control signal from the control circuit <NUM>. In a first mode, the pre-adder <NUM> feeds through the input data (praXL::praXR) to the multiplier <NUM>. In the first mode, no pre-addition is performed. In a second mode, the pre-adder <NUM> can add/subtract the output (praXL) of the permute circuit <NUM> with the output (praXR) of the permute circuit <NUM>. The special operation circuit <NUM> can operate in multiple modes. In a first mode, the special operation circuit <NUM> feeds through the input data to the multiplier <NUM> (praXR::pmcR). In additional modes, the special operation circuit <NUM> can output a constant '<NUM>' value, perform sign extension of the input data, and the like type manipulation of the input data.

The multiplier <NUM> is configured to multiply the output of the pre-adder <NUM> by the output of the special operation circuit <NUM>. The multiplier <NUM> can include an array of multiplier circuits configured to multiple different portions of the output of the pre-adder <NUM> with different portions of the output of the special operation circuit <NUM>. The operation of the multiplier <NUM> is determined by a control signal from the controller <NUM>. The post-adder <NUM> is configured to reduce the output lanes of the multiplier <NUM> by adding/subtracting particular lanes. For example, the post-adder <NUM> can take neighboring even lanes and neighboring odd lanes and adds them (or subtracts them). The post-adder <NUM> is configured to operate in different modes. In a first mode, the post-adder <NUM> passes the output from the post-adder <NUM> and performs no additional function. That is, the post-adder <NUM> is optionally included in the processing of the pipeline <NUM>. In a second mode, the post-adder <NUM> performs a similar function as the post-adder <NUM>. For example, the post-adder <NUM> can take neighboring even lanes and neighboring odd lanes and adds them (or subtracts them). The accumulator <NUM> is configured to accumulate (e.g., add or subtract) the output of the post-adder <NUM>. The functionality of the post-adder <NUM>, the post-adder <NUM>, and the accumulator (for add or subtract) is determined by control signals from the control circuit <NUM>. The output of the accumulator is stored in the register file <NUM>.

The upshift path <NUM> operates in parallel to the MAC path <NUM>. The upshift path <NUM> can read data from the register file <NUM>, or from any of the permute circuits <NUM>, <NUM>, and <NUM> via the multiplexer <NUM>. The upshift circuit <NUM> is configured to shift the output of the multiplexer <NUM> (e.g., left-shift) by a selectable amount under control of the control circuit <NUM>. The multiplexer <NUM> selects either the output of the upshift circuit <NUM> or the output of the post-adder <NUM> for coupling to the accumulator <NUM>. The upshift path <NUM> can be used to initialize the accumulator <NUM> with a value before processing.

<FIG> is a block diagram depicting a logical view <NUM> of the pipeline <NUM> for the vector processor <NUM> according to an example. The logical view <NUM> shows a register file <NUM>, permute circuits <NUM>, and calculation circuits <NUM>. The register file <NUM> is coupled to the calculation circuits <NUM> by the permute circuits <NUM>. The register file <NUM> can include, for example, the register configuration shown in <FIG> and <FIG> (or any other register configuration). The calculation circuits <NUM> include pre-adders, special operation circuits, multipliers, post-adders, accumulators, and the like configured to process data in the register file <NUM>. An example of the calculation circuits <NUM> is shown in <FIG> and described above (e.g., the circuits of the MAC path <NUM>). The permute circuits <NUM> function as a data selection network for the calculation circuits <NUM>.

In an example, the register file <NUM> includes the register file <NUM> and the register file <NUM>, as discussed above. In an example, the permute circuits <NUM> include the permute circuits <NUM>, <NUM>, and <NUM>, described above. Each register file <NUM> and <NUM> provides a plurality of output lanes, where each lane includes M-bits (e.g., <NUM> lanes each <NUM>-bits each). The permute circuit <NUM> is coupled to the register file <NUM> and is configured to generate a vector by selecting a set of the output lanes provided by the register file <NUM>. The permute circuit <NUM> is also coupled to the register file <NUM> and is configured to generate another vector by selecting a set of the output lanes provided by the register file <NUM> (e.g., a potentially different set than that selected by the permute circuit <NUM>). Similar to the register file <NUM>, the register file <NUM> is configured to provide a plurality of output lanes (e.g., a different number than the register file <NUM>). The permute circuit <NUM> is coupled to the register file <NUM> and is configured to generate another vector by selecting a set of output lanes thereof. The outputs of the permute circuits <NUM> are provided to the calculation circuits <NUM>, which perform, for example, MAC operations thereon.

In an example, each permute circuit <NUM> and <NUM> is configured to select <NUM> chunks of <NUM>-bits each from one of thirty-two <NUM>-bit lanes of an input vector. The <NUM> output lanes of <NUM>-bit each form the <NUM>-bit output vector. Each permute circuit <NUM> and <NUM> is a full multiplexer and can select any input. In an example, each permute circuit <NUM> and <NUM> can be implemented using a series of <NUM> multiplexers that are <NUM>-bits wide and select from <NUM> different source lanes. Alternative structures can be used, such as Benes networks and the like. The permute circuit <NUM> is functionally similar to the permute circuits <NUM> and <NUM>, but in an example only selects from an input vector of <NUM>-bits in width. The selection granularity is <NUM>-bits, hence each lane of the multiplier can be selected individually. Note that the numbers, widths, etc. discussed above for the permute circuits <NUM>, <NUM>, and <NUM> are exemplary and they can be configured with different widths, to select from different numbers of lanes, having different widths.

<FIG> is a block diagram depicting a programmable IC <NUM> according to an example that can be used as an implementation of the device <NUM> shown in <FIG>. The programmable IC <NUM> includes programmable logic <NUM>, configuration logic <NUM>, and configuration memory <NUM>. The programmable IC <NUM> can be coupled to external circuits, such as nonvolatile memory <NUM>, DRAM <NUM>, and other circuits <NUM>. The programmable logic <NUM> includes logic cells <NUM>, support circuits <NUM>, and programmable interconnect <NUM>. The logic cells <NUM> include circuits that can be configured to implement general logic functions of a plurality of inputs. The support circuits <NUM> include dedicated circuits, such as transceivers, input/output blocks, digital signal processors, memories, and the like. The logic cells and the support circuits <NUM> can be interconnected using the programmable interconnect <NUM>. Information for programming the logic cells <NUM>, for setting parameters of the support circuits <NUM>, and for programming the programmable interconnect <NUM> is stored in the configuration memory <NUM> by the configuration logic <NUM>. The configuration logic <NUM> can obtain the configuration data from the nonvolatile memory <NUM> or any other source (e.g., the DRAM <NUM> or from the other circuits <NUM>). In some examples, the programmable IC <NUM> includes a processing system <NUM>. The processing system <NUM> can include microprocessor(s), memory, support circuits, IO circuits, and the like.

<FIG> illustrates a field programmable gate array (FPGA) implementation of the programmable IC <NUM> that includes a large number of different programmable tiles including transceivers <NUM>, configurable logic blocks ("CLBs") <NUM>, random access memory blocks ("BRAMs") <NUM>, input/output blocks ("IOBs") <NUM>, configuration and clocking logic ("CONFIG/CLOCKS") <NUM>, digital signal processing blocks ("DSPs") <NUM>, specialized input/output blocks ("I/O") <NUM> (e.g., configuration ports and clock ports), and other programmable logic <NUM> such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. The FPGA can also include PCIe interfaces <NUM>, analog-to-digital converters (ADC) <NUM>, and the like.

In some FPGAs, each programmable tile can include at least one programmable interconnect element ("INT") <NUM> having connections to input and output terminals <NUM> of a programmable logic element within the same tile, as shown by examples included at the top of <FIG>. Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments <NUM>) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments <NUM>) can span one or more logic blocks. The programmable interconnect elements <NUM> taken together with the general routing resources implement a programmable interconnect structure ("programmable interconnect") for the illustrated FPGA.

In an example implementation, a CLB <NUM> can include a configurable logic element ("CLE") <NUM> that can be programmed to implement user logic plus a single programmable interconnect element ("INT") <NUM>. A BRAM <NUM> can include a BRAM logic element ("BRL") <NUM> in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile <NUM> can include a DSP logic element ("DSPL") <NUM> in addition to an appropriate number of programmable interconnect elements. An lOB <NUM> can include, for example, two instances of an input/output logic element ("IOL") <NUM> in addition to one instance of the programmable interconnect element <NUM>. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element <NUM> typically are not confined to the area of the input/output logic element <NUM>.

In the pictured example, a horizontal area near the center of the die (shown in <FIG>) is used for configuration, clock, and other control logic. Vertical columns <NUM> extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated in <FIG> include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic.

Claim 1:
A data processing engine, DPE, (<NUM>) for a DPE array (<NUM>) in an integrated circuit (IC), comprising:
a core (<NUM>) having compute circuitry (<NUM>) and a stall circuit (<NUM>) coupled to the compute circuitry (<NUM>);
a memory module (<NUM>) comprising
random access memory, RAM, banks (<NUM>);
memory interfaces (302W, 302N, <NUM>, 302E) coupled to the RAM banks (<NUM>), wherein a memory interface (302W) is coupled to a memory connection (308E) of the compute circuitry (<NUM>), and wherein another memory interface (302N, <NUM>, 302E) is coupled to a memory of another DPE <NUM> of the DPE array (<NUM>);
arbitration logic (<NUM>) configured to control which memory interface (302W, 302N, <NUM>, 302E) has access to which RAM bank (<NUM>), and to forward, to the stall circuit (<NUM>), a signal indicative of a memory collision; and
direct memory access, DMA, circuitry (<NUM>) coupled to the RAM banks (<NUM>); and
a DPE interconnect (<NUM>) comprising
streaming interconnect (<NUM>) comprising a stream switch (<NUM>) coupled to the DMA circuitry (<NUM>) and the core (<NUM>), the stream switch (<NUM>) being configured to route data streams through the stream switch (<NUM>) based on configuration data stored in configuration registers in the stream switch (<NUM>); and
memory-mapped interconnect (<NUM>) comprising a memory-mapped switch (<NUM>) coupled to the core (<NUM>) and the RAM banks (<NUM>), the memory-mapped switch (<NUM>) being configured to route address transactions based on a memory address,
wherein the stall circuit (<NUM>) is configured to assert a stall signal to stall the compute circuitry (<NUM>) in case of a memory collision.