Patent Description:
Voltage regulators have been implemented in conventional dedicated power management integrated circuits (PMICs). A conventional PMIC, which is separate from other integrated circuits on a circuit board, may have difficulty meeting the droop (transient) and power (efficiency) requirements of a modern multi-core application processor or communication processor, for example.

There has been a growing interest in integrating voltage regulators as part of system-on-chip (SOC) integrated circuit devices. Integrated voltage regulators, however, may present several challenges in chip design and layout. For example, passive components such as inductors and capacitors in voltage regulators may pose a design challenge, because passive components, such as inductors and capacitors, especially those with large inductance and capacitance values, typically have large form factors requiring large surface areas in a typical layout for a silicon SOC die.

Moreover, inductors in voltage regulators typically require very low resistances to minimize power losses in voltage regulation. In addition to occupying a significant amount of surface area of a typical silicon SOC die, such inductors may require thick metal traces on the SOC die in order to reduce the resistance values of the inductors. In advanced-node SOC wafer fabrication, however, such thick metal traces may not be feasible. Moreover, even if thick metal traces are implementable on a silicon SOC die, conventional fabrication processes for integrating inductors as part of a voltage regulator on a silicon SOC die may require several additional masks, thereby increasing the cost of fabrication. <CIT> describes a structure and method of making a coil inductor on a semiconductor chip, on an interconnection device, or on a plurality of stacked semiconductor chips. <CIT> relates to systems and methods for providing.

Exemplary embodiments of the disclosure are directed to integrated circuit devices and methods of making the same. In accordance with the present invention, there is provided a device as set out in claim <NUM> and a method of making a device as set out in claim <NUM>. Other aspects of the invention can be found in the dependent claims.

The accompanying drawings are presented to aid in the description of embodiments of the disclosure and are provided solely for illustration of the embodiments and not limitation thereof.

Aspects of the disclosure are described in the following description and related drawings directed to specific embodiments. Alternate embodiments may be devised. Additionally, well-known elements will not be described in detail or will be omitted so as not to obscure the relevant details of the disclosure.

Likewise, the term "embodiments" does not require that all embodiments include the discussed feature, advantage or mode of operation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Moreover, it is understood that the word "or" has the same meaning as the Boolean operator "OR," that is, it encompasses the possibilities of "either" and "both" and is not limited to "exclusive or" ("XOR"), unless expressly stated otherwise. It is also understood that the symbol "/" between two adjacent words has the same meaning as "or" unless expressly stated otherwise. Moreover, phrases such as "connected to," "coupled to" or "in communication with" are not limited to direct connections unless expressly stated otherwise.

<FIG> is a perspective view illustrating an embodiment of a system-on-chip (SOC) wafer <NUM> having a first surface <NUM> and a second surface <NUM> opposite each other. In an embodiment, the SOC wafer <NUM> comprises a semiconductor wafer, such as a silicon wafer. In alternate embodiments, the SOC wafer <NUM> may comprise a glass wafer, a quartz wafer, an organic wafer, or a wafer made of another material. In the embodiments, the SOC wafer <NUM> is integrated with an inductor wafer on which one or more inductors are provided.

<FIG> is a perspective view illustrating an embodiment of an inductor wafer <NUM> with a plurality of through vias 202a, 202b, 202c,. In the embodiment illustrated in <FIG>, the inductor wafer <NUM> has first and second surfaces <NUM> and <NUM> opposite each other, and the vias 202a, 202b, 202c,. are formed through the first and second surfaces <NUM> and <NUM> of the inductor wafer <NUM>. In an embodiment, the inductor wafer <NUM> comprises a glass wafer. In alternate embodiments, the inductor wafer <NUM> may comprise a quartz wafer, an organic wafer, or another type of low-loss dielectric material, to ensure that the inductor fabricated on the inductor wafer <NUM> has a low parasitic loss. For simplicity of illustration, detailed structure of the conductors in the vias 202a, 202b, 202c,. and the patterned conductive layers on the first and second surfaces <NUM> and <NUM> of the inductor wafer <NUM> which form one or more coils of an integrated inductor are not shown in the perspective view of <FIG>. Embodiments of the integrated inductor formed on the inductor wafer <NUM> will be described in further detail below with respect to <FIG> and the top plan view of <FIG>.

<FIG> is a perspective view illustrating an embodiment of face-to-face wafer-to-wafer bonding of the SOC wafer <NUM> and the inductor wafer <NUM>. In this embodiment, the second surface <NUM> of the SOC wafer <NUM> is joined with the first surface <NUM> of the inductor wafer <NUM>. Again, detailed structure of the integrated inductor formed on the inductor wafer <NUM> is omitted in <FIG> for simplicity of illustration. Embodiments of the integrated inductor formed on the inductor wafer <NUM> will be described with respect to <FIG>.

<FIG> is a sectional view illustrating an embodiment of a first process step in the manufacturing of an inductor on an inductor wafer with through vias. In <FIG>, an inductor wafer <NUM> having a first surface <NUM> and a second surface <NUM> is provided. The inductor wafer <NUM> may be a glass wafer, a quartz wafer, or another type of wafer made of a low-loss dielectric material, for example. In the embodiment shown in <FIG>, first and second vias <NUM> and <NUM> are formed within the inductor wafer <NUM> through the first and second surfaces <NUM> and <NUM>.

<FIG> is a sectional view illustrating an embodiment of a second process step in the manufacturing of the inductor with a magnetic layer. In <FIG>, a magnetic layer, such as a patterned thin-film magnetic layer <NUM>, is formed on the first surface <NUM> of the inductor wafer <NUM>. In the embodiment illustrated in <FIG>, the patterned thin-film magnetic layer <NUM> is formed on the first surface <NUM> of the portion of the inductor wafer <NUM> between the first and second vias <NUM> and <NUM>.

The patterned thin-film magnetic layer <NUM> may be fabricated in various manners. For example, a magnetic material, such as cobalt-tantalum-zirconium (CoTaZr), may be deposited by vacuum processes, plated, screen-printed, or laminated onto the first surface <NUM> of the inductor wafer <NUM> to form the thin-film magnetic layer <NUM>. Other magnetic materials, such as alloys of nickel-iron (NiFe), cobalt-iron (CoFe), or cobalt-nickel-iron (CoNiFe), with added materials such as phosphorus (P), boron (B) or carbon (C), may be used for the patterned thin-film magnetic layer <NUM> to tailor the magnetic and electrical properties of the patterned thin-film magnetic layer <NUM>. In an embodiment, the magnetic material for the patterned thin-film magnetic layer <NUM> is chosen so as to enable a boost in the inductance value of the inductor at the appropriate operating frequencies. Other types of magnetic materials may also be implemented as the patterned thin-film magnetic layer <NUM>. The magnetic layer <NUM> may also be formed by other techniques, for example, by sputtering a magnetic material on the first surface <NUM> of the inductor wafer <NUM>.

<FIG> is a sectional view of an embodiment of a third process step in the manufacturing of the inductor with a dielectric on the patterned thin-film magnetic layer. In <FIG>, a dielectric layer <NUM> is formed on top of the patterned thin-film magnetic layer <NUM>. In the embodiment illustrated in <FIG>, the dielectric layer <NUM> covers the entire top and side surfaces of the thin-film magnetic layer <NUM>, as well as portions of the first surface <NUM> of the inductor wafer <NUM> surrounding the patterned thin-film magnetic layer <NUM>. In an embodiment, the dielectric layer <NUM> comprises a polymer dielectric material. In an alternate embodiment, the dielectric layer <NUM> comprises an inorganic dielectric material, for example, silicon dioxide (SiO<NUM>). Other types of dielectric materials may also be used for the dielectric layer <NUM> within the scope of the disclosure.

<FIG> is a sectional view of an embodiment of a fourth process step in the manufacturing of the inductor with metal plating. In the sectional view shown in <FIG>, the first via <NUM> has sidewalls <NUM> and <NUM>, and likewise, the second via <NUM> has sidewalls <NUM> and <NUM> between the first and second surfaces <NUM> and <NUM> of the inductor wafer <NUM>. In an embodiment, a conductive layer <NUM> is formed on the dielectric layer <NUM>, on the sidewall <NUM> of the first via <NUM>, on the sidewall <NUM> of the second via <NUM>, and on the second surface <NUM> of the inductor wafer <NUM> between the first and second vias <NUM> and <NUM>. In an embodiment, the conductive layer <NUM> is formed by metal plating.

In a further embodiment, the conductive layer is formed by semi-additive plating of a metal such as copper (Cu). In the sectional view shown in <FIG>, the sidewall <NUM> opposite the sidewall <NUM> the first via <NUM> and at least portions of the first and second surfaces <NUM> and <NUM> of the inductor wafer <NUM> adjacent to the sidewall <NUM> are also covered by a conductive layer <NUM>. Likewise, as shown in <FIG>, the sidewall <NUM> opposite the sidewall <NUM> the second via <NUM> and at least portions of the first and second surfaces <NUM> and <NUM> of the inductor wafer <NUM> adjacent to the sidewall <NUM> are also covered by a conductive layer <NUM>. Similar to the conductive layer <NUM>, the conductive layers <NUM> and <NUM> may also be formed by metal plating, such as semi-additive copper plating.

In the embodiment illustrated in the sectional view of <FIG>, the conductive layer <NUM> is shown as a section of one loop of an inductor coil which comprises a plurality of loops. A top plan view of an embodiment of a solenoid inductor which comprises an inductor coil with multiple loops is shown in <FIG>, which will be described in further detail below. Other inductor topologies, for example, spiral inductors, toroid inductors, or racetrack inductors, may also be implemented instead of the solenoid inductor in the embodiments described and illustrated herein. In an SOC package with a limited amount of space, however, a solenoid inductor may be chosen for its small footprint and easy, efficient integration closest to the circuitry on the SOC die.

Referring to the embodiment shown in <FIG>, the conductive layer <NUM>, which is illustrated as the sectional view of one loop of coil of an inductor, surrounds the thin-film magnetic layer <NUM>, which is implemented as a magnetic core of the inductor. In an alternate embodiment, another magnetic layer may be provided within the inductor coil, for example, a magnetic layer formed on the second surface <NUM> of the inductor wafer <NUM> opposite the magnetic layer <NUM> as shown in <FIG>, to increase the overall magnetic flux and thus the overall inductance of the inductor. In an example not forming part of the present invention but useful for understanding, an inductor with multiple loops of coil, with each loop having a sectional view similar to the sectional view of the conductive layer <NUM> as shown in <FIG>, may be provided without any magnetic layer inside the coil, although such an inductor with no magnetic core would have a lower inductance compared to an inductor of the same size and the same number of loops having one or more magnetic cores.

<FIG> is a top plan view of an inductor <NUM> having a coil <NUM> with multiple loops before the SOC wafer is joined with the inductor wafer. In an embodiment, a sectional view of one of the loops <NUM> taken along sectional line 806a-806b is illustrated in <FIG>. Referring to the top plan view of <FIG>, the inductor <NUM> has two terminals <NUM> and <NUM> at two opposite ends of the coil <NUM> for electrical connections with other circuit components in a voltage regulator. In the embodiments, some of the pass-through vias in the inductor wafer <NUM>, like the first via <NUM> and the second via <NUM> as illustrated in <FIG>, are used to form electrical connections between die pads on the SOC die and pads on the substrate. For example, some of the pass-through vias may be connected to enable power supply connections and/or to provide ground planes to improve power delivery to the SOC die. In an embodiment, the conductive layer <NUM>, which may comprise a thick Cu plating on the inductor wafer <NUM>, can be used as an additional routing layer to improve the performance of an advanced node SOC device with an advanced node SOC wafer <NUM>. In a further embodiment, by using a combined design of the advanced node SOC wafer <NUM>, the inductor wafer <NUM>, and a package substrate <NUM> on an integrated circuit (IC) package <NUM>, which will be described in further detail below with respect to <FIG>, the thick Cu plating of the conductive layer <NUM> can be used to reduce the number of Cu layers in the advanced node SOC wafer <NUM>, or in the package substrate <NUM>, or both.

<FIG> is a sectional view illustrating an embodiment of a fifth process step in the manufacturing of a system-on-chip (SOC) device by joining an SOC wafer with an inductor wafer. In the embodiments, the SOC wafer <NUM> is provided with a plurality of metal columns, such as metal column <NUM> on the second surface <NUM> of the SOC wafer. In an embodiment, a solder <NUM> is provided on the metal column <NUM> for joining with a respective metal-plated via of the inductor wafer. In the sectional view illustrated in <FIG>, the metal column <NUM> on the second surface <NUM> of the SOC wafer <NUM> is aligned with the via <NUM> in the inductor wafer <NUM>, which is described above with respect to <FIG>. For simplicity of illustration, the thin-film magnetic layer <NUM> and the dielectric layer <NUM> are omitted in the sectional view of <FIG>.

<FIG> is a sectional view illustrating an embodiment of the SOC device of <FIG> after the SOC wafer and the inductor wafer are joined together. In the embodiment illustrated in <FIG>, the solder <NUM> connects the top portions of conductors <NUM> and <NUM> over the sidewalls <NUM> and <NUM> of the via <NUM>, respectively, and is positioned directly over the via <NUM> in the inductor wafer <NUM>. In an embodiment, the solder <NUM> may comprise a conventional solder material that melts under heat and solidifies when the temperature cools down.

<FIG> is a perspective view illustrating an embodiment of an inductor die after dicing of the joined SOC wafer and inductor wafer. In typical wafer fabrication processes, multiple identical chips may be fabricated on a single wafer with a large surface area. In an embodiment, a chip may be separated from a wafer by one of many dicing techniques known to persons skilled in the art. In the embodiment shown in <FIG>, the joined SOC wafer <NUM> and the inductor wafer <NUM> may be diced into a plurality of dies 1102a, 1102b, 1102c,. Any one of the dies 1102a, 1102b, 1102c,. includes one or more inductors and one or more other components, such as one or more capacitors, as part of an integrated or embedded voltage regulator.

<FIG> is a sectional view illustrating an embodiment of a system including a printed circuit board (PCB), an SOC package, and a voltage regulator which includes an inductor die. In <FIG>, a printed circuit board (PCB) <NUM> is provided, and an IC package <NUM> is provided on the PCB <NUM>. In an embodiment, the IC package may include one or more analog integrated circuits, one or more digital integrated circuits, or a combination thereof. In an embodiment, the IC package <NUM> may have one of various configurations known to persons skilled in the art, including but not limited to wirebond, flip-chip, or ball grid array (BGA), for example.

Referring to <FIG>, a die <NUM> that includes an inductor fabricated on an inductor wafer with through vias and joined with an SOC wafer in embodiments described above with respect to <FIG> is integrated with the IC package <NUM>. In an embodiment, the IC package <NUM> includes a package substrate <NUM>. In the embodiments, the die <NUM> is provided as a part of the circuitry for an integrated or embedded voltage regulator <NUM>, which also includes other components. For example, the voltage regulator <NUM> may include one or more additional passive components such as one or more capacitors. In <FIG>, the rest of the circuitry for the voltage regulator <NUM> are generically indicated by block <NUM>.

<FIG> is a simplified block diagram illustrating am embodiment of a system including a power management integrated circuit (PMIC) and an SOC device which includes an integrated or embedded voltage regulator and circuit using the voltage regulator. In the embodiment illustrated in <FIG>, the PMIC <NUM> is shown as a chip separate from the SOC device <NUM>. In an alternate embodiment, the PMIC <NUM> may be integrated as part of the SOC device <NUM>. Referring to <FIG>, the SOC device includes an inductor and capacitor (L & C) block <NUM>, a voltage regulator (VR) <NUM>, and one or more circuits <NUM> using the output voltage from the VR <NUM>. In an embodiment, the inductor and capacitor in the L & C block <NUM> may be integrated or embedded with the VR <NUM> on the same chip as the circuits <NUM> using the output voltage from the VR <NUM> in an SOC device.

Claim 1:
A device, comprising:
a system-on-chip, SOC, wafer (<NUM>) comprising an integrated voltage regulator;
an inductor wafer (<NUM>) having first (<NUM>) and second (<NUM>) surfaces and a plurality of vias (<NUM>, <NUM>) therethrough, the vias (<NUM>, <NUM>) forming a plurality of sidewalls (<NUM>, <NUM>, <NUM>, <NUM>) in the inductor wafer (<NUM>), the first surface (<NUM>) of the inductor wafer (<NUM>) disposed adjacent to the SOC wafer (<NUM>);
a magnetic layer (<NUM>) on at least a portion of the first surface (<NUM>) of the inductor wafer (<NUM>);
a dielectric layer (<NUM>) disposed on the magnetic layer (<NUM>) and on at least a portion of the first surface (<NUM>) of the inductor wafer (<NUM>); and
a conductive layer (<NUM>) disposed on the dielectric layer (<NUM>), on at least a portion of the first surface (<NUM>) of the inductor wafer (<NUM>), on at least a portion of the second surface (<NUM>) of the inductor wafer (<NUM>), and on at least some of the sidewalls (<NUM>, <NUM>, <NUM>, <NUM>) formed by the vias (<NUM>, <NUM>) in the inductor wafer (<NUM>), the conductive layer thereby forming an inductor having opposite ends electrically connected with other components in the voltage regulator,
wherein the SOC wafer (<NUM>) has at least two metal columns (<NUM>) on a surface thereof, facing the first surface (<NUM>) of the inductor wafer (<NUM>) and aligned with corresponding vias (<NUM>, <NUM>), for electrically connecting the conductive layer (<NUM>) to the SOC wafer (<NUM>).