Patent Description:
Generally, a display device includes a plurality of display elements and electronic elements for controlling electric signals applied to the display elements. Examples of the electronic elements include thin film transistors (TFTs), storage capacitors, and wires. Exemplary embodiments of the state of the art are shown in <CIT>, <CIT>, <CIT>, <CIT> and <CIT>.

To accurately control emission and a degree of emission by a display element, the number of TFTs that are electrically connected to each display element and the number of wires transferring an electric signal to the TFTs may be increased. Accordingly, efforts are actively made to achieve a high degree of integration of display elements and electronic elements in a display device and simultaneously reduce occurrence of defects.

Embodiments include a display device which is flexible while being resistant to damages caused by an external impact.

However, the embodiments described herein are exemplary, and the scope of the present disclosure is limited by the appended claims.

The present invention is defined in independent claim <NUM>.

The inorganic insulating layer may include a first gate insulating layer and a second gate insulating layer arranged on the first gate insulating layer, wherein the first conductive layer and the second conductive layer may be arranged on the first gate insulating layer and be spaced apart from each other by the lower valley, the second gate insulating layer may cover the first conductive layer and the second conductive layer, and the first contact hole and the second contact hole may pass through the second gate insulating layer.

The lower valley may surround at least some pixel circuits from among the plurality of pixel circuits.

The plurality of pixel circuits may include a third pixel circuit adjacent to the second pixel circuit, and the display device may further include: an additional connection wire arranged on a same layer as the connection wire, the additional connection wire connecting the second pixel circuit to the third pixel circuit; and an interlayer insulating layer arranged on the additional connection wire, the interlayer insulating layer having an upper valley in a region between the second pixel circuit and the third pixel circuit.

The additional connection wire may be formed integrally with the connection wire.

Each of the plurality of pixel circuits may include a driving thin film transistor and a storage capacitor, wherein the driving thin film transistor may overlap the storage capacitor.

The display device may further include: a bending organic material layer arranged in a bending area bent around a bending axis extending in the first direction in the peripheral region; and a fan-out wire extending in the second direction and arranged on the bending organic material layer.

The display device may further include a vertical connection wire arranged on the interlayer insulating layer and extending in a second direction crossing the first direction.

The vertical connection wire may include a driving voltage line and a data line.

The inorganic insulating layer may include a first gate insulating layer and a second gate insulating layer arranged on the first gate insulating layer, and the display device may further include: a first conductive layer arranged on the first gate insulating layer in the first pixel circuit; and a second conductive layer arranged on the first gate insulating layer in the second pixel circuit, wherein the first conductive layer and the second conductive layer may be spaced apart from each other with the first lower valley therebetween, and the first connection wire may be connected to the first conductive layer and the second conductive layer respectively through a first contact hole and a second contact hole passing through the first organic planarization layer and the first gate insulating layer.

At least one of the first lower valley and the second upper valley may surround at least some of the first to third pixel circuits.

Each of the first pixel circuit and the second pixel circuit may include a driving thin film transistor and a storage capacitor that may overlap each other, wherein an upper electrode of the storage capacitor of the first pixel circuit and an upper electrode of the storage capacitor of the second pixel circuit may be connected by a mesh connection line that is one of the first connection wire.

Each of the first pixel circuit, the second pixel circuit, and the third pixel circuit may include: an organic light-emitting element including a pixel electrode, an opposite electrode facing the pixel electrode, and an intermediate layer including an organic light-emitting layer arranged between the pixel electrode and the opposite electrode; and an encapsulation layer covering the organic light-emitting element, wherein the encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer arranged between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

At least a portion of the display area of the display device may be folded or rolled.

The embodiment of <FIG> does not form part of the present invention but is useful to understand it. The embodiments of <FIG> form part of the present invention.

As the present disclosure allows for various changes and numerous embodiments, exemplary embodiments will be illustrated in the drawings and described in detail in the written description. Effects and characteristics of present exemplary embodiments, and a method of accomplishing them will be apparent by referring to content described below in detail together with the drawings. However, the embodiments of the present disclosure may be implemented in various forms.

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings, and when descriptions are made with reference to the drawings, like or corresponding elements are given like reference numerals and repeated descriptions thereof are omitted.

It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

It will be further understood that the terms "comprises" and/or "comprising" used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, one or more intervening layers, regions, or components may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, it may be "directly connected" to the other layer, region, or component or may be "indirectly connected" to the other layer, region, or component with other layer, region, or component interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, it may be "directly electrically connected" to the other layer, region, or component or may be "indirectly electrically connected" to other layer, region, or component with other layer, region, or component interposed therebetween.

Expressions such as "at least one of" when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

<FIG> is a plan view of a display device according to an embodiment not forming part of the present invention.

Pixels PX including various display elements such as an organic light-emitting diode (OLED) may be arranged in a display area DA of a substrate <NUM>. Various wires transferring electric signals to be applied to the display area DA may be arranged in a peripheral area PA of the substrate <NUM>. Hereinafter, for convenience of description, a display device including an organic light-emitting diode is described as a display element. However, the present disclosure is not limited thereto and is applicable to various types of display devices such as a liquid crystal display device, an electrophoretic display device, and an inorganic electroluminescence (EL) display device.

<FIG> is a block diagram of a display device according to an embodiment.

The display device according to an embodiment includes a display unit <NUM> including a plurality of pixels PX, a scan driver <NUM>, a data driver <NUM>, an emission control driver <NUM>, and a controller <NUM>.

The display unit <NUM> includes a plurality of pixels PX arranged substantially in a matrix in the display area DA at intersections of a plurality of scan lines SL1 to SLn+<NUM>, a plurality of data lines DL1 to DLm, and a plurality of emission control lines EL1 to ELn. The plurality of scan lines SL1 to SLn+<NUM> and the plurality of emission control lines EL1 to ELn extend in a second direction or a row direction, and the plurality of data lines DL1 to DLm and driving voltage lines ELVDDL extend in a first direction or a column direction. In one pixel line, an n value of the plurality of scan lines SL1 to SLn+<NUM> may be different from an n value of the plurality of emission control lines EL1 to ELn.

According to one embodiment, each pixel PX is connected to three scan lines among the plurality of scan lines SL1 to SLn+<NUM>. The scan driver <NUM> generates three scan signals and transfers the scan signals to each pixel PX through the plurality of scan lines SL1 to SLn+<NUM>. For example, the scan driver <NUM> sequentially supplies scan signals to the scan lines SL2 to SLn, the previous scan lines SL1 to SLn-<NUM>, or the next scan lines SL3 to SLn+<NUM>.

An initialization voltage line IL may receive an initialization voltage from an external power source VINT and supply the same to each pixel PX.

In addition, each pixel PX is connected to one of the plurality of data lines DL1 to DLm, and connected to one of the plurality of emission control lines EL1 to ELn.

The data driver <NUM> transfers a data signal to each pixel PX through the plurality of data lines DL1 to DLm. The data signal is supplied to the corresponding pixel PX that is selected by a scan signal whenever the scan signal is supplied to the scan lines SL1 to SLn.

The emission control driver <NUM> generates an emission control signal and transfers the same to each pixel PX through the plurality of emission control lines EL1 to ELn. The emission control signal controls an emission time of the pixel PX. The emission control driver <NUM> may be omitted depending on the structure of the pixel PX.

The controller <NUM> changes a plurality of image signals IR, IG, and IB transferred from the outside to a plurality of image data signals DR, DG, and DB, and transfers the same to the data driver <NUM>. In addition, the controller <NUM> may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, generate control signals for controlling the scan driver <NUM>, the data driver <NUM>, and the emission control driver <NUM>, and respectively transfer the generated signals to the relevant drivers. That is, the controller <NUM> generates a scan driving control signal SCS controlling the scan driver <NUM>, a data driving control signal DCS controlling the data driver <NUM>, and an emission driving control signal ECS controlling the emission control driver <NUM>, and respectively transfers the generated signals to the relevant drivers.

Each of the pixels PX receives a driving power voltage ELVDD that is input from the outside, and a common power voltage ELVSS. The driving power voltage ELVDD may be a predetermined high-level voltage, and the common power voltage ELVSS may be a voltage that is lower than the driving power voltage ELVDD or a ground voltage. The driving power voltage ELVDD is supplied to each pixel PX through a driving voltage line ELVDDL.

Each of the pixels PX emits light of certain brightness based on a driving current supplied to a light-emitting element in response to a data signal transferred through the data lines DL1 to DLm.

<FIG> is an equivalent circuit diagram of one pixel of the display device shown in <FIG>.

Referring to <FIG>, each pixel PX includes a pixel circuit PC that is connected to signal lines <NUM>, <NUM>, <NUM>, and <NUM>, an initialization voltage line <NUM>, and a driving voltage line <NUM>, and a light-emitting element connected to the pixel circuit PC, in the present example, an organic light-emitting diode OLED.

The pixel circuit PC includes a plurality of thin film transistors (TFTs) T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst.

Although <FIG> illustrates a case where the signal lines <NUM>, <NUM>, <NUM>, and <NUM>, the initialization voltage line <NUM>, and the driving voltage line <NUM> are provided for each pixel PX, the present embodiment is not limited thereto. In another embodiment, at least one of the signal lines <NUM>, <NUM>, <NUM>, and <NUM>, and/or the initialization voltage line <NUM> may be shared with the adjacent pixels.

The TFTs may include a driving TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.

The signal lines include a scan line <NUM> transferring a scan signal Sn, a previous scan line <NUM> transferring a previous scan signal Sn-<NUM> to the first initialization TFT T4 and the second initialization TFT T7, an emission control line <NUM> transferring an emission control signal En to the operation control TFT T5 and the emission control TFT T6, and a data line <NUM> crossing the scan line <NUM> and transferring a data signal Dm. The driving voltage line <NUM> transfers the driving voltage ELVDD to the driving TFT T1, and the initialization voltage line <NUM> transfers the initialization voltage Vint to initialize the driving TFT T1 and a pixel electrode of the organic light-emitting diode OLED.

A driving gate electrode G1 of the driving TFT T1 is connected to a first electrode C1 of the storage capacitor Cst, a driving source electrode S1 of the driving TFT T1 is connected to the driving voltage line <NUM> via the operation control TFT T5, and a driving drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the organic light-emitting diode OLED via the emission control TFT T6. The driving TFT T1 receives a data signal Dm and supplies a driving current IOLED to the organic light-emitting diode OLED in response to a switching operation of the switching TFT T2.

A switching gate electrode G2 of the switching TFT T2 is connected to the scan line <NUM>, a switching source electrode S2 of the switching TFT T2 is connected to the data line <NUM>, and a switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1 and simultaneously connected to the lower driving voltage line <NUM> via the operation control TFT T5. The switching TFT T2 is turned on in response to a scan signal Sn transferred through the scan line <NUM> and performs a switching operation of transferring the data signal Dm transferred through the data line <NUM> to the driving source electrode S1 of the driving TFT T1.

A compensation gate electrode G3 of the compensation TFT T3 is connected to the scan line <NUM>, a compensation source electrode S3 of the compensation TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1 and simultaneously connected to the pixel electrode of the organic light-emitting diode OLED via the emission control TFT T6, and a compensation drain electrode D3 of the compensation TFT T3 is connected to the first electrode C1 of the storage capacitor Cst, the first initialization source electrode S4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on in response to the scan signal Sn transferred through the scan line <NUM> and diode-connects the driving TFT T1 by electrically connecting the driving gate electrode G1 to the driving drain electrode D1 of the driving TFT T1.

A first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scan line <NUM>, a first initialization drain electrode D4 of the first initialization TFT T4 is connected to a second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line <NUM>, and a first initialization source electrode S4 of the first initialization TFT T4 is connected to the first electrode C1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 is turned on in response to the previous scan signal Sn-<NUM> transferred through the previous scan line <NUM> and performs an initialization operation of initializing a voltage of the driving gate electrode G1 of the driving TFT T1 by transferring the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1.

An operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line <NUM>, an operation control source electrode S5 of the operation control TFT T5 is connected to the lower driving voltage line <NUM>, and an operation control drain electrode D5 of the operation control TFT T5 is connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

An emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line <NUM>, an emission control source electrode S6 of the emission control TFT T6 is connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3, and an emission control drain electrode D6 of the emission control TFT T6 is electrically connected to a second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light-emitting diode OLED.

The operation control TFT T5 and the emission control TFT T6 are simultaneously turned on in response to the emission control signal En transferred through the emission control line <NUM> to allow the driving voltage ELVDD to be transferred to the organic light-emitting diode OLED and thus allowing the driving current IOLED to flow through the organic light-emitting diode OLED.

A second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line <NUM>, the second initialization source electrode S7 of the second initialization TFT is connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the organic light-emitting diode OLED, and the second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization drain electrode D4 of the first initialization TFT T4 and the initialization voltage line <NUM>. The second initialization TFT T7 is turned on in response to the previous scan signal Sn-<NUM> transferred through the previous scan line <NUM> to initialize the pixel electrode of the organic light-emitting diode OLED.

Although <FIG> illustrates a case where the first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line <NUM>, the embodiment is not limited thereto. In another embodiment, the first initialization TFT T4 may be connected to the previous scan line <NUM> and driven in response to a previous scan signal Sn-<NUM>, and the second initialization TFT T7 may be connected to a separate signal line (for example, a next scan line Sn+<NUM>) and driven in response to a signal transferred through the separate signal line. Meanwhile, locations of the source electrodes S1 to S7 and the drain electrodes D1 to D7 shown in <FIG> may change depending on a type (p-type or n-type) of the transistors.

A specific operation of each pixel PX according to an embodiment is described below.

During an initialization period, when the previous scan signal Sn-<NUM> is supplied through the previous scan line <NUM>, the first initialization TFT T4 is turned on in response to the previous scan signal Sn-<NUM>, and the driving TFT T1 is initialized by the initialization voltage Vint supplied through the initialization voltage line <NUM>.

During a data programming period, when the scan signal Sn is supplied through the scan line <NUM>, the switching TFT T2 and the compensation TFT T3 are turned on in response to the scan signal Sn. In this case, the driving TFT T1 is diode-connected and forward-biased by the turned-on compensation TFT T3.

Then, a compensation voltage Dm+Vth that is reduced (or compensated) from the data signal Dm by a threshold voltage Vth of the driving TFT T1 (the data signal Dm is supplied through the data line <NUM> and Vth has a negative value) is applied to the driving gate electrode G1 of the driving TFT T1.

The driving voltage ELVDD and the compensation voltage Dm+Vth are applied to two opposite ends of the storage capacitor Cst, and a charge corresponding to a voltage difference between the two opposite ends is stored in the storage capacitor Cst.

During an emission period, the operation control TFT T5 and the emission control TFT T6 are turned on in response to the emission control signal En supplied through the emission control line <NUM>. The driving current IOLED corresponding to a voltage difference between a voltage of the gate electrode G1 of the driving TFT T1 and the driving voltage ELVDD is supplied to the organic light-emitting diode OLED through the emission control TFT T6.

<FIG> is an arrangement view illustrating locations of a plurality of TFTs, a storage capacitor, and two pixel circuits including first and second pixel circuits PC1 and PC2 that are disposed adjacent to each other in a display device according to an embodiment, <FIG> are arrangement views illustrating, for each layer, elements such as the plurality of TFTs, and the storage capacitor illustrated in <FIG>, and <FIG> is a cross-sectional view taken along lines I-I' and II-II' of <FIG>.

Referring to <FIG>, the display device according to an embodiment includes an inorganic insulating layer having a lower valley VA1 in a region between the first and second pixel circuits PC1 and PC2, and a first organic planarization layer <NUM> filling the lower valley VA1. In the present specification, the lower valley VA1 refers to an opening or a groove formed by removing a portion of the inorganic insulating layer.

In addition, the display device may include a horizontal connection wire <NUM> arranged on the first organic planarization layer <NUM> and extending in a first direction, and/or a vertical connection wire <NUM> arranged on the first organic planarization layer <NUM> and extending in a second direction.

In an embodiment, a barrier layer <NUM>, a buffer layer <NUM>, a first gate insulating layer <NUM>, and a second gate insulating layer <NUM> that are arranged below the horizontal connection wire <NUM> and including an inorganic material may be collectively referred to as an inorganic insulating layer. The inorganic insulating layer may include the lower valley VA1 formed as an opening or a groove in a region between adjacent pixel circuits.

<FIG> illustrates that the inorganic insulating layer has the lower valley VA1 formed as a groove. That is, the barrier layer <NUM> may continuously extend over the first pixel circuit PC1 and the second pixel circuit PC2 that are adjacent to each other. In addition, the buffer layer <NUM>, the first gate insulating layer <NUM>, and the second gate insulating layer <NUM> may respectively have openings 111a, 112a, and 113a in a region corresponding to the lower valley VA1.

Accordingly, the inorganic insulating layer including the barrier layer <NUM>, the buffer layer <NUM>, the first gate insulating layer <NUM>, and the second gate insulating layer <NUM> may be understood as having the lower valley VA1 formed as a groove in a region between the adjacent pixels. The groove may denote a trench formed in the inorganic insulating layer.

An opening of the inorganic insulating layer may denote a structure in which openings are formed in the buffer layer <NUM>, the first gate insulating layer <NUM>, and the second gate insulating layer <NUM> to expose a portion of the barrier layer <NUM>. In some embodiments, the opening of the inorganic insulating layer may extend through the barrier layer <NUM> and exposes a portion of the substrate <NUM> (see <FIG>).

The inorganic insulating layer may include various types of grooves that are different from the above groove. For example, a portion of an upper surface of the barrier layer <NUM> may be removed, and unlike this, a lower surface of the buffer layer <NUM> may not be removed. Various modifications may be made.

A width VAW1 of the lower valley VA1 of the inorganic insulating layer may be in the order of µm. For example, the width VAW1 of the lower valley VA1 of the inorganic insulating layer may have a value between about <NUM> to about <NUM>.

After the second gate insulating layer <NUM> is formed, the lower valley VA1 may be formed as an opening or a groove by performing a separate mask process and an etching process. The openings 111a, 112a, and 113a respectively of the buffer layer <NUM>, the first gate insulating layer <NUM>, and the second gate insulating layer <NUM> may be formed by the etching process. The etching process may be a dry etching process.

The first organic planarization layer <NUM> may fill the lower valley VA1 of the inorganic insulating layer. The first organic planarization layer <NUM> may be arranged over the entire regions of the first pixel circuit PC1 and the second pixel circuit PC2 while filling the lower valley VA1. The horizontal connection wire <NUM> and the vertical connection wire <NUM> are arranged on the first organic planarization layer <NUM>.

At least a portion of the lower valley VA1 of the inorganic insulating layer may be arranged between a plurality of pixel circuits. In <FIG>, the lower valley VA1 of the inorganic insulating layer surrounds the first and second pixel circuits PC1 and PC2. That is, the lower valley VA1 surrounds a circumference of the first pixel circuit PC1 and a circumference of the second pixel circuit PC2. However, the present embodiment is not limited thereto.

For example, the lower valley VA1 of the inorganic insulating layer may extend in a second direction in a region between the first pixel circuit PC1 and the second pixel circuit PC2 without entirely surrounding the first and second pixel circuits PC1 and PC2. Alternatively, the lower valley VA1 of the inorganic insulating layer may extend in the first direction in a region between a plurality of pixels. Various modifications may be made.

The lower valley VA1 of the inorganic insulating layer and the first organic planarization layer <NUM> filling the lower valley VA1 may reduce an influence of an external impact on the display device. Since the hardness of the inorganic insulating layer is higher than that of the first organic planarization layer <NUM>, a crack may occur in the inorganic insulating layer due to an external impact. When a crack occurs in the inorganic insulating layer, a probability that a crack occurs in various signal lines arranged in or on the inorganic insulating layer and a defect such as disconnection in the signal lines occurs is high.

In contrast, in the case of the display device according to the present embodiment, since the inorganic insulating layer includes the lower valley VA1 between a plurality of pixel circuits and the first organic planarization layer <NUM> fills the lower valley VA1, a probability that a crack propagates through the inorganic insulating layer is reduced. In addition, since the hardness of the first organic planarization layer <NUM> is less than that of an inorganic material layer, the first organic planarization layer <NUM> may absorb the stress caused by an external impact and thus effectively reduce concentration of the stress on the horizontal and vertical connection wires <NUM> and <NUM> arranged on the first organic planarization layer <NUM>.

In addition, since the first organic planarization layer <NUM> is arranged over the entire regions of the plurality of pixel circuits to provide a flat upper surface, a probability of defect occurrence may be drastically reduced in manufacturing the horizontal and vertical connection wires <NUM> and <NUM>.

The horizontal connection wire <NUM> and the vertical connection wire <NUM> may be arranged on the first organic planarization layer <NUM> to connect a plurality of pixel circuits to one another. The horizontal connection wire <NUM> and the vertical connection wire <NUM> may serve as wires transferring electric signals to the plurality of pixel circuits.

Hereinafter, a display device according to an embodiment is described with reference to <FIG> in detail. <FIG> illustrates a plan view of the first and second pixel circuits PC1 and PC2, and an organic light-emitting diode connected to each pixel circuit is omitted. <FIG> illustrates a schematic cross-section of pixels PX1 and PX2 in which an organic light-emitting diode OLED is connected to the first and second pixel circuits PC1 and PC2.

Each of <FIG> illustrates arrangements of a wire, an electrode, a semiconductor layer, etc. that are arranged in the same layer, and an insulating layer may be arranged between the layers illustrated in <FIG>. For example, the first gate insulating layer <NUM> (see <FIG>) may be arranged between a layer illustrated in <FIG> and a layer illustrated in <FIG>. The second gate insulating layer <NUM> (see <FIG>) may be arranged between a layer illustrated in <FIG> and a layer illustrated in <FIG>. The first organic planarization layer <NUM> (see <FIG>) may be arranged between a layer illustrated in <FIG> and a layer illustrated in <FIG>. An interlayer insulating layer <NUM> (see <FIG>) may be arranged between a layer illustrated in <FIG> and a layer illustrated in <FIG>. The layers illustrated in <FIG> may be electrically connected to one another through one or more contact holes defined in at least some of the above-described insulating layers.

Referring to <FIG>, <FIG>, and <FIG>, semiconductor layers AS1 to AS7 respectively of the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 are arranged in the same layer and may include the same material. For example, the semiconductor layers AS1 to AS7 may include polycrystalline silicon.

The semiconductor layers AS1 to AS7 are arranged on the buffer layer <NUM> (see <FIG>) arranged over the substrate <NUM>. The substrate <NUM> may include a glass material, a metal material, or a plastic material such as polyethylene terephthalate, polyethylene naphthalate, and polyimide. The buffer layer <NUM> may include an oxide layer such as SiOx and/or a nitride layer such as SiNx.

The substrate <NUM> may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. In the case where the substrate <NUM> includes a flexible or bendable material, the substrate <NUM> may include a polymer resin such as polyethersulphone, polyacrylate, polyetherimide, polyethyelene napthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate <NUM> may have a single-layered or multi-layered structure including one or more of the above-listed materials. The multi-layered structure may further include an inorganic layer. In an embodiment, the substrate <NUM> may have a stacked structure of an organic material/inorganic material/organic material.

The barrier layer <NUM> may be further arranged between the substrate <NUM> and the buffer layer <NUM>. The barrier layer <NUM> may prevent or reduce penetration of impurities from the substrate <NUM>, etc. into the semiconductor layers AS1 to AS7. The barrier layer <NUM> may include an inorganic material, an organic material, or an organic/inorganic composite material, and may include a single or multi-layered structure of an inorganic material and an organic material.

The buffer layer <NUM> may increase planarization of an upper surface of the substrate <NUM> and include an inorganic material such as a silicon oxide, a silicon nitride, and/or a silicon oxynitride.

A driving semiconductor layer (i.e., the semiconductor layer AS1) of the driving TFT T1, a switching semiconductor layer (i.e., the semiconductor layer AS2) of the switching TFT T2, a compensation semiconductor layer (i.e., the semiconductor layer AS3) of the compensation TFT T3, a first initialization semiconductor layer (i.e., the semiconductor layer AS4) of the first initialization TFT T4, an operation control semiconductor layer (i.e., the semiconductor layer AS5) of the operation control TFT T5, an emission control semiconductor layer (i.e., the semiconductor layer AS6) of the emission control TFT T6, and a second initialization semiconductor layer (i.e., the semiconductor layer AS7) of the second initialization TFT T7 may be connected to one another and bent in various shapes.

Each of the semiconductor layers AS1 to AS7 may include a channel region, and a source region and a drain region respectively at opposite sides of the channel region. For example, the source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and the drain region respectively correspond to a source electrode and a drain electrode. Hereinafter, terms "a source region" and "a drain region" are respectively used instead of a source electrode or a drain electrode.

The driving semiconductor layer, i.e., the semiconductor layer AS1, includes a driving channel region A1, a driving source region S1 and a driving drain region D1 that are arranged respectively at opposite sides of the driving channel region A1. The semiconductor layer AS1 may have a bent shape and thus the driving channel region A1 may be formed longer than the other channel regions A2 to A7. For example, the semiconductor layer AS1 may form a long channel in a narrow space by having a shape bent a plurality of number of times such as an omega shape or the letter "S". Since the driving channel region A1 is formed to be long, a driving range of a gate voltage applied to the driving gate electrode G1 is widened and thus a gray scale of light emitted from an organic light-emitting diode OLED may be controlled more delicately, and the display quality may improve.

The switching semiconductor layer, i.e., the semiconductor layer AS2, includes a switching channel region A2, and a switching source region S2 and a switching drain region D2 that are arranged respectively at opposite sides of the switching channel region A2. The switching drain region D2 is connected to the driving source region S1.

The compensation semiconductor layer, i.e., the semiconductor layer AS3, includes compensation channel regions A3a and A3c, and a compensation source region S3 and a compensation drain region D3 that are arranged respectively at opposite sides of the compensation channel regions A3a and A3c. The compensation TFT T3 formed in the semiconductor layer AS3 includes dual transistors and the two compensation channel regions A3a and A3c. A region A3b between the compensation channel regions A3a and A3c is a region doped with impurities and locally serves as a source region of one of the dual transistors and simultaneously serves as a drain region of the other dual transistor.

The first initialization semiconductor layer, i.e., the semiconductor layer AS4, includes first initialization channel regions A4a and A4c, and a first initialization source region S4 and a first initialization drain region D4 that are arranged respectively at opposite sides of the first initialization channel regions A4a and A4c. The first initialization TFT T4 formed in the semiconductor layer AS4 includes dual transistors and the two first initialization channel regions A4a and A4c. A region A4b between the first initialization channel regions A4a and A4c is a region doped with impurities and locally serves as a source region of one of the dual transistors and simultaneously serves as a drain region of the other dual transistor.

The operation control semiconductor layer, i.e., the semiconductor layer AS5, includes an operation control channel region A5, and an operation control source region S5 and an operation control drain region D5 that are arranged respectively at opposite sides of the operation control channel region A5. The operation control drain region D5 may be connected to the driving source region S1.

The emission control semiconductor layer, i.e., the semiconductor layer AS6, includes an emission control channel region A6, and an emission control source region S6 and an emission control drain region D6 that are arranged respectively at opposite sides of the emission control channel region A6. The emission control source region S6 may be connected to the driving drain region D1.

The second initialization semiconductor layer, i.e., the semiconductor layer AS7, includes a second initialization channel region A7, and a second initialization source region S7 and a second initialization drain region D7 that are arranged respectively at opposite sides of the second initialization channel region A7.

The first gate insulating layer <NUM> is arranged on the semiconductor layers AS1 to AS7. The first gate insulating layer <NUM> may include an inorganic material including an oxide or a nitride. For example, the first gate insulating layer <NUM> may include SiO<NUM>, SiNx, SiON, Al<NUM>O<NUM>, TiO<NUM>, Ta<NUM>O<NUM>, HfO<NUM>, or ZnO<NUM>.

In the present embodiment, the semiconductor layers AS1 to AS7 of adjacent pixel circuits are separated from one another. For example, the semiconductor layers AS1 to AS7 of the first pixel circuit PC1 are spaced apart from the semiconductor layers AS1 to AS7 of the second pixel circuit PC2.

Referring to <FIG>, <FIG>, and <FIG>, the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, and the driving gate electrode G1 are arranged over the first gate insulating layer <NUM>. The scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, and the driving gate electrode G1 are arranged in the same layer, and may include the same material. For example, the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, and the driving gate electrode G1 may include Mo, Cu, and Ti, and include a single layer or a multi-layer.

The driving gate electrode G1 is an island-type electrode and overlaps the driving channel region A1 of the semiconductor layer AS1. The driving gate electrode G1 serves as not only the gate electrode of the driving TFT T1 but also a first electrode C1 of the storage capacitor Cst. That is, the driving gate electrode G1 and the first electrode C1 may be understood as a single body.

Portions or protruding parts of the scan line <NUM>, the previous scan line <NUM>, and the emission control line <NUM> correspond to the gate electrodes of the TFTs T2 to T7.

Regions of the scan line <NUM> overlapping the switching channel region A2 and the compensation channel regions A3a and A3c respectively correspond to the switching gate electrode G2 and compensation gate electrodes G3a and G3b of the compensation gate electrode G3. Regions of the previous scan line <NUM> overlapping the first initialization channel regions A4a and A4c and the second initialization channel region A7 respectively correspond to first initialization gate electrodes G4a and G4b of the first initialization gate electrode G4, and the second initialization gate electrode G7. Regions of the emission control line <NUM> overlapping the operation control channel region A5 and the emission control channel region A6 respectively correspond to the operation control gate electrode G5 and the emission control gate electrode G6.

The compensation gate electrodes G3a and G3b are dual gate electrodes including the first compensation gate electrode G3a and the second compensation gate electrode G3b and may prevent or reduce occurrence of a leakage current.

In the present embodiment, the scan lines <NUM>, the previous scan lines <NUM>, the emission control lines <NUM>, and the driving gate electrodes G1 of adjacent pixel circuits are separated from one another. For example, the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, and the driving gate electrode G1 of the first pixel circuit PC1 are respectively spaced apart from the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, and the driving gate electrode G1 of the second pixel circuit PC2.

Here, the scan line <NUM>, the previous scan line <NUM>, and the emission control line <NUM> of the first pixel circuit PC1 may be respectively connected afterward to the scan line <NUM>, the previous scan line <NUM>, and the emission control line <NUM> of the second pixel circuit PC2 by the horizontal connection wire <NUM> arranged in a different layer.

The second gate insulating layer <NUM> is arranged over the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, and the driving gate electrode G1. The second gate insulating layer <NUM> may include an inorganic material including an oxide or a nitride. For example, the second gate insulating layer <NUM> may include SiO<NUM>, SiNx, SiON, Al<NUM>O<NUM>, TiO<NUM>, Ta<NUM>O<NUM>, HfO<NUM>, or ZnO<NUM>.

Referring to <FIG>, <FIG>, and <FIG>, a second electrode C2 of the storage capacitor Cst and the initialization voltage line <NUM> may be arranged on the second gate insulating layer <NUM>.

The second electrode C2 of the storage capacitor Cst and the initialization voltage line <NUM> are arranged in the same layer and may include the same material. For example, the second electrode C2 of the storage capacitor Cst and the initialization voltage line <NUM> may include a conductive material including Mo, Cu, and Ti, and include a single layer or a multi-layer including one or more of the above-listed materials.

In the present embodiment, the second electrodes C2 of the storage capacitors Cst and the initialization voltage lines <NUM> of the first and second pixel circuits PC1 and PC2 are separated from each other. For example, the second electrode C2 of the storage capacitor Cst of the first pixel circuit PC1 is spaced apart from the second electrode C2 of the storage capacitor Cst of the second pixel circuit PC2, and the initialization voltage line <NUM> of the first pixel circuit PC1 is spaced apart from the initialization voltage line <NUM> of the second pixel circuit PC2.

The first organic planarization layer <NUM> is arranged on the second electrode C2 of the storage capacitor Cst and the initialization voltage line <NUM>. The first organic planarization layer <NUM> may be arranged on the second electrode C2 of the storage capacitor Cst and the initialization voltage line <NUM> while filling the lower valley VA1 formed in the inorganic insulating layer.

The first organic planarization layer <NUM> may include one or more selected from the group consisting of acryl, methacrylic, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. The first organic planarization layer <NUM> may function as a protective film covering TFTs T1 to T7 and may serve to planarize upper portions thereof. The first organic planarization layer <NUM> may be a single layer or a multilayer.

Referring to <FIG>, <FIG>, and <FIG>, the horizontal connection wire <NUM> extending in the first direction is arranged on the first organic planarization layer <NUM>. The horizontal connection wire <NUM> extends from the first pixel circuit PC1 to the second pixel circuit PC2 and connects the first pixel circuit PC1 to the second pixel circuit PC2. The horizontal connection wire <NUM> may connect the pixels that are arranged in the first direction.

In the present embodiment, the semiconductor layers AS1 to AS7 arranged below the horizontal connection wire <NUM>, and conductive layers such as the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, the initialization voltage line <NUM>, and the first electrode C1 and the second electrode C2 of the storage capacitor Cst are separated for each pixel circuit. Accordingly, propagation of stress that may occur from one pixel circuit to another pixel circuit may be prevented. Since the horizontal connection wire <NUM> may include a material having a high elongation property, a defect caused by stress may be reduced.

The horizontal connection wire <NUM> may include an emission control connection line <NUM>, a mesh connection line <NUM>, a scan connection line <NUM>, a previous scan connection line <NUM>, and an initialization voltage connection line <NUM>.

The emission control connection line <NUM> connects the emission control line <NUM> of the first pixel circuit PC1 to the emission control line <NUM> of the second pixel circuit PC2 through contact holes CNT1a and CNT1b passing through the first organic planarization layer <NUM> and the second gate insulating layer <NUM>. The emission control connection line <NUM> may overlap the emission control line <NUM> of the first pixel circuit PC1 and the emission control line <NUM> of the second pixel circuit PC2 and extend in the first direction.

The mesh connection line <NUM> connects the second electrode C2 of the first pixel circuit PC1 to the second electrode C2 of the second pixel circuit PC2 through contact holes CNT3a and CNT2b passing through the first organic planarization layer <NUM>. Since the second electrode C2 of the storage capacitor Cst is connected to the driving voltage line <NUM> and thus receives a driving voltage, the mesh connection line <NUM> may transfer the driving voltage to the pixels arranged in the first direction. Due to the mesh connection line <NUM>, a driving voltage line having a mesh structure may be formed without a separate driving voltage line extending in the first direction. Therefore, a space required for the storage capacitor Cst may be reduced, and thus a high-quality display device may be obtained.

The scan connection line <NUM> connects the scan line <NUM> of the first pixel circuit PC1 to the scan line <NUM> of the second pixel circuit PC2 through contact holes CNT4a and CNT4b passing through the first organic planarization layer <NUM> and the second gate insulating layer <NUM>. The scan connection line <NUM> may overlap the scan line <NUM> of the first pixel circuit PC1 and the scan line <NUM> of the second pixel circuit PC2 and extend in the first direction.

The previous scan connection line <NUM> connects the previous scan line <NUM> of the first pixel circuit PC1 to the previous scan line <NUM> of the second pixel circuit PC2 through contact holes CNT5a and CNT5b passing through the first organic planarization layer <NUM> and the second gate insulating layer <NUM>. The previous scan connection line <NUM> may overlap the previous scan line <NUM> of the first pixel circuit PC1 and the previous scan line <NUM> of the second pixel circuit PC2 and extend in the first direction.

The initialization voltage connection line <NUM> connects the initialization voltage line <NUM> of the first pixel circuit PC1 to the initialization voltage line <NUM> of the second pixel circuit PC2 through contact holes CNT6a and CNT6b passing through the first organic planarization layer <NUM>. The initialization voltage connection line <NUM> may overlap the initialization voltage line <NUM> of the first pixel circuit PC1 and the initialization voltage line <NUM> of the second pixel circuit PC2 and extend in the first direction.

As described above, since the horizontal connection wire <NUM> connects the first pixel circuit PC1 to the second pixel circuit PC2, the horizontal connection wire <NUM> may supply electric signals to the connected pixels.

The interlayer insulating layer <NUM> may be arranged on the horizontal connection wire <NUM>. The interlayer insulating layer <NUM> may include an inorganic material including an oxide or a nitride. For example, the interlayer insulating layer <NUM> may include SiO<NUM>, SiNx, SiON, Al<NUM>O<NUM>, TiO<NUM>, Ta<NUM>O<NUM>, HfO<NUM>, or ZnO<NUM>.

Referring to <FIG>, <FIG>, and <FIG>, the vertical connection wire <NUM> extending in the second direction is arranged on the interlayer insulating layer <NUM>. The vertical connection wire <NUM> is insulated from the horizontal connection wire <NUM> by the interlayer insulating layer <NUM>. The vertical connection wire <NUM> may include the data line <NUM>, the driving voltage line <NUM>, a first node connection line <NUM>, a second node connection line <NUM>, and an intermediate connection line <NUM>.

The data line <NUM>, the driving voltage line <NUM>, the first node connection line <NUM>, the second node connection line <NUM>, and the intermediate connection line <NUM> are arranged in the same layer and may include the same material. For example, the data line <NUM>, the driving voltage line <NUM>, the first node connection line <NUM>, the second node connection line <NUM>, and the intermediate connection line <NUM> may include a conductive material having a high elongation property.

For example, the data line <NUM>, the driving voltage line <NUM>, the first node connection line <NUM>, the second node connection line <NUM>, and the intermediate connection line <NUM> may include aluminum. In an embodiment, the data line <NUM>, the driving voltage line <NUM>, the first node connection line <NUM>, the second node connection line <NUM>, and the intermediate connection line <NUM> may have a multi-layered structure of Ti/Al/Ti.

The data line <NUM> is connected to the switching source region S2 of the switching TFT T2 through a contact hole CNT7 passing through the interlayer insulating layer <NUM>, the first organic planarization layer <NUM>, the second gate insulating layer <NUM>, and the first gate insulating layer <NUM>. The data line <NUM> may connect the pixel circuits arranged in the second direction.

The driving voltage line <NUM> is connected to the operation control source region S5 of the operation control TFT T5 through a contact hole CNT8 passing through the interlayer insulating layer <NUM>, the first organic planarization layer <NUM>, the second gate insulating layer <NUM>, and the first gate insulating layer <NUM>.

In addition, the driving voltage line <NUM> is connected to the second electrode C2 of the storage capacitor Cst through a contact hole CNT9 passing through the interlayer insulating layer <NUM> and the first organic planarization layer <NUM>. The driving voltage line <NUM> may connect the pixel circuits arranged in the second direction.

The first node connection line <NUM> transfers the initialization voltage Vint that initializes the driving TFT T1 and a pixel electrode <NUM> of the organic light-emitting diode OLED. The first node connection line <NUM> is connected to the first and second initialization TFTs T4 and T7 through a contact hole CNT11 passing through the interlayer insulating layer <NUM>, the first organic planarization layer <NUM>, the second gate insulating layer <NUM>, and the first gate insulating layer <NUM>, and is also connected to the initialization voltage line <NUM> through a contact hole CNT10 passing through the interlayer insulating layer <NUM> and the first organic planarization layer <NUM>.

The second node connection line <NUM> connects the driving gate electrode G1 to the compensation drain region D3 of the compensation TFT T3 through contact holes CNT12 and CNT13. The driving gate electrode G1 that is of an island type may be electrically connected to the compensation TFT T3 by the second node connection line <NUM>.

The intermediate connection line <NUM> may be connected to the second initialization source region S7 of the second initialization TFT T7 through a contact hole CNT14 passing through the interlayer insulating layer <NUM>, the first organic planarization layer <NUM>, the second gate insulating layer <NUM>, and the first gate insulating layer <NUM>. The intermediate connection line <NUM> may be connected to the emission control drain region D6 of the emission control TFT T6 through a contact hole CNT15 passing through the interlayer insulating layer <NUM>, the first organic planarization layer <NUM>, the second gate insulating layer <NUM>, and the first gate insulating layer <NUM>.

The data line <NUM>, the driving voltage line <NUM>, and the intermediate connection line <NUM> may connect adjacent pixels in the second direction.

A second organic planarization layer <NUM> is arranged on the data line <NUM>, the driving voltage line <NUM>, the first node connection line <NUM>, the second node connection line <NUM>, and the intermediate connection line <NUM>. The second organic planarization layer <NUM> may include one or more selected from the group consisting of acryl, methacrylic, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. The second organic planarization layer <NUM> may be a single layer or a multilayer.

Referring to <FIG>, the first organic planarization layer <NUM> is arranged over the entire regions of the first pixel circuit PC1 and the second pixel circuit PC2 while filling the lower valley VA1 of the inorganic insulating layer between the first pixel circuit PC1 and the second pixel circuit PC2.

The first organic planarization layer <NUM> may include one or more selected from the group consisting of acryl, methacrylic, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. In some embodiments, the first organic planarization layer <NUM> may include a polyimide, phenylene, or siloxane-based high heat resistant organic material. Such a material may be suitable for forming a contact hole in the first organic planarization layer <NUM>. However, the present disclosure is not limited thereto.

The inorganic insulating layer has a higher hardness than the first organic planarization layer <NUM>, but may be vulnerable to cracks caused by stress. The first organic planarization layer <NUM> may absorb the stress due to its organic material characteristics.

In the present embodiment, the inorganic insulating layer has a lower valley VA1 formed by removing a portion thereof, and the first organic planarization layer <NUM> fills the lower valley VA1, and thus, stress that may be applied to the display device, or a crack caused by the stress may be prevented from propagating between the first and second pixel circuits PC1 and PC2.

Since the first organic planarization layer <NUM> is arranged over the entire regions of the first and second pixel circuits PC1 and PC2 to provide a flat upper surface, a defect that may occur when forming the horizontal connection wire <NUM> on the first organic planarization layer <NUM> may be reduced, and a coupling that may occur between the horizontal connection wire <NUM> and the vertical connection wire <NUM> that is arranged above the horizontal connection wires <NUM> may be reduced.

If an upper surface of the first organic planarization layer <NUM> is not flat, for example, if a portion of the upper surface of the first organic planarization layer <NUM> is convex, the horizontal connection wire <NUM> may be formed to have an inconsistent width due to the non-flat surface of the first organic planarization layer <NUM> in the process of forming the horizontal connection wire <NUM> by patterning a conductive layer. In addition, if the horizontal connection wire <NUM> is convex along the shape of the first organic planarization layer <NUM>, a coupling may occur between the horizontal connection wire <NUM> and the vertical connection wire <NUM> that is arranged above the horizontal connection wire <NUM>. Therefore, it is beneficial to form the upper surface of the first organic planarization layer <NUM> to be flat.

The horizontal connection wire <NUM> is arranged on the first organic planarization layer <NUM>. The horizontal connection wire <NUM> overlaps the lower valley VA1 that is arranged in a region between the first pixel circuit PC1 and the second pixel circuit PC2.

One end of the mesh connection line <NUM> is connected to the second electrode C2 of the storage capacitor Cst arranged in the first pixel circuit PC1 by the contact hole CNT3a passing through the first organic planarization layer <NUM>.

The other end of the mesh connection line <NUM> is connected to the second electrode C2 of the storage capacitor Cst arranged in the second pixel circuit PC2 by the contact hole CNT2b passing through the first organic planarization layer <NUM>.

The organic light-emitting diode OLED may be arranged on the second organic planarization layer <NUM>. The organic light-emitting diode OLED includes the pixel electrode <NUM>, an opposite electrode <NUM>, and an intermediate layer <NUM> that is arranged between the pixel electrode <NUM> and the opposite electrode <NUM> and includes an emission layer.

The pixel electrode <NUM> is connected to the intermediate connection line <NUM> through a contact hole CNT16 (see <FIG>) defined in the second organic planarization layer <NUM>, and is connected to the emission control drain region D6 of the emission control TFT T6 by the intermediate connection line <NUM>.

The pixel electrode <NUM> may be a reflective electrode including a reflective layer. For example, the reflective layer may include at least one selected from the group consisting of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), and chrome (Cr). A transparent or translucent electrode layer that includes at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In<NUM>O<NUM>), indium gallium oxide (IGO), and aluminum zinc oxide (AZO), may be arranged on the reflective layer.

According to an embodiment, the pixel electrode <NUM> may include three layers of ITO/Ag/ITO.

A pixel-defining layer <NUM> may be arranged over the second organic planarization layer <NUM>. The pixel-defining layer <NUM> defines a pixel by an opening corresponding to each sub-pixel, that is, an opening exposing a central portion of the pixel electrode <NUM>. In addition, the pixel-defining layer <NUM> prevents arcs, etc. from occurring at an edge of the pixel electrode <NUM> by increasing a distance between edges of the pixel electrode <NUM> and the opposite electrode <NUM> over the pixel electrode <NUM>. The pixel-defining layer <NUM> may include, for example, an organic material such as polyimide or hexamethyldisiloxane.

The intermediate layer <NUM> of the organic light-emitting diode OLED may include a material having a low molecular weight or a polymer material. In the case where the intermediate layer <NUM> includes a low molecular weight material, the intermediate layer <NUM> may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc. are stacked in a single or a composite configuration, and may include various organic materials such as copper phthalocyanine (CuPc), N,N'-Di(naphthalene-<NUM>-yl)-N,N'-diphenyl-benzidine (NPB), and tris-<NUM>-hydroxyquinoline aluminum (Alq3). These layers may be formed by vacuum evaporation.

In the case where the intermediate layer <NUM> includes a polymer material, the intermediate layer <NUM> may generally have a structure including an HTL and an EML. In this case, the HTL may include PEDOT, and the EML may include a polymer material such as a polyphenylene vinylene (PPV)-based material and a polyfluorene-based material. The intermediate layer <NUM> may be formed by screen printing, ink-jet printing, laser induced thermal imaging (LITI), etc..

The structure of the intermediate layer <NUM> is not limited to the above-described structure and may have various structures. For example, the intermediate layer <NUM> may include a layer having a single body over a plurality of pixel electrodes <NUM> or may include a layer that is patterned to respectively correspond to the plurality of pixel electrodes <NUM>.

The opposite electrode <NUM> is arranged over the display area DA. As illustrated in <FIG>, the opposite electrode <NUM> may be arranged to cover the display area DA. That is, the opposite electrode <NUM> may be formed as a single body over a plurality of organic light-emitting diodes OLED to correspond to the plurality of pixel electrodes <NUM>. The opposite electrode <NUM> may be a (semi) transparent electrode. For example, the opposite electrode <NUM> may include one or more selected from Ag, Al, Mg, Li, Ca, Cu, LiF/Ca, LiF/Al, MgAg, and CaAg, and may include a thin film having a thickness of several to several tens of nm to transmit light.

Since the organic light-emitting diode OLED may be easily damaged by external moisture or oxygen, an encapsulation layer <NUM> may cover and protect the organic light-emitting diode OLED. The encapsulation layer <NUM> may cover the display area DA and extend to outside of the display area DA. The encapsulation layer <NUM> may include a first inorganic encapsulation layer <NUM>, an organic encapsulation layer <NUM>, and a second inorganic encapsulation layer <NUM>.

The first inorganic encapsulation layer <NUM> may cover the opposite electrode <NUM> and include ceramic, a metal oxide, a metal nitride, a metal carbide, a metal oxynitride, In<NUM>O<NUM>, SnO<NUM>, ITO, a silicon oxide, a silicon nitride, and/or a silicon oxynitride. In some embodiments, other layers such as a capping layer may be arranged between the first inorganic encapsulation layer <NUM> and the opposite electrode <NUM>. Since the first inorganic encapsulation layer <NUM> is arranged to cover the opposite electrode <NUM> that is not flat, an upper surface of the first inorganic encapsulation layer <NUM> is not planarized.

The organic encapsulation layer <NUM> covers the first inorganic encapsulation layer <NUM>. Unlike the first inorganic encapsulation layer <NUM>, an upper surface of the organic encapsulation layer <NUM> may be made substantially flat. Specifically, an upper surface of a portion of the organic encapsulation layer <NUM> corresponding to the display area DA may be made substantially flat. The organic encapsulation layer <NUM> may include at least one selected from the group consisting of acryl, methacrylic, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

The second inorganic encapsulation layer <NUM> may cover the organic encapsulation layer <NUM> and include ceramic, a metal oxide, a metal nitride, a metal carbide, a metal oxynitride, In<NUM>O<NUM>, SnO<NUM>, ITO, a silicon oxide, a silicon nitride, and/or a silicon oxynitride.

Since the encapsulation layer <NUM> has a multi-layered structure including the first inorganic encapsulation layer <NUM>, the organic encapsulation layer <NUM>, and the second inorganic encapsulation layer <NUM>, even though a crack occurs in the encapsulation layer <NUM>, the encapsulation layer <NUM> may prevent the crack from being connected between the first inorganic encapsulation layer <NUM> and the organic encapsulation layer <NUM>, or between the organic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> through the above-described multi-layered structure. The encapsulation layer <NUM> may also prevent or reduce forming of a path through which external moisture or oxygen penetrates into the display area DA.

Although not shown, a spacer for preventing a damage of a mask may be further provided on the pixel-defining layer <NUM>. In addition, various functional layers such as a polarization layer for reducing external light reflection, a black matrix, a color filter, and/or a touchscreen layer including a touch electrode may be provided on the encapsulation layer <NUM>.

<FIG> is a portion of a cross-sectional view taken along line III-III' of <FIG>, and in <FIG>, layers arranged on the previous scan connection line <NUM> are omitted.

Referring to <FIG>, the display device according to the present embodiment includes the inorganic insulating layer having the lower valley VA1 in a region between the first pixel circuit PC1 and the second pixel circuit PC2 that are adjacent to each other, and the first organic planarization layer <NUM> that is arranged over the entire regions of the first pixel circuit PC1 and the second pixel circuit PC2 while filling the lower valley VA1.

The previous scan connection line <NUM> that is one of the horizontal connection lines <NUM> is arranged on the first organic planarization layer <NUM> and connected to the previous scan line 122a of the first pixel circuit PC1 through the contact hole CNT5a of the first pixel circuit PC1, and is connected to the previous scan line 122b of the second pixel circuit PC2 through the contact hole CNT5b of the second pixel circuit PC2.

The previous scan line 122a of the first pixel circuit PC1 and the previous scan line 122b of the second pixel circuit PC1 are spaced apart from each other by the lower valley VA1, but are connected to each other by the previous scan connection line <NUM>. The previous scan lines 122a and 122b may be arranged on the first gate insulating layer <NUM>, and the semiconductor layer AS4 of the first initialization TFT T4 (see <FIG>) may be arranged under the first gate insulating layer <NUM>. A portion of each of the previous scan lines 122a and 122b may function as a gate electrode of the first initialization TFT T4. The second gate insulating layer <NUM> may be arranged on the previous scan lines 122a and 122b.

The contact hole CNT5a of the first pixel circuit PC1 and the contact hole CNT5b of the second pixel circuit PC2 pass through the first organic planarization layer <NUM> and the second gate insulating layer <NUM>, and the previous scan connection line <NUM> may be connected to the previous scan lines 122a and 122b through the contact holes CNT5a and CNT5b.

<FIG> is a cross-sectional view of a portion of a display device according to an embodiment of the present invention. Specifically, <FIG> is a cross-sectional view illustrating a location corresponding to line I-I' and II-II of <FIG>. In <FIG>, same reference numerals as those shown in <FIG> denote same elements.

Referring to <FIG>, the display device according to the present embodiment includes an inorganic insulating layer having a lower valley VA1 in a region between a first pixel circuit PC1 and a second pixel circuit PC2 that are adjacent to each other, and a first organic planarization layer <NUM> that is arranged over the entire regions of the first pixel circuit PC1 and the second pixel circuit PC2 while filling the lower valley VA1.

In addition, the display device includes a horizontal connection wire <NUM> that is arranged on the first organic planarization layer <NUM> and connecting the first pixel circuit PC1 to the second pixel circuit PC2, and the horizontal connection wire <NUM> is connected to a second electrode C2 of the first pixel circuit PC1 through a contact hole CNT3a passing through the first organic planarization layer <NUM> and is connected to a second electrode C2 of the second pixel circuit PC2 through a contact hole CNT2b.

In the present embodiment, the display device includes an interlayer insulating layer <NUM> that is arranged on the horizontal connection wire <NUM>, and the interlayer insulating layer <NUM> is provided with an upper valley VA2. The upper valley VA2 is formed as an opening or a groove in a region between the first pixel circuit PC1 and the second pixel circuit PC2. The upper valley VA2 is filled with a second organic planarization layer <NUM>. Accordingly, a portion of the horizontal connection wire <NUM> is arranged between the first organic planarization layer <NUM> and the second organic planarization layer <NUM>.

The upper valley VA2 may overlap at least a portion of the lower valley VA1. However, the present disclosure is not limited thereto. The upper valley VA2 and the lower valley VA1 may be arranged in different regions. Various modifications may be made.

Since the upper valley VA2 is formed in the interlayer insulating layer <NUM>, stress applied to the interlayer insulating layer <NUM> that is provided as an inorganic insulating layer may be prevented from propagating between the first and second pixel circuits PC1 and PC2. In addition, since the second organic planarization layer <NUM> is arranged in the upper valley VA2, the second organic planarization layer <NUM> may absorb stress applied to the display device.

Since, in a region between a plurality of pixel circuits, the first organic planarization layer <NUM> is arranged under the horizontal connection wire <NUM> and the second organic planarization layer <NUM> is arranged on the horizontal connection wire <NUM>, the horizontal connection wire <NUM> may be resistant to damages such as cracks that may be cause by external stress.

The first organic planarization layer <NUM> and the second organic planarization layer <NUM> may include one or more selected from the group consisting of acryl, methacrylic, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

<FIG> and <FIG> are cross-sectional views of portions of display devices according to other embodiments of the present invention. In <FIG> and <FIG>, same reference numerals as those shown in <FIG> denote same elements.

Referring to <FIG>, the shape of a lower valley VA1 between a first pixel circuit PC1 and a second pixel circuit PC2 may be different from the shape of the lower valley VA1 shown in <FIG>.

In <FIG>, a barrier layer <NUM> and a buffer layer <NUM> in an inorganic insulating layer may be continuously arranged over a plurality of pixels. In addition, a first gate insulating layer <NUM> and a second gate insulating layer <NUM> may respectively have openings 112a and 113a in a region between adjacent pixels. Accordingly, the inorganic insulating layer including the barrier layer <NUM>, the buffer layer <NUM>, the first gate insulating layer <NUM>, and the second gate insulating layer <NUM> may be understood as having the lower valley VA1 in a region between the first pixel circuit PC1 and the second pixel circuit PC2.

The lower valley VA1 may be formed by using separate mask process and etching process after the second gate insulating layer <NUM> is formed. Accordingly, the shape of the lower valley VA1 of the inorganic insulating layer may be selected.

A structure shown in <FIG> may be formed by an etching process of forming the openings 112a and 113a respectively of the first gate insulating layer <NUM> and the second gate insulating layer <NUM>.

The shape of the lower valley VA1 of the inorganic insulating layer may be varied. For example, the barrier layer <NUM>, the buffer layer <NUM>, and the first gate insulating layer <NUM> may be continuously formed over the first pixel circuit PC1 and the second pixel circuit PC2, only the second gate insulating layer <NUM> may have the opening 113a, or only a portion of the second gate insulating layer <NUM> may be removed. Various modifications may be made.

The first organic planarization layer <NUM> does fill the lower valley VA1, and the horizontal connection wire <NUM> connecting adjacent pixels may be arranged on the first organic planarization layer <NUM>.

Referring to <FIG>, the inorganic insulating layer does include the lower valley VA1 that is formed by forming an opening in a region between a plurality of pixel circuits, that is, the first pixel circuit PC1 and the second pixel circuit PC2. That is, the barrier layer <NUM>, the buffer layer <NUM>, the first gate insulating layer <NUM>, and the second gate insulating layer <NUM> in the inorganic insulating layer may respectively have openings 101a, 111a, 112a, and 113a in a region between the first pixel circuit PC1 and the second pixel circuit PC2.

A width of each of the openings may be several µm. The openings may be formed by performing separate mask processes and dry etching after the second gate insulating layer <NUM> is formed. Accordingly, the lower valley VA1 of the inorganic insulating layer may have a shape of an opening or groove.

The first organic planarization layer <NUM> fills the openings, and the horizontal connection wire <NUM> connecting adjacent pixels may be arranged on the first organic planarization layer <NUM>.

<FIG> is a cross-sectional view of a portion of a display device according to another embodiment of the present invention. In <FIG>, same reference numerals as those shown in <FIG> denote same elements.

Referring to <FIG>, the display device includes a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 that are sequentially arranged in a first direction.

In the present embodiment, the display device includes an inorganic insulating layer having a lower valley VA1 in a region between the first pixel circuit PC1 and the second pixel circuit PC2 that are adjacent to each other, and a first organic planarization layer <NUM> arranged over the entire regions of the first pixel circuit PC1 and the second pixel circuit PC2.

The display device includes a first connection wire 140a that is arranged on the first organic planarization layer <NUM> and connecting the first pixel circuit PC1 to the second pixel circuit PC2.

An interlayer insulating layer <NUM> having an upper valley VA2 is provided in a region between the second pixel circuit PC2 and the third pixel circuit PC3, and the upper valley VA2 is filled with a second organic planarization layer <NUM>. A second connection wire 140b is arranged under the interlayer insulating layer <NUM> and partially overlaps the upper valley VA2 and connects the second pixel circuit PC2 to the third pixel circuit PC3.

In the present embodiment, the lower valley VA1 and the upper valley VA2 may not overlap each other in the entire area or a portion of the area of the display device. The flexibility of the display device may be obtained by the provision of the lower valley VA1 and the upper valley VA2, but the relative stiffness of the display device may be lowered. When the lower valley VA1 and the upper valley VA2 may be arranged in a non-overlapping manner in at least some of regions between a plurality of pixel circuits as shown in <FIG>, thereby obtaining the desired flexibility and stiffness of the display device.

In some embodiments, the lower valley VA1 and the upper valley VA2 may be arranged in a crossing manner in regions between a plurality of pixel circuits in one direction.

<FIG> and <FIG> are plan views of portions of display devices according to other embodiments.

Referring to <FIG> and <FIG>, a lower valley VA1 of an inorganic insulating layer or an upper valley VA2 of an interlayer insulating layer may group a plurality of pixels and surround the grouped pixels. In <FIG>, the lower valley VA1 and/or the upper valley VA2 surround two pixel circuits, that is, a first pixel circuit PC1 and a second pixel circuit PC2. In <FIG>, a lower valley VA1 of an inorganic insulating layer and/or an upper valley VA2 of an interlayer insulating layer surrounds six pixel circuit PC1 to PC6. The number of grouped pixel circuits may be modified variously.

The number of grouped pixels may be the same or may differ depending on a location in the display device. For example, in a region that is susceptible to a crack or stress, the lower valley VA1 of the inorganic insulating layer and/or the upper valley VA2 of the interlayer insulating layer may surround one pixel. In other regions, the lower valley VA1 of the inorganic insulating layer and/or the upper valley VA2 of the interlayer insulating layer may surround a plurality of pixels. Alternatively, the lower valley VA1 of the inorganic insulating layer and/or the upper valley VA2 of the interlayer insulating layer may be formed in only a portion of the display area DA.

<FIG> are views of a display device according to an embodiment. <FIG> illustrates that a display area of the display device is folded, and <FIG> illustrates that a display area of the display device is rolled.

Since the display device according to an embodiment includes the lower valley VA1 of the inorganic insulating layer and the first organic planarization layer <NUM> filling the lower valley VA1 in a display area DA, the display area DA is foldable or rollable, as illustrated in <FIG>.

That is, even when the display area DA is folded or rolled, since the display device includes the lower valley VA1 in the inorganic insulating layer, occurrence of a crack may be prevented or reduced because the first organic planarization layer <NUM> filling the lower valley VA1 may absorb stress caused by bending.

<FIG> is a plan view of a display device according to another embodiment. Referring to <FIG>, the display device according to an embodiment includes a bending area BA in a peripheral area PA, and the bending area BA is bent around a bending axis BAX. The display device may further include a bending valley VA' and a bending organic material layer <NUM>' that fills the bending valley VA' in the bending area BA. In addition, the display device may further include a fan-out wire <NUM> that is arranged on the bending organic material layer <NUM>', extending from a display area DA, and crossing the bending area BA.

The bending valley VA' may denote an opening or a groove formed in a portion of the inorganic insulating layer corresponding to the bending area BA. The bending valley VA' may be simultaneously formed when the lower valley VA1 (see <FIG>) is formed in the inorganic insulating layer in the display area DA.

The bending organic material layer <NUM>' may fill the bending valley VA' and absorb stress applied while the display device is bent. The bending organic material layer <NUM>' may be formed simultaneously with a first organic planarization layer (e.g., the first organic planarization layer <NUM> described above) in the display area DA and may include the same material as that of the first organic planarization layer <NUM>.

The fan-out wire <NUM> may denote a wire arranged in the peripheral area PA and transferring electric signals to the display area DA, and the electric signals are provided from a driving driver integrated circuit (IC) that is arranged in the peripheral area PA or a flexible printed circuit board (not shown).

The fan-out wire <NUM> may be formed simultaneously with a horizontal connection wire (e.g., the horizontal connection wire <NUM> described above) or a vertical connection wire (e.g., the vertical connection wire <NUM> described above) in the display area DA and may include the same material as that of the horizontal connection wire or the vertical connection wire. That is, the fan-out wire <NUM> may include a material having a high elongation property. For example, the fan-out wire <NUM> may include aluminum. The fan-out wire <NUM> may have a multi-layered structure in some embodiments. In an embodiment, the fan-out wire <NUM> has a stacked structure of Ti/Al/Ti.

The display device according to an embodiment may be made to be folded or rolled in the entire area of the display device or a selected portion or portions of the display area DA and/or the peripheral area PA.

Claim 1:
(Currently amended) A display device comprising:
a substrate (<NUM>) comprising a display area and a peripheral area outside the display area (DA), the display area (DA) comprising a plurality of pixel circuits (PC) and a plurality of display elements respectively connected to the plurality of pixel circuits (PC) to display an image;
an inorganic insulating layer arranged in the display area (DA), the inorganic insulating layer having a lower valley (VA1) as an opening or a groove in a region and arranged between a first pixel circuit (PC1) and a second pixel circuit (PC2) that are adjacent to each other;
a first organic planarization layer (<NUM>) arranged over entire regions of the first pixel circuit (PC1) and the second pixel circuit (PC2), the first organic planarization layer (<NUM>) filling the lower valley (VA1);
a connection wire (<NUM>) arranged on the first organic planarization layer (<NUM>), the connection wire (<NUM>) connecting the first pixel circuit (PC1) to the second pixel circuit (PC2); an interlayer insulating (<NUM>) layer arranged on the connection wire (<NUM>), the interlayer insulating layer (<NUM>) having an upper valley as an opening or a groove arranged in a region between at least two of the plurality of pixel circuits (PC); and a second organic planarization layer (<NUM>) arranged on the interlayer insulating layer (<NUM>) and over the entire regions of the first pixel circuit (PC1) and the second pixel circuit (PC2), the second organic planarization layer (<NUM>) filling the upper valley (VA2),
wherein the connection wire (<NUM>) is connected to a first conductive layer in the first pixel circuit (PC1) through a first contact hole (CNT3a) passing through the first organic planarization layer (<NUM>) and is connected to a second conductive layer in the second pixel circuit (PC2) through a second contact hole (CNT2b) passing through the first organic planarization layer (<NUM>), and
wherein the interlayer insulating layer (<NUM>) is disposed between the first organic planarization layer (<NUM>) and the plurality of display elements.