Patent Description:
This invention relates generally to magnetoresistive random access memory (MRAM). More particularly, this invention is directed to an MRAM reference cell with shape anisotropy to establish a well-defined magnetization orientation between a reference layer and a storage layer.

MRAM bit cell state determination typically relies on the use of amplifiers and comparators to determine if the MRAM bit's resistance is higher or lower than a stable reference resistor. The MRAM bit is considered a "<NUM>" or a "<NUM>" depending on whether its resistance is higher or lower than the reference. The reference resistance should be of a value that allows one to separate the two states of an MRAM device (parallel versus antiparallel magnetization, or, equivalently, low resistance versus high resistance).

An ideal circuit would involve temperature compensation such that over the operating temperature range the reference resistance varies at the same rate as the memory cell resistance as a function of temperature. An elegant way to achieve this thermal coefficient of resistance matching is to use a similar MRAM device as the reference element.

In the case of thermal-assist MRAM, high-temperature operations such as solder re-flow for device attach can decouple an antiferromagnetic layer from the ferromagnetic storage layer, allowing the storage layer magnetization to change direction, and thus causing the device to assume an indeterminate resistance. Because of this effect, resistors made from MRAM elements in thermal-assist MRAM do not provide useful, stable reference resistances against which one can compare the memory cell resistance.

It would be desirable to provide an MRAM reference cell that does not rely upon a non-MRAM ROM to set an MRAM reference resistance value, or upon large-area non-MRAM resistors with costly trimming steps and poorly matched temperature coefficients of resistance. In addition, it would be desirable to provide an MRAM reference cell that does not need to be programmed after solder re-flow associated with part attachment. Such a reference cell would provide a more compact memory, well-match temperature coefficient of resistance between memory elements and reference elements, and a reference memory with resistance value set by the circuit layout design rather than through a boot-up procedure.

<CIT> discloses a tunnel magnetic resistive element forming a magnetic memory cell including a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region.

<CIT> discloses a magnetic random access memory (MRAM) cell with a thermally assisted switching (TAS) writing procedure, comprising a magnetic tunnel junction formed from a ferromagnetic storage layer having a first magnetization adjustable at a high temperature threshold, a ferromagnetic reference layer having a fixed second magnetization, and an insulating layer, said insulating layer being disposed between the ferromagnetic storage and reference layers; a select transistor being electrically connected to said magnetic tunnel junction and controllable via a word line; a current line, electrically connected to said magnetic tunnel junction, passing at least a write current; characterized in that the magnetocrystalline anisotropy of the ferromagnetic storage layer is essentially orthogonal with the magnetocrystalline anisotropy of the ferromagnetic reference layer.

<CIT> discloses an integrated circuit having a cell, the cell including a first magnetic layer structure having a first magnetization along a first axis, a non-magnetic spacer layer structure disposed above the first magnetic layer structure, and a second magnetic layer structure disposed above the non-magnetic spacer layer structure. The second magnetic layer structure has a second magnetization along a second axis that is arranged in an angle with regard to the first axis such that by changing the direction of the second magnetization, the direction of the first magnetization along the first axis can be determined.

<CIT> discloses a nonvolatile memory including a memory area including a first magnetoresistive element, and a fuse circuit including a second magnetoresistive element serving as an anti-fuse element and configured to store correction information of the memory area when a defect exists in the memory area. The first magnetoresistive element includes a first storage layer, a first reference layer, and a first insulating film between the first storage layer and the first reference layer. The second magnetoresistive element includes a second storage layer, a second reference layer, and a second insulating film between the second storage layer and the second reference layer.

<CIT> discloses a two-axis magnetic field sensor having reduced compensation angle for zero offset.

<CIT> discloses a magnetoresistive effect element.

<CIT> discloses a magnetoresistive random access memory.

<CIT> discloses a read-out circuit of a magnetic device comprising a magnetoresistive memory element.

The present invention is set out in claim <NUM>. Preferred aspects are defined in dependent claims <NUM>-<NUM>. Only embodiments or examples comprising all the features of claim <NUM> are falling under the scope of protection of the present invention.

The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which:.

<FIG> illustrates a Magnetic Tunnel Junction (MTJ) stack <NUM> that may be utilized in accordance with an embodiment of the invention. MTJ stack <NUM> includes a low-blocking-temperature antiferromagnetic pinning layer <NUM>, a ferromagnetic storage layer <NUM>, a tunnel barrier <NUM>, a reference layer <NUM> with Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling through layer <NUM> to a pinned layer <NUM>, which is strongly pinned by a high-blocking-temperature antiferromagnet <NUM>. The invention is useful when the MRAM pinned layer <NUM> is strongly pinned even at high temperature and the storage layer <NUM> is not pinned at high temperature.

Standard materials may be used in the MTJ stack <NUM>. The invention is directed toward the shape of the MTJ stack <NUM>. In particular, the invention relies upon shape anisotropy to obtain desired performance. Anisotropy refers to directionally dependent properties in different directions. Shape anisotropy is used in this invention by modifying the aspect ratio in the plane of the MTJ stack layers <NUM> to obtain desired performance. Aspect ratio refers to size in different directions, such as the ratio of a major axis to a minor axis. For a circular MTJ, a top-down view of stack <NUM> would reveal that the major axis and minor axis are equivalent. The invention instead utilizes a high aspect ratio reference MTJ, such as MTJ <NUM> of <FIG>. As used herein, a high aspect ratio references an aspect ratio of at least <NUM>:<NUM> (i.e., a major axis of at least <NUM> and a minor axis of <NUM> or less). The resultant shape may be elliptical, diamond, or other configuration. The exact shape itself is less significant than the utilization of a high aspect ratio.

<FIG> illustrates a high aspect ratio MTJ <NUM> as an element in a reference block <NUM>. A standard (possibly circular) memory element MTJ <NUM> is an element in sensing block <NUM>. The reference block <NUM> also includes standard components, such as a variable resistor <NUM>, operational amplifier <NUM> and N-Channel MOSFET <NUM>. The N-Channel MOSFET <NUM> is a voltage-controlled current sink. Operating in conjunction with the operational amplifier <NUM>, it biases a constant current through the MTJ, thus generating a stable voltage on the input nodes to the comparator <NUM>. Similarly, the sensing block <NUM> includes standard components, such as a variable resistor <NUM>, operational amplifier <NUM> and N-Channel MOSFET <NUM>. A comparator <NUM> processes a reference signal from the reference block <NUM> and a sense signal from the sensing block <NUM>.

<FIG> illustrates a top-down view of high aspect ratio MTJ <NUM>. In this example, the high aspect ratio is manifested as an ellipse. That is, the MTJ stack <NUM> (e.g., corresponding to <NUM> in <FIG>), has the shape of an ellipse. The reference layer (e.g., <NUM> in <FIG>) is annealed during manufacture to have orientation of magnetization along the minor axis <NUM>. During standard wafer processing or solder re-flow conditions with temperature high enough to decouple the storage layer from the adjacent antiferromagnet, the storage layer (e.g., <NUM>) relaxes to a low energy state along major axis <NUM> substantially perpendicular to the reference layer by shape anisotropy. As detailed in <FIG> and <FIG>, the conductance of high aspect ratio MTJ <NUM> is approximately half way between minimum conductance and maximum conductance of a substantially round MTJ (e.g., <NUM>) of the same area. Solder re-flow temperatures are not high enough to disturb the direction of the reference layer, as it is coupled indirectly to an antiferromagnet with high blocking temperature. The high aspect ratio thus preserves the relative perpendicularity between storage and reference magnetic states even during solder re-flow. Consequently, after solder re-flow the reference MTJ <NUM> does not need to be programmed. Essentially, the MTJ is programmed through the anneal operation at the time of manufacture. Thereafter, the reference block <NUM> can operate without further programming.

<FIG> illustrates a segment of reference block <NUM>, including transistor <NUM>. The remaining elements shown in <FIG> are omitted for simplicity. For a refined manufacturing process, the appropriate high aspect ratio and device size may be known. On the other hand, for an immature manufacturing processing, it may be desirable to provide a reference block <NUM> with a variety of MTJs <NUM>, <NUM>, <NUM> and <NUM> with different high aspect ratios or areas. A multiplexer <NUM> may then be used to select the MTJ with the most effective high aspect ratio and area to serve as a midpoint reference for memory array MTJ resistance states. Series or parallel connections of the high aspect ratio device can be used as inputs to the multiplexer <NUM> if combinations are more convenient than shaping a single MTJ.

<FIG> illustrates angular orientations of magnetization direction between the storage layer and reference layer to assist with the interpretation of the plot in <FIG>. <FIG> also provides the equations governing the conductance of the MTJ for MTJ reference cells that that are not perfectly perpendicular to the reference layer.

<FIG> illustrates plotted conductance and resistance deviation as a function of the angle from parallel orientation. The X-axis refers to the angle from parallel orientation of the storage layer and the reference layer. In the ideal case, shape anisotropy would make this angle <NUM> degrees (i.e., perpendicular storage and reference layers), and corresponds to the diagram in <FIG>. The Y-axis in <FIG> gives the percent deviation from the halfway point of conductance or resistance. From the equation in <FIG>, we see the conductance at <NUM> degree (perpendicular) orientation is equal to the midpoint of the parallel and antiparallel configurations of the memory cell (i.e., zero percent deviation from the midpoint as per the Y-axis), and thus provides a very good reference against which to compare to a memory cell of the same area but of arbitrary shape. When dealing with conductance, it is straightforward to find the midpoint between maximum and minimum conductances as one rotates the orientation of the storage layer. If one choses to work with resistances, one must take into account that the perpendicular configuration does not provide the midpoint of resistance between minimum and maximum resistances. The perpendicular configuration of storage and reference magnetizations results in a resistance that is roughly <NUM>% less than the resistance of the midpoint between the high and low resistance states. One may therefore compensate by making the reference MTJ roughly <NUM>% smaller in area than the corresponding memory MTJs against which it is compared.

<FIG> illustrate alternate high aspect ratio shapes that may be used in accordance with embodiments of the invention.

Claim 1:
A magnetoresistive random access memory, MRAM, reference cell, comprising:
a reference magnetic tunnel junction (<NUM>, <NUM>) configured to produce a reference signal, the reference magnetic tunnel junction (<NUM>, <NUM>) having an aspect ratio of at least <NUM>:<NUM> of a major axis (<NUM>):minor axis (<NUM>), and including:
a reference layer (<NUM>), a pinned layer (<NUM>) and an antiferromagnet (<NUM>) adjacent to the pinned layer (<NUM>), wherein the reference layer (<NUM>) is coupled to the pinned layer (<NUM>), which is pinned by the adjacent antiferromagnet; and the reference layer (<NUM>) is magnetized along the minor axis (<NUM>) by annealing during manufacture; and
a storage layer (<NUM>) with magnetization along the major axis (<NUM>) and an antiferromagnetic pinning layer (<NUM>) adjacent to the storage layer (<NUM>), wherein the storage layer (<NUM>) magnetization is substantially perpendicular to the magnetization along the minor axis (<NUM>);
wherein the antiferromagnet (<NUM>) has a higher blocking temperature than the antiferromagnetic pinning layer (<NUM>), and the blocking temperatures are selected such that, when exposed to solder re-flow temperatures high enough to decouple the storage layer (<NUM>) from the adjacent antiferromagnetic pinning layer (<NUM>), the reference layer (<NUM>) is configured to remain coupled to the pinned layer (<NUM>), and the relative magnetization orientation of the reference layer (<NUM>) and the storage layer (<NUM>) along the minor axis (<NUM>) and the major axis (<NUM>), respectively, configured to be maintained by shape anisotropy caused by the aspect ratio.