Patent Description:
The present invention is defined by a method according to appended claim <NUM> and by an apparatus according to appended claim <NUM>. In some embodiments, a method of staging memory access requests includes receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.

In some embodiments, the method includes selecting the memory access request from the command queue; and executing the memory access request. In some embodiments, the method includes receiving another memory access request; determining that the staging buffer is full; and storing the other memory access request in the command queue without storing the other memory access request in the staging buffer. In some embodiments, the method includes selecting, based on one or more arbitration rules, the memory access request from a plurality of memory access requests in the staging buffer for moving to the command queue. In some embodiments, selecting, based on one or more arbitration rules, the memory access request includes selecting the memory access request based on one or more of an open Dynamic Random Access Memory page, a bank group rotation, a request type of the memory access request, or a sub-channel balancing.

In some embodiments, a memory management unit for staging memory access requests performs steps including: receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.

In some embodiments, the steps include selecting the memory access request from the command queue; and executing the memory access request. In some embodiments, the steps include receiving another memory access request; determining that the staging buffer is full; and storing the other memory access request in the command queue without storing the other memory access request in the staging buffer. In some embodiments, the steps include selecting, based on one or more arbitration rules, the memory access request from a plurality of memory access requests in the staging buffer for moving to the command queue. In some embodiments, selecting, based on one or more arbitration rules, the memory access request includes selecting the memory access request based on one or more of an open Dynamic Random Access Memory page, a bank group rotation, a request type of the memory access request, or a sub-channel balancing.

In some embodiments, a processor for staging memory access requests includes a memory management unit to perform steps including: receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.

In some embodiments, a system for staging memory access requests includes an apparatus including a processor, the processor including a memory management unit to perform steps including: receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer, to a command queue.

<FIG> is a block diagram of an example processor <NUM> according to some embodiments. The example processor <NUM> can be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, and the like. The processor <NUM> includes a memory management unit <NUM>. The memory management unit <NUM> receives memory access requests (e.g., requests to read and/or write data to a particular region of memory. The memory management unit <NUM> also performs the translation of virtual memory addresses in the memory access requests to physical memory addresses in order to perform the memory access request.

The memory management unit <NUM> includes a command queue <NUM>. The command queue <NUM> stores memory access requests as they are received (e.g., from a central processing unit or other component of the processor <NUM>) prior to execution to access Dynamic Random Access Memory <NUM>. Although the Dynamic Random Access Memory <NUM> is shown as being separate from the processor <NUM>, it is understood that the Dynamic Random Access Memory <NUM> may include on-chip Dynamic Random Access Memory <NUM> (e.g., as a component of the processor <NUM>). Where the Dynamic Random Access Memory <NUM> includes multiple banks, the memory management unit <NUM> may include multiple command queues <NUM> each corresponding to a respective bank.

The memory management unit <NUM> selects memory access requests for execution from the command queue <NUM> using one or more schemes, such as first-come-first-served (FCFS), first-ready, first-come-first-served (FR-FCFS), first-in-first-out (FIFO), etc. The memory management unit <NUM> includes a command queue arbiter <NUM> that selects memory access requests from the command queue <NUM> for execution using one or more rules. For example, the one or more rules are based on timing or clock information (e.g., an age of a memory access request). As another example, the one or more rules are based on a page table <NUM>. For example, memory access requests that will result in a page table <NUM> hit are preferentially selected from the command queue <NUM> for execution.

In existing approaches, memory access requests received by a memory management unit <NUM> are placed directly in a command queue <NUM> for subsequent execution. To improve performance and relieve pressure on the command queue <NUM>, the memory management unit <NUM> includes a staging buffer <NUM>. Memory access requests received by the memory management unit <NUM> are placed in the staging buffer <NUM>. A staging buffer arbiter <NUM> then selects, based on one or more arbitration rules, memory access requests from the staging buffer <NUM> for movement to the command queue <NUM>.

In some embodiments, the arbitration rules are based on a Dynamic Random Access Memory <NUM> page targeted by a memory access request. For example, a memory access request targeting a Dynamic Random Access Memory <NUM> page that is open is preferentially selected for movement to the command queue <NUM> as overhead required in closing and opening pages is reduced. As another example, a memory access request targeting a Dynamic Random Access Memory <NUM> page that is also targeted by another memory access request in the command queue <NUM>, and therefore will be open when the selected memory access request is executed, is preferentially selected.

In some embodiments, the arbitration rules are based on a bank group rotation or rank rotation. For example, where the Dynamic Random Access Memory <NUM> includes multiple banks, memory access requests are selected from the staging buffer <NUM> for addition to the command queue <NUM> such that consecutively added requests do not target a same bank. As an example, a memory access request targeting a first bank is moved to the command queue <NUM>, then a memory access request targeting a second bank is moved to the command queue <NUM>. Another memory access request targeting the first bank is then be added to the command queue <NUM>, etc. In some embodiments, memory access requests are selected to target different ranks within the same or different banks or to alternatively target different subchannels of Dynamic Random Access Memory <NUM> (e.g., sub-channel balancing).

In some embodiments, the arbitration rules are based on a request type for the memory access requests (e.g., read or write). As there is computational overhead in switching between Dynamic Random Access Memory <NUM> reads and writes, read requests and/or write requests are grouped together as part of a "burst" of requests for movement to the command queue <NUM>. Thus, a group of read requests and/or a group of write requests may be executed consecutively.

In some embodiments, the memory management unit <NUM> determines that the staging buffer <NUM> is full. Accordingly, the memory management unit <NUM> stores a received memory access request directly in the command queue <NUM> without storing the received memory access request in the staging buffer <NUM>.

For further explanation, <FIG> sets forth a flow chart illustrating an exemplary method for staging memory access requests according to embodiments of the present disclosure that includes receiving <NUM> (e.g., by a memory management unit <NUM> of a processor <NUM>) a memory access request <NUM> directed to Dynamic Random Access Memory <NUM>. The memory access request <NUM> includes a request to read or write data to or from Dynamic Random Access Memory <NUM>. The memory access request <NUM> is received via a data fabric or other interconnect coupling the memory management unit <NUM> to a central processing unit or other component.

The method of <FIG> also includes storing <NUM> (e.g., by the memory management unit <NUM>) the memory access request <NUM> in a staging buffer <NUM>. The method of <FIG> also includes moving <NUM> the memory access request <NUM> from the staging buffer <NUM> to a command queue <NUM>. Moving <NUM> the memory access request <NUM> includes removing the memory access request <NUM> from the staging buffer <NUM> and storing the memory access request <NUM> in the command queue <NUM>. In some embodiments, the memory access request <NUM> is moved in response to a number of memory access requests <NUM> in the staging buffer <NUM> meeting a threshold. In some embodiments, the memory access request <NUM> is moved in response to a number of memory access requests <NUM> in the command queue <NUM> falling below a threshold. In some embodiments, the memory access request <NUM> is moved in response to an age of the memory access request <NUM> (e.g., a time at which the memory access request <NUM> was received) meeting a threshold. In some embodiments the memory access request <NUM> is moved in response to one or more arbitration rules being satisfied.

For further explanation, <FIG> sets forth a flow chart illustrating an exemplary method for staging memory access requests according to embodiments of the present disclosure that includes receiving <NUM> (e.g., by a memory management unit <NUM> of a processor <NUM>) a memory access request <NUM> directed to Dynamic Random Access Memory <NUM>; storing <NUM> the memory access request <NUM> in a staging buffer <NUM>; and moving <NUM> the memory access request <NUM> from the staging buffer <NUM> to a command queue <NUM>.

The method of <FIG> differs from <FIG> in that the method of <FIG> also includes selecting <NUM> (e.g., by the memory management unit <NUM> of the processor <NUM>) the memory access request <NUM> from the command queue <NUM>. The memory access request <NUM> is selected from the command queue <NUM> using one or more schemes, such as first-come-first-served (FCFS), first-ready, first-come-first-served (FR-FCFS), first-in-first-out (FIFO), etc. In some embodiments, the memory management unit <NUM> includes a command queue arbiter <NUM> that selects memory access requests from the command queue <NUM> for execution using one or more rules. For example, the one or more rules are based on timing or clock information (e.g., an age of a memory access request). As another example, the one or more rules are based on a page table <NUM>. For example, memory access requests that will result in a page table <NUM> hit are preferentially selected from the command queue <NUM> for execution.

The method of <FIG> differs from <FIG> in that the method of <FIG> also includes executing <NUM> (e.g., by the memory management unit <NUM>), the memory access request <NUM>. Executing <NUM> the memory access request <NUM> includes reading data from a Dynamic Random Access Memory <NUM> address specified in the memory access request <NUM> and/or writing data to a Dynamic Random Access Memory <NUM> address specified in the memory access request <NUM>.

The method of <FIG> differs from <FIG> in that the method of <FIG> also includes receiving <NUM> another memory access request <NUM>. The method of <FIG> further differs from <FIG> in that the method of <FIG> also includes determining <NUM> that the staging buffer <NUM> is full. The staging buffer <NUM> includes a predefined amount of memory for storing a predefined maximum number of memory access requests. Accordingly, determining <NUM> that the staging buffer <NUM> is full includes determining that the staging buffer <NUM> is storing the predefined maximum number of memory access requests.

The method of <FIG> further differs from <FIG> in that the method of <FIG> also includes storing <NUM> the other memory access request <NUM> in the command queue <NUM> without storing the other memory access request <NUM> in the staging buffer <NUM>. Thus, the staging buffer <NUM> is bypassed when full.

The method of <FIG> differs from <FIG> in that the method of <FIG> also includes selecting <NUM> (e.g., by the memory management unit <NUM>, by a staging buffer arbiter <NUM> of the memory management unit <NUM>), based on one or more arbitration rules, the memory access request <NUM> from a plurality of memory access requests in the staging buffer <NUM> for moving to the command queue <NUM>.

In some embodiments, the arbitration rules are based on a bank group rotation or rank rotation. For example, where the Dynamic Random Access Memory <NUM> includes multiple banks, memory access requests are selected from the staging buffer <NUM> for addition to the command queue <NUM> such that consecutively added requests do not target a same bank. As an example, a memory access request targeting a first bank is moved to the command queue <NUM>, then a memory access request targeting a second bank is moved to the command queue <NUM>. Another memory access request targeting the first bank is then added to the command queue <NUM>, etc. In some embodiments, memory access requests are selected to target different ranks within the same or different banks. Memory access requests are also selected to alternatively target different subchannels of Dynamic Random Access Memory <NUM> (e.g., sub-channel balancing).

In some embodiments, the arbitration rules are based on a request type for the memory access requests (e.g., read or write). As there is computational overhead in switching between Dynamic Random Access Memory <NUM> reads and writes, read requests and/or write requests are grouped together as part of a "burst" of requests for movement to the command queue <NUM>. Thus, a group of read requests and/or a group of write requests are executed consecutively.

For further explanation, <FIG> sets forth a flow chart illustrating an exemplary method for staging buffer arbitration according to embodiments of the present disclosure that includes storing <NUM> (e.g., by a memory management unit <NUM> of a processor <NUM>) a plurality of memory access requests in a staging buffer <NUM>. The memory access requests include a request to read or write data to or from Dynamic Random Access Memory <NUM>. The memory access requests are via a data fabric or other interconnect coupling the memory management unit <NUM> to a central processing unit or other component.

The method of <FIG> also includes selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM>. A staging buffer arbiter <NUM> selects the memory access request <NUM> based on the one or more arbitration rules. The arbitration rules are applied to various attributes of the memory access requests stored in the staging buffer <NUM>, memory access requests stored in a command queue <NUM>, a page table <NUM>, and/or other attributes. For example, the arbitration rules are based on request type of memory access requests in the staging buffer <NUM> and/or command queue <NUM>, a currently open Dynamic Random Access Memory <NUM> page, bank groups targeted by the memory access requests in the staging buffer <NUM> and/or command queue <NUM>, refresh state of a bank or page targeted by memory access requests in the staging buffer <NUM> and/or command queue <NUM>, and/or sub-channels targeted by memory access requests in the staging buffer <NUM> and/or command queue <NUM>.

The method of <FIG> also includes moving <NUM> the memory access request <NUM> from the staging buffer <NUM> to a command queue <NUM>. Moving <NUM> the memory access request <NUM> includes deleting the memory access request <NUM> from the staging buffer <NUM> and/or freeing a portion of the staging buffer <NUM> storing the memory access request <NUM> for subsequent overwriting. Moving <NUM> the memory access request <NUM> also includes adding the memory access request <NUM> to the command queue <NUM>. Thus, the memory access request <NUM> is later executed from the command queue <NUM> by the memory management unit <NUM>.

For further explanation, <FIG> sets forth a flow chart illustrating an exemplary method for staging buffer arbitration according to embodiments of the present disclosure that includes storing <NUM> (e.g., by a memory management unit <NUM> of a processor <NUM>) a plurality of memory access requests in a staging buffer <NUM>; selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM>; and moving <NUM> the memory access request <NUM> from the staging buffer <NUM> to a command queue <NUM>.

The method of <FIG> differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> includes selecting <NUM> a memory access request burst of a same request type, wherein the memory access request burst includes the memory access request <NUM>. A memory access request burst includes a plurality of memory access requests of the same type (e.g., read or write). The memory access requests in the memory access request burst are selected for movement to the command queue <NUM> consecutively and/or at least partially simultaneously such that the memory access requests in the memory access request burst are later executed consecutively and/or at least partially simultaneously. For example, a burst of read requests are executed without executing an intervening write request. As another example, a burst of write requests are executed without executing an intervening read request. As switching between executing read and write requests to Dynamic Random Access Memory <NUM> costs computational overhead, this computational overhead is avoided by executing multiple memory access requests of a same request type. Accordingly, the memory access request <NUM> is selected based on other memory access requests of the same request type having been added to the command queue <NUM> and or based on other memory access requests of the same request type being stored in the staging buffer <NUM> that are subsequently added to the command queue <NUM> as part of the memory access request burst.

The method of <FIG> differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> includes selecting <NUM> the memory access request <NUM> based on one or more of: a bank targeted by another memory access request, a rank targeted by a memory access request, or a memory subchannel targeted by another memory access request. For example, in some embodiments, memory access requests are added to the command queue <NUM> such that executed memory access requests alternatingly target different Dynamic Random Access Memory <NUM> ranks or banks (e.g., rank balancing, bank balancing). In other embodiments, memory access requests are added to the command queue <NUM> such that the executed memory access requests target Dynamic Random Access Memory <NUM> subchannels in a balanced approach. Accordingly, the memory access request <NUM> is selected based on a rank, bank, or subchannel targeted by a memory access request already added to the command queue <NUM> (e.g., a queued memory access command targeting a different rank, bank, or subchannel). The memory access request <NUM> is also selected based on a rank, bank, or subchannel targeted by a memory access request in the staging buffer <NUM> that is later added to the command queue <NUM> (e.g., a staged memory access command targeting a different rank, bank, or subchannel).

The method of <FIG> differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> includes selecting <NUM> the memory access request <NUM> based on a Dynamic Random Access Memory <NUM> page targeted by another memory access request. If an executed memory access request targets a page that is not currently open, overhead occurs in closing the currently open page and opening the targeted page. Executing memory access requests targeting a same (e.g. open) page reduces this overhead. Accordingly, in some embodiments, the memory access request <NUM> is selected based on a page targeted by an already executed memory access request (e.g., an already open page). In some embodiments, the memory access request <NUM> is selected based on a page targeted by a memory access request stored in the command queue <NUM> to be executed prior to the selected memory access request <NUM> such that the targeted page will be open when the selected memory access request <NUM> is executed. In some embodiments, the memory access request <NUM> is selected based on a page targeted by another memory access request stored in the staging buffer <NUM> that will be subsequently selected for movement to the command queue <NUM> such that the targeted page is open when the other memory access request is executed.

The method of <FIG> differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> includes selecting <NUM> the memory access request <NUM> based on a priority value. In some embodiments, the priority value is an explicit priority value assigned to memory access requests <NUM> (e.g., a priority tier). In other embodiments, the priority value is calculated based on an attribute of memory access requests, such as an age of the memory access requests (e.g., a time at which a given memory access request was generated or received by the memory management unit <NUM>).

The method of <FIG> differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> includes identifying <NUM>, in the staging buffer <NUM>, another memory access request associated with a first page miss. In other words, execution of the other memory access request will result in a page miss and corresponding computational overhead. For example, the page table <NUM> is accessed to determine that execution of the other memory access request will result in a page miss.

The method of <FIG> further differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> also includes identifying <NUM>, in the command queue <NUM>, a queued memory access request associated with a second page miss different from the first page miss. For example, the queued memory access request is identified as having a same request type and targeting a same Dynamic Random Access Memory bank as the other memory access request in the staging buffer, but will result in a different row page miss.

The method of <FIG> further differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> also includes selecting <NUM>, in response to identifying the other memory access request and the queued memory access request, the memory access request <NUM>. In other words, the memory access request <NUM> is preferentially selected over the other memory access request in the staging buffer <NUM> associated with the first page miss.

The method of <FIG> differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> includes identifying <NUM>, in the staging buffer <NUM>, another memory access request associated with a first page conflict. In other words, execution of the other memory access request will result in a page conflict and corresponding computational overhead. For example, the page table <NUM> is accessed to determine that execution of the other memory access request will result in a page conflict.

The method of <FIG> further differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> also includes identifying <NUM>, in the command queue <NUM>, a queued memory access request associated with a second page conflict different from the first page conflict. For example, the queued memory access request is identified as having a same request type and targeting a same Dynamic Random Access Memory bank as the other memory access request in the staging buffer <NUM>, but will result in a different row page conflict.

The method of <FIG> further differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> also includes selecting <NUM>, in response to identifying the other memory access request and the queued memory access request, the memory access request <NUM>. In other words, the memory access request <NUM> is preferentially selected over the other memory access request in the staging buffer <NUM> associated with the first page conflict.

For further explanation, <FIG> sets forth a flow chart illustrating an exemplary method for staging memory access requests according to embodiments of the present disclosure that includes storing <NUM> (e.g., by a memory management unit <NUM> of a processor <NUM>) a plurality of memory access requests in a staging buffer <NUM>; selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM>; and moving <NUM> the memory access request <NUM> from the staging buffer <NUM> to a command queue <NUM>.

The method of <FIG> differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> includes identifying <NUM>, in the command queue <NUM>, a page hit request. A page hit request includes a memory access request targeting a currently open page of dynamic random access memory <NUM>. The method of <FIG> further differs from <FIG> in that selecting <NUM>, based on one or more arbitration rules, a memory access request <NUM> of the plurality of memory access requests from the staging buffer <NUM> includes selecting <NUM>, based on the memory access request <NUM> being another page hit request, the memory access request <NUM>. In other words, the memory access request <NUM> is preferentially selected for movement to the command queue <NUM> over other memory access requests that would result in a page miss. Thus, the staging buffer <NUM> will hold page conflict requests. In some implementations, the memory access request <NUM> is selected for movement to the command queue <NUM> such that the command queue <NUM> preferentially holds no more than one memory access request for each bank.

In view of the explanations set forth above, readers will recognize that the benefits of staging memory access requests according to embodiments of the present disclosure include:.

Exemplary embodiments of the present disclosure are described largely in the context of a fully functional computer system for staging memory access requests. Readers of skill in the art will recognize, however, that the present disclosure also can be embodied in a computer program product disposed upon computer readable storage media for use with any suitable data processing system. Such computer readable storage media can be any storage medium for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tape, and others as will occur to those of skill in the art. Persons skilled in the art will immediately recognize that any computer system having suitable programming means will be capable of executing the steps of the method of the disclosure as embodied in a computer program product. Persons skilled in the art will recognize also that, although some of the exemplary embodiments described in this specification are oriented to software installed and executing on computer hardware, nevertheless, alternative embodiments implemented as firmware or as hardware are well within the scope of the present disclosure.

The present disclosure can be a system, a method, and/or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

The computer readable storage medium can be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.

The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers.

Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein includes an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

In this regard, each block in the flowchart or block diagrams can represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block can occur out of the order noted in the figures.

The descriptions in this specification are for purposes of illustration only.

Claim 1:
A method of staging memory access requests, the method comprising:
storing (<NUM>) a plurality of memory access requests in a staging buffer (<NUM>);
selecting (<NUM>, <NUM>), based on one or more arbitration rules, between a first memory access request and a second memory access request from the plurality of memory access requests in the staging buffer (<NUM>) for moving to a command queue (<NUM>), wherein the one or more arbitration rules are applied to one or more attributes of a plurality of memory access requests already in the command queue (<NUM>); and
moving (<NUM>) the selected memory access request (<NUM>) from the staging buffer (<NUM>) to the command queue (<NUM>).