Patent Description:
Antenna array systems will be a ubiquitous component in forthcoming <NUM> (fifth generation) communication systems as a means of improving capacity at the presently used low GHz frequencies but more so to ensure sufficient coverage as the operating frequency extends to the mmW range. Antenna arrays typically consists of a regular structure of equispaced antenna elements.

Antenna arrays can be used to simultaneously transmit or receive multiple layers, e.g. through multiple beams in the special case of line-of-sight (LOS) communication or more generally through the concept of MU-MIMO (multi-user MIMO (multiple-input multiple-output)). During beam forming the antenna correlation properties are important such that highly correlated antennas may be combined coherently and thereby increasing the transmission efficiency. Typically, adjacent antennas present a higher correlation than distant antenna elements.

One key parameter when designing the <NUM> concept is energy efficiency. A base station may be equipped with a high number of antenna elements, even in the order of hundreds, and include a plurality of transceiver integrated circuits (ICs). In some use scenarios, all antenna elements and transceiver ICs might not be needed. Hence there is an opportunity to implement energy saving schemes by disabling, or inactivating, parts of the base station, sometimes even inactivating one or more complete transceiver IC.

<CIT> discloses an integrated circuit that includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.

<CIT> discloses a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port.

<CIT> discloses an integrated circuit that includes a clock distribution circuit and a logic block circuit. The clock distribution circuit is segregated from the logic block circuit to restrict contributors to phase noise to the clock distribution section of the circuit. The clock distribution circuit includes a front-end amplifier which buffers a clock input signal to a differential clock signal. The front-end amplifier is configured with as few components as possible and the components are selected for high current density and sized to minimize contributions to phase noise in the clock distribution circuit. The clock distribution circuit further includes an output latch circuit that receives the output signal of the logic block circuit and the low phase noise differential clock input signal from the front-end amplifier circuit. The output latch circuit re-clocks the final output of the integrated circuit. The output is representative of the output values determined by the logic block circuit.

<CIT> discloses how a first oscillatory signal is distributed to a number of destinations in an integrated circuit die. The frequency of a second oscillatory signal is made to track the average frequency of the first oscillatory signal, using an injection locked oscillator, as such rejecting high frequency jitter. The second oscillatory signal is provided to one or more of the destinations.

The inventors have realized that a reduced impact of reference clock phase noise can, at least for some usages, be obtained for ICs comprising multiple communication circuits (e.g. transceiver, transmitter, or receiver circuits) by means of using multiple input terminals for reference clock signals. An example of such a usage is when a communication apparatus comprising multiple such integrated circuits operates in a mode when only a subset of the ICs are enabled.

According to a first aspect, there is provided an integrated circuit configured to be connected to an antenna module having multiple antenna elements. The integrated circuit comprises a plurality of communications circuits, each of which is configured to be connected to an antenna element of the antenna module. It also comprises a first clock input terminal configured to receive a reference clock signal from outside the integrated circuit and a first clock-distribution network connected between the first clock input terminal and a first subset of the communication circuits. Furthermore, it comprises a second clock input terminal configured to receive a reference clock signal from outside the integrated circuit and a second clock-distribution network connected between the second clock input terminal and a second subset of the communication circuits.

The integrated circuit may comprise additional clock input terminals configured to receive reference clock signals from outside the integrated circuit. Furthermore, for each of said additional clock input terminals, the integrated circuit may comprise a clock-distribution network connected between that clock input terminal and an associated subset of the communication circuits.

Said clock-distribution networks may comprise buffer amplifiers connected in a tree structure.

Each of the plurality of communication circuits may have a reference-clock input connected to an output of a buffer amplifier of a clock-distribution network.

The communication circuits may, for instance, be transceiver circuits, receiver circuits, or transmitter circuits.

The communication circuits may be configured to communicate at a common radio frequency carrier frequency.

According to a second aspect, there is provided a communication apparatus comprising a reference clock signal generator configured to generate a main reference clock signal and a clock buffer circuit configured to receive the main reference clock signal at an input terminal and having a plurality of output buffers, each configured to output a reference clock signal with the same frequency as the main reference clock signal at an output terminal of the output buffer. The communication apparatus also comprises a plurality of integrated circuits according to the first aspect. Each output buffer of the clock buffer circuit has its output terminal connected to at most one of the clock input terminals of the same one of the integrated circuits.

The communication apparatus may comprise an antenna module having multiple antenna elements, each connected to a communication circuit of an integrated circuit among said plurality of integrated circuit.

The reference clock signal generator may, for instance, be a crystal oscillator.

In some embodiments, the communication apparatus is configured to selectively disable one or more of the plurality of integrated circuits.

In some embodiments, the communication apparatus is configured to operate with beamforming transmission or reception.

The communication apparatus may be configured for operation in a cellular communications network. For example, the communication apparatus may be a base station.

It should be emphasized that the term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

Further objects, features and advantages of embodiments of the invention will appear from the following detailed description, reference being made to the accompanying drawings, in which:.

<FIG> illustrates a communication environment wherein embodiments of the present invention may be employed. A wireless device <NUM> of a cellular communications system is in wireless communication with a radio base station <NUM> (or "base station <NUM>" for short) of the cellular communications system. The wireless device <NUM> may be what is generally referred to as a user equipment (UE). The wireless device <NUM> is depicted in <FIG> as a mobile phone, but may be any kind of device with cellular communication capabilities, such as a tablet or laptop computer, machine-type communication (MTC) device, or similar. Furthermore, a cellular communications system is used as an example throughout this disclosure. However, embodiments of the present invention may be applicable in other types of systems as well, such as but not limited to WiFi systems.

The radio base station <NUM> and wireless device <NUM> are examples of what in this disclosure is generically referred to as communication apparatuses. Embodiments are described below in the context of a communication apparatus in the form of the radio base station <NUM>. However, other types of communication apparatuses can be considered as well, such as a WiFi access point or WiFi enabled device.

According to the example shown in <FIG>, the radio base station <NUM> is equipped with an antenna module <NUM>, such as an antenna array comprising a plurality of antenna elements.

<FIG> is a block diagram of (part of) the base station <NUM> according to some embodiments. It comprises a reference clock signal generator <NUM> configured to generate a main reference clock signal. For instance, the reference clock signal generator <NUM> may be a crystal oscillator. In <FIG>, the base station <NUM> further comprises a clock buffer circuit <NUM>, which is configured to receive the main reference clock signal at an input terminal. The clock buffer circuit is further configured to output buffered reference clock signals on with the same frequency as the main reference clock signal. <FIG> shows a connection <NUM> with multiple wires from the clock buffer circuit <NUM>. The individual wires are referred to with the reference sign <NUM>m, where m is an integer index identifying the individual wire. Each individual wire is dedicated to carry one of the buffered reference clock signals. In the embodiment illustrated in <FIG>, the base station <NUM> further comprises a plurality of integrated circuits (IC) 10a-d, which are further described below with reference to <FIG>. As described below, each IC 10a-d comprises a number of communication circuits (referred to with reference signs <NUM>j, where j is an integer index identifying an individual communication circuit), such as transmitter circuits, receiver circuits, or transceiver circuits. Each such communication circuit <NUM>j is configured to be connected an antenna element <NUM> of the antenna module <NUM>. Reference sign <NUM> is used herein as a general reference to the antenna elements. For simplicity and ease of illustration, only one of the squares representing antenna elements in <FIG> is provided with the reference number <NUM>. The communication circuits <NUM>j may be configured to communicate at a common radio frequency carrier frequency. For example, in this way, the base station <NUM> may be configured to operate with beamforming or MIMO transmission or reception. The buffered reference clock signals may be used in the ICs 10a-d to generate local oscillator (LO) signals for up-conversion of a signal to be transmitted to the radio frequency carrier frequency and/or downconversion of a received signal from the radio frequency carrier frequency. This can for example be accomplished using phase-locked loops (PLLs) or other frequency synthesizers.

As an elucidating example, which is used in this description to illustrate how embodiments disclosed herein may be advantageously employed, the antenna module <NUM> is, in <FIG>, conceptually divided into sub arrays 20a-d. In the example, the antenna elements <NUM> in the sub array 20a are connected to communication circuits in the IC 10a, the antenna elements <NUM> in the sub array 20b are connected to communication circuits in the IC 10b, the antenna elements <NUM> in the sub array 20c are connected to communication circuits in the IC 10c, and the antenna elements <NUM> in the sub array 20d are connected to communication circuits in the IC 10d. The base station <NUM> may be configured to selectively disable one or more of the plurality of integrated circuits 10a-d, e.g. to save energy. Embodiments disclosed herein can provide a relatively low impact of phase noise in the reference clock signals in scenarios where only a subset of the sub arrays 20a-d and ICs 10a-d are enabled.

<FIG> is a block diagram of an IC <NUM> according to an embodiment. Each of the ICs 10a-d may be implemented in the same way as the IC <NUM>. The IC <NUM> comprises a plurality of communications circuits <NUM>j, each of which is configured to be connected to an antenna element <NUM> of the antenna module <NUM>. Furthermore, the IC <NUM> comprises a first clock input terminal <NUM><NUM> configured to receive a reference clock signal from outside the integrated circuit <NUM>. In <FIG>, the first clock input terminal <NUM><NUM> is connected to the wire <NUM><NUM>. The IC <NUM> also comprises a first clock-distribution network <NUM><NUM> connected between the first clock input terminal <NUM><NUM> and a first subset <NUM><NUM> of the communication circuits <NUM>j. In addition, the IC <NUM> comprises a second clock input terminal <NUM><NUM> configured to receive a reference clock signal from outside the integrated circuit <NUM>. In <FIG>, the second clock input terminal <NUM><NUM> is connected to the wire <NUM><NUM>. Moreover the IC <NUM> comprises a second clock-distribution network <NUM><NUM> connected between the second clock input terminal <NUM><NUM> and a second subset <NUM><NUM> of the communication circuits <NUM>j. As further described below, this structure of the reference clock distribution of the IC <NUM>, with more than one reference clock input terminal and associated clock distribution network, facilitates a relatively low impact of reference clock phase noise in some use scenarios.

As illustrated in <FIG>, the IC <NUM> may also have additional clock input terminals, such as a third clock input terminal <NUM><NUM> and a fourth clock input terminal <NUM><NUM>, configured to receive reference clock signals from outside the integrated circuit <NUM>, and for each of said additional clock input terminals <NUM><NUM>, <NUM><NUM>, a clock-distribution network <NUM><NUM>, <NUM><NUM> connected between that clock input terminal <NUM><NUM>, <NUM><NUM> and an associated subset, such as a third subset <NUM><NUM> and a fourth subset <NUM><NUM>, of the communication circuits <NUM>j.

As illustrated in <FIG> each of said clock-distribution networks <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM> may comprise buffer amplifiers <NUM>, <NUM>k connected in a tree structure. Each of the plurality of communication circuits <NUM>j may have a reference-clock input connected to an output of a buffer amplifier <NUM>k of one of the clock-distribution networks <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>. It should be noted that the different communication circuits <NUM>j within a subset, say <NUM>m, exhibits a slightly different phase noise in the reference clock signals, since they are provided by different buffers <NUM>k. However, the phase noise already present in the reference clock signal received on clock input terminal <NUM>m propagates to all communication circuits <NUM>j in the subset <NUM>m. Thus, there is a degree of correlation in the phase noise between the reference clock signals used by the communication circuits <NUM>j within the same subset <NUM>m.

<FIG> illustrates a block diagram of an embodiment of the clock buffer circuit <NUM>. As illustrated in <FIG>, the clock buffer circuit <NUM> may have a plurality of output buffers <NUM>m, each configured to output a buffered reference clock signal with the same frequency as the main reference clock signal at an output terminal of the output buffer <NUM>m. In the example illustrated in <FIG>, the output buffer <NUM><NUM> is configured to output its buffered reference clock signal to the wire <NUM><NUM>, the output buffer <NUM><NUM> is configured to output its buffered reference clock signal to the wire <NUM><NUM>, the output buffer <NUM><NUM> is configured to output its buffered reference clock signal to the wire <NUM><NUM>, and the output buffer <NUM><NUM> is configured to output its buffered reference clock signal to the wire <NUM><NUM>. The clock buffer circuit <NUM> may also comprise one or more buffers <NUM> connected between the reference clock signal generator <NUM> and the output buffers <NUM>m.

By using more than one clock input terminal for receiving reference clock signals, as in embodiments herein, it is possible to reduce the impact of phase noise. Consider, for comparison, an IC with only one single clock input terminal for receiving a single reference clock signal from outside the IC, e.g. from one single output buffer, such as the buffers <NUM>m, of a clock buffer circuit, such as the clock buffer circuit <NUM>. In such an IC, the LO signals in all communication circuits <NUM>j have to, ultimately, be derived from that single reference clock signal. Thus, even though there may be a clock-buffer tree between the single clock input terminal and the individual communication circuits <NUM>j, the phase noise of said single reference clock signal is affecting all LO signals derived therefrom in the same way, resulting in a relatively high degree of phase-noise correlation between the generated LO signals. In case different ICs of the base station use different reference clock signals, with relatively little mutual correlation in the phase noise, the effects of the phase noise may be suppressed by averaging when all ICs are enabled. However, when only a subset of the ICs, in the extreme case only a single IC, is enabled to save energy, the effects of the relatively highly correlated phase noise in the LO signals within a single chip may have a detrimental impact on the overall signal quality, e.g. in terms of signal-to-noise ratio (SNR). If instead, as in embodiments disclosed herein, each IC <NUM> is equipped with more than one clock input terminal for receiving reference clock signals from the outside, the phase-noise correlation between LO signals within the same IC <NUM> can be reduced. Some degree of correlation between the reference clock signal on wire <NUM><NUM> and the reference clock signal on wire <NUM><NUM> should be expected, since they are derived from the same main reference clock signal. However, the phase noise generated by the output buffer <NUM><NUM> is only affecting the communication circuits <NUM>j in the subset <NUM><NUM>, the phase noise generated by the output buffer <NUM><NUM> is only affecting the communication circuits <NUM>j in the subset <NUM><NUM>, the phase noise generated by the output buffer <NUM><NUM> is only affecting the communication circuits <NUM>j in the subset <NUM><NUM>, the phase noise generated by the output buffer <NUM><NUM> is only affecting the communication circuits <NUM>j in the subset <NUM><NUM>, and the phase noise generated by the output buffer <NUM><NUM> is only affecting the communication circuits <NUM>j in the subset <NUM><NUM>. Hence, overall, for each IC 10a-d, the average correlation of the LO signal phase noise between two communication circuits <NUM>j on the same IC 10a-d can be made lower when more than one reference clock input terminal is used, compared with an IC with only a single reference clock signal input terminal. This is further illustrated with examples in <FIG> described below.

<FIG> illustrates the sub array 20a according to an embodiment. An index i is given to each antenna element <NUM>, of the sub array 20a. The antenna element <NUM>i is, in this embodiment, connected to the communication circuit <NUM>, (<FIG>) of IC 10a. That is, antenna element <NUM><NUM> is connected to the communication circuit <NUM><NUM>, antenna element <NUM><NUM> is connected to the communication circuit <NUM><NUM>, etc. <FIG> illustrates the resulting reference clock distribution, provided that the antenna elements <NUM>, of the other sub arrays 20b-d are connected to the communication circuits <NUM>, of the other ICs 10b-d according to the same pattern. The different fill patterns given to the different antenna elements illustrate which antenna elements are driven by what output buffer <NUM>m in the clock buffer circuit <NUM>. It should be noted that each antenna element driven by a given output buffer <NUM>m is affected by the phase noise introduced by that output buffer <NUM>m. As a comparison, <FIG> illustrates the corresponding situation in case each integrated circuit 10a-d had only had a single clock input terminal, with the clock input terminal of IC 10a connected to the output buffer <NUM><NUM>, the clock input terminal of IC 10b connected to the output buffer <NUM><NUM>, the clock input terminal of IC 10c connected to the output buffer <NUM><NUM>, and the clock input terminal of IC 10d connected to the output buffer <NUM><NUM>. Consider a situation where only the sub array 20a and IC 10a are enabled, whereas the other sub arrays 20b-d and ICs 10b-d are disabled for saving energy. In the comparative example illustrated in <FIG>, all then enabled antenna elements are affected by the phase noise from the same output buffer <NUM><NUM>. The phase noise among the enabled antenna elements therefore shows a relatively high average mutual correlation. Hence, the resulting suppression of the effects of phase noise due to averaging over the multiple enabled antenna elements is relatively poor. In the embodiment illustrated in <FIG>, on the other hand, the average mutual correlation of the phase noise among the enabled antenna elements is considerably lower, since only a fraction (in this case one fourth) of the enabled antenna elements are driven by the same output buffer <NUM>m of the clock buffer circuit <NUM>. Therefore, the resulting suppression of the effects of phase noise due to averaging over the multiple enabled antenna elements is considerably better than for the comparative example illustrated in <FIG>. Similar effects are obtained, but not to the same degree, when two or three of the sub arrays are enabled. When all four sub arrays 20a-d are enabled, the embodiment in <FIG> and the comparative example illustrated in <FIG> have about the same suppression of the phase noise due to averaging over the multiple antenna elements. However, the impact of the correlation of phase noise between antenna elements may be expected to be larger for adjacent antenna elements than for antenna elements that are a farther distance apart. As a consequence, the embodiment in <FIG> may actually provide some degree of improved suppression of the phase noise compared with the comparative example illustrated in <FIG> even when all four sub arrays are enabled.

In the examples presented above, the number of output buffers <NUM>m and clock wires <NUM>m are the same as the number of clock input terminals <NUM>m. Each output buffer <NUM>m of the clock buffer circuit <NUM> has its output terminal connected to exactly one of the clock input terminals <NUM>m of each one of the ICs 10a-d. In other embodiments, the number of output buffers <NUM>m of the clock buffer circuit <NUM> may be higher than the number of clock input terminals <NUM>m. Then, for a given one of the ICs 10a-d, an output buffer <NUM>m may have its output terminal to one or none of the clock input terminals <NUM>m of the given ICs 10a-d. A formulation that covers both the scenario wherein the number of output buffers <NUM>m is equal to the number of clock input terminals <NUM>m of each one of the ICs 10a-d and the scenario wherein the number of output buffers <NUM>m is higher than the number of clock input terminals <NUM>m of each one of the ICs 10a-d is that each output buffer <NUM>m of the clock buffer circuit <NUM> has its output terminal connected to at most one of the clock input terminals <NUM>m of the same one of the integrated circuits 10a-d.

Claim 1:
An integrated circuit (<NUM>, 10a-d) configured to be connected to an antenna module (<NUM>) having multiple antenna elements (<NUM>), the integrated circuit (<NUM>, 10a-d) comprising:
a plurality of communications circuits (<NUM>j), each of which is configured to be connected to an antenna element (<NUM>) of the antenna module (<NUM>);
a first clock input terminal (<NUM><NUM>) configured to receive a reference clock signal from outside the integrated circuit (<NUM>, 10a-d);
a first clock-distribution network (<NUM><NUM>) connected between the first clock input terminal (<NUM><NUM>) and a first subset (<NUM><NUM>) of the communication circuits (<NUM>j);
a second clock input terminal (<NUM><NUM>) configured to receive a reference clock signal from outside the integrated circuit (<NUM>, 10a-d);and
a second clock-distribution network (<NUM><NUM>) connected between the second clock input terminal (<NUM><NUM>) and a second subset (<NUM><NUM>) of the communication circuits (<NUM>j).