Patent Description:
Optical sensors, in particular indirect time of flight (iToF) sensors, may use pixels with gate modulated storage nodes or memory nodes. A shallow trench isolation (STI) structure may be used to provide the required electrical isolation for these storage nodes. However, such optical sensors may exhibit a comparatively strong dark current due to the fact that a large part to the dark current is caused by electron-hole recombination at the STI interface. In order to improve such optical sensors, it may be desirable to provide a pixel with an electrical isolation structure which has a reduced impact on the dark current. Furthermore, it may also be desirable for such an electrical isolation structure to show a reduced impact on full well capacitance of the storage nodes compared to e.g. a junction isolation structure. Improved optical sensors as well as improved methods for fabricating optical sensors may help with solving these and other problems.

Document <CIT> shows an optical sensor according to the prior-art.

The problem on which the invention is based is solved by the features of the independent claims. Further advantageous examples are described in the dependent claims.

Various aspects pertain to an optical sensor comprising at least one pixel, the pixel comprising: a photoactive region configured to convert photons into charge carriers, a first and a second modulation gate configured to be modulated for indirect time of flight measurement, a first and a second storage node arranged on opposite sides of the photoactive region, the first and second storage nodes being configured to pin electrons generated in the photoactive region when the first, respectively the second modulation gate is active, and a first field plate arranged next to the first storage node at a first lateral side of the pixel and a second field plate arranged next to the second storage node at an opposite second lateral side of the pixel, wherein the first and second field plates are configured to be supplied with a negative bias voltage such that the first and second field plates provide electrical isolation for the first, respectively the second storage node.

Various aspects pertain to a method for fabricating at least one pixel for an optical sensor, the method comprising: fabricating a photoactive region configured to convert photons into charge carriers, fabricating a first and a second modulation gate configured to be modulated for indirect time of flight measurement, fabricating a first and a second storage node on opposite sides of the photoactive region, the first and second storage nodes being configured to pin electrons generated in the photoactive region when the first, respectively the second modulation gate is active, and fabricating a first field plate next to the first storage node at a first lateral side of the pixel and fabricating a second field plate next to the second storage node at an opposite second lateral side of the pixel, wherein the first and second field plates are configured to be supplied with a negative bias voltage such that the first and second field plates provide electrical isolation for the first, respectively the second storage node.

The accompanying drawings illustrate examples and together with the description serve to explain principles of the disclosure. Other examples and many of the intended advantages of the disclosure will be readily appreciated in view of the following detailed description. Identical reference numerals designate corresponding similar parts.

In the following detailed description, directional terminology, such as "top", "bottom", "left", "right", "upper", "lower" etc., is used with reference to the orientation of the Figure(s) being described. Because components of the disclosure can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only. It is to be understood that other examples may be utilized and structural or logical changes may be made.

In addition, while a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application, unless specifically noted otherwise or unless technically restricted.

The terms "coupled" and "connected", along with derivatives thereof may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other; intervening elements or layers may be provided between the "bonded", "coupled", or "connected" elements. However, it is also possible that the "bonded", "coupled", or "connected" elements are in direct contact with each other. Also, the term "exemplary" is merely meant as an example, rather than the best or optimal.

In several examples layers or layer stacks are applied to one another or materials are applied or deposited onto layers. It should be appreciated that any such terms as "applied" or "deposited" are meant to cover literally all kinds and techniques of applying layers onto each other. In particular, they are meant to cover techniques in which layers are applied at once as a whole as well as techniques in which layers are deposited in a sequential manner.

An efficient optical sensor and an efficient method for fabricating an optical sensor may for example reduce material consumption, ohmic losses, chemical waste, etc. and thus enable energy and/or resource savings. Improved optical sensors and improved methods for fabricating an optical sensor, as specified in this description, may thus at least indirectly contribute to green technology solutions, i.e. climate-friendly solutions providing a mitigation of energy and/or resource use.

<FIG> shows a plan view of a pixel <NUM> comprising a photoactive region <NUM>, a first modulation gate <NUM>, a second modulation gate <NUM>, a first storage node <NUM>, a second storage node <NUM>, a first field plate <NUM> and a second field plate <NUM>.

The pixel <NUM> may be part of an optical sensor, wherein the optical sensor may comprise a single pixel <NUM> or a plurality of pixels <NUM>. The plurality of pixels may e.g. be arranged in an array. The array of pixels <NUM> may be part of a common substrate (this is indicated by the dashed outline of the pixel <NUM> in <FIG>). The optical sensor may for example be an active-pixel sensor (APS). The optical sensor may for example be (part of) a time of flight (ToF) sensor device, in particular an indirect ToF sensor device.

The pixel <NUM> may comprise any suitable semiconductor material, e.g. Si and/or Ge. The pixel <NUM> may for example be configured to be sensitive in the infrared (IR) and/or the near-IR spectrum, e.g. for incident light at a wavelength of about <NUM> and/or about <NUM>. According to an example, the pixel <NUM> is configured for backside illumination. According to another example, the pixel <NUM> is configured for front side illumination (wherein the front side is the side shown in <FIG>).

The photoactive region <NUM> is configured to convert incident photons into charge carriers, in particular into electrons and holes. The photoactive region <NUM> may in particular be configured to convert the incident photons into electrons and holes via the inner photoelectric effect. The photoactive region <NUM> may be fabricated in one or more epitaxial layers. The photoactive region <NUM> may for example comprise one or more n-type epitaxial layers, e.g. n-type epitaxial Si layers.

The first and second modulation gates <NUM>, <NUM> are configured to be modulated for indirect time of flight measurements. The first and second modulation gates <NUM>, <NUM> may essentially be arranged above the photoactive region <NUM>. The modulation gates <NUM>, <NUM> may in particular be arranged at the front side of the pixel <NUM>. The first and second modulation gates <NUM>, <NUM> may for example comprise or consist of a poly-Si structure.

The first storage node <NUM> and the second storage node <NUM> are arranged at opposite sides of the photoactive region <NUM> (in particular, the storage nodes <NUM>, <NUM> may be arranged close to opposite lateral edges of the pixel <NUM>). The first storage node <NUM> is configured to pin (or to bin) electrons generated in the photoactive region <NUM> when the first modulation gate <NUM> is active and the second storage node <NUM> is configured to pin (or to bin) electrons generated in the photoactive region <NUM> when the second modulation gate <NUM> is active.

The first and second storage nodes <NUM>, <NUM> may be arranged below the front side of the pixel <NUM> (this is indicated in <FIG> by the dashed outlines of the storage nodes <NUM>, <NUM>). The storage nodes <NUM>, <NUM> may for example be arranged closer to the front side of the pixel <NUM> than to a backside of the pixel <NUM>.

According to an example, the first and second storage nodes <NUM>, <NUM> are memory nodes of the pixel <NUM>. According to another example, the first and second storage nodes <NUM>, <NUM> are pinned diodes of the pixel <NUM>. The storage nodes <NUM>, <NUM> may be arranged within one or more epitaxial layers of the pixel <NUM>. The storage nodes <NUM>, <NUM> may for example comprise an n-doped region of the pixel <NUM>. The storage nodes <NUM>, <NUM> may be surrounded by p-wells of the pixel <NUM>.

The first field plate <NUM> is arranged next to the first storage node <NUM> at a first lateral side of the pixel <NUM> and the second field plate <NUM> is arranged next to the second storage node <NUM> at an opposite second lateral side of the pixel <NUM> (wherein the lateral sides of the pixel <NUM> are indicated by dashed lines in <FIG>). The first and second field plates <NUM>, <NUM> are configured to be supplied with a negative bias voltage such that the first and second field plates <NUM>, <NUM> provide electrical isolation for the first, respectively the second storage node <NUM>, <NUM>. In this context "providing electrical isolation" for the storage nodes <NUM>, <NUM> may mean that the field plates <NUM>, <NUM> are configured to electrically isolate the storage nodes <NUM>, <NUM> towards one or more other pixels arranged next to the pixel <NUM>. In this way, no electrons or almost no electrons generated in the one or more neighboring pixels can diffuse into the storage nodes <NUM>, <NUM> (such electrons would contribute to a dark current).

The field plates <NUM>, <NUM> may be used instead of a junction isolation or instead of a shallow trench isolation (STI) for isolating the storage nodes <NUM>, <NUM>. Using the field plates <NUM>, <NUM> instead of an STI, the pixel <NUM> may exhibit a reduced dark current because a comparatively large contribution to the dark current comes from recombinations at the STI interface. This contribution can be eliminated by employing the field plates <NUM>, <NUM> instead. Furthermore, the field plates <NUM>, <NUM> may have less of an impact on full well capacitance of the storage nodes <NUM>, <NUM> compared to a junction isolation.

The field plates <NUM>, <NUM> may for example comprise a first, respectively a second polysilicon structure. The polysilicon structure may be arranged at or over the front side of the pixel <NUM>, for example in the same plane as the modulation gates <NUM>, <NUM>. In this case, the field plates <NUM>, <NUM> may be fabricated in the same process as the modulation gates <NUM>, <NUM>.

According to another example, the field plates <NUM>, <NUM> may comprise a first, respectively a second trench which may extend into one or more epitaxial layers and possibly also into a bulk semiconductor part of the pixel <NUM>. The trenches may for example extend into the pixel <NUM> from the front side of the pixel <NUM>. The trenches comprise an electrically conductive coating or an electrically conductive filling such that the bias voltage can be applied.

In general, the field plates <NUM>, <NUM> may comprise any suitable structure and any suitable material configured to be supplied with the bias voltage such that the storage nodes <NUM>, <NUM> can be electrically isolated as described above. In order to provide the bias voltage, the field plates <NUM>, <NUM> may be electrically coupled to contacts of the pixel <NUM> (in particular, the first field plate <NUM> may be coupled to a first contact and the second field plate <NUM> may be coupled to a second contact). The contacts may for example comprise metal traces.

According to an example, these contacts are at least partially arranged within a dielectric layer, wherein the dielectric layer is arranged above the photoactive region <NUM>, above the first and second modulation gates <NUM>, <NUM> and above the first and second field plates <NUM>, <NUM> (in other words, the contacts are arranged at the front side of the pixel <NUM>). The dielectric layer may in particular cover the modulation gats <NUM>, <NUM> and the field plates <NUM>, <NUM>. The dielectric layer may for example comprise an oxide, e.g. silicon oxide.

According to another example, the contacts are at least partially arranged within a semiconductor substrate of the pixel <NUM>. In this case, the contacts may comprise vias.

The field plates <NUM>, <NUM> may have any suitable shape and any suitable dimensions. The field plates <NUM>, <NUM> may for example have a rectangular footprint as shown in <FIG>. The footprint may for example have a length measured along a longer side of the footprint in the range of about <NUM> to about <NUM>. The lower limit of this range may also be about <NUM>, about <NUM>, about <NUM>, or about <NUM>. The upper limit of this range may also be about <NUM>, about <NUM>, about <NUM>, or about <NUM>. The footprint may for example have a width measured along a shorter side of the footprint in the range of about <NUM> to about <NUM>. The lower limit of this range may also be about <NUM>, about <NUM>, about <NUM>, about <NUM>, or about <NUM>. The upper limit of this range may also be about <NUM>, about <NUM>, about <NUM>, or about <NUM>.

According to an example, the pixel <NUM> may be part of an array of pixels, wherein the first field plate <NUM> is shared between the pixel <NUM> and a first adjacent pixel and/or wherein the second field plate <NUM> is shared between the pixel <NUM> and a second adjacent pixel. In other words, the first and second field plates <NUM>, <NUM> are configured to provide electrical isolation for respective storage nodes of respective adjacent pixels.

In the example shown in <FIG> the pixel <NUM> comprises two storage nodes <NUM>, <NUM> and two field plates <NUM>, <NUM>. However, the pixel <NUM> may comprise any suitable number of storage nodes and/or field plates, for example three storage nodes or four storage nodes and/or three field plates or four field plates. The further storage nodes and/or further field plates may for example be arranged at one or more of the remaining lateral sides of the pixel <NUM>.

<FIG> shows an optical sensor <NUM> comprising a sensor part <NUM> and a control part <NUM>. The sensor part <NUM> comprises one or more pixels <NUM>, in particular an array of pixels <NUM>. The control part <NUM> is configured to control the sensor part <NUM>.

For example, the control part <NUM> may be configured to control the modulation gates <NUM>, <NUM> of the pixel <NUM>. The control part <NUM> may also be configured to set a voltage value of the bias voltage for the field plates <NUM>, <NUM>. The control part <NUM> may in particular be configured to set the negative bias voltage to a first voltage value during a light detection state of the pixel <NUM> and to set the negative bias voltage to a second, higher voltage value (i.e. a more negative voltage value) during a readout state of the pixel. The second, higher voltage value may help with flushing the photo-electrons out of the storage nodes <NUM>, <NUM> during read out of the pixel <NUM>. This may speed up the readout process.

According to an example, the control part is configured to set identical voltage values for the bias voltage of the first field plate <NUM> and the second field plate <NUM>. According to another example, the control part may set different voltage values for the bias voltage of the first field plate <NUM> on the one hand and the second field plate <NUM> on the other hand.

<FIG> show sectional views of the pixel <NUM> according to two different specific examples.

In the example shown in <FIG>, the pixel <NUM> comprises first and second field plates <NUM>, <NUM> which comprise or consist of a first and a second polysilicon structure. The field plates <NUM>, <NUM> (in particular, the polysilicon structures) may for example be arranged in (or over) a dielectric layer <NUM> of the pixel <NUM>. The field plates <NUM>, <NUM> may be arranged above a semiconductor part <NUM> of the pixel <NUM>. The semiconductor part <NUM> may comprise one or more epitaxial layers, wherein the one or more epitaxial layers comprise the photoactive region <NUM>. The semiconductor part <NUM> may further comprise a bulk semiconductor part, wherein the one or more epitaxial layers are arranged over the bulk semiconductor part. The field plates <NUM>, <NUM> may be separated from the epitaxial layer(s) by the dielectric layer <NUM> or by a part of the dielectric layer <NUM> (i.e. a lower layer of a layer stack). In other words, in this example the field plates <NUM>, <NUM> do not extend into the epitaxial layers. In particular, the dielectric layer <NUM> is arranged between the field plates <NUM>, <NUM> and the storage nodes <NUM>, <NUM>. The dielectric layer <NUM> may comprise a layer stack. The dielectric layer <NUM> may comprise or consist of an oxide layer.

As shown in <FIG>, the first field plate <NUM> may be coupled to a first contact <NUM> and the second field plate <NUM> may be coupled to a second contact <NUM>. The first and second contacts <NUM>, <NUM> may e.g. comprise or consist of metal traces extending at least partially through the dielectric layer <NUM>.

In the example shown in <FIG>, the pixel <NUM> comprises first and second field plates <NUM>, <NUM> which comprise or consist of a first trench and a second trench. The first and second trenches comprise an electrically conductive coating or the first and second trenches are filled with electrically conductive material such that the bias voltage can be applied. The trenches may be coupled to first and second contacts (not shown in <FIG>). The contacts may e.g. extend towards the front side <NUM> or towards the backside <NUM> of the pixel <NUM>.

As shown in <FIG>, the pixel <NUM> may comprise the front side <NUM> and the backside <NUM>. The backside <NUM> may be a side of the bulk semiconductor part of the pixel <NUM>.

A thickness of the pixel <NUM> measured between the front side <NUM> and the backside <NUM> may for example be in the range of <NUM> to <NUM>. The lower limit of this range may also be about <NUM>, or about <NUM> and the upper limit may also be about <NUM>, or about <NUM>. A width of the pixel <NUM> measured between opposite lateral sides (the lateral sides are indicated by vertical dashed lines in <FIG>) may for example be in the range of <NUM> to <NUM>. The lower limit of the range may also be about <NUM> or about <NUM> and the upper limit may also be about <NUM>.

<FIG> shows a plan view of a further pixel <NUM> which may be similar or identical to the pixel <NUM>. The pixel <NUM> may comprise all components described with respect to the pixel <NUM> and it may further comprise the components described in the following.

The pixel <NUM> may for example comprise further polysilicon structures. The pixel <NUM> may for example comprise a third modulation gate <NUM> which may be arranged between the first and second modulation gates <NUM>, <NUM>. Similar to the first and second modulation gates <NUM>, <NUM>, the third modulation gate <NUM> may be configured to enable indirect time of flight measurements with the pixel <NUM>.

The pixel <NUM> may for example comprise a first transfer gate <NUM> and a second transfer gate <NUM>. The first transfer gate <NUM> may be configured to transfer electrons accumulated in the first storage node <NUM> to a first readout part (not shown) at the end of the integration time interval for readout of the pixel <NUM>. Similarly, the second transfer gate <NUM> may be configured to transfer electrons accumulated in the second storage node <NUM> to a second readout part (also not shown). Note that the storage nodes <NUM>, <NUM> are not shown in <FIG>.

According to an example, the pixel <NUM> may further comprise a drain <NUM>. The drain <NUM> may for example be arranged laterally next to the modulation gates <NUM>, <NUM> and <NUM>.

<FIG> shows an exemplary optical sensor unit <NUM> which may comprise a sensor part <NUM> and optionally an emitter part <NUM>. The sensor part <NUM> may comprise the optical sensor <NUM> with one or more pixels <NUM> or <NUM>, in particular an array of pixels <NUM> or <NUM>. The optical sensor unit <NUM> may for example be a time of flight sensor unit configured to measure a distance d to an object <NUM> and/or to measure a speed of the object <NUM>. The optional emitter part <NUM> is configured for emitting photons. According to another example, the sensor part <NUM> and the emitter part <NUM> are part of separate units.

According to an example, the optical sensor unit <NUM> (and consequently, the pixel <NUM> or the pixel <NUM>) is configured for front side illumination. According to another example, the optical sensor unit <NUM> (and consequently, the pixel <NUM> or the pixel <NUM>) is configured for backside illumination.

<FIG> is a flow chart of a method <NUM> for fabricating at least one pixel for an optical sensor. The method <NUM> may for example be used to fabricate the pixels <NUM> and <NUM>.

The method <NUM> comprises at <NUM> a process of fabricating a photoactive region configured to convert photons into charge carriers, at <NUM> a process of fabricating a first and a second modulation gate configured to be modulated for indirect time of flight measurement, at <NUM> a process of fabricating a first and a second storage node on opposite sides of the photoactive region, the first and second storage nodes being configured to pin electrons generated in the photoactive region when the first, respectively the second modulation gate is active, and at <NUM> a process of fabricating a first field plate next to the first storage node at a first lateral side of the pixel and fabricating a second field plate next to the second storage node at an opposite second lateral side of the pixel, wherein the first and second field plates are configured to be supplied with a negative bias voltage such that the first and second field plates provide electrical isolation for the first, respectively the second storage node.

Claim 1:
An optical sensor, comprising:
at least one pixel (<NUM>), comprising:
a photoactive region (<NUM>) configured to convert photons into charge carriers,
a first and a second modulation gate (<NUM>, <NUM>) configured to be modulated for indirect time of flight measurement,
a first and a second storage node (<NUM>, <NUM>) arranged on opposite sides of the photoactive region (<NUM>), the first and second storage nodes (<NUM>, <NUM>) being configured to pin electrons generated in the photoactive region (<NUM>) when the first, respectively the second modulation gate (<NUM>, <NUM>) is active, and
a first field plate (<NUM>) arranged next to the first storage node (<NUM>) at a first lateral side of the pixel (<NUM>) and a second field plate (<NUM>) arranged next to the second storage node (<NUM>) at an opposite second lateral side of the pixel (<NUM>),
characterised in that
the first and second field plates (<NUM>, <NUM>) are configured to be supplied with a negative bias voltage such that the first and second field plates (<NUM>, <NUM>) provide electrical isolation for the first, respectively the second storage node (<NUM>, <NUM>).