Patent Description:
Gallium nitride (GaN) based light emitting diodes (LEDs) have been applied and developed for about <NUM> years. GaN-based LEDs represent a significant change in LED technology and are used in a wide range of applications including natural color LED display devices, LED traffic sign boards, white LEDs, etc. In recent years, a highly efficient white LED is expected to replace fluorescent lamps and, in particular, efficiency of the white LED approaches an efficiency level of typical fluorescent lamps.

The GaN-based light emitting diode is generally formed by growing epitaxial layers on a substrate, for example, a sapphire substrate, and includes an N-type semiconductor layer, a P-type semiconductor layer and an active layer interposed between the N-type semiconductor layer and the P-type semiconductor layer. Further, an N electrode is formed on the N-type semiconductor layer and a P electrode is formed on the P-type semiconductor layer. The light emitting diode is electrically connected to and operated by an external power source through these electrodes. Here, electric current is directed from the P-electrode to the N-electrode through the semiconductor layers.

Generally, since the P-type semiconductor layer has high specific resistance, electric current is not evenly distributed in the P-type semiconductor layer, but is concentrated on a portion of the P-type semiconductor layer having the P-electrode formed thereon, causing a problem of current concentration on an edge of the P-type semiconductor layer. The current concentration leads to a reduction in light emitting area, thereby deteriorating luminous efficacy. To solve such problems, a transparent electrode layer having low specific resistance is formed on the P-type semiconductor layer so as to enhance current distribution. In this structure, when supplied from the P-electrode, the electric current is dispersed by the transparent electrode layer before entering the P-type semiconductor layer, thereby increasing a light emitting area of the LED.

However, since the transparent electrode layer tends to absorb light, the thickness of the transparent electrode layer is limited, thereby providing limited current dispersion. In particular, for a large area LED having an area of about <NUM><NUM> or more for high output, there is a limit in current dispersion through the transparent electrode layer.

Meanwhile, the electric current flows into the N electrode through the semiconductor layers. Accordingly, the electric current concentrates on a portion of the N-type semiconductor layer having the N-electrode formed thereon, that is, the current flowing in the semiconductor layers concentrates near a region of the N-type semiconductor layer on which the N-electrode is formed. Therefore, there is a need for a light emitting diode solving the problem of current concentration within the N-type semiconductor layer.

Typically, various types of electrode structures are used for the light emitting diode to ensure uniform current dispersion.

<FIG> illustrates a light emitting diode having a diagonal electrode structure.

In <FIG>, reference numeral <NUM> denotes an N electrode, <NUM> denotes a P electrode, <NUM> denotes an exposed N-type semiconductor layer, and <NUM> denotes a transparent electrode layer.

Referring to <FIG>, the diagonal electrode structure is highly effective for a small LED, but causes an increasing concentration of electric current on a central region of the LED as the size of the LED increases, such that only the central region of the LED emits light. In addition, an electrode pattern of a simple facing type structure also suffers from the same problem as the diagonal electrode structure.

<FIG> illustrates a light emitting diode having a combined electrode structure of a facing type structure and a symmetrical extension type structure, and <FIG> is a cross-sectional view taken along line A-A' of <FIG>.

In <FIG>, reference numeral <NUM> denotes a substrate, <NUM> denotes an N-type semiconductor layer, <NUM> denotes an active layer, <NUM> denotes a P-type semiconductor layer, <NUM> denotes a transparent electrode layer, <NUM> denotes an N electrode, <NUM> and <NUM> denote extension parts of the N electrode, <NUM> denotes a P electrode, and <NUM> and <NUM> denote extension parts of the P electrode.

Referring to <FIG>, the combined electrode structure of the facing type structure and the symmetrical extension type structure is generally used for large sized LEDs. It can be appreciated that the extension parts <NUM>, <NUM>, <NUM>, <NUM> of the electrodes are formed over a light emitting area of an LED chip with an increased area for ensuring uniform current distribution over the light emitting area.

For the combined type structure, however, since the N-type semiconductor layer <NUM> is exposed by mesa-etching to form the extension parts <NUM>, <NUM> of the P electrode <NUM> and the extension parts <NUM>, <NUM> of the N electrode <NUM>, the light emitting area is inevitably.

Moreover, in the current state of the art, the number of electrode pads formed on a single chip is more than doubled for current diffusion, and a mesa-etching area for forming electrodes and extension parts of these electrodes is also expanded. Expansion of the mesa-etching area caused by increase in the number of electrode pads results in a decrease of a light emitting area based on the same chip area, thereby deteriorating light emitting efficiency.

US patent publication No. <CIT> provides A flip-chip LED including a light emitting structure, a first dielectric layer, a first metal layer, a second metal layer, and a second dielectric layer. European patent publication <CIT> discloses a flip-chip LED having a light emitting structure in the form of a mesa having an inclined side surface, an insulating laser over the inclined side surface and a first electrode having an extension portion overlying the insulating layer over the inclined side surface.

US patent publication <CIT> discloses a light emitting diode structure having a distributed Bragg reflector structure.

According to the present invention, a light emitting diode is provided, as defined by independent claim <NUM>. The light emitting diode according to the present invention is configured to prevent a reduction in light emitting area resulting from formation of an electrode or electrode pad. Advantageous embodiments are provided in dependent claims.

Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.

Still other aspects, features, and advantages of the present invention are readily apparent from the following detailed description, simply by illustrating a number of particular embodiments and implementations, including the best mode for carrying out the present invention. The present invention can take the form of a variety of different embodiments, and several details can be modified in various obvious respects, all without departing from the scope of the present invention as defined by the appended claims. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.

Exemplary embodiments of the present invention disclose a light emitting diode. The light emitting diode includes a lower semiconductor layer formed on a substrate; an upper semiconductor layer disposed above the lower semiconductor layer to expose at least a portion of edge regions of the lower semiconductor layer; a first electrode formed on a region of the upper semiconductor layer, with an insulation layer interposed between the first electrode and the region of the upper semiconductor layer, to supply electric current to the lower semiconductor layer; a second electrode formed on another region of the upper semiconductor layer to supply electric current to the upper semiconductor layer; and an extension part of the first electrode extending from the first electrode to at least a portion of the exposed lower semiconductor layer.

The insulation layer may be formed by alternately stacking at least two insulation layers having different indices of refraction one above another. Here, the insulation layers positioned at the outermost sides may comprise a Si compound. The Si compound may be SiO<NUM>.

The insulation layer may be formed over the entire upper surface of the upper semiconductor layer.

The insulation layer may include an insulation layer of a DBR structure under the first electrode.

The light emitting diode may further include an insulation layer of a DBR structure under the extension part of the first electrode in a mesa surface region formed to expose the at least a portion of the edge regions of the lower semiconductor layer.

The light emitting diode may further include an insulation layer of a DBR structure around the extension part of the first electrode formed to reach the at least a portion of the exposed lower semiconductor layer.

The insulation layer of the DBR structure may be formed by alternately stacking at least two insulation layers having different indices of refraction one above another. Here, the insulation layers positioned at the outermost sides may comprise a Si compound. The Si compound may be SiO<NUM>.

The light emitting diode may further include an insulation layer of a DBR structure under the second electrode.

The extension part of the first electrode is formed on an inclined mesa surface extending from the upper semiconductor layer to the lower semiconductor layer.

The light emitting diode may further include an extension part of the second electrode extending from the second electrode on the upper semiconductor layer.

The substrate may further include an insulation layer of a DBR structure.

The insulation layer of the DBR structure may be formed by alternately stacking at least two insulation layers having different indices of refraction one above another. Here, the insulation layers at the outermost sides may comprise a Si compound. The Si compound may be SiO<NUM>.

The substrate may be a PSS substrate and the insulation layer of the DBR structure may be formed on a PSS region of the substrate.

The insulation layer of the DBR structure may be formed on a bottom surface of the substrate.

The light emitting diode may further include a transparent electrode layer on the upper semiconductor layer.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.

The invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

<FIG> is a plan view of a light emitting diode according to one exemplary embodiment, and <FIG> is a cross-sectional view taken along line A-A of <FIG>.

Referring to <FIG>, a first conductive lower semiconductor layer <NUM> is formed on a substrate <NUM>. The substrate <NUM> is not limited to a particular material, and may be a sapphire substrate.

A second conductive upper semiconductor layer <NUM> is formed above the first conductive lower semiconductor layer <NUM>. The upper semiconductor layer <NUM> is positioned within a region surrounded by edges of the lower semiconductor layer <NUM> to expose at least a portion of edge regions of the lower semiconductor layer <NUM>. Meanwhile, an active layer <NUM> is interposed between the lower semiconductor layer <NUM> and the upper semiconductor layer <NUM>. The active layer <NUM> is positioned under the upper semiconductor layer <NUM> while exposing the at least a portion of the edge regions of the lower semiconductor layer <NUM>.

The lower semiconductor layer <NUM>, active layer <NUM> and upper semiconductor layer <NUM> may be formed of, but not limited to, a GaN-based compound semiconductor material such as (B, Al, In, Ga)N. The active layer <NUM> is composed of elements determined to emit light at desired frequencies, for example, UV or blue light. The lower semiconductor layer <NUM> and the upper semiconductor layer <NUM> are formed of materials having a greater band gap than the active layer <NUM>.

As shown in the drawings, the lower semiconductor layer <NUM> and/or the upper semiconductor layer <NUM> may have a single layer structure or a multilayer structure. Further, the active layer <NUM> may have a single quantum well structure or a multi-quantum well structure. The light emitting diode may further include a buffer layer (not shown) between the substrate <NUM> and the lower semiconductor layer <NUM>. The buffer layer is selected to relieve lattice mismatch between the substrate <NUM> and the lower semiconductor layer <NUM> formed thereon.

These semiconductor layers <NUM>, <NUM>, <NUM> may be formed by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). According to the current invention, they are subjected to mesa-etching to expose regions of the lower semiconductor layer <NUM> via photolithography and etching.

Here, mesa-etching may be performed to form an inclined mesa surface on the semiconductor layer. The mesa surface may have a degree of inclination in the range of <NUM>~<NUM> degrees, and preferably in the range of <NUM>~<NUM> degrees.

The inclined mesa surface may enhance workability and reliability when forming a second insulation layer <NUM> of a DBR structure and an inclined extension part <NUM> of the first electrode described below. In addition, the inclined mesa surface increases a light emitting area.

An insulation layer is formed on the upper semiconductor layer <NUM>. The insulation layer may include a first insulation layer <NUM> and a second insulation layer <NUM>. The first insulation layer <NUM> is formed on the entire upper surface of the upper semiconductor layer <NUM> and the inclined surface which is formed by mesa etching, and may be formed of, for example, SiO<NUM>, Si<NUM>N<NUM>, Nb<NUM>O<NUM>, TiO<NUM>, etc..

The second insulation layer <NUM> may be formed on a selected region of the upper semiconductor layer <NUM> where the first electrode <NUM> is to be formed, and a selected region of the mesa surface where the inclined extension part <NUM> of the first electrode <NUM> is to be formed, the mesa surface being formed by the mesa etching.

The second insulation layer <NUM> may be formed, for example, in a distributed Bragg reflector (DBR) structure by alternately stacking materials, which have a great difference in index of refraction therebetween.

The DBR layer is used to provide high reflectivity to a variety of light emitting devices, which have a light emitting function, a light detection function, a light conversion function, etc. The DBR layer may be formed by alternately stacking two kinds of media having different indices of refraction to reflect light based on the difference between the indices of refraction.

The second insulation layer <NUM> is formed by alternately stacking two or more insulation layers having different indices of refraction, for example, SiO<NUM>, Si<NUM>N<NUM>, Nb<NUM>O<NUM>, or TiO<NUM>. The second insulation layer <NUM> may be formed by alternately stacking, for example, multiple layers of SiO<NUM> and TiO<NUM> or multiple layers of SiO<NUM> and Si<NUM>N<NUM> , followed by etching the stacked insulation layers in a predetermined pattern using photolithography.

Here, the insulation layers are stacked such that insulation layers comprising a Si compound, that is, SiO<NUM>, become the outermost layers. TiO<NUM> may suffer from deformation when subjected to thermal stress. If an insulation layer of TiO<NUM> is positioned at the outermost side when forming the second insulation layer <NUM> by alternately stacking SiO<NUM> and TiO<NUM>, cracking of the second insulation layer <NUM> may occur after deposition of the second insulation layer <NUM>. However, when stacking multiple layers of SiO<NUM> layers and TiO<NUM> layers by first stacking a SiO<NUM> layer exhibiting less response to thermal stress at the outermost side and then stacking a TiO<NUM> layer on the SiO<NUM> layer, the second insulation layer <NUM> exhibits thermal stability, thereby preventing cracking of the second insulation layer <NUM> after deposition thereof. Likewise, it is desirable that the second insulation layer <NUM> include a SiO<NUM> insulation layer as the outermost layer, which is finally deposited. This structure may guarantee reliability of the second insulation layer <NUM>. Since the second insulation layer <NUM> is formed by alternately stacking the insulation layers having different indices of refraction one above another, the second insulation layer <NUM> may have functions of the DBR. Accordingly, when light emitted from the active layer <NUM> is directed towards the first electrode <NUM>, the second insulation layer <NUM> may reflect the light, thereby effectively preventing the light emitted from the active layer <NUM> from being absorbed or blocked by the first electrode <NUM>.

Further, a DBR layer 111b may be formed on a PSS region 111a of the substrate <NUM>.

In another embodiment, an insulation layer having the DBR structure is also formed under the second electrode <NUM> excluding a portion contacting the upper semiconductor layer <NUM>, as well as the second insulation layer <NUM> of the DBR structure formed under the first electrode <NUM>.

In another embodiment, an insulation layer of the DBR structure is also formed on an exposed portion of the lower semiconductor layer <NUM> in order to improve emission of light reflected by the second insulation layer <NUM> under the first electrode <NUM> or on the mesa surface. According to the current invention, a DBR layer 111c is formed on a bottom side of the substrate <NUM>, as shown in <FIG>.

The first electrode <NUM> is formed in a first region on the upper semiconductor layer <NUM>, with the first and second insulation layers <NUM>, <NUM> interposed between the first electrode <NUM> and the upper semiconductor layer <NUM>. An inclined extension part <NUM> and a lower extension part <NUM> of the first electrode extend from the first electrode <NUM> to an edge region of the exposed lower semiconductor layer <NUM> and are formed along a first side of the substrate. The first electrode <NUM>, the inclined extension part <NUM> and the lower extension part <NUM> of the first electrode may be formed of the same material using the same process. For example, if the lower semiconductor layer is an N-type semiconductor layer, the first electrode <NUM>, the inclined extension part <NUM> and the lower extension part <NUM> of the first electrode may be formed of Ti/Al using a lift-off process.

Further, the second electrode <NUM> is formed in a second region on the upper semiconductor layer <NUM>. The second electrode <NUM> is positioned near a corner between a second side adjacent the first side and a third side adjacent the second side on the upper semiconductor layer <NUM>.

A transparent electrode layer (not shown) may be formed on the upper semiconductor layer <NUM> before forming the first insulation layer <NUM>. Generally, the transparent electrode layer is formed of indium tin oxide (ITO) or Ni/Au and has transparency. In addition, the transparent electrode layer may lower contact resistance through ohmic contact with the upper semiconductor layer <NUM>. On the other hand, the second electrode <NUM> has neither transparency nor forms an ohmic contact with the upper semiconductor layer <NUM>. A portion of the second electrode <NUM> is formed to contact with the upper semiconductor layer <NUM>, and the other portion of the second electrode <NUM> is formed to contact with the transparent electrode layer. Consequently, the second electrode <NUM> is configured to form a direct contact with the upper semiconductor layer <NUM>, thereby preventing electric current from flowing under the second electrode <NUM>. Therefore, the light is not generated in the domain of the active layer which is placed under the second electrode <NUM>, but generated in the domain of the active layer which is placed under the transparent electrode layer. With this structure, it is possible to minimize the light emitted from the active layer being absorbed and lost by the second electrode <NUM>.

Meanwhile, a first extension part <NUM> of the second electrode extends from the second electrode <NUM> on the upper semiconductor layer <NUM> to be formed adjacent the second side. A second extension part <NUM> of the second electrode extends from the second electrode <NUM> on the upper semiconductor layer <NUM> to be formed adjacent the third side. The second electrode <NUM> and the first and second extension parts <NUM>, <NUM> of the second electrode may be formed of the same material using the same process.

Improvement in light emitting area of the light emitting diode according to the embodiment will be described with reference to comparison of <FIG> with <FIG>.

In <FIG> and <FIG>, it can be seen that there is a great difference between the conventional technique and the embodiment in term of reduction in light emitting area resulting from formation of the lower electrode <NUM> and the first electrode <NUM>, each of which is formed to supply electric current to the lower semiconductor layer. Namely, in the light emitting diode of <FIG>, an area of the light emitting area including the active layer <NUM> is removed for formation of the lower electrode <NUM> during mesa etching. On the contrary, in the light emitting diode of <FIG>, the first electrode <NUM> is formed above the upper semiconductor layer <NUM>, with the first and second insulation layers <NUM>, <NUM> interposed between the first electrode and the upper semiconductor layer <NUM>, and the active layer <NUM> remains unetched. Accordingly, the light emitting diode according to the embodiment provides an effective solution of the problem of the related art, in which the light emitting area is reduced due to the formation of the electrode.

In addition, as can be seen from <FIG>, the second insulation layer <NUM> of the DBR structure formed under the first electrode <NUM> allows light to be effectively emitted to the outside instead of being absorbed or blocked by the first electrode <NUM>.

<FIG> is a plan view of a light emitting diode according to a further exemplary embodiment, <FIG> is a cross-sectional view taken along line B-B' of <FIG>, and <FIG> is a cross-sectional view taken along line C-C' of <FIG>.

The embodiment shown in <FIG> is different from the embodiment of <FIG> in terms of the number, positions and shapes of first and second electrodes, and the shapes of extension parts of the first and second electrodes.

Referring to <FIG>, <FIG>, first electrodes <NUM>, <NUM> are formed to face second electrodes <NUM>, <NUM> on an upper semiconductor layer <NUM>. Each of extension parts <NUM>, <NUM> of the first electrodes is positioned between extension parts <NUM>, <NUM> or extension parts <NUM>, <NUM> of the second electrodes to face each other.

A first conductive lower semiconductor layer <NUM> is formed on a substrate <NUM>. The substrate <NUM> is not limited to a particular material, and may be a sapphire substrate.

These semiconductor layers <NUM>, <NUM>, <NUM> may be formed by MOCVD or MBE and may be subjected to mesa-etching to expose regions of the lower semiconductor layer <NUM> via photolithography and etching.

The inclined mesa surface may enhance workability and reliability when forming a DBR layer <NUM> and an inclined extension part <NUM> of the first electrode described below. In addition, the inclined mesa surface provides an effect of increasing a light emitting area.

An insulation layer is formed on the upper semiconductor layer <NUM>. The insulation layer may include a first insulation layer <NUM> and a second insulation layer <NUM>. The first insulation layer <NUM> is formed on entire upper surface of the upper semiconductor layer <NUM> and the inclined mesa surface which is formed by mesa etching, and may be formed of, for example, SiO<NUM>, Si<NUM>N<NUM>, Nb<NUM>O<NUM>, TiO<NUM>, etc..

The second insulation layer <NUM> may be formed on a selected region of the upper semiconductor layer <NUM> where the first electrodes <NUM>, <NUM> is to be formed, and a selected region of the mesa surface where the inclined extension parts <NUM>, <NUM> of the first electrodes <NUM>, <NUM> are to be formed, the mesa surface being formed by the mesa etching.

The second insulation layer <NUM> may be formed, for example, in a DBR structure by alternately stacking materials, which have a great difference in index of refraction therebetween.

The second insulation layer <NUM> is formed by alternately stacking two or more insulation layers having different indices of refraction, for example, SiO<NUM>, Si<NUM>N<NUM>, Nb<NUM>O<NUM>, or TiO<NUM>. The second insulation layer <NUM> may be formed by alternately stacking, for example, multiple layers of SiO<NUM> and TiO<NUM> or multiple layers of SiO<NUM> and Si<NUM>N<NUM>, followed by etching a predetermined pattern into the stacked insulation layers using photolithography.

Here, the insulation layers are stacked such that insulation layers comprising a Si compound, that is, SiO<NUM>, become the outermost layers. TiO<NUM> may suffer from deformation when subjected to thermal stress. If an insulation layer of TiO<NUM> is positioned at the outermost side when forming the second insulation layer <NUM> by alternately stacking SiO<NUM> and TiO<NUM>, cracking of the second insulation layer <NUM> may occur after deposition of the second insulation layer <NUM>. However, when stacking multiple layers of SiO<NUM> layers and TiO<NUM> layers by first stacking a SiO<NUM> layer exhibiting less response to thermal stress at the outermost side and then stacking a TiO<NUM> layer on the SiO<NUM> layer, the second insulation layer <NUM> exhibits thermal stability, thereby preventing cracking of the second insulation layer <NUM> after deposition thereof. Likewise, it is desirable that the second insulation layer <NUM> include a SiO<NUM> insulation layer as the outermost layer, which is finally deposited. This structure may guarantee reliability of the second insulation layer <NUM>.

Since the second insulation layer <NUM> is formed by alternately stacking the insulation layers having different indices of refraction one above another, the second insulation layer <NUM> may have functions of the DBR. Accordingly, when light emitted from the active layer <NUM> is directed towards the first electrodes <NUM>, <NUM>, the second insulation layer <NUM> may reflect the light, thereby effectively preventing the light emitted from the active layer <NUM> from being absorbed or blocked by the first electrodes <NUM>, <NUM>.

Further, a DBR layer 211b may be formed on a PSS region 211a on the substrate <NUM>.

In yet another embodiment, an insulation layer having the DBR structure is also formed under the second electrodes <NUM>, <NUM> excluding a portion contacting the upper semiconductor layer <NUM>, as well as the second insulation layer <NUM> of the DBR structure formed under the first electrodes <NUM>, <NUM>.

In yet another embodiment, an insulation layer of the DBR structure is also formed on an exposed portion of the lower semiconductor layer <NUM> in order to improve emission of light reflected by the second insulation layer <NUM> under the first electrodes <NUM>, <NUM> or on the mesa surface. In yet another embodiment, a DBR layer 211c may be formed on a bottom side of the substrate <NUM>, as shown in <FIG>.

The first electrodes <NUM>, <NUM> are formed in a first region on the upper semiconductor layer <NUM>, with the first and second insulation layers <NUM>, <NUM> interposed between the first electrodes and the upper semiconductor layer. The extension parts <NUM>, <NUM> of the first electrodes extend from the first electrodes <NUM>, <NUM> to an edge region of the exposed lower semiconductor layer <NUM>. The first electrodes <NUM>, <NUM> and the extension parts <NUM>, <NUM> of the first electrodes may be formed of the same material using the same process. For example, if the lower semiconductor layer is an N-type semiconductor layer, the first electrodes <NUM>, <NUM> and the extension parts <NUM>, <NUM> of the first electrodes may be formed of Ti/Al using a lift-off process.

Further, the second electrodes <NUM>, <NUM> are formed in a second region on the upper semiconductor layer <NUM>. The second electrodes <NUM>, <NUM> are positioned near an edge of a second side facing a first side on the upper semiconductor layer <NUM> to be separated a predetermined distance from each other.

A transparent electrode layer (not shown) may be formed on the upper semiconductor layer <NUM> before forming the first insulation layer <NUM>. Generally, the transparent electrode layer is formed of indium tin oxide (ITO) or Ni/Au and has transparency. In addition, the transparent electrode layer may lower contact resistance through ohmic contact with the upper semiconductor layer <NUM>. On the other hand, the second electrodes <NUM>, <NUM> have neither transparency nor form an ohmic contact with the upper semiconductor layer <NUM>. A portion of the second electrodes <NUM>, <NUM> are formed to contact with the upper semiconductor layer <NUM>, and the other portion of the second electrodes <NUM>, <NUM> are formed to contact with the transparent electrode layer. Consequently, the second electrodes <NUM>, <NUM> are configured to form a direct contact with the upper semiconductor layer <NUM>, thereby preventing electric current from flowing under the second electrodes <NUM>, <NUM>. Therefore, the light is not generated in the domain of the active layer which is placed under the second electrodes <NUM>, <NUM>, but generated in the domain of the active layer which is placed under the transparent electrode layer. With this structure, it is possible to minimize the light emitted from the active layer being absorbed and lost by the second electrodes <NUM>, <NUM>.

Meanwhile, a first extension part <NUM> of the second electrode extends from the second electrode <NUM> on the upper semiconductor layer <NUM> to be formed adjacent the third side. A second extension part <NUM> of the second electrode extends along a central line of the substrate from an intermediate portion between the second electrodes <NUM>, <NUM>. A third extension part <NUM> of the second electrode extends from the second electrode <NUM> on the upper semiconductor layer <NUM> to be formed adjacent a fourth side facing the third side. The second electrodes <NUM>, <NUM> and the first, second and third extension parts <NUM>, <NUM>, <NUM> of the second electrode may be formed of the same material using the same process.

Improvement in light emitting area of the light emitting diode according to this embodiment will be described through comparison of <FIG> with <FIG>.

In <FIG> and <FIG>, it can be seen that there is a great difference between the conventional technique and the embodiment in term of reduction in light emitting area resulting from formation of the lower electrode <NUM> and the first electrodes <NUM>, <NUM>, each of which is formed to supply electric current to the lower semiconductor layer. Namely, in the light emitting diode of <FIG>, an area of the light emitting area including the active layer <NUM> is removed for formation of the lower electrode <NUM> during mesa etching. Thus, when two lower electrodes <NUM> are formed corresponding to the structure as shown in <FIG>, the light emitting area can be further reduced by mesa etching. On the contrary, in the light emitting diode of <FIG>, the first electrodes <NUM>, <NUM> are formed above the upper semiconductor layer <NUM>, with the first and second insulation layers <NUM>, <NUM> interposed between the first electrodes and the upper semiconductor layer <NUM>, and the active layer <NUM> remains unetched. As such, the light emitting diode according to the embodiment provides an effective solution to the problem of the related art in which the light emitting area is reduced due to the formation of the electrode.

In addition, as can be seen from <FIG> and <FIG>, the second insulation layer <NUM> of the DBR structure formed under the first electrodes <NUM>, <NUM> allows light to be effectively emitted to the outside instead of being absorbed or blocked by the first electrodes <NUM>, <NUM>.

As such, according to the current invention, an electrode and an extension part for supplying current to a lower semiconductor layer are formed above an upper semiconductor layer with an insulation layer interposed between the electrode and the upper semiconductor layer. Consequently, an area of the semiconductor layer removed by mesa-etching for forming the electrode and the extension part is reduced, thereby preventing a reduction in light emitting area.

Although the invention has been illustrated with reference to some exemplary embodiments in conjunction with the drawings, it will be apparent to those skilled in the art that various modifications and changes can be made in the invention without departing from the scope of the invention as defined by the appended claims. Therefore, it should be understood that the embodiments are provided by way of illustration only and are given to provide complete disclosure of the invention and to provide thorough understanding of the invention to those skilled in the art. Thus, it is intended that the invention covers the modifications and variations of this invention provided they come within the scope of the appended claims.

Claim 1:
A light emitting diode, comprising:
a lower semiconductor layer (<NUM>, <NUM>) formed on a substrate (<NUM>, <NUM>);
an upper semiconductor layer (<NUM>, <NUM>) disposed above the lower semiconductor layer (<NUM>, <NUM>) to expose at least a portion of the lower semiconductor layer (<NUM>, <NUM>) forming an inclined mesa surface by a mesa-etching;
a first electrode (<NUM>, <NUM>) formed on a region of the upper semiconductor layer (<NUM>, <NUM>), with an insulation layer (<NUM>, <NUM>, <NUM>, <NUM>) interposed between the first electrode and the region of the upper semiconductor (<NUM>, <NUM>), to supply electric current to the lower semiconductor layer (<NUM>, <NUM>);
a second electrode (<NUM>, <NUM>) formed on another region of the upper semiconductor layer (<NUM>, <NUM>) to supply electric current to the upper semiconductor layer (<NUM>, <NUM>); and
a DBR layer (111c) formed on a bottom side of the substrate (<NUM>),
wherein the first electrode (<NUM>, <NUM>) comprises an inclined extension part (<NUM>) formed on the inclined mesa surface extending from the first electrode (<NUM>, <NUM>) to the exposed portion of the lower semiconductor layer (<NUM>, <NUM>), and
wherein the insulation layer (<NUM>) is formed on the upper surface of the upper semiconductor layer (<NUM>, <NUM>) and the inclined mesa surface.