Patent Description:
High-speed and high-accuracy analog-to-digital converters (ADCs) are used in many electronic architectures and solutions. For example, high-speed, high-accuracy ADCs are used in digitally modulated radar systems, communication systems, and other environments. Design of such ADCs is challenging due to speed and accuracy requirements particularly for low power solutions. Further, with semiconductor processing using <NUM> nanometer (nm) processes and below, the difficulty in designing of such ADCs increases significantly.

Typical designs that are high-speed (e.g., sample rates of <NUM> gigahertz (GHz) and above) use time-interleaved stages to obtain composite sample rates that achieve desired speeds and throughput. The use of these time-interleaved stages, however, is susceptible to errors in the sampling process, require tightly controlled clock skew between the time-interleaved stages, and often require tuned delays between interleaved paths. In addition to skew, gain and offset errors within the time-interleaved states introduce spurious, unwanted noise. The sampling process errors and gain/offset errors degrade the output spectrum of these prior time-interleaved ADC solutions. As such, the digital conversion provided by these prior time-interleaved ADC solutions can suffer from accuracy degradation that degrades overall system performance.

<CIT> describes a low power current voltage mixed ADC architecture. In some implementations, an ADC device includes a comparator array configured to receive an input analog voltage signal, a capacitor configured to receive the input analog voltage signal, an opamp coupled with the capacitor, and a transistor array activated by the comparator array to add or subtract currents to form a residue output voltage signal, which corresponds to the input analog voltage signal, used in analog to digital conversion of the input analog voltage signal.

<CIT> discloses a current-mode DAC in which the output current is defined by control of a resistance value.

<NPL>, presents a current-mode wave-pipelined ADC that includes a pre-stage circuit for distribution of a plurality of delayed currents.

It is noted that the appended figures illustrate only example embodiments and are, therefore, not to be considered as limiting the scope of the present invention. The scope of the present invention is defined by the appended independent claims. Specific embodiments are defined by the dependent claims.

Systems and related methods are disclosed for MDAC-based time-interleaved analog-to-digital converters (ADCs) and related methods. For one embodiment, an MDAC (multiplying digital-to-analog converter) is used to convert an input voltage to a current and to generate an N-bit digital value that provides a most-significant-bit (MSB) portion of the digital conversion. This initial conversion reduces the resolution needed for the additional analog-to-digital conversion circuitry. The current from the MDAC is then sampled to generate time-interleaved currents that are provided to an array of ICRO (current-controlled ring oscillator) sub-ADCs that provide an additional M-bit digital value. This multi-stage conversion architecture provides efficiency and accuracy advantages over prior solutions that suffer from skew, gain and offset errors. For further embodiments, efficient calibration techniques are provided that rely upon the M-bit digital values and regions of operation determined by the N-bit digital values to generate calibration correction values. These calibration techniques provide further efficiency improvements. The embodiments described herein can be used in a wide range of environments including digitally modulated radar systems, vehicle networking, or other environments. A variety of features and variations can be implemented while taking advantage of the techniques described herein.

For the disclosed embodiments, the time-interleaved ADCs are based upon time-interleaved ICRO (current-controlled ring oscillator) sub-ADCs with a front-end MDAC stage. The front-end MDAC stage provides a portion of the digital conversion (e.g., N-bit) and an array of time-interleaved ICRO sub-ADCs provide the remaining portion of the digital conversion (e.g., M-bit). In part, the disclosed embodiments provide one or more of the following features or advantages:.

For one embodiment, the ADC circuity can be implemented using FinFET (Fin Field Effect Transistor) processes and CMOS (Complementary Metal Oxide Semiconductor) design. Low power operation can be achieved at core voltages of <NUM> volts and below. Further, <NUM> FinFET technology can be used to manufacture integrated circuits implementing these time-interleaved ADCs. For one example embodiment, a time-interleaved ADC is disclosed that operates at four (<NUM>) gigahertz (GHz) or above while providing a digital conversion of ten (<NUM>) bits or above. Additional or different features and variations can also be implemented.

The disclosed embodiments will now be described in more detail with respect to the drawings. <FIG> provide diagrams for an example embodiment of a time-interleaved ADC. <FIG> provide example embodiments for Robertson diagrams that can be implemented by the MDACs described with herein. <FIG> and <FIG> provide more detailed circuit diagrams and timing diagrams for an example embodiment of an MDAC and the generation of time-interleaved currents applied to an array of ICRO sub-ADCs. <FIG> and <FIG> provide more detailed diagrams for an efficient calibration technique for multi-stage analog-to-digital converters. Additional or different embodiments can also be implemented.

Looking first to <FIG>, a block diagram is provided of an example embodiment for an ADC <NUM> having a front-end MDAC <NUM>, a phased current generator <NUM>, and an array <NUM> of time-interleaved ICRO sub-ADCs. The ADC <NUM> receives an input signal (VIN) <NUM> and outputs a digital conversion output <NUM> having N+M bits. For one embodiment, the input signal <NUM> is a high-frequency signal including one or more frequency components of <NUM> or above, and the conversion digital output <NUM> is <NUM> bits or more. Variations can be implemented.

The input signal <NUM> is received by sample-and-hold (S/H) circuit <NUM>. The S/H circuit <NUM> samples the input signal <NUM> with a sample clock <NUM> having a global sample rate (fS) for the ADC <NUM>. For one embodiment, the S/H circuit is implemented with capacitors coupled to switches for switched capacitor operation. The S/H circuit <NUM> helps to prevent skew-induced errors because only one sample clock <NUM> is used to sample the input signal <NUM> as opposed to multiple sample clocks in prior solutions. Subsequent time interleaving for embodiment <NUM>, therefore, is not be affected by skew of this sample clock <NUM> because the input signal <NUM> has already been sampled. As shown further in <FIG>, the sample-and-held output voltage (V) <NUM> can also be buffered before it is routed to the input of a linear voltage-to-current multiplying digital-to-analog converter (VIMDAC) <NUM>.

The VIMDAC <NUM> provides an output current (I) <NUM> and the first N bits of the digital conversion output <NUM> provided by ADC <NUM>. As described in more detail with respect to <FIG>, the VIMDAC <NUM> first converts the output voltage (V) <NUM> from the S/H circuit <NUM> to the current domain and then converts this current to a residue output current (I) <NUM> that is provided to the phased current generator <NUM>. The voltage to current relationship of the residue current <NUM> is determined by bits triggered within the VIMDAC <NUM>, and the full-scale input range of the time-interleaved ADC circuit <NUM>. The N-bit digital value <NUM> from the VIMDAC <NUM> provides the first N bits of the overall digital conversion output <NUM> for the ADC <NUM>.

Phased current generator <NUM> receives output current (I) <NUM> from the VIMDAC <NUM> and outputs time-interleaved currents <NUM> to the array <NUM> of ICRO sub-ADCs within the time-interleaved ADC circuit <NUM>. As described in more detail in <FIG>, the current <NUM> is effectively sampled and held with an array of phased clock pulses and switch current circuits to generate the time-interleaved currents <NUM>.

The phased copies of the current <NUM> are provided as time-interleaved currents <NUM> to the array <NUM> of ICRO sub-ADCs. As shown in more detail in <FIG>, the separate ICRO sub-ADCs within array <NUM> receive these phased copies of the current <NUM> in a time-interleaved manner based upon phased clock pulses. The digital output values of each of the sub-ADCs are then averaged. The averaged digital output values are then combined together to form the M-bit digital value <NUM>. This combined M-bit digital value <NUM> is then combined with the N-bit digital value <NUM> from the VIMDAC <NUM> to form the N+M-bit digital conversion output <NUM> for the ADC <NUM>. As further described herein, nonlinearities and gain errors existing within the ADC signal path can be estimated and corrected in the digital domain through a calibration routine using a calibration sub-ADC <NUM> and calibration logic <NUM>. The calibration sub-ADC <NUM> generates a calibration value <NUM> based upon the current <NUM>. The calibration logic <NUM> then generates correction values <NUM> for the combiner <NUM> based upon this calibration value <NUM> and the N-bit digital value <NUM>. In addition, as described in more detail with respect to <FIG>, the calibration logic <NUM> can also operate without the calibration sub-ADC <NUM> to generate correction values <NUM> based upon the M-bit digital value <NUM> and the N-bit digital value <NUM>. Other variations can also be implemented while still taking advantage of the techniques described herein.

<FIG> is a circuit diagram of an example embodiment for S/H circuit <NUM>. The input signal (VIN) <NUM> is coupled to transmission gate <NUM> that is controlled by the sample clock <NUM> to sample the input signal <NUM> at a global sample rate (fS). For example, the transmission gate <NUM> can be a CMOS transmission gate including a PMOS (p-channel metal-oxide-semiconductor) transistor and an NMOS (p-channel metal-oxide-semiconductor) transistor controlled by the sample clock <NUM> and an inverted version of the sample clock <NUM>. The gate of the NMOS transistor can be coupled to the sample clock <NUM>, and the gate of the PMOS transistor can be computed to an inverted version of the sample clock <NUM>. When the sample clock <NUM> is at a high logic level, the input signal <NUM> is transmitted by the transmission gate <NUM> to node <NUM>. When the sample clock <NUM> is a low logic level, the input signal <NUM> is isolated from the node <NUM> by the transmission gate <NUM>. The capacitance <NUM> coupled between node <NUM> and ground stores a voltage proportional to the amplitude of the input signal <NUM>. This stored voltage is buffered by buffer <NUM>, which can be a CMOS buffer, and the output voltage (V) <NUM> provides a sampled voltage at the global sample rate (fS) based upon the sample clock <NUM>.

<FIG> is a circuit diagram of an example embodiment for VIMDAC <NUM>. The VIMDAC <NUM> receives the output voltage (V) <NUM> and generates the current (I) <NUM> and the N-bit digital value <NUM>. For the embodiment shown, the output voltage <NUM> is received by an array <NUM> of different comparators <NUM>, <NUM>, <NUM>. <NUM>, which compare the voltage <NUM> to different trip voltages <NUM>. The trip voltages <NUM> include trip voltage levels <NUM>, <NUM>, <NUM>. <NUM> coupled to comparators <NUM>, <NUM>, <NUM>. <NUM>, respectively. The outputs of these comparators <NUM>, <NUM>, <NUM>. <NUM> provide thermometer coded outputs that represent the N-bit digital value <NUM>. For example embodiments below, N = <NUM> and six (<NUM>) comparators are used to achieve <NUM> bits of resolution. The outputs of the comparators represent thermometer coded values that in turn represent binary values from <NUM> to <NUM>. The following TABLE provides an example embodiment for relationships between these values where <NUM> bits of resolution are achieved.

Looking back to <FIG>, comparator <NUM> compares the voltage <NUM> to trip voltage level <NUM> and provides the most significant thermometer coding value. Comparator <NUM> compares the voltage <NUM> to trip voltage level <NUM> and provides the next most significant thermometer coding value. Comparator <NUM> compares the voltage <NUM> to trip voltage level <NUM> and provides the next most significant thermometer coding value. This continues depending upon the number of bits selected for N and the resolution being achieved. The last comparator <NUM> compares the voltage <NUM> to trip voltage level <NUM> and provides the least significant thermometer coding value. The N-bit digital value <NUM> is a binary value based upon the thermometer coded value generated by the outputs of the comparators <NUM>, <NUM>, <NUM>. The N-bit digital value <NUM> provides the first N-bits of the digital conversion output <NUM> provided by the ADC <NUM>.

The N-bit digital value <NUM>, for example, as represented by thermometer coded values output by comparators <NUM>, <NUM>, <NUM>. <NUM>, is also used as a control word that is applied to the variable resistance circuit <NUM>. For example, the variable resistance circuit <NUM> can be implemented as an array of resistor loads, with the array of resistor loads being enabled or disabled using switches controlled by the N-bit digital value <NUM>. The variable resistance circuit <NUM> is coupled between the drain of NMOS transistor <NUM> and ground. The source for NMOS transistor <NUM> provides the current <NUM> to the phased current generator <NUM> as shown in <FIG>. The gate for the NMOS transistor <NUM> is controlled by a differential amplifier <NUM>. The differential amplifier <NUM> receives a common mode (CM) reference voltage <NUM> and a voltage input <NUM> from a variable tuning resistance <NUM>. The variable tuning resistance <NUM> receives the voltage <NUM> and provides the voltage input <NUM> to the differential amplifier <NUM>. The variable tuning resistance <NUM> can be implemented as a plurality of selectable resistors controlled by a digital input. The drain for NMOS transistor <NUM> is also coupled to the voltage input <NUM> for differential amplifier <NUM>.

In operation, the output current <NUM> is dependent upon the variable resistance circuit <NUM> and the voltage <NUM>, which is in turn dependent upon the amplitude of the input signal <NUM>. The output current <NUM> is also dependent upon the N-bit digital value <NUM> (e.g., as represented by thermometer coded values output by comparators <NUM>, <NUM>, <NUM>. <NUM>), which controls the variable resistance circuit <NUM>. As described in more detail below, the resistance for the variable resistance circuit <NUM> is determined by the outputs from the comparators <NUM>, <NUM>, <NUM>. <NUM>, and this variable resistance creates a current <NUM> that follows the voltage/current (V/I) equation for each region of the Robertson diagrams described below. The outputs from the comparators <NUM>, <NUM>, <NUM>. <NUM> effectively determine which region of the Robertson diagram is used, and the resistance is set based on the voltage-current (V/I) relationship for the region dictated by the comparator output word. The different regions for the Roberson diagrams represent different values for the N-bit digital value <NUM>.

<FIG> is a circuit diagram of example embodiments for the phased current generator <NUM> and the time-interleaved ADC circuit <NUM> shown in <FIG>. The output current (I) <NUM> is received by the phased current generator <NUM>, and the phased current generator <NUM> provides time-interleaved currents <NUM>, <NUM>. <NUM> that are copies of the current <NUM> to the time-interleaved ADC circuit <NUM>. The time-interleaved ADC circuit <NUM> includes the array <NUM> of ICRO sub-ADCs that receive the time-interleaved currents <NUM>, <NUM>. The time-interleaved ADC circuit <NUM> outputs the M-bit digital value <NUM>. It is noted that the example embodiment for the phase current generator <NUM> in <FIG> is implemented with PMOS transistors. The phase current generator <NUM> can also be implemented using NMOS transistors or a combination of PMOS and NMOS transistors. Other variations can also be implemented.

Looking in more detail to the phased current generator <NUM>, the current <NUM> is coupled to node <NUM>. Node <NUM> is coupled to the drain and gate of PMOS transistor <NUM> so that PMOS transistor <NUM> operates as a diode-connected device within a current mirror. The source of PMOS transistor <NUM> is coupled to node <NUM>, and node <NUM> is coupled to a supply voltage (VSUPPLY). The sources of PMOS transistors <NUM>, <NUM>. <NUM>, <NUM> are also coupled to node <NUM> and the supply voltage. The drains of PMOS transistors <NUM>, <NUM>. <NUM>, <NUM> are coupled to provide the time-interleaved currents <NUM>, <NUM>. <NUM> to the time-interleaved ADC circuit <NUM>. The gates of PMOS transistors <NUM>, <NUM>. <NUM>, <NUM> are coupled to node <NUM> through switches <NUM>, <NUM>. <NUM>, <NUM>. These switches <NUM>, <NUM>. <NUM>, <NUM> are controlled by time-interleaved phased clock pulses θ1, θ2. When turned "ON," these switches <NUM>, <NUM>. <NUM>, <NUM> connect the gates to node <NUM> thereby turning "ON" the PMOS transistors <NUM>, <NUM>. <NUM>, <NUM>. When "ON," the PMOS transistors <NUM>, <NUM>. <NUM>, <NUM> operate as current mirrors with respect to PMOS transistor <NUM> and generate copies of the current <NUM> on their respect drains. As such, PMOS transistors <NUM>, <NUM>. <NUM> and time-interleaved phased clock pulses θ1, θ2. θX (i.e., X different phased clock pulses) are used to provide copies of the current <NUM> as time-interleaved currents <NUM>, <NUM>. <NUM> to the array <NUM> of ICRO sub-ADCs. The PMOS transistor <NUM> and phased clock pulse θCal are used in a calibration mode to provide current <NUM> to the calibration sub-ADC <NUM>.

Looking to the time-interleaved ADC circuit <NUM>, the ICRO sub-ADCs <NUM>, <NUM>. <NUM> receive the phased clock pulses θ1, θ2. θX as phase-sampled versions of the residue output current (I) <NUM> from the VIMDAC <NUM>. In effect, each of these sub-ADCs <NUM>, <NUM>. <NUM> use sample-and-held and current-converted versions of the input signal <NUM> at distinct phase relations to the original signal. The digital values output from the sub-ADCS <NUM>, <NUM>. <NUM> are then provided to averaging circuits <NUM>, <NUM>. <NUM>, respectively. For example, the averaging circuits <NUM>, <NUM>. <NUM> can include logic circuits and registers that accumulate digital values from sub-ADCs <NUM>, <NUM>. <NUM> and average these digital values over a selected time period to provide averaged digital output values <NUM>, <NUM>. <NUM> to the combiner <NUM>. This time period is dependent on the global ADC sample rate (fS), the sample rate selected for the sub-ADCs, and the number of channels (i.e., X different sub-ADCs) in the time-interleaved sub-ADC array <NUM>. Each of the averaged digital output values <NUM>, <NUM>. <NUM>, for example, can provide M/X bits of the combined M-bit digital value <NUM> output by combiner <NUM>.

The calibration sub-ADC <NUM> can be used to calibrate operation of the sub-ADCs <NUM>, <NUM>. During calibration mode, a copy of the current <NUM> is provided through PMOS transistor <NUM> as calibration current <NUM> to the ICRO sub-ADC <NUM> within the calibration sub-ADC <NUM>. The averaging circuit <NUM> receives the digital values output from the ICRO sub-ADC <NUM> and provides an averaged digital value <NUM> to adder <NUM>. A digital calibration value <NUM> is then output to calibration (CAL) logic <NUM>. The calibration logic <NUM> can also receive the N-bit digital value <NUM> and the M-bit digital value <NUM>. During calibration mode, the calibration logic <NUM> compares this digital calibration value <NUM> to expected values and generates digital correction values <NUM>. The digital correction values <NUM> are provided to combiner <NUM> so that calibration adjustments can be made.

The calibration logic <NUM> logic can also operate without the calibration sub-ADC <NUM> to generate calibration correction values <NUM> as described in more detail with respect to <FIG>. For this calibration embodiment, the calibration logic <NUM> determines calibration correction values <NUM> for the different regions of operation for the VIMDAC <NUM>. As described in more detail below, the calibration logic <NUM> determines the region of operation from the N-bit digital value <NUM>, and then tracks maximum and minimum values for the M-bit digital value <NUM> within these different regions. Calibration correction values <NUM> for each operational region are then generated based upon differences between these maximum and minimum values.

As also shown in <FIG>, non-linearity corrections can be used to adjust the operation of the time-interleaved ADC circuit <NUM> through adders <NUM>, <NUM>. <NUM>, <NUM> coupled between the averaging circuits <NUM>, <NUM>. <NUM>, <NUM> and the combiner <NUM>. A bus <NUM> can provide outputs from the ICRO sub-ADCs <NUM>, <NUM>. <NUM>, <NUM> to a non-linearity correction controller <NUM>. The controller <NUM> processes these outputs, for example, by comparing them to desired operational parameters, and generates corrections to be applied as correction factors. These corrections can be applied through bus <NUM> to adders <NUM>, <NUM>. <NUM>, <NUM> in order to adjust the averaged digital values <NUM>, <NUM>. <NUM>, <NUM> before they are provided to combiner <NUM>. The corrections can be, for example, positive or negative digital values that are added to the averaged digital values <NUM>, <NUM>. <NUM>, <NUM>. Different corrections can also be generated and provided to each of the adders <NUM>, <NUM>. <NUM>, <NUM>. The calibration adjustments, such as through calibration correction values <NUM>, can also be applied through the operation of non-linearity correction controller <NUM>. As such, the averaged digital values <NUM>, <NUM>. <NUM>, <NUM> are adjusted to correct for nonlinearities and gain errors that are present along the signal conversion path.

The ICRO sub-ADCs <NUM>, <NUM>. <NUM>, <NUM> can be implemented as current-starved ring oscillators that operate as a first-order sigma-delta ADCs and sample at a rate independent of the global sample rate (fS) for sampling clock <NUM>. <CIT> provides example embodiments for current-controlled ring oscillators (ICROs) and related circuitry for high-speed ADC architectures that can be used for the disclosed embodiments. The ICRO ADCs described therein work on the principle that the frequency of the ring oscillator can be directly related to the input voltage of the signal being converted. The digital presentation of the input voltage applied is acquired by phase decoding the various phases of the ring oscillator to an equivalent digital code that relates the input voltage to an output decoded phase. This phase is then differentiated digitally in order to attain a representation of the ICRO frequency. The ring oscillator is a current driven, current starved oscillator and thus the correlation to the input is achieved by running the signal through a transconductance operation. <CIT> discloses an example implementation of a current driven ring oscillator.

For one embodiment, the ICRO sub-ADCs <NUM>, <NUM>. <NUM>, <NUM> have a sample rate of <NUM> or above. For another embodiment, the sample rate is <NUM> or above. Different sample rates could also be used including lower frequency sample rates. It is noted that a sample rate for the sub-ADCs <NUM>, <NUM>. <NUM>, <NUM> is preferably greater than the global sample rate (fS) for the ADC <NUM> based upon the global sampling clock <NUM> because this allows the selected time period for averaging to be adjusted. For example, increased averaging within the averaging circuits <NUM>, <NUM>. <NUM>, <NUM> can be implemented by increasing the selected time period. This increased averaging of each time-interleaved current <NUM>, <NUM>. <NUM> provides additional accuracy in the digital implementation of the averaged value. This adjustment in sample rates can be accomplished in part, for example, by reducing the number of stages in ring oscillators used within the ICRO sub-ADCs <NUM>, <NUM>. <NUM>, <NUM>. For one embodiment, a <NUM>-stage ring oscillator that runs at a sample rate of <NUM> is used for each of the ICRO sub-ADCs <NUM>, <NUM>. <NUM>, <NUM>. For one further embodiment, a sample rate of <NUM> is achieved using <NUM> stages (i.e., dropped by a factor of <NUM>). One advantage of this is reduction in stages is that the digital overhead in terms of die area and complexity is reduced by <NUM>-times. One disadvantage of this reduction in stages is that the digital logic must now run at a higher rate of <NUM>, which is more difficult to achieve. However, <NUM> FinFET processes or other advanced semiconductor processing can be used to achieve these sample rates of <NUM> or above.

During operations, the ICRO sub-ADCs <NUM>, <NUM>. <NUM> are not susceptible to timing skews and inaccuracies in the time-interleaved channels provided by the ICRO sub-ADCs <NUM>, <NUM>. <NUM> because the global sample-and-hold provided by S/H circuit <NUM> removes the need for sampling at each of the ICRO sub-ADCs <NUM>, <NUM>. In addition, using a redundant signed-digit topology in the VIMDAC <NUM> as shown in <FIG>, a simple calibration algorithm can be implemented in the digital domain to correct for non-linearities and gain errors. Other advantages can also be achieved.

As further shown in <FIG>, the sample-and-held output voltage (V) <NUM> is converted to a current through the resistor-based linear VIMDAC circuit <NUM>. The resulting residue current (I) <NUM> from the VIMDAC <NUM> is subsequently sampled-and-held with an array of switch circuits <NUM>, <NUM>. <NUM> as shown in <FIG>. For one embodiment, this sampling by the phased clock pulses θ1, θ2. θX occurs at an update rate of <MAT> where fS is <NUM>. For one further embodiment, the global sample rate (fS) is <NUM>, and sixteen (<NUM>) sub-ADCs are used in the array <NUM>. It is again noted that the number of interleaved sub-ADCs is completely flexible as well as the sample rate for the sub-ADCs. Therefore, the update rate for the time-interleaved residue currents <NUM>, <NUM>. <NUM> is not limited to a specific value and will change based on selected sample rate and accuracy desired for ADC <NUM>. Furthermore, where the converted digital values <NUM>, <NUM>. <NUM> from the sub-ADCS <NUM>, <NUM>. <NUM> are averaged to generate averaged digital values <NUM>, <NUM>. <NUM>, there is significant flexibility to increase the averaging at the cost of reduced throughput to further improve accuracy of the sub-ADCs <NUM>, <NUM>. Additional variations can also be made while still taking advantage of the techniques described herein.

<FIG> provides an example embodiment <NUM> for a Robertson diagram that is achieved by one example implementation of the VIMDAC <NUM>. Robertson diagrams are diagrams used to represent redundant signed-digit topologies typically found in switch-capacitor Nyquist ADCs. For embodiment <NUM>, the vertical axis <NUM> represents the residue output current (I) <NUM>, and the horizontal axis represents the sample-and-held voltage output (V) <NUM> with respect to the VIMDAC <NUM> of <FIG>. A nominal reference voltage (Vref) is used to generate the different trip voltage levels <NUM>, <NUM>, <NUM>. <NUM> for the comparators <NUM>, <NUM>, <NUM>. <NUM> for array <NUM> shown in <FIG>. In particular, six (<NUM>) different trip voltage levels <NUM>, <NUM>, <NUM>. <NUM> are provided: -5Vref/<NUM>, -3Vref/<NUM>, -Vref/<NUM>, Vref/<NUM>, 3Vref/<NUM>, and 5Vref/<NUM>. The middle voltage (VMID) is set to Vref. These trip voltage levels provide different output regions for the output current <NUM> as shown. In particular, a first region <NUM> represents a <NUM>-bit binary (b) output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The last region <NUM> represents a binary output of <NUM>. It is noted that the different trip voltage levels <NUM>, <NUM>, <NUM>. <NUM> are referenced to Vref for this embodiment such that their values referenced to ground are Vref-5Vref/<NUM>, Vref-3Vref/<NUM>, Vref-Vref/<NUM>, Vref+Vref/<NUM>, Vref+3Vref/<NUM>, and Vref+5Vref/<NUM>.

For one embodiment, a fully differential solution is implemented using the embodiment <NUM>. For both pseudo-differential paths, the resulting output current range causes the subsequent ICRO sub-ADC(s) to oscillate in the frequency ranges from <NUM>*fs to <NUM>*fS. This is accomplished in part by providing a two-times (2X) gain in the VIMDAC <NUM> through the differential amplifier <NUM>. While this gain increase would ideally translate to a <NUM> dB improvement in the signal-to-noise ratio, with separate ICRO sub-ADCs having uncorrelated quantization noise, the improvement is reduced. For example, with two separate ICRO sub-ADCs the improvement translates to only a <NUM> dB improvement for the 2X gain in the VIMDAC <NUM>.

<FIG> provides an additional example embodiment <NUM> for a Robertson diagram that is achieved by another implementation of the VIMDAC. For embodiment <NUM>, the vertical axis <NUM> represents the residue output current (I) <NUM>, and the horizontal axis represents the sample-and-held voltage output (V) <NUM> with respect to the VIMDAC <NUM> of <FIG>. A nominal reference voltage (Vref) is again used to generate the different trip voltage levels <NUM>, <NUM>, <NUM>. <NUM> for the comparators <NUM>, <NUM>, <NUM>. <NUM> for array <NUM> shown in <FIG>. In particular, six (<NUM>) different trip voltage levels <NUM>, <NUM>, <NUM>. <NUM> are provided: -5Vref/<NUM>, -3Vref/<NUM>, -Vref/<NUM>, Vref/<NUM>, 3Vref/<NUM>, and 5Vref/<NUM>. The middle voltage (VMID) is set to -4Vref/<NUM>. These trip voltage levels provide different output regions for the output current <NUM> as shown. In particular, a first region <NUM> represents a <NUM>-bit binary (b) output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The next region <NUM> represents a binary output of <NUM>. The last region <NUM> represents a binary output of <NUM>. It is noted that the different trip voltage levels <NUM>, <NUM>, <NUM>. <NUM> are referenced to Vref for this embodiment such that their values referenced to ground are Vref-5Vref/<NUM>, Vref-3Vref/<NUM>, Vref-Vref/<NUM>, Vref+Vref/<NUM>, Vref+3Vref/<NUM>, and Vref+5Vref/<NUM>.

With respect to the current levels, region <NUM> has a current range from current level <NUM> to current level <NUM>. Regions <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> have a current range from current level <NUM> to current level <NUM>. Region <NUM> has a current range from current level <NUM> to current level <NUM>. For one embodiment associated with the equations derived below, current level <NUM> is represented by the equation: Ires = Ic + Ic/<NUM>. Current level <NUM> is represented by the equation: Ires = Ic + Ic/<NUM>. Current level <NUM> is represented by the equation: Ires = -(Ic + Ic/<NUM>). Current level <NUM> is represented by the equation: Ires = -(Ic + Ic/<NUM>). When the N-bit digital value <NUM> is "<NUM>" in operational region <NUM>, the output current is represented by the equation: Ires = (<NUM>*Ic/<NUM>) - (M*Vin). When the N-bit digital value <NUM> is "<NUM>" in operational region <NUM>, the output current is represented by the equation: Ires = (<NUM>*Ic/<NUM>) - (M*Vin). When the N-bit digital value <NUM> is "<NUM>" in operational region <NUM>, the output current is represented by the equation: Ires = (<NUM>*Ic/<NUM>) -(M*Vin). When the N-bit digital value <NUM> is "<NUM>" in operational region <NUM>, the output current is represented by the equation: Ires = (<NUM>*Ic/<NUM>) - (M*Vin). When the N-bit digital value <NUM> is "<NUM>" in operational region <NUM>, the output current is represented by the equation: Ires = (<NUM>*Ic/<NUM>) -(M*Vin). When the N-bit digital value <NUM> is "<NUM>" in operational region <NUM>, the output current is represented by the equation: Ires = (<NUM>*Ic/<NUM>) - (M*Vin). When the N-bit digital value <NUM> is "<NUM>" in operational region <NUM>, the output current is represented by the equation: Ires = (<NUM>*Ic/<NUM>) - (M*Vin). It is noted that the vertical axis <NUM> is placed where Vin = -<NUM>*Vref/<NUM> and that the horizontal axis <NUM> is placed where Ires = Ic. Further, it is noted that "M" represents the slope of the lines and that "Ic" represents the center current for the ICRO sub-ADCs <NUM>, <NUM>. For one embodiment, the slope is four (e.g., M = <NUM>). Other variations and Robertson diagrams can also be implemented while still taking advantage of the techniques described herein.

Looking now to <FIG>, <FIG>, <FIG>, and <FIG>, circuit and timing diagrams are provided of an example differential embodiment for VIMDAC <NUM> and phased current generator <NUM>. This example embodiment can be used in an implementation operating at a high frequency, such as <NUM>, and providing <NUM>-bit resolution using a core supply voltage of one volt or below. This example embodiment is scalable to higher bit resolutions along with an increase in the number of comparators being used. Further, the accuracy of the comparators can be adjusted based upon the number of comparators being used and related trip points for the different operating regions.

As described in further detail below, the example embodiment provides a <NUM> bit VIMDAC including six (<NUM>) comparators operating at a sample rate of <NUM>. A resistor array controlled with switches coupled to the comparator outputs is implemented for the variable resistance circuit <NUM> and sets the residue current <NUM>. The operation of this switched resistor array as the variable resistance circuit <NUM> thereby sets the center current for the array of sub-ADCs <NUM> to the residue current <NUM> based upon the digital value <NUM>, which is <NUM> bits for this example embodiment. The variable resistance circuit <NUM> essentially operates as a digital-to-analog converter (DAC). The internal transistor amplifier <NUM> provides a summing junction for the resistor array, sums current from the resistor array, and provides the residue current <NUM> to the phased current generator <NUM>. A sample-and-hold switched current mirror circuit is used as the phased current generator <NUM> to create phased sample-and-held copies (θ1, θ2. θX) of the residue current <NUM> that are sent to the time-interleaved ADC circuit <NUM>.

The goal of this differential embodiment is to provide a VIMDAC that implements a current-mode implementation of the modified Robertson diagram as shown in <FIG>. As such, the scaled and sample-and-held phased versions of the residue current <NUM> are output to the array <NUM> of time-interleaved sub-ADCs. In <FIG>, output current is the dependent variable, and input voltage is the independent variable. A set of input-voltage-dependent residue current copies <NUM> are generated that enable the follow-on ICRO sub-ADCs to vary from <NUM>*Fs to <NUM>*FS. This variation in current translates to <NUM>*Ic to <NUM>*Ic (i.e., Ic ± Ic/<NUM>) where Ic is the center-current for the ICRO sub-ADCs. The center-current is the input current that allows the ring-oscillator within the ICRO sub-ADC to oscillate at the same frequency as the sampling frequency for the ICRO sub-ADC. A differential solution is shown, and the voltage <NUM> received by the VIMDAC <NUM> is converted to a residue current <NUM> to create the required sampled-and-held copies <NUM> of the residue current <NUM> to control the array <NUM> of ICRO sub-ADCs. It is further noted that additional features and variations could also be implemented while still taking advantage of the techniques described herein.

Looking now to <FIG>, a circuit diagram is provided of an example differential embodiment for VIMDAC <NUM>. The VIMDAC <NUM> receives the voltage (V) <NUM> as a positive input voltage (VIN_P) 106A and a negative input voltage (VIN_N) 106B. The VIMDAC <NUM> generates the output residue current (I) <NUM> as differential outputs 112A and 112B. The N-bit digital value <NUM> from comparator array <NUM> is used as a control word that is applied to the variable resistance circuit <NUM>. For this embodiment, the N-bit digital value <NUM> is a <NUM>-bit digital value that is provided to the variable resistance circuit <NUM> as thermometer bits (T1-T6) and an inverse version of these thermometer bits (bT1-bT6). The variable resistance circuit <NUM> is implemented as an array of resistor loads (R1-R6), and the resistor loads (R1-R6) are enabled or disabled using switches controlled by the thermometer bits (T1-T6) and inverse thermometer bits (bT1-bT6). A positive-side resistor (RP) and a negative-side resistor (RN) are always enabled within the resistor array. The variable resistance circuit <NUM> has a positive-side output 604A and a negative-side output 604B. The array of resistor loads (R1-R6) are coupled between ground and outputs 604A/604B depending upon the state of switches as controlled by the thermometer bits (T1-T6) and inverse thermometer bits (bT1-bT6). As such, a variable resistance load is provided based upon the digital value <NUM>.

The positive-side NMOS transistor 310A has its drain coupled to the positive-side output 604A from the variable resistance circuit <NUM>. The source for NMOS transistor 310A provides the positive-side residue current 112A that is output to the phased current generator <NUM>. The gate for the NMOS transistor 310A is controlled by positive-side differential amplifier 308A. The positive-side differential amplifier 308A receives the common mode (CM) reference voltage 306A and the positive-side voltage 106A through a variable tuning resistance 302A. The variable tuning resistance 302A can be implemented as a plurality of selectable resistors controlled by a digital input or as a fixed input resistance if desired. The drain of transistor 310A is also coupled to the output 304A of the variable tuning resistance 302A and the input of the positive-side differential amplifier 308A.

The negative-side NMOS transistor 310B has its drain coupled to the negative-side output 604B from the variable resistance circuit <NUM>. The source for NMOS transistor 310B provides the negative-side residue current 112B that is output to the phased current generator <NUM>. The gate for the NMOS transistor 310B is controlled by negative-side differential amplifier 308B. The negative-side differential amplifier 308B receives the common mode (CM) reference voltage 306B and the negative-side voltage 106B through a variable tuning resistance 302B. The variable tuning resistance 302B can be implemented as a plurality of selectable resistors controlled by a digital input or as a fixed input resistance if desired. The drain of transistor 310B is also coupled to the output 304B of the variable tuning resistance 302B and the input of the negative-side differential amplifier 308B.

For the example embodiment depicted, trip voltages <NUM> are generated within a resistor tree <NUM>. The resistor tree <NUM> includes a plurality of resistors coupled in series between a positive reference voltage (VREFP) and a negative reference voltage (VREFN). For this example embodiment, six (<NUM>) trip voltages <NUM> are generated from intervening nodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. In addition, for this example embodiment, two resistors (R) are coupled between each of these nodes, and three resistors (R) are coupled between nodes <NUM>/<NUM> and the reference voltages (VREFP and VREFN), respectively. Node <NUM> provides high trip voltage VH_3. Node <NUM> provides high trip voltage VH_2. Node <NUM> provides high trip voltage VH_1. Node <NUM> provides low trip voltage VL_3. Node <NUM> provides low trip voltage VL_2. Node <NUM> provides low trip voltage VL_1. The different trip voltages <NUM> are coupled to comparator array <NUM>, which also receives the voltages 106A/106B. The comparator array <NUM> outputs thermometer bits (T1-T6) and inverse thermometer bits (bT1-bT6) as digital value <NUM>.

<FIG> is a circuit diagram of an example differential embodiment for the comparator array <NUM> that receives the different trip voltages <NUM> for the embodiment of <FIG>. A difference voltage based upon the positive-side voltage (VIN_P) 106A and negative-side voltage (VIN_N) 106B is coupled to the positive input (+) for comparators <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. For comparator <NUM>, a difference voltage based upon trip voltage (VH_3) <NUM> and trip voltage (VL_1) <NUM> is coupled to the negative input (-) for comparator <NUM>. For comparator <NUM>, a difference voltage based upon trip voltage (VH_2) <NUM> and trip voltage (VL_2) <NUM> is coupled to the negative input (-) for comparator <NUM>. For comparator <NUM>, a difference voltage based upon trip voltage (VH_1) <NUM> and trip voltage (VL_3) <NUM> is coupled to the negative input (-) for comparator <NUM>. For comparator <NUM>, a difference voltage based upon trip voltage (VL _3) <NUM> and trip voltage (VH_1) <NUM> is coupled to the negative input (-) for comparator <NUM>. For comparator <NUM>, a difference voltage based upon trip voltage (VL_2) <NUM> and trip voltage (VH_1) <NUM> is coupled to the negative input (-) for comparator <NUM>. For comparator <NUM>, a difference voltage based upon trip voltage (VL_1) <NUM> and trip voltage (VH_3) <NUM> is coupled to the negative input (-) for comparator <NUM>.

The comparators <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> generate thermometer bits (T6, T5, T4, T3, T2, T1) and the inverse of these bits (bT6, bT5, bT4, bT3, bT2, bT1). These thermometer bits represent the N-bit digital value <NUM> as described above. The thermometer bits will be a high logic level when positive input (+) exceeds the negative (-) input and will be a low logic level otherwise. The digital value <NUM>, in the form of the thermometer bits (T6, T5, T4, T3, T2, T1) and inverse thermometer bits (bT6, bT5, bT4, bT3, bT2, bT1), controls the switches within the variable resistance load <NUM> as shown in <FIG>. Further, the digital value <NUM> is used to form an N-bit value that provides part of the conversion digital output <NUM> as shown in <FIG>.

<FIG> is a circuit diagram of an example differential embodiment for the phased current generator <NUM> that receives the differential residue currents 112A/112B from the VIMDAC <NUM> of <FIG>. For this differential embodiment, there are sixteen (<NUM>) positive-side PMOS transistors 804A and sixteen (<NUM>) negative-side PMOS transistors 804B that correspond to PMOS transistors <NUM>, <NUM>. <NUM> in <FIG>.

The positive-side current 112A is coupled to node 402A. Node 402A is coupled to the drain and gate of PMOS transistor 404A so that PMOS transistor 404A operates as a diode-connected device within a current mirror. The source of PMOS transistor 404A is coupled to node <NUM>, and node <NUM> is coupled to a supply voltage (VSUPPLY). The sources of PMOS transistors 804A are also coupled to node <NUM> and the supply voltage. The drains of PMOS transistors 804A are coupled to generate the time-interleaved currents 115A. The gates of PMOS transistors 804A are coupled to node 402A through switches. These switches are controlled by time-interleaved phased clock pulses (θ1-θ16) <NUM>. When turned "ON," these switches connect the gates to node 402A thereby allowing the PMOS transistors 804A to mirror the current in PMOS transistor 404A. As such, PMOS transistors 804A and time-interleaved phased clock pulses (θ1-θ16) <NUM> provide copies of the current 112A as time-interleaved currents 115A to the array <NUM> of ICRO sub-ADCs.

The negative-side current 112B is coupled to node 402B. Node 402B is coupled to the drain and gate of PMOS transistor 404B so that PMOS transistor 804B operates as a diode-connected device within a current mirror. The source of PMOS transistor 804B is coupled to node <NUM>, and node <NUM> is coupled to a supply voltage (VSUPPLY). The sources of PMOS transistors 804B are also coupled to node <NUM> and the supply voltage. The drains of PMOS transistors 804B are coupled to generate the time-interleaved currents 115B. The gates of PMOS transistors 804B are coupled to node 402B through switches. These switches are controlled by time-interleaved phased clock pulses (θ1-θ16) <NUM>. When turned "ON," these switches connect the gates to node 402B thereby allowing the PMOS transistors 804B to mirror the current in PMOS transistor 804B. As such, PMOS transistors 804B and time-interleaved phased clock pulses (θ1-θ16) <NUM> provide copies of the current 112B as time-interleaved currents 115B to the array <NUM> of ICRO sub-ADCs.

<FIG> is a timing diagram of an example embodiment <NUM> for phased clock pulses (θ1-θ16) <NUM> that can be generated and output to the embodiment for phased current generator <NUM> shown in <FIG>. The sample clock <NUM> is used as a master clock. The sub-ADC clock <NUM> is based upon the sample clock <NUM> and is used to time the array <NUM> of sub-ADCs shown in <FIG>. For the example embodiment <NUM>, the sub-ADC clock <NUM> has a quarter of the frequency (fS/<NUM>) of the global frequency (fS) for the sample clock <NUM>. Each of the phased clock pulses (θ1-θ16) <NUM> have a pulse that lasts for one cycle of the sample clock <NUM>, and the pulse repeats every sixteen (<NUM>) cycles of the sample clock <NUM>. As such, the pulses for the phased clock pulses (θ1-θ16) <NUM> do not overlap. As described above, the phased clock pulses (θ1-θ16) <NUM> are used to transfer the time-interleaved currents 115A/115B to the array <NUM> of ICRO sub-ADCs. More generally, it is noted that each of the phased clock pulses (θ1-θ16) <NUM> is pulsed to update the input to its respective sub-ADC with a period given by fS/X where X represents the number of different phases. For example, where there are sixteen (<NUM>) different phases as with the example embodiment <NUM> and where the sample clock has a frequency (fS) of <NUM> gigahertz (GHz), each of the phased clock pulses (θ1-θ16) <NUM> is pulsed at a frequency of <NUM> megahertz (MHz), which is <NUM> / <NUM> = <NUM>. It is further noted that the sub-ADC clock <NUM> can be implemented with different frequencies including frequencies slower or faster than those shown for embodiment <NUM>. For example, the sub-ADC clock <NUM> can have a frequency higher than the global frequency (fs) such as where averaging is used. Other variations can also be implemented.

<FIG> provides timing diagrams of an example embodiment for the operation of the phased current generator <NUM> to generate time-interleaved currents <NUM>. For this example embodiment as shown in diagram <NUM>, the input voltage (V) <NUM> is assumed to ramp through the different operational regions for the VIMDAC <NUM>, as determined by the array <NUM> of comparators shown in <FIG>. Diagram <NUM> represents an example phased clock pulse θX that is applied to switch circuit <NUM> to sample the residue current (I) <NUM> as shown in <FIG>. While one example phased clock pulse θX is shown, it is understood that each of the switch circuits <NUM>, <NUM>. <NUM> would receive a phased clock pulses θ1, θ2. Diagram <NUM> shows the residue current (I) <NUM> and the resulting time-interleaved current <NUM>/<NUM>/<NUM> that results from the sampling caused by the phased clock pulses θ1, θ2. θX being applied to one of the switch circuits <NUM>, <NUM>. Although a single sampled current (Isampled) is shown, it is noted that each of the switch circuits <NUM>, <NUM>. <NUM> would cause a time-interleaved current <NUM>, <NUM>. <NUM> to be generated as described with respect to <FIG>. Together, these time-interleaved currents <NUM> are provided to the array <NUM> of ICRO sub-ADCs as also shown in <FIG>.

Looking back to <FIG>, it is noted that equations can be derived for the operational current regions associated with the residue current <NUM> and the different trip voltages <NUM>. Before deriving the various operating region equations, however, Vref is defined in relation to Vrefp - Vrefn. The relationship is <MAT>, therefore each of the reference voltages in <FIG> and carried into the circuit diagrams of <FIG> as the different trip voltages <NUM> can be given as: <MAT>.

Now that the comparator trip voltages <NUM> are established, the next step is to derive the various regions of operation equations for the residue current. The first step is to derive the required current for the easiest region of operation and apply this learning to other regions of operation.

Looking at the generic diagram in <FIG>, the residue current Ires = Ix - I<NUM> = Ix - <MAT>, and for the case where Vin = Vmid the current is defined to be equal to the center current for the ICRO sub-ADC. The topology specific operating point on the modified Robertson diagram is not the middle of the Robertson diagram for <FIG> but allows the circuit to operate without having to source and sink current in the voltage to current circuit. Hence, the implementation of the circuit block diagram as shown in <FIG> enables the full operating range of the ICRO sub-ADCs. With this condition established, the current in each region is derived. It is noted that the equations below represent single-ended embodiments; however, the differential embodiment equations can be similarly derived.

As stated, the residue current <MAT> and for the case where Vin = Vmid I<NUM> = <NUM>. With this condition and looking at <FIG>, we can establish that Ires = Ix with <MAT> and <MAT>. If we let Rx = Rin and plug this back into the equation for Ires, then the following is reached: <MAT> where <MAT>.

Now from the Robertson diagram in <FIG>, the transconductance slope is <MAT> and the only place where this equation hold true is for <MAT>. Comparing against the comparator trip points established, this equation for the residue current holds true for the operating region <MAT>. This results in <MAT> with the slope given as <MAT>.

The next obvious region to derive the equations of operation is for the region <MAT>. In this region, set Vin = <NUM> (or -Vref). For the condition where Vin = <NUM> or as shown in diagram for differential operation Vin = -Vref , it is required the residue current to equal <MAT> therefor the equation for this region is <MAT>.

The next region is the upper boundary region of operation is for a full-scale input. In this region of operation, <MAT> where Vin = Vref = Vrefp - Vrefm, <MAT>. Looking at the patterns, a set of operating equations for each operating region given as:.

For the required resistance calculations of the VIMDAC topology embodiment shown in <FIG>, the determination is started by looking at the region for which the resistance is already defined <MAT>. In this region, Rx = Rin which holds true for <MAT>. In this region with <MAT> where <MAT>.

For the other regions of operation, Rx can be defined for each region. For <MAT> and <MAT>, where <MAT> and if use <MAT> given the constraint for this region, Rx can be defined. If the condition where Vin = <NUM> is taken, Rx can be easily solved. <MAT> and additionally, <MAT> and by combining these two equivalents, Rx can be found. <MAT> with Rin given as <MAT> and <MAT> provides that <MAT>.

For the region <MAT> again is easily solved for Rx by setting Vin = Vref = Vrefp - Vrefm which provides that <MAT>. Again, looking at the patterns, the resistance Rx for each section is nothing but a parallel set of resistors controlled by the comparator trip points for each region of operation.

Looking now to <FIG> and <FIG>, example embodiments are provided for calibration of multi-stage analog-to-digital converters, including the multi-stage ADC embodiments described above. Due to non-idealities for circuit implementations (e.g., component mismatch, limited amplifier gain and bandwidth, etc.), missing output digital values or codes may exist in the digital conversion output <NUM> at the transition regions for an initial ADC, such as the N-bit VIMDAC <NUM> utilized in the multi-stage ADC <NUM>. These missing digital values can occur due to various non-idealities in the VIMDAC <NUM> itself as well as any non-idealities in follow-on analog-to-digital conversion circuitry, such as the time-interleaved ADC <NUM>. For example, even with an ideal N-bit VIMDAC <NUM>, the missing digital values at the transition points become apparent if the follow-on ADC circuitry exhibits a nonlinear transfer function.

As described herein, calibration circuits and methods can be implemented to correct for these circuit non-idealities in multi-stage ADCs. The disclosed calibration embodiments implement efficient digital routines that approximate and correct these missing digital values. The calibration embodiments can also be implemented as background operations. Further, the disclosed calibration embodiments can be implemented with digital logic without requiring additional analog calibration circuitry or specialized predetermined calibration input sequences. Other advantages can also be achieved.

For one embodiment as described above with respect to <FIG>, calibration logic <NUM> operates to generate calibration correction values <NUM> by tracking maximum/minimum values for the M-bit digital value <NUM> within different operational regions for the VIMDAC <NUM>. In addition to the M-bit digital value <NUM>, the calibration logic <NUM> also receives the N-bit digital value <NUM> from the VIMDAC <NUM> and uses this N-bit digital value <NUM> to determine a current region of operation for the VIMDAC <NUM>. The calibration logic <NUM> executes one or more calibration algorithms to generate calibration correction values <NUM>, such as digital correction values, that are used to adjust and correct the digital conversion output <NUM>. For example, the digital correction values <NUM> can provide a correction value for each operational region for the VIMDAC <NUM>, and these correction values <NUM> can be applied by the combiner <NUM> to adjust the digital output values <NUM>, <NUM>. <NUM> being received from the sub-ADC array <NUM> as shown in more detail in <FIG>. In operation, these digital correction values <NUM> effectively correct for linearity errors within the N-bit digital value <NUM> generated by the VIMDAC <NUM>, within the M-bit digital value <NUM> generated by the additional analog-to-digital converter <NUM>, or both. As such, non-idealities within both the MDAC <NUM> and the additional analog-to-digital converter <NUM> are compensated by the calibration embodiments described herein.

<FIG> is a flow diagram of an example embodiment <NUM> for a calibration process that can be performed by calibration logic <NUM> for the multi-stage ADC <NUM> based upon the operation of an N-bit initial ADC, such as VIMDAC <NUM>, which has multiple operational regions (e.g., Z number of regions) followed by an M-bit additional ADC. As shown in the example embodiment <NUM>, the calibration method keeps track of minimum and maximum values for the M-bit digital value <NUM> for each of the Z regions of operation for the N-bit initial ADC. The calibration method uses these minimum and maximum values to generate the correction values <NUM> for the different regions determined by the N-bit digital value <NUM>. The correction values <NUM>, which can be digital values, are then applied to correct the N-bit digital value <NUM> output by the VIMDAC <NUM>, the M-bit digital value <NUM> output by the additional ADC <NUM>, or the N+M-bit digital conversion output <NUM> for the multi-stage ADC <NUM>. Further, as indicated above, the calibration method can be operated in the background during normal operations for the ADC <NUM>.

Looking in more detail to <FIG>, the calibration process begins in block <NUM>. In block <NUM>, a new result (RESULT) for the M-bit digital value <NUM> is obtained, which is based upon the residue current <NUM> from the VIMDAC <NUM> for the example embodiment described above. In block <NUM>, the region (Z) for the residue current <NUM> is determined based upon the N-bit digital value <NUM>. In block <NUM>, a determination is made whether the result is the first result for the region (Z). If "NO," then block <NUM> is reached. If "YES," then block <NUM> is reached where the maximum value for this region (REGION_MAX[Z]) is set to zero, and the minimum value for this region (REGION_MIN[Z]) is set to <NUM>. Block <NUM> is then reached. In block <NUM>, a determination is made whether the result is greater than the current value stored for the maximum value. If "NO," then block <NUM> is reached. If "YES," then block <NUM> is reached where the maximum value for this region (REGION_MAX[Z]) is set to the current result, which is the current value for the M-bit digital value <NUM>. Block <NUM> is then reached. In block <NUM>, a determination is made whether the result is less than the current value stored for the minimum value. If "NO," then block <NUM> is reached. If "YES," then block <NUM> is reached where the minimum value for this region (REGION_MIN[Z]) is set to the current result, which is the current value for the M-bit digital value <NUM>. Block <NUM> is then reached. In block <NUM>, a correction value (CORRECTION[Z]) for the region is set to an expected range value for the region (EXPECTED[Z]) less a difference between the maximum value (REGION_MAX[Z]) and the minimum value (REGION_MIN[Z]). Flow then passes back to block <NUM>. It is noted that the expected range value (EXPECTED[Z]) is an ideal value that depends upon the number of bits (N) converted by the MDAC front end and the number of bits (M) converted by the additional ADC <NUM>. It is also noted that the difference between the maximum value (REGION_MAX[Z]) and the minimum value (REGION_MIN[Z]) represents an approximated actual conversion range for that region. Further, it is noted that different or additional steps could also be implemented while still taking advantage of the techniques described herein.

<FIG> is a block diagram of an example embodiment for calibration logic <NUM> to implement the calibration process of <FIG>. A comparison engine <NUM> receives as inputs the M-bit digital value <NUM> from the additional ADC (e.g., ADC <NUM>) and the N-bit digital value <NUM> from the initial ADC (e.g. VIMDAC <NUM>). The maximum values for regions <NUM>-Z are stored in a lookup table <NUM>, and the minimum values for regions <NUM>-Z are stored in a lookup table <NUM>. The expected range values for the regions <NUM>-Z are stored in lookup table <NUM>. The comparison engine <NUM> determines a region of operation for the initial ADC based upon the N-bit digital value <NUM>, accesses the lookup tables <NUM> and <NUM>, and updates the stored values as described for embodiment <NUM> in <FIG>. For each region <NUM>-Z, the correction engine <NUM> compares the expected range values from lookup table <NUM> to the difference between the maximum and minimum values from lookup tables <NUM>/<NUM> to generate correction values that are stored in table <NUM>. A controller <NUM> is coupled to the comparison logic <NUM> and the correction logic <NUM> to facilitate control and timing for internal operations of the calibration logic <NUM>. The calibration correction values <NUM> stored in table <NUM> are then output to the combiner <NUM> to be used to adjust the M-bit digital value <NUM> and thereby correct for non-idealities in the operation of the initial ADC (e.g., VIMDAC <NUM>), the operation of the additional ADC (e.g., time-interleaved ADC <NUM>), or both. As described herein, the calibration correction values <NUM> are updated over time as updates occur in the maximum values or minimum values stored in lookup tables <NUM>/<NUM>. The expected range values stored in lookup table <NUM> can be programmable values or can be fixed values based upon the implementation for the multi-stage ADC. It is noted that that the calibration logic <NUM> can be implemented using one or more integrated circuits that are programmed to provide the functionality described herein. It is further noted that the tables <NUM>, <NUM>, <NUM>, and <NUM> can be implemented as one or more non-transitory computer-readable mediums. Other circuitry and variations can also be implemented while still taking advantage of the calibration techniques described herein.

As described herein, therefore, the calibration circuits and methods of <FIG> can be implemented as an efficient digital routine that approximates and corrects the missing digital values or codes in the transition regions for the front-end VIMDAC <NUM>. The digital routine operates in the background by assessing each result for the M-bit digital value <NUM>. For each given result, the digital routine determines from the N-bit digital value <NUM> from the MDAC <NUM> which region of the N-bit MDAC transfer function the code resides. Following this determination, the routine further determines if the current result represents either a maximum value or a minimum value for the region in which it resides. The calibration algorithm in effect stores an output value for a given region only if that particular value represents either a minimum value or a maximum value out of all of the values that have occurred for that given region. The difference between the maximum and minimum values represents an actual conversion range being implemented by a particular region. The difference between an expected range value and this actual conversion range represents a correction value that can be applied to adjust correct the actual conversion range. As time progresses, the calibration routine attains increasingly more accurate estimates of each region's minimum and maximum values. These minimum and maximum values are also compared between adjacent MDAC region transitions in order to calculate a correction value (e.g., jump code) between regions. This correction value is then added or subtracted out digitally in order to ultimately generate a corrected ADC output for the multi-stage ADC <NUM>. Because this is happening continuously, the accuracy of this correction improves with time. After some period of time, the correction values <NUM> will resolve, and the digital conversion output <NUM> of the multi-stage ADC <NUM> no longer contains missing code errors at the MDAC transition regions.

<FIG> are representative diagrams of ADC outputs versus ADC inputs before and after the calibration process of <FIG> has been applied. These ADC transfer curves represent ADC outputs after the N bits associated with the VIMDAC <NUM> are added to generate the overall digital conversion output <NUM>. For the example embodiment above, the VIMDAC <NUM> outputs the three MSBs (<NUM> to <NUM>) for the digital conversion output <NUM>.

Looking first to <FIG>, a representative diagram is shown of an embodiment <NUM> for an ideal ADC transfer curve <NUM> and an actual ADC transfer curve <NUM>. As described herein, the front-end VIMDAC <NUM> determines the first N bits of the digital conversion output <NUM> depending an operational region for the residue current112 based upon the voltage input <NUM>. For the examples above, there are seven (<NUM>) distinct regions for the VIMDAC <NUM> (e.g., a <NUM>-bit MDAC). For embodiment <NUM>, these distinct regions are regions <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> (representing outputs <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, respectively) that are determined by the trip voltages <NUM> provided to the array <NUM> of comparators as shown in <FIG>.

Looking now to <FIG>, a representative diagram is shown of an embodiment <NUM> for an ideal ADC transfer curve <NUM> and a corrected ADC transfer curve <NUM> after correction values have been applied. The front-end VIMDAC <NUM> again determines the first N bits of the digital conversion output <NUM> depending an operational region for the residue current112 based upon the voltage input <NUM>. However, for embodiment <NUM>, correction values generated by the calibration logic <NUM> have been applied to correct for missing digital values or codes at region transitions. For the examples above, there are again seven (<NUM>) distinct regions for the VIMDAC <NUM> (e.g., a <NUM> bit MDAC). For embodiment <NUM>, these distinct regions are regions <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> (representing outputs <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, respectively) that are determined by the trip voltages <NUM> provided to the array <NUM> of comparators as shown in <FIG>. As shown, the corrected ADC transfer curve <NUM> provides significantly improved linearity.

As described herein, a variety of embodiments can be implemented and different features and variations can be implemented, as desired.

For one embodiment, a circuit for analog to digital conversion is disclosed including a multiplying digital-to-analog converter (MDAC). The MDAC includes an amplifier coupled to convert a voltage received as an input to an output current, a variable load coupled to the amplifier to control the output current where the variable load is dependent upon a digital value, and an array of comparators coupled to receive the voltage as an input and having the digital value as an output. The digital value represents at least a portion of a digital conversion of the voltage.

According to the invention as claimed, the circuit also includes a phased current generator coupled to receive the output current and having a plurality of time-interleaved currents as outputs, and each time-interleaved current is a sampled copy of the output current. In further embodiments, the phased current generator includes a plurality of current mirror circuits coupled to mirror the output current and to output the time-interleaved currents, a plurality of switches coupled to enable or to disable the plurality of current mirror circuits, and a plurality of phased clock pulses coupled to control the switches. In still further embodiments, each of the current mirror circuits includes a transistor coupled to mirror the output current and to be controlled by one of the plurality of phased clock pulses.

In additional embodiments, the amplifier includes an NMOS transistor having its gate coupled to the voltage through a differential amplifier, having its drain coupled to the variable load, and having its source coupled to provide the output current.

In additional embodiments, the variable load includes a variable resistance circuit having a plurality of selectable resistors. In further embodiments, the plurality of selectable resistors include a plurality of resistors coupled to the amplifier through switches controlled by the digital value.

In additional embodiments, the array of comparators has a plurality of trip voltages as inputs. In further embodiments, the circuit also includes a resistor tree coupled between two reference voltages and having the plurality of trip voltages as outputs from intervening nodes. In further embodiments, each comparator provides a thermometer bit for the digital value based upon at least one of the trip voltages.

For one embodiment, a method for analog to digital conversion is disclosed including converting a voltage received by an amplifier to an output current, controlling the output current with a variable load coupled to the amplifier where the variable load is dependent upon a digital value, and generating the digital value with an array of comparators coupled to receive the voltage as an input. The converting, controlling, and generating provide a multiplying digital-to-analog converter (MDAC). Further, the digital value represents at least a portion of a digital conversion of the voltage.

In additional embodiments, the method includes generating a plurality of time-interleaved currents based upon the output current. In further embodiments, the generating of the plurality of time-interleaved currents includes generating a plurality of currents that mirror the output current with a plurality of current mirror circuits, controlling the plurality of current mirror circuits to output the plurality of currents using a plurality of switches, and applying a plurality of phased clock pulses to control the switches. In still further embodiments, each of the current mirror circuits includes a transistor coupled to mirror the output current that is controlled by one of the plurality of phased clock pulses.

In additional embodiments, the amplifier includes an NMOS transistor having its drain coupled to the variable load, and the method further includes applying the voltage to a gate of the NMOS transistor through a differential amplifier and providing the output current from a source of the NMOS transistor.

In additional embodiments, the controlling includes adjusting a variable resistance circuit having a plurality of selectable resistors to provide the variable load. In further embodiments, the adjusting includes applying a digital value to control switches that select which of the plurality of selectable resistors to include within the variable load.

In additional embodiments, the method also includes providing a plurality of trip voltages as inputs to the array of comparators. In further embodiments, the method also includes generating the plurality of trip voltages from intervening nodes within a resistor tree coupled between two reference voltages. In further embodiments, each comparator provides a thermometer bit for the digital value based upon at least one of the trip voltages. Current controlled multiplying digital-to-analog converters (MDACs) and related methods are disclosed for time-interleaved analog-to-digital converters (ADCs). For one embodiment, a circuit includes an MDAC having an amplifier that converts a voltage to an output current, a variable load that is dependent upon a digital value and that controls the output current from the amplifier, and an array of comparators that receive the voltage and output the digital value to the variable load. The digital value represents at least a portion of a digital conversion of the voltage. Further, the circuit includes a phased current generator that receives the output current and generates time-interleaved currents where each time-interleaved current is a sampled copy of the output current.

It is further noted that the functional blocks, components, systems, devices, or circuitry described herein can be implemented using hardware, software, or a combination of hardware and software. For example, the disclosed embodiments can be implemented using one or more integrated circuits that are programmed to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. The one or more integrated circuits can include, for example, one or more processors or configurable logic devices (CLDs) or a combination thereof. The one or more processors can be, for example, one or more central processing units (CPUs), controllers, microcontrollers, microprocessors, hardware accelerators, ASICs (application specific integrated circuit), or other integrated processing devices. The one or more CLDs can be, for example, one or more CPLDs (complex programmable logic devices), FPGAs (field programmable gate arrays), PLAs (programmable logic array), reconfigurable logic circuits, or other integrated logic devices. Further, the integrated circuits, including the one or more processors, can be programmed to execute software, firmware, code, or other program instructions that are embodied in one or more non-transitory tangible computer-readable mediums to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. The integrated circuits, including the one or more CLDs, can also be programmed using logic code, logic definitions, hardware description languages, configuration files, or other logic instructions that are embodied in one or more non-transitory tangible computer-readable mediums to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. In addition, the one or more non-transitory tangible computer-readable mediums can include, for example, one or more data storage devices, memory devices, flash memories, random access memories, read only memories, programmable memory devices, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, or any other non-transitory tangible computer-readable mediums. Other variations can also be implemented while still taking advantage of the techniques described herein.

Claim 1:
A circuit for analog to digital conversion (<NUM>), comprising:
a multiplying digital-to-analog converter (MDAC) (<NUM>), comprising:
an amplifier (<NUM>) coupled to convert a voltage received as an input to an output current;
a variable load coupled to the amplifier (<NUM>) to control the output current, the variable load being dependent upon a digital value;
an array of comparators (<NUM>) coupled to receive the voltage as an input and having the digital value as an output;
wherein the digital value represents at least a portion of a digital conversion of the voltage; characterised in that the circuit further comprises a phased current generator (<NUM>) coupled to receive the output current and having a plurality of time-interleaved currents as outputs, each time-interleaved current being a sampled copy of the output current.