Patent Description:
The present disclosure relates to testing, calibration, and tuning of integrated circuits, such as oscillator circuits.

Modern clocking circuits in integrated circuits require stable frequency references (e.g., oscillators) with fast turn-on, small output noise, and small power consumption. Because of stringent frequency stability requirements, an external resonator with a high-quality factor (such as a quartz crystal) is usually employed in conjunction with active components in the integrated circuit for generating the reference oscillations.

Furthermore, although capacitive load adjustments can be made for finely changing the oscillation frequency during normal operation, an accurate capacitive load must usually be provided for the resonator to prevent excessive frequency deviations in the absence of other adjustments. Although there are means to provide an integrated adjustable capacitance to a resonator, prescribing the value of this capacitance with good accuracy is a challenge because the capacitance in question must be measured against known standards. Additional challenges are presented by the unavailability of proper stimuli and/or circuitry for their application in complex systems such as integrated transceivers and by the low-supply-voltage environments where the active devices (such as transistors) must operate with small headroom voltages.

Several drawbacks associated with accurately measuring on-chip capacitance can be identified in the prior art. <FIG> is a circuit diagram of a previously proposed capacitance measurement approach based on measurement of transient currents. Such transient currents can be affected by the nonidealities of the comparator - e.g., finite gain and delay, which may cause capacitance over-charge and over-discharge, as well as oscillatory settling. In addition, the capacitance is inferred from a measured average current, which requires filtering of sharp current pulses and consequently relies on large on-chip capacitances, resulting in a relatively long settling time. To minimize comparator error contributions, the injected measurement frequency can be set to low values, further increasing the required averaging on-chip capacitance and measurement time.

<FIG> is a circuit diagram of another previously proposed capacitance measurement approach based on measuring amplitudes of sinusoidal signals. This approach is inherently inaccurate and difficult to perform in integrated systems.

<FIG> is a circuit diagram of another previously proposed capacitance measurement approach. Under this approach, there is also a need to measure average currents, with the inherent burden of filtering capacitor size and long measurement time due to settling.

<FIG> is a circuit diagram of another previously proposed capacitance measurement approach. This approach has the same drawbacks of the approach in <FIG>. In addition, the CMOS transistors and drivers in <FIG> must be able to handle relatively large current spikes during charging and discharging, which increases chip area.

<CIT> describes capacitive mismatch measurement. According to this document, an analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.

An on-chip capacitance measurement method and associated systems and devices are provided. Embodiments described herein rely on using the capacitor under test in an on-chip relaxation oscillator configuration whose charging/discharging currents, supply voltage, and output frequency are measured individually in a measurement block. The voltage thresholds of the relaxation oscillation are calculated from the circuit elements and the measured supply voltage. Because the oscillation frequency of the relaxation oscillator is a function of the capacitance under test, the charging/discharging currents, and the supply voltage (via voltage thresholds), the capacitance under test can be calculated using the measured values of the other quantities.

Using digitally controlled switches and other dedicated circuitry, a capacitor normally associated with other circuits (such as crystal oscillators) can be tested by putting the main circuit where the capacitor is used in high-impedance (high-Z) mode and connecting the capacitor to the relaxation oscillator for measurement. After the measurement is done, the capacitor is disconnected from the relaxation oscillator and the main circuit is returned to the normal mode. This can be done for a multiplicity of capacitors associated with a given circuit and can also be employed for tuning by adjusting the control code of digitally programmable capacitive loads in cases where highly accurate capacitances must be presented to a resonator for ensuring oscillation at the specified frequency.

Embodiments described herein provide an accurate, low-power, small-area on-chip system capable of measuring capacitance with high accuracy. An algorithm employing the above method and apparatus for tuning a crystal oscillator is also provided. Relevant circuit implementations used in the on-chip measurement system are also disclosed.

An example embodiment provides a method for measuring on-chip capacitance. The method includes disconnecting a target capacitance from a main circuit of an integrated circuit and connecting the target capacitance to a relaxation oscillator on the integrated circuit. The method further includes measuring an output of the relaxation oscillator and measuring the target capacitance based on the measured output.

Another example embodiment provides an integrated circuit. The integrated circuit includes a main circuit, a relaxation oscillator, and switching circuitry configured to selectively connect a target capacitance to the main circuit or to the relaxation oscillator. The integrated circuit further includes a measurement block configured to measure the target capacitance based on an output of the relaxation oscillator.

Another example embodiment provides a tuning circuit. The tuning circuit includes a relaxation oscillator and switching circuitry configured to selectively disconnect a target capacitance from a main circuit and connect the target capacitance to the relaxation oscillator. The tuning circuit further includes a measurement block configured to measure a value of the target capacitance based on an output of the relaxation oscillator and a tuning block configured to adjust the target capacitance based on the measured value.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the illustrative embodiments in association with the accompanying drawing figures.

<FIG> is a schematic block diagram of an integrated circuit <NUM> with a measurement circuit <NUM> according to the present disclosure. The measurement circuit <NUM> measures on-chip a single-ended capacitance C associated with the integrated circuit <NUM>, such as an oscillator. In normal operation, when digital control signal SELC is at logic <NUM>, switch swC is open and switch swCb is closed, connecting capacitance C to the main circuit <NUM> with which it is associated. When SELC is at logic <NUM>, switch swC is closed and switch swCb is open, effectively disconnecting capacitance C from the main circuit and connecting it to a relaxation oscillator <NUM> (present on the same chip) whose frequency is a function of capacitance C and other circuit parameters.

The value of capacitance C is measured with high accuracy by measuring the output frequency of the relaxation oscillator <NUM>, and all the quantities involved in producing its output waveform (such as voltage thresholds and charging/discharging currents) using dedicated circuitry in a measurement block <NUM>. This information may then be used in determining other quantities of interest associated with the main circuit <NUM> (e.g., its own oscillation frequency), once the capacitance C is reconnected to the main circuit <NUM> (e.g., by setting SELC to logic <NUM>). In some embodiments, the relaxation oscillator <NUM> can be enabled or disabled by control signal RELOSCEN.

<FIG> is a schematic diagram of an example embodiment of the measurement circuit <NUM> of <FIG>. Here, two adjustable capacitors C<NUM>, C<NUM> primarily associated with a van den Homberg crystal (XTAL) oscillator can be functionally disconnected from the crystal oscillator core <NUM> and can be in turn connected to the relaxation oscillator <NUM> via switches swC<NUM> and swC<NUM>. respectively. The switches swC<NUM> and swC<NUM> can be controlled by capacitor select signals SELC<NUM> and SELC<NUM>, respectively.

The functional disconnect from the crystal oscillator core <NUM> can be achieved by putting the crystal oscillator core <NUM> in high-impedance (high-Z) mode (e.g., by cutting off its supply current) using control signal HIGHZ, and by disconnecting the rest of the circuit (such as bias resistors Rx<NUM>, Rx<NUM>) using switches (swRx<NUM>, swRx<NUM>, respectively). The rest of the measurement circuit <NUM> in <FIG> is similar in form and function to the diagram of <FIG>.

<FIG> is a schematic diagram of an example digitally controlled capacitor bank <NUM> for the measurement circuit <NUM> of <FIG>. In an example aspect, one or both of capacitors C<NUM> and C<NUM> can be implemented as digitally controlled capacitor banks <NUM>. Each digitally controlled capacitor bank <NUM> can include M different capacitors C<NUM>, C<NUM>,. , CM-<NUM> selectively connected to node A (for capacitor C<NUM>) or node B (for capacitor C<NUM>) of <FIG> using corresponding switches swb<NUM>, swb<NUM>,. , swb(M-<NUM>) (e.g., using control signals b<NUM>, b<NUM>,. , bM-<NUM>). It should be understood that the capacitor bank <NUM> of <FIG> is illustrative in nature and other circuit arrangements may be used in other embodiments.

<FIG> is a schematic diagram of an example tuning circuit <NUM> for the integrated circuit <NUM> of <FIG>. The tuning circuit <NUM> is similar to the measurement circuit <NUM>, with a tuning block <NUM> added to control the settings for capacitors C<NUM> and C<NUM> associated with the crystal oscillator core <NUM>. Accordingly, in an example aspect the tuning block <NUM> provides digital control for one or more digitally controlled capacitor banks <NUM> as in <FIG>.

The tuning block <NUM> controls the capacitors C<NUM> and C<NUM> based on the data extracted by means of the relaxation oscillator <NUM> and the measurement block <NUM>. In some examples, capacitor C<NUM> cannot be physically separated from the parasitic capacitance CP when switch swc<NUM> is closed, and the tuning algorithm must take this aspect into account. For tuning purposes (e.g., connecting a specified capacitance in parallel with the crystal oscillator core <NUM>), if capacitors C<NUM> and C<NUM> are identical all the information relevant to capacitor C<NUM> (in particular, the size of the minimum capacitance step) can be extracted by measuring capacitor C<NUM>, which does not have any board parasitic capacitance CP connected in parallel to it. By measuring C<NUM> at the minimum setting (together with CP), the previously extracted capacitance step using C<NUM> can be used to calculate the target value of the (C<NUM> + CP) combination. This tuning algorithm is further discussed below with respect to <FIG>).

The tuning block <NUM> and/or the measurement block <NUM> can be implemented using discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In some embodiments the tuning block <NUM> and/or the measurement block <NUM> may be implemented with a microprocessor or any conventional processor, controller, microcontroller, or state machine.

<FIG> is a schematic diagram of an example relaxation oscillator <NUM> for the integrated circuit <NUM> of <FIG>. Here, Ct is the capacitance under test. A comparator COMP provides output VOUT based on an inverting input and a noninverting input. A first resistor R<NUM> is connected between supply voltage VDD and the noninverting input, and a second resistor R<NUM> is connected between the noninverting input and ground (e.g., forming a voltage divider coupled to the noninverting input). A third resistor is connected between the output VOUT and the noninverting input. The resistor arrangement permits the comparator COMP to operate with input voltage ranges that do not include the VDD/<NUM> point. This is advantageous in low-voltage systems in that the internal structure of the comparator COMP can be topologically simple and ensure operation of transistors away from the triode region (in CMOS implementations).

The capacitance under test Ct is connected between the inverting input of the comparator COMP and ground. A first current source I<NUM> is coupled between the supply voltage VDD and the inverting input, and a second current source I<NUM> is coupled between the inverting input and ground. The current sources I<NUM> and I<NUM> are connected using switches swI<NUM>, swI<NUM>b (connected to the first current source I<NUM>) and swI<NUM>, swI<NUM>b (connected to the first current source I<NUM>) such that the capacitance under test Ct oscillates between being charged and discharged.

In this regard, the enabling inputs of switches swI<NUM>, swI<NUM>b, swI<NUM>, swI<NUM>b are connected to the output VOUT such that in a first period the first current source I<NUM> is connected to the inverting input such that the capacitance under test Ct is charged while the second current source I<NUM> is disconnected. Once the capacitance under test Ct is charged, in a second period the first current source I<NUM> is disconnected and the second current source I<NUM> is connected to the inverting input such that the capacitance under test Ct is discharged.

<FIG> is a graphical representation of example waveforms of the relaxation oscillator <NUM> of <FIG>. With the notations in <FIG>, assuming rail-to-rail swing of the comparator output VOUT, the following equations can be derived for the circuit of <FIG>: <MAT> <MAT> <MAT> <MAT> <MAT> <MAT>.

In the above equations, I<NUM> and I<NUM> are the capacitor charging and discharging currents, respectively. VUTH and VLTH ·are the upper and lower voltage thresholds, respectively, of the relaxation oscillator <NUM>. ΔT<NUM> and ΔT<NUM> are the capacitor charging and discharging times, respectively. The output frequency of the relaxation oscillator <NUM> is obtained according to Equation <NUM>, being a function of I<NUM>, I<NUM>, ΔV (and implicitly a function of VDD through Equation <NUM>), and Ct.

From Equation <NUM>, if I<NUM>, I<NUM>, VDD are known or can be accurately measured (assuming R<NUM>, R<NUM>, R<NUM> are accurately known from the design of the circuit, which permits the accurate calculation of VUTH, VLTH, and ΔV according to Equations <NUM>, <NUM>, and <NUM>), and if the output frequency of the relaxation oscillator <NUM> can be measured accurately, then the capacitance under test Ct can be obtained as: <MAT> where ΔV is given by Equation <NUM>. In accordance with embodiments described herein, the measurement block <NUM> in <FIG>, <FIG>, or <FIG> performs the measurement of I<NUM>, I<NUM>, VDD, and fOUT and calculates Ct using Equation <NUM> and the known values of R<NUM>, R<NUM>, R<NUM>.

<FIG> is a schematic diagram of an example comparator COMP for the relaxation oscillator <NUM> of <FIG>. This illustrates a complementary metal-oxide-semiconductor (CMOS) implementation of the comparator COMP using field-effect transistors (FETs), though the comparator COMP may also be implemented using bipolar junction transistors (BJTs) or other types of transistors. The inverting input is connected to the gate of a first transistor M<NUM> (e.g., a p-type MOSFET (PMOS)) and the noninverting input is connected to the gate of a second transistor M<NUM> (e.g., a PMOS). The first transistor M<NUM> is connected in series with a complementary third transistor M<NUM> (e.g., an n-type MOSFET (NMOS)), which is connected to ground. Similarly, the second transistor M<NUM> is connected in series with a complementary fourth transistor M<NUM> (e.g., an NMOS), which is connected to ground. The gates of the third transistor M<NUM> and the fourth transistor M<NUM> are connected to the gates of a corresponding fifth transistor M<NUM> and sixth transistor M<NUM>, respectively. These gates are further connected to the corresponding drains of the third transistor M<NUM> and the fourth transistor M<NUM>.

The fifth transistor M<NUM> is connected in series with a complementary seventh transistor M<NUM> (e.g., a PMOS), which is connected to the supply voltage VDD. Similarly, the sixth transistor M<NUM> is connected in series with a complementary eight transistor M<NUM> (e.g., a PMOS), which is connected to the supply voltage VDD. The gates of the seventh transistor M<NUM> and the eighth transistor M<NUM> are connected together and to the drain of the seventh transistor M<NUM>.

Finally, a ninth transistor M<NUM> (e.g., a PMOS) is connected between the supply voltage VDD and the sources of the first transistor M<NUM> and the second transistor M<NUM>. The output VOUT of the comparator COMP is connected to the drain of the ninth transistor M<NUM> and the sources of the first transistor M<NUM> and the second transistor M<NUM>. A bias signal bias for the comparator COMP is connected to the gate of the ninth transistor M<NUM>.

<FIG> is a schematic diagram of another example embodiment of the measurement circuit <NUM> of <FIG>. Copies I<NUM>c, I<NUM>c, of the charging and discharging currents I<NUM>, I<NUM>, respectively, of the relaxation oscillator <NUM> are fed to the measurement block <NUM>. The measurement block <NUM> includes voltage measurement circuitry <NUM>, current measurement circuitry <NUM>, and frequency measurement circuitry <NUM>. These circuits are selectively connected using voltage measurement switch swVM (controlled by signal VCVM), current measurement switch swIM (controlled by signal VCIM), and frequency measurement switch swFM (controlled by signal VCFM).

When current measurement switch swIM is closed (e.g., signal VCIM is logic <NUM>), the currents to be measured are selected by control signal VCID. More specifically, if VCID is at logic <NUM>, then swsnk<NUM>,·swsrc<NUM>b are closed and swsnk<NUM>b,·swsrc<NUM> are open, which connects I<NUM>c to the measurement block <NUM> (e.g., the current measurement circuitry <NUM>). If VCID is at logic <NUM>, then swsnk<NUM>, ·swsrc<NUM>b are open and swsnk<NUM>b, ·swsrc<NUM> are closed, which connects I<NUM>c to the measurement block <NUM>.

In the configuration shown in <FIG>, it is not necessary to stop the relaxation oscillator <NUM> from oscillating when measuring I<NUM>c and I<NUM>c because these currents are copies of the actual charging and discharging currents I<NUM> and I<NUM> of the relaxation oscillator <NUM> and have no effect on its actual operation. Therefore, the configuration of <FIG> allows a rapid measurement of all the quantities needed in the calculation of Ct from Equation <NUM>.

<FIG> is a schematic diagram of another example embodiment of the measurement circuit <NUM> of <FIG>. Here, the actual charging and discharging currents I<NUM>, I<NUM> of the relaxation oscillator <NUM> are fed to the measurement block <NUM>. In this way, the measurement accuracy of capacitance Ct is improved by eliminating the errors associated with copying currents I<NUM>, I<NUM> (which was illustrated in <FIG>). To achieve this, control signal VCCT set to logic <NUM> performs the function of stopping the oscillation of the relaxation oscillator <NUM> by disconnecting the inputs of comparator COMP and feedback resistor R<NUM> from the relaxation oscillator feedback loop (by opening switches swosc<NUM>, swosc<NUM>, and swR<NUM>), and allowing forced large DC voltages to be applied to the inputs of the comparator COMP by closing switches swen<NUM>b and swen<NUM>b.

The polarity of the forced large DC voltages is controlled by signal VCTI and its associated control inverter INVf<NUM>. Thus, when VCTI is at logic <NUM>, the output of INVf<NUM> is at logic <NUM>, switches swfin<NUM>, swfin<NUM> are open, swfin<NUM>, swfin<NUM> are closed, the noninverting input of the comparator COMP is at ground, the inverting input of the comparator COMP is at VDD, causing the output VOUT to be at ground, thus closing swI<NUM>b, swI<NUM>, opening swI<NUM>, swI<NUM>b, in this way sending I<NUM> to the measurement block <NUM> as a sink current. When VCTI is at logic <NUM>, the output of INVf<NUM> is at logic <NUM>, switches swfin<NUM>, swfin<NUM> are closed, swfin<NUM>, swfin<NUM> are open, the noninverting input of the comparator COMP is at VDD, the inverting input of the comparator COMP is at ground, causing the output VOUT to be at VDD, thus opening swI<NUM>b, swI<NUM>, closing swI<NUM>, swI<NUM>b, in this way sending I<NUM> to the measurement block <NUM> as a source current.

Unlike in <FIG>, in the embodiment of <FIG> it is necessary to stop the relaxation oscillator <NUM> from oscillating when measuring currents I<NUM>, I<NUM>, therefore the frequency measurement cannot be done at the same time as measuring I<NUM>, I<NUM>, which causes the overall measurement process to be slower. However, there is improved accuracy relative to embodiment of <FIG>, because the errors associated with current copying are eliminated.

<FIG> is a flow diagram of a tuning algorithm for the tuning circuit <NUM> of <FIG>. This algorithm is described with reference to the capacitance measurement approaches described above with respect to <FIG> and <FIG>. The algorithm begins with disconnecting the crystal oscillator core <NUM> from the integrated circuit <NUM> (block <NUM>). Adjustable capacitor C<NUM> is then connected to the relaxation oscillator <NUM> and set to its minimum value (block <NUM>). The voltage, currents and frequency are measured and used to calculate the minimum value of C<NUM> (block <NUM>).

C<NUM> is connected to the relaxation oscillator <NUM> and set to its maximum value (block <NUM>). The voltage, currents and frequency are measured and used to calculate the maximum value of C<NUM> (block <NUM>). The C<NUM> minimum capacitance step value C<NUM>STEP is then calculated (block <NUM>). By design, C<NUM>STEP is the same as the C<NUM> minimum capacitance step value C<NUM>STEP.

Adjustable capacitor C<NUM> is then connected to the relaxation oscillator <NUM> and set to its minimum value (block <NUM>). The board parasitic capacitance CP is present as it is connected to C<NUM>. The voltage, currents and frequency are measured and used to calculate the minimum value of (C<NUM> + CP) (block <NUM>). C<NUM>CODE is calculated such that the minimum value of (C<NUM> + CP + C<NUM>LSB * C<NUM>CODE) is the target load capacitance for the crystal oscillator core <NUM> (block <NUM>). Finally, the value of C<NUM> is set using C<NUM>CODE (block <NUM>).

<FIG> is a flow diagram of a process for measuring on-chip capacitance. Dashed boxes represent optional steps. The process begins at operation <NUM>, with disconnecting a target capacitance from a main circuit of an integrated circuit. In an example aspect, the target capacitance is disconnected from the main circuit simultaneously with connecting the target capacitance to the relaxation oscillator. The process continues at operation <NUM>, with connecting the target capacitance to a relaxation oscillator on the integrated circuit.

The process continues at operation <NUM>, with measuring an output of the relaxation oscillator. The measured output may be one or more of a voltage (e.g., threshold voltage), a current (e.g., currents through the relaxation oscillator), or a frequency (e.g., a frequency of an output of the relaxation oscillator). The process continues at operation <NUM>, with measuring the target capacitance based on the measured output. The process optionally continues at operation <NUM>, with tuning the target capacitance based on the measured target capacitance.

In an example aspect, the target capacitance includes two capacitors associated with a crystal oscillator. As described above with respect to <FIG>, the capacitances of the two capacitors may be measured in sequence, beginning with the second capacitor C<NUM> which is not connected to the parasitic capacitance CP. One or both of the capacitors may be tuned based on the measured capacitances.

Although the operations of <FIG> and <FIG> are illustrated in a series, this is for illustrative purposes and the operations are not necessarily order dependent. Some operations may be performed in a different order than that presented. For example, operations <NUM> and <NUM> may be performed simultaneously. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in <FIG> and <FIG>.

<FIG> is a block diagram of a computer system <NUM> suitable for implementing on-chip capacitance measurement and/or tuning according to embodiments disclosed herein. The computer system <NUM> comprises any computing or electronic device capable of including firmware, hardware, and/or executing software instructions that could be used to perform any of the methods or functions described above. In this regard, the computer system <NUM> may be a circuit or circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, an array of computers, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer.

The example computer system <NUM> in this embodiment includes a processing device <NUM> or processor, a system memory <NUM>, and a system bus <NUM>. The processing device <NUM> represents one or more commercially available or proprietary general-purpose processing devices, such as a microprocessor, central processing unit (CPU), or the like. More particularly, the processing device <NUM> may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or other processors implementing a combination of instruction sets. The processing device <NUM> is configured to execute processing logic instructions for performing the operations and steps discussed herein.

In this regard, the various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with the processing device <NUM>, which may be a microprocessor, field programmable gate array (FPGA), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the processing device <NUM> may be a microprocessor, or may be any conventional processor, controller, microcontroller, or state machine. The processing device <NUM> may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The system memory <NUM> may include non-volatile memory <NUM> and volatile memory <NUM>. The non-volatile memory <NUM> may include read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and the like. The volatile memory <NUM> generally includes random-access memory (RAM) (e.g., dynamic random-access memory (DRAM), such as synchronous DRAM (SDRAM)). A basic input/output system (BIOS) <NUM> may be stored in the non-volatile memory <NUM> and can include the basic routines that help to transfer information between elements within the computer system <NUM>.

The system bus <NUM> provides an interface for system components including, but not limited to, the system memory <NUM> and the processing device <NUM>. The system bus <NUM> may be any of several types of bus structures that may further interconnect to a memory bus (with or without a memory controller), a peripheral bus, and/or a local bus using any of a variety of commercially available bus architectures.

The computer system <NUM> may further include or be coupled to a non-transitory computer-readable storage medium, such as a storage device <NUM>, which may represent an internal or external hard disk drive (HDD), flash memory, or the like. Although the description of computer-readable media above refers to an HDD, it should be appreciated that other types of media that are readable by a computer, such as optical disks, magnetic cassettes, flash memory cards, cartridges, and the like, may also be used in the operating environment, and, further, that any such media may contain computer-executable instructions for performing novel methods of the disclosed embodiments.

An operating system <NUM> and any number of program modules <NUM> or other applications can be stored in the volatile memory <NUM>, wherein the program modules <NUM> represent a wide array of computer-executable instructions corresponding to programs, applications, functions, and the like that may implement the functionality described herein in whole or in part, such as through instructions <NUM> on the processing device <NUM>. The program modules <NUM> may also reside on the storage mechanism provided by the storage device <NUM>. As such, all or a portion of the functionality described herein may be implemented as a computer program product stored on a transitory or non-transitory computer-usable or computer-readable storage medium, such as the storage device <NUM>, volatile memory <NUM>, non-volatile memory <NUM>, instructions <NUM>, and the like. The computer program product includes complex programming instructions, such as complex computer-readable program code, to cause the processing device <NUM> to carry out the steps necessary to implement the functions described herein.

An operator, such as the user, may also be able to enter one or more configuration commands to the computer system <NUM> through a keyboard, a pointing device such as a mouse, or a touch-sensitive surface, such as the display device, via an input device interface <NUM> or remotely through a web interface, terminal program, or the like via a communication interface <NUM>. The communication interface <NUM> may be wired or wireless and facilitate communications with any number of devices via a communications network in a direct or indirect fashion. An output device, such as a display device, can be coupled to the system bus <NUM> and driven by a video port <NUM>. Additional inputs and outputs to the computer system <NUM> may be provided through the system bus <NUM> as appropriate to implement embodiments described herein.

Therefore, from one perspective, there have been described an on-chip capacitance measurement method and associated systems and devices. Embodiments described herein rely on using the capacitor under test in an on-chip relaxation oscillator configuration whose charging/discharging currents, supply voltage, and output frequency are measured individually in a measurement block. The voltage thresholds of the relaxation oscillation are calculated from the circuit elements and the measured supply voltage. Because the oscillation frequency of the relaxation oscillator is a function of the capacitance under test, the charging/discharging currents, and the supply voltage (via voltage thresholds), the capacitance under test can be calculated using the measured values of the other quantities. Embodiments described herein provide an accurate, low-power, small-area on-chip system capable of measuring capacitance with high accuracy. An algorithm employing the above method and apparatus for tuning a crystal oscillator is also provided. Relevant circuit implementations used in the on-chip measurement system are also disclosed.

The operational steps described in any of the example embodiments herein are described to provide examples and discussion. Additionally, one or more operational steps discussed in the example embodiments may be combined.

Claim 1:
A method for measuring on-chip capacitance, the method comprising:
disconnecting (<NUM>) a target capacitance from a main oscillation circuit of an integrated circuit;
connecting (<NUM>) the target capacitance to a relaxation oscillator on the integrated circuit;
measuring (<NUM>) an output of the relaxation oscillator; and
measuring (<NUM>) the target capacitance based on the measured output