Patent Description:
Avionics products often provide circuits to read, ascertain or otherwise determine discrete inputs from other equipment in the aircraft. The discrete inputs may conform, for example, to one of two types: OPEN/GND or 28V/OPEN. Avionics products have typically used two different circuits to accommodate the two discrete types, providing internal pullups for the OPEN/GND discrete input and internal pull downs for 28V/OPEN discrete input. Therefore, the avionics products have frequently provided a quantity of each circuit type to cover a variety of possible aircraft applications. For any given application, rarely are all the discrete inputs of both types utilized, and often there is a shortage of one type or the other. This may result in valuable hardware being left unused, reducing the flexibility and cost-effectiveness of the product.

<CIT> discloses a control apparatus responsive to signals of different interface types. <CIT>, citable only against novelty under Article <NUM>(<NUM>) EPC, discloses a self-testing voltage monitor system. : "<NPL>, discloses a window comparator having a single internal reference. <CIT> discloses an input discriminator device. <CIT> discloses an input stage of a processing circuit.

In one aspect of the present disclosure, a discrete input determining circuit is provided. The discrete input determining circuit comprises an input biasing network connected to a discrete input for providing a first input voltage, a voltage divider network for dividing the first input voltage into a second input voltage and a third input voltage, a first comparator and a second comparator. The discrete input is operable in any one of an OPEN state, a positive voltage state, and a GND state. A non-inverting input terminal of the first comparator receives the second input voltage, and an inverting input terminal of the second comparator receives the third input voltage. An inverting input terminal of the first comparator and a non-inverting input terminal of the second comparator receive a reference voltage, and an output terminal of the first comparator and an output terminal of the second comparator are configured to provide a logic output.

In another aspect of the present disclosure, a discrete input determining method is provided. The discrete input determining method comprises biasing the discrete input to provide a first input voltage, dividing the first input voltage into a second input voltage and a third input voltage, comparing the second input with a reference voltage and outputting a first output, comparing the reference voltage with the third input and outputting a second output, and outputting a logic output by a logic function between the first output and the second output. The discrete input is in any one of an OPEN state, a positive voltage state, and a GND state.

Embodiments of the present disclosure will be described hereinbelow with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid obscuring the disclosure in unnecessary detail.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as is commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the terms "a" and "an" do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term "or" is meant to be inclusive and mean either or all of the listed items. The use of "including," "comprising" or "having" and variations thereof herein are meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms "connected" and "coupled" are not restricted to physical or mechanical connections or couplings, and can include electrical connections or couplings, whether direct or indirect. In addition, Terms indicating specific locations, such as "top", "bottom", "left", and "right", are descriptions with reference to specific accompanying drawings. Embodiments disclosed in the present disclosure may be placed in a manner different from that shown in the figures. Therefore, the location terms used herein should not be limited to locations described in specific embodiments.

<FIG> illustrates a schematic diagram of a discrete input determining circuit <NUM>. As shown in <FIG>, the discrete input determining circuit <NUM> comprises an input biasing network <NUM> connected to a discrete input for providing a first input voltage V<NUM>, a voltage divider network <NUM> for dividing the first input voltage V<NUM> into a second input voltage V<NUM> and a third input voltage V<NUM>, a first comparator <NUM> and a second comparator <NUM>. A non-inverting input terminal "+" of the first comparator <NUM> receives the second input voltage V<NUM>, and an inverting input terminal "-" of the second comparator <NUM> receives the third input voltage V<NUM>. An inverting input terminal "-" of the first comparator <NUM> and a non-inverting input terminal "+" of the second comparator <NUM> receive a reference voltage Vref. An output terminal of the first comparator <NUM> and an output terminal of the second comparator <NUM> are configured to provide a logic output F.

In one embodiment, the input biasing network <NUM> comprises a first power supply <NUM> and a first resistive load R<NUM>. The first resistive load R<NUM> is connected between the discrete input and the first power supply <NUM>, and a node P<NUM> between the discrete input and the first resistive load R<NUM> is connected to the voltage divider network <NUM>. When the discrete input is in the OPEN state, the first input voltage V<NUM> is a voltage at the node P<NUM> and the first input voltage V<NUM> is less than a positive voltage V+ of the discrete input, for example, the positive voltage V+ is equal to <NUM> volts. It is to be appreciated that <NUM> volts is used herein for illustrative purposes; however, virtually any voltage would be within the scope of the subject innovation.

The voltage divider network <NUM> can include a second resistive load R<NUM> and a third resistive load R<NUM> connection in series between the node P<NUM> and a ground. The second input voltage V<NUM> is a voltage at a node P<NUM> between the node P<NUM> and the second resistive load R<NUM>, and the third input voltage V<NUM> is a voltage at a node P<NUM> between the second resistive load R<NUM> and the third resistive load R<NUM>. In this case, the second input voltage V<NUM> is less than the first input voltage V<NUM>, and the third input voltage V<NUM> is less than the second input voltage V<NUM>. In another embodiment, the voltage divider network <NUM> further comprises a fourth resistive load R<NUM> connection in series between the node P<NUM> and the node P<NUM>, in this case, the second input voltage V<NUM> is less than the first input voltage V<NUM>. In one embodiment, when the discrete input is in an OPEN state, the first input voltage V<NUM> is determined by the relationship among the first power supply <NUM>, the first resistive load R<NUM>, the second resistive load R<NUM>, the third resistive load R<NUM>, and the fourth resistive load R<NUM>.

As for the first comparator <NUM>, the non-inverting input terminal "+" can be connected to the node P<NUM> for receiving the second input voltage V<NUM>, and the inverting input terminal "-" receives the reference voltage Vref. For example, when the second input voltage V<NUM> is larger than the reference voltage Vref, the first comparator <NUM> outputs a logic high level; when the second input voltage V<NUM> is less than the reference voltage Vref, the first comparator <NUM> outputs a logic low level. As for the second comparator <NUM>, the non-inverting input terminal "+" receives the reference voltage Vref, and the inverting input terminal "-" is connected to the node P<NUM> for receiving the third input voltage V<NUM>. When the third input voltage V<NUM> is larger than the reference voltage Vref, the second comparator <NUM> outputs the logic low level; when the third input voltage V<NUM> is less than the reference voltage Vref, the second comparator <NUM> outputs the logic high level. In an optional embodiment, the first comparator <NUM> and the second comparator <NUM> can be replaced by a window comparator or a dual comparator.

The output terminal of the first comparator <NUM> and the output terminal of the second comparator <NUM> can be open-collector type outputs that are wired together to implement a logic AND function so as to provide the logic output F, in this case, the discrete input determining circuit <NUM> further comprises an output configuration network <NUM>, wherein the output configuration network <NUM> comprises a second power supply <NUM> and a fifth resistive load R<NUM> connected between the second power supply <NUM> and the logic output F.

The discrete input determining circuit <NUM> can accommodate both OPEN/GND and 28V/OPEN discrete input types, and application of the discrete input determining circuit is more flexible and cost effective. The logic output can be routed to any general-purpose input or output (GPIO) pin on a microprocessor or a field programmable gate array (FPGA) used for the host product data processing.

<FIG> illustrates a flow chart of a discrete input determining method <NUM> in accordance with an embodiment of the present disclosure. The discrete input determining method <NUM> may include the steps as follows.

In step <NUM>, a first input voltage is provided by biasing a discrete input.

In step <NUM>, the first input voltage is divided into a second input voltage and a third input voltage. In one embodiment, the first input voltage is less than the positive voltage of the discrete input, and the second input voltage is less than the first input voltage, and the third input voltage is less than the second input voltage.

In step <NUM>, the second input voltage is compared with a reference voltage and a first output signal is outputted. In one embodiment, when the discrete input is in an OPEN state, the second input voltage is larger than the reference voltage so that the first output is a logic high level; when the discrete input is in the positive voltage state, the second input voltage is larger than the reference voltage so that the first output is the logic high level; when the discrete input is in a GND state, the second input voltage is less than the reference voltage so that the first output voltage is a logic low level.

In step <NUM>, the reference voltage is compared with the third input voltage and a second output is outputted. In one embodiment, when the discrete input is in the OPEN state, the reference voltage is larger than the third input voltage so that the second output is the logic high level; when the discrete input is in the positive voltage state, the reference voltage is less than the third input voltage so that the second output is the logic low level; when the discrete input is in the GND state, the reference voltage is larger than the third input voltage so that the second output is the logic high level.

In step <NUM>, a logic output is outputted by a logic function between the first output and the second output. In one embodiment, the logic function comprises a logic AND function, wherein when the discrete input is in the OPEN state, the logic output is the logic high level; when the discrete input is in the positive voltage state or the GND state, the logic output is the logic low level.

While steps of the discrete input determining method in accordance with embodiments of the present disclosure are illustrated as functional blocks, the order of the blocks and the separation of the steps among the various blocks shown in <FIG> are not intended to be limiting. For example, the blocks may be performed in a different order and a step associated with one block may be combined with one or more other blocks or may be subdivided into a number of blocks.

Claim 1:
A discrete input determining circuit (<NUM>), comprising:
an input biasing network (<NUM>) connected to a discrete input for providing a first input voltage (V<NUM>), wherein the discrete input is operable in any one of an OPEN state, a positive voltage state, and a GND state;
a voltage divider network (<NUM>) for dividing the first input voltage (V<NUM>) into a second input voltage (V<NUM>) and a third input voltage (V<NUM>);
a first comparator (<NUM>), wherein a non-inverting input terminal of the first comparator receives the second input voltage (V<NUM>); and
a second comparator (<NUM>), wherein an inverting input terminal of the second comparator receives the third input voltage (V<NUM>);
characterised in that: an inverting input terminal of the first comparator receives a reference voltage (Vref) and a non-inverting input terminal of the second comparator receives the reference voltage (Vref), and an output terminal of the first comparator and an output terminal of the second comparator are configured to provide a logic output (F).