Patent Description:
Mainboards, motherboards (or mobos), main circuit boards, base boards, planar boards or system boards are types of boards including a main circuit therein and are employed in electronic devices such as computers and elevators. Such a board is a main component of a scalable electronic device such as a computer and is an electronic board in which circuits for integration and connection of various types of cables or wires and an input/output port are installed. Such a board may be a printed circuit board (PCB) on which main components such as a central processing unit (CPU) or a random access memory (RAM) are mounted to operate a system and which provides an interface for connection to peripheral devices. A board installed in Apple's Macintosh or iPhone is called a logic board.

In a motherboard for a PC, a sound card and a network card are generally included and a CPU, a RAM, and a storage device may be further included according to a purpose.

A general-purpose board for a computer is a general type of manufactured board in which most major parts of a desktop computer can be used, and is also referred to as a main board. A special-purpose board is a board manufactured for a special purpose and has a stand-alone structure unlike a general-purpose board. Such a main board is used in notebook computers, game consoles, mobile phones, etc..

However, with the recent growing demand for music servers that reflect changes and the pursuit of convenience in digital music playback media (e.g., Compact Disc/Digital Versatile Disc (CD/DVD) → digital string play), achieving of high resolution, high sound quality, high-precision control, etc. is very limited in the case of existing audio/video (A/V) servers for audio streaming, medical computers, military computers, and various types of computers for high-precision control (e.g., three-dimensional (3D) printing).

In other words, when an existing computer is used in such an environment, much noise may occur and the quality of a clock may be degraded.

Documents <CIT>, <CIT> and <CIT> illustrate the technological background of the present invention.

<CIT> discloses a processor comprising: a plurality of voltage regulators; a plurality of clock generators; and a plurality of cores, wherein each core is coupled to one of the plurality of voltage regulators and one of the plurality of clock generators, and wherein at least one core is to perform an atomic ratio change of the corresponding clock generator responsive to a request to change a frequency of the at least one core.

<CIT> discloses a phase-locked loop integrated circuit comprising an analog-to-digital converter (ADC) responsive to a control voltage at an input thereof; a digital-to-analog converter (DAC) having an input responsive to an ADC output signal generated at an output of said ADC, said DAC input directly receiving a digital signal that retains all material digital information contained in the ADC output signal; and an impedance element having real and reactive components, a first current carrying terminal electrically coupled to an output of said DAC and a second current carrying terminal electrically shorted to the input of said ADC, said first current carrying terminal directly receiving an analog signal that retains all material analog information contained in a DAC output signal generated at the output of said DAC.

<CIT> discloses a regulator for providing a plurality of output voltages, comprising: a basic unit, amplifying an input voltage to obtain a core voltage according to a first control signal; and a plurality of replica units, each outputting one of the output voltages according to the input voltage and one of a plurality of second control signals, wherein at least two of the output voltages have different voltage levels, wherein the first control signal is set according to the second control signals, to make the voltage level of the core voltage substantially equal to or less than a maximum voltage level of the output voltages and substantially equal to or greater than a minimum voltage level of the output voltages.

Embodiments of the present disclosure are directed to providing a computing device in which ultra-low noise occurs and use of ultra-precision clocks is permitted for a music server for audio streaming, and a driving method of the computing device, because much noise occurs and low-quality clocks are used in existing computing devices such as computers or servers and thus the existing computing devices cannot be used in places requiring high sound quality, high resolution, and high precision.

The present invention relates to a computing device as defined in claim <NUM>, and to a driving method of a computing device as defined in claim <NUM>.

The above and other objects, features and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which:.

Descriptions of specific structures or functions of embodiments of the present disclosure are provided to merely describe embodiments of the present disclosure, and embodiments according to the present disclosure may be implemented in various forms and should not be understood as being limited to embodiments described in the present specification or application.

Various modifications may be made in embodiments according to the present disclosure and these embodiments may be implemented in various forms, and thus certain embodiments are illustrated in the drawings and described in detail in the present specification or application.

Terms such as first, second, etc. may be used to describe various components but the components are not limited by the terms. These terms are only used to distinguish one component from another component. For example, a first component could be termed a second component without departing from the scope of the present disclosure, and similarly, a second component could be termed a first component.

When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the component may be directly coupled or connected to the other component but another component may be interposed therebetween. In contrast, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that no component is interposed therebetween. Other expressions that describe a relationship between components, i.e., "between," "immediately between," "neighboring," "immediately neighboring to," etc. should be understood similarly.

The terms used herein are only used to describe certain embodiments and are not intended to limit the present disclosure. As used herein, the singular expressions are intended to include plural forms as well, unless the context clearly dictates otherwise. It should be understood that the terms "comprise" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, components, or a combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure pertains. Terms such as those defined in a commonly used dictionary should be interpreted as having meanings consistent with meanings in the context of related technologies and should not be interpreted with ideal or excessively formal meanings unless explicitly defined herein.

Hereinafter, the present disclosure will be described in detail by describing embodiments thereof with reference to the accompanying drawings. The same reference numerals shown in each drawing represent the same elements.

<FIG> is a diagram illustrating a structure of a computing device according to an embodiment of the present disclosure. <FIG> is a block diagram illustrating an example of a detailed structure of a motherboard of <FIG>.

As shown in <FIG>, a computing device <NUM> according to the embodiment of the present disclosure is a computing device used in, for example, an audio/video (A/V) server for audio streaming, a medical computer, a military computer requiring precise signal processing, or a computer requiring any of various types of precise control, such as three-dimensional (3D) printing, and includes some or all of a protection circuit unit <NUM>, a voltage supply <NUM>, and a motherboard <NUM>.

Here, "includes some or all of the protection circuit unit <NUM>, the voltage supply <NUM>, and the motherboard <NUM>" may be understood to mean that part of the computing device <NUM>, such as the protection circuit unit <NUM> or the voltage supply <NUM>, may be omitted or integrated with another component such as the motherboard <NUM>, but in order to assist with understanding of the present disclosure, it will be described herein that the computing device <NUM> includes all of the protection circuit unit <NUM>, the voltage supply <NUM>, and the motherboard <NUM>.

The protection circuit unit <NUM> may perform an operation to prevent electromagnetic interference of various types of electronic components on the motherboard <NUM> of the computing device <NUM>, and perform an operation to prevent problems such as over power, an overcurrent, and an overvoltage from occurring in the voltage supply <NUM>, i.e., a linear power supply according to an embodiment of the present disclosure, or protect a product or circuit when such a problem occurs. A representative example of the operations may be an automatic or temporary power shut-off function. The protection circuit unit <NUM> may be configured in various forms and thus is not limited to any form in embodiments of the present disclosure.

The voltage supply <NUM> supplies operating power or a power supply voltage Vcc to, for example, various types of elements in the form of an integrated circuit (IC), such as a central processing unit (CPU), a random access memory (RAM), or a local area network (LAN) on the main board <NUM>. The amounts of power required for these elements are different from each other. Thus, the voltage supply <NUM> is configured to generate various voltages to be used. In an embodiment of the present disclosure, effects of high sound quality, high precision, etc. are required and it is important to prevent noise from being delivered when power is supplied to each component. Accordingly, the voltage supply <NUM> according to an embodiment of the present disclosure may be operated while connected to linear regulators configured on the main board <NUM>.

The voltage supply <NUM> generally receives commercial power of <NUM> V and converts the commercial power into a direct current (DC) voltage of a predetermined level. To this end, the voltage supply <NUM> may include a DC-DC converter in addition to a rectifier, a smoothing circuit, and the like. Accordingly, it possible to generate and provide a highest voltage among power supply voltages of the elements on the main board <NUM>. For example, when the highest voltage is DC <NUM> V, a voltage of <NUM> V may be generated and provided. Alternatively, the voltage supply <NUM> according to an embodiment of the present disclosure may generate and provide various voltages while connected in parallel with regulators, and thus is not limited to only one form.

The motherboard <NUM> may be referred to as a main board, a main circuit or the like. The motherboard <NUM> may be a printed circuit board (PCB) for forming a main circuit of a CPU or a microprocessor unit (MPU) for operating the computing device <NUM>, a graphics processing unit (GPU), or the like. Alternatively, the motherboard <NUM> may further include peripheral circuits such as a communication module or a memory. <FIG> illustrates a case in which a (linear) regulator unit <NUM>, a plurality of elements <NUM> to <NUM> such as integrated circuit (IC) chips, and a (femto) clock generator <NUM> are configured on a main substrate.

Referring to <FIG>, the regulator unit <NUM> is connected to the voltage supply <NUM> of <FIG> to receive a voltage. The regulator unit <NUM> includes a plurality of regulators for supplying different voltages, e.g., <NUM> V, <NUM> V, <NUM> V, etc., to a RAM <NUM>, a CPU <NUM>, etc. More specifically, linear regulators may be configured to correspond to all elements requiring a power supply voltage. Therefore, the power supply voltage may be provided after being converted into a voltage with ultra-low noise (e.g., <<NUM> mV), which is required for each element, e.g., each chip. For example, in the case of a switched mode power supply (SMPS) regulator, much noise may occur during a switching operation of a switching element and be delivered to devices, i.e., elements, which are connected thereto, and thus, in an embodiment of the present disclosure, the SMPS regulator is not preferable and a linear regulator may be used.

The linear regulator employs a voltage dropping method, i.e., a method of directly dropping a voltage, and may be a type of DC-DC converter. In an embodiment of the present disclosure, a linear regulator that is relatively simple and in which low noise occurs is used. The plurality of linear regulators are connected in series to receive a voltage used in a preceding linear regulator and drop the voltage. Therefore, ultra-low noise may be achieved and thus noise may be reduced by a factor of <NUM> more when compared to, for example, in a computer employing an SMPS, thereby minimizing an effect on an external apparatus, and thus the linear regulator can be advantageously used in processing sensitive signals for audio, medical, military, and precision control purposes. In an embodiment of the present disclosure, the linear regulator may be very useful for a music server or the like. The linear regulator will be described in more detail below.

The plurality of elements <NUM> to <NUM> may include various types of elements configured in the form of an IC chip on the main substrate of the main board <NUM>. Each of the plurality of elements <NUM> to <NUM> may request the power supply voltage Vcc or a bias voltage for an operation thereof and thus may be supplied with a low-noise voltage from the linear regulator and perform a precision operation that generates low noise.

The main board <NUM> includes a processor such as the CPU <NUM>, an MPU, or a GPU for control of overall operations of the RAM <NUM>, the LAN <NUM>, and a Universal Serial Bus (USB) <NUM>. For example, the CPU <NUM> may temporarily store data provided through the LAN <NUM>, the USB <NUM>, etc. in the RAM <NUM>, and read and process the data. The CPU <NUM> may also perform a control operation to provide the elements <NUM> to <NUM> with a voltage provided through the regulator unit <NUM>. In addition, the CPU <NUM>, i.e., a controller, may use a clock signal generated by the clock generator <NUM> to synchronize the elements <NUM> to <NUM>. In other words, the generated clock signal may be used to synchronize the elements <NUM> to <NUM>.

The main board <NUM> further includes the clock generator <NUM> to generate a clock. The clock generator <NUM> generates femto-clocks for generating an ultra-precision clock according to an embodiment of the present disclosure. A clock generator that generates such a clock may include an oscillator. A femto-clock may be understood as having a frequency of <NUM> or less but in an embodiment of the present disclosure, different frequencies may be used in a frequency range of <NUM> or less. The clock generator <NUM> may use a precise clock that is more accurate at least <NUM> times or more than, for example, a crystal clock, thereby achieving high resolution, high sound quality, high-precision control, etc. A clock generated by the clock generator <NUM> may be used to control operations of the elements <NUM> to <NUM> and thus the clock generator <NUM> may generate clocks of various frequencies. To this end, clock generators or oscillators, the number of which is the same as that of the plurality of elements <NUM> to <NUM>, may be provided. Alternatively, in an embodiment of the present disclosure, a clock generator may be implemented in a linear form to sequentially convert a high-frequency clock into low-frequency clocks to be used. A frequency multiplier is configured to double or triple a frequency, but may be used to increase or decrease a frequency. The clock generator will be described in more detail below.

Due to the above configuration, according to an embodiment of the present disclosure, a higher quality clock having a small jitter delay, than, for example, a crystal clock, may be supplied to or used for the elements <NUM> to <NUM>, thereby enabling ultra-precision control of devices.

In an embodiment of the present disclosure, in the computing device <NUM> of <FIG>, linear regulators are configured to correspond to the elements <NUM> to <NUM>, and thus a device such as a cooler may not be needed to reduce heat in a regulator or the like. Generally, a linear regulator may include a heat sink plate to reduce heat, and in the related art, a fan is provided to discharge heat to the outside. However, such a component may not be needed.

<FIG> is a diagram illustrating an example of a detailed structure of the regulator unit of <FIG>. <FIG> is a diagram illustrating an example of a detailed structure of the clock generator of <FIG>. <FIG> is a diagram for describing improvement of voltage noise and jitter in the related art.

Referring to <FIG>, the regulator unit <NUM> of <FIG> includes a plurality of linear regulators, and the plurality of linear regulators are each connected to one of elements <NUM> to <NUM> of an element unit <NUM>.

The plurality of linear regulators are connected in series to one another such that they are configured in a linear form, i.e., in a line. Due to the above configuration, a first linear regulator receiving a highest voltage from the voltage supply <NUM> stabilizes the highest voltage, i.e., removes noise from the highest voltage, and supplies the stabilized voltage to an element CHIP #N connected to the first linear regulator, or a second linear regulator connected to the first linear regulator drops a voltage of the first linear regulator and supplies a stabilized voltage to an element CHIP #<NUM> connected to the second linear regulator. In an embodiment of the present disclosure, a noise-free voltage may be generated and provided without removing noise from a voltage. As described above, when the plurality of linear regulators are configured in a linear form, it may be useful in reducing power consumption or heat generation that occurs during a voltage drop. For example, the amounts of energy, i.e., power consumption rates, when a voltage of <NUM> V is dropped to <NUM> V and when the voltage of <NUM> V is dropped to directly to <NUM> V may be different from each other. In this case, the amount of heat generated is extremely large and thus sequential voltage dropping, i.e., a step-down operation, may be performed as described above with reference to <FIG>.

Alternatively, signals from the plurality of linear regulators may be provided to the CPU <NUM> of <FIG> for a monitoring operation and thus embodiments of the present disclosure are not particularly limited to any one form. Conversely, the CPU <NUM> may be connected to each linear regulator to control an operation thereof.

As shown in <FIG>, the clock generator <NUM> of <FIG> according to the embodiment of the present disclosure includes a plurality of clock generators, and each of the clock generators may be operated while connected to one of the plurality of elements <NUM> to <NUM>.

The plurality of clock generators may be clock generators that generate femto-clocks (e.g., <<NUM> femto sec) and may include a frequency generator, i.e., an oscillator. The plurality of clock generators may be operated under control of the CPU <NUM> of <FIG>, and the CPU <NUM> may perform control operations of the plurality of clock generators. Each of the clock generators, i.e., femto-clock generators, may be used to generate femto-clocks of various frequencies in a frequency range of <NUM> to <NUM> to operate the elements <NUM> to <NUM>. In <FIG>, the plurality of femto-clock generators may not be connected in series unlike a plurality of linear regulators connected in series, but embodiments of the present disclosure are not particularly limited thereto.

Due to the above configuration, a clock with very high jitter quality may be supplied using a femto-clock and thus purposes such as high resolution, high sound quality, and high-precision control may be achieved in the fields of audio, medical, and military technologies.

In other words, according to an embodiment of the present disclosure, the demand for a music server that reflects changes in digital music playback media can be flexibly responded to, and problems such as degradation of sound quality due to noise in existing computers and a low-quality clock or during playback of sound between a computer and a network may be fixed.

A computer is basically using a bit perfect technique, but the quality of power and the quality of a clock are very important factors that affect work performed in real time. Therefore, such important factors can be enhanced according to embodiments of the present disclosure. Here, the bit perfect technique is a technique for reproducing a sound source so that a bit depth/sampling rate of the sound source may be the same as that of a device (e.g., a sound card or a digital-to-analog converter (DAC)) that outputs the sound source, and is one technique used to improve the quality of sound when music is listened to.

<FIG> illustrates a comparison between noise in the linear regulator of <FIG> and noise in a general SMPS regulator, and noise in the general SMPS regulator is <NUM> mV but noise in a linear regulator according to an embodiment of the present disclosure is <NUM> mV or less as illustrated in <FIG>.

<FIG> illustrates a result of comparison of distortion of a waveform, i.e., jitter, due to a clock. As shown in <FIG>, jitter, i.e., a delay of a clock, may occur when a general crystal clock is used. Due to this problem, synchronization may not be accurately performed. Accordingly, in an embodiment of the present disclosure, a high-precision femto-clock may be used and femto-clock generators may be provided to correspond to the elements <NUM> to <NUM>, thereby reducing jitter. Here, the jitter is a value indicating a degree to which a signal occurs earlier or later than a reference point in time and indicates the difference between an ideal edge pointer and an actually measured waveform.

<FIG> is a flowchart of a driving process of the computing device of <FIG> according to an embodiment of the present disclosure.

Referring to <FIG> and <FIG> for convenience of description, in the computing device <NUM> of <FIG>, a linear regulator unit with a plurality of linear regulators converts a voltage supplied from a power supply into different voltages required for a plurality of elements and provides the different voltages to the plurality of elements (S600). For example, when the number of different voltages used in the computing device <NUM> is ten, the number of the plurality of linear regulators may be ten. Alternatively, when ten elements such as IC chips use a power supply voltage Vcc, ten linear regulators corresponding to the ten elements may be configured on a main board. Alternatively, in the above configuration, when a plurality of elements use the same voltage, linear regulators may be configured to be used through a common connection, or different linear regulators may be used. Linear regulators may be configured in various forms according to a system designer's intention and thus are not limited to only one form in an embodiment of the present disclosure.

Next, in the computing device <NUM>, a femto-clock generator with a plurality of femto-clock generators generates femto-clocks of different frequencies to be used for control of operations of a plurality of elements (S610). For example, clocks supplied to elements may be used for synchronization, and synchronization may be necessarily required for precision control.

The computing device <NUM> of <FIG> may perform various other operations, and these operations have been described above and thus redundant description is omitted.

According to an embodiment of the present disclosure, neighboring apparatuses are not negatively affected due to low noise, and a high-precision clock can be used to achieve high resolution, high sound quality, and an accurate control result when used in various fields of control.

In an embodiment of the present disclosure, a computer with high sound quality, which is capable of using not only audio data but also a general-purpose windows operating system (OS), can be manufactured and provided at a reasonable cost.

Although all components according to embodiments of the present disclosure are described as being combined together or operated in combination, the present disclosure should not be understood as being limited to the embodiments. That is, as long as the embodiment is within the scope of the present disclosure, at least one of all of the components may be selectively combined and operated. Each of the components may be implemented as one independent hardware component, or some or all of the components may be selectively combined and embodied as a computer program including program modules for performing some or all functions of a combination of one or more hardware components. Code and code segments of the computer program may be easily deduced by those of ordinary skill in the technical field of the present disclosure. The computer program may be stored in a non-transitory computer-readable medium and read and executed by a computer to implement an embodiment of the present disclosure.

Claim 1:
A computing device (<NUM>) with a main board (<NUM>) including a plurality of elements (<NUM>, <NUM>, <NUM>, <NUM>), the computing device (<NUM>) comprising:
a clock generation unit including a plurality of clock generators (<NUM>) configured to generate clocks of different frequencies to be used for control of operations of the plurality of elements (<NUM>, <NUM>, <NUM>, <NUM>),
wherein the plurality of clock generators (<NUM>) are connected to a processor on the main board (<NUM>), and
the processor controls the operations of the plurality of elements (<NUM>, <NUM>, <NUM>, <NUM>) using the clocks generated by the plurality of clock generators (<NUM>),
characterized in that:
each of the clock generators (<NUM>) is configured to generate clocks of various frequencies in a frequency range of <NUM> to <NUM>;
the computing device (<NUM>) further comprises a linear regulator unit (<NUM>) including a plurality of linear regulators configured to convert a voltage from a power supply into different voltages required for the plurality of elements (<NUM>, <NUM>, <NUM>, <NUM>) and apply the different voltages; and
the plurality of linear regulators are connected in series to receive a voltage used in a preceding linear regulator and drop the received voltage,
wherein a first linear regulator of the plurality of linear regulators receives a highest voltage from the power supply, stabilizes the highest voltage by removing noise from the highest voltage and supplies the stabilized voltage to an element CHIP N connected to the first linear regulator, and
a second linear regulator connected to the first linear regulator drops an output voltage of the first linear regulator and supplies a stabilized voltage by removing noise from the dropped voltage to an element CHIP (N-<NUM>) connected to the second linear regulator.