Patent Description:
Existing and emerging consumer applications have created an increasing need for real-time three-dimensional (3D) imagers. These imaging devices, also commonly known as depth sensors or depth mappers, enable the remote measurement of distance (and often intensity) of each point on a target scene - so-called target scene depth - by illuminating the target scene with one or more optical beams and analyzing the reflected optical signal.

Various methods are known in the art for generating light sources based on arrays of multiple light-emitting elements of optical radiation on a monolithic semiconductor substrate.

<CIT> describes an optical apparatus, which includes a beam source configured to generate an optical beam having a pattern imposed thereon. In one embodiment, an optoelectronic device comprises a semiconductor die on which a monolithic array of vertical-cavity surface-emitting laser (VCSEL) diodes is formed in a two-dimensional pattern that is not a regular lattice. The term "regular lattice" means a two-dimensional pattern in which the spacing between adjacent elements in the pattern (for example, between adjacent emitters in a VCSEL array) is constant and is synonymous with a periodic lattice. The pattern can be uncorrelated, in the sense that the auto-correlation of the positions of the laser diodes as a function of transverse shift is insignificant for any shift larger than the diode size. Random, pseudo-random, and quasi-periodic patterns are examples of such uncorrelated patterns.

<CIT> is related to a surface emitting semiconductor laser having a resonator in the vertical direction and emits light in the vertical direction. It requires a dummy laser to a have a laser oscillation which is shielded by an electrode so as to generate corresponding hear. It does not disclose electrodes configured not to inject an excitation current into a quantum well structure so that optoelectronic cells in a second set do not emit laser radiation.

<CIT> is directed to multi-zone illumination devices. As shown in Fig. 1A, to create electrical contacts for an array of VCSELs, a number of VCSEL mesas <NUM> are formed on a GaAs substrate, together with "shorting/grounding" mesas <NUM> (paragraph <NUM>). Similarly, <FIG> show arrays of VCSELs on a GaAs die, with inactive mesas at the edges of the dies. In <FIG>, multiple arrays of VCSELs are mounted side by side in an illumination module <NUM> (paragraph <NUM>). The active and inactive mesas are not interleaved on a die. Rather, they are segregated, with the inactive mesas at the edges of the group of active mesas.

<CIT> is related to a surface emitting laser array device used as a light source for optical information processing, optical communication, or an image forming apparatus using light. It does not disclose a second set of optoelectronic cells interleaved on a semiconductor die with a first set of optoelectronic cells.

<CIT> relates to a structure light source for generating high resolution passive and dynamically reconfigurable structure illumination patterns. It does not disclose a second set of optoelectronic cells interleaved on a semiconductor die with a first set of optoelectronic cells.

<CIT> relates to a VCSEL having a lower reflecting mirror, a resonator structure including an active layer, and a light emitting portion of a mesa structure in which an upper reflecting mirror is stacked on a substrate. It does not disclose a second set of optoelectronic cells interleaved on a semiconductor die with a first set of optoelectronic cells.

Embodiments of the present invention that are described hereinbelow provide improved methods for fabricating patterned light sources and light sources that can be produced by such methods.

There is therefore provided, in accordance with an embodiment of the invention, an optoelectronic device, including a semiconductor substrate and an array of optoelectronic cells, which are formed on the semiconductor substrate. The cells include first epitaxial layers defining a lower distributed Bragg-reflector (DBR) stack; second epitaxial layers formed over the lower DBR stack, defining a quantum well structure; third epitaxial layers, formed over the quantum well structure, defining an upper DBR stack; and electrodes formed over the upper DBR stack, which are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell. The array includes a first set of the optoelectronic cells that are configured to emit laser radiation in response to the excitation current and a second set of the optoelectronic cells, interleaved with the first set, in which at least one element of the optoelectronic cells, selected from among the epitaxial layers and the electrodes, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

In a disclosed example, the array is a regular array, while the first set of the optoelectronic cells are arranged in an uncorrelated pattern within the array.

In one example, the second set of the optoelectronic cells include implanted ions in the upper DBR stack, which increase an electrical resistance of the upper DBR stack by an amount sufficient to reduce the excitation current injected into the quantum well structure to below a threshold required for emitting laser radiation.

In accordance with the invention, the electrodes of the second set of the optoelectronic cells are configured so as not to inject the excitation current into the quantum well structure. In one example, the optoelectronic cells include an isolation layer between the epitaxial layers and the electrodes, and a part of the isolation layer is etched away in the first set of the optoelectronic cells and is not etched in the second set of the optoelectronic cells, so that the excitation current is not injected into the quantum well structure of the second set of the optoelectronic cells. In another example, the device includes conductors configured to feed electrical current to the optoelectronic cells, and an isolation layer, which isolates the electrodes of the second set of the optoelectronic cells from the conductors, so that the electrical current is not fed to the electrodes of the second set of the optoelectronic cells.

Additionally or alternatively, the device includes an isolation layer formed between the lower and upper DBR stacks, wherein the isolation layer is etched out of an area of the quantum well structure in the first set of the optoelectronic cells and is not etched out of the second set of the optoelectronic cells.

There is also provided, in accordance with the invention, a method for manufacturing an optoelectronic device. The method includes depositing first epitaxial layers on a semiconductor substrate to define a lower distributed Bragg-reflector (DBR) stack. Second epitaxial layers are deposited over the first epitaxial layers to define a quantum well structure. Third epitaxial layers are deposited over the second epitaxial layers to define an upper DBR stack. The epitaxial layers are etched to define an array of optoelectronic cells. Electrodes are deposited over the third epitaxial layers electrodes and are configurable to inject an excitation current into the quantum well structure of each optoelectronic cell so as to cause a first set of the optoelectronic cells to emit laser radiation in response to the excitation current. At least one element, selected from among the epitaxial layers and the electrodes, of a second set the optoelectronic cells, which is interleaved with the first set, is configured so that the optoelectronic cells in the second set do not emit the laser radiation.

Light sources emitting multiple beams are used, inter alia, in <NUM>-D (three-dimensional) mapping applications based on optical triangulation. As described in the above-mentioned <CIT>, it is advantageous to use a light source that projects a random or pseudo-random pattern on the target to be mapped. A desirable emitter for such a light source is a VCSEL (vertical-cavity surface-emitting laser) array, due to low power consumption, high reliability, and good beam quality. A random or pseudo-random pattern of emitters in a VCSEL array can be generated by a corresponding photolithographic mask. The non-periodic distribution of the emitters, however, may lead to reduced control over the photoresist pattern CD (critical dimensions), as well as poor etch uniformity due to uneven etch load effects.

The embodiments of the present invention that are described herein address the above limitations by fabricating a VCSEL array on a uniform grid, and disabling individual emitters. The disabled emitters can be interleaved with the enabled (operating) emitters in substantially any desired pattern, for example in a pseudo-random or otherwise uncorrelated pattern. The disclosed embodiments selectively disable emitters using modifications in the VCSEL fabrication process, for example by modifying the epitaxial layers or the electrodes of the VCSELs. As the design is based on a uniform grid, it can be manufactured reliably using standard photolithographic methods.

<FIG> is a schematic top view of an optoelectronic device comprising a semiconductor die <NUM> on which a monolithic array of enabled optoelectronic cells <NUM>, such as VCSELs, has been formed in an uncorrelated two-dimensional pattern, in accordance with an embodiment of the present invention. The array is formed on the semiconductor substrate by the same sort of photolithographic methods as are used to produce VCSEL arrays that are known in the art, with suitable thin film layer structures forming the VCSELs, and conductors providing electric power and ground connections from contact pads <NUM> to VCSELs <NUM> in the array.

The sort of uncorrelated pattern of enabled VCSELs <NUM> is produced using substantially the same processes as are used in fabricating a regular array (i.e., an array in the form of a regular lattice) of VCSEL-like cells. In contrast to a conventional regular array, however, only VCSELs <NUM> are selectively enabled, while disabling the remaining VCSEL-like cells. These disabled cells are referred to herein as "dummy cells <NUM>," since they are nearly identical in structure to VCSELs <NUM> but are incapable of laser emission due to thin film layer properties that are configured in the manufacturing process. In the following, the terms "disabling" and "disabled" are used synonymously with "not enabling" and "not enabled", respectively.

The ability to create an array of operating emitters in substantially any desired pattern, for example in a pseudo-random or otherwise uncorrelated pattern, based on a regular array of cells, has several advantages:.

<FIG> are schematic sectional views of enabled and disabled VCSELs. Each figure compares an enabled VCSEL (that can be used as the basis for enabled VCSELs <NUM>), in a figure labeled by "a", to a disabled VCSEL (as a possible basis for dummy cells <NUM>), in a figure labeled by "b". As the enabled and disabled VCSELs share most of the same elements, a detailed description of an enabled VCSEL is given with reference to <FIG>, below.

<FIG> are schematic sectional views of an enabled VCSEL <NUM> and a disabled VCSEL <NUM>, in accordance with an embodiment of the present invention.

Enabled VCSEL <NUM> in <FIG> is formed on a semiconductor substrate <NUM>. Epitaxial semiconductor layers of a VCSEL (a lower n-type distributed Bragg-reflector [n-DBR] stack <NUM>, a quantum well structure <NUM>, and an upper p-DBR stack <NUM>) are deposited over an area of semiconductor substrate <NUM>. Between n-DBR stack <NUM> and p-DBR stack <NUM> a confinement layer <NUM>, typically Al-oxide, is formed and patterned. Following the deposition of p-DBR stack <NUM>, an isolation layer <NUM> is deposited and patterned, and one or more p-electrodes <NUM> and n-electrodes <NUM> are deposited and patterned. Isolation trenches <NUM> are etched to define the array of VCSELs and to isolate neighboring VCSELs. Additionally, an isolation implant <NUM>, such as a proton implant, may be deposited adjacent to p-DBR stack <NUM> and quantum well structure <NUM> for increased isolation between neighboring VCSELs.

Disabled VCSEL <NUM> in <FIG> differs from enabled VCSEL <NUM> in that in the disabled VCSEL, isolation implant <NUM> extends into p-DBR stack <NUM> and possibly into quantum well structure <NUM>. Due to the lattice damage caused by the ion implantation, the resistance of the implanted layers increases from the non-implanted state, lowering the excitation current injected into quantum well structure <NUM> to below the threshold required for emitting laser radiation. As a result, the VCSEL is disabled and will not emit laser radiation.

Disabling of VCSEL <NUM> is achieved in the fabrication process by a modification of the photomask responsible for defining the lateral distribution of the deposition of isolation implant <NUM> so as to permit implantation ions to reach p-DBR stack <NUM> and possibly quantum well structure <NUM>.

<FIG> are schematic sectional views of an enabled VCSEL <NUM> and a disabled VCSEL <NUM>, in accordance with another embodiment of the present invention. Enabled VCSEL <NUM> is substantially similar to enabled VCSEL <NUM> of <FIG>, except that the present embodiment does not necessarily comprise isolation implant <NUM> for isolating neighboring VCSELs. Disabling VCSEL <NUM> is accomplished by preventing the injection of excitation current into p-DBR stack <NUM> and quantum well structure <NUM>. The differences between enabled VCSEL <NUM> and disabled VCSEL <NUM> in three alternative embodiments of the present invention are shown in <FIG>. These figures refer to <FIG>, and show an area <NUM> (marked by a dotted line) for enabled VCSEL <NUM> and an area <NUM> (marked by a dotted line) for disabled VCSEL <NUM>.

<FIG> are schematic sectional views of areas <NUM> and <NUM> of enabled and disabled VCSELs <NUM> and <NUM> of <FIG>, respectively, in accordance with an example.

In enabled VCSEL <NUM> an electrical contact between p-electrode <NUM> and p-DBR stack <NUM> is produced by etching a via in a location <NUM> in isolation layer <NUM> prior to deposition of the metal layer (M1) that serves as the p-electrode, thus enabling the flow of excitation current from the p-electrode to the p-DBR stack and further to quantum well structure <NUM>. In disabled VCSEL <NUM> no via is etched, as is shown by contiguous isolation layer <NUM> in a location <NUM>, thus preventing the flow of excitation current from p-electrode <NUM> into p-DBR stack <NUM> and further to quantum well structure <NUM>.

Disabling of VCSEL <NUM> is achieved in the fabrication process by a modification of the photomask responsible for delineating the etch of isolation layer <NUM> so as not to etch a via in location <NUM>.

In both enabled VCSEL <NUM> and disabled VCSEL <NUM> a via is etched in isolation layer <NUM> in locations <NUM> and <NUM>, respectively. A second isolation layer <NUM> is deposited over isolation layer <NUM>, and a via is etched in enabled VCSEL <NUM> in location <NUM>, whereas no via is etched in disabled VCSEL <NUM> in location <NUM>. p-electrode <NUM> is deposited over second isolation layer <NUM>, and the via etched in location <NUM> enables electrical contact between the p-electrode and p-DBR stack <NUM>, thus enabling the flow of excitation current from the p-electrode to the p-DBR stack and further to quantum well structure <NUM>. However, no electrical contact is established between p-electrode <NUM> and p-DBR stack <NUM> of disabled VCSEL <NUM> due to contiguous second isolation layer <NUM> in location <NUM>, thus preventing the flow of excitation current from the p-electrode into the p-DBR stack and further to quantum well structure <NUM>.

Disabling of VCSEL <NUM> is achieved in the fabrication process by a modification of the photomask responsible for delineating the etch of isolation layer <NUM> so as to prevent the etching of a via in location <NUM>.

<FIG> are schematic sectional views of areas <NUM> and <NUM> of enabled and disabled VCSELs <NUM> and <NUM> of <FIG>, respectively, in accordance with yet another embodiment of the present invention.

In both enabled VCSEL <NUM> and disabled VCSEL <NUM> an electrical contact between p-electrode <NUM> and p-DBR stack <NUM> is generated by etching a via in a location <NUM> in isolation layer <NUM>, similarly to enabled VCSEL of <FIG>. A second isolation layer <NUM> is deposited over p-electrode <NUM> (as opposed to depositing over isolation layer <NUM>, as in <FIG>). A via is etched in second isolation layer <NUM> in a location <NUM>, but no via is etched in a location <NUM>. A conducting layer <NUM> is deposited on second isolation layer <NUM> for feeding electrical current to the array of optoelectronic cells. Due to the via etched in location <NUM>, conducting layer <NUM> is in electrical contact with p-electrode <NUM>, and thereby with p-DBR stack <NUM>, enabling the flow of excitation current from the second metal layer to the p-DBR stack and further to quantum well structure <NUM>. However, due to contiguous second isolation layer <NUM> in location <NUM>, p-electrode <NUM> of disabled VCSEL <NUM> is isolated from conducting layer <NUM>, thus preventing feeding of electrical current to the p-electrode.

<FIG> are schematic sectional views of an enabled VCSEL <NUM> and a disabled VCSEL <NUM>, in accordance with an example. Enabled VCSEL <NUM> is substantially similar to enabled VCSEL <NUM> of <FIG>. Disabled VCSEL <NUM> differs from enabled VCSEL <NUM> in that confinement layer <NUM> is not etched in location <NUM>, preventing the growth of quantum well structure <NUM>.

Disabling of VCSEL <NUM> is achieved in the fabrication process by a modification of the photomask so as to prevent the etch of confinement layer <NUM> in location <NUM>.

Claim 1:
An optoelectronic device, comprising:
a semiconductor die (<NUM>); and
an array of optoelectronic cells (<NUM>, <NUM>), which are formed on the semiconductor die (<NUM>) and comprise:
first epitaxial layers (<NUM>) defining a lower distributed Bragg-reflector (DBR) stack;
second epitaxial layers (<NUM>) formed over the lower DBR stack, defining a quantum well structure;
third epitaxial layers (<NUM>), formed over the quantum well structure, defining an upper DBR stack; and
electrodes (<NUM>) formed over the upper DBR stack,
wherein the array comprises a first set of the optoelectronic cells (<NUM>) that are configured to emit laser radiation in response to an excitation current injected into the quantum well structure via the electrodes (<NUM>) and a second set of the optoelectronic cells (<NUM>) in which the electrodes (<NUM>) are configured so as not to inject an excitation current into the quantum well structure, so that the optoelectronic cells in the second set do not emit the laser radiation, characterized in that the second set of the optoelectronic cells (<NUM>) is interleaved on the semiconductor die (<NUM>) with the first set of the optoelectronic cells (<NUM>).