Patent Description:
The disclosure made herein is presented with respect to these and other considerations.

<CIT> discloses a two-wire power delivery system according to the preamble of claim <NUM>.

Technologies are described herein for a two-wire power delivery system that may be employed by a mobile device with a reversable cable. The described techniques allow for the two-wire power cable to be inserted in any orientation into the mobile device, without requiring a special keying or registration element, and without requiring any additional pins or wires. The mobile device includes a passive protection circuit that assists the two-wire power cable system in detecting the correct orientation for power delivery.

It should be appreciated that the above-described subject matter may also be implemented as part of an apparatus, system, or as part of an article of manufacture. These and various other features will be apparent from a reading of the following Detailed Description and a review of the associated drawings.

This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended that this Summary be used to limit the scope of the claimed subject matter.

In the following detailed description, reference is made to the accompanied drawings, which form a part hereof, and which is shown by way of illustration, specific example configurations of which the concepts can be practiced. These configurations are described in sufficient detail to enable those skilled in the art to practice the techniques disclosed herein, and it is to be understood that other configurations can be utilized, and other changes may be made, without departing from the spirit or scope of the presented concepts. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the presented concepts is defined only by the appended claims.

Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of "a," "an," and "the" includes plural reference, the meaning of "in" includes "in" and "on. " The term "connected" means a direct electrical connection between the items connected, without any intermediate devices. The term "coupled" means a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices and/or components. The terms "circuit" and "component" means either a single component or a multiplicity of components, either active and/or passive, that are coupled to provide a desired function. The term "signal" means at least a power, current, voltage, or data signal. The terms, "gate," "drain," and "source," can also mean a "base," "collector" and "emitter," and/or equivalent parts.

Mobile devices, such as cell phones, handheld gaming devices, smart watches, headphones and headsets often include rechargeable batteries. Cables and connectors for these mobile devices often may be used for many purposes, for example: to recharge the batteries, to allow device use when the battery charge is too low, and/or to transfer data into or out of the mobile device. Consequently, many mobile devices use power connector and cabling interfaces that are manufactured according to industry standards.

The Universal Serial Bus (USB) is an industry standard that establishes specifications for cables and connectors and the various protocols for connecting power and data. The USB standard has changed over time, and there now exists multiple versions of the standard (USB <NUM>, USB <NUM>, USB <NUM>, USB <NUM>, etc.). The evolution of the standard has led to increased data transmission speeds, as well as support for a variety of different connector styles.

Although there are now many different styles of connectors that are now supported in the USB standard, the connectors are still fairly large size since they support both power and data communications. Moreover, data communication cable designs tend to require certain considerations to minimize signal crosstalk and radio frequency (RF) interference, which results in special designs that may be bulky. Consequently, the design of power cables using these standardized cables and connectors may not be ideal in all applications.

Specially designed power cables can be used to power mobile devices. The design of such a power cable may require certain consideration to ensure the power cable is inserted with a correct orientation, specifically to prevent damage to the electronics and/or battery in the mobile device. A keying element may be employed to ensure proper orientation of the cable when connected to the mobile device. The mobile device may thus include a female connector that is specially designed to engage with a male cable, where the male to female connection only accepts a single orientation for proper engagement. For example, in a mini-USB style cable the keying element is found in the shape of an outer shield ring of the connector itself, where the outer ring has a trapezoidal shape (e.g., a D style connector) that can only engage in one orientation. In other examples, the mobile device may have a shaped detent that is designed to accept cable insertion when a matching protrusion on the cable aligns with the detent, and blocks cable insertion when the protrusion is in a reversed orientation or misaligned.

Some power cables can be designed to reversable, where no keying element is required to ensure proper engagement and where the cable can be accepted by the mobile device in any orientation. A power cable with a reversable design may require additional or redundant wires and pins ensure the positive and negative power connections engage properly irrespective of the cable orientation. Moreover, reversable power cables may require the power connection points to be offset or an identification pin may be required to allow the mobile device to detect the orientation of the cable. The presently disclosure contemplates these factors and other consideration in reversable cable and power connector design for portable devices.

A two-wire power delivery system is described herein that may be employed by a mobile device with a reversable cable. The described techniques allow for the power cable in a mobile device to be inserted in any orientation without requiring a special keying or registration element, and without requiring any additional pins or wires. Also, the presently described techniques allow for passive detection of orientation when the battery in the mobile device is discharged. Thus, the described two-wire power delivery system is efficient and economical, and has added features benefits that will be apparent from the below detailed description.

<FIG> shows a schematic diagram of an example power delivery system <NUM> for a mobile device with passive orientation detection. Power delivery system <NUM> includes a mobile device <NUM>, a switch circuit <NUM>, and a control circuit <NUM>.

Mobile device <NUM> further includes a battery <NUM>, a passive protection circuit <NUM>, and a system circuit <NUM>. Battery <NUM> may be any type of rechargeable battery (e.g. Lithium Ion polymer, Nickel-Metal Hydride, Etc. ), that may be utilized to power various circuits in the mobile device, either through direct or indirect connections. For example, system circuit <NUM> of mobile device <NUM> may be powered by battery <NUM>. The battery <NUM> my further include one or more individual batteries or cells, which may be arranged in either series or parallel configurations, which may collectively referred to as battery <NUM>.

The passive protection circuit <NUM> for mobile device <NUM> serves multiple functions. In one example, circuit <NUM> prevents an incorrectly connected battery charger (e.g., one where the power and ground pins are reversed) from damaging the circuits and/or the battery in the mobile device <NUM>. In another example, circuit <NUM> is specifically designed to collaboratively operate with the charger (e.g., the cable and connector that delivery power to the mobile device pins) to allow detection of the reverse polarity as will be understood by the other details found herein. The design of circuit <NUM> is passive, meaning that circuit <NUM> will continue to operate correctly even when the battery <NUM> is discharged (either partially or completely). Example passive protection circuits will be described with reference to <FIG> and <FIG>.

The passive protection circuit <NUM> of mobile device <NUM> is coupled to the switch circuit <NUM> via two power pins, a first power pin (PIN1) and a second power pin (PIN2). Switch circuit <NUM> is designed to selectively deliver power to the two power pins (PIN1, PIN2) of the mobile device <NUM> from an externally supplied power source, which may be described as a high-side supply (e.g., VH) and a low-side supply (e.g., VL). In some examples, the high-side supply may correspond to a positive supply (e.g., VH = +12V, +9V, +6V, +5V, or +3V, etc.) and a the low-side supply may correspond to a ground return (e.g., VL = 0V). In other examples, the low-side supply may correspond to another external supply such as a negative power supply (e.g., VL = -12V, -9V, -6V, -5V, or -3V, etc.). The examples provided herein are merely provided as general examples, and all varieties of power supplies are contemplated.

The switch circuit <NUM> is designed to selectively deliver power to the mobile device <NUM> in response to control signals (e.g., CTL), which are provided by the control circuit <NUM>. The control signals may correspond to any required number of control signals. Thus, switch circuit <NUM> is designed to selectively enable and disable power to the two pins such that the orientation of the two-wire connection from the first power pin (PIN1) and the second power pin (PIN2) may be tested for proper orientation, safety, and power delivery. In some examples, additional logic may be employed inside the switch circuit <NUM> to reduce the number of required control signals from the control circuit. Example switch circuits are described with reference to <FIG> and <FIG>.

Control circuit <NUM> includes several internal functions, which can broadly be considered as polarity detection <NUM>, short-circuit protection <NUM>, and switch control <NUM>. These functions may be provided by individual circuits, analog and/or digital, or combined into operation of a single circuit. In some examples, the functions of the control circuit <NUM> may be provided by a programmable logic device (PLD), a controller or other similar designs, which may be adapted (e.g., programmed) to perform the functions described herein. Example state machines that may be employed for at least a portion of the control circuit are described with reference to <FIG> and <FIG>.

Mobile device <NUM> may be any variety of portable electronic device that may benefit from a two-wire power deliver system, including but not limited to a head mounted display, a gaming device, a virtual reality headset, etc..

<FIG> shows a detailed schematic diagram of another example power delivery system <NUM> for a mobile device with passive orientation detection. Power delivery system <NUM> includes a mobile device <NUM>, a switch circuit <NUM>, and a control circuit <NUM>. System <NUM> is substantially similar to other example systems described herein, with the additional of an example mobile device <NUM> with a detailed example of passive protection circuit <NUM>.

Battery <NUM> includes a positive terminal (V+) that corresponds to the power VBAT supply for the mobile device <NUM>, and a negative terminal (V-) that corresponds to the ground (GND) of the mobile device <NUM>. The system circuit <NUM>, is illustrated as being coupled in parallel with battery <NUM>, but additional circuitry may be utilized to provide the power to the various system circuits <NUM> of mobile device <NUM>. The ground of the mobile device (GND) is also coupled to the second power pin PIN2, which serves as the ground return for any externally supplied power.

The example passive protection circuit <NUM> of <FIG> includes a first resistor R21, a second resistor R22, a third resistor R23, a transistor circuit <NUM>, and a diode circuit Z21. The first resistor R21 is coupled between the first power pin PIN1 and the second power pin PIN2, and is shown with a value of 100KQ. The second resistor R22 is coupled between the second power pin PIN2 and an intermediate node <NUM>, and is shown with a value of 10KQ. The third resistor R23 is coupled between the second power pin PIN2 and the positive terminal (V+) of the battery <NUM>, and is shown with a value of 100KQ. Transistor circuit <NUM> includes first port coupled to the first power pin PIN1, a second port coupled to the positive terminal (V+) of the battery <NUM>, and a third port coupled to the intermediate node <NUM>. The diode circuit Z21 is coupled between the positive terminal (V+) of the battery and the intermediate node <NUM>, which is configured to operate as a voltage clamp on the VGS voltage of the transistor circuit <NUM>. The precise resistor values may vary, and these values are merely provided as examples.

Transistor circuit <NUM> includes a p-type transistor (e.g., a p-FET), which is configured to conditionally activate based on the polarity and voltage conditions applied to the first power pin PIN1 and the second power pin PIN2. A first source or drain terminal of the p-type transistor is coupled to the first power pin PIN1, while a second source or drain terminal is coupled to the positive terminal (V+) of the battery, and a gate terminal is coupled to the intermediate node <NUM>. The transistors described herein may be any appropriate device such as a metal oxide semiconductor device (MOS), a junction field effect transistor (JFET) device, or some other field effect transistor (FET) device. The transistor circuits described herein may further include other components that may be required to ensure proper operation of the functions provided by the specific transistors.

The operation of the passive protection circuit <NUM> will be described with further reference to the control circuit <NUM> and the switch circuit <NUM>, which collaboratively configure the first and second power pins PIN1, PIN2. As follows:.

In a first operating phase: IDLE, the switch control circuit <NUM> configures the switch circuit <NUM> to operate both the first and second power pins PIN1, PIN2 in a "no connect" or "open circuit" configuration where they are both decoupled from power.

In a second operating phase: TESTA, the switch control circuit <NUM> configures the switch circuit <NUM> to couple PIN1 to the high-side supply (VH) and couple PIN2 through a pulldown resistor to the low-side supply (VL) or ground return (GND). This configuration is in a test condition to determine if the normal orientation is appropriate.

In a third operating phase: TESTB, the switch control circuit <NUM> may configure the switch circuit <NUM> to couple PIN1 to the high-side supply (VH) and couple PIN2 through a pulldown resistor to the low-side supply (VL) or ground return (GND). This configuration is in a test condition to determine if the reverse orientation is appropriate.

In a fourth operating phase: CONNECTA, the switch control circuit <NUM> may configure the switch circuit <NUM> to couple PIN1 to the high-side supply (VH) and couple PIN2 to the low-side supply (VL) or ground return (GND). This configuration is a normal orientation connection.

In a fifth operating phase: CONNECTB, the switch control circuit <NUM> may configure the switch circuit <NUM> to couple PIN2 to the high-side supply (VH) and couple PIN1 to the low-side supply (VL) or ground return (GND). This configuration is a reverse orientation connection.

In the first operating phase, IDLE, the power pins PIN1 and PIN2 are in an open circuit condition and no current will flow through the first and second resistors R21, R22 of the passive protection circuit <NUM>. Therefore, the intermediate node <NUM> will have the same potential as the negative terminal (V-) of the battery <NUM> (e.g., GND), and the transistor circuit <NUM> will be inactive since there is no forward bias applied between the source and gate terminals. Since transistor circuit <NUM> is inactive, there is no conduction path from the positive battery terminal (V+) to PIN1, and thus the impedance of the passive protection circuit (between PIN1 and PIN2) will correspond to an open circuit (e.g., a high impedance).

In the second and fourth operating phases, TESTA and CONNECTA, PIN1 is configured as a positive power supply (VH) and PIN2 is configured as a conduction path to the negative power supply (VH) or ground return (GND). Assuming there are no short circuit conditions, the transistor circuit <NUM> is forward biased or activated, and power from the first power supply pin PIN1 will be coupled to the positive terminal (V+) of the battery <NUM>. In this operating phase, the impedance of the passive protection circuit (between PIN1 and PIN2) will correspond to the parallel combination of resistors R21 and R23, with an effective resistance that is determined by their values (e.g., 100KΩ / <NUM> or 50KQ in this example).

In the third and fifth operating phases, TESTB and CONNECTB, PIN2 is configured as a positive power supply (VH) and PIN1 is configured as a conduction path to the negative (VL) or return (e.g., GND) of the power supply. Assuming no short circuit conditions, the transistor circuit <NUM> is reverse biased or deactivated and thus blocks conduction between PIN1 and the positive terminal (V+) of the battery <NUM>. Since conduction is blocked, power will flow through resistor R21 but not the other resistors R22 and R23, and thus the impedance of the passive protection circuit (between PIN1 and PIN2) will correspond to the R21 (e.g., 100KQ in this example).

<FIG> shows a detailed schematic diagram of yet another example power delivery system <NUM> for a mobile device with passive orientation detection. Power delivery system <NUM> includes a switch circuit <NUM>, and a control circuit <NUM>. System <NUM> is substantially similar to other example systems described herein, with the addition of an example switch circuit <NUM>. The mobile device of <FIG> with passive circuit protection <NUM> is compatible with the switch circuit of <FIG>, as will become apparent from the below discussion.

The example switch circuit <NUM> of <FIG> includes a first resistor R31, a second resistor R32, a first transistor circuit <NUM>, a second transistor circuit <NUM>, a third transistor circuit <NUM>, a fourth transistor circuit <NUM>, a fifth transistor circuit <NUM>, and a sixth transistor circuit <NUM>. The first resistor R31 is coupled between the first power pin PIN1 and a first intermediate node <NUM>, and is shown with a value of 100KQ. The second resistor R32 is coupled between the second power pin PIN2 and a second intermediate node <NUM>, and is shown with a value of 100KΩ. The first transistor circuit <NUM> includes first port coupled to the high-side supply (VH), a second port coupled to the first power pin PIN1, and a third port coupled to a PIN1 high enable control <NUM> (PIN1_H_EN). The second transistor circuit <NUM> includes first port coupled to the first power pin PIN1, a second port coupled to the low-side supply (VL), and a third port coupled to a PIN1 ground enable control <NUM> (e.g., PIN1_GND_EN). The third transistor circuit <NUM> includes a first port coupled to the first intermediate node <NUM>, a second port coupled to the low-side supply (VL), and a third port coupled to a first pulldown control <NUM> (e.g., PIN1_PD_EN). The fourth transistor circuit <NUM> includes first port coupled to the high-side supply (VH), a second port coupled to the second power pin PIN2, and a third port coupled to a PIN2 high enable control <NUM> (PIN2_H_EN). The fifth transistor circuit <NUM> includes a first port coupled to the second power pin PIN2, a second port coupled to the low-side supply (VL), and a third port coupled to a PIN2 ground enable control <NUM> (e.g., PIN2_GND_EN). The sixth transistor circuit <NUM> includes a first port coupled to the second intermediate node <NUM>, a second port coupled to the low-side supply (VL), and a third port coupled to a second pulldown control <NUM> (e.g., PIN2_PD_EN). Transistor circuits <NUM> and <NUM> are illustrated as including p-type transistors, while transistor circuits <NUM>, <NUM>, <NUM>, and <NUM> are illustrated as including n-type transistors; but other transistor arrangements are contemplated. The precise resistor values may vary, and these values are merely provided as examples.

The operation of switch circuit <NUM> will be described with reference to the operating phases and Table <NUM> previously described above for <FIG>.

In the first operating phase, IDLE, both power pins (PIN1, PIN2) are isolated from the high-side supply (e.g., VH) and the low-side supply (e.g., VL). Based on this operating condition, transistor circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> are all disabled so they present a high impedance. The control signals for the p-type transistors illustrated herein will all correspond to high signals (e.g., VH) since the p-type transistors are activated with a low signal (e.g., VL), while the control signals for the n-type transistors will all correspond to low signals (e.g., VL) since the n-type transistors are activated with a high signal (e.g., VH). Thus, for these transistor circuits to be fully disabled:.

In the second operating phase, TESTA, the first power pin (PIN1) is coupled to the high-side supply (e.g., VH) and the second power pin (PIN2) is coupled to the low-side supply (e.g., VL) though the pulldown resistor (R32). Based on this operating condition, transistor circuits <NUM> and <NUM> are active, and the remaining transistor circuits <NUM>, <NUM>, <NUM>, and <NUM> are disabled so they present a high impedance. Thus, for these transistor circuits to be configured properly:.

In the third operating phase, TESTB, the second power pin (PIN2) is coupled to the high-side supply (e.g., VH) and the first power pin (PIN1) is coupled to the low-side supply (e.g., VL) though the pulldown resistor (R31). Based on this operating condition, transistor circuits <NUM> and <NUM> are active, and the remaining transistor circuits <NUM>, <NUM>, <NUM>, and <NUM> are disabled so they present a high impedance. Thus, for these transistor circuits to be configured properly:.

In the fourth operating phase, CONNECTA, the first power pin (PIN1) is coupled to the high-side supply (e.g., VH) and the second power pin (PIN2) is coupled to the low-side supply (e.g., VL). Based on this operating condition, transistor circuits <NUM> and <NUM> are active, and the remaining transistor circuits <NUM>, <NUM>, <NUM>, and <NUM> are disabled so they present a high impedance. Thus, for these transistor circuits to be configured properly:.

In the fifth operating phase, CONNECTB, the first power pin (PIN1) is coupled to the low-side supply (e.g., VL) and the second power pin (PIN2) is coupled to the hide-side supply (e.g., VH). Based on this operating condition, transistor circuits <NUM> and <NUM> are active, and the remaining transistor circuits <NUM>, <NUM>, <NUM>, and <NUM> are disabled so they present a high impedance. Thus, for these transistor circuits to be configured properly:.

The second operating phase is referred to as TESTA. In this operating phase the conditions are tested to verify the connection and orientation of the connection. In particular, PIN2_DETECT is evaluated to determine what voltage is present when PIN1 is coupled to VH and PIN2 is coupled to VL (or GND) via pulldown resistor R32. There are multiple possibilities to consider for TESTA: an open circuit where the passive protection circuit is disconnected, a closed circuit where the passive protection circuit is connected and in the correct orientation, a closed circuit where the passive protection circuit is connected and in the incorrect orientation (and should be reversed), or a closed circuit where the passive protection circuit is connected and under a short circuit condition.

When the cable is not connected to a mobile device, or some other open circuit condition exists, the voltage at PIN2 will collapse to GND (or VL) since the pulldown resistor R32 is active on PIN2. Thus, if TESTA yields a detection voltage of GND (VL), then there is no load connected, and we can proceed back to the IDLE or NC condition.

When the cable is connected and there is a short circuit between PIN1 and PIN2, then the voltage at PIN2 will correspond to a high voltage near VH. Thus, if TEST A yields a detection voltage at PIN <NUM> of VH, there is likely a short circuit. However, the other conditions must be tested to verify a short circuit.

When the cable is connected and the orientation is correct, the passive protection circuit <NUM> will allow conduction from PIN1 to both resistors R21 and resistor R23. , which will result in a combined resistance of R21 and R23 in parallel between PIN1 and PIN2. Given they are of equal values (in some examples), their overall combined resistance is given by R21/<NUM>. Combining the resistance of R21/<NUM> and R32 from the pulldown resistor yields a detection voltage of DETECT ≈ (VH - VL) *R32/(R32 + R21/<NUM>). Assuming R32 has the same resistance value of R21, and VL = 0V, the detection voltage at PIN2 will correspond to approximately <NUM>/<NUM> of the supply voltage (e.g., DETECT ≈ <NUM>*VH / <NUM> when VL= 0V).

When the cable is connected but the orientation is incorrect, the passive protection circuit <NUM> will block conduction between PIN1 and resistor R23, and the only conduction path provided from PIN1 to PIN2 will be via R21. Combining the resistance of R21 and R32 from the pulldown resistor yields a detection voltage of DETECT ≈ (VH - VL)*R32/(R32 + R21). Assuming R21 and R32 have the same resistance values, and VL = 0V, the voltage at PIN2 will correspond to approximately half of the supply voltage (e.g., DETECT ≈ VH / <NUM> when VL= 0V).

The third operating phase is referred to as TESTB. In this operating phase the conditions are tested to verify the orientation of the connection is reversed. In particular, PIN1_DETECT is evaluated to determine what voltage is present when PIN2 is coupled to VH and PIN1 is coupled to VL (or GND) via pulldown resistor R31. There are multiple possibilities to consider for TESTB: an open circuit where the passive protection circuit is disconnected, a closed circuit where the passive protection circuit is connected and in the correct orientation, a closed circuit where the passive protection circuit is connected and in the incorrect orientation, or a closed circuit where the passive protection circuit is connected and under a short circuit condition. The analysis for TEST B is substantially similar to TEST A.

When the cable is connected and the reverse orientation is correct, the passive protection circuit <NUM> will allow conduction from PIN2 to both resistors R21 and resistor R23, which will result the combined resistance of R21 and R23 in parallel between PIN1 and PIN2. Given they are of equal values, their overall resistance is given by R21/<NUM>. Combining the resistance of R21/<NUM> and R32 from the pulldown resistor yields a detection voltage of DETECT ≈ (VH - VL) *R31/(R31 + R21/<NUM>). Assuming R31 has the same resistance value of R21, and VL = 0V, the detection voltage at PIN2 will correspond to approximately <NUM>/<NUM> of the supply voltage (e.g., DETECT ≈ <NUM>*VH / <NUM> when VL = 0V).

When the cable is connected but the orientation is incorrect, the passive protection circuit <NUM> will block conduction between PIN1 and resistor R23, and the only conduction path provided from PIN1 to PIN2 will be via R21. Combining the resistance of R21 and R31 from the pulldown resistor yields a detection voltage of DETECT ≈ (VH - VL) *R31/(R31 + R21). Assuming R21 and R31 have the same resistance values, and VL = 0V, the voltage at PIN2 will correspond to approximately half of the supply voltage (e.g., DETECT ≈ VH / <NUM> when VL = 0V).

Transistor circuits <NUM> and <NUM> each are illustrated to include a p-type transistor (e.g., a p-FET); while transistor circuits <NUM>, <NUM>, <NUM> and <NUM> each are illustrated to include a n-type transistor (e.g., an n-FET); where each transistor circuit is configured to conditionally activate based on the polarity and voltage conditions applied at their respective source and gate terminals. For each transistor circuit, a first source or drain terminal of the p-type transistor is coupled to the first port in the respective transistor circuit, while the second source or drain terminal is coupled to the second port, and the gate terminal is coupled to the third port. For example, a first source or drain terminal of the p-type transistor in the transistor circuit <NUM> may be coupled to the high-side supply (VH), while a second source or drain terminal is coupled to the first power pin PIN1, and a gate terminal may be coupled to the control signal at node <NUM>. The control signals for the p-type transistor circuits are active on a low signal (VL), while the control signals for the n-type transistor circuits are active on a high signal (VH). However, the logic level for activation of the various circuits could be changed by simple logic inverters if needed.

The transistors described herein may be any appropriate device such as a metal oxide semiconductor device (MOS), a junction field effect transistor (JFET) device, or some other field effect transistor (FET) device. The transistor circuits described herein may further include other components that may be required to ensure proper operation of the functions provided by the specific transistor circuits. Additionally, although described as p-type transistors and n-type transistors, other combinations of n-type and p-type transistors may be adapted for use in the present system.

<FIG> shows a detailed schematic diagram of still another example power delivery system <NUM> for a mobile device with passive orientation detection. Power delivery system <NUM> includes a mobile device <NUM>, a switch circuit <NUM>, and a control circuit <NUM>. System <NUM> is substantially similar to other example systems described herein, with the additional of an example mobile device <NUM> with a detailed example of passive protection circuit <NUM>. The passive protection circuit of <FIG> is similar to that shown in <FIG>, but where the signals are blocked using n-type transistor circuits instead of p-type.

Battery <NUM> again includes a positive terminal (V+) that corresponds to the power VBAT supply for the mobile device <NUM>, and a negative terminal (V-) that corresponds to the ground (GND) of the mobile device <NUM>; with the system circuit <NUM> illustrated as being coupled in parallel with battery <NUM>. However, the ground of the mobile device (GND) is not coupled directly to the second power pin PIN2 as was described for <FIG>. Instead, the positive battery terminal (V+) of the mobile device (VBAT) is coupled to the first power pin PIN1, and the ground of the mobile device is isolated from the second power pin PIN2 as will be described below.

The example passive protection circuit <NUM> of <FIG> includes a first resistor R41, a second resistor R42, a third resistor R43, a transistor circuit <NUM>, and a diode circuit Z41. The first resistor R41 is coupled between the first power pin PIN1 and the second power pin PIN2, and is shown with a value of 100KQ. The second resistor R42 is coupled between the first power pin PIN1 and an intermediate node <NUM>, and is shown with a value of 10KQ. The third resistor R43 is coupled between the first power pin PIN1 and the negative terminal (V-) of the battery <NUM>, and is shown with a value of 100KQ. Transistor circuit <NUM> includes first port coupled to the first power pin PIN1, a second port coupled to the positive terminal (V+) of the battery <NUM>, and a third port coupled to the intermediate node <NUM>. The diode circuit Z41 is coupled between the positive terminal (V+) of the battery and the intermediate node <NUM>, which is configured to operate as a voltage clamp on the VGS voltage of the transistor circuit <NUM>. The precise resistor values may vary, and these values are merely provided as examples.

Transistor circuit <NUM> includes an n-type transistor (e.g., a n-FET), which is configured to conditionally activate based on the polarity and voltage conditions applied to the first power pin PIN1 and the second power pin PIN2. A first source or drain terminal of the n-type transistor is coupled to the second power pin PIN2, while a second source or drain terminal is coupled to the negative terminal (V-) of the battery, and a gate terminal is coupled to the intermediate node <NUM>. The transistors described herein may be any appropriate device such as a metal oxide semiconductor device (MOS), a junction field effect transistor (JFET) device, or some other field effect transistor (FET) device. The transistor circuits described herein may further include other components that may be required to ensure proper operation of the functions provided by the specific transistors.

The operation of the passive protection circuit <NUM> in <FIG> will again be described with further reference to the control circuit <NUM> and the switch circuit <NUM>, which collaboratively configure the first and second power pins PIN1, PIN2. As follows:.

Table <NUM> is similar to Table <NUM> described previously, except that the detection is for the TESTA and TESTB conditions are implemented with a pullup circuit instead of a pulldown circuit.

In the first operating phase: IDLE, the switch control circuit <NUM> configures the switch circuit <NUM> to operate both the first and second power pins PIN1, PIN2 in a "no connect" or "open circuit" configuration where they are both decoupled from power.

In a second operating phase: TEST1, the switch control circuit <NUM> configures the switch circuit <NUM> to couple PIN2 to the low-side supply (VL) and couple PIN1 through a pullup resistor to the high-side supply (VH). This configuration is in a test condition to determine if the normal orientation is appropriate.

In a third operating phase: TEST2, the switch control circuit <NUM> may configure the switch circuit <NUM> to couple PIN1 to the low-side supply (VL) and couple PIN2 through a pullup resistor to the high-side supply (VH). This configuration is in a test condition to determine if the reverse orientation is appropriate.

In a fourth operating phase: CONNECT1, the switch control circuit <NUM> may configure the switch circuit <NUM> to couple PIN1 to the high-side supply (VH) and couple PIN2 to the low-side supply (VL) or ground return (GND). This configuration is a normal orientation connection.

In a fifth operating phase: CONNECT2, the switch control circuit <NUM> may configure the switch circuit <NUM> to couple PIN2 to the high-side supply (VH) and couple PIN1 to the low-side supply (VL) or ground return (GND). This configuration is a reverse orientation connection.

In the first operating phase, IDLE, the power pins PIN1 and PIN2 are in an open circuit condition and no current will flow through the first and second resistors R41, R42 of the passive protection circuit <NUM>. Therefore, the intermediate node <NUM> will have the same potential as the positive terminal (V+) of the battery <NUM> (e.g., VBAT), and the transistor circuit <NUM> will be inactive since there is no forward bias applied between the source and gate terminals. Since transistor circuit <NUM> is inactive, there is no conduction path from the negative battery terminal (V-) to PIN2, and thus the impedance of the passive protection circuit (between PIN1 and PIN2) will correspond to an open circuit (e.g., a high impedance).

In the second and fourth operating phases, TEST1 and CONNECT1, PIN2 is configured as a negative power supply (VL) and PIN1 is configured as a conduction path to the positive power supply (VH). Assuming there are no short circuit conditions, the transistor circuit <NUM> is forward biased or activated, and power from the second power supply pin PIN2 will be coupled to the negative terminal (V-) of the battery <NUM>. In this operating phase, the impedance of the passive protection circuit (between PIN1 and PIN2) will correspond to the parallel combination of resistors R41 and R43, with an effective resistance that is determined by their values (e.g., 100KΩ / <NUM> or 50KΩ in this example).

In the third and fifth operating phases, TEST2 and CONNECT <NUM>, PIN1 is configured as a negative power supply (VL) and PIN2 is configured as a conduction path to the positive (VH) power supply. Assuming no short circuit conditions, the transistor circuit <NUM> is reverse biased or deactivated and thus blocks conduction between PIN2 and the negative terminal (V-) of the battery <NUM>. Since conduction is blocked, power will flow through resistor R41 but not the other resistors R42 and R43, and thus the impedance of the passive protection circuit (between PIN1 and PIN2) will correspond to R41 (e.g., 100KQ in this example).

<FIG> shows a detailed schematic diagram of yet still another example power delivery system <NUM> for a mobile device with passive orientation detection. Power delivery system <NUM> includes a switch circuit <NUM>, and a control circuit <NUM>. System <NUM> is substantially similar to other example systems described herein, with the addition of an example switch circuit <NUM>. The mobile device of <FIG> with passive circuit protection <NUM> is compatible with the switch circuit of <FIG>, as will become apparent from the below discussion.

The example switch circuit <NUM> of <FIG> includes a first resistor R51, a second resistor R52, a first transistor circuit <NUM>, a second transistor circuit <NUM>, a third transistor circuit <NUM>, a fourth transistor circuit <NUM>, a fifth transistor circuit <NUM>, and a sixth transistor circuit <NUM>. The first resistor R51 is coupled between the high-side supply (VH) and a first intermediate node <NUM>, and is shown with a value of 100KΩ. The second resistor R52 is coupled between the high-side supply (VH) and a second intermediate node <NUM>, and is shown with a value of 100KΩ. The first transistor circuit <NUM> includes first port coupled to the high-side supply (VH), a second port coupled to the first power pin PIN1, and a third port coupled to a PIN1 high enable control <NUM> (PIN1_H_EN). The second transistor circuit <NUM> includes first port coupled to the first power pin PIN1, a second port coupled to the low-side supply (VL), and a third port coupled to a PIN ground enable control <NUM> (e.g., PIN1_GND_EN). The third transistor circuit <NUM> includes a first port coupled to the first intermediate node <NUM>, a second port coupled to the first power pin (PIN1), and a third port coupled to a first pullup control <NUM> (e.g., PIN1_PU_EN). The fourth transistor circuit <NUM> includes first port coupled to the high-side supply (VH), a second port coupled to the second power pin PIN2, and a third port coupled to a PIN2 high enable control <NUM> (PIN2_H_EN). The fifth transistor circuit <NUM> includes first port coupled to the second power pin PIN2, a second port coupled to the low-side supply (VL), and a third port coupled to a PIN2 ground enable control <NUM> (e.g., PIN2_GND_EN). The sixth transistor circuit <NUM> includes a first port coupled to the second intermediate node <NUM>, a second port coupled to the second power pin (PIN2), and a third port coupled to a second pullup control <NUM> (e.g., PIN2_PU_EN). Transistor circuits <NUM>, <NUM>, <NUM>, and <NUM> are illustrated as including p-type transistors, while transistor circuits <NUM> and <NUM> are illustrated as including n-type transistors; but other transistor arrangements are contemplated. The precise resistor values may vary, and these values are merely provided as examples.

In the second operating phase, TESTA, the first power pin (PIN1) is coupled to the high-side supply (e.g., VH) through the pullup resistor R51, and the second power pin (PIN2) is coupled to the low-side supply (e.g., VL). Based on this operating condition, transistor circuits <NUM> and <NUM> are active, and the remaining transistor circuits <NUM>, <NUM>, <NUM>, and <NUM> are disabled so they present a high impedance. Thus, for these transistor circuits to be configured properly:.

In the third operating phase, TESTB, the second power pin (PIN2) is coupled to the high-side supply (e.g., VH) through the pullup resistor (R52) )and the first power pin (PIN1) is coupled to the low-side supply (e.g., VL). Based on this operating condition, transistor circuits <NUM> and <NUM> are active, and the remaining transistor circuits <NUM>, <NUM>, <NUM>, and <NUM> are disabled so they present a high impedance. Thus, for these transistor circuits to be configured properly:.

The second operating phase is referred to as TESTA. In this operating phase the conditions are tested to verify the connection and orientation of the connection. In particular, PIN1 DETECT is evaluated to determine what voltage is present when PIN1 when PIN2 is coupled to VL (or GND) and PIN1 is coupled to VH via pullup resistor R51. There are multiple possibilities to consider for TESTA: an open circuit where the passive protection circuit is disconnected, a closed circuit where the passive protection circuit is connected and in the correct orientation, a closed circuit where the passive protection circuit is connected and in the incorrect orientation (and should be reversed), or a closed circuit where the passive protection circuit is connected and under a short circuit condition.

When the cable is not connected to a mobile device, or some other open circuit condition exists, the voltage at PIN1 will be drawn up to the high-side supply since the pullup resistor R51 is active on PIN1. Thus, if TESTA yields a detection voltage of VH, then there is no load connected, and we can proceed back to the IDLE or NC condition.

When the cable is connected and there is a short circuit between PIN1 and PIN2, then the voltage at PIN1 will correspond to a low voltage near VL. Thus, if TEST A yields a detection voltage at PIN <NUM> of VL, there is likely a short circuit. However, the other conditions must be tested to verify a short circuit.

When the cable is connected and the orientation is correct, the passive protection circuit <NUM> will allow conduction from PIN2 to both resistors R41 and resistor R43. , which will result in a combined resistance of R41 and R43 in parallel between PIN1 and PIN2. Given they are of equal values (in some examples), their overall combined resistance is given by R41/<NUM> or <NUM>*R41. Combining the resistance of <NUM>*R41 and R51 from the pullup resistor yields a detection voltage of DETECT ≈ (VH - VL) *<NUM>*R41/(R51 + <NUM>*R41). Assuming R41 has the same resistance value of R51, and VL = 0V, the detection voltage at PIN1 will correspond to approximately <NUM>/<NUM> of the supply voltage (e.g., DETECT ≈ VH / <NUM> when VL = 0V).

When the cable is connected but the orientation is incorrect, the passive protection circuit <NUM> will block conduction between PIN2 and resistor R43, and the only conduction path provided from PIN1 to PIN2 will be via R41. Combining the resistance of R41 and R51 from the pullup resistor yields a detection voltage of DETECT ≈ (VH - VL)*R41/(R41 + R51). Assuming R41 and R51 have the same resistance values, and VL = 0V, the voltage at PIN1 will correspond to approximately half of the supply voltage (e.g., DETECT ≈ VH / <NUM> when VL = 0V).

The third operating phase is referred to as TESTB. In this operating phase the conditions are tested to verify the orientation of the connection is reversed. In particular, PIN2_DETECT is evaluated to determine what voltage is present on PIN2 when PIN1 is coupled to VL (or GND) and PIN2 is coupled to VH via pullup resistor R52. There are multiple possibilities to consider for TESTB: an open circuit where the passive protection circuit is disconnected, a closed circuit where the passive protection circuit is connected and in the correct orientation, a closed circuit where the passive protection circuit is connected and in the incorrect orientation, or a closed circuit where the passive protection circuit is connected and under a short circuit condition. The analysis for TEST B is substantially similar to TEST A.

When the cable is connected and the reverse orientation is correct, the passive protection circuit <NUM> will allow conduction from PIN2 to both resistors R41 and resistor R43, which will result the combined resistance of R41 and R43 in parallel between PIN1 and PIN2. Given they are of equal values, their overall resistance is given by R41/<NUM> or <NUM>*R41. Combining the resistance of <NUM>*R41 and R52 from the pullup resistor yields a detection voltage of DETECT ≈ (VH - VL) *<NUM>*R41/(R52 + <NUM>*R41). Assuming R41 has the same resistance value of R52, and VL = 0V, the detection voltage at PIN2 will correspond to approximately <NUM>/<NUM> of the supply voltage (e.g., DETECT ≈ VH / <NUM> when VL = 0V).

When the cable is connected but the orientation is incorrect, the passive protection circuit <NUM> will block conduction between PIN2 and resistor R43, and the only conduction path provided from PIN1 to PIN2 will be via R21. Combining the resistance of R21 and R31 from the pullup resistor yields a detection voltage of DETECT ≈ (VH - VL) *R41/(R41 + R51). Assuming R41 and R51 have the same resistance values, and VL = 0V, the voltage at PIN2 will correspond to approximately half of the supply voltage (e.g., DETECT ≈ VH / <NUM> when VL = 0V).

Transistor circuits <NUM>, <NUM>, <NUM> and <NUM> each are illustrated to include a p-type transistor (e.g., a p-FET); while transistor circuits <NUM> and <NUM> each are illustrated to include a n-type transistor (e.g., an n-FET); where each transistor circuit is configured to conditionally activate based on the polarity and voltage conditions applied at their respective source and gate terminals. For each transistor circuit, a first source or drain terminal of the p-type transistor is coupled to the first port in the respective transistor circuit, while the second source or drain terminal is coupled to the second port, and the gate terminal is coupled to the third port. The control signals for the p-type transistor circuits are active on a low signal (VL), while the control signals for the n-type transistor circuits are active on a high signal (VH). However, the logic level for activation of the various circuits could be changed by simple logic inverters if needed.

<FIG> shows a detailed state diagram <NUM> for a control circuit for an example power delivery system for a mobile device with passive orientation detection. State diagram <NUM> is suitable for use with the control circuit of <FIG> as will become apparent from the discussion below.

Processing for the control circuit begins in a first state (STATE <NUM>), which corresponds to an IDLE state. In the IDLE state, PIN1 and PIN2 are set in a "no connect" or "open circuit" condition as previously described. A timer is employed in the IDLE state. Once the timer expires (i.e., TIMER ELAPSED) the control circuit transitions from the first state (STATE l) to a second state (STATE2).

The second state (STATE <NUM>) corresponds to a DETECT state. In the DETECT state, PIN1 is coupled to the high-side supply (e.g., VH) and PIN2 is configured to test the orientation of the power connector for a normal orientation. For example, transistor circuits <NUM> and <NUM> of switch circuit <NUM> may be activated by the controller circuit <NUM> in STATE <NUM>, where activation of the pulldown resistor R32 via transistor circuit <NUM> will allow testing of the voltage at PIN2_DETECT. When voltage is detected at GND (e.g., "DETECT = GND" or "DETECT = VL"), this indicates that the cable is not connected or that there is an open circuit since there is no conduction path from PIN1 to PIN2. When voltage is detected above ground ("DETECT != GND" or "DETECT != VL"), this indicates that there is a conduction path between PIN <NUM> and PIN2. STATE <NUM> transitions back to STATE <NUM>, the IDLE state, when "DETECT = VL". STATE <NUM> transitions to STATE <NUM> when "DETECT != VL".

The third state (STATE <NUM>) corresponds to an ATTACH A state. In the ATTACH A state, PIN1 is coupled to the high-side supply (e.g., VH) and the PIN2 DETECT voltage is evaluated to be either at the high-supply voltage ("DETECT = VH"), at about half the supply voltage ("DETECT ≈ VH/<NUM>"), or between the half supply voltage and the high supply voltage ("VH/<NUM> < DETECT < VH"). The control circuit transitions from the third state to a first state when the PIN2_DETECT yields "DETECT = VH". The control circuit transitions from the third state to a fourth state when the PIN2_DETECT yields "DETECT ≈ VH/<NUM>". The control circuit transitions from the third state to a fifth state when the PIN2_DETECT yields "VH/<NUM> < DETECT < VH".

The fourth state (STATE <NUM>) corresponds to CONNECTED B, wherein PIN1 is coupled to VL and PIN2 is coupled to VL. The control circuit will maintain the switch circuit in this state as long as the operating current is above a minimum threshold (Current > IMIN). When the detected current drops below the minimum threshold (Current < IMIN), the fourth state transitions back to the first state (IDLE).

The fifth state (STATE <NUM>) corresponds to ATTACHB, wherein PIN2 is coupled to the low-side supply VL. , and the PIN1 DETECT voltage is evaluated. The fifth state is a reverse of the third state. If the PIN1_DETECT yields a voltage between the half supply voltage and the high supply voltage ("VH/<NUM> < DETECT < VH") in this state then a short is detected since the voltage was unchanged with a reversal of pins between STATE <NUM> and STATE <NUM>; and the fifth state will transition to a seventh state. If the PIN1 DETECT corresponds to a voltage at about the half supply voltage in the fifth state ("DETECT ≈ VH/<NUM>") in this state, then a reversal is required and the fifth state transitions to the sixth state. Lastly, if the detected voltage drops to GROUND (or VL) in state <NUM>, then this indicates an IDLE condition and the control circuit transitions to the first state.

The sixth state (STATE <NUM>) corresponds to CONNECTED A, wherein PIN2 is coupled to VL and PIN1 is coupled to VL. The control circuit will maintain the switch circuit in this state as long as the operating current is above a minimum threshold (Current > IMIN). When the detected current drops below the minimum threshold (Current < IMIN), the sixth state transitions back to the first state (IDLE).

The seventh state (STATE <NUM>) corresponds to SHORT CIRCUIT, wherein PIN2 and PIN are disconnected from power (PIN1 = NC, PIN2 = NC) and a timeout counter starts. The timeout will prevent reconnection to power for a minimum amount of elapsed time to prevent damage. After the timeout counter expires, the seventh state transitions back to the first state (IDLE).

<FIG> shows a detailed state diagram <NUM> for another control circuit for an example power delivery system for a mobile device with passive orientation detection. State diagram <NUM> is suitable for use with the control circuit of <FIG> as will become apparent from the discussion below.

The second state (STATE <NUM>) corresponds to a DETECT state. In the DETECT state, PIN2 is coupled to the low-side supply (e.g., VL or GND in this example) and PIN1 is configured to test the orientation of the power connector for a normal orientation. For example, transistor circuits <NUM> and <NUM> of switch circuit <NUM> may be activated by the controller circuit <NUM> in STATE <NUM>, where activation of the pullup resistor R51 via transistor circuit <NUM> will allow testing of the voltage at PIN1_DETECT. When voltage is detected at the high-side supply (e.g., "DETECT = VH"), this indicates that the cable is not connected or that there is an open circuit since there is no conduction path from PIN1 to PIN2. When voltage is detected below the high-side supply ("DETECT != VH"), this indicates that there is a conduction path between PIN <NUM> and PIN2. STATE <NUM> transitions back to STATE <NUM>, the IDLE state, when "DETECT = VH". STATE <NUM> transitions to STATE <NUM> when "DETECT != VH".

The third state (STATE <NUM>) corresponds to an ATTACH A state. In the ATTACH A state, PIN2 is coupled to the low-side supply (e.g., VL or GND in this example) and the PIN1 DETECT voltage is evaluated to be either at the high-supply voltage ("DETECT = VH"), at about half the supply voltage ("DETECT ≈ VH/<NUM>"), or between the half supply voltage and the low supply voltage or GND ("GND < DETECT < VH/<NUM>"). The control circuit transitions from the third state to the first state (IDLE) when the PI12_DETECT yields "DETECT = VH". The control circuit transitions from the third state to a fourth state when the PIN1 DETECT yields "DETECT ≈ VH/<NUM>". The control circuit transitions from the third state to a fifth state when the PIN1 DETECT yields "GND < DETECT < VH/<NUM>".

The fourth state (STATE <NUM>) corresponds to CONNECTED B, wherein PIN1 is coupled to VL (or GND in this example) and PIN2 is coupled to VH. The control circuit will maintain the switch circuit in this state as long as the operating current is above a minimum threshold (Current > IMIN). When the detected current drops below the minimum threshold (Current < IMIN), the fourth state transitions back to the first state (IDLE).

The fifth state (STATE <NUM>) corresponds to ATTACHB, wherein PIN1 is coupled to the low-side supply (VL or GND in this example), and the PIN2_DETECT voltage is evaluated. The fifth state is a reverse of the third state. If the PIN2_DETECT yields a voltage between the high-side supply voltage and the low-side supply or GND ("GND < DETECT < VH/<NUM>") in this state, then a short circuit is detected since the voltage was unchanged with a reversal of pins between STATE <NUM> and STATE <NUM>; and the fifth state will transition to a seventh state. If the PIN2_DETECT corresponds to a voltage at about the half supply voltage in the fifth state ("DETECT ≈ VH/<NUM>"), then a reversal of the power connection is required and the fifth state transitions to the sixth state. Lastly, if the detected voltage drops to GND (or VL in another example) in state <NUM>, then this indicates an IDLE condition and the control circuit transitions to the first state.

The sixth state (STATE <NUM>) corresponds to CONNECTED A, wherein PIN2 is coupled to VL (or GND in this example) and PIN1 is coupled to VH. The control circuit will maintain the switch circuit in this state as long as the operating current is above a minimum threshold (Current > IMIN). When the detected current drops below the minimum threshold (Current < IMIN), the sixth state transitions back to the first state (IDLE).

The seventh state (STATE <NUM>) corresponds to SHORT CIRCUIT, wherein PIN2 and PIN1 are disconnected from power (PIN1 = NC, PIN2 = NC) and a timeout counter starts. The timeout will prevent reconnection to power for a minimum amount of elapsed time to prevent damage. After the timeout counter expires, the seventh state transitions back to the first state (IDLE).

The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.

Claim 1:
A two-wire power delivery system comprising:
a passive protection circuit in a mobile device with a two-wire power interface that includes two power pins;
a control circuit, external from the mobile device, wherein the control circuit is powered by a high-side power supply (VH) and a low-side power supply (VL), and wherein the control circuit is configured to detect a voltage at a detect pin and generate one or more control signals; and
a switch circuit, external from the mobile device, that is configured to selectively control connections between the two power pins (PIN1, PIN2) of the mobile device and one or more of the high-side power supply (VH), the low-side power supply (VL), and the voltage detect pin of the control circuit, such that:
in an IDLE state;
in a TEST state, one of the two power pins (PIN1, PIN2) of the mobile device is coupled to one of the high-side power supply and the low-side power supply by the switch circuit, and the other of the two power pins (PIN1, PIN2) is coupled through a series resistor to the other of the high-side power supply and the low-side power supply which corresponds to the detect pin of the control circuit, wherein the control circuit determines an orientation of the two power pins based on a detected voltage at the detect pin; and
in a CONNECT state, one of the two power pins is coupled to one of the high-side power supply and the low-side power supply by the switch circuit, and the other of the two power pins is coupled to the other of the high-side power supply and the low-side power supply by the switch circuit based on the determined orientation,
characterized in that the switch circuit is configured to decouple the two power pins (PIN2, PIN2) from external power.