Patent Description:
Non-volatile memory has been used extensively in personal computers, telecommunications, consumer electronics and other fields. Electrically erasable programmable read only memory (EEPROM) and flash memory are among the most widely employed non-volatile memory.

The <CIT> describes an apparatus with a first and second plane of memory cells, a buffer and controller that an independent state completion for each plane during flash memory programming.

The <CIT> describes a non-volatile memory with customized control of injection type of disturb during program verify for improved program performance.

The <CIT> describes a NAND cell encoding to improve data integrity by obtaining the temperature and modify the cell encoding based on the obtained temperature.

Memory devices may be classified into a single-plane type and a multi-plane type in accordance with the structural configuration of memory arrays. The single-plane type memory device includes memory arrays organized into a single plane, and the multi-plane type memory device includes memory arrays organized into a plurality of planes. When programming the multi-plane type memory device, two or more memory planes may be programmed simultaneously to enhance the programming efficiency. However when the multi-plane type memory device contains defective memory planes, both the normal memory planes and defective memory planes will be repeatedly programmed in an attempt to program data into the defective memory planes, decreasing the programming speed, reducing the programming efficiency, and increasing program disturbance in the normal memory plane.

According to one embodiment, a memory device includes a plurality of planes, a row driver and a controller. A method of programming the memory device includes in a program operation, the row driver applying a program pulse to a plurality of memory cells of a first plane of the plurality of planes; after the row driver applies the program pulse to the plurality of memory cells, the controller verifying if the plurality of memory cells have reached a predetermined program state; and if a preset number of the plurality of memory cells have failed to reach the predetermined program state after the plurality of memory cells have been verified for a predetermined number of times, the controller disabling the first plane.

Although embodiments of the invention will be described with reference to a <NUM>-dimentional NAND flash device, it will be understood that embodiments of the present inventive concept are not limited thereto to this configuration but are also applicable to a <NUM>-dimentional NAND flash memory device. In addition, the invention is applicable to other nonvolatile memory devices, such as an electrically erasable and programmable read only memory (EEPROM), a NOR flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like, without departing from the scope of the present invention.

<FIG> is a block diagram of a memory device <NUM> according to an embodiment of the invention. The memory device <NUM> has a dual-plane structure, and may include a controller <NUM>, a voltage generation circuit <NUM>, a row decoder <NUM>, column drivers <NUM>, <NUM> and planes <NUM>, <NUM>. While the dual-plane structure is used in the embodiment, it should be appreciated that other numbers of planes may also be adopted within the scope of the invention. The planes <NUM>, <NUM> may be programmed simultaneously. After programming, if the plane <NUM> or the plane <NUM> is verified as failed for a predetermined number of times, the row driver <NUM> may disable the failed plane <NUM> or <NUM> from subsequent programming. The disablement of the failed plane reduces the time spent in an attempt to program the same, and reduce program disturbance in the operating plane.

The controller <NUM> may be coupled to the voltage generation circuit <NUM> and the column drivers <NUM>, <NUM>. The voltage generation circuit <NUM> may be coupled to the row driver <NUM>. The row driver <NUM> may be coupled to the plane <NUM> via a string select line SSL1, word lines WL1(<NUM>) to WL1(N) and a ground select line GSL1, N being a positive integer, e.g., N=<NUM>. The row driver <NUM> may be coupled to the plane <NUM> via a string select line SSL2, word lines WL2(<NUM>) to WL2(N) and a ground select line GSL2. The column driver <NUM> may be coupled to the plane <NUM> via bit lines BL1(<NUM>) to BL1(M), M being a positive integer, e.g., M=<NUM>. The column driver <NUM> may be coupled to the plane <NUM> via bit lines BL2(<NUM>) to BL2(M). Each of the planes <NUM>, <NUM> may contain a plurality of blocks, each block may contain a plurality of pages, and each page may contain an array of memory cells. The array of memory cells in the plane <NUM> may be addressed by the word lines WL1 (<NUM>) to WL1(N) and the bit lines BL1(<NUM>) to BL1(M), and the array of memory cells in the plane <NUM> may be addressed by the word lines WL2(<NUM>) to WL2(N) and the bit lines BL2(<NUM>) to BL2(M).

The controller <NUM> may communicate with an external host to receive data for storage in the planes <NUM>, <NUM> and to transmit data fetched from the planes <NUM>, <NUM>. The controller <NUM> may receive commands, addresses or data from the external host and generate column address signals Scadrl, Scadr2, a row address signal Sradr and a voltage control signal Svc. The voltage generation circuit <NUM> may generate voltages for read, program, erasure and verification operations in response to the voltage control signal Svc from the controller <NUM>. The voltages generated by the voltage generation circuit <NUM> may exceed a supply voltage provided to the memory device <NUM>. The row driver <NUM> may operate in response to the row address signal Sradr from the controller <NUM> to select word lines for the read, program, erasure and verification operations. The column drivers <NUM>, <NUM> may operate in response to the column address signals Scadrl, Scadr2 from the controller <NUM> to generate bit line signals to select bit lines for the read, program, erasure and verification operations. In the program operations, the voltage generation circuit <NUM> may generate a program voltage (e.g., 20V) and a program pass voltage (e.g., 10V) using the supply voltage (e.g., <NUM>. 3V), the row driver <NUM> may apply a program pulse having the magnitude of the program voltage to selected word lines, apply the program pass voltage to unselected word lines, apply the supply voltage to the string select lines SSL1, SSL2 and apply the ground voltage to the ground select lines GSL1, GSL2, and the column drivers <NUM>, <NUM> may apply a ground voltage (e.g., 0V) to selected bit lines, and apply the supply voltage to unselected bit lines. In the verification operations, the voltage generation circuit <NUM> may generate an appropriate verification voltage, the row driver <NUM> may apply the appropriate verification voltage to selected word lines, apply the supply voltage to the string select lines SSL1, SSL2 and apply the supply voltage to the ground select lines GSL1, GSL2, and the column drivers <NUM>, <NUM> may apply the ground voltage to unselected bit lines, and apply the supply voltage to selected bit lines of the planes <NUM>, <NUM> to read data from selected memory cells on the selected bit lines, respectively. If data read is incorrect, the controller <NUM> may verify the selected memory cell as failed, and if data read is correct, the controller <NUM> may verify the selected memory cell as passed.

<FIG> is a schematic diagram of a page in the planes <NUM>, <NUM>. The page may include memory cells C(<NUM>,<NUM>) to C(M,N), string select cells Css(<NUM>) to Css(M) and ground select cells Cgs(<NUM>) to Cgs(M). The memory cells C(<NUM>,<NUM>) to C(M,N) may be floating-gate transistors or charge-trapping transistors, and each of the memory cells C(<NUM>,<NUM>) to C(M,N), the string select cells Css(<NUM>) to Css(M) and the ground select cells Cgs(<NUM>) to Cgs(M) may include a control terminal, a first terminal and a second terminal. A string select line SSLn may be coupled to the control terminals of the string select cells Css(<NUM>) to Css(M), and the bit lines BL(<NUM>) to BL(M) may be respectively coupled to the first terminals of the string select cells Css(<NUM>) to Css(M). The memory cells C(<NUM>,<NUM>) to C(M,N) may be arranged into rows of memory cells coupled to the respective word lines WL(<NUM>) to WL(N). The word lines WL(<NUM>) to WL(N) may be coupled to the control terminals of the memory cells C(<NUM>,<NUM>) to C(M,<NUM>) of the first row to the control terminals of the memory cells C(<NUM>,N) to C(M,N) of the Nth row, respectively, and the first terminals of the memory cells C(<NUM>,<NUM>) to C(M,<NUM>) may be respectively coupled to the second terminals of the string select cells Css(<NUM>) to Css(M). A ground select line GSLn may be coupled to the control terminals of the ground select cells Cgs(<NUM>) to Cgs(M), the first terminals of the ground select cells Cgs(<NUM>) to Cgs(M) may be respectively coupled to the second terminals of the memory cells C(<NUM>,N) to C(M,N), and the second terminals of the ground select cells Cgs(<NUM>) to Cgs(M) may be coupled to ground terminals. The ground terminals may provide the ground voltage.

The memory cells C(<NUM>,<NUM>) to C(M,N) may be of a single-level cell (SLC) type, a multi-level cell (MLC) type, a triple-level cell (TLC) type, a quad-level cell (QLC) type, a penta-level cell (PLC) type, or a higher-level type. Each memory cells C(m,n) may hold one of Q possible data states, where Q is a positive integer equal to or greater than <NUM>, e.g., Q=<NUM> for an SLC, Q=<NUM> for an MLC, Q=<NUM> for a TLC, Q=<NUM> for a QLC, and Q=<NUM> for a PLC. The Q possible data states may include an erase state S(<NUM>) and program states S(<NUM>) to S(Q-<NUM>), with the program state S(<NUM>) being the lowest program state and the program state S(Q-<NUM>) being the highest program state. In one example, a TLC may be programmed into one of <NUM> possible data states, with the program state S(<NUM>) being the lowest program state and the program state S(<NUM>) being the highest program state.

The memory cells C(<NUM>,<NUM>) to C(M,N) may be initially set in the erase state S(<NUM>), and later, a series of program-verification operations may be performed on the memory cells C(<NUM>,<NUM>) to C(M,N) to program the same into respective target program states. The series of program-verification operations may start from the lowest program state S(<NUM>) and proceed to higher program states until the threshold voltages of selected memory cells reach respective verification voltage levels of respective target program states. In some embodiments, the verification voltages may be selected as the minimum threshold voltages of threshold voltage distribution curves of the program states S(<NUM>) to S(Q-<NUM>), respectively. Each program-verification operation may include a program operation and a subsequent verification operation. In the program operation, some of the memory cells C(<NUM>,<NUM>) to C(M,N) may be selected and programmed into a program state in a row-by-row manner from the first row to the Nth row, or from the Nth row to the first row. In the subsequent verification operation, the controller <NUM> may verify whether the selected memory cells have reached the program states in the row-by-row manner from the first row to the Nth row, or from the Nth row to the first row. In this fashion, the memory cells C(<NUM>,<NUM>) to C(M,N) may be programmed into the respective target program states.

<FIG> is a block diagram of the column drivers <NUM>, <NUM> and the controller <NUM>. Each of the column drivers <NUM>, <NUM> may include page buffers <NUM> to 30n, fail bit counters <NUM> to 32n and column decoders <NUM> to 34n. The controller <NUM> may include an adder <NUM>. In some embodiments, the column drivers <NUM>, <NUM> may further include sense amplifiers to detect currents from the selected bit lines, thereby reading data from the planes <NUM>, <NUM>, respectively. The page buffers <NUM> to 30n may be coupled to the fail bit counters <NUM> to 32n, respectively. The fail bit counters <NUM> to 32n may be coupled to the column decoders <NUM> to 34n, respectively. The column decoders <NUM> to 34n may be coupled to the adder <NUM>. In some embodiments, the adder <NUM> may be located in each of the column drivers <NUM>, <NUM>, and may be coupled to the controller <NUM>.

When verifying a program state S(q) of the planes <NUM>, <NUM>, the column decoders <NUM> to 34n may receive column addresses in the column address signals Scadrl, Scadr2 to select bit lines of the planes <NUM>, <NUM>, so as to retrieve data from selected memory cells in the pages of the planes <NUM>, <NUM> to the page buffers <NUM> to 30n, respectively. The fail bit counters <NUM> to 32n may count the number of memory cells verified as failed in the pages of the planes <NUM>, <NUM> to generate page fail bit counts, respectively. The adder <NUM> may accumulate page fail bit counts of all pages of the plane <NUM> to generate a first plane fail bit count, and accumulate page fail bit counts of all pages of the plane <NUM> to generate a second plane fail bit count. If the first plane fail bit count is less than a preset plane fail bit count, the controller <NUM> may verify the plane <NUM> as passed, and if the first plane fail bit count exceeds the preset plane fail bit count, the controller <NUM> may verify the plane <NUM> as failed. Similarly, if the second plane fail bit count is less than the preset plane fail bit count, the controller <NUM> may verify the plane <NUM> as passed, and if the second plane fail bit count exceeds the preset plane fail bit count, the controller <NUM> may verify the plane <NUM> as failed. When the planes <NUM>, <NUM> are verified as failed for a predetermined number of times, e.g., <NUM> times, the controller <NUM> may disable the planes <NUM>, <NUM>. When the planes <NUM>, <NUM> are verified as passed prior to being verified as failed for the predetermined number of times, the controller <NUM> may continue to program the planes <NUM>, <NUM> into the next program state S(q+<NUM>).

When the plane <NUM> and/or the plane <NUM> is verified as passed, the controller <NUM> may generate a fail bit pass signal indicating a program pass, and when both the plane <NUM> and the plane <NUM> are verified as failed, the controller <NUM> may generate a fail bit pass signal indicating a program failure. The fail bit pass signal may be used to determine whether to continue to program the memory device <NUM>. In some embodiments, the controller <NUM> may set the fail bit pass signal to the logical high to continue programming of the memory device <NUM>, and set the fail bit pass signal to the logical low to cease programming of the memory device <NUM>. In some embodiments, the controller <NUM> may further generate a status report indicating a program result upon exiting the program-verification operations. When at least one of the planes <NUM>, <NUM> completes programming of the highest state S(Q-<NUM>), the status report may indicate a program pass. When both the planes <NUM>, <NUM> are disabled prior to completion of programming of the highest state S(Q-<NUM>), the status report may indicate a program failure. When program pulses applied to the memory device <NUM> exceed a maximum program pulse count, the status report may indicate a program failure.

<FIG> is a schematic diagram of a selected circuit in the controller <NUM>. The controller <NUM> may include AND gates <NUM> and <NUM> to control access to the planes <NUM> and <NUM>, respectively. The AND gate <NUM> may receive a plane address signal Sap1, a fail bit pass signal Sfbp and a plane disable signal Sdisp1 to generate a plane select signal Ssp1. The AND gate <NUM> may receive a plane address signal Sap2, the fail bit pass signal Sfbp and a plane disable signal Sdisp2 to generate a plane select signal Ssp2. The controller <NUM> may generate the column address signal Scadr1 according to the plane select signal Sspl, generate the column address signal Scadr2 according to the plane select signal Ssp2, and generate the row address signal Sradr according to the plane select signals Sspl, Ssp2. In some embodiments, when it is determined to disable the plane <NUM>, the controller <NUM> may set the plane disable signal Sdisp1 a logical low, the AND gate <NUM> may block the plane select signal Ssp1 in response to the plane disable signal Sdisp1 by setting the plane select signal Ssp1 to the logical low, and the controller <NUM> may generate the row address signal Sradr and the column address signal Scadr1 to deselect the word lines WL1(<NUM>) to WL1(N) and the bit lines BL1(<NUM>) to BL1(M) of the plane <NUM>. Likewise, when it is determined to disable the plane <NUM>, the controller <NUM> may set the plane disable signal Sdisp2 to the logical low, the AND gate <NUM> may block the plane select signal Ssp2 in response to the plane disable signal Sdisp2 by setting the plane select signal Ssp2 to the logical low, and the controller <NUM> may generate the row address signal Sradr and the column address signal Scadr2 to deselect the word lines WL2(<NUM>) to WL2(N) and the bit lines BL2(<NUM>) to BL2(M) of the plane <NUM>.

In some embodiments, the AND gate <NUM> may receive a first block address signal in place of the plane address signal Sap1 to generate a first block select signal, and the AND gate <NUM> may receive a second block address signal in place of the plane address signal Sap2 to generate a second block select signal. The controller <NUM> may generate the column address signal Scadr1 according to the first block select signal, generate the column address signal Scadr2 according to the second block select signal, and generate the row address signal Sradr according to the first block select signal and the second block select signal. In some embodiments, when it is determined to disable the plane <NUM>, the controller <NUM> may set the plane disable signal Sdisp1 to the logical low, the AND gate <NUM> may block the first block select signal in response to the plane disable signal Sdisp1 by setting the first block select signal to the logical low, and the controller <NUM> may generate the row address signal Sradr and the column address signal Scadr1 to deselect the word lines WL1(<NUM>) to WL1(N) and the bit lines BL1(<NUM>) to BL1(M) of the plane <NUM>. Likewise, when it is determined to disable the plane <NUM>, the controller <NUM> may set the plane disable signal Sdisp2 to the logical low, the AND gate <NUM> may block the second block select signal in response to the plane disable signal Sdisp2 by setting the second block select signal to the logical low, and the controller <NUM> may generate the row address signal Sradr and the column address signal Scadr2 to deselect the word lines WL2(<NUM>) to WL2(N) and the bit lines BL2(<NUM>) to BL2(M) of the plane <NUM>.

The controller <NUM> may employ a program state counter q, failed verification counts Cvfl, Cvf2 and a program pulse count Cp to generate the plane disable signals Sdispl, Sdisp2 to control access to the planes <NUM>, <NUM>. The program state counter q may be a positive integer ranging between <NUM> and (Q-<NUM>). The failed verification counts Cvfl, Cvf2 may be positive integers ranging between <NUM> and a maximum failure count Cvmax (q). The maximum failure count Cvmax(q) may define the maximum number of times to perform verifications of a program state S(q) prior to disabling a plane, and may be specific to the program state S(q). For example, the program states S(<NUM>) to S(<NUM>) may be assigned maximum failure counts Cvmax(<NUM>) to Cvmax(<NUM>), respectively. The maximum failure count Cvmax(q) may be a positive integer greater than <NUM>, and may be set during a manufacturing setup. The program pulse count Cp may be positive integers ranging between <NUM> and a maximum program pulse count Cpmax. The maximum program pulse count Cpmax may define the maximum number of times to apply program pulses to the planes <NUM>, <NUM>, and may be a positive integer greater than <NUM> and set during the manufacturing setup.

When the planes <NUM>, <NUM> are verified as failed for the predetermined number of times as defined by the maximum failure count Cvmax(q), the controller <NUM> may disable the planes <NUM>, <NUM> for the subsequent programming, thereby accelerating data programming and reducing program disturbance in the operating plane.

<FIG> is a flowchart of a method <NUM> of programming the memory device <NUM>. The method <NUM> comprises Steps S502 to S542, performing multi-plane program on the planes <NUM>, <NUM> and disabling the planes <NUM>, <NUM> according to respective failed verification counts Cvfl, Cvf2 of the planes <NUM>, <NUM>. Steps S502 to S508 are used to program and verify the memory device <NUM>. Steps S512 to S516 are used to determine whether to disable the plane <NUM>. Steps S522 to S526 are used to determine whether to disable the plane <NUM>. Steps S532 to S536 are used to complete programming of the program-enabled planes <NUM>, <NUM>. Steps S540 and S542 are used to disable programming of the memory device <NUM> according to a program pulse count Cp. Any reasonable step change or adjustment is within the scope of the disclosure. Steps S502 to S542 are explained as follows:.

The method <NUM> may be exemplified using the memory device <NUM> and TLC memory cells to illustrate details of Steps. Upon startup of the multi-plane program, the planes <NUM>, <NUM> are initialized for programming. The controller <NUM> sets the plane disable signals Sdispl, Sdisp2 and the fail bit pass signal Sfbp to the logical high, and sets the program pulse count Cp, the failed verification counts Cvfl, Cvf2 to and the program state counter q (S502). In some embodiments, the program pulse count Cp and the failed verification counts Cvfl, Cvf2 may be reset to <NUM> (Cp=<NUM>, Cvf1=<NUM>, Cvf2=<NUM>), and the program state counter q may be reset to <NUM> (q=<NUM>). Next, the row driver <NUM> applies a program pulse to selected word lines of the planes <NUM>, <NUM> (S504) and the controller <NUM> increments the program pulse count Cp by <NUM> (Cp=<NUM>) (S506). The controller <NUM> verifies if memory cells of the planes <NUM>, <NUM> has reached the program state S(<NUM>) (S508). If more than a preset number of the memory cells of the planes <NUM>, <NUM> have failed to reach the program state S(<NUM>), the controller <NUM> will verify the planes <NUM>, <NUM> as failed. If less than the preset number of the memory cells of the planes <NUM>, <NUM> have failed to reach the program state S(<NUM>), the controller <NUM> will verify the planes <NUM>, <NUM> as passed.

If the controller <NUM> has verified the plane <NUM> as failed (S510), the controller <NUM> next determines whether the failed verification count Cvf1 is less than a maximum failure count Cvmax(<NUM>) of the program state S(<NUM>) (S512). In some embodiments, the maximum failure count Cvmax(<NUM>) may be <NUM>. If the failed verification count Cvf1 (Cvf1=<NUM>) is less than a maximum failure count Cvmax(<NUM>) (Cvmax(<NUM>)=<NUM>), the controller <NUM> increments the failed verification count Cvf1 by <NUM> (Cvf1=<NUM>) (S514). In Step S540, the controller <NUM> determines whether the program pulse count Cp is less than the maximum program pulse count Cpmax. In some embodiments, the maximum program pulse count Cpmax may be <NUM>. If the program pulse count Cp (Cp=<NUM>) is less than the maximum program pulse count Cpmax (Cpmax=<NUM>), the controller <NUM> iterates over Steps S504 to S514 and Step S540 until the plane <NUM> remains verified as failed when the failed verification count Cvf1 reaches <NUM>. When the controller <NUM> determines that the failed verification count Cvf1 (Cvf1=<NUM>) is not less than a maximum failure count Cvmax(<NUM>) (Cvmax(<NUM>)=<NUM>), the controller <NUM> sets the plane disable signal Sdisp1 to the logical low while maintaining the fail bit pass signal Sfbp to the logical high to disable the plane <NUM> (S516).

Similarly, if the controller <NUM> has verified the plane <NUM> as failed (S520), the controller <NUM> next determines whether the failed verification count Cvf2 (Cvf2=<NUM>) is less than the maximum failure count Cvmax(<NUM>) (Cvmax(<NUM>)=<NUM>) of the program state S(<NUM>) (S522). If so, the controller <NUM> increments the failed verification count Cvf2 by <NUM> (Cvf2=<NUM>) (S524). In Step S540, the controller <NUM> determines whether the program pulse count Cp (Cp=<NUM>) is less than the maximum program pulse count Cpmax (Cpmax=<NUM>). If so, the controller <NUM> iterates over Steps S504 to S508, Steps S520 to S524 and Step S540 until the plane <NUM> remains verified as failed when the failed verification count Cvf2 reaches <NUM>. When the controller <NUM> determines that the failed verification count Cvf2 (Cvf2=<NUM>) is not less than a maximum failure count Cvmax(<NUM>) (Cvmax(<NUM>)=<NUM>), the controller <NUM> sets the plane disable signal Sdisp2 to the logical low while maintaining the fail bit pass signal Sfbp to the logical high to disable the plane <NUM> (S526).

If the controller <NUM> has verified both the planes <NUM>, <NUM> as passed prior to the respective failed verification counts Cvfl, Cvf2 reaching the maximum failure count Cvmax(<NUM>), or verified one of the planes <NUM>, <NUM> as passed prior to the respective failed verification counts Cvfl, Cvf2 reaching the maximum failure count Cvmax(<NUM>) and disabled the other one of the planes <NUM>, <NUM> (S530), the controller <NUM> next determines whether the program state S(<NUM>) is less than the highest program state S(<NUM>) (S532). For example, the controller <NUM> may verify the plane <NUM> as passed and the plane <NUM> as failed upon applying the fourth program pulse (Cp=<NUM>, Cvf1=<NUM>, Cvf2=<NUM>), disable the plane <NUM> (S526) and proceed to program the plane <NUM> into the next program state S(<NUM>). If the program state S(<NUM>) is less than the highest program state S(<NUM>), the controller <NUM> increments the program state counter q by <NUM> (q=<NUM>) and resets the failed verification counts Cvfl, Cvf2 to <NUM> (Cvf1=<NUM>, Cvf2=<NUM>) (S534), and determines whether the program pulse count Cp (Cp=<NUM>) is less than the maximum program pulse count Cpmax (Cpmax=<NUM>) (S540). If so, since the plane <NUM> has been disabled, the controller <NUM> iterates over S504 to S514, Steps S530 to S534, and Step S540 until the plane <NUM> is disabled, the highest program state S(<NUM>) is reached, or the program pulse count Cp reaches the maximum program pulse count Cpmax. When both the plane <NUM> and the plane <NUM> are disabled, the controller <NUM> sets the plane disable signal Sdisp1 and the fail bit pass signal Sfbp to the logical low, generates a status report indicating that a program failure and exits the method <NUM> (S516). When the highest program state S(<NUM>) is reached, the controller <NUM> generates the status report indicating that a program pass and exits the method <NUM> (S536). When the program pulse count Cp (Cp=<NUM>) reaches the maximum program pulse count Cpmax (Cpmax=<NUM>), the controller <NUM> sets the fail bit pass signal Sfbp to the logic low, generates the status report indicating that a program failure and exits the method <NUM> (S542).

In Steps S512 and S522, the maximum failure count Cvmax(q) may be identical to or different from other maximum failure counts Cvmax (<NUM>) to Cvmax(q-<NUM>), Cvmax(q+<NUM>) to Cvmax (Q-<NUM>). For example, two or more of the maximum failure counts Cvmax(<NUM>) to Cvmax(<NUM>) may be identical, e.g., Cvmax (<NUM>)=Cvmax (<NUM>)=. =Cvmax(<NUM>)=<NUM>. In other embodiments, two or more of the maximum failure counts Cvmax(<NUM>) to Cvmax(<NUM>) may be different, e.g., Cvmax(<NUM>)=<NUM> and Cvmax(<NUM>)=<NUM>.

In Steps S516 and S526, the plane disable signals Sdispl, Sdisp2 are set to the logical low to set the plane select signals Sspl, Ssp2 to the logical low, set the first block select signal or the second block select signal to the logical low, or set other signals controlling the word lines WL1(<NUM>) to WL1(N), WL2(<NUM>) to WL2(N), the bit lines BL1(<NUM>) to BL1(M), BL2 (<NUM>) to BL2(M), the string select lines SSL1, SSL2, and the ground select lines GSL1, GSL2 to the logical low. When one of the planes <NUM>, <NUM> is verified as passed, the fail bit pass signal Sfbp may be set to the logical high to continue programming of the memory device <NUM>.

The method <NUM> is used to identify a failed plane upon verifying the plane as failed for a predetermined number of times, and disable the failed plane while continuing to program the operating plane, thereby accelerating data programming and reducing program disturbance in the operating plane.

<FIG> is a flowchart of a method <NUM> of programming the memory device <NUM>. The method <NUM> comprises Steps S602 to S616, disabling the planes <NUM>, <NUM> according to respective failed verification counts Cvfl, Cvf2 of the plane <NUM>/<NUM>. Steps S602 and S604 are used to program and verify the memory device <NUM>. Steps S606 to S610 are used to determine whether to disable the plane <NUM>/<NUM>. Steps S612 to S616 are used to continue to complete programming of the program-enabled planes <NUM>, <NUM>. Any reasonable step change or adjustment is within the scope of the disclosure. Steps S602 to S616 are explained as follows:.

The explanation for Steps S602 to S616 have been provided in the preceding paragraphs and will not be repeated here. In the method <NUM>, when the planes <NUM>, <NUM> are verified as failed for the predetermined number of times, the controller <NUM> may disable the failed planes <NUM>, <NUM> for the subsequent programming, thereby accelerating data programming and reducing program disturbance in the operating plane.

Claim 1:
A method (<NUM>, <NUM>) of programming a memory device (<NUM>), the memory device (<NUM>) comprising planes (<NUM>, <NUM>), and a controller (<NUM>) coupled to the planes (<NUM>,<NUM>), the method (<NUM>, <NUM>) comprising:
applying, by the controller (<NUM>), a first program pulse to selected word lines of the planes (<NUM>, <NUM>);
verifying, by the controller (<NUM>), whether memory cells of the planes (<NUM>, <NUM>) have reached a predetermined program state(S(Q));
in response to more than a preset number of the memory cells of the planes (<NUM>, <NUM>) have failed to reach the program state (S(q)), after the plurality of memory cells have been verified for a predetermined number of times, verifying, by the controller (<NUM>), the planes (<NUM>, <NUM>) as failed;
incrementing, by the controller (<NUM>), a failed verification count (Cvf1, Cvf2) in response to the planes (<NUM>,<NUM>) have not been programmed successfully yet;
if the planes (<NUM>, <NUM>) are verified as failed for the predetermined number of times as defined by a maximum failure count (Cvmax(q)), disabling, by the controller (<NUM>), the planes (<NUM>,<NUM>) for the subsequent programming.