Patent Description:
The following publication is acknowledged: <NPL>.

The present disclosure is better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

Clock distribution for the components of a ring transport often consumes considerable power, and this power consumption is exacerbated by conventional implementations in which errant clock wake signals circle the ring transport indefinitely, leading to a ring transport that is full of clock wake signals and thus continuously clocked. The following disclosure describes systems and techniques for reduced power consumption in a ring transport through implementation of a sleep controller that serves to suppress, or "squash", errant clock wake signals traveling through the ring transport. In suppressing these errant clock wake signals, the nodes of the ring transport can switch to an unclocked state, and thus reduce their power consumption, while the ring transport is idle.

In at least one embodiment, the ring transport includes a plurality of nodes connected into a ring via a wire interconnect composed of a plurality of wires, including wires for conducting control signaling and wires for conducting data signaling. A sleep controller is connected to a select node and operates to control operation of the node with regard to forwarding, or "repeating", clock wake signals received at the node. The sleep controller monitors the wire interconnect at the controlled node for clock wake signals and data packets. After a specified idle duration at the node in which no data traffic has been received by the node, the sleep controller configures the node into an active clock suppression state in which the node is controlled so as to suppress any received clock wake signals (that is, to refrain from forwarding any received clock wake signals). In at least one embodiment, the sleep controller maintains the node in this clock suppression state for a duration sufficient to clear any errant clock wake signals traveling around the ring transport. After lapse of the specified duration for the clock suppression state, the sleep controller enters a dormant state in which the node is permitted to forward any newly received clock wake signal, and if the clock wake signal is followed by a data packet, the sleep controller reverts to an active state in which the node is controlled to implement active operation.

In this manner, the sleep controller acts via the controlled node to actively clear errant clock wake signals from the ring transport following an idle period, and then reverts to a state in which the node can react to a new clock wake signal appearing on the ring transport, which is a likely indication of the start up of data traffic again on the ring transport. Through this active clock wake signal suppression, the ring transport is allowed to switch to an actual idle state in the absence of errant clock signals, and thus the nodes can remain in an unclocked state, with commensurate reduction in power reduction, during this idle state.

<FIG> illustrates an integrated circuit (IC) device <NUM> having a ring transport <NUM> employing active clock wake suppression in accordance with some embodiments. The IC device <NUM> can include a single IC chip, such as a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), and the like, or multiple IC chips mounted on a common substrate, circuit board, or other carrier, such as a multi-chip module (MCM). Examples of the IC device <NUM> include central processing units (CPUs), graphics processing units (GPUs), accelerated processing units (APUs), digital signal processors (DSPs), or other processors, as well as other systems typically implemented on one or more IC chips.

The ring transport <NUM> includes a plurality of nodes <NUM>, such as the depicted four nodes <NUM>-<NUM> to <NUM>-<NUM>, connected via a wire interconnect <NUM> into a ring shape such that control and data signaling is transmitted node-to-node in a single direction (e.g., clockwise direction <NUM>) for a uni-directional ring implementation or in either direction for a bi-directional ring implementation. This control and data signaling continue to circle around the ring shape until consumed or suppressed at one of the nodes <NUM>. Each node <NUM> is connected to one or more components <NUM> of the IC device <NUM>, such as components <NUM>-<NUM> to <NUM>-<NUM> connected to nodes <NUM>-<NUM> to <NUM>-<NUM>, respectively. These components <NUM> operate to one or both of inject data traffic into the ring transport <NUM> via the corresponding node <NUM> for transmission to one or more other nodes <NUM> or to consume data traffic being transmitted by the ring transport <NUM> from another node <NUM>. The components <NUM> include any of a variety of elements of the IC device <NUM>, such as processing elements, storage elements, bus or interface elements, input/output device elements, and the like.

The nodes <NUM> and the components <NUM> are clocked based on a ring clock signal <NUM>, also referred to herein as "RING_CLK" <NUM>, distributed among the nodes <NUM> and components <NUM> via a clock distribution tree <NUM>. The ring clock signal <NUM> can be, for example, the system clock for the IC device <NUM>, or a clock derived therefrom and particular to the ring transport <NUM>. If the ring transport <NUM> and the associated components <NUM> remain active and thus clocked the entire time the IC device <NUM> is at least minimally powered, considerable power would be consumed by the clock distribution tree <NUM> and its clock sinks. To avoid this unnecessary power draw, the ring transport <NUM> employs a clock wake scheme in which the nodes <NUM> and the components <NUM> clocked by RING_CLK <NUM> are clock gated between transmissions of data packets on the ring transport <NUM>. Thus, when a node is preparing to transmit a data packet on the ring transport <NUM>, the node inserts a clock wake signal <NUM>, also referred to herein as "CLK_EN" <NUM>, that precedes the signaling representing the data packet by a specified number of clock cycles (e.g., <NUM> clock cycle). Thus, a node <NUM> receiving the clock wake signal <NUM> responds by switching from a clock gating state to a clocked state by deactivating the clock gating at the node <NUM> and its associated one or more components <NUM>, and thus is ready to receive and process the data packet following the clock wake signal <NUM>.

While the use of such clock wake signaling allows the nodes <NUM> to receive data traffic from upstream on short notice while also facilitating use of lower-power clock-gated idle states between data packets, the clock wake signaling often could otherwise lead to the entire ring transport <NUM> being continually clocked, and thus never able to enter into a lower-power idle state. To illustrate, unless a receiving node is able to determine that a given data packet is being consumed at the next node, the receiving node is unable to signal to the next node that a given clock wake signal should not be propagated further. As such, the clock wake signals that preceded a data packet could remain in the ring transport after the following data packet has been consumed and removed, and thus the ring transport <NUM> eventually could be "filled" with clock wake signals that effectively result in the ring transport <NUM> being continuously clocked. One solution to this errant clock wake signaling is the implementation of additional wires and logic to enable calculation at a given node as to whether a received data packet will be consumed and not propagated further at the next node, and using faster circuitry and wires to drive that indicator more quickly to the next node in time to enable its clocks. But such wiring and logic often is impracticable or consumes enough power to negate the power savings otherwise achievable through the clock wake scheme.

To mitigate the effect of errant clock wake signaling without relying on additional higher power wiring and logic at each node, in at least one embodiment the ring transport <NUM> employs a sleep controller <NUM> at a select one of the nodes <NUM> (e.g., node <NUM>-<NUM> in the illustrated example). In at least one embodiment, the sleep controller <NUM> operates to enter an active clock suppression state responsive to an idle condition at the associated node <NUM>-<NUM>. This idle condition includes, for example, the node <NUM>-<NUM> being idle for a specified duration. In this active clock suppression state, the sleep controller <NUM> controls the node <NUM>-<NUM> to suppress forwarding of any received clock wake signals <NUM>, that is, to "squash" any received clock wake signals <NUM> until either a valid data packet is received or a specified duration has passed. If a valid data packet is received while in the active clock suppression state, the sleep controller <NUM> ceases control of the node <NUM>-<NUM> to suppress received clock wake signals <NUM> and enters the normal active state. If the specified duration has passed, the sleep controller <NUM> enters a dormant state in which the node <NUM>-<NUM> is no longer being controlled to actively suppress received clock wake signals <NUM> (that is, the node <NUM>-<NUM> is permitted to forward clock wake signals <NUM>), and thus the node <NUM>-<NUM> can return to an active state in response to a clock wake signal <NUM> and a following data packet in short order. Under this approach, the active suppression of clock wake signals <NUM> at the node <NUM>-<NUM> for the specified duration allows the node <NUM>-<NUM> and the sleep controller <NUM> to remove any errant clock wake signals <NUM> from the ring transport <NUM>, and thus enter the dormant state in which the next clock wake signal <NUM> received should be a valid clock wake signal <NUM> that precedes a data packet and thus signaling that the ring transport <NUM> has returned to active data transmission.

<FIG> illustrates an implementation of the node <NUM>-<NUM> and the sleep controller <NUM> of the ring transport <NUM> of <FIG> in greater detail in accordance with some embodiments. For ease of illustration, the node <NUM>-<NUM> and sleep controller <NUM> are depicted for a uni-directional ring configuration that transmits signaling in the clockwise direction <NUM> (<FIG>). For a bi-directional ring configuration, it will be appreciated that the components and operations described below would be replicated for the control and data signaling traveling in the opposite direction (e.g., counter-clockwise).

In one embodiment, the wire interconnect <NUM> includes a plurality of wires (also commonly referred to as traces, leads, conductive lines, etc.), including wires for control signaling and wires for data signaling. The wires for data signaling include K data wires <NUM> to carry K data bits of a data packet (bits D0 to DK-<NUM>) in parallel (K >= <NUM>), or for a differential signaling implementation, <NUM>*K data wires <NUM>. The wires for control signaling include a valid wire <NUM> to carry a VALID signal that is asserted in conjunction with insertion of the data on the K data wires for a data packet to signal that the states of the data wires <NUM> represent valid data. The wires for control signaling further includes a CLK_EN wire <NUM> for communicating a clock wake signal <NUM> (e.g., a pulse or other temporary assertion of the CLK_EN wire <NUM>) a specified number of clock cycles (e.g., one clock cycle) preceding insertion of a corresponding data packet on the data wires <NUM>. The nodes <NUM>, including node <NUM>-<NUM>, implement a repeater <NUM> that serves to buffer, amplify, and forward the signaling of the wire interconnect <NUM> received at the input of the node <NUM>. In one embodiment, the repeater <NUM> is implemented as a plurality of digital buffers <NUM>, one for each wire of the wire interconnect with each digital buffer <NUM> having an input connected to the corresponding upstream wire segment on the input side of the node <NUM> and an output connected to the corresponding downstream wire segment on the output side of the node <NUM>. Although a per-wire single digital buffer implementation is shown, the repeater <NUM> can be implemented using other circuit configurations using the guidelines provided herein. Each of the nodes <NUM> further includes a skid buffer <NUM> disposed at the input side (as shown) or the output side of the node <NUM>. The skid buffer <NUM> includes dual buffers <NUM>, <NUM>, multiplexing/demultiplexing circuitry <NUM>, <NUM>, and a controller <NUM>, and operates to buffer incoming data packets received on the data wires <NUM> for forwarding downstream. The dual buffers <NUM>, <NUM> allows the skid buffer <NUM> to buffer an incoming data packet while a previously received data packet is processed for subsequent downstream transmission.

Each node <NUM> further includes a node interface <NUM> that serves as the interface between the wire interconnect <NUM> of the node and the one or more components <NUM> of that node. The node interface <NUM> is coupled to the various wires of the wire interconnect <NUM> and operates to inject data packets for data received from the components <NUM> into the ring transport <NUM> for transmission to the downstream node, along with controlling the CLK_EN wire <NUM> and the valid wire <NUM> to provide the clock wake signal <NUM> that precedes the injected data packet and the valid signaling used to indicate the states of the data wires <NUM> represent valid data. On the receiving side, the node interface <NUM> operates to receive a clock wake signal <NUM> on the input side of the CLK_EN wire <NUM>, and in response deactivate any clock gating applied to the ring clock signal <NUM> at the node <NUM> or the one or more components <NUM> so that the node <NUM> and one or more components <NUM> are activated and clocked in time for receipt of the data packet that is expected to follow receipt of the clock wake signal <NUM>. If such a data packet does follow, the node interface <NUM> operates to determine if the data packet is intended for a component <NUM> associated with the node, and if so, provide a copy of the data of the data packet to the intended component <NUM>.

Turning to the sleep controller <NUM>, in one embodiment this component includes a state machine <NUM> and a set of count-down timers clocked by the ring clock signal <NUM> or clock derived therefrom, including an idle timer <NUM> and a suppression timer <NUM>. The state machine <NUM> is implemented using hardcoded logic, programmable logic, a processor executing firmware or hardware, or a combination thereof. The state machine <NUM> has an input coupled to the input side of the CLK_EN wire <NUM> to monitor for receipt of clock wake signals <NUM> at the node <NUM>-<NUM>, an input coupled to the input side of the valid wire <NUM> to monitor for receipt of valid data packets at the node <NUM>-<NUM> (recalling that assertion of the valid wire <NUM> signals that the "data" signaled by the data wires <NUM> is valid), and an output to provide a sleep signal <NUM> used to control the digital buffer <NUM> for the CLK_EN wire <NUM> such that if the sleep signal <NUM> is asserted (that is, SLEEP=<NUM>) and there is no incoming valid data packet (that is, VALID = <NUM>), then the digital buffer <NUM> is effectively disabled and thus does not repeat any received clock wake signal <NUM> while in this state (that is, suppresses or "squashes" any received clock wake signal <NUM>). In the illustrated embodiment, this arrangement is implemented using an AND gate <NUM> disposed between the upstream segment of the CLK_EN wire <NUM> and the input of the digital buffer <NUM>, whereby the AND gate <NUM> includes an inverted input to receive an inverted representation of the sleep signal <NUM>, an input coupled to the upstream segment of the CLK_EN wire <NUM>, and an output that serves as the input of the digital buffer <NUM> for the CLK_EN wire <NUM>. In other embodiments, a different logic implementation is used in accordance with the teachings provided herein.

The operation of the state machine <NUM> in controlling the operation of the node <NUM>-<NUM> is represented by the illustrated state diagram <NUM>, which includes four operational states: active state <NUM>, idle state <NUM>, clock suppression state <NUM>, and dormant state <NUM>. The state machine <NUM> monitors the CLK_EN wire <NUM> and the valid wire <NUM> as described above to detect the presence of clock wake signals <NUM> (CLK_EN) and data traffic passing through the node <NUM>-<NUM>. While there is active data traffic, the state machine <NUM> remains in the active state <NUM>, during which the sleep signal <NUM> is not asserted (or deasserted), and thus any received clock wake signals <NUM> are permitted to be forwarded by the repeater <NUM>. If a clock wake signal <NUM> is received without a following data packet, then the state machine <NUM> enters the idle state <NUM>. As with the active state <NUM>, in the idle state the sleep signal <NUM> is not asserted and thus allowing received clock wake signals <NUM> to be forwarded to the downstream node. After occurrence of a specified idle condition, such as after the lapse of a first specified duration in the idle state <NUM> (as measured via the idle timer <NUM> without receipt of any data traffic at the node <NUM>-<NUM>), the state machine <NUM> enters the clock suppression state <NUM>. While in the clock suppression state <NUM>, the sleep controller <NUM> actively suppresses any clock wake signals <NUM> received at the node <NUM>-<NUM> by asserting the sleep signal <NUM>, which in turn effectively disables digital buffer <NUM> on the CLK_EN wire <NUM>. This in turn prevents the repeater <NUM> from repeating any received clock wake signal <NUM> received at the input side of the node <NUM>-<NUM>.

The state machine <NUM> remains in the clock suppression state <NUM> for a second specified duration unless data traffic is received at the node <NUM>-<NUM> (as measured via the suppression timer <NUM>). This second specified duration, in one embodiment, is selected or otherwise specified to represent a duration expected to allow any errant clock wake signals <NUM> present in the ring transport <NUM> to reach the node <NUM>-<NUM> and subsequently be suppressed before entry into the dormant state <NUM> occurs. If data traffic is received while in the clock suppression state <NUM> and prior to lapse of the second specified duration, the state machine <NUM> returns to the active state. Otherwise, while in the dormant state <NUM>, the node <NUM>-<NUM> switches to a clock-gated state and the state machine <NUM> deasserts the sleep signal <NUM> so as to permit downstream propagation of any received clock wake signals <NUM> by the repeater <NUM>. If a clock wake signal <NUM> is received and followed by a data packet, then the state machine <NUM> returns to the active state <NUM>. If a clock wake signal <NUM> is received and no data packet follows, then the state machine <NUM> returns to the idle state <NUM>.

<FIG> illustrates a method <NUM> describing the idle-clock suppressing-dormant state transitions of the state machine <NUM> implemented by the sleep controller <NUM> in more detail in accordance with some embodiments. Note that while certain blocks are illustrated in a given order in <FIG>, the processes represented by these blocks can be performed concurrently or in a different order. Block <NUM> represents the state machine <NUM> entering the idle state <NUM> after detecting receipt of a clock wake signal <NUM> that is not followed by a data packet. In response to entry into the idle state <NUM>, at block <NUM> the state machine <NUM> resets the idle timer <NUM> to a value M representative of the first specified duration, which can be fixed or programmable and which is specified based on any of a variety of considerations, such as from modeling of an operation of the ring transport <NUM> or based on real-time feedback during actual operation of the ring transport <NUM>. The idle timer <NUM> then counts down from M with every cycle of the ring clock signal <NUM>. While the idle timer <NUM> has not elapsed, at block <NUM> the state machine <NUM> monitors for receipt of any data packets at the node <NUM>-<NUM>. If a data packet is received, then at block <NUM> the state machine <NUM> returns to the active state <NUM>. Otherwise, when M cycles have passed since entry into the idle state <NUM> (that is, the idle timer <NUM> has lapsed) as determined at block <NUM>, the state machine <NUM> enters the clock suppression state <NUM> at block <NUM>.

In response to entering the clock suppression state, at block <NUM> the state machine <NUM> resets the suppression timer <NUM> to a value N representative of the second specified duration, which is either fixed or programmable. In at least one embodiment, the value N is set as a time (measured in clock cycles) sufficient to allow all errant clock wake signals <NUM> present on the ring transport <NUM> to be suppressed at node <NUM>-<NUM>. To illustrate, if it takes <NUM> clock cycles for a clock wake signal <NUM> to complete a circuit around the ring transport <NUM>, then the value N could be set to a value slightly larger than <NUM>, such as <NUM> for example, so as to allow sufficient time for any given errant clock wake signal <NUM> on the ring transport <NUM> to reach the node <NUM>-<NUM> so that it can be suppressed. Once reset to value N, the suppression timer <NUM> counts down from N with each cycle of the ring clock signal <NUM>.

Further in response to entering the clock suppression state <NUM>, the state machine <NUM> asserts the sleep signal <NUM> at block <NUM>. Assertion of the sleep signal <NUM> in turn configures the digital buffer <NUM> on the CLK_EN wire <NUM> to refrain from repeating any received clock wake signal <NUM>, and thus squashing or otherwise suppressing any errant clock wake signals <NUM> received at the node <NUM>-<NUM> while in the clock suppression state <NUM>.

As represented by decision block <NUM>, the state machine <NUM> monitors for the lapse of the suppression timer <NUM> (that is, whether N clock cycles have passed since entering the clock suppression state <NUM>). If the suppression timer <NUM> has lapsed, then at block <NUM> the state machine <NUM> enters the dormant state <NUM> and deasserts the sleep signal <NUM>. With the sleep signal <NUM> deasserted in the dormant state <NUM>, the digital buffer <NUM> is activated and thus able to forward any clock wake signals <NUM> received from the upstream node <NUM> to the downstream node <NUM>. Accordingly, at block <NUM> the state machine <NUM> monitors for receipt of a data packet at the node <NUM>-<NUM> and at block <NUM> the state machine <NUM> monitors for receipt of a clock wake signal <NUM> without a following data packet. If a data packet is received at the node <NUM>-<NUM> while in the dormant state <NUM>, then the state machine <NUM> reverts to the active state <NUM> at block <NUM>. If a clock wake signal <NUM> without a following data packet is received at the node <NUM>-<NUM> while in the dormant state <NUM>, then the state machine reverts to the idle state <NUM> at block <NUM>.

Returning to block <NUM>, while the second specified period has not elapsed while in the clock suppression state <NUM>, the state machine <NUM> monitors for receipt of a data packet at block <NUM>. Recall that in the active, idle, and dormant states, there is no active clock wake signal suppression. As such, when a data packet is received at the node <NUM>-<NUM> in any of those states, the clock wake signal preceding the data packet is forwarded by the repeater <NUM> and then the received data packet is processed on the next clock cycle as usual. However, in the clock suppression state <NUM>, clock wake signals are suppressed at the node <NUM>-<NUM>. Accordingly, if a data packet is detected as received at the node <NUM>-<NUM> at block <NUM>, this means that the clock wake signal that preceded the data packet was suppressed, and thus the data packet cannot be immediately processed and transmitted downstream as there is no repeated clock wake signal proceeding it. Instead, the node <NUM>-<NUM> generates a new clock wake signal <NUM> to precede the repeated data packet toward the downstream node <NUM>-<NUM>.

Accordingly, in response to receipt of a data packet while in the clock suppression state <NUM>, the data packet is buffered in one of the dual buffers <NUM>, <NUM> of the skid buffer <NUM> at block <NUM>, the sleep signal <NUM> is deasserted so as to reactivate the tristate digital buffer <NUM> on the CLK_EN wire <NUM> at block <NUM>, and at block <NUM> the state machine <NUM> generates a clock wake signal <NUM> for transmission by the tristate digital buffer <NUM> to the downstream node <NUM>-<NUM> via the CLK_EN wire <NUM>. For the clock cycle following generation of the clock wake signal <NUM>, at block <NUM> the skid buffer outputs the buffered data packet on the data wires <NUM> and asserts the valid wire <NUM> so as to forward the data packet and valid signal downstream following the generated clock wake signal. Moreover, as there is a delay caused by having to recreate the suppressed clock wake signal <NUM> before the data packet can be repeated, it is possible that another data packet is received during this process. As such, the skid buffer <NUM> utilizes the other buffer to temporarily store this second received data packet until the first received packet has been transmitted, at which point the second data packet can be provided for forwarding to the next node <NUM>-<NUM> in the same manner, and so on.

In some embodiments, the apparatus and techniques described above are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the IC device <NUM> described above with reference to <FIG>. Electronic design automation (EDA) and computer aided design (CAD) software tools often are used in the design and fabrication of these IC devices. These design tools typically are represented as one or more software programs. The one or more software programs include code executable by a computer system to manipulate the computer system to operate on code representative of circuitry of one or more IC devices to perform at least a portion of a process to design or adapt a manufacturing system to fabricate the circuitry. This code includes instructions, data, or a combination of instructions and data. The software instructions representing a design tool or fabrication tool typically are stored in a computer readable storage medium accessible to the computing system. Likewise, the code representative of one or more phases of the design or fabrication of an IC device is either stored in and accessed from the same computer readable storage medium or a different computer readable storage medium.

A computer readable storage medium includes any non-transitory storage medium, or combination of non-transitory storage media, accessible by a computer system during use to provide instructions and/or data to the computer system. Such storage media include, but are not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-Ray disc), magnetic media (e.g., floppy disc, magnetic tape, or magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or Flash memory), or microelectromechanical systems (MEMS)-based storage media. The computer readable storage medium can be embedded in the computing system (e.g., system RAM or ROM), fixedly attached to the computing system (e.g., a magnetic hard drive), removably attached to the computing system (e.g., an optical disc or Universal Serial Bus (USB)-based Flash memory), or coupled to the computer system via a wired or wireless network (e.g., network accessible storage (NAS)).

In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer readable storage medium. The executable instructions stored on the non-transitory computer readable storage medium can be in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executable by one or more processors.

In accordance with one aspect, a method includes monitoring, at a node of a ring transport of an integrated circuit (IC) device, a wire used to transmit clock wake signals around the ring transport. The method further includes configuring the node into a clock suppression state for a first specified duration responsive to identifying an idle condition on the ring transport via the monitoring of the wire, wherein while in the clock suppression state the node suppresses further transmission of any clock wake signals received at the node. In some embodiments, the method further includes, at each node of a plurality of nodes of the ring transport, switching from a clock gated state to a clocked state responsive to receiving a clock wake signal at the node.

In accordance with another aspect, an IC device includes a ring transport having a plurality of nodes and a wire interconnect coupling the plurality of nodes in a ring, the wire interconnect including a wire configured to transmit clock wake signals around the ring transport. The ring transport further includes a sleep controller coupled to a select node of the plurality of nodes, wherein the sleep controller is to configure the select node into a clock suppression state for a first specified duration responsive to identifying an idle condition on the ring transport via monitoring of the wire, wherein while in the clock suppression state the node suppresses further transmission of any clock wake signals received at the select node. In some embodiments, each node of the plurality of nodes is configured to switch from a clock gated state to a clocked state responsive to receiving a clock wake signal at the node. Further, in some embodiments, the idle condition comprises a lapse of a second specified duration since a clock wake signal without a following data packet was received at the select node. Moreover, in some embodiments, the first specified duration is represented by a first specified number of clock cycles of a clock signal used to clock the ring transport, the first specified number of clock cycles having a corresponding duration at least equal to a duration needed for a clock wake signal to circle the ring transport, and the second specified duration is represented by a second specified number of clock cycles of the clock signal. Further, in some embodiments, the sleep controller is to configure the select node into a dormant state responsive to a lapse of the first specified duration and to an absence of any data traffic received at the select node while in the clock suppression state, wherein while in the dormant state the select node is permitted to forward clock wake signals received at the select node.

In accordance with yet another aspect, a device includes a ring transport configured to transport data packets among a plurality of nodes, each node selectively clocked by clock signal and each data packet preceded in the ring transport by a clock wake signal. A select node of the plurality of nodes is configured to, responsive to the ring transport being idle for a first specified duration, suppress any clock wake signal received at the select node during a second specified duration following the first specified duration.

Note that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device may not be required, and that one or more further activities can be performed, or elements included, in addition to those described. Still further, the order in which activities are listed is not necessarily the order in which the activities are performed.

Claim 1:
A method, comprising:
monitoring, at a node (<NUM>) of a ring transport (<NUM>) of an integrated circuit, IC, device (<NUM>), a wire (<NUM>) used to transmit clock wake signals (<NUM>) around the ring transport, the ring transport comprising a plurality of nodes (<NUM>) connected into a ring via a wire interconnect (<NUM>) comprising a plurality of wires; and
configuring the node (<NUM>) into a clock suppression state for a first specified duration responsive to identifying an idle condition on the ring transport (<NUM>) via the monitoring of the wire (<NUM>), wherein while in the clock suppression state the node suppresses further transmission of any clock wake signals received at the node, wherein the clock wake signals (<NUM>) comprise signals that precede a transmitted packet in the ring transport,
wherein the idle condition comprises a lapse of a second specified duration since a clock wake signal (<NUM>) was received at the node without a following data packet.