Patent Description:
Embodiments described herein generally include techniques to support multiple interconnect protocols for a single interconnect.

As computing systems are advancing, the components therein are becoming more complex. Thus, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth and latency requirements are met for optimal component operation. Furthermore, different market segments need different interconnect architectures and protocols to suit the market's needs. For example, these computing systems may provide various processing capabilities that require different add-in cards having physical resources. These add-in cards may be coupled with the baseboard and may require any number of different interconnect protocols. However, connector space on the baseboard may be limited, and a single connector typical supports a single interconnect protocol. Thus, embodiments may be directed to solving these and other problems.

<CIT>relates to point-to-point interconnects. For example, physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

<CIT> relates to techniques for Cross-Die Interface (CDI) snoop and/or Global Observation (GO) message ordering. For example, the order of a snoop message and a completion message are determined based at least on status of two bits. The snoop and completion messages are exchanged between a first integrated circuit die and a second integrated circuit die. The first integrated circuit die and the second integrated circuit die are coupled through a first interface and a second interface and the snoop message and the completion message are exchanged over at least one of the first interface and the second interface.

<CIT> relates to multi-protocol tunneling across a multi-protocol I/O interconnect of a computer apparatus. For example, a method for synchronizing time across the multi-protocol I/O interconnect includes providing a first local time of a first switch of a switching fabric of a multi-protocol interconnect to a second switch of the switching fabric, and adjusting a second local time of the second switch to the first local time.

The invention is generally directed to enabling multiple protocols on a single interconnect. More specifically the invention includes processing messages and data in accordance with an appropriate protocol based on the message type. A message for communication via an interconnect is detected by interface logic and circuitry. The interface logic and circuitry detects the message and determines a message type for the message. The interface logic and circuitry also determines an interconnect protocol of a plurality of interconnect protocols to communicate the message via the interconnect. More specifically, the interface logic and circuitry determines the interconnect protocol based on a message type, which may include a non-coherent message type, a coherent message type, a memory message type, and so forth.

The invention also includes providing the message to a multi-protocol multiplexer; the multi-protocol multiplexer causes communication of the message utilizing the interconnect protocol via the interconnect with the device. In embodiments, the multi-protocol multiplexer may determine whether resources are available for an interconnect specific queue at the destination device. If resources are available, the multi-protocol multiplexer may cause the message to be sent to the device via the interconnect. If resources are not available, the multi-protocol multiplexer may wait until resources are available and send the message.

These and other details will become more apparent in the following description.

Reference is now made to the drawings, wherein like reference numerals are used to refer to like elements throughout. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate a description thereof.

<FIG> illustrates an example of an operating environment <NUM> that may be representative of various embodiments. Operating environment <NUM> depicted in <FIG> illustrates a general overview of a host processor <NUM> which may be part of a system per some embodiments, such as a computer system, compute system, networking system, distributed system, and the like configured for multi-protocol support per some embodiments. In various instances, host processor <NUM> may be any type of computational element, such as but not limited to, a microprocessor, a processor, central processing unit, digital signal processing unit, dual-core processor, a quad-core processor, a multi-core processor, mobile device processor, desktop processor, single core processor, a system-on-chip (SoC) device, complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a field-programmable gate array (FPGA) circuit, application specific integrated circuit (ASIC) or any other type of processor or processing circuit on a single chip or integrated circuit. Host processor <NUM> may have a number of elements, including one or more cores 115a-n, interface logic <NUM>, memory logic <NUM>, and an interface <NUM> having a number of connectors <NUM>.

In the illustrated example, host processor <NUM> includes a plurality of cores 115a-n. However, embodiments are not limited in this manner, and host processor <NUM> may include any number of cores, including a single core. Moreover, the multiple core design can integrate different types of processor cores on the same integrated circuit (IC) die, (for instance, in a heterogeneous design). Thus, one or more cores 115a-n may be different from each other. In some instances, each core of a multiple core design may be the same (for instance, in a homogeneous design).

Cores 115a-n of host processor <NUM> can read and execute program instructions. The instructions are typically central processing unit (CPU) instructions (such as add, move data, and branch). The multiple core design enables the host processor <NUM> to execute or run multiple instructions at the same time, increasing overall speed for programs and applications. In some instances, cores 115a-n may be integrated onto a single integrated circuit die (known as a chip multiprocessor or CMP), or onto multiple dies in a single chip package. Also, host processor <NUM> with a multiple core design can be implemented as symmetrical or asymmetrical multiprocessors.

In some embodiments, host processor <NUM> includes an interface <NUM> and connectors <NUM>. Connectors <NUM> and interface <NUM> may provide physical connections to couple with other devices, such as interface components, memory, processing cards, networking interface components, accelerator cards, and so forth. Interface <NUM> and connectors <NUM> can include one or more wires, bumps, pins, or signal traces capable of communicating information and data via electrical signaling. In some instances, interface <NUM> and connectors <NUM> may be coupled with a physical slot capable of accepting processing cards. These processing cards typically provide additional processing and memory, which may be directed to a specific task, for instance, graphics processing, network processing, storage processing, interface processing, and the like. In some embodiments, interface <NUM> and connectors <NUM> may provide a common set of pins that support communication via a number of interconnect protocols. Note that in some embodiments, the interface <NUM> may be coupled with other devices in-die, e.g. on the same integrated chip, or off-die e.g. on different integrated chips or cards as discussed.

In some embodiments, interface <NUM> and connectors <NUM> are part of and enable an interconnect or logical link to send and receive data and messages. The data and messages communicated via the interconnect and the logical link include data, control messages, memory requests, memory responses, input/output (I/O) requests, I/O responses, and so forth.

Host processor <NUM> includes interface logic <NUM> to enable and cause communication of data and messages via interface <NUM> in accordance with one or more interconnect protocols. According to the invention, the interface logic <NUM> and interface <NUM> supports a single interconnect, link, or bus capable of dynamically processing data and messages in accordance with a plurality of interconnect protocols, such as a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Examples of a non-coherent interconnect protocol include Intel ® On-Chip Scalable Fabric (IOSF) protocol, peripheral component interconnect (PCI) protocol, peripheral component interconnect express (PCIe or PCI-E) protocol, Intel® Accelerator Link (IAL) input/output (I/O) IAL. io protocol, ARM® advanced extensible interface (AXI) protocol, AMD® Hypertransport® protocol, and so forth. Examples of a coherent interconnect protocol may include an intra-device interconnect (IDI) protocol, IAL cache (IAL. cache) protocol, Intel® UltraPath Interconnect® (UPI) protocol, Cache Coherent Interconnect for Accelerators® (CCIX) protocol, AMD® Coherent HyperTransport®, and so forth. Examples of a memory interconnect protocol may include scalable memory interconnect (SMI) protocol, SMI 3rd generation (SMI3), memory protocols, memory semantic protocols, IAL memory (IAL. mem) protocol, GenZ® protocol, and so forth.

The interface logic <NUM> is coupled to a multi-protocol multiplexer, as will be discussed in more detail in <FIG>, such that host processor <NUM> and components thereof may support multiple protocols for one or more coupled devices. In some embodiments, a device may require support for only one of the interconnect protocols, while other devices may require support for any combination of the interconnect protocols. For example, one class of devices may be considered producer-consumer devices and require support for non-coherent interconnect protocol communication, e.g. PCIe and IOSF. These devices may include a network accelerator, a cryptographic device, a compression device, and so forth. These devices also benefit from support for AiA instructions for basic user level work submission, work submission, flow control, and so forth. The non-coherent interconnect protocol may provide support for device discovery, device configuration, device error reporting, interrupts, dynamic memory addressing (DMA) data transfers, and so forth. In another example, a class of devices may be considered producer-consumer plus devices which may require support for support for device discovery, device configuration, device error reporting, interrupts, dynamic memory addressing (DMA) data transfers, as discussed above with respect to the producer-consumer devices. The producer-consumer plus devices may also require support for an ordering model, execution of atomic operations, and cache coherency. Thus, the interface logic <NUM> provides non-coherent interconnect protocol functionality, and coherent interconnect protocol functionality in a dynamic manner. Moreover, the interface logic <NUM> may provide the coherent interconnect protocol to support atomics and enable a device to issue coherent read and write requests, for example. These producer-consumer plus devices may include fabric interface devices and the like.

The interface logic <NUM> provides support for multiple interconnect protocols including a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnects protocol. One class of devices that may require these interconnect protocols may be software assisted device memory devices (SADM) which include devices with an attached memory, and the memory is managed with hardware cache coherence process. Moreover, the performance of the cache coherency process is managed via software or with software assistance. Examples of SADM include, but are not limited to discrete field programmable gate array (FPGA) devices, graphic devices, and so forth. In addition to the above-discussed functionality provided by the non-coherent and coherent interconnect protocols, these devices may include an attached memory and require support such that a processor can access the memory and cache coherency. A memory interconnects protocol may provide access and cache coherency support for the devices. Another class of devices that may require support for a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol may be autonomous device memory devices and giant cache devices such as dense computational offloading devices, general-purpose computing or graphics processing units (GPGPU), and so forth. These devices may be accelerators with attached memory and include usages where data placement is not practical, e.g. scheduling data movement of prohibitive due to the complexity of the data, or a data footprint is larger than the attached memory.

According to the invention, the interface logic <NUM> provides multiple protocols dynamically based on messages and data for communication between the host processor <NUM> and coupled device.

The interface logic <NUM> determines a message type for the message and determine which interconnect protocol to process the message. More specifically, the interface logic <NUM> detects a message to communicate via the interconnect. In embodiments, the message may have been generated by a core <NUM>-n or another I/O device and be for communication to a device coupled via the interface <NUM>. The interface logic <NUM> determines a message type for the message, such as a non-coherent message type, a coherent message type, and a memory message type. The interface logic <NUM> determines whether a message, e.g. a request, is an I/O request or a memory request for a coupled device based on a lookup in an address map. If an address associated with the message maps as an I/O request, the interface logic <NUM> processes the message utilizing a non-coherent interconnect protocol and send the message to a link controller and multiplexer as a non-coherent message for communication to the coupled device. The interface logic <NUM> determines an address associated with the message indicates the message is memory request based on a lookup in the address table. The interface logic <NUM> may process the message utilizing the memory interconnect protocol and send the message to the link controller and multiplexer for communication to the coupled device.

The interface logic <NUM> determines a message is a coherent message based on one or more cache coherency and memory access actions (read/write operations) performed. More specifically, the host processor <NUM> may receive a coherent message or request that is sourced by the coupled device. One or more of the cache coherency and memory access actions may be performed to process the message and based on these actions; the interface logic <NUM> may determine a message sent in response to the request may be a coherent message. The interface logic <NUM> processes the message in accordance with the coherent interconnect protocol and send the coherent message to the link controller and multiplexer to send to the coupled device. In some embodiments, the interface logic <NUM> may determine a message type of a message based on an address associated with the message, an action caused by the message, information within the message, e.g. an identifier, a source of the message, a destination of a message, and so forth. Note that message types may be determined for messages both sent and received from or by the host processor <NUM>.

In some embodiments, host processor <NUM> may include memory logic <NUM>, as discussed in more detail in <FIG>. Memory logic <NUM> may perform operations for a memory of host processor <NUM>, such as a dynamic random access memory (DRAM) that may be coupled to the host processor <NUM> or any other type of memory, which typically is not on the same die as the host processor <NUM>, for example. Memory logic <NUM> may enable the host processor <NUM> to read and write data to and from memory (not shown).

In some embodiments, the host processor <NUM> may include cache <NUM> and cache logic <NUM>, which may enable a coherency support for cache <NUM> usage of cores 115a-n of host processor <NUM>. The cache <NUM> may be in a hierarchical layout having a number of levels, such as a first level cache and a second level cache. In some instances, some amount of cache <NUM> may be implemented as part of each of the processor cores <NUM> themselves. Additional cache <NUM> may be shared among the cores <NUM> in a hierarchal format. Since there may be two or more processing elements or cores 115a-n working at the same time, it is possible that they simultaneously access the same location of a cache <NUM>. If one of the cores 115a-n changes data in a location, cache logic <NUM> may notify all the other cores 115a-n of changes to shared values in memory, for example.

<FIG> illustrates an example of an interconnect protocol stack <NUM> that may be representative of various embodiments. interconnect protocol stack <NUM> depicted in <FIG> illustrates an embodiment of an interconnect protocol stack <NUM>. In general, interconnect protocol stack <NUM> may include or represent interconnect protocols used by a multi-protocol system according to some embodiments, including, without limitation, a coherent interconnect protocol, a non-coherent interconnect protocol, and a memory interconnect protocol, and/or the like. Note that embodiments, may include a separate interconnect protocol stack <NUM> for each of the multiple interconnect protocols, each may be representative of interconnect protocol stack <NUM>. However, each protocol stack may conduct specific and/or unique processing based on the particular interconnect protocol.

Interconnect protocol stack <NUM> may include a number of layers, such as a transaction layer <NUM>, a link layer <NUM>, and a physical layer (PHY) <NUM>. In various embodiments, portions of interconnect protocol stack <NUM> may be implemented as part of interface logic <NUM>, interface <NUM>, connectors <NUM>, or any combination thereof. However, embodiments are not limited in this manner, and portions of interconnect protocol stack <NUM> may be implemented in different elements of host processor <NUM>.

In some embodiments, interconnect protocol stack <NUM> and interconnect protocols may communicate data between a coherent fabric <NUM> and a device. Coherent fabric <NUM> may connect and include cores <NUM>, memory logic <NUM>, memory, cache <NUM>, cache logic <NUM>, and so forth with interface logic <NUM>. Transaction layer <NUM> may handle data and action requests and messages. Transaction layer <NUM> may parse the action requests and messages and initiate the appropriate actions in the processor's memory system according to protocol specific rules, such as ordering rules. Transaction layer <NUM> may also process data and action requests which may include read and write instructions. Action requests may also include cache coherency actions for a memory interconnect protocol and/or coherent interconnect protocol, for example, and address translation actions for non-coherent interconnect protocol, for example. The messages processed by transaction layer <NUM> may include error messages, request messages, response messages, interrupts, and/or the like.

Transaction layer <NUM> may provide an interface between cores <NUM>, and interconnect architecture including at least portions of PHY layer <NUM>, which may include interface <NUM>, and connectors <NUM> coupled to another device. Transaction layer <NUM> may also communicate information between cores <NUM> and the processor's coherent fabric and another device via link layer <NUM> and PHY layer <NUM> in transaction layer packets (TLPs). As mentioned, this information may include memory reads, memory writes, input/output (I/O), I/O writes, messages, completion, and so forth.

Link layer <NUM>, also referred to as a data link layer may operate as an intermediate stage between transaction layer <NUM> and PHY <NUM>. In one embodiment, link layer <NUM> may provide a reliable mechanism for exchanging TLPs between two components in a link. Link layer <NUM> may append information, for instance, packet sequence identification, to the TLPs when sending data and may remove the information from packets when receiving data. Link layer <NUM> may also determine and append an error detection code (CRC) to the packet header/payload of the TLPs. Link layer <NUM> may send the modified TLPs to PHY <NUM> for transmission across a physical link, for example, interface <NUM> and connectors <NUM>, to an external device.

In one embodiment, interconnect protocol stack <NUM> may also include a PHY <NUM>, which may include a logical sub-block <NUM> and an electrical sub-block <NUM> to physically transmit a packet to an external device. In some embodiments, PHY <NUM> may include portions of interface logic <NUM>, interface <NUM>, and connectors <NUM> or pins.

In some instances, logical sub-block <NUM> may be divided into a media access control (MAC) sublayer and a physical coding sublayer (PCS). In some instances, the PHY Interface for PCI Express (PIPE), published by Intel® Corp. , defines the MAC/PCS functional partitioning and the interface between these two sub-layers. The PIPE specification also identifies the physical media attachment (PMA) layer, which includes the serializer/deserializer (SerDes) circuitry and other analog circuitry.

Logical sub-block <NUM> may also be responsible for the logical functions of PHY <NUM>. Logical sub-block <NUM> may include a buffer that may function either as a drift buffer or an elastic buffer. Further, logical sub-block <NUM> may include a data encoding section, which can encode data using a 128b/130b transmission code, where <NUM>-bit symbols are transmitted/received. In some embodiments, logical sub-block <NUM> includes a transmit section to prepare outgoing information for transmission by electrical sub-block <NUM>, and a receiver section to identify and prepare received information before passing it to link layer <NUM>. Electrical sub-block <NUM> includes a transmitter and a receiver to send and receive data. The transmitter is supplied by logical sub-block <NUM> with symbols and transmits onto an external device. The receiver is supplied with symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is supplied to logical sub-block <NUM>.

<FIG> illustrates an example of an operating environment <NUM> that may be representative of various embodiments. The operating environment <NUM> depicted in <FIG> may include a device <NUM> operative to provide processing and/or memory capabilities. For example, device <NUM> may be, an accelerator or processor device communicatively coupled to a host processor <NUM> via an interconnect <NUM>, which may be single interconnect, bus, trace, and so forth. The device <NUM> and host processor <NUM> communicate over link <NUM> to enable data and message to pass therebetween. The link <NUM> is operable to support multiple protocols and communication of data and messages via the multiple interconnect protocols. For example, the link <NUM> may support various interconnect protocols, including, without limitation, a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnects protocol. Non-limiting examples of supported interconnect protocols may include PCI, PCIe, USB, IDI, IOSF, SMI, SMI3, IAL. cache, and IAL. mem, and/or the like. For example, the link <NUM> may support a coherent interconnect protocol (for instance, IDI), a memory interconnect protocol (for instance, SMI3), and non-coherent interconnect protocol (for instance, IOSF).

In embodiments, the device <NUM> may include accelerator logic <NUM> including circuitry <NUM>. In some instances, the accelerator logic <NUM> and circuitry <NUM> may provide processing and memory capabilities. In some instances, the accelerator logic <NUM> and circuitry <NUM> may provide additional processing capabilities in conjunction with the processing capabilities provided by host processor <NUM>. Examples of device <NUM> may include producer-consumer devices, producer-consumer plus devices, software assisted device memory devices, autonomous device memory devices, and giant cache devices, as previously discussed. The accelerator logic <NUM> and circuitry <NUM> may provide the processing and memory capabilities based on the device. For example, the accelerator logic <NUM> and circuitry <NUM> may communicate using interconnects using, for example, a coherent interconnect protocol (for instance, IDI) for various functions, such as coherent requests and memory flows with host processor <NUM> via interface logic <NUM> and circuitry <NUM>. The interface logic <NUM> and circuitry <NUM> may determine an interconnect protocol based on the messages and data for communication. In another example, the accelerator logic <NUM> and circuitry <NUM> may include coherence logic that includes or accesses bias mode information. The accelerator logic <NUM> including coherence logic may communicate the access bias mode information and related messages and data with host processor <NUM> using a memory interconnect protocol (for instance, SMI3) via the interface logic <NUM> and circuitry <NUM>. The interface logic <NUM> and circuitry <NUM> may determine to utilize the memory interconnect protocol based on the data and messages for communication.

In some embodiments, the accelerator logic <NUM> and circuitry <NUM> may include and process instructions utilizing a non-coherent interconnect, such as a fabric-based protocol (for instance, IOSF) and/or a peripheral component interconnect express (PCIe or PCI-E) protocol. In various embodiments, a non-coherent interconnect protocol may be utilized for various functions, including, without limitation, discovery, register access (for instance, registers of device <NUM>), configuration, initialization, interrupts, direct memory access, and/or address translation services (ATS). Note that the device <NUM> may include various accelerator logic <NUM> and circuitry <NUM> to process information and may be based on the type of device, e.g. producer-consumer devices, producer-consumer plus devices, software assisted device memory devices, autonomous device memory devices, and giant cache devices. Moreover and as previously discussed, depending on the type of device, device <NUM> including the interface logic <NUM>, the circuitry <NUM>, the protocol queue(s) <NUM> and multi-protocol multiplexer <NUM> may communicate in accordance with one or more protocols, e.g. non-coherent, coherent, and memory interconnect protocols.

In various embodiments, host processor <NUM> may be similar to host processor <NUM>, as discussed in <FIG>, and include similar or the same circuitry to provide similar functionality. The host processor <NUM> may be operably coupled to host memory <NUM> and may include coherence logic (or coherence and cache logic) <NUM>, which may include a cache hierarchy and have a lower level cache (LLC). Coherence logic <NUM> may communicate using various interconnects with interface logic <NUM> including circuitry <NUM> and one or more cores <NUM>a-n. In some embodiments, the coherence logic <NUM> may enable communication via one or more of a coherent interconnect protocol, and a memory interconnect protocol. In some embodiments, the coherent LLC may include a combination of at least a portion of host memory <NUM> and accelerator memory <NUM>. Embodiments are not limited in this manner.

Host processor <NUM> may include bus logic <NUM>, which may be or may include PCIe logic. In various embodiments, bus logic <NUM> may communicate over interconnects using a non-coherent interconnect protocol (for instance, IOSF) and/or a peripheral component interconnect express (PCIe or PCI-E) protocol. In various embodiments, host processor <NUM> may include a plurality of cores 365a-n, each having a cache. In some embodiments, cores 365a-n may include Intel® Architecture (IA) cores. Each of cores 365a-n may communicate with coherence logic <NUM> via interconnects. In some embodiments, the interconnects coupled with the cores 365a-n and the coherence and cache logic <NUM> may support a coherent interconnect protocol (for instance, IDI). In various embodiments, the host processor may include a device <NUM> operable to communicate with bus logic <NUM> over an interconnect. In some embodiments, device <NUM> may include an I/O device, such as a PCIe I/O device.

The host processor <NUM><NUM> includes interface logic <NUM> and circuitry <NUM> to enable multi-protocol communication between the components of the host processor <NUM> and the device <NUM>. The interface logic <NUM> and circuitry <NUM> process and enable communication of messages and data between the host processor <NUM> and the device <NUM> in accordance with one or more interconnect protocols, e.g. a non-coherent interconnect protocol, a coherent interconnect, protocol, and a memory interconnect protocol, dynamically. In embodiments, the interface logic <NUM> and circuitry <NUM> may support a single interconnect, link, or bus capable of dynamically processing data and messages in accordance with the plurality of interconnect protocols.

The interface logic <NUM> is coupled to a multi-protocol multiplexer <NUM> having one or more protocol queues <NUM> to send and receive messages and data with device <NUM> including multi-protocol multiplexer <NUM> and also having one or more protocol queues <NUM>. Protocol queues <NUM> and <NUM> may be protocol specific. Thus, each interconnect protocol may be associated with a particular protocol queue. The interface logic <NUM> and circuitry <NUM> process messages and data received from the device <NUM> and sent to the device <NUM> utilizing the multi-protocol multiplexer <NUM>. For example, when sending a message, the interface logic <NUM> and circuitry <NUM> process the message in accordance with one of interconnect protocols based on the message. The interface logic <NUM> and circuitry <NUM> send the message to the multi-protocol multiplexer <NUM> and a link controller. The multi-protocol multiplexer <NUM> or arbitrator may store the message in a protocol queue <NUM>, which may be protocol specific. The multi-protocol multiplexer <NUM> and link controller may determine when to send the message to the device <NUM> based on resource availability in protocol specific protocol queues of protocol queues <NUM> at the multi-protocol multiplexer <NUM> at device <NUM>. When receiving a message, the multi-protocol multiplexer <NUM> may place the message in a protocol-specific queue of queues <NUM> based on the message. The interface logic <NUM> and circuitry <NUM> may process the message in accordance with one of the interconnect protocols.

According to the invention, the interface logic <NUM> and circuitry <NUM> processes the messages and data to and from device <NUM> dynamically. For example, the interface logic <NUM> and circuitry <NUM> determine a message type for each message and determine which interconnect protocol of a plurality of interconnect protocols to process each of the messages. Different interconnect protocols may be utilized to process the messages.

The interface logic <NUM> detects a message to communicate via the interconnect <NUM>. In embodiments, the message may have been generated by a core <NUM> or another I/O device <NUM> and be for communication to a device <NUM>. The interface logic <NUM> determines a message type for the message, such as a non-coherent message type, a coherent message type, and a memory message type. The interface logic <NUM> determines whether a message, e.g. a request, is an I/O request or a memory request for a coupled device based on a lookup in an address map. If an address associated with the message maps as an I/O request, the interface logic <NUM> processes the message utilizing a non-coherent interconnect protocol and send the message to a link controller and the multi-protocol multiplexer <NUM> as a non-coherent message for communication to the coupled device. The multi-protocol <NUM> may store the message in an interconnect specific queue of protocol queues <NUM> and cause the message to be sent to device <NUM> when resources are available at device <NUM>.

The interface logic <NUM> determines an address associated with the message indicates the message is memory request based on a lookup in the address table. The interface logic <NUM> <NUM> processes the message utilizing the memory interconnect protocol and send the message to the link controller and multi-protocol multiplexer <NUM> for communication to the coupled device <NUM>. The multi-protocol multiplexer <NUM> may store the message an interconnect protocol-specific queue of protocol queues <NUM> and cause the message to be sent to device <NUM> when resources are available at device <NUM>.

The interface logic <NUM> determines a message is a coherent message based on one or more cache coherency and memory access actions performed. More specifically, the host processor <NUM> may receive a coherent message or request that is sourced by the coupled device <NUM>. One or more of the cache coherency and memory access actions may be performed to process the message and based on these actions; the interface logic <NUM> may determine a message sent in response to the request may be a coherent message. The interface logic <NUM> processes the message in accordance with the coherent interconnect protocol and send the coherent message to the link controller and multi-protocol multiplexer <NUM> to send to the coupled device <NUM>. The multi-protocol multiplexer <NUM> may store the message in an interconnect protocol-specific queue of queues <NUM> and cause the message to be sent to device <NUM> when resources are available at device <NUM>. Embodiments are not limited in this manner.

In some embodiments, the interface logic <NUM> may determine a message type of a message based on an address associated with the message, an action caused by the message, information within the message, e.g. an identifier, a source of the message, a destination of a message, and so forth. The interface logic <NUM> may process received messages based on the determination and send the message to the appropriate component of host processor <NUM> for further processing. The interface logic <NUM> may process a message to be sent to device <NUM> based on the determination and send the message to a link controller (not shown) and multi-protocol multiplexer <NUM> for further processing. The message types may be determined for messages both sent and received from or by the host processor <NUM>.

<FIG> illustrates a first logic flow diagram <NUM> for processing a message and data to send to another device. Although the logic flow diagram <NUM> illustrates certain operations are occurring in a particular order, embodiments are not limited in this manner. Some operations may occur before or after other operations, and some may occur in parallel. Moreover, the logic flow <NUM> may be representative of some or all the operations executed by one or more embodiments described herein.

At block <NUM>, embodiments include detecting a message or data to send to a device coupled via a interconnect. The message or data may be generated by a core, an I/O device, or a device coupled via a bus or trace. The message or data may be destined for another coupled device via an interconnect, such as an accelerator device. At block <NUM>, the logic flow includes determining a message type for the message. This includes determining a message type, such as a non-coherent message type, a coherent message type, and a memory message type. The determination is based on the message, information associated with the message optionally on actions/operations caused by the message, and so forth. At block <NUM>, the logic flow <NUM> includes determining an interconnect protocol to process the message based on the message type. The invention includes determining to process the message utilizing one of a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol based on the message. A non-coherent message type may be processed via non-coherent interconnect protocol, a coherent message type may be processed via the coherent interconnect protocol, and a memory message type may be processed via the memory interconnect protocol, for example.

At block <NUM>, the logic flow <NUM> includes sending the message to a link controller and a multi-protocol multiplexer to send to a coupled device. More specifically, interface logic and circuitry processes the message in accordance with the determined interconnect protocol and send the message to the link controller and multi-protocol multiplexer, which may determine when to send the message to a coupled device. For example and at decision block <NUM>, the multiplexer or arbitrator may determine whether resources are available in a interconnect protocol specific are available to send the message. If not, the logic flow <NUM> may wait until resources are available. If resources are available at block <NUM>, the logic flow <NUM> may include sending the message to a coupled device via an interconnect at block <NUM>.

<FIG> illustrates a first logic flow diagram <NUM> for processing a message and data received by a host processor. Although the logic flow diagram <NUM> illustrates certain operations are occurring in a particular order, some operations may occur before or after other operations, and some may occur in parallel. Moreover, the logic flow <NUM> may be representative of some or all the operations executed by one or more embodiments described herein.

At block <NUM>, embodiments include receiving and detecting a message or data to communicate via an interconnect. The message or data may be generated by a coupled device, such as an accelerator device. The message or data may be stored in interconnect protocol-specific protocol queue, and at block <NUM>, the logic flow may include interface logic processing the message or data. Further and at block <NUM>, the logic flow may include determining a message type of the message. The invention includes determining a message type, such as a non-coherent message type, a coherent message type, and a memory message type. The determination is based on the message, information (address) associated with the message, optionally on actions/operations caused by the message, and so forth. At block <NUM>, the logic flow <NUM> includes include determining an interconnect protocol to process the message based on the message type. This includes determining to process the message utilizing one of a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol based on the message. A non-coherent message type may be processed via non-coherent interconnect protocol, a coherent message type may be processed via the coherent interconnect protocol, and a memory message type may be processed via the memory interconnect protocol, for example. Embodiments are not limited in this manner.

At block <NUM>, the logic flow <NUM> may include processing the message or data in accordance with the interconnect protocol. More specifically, interface logic and circuitry may process the message in accordance with the determined interconnect protocol. At block <NUM>, the logic flow <NUM> may include sending the message or data to the appropriate destination, e.g. a core, a cache, an I/O device, and so forth.

<FIG> illustrates a first logic flow diagram <NUM> for processing a message and data. Although the logic flow diagram <NUM> illustrates certain operations are occurring in a particular order, some operations may occur before or after other operations, and some may occur in parallel. Moreover, the logic flow <NUM> may be representative of some or all the operations executed by one or more embodiments described herein.

The logic flow <NUM> includes detecting a message to communicate via the interconnect at block <NUM>. For example, interface logic and circuitry may detect a message to send via an interconnect to a coupled device. At block <NUM>, the logic flow includes determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message. The interconnect protocol is determined based on a message type, which includes a non-coherent message type, a coherent message type, a memory message type. Embodiments are not limited in this manner.

At block <NUM>, the logic flow <NUM> includes : providing the message to the multi-protocol multiplexer, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device. In embodiments, the multi-protocol multiplexer may determine whether resources are available for an interconnect specific protocol queue at the destination device. If resources are available, the multi-protocol multiplexer may cause the message to be sent to the device via the interconnect. If resources are not available, the multi-protocol multiplexer may wait until resources are available and send the message. Embodiments are not limited in this manner.

<FIG> illustrates an example of a storage medium <NUM>. Storage medium <NUM> may comprise an article of manufacture. In some examples, storage medium <NUM> may include any non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. Storage medium <NUM> may store various types of computer-executable instructions, such as instructions to implement logic flows <NUM>, <NUM>, and <NUM>.

Examples of a computer readable or machine readable storage medium may include any tangible media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like.

<FIG> illustrates an embodiment of an exemplary computing architecture <NUM> suitable for implementing various embodiments as previously described. In various embodiments, the computing architecture <NUM> may comprise or be implemented as part of an electronic device. In some embodiments, the computing architecture <NUM> may be representative, for example, of apparatuses and devices illustrated in <FIG>.

As used in this application, the terms "system" and "component" and "module" are intended to refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution, examples of which are provided by the exemplary computing architecture <NUM>. For example, a component can be, but is not limited to being, a process running on a processor, a processor, a hard disk drive, multiple storage drives (of optical and/or magnetic storage medium), an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution, and a component can be localized on one computer and/or distributed between two or more computers. Further, components may be communicatively coupled to each other by various types of communications media to coordinate operations. The coordination may involve the uni-directional or bi-directional exchange of information. For instance, the components may communicate information in the form of signals communicated over the communications media. The information can be implemented as signals allocated to various signal lines. In such allocations, each message is a signal. Further embodiments, however, may alternatively employ data messages. Such data messages may be sent across various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.

As shown in <FIG>, the computing architecture <NUM> comprises a processing unit <NUM>, a system memory <NUM> and a system bus <NUM>. The processing unit <NUM> can be any of various commercially available processors, including without limitation an AMD® Athlon®, Duron® and Opteron® processors; ARM® application, embedded and secure processors; IBM® and Motorola@ DragonBall® and PowerPC® processors; IBM and Sony® Cell processors; Intel® Celeron®, Core (<NUM>) Duo®, Itanium®, Pentium®, Xeon®, and XScale® processors; and similar processors. Dual microprocessors, multi-core processors, and other multi processor architectures may also be employed as the processing unit <NUM>.

The computer <NUM> may include various types of computer-readable storage media in the form of one or more lower speed memory units, including an internal (or external) hard disk drive (HDD) <NUM>, a magnetic floppy disk drive (FDD) <NUM> to read from or write to a removable magnetic disk <NUM>, and an optical disk drive <NUM> to read from or write to a removable optical disk <NUM> (e.g., a CD-ROM or DVD). The HDD <NUM>, FDD <NUM> and optical disk drive <NUM> can be connected to the system bus <NUM> by a HDD interface <NUM>, an FDD interface <NUM> and an optical drive interface <NUM>, respectively. The HDD interface <NUM> for external drive implementations can include at least one or both of Universal Serial Bus (USB) and IEEE <NUM> interface technologies.

The drives and associated computer-readable media provide volatile and/or nonvolatile storage of data, data structures, computer-executable instructions, and so forth. For example, a number of program modules can be stored in the drives and memory units <NUM>, <NUM>, including an operating system <NUM>, one or more application programs <NUM>, other program modules <NUM>, and program data <NUM>. In one embodiment, the one or more application programs <NUM>, other program modules <NUM>, and program data <NUM> can include, for example, the various applications and/or components systems <NUM>, <NUM>, and <NUM>.

A user can enter commands and information into the computer <NUM> through one or more wire/wireless input devices, for example, a keyboard <NUM> and a pointing device, such as a mouse <NUM>. Other input devices may include microphones, infra-red (IR) remote controls, radiofrequency (RF) remote controls, game pads, stylus pens, card readers, dongles, finger print readers, gloves, graphics tablets, joysticks, keyboards, retina readers, touch screens (e.g., capacitive, resistive, etc.), trackballs, trackpads, sensors, styluses, and the like. These and other input devices are often connected to the processing unit <NUM> through an input device interface <NUM> that is coupled to the system bus <NUM>, but can be connected by other interfaces such as a parallel port, IEEE <NUM> serial port, a game port, a USB port, an IR interface, and so forth.

When used in a WAN networking environment, the computer <NUM> can include a modem <NUM>, or is connected to a communications server on the WAN <NUM>, or has other means for establishing communications over the WAN <NUM>, such as by way of the Internet. The modem <NUM>, which can be internal or external and a wire and/or wireless device, connects to the system bus <NUM> via the input device interface <NUM>. In a networked environment, program modules depicted relative to the computer <NUM>, or portions thereof, can be stored in the remote memory/storage device <NUM>. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between the computers can be used.

The computer <NUM> is operable to communicate with wire and wireless devices or entities using the IEEE <NUM> family of standards, such as wireless devices operatively disposed in wireless communication (e.g., IEEE <NUM> over-the-air modulation techniques). This includes at least Wi-Fi (or Wireless Fidelity), WiMax, and Bluetooth™ wireless technologies, among others. Thus, the communication can be a predefined structure as with a conventional network or simply an ad hoc communication between at least two devices. Wi-Fi networks use radio technologies called IEEE <NUM>. 11x (a, b, g, n, etc.) to provide secure, reliable, fast wireless connectivity. A Wi-Fi network can be used to connect computers to each other, to the Internet, and to wire networks (which use IEEE <NUM>-related media and functions).

Some embodiments may be implemented, for example, using a machine-readable medium or article which may store an instruction or a set of instructions that, if executed by a machine, may cause the machine to perform a method and/or operations in accordance with the embodiments. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and/or software. The machine-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disk Read Only Memory (CD-ROM), Compact Disk Recordable (CD-R), Compact Disk Rewriteable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of Digital Versatile Disk (DVD), a tape, a cassette, or the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

Claim 1:
An apparatus comprising:
an interface logic (<NUM>) configured to determine a message type for a message to be communicated via a link (<NUM>) operable to support the plurality of interconnect protocols and determine one of the plurality of interconnect protocols to process the message; and
a multi-protocol multiplexer (<NUM>) coupled to the interface logic (<NUM>), wherein the multi-protocol multiplexer (<NUM>) is configured to communicate the message via the link (<NUM>);
wherein:
the interface logic (<NUM>) is configured to determine a first interconnect protocol of the plurality of interconnect protocols to process the message, the first interconnect protocol comprising a non-coherent protocol comprising a Peripheral Component Interconnect Express protocol;
the interface logic (<NUM>) is configured to determine a second interconnect protocol of the plurality of interconnect protocols to process the message, the second interconnect protocol comprising a coherent protocol; and
the interface logic (<NUM>) is configured to determine a third interconnect protocol of the plurality of interconnect protocols to process the message, the third interconnect protocol comprising a memory interconnect protocol, and
wherein the message type is determined based on information associated with the message.