Patent Description:
High-density memory arrays, e.g. Magnetic Random Access Memory (MRAM) arrays can suffer from the so-called sneak path problem. This problem arises from cross-talk interference between adjacent memory cells caused by a sneak path current, e.g. between a read-out cell and a neighboring cell. This can result in misinterpretation of the read-out signal of the read-out cell.

Selector devices can be used to protect the read-out signals. In particular, the sneak path problem can be mitigated by inserting selector devices next to the memory cells. The selector devices provide a threshold (diode behavior) for device selection based on word-line and bit-line (source line) voltage.

In Spin-Torque-Transfer (STT)-MRAM array, for instance, the selector devices should be bipolar (a write operation needs current in an opposite direction than a read operation), i.e., there is need for bipolar diodes with a threshold behavior in opposite directions. In particular, bipolar, highly non-linear, selector devices should be inserted next to the memory cells.

One candidate for such selector devices is a double-sided Indium-Gallium-Zinc-Oxide (IGZO) Schottky diode, as it is illustrated in <FIG> next to a memory element (forming a memory cell) of a memory array. In particular, <FIG> shows a selector device <NUM>, which is formed by a top electrode <NUM> and a bottom electrode <NUM> connected by an IGZO channel <NUM>. The selector device <NUM> is connected to a Magnetic Tunnel Junction (MTJ) memory element comprising an MTJ top electrode <NUM>, an MTJ <NUM>, and a MTJ bottom electrode <NUM>.

The selector device requires both contacts of the vertical IGZO channel <NUM> to be of the Schottky type, i.e. a Schottky interface needs to be formed between the IGZO <NUM> and the top electrode <NUM>, as well as between the IGZO <NUM> and the bottom electrode <NUM>. However, it is difficult to obtain a Schottky contact at the top interface of the IGZO channel <NUM>, i.e. the interface to the top electrode <NUM>, because a plasma-assisted process (e.g. Physical Vapor Deposition (PVD) that is typically involved in the deposition of the top electrode <NUM>, damages the IGZO <NUM>. Thereby, defects are created that make the contact of the IGZO <NUM> to the top electrode <NUM> Ohmic instead of Schottky. This leads to the sneak path problem described above.

Attempts have been made to reduce the power of the plasma, which is involved in the deposition of the top electrode <NUM>, but that attempt was still not sufficient to obtain a good Schottky contact between the IGZO <NUM> and the top electrode <NUM>.

<NPL>, discloses a high-performance a-IGZO thin film diode as selector for cross-point memory application.

<NPL>, discloses gigahertz operation of a-IGZO Schottky diodes.

<CIT> discloses an MRAM cell including a magnetic tunneling junction.

<CIT> discloses a two-terminal switching element having a bidirectional switching characteristic, a resistive memory cross-point array including the same, and methods for manufacturing the two-terminal switching element and the cross-point resistive memory array.

<NPL> discloses high performance Schottky diodes based on indium-gallium-zinc-oxide.

<NPL> discloses an optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional double- sided Schottky selector for high density RRAM arrays.

In view of the above, embodiments of the present invention aim to provide an improved solution to the sneak path problem. An objective is to provide a selector device and an integration flow for fabricating the selector device, which results in a bipolar selector device having good Schottky contacts. The selector device comprises a double-sided Schottky diode. To this end, defects that make the contacts Ohmic instead of Schottky should not be created. The selector device should in particular be based on a semiconductor material comprising a metal oxide material, like IGZO.

The objective is achieved by the embodiments of the invention provided in the enclosed independent claims. Advantageous implementations of these embodiments are defined in the dependent claims.

A first aspect of the invention provides a method for forming a selector device for a memory array, the method comprising: forming a first electrode layer, wherein the first electrode layer is embedded in an oxide, forming a second electrode layer above the first electrode layer, wherein the second electrode layer is separated from the first electrode layer by the oxide, forming an opening in the second electrode layer and in the oxide, wherein forming the opening exposes a part of the top surface of the first electrode layer, and depositing a semiconductor material, such that it fills the opening and forms a semiconductor layer on the top surface of the second electrode layer, wherein the semiconductor material contacts the first electrode layer and the second electrode layer, wherein the semiconductor material comprises a metal oxide material or amorphous silicon, and wherein the first electrode layer, the semiconductor material, and the second electrode layer form a double-sided Schottky diode.

The method of the first aspect results in a selector device. In particular, the way in which the semiconductor material is formed, leads to Schottky interfaces between this semiconductor material and the first and second electrode layer, respectively.

For forming the opening, for example, a trench may be formed, e.g. etched, through the second electrode layer and the oxide onto the top surface of the first electrode layer, such that the trench exposes a part of the top surface of the first electrode layer. Alternatively, an aperture may first be formed in the second electrode layer, and the second electrode layer can then be used as a hard mask for an oxide etch through the aperture, which lands on the first electrode layer. Alternatively, the second electrode layer could be patterned into a perforated shape, e.g. with a Damascene process, and can then be used as a hard mask for an oxide etch, which lands on the first electrode layer.

In an implementation of the method, the bottom surface of the first electrode layer is electrically connected to a memory element of the memory array.

Thus, the selector device can function in the memory array to mitigate the sneak path problem.

In an implementation of the method, the method further comprises patterning the semiconductor layer into a semiconductor patch arranged on the top surface of the second electrode layer.

In an implementation of the method, the method further comprises forming a dielectric layer around the semiconductor patch, and forming a metal layer, in particular forming a tungsten layer, around the dielectric layer, wherein the metal layer contacts the top surface of the second electrode layer.

This allows forming the metal layer wrapped around the top of the semiconductor patch (remainder of the patterned semiconductor layer), but isolated by the dielectric layer, while the metal layer connects directly to the second electrode layer to ensure electrical connectivity. The metal layer may provide connection to a BEOL structure.

In an implementation of the method, the method further comprises encapsulating the semiconductor patch with the dielectric layer, anisotropically etching the dielectric layer, such that a part of the top surface of the second electrode layer is exposed without exposing the encapsulated semiconductor patch, further encapsulating the encapsulated semiconductor patch with the metal layer, such that the metal layer contacts the exposed part of the top surface of the second electrode layer.

In an implementation of the method, the dielectric layer is an aluminum oxide layer.

In an implementation of the method, the method further comprises forming a BEOL structure above the metal layer, wherein the BEOL structure is electrically connected to the metal layer.

A second aspect of the invention provides a selector device for a memory array, the selector device comprising:a first electrode layer embedded in an oxide ,a second electrode layer arranged above the first electrode layer and separated from the first electrode layer by the oxide,a semiconductor material forming a semiconductor layer on the top surface of the second electrode layer, and extending through the second electrode layer and the oxide onto the top surface of the first electrode layer, wherein the semiconductor material contacts the first electrode layer and the second electrode layer, wherein the semiconductor material comprises a metal oxide material or amorphous silicon, wherein the first electrode layer, the semiconductor material, and the second electrode layer form a double-sided Schottky diode, and wherein the selector device is formed using the method according to the first aspect.

With the selector device of the second aspect, a double-sided Schottky barrier is obtained, which is necessary to counter the sneak path problem. In particular, a Schottky contact/interface is formed between the semiconductor material and the first electrode layer, as well as between the semiconductor material and the second electrode layer. Due to the arrangement of the semiconductor material and how it contacts the first and second electrode layer, respectively, any defects that are created do not impact the Schottky interfaces. This is, because any defects that are created are remote from the Schottky interfaces. Thus, the selector device of the second aspect provides an improved solution to the sneak path problem.

In an implementation of the selector device, the semiconductor material comprising the metal oxide material comprises indium gallium zinc oxide or indium tin oxide.

These materials form particularly good Schottky contacts, and therefore improve the selector device further.

The selector device provides a bipolar threshold (diode behavior), which is well suitable for device selection based on word-line and bit-line (source line) voltage in a memory array.

In an implementation of the selector device, a first Schottky interface is formed between the semiconductor material extending through the oxide and the top surface of the first electrode layer, and a second Schottky interface is formed between the bottom surface of the semiconductor layer and the top surface of the second electrode layer.

In an implementation of the selector device, the first electrode layer and/or the second electrode layer comprises platinum, palladium, and/or gold.

These materials have beneficially a work function in a range that provides a preferable Schottky barrier height, and the desired off-current needed for selector activity in, for example, an MRAM array. Palladium may beneficially form an interfacial palladium oxide, e.g. after ozone treatment, which is oxide-rich and thus reduces surface defect concentration of the semiconductor material.

In an implementation of the selector device, the selector device further comprises a dielectric layer, in particular an aluminum oxide layer, formed on the top and on the sides of the semiconductor layer.

In an implementation of the selector device, the selector device further comprises a metal layer, in particular a tungsten layer, formed on the top and on the sides of the dielectric layer, wherein the metal layer directly contacts the top surface of the second electrode layer.

The implementation forms allow forming the metal layer wrapped around the top of the semiconductor layer, but isolated by the dielectric layer, while the metal layer connects directly to the second electrode layer to ensure electrical connectivity.

A selector device fabricated using the method of the first aspect can be distinguished from conventional selector devices, in particular, in the resulting semiconductor material connecting the first electrode layer and the second electrode layer.

A third aspect of the invention provides a memory device, comprising: a memory array including a plurality of memory elements, and a plurality of selector devices, wherein each selector device is according to the second aspect or any implementation thereof, wherein each selector device is electrically connected to one of the memory elements.

The memory device of the third aspect enjoys the advantages of the selector device of the second aspect described above. In particular, in the memory array of the memory device, the sneak path problem is solved.

The above described aspects and implementations are explained in the following description of embodiments with respect to the enclosed drawings:.

<FIG> shows a selector device <NUM> according to an embodiment of the invention in a cross-sectional view. The selector device <NUM> is suitable for a memory array, i.e. it can be inserted into the memory array, in particular, can be electrically connected to one of the memory elements (forming the memory cells) of the memory array. In the memory array, a plurality of the selector devices <NUM> can solve the sneak path problem.

The selector device <NUM> comprises a first (bottom) electrode layer <NUM>, which is embedded in an oxide <NUM>, e.g., a silicon dioxide. The first electrode layer <NUM> may be made of, or may comprise, platinum, palladium, and/or gold.

Further, the selector device <NUM> comprises a second (top) electrode layer <NUM>, which is arranged above the first electrode layer <NUM>, and is separated from the first electrode <NUM> layer by the oxide <NUM>, in particular, by a part of the oxide <NUM>. The second electrode layer <NUM> may be made of, or may comprise, platinum, palladium, and/or gold.

Notably, the term "above" may be related to a stacking direction of the layers of the selector device <NUM>, which is in <FIG> from the bottom to the top of the figure. The stacking direction may correspond to a fabrication direction of the layers. The terms "beneath", or "top" or "bottom", or similar terms, are likewise related to this stacking direction. The second electrode layer <NUM> is specifically distanced from the first electrode layer by a certain thickness/part of the oxide <NUM>.

The selector device further comprises a semiconductor material <NUM>, which may be, or may comprise, a metal oxide material. For example, it may be, or may comprise, IGZO, or ITO, or it may be, or may comprise, amorphous silicon or a similar material. The semiconductor material <NUM> forms a semiconductor layer 14a on the top surface of the second electrode layer <NUM>. Further, the semiconductor material <NUM> extends through, e.g. forms a semiconductor channel 14b through, the second electrode layer <NUM> and the oxide <NUM>, respectively, which lands on the top surface of the first electrode layer <NUM>. The semiconductor layer 14a and the semiconductor channel 14b may be formed integrally. The semiconductor material <NUM> contacts the second electrode layer <NUM>, in particular, the semiconductor layer 14a contacts a top surface of the second electrode layer <NUM>. Further, the semiconductor material <NUM> contacts the first electrode layer <NUM>, in particular, the semiconductor channel 14b contacts the top surface of the first electrode layer <NUM>.

Thereby, multiple Schottky interfaces are formed as indicated in <FIG>. A first Schottky interface is formed between the semiconductor material <NUM>, which extends through the oxide <NUM>, and the top surface of the first electrode layer <NUM>. One or more second Schottky interfaces are formed between the bottom surface of the semiconductor layer 14a and the top surface of the second electrode layer <NUM>. Thus, the first electrode layer <NUM>, the semiconductor material <NUM>, and the second electrode layer <NUM> form a double-sided Schottky diode.

The formation of these Schottky interface between the semiconductor material <NUM> and, respectively, the first electrode layer <NUM> and the second electrode layer <NUM>, is an important aspect. The materials of the first and second electrode layer <NUM> and <NUM> should thus, respectively, be selected such that the work function of the material is in a range that results in a Schottky barrier having a desired height and a desired off-current needed for selector activity in a memory array. Thus, platinum, palladium, and/or gold are preferred materials for the first and/or the second electrode layers <NUM> and <NUM>, in particular, in combination with IGZO as the semiconductor material <NUM>. Furthermore, palladium can form an interfacial palladium oxide, e.g. after ozone treatment, which is oxide-rich, and may hence advantageously reduce the surface defect concentration of the IGZO.

It is also illustrated in <FIG> that any defects that are formed in the semiconductor material <NUM>, are not formed close to or at the first Schottky interface between the semiconductor layer 14a and the second electrode layer <NUM>. Thus, this interface is not endangered to become Ohmic during fabrication of the selector device <NUM>.

<FIG> shows the selector device <NUM> according to an embodiment of the invention, which builds on the embodiment shown in <FIG>. In particular, the selector device <NUM> of <FIG> comprises further, optional features, and is exemplarily illustrated as provided in a memory array. Same features in <FIG> and <FIG> are labelled with the same reference signs, and function likewise.

The selector device <NUM> shown in <FIG> further comprises a dielectric layer <NUM>, which is formed on the top and on the sides of the semiconductor layer 14a. The dielectric layer <NUM> may thus be wrapped around the semiconductor layer 14a. The dielectric layer <NUM> may be, or may comprise, an aluminum oxide layer or silicon dioxide. These oxides do not tend to absorb oxygen from the semiconductor material, e.g. IGZO, in contrast to other dielectrics like silicon nitride. Absorption of oxygen would cause oxygen vacancies in the semiconductor material, which would induce traps. Further, the selector device <NUM> comprises a metal layer <NUM>, which is formed on the top and on the sides of the dielectriclayer <NUM>. The metal layer <NUM> may thus be wrapped around the dielectriclayer <NUM>. The metal layer <NUM> is formed such that it contacts the top surface of the second electrode layer <NUM>. The metal layer <NUM> may be, or may comprise, tungsten.

Further, the selector device <NUM> of <FIG> is connected to a memory element of the memory array, into which it is inserted, in particular it is connected to a top electrode <NUM> of the memory element. The memory element may be a MTJ memory element and may form a bit-cell of the memory array. The top electrode <NUM> is notably not a part of the selector device <NUM>. The selector device <NUM> and the memory element may form a memory device. A memory device according to an embodiment of the invention may also be formed by the memory array, which includes a plurality of memory elements, and a plurality of selector devices <NUM>, wherein each selector device <NUM> is connected to one of the memory elements as shown in <FIG>. This memory device does not suffer significantly from the sneak path problem.

For fabricating the selector device <NUM>, which is shown in <FIG>, the top (second) electrode layer <NUM> may be deposited before the semiconductor material <NUM> (e.g. the IGZO). The semiconductor material channel 14b of the selector device <NUM> may then be formed by first etching through the second electrode layer <NUM> and the oxide <NUM>, which separates the second electrode layer <NUM> from the bottom (first) electrode layer <NUM>. Second, by depositing the semiconductor material <NUM> to fill the etched opening or trench, thereby creating a contact of the semiconductor material <NUM> to both the second electrode layer <NUM> and the first electrode layer <NUM>.

The dielectriclayer <NUM> may then be deposited on top of the semiconductor material <NUM>, hence, potentially creating defects at the interface of semiconductor material <NUM> and dielectriclayer <NUM>. However, such defects have no impact on the electrical performance of the selector device <NUM>, because they are not located in the path of the current, or near the Schottky interface between the second electrode layer <NUM> and the semiconductor material <NUM>.

A connection to the upper levels of the BEOL may be obtained. For instance, by further using an etch stop layer (e.g., Al2O3) and an anisotropic opening etch, which may expose the first electrode layer <NUM> without reaching the top of the semiconductor layer 14a. This can prevent that a contact between the BEOL and the semiconductor material <NUM> becomes Ohmic.

In the selector device <NUM> shown in <FIG>, particularly due to the integration flow used for its fabrication that is presented in detail below, both the sidewalls <NUM> of the semiconductor channel 14b, and the interfaces of the semiconductor material <NUM> to the first and second electrode layers <NUM> and <NUM> are defect free. Any defects are concentrated at the top of the semiconductor material <NUM>, i.e. close its interface to the oxide <NUM> or dielectric layer <NUM>, wherein those defects have no impact on the selector device <NUM> performance. In particular, the performance is not impacted by those defects, since there is only a potential difference between the second and first electrode layer <NUM> and <NUM>, but there is no potential difference between the second electrode layer <NUM> and the top of the device <NUM>, during operation of the selector device <NUM>. The sidewalls <NUM> of the semiconductor channel 14b are not exposed to etching, and thus no defects are created.

<FIG> shows a general method <NUM> for fabricating the selector device <NUM> shown in <FIG> or <FIG>. The method <NUM> comprises: a step <NUM> of forming a first electrode layer <NUM>, wherein the first electrode layer <NUM> is embedded in an oxide <NUM>; a step <NUM> of forming a second electrode layer <NUM> above the first electrode layer <NUM>, wherein the second electrode layer <NUM> is separated from the first electrode layer <NUM> by the oxide <NUM>; a step <NUM> of forming an opening <NUM> in the second electrode layer <NUM> and in the oxide <NUM>, wherein forming the opening <NUM> exposes a part of the top surface of the first electrode layer <NUM>; and a step <NUM> of depositing <NUM> a semiconductor material <NUM>, such that it fills the opening <NUM> and forms a semiconductor layer 14a on the top surface of the second electrode layer <NUM>, wherein the semiconductor material <NUM> contacts the first electrode layer <NUM> and the second electrode layer <NUM>.

A detailed integration flow for fabricating the selector device <NUM> as shown in <FIG> or <FIG> is illustrated in <FIG>. This integration flow includes the steps of the general method <NUM>, and is shown in particular for integration of the selector device <NUM> into a memory array,.

<FIG> shows steps 1a-3a of the integration flow. It is here exemplarily assumed that a magnetic memory element of the memory array is already formed by a top electrode <NUM>, a MTJ <NUM>, and a bottom electrode <NUM>. Further, it is assumed that the first electrode layer <NUM> is already deposited onto the top electrode <NUM> of the memory element, and that the first electrode layer <NUM> is embedded into an oxide <NUM>. This relates to step <NUM> of the general method <NUM>.

In step 1a, the second electrode layer <NUM> is deposited. For forming the second electrode layer <NUM>, like the first electrode layer <NUM>, a platinum blanket deposition may be performed. This step 1a relates to step <NUM> of the general method <NUM>.

In step 2a<NUM>, a lithographic etch <NUM> (indicated with the arrows) may be performed to create an opening <NUM>, e.g. a trench, in the second electrode layer <NUM> and in the oxide <NUM>, such that the opening <NUM> lands on the first electrode layer <NUM> and exposes a part of the top surface of the first electrode layer <NUM>. This step 2a<NUM> relates to step <NUM> of the general method <NUM>.

In step 2a<NUM>, an alternative to step 2a<NUM> is shown. Here, the second electrode layer <NUM> is patterned first, e.g. an aperture <NUM> is formed in the second electrode layer <NUM>. This may be done by etching. The patterned second electrode layer <NUM> can then be used as a hard mask for an oxide etch <NUM> into the oxide <NUM> (as indicated with the arrows). The etch <NUM> in the end lands on the first electrode layer <NUM> and forms the opening <NUM> (as indicated with the dotted lines).

In step 3a, the semiconductor material <NUM>, for instance IGZO, is deposited and fills the opening <NUM> created in step 2a<NUM> or 2a<NUM>. Thereby, no damage is created to the Schottky interface, which is formed between the semiconductor material <NUM> and the second electrode layer <NUM>. This step 3a relates to step <NUM> of the general method <NUM>.

<FIG> shows steps 1b-3b of the integration flow, which are alternative to the steps 1a-3a shown in <FIG>. In particular, <FIG> shows how the opening <NUM> can be obtained using a Damascene process. It is here again exemplarily assumed that a magnetic memory element of the memory array is already formed by a top electrode <NUM>, a MTJ <NUM>, and a bottom electrode <NUM>. Further, it is assumed that the first electrode layer <NUM> is already deposited onto the top electrode <NUM> of the memory element, and that the first electrode layer <NUM> is embedded into an oxide <NUM>. This relates to step <NUM> of the general method <NUM>. Further, it is assumed that the oxide <NUM> has already been patterned, e.g. by a patterning etch, to form a protruding structure <NUM>.

In step 1b, the second electrode layer <NUM> is deposited. For forming the second electrode layer <NUM>, like the first electrode layer <NUM>, a platinum blanket deposition may be performed. The second electrode layer <NUM> is specifically deposited over the protruding structure <NUM> and on the recessed surface of the oxide <NUM>, i.e., the second electrode layer <NUM> encapsulates the protruding structure <NUM>. This step 1a relates to step <NUM> of the general method <NUM>.

In step 2b<NUM>, CMP <NUM> is performed, in order to reduce the thickness of the second electrode layer <NUM>. In particular, the thickness is reduced such that the second electrode layer <NUM> is removed from the top surface of the protruding structure <NUM>, and only remains next to the protruding structure <NUM> on the recessed top surface of the oxide <NUM>.

In step 2b<NUM>, a self-aligned oxide etch <NUM> is performed into the oxide <NUM> (aligned with the protruding structure <NUM>). That is, the patterned second electrode layer <NUM> is used as a hard mask for the oxide etch <NUM> (as indicated with the arrows). The etch <NUM> in the end lands on the first electrode layer <NUM> and forms the opening <NUM> (as indicated with the dotted lines). This step 2b<NUM> relates to step <NUM> of the general method <NUM>.

In step 3b, the semiconductor material <NUM>, for instance IGZO, is deposited and fills the opening <NUM> created in step 2b<NUM> and 2b<NUM>. Thereby, no damage is created to the Schottky interface, which is formed between the semiconductor material <NUM> and the second electrode layer <NUM>. This step 3b relates to step <NUM> of the general method <NUM>.

<FIG> shows further steps <NUM>-<NUM> of the integration flow, wherein step <NUM> continues either step 3a of <FIG> or step 3b of <FIG>. Notably, from now on, the MTJ <NUM> and second electrode <NUM> and below are not illustrated anymore for sake of simplicity.

In step <NUM>, the semiconductor material <NUM> is planarized <NUM>. For instance, Chemical Mechanical Planarization/Polishing (CMP) or CMP + etch after planarization may be performed, in order to reduce the defect density. Defects in the semiconductor material <NUM> may form at its top as indicated, but these defects have no impact on later performance of the selector device <NUM>. No damage/defects are created at the interface between the semiconductor material <NUM> and the second electrode layer <NUM>, so that a good Schottky contact is formed. This step <NUM> still relates to step <NUM> of the general method <NUM>.

In step <NUM>, a dielectric layer <NUM> is provided onto the semiconductor material <NUM>. In particular, an aluminum oxide layer may be deposited, e.g., by means of Plasma-Enhanced Chemical Vapor Deposition (PECVD).

In step <NUM>, the dielectric layer <NUM> is patterned. For example, Reactive Ion Etching (RIE) <NUM> may be used to pattern the (aluminum) dielectric layer <NUM>, and the patterning is stopped before the etching <NUM> reaches the semiconductor material <NUM>.

In step <NUM>, Ion Beam Etching (IBE) <NUM>, using the dielectric layer <NUM> as a hard mask, is performed, in order to further pattern the dielectric layer <NUM>, and specifically to also pattern the semiconductor material <NUM>. In particular, the semiconductor layer 14a formed on the second electrode layer <NUM> is patterned into a semiconductor patch. Notably, re-sputtering of the material of the second electrode layer <NUM>, e.g. re-sputtering of platinum, is not an issue at the semiconductor material sidewall (indicated by the dashed arrow and circle).

<FIG> shows further steps <NUM>-<NUM> of the integration flow.

In step <NUM>, an oxygen anneal is performed, leading to oxygen penetration <NUM> into the semiconductor material <NUM>, in particular from the sides. This improves the quality of the semiconductor channel 14b, in particular for IGZO as the semiconductor material <NUM>, by reducing the density of oxygen vacancy traps.

In step <NUM>, conformal PECVD <NUM> is performed to further deposition dielectric material, e.g. aluminum oxide. This is, in particular, performed such that the resulting dielectric layer <NUM> encapsulates the semiconductor patch formed in step <NUM>. Thus, the path for oxygen and moisture is blocked. In particular, the encapsulation ensures that the oxygen inserted by the anneal (see above) does not escape.

In step <NUM>, a sacrificial material <NUM> is provided over the dielectric layer <NUM>, specifically filled as indicated by the arrow, and is then planarized. The sacrificial material <NUM> may be a material that is selectively removable with respect to the material of the metal layer <NUM>, e.g. W/Cu, and/or with respect to the material of the dielectric layer <NUM>. For instance, the sacrificial material <NUM> may be an oxide, like a silicon oxide.

In step <NUM>, an opening <NUM> in the sacrificial material <NUM> is created by performing a lithographic etch, wherein the etch stops on the dielectric layer <NUM>. The etch stop may be achieved by the sacrificial material <NUM> being selectively removable with respect to the dielectric layer <NUM>.

<FIG> shows steps <NUM>-<NUM> of the integration flow.

In step <NUM>, the dielectric layer <NUM> is anisotropically etched <NUM> through the opening <NUM> formed in step <NUM>, in order to expose parts of the top surface of the second electrode layer <NUM>.

In step <NUM>, a metal layer <NUM> is filled into the openings etched in step <NUM> and <NUM>. In particular, a tungsten fill Damascene process can be applied, in order to fill tungsten into the openings. Also a titanium nitride barrier may be formed in this step.

In step <NUM>, a self-aligned etch is performed, i.e. self-aligned on the metal layer <NUM>, in order to etch the sacrificial material <NUM>, parts of the dielectric layer <NUM>, and parts of the second electrode layer <NUM>. The self-aligned etch does not need to be selective to the materials of the dielectric layer <NUM> and of the second electrode layer <NUM>, because these are typically very thin layers. Thus, it is acceptable if the etch of the dielectric layer <NUM> and the second electrode layer <NUM> also etches the metal layer <NUM> (which is typically much thicker than the dielectric layer <NUM> and the second electrode layer <NUM>, respectively). Selectivity between the sacrificial material <NUM> and the metal layer <NUM>, however, is preferred.

In step <NUM>, a continuation to the BEOL is processed <NUM>. In particular, PECVD can be used, in order to dispose an oxide, in which BEOL can be further processed.

Claim 1:
Method (<NUM>) for forming a selector device (<NUM>) for a memory array, the method (<NUM>) comprising:
forming (<NUM>) a first electrode layer (<NUM>), wherein the first electrode layer (<NUM>) is embedded in an oxide (<NUM>),
forming (<NUM>) a second electrode layer (<NUM>) above the first electrode layer (<NUM>), wherein the second electrode layer (<NUM>) is separated from the first electrode layer (<NUM>) by the oxide (<NUM>),
forming (<NUM>) an opening (<NUM>) in the second electrode layer (<NUM>) and in the oxide (<NUM>), wherein forming (<NUM>) the opening (<NUM>) exposes a part of the top surface of the first electrode layer (<NUM>), and
depositing (<NUM>) a semiconductor material (<NUM>), such that it fills the opening (<NUM>) and forms a semiconductor layer (14a) on the top surface of the second electrode layer (<NUM>),
wherein the semiconductor material (<NUM>) contacts the first electrode layer (<NUM>) and the second electrode layer (<NUM>),
wherein the semiconductor material (<NUM>) comprises a metal oxide material or amorphous silicon, and
wherein the first electrode layer (<NUM>), the semiconductor material (<NUM>), and the second electrode layer (<NUM>) form a double-sided Schottky diode.