Patent Description:
Semiconductor memory devices may be classified into non-volatile memory devices such as flash memory devices and volatile memory devices such as DRAMs. High speed operation and cost efficiency of DRAMs make it possible for DRAMs to be used for system memories.

<CIT> discloses a semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.

<CIT> discloses testing of operation of on-die ECC.

The invention is defined in the appended independent device claims <NUM> and <NUM> to which reference should be made.

Features will become apparent to those of skill in the art by describing in detail example embodiments with reference to the attached drawings in which:.

<FIG> is a block diagram illustrating a memory system according to example embodiments.

Referring to <FIG>, a memory system <NUM> may include a memory controller <NUM> and a semiconductor memory device <NUM>.

The memory controller <NUM> may control overall operation of the memory system <NUM>. The memory controller <NUM> may control overall data exchange between an external host and the semiconductor memory device <NUM>. For example, the memory controller <NUM> may write data in the semiconductor memory device <NUM> or read data from the semiconductor memory device <NUM> in response to request from the host. In addition, the memory controller <NUM> may issue operation commands to the semiconductor memory device <NUM> for controlling the semiconductor memory device <NUM>. The memory controller <NUM> may be referred to as an external device.

In some example embodiments, the semiconductor memory device <NUM> may be a memory device including dynamic memory cells such as a dynamic random access memory (DRAM), double data rate <NUM> (DDR4) synchronous DRAM (SDRAM), or a low power DDR5 (LPDDR4) SDRAM.

The memory controller <NUM> may transmit a command CMD and an address (signal) ADDR to the semiconductor memory device <NUM>, transmit a main data MD to the semiconductor memory device <NUM> in a normal mode, and transmit a test data TD including at least one error bit to the semiconductor memory device <NUM> and receive a decoding result data DRD from the semiconductor memory device <NUM> in a test mode. An error bit may be a bit of data that is erroneous. This data can be identified as erroneous through use of error correction code.

The memory controller <NUM> may include a central processing unit (CPU) <NUM> and an error log register <NUM>.

The semiconductor memory device <NUM> may include a memory cell array <NUM> (which stores the main data MD and the test data TD), an error correction code (ECC) circuit <NUM>, and a control logic circuit <NUM>.

The control logic circuit <NUM> may control access to the memory cell array <NUM>, and may control the ECC circuit <NUM> based on the command CMD and the address ADDR. The memory cell array <NUM> may include a normal cell region and a parity cell region.

The ECC circuit <NUM>, in a normal mode, may receive the main data MD accompanied by a first command, which includes normal data bits from the memory controller <NUM>, may perform an ECC encoding on the main data to generate a parity data, and may store the main data MD and the parity data in the normal cell region and the parity cell region, respectively.

The ECC circuit <NUM>, in a test mode, may receive the test data TD accompanied by a second command, which includes at least one error bit from the memory controller <NUM>, may store the test data TD in one of the normal cell region and the parity cell region, respectively, and may perform an ECC decoding on the test data TD and one of the main data MD and the parity data in response to a read command to provide the decoding result data DRD to the memory controller <NUM>.

The memory controller <NUM> may record error information of the ECC circuit <NUM> and the memory cell array <NUM> associated with various error patterns in the error log register <NUM>.

<FIG> is a block diagram illustrating an example of the memory controller in the memory system of <FIG> according to example embodiments.

Referring to <FIG>, the memory controller <NUM> may include the CPU <NUM>, a data buffer <NUM>, a test data generator <NUM>, an error injection register set <NUM>, the error log register <NUM>, a multiplexer <NUM>, a command buffer <NUM>, and an address buffer <NUM>.

The CPU <NUM> may receive a request REQ and a data DTA from the host, and provide the data DTA to the data buffer <NUM>. The CPU <NUM> may control the data buffer <NUM>, the test data generator <NUM>, the error injection register set <NUM>, the multiplexer <NUM>, the command buffer <NUM>, and the address buffer <NUM>.

The data buffer <NUM> may buffer the data DTA to provide the main data MD to the test data generator <NUM> and the multiplexer <NUM>. The error injection register set <NUM> may store an error bit set EB_BL including at least one error bit, and the error bit set EB_BL may be associated with the test data TD to be provided to the semiconductor memory device <NUM>.

The test data generator <NUM> may generate the test data (set) TD based on the main data MD and the error bit set EB_BL, and may provide the test data TD to the multiplexer <NUM>.

The multiplexer <NUM> may receive the main data MD and the test data TD, may select the main data MD to provide the main data MD to the semiconductor memory device <NUM> in the normal mode, and may select the test data TD to provide the test data TD to the semiconductor memory device <NUM> in the test mode, in response to a mode signal MS from the CPU <NUM>.

The command buffer <NUM> may store the command CMD corresponding to the request REQ, and transmit the command CMD to the semiconductor memory device <NUM> under control of the CPU <NUM>.

The address buffer <NUM> may store the address ADDR and transmit the address ADDR to the semiconductor memory device <NUM> under control of the CPU <NUM>.

<FIG> illustrates a data set corresponding to a plurality of burst lengths in the memory system of <FIG> according to example embodiments.

Referring to <FIG>, a data set DQ_BL corresponding to a plurality of burst lengths are input to/output from the semiconductor memory device <NUM>. The data set DQ_BL includes data segments DQ_BL_SG1~DQ_BL_SGk each corresponding to each of the plurality of burst lengths, where k is an integer greater than three. The data set DQ_BL corresponding to the plurality of burst lengths may be stored in the memory cell array <NUM> of the semiconductor memory device <NUM>. The data set DQ_BL may include the main data MD and the test data TD.

<FIG> illustrates the error injection register set, the data buffer, and the test data generator in the memory controller of <FIG> according to example embodiments.

Referring to <FIG>, the error injection register set <NUM> may include a register write circuit <NUM> and a plurality of error injection registers <NUM>~<NUM>.

The data buffer <NUM> may include a plurality of data input registers <NUM>~<NUM>. Each of the data input registers <NUM>~<NUM> may store corresponding one of first units of first data bits DQ_BL_SG1~DQ_BL_SGk, corresponding to a burst length of the semiconductor memory device <NUM>, in the data set DQ_BL. Each of the data input registers <NUM>~<NUM> may provide the test data generator <NUM> with corresponding one of first units of first data bits DQ_BL_SG1~DQ_BL_SGk in the data set DQ_BL.

Each of the error injection registers <NUM>~<NUM> may store corresponding one of second units of second data bits EB_BL_SG1~EB_BL_SGk corresponding to each of the data input registers <NUM>~<NUM> and corresponding to each of the first units of first data bits DQ_BL_SG1~DQ_BL_SGk. A size of the first unit may be the same as a size of the second unit.

The register write circuit <NUM> may maintain the second data bits stored in the error injection registers <NUM>~<NUM> at a default level (e.g., a first logic level, e.g., a logic low level), or may change at least one of the second data bits to a second logic level based on a control of the CPU <NUM>.

The test data generator <NUM> may include a plurality of exclusive OR gates <NUM>~<NUM>.

The plurality of exclusive OR gates <NUM>~<NUM> may perform an exclusive OR operation on corresponding data bits of the first units of first data bits DQ_BL_SG1~DQ_BL_SGk and the second units of second data bits EB_BL_SG1~EB_BL_SGk, respectively, to generate test data TD_SG1~TD_SGk. The test data TD_SG1~TD_SGk may include a test main data or test parity data TPRT.

<FIG> is a block diagram illustrating an example of the semiconductor memory device in the memory system of <FIG> according to example embodiments.

Referring to <FIG>, the semiconductor memory device <NUM> may include the control logic circuit <NUM>, an address register <NUM>, a bank control logic <NUM>, a row address multiplexer <NUM>, a refresh counter <NUM>, a column address latch <NUM>, a row decoder <NUM>, a column decoder <NUM>, a sense amplifier unit <NUM>, an input/output (I/O) gating circuit <NUM>, a data I/O buffer <NUM>, the memory cell array <NUM>, and the ECC circuit <NUM>.

The memory cell array <NUM> may include first through eighth bank arrays <NUM>~<NUM>. The row decoder <NUM> may include first through eighth bank row decoders 260a~<NUM> respectively coupled to the first through eighth bank arrays <NUM>~<NUM>. The column decoder <NUM> may include first through eighth bank column decoders 270a~<NUM> respectively coupled to the first through eighth bank arrays <NUM>~<NUM>. The sense amplifier unit <NUM> may include first through eighth bank sense amplifiers 285a-<NUM> respectively coupled to the first through eighth bank arrays <NUM>-<NUM>.

The first through eighth bank arrays <NUM>~<NUM>, the first through eighth bank row decoders 260a~<NUM>, the first through eighth bank column decoders 270a-<NUM>, and the first through eighth bank sense amplifiers 285a-<NUM> may form first through eighth banks. Each of the first through eighth bank arrays <NUM>~<NUM> may include a plurality of volatile memory cells MC formed at intersections of a plurality of word-lines WL and a plurality of bit-line BTL. Whilst the embodiment of <FIG> shows eight bank arrays <NUM>~<NUM> including eight of each of the bank row decoders 260a~<NUM>, column decoders 270a~<NUM>, and sense amplifiers 285a-<NUM>, alternative embodiments include alternative numbers of bank arrays.

The address register <NUM> may receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller <NUM>. The address register <NUM> may provide the received bank address BANK_ADDR to the bank control logic <NUM>, provide the received row address ROW_ADDR to the row address multiplexer <NUM>, and provide the received column address COL_ADDR to the column address latch <NUM>.

The bank control logic <NUM> may generate bank control signals in response to the bank address BANK_ADDR. One of the first through eighth bank row decoders 260a~<NUM> corresponding to the bank address BANK_ADDR is activated in response to the bank control signals, and one of the first through eighth bank column decoders 270a~<NUM> corresponding to the bank address BANK_ADDR is activated in response to the bank control signals.

The row address multiplexer <NUM> may receive the row address ROW_ADDR from the address register <NUM>, and receive a refresh row address REF_ADDR from the refresh counter <NUM>. The row address multiplexer <NUM> may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA that is output from the row address multiplexer <NUM> may be applied to the first through eighth bank row decoders 260a~<NUM>. The refresh counter <NUM> may sequentially output the refresh row address REF_ADDR under control of the control logic circuit <NUM>. When the command CMD from the memory controller <NUM> corresponds to an auto refresh command or a self-refresh entry command, the control logic circuit <NUM> may control the refresh counter <NUM> to output the refresh row address REF_ADDR sequentially.

The activated one of the first through eighth bank row decoders 260a~<NUM> (activated by the bank control logic <NUM>) may decode the row address RA that is output from the row address multiplexer <NUM>, and activate a word-line corresponding to the row address RA. For example, the activated bank row decoder may apply a word-line driving voltage to the word-line corresponding to the row address RA.

The column address latch <NUM> may receive the column address COL_ADDR from the address register <NUM>, and temporarily stores the received column address COL_ADDR. In some example embodiments, in a burst mode, the column address latch <NUM> may generate column addresses that increment from the received column address COL_ADDR. The column address latch <NUM> may apply the temporarily stored or generated column address to the first through eighth bank column decoders 270a~<NUM>.

The activated one of the first through eighth bank column decoders 270a~<NUM> may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR' or a target scrubbing column address TSCA through the I/O gating circuit <NUM>.

The I/O gating circuit <NUM> may include circuitry for gating input/output data, and may further include input data mask logic, read data latches for storing data that is output from the first through eighth bank arrays <NUM>~<NUM>, and write drivers for writing data to the first through eighth bank arrays <NUM>~<NUM>.

A codeword read from one bank array of the first through eighth bank arrays <NUM>~<NUM> may be sensed by a sense amplifier coupled to the one bank array from which the data is to be read, and may be stored in the read data latches. The codeword stored in the read data latches may be provided to the memory controller <NUM> via the data I/O buffer <NUM> after ECC decoding is performed on the codeword by the ECC circuit <NUM>.

The main data MD to be written in one bank array of the first through eighth bank arrays <NUM>~<NUM> may be provided to the data I/O buffer <NUM> from the memory controller <NUM>. The main data MD may be provided from the I/O buffer <NUM> to the ECC circuit <NUM>. The ECC circuit <NUM> may perform an ECC encoding on the main data MD to generate parity data. The ECC circuit <NUM> may provide the main data MD and the parity data to the I/O gating circuit <NUM>. The I/O gating circuit <NUM> may write the main data MD and the parity data in a sub-page of a target page in one bank array through the write drivers.

The data I/O buffer <NUM> may provide the main data MD from the memory controller <NUM> to the ECC circuit <NUM> in a write operation of a normal mode of the semiconductor memory device <NUM>, and may provide one of a test main data TMD including at least one error bit and a test parity data TPRT including at least one error bit from the memory controller <NUM> to the ECC circuit <NUM> in a write operation of a test mode of the semiconductor memory device <NUM>.

The ECC circuit <NUM>, in the write operation of the normal mode, may receive the main data MD accompanied by a first command (which includes normal data bits) from the memory controller <NUM>, may perform an ECC encoding on the main data to generate the parity data, and may store the main data MD and the parity data in the normal cell region and the parity cell region of a target bank, respectively.

The ECC circuit <NUM>, in a test mode, may receive one of the test main data TMD (including the at least one error bit and the test parity data TPRT including at least one error bit accompanied by a second command) from the memory controller <NUM>, and may store one of the test main data TMD and the test parity data TPRT in one of the normal cell region and the parity cell region of the target bank array. The second command may be activated by setting a test mode register set.

When the test mode designates a first sub test mode, the ECC circuit <NUM> may store the test parity data TPRT in the parity cell region of the target bank array, may read the main data MD stored in the normal cell region and the test parity data TPRT in the parity cell region in a read operation in response to a read command, may perform the ECC decoding on the main data MD and the test parity data TPRT to generate the decoding result data DRD, and may provide the decoding result data DRD to the memory controller <NUM> through the data I/O buffer <NUM>.

When the test mode designates a second sub test mode, the ECC circuit <NUM> may store the test main data TMD in the normal cell region of the target bank array, may read the test main data TMD stored in the normal cell region and the parity data in the parity cell region in a read operation in response to a read command, may perform the ECC decoding on the test main data TMD and the parity data to generate the decoding result data DRD, and may provide the decoding result data DRD to the memory controller <NUM> through the data I/O buffer <NUM>.

The control logic circuit <NUM> may control operations of the semiconductor memory device <NUM>. For example, the control logic circuit <NUM> may generate control signals for the semiconductor memory device <NUM> in order to perform a write operation or a read operation. The control logic circuit <NUM> may include a command decoder <NUM>, which decodes the command CMD received from the memory controller <NUM>, and a mode register <NUM>, which sets an operation mode of the semiconductor memory device <NUM>.

The command decoder <NUM> may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc..

The control logic circuit <NUM> may generate a first control signal CTL1 to control the I/O gating circuit <NUM> and a second control signal CTL2 to control the ECC circuit <NUM>.

<FIG> illustrates an example of the first bank array in the semiconductor memory device of <FIG>.

Referring to <FIG>, the first bank array <NUM> may include a plurality of word-lines WL1~WLm (m is a natural number greater than two), a plurality of bit-lines BTL1~BTLn (n is a natural number greater than two), and a plurality of volatile memory cells MCs disposed at intersections of the word-lines WL1~WLm and the bit-lines BTL1~BTLn. Each of the memory cells MCs may include a cell transistor coupled to each of the word-lines WL1~WLm and each of the bit-lines BTL1~BTLn, and may include a cell capacitor coupled to the cell transistor.

<FIG> is a block diagram illustrating an example of the ECC circuit in the semiconductor memory device of <FIG> according to example embodiments.

Referring to <FIG>, an ECC circuit 400a may include an ECC engine <NUM>, a demultiplexer <NUM>, a multiplexer <NUM>, and a buffer circuit <NUM>.

The buffer circuit <NUM> may include buffers <NUM>, <NUM>, <NUM> and <NUM>. The buffers <NUM>, <NUM>, <NUM> and <NUM> may be controlled by a buffer control signal BCTL.

The demultiplexer <NUM>, in a normal mode, may receive the main data MD, and may provide the main data MD to the ECC engine <NUM> and the buffer <NUM> in response to a first selection signal SS1.

The demultiplexer <NUM>, in a test mode, may receive one of the test main data TMD or the test parity data TPRT.

When the demultiplexer <NUM> receives the test parity data TPRT in the test mode, the demultiplexer <NUM> may provide the test parity data TPRT to the multiplexer <NUM> in response to the first selection signal SS1. That is, the demultiplexer <NUM> may be configured to provide the test parity data TPRT to the multiplexer <NUM> in response to receiving the test parity data TPRT and in response to the first selection signal SS1.

When the demultiplexer <NUM> receives the test main data TMD in the test mode, the demultiplexer <NUM> may provide the test main data TMD to the buffer <NUM> of the buffer circuit <NUM> in response to the first selection signal SS1. That is, the demultiplexer <NUM> may be configured to provide the test main data TMD to the buffer <NUM> of the buffer circuit <NUM> in response to receiving the test main data TMD and in response to the first selection signal SS1.

The ECC engine <NUM> may perform an ECC encoding on the main data MD to generate the parity data PRT in the normal mode, and provide the parity data PRT to the multiplexer <NUM>.

The multiplexer <NUM> may provide the parity data PRT to the buffer <NUM> of the buffer circuit <NUM> in response to a second selection signal SS2 in the normal mode, and may provide the test parity data TPRT to the buffer <NUM> of the buffer circuit <NUM> in response to the second selection signal SS2 in the test mode when the test mode designates the first sub test mode.

The buffer circuit <NUM> may be coupled to the I/O gating circuit <NUM> in <FIG>.

The buffer <NUM> may provide the main data MD to the I/O gating circuit <NUM> in the normal mode, and provide the test parity data TPRT to the I/O gating circuit <NUM> in the test mode when the test mode designates the first sub test mode.

The buffer <NUM> may provide the main data MD from the I/O gating circuit <NUM> to the ECC engine <NUM> in the first sub test mode of the test mode, and provide the test main data TMD from the I/O gating circuit <NUM> to the ECC engine <NUM> in the second sub test mode of the test mode.

The buffer <NUM> may provide the parity data PRT from the multiplexer <NUM> to the I/O gating circuit <NUM> in the first sub test mode, and provide the test parity data TPRT from the multiplexer <NUM> to the I/O gating circuit <NUM> in the second sub test mode.

The buffer <NUM> may provide the test parity data TPRT from the I/O gating circuit <NUM> to the ECC engine <NUM> in the first sub test mode, and provide the parity data PRT from the I/O gating circuit <NUM> to the ECC engine <NUM> in the second sub test mode.

The ECC engine <NUM>, in the first sub test mode, may perform the ECC decoding on the main data MD read from the normal cell region and the test parity data TPRT read from the parity cell region to generate the decoding result data DRD, and may provide the decoding result data DRD to the memory controller <NUM> through the data I/O buffer <NUM>.

The ECC engine <NUM>, in the second sub test mode, may perform the ECC decoding on the test main data TMD read from the normal cell region and the parity data PRT read from the parity cell region to generate the decoding result data DRD, and may provide the decoding result data DRD to the memory controller <NUM> through the data I/O buffer <NUM>.

Since the test parity data TPRT read from the parity cell region includes at least one error bit in the first sub test mode and the test main data TMD read from the normal cell region includes at least one error bit in the second sub test mode, the decoding result data DRD may indicate a result of the ECC decoding based on the at least one error bit. The at least one error bit may include one of a single bit error, a double bit error, a symbol error, and a data I/O pad error according to user's selection.

In <FIG>, the first selection signal SS1, the second selection signal SS2, and the buffer control signal BCTL may be included in the second control signal CTL2 in <FIG>.

<FIG> is a block diagram illustrating an example of the ECC engine in the ECC circuit of <FIG> according to example embodiments.

In <FIG>, the first bank array <NUM> is illustrated together for convenience of explanation. The first bank array <NUM> may include a normal cell region NCA and a parity cell region PCA.

Referring to <FIG>, the ECC engine <NUM> may include an ECC encoder <NUM>, an ECC decoder <NUM>, and an (ECC) memory <NUM>. The ECC memory <NUM> may store an ECC <NUM>.

The ECC encoder <NUM> may be coupled to the ECC memory <NUM>, and may generate parity data PRT associated with the main data MD to be stored in the normal cell region NCA of the first bank array <NUM> in the normal mode. The parity data PRT may be stored in the parity cell region PCA of the first bank array <NUM>.

In the first sub test mode, the test parity data TPRT may be stored in the parity cell region PCA of the first bank array <NUM>. In the second sub test mode, the test main data TMD may be stored in the normal cell region NCA of the first bank array <NUM>.

The ECC decoder <NUM> may be coupled to the ECC memory <NUM>. The ECC decoder <NUM> may perform an ECC decoding on the main data MD and the test parity data TPRT read from the first bank array <NUM> by using the ECC <NUM> to generate the decoding result data DRD in the first sub test mode. The ECC decoder <NUM> may perform an ECC decoding on the test main data TMD and the parity data PRT read from the first bank array <NUM> by using the ECC <NUM> to generate the decoding result data DRD in the second sub test mode.

<FIG> illustrates an example of the ECC encoder in the ECC engine of <FIG> according to example embodiments.

Referring to <FIG>, the ECC encoder <NUM> may include a parity generator <NUM>. The parity generator <NUM> may receive the main data MD and a basis bit BB, and generate the parity data PRT by performing, for example, an XOR array operation. The basis bit BB may be a bit for generating the parity data PRT with respect to the main data MD, and may include b'<NUM>. The basis bit BB may include other particular bits instead of b'<NUM>.

<FIG> illustrates an example of the ECC decoder in the ECC engine of <FIG> according to example embodiments.

Referring to <FIG>, the ECC decoder <NUM> may include a syndrome generation circuit <NUM>, an error locator <NUM>, and a data corrector <NUM>. The syndrome generation circuit <NUM> may include a check bit generator <NUM> and a syndrome generator <NUM>.

The check bit generator <NUM> may generate check bits CHB based on the main data MD by performing an XOR array operation in the first sub test mode, and based on the test main data TMD by performing an XOR array operation in the second sub test mode. The syndrome generator <NUM> may generate a syndrome SDR by comparing corresponding bits of the test parity data TPRT and the check bits CHB in the first sub test mode, and by comparing corresponding bits of the parity data PRT and the check bits CHB in the second sub test mode.

The error locator <NUM> may generate an error position signal EPS indicating a position of an error bit in the main data MD or the test main data TMD to provide the error position signal EPS to the data corrector <NUM> when all bits of the syndrome SDR are not 'zero'.

The data corrector <NUM> may receive the main data MD in the first sub test mode and receive the test main data TMD in the second sub test mode, corrects the error bit in the main data MD or the test main data TMD based on the error position signal EPS when the main data MD or the test main data TMD includes the error bit, and output the decoding output data DRD.

Since the data corrector <NUM> corrects error bits within an error correction capability of the ECC <NUM> based on the ECC <NUM>, the data corrector <NUM> outputs the decoding output data DRD without correcting error bits when the main data MD or the test main data TMD includes error bits exceeding the error correction capability of the ECC <NUM>.

Therefore, the memory controller <NUM> may determine an error pattern of data of the ECC circuit <NUM>, due to an intentional error bit included in the test parity data TPRT or the test main data TMD by analyzing the decoding result data DRD.

<FIG> is a block diagram illustrating another example of the ECC circuit in the semiconductor memory device of <FIG> according to example embodiments.

Referring to <FIG>, an ECC circuit 400b may include an ECC engine <NUM>, a demultiplexer <NUM>, a multiplexer <NUM>, a path selection circuit <NUM>, a buffer circuit <NUM>, and a storage <NUM>.

The ECC circuit 400b of <FIG> differs from the ECC circuit 400a of <FIG> in that the ECC circuit 400b further includes the path selection circuit <NUM> and the storage <NUM>, and stores the main data MD, the parity data PRT, the test main data TMD, and the test parity data TPRT in one of the memory cell array <NUM> and the storage <NUM>.

The path selection circuit <NUM> may include demultiplexers <NUM> and <NUM> and multiplexers <NUM> and <NUM>.

The demultiplexer <NUM> may receive the main data MD from the demultiplexer <NUM> in the normal mode, and receive the test main data TMD from the demultiplexer <NUM> in the second sub test mode. The demultiplexer <NUM> may provide the buffer <NUM> with the main data MD or the test main data TMD in a first storage mode and may provide the storage <NUM> with the main data MD or the test main data TMD in a second storage mode, in response to a third selection signal SS3.

The demultiplexer <NUM> may receive the parity data PRT from the multiplexer <NUM> in the normal mode, and receive the test parity data from the multiplexer <NUM> in the second sub test mode. The demultiplexer <NUM> may provide the buffer <NUM> with the parity data PRT or the test parity data TPRT in the first storage mode and may provide the storage <NUM> with the parity data PRT or the test parity data TPRT in the second storage mode, in response to the third selection signal SS3.

The storage <NUM> may output the main data MD and the test parity data TPRT or output the test main data TMD and the parity data PRT to the path selection circuit <NUM> in response to a control signal SCTL.

The multiplexer <NUM> may receive the main data MD or the test main data TMD from the buffer <NUM> in the first storage mode, and receive the main data MD or the test main data TMD from the storage <NUM> in the second storage mode. The multiplexer <NUM> may provide the main data MD to the ECC engine <NUM> in the first sub test mode and provide the test main data TMD to the ECC engine <NUM> in the second sub test mode, in response to the third selection signal SS3.

The multiplexer <NUM> may receive the parity data PRT or the test parity data TPRT from the buffer <NUM> in the first storage mode, and receive the parity data PRT or the test parity data TPRT from the storage <NUM> in the second storage mode. The multiplexer <NUM> may provide the test parity data TPRT to the ECC engine <NUM> in the first sub test mode and provide the parity data PRT to the ECC engine <NUM> in the second sub test mode, in response to the third selection signal SS3.

The ECC engine <NUM>, in the first sub test mode, may perform the ECC decoding on the main data MD read from the normal cell region NCA or the storage <NUM> and the test parity data TPRT read from the parity cell region PCA or the storage <NUM> to generate the decoding result data DRD, and may provide the decoding result data DRD to the memory controller <NUM> through the data I/O buffer <NUM>.

The ECC engine <NUM>, in the second sub test mode, may perform the ECC decoding on the test main data TMD read from the normal cell region NCA or the storage <NUM> and the parity data PRT read from the parity cell region PCA or the storage <NUM> to generate the decoding result data DRD, and may provide the decoding result data DRD to the memory controller <NUM> through the data I/O buffer <NUM>.

When the main data MD, the parity data PRT, the test main data TMD, and the test parity data TPRT are stored in the memory cell array <NUM>, the decoding result data DRD may indicate an error pattern generated in the memory cell array <NUM> by using the intentional error bit.

When the main data MD, the parity data PRT, the test main data TMD, and the test parity data TPRT are stored in the storage <NUM>, the decoding result data DRD may indicate error pattern generated in the ECC engine <NUM> by using the intentional error bit.

In <FIG>, the first selection signal SS1, the second selection signal SS2, the third selection signal SS3, the control signal SCTL, and the buffer control signal BCTL may be included in the second control signal CTL2 in <FIG>.

<FIG> is a block diagram illustrating an example of the storage in <FIG> according to example embodiments.

Referring to <FIG>, the storage <NUM> may include a first region <NUM> and a second region <NUM>.

The first region <NUM> may be referred to as a normal region, and may store the main data MD in the normal mode. The main data MD may be read from the first region <NUM> in the first sub test mode, and the test main data TMD may be stored in and be read from the first region <NUM> in the second sub test mode.

The second region <NUM> may be referred to as a parity region, and may store the parity data PRT in the normal mode. The test parity data TPRT may be stored in and be read from the second region <NUM> in the first sub test mode, and the parity data PRT may be stored in and read from the second region <NUM> in the second sub test mode.

<FIG> illustrates second data bits that may be stored in the error injection register set in <FIG>.

Referring to <FIG>, second data bits V having a first logic level as a default logic level may be stored in the error injection registers <NUM>~<NUM> in the error injection register set <NUM>. The register write circuit <NUM> may change at least one of the second data bits V to a second logic level such that the test data TD_SG1~TD_SGk representing various error patterns may be provided to the semiconductor memory device <NUM>.

The memory controller <NUM> may analyze an error pattern of the decoding result data DRD, and may log error information associated with the error pattern in the error log register <NUM>.

<FIG> illustrate various error patterns that the error injection register set may represent according to example embodiments.

Referring to <FIG>, only one of the second data bits EB_BL_SG1~EB_BL_SGk has a logic high level. Therefore, the error pattern of <FIG> represents a single bit error.

Referring to <FIG>, two of the second data bits EB_BL_SG1~EB_BL_SGk have a logic high level. Therefore, the error pattern of <FIG> represents a double bit error.

<FIG> illustrates an error pattern associated with a data pad.

Referring to <FIG>, all data bits associated with a data I/O pad DQ1 of the second data bits EB_BL_SG1~EB_BL_SGk have a logic high level. Therefore, the error pattern of <FIG> represents an error pattern associated with a data I/O pad.

In addition, the error injection register set of <FIG> may represent various error patterns such a symbol error pattern.

<FIG> illustrates a command sequence that the semiconductor memory device receives in an error injection test mode according to example embodiments.

Referring to <FIG> and <FIG>, the mode register <NUM> may be set to an error injection test entry mode in response to a first mode register set command MRS1.

A target word-line in the memory cell array may be activated in response to an active command ACT, the main data MD accompanied by a first write command WR1 (a first command) may be provided to the ECC circuit <NUM>, and the parity data PRT may be generated and the main data MD and the parity data PRT may be stored in the normal cell region and the parity cell region coupled to the target word-line, respectively.

The test data TD including at least one error bit accompanied by a second write command WR2 (a second command) may be provided to the ECC circuit <NUM>, and the test data TD may be stored in one of the in the normal cell region and the parity cell region coupled to the target word-line.

One of the main data MD and the parity data PRT and the test data TD may be read in response to a read command RD, and the ECC circuit <NUM> may perform an ECC decoding on one of the main data MD and the parity data PRT and the test data TD to generate the decoding result data DRD and provide the decoding result data DRD to the memory controller <NUM>.

The first write command WR1, the second write command WR2, and the read command RD during a first interval INT11 indicate that an error injection test is performed on a codeword stored in a target page of the target word-line.

The first write command WR1, the second write command WR2, and the read command RD during a second interval INT12 indicate that an error injection test is performed on another codeword stored in a target page of the target word-line.

When the error injection test is repeatedly performed on the codewords and the error injection test on all codewords is completed, the target word-line may be precharged in response to a precharge command PRE and the mode register <NUM> may be set to an error injection test exit mode in response to a second mode register set command MRS2.

Although the semiconductor memory device <NUM> may be set to the error injection test mode by setting the mode register <NUM> in <FIG>, the error injection test mode of the semiconductor memory device <NUM> may be executed by setting a test mode register set or a specified command sequence.

<FIG> illustrate that data is exchanged between the memory controller and the semiconductor memory device in the memory system of <FIG>, respectively.

Referring to <FIG>, the first bank array <NUM> of the memory cell array <NUM> may include a normal cell region NCA and a parity cell region PCA.

In <FIG>, it is assumed that data is stored in memory cells coupled to a word-line WLj in the normal cell region NCA and the parity cell region PCA.

<FIG> illustrates the memory system of <FIG> in the normal mode.

Referring to <FIG>, when the main data MD accompanied by a first command (a first write command) is provided from the memory controller <NUM> in the normal mode, the ECC circuit 400a may perform an ECC encoding on the main data MD to generate the parity data PRT and may store the main data MD and the parity data PRT in the normal cell region NCA and the parity cell region PCA of the first bank array <NUM>, respectively.

<FIG> illustrates the memory system of <FIG> when the test mode designates the first sub test mode.

Referring to <FIG>, when the test mode designates the first sub test mode, the memory controller <NUM> may transmit the test parity data TPRT including at least one error bit to the semiconductor memory device <NUM> and the semiconductor memory device <NUM> may receive the test parity data TPRT through a first data I/O pad through which the semiconductor memory device <NUM> receives the main data MD. The ECC circuit 400a may store the test parity data TPRT accompanied by a second command (a second write command) in a memory location in which the parity data PRT is stored in the parity cell region PCA.

The ECC circuit 400a may read the main data MD and the test parity data TPRT from the normal cell region NCA and the parity cell region PCA, respectively, in response to a read command, may perform an ECC decoding on the main data MD and the test parity data TPRT to generate a decoding result data DRD1, and may transmit the decoding result data DRD1 to the memory controller <NUM> through the first data I/O pad.

The memory controller <NUM> may analyze a code of the ECC circuit 400a based on the decoding result data DRD1 when the parity data includes an error bit, and may provide an external host with a result of the analysis.

<FIG> illustrates the memory system of <FIG> when the test mode designates the second sub test mode.

Referring to <FIG>, when the test mode designates the second sub test mode, the memory controller <NUM> may transmit the test main data TMD including at least one error bit to the semiconductor memory device <NUM>, and the semiconductor memory device <NUM> may receive the test main data TMD through a first data I/O pad through which the semiconductor memory device <NUM> receives the main data MD. The ECC circuit 400a may store the test main data TMD accompanied by a second command (a second write command) in a memory location in which the main data MD is stored in the normal cell region NCA.

The ECC circuit 400a may read the test main data TMD and the parity data PRT from the normal cell region NCA and the parity cell region PCA, respectively, in response to a read command, may perform an ECC decoding on the test main data TMD and the parity data PRT to generate a decoding result data DRD2, and may transmit the decoding result data DRD2 to the memory controller <NUM> through the first data I/O pad.

The memory controller <NUM> may analyze code of the ECC circuit 400a based on the decoding result data DRD2 when the parity data includes an error bit, and may provide an external host with a result of the analysis.

<FIG> is a flow chart illustrating a method of operating a semiconductor memory device according to example embodiments.

Referring to <FIG> and <FIG>, in a method of operating a semiconductor memory device <NUM> including a memory cell array <NUM> that includes a normal cell region NCA and a parity cell region PCA, the semiconductor memory device <NUM> may receive a main data MD including normal bits, accompanied by a first command, from a memory controller <NUM>. An ECC circuit <NUM> in the semiconductor memory device <NUM> may generate parity data PRT based on the main data MD (by performing an ECC encoding on the main data MD) (operation S110).

The ECC circuit 400a may store the main data MD and the parity data PRT in the normal cell region NCA and the parity cell region PCA, respectively (operation S120).

A control logic circuit <NUM> in the semiconductor memory device <NUM> may determine whether a test mode designates either a first sub test mode or a second sub test mode (operation S130).

When the test mode designates the first sub test mode, the semiconductor memory device <NUM> may receive a test parity data TPRT including at least one error bit through a first data I/O pad through which the semiconductor memory device <NUM> receives the main data MD from the memory controller <NUM> (operation S140).

The ECC circuit 400a may store the test parity data TPRT in a memory location in which the parity data PRT is stored in the parity cell region PCA (operation S150).

The ECC circuit 400a may read the main data MD and the test parity data TPRT from the normal cell region NCA and the parity cell region PCA, respectively, in response to a read command, and may perform an ECC decoding on the main data MD and the test parity data TPRT to transmit a decoding result data DRD to the memory controller <NUM> (operation S160).

When the test mode designates the second sub test mode, the semiconductor memory device <NUM> may receive a test main data TMD including at least one error bit through a first data I/O pad through which the semiconductor memory device <NUM> receives the main data MD from the memory controller <NUM> (operation S170).

The ECC circuit 400a may store the test main data TMD in a memory location in which the main data MD is stored in the normal cell region NCA (operation S180).

The ECC circuit 400a may read the test main data TMD and the parity data PRT from the normal cell region NCA and the parity cell region PCA, respectively, in response to a read command, and may perform an ECC decoding on the test main data TMD and the parity data PRT to transmit a decoding result data DRD to the memory controller <NUM> (operation S190).

In a semiconductor memory device and a memory system according to example embodiments, the memory system may inject at least one error bit (e.g. at least one erroneous bit) in the main data or the parity data in the error injection test mode, and the ECC circuit in the semiconductor memory device may perform an ECC decoding on the data in which the at least one error bit is injected to generate a decoding result data, and transmit the decoding result data to the memory controller. The memory controller may analyze an ECC in the semiconductor memory device based on the decoding result data when various error patterns are implemented in the main data or the parity data.

<FIG> is a block diagram illustrating a semiconductor memory device according to example embodiments.

Referring to <FIG>, a semiconductor memory device <NUM> may include at least one buffer die <NUM> and group dies <NUM> providing a soft error analyzing and correcting function in a stacked chip structure.

The group dies <NUM> may include a plurality of memory dies <NUM>-<NUM> to <NUM>-p stacked on the at least one buffer die <NUM>, and may convey data through a plurality of through silicon via (TSV) lines.

Each of the memory dies <NUM>-<NUM> to <NUM>-p may include a cell core <NUM> (which includes a normal cell region and a parity cell region, and stores data) and a cell core ECC circuit <NUM> (which generates transmission parity bits (i.e., transmission parity data) based on transmission data to be sent to the at least one buffer die <NUM>). The cell core ECC circuit <NUM> may employ the ECC circuit 400a of <FIG> or the ECC circuit 400b of <FIG>.

The cell core ECC circuit <NUM>, in an error injection test mode, may receive main data or parity data that includes at least one error bit, may store test parity data in a parity cell region in a first sub test mode, and may store test main data in a normal cell region in a second sub test mode.

The cell core ECC circuit <NUM> may read the data in which the error bit is injected, may perform ECC decoding on the main data and the parity data in one of which at least one error bit is injected to generate a decoding result data, and may transmit the decoding result data to the memory controller <NUM>. The memory controller <NUM> may analyze an ECC in the semiconductor memory device <NUM> based on the decoding result data when various error patterns are implemented in the main data or the parity data.

The at least one buffer die <NUM> may include a via ECC circuit <NUM> that corrects a transmission error using the transmission parity bits when a transmission error is detected from the transmission data received through the TSV liens, and generates error-corrected data.

The semiconductor memory device <NUM> may be a stack chip type memory device or a stacked memory device that conveys data and control signals through the TSV lines. The TSV lines may be also called 'through electrodes'.

The cell core ECC circuit <NUM> may perform error correction on data that is output from the memory die <NUM>-p before the transmission data is sent.

A transmission error that occurs at the transmission data may be due to noise that occurs at the TSV lines. Since data failure due to the noise occurring at the TSV lines may be distinguishable from data failure due to a false operation of the memory die, it may be regarded as soft data failure (or a soft error). The soft data failure may be generated due to a transmission failure on a transmission path, and may be detected and remedied by an ECC operation.

A data TSV line group <NUM> that is formed at one memory die <NUM>-p may include TSV lines L1 to Lp, and a parity TSV line group <NUM> may include TSV lines L10 to Lq. The TSV lines L1 to Lp of the data TSV line group <NUM> and the parity TSV lines L10 to Lq of the parity TSV line group <NUM> may be connected to micro bumps MCB that are correspondingly formed among the memory dies <NUM>-<NUM> to <NUM>-p.

Each of the memory dies <NUM>-<NUM> to <NUM>-p may include DRAM cells, each including at least one access transistor and one storage capacitor.

The semiconductor memory device <NUM> may have a three-dimensional (3D) chip structure or a <NUM>. 5D chip structure to communicate with the host through a data bus B10. The buffer die <NUM> may be connected with the memory controller through the data bus B10.

The cell core ECC circuit <NUM> may output transmission parity data as well as the transmission data through the parity TSV line group <NUM> and the data TSV line group <NUM>, respectively. The output transmission data may be data that is error-corrected by the cell core ECC circuit <NUM>.

The via ECC circuit <NUM> may determine whether a transmission error occurs at the transmission data received through the data TSV line group <NUM>, based on the transmission parity data received through the parity TSV line group <NUM>. When a transmission error is detected, the via ECC circuit <NUM> may correct the transmission error on the transmission data using the transmission parity data. When the transmission error is uncorrectable, the via ECC circuit <NUM> may output information indicating occurrence of an uncorrectable data error.

When an error is detected from read data in a high bandwidth memory (HBM) or the stacked memory structure, the error may be an error occurring due to noise while data is transmitted through the TSV. According to example embodiments, as illustrated in <FIG>, the cell core ECC circuit <NUM> may be included in the memory die, and the via ECC circuit <NUM> may be included in the buffer die <NUM>. Accordingly, it may be possible to detect and correct a soft data failure. The soft data failure may include a transmission error that is generated due to noise when data is transmitted through TSV lines.

<FIG> is a diagram illustrating a semiconductor package including the stacked memory device, according to example embodiments.

Referring to <FIG>, a semiconductor package <NUM> may include one or more stacked memory devices <NUM> and a graphic processing unit (GPU) <NUM>. The GPU <NUM> may include a memory controller <NUM>.

The stacked memory devices <NUM> and the GPU <NUM> may be mounted on an interposer <NUM>, and the interposer may be mounted on a package substrate <NUM>. The package substrate <NUM> may be mounted on solder balls <NUM>. The memory controller <NUM> may employ the memory controller <NUM> in <FIG>.

Each of the stacked memory devices <NUM> may be implemented in various forms, and may be a memory device in a high bandwidth memory (HBM) form in which a plurality of layers are stacked. Each of the stacked memory devices <NUM> may include a buffer die and a plurality of memory dies. Each of the memory dies may include a memory cell array and an ECC circuit.

The plurality of stacked memory devices <NUM> may be mounted on the interposer <NUM>, and the GPU <NUM> may communicate with the plurality of stacked memory devices <NUM>. For example, each of the stacked memory devices <NUM> and the GPU <NUM> may include a physical region, and communication may be performed between the stacked memory devices <NUM> and the GPU <NUM> through the physical regions.

By way of summation and review, due to continuing shrink in a fabrication design rule of DRAMs, bit errors of memory cells in the DRAMs may increase and yield of the DRAMs may decrease.

As described above, in a semiconductor memory device and a memory system according to example embodiments, the memory system may inject at least one error bit (e.g. at least one erroneous bit) in the main data or the parity data in the error injection test mode, the ECC circuit in the semiconductor memory device may perform an ECC decoding on the data in which the at least one error bit is injected to generate a decoding result data, and may transmit the decoding result data to the memory controller. The memory controller may analyze an ECC in the semiconductor memory device based on the decoding result data when various error patterns are implemented in the main data or the parity data.

Embodiments may be applied to systems using semiconductor memory devices that employ an ECC circuit. For example, embodiments may be applied to systems such as be a smart phone, a navigation system, a notebook computer, a desk top computer and a game console that use the semiconductor memory device as a working memory.

Embodiments may provide a semiconductor memory device capable of performing an error injection test. Embodiments may provide a memory system capable of performing an error injection test.

Devices or components that are said to be configured to perform a step "when" an event occurs or a criterion is satisfied, may be considered to perform the step "in response to" the event occurring or the criterion being satisfied.

Claim 1:
A semiconductor memory device, comprising:
a memory cell array (<NUM>) including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the memory cell array (<NUM>) including a normal cell region (NCA) and a parity cell region (PCA);
an error correction code, hereinafter referred to as ECC, circuit (<NUM>); and
a control logic circuit (<NUM>) configured to control the ECC circuit (<NUM>),
wherein the ECC circuit (<NUM>) is configured to:
in a normal mode:
receive a main data including normal data bits from an external device (<NUM>), the main data being accompanied by a first write command;
perform an ECC encoding on the main data to generate a parity data; and
store the main data and the parity data in the normal cell region (NCA) and the parity cell region (PCA), respectively, and
in a test mode:
receive a test data from the external device (<NUM>), the test data including one of test main data or test parity data and including at least one error bit, the test data being accompanied by a second write command;
store the test data in one of the normal cell region and the parity cell region; and
perform an ECC decoding on the test data and one of the main data and the parity data in response to a read command to provide a decoding result data to the external device (<NUM>);
wherein when the test mode designates a first sub test mode, the ECC circuit is configured to:
receive a test parity data including the at least one error bit as the test data;
store the test parity data in the parity cell region in a memory location in which the parity data is stored;
read the main data and the test parity data in response to a read command; and
perform the ECC decoding on the main data and the test parity data to output the decoding result data; and
wherein when the test mode designates a second sub test mode, the ECC circuit is configured to:
receive a test main data including the at least one error bit as the test data;
store the test main data in the normal cell region in a memory location in which the main data is stored; and
read the test main data and the parity data in response to a read command; and
perform the ECC decoding on the test main data and the parity data to output the decoding result data.