Patent Description:
Thin film piezoelectric materials can be used in sensors and transducers. Piezoelectric sensors and transducers are also used in devices such as gyro-sensors, ink-jet printer heads and other Microelectromechanical systems (MEMS) devices, including acoustic resonator used in mobile phones and other wireless applications. These thin piezoelectric films can be fabricated by techniques such as sputtering, pulsed laser ablation (PLD), MOCVD, and sol-gel deposition.

In semiconductor processing, physical vapor deposition (PVD) (e.g., sputtering process) is a conventionally used process for depositing a thin film. A PVD process includes bombarding a target that has a source material. Ions are generated in a plasma within a chamber, causing the source material to be sputtered from the target to a substrate. During some PVD processes, the sputtered source material is then accelerated towards the substrate being processed via a voltage bias. The source material is deposited on the surface of the substrate. In some examples, the sputtered source material may react with another reactant. In the case of sputtering a fabricated layer on a substrate, epitaxial growth of the thin films can demonstrate strain and/or dislocated structure due to the thermal and lattice mismatch between the piezoelectric-based materials and the substrate.

During deposition of the sputtered material, a thickness and stress uniformity of the sputtered thin films may be affected by several controlled parameters. The controlled parameters can include a strength of a magnetic field used to trap electrons near the surface of a sputtering target, a lattice match or mismatch between adjacent materials, and crystal orientation of the substrate can make it difficult to maintain uniform properties of thin films. Such non-uniformity of thin films can cause fluctuation of with-in-wafer (WIW) piezoelectric properties and reduce production yield of piezoelectric devices. <CIT> describes a piezoelectric element and a method for forming the piezoelectric element. <CIT> describes piezoelectric thin film which is obtained by sputtering and which is made of tantalum aluminum nitride.

Accordingly, there is a need for an improved method and apparatus for depositing piezoelectric materials and extending the lifetime of thin films used in sensing devices.

The subject-matter of the invention is disclosed in the appended claims.

Disclosed herein is an apparatus and method for fine tuning the properties of a thin film. In one example, a method of forming a piezoelectric film includes (a) depositing a first piezoelectric film layer on a surface of a substrate by a first physical vapor deposition (PVD) process. The method further includes (b) depositing a second piezoelectric film layer, on top of and in contact with the first piezoelectric film layer, by a second physical vapor deposition (PVD) process. The method continues by (c) reducing a temperature of the substrate after forming the first piezoelectric film layer and before forming the second piezoelectric film layer. The temperature is reduced by performing a process for a first period of time. Processes (a), (b) and (c) are additionally performed one or more times. Process (c), in the additionally performed processes (a), (b) and (c), is performed for a second period of time. The second period of time is different than the first period of time. The first PVD process and the second PVD process each comprise a sputtering process.

In another example, the method of forming a piezoelectric film includes (a) depositing, in a first processing chamber, a first piezoelectric film layer on a surface of a substrate by a first physical vapor deposition (PVD) process. The method includes (b) depositing, in the first processing chamber, a second piezoelectric film layer, on top of and in contact with the first piezoelectric film layer, by a second PVD process. The method continues by (c) reducing a temperature of a substrate after forming the first piezoelectric film and before forming the second piezoelectric film. The temperature is reduced by performing a process for a first period of time. Processes (a), (b) and (c) are additionally performed one or more additional times. The additionally performed process (c) is performed for a second period of time. The second period of time is different than the first period of time.

In yet another example, an apparatus for processing a substrate includes a processor coupled to at least one non-transitory computer readable medium. The at least one non-transitory computer readable medium includes instructions which when executed by the processor are configured to cause the apparatus to perform a method. The method includes (a) depositing a first piezoelectric film layer on a surface of a substrate by a first physical vapor deposition (PVD) process. Additionally, the method includes (b) depositing a second piezoelectric film layer, on top of and in contact with the first piezoelectric film layer, by a second physical vapor deposition (PVD) process. The method continues by (c) reducing a temperature of the substrate after forming the first piezoelectric film layer and before forming the second piezoelectric film layer. The temperature is reduced by performing a process for a first period of time. Processes (a), (b) and (c) are additionally performed one or more times. Process (c), in the additionally performed processes (a), (b) and (c), is performed for a second period of time. The second period of time is different than the first period of time. The first PVD process and the second PVD process each comprise a sputtering process.

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to examples, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only examples and are therefore not to be considered limiting of its scope, and may admit to other equally effective examples.

It is contemplated that elements and features of one example may be beneficially incorporated in other examples without further recitation.

Disclosed herein is an apparatus and method for fine tuning the properties of a thin film during a thin film deposition process, such as a process that includes a sputtering process. When piezo-electric materials are deposited on a substrate at high temperatures, crystal orientation is improved, resulting in smaller full-width-half-maximum (FWHM) peaks due to the decrease in variation in the crystal orientation. However, when a thin film is formed at high substrate deposition temperatures, with-in-wafer (WIW) stress uniformity increases. In contrast, lower substrate temperatures correlate to better WIW stress uniformity, but larger FWHM peaks. The crystalline structures of the thin film layers disclosed herein were studied (or inspected) using X-ray diffraction (XRD). Therefore, a method is needed to solve the conflicting effects on variations in crystal orientation and film stress.

In an effort to address these competing effects, a multistep process sequence has been developed and is disclosed herein. The process sequence generally includes the formation of a first thin layer, so called a seed layer, and a second layer, or also referred to herein as a bulk layer, forms the rest of the deposited film thickness. In another example, the bulk layer is formed on top of and in contact with the substrate without a deposited seed layer. A separate temperature control is used during the deposition processes used to form the two layers. In one embodiment, the seed layer deposition process includes heating the substrate to a high temperature (e.g., <NUM> C - <NUM> C) in a first chamber, such as a lamp heated chamber or heated substrate support pedestal containing chamber, and then depositing the seed layer in separate deposition chamber that has a substrate support that is maintained at a temperature that is less than the temperature that the substrate achieves in the first chamber. In one example, the seed layer deposition process includes a sputtering process that is adapted to form a piezo-electric material. The high temperature achieved by the substrate while the seed layer is formed provides a good surface condition for nucleation of the thin film layer and allows the formed crystals to have to have a preferred crystal orientation (e.g., small variation in crystal orientation). Afterwards, the substrate with the seed layer disposed thereon is sent to a different chamber for cooling. After the substrate is cooled, the substrate is sent back to the process chamber, which has a substrate support that is controlled to a temperature around room temperature to continue deposition of the bulk layer. It has been found that this deposition-cooling-deposition process sequence is able to avoid the conflict between the temperature effect on stress and crystal orientation, and instead, provides a positive effect to each property. Advantageously, the apparatus and method disclosed herein enables the formation of a thin layer that has both a smaller FWHM and an improved stress uniformity and stress level. The separate temperature control during the different parts of the processing sequence enables improved overall film properties by reducing film stress and improving crystal orientation.

During sputtering of the thin film layers, differences in surface properties of the thin film layers and/or one or more regions of the substrate surface can result in cone defects, stacking defects, and other surface defects. The defects increase surface roughness, weaken piezoelectric coupling between layers and ultimately degrade the performance of a formed piezoelectric device. During deposition of a high temperature seed layer, parameters such as degas temperature, pressure, bias power, target-substrate spacing, and gas ratio are adjusted in order to suppress the cone defects and improve the crystal quality of thin film layers.

The methods and apparatuses disclosed herein also enable the fine-tuning of the properties of a thin film by adjusting processing parameters during the formation of the bulk layer. In general, deposition process parameters, process time, and a cooling recipe process parameters are adjusted in order to improve stress uniformity and crystal orientation. The deposition process pressure, deposition bias power, sputter target power, gas ratio concentration (e.g., reactive gas to inert gas concentration ratio) are examples of adjustable deposition process parameters. The cooling process pressure, substrate support temperature, and cooling gas composition are examples of adjustable cooling process parameters. The deposition and cooling process parameters can be adjusted alone or in combination with the process time. Accordingly, by fine tuning the above-noted parameters while depositing the bulk layer, an increased within wafer (WIW) stress uniformity and crystal orientation of thin film properties are available.

<FIG> is a plan view of a cluster tool <NUM> that is adapted to deposit thin film layers on a substrate. One example of the cluster tool <NUM> is commercially available from Applied Materials, Inc. of Santa Clara, Calif. , and is known as the Endura® system.

The cluster tool <NUM> includes a factory interface <NUM>, loading dock <NUM>, a first robot <NUM>, and a second robot <NUM>. An orient chamber <NUM>, degas chamber <NUM>, first processing chambers <NUM> and <NUM>, second processing chambers <NUM>-<NUM>, a second robot <NUM>, and a main frame <NUM> are included in the cluster tool <NUM>. The cluster tool <NUM> also includes a first transfer chamber <NUM> and a second transfer chamber <NUM>.

Each cassette <NUM>, or FOUP, is configured to receive a plurality of substrates <NUM>. In this configuration, the substrates <NUM> are removed from the cassette <NUM>, by one of the factory interface robots <NUM>. The factory interface robots <NUM> will transfer the substrate <NUM> from the cassette <NUM> and load the substrate <NUM> into the loading dock <NUM> (i.e., load lock). Upon completion of substrate processing in the cluster tool <NUM>, the processed substrates <NUM> are then returned to their respective cassette <NUM>.

A main frame <NUM> includes the first transfer chamber <NUM> that includes a first robot <NUM>. The first robot <NUM> is configured to move the substrate <NUM> between the orient chamber <NUM>, degas chamber <NUM>, and a first processing chamber <NUM>. Each of the orient chamber <NUM>, degas chamber <NUM>, and a first processing chamber <NUM> is arranged around the periphery of the first transfer chamber <NUM>. In some configurations, the first transfer chamber <NUM> is vacuum pumped to a moderately low pressure, for example, about <NUM> milliTorr or less. The second transfer chamber <NUM> is pumped to a lower pressure, for example, <NUM> microTorr or less. Accordingly, the first transfer chamber <NUM> or the second transfer chamber <NUM> is maintained at least at a moderate vacuum level to prevent the transfer of contamination between the first transfer chamber <NUM> and the second transfer chamber <NUM>. It is understood that any discussion or description of the first processing chamber <NUM> necessarily includes the first processing chamber <NUM>, unless explicitly stated otherwise.

A second robot <NUM> is configured to move the substrate(s) <NUM> between the first processing chamber <NUM> and a second processing chamber <NUM>. The second robot <NUM> is disposed within the second transfer chamber <NUM>. The second robot <NUM> is configured to transfer substrates <NUM> to and from the first processing chamber <NUM> and the second processing chamber <NUM> or other process chambers <NUM>-<NUM> attached to the second transfer chamber <NUM> portion of the main frame <NUM>. In one configuration, each of the first robot <NUM> and the second robot <NUM> is a "frog-leg" type robot, available from Applied Materials, Inc. of Santa Clara, Calif. The first transfer chamber <NUM> can be selectively isolated from each of the orient chamber <NUM>, degas chamber <NUM>, and first processing chamber <NUM> by use of slit valves (not shown) that are disposed between each of the orient chamber <NUM>, degas chamber <NUM>, and first processing chamber <NUM>. The second transfer chamber <NUM> can be selectively isolated from each of the first processing chamber <NUM> and the second processing chamber <NUM> by use of slit valves that are disposed between each of the first processing chamber <NUM> or the second processing chamber <NUM>. Herein, it is understood that any discussion or description of the second processing chamber <NUM> includes any one of the second processing chambers <NUM>-<NUM>.

Each loading dock <NUM> is each selectively isolated from both the first transfer chamber <NUM> by slit valves and from the exterior region <NUM> of the factory interface <NUM> by vacuum doors (not shown). In this configuration, the factory interface robots <NUM> in the factory interface are configured to move a substrate <NUM> from a cassette <NUM> to the loading dock <NUM>. The substrate <NUM> is then isolated from the exterior region <NUM> of the factory interface <NUM> by the vacuum door (not shown) coupled to the loading dock <NUM>. The substrate <NUM> is transferred to the loading dock <NUM>. After the loading dock <NUM> is pumped down to a desired pressure, the substrate <NUM> can then be accessed by the first robot <NUM> through a slit valve opening (not shown) formed between the first transfer chamber <NUM> and the loading dock <NUM>.

Each substrate <NUM> is loaded into a cassette <NUM> that is coupled to a factory interface <NUM>. The substrate <NUM> may have a diameter in a range from about <NUM> to about <NUM>. The substrate <NUM> may be formed from a variety of materials, including Si, SiC or SiC-coated graphite. In one example, the substrate <NUM> includes a silicon carbide material and has a surface area of about <NUM>,<NUM><NUM> or more. In another example, the surface area of the substrate <NUM> may be about <NUM>,<NUM><NUM> or more, and about <NUM>,<NUM><NUM> or more.

One or more orient chambers <NUM> may be used to align the substrate <NUM> in a desired rotational orientation within the cluster tool <NUM>. By aligning the substrate <NUM>, the substrate <NUM> is also aligned. The orient chamber <NUM> may be positioned proximate the loading dock <NUM> and proximate the degas chamber <NUM>.

In some embodiments, the orient chambers <NUM> include a heat source, such as lamps or infrared generating radiant heaters. The heat source within the orient chambers <NUM> can be adapted to heat the substrate <NUM> and each substrate <NUM> to a desired temperature. The orient chambers <NUM> can be pressurized under a vacuum condition to ensure that any undesirable water or other contamination is removed from the surface of the substrate <NUM> prior to processing in other downstream chambers.

In some embodiments, the cluster tool <NUM> includes a pre-clean chamber <NUM> that is adapted to clean the surface of a substrate <NUM> by use of cleaning process that includes exposing the surface of the substrate to a radio frequency (RF) generated plasma and/or one or more pre-cleaning gas compositions that includes a carrier gas (e.g., Ar, He, Kr) and/or a reactive gas (e.g., hydrogen). In some embodiments, the pre-clean chamber <NUM> is adapted to perform a process that may include a non-selective sputter etching process. The pre-clean chamber <NUM> will typically include components similar to the components found in the pre-clean chamber <NUM>, which is described below in conjunction with <FIG>.

Each first processing chamber <NUM> is configured to process the substrate(s) <NUM> therein. Processing may include cooling the substrate, heating the substrate <NUM>, etching and/or depositing one or more layers on a surface of the substrate <NUM>. In one configuration, the first processing chamber <NUM> is configured to cool or heat a substrate <NUM>.

Each of the processing chambers <NUM>-<NUM> are adapted to perform an etch and/or deposition process. In some embodiments, the deposition process may include a sputter deposition process (i.e., PVD deposition process). The sputter deposition process may also include temperature regulation step that is adapted to a cool down and/or control the temperature of the substrate during processing.

<FIG> is a plan view of a process chamber <NUM> that can be part of one or more of the processing chamber <NUM>-<NUM>. The process chamber <NUM> is adapted to deposit thin film layers on the substrate <NUM> in the cluster tool illustrated in <FIG>. The processing chamber <NUM> can be a magnetron type PVD chamber available from Applied Materials, Inc. of Santa Clara, Calif. The processing chamber <NUM> includes a chamber <NUM>, a target <NUM>, a magnetron <NUM>, a vacuum pumping system <NUM>, a substrate support assembly <NUM>, and a process kit <NUM>. In one example, the target <NUM> is a scandium (Sc) doped aluminum (Al) target. In one example, the target <NUM> is a scandium (Sc) doped aluminum (Al) target that has between about 1at% and <NUM> at% scandium. In another example, an aluminum (Al) target has between about <NUM> at% and <NUM> at% scandium, or between about <NUM> at% and <NUM> at% scandium. In yet another example, an aluminum (Al) target has between about <NUM> at% and <NUM> at% scandium, or between about <NUM> at% and <NUM> at% scandium. In another example, the target <NUM> may be made from Al.

The chamber <NUM> supports the target <NUM>, which is sealed at one end of the chamber <NUM> through a target isolator <NUM> using a plurality of O-rings. The chamber <NUM> may be held under vacuum.

The process kit <NUM> includes an edge ring <NUM>, a first shield <NUM> and the second shield <NUM> that are separated by a second dielectric shield isolator <NUM>. The process kit <NUM> parts are positioned within the chamber <NUM> to protect the chamber wall <NUM>. A metal within the process kit <NUM> is electrically grounded from the sputtered material that is generated in an interior volume <NUM>. The first shield <NUM> may be permitted to float electrically and the second shield <NUM> is electrically grounded. In an alternate example, either or both of the first shield <NUM> or second shield <NUM> may be grounded, floating or biased to the same or different non-ground levels. The first shield <NUM> and second shield <NUM> may be made of stainless steel. An inner surface <NUM> may be bead-blasted or otherwise roughened to promote adhesion of the material sputter deposited on the inner surface <NUM>.

The substrate support assembly <NUM> includes a pedestal <NUM>. The pedestal <NUM> may include an electrostatic chuck <NUM> that has a supporting surface that is adapted to support a substrate <NUM> over an electrode <NUM>. It is appreciated that other devices may be used to hold the substrate <NUM> in place during processing. Resistive heaters, refrigerant channels, and/or thermal transfer gas cavities, which are not illustrated in <FIG>, may be formed in the pedestal <NUM> to provide thermal control of the substrate <NUM> during processing. The electrode <NUM>, which is coupled to a first power supply <NUM>, may apply an RF and/or a DC bias to the substrate <NUM> to attract a plasma <NUM> ionized deposition material and processes gases. In other applications, biasing of the substrate <NUM> may be reduced or eliminated to further reduce the potential for damage to the deposited thin film layer.

The target <NUM> has at least a surface portion made of a material to be sputter deposited on substrate <NUM>. In one example, a pulsed DC, RF and/or a pulsed RF bias signal is applied to the target <NUM> by a second power source <NUM>. The pulsed DC, RF and/or pulsed RF bias signal enables the deposition of an optional non-conductive layer, such as a PZT or aluminum nitride layer. In order to attract the ions generated by the plasma <NUM> to sputter the target <NUM>, the target <NUM> may be biased by the second power source <NUM> to provide an average power of <NUM> to <NUM> kW, for example. The pulsed DC and/or RF bias signal applied to the target <NUM> may include a signal that has a plurality of alternating first and second intervals (detailed below). Each of the first intervals, the voltage of the applied bias signal is negative to attract ions to sputter the target <NUM>. During the alternating second interval, the applied bias signal is lower than the bias applied during the first interval, unbiased (e.g., zero applied voltage). In some examples, the applied bias signal has a positive voltage to repel positively charged ions from the target <NUM> to reduce arcing.

One skilled in the art will appreciate that the pulsed bias signal applied to the target <NUM> can provide many beneficial processing advantages, depending upon the particular application. For example, the pulsed bias signal may be used to reduce the deposition rate, form plasma <NUM>, and increase the peak energy in the plasma <NUM> for effectively controlling a plasma chemistry to form a film stack <NUM> (illustrated in <FIG>). For example, thin film layers which are closer to stoichiometric proportions might be obtained when a pulsed biasing signal is applied to the target <NUM>. Still other possible features include an increase in thin film quality, particularly for the film stack <NUM>. Additionally, thin film sheet resistance may be reduced, due to possible elimination of undesirable micro voids and columnar structures, when a pulsed bias is applied. It is appreciated that in some examples, a non-pulsed biasing signal may be applied to bias the target <NUM> during one or more parts of the deposition process, or in combination with a pulsed bias signal. The non-pulsed biasing signal can be a constant DC or an RF power level bias signal.

The substrate <NUM> mounted on the pedestal <NUM> can be biased to attract or repel ions generated in the formed plasma <NUM>. For example, the first power supply <NUM> may be provided to apply RF power to the pedestal <NUM> to bias the substrate <NUM> to attract deposition material ions during the deposition process. In addition, the first power supply <NUM> may be configured to apply RF power to the electrode <NUM> of pedestal <NUM> to couple supplemental energy to the plasma <NUM>. During the deposition process, the pedestal <NUM> may be electrically floating. Accordingly, a negative DC bias may nonetheless develop on the pedestal <NUM>. Alternatively, the pedestal <NUM> may be biased by a source at a voltage of between -<NUM> Volts to +<NUM> Volts, such as about -<NUM> VDC. For example, the pedestal <NUM> may be biased in order to bias the substrate <NUM>, attracting the ionized deposition material to the substrate <NUM>. In some configurations, a capacitor tuner (not shown) can be used with the second power source <NUM> to control the floating potential on the substrate <NUM> during processing. In an alternative example, the substrate <NUM> may be left floating electrically.

If the first power supply <NUM>, used to bias the substrate <NUM> through the pedestal <NUM>, is an RF power supply, the supply may operate at a frequency of about <NUM> to about <NUM>. The pedestal <NUM> may be supplied with RF power in a range of <NUM> watts to <NUM> kW. A computer-based controller <NUM> may be programmed to control the power levels, voltages, currents and frequencies. Accordingly, it is understood that the above-mentioned power level, voltage level, and frequencies may vary according to the program.

The vacuum pumping system <NUM> includes a pump assembly <NUM> and valve <NUM>. The pump assembly <NUM> may include a cryopump, roughing pump(s) (not shown) that are used to maintain a desirable pressure in the interior volume <NUM> of the processing chamber <NUM>.

The magnetron <NUM> is disposed adjacent to and is rotated relative to the target <NUM>. A plurality of magnets <NUM> is included in the magnetron <NUM>. The plurality of magnets <NUM> include plural polarized magnets N, and plural magnets S having an opposite polarization to magnets N. The magnets <NUM> are used to confine plasma <NUM> generated in the interior volume <NUM> by biasing the target <NUM> using the second power source <NUM> to sputter material from a front surface <NUM> of the target <NUM>. The second power source <NUM> has a second power supply <NUM> that is configured to deliver DC and/or RF power to the target <NUM>. In some example, delivery of RF power to the second power source <NUM> may also include a match circuit <NUM>.

The magnetron <NUM> can be tilted with respect to a surface of the target <NUM>, such as the front surface <NUM> or back surface <NUM>. In other words, the magnetron <NUM> forms an angle <NUM> with respect to a central axis <NUM> or the axis of rotation of the magnetron <NUM>. The tilting of the magnetron <NUM> at an angle <NUM> may be controlled by the controller <NUM> via the motor <NUM>. The degree of the tilting of the magnetron <NUM> may be adjusted between processing batches, between substrates <NUM>, or in-situ during the processing of the substrate(s) <NUM>. The angle <NUM> at which the magnetron <NUM> is tilted may be controlled based on thin film thickness or stress data feedback. The specific component of the magnetron <NUM> that is tilted at the angle <NUM> with respect to the target <NUM> may vary. In one example, the longitudinal dimension of the backing plate <NUM> (e.g., yoke) is tilted at the angle <NUM> with respect to the target <NUM>. In one example, a plane <NUM> (e.g., parallel to the X-Y plane) defined by lower ends of magnets <NUM> facing the back surface <NUM> of the target <NUM> is tilted at the angle <NUM> with respect to the target <NUM>. In one example, the magnetron <NUM> is tilted with respect to the back surface <NUM> of the target <NUM>. In another example, the magnetron is tilted with respect to the front surface <NUM>.

In one embodiment, when the magnetron <NUM> is rotated about the central axis <NUM> by a rotation motor <NUM> during processing, the angle <NUM> is maintained between the magnetron <NUM> and the target <NUM>, such that any point on the magnetron <NUM>, as is rotated about the central axis <NUM>, will remain the same vertical distance (i.e., Z-direction distance) from a surface of the target <NUM>, such as the back surface <NUM>. As the magnetron <NUM> rotates, the strength of the magnetic field produced by the magnetron <NUM> is an average of the various strengths of magnetic fields produced by each magnet <NUM>. The magnetic field is averaged across the front surface <NUM> of the target <NUM>. The averaging of the strengths of the magnetic fields enables uniform thin film properties and uniform erosion of the target <NUM>.

The angle <NUM> is determined by establishing an angle between the back surface <NUM>, as shown in <FIG>, of the target <NUM> and the plane <NUM> of the magnetron <NUM>. Another manner of determining the angle <NUM> is establishing an angle between the front surface <NUM> of the target <NUM> and the plane <NUM> of the magnetron <NUM>. For simplicity, any discussion of the angle <NUM> formed between the magnetron <NUM> and the target <NUM>, necessarily include the surfaces <NUM> or <NUM> of the target <NUM> and the plane <NUM> of the magnetron <NUM>. The angle <NUM> formed between the magnetron <NUM> and the target <NUM> may be from about <NUM> degrees to about <NUM> degrees. In another example, the angle <NUM> is from about <NUM> degree to about <NUM> degrees. If the angle <NUM> of the tilting of the magnetron <NUM> with respect to the target <NUM> is less than about <NUM> degrees, the effect of the averaging of the magnetic fields strengths can be diminished. As noted, the angle <NUM> of the tilted magnetron <NUM> with respect to the target <NUM> is less than or equal to about <NUM> degrees. Accordingly, the magnetron <NUM> and the central axis <NUM> form an acute angle (not labelled) ranging from about <NUM> degrees to about <NUM> degrees. The acute angle may range from about <NUM> degrees to about <NUM> degrees. A sum of the angle <NUM> and the acute angle is typically <NUM> degrees.

A first gas source <NUM> supplies a gas to the chamber <NUM> through a mass flow controller <NUM>. One example of the gas is a chemically inactive noble gas, such as argon (Ar). The gas can be admitted to the top of the chamber <NUM>, or as illustrated, at the bottom of the chamber <NUM>. One or more inlet pipes (not illustrated) penetrate apertures through the bottom of a second shield <NUM>. Alternatively, inlet pipes may be coupled to apertures within the pedestal <NUM>. During PVD processes, a nitrogen (N) gas may be delivered from a second gas source <NUM> to form a layer on the substrate <NUM>. The layer may include a material such as aluminum nitride (AIN).

<FIG> is a cross sectional view of another processing chamber <NUM> adapted to process the substrate in the cluster tool illustrated in <FIG>. An example of the processing chamber <NUM> useful for the present disclosure is the Pre-Clean II Chamber available from Applied Materials, Inc. , Santa Clara, CA.

The pre-clean chamber <NUM> has a substrate support assembly <NUM> disposed in a chamber enclosure <NUM> under a dome <NUM>. In one example, the dome <NUM> may be made from quartz. The pedestal <NUM> includes the substrate support assembly <NUM> having a substrate support <NUM>. The substrate support <NUM> is disposed within a recess <NUM> on the substrate support assembly <NUM>. During processing, the substrate <NUM> is placed on the substrate support <NUM>. At least one locating pin <NUM> retains the substrate in a desired lateral position on the substrate support <NUM>.

A coil <NUM> is disposed outside of the dome <NUM> and connected to an RF power source <NUM>. The RF power source <NUM> initiates and maintains a plasma formed from the process gases within the processing chamber <NUM>. An RF match network <NUM> is provided to match the RF power source <NUM> and the coil <NUM>. The substrate support assembly <NUM> is connected to a DC power source <NUM> that provides a bias to the substrate support assembly <NUM>.

The substrate <NUM> may be pre-cleaned or etched using the plasma in the processing chamber <NUM> prior to depositing one or more layer within a film stack <NUM>, as shown in <FIG>. Once the substrate <NUM> is positioned for processing in the processing chamber <NUM>, a processing gas is introduced into the interior volume <NUM>. The processing gas may include between about <NUM>% and about <NUM>% hydrogen (H) and the balance a carrier gas. The processing gas may be between about <NUM>% and about <NUM>% of H.

The processing gas can include a carrier gas, such as Ar or helium (He), at a concentration of between about <NUM>% and about <NUM>%. The processing gas is ignited in the interior volume <NUM> to form the plasma, thus subjecting the substrate <NUM> to the plasma. For example, plasma may be generated by applying between about <NUM> W and about <NUM> W of power from the RF power source <NUM> to the coil <NUM>. The DC power source <NUM> may also provide power between about <NUM> W and about <NUM> W of DC bias power. The plasma may be maintained for a period between about <NUM> seconds and about <NUM> seconds. Once the pre-cleaning process is completed, processing chamber <NUM> is evacuated to exhaust the processing gas and the reacted byproducts from the processing chamber <NUM>.

<FIG> is a side view of an exemplary film stack <NUM> produced within the cluster tool disclosed in <FIG>. The film stack <NUM> may include the substrate <NUM>, an optional seed layer <NUM>, and a bulk layer <NUM>. In an alternate embodiment, the bulk layer <NUM> is formed on top of and in contact with a surface of the substrate <NUM>. The bulk layer <NUM> may include one or more interlayer(s) <NUM>, where each interlayer <NUM> may be expressed as <NUM>(n), where n is the number of interlayers <NUM> in the bulk layer <NUM> that may vary from <NUM> to n. For example, while n=<NUM> in the example illustrated in <FIG>, in an alternate example, n is from <NUM> to <NUM>, or even <NUM> to <NUM>.

In one example, the bulk layer <NUM> is scandium-doped aluminum nitride (ScAIN). In another example, the bulk layer <NUM> is AIN. The substrate <NUM>, in some examples, has a crystal orientation of <<NUM>>. The substrate <NUM> may include other layers having an appropriate lattice, including but not limited to a polycrystalline molybdenum, and AIN.

<FIG> is a flow chart depicting an exemplary method <NUM> of producing the film stack <NUM> within the cluster tool illustrated in <FIG>.

At block <NUM>, the substrate <NUM> is loaded into the loading dock <NUM> of the cluster tool <NUM>. In an example, the first robot <NUM> moves the substrate <NUM> to the orient chamber <NUM>. The substrate <NUM> is passed through the first transfer chamber <NUM> by the first robot <NUM>. The robot <NUM> in the first transfer chamber <NUM> moves the substrate <NUM> from the orient chamber <NUM> to the first processing chamber <NUM>. As stated above, pressure (P) in the first transfer chamber <NUM> may be about <NUM> microTorr. Accordingly, the pressure is held in a vacuum state. As detailed above, process gas is supplied to first processing chamber <NUM>.

Optionally, at block <NUM>, the seed layer <NUM> is formed on the substrate <NUM>. During block <NUM> the substrate <NUM> is heated within a heated process chamber (e.g., degas chamber <NUM>) to a desired first temperature (e.g., temperature between <NUM> to <NUM>) and then a seed layer is formed on the substrate in a second processing chamber <NUM> at a second processing temperature (e.g., temperature less than or substantially equal to the degas temperature). The seed layer <NUM> can be formed in the second processing chamber that includes the components shown in processing chamber <NUM>. The process performed during block <NUM> may include delivering a pulsed DC, RF and/or a pulsed RF bias signal to the target <NUM> by the second power source <NUM> to form a sputtered material layer. In one example, the incoming substrate temperature to the second processing chamber, and thus substrate processing temperature, is greater than room temperature, such as between about <NUM> and about <NUM>. In one example, the seed layer <NUM> has a thickness from about <NUM> to about <NUM>. It has been found that, by maintaining a high initial temperature (e.g., degas temperature), defects formed in the seed layer <NUM> decrease.

At block <NUM>, the bulk layer <NUM> is formed on or over the substrate <NUM>. As noted above, process gas is supplied to the second processing chamber <NUM>. The bulk layer <NUM> can be formed in the second processing chamber <NUM> that includes the components shown in processing chamber <NUM>. The bulk layer <NUM> includes at least one interlayer <NUM> that is formed on or over the substrate <NUM> in the second processing chamber <NUM>. In one example, a first interlayer <NUM>(<NUM>) of the bulk layer <NUM> can be formed to a thickness from about <NUM> microns to <NUM> micron. In one example, the bulk layer <NUM> can be formed to a total thickness from about <NUM> to <NUM> microns, or such as about <NUM> microns to <NUM> microns. In another example, the bulk layer <NUM> can be formed to a total thickness of about <NUM> microns to about <NUM> microns. In yet another example, the bulk layer <NUM> can be formed to a total thickness of about <NUM> microns to about <NUM> microns, or a total thickness of about <NUM> microns to about <NUM> microns, or a total thickness of about <NUM> microns to about <NUM> micron. In an alternative example, the bulk layer <NUM> can be any desired thickness between about <NUM> microns to about <NUM> microns However, the thickness of the bulk layer <NUM> is not limited to this range and may be deposited on the substrate <NUM> to any desired thickness.

In some embodiments, the bulk layer <NUM> is formed on the substrate during block <NUM> may include two or more processing steps, such as blocks <NUM>-<NUM> as shown in <FIG>. In some embodiments, the first interlayer <NUM>(<NUM>) of the bulk layer <NUM> is formed at a temperature between about room temperature (~<NUM>) and about <NUM>. In some embodiments, the first processing chamber <NUM> is maintained at room temperature when the film stack <NUM> is cooled in the first processing chamber <NUM>. In some embodiments, the bulk layer <NUM> is formed in an environment including Ar and N. In one example, the ratio of Ar to N may be about <NUM> to <NUM> by volume. In another example, the ratio of Ar to N may be about <NUM> to <NUM> by volume. During block <NUM> the first power supply <NUM> applies a first power bias P1 to the substrate <NUM> using the electrode <NUM> for a first duration of time (t1). A first interlayer <NUM>(<NUM>) is formed on the film stack <NUM>. A first bias power P1 is between about <NUM> Watts and about <NUM> Watts.

A second interlayer <NUM>(<NUM>) is formed on top of and in contact with the first interlayer <NUM>(<NUM>), at block <NUM>. In one example, a second interlayer <NUM>(<NUM>) of the bulk layer <NUM> can be formed to a thickness from about <NUM> microns to <NUM> micron. A second power bias P2 is applied to the substrate <NUM> through the electrode <NUM> from the first power supply <NUM>, for a second duration of time (t2). The first duration of time is between about <NUM> second and about <NUM> seconds. In another example, the first duration of time and the second duration of time is between about <NUM> second and about <NUM> seconds, such as about <NUM> second and <NUM> seconds, or such as about <NUM> second and <NUM> seconds. The second duration of time is greater than <NUM> seconds and less than or equal to about <NUM> seconds. In one example, the first time may be about <NUM> seconds and the second time can be about <NUM> seconds. A second bias power P2 is less than about <NUM> Watts and greater than or equal to <NUM> watts. For example, the first bias power P1 may be about <NUM> watts and the second bias power P2 may be about <NUM> watt. In another example, the second bias power P2 can be about <NUM> Watts.

The first interlayer <NUM>(<NUM>) and the second interlayer <NUM>(<NUM>) are formed in the same second processing chamber <NUM>. In an alternative example, the first interlayer <NUM>(<NUM>) may be formed in one of the second processing chamber <NUM>, and the second interlayer <NUM>(<NUM>) may be formed in a different second processing chamber <NUM> of the cluster tool <NUM>. Accordingly, in at least one example, the first bias power P1 is higher than the second bias power P2. In the same example, the second duration of time (t2) is greater than the first duration of time (t1). An exemplary frequency of either the first bias power P1 or second bias power P2 is about <NUM>. In some embodiments, the process recipe parameters, or process variables, used to deposit the first interlayer <NUM>(<NUM>) are different from the process recipe parameters used to deposit the second interlayer <NUM>(<NUM>). In one example, a process used to deposit the first interlayer <NUM>(<NUM>) and a process used to deposit the second interlayer <NUM>(<NUM>) have at least one process parameter that is different, wherein the at least one process parameter is selected from a group consisting of deposition process pressure, bias power and the deposition process time.

At block <NUM>, the temperature of the film stack <NUM> is reduced. Prior to reducing the temperature at block <NUM>, the film stack <NUM> includes at least the substrate <NUM> and the bulk layer <NUM>. In one example, the film stack <NUM> is transferred from the second processing chamber <NUM> to the first processing chamber <NUM> in order to cool the film stack <NUM>. The first processing chamber <NUM> may be maintained at a reduced temperature, when the substrate <NUM> is cooled in the first processing chamber <NUM>. In another example, the film stack <NUM> is not transferred to the first processing chamber <NUM>, but is subject to the reduced temperature in the second processing chamber <NUM>. The reduced temperature may be achieved by removing heat from the interior volume <NUM>, e.g., by discontinuing the supply of power to the second power source <NUM> or chucking the substrate <NUM> to the cooled pedestal <NUM>. In another example, the bulk layer <NUM> may be deposited in interlayer pairs <NUM>. Each interlayer pair <NUM> may be expressed as <NUM>(n), where n is the number of interlayers <NUM> in the bulk layer <NUM> that may vary from <NUM> to n. For example, while n=<NUM> in the example illustrated in <FIG>, in an alternate example, n is from <NUM> to <NUM>. As shown, a first interlayer pair <NUM>(<NUM>) includes the first interlayer <NUM>(<NUM>) and the second interlayer <NUM>(<NUM>). At block <NUM>, the temperature of the film stack <NUM> may be reduced between successive interlayer pairs <NUM> (e.g. <NUM>(n) and <NUM>(n+<NUM>)). In yet another example, the temperature at block <NUM> may be reduced after deposition of the interlayer <NUM>(n) at block <NUM> before deposition of another interlayer <NUM>(n+<NUM>) at block <NUM>. In this example, the <NUM> is cooled between a depositions of the interlayer <NUM>(n) at block <NUM> and a deposition of interlayer <NUM> (n+<NUM>) at block <NUM>.

In one example, the film stack <NUM> temperature can be reduced by pausing the deposition process for a period time, Δtcool. Plasma is not directed to film stack <NUM> while deposition is paused. The deposition may be paused for a period of time Δtcool from about <NUM> second to about <NUM> seconds, such as about <NUM> seconds to about <NUM> seconds. The period of time, Δtcool, may be referred to as pausing period of time when the deposition process is paused. In another example, the period of time Δtcool at which deposition is paused is between about <NUM> seconds and <NUM> seconds. In another example, the period of time Δtcool is less than or equal to about <NUM> seconds. The period of time Δtcool can be from about <NUM> seconds and about <NUM> seconds. In yet another example, when deposition of the film stack <NUM> is paused, the period of time Δtcool can be paused for any desired period of time between about <NUM> second to about <NUM> seconds, incremented by <NUM> second.

When the film stack <NUM> is actively cooled, the substrate <NUM> of the film stack <NUM> is placed on top of and in direct contact with a temperature regulated body, such as the substrate support <NUM>. Alternatively, the film substrate <NUM> may be placed on top of and in direct contact with the electrostatic chuck <NUM>. The substrate support <NUM> or the electrostatic chuck <NUM> may have a temperature lower than the substrate <NUM>, and thus can be used to actively cool the substrate <NUM>. The temperature is reduced for the period time, Δtcool. The period of time Δtcool can be any period of time from about <NUM> second to about <NUM> seconds. In one example, the period of time Δtcool is between about <NUM> seconds and <NUM> seconds. In another example, the period of time Δtcool is about <NUM> seconds. As the period of time Δtcool increases, stress (MPa) decreases between the crystal structures in the film stack <NUM>. As stated above, the substrate <NUM>, and therefore the film stack <NUM>, can be cooled in an environment that includes Ar and N<NUM>. In one example, the period of time Δtcool at which the film stack <NUM> is cooled is less than the period of time needed to deposit the interlayer <NUM>. In another example, the period of time Δtcool at which the film stack <NUM> is cooled is equal to or greater than the period of time needed to deposit the interlayer <NUM>. In yet another example, when the film stack <NUM> is actively cooled, the period of time Δtcool can be any desired period of time between about <NUM> second to about <NUM> seconds, incremented by <NUM> second. Applicant notes that the film stack <NUM> can be actively cooled for the same periods of time Δtcool as deposition of the film stack <NUM> is paused, as described above.

After the film stack <NUM> is processed to form a bulk layer <NUM> that has a desired thickness by performing one of more of the blocks <NUM>-<NUM> multiple times, according to the method <NUM> disclosed herein, the film stack <NUM> may be returned factory interface <NUM>. In one example, the sequence of blocks <NUM>-<NUM> were performed at least two times, such as at least four times, or even at least <NUM> times. The substrate <NUM> may be moved from the second processing chamber <NUM>, and transferred to the first processing chamber <NUM>. The film stack <NUM> may then be transferred from the first processing chamber <NUM> to the loading dock <NUM> by the first robot <NUM>. Subsequently, the film stack <NUM> may be returned to the factory interface <NUM>.

<FIG> is a graph illustrating how a stress profile across the substrate <NUM> changes with respect to a cooling time during the formation of a series of interlayers <NUM> using a desirable process sequence, such as performing the sequence of blocks <NUM>-<NUM> multiple times.

The graph <NUM> illustrates the effect of increasing cooling time (e.g. Δtcool) at block <NUM> on radially measured stress values across the film stack <NUM>. Lines <NUM>-<NUM> represent the stress profile radially across the substrate <NUM> for the bulk layer <NUM> deposited after performing block <NUM>. Each line <NUM>-<NUM> demonstrates a stress profile across the surface of the substrate <NUM>, at different cooling times. For example, line <NUM> represents a stress profile in a film stack <NUM> where the process(es) performed during block <NUM> include the use of a cooling time of about <NUM> seconds. Line <NUM> demonstrates a stress profile in a film stack <NUM> where a cooling time of about <NUM> seconds is used during block <NUM>. The line <NUM> represents a stress profile in a film stack <NUM> where the process(es) performed during block <NUM> include the use of a cooling time of about <NUM> seconds. In at least one example, the cooling time is about <NUM> seconds during block <NUM>. A comparative example <NUM>, demonstrates the stress profile across the substrate <NUM> when portions of the bulk layer <NUM> are deposited without the intervening reduction in temperature during block <NUM> between deposition steps. Stated differently, no cooling time is introduced during the formation of layers in the formation of the comparative example <NUM>.

As illustrated in <FIG>, as the cooling time increases, the variations in center-to-edge stress profile decreases (e.g. a standard deviation) and the average or mean stress profile across the substrate <NUM> decreases. For example, in the comparative example <NUM>, a maximum stress value is about <NUM> and a minimum stress value is about <NUM>. However, a maximum value 612a of line <NUM> is about <NUM> and a minimum value 612b is at about <NUM>. Comparing the maximum value 612a and minimum value 612b in the line <NUM> to the maximum stress value and minimum stress value of the comparative example <NUM> demonstrates an average reduction in stress across the substrate <NUM> as cooling time increases. Additionally, as shown in line <NUM>, at the center of the substrate <NUM> (i.e. where substrate <NUM> radius is <NUM>), when the cooling time is about <NUM> seconds, there is a <NUM>% drop in stress with respect to the comparative example <NUM>. Line <NUM> illustrates that when the cooling step is about <NUM> seconds, there is a <NUM>% drop in stress. Line <NUM> demonstrates about a <NUM>% drop in stress, with respect to the comparative example <NUM>. It is understood that these examples are only illustrative and incorporate other examples not specifically detailed herein, based upon the differences between the lines <NUM>-<NUM>, and differences between the lines <NUM>-<NUM> and the comparative example <NUM>.

<FIG> illustrates the degree of crystallization variation in a thin film layer formed from multiple successive interlayers <NUM> that were formed with a varying intermediate cooling step (i.e., block <NUM>).

The curves shown in <FIG> are examples of rocking curves. A rocking curve, which are typically formed by use of an XRD inspection process, is able to detect the presence of one or more crystal orientations in a deposited film layer formed from multiple interlayers <NUM>. The results of the generated rocking curves enables one to identify attributes of defects found in a formed layer, such as dislocation density, mosaic spread, curvature, misorientation of adjacent crystalline structures, and crystalline inhomogeneity. Measuring a peak of a given rocking curve corresponds to the regularity of the atomic spacing (i.e., d-spacing), which describes a distance between planes of atoms in the crystal structure of a given interlayer <NUM>(n). Measuring the relative amplitude of the peak may also provide parameters such as composition, strain, and relaxation. A graph <NUM> includes a curve <NUM> of the bulk layer <NUM> that was generated by reducing the temperature between formation of successive interlayers (e.g. <NUM>(n) and <NUM>(n+<NUM>)), utilizing the method of block <NUM> through block <NUM> multiple times. Curve <NUM> was formed with an interlayer deposition time of about <NUM> seconds that are performed about <NUM> times. Otherwise stated, the curve <NUM> shows the formation of about <NUM> interlayers <NUM>. Accordingly, the curve <NUM> has a single peak <NUM> indicating that an interface of two adjacent groups of successive interlayers <NUM> and formed interlayers <NUM> have substantially the same crystal orientation. For example, a first group of interlayers can be interlayer <NUM>(<NUM>) and interlayer <NUM>(<NUM>), and the cooling time at block <NUM> occurs between interlayer <NUM>(<NUM>) and interlayer <NUM>(<NUM>).

While this graph shows a configuration of <NUM> groups of successive interlayers <NUM>, it has been found that forming more than about <NUM> groups of successive interlayers <NUM>, with a block <NUM> process step interposed between each deposition step, achieves a film stack <NUM> having similar properties as illustrated in the curve <NUM>. Additionally, it has been found that the cooling time between adjacent groups of successive interlayers <NUM> can be from about <NUM> to about <NUM> seconds. Each interlayer <NUM> represented in the curve <NUM> was deposited for a period of time between about <NUM> seconds to about <NUM> seconds.

A comparative example <NUM> is another curve that was generated on a bulk film layer (not shown) that included two interlayers <NUM> deposited for a first period and a second period of time. The comparative example <NUM> is deposited in two depositions without interim cooling of the substrate <NUM> at block <NUM>. The first period is about <NUM> seconds or greater, and a second period being about <NUM> seconds or greater. In the comparative example <NUM>, a first peak <NUM> and a second peak <NUM> indicate that an interface of two successive interlayers <NUM> have a different crystal orientation, which may originate from small angle grain boundaries at the interface or each interlayer <NUM>. As illustrated, the comparative example <NUM> shows a first peak <NUM> between angle <NUM> and angle <NUM>. The first peak <NUM> has a value of about <NUM>. A second peak <NUM> is shown in the comparative example <NUM> between angle <NUM> and angle <NUM>. The second peak <NUM> has a value of about <NUM>. The dual peak (i.e. first peak <NUM> and second peak <NUM>) of the comparative example <NUM> demonstrates the undesirable presence of variation in the crystal orientation between a first interlayer <NUM>(n) and a second interlayer <NUM>(n+<NUM>).

The curve <NUM> demonstrates a thin film layer that includes a single peak <NUM> between angle <NUM> and angle <NUM>. The single peak <NUM> in curve <NUM> indicates a greater crystal orientation uniformity at the interface of successive interlayers <NUM> with respect to the comparative example <NUM>. It is believed that when forming the bulk layer <NUM> at blocks <NUM>-<NUM>, as the number of cycles increases (<NUM>-<NUM>), the number of defects at the interface of successive interlayers <NUM> decreases. As the number of cycles increases to between about <NUM> cycles and between about <NUM> cycles, the defects between the successive interlayers <NUM> significantly diminishes such that the single peak <NUM> remains. For example, when the number of cycles increases above about <NUM>, the single peak <NUM> is formed. The interface of the successive interlayers <NUM> becomes smoother, such that the crystal orientation between successive interlayers <NUM> creates an average slope of about <NUM> degrees on the rocking curve of graph <NUM>.

<FIG> is a plan view of a controller <NUM> that can provide instructions to the any one of the processing chambers depicted in <FIG>.

An optional display unit <NUM> may be coupled to the controller <NUM>. The controller <NUM> includes a processor <NUM>, a memory <NUM>, and support circuits <NUM> that are coupled to one another. The controller <NUM> may be on-board the cluster tool <NUM>, or in an alternative example, the controller <NUM> may be on-board one of the processing chambers in <FIG> or <FIG>, or a remote device (not shown).

The display unit <NUM> includes an input control unit, such as power supplies, clocks, cache, input/output (I/O) circuits, coupled to the various components of the display unit <NUM> to facilitate control thereof. The processor <NUM> may be one of any form of general purpose microprocessor, or a general purpose central processing unit (CPU), each of which can be used in an industrial setting, such as a programmable logic controller (PLC).

The memory <NUM> is non-transitory and may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), or any other form of digital storage, local or remote. The memory <NUM> contains instructions, that when executed by the processor <NUM>, facilitates the operation of any of the processing chambers illustrated in <FIG>. The instructions in the memory <NUM> are in the form of a program product such as a program that implements the method of the present disclosure. The program code of the program product may conform to any one of a number of different programming languages. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are examples of the present disclosure.

Claim 1:
A method of forming a piezoelectric film, comprising:
(a) depositing a first piezoelectric film layer on a surface of a substrate by a first physical vapor deposition, PVD, process;
(b) depositing a second piezoelectric film layer, on top of and in contact with the first piezoelectric film layer, by a second physical vapor deposition, PVD, process;
(c) reducing a temperature of the substrate after forming the first piezoelectric film layer and before forming the second piezoelectric film layer, wherein the temperature is reduced by performing a process for a first period of time; and
additionally performing processes (a), (b) and (c) one or more times, wherein process (c) in the additionally performed processes (a), (b) and (c) is performed for a second period of time, and the second period of time being different than the first period of time;
wherein the first PVD process and the second PVD process are sputtering processes.