Patent Description:
Many functions of an advanced electronic device, such as a mobile phone, are implemented in a system-on-a-chip (SoC) integrated circuit. The SoC consumes current that changes with the number and kind of operations it performs. Descriptions of an element in terms of current or power are interchangeable after scaling by a respective voltage. The operations performed can change rapidly, for example, a few nanoseconds. The change in current consumption can be large, for example, a few amps. This results in a large current time derivative (dI/dt) that can interfere with operation of the SoC.

A power distribution network supplies power, for example, as a voltage supply, to the SoC. The SoC may be packaged in an integrated-circuit package that may be mounted on an interconnection substrate, such as a printed circuit board, for connection with other components including, for example, a power supply and battery. The power distribution network includes connections through the printed circuit board and integrated-circuit package. The connections of the power distribution network can have substantial parasitic inductance. This inductance combined with the large current time derivatives can cause large spike-like dips in the supply voltage, also referred to as droop, in the voltage supplied to the SoC. The droop can be so large as to interfere with proper operation of the device.

The voltage level supplied to the SoC is generally increased (which may be referred to as guardbanding) by the amount of voltage droop so the "drooped" voltage is sufficient for proper operation of the SoC. Guardbanding the voltage level increases power consumption and is undesirable, for example, due to increased temperature and decreased battery duration. Some prior systems have attempted to reduce the voltage droop, for example, by reducing inductance in the power distribution network or adding decoupling capacitors on or close to the SoC. For example, external landside capacitors (LSCs) and embedded-passive-substrate (EPS) capacitors may be added during routing of the PDN. Added decoupling capacitors may only slightly reduce the voltage droop. Additionally, they can be size and cost prohibitive. Attention is drawn to document <CIT> which relates to a hybrid regulator in which a switching regulator and a series regulator are inter-connected. In the hybrid regulator, most of the current required for a load is supplied from the switching regulator which has a poor regulation performance while having high efficiency. The hybrid regulator also includes a sensing unit for the rapid sensing of the current supplied to the load. Based on the operation of the sensing unit, the series regulator, which has a poor power efficiency while exhibiting an excellent regulation performance, supplies or absorbs only a small amount of ripple current. The series regulator serves as an independent voltage source whereas the switching regulator serves as a dependent current source. Further attention is drawn to document <CIT> which relates to a voltage regulation circuit includes a DC-DC converter configured to control a first current provided from a source to a load via a first output, and a linear regulator configured to control a second current provided from the source to the load via a second output. The voltage regulation circuit further includes a single control loop configured to receive an output voltage across the load and a first reference voltage. The single control loop is further configured to generate a single error signal between the output voltage across the load and the first reference voltage and to control the DC-DC converter and the linear regulator using the single error signal such that when the single error signal is outside of a predetermined range the DC-DC converter provides the first current to the load and the linear regulator provides the second current to the load simultaneously. Document <CIT> relates to a switched mode assisted linear (SMAL) amplifier/regulator architecture which may be configured as a SMAL regulator to supply power to a dynamic load, such as an RF power amplifier. A SMAL regulator includes configurations in which a linear amplifier and a switched mode converter (switcher) parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched mode converter are cooperatively controlled to supply load current. The amplifier may include separate feedback loops: an external relatively lower speed feedback loop may be configured for controlling signal path bandwidth, and an internal relatively higher speed feedback loop may be configured for controlling output impedance bandwidth of the linear amplifier. The linear amplifier may be AC coupled to the supply node, and the switched converter is configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control. Document <CIT> relates to a transient response circuit for a step-down DC to DC converter having a DC input and a DC output. The transient response circuit includes a high pass filter for detecting transients at the DC output of the DC to DC converter, a first comparator responsive to the high pass filter for providing a first comparator output that is active when the high pass filter detects a negative transient that is less than a first threshold voltage, a second comparator responsive to the high pass filter for providing a second comparator output that is active when the high pass filter detects a positive transient that is greater than a second threshold voltage, a first switching circuit responsive to the first comparator for providing a current path between the input of the DC to DC converter and the output of the DC to DC converter when the first comparator output is active, and a second switching circuit responsive to the second comparator for providing a current path between the output of the DC to DC converter and a ground reference potential when the second comparator output is active.

Further embodiments of the invention are defined by the appended dependent claims.

The present invention is advantageous in view of the background art in that it supplies current to a load device in response to high-frequency changes in the voltage on a power rail such as a droop due to rapid changes in the current demand of the load device.

Other features and advantages of the present invention should be apparent from the following description which illustrates, by way of example, aspects of the invention.

The details of the present invention, both as to its structure and operation, may be gleaned in part by study of the accompanying drawings, in which like reference numerals refer to like parts, and in which:.

The detailed description set forth below, in connection with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. In some instances, well-known structures and components are shown in simplified form in order to avoid obscuring such concepts.

<FIG> is a schematic diagram of a model of a power distribution network (PDN). The PDN may be segregated into interconnect domains corresponding to a die domain <NUM>, a package domain <NUM>, a power-supply domain <NUM>, and a circuit-board domain <NUM>. Each of the PDN interconnect domains includes respective combinations of resistances, capacitances, and inductances that form a characteristic impedance for that domain. The resistances, capacitances, and inductances may be referred to as parasitic elements. These parasitic elements may be aggregated into equivalent component values of resistance, capacitance, and inductance that are present between components mounted within the PDN interconnect domains. For example, the circuit-board domain <NUM> may contribute series inductance due to the traces conducting current from a battery <NUM> to a power supply <NUM> in the power-supply domain <NUM>. The components within the PDN interconnect domains may have equivalent values of resistance, capacitance, and inductance that interact electrically with the parasitic elements of the PDN interconnect domains.

In the PDN model of <FIG>, the circuit-board domain <NUM> includes a circuit-board-inter-planar capacitance <NUM> that may aggregates per unit length of interconnect traces across the interconnect substrate. The interconnect traces also contribute a circuit-board-equivalent-series resistance <NUM> and a circuit-board-equivalent-series inductance (L-pcb) <NUM> that aggregate per unit length of the trace.

The battery-equivalent impedance includes an equivalent-battery-output resistance <NUM> in series between the battery <NUM> and the parasitic elements of the circuit-board domain <NUM>. The power supply <NUM> in the power-supply domain <NUM> receives power from the battery <NUM> through the equivalent-battery-output resistance <NUM>, the circuit-board-equivalent-series resistance <NUM>, and the circuit-board-equivalent-series inductance <NUM>. The power supply <NUM> includes an equivalent-power-supply-output resistance <NUM>. Other impedances of the power supply may be lumped into an equivalent-power-supply output impedance <NUM> including series inductance, resistance, and capacitance. A power-supply-domain inductance <NUM> models the inductance encountered in routing traces between the power supply <NUM> and the package domain <NUM>.

In a fashion similar to that of the circuit-board domain <NUM>, the package domain <NUM> includes a package-inter-planar capacitance <NUM>, a package-equivalent-series inductance <NUM>, and a package-equivalent-series resistance <NUM>. Each of these parasitic elements aggregates per unit length that the PDN runs through the package domain <NUM>. The die domain <NUM> is modeled with an equivalent-load impedance <NUM> and a switched-equivalent-load impedance <NUM>. The equivalent-load impedance <NUM> represents portions of the SoC (which from a power distribution network viewpoint may be referred to as the load) that are not switching and/or portions of SoC circuitry that are in a continuous or standby operation. The switched-equivalent-load impedance <NUM> represents portions of SoC circuitry that are activated or deactivated according to particular operations of the SoC. A switch <NUM> symbolically represents the switched activity of the switched-equivalent-load impedance <NUM>.

<FIG> is a graph of the droop characteristic of a power distribution network in the time domain. The droop characteristic will be described with reference to the PDN of <FIG> but similar effects occur in other systems. The graph shows a supply voltage <NUM> at the SoC in the die domain <NUM>. The y-axis of the graph is voltage and the x-axis of the graph is time. Initially, the SoC draws a low level of current from the battery <NUM> via the power supply <NUM>. At time <NUM>, the SoC switches to drawing a high level of current. The low level of current is modeled by the switch <NUM> in the load model being open and the high level of current is modeled by the switch <NUM> being closed. Initially, the supply voltage <NUM> (at the load) is at a nominal voltage level. At time <NUM>, the current drawn by the load increases rapidly. This increase in current is satisfied by additional current from the battery <NUM> flowing through the circuit-board domain <NUM>, the package domain <NUM>, power-supply domain <NUM>, and the die domain <NUM>. The inductances in this path result in a spike-like dip <NUM> in the supply voltage <NUM>. The spike-like dip <NUM> may result in the supply voltage <NUM> dropping below a minimum level for proper operation of the SoC. For example, in some systems, a droop characteristic <NUM> may be as much as an <NUM>-<NUM>% drop in the supply voltage <NUM> for a <NUM> amp load-current transient occurring in a <NUM> ns timeframe.

<FIG> is a graph of impedance of a power distribution network in the frequency domain. The graph will be described with reference to the power distribution network of <FIG>; however, other networks result in similar impedances. The graph shows several impedance peaks that correspond to the respective impedances formed from parasitic elements in the respective PDN interconnect domains. A first impedance peak <NUM> corresponds to the current limiting impedances in the die domain <NUM>. The first impedance peak <NUM> may be primarily associated with the frequency dependent impedances seen by the portion of the PDN path on-die. The first impedance peak <NUM> may have a center frequency of about <NUM> and may be the largest impedance peak. A second impedance peak <NUM> corresponds to the current limiting impedances created by the parasitic elements formed as the PDN is routed through the package domain <NUM>. The second impedance peak <NUM> may have a center frequency of about <NUM>. A third impedance peak <NUM> corresponds to the current limiting impedances caused by the parasitic elements in the circuit-board domain <NUM>. The third impedance peak <NUM> may have a center frequency of about <NUM>-<NUM>. When variations in SoC currents occur at or near the frequencies of the impedance peaks, the effect of voltage droop is increased.

The system of <FIG> includes the power supply <NUM> between the battery <NUM> and the load device to provide voltage regulation and avoid droop characteristics. The power supply <NUM> may be a switching-mode power supply (SMPS) and provide power to the load device with the degree of supply voltage regulation that is available according to the regulating abilities of the SMPS. The SMPS may be implemented within the circuit-board domain <NUM> on a separate die from the load device and provide power through the circuit board interconnection layers to the SoC die (load device in the die domain <NUM>). The SMPS receives power from the battery <NUM>. The battery <NUM> connects to the SMPS through the circuit board. The SMPS is coupled to the die through the parasitic elements introduced by the interconnection path through the circuit-board domain <NUM> and the package domain <NUM>. These interconnection path parasitic elements correspond to the package-inter-planar capacitance <NUM>, the package-equivalent-series inductance <NUM>, the package-equivalent-series resistance <NUM>, and the power-supply-domain inductance <NUM> described above.

<FIG> is a graph of frequency responses of a switching-mode power supply (SMPS) and a low dropout voltage regulator (LDO). The graph includes a SMPS frequency response <NUM> and an LDO frequency response <NUM> plotted versus frequency. The SMPS frequency response <NUM> and the LDO frequency response <NUM> are plotted in terms of output power in <FIG>. Other measures, for example, current, may also be used. The frequency responses are generally flat at low frequencies and then decline at higher frequencies. The SMPS frequency response <NUM> may be described as having a SMPS corner frequency <NUM> where the power is attenuated by <NUM> dB (or a factor of two) and a corresponding SMPS bandwidth <NUM>. Similarly, the LDO frequency response <NUM> may be described as having a LDO corner frequency <NUM> and a corresponding LDO bandwidth <NUM>.

An exemplary SMPS may have a bandwidth of about <NUM>. Generally, the SMPS bandwidth <NUM> may occur at about one-fifth of the SMPS clock frequency. This bandwidth is not sufficient for the SMPS to supply rapidly changing power requirements that can occur in an SoC. The SMPS is, however, suited for supplying relatively large amounts of current with a high efficiency. For example, the SMPS may be able to supply <NUM> A with an efficiency of about <NUM>%.

An exemplary LDO may have a bandwidth of about <NUM>. This bandwidth is much better suited than the SMPS bandwidth for supplying rapidly changing power requirements that can occur in an SoC. The LDO is, however, less efficient than the SMPS. For example, an LDO that receives a <NUM> V input supply voltage and produces a <NUM> V output will have an efficiency less than <NUM>%.

<FIG> is a functional block diagram of an electronic system including a capacitively-coupled hybrid parallel power supply according to a presently disclosed embodiment. The system uses a hybrid parallel power supply to provide power to a load device <NUM>. The hybrid parallel power supply capacitively couples a power supply (e.g., a switching-mode power supply) with a voltage regulator (e.g., a low dropout voltage regulator). The hybrid parallel power supply combines advantageous features of both switching-mode power supplies and low dropout voltage regulators. The hybrid parallel power supply is power efficient and can supply a stable voltage to a load device, such as a smartphone SoC, whose current demand rapidly changes.

The hybrid parallel power supply includes a first power supply ("SMPS1") <NUM> connected in parallel with a voltage regulator ("LDO") <NUM>. The first power supply <NUM> supplies power to a power rail <NUM>. The first power supply <NUM> works to regulate the power rail <NUM> to a first target voltage level, for example, <NUM> V. The first target voltage level may be configurable, for example, using a control register. The first power supply <NUM> receives power from a first supply terminal <NUM> (e.g., connected to the battery <NUM> in the system of <FIG> via connections on a circuit board <NUM>). The first power supply <NUM> is able to supply power to the power rail <NUM> with high efficiency. The first power supply <NUM> may be a switching-mode power supply (SMPS).

The voltage regulator <NUM> also supplies power to the power rail <NUM> via a coupling capacitor <NUM>. The voltage regulator <NUM> works to regulate the power rail <NUM> to a second target voltage level. The second target voltage level may be configurable, for example, using a control register. The voltage regulator <NUM> has an input connected to a second supply terminal <NUM> from which the voltage regulator <NUM> receives power. The voltage regulator <NUM> has an output connected to a first terminal of the coupling capacitor <NUM>. A second terminal of the coupling capacitor <NUM> connects to the power rail <NUM>. The voltage regulator <NUM> is able to provide current with a high-frequency-response characteristic to the power rail <NUM>. The voltage regulator <NUM> may be a low dropout voltage regulator (LDO). An LDO can operate with low headroom (difference between the input voltage and output voltage), for example, regulating a <NUM> V input to produce a <NUM> V output.

The voltage regulator <NUM>, in an embodiment, operates with a Class-AB current mode output. Such circuits can have high bandwidths, for example, <NUM>. The Class-AB current mode output of the voltage regulator <NUM> sources current via the coupling capacitor <NUM> to the power rail <NUM> (e.g., to the load device <NUM>) when the voltage on the power rail <NUM> is below the second target voltage level and sinks current via the coupling capacitor <NUM> from the power rail <NUM> when the voltage on the power rail <NUM> is above the second target voltage level. The voltage regulator <NUM> is capacitively isolated by the coupling capacitor <NUM> from the first power supply <NUM>. The capacitive isolation provided by the coupling capacitor <NUM> may maintain stability of the hybrid parallel power supply by preventing contention between differing output levels of the voltage regulator <NUM> and the first power supply <NUM>. According to certain exemplary embodiments, the coupling capacitor <NUM> may be about <NUM> nF. Further, systems may operate reliably with coupling capacitors that have large (e.g., <NUM> pH) series inductance.

The first power supply <NUM> and the voltage regulator <NUM> operate to regulate the voltage level of the power rail <NUM>. This voltage regulation may be understood as the monitoring of the voltage level of the power rail <NUM> and when the voltage level differs from the respective target voltage level, changing operation of circuits driving the power rail <NUM> so that the voltage level moves toward the target voltage level. The voltage level of the power rail <NUM> may vary due to changes in current demand of the load device <NUM> and limitations in the response of the hybrid parallel power supply due, for example, to output impedances of the first power supply <NUM> and the voltage regulator <NUM> and response times of the first power supply <NUM> and the voltage regulator <NUM>.

The second target voltage level, to which the voltage regulator <NUM> regulates the power rail <NUM>, may be different from the first target voltage level, to which the first power supply <NUM> regulates the power rail <NUM>. The second target voltage level may be, for example, an offset voltage less than the first target voltage level. For example, in a hybrid parallel power supply where the first target voltage level is <NUM> V, the second target voltage level may be <NUM> V. In this arrangement, the first power supply <NUM> may supply most of the current dissipated by the load device <NUM> with the voltage regulator <NUM> rapidly supplying or sinking current in response to changes in the voltage on the power rail <NUM>.

The hybrid parallel power supply of <FIG> includes a second power supply ("SMPS2") <NUM> to supply power to the voltage regulator <NUM> via second supply terminal <NUM>. The second power supply <NUM> works to drive the first supply terminal <NUM> to a third target voltage level. The third target voltage level may be chosen, for example, to allow efficient operation of the voltage regulator <NUM>. The third target voltage level may also be a level used by other components in the system. The third target voltage level may be, for example, <NUM> V when the nominal level on the power rail <NUM> is <NUM> V. The second power supply <NUM> is able to supply power to the voltage regulator <NUM> with high efficiency. The second power supply <NUM> receives power from the first supply terminal <NUM>. The second power supply <NUM> may be a switching-mode power supply.

The voltage regulator <NUM> and the load device <NUM> may be fabricated on a first die ("DIE <NUM>") <NUM>. Since the voltage regulator <NUM> and the load device <NUM> are located together, parasitic impedances between the voltage regulator <NUM> and the load device <NUM> are small. Portions of the power rail <NUM> may also be fabricated on the first die <NUM>. The coupling capacitor <NUM> may be fabricated on the first die <NUM> or external to the first die <NUM> (e.g., on the circuit board <NUM> or an integrated-circuit package housing the first die <NUM>) or a combination of on-die and external capacitors. Board and package parasitic impedances do not substantially impair the connection between the voltage regulator <NUM>, the coupling capacitor <NUM>, and the load device <NUM>.

In the embodiment of <FIG>, the first die <NUM> includes an on-die capacitor <NUM> connected to the second supply terminal <NUM>, which supplies power to the voltage regulator <NUM>. The on-die capacitor <NUM> may be referred to as a bypass capacitor. The on-die capacitor <NUM> can supply current to the voltage regulator <NUM> with a high-frequency-response characteristic. The on-die capacitor <NUM> supports the voltage regulator <NUM> supplying current to the load device <NUM> with a high-frequency-response characteristic and aids in reducing a droop characteristic that would otherwise occur on the power rail <NUM> when the current demand of the load device <NUM> rapidly changes. The on-die capacitor <NUM> stores more charge than a capacitor on the power rail <NUM> due to the higher voltage of second supply terminal <NUM> compared to the power rail <NUM>. As a result, the parallel combination of the voltage regulator <NUM> and the first power supply <NUM> may operate without (or with little) further capacitance, such as a bulk capacitor, an external capacitor, a landside capacitor, or an embedded-passive-substrate (EPS) capacitor. According to certain exemplary embodiments, the on-die capacitor <NUM> may be about <NUM> nF.

The on-die capacitor <NUM> may alternatively be fabricated external to the first die <NUM>, for example, on a circuit board or integrated circuit package, or a combination of on-die and external capacitors. Provisioning of the on-die capacitor <NUM> and the coupling capacitor <NUM> on die, on package, or on circuit board may be determined according to the relative costs and performance of the respective implementations. These costs may include the costs of capacitors, interconnection, and package pins. Performance of the power distribution network generally improves with capacitance closer to the load device.

The first power supply <NUM> and the second power supply <NUM> may be fabricated on a second die ("DIE <NUM>") <NUM>. Combining the voltage regulator <NUM> and the load device <NUM> on the first die <NUM> and combining the first power supply <NUM> and the second power supply <NUM> on the second die may allow the various components to be manufactured using fabrication processes that are selected for the particular requirements of the components. For example, the voltage regulator <NUM> and the load device <NUM> may be manufactured using a high-density complementary metal-oxide-semiconductor (CMOS) process that allows many functions to be provided by the load device <NUM> and the first power supply <NUM> and the second power supply <NUM> may be manufactured using a high-power process that allows high efficiency power supplies. The first die <NUM> and the second die <NUM> may be mounted (directly or using integrated circuit packages) on an interconnection substrate, such as the circuit board <NUM>. In an embodiment, the second die <NUM> may be a power-management integrated circuit (PMIC).

A system using a hybrid parallel power supply may be more power efficient than systems using an SMPS, an LDO, or a series SMPS-LDO combination. The efficiency of the hybrid parallel power supply for an example implementation is about <NUM>%. The hybrid parallel power supply can also lower system power by allowing a smaller voltage guardband. This is particularly valuable in systems (such as a CMOS SoC) where the power is proportional to the voltage squared. An SoC with the voltage regulator <NUM> and the load device <NUM> may also have a reduced number of pins due, for example, to reduced use of decoupling capacitors on the power rail <NUM>.

The parallel combination of the LDO and SMPS combines the characteristics of the individual circuits to efficiently supply power while reducing voltage droop caused by rapid load current changes. The SMPS can be viewed as generally involved in supplying the steady-state current needs of the load device. In this way, the relatively large current demand of the load device is provided with the high efficiency of the SMPS. The LDO can be viewed as generally involved in supplying current to the load device in response in changes in the load current that could otherwise cause large voltage droops. That is, the LDO rapidly reacts to drops in the supply voltage and supplies current to the load device until the SMPS can react. The high bandwidth of the LDO enables the hybrid parallel power supply to provide sufficient current in a timely manner such that the droop characteristics are greatly reduced. Additionally, a parallel combination of the LDO and SMPS may allow use of a simplified SMPS, for example, an SMPS with fewer phases.

<FIG> is a functional block diagram of an electronic system with a capacitively-coupled hybrid parallel power supply according to a presently disclosed embodiment. The hybrid parallel power supply of <FIG> generally corresponds to the hybrid parallel power supply in the system of <FIG>. According, the description of the system of <FIG> may omit details common to the system of <FIG>. The system of <FIG> includes the first power supply <NUM> supplying power to the load device <NUM> and the voltage regulator <NUM> (receiving power from the second power supply <NUM>) supplying power to the load device <NUM> via the coupling capacitor <NUM>. The load device <NUM> (which may be an SoC including a processor and other circuits) is modeled with an equivalent load impedance 675a and a switched equivalent load impedance 675b.

The voltage regulator <NUM> includes an operational amplifier <NUM>, the coupling capacitor <NUM>, a reference converter ("DAC") <NUM>, and a bandgap source <NUM>. The reference converter <NUM> and the bandgap source <NUM> combine to produce a reference voltage that sets the second target voltage level at which the voltage regulator <NUM> supplies power to the power rail <NUM>. The bandgap source <NUM> produces a reference output voltage that is nearly constant (e.g., less than <NUM>% variation with process, supply voltage, and temperature). The bandgap source <NUM>, in an embodiment, produces the reference output voltage at a sub-bandgap level (e.g., <NUM> V). The reference converter <NUM> scales the reference output voltage from the bandgap source <NUM> to produce the reference voltage. For example, the reference converter <NUM> may scale a <NUM> V reference output voltage from the bandgap source <NUM> by <NUM>/<NUM> to produce a <NUM> V reference voltage. The reference converter <NUM> may be a digital-to-analog converter (DAC). The reference converter <NUM> may receive a digital input to configure the reference voltage. The digital input may be used to adjust the second target voltage level.

The second target voltage level used by the voltage regulator <NUM>, in an example helpful for understanding the invention, is set by a reference level produced by a reference level module. The reference level module may supply the reference voltage by scaling and low-pass filtering the power rail <NUM>. Setting the second target voltage level at a scaled level relative to the average level on power rail <NUM> may avoid concern with mismatches between the first and second target voltage levels. The voltage regulator <NUM> then supplies current to the load device <NUM> via the coupling capacitor <NUM> when the power rail <NUM> drops below the reference voltage. The reference level module may, for example, use a scale factor (of the second target voltage level relative to the level of the power rail <NUM>) of <NUM>/<NUM>. The amount of filtering may be chosen, for example, based on the bandwidth of the first power supply <NUM>. The reference level module may include a resistor divider to provide scaling coupled with a capacitor to provide filtering. The resistor divider may be variable so that the amount of scaling can be adjusted. The filtering may also be adjustable.

The operational amplifier <NUM> has an output coupled to a first terminal of the coupling capacitor <NUM>. A second terminal of the coupling capacitor <NUM> is coupled to the power rail <NUM>. The coupling capacitor <NUM> may be, for example, fabricated using transistor gate capacitance. Other capacitor structures may additionally or alternatively be used. Additionally, combinations of on die, on package, and on circuit board capacitors may be selected according to the relative costs and performance of the respective implementations. These costs may include the costs of the capacitors, interconnection, and package pins. Performance of the power distribution network generally improves with capacitance closer to the load device <NUM> and the operational amplifier <NUM>.

The operational amplifier <NUM> has its non-inverting input ("+") connected to the reference voltage from the reference converter <NUM> and its inverting input ("-") coupled to the power rail <NUM>. The inverting input of the operational amplifier <NUM> may be coupled directly to the power rail <NUM> or may be coupled to the power rail <NUM> via a feedback device <NUM>. In the example helpful for understanding the invention illustrated in <FIG>, a low-pass filter provides feedback from the power rail <NUM> to the operational amplifier <NUM>. The low-pass filter provides a low-pass filtered version of the voltage of the power rail <NUM> to the operational amplifier <NUM>. The low-pass filter may be implemented, as illustrated in <FIG>, with a resistor-capacitor network.

In the actual embodiment, the feedback device <NUM> utilizes a high-pass filter. In such an implementation, the voltage regulator <NUM> supplies current to the load device <NUM> in response to high-frequency changes in the voltage on the power rail <NUM> such as a droop due to rapid changes in the current demand of the load device <NUM>. In an example embodiment, the high-pass filter includes a capacitor coupled between the power rail <NUM> and the inverting input of the operational amplifier <NUM> and a resistor coupled between the inputs of the operational amplifier <NUM>. The second target voltage level may be set, for example, to a midpoint of the output range of the operational amplifier <NUM>. The frequency response of the high-pass filter may be chosen based, for example, on the response characteristics of the first power supply <NUM>.

The characteristics of the feedback device <NUM> may be arranged to tune the power regulation response of the voltage regulator <NUM> and provide a particular response to a droop event. The voltage on the power rail <NUM> may have time-varying voltage components that may be conceptualized as a signal riding on top of the first target voltage level. The feedback device <NUM> filters out high-frequency components appearing on the power rail <NUM> and pass remaining components to the inverting input of the operational amplifier <NUM>. The feedback device <NUM> can effectively change the bandwidth of the voltage regulator <NUM>.

The operational amplifier <NUM> may be a Class-AB operational amplifier, for example, a class-AB operational transconductance amplifier (OTA). Other types of operational amplifiers may also be used, for example, an amplifier with a voltage-mode output. An operational transconductance amplifier can have high bandwidth so that the voltage regulator <NUM> can provide current to the power rail <NUM> with a high-frequency-response characteristic. Additionally, a Class-AB OTA may be fabricated using standard logic transistors and without special devices or device fabrication techniques. The voltage regulator <NUM> may also have low quiescent current and thus contribute to overall power reduction for the system. The LDO may also be implemented within a small amount of die area.

The output of the operational amplifier <NUM> sources or sinks current based on the voltage difference between the inverting and non-inverting inputs. The feedback loop from the output of the operational amplifier <NUM> through the coupling capacitor <NUM> to the power rail <NUM> back to the inverting input of the operational amplifier <NUM> via the feedback device <NUM> allows the voltage regulator <NUM> to regulate the level of the power rail <NUM>.

The system of <FIG> includes the on-die capacitor <NUM> and a second capacitor <NUM> located in a package <NUM> housing the SoC and connected to the input of the voltage regulator <NUM>. The values of the second capacitor <NUM> and the on-die capacitor <NUM> may be selected based on, for example, cost, performance, and size. In an example embodiment, the capacitance of the second capacitor <NUM> may be about <NUM> times greater than the capacitance of the on-die capacitor <NUM>. For example, the capacitance of the second capacitor <NUM> may be <NUM> nF and the capacitance of the on-die capacitor <NUM> may be <NUM> nF. In some embodiments, a further capacitor may be located on the circuit board <NUM> and connected to the input of the voltage regulator <NUM>.

In some embodiments, a rail capacitor <NUM> located in the first die <NUM> is connected to the power rail <NUM>. The rail capacitor <NUM> may work in combination with the on-die capacitor <NUM> to provide current to the load device <NUM> during a droop event. Other combinations of capacitors on the circuit board <NUM>, the package <NUM>, the first die <NUM>, or other locations may also be used.

<FIG> also shows interconnection-parasitic elements 665a,b that represent the reactive elements encountered in making various electrical connections between the first power supply <NUM> and the power rail <NUM> and the second power supply <NUM> and the voltage regulator <NUM>. The interconnection-parasitic elements 665a,b are shown in the domain of the circuit board <NUM> between the first die <NUM> and the second die <NUM>. The interconnection-parasitic elements 665a,b may be combinations of resistors, capacitors, and inductors that represent an equivalent impedance encountered by electrical connections spanning between the first die <NUM> and the second die <NUM>.

<FIG> is a functional block diagram of an electronic system with a capacitively-coupled hybrid parallel power supply according to a presently disclosed embodiment. The hybrid parallel power supply of <FIG> is similar to the hybrid parallel power supply in the system of <FIG>. Accordingly, the description of the system of <FIG> omits details common to the system of <FIG>.

The capacitively-coupled hybrid parallel power supply of <FIG> includes a PMIC control module <NUM> to supply a control signal to the first power supply <NUM>. The PMIC control module <NUM> may also supply a control signal to the second power supply <NUM>. The PMIC control module <NUM> may be implemented in various ways. When the first power supply <NUM> is arranged to receive a digital control signal, the PMIC control module <NUM> supplies the control signal in digital form. For example, the PMIC control module <NUM> may signal the first target voltage level to the first power supply <NUM> using, for example, a serial protocol. The PMIC control module <NUM> may signal the first target voltage level open loop. Alternatively, the PMIC control module <NUM> may signal the first target voltage level closed loop by, for example, comparing the relative levels of the power rail <NUM> and the reference output voltage from the bandgap source <NUM>.

Alternatively, when the first power supply <NUM> is arranged to receive an analog control signal, the PMIC control module <NUM> supplies the control signal in analog form. The PMIC control module <NUM> may signal the first target voltage level to the first power supply <NUM> open loop by supplying the control signal at the first target voltage level or a scaled version of the first target voltage level. Alternatively, the PMIC control module <NUM> may signal the first target voltage level closed loop by, for example, comparing the relative levels of the power rail <NUM> and reference output voltage from the bandgap source <NUM>. The first power supply <NUM> can utilize the closed-loop control signal to produce a corresponding change in the voltage generated by the first power supply <NUM> on the power rail <NUM>.

The PMIC control module <NUM>, in an example closed-loop analog embodiment, includes a second operational amplifier having an output that provides the control signal to the first power supply <NUM>. The non-inverting input of the second operational amplifier connects to a supply reference voltage. The inverting input of the second operational amplifier connects to the power rail <NUM>. The supply reference voltage sets the first target voltage level at which the first power supply <NUM> supplies power to the power rail <NUM>. The supply reference voltage is produced by a second reference converter that scales the reference output voltage from the bandgap source <NUM> to produce the supply reference voltage. For example, the second reference converter may scale a <NUM> V reference output voltage from the bandgap source <NUM> by <NUM>/<NUM> to produce a <NUM> V supply reference voltage. The second reference converter may be a direct current (DC) converter, also known as a DC-to-DC converter. The second reference converter may receive a digital input to adjust the level of the supply reference voltage.

<FIG> is a time-domain graph of a droop characteristic in a system using a hybrid parallel power supply according to a presently disclosed embodiment. The graph illustrates operation of the hybrid parallel power supplies of <FIG>. Similar to the graph of <FIG>, the graph of <FIG> illustrates an example of a rapid change in current at time <NUM>. The graph of <FIG> plots load current <NUM> for the load device <NUM> and supply voltage <NUM> for the power rail <NUM>. Prior to time <NUM>, the load current <NUM> is <NUM> A. At time <NUM>, the load current <NUM> rapidly increases to <NUM> A.

In addition to the step in current demand of the load device at time <NUM>, small variations in the load current <NUM> occur, for example, as different calculations are performed in a processor in the load device <NUM>. These small variations in the load current <NUM> cause ripples (small variations, e.g., <NUM> mV) in the supply voltage <NUM>. The ripples in the supply voltage may be at frequencies that are higher than the bandwidth of the first power supply <NUM>. The first power supply <NUM> will then supply current to the power rail <NUM> based on a low-pass filtered average of the supply voltage. The ripples in the supply voltage may, however, be at frequencies that are within the bandwidth of the voltage regulator <NUM>. The voltage regulator <NUM> will then supply current the power rail <NUM> that reduces the magnitude of the ripples.

Prior to time <NUM>, the supply voltage <NUM> is at a nominal voltage level, for example, <NUM> V. At time <NUM>, the rapid increase in load current causes a droop characteristic <NUM> in the supply voltage <NUM>. The high frequency response of the voltage regulator <NUM> allows it to quickly increase current supplied to the load device <NUM> to reduce the magnitude of the droop characteristic <NUM>. The current provided to the load through the coupling capacitor <NUM> by the voltage regulator <NUM> conforms with the voltage-current relationship: <MAT>. Since the voltage change across the coupling capacitor can be much larger than the magnitude of the voltage droop (due to the change in the output of the voltage regulator <NUM>), the coupling capacitor <NUM> can supply a much larger current to the load than a similarly sized bypass capacitor (e.g., coupled between the power rail <NUM> and the ground reference).

An example system has a resultant droop characteristic of less than <NUM>% for a <NUM> A/<NUM> ns step change in load current. The apparatus and systems described above relate to a droop characteristic defined in terms of a spike-like lowering of the supply voltage at a load device on a die. A similar effect, but with a positive-going spike, may be realized in certain circuit situations where the current demand of a load device rapidly decreases. The capacitively-coupled hybrid parallel power supplies disclosed herein may reduce positive-going spikes in the power supply level by the voltage regulator <NUM> sinking current from the power rail <NUM> via the coupling capacitor <NUM>.

<FIG> is a flowchart of a process for supplying power to an electronic device according to a presently disclose embodiment. The process will be described with reference to the system of <FIG>; however, various embodiments of the process may be applied to any suitable apparatus.

In block <NUM>, the process supplies current from a power supply to a load device via a power rail at a first target voltage level. In block <NUM>, an efficient power supply, such as a switching mode power supply, is used. For example, the first power supply <NUM> can regulate the power rail <NUM> to a first target voltage level to supply current to the load device <NUM>.

In block <NUM>, the process supplies current from a voltage regulator to the load device via a coupling capacitor at a second target voltage level. The supplied current may be negative, for example, when the level of the power rail <NUM> is higher than a desired regulation level. In block <NUM>, a voltage regulator, such as a low dropout voltage regulator, with a high-frequency-response characteristic is used. For example, the voltage regulator <NUM> can regulate the power rail <NUM> to a second supply voltage level to supply current to the load device <NUM>. The first target voltage level and the second target voltage level may be the same or different and may be configurable. The process may generate the first target voltage level and the second target voltage level by generating a reference output voltage based on a bandgap source and then generating the second target voltage level based on a first digital input and the reference output voltage and generating the first target voltage level based on a second digital input and the reference output voltage.

The process of <FIG> may be modified, for example, by adding or altering blocks. Additionally, blocks may be performed concurrently.

Although features of the invention are described above for particular embodiments, many variations are possible. For example, capacitively-coupled hybrid parallel power supplies may be formed using other fabrication processes including processes different types of transistors. Additionally, hybrid parallel power supplies may use different types of voltage regulators and different types of power supplies. Further, hybrid parallel power supplies may have different numbers of power supplies and voltage regulators. In another variation, the voltage regulator <NUM> can be shut off and removed from providing voltage regulation. In yet another variation, a low-power retention voltage regulator is included on the SoC for use during standby modes. Additionally, features of the various embodiments may be combined in combinations that differ from those described above.

Those of skill in the art will appreciate that the various illustrative blocks and modules described in connection with the embodiments disclosed herein can be implemented in various forms. Some blocks and modules have been described above generally in terms of their functionality. How such functionality is implemented depends upon the design constraints imposed on an overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the invention. In addition, the grouping of functions within a module, block, or step is for ease of description. Specific functions or steps can be moved from one module or block or distributed across to modules or blocks without departing from the invention.

Claim 1:
A hybrid parallel power supply, comprising:
a first power supply (<NUM>) connected to a power rail (<NUM>) and configured to supply current to a load device (<NUM>) via the power rail (<NUM>), the first power supply (<NUM>) being further configured to regulate the power rail (<NUM>) to a first target voltage level;
a coupling capacitor (<NUM>) having a first terminal coupled to the power rail (<NUM>); and
a voltage regulator (<NUM>) comprising an operational amplifier (<NUM>) having a first input coupled to the power rail (<NUM>) by a high-pass filter, a second input arranged to receive a reference voltage at a second target voltage level, and an output coupled to a second terminal of the coupling capacitor (<NUM>).