Patent Description:
The semiconductor integrated circuit industry has experienced rapid growth. The development of integrated-circuit design and advancements in materials technology has produced generations of integrated circuits. Each generation has smaller and more complex circuits than the previous generation. In the process of integrated-circuit development, geometric size has gradually been reduced.

The gate-all around (GAA) nanosheet (NS) device has been introduced in an effort to improve gate control by increasing gate and channel coupling, reduce OFF-state leakage current, and reduce short-channel effects (SCE). A gate-all around nanosheet device has a gate stack wrapped around the channel region providing access to the channel on four sides. The gate-all around nanosheet device provides a channel in a silicon nanosheet.

As integrated circuits have shrunk, the size of the transistor and metal lines has decreased. Therefore, the power rail resistance may increase, and the IR drop may lead to poor circuit performance and worse electron migration (EM). Moreover, a conventional Hi-R resistor incurs an extra cost for the mask and takes up more chip area.

Although existing nanosheet field effect transistor device structures have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects, and need to be improved. This is especially true of the control of the power rail resistance and a resistor with lower cost.

<CIT> discloses gate-all-around devices with power lines in boundary regions. <CIT> discloses multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods, in particular, a floating body DRAM transistor and device.

<CIT> discloses multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods, in particular, vertically oriented 3D memories.

<CIT> discloses methods of fabrication for and applications of a device referred to as Stacked Independently Contacted Field effect Transistors (SICFETs).

<CIT> discloses a method for forming source/drain contact (CA) power rails using a three mask decomposition process.

According to a first aspect of the invention there is provided a semiconductor device structure according to claim <NUM>.

According to a second aspect of the invention there is provided a method for forming a semiconductor device structure according to claim <NUM>.

Optional features are specified in the dependent claims.

It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to other elements or features as illustrated in the figures.

Herein, the terms "around," "about," "substantial" usually mean within <NUM>% of a given value or range, preferably within <NUM>%, and better within <NUM>%, or <NUM>%, or <NUM>%, or <NUM>%, or <NUM>%. It should be noted that the quantity herein is a substantial quantity, which means that the meaning of "around," "about," "substantial" are still implied even without specific mention
of the terms "around," "about," "substantial.

Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. In different embodiments, additional operations can be provided before, during, and/or after the stages described the present disclosure. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor structure in the present disclosure. Some of the features described below can be replaced or eliminated for different embodiments.

The embodiments of the present disclosure provide a nanosheet field effect transistor device structure. By forming an epitaxial structure under the power rail and electrically connected to the power rail, the power rail resistance may be reduced and the circuit performance may be enhanced and the electron migration (EM) may be mitigated. Moreover, by forming contact structures on opposite sides of the epitaxial structures, a resistor producing in the front-end process is provided. The chip area and the cost for the mask may be further reduced.

<FIG> is a top view of a nanosheet field effect transistor device structure <NUM> in accordance with some embodiments. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> are cross-sectional representations of various stages of forming a nanosheet field effect transistor device structure <NUM> shown in <FIG> in accordance with some embodiments. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> show cross-sectional representations taken along line <NUM>-<NUM>' in <FIG>. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> show cross-sectional representations taken along line <NUM>-<NUM>' in <FIG>. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>show cross-sectional representations taken along line <NUM>-<NUM>' in <FIG>.

As shown in <FIG> in accordance with some embodiments, the nanosheet field effect transistor device structure <NUM> includes a device region 10D and a boundary region 10B. The device region 10D includes gate structures <NUM> extending in the Y direction and a nanosheet stack <NUM> extending in the X direction. The nanosheet stack <NUM> in the device region 10D includes a channel region <NUM> under the gate structures <NUM> and a source/drain region <NUM> between the gate structures <NUM>. The boundary region 10B includes a power rail <NUM> and another nanosheet stack <NUM> (not shown) extending in the X direction. The nanosheet stack <NUM> in the boundary region 10B is formed directly beneath the power rail <NUM> and electrically connected to the power rail <NUM>. According to the invention, the source/drain region <NUM> is electrically connected to the power rail <NUM>, as shown in <FIG>. By forming a nanosheet stack <NUM> in the boundary region 10B directly beneath the power rail <NUM> and electrically connected to the power rail <NUM>, the power rail resistance may be decreased.

The following description describes the forming method of the nanosheet field effect transistor device structure <NUM> in <FIG>. A substrate <NUM> is provided as shown in <FIG>, <FIG>, and <FIG> in accordance with some embodiments. The substrate <NUM> may be a semiconductor wafer such as a silicon wafer. The substrate <NUM> may also include other elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium nitride, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GalnP, and/or GalnAsP. In some embodiments, the substrate <NUM> includes an epitaxial layer. For example, the substrate <NUM> has an epitaxial layer overlying a bulk semiconductor. In addition, the substrate <NUM> may also be semiconductor on insulator (SOI). The SOI substrate may be fabricated by a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, other applicable methods, or a combination thereof. In some embodiments, the substrate <NUM> may be an N-type substrate. In some embodiments, <NUM> the substrate <NUM> may be a P-type substrate.

Next, a nanosheet stack <NUM> is formed on the substrate <NUM>, as shown in <FIG>, <FIG>, <FIG>, and <FIG>. The nanosheet stack <NUM> includes first semiconductor layers <NUM> and second semiconductor layers <NUM> vertically alternately stacked over the substrate <NUM>. It should be noted that, although there are four layers of the first semiconductor layers <NUM> and three layers of the second semiconductor layers <NUM> in the embodiments shown in <FIG>, <FIG>, and <FIG>, the number of first semiconductor layers <NUM> and the second semiconductor layers <NUM> is not limited thereto.

The first semiconductor layers <NUM> may be made of silicon, silicon germanium, germanium tin, silicon germanium tin, gallium arsenide, indium gallium arsenide, indium arsenide, another suitable material, or a combination thereof. The semiconductor material layers <NUM> may be made of silicon, silicon germanium, germanium tin, silicon germanium tin, gallium arsenide, indium gallium arsenide, indium arsenide, another suitable material, or a combination thereof. In some embodiments, the first semiconductor layers <NUM> and the second semiconductor material layers <NUM> are made of different materials. For example, the first
semiconductor layers <NUM> are made of silicon germanium, and the second semiconductor material layers <NUM> are made of silicon.

The first semiconductor material layers <NUM> and the second semiconductor material layers <NUM> may be formed by an epitaxial growth process. Each of the first semiconductor material layers <NUM> and the second semiconductor material layers <NUM> may be formed by a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure CVD (LPCVD) process, and/or an ultrahigh vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, another applicable process, or a combination thereof.

Afterwards, a photoresist layer may be formed over the nanosheet stack <NUM> (not shown). The photoresist layer may be patterned by a patterning process including a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

Next, after the photoresist layer is patterned, the nanosheet stack <NUM> and the upper portion of the substrate <NUM> are patterned by using the patterned photoresist layer as a mask as shown in <FIG> and <FIG> in accordance with some embodiments. As a result, a patterned nanosheet stack <NUM> and a patterned substrate <NUM> may be obtained. Afterwards, the patterned photoresist layer may be removed.

Next, an isolation layer <NUM> is formed to cover the nanosheet stack <NUM> and the substrate <NUM>, as shown in <FIG> and <FIG> in accordance with some embodiments. The isolation layer <NUM> may be made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or another low-k dielectric material. The isolation layer <NUM> may be deposited by a deposition process, such as a chemical vapor deposition (CVD) process, a spin-on-glass process, or another applicable process.

As shown in <FIG> and <FIG> in accordance with some embodiments, after the nanosheet stack <NUM> is patterned, separate nanosheet stacks <NUM> are formed in the source/drain region <NUM> in the device region 10D and the boundary region 10B respectively. The nanosheet stack <NUM> may be separated by the isolation layer <NUM>.

Afterwards, in some embodiments, the isolation layer <NUM> is planarized to expose the top surface of the nanosheet stack <NUM> (not shown). In some embodiments, the isolation layer <NUM> may be planarized by a chemical mechanical polishing (CMP) process.

Next, an etching process is performed on the isolation layer <NUM>, as shown in <FIG> and <FIG> in accordance with some embodiments. In some embodiments, the isolation layer <NUM> is completely removed. Therefore, the nanosheet stack <NUM> and the substrate <NUM> are exposed, as shown in <FIG>. In some embodiments, a portion of the isolation layer <NUM> is removed. As a result, the nanosheet stack <NUM> may be exposed and the remaining isolation layer <NUM> may surround the top portion of the substrate <NUM>. The remaining isolation layer <NUM> may be an isolation structure such as a shallow trench isolation (STI) structure surrounding the top portion of the substrate <NUM>. The isolation structure may be configured to prevent electrical interference or crosstalk.

Afterwards, a dummy gate layer <NUM> is formed over the top surface and the sidewalls of the nanosheet stack <NUM> as shown in <FIG>and <FIG> in accordance with some embodiments. The dummy gate layer <NUM> defines a channel region <NUM> and a source/drain region <NUM>. As shown in <FIG> in accordance with some embodiments, the channel region <NUM> is directly under the dummy gate layer <NUM>, and the source/drain region <NUM> is on the opposite side of the channel region <NUM> and is not covered by the dummy gate layer <NUM>.

The dummy gate layer <NUM> may include a dummy dielectric layer and a dummy gate electrode layer (not shown). The dummy dielectric layer may be first conformally formed over the nanosheet stack <NUM>. The dummy dielectric layer may be made of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, dielectric material(s) with high dielectric constant (high-k), or a combination thereof. The dummy dielectric layer may be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), or plasma enhanced CVD (PECVD).

After forming the dummy dielectric layer, the dummy gate electrode layer may be conformally formed over the dummy dielectric layer. The dummy gate electrode layer may be made of polysilicon. The dummy gate electrode layer may be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), or plasma enhanced CVD (PECVD).

Afterwards, as shown in <FIG>, <FIG> and <FIG> in accordance with some embodiments, an etching process is performed on the dummy gate layer <NUM> to form a dummy gate structure <NUM> by using a patterned hard mask layer <NUM>. The dummy gate layer <NUM> may be partially removed in the etching process. The etching process may be a dry etching process or a wet etching process. In some embodiments, the dummy dielectric layer and the dummy gate electrode layer are etched by a dry etching process. The dry etching process may include using a fluorine-based etchant gas, such as SF<NUM>, CxFy (where x and y may be positive integers), NF<NUM>, or a combination thereof. After the etching process, the nanosheet stack <NUM> is exposed in the source/drain region <NUM> and the boundary region 10B, as shown in <FIG>and <FIG>.

Next, the first semiconductor layers <NUM> in the source/drain region <NUM> are removed, and a pair of spacers <NUM> are formed on sidewalls of the dummy gate layer <NUM>, as shown in <FIG> and <FIG> in accordance with some embodiments. The first semiconductor layers <NUM> in the source/drain region <NUM> may be removed by a dry etching process, such as an anisotropic etching process. The spacers <NUM> may be made of silicon oxide, silicon nitride, silicon oxynitride, and/or dielectric materials. The spacers <NUM> may be formed by a chemical vapor deposition (CVD) process, a spin-on-glass process, or other applicable processes. In some embodiments, the spacers <NUM> also fill in the gap between the first semiconductor layers <NUM> in the source/drain region <NUM> (not shown).

Next, epitaxial structures <NUM> are formed in the source/drain region <NUM> and the boundary region 10B, as shown in <FIG> and <FIG> in accordance with some embodiments. In some embodiments, the second semiconductor layers <NUM> in the source/drain region <NUM> are removed, and a strained material is grown by an epitaxial (epi) process to form the epitaxial structures <NUM> in the source/drain region <NUM> and the boundary region 10B. In addition, the lattice constant of the strained material may be different from the lattice constant of the substrate <NUM>. In some embodiments, the second semiconductor layers <NUM> in the source/drain region <NUM> are not removed, and the strained material is grown cladding around the second semiconductor layers <NUM> in the source/drain region <NUM> and the boundary region 10B. The type of the strained material in the present disclosure is not limited, depending on the needs of mobility or resistance improvement. In some embodiments as shown in <FIG>and <FIG>, the epitaxial structures <NUM> include vertically arranged epitaxial layers.

The epitaxial structures <NUM> may include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, SiC, SiP, other applicable materials, or a combination thereof. The epitaxial structures <NUM> may be formed by an epitaxial growth step, such as metalorganic chemical vapor deposition (MOCVD), metalorganic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma-enhanced chemical vapor deposition (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), or any other suitable method.

According to the invention, after the epitaxial structure <NUM> is formed, an inter-layer dielectric (ILD) structure <NUM> is formed to cover the epitaxial structure <NUM> as shown in <FIG>and <FIG>. The inter-layer dielectric structure <NUM> may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The inter-layer dielectric structure <NUM> may be formed by chemical vapor deposition (CVD), spin-on coating, or other applicable processes.

Afterwards, a planarizing process is performed on the inter-layer dielectric structure <NUM> until the top surface of the dummy gate layer <NUM> is exposed in accordance with some embodiments (not shown). After the planarizing process, the top surface of the dummy gate layer <NUM> may be substantially level with the top surfaces of the spacers <NUM> and the inter-layer dielectric structure <NUM>. The planarizing process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, another applicable process, or a combination thereof.

Next, the dummy gate layer <NUM> in the channel region <NUM> is removed, as shown in <FIG> and <FIG> in accordance with some embodiments. Therefore, the first semiconductor layer <NUM> and the second semiconductor layer <NUM> in the channel region <NUM> may be exposed. The dummy gate layer <NUM> may be removed by an etching process, such as a dry etching process or a wet etching process.

After removing the dummy gate layer <NUM> in the channel region <NUM>, the first semiconductor <NUM> in the channel region <NUM> is removed, as shown in <FIG> and <FIG> in accordance with some embodiments. The second semiconductor layers <NUM> are left in the channel region <NUM>. The first semiconductor <NUM> in the channel region <NUM> may be removed by an etching process, such as an anisotropic etching process.

Next, a gate stack <NUM> is formed surrounding the second semiconductor layers <NUM> in the channel region <NUM>, as shown in <FIG> and <FIG>in accordance with some embodiments. In some embodiments, the gate stack <NUM> fills in the space between the second semiconductor layers <NUM> in the channel region <NUM>. The gate stack <NUM> may include a gate dielectric layer, a work function layer, and a gate electrode layer (not shown). After forming the gate stack <NUM>, the gate structure <NUM> in the channel region <NUM> includes vertically arranged second semiconductor layers <NUM> surrounded by the gate stack <NUM> as shown in <FIG> and <FIG> in accordance with some embodiments.

The gate dielectric layer may include a high-k dielectric layer (e.g., the dielectric constant is greater than <NUM>) such as hafnium oxide (HfO<NUM>). The high-k dielectric layer may include other high-k dielectrics such as LaO, AlO, ZrO, TiO, Ta<NUM>O<NUM>, Y<NUM>O<NUM>, SrTiO<NUM>, BaTiO<NUM>, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, BaTiO<NUM>, SrTiO<NUM>, Al<NUM>O<NUM>, other applicable high-k dielectric materials, or a combination thereof. The gate dielectric layer may be formed by a chemical vapor deposition process (CVD) (e.g., a plasma enhanced chemical vapor deposition (PECVD) process, a metalorganic chemical vapor deposition (MOCVD) process, or a high density plasma chemical vapor deposition (HDPCVD)), an atomic layer deposition (ALD) process (e.g., a plasma enhanced atomic layer deposition (PEALD) process), a physical vapor deposition (PVD) process (e.g., a vacuum evaporation process, or a sputtering process), other applicable processes, or a combination thereof.

The work function metal layer may be formed surrounding the gate dielectric layer. The work function metal layer may provide the desired work function for transistors to enhance device performance including improved threshold voltage. The work function metal layer may be made of metal materials, and the metal materials may include N-work-function metal or P-work-function metal. For N-type transistors, N-work-function metal may include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination thereof. For P-type transistors, the P-work-function metal may include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru) or a combination thereof.

The gate electrode layer is formed surrounding the work function metal layer. The gate electrode layer may be made of a conductive material, such as aluminum, copper, tungsten, titanium, tantulum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other applicable materials. The gate electrode layer may be formed by a chemical vapor deposition process (e.g., a low pressure chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process), a physical vapor deposition process (e.g., a vacuum evaporation process, or a sputtering process), other applicable processes, or a combination thereof.

Next, a first contact structure <NUM> is formed surrounding the epitaxial structure <NUM> in the source/drain region <NUM> and in the boundary region 10B, as shown in <FIG>and <FIG>in accordance with some embodiments. In some embodiments, the first contact structure <NUM> fills in the space between the vertically arranged epitaxial layers of the epitaxial structure <NUM>. Therefore, the resistance of may be further reduced.

In some embodiments, openings are formed in the interlayer dielectric structure <NUM> (not shown), and a conductive material is filled in the openings to form the first contact structure <NUM>. The first contact structure <NUM> may be made of metal materials (e.g., W, Al, or Cu), metal alloys, poly-Si, other applicable conductive materials, or a combination thereof. The first contact structure <NUM> may be formed by using a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD, e.g., evaporation or sputter), an atomic layer deposition process (ALD), an electroplating process, another suitable process, or a combination thereof to deposit the conductive materials of the first contact structure <NUM> in the openings. A chemical mechanical polishing (CMP) process or an etching back process may be then optionally performed to remove excess conductive materials to form the first contact structure <NUM>.

Next, according to the invention, a dielectric layer <NUM> is formed over the ILD structure <NUM> and a metal layer <NUM> is formed in the dielectric layer <NUM>, as shown in <FIG>and <FIG>. The metal layer <NUM> is in direct contact with and electrically connected to the first contact structure <NUM> formed in the source/drain region <NUM> and in the boundary region 10B. The dielectric layer <NUM> may be made of silicon oxide. The dielectric layer <NUM> may be deposited by CVD processes such as atmospheric pressure CVD (APCVD), low-pressure CVD (LPCVD), and plasma-enhanced CVD (PECVD).

The metal layer <NUM> may include Cu, W, Ag, Ag, Sn, Ni, Co, Cr, Ti, Pb, Au, Bi, Sb, Zn, Zr, Mg, In, Te, Ga, other applicable metallic materials, an alloy thereof, or a combination thereof. In some embodiments, the metal layer <NUM> includes a stacked structure of TiN/AlCu/TiN. The metal layer <NUM> may be deposited by a physical vapor deposition process (e.g., evaporation or sputtering), an atomic layer deposition process (ALD), an electroplating process, other applicable processes or a combination thereof, and then a chemical mechanical polishing (CMP) process or an etching back process is then optionally performed to remove excess conductive materials.

Next, a dielectric layer <NUM> is formed over the dielectric layer <NUM>, and a via <NUM> and a power rail <NUM> are formed in the dielectric layer <NUM> in the boundary region 10B, as shown in <FIG>. According to the invention, the power rail <NUM> is formed directly above the epitaxial structure <NUM> in the boundary region 10B and electrically connected to the epitaxial structure <NUM> in the boundary region 10B. By electrically connecting the epitaxial structure <NUM> in the boundary region 10B to the power rail <NUM> in parallel, the power rail resistance may be effectively reduced, and the IR drop may be suppressed, and electron migration may be improved.

The processes for forming the via <NUM> may be the same as, or similar to, those used to form the first contact structure <NUM>. The processes for forming the power rail <NUM> may be the same as, or similar to, those used to form the metal layer <NUM>. For the purpose of brevity, the descriptions of these processes are not repeated herein. In some embodiments, the via <NUM> and the power rail <NUM> are formed separately. In some embodiments, the via <NUM> and the power rail <NUM> are formed at the same time by a dual damascene process.

Next, a second contact structure <NUM> is formed on the gate stack <NUM>, as shown in <FIG> in accordance with some embodiments. In some embodiments, the second contact structure <NUM> is electrically connected to the gate stack <NUM>. The processes for forming the second contact structure <NUM> are the same as, or similar to, those used to form the first contact structure <NUM>. For the purpose of brevity, the descriptions of these processes are not repeated herein.

In some embodiments as shown in <FIG>, the space S between the epitaxial structure <NUM> in the source/drain region <NUM> and the epitaxial structure <NUM> in the boundary region 10B is in a range from about <NUM>% to about <NUM>% of the width W1 of the epitaxial structure <NUM> in the source/drain region <NUM>. In some other preferred embodiments as shown in <FIG>, the space S between the epitaxial structure <NUM> in the source/drain region <NUM> and the epitaxial structure <NUM> in the boundary region 10B is in a range from about <NUM>% to about <NUM>% of the width W1 of the epitaxial structure <NUM> in the source/drain region <NUM>. If the space S is too large, the circuit area may be too large. If the space S is too small, the epitaxial structure <NUM> in the source/drain region <NUM> and the epitaxial structure <NUM> in the boundary region 10B may short-circuit and there may be more defects.

In some embodiments as shown in <FIG>, the width W2 of the epitaxial structure <NUM> in the boundary region 10B is in a range from about <NUM>% to about <NUM>% of the width WP of the power rail <NUM>. In some other preferred embodiments as shown in <FIG>, the width W2 of the epitaxial structure <NUM> in the boundary region 10B is in a range from about <NUM>% to about <NUM>% of the width WP of the power rail <NUM>. If the width W2 is too wide, the epitaxial structure <NUM> in the source/drain region <NUM> and the epitaxial structure <NUM> in the boundary region 10B may short-circuit. If the width W2 is to narrow, the power rail resistance may still be high.

By forming an extra epitaxial structure <NUM> under the power rail <NUM> in the boundary region 10B and electrically connecting the extra epitaxial structure <NUM> and the power rail <NUM>, the power rail resistance may be effectively reduced, the IR drop may be suppressed, and the electron migration may be improved. Moreover, with the first contact structure <NUM> filled in the space between the vertically arranged epitaxial layers <NUM>, the power rail resistance may be further reduced.

Many variations and/or modifications may be made to the embodiments of the disclosure. <FIG> are cross-sectional representations of various stages of forming a nanosheet field effect transistor device structure <NUM> useful for understanding the invention. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown in <FIG> the epitaxial structures <NUM> in the source/drain region <NUM> and the boundary region 10B are single epitaxial blocks.

After the spacers <NUM> are formed, the first semiconductor layers <NUM> and the second semiconductor layers <NUM> in the source/drain region <NUM> and the boundary region 10B are both removed by an etching process, as shown in <FIG>. The etching process may include dry etching process, wet etching process, reactive ion etching, and/or other suitable etching process. The dry etching process may be performed by an oxygen-containing gas, a fluorine-containing gas (such as CF<NUM>, SF<NUM>, CH<NUM>F<NUM>, CHF<NUM>, and/or C<NUM>F<NUM>), a chlorine-containing gas (such as Cl<NUM>, CHCl<NUM>, CCl<NUM>, and/or BCl<NUM>), bromine-containing gas (such as HBr and/or CHBR<NUM>), iodine- containing gas, other suitable gas and/or plasma, or a combination thereof. The wet etching process may be performed in wet etching etchant including diluted hydrofluoric acid (DHF), potassium hydroxide (KOH), ammonia, hydrofluoric acid (HF), nitric acid (HNO<NUM>), and/or acetic acid (CH<NUM>COOH), other suitable wet etching etchant, or a combination thereof.

Next, an epitaxial structure <NUM> which is a single epitaxial block is formed in the source/drain region <NUM> and the boundary region 10B, as shown in <FIG>. The processes of forming the epitaxial structure <NUM> are the same as, or similar to, those used to form the epitaxial structure <NUM> described in the previous embodiments. For the purpose of brevity, the descriptions of these processes are not repeated herein. Compared to the embodiment with vertically arranged epitaxial layers, it is easier to form a single epitaxial block of the epitaxial structure <NUM>, and may improve production yield and transistor current by mobility enhancement.

Next, the first contact structure <NUM> is formed surrounding the epitaxial structure <NUM> in the source/drain region <NUM> and the boundary region 10B, as shown in <FIG> The epitaxial structure <NUM> may be spaced apart from the substrate as shown in <FIG>, and first contact structure <NUM> may wrap around the epitaxial structure <NUM> to further reduce the resistance. This may improve production yield and transistor current by mobility enhancement.

Afterwards, the power rail <NUM> is formed directly above the epitaxial structure <NUM> formed in the boundary region 10B, and the power rail <NUM> is electrically connected to the epitaxial structure <NUM> formed in the boundary region 10B, as shown in <FIG>.

By forming an extra epitaxial structure <NUM> under the power rail <NUM> in the boundary region 10B and electrically connecting the extra epitaxial structure <NUM> and the power rail <NUM>, the power rail resistance may be effectively reduced, the IR drop may be suppressed, and the electron migration may be improved. Moreover, since the epitaxial structure <NUM> is a single epitaxial block, it may be easier to wrap around the first contact structure <NUM>, and the production yield may be further improved and transistor current by mobility enhancement.

Many variations and/or modifications may be made to the embodiments of the disclosure. <FIG> are cross-sectional representations of various stages of a modified nanosheet field effect transistor device structure <NUM>, in accordance with some other embodiments of the disclosure. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown in <FIG> in accordance with some embodiments, the epitaxial structure <NUM> in the source/drain region <NUM> and the epitaxial structure <NUM> in the boundary region 10B include a different number of epitaxial layers.

After etching back the isolation layer <NUM>, the number of first semiconductor layers <NUM> and the second semiconductor layers <NUM> in the source/drain region <NUM> and in the boundary region 10B exposed from the isolation layer <NUM> are different, as shown in <FIG> in accordance with some embodiments. In some embodiments, the number of first semiconductor layers <NUM> and the second semiconductor layers <NUM> in the boundary region 10B is more than that of in the source/drain region <NUM>. Therefore, after removing the first semiconductor layers <NUM> exposed from the isolation layer <NUM>, the number of left second semiconductor layers <NUM> in the source/drain region <NUM> and in the boundary region 10B exposed from the isolation layer <NUM> are different, as shown in <FIG> in accordance with some embodiments.

Next, the epitaxial structure <NUM> is formed at where the second semiconductor layers <NUM> are exposed from the isolation layer <NUM>, as shown in <FIG> in accordance with some embodiments. The number of the epitaxial layers of the epitaxial structure <NUM> in the source/drain region <NUM> and in the boundary region 10B may be different. Moreover, as shown in <FIG> and <FIG>, the contact structure <NUM> wrapping around the epitaxial structure <NUM> in the boundary region 10B is larger than that of in the source/drain region <NUM>. Therefore, the resistance of the contact structure <NUM> in the boundary region 10B is lower than that in the source/drain region <NUM>.

It should be noted that, although there are three epitaxial layers of the epitaxial structure <NUM> in the source/drain region <NUM> and five epitaxial layers of the epitaxial structure <NUM> in the boundary region 10B in the embodiments shown in <FIG>, the number of epitaxial layers of the epitaxial structure <NUM> in the source/drain region <NUM> and in the boundary region 10B is not limited thereto.

By forming an extra epitaxial structure <NUM> under the power rail <NUM> in the boundary region 10B and electrically connecting the extra epitaxial structure <NUM> and the power rail <NUM>, the power rail resistance may be effectively reduced, the IR drop may be suppressed, and the electron migration may be improved. Moreover, since the epitaxial structure <NUM> is larger under the power rail <NUM>, the power rail resistance may be further reduced.

<FIG> is a cross-sectional representation of a modified nanosheet field effect transistor device structure <NUM>, useful for understanding the invention. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown in <FIG> the epitaxial structure <NUM> in the source/drain region <NUM> includes a single epitaxial block, and the epitaxial structure <NUM> in the boundary region 10B includes vertically arranged epitaxial layers.

After the spacers <NUM> are formed, the first semiconductor layers <NUM> and the second semiconductor layers <NUM> in the source/drain region <NUM> are removed by an etching process, as shown in <FIG>. Meanwhile, only the first semiconductor layers <NUM> in the boundary region 10B are removed by the etching process. Therefore, a single epitaxial block may be formed in the source/drain region <NUM> and vertically arranged epitaxial layers may be formed in the boundary region 10B. Since in the boundary region 10B the epitaxial layers <NUM> are vertically arranged, the first contact structure <NUM> filled in the space between the vertically arranged epitaxial layers <NUM>. The contact structure <NUM> may have a lower resistance in the boundary region 10B than in the source/drain region <NUM>, and the power rail resistance may be further reduced.

By forming an extra epitaxial structure <NUM> under the power rail <NUM> in the boundary region 10B and electrically connecting the extra epitaxial structure <NUM> and the power rail <NUM>, the power rail resistance may be effectively reduced, the IR drop may be suppressed, and the electron migration may be improved. Since the epitaxial structure <NUM> in the source/drain region <NUM> is a single epitaxial block, it may be easier to wrap around the first contact structure <NUM>, and the production yield may be further improved and transistor current by mobility enhancement. Moreover, since the epitaxial structure <NUM> in the boundary region 10B is vertically arranged epitaxial layers, the power rail resistance may be further reduced.

<FIG> is a perspective representation of a modified nanosheet field effect transistor device structure <NUM>. <FIG> is a top view of a modified nanosheet field effect transistor device structure <NUM>. <FIG> is a cross-sectional representation of a modified nanosheet field effect transistor device structure <NUM>. <FIG> shows a cross-sectional representation taken along line <NUM>-<NUM>' in <FIG>. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown in <FIG>, between the gate structures <NUM>, a pair of contact structures <NUM> are disposed on opposite sides of the epitaxial structure <NUM>. Moreover, each of the contact structures <NUM> surrounds a portion of the epitaxial structure <NUM>, and the pair of contact structures <NUM> are spaced apart from each other by the epitaxial structure <NUM>.

The contact structures <NUM> are formed on opposite sides of the epitaxial structure <NUM>, as shown in <FIG>. Therefore, a resistor <NUM> is formed at the epitaxial structure <NUM> between the contact structures <NUM>. Compared to the conventional resistor design, the resistor <NUM> between the contact structures <NUM> may be formed without extra masks and the chip area may be reduced.

As shown in <FIG> and <FIG>, by forming another pair of contact structures 522P between the gate structures <NUM> and another gate structure 121P parallel to gate structures <NUM>, another resistor 536P is formed between the contact structures 522P. Moreover, as shown in <FIG>, the contact structures <NUM> are electrically connected to the contact structures 522P at each end. Therefore, the resistors <NUM> and 536P between the contact structures <NUM> and 522P are connected in parallel.

It should be noted that, although there are three gate structures <NUM> and 121P and two pair of contact structures <NUM> and 522P in the examples shown in <FIG> and <FIG>, the number of gate structures <NUM> and 121P and contact structures <NUM> and 522P is not limited thereto. The number of gate structures <NUM> and 121P and contact structures <NUM> and 522P may be modified, depending on the demands on the resistance of the resistor.

In some examples as shown in <FIG>, the ratio of width W to height H of the epitaxial structure <NUM> is in a range from about <NUM>% to about <NUM>%. If the ratio is too high, it may not be easy to form an epitaxial structure <NUM> between the gate structures <NUM>. If the ratio is too low, extra chip area may be needed to meet the resistance requirements. The width W of the epitaxial structure <NUM> may be modified, depending on the demands on the resistance of the resistor <NUM>.

The epitaxial structure <NUM> may include vertically arranged epitaxial layers as shown in <FIG>. Therefore, the resistance of the resistor <NUM> is the parallel resistance of each epitaxial layer is connected in parallel between the contact structures <NUM>. By forming epitaxial structure <NUM> between a pair of contact structures <NUM> and 522P, a resistor <NUM> is formed without using an extra mask. The resistance of the resistor <NUM> may be modified by changing the width W of the epitaxial structure <NUM> and the number of epitaxial structures <NUM> connected in parallel.

<FIG> is a cross-sectional representation of a modified nanosheet field effect transistor device structure <NUM>. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown in <FIG>, the epitaxial structure <NUM> includes a single epitaxial block.

In some embodiments, the epitaxial structure <NUM> is formed by removing the first semiconductor layers <NUM> and the second semiconductor layers <NUM> between the gate structures <NUM> by an etching process and forming a single epitaxial block between the gate structures <NUM>. Therefore, it may be easier to form the epitaxial structure <NUM>, and the production yield may be further improved and transistor current by mobility enhancement.

By forming the epitaxial structure <NUM> between a pair of contact structures <NUM>, a resistor <NUM> is formed without using an extra mask. The resistance of the resistor <NUM> may be modified by adjusting the width W of the epitaxial structure <NUM> and the number of epitaxial structures <NUM> connected in parallel. Moreover, since the epitaxial structure <NUM> includes a single epitaxial block, it may be easier to be formed the epitaxial structure <NUM>, and the production yield may be further improved and transistor current by mobility enhancement.

<FIG> is a cross-sectional representation of a modified nanosheet field effect transistor device structure <NUM>. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown in <FIG>, the epitaxial structure is not formed and the second semiconductor layers <NUM> are left between the gate structures as the body of resistor <NUM>.

By forming the second semiconductor layers <NUM> between a pair of contact structures <NUM>, a resistor <NUM> is formed without using an extra mask. The resistance of the resistor <NUM> may be modified by adjusting the width W of the second semiconductor layers <NUM> and the number of second semiconductor layers <NUM> connected in parallel. Moreover, by taking the second semiconductor layers <NUM> is as the body of the resistor <NUM>, it may save the production cost and time.

As mentioned above, in the present disclosure, a method of forming a nanosheet field effect transistor device structure is provided. With an extra epitaxial structure directly under the power rail, the power rail resistance may be reduced, the IR drop may be suppressed, and the electron migration may be improved. With vertically arranged epitaxial layers, the power rail resistance may be further reduced. With a single epitaxial block, the production yield may be improved and transistor current by mobility enhancement. With contact structures formed on opposite sides of the epitaxial structure, a resistor may be formed without using an extra mask. The resistance of the resistor may be fine-tuned by modifying the dimensions of the epitaxial structure, or connecting the same epitaxial structures in parallel.

It should be noted that although some of the benefits and effects are described in the embodiments above, not every embodiment needs to achieve all the benefits and effects.

Claim 1:
A semiconductor device structure, comprising:
a substrate (<NUM>), wherein the substrate comprises a device region (10D) and a boundary region (10B), and the device region (10D) comprises a channel region (<NUM>) and a source/drain region (<NUM>);
vertically stacked nanosheet layers (<NUM>) formed on the channel region (<NUM>), surrounded by a gate stack (<NUM>), and vertically stacked nanosheet layers (<NUM>, <NUM>) parallel to the vertically stacked nanosheet layers (<NUM>) formed on the channel region (<NUM>), formed on the boundary region (10B);
epitaxial structures (<NUM>) formed on the source/drain region (<NUM>) surrounded by a first contact structure (<NUM>) and separate epitaxial structures (<NUM>) formed on the boundary region (10B) surrounded by a second contact structure (<NUM>), the contact structures (<NUM>) separated by an interlayer dielectric (<NUM>) and interconnected by a metal layer (<NUM>) on the contact structures (<NUM>); and
a power rail (<NUM>) formed directly above the epitaxial structures (<NUM>) on the boundary region (10B) and electrically connected to the metal layer (<NUM>) with a via (<NUM>),
wherein the epitaxial structures (<NUM>) formed on the source/drain region (<NUM>) are in contact with the nanosheet layers (<NUM>) formed on the channel region (<NUM>) and function as a source/drain, and
wherein the epitaxial structures (<NUM>) on the source/drain region (<NUM>) on the device region (10D) and the epitaxial structures (<NUM>) on the boundary region (10B) are spaced apart from each other.