Patent Description:
In general, OTP devices can be blown or permanently written to a predetermined logic state. Once blown, they cannot be overwritten to a different logic state. For example, such OTP devices may include fuses or anti-fuses. On the other hand, reprogrammable devices (i.e. non-OTP devices) can be temporarily written to a logic state. The values stored in the reprogrammable devices are temporarily stored in that they can be overwritten with a different logic state.

European patent application, publication number <CIT> discloses an integrated circuit including an Al logic circuit and embedded one-time programmable MRAM memory electric coupled to the Al logic circuit. The embedded OTP MRAM memory may include multiple storage cells, one or more reference resistors, and a memory-reading circuit for determining the state of each storage cell. The reading circuit may include a multiplexer configured to electrically couple each storage cell to a reference resistor; a source line selectively providing an input electoral signal to each storage cell to generate a first output signal; a driving circuit providing an input electoral signal to the reference resistor to generate a second upper signal; and a comparator configured to compare the first output signal and second upper signal to generate an output signal that indicates the state of each storage cell. Each reference resistor may be shared among multiple storages in an array or multiple storage arrays. Document <CIT> discloses a magnetoresistive random access memory array including MRAM cells arranged in rows and columns, wherein a plurality of rows of the MRAM array is configured as a single one-time-programmable row having OTP cells.

Various optional features are described in the dependent claims.

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale.

The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.

As disclosed herein, a memory includes memory cells that can be utilized as one-time programmable (OTP) devices. A memory is arranged in rows (along word lines) and columns (along bit line/source line pairs), in which the intersection of each row (word line) and column (bit line/source line pair) has a corresponding memory cell having a storage element. Each storage element is capable of storing a logic state. In one embodiment, all the cells of a memory are configured as OTP devices. In some embodiments, the memory may include both OTP devices as well as reprogrammable memory cells (in which reprogrammable memory cells can be written multiple times over the life of the memory). The storage elements of the cells which are used as OTP devices may be "blown" during an OTP write in order to provide a permanent conductive state which is determinable from the conductive state of an unblown cell (i.e. non-blown cell). In this manner, permanent values can be stored in the memory which can later be read. Each OTP device which is not blown during the OTP write can either be in a high conductive state (HCS) or a low conductive state (LCS). Memories whose cells can either be in the LCS or HCS may include, for example, magneto-resistive random access memories (MRAMs), Resistive random access memories (ReRAMs), phase changing memories (PCM), ferroelectric random access memories (FeRAMs), electric fuse or anti-fuse type memories, or the like.

Each time a read is performed from OTP cells of the memory, a blind write is first performed as part of the read operation in order to program all non-blown cells being read to a predetermined one of the LCS or HCS prior to completing the read operation. This increases the read window for an OTP read, which may allow for the use of smaller sense amplifiers and fewer precision references.

<FIG> and <FIG> are graphs, each showing a distribution of conductivity of cells of a memory array according to one embodiment of the present invention. In <FIG> and <FIG>, the conductivity values are on the X axis and the number of cells having a particular conductivity are on the Y axis. <FIG> and <FIG> show the conductivity distribution for cells of an array that are blown and those that are not blown. The cells that are not blown are either in a LCS or a HCS.

In <FIG>, the blown cells have a conductivity distribution <NUM> centered on the conductivity value BC. The high conductivity cells have a conductivity distribution <NUM> centered on resistance CH, and the low conductivity cells have a conductivity distribution <NUM> centered on CL. The OTP reference conductivity can be centered half way between BC and CH. The reprogrammable conductivity resistance (i.e. the memory reference conductivity) can be centered halfway between CL and CH.

Therefore, if the cells of the memory array were reprogrammable memory cells, then, during a read operation, sense amplifiers would determine whether the conductivity of a particular cell is higher or lower than the reprogrammable reference conductivity (in which a higher conductivity may correspond to a logic level zero and a lower conductivity to a logic level one, or vice versa). However, if the cells of the array are all OTP cells, during a read operation, cells with a conductivity greater than the OTP reference conductivity correspond to blown cells and provide a read output value of a first logic state (e.g. <NUM>) while cells with a conductivity less than the OTP reference conductivity correspond to non-blown cells (which can be in either the LCS or HCS) and provide a read output value of a second logic state (e.g. <NUM>). In this case, the sense amplifiers of read circuitry may be provided with a voltage reference which corresponds to the OTP reference conductivity.

In this example, the read window of an OTP cell is provided by window <NUM>, which is the difference between distribution <NUM> and distribution <NUM> (the higher conductivity cells of the non-blown cells). The OTP reference conductivity should therefore be centered within window <NUM>, such as halfway between CH and BC (e.g. (CH+BC)/<NUM>). However, if it were known that all non-blown cells in a memory array were in the LCS (rather than being in either the LCS or HCS), the distribution of non-blown cells would be represented just by distribution <NUM>. In this case, the read window of an OTP cell is expanded to the difference between distribution <NUM> and distribution <NUM>, represented by window <NUM>. Window <NUM> being wider than window <NUM> allows for a less precise reference generator during reads of the OTP memory. Even with a less precise reference, there is a larger margin (between the OTP reference and distribution <NUM>) in which to determine whether or not a cell has a larger conductivity than the OTP reference conductivity.

In the example of <FIG>, the permanent state of blown cells has a conductivity that is much higher than the conductivity of the HCS. Therefore, if it is known that all non-blown cells are in the LCS (rather than being in either the LCS or HCS), the distribution of non-blown cells would be represented just by distribution <NUM>. In the example of <FIG>, the permanent state of blown cells has a conductivity that is instead much lower than the conductivity of the LCS. In this case, if it is known that all non-blown cells are in the HCS (rather than being in either the LCS or HCS), the distribution of non-blown cells would be represented just by distribution <NUM>. This would also result in a wider read window of an OTP cell (that is, the read window for the example of <FIG> is expanded to the difference between distribution <NUM> and distribution <NUM>, represented by window <NUM>, rather than window <NUM> which would be the case if the non-blown cells were in either the HCS or LCS state). Similarly, window <NUM> being wider than window <NUM> allows for a less precise reference generator during reads of the OTP memory.

Therefore as part of any read operation from the memory array <NUM>, a blind write is first performed which results in programming all non-blown cells being read to a predetermined one of the LCS or HCS prior to sensing the cells to complete the read operation. For OTP memories (e.g. resistive memories, anti-fuse type memories) whose blown state is as illustrated in <FIG> (having a conductivity greater than the HCS), the predetermined one of the LCS or HCS for the blind write is the LCS, such that, for the address location being read, distribution <NUM> shifts (as indicated by arrow <NUM>) into distribution <NUM> in which all non-blown cells being read are in the LCS and fall within distribution <NUM>. For OTP memories (e.g. fuse-type memories) whose blown state is as illustrated in <FIG> (having a conductivity less than the LCS), the predetermined one of the LCS or HCS for the blind write is the HCS, such that, for the address location being read, distribution <NUM> shifts (as indicated by arrow <NUM>) into distribution <NUM> in which all non-blown cells being read are in the HCS and fall within distribution <NUM>. By performing a blind write as part of every read operation to ensure non-blown cells are in a predetermined one of the LCS or HCS, for the read data stored at the access address, only a distribution of the predetermined one of the LCS or HCS would be present (e.g. <NUM>, <NUM>) without a distribution of cells that are in the other of the LCS or HCS (e.g. <NUM>, <NUM>), resulting in a wider read window (e.g. <NUM>, <NUM>).

In the embodiments illustrated in <FIG>, it will be assumed that the memory having OTP cells is an MRAM (whose distributions are characterized by <FIG>). Therefore, as disclosed herein, an MRAM includes an array of MRAM cells that can be utilized as one-time programmable (OTP) devices, in which the storage element of each memory cell is implemented as a magnetic tunnel junctions (MTJ). The MRAM is arranged in rows (along word lines) and columns (along bit line/source line pairs), in which the intersection of each row (word line) and column (bit line/source line pair) has a corresponding MRAM cell having a select transistor and a magnetic tunnel junction (MTJ). In one embodiment, all the cells of an MRAM are configured as OTP devices. In some embodiments, the MRAM may include both OTP devices as well as reprogrammable MRAM cells (in which reprogrammable MRAM cells can be written multiple times over the life of the memory). The MTJs of the cells which are used as OTP devices may be "blown" during an OTP write in order to provide a permanent resistance which is determinable from the resistance of an unblown cell (i.e. non-blown cell), regardless of the magnetic state of the cell. In this manner, permanent values can be stored in the MRAM which can later be read. Each OTP device which is not blown during the OTP write can either be in a high resistive state (HRS) or a low resistive state (LRS), as determined by the direction of magnetization of the free layer of the MTJ.

Note that the HRS in the MRAM corresponds to the LCS while the LRS in the MRAM corresponds to the HCS. Similarly, the blown state of an MRAM cell has a relatively low resistance value (corresponding to a relatively high conductivity value) as compared to the non-blown state, regardless of whether the non-blown cell is in the HRS (corresponding to the LCS) or the LRS (corresponding to the HCS). In one embodiment, as will be described in more detail below, each time a read is performed from OTP cells of the MRAM, a blind write is first performed as part of the read operation in order to program all non-blown cells being read to the HRS prior to completing the read operation. This increases the read window for an OTP read.

<FIG> is a diagram of an MRAM according to one embodiment of the present invention. Memory <NUM> includes an array <NUM> of MRAM cells (<NUM>-<NUM>) located in M rows and N columns (<NUM>, <NUM>, <NUM>) for storing data, in which each of M and N can be any positive integer greater than one. In the illustrated embodiments herein, it is assumed that all cells of array <NUM> are configured as OTP cells (i.e. OTP devices), therefore memory <NUM> may be referred to as an OTP memory. However, in an alternate embodiment, array <NUM> may be a portion of a larger memory array which also includes reprogrammable (i.e. non-OTP) MRAM cells. In this alternate embodiment, note that more circuitry may be needed in memory <NUM> than those elements illustrated in <FIG>. MRAM <NUM> also includes a control circuit <NUM> which receives read and write access requests for MRAM <NUM>. Each access request includes a corresponding access address (ADDR) which identifies (i.e. addresses) a selected set of MRAM cells for the access request, a corresponding read/write indicator (R/W) which indicates whether the access request is a read or a write request, and corresponding write data (DATA) if the access request is a write request. Control circuit <NUM> also includes a read state machine <NUM> (which may also be referred to as a read operation controller).

Still referring to <FIG>, column <NUM> includes cells <NUM>-<NUM>, column <NUM> includes cells <NUM>-<NUM>, and column <NUM> includes cells <NUM>-<NUM>. In one embodiment, each cell (<NUM>) is characterized as an MRAM cell that includes a magnetic tunnel junction (MTJ) (<NUM> for cell <NUM>) and a select transistor (<NUM> for cell <NUM>) whose control terminal is coupled to a word line (WL1 for cell <NUM>) that is asserted to access a specific row of memory cells for either reads or writes to the cells. The word lines (WL1-WLM) are provided by an address row decoder <NUM> and are selectively activated (i.e. asserted) based on the memory address of an access request received by control <NUM> from processing circuity (not shown).

Each MRAM cell of a column is connected to a corresponding array bit line of the column (one of ABL1-ABLN) and a corresponding array source line of the column (a corresponding one of ASL1-ASLN). In the illustrated embodiment, the MRAM cell is connected to the array source line at the source of the select transistor. For example, MRAM cell <NUM> is connected to ABL1 of column <NUM>, and the corresponding ASL1 of column <NUM>, in which ASL1 is connected at the source of select transistor <NUM>. Although <FIG> shows that array <NUM> includes four rows (corresponding to word lines WL1-WLM) and three columns (<NUM>, <NUM>, and <NUM>), other embodiments may include a different number of rows (M) and/or a different number of columns (N).

In some embodiments, the MTJs of the cells <NUM>-<NUM> of MRAM array <NUM> have the same structure. As used herein, MTJs having the same structure mean that the corresponding structures of the MTJs have the same physical dimensions and are made of the same materials within manufacturing tolerances. Note that although a one-transistor one-resistor (1T1R or 1T1MTJ) is illustrated in <FIG>, the cells can have a different configuration, such as a one-transistor two-resistor (1T2R) configuration. As used herein with respect to information stored in a memory, the term "data" also includes instructions or commands stored in a memory.

Memory <NUM> includes read circuitry <NUM> for reading data stored in the cells of array <NUM>. In the embodiment shown, read circuitry <NUM> includes sense amplifiers (SAs) <NUM> and <NUM>, each for sensing the data value stored in a memory cell by comparing the resistance of the memory cell to a reference resistance. During a read operation, a sense amplifier (e.g. SA1 <NUM>) is coupled to a corresponding bit line (e.g. ABL1) of a selected column (e.g. <NUM>) by column decoder <NUM> to compare a resistance of a selected cell (e.g. <NUM>) of that column to the reference resistance. (Alternatively, the sense amplifiers can each be coupled to a corresponding source line instead of a corresponding bit line. ) Each sense amplifier also receives a read enable signal (RD_EN) from control circuit <NUM> which is asserted to enable the sensing of the data values stored in a selected set of MRAM cells indicated by a received read access address. The sense amplifiers SA1-SAK output the read data (DO1-DOK) to processing circuitry (not shown) on a data bus (not shown). A reference signal, REF, indicative of the reference resistance is provided to the sense amplifiers by a reference circuit <NUM>.

Note that in alternate embodiments in which other types of memories are used, such as ReRAM, PCM, FeRAM, fuse or anti-fuse type memories, etc., the reference signal, REF, may instead be indicative of the reference conductivity. The sense amplifiers may be coupled to the bit lines or source lines, as needed, to sense voltage or current, as needed, to determine the conductivity of a selected cell for comparison with the reference conductivity.

Memory <NUM> includes write circuitry <NUM> for writing data to memory cells of array <NUM>. In the embodiment shown, write circuitry <NUM> includes bit line control circuits (e.g. <NUM> and <NUM>) for controlling the voltage of the array bit lines (ABL1, ABLN) of selected columns during a memory write operation to selected MRAM cells of the array. The write circuitry also includes source line control circuits (e.g. <NUM> and <NUM>) for controlling the voltage of the array source lines (ASL1, ASLN) of selected columns during a memory write operation to the selected MRAM cells.

During reads and writes, control circuit <NUM> provides a first portion of ADDR to row decoder <NUM> and a second portion of ADDR to column decoder <NUM>. During a memory access operation (read or write), row decoder <NUM> activates a selected word line based on the received first portion of ADDR. Row decoder <NUM> may activate the selected word line by setting the selected word line to a voltage that is greater than ground.

During a memory access operation, column decoder <NUM> couples a selected subset of K columns of array <NUM>, based on the second portion of ADDR, to read circuitry <NUM> or write circuitry <NUM>. For example, during a memory write operation, column decoder <NUM> couples the K array bits lines of the K selected columns to the corresponding bit line control circuits (e.g. <NUM> and <NUM>) via write bit lines (WBL1-WBLK) and the corresponding K array source lines of the K selected columns to the corresponding source line control circuits (e.g. <NUM> and <NUM>) via write source lines (WSL1-WSLK). During a memory read operation, column decoder <NUM> couples the K array bit lines of the K selected columns to sense amplifiers SA1 -- SAK via read bit lines (RBL1-RBLK). In an alternate embodiment, the source lines of the K selected columns, instead of the bit lines, may be coupled to the sense amplifiers via read source lines. During the memory read operation, as will be discussed further below, column decoder <NUM> also couples the K array bit lines of the K selected columns to the corresponding bit line control circuits, and the K array source lines of the K selected columns to the corresponding source line control circuits.

In one embodiment, the decode ratio (N/K) of decoder <NUM> is <NUM> to <NUM>, where N is the number of columns in array <NUM> and K is the number of sense amplifiers/line control circuit pairs. However, this ratio may be of other values in other embodiments (e.g. <NUM>, <NUM>, <NUM>). In one embodiment, K is <NUM> and N is <NUM>, but these may be of different values in other embodiments. Some embodiments do not include a column decoder where each column includes its own sense amplifier and bit line control circuit/source line control circuit pair.

In one embodiment, memory <NUM> is located on the same integrated circuit (IC) as the processing circuitry (not shown) that requests the memory accesses. In other embodiments, memory <NUM> may be located on a separate integrated circuit. In still other embodiments, memory <NUM> may have other configurations. Also, in one embodiment, any OTP memory cells can be located outside of an array configuration, and, although area inefficient, may even be scattered around the IC.

The cells of array <NUM> can be utilized as reprogrammable MRAM cells where a data state can be changed multiple times over the life of array <NUM> or OTP cells where a data state can be permanently programmed in the cell. In the illustrated embodiment, all cells of array <NUM> are utilized as OTP cells, but the structure of the MTJs in an OTP cell is the same as they would be in a reprogrammable MRAM cell.

<FIG> is a side view of an MRAM cell, which can represent any of the OTP cells of array <NUM> of <FIG>, according to one embodiment of the present invention. In the embodiment shown, an access transistor <NUM> of cell <NUM> is a complementary metal-oxide-semiconductor (CMOS) transistor with a source region <NUM> and drain region <NUM> located in a semiconductor substrate <NUM> of an integrated circuit. Source region <NUM> is connected to array source line ASL1. Drain region <NUM> is connected to magnetic tunnel junction (MTJ) <NUM> by via <NUM> which is located in one or more interconnect layers of the integrated circuit of the MRAM. The gate <NUM> of transistor <NUM> is connected to a word line WL1.

In the embodiment shown, MTJ <NUM> includes a conductive contact layer <NUM>, a pinned magnetic layer <NUM>, a tunnel dielectric layer <NUM>, and a free magnetic layer <NUM>. In the embodiment shown, MTJ <NUM> also includes additional layers <NUM> that include conductive layers. In one embodiment, pinned magnetic layer <NUM> and free magnetic layer <NUM> are made of ferromagnetic materials such as cobalt iron boron (CoFeB) and tunnel dielectric layer is made of a dielectric material such as magnesium oxide (MgO). However, these layers may be made of other materials in other embodiments. Also, in other embodiments, an MRAM cell may have other configurations.

The magnetization direction of the pinned layer <NUM> is fixed. The magnetization direction of free layer <NUM> can be programmed to be in a parallel direction or an anti-parallel direction to the magnetization direction of pinned layer <NUM> in order to place the cell <NUM> into a high resistive state (HRS) or a low resistive state (LRS). When the magnetization direction of free layer <NUM> is in an anti-parallel direction, the resistance of the MTJ is at a relatively high value, corresponding to the HRS. When the magnetization direction of free layer <NUM> is in a parallel direction, the resistance of the MTJ is of a relatively lower value, corresponding to the LRS. If cell <NUM> were utilized as a reprogrammable MRAM cell, the HRS corresponds to storing <NUM> in the memory cell, and the LRS to storing a <NUM>. A sense amplifier coupled to both the array bit line of the cell and to a reference resistance that is in between the high resistive value and the low resistive value could determine, during a read of the reprogrammable cell, whether a one (<NUM>) value (e.g. HRS, corresponding to LCS) or a zero (<NUM>) value (e.g. LRS, corresponding to HCS) is stored in the MTJ. Alternatively, the HRS (and thus the LCS) may instead correspond to a zero value and the LRS (and thus HCS) to a one value, however, for the embodiments discussed herein, it is assume that the HRS (and thus LCS) corresponds to the one value.

During a write operation to a reprogrammable MRAM cell, the magnetization direction of free layer <NUM> can be set by applying a voltage differential of sufficient magnitude across the MTJ to generate the desired current density for setting the magnetization direction of free layer <NUM>. In one embodiment, the magnetization direction of free layer <NUM> can be set in one direction by applying a higher voltage (VH) to the array bit line (ABL1) and a lower voltage (Gnd) to the source line (ASL1) while the select transistor is conductive, and can similarly be set in the other direction by applying the lower voltage (Gnd) to the array bit line and the higher voltage (VH) to the array source line while the select transistor is conductive. That is, current in a first direction through the MTJ programs the MTJ to a first logic state, and current in a second direction, opposite the first direction, programs the MTJ to a second logic state. In this manner, a reprogrammable MRAM cell can be programmed any number of times to the HRS or LRS, to store a <NUM> or a <NUM>.

In one embodiment, layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> have a circular disk configuration where the width shown in <FIG> is the diameter of the circle. The greater the surface area of the circle, the higher the voltage differential needed to switch the resistive state of the cell. In one embodiment, the voltage differential between VH and ground is in the range of <NUM>-<NUM> Volts but may be of other values in other embodiments.

While a reprogrammable MRAM cell can be in the HRS or the LRS, an OTP MRAM cell (or the MTJ within the OTP MRAM cell) can either be in a permanently blown state or in a non-blown state. Assuming cell <NUM> is an OTP cell, during a write operation, a sufficiently higher voltage differential can be applied between the array bit line and array source line when select transistor <NUM> is conductive to permanently break down the resistance of tunnel dielectric layer <NUM>. In this manner, MTJ <NUM> results in having a relatively low resistance value (and thus a relatively high conductivity value) as compared to the resistance value (or conductivity value, respectively) of a non-blown cell (whether in the HRS or the LRS) where the tunnel dielectric layer is not broken down. As used herein, a cell whose tunnel dielectric has been permanently broken down is referred to as a blown cell and is thus in a permanently blown state. In one embodiment, a blown cell corresponds to permanently storing an OTP value of zero (<NUM>). In one embodiment, a non-blown cell (i.e. a cell being in the non-blown state), regardless of whether it is in a HRS or a LRS, corresponds to storing a value of one (<NUM>). Once a cell has been blown, it cannot be programmed to provide the HRS or the LRS value (i.e. the LCS or the HCS value) regardless of the magnetization direction of free layer <NUM>. Therefore, any write operation to a blown OTP cell does not change the stored value of the cell.

<FIG> is a graph showing a distribution of resistances of cells of an MRAM array according to one embodiment of the present invention. In <FIG>, the resistance values are on the X axis and the number of cells having a particular resistance are on the Y axis. <FIG> shows the resistance distribution for cells of an MRAM array that are blown and those that are not blown (note that <FIG> is analogous to <FIG>). The cells that are not blown are either in a low resistance state or a high resistance state depending upon, in one embodiment, whether the magnetization direction of the free layer of its MTJ is in a parallel or anti-parallel direction with the magnetization of the fixed layer. In the embodiment shown, the blown cells have a resistance distribution <NUM> centered on the resistive value RB. The low resistance state cells have a resistance distribution <NUM> centered on RL, and the high resistance state cells have a resistance distribution <NUM> centered on resistance RH. The OTP reference resistance can be centered halfway between RB and RL. The reprogrammable MRAM reference resistance can be centered halfway between RL and RH.

Therefore, if the cells of the MRAM array were reprogrammable MRAM cells, then, during a read operation, sense amplifiers would determine whether the resistance of a particular cell is higher or lower than the reprogrammable MRAM reference resistance. However, the cells of MRAM array <NUM> are OTP cells, in which, during a read operation, cells with a resistance less than the OTP reference resistance correspond to blown cells and provide an read output value of <NUM> while cells with a resistance greater than the OTP reference resistance correspond to non-blown cells (which can be in either the HRS or LRS) and provide a read output value of <NUM>. In this case, the sense amplifiers of read circuitry <NUM> may be provided with a voltage reference which corresponds to the OTP reference resistance.

In this example, the read window of an OTP cell is provided by window <NUM>, which is the difference between distribution <NUM> and distribution resistance <NUM> (the lower resistance cells of the non-blown cells). The OTP reference resistance should therefore be centered within window <NUM>, such as half way between RB and RL (e.g. (RB+RL)/<NUM>). However, if it were known that all non-blown cells in an MRAM array were in the HRS (rather than being in either the LRS or HRS), the distribution of non-blown cells would be represented just by distribution <NUM>. In this case, the read window of an OTP cell is expanded to the difference between distribution <NUM> and distribution <NUM>, represented by window <NUM>. Window <NUM> being greater than window <NUM> allows for a less precise reference generator during reads of the OTP MRAM memory. Even with a less precise reference, there is a larger margin (between the OTP reference and distribution <NUM>) in which to determine whether or not a cell has a larger resistance than the OTP reference resistance.

Therefore, in one embodiment, as part of any read operation from array <NUM>, a write of "<NUM>" to all cells being read (corresponding to programming these cells to the HRS) is performed prior to sensing the cells to complete the read operation. In doing so, for the address location being read, distribution <NUM> shifts (as indicated by arrow <NUM>) into distribution <NUM> in which all non-blown cells being read fall within distribution <NUM>. By performing a write as part of every read operation to ensure non-blown cells are in the HRS, for the read data stored at the access address, a distribution of LRS cells (e.g. <NUM>) would no longer be present, only a distribution of HRS cells (e.g. <NUM>). This results in the wider read window <NUM>.

<FIG> illustrates example circuitry for implementing the bit line and source line control circuits of <FIG>. <FIG> illustrates bit line control circuit <NUM> and source line control circuit <NUM> in accordance with one embodiment of the present invention. Each of bit line control circuit <NUM> and source line control circuit <NUM> receives a corresponding data bit of the write data (e.g. DI1), a blind write indicator (BW), and a write enable signal (WR_EN). Bit line control circuit <NUM> includes inverter <NUM>, AND gate <NUM>, and switches <NUM>, <NUM>, and <NUM>. Source line control circuit <NUM> includes an AND gate <NUM> and switches <NUM>, <NUM>, and <NUM>. As used herein, each switch receives a control signal, which when asserted, indicates the switch is on or closed and thus in a conductive state, and when negated, indicated the switch is off or open and thus in a non-conductive state. The switches herein can be implemented with any type of switching circuitry, such as a transistor or combination of transistors. Switch <NUM> is coupled between WBL1 and a circuit node <NUM> of bit line control circuit <NUM>, and switch <NUM> is coupled between WSL1 and a circuit node <NUM> of source line control circuit <NUM>. Each of switches <NUM> and <NUM> receive WR_EN as a control signal such that when WR_EN is asserted, switches <NUM> and <NUM> are on or closed to connect WBL1 to circuit node <NUM> and WSL1 to circuit node <NUM>.

Switch <NUM> is coupled between a first voltage supply terminal and circuit node <NUM>, and switch <NUM> is coupled between a second voltage supply terminal and circuit node <NUM>. The first voltage supply terminal provides a voltage, VB, which is greater than a voltage, GND, provided by the second voltage supply terminal. Note that for simplicity, each of the first and second voltage supply terminals may be referred to as VB and GND, respectively.

Switch <NUM> receives an output of inverter <NUM> as a control signal. An input of inverter <NUM> is coupled to receive BW, which, when asserted, indicates a blind write is being performed and when negated, indicates a blind write is not being performed. Therefore, switch <NUM> is controlled by BW in which switch <NUM> is on, providing VB to node <NUM>, when BW is negated. Switch <NUM> is off and decouples VB from node <NUM> when BW is asserted. Switch <NUM> receives an output of AND gate <NUM> as a control signal. A first input of AND gate <NUM> is coupled to receive DI1 and a second input is coupled to receive BW. Therefore, when both DI1 and BW are asserted to a logic level one, switch <NUM> is on providing GND to circuit node <NUM>. When either DI1 or BW are negated to a logic level zero, switch <NUM> is open and decouples GND from circuit node <NUM>.

Switch <NUM> is coupled between a third voltage supply terminal and circuit node <NUM>, and switch <NUM> is coupled between GND and circuit node <NUM>. The third voltage supply terminal provides a voltage, VH, which is greater than GND but less than VB. Note that for simplicity, the third voltage supply terminal may be referred to as VH.

Switch <NUM> receives BW as a control signal. When BW is asserted, switch <NUM> is on, providing VH to circuit node <NUM>, and when BW is negated, switch <NUM> is off, decoupling VH from circuit node <NUM>. Switch <NUM> receives an output of AND gate <NUM> as a control signal. A first input of AND gate <NUM> is coupled to receive an inverse of DI1 (as indicated by the bubble at the first input) and a second input is coupled to receive an inverse of BW (as indicated by the bubble at the second input). Therefore, when both DI1 and BW are negated to a logic level zero, switch <NUM> is on providing GND to circuit node <NUM>. When either DI1 or BW are asserted to a logic level one, switch <NUM> is opened and decouples GND from circuit node <NUM>.

In operation, each of circuits <NUM> and <NUM> provide the appropriate write voltage to WBL1 and WSL1 during a write (when WR_EN is asserted). During the write, WBL1 is connected to either VB or GND and WSL1 is connected to either VH or GND, depending on the values of BW and DI1. During an OTP write (BW=<NUM>) in which the MTJ connected to WBL1 and WSL1 is to be blown, VB is provided to WBL1 while WSL1 is at GND. VB should provide a voltage level such that the differential between VB and GND is sufficient to blow the MTJ. During a blind write (BW=<NUM>), VH is provided to WSL1 while WBL1 is at GND. In this case, the direction of the current through the MTJ connected to WBL1 and WSL1 sets the MTJ to the HRS, but should not blow the MTJ. Note that a blind write is also characterized as a non-OTP write.

Each of bit line control circuits and source line control circuits of write circuitry <NUM> are implemented in the same way. In one embodiment, they are all implemented as illustrated in <FIG>. In other embodiments, note that the logic provided by the circuitry and logic gates of <FIG> can be implemented with different circuitry, including different circuit implementations. In another embodiment, in which memory <NUM> also includes reprogrammable MRAM cells, the bit line and source line control circuits may need further circuitry in order to implement regular writes to the reprogrammable MRAM cells to direct current through the MTJs as needed to write non-OTP ones or zeros to these MRAM cells.

Note that in alternate embodiments, in which the memory is a different type of memory, such as an ReRAM, PCM, or FeRAM, the bit line control circuits and source line control circuits may be implemented differently, as needed, to apply the appropriate voltage over the storage elements to blow the storage elements or to program them to the desired LCS or HCS. In alternate embodiments, each bit line control circuit and source line control circuit would also receive the appropriate voltage values, similar to VB, VH, and GND, as needed for the OTP writes or non-OTP writes.

Operation of memory <NUM> with respect to reads and writes will be described further in combination with <FIG> and <FIG> illustrates, in flow diagram form, a method <NUM> for per performing a write operation and a read operation to memory <NUM> of <FIG>. Method <NUM> begins by receiving a write request (in block <NUM>) in which the write request has a corresponding write access address (e.g. ADDR) of an OTP memory (e.g. memory <NUM>) and corresponding OTP write data (e.g. DATA). In this case, R/W indicator would be negated to zero to indicate that the request is a write request.

In block <NUM>, an OTP write operation of the received write data is performed to the corresponding write access address. In performing the OTP write operation, a first supply voltage, VB, is used to blow the memory cells being written with the <NUM> of the received OTP write data. In the illustrated example of memory <NUM> in <FIG>, control circuit <NUM> receives ADDR, R/W, and DATA. Control circuit <NUM> provides a portion of the address to row decoder <NUM> to activate the word line corresponding to the memory cells selected by the access address. In one embodiment, a first word line voltage, which may be greater than the voltage applied to the word line to typically write a reprogrammable MRAM cell, is applied to the word line to activate the word line. Control circuit <NUM> also provides a portion of the address to column decoder <NUM> which couples the bit lines and source lines of the selected memory cells to WBL1-WBLK and WSL1-WSLK, respectively. Control circuit <NUM> provides the K-bit DATA as the data input (DI) to the bit line and source line control circuits. Therefore, DI1-DIK is provided to each of WBL1-WBLK, respectively, and to each of WSL1-WSLK, respectively.

For the write operation of block <NUM>, control circuit <NUM> asserts WR_EN since a write operation is occurring (as indicated by the R/W indicator). Control circuit <NUM> also negates BW to zero since an OTP write operation is occurring rather than a blind write. For programming OTP write data into OTP memory <NUM>, only writes of <NUM> are performed in which the memory cells receiving the <NUM> are blown. The <NUM> in the programmed OTP data simply correspond to cells which are not blown. Therefore, during the write of OTP data, the cells receiving <NUM> of the write data are blown and nothing is done to the cells receiving <NUM> of the write data.

Referring to <FIG> as an example for this write, if DI1 is a zero, then the corresponding selected MTJ should be blown. With BW = <NUM> and WR_EN = <NUM>, switches <NUM>, <NUM>, <NUM>, and <NUM> are all on and switches <NUM> and <NUM> are off. Therefore, for any bit of the write data which is a <NUM>, VB is provided to the bit line (WBL1) and the source line (WSL1) is grounded, resulting in a voltage differential over the selected MTJ which blows the MTJ. However, if DI1 were instead a one, switches <NUM>, <NUM>, and <NUM> are on, but switches <NUM>, <NUM> and <NUM> are off. Therefore, for any bit of the write data which is a <NUM>, VB is provided to the bit line but the source line is left floating, which inhibits any current through the selected MTJ, and the selected MTJ still remains non-blown.

Blocks <NUM> and <NUM> can be used to perform any number of OTP writes to memory <NUM>. For example, these OTP writes can be performed during manufacture, before or after solder reflow of an integrated circuit containing memory <NUM>. Since no current is provided during OTP writes of <NUM> to the selected cell, the resistance of the cell is not typically known. That is, it may be in a HRS or a LRS. Anytime after programming OTP memory <NUM> with OTP data, OTP memory <NUM> can be read.

In block <NUM>, a read request is received by the OTP memory to read the OTP data stored at the corresponding read access address. In this case, control circuit <NUM> receives the read access address, ADDR, and the R/W indicator would be asserted to <NUM> to indicate a read access request. As with a write operation, control circuit <NUM> provides a portion of the address to row decoder <NUM> to activate the word line corresponding to the memory cells selected by the access address. In one embodiment, a second word line voltage, which may be lower than the first word line voltage (applied to the word line during an OTP write operation), is applied to the word line to activate the word line. For the read operation, control circuit <NUM> also provides a portion of the address to column decoder <NUM> which couples the bit lines of the selected memory cells to the read bit lines (RBL1-RBLK), respectively, and couples the bit lines and source lines of the selected memory cells to WBL1-WBLK and WSL1-WSLK, respectively. (Although not illustrated, in an alternate embodiment, column decoder <NUM> may couple the source lines of the selected memory cells to read source lines. ) In response to the read request, a read operation (block <NUM>) is performed. The read operation (block <NUM>) includes both a blind write portion (block <NUM>) and a subsequent read portion (<NUM>), which are controlled by control circuit <NUM>. In one embodiment, the write and read portions of the read operation are controlled by read state machine (SM) <NUM> within control circuit <NUM>.

First, in block <NUM>, control circuit <NUM> (e.g. read SM <NUM>) asserts both BWand WR_EN to a logic level <NUM> and negates RD_EN to a logic level <NUM> for a first portion of the read operation in order to perform a write of all <NUM> to the read access address, using VH. Control circuit <NUM> driving BW to a logic level one forces a write of all <NUM> (in which DI1-D1K are provided as all <NUM> to the bit line and source line control circuits of write circuitry <NUM>). Referring to <FIG>, with BW=<NUM>, WR_EN=<NUM>, and DI1 = <NUM>, switches <NUM>, <NUM>, <NUM>, and <NUM> are on, and switches <NUM> and <NUM> are off. This results in VH being provided to all the write source lines WSL1-WSLK, and all write bit lines WBL1-WBLK being grounded. In this manner, all MTJs in the selected cell (selected by the access address of the read request) are programmed to the HRS. This write is characterized as a blind write because a write of <NUM> is performed on the MTJs of all the cells selected by the access address of the read request, regardless of whether a particular MTJ has previously been blown or not (i.e. regardless of whether a particular cell already stores an OTP zero or not. ) Note that a blind write of <NUM> is inhibited because control circuit <NUM> forces all write data to a <NUM> for the blind write operation. Note also that during the blind write portion of the read operation, RD_EN is negated such that the sense amplifiers SA1-SAK are not yet enabled.

Secondly, in block <NUM> which occurs after completion of the blind write in block <NUM>, BW and WR_EN are negated to <NUM> and RD_EN is asserted to <NUM> for a second portion of the read operation. With RD_EN asserted, sense amplifiers SA1-SAK sense the selected cells by comparing the voltage on each selected bit line to a reference voltage, REF, received from reference circuit <NUM> to obtain the OTP data from the read access address and output the obtained OTP data as the read data output of the read operation (DO1-DOK). In an alternate embodiment, REF may correspond to a reference current instead in which the sense amplifiers compare the current on each selected bit line with the reference current. Note that REF is indicative of the reference resistance, as was discussed with respect to <FIG>.

Since a blind write to at least the memory cells corresponding to the read access address guarantees that any non-blown memory cells are in the HRS prior to sensing the cells, reference circuit <NUM> is capable of providing a less precise reference voltage or current, due to the wider read window as was described above in reference to the graph of <FIG>. This allows for smaller reference or bias generation circuits and reduced standby currents. Also, since a blind write is performed, each of the non-blown memory cells being read is set to the HRS without knowing or needing to know the values of the originally stored data.

In addition to increasing the read window, blind writes may also be used for tampering detection. For example, a normal read can first be performed and the read data stored somewhere, followed by a blind write and a subsequent read (similar to the read from OTP cells described herein). The read data from the subsequent read can then be compared to the stored read data from the prior normal read to determine if a tampering condition has occurred with respect to the selected address. Note that this method may require the use of more precise references, but that may be justified in order to achieve improved tampering detection.

Therefore, by now it can be understood how the read window of an OTP memory, such as an OTP MRAM memory, can be widened, allowing for generation of an imprecise reference for read operations. In one embodiment, this is achieved by performing a blind write in the first portion of every read operation. The blind write programs every memory cell selected by the access address corresponding to the read operation, regardless of the conductivity of the selected memory cells. With the blind write, those non-blown storage elements of the selected cells are set to a predetermined one of the LCS or HCS while the blown storage elements remain unaffected. For example, for an OTP MRAM memory, the blind write writes a <NUM> to every selected MRAM cell, regardless of the resistances of the selected MRAM cells, such that those non-blown MTJs of the selected cells are set to the HRS while the blown MTJs remain unaffected. After completion of the blind write, in the subsequent second portion of the read operation, the read operation is completed by sensing the selected cells and providing the sensed data from the selected cells as the read OTP data.

Claim 1:
A memory comprising:
a plurality of one-time programmable, OTP, memory cells, wherein each OTP memory cell includes a corresponding storage element, wherein the corresponding storage element is capable of being in a permanently blown state or non-blown state, in which, in the non-blown state, the corresponding storage element is capable of being in a low conductive state, LCS, or a high conductive state, HCS, the LCS corresponding to a lower conductivity than the HCS;
characterised in that the memory is further comprising :
control circuitry configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells:
direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and
after the write circuitry applies the voltage differential across the corresponding storage element of each selected OTP memory cell, direct read circuity to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.