Patent Description:
Portable electronic devices are ubiquitous accoutrements in modern life. Cellular telephones, smartphones, satellite navigation receivers, e-book readers and tablet computers, wearable computers (e.g., glasses, wrist computing), cameras, and music players are just a few examples of the many types of portable electronic devices in widespread use. Portable electronic devices are powered by batteries - either replaceable batteries such as alkaline cells, or rechargeable batteries such as NiCd, NiMH, LiOn, or the like. In either case, the useful life of portable electronic devices is limited by available battery power, which decreases in proportion to the length of use of the device, and the level of power consumption during that use.

Trends in portable electronic device design exacerbate the problem of limited available power. First, device form factors tend to shrink, due to increasing integration of electronics and miniaturization of component parts, such as disk drives. This forces the size of the battery to shrink as well, which generally reduces the available energy storage capacity. Second, electronic devices are increasingly sophisticated, offering new applications, more sophisticated user interfaces, enhancements such as encryption, and the like. The additional software implementing these features requires increased computational power to execute, which translates to larger, or additional, processors and more memory. Finally, successive generations of portable electronic device often add additional features such as various modes of wireless connectivity, which may require the integration of additional chip sets and other electronics. An increase in the demand for power by more processors and circuits, coupled with ever-shrinking battery size and capacity, has made power management a critical area of optimization for portable electronic device designers.

Several approaches to power management are known in the art. One such approach is to identify circuits (or sub-circuits) that are not used for extended periods, and put them into a low-activity state, also referred to as a "sleep" mode, even if other circuits in the device are fully active. As one example, the illuminated display screen of many devices will shut off after a (selectable) duration of no user interactivity. One way to shut down digital circuits is to isolate clocks signals from these circuits. Since storage elements within the digital circuits only change state in response to clock signal edges or levels, power-consuming electrical activity within the circuits effectively ceases.

A more sophisticated approach to the "sleep" technique is to match the frequency of a clock signal to the level of activity of a digital circuit. For example, a processor engaged in heavy computation may be clocked at a high frequency, to extract maximum performance. However, when the processor is performing merely background tasks, the frequency of its clock signal may be reduced without a user-noticeable degradation of performance, which concomitantly reduces the power consumed.

Another approach to power management is to vary the power supplied to various circuits (or sub-circuits) according to the instantaneous load of the circuit. In this manner, circuits that are engaged in computation or other activity are provided sufficient power to operate, and circuits experiencing a lighter load are provided with a lower level of current.

All of these power management techniques are problematic when applied to a wireless modem, which may include a digital broadband integrated circuit (IC), radio frequency IC, and power amplifier. When user is actively using the data connection and expecting high download speed and short latency, the modem is configured with highest performance settings, such as high speed clocks, full power, and all circuits enabled. When the data connection requirements are relaxed, there is an opportunity to save power by lowering the wireless modem performance, such as by lowering clock frequencies, gating clocks to some circuits, lowering supply voltages, and shutting down circuits that are not used. Such wireless modem throttling is limited by the fact that the user may resume data connection usage at any time, and the wireless modem must return from a power-saving mode to full performance, without user-perceptible delay. This means that the wireless modem has few tens of milliseconds to resume from a power-saving mode to a high performance mode.

When the wireless mode enters a limited performance or power-saving mode, voltage regulators may be configured to a mode where output current capability is limited. Another power-saving measure is to limit clock signal distribution to switching mode analog blocks (e.g., Switched Mode Power Supply) by digital control such as clock gating, or even disabling the clock generation circuit completely. Disabling the clock generation circuit achieves best power savings, but it can be done only when none of the wireless modem circuits require a clock signal. Another constraint is that the clock generation circuit must have a start-up time fast enough to satisfy the full power transition time requirements of all blocks receiving the clock signal(s).

New generations of wireless modem design simultaneously require higher frequency and reduced power consumption. For example, a <NUM> control bus is targeted, in future designs, to operate at <NUM>. One approach to reaching these challenging design goals is to enter restricted-clock, or "sleep" mode more often. However, this requires a very fast start-up time from the dormant state, such as <NUM> u-sec, compared to current designs of <NUM> u-sec.

A large challenge to designing a clock generation circuit with a fast start-up time, but which consumes little power during operation, is that RC factors are large and bias currents are small. As intermediate nodes begin to charge from ground (or supply voltage), they not only charge slowly but also it takes time for transient perturbations in the node voltages to settle. Settling of the node voltages at the proper operating values is essential to achieve an accurate clock signal.

Known approaches to decreasing the clock generation circuit start-up time include boosting bias currents, disconnecting capacitors, and transferring target voltages directly to intermediate and output nodes. All of these approaches suffer from the deficiency that once intermediate circuit nodes are charged, it still takes time to settle the node voltage sufficiently to achieve frequency stability. Accordingly, the known approaches are insufficient to reduce clock generation circuit start-up time by the necessary amount.

Korean Patent Publication No. <CIT>, titled "Low power relaxation oscillator circuit," describes a boost circuit that injects current into both nodes n1 and n2 of the capacitor C of a relaxation oscillator.

The paper by <NPL>, describes a scheme to shift the oscillator switching delay to prior to a comparator reaching a reference voltage as the capacitor charges. This is accomplished by doubling the charging current at the beginning of every half cycle of oscillation, which the authors refer to as "boost charging.

<CIT>describes a dual mode relaxation oscillator that generates clock signals in both normal and low-power mode, with the clock in low-power mode being less accurate.

<CIT>describes a multi-mode relaxation oscillator which generates a lower frequency clock signal in low-power mode than in normal operating mode.

The Application note AN9334. <NUM> published by <NPL>, describes a crystal oscillator having an enable pin operative to turn off an output buffer in stand-by mode to save power. The internal oscillator continues to run in stand-by mode. Power savings are limited to <NUM>%.

None of these prior art solutions can achieve a high frequency clock generation circuit having a low-power mode with approximately <NUM>% power consumption reduction, yet with very short start-up time to return to full operating mode of approximately <NUM> u-sec.

The Background section of this document is provided to place the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

<CIT> discloses a method for calibrating bias current for low power real time clock oscillator.

<CIT> discloses a main power module being configured to selectively supply a power and clock signal to change the power stage of devices.

<CIT> discloses reacquiring timing reference from a wireless network after a sleep mode.

According to the technical background of the invention, a clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values (i.e., in ON mode). This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON - for example, in the range of <NUM>% of startup time from OFF to ON (i.e., <NUM> usec as compared to <NUM> usec). The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem). The small bias current applied in STANDBY mode may be in the range of <NUM>% of the bias current applied to the clock generation circuit in ON mode.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings.

For simplicity and illustrative purposes, the present invention is described by referring mainly to an exemplary embodiment thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention.

<FIG> depicts portions of a representative system <NUM> in a portable electronic device. The system <NUM> includes a Power Management Unit (PMU) <NUM> and an electronic circuit <NUM>, such as the baseband processing system of a wireless communication terminal. A digital baseband circuit is the heart of a wireless modem in a communication terminal, receiving baseband data an RF transceiver (not shown) and decoding user data from it, as well as encoding user data and sending it to the RF transceiver to be transmitted over the air.

The PMU <NUM> includes a clock generation circuit <NUM>, a Switched Mode Power Supply <NUM>, and a control circuit <NUM>. The clock generation circuit <NUM> generates one or more clocking signals to drive the power-transfer switches in the SMPS <NUM>, which regulates and transfers power (e.g., from a battery) to the digital or analog electronic circuit <NUM>, and other circuits (not shown). Thus, suspending the operation of the clock generation circuit <NUM> will shut down power supplied to the electronic circuit <NUM>.

The electronic circuit <NUM> includes a power controller circuit <NUM>, and may include various digital or analog circuits, such as a processor <NUM> and/or Digital Signal Processor (DSP) <NUM>, and a high speed interface <NUM>, such as to memory, an external bus, a wireless transceiver, or the like. The power controller circuit <NUM> may communicate with the PMU control circuit <NUM> via a serial interface such as I2C or SPMI. The PMU <NUM> thus receives clock requests and commands from the power control circuit <NUM>, and controls circuits on the PMU <NUM> in response, such as adjusting bias voltages and currents, enabling/disabling clock drivers, adjusting the duty cycle of the SMPS <NUM> switching, and the like. Only the control signals relevant to discussion of the present invention are shown; those of skill in the art will recognize that the circuits depicted many interact via numerous other control, clock, power, and similar signals. Accordingly, those of skill in the art will readily recognize that the block diagram of <FIG> is representative only, and is no way limiting regarding the application of the present invention.

To preserve battery power, one or more of the circuits <NUM>, <NUM>, <NUM> may be placed into "sleep" mode, by reducing or eliminating the power supplied to the circuit <NUM>, <NUM>, <NUM>, or by suspending the clock signals supplied to a digital circuit. One straightforward way to suspend power from the SMPS <NUM> is to halt the clock signal from the clock generation circuit <NUM> that drives the SMPS <NUM> energy transfer switches. The clock signal may be suspended by gating off the output of the clock generation circuit <NUM>, while leaving its internal oscillator running. This allows for faster start-up time, but is less efficient as the clock generation circuit <NUM> continues to consume power. For greater power savings, when a long startup time can be tolerated, the entire clock generation circuit <NUM>, including its oscillator, may be shut down. Accordingly, known clock generation circuits have two operational states: ON and OFF.

According to one or more examples described herein, a clock generation circuit <NUM> has three operational states or modes: ON, OFF, and STANDBY. During STANDBY mode, certain intermediate circuit nodes internal to the clock generation circuit <NUM> are charged to a target voltage with a small bias current, referred to herein as a pre-bias. The pre-bias current can be scaled to a minimal value, e.g., in the range of <NUM>% of the clock generation circuit ON mode bias current. Simulations reveal an improvement in startup time from STANDBY to ON modes of <NUM> usec, as opposed to the OFF to ON startup time of <NUM> usec. Although the clock generation circuit <NUM> consumes some current in STANDBY mode, the faster startup time allows the system <NUM> to disable the clock generation circuit <NUM> more often, as compared to conventional clock generation circuits, with their longer OFF to ON startup time.

<FIG> depicts an overall method <NUM> of delivering power to an electronic circuit <NUM>, such as a digital baseband system, in a portable electronic device. Initially, the PMU <NUM> is powered on (block <NUM>). The PMU <NUM> performs a start-up sequence, which includes powering ON a clock generation circuit <NUM>, and conditioning the clock generation circuit <NUM> output to generate one or more clock signals (block <NUM>). The clock signals may, for example, provide a switching signal for the SMPS <NUM> that deliver power to the other electronics <NUM> in the system <NUM>. After a relatively long startup duration (e.g., <NUM> usec), the clock generation circuit <NUM> is in an ON state (block <NUM>).

As long as at least one circuit <NUM>, <NUM>, <NUM>, <NUM> or module in the system <NUM> requests a clock signal (block <NUM>), the clock generation circuit <NUM> remains ON (block <NUM>). In the event that all relevant electronic circuits <NUM>, <NUM>, <NUM>, <NUM> are placed in a "sleep" mode to preserve power (block <NUM>), the method <NUM> checks whether the clock generation circuit <NUM> may be fully disabled (block <NUM>). This may comprise, for example, checking the state of one or more status bits in a status register or other predefined memory location. In use cases where a fast startup time is not critical, and maximum power savings are desired, the PMU <NUM> turns the clock generation circuit <NUM> OFF (block <NUM>). The clock generation circuit <NUM> remains OFF until a circuit <NUM>, <NUM>, <NUM>, <NUM> requests a clock signal (block <NUM>), when the clock generation circuit <NUM> is turned ON (block <NUM>) and power and clocks are supplied. This transition (block <NUM> to <NUM>) incurs a significant delay.

When it is again decided to place the system <NUM> in sleep mode (block <NUM>) but a fast startup time is required (e.g., to respond to activity on an external bus, to process an incoming wireless signal, or the like), the status information (block <NUM>) may indicate that the PMU <NUM> may place the clock generation circuit <NUM> in STANDBY mode (block <NUM>). In STANDBY mode, the clock generation circuit <NUM> does not generate an output; however, a voltage is maintained on internal nodes by a small pre-bias current. Because of the pre-bias current, when a circuit <NUM>, <NUM>, <NUM> again requests a clock signal (block <NUM>), the clock generation circuit <NUM> may exit STANDBY and be fully ON (block <NUM>) and operational in a very short startup time (e.g., <NUM> usec). The fast startup time enables greater use of STANDBY mode, reducing overall power consumption.

<FIG> depicts an example clock generation circuit <NUM> that is not covered by the appended claims. The clock generation circuit <NUM> includes an RC oscillator <NUM>, clock quality analyzer <NUM>, AND gate function <NUM>, and output driver <NUM>. As well known in the art, the op amp in the RC oscillator <NUM> will generate a periodic output signal, the frequency of which depends on the values of the capacitor C and resistor R, when a bias driver <NUM> powers up the oscillator <NUM> op amp, and provides a relatively large bias current. A clock quality analyzer circuit <NUM> monitors the oscillator <NUM> output, and will only output a "<NUM>" toward the AND function <NUM> when the clock signal meets predetermined quality specifications regarding voltage, frequency, jitter, ripple, duty cycle, and the like. The AND gate function <NUM> allows the RC oscillator <NUM> output to pass to the output buffer <NUM> only if the ClockRequest input is asserted, and the clock quality analyzer circuit <NUM> determines that the clock signal is within specification. In conventional clock generation circuits, the clock quality analyzer circuit <NUM> may suspend the clock signal for <NUM> usec or more, in transitioning from OFF to ON.

A StandBy input signal triggers a pre-bias driver <NUM> to provide a lower, pre-bias current to the amplifier in the RC oscillator <NUM> when the oscillator <NUM> is in STANDBY mode. The pre-bias current keeps the amplifier charged, but is insufficient to enable oscillation. When the ClockRequest signal is asserted, full bias is established and the RC oscillator <NUM> starts up, quickly settling to the proper output point, generating a high quality clock signal at the correct frequency. The clock quality analyzer circuit <NUM> verifies this, and rapidly enables the AND gate function <NUM> to pass the clock signal to the output buffer <NUM>.

<FIG> is a timing diagram depicting the operational state of the system <NUM> and the clock generation circuit <NUM>, as well as control signals StandBy and ClockRequest. Initially, the system <NUM> (including the clock generation circuit <NUM>) is OFF. Upon power-up, the system <NUM> is in a STARTUP state during which various circuits <NUM>, <NUM> power up and initialize. During this time, the clock generation circuit <NUM> transitions from OFF to ON states, as indicated by the relatively long hashed startup time. Generally, the clock generation circuit <NUM> startup time is not the critical system startup parameter, as other circuits (e.g., processors <NUM>, <NUM>) have much longer initialization/boot-up sequences.

Once all circuits initialize, the clock generation circuit <NUM> provides at least one clock signal to the SMPS <NUM>, which provides power to circuits <NUM>, <NUM>, <NUM>. The system <NUM> is in ACTIVE state. When operational conditions permit, for power conservation purposes the system <NUM> goes into SLEEP mode, and the clock generation circuit <NUM> is placed in STANDBY. This occurs because ClockRequest is deasserted, indicating no circuit <NUM>, <NUM>, <NUM>, <NUM> requires clock signals. However, the StandBy signal remains asserted. This causes a pre-bias current to be applied to the RC oscillator circuit <NUM> within the clock generation circuit <NUM>, almost fully charging the amplifier and maintaining the output node at near its operational voltage. When the system <NUM> exits SLEEP mode by again asserting ClockRequest, only a very short startup time is required to transition the clock generation circuit <NUM> from STANDBY to ON. This translates to a corresponding brief duration in which the system <NUM> transitions from SLEEP to ACTIVE mode.

<FIG> is a qualitative graph depicting the relationship between current consumption and startup time for each of the three operating modes of the clock generation circuit <NUM>. When the clock generation circuit <NUM> is ON, there is no problem with startup time; however, the current consumption is at a maximum. When the clock generation circuit <NUM> is OFF there is zero current consumption, but the startup time is long. The STANDBY mode provides a compromise. The power consumption is only <NUM>/<NUM> that during the fully ON state, and while the startup time is not zero, it is only <NUM>/<NUM> the time required to transition out of the OFF state. For use cases where tight startup time requirements preclude turning the clock generation circuit <NUM> fully OFF, the STANDBY mode provides an additional way to save <NUM>% of the power, while still satisfying startup time requirements.

The clock generation circuit <NUM> depicted in <FIG> is based on an RC oscillator <NUM>. A more complex, and more commonly deployed, form of clock generation circuit <NUM> employs a relaxation oscillator, depicted in block diagram form in <FIG>. A relaxation oscillator operates by repeatedly charging and discharging an integration capacitor via a feedback loop.

A bandgap reference circuit <NUM> generates a reference voltage Vref, and provides it to both a scaling/buffering circuit <NUM> and the current generation circuit <NUM>. The scaling and buffering circuit <NUM> scales and buffers the reference voltage Vref, outputting a steady threshold voltage Vth. The current generation with trimming circuit <NUM> generates a charging current Icharge, which charges an integration capacitor in an integration circuit <NUM>. As indicated by the dashed-line box, the current generation circuit <NUM> and integration circuit <NUM> are tightly coupled.

The integration circuit <NUM> outputs a saw-tooth integrated voltage Vint, which increases as the integration capacitor charges and returns to zero when the capacitor discharges. A comparison circuit <NUM> compares the integrated voltage Vint to the threshold voltage Vth, and generates a reset impulse when they are equal. The reset signal is fed back to the integration circuit <NUM>, as a trigger to discharge the integration capacitor. The integration capacitor then begins charging again to generate the next cycle. A shaping and buffering circuit <NUM> conditions the saw-tooth wave of the integrated voltage Vint, outputting a square clock signal Clock. The frequency of the Clock signal is determined by the threshold voltage Vth and the magnitude of the current Icharge, which directly controls the charging time of the integration capacitor.

<FIG> depicts a conventional implementation of the current generation circuit <NUM> and integration circuit <NUM>. A trim code applied to the chain of resistors sets the resistance in the current generating path <NUM> (i.e., through transistor M1, the gate of which is controlled by the amplifier <NUM>), thus controlling the current through this path. A current mirror comprising matched transistors M2 and M3 copies this current to a proportional charging current Icharge in the integration path <NUM>, where it charges the integration capacitor Cint. The integration circuit <NUM> outputs the integrated voltage Vint as the voltage across the capacitor Cint. The reset signal received in feedback from the comparison circuit <NUM> discharges the capacitor to begin the next charging iteration. When the ClockRequest = <NUM> to place the clock generation circuit <NUM> in OFF state, the gates of the current mirror are pulled high, shutting off both transistors and halting the charging current flow. When these circuits <NUM>, <NUM> are again turned ON, transients at the output of the amplifier <NUM> must settle before a stable charging current Icharge is reestablished, which is necessary for frequency-stable clock generation.

However, the current generation circuit <NUM> and integration circuit <NUM> are not the only sources of startup transients that cause a lengthy startup time in transitioning the clock generation circuit <NUM> from OFF to ON. <FIG> depicts transients in the threshold voltage Vth caused by the amplifier startup. Additionally, the charging current Icharge experiences transients. Furthermore, transients appear in the biasing of the comparator in the comparison circuit <NUM>. All of these transients must settle, and the relevant nodes reach a steady-state voltage, before a clock signal can be output.

As indicated in <FIG>, the StandBy signal is, according to the invention, distributed to the scaling and buffering circuit <NUM>, the current generation circuit <NUM>, the integration circuit <NUM>, and the comparison circuit <NUM>. When ClockRequest = <NUM> but StandBy = <NUM>, the clock generation circuit <NUM> enters a STANDBY mode, in which pre-bias currents are supplied to amplifiers in the clock generation circuit <NUM> to reduce startup transients, and hence startup time, when the clock generation circuit <NUM> is turned fully ON.

<FIG> depicts the current generation circuit <NUM> and integration circuit <NUM> in STANDBY mode according to the invention.

As with the prior art circuit of <FIG>, ClockRequest = <NUM> pulls the gates of the mirror current transistors M2, M3 high, turning M3 off and making Icharge = <NUM> in the integration circuit <NUM>. The amplifier <NUM> receives a low pre-bias current. Logic in the current generation circuit <NUM> replaces the trim resistors with a series of diode-connected transistors when ClockRequest = <NUM> AND StandBy = <NUM>. In this configuration, both the amplifier <NUM> and the transistor M1 are biased very close to their operating points. M1 can then return to full conduction very rapidly when ClockRequest = <NUM>, with low transients that quickly settle, yielding a very short startup time to a stable clock output.

<FIG> depicts the StandBy input providing a pre-bias current to the comparator amplifier in the scaling and buffering circuit <NUM> during STANDBY mode. This biases the amplifier to near its operational point. The values of resistors R1 and R2 are increased so that the amplifier with lower biasing can drive them. Higher resistor values are not problematic since the threshold voltage Vth is always constant and there is no need to settle fast. The amplifier bias is increased when the clock generation circuit <NUM> is turned ON so that the threshold voltage Vth is more stable, even when the comparator is switching.

<FIG> depicts the StandBy input providing a pre-bias current to the comparator amplifier in the comparison circuit <NUM> during STANDBY mode. This biases the amplifier to near its operational point. The amplifier bias is increased when the clock generation circuit <NUM> is turned ON so that the comparator can switch rapidly enough.

<FIG> depict transistor-level views of various implementations of the current generation circuit <NUM> and integration circuit <NUM> of the relaxation oscillator of a clock generation circuit <NUM>. For clarity, a single control signal "enable" and its inverse "disable" are shown controlling switches. The enable/disable signals result from the ClockRequest signal described above (and possibly other system logic).

<FIG> depicts a conventional circuit, in which the clock generation circuit <NUM> is OFF. <FIG> depicts the same circuit in the ON state. The current generation path <NUM> includes transistors M2, M1, and the variable (trim) resistors. An amplifier <NUM> drives the gate of M1. A bias current circuit <NUM> provides additional current Ibias to the amplifier <NUM>, in the ON state.

<FIG> depicts the clock generation circuit <NUM> in the OFF state. The transistor M1 is isolated, with no current flowing through the variable resistance R to generate current in the current generating path <NUM>. Thus, no charging current Icharge flows in the integration path <NUM> to charge a capacitor (not shown). The amplifier <NUM> is disabled, and its inverting input is grounded. The bias current circuit <NUM> is disabled.

<FIG> depicts the same circuits in the ON state. The transistor M1 is connected to both M2 and the resistors R, generating current in the path <NUM>, which is mirrored in the integration path <NUM> as Icharge. The amplifier <NUM> is enabled, its inverting input is connected to the source of M1, and a bias current Ibias is applied to the amplifier <NUM> by the bias circuit <NUM>. Because Ibias goes from zero to its full value when the oscillator <NUM> is switched ON, transients at the output of the amplifier <NUM> require several microseconds to stabilize.

<FIG> and <FIG> depict similar circuits, but in which a small bias current Ibias/<NUM> is continuously applied to the amplifier <NUM>. That is, <FIG> depicts the clock generation circuit <NUM> in STANDBY mode, and <FIG> shows it in the fully ON state.

In <FIG>, the amplifier <NUM> is enabled, and its inverting input is connected to the current generation path <NUM>, in which a small current flows through M1 and the chain of diodes. A small bias current Ibias/<NUM> is continuously applied to the amplifier <NUM> by the bias circuit <NUM>. This keeps the amplifier <NUM> biased very close to its operating point.

In <FIG>, the clock generation circuit <NUM> is switched ON, and the trim resistors R are switched into the current generating path <NUM>. Charging current Icharge is established in the integration path <NUM>. The amplifier <NUM> is fully enabled, and Ibias/<NUM> is continuously applied by the bias circuit <NUM>.

<FIG> is a graph of transients on Icharge and the bias current Ibias as the clock generation circuit <NUM> switches from OFF to ON. <FIG> depicts the same for transitioning the clock generation circuit <NUM> between STANDBY and ON modes. With constant bias (i.e., the STANDBY mode), the bias points of the amplifier <NUM> are almost constant all the time, and therefore the transients are much smaller. They also settle faster, allowing for a faster startup time. Additionally, the bias current can be much lower (e.g., in the range of <NUM>% of the full bias current).

<FIG> depict transistor-level views of other example implementations of the current generation circuit <NUM> and integration circuit <NUM> of a relaxation oscillator in a clock generation circuit <NUM>, wherein the integration circuit generates a integration capacitor charging voltage Vcharge rather than the reference current Icharge described above. <FIG> and <FIG> depict the case of switched biasing, where the clock generation circuit <NUM> is in OFF and ON states, respectively. <FIG> and <FIG> depict the same circuit with constant biasing, where the clock generation circuit <NUM> is in STANDBY and ON states, respectively.

In <FIG>, the current generating path <NUM> and amplifier <NUM> are disabled, and no current flows through the variable (trim) resistors. The bias current circuit <NUM> is also disabled. Vcharge = <NUM>, so the integration capacitor (not shown) does not charge/discharge to generate a Clock signal.

In <FIG>, the current generating path <NUM> and amplifier <NUM> are enabled, and current through the variable (trim) resistors generates a charging voltage Vcharge. The bias circuit <NUM> is enabled, providing a bias current Ibias to the amplifier <NUM>.

<FIG> depicts an example where a partial bias is applied to the amplifier <NUM>, when the clock generation circuit <NUM> is in STANDBY mode. No current flows through the variable (trim) resistors, so Vcharge = <NUM>. However, the amplifier <NUM> is enabled and the bias circuit <NUM> applies a partial bias current. Note that transistor <NUM> is disabled, limiting the bias current to only that required to bias the amplifier <NUM> to near its operating point.

<FIG> depicts the clock generation circuit <NUM> in fully ON state. Current flowing through the variable (trim) resistors generates a charging voltage Vcharge. The amplifier <NUM> is fully on, and the bias current circuit <NUM> provides both the standby bias current, and additionally enables transistor <NUM>, providing additional bias current. This additional bias current during operation helps the amplifier <NUM> deal with transient loads.

In all of the circuits according to the appended claims a clock generation circuit <NUM> transitions from a STANDBY mode, in which a small, pre-bias current is applied to amplifiers, to a fully ON state, with fewer transients, which quickly settle to a steady-state. Hence, the clock generation circuit <NUM> startup time is dramatically shorter than in prior art designs, which only transition the clock generation circuit <NUM> between OFF and ON states. The pre-bias current consumption in the STANDBY state is small, such as in the range of <NUM>% of the bias current applied in the ON state. The very fast startup time allows the clock generation circuit <NUM> to be placed in STANDBY more often than conventional circuits, thus reducing overall power consumption, despite the small pre-bias current consumption in the STANDBY state. For example, the clock generation circuit <NUM> may be placed in STANDBY mode when an external bus or wireless interface is dormant, but may become active at any time, requiring e.g., the capture of burst data transfers.

Claim 1:
A clock generation circuit (<NUM>) comprising:
a bias circuit (<NUM>);
an oscillator circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) operative to selectively generate a periodic signal, wherein the oscillator circuit is a relaxation oscillator circuit comprising:
an integration capacitor (Cint);
an amplifier (<NUM>) coupled to a first transistor (M1) to control a gate of the first transistor (M1) so as to control a current through a current generating circuit (<NUM>) of the relaxation oscillator circuit; and
a current mirror (M2, M3) configured to copy the current through the current generating circuit (<NUM>) to an integration circuit (<NUM>) of the relaxation oscillator to produce a charging current (Icharge) for charging the integration capacitor (Cint); and
an output circuit (<NUM>) operative to receive the periodic signal from the oscillator circuit and to output a clock signal;
and
wherein the clock generation circuit (<NUM>) is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication (ClockRequest, StandBy) provided for the clock generation circuit; wherein:
in the first full power mode, the oscillator circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) provides the periodic signal to the output circuit (<NUM>) and the output circuit (<NUM>) generates a clock signal;
in the second sleep mode, the oscillator circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) is disabled; and
in the third standby mode, the amplifier (<NUM>) is biased to a voltage close to its operating voltage but the oscillator circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) does not generate the periodic signal.