Patent Description:
This section is intended to provide a background or context to the invention disclosed below. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise explicitly indicated herein, what is described in this section is not prior art to the description in this application and is not admitted to e prior art by inclusion in this section. Abbreviations that may be found in the specification and/or the drawing figures are defined below, after the main part of the detailed description section.

There are many different error correction codes used in wireless communication. Such codes allow certain types of errors to be corrected during the decoding of received information.

Low Density Parity Check (LDPC) is a type of error correction code, which is already used in <NUM>. 11n, <NUM>. 16e, and many other standards. Recently, LDPC has received more attention as a promising coding scheme to fulfill next generation (i.e., <NUM>) mobile radio requirements.

In particular, LDPC has been selected as channel coding for eMBB in <NUM>. It would therefore be beneficial to improve LDPC.

The following disclosure is divided into sections for ease of reference.

The examples herein describe techniques for error correction. Additional description of these techniques is presented after a system into which the exampels may be used is described.

Turning to <FIG>, this figure shows a block diagram of one possible and non-limiting system in which the embodiments may be practiced. In <FIG>, a user equipment (UE) <NUM> is in wireless communication with a wireless network <NUM>. A UE is a wireless, typically mobile device that can access a wireless network. The UE <NUM> includes one or more processors <NUM>, one or more memories <NUM>, and one or more transceivers <NUM> interconnected through one or more buses <NUM>. The one or more buses <NUM> may be address, data, or control buses, and may include any interconnection mechanism, such as a series of lines on a motherboard or integrated circuit, fiber optics or other optical communication equipment, and the like. The UE <NUM> includes an error correction module <NUM>, comprising one of or both parts <NUM>-<NUM> and/or <NUM>-<NUM>, which may be implemented in a number of ways. The error correction module <NUM> may be implemented in hardware as error correction module <NUM>-<NUM>, such as being implemented as part of the one or more processors <NUM>. The error correction module <NUM>-<NUM> may be implemented also as an integrated circuit (illustrated by reference <NUM> and commonly called a "chip") or through other hardware such as a programmable gate array. In another example, the error correction module <NUM> may be implemented as error correction module <NUM>-<NUM>, which is implemented as computer program code <NUM> and is executed by the one or more processors <NUM>. For instance, the one or more memories <NUM> and the computer program code <NUM> may be configured to, with the one or more processors <NUM>, cause the user equipment <NUM> to perform one or more of the operations as described herein. The UE <NUM> communicates with eNB <NUM> via a wireless link <NUM>.

The eNB (evolved NodeB) <NUM> is a base station (e.g., for LTE, long term evolution) that provides access by wireless devices such as the UE <NUM> to the wireless network <NUM>. The eNB <NUM> includes one or more processors <NUM>, one or more memories <NUM>, one or more network interfaces (N/W I/F(s)) <NUM>, and one or more transceivers <NUM> interconnected through one or more buses <NUM>. The eNB <NUM> includes an error correction module <NUM>, comprising one of or both parts <NUM>-<NUM> and/or <NUM>-<NUM>, which may be implemented in a number of ways. The error correction module <NUM> may be implemented in hardware as error correction module <NUM>-<NUM>, such as being implemented as part of the one or more processors <NUM>. The error correction module <NUM>-<NUM> may be implemented also as an integrated circuit (illustrated by reference <NUM> and commonly called a "chip") or through other hardware such as a programmable gate array. In another example, the error correction module <NUM> may be implemented as error correction module <NUM>-<NUM>, which is implemented as computer program code <NUM> and is executed by the one or more processors <NUM>. For instance, the one or more memories <NUM> and the computer program code <NUM> are configured to, with the one or more processors <NUM>, cause the eNB <NUM> to perform one or more of the operations as described herein. Two or more eNBs <NUM> communicate using, e.g., link <NUM>. The link <NUM> may be wired or wireless or both and may implement, e.g., an X2 interface.

The one or more buses <NUM> may be address, data, or control buses, and may include any interconnection mechanism, such as a series of lines on a motherboard or integrated circuit, fiber optics or other optical communication equipment, wireless channels, and the like. For example, the one or more transceivers <NUM> may be implemented as a remote radio head (RRH) <NUM>, with the other elements of the eNB <NUM> being physically in a different location from the RRH, and the one or more buses <NUM> could be implemented in part as fiber optic cable to connect the other elements of the eNB <NUM> to the RRH <NUM>.

The wireless network <NUM> may include a network control element (NCE) <NUM> that may include MME (Mobility Management Entity)/SGW (Serving Gateway) functionality, and which provides connectivity with a further network, such as a telephone network and/or a data communications network (e.g., the Internet). The eNB <NUM> is coupled via a link <NUM> to the NCE <NUM>. The link <NUM> may be implemented as, e.g., an S1 interface. The NCE <NUM> includes one or more processors <NUM>, one or more memories <NUM>, and one or more network interfaces (N/W I/F(s)) <NUM>, interconnected through one or more buses <NUM>. The one or more memories <NUM> and the computer program code <NUM> are configured to, with the one or more processors <NUM>, cause the NCE <NUM> to perform one or more operations.

The computer readable memories <NUM>, <NUM>, and <NUM> may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory. The computer readable memories <NUM>, <NUM>, and <NUM> may be means for performing storage functions. The processors <NUM>, <NUM>, and <NUM> may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on a multi-core processor architecture, as non-limiting examples. The processors <NUM>, <NUM>, and <NUM> may be means for performing functions, such as controlling the UE <NUM>, eNB <NUM>, and other functions as described herein.

Having thus introduced one suitable but non-limiting technical context for the practice of the examples of this invention, the examples will now be described with greater specificity.

As previously described, LDPC has been selected as channel coding for eMBB in <NUM>. This occurred in part in a 3GPP RAN1 #<NUM> meeting. For the UL eMBB data channels, the working assumption was to adopt flexible LDPC as the single channel coding scheme for small block sizes (to be confirmed unless significant issues are identified). It was previously already agreed upon to adopt LDPC for large block sizes. In this meeting, for the DL eMBB data channels, it was agreed to adopt flexible LDPC as the single channel coding scheme for all block sizes.

Further, it is also agreed that IR HARQ should be supported for LDPC in <NUM>, as agreement was reached for this in the 3GPP RANI #<NUM> meeting. Additional agreement was reached for channel coding technique(s) designed for data channels of NR support both Incremental Redundancy (IR) (or similar) and Chase Combining (CC) HARQ.

Moreover, agreement was reached in the 3GPP RANI #<NUM> meeting that code extension of a parity-check matrix is used for IR HARQ/rate-matching support, and lower-triangular extension, which includes diagonal-extension as a special case, would be used.

Thus, LDPC is gaining acceptance and prominence for <NUM>. The instant inventions are directed toward improving the LDPC and the use of LDPC.

As an introduction, details of LDPC are more often discussed in association with the parity check matrix (PCM), which is used for encoding and decoding. Among different variants of LDPC, quasi-cyclic (QC) LDPC is considered as the most practical way of using LDPC codes in realistic situations. In QC-LDPC, the PCM can be generated by expanding a base matrix based on the expansion factor Z, where the base matrix can be defined as the following: <MAT> where Pi,j equals -<NUM> or a non-negative value, i=<NUM>,<NUM>,. M, and j=<NUM>,<NUM>,.

When generating the PCM, the following is performed:.

Considering a corresponding Tanner graph of the PCM, constructions should satisfy some PCM criteria, e.g., avoid length four circles or keep a low ratio of length four circles or keep a good girth profile with low ratio of small (e.g., four, six) circles in the Tanner graph. Otherwise, the performance of the LDPC coding scheme has been found to be not that good. For example, the PEG method can be used to generate the PCM that guarantees the aforementioned requirements. As is known, the girth g of the code is the length of the shortest circle in its Tanner graph. The girth profile is the profile of the length of the circle in its Tanner graph.

For LDPC, message passing is used in decoding, where there is message passing from a variable node to a check node and from the check node to the variable node. The Min-Sum decoding scheme is one practical scheme with less complexity, which is selected as an effective implementable decoding scheme. In Min-Sum decoding, comparison and selection are used for message selection and passing.

Layered decoding is one important decoding scheme with high implementation efficiency, e.g. smaller chip area (e.g., for integrated circuit <NUM> or <NUM> or both) and smaller number of iterations as compared with the flooding decoding. In layered decoding, several rows are row orthogonal (that is, there is at most one element not indicative of an all-zero matrix per column of multiple rows or equivalently at most one identity matrix cyclic shift value per column of multiple rows) and are column-wise combined into one row as one layer in decoding.

Turning to <FIG>, this figure illustrates both row orthogonality in part of an LDPC base matrix (illustrated by reference <NUM>) and message passing in single layer decoding processing (illustrated by reference <NUM>). As illustrated by reference <NUM>, rows R, R+<NUM>, and R+<NUM> are rows of (or a subset of columns of rows of) an LDPC base matrix and are combined into one row <NUM>. The row <NUM> is comprised of values from left to right as follows: value <NUM>-<NUM> from row R; value <NUM>-<NUM> from row R+<NUM>; value <NUM>-<NUM> from row R+<NUM>; value <NUM>-<NUM> from row R+<NUM>; value <NUM>-<NUM> from row R; value <NUM>-<NUM> from row R+<NUM>;. ; value <NUM>-(N-<NUM>) from row R+<NUM>; value <NUM>-(N-<NUM>) from row R; and value <NUM>-N from row R+<NUM>. In the message passing in single layer decoding processing <NUM>, the single layer processing <NUM> comprises a number of comparison and selection processes <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> performed as follows: process <NUM>-<NUM> uses the values <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-(N-<NUM>) from row <NUM>; process <NUM>-<NUM> uses the values <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-N from row <NUM>; and process <NUM>-<NUM> uses the values <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-(N-<NUM>) from row <NUM>. The single layer processing <NUM> performs operations equivalent to the message passing between the variable and check nodes. Each of these processes <NUM> outputs their respective output values in the same order. The output is row <NUM>, comprising values <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-(N-<NUM>), <NUM>-(N-<NUM>), and <NUM>-N.

Although such single layer decoding processing is valuable (and may be used herein), in <NUM> and especially for eMBB, the block size could be very large considering the requirement of Gbps throughput. A general case could be that there are hundreds of code blocks in one transmission and each block contains as many as <NUM>~<NUM> information bits. Based on the requirement of this general case from <NUM>, to achieve high throughput, multiple parallel LDPC decoders should be implemented in one terminal, e.g., a UE, and the number of decoders in an eNB might be several times the number of decoders implemented in a single UE. Meanwhile, in each decoder, there should be implementations of multiple layers, and all these layers should be optimized separately to guarantee high decoding speed and low energy consumption. This is a significant challenge.

In the general design of an LDPC base matrix, the Pi,j are not related to each other, so for each layer, there should be different switching networks to pass the messages from each block based on the independent Pi,j. This switching network is one main component in min-sum decoder for LDPC and will occupy a large ratio of chip area (such as in semiconductors <NUM> or <NUM> or both) in each parallel decoder. It is a problem as how to reduce the complexity and chip area of the switching network.

The examples herein improve the current LDPC base matrix and PCM generation and use. In particular, the LDPC base matrix is adapted such that it comprises a plurality of typically non-identical, row-orthogonal parts, each part having a column-wise combination of rows that may be derived from a single vector common for the parts by, for each part, at most replacement of less than all of the vector values by values indicative of an all-zero matrix (typically denoted as -<NUM>) and one of cyclic shifting or interleaving of the resultant rows in a part and modification of the rows with zero or more elements consisting of values indicative only of the all-zero matrix. Such parts may be generated by a variety of techniques. In particular, in an exemplary aspect, the following techniques may be used:.

Now that an overview has been provided, additional detail is provided.

In particular, the following provides examples for implementing features of the claimed invention, where the claimed invention of the independent claim comprises a method for encoding or decoding data, the method comprising: storing, by a user equipment, UE (<NUM>), a plurality of starting vectors; receiving (<NUM>, <NUM>, <NUM>, <NUM>), from a base station (<NUM>) for generation of a base matrix (<NUM>, <NUM>) comprised of multiple parts, each part comprising a plurality of columns and rows and at least two of the multiple parts comprising orthogonal rows, a first starting vector (<NUM>) of the plurality of starting vectors or a vector index to the first starting vector of the plurality of starting vectors, and in addition one or more of the following signalling parameters: a row-indication vector or an index to a set of row-indication vectors to be used for generating said plurality of rows for at least one of the at least two parts comprising orthogonal rows, wherein the row-indication vector comprises a row-indication for each element of the first starting vector; a cyclic shift to be used for generating said plurality of rows for at least one of said at least two parts comprising orthogonal rows; and/or an interleaving vector or an index to a set of interleaving vectors to be applied for generating said plurality of rows for at least one of said at least two parts comprising orthogonal rows; generating.

(<NUM>), by the UE, the base matrix using the first starting vector and at least one of said additionally received signalling parameters, wherein the base matrix (<NUM>, <NUM>) is comprised of integers, wherein each integer is representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix, wherein said at least two parts (<NUM>, <NUM>) comprising orthogonal rows are configured such that their respective column-wise combinations of rows represents the first starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the first starting vector substituted by integers indicative of the all-zero matrix, wherein said at least two parts comprising orthogonal rows (<NUM>, <NUM>) are not identical; applying the base matrix (<NUM>, <NUM>) to a quasi-cyclic low density parity check, LDPC, coder; and using the applied base matrix (<NUM>, <NUM>) for one of encoding data (<NUM>) using the LDPC coder or decoding data (<NUM>) using the LDPC coder.

The base matrix and PCM are used for encoding and decoding, and overall flows describing encoding and decoding are described below. Before that, though, base matrix and PCM considerations are described.

The base matrix can be one base matrix for some code rate or a rate-compatible base matrix that supports IR HARQ or supports multiple code rates based on different parts of the base matrix. For rate-compatible base matrix, we consider the method of extension from a base matrix supporting a high code rate to a final extended base matrix supporting a low code rate. Two methods are described in detail below.

A first method is described in reference to <FIG> is a logic flow diagram for matrix generation with row reusing and shifting for LDPC. This figure further illustrates the operation of a method, a result of execution of computer program instructions embodied on a computer readable memory, functions performed by logic implemented in hardware, and/or interconnected means for performing functions in accordance with exemplary embodiments.

In this method, one (starting) vector is distributed into a set of multiple rows (see block <NUM>), with row orthogonality, where the starting vector includes multiple non-negative values. Block <NUM> involves performing a cyclic shift of the set of multiple rows to generate one part of the base matrix. In block <NUM>, the same starting vector is reused and the starting vector is distributed into another set of multiple rows, with row orthogonality. A cyclic shift is performed in block <NUM> of the other set of multiple rows to generate another part of the base matrix. It is noted the examples described herein use different cyclic shifts for blocks <NUM> and <NUM>, but the same number of shifts may be performed for blocks <NUM> and <NUM>. Furthermore, while cyclic shifting is described in reference blocks <NUM> and <NUM> (corresponding to <FIG> and <FIG>, respectively) interleaving may be performed instead (e.g., see <FIG>).

Certain operations in these blocks are illustrated in <FIG>. <FIG> illustrates two distributions of sets of multiple rows in accordance with operations in <FIG>, <FIG> illustrates a cyclic shift for one set of multiple rows from <FIG>, and <FIG> illustrates a cyclic shift for another set of multiple rows from <FIG>. Furthermore, <FIG> illustrates use of the two generated sets of rows as parts of an extension part of one rate-compatible base matrix.

In the following example shown in <FIG>, one starting vector is distributed into three orthogonal rows and cyclic shifted to generate one part of base matrix, and the same starting vector is distributed into another three orthogonal rows and cyclic shifted to generate another part of the base matrix. <FIG> illustrates a starting vector <NUM> comprising values P1 through P12. This starting vector <NUM> is distributed (reference <NUM>) to a set <NUM> of rows <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> in this example. The same starting vector <NUM> is distributed (reference <NUM>) to another set <NUM> of rows <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. Each of the values P1 through P12 represents a shift value for an identity matrix (generally indicated by a non-negative integer value) and the "blank" values represent all-zero matrices (generally indicated with -<NUM>). The number of rows is merely illustrative, as is the number of values for individual rows.

<FIG> illustrates a cyclic shift <NUM>, where the last two values in rows <NUM> for the set <NUM> are shifted to the beginning of the rows to create the set <NUM> of rows, with rows <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> after the cyclic shift. <FIG> illustrates a cyclic shift <NUM>, where the last six values in rows <NUM> for the set <NUM> are shifted to the beginning of the rows to create the set <NUM> of rows, with rows <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> after the cyclic shift.

The generated two parts <NUM>, <NUM> are used as an extension part of one rate-compatible base matrix, where the extension is from a base matrix supporting a high code rate. This is illustrated by <FIG>, where an extension operation <NUM> is performed on a base matrix <NUM> to form a rate-compatible base matrix <NUM> with an extension <NUM> comprising the sets <NUM>, <NUM> of rows. In general, the area <NUM> should contain nothing but elements indicating all-zero matrices next to the grey part <NUM>, but should not have all only elements indicating all-zero matrices next to the added parts <NUM>, <NUM>. In this example, the width of <NUM> and <NUM> are same as the width of <NUM>. It should be noted that the width of <NUM> and <NUM> could be less than the width of <NUM> in other cases. In some cases, parts <NUM> and <NUM> may consist of a subset of the number of columns of <NUM> where remaining columns may be comprised of elements indicating all-zero matrices.

A second method is described in reference to <FIG>. In block <NUM>, one (starting) vector is copied to multiple rows and the multiple rows are sparsed to structure the sparsed set of rows as row orthogonal, where the starting vector includes multiple non-negative values. Sparsing means each of the values P1 through P12 is indicative of a shift value of an identity matrix (generally indicated by a non-negative integer) and the "blank" values are indicative of all-zero matrices (general indicated by -<NUM>), and the "blank" values are placed in locations where the values P1 through P12 are not placed. In other words, it is determined how to make a resultant sparsed set of rows such that each set of rows only contain one value of P1 through P12 in its original column position in one of the rows, and the other values for other rows for that column position contain indications of all-zero matrices.

In block <NUM>, the set of sparsed rows is cyclic shifted to generate one part of the base matrix. In block <NUM>, the starting vector is copied to another set of multiple rows and the set of multiple rows are sparsed as described above to structure the other set of sparsed rows as row orthogonal. Note that the number of rows in the set of multiple rows may be different between blocks <NUM> and <NUM>, see, e.g., <FIG> and <FIG>. In block <NUM>, the other set of sparsed rows is cyclic shifted to generate another part of the base matrix. While cyclic shifting is described in reference blocks <NUM> and <NUM> (corresponding to <FIG> and <FIG>, respectively) interleaving may be performed instead (e.g., see <FIG>).

Certain operations in these blocks are illustrated in <FIG>. <FIG> illustrates copying a starting vector into multiple rows and performing multiple sparsing operations in accordance with operations in <FIG>, <FIG> illustrates a cyclic shift for one set of multiple rows from <FIG>, and <FIG> illustrates a cyclic shift for another set of multiple rows from <FIG>. Additionally, <FIG> illustrates use of the two generated sets of rows as parts of an extension part of one rate-compatible base matrix.

In the following example shown in <FIG>, one starting row is copied into multiple rows and those rows are sparsed to create two sets of orthogonal rows, and those sets are cyclic shifted to generate parts of a base matrix. <FIG> illustrates a starting row <NUM> comprising values P1 through P12. This starting row <NUM> is copied (reference <NUM>) to a set <NUM> of copies <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> in this example. The set <NUM> of copies <NUM> is sparsed (reference <NUM>) to a set <NUM> of rows <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. The set <NUM> of copies <NUM> is sparsed (reference <NUM>) to another set <NUM> of rows <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. Each of the values P1 through P12 is non-negative and the "blank" values are indicative of all-zero matrices. The sparsing therefore creates a set <NUM> of sparsed rows <NUM> where in each column position only at most one of the elements P1 through P12 is positioned and the other values in the rows <NUM> are indicative of all-zero matrices. Similarly, sparsing creates a set <NUM> of sparsed rows <NUM> where in each column position only one of the elements P1 through P12 is positioned and the other values in the rows <NUM> are indicative of all-zero matrices. The number of rows is merely illustrative, as is the number of values for individual rows.

In this example, the generated two parts <NUM>, <NUM> are used as an extension part of one rate-compatible base matrix, where the extension is from a base matrix supporting a high code rate. This is illustrated by <FIG>, where an extension operation <NUM> is performed on a base matrix <NUM> to form a rate-compatible base matrix <NUM> with an extension <NUM> comprising the sets <NUM>, <NUM> of rows. See also <FIG> and its corresponding text.

Another example is depicted in <FIG>. A layer decoder (<NUM>, <NUM>) is configured in accordance with two sets <NUM> and <NUM> of multiple rows. More particularly, the layer decoder is configured with a switching fabric representative of the vector <NUM> of cyclic shift values [<NUM><NUM><NUM><NUM><NUM><NUM>]. The two sets <NUM>, <NUM> of multiple rows are configured such that they are row-orthogonal and their corresponding column-wise combination (<NUM>, <NUM>) is a sparsed and cyclic shifted representation of the same [<NUM><NUM><NUM><NUM><NUM><NUM>] vector <NUM>. That is, column-wise combination <NUM> is observed to correspond to [<NUM><NUM><NUM><NUM><NUM><NUM>] by a cyclic shift of three columns and replacement of element two (<NUM>) with an indication of an all-zero matrix, shown here as blank. In block <NUM>, a sparsing of an entire column of the row-orthogonal set <NUM> is performed corresponding to element (<NUM>) of the original vector <NUM>, and this sparsing is indicated in the column-wise combination <NUM> by the indication of an all-zero matrix. And column-wise combination <NUM> may be observed to be corresponding to [<NUM><NUM><NUM><NUM><NUM><NUM>] by cyclic shift of two and replacement of element one (<NUM>) with an indication of an all-zero matrix, shown here as blank. In block <NUM>, a sparsing of an entire column of the row-orthogonal set <NUM> is performed corresponding to element (<NUM>) of the original vector <NUM>, and this sparsing is indicated in the column-wise combination <NUM> by the indication of an all-zero matrix.

When processing data in accordance with the first set <NUM>, the layer decoder <NUM> is configured by disablement of part of the switching fabric <NUM> corresponding to element two (<NUM>) and cyclic shifting of the input by three. When processing data in accordance with the second set <NUM>, the layer decoder <NUM> is configured by disablement of the switching fabric part corresponding to element one (<NUM>) and cyclic shifting of the input by two. Disablement of a portion of the switching fabric <NUM> may for example be achieved by simple disablement of certain gates on the die at the ingress to the switching fabric, by preventing storage of the output of the portion of the switching fabric or by skipping reading the output of the portion of the switching fabric into a different memory. The input may be shifted by actual shifting of the data in the input memory or more conveniently by memory readdressing. Both cyclic shifting and disabling require minimal amounts of additional logic. Because of this, layer decoders <NUM> and <NUM> may conveniently be the same layer decoder (unlike a conventional system, where two layer decoders would be necessary) configured in two different ways. This is illustrated by a layer decoder <NUM> and its switching fabric <NUM> being configured (see block <NUM>) to perform proper shifting and sparsing of column to create layer decoders <NUM>, <NUM>. In an example, the error correction module <NUM>/<NUM> performs the configuring in the block <NUM>, and the layer decoder <NUM> and its switching fabric <NUM> could be implemented as part of the error correction module <NUM>/<NUM>, or be implemented as part of a transmitter <NUM>/<NUM> (e.g., as an encoder) or as part of a receiver <NUM>/<NUM> (e.g., as a decoder), separate from the error correction module <NUM>/<NUM>. Other configurations are possible.

For example, a single coder <NUM> (e.g., a decoder or encoder) could be configured (block <NUM>) to perform the copying in blocks <NUM>/<NUM> (or distributing in blocks <NUM>/<NUM>), the sparsing of the rows and individual columns (as in references <NUM> and <NUM>), and the cyclic shifts for blocks <NUM>/<NUM>, and further to create and implement the layer decoders <NUM>/<NUM> (as previously described). The single coder <NUM> could be implemented as part of the error correction module <NUM>/<NUM>, or be implemented as part of a transmitter <NUM>/<NUM> (e.g., as an encoder) or as part of a receiver <NUM>/<NUM> (e.g., as a decoder), e.g., separate from the error correction module <NUM>/<NUM>. The error correction module <NUM>/<NUM> may perform the operations in block <NUM>, where the coder <NUM> is configured with vector <NUM>, an indication to copy (or distribute), sparsing information (e.g., for rows and/or columns), and cyclic shift information (and any other suitable information) to cause LDPC decoding (or encoding).

In the example depicted in <FIG>, the two sets of multiple rows are derived in accordance with the process depicted in <FIG> from the vector <NUM> (starting row) [<NUM><NUM><NUM><NUM><NUM><NUM>] through copying and sparsing (<NUM>) the vector into <NUM> followed by cyclic shifting (<NUM>) and through copying and sparsing (<NUM>) the vector into <NUM> followed by cyclic shifting (<NUM>). In another example, the two sets <NUM> and <NUM> may be derived similarly with the process depicted in <FIG>. The order of sparsing and cyclic shifting may naturally be reversed. As may be observed, sets <NUM> and <NUM> are depicted to have a different number of rows. There are generally no requirements that sets of multiple rows have the same number of rows.

<FIG> depicts another example. This example differs from that of <FIG> mainly in that instead of cyclic shifting, the column-wise combinations <NUM>, <NUM> of the two sets of multiple rows <NUM> and <NUM> correspond to the vector [<NUM><NUM><NUM><NUM><NUM><NUM>] by interleaving (for blocks <NUM> and <NUM>) and sparsing, rather than cyclic shifting and sparsing. Correspondingly, the input of the layer decoder (<NUM>, <NUM>) must be interleaved. Entire columns are sparsed in blocks <NUM> and <NUM>. As with <FIG>, in <FIG>, a layer decoder <NUM> and switching fabric <NUM> may be configured (block <NUM>) to perform proper shifting and sparsing of column(s) to create layer decoders <NUM>, <NUM>. Furthermore, it is possible that a single coder <NUM> (e.g., a decoder or encoder) could be configured (block <NUM>) to perform the copying in blocks <NUM>/<NUM> (or distributing in blocks <NUM>/<NUM>), the sparsing of the rows and individual columns (as in references <NUM>/<NUM> and <NUM>/<NUM>), and the interleaving for blocks <NUM>/<NUM>. The single coder <NUM> could be implemented as part of the error correction module <NUM>/<NUM>, or be implemented as part of a transmitter <NUM>/<NUM> (e.g., as an encoder) or as part of a receiver <NUM>/<NUM> (e.g., as a decoder). The error correction module <NUM>/<NUM> may perform the operations in block <NUM>, where the coder <NUM> is configured with vector <NUM>, an indication to copy (or distribute), sparsing information (e.g., for rows and/or columns), and cyclic shift information (and any other suitable information) to cause LDPC decoding (or encoding).

It should be understood that also examples are envisioned where one or more sets of multiple rows are corresponding to interleaving and one or more other sets of multiple rows are corresponding to cyclic shifting. A layer decoder capable of handling these sets will for such embodiments have an input interleaving capability, which for sets corresponding to cyclic shifting will have its input interleaving set to reflect the cyclic shift.

<FIG> depicts another example, which is similar to that depicted in <FIG> with the distinction that instead of block <NUM>, the set of multiple rows <NUM> is expanded at <NUM> by inserting an additional column consisting of only values indicative of the all-zero matrix. The layer decoder <NUM> may be correspondingly configured to skip (reference <NUM>) input data corresponding to the inserted column.

There are at least two implementation methods, as follows.

In a first implementation, one or more of the techniques presented above are used to generate the base matrix used in <NUM>, e.g., eMBB. The base matrix of the PCM is pre-generated according to one or more of the techniques above and stored in a UE <NUM>, and the UE <NUM> use the base matrix (and/or PCM) for decoding.

In a second implementation, the UE <NUM> generates a base matrix (and/or PCM) according to one or more of the techniques presented above, and the UE <NUM> uses the base matrix (and/or PCM) for decoding.

The implementations mentioned above are based on a predefined base matrix. The use of a predefined base matrix is not claimed. Instead the claimed invention generates a matrix based on signaling between a UE and a base station. For example, there are other ways to make the eNB and UE use the same base matrix, as the signaling between eNB and UE (most probably will be eNB configure to UE), where the signaling can include one or some combination of the following:.

Furthermore, it is also possible to predefine some parameter and transmit some parameter based on signaling between eNB and UE. For example, as claimed, a UE stores a plurality of vectors (starting rows), where the eNB signals from which vector the UE should generate the sets of multiple rows. Because memory storage space for a vector (starting row) is significantly smaller than that of corresponding sets of multiple rows and many sets of multiple rows may be generated from the same vector by different sparsing and cyclic shifting or interleaving, combinations of significantly reduced storage space and more flexible base matrix selection can be achieved.

<FIG> depicts a few possible examples of such parameter signaling. In all of these examples, an eNB <NUM> transmits (<NUM>) substantially an entire vector to a UE <NUM> or an index to a vector of one or more vectors stored in the UE, which the UE receives and uses to generate (<NUM>) sets of multiple rows of a PCM. The UE may subsequently use the generated PCM to transmit (<NUM>) encoded data and/or to decode (<NUM>) encoded data received from the eNB. Correspondingly, the eNB may use the vector to generate the same PCM to transmit (<NUM>) encoded data and/or to decode (<NUM>) encoded data received from the eNB.

In an example, the eNB may in addition to <NUM> and <NUM> transmit (<NUM>) a cyclic shift value for generating (<NUM>) at the UE at least one set of multiple rows of the PCM.

In another example, the eNB may in addition to <NUM>, <NUM> and in addition or instead of <NUM>, <NUM> transmit (<NUM>) an interleaving indication for generating (<NUM>) at the UE the sets of multiple rows of the PCM, wherein the interleaving indication is indicative of an interleaving vector of at least one set of multiple rows of the PCM. The interleaving indication takes the form of an index into a set of possible interleaving vectors or take the form of an interleaving vector.

In another example, the eNB may in addition to <NUM>, <NUM> and in addition or instead of <NUM>, <NUM> and/or <NUM>, <NUM> transmit (<NUM>) an row-indication vector indication for generating (<NUM>) at the UE the sets of multiple rows, wherein the row-indication vector indication is indicative of at least one row-indication vector of at least one set of multiple rows of the PCM. The row-indication vector indication takes the form of an index into a set of row-indication vectors, or take the form of a row-indication vector.

As such, a UE may for example receive a vector index, a cyclic shift value for one set of multiple rows, an index of interleaving vector for another set of multiple rows and an index of a row-indication vector for each of the one and another set of multiple rows and generate the sets of rows of the PCM in accordance with the received indexes and the cyclic shift value before using the generated PCM for transmitting (<NUM>) or decoding data (<NUM>).

When the base matrix is generated by one of the techniques described above, or by any method derivative therefrom, at least such that such that it comprises a plurality of, typically non-identical, row-orthogonal parts, each having a column-wise combination that may be derived from a same row for the parts by, for each part, at most replacement of less than all of the same row values by values indicative of an all-zero matrix (typically denoted as -<NUM>) and expansion of the vector with zero or more elements consisting of values indicative only of the all-zero matrix and one of cyclic shifting or interleaving of the resultant vector, then layered decoding can be shared by multiple layers generated by the same row (as one example of a technical effect). In detail, when two layers are generated by a same row or at least have a column-wise combination corresponding to the same row, then one set of cyclic shift processor and layer decoder can be used for any of the two layers. We only need to set the exact cyclic shift value, such that the layer can be decoded. So the set of cyclic shift processor and layer decoder can be shared by the layers generated by the same row. The same applies if interleaving rather than cyclic shifting is applied. Only one switching network is needed and shared for all layers corresponding to the same row, so the chip area (as an example) can be reduced.

Also, based on the techniques presented above, the effort of base matrix design and the standard effort will be reduced.

Furthermore, as described above, there is also an improvement in data storage. For instance, it is possible to store only the original vector and thereby save on data storage. Conventional storage is the straightforward storage of the parts (see parts <NUM> and <NUM> of the figures) in the base matrix. Basically, the possible number of cyclic shifts of the identity matrix is Z, so one needs ceil (log<NUM>(Z+<NUM>)) bits (where "ceil" is a well-known ceiling function) to store each element of the base matrix, since one needs one additional value to indicate -<NUM>. If Z=<NUM>, one hence needs <NUM> bits per entry of the base matrix. For two parts each of size 4x12, one would end up storing <NUM> bits. By comparison, the disclosed methods might require <NUM> or <NUM> bits, depending on whether cyclic shifting is used or the more flexible interleaving approach is used. These numbers are merely illustrative, but do indicate a storage savings. Thus, generating a base matrix on the bases of a stored original vector rather than storing the base matrix itself allows for significant storage space saving.

The above description uses the terms "user equipment" and "base station" (or eNB). These terms are used solely for ease of description. The user equipment may be any wireless mobile device and the base station may be any wireless network access node allowing the wireless mobile device to access a wireless network. For instance, the terminology used in local area networks (LANs) (such as WI-FI, a technology that allows electronic devices to connect to a wireless LAN) is typically that a base station is referred to as an access point and the wireless mobile devices have many different names.

One skilled in the art will understand that while the examples depicted in this disclosure use very small sets of multiple rows to facilitate easily understood drawings, sets of multiple rows of a base matrix in accordance with embodiments of the invention in practical systems will reflect a substantial portion, while not necessarily all, of the base matrix.

Embodiments herein may be implemented in software (executed by one or more processors), hardware (e.g., an application specific integrated circuit), or a combination of software and hardware. In an example embodiment, the software (e.g., application logic, an instruction set) is maintained on any one of various conventional computer-readable media. In the context of this document, a "computer-readable medium" may be any media or means that can contain, store, communicate, propagate or transport the instructions for use by or in connection with an instruction execution system, apparatus, or device, such as a computer, with one example of a computer described and depicted, e.g., in <FIG>. A computer-readable medium may comprise a computer-readable storage medium (e.g., memories <NUM>, <NUM>, <NUM> or other device) that may be any media or means that can contain, store, and/or transport the instructions for use by or in connection with an instruction execution system, apparatus, or device, such as a computer. A computer-readable storage medium does not comprise propagating signals.

Although various aspects are set out above, other aspects comprise other combinations of features from the described embodiments, and not solely the combinations described above.

It is also noted herein that while the above describes example embodiments of the invention, these descriptions should not be viewed in a limiting sense. Rather, there are several variations and modifications which may be made without departing from the scope of the present invention as defined in the appended claims.

Claim 1:
A method for encoding or decoding data, the method comprising:
storing, by a user equipment, UE (<NUM>), a plurality of starting vectors;
receiving (<NUM>, <NUM>, <NUM>, <NUM>), from a base station (<NUM>) for generation of a base matrix (<NUM>, <NUM>) comprised of multiple parts, each part comprising a plurality of columns and rows and at least two of the multiple parts comprising orthogonal rows, a first starting vector (<NUM>) of the plurality of starting vectors or a vector index to the first starting vector of the plurality of starting vectors, and in addition one or more of the following signalling parameters:
a row-indication vector or an index to a set of row-indication vectors to be used for generating said plurality of rows for at least one of the at least two parts comprising orthogonal rows, wherein the row-indication vector comprises a row-indication for each element of the first starting vector;
a cyclic shift to be used for generating said plurality of rows for at least one of said at least two parts comprising orthogonal rows; and/or
an interleaving vector or an index to a set of interleaving vectors to be applied for generating said plurality of rows for at least one of said at least two parts comprising orthogonal rows;
generating (<NUM>), by the UE, the base matrix using the first starting vector and at least one of said additionally received signalling parameters, wherein the base matrix (<NUM>, <NUM>) is comprised of integers, wherein each integer is representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix, wherein said at least two parts (<NUM>, <NUM>) comprising orthogonal rows are configured such that their respective column-wise combinations of rows represents the first starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the first starting vector substituted by integers indicative of the all-zero matrix, wherein said at least two parts comprising orthogonal rows (<NUM>, <NUM>) are not identical;
applying the base matrix (<NUM>, <NUM>) to a quasi-cyclic low density parity check, LDPC, coder; and
using the applied base matrix (<NUM>, <NUM>) for one of encoding data (<NUM>) using the LDPC coder or decoding data (<NUM>) using the LDPC coder.