Patent Description:
The present disclosure relates to a thin-film transistor, a display device including the same, and a method of manufacturing the same. More particularly, the present disclosure relates to a thin-film transistor including a silicon semiconductor layer disposed between each of oxide semiconductor layers, a display device including the same, and a method of manufacturing the same.

A thin-film transistor may be manufactured on a glass substrate or a plastic substrate, and the thin-film transistor is widely used as a switching device or a driving device in a display device, such as a liquid crystal display device or an organic light-emitting device. According to a material used for an active layer, the thin-film transistor may be categorized into an amorphous silicon thin-film transistor having an active layer of amorphous silicon, a polycrystalline silicon thin-film transistor having an active layer of polycrystalline silicon, and an oxide semiconductor thin-film transistor having an active layer of oxide semiconductor.

The amorphous silicon is deposited in a short time, and is formed as an active layer, whereby the amorphous silicon thin-film transistor (a-Si TFT) has advantages of short manufacturing time and low manufacturing cost. Meanwhile, it has disadvantages of inferior current driving efficiency due to low mobility, and a change of a threshold voltage. Thus, it is difficult to use the amorphous silicon thin-film transistor for an active matrix organic light-emitting device (AMOLED).

The polycrystalline silicon thin-film transistor (poly-Si TFT) may be obtained by depositing amorphous silicon and crystallizing the deposited amorphous silicon. The polycrystalline silicon thin-film transistor has advantages of high electron mobility and great stability, realization of a thin profile and high resolution, and high power efficiency. The polycrystalline silicon thin-film transistor may include a low-temperature polysilicon (LTPS) thin-film transistor, and a polysilicon thin-film transistor. However, a process of manufacturing the polycrystalline silicon thin-film transistor inevitably needs a step of crystallizing the amorphous silicon, whereby a manufacturing cost is increased due to the increased number of manufacturing steps. Also, the polycrystalline silicon thin-film transistor has a disadvantage of crystallization at a high temperature. Thus, it is difficult to apply the polycrystalline silicon thin-film transistor to a large-sized display device.

The oxide semiconductor thin-film transistor ("oxide semiconductor TFT"), which has high mobility and has a large resistance change in accordance with an oxygen content, is advantageous in that it facilitates obtaining desired properties. Also, an active layer of oxide is formed at a relatively low temperature for a process of manufacturing the oxide semiconductor thin-film transistor, whereby it is possible to lower a manufacturing cost. Also, owing to the properties of oxide, an oxide semiconductor is transparent, whereby it is favorable to realization of a transparent display device. However, in comparison to the polycrystalline silicon thin-film transistor, the oxide semiconductor thin-film transistor has relatively low stability and electron mobility.

Recently, with an advancement of high resolution or high pixel density in a mobile display device, lots of pixels are arranged in a small area, whereby a thin-film transistor for switching or driving the pixel inevitably needs good electrical properties and high stability. Thus, it is desirable to provide a thin-film transistor having good electrical properties and high stability.

<CIT> describes a thin film transistor including a substrate, a source electrode and a drain electrode formed on the substrate, a channel layer formed between the source electrode and the drain electrode, an insulative layer covering the channel layer and a gate electrode formed on the insulative layer.

<CIT> describes a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode.

In an aspect, a thin-film transistor is provided as defined in claim <NUM>. In another aspect, a display device is provided as defined in claim <NUM>. In another aspect, a method of manufacturing a thin-film transistor is provided as defined in claim <NUM>. Embodiments of the present disclosure will now be described. The scope of the invention is defined by the appended claims and only the implementations described below that are consistent with the claims fall within their scope.

Accordingly, the present disclosure is directed to a thin-film transistor, a display device including the same, and a method of manufacturing the same that substantially obviate one or more of the issues due to limitations and disadvantages of the related art.

The present disclosure provides a thin-film transistor having good electrical stability, a display device comprising the same, and a method of manufacturing the same.

The present disclosure provides a thin-film transistor having improved electrical stability by the use of a silicon semiconductor layer disposed between two oxide semiconductor layers, a display device comprising the same, and a method of manufacturing the same.

Additional features will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts provided herein. Other features of the inventive concepts may be realized and attained by the structure particularly pointed out in the written description, or derivable therefrom, and the claims hereof as well as the appended drawings.

In an example, there is provided a thin-film transistor, including: a semiconductor layer including: a first oxide semiconductor layer including gallium (Ga), a second oxide semiconductor layer, and a silicon semiconductor layer between the first oxide semiconductor layer and the second oxide semiconductor layer, and a gate electrode spaced apart from the semiconductor layer and partially overlapping at least a part of the semiconductor layer.

In another example, there is provided a display device, including: a substrate, a pixel driving circuit on the substrate, and a display element connected to the pixel driving circuit, the pixel driving circuit including a thin-film transistor, the thin-film transistor including: a semiconductor layer including: a first oxide semiconductor layer including gallium (Ga), a second oxide semiconductor layer, and a silicon semiconductor layer between the first oxide semiconductor layer and the second oxide semiconductor layer, and a gate electrode spaced apart from the semiconductor layer and partially overlapping at least a part of the semiconductor layer.

In another example, there is provided a method of manufacturing a thin-film transistor, the method including: providing a semiconductor layer including: providing a first oxide semiconductor layer including gallium (Ga), providing a second oxide semiconductor layer, and forming a silicon semiconductor layer by metal-organic chemical vapor deposition (MOCVD) between the first oxide semiconductor layer and the second oxide semiconductor layer, and providing a gate electrode spaced apart from the semiconductor layer and partially overlapping at least a part of the semiconductor layer.

Other systems, methods, features and advantages will be, or will become, apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the present disclosure, and be protected by the following claims. Nothing in this section should be taken as a limitation on those claims. Further examples and advantages are discussed below in conjunction with embodiments of the disclosure. It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are examples and explanatory, and are intended to provide further explanation of the disclosure as claimed.

The accompanying drawings, that may be included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain various principles of the disclosure.

Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures.

Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, when a detailed description of well-known functions or configurations related to this document is determined to unnecessarily cloud a gist of the inventive concept, the detailed description thereof will be omitted. The progression of processing steps and/or operations described is an example; however, the sequence of steps and/or operations is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps and/or operations necessarily occurring in a particular order. Like reference numerals designate like elements throughout. Names of the respective elements used in the following explanations are selected only for convenience of writing the specification and may be thus different from those used in actual products.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms.

The term "at least one" should be understood as including any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of a first item, a second item, and a third item" denotes the combination of all items proposed from two or more of the first item, the second item, and the third item as well as the first item, the second item, or the third item.

In the description of embodiments, when a structure is described as being positioned "on or above" or "under or below" another structure, this description should be construed as including a case in which the structures contact each other as well as a case in which a third structure is disposed therebetween. The size and thickness of each element shown in the drawings are given merely for the convenience of description, and embodiments of the present disclosure are not limited thereto.

The terms "first horizontal axis direction," "second horizontal axis direction," and "vertical axis direction" should not be interpreted only based on a geometrical relationship in which the respective directions are perpendicular to each other, and may be meant as directions having wider directivities within the range within which the components of the present disclosure can operate functionally.

Features of various embodiments of the present disclosure may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. Embodiments of the present disclosure may be carried out independently from each other, or may be carried out together in co-dependent relationship.

In the embodiments of the present disclosure, a source electrode and a drain electrode are distinguished from each other, for convenience of explanation. However, the source electrode and the drain electrode are used interchangeably. Thus, the source electrode may be the drain electrode, and the drain electrode may be the source electrode. Also, the source electrode in any one embodiment of the present disclosure may be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any one embodiment of the present disclosure may be the source electrode in another embodiment of the present disclosure.

In one or more embodiments of the present disclosure, for convenience of explanation, a source region is distinguished from a source electrode, and a drain region is distinguished from a drain electrode. However, embodiments of the present disclosure are not limited to this structure. For example, a source region may be a source electrode, and a drain region may be a drain electrode. Also, a source region may be a drain electrode, and a drain region may be a source electrode.

<FIG> is a cross-sectional view illustrating a thin-film transistor according to one embodiment of the present disclosure.

A thin-film transistor <NUM> according to one embodiment of the present disclosure includes a semiconductor layer <NUM>, and a gate electrode <NUM> spaced apart from the semiconductor layer <NUM> and partially overlapping the semiconductor layer <NUM>. As used herein, when a first element is described as partially overlapping a second element, the first element may partially overlap the second element in a cross-sectional view of the first and second elements. In other words, the first element may be disposed at least partially vertically above or below the second element in a cross-sectional view of the first and second elements. As used herein, references to elements being vertically above or below other elements should not be understood as referring to absolute orientations of an element, but rather as indicating relative positions of elements. As used herein, a vertical direction may refer to a direction perpendicular to a plane of the first element and/or the second element. With reference to the example of <FIG>, the semiconductor layer <NUM> may be on a substrate <NUM>.

The substrate <NUM> may include glass or plastic. For example, the substrate <NUM> may include a transparent plastic material having flexibility, for example, polyimide.

A buffer layer <NUM> may be on the substrate <NUM>. The buffer layer <NUM> may include at least one of silicon oxide and silicon nitride. The buffer layer <NUM> may be formed in a single-layered structure, or in a multi-layered structure having at least two layers. The buffer layer <NUM> may have good insulating properties and good planarization properties, and the buffer layer <NUM> may protect the semiconductor layer <NUM>. The buffer layer <NUM> may be omitted.

According to one embodiment of the present disclosure, the semiconductor layer <NUM> includes a first oxide semiconductor layer <NUM>, a second oxide semiconductor layer <NUM>, and a silicon semiconductor layer <NUM> between the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM>. The silicon semiconductor layer <NUM> contacts each of the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM>. The first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM> are spaced apart from each other by the silicon semiconductor layer <NUM>. With reference to <FIG>, the first oxide semiconductor layer <NUM> contacts one surface of the silicon semiconductor layer <NUM>. The second oxide semiconductor layer <NUM> contacts the other surface of the silicon semiconductor layer <NUM>. According to the invention, the silicon semiconductor layer <NUM> contacts the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM>.

With reference to <FIG>, the first oxide semiconductor layer <NUM>, the silicon semiconductor layer <NUM>, and the second oxide semiconductor layer <NUM> are sequentially disposed on the substrate <NUM>. However, embodiments of the present disclosure are not limited to the above structure. For example, the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM> may be positioned interchangeably.

According to the invention, the first oxide semiconductor layer <NUM> serves as a supporting layer for supporting the second oxide semiconductor layer <NUM>, and the second oxide semiconductor layer <NUM> serves as a channel layer. A channel of the semiconductor layer <NUM> is formed in the second oxide semiconductor layer <NUM>.

The first oxide semiconductor layer <NUM> serving as the supporting layer has great film stability and good mechanical properties. For the great film stability, the first oxide semiconductor layer <NUM> includes gallium (Ga). Herein, gallium (Ga) may form a stabilized bonding to oxygen, and gallium oxide has good film stability. Thus, if the oxide semiconductor layer includes gallium (Ga), it is possible to improve film stability and etch resistance. According to one embodiment of the present disclosure, the first oxide semiconductor layer <NUM> may include one or more of: an IGZO (indium gallium zinc oxide; InGaZnO)-based oxide semiconductor material, an IGO (indium gallium oxide; InGaO)-based oxide semiconductor material, an IGTO (indium gallium tin oxide; InGaSnO)-based oxide semiconductor material, an IGZTO (indium gallium zinc tin oxide; InGaZnSnO)-based oxide semiconductor material, a GZTO (gallium zinc tin oxide; GaZnSnO)-based oxide semiconductor material, a GZO (gallium zinc oxide; GaZnO)-based oxide semiconductor material, and a GO (gallium oxide; GaO)-based oxide semiconductor material. Embodiments are not limited to these examples.

For the good film stability, the first oxide semiconductor layer <NUM> may include gallium (Ga) of <NUM> atom% or more in comparison to a total metallic element with respect to an atom number. When gallium (Ga) of <NUM> atom% or more is included in the total metallic element of the first oxide semiconductor layer <NUM>, the first oxide semiconductor layer <NUM> may have the good film stability.

According to one embodiment of the present disclosure, the metallic element of the first oxide semiconductor layer <NUM> may be all gallium (Ga). In this case, the first oxide semiconductor layer <NUM> may include the GO (GaO)-based oxide semiconductor material, and the content of gallium (Ga) in the entire metallic element of the first oxide semiconductor <NUM> may be <NUM> atom%. In consideration of the electrical properties of the first oxide semiconductor layer <NUM>, the first oxide semiconductor layer <NUM> may include gallium (Ga) of <NUM> atom% or less in comparison to the total metallic element.

According to one embodiment of the present disclosure, the first oxide semiconductor layer <NUM> may have a thickness of <NUM> to <NUM>. If the thickness of the first oxide semiconductor layer <NUM> is less than <NUM>, the film stability of the first oxide semiconductor layer <NUM> may be deteriorated. Meanwhile, if the thickness of the first oxide semiconductor layer <NUM> is more than <NUM>, the semiconductor layer <NUM> may have an increased total thickness so that it may be difficult to realize a thin profile of a display device.

According to one embodiment of the present disclosure, a channel of the thin-film transistor <NUM> is formed in the second oxide semiconductor layer <NUM>. Thus, the second oxide semiconductor layer <NUM> may be referred to as a "channel" layer. The second oxide semiconductor layer <NUM> includes an oxide semiconductor material. For example, the second oxide semiconductor layer <NUM> may include an IZO (indium zinc oxide; InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (indium tin oxide; InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, or an ITZO (indium tin zinc oxide; InSnZnO)-based oxide semiconductor material. However, embodiments of the present disclosure are not limited to the above. For example, the second oxide semiconductor layer <NUM> may include other oxide semiconductor materials generally known to those in the art.

According to the invention, a concentration of gallium (Ga) in the first oxide semiconductor layer <NUM> is higher than a concentration of gallium (Ga) in the second oxide semiconductor layer <NUM>. Thus, the first oxide semiconductor layer <NUM> has greater film stability in comparison to that of the second oxide semiconductor layer <NUM>.

Indium (In) may improve a carrier concentration and current properties in the oxide semiconductor layer. According to one embodiment of the present disclosure, a concentration of indium (In) in the second oxide semiconductor layer <NUM> may be higher than a concentration of indium (In) in the first oxide semiconductor layer <NUM>. Thus, the second oxide semiconductor layer <NUM> may have greater electrical properties in comparison to that of the first oxide semiconductor layer <NUM>. According to one embodiment of the present disclosure, to provide the second oxide semiconductor layer <NUM> functioning as the channel layer, a carrier concentration of the second oxide semiconductor layer <NUM> may be higher than a carrier concentration of the first oxide semiconductor layer <NUM>.

However, if the thickness of the second oxide semiconductor layer <NUM> having the high carrier concentration is increased too much, a variable range of a threshold voltage in the thin-film transistor <NUM> may be increased due to the high carrier concentration of the second oxide semiconductor layer <NUM>, to thereby deteriorate the switching properties. Thus, according to one embodiment of the present disclosure, the second oxide semiconductor layer <NUM> may have a thickness of <NUM> or less.

Meanwhile, if the thickness of the second oxide semiconductor layer <NUM> is excessively small, the film stability of the second oxide semiconductor layer <NUM> is lowered so that it is difficult to provide a uniform film. Thus, the second oxide semiconductor layer <NUM> may have a thickness of <NUM> or more.

According to one embodiment of the present disclosure, the second oxide semiconductor layer <NUM> may have a thickness of <NUM> to <NUM>. For example, the second oxide semiconductor layer <NUM> may have a thickness of <NUM> to <NUM>.

According to one embodiment of the present disclosure, the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM> may be formed by metal-organic chemical vapor deposition (MOCVD). If the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM> are formed by MOCVD, each of the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM> may be a stable thin film having a uniform surface. Thus, it may be possible to form the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM> having uniformity, stability, and fine film structure by the MOCVD.

Generally, gallium (Ga) may be excited by light, and then the excited gallium may emit an excited electron. Also, gallium (Ga) may trap a hole so that it may be possible to prevent an electron from being restricted by the hole.

When the first oxide semiconductor layer <NUM> is irradiated with light, gallium (Ga) included in the first oxide semiconductor layer <NUM> may absorb light, to thereby emit the electron. If the first oxide semiconductor layer <NUM> is in direct contact with the second oxide semiconductor layer <NUM>, the electron generated from gallium (Ga) of the first oxide semiconductor layer <NUM> by the light absorption may be transferred to the second oxide semiconductor layer <NUM>, whereby the carrier concentration of the second oxide semiconductor layer <NUM> may be increased. When the carrier (e.g., electron) concentration of the second oxide semiconductor layer <NUM> is increased, a threshold voltage may be lowered, whereby the threshold voltage of the thin-film transistor <NUM> may be shifted to a negative (-) direction. As a result, the driving properties of the thin-film transistor <NUM> may become unstable. To reduce or prevent the driving properties of the thin-film transistor <NUM> from being unstable, according to one embodiment of the present disclosure, the silicon semiconductor layer <NUM> is disposed between the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM>.

According to one embodiment of the present disclosure, the silicon semiconductor layer <NUM> may be an intrinsic silicon semiconductor layer. The term "intrinsic silicon semiconductor" indicates a pure semiconductor without any impurities.

For example, the silicon semiconductor layer <NUM> according to one embodiment of the present disclosure may include the intrinsic silicon semiconductor. The silicon semiconductor layer <NUM> may include silicon in which impurities are not included, or in which impurities are scarcely included (e.g., very few impurities are included).

Also, according to one embodiment of the present disclosure, the silicon semiconductor layer <NUM> may include amorphous silicon. For example, when a silicon layer is formed by a deposition method, and an additional heat treatment is not carried out, the silicon semiconductor layer <NUM> of the amorphous silicon may be formed. However, embodiments of the present disclosure are not limited to the above. For example the silicon semiconductor layer <NUM> may include polycrystalline silicon (poly-Si).

According to the invention, the silicon semiconductor layer <NUM> functions as a light-shielding layer or an electron-interrupting layer. The silicon has low light transmittance so that it may be possible to block light. Accordingly, it may be possible to reduce or prevent light from being transmitted through the first oxide semiconductor layer <NUM> or the second oxide semiconductor layer <NUM>. For example, when light is incident from an upper side of the drawing in which the second oxide semiconductor layer <NUM> is positioned, the silicon semiconductor layer <NUM> may block light so that it may be possible to restrict or prevent the first oxide semiconductor layer <NUM> from being irradiated with light.

Also, a slight amount of current may flow through the silicon semiconductor layer <NUM> of the intrinsic semiconductor or a current may scarcely flow through the silicon semiconductor layer <NUM> of the intrinsic semiconductor, whereby the silicon semiconductor layer <NUM> may block or reduce a current flow. For example, when light is incident from a lower side of the <FIG> drawing in which the substrate <NUM> is positioned, light may approach the first oxide semiconductor layer <NUM>, whereby the electron may be generated in the first oxide semiconductor layer <NUM>. However, the silicon semiconductor layer <NUM> may serve as the electron interrupting layer so that it may be possible to restrict or prevent the electron generated in the first oxide semiconductor layer <NUM> from being transferred to the second oxide semiconductor layer <NUM>. As a result, it may be possible to avoid or prevent the carrier concentration of the second oxide semiconductor layer <NUM> from being increased, and to constantly maintain the electrical properties in the second oxide semiconductor layer <NUM>.

The silicon semiconductor layer <NUM> has the properties of blocking the light, and of interrupting the electron transfer. For example, the silicon semiconductor layer <NUM> may maintain the properties of semiconductor. As a result, a laminated structure, including the first oxide semiconductor layer <NUM>, the silicon semiconductor layer <NUM>, and the second oxide semiconductor layer <NUM>, may serve as the semiconductor layer <NUM> having the properties of semiconductor.

According to one embodiment of the present disclosure, the silicon semiconductor layer <NUM> may have a thickness of <NUM> to <NUM>. If the thickness of the silicon semiconductor layer <NUM> is less than <NUM>, the film stability and the light blocking properties of the silicon semiconductor layer <NUM> may be deteriorated. For example, if the thickness of the silicon semiconductor layer <NUM> is more than <NUM>, etching of the semiconductor layer <NUM> may become more difficult, and a processing cost may increase. In addition, if the thickness of the silicon semiconductor layer <NUM> is more than <NUM>, a carrier may be generated by a radiation of light, which may deteriorate the properties of the blocking current or the electron transfer.

According to one embodiment of the present disclosure, the silicon semiconductor layer <NUM> may be formed by metal-organic chemical vapor deposition (MOCVD). The silicon semiconductor layer <NUM> having a uniform surface, a thin profile, and a film stability may be formed by metal-organic chemical vapor deposition (MOCVD).

Also, if all of the first oxide semiconductor layer <NUM>, the second oxide semiconductor layer <NUM>, and the silicon semiconductor layer <NUM> are formed by metal-organic chemical vapor deposition (MOCVD), the first oxide semiconductor layer <NUM>, the silicon semiconductor layer <NUM>, and the second oxide semiconductor layer <NUM> may be sequentially formed without vacuum braking. As a result, it may be possible to decrease a manufacturing cost and to improve a process stability.

A gate insulating layer <NUM> may be on the semiconductor layer <NUM>. The gate insulating layer <NUM> may include at least one of: silicon oxide and silicon nitride. The gate insulating layer <NUM> may include oxide aluminum (Al<NUM>O<NUM>). The gate insulating layer <NUM> may be formed in a single-layered structure or a multi-layered structure.

With further reference to <FIG>, the gate electrode <NUM> may be on the gate insulating layer <NUM>. The gate electrode <NUM> may be insulated from the semiconductor layer <NUM>, and may partially overlap the semiconductor layer <NUM>.

The gate electrode <NUM> may include one or more of: an aluminum-based metal, such as aluminum (Al) or an aluminum alloy; a silver-based metal such as silver (Ag) or a silver alloy; a copper-based metal, such as copper (Cu) or a copper alloy; a molybdenum-based metal, such as molybdenum (Mo) or a molybdenum alloy; chromium (Cr); tantalum (Ta), neodymium (Nd); and titanium (Ti). The gate electrode <NUM> may have a multi-layered structure, including at least two layers with different physical properties.

An insulating interlayer <NUM> may be on the gate electrode <NUM>. The insulating interlayer <NUM> may include an insulating material. For example, the insulating interlayer <NUM> may include an organic material, an inorganic material, or a deposition structure including an organic material and an inorganic material.

The thin-film transistor <NUM> according to one embodiment of the present disclosure may include a source electrode <NUM> and a drain electrode <NUM>. With further reference to <FIG>, the source electrode <NUM> and the drain electrode <NUM> may be on the insulating interlayer <NUM>. The source electrode <NUM> and the drain electrode <NUM> may be spaced apart from each other, and may be connected to the semiconductor layer <NUM>. With additional reference to <FIG>, the source electrode <NUM> and the drain electrode <NUM> may be respectively connected to the semiconductor layer <NUM> through contact holes provided in the insulating interlayer <NUM>. For example, each of the source electrode <NUM> and the drain electrode <NUM> may be connected to the second oxide semiconductor layer <NUM> of the semiconductor layer <NUM>.

The source electrode <NUM> and the drain electrode <NUM> may include one or more of: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. Each of the source electrode <NUM> and the drain electrode <NUM> may be formed in a single-layered structure, including the above metal or its alloy, or may be formed in a multi-layered structure, including at least two layers of the above metal or its alloy.

The semiconductor layer <NUM>, the gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM>, which are shown in <FIG>, constitute the thin-film transistor <NUM>. However, embodiments of the present disclosure are not limited to the above. Herein, other parts of the semiconductor layer <NUM>, except a channel region overlapping the gate electrode <NUM>, may become conductive, and then the conductive portions may become a source region and a drain region that may be spaced apart from each other with respect to the channel region therebetween. Thus, the source region and the drain region may serve as the source electrode <NUM> and the drain electrode <NUM>, respectively.

<FIG> is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present disclosure.

Hereinafter, to avoid a repetitive explanation, a detailed description for the same parts will be omitted. In comparison with the thin-film transistor <NUM> shown in the example of <FIG>, a thin-film transistor <NUM> shown in the example of <FIG> may further include a light-shielding layer <NUM> between a substrate <NUM> and a buffer layer <NUM>. The light-shielding layer <NUM> may overlap a semiconductor layer <NUM>. The light-shielding layer <NUM> may block light incident on the semiconductor layer <NUM> of the thin-film transistor <NUM> from the external environment, to thereby reduce or prevent the semiconductor layer <NUM> from being damaged by the externally-provided light.

Generally, the light-shielding layer <NUM> may include an electrically conductive material, such as metal. The buffer layer <NUM> may be on the light-shielding layer <NUM> to insulate the light-shielding layer <NUM> and the semiconductor layer <NUM> from each other. The light-shielding layer <NUM> may be electrically connected to any one of a source electrode <NUM> and a drain electrode <NUM>.

A thin-film transistor <NUM> of the <FIG> example may include a gate electrode <NUM> on a substrate <NUM>, and a semiconductor layer <NUM> spaced apart from the gate electrode <NUM> and partially overlapping the gate electrode <NUM>. Also, the thin-film transistor <NUM> may include a gate insulating layer <NUM> between the gate electrode <NUM> and the semiconductor layer <NUM>, a source electrode <NUM> connected to the semiconductor layer <NUM>, and a drain electrode <NUM> spaced apart from the source electrode <NUM> and connected to the semiconductor layer <NUM>.

As shown in <FIG>, the structure in which the gate electrode <NUM> is disposed below the semiconductor layer <NUM> may be referred to as a "bottom-gate" structure. Herein, the semiconductor layer <NUM>, the gate electrode <NUM>, the source electrode <NUM>, and the drain electrode <NUM> may constitute the thin-film transistor <NUM>.

With reference to <FIG>, a first oxide semiconductor layer <NUM>, a silicon semiconductor layer <NUM>, and a second oxide semiconductor layer <NUM>, which may constitute the semiconductor layer <NUM>, are sequentially deposited on the substrate <NUM>. However, embodiments of the present disclosure are not limited to the above structure. For example, the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM> may be positioned interchangeably.

<FIG> is a cross-sectional view illustrating a thin-film transistor <NUM> according to another embodiment of the present disclosure.

In comparison with the thin-film transistor <NUM> shown in the <FIG> example, the thin-film transistor <NUM> shown in the <FIG> example may further include an etch stopper <NUM> on a semiconductor layer <NUM>. The etch stopper <NUM> may include an insulating material. The etch stopper <NUM> may protect a channel region of the semiconductor layer <NUM>. Thus, the semiconductor layer <NUM> according to one embodiment of the present disclosure may be applied to the thin-film transistor <NUM> having an etch stopper structure.

<FIG> is a graph illustrating a relation between a thickness of an oxide semiconductor layer and a carrier concentration of an oxide semiconductor layer in a thin-film transistor having uniformity of a threshold voltage.

To provide an oxide semiconductor layer functioning as a channel layer of a thin-film transistor, the oxide semiconductor layer may have a high carrier concentration. However, on the presumption that the oxide semiconductor layer has the high carrier concentration, if a thickness of the oxide semiconductor layer is increased, a variable range of the threshold voltage in the thin-film transistor may be increased due to a large amount of carriers existing in the oxide semiconductor layer, whereby the switching properties may be lowered. To prevent this problem, the thickness of the oxide semiconductor layer may be small.

In <FIG>, when a thin-film transistor has an oxide semiconductor layer, a variable range of a threshold voltage may be <NUM> V or less, which may provide conditions enabling good uniformity of threshold voltage. For example, when the variable range of the threshold voltage in the thin-film transistor is <NUM> V or less, the thickness of the oxide semiconductor layer for the carrier concentration of the oxide semiconductor layer may be as shown in <FIG>.

With reference to <FIG>, as the carrier concentration of the oxide semiconductor layer increases, the thickness of the oxide semiconductor layer may have to be small, whereby the variable range of the threshold voltage in the thin-film transistor may be 1V or less. For example, on the presumption that an IGZO-based oxide semiconductor layer (In:Ga:Zn = <NUM>:<NUM>:<NUM>, atom number) has a carrier concentration of <NUM><NUM>/cm<NUM>, when a thickness of the IGZO-based oxide semiconductor layer is about <NUM> or less, a variable range of a threshold voltage in a thin-film transistor may be <NUM> V or less.

Hereinafter, when a semiconductor layer is formed only with a second oxide semiconductor layer <NUM> functioning as a channel layer, its problem will be described as follows.

<FIG> is a cross-sectional view illustrating a thin-film transistor according to a Comparative Example <NUM>.

The thin-film transistor according to the Comparative Example <NUM> includes a semiconductor layer formed only with a second oxide semiconductor layer <NUM> functioning as a channel layer. For example, the thin-film transistor of <FIG> is similar in structure to the thin-film transistor <NUM> of <FIG>. However, the thin-film transistor of <FIG> includes the semiconductor layer formed only with the second oxide semiconductor layer <NUM>. The second oxide semiconductor layer <NUM> has a thickness of about <NUM> to realize the switching properties.

<FIG> is a photograph showing damage (DM) generated in the thin-film transistor of <FIG>.

With reference to <FIG>, the second oxide semiconductor layer <NUM>, which has a thickness of about <NUM> and is singly provided on a buffer layer <NUM>, has an instable film shape having an uneven surface, and damage (DM) of a cutting shape are generated in the second oxide semiconductor layer <NUM>. To overcome this problem, which might be generated in the above structure of the semiconductor layer formed only with the second oxide semiconductor layer <NUM>, a first oxide semiconductor layer <NUM> functioning as a supporting layer may be disposed below the second oxide semiconductor layer <NUM> (e.g., Comparative Example <NUM>).

With reference to <FIG>, the thin-film transistor according to the Comparative Example <NUM> includes a semiconductor layer, wherein the semiconductor layer includes a first oxide semiconductor layer <NUM>, and a second oxide semiconductor layer <NUM> on the first oxide semiconductor layer <NUM>. In <FIG>, the first oxide semiconductor layer <NUM> functioning as a supporting layer includes gallium (Ga), whose concentration is relatively higher than that of the second oxide semiconductor layer <NUM> to realize the film stability. For example, the first oxide semiconductor layer <NUM> corresponds to an IGZO-based oxide semiconductor layer in which an atom ratio of indium (In), gallium (Ga), and zinc (Zn) is <NUM>:<NUM>:<NUM> (In:Ga:Zn = <NUM>:<NUM>:<NUM>, atom number).

<FIG> is a graph illustrating a comparison result of showing a threshold voltage in the thin-film transistor of the Comparative Example <NUM> onto which light is irradiated, and a threshold voltage in the thin-film transistor of the Comparative Example <NUM> onto which light is not irradiated.

The graph of <FIG> shows a current (IDS) between a source electrode and a drain electrode in accordance with a voltage (VGS) between a gate electrode and a source electrode. In <FIG>, "I<NUM>" is a line (solid line) illustrating the threshold voltage before light is irradiated, and "isr" is a line (dotted line) illustrating the threshold voltage after light is irradiated.

Generally, gallium (Ga) is excited by light, and then the excited gallium may emit an excited electron. Also, gallium (Ga) traps a hole so that it is possible to prevent an electron from being restricted by the hole. If the first oxide semiconductor layer <NUM> is irradiated with light, gallium (Ga) included in the first oxide semiconductor layer <NUM> absorbs light, to thereby emit the excited electron. In the thin-film transistor according to the Comparative Example <NUM> (see <FIG>), as the first oxide semiconductor layer <NUM> is in direct contact with the second oxide semiconductor layer <NUM>, the electron generated from gallium (Ga) by the light absorption is transferred to the second oxide semiconductor layer <NUM>, whereby the carrier concentration of the second oxide semiconductor layer <NUM> is increased. If the carrier (electron) concentration of the second oxide semiconductor layer <NUM> is increased, the threshold voltage is lowered, whereby the threshold voltage of the thin-film transistor is shifted to a negative (-) direction. As a result, as shown in <FIG>, in comparison to "I<NUM>" corresponding to the graph showing the threshold voltage before light is irradiated, "IST" corresponding to the graph showing the threshold voltage after light is irradiated is shifted to a negative (-) direction.

To reduce or prevent the driving instability of the thin-film transistor, that is, to reduce or prevent the carrier concentration of the second oxide semiconductor layer <NUM> from being increased by the first oxide semiconductor layer <NUM>, the thin-film transistor <NUM> according to the invention includes the silicon semiconductor layer <NUM> between the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM>. The silicon semiconductor layer <NUM> functions as the light-shielding layer or electron-interrupting layer.

<FIG> is a graph illustrating a light transmittance of silicon.

With reference to <FIG>, silicon shows a light transmittance of <NUM>% or less in a visible ray range. For example, silicon has a light transmittance of <NUM>% or less for light having a wavelength of <NUM> to <NUM> corresponding to a wavelength range enabling the generation of excited electron by the use of gallium (Ga) included in the first oxide semiconductor layer <NUM>.

Thus, silicon having a low light transmittance is capable of blocking light. As a result, if light is incident from an upper side of the drawing in which the second oxide semiconductor layer <NUM> is positioned, the silicon semiconductor layer <NUM> may block light so that it may be possible to restrict or prevent the first oxide semiconductor layer <NUM> from being irradiated with light. Thus, it may be possible to restrict or prevent the excited electron from being generated in the first oxide semiconductor layer <NUM>.

Also, a slight amount of current may flow through the silicon semiconductor layer <NUM> of intrinsic semiconductor, or a current may scarcely flow through the silicon semiconductor layer <NUM> of intrinsic semiconductor, whereby the silicon semiconductor layer <NUM> may block or reduce a current flow. As a result, even though an electron may be generated in the first oxide semiconductor layer <NUM> by incident light from a lower side of the drawing in which the substrate <NUM> is positioned, the silicon semiconductor layer <NUM> may serve as the electron interrupting layer so that it may be possible to restrict or prevent the electron generated in the first oxide semiconductor layer <NUM> from being transferred to the second oxide semiconductor layer <NUM>. Thus, according to the invention, if the silicon semiconductor layer <NUM> is disposed between the first oxide semiconductor layer <NUM> and the second oxide semiconductor layer <NUM>, it may be possible to avoid or prevent the carrier concentration of the second oxide semiconductor layer from being increased, to thereby constantly maintain the electrical properties in the second oxide semiconductor layer <NUM>.

<FIG> is a graph illustrating a comparison result of showing a threshold voltage in the thin-film transistor according to one embodiment of the present disclosure onto which light is irradiated, and a threshold voltage in the thin-film transistor according to one embodiment of the present disclosure onto which light is not irradiated.

The graph of <FIG> is expressed as a current (IDS) between a source electrode and a drain electrode in accordance with a voltage (VGS) between a gate electrode and a source electrode. In <FIG>, "I<NUM>" is a line (solid line) illustrating the threshold voltage before light is irradiated, and "isr" is a line (dotted line) illustrating the threshold voltage after light is irradiated.

With reference to <FIG>, in comparison to "I<NUM>" corresponding to the graph showing the threshold voltage before light is irradiated, "IST" corresponding to the graph showing the threshold voltage after light is irradiated is not very (scarcely) shifted. Thus, according to one embodiment of the present disclosure, it may be possible to secure the driving stability of the thin-film transistor <NUM>.

<FIG> is a view illustrating a display device according to another embodiment of the present disclosure. <FIG> is a circuit diagram illustrating any one pixel (P) of <FIG>. <FIG> is a plane view illustrating the pixel (P) of <FIG>. <FIG> is a cross-sectional view along line I-I' of <FIG>.

Hereinafter, a display device <NUM> according to another embodiment of the present disclosure will be described with reference to <FIG>. The display device <NUM> according to another embodiment of the present disclosure may include a substrate <NUM>, a pixel driving circuit (PDC) on the substrate <NUM>, and a display element <NUM> connected to the pixel driving circuit (PDC). The pixel driving circuit (PDC) may include a thin-film transistor. Any of the thin-film transistors <NUM>, <NUM>, <NUM>, and <NUM> shown in the examples of <FIG>, <FIG> may be used for the thin-film transistor. Thus, to avoid a repetitive explanation, a detailed description for the thin-film transistors <NUM>, <NUM>, <NUM>, and <NUM> will be omitted.

As shown in the <FIG> example, the display device <NUM> according to another embodiment of the present disclosure may include a pixel (P), a gate driver <NUM>, a data driver <NUM>, and a controller <NUM> on a substrate <NUM>. On the substrate <NUM>, there may be gate lines (GL) and data lines (DL), and the pixel (P) may be at a crossing portion of the gate line (GL) and the data line (DL). The pixel (P) may include a display element <NUM>, and a pixel driving circuit (PDC) for driving the display element <NUM>. An image may be displayed by driving the pixel (P).

The controller <NUM> may control the gate driver <NUM> and the data driver <NUM>. The controller <NUM> may output a gate control signal (GCS) for controlling the gate driver <NUM> and a data control signal (DCS) for controlling the data driver <NUM> by the use of vertically / horizontally synchronized signal and clock signal supplied from an external system (not shown). Also, the controller <NUM> may sample input video data, which may be provided from the external system, and then may re-align the sampled video data, and may supply the re-aligned digital video data (RGB) to the data driver <NUM>.

The gate control signal (GCS) may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a gate clock (GCLK). Also, control signals for controlling a shift register may be included in the gate control signal (GCS). The data control signal (DCS) may include a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), and a polarity control signal (POL).

The data driver <NUM> may supply a data voltage to the data lines (DL) on the substrate <NUM>. For example, the data driver <NUM> may convert the video data (RGB) provided from the controller <NUM> into an analog data voltage, and may supply the analog data voltage to the data lines (DL).

The gate driver <NUM> may sequentially supply a gate pulse (GP) to the gate lines (GL) for one (<NUM>) frame period. Herein, "one frame" indicates the period in which one image is output through a display panel. Also, the gate driver <NUM> may supply a gate-off signal for turning off the switching device to the gate line (GL) for the remaining period of one frame in which the gate pulse (GP) is not supplied. Hereinafter, the gate pulse (GP) and the gate-off signal (Goff) are referred to together as "scan signals (SS).

According to one embodiment of the present disclosure, the gate driver <NUM> may be on the substrate <NUM>. A structure of directly providing the gate driver <NUM> on the substrate <NUM> may be referred to as Gate-In-Panel (GIP) structure.

The circuit diagram of <FIG> corresponds to an equivalent circuit diagram for one pixel (P) in a display device <NUM>, including an organic light-emitting diode (OLED). A pixel driving circuit (PDC) of <FIG> may include a first thin-film transistor (TR1) corresponding to a switching transistor, and a second thin-film transistor (TR2) corresponding to a driving transistor. Any of the thin-film transistors <NUM>, <NUM>, <NUM>, and <NUM> shown in <FIG>, <FIG> may be used for the first thin-film transistor (TR1) and the second thin-film transistor (TR2).

The first thin-film transistor (TR1) may be connected to gate and data lines (GL, DL), and may be turned on or turned off by a scan signal (SS) supplied through the gate line (GL). The data line (DL) may provide a data voltage (Vdata) to the pixel driving circuit (PDC), and the first thin-film transistor (TR1) may control an application of the data voltage (Vdata).

A driving voltage line (PL) may provide a driving voltage (Vdd) to a display element <NUM>, and the second thin-film transistor (TR2) may control the driving voltage (Vdd). The driving voltage (Vdd) may correspond to a pixel driving voltage for driving the organic light-emitting diode (OLED) corresponding to the display element <NUM>.

When the first thin-film transistor (TR1) is turned on by the scan signal (SS) applied from a gate driver <NUM> via the gate line (GL), the data voltage (Vdata) supplied via the data line (DL) may be supplied to a gate electrode (G2) of the second thin-film transistor (TR2) connected to the emission element <NUM>. The data voltage (Vdata) may be charged in a first capacitor (C1) provided between the gate electrode (G2) of the second thin-film transistor (TR2) and a source electrode (S2) of the second thin-film transistor (TR2). The first capacitor (C1) may correspond to a storage capacitor (Cst). The first capacitor (C1) may include a first capacitor electrode (C11) connected to the gate electrode (G2) of the second thin-film transistor (TR2), and a second capacitor electrode (C12) connected to the source electrode (S2) of the second thin-film transistor (TR2). A supply amount of current supplied to the organic light-emitting diode (OLED) corresponding to the display element <NUM> through the second thin-film transistor (TR2) may be controlled in accordance with the data voltage (Vdata), whereby it may be possible to control a grayscale of the light emitted from the display element <NUM>.

With reference to <FIG> and <FIG>, the pixel driving circuit (PDC) may be on a substrate <NUM>. The substrate <NUM> may include glass or plastic. For example, the substrate <NUM> may include a transparent plastic material having flexibility, for example, polyimide.

The pixel driving circuit (PDC) may include a light-shielding layer (LS1, LS2) on the substrate <NUM>, a buffer layer <NUM> on the light-shielding layer (LS1, LS2), a semiconductor layer (A1, A2) <NUM> on the buffer layer <NUM>, a gate electrode (G1, G2) partially overlapping the semiconductor layer (A1, A2) <NUM>, and a source electrode (S1, S2) and a drain electrode (D1, D2) connected to the semiconductor layer (A1, A2) <NUM>. The light-shielding layer (LS1, LS2) may be formed of an electrical conductive material such as metal. The light-shielding layer (LS1, LS2) may have the light-blocking properties. According to one embodiment of the present disclosure, the light-shielding layer (LS1, LS2) may block externally-provided light, to thereby protect the semiconductor layer <NUM>.

The buffer layer <NUM> may be on the light-shielding layer (LS1, LS2). The buffer layer <NUM> may include an insulating material, and may protect the semiconductor layer <NUM> from externally-provided moisture or oxygen. The semiconductor layer (A1) of the first thin-film transistor (TR1) and the semiconductor layer (A2) of the second thin-film transistor (TR2) may be on the buffer layer <NUM>. At least one of the semiconductor layer (A1) of the first thin-film transistor (TR1) and the semiconductor layer (A2) of the second thin-film transistor (TR2) may include a first oxide semiconductor layer <NUM> on the buffer layer <NUM>, a silicon semiconductor layer <NUM> on the first oxide semiconductor layer <NUM>, and a second oxide semiconductor layer <NUM> on the silicon semiconductor layer <NUM>.

With further reference to <FIG>, each of the semiconductor layer (A1) of the first thin-film transistor (TR1) and the semiconductor layer (A2) of the second thin-film transistor (TR2) may be formed in a structure including the first oxide semiconductor layer <NUM>, the silicon semiconductor layer <NUM>, and the second oxide semiconductor layer <NUM> deposited in sequence. However, embodiments of the present disclosure are not limited to the above. For example, any one of the semiconductor layer (A1) of the first thin-film transistor (TR1) and the semiconductor layer (A2) of the second thin-film transistor (TR2) may be formed in a structure including the first oxide semiconductor layer <NUM>, the silicon semiconductor layer <NUM>, and the second oxide semiconductor layer <NUM> deposited in sequence.

A gate insulating layer <NUM> may be on the semiconductor layer <NUM>. The gate insulating layer <NUM> may have the insulating properties. The gate electrode (G1, G2) may be on the gate insulating layer <NUM>. The gate electrode (G1, G2) may be an area extending from the gate line (GL), or may be a part of the gate line (GL). An insulating interlayer <NUM> may be on the gate electrode (G1, G2).

The source electrode (S1, S2) and the drain electrode (D1, D2) may be on the insulating interlayer <NUM>. According to one embodiment of the present disclosure, the source electrode (S1, S2) and the drain electrode (D1, D2) are distinguished from each other for convenience of explanation; however, the source electrode (S1, S2) and the drain electrode (D1, D2) may be used interchangeably. For example, the source electrode (S1, S2) may be the drain electrode (D1, D2), and the drain electrode (D1, D2) may be the source electrode (S1, S2).

According to one embodiment of the present disclosure, the source electrode (S1) and the drain electrode (D1) included in the first thin-film transistor (TR1) may be spaced apart from each other, and may be connected to the semiconductor layer (A1) of the first thin-film transistor (TR1). The source electrode (S2) and the drain electrode (D2) included in the second thin-film transistor (TR2) may be spaced apart from each other, and may be connected to the semiconductor layer (A2) of the second thin-film transistor (TR2).

Also, the data line (DL) and the driving power line (PL) may be on the insulating interlayer <NUM>. According to one embodiment of the present disclosure, the source electrode (S1) of the first thin-film transistor (TR1) may be connected to the data line (DL). The drain electrode (D2) of the second thin-film transistor (TR2) may be connected to the driving power line (PL).

As shown in the <FIG> example, the first thin-film transistor (TR1) may include the semiconductor layer (A1) <NUM>, the gate electrode (G1), the source electrode (S1), and the drain electrode (D1). The first thin-film transistor (TR1) may function as the switching transistor for controlling the data voltage (Vdata) applied to the pixel driving circuit (PDC).

The second thin-film transistor (TR2) may include the semiconductor layer (A2) <NUM>, the gate electrode (G2), the source electrode (S2), and the drain electrode (D2). The second thin-film transistor (TR2) may function as the driving transistor for controlling the driving voltage (Vdd) applied to the display element <NUM>.

A planarization layer <NUM> may be on the source electrode (S1, S2), the drain electrode (D1, D2), the data line (DL), and the driving power line (PL). The planarization layer <NUM> may planarize an upper surface of the first thin-film transistor (TR1) and an upper surface of the second thin-film transistor (TR2), and may also protect the first thin-film transistor (TR1) and the second thin-film transistor (TR2).

A first electrode <NUM> of the display element <NUM> may be on the planarization layer <NUM>. The first electrode <NUM> of the display element <NUM> may be connected to the source electrode (S2) of the second thin-film transistor (TR2) via a contact hole provided in the planarization layer <NUM>.

A bank layer <NUM> may be in the edge of the first electrode <NUM>. The bank layer <NUM> may define an emission area of the display element <NUM>.

An organic emission layer <NUM> may be on the first electrode <NUM>, and a second electrode <NUM> may be on the organic emission layer <NUM>, whereby the display element <NUM> may be completed. The display element <NUM> shown in the example of <FIG> may correspond to the organic light-emitting diode (OLED). Accordingly, the display device according to one embodiment of the present disclosure may correspond to the organic light-emitting display device.

<FIG> is a circuit diagram illustrating any one pixel (P) of a display device according to another embodiment of the present disclosure.

<FIG> is an equivalent circuit diagram for a pixel (P) of an organic light-emitting display device. The pixel (P) of a display device <NUM> shown in the <FIG> example may include an organic light-emitting diode (OLED) corresponding to a display element <NUM>, and a pixel driving circuit (PDC) for driving the display element <NUM>. The display element <NUM> may be connected to the pixel driving circuit (PDC). In the pixel (P), there may be signal lines (DL, GL, PL, RL, SCL) for supplying a signal to the pixel driving circuit (PDC). A data voltage (Vdata) may be supplied to a data line (DL), a scan signal (SS) may be supplied to a gate line (GL), a driving voltage (VDD) for driving the pixel may be supplied to a driving voltage line (PL), a reference voltage (Vref) may be supplied to a reference line (RL), and a sensing control signal (SCS) may be supplied to a sensing control line (SCL).

With reference to <FIG>, when the gate line of the nth pixel (P) is referred to as "GLn", the gate line of the neighboring (n-<NUM>)th pixel (P) may be "GLn-<NUM> ", and the gate line of the (n-<NUM>)th pixel (P) may serve as the sensing control line (SCL) of the nth pixel (P). For example, the pixel driving circuit (PDC) may include a first thin-film transistor (TR1, e.g., a switching transistor) connected to the gate line (GL) and the data line (DL), a second thin-film transistor (TR2, e.g., a driving transistor) configured to control a level of current provided to the display element <NUM> in accordance with the data voltage (Vdata) transmitted through the first thin-film transistor (TR1), and a third thin-film transistor (TR3, e.g., a reference transistor) configured to sense the properties of the second thin-film transistor (TR2).

A first capacitor (C1) may be positioned between the display element <NUM> and a gate electrode (G2) of the second thin-film transistor (TR2). The first capacitor (C1) may be referred to as a "storage capacitor (Cst).

The first thin-film transistor (TR1) may be turned on by the scan signal (SS) supplied to the gate line (GL), and the first thin-film transistor (TR1) may transmit the data voltage (Vdata), which may be supplied to the data line (DL), to the gate electrode (G2) of the second thin-film transistor (TR2). The third thin-film transistor (TR3) may be connected to the reference line (RL) and a first node (n1) between the display element <NUM> and the second thin-film transistor (TR2). The third thin-film transistor (TR3) may be turned on or turned off by the sensing control signal (SCS), and the third thin-film transistor (TR3) may sense the properties of the second thin-film transistor (TR2) corresponding the driving transistor for a sensing period.

A second node (n2) connected to the gate electrode (G2) of the second thin-film transistor (TR2) may be connected to the first thin-film transistor (TR1). The first capacitor (C1) may be formed between the second node (n2) and the first node (n1).

When the first thin-film transistor (TR1) is turned on, the data voltage (Vdata) supplied through the data line (DL) may be supplied to the gate electrode (G2) of the second thin-film transistor (TR2). The first capacitor (C1) formed between a source electrode (S2) and the gate electrode (G2) of the second thin-film transistor (TR2) may be charged with the data voltage (Vdata). When the second thin-film transistor (TR2) is turned on, a current may be supplied to the display element <NUM> through the second thin-film transistor (TR2) by the driving voltage (Vdd) for driving the pixel, whereby light may be emitted from the display element <NUM>.

The first thin-film transistor (TR1), the second thin-film transistor (TR2), and the third thin-film transistor (TR3) shown in <FIG> may be substantially similar in structure to any one among the thin-film transistors <NUM>, <NUM>, <NUM>, and <NUM> shown in <FIG>, <FIG>. Duplicate description will be omitted.

<FIG> is a circuit diagram illustrating a pixel of a display device according to another embodiment of the present disclosure.

The pixel (P) of a display device <NUM> shown in the <FIG> example may include an organic light-emitting diode (OLED) corresponding to a display element <NUM>, and a pixel driving circuit (PDC) for driving the display element <NUM>. The display element <NUM> may be connected to the pixel driving circuit (PDC). The pixel driving circuit (PDC) may be include thin-film transistors (TR1, TR2, TR3, TR4).

In the pixel (P), there may be signal lines (DL, EL, GL, PL, SCL, RL) for supplying a driving signal to the pixel driving circuit (PDC). In comparison with the pixel (P) of the <FIG> example, the pixel (P) of the <FIG> example further includes an emission control line (EL). An emission control signal (EM) may be supplied to the emission control line (EL). Also, in comparison with the pixel driving circuit (PDC) of <FIG>, the pixel driving circuit (PDC) of <FIG> further includes a fourth thin-film transistor (TR4) corresponding to an emission control transistor configured to control an emission time point of the second thin-film transistor (TR2). With reference to <FIG>, when the gate line of the nth pixel (P) is referred to as "GLn", the gate line of the neighboring (n-<NUM>)th pixel (P) may be "GLn-<NUM> ", and the gate line of the (n-<NUM>)th pixel (P) may serve as the sensing control line (SCL) of the nth pixel (P).

A first capacitor (C1) may be positioned between the display element <NUM> and a gate electrode (G2) of the second thin-film transistor (TR2). Also, a second capacitor (C2) may be between one electrode of the display element <NUM> and a terminal supplied with a driving voltage (Vdd) among a plurality of terminals included in the fourth thin-film transistor (TR4).

The first thin-film transistor (TR1) may be turned on by the scan signal (SS) supplied to the gate line (GL), and the first thin-film transistor (TR1) may transmit the data voltage (Vdata), which may be supplied to the data line (DL), to the gate electrode (G2) of the second thin-film transistor (TR2). The third thin-film transistor (TR3) may be connected to the reference line (RL), and may be turned on or turned off by the sensing control signal (SCS). The third thin-film transistor (TR3) may sense the properties of the second thin-film transistor (TR2) corresponding the driving transistor for a sensing period.

The fourth thin-film transistor (TR4) may transmit the driving voltage (Vdd) to the second thin-film transistor (TR2), or may block the driving voltage (Vdd) in accordance with the emission control signal (EM). When the fourth thin-film transistor (TR4) is turned on, a current may be supplied to the second thin-film transistor (TR2), whereby light may be emitted from the display element <NUM>.

The first thin-film transistor (TR1), the second thin-film transistor (TR2), the third thin-film transistor (TR3) and the fourth thin-film transistor (TR4) shown in <FIG> may be substantially similar in structure to any one among the thin-film transistors <NUM>, <NUM>, <NUM>, and <NUM> shown in <FIG>, <FIG>.

The pixel driving circuit (PDC) according to another embodiment of the present disclosure may be formed in various structures in addition to the above-described structure. For example, the pixel driving circuit (PDC) may include five or more thin-film transistors.

Claim 1:
A thin-film transistor (<NUM>, <NUM>, <NUM>, <NUM>, TR1, TR2, TR3, TR4), comprising:
a semiconductor layer (<NUM>, A1, A2) comprising:
a first oxide semiconductor layer (<NUM>) comprising gallium, wherein the first oxide semiconductor layer is configured to serve as a supporting layer for supporting a second oxide semiconductor layer (<NUM>);
the second oxide semiconductor layer (<NUM>), wherein the second oxide semiconductor layer is configured to serve as a channel layer; and
a silicon semiconductor layer (<NUM>) between the first oxide semiconductor layer and the second oxide semiconductor layer such that the first oxide semiconductor layer (<NUM>) contacts a first surface of the silicon semiconductor layer (<NUM>) and the second oxide semiconductor layer (<NUM>) contacts a second surface of the silicon semiconductor layer (<NUM>) opposite to the first surface, wherein the silicon semiconductor layer is configured to function as a light-shielding layer and/or an electron-interrupting layer; and
a gate electrode (<NUM>, G1, G2) spaced apart from the semiconductor layer and partially overlapping at least a part of the semiconductor layer,
wherein a concentration of gallium in the first oxide semiconductor layer (<NUM>) is higher than a concentration of gallium in the second oxide semiconductor layer (<NUM>).