Patent Description:
One or more embodiments can be applied advantageously to semiconductor devices for the automotive and consumer mass market.

A so-called insulated metal substrate (IMS) is frequently used in lieu of a conventional printed circuit board (PCB) as an insulated metal card (IMC), for applications - in the automotive sector, for instance - where high thermal power is desired to be dissipated by a semiconductor device package.

It is noted that a package such as a QFN (Quad-Flat No-lead) module on IMS may exhibit a high coefficient of thermal expansion - CTE and produce high stresses transmitted to QFN module solder joint.

A thin organic layer is not enough to relieve stress.

As a result, large QFN modules (7x7 mm or 10x10 mm, for example) may fail to meet reliability criteria (solder joint failure at BLR/thermal cycle or Thermal Shocks and Card Bending).

This suggests that QFP (Quad Flat Package) modules should be used in the place of QFN modules, which in turn may result in a larger space undesirably occupied on the board.

By way of general background art, document <CIT> discloses a semiconductor package that includes a lead frame including a chip mounting portion and a terminal portion. A semiconductor chip is mounted on the chip mounting portion and connected to the terminal portion, with a through groove penetrating the terminal portion from one surface on a side of the semiconductor chip to another surface in a thickness direction of the terminal portion, a lid portion covering an end portion of the through groove on the side of the semiconductor chip, and a resin portion sealing the semiconductor chip, wherein the another surface of the terminal portion and a side surface of the terminal portion facing an outside of the semiconductor package are coated by a plating film.

Additionally, document <CIT> discloses a process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions. The process envisages depositing in the separation regions beads of conductive soldering material so as to join together wire-bonding contacting areas corresponding to adjacent pads; fixing the devices to the respective pads; and carrying out a thermal process designed to sinter or re-flow the beads of conductive soldering material into soldered beads.

Document <CIT> discloses a lead frame on which a polyimide resin is coated is used as a coating resin on the surface of an internal lead except the back surface of a tab and a bonding area in advance. The polyimide resin having good bondability is coated on the package resin and a lead frame having low affinity to effectively prevent a separation from occurring in the boundary between the tab and the resin due to a heating cycle applied to the package and a crack from occurring in the vicinity of the back surface of the tab.

Neither of these documents properly addresses issues related to the fact that a package such as a QFN (Quad-Flat No-lead) module on IMS may exhibit a high coefficient of thermal expansion and produce high stresses transmitted to QFN module solder joint.

An object of one or more embodiments is to contribute in addressing the issues discussed in the foregoing.

According to one or more embodiments, such an object can be achieved by means of a method having the features set forth in the claims that follow.

One or more embodiments may relate to a corresponding semiconductor product.

The claims are an integral part of the technical teaching on the embodiments as provided herein.

One or more embodiments may involve a QFN manufacturing method that facilitates increased lead flexibility.

In one or more embodiments a low elasticity modulus mass is interposed between leads and molding at lead tips.

One or more embodiments facilitate using large QFN packages (10x10 mm, for instance) on an insulated metal substrate - IMS.

Those of skill in the art will otherwise appreciate that, while particularly advantageous results can be achieved in connection with QFN packages, the embodiments as discussed herein are not limited to use in connection with QFN packages.

It will be appreciated that, for the sake of simplicity and ease of explanation, the various figures may not be drawn to a same scale.

Reference to "an embodiment" or "one embodiment" within the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment.

It will be appreciated that, unless the context indicates otherwise, like parts or elements are indicated throughout the figures with like reference symbols, and a detailed description will not be repeated for each and every figure for brevity.

A possible drawback encountered with QFN (Quad-Flat No-lead) modules when used in connections with insulated metal cards (IMCs) is related with card materials. The desire of achieving a high thermal power dissipation involves using thick cards of, e.g., copper with a thin layer of dielectric.

<FIG> is exemplary of such an arrangement including a QFN package <NUM> mounted on an IMC <NUM> having a layered structure including a base copper layer (<NUM> H1/<NUM>) <NUM>, a dielectric layer <NUM>, a top copper layer <NUM> and a solder mask <NUM> into which a bond pad BP is formed to facilitate the provision of a solder joint <NUM> for the package <NUM>.

Such a thick copper card inevitably exhibits a high coefficient of thermal expansion (CTE) and high stresses transmitted to the solder joint <NUM> with the QFN package <NUM>. The thin organic layer <NUM> is not enough to relieve stress.

For instance, results board level reliability (BLR) simulation done on a QFN 7x7 module shows a possible lifetime drop to a maximum of <NUM> cycles in comparison with <NUM> cycles for a QFN 7x7 on a FR4 multilayer board.

An approach to address these issues may involve using Thin Quad Flat Package (TQFP) modules with flexible contacts capable of relieving thermomechanical stresses.

Another approach may involve using copper cards with a thicker PCB interposer to relieve stress.

These approaches are not exempt from drawbacks. For instance:.

By referring now to <FIG>, one or more embodiments may involve providing (in a semiconductor device package such as <NUM>) a half-etched leadframe <NUM>.

The designation leadframe (or lead frame) is currently used (see, for instance, the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame which provides (at a die pad or paddle, 12A) support for a semiconductor chip or die as well as electrical leads 12B to couple the semiconductor chip or die to other electrical components or contacts.

Essentially, a leadframe <NUM> comprises an array of electrically-conductive formations (leads) 12B which from a peripheral location extend inwardly in the direction of the semiconductor chip or die, thus forming an array of electrically-conductive formations from the die pad 12A having at least one semiconductor chip or die attached thereon.

It will be otherwise appreciated that the specification "No-leads" as applied to a QFN package is not in contradiction to the provision therein of a leadframe including leads: in fact, a key feature of a QFN package lies in that the leads therein do not protrude radially from the package, so that the (quad) package has "no leads" protruding therefrom.

As visible in the enlarged partial view of <FIG>, in one or more embodiments the external leads 12B in the leadframe have slots 120B formed therein near their distal ends. These slots 120B may be provided during formation of the leadframe <NUM> from a sheet or reel of material such as copper via a conventional etching process.

Adopting current language in etching technology, the slots 120B may be referred to as being "half-etched" in the leadframe material. However, this does not necessarily imply that the slots 120B have a depth equal to half the thickness of the leadframe <NUM>.

Also, it will be appreciated that figures from <FIG> onwards may refer to manufacturing simultaneously plural devices <NUM> which are finally separated in a "singulation" step.

Semiconductor devices such as <NUM> comprise, in a manner known per se to those of skill in the art, one or more semiconductor chips or dice <NUM> arranged (attached, via a die attach material) on the die pads 12A of the leadframe <NUM> as exemplified in <FIG>.

Electrical coupling of the leads 12B in the leadframe <NUM> with the semiconductor chip or die <NUM> may be via wires forming a wire-bonding pattern <NUM> around the chips or dice <NUM>.

A device package may then be completed by an insulating encapsulation <NUM> formed by molding a compound such as an epoxy resin on the leadframe <NUM> and the semiconductor chip(s) <NUM> attached thereon (plus the wire bonding pattern <NUM>).

In one or more embodiments, such step or act as illustrated in <FIG> is preceded by the step or act illustrated in <FIG> and <FIG>, wherein a low elastic modulus (LEM) material <NUM> is dispensed into the slots 120B.

The elastic modulus (or modulus of elasticity) is a physical entity - measured in Nm-<NUM> or Pa, even if megapascals (MPa or N/mm<NUM>) or gigapascals (GPa or kN/mm<NUM>) are frequently used - which indicates the resistance of an object or a substance to being deformed (elastically, that is, non-permanently) in response to a stress applied to it. A stiffer material will thus have a higher elastic modulus and a softer material will thus have a lower elastic modulus.

The modified polycarbamin acid derivate material available under the commercial designation DELO DUALBOND BS3770 with DELO DUALBOND BS3770 DELO Industrie Klebstoffe GmbH & Co. KGaA of Gewerbegebiet Schöffelding, DELO-Allee <NUM>, <NUM> Windach, Germany - (see delo-adhesives. com) and having a Young's modulus of 2MPa (Rheometer|<NUM> <NUM> mW/cm<NUM> |<NUM>|Plus|<NUM>|<NUM>) was found to be adequate for use as a resilient material <NUM> in one or more embodiments.

Other materials exhibiting similar performance and, more generally, other materials that the person skilled in the art would regard as resilient materials having a low elastic modulus (that is, easy deformability under stress) in the context of use considered herein can be used satisfactorily in the embodiments.

Examples of possible alternative materials include the material designated Master Bond Supreme <NUM> HT Epoxy Insulation Adhesive available with Master Bond Inc. of Hackensack, NJ <NUM> USA (see masterbond. com) or the material designated Dymax 9037F Acrylated Insulant Adhesive available with Dymax Corporation of Torrington, CT <NUM> USA (see dymax.

Materials as discussed above can be adequately applied at the slots 120B, via a dispensing needle as indicated at N in <FIG>, and then cured, via UV curing for instance.

As illustrated in <FIG>, the material <NUM> can be dispensed with a thickness <NUM>-<NUM> and provide a sort of cushion or lining covering the front or top surface, and possibly the sides - see <FIG>, to be discussed later, of the leads 12B (at their distal ends).

As illustrated in <FIG> an insulating encapsulation <NUM> is formed by molding a compound such as an epoxy resin on the leadframe <NUM> and the semiconductor chip(s) <NUM> attached thereon (plus the wire bonding pattern <NUM>) and the material <NUM>.

If not completed earlier, polymerization (curing) of the material <NUM> can be completed (at a temperature of, e.g., <NUM>) together with curing of the insulating encapsulation <NUM>.

<FIG> is exemplary of (otherwise conventional) back etching applied at BE and of the possibility (see <FIG>) for a bottom plated area <NUM> at the leads 12B stopping before the top bonding area.

<FIG> is exemplary of a conventional singulation step (performed via a blade B, for instance) leading to the formation of individual (e.g., QFN) packages <NUM>.

Those of skill in the art will otherwise appreciate that the sequence of steps or acts of <FIG> is merely exemplary in so far as:.

Various such possible alternatives of embodiments will now be discussed in connection with <FIG>, and <FIG>, plus <FIG> and <FIG> and <FIG>.

For the sake of simplicity and ease of understanding, unless the context indicates otherwise, parts or elements like parts or elements already discussed in connection with <FIG> are indicated in the following figures with like reference symbols, and a detailed description will not be repeated for brevity.

For simplicity, certain details possibly illustrated in <FIG> may not be reproduced in the following figures.

The steps exemplified in <FIG> contemplate a half cut 12C formed (in manner know per se - <FIG>) at the back or bottom side of the lead frame <NUM> (this is exemplified only at the central portion of the figures for simplicity) followed by (likewise conventional - <FIG>) plating at 120C so that, after singulation (<FIG>), plated solderwettable lead flanks become available as visible in <FIG>
<FIG> are exemplary of the possibility of applying one or more embodiments to an (otherwise conventional) QFN-with-tape manufacturing process.

Those of skill in the art will again appreciate that the sequence of steps or acts of <FIG> is merely exemplary in so far as:.

As exemplified in <FIG> and <FIG>, the low elastic module material <NUM> embedded between the leads 12B and the molding material <NUM> effectively relieves thermomechanical stresses due to the (high) CTE mismatch between the module <NUM> and the substrate <NUM> (an IMS-card, for instance) which would otherwise be transferred to the solder joints <NUM>.

The low elastic module material <NUM> facilitates a sort of sealing effect of the modules thanks to improved adhesion to the substrate material (e.g., copper), which may be further improved by chemical compatibility with the mold material <NUM> and/or design of the slots 120B.

In this latter respect, <FIG> are exemplary of the possibility of causing the "soft" cushion or pad provided by the low elastic module material <NUM> to extend:.

Normalized solder life simulation results for temperature cycles TC (-<NUM>/+125C) based on a Finite Element Analysis (FEA) modelling have shown that packaging with flexible contacts as exemplified in <FIG> may provide nearly <NUM>% and <NUM>% increase in solder life when applied to a QFNmr 10x10mm package.

It will be noted that the leads 12B have distal ends facing away from the die pad with the recessed portions 120B provided at front (upper) surfaces of these distal ends. The aforesaid (blind) recessed portions at the front (upper) surfaces are in contrast to the through grooves visible, for instance in <CIT>.

Resilient material <NUM> is thus filled at said recessed portions 120B so that the resilient material <NUM> facilitates flexibility of the leads at such distal ends.

Advantageously, the recessed portions 120B are at a distance from the extremities of the distal ends of the leads in the array 12B.

That is, the recessed portions 120B do not extend to the (terminal) extremities of the leads <NUM>. The leads <NUM> thus have non-recessed terminal ends with the (blind, not through) recessed portions providing a (flexible) section of reduced thickness.

As noted, the recessed portions may comprise half-etched portions of the leadframe that can be formed at the same time as other half-etched portion of the leadframe.

The resilient material fills the recessed portions.

The recessed portions do not extend to the end of the distal portions of the leads (so that end singulation does not occur through recessed portions).

A flexible (intermediate) portion in the lead contact region is thus formed, with the leads having their full thickness at their terminal extremities.

Claim 1:
A method, comprising:
arranging at least one semiconductor chip (<NUM>) on a surface of a leadframe (<NUM>) wherein the at least one semiconductor chip (<NUM>) is arranged at a die pad (12A) of the leadframe (<NUM>) and the leadframe has an array of electrically-conductive leads (12B) around the die pad (12A), the leads in the array having distal ends facing away from the die pad (12A) as well as recessed portions (120B) in front surfaces of said distal ends of the leads in the array (12B), wherein said recessed portions (120B) are at a distance from the extremities of said distal ends of the leads in the array (12B),
forming (N) resilient material (<NUM>) at said recessed portions (120B) at the distal ends of the leads in the array (12B), wherein the resilient material (<NUM>) fills the recessed portions (120B), and
molding onto the at least one semiconductor chip (<NUM>) arranged on the leadframe (<NUM>) an insulating encapsulation (<NUM>) of the at least one semiconductor chip (<NUM>) arranged on the leadframe, wherein the resilient material (<NUM>) is sandwiched between the insulating encapsulation (<NUM>) and the distal ends of the leads in the array (12B) at said recessed portions (120B), wherein the resilient material (<NUM>) facilitates flexibility of said leads (12B) at said distal ends.