Patent Description:
Integrated circuits typically comprise power rails (for example for VSS and VDD supply voltage distribution). Traditionally, power rails have been encapsulated within a back-end-of-line (BEOL) interconnect structure located above the level of the active physical devices (such as transistors). Current advanced technology nodes may in contrast be provided with a "buried" power rail (BPR) which may be formed in a trench in the substrate, such that the power rail may be located at a level below the active physical devices. Burying power rails enables the cross-section of the power rails to be increased (for example reducing the line resistance) without occupying valuable space in the BEOL interconnect structure. Additionally, BPRs may facilitate design of reduced track height standard cells by allowing neighbouring circuit cells to share a common (e.g. increased cross-section) BPR.

A BPR and a source/drain body of an adjacent horizontal channel transistor (e.g. a finFET, or a nanosheet- or nanowire-FET) may be interconnected by forming a via-like metal contact on the source/drain body and extending therefrom to land on the BPR. This interconnect is also known as a via-to-BPR (VBPR). Forming the metal contact typically involves high aspect ratio etching through inter-layer dielectric, liner layers and/or capping layers within narrow contact trenches between gates, with entailing challenges during metal filling. The further aggressive scaling and drive towards high aspect ratio device structures make these issues increasingly challenging.

<CIT> discloses an integrated circuit device including an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

In light of the above, it is an objective to provide an improved method for interconnecting a buried wiring line and a source/drain body, at least partly addressing the afore-mentioned challenges. Further and alternative objectives may be understood from the following.

<The invention is defined by the claims. There> is provided a method for interconnecting a buried wiring line and a source/drain body, the method comprising:.

The method facilitates forming of an interconnection between a buried wiring line and a source/drain body. The forming of the via hole and the metal via therein may be referred to as a metal via "prefill", wherein the interconnection is completed by subsequently forming the source/drain contact on the prefill and the source/drain body. The method thereby reduces the required depth for the contact opening since the contact opening need only extend to a sufficient depth for exposing the upper via portion of the metal via / prefill. This additionally facilitates a void free metal filling as less height needs to be filled during the source/drain contact formation.

The term "fin structure" as used herein refers to a fin-shaped structure with a longitudinal dimension oriented in a horizontal direction (e.g. a "first" horizontal direction) along the substrate and protruding vertically therefrom.

The fin structure may comprise a single channel layer integrally formed with the fin structure (wherein the fin structure may be a single fin-shaped semiconductor body). The fin structure may however also comprise one or more horizontally oriented channel layers stacked over a base portion of the fin structure protruding from the substrate.

Relative spatial terms such as "vertical", "upper", "lower", "top", "bottom", "above", "under", "below", are herein to be understood as denoting locations or orientations within a frame of reference of the substrate. In particular, the terms may be understood as locations or orientations along a normal direction to the substrate (i.e. a main plane of extension of the substrate). Correspondingly, terms such as "lateral" and "horizontal" are to be understood as locations or orientations parallel to the substrate (i.e. parallel to the main plane of extension of the substrate).

In some embodiments, the buried wiring line may be a BPR. The method is however applicable to also other types of buried wiring lines.

In some embodiments, the metal via may be formed such that the upper via portion of the metal via protrudes above the via hole in the first insulating layer structure. The metal via may thus be formed with a height exceeding a depth of the via hole in the first insulating layer structure. This further reduces the required depth for the contact opening and the metal fill during the source/drain contact formation.

The temporary process layer may in the following be referred to using the label "first", to distinguish from a "second" temporary process layer discussed below.

Using a temporary process layer to form the via hole may facilitate the via hole formation since the material of the temporary process layer may be selected with regard to its etching and masking properties and with less regard to its suitability as a layer in the final device, e.g. its insulating properties. For instance, the source/drain body may in some embodiments be covered by a dielectric etch stop layer (liner), wherein the via opening may be formed by etching the first temporary process layer selectively to the etch stop layer.

In some embodiments, the via opening may be formed to be displaced (horizontally) relative the source/drain body such that the source/drain body is separated from the via opening by a remaining portion of the first temporary process layer.

The first temporary process layer may be an organic material layer, such as an organic planarizing layer (e.g. an organic spin-on-layer). An organic / carbon-based material may be etched with a high selectivity to typical interlayer dielectrics (ILD) and dielectric etch stop layers.

The method may further comprise forming an contact etch stop layer (liner) covering the first insulating layer structure and the source/drain body, wherein the method further may comprise opening the etch stop layer over the buried wiring line prior to forming the via hole, and opening the etch stop layer on the source/drain body prior to forming the source/drain contact.

In some embodiments, the metal via may be formed by selective deposition of metal in the via hole in the first insulating layer structure.

This enables a bottom-up deposition of metal in the via hole, allowing void-free filling of the via hole and a precise control of a height dimension of the metal via. Additionally, the need for a subsequent metal recess or etch-back is obviated since the metal is deposited selectively at the position of the via hole. The deposition of metal may be stopped when the upper via portion protrudes by a desired amount above the via hole.

Forming the metal comprises depositing metal in the via hole and in the via opening, and wherein the method further comprises removing the first temporary process layer subsequent to forming the metal via.

The metal is accordingly deposited without first removing the first temporary process layer. This enables forming of a metal via / prefill with an increased vertical dimension since the via opening, in addition to the via hole, may act as a template for the metal deposition. As may be appreciated, this reduces the required depth of the contact opening subsequently formed in the second insulating layer structure. The metal deposition may be a selective deposition (i.e. bottom-up) as discussed above, or a top-down deposition followed by a metal recess to remove overburden metal (i.e. deposited outside the via opening).

The metal via is formed such that the upper portion protrudes above a level of the source/drain body.

In some embodiments, the method may further comprise, prior to forming the second insulating layer structure:.

The contact opening may hence be formed in a tone-inverted fashion, wherein the dummy contact block may be replaced with the source/drain contact (e.g. a "replacement metal contact process").

The second temporary process layer may be an organic material layer. An organic / carbon-based material may be etched with a high selectivity to typical ILDs and dielectric etch stop layers. The second temporary process layer may for instance be an organic planarizing layer.

In some embodiments the second insulating layer structure may be formed to embed and cover the dummy contact block; wherein a sacrificial gate may be formed across the at least one channel layer prior to forming the source/drain body, and wherein the method may further comprise, while the second insulating layer structure covers the dummy contact block, replacing the sacrificial gate with a metal gate.

The dummy contact block (which as mentioned above may be organic and hence be sensitive to elevated process temperatures) may accordingly be masked from the process conditions (typically involving elevated process temperatures) during the replacement metal gate (RMG) process. Forming the metal gate prior to forming the source/drain contact may additionally reduce a risk of a degraded source/drain contact-body interface.

In some embodiments, the second insulating layer structure may be formed to cover the upper via portion and the source/drain body, and wherein the contact opening may be formed by etching the second insulating layer structure to expose the source/drain body and the upper via portion.

In some embodiments, a sacrificial gate may be formed across the at least one channel layer prior to forming the source/drain body, and wherein the method may further comprise replacing the sacrificial gate with a metal gate subsequent to forming the second insulating layer structure and prior to forming the contact opening. The source/drain body and the metal via may accordingly be masked from the process conditions (typically involving elevated process temperatures) during the replacement metal gate (RMG) process. Forming the metal gate prior to forming the source/drain contact may additionally reduce a risk of a degraded source/drain contact-body interface.

The above, as well as additional objects, features and advantages, may be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings.

Hereafter follows a detailed description of embodiments of a method for forming a semiconductor device, more specifically for forming an interconnection between a buried wiring line and a source/drain body, e.g. a source/drain body of a FET transistor device. The FET transistor device may comprise at least one horizontally oriented channel layer. Examples of applicable FET devices include the finFET device (e.g. comprising a single fin-shaped channel layer) and the horizontal/lateral nanowire- or nanosheet-channel FET device (e.g. comprising a number of vertically stacked nanowires or nanosheets). While reference in the following will be made mainly to a buried wiring line in the form of a BPR, it is to be noted that the method is equally applicable to also other types of buried wiring lines, such as buried interconnect lines, buried routing lines, or buried inter-cell signal lines for memory or logic applications.

<FIG> show a preliminary device structure <NUM> wherein <FIG> is a cross-section taken along line A-A' indicated in the top-down view of <FIG>. The device structure <NUM> comprises a substrate <NUM>. The substrate <NUM> may be a conventional semiconductor substrate suitable for CMOS processing. The substrate <NUM> may be a single-layered semiconductor substrate, for instance formed by a bulk substrate such as a Si substrate, a germanium (Ge) substrate or a silicon-germanium (SiGe) substrate. A multi-layered / composite substrate is however also possible, such as an epitaxially grown semiconductor layer on a bulk substrate, or a semiconductor-on-insulator (SOI) substrate, such as a Si-on-insulator substrate, a Ge-on-insulator substrate, or a SiGe-on-insulator substrate. The X- and Y-directions indicated in the figures designate first and second horizontal directions, mutually perpendicular to each other and parallel to a main plane of the substrate <NUM>. The Z-direction designate a vertical direction normal to the main plane of the substrate <NUM>.

The device structure <NUM> further comprises a number of fin structures <NUM> formed on the substrate <NUM>. Each fin structure <NUM> forms an elongated fin-shaped structure with a longitudinal dimension oriented in Y-direction and protruding in the Z-direction from the substrate <NUM>. A width dimension of each fin structure <NUM> is oriented in the X-direction. The fin structures <NUM> extend in parallel to each other and are spaced apart in the X-direction. While reference in the following mainly will be made to one fin structure <NUM>, the method to be disclosed may be applied in parallel to any number of fin structures. The fin structures <NUM> may be formed e.g. by etching trenches in a semiconductor layer of a channel material (e.g. for forming a finFET device), or in a semiconductor layer stack of sacrificial layers of a sacrificial material and channel layers of a channel material, arranged alternatingly with each other (e.g. for forming a nanowire- or nanosheet-channel FET device). The pattern of fin structures may be etched back or cut at positions where no fin structures are desired, e.g. as exemplified in region C of <FIG>. After forming the fin structures <NUM>, the fin structures <NUM> may be surrounded by shallowtrench isolation (STI) <NUM>, e.g. by filling the trenches with insulating material (e.g. an ILD such as SiO<NUM>) and etching back the same to a desired height. Techniques for fin patterning and STI formation are per se well known in the art and will hence not be further discussed herein.

The device structure <NUM> further comprises a buried wiring line, hereinafter exemplified as a BPR <NUM>. The BPR <NUM> is formed in a trench <NUM> extending alongside the fin structure <NUM> in the Y-direction. The BPR <NUM> may be formed by etching the trench <NUM> through the STI <NUM> and into the substrate <NUM>. The BPR <NUM> may then be formed in the trench <NUM> by filling the trench <NUM> with one or more metals (e.g. a barrier metal and a fill metal) and thereafter etching back the metal to form the BPR <NUM> with a desired height (along the Z-direction) in the trench <NUM>. The BPR <NUM> may then be capped by an insulating layer structure <NUM> (i.e. a "first insulating layer structure") comprising one or more insulating layers, for instance a nitride liner (e.g. SiN) and an interlayer dielectric (e.g. SiO<NUM>). For conciseness, combined structure of the STI <NUM> and the first insulating layer structure <NUM> may in the following be denoted "lower isolation layer structure <NUM>".

As indicated in <FIG>, additional BPRs may be formed in parallel to the BPR <NUM>, alongside another one of the fin structures. While in the illustrated method, the BPR <NUM> is formed with a height such that the BPR <NUM> protrudes into a lower thickness portion of the STI <NUM>, this is merely an example and it is also possible to form the BPR <NUM> with a smaller height such that the BPR <NUM> is embedded only within a thickness portion of the substrate <NUM>.

The device structure <NUM> further comprises a number of sacrificial gate structures <NUM> formed across the fin structure(s) <NUM>. Each sacrificial gate structure <NUM> extends in the X-direction and overlaps a respective channel region of each fin structure <NUM>. The sacrificial gate structure(s) <NUM> may be formed after forming the BPR(s) <NUM>. Each sacrificial gate structure <NUM> may comprise a sacrificial gate or sacrificial gate body formed by depositing a sacrificial gate layer, e.g. of a-Si, and then patterning the sacrificial gate body therein using single- or multiple-patterning techniques, as per se is known in the art. The sacrificial gate body may be provided with a gate spacer <NUM> (e.g. an conformally deposited nitride such as SiN deposited by atomic layer deposition, ALD) formed to extend along sidewalls of each sacrificial gate body. Furthermore, a gate cap (omitted from <FIG>), e.g. of a hard mask material, may be provided on top of the sacrificial gate body. Further details of forming sacrificial gate structures is per se well known in the art and will hence not be further discussed herein.

The device structure <NUM> further comprises source/drain bodies <NUM> for each FET device, formed by epitaxy at either side of each sacrificial gate structure <NUM> (and channel region). The source/drain bodies <NUM> may be doped in accordance with the intended conductivity type of the FET devices to be formed, e.g. using in-situ doping techniques. Each source/drain body <NUM> is formed on, i.e. in contact with, the one or more channel layer of a respective fin structure <NUM>. Source/drain bodies <NUM> on neighboring fin structures <NUM> may as shown be formed to merge to form common source/drain bodies for the neighboring fin structures <NUM>.

The source/drain bodies <NUM> may as shown subsequently be covered by an etch stop layer <NUM>, e.g. a dielectric etch stop layer or liner (e.g. an ALD-deposited SiN) for protecting the source/drain bodies <NUM> during subsequent processing steps.

Prior to the epitaxy, the fin structures <NUM> may be recessed by etching back the fin structures <NUM> in a top-down direction (e.g. negative Z) at either side of each sacrificial gate structure, while using the sacrificial gate structure as an etch mask. Each fin structure <NUM> may thereby be partitioned into a plurality of fin structure portions, each comprising one or more channel layer portions preserved in the channel region underneath each sacrificial gate <NUM>. The etch back may thus define end surfaces of the (respective) channel layer(s) at either side of each sacrificial gate structure <NUM> on which the source/drain bodies <NUM> may be grown. The sacrificial gate structures <NUM> may prior to the fin recess and the forming of the source/drain bodies <NUM> be surrounded by ILD (e.g. SiO<NUM>). Source/drain trenches may then be etched in the ILD at locations where fin structures <NUM> are to be recessed and the source/drain bodies <NUM> are to be formed. Accordingly, the view in <FIG> may correspond to a cross section taken along a source/drain trench.

<FIG> illustrate process steps for forming a via hole <NUM> in the first insulating layer structure <NUM> to expose an upper surface of the buried wiring line <NUM>.

In <FIG> a (first) temporary process layer <NUM> has been formed over the lower isolation layer structure <NUM> and the source/drain bodies <NUM>. The temporary process layer <NUM> may be an organic material layer such as an organic planarizing layer deposited by chemical vapor deposition (CVD) or by spin-on-deposition (e.g. a spin-on-carbon layer). More generally, the temporary process layer <NUM> may however be formed by any material facilitating the patterning process to be described below and presenting a sufficient etch contrast with respect to the materials of the lower isolation layer structure <NUM>.

A photoresist layer <NUM> and one or more underlayers <NUM> (e.g. a spin-on-glass layer) have further been formed over the temporary process layer <NUM>. An opening <NUM> has been patterned in the photoresist layer <NUM>, e.g. by lithography. In <FIG>, the opening <NUM> has been transferred by etching into the temporary process layer <NUM> (thus forming via opening <NUM> therein) and subsequently into the first insulating layer structure <NUM>, thereby forming the via hole <NUM>. The etching may be stopped on the upper surface of the BPR <NUM>. An anisotropic etching process, for instance a dry etching process such as reactive ion etching (RIE), may be used. As may be appreciated, the transfer of the opening <NUM> into the first insulating layer structure <NUM> may comprise a sequence of etch steps with different etching chemistries suitable for etching the different materials of e.g. the temporary process layer <NUM>, the etch stop layer <NUM> and of the first insulating layer structure <NUM>.

In <FIG>, the temporary process layer <NUM> has been removed from the device structure <NUM>, e.g. using a suitable etching process, such as a plasmabased dry etch.

In the following, various ways to form the via will be described. <FIG> illustrate formation of the via wherein the metal via is formed such that the upper portion protrudes above a level of the source/drain body, as defined in the claims. <FIG> may be seen as examples useful for understanding the invention. Process steps discussed in conjunction with <FIG> may be combined with the process steps of <FIG>, as understood by the skilled person.

In <FIG> a metal via / "prefill" <NUM> has been formed in the via hole <NUM>, on the exposed upper surface of the BPR <NUM>. The metal via <NUM> may be formed by area selective deposition (ASD) of metal in the via hole <NUM>. Various processes for ASD are possible.

In one example, ASD of prefill metal by ALD or electro-less deposition (ELD) adapted to seed from the exposed metal surface of the BPR <NUM> may be used. Examples of suitable prefill metals include e.g. Ru or Co. ELD, or synonymously electro-less plating or auto-catalytic plating, enables a "bottom-up" deposition of a metal on a metal surface (e.g. the BPR <NUM>), wherein the metal surface acts as an electrode and catalyst for a reduction of metal ions to form the metal material. The metal ions may be dissolved in a solution, e.g. an aqueous solution comprising a reducing agent.

In another example, for improved area selectivity, the metal deposition may be preceded by a functionalization of the exposed surface of the BPR <NUM> and/or sidewalls of the via hole <NUM>. For instance, a seed layer may be deposited selectively by ALD on the exposed surface of the BPR <NUM>, to facilitate subsequent seeding of ALD- or ELD-deposited prefill metal. Alternatively, a treatment step such as a short etch step (e.g. a H<NUM> plasma etch) may be applied to increase a hydrophilicity or hydrophobicity of the exposed surface of the BPR <NUM> and/or sidewalls of the via hole <NUM> relative exposed surfaces outside the via hole <NUM>. Alternative a treatment step including a selective deposition of a self-assembled monolayer (SAM) on the BPR <NUM> and/or sidewalls of the via hole <NUM> may be applied. For example, the SAM may have a hydrophobic tail group and a head group adapted to bond to the exposed surface of the BPR <NUM> and/or the sidewalls of the via hole <NUM>, but not to exposed surfaces outside the via hole <NUM> (e.g. the etch stop layer <NUM>. The tail group may meanwhile be adapted to act as a seed for a subsequent deposition of the prefill metal (e.g. by ALD).

The metal via <NUM> may as shown be formed with a height exceeding a depth (as seen along the Z-direction) of the via hole <NUM>, such that an upper via portion 136a of the metal via <NUM> protrudes above the via hole <NUM> and the first insulating layer structure <NUM> (as well an upper surface of the lower isolation layer structure <NUM>). This is however merely an option and it is also possible to form the metal via <NUM> to only partially fill a depth of the via hole <NUM>.

While in the figures, a metal via <NUM> is formed only on a BPR <NUM> adjacent one source/drain body <NUM>, it is to be understood that a corresponding metal via may be formed adjacent any number of source/drain bodies in parallel.

In <FIG>, a (second) insulating layer structure <NUM> has been formed over the device structure <NUM>, to cover the metal via <NUM> and the lower isolation layer structure <NUM> and the source/drain bodies <NUM> (and the etch stop layer <NUM> if present). The insulating layer structure <NUM> may be formed by a layer of ILD (e.g. SiO<NUM> deposited by CVD), but may also be a composite layer structure of two or more insulating layers of different materials such as a dielectric liner (e.g. a nitride such as SiN) followed by a layer of ILD (e.g. SiO<NUM>). As may be understood from the afore-going discussion, the sacrificial gate structures <NUM> shown in <FIG> may hence again be surrounded by ILD (e.g. the source/drain trenches may be re-filled). The insulating layer structure <NUM> may further be subjected to chemical mechanical polishing (CMP) to planarize an upper surface of the insulating layer structure <NUM>.

In <FIG> a contact opening <NUM> has been formed in the (second) insulating layer structure <NUM> by etching to expose the source/drain body <NUM> and the upper via portion 136a of the metal via <NUM>. An additional short etch step (e.g. an isotropic nitride etch) may be applied to open the etch stop layer <NUM> on the source/drain bodies <NUM>, if present. The contact opening <NUM> may be formed in a lithography-and-etching process, e.g. comprising lithographically defining a contact opening pattern in a resist layer, and transferring the pattern into lower layers of a lithographic layer stack, e.g. comprising a hard mask <NUM> and further an organic planarizing layer (e.g. spin-on-carbon) and a spin-on-glass layer (omitted from <FIG> for illustrational clarity). The contact opening pattern may subsequently be transferred into the insulating layer structure <NUM>. Any suitable conventional combination of etching processes (e.g. wet and/or dry) and etching chemistries may be used to form the contact opening <NUM>.

<FIG> show forming of a source/drain contact <NUM> in the contact opening <NUM>, on the upper via portion 136a and the source/drain body <NUM>, thereby interconnecting the BPR <NUM> and the source/drain body <NUM>.

The forming of the source/drain contact <NUM> may as depicted comprise depositing one or more contact metals in the contact opening <NUM>, such as a barrier metal <NUM> (e.g. TiN) and a contact fill metal <NUM> (e.g. W, Cu, Al) respectively deposited using e.g. ALD, CVD or physical vapor deposition (PVD). An overburden of contact metal may subsequently be removed by a planarization and/or metal etch back process, such as CMP.

The deposition of contact metal may be preceded by forming a contact silicide <NUM> on the source/drain bodies <NUM>. Silicide formation may be done using conventional techniques, e.g. by depositing a suitable metal (such as Ti) followed by anneal to trigger silicidation. After anneal, non-silicided metal may be removed by a metal etch (e.g. isotropic, wet or dry).

As shown in <FIG>, the contact formation may proceed by recessing the deposited contact metal to form a final source/drain contact <NUM> of a desired height.

The openings in the insulating layer structure <NUM> may as shown be filled or "plugged" with an insulating material, e.g. by an ILD such as CVD-deposited SiO<NUM>, thereby capping the source/drain contact <NUM> with insulating material. The insulating material may be deposited and then planarized, e.g. by CMP, to arrive at the device structure <NUM> in <FIG>.

As further shown in <FIG>, additional source/drain contacts <NUM> may be formed on source/drain bodies in adjacent contact openings. In the illustrated example, the source/drain contact <NUM> is however not formed in contact with any BPR but merely contacts the respective source/drain body. Accordingly, a source/drain contact <NUM> interconnecting a BPR <NUM> and a source/drain body <NUM> may be formed in parallel to a "conventional" source/drain contact <NUM> merely forming a contact for a source/drain body.

The method as set out above may further be supplemented with a replacement metal gate (RMG) process to replace the sacrificial gate bodies of the sacrificial gate structures <NUM> shown in <FIG> with functional gate stacks (e.g. comprising metal gates) in each channel region. The RMG process may be performed after the stage of the method shown in <FIG>, i.e. after forming (and planarizing) the (second) insulating layer structure <NUM> and prior to forming the contact opening <NUM>. <FIG> is a representative schematic top-down view of the device structure <NUM> at this stage of the method wherein, additionally, the sacrificial gate structures <NUM> (e.g. the gate cap and the sacrificial gate body) have been removed by etching, thereby forming gate trenches <NUM> in the insulating layer structure <NUM>, extending across and exposing the fin structure(s) <NUM> in the respective channel regions.

In <FIG>, a functional gate stack <NUM> has been deposited in the gate trenches <NUM>, to overlap the respective channel regions. The gate stack <NUM> may comprise a gate dielectric layer and a gate metal stack comprising one or more effective a work function metal (WFM) layers and a gate fill metal. The gate dielectric layer may be formed of a conventional a high-k dielectric e.g. HfO<NUM>, HfSiO, LaO, AlO or ZrO. The WFM layer may be formed of one or more effective WFMs (e.g. an n-type WFM such as TiAl or TiAlC and/or a p-type WFM such as TiN or TaN). The gate fill metal may be formed of conventional gate fill metals e.g. W, Al, Co or Ru. The gate dielectric layer and the first WFM may be deposited by ALD. The gate fill metal may for instance be deposited by CVD or PVD. The gate stack may after deposition be recessed using a metal etch-back process to provide the functional gate stacks <NUM> with a desired vertical dimension and then be covered by a gate cap, e.g. of a nitride such as SiN. The method may thereafter proceed in accordance with <FIG> and onwards by forming the contact opening <NUM>.

As will be appreciated by a skilled person, an overall method for forming a FET device may include additional process steps in dependence on particular type of device that is to be formed. For instance, a method for forming a horizontal/lateral nanowire- or nanosheet-channel FET device (e.g. comprising a number of vertically stacked nanowires or nanosheets) with a wrap-around gate or gate-all-around may additionally comprise a "channel release process". In a channel release process, sacrificial layers arranged alternatingly with channel layers of each fin structure <NUM> may be removed in the channel regions by etching, within the gate trenches <NUM>, the sacrificial material selectively to the channel material. Thereby the channel layers may be "released", such that the functional gate stack <NUM> may be subsequently deposited in each gate trench <NUM> to surround the channel layers.

Furthermore, to facilitate among the "channel release", process steps may be performed for forming so-called "inner spacers" on end surfaces of the sacrificial layers, after fin recess and prior to source/drain body epitaxy. Inner spacer formation generally comprises, as per se is known in the art, laterally recessing (i.e. etching back along the +Y and -Y directions) the sacrificial layers from both sides of each sacrificial gate <NUM> using an isotropic etching process selective to the sacrificial material, and filling the recesses with an inner spacer material (e.g. an ALD-deposited oxide, nitride or carbide). Spacer material deposited outside the recesses may be removed by a subsequent etch step. The inner spacers may thus, among others, act as an etch mask for the source/drain bodies <NUM> during the channel release.

<FIG> schematically illustrate a method for interconnecting a buried wiring line and a source/drain body.

The method initially proceeds as shown and disclosed with reference to <FIG> above. The device structure <NUM> shown in <FIG> hence corresponds to the device structure <NUM> shown in <FIG>, however, in contrast to the preceding method, after forming the metal via <NUM>, the method proceeds by forming a (second) temporary process layer <NUM> covering the upper via portion 136a and the source/drain body <NUM> (or source/drain bodies in the source/drain trench). The second temporary process layer <NUM> may be like the first temporary process layer <NUM> be an organic material layer, such as a spin-on-carbon layer.

In <FIG>, the second temporary process layer <NUM> has been patterned to form a dummy contact block <NUM> on the upper via portion 136a and the source/drain body <NUM>. The second temporary process layer <NUM> may like the first temporary process layer <NUM> be patterned using a lithography and etching process. As shown in <FIG>, a photoresist layer <NUM> and one or more underlayers <NUM> (e.g. a spin-on-glass layer) may be formed over the second temporary process layer <NUM>. The contact block pattern may be patterned in the photoresist layer <NUM>, e.g. by lithography, and subsequently transferred into the underlayer(s) <NUM> and then the second temporary process layer <NUM>.

In <FIG>, a second insulating layer structure <NUM> corresponding to the second insulating layer structure <NUM> (e.g. an ILD layer such as SiO<NUM>) has been formed to embed the dummy contact block <NUM>. The second insulating layer structure <NUM> has further been planarized and/or etched back to expose an upper surface of the dummy contact clock <NUM>.

In <FIG>, a contact opening <NUM> corresponding to the contact opening <NUM> has been formed by removing the dummy contact block <NUM> selectively to the second insulating layer structure <NUM>, thereby exposing the upper via portion 136a and the source/drain body <NUM> (or the etch stop layer <NUM> thereon, if present).

<FIG> shows the device structure <NUM> after completing the forming of the source/drain contact <NUM> and capping the same with insulating material <NUM>.

Similar to the preceding method, the present method may further be supplemented with an RMG process, e.g. after completing the forming of the source/drain contact <NUM>. The RMG process may otherwise proceed in a corresponding manner as set out above and will hence not be repeated here.

<FIG> schematically illustrate a method for interconnecting a buried wiring line and a source/drain body according to a further embodiment. The method as shown in <FIG> differs from the method shown in <FIG> in that after forming the dummy contact block <NUM> as shown in <FIG>, the dummy contact block <NUM> is recessed (e.g. by an anisotropic top-down etch back) to form a recessed dummy contact block <NUM>' on the upper via portion 136a and the source/drain body <NUM>. <FIG> shows the resulting device structure <NUM>'.

In <FIG>, a second insulating layer structure <NUM>' corresponding to the second insulating layer structure <NUM> has subsequently been formed to embed and cover the recessed dummy contact block <NUM>'.

The method may thereafter proceed by forming an opening in the second insulating layer structure to expose an upper surface of the recessed dummy contact block <NUM>' (e.g. using a lithography-and-etching process). The dummy contact block <NUM>' may then be removed to form a corresponding to contact opening <NUM> in <FIG>, and forming a source/drain contact corresponding to <NUM> therein as shown in <FIG>. The contact opening may be formed by removing the recessed dummy contact block <NUM>' selectively to the second insulating layer structure by etching from the opening in the second insulating layer structure <NUM>'.

One merit of this approach is that an amount of dummy contact block material which needs to be removed to form the contact opening may be reduced. This may reduce the exposure of e.g. the upper via portion 136a and the source/drain body <NUM> to the etching chemistry.

Additionally, an RMG process may be performed prior to removing the dummy contact block <NUM>' and forming the source/drain contact. This since the recessed dummy contact block <NUM>' may be covered and thus masked by the second insulating layer structure <NUM> during the RMG process.

<FIG> schematically illustrate a method for interconnecting a buried wiring line and a source/drain body according to the invention.

The method proceeds as shown and disclosed with reference to <FIG> above. The device structure <NUM> shown in <FIG> hence corresponds to the device structure <NUM> shown in <FIG>, however, differs in that the metal via <NUM> is deposited after forming the via opening in the temporary process layer <NUM> and prior to removing the same. That is, the metal via <NUM> may hence be formed in the via hole <NUM> in the insulating layer structure <NUM> and in the via opening <NUM> in the first sacrificial process layer <NUM>. The upper via portion 336a of the metal via <NUM> is hence formed in the via opening <NUM>. In particular, as shown in <FIG>, the metal via <NUM> may be formed with a height such that the upper portion 336a protrudes above a level of the source/drain body <NUM>. The metal via <NUM> may be formed using any of the above-described ASD-techniques. However it is also possible to form the metal via <NUM> by filling the via hole <NUM> and the via opening <NUM> with metal by a (top-down) metal deposition, and thereafter removing overburden metal by a planarization and/or metal etch back process, such as CMP. The first temporary process layer <NUM> may subsequently be removed, thereby arriving at the device structure <NUM> show in <FIG>.

The method may thereafter proceed as shown in <FIG> (corresponding to <FIG>), <FIG> (corresponding to <FIG>), and <FIG> (corresponding to <FIG>). The "extended height metal via <NUM>" is however also compatible with the dummy contact formation approaches disclosed in connection with <FIG> and <FIG>, respectively, wherein the respective discussions of the RMG process applies correspondingly.

Claim 1:
A method for interconnecting a buried wiring line (<NUM>) and a source/drain body (<NUM>), the method comprising:
forming a fin structure (<NUM>) on a substrate (<NUM>), the fin structure comprising at least one channel layer;
forming a buried wiring line in a trench (<NUM>) extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure (<NUM>);
forming a source/drain body on the at least one channel layer by epitaxy;
forming a via hole (<NUM>) in the first insulating layer structure to expose an upper surface of the buried wiring line;
forming a metal via (<NUM>) in the via hole:
forming a second insulating layer structure (<NUM>) over the first insulating layer structure, wherein a contact opening (<NUM>) is defined in the second insulating layer structure to expose the source/drain body and an upper via portion (336a) of the metal via;
forming a source/drain contact (<NUM>) in the contact opening, on the upper via portion and the source/drain body, thereby interconnecting the buried wiring line and the source/drain body; the method characterized by
forming a first temporary process layer (<NUM>) over the first insulating layer structure and the source/drain body;
forming a via opening (<NUM>) in the first temporary process layer by etching
wherein the via hole in the first insulating layer structure subsequently is formed by transferring the via opening into the first insulating layer structure by etching, and wherein the first temporary process layer is removed prior to forming the second insulating layer structure; and
wherein forming the metal comprises depositing metal in the via hole and in the via opening, and wherein the method further comprises removing the first temporary process layer subsequent to forming the metal via; and
wherein the metal via is formed such that the upper portion protrudes above a level of the source/drain body.