Patent Description:
Compared to a conventional class-AB amplifier, a class-G amplifier may be configured to dynamically adjust a power voltage and greatly improve power efficiency and is widely utilized in audio applications. Please refer to <FIG>, which is a structural diagram of a conventional class-G amplifier circuit <NUM> with a digital input. The conventional class-G amplifier circuit <NUM> includes a digital front end circuit <NUM>, a digital-to-analog converter (DAC) <NUM>, a class-AB amplifier <NUM>, a charge-pump control logic circuit <NUM> and a charge pump circuit <NUM>. The charge-pump control logic circuit <NUM> adjusts an output voltage of the charge pump circuit <NUM> according to an input signal, such that the charge pump circuit <NUM> may transform among different voltage modes.

To avoid larger inrush currents generated when transforming modes, before the conventional charge pump circuit <NUM> is transformed from a <NUM>/3VDD mode to a VDD mode, the conventional charge pump circuit <NUM> enters a soft ramp-up mode, an output voltage of the charge pump circuit <NUM> is charged by a smaller fixed current. After the charge pump circuit <NUM> is charged for a fixed time period, the charge pump circuit <NUM> enters the VDD mode. When the charge pump circuit <NUM> is transformed from the VDD mode to the <NUM>/3VDD mode, a three-phase soft switching is utilized for transforming the output voltage to the <NUM>/3VDD mode. However, a charging time period of the conventional charge pump circuit <NUM> is fixed during the soft ramp-up mode. If the charging period is not long enough, the charge pump circuit <NUM> enters the VDD mode and huge inrush currents are generated, which causes distortions when the class-G amplifier circuit is applied on the audio and generates pop noises. In contrast, if the charging period is too long, a ramp-up process of the output voltage is too slow and causes clipping of the output voltage of the class-G amplifier circuit and distortions. In addition, the charging time of the output voltage of the charge pump circuit <NUM> is easily affected by an output device and loading current, which makes digital control logic of the class-G amplifier circuit difficult. Moreover, a time period needed for the transformation to the <NUM>/3VDD is directly related to the loading current and output capacitors. When the time period is too short, the output voltage of the charge pump circuit <NUM> cannot be reduced to the <NUM>/3VDD mode. In contrast, if the time period is too long, the output voltage is lower than <NUM>/3VDD due to a huge impedance caused by the soft switching of the charge pump circuit <NUM>, which generates huge inrush currents.

application No. <CIT> provides an signal amplifying circuit and associated methods to generate positive and negative output voltages together spanning a voltage approximately equal to an input voltage circuit. application No. <CIT> provides a multi-mode voltage regulation with feedback to regulate a voltage with multiple selectable voltage regulator (VR) modes, such as a power gate VR mode, a switched-capacitor VR (SCVR) mode and a low drop-out (LDO) mode. <NPL>" discloses a feed forward circuit to enhance the performance of the LDO regulator's PSRR for delay matching in DPWM by changing supply voltage of delay elements.

Therefore, how to provide a charge pump circuit capable of minimizing the inrush currents during the mode transformations, so as to avoid circumstances of distortions caused by the pop noises or clipping and optimize the efficiency of the amplifier, has been an object in the industry.

It is therefore an object of the present application to provide a charge pump circuit and controlling method to avoid circumstances of distortion caused by the generated pop noises or clipping and optimize the efficiency of the class-G amplifier circuit.

To solve the technical problems mentioned above, the present application provides a digital control circuit, configured to receive a up digital signal and a down digital signal, and adjust a first output voltage to a voltage level of an input voltage and adjust an second output voltage to a ground voltage level according to the up digital signal and the down digital signal, comprises a digital-to-analog converter (DAC), configured to generate a corresponding up reference voltage and a corresponding down reference voltage according to the up digital signal and the down digital signal; and a voltage follower, comprising a plurality of operational amplifiers and a plurality of transistor switches, configured to lock the first output voltage and the second output voltage according to the up reference voltage and the down reference voltage; wherein the up digital signal and the down digital signal are varied with time.

An embodiment of the present application provides a charge pump circuit, comprises a digital control circuit, coupled to a switch module of the charge pump, configured to receive a up digital signal and a down digital signal, and adjust a first output voltage to a voltage level of an input voltage and adjust an second output voltage to a ground voltage level according to the up digital signal and the down digital signal, comprises a digital-to-analog converter (DAC), configured to generate a corresponding up reference voltage and a corresponding down reference voltage according to the up digital signal and the down digital signal; and a voltage follower, comprising a plurality of operational amplifiers and a plurality of transistor switches, configured to lock the first output voltage and the second output voltage according to the up reference voltage and the down reference voltage.

Preferably, the charge pump circuit further comprises a balance release circuit, coupled to the digital control circuit and the switch module, configured to maintain a common mode voltage of the first output voltage and the second output voltage at a fixed value through a common mode feedback loop, when the first output voltage and the second output voltage is discharging or charging; wherein the common mode voltage is half of the input voltage; wherein the common mode feedback loop includes a plurality of operational amplifiers and a plurality of resistors.

Preferably, the switch module, comprises a plurality of switches, a plurality of output capacitors, a loading resistor and a soft ramp-up switch, and is configured to generate the first output voltage and the second output voltage according to the input voltage and control the plurality of switches and the soft ramp-up switch to transform the first output voltage and the second output voltage with a first mode, a ramp-up mode, a second mode and a balance release mode.

Preferably, when the charge pump circuit is transformed from the first mode to the ramp-up mode, the first output voltage is adjusted to the voltage level of the input voltage according to the up reference voltage and the second output voltage is adjusted to the ground voltage level according to the down reference voltage.

Preferably, when the charge pump circuit is transformed from the ramp-up mode to the second mode, the plurality of transistor switches of the digital control circuit are turned on to connect the input voltage and the ground voltage level to enter the second mode.

Preferably, the first output voltage and the second output voltage are only related to the up reference voltage and the down reference voltage.

Preferably, the digital control circuit is connected to the first output voltage and the second output voltage.

Preferably, when the charge pump circuit is transformed from the second mode to the balance release mode, the first output voltage is discharged and the second output voltage is charged by the loading resistor and the plurality of capacitors, the common mode voltage of the first output voltage and the second output voltage is maintained at the fixed value by the common mode feedback loop of the balance release circuit.

Preferably, when the charge pump circuit is transformed from the second mode to the balance release mode, a switching operation of the plurality of switches of the switch module is stopped, and a switch of the common mode feedback loop is turned on.

Preferably, the fixed value is half of the input voltage.

Preferably, when the first output voltage and the second output voltage are completely discharged, the charge pump circuit is transformed from the balance release mode to the first mode.

Preferably, wherein when the first output voltage is determined smaller than <NUM>/<NUM> of the input voltage or when the second output voltage is determined larger than <NUM>/<NUM> of the input voltage by a logic circuit, a voltage level of a logic signal is changed; the charge pump circuit is transformed from the balance release mode to the first mode according to a variation of the voltage level of the logic signal; and a charge pump controller is notified by the logic signal.

Preferably, when the charge pump circuit is transformed from the balance release mode to the first mode, the first output voltage is <NUM>/<NUM> of the input voltage and the second output voltage HPVSS is <NUM>/<NUM> of the input voltage, so as to achieve a stable state voltage of the first mode.

An embodiment of the present application provides a controlling method for a charge pump circuit, comprises receiving a up digital signal and a down digital signal; converting the up digital signal and the down digital signal to a up reference voltage and a down reference voltage; adjusting a first output voltage to a voltage level of an input voltage and an second output voltage to a ground voltage level according to the up reference voltage and the down reference voltage; turning on a plurality of transistor switches of the digital control circuit of the charge pump circuit to connect the input voltage and a ground voltage level; discharging the first output voltage and charging the second output voltage; and maintaining a common mode voltage of the first output voltage and the second output voltage at a fixed value by a common mode feedback loop.

The charge pump circuit of the present application locks the output voltage of the charge pump circuit according to the input signal to reduce inrush currents during the mode transformation, so as to avoid circumstances of distortions caused by pop noises or clipping generated by the class-G amplifier circuit. In addition, since the energy discharged by the charge pump circuit is completely consumed on the loading resistor in the balance release mode, which is more capable of optimizing the efficiency of the class-G amplifier circuit compared with the soft switching mode of the conventional charge pump circuit.

In order to make the objects, technical solutions and advantages of the present application become more apparent, the following relies on the accompanying drawings and embodiments to describe the present application in further detail. It should be understood that the specific embodiments described herein are only for explaining the present application and are not intended to limit the present application.

Please refer to <FIG>, which is a schematic diagram of a charge pump circuit <NUM> according to an embodiment of the present application. The charge pump circuit <NUM> includes a switch module <NUM>, a digital control circuit <NUM> and a balance release circuit <NUM>. The switch module <NUM> is configured to generate a first output voltage HPVDD and a second output voltage HPVSS according to an input voltage VDD, which includes switches S1, S2, S3, S4, S5, S6, output capacitors CUP, CDN, a loading resistor RL and a soft ramp-up switch S1soft. The digital control circuit <NUM> is configured to lock the first output voltage HPVDD and the second output voltage HPVSS. The balance release circuit <NUM> is configured to maintain a common mode voltage of the first output voltage and the second output voltage at Vcm through a common mode feedback loop, when the first output voltage HPVDD and the second output voltage HPVSS is discharging or charging. A charge pump controller <NUM> is configured to output an up digital signal DUP and a down digital signal DDN, and adjust the first output voltage HPVDD to a voltage level of the input voltage VDD, and adjust the second output voltage HPVSS to a voltage level of GND. In addition, the charge pump controller <NUM> is configured to determine whether a mode transformation process of the charge pump circuit <NUM> is completed or not according to a logic signal DNOK. Therefore, the charge pump circuit <NUM> of the present application locks the first output voltage HPVDD and the second output voltage HPVSS of the switch module <NUM> by the digital control circuit <NUM> and the balance release circuit <NUM>, so as to reduce inrush currents generated during the mode transformation of the charge pump circuit <NUM> and consume all discharged energy on the loading resistor to increase the power efficiency of the charge pump circuit <NUM>.

In detail, the digital control circuit <NUM> includes a digital-to-analog converter DAC and a voltage follower Vf, wherein the digital-to-analog converter DAC is configured to generate a corresponding up reference voltage VRUP and a corresponding down reference voltage VRDN according to the up digital signal DUP and the down digital signal DDN. The voltage follower Vf includes switches S7, S8, S9, an operational amplifier Op and transistor switches MUP, MDN to lock the first output voltage HPVDD and the second output voltage HPVSS respectively according to the up reference voltage VRUP and the down reference voltage VRDN. Notably, since the up reference voltage VRUP is generated by the up digital signal DUP, and the down reference voltage VRDN is generated by the down digital signal DDN, variation speeds of the first output voltage HPVDD and the second output voltage HPVSS are dynamically varied in time according to the input signal of the class-G amplifier circuit <NUM>. That is, the first output voltage HPVDD is only related to the up reference voltage VRUP in an ascending process, and the second output voltage HPVSS is only related to the down reference voltage VRDN in a descending process, so as to avoid clipping of the class-G amplifier circuit <NUM> because the first output voltage HPVDD and the second output voltage HPVSS are incapable of varying in time. The balance release circuit <NUM> includes a logic circuit LC and the common mode feedback loop, wherein the common mode feedback loop includes a common mode operational amplifier OPcm, a switch SBR and a common mode resistor Rcm, so as to detect a common mode voltage Vcm when the first output voltage HPVDD and the second output voltage HPVSS are freely discharged or charged and maintain an average value of the first output voltage HPVDD and the second output voltage HPVSS at VDD/<NUM> by a feedback control. When the first output voltage HPVDD is smaller than <NUM>*VDD/<NUM> or when the second output voltage HPVSS is larger than VDD/<NUM>, which represents that the first output voltage HPVDD and the second output voltage HPVSS are completely discharged or charged, the logic signal DNOK of the balance release circuit <NUM> is changed from a low voltage level (DNOK=LOW) to a high voltage level (DNOK=HIGH) and the charge pump controller <NUM> is notified.

Regarding an operation method of the charge pump circuit <NUM>, please refer to <FIG>, which is a flow chart of a controlling method <NUM> according to an embodiment of the present application. The controlling method <NUM> includes the following steps:.

Step <NUM>: The charge pump circuit <NUM> is transformed from a first mode (<NUM>/3VDD mode) to a ramp-up mode and the first output voltage HPVDD is adjusted to the voltage level of the input voltage VDD according to the up reference voltage VRUP and the second output voltage HPVSS is adjusted to the ground voltage level according to the down reference voltage VRDN.

Step <NUM>: The charge pump circuit <NUM> is transformed from the ramp-up mode to a second mode (VDD mode), the transistor switches of the digital control circuit <NUM> are turned on to enter the second mode.

Step <NUM>: The charge pump circuit <NUM> is transformed from the second mode to a balance release mode, the loading resistor RL discharges the first output voltage HPVDD and charges the second output voltage HPVSS, and the common mode voltage Vcm of the first output voltage HPVDD and the second output voltage HPVSS is maintained by the common mode feedback loop of the balance release circuit <NUM>.

Step <NUM>: When a voltage level of the logic signal DNOK of the balance release circuit <NUM> is changed, the charge pump circuit <NUM> is transformed from the balance release mode to the first mode.

As can be known from the above controlling method <NUM>, the charge pump circuit <NUM> is configured to operate among the first mode, the ramp-up mode, the second mode and the balance release mode by the switch module <NUM>, the digital control circuit <NUM> and the balance release circuit <NUM>. Please refer to <FIG>, which is a schematic diagram of a mode transformation <NUM> of the charge pump circuit <NUM> according to an embodiment of the present application. As shown in <FIG>, the charge pump circuit <NUM> is transformed from the first mode to the ramp-up mode, from the ramp-up mode to the second mode and from the second mode to the balance release mode by the digital control, and transformed from the balance release mode to the first mode according to the logic signal DNOK (DNOK=HIGH).

In detail, the charge pump circuit <NUM> generates the first output voltage HPVDD and the second output voltage HPVSS with three different phases by switching the switches S1-S6 and the soft ramp-up switch S1soft of the switch module <NUM>. When the charge pump circuit <NUM> is going to perform the mode transformation, in step <NUM>, the switches S1-S6 are stopped switching to enter the ramp-up mode. In the meantime, the first output voltage HPVDD is adjusted to the voltage level of the input voltage VDD according to the up reference voltage VRUP, and the second output voltage HPVSS is adjusted to the ground voltage level GND according to the down reference voltage VRDN. Notably, since the up reference voltage VRUP is generated by the up digital signal DUP and the down reference voltage VRDN is generated by the down digital signal DDN, the variation speeds of the first output voltage HPVDD and the second output voltage HPVSS are dynamically varied in time with the input signal of the class-G amplifier circuit <NUM>.

In step <NUM>, when the charge pump circuit <NUM> is transformed from the ramp-up mode to the second mode, the transistor switches MUP, MDN are turned on to connect to the input voltage VDD and the ground voltage level GND and enter the second mode. In this step, the first output voltage HPVDD and the second output voltage HPVSS are only related to the up reference voltage VRUP and the down reference voltage VRDN. The up reference voltage VRUP and the down reference voltage VRDN are controlled by the up digital signal DUP and the down digital signal DDN of the charge pump controller <NUM>. Therefore, in step <NUM> of the mode transformation process, larger inrush currents caused by a huge voltage difference of loading resistor RL or bias of the output capacitors CUP, CDN would not be generated by the charge pump circuit <NUM>. In addition, since the digital control circuit <NUM> is connected to the first output voltage HPVDD and the second output voltage HPVSS, the digital control circuit <NUM> may precisely predict the first output voltage HPVDD and the second output voltage HPVSS of the switch module <NUM>. Therefore, based on the variation speed of the input signal (i.e. the up digital signal DUP and the down digital signal DDN) of the charge pump circuit <NUM>, the first output voltage HPVDD and the second output voltage HPVSS are adaptively changed in time, so as to reduce the inrush currents without clipping of the output of the class-G amplifier circuit <NUM>.

Then, in step <NUM>, the charge pump circuit <NUM> is transformed from the second mode to the balance release mode, the switching operation of the switches S1-S6 is stopped, and the switch SBR is turned on, such that the loading resistor RL and the capacitors CUP, CDN discharge the first output voltage HPVDD, and charge the second output voltage HPVSS. Then, the common mode voltage of the first output voltage HPVDD and the second output voltage HPVSS is maintained at Vcm (i.e. VDD/<NUM>)by the common mode feedback loop of the balance release circuit <NUM>.

Finally, in step <NUM>, when the first output voltage HPVDD is determined smaller than <NUM>*VDD/<NUM> or when the second output voltage HPVSS is determined larger than VDD/<NUM> by the logic circuit LC, the voltage level of the logic signal DNOK is changed. The charge pump circuit <NUM> is transformed from the balance release mode to the first mode according to the variation of the voltage level of the logic signal DNOK, e.g. from the low voltage level to the high voltage level, and the charge pump controller <NUM> is notified by the logic signal DNOK.

Since the energy stored in the capacitors CUP, CDN may be completely released on the loading resistor RL in step <NUM>, the efficiency of the class-G amplifier circuit <NUM> may be improved. In addition, when capacitance values of the capacitors CUP, CDN mismatch, the variation speeds of the first output voltage HPVDD and the second output voltage HPVSS when charging/discharging are not identical, which generates larger inrush currents when the charge pump circuit <NUM> is transformed to the first mode with only one (i.e. the first output voltage HPVDD or the second output voltage HPVSS) achieving a stable state voltage of the first mode. Therefore, in this embodiment, the common mode voltage of the first output voltage HPVDD and the second output voltage HPVSS is maintained at VDD/<NUM> by the feedback control of the common mode feedback circuit of the balance release circuit <NUM>. In this way, even if the capacitance values of the capacitors CUP, CDN mismatch, the stable state voltage of the first mode is achieved and the larger inrush currents are prevented when the charge pump circuit <NUM> is transformed from the balance release mode to the first mode, the first output voltage HPVDD is <NUM>*VDD/<NUM> and the second output voltage HPVSS is VDD/<NUM>.

Table <NUM> shows a state table of the switches (on/off) of the charge pump circuit <NUM> in different modes:.

Notably, the embodiments mentioned above are to briefly illustrate concepts of the present application, and those skilled in the art may make modifications thereto. For example, the switches mentioned above may be implemented by transistor switches or other switches, or the logic circuit may be implemented by other circuits with the same function and not limited thereto, which all belong to the scope of the present application. The invention is only limited by the appended claims.

Claim 1:
A charge pump circuit (<NUM>) for supplying power to a class-G amplifier, wherein the class-G amplifier comprises an input configured to receive a time-varying input signal (Input Signal), the charge pump (<NUM>) comprising:
a switch module (<NUM>) configured to generate a first output voltage (HPVDD) at a first output terminal of the charge pump circuit (<NUM>) and a second output voltage (HPVSS) at a second output terminal of the charge pump circuit (<NUM>) according to an input voltage (VDD), wherein said first and second output terminals are connectable to the class-G amplifier for supplying power;
a digital control circuit (<NUM>), coupled to the first output terminal of the charge pump circuit (<NUM>) and the second output terminal of the charge pump circuit (<NUM>), configured to receive an up digital signal (DUP) and a down digital signal (DDN), which are based on the input signal (Input Signal), and configured to adjust the first output voltage (HPVDD) to a voltage level of the input voltage (VDD) and adjust the second output voltage (HPVSS) to a ground voltage level according to the up digital signal (DUP) and the down digital signal (DDN) during a ramp-up mode in which the switch module (<NUM>) stopped switching, comprising:
a digital-to-analog converter (DAC), configured to generate a corresponding up reference voltage (VRUP) and a corresponding down reference voltage (VRDN) according to the up digital signal (DUP) and the down digital signal (DDN); and
a voltage follower (Vf), comprising a plurality of operational amplifiers (OP) and a plurality of transistor switches (MUP, MDN), configured to lock the first output voltage (HPVDD) and the second output voltage (HPVSS) according to the up reference voltage (VRUP) and the down reference voltage (VRDN);
wherein the plurality of transistor switches (MUP, MDN) are configured to directly receive the first output voltage (HPVDD) and the second output voltage (HPVSS) .