Patent Description:
Embodiments described herein relate generally to semiconductor device.

A semiconductor device having a semiconductor chip such as a metal oxide semiconductor field effect transistor (MOSFET) is used for applications such as power conversion. For example, when semiconductor device described above is a vertical MOSFET, a source electrode provided on an upper surface of a semiconductor chip is connected to a connector provided on MOSFET, for example.

Note that in the following description, the same members and the like are denoted by the same reference numerals, and description of members and the like once described is appropriately omitted.

In this specification, in order to illustrate the positional relationship of parts and the like, the upward direction of the drawings may be referred to as "upper", and the downward direction of the drawings may be referred to as "lower". Here, the terms "up" and "down" do not necessarily indicate a relationship with the direction of gravity.

Hereinafter, a case where a first conductivity type is n-type and a second conductivity type is p-type will be exemplified.

In the following description, notations of n+, n, n-, p+, p, and p- indicate a relative level of an impurity concentration of each of the conductivity types. That is, n+ indicates that an impurity concentration of n-type is relatively higher than n, and n- indicates that the impurity concentration of n-type is relatively lower than n. p+ indicates that an impurity concentration of p-type is relatively higher than p, and p- indicates that the impurity concentration of p-type is relatively lower than p. Note that n+ type and n- type may be simply referred to as n type, and p+ type and p- type may be simply referred to as p type.

The semiconductor device of the present embodiment includes a lead frame; a first bonding material provided on the lead frame; a semiconductor chip provided on the first bonding material, the semiconductor chip including a lower surface, an upper surface, a first electrode provided on the lower surface, the first electrode being connected to the first bonding material, a second electrode provided on the upper surface, and a plurality of electrode pads connected to the second electrode; a plurality of second bonding materials, each of the second bonding materials being provided on each of the electrode pads; and a first connector connected to at least one of the second bonding materials, wherein the second bonding material which is not connected to the first connector is not connected to a connector or a wire. The semiconductor device of the present embodiment includes a lead frame (<NUM>); a first bonding material (<NUM>) provided on the lead frame (<NUM>); a semiconductor chip (<NUM>) provided on the first bonding material (<NUM>), the semiconductor chip (<NUM>) including a lower surface (10a), an upper surface (10b), a first electrode (<NUM>) provided on the lower surface (10a), the first electrode (<NUM>) being connected to the first bonding material (<NUM>), a second electrode (<NUM>) provided on the upper surface (10b), and a plurality of first electrode pads (<NUM>) connected to the second electrode (<NUM>); a plurality of second bonding materials (<NUM>), each of the second bonding materials (<NUM>) being provided on each of the first electrode pads (<NUM>); and a first connector (<NUM>), wherein the second bonding materials (<NUM>) includes at least one third bonding material (20a) which is joined (bonded) to the first connector (<NUM>) and a fourth bonding material (20b) which is not connected to the first connector (<NUM>) or a wire (<NUM>), and wherein the first electrode pads (<NUM>) include at least one second electrode pad (17a) provided below the third bonding material (20a) and a third electrode pad (17b) provided below the fourth bonding material (20b).

The semiconductor device of the present embodiment includes a lead frame; a first bonding material provided on the lead frame; a semiconductor chip provided on the first bonding material, the semiconductor chip including a lower surface, an upper surface, a first electrode provided on the lower surface, the first electrode being connected to the first bonding material, a second electrode provided on the upper surface, and a plurality of electrode pads connected to the second electrode; a plurality of second bonding materials, each of the second bonding materials being provided on each of the electrode pads; a first connector connected to at least one of the second bonding materials; and a sealing resin provided on the second bonding material not being connected to the first connector. The semiconductor device of the present embodiment includes a lead frame (<NUM>); a first bonding material (<NUM>) provided on the lead frame (<NUM>); a semiconductor chip (<NUM>) provided on the first bonding material (<NUM>), the semiconductor chip (<NUM>) including a lower surface (10a), an upper surface (10b), a first electrode (<NUM>) provided on the lower surface (10a), the first electrode (<NUM>) being connected to the first bonding material (<NUM>), a second electrode (<NUM>) provided on the upper surface (10b), and a plurality of first electrode pads (<NUM>) connected to the second electrode (<NUM>); a plurality of second bonding materials (<NUM>), each of the second bonding materials (<NUM>) being provided on each of the first electrode pads (<NUM>); a first connector (<NUM>) connected to at least one of the second bonding materials (<NUM>); and a sealing resin (<NUM>), wherein the second bonding materials (<NUM>) further include a fourth bonding material (20b) which is not connected to the first connector (<NUM>), and wherein the sealing resin (<NUM>) is provided on the fourth bonding material (<NUM>).

<FIG> is a schematic top view of the semiconductor device <NUM> of the present embodiment. <FIG> is a schematic cross-sectional view of a main part of the semiconductor device <NUM> of the present embodiment. <FIG> is a schematic diagram of a cross section taken along line A-A' in <FIG>. <FIG> are schematic diagrams of a cross section taken along line A-A' in <FIG>. <FIG> is a schematic view of a A-A' cross-section in the vicinity of a second bonding material 20a. <FIG> is a schematic view of a A-A' cross-section in the vicinity of the second bonding material 20b. In <FIG>, a sealing resin <NUM> is also shown. In <FIG> and <FIG>, the sealing resin <NUM> is not illustrated.

The semiconductor device <NUM> of the present embodiment will be described using <FIG>, <FIG> and <FIG>.

A lead frame <NUM> is a member on which a semiconductor chip <NUM> is disposed and includes a conductive material such as Cu (copper). The lead frame <NUM> includes a first bed <NUM> and a first outer lead <NUM>. The first bed <NUM> includes a first bed surface <NUM>. The semiconductor chip <NUM> is provided on the first bed surface <NUM>. The first outer lead <NUM> is connected to the first bed <NUM>. The first outer lead <NUM> is used to connect the semiconductor chip <NUM> and an external circuit (not shown).

A first bonding material <NUM> is provided between the first bed surface <NUM> of the lead frame <NUM> and the semiconductor chip <NUM>. The first bonding material <NUM> is provided on the first bed surface <NUM> of the lead frame <NUM>. The first bonding material <NUM> joins a drain electrode (an example of a first electrode) <NUM> of the semiconductor chip <NUM> and the first bed surface <NUM>. For example, if the semiconductor chip <NUM> is provided with a MOSFET, the first bonding material <NUM> connects the drain electrode <NUM> of the semiconductor chip <NUM> and the first bed surface <NUM>.

The semiconductor chip <NUM> is provided on the first bonding material <NUM>. The semiconductor chip <NUM> has a lower surface 10a, and an upper surface 10b. Further, the semiconductor chip <NUM> includes the drain electrode <NUM> provided on the lower surface 10a, a source electrode (an example of a second electrode) <NUM> provided on the upper surface 10b, a plurality of electrode pads <NUM> provided on the source electrode <NUM>, and a third insulating film <NUM> provided on the source electrode <NUM>. The semiconductor chip <NUM> is, for example, a chip in which the vertical MOSFET or an IGBT(Insulated Gate Bipolar Transistor) or the like is provided on a semiconductor substrate such as an Si (silicon) substrate, an SiC (silicon carbide) substrate, a GaAs (gallium arsenide) substrate, or a GaN (gallium nitride) substrate.

Here, an X-direction, a Y-direction vertically intersecting with the X-direction, and a Z-direction vertically intersecting with the X-direction and the Y-direction are defined. It is assumed that the first bed surface <NUM>, the lower surface 10a and the upper surface 10b are provided parallel to the XY plane.

For example, if the semiconductor chip <NUM> is provided with a MOSFET, the source electrode <NUM> corresponds to a source electrode of such a MOSFET. The source electrode <NUM> includes, for example, Al (aluminum).

The third insulating film <NUM> is provided on the source electrode <NUM> of the semiconductor chip <NUM>. The third insulating film <NUM> is provided, for example, on an end of the semiconductor chip <NUM> and on an end of the source electrode <NUM>. The third insulating film <NUM> has an opening 13a and an opening 13b on the source electrode <NUM>. The opening 13a and the opening 13b pass through the third insulating film <NUM>. The third insulating film <NUM> includes, for example, an insulating material such as polyimide. Note that the number of the openings <NUM> is not limited to those shown in this embodiment.

The plurality of electrode pads <NUM> are provided in the opening <NUM> on the source electrode <NUM>. The plurality of electrode pads <NUM> are connected to the source electrode <NUM>. An electrode pad 17a is provided on the source electrode <NUM> in the opening 13a. An electrode pad 17b is provided on the source electrode <NUM> in the opening 13b. Note that the number of electrode pads <NUM> is not limited to those shown in this embodiment. The electrode pad <NUM> includes, for example, a first layer <NUM> including Ni (nickel) and a second layer <NUM> provided on the first layer <NUM> and including Au (gold). The configuration of the electrode pad <NUM> is not limited to that described above. For example, the electrode pad <NUM> may include an alloy of Ni and Au. For example, the electrode pad <NUM> may include a layer containing Ni, a layer containing Pd (palladium) provided on the layer containing Ni, and a layer containing Au provided on the layer containing Pd. Further, the electrode pad <NUM> may contain Cu, for example. Further, the electrode pad <NUM> may have, for example, layers including Cu. The electrode pad <NUM> is provided, for example, to increase the bonding strength between the source electrode <NUM> and the second bonding material <NUM>.

A plurality of second bonding materials <NUM> are provided on each of the electrode pads <NUM>. A second bonding material 20a is provided on the electrode pad 17a. A second bonding material 20b is provided on the electrode pad 17b. The second bonding material <NUM> may be referred to as a metal layer.

A first connector <NUM> includes a first end 51a and a second end 51b. The first connector <NUM> includes, for example, a conductive material such as Cu. Incidentally, the surface of the first connector <NUM> may be plated by a material containing, for example, Tin (Sn). The first end 51a is provided on the second bonding material 20a in the opening <NUM> and is connected to the second bonding material 20a. Thus, the first connector <NUM> is electrically connected to the electrode pad 17a via the second bonding material 20a. On the other hand, the first connector <NUM> is not connected to the second bonding material 20b. The first connector <NUM> is not connected to the electrode pad 17b via the second bonding material 20b. The second end 51b is provided on the second bed <NUM> and is connected to the second bed <NUM> using a third bonding material <NUM>. The first connector <NUM> is provided to extend in the Y-direction and straddles between the first post <NUM> and the lead frame <NUM>. Incidentally, even when the electrode pad 17a and the second bed <NUM> are connected using a wire instead of the first connector <NUM>, such wire is not connected to the second bonding material 20b. Further, such wire is not connected to the electrode pad 17a via the second bonding material 20b.

The sealing resin <NUM> is provided on the third insulating film <NUM> and the second bonding material <NUM> so as to cover at least the third insulating film <NUM>, the electrode pad <NUM>, and the second bonding material <NUM>. Here, as shown in <FIG>, around the second bonding material 20a, the sealing resin <NUM> is provided so as to cover around the second bonding material 20a and around the first end 51a of the first connector <NUM>. On the other hand, as shown in <FIG>, around the second bonding material 20b, the sealing resin <NUM> is provided so as to cover the second bonding material 20b. In this instance, the entire upper surface of the second bonding material 20b is in direct contact with the sealing resin <NUM>. The sealing resin <NUM> includes, for example, a resin such as an epoxy resin. Further, the sealing resin <NUM> may include a filler such as silica or alumina.

The first post <NUM> includes a second bed <NUM> and a second outer lead <NUM>. The first post <NUM> includes a conductive material such as Cu. The second outer lead <NUM> is used for connecting the semiconductor chip <NUM> and an external circuit (not shown).

A second post <NUM> includes a second bed <NUM> and a third outer lead <NUM>. The second post <NUM> includes a conductive material such as Cu. The third outer lead <NUM> is used for connecting the semiconductor chip <NUM> and an external circuit (not shown).

A third bonding material <NUM> is provided between the second bed <NUM> and the second end 51b. The third bonding material <NUM> connects the second bed <NUM> and the second end <NUM>.

A third connector <NUM> has a third end 61a and a fourth end 61b. The third connector <NUM> includes, for example, a conductive material such as Cu. Incidentally, the surface of the third connector <NUM> may be plated by a material containing, for example, Sn. The third end 61a is electrically connected to the semiconductor chip <NUM> via a fourth bonding material <NUM> provided on the semiconductor chip <NUM>. The fourth bonding material <NUM>, for example, is electrically connected to the gate electrode of MOSFET.

Incidentally, the first connector <NUM> and the third connector <NUM> can not be easily bent and are hard connectors, which are different from wires used for bonding.

A fifth bonding material <NUM> is provided between the second bed <NUM> and the fourth end 61b. The fifth bonding material <NUM> connects the second bed <NUM> and the fourth end 61b.

<FIG> is a schematic top view of a semiconductor device <NUM> according to another aspect of the present embodiment. Instead of the third connector <NUM>, a wire <NUM> is used. Instead of the third connector <NUM>, the wire <NUM> may be used. An end 63a of the wire <NUM> is connected to the fourth bonding material <NUM>. An end 63b of the wire <NUM> is connected to the fifth bonding material <NUM>.

As the first bonding material <NUM>, the second bonding material <NUM>, the third bonding material <NUM>, the fourth bonding material <NUM>, and the fifth bonding material <NUM>, for example, solder containing Pb (lead) and Sn (tin), solder containing Pb, Aq (silver), and Sn (tin), solder containing Sn and Sb (antimony), solder containing Au (gold) and Sn, solder containing Au and Si, or solder containing Au and Ge (germanium), Ag paste, ultrasonic solder, or the like can be preferably used.

Next, the operation and effects of semiconductor device of the present embodiment will be described.

<FIG> is a schematic top view of a semiconductor device <NUM> as a first comparative example of the present embodiment. The number of openings <NUM> and the number of second bonding material <NUM> are one. Then, the number of electrode pads <NUM> (not shown) in <FIG> is also one. Further, the area of the opening <NUM> in the XY-plane, the area of the second bonding material <NUM> in the XY-plane and the area of the electrode pad <NUM> in the XY-plane, respectively, are larger than those in the semiconductor device <NUM>.

The semiconductor chip <NUM> itself tends to warp due to internal stress of the semiconductor chip, for example, when the Z-direction is facing up. On the other hand, particularly when Ni is included in the electrode pad <NUM>, due to the tensile stresses of Ni, so as to cancel the internal stress of the semiconductor chip, it was possible to suppress the warpage of the semiconductor chip and a wafer. In this way, carrying trouble of the semiconductor chip and the wafer is prevented. Incidentally, for example, even when Cu is included in the electrode pad <NUM>, similarly, it was possible to prevent the carrying trouble of the semiconductor chip and the wafer.

In order to reduce the on-resistance of the semiconductor device as much as possible, the semiconductor device <NUM> uses a connector <NUM> having a larger volume than the connector <NUM> used in the semiconductor device <NUM>. The connector <NUM> includes an end 510a connected to the second bonding material <NUM> and an end 510b connected to the third bonding material <NUM>.

<FIG> is a schematic view of a cross section A-A' of the first comparative example of the semiconductor device <NUM> of the present embodiment. Arrows shown in the lead frame <NUM>, the semiconductor chip <NUM>, and the connector <NUM> schematically show a thermal expansion when the semiconductor device <NUM> is heated by reliability assessment such as temperature cycling test.

Generally, as compared with the thermal expansion coefficient of the semiconductor material such as Si used in semiconductor chip <NUM>, the thermal expansion coefficient of Cu or the like used in the lead frame <NUM> and the connector <NUM> is large. Therefore, due to the temperature rise of the semiconductor device <NUM>, the semiconductor chip <NUM> is stretched strongly in the XY plane. Therefore, by the reliability assessment such as thermal cycling test, the semiconductor chip <NUM> cracks, and it was sometimes impossible to achieve high reliability.

<FIG> is a schematic top view of a semiconductor device <NUM> as a second comparative example of the present embodiment. The number of openings <NUM> and the number of second bonding materials <NUM> are one. Then, the number of electrode pads <NUM> (not shown) in <FIG> is also one. Further, the area of the opening <NUM> in the XY-plane, the area of the second bonding material <NUM> in the XY-plane, and the area of the electrode pad <NUM> in the XY-plane, respectively, are smaller than that of the semiconductor device <NUM>.

To achieve high reliability, the volume of the connector <NUM> is reduced to less than the volume of the connector <NUM> of the semiconductor device <NUM> shown in <FIG> and <FIG>. Thus, at the time of temperature rise of the semiconductor chip <NUM>, it is suppressed that the semiconductor chip <NUM> is stretched strongly in the XY-plane. However, in such cases, with the use of the connector <NUM> having a small volume, the area of electrode pad <NUM> has become smaller. Therefore, the tensile stresses of the above electrode pad <NUM> is reduced, it was sometimes impossible to suppress warpage of the semiconductor chip and the wafer. Therefore, the semiconductor chip and the wafer may not be transported in some cases.

Therefore, the semiconductor device <NUM> of the present embodiment includes the first connector <NUM> which is electrically connected to at least one of the plurality of electrode pads <NUM>.

<FIG> is a schematic diagram showing the operation and effects of the semiconductor device <NUM> of the present embodiment. Arrows shown in the lead frame <NUM>, the semiconductor chip <NUM> and the connector <NUM> schematically show thermal expansion due to temperature rise of the semiconductor device <NUM>.

The reduced volume of the first connector <NUM> reduces the thermal expansion of the first connector <NUM>. Therefore, cracks in the semiconductor chip <NUM> are less likely to occur. Furthermore, by providing the second bonding material 20b which is not connected to the first connector <NUM> or the wire, warpage due to internal stress in the semiconductor chip or the wafer state can be canceled out by the tensile stresses of the electrode pad 17b provided below the second bonding material 20b. Therefore, it is possible to suppress warpage of semiconductor chip and the wafer state. This can prevent the carrying trouble of the semiconductor chip and the wafer. Therefore, it is possible to provide a semiconductor device <NUM> with improved reliability.

The second bonding material 20b which is not electrically connected to the first connector <NUM> is covered with the sealing resin <NUM>. Or, the second bonding material 20b which is not electrically connected to the first connector <NUM> is not connected to the connector or the wire.

According to the semiconductor device <NUM> of the present embodiment, the semiconductor device <NUM> with improved reliability can be provided.

The semiconductor device of the present embodiment is different from the semiconductor device of the first embodiment in that the semiconductor device of the present embodiment further includes a first semiconductor layer of first conductivity type provided on the first electrode, a first semiconductor region of second conductivity type provided on the first semiconductor layer, a second semiconductor region of first conductivity type provided on the first semiconductor region, the second electrode provided on the second semiconductor region, the second electrode being electrically connected to the second semiconductor region, and a third electrode provided in a first trench, the first trench reaching the first semiconductor layer from above the first semiconductor region, the third electrode facing the first semiconductor layer via a first insulating film, wherein the first trench extends in a first direction parallel to the upper surface, and wherein the electrode pad which is provided above the first trench and which is not connected to the first connector via the second bonding material extends in a second direction, the second direction is parallel to the upper surface and intersects the first direction. The semiconductor device of the present embodiment is different from the semiconductor device of the first embodiment in that the semiconductor device of the present embodiment further includes a first semiconductor layer (<NUM>) of first conductivity type provided on the first electrode (<NUM>), a first semiconductor region (<NUM>) of second conductivity type provided on the first semiconductor layer (<NUM>), a second semiconductor region (<NUM>) of first conductivity type provided on the first semiconductor region (<NUM>), and a third electrode (<NUM>) provided in a first trench (<NUM>), the first trench (<NUM>) reaching the first semiconductor layer (<NUM>) from above the first semiconductor region (<NUM>), the thi129second rd electrode (<NUM>) facing the first semiconductor layer (<NUM>) via a first insulating film (<NUM>), wherein the second electrode (<NUM>) is provided on the second semiconductor region (<NUM>) and is electrically connected to the second semiconductor region (<NUM>), wherein the first trench (<NUM>) extends in a first direction (Y-direction) parallel to the upper surface (10b), and wherein the third electrode pad (17b) is provided above the first trench (<NUM>) and extends in a second direction (X-direction) parallel to upper surface (10b) and intersecting the first direction (Y-direction). Here, description of the same content as that of semiconductor device of the first embodiment is omitted.

<FIG> is a schematic top view of a semiconductor device <NUM> of the present embodiment.

In <FIG>, the second bonding material <NUM> is not shown, and the electrode pad <NUM> provided below the second bonding material <NUM> is shown. The same shall apply to <FIG> and subsequent figures.

The first end 51a of the first connector <NUM> is connected to the electrode pad 17a<NUM> and the electrode pad 17a<NUM> via the second bonding material <NUM>. Further, the second bonding material 20a<NUM> and the second bonding material 20a<NUM> are provided on the electrode pad 17a<NUM> and the electrode pad 17a<NUM>. The first end 51a may be connected to one electrode pad.

Further, in the semiconductor device <NUM>, a plurality of electrode pads 17b is provided. Each electrode pad 17b extends in the X-direction.

<FIG> is a schematic cross-sectional view of a main part of a semiconductor device <NUM> of the present embodiment. Trench-type MOSFET is provided in the semiconductor chip <NUM> of semiconductor device <NUM>. Incidentally, in the semiconductor chip <NUM>, for example, trench-type IGBT may be provided.

The drain electrode <NUM> functions as MOSFET's drain electrode.

A drain layer <NUM> is provided on the drain electrode <NUM>. The drain layer <NUM> includes, for example, a n+ type semiconductor material.

A drift layer (an example of a first semiconductor layer) <NUM> is provided on the drain layer <NUM>. The drift layer <NUM> functions as a drift layer of the MOSFET. The drift layer <NUM> includes, for example, an n- type semiconductor material.

A base region (an example of a first semiconductor region) <NUM> is provided on the drift layer <NUM>. The base region <NUM> functions as a base of the MOSFET. The base region <NUM> is a region that forms a channel when a voltage is applied to the gate electrode <NUM> to be described later, allowing carriers to flow between the drain layer <NUM> and source region <NUM> to be described later. The base region <NUM> contains, for example, a p-type semiconductor material.

A source region (an example of a second semiconductor region) <NUM> is provided on the base region <NUM>. The source region <NUM> functions as a source of the MOSFET. Carriers flow between the source region <NUM> and the drain layer <NUM> when appropriate voltage is applied to the gate electrode <NUM>, which will be described later. The source region <NUM> includes, for example, a n+ type semiconductor material.

The contact region <NUM> is provided on the base region <NUM> and is electrically connected to the base region <NUM> and the source region <NUM>. The contact region <NUM> is provided in order to improve electrical contact of the base region <NUM> and the source region <NUM> with the source electrode <NUM>. The contact region <NUM> includes, for example, a p+ type semiconductor material.

A trench <NUM> is provided to reach the drift layer <NUM> from above the base region <NUM> and the source region <NUM>. The trench <NUM> extends in the back direction of the figure (Y-direction, which is an example of a first direction). In other words, the trench <NUM> extends in the Y direction perpendicular to the direction in which electrode pad 17b extends (X-direction, an example of a second direction).

A first insulating film <NUM> is provided in the trench <NUM>. For example, the first insulating film <NUM> is provided so as to cover a field plate electrode <NUM>, which will be described later. The first insulating film <NUM> is a field plate insulating film. For example, the first insulating film <NUM> is provided between the field plate electrode <NUM> and the gate electrode <NUM>. However, the form of the first insulating film <NUM> is not limited to this form. The first insulating film <NUM> includes, but is not limited to, SiOx (silicon oxide).

A fifth insulating film <NUM> is provided, in the trench <NUM>, between the base region <NUM> and the gate electrode <NUM> on the first insulating film <NUM> and between the interlayer insulating film <NUM> which will be described later and the source region <NUM> on the first insulating film <NUM>. The fifth insulating film <NUM> is a gate insulating film. The fifth insulating film <NUM> includes, but is not limited to, SiOx (silicon oxide).

The field plate electrode (an example of a third electrode) <NUM> is provided in the trench <NUM> so as to face the drift layer <NUM> via the first insulating film <NUM>. For example, the field plate electrode <NUM> is provided side by side with the drift layer <NUM>. Like the trench <NUM>, the field plate electrode <NUM> extends in the Y-direction. The field plate electrode <NUM>, for example, is provided to assist extending the depletion layer from the base region <NUM> to the drift layer <NUM>, and to increase the breakdown voltage.

The gate electrode <NUM> is provided above the field plate electrode <NUM>. The gate electrode <NUM> is provided between the plurality of base regions <NUM> via the fifth insulating films <NUM>. The gate electrode <NUM> extends in the Y-direction. The gate electrode <NUM> is an electrode that serves as a gate for MOSFET.

The interlayer insulating film <NUM> is provided above the source region <NUM>, on the gate electrode <NUM>, and on the fifth insulating film <NUM>. The interlayer insulating film <NUM> includes, for example, but is not limited to, SiOx.

The source electrode <NUM> is provided on the source region <NUM> and the contact region <NUM>, and is electrically connected to the source region <NUM> and the contact region <NUM>. The electrode pads <NUM> (not shown in <FIG>) are appropriately provided on the source electrode <NUM>.

<FIG> is a schematic cross-sectional view of a main part of semiconductor device <NUM> of the present embodiment. <FIG> is a schematic cross-sectional view for showing an example of a connection method of the field plate electrode <NUM> and the source electrode <NUM> and an example of a connection method of the gate electrode <NUM> and the gate metal <NUM>. For example, a schematic cross-sectional view of <FIG> corresponds to a schematic cross-sectional view in a D-D' cross-section of <FIG>.

The field plate electrode <NUM> has a portion extending in the Z-direction. The field plate electrode <NUM> is electrically connected to the source electrode <NUM> through a contact hole formed in the interlayer insulating film <NUM> by using the portion extending in the Z-direction.

The gate electrode <NUM> is electrically connected to the gate metal <NUM> through a contact hole provided in the interlayer insulating film <NUM>. For example, the gate metal <NUM> is provided below the fourth bonding material <NUM> (<FIG>) and is electrically connected to the fourth bonding material <NUM>.

Note that the portion <NUM> of gate electrode <NUM> extending in the Y-direction may be provided, for example, below between the electrode pad 17a<NUM> and the electrode pad 17a<NUM> (<FIG>). In such cases, the portion <NUM> of the gate electrode <NUM> extending in the Y-direction is an example of a conductive line, or a connection wiring connected to the gate electrode <NUM>. The plurality of second bonding materials (<NUM>) includes the plurality of third bonding materials (20a) joined to the first connector (<NUM>), and the semiconductor device further includes a connection wiring (<NUM>) connected to the third electrode (<NUM>) and provided below between the third bonding materials (20a).

The semiconductor chip <NUM> having the trench <NUM> has a higher internal stress and tends to warp in a plane perpendicular to the direction in which trench <NUM> extends. For example, as in semiconductor device <NUM>, when the trench <NUM> is extended in the Y-direction, the internal stress is higher in the XZ-plane than in the YZ-plane, and the semiconductor chip <NUM> tends to warp.

Therefore, in the semiconductor device <NUM>, electrode pad <NUM> is provided so as to extend in the X-direction. Thus, the warpage of the semiconductor chip <NUM> in the XZ plane can be suppressed better.

The semiconductor device <NUM> of the present embodiment can also provide the semiconductor device with improved reliability.

The semiconductor device of the present embodiment is different from the semiconductor device of the first and second embodiments in that the semiconductor device of the present embodiment further includes a fourth electrode provided in a second trench, the second trench reaching the first semiconductor layer from above the first semiconductor region, the fourth electrode facing the first semiconductor layer via a second insulating film, wherein the second trench extends in a third direction parallel to the upper surface and intersecting the first direction, and wherein the electrode pad which is provided above the second trench and which is not connected to the first connector via the second bonding material extends in a fourth direction, the fourth direction is parallel to the upper surface and intersects the third direction. The semiconductor device of the present embodiment is different from the semiconductor device of the first and second embodiments in that the semiconductor device of the present embodiment further includes a fourth electrode (<NUM>) provided in a second trench (<NUM>), the second trench (<NUM>) reaching the first semiconductor layer (<NUM>) from above the first semiconductor region (<NUM>), the fourth electrode (<NUM>) facing the first semiconductor layer (<NUM>) via a second insulating film (<NUM>), wherein the second trench (<NUM>) extends in a third direction (X-direction) parallel to the upper surface (10b) and intersecting the first direction (Y-direction), and wherein the first electrode pad (17c) provided above the second trench (<NUM>) and not electrically connected to the first connector (<NUM>) via the second bonding material (<NUM>) extend in a fourth direction (Y-direction), the fourth direction (Y-direction) is parallel to the upper surface (10b) and intersects the third direction (X-direction). Here, description of contents overlapping with the first and second embodiments is omitted.

In a first region 16a on the source electrode <NUM>, the electrode pads 17b extend in the X-direction (an example of a second direction). The trench <NUM> (an example of a first trench) below the electrode pads 17b, the first insulating film <NUM> (an example of a second insulating film) below the electrode pads 17b, and the field plate electrode <NUM> below the electrode pads 17b extend in the Y-direction (an example of a first direction).

In a second region 16b on the source electrode <NUM>, the electrode pads 17c extend in the Y-direction (an example of a fourth direction). The trench <NUM> (an example of a second trench) below the electrode pads 17c, the first insulating film <NUM> (an example of a second insulating film) below the electrode pads 17c, and the field plate electrode <NUM> (an example of the fourth electrode) below the electrode pads 17c extend in the X-direction (an example of a third direction).

Even when the direction in which trench <NUM> extends differs depending on the region, such as in semiconductor device <NUM>, the warpage of semiconductor chip <NUM> can be suppressed better.

The semiconductor device of the present embodiment is different from the semiconductor device of the first embodiment in that a plurality of electrode pads which are not connected to the first connector is provided. Here, descriptions of the same contents as those of the first to third embodiments are omitted.

<FIG> is a schematic top view of a semiconductor device <NUM> of the present embodiment. The electrode pad 17a is electrically connected to the first end 51a of the first connector <NUM>. On the other hand, an electrode pad 17b, an electrode pad 17c, an electrode pad 17d, an electrode pad 17e and an electrode pad 17f are not electrically connected to the first connector <NUM>.

The semiconductor device of the present example is different from the semiconductor device of the fourth embodiment in that it includes a second connector connected to a plurality of electrode pads, and the electrode pads are not connected to the first connector. Here, descriptions of the same contents as those of the first to fourth embodiments are omitted.

<FIG> is a schematic top view of a semiconductor device <NUM> of the present example. The second connector <NUM> is connected to the electrode pad 17b, the electrode pad 17c, the electrode pad 17d, the electrode pad 17e and the electrode pad 17f via the second bonding materials 20b, 20c, 20d, 20e and 20f (not illustrated). The semiconductor device <NUM> of the present embodiment includes a second connector (<NUM>) connected to the fourth bonding material (<NUM>) which is not connected to the first connector (<NUM>).

For example, when the first connector <NUM> is connected to the electrode pad 17a by reflow, when the melted bonding material is cured, the position of the first connector <NUM> may be shifted from the predetermined position and cured. By providing the second connector <NUM>, such a shift is suppressed.

The semiconductor device <NUM> of the present example can also provide the semiconductor device with improved reliability.

Fifth embodiment) <FIG> is a schematic top view of a semiconductor device <NUM> of the present embodiment. Descriptions overlapping with those of the first to fourth embodiments are omitted. The first connector <NUM> is connected to the electrode pad 17a and the electrode pad 17b. A connector and a wire are not connected to the electrode pad 17c and the electrode pad 17d.

<FIG> is a schematic top view of a semiconductor device <NUM> of the present example. The description of the contents overlapping with the first embodiment to the fifth embodiment is omitted. The difference from the semiconductor device <NUM> shown in <FIG> is that the second connector <NUM> is connected to the electrode pad 17c and the electrode pad 17d.

Claim 1:
A semiconductor device (<NUM>) comprising:
a lead frame (<NUM>);
a first bonding material (<NUM>) provided on the lead frame (<NUM>);
a semiconductor chip (<NUM>) provided on the first bonding material (<NUM>), the semiconductor chip (<NUM>) including
a lower surface (10a),
an upper surface (10b),
a first electrode (<NUM>) provided on the lower surface (10a), the first electrode (<NUM>) being connected to the first bonding material (<NUM>),
a second electrode (<NUM>) provided on the upper surface (10b), and
a plurality of electrode pads (<NUM>) connected to the second electrode (<NUM>);
a plurality of second bonding materials (<NUM>), each of the second bonding materials (<NUM>) being provided on each of the electrode pads (<NUM>);
a first connector (<NUM>) connected to at least one of the second bonding materials (<NUM>); and
a sealing resin (<NUM>) provided on the second bonding material (<NUM>) not being connected to the first connector (<NUM>).