Patent Description:
Image sensors commonly included in modern electronic devices are known. However, as electronic devices become smaller and the number of features in a single device increases, the available area in the electronic devices becomes increasingly scarce. The documents <CIT> and <CIT> are relevant for this invention.

The claimed invention proposes a unit pixel structure with the features of claim <NUM>. Further advantageous embodiments are disclosed in the dependent claims.

There is disclosed a unit pixel structure that comprises a semiconductive stack having a front side and a back side opposite the front side. The semiconductive stack comprises a first doped layer, a second doped layer disposed over the first doped layer, a third doped layer disposed over the second doped layer, and a fourth doped layer disposed over the third doped layer. A sensor well region is formed within the fourth doped layer, a floating diffusion region is formed within the fourth doped layer and separate from the sensor well region. A first gate structure is disposed over the semiconductive stack and positioned between the sensor well region and the floating diffusion region. A second gate structure is arranged around the floating diffusion region and extending through the third doped layer.

There is further disclosed that an area of the sensor well region may be less than an area of the second doped layer. In some embodiments, the area of the sensor well region is in a range of about <NUM>% to <NUM>% of the area of the second doped layer. The unit pixel structure may further comprise a pinning implant region formed over the sensor well region in the fourth doped layer. The first doped layer, the third doped layer, and the fourth doped layer are of a first dopant type, and the second doped layer is of a second dopant type, and the third doped layer has a heavier doping concentration than the fourth doped layer.

There is further disclosed that a doping concentration of the third doped layer may be about <NUM> to <NUM> times heavier than the fourth doped layer. The first dopant type may be p-type, and the second dopant type may be n-type. A thickness of the first doped layer may range from about <NUM> to <NUM>, a thickness of the second doped layer may range from about <NUM> to <NUM>, a thickness of the third doped layer may range from about <NUM> to <NUM>, and a thickness of the fourth doped layer may range from about <NUM> to <NUM>. The first gate structure may protrude from the semiconductive stack and the second gate structure has a height less than a height of protrusion of the first gate structure.

There is further disclosed that the second gate structure may be formed on a periphery of the semiconductive stack structure and laterally surround the semiconductive stack structure. The second gate structure may penetrate through the entire semiconductive stack structure. The second gate structure may comprise a gate electrode and a gate insulating layer surrounding the gate electrode, wherein the gate insulating layer exposes from the back side of the semiconductive stack structure, and wherein the gate electrode and the gate insulating layer expose from front side. The unit pixel structure may further comprises a gate isolation well region extending across a thickness of the semiconductive stack structure and extending laterally along an inner periphery of the second gate structure.

The unit pixel structure may further comprise an isolation structure laterally surrounding the semiconductive stack structure, the isolation structure penetrating through the entire semiconductive stack structure. The unit pixel structure may further comprise a transfer region surrounding the second gate structure. The transfer region may comprise a doped layer of single dopant type having substantially uniform dopant distribution. The transfer region may comprise a doped layer of single dopant type having graded dopant distribution.

The transfer region may comprise a doped layer of dual dopant type having graded dopant distribution across a depth thereof. The isolation structure may comprise an insulator insert laterally surrounding the semiconductive stack structure; a dielectric layer encapsulating the insulator insert; a shallow well region being formed over the dielectric layer and the insulator insert; and a deep well region laterally surrounding the dielectric layer and the shallow well region. The insulator insert may be made of dielectric materials including oxide, nitride and oxynitride. The isolation structure may comprise a silicon insert laterally surrounding the semiconductive stack structure; a dielectric layer laterally surrounding the silicon insert; and a deep well region laterally surrounding the dielectric layer.

The silicon insert may be made of poly silicon. A dopant type of the silicon insert may be different from a dopant type of the second gate structure. The dopant type of the silicon insert may be p-type and the dopant type of the second gate structure may be n-type. The silicon insert may be exposed from the front side, and electrically coupled to a voltage supply.

There is further disclosed an image sensor structure that comprises a semiconductive stack having a front side and a back side opposite the front side, the semiconductive stack comprises a first doped layer, a second doped layer disposed over the first doped layer, a third doped layer disposed over the second doped layer, and a fourth doped layer disposed over the third doped layer; and a plurality of unit pixels formed in the semiconductive stack and arranged in a matrix pattern, each one of the plurality of unit pixels comprises a sensor well region formed within the fourth doped layer, a floating diffusion region formed within the fourth doped layer and separate from the sensor well region, a first gate structure disposed over the semiconductive stack and positioned between the sensor well region and the floating diffusion region, and a second gate structure arranged around the floating diffusion region and extending through the third doped layer.

The unit pixel may further comprise a pinning implant region formed over the sensor well region in the fourth doped layer. The first doped layer, the third doped layer, and the fourth doped layer are of a first dopant type, and the second doped layer is of a second dopant type, and the third doped layer has a heavier doping concentration than the fourth doped layer. A doping concentration of the third doped layer may be about <NUM> to <NUM> times heavier than the fourth doped layer. The first dopant type may be p-type, and the second dopant type may be n-type.

A thickness of the first doped layer may range from about <NUM> to <NUM>, a thickness of the second doped layer may range from about <NUM> to <NUM>, a thickness of the third doped layer may range from about <NUM> to <NUM>, and a thickness of the fourth doped layer may range from about <NUM> to <NUM>. The first gate structure may be protruding from the semiconductive stack and the second gate structure may have a height less than a height of protrusion of the first gate structure. The second gate structure may form a grid pattern in the semiconductive stack, and wherein the sensor well region, the first gate structure, and the floating diffusion of the unit pixel are formed within an opening of the grid pattern. The image sensor structure may further comprise a gate isolation well region extending across a thickness of the semiconductive stack and extending laterally along a periphery of the opening.

An area of the sensor well region my be less than an area of the opening of the grid pattern. The area of the sensor well region may range of about <NUM>% to <NUM>% of the area of the opening. The second gate structure may penetrate through the entire semiconductive stack. The second gate structure may comprise a gate electrode and a gate insulating layer surrounding the gate electrode, wherein the gate insulating layer exposes from the back side of the semiconductive stack, and wherein the gate electrode and the gate insulating layer expose from front side.

First gate structures of the plurality of unit pixels may be electrically coupled to a first voltage supply and the second gate structure is electrically coupled to a second voltage supply. The image sensor structure may further comprises an isolation structure forming a grid pattern that laterally surrounds each of the plurality of unit pixels, the isolation structure penetrating through the entire semiconductive stack, and the unit pixel of the plurality of unit pixels formed within an opening of the grid pattern. The unit pixel structure may further comprise a transfer region surrounding the second gate structure.

The transfer region may comprise a doped layer of single dopant type having substantially uniform dopant distribution. The transfer region may comprise a doped layer of single dopant type having graded dopant distribution. The transfer region may comprise a doped layer of dual dopant type having graded dopant distribution across a depth thereof. The isolation structure may comprise an insulator insert laterally surrounding the semiconductive stack; a dielectric layer encapsulating the insulator insert; a shallow well region being formed over the dielectric layer and the insulator insert; and a deep well region laterally surrounding the dielectric layer and the shallow well region.

The insulator insert may be made of dielectric materials including oxide, nitride and oxynitride. The isolation structure may comprise a silicon insert laterally surrounding the semiconductive stack; a dielectric layer laterally surrounding the silicon insert; and a deep well region laterally surrounding the dielectric layer. The silicon insert may be made of poly silicon.

A dopant type of the silicon insert may be different from a dopant type of the second gate structure. The dopant type of the silicon insert may be p-type and the dopant type of the second gate structure may be n-type. The silicon insert may be exposed from the front side, and electrically coupled to a voltage supply. An area of the sensor well region may be less than an area of the opening of the grid pattern. The area of the sensor well region may range of about <NUM>% to <NUM>% of the area of the opening.

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting of the disclosure. It will be further understood that the terms "comprises" and/or "comprising," or "includes" and/or "including" or "has" and/or "having" when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

As the area in the image sensor devices becomes increasingly limited, there is a need to develop an image sensor having sensing elements that are sensitive to optical signals of more than one spectrum range in a small area without compromising on the resolution. Accordingly, some embodiments described herein provide an image sensor having sensing elements that are sensitive to optical signals of more than one spectrum range in a small area without compromising the resolution.

In some embodiments, described in detail below, a semiconductive stack may be fabricated using epitaxial process, in which the layers of the semiconductive stack are epitaxially deposited layer by layer. As compared to high-energy implantation process, the epitaxial deposition process adopted in one or more embodiments described herein may help to minimize crystalline damages, offer increased accuracy in alignment/positioning, and improve confinement of doping profiles for individual inter-layers.

Referring now to <FIG> illustrates semiconductive stack <NUM> for use in an image sensor device according to one or more embodiments described herein. As shown in <FIG> semiconductive stack <NUM> may include front side <NUM> and back side <NUM>, which may be opposite front side <NUM>. Semiconductor stack <NUM> may include a first doped layer <NUM>, a second doped layer <NUM> disposed on the first doped layer <NUM>, a third doped layer <NUM> disposed on the second doped layer <NUM>, and a fourth doped layer <NUM> disposed on the third doped layer <NUM>. In some embodiments, doped layer <NUM>, doped layer <NUM>, doped layer <NUM>, and doped layer <NUM> may form a device region for an unit pixel of an image sensor (not shown in <FIG>). In some embodiments, described in further detail below, semiconductor stack <NUM> may include at least two photodiodes.

In some embodiments, the first doped layer <NUM>, the third doped layer <NUM>, and the fourth doped layer <NUM> include a first dopant type (not shown in <FIG>) and the second doped layer <NUM> is of a second dopant type (not shown). In some embodiments, the third doped layer <NUM> may include a heavier concentration of dopant relative to the fourth doped layer <NUM>. In some exemplary embodiments, the first dopant type may be p-type, and the second dopant type may be n-type. Semiconductive stack <NUM> including the first doped layer <NUM>, the second doped layer <NUM>, the third doped layer <NUM>, and the fourth doped layer <NUM> may be utilized as a device region for a unit pixel of an image sensor, in which at least two photodiodes are formed, which is discussed in further detail below. It is noted that the type of doping disclosed above is merely an exemplary embodiment, and, in some embodiments, the order of dopant type may be switched. For example, in some embodiments, the order of the combination of the type of dopants of the first doped layer <NUM>, the second doped layer <NUM>, the third doped layer <NUM>, and the fourth doped layer <NUM> may be different than as described above (e.g., the first dopant type may be n-type while the second dopant type may be p-type).

In some embodiments, the thickness of semiconductive stack <NUM> ranges from about <NUM> to <NUM> (as used herein "about" means the difference is negligible). In some embodiments, the thickness of the first doped layer <NUM> ranges from about <NUM> to <NUM>, a thickness of the second doped layer <NUM> ranges from about <NUM> to <NUM>, a thickness of the third doped layer <NUM> ranges from about <NUM> to <NUM>, and a thickness of the fourth doped layer <NUM> ranges from about <NUM> to <NUM>. In some embodiments, a combined thickness of the first doped layer <NUM> and the second doped layer <NUM> may be substantially (as used herein "substantially" means the difference is negligible) equal to a thickness of the fourth doped layer <NUM>.

The pixel structure (not shown in <FIG>) in accordance with one or more embodiments may be employed in either a front side illumination (FSI) or back side illumination (BSI) arrangement. In some embodiments, when semiconductive stack <NUM> is used for back side illumination image pixel, a combined thickness of the first doped layer <NUM> and the second doped layer <NUM> may be less than a thickness of the fourth doped layer <NUM>. In some embodiments, when semiconductive stack <NUM> may be used for front side illumination pixel, a combined thickness of the first doped layer <NUM> and the second doped layer <NUM> may be greater than a thickness of the fourth doped layer <NUM>.

In some embodiments, the first doped layer <NUM>, the second doped layer <NUM>, the third doped layer <NUM>, and the fourth doped layer <NUM> are formed on a substrate (not shown) epitaxially and the substrate may be removed after the epitaxial process. The order of forming the doped layers (e.g., doped layers <NUM>, <NUM>, <NUM>, <NUM>) of semiconductive stack <NUM> is not limited by the exemplary embodiments. In some embodiments, the first doped layer <NUM> may be formed first on the substrate. In some other embodiment, the fourth doped layer <NUM> may be formed first on the substrate. In some embodiments, back side <NUM> of semiconductive stack <NUM> may be treated to form uneven (e.g., rough surface) on the first doped layer <NUM> to help reflecting the incident light received by the unit pixels.

Referring now to <FIG> and <FIG>, in conjunction with <FIG>, <FIG> illustrates a cross section of an exemplary unit pixel 10A in accordance with one or more embodiments. <FIG> illustrates planar view of front side <NUM> of unit pixel 10A in <FIG> for use in an image sensor device in accordance with one or more embodiments. The cross section in <FIG> is taken along line CC' of <FIG>. As shown in <FIG>, in some embodiments, an image sensor <NUM> comprises a plurality of unit pixels 10A, for example. In some embodiments, unit pixels 10A may be arranged in a matrix, which is discussed in further detail below.

As shown in <FIG>, in some embodiments, unit pixel 10A comprises semiconductive stack <NUM>, sensor well region <NUM>, floating diffusion region <NUM>, gate structure 118A, and gate structure 119A. For clarity, gate structures 118A, 119A are depicted in <FIG> as broken lines showing the approximate location of gate structures 118A, 119B. However, the depiction of gate structures 118A, 119A as shown in <FIG> are not intended to be limiting, rather shown as an exemplary implementation. In some embodiments, gate structures 118A, 119A may encompass more, or less, of semiconductive stack <NUM>. Gate structures 118A, 119A are described in further detail below. In one embodiment, an area of unit pixel 10A may be about a <NUM> by <NUM>. In another embodiment, sensor well region <NUM> may be formed within doped layer <NUM>. In yet another embodiment, floating diffusion region <NUM> may be formed within doped layer.

In some embodiments, gate structure 118A may be a horizontal transfer gate (HTG). Gate structure 118A may be disposed over semiconductive stack <NUM> and positioned between sensor well region <NUM> and floating diffusion region <NUM>. Gate structure 118A includes a gate electrode <NUM> and a gate insulating layer <NUM>. Gate insulating layer <NUM> may be formed between semiconductive stack <NUM> and gate electrode <NUM>. In some embodiments, an induced channel 118c may induced by the charge of the gate electrode <NUM> on the fourth doped layer <NUM> between the sensor well region <NUM> and the floating diffusion region <NUM>.

In some embodiments, gate structure 119A may be a vertical transfer gate (VTG). Gate structure 119A may be arranged around the floating diffusion region <NUM> and extending through doped layer <NUM>, as shown in <FIG>. As shown in <FIG> an induced channel 119c for transferring stored charges to floating diffusion region <NUM> may be formed along an area of the lateral side of gate structure 119A free of the gate isolation well region <NUM>.

In the embodiment shown in <FIG>, gate structure 119A (not shown in <FIG>) may be formed on a periphery of unit pixel 10A and penetrates through the entirety of semiconductive stack <NUM>. Gate structure 119A includes gate electrode <NUM> and gate insulating layer <NUM>. Gate insulating layer <NUM> of gate structure 119A may be exposed from front side <NUM> and back side <NUM> of semiconductive stack <NUM>. In some embodiments, gate electrode <NUM> may be exposed from front side <NUM> of semiconductive stack <NUM>. The structural arrangement, as described above in accordance with the one or more embodiments, enables gate structure 119A to serve the dual roles of control gate (for one of the photo diodes) as well as pixel isolation structure, which is discussed in further detail below. Accordingly, the need for standalone pixel isolation structures (such as deep trench isolation) may be eliminated, thereby allowing more efficient utilization of valuable area budget.

In some embodiments, the height of gate structure 118A extending away from semiconductive stack <NUM> may be greater than the height of gate structure 119A extending away from semiconductive stack <NUM>. In some embodiments, gate structure 119A may be substantially coplanar to front side <NUM> of semiconductive stack <NUM>. In some embodiments, unit pixel 10A further comprises gate isolation well region <NUM>. Gate isolation well region <NUM> may extend across the width (i.e., thickness) of semiconductive stack <NUM>. As shown in <FIG>, gate isolation well region <NUM> may further extend laterally along inner periphery of gate structure 119A. In some embodiments, gate isolation well region <NUM> surrounds semiconductive stack <NUM> used to form unit pixel 10A. In some embodiments, gate isolation well region <NUM> may be a p-type well region.

Referring back now to <FIG>, during operation, an induced channel 119C for transferring stored charges to floating diffusion region <NUM> may be formed along an area of the lateral side of gate structure 119A free of the gate isolation well region <NUM>. In some embodiments, a width of induced channel 119c may be less than or substantially equal to a width of floating diffusion region <NUM> surrounding gate structure 119A. In another embodiment, a width of the induced channel 119c may be greater than a width of the floating diffusion region <NUM> surrounding gate structure 119A. In some embodiments, unit pixel 10A further includes pinning implant region <NUM> formed over sensor well region <NUM> in doped layer <NUM>. The inclusion of pinning implant <NUM> may help to alleviate dark current issues. In some embodiments, the area of the pinning implant <NUM> may be substantially the same as the area of the sensor well region <NUM>.

In some embodiments, unit pixel 10A may be a dual photodiode configuration, which enables the sensing of dual optical spectrums in a single unit pixel. For example, unit pixel 10A may include a first photodiode and a second photodiode stacked on top of each other. In some embodiments, the second doped layer <NUM> may be a part of the first photodiode and may be configured to be a short-wavelength photosensitive region used for detecting shorter wavelength spectrum of the incident light. The short wavelength spectrum includes visible lights. The third doped layer <NUM> may be used as an anti-spill-back layer configured to suppress the charges from being spilled back to doped layer <NUM> after completion of a charge transfer.

For example, the heavier doping of the third doped layer <NUM> builds a potential hump between the second doped layer <NUM> and the fourth doped layer <NUM> to support complete transfer of charges and to suppress signal lag. Sensor well region <NUM> may be part of the second photodiode and includes a n-type well formed within the fourth doped layer <NUM> to form a long-wavelength photosensitive region to detect the longer wavelength spectrum of the incident light. The longer wavelength spectrum may include the electromagnetic wave in the infrared spectrum. In some embodiments, an area of sensor well region <NUM> may be less than an area of the second doped layer <NUM> in an exemplary unit pixel 10A. The area of sensor well region <NUM> may be in a range of about <NUM>% to <NUM>% of the second doped layer <NUM> in one exemplary unit pixel 10A. In some embodiments, the area of sensor well region <NUM> may be as small as will be allowed by the design rule for the technology and as large as will be allowed by the design rule for the technology in relation to a gate and a neighboring diffusion region such as gate structure 118A and floating diffusion region <NUM>.

In some embodiments, the pinning implant <NUM> includes a p-type doped region used to reduce dark current. The floating diffusion region <NUM> includes a n-type doped region. For a front side illumination using the present disclosure, the second doped layer <NUM> may be a part of the first photodiode and may be configured to be a long-wavelength photosensitive region used for detecting longer wavelength spectrum of the incident light. And, the sensor well region <NUM> may be a part of the second photodiode and includes a n-type well formed within the fourth doped layer <NUM> to form a short-wavelength photosensitive region to detect the shorter wavelength spectrum of the incident light.

In other embodiments, unit pixel 10A further includes a portion of the dielectric layer <NUM> covering the back side <NUM> of unit pixel <NUM>. The dielectric layer <NUM> includes a high-k dielectric passivation material. The dielectric layer <NUM> covering the back side <NUM> may be used to suppress the generation of dark currents. The first doped layer <NUM> may be used as a buffer between the second doped layer <NUM>. The dielectric layer <NUM> may be used to suppress generation of dark currents by isolating the second doped layer <NUM> from the dielectric layer <NUM>. An insulating layer <NUM> may be further disposed over the back side <NUM>. The insulating layer <NUM> covers the dielectric layer <NUM>. The insulating layer <NUM> may be a dielectric material including silicon-dioxide, nitride, oxynitride. A metal grid pattern <NUM> may be formed over the insulating layer <NUM>. The metal grid pattern may be made of material including tungsten, aluminum, copper. In some embodiments, the metal grid pattern <NUM> may be aligned with gate structure 119A. A passivation layer <NUM> may be further formed over the insulating layer <NUM>. The passivation layer <NUM> may be a dielectric material including silicon-dioxide, nitride, oxynitride. The passivation layer <NUM> covering a portion of the lateral side of the metal grid pattern <NUM>.

To form a front side illumination using the present disclosure, the dielectric layer <NUM> covering back side <NUM> of unit pixel 10A, the insulating layer <NUM>, the metal grid pattern <NUM>, and the passivation layer <NUM> are no longer formed on the structure. Instead, substrate <NUM>' may be disposed on back side <NUM> of unit pixel 10D as shown in <FIG>. In some embodiments, substrate <NUM>' may be the substrate used in forming semiconductive stack <NUM>.

In some embodiments, an image sensor (for example, the same or similar to image sensor <NUM>, <NUM>) comprises a plurality of unit pixels 10A arranged in a matrix pattern (e.g. as shown in <FIG>). Gate structure 119A forms a grid pattern in semiconductive stack <NUM>. The sensor well region <NUM>, gate structure 118A, and the floating diffusion region <NUM> of each unit pixel are formed within an opening of the grid pattern. In some embodiments, a sensing area of the second doped layer <NUM> for unit pixel 10A may be an area of the opening of the grid pattern.

The plurality of unit pixels 10A (e.g., as shown in <FIG>) may share a common second gate structure (e.g., 119A). In some embodiments, the voltage supply V2 may be shared by gate electrodes <NUM> of plurality unit pixels in the image sensor. In some embodiments, the voltage supply V2 may be electrically coupled to contacts <NUM> disposed on the exposed portion of gate structure 119A closest to the induced channel (e.g., an area of the lateral side of gate structure 119A not laterally covered by the gate isolation well region <NUM>). A first set of charges are stored in the first photodiode reflecting the incident light detected.

Upon activation of gate electrode <NUM>, the first set of charges are transferred from the first photodiode to floating diffusion region <NUM> through channel 119c induced by the charge of the gate electrode <NUM> on semiconductive stack <NUM> between the second doped layer <NUM> and the floating diffusion region <NUM>. A backend readout circuit (not shown) may be coupled to the floating diffusion region <NUM> through a terminal V3 to determine the amount of charges detected in the first photodiode. When operating the image sensor, a voltage supply V1 may be electrically coupled to gate electrode <NUM>' of gate structure 118A. In some embodiments, the voltage supply V1 may be shared by the gate electrodes <NUM>' of the plurality unit pixels in the image sensor (not shown).

In some embodiments, the voltage supply V1 electrically coupled to gate electrode <NUM> of each unit pixel 10A may be separate from other unit pixels 10A to activate the gate electrode <NUM> of different unit pixels 10A at different times. A second set of charges are stored in the second photodiode reflecting the incident light detected. Upon activation of gate electrode <NUM>, the second set of charges are transferred from the second photodiode to the floating diffusion region <NUM> through a channel 118c induced by the charge of the gate electrode <NUM> on the fourth doped layer <NUM> between the sensor well region <NUM> and the floating diffusion region <NUM>. A backend readout circuit may be coupled to the floating diffusion region <NUM> through a terminal V3 to determine the amount of charges detected in the second photodiode. In other words, the exemplary embodiment as shown in <FIG> supports an image sensor having a global shutter. On the other hand, with alternation of the surrounding gate arrangement (e.g., providing separated ring gates instead of a joined mesh pattern), it may be also possible to form individual ring gates that support rolling shutter operation.

Referring now to <FIG> in conjunction with <FIG>, <FIG> illustrates a cross section of a unit pixel 10B according to some embodiments of the present disclosure. <FIG> illustrates a planar view of a front side <NUM> of unit pixel 10B in <FIG> according to one or more embodiments described herein. <FIG> illustrates a planar view of a back side <NUM>' of unit pixel 10B in <FIG> according to one or more embodiments described herein. The cross section in <FIG> is taken along line AA' of <FIG>.

In some embodiments, an area of unit pixel 10B may be a <NUM> by <NUM> square area. In some embodiments, unit pixel 10B comprises semiconductive stack <NUM> in <FIG>, sensor well region <NUM>', floating diffusion region <NUM>', a first gate structure 118A', and a second gate structure 119A'. Sensor well region <NUM>' may be formed within doped layer <NUM>'. Floating diffusion region <NUM>' may be formed within the fourth doped layer <NUM>'. Gate structure 118A' may be a horizontal transfer gate (HTG). Gate structure 118A' includes a gate electrode <NUM>' and a gate insulating layer <NUM>'. Gate structure 118A' may be disposed over semiconductive stack <NUM> and positioned between the sensor well region <NUM>' and floating diffusion region <NUM>'. Gate insulating layer <NUM>' may be formed between semiconductive stack <NUM> and the gate electrode <NUM>'. Gate structure 119A' may be a vertical transfer gate (VTG). Gate structure 119A' includes a gate electrode <NUM>' and a gate insulating layer <NUM>'. Gate structure 119A' may be arranged around floating diffusion region <NUM>' and extending through the third doped layer <NUM>'.

In some embodiments, gate structure 119A' penetrates through the first doped layer <NUM>'. In other embodiments, gate structure 119A' does not penetrate through the first doped layer <NUM>' and only partially penetrates through doped layer <NUM>'. The height of gate structure 118A' extending away from semiconductive stack <NUM> may be greater than the height of gate structure 119A' extending away from semiconductive stack <NUM>. In some embodiments, gate structure 119A' may be substantially planar to front side <NUM>' of semiconductive stack <NUM>. The lateral side of gate structure 119A' may be where a channel may be formed for transferring of stored charges to floating diffusion region <NUM>'.

In some embodiments, unit pixel 10B further includes an isolation structure <NUM> laterally surrounding unit pixel 10B. Isolation structure <NUM> may be penetrating through the entire semiconductive stack <NUM>. Isolation structure <NUM> may be a passive isolation structure. As shown in <FIG>, isolation structure <NUM> includes insulator insert <NUM>', dielectric layer <NUM>', shallow well region <NUM>', and deep well region <NUM>'. The insulator insert <NUM>' laterally surrounds semiconductive stack <NUM>. In some embodiments, the insulator insert <NUM>' may be substantially planar to the back side <NUM>'. Insulator insert <NUM>' may be made of materials including oxide, nitride and oxynitride. Dielectric layer <NUM>' encapsulates insulator insert <NUM>'. Shallow well region <NUM>' may be formed over dielectric layer <NUM>' and insulator insert <NUM>'. In some embodiments, shallow well region <NUM>' may be substantially planar to front side <NUM>'. In some embodiments, shallow well region <NUM>' may be a p-type well region. Deep well region <NUM>' may laterally surrounding dielectric layer <NUM>' and shallow well region <NUM>'. In some embodiments, deep well region <NUM>' may be a p-type well region.

In some embodiments, unit pixel 10B further includes transfer region <NUM>' surrounding gate structure 119A'. The transfer region <NUM>' may be an area where the induced channel may be formed. In some embodiments, transfer region <NUM>' may be doped with a doping profile that facilitates anti-blooming and suppresses dark current during exposure and accumulation of charges. In some embodiments, transfer region <NUM>' includes a doped layer of single dopant type having substantially uniform dopant distribution. In other embodiments, transfer region <NUM>' includes a doped layer of single dopant type having a graded dopant distribution. In other embodiments, transfer region <NUM>' comprises a doped layer of dual dopant type having graded dopant distribution across a depth thereof. The portion of transfer region31' closest to back side <NUM>' may be of a first dopant type. And, the portion of the transfer region <NUM>' closest to the front side <NUM>' may be of a second dopant type. The first dopant type of the transfer region <NUM>' gradually changes to the second dopant type of transfer region31' along the lateral side of gate structure 119A'. In some embodiments, the first dopant type may be p-type while the second dopant type may be n-type. In some embodiments, unit pixel 10B further includes a pinning implant <NUM>' used to reduce dark current formed over the sensor well region <NUM>' in the fourth doped layer <NUM>'. In some embodiments, the area of the pinning implant <NUM>' may be substantially the same as the area of the sensor well region <NUM>'.

In some embodiments, unit pixel 10B may be of a dual photodiode configuration, which enables the sensing of dual optical spectrums in a single unit pixel. Unit pixel 10B has a first photodiode and a second photodiode stacked on top of each other. In some embodiments, the second doped layer <NUM>' may be a part of the first photodiode and may be configured to be a short-wavelength photosensitive region used for detecting shorter wavelength spectrum of the incident light. The short wavelength spectrum includes visible lights. The third doped layer <NUM>' may be used as an anti-spill-back layer configured to suppress the charges from being spilled back to the second doped layer <NUM>' after completion of a charge transfer. The heavier doping of the third doped layer <NUM>' builds a potential hump between the second doped layer <NUM>' and the fourth doped layer <NUM>' to support complete transfer of charges and to suppress signal lag. The sensor well region <NUM>' may be a part of the second photodiode and includes a n-type well formed within the fourth doped layer <NUM>' to form a long-wavelength photosensitive region to detect the longer wavelength spectrum of the incident light. The long wavelength spectrum includes the infrared light. In some embodiments, an area of the sensor well region <NUM>' may be less than an area of doped layer <NUM>' in unit pixel 10B. The area of sensor well region <NUM>' may be in a range of about <NUM> to <NUM>% of the second doped layer <NUM>' in an exemplary unit pixel 10B. In some embodiments, the area of the sensor well region may be as small as will be allowed by the design rule for the technology and as large as will be allowed by the design rule for the technology in relation to the gates and a neighboring diffusion region such as gate structure 118A', gate structure 119A', and floating diffusion region <NUM>'. Pinning implant <NUM>' includes a p-type doped region used to reduce dark current. Floating diffusion region <NUM>' includes a n-type doped region. For a front side illumination using the present disclosure, the second doped layer <NUM>' may be a part of the first photodiode and may be configured to be a long-wavelength photosensitive region used for detecting longer wavelength spectrum of the incident light. And, the sensor well region <NUM>' may be a part of the second photodiode and includes a n-type well formed within the fourth doped layer <NUM>' to form a short-wavelength photosensitive region to detect the shorter wavelength spectrum of the incident light.

In other embodiments, unit pixel 10B further includes a portion of dielectric layer <NUM>' covering back side <NUM>' of unit pixel 10B. dielectric layer <NUM>' includes a high-k dielectric passivation material. dielectric layer <NUM>' covering the back side <NUM>' may be used to suppress the generation of dark currents. The first doped layer <NUM>' may be used as a buffer between the second doped layer <NUM>'. Dielectric layer <NUM>' may be used to suppress generation of dark currents by isolating the second doped layer <NUM>' from dielectric layer <NUM>'. Insulating layer <NUM>' may be further disposed over back side <NUM>'. Insulating layer <NUM>' covers dielectric layer <NUM>'. Insulating layer <NUM>' may be a dielectric material including silicon-dioxide, nitride, oxynitride. A metal grid pattern <NUM>' may be formed over insulating layer <NUM>'. Metal grid pattern <NUM> may be made of material including tungsten, aluminum, copper. In some embodiments, metal grid pattern <NUM>' may be aligned with gate structure 119A'. passivation layer <NUM>' may be further formed over the insulating layer <NUM>'. Passivation layer <NUM>' may be a dielectric material including silicon-dioxide, nitride, oxynitride. Passivation layer <NUM>' covering a portion of the lateral side of the metal grid pattern <NUM>'.

In some embodiments, a front side illumination using the present disclosure may be formed wherein the dielectric layer <NUM>' covering the back side <NUM>' of unit pixel 10B, the insulating layer <NUM>', the metal grid pattern <NUM>', and the passivation layer <NUM>' are no longer formed on device 10B. Instead, a substrate <NUM>' may be disposed on the back side <NUM>' of unit pixel 10E as shown in <FIG>. In some embodiments, the substrate <NUM>' may be the substrate used in forming semiconductive stack <NUM>.

As shown in <FIG>, in some embodiments, image sensor <NUM> may include a plurality of unit pixels 10B arranged in a matrix pattern, (the same or similar to the plurality of unit pixels 10A as shown in <FIG> for example). Isolation structure <NUM> may form a grid pattern in semiconductive stack <NUM>. Each unit pixel 10B may be formed within an opening of the grid pattern. Isolation structure <NUM> may be used to isolate unit pixels 10B from each other. In some embodiments, a sensing area of doped layer <NUM>' for unit pixel 10B may be substantially equal to an area of the opening of the grid pattern.

When operating the image sensor, a voltage supply V2 may be electrically coupled to the gate electrode <NUM>' of gate structure 118A'. In some embodiments, the voltage supply V2 may be shared by the gate electrodes <NUM>' of the plurality unit pixels in the image sensor. In other embodiments, the voltage supply V2 electrically coupled to the gate electrode <NUM>' of each unit pixel 10B may be separate from other unit pixels 10B to activate the gate electrode <NUM>' of different unit pixels 10B at different times. A first set of charges are stored in the first photodiode reflecting the incident light detected. Upon activation of the gate electrode <NUM>', the first set of charges may be transferred from the first photodiode to floating diffusion region <NUM>' through channel 119c induced by the charge of the gate electrode <NUM>' on semiconductive stack <NUM> between the second doped layer <NUM>' and floating diffusion region <NUM>'. A backend readout circuit (not shown) may be coupled to floating diffusion region <NUM>' through a terminal V3 to determine the amount of charges detected in the first photodiode. When operating the image sensor, a voltage supply V1 may be electrically coupled to the gate electrode <NUM>' of gate structure 118A'. In some embodiments, the voltage supply V1 may be shared by the gate electrodes <NUM>' of the plurality unit pixels in the image sensor. In other embodiments, the voltage supply V1 electrically coupled to the gate electrode <NUM>' of each unit pixel 10B may be separate from other unit pixels 10B to activate the gate electrode <NUM> of different unit pixels 10B at different times. A second set of charges are stored in the second photodiode reflecting the incident light detected. Upon activation of the gate electrode <NUM>', the second set of charges may be transferred from the second photodiode to floating diffusion region <NUM>' through a channel induced by the charge of the gate electrode <NUM>' on the fourth doped layer <NUM>' between the sensor well region <NUM>' and floating diffusion region <NUM>'. A backend readout circuit may be coupled to floating diffusion region <NUM>' through a terminal V3 to determine the amount of charges detected in the second photodiode.

Referring now to <FIG>, <FIG> illustrates a cross section of unit pixel 10C according to some embodiment of the present disclosure. <FIG> illustrates a planar view of unit pixel 10C in <FIG> according to some embodiment of the present disclosure. The cross section in <FIG> may be taken along line BB' of <FIG>. In some embodiments, an area of the unit pixel 10C may be a <NUM> by <NUM> square area. In some embodiments, unit pixel 10C comprises semiconductive stack <NUM> in <FIG>, a sensor well region <NUM>", a floating diffusion region <NUM>", a first gate structure, and a second gate structure (for clarity the first and second gate structures are not shown in <FIG>). In some embodiments, the first gate structure and the second gate structure may be the same or similar to gate structures 118A, 119A, as described above.

In some embodiments, sensor well region <NUM>" may be formed within the fourth doped layer <NUM>". Floating diffusion region <NUM>" may be formed within the fourth doped layer <NUM>". Gate structure 118A" may be a horizontal transfer gate (HTG). Gate structure 118A" includes a gate electrode <NUM>" and a gate insulating layer <NUM>". Gate structure 118A" may be disposed over semiconductive stack <NUM>" and positioned between sensor well region <NUM>" and floating diffusion region <NUM>". Gate insulating layer <NUM>" may be formed between semiconductive stack <NUM>" and the gate electrode <NUM>". Gate structure 119A" may be a vertical transfer gate (VTG). Gate structure 119A" include a gate electrode <NUM>" and a gate insulating layer <NUM>". Gate structure 119A" may be arranged around floating diffusion region <NUM>" and extending through the third doped layer <NUM>".

In some embodiments, gate structure 119A" penetrates through the first doped layer <NUM>". In other embodiments, gate structure 119A" does not penetrate through the first doped layer <NUM>" and only partially penetrates through the second doped layer <NUM>". The height of gate structure 118A" extending away from semiconductive stack <NUM> may be greater than the height of gate structure 119A" extending away from semiconductive stack <NUM>. In some embodiments, gate structure 119A" may be substantially planar to the front side <NUM>" of semiconductive stack <NUM>. The lateral side of gate structure 119A" may be where a channel may be formed for transferring of stored charges to floating diffusion region <NUM>".

In some embodiments, unit pixel 10C further includes an isolation structure laterally surrounding unit pixel 10C. Isolation structure <NUM> may be penetrating through the entire semiconductive stack. Isolation structure <NUM> may be an active isolation structure. Isolation structure <NUM> includes a silicon insert <NUM>", a dielectric layer <NUM>", and a deep well region <NUM>". The silicon insert <NUM>" may be laterally surrounding semiconductive stack <NUM>". The silicon insert <NUM>" may be made of poly silicon. A dopant type of the silicon insert <NUM>" may be different from a dopant type of the gate electrode <NUM>" of gate structure 119A". In some embodiments, the dopant type of the silicon insert <NUM>" may be p-type and the dopant type of the gate electrodes <NUM>" of gate structure 119A" may be n-type. The silicon insert <NUM>" may be exposed from the front side <NUM>" and may be electrically coupled to a voltage supply V4. The dielectric layer <NUM>" may be laterally surrounding the silicon insert <NUM>". The deep well region <NUM>" may be laterally surrounding the dielectric layer <NUM>". In some embodiments, deep well region <NUM>" may be a p-type well region.

In some embodiments, unit pixel 10B further includes transfer region <NUM>" surrounding gate structure 119A". Transfer region <NUM>" may be an area where the induced channel may be formed. The transfer region <NUM>" may be doped with a doping profile that facilitates anti-blooming and suppresses dark current during exposure and accumulation of charges. In some embodiments, transfer region <NUM>" comprises a doped layer of single dopant type having substantially uniform dopant distribution. In other embodiments, transfer region <NUM>' includes a doped layer of single dopant type having a graded dopant distribution. In other embodiments, transfer region <NUM>" includes a doped layer of dual dopant type having graded dopant distribution across a depth thereof. The portion of the transfer region <NUM>" closest to back side <NUM>" may be of a first dopant type. And, the portion of the transfer region <NUM>" closest to the front side <NUM>" may be of a second dopant type. The first dopant type of transfer region <NUM>" gradually changes to the second dopant type of transfer region <NUM>" along the lateral side of gate structure 119A". In some embodiments, the first dopant type may be p-type while the second dopant type may be n-type. In some embodiments, unit pixel 10C further includes pinning implant <NUM>" used to reduce dark current may be formed over sensor well region <NUM>" in the fourth doped layer <NUM>". In some embodiments, the area of pinning implant <NUM>" may be substantially the same as the area of sensor well region <NUM>".

In some embodiments, unit pixel 10C may be a dual photodiode configuration, which enables the sensing of dual optical spectrums in a single unit pixel. Unit pixel 10C has a first photodiode and a second photodiode stacked on top of each other. In some embodiments, the second doped layer <NUM>" may be a part of the first photodiode and may be configured to be a short-wavelength photosensitive region used for detecting shorter wavelength spectrum of the incident light.

For example, the short wavelength spectrum includes visible lights. In some embodiments, the third doped layer <NUM>" may be used as an anti-spill-back layer configured to suppress the charges from being spilled back to the second doped layer <NUM>" after completion of a charge transfer. The heavier doping of the third doped layer <NUM>" builds a potential hump between the second doped layer <NUM>" and the fourth doped layer <NUM>" to support complete transfer of charges and to suppress signal lag. The sensor well region <NUM>" may be a part of the second photodiode and includes a n-type well formed within the fourth doped layer <NUM>" to form a long-wavelength photosensitive region to detect the longer wavelength spectrum of the incident light. The long wavelength spectrum includes the infrared light.

In some embodiments, an area of the sensor well region <NUM>" may be less than an area of the second doped layer <NUM>" in one unit pixel 10C. The area of the sensor well region <NUM>" may be in a range of about <NUM> to <NUM>% of the second doped layer <NUM>" in one unit pixel 10C. In some embodiments, the area of the sensor well region may be as small as will be allowed by the design rule for the technology and as large as will be allowed by the design rule for the technology in relation to the gates and a neighboring diffusion region such as gate structure 118A", gate structure 119A", and floating diffusion region <NUM>". Pinning implant <NUM>" may include a p-type doped region used to reduce dark current. Floating diffusion region <NUM>" includes a n-type doped region. When adopting the instantly disclosed unit pixel structure to the front side illumination device, as discussed above, the second doped layer <NUM>" may be a part of the first photodiode and configured to be a long-wavelength photosensitive region used for detecting longer wavelength spectrum of the incident light. And, sensor well region <NUM>" may be a part of second photodiode and includes a n-type well formed within the fourth doped layer <NUM>" to form a short-wavelength photosensitive region to detect the shorter wavelength spectrum of the incident light.

In other embodiments, unit pixel 10C further includes a portion of the dielectric layer <NUM>" covering the back side <NUM>" of unit pixel 10C. Dielectric layer <NUM>" includes a high-k dielectric passivation material. Dielectric layer <NUM>" covering the back side <NUM>" may be used to suppress the generation of dark currents. The first doped layer <NUM>" may be used as a buffer between the second doped layer <NUM>". Dielectric layer <NUM>" may be used to suppress generation of dark currents by isolating the second doped layer <NUM>' from dielectric layer <NUM>". An insulating layer <NUM>" may be further disposed over the back side <NUM>". The insulating layer <NUM>" covers dielectric layer <NUM>". The insulating layer <NUM>" may be a dielectric material including silicon-dioxide, nitride, oxynitride. Metal grid pattern <NUM>" may be formed over the insulating layer <NUM>". Metal grid pattern <NUM> may be made of material including tungsten, aluminum, copper. In some embodiments, the metal grid pattern <NUM>" may be aligned with gate structure 119A". A passivation layer <NUM>" may be further formed over the insulating layer <NUM>". Passivation layer <NUM>" may be a dielectric material including silicon-dioxide, nitride, oxynitride. Passivation layer <NUM>" may cover a portion of the lateral side of metal grid pattern <NUM>".

In some embodiments, to form a front side illumination using the present disclosure, dielectric layer <NUM>" covering the back side <NUM>" of unit pixel 10C, the insulating layer <NUM>", the metal grid pattern <NUM>", and the passivation layer <NUM>" are no longer formed on the device <NUM>. Instead, a substrate <NUM>" may be disposed on the back side <NUM>" of unit pixel 10F as shown in <FIG>. In some embodiments, the substrate <NUM>" may be the substrate used in forming semiconductive stack <NUM>.

In some embodiments, an image sensor comprises a plurality of unit pixels 10C arranged in a matrix pattern. Isolation structure <NUM> forms a grid pattern in semiconductive stack <NUM>. Each unit pixel 10C may be formed within an opening of the grid pattern. In some embodiments, a sensing area of the second doped layer <NUM>" for one unit pixel 10C may be substantially equal to an area of the opening of the grid pattern.

During operation of the image sensor, a voltage supply V2 may be electrically coupled to the gate electrode <NUM>" of gate structure 118A". In some embodiments, the voltage supply V2 may be shared by the gate electrodes <NUM>" of the plurality unit pixels in the image sensor. In other embodiments, the voltage supply V2 electrically coupled to the gate electrode <NUM>" of each unit pixel 10C may be separate from other unit pixels 10C to activate the gate electrode <NUM>" of different unit pixels 10C at different times. A first set of charges are stored in the first photodiode reflecting the incident light detected. Upon activation of the gate electrode <NUM>", the first set of charges may be transferred from the first photodiode to floating diffusion region <NUM>" through a channel induced by the charge of the gate electrode <NUM>" on semiconductive stack <NUM> between the second doped layer <NUM>" and floating diffusion region <NUM>". A backend readout circuit may be coupled to floating diffusion region <NUM>" through a terminal V3 to determine the amount of charges stored in the first photodiode. When operating the image sensor, a voltage supply V1 may be electrically coupled to the gate electrode <NUM>" of gate structure 118A". In some embodiments, the voltage supply V1 may be shared by the gate electrodes <NUM>" of the plurality unit pixels in the image sensor. In other embodiments, the voltage supply V1 electrically coupled to the gate electrode <NUM>" of each unit pixel 10C may be separate from other unit pixels 10C to activate the gate electrode <NUM>" of different unit pixels 10C at different times. A second set of charges are stored in the second photodiode reflecting the incident light detected. Upon activation of the gate electrode <NUM>", the second set of charges may be transferred from the second photodiode to floating diffusion region <NUM>" through a channel induced by the charge of the gate electrode <NUM>" on the fourth doped layer <NUM>" between the sensor well region <NUM>" and floating diffusion region <NUM>". A backend readout circuit (not shown) may be coupled to floating diffusion region <NUM>" through a terminal V3 to determine the amount of charges stored in the second photodiode.

For the embodiments as illustrated in <FIG>, <FIG>, and <FIG>, a plurality of contacts (e.g., <NUM>, <NUM>', and <NUM>") may be formed on the exposed portion of gate structure 119A (e.g., from the front side <NUM>, <NUM>' and <NUM>") to electrically couple respective voltage supplies and output terminals such as the terminal V3. As illustrated in <FIG>, <FIG>, and <FIG> contact <NUM>, <NUM>', and <NUM>" may be further disposed on and electrically coupled to the fourth doped layer <NUM>, <NUM>', and <NUM>" to electrically couple the fourth doped layer <NUM>, <NUM>', and <NUM>" to bias voltage supply or a ground terminal. The fourth doped layer <NUM>, <NUM>', and <NUM>" may be used as a bulk or a body of the corresponding unit pixel. The contacts <NUM>, <NUM>', <NUM>", <NUM>, <NUM>', and <NUM>" shown in <FIG> are used to show parts of unit pixels 10A, 10B, and 10C having electrical coupling to circuits outside unit pixels 10A, 10B, and 10C. Nevertheless, it should be noted that the number of contacts <NUM>, <NUM>', <NUM>", <NUM>, <NUM>', and <NUM>" as shown in <FIG> are not meant to be used as a limitation for the exact positioning or the number of contacts to be used by unit pixels 10A, 10B, and 10C.

Referring now to <FIG> illustrates band diagrams <NUM> of unit pixel <NUM> according to some embodiment of the present disclosure. band diagram <NUM> is a diagram plotting various charges during the operation of unit pixel <NUM> (e.g., 10A, 10B, 10C, 10D,and/or 10E). In operation STP01, unit pixel <NUM> has completed the light exposure. Equivalent charges of the visible light detected are stored in a photosensitive region RGB_PD and equivalent charges of the infrared light detected are stored in a photosensitive region IR_PD. In operation STP02, the charges stored in the photosensitive region IR_PD are transferred. A bias voltage V1 is supplied to the gate HTG (e.g. gate 118A) to induce a channel (e.g. 118C) under the gate HTG. The potential barrier between the photosensitive region IR_PD and the charge storage region FD is lowered such that the equivalent charges of the detected infrared light begins to be transferred to the storage region FD. In operation STP03, the charges stored in the photosensitive region IR_PD are completely transferred to the charge storage region FD. The equivalent charge of the detected infrared light is read out from the charge storage region FD as an IR voltage signal. In operation STP04, the charge storage region FD is reset by supplying a reset voltage to the charge storage region FD. And, the potential barrier between the photosensitive region IR_PD and the charge storage region FD is reimplemented by removing the bias voltage V1 from the gate HTG. In operation STP05, the charges stored in the photosensitive region RGB_PD are transferred. A bias voltage V2 is supplied to the gate VTG to induce a channel around the gate VTG. The potential barrier between the photosensitive region RGB_PD and the charge storage region FD is lowered such that the equivalent charges of the detected visible light begins to be transferred to the storage region FD. In operation STP06, the charges stored in the photosensitive region RGB_PD are completely transferred to the charge storage region FD. The equivalent charge of the detected visible light is read out from the charge storage region FD as an RGB voltage signal.

Referring now to <FIG> <FIG> and <FIG>, <FIG> illustrates energy band diagrams <NUM> of an exemplary unit pixel <NUM> (e.g., 10A, 10B, 10C, 10D, 10E) according to one or more embodiments, band diagram <NUM> illustrates the operation of a photodiode in an exemplary unit pixel <NUM> having anti-spill-back layer. In some embodiments, unit pixel <NUM> comprises an anti-spill-back layer (e.g., doped layer <NUM>/<NUM>/<NUM>'/<NUM>"). In operation STP11, unit pixel <NUM> has completed the light exposure. Equivalent charges of the visible light detected are stored in a photosensitive region RGB_PD. The anti-spill-back layer may generate potential hump <NUM>. Potential hump <NUM> may be generated through the dopant concentration difference between the anti-spill-back layer (e.g., layer <NUM>) and adjacent layers (e.g., <NUM>, <NUM>). Proper arrangement of dopant concentration differentiation in these layers may create effective potential bump that enhances the operational performance of unit pixel <NUM>.

For example, a higher dopant concentration in the anti-spill-back layer (e.g., layer <NUM>) helps to improve device property. In some embodiments, barrier height <NUM> of potential bump <NUM> may be configured to be about <NUM> mV. To this end, it is found that this target potential bump may be achieved when the dopant concentration in the anti-spill-back layer (e.g., layer <NUM>) may be about <NUM> times of that in the neighboring layer (e.g., layer <NUM>). However, it should be noted that an overly large difference in dopant concentration may lead to adverse effect such as worsening of the blooming issue.

In operation STP12, the charges stored in the photosensitive region RGB_PD are transferred to the charge storage region FD upon activating the gate VTG. (e.g., 119A) A bias voltage V2 may be supplied to the gate VTG to induce a channel (e.g., 119c) around the gate VTG. The designs for the channel doping profile and gate bias for switch-on the gate VTG are optimized. The profile of the vertical induced channel in the band diagram is shown to be smooth to allow the charges stored in the photosensitive region RGB_PD to be effectively transferred through the vertical channel and into the charge storage region FD. The charges stored in the photosensitive region RGB_PD are transferred to the storage region FD with sufficient kinetic energy. Thus, the transfer of the charges stored in the photosensitive region RGB_PD are not inhibited by the potential hump. In operation STP13, potential hump <NUM> may be implemented when almost all of the charges stored in the photosensitive region RGB_PD are transferred to the storage region FD. Potential hump generates <NUM> a potential barrier such that the charges previously stored in the photosensitive region RGB_PD will not spill back once the charge has passed the hump. In operation STP14, the transfer of charges to the storage region FD is finished without having spill back.

Referring now to <FIG> illustrates a cross sectional view of a sensing unit <NUM> according to some embodiment of the present disclosure. Sensing unit <NUM> comprises four unit pixels having dual-photodiode structure. Sensing unit <NUM> includes one red pixel <NUM>, one blue pixel <NUM> and two green pixels <NUM>, <NUM> arranged in a RGBG pattern as shown in <FIG>. Since the light absorption depth is dependent on wavelength, the photosensitive regions for visible light such as RGB color light are disposed near the light incident surface while the photosensitive regions for IR light are located farther from the light incident surface.

In some embodiments, an interlayer 13A may be formed as an isolating potential barrier to avoid mixing signal charges from the photosensitive regions for visible light and IR light. IR-cut free color filters are used to allow the IR radiation to pass though the pixels. When the light is incident on the back side of pixel <NUM>, <NUM>, <NUM>, <NUM>, at least some or every pixel of sensing unit <NUM> receives both RGB-band and IR-band of the incident light. Therefore, with the dual-photodiode pixels proposed according to the embodiments of the present disclosure, the signal acquisitions for both RGB-band and IR-band are more efficient and cost-effective with only a single chip than the conventional RGB-IR image sensors that need to combine separate sensor chips for RGB-band and IR-band.

Claim 1:
A unit pixel structure, comprising:
a semiconductive stack (10A) having a front side (<NUM>) and a back side (<NUM>) opposite the front side, the semiconductive stack comprising:
a first doped layer (<NUM>, <NUM>);
a second doped layer (<NUM>, <NUM>) disposed over the first doped layer (<NUM>, <NUM>);
a third doped layer (<NUM>, <NUM>) disposed over the second doped layer (<NUM>, <NUM>); and
a fourth doped layer (<NUM>, <NUM>) disposed over the third doped layer (<NUM>, <NUM>);
a sensor well region (<NUM>) formed within the fourth doped layer (<NUM>, <NUM>);
a floating diffusion region (<NUM>) formed within the fourth doped layer (<NUM>, <NUM>) and separate from the sensor well region (<NUM>);
a first gate structure (118A) disposed over the semiconductive stack and positioned between the sensor well region (<NUM>) and the floating diffusion region (<NUM>); and
a second gate structure (119A) arranged around the floating diffusion region (<NUM>) and extending through the third doped layer (<NUM>, <NUM>),
wherein the second gate structure (119A) comprises a gate electrode (<NUM>) and a gate insulating layer (<NUM>) surrounding the gate electrode; and
wherein a doping concentration of the third doped layer (<NUM>, <NUM>) is heavier than the fourth doped layer (<NUM>, <NUM>);
wherein the third doped layer is arranged between the floating diffusion region and the first photodiode so as to build a potential hump between the floating diffusion region and the first photodiode,
wherein the first doped layer, the third doped layer, and the fourth doped layer are of a first dopant type and wherein the second layer is of a second dopant type, and wherein the third doped layer is entirely p-type or entirely n-type.