Patent Description:
Conventionally, a wide gap semiconductor device using silicon carbide or the like has been known (see, for example, <CIT>). In the wide gap semiconductor device, there is a need to lower an on-voltage of a Schottky barrier diode (SBD). Since most of the on-voltage of an SBD is due to a built-in voltage derived from Schottky junction, the on-voltage can be effectively lowered by lowering ϕB (Schottky barrier).

When n-type silicon carbide, which is a kind of wide gap semiconductor device, is taken as an example, ϕBn of SiC-SBD is generally controlled by a Schottky electrode, and Ti, Ni, Pt, or the like is used as the Schottky electrode of SiC-SBD. Among them, Ti is known to have the smallest ϕBn, and most of commercially available n-type SiC-SBDs use Ti as the Schottky electrode.

If the conventionally used electrode is changed, an etching step needs to be changed in addition to a deposition step itself. Therefore, there is a demand to lower ϕB without changing the material of the SBD electrode.

<CIT> and <CIT> disclose a method for manufacturing a silicon carbide semiconductor. Heat treatment is performed at a crystal recovery temperature to promote the recovery of crystal defects in the metal layer. Heat treatment is performed at <NUM> ±<NUM>.

The present invention provides a wide gap semiconductor device capable of lowering ϕB without changing the material of a metal layer that has been conventionally used.

In the present invention, when an aspect is adopted in which: a single crystal layer is provided in an interface region having a thickness of up to <NUM> from the interface between a wide gap semiconductor layer and a metal layer; and when it is assumed that a lattice constant, in an equilibrium state, of the C-axis of a metal constituting the metal layer is L, the interface region includes first region in which a C-axis lattice constant L1 is smaller than L by <NUM>% to <NUM>%, ϕB can be lowered.

In the present embodiment, "one side" means a front surface side that is the upper side in <FIG>, and "the other side" means a back surface side that is the lower side in <FIG>.

The present embodiment will be described by using an n-type silicon carbide semiconductor device (hereinafter, simply referred to as a "silicon carbide semiconductor device") A special silicon carbide substrate may be adopted in which a single crystal silicon carbide layer is formed on polycrystalline silicon carbide.

As shown in <FIG>, the silicon carbide semiconductor device has a silicon carbide substrate <NUM>, a silicon carbide layer <NUM> provided on the one side (front surface side) of the silicon carbide substrate <NUM>, and a metal electrode <NUM> that is a metal layer provided on the one side of the silicon carbide layer <NUM> to function as a front surface electrode. Note that as an example in the aspect shown in <FIG>, the silicon carbide layer <NUM> is directly provided on the silicon carbide substrate <NUM>, and the metal electrode <NUM> is directly provided on the silicon carbide layer <NUM>. As shown in <FIG>, the metal electrode <NUM> has a single crystal layer <NUM> in an interface region at an interface with the silicon carbide layer <NUM>. When it is assumed that a lattice constant, in an equilibrium state, of the C-axis of a metal constituting the metal electrode <NUM> is L, the single crystal layer <NUM> in the interface region may include first region in which a C-axis lattice constant is smaller than L by <NUM>% to <NUM>% (each having L1). The single crystal layer <NUM> may be formed by heteroepitaxial growth.

In the present embodiment, the "interface region" in the metal electrode <NUM> means a region in the range of <NUM> from the interface between the metal electrode <NUM> and the silicon carbide layer <NUM>, in the thickness direction, toward the metal electrode <NUM> (the one side). On the further one side of the interface region of the metal electrode <NUM>, the metal electrode <NUM> may have a single crystal structure, a polycrystalline structure, or an amorphous structure.

As shown in <FIG>, the metal electrode <NUM> may be provided with a connection electrode <NUM>. In addition, the connection electrode <NUM> may be provided with a connection part <NUM>. The connection part <NUM> may be a wire or a connecting body.

The connection electrode <NUM> may contain aluminum, an aluminum alloy containing silicon, an aluminum alloy containing copper, titanium, or the like, or may include a laminated film of an aluminum alloy containing silicon, an aluminum alloy containing copper, or aluminum and titanium. Without being limited thereto, the connection electrode <NUM> may contain another metal such as copper, gold, or nickel.

A back surface electrode <NUM> may be provided on the other side (back surface side) of the silicon carbide semiconductor substrate <NUM>. The back surface electrode <NUM> may contain nickel, titanium, or the like. An insulating layer <NUM>, containing oxide or the like, may be provided in a region that is located on the one side (front surface side) of the silicon carbide layer <NUM> and in which a first electrode part <NUM> is not provided.

The single crystal layer <NUM> in the interface region may include the first region, in which the C-axis lattice constant is L1, at <NUM>% or more, or may include the first region at <NUM>% or more thereof. In the present embodiment, "containing the first region at A% or more" means that when one image is captured with a TEM, the first region in which the lattice constant is L1 can be confirmed at A% or more in all region (see <FIG>). However, whether or not the first region is at <NUM>% or more included may be confirmed by capturing a plurality of images (e.g., <NUM> to <NUM> images) with a TEM and using measurement results in the plurality of images.

When the metal contains Ti, the lattice constant L in an equilibrium state is <NUM>. Therefore, the fact that the C-axis lattice constant L1 is smaller than L by <NUM>% to <NUM>% means that the C-axis lattice constant L1 falls within the range of <NUM> to <NUM>. <FIG> is a graph in which the cumulative probabilities of the C-axis lattice constant L1 are plotted. The graph shows that when annealing is performed at <NUM> for <NUM> minutes in a vacuum state of 1E-<NUM> Pa (<NUM> × <NUM>-<NUM> Pa), the probability that the C-axis lattice constant L1 is about <NUM> or less is less than <NUM>%, whereas when annealing is performed at <NUM> for <NUM> minutes in a vacuum state of 1E-<NUM> Pa, the probability that the C-axis lattice constant L1 is about <NUM> or less is <NUM>%. TEM is used for the measurement, and the result is obtained by cross-sectional diffraction images (see <FIG> shows a cross-sectional TEM image at <NUM>,000x magnification, a cross-sectional TEM image at <NUM>,<NUM>,000x magnification, and a selected-area electron diffraction pattern. The lattice constant L1 of the single crystal can be measured from the selected-area electron diffraction pattern.

As confirmed by the inventors, it is found, as shown in <FIG>, that ϕBn (eV) decreases as the C-axis lattice constant L1 decreases. It has also been confirmed, as shown in <FIG>, that as a result of verification by first-principles calculations, the Fermi level (Ef) changes in a direction of lowering ϕBn by reducing the lattice constant. The value (C-axis lattice constant) on the horizontal axis shown in <FIG> represents a lattice constant when the cumulative probability is <NUM>%. Note that there is the relationship that the larger Ef (eV), the smaller ϕBn (eV).

The crystal structure of the silicon carbide layer <NUM> may have a hexagonal structure, or may have a hexagonal close-packed structure. The crystal structure of the metal electrode <NUM> may have a hexagonal structure, or may have a hexagonal close-packed structure. The metal of the metal electrode <NUM> in the interface region may contain Ti. However, without being limited thereto, the metal of the metal electrode <NUM> in the interface region may include a metal containing Ti as a main component, or may include Ni, Pt, Mo, a metal containing Ni as a main component, a metal containing Pt as a main component, or a metal containing Mo as a main component. However, from the viewpoint that ϕBn can be lowered to a small value, it is advantageous to use the metal electrode <NUM> containing Ti or the metal electrode <NUM> including a metal containing Ti as a main component, and it is particularly advantageous to use the metal electrode <NUM> containing Ti. Note that the term "main component" means that it occupies <NUM>% or more in mass percent, and the metal containing Ti as a main component means a metal containing <NUM> mass% or more of Ti.

Even when the metal of the metal electrode <NUM> in the interface region contains Ti, a metal layer containing Ni, Al, or the like may be provided on the one side of the electrode containing Ti.

The single crystal layer <NUM> in the interface region may include first region containing Ti in which the C-axis lattice constant L1 is <NUM> or less.

Next, an example of a manufacturing method will be described. In the following manufacturing example, an aspect will be described in which Ti is used as the metal electrode <NUM>.

A Ti layer is deposited on a substrate in which the silicon carbide layer <NUM> is provided on the silicon carbide substrate <NUM>. For the deposition of the Ti layer, electron beam deposition may be used, or sputtering may be used. A deposition rate is, for example, <NUM> to <NUM>/s (e.g., <NUM>/s), and the degree of vacuum at the time of the deposition of the Ti layer is, for example, 1E-<NUM> Pa to 1E-<NUM> Pa (e.g., 1E-<NUM> Pa).

Next, the substrate provided with the Ti layer is annealed (heated) at <NUM> or lower. The substrate provided with the Ti layer is annealed, for example, at <NUM> for <NUM> minutes to <NUM> minutes (e.g., <NUM> minutes). As a result, the metal electrode <NUM> including the Ti layer is generated.

Immediately after the Ti layer is deposited on the silicon carbide layer <NUM>, vacancies are included in the Ti layer in the interface region between the silicon carbide layer <NUM> and the Ti layer. When the Ti layer is annealed, crystallized of Ti proceeds while the vacancies are diffused outward. It is considered that when the annealing temperature is set to <NUM> to <NUM>, perfect crystal Ti (equilibrium state) is obtained, and the C-axis lattice constant increases (see <FIG>). As a result, ϕBn is saturated at a large value.

On the other hand, when the annealing is performed at <NUM> or lower (e.g., <NUM>) as in the present embodiment, the vacancies in the Ti layer are suppressed from being diffused outward, so that a state of including many vacancies can be realized. As a result, it is considered that stress is generated in the Ti layer, and the intervals between the Ti atoms tend to be uneven (see <FIG>). Then, region (first region) in which a lattice constant is smaller than that at the time of complete crystallization and region (second region) in which a lattice constant is larger than that therein are both generated. When the number of the region (first region) in which a lattice constant is small is larger than the number of the region (second region) in which a lattice constant is large, ϕBn can be lowered.

Here, <FIG> are simplified views for understanding the above description. In a region including the atoms arranged on the right-most in <FIG>, the interatomic distances between the arranged constituent atoms are constant L, and the average lattice constant in the C-axis direction is L. In a region including the atoms arranged second from the right in <FIG>, the interatomic distances between the arranged constituent atoms are uneven by being divided into L1, L2, and L. L1 is smaller than L. L2 is larger than L. However, since the number of the regions, in each of which the interatomic distances are L1, and the number of the regions, in each of which the interatomic distances are L2, are equal, the average lattice constant of the lattice constants in the C-axis direction is L in this region. In a region including the atoms arranged third from the right in <FIG>, the interatomic distances between the arranged constituent atoms are uneven by being divided into L1 and L. L1 is smaller than L. Therefore, the average lattice constant of the lattice constants in the C-axis direction is smaller than L in this region. In a region including the atoms arranged fourth from the right in <FIG>, the interatomic distances between the arranged constituent atoms are uneven by being divided into L1 and L. L1 is smaller than L. Therefore, the average lattice constant of the lattice constants in the C-axis direction is smaller than L in this region.

As a result, when the aspect of <FIG> is viewed as a whole, the average lattice constant in the C-axis direction is smaller than L. <FIG> can be said to show an actual measurement result supporting this. <FIG> shows that when annealing is performed at <NUM> or lower (here, <NUM>), region (second region) in which the lattice constant in the C-axis direction is large exist (a plot exists at a location where the C-axis lattice constant is about <NUM>), but region (first region) in which the lattice constant is small also exist (a plot also exists at a location where the C-axis lattice constant is about <NUM>). And, it is shown that the number of the region (second region), in which the lattice constant is large, is smaller than the number of region (first region) in which the lattice constant is small. That is, the lattice constant in the C-axis direction decreases on average. As a result, ϕBn decreases as described above.

It can also be confirmed that the lattice constant decreases by the fact that when one image is captured with TEM, the first region occupies a wider region than the second region. Alternatively, it may also be confirmed that the first region occupies a wider region than the second region by capturing a plurality of images (e.g., <NUM> to <NUM> images) with TEM and using measurement results in the plurality of images.

Note that as shown in <FIG>, it could be confirmed that ϕBn also decreased when the annealing was performed at <NUM> or higher, while as shown in <FIG>, when the annealing was performed at <NUM> or higher, the n value (ideal factor) was deteriorated. This is considered to be because a chemical reaction occurs between the Ti layer and the silicon carbide layer <NUM>. The value (C-axis lattice constant) on the horizontal axis shown in <FIG> also represents a lattice constant when the cumulative probability is <NUM>%, similarly to <FIG>.

Next, another manufacturing example different from the above will be described. Similarly to the manufacturing example <NUM>, a Ti layer is deposited on a substrate in which the silicon carbide layer <NUM> is provided on the silicon carbide substrate <NUM>. For the deposition of the Ti layer, electron beam deposition may be used, or sputtering may be used. A deposition rate is, for example, <NUM> to <NUM>/s (e.g., <NUM>/s), and the degree of vacuum at the time of the deposition of the Ti layer is, for example, 1E-<NUM> Pa to 1E-<NUM> Pa (e.g., 1E-<NUM> Pa).

Next, the substrate provided with the Ti layer is annealed (heated) at <NUM> to <NUM>. The substrate provided with the Ti layer is annealed, for example, at <NUM> for between <NUM> minutes and <NUM> minutes (inclusive) (e.g., <NUM> minutes). <FIG> is a graph showing a relationship between an annealing time when annealing is performed at <NUM> and ϕBn (eV), and it can be confirmed that ϕBn (eV) decreases when the annealing time is short.

As described above, immediately after the Ti layer is deposited on the silicon carbide layer <NUM>, a state is created at the interface between the silicon carbide layer <NUM> and the Ti layer, in which vacancies are included in the Ti layer. When the Ti layer is annealed, crystallized of Ti proceeds while the vacancies in the Ti layer are diffused outward. In this respect, even when annealing is performed at <NUM> to <NUM>, the vacancies in the Ti layer are suppressed from being diffused outward by shortening the annealing time. Therefore, a state in which many vacancies are included in the Ti layer can be realized, and region, in which a lattice constant is smaller than that at the time of complete crystallization, can be formed by generating stress. As a result, ϕBn can be lowered.

Next, a manufacturing example <NUM> different from the above manufacturing examples <NUM> and <NUM> will be described.

Also in the manufacturing example <NUM>, a Ti layer is deposited on a substrate in which the silicon carbide layer <NUM> is provided on the silicon carbide substrate <NUM>, similarly to the manufacturing examples <NUM> and <NUM>. For the deposition of the Ti layer, electron beam deposition may be used, or sputtering may be used. However, a deposition rate in the manufacturing example <NUM> is set to be less than <NUM>/s. For example, the deposition rate may be, for example, <NUM>/s or less (e.g., <NUM>/s), and the degree of vacuum at the time of the deposition of the Ti layer is, for example, 1E-<NUM> Pa to 1E-<NUM> Pa (e.g., 1E-<NUM> Pa).

Next, the substrate provided with the Ti layer is annealed (heated) at <NUM> to <NUM>. The substrate provided with the Ti layer is annealed, for example, at <NUM> for <NUM> minutes to <NUM> minutes (e.g., <NUM> minutes).

By reducing the deposition rate as in the present manufacturing example, the probability that molecules, atoms, ions, and the like other than Ti fly to the front surface of the silicon carbide layer <NUM> at the time of the deposition relatively increases. Therefore, a state is created in which more vacancies are included in the Ti layer at the interface between the Ti layer and the silicon carbide layer <NUM>. Therefore, even when the annealing temperature is set to <NUM> to <NUM> and the annealing time is set to <NUM> minutes, more vacancies remain in the Ti layer. Therefore, region in which a lattice constant is smaller than that at the time of complete crystallization can be formed by generating stress, and ϕB can be lowered.

The results of changing, by the inventors of the present application, the deposition rate under conditions in which the annealing is performed at <NUM> for <NUM> minutes are as shown in Table <NUM> below. These results are shown in <FIG>.

Next, a manufacturing example <NUM> different from the manufacturing examples <NUM> to <NUM> will be described.

Also in the manufacturing example <NUM>, a Ti layer is deposited on a substrate in which the silicon carbide layer <NUM> is provided on the silicon carbide substrate <NUM>, similarly to the manufacturing examples <NUM> to <NUM>. For the deposition of the Ti layer, electron beam deposition may be used, or sputtering may be used. However, the degree of vacuum at the time of the deposition in the manufacturing example <NUM> is set to 5E-<NUM> Pa or more. For example, a deposition rate is, for example, <NUM> to <NUM>/s (e.g., <NUM>/s), and the degree of vacuum at the time of the deposition of the Ti layer is 5E-<NUM> Pa or more (e.g., <NUM>. 3E-<NUM> Pa). If the degree of vacuum is excessively increased, various problems occur, and thus the upper limit value is 1E-<NUM> Pa.

By increasing the degree of vacuum as in the present manufacturing example, the probability that molecules, atoms, ions, and the like other than Ti fly to the front surface of the silicon carbide layer <NUM> at the time of the deposition relatively increases. Therefore, a state is created in which more vacancies are included in the Ti layer at the interface between the Ti layer and the silicon carbide layer <NUM>. Therefore, even when the annealing temperature is set to <NUM> to <NUM> and the annealing time is set to <NUM> minutes, more vacancies remain in the Ti layer. Therefore, region in which a lattice constant is smaller than that at the time of complete crystallization can be formed by generating stress, and ϕBn can be lowered.

The results of the inventors of the present application setting the degree of vacuum to <NUM>. 3E-<NUM> Pa under conditions in which the annealing is performed at <NUM> for <NUM> minutes are as shown in Table <NUM> below, and it could be confirmed that ϕBn could be lowered.

Next, effects of the present embodiment having the above-described configuration will be described. Note that all aspects described in the "effects" can be adopted in the above configuration.

In the present embodiment, when an aspect is adopted in which the single crystal layer <NUM> in the interface region of the metal electrode <NUM> includes first region in which the C-axis lattice constant L1 is smaller than the lattice constant L in an equilibrium state by <NUM>% to <NUM>%, ϕBn can be lowered without changing the material of the metal electrode <NUM>.

When the single crystal layer <NUM> in the interface region includes the first region, in which the C-axis lattice constant is L1 (value smaller than L by <NUM>% to <NUM>%), at <NUM>% or more, ϕBn can be lowered more reliably. In addition, when the single crystal layer <NUM> in the interface region includes the first region, in which the C-axis lattice constant is L1 (value smaller than L by <NUM>% to <NUM>%), at <NUM>% or more, ϕBn can be lowered even more reliably (see <FIG> and <FIG>).

When the metal electrode <NUM> in the interface region contains hexagonal Ti and the silicon carbide layer <NUM> in contact with the Ti has a hexagonal structure, ϕBn can be lowered more reliably.

When the single crystal layer <NUM> in the interface region contains Ti, the originally low ϕBn can be further lowered, and when the single crystal layer includes the first region containing Ti in which the C-axis lattice constant L1 is <NUM> or less, ϕBn can be lowered more reliably.

Claim 1:
A silicon carbide device comprising:
a silicon carbide layer (<NUM>); and
a metal layer provided on the silicon carbide layer (<NUM>),
wherein the metal layer has a single crystal layer (<NUM>) in an interface region at an interface with the silicon carbide layer (<NUM>),
when it is assumed that a lattice constant, in an equilibrium state, of a metal constituting the metal layer is L, the single crystal layer (<NUM>) in the interface region includes a first region in which a lattice constant L1 is smaller than L by <NUM>% to <NUM>%.