Patent Description:
This application relates to processors, and more particularly to the load step balancing of a processor clock frequency in response to changes in processor load.

The amount of processing performed per clock cycle by a processor is subject to change as the associated computations become more intensive. During low load periods, relatively few execution units such as multiply-and-accumulate (MAC) units are active in each processor clock cycle. But in response to sudden load changes, the number of active execution units may increase dramatically. The current demanded by the processor from its power supply rail will thus change in concert with the change in processing load. The resulting increase in current demand by the processor may cause its power supply voltage to droop undesirably, resulting in fault conditions.

It is thus conventional to lower a processor's clock frequency during periods of increased processing demand. For example, the clock frequency may be halved during such increased load periods. But lowering the clock frequency by too much results in the power supply voltage increasing undesirably, which leads to fault conditions such as hold violations. Conversely, lowering the clock frequency by too little results in low voltage fault conditions. Prior art load balancing techniques thus wavered between power distribution network (PDN) fault conditions resulting from too-high of a power supply voltage and fault conditions resulting from too-low of a power supply voltage.

Accordingly, there is a need in the art for improved load step balancing of the processor clock frequency in response to processor load increases. Attention is drawn to <CIT> describing systems and methods for power distribution network (PDN) droop/overshoot mitigation. In one aspect, a method for activating one or more processors comprises reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors. The method also comprises activating the one or more processors after the frequency of the clock signal is reduced, and increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated. Attention is further drawn to <CIT> describing an apparatus comprising a clock shaper configured to derive a frequency of a reference clock signal into a plurality of n frequencies associated to a plurality of n gated clocks, Clock <NUM>, Clock <NUM>,. , Clock n-<NUM>, and configured to generate a plurality of m clock enable signals, where n is a number of the gated clocks and m corresponds to a divisor; a plurality of n coupled clock selection and gating units receiving the reference clock and the plurality of m clock enable signals, and configured to select one of the plurality of m clock enable signals and to gate to an output clock; and a phase decoding unit configured to decode the plurality of m clock enable signals based on a plurality of received division value per clock signals, and configured to generate a plurality of n clock selection signals, wherein one of the plurality of n clock selection signals corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks; wherein the plurality of n coupled clock selection and gating units are responsive to the plurality of n clock selection signals to generate the output clock with the selected frequency. Further attention is drawn to <CIT> describing supply voltage droop management circuits for reducing or avoiding supply voltage droops. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.

To minimize PDN noise, the processor clock frequency is decreased proportionally to a processor load increase. To quantify the load increase, a default number of execution units that are active while the processor operates in a default mode of operation are determined. The default mode of operation corresponds to a low load state. During a transition from the default mode of operation to an increased load mode of operation in which the processor operates in an increased load mode of operation, the number of active execution units is increased by a multiple greater than one of the default number. During this transition, the processor clock frequency is decreased so as to be inversely proportional to the multiple of the default number of active execution units. Because of this proportionality, a current drawn by the processor from a power rail does not significantly change while the processor transitions from the default mode of operation to the increased load mode of operation. A power supply regulating a power supply voltage carried on the power rail may thus keep the power supply voltage from undershooting or overshooting a desired value despite the sudden increase in load for the processor.

These and other advantageous features may be better appreciated through the following detailed description.

Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows.

Turning now to the drawings, <FIG> illustrates a system <NUM> configured for load step balancing as disclosed herein. In one implementation, system <NUM> may comprise a system-on-a-chip (SoC) or another type of suitable integrated circuits. A processor such as a graphics processing unit (GPU) <NUM> includes a plurality of execution units <NUM>. It will be appreciated, however, that the load balancing technique disclosed herein is widely applicable to other types of processors such as general purpose central processing units (CPUs). As known in the processor arts, each active execution unit <NUM> is configured to execute instructions for a computer program for GPU <NUM>. During a default load state or mode of operation (lowest load state) for GPU <NUM>, only a default number of execution units <NUM> are active in each clock cycle of a processor clock signal <NUM>. During this default load state, processor clock signal <NUM> cycles at a maximum frequency denoted herein as FMAX. Based upon the default number of active execution units <NUM> and the clocking frequency of FMAX, GPU <NUM> will draw a current I from a power rail <NUM>. A power source such as power management integrated circuit (PMIC) <NUM> regulates power rail <NUM> to keep it charged to a desired power supply voltage for GPU <NUM>. But the load for GPU <NUM> may suddenly increase such that the number of active execution units <NUM> in each clock cycle significantly increases over the default number that are active during the default load state. For example, should the number of active execution units <NUM> increase to four times the default number, GPU <NUM> will draw a current of approximately four times the default current I from power rail <NUM>.

A power supply such as PMIC <NUM> cannot maintain the power supply voltage in the face of such a sudden increase in current demand. Processor system <NUM> is thus configured to practice an intelligent load balancing such that the processor clocking frequency is reduced proportionally to the load increase. In the following discussion, it will be assumed that each execution unit <NUM> is a multiply-and-accumulate (MAC) unit. However, it will be appreciated that other suitable units such as an arithmetic-logic unit (ALU) or a floating point unit (FPU) may form execution units <NUM> in alternative implementations. The average current iavg(t) drawn from power rail <NUM> during operation by GPU <NUM> at clock frequency of fclk then becomes: <MAT> where NMAC is the number of active MAC units active in each clock cycle, α is a proportionality factor for the current demand for each active MAC unit that depends upon the MAC unit capacitance and the power supply voltage, and β represents the dynamic leakage.

To establish load balance equality such that there is no change in the rate of current consumption dI/dt by GPU <NUM> despite the sudden increase in load, the starting current consumption in the default mode of operation (Iinitial(t)) should equal the current consumption after the load step increase (Istep(t)). Substitution into Equation (<NUM>) for the initial and final currents before and after the load step increase leads to the following equality: <MAT> where Ninitial is the default number of active MAC units during default operation of GPU <NUM>, fMAX is the default clock frequency, Nfinal is the number of active MAC units after the load increase, and fstep is the reduced processor clock frequency after the load step increase.

Solving for the reduced clock frequency fstep of Equation (<NUM>) leads to the following expression: <MAT> where Nfinal equals Ninitial plus some additional number Δn of active MAC units.

As implied by the suffix "MAX," the default clocking frequency fMAX is the maximum clocking frequency whereas the stepped clock frequency fstep in response to the load increase is lower than fMAX. By making the clocking frequency reduction proportional to the load increase as follows from Equation (<NUM>), system <NUM> ensures that the current consumption from the power rail <NUM> is effectively unchanged despite the sudden transition from the default mode of operation to an increased load mode of operation for GPU <NUM>. The resulting reduction in clocking frequency is thus quite advantageous because the power supply voltage for GPU <NUM> will neither overshoot nor undershoot from its desired value despite the sudden processor load increase. Moreover, since the frequency decrease is proportional to the load increase, it doesn't matter if the load increase is very significant or merely significant because the frequency decrease is tailored to the load increase.

Another advantage of this frequency reduction is that a clock source such as a phase-locked loop (PLL) from which processor clock signal <NUM> is derived may remain locked despite the changes in clocking frequency. For example, a PLL <NUM> in system <NUM> drives a clock divider <NUM> with a source clock signal <NUM> that cycles at a multiple of fMAX, e.g., two times fMAX. Clock divider <NUM> divides source clock signal <NUM> to produce processor clock signal <NUM>. This division may be approximated by a ratio (N/M) of integers N and M. The resulting clock division keeps certain edges of processor clock signal <NUM> synchronous with corresponding edges in source clock signal <NUM> so that PLL <NUM> may remain locked. For example, suppose the integer M equals <NUM>. In that case, the following values of N in the following Table <NUM> may be used in clock divider <NUM> to produce the following reductions of clock frequency:.

Note the numerator N in the ratio N/M does not equal an integer when the clock frequency is reduced by <NUM>% and also by <NUM>% when M equals <NUM>. However, for the remaining clock frequency reductions in response to load increases, N has an integer value. The percentages from Table <NUM> are plotted as a function of the execution unit ratio increase (Nfinal/Ninitial) in <FIG>. The decrease from one frequency step to the next becomes asymptotically less with each increase in execution unit usage. For example, a doubling of execution unit usage from the default demand usage leads to a reduction of clocking frequency by <NUM>% whereas a six-fold increase in demand from the default mode of operation leads to a reduction of clocking frequency of just <NUM>%. Although there is only one processor clock signal <NUM>, the clocking of GPU <NUM> at the <NUM>% frequency of Fmax may be deemed to be clocking of GPU <NUM> by a first processor clock signal. Similarly, the clocking of GPU <NUM> at the <NUM>% frequency may be deemed to be a clocking of GPU <NUM> by a second processor clock signal, and so on for the remaining clock frequency percentages.

Waveforms for the resulting processor clock signals <NUM> based upon an appropriate selection of edges from source clock signal <NUM> are shown in <FIG>. For example, to produce the <NUM>% clock signal having the FMAX frequency for clocking GPU <NUM> during its default operation, clock divider <NUM> (<FIG>) may respond to the rising edges of source clock signal <NUM> to produce corresponding rising and falling edges of the <NUM>% clock signal. In particular, the rising edges for source clock signal <NUM> may be divided into even and odd rising edges. A first rising edge, a third rising edge, and so on form a set of odd rising edges whereas a second rising edge, a fourth rising edge, and so on form a set of even rising edges. Clock divider <NUM> produces a rising edge in the <NUM>% clock signal responsive to the odd rising edges and produces a falling edge in the <NUM>% clock signal responsive to the even rising edges. It will be appreciated that clock divider <NUM> may instead be configured to respond to falling edges in source clock signal <NUM>. The resulting duty cycle for the <NUM>% clock signal is <NUM>-<NUM>. Note that PLL <NUM> may advantageously remain locked while clock divider <NUM> divides source clock signal <NUM> into the <NUM>% form of processor clock signal <NUM> since clock divider <NUM> is responding to edges in source clock signal <NUM> to produce corresponding edges in processor clock signal <NUM>.

The division by clock divider <NUM> to form the reduced frequencies for processor clock signal <NUM> is analogous to the division for forming the <NUM>% clock signal. For example, to divide source clock signal <NUM> to the <NUM>% clock frequency, clock divider <NUM> responds to a first rising edge of source clock signal <NUM> to produce a first rising edge of processor clock signal <NUM> having the <NUM>% clock frequency. To achieve a frequency of <NUM>% of the period of the <NUM>% frequency, clock divider <NUM> responds to a falling edge of source clock signal <NUM> that occurs <NUM> clock cycles after its initial rising edge. Given this period for the <NUM>% clock frequency equaling <NUM> clock cycles of source clock signal <NUM>, the duty cycle for the <NUM>% clock frequency cannot be <NUM>-<NUM>. However, all the remaining decreased (stepped) clock frequencies correspond to a <NUM>-<NUM> clock cycle. For example, the period of the <NUM>% clock signal equals <NUM> cycles of source clock signal <NUM> so the rising and falling edges for the <NUM>% clock signal are each separated by <NUM> periods for source clock signal <NUM>. Similarly, the period for the <NUM>% clock signal equals four cycles of source clock signal <NUM> so that the rising and falling edges for the <NUM>% clock signal are separated by two cycles of source clock signal <NUM>. The period for the <NUM>% clock signal equals five cycles of source clock signal <NUM> so that the rising and falling edges for the <NUM>% clock signal are separated by <NUM> cycles of source clock signal <NUM>. Similarly, the period for the <NUM>% clock signal (<NUM> cycles of source clock signal <NUM>), the period for the <NUM>% clock signal (<NUM> cycles of source clock signal <NUM>), and the period for the <NUM>% clock signal (<NUM> cycles of source clock signal <NUM>) all equal a whole number of cycles of the source clock signal <NUM> so that their duty cycles are <NUM>-<NUM>. It will be appreciated that source clock signal <NUM> need not be overclocked at twice the frequency of FMAX but may instead be clocked at other even multiples of FMAX (e. g, four times, eight times, etc.). Moreover, these alternative overclocking frequencies allow clock divider <NUM> to achieve alternative clock divisions besides just the percentages shown in <FIG> and <FIG>. These various clock frequency percentages are all instantiations of processor clock signal <NUM>.

Referring again to <FIG>, GPU <NUM> includes an activity predictor (dI/dt) <NUM> that alerts system <NUM> regarding any upcoming increases in load demand by its MACs. For example, activity predictor <NUM> may predict imminent increases in load demand by examining the operation code (opcode) that will be executed by the MACs. As illustrated, activity predictor <NUM> is implemented through software running on GPU <NUM> but it will be appreciated that dedicated hardware may also be used to form the activity predictions. In the following discussion, it will be assumed that the activity predictions from activity predictor <NUM> are digital activity codes that map to a particular integer value for the numerator N used in the N/M division performed by clock divider <NUM>. As noted earlier, only certain ones of the divided clock signals from clock divider <NUM> that are used to form processor clock signal <NUM> actually correspond to integer values for N if the divisor M is assumed to equal forty-eight. But it is a useful model to assume that the clock division corresponds to a division by the ratio N/M formed by integers N and M. With regard to a value of M equaling forty-eight, the <NUM>% clock signal corresponds to a value of N equaling twenty-four. An activity code for the default mode of operation would thus map to a value of N equaling twenty-four. In such an implementation, there may thus be twenty-three other activity codes that would map to reduced values of N ranging from twenty-three all the way down to one.

But keeping PLL <NUM> locked such that processor clock signal <NUM> is synchronous with source clock signal <NUM> allows for only certain values of stepped clock frequencies. For example, the percentages of <FIG> and <FIG> discussed above provide for just seven stepped down clock frequencies ranging from the <NUM>% clock signal to the <NUM>% clock signal. System <NUM> thus includes a controller <NUM> that is configured to respond to the activity codes to command clock divider <NUM> to output one of the stepped clock signals thus quantizes the various activity codes from activity predictor <NUM>. Such a quantizing is effectively a quantizing of the multiple of the default number of active MACs to a quantized value. To perform the mapping between the increased load identified by the activity codes and the corresponding reduced clocking frequency, controller <NUM> includes a look-up table (LUT) <NUM>. It will be appreciated that a software-based mapping may be performed in alternative implementations. LUT <NUM> also includes a logic circuit that quantizes the various load levels into the reduced frequencies discussed with regard to <FIG> and <FIG>. For example, the <NUM>% clocking frequency corresponds to a load increase of <NUM> times as many MAC units being used in each clock cycle as compared to the MAC usage in the default mode of operation. Similarly, the <NUM>% clock frequency corresponds to a load increase of <NUM> times as many MAC units being used as compared to the usage in the default mode of operation. LUT <NUM> may thus quantize by mapping minor increases in load to the default clocking frequency of FMAX. For example, LUT <NUM> may quantize all activity codes that correspond to an initial minor load range of <NUM> to <NUM> times the default number of MAC units to the default clocking frequency of FMAX. A first significant load range such as from <NUM> to <NUM> times the default MAC usage may be mapped by LUT <NUM> to the <NUM>% clocking frequency. The entire expected range of MAC usage increase may thus be quantized and mapped in this fashion to a corresponding reduced clocking frequency. LUT <NUM> then commands clock divider to achieve the appropriate clock division. The resulting change in current draw dI/dt from power rail <NUM> as GPU <NUM> transitions from the default mode of operation to an increased load mode of operation will thus be substantially zero. In particular, the change in current draw dI/dt will equal zero should the MAC usage increase correspond exactly to the <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> multiples of the default number of MAC units that are discussed with regard to <FIG> and <FIG>. But the change in current draw dI/dt will still be substantially zero if the MAC usage increase is instead skewed with regard to these exact multiples as quantized through LUT <NUM>.

In one implementation, controller <NUM> may be deemed to comprise a means for quantizing the multiple of the default number of the MAC units to a quantized value and for mapping the quantized value into a reduced clock frequency that is inversely proportional to the quantized value and to further comprise a means for controlling clock divider <NUM> so that the divided frequency equals fMAX while GPU <NUM> is configured to operate in the default mode of operation and so that the divided frequency equals the reduced clock frequency while the GPU <NUM> is configured to transition from the default mode of operation into the increased load mode of operation.

Some example signal waveforms for system <NUM> are shown in <FIG> with regard to the transition from the default mode of operation to an increased load mode of operation. In particular, activity predictor <NUM> (<FIG>) may assert a significant load step signal <NUM> should the load increase be greater than the initial minor load range discussed above. In particular, there is an initial minor load range from the 1X multiple of the default number of active MAC units to some slightly increased multiple such as <NUM>. Load increases falling within this initial minor range are not significant enough to trigger a clock division since the increase in load is relatively minor. Thus, activity predictor <NUM> may be configured to assert a significant load step signal <NUM> only when the load increase is such that the multiple of the default number of active MAC units is above this initial minor range. An activity code <NUM> changes in conjunction with the assertion of significant load step signal <NUM>. LUT <NUM> of system <NUM> maps the change in activity code <NUM> to a stepped clock frequency designated as Fstep in <FIG> such that the clocking frequency or clocking rate of GPU <NUM> is dropped from FMAX to the Fstep frequency. Controller <NUM> asserts a step complete signal <NUM> after the clocking frequency is dropped whereupon a set <NUM> of additional MAC units are enabled in the increased load mode of operation.

But note that a power source such as PMIC <NUM> can respond to the increased current demand that would result from increasing the load while GPU <NUM> is clocked at the maximum frequency FMAX so long as the change in load is gradual as opposed to the sudden load transition addressed by controller <NUM> and clock divider <NUM>. Controller <NUM> is thus configured to gradually increase the clocking frequency following the transition period while GPU <NUM> is clocked at the stepped clock frequency. For example, activity predictor <NUM> (or some other suitable source) may assert a step enable signal <NUM> while clock divider <NUM> should apply the appropriate frequency step division during the transition period from the default mode of operation to the increased load mode of operation. When step enable signal <NUM> is again de-asserted, controller <NUM> (such as through LUT <NUM>) commands clock divider <NUM> to begin ramping the clock frequency back to the maximum frequency FMAX. But as discussed with regard to <FIG> and <FIG>, there is only a finite set of reduced clock frequencies that may be synchronously produced from an overclocked source such as source clock signal <NUM>. The ramping of frequency thus is not analog but instead involves a stepping up from the reduced clock frequency through any intervening reduced clock frequencies from the finite set of reduced clock frequencies until the maximum frequency FMAX is reached.

For example, suppose processor clock signal <NUM> is stepped to cycle at the <NUM>% clock frequency. In response to the de-assertion of step enable signal <NUM> at the end of the transition period, controller <NUM> may then command clock divider <NUM> to increase the clock frequency to the <NUM>% clock frequency for a first number of cycles and then to increase to the <NUM>% clock frequency for a second number of cycles. Finally, controller <NUM> would increase the clock frequency to FMAX for a third number of cycles before the ramping frequency increase is deemed to be complete.

The resulting control of the frequency for processor clock signal <NUM> is quite advantageous as the clocking frequency is deterministically known at all times during the transition period and also during the ramping back up period. Other processes in GPU <NUM> may thus benefit from this deterministic knowledge of the clocking frequency. For example, consider the table shown in <FIG> for the finite set of stepped clock frequencies discussed with regard to <FIG> and <FIG>. Each step down frequency target corresponds to a time interval count back to the <NUM>% (FMAX) frequency. The time interval count corresponds to how many different stepped frequencies (including FMAX) are utilized during the transition and ramping back periods. For example, the <NUM>% clock frequency is the initial stepped down frequency from FMAX. The time interval count is thus <NUM> because the clock frequency will first be stepped to <NUM>% for the transition period and then increased again to <NUM>% during the ramping up period. But the number of cycles for processor clock signal <NUM> at each distinct stepped frequency (including the <NUM>% frequency during the ramp back period) is known. For example, processor clock signal <NUM> will cycle a first predetermined number of periods equaling <NUM> periods upon stepping down to the <NUM>% clock frequency. It will then cycle for a second predetermined number of periods equaling <NUM> periods at the <NUM>% clock frequency to complete the ramping back period to achieve the maximum clocking frequency FMAX. In this fashion, the clock frequency is deterministically determined at all times during the stepped down period and also during the ramping back period. To keep the transition period approximately the same for all the various different load increases, the number of clock periods is reduced for the stepped period as the clock period is slowed. For example, the stepped period at the <NUM>% clock frequency is just <NUM> cycles. It will be appreciated that the cycle numbers shown in <FIG> are merely representative and may be varied in alternative implementations. The increase in load for GPU <NUM> that maps to the <NUM>% clocking frequency may be designated as a first increased load mode of operation. Similarly, the increase in load for GPU <NUM> that maps to the <NUM>% clocking frequency may be designated as a second increased load mode of operation, and so on.

Referring again to <FIG>, note that other processes may also instruct clock divider <NUM> to change the frequency of processor clock signal <NUM>. An arbitrator <NUM> in controller <NUM> is thus configured to arbitrate between the load step balancing frequency changes discussed herein and alternative techniques to adjust the clocking frequency. For example, an existing clock management technique may be denoted as limits management hardware (LMH) as issued from an LMH requestor <NUM> implemented through software on GPU <NUM>. Arbitrator <NUM> may be configured to give priority to the load step balancing requests from activity predictor <NUM> as opposed to LMH requests from LMH requestor <NUM>. Should only an LMH request be active, LUT <NUM> may map the LMH command into a certain value N for the N/M division by clock divider <NUM>. As discussed above, clock divider <NUM> cannot achieve arbitrary values for the ratio N/M but instead produces only the finite set of reduced clock frequencies discussed herein. But clock divider <NUM> may mimic the desired values for N and M as commanded by a particular LMH setting by dithering between appropriate frequencies from the finite set of reduced clock frequencies. For example, suppose M is <NUM> and N is <NUM>. The resulting ratio (<NUM>/<NUM>) cannot be achieved by clock divider <NUM> since it can only respond to edges of source clock signal <NUM>. But clock divider <NUM> can synchronously step down the frequency to the <NUM>% clock frequency and also to the <NUM>% clock frequency. Thus, clock divider <NUM> can approximate the N/M ratio of <NUM>/<NUM> by an appropriate dithering between the <NUM>% clock frequency and the <NUM>% clock frequency. In this fashion, clock divider <NUM> may approximate any desired value of N/M as N is reduced from its value at FMAX (which is <NUM> if M is <NUM>) all the way to <NUM>.

An example method of load step balancing will now be discussed with regard to <FIG>. The method includes an act <NUM> of clocking a processor at a default clocking frequency while the processor operates in a default mode of operation using a default number of execution units and while the processor draws a default current from a power rail. The operation of GPU <NUM> in the default mode of operation prior to a significant load increase in an example of act <NUM>. The method also includes an act <NUM> that is responsive to a projected increase in processor load in which the processor operates in an increased load mode of operation using a first multiple of the default number of execution units and includes determining a first decreased clocking frequency that is inversely proportional to the first multiple of the default number of execution units, wherein the first multiple is a number greater than one and the first decreased clocking frequency is less than the default clocking frequency. The mapping within LUT <NUM> of a load increase to a reduced clocking frequency is an example of act <NUM>. Finally, the method includes an act <NUM> of clocking the processor at the first decreased clocking frequency while the processor performs a transition from the default mode of operation to the first increased load mode of operation so that the processor draws substantially the default current from the power rail during the transition from the default mode of operation to the first increased load mode of operation. The transition of GPU <NUM> to an increased load mode of operation while being clocked at a reduced clocking frequency such as from the finite set of reduced clocking frequencies discussed with regard to <FIG> and <FIG> is an example of act <NUM>.

Claim 1:
A method, comprising:
clocking (<NUM>) a processor (<NUM>) at a default clocking frequency while the processor operates in a default mode of operation using a default number of execution units (<NUM>) and while the processor draws a default current from a power rail (<NUM>);
responsive (<NUM>) to a first projected increase in a load for the processor in which the processor operates in a first increased load mode of operation using a first multiple of the default number of execution units, determining a first decreased clocking frequency that is inversely proportional to the first multiple of the default number of execution units, wherein the first multiple is a number greater than one and the first decreased clocking frequency is less than the default clocking frequency; and
clocking (<NUM>) the processor at the first decreased clocking frequency while the processor performs a transition from the default mode of operation to the first increased load mode of operation so that the processor draws substantially the default current from the power rail during the transition from the default mode of operation to the first increased load mode of operation.