Patent Description:
In the field of electronics, class D amplifiers offer improved efficiency over other designs such as class AB amplifiers. For example, a class AB amplifier may operate at <NUM>% efficiency when amplifying a <NUM>% full scale signal. In contrast, a class D amplifier may operate at <NUM>% efficiency when amplifying the same <NUM>% full scale signal. Indeed, the smaller the signal, the bigger the efficiency advantage that is provided by a class D amplifier over a class AB amplifier.

However, class D amplifiers present design challenges. In operation, class D amplifiers may use differential pulse width modulation (PWM) signals. When such signals are switched between common mode (e.g., both low or both high) and differential mode (e.g., one low and one high), disturbances are introduced. Such disturbances may include, for example, analog voltage transitions that are not part of the original signal intended to be amplified. If left unchecked, such disturbances can require the amplifier to use additional power as it integrates the unintended voltage transitions and also introduces noise and distortion into the final amplified signal.

Conventionally, such disturbances may be mitigated by the use of large capacitors (e.g., <NUM> pf). However, such capacitors can complicate or restrict the design of products incorporating them as the capacitors may consume large portions of the physical area available in a circuit. This problem is especially acute in cases where a class D amplifier is desired to be implemented with a small form factor, such as consumer electronic devices. The prior art document <CIT> (<CIT>), document <CIT> (<CIT>)and document <CIT> (<CIT>) disclose relevant teachings on how a common mode disturbance can be minimized by acting on inputs of an integrator of a class-D amplifier.

In accordance with embodiments set forth herein, various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. For example, an active common mode compensation circuit may be used to apply voltage offsets to the inputs of an integrator of a loop filter of the amplifier. Such offsets may be used to offset disturbances resulting from the switching of differential PWM signals between common mode and differential mode configurations. As a result, the integrator may be operated with reduced power, reduced noise, and reduced distortion. In addition, the compensation circuit may reduce or eliminate the need for large capacitors that are conventionally used for passively reducing disturbances.

In one embodiment, an amplifier includes a power stage configured to generate first and second PWM signals; an integration stage comprising input nodes configured to receive an input differential analog signal, wherein the integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal; and an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode.

In another embodiment, a method includes providing, by a power stage of an amplifier, first and second PWM signals to an integration stage of the amplifier; receiving, at input nodes of the integration stage, an input differential analog signal; generating, by the integration stage, an output differential analog signal in response to the PWM signals and the input differential analog signal; and providing, by an active compensation circuit of the amplifier, a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode.

A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.

Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows.

In accordance with embodiments set forth herein, various techniques are provided to reduce common mode disturbance associated with a loop filter of an amplifier. For example, an active common mode compensation circuit may be used to apply voltage offsets to the inputs of an integrator of a loop filter of the class D amplifier. Such an approach can reduce or eliminate conventional capacitors that may be otherwise be used in a low pass filter to passively reduce common mode disturbance. In addition, such an approach permits a differential current source signal to be applied directly to the integrator in some embodiments.

Turning now to the drawings, <FIG> illustrates a system <NUM> including a class D amplifier <NUM> in accordance with an embodiment of the disclosure. In various embodiments, system <NUM> may be any appropriate system with electronics used to amplify signals. For example, in some embodiments, system <NUM> may be a wireless headset system (e.g., a Bluetooth headset) used to amplify audio signals for listening by a user. System <NUM> may be other types of consumer electronic devices or other systems in various embodiments.

Amplifier <NUM> includes a loop filter <NUM>, an analog-to-PWM converter <NUM>, a power stage <NUM>, and feedback paths 150A-B. In operation, loop filter <NUM> integrates a differential analog signal through one or more integration stages (e.g., further shown in <FIG> and <FIG>). Converter <NUM> converts the integrated differential analog signal to differential PWM signals. Power stage <NUM> amplifies the differential PWM signals to provide PWM signals pwmp and pwmm which may be combined as appropriate for use (e.g., applied to one or more additional components <NUM> (e.g., a speaker or other appropriate component) of system <NUM>. As shown, amplified PWM signals pwmp and pwmm are fed back to loop filter <NUM> through feedback paths 150A-B to operate loop filter <NUM> as further discussed herein.

<FIG> illustrates a signal source <NUM>, an integration stage <NUM>, and an active compensation circuit <NUM> of loop filter <NUM> provided in amplifier <NUM> in accordance with an embodiment of the disclosure.

Signal source <NUM> may be any signal source desired to be amplified by amplifier <NUM>. In <FIG>, signal source <NUM> is a current source digital-to-analog converter (CSDAC). In this case, signal source <NUM> provides an input differential analog current signal that is received and integrated by integration stage <NUM>.

Integration stage <NUM> includes an integrator <NUM> (e.g., an operational amplifier and/or other appropriate integration circuit) with input nodes 214A-B and output nodes 216A-B. Input nodes 214A-B receive the differential analog current signal provided by signal source <NUM>. Output nodes 216A-B provide a resulting output differential analog signal (e.g., an integrated differential analog signal) to an appropriate downstream component (e.g., another integration stage as shown in <FIG> or converter <NUM>) which is also fed back to input nodes 214A-B through feedback paths as shown.

Integration stage <NUM> further includes resistors 218A-B and 220A-B. Resistors 220A and 220B receive amplified PWM signals pwmp and pwmm from power stage <NUM> through feedback paths 150A-B (e.g., shown in <FIG>). As PWM signals pwmp and pwmm alternate between low and high voltages (e.g., between <NUM> volts and <NUM> volts, between <NUM> volts and <NUM> volts, or other voltages) the differential analog current signal provided by signal source <NUM> will be converted to input voltages at input nodes 214A-B as a result of current flow through resistors 218A-B and 220A-B. In this regard, the voltages at input nodes 214A-B to be integrated by integrator <NUM> are generated in response to the differential analog current signal and the switching of the PWM signals pwmp and pwmm between low and high voltages (e.g., voltage transitions of the PWM signals pwmp and pwmm).

In various embodiments, as PWM signals pwmp and pwmm cycle, they may exhibit both differential mode and common mode behavior. In differential mode, PWM signals pwmp and pwmm exhibit different voltages (e.g., low and high respectively, or high and low respectively). In common mode, PWM signals pwmp and pwmm exhibit the same voltages (e.g., both low, or both high).

As discussed, when PWM signals pwmp and pwmm are switched between common mode (e.g., both low or both high) and differential mode (e.g., one low and one high), disturbances are introduced. For example, in <FIG>, such disturbances may manifest as unintended changes in voltage at input nodes 214A-B. Such disturbances can require integrator <NUM> to use additional power as it integrates the unintended voltage transitions and also introduces noise and distortion into the final amplified signal.

In order to reduce the disturbances, loop filter <NUM> further includes compensation circuit <NUM>. Compensation circuit <NUM> includes transistors 252A-B, circuit path <NUM>, and logic circuits 256A-B. As shown, logic circuits 256A-B (e.g., OR and AND gates, respectively) receive PWM signals pwmp and pwmm and provide resulting logic output signals to gates of transistors 252A-B. PMOS transistor 252A is connected to a voltage source (labeled pvddhp) and NMOS transistor 252B is connected to ground. Transistors 252A-B provide a compensation signal (e.g., labeled comp) to circuit path <NUM> (e.g., and therefore also to resistors 222A-B) synchronously with and in response to PWM signals pwmp and pwmm in accordance with the following Table <NUM>:.

As set forth in Table <NUM>, a high compensation signal value (e.g., a voltage of pvddhp) will be provided to circuit path <NUM> and resistors 222A-B when both PWM signals pwmp and pwmm are low (e.g., low common mode). A low compensation signal value (e.g., a voltage of zero) will be provided when both PWM signals pwmp and pwmm are high (e.g., high common mode). An intermediate compensation signal value (e.g., a voltage of pvddhp/<NUM> due to circuit path <NUM> floating as a result of both transistors 252A-B being turned off) will be provided when PWM signals pwmp and pwmm are different (e.g., differential mode). Although particular transistors 252A-B and logic circuits 256A-B are provided in <FIG>, other circuits (e.g., one or more inverters, other logic circuits, and/or other components) may be used as appropriate.

Thus, it will be appreciated that the compensation signal comp provided by compensation circuit <NUM> will be actively adjusted with and correlate to the common mode or differential mode operation of PWM signals pwmp and pwmm. By applying the compensation signal to resistors 222A-B, the voltages at nodes 224A-B and 214A-B will be affected by the voltages provided by PWM signals pwmp and pwmm as well as compensation signal comp. In particular, the voltage of compensation signal comp will operate to offset disturbances at input nodes 214A-B resulting from the switching of PWM signals pwmp and pwmm between common mode and differential mode.

Although compensation circuit <NUM> is illustrated as directly receiving PWM signals pwmp and pwmm, other embodiments are contemplated. For example, other signals correlated with, synchronized with, and/or or related to PWM signals pwmp and pwmm may be used to generate compensation signal comp in various embodiments.

As shown, integration stage <NUM> further includes optional capacitors 226A-B which may be used to implement low pass filters to further reduce the disturbances caused by the switching of PWM signals pwmp and pwmm between common mode and differential mode. Because compensation circuit <NUM> already substantially reduces or eliminates the disturbances, capacitors 226A-B may be implemented with a relatively small size (e.g., <NUM> pf) in comparison with conventional low pass filter capacitors (e.g., <NUM> pf). An additional optional capacitor <NUM> may be removed in some embodiments.

As discussed, loop filter <NUM> may include one or more integration stages. Accordingly, <FIG> expands upon the embodiment of <FIG> and illustrates integration stages <NUM>, <NUM>, and <NUM> implemented in series with each other and provided in loop filter <NUM> in accordance with an embodiment of the disclosure.

As shown, <FIG> includes the integration stage <NUM> of <FIG> feeding integration stage <NUM> which feeds integration stage <NUM>. Output nodes 296A-B of integration stage 290A-B may provide a resulting integrated differential analog signal to an appropriate downstream component such as converter <NUM>.

Integration stages <NUM>, <NUM>, and <NUM> receive PWM signals pwmp and pwmm (e.g., from power stage <NUM> of <FIG>), and further receive compensation signal comp from compensation circuit <NUM>. Accordingly, disturbances at input nodes 214A-B, 284A-B, and 294A-B of integrators <NUM>, <NUM>, and <NUM>, respectively, may be compensated for in the manner discussed with regard to <FIG>.

<FIG> illustrates voltage plots of various signals of loop filter <NUM> without common mode compensation applied in accordance with an embodiment of the disclosure. Plot <NUM> illustrates PWM signal pwmp. Plot <NUM> illustrates the voltage at input node 214A of integration stage <NUM> without compensation signal comp applied. Plot <NUM> illustrates the voltage at input node 284A of integration stage <NUM> without compensation signal comp applied.

As shown, when compensation signal comp is not applied, the voltages at input nodes 214A and 284B are continuously changing which is the voltage disturbance manifested by the switching of PWM signals pwmp and pwmm between common mode and differential mode. As a result of this continuous changing of the voltage at input nodes 214A and 284B, integrators <NUM> and <NUM> are forced to continuously operate, thus increasing their power usage and also introducing associated noise and distortion into the output signal of amplifier <NUM>.

<FIG> illustrates voltage plots of various signals of loop filter <NUM> with common mode compensation applied to integration stage <NUM> but not applied to integration stage <NUM> in accordance with an embodiment of the disclosure. Plot <NUM> illustrates PWM signal pwmp. Plot <NUM> illustrates the voltage at input node 214A of integration stage <NUM> with compensation signal comp applied. Plot <NUM> illustrates the voltage at input node 284A of integration stage <NUM> without compensation signal comp applied.

By comparing plots <NUM> and <NUM> of <FIG> and <FIG>, it will be appreciated that when compensation signal comp is applied, the voltage at input node 214A settles quickly at a steady state (e.g., exhibits reduced disturbance) after PWM signals pwmp and pwmm switch between common mode and differential mode. This is further apparent by comparing plots <NUM> and <NUM> for integration stages <NUM> and <NUM> with and without compensation signal comp applied, respectively. As shown, plot <NUM> exhibits continuous voltage changes while plot <NUM> reaches and holds various steady states quickly. Thus, in this case, integrator <NUM> will not be forced to continuously operate, thereby reducing its power usage and also reducing noise and distortion in the output signal of amplifier <NUM>. Meanwhile, integrator <NUM> will continue to exhibit the problems discussed with regard to integrator <NUM> in <FIG>.

<FIG> illustrates another example of voltage plots of various signals of loop filter <NUM> without common mode compensation applied in accordance with an embodiment of the disclosure. Plot <NUM> illustrates PWM signals pwmp and pwmm. Plot <NUM> illustrates the voltage at input node 214A of integration stage <NUM> without compensation signal comp applied. Plot <NUM> illustrates the voltage at input node 284A of integration stage <NUM> without compensation signal comp applied.

As similarly discussed with regard to <FIG>, when compensation signal comp is not applied, the voltages at input nodes 214A and 284B are continuously changing and exhibiting voltage disturbances caused by the switching of PWM signals pwmp and pwmm between common mode and differential mode. As a result, integrators <NUM> and <NUM> are forced to continuously operate, thus causing the problems discussed with regard to <FIG>.

<FIG> illustrates voltage plots of various signals of loop filter <NUM> with common mode compensation applied to both of integration stages <NUM> and <NUM> in accordance with an embodiment of the disclosure. Plot <NUM> illustrates PWM signals pwmp and pwmm. Plot <NUM> illustrates compensation signal comp. Plot <NUM> illustrates the voltage at input node 214A of integration stage <NUM> with compensation signal comp applied. Plot <NUM> illustrates the voltage at input node 284A of integration stage <NUM> also with compensation signal comp applied.

By referencing plots <NUM> and <NUM> together, it will be appreciated that compensation signal comp is synchronous with PWM signals pwmp and pwmm. In particular, plot <NUM> exhibits a low voltage (e.g. zero voltage) when PWM signals pwmp and pwmm are both high (e.g., a first common mode configuration), a high voltage (e.g., <NUM> volts) when PWM signals pwmp and pwmm are both low (e.g., a second common mode configuration), and an intermediate voltage (e.g., <NUM> volts) when PWM signals pwmp and pwmm differ from each other (e.g., differential mode configuration). It will be appreciated that this operation is similar to the operation of compensation circuit <NUM> and Table <NUM> as discussed. Other values of the high, low, and intermediate voltages may be used as appropriate for various embodiments.

By comparing plots <NUM> and <NUM>, and likewise comparing plots <NUM> and <NUM>, it will be appreciated that the voltages at input nodes 214A-B settle more quickly (e.g., exhibit reduced disturbance) after PWM signals pwmp and pwmm switch between common mode and differential mode when compensation signal comp is applied (e.g., in plots <NUM> and <NUM>) than when it is not applied (e.g., in plots <NUM> and <NUM>). Thus, when compensation signal comp is applied, integrators <NUM> and <NUM> may consume less power and accordingly reduce noise and distortion in the output signal of amplifier <NUM>.

Although <FIG> have been discussed in relation to integrators <NUM> and <NUM>, similar results may be obtained by applying compensation signal comp to integrator <NUM> and additional integrators as desired.

<FIG> illustrates a process performed by amplifier <NUM> in accordance with an embodiment of the disclosure. Although various sequential blocks are illustrated, it will be appreciated that one or more of the blocks may be performed simultaneously and/or in a different order as appropriate.

In block <NUM>, signal source <NUM> provides a differential current signal to input nodes 214A-B. In block <NUM>, power stage <NUM> provides PWM signals pwmp and pwmm to resistors 220A-B of loop filter <NUM> through feedback paths 150A-B. In block <NUM>, compensation circuit <NUM> generates compensation signal comp which is provided to resistors 222A-B of loop filter <NUM> through circuit path <NUM>.

In block <NUM>, input voltages are generated at input nodes 214A-B in response to the current signal received from signal source <NUM> flowing through one or more of resistors 218A, 220A, 218B, and 220B. As discussed, the application of compensation signal comp to resistors 222A-B (e.g., which affects the voltages at nodes 224A-B connected between resistors 218A/220A and 218B/220B) reduces the voltage disturbance at input nodes 214A-B that would otherwise be present as PWM signals pwmp and pwmm switch between common mode and differential mode.

In block <NUM>, integrator <NUM> integrates the voltages at input nodes 214A-B to generate an integrated differential analog signal at output nodes 216A-B. In block <NUM>, the preceding blocks <NUM> to <NUM> are repeated for integration stages <NUM> and <NUM> with integration stage <NUM> feeding integration stage <NUM> which feeds integration stage <NUM>. As discussed, the operation of block <NUM> may be performed simultaneously with one or more of the other blocks discussed herein in some embodiments.

In block <NUM>, converter <NUM> converts the integrated differential analog signal received from output nodes 296A-B of integration stage 290A-B to differential PWM signals. In block <NUM>, power stage <NUM> amplifies the differential PWM signals to provide PWM signals pwmp and pwmm. In block <NUM>, PWM signals pwmp and pwmm are provided to one or more additional components <NUM> for use by system <NUM> as discussed.

In view of the above disclosure, it will be appreciated that by incorporating active compensation circuit <NUM>, class D amplifier <NUM> may be implemented in a manner that reduces voltage disturbances while also reducing or eliminating the use of capacitors for low pass filtering of such disturbances. In some embodiments, the use of compensation circuit <NUM> improves the total harmonic distortion of amplifier <NUM> from -90dB to -105dB. Such improved performance permits amplifier <NUM> to be used with HiFi quality signal amplification in audio applications. In addition, the reduction or elimination of such capacitors also permits a current based signal source (e.g., a CSDAC or otherwise) to be interfaced directly to integrator <NUM>, thus permitting the current based signal source to be merged with loop filter <NUM>.

Claim 1:
An amplifier (<NUM>) comprising:
a power stage (<NUM>) configured to generate first and second PWM signals (pwmp, pwwmm);
an integration stage (<NUM>) comprising input nodes (214A, 214B) configured to receive an input differential analog signal, wherein the integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal; and
an active compensation circuit (<NUM>) configured to provide a compensation signal (comp) to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode; characterized in that the compensation signal comprises:
a low voltage when the PWM signals are in a first common mode configuration when the PWM signals are both high;
a high voltage when the PWM signals are in a second common mode configuration when the PWM signals are both low; and
a floating intermediate voltage when the PWM signals are in a differential mode configuration such that the voltage at the input nodes settles quickly at a steady state.