Patent Description:
Research is being conducted for implementing neuromorphic circuits mimicking the human brain, which involves designing neural circuits and synapse circuits respectively corresponding to neurons and synapses of the human nerve system. Realization of a semiconductor chip including a neuromorphic circuit ("neuromorphic chip") employs, along with synaptic cores including neuron groups, routers in the semiconductor device for multiple input and output connections between synaptic cores. In this regard, a circuit that facilitates multiple input and output connections and data transmission and reception is desirable to mimic the human nerve system having sophisticated connections. <CIT> discloses a three-dimensional integration of synapse circuitry is formed. One or more neuron layers each comprises a plurality of computing elements, and one or more synapse layers each comprising an array of memory elements are formed on top of the one or more neuron layers. A plurality of staggered through-silicon vias (TSVs) connect the one or more neuron layers to the one or more synapse layers and operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers.

The inventive concept provides a neuromorphic circuit having a three-dimensional stack structure and capable of emulating a high-performance nervous system by facilitating multiple input and output connections.

The invention provides a semiconductor device in accordance with claim <NUM>.

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which like reference characters denote like elements or functions, wherein:.

Embodiments of the inventive concept will now be described below with reference to the accompanying drawings.

<FIG> is a block diagram illustrating a data processing system <NUM> according to an embodiment of the inventive concept. Data processing system <NUM> may include a processing unit <NUM> and a semiconductor device <NUM>. The processing unit <NUM> may be any of various types of execution processing units, such as a central processing unit (CPU), a hardware accelerator such as a field-programmable gate array (FPGA), a massively parallel processor array (MPPA), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a neural processing unit (NPU), a tensor processing unit (TPU) or a multi-processor system-on-chip (MPSoC).

The data processing system <NUM> may be a system processing various types of data, and may be a system performing artificial intelligence computation such as neuromorphic computation or neural network computation according to an embodiment. For example, at least a portion of neuromorphic computation may be performed by circuitry on the semiconductor device <NUM>, and an intermediate result or a final result of neuromorphic computation may be recorded to a memory in the semiconductor device <NUM> or read from the semiconductor device <NUM>. In addition, the semiconductor device <NUM> may include a memory array storing information during a process of neuromorphic computation or neural network computation. The processing unit <NUM> may include a memory controller (not shown) for controlling a read/write operation on such a memory array.

For example, the data processing system <NUM> may be implemented as a personal computer (PC), a data server, a cloud system, an artificial intelligence server, a network-attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. In addition, when the data processing system <NUM> is a portable electronic device, the data processing system <NUM> may be a laptop computer, a mobile device, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), a MP3 player, a handheld game console, an e-book, a wearable device or the like.

According to an embodiment, the data processing system <NUM> performs neuromorphic computation, and the semiconductor device <NUM> may include neural circuits and synapse circuits respectively corresponding to neurons and synapses present in the human nervous system, as hardware components. Here, since the semiconductor device <NUM> performs neuromorphic computation, the semiconductor device <NUM> may be referred to as a neuromorphic device or a neuromorphic chip or integrated circuit (IC). A neuromorphic chip may include various circuit components mathematically modeling real neurons, and may include, for example, a memory array used to store synapse information or perform weight multiplication, or an operator performing an accumulation computation of weight-reflected multiple inputs or an activation function operation. A neuromorphic chip may be used in various fields such as data classification, pattern recognition or the like.

According to an embodiment of the inventive concept, the semiconductor device <NUM> may include a plurality of three-dimensionally stacked semiconductor layers to implement the neuromorphic computation function as described above. For example, the semiconductor device <NUM> may include first through Nth semiconductor layers Layer <NUM> through Layer N (hereafter, just "Layer <NUM> through Layer N", for brevity), where Layer <NUM> through Layer N include: synaptic cores performing neuromorphic computation; at least one router arranged to correspond to each synaptic core to control transfer of information such as a computation input or a computation result (or to determine an information transfer path); and interconnects arranged between routers to form a physical transfer path. Herein, a physical transfer path may be an electrical or optical transfer path configured for transferring information or control signals between circuits that are connected to the physical transfer path at different points.

The semiconductor device <NUM> may be implemented as a semiconductor chip, IC, or a semiconductor package in which layers Layer <NUM> through Layer N are stacked, and information may be exchanged between Layer <NUM> through Layer N via conductive lines such as through electrodes. For example, although not illustrated in <FIG>, a through silicon via (TSV) is included in the semiconductor device <NUM> as a through electrode.

For example, synaptic cores may be arranged in some of layers Layer <NUM> through Layer N, and these semiconductor layers may be referred to as synaptic core layers. In addition, in other semiconductor layers among Layer <NUM> through Layer N, interconnects may be arranged, and these semiconductor layers may be referred to as interconnect layers. Further, routers may be arranged in the synaptic core layers and/or the interconnect layers.

Each synaptic core layer may include a plurality of synaptic cores, where a plurality of neural circuits and synaptic circuits may be implemented in each synaptic core. According to an embodiment, each synaptic core includes a memory circuit <NUM> storing synapse information for calculating weights between neural circuits and a computation circuit <NUM> including various operators for neuromorphic computation. For example, the memory circuit <NUM> may include a reconfigurable memory array, and the computation circuit <NUM> may include logic to perform a computation function such as data multiplication, summation, and activation function operations or the like that are associated with neuromorphic computation.

Each synaptic core may further include local routers used to control information transfer between neural circuits within that synaptic core, and local interconnects used to form a physical transfer path between local routers. Semiconductor device <NUM> may further include routers for information transfer between the synaptic cores, which may be referred to as global routers, and information transfer paths between the global routers, which may be referred to as global interconnects.

In an embodiment, the synaptic core layers and the interconnect layers of Layers <NUM> through N may be alternately stacked. For example, first, third,. , and (N-<NUM>)th semiconductor layers Layer <NUM>, Layer <NUM>,. , Layer (N-<NUM>) may be synaptic core layers, and second, fourth,. , Nth semiconductor layers Layer <NUM>, Layer <NUM>,. Layer N may be interconnect layers.

According to an operation example, Layer <NUM> may be a synaptic core layer, and input information from the processing unit <NUM> or another semiconductor layer may be provided to a first synaptic core in Layer <NUM>. The first synaptic core may perform a neuromorphic computation by using input information and a weight, and may provide a computation result to Layer <NUM>, which is an interconnect layer. The computation result may be transferred via an interconnect of Layer <NUM> to a second synaptic core of Layer <NUM> via transfer path control, or the computation result may be provided to a third synaptic core of Layer <NUM>.

With semiconductor device <NUM>, information may be transferred in various manners between multiple semiconductor layers according to the above-described structure. For example, a synaptic core in any one synaptic core layer may receive input information from any other synaptic core layer, and may provide a computation result to any other synaptic core layer.

According to the above-described embodiment of the inventive concept, and as will be described further below, since synaptic cores, routers, and interconnects are implemented as a three-dimensional stack in semiconductor layers, this facilitates the implementation of a high-capacity brain-like structure and the handling of multiple inputs and outputs therein. In addition, due to a higher capacity of each chip unit, the number of semiconductor chips needed for actual neuromorphic computation may be reduced, and accordingly, chip-to-chip connections may be reduced, thereby reducing a system size and enabling low-power consumption.

Meanwhile, information transmission between Layer <NUM> through Layer N as described above may be performed by using elements such as a TSV. For example, a TSV formed in at least one of adjacent semiconductor layers may allow for information exchange between the adjacent layers. In an embodiment (illustrated later), a TSC may pass through all of the layers Layer <NUM> through Layer N.

While the semiconductor device <NUM> has been described as one that performs a neuromorphic computation, the inventive concept is not limited thereto. For example, processing circuitry performing a neural network computation according to a predefined neural network model based on control of the processing unit <NUM> may be included in some semiconductor layers of the semiconductor device <NUM>. Some examples of the neural network model may include various types of models such as Convolutional Neural Networks (CNN), Recurrent Neural Networks (RNN), Deep Belief Networks, Restricted Boltzman Machines. For instance, a portion of neural network computation may be performed by using the processing unit <NUM>, and another portion thereof may be performed by using the semiconductor device <NUM>. In this case, when the semiconductor device <NUM> performs neural network computation, it may do so based on input data received from the processing unit <NUM> and provide a computation result to the processing unit <NUM>, or may generate an information signal based on the computation result and provide the information signal to the processing unit <NUM>.

<FIG> is a block diagram illustrating an example of elements and connections therebetween for implementing a neuromorphic chip function. While the elements are illustrated two-dimensionally in <FIG> for ease of explanation, according to embodiments of the inventive concept, the elements illustrated in <FIG> may be arranged three-dimensionally.

A neuromorphic chip may include a plurality of synaptic cores, a plurality of routers corresponding to the synaptic cores, and interconnects via which information is transferred between the routers. For example, at least one router may be provided in association with each synaptic core. As described above, routers and interconnects between the synaptic cores may be respectively referred to as global routers and global interconnects. In the example arrangement of <FIG>, one global router is connected to each respective synaptic core, and the global routers electrically or optically connect to one another via global interconnects. The shown elements of <FIG> may be disposed in one or more of Layer <NUM> to Layer N of <FIG>. It is noted that the global routers may be reconfigurable routers functioning as a gate for signal connection between the synaptic cores.

A synaptic core represents a plurality of neuron assemblies, and includes a memory array storing synapse information. In addition, while not illustrated in <FIG>, a synaptic core includes local routers and local interconnects for information transfer between a plurality of neural circuits.

Each synaptic core may receive input information through a global router, and transmit a computation result obtained by using the input information through the global router. For example, each synaptic core may provide a computation result and also output, through the global router, path information leading to another synaptic core which is to receive the computation result. The computation result may be provided to at least one other synaptic core through interconnects between global routers. In a neuromorphic chip having a three-dimensional structure according to embodiments of the inventive concept, each synaptic core may further output, through the global router, information indicating a semiconductor layer where the other synaptic core(s) is located, to facilitate information transmission between a plurality of semiconductor layers.

Meanwhile, routing information may be stored in the synaptic core to control an information transfer path through the associated global router, and a memory array used to store routing information may be implemented as part of a memory array used to implement a neural circuit in the synaptic core. Alternatively, the memory array for storing routing information is implemented in a separate memory area.

The global interconnects and the local interconnects described above may be formed of various types of materials having electric conductivity or of an optical material.

<FIG> is a structural diagram illustrating a semiconductor device <NUM> of <FIG> according to the invention. As shown in <FIG>, the semiconductor device <NUM> includes a plurality of semiconductor layers that communicate with each other via a TSV. (Each of the cylinders shown in <FIG> and other figures discussed hereafter is a TSV. ) Note that while six semiconductor layers are illustrated in <FIG> (aside from the silicon layers <NUM>), any suitable number of semiconductor layers may be used. Hereafter, a semiconductor layer in which at least one synaptic core is disposed may be referred to as a synaptic core layer, and a semiconductor layer in which a router and/or an interconnect is disposed may be referred to as a router/interconnect (R/I) layer. Here, it is assumed that one synaptic core layer and one router/interconnect layer form one layer set. In the below discussion, "interconnects" are understood to be global interconnects, and "routers" are understood to be global routers, unless indicated otherwise.

The semiconductor device <NUM> includes first through third layer sets <NUM> through <NUM>. The first layer set <NUM> may include a first synaptic core layer <NUM> and a first router/interconnect layer <NUM>. The first router/interconnect layer <NUM> is stacked on the first synaptic core layer <NUM> and may communicate with the first synaptic core layer <NUM> via a TSV. In addition, the second layer set <NUM> may be stacked on the first layer set <NUM> via a TSV and include a second synaptic core layer <NUM> and a second router/interconnect layer <NUM>. In addition, the second router/interconnect layer <NUM> is stacked on the second synaptic core layer <NUM> and communicates with the second synaptic core layer <NUM> via a TSV. The third layer set <NUM> may also include a third synaptic core layer <NUM> and a third router/interconnect layer <NUM>.

As mentioned, each of the cylinders shown in <FIG> and other figures discussed hereafter is a TSV, thus it is seen that a set of TSVs between adjacent semiconductor layers may be used to communicatively connect circuits in different layers to one another. Although shown to exist with a layer thickness between adjacent semiconductor layers such as <NUM>, <NUM>, the TSVs may exist entirely within the semiconductor layers such as <NUM>, <NUM>. In this case, when adjacent layers are said to be "stacked on" each other, surfaces of the adjacent layers may be in direct contact without any additional semiconductor layer therebetween. Alternatively, each set of TSVs may be formed at least partially within a separate silicon layer <NUM>, and each TSV may or may not extend within the adjacent layers such as <NUM>, <NUM> but may instead make electrical contact with conductive traces on the surfaces of the adjacent layers. In either case, when one layer is said herein to be stacked on another layer, the surfaces of the two layers may be in direct contact (as in the case where the TSVs are disposed entirely within the respective layers), or they may be spaced closely together but not in direct contact (as in the case where the TSVs are provided at least partially within a separate layer <NUM>).

At least one router may be arranged to correspond to each synaptic core. Herein, a router said to be arranged to correspond to a synaptic core, or to just correspond to a synaptic core, is a router associated with, and directly connected to, that synaptic core for signal communication. For example, one synaptic core and one router corresponding to this synaptic core may be arranged in semiconductor layers at different locations. Alternatively, two or more routers may be associated with any one synaptic core. For instance, with regard to one synaptic core with all its elements entirely within any one semiconductor layer, routers corresponding to this synaptic core may be arranged in different semiconductor layers located above and below the one semiconductor layer.

In the semiconductor device <NUM> illustrated in <FIG>, with regard to a synaptic core, a router, and an interconnect included to implement a neuromorphic chip, an R/I layer that includes both the router and the interconnect, and a synaptic core layer that includes the synaptic core having a memory array, may be separated but connected to each other by using a TSV connection technique.

According to an operation example, a plurality of synaptic cores may be arranged in the first synaptic core layer <NUM>, and information from any one of the synaptic cores may be provided to the first R/I layer <NUM> via a TSV. The information provided to the first R/I layer <NUM> may be provided to the second synaptic core layer <NUM> of the second layer set <NUM> or the third synaptic core layer <NUM> of the third layer set <NUM> via a TSV formed on the first R/I layer <NUM>. In another connection path, the information provided to the first R/I layer <NUM> may be provided to another synaptic core in the first synaptic core layer <NUM> via a TSV formed under the first R/I layer <NUM>.

Similarly, information from a synaptic core in the second synaptic core layer <NUM> may be transmitted to another synaptic core via a TSV on or under the second synaptic core layer <NUM>. For example, information from a synaptic core in the second synaptic core layer <NUM> may be provided to a synaptic core in the third synaptic core layer <NUM> through a TSV on the second synaptic core layer <NUM> and the second R/I layer <NUM>. Alternatively, information from a synaptic core in the second synaptic core layer <NUM> may be provided to a synaptic core in the second synaptic core layer <NUM> through a TSV under the second synaptic core layer <NUM> and the first R/I layer <NUM>. Alternatively, information from a synaptic core in the second synaptic core layer <NUM> may be provided to another synaptic core in the second synaptic core layer <NUM> through a TSV on or under the second synaptic core layer <NUM>.

<FIG> is a flowchart of an operating method of a semiconductor device according to an embodiment of the inventive concept. As the semiconductor device is assumed as performing neuromorphic computation, the operating method of <FIG> may correspond to a neuromorphic computation method.

Referring to <FIG>, the semiconductor device may include a plurality of semiconductor layers that are stacked three-dimensionally; for example, first through third semiconductor layers may be sequentially stacked. In addition, the first through third semiconductor layers may communicate with each other via a through electrode such as a TSV, and a synaptic core as described above may be arranged in each of the first through third semiconductor layers, and an interconnect (e.g., a global interconnect) may be arranged in the second semiconductor layer.

First, a first synaptic core in the first semiconductor layer may perform neuromorphic computation based on input information, and a computation result may be generated from the first synaptic core (S <NUM><NUM>). The computation result may be transferred to a first router associated with the first synaptic core (S12). According to an embodiment, the first router may be arranged in the second semiconductor layer in addition to an interconnect. The first router may receive routing information associated with information transfer, along with the computation result and determine the routing information (S <NUM>), and may determine a location of a semiconductor layer to which the computation result is to be provided. For example, it may be determined (S14) whether the computation result is to be provided to another semiconductor layer.

The computation result may be provided to a synaptic core located in the first semiconductor layer or another semiconductor layer based on a result of the determination. For example, when the computation result is provided to the third semiconductor layer located on the first semiconductor layer, the computation result may be provided to a second router via an interconnect of the second semiconductor layer (S <NUM>), and the computation result may be provided to a second synaptic core of the third semiconductor layer corresponding to the second router (S16). On the other hand, when the computation result is provided to another synaptic core of the first semiconductor layer, the computation result may be provided to a third router via the interconnect of the second semiconductor layer (S <NUM>), and the computation result may be provided to a third synaptic core of the first semiconductor layer corresponding to the third router (S <NUM>).

<FIG> illustrates a structural diagram of a layer set of a semiconductor device. The layer set includes a synaptic core layer having at least one synaptic core and a plurality of routers, an interconnect layer, and a set of TSVs between the synaptic core layer and the interconnect layer. In this case not in accordance with the invention, the interconnect layer may exclude routers. By way of example, interconnects in this interconnect layer may be laid out in two vertical levels, where one vertical level includes a plurality of first interconnects running parallel to each other in a first direction, and the other vertical level includes a plurality of second interconnects running parallel to each other in a second direction orthogonal to the first direction. Alternatively, parallel running interconnects may be provided on just a single level within the interconnect layer. Other layouts are also contemplated, such as a plurality of concentric circular, square, or other shaped interconnects on the same or different levels within the interconnect layer.

<FIG> illustrates a semiconductor device <NUM> not in accordance with the invention. Semiconductor device <NUM> includes a plurality of stacked layer sets each having the configuration of the layer set of <FIG>. The layer sets may include, e.g., first through third layer sets <NUM> through <NUM>. First layer set <NUM> may include a first synaptic core layer <NUM> in which at least one synaptic core 311_1 and at least one router 311_2 are arranged and a first interconnect layer <NUM> in which an interconnect is arranged, and the first synaptic core layer <NUM> and the first interconnect layer <NUM> may communicate with each other via a TSV. The second and third layer sets <NUM> and <NUM> may also be configured in the same manner as the first layer set <NUM> and stacked on the first layer set <NUM>, and as a TSV is formed between the first through third layer sets <NUM> through <NUM>, information may be transmitted between the first through third layer sets <NUM> through <NUM> via the TSV.

For example, regarding the first layer set <NUM>, information from synaptic cores in the first synaptic core layer <NUM> (for example, a computation result) may be provided to routers implemented in the same semiconductor layer, and then provided to the first interconnect layer <NUM> via a router and a TSV. For example, information from a first synaptic core in the first synaptic core layer <NUM> may be transferred via an interconnect formed in the first interconnect layer <NUM>, and provided to a second synaptic core in the second synaptic core layer <NUM> through a router formed in the second synaptic core layer <NUM>. In another connection path, information from the first synaptic core in the first synaptic core layer <NUM> may be transferred via an interconnect formed in the first interconnect layer <NUM>, and then provided to a third synaptic core in the first synaptic core layer <NUM> via a router formed in the first synaptic core layer <NUM>.

<FIG> illustrates an example of information transfer between synaptic cores within an example configuration of semiconductor device <NUM> of <FIG>. The principles illustrated and described may also apply to other semiconductor device configurations.

As shown in <FIG>, semiconductor device <NUM> includes a plurality of layer sets; for example, first through third layer sets Layer Set <NUM> through Layer Set <NUM> are illustrated. In addition, each layer set may include one synaptic core layer and one router/interconnect layer. Information from a starting synaptic core may be provided to an end synaptic core via at least one router and at least one a synaptic core. In the example depicted, information from a first synaptic core SC1 in the first layer set Layer Set <NUM> is provided to a third synaptic core SC3 in the third layer set Layer Set <NUM>.

Along with information such as a computation result, the first synaptic core SC1 may further generate path information (or connection information) to a synaptic core (for example, a second synaptic core SC2) to which the computation result is to be transferred. For example, the path information may include information indicating a router or a synaptic core to which a computation result is to be provided. According to an embodiment, the path information may include layer information L, router information R, and interconnect information I.

For example, information from the first synaptic core SC1 may be provided to a corresponding router R1 located in the first layer set Layer Set <NUM>, and the router R1 may decode the path information from the first synaptic core SC1. In addition, a transfer path of a computation result may be controlled based on a decoding result, and for example, a computation result may be provided to a second router R2 corresponding to a position Rj in the second layer set Layer Set <NUM> based on layer information L and interconnect information I included in the path information. In addition, the computation result may be provided to the second synaptic core SC2 corresponding to the second router R2, and the second synaptic core SC2 may generate a computation result based on received information, and may also generate path information (layer information L, router information R, and interconnect information I) used to control a path through which the computation result is to be transferred.

According to the above-described process, the computation result may be transferred via routers R4 and R5 in the third layer set Layer Set <NUM>, and the computation result may be provided to the third synaptic core SC3 corresponding to the fifth router R5.

Note that the operations explained for <FIG> may also apply to the semiconductor device <NUM> of <FIG>, except that the routers are disposed within the synaptic core layers.

<FIG> are block diagrams illustrating respective implementation examples of semiconductor layers according to locations of routers. In <FIG>, a router is arranged in the same layer as an interconnect, and in <FIG>, a router is arranged in the same layer as a synaptic core.

Referring to <FIG>, a router may be arranged in the same layer as an interconnect and include a complementary metal oxide semiconductor (CMOS) circuit used to decide a direction toward a synaptic core to which information is to be transferred. In addition, an interconnect may include a physical wiring area that forms a transfer path of information. Along with this, the synaptic core may include a memory area for storing synapse information or the like and a CMOS circuit area used to perform computation.

In the embodiment of <FIG>, as a router is arranged in the same layer as a synaptic core, only a physical wiring area that forms a transfer path of information may be formed in an interconnect layer. Meanwhile, in a router/synaptic core layer where a router and a synaptic core are arranged, the above-described memory area may be formed in addition to a CMOS circuit area that functions as a router and is used for neuromorphic computation.

According to the embodiment illustrated in <FIG>, a relatively large number of synaptic cores may be arranged in a synaptic core layer, and as a transfer path of information is formed by the router/interconnect layer, information may be transferred easily and efficiently. In addition, according to the embodiment illustrated in <FIG>, as only a physical wiring area may be formed in the interconnect layer, the interconnect layer may be easily implemented and the manufacturing costs may be reduced.

<FIG> and <FIG> are block diagrams illustrating respective implementation examples of TSVs included in a semiconductor device according to embodiments of the inventive concept.

Referring to <FIG> and <FIG>, the semiconductor device includes a plurality of semiconductor layers and TSVs for communication between the semiconductor layers, where the plurality of semiconductor layers may include synaptic core layers and router/interconnect layers that are alternately stacked vertically. In <FIG>, an example in which a plurality of semiconductor layers are arranged and then each TSV is formed to pass through all of the semiconductor layers is illustrated. A TSV in this embodiment may thus be referred to as a "multi-layer TSV". In other examples, multi-layer TSVs may be provided to extend through only some of the semiconductor layers. Still other examples may utilize a combination of multi-layer TSVs and "adjacent-layer TSVs" (TSVs that only connect circuit elements of adjacent semiconductor layers, as in the examples seen earlier and in <FIG>). In the embodiment of <FIG>, as illustrated in the above-described embodiments of <FIG>, etc., each TSV is an "adjacent layer TSV" formed between just two adjacent semiconductor layers. In addition, while routers used to control an information transfer path are arranged in an interconnect layer in the embodiments of <FIG> and <FIG>, the routers may also or alternatively be arranged in a synaptic core layer as in <FIG>.

According to the embodiment of <FIG>, information output from a synaptic core in the first semiconductor layer <NUM> may be directly transferred to an R/I layer that is not adjacent to the first semiconductor layer <NUM>, without passing through an interconnect in an R/I layer adjacent to the first semiconductor layer <NUM>. For example, information output from a synaptic core in the first semiconductor layer <NUM> may be provided directly to a fourth semiconductor layer <NUM>, and the information may be provided to a third semiconductor layer <NUM> or a fifth semiconductor layer <NUM> via an interconnect of the fourth semiconductor layer <NUM>.

<FIG> is a block diagram illustrating an example in which a semiconductor device <NUM> according to embodiments of the inventive concept performs neuromorphic computation. As in the above-described embodiments, the semiconductor device <NUM> includes a plurality of semiconductor layers, where the plurality of semiconductor layers may include synaptic core layers and router/interconnect layers that are alternately stacked.

Neuromorphic computation or neural network computation may be performed in a plurality of nodes as illustrated in <FIG>. A result of a computation performed in nodes of any one layer may be provided to other nodes of a next layer. For example, a plurality of nodes may constitute an input layer, at least one hidden layer, and an output layer.

According to an embodiment, nodes performing neuromorphic computation may be implemented as a neural circuit and a synapse circuit included in a synaptic core, and information transfer between nodes may be performed by using a router/interconnect layer. For instance, an operation of providing a result of a computation performed by using input information and a weight from a node to another node, may include an operation of providing information from any one synaptic core of the semiconductor device <NUM> to a synaptic core of another semiconductor layer via a router/interconnect layer.

According to an embodiment, some of the semiconductor layers of the semiconductor device <NUM> may constitute an input layer <NUM> described above; some other semiconductor layers may constitute at least one hidden layer <NUM>; and the remaining semiconductor layers may constitute an output layer <NUM>. For example, one synaptic core layer and one router/interconnect layer in a lower portion may be included in the input layer <NUM>, and a plurality of synaptic core layers and a plurality of router/interconnect layers located on the input layer <NUM> may be included in the hidden layer <NUM>, and one synaptic core layer and one router/interconnect layer in an upper portion are included in the output layer <NUM>. In an alternative example, semiconductor layers at predefined locations from among a plurality of semiconductor layers included in the semiconductor device <NUM> may also constitute the input layer <NUM>, the hidden layer <NUM>, and the output layer <NUM> described above.

A computation result from the input layer <NUM> may be provided to a synaptic core layer in the hidden layer <NUM> via a TSV. In addition, a computation result from any one synaptic core layer of the hidden layer <NUM> may be provided to another synaptic core layer of the hidden layer <NUM> or to a synaptic core layer in the output layer <NUM>. In addition, a final computation result from the output layer <NUM> may be stored in the semiconductor device <NUM> or provided to the outside.

According to the embodiment illustrated in <FIG>, under an assumption that neuromorphic computation includes a plurality of hierarchical computations, operation in nodes of the same layer (input, hidden or output layer) may be performed in a semiconductor layer or layers located at the same vertical region of the semiconductor device <NUM>. Further, a result of the operation may be easily transferred to a semiconductor layer corresponding to nodes of another layer via a TSV. Because interconnects are disposed in a semiconductor layer at a different location from that of a semiconductor layer in which synaptic cores are formed, the interconnects may be implemented more easily. Moreover, information transfer efficiency may be increased.

<FIG> schematically illustrates an example of a synaptic core, <NUM>, that may be used for any of the synaptic cores in the embodiments herein. Synaptic core <NUM> may include a plurality of neural circuits (NC), where some neural circuits may receive input information from outside synaptic core <NUM>, and may provide a result of predefined neuromorphic computation to at least one other neural circuit in the same synaptic core. In addition, some other neural circuits of the synaptic core <NUM> may receive a computation result generated in the synaptic core as input information, and the computation result may be provided to other neural circuits in the synaptic core. Local routers (not shown) may be included within or outside any neural circuit to route the information to another, target neural circuit via local interconnects (the shown arrowed paths). Still other neural circuits in the synaptic core <NUM> may provide a neuromorphic computation result to an external synaptic core(s).

<FIG> and <FIG> are configurational / block diagrams illustrating respective synaptic cores with circuit components thereof disposed in different semiconductor layers of a semiconductor device. According to an embodiment of the inventive concept, circuit components of a single synaptic core may be spread across a plurality of semiconductor layers as illustrated in <FIG>. In the embodiment of <FIG>, a first synaptic core 600A, which is an embodiment of synaptic core <NUM>, includes neural circuits NC, also called "neurons", distributed in a plurality of semiconductor layers; and router/interconnect (R/I) layers arranged in semiconductor layers different from those containing the neural circuits. For example, some neural circuits may be arranged in a first semiconductor layer 611A, other neural circuits may be arranged in a third semiconductor layer 613A, and a second semiconductor layer 612A, which is an R/I layer including a router/interconnect, may be disposed between the first and third semiconductor layers 611A, 613A. Here, the router and interconnect of the R/I layer is a local router and a local interconnect.

Meanwhile, referring to <FIG> not in accordance with the invention, in a semiconductor device 600B, neural circuits and routers may be arranged in some of the semiconductor layers thereof, and interconnects may be arranged in some other semiconductor layers. For example, some neural circuits and routers may be arranged in a first semiconductor layer 611B; other neural circuits and routers may be arranged in a third semiconductor layer 613B; and a second semiconductor layer 612B in which an interconnect is arranged may be located between the first semiconductor layer 611B and the third semiconductor layer 613B.

According to the embodiments illustrated in <FIG>, <FIG>, and <FIG>, a synaptic core having a three-dimensional stack structure formed by using at least two semiconductor layers may be implemented. That is, as a plurality of neural circuits included in one synaptic core and a local router and a local interconnect included for connection between the neural circuits are formed in a plurality of semiconductor layers according to the above-described embodiments, a synaptic core may be easily implemented and an information transfer efficiency may also be increased.

<FIG> and <FIG> are configurational / block diagrams illustrating respective embodiments of a semiconductor device according to the inventive concept. In these devices, each synaptic core is implemented in a three-dimensional stack form, and connections between a plurality of synaptic cores are also implemented in a three-dimensional stack form.

Referring to <FIG>, a semiconductor device 700A may include a plurality of semiconductor layers which may include a plurality of synaptic cores and global router/interconnect layers between the synaptic cores. In the illustrated example, the semiconductor layers include multiple layers forming a first synaptic core 710A, multiple layers forming a second synaptic core 720A, and a global router/interconnect layer 730A between the first and second synaptic cores 710A and 720A. In other embodiments, semiconductor device 700A may include more synaptic cores and global router/interconnect layers.

In any of the synaptic cores 710A, 720A, neural circuits may be respectively formed in different semiconductor layers. Neural circuits in the same or different layers may transmit / receive information to each other via a local router/interconnect layer formed in an additional semiconductor layer. In addition, the first synaptic core 710A and the second synaptic core 720A may transmit or receive information to each other via the global router/interconnect layer 730A.

Referring to <FIG>, a first semiconductor layer 711B in which some neural circuits and local routers of a first synaptic core 710B are arranged and a third semiconductor layer 713B in which some other neural circuits and local routers of the first synaptic core 710B are arranged may have a three-dimensional stack structure, and a second semiconductor layer 712B including a local interconnect may be arranged between the first semiconductor layer 711B and the third semiconductor layer 713B. In addition, the first through third semiconductor layers 711B through 713B may transmit / receive information to or from each other via a TSV. Further, the first synaptic core 710B and the second synaptic core 720B may transmit or receive information to or from each other via a TSV and a global interconnect layer 730B.

According to an embodiment, local routers and global routers described above may be formed in the same semiconductor layer as a synaptic core (or neural circuits), and local interconnects and global interconnects may be formed in another semiconductor layer different from that of the synaptic core.

Information from some neural circuits of the first synaptic core 710B may be provided to other neural circuits in the first synaptic core 710B through local routers and local interconnects, and information from some other neural circuits of the first synaptic core 710B may be provided to neural circuits of the second synaptic core 720B through global routers and global interconnects.

According to the embodiments illustrated in <FIG> and <FIG>, circuits in each of the above-described synaptic core units are formed with a three-dimensional stack structure, and circuits in a plurality of synaptic core units, when considered collectively, may also have a three-dimensional stack structure. Here, by arranging local interconnects and global connects at appropriate locations of a plurality of semiconductor layers, information transfer efficiency may be enhanced.

It is noted that while <FIG> illustrates that local routers and global routers are both formed in the same semiconductor layer as a synaptic core (or neural circuits), other configurations are available. For example, while a local router is formed in a same semiconductor layer as neural circuits, a global router may also be formed in the global interconnect layer 730B. Alternatively, while a global router is formed in a same semiconductor layer as neural circuits, a local router may also be formed in a same semiconductor layer as a local interconnect.

<FIG> are signal and block diagrams, respectively, illustrating an example of a semiconductor device according to another embodiment of the inventive concept.

As illustrated in <FIG>, as an example of neuromorphic computation made by a semiconductor device, synapse weights (ω0, ω1, ω2) are multiplied with information represented by values (x0, x1, x2) from a plurality of neurons, and a summation operation (Σ) is performed on the multiplication results (w0x0, w1x1,. Further, a characteristic function (b) and an activation function (f) may be performed on a result of the summation operation, thereby providing a computation result.

<FIG> illustrates a semiconductor device <NUM> including a plurality of semiconductor layers and interconnects therebetween. The semiconductor layers may include an input layer <NUM> through which information from an outside source is received, a weight layer <NUM> storing weight information used for neuromorphic computation, a multiplication layer <NUM> in which multiplication based on weights is performed, an accumulation layer <NUM> in which an accumulation computation on multiplication results is performed, an activation layer <NUM> performing an activation function, and an output layer <NUM> from which a computation result is output. The activation function may correspond to various types of operations, and include, for example, sigmoid, ReLU (Rectified Linear Unit), hyper-tangent, and threshold.

Each of the semiconductor layers included in the semiconductor device <NUM> may include circuits used to perform corresponding operation processing, and for example, a computation circuit for performing analog or digital operations may be included in the semiconductor layers. In addition, according to the embodiment illustrated in <FIG>,.

various functions performed in accordance with any one neural circuit may be distributed to at least two semiconductor layers for implementation. The input layer <NUM> may receive a plurality of inputs via a semiconductor layer (not shown) in which routers and interconnects according to the above-described embodiments are formed. A computation result may be output from the output layer <NUM> through a semiconductor layer (not shown) in which the routers and the interconnects according to the above-described embodiments are formed.

<FIG> is a circuit diagram illustrating an example of a neuromorphic circuit <NUM> according to an embodiment. The neuromorphic circuit <NUM> may be included in a synaptic core in any of the above-described embodiments.

Neuromorphic circuit <NUM> may include a plurality of neural circuits <NUM> and <NUM> and a plurality of synapse circuits <NUM> providing connection between the neural circuits. Neural circuits <NUM> and <NUM> may be pre-synaptic neural circuits (Pre-NC) <NUM> and post-synaptic neural circuits (Post-NC) <NUM>, respectively. Synapse circuits <NUM> may be arranged in an area where the pre-synaptic neural circuits <NUM> and the post-synaptic neural circuits <NUM> intersect each other. While the neuromorphic circuit <NUM> having a matrix structure including four pre-synaptic neural circuits <NUM> and four post-synaptic neural circuits <NUM> is illustrated in <FIG>, the neuromorphic circuit <NUM> may include any suitable number of neural circuits.

Meanwhile, the synapse circuits <NUM> may include various types of memories, and for example, weights may be stored in the synapse circuits <NUM> through memrister-based design. A multiplication computation may be performed at points of intersection of the pre-synaptic neural circuits <NUM> and the post-synaptic neural circuits <NUM>. Some examples of the types of memories used to implement the neuromorphic circuit <NUM> include DRAM and SRAM using a CMOS transistor technique, phase change RAM (PRAM), phase-change memory (PCM), resistive RAM (ReRAM), magnetic RAM (MRAM), a spin transfer torque magnetic RAM (STT-MRAM) using a resistive memory technique, or the like.

As an operation example, the pre-synaptic neural circuits <NUM> may output input data to the synapse circuits <NUM>, and the synapse circuits <NUM> may vary conductance of a memrister based on a predefined threshold voltage, and a connection intensity between the pre-synaptic neural circuits <NUM> and the post-synaptic neural circuits <NUM> may be varied based on a result of varying the conductance. For example, when conductance of a memrister increases, an intensity of connection between a pre-synaptic neural circuit and a post-synaptic neural circuit corresponding to the memrister may increase; when conductance of the memrister decreases, an intensity of connection between a pre-synaptic neural circuit and a post-synaptic neural circuit corresponding to the memrister may decrease. A weight may be applied to signals provided to the post-synaptic neural circuits <NUM> based on conductance of a memrister of the synapse circuits <NUM>. A result obtained by assigning a weight to each piece of input data (or by multiplying a weight by each piece of input data) may be provided to the post-synaptic neural circuits <NUM>. Although not illustrated in <FIG>, elements for implementing other functions associated with neural network computation (for example, activation function operation) may be further included in the neuromorphic circuit <NUM>.

<FIG> is a block diagram illustrating an example in which a semiconductor device according to embodiments of the inventive concept is embodied as a high bandwidth memory (HBM) <NUM>. The HBM <NUM> may include a logic die (or buffer die) <NUM> including control logic <NUM> for a memory operation and for controlling a neuromorphic computation and core dies <NUM> each including a memory cell array. A synaptic core <NUM> for neuromorphic computation may be respectively arranged in the core dies <NUM>. The HBM <NUM> may have a greater bandwidth by including a plurality of channels having independent interfaces to each other. In the example of <FIG>, the HBM <NUM> includes four core dies <NUM>, and each of the core dies <NUM> includes two channels, but any suitable number of core dies and channels may be provisioned. (In a minimal case, only one core die may be included).

The logic die <NUM> may further include a TSV area <NUM>, a physical area PHY <NUM>, and a direct access area <NUM>. The control logic <NUM> controls overall operations in the HBM <NUM>, and may perform, for example, an internal control operation in response to a command from an external controller.

TSV area <NUM> corresponds to an area where a TSV is formed for communication with the core dies <NUM>. The physical area PHY <NUM> may include a plurality of input circuits for communication with an external controller, and the direct access area <NUM> may directly communicate with an external tester via a conductive unit arranged on an external surface of the HBM <NUM>. Various signals provided by the tester may be provided to core dies <NUM> through the direct access area <NUM> and the TSV area <NUM>. Alternatively, according to a modifiable embodiment, various signals provided from a tester may be provided to the core dies <NUM> via the direct access area <NUM>, the physical area PHY <NUM>, and the TSV area <NUM>.

According to an embodiment of the inventive concept, each of the core dies <NUM> may include a plurality of synaptic cores <NUM>, and information from a synaptic core of any one core die (or a computation result) may be provided to a synaptic core of another core die. In addition, a semiconductor layer in which a router and an interconnect according to the above-described embodiment are arranged may be formed on each of the core dies <NUM>.

For example, a first core die Core Die <NUM> and a second core die Core Die <NUM>, information from a first synaptic core of the first core die Core Die <NUM> may be provided to the second core die Core Die <NUM> through a TSV of the TSV area <NUM> and a router/interconnect layer <NUM>. For example, information from the first synaptic core may be provided to a synaptic core of the same core die Core Die <NUM> through the TSV of the TSV area <NUM> or to any one synaptic core of other core dies.

According to the embodiment illustrated in <FIG>, as the HBM <NUM> having a greater bandwidth is used in performing neuromorphic computation, the bandwidth of the channels may be efficiently used in computing large-capacity data, and data latency may be reduced.

<FIG> is a block diagram illustrating an example of a mobile device, <NUM>, including a neuromorphic chip according to an embodiment of the inventive concept. The mobile device <NUM> is an example of a data processing system, and may include an application processor <NUM> and a neuromorphic chip <NUM>. The application processor <NUM> may be implemented as a system on chip (SoC). The system on chip (SoC) may include a system bus (not shown) to which a protocol having predefined bus standards is applied, and may include various Intellectual Properties (IP) connected to the system bus. As the standards for a system bus, an Advanced Microcontroller Bus Architecture (AMBA) protocol available by Advanced RISC Machine (ARM) may be applied. Examples of bus types of the AMBA protocol may include, for example, Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), AXI4, or AXI Coherency Extensions (ACE). In addition, other types of protocols such as uNetwork by SONICs® Inc. or CoreConnect by IBM®, or open core protocol by the OCP-IP may also be applied.

The application processor <NUM> may include a central processing unit <NUM> and a hardware accelerator <NUM> related to neuromorphic computation or neural network computation. While <FIG> illustrates one hardware accelerator <NUM>, the application processor <NUM> may include two or more hardware accelerators of various types. In addition, the application processor <NUM> may further include a memory <NUM> storing instructions to control an overall operation of the mobile device <NUM>. In addition, the application processor <NUM> may further include a modem processor <NUM> as an element for controlling a modem communication function, and the application processor <NUM> including the modem processor <NUM> may also be referred to as ModAP.

The neuromorphic chip <NUM> may include a semiconductor device according to the above-described embodiments. For example, the neuromorphic chip <NUM> may be a semiconductor package or a semiconductor chip having a stack structure of a plurality of semiconductor layers. For example, the neuromorphic chip <NUM> may include at least one synaptic core layer in which synaptic cores according to the above-described embodiments are formed and a router/interconnect layer arranged to correspond to the synaptic core layer. According to the above-described embodiments, the neuromorphic chip <NUM> may also be implemented such that synaptic cores and routers are formed in a same semiconductor layer, and interconnects are formed in an additional semiconductor layer.

According to the above-described embodiments, a plurality of semiconductor layers included in the neuromorphic chip <NUM> may communicate with each other via through electrodes such as a TSV, and information from a synaptic core of any one semiconductor layer of an embodiment of the inventive concept may be provided to a synaptic core of another semiconductor layer through a TSV and a router/interconnect layer.

In the above-described embodiments, through silicon vias (TSVs) have been described as an example of a through electrode (the latter also known as a via (vertical interconnected access)) but other types of through electrodes may be substituted for the TSVs.

Circuitry and interconnection arrangements exemplified above may be applied to other semiconductor devices such as an integrated circuit with a large number of parallel processing elements of a parallel processing system that employs routers to communicate information and control signals and share tasks with one another. The processing elements, disposed in semiconductor layers akin to the description above for the synaptic cores (which are themselves examples of processing elements), may be selectively and dynamically interconnected with each other through use of the global routers, global interconnects and TSVs in the same manner as described above for the synaptic cores.

Claim 1:
A semiconductor device comprising:
a first semiconductor layer (<NUM>) comprising one or more synaptic cores (<NUM>), each synaptic core comprising neural circuits (<NUM>) and a memory array (<NUM>) storing synapse information to perform neuromorphic computation;
a second semiconductor layer (<NUM>) stacked on the first semiconductor layer (<NUM>) and comprising an interconnect (TSV) forming a physical transfer path between synaptic cores (<NUM>);
a third semiconductor layer (<NUM>) stacked on the second semiconductor layer (<NUM>) and comprising one or more synaptic cores (<NUM>) each synaptic core comprising neural circuits (<NUM>) and a memory array (<NUM>) storing synapse information to perform neuromorphic computation; and
one or more through electrodes (TSV), through which information is transferred between the first through third semiconductor layers,
wherein a first synaptic core (SC1) in the first semiconductor layer is configured to transfer information including a result of neuromorphic computation to a second synaptic core in the third semiconductor layer (SC2) via the one or more through electrodes and the interconnect of the second semiconductor layer <NUM>),
wherein the second semiconductor layer (<NUM>) further comprises a router for determining an information transfer path between the synaptic cores.