Patent Description:
Nanowires show great promise for applications in quantum computing. Unfortunately, it is difficult to manufacture high quality nanowires in precise device geometries. Conventional processes for manufacturing nanowires include selective-area-growth (SAG) wherein nanowires are selectively grown directly on a substrate through a patterned mask layer. For many nanowire devices to function properly, the nanowires must be made of a conducting semiconductor material such as indium arsenide (InAs), indium antimonide (InSb), or indium arsenide antimonide (InAsSb). The substrate on which the nanowires are grown then must be an electrically insulating material at all relevant device operating frequencies, including RF. Examples of substrate materials meeting these criteria include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), silicon (Si), and germanium (Ge). There is often a large difference in the crystal lattice constant of the substrate and the nanowires. This crystal lattice mismatch causes crystalline defects in the nanowires during growth such as dislocations and stacking faults. The crystalline defects can penetrate the nanowires and in turn decrease the performance of the resulting nanowires.

In light of the above, there is a need for nanowires with reduced crystalline defects and methods of manufacturing the same.

<CIT> describes a radiation-emitting semiconductor component which is specified with at least one semiconductor layer sequence (<NUM>) grown epitaxially on a growth substrate (<NUM>) along a growth direction (<NUM>, <NUM>), which is based on a group III nitride compound semiconductor material and which has nitrogen polarity in the growth direction, the semiconductor layer sequence (<NUM>) in the growth direction (<NUM>, <NUM>) has an n-doped semiconductor layer (<NUM>) and above it an active zone (<NUM>), the active zone (<NUM>) containing at least one active layer which emits electromagnetic radiation during operation of the semiconductor component, and wherein the semiconductor layer sequence (<NUM>) is designed as a nanorod.

Furthermore, a method for producing a radiation-emitting semiconductor component is specified, wherein a plurality of the aforementioned nanorods (<NUM>) is covered by a planarized transparent dielectric material (<NUM>) and a reflective metal layer (<NUM>) on top, a carrier substrate (<NUM>) is then applied thereon, and the growth substrate (<NUM>) is removed thereafter.

<CIT> describes a process for fabricating multiple devices on a single substrate based on a structure transfer process. During operation, the process starts by forming structures of multiple devices on a first substrate. The process then bonds the structures of the multiple devices onto a second substrate. Next, the process transfers the multiple devices from the first substrate onto the second substrate by fracturing the structures of the multiple devices off the first substrate, wherein the transferred devices preserve physical orientation and material properties of the said fabricated structures, which may be semiconductor nanowires.

<CIT> describes a method of selective growth without catalyst on a semi-conducting structure. According to the method, which is applicable in electronics in particular: a semi-conducting structure, such as a nanowire, is formed from first gaseous or molecular flows; at a same time or subsequently, at least one second gaseous or molecular flow is added thereto, to selectively in situ grow a dielectric layer on the structure; and then another semi-conducting structure is grown thereon from third gaseous or molecular flows. The structure may then be detached from its growth substrate and deposited/laid onto another substrate.

<CIT> describes a mixed semiconductor-superconductor platform, particularly semiconductor-superconductor nanowires for use in quantum computing, which is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

The invention is set out in the appended independent claim <NUM>. Further embodiments are specified by the dependent claims.

In one embodiment, a method for manufacturing a nanowire includes providing a sacrificial substrate, providing a patterned mask layer on the sacrificial substrate, providing a nanowire on the sacrificial substrate through an opening in the patterned mask layer, providing a support structure on the nanowire, and removing the sacrificial substrate. A superconductor layer is provided on a top side of the nanowire before removing the sacrificial substrate. Because the sacrificial substrate is used for growing the nanowire and later removed, the material of the sacrificial substrate can be chosen to be lattice matched with the material of the nanowire without regard to the electrical properties thereof. Accordingly, a high-quality nanowire can be grown and operated without the degradation in performance normally experienced when using a lattice matched substrate.

In one embodiment, the sacrificial substrate is removed by a mechanical process such as polishing or grinding. In another embodiment, the sacrificial substrate is removed by a selective etching process. A sacrificial layer may be provided between the sacrificial substrate and the nanowire to facilitate the selective etching process in some embodiments.

Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the present invention, and together with the description serve to explain the principles of the invention.

<FIG> is a flow chart illustrating a method for manufacturing a nanowire according to one embodiment of the present invention. <FIG> illustrate each one of the steps in <FIG> and thus <FIG> and <FIG> are discussed together below. First, a sacrificial substrate <NUM> is provided (block <NUM> and <FIG>). The sacrificial substrate <NUM> provides support for growing a high-quality nanowire. Accordingly, the sacrificial substrate <NUM> is a material that is lattice matched with the material of the nanowire that will be grown on it. As defined herein, materials that are lattice matched have a difference in lattice constant less than <NUM>%. As discussed above, materials that provide good lattice matching for growing nanowires are often incompatible with the operation of the nanowires. This is because materials that provide good lattice matching are often not electrically insulating materials. The sacrificial substrate <NUM> is removed in a later step as discussed below and thus the electrical properties of the sacrificial substrate are irrelevant. Accordingly, the material of the sacrificial substrate <NUM> may be chosen solely based on its mechanical properties, namely its lattice constant in order to provide an ideal growth surface for one or more nanowires. Depending on the material of the nanowires grown on the sacrificial substrate <NUM>, the sacrificial substrate may comprise Indium Arsenide (InAs), Indium Antimonide (InSb), or Gallium Antimonide (GaSb).

A patterned mask layer <NUM> is provided on the sacrificial substrate <NUM> (block <NUM> and <FIG>). The patterned mask layer <NUM> may comprise an oxide material such as silicon dioxide, or any other suitable material for providing a mask layer. Providing the patterned mask layer <NUM> may comprise providing a blanket mask layer then patterning the blanket mask layer using a lithography process. One or more openings in the patterned mask layer <NUM> expose a surface of the sacrificial substrate <NUM> on which one or more nanowires can be grown.

A nanowire <NUM> is provided on the sacrificial substrate <NUM> through an opening in the patterned mask layer <NUM> (block <NUM> and <FIG>). Providing the nanowire <NUM> may comprise growing the nanowire <NUM> using a selective area growth (SAG) process. While the nanowire <NUM> is shown as a unified structure, the nanowire <NUM> may include any number of nanowire layers, which may be grown together or separately, and may comprise the same or different materials. The nanowire <NUM> may comprise, for example, indium arsenide (InAs), indium antimonide (InSb), and indium arsenide antimonide (InAsSb). The nanowire may have a thickness between <NUM> and <NUM>. Further, the nanowire <NUM> may have a diameter on the order of a nanometer (<NUM>-<NUM> meters) or a ratio of length to width greater than <NUM>. Because the material of the sacrificial substrate <NUM> is chosen to be lattice matched with the material of the nanowire <NUM>, the resulting quality of the nanowire <NUM> can be very high. In other words, the nanowire <NUM> may have very few, if any defects such as dislocations and stacking faults, thereby improving the performance of the nanowire <NUM>.

A superconductor layer <NUM> is provided on the nanowire <NUM> (block <NUM> and <FIG>). The superconductor layer <NUM> may also be provided on a portion of the patterned mask layer <NUM>. The superconductor layer <NUM> may be provided by any suitable deposition process. The superconductor layer <NUM> may comprise one of aluminum, lead, niobium, indium, tin, and vanadium. A thickness of the superconductor layer <NUM> may be between <NUM> and <NUM>.

A support structure <NUM> is provided on the nanowire <NUM> and the superconductor layer <NUM> (block <NUM> and <FIG>). The support structure <NUM> may comprise a dielectric material such as silicon nitride (SiN), or silicon dioxide (SiO<NUM>), or may comprise an organic polymer film. The support structure <NUM> is provided to give mechanical support to the nanowire <NUM> to allow removal of the sacrificial substrate <NUM> as discussed below. The support structure <NUM> may be provided by any suitable deposition process for a dielectric, including both in-situ and ex-situ processes.

The sacrificial substrate <NUM> is removed (block <NUM> and <FIG>). The sacrificial substrate <NUM> may be removed by any suitable process, such as by a mechanical process (e.g., polishing/grinding) or a chemical process (e.g., selective etching). While not shown in <FIG>, the patterned mask layer <NUM> may also be removed. As discussed above, the sacrificial substrate <NUM> provides an ideal growth substrate for the nanowire <NUM> because the material of the sacrificial substrate <NUM> is chosen to be lattice matched with the material of the nanowire <NUM>. However, the sacrificial substrate <NUM> does not have desirable electrical properties for the operation of the nanowire <NUM>. By providing the sacrificial substrate <NUM> as a growth substrate and later removing it, a high-quality nanowire <NUM> can be grown without interfering with the later operation of the nanowire <NUM>. Further, the sacrificial substrate <NUM> may be reused in some cases, thereby reducing waste and cost of manufacturing.

Optionally, a backside layer <NUM> may be provided on the nanowire <NUM> (block <NUM> and <FIG>). In some embodiments, the backside layer <NUM> is a single capping layer or an additional superconductor layer as illustrated in <FIG>. In other embodiments, the backside layer <NUM> is a gate structure including a dielectric layer <NUM> and gate contact <NUM> on the dielectric layer <NUM> as illustrated in <FIG>. Notably, the backside layer <NUM> may comprise any number of additional layers configured to perform any desired function without departing from the principles of the present disclosure. While the superconductor layer <NUM> is provided on a top side of the nanowire <NUM> in block <NUM>, the backside layer <NUM> may be provided on a back side of the nanowire <NUM> exposed after removing the sacrificial substrate <NUM>. Accordingly, the nanowire <NUM> may effectively be sandwiched between the superconductor layer <NUM> and the backside layer <NUM>. The backside layer <NUM> may allow for the creation of an additional electrostatic gate, which may enable additional control over the position of the electron wavefunction in the nanowire <NUM> and/or the density of electrons therein. Accordingly, the performance of the nanowire <NUM> may be improved.

<FIG> is a flow chart illustrating a method for manufacturing a nanowire according to an additional embodiment of the present invention. <FIG> illustrate each one of the steps in <FIG> and thus <FIG> and <FIG> are discussed together below. The method discussed with respect to <FIG> is largely the same as that discussed in <FIG>, and begins by providing the sacrificial substrate <NUM> (block <NUM> and <FIG>). The sacrificial substrate <NUM> provides support for growing a high-quality nanowire. Accordingly, the sacrificial substrate <NUM> is a material that is lattice matched with the material of the nanowire that will be grown on it. Depending on the material of the nanowires grown on the sacrificial substrate <NUM>, the sacrificial substrate <NUM> may comprise Indium Arsenide (InAs), Indium Antimonide (InSb), Indium phosphide (InP), or Gallium Antimonide (GaSb). In some embodiments, the sacrificial substrate <NUM> may comprise multiple layers such as a graded buffer layer.

A sacrificial layer <NUM> is provided on the sacrificial substrate <NUM> (block <NUM> and <FIG>). The sacrificial layer <NUM> provides a barrier between the sacrificial substrate <NUM> and the nanowire that will be grown thereon. A material of the sacrificial layer <NUM> is chosen to be selectively etchable with respect to the material of the nanowire <NUM> so that the sacrificial substrate <NUM> can be easily removed in a later etching process discussed below. In various embodiments, the sacrificial layer <NUM> may comprise Aluminum Antimonide (AlSb), Aluminum Arsenide (AlAs), and Aluminum Gallium Arsenide (AlGaSb), including an aluminum arsenide etch stop layer. The sacrificial layer <NUM> may also provide a lattice match with the material of the nanowire <NUM>.

The patterned mask layer <NUM> is provided on the sacrificial layer <NUM> (block <NUM> and <FIG>). The patterned mask layer <NUM> may comprise an oxide material such as silicon dioxide, or any other suitable material for providing a mask layer. Providing the patterned mask layer <NUM> may comprise providing a blanket mask layer then patterning the blanket mask layer using a lithography process. One or more openings in the patterned mask layer <NUM> expose a surface of the sacrificial substrate <NUM> on which one or more nanowires can be grown. While the sacrificial layer <NUM> is shown as a blanket layer on the sacrificial substrate <NUM> such that the patterned mask layer <NUM> is provided on the sacrificial layer <NUM>, in some embodiments the sacrificial layer <NUM> may only be provided in the openings of the patterned mask layer <NUM> such that the patterned mask layer <NUM> is provided on the sacrificial substrate <NUM> before the sacrificial layer <NUM>.

The nanowire <NUM> is provided on the sacrificial layer <NUM> through an opening in the patterned mask layer <NUM> (block <NUM> and <FIG>). Providing the nanowire <NUM> may comprise growing the nanowire <NUM> using a selective area growth (SAG) process. While the nanowire <NUM> is shown as a unified structure, the nanowire <NUM> may include any number of nanowire layers, which may be grown together or separately, and may comprise the same or different materials. The nanowire <NUM> may comprise, for example, indium arsenide (InAs) indium antimonide (InSb), and indium arsenide antimonide (InAsSb). The nanowire <NUM> may have a thickness between <NUM> and <NUM>. Further, the nanowire <NUM> may have a diameter on the order of a nanometer (<NUM>-<NUM> meters) or a ratio of length to width greater than <NUM>. Because the material of the sacrificial substrate <NUM> and the sacrificial layer <NUM> are chosen to be lattice matched with the material of the nanowire <NUM>, the resulting quality of the nanowire <NUM> can be very high. In other words, the nanowire <NUM> may have very few, if any defects such as dislocations and stacking faults, thereby improving the performance of the nanowire <NUM>.

The superconductor layer <NUM> is provided on the nanowire <NUM> (block <NUM> and <FIG>). The superconductor layer <NUM> may also be provided on a portion of the patterned mask layer <NUM>. The superconductor layer <NUM> may be provided by any suitable deposition process. The superconductor layer <NUM> may comprise one of aluminum, lead, niobium, indium, tin, and vanadium. A thickness of the superconductor layer <NUM> may be between <NUM> and <NUM>.

The support structure <NUM> is provided on the nanowire <NUM> and the superconductor layer <NUM> (block <NUM> and <FIG>). The support structure <NUM> may comprise a dielectric material such as silicon nitride (SiN) silicon dioxide (SiO<NUM>), or an organic polymer film. The support structure <NUM> is provided to give mechanical support to the nanowire <NUM> to allow removal of the sacrificial substrate <NUM> as discussed below. The support structure <NUM> may be provided by any suitable deposition process for a dielectric, including both in-situ and ex-situ processes.

The sacrificial substrate <NUM> and the sacrificial layer <NUM> are removed (block <NUM> and <FIG>). While not shown in <FIG>, the patterned mask layer <NUM> may also be removed. As discussed above, removing the sacrificial substrate <NUM> may comprise selectively etching the sacrificial layer <NUM>, whose material is chosen to be selectively etched with respect to the material of the nanowire <NUM>. By providing the sacrificial substrate <NUM> as a growth substrate and later removing it, a high-quality nanowire <NUM> can be grown without interfering with the later operation of the nanowire <NUM>.

Optionally, the backside layer <NUM> may be provided on the nanowire <NUM> (block <NUM> and <FIG>). As discussed above, the backside layer <NUM> may comprise a single capping layer or additional superconductor layer as shown in Figure <NUM>-<NUM> or a gate control structure including a dielectric layer <NUM> and a gate contact <NUM> on the dielectric layer <NUM> as shown in Figure <NUM>-<NUM>. Notably, the backside layer <NUM> may comprise any number of additional layers configured to perform any desired function without departing from the principles of the present disclosure. Specifically, while the superconductor layer <NUM> is provided on a top side of the nanowire <NUM> in block <NUM>, the backside layer <NUM> may be provided on a back side of the nanowire <NUM> exposed after removing the sacrificial substrate <NUM>. Accordingly, the nanowire <NUM> may effectively be sandwiched between the superconductor layer <NUM> and the backside layer <NUM>. The backside layer <NUM> may allow for the creation of an additional electrostatic gate, which may enable additional control over the position of the electron wavefunction in the nanowire <NUM> and/or the density of electrons therein. Accordingly, the performance of the nanowire <NUM> may be improved.

Notably, the processes discussed above are merely illustrative. In general, the present disclosure contemplates growing one or more nanowires on a lattice matched sacrificial substrate, then later removing the sacrificial substrate so that it does not interfere with the operation of the one or more nanowires. Those skilled in the art will appreciate that any suitable process for accomplishing these objectives is contemplated herein.

Claim 1:
A method for manufacturing a nanowire (<NUM>) comprising:
• providing a sacrificial substrate (<NUM>) (block <NUM>);
• providing a patterned mask layer (<NUM>) on the sacrificial substrate (block <NUM>);
• providing the nanowire on the sacrificial substrate through an opening in the patterned mask layer (block <NUM>);
• providing a support structure (<NUM>) on the nanowire (block <NUM>);
• removing the sacrificial substrate (block <NUM>); and
• providing a superconductor layer (<NUM>) on a top side of the nanowire before removing the sacrificial substrate (block <NUM>).