Patent Description:
Integrated circuit (IC) devices are fabricated in a semiconductor wafer and divided into individual chips. Afterwards, those chips are assembled in package form to be used in electronic products. The package provides a structure to support the chip and protect the chip from the environment. The package also provides electrical connections to and from the chip.

In recent years, as electronic products have been become increasingly multifunctional and have been scaled down in size, there is a desire for manufacturers of semiconductor devices to make more devices formed on a single semiconductor wafer, so that the electronic products that include these devices can be made more compact. This results in many new challenges to the structural and electrical design of the package.

Accordingly, a chip scale package (CSP) technology has been developed to satisfy the industry's demands (e.g., the smaller chip size and form factor). Moreover, a wafer level package (WLP) technology also has been introduced for cost-effective fabrication of packages. Such a technology is referred to as wafer-level chip scale package (WLCSP).

However, in the use of the WLCSP process, the surface of each chip in the respective package is exposed to the environment after the packages are separated from the package wafer. As a result, damage to the chip may occur, thereby reducing the reliability of the semiconductor packages. Thus, a novel semiconductor package structure and the fabrication method thereof are desirable.

A method for packaging semiconductor dies is known from <CIT>. The method comprises placing individual dies on an interface layer above a carrier substrate, encapsulating the dies by an encapsulant and forming insulating and redistribution layers above the dies and the encapsulant.

<CIT> discloses a semiconductor package structure comprising a semiconductor die with conductive pads and an insulating layer at a first surface thereof, an RDL structure formed on the insulating layer and electrically coupled to the semiconductor die via the conductive pads, a first protective insulating layer covering the first surface and side surfaces of the semiconductor die, a first passivation layer covering the first protective insulating layer and the RDL structure, and conductive structures passing through the first passivation layer and electrically coupled to the RDL structure.

<CIT> discloses a method for packaging semiconductor dies, which comprises forming a first conductive layer comprising conductive pads electrically connected to circuitry on an active surface of the dies, conformally applying an insulating stress-relief layer over the active surface, forming a temporary planarization layer on the stress-relief layer, and depositing a (second) protective insulating layer to cover a back surface and lateral surfaces of the semiconductor dies. The temporary planarization layer is removed completely and portions of the insulating layer are selectively removed to expose the conductive pads. Another (first) protective insulating layer is formed over the second protective insulating layer and the stress-relief layer. A conductive layer conductive layer functioning as a fan-out redistribution layer is formed on the first protective insulating layer and the conductive pads and is covered by a passivation layer prior to singulating the wafer into individual dies.

The present invention relates to a semiconductor package structure according to claim <NUM> and a method of forming a semiconductor package structure according to claim <NUM>. Embodiments of the present invention are detailed in the dependent claims.

A detailed description is given in the following examples useful for understanding the present invention and embodiments of the present invention with reference to the accompanying drawings.

The scope of the invention is determined by reference to the appended claims.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

<FIG> are cross-sectional views of an exemplary method of forming a semiconductor package structure useful for understanding the invention but not encompassed by the wording of the claims. As shown in <FIG>, a substrate <NUM> is provided. In some examples, the substrate <NUM> may include a plurality of chip regions and a scribe line region that surrounds the plurality of chip regions and separates the adjacent chip regions from each other. To simplify the diagram, only two complete and adjacent chip regions C and a scribe line region S separating these chip regions C are depicted herein. The substrate <NUM> may be a silicon wafer so as to facilitate the wafer-level packaging process. For example, the substrate <NUM> may be a silicon substrate or another semiconductor substrate.

In some examples, the chip regions C of the substrate <NUM> include integrated circuits (not shown) therein. In some examples, an insulating layer <NUM> is formed on the substrate <NUM>. The insulating layer <NUM> may serve as an inter-dielectric (ILD) layer, an inter-metal dielectric (IMD) layer, a passivation layer or a combination thereof. To simplify the diagram, only a flat layer is depicted herein. In some examples, the insulating layer <NUM> is made of an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a combination thereof, or another suitable insulating material.

Moreover, the insulating layer <NUM> includes one or more conductive pads <NUM> therein. The conductive pads <NUM> correspond to the chip regions C of the substrate <NUM> and are adjacent to the upper surface of the substrate <NUM>. The conductive pad <NUM> may be formed of metal, such as copper, aluminum, or another suitable metal material. To simplify the diagram, only one conductive pad <NUM> formed on the substrate <NUM> in each chip region C and exposed from the insulating layer <NUM> is depicted herein as an example. In some examples, the ICs in the chip region C is electrically connected to the corresponding conductive pad <NUM>. The aforementioned structure define a number of semiconductor dies/chips after the chip regions C are separated from each other by dicing the scribe line region S of the substrate <NUM>.

In some examples, a conductive layer (not shown), such as a metal layer, is formed on the insulating layer <NUM> and passing through the insulating layer <NUM> to electrically couple to the exposed pads <NUM> in the chip regions C. Afterwards, the conductive layer is patterned to form a redistribution layer (RDL) structure <NUM> in each of the chip regions C, so that the RDL structure <NUM> is electrically coupled to the subsequent formed semiconductor die, as shown in <FIG>.

As shown in <FIG>, in some examples, the chip regions C are separated from each other by dicing the scribe line region S of the substrate <NUM> to form semiconductor dies with the RDL structures <NUM> thereon. The formed semiconductor die may be a system on chip (SOC) integrated circuit die. The SOC integrated circuit die, for example, may include a logic die including a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller or any combination thereof. Each of semiconductor dies includes a substrate <NUM>, at least one conductive pad <NUM> formed on the substrate <NUM>, and an insulating layer <NUM> formed over the substrate <NUM> and having an opening to expose the conductive pad <NUM>. Moreover, the semiconductor die has a first surface 101a (e.g., an active surface of the semiconductor die), a second surface 101b (e.g., a non-active surface of the semiconductor die) opposite the first surface 101a, and a third surface 101c (e.g., a sidewall surface of the semiconductor die) adjoined between the first surface 101a and the second surface101b.

As shown in <FIG>, in some examples, a carrier substrate <NUM> with an adhesive layer <NUM> formed thereon is provided. The carrier substrate <NUM> may be made of silicon, glass, ceramic or the like, and may have a shape that is the same or similar to the semiconductor wafer, and therefore the carrier substrate <NUM> is sometimes referred to as a carrier wafer. The adhesive layer <NUM> may be made of a light-to-heat conversion (LTHC) material or another suitable material. Afterwards, in some examples, the second surface 101b of each semiconductor die that has an RDL structure <NUM> formed on the first surface 101a of the semiconductor die is mounted onto the carrier substrate <NUM> via the adhesive layer <NUM> using a pick-and-place process.

Next, in some examples, a protective insulating layer <NUM> is formed to cover the first surface 101a and the third surface 101c of the semiconductor dies and to surround the RDL structures <NUM>, so that each of the formed semiconductor dies with an RDL structure <NUM> thereon is encapsulated by the protective insulating layer <NUM>. In some examples, the protective insulating layer <NUM> protects the semiconductor dies from the environment, thereby preventing the semiconductor die in the subsequently formed semiconductor package structure from damage due to, for example, the stress, the chemicals and/or the moisture.

In some examples, the protective insulating layer <NUM> is made of an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material. In some examples, the protective insulating layer <NUM> is made of an epoxy molding compound (EMC) and formed by a molding process. For example, the protective insulating layer <NUM> (such as in an epoxy or resin) may be applied while substantially liquid, and then may be cured through a chemical reaction. The protective insulating layer <NUM> may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being formed around the semiconductor dies, and then may be cured through a UV or thermal curing process. The protective insulating layer <NUM> may be cured with a mold (not shown).

After the protective insulating layer <NUM> is formed, the semiconductor dies with RDL structures <NUM> encapsulated by the protective insulating layer <NUM> are de-bonded from the carrier substrate <NUM>, as shown in <FIG>. In some examples, a de-bonding process is performed by exposing the adhesive layer <NUM> (shown in <FIG>) using a laser or UV light when the adhesive layer <NUM> is made of an LTHC material. The LTHC material may be decomposed due to generated heat from the laser or UV light, and hence the carrier substrate <NUM> is removed from the structure including the semiconductor dies, the RDL structures <NUM>, and the protective insulating layer <NUM>. As a result, the second surface 101b of each semiconductor die is exposed from the protective insulating layer <NUM>. The resulting structure is shown in <FIG>.

In some examples, after the carrier substrate <NUM> is removed by the de-bonding process, a grinding process is performed on the top surface of the protective insulating layer <NUM> until the RDL structures <NUM> are exposed from the protective insulating layer <NUM>, as shown in <FIG>. For example, the top surface of the protective insulating layer <NUM> may be grinded by a chemical mechanical polishing (CMP) process or another suitable grinding process.

Afterwards, the protective insulating layer <NUM> and the RDL structures <NUM> are covered with a passivation layer <NUM>, as shown in <FIG>. In some examples, the passivation layer <NUM> is formed on the protective insulating layer <NUM> and the RDL structures <NUM> by a coating process or another suitable deposition process. Afterwards, the passivation layer <NUM> is patterned by lithography or a combination of lithograph and etching to form openings that expose the RDL structures <NUM>. In some examples, the passivation layer <NUM> is made of a material that is different from the material of the protective insulating layer <NUM>. In some examples, the passivation layer <NUM> is made of polyimide or polybenzoxazole (PBO).

In some examples, during patterning the passivation layer <NUM>, the passivation layer <NUM> is also divided into several portions, so that each of the semiconductor dies is covered by a respective portion of passivation layer <NUM>. In some other examples, the passivation layer <NUM> is divided into several portions by the subsequent dicing process.

After openings are formed in the passivation layer <NUM>, conductive structures <NUM> respectively pass through the passivation layer <NUM> via those openings formed in the passivation layer <NUM>, as shown in <FIG>. In some examples, the conductive structures <NUM> fill into the openings formed in the passivation layer <NUM>, so that each of the conductive structures <NUM> is electrically coupled to the respective exposed RDL structure <NUM> under the opening in the passivation layer <NUM>.

In some examples, the conductive structure <NUM> includes an optional under-bump metallurgy (UBM) layer <NUM> and a solder bump <NUM> on the UBM layer <NUM>. In some other examples, the conductive structure <NUM> includes a conductive bump structure such as a copper bump, a conductive pillar structure, a conductive wire structure, or a conductive paste structure.

After the conductive structures <NUM> are formed, an optional protective insulating layer <NUM> is formed to cover the exposed second surfaces 101b of the semiconductor dies, as shown in <FIG>. The protective insulating layer <NUM> is sometimes referred to as a die backside film (DBF) that is made of a thermoset material, such as an epoxy resin material. In some other examples, the protective insulating layer <NUM> is made of a material that is the same as the material of the protective insulating layer <NUM>. For example, the protective insulating layer <NUM> is made of an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material.

In some examples, after the protective insulating layer <NUM> is formed, a singulation is carried out to saw through the formed structure shown in <FIG>. For example, a dicing process may be performed on the formed structure shown in <FIG>. As a result, multiple separate semiconductor package structures are formed.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure useful for understanding the invention but not encompassed by the wording of the claims. In <FIG>, one of the semiconductor package structures 10a that is formed by dicing the formed structure shown in <FIG> is shown. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> may be omitted for brevity. In some examples, the semiconductor package structure 10a includes a semiconductor die that includes a substrate <NUM>, at least one conductive pad <NUM> formed on the substrate <NUM>, and an insulating layer <NUM> formed over the substrate <NUM> and having an opening to expose the conductive pad <NUM>, as shown in <FIG>. The semiconductor die has a first surface 101a (e.g., an active surface of the semiconductor die), a second surface 101b (e.g., a non-active surface of the semiconductor die) opposite the first surface 101a, and a third surface 101c (e.g., a sidewall surface of the semiconductor die) adjoined between the first surface 101a and the second surface 101b.

In some examples, the semiconductor package structure 10a further includes a protective insulating layer <NUM> that covers the first surface 101a and the third surface 101c of the semiconductor die, and a protective insulating layer <NUM> that covers the second surface 101b of the semiconductor die. The thickness of the portion of the protective insulating layer <NUM> covering the first surface 101a and the thickness of the of the portion of the protective insulating layer <NUM> covering the third surface 101c of the semiconductor die can be adjusted, so as to fine-tune the protection ability of the semiconductor package structure 10a.

In some examples, the protective insulating layer <NUM> and the protective insulating layer <NUM> are made of the same material or different materials. For example, such a material may include an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material. Alternatively, the protective insulating layer <NUM> is made of an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material, and the protective insulating layer <NUM> is made of a DBF material that includes a thermoset material, such as an epoxy resin material.

In some examples, the semiconductor package structure 10a further includes an RDL structure <NUM> electrically coupled to the semiconductor die via the conductive pad <NUM> and surrounded by the protective insulating layer <NUM> on the first surface 101a of the semiconductor die.

In some examples, the semiconductor package structure 10a further includes a passivation layer <NUM> covering the RDL structure <NUM> and a portion of the protective insulating layer <NUM> surrounding the RDL structure <NUM>. The passivation layer <NUM> may be made of polyimide or polybenzoxazole (PBO).

In some examples, the semiconductor package structure 10a further includes at least one conductive structure <NUM> that includes an optional UBM layer <NUM> and a solder bump <NUM> and passes through the passivation layer <NUM>, so as to be electrically coupled to the semiconductor die through the RDL structure <NUM>.

In some examples, the semiconductor package structure 10a shown in <FIG> is a CSP structure. The CSP structure may include an SOC package. Moreover, the semiconductor package structure 10a may be mounted on a base (not shown). The base may include a printed circuit board (PCB) and may be formed of polypropylene (PP). Alternatively, the base may include a package substrate. The semiconductor package structure 10a may be mounted on the base by a bonding process. For example, the semiconductor package structure 10a may be mounted on the base by the bonding process and electrically coupled to the base using the conductive structures <NUM> as connectors.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure in accordance with some examples. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> may be omitted for brevity. In some examples, the semiconductor package structure 10b is similar to the semiconductor package structure 10a shown in <FIG>. Compared to the semiconductor package structure 10a, there is no protective insulating layer <NUM> formed in the package structure 10b, and hence the second surface 101b of the semiconductor die is exposed to the environment. In some examples, the semiconductor package structure 10b is formed by a method that is similar to the method shown in <FIG>, except that the formation of the protective insulating layer <NUM>, as shown in <FIG>, is omitted. Namely, after the structure shown in <FIG> is formed, a singulation is carried out to saw through the formed structure shown in <FIG>.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure useful for understanding the invention but not encompassed by the wording of the claims. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> may be omitted for brevity. In some examples, the semiconductor package structure 10c is similar to the semiconductor package structure 10a shown in <FIG>. Compared to the semiconductor package structure 10a, the semiconductor package structure 10c further includes a passivation layer <NUM> formed between the first surface 101a of the semiconductor die and the RDL structure <NUM> and covered by the protective insulating layer <NUM>. In some examples, the material and the method used for the passivation layer <NUM> are the same as or similar to those used for the passivation layer <NUM>. For example, the passivation layer <NUM> is made of polyimide or polybenzoxazole (PBO). In some examples, the semiconductor package structure 10c is formed by a method that is similar to the method shown in <FIG>, except that an additional passivation layer <NUM> is formed prior to the formation of the RDL structure <NUM>. Prior to the formation of the RDL structure <NUM>, at least one opening is formed in the passivation layer <NUM>, so that the passivation layer <NUM> exposes the conductive pad <NUM> and surrounds the opening formed in the insulating layer <NUM>.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure useful for understanding the invention but not encompassed by the wording of the claims. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> and <FIG> may be omitted for brevity. In some examples, the semiconductor package structure 10d is similar to the semiconductor package structure 10c shown in <FIG>. Compared to the semiconductor package structure 10c, there is no protective insulating layer <NUM> formed in the package structure 10d, and hence the second surface 101b of the semiconductor die is exposed to the environment. In some examples, the semiconductor package structure 10d is formed by a method that is similar to the method used for forming the semiconductor package structure 10c, except that the formation of the protective insulating layer <NUM> is omitted.

<FIG> are cross-sectional views of an exemplary method of forming a semiconductor package structure in accordance with some embodiments of the present invention. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to <FIG> may be omitted for brevity. As shown in <FIG>, a structure as shown in <FIG> is provided. Afterwards, a first protective insulating layer 110a to cover the first surface 101a of each semiconductor die and surround each RDL structure <NUM>, so that the top surfaces and sidewalls of the RDL structures <NUM> are covered or encapsulated by the first protective insulating layer 110a. In some embodiments, the first protective insulating layer 110a is made of an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material. In some embodiments, the first protective insulating layer 110a is formed by a coating process, a molding process, or another suitable process.

As shown in <FIG>, in some embodiments, after the first protective insulating layer 110a is formed, the chip regions C are separated from each other by dicing the scribe line region S of the substrate <NUM> to form semiconductor dies with the RDL structures <NUM> thereon. The formed semiconductor die has a first surface 101a (e.g., an active surface of the semiconductor die), a second surface 101b (e.g., a non-active surface of the semiconductor die) opposite the first surface 101a, and a third surface 101c (e.g., a sidewall surface of the semiconductor die) adjoined between the first surface 101a and the second surface101b. Moreover, the first protective insulating layer 110a has a sidewall <NUM> that is substantially aligned with the third surface 101c of the semiconductor die.

Still referring to <FIG>, in some embodiments, a carrier substrate <NUM> with an adhesive layer <NUM> formed thereon is provided. Afterwards, in some embodiments, each of the formed semiconductor dies with an RDL structure <NUM> formed on the first surface 101a of the semiconductor die is mounted onto the carrier substrate <NUM> by attaching the top surface of the first protective insulating layer 110a to the adhesive layer <NUM> using a pick-and-place process. As a result, the second surface 101b of each semiconductor die is opposite the carrier substrate <NUM>.

Next, a second protective insulating layer <NUM> is formed using a molding process to cover the second surface 101b and the third surface 101c of the semiconductor dies and surround the first protective insulating layer 110a, so that the second protective insulating layer <NUM> extends from the third surface 101c of each semiconductor die to the sidewall <NUM> of the respective protective insulating layer. As a result, each of the formed semiconductor dies with an RDL structure <NUM> thereon is encapsulated by a protective structure including the first protective insulating layer 110a and the second protective insulating layer <NUM>.

The protective structure protects the semiconductor dies from the environment, thereby preventing the semiconductor die in the subsequently formed semiconductor package structure from damage due to, for example, the stress, the chemicals and/or the moisture. In some embodiments, the second protective insulating layer <NUM> of the protective structure is formed by a molding process while the first protective insulating layer 110a of the protective structure is formed by a coating process.

After the protective structure is formed, the semiconductor dies with RDL structures <NUM> encapsulated by the protective structure are de-bonded from the carrier substrate <NUM> by a de-bonding process as shown in <FIG>. The resulting structure is shown in <FIG>.

After the carrier substrate <NUM> is removed by the de-bonding process, a grinding process is performed on the first protective insulating layer 110a above the RDL structures <NUM> and a portion of the second protective insulating layer <NUM> surrounding the first protective insulating layer 110a until the RDL structures <NUM> are exposed from the first protective insulating layer 110a, as shown in <FIG>. The first protective insulating layer 110a and the second protective insulating layer <NUM> may be grinded by a CMP process or another suitable grinding process.

Afterwards, the first protective insulating layer 110a and the RDL structures <NUM> are covered with a patterned first passivation layer <NUM>, as shown in <FIG>. In some embodiments, the first passivation layer <NUM> is made of a material that is different from the material of the first protective insulating layer 110a and the material of the second protective insulating layer <NUM>. In some embodiments, during patterning the first passivation layer <NUM>, the first passivation layer <NUM> is also divided into several portions, so that each of the semiconductor dies is covered by a respective portion of first passivation layer <NUM>. In some other embodiments, the first passivation layer <NUM> is divided into several portions by the subsequent dicing process.

After openings are formed in the first passivation layer <NUM>, conductive structures <NUM> including an optional UBM layer <NUM> and a solder bump <NUM> respectively pass through the first passivation layer <NUM> via those openings, as shown in <FIG>. As a result, each of the conductive structures <NUM> is electrically coupled to the respective exposed RDL structure <NUM>.

In some embodiments, after the conductive structures <NUM> is formed, a singulation (e.g., a dicing process) is carried out to saw through the formed structure shown in <FIG>. As a result, multiple separate semiconductor package structures are formed.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the present invention. In <FIG>, one of the semiconductor package structures 20a that is formed by dicing the formed structure shown in <FIG> is shown. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to <FIG> may be omitted for brevity. The semiconductor package structure 20a includes a semiconductor die that includes a substrate <NUM>, at least one conductive pad <NUM> formed on the substrate <NUM>, and an insulating layer <NUM> formed over the substrate <NUM> and having an opening to expose the conductive pad <NUM>, as shown in <FIG>. The semiconductor die has a first surface 101a (e.g., an active surface of the semiconductor die), a second surface 101b (e.g., a non-active surface of the semiconductor die) opposite the first surface 101a, and a third surface 101c (e.g., a sidewall surface of the semiconductor die) adjoined between the first surface 101a and the second surface101b.

The semiconductor package structure 20a further includes a first protective insulating layer 110a that covers the first surface 101a of the semiconductor die, and a second protective insulating layer <NUM> that covers the second surface 101b and the third surface 101c of the semiconductor die and that surrounds the first protective insulating layer 110a. The first protective insulating layer 110a has a sidewall <NUM> that is substantially aligned with the third surface 101c of the semiconductor die. The second protective insulating layer <NUM> extends from the third surface 101c of the semiconductor die to the sidewall <NUM> of the first protective insulating layer 110a. The thickness of the first protective insulating layer 110a covering the first surface 101a and the thickness of the second protective insulating layer <NUM> covering the second surface 101b and the third surface 101c of the semiconductor die can be adjusted, so as to fine-tune the protection ability of the semiconductor package structure 20a.

In some embodiments, the first protective insulating layer 110a and the second protective insulating layer <NUM> are made of the same material or different materials. For example, such a material may include an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material.

The semiconductor package structure 20a further includes an RDL structure <NUM> electrically coupled to the semiconductor die via the conductive pad <NUM> and surrounded by the first protective insulating layer 110a.

The semiconductor package structure 20a further includes a first passivation layer <NUM> covering the RDL structure <NUM> and a portion of the first protective insulating layer 110a surrounding the RDL structure <NUM>. Moreover, the first passivation layer <NUM> is made of for example, polyimide or polybenzoxazole (PBO).

The semiconductor package structure 20a further includes at least one conductive structure <NUM> that includes an optional UBM layer <NUM> and a solder bump <NUM> and passes through the first passivation layer <NUM>, so as to be electrically coupled to the semiconductor die through the RDL structure <NUM>.

In some embodiments, the semiconductor package structure 20a shown in <FIG> is a CSP structure. The CSP structure may include an SOC package. Moreover, the semiconductor package structure 20a may be mounted on a base (not shown). The base may include a printed circuit board (PCB) and may be formed of polypropylene (PP). Alternatively, the base may include a package substrate. Similar to the semiconductor package structure 10a, the semiconductor package structure 20a may be mounted on the base by a bonding process and electrically coupled to the base using the conductive structures <NUM> as connectors.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure in accordance with some embodiments of the present invention. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to <FIG> may be omitted for brevity. The semiconductor package structure 20b is similar to the semiconductor package structure 20a shown in <FIG>. Compared to the semiconductor package structure 20a, the semiconductor package structure 20b further includes a second passivation layer <NUM> formed between the first surface 101a of the semiconductor die and the RDL structure <NUM> and covered by the first protective insulating layer 110a. In some embodiments, the material and the method used for the second passivation layer <NUM> are the same as or similar to those used for the first passivation layer <NUM> and different from those used for the first protective insulating layer 110a and those used for the second protective insulating layer <NUM>. In some embodiments, the semiconductor package structure 20b is formed by a method that is similar to the method shown in <FIG>, except that an additional second passivation layer <NUM> is formed prior to the formation of the RDL structure <NUM>. Prior to the formation of the RDL structure <NUM>, at least one opening is formed in the second passivation layer <NUM>, so that the second passivation layer <NUM> exposes the conductive pad <NUM> and surrounds the opening formed in the insulating layer <NUM>.

<FIG> are cross-sectional views of an exemplary method of forming a semiconductor package structure useful for understanding the invention but not encompassed by the wording of the claims. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> or <FIG> may be omitted for brevity. As shown in <FIG>, a structure as shown in <FIG> is provided. Afterwards, the chip regions C are separated from each other by dicing the scribe line region S of the substrate <NUM> to form semiconductor dies with the RDL structures <NUM> thereon. The formed semiconductor die has a first surface 101a (e.g., an active surface of the semiconductor die), a second surface 101b (e.g., a non-active surface of the semiconductor die) opposite the first surface 101a, and a third surface 101c (e.g., a sidewall surface of the semiconductor die) adjoined between the first surface 101a and the second surface101b.

As shown in <FIG>, in some examples, a carrier substrate <NUM> with an adhesive layer <NUM> formed thereon is provided. Afterwards, in some examples, each of the formed semiconductor dies with an RDL structure <NUM> formed on the first surface 101a of the semiconductor die is mounted onto the carrier substrate <NUM> by attaching the top surface and sidewall surface of the RDL structure <NUM> to the adhesive layer <NUM> using a pick-and-place process. As a result, the second surface 101b of each semiconductor die is opposite the carrier substrate <NUM>.

Next, in some examples, a protective insulating layer <NUM> is formed using a molding process to cover the second surface 101b and the third surface 101c of the semiconductor dies and surround the protective insulating layer 110a, so that the protective insulating layer <NUM> extends from the third surface 101c of each semiconductor die to the sidewall <NUM> of the respective protective insulating layer.

In some examples, after the protective insulating layer <NUM> is formed, the semiconductor dies with RDL structures <NUM> are de-bonded from the carrier substrate <NUM> by a de-bonding process (as shown in <FIG>). The resulting structure is shown in <FIG>.

In some examples, after the de-bonding process, a protective insulating layer 110a is formed by a coating process to cover the first surface 101a of each semiconductor die and surround each RDL structure <NUM>, as shown in <FIG>. As a result, the top surfaces and sidewalls of the RDL structures <NUM> are covered or encapsulated by the protective insulating layer 110a. Moreover, a portion of the protective insulating layer <NUM> covering the third surface 101c of the semiconductor die is capped by the protective insulating layer 110a. In some other examples, the protective insulating layer 110a is formed by a molding process or another suitable process.

Due to the formation of a protective structure including the protective insulating layer 110a and the protective insulating layer <NUM>, each of the formed semiconductor dies with an RDL structure <NUM> thereon is encapsulated. The protective structure protects the semiconductor dies from the environment, thereby preventing the semiconductor die in the subsequently formed semiconductor package structure from damage due to, for example, the stress, the chemicals and/or the moisture.

In some examples, after the protective structure is formed, a grinding process is performed on the protective insulating layer 110a above the RDL structures <NUM> until the RDL structures <NUM> are exposed from the protective insulating layer 110a, as shown in <FIG>. For example, the protective insulating layer 110a may be grinded by a CMP process or another suitable grinding process.

Afterwards, the protective insulating layer 110a and the RDL structures <NUM> are covered with a patterned passivation layer <NUM>, as shown in <FIG>. In some examples, the passivation layer <NUM> is made of a material that is different from the material of the protective insulating layer 110a and the material of the protective insulating layer <NUM>. In some examples, during patterning the passivation layer <NUM>, the passivation layer <NUM> is also divided into several portions, so that each of the semiconductor dies is covered by a respective portion of passivation layer <NUM>. In some other examples, the passivation layer <NUM> is divided into several portions by the subsequent dicing process.

After openings are formed in the passivation layer <NUM>, conductive structures <NUM> including an optional UBM layer <NUM> and a solder bump <NUM> respectively pass through the passivation layer <NUM> via those openings, as shown in <FIG>. As a result, each of the conductive structures <NUM> is electrically coupled to the respective exposed RDL structure <NUM>.

In some examples, after the conductive structures <NUM> is formed, a singulation (e.g., a dicing process) is carried out to saw through the formed structure shown in <FIG>. As a result, multiple separate semiconductor package structures are formed. In some examples, in the semiconductor package structure, the protective insulating layer 110a has a sidewall and a portion of the protective insulating layer covering the third surface 101c of the semiconductor die has a sidewall, and those sidewalls are substantially aligned with each other.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure useful for understanding the invention but not encompassed by the wording of the claims. In <FIG>, one of the semiconductor package structures 30a that is formed by dicing the formed structure shown in <FIG> is shown. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> or <FIG> may be omitted for brevity. In some examples, the semiconductor package structure 30a includes a semiconductor die that includes a substrate <NUM>, at least one conductive pad <NUM> formed on the substrate <NUM>, and an insulating layer <NUM> formed over the substrate <NUM> and having an opening to expose the conductive pad <NUM>, as shown in <FIG>. The semiconductor die has a first surface 101a (e.g., an active surface of the semiconductor die), a second surface 101b (e.g., a non-active surface of the semiconductor die) opposite the first surface 101a, and a third surface 101c (e.g., a sidewall surface of the semiconductor die) adjoined between the first surface 101a and the second surface 101b.

In some examples, the semiconductor package structure 30a further includes a protective insulating layer 110a that covers the first surface 101a of the semiconductor die, and a protective insulating layer <NUM> that covers the second surface 101b and the third surface 101c of the semiconductor die and that surrounds the protective insulating layer 110a. The protective insulating layer 110a has a sidewall <NUM> and a portion of the protective insulating layer 110a covering the third surface 101c of the semiconductor die has a sidewall <NUM>. In some examples, the sidewall <NUM> is substantially aligned with the sidewall <NUM>. Moreover, the portion of the protective insulating layer <NUM> covering the third surface 101c of the semiconductor die is capped by the protective insulating layer 110a. The thickness of the protective insulating layer 110a covering the first surface 101a and the thickness of the protective insulating layer <NUM> covering the second surface 101b and the third surface 101c of the semiconductor die can be adjusted, so as to fine-tune the protection ability of the semiconductor package structure 30a.

In some examples, the protective insulating layer 110a and the protective insulating layer <NUM> are made of the same material or different materials. For example, such a material may include an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material.

In some examples, the semiconductor package structure 30a further includes an RDL structure <NUM> electrically coupled to the semiconductor die via the conductive pad <NUM> and surrounded by the protective insulating layer 110a.

In some examples, the semiconductor package structure 30a further includes a passivation layer <NUM> covering the RDL structure <NUM> and a portion of the protective insulating layer 110a surrounding the RDL structure <NUM>. Moreover, the passivation layer <NUM> is made of for example, polyimide or polybenzoxazole (PBO).

In some examples, the semiconductor package structure 30a further includes at least one conductive structure <NUM> that includes an optional UBM layer <NUM> and a solder bump <NUM> and passes through the passivation layer <NUM>, so as to be electrically coupled to the semiconductor die through the RDL structure <NUM>.

In some examples, the semiconductor package structure 30a shown in <FIG> is a CSP structure. The CSP structure may include an SOC package. Moreover, the semiconductor package structure 30a may be mounted on a base (not shown). The base may include a printed circuit board (PCB) and may be formed of polypropylene (PP). Alternatively, the base may include a package substrate. Similar to the semiconductor package structure 10a or 20a, the semiconductor package structure 30a may be mounted on the base by a bonding process and electrically coupled to the base using the conductive structures <NUM> as connectors.

<FIG> is a cross-sectional view of an exemplary semiconductor package structure useful for understanding the invention but not encompassed by the wording of the claims. Descriptions of elements of the examples hereinafter that are the same as or similar to those previously described with reference to <FIG> may be omitted for brevity. In some examples, the semiconductor package structure 30b is similar to the semiconductor package structure 30a shown in <FIG>. Compared to the semiconductor package structure 30a, the semiconductor package structure 30b further includes a passivation layer <NUM> formed between the first surface 101a of the semiconductor die and the RDL structure <NUM> and covered by the protective insulating layer 110a. In some examples, the material and the method used for the passivation layer <NUM> are the same as or similar to those used for the passivation layer <NUM> and from those used for the protective insulating layer 110a and those used for the protective insulating layer <NUM>. In some examples, the semiconductor package structure 30b is formed by a method that is similar to the method shown in <FIG>, except that an additional passivation layer <NUM> is formed prior to the formation of the RDL structure <NUM>. Prior to the formation of the RDL structure <NUM>, at least one opening is formed in the passivation layer <NUM>, so that the passivation layer <NUM> exposes the conductive pad <NUM> and surrounds the opening formed in the insulating layer <NUM>.

According to the foregoing examples useful for understanding the present invention and the foregoing embodiments of the present invention, the semiconductor package structure is designed to fabricate a protective structure in the semiconductor package structure to cover or encapsulate the semiconductor die in the semiconductor package structure. The protective structure includes one or more protective insulating layers to protect the semiconductor die from the environment, thereby preventing the semiconductor die in the semiconductor package structure from damage due to, for example, the stress, the chemicals and/or the moisture.

Claim 1:
A semiconductor package structure (20a, 20b), comprising:
a semiconductor die having a first surface (101a), a second surface (101b) opposite the first surface (101a), and a third surface (101c) adjoined between the first surface (101a) and the second surface (101b), the semiconductor die including a substrate (<NUM>), at least one conductive pad (<NUM>) formed on the substrate (<NUM>), and an insulating layer (<NUM>) formed over the substrate (<NUM>), wherein the insulating layer (<NUM>) forms the first surface (101a) of the semiconductor die and has an opening to expose the conductive pad (<NUM>);
a first protective insulating layer (110a) covering the first surface (101a); and
a redistribution layer, RDL, structure (<NUM>) electrically coupled to the semiconductor die via the conductive pad (<NUM>) and surrounded by the first protective insulating layer (110a),
wherein:
a sidewall (<NUM>) of the first protective insulating layer (110a) is substantially aligned with the third surface (101c) of the semiconductor die;
the semiconductor package structure (20a, 20b) further comprises a second protective insulating layer (no) covering the second surface (101b) and the third surface (101c) of the semiconductor die and surrounding the first protective insulating layer (110a); and
a top surface of the first protective insulating layer (110a), the RDL structure (<NUM>) and the second protective insulating layer (no) is formed by forming the first protective insulating layer (110a) so that top surfaces and sidewalls of the RDL structure (<NUM>) are covered or encapsulated by the first protective insulating layer (110a),forming the second protective insulating layer (no) so as to surround the first protective insulating layer (110a) and performing a grinding process on the top surface of the first protective insulating layer (110a) above the RDL structure (<NUM>) and the portion of the second protective insulating layer (no) surrounding the first protective insulating layer (110a) until the RDL structure (<NUM>) is exposed from the first protective insulating layer (110a),
wherein the semiconductor package structure (20a, 20b) further comprises:
a first passivation layer (<NUM>) covering the top surface of the first protective insulating layer (110a) and the RDL structure (<NUM>); and
at least one conductive structure (<NUM>) passing through the first passivation layer (<NUM>) and electrically coupled to the RDL structure (<NUM>).