Patent Description:
In the current era of big data, quintillion bytes of data are created from edge devices and uploaded to storages and/or servers in the cloud every day. The edge devices providing entry points into enterprises or service providers' core networks can include, for non-limiting examples, routers, switches, multiplexers, and a variety of network access devices. For data protection, cryptography is often used in networking and storage of such data to make sure that the data is transmitted from the edge device and stored in the cloud securely. Different edge devices may need different processing rates.

For a non-limiting example, a <NUM> (or gbps) cryptographic engine is configured to encrypt and decrypt a data transfer at processing rate of <NUM> gbps (i.e., billions of bits per second), <NUM> gbps, and <NUM> gbps. An exemplary cryptographic system comprising four <NUM> cryptographic engines, two <NUM> cryptographic engines, and one <NUM> engine then picks one or more of the cryptographic engines based on the required processing rate of each data transfer. For non-limiting examples:.

Such cryptographic system however, is extremely costly because of redundant cryptographic engines being included in the cryptographic system.

Another conventional approach is to use time division multiplexing (TDM) on one single, e.g., <NUM>, cryptographic engine with ingress and egress buffers for each data transfer. The configurability is achieved by rearranging these additional ingress and egress buffers with some overhead mechanisms to switch data transfers among the buffers based on the required processing rates. However, this approach has cost and latency penalty because of the additional ingress and egress buffers, the lack of physical isolation, and power gating due to the sharing one single cryptographic engine.

Document <CIT> describes systems and methods associated with aggregation of cryptography engines.

Document <CIT> describes a receiving apparatus and method in view of a SerDes Framer Interface Level <NUM>.

Document <NPL>, describes a parallel architecture for cryptographic algorithm handling.

Accordingly, a need has arisen for a high-speed and configurable cryptographic system. A new cryptographic system is proposed where the cryptographic system includes a plurality of low processing rate (e.g., <NUM>) slices. Each slice may be configured to perform cryptographic operations on a data transfer at certain processing rate. The cryptographic system allows various aggregation/configuration among the plurality of low-rate processing slices to form processing units at various higher processing rates for integrity and/or confidentiality of data encryption/decryption. Such slice-aggregated cryptographic system achieves cost efficiency by adopting reusable and configurable components/slices, power efficiency by turning on only the slices that are needed for the current data transfer task, and secured design for data integrity since the slices used for the data transfer are physical isolated.

A system comprises one or more slice-aggregated cryptographic slices where each slice may be configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices where each slice may be configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to insert or remove a signature of the portion of the incoming data transfer and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.

It is appreciated that the plurality of operations is one or more of generating or checking the signature of the data transfer for integrity and encrypting or decrypting the data transfer for confidentiality. The portion of the incoming data transfer processed on one slice-aggregated cryptographic slice is physically isolated from the portions of the incoming data transfer processed on others slice-aggregated cryptographic slices. In some embodiments, the system further comprises one or more cross-slice channels among the slice-aggregated cryptographic slices, wherein each of the one or more cross-slice channels is configured to propagate information generated from one slice-aggregated cryptographic slice to another slice-aggregated cryptographic slice to achieve slice aggregation. In some embodiments, each of the one or more cross-slice channels is further configured to broadcast commonly-used information to all individual cryptographic slices within a slice-aggregated cryptographic slice so that per-slice resources are cascaded, shared, and operated together among the individual cryptographic slices based on configuration of the slice-aggregated cryptographic slice.

These and other aspects may be understood with reference to the following detailed description.

So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

It is contemplated that elements of one example may be beneficially incorporated in other examples.

Examples described herein relate to efficient and configurable slice-aggregated cryptographic system. Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. For example, various methods according to some examples can include more or fewer operations, and the sequence of operations in various methods according to examples may be different than described herein. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described.

The slice-aggregated cryptographic system described hereinafter uses a non-limiting example of four <NUM> cryptographic engines (a. slice) to illustrate the proposed approach to aggregate each slice based on the required processing rates. For non-limiting examples, the system is configured to aggregate two <NUM> cryptographic slices into one aggregated <NUM> cryptographic slice, or four <NUM> cryptographic slices into one aggregated <NUM> cryptographic slice. The system has no redundant slice for cost efficiency and provides per-slice controllability for power efficiency. The system also achieves physical isolation on each aggregated slice for data security. Although a four-slice cryptographic system is used as a non-limiting example to illustrate the proposed approach, same approach is also applicable to cryptographic systems having various number of cryptographic engines at varying data processing rates.

Referring now to <FIG>, which are block diagrams depicting examples of configurable slice-aggregated cryptographic systems for performing cryptographic operations on data transfers at various processing rates are shown.

<FIG> depicts an example of an architecture of a slice-aggregated cryptographic system <NUM>. The slice-aggregated cryptographic system <NUM> comprises a plurality of individual cryptographic slices 102_1,. , 102_4, e.g., Slice #<NUM> to Slice #<NUM> as shown in <FIG>. It is appreciated that each individual cryptographic slice <NUM> may be configured to process an incoming data transfer at <NUM> or 100gbps. As shown in <FIG>, each cryptographic slice <NUM> includes at least the following components in a chain: an ingress block <NUM>, which is in a serial connection with a cryptographic engine <NUM>, which is in a serial connection an egress block <NUM>. The ingress block <NUM> is configured to take an incoming data transfer at a certain processing rate, e.g., <NUM>, inform the cryptographic engine <NUM> of processing (e.g., cryptographic operations) needed for the data transfer, and feed the data into the cryptographic engine <NUM> accordingly for such processing. Upon receiving the data from the ingress block <NUM>, the cryptographic engine <NUM> is configured to perform one or more cryptographic processing and/or operations on the data. The cryptographic operations include but are not limited to generating or checking a signature of the data transfer for integrity and/or encrypting or decrypting the data for confidentiality. Once the cryptographic operations are completed by the cryptographic engine <NUM>, the egress block <NUM> is configured to insert or remove a signature of the data transfer and transmit the encrypted or decrypted data for further processing or transmission.

In some embodiments, a slice-aggregated cryptographic system is configured to aggregate multiple individual cryptographic slices <NUM> into one slice-aggregated cryptographic slice to meet the required processing rate of an incoming data transfer. <FIG> depicts an example of an architecture of a slice-aggregated cryptographic system <NUM>. The slice-aggregated cryptographic system <NUM> comprises two slice-aggregated cryptographic slices 202_1 and 202_2, each comprising two individual <NUM> cryptographic slices 102_1/102_2 and 102_3/102_4, respectively. As a result, each <NUM>-slice-aggregated cryptographic slice <NUM> is configured to process an incoming data transfer at <NUM> or 200gbps, i.e., aggregated processing rates of the two individual cryptographic slices <NUM> in the slice-aggregated cryptographic slice <NUM>. When a data transfer at <NUM> is received by the slice-aggregated cryptographic slice <NUM>, the incoming data transfer is split between and fed into the ingress blocks <NUM> of the two individual cryptographic slices <NUM> of the slice-aggregated cryptographic slice <NUM> and processed by components in each of the individual cryptographic slices <NUM> in parallel as discussed above. Once the two individual cryptographic slices <NUM> have both completed processing their respective portions of the data transfer, the slice-aggregated cryptographic slice <NUM> is configured to merge output from the egress blocks <NUM> of its two individual cryptographic slices <NUM> into one data output for further transfer and/or processing.

<FIG> depicts an example of an architecture of a slice-aggregated cryptographic system <NUM>. The slice-aggregated cryptographic system <NUM> comprises one slice-aggregated cryptographic slice <NUM> comprising four individual <NUM> cryptographic slices 102_1,. As a result, the <NUM>-slice-aggregated cryptographic slice <NUM> is configured to process an incoming data transfer at <NUM> or 400gbps, i.e., the aggregated processing rate of the four individual cryptographic slices <NUM> in the slice-aggregated cryptographic slice <NUM>. When a data transfer at <NUM> is received by the slice-aggregated cryptographic slice <NUM>, the incoming data is split among and fed into the ingress blocks <NUM> of the four individual cryptographic slices <NUM> of the slice-aggregated cryptographic slice <NUM> and processed by components in each of the individual cryptographic slices <NUM> in parallel, as discussed above. Once all four individual cryptographic slices <NUM> have completed processing their respective data, the slice-aggregated cryptographic slice <NUM> is configured to merge output from the egress blocks <NUM> of its four individual cryptographic slices <NUM> into one data output for further transfer and/or processing.

In some embodiments, a slice-aggregated cryptographic system is configured to include a mix of both one or more individual cryptographic slices <NUM> as well as one or more slice-aggregated cryptographic slices in order to accommodate multiple data transfers at different processing rates. <FIG> depicts an example of an architecture of a hybrid slice-aggregated cryptographic system <NUM>. The hybrid slice-aggregated cryptographic system <NUM> includes two individual <NUM> cryptographic slices 102_1 and 102_4, and one <NUM>-slice-aggregated cryptographic slice <NUM> that includes two individual <NUM> cryptographic slices 102_2 and 102_3. Under such configuration, the hybrid slice-aggregated cryptographic system <NUM> is configured to process multiple incoming data transfers at different required processing rates at the same time, e.g., a first data transfer at <NUM> via the individual <NUM> cryptographic slice102_1 and a second data transfer at <NUM> via the <NUM>-slice-aggregated cryptographic slice <NUM> including two individual <NUM> cryptographic slices 102_2 and 102_3. Note that the individual cryptographic slice 102_4 in the example of <FIG> is not used and can be powered off (inactive) for power efficiency as discussed in step <NUM> of <FIG> below.

In some embodiments, each of the slice-aggregated cryptographic systems discussed above further includes one or more cross-slice channels <NUM> among the individual and/or slice-aggregated cryptographic slices. It is appreciated that each cross-slice channel <NUM> is configured to propagate generated metadata from one cryptographic slice to another cryptographic slice to achieve slice aggregation. In some embodiments, each cross-slice channel <NUM> may further be configured to broadcast commonly-used metadata to all individual cryptographic slices within a slice-aggregated cryptographic slice so that per-slice resources can be cascaded, shared, and operated together among the individual cryptographic slices based on the configuration of the slice-aggregated cryptographic slice. Resource-sharing within the slice-aggregated cryptographic slice, as described above, is cost efficient because resources of a low processing rate cryptographic slice can be reused by other cryptographic slices. In addition, since the slice-aggregated cryptographic systems, as discussed above, do not rely on time-division-multiplexing method no matter whether a cryptographic slice is a single cryptographic slice or aggregated with others into a slice-aggregated cryptographic slice, such slice-aggregated cryptographic systems provide better data security because the data portion processed on each cryptographic slice or slice-aggregated cryptographic slice is physically isolated from the data portion processed on others cryptographic slices.

In some embodiments, aggregating a plurality of the individual cryptographic slices into a slice-aggregated cryptographic slice involves sharing/propagating information/metadata among various components of the individual cryptographic slices <NUM>. In some embodiments, where the ingress blocks <NUM> of the individual cryptographic slices <NUM> are finite-state-machine based, relevant information of the ingress blocks <NUM> including but not limited to next state, internal flags, saved data, and statistic counters of the finite-state-machine based ingress blocks <NUM> are propagated from one individual cryptographic slice <NUM> to the next individual cryptographic slice <NUM> during aggregation of the individual cryptographic slices <NUM>. In some embodiments, where the cryptographic engines <NUM> are mathematic-logic based, operation results by the cryptographic engines <NUM> including but not limited to XOR results, multiplier results, and other cryptographic-algorithm-specific results of the mathematic-logic based cryptographic engines <NUM> are propagated from one individual cryptographic slice to the next individual cryptographic slice during aggregation of the individual cryptographic slices. In some embodiments, where the egress blocks <NUM> of the individual cryptographic slices are also finite-state-machine based, relevant information of the egress blocks <NUM> are propagated from one individual cryptographic slice to the next individual cryptographic slice in similar ways as the ingress blocks <NUM>. In some embodiments, current data framing information and end results are broadcasted to all individual cryptographic slices <NUM> for resource sharing. In some embodiments, only a part (e.g., one or more components) of the individual cryptographic slices <NUM> is aggregated by one of the slice-aggregated cryptographic slices, e.g., only the cryptographic engines <NUM> are aggregated across the individual cryptographic slices <NUM>.

In some embodiments, each slice-aggregated cryptographic slice is configured to handle the information/metadata based on configuration of the slice-aggregated cryptographic slice. <FIG> is a sequence diagram illustrating an example of operations for metadata sharing among cryptographic slices. Although the figure depicts functional steps in a particular order for purposes of illustration, the processes are not limited to any particular order or arrangement of steps. One skilled in the relevant art will appreciate that the various steps portrayed in this figure could be omitted, rearranged, combined and/or adapted in various ways.

As shown by the example of <FIG>, it is first determined at step <NUM> whether an individual cryptographic slice has been designated as a master slice. If an individual cryptographic slice is a master slice, the master slice is configured to generate current data framing information of the cryptographic slice at step <NUM>. It is then determined at step <NUM> whether the master slice is the only cryptographic slice or a part of a slice-aggregated cryptographic slice, e.g., cryptographic slice 102_1 in slice-aggregated cryptographic slice 202_1 of <FIG>, cryptographic slice 102_1 in slice-aggregated cryptographic slice <NUM> of <FIG>, and cryptographic slice 102_2 in slice-aggregated cryptographic slice <NUM> of <FIG>. If the master slice is the only cryptographic slice, it ignores any incoming information/metadata and not necessarily generate any metadata by itself. Otherwise, if the master slice is determined to be a part of a slice-aggregated cryptographic slice having more than one individual cryptographic slice, even if it is not a master slice (step <NUM>), it takes metadata from the previous individual cryptographic slice in the slice-aggregated cryptographic slice and generate its own metadata accordingly at step <NUM>. A non-master cryptographic slice that is not part of a slice-aggregated cryptographic slice is an invalid configuration, meaning that the individual cryptographic slice is not used and can be powered off for power efficiency at step <NUM>.

<FIG> is a block diagram depicting a programmable integrated circuit (IC) <NUM> according to an example. The programmable IC <NUM> can implement the integrated circuit (IC) chip of systems of <FIG>, in whole or in part. The programmable IC <NUM> includes a processing system <NUM>, programmable logic <NUM>, configuration logic <NUM>, and configuration memory <NUM>. The programmable IC <NUM> can be coupled to external circuits, such as nonvolatile memory <NUM>, RAM <NUM>, and other circuits <NUM>.

The processing system <NUM> can include microprocessor(s), memory, support circuits, IO circuits, and the like. The programmable logic <NUM> includes logic cells <NUM>, support circuits <NUM>, and programmable interconnect <NUM>. The logic cells <NUM> include circuits that can be configured to implement general logic functions of a plurality of inputs. The support circuits <NUM> include dedicated circuits, such as transceivers, input/output blocks, digital signal processors, memories, and the like. The logic cells and the support circuits <NUM> can be interconnected using the programmable interconnect <NUM>. Information for programming the logic cells <NUM>, for setting parameters of the support circuits <NUM>, and for programming the programmable interconnect <NUM> is stored in the configuration memory <NUM> by the configuration logic <NUM>. The configuration logic <NUM> can obtain the configuration data from the nonvolatile memory <NUM> or any other source (e.g., the RAM <NUM> or from the other circuits <NUM>).

<FIG> illustrates an FPGA implementation of the programmable IC <NUM> that includes a large number of different programmable tiles including configurable logic blocks ("CLBs") <NUM>, random access memory blocks ("BRAMs") <NUM>, signal processing blocks ("DSPs") <NUM>, input/output blocks ("IOBs") <NUM>, configuration and clocking logic ("CONFIG/CLOCKS") <NUM>, digital transceivers <NUM>, specialized input/output blocks ("I/O") <NUM> (e.g., configuration ports and clock ports), and other programmable logic <NUM> such as digital clock managers, system monitoring logic, and so forth. The FPGA can also include PCIe interfaces <NUM>, analog-to-digital converters (ADC) <NUM>, and the like.

In some FPGAs, each programmable tile can include at least one programmable interconnect element ("INT") <NUM> having connections to input and output terminals <NUM> of a programmable logic element within the same tile, as shown by examples included in <FIG>. Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element <NUM> can also include connections to interconnect segments <NUM> of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments <NUM>) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments <NUM>) can span one or more logic blocks. The programmable interconnect elements <NUM> taken together with the general routing resources implement a programmable interconnect structure ("programmable interconnect") for the illustrated FPGA.

In an example implementation, a CLB <NUM> can include a configurable logic element ("CLE") <NUM> that can be programmed to implement user logic plus a single programmable interconnect element ("INT") <NUM>. A BRAM <NUM> can include a BRAM logic element ("BRL") <NUM> in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A signal processing block <NUM> can include a DSP logic element ("DSPL") <NUM> in addition to an appropriate number of programmable interconnect elements. An IOB <NUM> can include, for example, two instances of an input/output logic element ("IOL") <NUM> in addition to one instance of the programmable interconnect element <NUM>. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the input/output logic element <NUM> typically are not confined to the area of the input/output logic element <NUM>.

In the pictured example, a horizontal area near the center of the die is used for configuration, clock, and other control logic. Vertical columns <NUM> extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated in <FIG> include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic.

Note that <FIG> is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of <FIG> are purely exemplary. For example, in an actual FPGA more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.

Claim 1:
A system (<NUM>) comprising:
one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices (102_1, ..., 102_4), wherein each cryptographic slice of the one or more individual cryptographic slices (102_1, ..., 102_4) is configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate, wherein each of the one or more individual cryptographic slices (102_1, ..., 102_4) comprises at least the following components in a serial connection:
an ingress block (<NUM>) configured to take the portion of the incoming data transfer at the second processing rate, inform a cryptographic engine (<NUM>) of the operations needed, and feed the portion of the incoming data transfer to the cryptographic engine (<NUM>);
said cryptographic engine (<NUM>) configured to perform the operations on the portion of the incoming data transfer; and
an egress block (<NUM>) configured to insert or remove a signature of the portion of the incoming data transfer and output the portion of the incoming data transfer once the operations have completed;
wherein the first processing rate of each of the one or more slice-aggregated cryptographic slices equals aggregated second processing rates of the one or more individual cryptographic slices (102_1, ..., 102_4) in the slice-aggregated cryptographic slice,
wherein each slice of the one or more slice-aggregated cryptographic slices is configured to split and feed portions of the incoming data transfer into the ingress blocks (<NUM>) of the one or more individual cryptographic slices (102_1, ..., 102_4) in the slice-aggregated cryptographic slice.