Patent Description:
The following relates generally to wireless communication and more specifically to self-decodable redundancy versions (RVs) for LDPC codes.

Examples of such multiple-access systems include fourth generation (<NUM>) systems such as a Long Term Evolution (LTE) systems or LTE-Advanced (LTE-A) systems, and fifth generation (<NUM>) systems which may be referred to as New Radio (NR) systems. These systems may employ technologies such as code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiple access (OFDMA), or discrete Fourier transform-spread-OFDM (DFT-S-OFDM).

Wireless devices in a wireless communications system may transmit data to each other in the form of codewords. These codewords may be encoded by a transmitting device (e.g., a base station or UE) using an encoding algorithm. Error correcting codes may be used to introduce redundancy in a codeword so that transmission errors may be detected and corrected. Some examples of encoding algorithms with error correcting codes include convolutional codes (CCs), LDPC codes, and polar codes.

Wireless devices may also use retransmission techniques to improve the chances that a transmitted codeword is received. For example, wireless devices may support techniques for retransmitting multiple versions of a codeword (e.g., redundancy versions (RVs)) to improve the chances that the codeword is received. The redundancy version may tell a wireless device about the amount of redundancy added into a codeword while encoding. In some cases, some redundancy versions of a codeword may include mainly parity bits that a receiving device may combine with an original transmission of the codeword to decode the codeword. In such cases, however, if a receiving device fails to receive an original transmission of a codeword, the receiving device may not be able to decode some retransmitted versions of the codeword independently to identify any information in the codeword. As a result, a wireless communications system may experience reduced throughput.

The described techniques relate to improved methods, systems, devices, or apparatuses that support self-decodable redundancy versions for low-density parity-check (LDPC) codes. Aspects of the present invention are provided in the independent claims. Preferred embodiments are provided in the dependent claims.

Some wireless communications systems may support the use of error-correcting codes for introducing redundancy in a codeword so that transmission errors may be detected and corrected. These error correcting codes may generally compensate for the intrinsic unreliability of information transfer over the air interface. Low-density parity-check (LDPC) codes are one type of error correcting codes which may be used to increase the robustness of a transmission.

In addition to using error correcting codes, a wireless device may also support retransmissions of a codeword to increase the likelihood that the codeword is received successfully. Each of the multiple transmissions (e.g., and retransmissions) may include some portion of systematic bits (e.g., generated by a kernel of an encoder) and parity bits of the codeword, such that the decoder can use incremental redundancy (IR) to combine the codeword bits received in the multiple transmissions. In some cases, however, when LDPC coding schemes are used, some retransmissions of a codeword may not be self-decodable. That is, the retransmissions of the codeword may not include sufficient information about the encoded data bits to be independently decoded even without any transmission loss. Instead, the retransmissions may provide additional parity bits to allow a receiving device to successfully decode an original transmission of the codeword (e.g., using IR). In such cases, when the receiving device fails to receive the original transmission of the codeword, some retransmissions of the codeword may result in further decoding failures even where the channel would support decoding of the original transmission. These additional decoding failures may result in reduced throughput in a wireless communications system, especially in communications systems where bursty interference is present.

Redundancy versions may find use cases in many aspects of communications, such as grant-free transmissions, ultra-reliable low latency communication (URLLC), system information block (SIB) transmissions, etc. There are four different redundancy versions in NR. Redundancy version <NUM> (RV0) will normally be the first transmission due to its performance relative to the other RVs. Subsequent transmissions may utilize RV1, RV2, or RV3. RV3 is self-decodable at high coding rates, but its IR combining gain is relatively less than the other RVs. RV1 and RV2 are not self-decodable at high coding rates, but their IR combining gain is better than RV3. In use cases with a tight latency budget (e.g., URLLC), an efficient redundancy version having a good combination of self-decodability at high coding rates and IR combining gain is desirable.

As described herein, a wireless device supports efficient techniques for generating a retransmission for a codeword such that the retransmission may be independently decodable even when an original transmission of the codeword suffered high interference or was not received at all (e.g., when an original transmission grant was missed). Specifically, the wireless device re-orders bits in an encoded bit stream for a retransmission before storing these bits in a circular buffer. Once the bits are re-ordered and stored in the circular buffer, the wireless device selects bits from the buffer and transmits the selected bits to the receiving device. By re-ordering bits in the encoded bit stream, the wireless device ensures that sets of information bits are distributed evenly across the selected bits. Accordingly, when the wireless device selects bits from the circular buffer for the retransmission, the retransmission includes sufficient systematic bits to enable the retransmission to be decoded by the receiving device with or without being combined with an original transmission.

In one example, the wireless device may re-order the bits in the encoded bit stream by first generating a matrix of bits that includes bits in the encoded bit stream. The matrix may be generated by allocating bits of the encoded bit stream to a number of rows and columns, where an equal number of bits may be allocated to each row and each column. Once the matrix is generated, the wireless device may perform a random circular shift on bits in each of the rows to randomize the bits to be included in the retransmission. The wireless device may then select bits to be stored in a circular buffer in order of increasing row index followed by increasing column index, and the wireless device may store the selected bits in the circular buffer. As such, when the wireless device selects a contiguous set of stored bits from the circular buffer for the retransmission, the selected bits may include sufficient information bits such that the retransmission may be self-decodable.

Aspects of the disclosure introduced above are described below in the context of a wireless communications system. Examples of processes and signaling exchanges that support self-decodable redundancy versions for LDPC codes are then described. Aspects of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to self-decodable redundancy versions for LDPC codes.

<FIG> illustrates an example of a wireless communications system <NUM> that supports self-decodable redundancy versions for LDPC codes in accordance with various aspects of the present disclosure. The wireless communications system <NUM> includes base stations <NUM>, UEs <NUM>, and a core network <NUM>. In some examples, the wireless communications system <NUM> may be a Long Term Evolution (LTE) network, LTE-Advanced (LTE-A) network, or a New Radio (NR) network. In some cases, wireless communications system <NUM> may support enhanced broadband communications, ultra-reliable (i.e., mission critical) communications, low latency communications, and communications with low-cost and low-complexity devices.

Each base station <NUM> may provide communication coverage for a respective geographic coverage area <NUM>. Control information and data may be multiplexed on an uplink channel or downlink according to various techniques. Control information and data may be multiplexed on a downlink channel, for example, using time division multiplexing (TDM) techniques, frequency division multiplexing (FDM) techniques, or hybrid TDM-FDM techniques. In some examples, the control information transmitted during a transmission time interval (TTI) of a downlink channel may be distributed between different control regions in a cascaded manner (e.g., between a common control region and one or more UE-specific control regions).

A UE <NUM> may also be referred to as a mobile station, a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, a wireless communications device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. A UE <NUM> may be a cellular phone, a personal digital assistant (PDA), a wireless modem, a wireless communication device, a handheld device, a tablet computer, a laptop computer, a cordless phone, a personal electronic device, a handheld device, a personal computer, a wireless local loop (WLL) station, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a machine type communication (MTC) device, an appliance, an automobile, or the like.

The P-GW may provide internet protocol (IP) address allocation as well as other functions.

The core network <NUM> may provide user authentication, access authorization, tracking, IP connectivity, and other access, routing, or mobility functions. At least some of the network devices, such as base station <NUM> may include subcomponents such as an access network entity, which may be an example of an access node controller (ANC). Each access network entity may communicate with a number of UEs <NUM> through a number of other access network transmission entities, each of which may be an example of a smart radio head, or a transmission/reception point (TRP).

UEs <NUM> and base stations <NUM> supports retransmissions of data to increase the likelihood that data is received successfully. Hybrid automatic repeat request (HARQ) feedback is one technique of increasing the likelihood that data is received correctly over a communication link <NUM>.

Wireless communications system <NUM> supports the use of error-correcting codes for introducing redundancy in a codeword so that transmission errors may be detected and corrected. As discussed above, these error correcting codes may generally compensate for the intrinsic unreliability of information transfer over the air interface. LDPC codes are one type of error correcting codes which use an iterative coding system. Gallager codes are an example of "regular" LDPC codes. Regular LDPC codes are linear block codes in which most of the elements of its parity check matrix H are '<NUM>'. LDPC codes can be represented by bipartite graphs (often referred to as "Tanner graphs"). In a bipartite graph, a set of variable nodes corresponds to bits of a codeword (e.g., information bits or systematic bits), and a set of check nodes correspond to a set of parity-check constraints that define the code. Edges in the graph connect variable nodes to check nodes. Thus, the nodes of the graph are separated into two distinctive sets with edges connecting nodes of two different types - variable and check.

Graphs as used in LDPC coding may be characterized in a variety of manners. A lifted code is created by copying a bipartite base graph (G) (or a protograph), a number of times, Z. The number of times is referred to herein as the lifting, lifting size, or lifting size value. A variable node and a check node are considered "neighbors" if they are connected by an "edge" (i.e., the line connecting the variable node and the check node) in the graph. In addition, for each edge (e) of the bipartite base graph (G), a permutation (generally an integer value associated with the edge permutation that is represented by k and referred to as the lifting value) is applied to the Z copies of edge (e) to interconnect the Z copies of G. A bit sequence having a one-to-one association with the variable node sequence is a valid codeword if and only if, for each check node, the bits associated with all neighboring variable nodes sum to <NUM> modulo <NUM> (i.e., they include an even number of <NUM>'s). The resulting LDPC code may be quasi-cyclic (QC) if the permutations (liftings values) used are cyclic.

<FIG> illustrate graphical <NUM>-a and matrix representations <NUM>-b, respectively, of an example LDPC code in accordance with various aspects of the present disclosure. For example, <FIG> shows a bipartite graph <NUM>-a representing an example LDPC code. Bipartite graph <NUM>-a includes a set of five variable nodes <NUM> (represented by circles) connected to four check nodes <NUM> (represented by squares). Edges in bipartite graph <NUM>-a connect variable nodes <NUM> to check nodes <NUM> (the edges are represented by the lines connecting variable nodes <NUM> to check nodes <NUM>). Bipartite graph <NUM>-a consists of |V| = <NUM> variable nodes and |C| = <NUM> check nodes, connected by |E| = <NUM> edges.

Bipartite graph <NUM>-a may be represented by a simplified adjacency matrix, which may also be known as a parity check matrix (PCM). <FIG> shows a matrix representation <NUM>-b of bipartite graph <NUM>-a. Matrix representation <NUM>-b includes a PCM H and a codeword vector x, where x<NUM>-x<NUM> represent bits of the codeword x. H is used for determining whether a received signal was normally decoded. H has C rows corresponding to j check nodes and V columns corresponding to i variable nodes (i.e., a demodulated symbol), where the rows represent the equations and the columns represent the bits of the codeword. In <FIG>, matrix H has four rows and five columns corresponding to four check nodes and five variable nodes, respectively. If a j-th check node is connected to an i-th variable node by an edge (i.e., the two nodes are neighbors), then there is a <NUM> in the i-th column and in the j-th row of the parity check matrix H. That is, the intersection of an i-th row and a j-th column contains a "<NUM>" where an edge joins the corresponding vertices and a "<NUM>" where there is no edge. The codeword vector x represents a valid codeword if and only if Hx = <NUM>, for example, if for each constraint node, the bits neighboring the constraint, via their association with variable nodes, sum to <NUM> modulo <NUM> (i.e., they comprise an even number of <NUM>'s). Thus, if the codeword is received correctly, then Hx = <NUM> (mod <NUM>). When the product of a coded received signal and the PCM H becomes '<NUM>', this signifies that no error has occurred.

The number of demodulated symbols or variable nodes is the LDPC code length. The number of non-zero elements in a row (column) is defined as the row (column) weight d(c)d(v). The degree of a node refers to the number of edges connected to that node. For example, as shown in <FIG>, the variable node <NUM> has three degrees of connectivity, with edges connected to check nodes <NUM>, <NUM>, and <NUM>. Variable node <NUM> has three degrees of connectivity, with edges connected to check nodes <NUM>, <NUM>, and <NUM>. Variable node <NUM> has two degrees of connectivity, with edges connected to check nodes <NUM> and <NUM>. Variable node <NUM> has two degrees of connectivity, with edges connected to check nodes <NUM> and <NUM>. And variable node <NUM> has two degrees of connectivity, with edges connected to check nodes <NUM> and <NUM>. This feature is illustrated in the matrix H shown in <FIG> where the number of edges incident to a variable node <NUM> is equal to the number of <NUM>'s in the corresponding column and is called the variable node degree d(v). Similarly, the number of edges connected with a check node <NUM> is equal to the number of <NUM>'s in a corresponding row and is called the check node degree d(c). For example, as shown in <FIG>, the first column in the matrix H corresponds to the variable node <NUM> and the corresponding entries in the column (<NUM>, <NUM>, <NUM>, <NUM>) indicates the edge connections to the check nodes <NUM>, <NUM>, and <NUM>, while the <NUM> indicates that there is not an edge to check node <NUM>. The entries in the second, third, fourth, and fifth columns of H represent the edge connections of the variable nodes <NUM>, <NUM>, <NUM>, and <NUM>, respectively, to the check nodes.

A regular graph or a regular code is one for which all variable nodes have the same degree and all constraint nodes have the same degree. On the other hand, an irregular code has constraint nodes and/or variable nodes of differing degrees. For example, some variable nodes may be of degree <NUM>, others of degree <NUM>, and still others of degree <NUM>.

"Lifting" enables LDPC codes to be implemented using parallel encoding and/or decoding implementations while also reducing the complexity typically associated with large LDPC codes. Lifting helps enable efficient parallelization of LDPC decoders while still having a relatively compact description. In some cases, LDPC codes can be lifted by taking Z (size of the lift) copies of the base PCM and assigning random permutations (according to integer lifting values k) to each edge bundle to interconnect the Z copies and obtain the final PCM. The final PCM has a blocklength Z times the size of the base PCM. Typically, the permutation used is a cyclic permutation (e.g., using circulant matrices to obtain the final PCM). The final PCM can be represented by replacing the non-zero entries in the base PCM by integers up to the size Z - <NUM>. The integer represents the cyclic shift (by that integer value) associated to the lifted bundle of edges in the lifted code structure. These may be referred to as quasi-cyclic LDPC codes.

A cyclically lifted LDPC code can also be interpreted as a code over the ring of binary polynomials modulo xz + <NUM>. In this interpretation, a binary polynomial, (x) = b<NUM> + b<NUM>x + b<NUM>x<NUM> +. + bz-<NUM>xz-<NUM> may be associated to each variable node in the base graph. The binary vector (b<NUM>, b<NUM>, b<NUM>,. , bz-<NUM>) corresponds to the bits associated to Z corresponding variable nodes in the lifted graph, that is, Z copies of a single base variable node. A cyclic permutation by k (referred to as a lifting value associated to the edges in the graph) of the binary vector is achieved by multiplying the corresponding binary polynomial by xk where multiplication is taken modulo xz + <NUM>. A degree d parity check in the base graph can be interpreted as a linear constraint on the neighboring binary polynomials B<NUM>(x),. ,Bd(x), written as xk<NUM>B<NUM>(x) + xk<NUM>B<NUM>(x) +. + xkdBd(x) = 0xk<NUM>B<NUM>(x) + xk<NUM>B<NUM>(x) +. + xkdBd(x) = <NUM>, the values, k<NUM>,. ,kd are the cyclic lifting values associated to the corresponding edges.

This resulting equation is equivalent to the Z parity checks in the cyclically lifted Tanner graph corresponding to the single associated parity check in the base graph. Thus, the PCM for the lifted graph can be expressed using the matrix for the base graph in which <NUM> entries are replaced with monomials of the form xk and <NUM> entries are lifted as <NUM>, but now the <NUM> is interpreted as the <NUM> binary polynomial modulo xz + <NUM>. Such a matrix may be written by giving the value k in place of xk. In this case the <NUM> polynomial is sometimes represented as "-<NUM>" and sometimes as another character in order to distinguish it from x<NUM>.

Typically, a square submatrix of the parity check matrix represents the parity bits of the code. The complementary columns correspond to information bits that, at the time of encoding, are set equal to the information bits to be encoded. The encoding may be achieved by solving for the variables in the aforementioned square submatrix in order to satisfy the parity check equations. The parity check matrix H may be partitioned into two parts M and N where M is the square portion. Thus, encoding reduces to solving Mc = s = Nd where c and d comprise x. In the case of quasi-cyclic codes, or cyclically lifted codes, the above algebra can be interpreted as being over the ring of binary polynomials modulo xz + <NUM>.

A received LDPC codeword can be decoded to produce a reconstructed version of the original codeword. In the absence of errors, or in the case of correctable errors, decoding can be used to recover the original data unit that was encoded. Redundant bits may be used by decoders to detect and correct bit errors. LDPC decoders generally operate by iteratively performing local calculations and passing those results by exchanging messages within the bipartite graph along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. These steps may be repeated several times. For example, each variable node <NUM> in the graph <NUM>-a may initially be provided with a "soft bit" (e.g., representing the received bit of the codeword) that indicates an estimate of the associated bit's value as determined by observations from the communications channel. Using these soft bits the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to memory. The update operations are typically based on the parity check constraints of the corresponding LDPC code. In implementations for lifted LDPC codes, messages on like edges are often processed in parallel.

LDPC codes designed for high speed applications often use quasi-cyclic constructions with large lifting factors and relatively small base graphs to support high parallelism in encoding and decoding operations. LDPC codes with higher code rates (e.g., the ratio of the message length to the codeword length) tend to have relatively fewer parity checks. If the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node), then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges (e.g., the variable node may have a "double edge"). If the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node), then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges.

Having a base variable node and a base check node connected by two or more edges is generally undesirable for parallel hardware implementation purposes. For example, such double edges may result in multiple concurrent read and write operations to the same memory locations, which in turn may create data coherency problems. A double edge in a base LDPC code may trigger parallel reading of the same soft bit value memory location twice during a single parallel parity check update. Thus, additional circuitry is typically needed to combine the soft bit values that are written back to memory, so as to properly incorporate both updates. Eliminating double edges in the LDPC code helps to avoid this extra complexity.

<FIG> illustrates an example of a bipartite graph <NUM> showing liftings of three copies of the bipartite graph <NUM>-a of <FIG> in accordance with various aspects of the present disclosure. Three copies (comprising first copy with variable node <NUM> and check node <NUM>, second copy with variable node <NUM> ' and check node <NUM> ', and third copy with variable node <NUM>' ' and check node <NUM> ' ') may be interconnected by permuting like edges among the copies. If the permutations are restricted to cyclic permutations, then the resulting bipartite graph <NUM> corresponds to a quasi-cyclic LDPC with lifting Z = <NUM>. The original graph <NUM>-a from which three copies were made is referred to herein as the base graph. To obtain graphs of different sizes, a "copy and permute" operation can be applied to the base graph. A corresponding PCM of the lifted graph can be constructed from the PCM of the base graph by replacing each entry in the base PCM with a Z × Z matrix. The <NUM> entries (those having no base edges) are replaced with the <NUM> matrix and the <NUM> entries (indicating a base edge) are replaced with a Z × Z permutation matrix. In the case of cyclic liftings, the permutations are cyclic permutations. <FIG> illustrates an example of an integer representation of a PCM <NUM> in accordance with various aspects of the present disclosure. The sub-block <NUM> shown in <FIG> shows a shifted identity matrix for an entry in the base PCM.

<FIG> illustrates an example of a base PCM <NUM> in accordance with various aspects of the present disclosure. As shown in <FIG>, the example base PCM <NUM> has information (systematic) bit columns <NUM> (i.e., variable nodes) which include a "core" structure <NUM> of some number of degree <NUM> or higher variable nodes along with some state (punctured) nodes <NUM> that are of higher degree, which together form the set of information bit columns <NUM>. For simplicity of description, all of the systematic bit columns other than the high degree punctured state nodes are degree <NUM>, but the disclosed techniques are not so limited.

As shown in <FIG>, the base PCM <NUM> structure includes a parity structure <NUM>. The parity structure <NUM> includes an accumulate chain terminated by a degree <NUM> node (e.g., similar to the IEEE <NUM>. 11n standard LDPC code). Alternate encoding structures may be used, for example to support deeper error floors, and the disclosed techniques may be applied to such variations on the encoding structure. As shown in <FIG>, the base PCM <NUM> structure may also include one or more degree one parity bits <NUM>. The degree one parity bits <NUM> are connected via a check node only to the state nodes.

The bit columns <NUM> and parity structure <NUM> may be referred to as the "core graph" or "core PCM". As shown in <FIG>, the core graph can be extended using additional parity-bits for further incremental redundancy (IR)-HARQ transmissions (IR-HARQ extensions <NUM>) to define codes of a lower code rate than the rate associated to the core graph. The complete graph or some portion beyond the core graph may be referred to as an "extended graph". The core graph has an associated code rate determined by its parameters (i.e., variable nodes, check nodes, edges, puncturing, etc.). Some parity bits in the core graph can be punctured to support code rates above the code rate of the core graph. Lower coding rates may be obtained by extending the core graph with parity bits.

Shortening of the base graph and the lifted graph may be used to achieve the finer granularity in blocklength. The core graph may have a maximum number of information columns, denoted by kb,max. When the base code is shortened, one or more information bits are declared known (e.g., by setting the bit to <NUM>}and they are not used in the transmitted code. When a bit in the base graph is known, the entire corresponding column of Z bits in the lifted graph is declared known. The receiver may know a priori the bits that are fixed to <NUM> and can exploit that knowledge in the decoding process. In parallel decoding architectures an entire known column can be skipped in the decoding process, so the known column incurs no operations at the receiver, hence the coding system can operate as if the base graph were actually smaller. This may not typically apply to shortening that is less than an entire column.

A base graph structure that gives very good performance for shortening over some range is provided. The shortening of the base graph results in a range of supported information columns from a minimum value of kb,min up to a maximum value of kb,max. The structure of the shortening guarantees that at most one lifted column of information bits of the lifted graph will be partially shortened. All other information bit columns may be completely used or completely shortened (e.g., shortened at the base graph level). In addition to the information bits in the base graph, the base graph structure can support a number of parity bits in the range from a minimum of cb,min to a maximum of cb,max. The minimum may be less than the number of parity bits in the core graph (e.g., some parity bits may be punctured) to support higher transmission rates. The maximum number of parity bits (cb,max) corresponds to the maximum number of the parity bits in the extended graph and may be substantially larger than the number of parity bits in the core graph.

The base graph can be designed by a process of successive optimization to ensure that the base graphs for all supported shortenings yield good performance. An example optimized nested base graph <NUM> is illustrated in <FIG>. To obtain the optimized base graph <NUM>, a base graph with kb,min information bit columns <NUM> (for both the core and the extended base graph), including the state nodes <NUM> and core <NUM>, may be optimized. The total number of parity bits is equal to cb,max-cb,min and may be obtained by puncturing degree two parity bit columns in the core graph so that the base graph yields the desired highest possible coding rate. Once the base graph with kb,min information bit columns is obtained, a column <NUM> is added to optimize the base graph for performance over kb,min+<NUM> information bit columns. Adding of bit columns <NUM> to the base graph is repeated in an iterative process until an optimized base graph on kb,max information bit columns <NUM> is obtained.

<FIG> illustrates an example of an IR HARQ circular buffer <NUM> for the example LDPC code structure of <FIG> in accordance with various aspects of the present disclosure. In some cases, a wireless device may encode a set of information bits using a lifted LDPC code to generate an encoded bit stream, and the wireless device may store the encoded bit stream in the IR HARQ circular buffer <NUM>. To determine bits for an original transmission of the encoded bit stream (i.e., RV0 <NUM>), the wireless device may select a starting bit (e.g., a first systematic bit), and the wireless device may read a contiguous set of bits from the circular buffer for the original transmission. The wireless device may also read a contiguous set of bits from the circular buffer for a retransmission. In this example, the original transmission or retransmission may include the systematic bits and some portion of the parity bits stored in the circular buffer.

In addition to the original transmission, the wireless device is also scheduled for one or more retransmissions of the encoded bit stream (e.g., in response to a negative acknowledgement (NACK) received from a receiving device). Accordingly, the wireless device identifies a starting bit (e.g., a first bit subsequent to the last bit transmitted from the circular buffer in the original transmission), and the wireless device reads a contiguous set of bits following the starting bit from the circular buffer for a retransmission (e.g., RV1 <NUM>). In the example of <FIG>, the retransmission may include parity extension bits (Rmin). When a receiving device receives the retransmission, the receiving device may combine the retransmission with the original transmission in the decoding process to identify the information bits in the original transmission. The wireless device may gather a contiguous set of encoded bits and re-order the bits. The wireless device then writes the re-ordered set of bits to a second circular buffer. Upon retransmission, the wireless device transmits the re-ordered set of bits from the second circular buffer. The re-ordered set of bits is read and transmitted contiguously from the second circular buffer. The wireless device selects a starting bit for reading a contiguous set of bits from the second circular buffer. The wireless device may select the starting bit based on a redundancy version of the information bits.

In some examples, the wireless device may read a contiguous set of bits following the starting bit from the circular buffer for a retransmission. The wireless device may re-order the bits upon reading the bits from the circular buffer. Upon retransmission, the wireless device may then transmit the re-ordered bits contiguously. In some examples, the wireless device may re-order the bits upon reading the bits from the circular buffer. The wireless device may thus select bits non-contiguously from the ordered bits stored in the buffer, with the selected non-contiguous bits thus forming a re-ordered set of bits. Upon retransmission, the wireless device may then transmit the selected non-contiguous bits.

In some cases, however, the receiving device may fail to receive the original transmission of the encoded bit stream. As such, if the receiving device receives the retransmission including the parity extension bits, the receiving device may not be able to independently decode these bits. That is, since a retransmission may not include any systematic bits (or only a small number of systematic bits), the retransmission may not be self-decodable, and the retransmission may fail to decode successfully if an original transmission of the encoded bit stream was subject to high interference or was not received at all. As a result, the wireless device may experience reduced throughput and resources used for the retransmission may be wasted.

The techniques described herein allow a wireless device to generate self-decodable retransmissions such that a receiving device may be able to decode the retransmission and identify some information bits even when the receiving device fails to receive an original transmission of the information bits. In the embodiments of the claimed invention, the wireless device supports techniques for re-ordering bits of an encoded bit stream before storing these bits in a circular buffer for a retransmission such that the retransmission includes at least some information bits and is self-decodable. The transmitting device does not re-order bits prior to an original transmission because the original transmission may already be associated with a high coding gain and low complexity.

<FIG> illustrates an example of a transmit chain <NUM> in which re-ordering is performed prior to storing bits in a circular buffer for retransmissions in accordance with various aspects of the present disclosure. Although not shown in <FIG>, prior to encoding, a transmitting device may segment a set of information bits (e.g., corresponding to a transport block) into a number of segments. The transmitting device may then encode each of the segments separately. As shown in <FIG>, the transmitting device uses the information bits to be transmitted and the selected lifting size value Z to generate a lifted graph (e.g., referred to as the mother code) which is input to the encoder to encode the information bits at block <NUM>. The encoded bits can be input to the puncturing module which can puncture systematic bits associated with filler state nodes (e.g., according to puncturing pattern) and output a punctured bit stream at block <NUM>.

After performing the operations described above, at block <NUM> the transmitting device performs a fixed re-ordering of the punctured bit stream for one or more retransmissions such that the retransmissions is self-decodable. According to the claimed invention, re-ordering is performed prior to storing the coded bits in a circular buffer to be used to select bits for the retransmission. By re-ordering the bits (e.g., based on a fixed algorithm) before storing the bits in the circular buffer, the transmitting device evenly distributes information bits across the circular buffer. Accordingly, when the transmitting device selects a contiguous set of bits from the circular buffer for a retransmission, the selected bits includes a number of systematic bits such that the retransmission is self-decodable. In some cases, the use of these techniques for generating self-decodable retransmissions may result in a minimal loss to the HARQ gain associated with the retransmissions.

Once the bits in the punctured bit stream are re-ordered and stored in the circular buffer, at block <NUM> the transmitting device selects bits from the circular buffer to be retransmitted. The transmitting device selects a starting bit in the circular buffer, and the transmitting device reads a contiguous set of bits from the circular buffer for the retransmission based on a redundancy version associated with the retransmission. Since the re-ordering interleaves systematic bits and parity bits in the circular buffer, when the transmitting device reads sets of contiguous bits from the buffer for a retransmission, the retransmission each contains both systematic and parity bits and, thus, is self-decodable.

<FIG> illustrates an example of re-ordering techniques <NUM> that support self-decodable redundancy versions for LDPC codes in accordance with various aspects of the present disclosure. In this example, a transmitting device may generate a matrix of bits that includes bits in the encoded bit stream by allocating bits of the encoded bit stream to a number of rows and columns, where an equal number of bits may be allocated to each row and each column and the bits may be inserted by order of increasing column and then increasing row. In the example of <FIG>, each of the rows of the matrix may include Z bits. In other examples, however, each of the rows of the matrix may include any number of bits (e.g., greater than one) such that each row includes the same number of bits. That is, the number of bits in each row may be determined based on a factor of the number of bits in the encoded bit stream (N).

Once the matrix is generated, the transmitting device may perform a random circular shift on bits in each of the rows to randomize the bits to be included in the retransmission (as shown in <NUM>). In the case that a number of filler bits are punctured (e.g., from a shortening procedure), the transmitting device may account for the punctured bits. Alternatively, this step may be part of the encoder graph stage in transmit chain <NUM>.

The transmitting device may then select bits <NUM> to be stored in a circular buffer in order of increasing row index followed by increasing column index. Because the systematic bits are generally found in a first subset of rows of the matrix, the bits stored in the circular buffer may include interleaved systematic and parity bits when selected first by increasing row index. As such, when the transmitting device selects a contiguous set of stored bits from the circular buffer for the retransmission, the selected bits may include sufficient systematic bits such that the retransmission is self-decodable.

Although this example is described as inserting bits into the matrix first by column and then by row and performing a random circular shift on bits in each of the rows, it should be understood that the transmitting device may insert bits into the matrix first by row and then by column and perform this random circular shift on bits in each of the columns (or any other dimension). In this case, the transmitting device may select bits to be stored in the circular buffer in order of increasing column index followed by increasing row index. In other words, the transmitting device may interleave sets of systematic bits and sets of parity bits for retransmissions, and the transmitting device may store the interleaved bits in the circular buffer. Further, although the above examples describe two different buffers for storing the encoded bit stream for an original transmission and storing the re-ordered encoded bit stream for retransmissions, it should be understood that the transmitting device may perform the operations using a single circular buffer. For example, the transmitting device may first store the encoded bit stream in a circular buffer for an original transmission, and then re-order the bits in the circular buffer for retransmissions (e.g., overwriting the original bit order). Although described as a random circular shift, it should be understood that the circular shift may be given by a pseudo-random function such that both the encoder and decoder can determine the circular shift pattern based on known information.

In some examples, alternative interleaving techniques may be used for the re-ordering of the circular buffer for retransmissions. For example, a structured interleaving may be used that maintains a proportion of systematic bits to parity bits within a given window size over the circular buffer size, where the window size may be less than a bit length for transmissions or retransmissions. The structured interleaving thus ensures that retransmissions for each redundancy version are self-decodable. In other examples, a random (e.g., pseudo-random) bit-level interleaving may be used. Random interleaving, especially at lower code rates, may generally approach the results of structured interleaving. However, random interleaving is typically more computationally complex than structured interleaving.

Additionally or alternatively, a transmitting device may be configured to restrict a mother code rate to improve the self-decodability of retransmissions. As discussed above, the mother code may correspond to the lifting graph which may be input to an encoder to encode information bits. The mother code rate may correspond to the code rate of an encoded bit stream generated by the transmitting device. In some aspects, the transmitting device may restrict the mother code rate to code rates higher than the lowest code rate allowable (e.g., the lowest code rate that can be achieved from the base graph (e.g., <NUM>/<NUM>)). As such, the number of systematic bits may be higher in an encoded bit stream which may be stored in a circular buffer.

In such aspects, when the transmitting device selects a contiguous set of bits from the circular buffer to be retransmitted, the retransmission may include more systematic bits than would be included if a lower code rate was used to generate the encoded bit stream. Since the retransmission may include more systematic bits, the self-decodability of the retransmission may be improved. In addition, the restriction of the mother code rate to higher code rates may improve computational complexity and buffer management (e.g., since there may be less parity bits). In some cases, in order to limit the complexity of decoding original transmissions and retransmissions, the mother code rate may be restricted for both original transmissions and retransmissions. In some examples, a first mother code rate (e.g., <NUM>/<NUM>) may be used (e.g., assumed), except at higher peak rates where a different mother code rate (e.g., <NUM>/<NUM>) may be used.

<FIG> shows a block diagram <NUM> of a wireless device <NUM> that supports self-decodable redundancy versions for LDPC codes in accordance with various aspects of the present disclosure. Wireless device <NUM> may be an example of aspects of a UE <NUM> or base station <NUM> as described herein. Wireless device <NUM> may include receiver <NUM>, communications manager <NUM>, and transmitter <NUM>. Wireless device <NUM> may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses).

Receiver <NUM> may receive information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, and information related to self-decodable redundancy versions for LDPC codes, etc.). Information may be passed on to other components of the device. The receiver <NUM> may be an example of aspects of the transceiver <NUM> described with reference to <FIG>. The receiver <NUM> may utilize a single antenna or a set of antennas.

Communications manager <NUM> may be an example of aspects of the communications manager <NUM> described with reference to <FIG>. Communications manager <NUM> and/or at least some of its various sub-components may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of the communications manager <NUM> and/or at least some of its various sub-components may be executed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure.

The communications manager <NUM> and/or at least some of its various sub-components may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations by one or more physical devices. In some examples, communications manager <NUM> and/or at least some of its various sub-components may be a separate and distinct component in accordance with various aspects of the present disclosure. In other examples, communications manager <NUM> and/or at least some of its various sub-components may be combined with one or more other hardware components, including but not limited to an I/O component, a transceiver, a network server, another computing device, one or more other components described in the present disclosure, or a combination thereof in accordance with various aspects of the present disclosure.

Communications manager <NUM> may encode a set of information bits using a lifted LDPC code for a lifting size value Z from a base graph, the lifted LDPC code having a set of variable nodes corresponding to one or more information bits and parity bits and a set of check nodes, to generate an encoded bit stream. Communications manager <NUM> may then coordinate with transmitter <NUM> to transmit a redundancy version corresponding to the set of information bits, the redundancy version either comprising a contiguous set of bits from a circular buffer storing the encoded bit stream or a re-ordered set of bits from the encoded bit stream. In some cases, communications manager <NUM> may coordinate with transmitter <NUM> to transmit selected bits from the second circular buffer in a retransmission.

Transmitter <NUM> may transmit a contiguous set of bits from the second circular buffer.

<FIG> shows a block diagram <NUM> of a communications manager <NUM> that supports self-decodable redundancy versions for LDPC codes in accordance with various aspects of the present disclosure. The communications manager <NUM> may be an example of aspects of a communications manager <NUM>, a communications manager <NUM>, or a communications manager <NUM> described with reference to <FIG>, <FIG>, and <FIG>. The communications manager <NUM> may include encoder <NUM>, bit selector <NUM>, circular buffer manager <NUM>, bit re-ordering manager <NUM>, bit matrix generator <NUM>, circular shift manager <NUM>, and bit interleaver <NUM>. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses).

Encoder <NUM> may encode a set of information bits using a lifted LDPC code for a lifting size value Z from a base graph, the lifted LDPC code having a set of variable nodes corresponding to one or more information bits and parity bits and a set of check nodes, to generate an encoded bit stream. In some cases, the lifted LDPC code may be restricted to a lifted LDPC code corresponding to a code rate higher than a lowest code rate associated with the base graph. In some cases, the lowest code rate associated with the base graph includes a mother code. In some cases, encoder <NUM> may restrict a size of the mother code for an original transmission and for retransmissions of the set of information bits.

Bit re-ordering manager <NUM> may re-order bits in the encoded bit stream to create the re-ordered set of bits. In some cases, the re-ordering is a structured re-ordering that ensures that retransmissions are self-decodable for all redundancy versions. In some cases, the re-ordering of the bits in the encoded bit stream is a random re-ordering. Bit re-ordering manager <NUM> may re-order the stored bits upon selection. In some cases, the re-ordered set of bits comprises the re-ordered stored bits. Bit re-ordering manager <NUM> may re-order stored bits from the circular buffer for a retransmission based at least in part on the redundancy version. Bit re-ordering manager <NUM> may also re-order bits in the encoded bit stream for a retransmission based at least in part on a code rate of the encoded bit stream.

Bit selector <NUM> may selecting between the contiguous set of bits and the re-ordered set of bits. In some cases, the transmitting is based at least in part on the selection. Bit selector <NUM> may select a starting bit for reading the contiguous set of bits from the second circular buffer based at least in part on the redundancy version. selecting stored bits from the circular buffer for a retransmission based at least in part on the redundancy version. Bit selector <NUM> may select bits by reading ordered stored bits non-contiguously from the circular buffer. In some cases, the re-ordered set of bits comprises the selected bits. Bit selector <NUM> may select bits in order of increasing row index followed by increasing column index.

Circular buffer manager <NUM> may writing the re-ordered set of bits to a second circular buffer. Circular buffer manager <NUM> may store the selected bits. Bit matrix generator <NUM> may generate a matrix of bits by allocating bits of the encoded bit stream to a set of rows and columns, where a first equal number of bits is allocated to each row and a second equal number of bits is allocated to each column. In some cases, each row includes Z bits. Circular shift manager <NUM> may perform a random circular shift on bits in each row of the set of rows. Bit interleaver <NUM> may select bits to be stored in the second circular buffer in order of increasing row index followed by increasing column index.

<FIG> shows a diagram of a system <NUM> including a device <NUM> that supports self-decodable redundancy versions for LDPC codes in accordance with various aspects of the present disclosure. Device <NUM> may be an example of or include the components of wireless device <NUM> or a UE <NUM> as described above, e.g., with reference to <FIG>. Device <NUM> may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including UE communications manager <NUM>, processor <NUM>, memory <NUM>, software <NUM>, transceiver <NUM>, antenna <NUM>, and I/O controller <NUM>. These components may be in electronic communication via one or more buses (e.g., bus <NUM>). Device <NUM> may communicate wirelessly with one or more base stations <NUM>.

Processor <NUM> may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor <NUM> may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor <NUM>. Processor <NUM> may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting self-decodable redundancy versions for LDPC codes).

Software <NUM> may include code to implement aspects of the present disclosure, including code to support self-decodable redundancy versions for LDPC codes. Software <NUM> may be stored in a non-transitory computer-readable medium such as system memory or other memory. In some cases, the software <NUM> may not be directly executable by the processor but may cause a computer (e.g., when compiled and executed) to perform functions described herein.

<FIG> shows a diagram of a system <NUM> including a device <NUM> that supports self-decodable redundancy versions for LDPC codes in accordance with various aspects of the present disclosure. Device <NUM> may be an example of or include the components of wireless device <NUM> or a base station <NUM> as described above, e.g., with reference to <FIG>. Device <NUM> may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including base station communications manager <NUM>, processor <NUM>, memory <NUM>, software <NUM>, transceiver <NUM>, antenna <NUM>, network communications manager <NUM>, and inter-station communications manager <NUM>. These components may be in electronic communication via one or more buses (e.g., bus <NUM>). Device <NUM> may communicate wirelessly with one or more UEs <NUM>.

Processor <NUM> may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor <NUM> may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor <NUM>. Processor <NUM> may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting self-decodable redundancy versions for LDPC codes).

Software <NUM> may include code to implement aspects of the present disclosure, including code to support self-decodable redundancy versions for LDPC codes. Software <NUM> may be stored in a non-transitory computer-readable medium such as system memory or other memory. In some cases, the software <NUM> may not be directly executable by the processor but may cause a computer (e.g., when compiled and executed) to perform functions described herein.

Inter-station communications manager <NUM> may manage communications with other base station <NUM>, and may include a controller or scheduler for controlling communications with UEs <NUM> in cooperation with other base stations <NUM>. In some examples, inter-station communications manager <NUM> may provide an X2 interface within an LTE/LTE-A wireless communication network technology to provide communication between base stations <NUM>.

<FIG> shows a flowchart illustrating a method <NUM> for self-decodable redundancy versions for LDPC codes in accordance with various aspects of the present disclosure. The operations of method <NUM> may be implemented by a UE <NUM> or base station <NUM> or its components as described herein. For example, the operations of method <NUM> may be performed by a communications manager as described with reference to <FIG>. In some examples, a UE <NUM> or base station <NUM> may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the UE <NUM> or base station <NUM> may perform aspects of the functions described below using special-purpose hardware.

At block <NUM> the UE <NUM> or base station <NUM> may encode a set of information bits using a lifted LDPC code for a lifting size value Z from a base graph, the lifted LDPC code having a plurality of variable nodes corresponding to one or more information bits and parity bits and a plurality of check nodes, to generate an encoded bit stream. The operations of block <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of block <NUM> may be performed by a encoder as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may transmit a redundancy version corresponding to the set of information bits, the redundancy version either comprising a contiguous set of bits from a circular buffer storing the encoded bit stream or a re-ordered set of bits from the encoded bit stream. The operations of block <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of block <NUM> may be performed by a transmitter as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may re-order bits in the encoded bit stream. The operations of block <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of block <NUM> may be performed by a bit re-ordering manager as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may write the re-ordered set of bits to a second circular buffer. The operations of block <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of block <NUM> may be performed by a circular buffer manager as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may transmit a contiguous set of bits from the second circular buffer. The operations of block <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of block <NUM> may be performed by a transmitter as described with reference to <FIG>.

Claim 1:
A method for wireless communication comprising an original transmission of bits of an encoded bit stream and a retransmission of bits of the encoded bit stream, the method comprising:
encoding (<NUM>; <NUM>) a set of information bits using a lifted quasi-cyclic low-density parity-check, LDPC, code obtained from a base graph using a lifting size value Z, the lifted LDPC code having a plurality of variable nodes corresponding to one or more information bits and parity bits and a plurality of check nodes, to generate the encoded bit stream;
storing the encoded bit stream in a first circular buffer;
re-ordering (<NUM>; <NUM>) bits in the encoded bit stream to create a re-ordered set of bits;
storing the re-ordered set of bits in a second circular buffer, wherein
information bits are evenly distributed across the second circular buffer; and
transmitting (<NUM>; <NUM>) a redundancy version, RV, corresponding to the set of information bits, the RV either comprising a contiguous set of bits from the first circular buffer for the original transmission or a contiguous set of bits from the second circular buffer for the retransmission, wherein the RV for the retransmission comprises sufficient information bits that the RV can be decoded without the original transmission.