Patent Description:
A FET, e.g., a metal-oxide-semiconductor (MOS) FET (MOSFET), is a three-terminal device that includes source, drain, and gate terminals and uses electric field to control current flowing through the device. A FET typically includes a channel body of a semiconductor channel material, a source and a drain regions provided in the channel material, and a gate stack that includes at least a gate electrode material and may also include a gate dielectric material, the gate stack provided over a portion of the channel material between the source and the drain regions.

Recently, FETs with non-planar architectures, such as FinFETs (also sometimes referred to as "wrap-around gate transistors" or "tri-gate transistors") and nanoribbon/nanowire transistors (also sometimes referred to as "all-around gate transistors"), have been extensively explored as alternatives to transistors with planar architectures.

Introducing germanium into a silicon channel body to create a silicon germanium channel body may increase mobility of charge carriers in transistor devices and allow fabrication of P-type MOS (PMOS) transistors. However, fabricating complementary MOS (CMOS) integrated circuit (IC) devices having both silicon channel N-type MOS (NMOS) transistors and silicon germanium channel PMOS transistors in non-planar architectures on the same substrate, e.g., on the same bulk silicon substrate, is challenging.

<CIT> discloses a semiconductor structure including a portion of a substrate having a first well region and a second well region, an isolation region, a first fin and a second fin. The first fin may include a center region and a peripheral region surrounding the center region. The peripheral region of the first fin may include silicon germanium and the center region includes silicon and may be free of germanium.

<CIT> discloses a FinFET comprising a gate dielectric layer, and a gate electrode. A fin is formed by a semiconductor layer with a low germanium concentration. Further, the fin comprises germanium-rich layers formed in a second portion of the fin. As such, edge regions of the first portions and second portions of the fins have a higher germanium concentration than center regions of the first portions and second portions of the fins.

<CIT> discloses a CMOS device comprising a transistor of a first type on a first region on a first region and a transistor of a complementary type on a second region of substrate. A cladding is formed of a semiconductor having a narrower band gap than the semiconductor body. The substrate is comprised of a silicon semiconductor substrate having an undoped, or intrinsic epitaxial silicon region. A semiconductor film is ideally a silicon film.

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

For purposes of illustrating IC structures that include non-planar SiGe transistors fabricated using silicon replacement, proposed herein, it might be useful to first understand phenomena that may come into play in such devices. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications. While some of the following descriptions may be provided for the example of transistors being implemented as FinFETs or nanoribbon transistors, embodiments of the present disclosure are equally applicable to transistor arrangements employing transistors of other nanowire architectures, such as nanowire or nanocomb transistors.

As described above, recently, FETs with non-planar architectures, such as FinFETs and nanoribbon transistors, have been extensively explored as alternatives to transistors with planar architectures.

In a FinFET, a semiconductor structure shaped as a fin extends away from a base (e.g., from a semiconductor substrate), and a gate stack wraps around the upper portion of the fin (i.e., the portion farthest away from the base), potentially forming a gate on <NUM> sides of the fin. The portion of the fin around which the gate stack wraps around is referred to as a "channel" or a "channel portion" of a FinFET. A semiconductor material of the channel portion is commonly referred to as a "channel material" of the transistor. A source region and a drain region are provided in the fin on the opposite sides of the gate stack, forming, respectively, a source and a drain of a FinFET.

In a nanoribbon transistor, a gate stack may be provided around a portion of an elongated semiconductor structure called "nanoribbon", potentially forming a gate on all sides of the nanoribbon. The "channel" or the "channel portion" of a nanoribbon transistor is the portion of the nanoribbon around which the gate stack wraps around. A source region and a drain region are provided in the nanoribbon on each side of the gate stack, forming, respectively, a source and a drain of a nanoribbon transistor. In some settings, the term "nanoribbon" has been used to describe an elongated semiconductor structure that has a rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" has been used to describe a similar structure but with a circular transverse cross-section. The term "nanocomb transistor" has been used to describe a transistor similar to a nanoribbon transistor in that it uses a nanoribbon as described above, but with the gate stack provided only on <NUM> of the <NUM> sides of the nanoribbon, potentially forming a gate on <NUM> sides of the nanoribbon. In the following, a term "nanoribbon-based transistor" is used to refer to any of a nanoribbon transistor, a nanowire transistor, a nanocomb transistor, or a transistor such as a nanoribbon, nanowire, or nanocomb transistor but having transverse cross-sections of any geometry (e.g., oval, or a polygon with rounded corners).

Fabricating CMOS devices having both non-planar silicon (Si) channel NMOS transistors (referred to herein as "Si transistors") and non-planar SiGe channel PMOS transistors (referred to herein as "SiGe transistors") on the same substrate, e.g., on the same bulk silicon substrate, is challenging. Taking nanoribbon transistors as an example, oftentimes, fabrication of a CMOS device having both Si channel nanoribbon transistors and SiGe channel nanoribbon transistors requires using different substrates for fabricating Si channel and SiGe channel transistors. Other times, it requires using differential stacks for NMOS transistors (i.e., the Si transistors) and PMOS transistors (i.e., the SiGe transistors). Often these differential stacks require different starting substrates and different epitaxial processes used to form them, increasing design complexity and fabrication costs. In addition, Si channel and SiGe channel nanoribbons formed using conventional techniques typically result in different heights of the nanoribbons for NMOS and PMOS transistors, leading to further challenges, e.g., in terms of encapsulation, etching, metallization, or packaging of such structures.

Described herein are IC structures/devices with non-planar SiGe transistors fabricated using silicon replacement. In general, silicon replacement as described herein, a process that may also be referred to as a "silicon replacement condensation technique," refers to providing, over a support structure (e.g., a substrate, a wafer, a chip, or a die), a channel body for a non-planar transistor, the channel body including silicon, providing a cladding layer that includes germanium (e.g., the cladding layer may take form of a Ge-rich SiGe material) over at least a portion of the channel body, and annealing the channel body so that at least some of the germanium of the cladding layer diffuses into the channel body. In context of the present disclosure, the channel body is a fin if the transistor is a FinFET transistor, and is a nanoribbon or a nanowire if the transistor is a nanoribbon-based transistor (i.e., a nanoribbon transistor, a nanowire transistor, or a nanocomb transistor). Following silicon replacement, the cladding layer (which may have become substantially oxide as a result of the anneal) may be removed. Fabricating non-planar SiGe transistors using silicon replacement advantageously allows forming IC structures with both silicon and SiGe transistors on a single support structure in a manner that is less complicated and costly compared to prior art implementations.

While some descriptions are provided herein with reference to nanoribbon transistors, these descriptions are equally applicable to embodiments of any nanoribbon-based transistors such as nanowire transistors, nanocomb transistors, or other non-planar FETs besides FinFETs, e.g., to nanoribbon transistors, nanowire transistors, or transistors such as nanoribbon, nanowire, or nanocomb transistors but having transverse cross-sections of any geometry (e.g., oval, or a polygon with rounded corners).

Each of the structures, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, no single one of which being solely responsible for the all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, some descriptions may refer to a particular source (S) or drain (D) region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because under certain operating conditions, designations of source and drain are often interchangeable. Therefore, descriptions provided herein may use the term of a "S/D region/contact" to indicate that the region/contact can be either a source region/contact, or a drain region/contact. In another example, the term "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide, while the term "low-k dielectric" refers to a material having a lower k than silicon oxide. If used, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between the elements, generally refer to being within +/- <NUM>-<NUM>% of a target value based on the context of a particular value as described herein or as known in the art.

In the present disclosure, the term "connected" may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term "coupled" may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

The description may use the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g., <FIG>, such a collection may be referred to herein without the letters, e.g., as "<FIG>.

In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so "ideal" when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

Various transistor arrangements and IC structures with one or more non-planar SiGe transistors fabricated using silicon replacement as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

<FIG> is a perspective view of an example FinFET <NUM>, according to some embodiments of the disclosure. The FinFET <NUM> illustrates an example structure for a non-planar SiGe transistor fabricated using silicon replacement as described herein. For example a plurality of fins with transistors such as the FinFETs <NUM> may be used to provide an IC structure having silicon FinFETs and silicon germanium FinFETs integrated over a single support structure using silicon replacement, as described with reference to <FIG>, <FIG>, and <FIG>. The FinFET <NUM> shown in <FIG> is intended to show relative arrangement(s) of some of the components therein. In various embodiments, the FinFET <NUM>, or portions thereof, may include other components that are not illustrated (e.g., any further materials, such as e.g. spacer materials, surrounding the gate stack of the FinFET <NUM>, electrical contacts to the S/D regions of the FinFET <NUM>, etc.).

As shown in <FIG>, the FinFET <NUM> may be provided over a base <NUM>, where the term "base" may refer to any suitable support structure on which a transistor may be built, e.g., a substrate, a die, a wafer, or a chip. As also shown in <FIG>, the FinFET <NUM> may include a fin <NUM>, extending away from the base <NUM>. A portion of the fin <NUM> that is closest to the base <NUM> may be enclosed by an insulator material <NUM>, commonly referred to as a "shallow trench isolation" (STI). The portion of the fin <NUM> enclosed on its' sides by the STI <NUM> is typically referred to as a "subfin portion" or simply a "subfin. " As further shown in <FIG>, a gate stack <NUM> that includes at least a layer of a gate electrode material <NUM> and, optionally, a layer of a gate dielectric <NUM>, may be provided over the top and sides of the remaining upper portion of the fin <NUM> (e.g., the portion above and not enclosed by the STI <NUM>), thus wrapping around the upper-most portion of the fin <NUM>. The portion of the fin <NUM> over which the gate stack <NUM> wraps around may be referred to as a "channel portion" of the fin <NUM> because this is where, during operation of the FinFET <NUM>, a conductive channel may form. The channel portion of the fin <NUM> is a part of an active region of the fin <NUM>. A first S/D region <NUM>-<NUM> and a second S/D region <NUM>-<NUM> (also commonly referred to as "diffusion regions") are provided on the opposite sides of the gate stack <NUM>, forming source and drain terminals of the FinFET <NUM>.

In general, implementations of the present disclosure may be formed or carried out on a support structure such as a semiconductor substrate, composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which one or more non-planar SiGe transistors fabricated using silicon replacement as described herein may be built falls within the spirit and scope of the present disclosure. In various embodiments, the base <NUM> may include any such substrate material that provides a suitable surface for forming the FinFET <NUM>.

As shown in <FIG>, the fin <NUM> may extend away from the base <NUM> and may be substantially perpendicular to the base <NUM>. The fin <NUM> may include one or more semiconductor materials, e.g. a stack of semiconductor materials, so that the upper-most portion of the fin (namely, the portion of the fin <NUM> enclosed by the gate stack <NUM>) may serve as the channel region of the FinFET <NUM>. Therefore, as used herein, the term "channel material" of a transistor may refer to such upper-most portion of the fin <NUM>, or, more generally, to any portion of one or more semiconductor materials in which a conductive channel between source and drain regions may be formed during operation of a transistor.

As shown in <FIG>, the STI material <NUM> may enclose the sides of the fin <NUM>. A portion of the fin <NUM> enclosed by the STI <NUM> forms a subfin. In various embodiments, the STI material <NUM> may be a low-k or high-k dielectric including, but not limited to, elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Further examples of dielectric materials that may be used in the STI material <NUM> may include, but are not limited to silicon nitride, silicon oxide, silicon dioxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

Above the subfin portion of the fin <NUM>, the gate stack <NUM> may wrap around the fin <NUM> as shown in <FIG>. In particular, the gate dielectric <NUM> may wrap around the upper-most portion of the fin <NUM>, and the gate electrode <NUM> may wrap around the gate dielectric <NUM>. The interface between the channel portion of the fin <NUM> and the subfin portion of the fin <NUM> is located proximate to where the gate electrode <NUM> ends.

The gate electrode <NUM> may include one or more gate electrode materials, where the choice of the gate electrode materials may depend on whether the FinFET <NUM> is a PMOS transistor or an NMOS transistor. For a PMOS transistor, gate electrode materials that may be used in different portions of the gate electrode <NUM> may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, gate electrode materials that may be used in different portions of the gate electrode <NUM> include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode <NUM> may include a stack of a plurality of gate electrode materials, where zero or more materials of the stack are workfunction (WF) materials and at least one material of the stack is a fill metal layer. Further materials/layers may be included next to the gate electrode <NUM> for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.

If used, the gate dielectric <NUM> may include a stack of one or more gate dielectric materials. In some embodiments, the gate dielectric <NUM> may include one or more high-k dielectric materials. In various embodiments, the high-k dielectric materials of the gate dielectric <NUM> may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric <NUM> may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric <NUM> during manufacture of the FinFET <NUM> to improve the quality of the gate dielectric <NUM>.

In some embodiments, the gate stack <NUM> may be surrounded by a dielectric spacer, not specifically shown in <FIG>. The dielectric spacer may be configured to provide separation between the gate stacks <NUM> of different FinFETs <NUM> which may be provided along a single fin (e.g., different FinFETs provided along the fin <NUM>, although <FIG> only illustrates one of such FinFETs), as well as between the gate stack <NUM> and the source/drain contacts disposed on each side of the gate stack <NUM>. Such a dielectric spacer may include one or more low-k dielectric materials. Examples of the low-k dielectric materials that may be used as the dielectric spacer include, but are not limited to, silicon dioxide, carbon-doped oxide, silicon nitride, fused silica glass (FSG), and organosilicates such as silsesquioxane, siloxane, and organosilicate glass. Other examples of low-k dielectric materials that may be used as the dielectric spacer include organic polymers such as polyimide, polynorbornenes, benzocyclobutene, perfluorocyclobutane, or polytetrafluoroethylene (PTFE). Still other examples of low-k dielectric materials that may be used as the dielectric spacer include silicon-based polymeric dielectrics such as hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ). Other examples of low-k materials that may be used in a dielectric spacer include various porous dielectric materials, such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly <NUM>. When such a dielectric spacer is used, then the lower portions of the fin <NUM>, e.g., the subfin portion of the fin <NUM>, may be surrounded by the STI material <NUM> which may, e.g., include any of the high-k dielectric materials described herein.

In various embodiments, the fin <NUM> may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the fin <NUM> may include a combination of semiconductor materials where one semiconductor material is used for the channel portion and another material, sometimes referred to as a "blocking material," is used for at least a portion of the subfin portion of the fin <NUM>. For example, the subfin of the fin <NUM> may be a material having a band offset (e.g., valance band offset for PMOS transistors or conduction band offset for NMOS devices) from the channel portion. In some embodiments, the channel portion of the fin <NUM> may be an intrinsic semiconductor material, i.e., a semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel portion of the fin <NUM>, for example to further fine-tune a threshold voltage (Vt), to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion of the fin <NUM> may be relatively low, for example below <NUM><NUM> dopant atoms per cubic centimeter (cm-<NUM>), and advantageously below <NUM><NUM> cm-<NUM>. When the FinFET <NUM> is an NMOS transistor, the channel portion of the fin <NUM> may advantageously include silicon, e.g., a monocrystalline Si. When the FinFET <NUM> is a PMOS transistor, the channel portion of the fin <NUM> may advantageously include a semiconductor material that includes silicon and germanium, e.g., Si<NUM>-xGex, where Ge content (x) may be at least about <NUM>, e.g., between about <NUM> and <NUM>. In other example embodiments, the channel portion of the fin <NUM> may have a Ge content between about <NUM> and <NUM>, e.g., at least about <NUM>. In some P-type transistor embodiments, the subfin of the fin <NUM> may be Si and at least a portion of the subfin may also be doped with impurities (e.g., N-type) to a higher impurity level than the channel portion. The fin SiGe to subfin Si interface may induce a compressive strain on the SiGe fin portion, enhancing hole mobility in the PMOS transistor.

Turning to the first S/D region <NUM>-<NUM> and the second S/D region <NUM>-<NUM> on respective different sides of the gate stack <NUM>, in some embodiments, the first S/D region <NUM>-<NUM> may be a source region and the second S/D region <NUM>-<NUM> may be a drain region. In other embodiments this designation of source and drain may be interchanged, i.e., the first S/D region <NUM>-<NUM> may be a drain region and the second S/D region <NUM>-<NUM> may be a source region. Although not specifically shown in <FIG>, the FinFET <NUM> may further include S/D electrodes (also commonly referred to as "S/D contacts"), formed of one or more electrically conductive materials, for providing electrical connectivity to the S/D regions <NUM>, respectively. In some embodiments, the S/D regions <NUM> of the FinFET <NUM> may be regions of doped semiconductors, e.g., regions of doped channel material of the fin <NUM>, so as to supply charge carriers for the transistor channel. In some embodiments, the S/D regions <NUM> may be highly doped, e.g. with dopant concentrations of about <NUM>·<NUM><NUM> cm-<NUM>, in order to advantageously form Ohmic contacts with the respective S/D electrodes, although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the S/D regions <NUM> of the FinFET <NUM> are the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in a region of the semiconductor channel material between the first S/D region <NUM>-<NUM> and the second S/D region <NUM>-<NUM>, and, therefore, may be referred to as "highly doped" (HD) regions.

In some embodiments, the S/D regions <NUM> may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the one or more semiconductor materials of the upper portion of the fin <NUM> to form the S/D regions <NUM>. An annealing process that activates the dopants and causes them to diffuse further into the fin <NUM> may follow the ion implantation process. In the latter process, the one or more semiconductor materials of the fin <NUM> may first be etched to form recesses at the locations for the future source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material (which may include a combination of different materials) that is used to fabricate the S/D regions <NUM>. In some implementations, the S/D regions <NUM> may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions <NUM> may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. Although not specifically shown in the perspective illustration of <FIG>, in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain contacts (i.e., electrical contacts to each of the S/D regions <NUM>).

The FinFET <NUM> may have a gate length, GL, (i.e. a distance between the first S/D region <NUM>-<NUM> and the second S/D region <NUM>-<NUM>), a dimension measured along the fin <NUM> in the direction of the x-axis of the example reference coordinate system x-y-z shown in <FIG>, which may, in some embodiments, be between about <NUM> and <NUM> nanometers, including all values and ranges therein (e.g. between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers). The fin <NUM> may have a thickness, a dimension measured in the direction of the y-axis of the reference coordinate system x-y-z shown in <FIG>, that may, in some embodiments, be between about <NUM> and <NUM> nanometers, including all values and ranges therein (e.g. between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers). The fin <NUM> may have a height, a dimension measured in the direction of the z-axis of the reference coordinate system x-y-z shown in <FIG>, which may, in some embodiments, be between about <NUM> and <NUM> nanometers, including all values and ranges therein (e.g. between about <NUM> and <NUM> nanometers, between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers).

Although the fin <NUM> illustrated in <FIG> is shown as having a rectangular cross-section in a z-y plane of the reference coordinate system shown in <FIG>, the fin <NUM> may instead have a cross-section that is rounded or sloped at the "top" of the fin <NUM>, and the gate stack <NUM> (including the different portions of the gate dielectric <NUM>) may conform to this rounded or sloped fin <NUM>. In use, the FinFET <NUM> may form conducting channels on three "sides" of the channel portion of the fin <NUM>, potentially improving performance relative to single-gate transistors (which may form conducting channels on one "side" of a channel material or substrate) and double-gate transistors (which may form conducting channels on two "sides" of a channel material or substrate).

While <FIG> illustrates a single FinFET <NUM>, in some embodiments, a plurality of FinFETs may be arranged next to one another (with some spacing in between) along the fin <NUM>.

<FIG> provide cross-sectional side views (i.e., the views of the y-z plane of the example reference coordinate system shown in <FIG>) of IC structures <NUM> having a silicon fin of a first FinFET as shown in <FIG> and a silicon germanium fin of a second FinFET as shown in <FIG> integrated over a single support structure using silicon replacement, according to various embodiments of the present disclosure. The IC structures shown in <FIG> are intended to show relative arrangement(s) of some of the components therein and in various embodiments, the IC structures shown in <FIG>, or portions thereof, may include other components that are not illustrated (e.g., any further materials, such as spacer materials, S/D regions or electrical contacts thereto, etc.). Same holds for subsequent drawings of the present disclosure. A legend provided within a dashed box at the bottom of <FIG> illustrates colors/patterns used to indicate some portions or materials of some of the elements shown in <FIG>, so that the drawings are not cluttered by too many reference numerals (the same holds for subsequent drawings of the present disclosure that include a legend at the bottom of the drawings). For example, <FIG> use different colors/patterns to identify the STI <NUM>, the gate electrode material <NUM>, a material <NUM> of the base <NUM>, a SiGe material <NUM>, etc..

The IC structures shown in <FIG>, as well as in <FIG>, are examples of how a plurality of the FinFETs <NUM> may be arranged in an IC structure. Therefore, the IC structures shown in <FIG>, as well as in <FIG> illustrate some elements labeled with the same reference numerals as those used in <FIG> to indicate similar or analogous elements in these drawings, so that, in the interests of brevity, descriptions of a given element provided with reference to one drawing does not have to be repeated again for other drawings. For example, <FIG> and <FIG> illustrate the fin <NUM> (in particular, a plurality of such fins), the STI <NUM>, and the gate electrode material <NUM>. The same holds for subsequent drawings of the present disclosure - elements with reference numerals used in one drawing and shown again in another drawing refer to similar or analogous elements so that their descriptions do not have to be repeated for each drawing.

<FIG> illustrates an IC structure 200A that includes at least two fins, shown as a first fin <NUM>-<NUM> and a second fin <NUM>-<NUM>. Both the first and the second fins <NUM> may extend away from the base <NUM>, as was described with reference to <FIG>. The first fin <NUM>-<NUM> may include substantially the same material as that of the base <NUM>, e.g., silicon, e.g., monocrystalline silicon, shown as a silicon material <NUM>, while at least a portion of the second fin <NUM>-<NUM> may include at least one SiGe material. In particular, the embodiment shown in <FIG> illustrates a first portion <NUM>-<NUM> of the second fin <NUM>-<NUM>, a second portion <NUM>-<NUM> of the second fin <NUM>-<NUM>, and a third portion <NUM>-<NUM> of the second fin <NUM>-<NUM>.

The second portion <NUM>-<NUM> is the portion closest to the base <NUM> and may include substantially the same material as the base <NUM>, e.g., the silicon material <NUM>.

The third portion <NUM>-<NUM> is the portion farthest away from the base <NUM>, compared to the first and second portions <NUM>-<NUM>, <NUM>-<NUM>. This is the portion of the fin <NUM>-<NUM> around which the gate stack <NUM> is provided, as shown in <FIG> with the gate electrode material <NUM> surrounding the third portion <NUM>-<NUM> (although not specifically shown in <FIG>, in some embodiments, the IC structure 200A may also include the gate dielectric <NUM> between the second fin <NUM>-<NUM> and the gate electrode material <NUM>, as described with reference to <FIG>). The third portion <NUM>-<NUM> of the second fin <NUM>-<NUM> includes a SiGe material <NUM>. As shown in <FIG>, in some embodiments, a portion of the SiGe material <NUM> shown in <FIG> as a portion <NUM> indicated with dots in the SiGe material <NUM> near the sidewalls and the top of the second fin <NUM>-<NUM> may have a higher germanium concentration than the rest of the SiGe material <NUM> (e.g., than the central portion of the SiGe material <NUM> in the second fin <NUM>-<NUM>). Thus, in some embodiments, a higher germanium concentration portion <NUM> of the SiGe material <NUM> may be between the SiGe material <NUM> in the center of the second fin <NUM>-<NUM> and the gate electrode material <NUM>. In some embodiments, a concentration of germanium of the SiGe material <NUM> in the portion <NUM> (i.e., near the sidewalls of the third portion <NUM>-<NUM> of the second fin <NUM>-<NUM>) may be at least about <NUM> times higher, including all values and ranges therein, e.g., at least about <NUM> times higher, e.g., about <NUM> times higher, than the concentration of germanium in the SiGe material <NUM> (i.e., in the middle of the third portion <NUM>-<NUM> of the second fin <NUM>-<NUM>). The gradient in concentrations of germanium between the SiGe material <NUM> in the outer portion <NUM> of the second fin <NUM>-<NUM> and the SiGe material <NUM> in the central portion of the fin <NUM>-<NUM> may be one of the characteristic features of using silicon replacement to form a SiGe fin based on which one or more FinFETs may be formed. In some embodiments, the atomic percentage of germanium in the SiGe material <NUM> may be between about <NUM> and <NUM>%, e.g., the atomic percentage of germanium in the SiGe material <NUM> may be at least about <NUM>%. In some such embodiments, the remaining percentage of atoms may be silicon atoms, possibly with some impurities in negligible amounts. For example, in some embodiments, the atomic percentage of silicon in the SiGe material <NUM> may be between about <NUM> and <NUM>%, e.g., the atomic percentage of silicon in the SiGe material <NUM> may be at most about <NUM>%. On the other hand, the silicon material <NUM> may include silicon in higher concentrations than the SiGe material <NUM>. For example, in some embodiments, a concentration of silicon in the silicon material <NUM> may be at least about <NUM> times higher, including all values and ranges therein, than in the SiGe material <NUM>. For example, in some embodiments, the atomic percentage of silicon in the silicon material <NUM> may be between about <NUM> and <NUM>%, e.g., the atomic percentage of silicon in the silicon material <NUM> may be at least about <NUM> or <NUM>%.

The first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> may be the portion between the second portion <NUM>-<NUM> and the third portion <NUM>-<NUM>. As shown in <FIG>, a part of the fin <NUM>-<NUM> near the sidewalls of the first portion <NUM>-<NUM> includes the SiGe material <NUM>, e.g., having a shape of a tail as shown in <FIG>, with the amount of germanium decreasing towards the base <NUM>. On the other hand, the middle part of the first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> may include substantially the silicon material <NUM> of the base <NUM>. While <FIG> illustrates that the first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> includes the SiGe material <NUM> in higher concentration (as in the portion <NUM>, described above), in other embodiments (not specifically shown in <FIG>), the first portion <NUM>-<NUM> may include the SiGe material <NUM> in lower concentrations (as the material in the center of the second fin <NUM>-<NUM>, described above) near the sidewalls of the fin <NUM>-<NUM>. The tail shape in concentrations of germanium in the SiGe material <NUM> at the sidewalls of the first portion <NUM>-<NUM> of the fin <NUM>-<NUM> decreasing from the third portion <NUM>-<NUM> towards the second portion <NUM>-<NUM> is another one of the characteristic features of using silicon replacement to form a SiGe fin based on which one or more FinFETs may be formed.

In some embodiments of the IC structure 200A, the height (i.e., a dimension measured along the z-axis of the example coordinate system shown) of the third portion <NUM>-<NUM> of the second fin <NUM>-<NUM> may be between about <NUM> and <NUM>% of the total height of the second fin <NUM>-<NUM>. The remaining portion of the height of the second fin <NUM>-<NUM> may include the heights of the first and second portions <NUM>-<NUM>, <NUM>-<NUM>. In some embodiments, the height of the second portion <NUM>-<NUM> of the second fin <NUM>-<NUM> of the IC structure 200A may be between about <NUM> and <NUM>% of the total height of the second fin <NUM>-<NUM>.

In some embodiments, the STI <NUM> may be in contact with the sidewalls of both the first and the second portions <NUM>-<NUM>, <NUM>-<NUM> of the second fin <NUM>-<NUM>, as shown in <FIG>. In other embodiments, the STI <NUM> may be recessed so that at least a portion of the first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> is not surrounded by the STI <NUM>. In such embodiments, the portion of the first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> that is not surrounded by the STI <NUM> may be surrounded by the gate electrode material <NUM>. Such an embodiment is shown in an IC structure 200B of <FIG>. The IC structure 200B shown in <FIG> is substantially the same as the IC structure 200A shown in <FIG> except that in the IC structure 200B the first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> is not surrounded by the STI <NUM> but is surrounded by the gate electrode material <NUM>. The rest of the descriptions provided with respect to <FIG> are applicable to the IC structure 200B of <FIG> and, in the interests of brevity, are not repeated here.

<FIG> illustrates an IC structure 200C that is substantially the same as the IC structure 200A shown in <FIG> except that in the IC structure 200C the first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> extends further towards the base <NUM> so that the second portion <NUM>-<NUM> is no longer there. In such embodiments, all of the first portion <NUM>-<NUM> may be enclosed by the STI <NUM>, as shown in <FIG>. In some embodiments of the IC structure 200C, all of the third portion <NUM>-<NUM> of the second fin <NUM>-<NUM> may be the SiGe material <NUM> having a higher Ge concentration, as shown in <FIG> with dots in the SiGe material <NUM>. In some embodiments of the IC structure 200C, the height of the third portion <NUM>-<NUM> of the second fin <NUM>-<NUM> may be between about <NUM> and <NUM>% of the total height of the second fin <NUM>-<NUM>, with the remaining portion of the height of the second fin <NUM>-<NUM> being the height of the first portion <NUM>-<NUM>. The rest of the descriptions provided with respect to <FIG> are applicable to the IC structure 200C of <FIG> and, in the interests of brevity, are not repeated here.

<FIG> illustrates an IC structure 200D that is substantially the same as the IC structure 200C shown in <FIG> except that in the IC structure 200D some of the first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> is not is not surrounded by the STI <NUM> (i.e., the STI <NUM> is recessed in the IC structure 200D, similar to the IC structure 200B). In such embodiments, the portion of the first portion <NUM>-<NUM> of the second fin <NUM>-<NUM> that is not surrounded by the STI <NUM> may be surrounded by the gate electrode material <NUM>, as shown in <FIG>. The rest of the descriptions provided with respect to <FIG> are applicable to the IC structure 200D of <FIG> and, in the interests of brevity, are not repeated here.

In other embodiments, the SiGe material <NUM> of the IC structures 200C and 200C may be the SiGe material <NUM> with lower Ge concentration as described above (i.e., the SiGe material <NUM> shown in <FIG> may be without the dots shown in these figures).

<FIG> is a flow diagram of an example method <NUM> of fabricating an IC structure (e.g., any embodiments of the IC structures <NUM> shown in <FIG>) having silicon FinFETs and silicon germanium FinFETs integrated over a single support structure using silicon replacement, according to some embodiments of the present disclosure.

Although the operations of the method <NUM> are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple IC structures and/or multiple SiGe FinFETs as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more non-planar SiGe transistors fabricated using silicon replacement as described herein will be included.

In addition, the example manufacturing method <NUM> may include other operations not specifically shown in <FIG>, such as various cleaning or planarization operations as known in the art. For example, in some embodiments, the base <NUM>, as well as layers of various other materials subsequently deposited thereon, may be cleaned prior to, after, or during any of the processes of the method <NUM> described herein, e.g., to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g., a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the arrangements/devices described herein may be planarized prior to, after, or during any of the processes of the method <NUM> described herein, e.g., to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

Various operations of the method <NUM> may be illustrated with reference to the example embodiments shown in <FIG>, illustrating fabrication of the IC structures <NUM> according to various embodiments described above, but the method <NUM> may be used to manufacture any suitable IC structures having one or more non-planar SiGe transistors fabricated using silicon replacement according to any embodiments of the present disclosure. <FIG> illustrate cross-sectional side views similar to the view shown in <FIG> (i.e., a cross-section along the y-z plane), in various example stages in the manufacture of an IC structure having silicon FinFETs and silicon germanium FinFETs integrated over a single support structure using the method of <FIG> in accordance with some embodiments of the present disclosure.

The method <NUM> may begin with providing a plurality of fins over a base (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates the base <NUM> and two fins <NUM> (namely, the first fin <NUM>-<NUM> and the second fin <NUM>-<NUM>, as described above) extending away from the base <NUM>, with lower portions of the fins being enclosed by the STI <NUM>, while the upper portions of the fins being exposed. At this point, both of the fins <NUM> may be made of the silicon material <NUM>, i.e., the material of the base <NUM>. Methods for providing the fins <NUM> are known in the art and, therefore, are not described here in detail.

The method <NUM> may then proceed with providing a protective material over the fins (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates a protective material <NUM> provided as a layer over the fins <NUM>. The protective material <NUM> may include any suitable material that can protect the silicon material <NUM> of the N fin (i.e., the fin over which NMOS transistors are to be formed, which is the first fin <NUM>-<NUM> in the example described herein) from being converted to a silicon germanium material in later processes of the method <NUM>. In some embodiments, the protective material <NUM> may include one or more of dielectric materials selective to epitaxial SiGe growth such as oxide, SiN, SiOC, SiOCN, Al3O2, HfO2, ZrO2, etc. In some embodiments, the protective material <NUM> may be provided using a conformal deposition technique such as one or more of atomic layer deposition(ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or/and physical vapor deposition (PVD) processes such as e.g. sputter. However, in other embodiments, any other suitable deposition techniques may be used to provide the protective material <NUM> over the fins <NUM> provided in <NUM>, such as spin-coating or dip-coating.

The method <NUM> may then include providing an etch block material over the N fin (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates an etch block material <NUM> provided over the protective material <NUM> provided over the first fin <NUM>-<NUM>. The etch block material <NUM> may include any suitable material that is etch selective with respect to the protective material <NUM>, meaning that the etch block material <NUM> and the protective material <NUM> are selected so that etchants that may be used to etch the protective material <NUM> do not substantially etch the etch block material <NUM>. In some embodiments, the etch block material <NUM> may include one or more of lithographic patterning materials such as carbon hardmask, anti-reflective coatings, SiN, SiON, photoresist, etc. In some embodiments, the etch block material <NUM> may be provided using spin-on or any of the conformal deposition techniques described above. Although not specifically shown in <FIG>, in various embodiments, any suitable patterning techniques may be used in the process <NUM> to define the locations and the dimensions of the etch block material <NUM>, such as, but not limited to, photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with the use of one or more masks.

The method <NUM> may then include etching the protective material <NUM> that is not protected with the etch block material <NUM> and, following the etch, removing the etch block material <NUM> (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates that the silicon material <NUM> of the P fin (i.e., the fin over which PMOS transistors are to be formed, which is the second fin <NUM>-<NUM> in the example described herein) is now exposed because the protective material <NUM> has been etched away. The IC structure <NUM> also illustrates that the etch block material <NUM> has been removed from the N fin <NUM>-<NUM>. In some embodiments, process <NUM> may include performing an isotropic etch such as a wet etch using any suitable etchants. In other embodiments, process <NUM> may include performing an anisotropic etch. In some embodiments, the anisotropic etch of the process <NUM> may include an etch that uses etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (CI) based chemistries. In some embodiments, during the etch of the process <NUM>, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and <NUM> degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface. In some embodiments, the anisotropic etch of the process <NUM> may include a dry etch, such as radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE.

The method <NUM> may then proceed with performing selective deposition of a Ge-rich SiGe cladding over the P fin (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates a Ge-rich SiGe cladding <NUM> provided over the top and the sidewalls of the second fin <NUM>-<NUM>. In some embodiments, the Ge-rich SiGe cladding <NUM> may be a semiconductor material that includes Si and Ge atoms, with the atomic concentration of the Ge atoms being between about <NUM> and <NUM>%, including all values and ranges therein. In some embodiments, deposition of the Ge-rich SiGe cladding <NUM> may be selective to the protective material <NUM> and the STI <NUM> (e.g., may be selective to the insulator materials used in the protective material <NUM> and the STI <NUM>), which means that the cladding <NUM> may be selectively deposited on the sidewalls and the top of the second fin <NUM>-<NUM> but not the protective material <NUM> or the STI <NUM>. In some embodiments, the deposition of the Ge-rich SiGe cladding <NUM> may be conformal on the second fin <NUM>-<NUM>, as shown in <FIG>, or faceted (not specifically shown in the present drawings). In various embodiments, the Ge-rich SiGe cladding <NUM> may be a crystalline material, such as single crystal or polycrystalline configurations. In other embodiments, the Ge-rich SiGe cladding <NUM> may be amorphous (e.g., provided by amorphous deposition) to provide a conformal profile as depicted in <FIG>. Selective deposition of the Ge-rich SiGe cladding <NUM> to provide an amorphous configuration may be performed using any suitable technique such as gas source molecular beam epitaxy (GS-MBE), CVD, or rapid thermal CVD (RT-CVD). Selective deposition of the Ge-rich SiGe cladding <NUM> to provide a crystalline configuration may be performed using germane and applying deposition temperatures of up to <NUM> degrees Celsius.

Next, the method <NUM> may include annealing the IC structure formed in the process <NUM> to oxidize the Ge-rich SiGe cladding provided over the P fin (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates that, as a result of the anneal, the germanium diffuses from the Ge-rich SiGe cladding <NUM> provided over the top and the sidewalls of the second fin <NUM>-<NUM> into the silicon material <NUM> of the second fin <NUM>-<NUM>, thereby replacing the Si atoms in the silicon material <NUM> with Ge atoms (hence, the term "silicon replacement"), effectively converting the silicon material <NUM> into a SiGe semiconductor material. Because Ge atoms are leaving the Ge-rich SiGe cladding <NUM> during the anneal of the process <NUM>, the Ge-rich SiGe cladding <NUM> may be converted to an oxide material <NUM>. In some embodiments, the process <NUM> may include performing an anneal of the IC structure <NUM> at oxidation conditions (e.g., in oxygen ambient), using temperatures of about <NUM> degrees Celsius with wet and/or plasma-assisted oxidation, up to about <NUM> degrees Celsius, possibly with a slow cooling ramp. In some embodiments, the process <NUM> may include performing an anneal of the IC structure <NUM> in an inert ambient such as nitrogen. The anneal time may be selected to provide a desired composition profile of germanium in the silicon material <NUM> of the second fin <NUM>-<NUM>. For example, in some embodiments, the anneal time may be selected to partially convert the silicon material <NUM> of the second fin <NUM>-<NUM> that is encapsulated by the Ge-rich SiGe cladding <NUM> to a silicon germanium material. For example, the anneal time may be less than an hour (e.g., from seconds to about <NUM>-<NUM> minutes) at about <NUM> degrees Celsius to partially convert the silicon material <NUM> of the second fin <NUM>-<NUM> to SiGe. An anneal that partially converts the silicon material <NUM> of the second fin <NUM>-<NUM> to SiGe may provide a Ge-rich surface on the second fin <NUM>-<NUM> relative to the central portion of the second fin <NUM>-<NUM>, as is shown in <FIG> with the higher-Ge concentration interface portion <NUM> of the SiGe material <NUM> and the lower-Ge concentration inner portion of the SiGe material <NUM>, described above. As a result of performing the anneal, part of the second fin <NUM>-<NUM> that is not enclosed by the Ge-rich SiGe cladding <NUM> but is near the Ge-rich SiGe cladding <NUM> may also be converted to a SiGe material. This is shown in <FIG> with the tail portions of the SiGe material <NUM> near the sidewalls of the second fin <NUM>-<NUM> just below the Ge-rich SiGe cladding <NUM>, within the portion <NUM>-<NUM> of the second fin <NUM>-<NUM>, in areas identified in <FIG> with dotted contours <NUM>.

In other embodiments, the anneal time of the process <NUM> may be selected to fully or substantially fully convert the silicon material <NUM> of the second fin <NUM>-<NUM> that is encapsulated by the Ge-rich SiGe cladding <NUM> to a silicon germanium material, a result of which is shown in <FIG> as an IC structure <NUM>. In some embodiments, the second fin <NUM>-<NUM> may be fully converted from silicon to SiGe by annealing at about <NUM> degrees Celsius for about one hour. As shown in <FIG>, in this case, all of the silicon material <NUM> of the second fin <NUM>-<NUM> may be converted to the SiGe material <NUM>, e.g., as described with reference to <FIG>. As a result of performing the anneal longer, a further part of the second fin <NUM>-<NUM> that is not enclosed by the Ge-rich SiGe cladding <NUM> but is near the Ge-rich SiGe cladding <NUM> may also be converted to a SiGe material. This is shown in <FIG> with the tail portions of the SiGe material <NUM> in areas identified in <FIG> with dotted contours <NUM>. As shown in the dotted contours <NUM>, the SiGe material in the fin <NUM>-<NUM> now extends further down towards the base <NUM>, compared to the shorter anneal depicted in <FIG>.

The anneal of the process <NUM> is not limited to the example times, temperatures, and conditions described above and may include other suitable temperatures, anneal times, and anneal conditions in other embodiments of the present disclosure. For example, an anneal time may range from seconds to days depending on a selected temperature and desired composition of SiGe in the second fin <NUM>-<NUM>.

Next, the method <NUM> may proceed with removing the protective material from the N fin (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates that the protective material <NUM> has been removed from the first fin <NUM>-<NUM>. In some embodiments, the process <NUM> may include using an etch process (e.g., an isotropic etch) with suitable etchants for removing the protective material <NUM>.

The method <NUM> may also include removing the oxide material from the P fin (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates that the oxide material <NUM> has been removed from the second fin <NUM>-<NUM>. In some embodiments, the process <NUM> may include using an etch process (e.g., an isotropic etch) with suitable etchants for removing the oxide material <NUM>. In some embodiments, the process <NUM> may be performed before the process <NUM>.

<FIG> illustrates an IC structure <NUM> showing an example result of performing the processes <NUM> and <NUM> after the anneal process of process <NUM> that resulted in creation of the IC structure <NUM> shown in <FIG>.

The method <NUM> may also include providing source, drain, and gate terminals in the fins <NUM>-<NUM> and <NUM>-<NUM> of the IC structure resulting from performing the processes <NUM>-<NUM> (process <NUM> shown in <FIG>, a result of which is not shown in <FIG> but could be any of the embodiments shown in <FIG>). The process <NUM> may include providing the S/D regions <NUM> in the fins <NUM>, the S/D contacts, and the gate stack <NUM>, as described above, for each of the transistors. Processes for forming these transistor elements are known in the art and, therefore, are not described herein detail.

<FIG> is a perspective view of an example nanoribbon transistor <NUM>, according to some embodiments of the disclosure, not forming part of the present invention. The nanoribbon transistor 500illustrates an example structure for a non-planar SiGe transistor fabricated using silicon replacement as described herein. For example a plurality of nanoribbons with transistors such as the nanoribbon transistors 500may be used to provide an IC structure having silicon nanoribbon transistors <NUM> and silicon germanium nanoribbon transistors <NUM> integrated over a single support structure using silicon replacement, as described with reference to <FIG>, and <FIG>. The nanoribbon transistor <NUM> shown in <FIG> is intended to show relative arrangement(s) of some of the components therein. In various embodiments, the nanoribbon transistor <NUM>, or portions thereof, may include other components that are not illustrated (e.g., any further materials, such as e.g. spacer materials, surrounding the gate stack of the nanoribbon transistor <NUM>, electrical contacts to the S/D regions of the nanoribbon transistor <NUM>, etc.).

As shown, the nanoribbon transistor <NUM> of <FIG> may include a support structure <NUM>, a nanoribbon <NUM> provided over the support structure <NUM>, and a gate stack <NUM> comprising a gate electrode material <NUM> and, optionally, a gate dielectric <NUM>. Discussions provided above regarding the base <NUM>, the material of the fin <NUM>, the gate electrode material <NUM>, and the gate dielectric <NUM> are applicable to, respectively, the support structure <NUM>, the material of the nanoribbon <NUM>, the gate electrode material <NUM>, and the gate dielectric <NUM>, and, therefore, in the interests of brevity, are not repeated.

Unlike the fin <NUM> that extends away from the base <NUM> in the transistor shown in <FIG>, the nanoribbon transistor <NUM> includes a nanoribbon <NUM> that is provided above the support structure <NUM>. In various embodiments, the nanoribbon <NUM> may take the form of a nanowire or nanowire, for example. The gate stack <NUM> may wrap entirely or almost entirely around the nanoribbon <NUM>, as shown, with the channel portion of the nanoribbon <NUM> corresponding to the portion of the nanoribbon <NUM> wrapped by the gate stack <NUM>. In particular, the gate dielectric <NUM> may wrap around the channel material of the nanoribbon <NUM>, and the gate electrode material <NUM> may wrap around the gate dielectric <NUM>. The nanoribbon <NUM> may include S/D regions <NUM> on either side of the gate stack <NUM>, similar to the S/D regions <NUM> shown in <FIG>, thus realizing a transistor. The source and drain regions <NUM>-<NUM>, <NUM>-<NUM> may be contacted with S/D contacts, not specifically shown in <FIG>. The transistor <NUM> may have a gate length (i.e., a distance between the S/D regions <NUM>-<NUM> and <NUM>-<NUM>), a dimension measured along the nanoribbon <NUM>, in the direction of the x-axis of an exemplary reference coordinate system x-y-z shown in <FIG>, which may, in some embodiments, be between about <NUM> and <NUM> nanometers, including all values and ranges therein (e.g. between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers).

Although the nanoribbon <NUM> illustrated in <FIG> is shown as having a rectangular cross-section in a z-y plane of the reference coordinate system shown in <FIG>, the nanoribbon <NUM> may instead have a cross-section that is rounded or otherwise irregularly shaped, and the gate stack <NUM> may conform to the shape of the nanoribbon <NUM>. In use, the nanoribbon transistor <NUM> may form conducting channels on more than three "sides" of the nanoribbon <NUM>, potentially improving performance relative to FinFETs. In still further embodiments of the nanoribbon transistor <NUM>, the gate stack <NUM> may be provided over only <NUM> of the <NUM> sides of the nanoribbon <NUM> shown in <FIG>, thus forming a nanocomb transistor (which may be considered to be one type of the nanoribbon transistor <NUM>).

While <FIG> illustrates a single nanoribbon transistor <NUM>, in some embodiments, a plurality of nanoribbon transistors <NUM> may be arranged next to one another (with some spacing in between) along the nanoribbon <NUM>.

<FIG> is a flow diagram of an example method <NUM> of fabricating an IC structure having silicon nanoribbons and silicon germanium nanoribbons integrated over a single support structure using silicon replacement, according to some embodiments of the present disclosure, not forming part of the present invention.

Although the operations of the method <NUM> are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple IC structures and/or multiple SiGe nanoribbon transistors as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more non-planar SiGe transistors fabricated using silicon replacement as described herein will be included. In addition, the example manufacturing method <NUM> may include other operations not specifically shown in <FIG>, such as various cleaning or planarization operations as known in the art, e.g., as those described with reference to the method <NUM>.

Various operations of the method <NUM> may be illustrated with reference to the example embodiments shown in <FIG>, illustrating fabrication of the IC structures with silicon germanium nanoribbon transistors according to various embodiments described above, but the method <NUM> may be used to manufacture any suitable IC structures having one or more non-planar SiGe transistors fabricated using silicon replacement according to any embodiments of the present disclosure. <FIG> illustrate cross-sectional side views similar to the view shown in <FIG> (i.e., a cross-section along the y-z plane), in various example stages in the manufacture of an IC structure having silicon nanoribbon transistors and silicon germanium nanoribbon transistors integrated over a single support structure using the method of <FIG> in accordance with some embodiments of the present disclosure.

The method <NUM> may begin with providing at least two stacks over a base, each stack including a plurality of nanoribbons of a silicon material, separated from one another by a Ge-rich silicon germanium material (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates the support structure <NUM> and two stacks <NUM> (namely, the first stack <NUM>-<NUM> and the second stack <NUM>-<NUM>) extending away from the support structure <NUM>. Each stack <NUM> includes nanoribbons <NUM> of a silicon material <NUM>, separated by a Ge-rich silicon germanium material <NUM>. A dielectric material <NUM> may be provided to enclose the lower portions of the stacks <NUM>, similar to the STI <NUM> described above. The silicon material <NUM> may include any of the materials described above with reference to the silicon material <NUM>. The Ge-rich silicon germanium material <NUM> may include any of the materials described above with reference to the Ge-rich silicon germanium material <NUM>. As shown in <FIG>, the support structure <NUM> may also include the silicon material <NUM>. The stacks <NUM> of nanoribbons <NUM> may be provided in the process <NUM> using any suitable deposition and patterning techniques, such as epitaxial deposition of layers of the silicon material <NUM> alternating with layers of the Ge-rich silicon germanium material <NUM>, followed by any of the patterning techniques known in the art (some of which are described above) to form the stacks <NUM>. One of the two stacks <NUM> shown in <FIG> may be designated as an N stack (i.e., as a stack in which N-type nanoribbon transistors will be provided), e.g., the first stack <NUM>-<NUM>, while the other stack may be designated as a P stack (i.e., as a stack in which P-type nanoribbon transistors will be provided), e.g., the second stack <NUM>-<NUM>.

The method <NUM> may then proceed with providing a protective material over the N stack (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates a protective material <NUM> provided as a layer over the N stack <NUM>-<NUM>. The protective material <NUM> may include any of the materials described above with reference to the protective material <NUM> and may be provided over the N stack <NUM>-<NUM> using a number of processes and intermediate materials (e.g., similar to the processes <NUM>, <NUM>, and a part of the process <NUM>, described above).

Next, in some embodiments, the method <NUM> may include an optional process of etching back the SiGe material in the P type stack of the IC structure formed in the process <NUM> (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates that, as a result of the SiGe etchback of the process <NUM>, some of the Ge-rich silicon germanium material <NUM> may be recessed, laterally (the recessed portions shown in <FIG> as portions <NUM>), with respect to the nanoribbons <NUM> of the silicon material <NUM>. In some embodiments, the width (a dimension measured along the y-axis of the example coordinate system shown) of the Ge-rich silicon germanium material <NUM> that has been recessed in the portion <NUM> may be about <NUM>% smaller than the width of the nanoribbons <NUM>, e.g., about <NUM>-<NUM> nanometers smaller. In some embodiments, the process <NUM> may include performing selective etch of the Ge-rich silicon germanium material <NUM> with respect to the silicon material <NUM>. Performing the etchback in the process <NUM> may help with providing a more uniform and a more complete Ge diffusion in the anneal process <NUM>.

The method <NUM> may then proceed with performing an anneal of the IC structure formed in the process <NUM> or formed in the process <NUM>, in case the process <NUM> was not performed, to oxidize the Ge-rich silicon germanium material <NUM> that is exposed in the P type stack <NUM>-<NUM> (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates that, as a result of the anneal, the germanium diffuses from the Ge-rich silicon germanium material <NUM> in the P type stack <NUM>-<NUM> into the silicon material <NUM> of the nanoribbons <NUM> of that stack, thereby converting the silicon material <NUM> of the nanoribbons <NUM> of the stack <NUM>-<NUM> into a SiGe material <NUM> and converting the Ge-rich silicon germanium material <NUM> to an oxide material <NUM>. In some embodiments, the process <NUM> may include an anneal as described with reference to the process <NUM>. The anneal time may be selected to provide a desired composition profile of germanium in the silicon material <NUM> of the nanoribbons <NUM> in the second stack <NUM>-<NUM>. For example, in some embodiments, the anneal time may be selected to partially convert the silicon material <NUM> of the nanoribbons <NUM> in the second stack <NUM>-<NUM> to the SiGe material <NUM>. For example, the anneal time may be less than an hour (e.g., from seconds to about <NUM>-<NUM> minutes) at about <NUM> degrees Celsius to partially convert the silicon material <NUM> of the nanoribbons <NUM> in the second stack <NUM>-<NUM> to SiGe. An anneal that partially converts the silicon material <NUM> of the nanoribbons <NUM> in the second stack <NUM>-<NUM> to SiGe may provide a Ge-rich surface on the nanoribbons <NUM> relative to the central portion of the nanoribbons <NUM>, as is shown in <FIG> with the higher-Ge concentration interface portion <NUM> of the SiGe material <NUM> and the lower-Ge concentration inner portion of the SiGe material <NUM> in each of the nanoribbons <NUM> of the second stack <NUM>-<NUM>. The portion <NUM> and the SiGe material <NUM> are analogous to the portion <NUM> and the SiGe material <NUM>, described above.

As a result of performing the anneal in the process <NUM>, a portion of the silicon material <NUM> of the second stack <NUM>-<NUM> that is not supposed to be a nanoribbon for providing transistors therein but is in contact with the Ge-rich silicon germanium material <NUM> may also be converted to a SiGe material. This is shown in <FIG> with a portion <NUM> of the SiGe material <NUM>.

In other embodiments, the anneal time of the process <NUM> may be selected to fully or substantially fully convert the silicon material <NUM> of the second stack <NUM>-<NUM> to a silicon germanium material, a result of which is shown in <FIG> as an IC structure <NUM>. This longer anneal process may be analogous to the anneal process described with reference to <FIG>.

The anneal of the process <NUM> is not limited to the example times, temperatures, and conditions described above and may include other suitable temperatures, anneal times, and anneal conditions in other embodiments of the present disclosure. For example, an anneal time may range from seconds to days depending on a selected temperature and desired composition of SiGe in the second stack <NUM>-<NUM>.

Next, the method <NUM> may proceed with removing the oxide material <NUM> from the P stack and removing the Ge-rich SiGe material <NUM> from the N stack (process <NUM> shown in <FIG>, a result of which is illustrated with an IC structure <NUM>, shown in <FIG>). The IC structure <NUM> illustrates that the nanoribbons <NUM> of the silicon material <NUM> may remain where the first stack <NUM>-<NUM> used to be, and nanoribbons <NUM> of the SiGe material <NUM> may be where the nanoribbons <NUM> of the silicon material <NUM> of the second stack <NUM>-<NUM> used to be. Thus, as a result of performing the method <NUM>, the silicon nanoribbons <NUM> may be aligned with the SiGe nanoribbons <NUM>, e.g., aligned both at the bottom (as shown in <FIG> with a line <NUM> for one pair of Si and SiGe nanoribbons) and at the top (as shown in <FIG> with a line <NUM> for that pair of Si and SiGe nanoribbons). In some embodiments, the process <NUM> may include using various etch processes with suitable etchants for removing the oxide material <NUM> from the P stack and removing the Ge-rich SiGe material <NUM> from the N stack. Although not specifically shown in <FIG>, the nanoribbons <NUM> and <NUM> may be surrounded by a dielectric material, e.g., any of the materials described with reference to the STI <NUM>.

The method <NUM> may also include providing source, drain, and gate terminals in the nanoribbons <NUM> and <NUM> of the IC structure resulting from performing the processes <NUM>-<NUM>, thus forming nanoribbon transistors (process <NUM> shown in <FIG>, a result of which is not shown in <FIG> but could be any of the embodiments of the nanoribbon transistor shown in <FIG>). The process <NUM> may include providing the S/D regions <NUM> in the nanoribbons <NUM> and <NUM>, the S/D contacts, and the gate stack <NUM>, as described above, for each of the transistors. Processes for forming these transistor elements are known in the art and, therefore, are not described herein detail.

The IC structures illustrated in <FIG> do not represent an exhaustive set of assemblies in which one or more non-planar SiGe transistors fabricated using silicon replacement as described herein may be integrated, but merely provide examples of such structures. For example, although particular arrangements of materials are discussed with reference to <FIG>, intermediate materials may be included in various portions of these drawings. Additionally, although some elements of the arrangements are illustrated in <FIG> as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of various ones of these elements may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. For example, while <FIG> may illustrate various elements, e.g., the fins <NUM>, nanoribbons <NUM>, etc., as having perfectly straight sidewall profiles, i.e., profiles where the sidewalls extend perpendicularly to the base <NUM>, these idealistic profiles may not always be achievable in real-world manufacturing processes. Therefore, descriptions of various embodiments of non-planar SiGe transistors fabricated using silicon replacement as provided herein are equally applicable to embodiments where various elements of such integrated structures look different from those shown in the drawings due to manufacturing processes used to form them.

Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g., Physical Failure Analysis (PFA) would allow determination of the integration of one or more non-planar SiGe transistors fabricated using silicon replacement as described herein within an IC structure. In some implementations, the silicon replacement technique may leave a signature of higher Ge at the interface and can be detected e.g. at the edge of a fin of a FinFET by high resolution TEM cross section. In the case of partially or fully replaced SiGe nanoribbons, nanowires, and/or nanocombs, the height of the NMOS and PMOS may be substantially the same, the position of the nanoribbons, nanowires, and/or nanocombs in height may be substantially the same, with the main difference being that NMOS is Si and PMOS is SiGe. Inspection of a TEM cross section may allow to see in more detail the match in height and characterization techniques such as energy-dispersive X-ray (EDX) spectroscopy or electron energy loss (EEL) spectroscopy can detect any profile in the Ge concentration in the SiGe materials.

IC structures with one or more non-planar SiGe transistors fabricated using silicon replacement as disclosed herein may be included in any suitable electronic device. <FIG> illustrate various examples of devices and components that may include one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement as disclosed herein.

<FIG> are top views of a wafer <NUM> and dies <NUM> that may include one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement in accordance with any of the embodiments disclosed herein. In some embodiments, the dies <NUM> may be included in an IC package, in accordance with any of the embodiments disclosed herein. For example, any of the dies <NUM> may serve as any of the dies <NUM> in an IC package <NUM> shown in <FIG>. The wafer <NUM> may be composed of semiconductor material and may include one or more dies <NUM> having IC structures formed on a surface of the wafer <NUM>. Each of the dies <NUM> may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement as described herein), the wafer <NUM> may undergo a singulation process in which each of the dies <NUM> is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement as disclosed herein may take the form of the wafer <NUM> (e.g., not singulated) or the form of the die <NUM> (e.g., singulated). The die <NUM> may include supporting circuitry to route electrical signals to various memory cells, transistors, capacitors, as well as any other IC components. In some embodiments, the wafer <NUM> or the die <NUM> may implement or include a memory device (e.g., a DRAM or an SRAM device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die <NUM>.

<FIG> is a side, cross-sectional view of an example IC package <NUM> that may include one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package <NUM> may be a system-in-package (SiP).

The package substrate <NUM> may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face <NUM> and the face <NUM>, or between different locations on the face <NUM>, and/or between different locations on the face <NUM>.

The package substrate <NUM> may include conductive contacts <NUM> that are coupled to conductive pathways <NUM> through the package substrate <NUM>, allowing circuitry within the dies <NUM> and/or the interposer <NUM> to electrically couple to various ones of the conductive contacts <NUM> (or to other devices included in the package substrate <NUM>, not shown).

The IC package <NUM> may include an interposer <NUM> coupled to the package substrate <NUM> via conductive contacts <NUM> of the interposer <NUM>, first-level interconnects <NUM>, and the conductive contacts <NUM> of the package substrate <NUM>. The first-level interconnects <NUM> illustrated in <FIG> are solder bumps, but any suitable first-level interconnects <NUM> may be used. In some embodiments, no interposer <NUM> may be included in the IC package <NUM>; instead, the dies <NUM> may be coupled directly to the conductive contacts <NUM> at the face <NUM> by first-level interconnects <NUM>.

The IC package <NUM> may include one or more dies <NUM> coupled to the interposer <NUM> via conductive contacts <NUM> of the dies <NUM>, first-level interconnects <NUM>, and conductive contacts <NUM> of the interposer <NUM>. The conductive contacts <NUM> may be coupled to conductive pathways (not shown) through the interposer <NUM>, allowing circuitry within the dies <NUM> to electrically couple to various ones of the conductive contacts <NUM> (or to other devices included in the interposer <NUM>, not shown). The first-level interconnects <NUM> illustrated in <FIG> are solder bumps, but any suitable first-level interconnects <NUM> may be used. As used herein, a "conductive contact" may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

In some embodiments, an underfill material <NUM> may be disposed between the package substrate <NUM> and the interposer <NUM> around the first-level interconnects <NUM>, and a mold compound <NUM> may be disposed around the dies <NUM> and the interposer <NUM> and in contact with the package substrate <NUM>. In some embodiments, the underfill material <NUM> may be the same as the mold compound <NUM>. Example materials that may be used for the underfill material <NUM> and the mold compound <NUM> are epoxy mold materials, as suitable. Second-level interconnects <NUM> may be coupled to the conductive contacts <NUM>. The second-level interconnects <NUM> illustrated in <FIG> are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects <NUM> may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects <NUM> may be used to couple the IC package <NUM> to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to <FIG>.

The dies <NUM> may take the form of any of the embodiments of the die <NUM> discussed herein (e.g., may include any of the embodiments of the IC structures with non-planar SiGe transistors fabricated using silicon replacement as described herein). In embodiments in which the IC package <NUM> includes multiple dies <NUM>, the IC package <NUM> may be referred to as a multi-chip package (MCP). The dies <NUM> may include circuitry to perform any desired functionality. For example, one or more of the dies <NUM> may be logic dies (e.g., silicon-based dies), and one or more of the dies <NUM> may be memory dies (e.g., high bandwidth memory), including embedded memory dies as described herein. In some embodiments, any of the dies <NUM> may include one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement, e.g., as discussed above; in some embodiments, at least some of the dies <NUM> may not include any IC structures with non-planar SiGe transistors fabricated using silicon replacement.

The IC package <NUM> illustrated in <FIG> may be a flip chip package, although other package architectures may be used. For example, the IC package <NUM> may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package <NUM> may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies <NUM> are illustrated in the IC package <NUM> of <FIG>, an IC package <NUM> may include any desired number of the dies <NUM>. An IC package <NUM> may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face <NUM> or the second face <NUM> of the package substrate <NUM>, or on either face of the interposer <NUM>. More generally, an IC package <NUM> may include any other active or passive components known in the art.

<FIG> is a cross-sectional side view of an IC device assembly <NUM> that may include components having one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement in accordance with any of the embodiments disclosed herein. The IC device assembly <NUM> includes a number of components disposed on a circuit board <NUM> (which may be, e.g., a motherboard). The IC device assembly <NUM> includes components disposed on a first face <NUM> of the circuit board <NUM> and an opposing second face <NUM> of the circuit board <NUM>; generally, components may be disposed on one or both faces <NUM> and <NUM>. In particular, any suitable ones of the components of the IC device assembly <NUM> may include any of one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above with reference to <FIG> (e.g., may include one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement provided on a die <NUM>).

In some embodiments, the circuit board <NUM> may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board <NUM>. In other embodiments, the circuit board <NUM> may be a non-PCB substrate.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-interposer structure <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may electrically and mechanically couple the package-on-interposer structure <NUM> to the circuit board <NUM>, and may include solder balls (e.g., as shown in <FIG>), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure <NUM> may include an IC package <NUM> coupled to an interposer <NUM> by coupling components <NUM>. The coupling components <NUM> may take any suitable form for the application, such as the forms discussed above with reference to the coupling components <NUM>. The IC package <NUM> may be or include, for example, a die (the die <NUM> of <FIG>), an IC device, or any other suitable component. In particular, the IC package <NUM> may include one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement as described herein. Although a single IC package <NUM> is shown in <FIG>, multiple IC packages may be coupled to the interposer <NUM>; indeed, additional interposers may be coupled to the interposer <NUM>. The interposer <NUM> may provide an intervening substrate used to bridge the circuit board <NUM> and the IC package <NUM>. Generally, the interposer <NUM> may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer <NUM> may couple the IC package <NUM> (e.g., a die) to a BGA of the coupling components <NUM> for coupling to the circuit board <NUM>. In the embodiment illustrated in <FIG>, the IC package <NUM> and the circuit board <NUM> are attached to opposing sides of the interposer <NUM>; in other embodiments, the IC package <NUM> and the circuit board <NUM> may be attached to a same side of the interposer <NUM>. In some embodiments, three or more components may be interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer <NUM>. The package-on-interposer structure <NUM> may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly <NUM> may include an IC package <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may take the form of any of the embodiments discussed above with reference to the coupling components <NUM>, and the IC package <NUM> may take the form of any of the embodiments discussed above with reference to the IC package <NUM>.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-package structure <NUM> coupled to the second face <NUM> of the circuit board <NUM> by coupling components <NUM>. The package-on-package structure <NUM> may include an IC package <NUM> and an IC package <NUM> coupled together by coupling components <NUM> such that the IC package <NUM> is disposed between the circuit board <NUM> and the IC package <NUM>. The coupling components <NUM> and <NUM> may take the form of any of the embodiments of the coupling components <NUM> discussed above, and the IC packages <NUM> and <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above. The package-on-package structure <NUM> may be configured in accordance with any of the package-on-package structures known in the art.

<FIG> is a block diagram of an example computing device <NUM> that may include one or more components with one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device <NUM> may include a die (e.g., the die <NUM> (<FIG>)) including one or more IC structures with non-planar SiGe transistors fabricated using silicon replacement in accordance with any of the embodiments disclosed herein. Any of the components of the computing device <NUM> may include an IC package <NUM> (<FIG>). Any of the components of the computing device <NUM> may include an IC device assembly <NUM> (<FIG>).

A number of components are illustrated in <FIG> as included in the computing device <NUM>, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device <NUM> may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die.

Additionally, in various embodiments, the computing device <NUM> may not include one or more of the components illustrated in <FIG>, but the computing device <NUM> may include interface circuitry for coupling to the one or more components. For example, the computing device <NUM> may not include a display device <NUM>, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device <NUM> may be coupled. In another set of examples, the computing device <NUM> may not include an audio input device <NUM> or an audio output device <NUM>, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device <NUM> or audio output device <NUM> may be coupled.

The computing device <NUM> may include a processing device <NUM> (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device <NUM> may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device <NUM> may include a memory <NUM>, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory <NUM> may include memory that shares a die with the processing device <NUM>.

In some embodiments, the computing device <NUM> may include a communication chip <NUM> (e.g., one or more communication chips). For example, the communication chip <NUM> may be configured for managing wireless communications for the transfer of data to and from the computing device <NUM>. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium.

The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication chip <NUM> may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip <NUM> may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication chip <NUM> may operate in accordance with other wireless protocols in other embodiments. The computing device <NUM> may include an antenna <NUM> to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip <NUM> may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip <NUM> may include multiple communication chips. For instance, a first communication chip <NUM> may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip <NUM> may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip <NUM> may be dedicated to wireless communications, and a second communication chip <NUM> may be dedicated to wired communications.

The computing device <NUM> may include battery/power circuitry <NUM>. The battery/power circuitry <NUM> may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device <NUM> to an energy source separate from the computing device <NUM> (e.g., AC line power).

The computing device <NUM> may include a display device <NUM> (or corresponding interface circuitry, as discussed above). The display device <NUM> may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device <NUM> may include an audio output device <NUM> (or corresponding interface circuitry, as discussed above). The audio output device <NUM> may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device <NUM> may include an audio input device <NUM> (or corresponding interface circuitry, as discussed above). The audio input device <NUM> may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device <NUM> may include a GPS device <NUM> (or corresponding interface circuitry, as discussed above). The GPS device <NUM> may be in communication with a satellite-based system and may receive a location of the computing device <NUM>, as known in the art.

The computing device <NUM> may include an other output device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other output device <NUM> may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device <NUM> may include an other input device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other input device <NUM> may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The computing device <NUM> may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device <NUM> may be any other electronic device that processes data.

Claim 1:
An integrated circuit, IC, structure (200A), comprising:
a fin (<NUM>-<NUM>), extending away from a base (<NUM>), comprising a SiGe material, the fin (<NUM>-<NUM>) comprising a first portion (<NUM>-<NUM>), a second portion (<NUM>-<NUM>) and a third portion (<NUM>-<NUM>), the second portion (<NUM>-<NUM>) being closest to the base (<NUM>), the third portion (<NUM>-<NUM>) being the portion farthest away from the base (<NUM>),
where a concentration of germanium, Ge, near sidewalls of the third portion (<NUM>-<NUM>) of the fin (<NUM>-<NUM>) is at least <NUM> times higher than the concentration of Ge in a middle of the portion of the fin (<NUM>-<NUM>), wherein the fin (<NUM>-<NUM>) comprises a tail shape in concentrations of germanium in the SiGe material at sidewalls of the first portion (<NUM>-<NUM>) of the fin (<NUM>-<NUM>) decreasing from the third portion (<NUM>-<NUM>) towards the second portion (<NUM>-<NUM>); and
a gate stack (<NUM>) wrapping around the third portion (<NUM>-<NUM>) of the fin (<NUM>-<NUM>), wherein all of the middle of the third portion (<NUM>-<NUM>) of the fin (<NUM>-<NUM>) that is wrapped around by the gate stack (<NUM>) includes Ge and silicon, Si, with an atomic percentage of Ge being between <NUM> and <NUM>%.