Patent Description:
The present invention is defined by a phase-change-based memory die according to independent claim <NUM> and by a method of performing write operations in the phase-change-based memory die according to independent claim <NUM>. Advantageous features are set out in the dependent claims.

In the illustrative embodiment, a memory die (such as memory die <NUM> in <FIG>) has a buffer (such as buffer <NUM> in memory die <NUM>) that can buffer memory write operations received from a microcontroller (such as microcontroller <NUM> in <FIG>). The memory die <NUM> can space the memory write operations out by a required spacing, which complies with the power limits on the memory die <NUM>. Because the memory die <NUM> can buffer memory write operations, the microcontroller <NUM> can send multiple consecutive or burst write operations to the memory die <NUM> at the maximum command rate before the microcontroller <NUM> switches to a new rank or memory die <NUM>, which has a time cost associated with it. As the microcontroller <NUM> does not need to switch rank or die <NUM> for each write operation, the efficiency of memory operations is increased.

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).

Although the drawings depict particular computer systems, the concepts of various embodiments are applicable to any suitable computer systems. Examples of systems in which teachings of the present disclosure may be used include desktop computer systems, server computer systems, storage systems, handheld devices, tablets, other thin notebooks, system on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, digital cameras, media players, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include microcontrollers, digital signal processors (DSPs), SOCs, network computers (NetPCs), set-top boxes, network hubs, wide area networks (WANs) switches, or any other system that can perform the functions and operations taught below. Various embodiments of the present disclosure may be used in any suitable computing environment, such as a personal computing device, a server, a mainframe, a cloud computing service provider infrastructure, a datacenter, a communications service provider infrastructure (e.g., one or more portions of an Evolved Packet Core), or other environment comprising one or more computing devices.

<FIG> illustrates components of a computer system <NUM> in accordance with certain embodiments. System <NUM> includes a central processing unit (CPU) <NUM> coupled to an external input/output (I/O) controller <NUM>, a storage device <NUM> such as a solid state drive (SSD), and system memory device <NUM>. During operation, data may be transferred between a storage device <NUM> and/or system memory device <NUM> and the CPU <NUM>. In various embodiments, particular memory access operations (e.g., read and write operations) involving a storage device <NUM> or system memory device <NUM> may be issued by an operating system and/or other software applications executed by processor <NUM>. In various embodiments, a storage device <NUM> may include a storage device controller <NUM> and one or more memory chips <NUM> that each comprise any suitable number of memory partitions <NUM>.

In various embodiments, a memory partition <NUM> may include a 3D crosspoint memory array. In some embodiments, a 3D crosspoint memory array may comprise a transistor-less (e.g., at least with respect to the data storage elements of the memory) stackable crosspoint architecture in which memory cells sit at the intersection of row address lines and column address lines arranged in a grid.

CPU <NUM> comprises a processor <NUM>, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, an SOC, or other device to execute code (e.g., software instructions). Processor <NUM>, in the depicted embodiment, includes two processing elements (cores 114A and 114B in the depicted embodiment), which may include asymmetric processing elements or symmetric processing elements. However, a processor may include any number of processing elements that may be symmetric or asymmetric. CPU <NUM> may be referred to herein as a host computing device (though a host computing device may be any suitable computing device operable to issue memory access commands to a storage device <NUM>).

In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

A core <NUM> (e.g., 114A or 114B) may refer to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. A hardware thread may refer to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.

In various embodiments, the processing elements may also include one or more arithmetic logic units (ALUs), floating point units (FPUs), caches, instruction pipelines, interrupt handling hardware, registers, or other hardware to facilitate the operations of the processing elements.

I/O controller <NUM> is an integrated I/O controller that includes logic for communicating data between CPU <NUM> and I/O devices. In other embodiments, the I/O controller <NUM> may be on a different chip from the CPU <NUM>. I/O devices may refer to any suitable devices capable of transferring data to and/or receiving data from an electronic system, such as CPU <NUM>. For example, an I/O device may comprise an audio/video (A/V) device controller such as a graphics accelerator or audio controller; a data storage device controller, such as a magnetic storage disk or optical storage disk controller; a wireless transceiver; a network processor; a network interface controller; or a controller for another input device such as a monitor, printer, mouse, keyboard, or scanner; or other suitable device. In a particular embodiment, an I/O device may comprise a storage device <NUM> coupled to the CPU <NUM> through I/O controller <NUM>.

An I/O device may communicate with the I/O controller <NUM> of the CPU <NUM> using any suitable signaling protocol, such as peripheral component interconnect (PCI), PCI Express (PCIe), Universal Serial Bus (USB), Serial Attached SCSI (SAS), Serial ATA (SATA), Fibre Channel (FC), IEEE <NUM>, IEEE <NUM>, or other current or future signaling protocol. In particular embodiments, I/O controller <NUM> and an associated I/O device may communicate data and commands in accordance with a logical device interface specification such as Non-Volatile Memory Express (NVMe) (e.g., as described by one or more of the specifications available at www. nvmexpress. org/specifications/) or Advanced Host Controller Interface (AHCI) (e.g., as described by one or more AHCI specifications such as Serial ATA AHCI: Specification, Rev. <NUM> available at http://www. com/content/www/us/en/io/serial-ata/serial-ata-ahci-spec-rev1-<NUM>-<NUM>. In various embodiments, I/O devices coupled to the I/O controller <NUM> may be located off-chip (e.g., not on the same chip as CPU <NUM>) or may be integrated on the same chip as the CPU <NUM>.

CPU memory controller <NUM> is an integrated memory controller that controls the flow of data going to and from one or more system memory devices <NUM>. CPU memory controller <NUM> may include logic operable to read from a system memory device <NUM>, write to a system memory device <NUM>, or to request other operations from a system memory device <NUM>. In various embodiments, CPU memory controller <NUM> may receive write requests from cores <NUM> and/or I/O controller <NUM> and may provide data specified in these requests to a system memory device <NUM> for storage therein. CPU memory controller <NUM> may also read data from a system memory device <NUM> and provide the read data to I/O controller <NUM> or a core <NUM>. During operation, CPU memory controller <NUM> may issue commands including one or more addresses of the system memory device <NUM> in order to read data from or write data to memory (or to perform other operations). In some embodiments, CPU memory controller <NUM> may be implemented on the same chip as CPU <NUM>, whereas in other embodiments, CPU memory controller <NUM> may be implemented on a different chip than that of CPU <NUM>. I/O controller <NUM> may perform similar operations with respect to one or more storage devices <NUM>.

The CPU <NUM> may also be coupled to one or more other I/O devices through external I/O controller <NUM>. In a particular embodiment, external I/O controller <NUM> may couple a storage device <NUM> to the CPU <NUM>. External I/O controller <NUM> may include logic to manage the flow of data between one or more CPUs <NUM> and I/O devices. In particular embodiments, external I/O controller <NUM> is located on a motherboard along with the CPU <NUM>. The external I/O controller <NUM> may exchange information with components of CPU <NUM> using point-to-point or other interfaces.

A system memory device <NUM> may store any suitable data, such as data used by processor <NUM> to provide the functionality of computer system <NUM>. For example, data associated with programs that are executed or files accessed by cores <NUM> may be stored in system memory device <NUM>. Thus, a system memory device <NUM> may include a system memory that stores data and/or sequences of instructions that are executed or otherwise used by the cores <NUM>. In various embodiments, a system memory device <NUM> may store temporary data, persistent data (e.g., a user's files or instruction sequences) that maintains its state even after power to the system memory device <NUM> is removed, or a combination thereof. A system memory device <NUM> may be dedicated to a particular CPU <NUM> or shared with other devices (e.g., one or more other processors or other devices) of computer system <NUM>.

In various embodiments, a system memory device <NUM> may include a memory comprising any number of memory partitions, a memory device controller, and other supporting logic (not shown). A memory partition may include non-volatile memory and/or volatile memory.

Non-volatile memory is a storage medium that does not require power to maintain the state of data stored by the medium, thus non-volatile memory may have a determinate state even if power is interrupted to the device housing the memory. Nonlimiting examples of nonvolatile memory may include any or a combination of: 3D crosspoint memory, phase change memory (e.g., memory that uses a chalcogenide glass phase change material in the memory cells), ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM) ovonic memory, anti-ferroelectric memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), a memristor, single or multi-level phase change memory (PCM), Spin Hall Effect Magnetic RAM (SHE-MRAM), and Spin Transfer Torque Magnetic RAM (STTRAM), a resistive memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory.

Volatile memory is a storage medium that requires power to maintain the state of data stored by the medium (thus volatile memory is memory whose state (and therefore the data stored on it) is indeterminate if power is interrupted to the device housing the memory). Dynamic volatile memory requires refreshing the data stored in the device to maintain state. One example of dynamic volatile memory includes DRAM (dynamic random access memory), or some variant such as synchronous DRAM (SDRAM). A memory subsystem as described herein may be compatible with a number of memory technologies, such as DDR3 (double data rate version <NUM>, original release by JEDEC (Joint Electronic Device Engineering Council) on June <NUM>, <NUM>, currently on release <NUM>), DDR4 (DDR version <NUM>, JESD79-<NUM> initial specification published in September <NUM> by JEDEC), DDR4E (DDR version <NUM>, extended, currently in discussion by JEDEC), LPDDR3 (low power DDR version <NUM>, JESD209-3B, Aug <NUM> by JEDEC), LPDDR4 (LOW POWER DOUBLE DATA RATE (LPDDR) version <NUM>, JESD209-<NUM>, originally published by JEDEC in August <NUM>), WIO2 (Wide I/O <NUM> (WideIO2), JESD229-<NUM>, originally published by JEDEC in August <NUM>), HBM (HIGH BANDWIDTH MEMORY DRAM, JESD235, originally published by JEDEC in October <NUM>), DDR5 (DDR version <NUM>, currently in discussion by JEDEC), LPDDR5, originally published by JEDEC in January <NUM>, HBM2 (HBM version <NUM>), originally published by JEDEC in January <NUM>, or others or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

A storage device <NUM> may store any suitable data, such as data used by processor <NUM> to provide functionality of computer system <NUM>. For example, data associated with programs that are executed or files accessed by cores 114A and 114B may be stored in storage device <NUM>. Thus, in some embodiments, a storage device <NUM> may store data and/or sequences of instructions that are executed or otherwise used by the cores 114A and 114B. In various embodiments, a storage device <NUM> may store persistent data (e.g., a user's files or software application code) that maintains its state even after power to the storage device <NUM> is removed. A storage device <NUM> may be dedicated to CPU <NUM> or shared with other devices (e.g., another CPU or other device) of computer system <NUM>.

In the embodiment depicted, storage device <NUM> includes a storage device controller <NUM> and four memory chips <NUM> each comprising four memory partitions <NUM> operable to store data, however, a storage device may include any suitable number of memory chips each having any suitable number of memory partitions. A memory partition <NUM> includes a plurality of memory cells operable to store data. The cells of a memory partition <NUM> may be arranged in any suitable fashion, such as in rows (e.g., wordlines) and columns (e.g., bitlines), three dimensional structures, sectors, or in other ways. In various embodiments, the cells may be logically grouped into banks, blocks, subblocks, wordlines, pages, frames, bytes, slices, or other suitable groups. In various embodiments, a memory partition <NUM> may include any of the volatile or non-volatile memories listed above or other suitable memory. In a particular embodiment, each memory partition <NUM> comprises one or more 3D crosspoint memory arrays. 3D crosspoint arrays are described in more detail in connection with the following figures.

In various embodiments, storage device <NUM> may comprise a disk drive (e.g., a solid state drive); a memory card; a Universal Serial Bus (USB) drive; a Dual In-line Memory Module (DIMM), such as a Non-Volatile DIMM (NVDIMM); storage integrated within a device such as a smartphone, camera, or media player; or other suitable mass storage device.

In a particular embodiment, one or more memory chips <NUM> are embodied in a semiconductor package. In various embodiments, a semiconductor package may comprise a casing comprising one or more semiconductor chips (also referred to as dies). A package may also comprise contact pins or leads used to connect to external circuits. In various embodiments, a memory chip may include one or more memory partitions <NUM>.

Accordingly, in some embodiments, storage device <NUM> may comprise a package that includes a plurality of chips that each include one or more memory partitions <NUM>. However, a storage device <NUM> may include any suitable arrangement of one or more memory partitions and associated logic in any suitable physical arrangement. For example, memory partitions <NUM> may be embodied in one or more different physical mediums, such as a circuit board, semiconductor package, semiconductor chip, disk drive, other medium, or any combination thereof.

System memory device <NUM> and storage device <NUM> may comprise any suitable types of memory and are not limited to a particular speed, technology, or form factor of memory in various embodiments. For example, a storage device <NUM> may be a disk drive (such as a solid-state drive), memory integrated with a computing device (e.g., memory integrated on a circuit board of the computing device), a memory module (e.g., a dual in-line memory module) that may be inserted in a memory socket, or other type of storage device. Similarly, system memory <NUM> may have any suitable form factor. Moreover, computer system <NUM> may include multiple different types of storage devices.

System memory device <NUM> or storage device <NUM> may include any suitable interface to communicate with CPU memory controller <NUM> or I/O controller <NUM> using any suitable communication protocol such as a DDR-based protocol, PCI, PCIe, USB, SAS, SATA, FC, System Management Bus (SMBus), or other suitable protocol. In some embodiments, a system memory device <NUM> or storage device <NUM> may also include a communication interface to communicate with CPU memory controller <NUM> or I/O controller <NUM> in accordance with any suitable logical device interface specification such as NVMe, AHCI, or other suitable specification. In particular embodiments, system memory device <NUM> or storage device <NUM> may comprise multiple communication interfaces that each communicate using a separate protocol with CPU memory controller <NUM> and/or I/O controller <NUM>.

Storage device controller <NUM> may include logic to receive requests from CPU <NUM> (e.g., via an interface that communicates with CPU memory controller <NUM> or I/O controller <NUM>), cause the requests to be carried out with respect to the memory chips <NUM>, and provide data associated with the requests to CPU <NUM> (e.g., via CPU memory controller <NUM> or I/O controller <NUM>). Storage device controller <NUM> may also be operable to detect and/or correct errors encountered during memory operations via an error correction code (ECC engine). In various embodiments, controller <NUM> may also monitor various characteristics of the storage device <NUM> such as the temperature or voltage and report associated statistics to the CPU <NUM>. Storage device controller <NUM> can be implemented on the same circuit board or device as the memory chips <NUM> or on a different circuit board or device. For example, in some environments, storage device controller <NUM> may be a centralized storage controller that manages memory operations for multiple different storage devices <NUM> of computer system <NUM>.

In various embodiments, the storage device <NUM> also includes program control logic <NUM> which is operable to control the programming sequence performed when data is written to or read from a memory chip <NUM>. In various embodiments, program control logic <NUM> may provide the various voltages (or information indicating which voltages should be provided) that are applied to memory cells during the programming and/or reading of data (or perform other operations associated with read or program operations), perform error correction, and perform other suitable functions.

In various embodiments, the program control logic <NUM> may be integrated on the same chip as the storage device controller <NUM> or on a different chip. In the depicted embodiment, the program control logic <NUM> is shown as part of the storage device controller <NUM>, although in various embodiments, all or a portion of the program control logic <NUM> may be separate from the storage device controller <NUM> and communicably coupled to the storage device controller <NUM>. For example, all or a portion of the program control logic <NUM> described herein may be located on a memory chip <NUM>. In various embodiments, reference herein to a "controller" may refer to any suitable control logic, such as storage device controller <NUM>, chip controller <NUM>, or a partition controller. In some embodiments, reference to a controller may contemplate logic distributed on multiple components, such as logic of a storage device controller <NUM>, chip controller <NUM>, and/or a partition controller.

In various embodiments, storage device controller <NUM> may receive a command from a host device (e.g., CPU <NUM>), determine a target memory chip for the command, and communicate the command to a chip controller <NUM> of the target memory chip. In some embodiments, the storage device controller <NUM> may modify the command before sending the command to the chip controller <NUM>.

The chip controller <NUM> may receive a command from the storage device controller <NUM> and determine a target memory partition <NUM> for the command. The chip controller <NUM> may then send the command to a controller of the determined memory partition <NUM>. In various embodiments, the chip controller <NUM> may modify the command before sending the command to the controller of the partition <NUM>.

In some embodiments, all or some of the elements of system <NUM> are resident on (or coupled to) the same circuit board (e.g., a motherboard). In various embodiments, any suitable partitioning between the elements may exist. For example, the elements depicted in CPU <NUM> may be located on a single die (e.g., on-chip) or package or any of the elements of CPU <NUM> may be located off-chip or off-package. Similarly, the elements depicted in storage device <NUM> may be located on a single chip or on multiple chips. In various embodiments, a storage device <NUM> and a computing host (e.g., CPU <NUM>) may be located on the same circuit board or on the same device and in other embodiments the storage device <NUM> and the computing host may be located on different circuit boards or devices.

The components of system <NUM> may be coupled together in any suitable manner. For example, a bus may couple any of the components together. A bus may include any known interconnect, such as a multi-drop bus, a mesh interconnect, a ring interconnect, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a Gunning transceiver logic (GTL) bus. In various embodiments, an integrated I/O subsystem includes point-to-point multiplexing logic between various components of system <NUM>, such as cores <NUM>, one or more CPU memory controllers <NUM>, I/O controller <NUM>, integrated I/O devices, direct memory access (DMA) logic (not shown), etc. In various embodiments, components of computer system <NUM> may be coupled together through one or more networks comprising any number of intervening network nodes, such as routers, switches, or other computing devices. For example, a computing host (e.g., CPU <NUM>) and the storage device <NUM> may be communicably coupled through a network.

Although not depicted, system <NUM> may use a battery and/or power supply outlet connector and associated system to receive power, a display to output data provided by CPU <NUM>, or a network interface allowing the CPU <NUM> to communicate over a network. In various embodiments, the battery, power supply outlet connector, display, and/or network interface may be communicatively coupled to CPU <NUM>. Other sources of power can be used such as renewable energy (e.g., solar power or motion based power).

<FIG> illustrates a detailed exemplary view of the memory partition <NUM> of <FIG> in accordance with certain embodiments. In one embodiment, a memory partition <NUM> may include 3D crosspoint memory which may include phase change memory or other suitable memory types. In some embodiments, a 3D crosspoint memory array <NUM> may comprise a transistor-less (e.g., at least with respect to the data storage elements of the memory) stackable crosspoint architecture in which memory cells <NUM> sit at the intersection of row address lines and column address lines arranged in a grid. The row address lines <NUM> and column address lines <NUM>, called wordlines (WLs) and bitlines (BLs), respectively, cross in the formation of the grid and each memory cell <NUM> is coupled between a WL and a BL where the WL and BL cross (e.g., at a crosspoint). At the point of a crossing, the WL and BL may be located at different vertical planes such that the WL crosses over the BL but does not physically touch the BL. As described above, the architecture may be stackable, such that a wordline may cross over a bitline located beneath the wordline and another bitline for another memory cell located above the wordline. It should be noted that row and column are terms of convenience used to provide a qualitative description of the arrangement of WLs and BLs in crosspoint memory. In various embodiments, the cells of the 3D crosspoint memory array may be individually addressable. In some embodiments, bit storage may be based on a change in bulk resistance of a 3D crosspoint memory cell.

<FIG> illustrates a memory partition in accordance with certain embodiments. In the embodiment of <FIG>, a memory partition <NUM> includes memory partition controller <NUM>, wordline control logic <NUM>, bitline control logic <NUM>, and memory array <NUM>. A host device (e.g., CPU <NUM>) may provide read and/or write commands including memory address(es) and/or associated data to memory partition <NUM> (e.g., via storage device controller <NUM> and chip controller <NUM>) and may receive read data from memory partition <NUM> (e.g., via the chip controller <NUM> and storage device controller <NUM>). Similarly, storage device controller <NUM> may provide host-initiated read and write commands or device-initiated read and write commands including memory addresses to memory partition <NUM> (e.g., via chip controller <NUM>). Memory partition controller <NUM> (in conjunction with wordline control logic <NUM> and bitline control logic <NUM>) is configured to perform memory access operations, e.g., reading one or more target memory cells and/or writing to one or more target memory cells.

Memory array <NUM> corresponds to at least a portion of a 3D crosspoint memory (e.g., that may include phase change memory cells or other suitable memory cells) and includes a plurality of wordlines <NUM>, a plurality of bitlines <NUM> and a plurality of memory cells, e.g., memory cells <NUM>. Each memory cell is coupled between a wordline ("WL") and a bitline ("BL") at a crosspoint of the WL and the BL.

Memory partition controller <NUM> may manage communications with chip controller <NUM> and/or storage device controller <NUM>. In a particular embodiment, memory partition controller <NUM> may analyze one or more signals received from another controller to determine whether a command sent via a bus is to be consumed by the memory partition <NUM>. For example, controller <NUM> may analyze an address of the command and/or a value on an enable signal line to determine whether the command applies to the memory partition <NUM>. Controller <NUM> may be configured to identify one or more target WLs and/or BLs associated with a received memory address (this memory address may be a separate address from the memory partition address that identifies the memory partition <NUM>, although in some embodiments a portion of an address field of a command may identify the memory partition while another portion of the address field may identify one or more WLs and/or BLs). Memory partition controller <NUM> may be configured to manage operations of WL control logic <NUM> and BL control logic <NUM> based, at least in part, on WL and/or BL identifiers included in a received command. Memory partition controller <NUM> may include memory partition controller circuitry <NUM>, and a memory controller interface <NUM>. Memory controller interface <NUM>, although shown as a single block in <FIG>, may include a plurality of interfaces, for example a separate interface for each of the WL control logic <NUM> and the BL control logic <NUM>.

WL control logic <NUM> includes WL switch circuitry <NUM> and sense circuitry <NUM>. WL control logic <NUM> is configured to receive target WL address(es) from memory partition controller <NUM> and to select one or more WLs for reading and/or writing operations. For example, WL control logic <NUM> may be configured to select a target WL by coupling a WL select bias voltage to the target WL. WL control logic <NUM> may be configured to deselect a WL by decoupling the target WL from the WL select bias voltage and/or by coupling a WL deselect bias voltage (e.g., a neutral bias voltage) to the WL. WL control logic <NUM> may be coupled to a plurality of WLs <NUM> included in memory array <NUM>. Each WL may be coupled to a number of memory cells corresponding to a number of BLs <NUM>. WL switch circuitry <NUM> may include a plurality of switches, each switch configured to couple (or decouple) a respective WL, e.g., WL 215A, to a WL select bias voltage to select the respective WL 215A.

BL control logic <NUM> includes BL switch circuitry <NUM>. In some embodiments, BL control logic <NUM> may also include sense circuitry, e.g., sense circuitry <NUM>. BL control logic <NUM> is configured to select one or more BLs for reading and/or writing operations. BL control logic <NUM> may be configured to select a target BL by coupling a BL select bias voltage to the target BL. BL control logic <NUM> may be configured to deselect a BL by decoupling the target BL from the BL select bias voltage and/or by coupling a BL deselect bias voltage (e.g., a neutral bias voltage) to the BL. BL switch circuitry <NUM> is similar to WL switch circuitry <NUM> except BL switch circuitry <NUM> is configured to couple the BL select bias voltage to a target BL.

Sense circuitry <NUM> is configured to detect the state of one or more sensed memory cells <NUM> (e.g., via the presence or absence of a snap back event during a sense interval), e.g., during a read operation. Sense circuitry <NUM> is configured to provide a logic level output related to the result of the read operation to, e.g., memory partition controller <NUM>.

As an example, in response to a signal from memory partition controller <NUM>, WL control logic <NUM> and BL control logic <NUM> may be configured to select a target memory cell, e.g., memory cell 207A, for a read operation by coupling WL 215A to WL select bias voltage and BL 217A to BL select bias voltage as well as coupling the other WLs and BLs to respective deselect bias voltages. One or both of sense circuitries <NUM> may then be configured to monitor WL 215A and/or BL 217A for a sensing interval in order to determine the state of the memory cell 207A.

Thus, WL control logic <NUM> and/or BL control logic <NUM> may be configured to select a target memory cell for a read operation, initiate the read operation, sense the selected memory cell (e.g., for a snap back event) in a sensing interval, and provide the result of the sensing to, e.g., memory partition controller <NUM>.

In a particular embodiment, the sense circuitry <NUM> may include a WL load connected to a WL electrode or gate, and a BL load connected to a BL electrode or gate. When a particular wordline and bitline are selected in the array, a difference between WL load or WL voltage and the BL voltage corresponds to a read VDM. VDM may induce a current (icell) in the memory cell 207A dependent on a program state of the memory cell. A comparator such as a sense amplifier may compare icell with a reference current in order to read a logic state of the memory cell. In this manner, an output of the sense amplifier/comparator may be indicative of a state of the target memory cell. A latch may be coupled to the output of the comparator to store the output of the read operation.

For each matrix of arrays, there may be a number of sense amplifiers provided, with the sense circuitry <NUM> able to process up to a maximum number of sensed bits, such as <NUM> bits, from the sense amplifiers at one time. Hence, in one embodiment, <NUM> memory cells may be sensed at one time by sense amplifiers of the sense circuitry <NUM>.

<FIG> illustrates a memory cell <NUM> coupled to access circuitry <NUM> in accordance with certain embodiments. The memory cell <NUM> includes a storage material <NUM> between access lines <NUM> and <NUM>. The access lines <NUM>, <NUM> electrically couple the memory cell <NUM> with access circuitry <NUM> that writes to and reads the memory cell <NUM>. For example, access circuitry <NUM> may include WL switch circuitry <NUM>, BL switch circuitry <NUM>, sense circuitry <NUM>, or other suitable circuitry.

In one embodiment, storage material <NUM> includes a self-selecting material that exhibits memory effects. A self-selecting material is a material that enables selection of a memory cell in an array without requiring a separate selector element. Thus, storage material <NUM> may represent a "selector/storage material. " A material exhibits memory effects if circuitry (e.g., <NUM>) for accessing memory cells can cause the material to be in one of multiple states (e.g., via a write operation) and later determine the programmed state (e.g., via a read operation). Access circuitry <NUM> can store information in the memory cell <NUM> by causing the storage material <NUM> to be in a particular state. The storage material <NUM> can include, for example, a chalcogenide material or other material capable of functioning as both a storage element and a selector, to enable addressing a specific memory cell and determining what the state of the memory cell is. Thus, in one embodiment, the memory cell <NUM> is a self-selecting memory cell that includes a single layer of material that acts as both a selector element to select the memory cell and a memory element to store a logic state. In the embodiment depicted, each memory cell <NUM> is a two-terminal device (i.e., the memory cell <NUM> has two electrodes to receive control signals sufficient to write to and read from the memory cell <NUM>).

In other embodiments, each memory cell (e.g., <NUM>) includes a memory element configured to store information and a separate memory cell select device (e.g., selector) coupled to the memory element. Select devices may include ovonic threshold switches, diodes, bipolar junction transistors, field-effect transistors, etc. In one embodiment, a first chalcogenide layer may comprise the memory element and a second chalcogenide layer may comprise the select device.

The storage material <NUM> may include any suitable material programmable to a plurality of states. In some embodiments, the storage material <NUM> may include a chalcogenide material comprising a chemical compound with at least one chalcogen ion, that is, an element from group <NUM> of the periodic table. For example, the storage material <NUM> may include one or more of: sulfur (S), selenium (Se), or tellurium (Te). Additionally or alternatively, in various embodiments, storage material <NUM> may comprise germanium (Ge), antimony (Sb), bismuth (Bi), lead (Pb), tin (Sn), indium (In), silver (Ag), arsenic (As), phosphorus (P), molybdenum (Mo), gallium (Ga), aluminum (Al), oxygen (O), nitrogen (N), chromium (Cr), gold (Au), niobium (Nb), palladium (Pd), cobalt (Co), vanadium (V), nickel (Ni), platinum (Pt), titanium (Ti), tungsten (W), tantalum (Ta), or other materials. In various examples, the storage material <NUM> may include one or more chalcogenide materials such as such as Te-Se, Ge-Te, In-Se, Sb-Te, Ta-Sb-Te, As-Te, As-Se, Al-Te, As-Se-Te, Ge-Sb-Te, Ge-As-Se, Te-Ge-As, V-Sb-Se, Nb-Sb-Se, In-Sb-Te, In-Se-Te, Te-Sn-Se, V-Sb-Te, Se-Te-Sn, Ge-Se-Ga, Mo-Sb-Se, Cr-Sb-Se, Ta-Sb-Se, Bi-Se-Sb, Mo-Sb-Te, Ge-Bi-Te, W-Sb-Se, Ga-Se-Te, Ge-Te-Se, Cr-Sb-Te, Sn-Sb-Te, W-Sb-Te, As-Sb-Te, Ge-Te-Ti, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Se-Te-In, As-Ge-Sb-Te, Se-As-Ge-In, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn-Pt, Si-Ge-As-Se, In-Sn-Sb-Te, Ge-Se-Te-Si, Si-Te-As-Ge, Ag-In-Sb-Te, Ge-Se-Te-In-Si, or Se-As-Ge-Si-In. In other various examples, storage material <NUM> may include other materials capable of being programmed to one of multiple states, such as Ge-Sb, Ga-Sb, In-Sb, Sn-Sb-Bi, or In-Sb-Ge. One or more elements in a chalcogenide material (or other material used as storage material <NUM>) may be dopants. For example, the storage material <NUM> may include dopants such as: aluminum (Al), oxygen (O), nitrogen (N), silicon (Si), carbon (C), boron (B), zirconium (Zr), hafnium (Hf), or a combination thereof. In some embodiments, the chalcogenide material (or other material used as storage material <NUM>) may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms. The storage material <NUM> may include other materials or dopants not explicitly listed. In some examples, the storage material (such as any of the materials described above) is a phase change material. In other examples, the storage material <NUM> is not a phase change material, e.g., can be in one or multiple stable states (or transition between stable states) without a change in phase.

In some embodiments, a selector element coupled to storage material (e.g., in non-self-selecting memory cells) may also include a chalcogenide material. A selector device having a chalcogenide material can sometimes be referred to as an Ovonic Threshold Switch (OTS). An OTS may include a chalcogenide composition including any one of the chalcogenide alloy systems described above for the storage element and may further include an element that can suppress crystallization, such as arsenic (As), nitrogen (N), or carbon (C), to name a few. Examples of OTS materials include Te-As-Ge-Si, Ge-Te-Pb, Ge-Se-Te, Al-As-Te, Se-As-Ge-Si, Se-As-Ge-C, Se-Te-Ge-Si, Ge-Sb-Te-Se, Ge-Bi-Te-Se, Ge-As-Sb-Se, Ge-As-Bi-Te, and Ge-As-Bi-Se, among others.

In some embodiments, an element from column III of the periodic table ("Group III element") may be introduced into a chalcogenide material composition to limit the presence of another material (e.g., Ge) in the selector device. For example, a Group III element may replace some or all of the other material (e.g., Ge) in the composition of the selector device. In some embodiments, a Group III element may form a stable, Group III element-centered tetrahedral bond structure with other elements (e.g., Se, As, and/or Si). Incorporating a Group III element into the chalcogenide material composition may stabilize the selector device to allow for technology scaling and increased cross point technology development (e.g., three-dimensional cross point architectures, RAM deployments, storage deployments, or the like).

In one embodiment, each selector device comprises a chalcogenide material having a composition of Se, As, and at least one of B, Al, Ga, In, and Tl. In some cases, the composition of the chalcogenide material comprises Ge or Si, or both.

In one example, the storage material is capable of switching between two or more stable states without changing phase (in other examples the storage material may switch between two stable states by changing phase). In one such embodiment, the access circuitry <NUM> programs the memory cell <NUM> by applying one or more program pulses (e.g., voltage or current pulses) with a particular polarity to cause the storage material <NUM> to be in the desired stable state. In one embodiment, the access circuitry <NUM> applies program pulses to the access lines <NUM>, <NUM> (which may correspond to a bitline and a wordline) to write to or read the memory cell <NUM>. In one embodiment, to write to the memory cell <NUM>, the access circuitry applies one or more program pulses with particular magnitudes, polarities, and pulse widths to the access lines <NUM>, <NUM> to program the memory cell <NUM> to the desired stable state, which can both select memory cell <NUM> and program memory cell <NUM>. In various embodiments below, programming states are depicted as being associated with a single programming pulse, however, the single programming pulse may also be equivalent to a series of programming pulses that have the effective characteristics of the single programming pulse (e.g., a width of the single programming pulse may be equivalent to the sum of the widths of a series of shorter programming pulses).

In one embodiment, programming the memory cell <NUM> causes the memory cell <NUM> to "threshold" or undergo a "threshold event. " When a memory cell thresholds (e.g., during application of a program pulse), the memory cell undergoes a physical change that causes the memory cell to exhibit a certain threshold voltage in response to the application of a subsequent voltage (e.g., through application of a read pulse with a particular voltage magnitude and polarity). Programming the memory cell <NUM> can therefore involve applying a program pulse of a given polarity to induce a programming threshold event and application of current for a duration of time, which causes the memory cell <NUM> to exhibit a particular threshold voltage at a subsequent reading voltage of a same or different polarity. In one such embodiment, the storage material <NUM> is a self-selecting material that can be programmed by inducing a threshold event.

During a read operation, access circuitry <NUM> may determine a threshold voltage of a memory cell based on electrical responses to a read voltage applied to the memory cell. Detecting electrical responses can include, for example, detecting a voltage drop (e.g., a threshold voltage) across terminals of a given memory cell of the array or current through the given memory cell. In some cases, detecting a threshold voltage for a memory cell can include determining that the cell's threshold voltage is lower than or higher than a reference voltage, for example a read voltage. The access circuitry <NUM> can determine the logic state of the memory cell <NUM> based on the electrical response of the memory cell to the read voltage pulse.

As mentioned above, the access lines <NUM>, <NUM> electrically couple the memory cell <NUM> with circuitry <NUM>. The access lines <NUM>, <NUM> can be referred to as a bitline and wordline, respectively. The wordline is for accessing a particular word in a memory array and the bitline is for accessing a particular bit in the word. The access lines <NUM>, <NUM> can be composed of one or more metals including: Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicide nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN, or any other suitable electrically conductive material.

In one embodiment, electrodes <NUM> are disposed between storage material <NUM> and access lines <NUM>, <NUM>. Electrodes <NUM> electrically couple access lines <NUM>, <NUM> to storage material <NUM>. Electrodes <NUM> can be composed of one or more conductive and/or semiconductive materials such as, for example: carbon (C), carbon nitride (CxNy); n-doped polysilicon and p-doped polysilicon; metals including, Al, Cu, Ni, Mo, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicides nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; conductive metal oxides including RuO<NUM>, or other suitable conductive materials. In one embodiment, conductive wordline layer can include any suitable metal including, for example, metals including, Al, Cu, Ni, Mo, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicides nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN, or another suitable electrically conductive material.

The memory cell <NUM> is one example of a memory cell that may be used as a multi-level cell (storing more than a single logical bit). Other embodiments can include memory cells having additional or different layers of material than illustrated in <FIG> (e.g., a selection device between the access line <NUM> and the storage element, a thin dielectric material between the storage material and access lines, or other suitable configuration).

<FIG> is an isometric view of portions of a 3D crosspoint memory stack according to one embodiment. The specific layers are merely examples and will not be described in detail here. Stack <NUM> is built on substrate structure <NUM>, such as silicon or other semiconductor. Stack <NUM> includes multiple pillars <NUM> as memory cell stacks of memory cells <NUM> or <NUM>. In the diagram of stack <NUM>, it will be observed that the WLs and BLs are orthogonal to each other, and traverse or cross each other in a cross-hatch pattern. A crosspoint memory structure includes at least one memory cell in a stack between layers of BL and WL. As illustrated, wordlines (WL) <NUM> are in between layers of elements, and bitlines (BL) <NUM> are located at the top of the circuit. Such a configuration is only an example, and the BL and WL structure can be swapped. Thus, in one representation of stack <NUM>, the WLs can be the metal structures labeled as <NUM>, and the BLs can be the metal structures labeled as <NUM>. Different architectures can use different numbers of stacks of devices, and different configuration of WLs and BLs. It will be understood that the space between pillars <NUM> is typically an insulator.

Substrate structure <NUM>, such as a silicon substrate, may include control circuitry therein (not shown), such as control circuitry including transistors, row decoders, page buffers, etc. The control circuitry of substrate structure <NUM> may include, for example, a memory partition controller such as memory partition controller <NUM>, BL control logic such as BL control logic <NUM>, and WL control logic such as WL control logic <NUM> of <FIG>, access circuitry <NUM>, or other suitable control circuitry. Each row of WLs <NUM> extending in the Y direction, the corresponding cells as coupled to corresponding BLs, would define a memory array, and may correspond to a memory array such as memory array <NUM> of <FIG>.

Referring now to <FIG>, in one embodiment, a computer system <NUM> includes a microcontroller <NUM> connected to several memory dies <NUM>. Each memory die <NUM> includes a chip controller <NUM> and several partitions <NUM>. Each chip controller <NUM> includes a buffer <NUM>, a read controller <NUM>, and a write controller <NUM>. In the illustrative embodiment, the microcontroller <NUM> is connected to the memory die by a command bus <NUM> and a data bus <NUM>.

The microcontroller <NUM> may be any suitable microcontroller, such as a stand-alone microcontroller or a microcontroller <NUM> integrated into another component. For example, the microcontroller <NUM> may be included in the CPU memory controller <NUM>, the storage device controller <NUM>, a system memory device <NUM>, etc. The microcontroller <NUM> may be implemented as hardware, software, firmware, or a combination thereof. In some embodiments, the microcontroller <NUM> may be embodied as circuitry or collection of electrical devices.

The memory die <NUM> may be any suitable memory die or chip, such as the memory chip <NUM> described above. In the illustrative embodiment, the memory die <NUM> is a phase-change-based memory die. The chip controller <NUM> may be any suitable chip controller, such as the chip controller <NUM>. The chip controller <NUM> may be a stand-alone controller or may be integrated into another component. For example, in the illustrative embodiment, the chip controller <NUM> is integrated into the memory die <NUM>. In one embodiment, the chip controller <NUM> may be embodied as the chip controller <NUM>. More generally, some or all of the chip controller <NUM> may include or be a part of any suitable component. For example, the chip controller <NUM> may be included in the CPU memory controller <NUM>, the storage device controller <NUM>, a system memory device <NUM>, etc. In some embodiments, some or all of the chip controller <NUM> may be included in the microcontroller <NUM>. The chip controller <NUM> may be implemented as hardware, software, firmware, or a combination thereof. In some embodiments, the chip controller <NUM> may be embodied as circuitry or collection of electrical devices. The partitions <NUM> in the memory die <NUM> may be similar to the partitions <NUM> described above. Each memory die <NUM> may have any suitable number of partitions <NUM>, such as <NUM>-<NUM> partitions <NUM>. In the illustrative embodiment, each memory die <NUM> has a minimum average time period between memory write operations, which is greater than the minimum time between consecutive or burst memory operations that can be sent on the command bus <NUM>.

The buffer <NUM> may be embodied as any suitable volatile or non-volatile memory, such as DRAM, SDRAM, SRAM, etc. In the illustrative embodiment, the buffer <NUM> can be written faster than the partitions <NUM> can be written. The buffer <NUM> may be able to store any suitable number of commands and corresponding data, such as <NUM>-<NUM> commands and data. In the illustrative embodiment, the buffer <NUM> may be able to store <NUM>-<NUM> commands and corresponding data. In some embodiments, the buffer <NUM> may be split into a command buffer and a data buffer. In other embodiments, data may be stored in the buffer <NUM> together with the corresponding command. In the illustrative embodiment, any slot in the buffer <NUM> may correspond to an operation on any partition <NUM>.

The read controller <NUM> and the write controller <NUM> are configured to control read and write operations on the partitions <NUM>, respectively. The read controller <NUM> and write controller <NUM> may be implemented as hardware, software, firmware, or a combination thereof. The read controller <NUM> and/or write controller <NUM> may be incorporated into or include any other suitable component, such as the microcontroller <NUM>. The read controller <NUM> may perform a read operation in any suitable amount of time, such as <NUM>-<NUM> nanoseconds.

The command bus <NUM> and data bus <NUM> may be any suitable bus, such as a point-to-point interconnect, a serial interconnect, a parallel bus, a differential bus, a Gunning transceiver logic (GTL) bus, etc..

In use, the microcontroller <NUM> determines memory read and write operations to be sent to the memory dies <NUM>. For example, the microcontroller <NUM> may receive memory operations from a CPU <NUM>, an external I/O controller <NUM>, a bus, etc. The microcontroller <NUM> is configured to order memory read and write operations in a manner that lead to a high efficiency in memory operations. In the illustrative embodiment, in order to send a memory operation to a memory die <NUM>, the microcontroller <NUM> must perform a rank switching operation, which may involve sending a preamble, performing on-die termination, synchronizing a delay-locked loop and/or phase interpolator, etc. The rank switching operation may take several clock cycles, such as <NUM>-<NUM> clock cycles, of a clock signal of the microcontroller <NUM>. In the illustrative embodiment, rank switching takes up to <NUM> clock cycles. The clock corresponding to the clock cycles could have any suitable frequency, such as <NUM> megahertz to <NUM> gigahertz. The illustrative microcontroller <NUM> can send data to only one memory die <NUM> at a time.

In order to avoid the penalty imposed by rank switching, the microcontroller <NUM> performs several operations with one die <NUM> before switching to another die <NUM>. The microcontroller <NUM> may send any suitable number of read and write operations to different partitions <NUM> in any suitable order. However, as discussed in more detail below in regard to the chip controller <NUM>, multiple consecutive memory write operations may need to be buffered on the buffer <NUM> before being completed. As such, the microcontroller <NUM> may ensure that the number of write operations sent in any given period of time will not overflow the buffer <NUM>. For example, the microcontroller <NUM> may have a counter that tracks the number of operations stored in the buffer <NUM> at any given time. The microcontroller <NUM> can increment to the counter every time it sends an operation to the memory die <NUM> and decrement the counter every time the memory die <NUM> performs a write operation, which, in the illustrative embodiment, are performed in a deterministic manner. The microcontroller <NUM> may determine a maximum number of consecutive memory write operations that the memory die <NUM> can handle. As the memory die <NUM> can perform memory write operations at the same time it is receiving them (albeit at a slower rate), the maximum number of consecutive memory writes may be more than the number of write operations that can be stored in the buffer <NUM>. As discussed in more detail below, in the illustrative embodiment, the memory die <NUM> can interleave read and write operations to different partitions <NUM> on the same die <NUM>. As such, the illustrative microcontroller <NUM> does not need to be concerned about ordering or interleaving of read operations to different partitions <NUM>.

In the illustrative embodiment, there is a minimum delay between a write operation to a partition <NUM> and a read operation from the same partition <NUM>. The delay may be any suitable value, such as <NUM>-<NUM>,<NUM> clock cycles. For example, in one embodiment, the delay is <NUM> clock cycles. It should be appreciated that the delay should be between the write operation to the partition <NUM>, which may be delayed relative to the write operation sent over the command bus <NUM> for write operations that are stored in the buffer <NUM> before execution. In the illustrative embodiment, the microcontroller <NUM> keeps track of when each write operation will be performed to each partition <NUM> and ensures that a read operation for that partition <NUM> will not be sent to the memory die <NUM> until after the minimum delay period has passed. In other embodiments, the microcontroller <NUM> may send read operations, and the chip controller <NUM> may delay the read operations until the minimum delay period has passed.

In the illustrative embodiment, the microcontroller <NUM> will never send a write operation to the chip controller <NUM> that will overflow the buffer <NUM>. In some embodiments, the microcontroller <NUM> may send a write operation that can overflow the buffer <NUM>, and the chip controller <NUM> can discard such an operation and, optionally, send an error to the microcontroller <NUM> to notify it of the buffer overflow.

In the illustrative embodiment, the microcontroller <NUM> sends commands over a command bus <NUM>, and the microcontroller <NUM> sends and receives data over a data bus <NUM>. In the illustrative embodiment, a fixed time after a command is sent on the command bus <NUM>, data corresponding to the command is sent on the data bus <NUM>. For example, a fixed time after the microcontroller <NUM> sends a read command to the memory die <NUM> on the command bus <NUM>, the memory die <NUM> sends the read data to the microcontroller <NUM> on the data bus <NUM>. Similarly, a fixed time after the microcontroller <NUM> sends a write command to the memory die <NUM> on the command bus <NUM>, the microcontroller <NUM> sends the write data to the die <NUM> on the data bus <NUM>.

In the illustrative embodiment, each command on the command bus takes the same amount of time. Each command may take any suitable amount of time, such as <NUM>-<NUM> clock cycles. In the illustrative embodiment, each command takes <NUM> clock cycles. In the illustrative embodiment, the slot for data transfer on the data bus <NUM> corresponding to each command on the command bus <NUM> is the same or less time than the corresponding command on the command bus <NUM>, thus allowing the data bus <NUM> to always provide data for the corresponding command on the command bus <NUM>. The data bus <NUM> may transfer any suitable amount of data for a given command, such as <NUM>-<NUM> bytes of data.

The chip controller <NUM> is configured to receive and process commands from the microcontroller <NUM>. In the illustrative embodiment, the chip controller <NUM> can pass read commands to the read controller <NUM>, which can perform reads on one or more partitions <NUM> without conflict with write operations performed on other partitions <NUM>. For example, a read controller <NUM> can perform a read operation on a partition <NUM> simultaneously with a write operation on a different partition <NUM>. The read controller <NUM> can then pass the read data back on the data bus <NUM> at the appropriate time.

For write operations, the chip controller <NUM> can check if the write buffer <NUM> is empty. If it is, then the chip controller <NUM> can give the write command to the write controller <NUM>, which can perform a write operation immediately (as long as the minimum amount of time has passed since the last write operation). If the write buffer <NUM> is not empty, then the chip controller <NUM> adds the write command to the buffer <NUM>. In the illustrative embodiment, the microcontroller <NUM> should ensure that there is always room in the write buffer <NUM> for any write operations sent to the memory die <NUM>. In other embodiments, the chip controller <NUM> may receive a write operation while the buffer <NUM> is full. In such embodiments, the chip controller <NUM> may, e.g., discard the new write operation, discard a previous write operation, send an error message to the microcontroller <NUM>, set an error flag, etc..

The write controller <NUM> is configured to process write commands. When the write controller <NUM> receives a write command (or retrieves a write command from the buffer), the write controller <NUM> checks if enough time has passed since the previous write operation on the memory die <NUM>. If it has, the write controller <NUM> performs the write operation on the memory die <NUM>. If it has not, the write controller <NUM> will wait until it is time to perform the next write operation. The write controller <NUM> may perform a write operation in any suitable amount of time, such as <NUM>-<NUM>,<NUM> nanoseconds.

In the illustrative embodiment, each write operation to the partitions <NUM> on a memory die <NUM> is separated by the same amount of time as one command on the command bus <NUM>. For example, each command on the command bus <NUM> may take <NUM> clock cycles, and the time between consecutive memory write operations to the partitions <NUM> may be <NUM> clock cycles. As such, on average, every other command on the command bus <NUM> can be a write command. More generally, the amount of time between consecutive memory write operations to the partitions <NUM> can be any suitable amount of time, such as <NUM>-<NUM> clock cycles. That amount of time between consecutive write operations represents the no-gap command issuance to the same rank or die. As the memory die <NUM> can store write operations in the buffer <NUM>, consecutive write commands on the command bus <NUM> can be sent without any gap between them (e.g., if each command takes <NUM> clock cycles, the time from starting one write command to the next can be <NUM> clock cycles).

Referring now to <FIG>, in use, a microcontroller <NUM> may perform a method <NUM> for controlling memory operations. The method <NUM> begins in block <NUM>, in which the microcontroller <NUM> receives memory operations to send to one or more memory dies <NUM>. The microcontroller <NUM> may receive memory operations from a CPU <NUM>, an external I/O controller <NUM>, a bus, etc..

In block <NUM>, the microcontroller <NUM> arranges the received memory operations. The microcontroller <NUM> is configured to order memory read and write operations in a manner that lead to a high efficiency in memory operations. In the illustrative embodiment, in order to avoid the penalty imposed by rank switching, the microcontroller <NUM> arranges the memory operations so that there will be several operations with one die <NUM> before switching to another die <NUM> in block <NUM>. The microcontroller <NUM> may send any suitable number of read and write operations to different partitions <NUM> in any suitable order. However, as discussed above, multiple consecutive memory write operations may need to be buffered on the buffer <NUM> before being completed. As such, the microcontroller <NUM> arrange memory operations based on the size and space available in the buffer <NUM> of the target memory dies <NUM> in block <NUM>. For example, the microcontroller <NUM> may have a counter that tracks the number of operations that are (or, for future operations being ordered, will be) stored in the buffer <NUM> at any given time. The microcontroller <NUM> can increment to the counter every time it sends an operation to the memory die <NUM> and decrement the counter every time the memory die <NUM> performs a write operation, which, in the illustrative embodiment, are performed in a deterministic manner.

In block <NUM>, the microcontroller <NUM> sends memory operations to the memory dies <NUM>. In the illustrative embodiment, the microcontroller <NUM> sends a memory command on a command bus <NUM> to a memory die <NUM> in block <NUM>. A predefined time later, the microcontroller <NUM> reads data from (for a read command) or writes data to (for a write command) the data bus <NUM> connected to the memory die <NUM>. The method <NUM> loops back to block <NUM> to receive additional memory operations to perform.

Referring now to <FIG>, in use, a memory die <NUM> may perform a method <NUM> for performing memory operations. The method <NUM> begins in block <NUM>, in which the memory die <NUM> receives a memory operation from the microcontroller <NUM>. The memory die <NUM> may receive a memory read command in block <NUM> and may receive a memory write command in block <NUM>. In the illustrative embodiment, the memory die <NUM> receives a memory command on a command bus <NUM>. For a write operation, the memory die <NUM> receives write data on a data bus <NUM>. In the illustrative embodiment, the memory die <NUM> may receive the write data on the data bus <NUM> at a predefined time relative to receiving the write command. In particular, in the illustrative embodiment, the write data is received at the same time relative to a write command as the read data is sent on the data bus relative to a read command (see block <NUM> below).

In block <NUM>, if the memory operation is a write operation, the method <NUM> proceeds to block <NUM>. In <NUM>, if the memory write buffer <NUM> is empty, the method <NUM> proceeds to block <NUM> to perform the memory write operation (after receiving the write data on the data bus <NUM> and if enough time has passed since the last memory write operation).

Referring back to block <NUM>, if the memory write buffer <NUM> is not empty, the method <NUM> proceeds to block <NUM>, in which the memory die <NUM> adds the memory operation to the memory write buffer. When the write data corresponding to the write command is received on the data bus, it is also stored in the buffer <NUM>.

In some embodiments, the memory die <NUM> always adds incoming write operations to the buffer <NUM>. In such embodiments, the memory die <NUM> pulls the next write operation from the buffer whenever enough time has passed since the last memory write operation.

Referring back to block <NUM>, if the memory operation is not a memory write operation, the method <NUM> proceeds to block <NUM>. In block <NUM>, the memory die <NUM> performs the requested memory read operation. In the illustrative embodiment, the memory die <NUM> can perform the memory read operation on a partition <NUM> regardless of whether write operations are in the buffer <NUM> for other partitions <NUM>. In block <NUM>, the memory die <NUM> sends the read data on the data bus <NUM> to the microcontroller <NUM>.

In block <NUM>, the memory die <NUM> checks if it is time for a memory write operation. The memory die <NUM> may check if enough time (or clock cycles) has passed since the last memory operation. In the illustrative embodiment, the memory die <NUM> may check if at least <NUM> clock cycles have passed. If enough time has passed and there is a write operation in the buffer <NUM>, the memory die <NUM> performs a memory write operation in block <NUM>. The method <NUM> then loops back to block <NUM> to receive another memory operation.

Referring now to <FIG>, in one embodiment, a timing diagram <NUM> shows the timing of commands on the command bus <NUM>, data on the data bus <NUM>, and operations performed on the partitions <NUM>, for each of several time slots. It should be appreciated that, in the illustrative embodiment, additional time is needed when the microcontroller <NUM> performs a rank switch to change from sending operations to one memory die <NUM> to a second memory die <NUM>. The time for such a rank switch is not included in the timing diagram <NUM>. In practice, each memory operation is not necessarily going to line up with the slots marked in the figure. Rather, the time slots are included merely to show the approximate relative timing of different operations and tasks.

In the timing diagram <NUM>, the microcontroller <NUM> sends four consecutive memory write commands to a first memory die <NUM>, followed by sending four read commands to the first memory die <NUM>. The microcontroller <NUM> then sends four consecutive memory write commands to a second memory die <NUM>, followed by sending four read commands to the second memory die <NUM>. As the memory dies <NUM> have a buffer <NUM> that can fit at least four memory write operations, each memory die <NUM> can perform the memory write operations over a period of time. For example, the first memory die <NUM> can send the first memory write operation to a partition <NUM> in time slot <NUM> (at the same time as the write command is received). The partition <NUM> can perform the write operation as soon as the write data is available. However, the second memory write operation is not sent to the partition <NUM> until time slot <NUM>, one time slot after it was received, as the memory die <NUM> needs to wait a minimum amount of time before performing a subsequent write operation. Each of the third and fourth memory write operations are similarly delayed.

The first memory die <NUM> can perform the read operations simultaneously as the write operations. For example, the third write operation is sent to a partition <NUM> in time slot <NUM>, at the same time as the first read operation is sent to a different partition <NUM>. The read operations are seamlessly interwoven with the buffered write operations.

After the microcontroller <NUM> switches to sending operations to the second memory die <NUM>, the first memory die <NUM> can continue to complete the buffered write operations. For example, in time slot <NUM>, the microcontroller <NUM> sends a write command to the second memory die <NUM>, but the first memory die <NUM> is also performing the fourth write operation in a partition <NUM> at the same time. The write and read operations on the second memory die <NUM> can be completed in a similar manner as the write and read operations on the first memory die <NUM>.

Referring now to <FIG>, in one embodiment, a timing diagram <NUM> shows the timing of commands on the command bus <NUM>, data on the data bus <NUM>, and operations performed on the partitions <NUM>, for each of several time slots. In the timing diagram <NUM>, the microcontroller <NUM> sends four consecutive memory write commands to a first memory die <NUM>, then sends four consecutive memory write commands to a second memory die <NUM>, then sends four more consecutive memory write commands to the first memory die <NUM>, followed by four more consecutive memory write commands to the second memory die <NUM>. As for the timing diagram <NUM>, the memory write operations to the first memory die <NUM> are stored in the buffer <NUM>, and the first memory die <NUM> sends the data to the partitions to be written after the necessary delay. After the microcontroller <NUM> has partially or fully filled the buffer for the first memory die <NUM>, the microcontroller <NUM> switches to the second memory die <NUM>. It should be appreciated that the first memory die <NUM> continues performing write operations while the microcontroller <NUM> is sending memory write operations to the second memory die <NUM>. For example, in time slot <NUM>, the microcontroller <NUM> sends a memory write command to the second memory die <NUM>, while the first memory die <NUM> is performing a memory write operation that was sent to it back in time slot <NUM>.

By the time the microcontroller <NUM> has sent the fourth write command to the second memory die <NUM>, the first memory die <NUM> has completed its assigned memory write operations. As such, the microcontroller <NUM> can switch back to the first memory die <NUM> and send the memory die <NUM> additional memory write operations, partially or fully filling up the empty buffer <NUM> in the memory die <NUM>.

Claim 1:
A phase-change-based memory die (<NUM>) comprising:
a plurality of partitions (<NUM>); and
a chip controller (<NUM>), the chip controller to:
receive a first memory write operation at a first time;
receive a second memory write operation at a second time; and
send first memory write data corresponding to the first memory write operation to a first partition of the plurality of partitions;
wherein the phase-change-based memory die requires a minimum amount of time to elapse after performing a memory write operation before performing a subsequent write operation,
characterised in that the chip controller is further configured to:
determine that a time difference between the first time and the second time is less than the minimum amount of time before performing a subsequent write operation; and
in response to determining that the time difference between the first time and the second time is less than the minimum amount of time before performing a subsequent write operation:
store second memory write data corresponding to the second memory write operation in a buffer (<NUM>) of the phase-change-based memory die; and
send the second memory write data from the buffer to a second partition of the plurality of partitions at least after the minimum amount of time before performing a subsequent write operation after the first memory write data is sent to the first partition has elapsed.