Patent Description:
When performing I/O messages to write data on a drive, write coalescing is used to execute two or more I/O message requests to write data to a same row of a same drive together in one step. The data of the two or more data writings for the same row of the same drive may be stored by a cache controller in a cache segment (CS) row in the cache memory. In addition, there is a timeout for each I/O message. A firmware unit, in communication with the cache controller, checks the timeout. When getting close to the expiration of the timeout, the firmware unit provides an instruction to the cache controller to flush the data to the drive. When the CS row becomes fully dirty, e.g., is filled with new data, the cache controller performs a proactive flush of the CS row to the drive. It is highly desirable to maintain synchronization between the cache controller and the firmware unit and resolve the problem of stale data.

<CIT> discloses cache segment row flush operations.

However, for purposes of explanation, several aspects of the subject technology are depicted in the following figures.

The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the subject technology may be practiced. The appended drawings are incorporated herein and constitute part of the detailed description, which includes specific details for providing a thorough understanding of the subject technology. However, the subject technology is not limited to the specific details set forth herein and may be practiced without one or more of the specific details. In some instances, structures and components are shown in a block-diagram form in order to avoid obscuring the concepts of the subject technology.

When an element is referred to herein as being "connected" or "coupled" to another element, it is to be understood that the elements can be directly connected to the other element, or have intervening elements present between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it should be understood that no intervening elements are present in the "direct" connection between the elements. However, the existence of a direct connection does not exclude other connections, in which intervening elements may be present.

When performing I/O messaging to write data to a drive, write coalescing is used to gather together data of multiple writings to a row and perform the writing in one step to save time. In some embodiments, before writing to the drive, the data of a row is stored in a CS row of the cache memory where a CS row corresponds to a row of the drive. In some embodiments, before writing to the cache memory, a CS row of the cache memory is allocated. In addition, since each I/O message has a timeout and the hardware, e.g., the cache controller, does not have a timer, the timer is implemented by a firmware unit in communication with the cache controller. The firmware unit checks the timeout does not expire, e.g., does not timeout. At about the time of the expiration of the timeout, the firmware unit commands the cache controller to flush the data in the CS row to the drive. In addition, the data in the CS row is also flushed to the drive, when the CS row becomes fully dirty, e.g., the CS row is filled with new data. Then, the cache controller performs a proactive flush of the CS row to the drive and informs the firmware unit that the data in the CS row is flushed to the drive. Because a hardware operation is faster than a firmware operation that is performed based on a command/message queue, a synchronization between the cache module and the firmware unit is lost in some embodiments. In some embodiments, by flushing the CS row to the drive, the data in the CS row is committed, e.g., written to the drive. In some embodiments, after committing the data in the CS row to the drive, the CS row is cleaned, e.g., the CS row is marked as clean such that new data can be overwritten in the CS row.

In addition, if the cache controller performs the cleanup of the CS row after the CS row is flushed to the drive, the firmware unit may access data in the cache memory that does not exist. Also, the host, e.g., the processor, does not know about the CS rows and, thus, the I/O messages refer to a logical drive (LD) and a row number of the LD. In order to detect the timeout of the I/O message, the firmware unit receives an LD and row number of the LD and monitors the timeout based on the LD (e.g., two bytes) and row number of the LD (e.g., <NUM> bytes). Thus, the timeout data may easily fill a memory associated with the firmware unit and context exhaustion may happen and write coalescing may stop.

In the embodiments introduced below, instead of using the LD and the row number of the LD that takes ten bytes for tracking the timeout of multiple I/O messages, the local message ID (LMID) is used that takes two bytes because the number of LM buffers is limited, e.g., have <NUM> LM buffers, the ID of the LM buffers may be fit in two bytes. In some embodiments, as described above, the ID of the CS row is added to the LM buffer that is accessible, e.g., is retrievable, based on the LMID that is associated with, e.g., refers to, the local message buffer or the LM buffer. In some embodiments, the ID of the CS row that fits in one or more bytes, e.g. three bytes, is used for tracking the timeout.

Because the number of LM buffers and the number of CS rows are limited, the LM buffers and the CS rows are re-used in some embodiments and, thus, synchronization between the firmware unit and the cache module is addressed below. Although, the cache controller may proactively flush the CS row when the CS row is fully dirty, the cache controller or any other module of cache module may not initiate a purge of the CS row. In some embodiments, the cache controller sends a message to the firmware unit and the firmware unit sends an instruction to the cache module for the cleanup of the CS row as will be described below.

<FIG> illustrate a memory system <NUM> and an LM buffer <NUM>. The memory system <NUM> includes a cache module <NUM>, a storage memory <NUM>, an LM memory <NUM>, and a firmware unit <NUM> that includes a processor <NUM> and a firmware memory <NUM>. In some embodiments, the host <NUM> communicates with the firmware unit <NUM> through a storage controller (not shown), which includes the firmware unit <NUM> and the cache controller <NUM> through sending messages. In addition to the processor <NUM>, the host <NUM> includes a memory <NUM>, e.g., a random access memory. The cache module <NUM> includes a cache controller <NUM> and a cache memory <NUM>. In some embodiments, the firmware unit <NUM> is a non-volatile memory or includes a non-volatile memory that stores firmware instructions. In some embodiments, the cache controller <NUM> sends requests, via a link <NUM>, to be executed by the instructions of the firmware unit <NUM> by the processor <NUM>. In some embodiments, the firmware unit <NUM> sends responses back to the cache controller <NUM> via the link <NUM>. In some embodiments, the storage memory <NUM> is a physical drive. In some embodiments, the storage memory <NUM> is an LD.

In some embodiments, the cache memory is an aggregate of cache segment units of <NUM> kilo bytes (kB), <NUM> kB, <NUM> kB, or <NUM> kB. The cache controller <NUM> includes a cache flush hardware module <NUM> (e.g., a cache flush module), a cache update hardware module <NUM> (e.g., a cache update module), and an I/O dispatcher module <NUM>. In some embodiments, the cache controller <NUM> receives I/O messages and responds to I/O messages via a link <NUM> with a host <NUM>. In some embodiments, a message or command from the cache controller <NUM> requires a series of firmware instruction to be executed on the processor <NUM> of the firmware unit <NUM>. the firmware unit <NUM> and the host <NUM> execute instructions on separate processors. Firmware unit <NUM> services the IOs messages from the host <NUM> by the processor <NUM> and sends the status back to the host <NUM>.

In some embodiments, the messages sent to the firmware unit <NUM> are queued in a message queue, e.g., an instruction queue, of the firmware unit <NUM> and are executed one after the other. In some embodiments, the firmware unit <NUM> and the host <NUM> have separate memories, e.g., the firmware memory <NUM> and the memory <NUM>. The host <NUM> sends the I/O messages from the memory <NUM>, which are received by the storage controller and sent by cache controller <NUM> to the cache memory <NUM> and/or the LM memory <NUM>. In some embodiments, the cache controller <NUM> is a part of the storage controller and the I/O messages sent from the host <NUM> reach cache memory <NUM> through the link <NUM>, which may include other hardware units that translate the host messages.

A shown in <FIG>, the I/O dispatcher module <NUM> sends and receives data with the storage memory <NUM> via a link <NUM>. In some embodiments, the I/O dispatcher module <NUM> communicates and/or sends commands to the cache update hardware module <NUM>. Also, the cache controller <NUM> and the firmware unit <NUM> communicate via the link <NUM> and send and receive data. The memory system <NUM> additionally shows that the firmware unit <NUM> communicates and sends and receives data with the LM memory <NUM> via a link <NUM> and the cache controller <NUM> communicates, sends, and receives data with the LM memory <NUM> via a link <NUM>.

<FIG> shows an LM buffer <NUM>, a single memory unit, of the LM memory <NUM>. In some embodiments, each LM buffer has <NUM> bytes, <NUM> bytes, or more and the LM buffers are packed one after the other in the LM memory <NUM>. Thus, the first LM buffer <NUM> starts at address zero, e.g., beginning, of the LM memory <NUM> and the Nth LM buffer <NUM> starts at address <NUM>*(N-<NUM>) of the of the LM memory <NUM>. In some embodiments, the number of the LM buffers <NUM> in the LM memory <NUM> is <NUM> or <NUM>. In some embodiments, the LMID is an index to the address or location of the LM buffer <NUM> and, thus, the LMID is not more than two bytes. In some embodiments, when the cache controller <NUM> receives and I/O message via the link <NUM>, the I/O message includes an LMID and data to be written to the storage memory <NUM>. The cache controller <NUM> uses the LMID to access a corresponding LM buffer <NUM> of the LM memory <NUM> and retrieves, e.g., extracts, a content of the LM buffer <NUM>. The retrieved LM buffer <NUM> includes an ID of the LD (LDID), e.g., an address of the LD, at a memory location <NUM> of the LM buffer <NUM>. In addition, the retrieved LM buffer <NUM> includes a row number of the LD at a memory location <NUM>. In some embodiments, the LM memory <NUM> is used by the cache module <NUM> and by the firmware unit <NUM> that is in communication with the cache module <NUM> and, thus, the LM memory <NUM> is local memory for the messages. Therefore, the LM buffers <NUM> of the LM memory <NUM> are local buffers for the messages that are in communication with the cache module <NUM> that are stacked one after the other. Thus, the ID of the LM buffers <NUM> (or LMIDs) are indices of the LM buffers <NUM> in the LM memory <NUM>. Additionally, the LMID refers to a memory location of the LM buffer in the LM memory <NUM>. Therefore, assuming the LM buffer has <NUM> bytes, the first <NUM> bytes of the LM memory <NUM> has an ID that is zero and the Mth <NUM> bytes of the LM memory <NUM> between an ID that is M-<NUM>.

In some embodiments, the data in the I/O message is copied to a CS row of the cache memory <NUM>. In some embodiments, a row ID, e.g., a row number, of the CS row is copied to a memory location <NUM> of the LM buffer <NUM>. In some embodiments, each LM buffer <NUM> includes the address, e.g., the LMID, of another LM buffer <NUM>, e.g., the LMID corresponding to a previous I/O message with data stored in the CS row, Therefore, based on the tail LMID and the head LMID, a link list of LMIDs may be generated from the last data stored in the CS row to the first data stored in the CS row and the LMID of entire data in the CS row is accessible. In some embodiments, the LM buffer <NUM> corresponding to a first LMID does not include the LMID corresponding to a previous I/O message with data stored in the CS row and, thus, first LMID is a head LMID. In some embodiments, the link list of LMIDs may be generated based on only the tail LMID. In some embodiments, the LM buffer <NUM> in the LM memory <NUM> includes the LDID and the row number of the LD to be accessed in response to receiving the I/O message. In some embodiments, a physical memory based on the row number of the LD is accessed. In some embodiments, the cache controller <NUM> and the firmware unit <NUM> have access to the cache memory <NUM>. Thus, the message <NUM> to the cache flush hardware module <NUM> to flush the data includes the tail LMID and based on the tail LMID, the entire LMIDs of the data stored in CS row are accessible.

In some embodiments, the write command is loaded by the host <NUM> and is executed by the processor <NUM> of the host <NUM> and the processor <NUM> sends the write command to the cache flush hardware module <NUM>. In some embodiments, the cache controller <NUM> receives a first I/O message to write data to a drive with a first LDID and a first row number. As noted, first data in the first I/O message is copied to a CS row (having an ID for the CS row) of the cache memory <NUM> and the LMID of the LM buffer <NUM> of the LM memory <NUM> is added to the write-pending-list corresponding to the CS row. Then the cache controller <NUM> receives one or more second I/O messages to write data having the first LDID and the first row number such that the first I/O message and the one or more second I/O messages have identical, e.g., same, LDIDs and identical, e.g., same, row numbers. Second data in the second one or more I/O messages is copied, e.g., by the cache controller <NUM>, to the same CS row of the cache memory <NUM> and gets appended to the first data. Before the CS row becomes fully dirty, a cache flush timeout occurs. In response to the to the cache flush timeout, a flush command, e.g., the message <NUM> is sent to the cache flush hardware module <NUM> to flush the data in the CS row to the drive. In some embodiments, a write-pending-list is generated and maintained for each CS row that includes data. The write-pending-list may include the LMIDs associated with the data in the CS row, e.g., the LMIDs of the first I/O message and the one or more second I/O messages. In some embodiments, a write-pending-list of a CS row is generated and maintained in the CS row. In some embodiments, the write-pending-list of the CS row includes a tail LMID and a head LMID. The tail LMID refers an LM buffer <NUM> corresponding to data last stored in the CS row and the head LMID refers an LM buffer <NUM> corresponding to data first stored in the CS row. In some embodiments, a timestamp associated with the first I/O message, e.g. the timestamp associated with the CS row, becomes associated with the one or more second I/O messages. In some embodiments, a command or message between the firmware unit <NUM> and the cache module <NUM> is transferred via link <NUM>.

<FIG> illustrates a memory system <NUM>, according to various aspects of the subject technology. The memory system <NUM> shows the cache module <NUM> that includes the cache flush hardware module <NUM>, the cache update hardware module <NUM>, the cache memory <NUM>, and the I/O dispatcher module <NUM>. The received I/O message includes the LMID and the data to be written to the logical drive <NUM>. As described above, the cache controller <NUM> receives an I/O message <NUM> from the host <NUM> and the data in the I/O message is copied to a CS row <NUM>. Based on the LMID, the LM buffer <NUM> in the LM memory <NUM> may be accessed and the LDID and the row number of the LD may be accessed. The cache controller <NUM> checks if the CS row <NUM> is fully dirty. If it is not fully dirty, another I/O message is received. If the CS row <NUM> is fully dirty, the cache controller <NUM> sends an issue flush command <NUM> and sends the issue flush command <NUM> to the I/O dispatcher module <NUM>.

After the I/O message is received, a message <NUM> along with the ID of the CS row corresponding to CS row <NUM> is sent to firmware unit <NUM> to instruct the firmware unit <NUM> to acquire a timestamp for the CS row <NUM> and store the timestamp in the firmware memory <NUM> of the firmware unit <NUM>. Thus, for each first received I/O message on a new row of an LD, a timestamp is associated with the ID of the CS row. The LMID and the corresponding ID of the CS row are stored in an item of a cache managed write-pending-list. In some embodiments, the CS row has a timeout by which the data must be flushed and the I/O must be completed back to the host, e.g., a cache flush timeout. The timestamp for the CS row of the I/O message, is periodically, e.g., repeated in a constant interval, checked against the timeout by the firmware unit <NUM>.

In some embodiments, the issue flush command <NUM> includes a parity raid request (PRRQ) that includes a proactive flush bit. In response to the issue flush command <NUM> initiated by the cache controller <NUM>, because the CS row <NUM> had been fully dirty, the proactive flush bit is set to one by the cache controller <NUM>. On I/O completion, the I/O dispatcher module <NUM> checks if the proactive flush bit <NUM> is set to one. If the proactive flush bit <NUM> is set to one, then I/O dispatcher module <NUM> sends a flush complete message <NUM>, e.g., a command, to the firmware unit <NUM>. If the proactive flush bit <NUM> is not set to one, e.g. is set to zero, then I/O dispatcher module <NUM> sends a cache update message <NUM>, e.g., a command, to the cache update hardware module <NUM> to clean the CS row <NUM> and to generate an I/O complete message <NUM> and sent the I/O complete message <NUM> to the host <NUM> to indicate that the I/O message <NUM> is done and the data is committed to the logical drive <NUM>. Regardless of the proactive flush bit <NUM> being zero or one, the data is sent, by the I/O dispatcher module <NUM>. via a communication link <NUM> to the logical drive <NUM> to be written to the drive. In some embodiments, the I/O dispatcher module <NUM> stores the PRRQ in the LM buffer <NUM> corresponding to the LMID and change the type to PRRQ LMID.

In some embodiments, the cache update hardware module <NUM> receives a cache update message <NUM> from the I/O dispatcher when the proactive flush bit <NUM> is not set in the flush message. In an aspect of the subject technology, the cache controller further receives one or more second I/O messages. An LDID and a row number of the LD of the second I/O messages are identical with the LDID and the row number of the first I/O message. The cache controller also stores second data of the one or more second I/O messages in the CS row of the cache memory. The cache flush timeout is detected before the CS row becomes fully dirty, and in response to the detecting the cache flush timeout, the flush command is sent to the cache controller.

The firmware unit <NUM> receives the message <NUM> from the cache module <NUM> and creates a context <NUM>. As described, the message <NUM> includes the ID of the CS row that stores the I/O message <NUM>. In some embodiments, the context <NUM> is a table that include the ID of the CS row of the I/O message <NUM> and the table is created in the firmware memory <NUM>. For each entry, the table also includes one or more timestamps, e.g., the time one or more I/O messages are received, associated with the CS row ID, e.g., the ID of the CS row. Thus, the one or more I/O messages associated with the CS row are I/O messages that are stored in the CS row. The firmware unit <NUM> checks, e.g., periodically checks, the timestamps associated to the IDs of the CS rows that include data for an expiration, e.g., an expiry or timeout. In response to a timestamp associated with the ID of the CS row <NUM> being expired, the firmware unit <NUM> sends a message <NUM>, that includes the tail, e.g. the last, LMID in the write-pending-list for the ID of the CS row <NUM> associated with, e.g., related to, the expired timestamp to the cache flush hardware module <NUM>. The firmware unit <NUM> instructs the cache flush hardware module <NUM> to flush the data in the CS row <NUM> of cache memory <NUM>. In some embodiments, when more than one data of the I/O messages are in the CS row <NUM>, the expired timestamp is for the I/O message received earliest, however, the entire data in the CS row <NUM> is flushed. In some embodiments, the earliest timestamp of the data in the CS row <NUM> is the timestamp of the CS row <NUM> or the timestamp associated with the CS row <NUM>.

In some embodiments, the cache flush hardware module <NUM> derives the ID of the LD, e.g. the LDID, and the ID of the CS row <NUM> from the LMID and generates a message <NUM> that includes a parity raid request (PRRQ) with the proactive flush bit <NUM> that is set to zero and sends the message <NUM> to the I/O dispatcher module <NUM>. Because the proactive flush bit <NUM> is set to zero, the I/O dispatcher module <NUM> sends a cache update message <NUM> to the cache update hardware module <NUM> as described above. In some embodiments, the firmware unit <NUM> periodically checks the timestamp at about every <NUM> milliseconds (msec) to about every <NUM> msec, where about is within <NUM> percent. In some embodiments, a redundant array of independent disks (RAID) configuration uses disk striping with parity. Because data and parity are striped evenly across all of the disks, no single disk is a bottleneck. Striping also allows users to reconstruct data in case of a disk failure. Thus, the PRRQ instructs the I/O dispatcher module <NUM> how to distribute the data to be stored over the array of disks and how to generate parities. In some embodiments, the PRRQ is stored in the LM buffer <NUM> and is accessed based on the LMID, e.g., the PRRQ LMID, of the LM buffer <NUM>. In some embodiments, the LMIDs have different types depending on the data in the LM buffer <NUM> that the LMID refer to. Thus, the LMID of an LM buffer <NUM> that includes the PRRQ may be an PRRQ LMID, e.g., an LMID of the type PRRQ. In some embodiments, receiving a command that includes the PRRQ is that a command is received that includes the PRRQ LMID and PRRQ is accessible in the LM buffer <NUM> associated with the PRRQ LMID.

When a ID of the CS row has waited more than cache flush timeout in the firmware unit <NUM> or when the flush complete message <NUM> is received by the firmware unit <NUM>, a cleanup module <NUM> of the firmware unit is instructed to clean up the firmware context of the corresponding to the CS row ID, e.g., the CS row <NUM>. In the case of flush complete message <NUM> received by firmware unit <NUM>, when a proactive flush by the cache controller <NUM> is performed, the cleanup module <NUM> sends a message or command, e.g., a cache update message <NUM>, to the cache update hardware module <NUM>. In response, the cache update hardware module <NUM> cleans the CS row <NUM> and generates an I/O complete message <NUM> and sends the I/O complete message <NUM> to the host <NUM> to indicate that the I/O message <NUM> is done and the data is committed to the logical drive <NUM>.

<FIG> and <FIG> illustrate messaging of modules of a memory system, according to various aspects of the subject technology. <FIG> and <FIG> are consistent with <FIG>. <FIG> shows the steps arranged in a time <NUM> that corresponds to a condition that a timeout, e.g., a cache flush timeout is detected in the firmware unit <NUM> and shows the I/O message <NUM> from the host <NUM> to the cache module <NUM>. Then cache module <NUM> sends the message <NUM>, a write coalesce message, to the firmware unit <NUM> to monitor a timeout at step <NUM>. As noted before, a command or message between the firmware unit <NUM> and the cache module <NUM> are transferred via link <NUM>. After the timeout, e.g., when the timestamp of the ID of the CS row wait time in firmware has exceeded the cache flush timeout, e.g., a timeout has occurred, the firmware unit <NUM> sends the message <NUM> to the cache flush hardware module <NUM> to flush the data. The firmware unit <NUM> cleans up a portion of the firmware memory <NUM> associated with the firmware unit <NUM> in step <NUM> and removes a content of the table associated with the ID of the CS row of the flushed data. At step <NUM>, the I/O dispatcher module <NUM> sends the data, via a communication link <NUM> to the logical drive <NUM> to be written to the drive. Again, the I/O dispatcher module <NUM> sends the cache update message <NUM> to the cache update hardware module <NUM> of the cache module <NUM> and sends the I/O complete message <NUM> to the host <NUM> to indicate that the I/O message <NUM> is complete. In some embodiments, the cache flush timeout is <NUM>-<NUM> percent, shorter than the I/O timeout.

<FIG> also shows the steps arrange in the time <NUM> that corresponds to a condition that the CS row becomes fully dirty, e.g., all the data is new to be committed to the drive. The firmware unit <NUM> and shows the I/O message <NUM> from the host <NUM> to the cache module <NUM>. When the data for I/O message <NUM> is stitched to the cache, the cache module checks if the CS row is fully dirty in step <NUM> and flushes the CS row in step <NUM>, e.g., a proactive flush by the cache controller <NUM>. Since the proactive flush bit is set to one, flush complete message <NUM> is sent by the I/O dispatcher module <NUM> to the firmware unit <NUM> for cleanup and in response the firmware unit sends the cache update message <NUM> as described above.

The subject technology discussed above reduces the context exhaustion of the memory of the firmware unit. In addition, the subject technology resolves the synchronization problem between the firmware unit and the cache module and resolves the problem of stale data because the firmware unit performs the cleanup of the cache memory.

According to aspects of the subject technology, a memory system includes a firmware unit and a cache module that includes a cache controller and a cache memory. The cache controller receives a first I/O message that includes an LMID and first data. The cache controller also stores the first data in a CS row of the cache memory and sends an ID of the CS row to the firmware unit. The firmware unit provides firmware instructions such that in response to receiving the CS row ID, a timestamp for the ID of the CS row, is acquired and stored. The timestamp is periodically checked for the cache flush timeout. In response to detecting the cache flush timeout a flush command is sent with the ID of the CS row to the cache controller to instruct the cache controller to flush the first data in the CS row.

In an aspect of the subject technology, the cache controller further extracts the LMID and the first data of the first I/O message and allocate a CS row for the first data, and store the LMID and the ID of the CS row in a write-pending-list, and wherein the LMID is accessible based on the ID of the CS row. In an aspect of the subject technology, the periodic check of the cache flush timeout is performed at about every <NUM> milliseconds (msec), and on expiry of the cache flush timeout, the flush command is provided through a firmware instruction to the cache controller, and the firmware instruction includes the ID of the CS row and a proactive flush bit that is set to zero. In an aspect of the subject technology, the cache controller module further includes an I/O dispatcher module and a cache flush module. The cache flush module receives the flush command with the ID of the CS row from firmware and sends the flush command with the ID of the CS row to the I/O dispatcher module to flush the first data of the CS row. The flush command includes an LMID of a type of parity raid request (PRRQ). In an aspect of the subject technology, the cache module further includes an I/O dispatcher module extracts the PRRQ LMID from the flush command, retrieves an ID of a logical drive (LD) and a row number of the LD based on the PRRQ LMID as a location to flush the first data to, and flushes the first data in the CS row to a physical destination disk based on the row number of the LD. In an aspect of the subject technology, the cache module further includes a cache update module that in response to receiving a flush complete message by the I/O dispatcher module, the I/O dispatch module detects a proactive flush bit based on the PRRQ LMID, and in response to detecting that the proactive flush bit is set to zero, the I/O dispatcher module sends a cache update message to the cache update module, and in response to the cache update message, the cache update module does cleanup the CS row and generate an I/O complete message.

According to aspects of the subject technology, a memory system includes a firmware unit and a cache module that includes a cache controller and a cache memory. The cache controller receives an I/O message that includes data and a local message ID (LMID), stores the data of the I/O message in a CS row of the cache memory, and in response to the CS row being fully dirty, generates a PRRQ having a proactive flush bit that is set to one, stores the PRRQ in an LM buffer corresponding to the LMID to make the LMID a PRRQ LMID, and flush the data of the CS row. Also, in response to the proactive flush bit being set to one, sends a flush complete message with the PRRQ LMID to the firmware unit.

In an aspect of the subject technology, the cache module further includes a cache update hardware module. The firmware unit, in response to receiving the flush complete message, extracts the PRRQ LMID and provides a cache update message and the PRRQ LMID, through firmware instructions executable by a processor of the firmware unit, to the cache update module and requests to clean the CS row, and to generate an I/O complete message. In an aspect of the subject technology, the firmware unit receives the ID of the CS row from the cache module, in response to receiving the ID of CS row, stores a timestamp to check against a cache flush timeout, for the CS row, periodically checks for the cache flush timeout based on the timestamp, and before the cache flush timeout is detected, receives the flush complete message from an I/O dispatcher. In an aspect of the subject technology, the cache module further includes an I/O dispatcher module. The I/O dispatcher receives an issue flush command, retrieves the PRRQ LMID, retrieves the PRRQ and a logical drive (LD) ID and a row number of the LD based on the PRRQ LMID as a location to flush the data, and flushes the data in the CS row to the row number of the LD. Also, in response to completion of the flush, sends the flush complete message with the PRRQ LMID to the firmware unit. In an aspect of the subject technology, the I/O dispatcher module extracts the PRRQ LMID corresponding to the CS row, retrieves a logical drive (LD) ID and a row number of the LD from the PRRQ LMID as a location to flush the data and determines the destination disk, and flushes the data in the CS row to a physical destination based on the row number of the LD. In an aspect of the subject technology, the cache controller generates and maintains a write-pending-list in the cache memory. The write-pending-list includes a list of LMIDs associated with one or more I/O messages of each CS row. In an aspect of the subject technology, the I/O message is to write data to an LD.

According to aspects of the subject technology, a memory system includes a firmware unit and a cache module that includes a cache controller, a cache memory, and an I/O dispatcher module. The cache controller receives a first I/O message to write to an LD. The first I/O message comprises a first LMID and first data. The cache controller also retrieves the LD and a row number of the LD from the first LMID of the first I/O message to write to the LD, stores the data of the first I/O message in a CS row of the cache memory, incorporates an ID of the CS row and the LMID to a write-pending-list corresponding with the CS row, sends a message that includes the ID of the CS row to the firmware unit and the firmware unit provides firmware instructions that, in response to receiving the first CS row ID, saves a timestamp to check against a cache flush timeout, for the CS row, in response to receiving the ID of the CS row. Periodically checks for the cache flush timeout and in response to a proactive flush of the CS row of the cache memory by the cache controller and before the cache flush timeout is detected, receive a flush complete message and the first LMID from the I/O dispatcher module. Also, in response to receiving the flush complete message, extracts the ID of the CS row based on the first LMID, cleanup firmware context and send a cache update message including the first LMID to the cache controller to clean the CS row, and generate an I/O complete message.

In an aspect of the subject technology, the cache module further includes a cache update hardware module. The cache update hardware module cleans the CS row and generates the I/O complete message. In an aspect of the subject technology, the cache controller receives one or more second I/O messages to write to a drive that includes one or more second LMIDs and second data. The one or more second LMIDs includes a same LD and a same row number of the LD as the first LMID and generates and maintains the write-pending-list corresponding with the CS row that includes a list of one or more LMIDs associated with the first I/O message and the one or more second I/O messages of the CS row that includes the first data of the first I/O message and the second data of the one or more second I/O messages that correspond to the same row number of the same LD. In an aspect of the subject technology, the I/O dispatcher module receives a PRRQ having a proactive flush bit that is set to one, retrieves the LMID, retrieves a logical drive (LD) ID and a row number of the LD from the first LMID as a location to flush the first data, and flushes the first data in the CS row to the row number of the LD and on completion of the flush, sends the flush complete message with the first LMID referring to the PRRQ to the firmware unit. In an aspect of the subject technology, in response to the CS row being fully dirty, the cache controller generates the PRRQ having the proactive flush bit that is set to one, and sends the PRRQ and the data to the I/O dispatcher module to flush the data of the CS row. In an aspect of the subject technology, the I/O dispatcher module receives a PRRQ having a proactive flush bit that is set to zero, and sends the cache update message to the cache update hardware module to clean the CS row and to generate the I/O complete message.

Those of skill in the art would appreciate that the various illustrative blocks, modules, elements, components, memory systems, and algorithms described herein may be implemented as electronic hardware, computer software, or combinations of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, memory systems, and algorithms have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system.

It is understood that any specific order or hierarchy of blocks in the processes disclosed is an illustration of example approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes may be rearranged, or that all illustrated blocks should be performed. Any of the blocks may be simultaneously performed. In one or more implementations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems could generally be integrated together in a single software product or packaged into multiple software products.

As used in this specification and any claims of this application, the terms "base station," "receiver," "computer," "server," "processor," and "memory" all refer to electronic or other technological devices. For the purposes of the specification, the term "display" or "displaying" means displaying on an electronic device.

By way of example, the phrases "at least one of A, B, and C" and "at least one of A, B, or C" each refer to only A, only B, or only C; any combination of A, B, and C; and/or at least one of each of A, B, and C.

The predicate words "configured to," "operable to," and "programmed to" do not imply any particular tangible or intangible modification of a subject but rather are intended to be used interchangeably.

Phrases such as "an aspect," "the aspect," "another aspect," "some aspects," "one or more aspects," "an implementation," "the implementation," "another implementation," "some implementations," "one or more implementations," "an embodiment," "the embodiment," "another embodiment," "some embodiments," "one or more embodiments," "a configuration," "the configuration," "another configuration," "some configurations," "one or more configurations," "the subject technology," "the disclosure," "the present disclosure," and other variations thereof and alike are for convenience and do not imply that a disclosure relating to such phrase(s) is essential to the subject technology or that such disclosure applies to all configurations of the subject technology. A phrase such as "an aspect" or "some aspects" may refer to one or more aspects and vice versa, and this applies similarly to other foregoing phrases.

" Any embodiment described herein as "exemplary" or as an "example" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, to the extent that the term "include," "have," or the like is used in the description or the claims, such term is intended to be inclusive in a manner similar to the term "comprise" as "comprise" is interpreted when employed as a transitional word in a claim.

Moreover, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly recited in the claims.

Claim 1:
A memory system, comprising:
a firmware unit; and
a cache module that comprises a cache controller and a cache memory, the cache controller is configured to:
receive a first I/O message that comprises a local message ID (LMID) and first data,
store the first data in a cache segment (CS) row of the cache memory, and
send an ID of the CS row to the firmware unit; and
wherein the firmware unit is configured to provide firmware instructions to:
in response to receiving the ID of the CS row, acquire a timestamp for the ID of the CS row;
store the timestamp, and
periodically check for a cache flush timeout, and
in response to detecting the cache flush timeout, send a flush command with the ID of the CS row to the cache controller, wherein in response to receiving the flush command, the cache controller is configured to flush the first data of the CS row.