Patent Description:
Back end of line (BEOL) connections, where individual devices of an integrated circuit (transistors, capacitors, resistors, etc.) are interconnected with wiring on a wafer are traditionally realized using layers of metal at different height and vias that connect two metallization layers. The vias need to be carefully aligned to the metal above and the metal below. In recent technology nodes, the alignment to the top metal is ensured by using a self-aligned "trench via" approach, where the physical via is only created where both top metal and trench via overlap. For the alignment between via and bottom metal, no self-alignment scheme is currently available.

An example of self-aligned via design is given in document <CIT> and document <CIT> describes a grid self-aligned metal via processing scheme for back end of line interconnect comprising metallization layers comprising alternating metal lines and dielectric lines and a method of fabricating an interconnect structure for a semiconductor die.

A problem that arises with usual self-aligned via schemes is that the VIA mask must aim correctly on the bottom metallization layer. Otherwise, it can short to a neighboring line of the target bottom metallization layer. This problem is important in scaled technology nodes.

In addition the routing capabilities are limited.

The invention aims to improve the routing capabilities in terms of alignment, in terms of flexibility in R/C optimization and routing flexibility.

<CIT> discloses a process of forming a multi-level semiconductor metallization structure. <CIT> discloses a power rail for standard cell block.

To that end, the present invention proposes an integrated circuit comprising an interconnection system.

An integrated circuit according to the invention comprises a multilevel routing track, the multilevel routing track comprising at least a first and a second conductive line, wherein each of the first and the second conductive line comprises conductive parts extending in parallel in at least three levels including a lower extension line level, a centerline level arranged directly above the lower extension line level and an upper extension line level arranged directly above the centerline level, wherein the conductive parts in said three levels have longitudinal sidewalls that are coplanar;.

The wording given above "multilevel routing tracks" designates boundaries in which are created uninterrupted lines potentially at different levels in the metallization layer.

The invention has the advantage to allow flexibility in connecting lines between levels and increases the routing possibilities.

In embodiments, the conductive parts of the first and second conductive lines comprise upwards or downwards extensions providing conductive parts of different and/or varying thickness within their layer which permits to build conductive lines having various heights and length within a single layer.

In embodiments, at least some of the conductive parts of the conductive lines, within said multilevel routing track layer, change of level upwards or downwards within said centerline level, upper extension line level and lower extension line level.

This example reduces routing congestion in allowing provision of two signal lines levels in a layer with conductive lines, instead of adding metal and via layers which is costly.

In embodiments, the interconnection system of the invention is provided with two or three multilevel routing tracks layers each having three levels.

A detailed description of examples useful for understanding the invention will be discussed hereunder in reference to the attached drawings where:.

The present invention concerns improved internal routing in an integrated circuit such as for example the Back end of line (BEOL) connections of such integrated circuit. In traditional routing layers, each layer comprise parallel lines in one plane and lines of adjacent layers are perpendicular, with VIA layers providing point connectivity between crossing lines of adjacent layers. In the present invention, rather than all conductive lines of a layer lying in a single level where these lines are parallel and at the same level, the lines of a layer of the invention may lie in different levels, that is at different altitude in the layer.

<FIG> discloses a layer M1 with multiple levels L0, L1, L2 in a direction perpendicular to the plane of the layer. The layer is then referred to as a layer with multilevel routing tracks, the three levels form a centerline level L1, an upper extension line level L2 and a lower extension line level L0 that lie in a plane perpendicular to the plane of the layer. In the present invention, the longitudinal sidewalls of the parts inside a multilevel routing track at adjacent levels are self-aligned. This means that the parts in the multilevel track are coaxial to each other and have the same width. As a result, the sidewalls of those parts, which are parallel to the routing track and perpendicular to the plane defining the layer, are coplanar.

In this first example, the lines of the layer which are extending parallel to a first direction referred to as a longitudinal direction of the layer, follow multilevel routing tracks in a plane perpendicular to the layer plane. This allows several possibilities.

First the multilevel routing tracks permits to build lines having a height of more than one level such as part 20b of line <NUM> extending on the three levels of the layer and part 20a and 20c of line <NUM> extending on two levels, upper levels for part 20c and lower levels for part 20a.

Second, the routing tracks allow the lines to change levels such as line <NUM> and also line <NUM> which has a first part 22a on the lower extension line level L0, a second part 22b on the centerline level L1 and third part 22c on the upper extension line level L2.

The above concept allows lines in a single layer to extend one above the other such as lines <NUM> and <NUM> where line <NUM> is in the lower extension line level L0 and line <NUM> is in the upper extension line level L2. These conductive lines <NUM>, <NUM> are separated by insulating material <NUM> in the centerline level L1.

As seen above, the multilevel layer scheme can be used to make both thick wires <NUM> or thin wires <NUM> in a vertical direction in the multilevel layer M. This allows a better trade-off between resistance and capacitance of the lines and allows providing two lines one above each other.

<FIG> represents a front view of different types of parallel lines extending in a longitudinal direction in a layer M with three levels. Such layer includes low resistance lines <NUM>, 40a, 40b, one level low capacitance lines 41a, 41b, 42a and <NUM> and medium lines of two levels <NUM>, <NUM>.

<FIG> shows also in a same layer a one level height conductive line 42a between two three levels height conductive lines 40a, 40b which reduces parasitic capacitance of the three levels lines without sacrificing a routing track.

In addition, putting neighboring lines at different levels, such as single level lines 41a lying in the lower extension level and single level line <NUM> lying in the centerline limits parallel wires coupling. This can also be done with two levels lines such as lines <NUM>, <NUM>. Staggering neighboring wires provides reduction in capacitance.

<FIG> provides a cross sectional view of <FIG> along line AA which shows that a line may have a varying section e.g.: one level segments <NUM>, <NUM> at different levels and a thick segment <NUM>.

To summarize, <FIG> indicates how the different levels available in a metallization layer result in a different trade-off between R and C.

The multilevel layer also allows a more suited choice of the heights of each level using design technology co-optimization (DTCO).

However when a multilevel layer M1 is sandwiched between an upper and lower layers some limitations apply since lines in the upper L2 and lower L0 extensions levels of the multilevel layer must not make shorts circuits with lines or connection areas of the upper and lower layers.

It should be noted that <FIG> show several possible wiring solutions in a condensed format for conciseness and do not reflect a specific working wiring.

In addition, some process flows, e.g. SADP self-aligned double patterning or SAQP self-aligned quadruple patterning, additionally fix either the width or the space of lines to a specific value. In such case, the flexibility of the invention providing a variable height is even more important as in the normal flow, since there is very limited freedom to trade-off R and C in such process flows.

In some situations, a lower resistance (hereafter R) is more important than a low capacitance (hereafter C) such as power supply lines or first segments of long signal wires (close to a driver) which are on a critical path.

In other situations, a lower C is more important, and a higher R is acceptable. This is for example the case for short signal wires, and for the last stretch of long signal wires. This is also the case for signals that are not on critical paths.

The invention permits to respond to such issues.

The invention also applies to full BEOL stacks where an intermediate metallization layer M1 must be able to connect to a top layer M2 above and to a bottom layer M0 below.

<FIG> provides an embodiment of possible wiring situations where a middle multilevel layer M1, having three levels L0, L1, L2, is located between a lower layer M0 and an upper layer M1. In this example the lower M0 and upper M2 layers are single level layers having lines <NUM>, <NUM>, <NUM>, <NUM> extending in a direction perpendicular to the lines of the multilevel layer M1.

An advantage of this embodiment is that it provides additional routing resources. For example, line <NUM> may have various thickness segments 31a, 31b and various height segments 31b, 31c. This embodiment permits also to provide connection patterns where separate lines <NUM>, <NUM> in a same routing track, that is on a same longitudinal axis of the central layer M1, are connected to upper and lower lines <NUM>, <NUM> of a layer above and a layer under the central layer within a direction perpendicular to the plane of the layer. This is done with adding an isolation layer <NUM> inserted between the lines <NUM>, <NUM>. This solves the problem of what we call "handshake connections" where two separate lines on a same vertical plane in the same layer need to be connected separately to a line in an upper layer and a line in a lower layer which are above one other.

Second, this embodiment permits also to route two signal lines <NUM>, <NUM> in the single layer with multilevel routing tracks. In such case, an insulation layer <NUM> within the three level layer separates the two lines <NUM>, <NUM> providing what we call "fly-over connections". In the described situation, line <NUM> has down connections to lines <NUM>, <NUM> of the lower layer M0 while line <NUM> may be connected elsewhere.

This configuration permits to connect directly a line of an upper or lower layer with a line of the multilevel layer by routing said line of the multilevel layer respectively in the upper extension level or lower extension level to contact the line respectively in the layer above or in the layer under.

In further embodiments the upper and/or lower layers may be multilevel layer having at least two or three layers to provide more flexibility.

<FIG> provides an example of configuration for a full BEOL stack having three multilevel layers M0', M1', M2' each having three layers L0, L1, L2 which provide even more flexibility as each line can be routed up or down in its layer. In this full stack, there are also more options available using contact pads made of up or down localized extensions of the lines.

As examples, lines of one level height <NUM>, 54a may be provided in any level of a layer, line of two levels height <NUM>, <NUM>, <NUM>, <NUM> may be provided on the uppers or lowers levels of any layer provided that it does not short circuit a line of an adjacent layer. In addition, lines of three levels height such as line <NUM> for power lines may be provided.

Connection between lines of adjacent layers may use connection pads such as pad 51a between the two level line <NUM> and the two level line <NUM> and pad 60a between said two level line <NUM> and single level line <NUM>. A three level connection pad <NUM> may also be used to connect a line of the upper layer M2' to the lower layer M0' through the middle multilevel layer M1' such as line <NUM> in the upper layer M2' connected to line <NUM> of the lower layer M0' through a three level pad <NUM>.

The use of local pads such as pads 60a and 51a permit to provide connections when two vertically extended lines such as line <NUM> and <NUM> and line <NUM> and <NUM> that cross each other at noncontiguous levels. The same applies where line <NUM> connects to a two level line <NUM> through pad 62a and to a one level line <NUM> through pad 61a.

Depending on the situation, the selective deposition of this isolation layer can use a relatively relaxed mask and hence be significantly cheaper than an additional metallization layer that would otherwise be needed to achieve the same layout density.

It should be noted that case the upper layer M2 is a multilevel layer, a first connection between a line of the upper level M2 and the multilayer M1 can be made through a locally arranged down extension or pad of a crossing conductive line in said upper layer and a line of the middle multilevel layer.

In case the lower layer M0 is a multilevel layer a second connection may be made through a locally arranged up extension (pad) of a second crossing conductive line in said lower layer. <FIG> provides an example where line <NUM> has a pad 63a to connect with a line of the middle multilevel layer.

The depicted configuration provides even more flexibility to adapt the resistance and capacitance of the lines. Now, low capacitance lines can be either at the bottom, at the center, or at the top of the layer. Staggering neighboring lines further reduces capacitance as for lines <NUM> and <NUM>. One can also use this freedom to reduce the coupling between the metallization layers above and below.

The invention can be used in other situations.

<FIG> represents a prior art source drain connection system in a standard cell <NUM> in cross section between two gates.

The cell comprises a routing layer <NUM> comprising a Vss line <NUM>, a Vdd line <NUM> and signal lines 503a, 503b, 503c. Under the routing layer,are provided a contact layer <NUM> with contact pads between the routing layer and a middle of line layer <NUM> above the EPI contact level <NUM> providing connections for PMOS fins <NUM> and NMOS fins <NUM> e.g. neighboring NMOS and PMOS junctions of an inverter.

Such standard configuration does not permit to provide a connection from left track 506c to middle line 503c. In addition, there is a limited spacing <NUM> between the connection elements 506a, 506b of the fins of the junctions which may raise insulation issues.

The application of the above concept to such a system is shown in <FIG> where the cell <NUM> is similarly depicted in cross section. In this example, the middle of line layer is replaced with a multilevel layer M <NUM> of the invention.

The multilevel layer <NUM> is located under a connection level <NUM> to connect upper line layer <NUM> having Vss line <NUM>, Vdd line <NUM> and signal lines 603a, 603b, 603c. The connection level <NUM> and upper line level <NUM> may be part of a two level layer.

Under the multilevel layer <NUM> is found the EPI contact level <NUM> providing connections for PMOS fins <NUM> and NMOS fins <NUM>.

In this design, a connection <NUM> can now be done between a line 603b of the routing layer <NUM> with the contact line of the connection element 606c located in the two lower levels of the multilevel layer <NUM>, through a right extension <NUM> of line 606c in the upper level of the multilevel layer <NUM>. In such case, an insulating layer 612a separates said contact line from the connection element 606b.

Similarly, additional space for isolation between connection 606b and 606a may also be obtained by routing the connections from 606b to <NUM> and from 606a to <NUM> using staggered transitions from level <NUM> to level <NUM> of the multilevel layer <NUM>.

The multilevel configuration provides here again more flexibility in routing of signals and an increased robustness of the design.

Such a configuration using a three level middle of line layer may also permit to provide contact lines to buried power lines between junction fins in a lower level of the multilevel layer. By inserting an optional isolating layer at the center level of the buried multilevel layer, two different nets can be routed above one another in a single multilevel routing track. Example use cases are a global vdd net at a bottom level and a local power-gated vdd net at a top level, or a vdd net at a bottom level and a signal net at a top level.

Manufacturing of the layers uses standard techniques used in the integrated circuit field. For the extensions of lines towards the bottom, a modern dual damascene process can be used. For the extensions towards the top, a mask allowing a recessing step of the regions where the top extension is not desired can be used. Alternatively, a masked selective deposition scheme can be used to grow the top extensions.

A process for forming an integrated circuit related to the invention may comprise forming a multilevel layer comprising first parallel electrically conductive lines <NUM>, <NUM>, <NUM>, <NUM>, said multilevel layer comprising at least three levels L0, L1, L2 constituting a centerline level L1, an upper extension line level L2 and a lower extension line level L0. The levels provide multilevel routing tracks in which said conductive lines extend and are aligned.

The lines comprise conductive parts having longitudinal sidewalls perpendicular to said layer plane and inside a multilevel routing track.

In this regard <FIG> and <FIG> represent possible manufacturing processes with a dual damascene process providing construction of a M1 layer on a M0 layer in a semiconductor wafer for fabrication of the integrated circuits comprising the interconnection system.

<FIG> represent manufacturing lines in an intermediate multilevel layer located on a lower single level layer.

<FIG> represents a lower single level layer with two copper lines <NUM>, <NUM> schematically represented in a dielectric layer <NUM>. In <FIG> the multilevel layer of starts with the raising of three plies of dielectric layers 105a, 105b, 105c which may be oxide layers such as silicon dioxide, low-k dielectrics (k<silicon oxide), nitride liners, silicon oxide,. These plies are formed on an isolation cap <NUM> having openings above connection parts of the lower single level layer copper lines <NUM>, <NUM>. The dielectric layers 105a, 105b, 105c of the multilevel layer comprise openings or trenches 105d, 105e provided for forming the M1 layer copper lines as in <FIG> where line <NUM> comprises a junction part 106a extending below to contact the first layer line <NUM> and where line <NUM> is a three level line that contacts line <NUM> of the first layer.

The process between steps 7A, 7B and 7C may be a traditional dual damascene process known for self-aligned via, but with larger height for the line parts.

In <FIG> a mask <NUM> is defined through lithography to reveal part of the metal line <NUM> and in <FIG>, an upper part of the line <NUM> is removed through metal etch back also known as metal recess in order to leave a connection pad 106b on the upper level of layer M1 and a line <NUM> (which can be longer than represented) extending in the middle level of layer M1.

In <FIG>, the mask <NUM> is removed, a dielectric filler <NUM> finishes the M1 layer and a cap layer <NUM> is added to finish the layer.

Obviously lines <NUM>, <NUM> can be built anywhere inside the layer, the drawings showing exposed lines for comprehension only.

<FIG> represent a process where two isolated separate lines are created above one another in a routing track inside the M1 layer, and a thick line <NUM> is provided.

<FIG> is the same starting point than <FIG> and represents two transverse lines <NUM>, <NUM> present on a first layer having dielectric <NUM>. In <FIG> the same construction applies for dielectric layers 205a, 205b, 205c and conductive lines <NUM>, <NUM> than in <FIG> for the layers 105a, 105b, 105c and lines <NUM>, <NUM>.

In <FIG> a mask using lithography is provided, such mask leaving an exposed metal upper part of line <NUM>. In <FIG>, deep metal etch back removes the upper layers of line <NUM> to create a trench <NUM> and in <FIG> dielectric material <NUM> is filled in the trench <NUM> and the mask is removed. In <FIG> the upper layer of the added dielectric is removed <NUM> to provide an insulating spacer <NUM> and in <FIG> an upper conductive <NUM> line is deposited thus having finished lower line 207a under upper line <NUM>. Further steps such as similar steps than steps 7D to 7F can then be added.

<FIG> show another example of building a multilevel layer where a line comprises down and up extensions on a previous layer.

<FIG> describes a first layer with two metal lines <NUM>, <NUM> and dielectric <NUM>. <FIG> represents building a first level of the multilevel layer in an intermediate step after dielectric <NUM> deposition, mask <NUM> deposition using lithography and dielectric etching. The dielectric etching creates recesses in the dielectric to provide connecting locations to the lines of the former level.

In <FIG>, a three level metal layer is deposited, and the top of the metal layer is polished through chemical mechanical planarization.

In <FIG>, mask elements are deposited on top of the metal layer using a lithographic process and in <FIG> the metal is etched using direct metal etching. As can be seen, this process provides self-alignment of the bottom extension 308a of line <NUM> with line <NUM>. The bottom extension becomes a connecting pad to the line <NUM> under the multilevel layer.

In <FIG>, the layer is filled with dielectric and the top of the layer is polished through chemical mechanical planarization.

In <FIG> a further mask <NUM> is defined using lithography allowing to recess the line <NUM> to create a pad 308b which is again self-aligned with the line which is now finished with its bottom and up pads self-aligned and having planar sidewalls from the bottom to the top. In <FIG> a last step of filling the recess with dielectric and chemical mechanical planarization is done.

All these process examples show that self-alignment of the extensions which provide connection pads between layers is directly obtained since metal is deposited in the multilevel structure and removed where not needed.

Realization of contact between lines in the layers or between layers in such described process uses masks, metal deposition and metal etching in order to form pads providing a connection only where both extensions overlap. This increases the available margins with respect to the alignment of the connection points between metallization layers.

As disclosed in the figures, building multilevel lines uses deposits of metal in trenches providing directly self-alignment of the line parts in the levels.

To summarize, in the manufacturing process, conductive parts may be formed by dual damascene processing thereby aligning the sidewalls, providing a lithographic pattern <NUM> as in <FIG>, exposing conductive parts <NUM> in the dual damascene stack and etch-back of exposed conductive parts thereby forming a trench <NUM> as in <FIG>, and filling the trench with a dielectric material <NUM> as in <FIG>.

A similar approach is used in <FIG> where lithographic pattern <NUM> exposes metal line <NUM>, etch back of conductive part to provide trench <NUM> which is filled with dielectric <NUM>.

The process may provide further selectively removing the upper portion of the dielectric material <NUM> in the trench as in <FIG> and filling the upper portion <NUM> of the trench <NUM> with conductive material <NUM> to realize an upper line in the multilevel layer above a lower line 207a.

Conductive parts may also be formed by depositing a stack of conductive material(s) <NUM> as in <FIG>, with lithographic masks 307a, 307b patterning the conductive stack <NUM>, <NUM> through metal etch back as shown in <FIG>, forming a dielectric stack <NUM> surrounding the conductive stack as in <FIG> thereby leaving the upper surface of the conductive stack exposed, providing a lithographic pattern <NUM> as in <FIG> exposing part of the upper surface and etch-back of exposed part of the upper portion of the conductive stack thereby forming a trench <NUM> as in <FIG>, and filling the trench with a dielectric material <NUM> as in <FIG>.

In the process, a stack of conductive material(s) <NUM> can be deposited on a patterned dielectric layer <NUM> as in <FIG> and a stack of patterned dielectric material 205a, 205b, 205c can be provided for depositing conductive material <NUM>, <NUM> in trenches as in <FIG>.

In the manufacturing process, upward extensions of said conductive lines may be provided as in <FIG> through provision of lithography masking <NUM> and metal etch-back <NUM> of exposed conductive lines.

Selective downward extensions can be created by a first step of depositing and patterning an isolating layer as layers 105a, 105b, 105c in <FIG> or layer <NUM> in <FIG>, a second step of depositing metal on the patterned isolation layer such as line <NUM> with downward extension 106a in <FIG> or three level layer <NUM> in <FIG>.

The invention permits to realize complex multilevel wirings in integrated circuits without using complex via systems.

Claim 1:
An integrated circuit comprising an interconnection system which comprises a multilevel routing track
the multilevel routing track comprising at least a first (<NUM>) and a second (<NUM>) conductive line,
wherein each of the first and the second conductive line comprises conductive parts (31a, 31b, 31c) extending in parallel in at least three levels including a lower extension line level (L0), a centerline level (L1) arranged directly above the lower extension line level and an upper extension line level (L2) arranged directly above the centerline level,
wherein the conductive parts in said three levels have longitudinal sidewalls that are coplanar;
wherein a first of the conductive parts (31c) of the first conductive line is arranged in the lower extension line level;
wherein a first of the conductive parts (<NUM>) of the second conductive line is arranged in the upper extension line level;
the first conductive part of the first conductive line and the first conductive part of the second conductive line being separated by an insulating layer (<NUM>) arranged in the centerline level;
the first conductive part of the first conductive line being connected to a first crossing conductive line (<NUM>) under the first conductive part of the first conductive line, and the first conductive part of the second conductive line being connected to a second crossing conductive line (<NUM>) over the first conductive part of the first conductive line.