Patent Description:
The present application relates to the field of semiconductor technologies, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure.

With the development of semiconductor structures, the critical dimensions of the semiconductor structures are decreasing. However, due to the restriction of lithography machines, there is a limit to the scaling down of the critical dimensions of the semiconductor structures. Therefore, the researchers and practitioners in the semiconductor field are committed to manufacturing a chip with higher storage density by a wafer. In the two-dimensional or planar semiconductor devices, the memory cells are arranged in the horizontal direction. Thus the integration density of the two-dimensional or planar semiconductor device can be determined by the area occupied by a unit memory cell, and the integration density of the two-dimensional or planar semiconductor devices is greatly influenced by the technologies of forming fine patterns, which causes the limitation to the continuous increasing of the integration density of the two-dimensional or planar semiconductor devices. Therefore, the semiconductor devices are developing towards three-dimensional semiconductor devices.

However, with the increasing of the integration density of the semiconductor structure, the reduced spacing between adjacent memory cells causes that the adjacent memory cells are prone to interfere with each other, thereby leading to a deterioration of the electrical performance of the semiconductor structure. Thus it is difficult to achieve a balance between the integration density and the electrical performance of the semiconductor structure.

Document <CIT> discloses a memory device having gate wraparound structures with channels and bit lines extending along two different axes.

Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are at least beneficial to improving the electrical performance and the integration density of the semiconductor structure at the same time.

According to some embodiments of the present application, one aspect of the embodiments of the present application provides a semiconductor structure, comprising: semiconductor channels extending in a third direction, first gate structures, second gate structures and bit lines. Each of the semiconductor channels has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction. Each of the first gate structures is in contact with the first face. Each of the second gate structures is in contact with the second face. Each of the first gate structures is in contact with a respective one of the second gate structures, and forms a combined structure together with the respective one of the second gate structures. The combined structure has an L-shaped cross-section in the plane perpendicular to the third direction. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction. The first direction, the second direction and the third direction intersect with each other.

In some embodiments, the semiconductor channels are arranged at intervals in the first direction, and adjacent semiconductor channels are arranged axisymmetrically.

In some embodiments, each of the first gate structures and each of the second gate structures are in a one-to-one correspondence with the semiconductor channels. The semiconductor structure further comprises third gate structures and fourth gate structures, each of the third gate structures is in contact with ends of two adjacent second gate structures in the first direction, which are away from the respective first gate structure. Each of the fourth gate structures is in contact ends of two adjacent first gate structures in the first direction, which are away from the respective second gate structure. Gate structures are formed in the semiconductor structure, each of gate structures is formed by at least one of the first gate structures, at least one of the second gate structures, at least one of the third gate structures and at least one of the fourth gate structures.

In some embodiments, for every three adjacent semiconductor channels in the first direction, a neighboring pair among the adjacent semiconductor channels is in contact with a same second gate structure, and another neighboring pair among the adjacent semiconductor channels is in contact with a same first gate structure. The first gate structures and the second gate structures are alternately arranged in the first direction. Each of gate structures is formed by at least one of first gate structures and at least one of the second gate structures.

In some embodiments, the semiconductor channels are arranged at intervals in the first direction, and only one first face is provided between two adjacent second faces in the first direction, the first gate structures and the second gate structures are in a one-to-one correspondence with the semiconductor channels, each of the second gate structures is in contact with two adjacent first gate structures in the first direction. Each of the gate structures is formed by at least one of the first gate structures and at least one of the second gate structures.

In some embodiments, the semiconductor channels are arranged at intervals in the first direction and the second direction. The semiconductor channels arranged at intervals in the second direction are in a one-to-one correspondence with the gate structures. Spacings are provided between adjacent gate structures in the second direction.

In some embodiments, adjacent semiconductor channels in the second direction are arranged centrosymmetrically or axisymmetrically. Each of the bit lines is contact with and connected to the semiconductor channels arranged at intervals in the second direction.

In some embodiments, adjacent semiconductor channels in the second direction are arranged centrosymmetrically. Every two adjacent semiconductor channels in the second direction define a reference structure. Two second faces of the reference structure are located in the spacing between two first faces. The semiconductor structure further comprises: first isolation layers in contact with both of two second L-shaped sidewalls in the reference structure, and second isolation layers located between adjacent first isolation layers in the first direction. The first isolation layers are in contact with the second isolation layers, and the first isolation layers and the second isolation layers are alternately arranged in the first direction.

In some embodiments, a length of each one of the first isolation layers in the second direction is a first length. A length of each one of the second isolation layers in the second direction is a second length. A ratio of the second length to the first length ranges from <NUM>/<NUM> to <NUM>/<NUM>.

In some embodiments, each of the gate structures comprises a gate dielectric layer and a gate. The gate dielectric layer is disposed on the first face and the second face. The gate dielectric layer is in a one-to-one correspondence with each one of the semiconductor channels. The gate dielectric layer has an L-shaped cross-section in the plane perpendicular to the third direction. The gate is disposed on a side of the gate dielectric layer away from each one of the semiconductor channels.

In some embodiments, each of the bit lines comprises a first sub-bit line and a second sub-bit line which are spaced from each other in the first direction and extend in the second direction. The semiconductor structure further comprises insulation layers each located between the first sub-bit line and the second sub-bit line.

In some embodiments, a material of the semiconductor channel comprises silicon or silicon germanium.

In some embodiments, the semiconductor structure further comprises capacitive structures, each of the capacitive structures is at least in contact with a side of the respective semiconductor channel away from the bit lines in the third direction.

According to some embodiments of the present application, another aspect of the embodiments of the present application provides a manufacturing method for a semiconductor structure, comprising operations of: forming semiconductor channels extending in a third direction, in which each of the semiconductor channels has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction; forming first gate structures and second gate structures which are in contact with each other, in which each of the first gate structure is in contact with the first face, each of the second gate structure is in contact with the second face, and forms a combined structure together with a respective one of the second gate structures, the combined structure has an L-shaped cross-section in the plane perpendicular to the third direction; and forming bit lines extending in the second direction and located on a side of each of the semiconductor channels in the third direction. The first direction, the second direction and the third direction intersect with each other.

In some embodiments, the operation of forming the semiconductor channels comprising operations of : forming semiconductor columns arranged at intervals in the first direction and/or the second direction; forming the semiconductor channels on sidewalls of the semiconductor columns extending in the third direction, with each of the semiconductor columns being in contact with two respective semiconductor channels, wherein every two semiconductor channels in contact with a same semiconductor column are arranged centrosymmetrically, and/or the adjacent semiconductor channels in the first direction are arranged axisymmetrically.

In some embodiments, each of the semiconductor columns has a first side and a second side opposite to each other in the second direction. A length of each of the semiconductor columns in the second direction is a third length. After the semiconductor columns are formed and before the semiconductor channels are formed, the manufacturing method further comprises operations of: forming third isolation layers and fourth isolation layers alternately located between adjacent semiconductor columns in the first direction, in which one of sidewalls of each third isolation layer which extends in the third direction is aligned with the first sides, a length of each of the third isolation layers in the second direction is less than the third length, one of sidewalls of each fourth isolation layer which extends in the third direction is aligned with the second sides, a length of each of the fourth isolation layers in the second direction is less than the third length; and forming the semiconductor channels on parts of sidewalls of the semiconductor columns extending in the third direction which are exposed by the third isolation layers and the fourth isolation layers.

In some embodiments, a ratio of the length of each of the third isolation layers in the second direction to the third length ranges from <NUM>/<NUM> to <NUM>/<NUM>, and/or a ratio of the length of each of the fourth isolation layers in the second direction to the third length ranges from <NUM>/<NUM> to <NUM>/<NUM>.

In some embodiments, before the semiconductor columns are formed, the manufacturing method comprises: providing a substrate; and forming an initial insulation layer on the substrate. The operation of forming the semiconductor columns comprises: forming the semiconductor columns on a side of the initial insulation layer away from the substrate. After the semiconductor channels are formed, the operation of forming the bit lines comprises: removing the semiconductor columns to form first grooves, and forming first isolation layers filled in the first grooves; removing the third isolation layers and the fourth isolation layers; etching the initial insulation layer through gaps provided between the adjacent semiconductor channels in the first direction, to form second grooves, at least parts of bottom surfaces of the semiconductor channels facing the substrate are exposed from the second grooves, an orthographic projection of each gap on the substrate is located in an orthographic projection of a respective one of the second grooves on the substrate, remaining parts of the initial insulation layer form insulation layers; and forming the bit lines in the second grooves, with the bit lines being in contact with at least part of bottom surfaces of the semiconductor channels facing the substrate and exposed through the second groove, each of the bit lines comprises a first sub-bit line and a second sub-bit line which are located respectively on two opposite sides of the respective insulation layer in the first direction, the first sub-bit lines and the second sub-bit lines extend in the second direction.

In some embodiments, after the semiconductor channels are formed, the forming the first gate structures and the second gate structures comprises: forming second isolation layers covering parts of sidewalls of the first isolation layers extending in the third direction and exposed from the semiconductor channels, with each of the second isolation layers being connected to adjacent first isolation layers in the first direction, sidewalls of the semiconductor channels and the first isolation layers which extend in the third direction together form a reference sidewall, the reference sidewall comprises a first region, a second region and a third region arranged in sequence in the third direction; and forming gate structures located in the second region, with each of the gate structures being in contact with a plurality of the semiconductor channels arranged at intervals in the first direction, each of the gate structures comprises at least the first gate structures and the second gate structures.

In some embodiments, the bit lines are formed before the semiconductor channels and the gate structures are formed, and the operation of forming the bit lines comprises: providing a substrate and forming the bit lines on the substrate, with the bit lines extending in the second direction and being arranged at intervals in the first direction. The operation of forming the semiconductor channels comprises: forming the semiconductor channels on sides of the bit lines away from the substrate, with a bottom surface of each semiconductor channel facing the substrate being in contact with a respective one of the bit lines.

One or more embodiments are exemplified by the figures in the corresponding drawings, and these exemplary descriptions do not constitute limitations of the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to illustrate the technical solutions in the embodiments of the application or conventional technologies more clearly, the drawings used in the embodiments will be briefly described below. It is apparent that the drawings in the following descriptions are merely some embodiments of the application. Other drawings can be assumed by those skilled in the art according to these drawings without any creative work.

The embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, a cross-section of a semiconductor channel is L-shaped in a plane perpendicular to a third direction. In this way, in case that a plurality of semiconductor channels are arranged, the L-shaped cross-section of each of the semiconductor channels is beneficial to decreasing the intervals between adjacent semiconductor channels while ensuring the larger spacings between corresponding parts of the adjacent semiconductor channels. Therefore, more semiconductor channels can be provided in unit area, so as to improve the integration density of the semiconductor structure. Moreover, larger spacings between the opposite parts of the adjacent semiconductor channels are beneficial to weakening interferences between the adjacent semiconductor channels. In the subsequent combined structure of the first and second gate structures formed based on first L-shaped sidewalls of the semiconductor channels, larger spacings between opposite parts of the adjacent combined structures can be obtained, so as to weaken the interferences between the adjacent combined structures. Therefore, the electrical performance of the semiconductor structure is improved.

Each embodiment of the present application will be described in detail below with reference to the drawings. However those skilled in the art will appreciate that in the each embodiment of the present application, numerous technical details are presented for a better understanding of the present application. However, even without these technical details and various variations and modifications based on the following embodiments, technical solutions claimed by the embodiments of the present application may also be realized.

An embodiment of the present application provides a semiconductor structure, which will be described in detail with reference to the drawings. <FIG> is a partial schematic perspective view of the semiconductor structure of an embodiment of the present application. <FIG> is a partial schematic perspective view of semiconductor channels and gate structures in a semiconductor structure of an embodiment of the present application. <FIG> are five partial schematic top views of semiconductor structures of the embodiments of the present application. <FIG> is a schematic cross-sectional view of the structure shown in <FIG> along the line AA1. <FIG> is another schematic cross-sectional view of a semiconductor structure of an embodiment of the present application along line AA1. <FIG> is another partial schematic perspective view of a semiconductor structure of an embodiment of the present application.

With Reference to <FIG>, the semiconductor structure comprises semiconductor channels <NUM> extending in the third direction Z, first gate structures <NUM>, second gate structures <NUM> and bit lines <NUM> extending in the second direction Y. Each semiconductor channel <NUM> has an L-shaped cross-section in a plane perpendicular to the third direction Z, and comprises a first L-shaped sidewall <NUM> and a second L-shaped sidewall <NUM> which are opposite to each other and extend in the third direction Z. The first L-shaped sidewall <NUM> comprises a first face <NUM> extending in a first direction X and a second face <NUM> extending in a second direction Y. Each first gate structure <NUM> is in contact with the first face <NUM>. Each second gate structure <NUM> is in contact with the second face <NUM>. The first gate structures <NUM> are in contact with the second gate structures <NUM>. The combined structure of the first gate structure <NUM> and a second gate structure <NUM> has an L-shaped cross-section in a plane perpendicular to the third direction Z. Each bit line <NUM> is located on a side of each of the semiconductor channels <NUM> in the third direction Z. The first direction X, the second direction Y and the third direction Z intersect with each other.

It should be noted that the first gate structure <NUM> and the second gate structure <NUM> may be an integrally formed structure. Since the first gate structure <NUM> and the second gate structure <NUM> are in contact with each other, the first gate structure <NUM> and the second gate structure <NUM> shown in drawings are divided by a dashed line for clarity of drawings. When dividing the first gate structure <NUM> and the second gate structure <NUM>, in some embodiments, with reference to <FIG> and <FIG>, a portion connecting the first gate structure <NUM> and the second gate structure <NUM> which correspond to a same semiconductor channel <NUM> has been put under the first gate structure <NUM>. In other embodiments, with reference to <FIG>, the portion connecting the first gate structure <NUM> and the second gate structure <NUM> which correspond to a same semiconductor channel <NUM> has been put under the second gate structure <NUM>. It can be understood that the portion connecting the first gate structure <NUM> and the second gate structure <NUM> which correspond to a same semiconductor channel <NUM> may be put under the first gate structure <NUM> or the second gate structure <NUM>, the semiconductor structure of an embodiment of the present application is not limited thereto.

Embodiments of the present application will be described in more detail below with reference to the drawings.

With reference to <FIG>, in some embodiments, the semiconductor structure comprises a plurality of the semiconductor channels <NUM> arranged at intervals in the first direction X, and adjacent semiconductor channels <NUM> are arranged axisymmetrically. The symmetry axis I is a symmetry axis between two adjacent semiconductor channels <NUM> in the first direction X. In this way, among the plurality of semiconductor channels <NUM> arranged in the first direction X, every two semiconductor channels <NUM> spaced apart by one semiconductor channel <NUM> therebetween are able to have a same arrangement orientation in the semiconductor structure. In addition, the first faces <NUM> of the semiconductor channels <NUM> arranged in the first direction X tend to be aligned with each other. Therefore, one gate structure <NUM> is common to multiple semiconductor channels <NUM> arranged in the first direction X. It can be understood that the gate structure <NUM> comprises at least a plurality of the first gate structures <NUM> and a plurality of the second gate structures <NUM>.

On a premise that the plurality of semiconductor channels <NUM> are arranged at intervals in the first direction X, and adjacent semiconductor channels <NUM> are arranged axisymmetrically, the gate structures <NUM> will be described in detail by two embodiments below.

In some embodiments, with reference to <FIG>, <FIG>, the semiconductor structure comprises a plurality of the first gate structures <NUM> and a plurality of the second gate structures <NUM>. Each of the first gate structures <NUM> and each of the second gate structures <NUM> are in a one-to-one correspondence with the semiconductor channels <NUM>. That is, each first face <NUM> is in contact with a respective first gate structure <NUM>, and each second face <NUM> is in contact with a respective second gate structure <NUM>.

The semiconductor structure may further comprise third gate structures <NUM> and fourth gate structures <NUM>. Each of the third gate structures is in contact with ends of two adjacent second gate structures <NUM> in the first direction X which are away from the first gate structure <NUM>. Each of the fourth gate structures is in contact with ends of two adjacent first gate structures <NUM> in the first direction X which are away from the second gate structure <NUM>. Each of the gate structures <NUM> is formed by at least one of the first gate structures <NUM>, at least one of the second gate structures <NUM>, at least one of the third gate structures <NUM> and at least one of the fourth gate structures <NUM>.

It can be understood that each of the gate structures <NUM>, as a whole, can form an elongated structure extending in the first direction X and having grooves. The first gate structures <NUM>, the second gate structures <NUM>, the third gate structures <NUM> and the fourth gate structures <NUM> can be integrally formed at the same time. For a single gate structure <NUM>, every two adjacent second gate structures <NUM> and a third gate structure <NUM> form a U-shaped opening.

It should be noted that the connection relationships between the first gate structures <NUM> and the semiconductor channels <NUM> will be described in detail by two embodiments below.

Each of the semiconductor channels <NUM> further comprises a third face <NUM> which is adjacent to the first face <NUM>, and opposite to the second face <NUM>. The third face <NUM> also extends in the third direction Z.

In an example, with reference to <FIG> and <FIG>, each of the fourth gate structure <NUM> is in contact with the respective first gate structures <NUM>, and is also in contact with the respective third faces <NUM>. In this way, the facing area between the gate structure <NUM> and each semiconductor channel <NUM> is increased, so as to improve a control capability of the gate structure <NUM> on the semiconductor channels <NUM>.

In another example, with reference to <FIG>, in a case that each of the fourth gate structures <NUM> is in contact with the respective first gate structures <NUM>, each of the third faces <NUM> is in contact with a respective one of second isolation layers <NUM>, which will be described in detail later.

It can be understood that the gate structure <NUM> may be or may not be in contact with the third faces <NUM> in the semiconductor structure, which can be flexibly adjusted according to an actual requirement.

In some other embodiments, with reference to <FIG>, for every three adjacent semiconductor channels <NUM> in the first direction X, a neighboring pair among the three adjacent semiconductor channels <NUM> is in contact with a same second gate structure <NUM>, and another neighboring pair among the three adjacent semiconductor channels <NUM> is in contact with a same first gate structure <NUM>. The first gate structures <NUM> and the second gate structures <NUM> are alternately arranged in the first direction X. Each of the gate structures <NUM> is formed by at least one of the first gate structures <NUM> and at least one of the second gate structures <NUM>.

It can be understood that each second gate structure <NUM> is in contact with two adjacent second faces <NUM> in the first direction X, and each first gate structure <NUM> is in contact with two adjacent first faces <NUM> in the first direction X. In addition, each gate structure <NUM> may form an elongated structure extending in the first direction X and having protrusions. The first gate structures <NUM> and the second gate structures <NUM> may be formed in one piece. It should be noted that, in an example shown in <FIG>, the first gate structure <NUM> is in contact with respective first faces <NUM>, and in contact with respective third faces <NUM> and a respective one of the second isolation layers <NUM>. In actual application, each of the first gate structures <NUM> can be only in contact with the first faces <NUM> and the second isolation layer <NUM>, and each of the third faces <NUM> is in contact with and connect to the second isolation layers <NUM>.

It should be noted that, in the example shown in <FIG>, adjacent semiconductor channels <NUM> arranged at intervals in the first direction X are arranged axisymmetrically. Thus there may be only one second gate structure <NUM> or only one first gate structure <NUM> between every two adjacent second faces <NUM> in the first direction X. That is, there may be no first face <NUM> or there may be two first faces <NUM> located between the adjacent second faces <NUM> in the first direction X.

In some embodiments, with reference to <FIG> and <FIG>, a plurality of the semiconductor channels <NUM> are arranged at intervals in the first direction X. A first face130 is provided between two adjacent second faces <NUM> in the first direction X. The of the first gate structures <NUM> and the second gate structures <NUM> are in a one-to-one correspondence with the semiconductor channels <NUM>. Each of the second gate structures <NUM> is in contact with two adjacent first gate structures <NUM> in the first direction. Each of the gate structures is formed by at least one of the first gate structures <NUM> and at least one of the second gate structures <NUM>.

It can be understood that, in examples shown in <FIG> and <FIG>, the semiconductor channels <NUM> arranged at intervals in the first direction X have a same arrangement orientation, such that the first faces <NUM> of the semiconductor channels <NUM> arranged in the first direction X tend to be aligned with each other. Therefore, one gate structure is common to the plurality of semiconductor channels <NUM> arranged in the first direction X.

On a premise that the plurality of semiconductor channels <NUM> are arranged at intervals in the first direction X, and adjacent semiconductor channels <NUM> are not arranged axisymmetrically, the gate structures <NUM> will be described in detail by two embodiments below.

In an example, with reference to <FIG>, each of the second gate structures <NUM> is in contact with two adjacent first gate structures <NUM> in the first direction X, and also in contact with at least the third face <NUM>. In this way, an area of the gate structure <NUM> directly facing the respective semiconductor channels <NUM> can be increased, so as to improve a control capability of the gate structures <NUM> on the semiconductor channels <NUM>. It should be noted that in the example shown in <FIG>, there is an interval space between the second face <NUM> of one of two adjacent semiconductor channels <NUM> and the third face <NUM> of the other of the two adjacent semiconductor channels <NUM>, and the interval space is filled by the respective second gate structure <NUM>. In actual application, in the arranging manner of the semiconductor channels <NUM> shown in <FIG>, and in a case of the gate structure <NUM> in contact with the first faces <NUM>, the second faces <NUM> and the third faces <NUM>, the gate structure <NUM> may further comprises other gate structures in addition to the first gate structures <NUM> and the second gate structures <NUM>. The specific configuration of the gate structure <NUM> is not limited.

In another example, with reference to <FIG>, each of the first gate structures <NUM> is in contact with the first face <NUM>, and also in contact with the second isolation layer <NUM>. That is, a length of each of the first gate structures <NUM> in the first direction X is greater than a length of the semiconductor channel <NUM> corresponding to this first gate structure <NUM> in the first direction X. Furthermore, the second isolation layer <NUM> is in contact with the third face <NUM>. It should be noted that, in the arranging manner of the semiconductor channels <NUM> shown in <FIG>, in a case of the gate structure <NUM> in contact with the first faces <NUM> and the second faces <NUM>, the gate structure <NUM> may further comprises other gate structures in addition to the first gate structures <NUM> and the second gate structures <NUM>. That is, the specific configuration of the gate structure <NUM> is not limited.

It should be noted that in the example shown in <FIG> and <FIG>, there are <NUM> semiconductor channels <NUM> arranged at intervals in the first direction X. In actual application, the number of semiconductor channels <NUM> arranged at intervals in the first direction X is not limited, and for example, may be <NUM>, <NUM>, <NUM> etc..

In the above embodiments, with reference to <FIG> and <FIG>, the semiconductor structure comprises a plurality of the semiconductor channels <NUM> arranged at intervals in the second direction Y. Each of the semiconductor channels <NUM> arranged at intervals in the second direction Y is in a one-to-one correspondence with the gate structures <NUM>. Spacings are provided between adjacent gate structures <NUM> in the second direction Y.

It can be understood that the L-shape of each of the semiconductor channels <NUM> is beneficial to increasing the integration density of the semiconductor channels <NUM> and increasing the intervals between the adjacent first gate structures <NUM> in the second direction Y, so as to mitigate the interferences between the adjacent gate structures <NUM>.

In some embodiments, with reference to <FIG> and <FIG>, adjacent semiconductor channels <NUM> in the second direction Y are arranged centrosymmetrically. A symmetry point II is a symmetry point of two adjacent semiconductor channels <NUM> in the second direction Y.

It can be understood that, as the adjacent semiconductor channels <NUM> in the second direction Y are arranged centrosymmetrically, two second faces <NUM> of some of adjacent semiconductor channels <NUM> in the second direction Y are located between two respective first faces <NUM> due to the L-shapes of the semiconductor channels <NUM>, such that two second gate structures <NUM> corresponding to two semiconductor channels <NUM> adjacent in the second direction Y are located between the two respective first faces <NUM>. Thereby overall spaces occupied by adjacent semiconductor channels <NUM> in the second direction Y in the semiconductor structure are reduced, and an integration density of the semiconductor channels <NUM> is improved. In addition, with reference to <FIG> and <FIG> to <NUM>, semiconductor channels <NUM> adjacent in the first direction X are arranged axisymmetrically and semiconductor channels <NUM> adjacent in the second direction Y are arranged centrosymmetrical. Thus, the second gate structures <NUM> of one of two adjacent gate structures <NUM> in the second direction Y and second gate structures <NUM> of the other of two adjacent gate structures <NUM> in the second direction Y are staggered in the first direction X, so as to increase the spacing between two second gate structures <NUM> opposite in the second direction Y. Therefore, the integration density of the semiconductor channels <NUM> in the semiconductor structure is improved. Intervals between the first gate structures <NUM> opposite in the second direction Y are decreased, and intervals between the second gate structures <NUM> opposite in the second direction Y are also decreased, so as to weaken interferences between adjacent gate structures <NUM> and improve the electrical performance of the semiconductor structure.

In actual application, adjacent semiconductor channels <NUM> in the second direction Y can be arranged axisymmetrically. That is, the arrangements of the semiconductor channels <NUM> in the first direction X and in the second direction Y are not limited in the semiconductor structure of an embodiment of the present application, as long as "a same gate structure <NUM> is common to a plurality of the semiconductor channels <NUM> are arranged at intervals in the first direction X, each of a plurality of the semiconductor channels <NUM> arranged at intervals in the second direction Y is in a one-to-one correspondence with the gate structures <NUM>, and intervals are arranged between adjacent gate structure <NUM> in the second direction Y".

In above embodiments with reference to <FIG>, <FIG>, <FIG>, a single bit line <NUM> may be in contact with multiple semiconductor channels <NUM> arranged at intervals in the second direction Y.

It should be noted that in examples in <FIG>, <FIG>, and <FIG>, the number of the semiconductor channels <NUM> arranged at intervals in the second direction Y is <NUM>. In <FIG>, <FIG>, the number of the semiconductor channels <NUM> arranged at intervals in the second direction Y is <NUM>. In actual application, the number of semiconductor channels <NUM> arranged at intervals in the second direction Y is not limited, and may be <NUM>, <NUM>, <NUM>, etc..

In above embodiments with reference to <FIG> and <FIG>, the adjacent semiconductor channels <NUM> in the second direction Y are arranged centrosymmetrically. Every two adjacent semiconductor channels <NUM> in the second direction Y define a reference structure <NUM>. Two second faces <NUM> of the reference structure are located in the spacing between two first faces <NUM>. The semiconductor structure may further comprises: first isolation layers <NUM> in contact with two second L-shaped sidewalls <NUM> of in the reference structure160, and second isolation layers <NUM> in contact with two second L-shaped sidewalls <NUM> of a respective one of the reference structures160, each of the second isolation layers is located between adjacent first isolation layers <NUM> in the first direction X. The first isolation layers <NUM> are in contact with the second isolation layers <NUM>, and the first isolation layers <NUM> and the second isolation layers <NUM> are alternately arranged in the first direction X (i.e. arranged one after another in the first direction X).

In the semiconductor structure, each of the first isolation layers <NUM> is configured to provide the insulation between two semiconductor channels <NUM> in contact with this first isolation layer. Each of the second isolation layers <NUM> is configured to provide the insulation between adjacent respective gate structures <NUM> in the second direction Y and respective semiconductor channels <NUM>.

It can be understood that each of the first isolation layers <NUM> can be a rectangular prism with four corners. Each of the first isolation layers <NUM> may be in contact with two semiconductor channels <NUM>. In the examples shown in <FIG>, every two semiconductor channels <NUM> corresponding to a same first isolation layer <NUM> are respectively located at two corners of the first isolation layer <NUM> which are furthest from each other, so as to increase an overall spacing between the two semiconductor channels <NUM>. In actual application, every two semiconductor channels <NUM> corresponding to a same first isolation layer <NUM> may be respectively located at any two corners of the first isolation layer <NUM>.

The second isolation layers <NUM> in various embodiments will be described in detail below respectively.

In some embodiments, with reference to <FIG>, <FIG>, <FIG>, each of the second isolation layers <NUM> is located between adjacent first isolation layers <NUM> in the first direction X, and between two gate structures <NUM> corresponding to a reference structure <NUM>. Each of the second isolation layers <NUM> is not in contact with or connected to the third face <NUM>, and each of the gate structures <NUM> is in contact with the third faces <NUM>.

In other embodiments, with reference to <FIG> and <FIG>, each of the second isolation layers <NUM> is located between adjacent first isolation layers <NUM> in the first direction X, and between two gate structures <NUM> corresponding to a reference structure <NUM>. Each of the second isolation layers <NUM> is in contact with the third faces <NUM>.

It can be understood that arrangement of the second isolation layers <NUM> varies according to that of the gate structures <NUM>, to provide insulation between the adjacent gate structures <NUM> in the second direction Y and the semiconductor channels <NUM>.

In some embodiments, with reference to <FIG>, <FIG>, and <FIG>, a length of each of the first isolation layers <NUM> in the second direction Y is a first length. A length of each of the second isolation layers <NUM> in the second direction Y is a second length. A ratio of the second length to the first length ranges from <NUM>/<NUM> to <NUM>/<NUM>. On the one hand, since the ratio of the second length to the first length is greater than or equal to <NUM>/<NUM>, every two semiconductor channels <NUM> in contact with a same first isolation layer <NUM> do not have regions directly facing each other, thereby reducing the interference between said two semiconductor channels <NUM>, such as the parasitic capacitance between them. On the other hand, since the ratio of the second length to the first length is less than or equal to <NUM>/<NUM>, it is convenient to provide semiconductor channels <NUM> with a large size, thereby ensuring that gate structure <NUM> and the semiconductor channels <NUM> have sufficient areas directly facing each other.

In some embodiments, with reference to <FIG>, each of the gate structures <NUM> comprises a gate dielectric layer <NUM> and a gate <NUM>. The gate dielectric layer <NUM> is disposed on the first face <NUM> and second face <NUM>. The gate dielectric layer <NUM> is in a one-to-one correspondence with the semiconductor channels <NUM>. The gate dielectric layer <NUM> has an L-shaped cross-section in a plane perpendicular to the third direction Z. The gate <NUM> is disposed on a side of the gate dielectric layer <NUM> away from each of the semiconductor channels <NUM>. It can be understood that in an example shown in <FIG>, only the first gate structures <NUM> and the second gate structures <NUM> comprise the gate dielectric layer <NUM>. Each of the third gate structures <NUM> and the fourth gate structures <NUM> is formed only by the gate <NUM>. That is, for a single gate structure <NUM>, the gate structure may comprise a plurality of the gate dielectric layers <NUM> arranged axisymmetrically in the first direction and a gate <NUM> common to the plurality of gate dielectric layers <NUM>.

It should be noted that the arrangement manner of the gate dielectric layer <NUM> and the gate <NUM> in the gate structures <NUM> shown in <FIG> is also applicable to the examples shown in <FIG>, <FIG>, and <FIG>. In addition, in actual application, a same gate dielectric layer <NUM> may also be common to the plurality of semiconductor channels <NUM> arranged at intervals in the first direction X while ensuring that the gate dielectric layer <NUM> is located on the first face <NUM> and the second face <NUM>,.

The semiconductor structure further comprises a substrate <NUM> located on the side of the bit lines <NUM> away from the semiconductor channels <NUM>.

The bit lines <NUM> are described in detail below through following embodiments.

In some embodiments, with reference to <FIG>, for a single bit line <NUM>, the bit line <NUM> is a single layer structure. In addition, an orthographic projection of each semiconductor channel <NUM> on the substrate <NUM> is located in an orthographic projection of respective bit line <NUM> on the substrate <NUM>. That is, an entire bottom surface of each semiconductor channel <NUM> facing the substrate <NUM> is in contact with the respective bit line <NUM>, which facilitates increasing a contact area between the bit line <NUM> and the respective semiconductor channel <NUM>. Therefore a contact resistance between the bit line <NUM> and the respective semiconductor channel <NUM> is reduced, so as to improve the electrical performance of the semiconductor structure. In an example, a material of the bit lines <NUM> can be a doped semiconductor material, such as a silicon material doped with N-type ions or P-type ions. Specifically, the N-type ions may be at least one of arsenic ions, phosphorus ions or antimony ions, and the P-type ions may be at least one of boron ions, indium ions, or gallium ions.

In other embodiments, with reference to <FIG>, each of the bit lines <NUM> comprises a first sub-bit line <NUM> and a second sub-bit line <NUM> which are spaced from each other in the first direction X, the first sub-bit line <NUM> and the second sub-bit line <NUM> extend in the second direction Y. The semiconductor structure further comprises insulation layers <NUM> each located between the first sub-bit line <NUM> and the second sub-bit line <NUM>. In an example, materials of the bit lines <NUM> comprises at least one of metallic materials such as tungsten, aluminum, titanium, or tantalum, or at least one of conductive materials such as titanium nitride, tantalum nitride, or tungsten nitride.

In some embodiments, a material of the semiconductor channels <NUM> comprises silicon or silicon germanium. In an example, the material of the semiconductor channels <NUM> is silicon germanium, which facilitates improving the carrier mobility of the channel regions in the semiconductor channels <NUM> through silicon germanium, so as to increase an on/off ratio of a transistor formed by the gate structures <NUM> and the semiconductor channels <NUM>. Therefore, the electrical performance of the semiconductor structure can be improved. The channel region in the semiconductor channel <NUM> refers to the semiconductor channels <NUM> in contact with the gate structure <NUM>.

In some embodiments, with reference to <FIG>, the semiconductor structure may further comprise capacitive structures <NUM>, each of which at least in contact with a side of the respective semiconductor channel <NUM> away from the respective bit line <NUM>. It can be understood that each of the capacitive structures <NUM> is in a one-to-one correspondence with the semiconductor channels <NUM>. In examples shown in <FIG>, the integration density of the semiconductor channels <NUM> in the semiconductor structure is improved. Therefore the integration density of the capacitive structures <NUM> in the semiconductor structure is also improved.

It should be noted that <FIG> shows the capacitor structures <NUM> added on the basis of the semiconductor structure of <FIG>. It can be understood that in the examples shown in <FIG>, in case that adjacent capacitive structures <NUM> are arranged at intervals. The application is not limited to the specific arrangement of the capacitive structures <NUM>, as long as a contact area between the capacitive structure <NUM> and the side of the respective semiconductor channel <NUM> away from the substrate <NUM> is increased as much as possible.

To sum up, the semiconductor channel <NUM> has an L-shaped cross-section in the plane perpendicular to the third direction Y. In this way, in case that a plurality of semiconductor channels <NUM> are arranged, the L-shaped cross-section of each of the semiconductor channels <NUM> is beneficial to decreasing intervals between whole adjacent semiconductor channels <NUM> while ensuring a larger spacing between opposite parts of the adjacent semiconductor channels <NUM>. Therefore, a larger number of semiconductor channels <NUM> can be provided in per unit area, so as to improve the integration density of the semiconductor structure. Moreover, larger spacing between the opposite parts of the adjacent semiconductor channels <NUM> is beneficial to weakening the interference between the adjacent semiconductor channels <NUM>. In the combined structures of the first gate structures <NUM> and the second gate structures <NUM> formed based on the first L-shaped sidewalls <NUM> of the semiconductor channels <NUM>, larger spacing between opposite parts of the adjacent combined structures can be obtained, so as to weaken interferences between the adjacent combined structures. Therefore, the electrical performance of the semiconductor structure is improved.

Another embodiment of the present application further provides a manufacturing method of a semiconductor structure, which is used for manufacturing the semiconductor structure of the above embodiments. The manufacturing method of the semiconductor structure of another embodiment of the present application will be described in detail below with reference to <FIG>. <FIG> are partial schematic views, each of which corresponds to a respective operation of the manufacturing method of the semiconductor structure of the embodiment of the present application.

It should be noted that identical or corresponding parts with above embodiments will not be repeated here. <FIG> and <FIG> are schematic perspective views, each of which corresponds to the respective operation of the manufacturing method of the semiconductor structure. <FIG> is a schematic cross-sectional view of <FIG> along line AA1. <FIG> is a schematic cross-sectional view corresponding to an operation in the manufacturing method of the semiconductor structure of the embodiment of the present application.

With reference to <FIG>, the manufacturing method of the semiconductor structure comprises an operation of forming semiconductor channels <NUM> extending in a third direction Z. Each semiconductor channel <NUM> has an L-shaped cross-section in a plane perpendicular to the third direction Z, and comprises a first L-shaped sidewall <NUM> and a second L-shaped sidewall <NUM> which are opposite to each other and extend in the third direction Z. The first L-shaped sidewall <NUM> comprises a first face <NUM> extending in a first direction X and a second face <NUM> extending in a second direction Y. The method also comprises an operation of forming first gate structures <NUM> and second gate structures <NUM> which are in contact with each other. Each first gate structure <NUM> is in contact with the first face <NUM>, each second gate structure <NUM> is in contact with the second face <NUM>. A combined structure formed by the first gate structure <NUM> and the second gate structure <NUM> has an L-shaped cross-section in the plane perpendicular to the third direction Z. The method also comprises an operation of forming bit lines <NUM> extending in the second direction Y and located on a side of the semiconductor channel <NUM> in the third direction Z. The first direction X, the second direction Y and the third direction Z intersect with each other.

It should be noted that the first gate structure <NUM> and the second gate structure <NUM> are formed after the formation of the semiconductor channel <NUM>. In another embodiment of the present application, a sequence of the formation of the semiconductor channel <NUM> and the formation of the bit line <NUM> is not limited and can be adjusted according to the actual requirement. The manufacturing method of the embodiment of the present application comprises but is not limited to specific examples of the manufacturing method for the semiconductor structure in the following description.

In some embodiments, with reference to <FIG> or <FIG>, the operation of forming the semiconductor channels <NUM> may comprise: forming semiconductor columns <NUM> arranged at intervals in the first direction X and/or the second direction Y. A material of the semiconductor columns <NUM> may be a semiconductor material such as silicon or silicon germanium.

It can be understood that by means of the semiconductor columns <NUM>, the semiconductor channels <NUM> each located on a part of the sidewall of the respective semiconductor column <NUM> extending in the third direction Z will be subsequently formed. Therefore, an arrangement manner of the semiconductor columns <NUM> generally determines an arrangement manner of the semiconductor channels <NUM>. For example, if the semiconductor columns <NUM> are arranged at intervals in the first direction X, the semiconductor channels <NUM> are also arranged at intervals in the first direction X; if the semiconductor columns <NUM> are arranged at intervals in the second direction Y, the semiconductor channels <NUM> are also arranged at intervals in the second direction Y.

It should be noted that in an example of <FIG> and <FIG>, four semiconductor columns <NUM> are arranged at intervals in the first direction X. In actual application, the number of semiconductor columns <NUM> arranged at intervals in the first direction X is not limited. Furthermore, a plurality of the semiconductor columns <NUM> may also be arranged at intervals in the second direction Y, or a plurality of the semiconductor columns <NUM> may be arranged at intervals in the first direction X and arranged at intervals in the second direction Y. In addition, the present application is not limited to a specific process for forming the plurality of semiconductor columns <NUM>.

A sequence of the formation of the semiconductor columns <NUM> and the formation of the bit lines <NUM> will be described in detail below through following embodiments.

In some embodiments with reference to <FIG>, the bit lines <NUM> are formed prior to the formation of the semiconductor channels <NUM> and the gate structures <NUM>, i.e. prior to the formation of the semiconductor columns <NUM>. The operation of forming the bit lines <NUM> may comprise: providing a substrate <NUM>; and forming, bit lines <NUM> extending in the second direction Y and arranged at intervals in the first direction X, on the substrate <NUM>.

It will be understood that, in some embodiments, the substrate <NUM>, the bit lines <NUM> and the semiconductor columns <NUM> have same semiconductor chemical elements. Therefore, the substrate <NUM>, the bit lines <NUM> and the semiconductor columns <NUM> may be formed by a same film structure composed of the semiconductor chemical elements. Thereby a process for forming the bit lines <NUM> is simplified. In addition, a material of the bit lines <NUM> may be doped semiconductor material, such as silicon material doped with N-type ions or P-type ions.

With reference to <FIG> and <FIG>, the operation of forming the semiconductor channels <NUM> may comprise: forming the semiconductor channels <NUM> on a side of the bit lines <NUM> away from the substrate <NUM>, with a bottom surface of each semiconductor channel <NUM> facing the substrate <NUM> being in contact with the respective bit line <NUM>.

With reference to <FIG>, after the bit lines <NUM> are formed and before the semiconductor columns <NUM> are formed, the manufacturing method further comprises: forming first dielectric layers <NUM> each located between adjacent bit lines <NUM> to provide the insulation between adjacent bit lines <NUM>.

In other embodiments, with reference to <FIG>, before the semiconductor columns <NUM> are formed, the manufacturing method may further comprise: providing a substrate <NUM>; forming an initial insulation layer <NUM> on the substrate <NUM>. In a subsequent operation, the initial insulation layer <NUM> will be etched to provide spaces for forming the bit lines <NUM>. Continue with reference to <FIG>, the operation of forming the semiconductor columns <NUM> may comprise: forming the semiconductor columns <NUM> on a side of the initial insulation layer <NUM> away from the substrate <NUM>.

With reference to <FIG>, the semiconductor channels <NUM> are formed on sidewalls of the semiconductor columns <NUM> extending in the third direction Z. Every two semiconductor channels <NUM> in contact with a same semiconductor column <NUM> are arranged centrosymmetrically, and/or adjacent semiconductor channels <NUM> in the first direction X are arranged axisymmetrically.

It can be understood that each of the semiconductor columns <NUM> may be a rectangular prism with four corners. Each of the semiconductor columns <NUM> may be in contact with two respective semiconductor channels <NUM>. Furthermore, in an example shown in <FIG>, the two semiconductor channels <NUM> corresponding to a same semiconductor column <NUM> are respectively located at two corners of the semiconductor column <NUM> which are furthest from each other, so as to increase an overall spacing between the two semiconductor channels <NUM>. In actual application, the two semiconductor channels <NUM> corresponding to a same semiconductor column <NUM> may be respectively located at any two corners of the semiconductor column <NUM>.

The operation of forming semiconductor channels comprises, but is not limited to, the following embodiments:.

In some embodiments, with reference to <FIG>, each of the semiconductor columns <NUM> has a first side <NUM> and a second side <NUM> opposite to each other in the second direction Y. A length of each semiconductor column <NUM> in the second direction Y is a third length. After the semiconductor columns <NUM> are formed and before the semiconductor channels <NUM> are formed, the manufacturing method may further comprise the operations described below.

Continue with reference to <FIG>, the operation of forming third isolation layers <NUM> and fourth isolation layers <NUM> is shown. The third isolation layers <NUM> and the fourth isolation layers <NUM> are alternately located between adjacent semiconductor columns <NUM> in the first direction X. One of sidewalls of each third isolation layers <NUM> which extends in the third direction Z is flush with the first side <NUM>. A length of each of the third isolation layers <NUM> in the second direction Y is less than the third length. One of sidewalls of each fourth isolation layers <NUM> which extends in the third direction Z is flush with the second side <NUM>. A length of each of the fourth isolation layers <NUM> in the second direction Y is less than the third length.

In some embodiments, each of two opposite end surfaces of each third isolation layer <NUM> in the third direction Z is flush with a respective one of two opposite end surfaces of each semiconductor column <NUM> in the third direction Z, respectively. Each of two opposite end surfaces of each fourth isolation layer <NUM> in the third direction Z is flush with a respective one of two opposite end surfaces of each semiconductor column <NUM> in the third direction Z, respectively. It can be understood that, in the third direction Z, top surfaces of the third isolation layers <NUM>, top surfaces of the fourth isolation layers <NUM> and top surfaces of the semiconductor columns <NUM> are flush with each other, and bottom surfaces of the third isolation layers <NUM>, bottom surfaces of the fourth isolations layer <NUM> and bottom surfaces of the semiconductor columns <NUM> are flush with each other.

Each of the semiconductor columns <NUM> has a third side <NUM> and a fourth side <NUM> opposite to each other in the first direction X. The third side <NUM> may be divided into a first region and a second region in the second direction Y. The fourth side <NUM> may be divided into a third region and a fourth region in the second direction Y. Each of the third isolation layers <NUM> may completely cover the first region(s) of the respective semiconductor column(s), and each of the fourth isolation layers <NUM> may completely cover the fourth region(s) of the respective semiconductor column(s).

With reference to <FIG>, each of the semiconductor channels <NUM> are formed on parts of sidewalls of the respective semiconductor column <NUM> extending in the third direction Z which are exposed form the third isolation layer <NUM> and the fourth isolation layer <NUM>. It can be understood that a third L-shaped sidewall may be formed by the first side <NUM> and the exposed third region, and a fourth L-shaped sidewall may be formed by the second side <NUM> and the exposed second region. One semiconductor channel <NUM> can be formed based on the third L-shaped sidewall, and another semiconductor channel <NUM> can be formed based on the fourth L-shaped sidewall. The third isolation layers <NUM> and the fourth isolation layers <NUM> serve to isolate every two semiconductor channels <NUM> from one another. Each of the second L-shaped sidewalls <NUM> of the semiconductor channels <NUM> is in contact with the third L-shaped sidewall or the fourth L-shaped sidewall.

In an example, by means of an epitaxial growth process, each of the semiconductor channels <NUM> may be formed on the exposed parts of the sidewalls of the respective semiconductor column <NUM> extending in the third direction Z.

In some embodiments, a length of each of the semiconductor columns <NUM> in the second direction Y is a third length. A ratio of the length of each of the third isolation layers <NUM> in the second direction Y to the third length ranges from <NUM>/<NUM> to <NUM>/<NUM>, and/or a ratio of the length of each of the fourth isolation layers <NUM> in the second direction Y to the third length ranges from <NUM>/<NUM> to <NUM>/<NUM>.

It can be understood that the semiconductor channels <NUM> are formed based on parts of the sidewalls of the semiconductor columns <NUM> which are not covered by the third layers <NUM> and fourth isolation layers <NUM>. Therefore, a size of the semiconductor channel <NUM> is affected by a size of the third isolation layer <NUM> and a size of the fourth isolation layer <NUM>.

In actual application, due to limitations of the manufacturing process or actual requirements, the length of the third isolation layer <NUM> in the second direction Y may be not equal to the length of the fourth isolation layer <NUM> in the second direction Y, that is, the sizes of two semiconductor channels <NUM> corresponding to a same semiconductor column <NUM> may not be identical. In other embodiments, the length of the third isolation layer <NUM> in the second direction Y may be equal to the length of the fourth isolation layer <NUM> in the second direction Y.

For the third isolation layers <NUM> or the fourth isolation layers <NUM>, on the one hand, the ratio of the length of the third isolation layer <NUM> or the fourth isolation layer <NUM> in the second direction Y to the third length is greater than or equal to <NUM>/<NUM>, so as to avoid that two semiconductor channels <NUM> in contact with adjacent third isolation layer <NUM> and fourth isolation layer <NUM> have regions directly facing each other, thereby reducing the interference between said two semiconductor channels <NUM>, such as parasitic capacitance between them. On the other hand, the ratio of the length of the third isolation layer <NUM> or the fourth isolation layer <NUM> in the second direction Y to the third length is less than or equal to <NUM>/<NUM>, such that each semiconductor channel <NUM> has a large size, thereby ensuring that the gate structure <NUM> and the semiconductor channel <NUM> have sufficient areas directly facing each other.

It should be noted that the manufacturing method of the embodiment of the present application does not limit a specific process for forming the third isolation layers <NUM> and the fourth isolation layers <NUM>. For example, an initial isolation layer which covers all sidewalls of the semiconductor columns <NUM> extending in the third direction Z is formed first, and the initial isolation layer is etched to form the third isolation layers <NUM> and the fourth isolation layers <NUM>. In addition, spaces occupied by the third isolation layers <NUM> and fourth isolation layers <NUM> will be used for forming the first isolation layers <NUM> (with reference to <FIG>). A material of the third isolation layers <NUM> may be the same as or different from a material of the fourth isolation layers <NUM>. For example, the material of the third isolation layers <NUM> and the material of the fourth isolation layer <NUM> may both be silicon oxide.

In other embodiments, the operation of forming the semiconductor channels <NUM> may comprise: forming an initial semiconductor channel (not shown) on four sidewalls of the semiconductor column <NUM> extending in the third direction Z, then etching the initial semiconductor channel by means of a mask to form the final semiconductor channel. A process for forming the initial semiconductor channel may also use the epitaxial growth process.

In some embodiments, according to above description and with reference to <FIG>, before the semiconductor columns <NUM> are formed, the manufacturing method may further comprise: providing the substrate <NUM>; and forming an initial insulation layer <NUM> on the substrate <NUM>. The operation of forming the semiconductor columns <NUM> comprises: forming the semiconductor columns <NUM> on a side of the initial insulation layer <NUM> away from the substrate <NUM>. After the semiconductor channels <NUM> are formed, the formation of the bit lines <NUM> comprises the following.

With reference to <FIG>, the semiconductor columns <NUM> are removed to form first grooves <NUM>.

With reference to <FIG> and <FIG>, the first isolation layers <NUM> filled into the first groove <NUM> are formed.

With reference to <FIG> and <FIG>, the third isolation layers <NUM> and the fourth isolation layers <NUM> are removed.

With reference to <FIG>, second dielectric layers <NUM> are formed, with gaps <NUM> being provided between the adjacent semiconductor channels <NUM> in the first direction X.

With reference to <FIG>, the initial insulation layer <NUM> is etched through the gaps <NUM> to form second grooves <NUM>. At least a part of the bottom surface of each semiconductor channel <NUM> facing the substrate <NUM> is exposed through the second grooves <NUM>. An orthographic projection of each gap <NUM> on the substrate <NUM> is located in an orthographic projection of the respective second groove <NUM> on the substrate <NUM>. Remaining part of the initial insulation layer forms the insulation layers <NUM>.

With reference to <FIG> and <FIG>, the bit lines <NUM> are formed in the second grooves <NUM>. Each of the bit lines <NUM> is in contact with at least part of the bottom surfaces of the respective semiconductor channels <NUM> facing the substrate <NUM> and exposed through the second groove <NUM>. Each of the bit lines <NUM> comprises a first sub-bit line <NUM> and a second sub-bit line <NUM> which are located respectively on two opposite sides of the insulation layer <NUM> in the first direction X. The first sub-bit lines <NUM> and the second sub-bit lines <NUM> extend in the second direction Y.

In above embodiments, with reference to <FIG>, after the third isolation layers <NUM> (with reference to <FIG>) and the fourth isolation layers <NUM> (with reference to <FIG>) are removed, the first isolation layers <NUM> are formed in spaces previously occupied by the third isolation layers <NUM> and the fourth isolation layers <NUM>. It should be noted that the manufacturing method of the embodiment of the present application does not limit the specific process for forming the first isolation layers <NUM>.

In some embodiments, with reference to <FIG>, after the semiconductor channels <NUM> are formed, the operation of forming the first gate structures <NUM> and the second gate structures <NUM> may comprise: forming the second isolation layers <NUM>. The second isolation layers <NUM> cover parts of the sidewalls of the first isolation layers <NUM> extending in the third direction Z and exposed form the semiconductor channels <NUM>. Each of the second isolation layers <NUM> is connected to adjacent first isolation layers in the first direction. It can be understood that the second isolation layers <NUM> are formed after the third isolation layers <NUM> (with reference to <FIG>) and the fourth isolation layers <NUM> (with reference to <FIG>) are removed, that is, the second isolation layers <NUM> are formed in the spaces previously occupied by the third isolation layers <NUM> and the fourth isolation layers <NUM>. It should be noted that the manufacturing method of the embodiment of the present application does not limit the specific process for forming the second isolation layers <NUM>.

With reference to <FIG> and <FIG>, the sidewalls of semiconductor channels <NUM> and the sidewalls of the first isolation layers <NUM> which extend in the third direction Z together form a reference sidewall <NUM>. The reference sidewall <NUM> comprises a first region <NUM>, a second region <NUM> and a third region <NUM> arranged successively in the third direction Z. The gate structure <NUM> is formed in the second region <NUM>. The gate structure <NUM> is in contact with a plurality of the semiconductor channels <NUM> arranged at intervals in the first direction X. The gate structure <NUM> comprises at least the first gate structures <NUM> and the second gate structures <NUM>.

It should be noted that the specific configuration of the gate structure <NUM> may be referred to the embodiment of the present application and will not be described here. Furthermore, <FIG> do not show structures such as the substrate and the bit lines etc., and the operations shown in <FIG> are applicable to two cases respectively shown in <FIG> and <FIG>. <FIG> and <FIG> merely take the substrate <NUM> and the bit lines <NUM> shown in <FIG> as examples. In actual application, the operations of forming the forming the first isolation layers <NUM> and the second isolation layers <NUM> shown in <FIG> and <FIG> are also applicable to the case shown in <FIG>. That is, the process operations of the manufacturing method shown in <FIG> and <FIG> are applicable to both cases respectively shown in <FIG> and <FIG>. Moreover, the manufacturing method of the embodiment of the present application does not limit the specific process for forming the gate structures <NUM>.

In conclusion, in the semiconductor structure produced by the manufacturing method of an embodiment of the present application, each semiconductor channel <NUM> have the L-shaped cross-section in the plane perpendicular to the third direction Y. In this way, in case that a plurality of semiconductor channels <NUM> are provided, the L-shaped cross-section of each of the semiconductor channels <NUM> is beneficial to decreasing the overall intervals between adjacent semiconductor channels <NUM> while ensuring larger spacings between opposite parts of the adjacent semiconductor channels <NUM>. Therefore, a larger number of semiconductor channels <NUM> can be provided in per unit area, so as to improve the integration density of the semiconductor structure. Moreover, larger spacing between the opposite parts of the adjacent semiconductor channels <NUM> is beneficial to weakening the interference between the adjacent semiconductor channels <NUM>. In the combined structure of the first gate structures <NUM> and the second gate structures <NUM> formed based on the first L-shaped sidewalls <NUM> of the semiconductor channels <NUM>, larger spacings between opposite parts of the adjacent combined structures can be obtained, so as to weaken the interference between the adjacent combined structures. Therefore, the electrical performance of the semiconductor structure is improved.

Claim 1:
A semiconductor structure, comprising:
semiconductor channels (<NUM>) extending in a third direction (Z), each of the semiconductor channels (<NUM>) has an L-shaped cross-section in a plane perpendicular to the third direction (Z), each of the semiconductor channels (<NUM>) comprises a first L-shaped sidewall (<NUM>) and a second L-shaped sidewall (<NUM>) which are opposite to each other and extend in the third direction (Z), the first L-shaped sidewall (<NUM>) comprises a first face (<NUM>) extending in a first direction (X) and a second face (<NUM>) extending in a second direction (Y);
first gate structures (<NUM>), each of the first gate structures (<NUM>) is in contact with the first face (<NUM>);
second gate structures (<NUM>), each of the second gate structures (<NUM>) is in contact with the second face (<NUM>), each of the first gate structures (<NUM>) is in contact with a respective one of the second gate structures (<NUM>), and forms a combined structure together with the respective one of the second gate structures (<NUM>), the combined structure has an L-shaped cross-section in the plane perpendicular to the third direction (Z); and
bit lines (<NUM>) extending in the second direction (Y) and located on a side of each of the semiconductor channels (<NUM>) in the third direction (Z);
wherein the first direction (X), the second direction (Y) and the third direction (Z) intersect with each other.