Patent Description:
By forming a network of such nanowires and inducing the topological regime in parts of the network, it is possible to create a quantum bit (qubit) which can be manipulated for the purpose of quantum computing. A quantum bit, or qubit, is an element upon which a measurement with two possible outcomes can be performed, but which at any given time (when not being measured) can in fact be in a quantum superposition of the two states corresponding to the different outcomes.

To induce MZMs, the device is cooled to a temperature where the superconductor (e.g. aluminium, Al) exhibits superconducting behaviour. The superconductor causes a proximity effect in the adjacent semiconductor, whereby a region of the semiconductor near the interface with the superconductor also exhibits superconducting properties. Topological phase behaviour is induced in the adjacent semiconductor as well as the superconductor. It is in this region of the semiconductor where the MZMs are formed.

Another condition for inducing the topological phase where MZMs can form is the application of a magnetic field in order to lift the spin degeneracy in the semiconductor. Degeneracy in the context of a quantum system refers to the case where different quantum states have the same energy level. Lifting the degeneracy means causing such states to adopt different energy levels. Spin degeneracy refers to the case where different spin states have the same energy level. Spin degeneracy can be lifted by means of a magnetic field, causing an energy level spilt between the differently spin-polarized electrons. This is known as the Zeeman effect. The g-factor refers to the coefficient between the applied magnetic field and the spin splitting. Typically, the magnetic field is applied by an external electromagnet.

The fabrication of heterostructures comprising an aluminium layer arranged on an InAs semiconductor nanowire has been reported [<NPL>)]. Also of interest are devices based on InSb nanowires. InSb has high electron mobility, strong spin-orbit coupling, and a large Landé g-factor, which are considered to be useful properties for allowing MZMs to be induced [<NPL>)].

When fabricating a heterostructure, a metal layer may be grown over the entire surface of the chip. In order to form a usable device, areas of semiconductor which are not covered by metal may be needed, for example to create junctions. There is therefore a need for a method for selectively patterning the metal.

The use of shadow masks to control deposition of the metal layer has been described in e.g. <CIT>; <CIT> and <CIT>. The ability to remove metal selectively would be useful in combination with these techniques, for example to allow different devices fabricated on the same chip to be electrically separated to avoid short circuits.

<NPL>) discloses the selective-area epitaxy of Al to InSb nanowires.

<NPL>) discloses the bottom-up synthesis of quantum devices including nanowire networks.

<NPL> [cond-mat. mes-hall] discloses the shadow-wall lithography of ballistic semiconductor-superconductor hybrid devices.

<CIT> discloses a method of fabricating a device, the method comprising: forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited.

<CIT>, which falls under A. <NUM>(<NUM>) EPC, discloses a method of selectively etching a metal component of a workpiece further comprising a ferromagnetic insulator component. The method comprises contacting the metal component with an etchant solution. The etchant solution comprises a basic etchant and a solvent.

The present invention provides a method for selectively etching a metal component of a workpiece, according to claim <NUM>. The method comprises: forming a hard mask over the metal component; and etching the metal component using an etchant solution, whereby the hard mask controls the etching; wherein the etchant solution is a basic etchant solution; and wherein the workpiece includes a semiconductor component below the metal component comprising a material of.

where x is in the range <NUM> to <NUM>. It has been found that by using a basic etchant in combination with a hard mask, high resolution etching of the metal may be made possible and good selectivity may be achieved.

Certain more specific aspects of the invention are set out in the dependent claims.

It should be noted that <FIG> are schematic and are not to scale.

As used herein, the verb 'to comprise' is used as shorthand for 'to include or to consist of'. In other words, although the verb 'to comprise' is intended to be an open term, the replacement of this term with the closed term 'to consist of' is explicitly contemplated, particularly where used in connection with chemical compositions.

Directional terms such as "top", "bottom", "left", "right", "above", "below", "horizontal" and "vertical" are used herein for convenience of description and relate to the orientation shown in <FIG>. For the avoidance of any doubt, this terminology is not intended to limit orientation in an external frame of reference.

A "nanowire" is an elongate member having a nano-scale width, and a length-to-width ratio of at least <NUM>, or at least <NUM>, or at least <NUM>. A typical example of a nanowire has a width in the range <NUM> to <NUM>, optionally <NUM> to <NUM> or <NUM> to <NUM>. Lengths are typically of the order of micrometres, e.g. at least <NUM>, or at least <NUM>.

The term "workpiece" may refer in particular to a partially fabricated device.

"Creep", which may also be referred to as "over-etching" or "mask underrun", is when material covered by the outer edges of a mask is removed by the etchant. The creep distance is the distance from the edge of the mask to the edge of the material after the etch.

"SEM" stands for scanning electron microscopy. "TEM" stands for transmission electron microscopy. "SAG" stands for selective area growth. "VLS" stands for "vapour-liquid-solid", and may, depending on the context, refer to the vapour-liquid-solid process or to a nanowire grown by that process. "TMAH" is tetramethyl ammonium hydroxide. "PMMA" is poly(methylmethacrylate). "IPA" is isopropyl alcohol, i.e. propan-<NUM>-ol. MIBK is methyl isobutyl ketone.

The inventors have found that the etching of metals, such as aluminium, in the presence of InSb and similar semiconductor materials is particularly challenging. Good selectivity is desired, i.e., the ability to remove the metal without damaging the semiconductor excessively. High resolution, i.e. a small creep distance underneath the mask used to control the etching, is also desired. As described in the Comparative Examples, various existing etching recipes were trialed and found to be unsatisfactory, in that they had inadequate resolution and, in some instances, destroyed the semiconductor nanowires.

It has been found that by using a hard mask (for example, sputtered SiNx) in combination with a basic etchant (for example, an aqueous solution of tetramethyl ammonium hydroxide) metals can be etched in the presence of InSb and the like with good resolution and without destroying the semiconductor.

An example method of fabricating a device will now be explained with reference to <FIG> and <FIG>. <FIG> is a flowchart outlining the method, and <FIG> are schematic cross sections of work pieces obtained at various stages of the method.

The present method may be useful for the fabrication of devices comprising semiconductor-superconductor heterostructures, for example, qubit devices. The method may also be applied to other types of devices comprising a combination of semiconductor and metal components.

At block <NUM>, a semiconductor component is fabricated. The semiconductor component comprises a material of Formula <NUM>:.

where x is in the range <NUM> to <NUM>. An example of a workpiece obtained at this stage is illustrated in <FIG>.

The present method is particularly applicable to indium antimonide. It has been found that indium antimonide is especially susceptible to damage by acidic etchants. Materials according to Formula <NUM>, where x is less than or equal to <NUM>, optionally less than or equal to <NUM>, optionally less than or equal to <NUM>, further optionally less than or equal to <NUM> may be expected to behave similarly to indium antimonide. Materials of Formula <NUM> where x is less than or equal to <NUM> are expected to behave very similarly to indium antimonide.

The semiconductor component may be fabricated on substrate. The substrate may be any structure on which the device is to be constructed. The substrate typically comprises a wafer, i.e. a piece of single crystalline material. One example wafer material is indium phosphide. Other examples of wafer materials include gallium arsenide, indium antimonide, indium arsenide, and silicon. The substrate may be a more elaborate workpiece, further comprising additional structures arranged on or over the wafer. The substrate may include layers of two or more materials.

The substrate may have a planar surface, and the semiconductor component may be grown epitaxially on the planar surface. Alternatively, the surface of the substrate may include a channel or trench, and the semiconductor component may be grown in the channel or trench. An example is illustrated in <FIG>, which shows a wafer <NUM> and a semiconductor component <NUM> arranged in a channel in the surface of the wafer <NUM>.

Fabricating the semiconductor component in a channel may allow a workpiece having a substantially planar surface to be obtained. This may make the use of lift-off processes at later stages easier.

The semiconductor component may comprise a nanowire. In particular, the semiconductor component may take the form of a network of nanowires. A network of nanowires comprises two or more interconnected nanowires. An SEM image of an example network of nanowires is shown in <FIG>.

In implementations where the semiconductor component comprises a network of nanowires, the nanowires of the network may be grown simultaneously in a single step. Alternatively, the network may be assembled by transferring nanowires from a growth substrate and then subsequently connecting the nanowires together.

The process used to fabricate the semiconductor component is not particularly limited.

One example process for fabricating semiconductor components is selective area growth, "SAG". SAG comprises forming a mask over the substrate, then growing the semiconductor using e.g. molecular beam epitaxy. The mask controls the position at which the semiconductor grows. SAG may be particularly useful for constructing networks of nanowires, since the nanowires and junctions between the nanowires can be conveniently formed at the same time by configuring the openings in the mask appropriately.

Another example process for fabricating semiconductor components is the vapour-liquid-solid, VLS, process. VLS forms vertically orientated nanowires on a growth substrate. By vertically orientated is meant the length direction of the nanowires is perpendicular to the surface of the growth substrate. After growing the nanowires by VLS, the nanowires may be cleaved from the substrate and then positioned that substrate, or transferred to another substrate as desired. Alternatively, the VLS nanowires may remain on the growth substrate, and may be used as components of a vertically-orientated device, such as described in <CIT> or <CIT>. A network of nanowires may be fabricated by connecting together two or more of VLS grown nanowires.

At block <NUM>, a metal component <NUM> is fabricated over the semiconductor component. This may yield a workpiece as illustrated in <FIG>.

The metal component <NUM> is typically in the form of a layer. The metal component <NUM> may be arranged on, e.g., may cover, the surface of the substrate <NUM> and the semiconductor component <NUM>.

The metal component may have a thickness in the range <NUM> to <NUM>, optionally <NUM> to <NUM>.

The process used to form the metal component <NUM> is not particularly limited. Examples of useful processes include evaporation and molecular beam epitaxy. The metal may be deposited globally, i.e. may cover the surface of the workpiece. Alternatively, the metal may be deposited selectively on selected portions of the surface, for example by using one or more shadow walls to control a directional deposition.

The metal may be any metal which is compatible with the etchant solution discussed below. In other words, the metal is alkali-etchable metal. Etchants for various metals are disclosed in <NPL>.

The metal may be a superconductor material. For example, the metal may be selected from aluminium, lead, vanadium, and tin. In particular, the metal may be aluminium.

At block <NUM>, a hard mask <NUM> is formed over the metal component <NUM>. The hard mask <NUM> covers regions of the metal component <NUM> where the metal will be present in the finished device, while exposing regions of the metal component <NUM> which are to be removed. An example workpiece obtained at this stage is shown in <FIG>.

The hard mask may comprise any hard mask material which will not react with the etchant solution described below, and which will adhere to the metal. Examples of useful hard mask materials include hafnium oxide, silicon oxide and silicon nitride. In particular, the hard mask material may be silicon oxide or silicon nitride.

The hard mask may be patterned using any suitable process, for example by lift-off.

Lift-off comprises applying a layer of resist over the metal component <NUM>, and then patterning the resist by lithography, typically electron beam lithography. A layer of the hard mask material is then deposited, for example by sputtering. Subsequently, the resist is stripped to yield the hard mask.

The layer of hard mask material may have any appropriate thickness, for example a thickness in the range <NUM> to <NUM>, optionally about <NUM>.

The resist may comprise poly(methyl methacrylate), PMMA. PMMA is one illustrative example of an electron beam resist. The resist may have a thickness in the range <NUM> to <NUM>.

An example developer for PMMA comprises a mixture of methyl isobutyl ketone ("MIBK") and isopropyl alcohol ("IPA"). The ratio of MIBK to IPA may be <NUM> : <NUM> by volume. Acetone may be used to strip the resist.

Other resists, developers, and stripping solvents may be used.

At block <NUM>, the metal component <NUM> is etched using an etchant solution. The hard mask <NUM> controls the etch, such that the exposed reasons of the metal component <NUM> are selectively removed.

The etchant solution is a basic etchant solution. It has surprisingly been found that the use of a basic etchant solution may allow metal such as aluminium to be etched in the presence of semiconductor materials of Formula <NUM>, without excess damage to the semiconductor material. Using a basic etchant in combination with a hard mask may further allow for high-resolution etching to be achieved. It has been found that the etchant creeps under the mask only to a small extent, and that the shape of the edge of the metal component corresponds well to the shape of the edge of the mask.

The etchant solution may comprise, as an active component, a strong base. Examples of strong bases include alkali metal hydroxides such as sodium hydroxide and potassium hydroxide; alkaline earth metal hydroxides such as barium hydroxide; and quaternary ammonium hydroxides such as tetramethyl ammonium hydroxide.

In particular, the etchant solution may comprise tetramethyl ammonium hydroxide as an active component. Tetramethyl ammonium hydroxide was investigated in the examples reported below.

The etchant solution is typically an aqueous solution. The solvent may be water, or a cosolvent mixture including water and one or more further solvents, such as a C1 to C5 alkanol. In other implementations, any other suitable polar, protic solvent may be used. Any solvent which allows the active component to behave as a strong base, i.e. to ionise fully, may be used.

The concentration of the basic etchant is not particularly limited and may be selected as appropriate. For example, the concentration may be in the range <NUM> to <NUM>.

The reaction time for the etch may be selected as appropriate depending, for example, the concentration of the etchant, the thickness of the metal component to be etched. Typical reaction times are in the range <NUM> seconds to <NUM> minutes. In implementations where the metal is aluminium, the aluminium may remain in contact with the etchant until the silvery colour of the aluminium visibly fades plus about <NUM> seconds, before terminating the etch.

The etching may be performed at a temperature of up to <NUM>, optionally <NUM> ± <NUM>. By performing the etch at or below room temperature, diffusion of the metal into the semiconductor material and/or damage to the semiconductor by the etchant may be reduced.

The etchant solution is typically agitated during the etch. The agitation may comprise manual agitation or the use of a magnetic stirrer or the like.

The etching may be terminated by rinsing. Rinsing removes residual etchant from the surface of the chip, thereby improving resolution since any residual etchant may continue to etch the metal film and exacerbate creeping under the mask. Examples of solvents useful for rinsing are water and isopropanol. Rapid rinsing may allow for improved resolution, for example, the workpiece or chip may be rinsed in a first rinsing bath for about <NUM> seconds. Multiple sequential rinsing steps may be performed. For example, the workpiece may be rinsed in three sequential rinsing baths. The solvent in each rinsing bath may be independently selected.

After the etching, further operations may be performed as necessary depending on the nature of the desired device. For example, electrical contacts and/or a protective layer of a dielectric may be added.

A workpiece of the type shown in <FIG> was fabricated on an indium phosphide substrate. The semiconductor material was InSb, and the metal was aluminium.

A poly(methylmethacrylate), PMMA, mask was formed over the aluminium. PMMA is an example of a soft polymer mask. After defining an opening in the mask, the aluminium was etched using Transene-D. Transene-D is a commercially available acidic etchant which comprises an aqueous solution of phosphoric acid, sodium m-nitrobenzene sulfonate and acetic acid.

The etch was performed at a temperature of <NUM>. The reaction time was <NUM> seconds.

An SEM micrograph of the product is shown in <FIG>. The SEM image shows that the InSb nanowires were etched away, leaving voids. Further, the edges of the etched region have badly defined, rough edges indicative of uncontrolled creeping of the etchant under the mask.

Transene-D has been reported to give good yields and resolution in indium arsenide / aluminium systems. The present results demonstrate that indium antimonide is much more susceptible to damage by acids than indium arsenide.

Additional experiments were performed using a buffered solution of hydrogen fluoride as the etchant. Buffered hydrogen fluoride is another commercially available acidic etchant for aluminium. This etchant gave very poor resolution, with a high rate of creep under the mask.

A workpiece was prepared as described above with reference to Comparative Example <NUM>. A PMMA mask was formed over the workpiece. The workpiece was then edged using MF321. MF321 is a commercially available basic etchant solution, which contains <NUM> % tetramethyl ammonium hydroxide by weight as an active ingredient. The reaction time for the etch was <NUM> seconds. An SEM micrograph of the resulting product is shown in <FIG>.

As is illustrated in <FIG>, unlike the acidic etchant of Comparative Example <NUM>, MF321 did not remove the InSb nanowire. However, uncontrolled creeping of the etchant under the mask was observed. The extent of the creep was of the order of a few microns. The edges of the aluminium were uneven and poorly defined.

An aluminium layer was fabricated on a substrate, and a PMMA mask was applied. The aluminium layer was then etched using aqueous solution comprising <NUM> % tetramethyl ammonium hydroxide by weight. The reaction time for the etch was <NUM> seconds.

Micrographs of the product at different levels of magnification are shown in <FIG>. The location of one of the etchant windows defined by the mask is shown by dashed lines.

Dark regions of the micrographs correspond to regions where aluminium was removed. Bright regions correspond to regions covered by aluminium. As may be seen, similar to the method of Comparative Example <NUM>, a creeping distance of the order of several microns was observed. The edges of the aluminium again had a poorly defined, irregular shape. These findings demonstrate that adjusting the concentration of the etchant and the reaction time did not solve the problem of creep.

A workpiece of the type shown in <FIG> was fabricated. The semiconductor component comprised InSb, and the metal component comprised aluminium.

A PMMA electron beam resist having a thickness in the range <NUM> to <NUM> was applied to the workpiece, exposed, and developed using a mixture of MIBK and IPA at a ratio of <NUM> :<NUM> by volume to form a patterned layer of resist. A layer of silicon nitride was then deposited on the workpiece by sputtering, before being formed into a hard mask by lift-off.

The aluminium was etched using an aqueous solution of tetramethyl ammonium hydroxide, TMAH. The TMAH was present at a concentration of <NUM>% by weight of the solution. The reaction time was <NUM> minutes. The product was then inspected using SEM and TEM.

<FIG> is an annotated SEM micrograph of the product. The Fig. shows a network of InSb nanowires <NUM>, confirming that the InSb was not removed by the etchant. The dark region <NUM> corresponds to the silicon nitride hard mask. As is typical for sputtered thin films, the hard mask has a rolled edge <NUM>.

The creeping distance, corresponding to the distance from the visible edge of the aluminium under the mask to the edge of the mask, is shown by the white arrow. The creeping distance was only about <NUM>, demonstrating an improvement in resolution compared to Comparative Examples <NUM> and <NUM>. Further, the shape of the edge of the aluminium conformed well to the shape of the edge of the mask, showing that the etch was well-controlled.

<FIG> shows a transmission electron microscopy micrograph of the product, taken through a cross-section of one of the nanowires. Slight degradation to the exposed surface of the InSb nanowire, in the region highlighted by ellipse <NUM>, was observed. The damage did not extend beyond a depth of about <NUM>. This is an acceptable degree of damage, and is comparable to the level of damage caused when etching aluminium on InAs using Transene-D.

Further experiments were performed using MF321 as the etchant solution, a more dilute solution having a TMAH concentration of about <NUM> % by weight. Similar results were obtained.

Other variants or use cases of the disclosed techniques may become apparent to the person skilled in the art once given the disclosure herein.

Claim 1:
A method for selectively etching a metal component (<NUM>) of a workpiece, which method comprises:
forming (<NUM>) a hard mask (<NUM>) over the metal component (<NUM>); and
etching (<NUM>) the metal component (<NUM>) using an etchant solution, whereby the hard mask (<NUM>) controls the etching;
wherein the etchant solution is a basic etchant solution; and
wherein the workpiece includes a semiconductor component (<NUM>) below the metal component (<NUM>) comprising a material of

        Formula <NUM>:     InAsxSb<NUM>-x

where x is in the range <NUM> to <NUM>.