Patent Description:
As memory devices are shrinking to smaller die size to reduce manufacturing cost and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. A three-dimensional (3D) memory architecture can address the density and performance limitation in planar memory cells.

In a 3D NAND memory, a staircase structure is typically used to provide electrical contacts between word lines and control gates of the vertically stacked memory cells. However, as storage capacity continues to increase in a 3D NAND memory, the number of vertically stacked memory cells has been increased greatly. Accordingly, the lateral dimensions of the staircase structure are also increased, which reduces the effective storage capacity per area. Furthermore, larger staircase structure introduces higher mechanical stress between the memory array region and the staircase region, which may cause reliability problems in the 3D NAND memory. Therefore, a need exists for contact structures of a 3D memory that can provide electrical connections between word lines and control gates of the vertically stacked memory cells without using a staircase structure. <CIT> discloses a multiheight electrically conductive via contacts for a multilevel interconnect structure.

Embodiments of a three-dimensional (3D) memory device are described in the present disclosure.

One aspect of the present disclosure provides a three-dimensional (3D) memory structure according to claim <NUM>.

In some embodiments, the 3D memory structure of claim <NUM> also includes a common source contact vertically penetrating the film stack, wherein the common source contact is electrically connected with a substrate. In some embodiments, the common source contact includes an isolation liner configured to electrically isolate the common source contact from the conductive layers of the film stack.

In some embodiments, the 3D memory structure further includes a plurality of dummy memory strings vertically penetrating through the film stack adjacent to the plurality of contact structures, wherein each of the plurality of dummy memory strings includes a core filling film.

In some embodiments, the plurality of contact structures are coplanar with the film stack.

In some embodiments, the plurality of contact structures are randomly distributed in a memory array.

The embodiments of <FIG> and <FIG> are not forming part of the claimed invention, but are useful for its understanding. The embodiments of <FIG> and <FIG> are in accordance with the claimed invention.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology can be understood at least in part from usage in context. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as "a," "an," or "the," again, can be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of "on," "above," and "over" in the present disclosure should be interpreted in the broadest manner such that "on" not only means "directly on" something, but also includes the meaning of "on" something with an intermediate feature or a layer therebetween. Moreover, "above" or "over" not only means "above" or "over" something, but can also include the meaning it is "above" or "over" something with no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process step in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated <NUM> degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly.

The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where a semiconductor device is formed, and therefore the semiconductor device is formed at a top side of the substrate unless stated otherwise. The bottom surface is opposite to the top surface and therefore a bottom side of the substrate is opposite to the top side of the substrate.

A layer has a top side and a bottom side where the bottom side of the layer is relatively close to the substrate and the top side is relatively away from the substrate. A layer can extend over the entirety of an underlying or overlying structure, or can have an extent less than the extent of an underlying or overlying structure. For example, a layer can be located between any set of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. For example, an interconnect layer can include one or more conductive and contact layers (in which contacts, interconnect lines, and/or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

In the present disclosure, for ease of description, "tier" is used to refer to elements of substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer can be referred to as "a tier," a word line and the underlying insulating layer can together be referred to as "a tier," word lines of substantially the same height can be referred to as "a tier of word lines" or similar, and so on.

As used herein, the term "nominal/nominally" refers to a desired, or target, value of a characteristic or parameter for a component or a process step, set during the design phase of a product or a process, together with a range of values above and/or below the desired value.

In the present disclosure, the term "horizontal/horizontally/lateral/laterally" means nominally parallel to a lateral surface of a substrate, and the term "vertical" or "vertically" means nominally perpendicular to the lateral surface of a substrate.

As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate.

<FIG> illustrates a top-down view of an exemplary three-dimensional (3D) memory device <NUM>, according to some embodiments of the present disclosure. This embodiment is not forming part of the claimed invention. The 3D memory device <NUM> can be a memory chip (package), a memory die or any portion of a memory die, and can include one or more memory planes <NUM>, each of which can include a plurality of memory blocks <NUM>. Identical and concurrent operations can take place at each memory plane <NUM>. The memory block <NUM>, which can be megabytes (MB) in size, is the smallest size to carry out erase operations. Shown in <FIG>, the exemplary 3D memory device <NUM> includes four memory planes <NUM> and each memory plane <NUM> includes six memory blocks <NUM>. Each memory block <NUM> can include a plurality of memory cells, where each memory cell can be addressed through interconnections such as bit lines and word lines. The bit lines and word lines can be laid out perpendicularly (e.g., in rows and columns, respectively), forming an array of metal lines. The direction of bit lines and word lines are labeled as "BL" and "WL" in <FIG>. In this disclosure, memory block <NUM> is also referred to as a "memory array" or "array. " The memory array is the core area in a memory device, performing storage functions.

The 3D memory device <NUM> also includes a periphery region <NUM>, an area surrounding memory planes <NUM>. The periphery region <NUM> contains many digital, analog, and/or mixed-signal circuits to support functions of the memory array, for example, page buffers, row and column decoders and sense amplifiers. Peripheral circuits use active and/or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to a person of ordinary skill in the art.

It is noted that, the arrangement of the memory planes <NUM> in the 3D memory device <NUM> and the arrangement of the memory blocks <NUM> in each memory plane <NUM> illustrated in <FIG> are only used as an example, which does not limit the scope of the present disclosure.

Referring to <FIG>, an enlarged top-down view of a region <NUM> in <FIG> is illustrated, according to some embodiments of the present disclosure. This embodiment is not forming part of the claimed invention. The region <NUM> of the 3D memory device <NUM> can include a staircase region <NUM> and a channel structure region <NUM>. The channel structure region <NUM> can include an array of memory strings <NUM>, each including a plurality of stacked memory cells. The staircase region <NUM> can include a staircase structure and an array of contact structures <NUM> formed on the staircase structure. In some embodiments, a plurality of slit structures <NUM>, extending in the direction of the word lines (WL) across the channel structure region <NUM> and the staircase region <NUM>, can divide a memory block into multiple memory fingers <NUM>, where the direction of the WL (i.e., the WL direction) is similar to the one shown in <FIG>. At least some slit structures <NUM> can function as the common source contact for an array of memory strings <NUM> in channel structure regions <NUM>. A top select gate cut <NUM> can be disposed, for example, in the middle of each memory finger <NUM> to divide a top select gate (TSG) of the memory finger <NUM> into two portions, and thereby can divide a memory finger into two memory slices <NUM>, where memory cells in a memory slice <NUM> that share the same word line form a programmable (read/write) memory page. While erase operation of a 3D NAND memory can be carried out at memory block level, read and write operations can be carried out at memory page level. A memory page can be kilobytes (KB) in size. In some embodiments, region <NUM> also includes dummy memory strings <NUM> for process variation control during fabrication and/or for additional mechanical support.

<FIG> illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure <NUM>, according to some embodiments of the present disclosure. This embodiment is not forming part of the claimed invention. The memory array structure <NUM> includes a substrate <NUM>, an insulating film <NUM> over the substrate <NUM>, a tier of lower select gates (LSGs) <NUM> over the insulating film <NUM>, and a plurality of tiers of control gates <NUM>, also referred to as "word lines (WLs)," stacking on top of the LSGs <NUM> to form a film stack <NUM> of alternating conductive and dielectric layers. The dielectric layers adjacent to the tiers of control gates are not shown in <FIG> for clarity.

The control gates of each tier are separated by slit structures <NUM>-<NUM> and <NUM>-<NUM> through the film stack <NUM>. The memory array structure <NUM> also includes a tier of top select gates (TSGs) <NUM> over the stack of control gates <NUM>. The stack of TSG <NUM>, control gates <NUM> and LSG <NUM> is also referred to as "gate electrodes. " The memory array structure <NUM> further includes memory strings <NUM> and doped source line regions <NUM> in portions of substrate <NUM> between adjacent LSGs <NUM>. Each memory string <NUM> includes a channel hole <NUM> extending through the insulating film <NUM> and the film stack <NUM> of alternating conductive and dielectric layers. Memory strings <NUM> also includes a memory film <NUM> on a sidewall of the channel hole <NUM>, a channel layer <NUM> over the memory film <NUM>, and a core filling film <NUM> surrounded by the channel layer <NUM>. A memory cell <NUM> can be formed at the intersection of the control gate <NUM> and the memory string <NUM>. The memory array structure <NUM> further includes a plurality of bit lines (BLs) <NUM> connected with the memory strings <NUM> over the TSGs <NUM>. The memory array structure <NUM> also includes a plurality of metal interconnect lines <NUM> connected with the gate electrodes through a plurality of contact structures <NUM>. The edge of the film stack <NUM> is configured in a shape of staircase to allow an electrical connection to each tier of the gate electrodes.

In <FIG>, for illustrative purposes, three tiers of control gates <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> are shown together with one tier of TSG <NUM> and one tier of LSG <NUM>. In this example, each memory string <NUM> can include three memory cells <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, corresponding to the control gates <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, respectively. In some embodiments, the number of control gates and the number of memory cells can be more than three to increase storage capacity. The memory array structure <NUM> can also include other structures, for example, TSG cut, common source contact and dummy memory string. These structures are not shown in <FIG> for simplicity.

To pursue higher storage capacity in a 3D memory, the number of vertically stacked memory cells has been increased greatly. As a result, the number of control gates or word lines <NUM> has been increased greatly. To form electrical contact (e.g., contact structure <NUM>) for each word line <NUM>, the staircase region <NUM> has been extended laterally from either side of the channel structure region <NUM>. The increased dimension of staircase region <NUM> reduces the effective storage capacity per unit area and thus increases cost per bit of the 3D memory. Furthermore, large staircase region <NUM> may introduce mechanical stress in the channel structure region <NUM>, which may cause reliability problems in the memory cells. Therefore, a need exists to form contact structures for a 3D memory without relying on a staircase structure.

<FIG> illustrates an exemplary fabrication process <NUM> for forming a 3D memory device, accordance to some embodiments of the present disclosure. This fabrication process is not forming part of the claimed invention. Only the resulting memory structure of <FIG> is in accordance with the claimed invention. <FIG>, <FIG>, <FIG> illustrate cross-sectional views of the 3D memory device at various process steps according to the fabrication process <NUM>. It should be understood that the process steps shown in fabrication process <NUM> are not exhaustive and that other process steps can be performed as well before, after, or between any of the illustrated process steps. In some embodiments, some process steps of exemplary fabrication process <NUM> can be omitted or other process steps can be included, which are not described here for simplicity. In some embodiments, process steps of fabrication process <NUM> can be performed in a different order and/or vary.

As shown in <FIG>, fabrication process <NUM> starts at process step S410, where an alternating dielectric stack can be disposed on a substrate. An example of a 3D memory device at the process step S410 is shown as a 3D memory structure <NUM> in <FIG>.

In some embodiments, the substrate of the 3D memory structure <NUM> can be similar to the substrate <NUM> in <FIG>. The substrate <NUM> can provide a platform for forming subsequent structures. In some embodiments, the substrate <NUM> can be any suitable semiconductor substrate having any suitable semiconductor materials, such as monocrystalline, polycrystalline or single crystalline semiconductors. For example, the substrate <NUM> can include silicon, silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compound, or any combinations thereof. In some embodiments, the substrate <NUM> can include a layer of semiconductor material formed on a handle wafer, for example, glass, plastic, or another semiconductor substrate.

A front surface 330f of the substrate <NUM> is also referred to as a "main surface" or a "top surface" of the substrate herein. Layers of materials can be disposed on the front surface 330f of the substrate <NUM>. A "topmost" or "upper" layer is a layer farthest or farther away from the front surface 330f of the substrate. A "bottommost" or "lower" layer is a layer closest or closer to the front surface 330f of the substrate.

In some embodiments, the alternating dielectric stack <NUM> includes a plurality of dielectric layer pairs <NUM> alternatingly stacked on top of each other, where each dielectric layer pair <NUM> includes a first dielectric layer <NUM> and a second dielectric layer <NUM> (also referred to as "sacrificial layer") that is different from the first dielectric layer <NUM>. The alternating dielectric stack <NUM> extends in a lateral direction that is parallel to the front surface 330f of the substrate <NUM>.

In the alternating dielectric stack <NUM>, first dielectric layers <NUM> and second dielectric layers <NUM> alternate in a vertical direction, perpendicular to the substrate <NUM>. In the other words, each second dielectric layer <NUM> can be sandwiched between two first dielectric layers <NUM>, and each first dielectric layer <NUM> can be sandwiched between two second dielectric layers <NUM> (except the bottommost and the topmost layer).

The formation of the alternating dielectric stack <NUM> can include disposing the first dielectric layers <NUM> to each have the same thickness or to have different thicknesses. Example thicknesses of the first dielectric layers <NUM> can range from <NUM> to <NUM>, preferably about <NUM>. Similarly, the second dielectric layer <NUM> can each have the same thickness or have different thicknesses. Example thicknesses of the second dielectric layer <NUM> can range from <NUM> to <NUM>, preferably about <NUM>. It should be understood that the number of dielectric layer pairs <NUM> in <FIG> is for illustrative purposes only and that any suitable number of layers may be included in the alternating dielectric stack <NUM>.

In some embodiments, the first dielectric layer <NUM> includes any suitable insulating materials, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS or silicon oxide with F-, C-, N-, and/or H- incorporation. The first dielectric layer <NUM> can also include high-k dielectric materials, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide films. In some embodiments, the first dielectric layer <NUM> can be any combination of the above materials.

The formation of the first dielectric layer <NUM> on the substrate <NUM> can include any suitable deposition methods such as, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density-plasma CVD (HDP-CVD), thermal oxidation, nitridation, any other suitable deposition method, and/or combinations thereof.

In some embodiments, the second dielectric layer <NUM> includes any suitable material that is different from the first dielectric layer <NUM> and can be removed selectively with respect to the first dielectric layer <NUM>. For example, the second dielectric layer <NUM> can include silicon oxide, silicon oxynitride, silicon nitride, TEOS, poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon, and any combinations thereof. In some embodiments, the second dielectric layer <NUM> also includes amorphous semiconductor materials, such as amorphous silicon or amorphous germanium. The second dielectric layer <NUM> can be disposed using a similar technique as the first dielectric layer <NUM>, such as CVD, PVD, ALD, thermal oxidation or nitridation, or any combination thereof.

In some embodiments, the first dielectric layer <NUM> can be silicon oxide and the second dielectric layer <NUM> can be silicon nitride.

In some embodiments, the alternating dielectric stack <NUM> can include layers in addition to the first dielectric layer <NUM> and the second dielectric layer <NUM>, and can be made of different materials and/or with different thicknesses.

In addition to the alternating dielectric stack <NUM>, in some embodiments, peripheral devices (not shown) can be formed in the periphery region <NUM> (see <FIG>) on the front surface 330f of the substrate <NUM>. In some embodiments, active device areas (not shown) can also be formed in the memory blocks <NUM> (see <FIG>) on the front surface 330f of the substrate <NUM>. In some embodiments, the substrate <NUM> can further include an insulating film <NUM> on the front surface 330f (not shown in <FIG>). The insulating film <NUM> can be made of the same or different material from the alternating dielectric stack <NUM>.

The peripheral devices can include any suitable semiconductor devices, for example, metal oxide semiconductor field effect transistors (MOSFETs), diodes, resistors, capacitors, etc. The peripheral devices can be used in the design of digital, analog and/or mixed signal circuits supporting the storage function of the memory core, for example, row and column decoders, drivers, page buffers, sense amplifiers, timing and controls.

The active device areas in the memory blocks are surrounded by isolation structures, such as shallow trench isolation. Doped regions, such as p-type doped and/or n-type doped wells, can be formed in the active device area according to the functionality of the array devices in the memory blocks.

Referring to <FIG>, at process step S415, a hard mask can be disposed on the alternating dielectric stack, according to some embodiments of the present disclosure. An example of a 3D memory device at process step S415 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes a hard mask <NUM> disposed on the alternating dielectric stack <NUM>. The hard mask <NUM> is used to provide protection to the underlying structures and materials during subsequent etching process. In some embodiments, the hard mask <NUM> includes any suitable material that can withstand the etching process, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, amorphous silicon, polycrystalline silicon, high-k dielectric materials, or any combination thereof. In some embodiments, the hard mask <NUM> can include amorphous carbon. In some embodiments, amorphous carbon can be doped with other etch-resistant elements, such as boron, to improve the etch-resistance of the amorphous carbon. In some embodiments, a thin metal or metal oxide layer, such as zirconium oxide (ZrO<NUM>), yttrium oxide (Y<NUM>O<NUM>), and aluminum oxide (Al<NUM>O<NUM>), can be disposed on top of the amorphous carbon layer. The hard mask <NUM> can be disposed by LPCVD, RTCVD, PECVD, ALD, PVD, evaporation, sputtering, or any combination thereof.

<FIG> illustrates a 3D memory structure <NUM>, according to some embodiments of the present disclosure. The 3D memory structure <NUM> includes a contact defining mask <NUM> disposed on the hard mask <NUM> over the alternating dielectric stack <NUM>. In some embodiments, the contact defining mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. The contact defining mask <NUM> defines the location of contact structures for control gates and select gates of a 3D memory device that will be formed in the subsequent processes. In some embodiments, the contact structures can be similar to the contact structures <NUM> for the control gate <NUM>, top select gate (TSG) <NUM> and lower select gate (LSG) <NUM> shown in <FIG>. The contact structures <NUM> can be placed in a region (e.g., the staircase region <NUM>) adjacent to the channel structure region <NUM> in <FIG>. In some embodiments, the contact structures <NUM> can also be placed inside the channel structure region <NUM>, which will be discussed in detail below.

Referring to <FIG>, at process step S420, a plurality of hard mask openings can be formed by patterning the hard mask, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S420 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes a plurality of hard mask openings <NUM>, formed by patterning the hard mask <NUM> using the contact defining mask <NUM> in <FIG>. The hard mask openings expose a top surface <NUM>-t of the first dielectric layer pair (i.e., the topmost dielectric layer pair in the alternating dielectric stack <NUM>).

In some embodiments, the hard mask openings <NUM> can be patterned by using a suitable etching process such as wet etching, dry etching, and/or a combination thereof. In some embodiments, the hard mask <NUM> can be etched using an anisotropic etching such as a reactive ion etching (RIE) or other dry etching processes. In some embodiments, the hard mask <NUM> is silicon oxide. In this example, the etching of silicon oxide can include RIE using fluorine-based gases such as carbon-fluorine (CF<NUM>), hexafluoroethane (C<NUM>F<NUM>), CHF<NUM>, or C<NUM>F<NUM> and/or any other suitable gases. In some embodiments, the silicon oxide layer can be etched by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the hard mask <NUM> is silicon nitride. In this example, the etching of silicon nitride can include RIE using O<NUM>, N<NUM>, CF<NUM>, NF<NUM>, Cl<NUM>, HBr, BCl<NUM>, and/or combinations thereof. The methods and etchants to pattern the hard mask <NUM> should not be limited by the embodiments of the present disclosure.

In some embodiments, after forming the hard mask openings <NUM>, the contact defining mask <NUM> in <FIG> can be removed by using techniques such as dry etching with O<NUM> or CF<NUM> plasma, or wet etching with resist/polymer stripper, for example solvent based chemicals.

Referring to <FIG>, at process step S425, a first contact mask can be formed over the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S425 is illustrated as a 3D memory structure <NUM> in <FIG>.

In some embodiments, the 3D memory structure <NUM> includes a first contact mask <NUM> disposed on the 3D memory structure <NUM>, over at least a portion of the alternating dielectric stack. In some embodiments, the first contact mask <NUM> covers half of the hard mask openings <NUM> and exposes the other half of the hard mask openings <NUM>. In some embodiments, the first contact mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography.

Referring to <FIG>, at process step S430, a first subset of contact openings can be formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S430 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes a first subset of contact openings <NUM>.

In some embodiments, the first subset of contact openings <NUM> can be formed by etching one dielectric layer pair <NUM> using the first contact mask <NUM> shown in <FIG>. The first subset of contact openings <NUM> expose a top surface <NUM>-t of the second dielectric layer pair, where the second dielectric layer pair is located below the first or topmost dielectric layer pair in the alternating dielectric stack <NUM>. In this disclosure, the dielectric layer pairs are counted sequentially from top to bottom in the alternating dielectric stack <NUM>. In some embodiments, one or more dielectric layer pairs <NUM> can be etched with the first contact mask <NUM>. The etching process for the first dielectric layer <NUM> can have a high selectivity over the second dielectric layer <NUM>, and/or vice versa. Accordingly, an underlying dielectric layer pair <NUM> can function as an etch-stop layer. As a result, multiple dielectric layer pairs <NUM> can be etched controllably.

In some embodiments, dielectric layer pair <NUM> can be etched by using an anisotropic etching such as a reactive ion etching (RIE) or other dry etching processes. In some embodiments, the first dielectric layer <NUM> is silicon oxide. In this example, the etching of silicon oxide can include RIE using fluorine-based gases such as carbon-fluorine (CF<NUM>), hexafluoroethane (C<NUM>F<NUM>), CHF<NUM>, or C<NUM>F<NUM> and/or any other suitable gases. In some embodiments, the silicon oxide layer can be etched by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the second dielectric layer <NUM> is silicon nitride. In this example, the etching of silicon nitride can include RIE using O<NUM>, N<NUM>, CF<NUM>, NF<NUM>, Cl<NUM>, HBr, BCl<NUM>, and/or combinations thereof. The methods and etchants used for etching the dielectric layer pair <NUM> should not be limited by the embodiments of the present disclosure.

In some embodiments, after forming the first subset of contact openings <NUM>, the first contact mask <NUM> can be removed by using techniques such as dry etching with O<NUM> or CF<NUM> plasma, or wet etching with resist/polymer stripper, for example solvent based chemicals.

In some embodiments, after the process step S430, half of the hard mask openings <NUM> can be converted to the first subset of contact openings <NUM>, with the other half remains as hard mask openings <NUM>. Accordingly, top surfaces of the first and second dielectric layer pairs <NUM>-t and <NUM>-t can be exposed inside the hard mask openings <NUM> and the first subset of contact openings <NUM>, respectively.

In some embodiments, the alternating dielectric stack <NUM> includes L number of dielectric layer pairs <NUM>. In some embodiments, the 3D memory structure <NUM> (in <FIG>) includes N number of hard mask openings <NUM>, wherein the number N is larger or equal to the number L, i.e., N ≥ L. In this example, half of the hard mask openings <NUM> can be converted to the first subset of contact openings <NUM>. In the other words, after process step S430, the number of first subset of contact openings <NUM> can be N/<NUM> and the number of remaining hard mask openings <NUM> can also be N/<NUM>. However, the first subset of contact openings <NUM> is not limited as described above and can include any suitable number of the hard mask openings <NUM>.

Referring to <FIG>, at process step S435, a second contact mask can be formed over the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S435 is illustrated as a 3D memory structure <NUM> in <FIG>.

In some embodiments, the 3D memory structure <NUM> includes a second contact mask <NUM> disposed on the 3D memory structure <NUM>, over at least a portion of the alternating dielectric stack <NUM>. In some embodiments, the second contact mask <NUM> covers half of the remaining hard mask openings <NUM> and exposes the other half of the remaining hard mask openings <NUM>. In some embodiments, the second contact mask <NUM> also covers half of the first subset of contact openings <NUM> and exposes the other half of the first subset of contact openings <NUM>. In some embodiments, the second contact mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography.

Referring to <FIG>, at process step S440, a second subset of contact openings and a third subset of contact openings can be formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S440 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes a second subset of contact openings <NUM> and a third subset of contact openings <NUM>.

In some embodiments, the second and third subsets of contact openings <NUM> can be formed by etching two dielectric layer pairs <NUM> using the second contact mask <NUM> shown in <FIG>. In some embodiments, one or more dielectric layer pairs <NUM> can be etched with the second contact mask <NUM>. The etching processes for the first and second dielectric layers <NUM> and <NUM> can be similar to those used for the first subset of contact openings <NUM>, where each dielectric layer pair <NUM> can be etched controllably with an etch-stop on the underlying dielectric layer pair <NUM>.

In some embodiments, the first and second contact masks <NUM> and <NUM> can be designed such that the second subset of contact openings <NUM> include half of the first subset of contact openings <NUM> and the third subset of contact openings <NUM> include half of the remaining hard mask openings <NUM> that are not converted to the first subset of contact openings <NUM> at the process step <NUM>. In the example that the hard mask openings <NUM> are formed by etching through the hard mask <NUM> and the first subset of contact openings <NUM> are formed by etching one dielectric layer pair <NUM>, by etching two dielectric layer pair <NUM> at process step S440, the second subset of contact openings <NUM> can extend through three dielectric layer pairs and expose a top surface <NUM>-t of the fourth dielectric layer pair. In the meantime, the third subset of contact openings <NUM> can extend through two dielectric layer pairs and expose a top surface <NUM>-t of the third dielectric layer pair. Accordingly, after process step S440, half of the first subset of contact openings <NUM> are converted to the second subset of contact openings <NUM> and half of the remaining hard mask openings <NUM> are converted to the third subset of contact openings <NUM>.

As shown in <FIG>, the 3D memory structure <NUM> can also include some of the first subset of contact openings <NUM> extending through one dielectric layer pair <NUM> and exposing the top surface <NUM>-t of the second dielectric layer pair. The 3D memory structure <NUM> can also include some of the hard mask openings <NUM> extending through the hard mask <NUM> and exposing the top surface <NUM>-t of the first dielectric layer pair. As illustrated in <FIG>, these openings are covered by the second contact mask <NUM> at process step S435, and are protected during the etching process of the dielectric layer pairs <NUM> at process step S440. Therefore, depths of the aforementioned openings are not changed at process step S440.

After process step S440, top surfaces of the first, second, third and fourth dielectric layer pairs can be exposed inside in the hard mask openings <NUM>, the first subset of contact openings <NUM>, the third subset of contact openings <NUM> and the second subset of contact openings <NUM>, respectively.

In the example that the 3D memory structure <NUM> includes N/<NUM> number of first subset of contact openings <NUM> and N/<NUM> number of hard mask openings <NUM>, after process step S430, the 3D memory structure <NUM> can include N/<NUM> number of second subset of contact openings <NUM> and N/<NUM> number of third subset of contact openings <NUM>. In the meantime, there can be N/<NUM> number of first subset of contact openings <NUM> and N/<NUM> number of hard mask openings <NUM> remaining in the 3D memory structure <NUM>.

It is noted that arrangement of the first, second and third subsets of contact openings <NUM>, <NUM> and <NUM> and the hard mask openings <NUM> in <FIG> is for illustration purpose only. The 3D memory structure <NUM> can include different arrangements and depths in the first, second and third subsets of contact openings <NUM>, <NUM> and <NUM>, as well as the hard mask openings <NUM>.

Referring to <FIG>, at process step S445, a third contact mask is formed over the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S445 is illustrated as a 3D memory structure <NUM> in <FIG>.

The 3D memory structure <NUM> includes a third contact mask <NUM> disposed on the 3D memory structure <NUM>, over at least a portion of the alternating dielectric stack <NUM>. In some embodiments, the third contact mask <NUM> covers half of the remaining hard mask openings <NUM> and exposes the other half of the remaining hard mask openings <NUM>. In some embodiments, the third contact mask <NUM> also covers half of the remaining first subset of contact openings <NUM> and exposes the other half of the remaining first subset of contact openings <NUM>. In some embodiments, the third contact mask <NUM> also covers half of the second subset of contact openings <NUM> and exposes the other half of the second subset of contact openings <NUM>. In some embodiments, the third contact mask <NUM> also covers half of the third subset of contact openings <NUM> and exposes the other half of the third subset of contact openings <NUM>. In some embodiments, the third contact mask <NUM> can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography.

Referring to <FIG>, at process step S450, a fourth subset, a fifth subset, a sixth subset and a seventh subset of contact openings are formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S450 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes a fourth subset of contact openings <NUM>, a fifth subset of contact openings <NUM>, a sixth subset of contact openings <NUM> and a seventh subset of contact openings <NUM>, formed in the alternating dielectric stack <NUM>, according to some embodiments of the present disclosure.

In some embodiments, the fourth, fifth, sixth and seventh subsets of contact openings <NUM>-<NUM> can be formed by etching four dielectric layer pairs <NUM> using the third contact mask <NUM> shown in <FIG>. In some embodiments, one or more dielectric layer pairs <NUM> can be etched using the third contact mask <NUM>. The etching processes for the first and second dielectric layers <NUM> and <NUM> can be similar to those used for the first, second and third subsets of contact openings <NUM>, <NUM> and <NUM>, where each dielectric layer pair <NUM> can be etched controllably with an etch-stop on the underlying dielectric layer pair <NUM>.

<FIG> illustrates the relationships between contact openings at various process steps, according to some embodiments of the present disclosure. The dielectric layer pair <NUM> (counted from top to bottom) that each contact opening exposes is shown in parenthesis. In some embodiments, the first, second and third contact masks <NUM>, <NUM> and <NUM> can be designed such that a portion of the hard mask openings <NUM> can be converted to the first subset of contact openings <NUM> at process step S430. A portion of the first subset of contact openings <NUM> can be converted to the second subset of contact openings <NUM> at process step S440 and then a portion of the second subset of contact openings <NUM> can be converted to the fourth subset of contact openings <NUM> at process step S450. In the meantime, a portion of the remaining first subset of contact openings <NUM> at process step S440 can be converted to the fifth subset of contact openings <NUM> at process step S450. In this example, a portion of the remaining hard mask openings <NUM> at process step S430 can be converted to the third subset of contact openings <NUM> at process step S440, while a portion of the third subset of contact openings <NUM> can be converted to the seventh subset of contact openings <NUM> at process step S450. A portion of the remaining hard mask openings <NUM> at process step S440 can be converted to the sixth subset of contact openings <NUM> at process step S450. It is noted that the portion of contact openings subjected to the etching of dielectric layer pair <NUM> at each process step can be any suitable number and is not limited to a half or <NUM>% shown in the <FIG> and <FIG>.

As discussed previously, in some embodiments, there are N number of hard mask openings <NUM> after process step S420 and the 3D memory structure <NUM> can have N/<NUM> number of first subset of contact openings <NUM> and N/<NUM> number of hard mask openings <NUM> after process step S420. The 3D memory structure <NUM> can have N/<NUM> number of first subset of contact openings <NUM>, N/<NUM> number of second subset of contact openings <NUM>, N/<NUM> number of third subset of contact openings <NUM>, and N/<NUM> number of hard mask openings <NUM> after process step S440. In some embodiments, the 3D memory structure <NUM> can have N/<NUM> number of first subset of contact openings <NUM>, N/<NUM> number of second subset of contact openings <NUM>, N/<NUM> number of third subset of contact openings <NUM>, N/<NUM> number of fourth subset of contact openings <NUM>, N/<NUM> number of fifth subset of contact openings <NUM>, N/<NUM> number of sixth subset of contact openings <NUM>, N/<NUM> number of seventh subset of contact openings <NUM> and N/<NUM> number of hard mask openings <NUM>.

As previously discussed, in some embodiments, the hard mask openings <NUM> can be formed by etching through the hard mask <NUM> at process step S420, and the first subset of contact openings <NUM> can be formed by etching one dielectric layer pair <NUM> at process step S430. Subsequently, the second and third subsets of contact openings <NUM> and <NUM> can be formed by etching two dielectric layer pairs <NUM> at process step S440. Accordingly, the hard mask opening <NUM> can expose the first dielectric layer pair, i.e., the topmost dielectric layer pair. The first subset of contact openings <NUM>, converted from the hard mask openings <NUM>, can extend through one dielectric pair <NUM> and expose the second dielectric pair, below the first dielectric layer pair. The second and third subsets of contact openings <NUM> and <NUM>, converted from respective first subset of contact openings <NUM> and the hard mask openings <NUM>, can extend through three and two dielectric layer pairs <NUM>, respectively. In the other words, the second and third subsets of contact openings <NUM> and <NUM> can expose the fourth and the third dielectric layer pair, respectively. Referring to <FIG> and <FIG>, in some embodiments, the fourth to seventh subsets of contact openings <NUM>-<NUM> can be formed by etching through four dielectric layer pairs <NUM>. As a result, after process step S450, the fourth subset of contact openings <NUM>, converted from the second subset of contact openings <NUM>, can extend through seven dielectric layer pairs <NUM> and expose a top surface <NUM>-t of the eighth dielectric layer pair. The fifth subset of contact openings <NUM>, converted from the first subset of contact openings <NUM>, can extend through five dielectric layer pairs <NUM> and expose a top surface <NUM>-t of the sixth dielectric layer pair. The sixth subset of contact openings <NUM>, converted from the hard mask openings <NUM>, can extend through four dielectric layer pairs <NUM> and expose a top surface <NUM>-t of the fifth dielectric layer pair. Similarly, the seventh subset of contact openings <NUM>, converted from the third subset of contact openings <NUM>, can extend through six dielectric layer pairs <NUM> and expose a top surface <NUM>-t of the seventh dielectric layer pair.

It is noted that arrangement of the first to seventh subsets of contact openings <NUM>, <NUM>-<NUM>, <NUM>-<NUM> and the hard mask openings <NUM> in <FIG> and <FIG> are for illustration purpose only. The 3D memory structure <NUM> can have different arrangements and different depths (i.e., etched dielectric layer pair) in the first to seventh subsets of contact openings <NUM>, <NUM>-<NUM>, <NUM>-<NUM> and the hard mask openings <NUM>. In the other words, the aforementioned contact openings can be randomly distributed in the alternating dielectric stack <NUM>.

The fabrication processes can be continued by forming another contact mask covering at least a portion of the contact holes on the 3D memory structure <NUM> and then etching one or more dielectric layer pairs <NUM>. These process steps can be repeated until a top surface of each dielectric layer pair <NUM> is exposed inside at least one of the contact openings. In some embodiments, at an i-th process step for forming one or more subsets of contact openings, where i=<NUM>, <NUM>, <NUM>,. , each of current subsets of contact openings can be split into two groups, where one group can be subject to an etching process of <NUM>(i-<NUM>) number of dielectric layer pairs and form new subsets of contact openings. The other group in each of current subsets of contact openings can be protected by a mask and exposed to the etching process. After the i-th process step, top surfaces of the <NUM>st, <NUM>nd. , <NUM>i-th dielectric layer pairs can be exposed inside at least one of the contact openings.

In some embodiments, each of the current subsets of contact openings can be split into two groups with equal number of contact openings, where one group remains the same as current subsets of contact openings and the other group forms new subsets of contact openings. For example, N number of hard mask openings can be split into N/<NUM> number of hard mask openings and N/<NUM> number of first subset of contact openings. Next, the first subset of contact openings can be split into N/<NUM> number of second subset of contact openings and N/<NUM> number of first subset of contact openings. In this example, at least one contact opening can be formed for each dielectric layer pair of an alternating dielectric stack with a total <NUM>(n-<NUM>) number of dielectric layer pairs by using as few as n number of masks and etching steps.

After forming contact openings in the alternating dielectric stack <NUM>, the hard mask <NUM> can be removed.

Referring to <FIG>, at process step S455, a filling material can be disposed inside the contact openings, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S455 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes contact fills <NUM> formed by disposing a filling material <NUM> inside the contact openings (<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) and hard mask openings <NUM> in the 3D memory structure <NUM> (as shown in <FIG>). In some embodiments, the contact fill <NUM> also include a liner <NUM> disposed prior to the deposition of the filling material <NUM>.

The filling material <NUM> and the liner <NUM> can be any suitable material that can be selectively removed over the first dielectric layer <NUM> and/or second dielectric layer <NUM> in the subsequent processes. In some embodiments, the filling material <NUM> and the liner <NUM> can be an insulator, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, amorphous carbon, and/or a combination thereof. In some embodiments, the filling material <NUM> can be silicon nitride and the liner <NUM> can be silicon oxide. The filling material <NUM> and the liner <NUM> can be formed by CVD, PVD, sputtering, evaporating, and/or any combination thereof.

In some embodiments, the 3D memory structure <NUM> can be planarized after disposing the filling material <NUM> and the liner <NUM> to form a coplanar top surface.

Referring to <FIG>, at process step S460, a plurality of memory strings can be formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S460 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes a plurality of memory strings (e.g., the memory strings <NUM> in <FIG> and <FIG>).

To form the plurality of memory strings <NUM>, a plurality of channel holes (e.g., the channel holes <NUM>) can be formed first in the alternating dielectric stack <NUM>, penetrating the entire alternating dielectric stack <NUM> and extending into the substrate <NUM>. In some embodiments, forming of the channel holes <NUM> includes processes such as photolithography and etching. In some embodiments, a capping layer <NUM> formed by a carbon-based polymer material or a hard mask can be used in addition to photoresist for the etching process. The capping layer <NUM> can include silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, or polycrystalline silicon, or any combination thereof. The etching process to form the channel holes <NUM> can include a dry etching, a wet etching, or a combination thereof. In some embodiments, the alternating dielectric stack <NUM> can be etched using an anisotropic etching such as a reactive ion etch (RIE). In some embodiments, fluorine or chlorine based gases such as carbon-fluorine (CF<NUM>), hexafluoroethane (C<NUM>F<NUM>), CHF<NUM>, C<NUM>F<NUM>, Cl<NUM>, BCl<NUM>, etc., or any combination thereof, can be used. The methods and etchants to etch the first and second dielectric layers <NUM>/<NUM> should not be limited by the embodiments of the present disclosure.

In some embodiments, the 3D memory structure <NUM> further includes an epitaxial layer <NUM> inside the channel hole <NUM>. The epitaxial layer <NUM> can include any suitable semiconductor material, such as silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, III-V compound, or any combination thereof. The epitaxial layer <NUM> can be epitaxially grown from the substrate <NUM>. In some embodiments, the epitaxial layer <NUM> can be selectively grown from an exposed surface of the substrate <NUM> inside the channel hole <NUM>. In some embodiments, the epitaxial layer <NUM> can be a polycrystalline semiconductor material, for example, polycrystalline silicon.

In some embodiments, the epitaxial layer <NUM> can be epitaxially grown from a doped region (not shown in <FIG>) in the substrate <NUM>. The doped region can be formed by ion implantation using p-type or n-type dopants, for example boron, phosphorus, arsenic, or any combination thereof. The ion implantation can be performed before the deposition of the alternating dielectric stack <NUM>. In some embodiments, the ion implantation can be performed after channel hole etching.

After forming the channel holes <NUM> and epitaxial layer <NUM>, a memory film (e.g., the memory film <NUM> in <FIG>) can be disposed on a sidewall of each channel hole <NUM>, and a top surface of the epitaxial layer <NUM>. In some embodiments, the memory film <NUM> can be a composite layer including a tunneling layer, a storage layer (also known as "charge trap/storage layer"), and a blocking layer. Each channel hole <NUM> can have a cylinder shape. The tunneling layer, the storage layer, and the blocking layer are arranged along a direction from the center toward the outer of the channel hole in the above order, according to some embodiments. The tunneling layer can include silicon oxide, silicon nitride, or any combination thereof. The blocking layer can include silicon oxide, silicon nitride, high dielectric constant (high-k) dielectrics, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film <NUM> includes ONO dielectrics (e.g., a tunneling layer including silicon oxide, a storage layer including silicon nitride, and a blocking layer including silicon oxide).

Next, a channel layer <NUM> and a core filling film <NUM> can be disposed inside the channel holes <NUM>. The channel layer <NUM> covers a sidewall of the memory film <NUM> inside the channel hole <NUM> and is connected with the epitaxial layer <NUM>. The channel layer <NUM> can be any suitable semiconductor material such as silicon. In some embodiments, the channel layer <NUM> can be amorphous, polysilicon, or single crystalline silicon. The channel layer <NUM> can be formed by any suitable thin film deposition processes including, but not limited to, CVD, PVD, ALD, or a combination thereof. In some embodiments, a thickness of the channel layer <NUM> can be in a range from about <NUM> to about <NUM>. In some embodiments, the core filling film <NUM> can be disposed to fill each channel hole <NUM>. In some embodiments, the middle of the core filling film <NUM> can include one or more air gaps. The core filling film <NUM> can be any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, spin-on-glass, boron or phosphorus doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine doped oxide (SiOF), or any combination thereof. The core filling film <NUM> can be deposited by using, for example, ALD, PVD, CVD, spin-coating, sputtering, or any other suitable film deposition techniques. The core filling film <NUM> can also be formed by using repeated deposition and etch-back processes. The etch-back process can include, but not limited to, a wet etching, a dry etching, or a combination thereof.

In some embodiments, the core filling film <NUM>, the channel layer <NUM> and the capping layer <NUM> are can be coplanar in the 3D memory structure <NUM>. The planarization process includes chemical mechanical polishing, RIE, wet etching, or a combination thereof. The planarization process removes excess core filling film <NUM>, channel layer <NUM> and the memory film <NUM> outside the channel hole <NUM>. Accordingly, the channel layer <NUM> and the memory film <NUM> can be disconnected between adjacent channel holes <NUM>.

In some embodiments, a plurality of dummy memory strings (e.g., the dummy memory strings <NUM> in <FIG>) can also be formed in the alternating dielectric stack <NUM>, adjacent to the memory strings <NUM> and/or contact openings <NUM>, <NUM>-<NUM>, and <NUM>-<NUM>. While the memory strings <NUM> can be used for memory storage, dummy memory strings <NUM> can be used to provide structural support and improve process uniformity during manufacturing. In some embodiments, the dummy memory strings <NUM> can also include the core filling film <NUM> and can be formed using similar techniques as the memory strings <NUM>.

<FIG> illustrates a 3D memory structure <NUM>, according to some embodiments of the present disclosure. The 3D memory structure <NUM> includes a plurality of slit openings <NUM> penetrating through the entire alternating dielectric stack <NUM>. In some embodiments, the slit openings <NUM> can extend laterally along the WL direction in the x-y plane that parallel to the top surface 330f. The slit openings <NUM> can form slit structures <NUM> (in <FIG> and <FIG>) in subsequent fabrication processes. The arrangement of the slit openings <NUM> in <FIG> is only for illustration purpose and is not so limited.

Referring to <FIG>, at process step S465, a film stack of alternating conductive and dielectric layers can be formed, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S465 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes a film stack of alternating conductive and dielectric layers, similar to the film stack <NUM> in <FIG>.

After forming the slit openings <NUM>, the second dielectric layer <NUM> in the alternating dielectric stack <NUM> (in <FIG>) can be removed laterally from the slit openings <NUM>, forming lateral tunnels (not shown in <FIG>). Conductive layers <NUM> can then be disposed inside these lateral tunnel to form the film stack <NUM>.

The second dielectric layer <NUM> (in <FIG>) can be removed by any suitable etching process, e.g., an isotropic dry etch or wet etch, that is selective over the alternating dielectric stack <NUM>, such that the etching process can have minimal impact on the first dielectric layer <NUM>. In some embodiments, the second dielectric layer <NUM> can be silicon nitride. In this example, the second dielectric layer <NUM> can be removed by RIE using one or more etchants of CF<NUM>, CHF<NUM>, C<NUM>F<NUM>, C<NUM>F<NUM>, and CH<NUM>F<NUM>. In some embodiments, the second dielectric layer <NUM> can be removed using wet etch, such as phosphoric acid. After removing the second dielectric layer <NUM>, sidewalls of the memory film <NUM> can be exposed in the lateral tunnels.

In some embodiments, the conductive layer <NUM> can include any suitable conductive material that is suitable for a gate electrode, e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and/or any combination thereof. The conductive material can fill the lateral tunnels using a suitable deposition method such as CVD, physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, thermal evaporation, e-beam evaporation, metal-organic chemical vapor deposition (MOCVD), and/or ALD. In some embodiments, the conductive layers <NUM> include tungsten (W) deposited by CVD.

In some embodiments, the conductive layer <NUM> can also be poly-crystalline semiconductors, such as poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon and any other suitable material, and/or combinations thereof. In some embodiments, the poly-crystalline material can be incorporated with any suitable types of dopant, such as boron, phosphorous, or arsenic. In some embodiments, the conductive layer <NUM> can also be amorphous semiconductors.

In some embodiments, the conductive layer <NUM> can be made from a metal silicide, including WSix, CoSix, NiSix, or AlSiy, etc. The forming of the metal silicide material can include forming a metal layer and a poly-crystalline semiconductor using similar techniques described above. The forming of metal silicide can further include applying a thermal annealing process on the deposited metal layer and the poly-crystalline semiconductor layer, followed by removal of unreacted metal.

In some embodiments, a gate dielectric layer can be disposed in the lateral tunnels prior to the conductive layer <NUM> (not shown in <FIG>) to reduce leakage current between adjacent word lines (gate electrodes) and/or to reduce leakage current between gate and channel. The gate dielectric layer can include silicon oxide, silicon nitride, silicon oxynitride, and/or any suitable combinations thereof. The gate dielectric layer can also include high-k dielectric materials, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and/or any combination thereof. The gate dielectric layer can be disposed by one or more suitable deposition processes, such as CVD, PVD, and/or ALD.

The conductive layers <NUM> can function as gate electrodes at the intersection with memory strings <NUM>. In <FIG>, the ten conductive layers <NUM> can form ten gate electrodes for each memory string <NUM>, e.g., TSG <NUM>, LSG <NUM> and eight control gates <NUM>. Corresponding to eight control gates <NUM>, each memory string <NUM> can have eight memory cells <NUM>. It is noted that the number of memory strings and memory cells are shown for illustrative purposes in <FIG>, and can be increased for higher storage capacity.

After forming the film stack <NUM> of alternating conductive and dielectric layers, conductive materials inside the slit openings <NUM> during deposition can be removed. In some embodiments, insulating materials can be disposed inside some of the slit openings <NUM> to form slit structures <NUM>, separating a memory block into multiple programmable and readable memory fingers (see Fig. 2A-2B).

<FIG> illustrates a 3D memory structure <NUM>, according to some embodiments of the present disclosure. The 3D memory structure <NUM> includes a plurality of contact holes <NUM>, formed by removing the filling materials <NUM> inside the contact fills <NUM> in the 3D memory structure <NUM> in <FIG>. In some embodiments, the contact holes <NUM> can be formed by lithography, wet chemical etch, dry etch, or a combination thereof. In some embodiments, the contact holes <NUM> extend through the capping layer <NUM>, one or more pairs of conductive layer <NUM> and first dielectric layer <NUM>. The contact holes <NUM> can expose the conductive layer <NUM> in the film stack <NUM>. In some embodiments, the liner <NUM> covers a sidewall of each conductive layer <NUM> inside each contact hole <NUM> and exposes a top surface of a conductive layer <NUM> at a bottom of each contact hole <NUM>.

In some embodiments, an isolation liner <NUM> can be formed on a sidewall of the slit opening <NUM>, where the isolation liner <NUM> inside the slit opening <NUM> covers a sidewall of each conductive layer <NUM> of the film stack <NUM>. In some embodiments, the isolation liner <NUM> can also be formed inside the contact hole <NUM>. The isolation liner <NUM> can be any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride or any combination thereof.

Referring to <FIG>, at process step S470, a contact structure can be formed to electrically connect with the conductive layer in the film stack of alternating conductive and dielectric layers, according to some embodiments of the present disclosure. An exemplary 3D memory device at process step S470 is illustrated as a 3D memory structure <NUM> in <FIG>. The 3D memory structure <NUM> includes a plurality of contact structures, similar to the contact structures <NUM> in <FIG>, where the contact structure <NUM> provides electric connection with the conductive layer <NUM> in the film stack <NUM>. In some embodiments, each contact structure <NUM> includes a liner surrounding a conductive material. In some embodiments, the isolation liner <NUM> and/or the liner <NUM>, covered a sidewall of the contact structure <NUM>, can electrically isolate the contact structure <NUM> from one or more conductive layers <NUM> of the film stack <NUM>. The 3D memory structure <NUM> can also include a common source contact <NUM>, electrically connected with the substrate <NUM>. In some embodiments, the isolation liner <NUM> can electrically isolate the common source contact <NUM> from the conductive layers <NUM> of the film stack <NUM>.

The contact structure <NUM> and the common source contact <NUM> can be formed by disposing a conductive material inside the contact hole <NUM> and the slit opening <NUM>. In some embodiments, the conductive material can include tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and/or any combination thereof. The conductive material can be disposed by CVD, PVD, PECVD, MOCVD, sputtering, thermal evaporation, e-beam evaporation, ALD, and/or a combination thereof. In some embodiments, the conductive material can be tungsten (W) deposited by CVD.

In some embodiments, the conductive material used for the contact structure <NUM> and common source contact <NUM> can also be poly-crystalline semiconductors, such as poly-crystalline silicon, poly-crystalline germanium, poly-crystalline germanium-silicon and any other suitable material, and/or combinations thereof. In some embodiments, the poly-crystalline material can be incorporated with any suitable types of dopant, such as boron, phosphorous, or arsenic. In some embodiments, the conductive material can also be amorphous semiconductors.

In some embodiments, the conductive material can be made from a metal silicide, including WSix, CoSix, NiSix, or AlSiy, etc. The forming of the metal silicide material can include forming a metal layer and a poly-crystalline semiconductor using similar techniques described above. The forming of metal silicide can further include applying a thermal annealing process on the deposited metal layer and the poly-crystalline semiconductor layer, followed by removal of unreacted metal.

In some embodiments, excess conductive material outside the contact hole <NUM> and slit opening <NUM> can be removed after the deposition by using an etching process or planarization process. The etching process to remove the excess conductive material can include wet chemical etch and/or dry etch (e.g., RIE). The planarization process can include chemical mechanical polishing (CMP).

It is noted that the contact structures <NUM> in <FIG> and contact holes <NUM> in <FIG> correspond to the hard mask openings <NUM> and/or contact openings <NUM>, <NUM>-<NUM>, <NUM>-<NUM> in <FIG>. As discussed previously, in some embodiments, at least one contact opening can be formed for each dielectric layer pair in an alternating dielectric stack with a total <NUM>(n-<NUM>) number of dielectric layer pairs by using only n number of masks and etching steps. In addition, according to the present disclosure, at least one contact structure <NUM> can be formed for each conductive layer <NUM> in the film stack <NUM> without using a staircase structure. In this example, the contact structures <NUM> are formed in the channel structure region <NUM> (shown in <FIG>), i.e., inside a memory array, and the contact structure and the memory strings are arranged alternatingly along a X-direction in a portion of the channel structure region. In some embodiments, the contact structures <NUM> can be randomly distributed in the memory array, adjacent to the memory strings <NUM> and/or dummy memory strings <NUM>. The conductive layer <NUM> of the film stack <NUM> can be functioned as gate electrodes, for example, the control gate (word line) <NUM> and the top and lower select gates <NUM> and <NUM> shown in <FIG>. By moving the contact structures <NUM> close to the memory strings <NUM>, delay from word lines to gate electrodes of the memory cells <NUM> can be shortened accordingly. As a result, the performance of the 3D memory device can be improved. In some embodiments, dummy memory strings <NUM> can also be formed adjacent to the contact structures <NUM> and/or the memory strings <NUM> in the memory array.

In some embodiments, the contact masks used in the fabrication process <NUM> described in <FIG> can have different designs and arrangements. <FIG> provide perspective views of 3D memory structures at various process steps (e.g., process steps S410-S470), showing a different method to form the contact openings, compared with the examples in <FIG>, <FIG> and <FIG>. Detailed description for <FIG> is omitted here as the method shown is self-explanatory from these figures and can be understood by a person skilled in the art.

<FIG> illustrates another exemplary fabrication process <NUM> for forming a 3D memory device, accordance to some embodiments of the present disclosure. This fabrication process is not forming part of the claimed invention. Only the resulting memory structure of <FIG> is in accordance with the claimed invention. <FIG> illustrate cross-sectional views of the 3D memory device at various process steps according to the fabrication process <NUM>. It should be understood that the process steps shown in fabrication process <NUM> are not exhaustive and that other process steps can be performed as well before, after, or between any of the illustrated process steps. In some embodiments, some process steps of exemplary fabrication process <NUM> can be omitted or other process steps can be included, which are not described here for simplicity. In some embodiments, process steps of fabrication process <NUM> can be performed in a different order and/or vary.

Only the differences from <FIG>, <FIG>, and <FIG> are illustrated in <FIG>. Similar process steps and structures can be referred back to the previous figures and corresponding descriptions.

Referring to <FIG>, fabrication process <NUM> starts at process step S2210, where an alternating dielectric stack is disposed on a substrate. The exemplary 3D memory structure <NUM> of a 3D memory device at process step S2210 is shown in <FIG>. The alternating dielectric stack <NUM> can include first and second dielectric layers <NUM> and <NUM>.

Referring to <FIG>, at process step S2220, channel holes and memory strings can be formed in the alternating dielectric stack. An exemplary 3D memory structure <NUM> at process step S2220 is shown in <FIG>, where the channel holes <NUM> and the memory strings <NUM> are similar to the respective ones in <FIG> and can be formed by using similar techniques. At process step S2220, dummy memory strings, similar to the dummy memory strings <NUM> in <FIG> can also be formed by using similar techniques.

Referring to <FIG>, at process step S2230, a plurality of contact openings can be formed in the alternating dielectric stack by using multiple contact masks. An exemplary 3D memory structure <NUM> at process step S2230 is shown in <FIG>, where the hard mask openings <NUM>, the first subset of contact openings <NUM>, the second and third subsets of contact openings <NUM>-<NUM>, and the fourth to seventh subsets of contact openings <NUM>-<NUM> can be similar to the respective ones in <FIG> and can be formed by using similar processes in the process steps S415-S450 described in <FIG> and <FIG> and <FIG>.

Referring to <FIG>, at process step S2240, a liner is disposed on a sidewall of each contact openings. An exemplary 3D memory structure <NUM> at process step S2240 is shown in <FIG>, where the liner <NUM> is similar to the one in <FIG> and can be formed using similar techniques.

Referring to <FIG>, at process step S2250, slit openings can be formed in the alternating dielectric stack. An exemplary 3D memory structure <NUM> at process step S2250 is shown in <FIG>, where the slit opening <NUM> is similar to the one in <FIG> and can be formed using similar techniques.

Referring to <FIG>, at process step S2260, a film stack of alternating conductive and dielectric layers can be formed. An exemplary 3D memory structure <NUM> at process step S2260 is shown in <FIG>, where the film stack <NUM> of alternating conductive and dielectric layers is similar to the one in <FIG> and can be formed using similar techniques.

<FIG> illustrates a 3D memory structure <NUM>, according to some embodiments of the present disclosure. The 3D memory structure <NUM> includes the isolation liner <NUM> formed on a sidewall of the slit opening <NUM>. The isolation liner <NUM> can be similar to the one in <FIG>, and can be formed using similar techniques. The 3D memory structure <NUM> can also include the contact holes <NUM> formed inside the plurality of contact openings in <FIG> (e.g., the hard mask openings <NUM>, the first subset of contact openings <NUM>, the second and third subsets of contact openings <NUM>-<NUM>, and the fourth to seventh subset of contact openings <NUM>-<NUM>). The contact holes <NUM> expose top surfaces of the conductive layers <NUM> and can be formed using similar techniques as the ones shown in <FIG>.

Referring to <FIG>, at process step S2270, contact structures can be formed to electrically connect with the conductive layer in the film stack of alternating conductive and dielectric layers. An exemplary 3D memory structure <NUM> at process step S2270 is shown in <FIG>, where the contact structures <NUM> are similar to the ones in <FIG> and can be formed using similar techniques. The 3D memory structure <NUM> can also include the common source contact <NUM>, similar to the one in <FIG>.

Similar to fabricate process <NUM>, fabrication process <NUM> can also form at least one contact structure <NUM> for each conductive layer <NUM> in the film stack <NUM> of alternating conductive and dielectric layers. These contact structures <NUM> can be formed inside the channel structure region <NUM> (in <FIG>), and can be arranged adjacent to the memory strings <NUM>.

In summary, the present disclosure describes various embodiments of a 3D memory device and methods of making the same.

The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt, for various applications, such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the disclosure and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the disclosure and guidance.

Claim 1:
A three-dimensional (3D) memory structure (<NUM>, <NUM>) comprising:
a film stack (<NUM>), the film stack (<NUM>) comprising conductive and dielectric layers alternatingly stacked on top of each other in a vertical direction ;
memory strings (<NUM>) in a channel structure region penetrating through the film stack (<NUM>) in the vertical direction, wherein each of the memory strings (<NUM>) comprise a memory film (<NUM>), a channel layer (<NUM>) and a core filling film (<NUM>); and
contact structures (<NUM>) in the channel structure region penetrating through one or more of the conductive and dielectric layers in the vertical direction such that each conductive layer of the film stack is electrically connected to at least one of the contact structures, wherein
each contact structure (<NUM>) comprises a liner surrounding a conductive material, wherein the liner (<NUM>) comprises an insulator configured to electrically isolate the contact structures (<NUM>) from one or more conductive layers (<NUM>) of the film stack (<NUM>);
the conductive material contacts each conductive layer of the film stack;
characterized in that
the contact structures (<NUM>) and the memory strings (<NUM>) are arranged alternatingly along a X-direction, which is perpendicular to the vertical direction, in a portion of the channel structure region.