Patent Description:
Non-volatile memory device is almost the necessary part in digital electronic products. The digital electronic products, such as computer, mobile phone, camera, video recorder and so on, are also indispensable products in daily life. Thus, the non-volatile memory device is generally required.

Further due to a great development of multi-media in an example, the amount of stored data as needed is also accordingly increasing. In this situation, the development for designing the non-volatile memory is still proceeded, so to increase the storage capability for the limited device area. In other words, the device area occupied by the memory cell should be reduced.

In the developing technology, the resistive memory has been proposed. The resistive memory material in the structure of the resistive memory cell may vertically extend from the substrate to form the memory cell, so that the use of device area may be reduced. The property of resistive memory material is changing the conductive state of the resistive memory material by applying the operation bias, in which the resistance levels exits two states, so to be used for storing binary data.

Based on the structure of resistive memory device, it is still under developing that multiple memory cells may commonly share one control transistor.

<CIT> discloses a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

<CIT> discloses a resistive random access memory includes a substrate with a transistor, a bottom electrode electrically connected to the transistor source/drain, several top electrodes, and several resistance-switching layers and current limiting layers between the bottom electrode and top electrodes. The resistance-switching layers and/or current limiting layers, preferably of tantalum or hafnium oxide, may be integrally formed and shared by several cells. The 1TnR memory thus saves device area on the substrate by generating several conductive filaments at one transistor location.

<NPL> aims to provide RRAM as a cost-competitive candidate for high-density and high-capacity commercial products. Research results that advance the design of high-density RRAM arrays are presented. The scaling effects of on-chip interconnects on RRAM array performance is discussed.

<CIT> discloses memory devices and methods providing improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown aiming to provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

The invention provides a structure of memory device and a method for fabricating the memory device according to the appended claims. The memory device is based on the vertical memory structure and one transistor may be shared by multiple memory cells. In an example, four memory cells may share one transistor. The following disclosure serves abetter understanding of the present invention.

The invention provides a structure of memory device. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures are disposed on the conductive layer to form a quadrilateral structure.

In an embodiment, as to the structure of memory device, two of the four memory structures extend along a first direction as a first pair, and another two of the four memory structures extend along a second direction as a second pair, the first direction intersects the second direction.

In an embodiment, as to the structure of memory device, the structure further comprises four interconnection lines, respectively connected to the four memory structures.

In the invention, as to the structure of memory device, the structure further comprises a first pair of interconnection lines, respectively connected to the first pair of the four memory structures and a second pair of interconnection lines, respectively connected to the second pair of the four memory structures. The first pair of interconnection lines and the second pair of interconnection lines are extending along two different directions.

In an embodiment, as to the structure of memory device, the first pair of interconnection lines is higher than the second pair of interconnection lines.

In an embodiment, as to the structure of memory device, the first pair of interconnection lines has a protruding portion to contact the first pair of the four memory structures.

In an embodiment, as to the structure of memory device, the contact structure comprises at least one contact pole.

In an embodiment, as to the structure of memory device, each of the four memory structures is a resistive memory structure or a phase-change memory structure.

In an embodiment, as to the structure of memory device, the conductive layer is a single layer.

In an embodiment, as to the structure of memory device, the conductive layer comprises: a metal layer, disposed on the contact structure and a via layer, disposed on the metal layer, wherein the first pair of memory structures and the second pair of memory structures are disposed on the via layer.

In an embodiment, as to the structure of memory device, the via layer has a concave at a central region surrounded by a peripheral region, and the four memory structures are disposed on the via layer at the peripheral region.

The invention further provides a method for fabricating memory device. The method comprises forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are fomed on the conductive layer to form a quadrilateral structure.

In an embodiment, as to the method for fabricating memory device, two of the four memory structures extend along a first direction as a first pair, and another two of the four memory structures extend along a second direction as a second pair, the first direction intersects the second direction.

In an embodiment, as to the method for fabricating memory device, the method further comprises forming four interconnection lines, respectively connected to the four memory structures.

In the invention, as to the method for fabricating memory device, the method further comprises forming a first pair of interconnection lines, respectively connected to the first pair of the four memory structures; and forming a second pair of interconnection lines, respectively connected to the second pair of the four memory structures. The first pair of interconnection lines and the second pair of interconnection lines are extending along two different directions.

In an embodiment, as to the method for fabricating memory device, the first pair of interconnection lines is higher than the second pair of interconnection lines, wherein the first pair of interconnection lines has a protruding portion to contact the first pair of the four memory structures.

In an embodiment, as to the method for fabricating memory device, each of the four memory structures is a resistive memory structure or a phase-change memory structure.

In an embodiment, as to the method for fabricating memory device, the conductive layer is single layer.

In an embodiment, as to the method for fabricating memory device, the step of forming the conductive layer comprises forming a metal layer on the contact structure and forming a via layer on the metal layer, wherein the first pair of the memory structures and the second pair of the memory structures are disposed on the via layer.

In an embodiment, as to the method for fabricating memory device, the via layer has a concave at a central region surrounded by a peripheral region, and the four memory structures are disposed on the via layer at the peripheral region.

The invention is directed to semiconductor fabricating technology, in which the structure and the fabrication method for memory device is related to. The structure of memory device includes one transistor which may be at least shared by four memory structure in an example.

Several embodiments are provided for describing the invention, but the invention is not limited to the embodiments as provided. Further, the invention does not exclude a proper combination between the embodiments.

The invention firstly looks into a vertical memory device. <FIG> is a drawing in cross-sectional view, schematically illustrating a structure of vertical memory device as being looked into, according to an embodiment of the invention.

Referring to <FIG>, to a memory cell of the memory device, the usual implementation is that one transistor is corresponding to one memory structure. A transistor is formed on the substrate <NUM>. The basic structure of the transistor includes a gate insulating layer <NUM>, a gate electrode <NUM> on the gate insulating layer <NUM>, a spacer <NUM> on the sidewall of the gate <NUM> and source/drain regions <NUM> in the substrate <NUM> at both sides of the gate electrode <NUM>.

In fabrication, an inter-layer dielectric (ILD) layer <NUM> may covers over the substrate <NUM>. A contact structure <NUM> is formed in the inter-layer dielectric layer <NUM> to contact in connection with the source/drain regions <NUM>. An interconnection layer <NUM> as needed is also formed on the inter-layer dielectric layer <NUM> to connect another end of the contact structure <NUM>.

A memory structure is on the interconnection layer <NUM>. The memory structure includes a memory material layer <NUM>. In addition, a bottom electrode <NUM> and a top electrode <NUM> may also be included on the memory material layer <NUM>, so for external connection. A via structure <NUM> may also be on the top electrode <NUM>. Another end of the via structure <NUM> is further connected to the interconnection layer <NUM>. As usually known, due to the need in fabrication, the memory structure and the interconnection layer <NUM>, <NUM> are enclosed by the inter-layer dielectric layer. The detail is not described here.

After looking into the structure of memory device in <FIG>, the invention has observed that the device area used by the structure of the vertical memory device is mainly determined by the device area used by the transistor. Howe to make multiple memory cells to share one transistor is one of the concerning issues in developing trend. The invention provides a design structure in which multiple memory cells share one transistor.

<FIG> is a drawing in a perspective view, schematically illustrating a structure of vertical memory device, according to an embodiment of the invention. Referring to <FIG>, the structure of the memory device as provided in the invention includes a transistor <NUM> formed on the substrate <NUM>. The contact structure <NUM> is disposed on the source/drain region <NUM> of the transistor <NUM>. A conductive layer including the metal layer <NUM> and the via layer <NUM> in an example is disposed on the contact structure <NUM>. The number of the contact structure <NUM> as actually needed may be single or multiple. In an embodiment, the number of the contact structure <NUM> is two as an example. In an embodiment, the metal layer <NUM> of the conductive layer is disposed on the contact structure <NUM> with contact and is indirectly connected to the transistor <NUM>.

The four memory structures 216a, 216b, 216c, 216d are disposed on the via layer <NUM> of the conductive layer, to form a quadrilateral structure. Here, the inter-layer dielectric structure used to support the foregoing device elements during the fabrication is known in the ordinary art, the description in detail is omitted here.

In an embodiment, the conductive layer is formed by the metal layer <NUM> and the via layer <NUM> as stacked. In another embodiment, the conductive layer may be a single-layer structure. The use of the metal layer <NUM> is to improve the stable connection with contact structure <NUM>. The via structure <NUM> has is helpful to support the four memory structures 216a, 216b, 216c, 216d and is connected to the metal layer <NUM>, and then is further electrically connected to the contact structure <NUM>.

As to the structure of the via layer <NUM> for supporting the four memory structures 216a, 216b, 216c, 216d, it is also used to electric coupling between the four memory structures 216a, 216b, 216c, 216d and the source/drain region <NUM> of the transistor. In an embodiment, the via layer <NUM> has an indent <NUM> ate the central region in an example, surrounded by the peripheral region <NUM>. Thus, the four memory structures 216a, 216b, 216c, 216d are disposed on the peripheral region <NUM>.

In an embodiment, two memory structures 216a, 216b of the four memory structures 216a, 216b, 216c, 216d may be formed as a pair, and another memory structures 216c, 216d of the four memory structures 216a, 216b, 216c, 216d may be formed as another pair. The pair of memory structures 216a, 216b are respectively connected to two interconnection lines <NUM>. The interconnection lines <NUM> are extending along one direction. Another pair of memory structures 216c, 216d are respectively connected to another two interconnection lines <NUM>. The interconnection lines <NUM> are extending along another direction and intersect the interconnection lines <NUM>, such as perpendicularly intersecting. The four lines of the pair of the interconnection lines <NUM> and the pair of interconnection lines <NUM> may be respectively corresponding to the four memory structures 216a, 216b, 216c, 216d to apply the operation voltages which are for writing, reading or erasing operation.

Since the extending directions of the interconnection lines <NUM> and the interconnection lines <NUM> are different, resulting in intersection, the height as disposed in an embodiment may be different, so to avoid the short circuit due to contact. In an embodiment as an example, the pair of interconnection lines <NUM> corresponding to the pair of memory structures 216c, 216d may include a protruding part <NUM>, so that the pair of the interconnection lines <NUM> would be higher than the pair of the interconnection lines <NUM>, without contacting to each other. However, the invention is not limited to the embodiment.

The fabrication process flows are subsequently described. <FIG> are drawings in cross-sectional view, schematically illustrating a processing flow of fabricating the memory device, according to an embodiment of the invention.

Referring to <FIG>, the substrate <NUM> as provided is used to firstly fabricate a transistor <NUM> on the substrate <NUM>. The transistor <NUM> includes the source/drain region <NUM> in the substrate <NUM>. The inter-layer dielectric layer 306a is formed on the substrate <NUM> to cover over the transistor <NUM>. A contact structure <NUM> is formed in the inter-layer dielectric layer 306a in contacting with the source/drain region <NUM>. A further inter-layer dielectric layer 306b is formed on the inter-layer dielectric layer 306a. A metal layer <NUM> is formed in the inter-layer dielectric layer 306b to contact with the contact structure <NUM>, so to have the connection.

In an embodiment, a via layer may be further formed in the metal layer <NUM> to support the memory structures. In the formation of the via layer in the semiconductor fabrication flow, a further inter-layer dielectric layer 306c is formed on the inter-layer dielectric layer 306b. The inter-layer dielectric layer 306c has an opening <NUM> to expose the metal layer <NUM>. A via conductive layer <NUM> as to be subsequently formed into the via layer is formed in the inter-layer dielectric layer 306c. The via conductive layer <NUM> is also covering over the sidewall of the opening <NUM> and the exposed portion of the metal layer <NUM>. Another inter-layer dielectric layer 306d is formed on the inter-layer dielectric layer 306c, also filling into the indent corresponding to the opening <NUM>.

Referring to <FIG>, through the polishing process, a portion of the inter-layer dielectric layer 306d and the via conductive layer <NUM> above the inter-layer dielectric layer 306c is removed. As a result, the remaining portion of the via conductive layer <NUM> forms the conductive layer <NUM> as shown in <FIG>. The inter-layer dielectric layer 306d inside the opening <NUM> may still have the residual portion, so that a flat plane is obtained.

In an embodiment, the metal layer <NUM> and the via conductive layer <NUM> may be generally treated as a conductive layer <NUM>. As viewed to the structure, the conductive layer <NUM> may be a single layer or a combination of the metal layer <NUM> and the via conductive layer <NUM>, in an example. In addition, the via conductive layer <NUM> serving as the via layer in an embodiment may need no the indent at the central region corresponding to the opening <NUM>. The conductive layer <NUM> may be adjusted according to the actual design in need.

Referring to <FIG>, an inter-layer dielectric layer 306e is formed on the inter-layer dielectric layer 306d. The memory structure <NUM> is formed in the inter-layer dielectric layer 306e and contacts with the conductive layer <NUM>, such as contacting the via conductive layer <NUM> serving as the via layer, to have the connection. The memory structure <NUM> in an example includes memory material for the resistive memory structure or the phase change memory structure.

After planarization, the inter-layer dielectric layer 306f is further formed on the inter-layer dielectric layer 306e. The structure of the interconnection line <NUM> is subsequently formed in the inter-layer dielectric layer 306f to connect the memory structure <NUM>. As to the embodiment in <FIG>, the interconnection lines <NUM> have four lines, in which a pair of the interconnection lines <NUM> is shown in this cross-sectional structure.

As to the layout of the memory structurers <NUM> on the conductive layer <NUM> may have various manners. <FIG> is a drawing in a top view, schematically illustrating a portion of the structure of the memory device, according to an embodiment of the invention. Referring to <FIG>, when the via conductive layer <NUM> serving as the via layer may have the indent structure at the central region, in an example. The indent is filled by the inter-layer dielectric layer 306d. The peripheral region of the via conductive layer <NUM> in an example is shown in <FIG>, taking the quadrilateral geometric structure as an example. The four memory structures 316a, 316b, 316c, 316d are respectively located at four sides of the quadrilateral structure, in contact with the via conductive layer <NUM> as shared. Four interconnection lines 318a, 318b, 318c, 318d are respectively located above the memory structures 316a, 316b, 316c, 316d with contact. In the embodiment, the pair of interconnection lines 318a, 318b in an example is higher then the pair of interconnection lines 318c, 318d.

With the similar aspect, the implementation of the via conductive layer <NUM> and the memory structures 316a, 316b, 316c, 316d is not just limited to the embodiments and may have other modifications. <FIG> is a drawing in a plane view, schematically illustrating a layout of the memory device, according to an embodiment of the invention. Referring to <FIG>, the surface of the via conductive layer <NUM> may be flat without indent, in which there is no the inter-layer dielectric layer 306d shown in <FIG>. The locations of the memory structures 316a, 316b, 316c, 316d may be at proper locations of the via conductive layer <NUM>, such as at the center region for each of the four sides. In an embodiment, the conductive layer <NUM> as stated above in an integration may be the via conductive layer <NUM> as a single layer.

<FIG> is a drawing in a plane view, schematically illustrating a layout of the memory device, according to an embodiment of the invention. Referring to <FIG>, the locations of the memory structures 316a, 316b, 316c, 316d may also be on the four corners of the via conductive layer <NUM>.

<FIG> is a drawing in a perspective view, schematically illustrating a layout of the memory device, according to an embodiment of the invention. Referring to <FIG>, the implementation of the interconnection lines 318a, 318b, 318c, 318d is further described. In an embodiment, to adapt the heights of the interconnection lines 318a, 318b, 318c, 318d, in an example, the locations of the interconnection lines to connect to the memory structures 316c, 316d are relatively higher, so to avoid a short circuit by contact to the interconnection lines to connect to the memory structures 316a, 316b. The top of the memory structures 316c, 316d may additionally implemented with a protruding portion <NUM>. The protruding portion <NUM> in an embodiment may be as a part structure of the interconnection lines.

Further to an embodiment, the memory structures may directly have different heights in accordance with the connection to the interconnection lines. In this situation, the memory structure may have different lengths, in which the operation may accordingly adjusted. The invention is not just limited to the embodiments as provided.

Further to <FIG>, the structure as indicated by the dashed line is for the situation that the via conductive layer <NUM> serving as the via layer has the indent. Thus, the memory structures 316a, 316b, 316c, 316d are located at the peripheral region of the via conductive layer <NUM>. In an embodiment, the conductive layer <NUM> in an example is a combination of the metal layer <NUM> and the via conductive layer <NUM>. However, the conductive layer <NUM> may be just the via conductive layer <NUM> without stacking layer.

Claim 1:
A structure of memory device, comprising:
a transistor (<NUM>), formed on a substrate (<NUM>);
a contact structure (<NUM>), disposed on a source/drain region of the transistor;
a conductive layer (<NUM>+<NUM>, <NUM>), disposed on the contact structure;
four memory structures (216a-216d), disposed on the conductive layer to form a quadrilateral structure, wherein two of the four memory structures extend along a first direction as a first pair, and another two of the four memory structures extend along a second direction as a second pair, the first direction intersects the second direction;
a first pair of interconnection lines (<NUM>), respectively connected to the first pair of the four memory structures; and
a second pair of interconnection lines (<NUM>), respectively connected to the second pair of the four memory structures,
the structure of memory device being characterized in that the first pair of interconnection lines (<NUM>) and the second pair of interconnection lines (<NUM>) are extending along two different directions.