Patent Description:
Wideband wired data communications system circuitry can include several stages including modules to equalize, amplify and/or re-drive signals for its data channels. Usually one stage cannot provide enough gain or equalization. In such multistage systems, the use of intermediate buffers between each stage may be advantageous. Oftentimes, however, the buffer consumes even more power than the equalizer, amplifier and drivers, which makes a buffer block design more critical in the system, especially for use in low voltage (e.g., ~<NUM>. 8V) systems. What are needed are improvements in wide bandwidth communication circuitry that reduce the power consumption and lead to more efficiency.

United States patent, number <CIT> discloses a linear equalizer including sets of transistors, a resistor, and first and second obedience elements. A peaking gain of the linear equalizer is programmable by adjusting a direct current component of at least one input signal that is received at the least one input terminal and that is applied to the set transistors.

United States patent number <CIT> discloses a continuous time linear equalizer (CTLE) using both cross-coupled cascades and inductive peaking to reduce distortion in a signal received from the communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance with the equalizer are negligible, the equalizer essentially functions as a traditional cascade amplifier the present high gain. At high frequencies, the increases in inductive impedances within equalizer act to boost a gain of equalizer.

Embodiments of a wideband buffer circuit and a wideband communication circuit that uses the wideband buffer circuit are disclosed. In an embodiment, the wideband buffer circuit includes first and second transistors deployed as a voltage buffer and connected to first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. Similarly, the second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

In an embodiment, the wideband buffer circuit further includes a capacitor connected to a first node between the first cross-coupled transistor and the first current source and a second node between the second cross-coupled transistor and the second current source.

In an embodiment, the first output terminal is connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and the second output terminal is connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor.

In an embodiment, the first and second transistors are emitter followers.

In an embodiment, the first and second input terminals are connected to bases or gates of the first and second transistors.

In an embodiment, each of the first and second current sources includes a bipolar transistor and a resistor connected in series to ground.

In an embodiment, each of the first and second current sources includes a metal-oxide-semiconductor (MOS) transistor connected to the fixed voltage.

In an embodiment, the wideband buffer circuit further includes a first resistor connected to a supply voltage and the first transistor and a second resistor connected to the supply voltage and the second transistor.

In an embodiment, the wideband buffer circuit further includes a third current source connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and to the fixed voltage and a fourth current source connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor and to the fixed voltage.

In an embodiment, the wideband communication circuit includes a wideband buffer with first and second input terminals to receive input signals and first and second output terminals to transmit output signals, and a continuous-time linear equalizer (CTLE) connected to the first and second output terminals of the wideband buffer to equalize the output signals from the wideband buffer. The wideband buffer includes first and second transistors deployed as a voltage buffer and connected to the first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to the first and second output terminals, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. Similarly, the second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

In an embodiment, the wideband buffer further includes a capacitor connected to a first node between the first cross-coupled transistor and the first current source and a second node between the second cross-coupled transistor and the second current source.

In an embodiment, the first output terminal of the wideband buffer is connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and the second output terminal of the wideband buffer is connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor.

In an embodiment, the first and second input terminals of the wideband buffer are connected to bases or gates of the first and second transistors.

In an embodiment, the wideband buffer further comprises a first resistor connected to a supply voltage and the first transistor and a second resistor connected to the supply voltage and the second transistor.

In an embodiment, the wideband buffer further comprises a third current source connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and to the fixed voltage and a fourth current source connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor and to the fixed voltage.

In an embodiment, the wideband communication circuit further includes a transmitter driver connected to the CTLE, wherein the wideband communication circuit is a redriver.

In an embodiment, the wideband buffer circuit includes first and second transistors deployed as a voltage buffer and connected to first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, wherein resistors of the first and second parallel resistor-capacitor pairs provide signal paths for low frequency signals and wherein capacitors of the first and second parallel resistor-capacitor pairs provide signal paths for high frequency signals, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals, another capacitor connected to the first and second cross-coupled transistors and the first current source, wherein the another capacitor and the first and second cross-coupled transistors provide negative capacitance for bandwidth expansion, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. Similarly, the second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

In an embodiment, the wideband buffer circuit further includes a first resistor connected to a supply voltage and the first transistor and a second resistor connected to the supply voltage and the second transistor, wherein the first and second resistors provide protection from electrostatic discharge (ESD) events.

In an embodiment, the wideband buffer circuit further includes a third current source connected to a first node between the first parallel resistor-capacitor pair and the first cross-coupled transistor and to the fixed voltage and a fourth current source connected to a second node between the second parallel resistor-capacitor pair and the second cross-coupled transistor and to the fixed voltage, wherein the third and fourth current sources are configured to adjust DC values of output signals on the first and second output terminals.

These and other aspects in accordance with embodiments will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example of the principles of the embodiments.

It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended Figs. could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the Figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments.

The present invention may be embodied in other specific forms without departing from its essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the embodiments is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment.

<FIG> illustrates a typical architecture of a linear redriver <NUM> in accordance with prior art. The linear redriver <NUM> includes a continuous-time linear equalizer (CTLE) <NUM> to equalize input signals and a linear transmitter (TX) line driver <NUM> to retransmit the signals based on signal standard specifications. Due to gain variation over PVT (process, voltage and temperature) and significant parasitic loadings from the transmitter (not shown in <FIG>), a gain stage <NUM> may be needed between the CTLE <NUM> and the TX line driver <NUM>. The gain stage <NUM> can be a programmable gain amplifier (PGA) or an automatic gain control (AGC) stage. Depending on the design, the programmable gain stage can stay or be eliminated.

Turning now to <FIG>, a wideband wired communication circuit in the form of a linear redriver <NUM> without the need of a gain stage in which embodiments of the invention may be implemented is illustrated. As shown in <FIG>, the linear redriver <NUM>, which can be used in, for example, USB/HDMI/DP/Thunderbolt/PCIe/CIO data communication paths, includes an equalization block <NUM> that receives input signals at input terminals IP and IN and a transmission block <NUM> that outputs signal at output terminals OP and ON. The equalization block <NUM> includes a CTLE <NUM>, while the transmission block <NUM> includes a TX driver <NUM>. The TX driver <NUM> operates to drive a termination load disposed at a TX driver output. Output from the TX driver <NUM> typically drives <NUM>-Ohm load terminations <NUM> at its outputs, which are each connected to a switch <NUM>. The <NUM>-Ohm load terminations <NUM> and the associated switches <NUM> are shown as a Transmit Termination (TXT) within the dashed box positioned after the transmission block <NUM>. Similar <NUM>-Ohm loads <NUM> can also be found to affect the inputs of the equalization block <NUM>, which are also each connected to a switch <NUM>. The <NUM>-Ohm termination resistors <NUM> and the associated switches <NUM> are shown as a Receive Termination (RXT) within the dashed box positioned before the equalization block <NUM>. A CTLE buffer <NUM> (BUF), which is designed in accordance with embodiments of the invention, can be disposed inline before the CTLE <NUM> to isolate the CTLE from the inputs and set a certain direct current (DC) level for the CTLE. A TX pre-driver <NUM> (PDR) can be disposed inline after the CTLE <NUM> and before the TX driver <NUM>. A buffer circuit described herein in accordance with embodiments of the invention may be used as the CTLE buffer <NUM> and/or the TX pre-driver buffer <NUM>.

The TX driver <NUM> can be provided as a simple differential pair to drive what is typically a <NUM>-Ohm termination (see <FIG>, <NUM>-Ohm load terminations <NUM> or <NUM>-Ohm load of the next stage). But this can call for the differential pair transistors to be relatively large devices. Furthermore, parasitic capacitors of the TX driver <NUM> and routing may load the CTLE <NUM> and impact its performance. As a result, the TX predriver buffer <NUM> may be needed to isolate the CTLE <NUM> from the TX driver <NUM> and drive the long routing path from the CTLE to the TX driver. The TX pre-driver buffer <NUM> may also provide the right or desired DC level for the TX driver inputs.

The redriver <NUM> is illustrated using <NUM>-Ohm terminations <NUM> to supply as the input terminations. Thus, any circuit required for the redriver <NUM> needs to work with higher DC level. In the case of termination to ground, the circuit needs to work with lower DC levels.

Turning now to <FIG>, a wideband buffer circuit <NUM> in bipolar form in accordance with embodiments of the invention is illustrated. The architecture of this wideband buffer circuit <NUM> can be used to provide the signal buffering and level shifting functions desirable for wideband communications systems, including those depending on low voltage systems. It can also be used to boost the high frequency gain of a communications circuit to expand the bandwidth (BW) of signals. It can be used to fulfill the predriver and redriver requirements, as described with respect to <FIG>. Using bipolar transistors, which can also be provided in bipolar complementary metal-oxide-semiconductor (BiCMOS) technology, the input stage typically needs a certain DC level (e.g., set at the DC common mode voltage level, or needed by design, "desired level"). To achieve this, use of a buffer before CTLE <NUM>, as shown in <FIG>, is desirable to isolate incoming signals from inputs of the CTLE <NUM> and set their DC level.

As shown in <FIG>, the wideband buffer circuit <NUM> includes two parallel paths from a supply rail <NUM>, e.g., Vcc, to a fixed voltage, e.g., ground. The first path includes a resistor <NUM>-<NUM> with a resistance value of RU, a first bipolar transistor <NUM>-<NUM>, a parallel resistor-capacitor pair <NUM>-<NUM>, a second bipolar transistor <NUM>-<NUM> and a current source <NUM>-<NUM>. The parallel resistor-capacitor pair <NUM>-<NUM> includes a capacitor <NUM>-<NUM> with a capacitance value of Cs and a resistor <NUM>-<NUM> with a resistance value of RS. Similarly, the second path includes a resistor <NUM>-<NUM> with a resistance value of RU, a first bipolar transistor <NUM>-<NUM>, a parallel resistor-capacitor pair <NUM>-<NUM>, a second bipolar transistor <NUM>-<NUM> and a current source <NUM>-<NUM>. The parallel resistor-capacitor pair <NUM>-<NUM> includes a capacitor <NUM>-<NUM> with a capacitance value of CS and a resistor <NUM>-<NUM> with a resistance value of RS. The bipolar transistors <NUM>-<NUM> and <NUM>-<NUM> are cross-coupled transistors, where the emitters of these transistors are connected to a capacitor <NUM> with a capacitance value of C. Thus, the capacitor <NUM> is connected to a node between the transistor <NUM>-<NUM> and the current source <NUM>-<NUM>, and to a node between the transistor <NUM>-<NUM> and the current source <NUM>-<NUM>. The wideband buffer circuit <NUM> includes a pair of input terminals IP and IN, which are connected to the bases of the transistors <NUM>-<NUM> and <NUM>-<NUM>, respectively, and a pair of output terminals OP and ON, which are connected to the collectors of the transistors <NUM>-<NUM> and <NUM>-<NUM>, respectively. The input terminals IP and IN and the output terminals OP and ON are used to receive and output differential signals.

The pair of bipolar transistors <NUM>-<NUM> and <NUM>-<NUM>, which are configured as emitter followers, are the major devices to buffer the input signals on the input terminals IP and IN. These input transistors act as the main isolator between the inputs and the next stage. The current sources <NUM>-<NUM> and <NUM>-<NUM> provides bias current, which is DC current of IDC, which provide bias current for the wideband communications circuit <NUM>.

The resistors <NUM>-<NUM> and <NUM>-<NUM> help to protect the transistors <NUM>-<NUM> and <NUM>-<NUM> against electrostatic discharge (ESD) events with respect to supply. Each of the resistors <NUM>-<NUM> and <NUM>-<NUM> limits the current between DBC (base-collector Diode) of the connected transistor and the supply during ESD event, while zap is between the base, which may be connected to a pin when using the wideband buffer circuit <NUM> as a CTLE input buffer, and the supply. This will be a simple solution to protect the transistors <NUM>-<NUM> and <NUM>-<NUM> and removes the need of using large transistors to be self-robust against ESD event, which means smaller devices can be used that work for higher speed. It also avoids the need for a series resistor with each of the bases of the transistors <NUM>-<NUM> and <NUM>-<NUM>, which will reduce the BW and is a handicap for high-speed application.

The parallel resistor-capacitor pairs <NUM>-<NUM> and <NUM>-<NUM> shape DC and AC paths from the input terminals IP and IN to the output the output terminals OP and ON. Each of the resistors <NUM>-<NUM> and <NUM>-<NUM> causes a DC shift from the corresponding input to the corresponding output, which can be adjustable by changing the current IDC that is controlled by the corresponding current source <NUM>-<NUM> or <NUM>-<NUM>. The DC shift will be: VBE-RS*IDC, where VBE is the voltage across the base and the emitter of the transistor <NUM>-<NUM> or <NUM>-<NUM>, RS is the electrical resistance of each of the resistors <NUM>-<NUM> and <NUM>-<NUM>, and IDC is the current supplied by each of the current sources <NUM>-<NUM> and <NUM>-<NUM>. Thus, the DC shift can be adjusted with the RS value (to make it switchable which of course is not recommended in a high-speed application). In addition, making the current IDC programmable is the better solution and will not impact the high-speed performance of the wideband buffer circuit <NUM> significantly. The DC and low frequency path of signal will be through the resistor <NUM>-<NUM> or <NUM>-<NUM>. The high-speed path of signal will be through the capacitor <NUM>-<NUM> and <NUM>-<NUM>. Also, it is noted here that "RS and CS", where RS is the electrical resistance of each of the resistors <NUM>-<NUM> and <NUM>-<NUM> and CS is the capacitance of each of the capacitor <NUM>-<NUM> and <NUM>-<NUM>, forms a zero in the signal path which acts as a boost for higher frequency which compensates any BW reduction at high frequency. It practically serves as a passive CTLE in combination with the capacitance CLOAD and the resistance RLOAD for the load of the next stage which the wideband buffer circuit <NUM> is driving (e.g. a CTLE or a TX driver), which is illustrated in <FIG>. The value of the capacitors <NUM>-<NUM> and <NUM>-<NUM> can be adjusted to shape the zero. It also needs to be aligned with the negative capacitance (explained below) and CLOAD.

The cross-coupled transistors <NUM>-<NUM> and <NUM>-<NUM> and the capacitor <NUM> shape a negative capacitance to help BW expansion. The negative capacitance will partially compensate parasitic capacitances of the wideband buffer circuit <NUM> itself at the output terminals OP and ON and the capacitive loading effect of the next stage (CLOAD).

Negative capacitance for BW extension, which is implemented in the wideband buffer circuit <NUM>, is now described with reference to <FIG>, which illustrates a known technique to generate a negative capacitor. In general, it can be shown that using cross-coupled transistors <NUM>-<NUM> and <NUM>-<NUM>, which can be bipolar or metal-oxide-semiconductor (MOS) transistors that are provided with voltages Vp and Vm, respectively, that are connected to current sources <NUM>-<NUM> and <NUM>-<NUM> and an impedance element <NUM>, as shown in <FIG>, provides an input impedance of:<MAT>
where ZE is the impedance of an electrical element <NUM> and gm is the transconductance of each of the two transistors <NUM>-<NUM> and <NUM>-<NUM>. Thus, the input impedance will be approximately equal to the negative impedance of the load, if ZE >> <NUM>/gm. As a result, when the electrical element <NUM> is a capacitor with a capacitance of CE, combination of the transistors <NUM>-<NUM> and <NUM>-<NUM> and the capacitor <NUM> provide a negative capacitance of ~CE. Although this is shown for NPN-bipolar junction transistor (BJT) implementation in <FIG>, it is valid for the case where the transistors <NUM>-<NUM> and <NUM>-<NUM> are replaced with N-type MOS (NMOS) transistors. Also, the same principals are valid for PNP-BJT or P-type MOS (PMOS) transistor implementation.

Turning now to <FIG>, a complete wideband buffer circuit 600A having high-speed buffer and level shifter capabilities in bipolar technology with NPN BJTs in accordance with an embodiment of the invention is shown. The wideband buffer circuit 600A includes all the elements of the wideband buffer circuit <NUM> depicted in <FIG>. However, in <FIG>, the components of the current sources <NUM>-<NUM> and <NUM>-<NUM> are also illustrated. As shown in <FIG>, the current source <NUM>-<NUM> includes a bipolar transistor <NUM>-<NUM> and a resistor <NUM>-<NUM> with a resistance value of RE, which are connected in series. Similarly, the current source <NUM>-<NUM> includes a bipolar transistor <NUM>-<NUM> and a resistor <NUM>-<NUM> with a resistance value of RE, which are also connected in series. The wideband buffer circuit 600A may be implemented with PNP BJTs for lower common mode voltages at the input terminals IP and IN.

Turning now to <FIG>, a complete wideband buffer circuit 600B having high-speed buffer and level shifter capabilities in complementary metal-oxide-semiconductor (CMOS) technology with NMOS transistors in accordance with an embodiment of the invention is shown. The wideband buffer circuit 600B also includes all the elements of the wideband buffer circuit <NUM>. However, in <FIG>, the transistors are NMOS transistors. In addition, in <FIG>, the components of the current sources <NUM>-<NUM> and <NUM>-<NUM> are also illustrated. As shown in <FIG>, the current source <NUM>-<NUM> includes an NMOS transistor <NUM>-<NUM> and the current source <NUM>-<NUM> includes an NMOS transistor <NUM>-<NUM>. The wideband buffer circuit 600B may be implemented with PMOS transistors for lower common mode voltages at the input terminals IP and IN.

<FIG> shows a graph <NUM> that depicts the alternation current (AC) response of a wideband buffer circuit, such as the wideband buffer circuit 600A or 600B, with a differential load capacitance of CLOAD in accordance with an embodiment of the invention. In the graph <NUM>, the top curve <NUM> shows the AC response without the capacitor <NUM>-<NUM> or <NUM>-<NUM>, which is the DC (and low-frequency) signal path. The middle curve <NUM> shows the AC response of the buffer circuit with a negligible Rs, which is the high-frequency signal path, and as shown in the graph, it generates a zero to boost the high frequency gain, which is expanding the BW. The bottom curve <NUM> shows the complete buffer response, which has the expanded BW. The right adjustment of CS and CE (which generates the negative capacitance) for the CLOAD provides the desired BW of the buffer circuit.

Referring back to <FIG>, the output DC voltage of the wideband buffer circuit <NUM> can be adjusted by adjusting the IDC current sources <NUM>-<NUM> and <NUM>-<NUM>. However, there are applications where different output DC values may be needed. <FIG> shows a wideband buffer circuit <NUM> in accordance with an embodiment of the invention that can be used to adjust DC values of QP and QN outputs independently. The wideband buffer circuit <NUM> includes all the elements of the wideband buffer circuit <NUM>. In addition, the wideband buffer circuit <NUM> includes a current source <NUM>-<NUM> that is parallel to the current source <NUM>-<NUM>, and a current source <NUM>-<NUM> that is parallel to the current source <NUM>-<NUM>. The currents IDC1 and IDC2 supplied by the current sources <NUM>-<NUM> and <NUM>-<NUM> can be adjusted to adjust the DC values of QP and QN outputs independently.

Claim 1:
A wideband buffer circuit (<NUM>) comprising:
first and second transistors (<NUM>-<NUM>, <NUM>-<NUM>) deployed as a voltage buffer and connected to first and second input terminals;
first and second parallel resistor-capacitor pairs (<NUM>-<NUM>, <NUM>-<NUM>)_connected to the first and second transistors;
first and second cross-coupled transistors (<NUM>-<NUM>, <NUM>-<NUM>) connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals; and
first and second current sources (<NUM>-<NUM>, <NUM>-<NUM>) connected to the first and second cross-coupled transistors and a fixed voltage,
wherein the first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series and wherein the second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.