Patent Description:
Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using an ultra-fine mechanism. This achieves extreme programming accuracy and programming speed with optimal area.

<CIT> discloses an artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.

<CIT> discloses that numerous embodiments of programming systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

<FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes the artificial neural network adaptive to inputs and capable of learning. Typically, artificial neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for highperformance information processing is a lack of adequate hardware technology. Indeed, practical artificial neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>, published as <CIT>. The non-volatile memory arrays operate as an analog neuromorphic memory. The term neuromorphic, as used herein, means circuitry that implement models of neural systems. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells arranged in this manner can be referred to as a vector by matrix multiplication (VMM) array.

Examples of different non-volatile memory cells that can be used in VMMs will now be discussed.

Various types of known non-volatile memory cells can be used in the VMM arrays. For example, <CIT> ("the '<NUM> patent"), discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline terminal <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electron current will flow from the drain region <NUM> towards the source region <NUM> (source line terminal). The electrons will accelerate and become energized (heated) when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> with the addition of control gate (CG) terminal <NUM>. Control gate terminal <NUM> is biased at a high voltage, e.g., 10V, in programming, low or negative in erase, e.g., 0v/-8V, low or mid range in read, e.g., 0v/<NUM>. Other terminals are biased similarly to that of <FIG>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> except that memory cell <NUM> does not contain an erase gate EG terminal. An erase is performed by biasing the substrate <NUM> to a high voltage and biasing the control gate CG terminal <NUM> to a low or negative voltage. Alternatively, an erase is performed by biasing word line terminal <NUM> to a positive voltage and biasing control gate terminal <NUM> to a negative voltage. Programming and reading is similar to that of <FIG>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate terminal. The erase operation (whereby erasing occurs through use of the erase gate terminal) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line terminal during a program operation to compensate for a lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except that floating gate <NUM> extends over the entire channel region <NUM>, and control gate terminal <NUM> (which here will be coupled to a word line) extends over floating gate <NUM>, separated by an insulating layer (not shown). Programming is performed using hot electron injection from channel <NUM> to floating gate <NUM> in the channel region next to the drain region <NUM>, and erasing is performed using by Fowler-Nordheim electron tunneling from floating gate <NUM> to substrate <NUM>. The read operations operate in a similar manner to that described previously for memory cell <NUM>.

<FIG> depicts twin split-gate memory cell <NUM>. Memory cell <NUM> comprises floating gate (FG) <NUM> disposed over and insulated from the substrate <NUM>, a control gate <NUM> (CG) disposed over and insulated from the floating gate <NUM>, an erase gate <NUM> (EG) disposed adjacent to and insulated from the floating and control gates <NUM>/<NUM> and disposed over and insulated from the substrate <NUM>, where the erase gate is created with a T shape such that a top corner of the control gate CG faces the inside corner of the T shaped erase gate to improve erase efficiency, and a drain region <NUM> (DR) in the substrate adjacent the floating gate <NUM> (with a bit line contact <NUM> (BL) connected to the drain diffusion regions <NUM> (DR)). The memory cells are formed as pairs of memory cells (A on the left and B on the right), sharing a common erase gate <NUM>. This cell design differs from that the memory cells discussed above with reference to <FIG> at least in that it lacks a source region under the erase gate EG, lacks a select gate (also referred to as a word line), and lacks a channel region for each memory cell. Instead, a single continuous channel region <NUM> extends under both memory cells (i.e. extends from the drain region <NUM> of one memory cell to the drain region <NUM> of the other memory cell). To read or program one memory cell, the control gate <NUM> of the other memory cell is raised to a sufficient voltage to turn on the underlying channel region portion via voltage coupling to the floating gate <NUM> there between (e.g. to read or program cell A, the voltage on FGB is raised via voltage coupling from CGB to turn on the channel region portion under FGB). Erasing is performed using Fowler Nordheim electron tunneling from floating gate <NUM> to erase gate <NUM>. Programming is performed using hot electron injection from channel <NUM> to floating gate <NUM>, this is indicated as PROGRAM <NUM> in Table <NUM>. Alternatively, programming is performed using Fowler Nordheim electron tunneling from erase gate <NUM> to floating gate <NUM>, this is indicated as PROGRAM <NUM> in Table <NUM>. Alternatively programming is performed using Fowler Nordheim electron tunneling from channel <NUM> to floating gate <NUM>, in this case the condition is similar to PROGRAM <NUM> except the substrate is biased at a low voltage or negative voltage while erase gate is biased at a low positive voltage.

Table No. <NUM> depicts typical voltage ranges that can be applied to the terminals of memory cell <NUM> for performing read, erase, and program operations. Cell A (FG,CGA,BLA) is selected for read, program, and erase operation.

The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. The methods and means described herein may apply to volatile memory technologies used for neural network such as SRAM, DRAM, and other volatile synapse cells, without limitation.

S0 is the input layer, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the layers of feature map C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

<FIG> is a block diagram of a system that can be used for that purpose. VMM system <NUM> includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in <FIG>) between one layer and the next layer. Specifically, VMM system <NUM> comprises VMM array <NUM> comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the respective inputs for the non-volatile memory cell array <NUM>. Input to VMM array <NUM> can be from the erase gate and wordline gate decoder <NUM> or from the control gate decoder <NUM>. Source line decoder <NUM> in this example also decodes the output of VMM array <NUM>. Alternatively, bit line decoder <NUM> can decode the output of VMM array <NUM>.

VMM array <NUM> serves two purposes. First, it stores the weights that will be used by the VMM system <NUM>. Second, VMM array <NUM> effectively multiplies the inputs by the weights stored in VMM array <NUM> and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, VMM array <NUM> negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of VMM array <NUM> is supplied to a differential summer (such as a summing opamp or a summing current mirror) <NUM>, which sums up the outputs of VMM array <NUM> to create a single value for that convolution. The differential summer <NUM> is arranged to perform summation of both positive weight and negative weight inputs to output the single value.

The summed up output values of differential summer <NUM> are then supplied to an activation function circuit <NUM>, which rectifies the output. The activation function circuit <NUM> may provide sigmoid, tanh, ReLU functions, or any other non-linear function. The rectified output values of activation function circuit <NUM> become an element of a feature map of the next layer (e.g. C1 in <FIG>), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array <NUM> constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summer <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

The input to VMM system <NUM> in <FIG> (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level (e.g., current, voltage, or charge), binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

The output generated by input VMM system 32a is provided as an input to the next VMM system (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level <NUM>) 32c, and so on. The various layers of VMM system <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical system comprising a respective non-volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time multiplexed for various portion of its array or neurons. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion: <MAT>where <MAT> where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor = <NUM> + (Cdep/Cox) with Cdep = capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox* (n-<NUM>) * Vt<NUM> where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT> Here, wp is w of a reference or peripheral memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT>.

Here, wp is w of a reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier VMM array, the output current is: <MAT> <MAT> <MAT> <MAT>.

Alternatively, the non-volatile memory cells of VMM arrays described herein can be configured to operate in the linear region: <MAT> <MAT> meaning weight W in the linear region is proportional to (Vgs-Vth).

Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region: <MAT> <MAT>.

Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.

VMM array <NUM> implements uni-directional tuning for non-volatile memory cells in memory array <NUM>. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

The input to the VMM arrays can be an analog level, a binary level, timing pulses, or digital bits and the output can be an analog level, a binary level, timing pulses, or digital bits (in this case an output ADC is needed to convert output analog level current or voltage into digital bits).

For each memory cell in a VMM array, each weight w can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of <NUM> or more cells). In the differential cell case, two memory cells are needed to implement a weight w as a differential weight (w = w+- w-). In the two blend memory cells, two memory cells are needed to implement a weight w as an average of two cells.

One challenge with VMM arrays is that they require extreme precision during the programming process. For example, if each cell in the VMM array can store one of N different values (e.g., N=<NUM> or <NUM>), then the system must be able to deposit small increments of additional charge on the floating gate of the selected cell to achieve the desired change in level. One the other hand, it is still important that programming be as fast as possible, and there is an inherent tradeoff between programming precision and programming speed.

What is needed is an improved VMM system that is able to achieve precise programming while still completing the programming process at a relatively quick pace.

Numerous embodiments of analog neural memory arrays are disclosed. Two or more memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, and one or more of the memory cells can be programmed using a fine mechanism. This achieves extreme programming accuracy and programming speed.

<FIG> depicts a block diagram of VMM system <NUM>. VMM system <NUM> comprises VMM array <NUM>, row decoders <NUM>, high voltage decoders <NUM>, column decoders <NUM>, bit line drivers <NUM>, input circuit <NUM>, output circuit <NUM>, control logic <NUM>, and bias generator <NUM>. VMM system <NUM> further comprises high voltage generation block <NUM>, which comprises charge pump <NUM>, charge pump regulator <NUM>, and high voltage level generator <NUM>. VMM system <NUM> further comprises algorithm controller <NUM>, analog circuitry <NUM>, control logic <NUM>, and test control logic <NUM>. The systems and methods described below can be implemented in VMM system <NUM>.

The input circuit <NUM> may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter), AAC (analog to analog converter, such as current to voltage converter), PAC (pulse to analog level converter), or any other type of converters. The input circuit <NUM> may implement normalization, scaling functions, or arithmetic functions. The input circuit <NUM> may implement temperature compensation function for input. The input circuit <NUM> may implement activation function such as ReLU or sigmoid. The output circuit <NUM> may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as current to voltage converter), APC (analog to pulse(s) converter), or any other type of converters. The output circuit <NUM> may implement activation function such as ReLU or sigmoids. The output circuit <NUM> may implement statistic normalization, regularization, up/down scaling functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit <NUM> may implement temperature compensation function for neuron outputs or array outputs (such as bitline output) such as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.

<FIG> depicts prior art VMM system <NUM>. VMM system <NUM> comprises exemplary cells <NUM> and <NUM>, exemplary bit line switch <NUM> (which connects bit lines to sensing circuitry), exemplary dummy bit line switch <NUM> (which couples to a low level such as ground level in read), exemplary dummy cells <NUM> and <NUM> (source line pulldown cells). Bit line switch <NUM> is coupled to a column of cells, including cells <NUM> and <NUM>, that are used to store data in VMM system <NUM>. Dummy bit line switch <NUM> is coupled to a column (bitline) of cells that are dummy cells are not used to store data in VMM system <NUM>. This dummy bitline (aka source line pulldown bitline) is used as source line pulldown in read, meaning used to pull the source line SL to low level such ground level through the memory cells in the dummy bitline.

One drawback of VMM system <NUM> is that the input impedance for each cell varies due to the length of the electrical path through the relevant bit line switch, the cell itself, and the relevant dummy bit line switch. For example, <FIG> shows the electrical path through bit line switch <NUM>, cell <NUM>, dummy cell <NUM>, and dummy bit line switch <NUM>. Similarly, <FIG>shows the electrical path through bit line switch <NUM>, vertical metal bitline <NUM>, cell <NUM>, dummy cell <NUM>, vertical metal bitline <NUM>, and dummy bit line switch <NUM>. As can be seen, the path through cell <NUM> traverses a significantly larger length of bit line and dummy bit line, which is associated with a higher capacitance and higher resistance. This results in cell <NUM> having a greater parasitic impedance in the bit line or source line than cell <NUM>. This variability is a drawback, for instance, because it results in a variance in the precision of the cell output as applied to read or verify (for program/erase tuning cycles) cells depending on their location within the array.

<FIG> depicts improved VMM system <NUM>. VMM system <NUM> comprises exemplary cells <NUM> and <NUM>, exemplary bit line switch <NUM> (which connects the bit lines to sensing circuitry), exemplary dummy cells <NUM> and <NUM> (source line pulldown cells), and exemplary dummy bit line switch <NUM> (which couples to a low level such as ground level in read, this switch connects to dummy bit line that connects to dummy cells used as source line pulldown). As can be seen, exemplary dummy bit line switch <NUM> and the other dummy bit line switches are located on the opposite end of the array from bit line switch <NUM> and the other bit line switches.

The benefit of this design can be seen in <FIG> depicts the electrical path through bit line switch <NUM>, cell <NUM>, dummy cell <NUM> (source line pulldown cell), vertical metal bit line <NUM>, and dummy bit line switch <NUM> (which couples to a low level such as ground level in read). <FIG> depicts the electrical path through bit line switch <NUM>, vertical metal line <NUM>, cell <NUM>, dummy cell <NUM> (source line pulldown cell), and dummy bit line switch <NUM>. The paths are substantially the same (cells, interconnect lengths), which is true for all cells in VMM system <NUM>. As a result, the impedance of the bit line impedance plus source line impedance of each cell is substantially the same, which means that the variance in the amount of parasitic voltage drop drawn to read or verify operation of the various cells in the array is relatively same.

<FIG> depicts VMM system <NUM> with global source line pulldown bitline. VMM system <NUM> is similar to VMM system <NUM>, except that: the dummy bit lines 2005a-2005n or 2007a-2007n are connected together (to act as global source line pulldown lines to pull memory cell source lines to ground level during read or verify), the dummy bit line switches, such as dummy bit line switch <NUM> and <NUM>, are connected or coupled to a common ground; and the source lines are coupled together to source line switch <NUM>, which selectively pulls the source lines to ground. These changes further decrease the variance in (array) parasitic impedance among cells during read or verify operations.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises bit line switch <NUM>, pulldown bit line switch <NUM>, pulldown bit line switch <NUM>, bit line switch <NUM>, data cell <NUM> (herein, a "data cell" is a memory cell used to store a weight value for a neural network), pulldown cell <NUM>, pulldown cell <NUM>, and data cell <NUM>. Note that the pulldown cells <NUM> and <NUM> are adjacent to each together. This allows vertical metal lines BLpdx of the two pulldown cells <NUM> and <NUM> to be connected together (line <NUM>) to reduce parasitic resistance due to the resulting wider metal line. During a read or verify (for program/erase tuning cycles) operation of data cell <NUM>, current will flow through bit line switch <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM>, where it flows into the source line terminals of pulldown cells <NUM> and <NUM> and through pulldown bit line switches <NUM> and <NUM>. During a read or verify (for program/erase tuning cycles) operation of cell <NUM>, current will flow through bit line switch <NUM> into the bit line terminal of data cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM>, where it flows into the source line terminals of pulldown cells <NUM> and <NUM> and through pulldown bit line switches <NUM> and <NUM>. This pattern of columns repeats throughout the array, where every four columns contains two columns of data cells and two adjacent array columns used for pulldown operations. In another embodiment, the diffusion of the two pulldown cells of the two adjacent columns can be merged together into one bigger diffusion to increase the pulldown capability. In another embodiment, the diffusion of the pulldown cell can be made to be bigger than that of the data cell diffusion to increase the pulldown capability. In another embodiment, each pulldown cell has a bias condition different than a bias condition of a selected data cell.

In one embodiment, the pulldown cell has the same physical structure as a regular data memory cell. In another embodiment, the pulldown cell has a different physical structure than a regular data memory cell, for example, the pulldown cell can be a modified version of a regular data memory cell such as by modifying one or more physical dimensions (width, length, etc.) for electrical parameters (layer thickness, implant, etc.). In another embodiment, the pulldown cell is a regular transistor (without a floating gate) such as an IO or high voltage transistor.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises bit line <NUM>, pulldown bit line <NUM>, data cells <NUM> and <NUM>, pulldown cells <NUM> and <NUM>, and source line <NUM>. During a read or verify operation of cell <NUM>, current will flow through bit line switch <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM> and into the source line terminals of pulldown cell <NUM> and through pulldown bit line BLpd <NUM>. This design is repeated for every column, with the net result that the row containing pulldown cell <NUM> is a row of pulldown cells.

During a read or verify (for program/erase tuning cycles) operation of cell <NUM>, current will flow through bit line switch <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM> and into the source line terminals of pulldown cell <NUM> and through pulldown bit line <NUM>. This design is repeated for every column, with the net result that the row containing pulldown cell <NUM> is a row of pulldown cells. As shown in <FIG>, there are four rows, the two middle adjacent rows are used for pulldown cells, the top and bottom rows are data cells.

Table No. <NUM> depicts operating voltages for VMM system <NUM>. The columns in the table indicate the voltages placed on bit lines for selected cells, bit line pulldowns, word lines for selected cells, control gates for selected cells, word lines WLS for selected pulldown cells, control gates CGS for selected pulldown cells, erase gates for all cells, and source lines for all cells. Note that the voltage bias for CGS and WLS in read are higher than that of the regular WL and CG biases to enhance the drive capability of the pulldown cells. The voltage biased for WLS and CGS can be negative in programming to reduce disturb.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises bit line <NUM>, bit line <NUM>, data cells <NUM> and <NUM>, and pulldown cells <NUM> and <NUM>. During a read or verify (for program/erase tuning cycles) operation of cell <NUM>, current will flow through bit line <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line terminals of pulldown cell <NUM> and through bit line <NUM> (acting as pulldown bit line in this case). This design is repeated for every column, with the net result that the row containing pulldown cell <NUM>, in a first mode, is a row of pulldown cells. During a read or verify (for program/erase tuning cycles) operation of data cell <NUM>, current will flow through bit line <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line terminals of pulldown cell <NUM> and through bit line <NUM> (acting as pulldown bit line in this case). This design is repeated for every column, with the net result that the row containing pulldown cell <NUM>, in a second mode, is a row of pulldown cells. As shown in <FIG>, there are four rows, the alternative odd (or even) rows are used for pulldown cells, the alternative even (or odd) rows are data cells.

Notably, during a second mode, cells <NUM> and <NUM> are active in read or verify and cells <NUM> and <NUM> are used for the pulldown process, with the roles of bit lines <NUM> and <NUM> being reversed.

Table No. <NUM> depicts operating voltages for VMM system <NUM>. The columns in the table indicate the voltages placed on bit lines for selected data cells, bit lines for selected pulldown cells, word lines for selected data cells, control gates for selected data cells, word lines WLS for selected pulldown cells, control gates CGS for selected pulldown cells, erase gates for all cells, and source lines for all cells.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises bit line <NUM>, pulldown bit line <NUM>, (data) cell <NUM>, source line <NUM>, and pulldown cells <NUM>, <NUM>, and <NUM>. During a read or verify operation of cell <NUM>, current will flow through bit line <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM>, and where it then flows into the source line terminal of pulldown cells <NUM>, <NUM>, and <NUM>, from which is flows through pulldown bit line <NUM>. This design is repeated for every column, with the net result that the rows containing pulldown cells <NUM>, <NUM>, and <NUM> each are rows of pulldown cells. This maximizes the pulldown applied to the source line terminal of cell <NUM>, as current is drawn through three cells into pulldown bit line <NUM>. Note the source lines of the four rows are connected together.

Table No. <NUM> depicts operating voltages for VMM system <NUM>. The columns in the table indicate the voltages placed on bit lines for selected cells, bit line pulldowns, word lines for selected cells, control gates for selected cells, erase gates for selected cells, word lines WLS for selected pulldown cells, control gates CGS for selected pulldown cells, erase gates for selected pulldown cells, and source lines for all cells.

<FIG> depicts an exemplary layout <NUM> for VMM system <NUM> of <FIG>. The light squares indicate metal contacts to bit lines such as bit line <NUM> and pulldown bit lines such as pulldown bit line <NUM>.

<FIG> depicts an alternative layout <NUM> for a VMM system similar to the VMM system <NUM> of <FIG>, with the difference that pulldown bit line <NUM> is extremely wide and traverses two columns of pulldown cells. That is, the diffusion area for pulldown bit line <NUM> is wider than the diffusion area for bit line <NUM>. Layout <NUM> further shows cells <NUM> and <NUM> (pulldown cell), source line <NUM>, and bit line <NUM>. In another embodiment, the diffusion of the two pulldown cells (left and right) can be merged together into one bigger diffusion.

<FIG> depicts VMM system <NUM>. To implement negative and positive weights of a neural network, half of the bit lines are designated as w+ lines (bit lines connecting to memory cells implementing positive weights), and the other half of the bit lines are designated as w- lines (bit lines connecting to memory cells implementing negative weights) and are interspersed among the w+ lines in an alternating fashion. The negative operation is done at the output of the w- bit line (neuron output) by a summation circuit, such as summation circuits <NUM> and <NUM>. The output of a w+ line and the output of a w- line are combined together to give effectively w = w+ - w- for each pair of (w+, w-) cells for all pairs of (w+, w-) lines. The dummy bitlines or source line pulldown bitlines used to avoid FG-FG coupling and/or reduce IR voltage drop in the source line in read are not shown in the figure. The input (such as to CG or WL) to the system <NUM> can has positive value or negative value input. For the case of the input has negative value, since actual input to array is still positive (such as an voltage level on CG or WL), the array output (bitline output) is negated before output to realize the equivalent function of the negative value input.

Alternatively, with reference to <FIG>, positive weights can be implemented in a first array <NUM> and negative weights can implemented in a second array <NUM>, separate from the first array, and the resulting weights are appropriately combined together by summation circuits <NUM>. Similarly, the dummy bitlines (not shown) or source line pulldown bitlines (not shown) are used to avoid FG-FG coupling and/or reduce IR voltage drop in the source line in read.

Alternatively, <FIG> depicts VMM system <NUM> to implement negative and positive weights of a neural network with positive or negative input. First array <NUM> implements positive value inputs with negative and positive weights and second array <NUM> implements negative value inputs with negative and positive weights. The output of the second array is negated before adding to the output of the first array by the summer <NUM> since any input to any array only has positive value (such as an analog voltage level on CG or WL).

Table 10A shows an exemplary layout of a physical array arrangement of a (w+, w-) pair of bit lines BL0/<NUM> and BL2/<NUM>, where <NUM> rows are coupled to source line pulldown bit lines BLPWDNs. Pair of (BL0, BL1) bit lines is used to implement (w+, w-) lines. Between the (w+, w-) line pair, there is a source line pulldown bit line (BLPWDN). This is used to prevent coupling (e.g., FG to FG coupling) from adjacent (w+, w-) lines into the current (w+, w-) lines. Basically, the source line pulldown bit line (BLPWDN) serves as physical barrier between pair of (w+, w-) lines.

Additional details regarding the FG to FG coupling phenomena and mechanisms for counteracting that phenomena are found in <CIT> by the same assignee, and titled "Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network.

Table 10B shows different exemplary weight combination. '<NUM>' means that the cell is used and has a real output value, whereas '<NUM>' means the cell is not used and has no value or no significant output value.

In another embodiment, dummy bit lines instead of source line pulldown bit lines can be used.

In another embodiment, dummy rows can also be used as physical barriers to avoid coupling between rows.

Table 11A shows another array embodiment of a physical arrangement of (w+, ,w-) pair lines BL0/<NUM> and BL2/<NUM> with redundant lines BLO1,BL23 and source line pulldown bit lines BLPWDN. BLO1 is used to weight re-mapping for pair BL0/<NUM> and BL23 is used to weight remapping for pair BL2/<NUM>.

Table 11B shows a case of distributed weight that needs no re-mapping, basically there is no adjacent '<NUM>' between BL1 and BL3, which causes adjacent bit line coupling.

In one embodiment, the weight mapping is such that the total current along a bitline is approximately constant to maintain approximately constant bitline voltage drop. In another embodiment, the weight mapping is such that the total current along a source line is approximately constant to maintain approximately constant source line voltage drop.

Table 11C shows a case of distributed weight that needs re-mapping, basically there is adjacent '<NUM>' between BL1 and BL3, which causes adjacent bit line coupling. This re-mapping is shown in Table 11D, resulting in no '<NUM>' value between any adjacent bit lines. Furthermore, by re-mapping, meaning re-distributing the weights, the '<NUM>' real value weight among the bit lines, the total current along the bit line is now reduced leading to more precise value in the bit line (output neuron). In this case, additional columns (bitline) are needed (BLO1, BL23) to act as redundant columns. Tables 11E and 11F depict another embodiments of remapping noisy cells (or defective cells) into the redundant (spare) columns such as BL01, BL23 in Table 10E or BLOB and BL1B in Table 11F. A summer is used to sum up the bit line outputs with mapping appropriately.

Table <NUM> shows an embodiment of array physical arrangement that is suitable for <FIG>. Since each array has either positive weight or negative weight, a dummy bitline acting as source line pulldown and physical barrier to avoid FG-FG coupling is needed for each bit line.

Another embodiment has a tuning bit line as an adjacent bit line to a target bitline to tune the target bit line to final target by virtue of FG-FG coupling. In this case source line pulldown bitline (BLPWDN is inserted on one side of the target bit line that does not border the tuning bitline.

Alterative embodiment for mapping noisy or defective cells are to designate these cells (after identify them as noisy or defective by sensing circuitry) as non-used cells, meaning they are to be (deeply) programed to not contribute any value to the neuron output.

An embodiment for handling fast cells are first to identify these cells, then apply a more precision algorithm to these cells such as smaller or no voltage increment pulses or using floating gate coupling algorithm.

<FIG> depicts an optional redundant array <NUM> that can be included in any of the VMM arrays discussed thus far. Redundant array <NUM> can be used as redundancy to replace defective columns if any of the columns attached to bit line switches are deemed defective. The redundant array can have its own redundant neuron outputs (e.g., bit lines) and ADC circuits for redundancy purpose. For the case of redundancy is needed, the output of redundancy ADC is to replace the output of the ADC of the bad bit line. Redundant array <NUM> can also be used for weight mapping such as described in Table 10x for power distribution across bit lines.

<FIG> depicts VMM system <NUM>, which comprises array <NUM>, array <NUM>, column multiplexors <NUM>, local bit lines LBL 2905a-d, global bit line GBL <NUM> and <NUM>, and dummy bit line switches <NUM>. The column multiplexors <NUM> is used to select top local bit line <NUM> of the array <NUM> or bottom local bit line <NUM> of the array <NUM> into the global bit line <NUM>. In one embodiment, the (metal) global bit line <NUM> has the same number of lines as number of the local bit lines, e.g. <NUM> or <NUM>. In another embodiment, the global bit line <NUM> has only one (metal) line per N number of local bit lines, such as one global bit line per <NUM> or <NUM> local bit lines. The column multiplexors <NUM> further includes multiplexing (muxing) the adjacent global bit line (such as GBL <NUM>) into the current global bit line (such as GBL <NUM>) to effectively increase the width of the current global bit line. This reduces the voltage drop across the global bit line.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises array <NUM>, (shift registers) SRs <NUM>, digital-to-analog converters <NUM> (which receives the input from the SRs <NUM> and output an equivalent (analog or pseudo-analog) level or info), summer circuits <NUM>, analog-to-digital converters <NUM>, and bit line switches <NUM>. Dummy bit lines and dummy bit line switches are present but not shown. As shown, ADC circuits can be combined together to create a single ADC with greater precision (i.e., greater number of bits).

Summer circuits <NUM> can include the circuits that are shown in <FIG>. It may include circuits for normalization, scaling, arithmetic operations, activation, statistical rounding, etc..

<FIG> depicts current-to-voltage summer circuit <NUM> adjustable by a variable resistor, which comprises current source <NUM>-<NUM>,. , <NUM>-n drawing current Ineu(<NUM>),. , Ineu(n), respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier <NUM>, variable holding capacitor <NUM>, and variable resistor <NUM>. Operational amplifier <NUM> outputs a voltage, Vneuout = R3103 * (Ineu1 + Ineu0), which is proportional to the current Ineux. The holding capacitor <NUM> is used to hold the output voltage when switch <NUM> is open. This holding output voltage is used for example to be converted into digital bits by an ADC circuit.

<FIG> depicts current-to-voltage summer circuit <NUM> adjustable by a variable capacitor (basically an integrator), which comprises current source <NUM>-<NUM>,. , <NUM>-n drawing current Ineu(<NUM>),. Ineu (n), respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier <NUM>, variable capacitor <NUM>, and switch <NUM>. Operational amplifier <NUM> outputs a voltage, Vneuout = Ineu*integration time/C3203, which is proportional to the current Ineu(s).

<FIG> depicts voltage summer <NUM> adjustable by variable capacitors (i.e., a switch cap SC circuit), which comprises switches <NUM> and <NUM>, variable capacitors <NUM> and <NUM>, operational amplifier <NUM>, variable capacitor <NUM>, and switch <NUM>. When switch <NUM> is closed, input VinO is provided to operational amplifier <NUM>. When switch <NUM> is closed, input Vin1 is provided to operational amplifier <NUM>. Optionally, switches <NUM> and <NUM> are not closed at the same time. Operational amplifier <NUM> generates an output Vout, that is an amplified version of the input (either VinO and/or Vin1, depending on which switch is closed among switches <NUM> and <NUM>). That is Vout = Cin/Cout * (Vin), Cin is C3303 or C3304, Cout is C3306. For example, Vout = Cin/Cout * Σ (Vinx), Cin = C3303 = C3304. In one embodiment, VinO is a W+ voltage and Vin1 is a W- voltage, and voltage summer <NUM> adds them together to generate output voltage Vout.

<FIG> depicts voltage summer <NUM>, which comprises switches <NUM>, <NUM>, <NUM>, and <NUM>, variable input capacitors <NUM>, operational amplifier <NUM>, variable feedback capacitor <NUM>, and switch <NUM>. In one embodiment, VinO is a W+ voltage and Vin1 is a W-voltage, and voltage summer <NUM> adds them together to generate output voltage Vout.

For Input = VinO: when switch <NUM> and <NUM> are closed, input VinO is provided to top terminal of the capacitor <NUM>. Then switch <NUM> is open and switch <NUM> is closed to transfer the charge from the capacitor <NUM> into the feedback capacitor <NUM>. Basically, then the output VOUT = (C3358/C3356) * VinO (for case of with VREF =<NUM> as example).

For Input = Vin1: when switch <NUM> and <NUM> are closed, both terminals of the capacitor <NUM> are discharged to VREF. Then switch <NUM> is open and switch <NUM> is closed, charging the bottom terminal of the capacitor <NUM> to Vin1, which in turn charges up the feedback capacitor <NUM> to VOUT = -(C3358/C3356) * Vin1 (for case of VREF=<NUM>).

Hence, if Vin1 input is enabled after VinO input is enabled, VOUT = (C3358/C3356) * (Vin <NUM> - Vin1), for case of VREF=<NUM> as example. This is used for example to realize w = w+ - w-.

Methods of input and output operation to <FIG> which applies to the VMM arrays discussed above can be in digital or analog form. Methods include:.

By sequentially operates on the arrays, the power is more evenly distributed. The neuron (bit line) binary index method also reduce the power in the array since each cell in the bit line only has binary levels, the <NUM>^n level is accomplished by the summer circuit <NUM>.

Each ADC as shown in <FIG> can be configured to combine with next ADC for higher bit implementation with appropriate design of the ADC.

<FIG> depict output circuits that can be used for summer circuits <NUM> and analog-to-digital converters <NUM> in <FIG>.

<FIG> depicts output circuit <NUM>, which comprises analog-to-digital converter <NUM>, which receives neuron output <NUM> and outputs output digital bits <NUM>.

<FIG> depicts output circuit <NUM>, which comprises neuron output circuit <NUM> and analog-to-digital converter <NUM>, which together receive neuron output <NUM> and generates outputs <NUM>.

<FIG> depicts output circuit <NUM>, which comprises neuron output circuit <NUM> and converter <NUM>, which together receive neuron output <NUM> and generates outputs <NUM>.

Neuron output circuit <NUM> or <NUM> can, for example, perform summing, scaling, normalization, arithmetic operations, etc. Converter <NUM>, for example, can perform ADC, PDC, AAC, APC operation, etc..

<FIG> depicts neuron output circuit <NUM>, which comprises adjustable (scaling) current source <NUM> and adjustable (scaling) current source <NUM>, which together generate output iOUT, which is the neuron output. This circuit can perform summation of positive weight and negative weights, i.e., w = w+ - w-, and up or down scaling of the output neuron current at the same time.

<FIG> depicts configurable neuron serial analog-to-digital converter <NUM>. It includes integrator <NUM> which integrates the neuron output current into the integrating capacitor <NUM>. One embodiment is that the digital output (count output) <NUM> is produced by clocking the ramping VRAMP <NUM> until the comparator <NUM> switches polarity or another embodiment is by ramping down node VC <NUM> by the ramp current <NUM> until the VOUT <NUM> reaches the VREF <NUM>, at which point the EC <NUM> signal disables the counter <NUM>. The (n-bit) ADC is configurable to have lower number of bit precision <n -bits or higher number of bit precision > n -bits depending on target application. The configurability is done such as by configuring the capacitor <NUM>, the current <NUM>, or ramping rate of the VRAMP <NUM>, the clocking <NUM>, etc. In another embodiment, the ADC circuits of a VMM array is configured to have lower precision < n-bits and the ADC circuits of another VMM array is configured to have high precision > n-bits. Further this ADC circuit of one neuron circuit can be configured to combine with the next ADC of the next neuron circuit to produce higher n-bit ADC precision such as by combining the integrating capacitor <NUM> of the two ADC circuits.

<FIG> depicts configurable neuron SAR (successive approximation register) analog-to-digital converter <NUM>. This circuit is a successive approximation converter that bases on charge redistribution using binary capacitors. It includes a binary CDAC (DAC basing on capacitors) <NUM>, op-amp/comparator <NUM>, SAR logic <NUM>. As shown GndV <NUM> is a low voltage reference level, for example ground level.

<FIG> depicts a configurable neuron combo SAR analog-to-digital converter <NUM>. This circuit combines two ADCs from two neuron circuits into one to achieve higher precision n-bit, for example for <NUM>-bit ADC for one neuron circuit, this circuit can achieve > <NUM>-bit precision such as <NUM>-bit ADC precision by combining two <NUM>-bit ADCs. The combo circuit topology is equivalent to a split cap (bridge capacitor (cap) or attention cap) SAR ADC circuit, for example a <NUM>-bit 4C-4C SAR ADC resulted by combining two adjacent <NUM>-bit 4C SAR ADC circuits. A bridge circuit <NUM> is needed to accomplish this, the capacitance of capacitor of this circuit is = (total number of CDAC cap unit / total number of CDAC cap unit -<NUM>).

<FIG> depicts a configurable neuron, pipelined SAR CDAC ADC circuit <NUM> that can be used to combine with the next SAR ADC to increase the number of bits in a pipelined fashion. Residue voltage <NUM> is generated by capacitor <NUM> Cf to provide as input to next stage of pipelined ADC (e.g. to provide gain of <NUM> (ratio of Cf to C of all caps in DAC <NUM>) as input to next SAR CDAC ADC).

Additional implementation details regarding configurable output neuron (such as configurable neuron ADC) circuits can be found in <CIT> by the same assignee, and titled "Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in a Deep Learning Artificial Neural Network.

Applicant previously invented a mechanism for achieving precise data tuning in an analog neural memory in an artificial neural network, which is described in <CIT>, and titled, "Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network. " That previous application discloses embodiments for performing coarse programming, fine programming, and ultra-fine programming of a selected cell in a VMM. Thus, that application contemplates performing up to three types of programming on each selected cell. While this approach can achieve extremely precise programming, it also takes a significant amount of time, as each selected cell in the array must go through all three types of programming processes.

<FIG> depict embodiment that improve upon the programming mechanism of the prior art and the prior application.

<FIG> depicts logical cell <NUM>. In this example, logical cell comprises three memory cells, which are labeled fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM>. Fine cell <NUM>-<NUM> is coupled to fine bit line <NUM>-<NUM>, coarse cell <NUM>-<NUM> is coupled to coarse bit line <NUM>-<NUM>, and coarse cell <NUM>-<NUM> is coupled to coarse bit line <NUM>-<NUM>. Logical cell <NUM> contains data that in the prior art would have been stored in a (physical) single cell. For example, logical cell <NUM> can hold one of N different values, where N is the total number of different values that can be stored in logical cell <NUM> (e.g., N=<NUM> or <NUM>). Unlike in the prior art, rather than performing multiple types of programming (e.g., coarse programming and fine programming) on each physical cell, a coarse programming method is performed on coarse cell <NUM>-<NUM> over coarse bit line <NUM>-<NUM>, a coarse programming method is performed on coarse cell <NUM>-<NUM> over coarse bit line <NUM>-<NUM>, and a coarse and/or a fine programming method are performed on fine cell <NUM>-<NUM> over fine bit line <NUM>-<NUM>. That is, a fine programming method is not performed on coarse cells <NUM>-<NUM> and <NUM>-<NUM>. By implementing this approach, the programming time will be much shorter compared to the approach of doing coarse and fine programming for all three cells since fine programming, in particular, takes a relatively large amount of time.

<FIG> depicts program and verify method <NUM> performed on logical cell <NUM> of <FIG>.

The first step is to erase fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM> (step <NUM>). Optionally, the first step further comprises, after erasing, performing a coarse programming method on all three cells to intermediate values.

The second step is to program coarse cell <NUM>-<NUM> using a coarse programming method and to verify logical cell <NUM> after that operation to confirm that coarse cell <NUM>-<NUM> is correctly programmed to the intended coarse value for coarse cell <NUM>-<NUM> (step <NUM>). The alternative method is to verify the coarse cell by itself.

The third step is to program coarse cell <NUM>-<NUM> using a coarse programming method and to verify logical cell <NUM> after that operation to confirm that coarse cell <NUM>-<NUM> and coarse cell <NUM>-<NUM> together have been correctly programmed to the intended coarse value for coarse cells <NUM>-<NUM> and <NUM>-<NUM> together, reflected as the value for logical cell <NUM> (step <NUM>).

The fourth step is to program fine cell <NUM>-<NUM> using a fine programming method and to verify logical cell <NUM> after that operation to confirm that fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM> together have been correctly programmed to the intended value for logical cell <NUM> (step <NUM>).

Table <NUM> depicts examples of target values for logical cell <NUM>, fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM>:.

As can be appreciated with reference to Table <NUM>, only fine cell <NUM>-<NUM> needs to have a precise and accurate value within an allowed percentage (e.g., +/-<NUM>%, +/-<NUM>%, without limitation) of the final target value for logical cell <NUM>. For example, Applicant has determined that coarse cells can have as example +/-<NUM>% of the target value for the coarse cell (as any inaccuracy can be compensated for by fine cell <NUM>-<NUM>), whereas the fine cell can have +/-<NUM>% of the target value for the logical cell. Hence, coarse cells can be programmed with coarser voltage steps, which allows them to reach their targets much faster. One method of assigning the charge levels for each of the N levels for memory cells is as follows. First, determine a current range with maximum current Imax in sub-threshold or any other regions from data characterization, typically the current range Imax is within the voltage on the floating approximately = Vtfg - <NUM>. Second, determine the leakage current, Ileak, from the physical memory cell when the cell is in the off condition (e.g., WL =0V, CG = 0V). The lowest charge for the lowest of the N levels will be some factor a*Ileak, for example a = <NUM> for a <NUM> row array. The highest charge for the highest of the N levels is the charge associated with the maximum current Imax of the current range. Third, determine the program resolution when program to Imax using a coarse/fine or a coarse/fine/ultra-fine algorithm. Typically, a standard deviation (sigma) variation of the Imax target is a single electron program resolution for the coarse/fine algorithm and sub-electron program resolution for coarse/fine/ultra-fine (bitline tuning or floating gate-floating gate coupling tuning method). For example, a target delta level for a neural network could be = (IdeltaL= I(Ln) - I(Ln-<NUM>) = b*1sigma variation, b typically can be <NUM> or <NUM> or <NUM> depending on the desired network accuracy for a particular application. For exemplary embodiment, the number of levels, NL, is = (Imax- a*Ileak) / IdeltaL with a is a predetermined number basing on data characterization.

<FIG> depicts logical cell <NUM>. In this example, logical cell <NUM> comprises four memory cells, which are labeled tuning cell <NUM>-<NUM>, fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM>. Tuning cell <NUM>-<NUM> is coupled to tuning bit line <NUM>-<NUM>, fine cell <NUM>-<NUM> is coupled to fine bit line <NUM>-<NUM>, coarse cell <NUM>-<NUM> is coupled to coarse bit line <NUM>-<NUM>, and coarse cell <NUM>-<NUM> is coupled to coarse bit line <NUM>-<NUM>. Logical cell <NUM> contains data that in the prior art would have been stored in a single physical cell. For example, logical cell <NUM> can hold one of N different values, where N is the total number of different values that can be stored in logical cell (e.g., N=<NUM> or <NUM>). Unlike in the prior art, rather than performing multiple types of programming (e.g., coarse programming, fine programming, ultra-fine (FG-FG tuning) or tuning programming) on each physical cell, coarse programming is performed on coarse cell <NUM>-<NUM> over coarse bit line <NUM>-<NUM>, coarse programming is performed on coarse cell <NUM>-<NUM> over coarse bit line <NUM>-<NUM>, coarse and/or fine programming are performed on fine cell <NUM>-<NUM> over fine bit line <NUM>-<NUM>, and FG-FG tuning (ultra-fine) programming is performed on tuning cell <NUM>-<NUM> over tuning bit line <NUM>-<NUM>. That is, ultra-fine and fine programming are not performed on coarse cells <NUM>-<NUM> and <NUM>-<NUM>, and ultra-fine programming is not performed on fine cell <NUM>-<NUM>.

The ultra-fine programming allows the logical cell to reach within the target % of the final target value, for example +/- <NUM>% or +/-<NUM>%, without limitation. The ultra-fine programming is performed by programming the tuning cell <NUM>-<NUM>. The tuning cell <NUM>-<NUM> tunes the fine cell <NUM>-<NUM> through the FG-FG coupling (FG of the tuning cell <NUM>-<NUM> couples to FG of the fine cell <NUM>-<NUM>). For example, if the percentage of coupling from FG-FG of the tuning cell to the fine cell is ~<NUM>%, this means that a 4mV change in FG of the tuning cell (such as from CG program increment of 10mV of one cell ) results in <NUM>. 12mV change in FG of the fine cell (from FG to FG coupling of adjacent two cells). The coarse cell target for each of coarse cell <NUM>-<NUM> and <NUM>-<NUM> example can be within +/-<NUM>%, the fine cell target can be within <NUM>%, the tuning cell tuning target can be +/-<NUM>%. Note that only one tuning cell is needed for three (multiple) physical cells to realize one logic cell.

The first step is to erase tuning cell <NUM>-<NUM>, fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM> (step <NUM>). Optionally, the first step further comprises performing a coarse programming method on fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM> to intermediate values.

The second step is to program coarse cell <NUM>-<NUM> using a coarse programming method and to verify logical cell <NUM> after that operation to confirm that coarse cell <NUM>-<NUM> is correctly programmed to the intended coarse value for coarse cell <NUM>-<NUM> (step <NUM>).

The third step is to program coarse cell <NUM>-<NUM> using a coarse programming method and to verify logical cell <NUM> after that operation to confirm that coarse cell <NUM>-<NUM> and coarse cell <NUM>-<NUM> together have been correctly programmed to the intended coarse value for coarse cells <NUM>-<NUM> and <NUM>-<NUM> together (step <NUM>).

The fourth step is to program fine cell <NUM>-<NUM> using a fine programming method and to verify logical cell <NUM> after that operation to confirm that fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM> together have been correctly programmed to the intended value for logical cell <NUM> (step <NUM>).

The fifth step is to program tuning cell <NUM>-<NUM> using a tuning method and to verify logical cell <NUM> after that operation to confirm that tuning cell <NUM>-<NUM>, fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM> together have been correctly programmed to the intended value for logical cell <NUM> (step <NUM>).

Table <NUM> depicts examples of a target value for logical cell <NUM>, tuning cell <NUM>-<NUM>, fine cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, and coarse cell <NUM>-<NUM>:.

<FIG> depicts array <NUM>. Array <NUM> comprises a plurality of logical cells, such as exemplary logical cell <NUM>, which here follows the structure of logical cell <NUM>. Thus, logical cell <NUM> comprises tuning cell <NUM>-<NUM> coupled to tuning bit line <NUM>-<NUM>, fine cell <NUM>-<NUM> coupled to fine bit line <NUM>-<NUM>, coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>, and coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>. Here, each row contains a plurality of logical cells of the same structure as logical cell <NUM>, and array <NUM> comprises a plurality of rows, such as exemplary rows <NUM> and <NUM>. Note in the same row, the next logic cell has its tuning cell next to coarse cell of the previous logical cell, this is used to minimize FG-FG coupling between the two logical cells, as the capacitive effect will be relatively small on coarse cell <NUM>-<NUM> compared to, for example, fine cell <NUM>-<NUM>.

<FIG> depicts array <NUM>. Array <NUM> is similar to array <NUM> except that array <NUM> also comprises columns of isolation cells coupled to isolation bit lines. For example, array <NUM> comprises logical cell <NUM> comprising tuning cell <NUM>-<NUM> coupled to tuning bit line <NUM>-<NUM>, fine cell <NUM>-<NUM> coupled to fine bit line <NUM>-<NUM>, coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>, and coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>. Array <NUM> further comprises isolation cell <NUM>-<NUM> coupled to isolation bitline <NUM>-<NUM> and isolation cell <NUM>-<NUM> coupled to isolation bitline <NUM>-<NUM>, where isolation cells <NUM>-<NUM> and <NUM>-<NUM> are adjacent to logical cell <NUM> on either side of it. Isolation cells <NUM>-<NUM> and <NUM>-<NUM> are not used to store data; rather, they are used to provide a buffer between logical cells to reduce any unwanted disturb effects between logical cells. Preferably, the isolation cells are deeply programmed so that the FG voltage of the isolation cells is at the lowest value possible. Alternatively, the isolation cells are partially erased, fully erased, or in native state (no erase or program). Alternatively, the isolation cells are partially programmed. Alternatively, the isolation cells are dummy cells. Note that for the same row, the isolation cells in between logical cells is adjacent to one coarse cell of the previous logical cell and adjacent the tuning cell of the following logical cell.

<FIG> depicts array <NUM>. Array <NUM> is similar to array <NUM> except that array <NUM> also comprises columns of strap cells that are not coupled to any bit lines. For example, array <NUM> comprises logical cell <NUM> comprising tuning cell <NUM>-<NUM> coupled to tuning bit line <NUM>-<NUM>, fine cell <NUM>-<NUM> coupled to fine bit line <NUM>-<NUM>, coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>, and coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>. Array <NUM> further comprises strap cells <NUM>-<NUM> and <NUM>-<NUM> located adjacent to logical cell <NUM> on either side of it. Strap cells <NUM>-<NUM> and <NUM>-<NUM> are not used to store data; rather, they are used as an area in which conductive connections (like metal interconnect) can be made between various lines (poly lines) within array <NUM> (such as WL strap for word lines, EG strap for erase gate lines, CG strap for control gate lines, SL strap source lines, or strap combination like SLWL strap, SLCG strap, SLEG trap; strap cells might still have dummy floating gate structures in their structures) and devices and connections outside of array <NUM> (such as driver circuits). Alternatively, isolation cells are placed between strap cells and tuning cells. Alternatively, isolation cells are placed next to strap cells.

<FIG> depicts array <NUM>. Array <NUM> is similar to array <NUM> except that array <NUM> also comprises columns of pulldown cells coupled to pulldown source lines of the array. For example, array <NUM> comprises logical cell <NUM> comprising tuning cell <NUM>-<NUM> coupled to tuning bit line <NUM>-<NUM>, fine cell <NUM>-<NUM> coupled to fine bit line <NUM>-<NUM>, coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>, and coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>. Array <NUM> further comprises pulldown cell <NUM>-<NUM> coupled to pulldown bitline <NUM>-<NUM> and pulldown cell <NUM>-<NUM> coupled to pulldown bitline <NUM>-<NUM>, where pulldown cells <NUM>-<NUM> and <NUM>-<NUM> are adjacent to logical cell <NUM> on either side of it. Pulldown cells <NUM>-<NUM> and <NUM>-<NUM> are not used to store data; rather, as described above with reference to <FIG>, they are used to pulldown source line terminals to ground as needed.

<FIG> depicts array <NUM>. Array <NUM> comprises logical cell <NUM> comprising tuning cell <NUM>-<NUM> and tuning cell <NUM>-<NUM> coupled to tuning bit line <NUM>-<NUM>; coarse cell <NUM>-<NUM> and fine cell <NUM>-<NUM> coupled to mixed bit line <NUM>-<NUM>; coarse cell <NUM>-<NUM> and coarse cell <NUM>-<NUM> coupled to coarse bitline <NUM>-<NUM>. Thus, in array <NUM>, each logic cell comprises three cells in one row (such as an even row) and three cells in an adjacent row (such as an odd row). Three of the cells are coarse cells, one cell is a fine cell, and two cells are tuning cells. Consistent with programming methods described previously, when logic cell <NUM> is programmed, the order in which the cells are programmed are: coarse cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, coarse cell <NUM>-<NUM>, fine cell <NUM>-<NUM>, tuning cell <NUM>-<NUM> (which is expected to have minimal effect on coarse cell <NUM>-<NUM>), and tuning cell <NUM>-<NUM>. During a read or verify operation, all six cells are read as one logical cell. Through this approach, the mismatch between odd and even rows is averaged together such as to minimize I-V slope mismatch.

Claim 1:
A vector by matrix multiplication, VMM, array comprising:
a memory array of non-volatile memory cells (<NUM>) arranged in rows and columns and configured to provide inputs to the VMM array on the control gate lines and the output of the VMM array on the source lines, wherein the current placed on each source line performs a summing function of all the memory cells connected to that particular source line;
wherein the array comprises a logical cell (<NUM>) comprising one or more non-volatile memory cells (<NUM>) configured as coarse cells (<NUM>-<NUM>, <NUM>-<NUM>) and one or more non-volatile memory cells (<NUM>) configured as fine cells (<NUM>-<NUM>), wherein during a programming operation one of N possible values is stored and verified in the logical cell (<NUM>) by performing coarse programming (<NUM>, <NUM>) and not fine programming on the one or more coarse cells (<NUM>-<NUM>, <NUM>-<NUM>), performing fine programming (<NUM>) on the one or more fine cells (<NUM>-<NUM>), and verifying (<NUM>) the logical cell has been correctly programmed to the one of N possible values.