Patent Description:
Prior art wiring structures are disclosed in documents <CIT>, <CIT> and <CIT>.

Most of electronic device comprises a functional area with a plurality of functional units (e.g., displaying units, touching units, sensing unit, transmitting units, or receiving unit), a peripheral circuit area comprises a plurality of wires connected to the functional units respectively, and a chip IC connected drives the functional units through the wires. For narrow boarder purpose, the ratio of the functional area is getting higher and thus to compress the ratio of the peripheral circuit area. As resolution, quality, power increasing, number of wires or size of wires must increase to satisfy electrical requirement. New wiring structure must be developed for arranging more wires into a compact space.

This in mind, the present disclosure aims at providing an electronic device including a wiring structure with a mesh pattern region that can achieve some advantages, such as having a smaller area or narrower width, thereby increasing the overall device density, or having a stronger structure.

This is achieved by an electronic device according to the claims. The dependent claims pertain to corresponding further developments and improvements.

As will be seen more clearly from the detailed description following below, an electronic device including a wiring structure is provided by the present disclosure. The wiring structure includes a first wiring pattern, a second wiring pattern and a first insulating layer. The first wiring pattern comprises a plurality of first input wires along a first direction, a plurality of first output wires along the first direction and a plurality of first bridge wires along the first direction, wherein the plurality of first bridge wires are disposed between the plurality of first input wires and the plurality of first output wires. The second wiring pattern comprises a plurality of second input wires along a second direction different from the first direction, a plurality of second output wires along the second direction and a plurality of second bridge wires along the second direction, wherein the plurality of second bridge wires are disposed between the plurality of second input wires and the plurality of second output wires, one of the plurality of second bridge wiring crosses at least one of the plurality of first input wires or at least one of plurality of first output wires. The first insulating layer is disposed between the first wiring pattern and the second wiring pattern, wherein the second wiring pattern is disposed on the first insulating layer, and the first wiring pattern and the second wiring pattern are different layers and separated with the first insulating layer. One of the plurality of first input wires is electrically connected to corresponding one of the plurality of first output wires through one of the plurality of second bridge wires. The first wiring pattern further comprises a plurality of first input terminals along a third direction different from the first direction and the second direction, and the plurality of first input terminals are electrically connected to the plurality of first input wires respectively, the second wiring pattern further comprises a plurality of second input terminals along the third direction and electrically connected to the plurality of second input wires respectively, and the plurality of first input terminals interlace with the plurality of second input terminals.

The present disclosure provides a wiring structure of an electronic device, the wiring structure can be formed by two different wiring patterns, and the two different wiring patterns can be electrically connected to each other through a plurality of contact structures. The two wiring patterns are overlapped with each other and to form the wiring structure with a mesh pattern region. The wiring structure with a mesh pattern region has some advantages, such as having a compact area or narrower width, thereby increasing the overall device density, or having a narrow boarder area.

These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the embodiment that is illustrated in the various figures and drawings.

In the following, the disclosure is further illustrated by way of example, taking reference to the accompanying drawings.

The present disclosure may be understood by reference to the following detailed description, taken in conjunction with the drawings as described below. It is noted that, for purposes of illustrative clarity and being easily understood by the readers, various drawings of this disclosure show a portion of an electronic device (i.e. a display device in this disclosure), and certain elements in various drawings may not be drawn to scale. In addition, the number and dimension of each device shown in drawings are only illustrative and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will understand, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include", "comprise" and "have" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Thus, when the terms "include", "comprise" and/or "have" are used in the description of the present disclosure, the corresponding features, areas, steps, operations and/or components would be pointed to existence, but not limited to the existence of one or a plurality of the corresponding features, areas, steps, operations and/or components.

When the corresponding component such as layer or area is referred to "on another component (or the variant thereof)" or "extend to another component", it may be directly on another component or directly extend to another component, or other component may exist between them. On the other hand, when the component is referred to "directly on another component (or the variant thereof)" or "directly extend to another component", any component does not exist between them.

It will be understood that when an element or layer is referred to as being "connected to" another element or layer, it can be directly connected to the other element or layer, or intervening elements or layers may be presented. In contrast, when an element is referred to as being "directly connected to" another element or layer, there are no intervening elements or layers presented. In addition, when the component is referred to "be coupled to/with another component (or the variant thereof)", it may be directly connected to another component, or may be indirectly connected (such as electrically connected) to another component through other component or components.

It will be understood that when "a portion of a structure" is between another two components, this structure can be totally between or partially between these components.

The terms "about", "substantially", "equal", or "same" generally mean within <NUM>% of a given value or range, or mean within <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, or <NUM>% of a given value or range.

In addition, the phrase "in a range from a first value to a second value" indicates the range includes the first value, the second value, and other values in between.

One wire "cross" another wire generally means two individual wires have overlap region in a top view (plane view). The two wires may be in different layers and electrically isolated to each other. One group of wires "interlace with" another group of wires generally means two individual groups of wires are arranged alternately into a stagger pattern.

Two wires "electrically independent" generally means that the two wires are electrically isolated in the beginning when there is no electrical connection (e.g., direct contact or contact to each other through via hole) therebetween, and they may be electrically connected while further electrical connection is established.

One direction is "inbetween" two the other directions generally mean an included angle (in counterclockwise direction) between the direction and a reference direction is between the other two included angles (in counterclockwise direction) between the other directions and the reference direction respectively.

Although terms such as first, second, third, etc., may be used to describe diverse constituent elements, such constituent elements are not limited by the terms. The terms are used only to discriminate a constituent element from other constituent elements in the specification. The claims may not use the same terms, but instead may use the terms first, second, third, etc. with respect to the order in which an element is claimed. Accordingly, in the following description, a first constituent element may be a second constituent element in a claim.

Electronic device may be one of display device, antenna device, sensing device or splicing device, but not be limited thereto. Electronic device may be flexible or foldable devices. Electronic device may be liquid crystal display device, organic light emitting diode display device (OLED), inorganic light emitting diode display device (LED), minimeter-sized light emitting diode display device (mini-LED), micrometer-sized light emitting diode display device (micro-LED), quantum dot light emitting diode display device (QLED), but not be limited thereto. Antenna device may be liquid crystal antenna device, but not be limited thereto. Splicing device may be splicing display device or splicing antenna device, but not be limited thereto.

Referring to <FIG>, <FIG> is a schematic diagram showing a top view of a first wiring pattern according to a first embodiment of the present disclosure, <FIG> is a schematic diagram showing a top view of a second wiring pattern according to a first embodiment of the present disclosure, and <FIG> is a schematic diagram showing a top view of a wiring structure of an electronic device comprising the first wiring pattern, the second wiring pattern and a plurality of second intermediate wires according to a first embodiment of the present disclosure. The wiring structure is located in a peripheral area of the electronic device, and the wiring structure is electrically connected to a plurality of function units of a functional area of the electronic device and driving IC. The functional units are display units (e.g., display pixels, light emitting diode), sensing units (e.g., touch sensors, finger print sensors), or antenna units. The wiring structure still is located in the functional area for driving functional units. As shown in <FIG>, the present disclosure includes a wiring structure <NUM> in an electronic device, the wiring structure <NUM> includes at least two patterns: a first wiring pattern <NUM> (shown in <FIG>) and a second wiring pattern <NUM> (shown in <FIG>). In one embodiment of the present disclosure, the first wiring pattern <NUM> and the second wiring pattern <NUM> are in different layers and electrically independent to each other, and separated with an insulating layer. In one embodiment of the present disclosure, the second wiring pattern <NUM> is disposed above the first wiring pattern <NUM>, in other words, when viewed in a top view, the second wiring pattern <NUM> partially overlaps the first wiring pattern <NUM>. In another embodiment, the second wiring pattern <NUM> is under the first pattern <NUM>. In one embodiment of the present disclosure, the first wiring pattern <NUM> and the second wiring pattern <NUM> are symmetrical along a vertical direction (such as the Y-axis shown in <FIG>). In another embodiment, an included angle (acute angle) between the first wiring pattern <NUM> and the vertical direction is different from an include angle (acute angle) between the second wiring pattern <NUM> and the vertical direction, and the first wiring pattern <NUM> and the second wiring pattern <NUM> are asymmetrical.

In one embodiment of the present disclosure, the first wiring pattern <NUM> at least comprises three parts: a plurality of first input wires <NUM>, a plurality of first output wires <NUM> and a plurality of first bridge wires <NUM>, wherein in some embodiments, each first input wires <NUM>, each first output wires <NUM> and each first bridge wires <NUM> are arranged along a first direction D1 separately and electrically independent to each other. Besides, in the top view, the angle (acute angle) between the vertical direction (i.e. the Y-axis) and the first direction D1 (in clockwise direction) is defined as a first angle θ1, wherein in the present disclosure, the first angle θ1 is greater than <NUM> degree and smaller than <NUM> degrees.

In one embodiment of the present disclosure, the first input wires <NUM>, the first output wires <NUM> and the first bridge wires <NUM> are separated from each other with interval therebetween. In other words, the plurality of the first input wires <NUM> do not contact to each other directly, the plurality of the first output wires <NUM> do not contact to each other directly, and the plurality of the first bridge wires <NUM> do not contact to each other directly. In addition, in one embodiment of the present disclosure, the number of the first input wires <NUM> can be same as the number of the first output wires <NUM>. For example, in this embodiment, there are five first input wires <NUM> and five first output wires <NUM> shown in <FIG>. In another embodiment, the number of first input wires <NUM> is different from the number of the first output wires <NUM>. Besides, the first bridge wires <NUM> are disposed between the first input wires <NUM> and the first output wires <NUM>. In other words, the first bridge wires <NUM> are located in an interval space between an area of first input wires <NUM> and an area of first output wires <NUM>.

Besides, in one embodiment of the present disclosure, the first wiring pattern <NUM> further comprises a plurality of first input terminals <NUM> and a plurality of first output terminals <NUM>. The first input terminals <NUM> and the first output terminals <NUM> are arranged along a third direction D3 (i.e. the Y-axis). In the embodiment, the third direction D3 (i.e. the Y-axis) is inbetween the first direction D1 and the second direction D2. In one embodiment, each first input terminal <NUM> is electrically connected to one first input wire <NUM> respectively (the first input terminals <NUM> may electrically connect to driving IC through contact pads), and the number of the first input wires <NUM> is same as the number of the first input terminals <NUM> (for example, there are five first input terminals <NUM> shown in <FIG>). In another embodiment, the number of the first input wires <NUM> is different from the number of the first input terminals <NUM>. On the other hand, each first output terminal <NUM> is electrically connected to one first output wire <NUM> respectively (the first output terminals <NUM> electrically connects to functional units in the functional area of the electronic device), and the number of the first output wires <NUM> is same as the number of the first output terminals <NUM> (for example, there are five first output terminals <NUM> shown in <FIG>). In another embodiment, the number of the first output wires <NUM> is different from the number of the first output terminals <NUM>.

In one embodiment of the present disclosure, the first wiring pattern <NUM> is formed on a substrate <NUM>, the substrate <NUM> is a rigid substrate or a flexible substrate, wherein the rigid substrate is such as a glass substrate, a plastic substrate, a quartz substrate, a sapphire substrate or other suitable rigid substrate, and the flexible substrate includes polyimide (PI), polyethylene terephthalate (PET) and/or other suitable flexible material. And first wiring pattern <NUM> includes metal (Cu, Al, Mo, Ti, Ag, Au, etc.) and/or transparent conductive material, wherein the transparent conductive material includes indium tin oxide (ITO), indium zinc oxide (IZO)) and/or any other suitable conductive material.

Next, as shown in <FIG>, a first insulating layer <NUM> is formed, to cover the substrate <NUM> and the first wiring pattern <NUM>, and a second wiring pattern <NUM> is then formed on the first insulating layer <NUM>. Therefore, the first insulating layer <NUM> is disposed between the first wiring pattern <NUM> and the second wiring pattern <NUM> for electrically isolated in the beginning. In order to simplify the illustration, only the second wiring pattern <NUM> is drawn in <FIG>, and the first wiring pattern <NUM> is omitted from <FIG>.

In one embodiment of the present disclosure, the material of the first insulating layer <NUM> includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and/or any other suitable insulating material, but not limited thereto. The second wiring pattern <NUM> includes metal (Cu, Al, Mo, Ti, Ag, Au, etc.) and/or transparent conductive material, wherein the transparent conductive material can include indium tin oxide (ITO), indium zinc oxide (IZO)) and/or any other suitable conductive material, but not limited thereto. The second wiring pattern <NUM> is formed on the first insulating layer <NUM>, wherein the second wiring pattern <NUM> partially overlaps the first wiring pattern <NUM> in the top view, and in one embodiment of the present disclosure, the first wiring pattern <NUM> and the second wiring pattern <NUM> are symmetrical along a vertical direction. In another embodiment, an included angle between the first wiring pattern <NUM> and the vertical direction is different from an include angle between the second wiring pattern <NUM> and the vertical direction, and the first wiring pattern <NUM> and the second wiring pattern <NUM> are asymmetrical.

More detail, in one embodiment of the present disclosure, the second wiring pattern <NUM> at least comprises three parts: a plurality of second input wires <NUM>, a plurality of second output wires <NUM> and a plurality of second bridge wires <NUM>, wherein in some embodiments, each second input wires <NUM>, each second output wires <NUM> and each second bridge wires <NUM> are arranged along a second direction D2, and the second direction D2 is different from the first direction D1 mentioned above. Besides, in the top view, the angle (acute angle) between the vertical direction (i.e. the and the second direction D2 (in counterclockwise direction) is defined as a second angle θ2, wherein in the present disclosure, the second angle θ2 is greater than <NUM> degree and smaller than <NUM> degrees. In some embodiment, the first angle θ1 is the same as the second angle θ2, but not limited thereto.

In one embodiment of the present disclosure, the second input wires <NUM>, the second output wires <NUM> and the second bridge wires <NUM> are separated from each other with interval therebetween. In other words, the plurality of the second input wires <NUM> do not contact to each other directly, the plurality of the second output wires <NUM> do not contact to each other directly, and the plurality of the second bridge wires <NUM> do not contact to each other directly. In addition, in one embodiment of the present disclosure, the number of the second input wires <NUM> is the same as the number of the second output wires <NUM>. For example, in this embodiment, there are five second input wires <NUM> and five second output wires <NUM> shown in <FIG>. Besides, the second bridge wires <NUM> are disposed between the second input wires <NUM> and the second output wires <NUM>.

Besides, in one embodiment of the present disclosure, the second wiring pattern <NUM> further comprises a plurality of second input terminals <NUM> and a plurality of second output terminals <NUM> arranged along a third direction D3 (i.e. the Y-axis). Each second input terminal <NUM> is electrically connected to one second input wire <NUM> respectively (the second input wires <NUM> electrically connects to driving IC through contact pads), and the number of the second input wires <NUM> is the same as the number of the second input terminals <NUM> (for example, there are five second input terminals <NUM> shown in <FIG>). In another embodiment, the number of second input wires <NUM> is different from the number of the second input terminals <NUM>. On the other hand, each second output terminal <NUM> is electrically connected to one second output wire <NUM> respectively (for example, the second output terminal <NUM> electrically connects to functional units in the functional area of the electronic device), and the number of the second output wires <NUM> is the same as the number of the second output terminals <NUM> (for example, there are five second output terminals <NUM> shown in <FIG>). In another embodiment, the number of the second output wires <NUM> is different from the number of the second output terminals <NUM>.

Next, referring to <FIG>, the second wiring pattern <NUM> shown in <FIG> overlaps the first wiring pattern <NUM> shown in <FIG> in the top view. In other words, <FIG> is obtained by overlapping first wiring pattern <NUM> shown in <FIG> and the second wiring pattern <NUM> shown in <FIG>. In order to simplify the illustration, the labels of some components are not shown in <FIG> (for example, the first input wires <NUM>, the first output wires <NUM>, the first bridge wires <NUM>, the second input wires <NUM>, the second output wires <NUM> or the second bridge wires <NUM> are omitted in <FIG>), but since the positions of these components are clearly indicated in <FIG>, the positions of these components in <FIG> can be known by comparing the components' positions in <FIG>.

As shown in <FIG>, the wiring structure <NUM> of the present disclosure at least comprises the first wiring pattern <NUM> and the second wiring pattern <NUM>. Since the first wiring pattern <NUM> is arranged along the first direction D1, and the second wiring pattern <NUM> is arranged along the second direction D2, after the first wiring pattern <NUM> and the second wiring pattern <NUM> are partially overlapped with each other, the plurality of first bridge wires <NUM> cross the plurality of second bridge wires <NUM> and to form a mesh pattern region MPR. In one embodiment, one second bridge wire <NUM> crosses at least one first input wire <NUM>, or at least one first output wire <NUM>. Besides, in one embodiment of the present disclosure, when viewed in a top view, a plurality of contact structures CT are formed on both sides of the mesh pattern region MPR, and the contact structures CT are arranged along a third direction D3 (i.e. the Y-axis). In some embodiment, the contact structures CT electrically connected to the first wiring pattern <NUM> and the second wiring pattern <NUM> along a Z-axis direction. The contact structure CT is via hole with electrical connecting plug. In some embodiment, the contact structures CT is disposed at one terminal of the first input wire <NUM>, one terminal of the first output wire <NUM>, one terminal of the second input wire <NUM>, one terminal of the second output wire <NUM>, both terminals of the first bridge wire <NUM>, or both terminals of the second bridge wire <NUM>. In another embodiment, the contact structure is placed in the middle or any place except terminals of the first bridge wire <NUM> or the second bridge wire Therefore, in this embodiment, as shown in <FIG>, the plurality of first input wires <NUM> are electrically connected to the plurality of first output wires <NUM> through the plurality of second bridge wires <NUM> and the plurality of contact structures CT respectively; and the plurality of second input wires <NUM> are electrically connected to the plurality of second output wires <NUM> through the plurality of first bridge wires <NUM> and the plurality of contact structures CT respectively. In one embodiment of the disclosure, the first input terminals <NUM> are interlaced with the second input terminals <NUM>, and the first output terminals <NUM> are interlaced with the second output terminals <NUM> with intervals therebetween. In another embodiment, the first input terminals <NUM> are interlaced with the second input terminals <NUM> in partially overlapping, and the first output terminals <NUM> are interlaced with the second output terminals <NUM> in partially overlapping.

Besides, in this embodiment, the first wiring pattern <NUM> further comprises a plurality of second intermediate wires <NUM> extending in a fourth direction D4 (i.e. the X-axis direction, wherein the fourth direction D4 is perpendicular to the third direction D3 in some embodiments) respectively, and the first direction D1 is inbetween the third direction D3 and the fourth direction D4. In another embodiment, the fourth direction D4 is not perpendicular to the third direction D3. However, in some embodiment of the present disclosure, the second intermediate wires <NUM> is not arranged along the fourth direction, and they are arranged along another direction. In addition, the plurality of second intermediate wires <NUM> are electrically connected to the plurality contact structures CT. In the present disclosure, the second intermediate wires <NUM> are electrically connected to other elements, such as thin film transistors (TFT), another electronic devices, signals lines (such as data lines, scan lines), driving IC or other suitable circuits. Besides, in one embodiment, the second intermediate wires <NUM> and the second wiring pattern <NUM> are disposed in a same layer by a same production process. In another embodiment, the second intermediate wires <NUM> and the second wiring pattern <NUM> are disposed in different layers by different production processes.

Since the first wiring pattern <NUM> is electrically connected to the second wiring pattern <NUM> through the plurality of contact structures CT, so the signals can be transmitted in the first wiring pattern <NUM> and in the second wiring pattern <NUM> alternately. For example, as shown in <FIG>, signals <NUM>-<NUM> (including signal <NUM>, signal <NUM>, signal <NUM>, signal <NUM>, signal <NUM>, signal <NUM>, signal <NUM>, signal <NUM>, signal <NUM> and signal <NUM>) are labeled beside the first input terminals <NUM>, beside the second input terminals <NUM> or beside the second intermediate wires <NUM>. An element labeled with the signal number, representing the signal passing through the element. Takes the signal <NUM> as an example, the signal <NUM> is transmitted from a first input terminal <NUM>, passing through a first input wire <NUM>, a second bridge wire <NUM> and a first output wire <NUM> in sequence, and reached the first output terminal <NUM>. Besides, the signal <NUM> also electrically connected to two of the second intermediate wires <NUM> through the contact structures CT.

The wiring structure of the present disclosure (including the wiring structures <NUM> and other wiring structures shown in different embodiments of the present disclosure) has at least one advantage of the following advantages mentioned here: First, the wiring structure is structured by two conductive layers (i.e. the first wiring pattern <NUM> and the second wiring pattern <NUM>), so the manufacturing is relatively simple. Second, since the contact structures CT are arranged on both sides of the mesh pattern region MPR along the third direction D3 and do not occupy the area in the mesh pattern region MPR, so the width W of the mesh pattern region MPR is relatively small, and thereby decreasing the total area of the wiring structure and increasing the device density. Third, since each signal path has a similar length, and each wires overlaps the other wires in the top view, the wiring structure has uniform resistance and uniform coupling capacitance. Fourth, since every wire are overlapped with each other alternatively, the noise and the crosstalk of the wiring structure is canceled or reduced, besides, the EMC (electromagnetic compatibility) effect should be better. Fifth, since there are a plurality of spaces in the mesh pattern region MPR between the wires, so when the following processes, such as an UV curing process for sealing is performed, it does not need to make a greater hole patterns in the mesh pattern region MPR. Or sixth, since the wiring structure has a mesh pattern region MPR, every wire can be made shorter. Therefore, the wiring structure is stronger for against twisting force in case of using flexible substrate compared with conventional straight-line wiring patterns.

It should be note that the sizes, the dimensions or the ranges of each element shown in the embodiment are only for illustrated, and the present disclosure is not limited thereto.

In this present disclosure, the wiring structure is electrically connected to other components, such as TFT, display medium or other suitable circuits. In one case, the semiconductor layer of TFT comprises amorphous silicon, polysilicon such as low-temp polysilicon (LTPS) or oxide semiconductor such as indium gallium zinc oxide (IGZO). However, the present disclosure is not limited thereto. In one case, the display medium can be liquid crystals (LC), organic light-emitting diodes (OLED), minimeter-sized light-emitting diodes (mini LED), micrometer-sized light-emitting diodes (micro LED), quantum dot light-emitting diodes (QLED), quantum dots (QD), phosphors, fluorescence or other display elements, and is not limited thereto. A chip size of the LED is about <NUM> to <NUM>, a chip size of the mini-LED is about <NUM> to <NUM>, and a chip size of the micro-LED is about <NUM> to <NUM>, but the present embodiment is not limited thereto.

The following description will detail the different embodiments of the wiring structure of the present disclosure. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.

Referring to <FIG> is a schematic diagram showing a top view of a wiring structure according to a second embodiment of the present disclosure. In this embodiment, a wiring structure <NUM> is provided. The difference between the first embodiment and this embodiment is that in this embodiment, the plurality of second intermediate wires <NUM> are replaced by a plurality of first intermediate wires <NUM>, wherein the first intermediate wires <NUM> and the first wiring pattern <NUM> are disposed in a same layer. In other words, the first intermediate wires <NUM> and the second wiring pattern <NUM> are disposed in different layers. Besides, in this embodiment, the plurality of first intermediate wires <NUM> are electrically connected to the first wiring pattern <NUM> and/or the second wiring pattern <NUM> through the plurality of contact structures CT, and the first intermediate wires <NUM> are arranged along the fourth direction D4 (the X-axis).

Referring to <FIG> is a schematic diagram showing a top view of a wiring structure according to a third embodiment of the present disclosure. In this embodiment, a wiring structure <NUM> is provided. The difference between the first embodiment and this embodiment is that in this embodiment, the intermediate wires comprise the first intermediate wires <NUM> and the second intermediate wires <NUM>. In other words, some of the intermediate wires are the first intermediate wires <NUM> (shown in <FIG>), and others intermediate wires are the second intermediate wires <NUM> (shown in <FIG>). In addition, the first intermediate wires <NUM> and the second intermediate wires <NUM> are arranged alternately. In some embodiments of the present disclosure, the intermediate wires are formed in different layers, and the shapes or the positions of the intermediate wires can be adjusted according to actual requirements. Besides, in this embodiment, the plurality of first intermediate wires <NUM> and the second intermediate wires <NUM> are electrically connected to the first wiring pattern <NUM> and/or the second wiring pattern <NUM> through the plurality of contact structures CT, and the first intermediate wires <NUM> and/or the second intermediate wires <NUM> are arranged along the fourth direction D4 (the X-axis), but not limited thereto.

Referring to <FIG> is a schematic diagram showing a top view of a wiring structure according to a fourth embodiment of the present disclosure. In this embodiment, a wiring structure <NUM> is provided. The difference between the first embodiment and this embodiment is that in this embodiment, a third wiring pattern is further formed above the second wiring pattern <NUM>, there is an insulating layer disposed between the third wiring pattern and the second wiring pattern <NUM>. In some embodiment, the second wiring pattern <NUM> is disposed between the first wiring pattern <NUM> and the third wiring pattern, and the second wiring pattern <NUM> is disposed between the two insulating layers. In this embodiment, the third wiring pattern comprises a plurality of third intermediate wires <NUM>. More detail, the wiring structure <NUM> of this embodiment further comprises a plurality of third intermediate wires <NUM> disposed above the second wiring pattern <NUM>, and a second insulating layer <NUM> is formed between the second wiring pattern <NUM> and the third intermediate wires <NUM> (the third wiring pattern). In other words, in this embodiment, the intermediate wires comprise the first intermediate wires <NUM> and the third intermediate wires <NUM>. In this embodiment, some of the contact structures CT penetrate the second insulating layer <NUM> and are electrically connected to the third intermediate wires <NUM>, therefore, at least one of the third intermediate wires <NUM> is electrically connected to the first wiring pattern <NUM> and/or the second wiring pattern <NUM> through the contact structure CT. In addition, since the third intermediate wires <NUM> and the second wiring pattern <NUM> are disposed in different layers, so the shapes or the positions of the third intermediate wires <NUM> can be adjusted according to actual requirements. In some embodiments, the third intermediate wires <NUM> overlap with the second wiring pattern <NUM>.

Referring to <FIG> is a schematic diagram showing a top view of a wiring structure according to a fifth embodiment of the present disclosure. In this embodiment, a wiring structure <NUM> is provided. In this embodiment, the first bridge wires and the second input wires are omitted, and the number of the first input wires and the first input terminals is adjusted. More detail, the number of the first input wires <NUM> and the first input terminal <NUM> in this embodiment is more than the number of the first input wires <NUM> and the first input terminal <NUM> recited in other embodiments mentioned above. Specifically, there are ten first input wires <NUM> and ten first input terminal <NUM> shown in <FIG>. Besides, the intermediate wires comprise the plurality of second intermediate wires <NUM> and the plurality of third intermediate wires <NUM>. Since the second intermediate wires <NUM> and the plurality of third intermediate wires <NUM> are disposed on different planes, so in some embodiment of the present disclosure, parts of the third intermediate wires <NUM> overlap with the second wiring pattern <NUM> or the second intermediate wires <NUM>.

Referring to <FIG> is a schematic diagram showing a top view of a wiring structure according to a sixth embodiment of the present disclosure. In this embodiment, a wiring structure <NUM> is provided. It should be note that in this embodiment, the plurality of second output terminals <NUM> interlace with and cross the plurality of first output terminals <NUM>, or the plurality of first output terminals <NUM> interlace with and cross the plurality of second output terminals <NUM>. Therefore, the arranging order of the signals at the input terminals is the same as the arranging order of the signals at the output terminals. For example, taking <FIG> as an example, from left to right of the input terminals, the signals of numbers <NUM>-<NUM> are sequentially arranged, and at the output terminals, the signals of numbers <NUM>-<NUM> are also arranged in order from left to right. In this embodiment, the wiring structure <NUM> is electrically connected to another wiring structure along the Y-axis direction, and the output terminals of the wiring structure <NUM> are used as the input terminals of another wiring structure. In other words, a plurality of wiring structures <NUM> are connected to each other repeatedly.

Besides, in some embodiment of the present disclosure, the plurality of second input terminals <NUM> also crosses the plurality of first input terminals <NUM>, or the plurality of first input terminals <NUM> cross the plurality of second input terminals <NUM>, it should also be within the scope of the present disclosure.

Claim 1:
An electronic device (<NUM>), comprising:
a wiring structure (<NUM>), comprising:
a first wiring pattern (<NUM>) comprising a plurality of first input wires (<NUM>) along a first direction (D1), a plurality of first output wires (<NUM>) along the first direction (D1), and a plurality of first bridge wires (<NUM>) along the first direction (D1), wherein the plurality of first bridge wires (<NUM>) are disposed between the plurality of first input wires (<NUM>) and the plurality of first output wires (<NUM>);
a second wiring pattern (<NUM>) comprising a plurality of second input wires (<NUM>) along a second direction (D2) different from the first direction (D1), a plurality of second output wires (<NUM>) along the second direction (D2), and a plurality of second bridge wires (<NUM>) along the second direction (D2), wherein the plurality of second bridge wires (<NUM>) are disposed between the plurality of second input wires (<NUM>) and the plurality of second output wires (<NUM>), one of the plurality of second bridge wires (<NUM>) crosses at least one of the plurality of first input wires (<NUM>) or at least one of the plurality of first output wires (<NUM>) ; and
a first insulating layer (<NUM>) disposed between the first wiring pattern (<NUM>) and the second wiring pattern (<NUM>), wherein the second wiring pattern (<NUM>) is disposed on the first insulating layer (<NUM>), and the first wiring pattern (<NUM>) and the second wiring pattern (<NUM>) are different layers and separated with the first insulating layer (<NUM>) ;
wherein one of the plurality of first input wires (<NUM>) is electrically connected to corresponding one of the plurality of first output wires (<NUM>) through one of the plurality of second bridge wires (<NUM>);
wherein the first wiring pattern (<NUM>) further comprises a plurality of first input terminals (<NUM>) along a third direction (D3) different from the first direction (D1) and the second direction (D2), and the plurality of first input terminals (<NUM>) are electrically connected to the plurality of first input wires (<NUM>) respectively, the second wiring pattern (<NUM>) further comprises a plurality of second input terminals (<NUM>) along the third direction (D3) and electrically connected to the plurality of second input wires (<NUM>) respectively, and the plurality of first input terminals (<NUM>) interlace with the plurality of second input terminals (<NUM>).