Patent Description:
A memory is an important part of a computer architecture, and has a decisive influence on the speed, integration and power consumption of the computer. The basic cell of the traditional memory usually realizes read and write functions through a memory cell (such as a magnetic memory cell) and a drive transistor connected in series. However, the read and write success rate of the memory based on the magnetic memory cell has different electrical requirements for the transistor, resulting in a low read and write success rate of the magnetic memory cell.

According to various embodiments, a semiconductor structure and a method for manufacturing a semiconductor structure are provided.

In the above semiconductor structure, the second channel region of the second transistor has an area different from an area of the first channel region of the first transistor, which can meet different requirements of read and write and improve the success rate of data read and write.

A method for manufacturing a semiconductor structure, including:.

Devices of the prior art are described in <CIT>, <CIT>, <CIT>, <CIT>, <CIT> and <CIT>.

In order to explain technical solutions of the present invention as defined by the claims more clearly, the accompanying drawings to be used for describing the embodiments of the present invention in view of the prior art will be introduced simply. Apparently, the accompanying drawings to be described below are merely some embodiments of the present invention. A person of ordinary skill in the art may obtain other drawings according to these drawings without paying any creative effort.

In order to facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant accompanying drawings. Embodiments of the present invention are shown in the drawings. However, the present invention may be implemented in many different forms, and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention is more thorough and comprehensive.

Unless otherwise defined, all technological and scientific terms used herein have the same meanings as commonly understood by those of ordinary skill in the technical field of the present disclosure. The terms used in the description of the present invention are only for the purpose of describing specific embodiments, but are not intended to limit the present invention as defined by the claims.

It should be understood that, when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" other element or layer, the element or layer may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be an intermediate element or layer therebetween. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" other element or layer, there is no intermediate element or layer therebetween. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or portions, these elements, components, regions, layers, doping types and/or portions should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be expressed as a second element, component, region, layer or portion; for example, the first doping type may be expressed as the second doping type, and similarly, the second doping type may be expressed as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used here to describe the relationship between one element or feature shown in the figure and other element or feature. It should be understood that, in addition to the orientations shown in the figures, the spatial relationship terms also include different orientations of devices in use and operation. For example, if a device in the figure is turned over, an element or feature described as "below" or "under" or "beneath" other element will be oriented "on" the other element or feature. Therefore, the exemplary terms "below" and "under" may include both orientations of above and below. In addition, the device may also include another orientation (for example, <NUM>-degree rotation or other orientation), and the spatial terms used herein are interpreted accordingly.

When used herein, the singular forms of "a", "an" and "the/this" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprise/include" or "have" and the like designate the existence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term "and/or" includes any and all combinations of relevant items listed.

The embodiments of the invention are described here with reference to schematic diagrams of ideal embodiments (and intermediate structures) of the present invention, so that changes in the shape shown due to, for example, manufacturing technology and/or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of regions shown here, but include shape deviations due to, for example, manufacturing technology. For example, an implanted region shown as a rectangle usually has round or curved features and/or implant concentration gradients at its edges, rather than a binary change from the implanted region to a non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in a region between the buried region and a surface through which the implantation proceeds. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of a device, while the invention is defined by the claims.

In one embodiment, referring to <FIG>, a semiconductor structure is provided, including a substrate <NUM>, a first transistor <NUM>, a second transistor <NUM>, and a memory cell <NUM>.

The substrate <NUM> may be, but is not limited to, a semiconductor substrate such as a silicon, gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI substrate. Both the first transistor <NUM> and the second transistor <NUM> are formed in the substrate <NUM>.

The first transistor <NUM> includes a first channel region <NUM> and a first terminal <NUM>. The first channel region <NUM> is located inside the substrate <NUM>, and the first terminal <NUM> is located on a surface of the substrate <NUM>.

It can be understood that the first channel region <NUM> may be a region where a conductive channel is formed when the first transistor <NUM> is turned on.

The first terminal <NUM> may be configured as a source, or the first terminal <NUM> may also be configured as a drain.

The second transistor <NUM> includes a second channel region <NUM> and a second terminal <NUM>. The second channel region <NUM> is located inside the substrate <NUM>, and the second terminal <NUM> is located on the surface of the substrate <NUM>.

Similarly, it can be understood that the second channel region <NUM> may be a region where a conductive channel is formed when the second transistor <NUM> is turned on.

The second terminal <NUM> may be configured as a source, or the second terminal <NUM> may also be configured as a drain.

The first terminal <NUM> of the first transistor <NUM> and the second terminal <NUM> of the second transistor <NUM> are heavily doped sources or drains, both of which can be connected to signal lines to read or write data.

The first transistor <NUM> and the second transistor <NUM> have a common terminal <NUM>, and the common terminal <NUM> is a common source or a common drain of the first transistor <NUM> and the second transistor <NUM>.

One end of the memory cell <NUM> is connected to the common terminal <NUM>, and the other end may be connected to a bit line (BL). Specifically, the memory cell <NUM> may be connected to the common terminal <NUM> and the bit line BL by a conductive plug <NUM>, respectively.

As an example, the memory cell <NUM> may be any one of a capacitive memory cell, a resistive memory cell, a magnetic memory cell, a phase change memory cell, and a ferroelectric memory cell.

The second channel region <NUM> of the second transistor <NUM> has an area different from that of the first channel region <NUM> of the first transistor <NUM>. Specifically, as shown in <FIG>, the first transistor <NUM> and the second transistor <NUM> have a common terminal <NUM>, the common terminal <NUM> may be a common source or a common drain of the first transistor <NUM> and the second transistor <NUM>, a surface region of the substrate <NUM> between the common terminal <NUM> and the first terminal <NUM> is the first channel region <NUM> of the first transistor <NUM>, and a surface region of the substrate <NUM> between the common terminal <NUM> and the second terminal <NUM> is the second channel region <NUM> of the second transistor <NUM>. The area of the first channel region <NUM> may be a surface area of the first channel region <NUM> on the substrate <NUM>; the area of the second channel region <NUM> may be a surface area of the second channel region <NUM> on the substrate <NUM>; as shown in <FIG>, the first channel region <NUM> is U-shaped on the substrate <NUM>, and the area of the first channel region <NUM> may be a sum of a bottom area of the U-shape and a side wall area of the U-shape. Similarly, the second channel region <NUM> is U-shaped on the substrate <NUM>, and the area of the second channel region <NUM> may be a sum of a bottom area of the U-shape and a side wall area of the U-shape.

Therefore, the semiconductor structure in this embodiment can meet different requirements of read and write and improve the success rate of data read and write.

In one embodiment, the first channel region <NUM> has a first width, and the second channel region <NUM> has a second width, wherein the second width is greater than the first width. As shown in <FIG>, the first width of the first channel region <NUM> may be the length of a line where the first channel region <NUM> intersects the first terminal <NUM>, and the second width of the second channel region <NUM> may be the length of a line where the second channel <NUM> intersects the second terminal <NUM>.

For example, when the memory cell <NUM> is a magnetic memory cell, it may include a magnetic tunnel junction (MTJ). As such, the first transistor <NUM> having the first channel region <NUM> with a smaller width may be selected as a data reading transistor, and the second transistor <NUM> having the second channel region <NUM> with a larger width may be selected as a data writing transistor.

Specifically, when data is read from the memory cell <NUM>, the first transistor <NUM> is turned on and the second transistor <NUM> is turned off; when data is written into the memory cell <NUM>, the first transistor <NUM> is turned off and the second transistor <NUM> is turned on. By configuring the second width to be greater than the first width, the driving current of the second transistor <NUM> is greater than that of the first transistor <NUM>, thereby meeting the requirement of different driving currents of the first transistor <NUM> and the second transistor <NUM>. As such, the misread rate and the miswrite rate of data can be reduced at the same time, thereby increasing the success rate of data read and write.

Further, the semiconductor structure may further include a bottom electrode BE and a top electrode TE, and the bottom electrode BE and the top electrode TE are respectively located at the bottom and top of the magnetic tunnel junction (MTJ).

In one embodiment, the second width is <NUM> to <NUM> times the first width. As such, the driving current of the second transistor can be effectively increased, and the problem of excessive width, which leads to excessive area occupation and lower storage density, can be avoided.

In one embodiment, referring to <FIG>, the substrate <NUM> further includes at least one active region <NUM>. The active region <NUM> is formed in the substrate <NUM>. The first transistor <NUM> and the second transistor <NUM> are formed in the active region <NUM>. One active region <NUM> corresponds to one memory cell.

As an example, specifically, referring to <FIG> at the same time, ions may be implanted into the substrate <NUM> to form a well region of a first conductive type. The first conductive type may be P-type or N-type. When the first conductive type is P-type, the first terminal <NUM> of the first transistor <NUM>, the second terminal <NUM> of the second transistor <NUM>, and the common terminal <NUM> of the first transistor <NUM> and the second transistor <NUM> are N-type. When the first conductive type is N-type, the first terminal <NUM> of the first transistor <NUM>, the second terminal <NUM> of the second transistor <NUM>, and the common terminal <NUM> of the first transistor <NUM> and the second transistor <NUM> are P-type.

Shallow trench isolation (STI) structures may be further formed on the substrate <NUM>, and a plurality of active regions <NUM> are isolated in the substrate <NUM> through the shallow trench isolation structures. The first transistor <NUM> and the second transistor <NUM> are formed in the active region <NUM>.

In this embodiment, the first transistor <NUM> and the second transistor <NUM> are distributed on two opposite sides of the extension direction of the active region <NUM>. In addition, the first transistor <NUM> and the second transistor <NUM> located in the active region <NUM> have a common terminal <NUM>.

The common terminal <NUM> may be connected to the memory cell, and may be a source or a drain.

In this embodiment, the first transistor <NUM> and the second transistor <NUM> share the common terminal <NUM>, which can effectively control read and write operations of the memory cell, thereby improving the success rate of data read and write.

In one embodiment, referring to <FIG>, the semiconductor structure further includes a plurality of word lines WL extending in a first direction. The word lines WL are used to provide gate voltage signals for the first transistor <NUM> and the second transistor <NUM>.

The portion of the word line WL corresponding to the active region <NUM> may serve as a first gate <NUM> of the first transistor <NUM> and/or a second gate <NUM> of the second transistor <NUM>. Specifically, as shown in <FIG> and <FIG>, the word lines WL may be buried word lines, and the two word lines WL pass through the same active region <NUM>; the portion of the word line WL that overlaps the active region <NUM> may serve as the first gate <NUM> of the first transistor <NUM> and/or the second gate <NUM> of the second transistor <NUM>. The bottom and side walls of the first gate <NUM> are opposite to the first channel region <NUM> of the first transistor <NUM>, and the bottom and side walls of the second gate <NUM> are opposite to the second channel region <NUM> of the second transistor <NUM>.

In this embodiment, a plurality of active regions <NUM> is staggered. In addition, each active region <NUM> extends in a second direction, and the second direction is inclined at a preset angle with respect to the first direction. The preset angle may be between <NUM>° and <NUM>°.

Within the limited substrate space, more active regions can be arranged, thereby increasing the density of memory cells.

Further, in the second direction, the first transistors <NUM> and the second transistors <NUM> located in the adjacent active regions <NUM> are disposed opposite to each other.

The active regions <NUM> are arranged in a staggered array. The arrangement of the active regions <NUM> is more regular, so that the performance of the memory formed is more uniform and stable everywhere, and the layout design is convenient.

Furthermore, in the first direction, the first transistors <NUM> and the second transistors <NUM> located in the adjacent active regions <NUM> correspond to the same word line WL.

As such, the density of the active regions <NUM> in the substrate <NUM> can be further increased, thereby increasing the density of memory cells.

In one embodiment, referring to <FIG>, every two active regions <NUM> among the plurality of active regions <NUM> constitute an active region pair. And, the active region pairs are arranged in an array. Meanwhile, the first transistors <NUM> of two active regions <NUM> in each active region pair are adjacent and opposite to each other.

In the central part of each active region pair, two first transistors <NUM> can be arranged side by side, which can effectively save substrate space. Therefore, in the limited substrate space, more active regions can be arranged, thereby increasing the density of memory cells.

Further, the semiconductor structure may include a plurality of word lines WL extending in the first direction. Meanwhile, the word lines WL may include first word lines WL1 and second word lines WL2 alternately arranged in the second direction.

The first word line WL1 penetrates the first transistors <NUM> of the active regions in the active region pairs of the same column, and the second word line WL2 penetrates the second transistors <NUM> of the active regions in the active region pairs of the same column.

In addition, the two first transistors <NUM> in the same active region pair are penetrated by the same first word line WL1. As such, the density of the active regions <NUM> in the substrate <NUM> can be further increased, thereby increasing the density of memory cells.

Furthermore, the extension direction of the active regions <NUM> is the second direction. At this time, the first direction may be perpendicular to the second direction, which facilitates the layout design of the word lines WL.

In one embodiment, referring to <FIG>, a method for manufacturing a semiconductor structure is provided, including:.

The substrate <NUM> may be, but is not limited to, a semiconductor substrate such as a silicon, gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI substrate.

The first channel region <NUM> may be a region where a conductive channel is formed when the first transistor <NUM> is turned on. The first terminal <NUM> may be a drain or a source.

The second terminal <NUM> may be configured as a source or a drain.

The memory cell <NUM> is a device unit capable of implementing a storage function. As an example, the memory cell <NUM> may be any one of a capacitive memory cell, a resistive memory cell, a magnetic memory cell, a phase change memory cell, and a ferroelectric memory cell.

The second channel region <NUM> of the second transistor <NUM> has an area different from that of the first channel region <NUM> of the first transistor <NUM>.

Specifically, as shown in <FIG>, the first transistor <NUM> and the second transistor <NUM> have a common terminal <NUM>, the common terminal <NUM> may be a common source or a common drain of the first transistor <NUM> and the second transistor <NUM>, a surface region of the substrate <NUM> between the common terminal <NUM> and the first terminal <NUM> is the first channel region <NUM> of the first transistor <NUM>, and a surface region of the substrate <NUM> between the common terminal <NUM> and the second terminal <NUM> is the second channel region <NUM> of the second transistor <NUM>.

The area of the first channel region <NUM> may be a surface area of the first channel region <NUM> on the substrate <NUM>; the area of the second channel region <NUM> may be a surface area of the second channel region <NUM> on the substrate <NUM>; as shown in <FIG>, the first channel region <NUM> is U-shaped on the substrate <NUM>, and the area of the first channel region <NUM> may be a sum of a bottom area of the U-shape and a side wall area of the U-shape. Similarly, the second channel region <NUM> is U-shaped on the substrate <NUM>, and the area of the second channel region <NUM> may be a sum of a bottom area of the U-shape and a side wall area of the U-shape.

Therefore, the semiconductor structure formed by the method of this embodiment can meet different requirements of read and write and improve the success rate of data read and write.

In one embodiment, the first channel region <NUM> has a first width, and the second channel region <NUM> has a second width, wherein the second width is greater than the first width.

As shown in <FIG>, the first width of the first channel region <NUM> may be the length of a line where the first channel region <NUM> intersects the first terminal <NUM>, and the second width of the second channel region <NUM> may be the length of a line where the second channel region <NUM> intersects the second terminal <NUM>.

In one embodiment, referring to <FIG> and <FIG>, step S2 specifically includes:.

The first gate <NUM> is a gate of the first transistor <NUM>, and the second gate <NUM> is a gate of the second transistor <NUM>. The bottom and side walls of the first gate <NUM> are opposite to the first channel region <NUM>. The bottom and side walls of the second gate <NUM> are opposite to the second channel region <NUM>.

That is, the first transistor <NUM> includes the first gate <NUM>, the first channel region <NUM>, the first terminal <NUM>, and the common terminal <NUM>. The first terminal <NUM> and the common terminal <NUM> are respectively a drain and a source of the first transistor <NUM>. It can be understood that there may also be a first gate dielectric layer <NUM> (such as an oxide layer) between the first gate <NUM> and the first channel region <NUM>.

The second transistor <NUM> includes the second gate <NUM>, the second channel region <NUM>, the second terminal <NUM> and the common terminal <NUM>. The second terminal <NUM> and the common terminal <NUM> are respectively a drain and a source of the second transistor <NUM>. It can be understood that there is a second gate dielectric layer <NUM> (such as an oxide layer) between the second gate <NUM> and the second channel region <NUM>.

The first transistor <NUM> and the second transistor <NUM> share the common terminal <NUM>, which can effectively improve space utilization, thereby reducing device size. The common terminal <NUM> may be a common source or a common drain of the first transistor <NUM> and the second transistor <NUM>.

In this embodiment, the gate (first gate) of the first transistor <NUM> and the gate (second gate) of the second transistor <NUM> are both buried gate structures.

Of course, the present application is not limited to this. The gates of the first transistor <NUM> and the second transistor <NUM> may also be in other forms (for example, planar gates).

In one embodiment, referring to <FIG>, the method for manufacturing a semiconductor structure further includes: forming a plurality of word lines WL extending in a first direction in the substrate <NUM>.

As an example, the word line WL may be formed in the first gate trench 110a and the second gate trench 110b. The portion of the word line WL corresponding to the active region <NUM> may serve as the first gate <NUM> of the first transistor <NUM> and/or the second gate <NUM> of the second transistor <NUM>.

A plurality of active regions <NUM> are staggered, the active regions <NUM> extend in a second direction, and the second direction is inclined at a preset angle with respect to the first direction.

In one embodiment, in the second direction, the first transistors and the second transistors located in the adjacent active regions are disposed opposite to each other; and in the first direction, the first transistors and the second transistors located in the adjacent active regions correspond to the same word line.

In one embodiment, referring to <FIG>, every two active regions <NUM> among the plurality of active regions <NUM> constitute an active region pair, the active region pairs are arranged in an array, and the active regions extend in the second direction; the first transistors <NUM> of the two active regions <NUM> in each active region pair are adjacent and opposite to each other.

In one embodiment, the method for manufacturing a semiconductor structure further includes forming a plurality of word lines WL extending in the first direction in the substrate. The word lines WL include first word lines WL1 and second word lines WL2 alternately arranged in the second direction. The first word line WL1 penetrates the first transistors <NUM> of the active regions in the active region pairs of the same column, the second word line penetrates the second transistors <NUM> of the active regions in the active region pairs of the same column, and the two first transistors <NUM> in the same active region pair are penetrated by the same first word line WL1.

In one embodiment, the active regions extend in the second direction, and the first direction is perpendicular to the second direction.

For the specific limitations on the method for manufacturing a semiconductor structure, reference may be made to the above limitations on the semiconductor structure, and details are not described herein again.

In the description of this specification, the description with reference to the term "one embodiment" or the like means that the specific feature, structure, material or feature described in conjunction with the embodiment or example is included in at least one embodiment of the present invention or relating to an example. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

Claim 1:
A semiconductor structure, characterized by comprising:
a substrate (<NUM>);
a first transistor (<NUM>), comprising a first channel region (<NUM>) located in the substrate (<NUM>);
a second transistor (<NUM>), comprising a second channel region (<NUM>) located in the substrate (<NUM>), and the first transistor (<NUM>) and the second transistor (<NUM>) having a common source (<NUM>) or a common drain (<NUM>); and
a memory cell (<NUM>), connected to the common source (<NUM>) or the common drain (<NUM>)
characterised by
the second channel region (<NUM>) having an area different from an area of the first channel region (<NUM>).