Patent Description:
In recent years, an amplifier (also referred to as a full digital amplifier), which does not convert a digital audio signal into an analog signal, but directly generates a switching signal by digital modulation and amplifies the digital signal as is, has been developed. However, in a full digital amplifier, since the driver circuit switches directly to the power supply circuit, the waveform of the power supply noise appears at the amplifier output due to the mixing of the power supply noise. In addition, when a large current flows due to the wire resistance of the wiring from the power supply circuit and the like, the voltage drops and harmonic distortion occurs. Furthermore, as the switching transistor, a metal oxide semiconductor field effect transistor (MOSFET) or the like capable of high-speed response is used. However, since switching is performed at several hundred kHz or higher, waveform fluctuations such as rise delay, overshoot, or ringing occur at the rising portion of the switching waveform due to the parasitic capacitance of the MOSFET and the inductance component on the board pattern, and harmonic distortion and noise increase.

Therefore, a technology to reduce the distortion component by extracting the input/output difference, that is, the components such as distortion and noise (hereinafter, also referred to as the distortion component) using the feedback technology and returning them to the input in the opposite phase has been developed (for example, Patent Literature (PTL) <NUM> and <NUM>).

PTL <NUM> discloses a signal processing device in which distortion and noise in high power digital PWM amplifiers is reduced by measuring the difference between the desired output signal and the actual output signal on a pulse by pulse basis. This analog error is converted into a digital signal with an analog to digital converter (ADC). The digital error signal is then used to correct the feedback of the delta sigma modulator in real time.

In order to accurately extract the input/output difference using the feedback technology, it is necessary to subtract the signal that is to be fed back and the input signal on the same scale, that is, the amplitude, DC offset and the like of the signal that is to be fed back need to be adjusted. For example, as a method of making the adjustment, a method of using a variable resistor can be considered. However, when a variable resistor is used, the resistance value shifts due to aged deterioration of the variable resistor, and the resistance value also shifts due to an impact such as vibration. Furthermore, when the variable resistor is manually adjusted, the adjustment varies depending on the person making the adjustment. In this way, in the method using a variable resistor, it is difficult to accurately adjust the amplitude and DC offset of the signal that is to be fed back, that is, it is difficult to accurately extract the distortion component.

Therefore, the present disclosure provides a signal processing device or the like capable of more accurately extracting distortion components using feedback technology.

The signal processing device in the present disclosure is defined by the independent claim <NUM>. A corresponding method for adjusting parameters for the signal processing device is defined by the independent claim <NUM>.

According to the signal processing device and the like in the present disclosure, the distortion component can be extracted more accurately by using the feedback technology.

Hereinafter, an embodiment will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed description of already well-known matters and duplicate description for substantially the same configuration may be omitted. This is to avoid unnecessary redundancy of the following description and to facilitate the understanding of those skilled in the art.

It should be noted that the inventor provides the accompanying drawings and the following description in order for those skilled in the art to fully understand the present disclosure, and these are not intended to limit the subject matter described in the claims.

Hereinafter, an embodiment will be described with reference to <FIG>.

<FIG> is a configuration diagram showing an example of signal processing device <NUM> according to the embodiment. In addition to signal processing device <NUM>, <FIG> shows no-signal generator <NUM>, test signal generator <NUM>, and speaker <NUM>. No-signal generator <NUM>, test signal generator <NUM>, and speaker <NUM> may be provided in signal processing device <NUM>.

Signal processing device <NUM> is a device that inputs a digital audio signal obtained from a music source, processes the digital audio signal, and outputs an analog signal to speaker <NUM> in order to reproduce the music source stored in a storage medium such as a compact disc (CD), a digital versatile disc (DVD), a Blu-ray (registered trademark) disc (BD), a hard disc drive (HDD) or the like.

In addition, signal processing device <NUM> has a function of feeding back the signal output to speaker <NUM> to reduce the distortion component generated in power amplifier circuit <NUM> or the like described later. It should be noted that in signal processing device <NUM>, the parameters of the circuit configuration related to the feedback can be adjusted without using the variable resistor by the processing by controller <NUM> or the like described later.

Signal processing device <NUM> includes subtractor <NUM>, signal processing circuit <NUM>, power amplifier circuit <NUM>, A/D converter <NUM>, analog LPF <NUM>, offset adjuster <NUM>, amplitude adjuster <NUM>, delay adjuster <NUM>, and reference signal generator <NUM>, subtractor <NUM>, compensation filter <NUM>, decimation filter <NUM>, switch <NUM>, selector <NUM> and controller <NUM>.

Subtractor <NUM> is a circuit that subtracts a feedback signal from an input signal that is a digital audio signal and outputs a first digital signal. The feedback signal is a signal generated by feeding back an analog signal output from power amplifier circuit <NUM> and performing various signal processing. For example, the feedback signal is a signal that is obtained by processing an analog signal by analog LPF <NUM>, A/D converter <NUM>, offset adjuster <NUM>, amplitude adjuster <NUM>, subtractor <NUM>, compensation filter <NUM> and decimation filter <NUM>, and is output from decimation filter <NUM>. The feedback signal includes a distortion component generated by power amplifier circuit <NUM> or the like, and the distortion component generated by power amplifier circuit <NUM> or the like can be canceled by subtracting the distortion component in advance in subtractor <NUM>.

Signal processing circuit <NUM> is a circuit that performs signal processing on the first digital signal and outputs the second digital signal. Signal processing circuit <NUM> includes ΔΣ modulator <NUM> and pulse width modulation (PWM) modulator <NUM>.

ΔΣ modulator <NUM> requantizes the number of gradations of the pulse width of PWM modulator <NUM> which is smaller than the input audio signal. Due to the feature of the noise shaping of the ΔΣ-modulation that pushes the re-quantization noise out of the audible band of, for example, <NUM> or more, the re-quantization noise generated at the time of re-quantization is reduced in the audible band.

PWM modulator <NUM> converts a signal output by ΔΣ modulator <NUM> to a second digital signal (pulse width modulated signal) having the gradation of the pulse width represented by two values of <NUM> and <NUM> or <NUM> and -<NUM> for the gradation of the amplitude level of the signal.

The second digital signal contains a distortion component when it is amplified by power amplifier circuit <NUM> and converted into an analog signal. In order to reduce this distortion component, the difference between the signals before and after the distortion component is superimposed is extracted. As shown in <FIG>, the second digital signal before the distortion component is superimposed is input to subtractor <NUM>.

Power amplifier circuit <NUM> is a circuit that amplifies the signal amplitude of the second digital signal, converts the amplified second digital signal into an analog signal, and outputs the analog signal. Power amplifier circuit <NUM> includes driver circuit <NUM>, switching transistors <NUM> and <NUM>, and low pass filter (LPF) <NUM>. It should be noted that power amplifier circuit <NUM> is a circuit that also includes a D/A conversion function because it converts a digital signal into an analog signal and outputs the analog signal.

Driver circuit <NUM> and switching transistors <NUM> and <NUM> are circuits that amplify the second digital signal. Switching transistors <NUM> and <NUM> are included in a push-pull circuit. Switching transistors <NUM> and <NUM> are, for example, n-type MOSFETs, respectively. It should be noted that switching transistors <NUM> and <NUM> may be a combination of an n-type MOSFET and a p-type MOSFET.

LPF <NUM> is a filter that demodulates the amplified signal into an analog signal (analog audio signal), and it filters the components higher than a predetermined cutoff frequency such as re-quantization noise of the ΔΣ modulator and a carrier signal superimposed by PWM modulation out of the amplified signal and outputs the filtered signal. LPF <NUM> includes an inductor and a capacitor in order to reduce power loss.

In power amplifier circuit <NUM>, when the signal is amplified, power supply noise, distortion due to wiring resistance, distortion due to fluctuation of the switching waveform, and the like occur, so that the analog signal output from power amplifier circuit <NUM> includes a distortion component. In order to reduce such a distortion component, the analog signal output from power amplifier circuit <NUM> is fed back. The analog signal on which the distortion component to be fed back is superimposed is converted into a third digital signal by A/D converter <NUM> described later, and the difference (that is, the distortion component) between the third digital signal and the second digital signal before the distortion component is superimposed is extracted by subtractor <NUM>.

Analog LPF <NUM> is a filter for performing antialiasing processing at the time of A/D conversion. Analog LPF <NUM> removes aliasing noise, which is a frequency component exceeding half of the sampling frequency of A/D converter <NUM>, in advance.

A/D converter <NUM> is a circuit that converts an analog signal into a third digital signal and outputs the third digital signal. In order to extract the difference (that is, the distortion component) between the second digital signal and the analog signal output from power amplifier circuit <NUM>, A/D converter <NUM> converts the analog signal into a digital signal having the same signal format as the second digital signal.

Offset adjuster <NUM> is a circuit that adjusts the DC offset for the third digital signal. Specifically, offset adjuster <NUM> adjusts the DC offset using a first parameter regarding the DC offset determined based on the output of offset adjuster <NUM> which is output when no signal is input to signal processing circuit <NUM> by subtractor <NUM>. The first parameter will be described later. Since A/D converter <NUM> causes a DC offset error at the time of A/D conversion, a digital signal deviated by the DC offset from the input analog signal is output. When a digital signal having an error with respect to the input analog signal is output, the distortion component is extracted based on the digital signal having the error, so that it becomes difficult to accurately extract the distortion component. For this reason, offset adjuster <NUM> adjusts the DC offset for the third digital signal.

Amplitude adjuster <NUM> is a circuit that adjusts the amplitude for the third digital signal. Specifically, amplitude adjuster <NUM> adjusts the amplitude using a second parameter regarding the amplitude determined based on (i) an output of amplitude adjuster <NUM> which is output when the input signal and the feedback signal are not input to subtractor <NUM> and a first test signal is input to signal processing circuit <NUM> and (ii) the first test signal. The second parameter will be described later. In power amplifier circuit <NUM>, the second digital signal is amplified, the amplified second digital signal is converted into an analog signal, and the analog signal is converted into a third digital signal by A/D converter <NUM>. That is, the scale of the third digital signal is different from that of the second digital signal by the amount amplified by power amplifier circuit <NUM>, and it is necessary to match the scale at the time of extracting the difference. For this reason, amplitude adjuster <NUM> adjusts the amplitude for the third digital signal. It should be noted that amplitude adjuster <NUM> adjusts the amplitude for the third digital signal having DC offset adjusted by offset adjuster <NUM>.

Delay adjuster <NUM> is a circuit that adjusts the delay of the second digital signal. Specifically, delay adjuster <NUM> adjusts the delay using a third parameter regarding the delay determined based on a difference signal when the input signal and the feedback signal are not input to subtractor <NUM> and the second test signal is input to signal processing circuit <NUM>. The third parameter and the difference signal will be described later. In A/D converter <NUM>, a delay occurs at the time of A/D conversion, so that a phase shift between the second digital signal and the third digital signal occurs. For this reason, delay adjuster <NUM> delays the second digital signal in order to reduce the phase shift and perform the subtraction of the second digital signal and the third digital signal at the same timing.

It should be noted that signal processing device <NUM> includes offset adjuster <NUM>, amplitude adjuster <NUM>, and delay adjuster <NUM>, but these components may not necessarily be used. That is, depending on the situation, the DC offset may not be adjusted, the amplitude may not be adjusted, or the delay may not be adjusted.

Reference signal generator <NUM> is a circuit that converts the second digital signal into a signal that matches the sampling frequency and the number of bits of the third digital signal, and includes an LPF and a decimation circuit. The second digital signal output from signal processing circuit <NUM> is, for example, a <NUM>-bit, <NUM> signal. On the other hand, the third digital signal output from A/D converter <NUM> is, for example, a <NUM>-bit, <NUM> signal. Reference signal generator <NUM> converts the second digital signal into a reference signal having the same multi-bit configuration and the same frequency as the third digital signal by filtering the re-quantization noise of the ΔΣ modulator and the carrier signal superimposed by the PWM modulation, and converting to the same frequency as the third digital signal by the decimation circuit. This makes it possible to subtract the second digital signal (reference signal) and the third digital signal.

Subtractor <NUM>, compensation filter <NUM> and decimation filter <NUM> are components of a calculator that extracts a difference signal which is a difference between the third digital signal having the DC offset adjusted by the offset adjuster and the amplitude adjusted by the amplitude adjuster and the second digital signal having the delay adjusted by the delay adjuster, and outputs the feedback signal based on the difference signal.

Subtractor <NUM> is a circuit that subtracts the second digital signal (reference signal) having the delay adjusted by delay adjuster <NUM> from the third digital signal having the DC offset adjusted by offset adjuster <NUM> and the amplitude adjusted by amplitude adjuster <NUM>, and outputs a difference signal, which is the difference therebetween.

Compensation filter <NUM> is a filter that extracts and outputs a frequency component corresponding to a distortion component included in the difference signal. Compensation filter <NUM> is connected to, for example, the selection terminal of selector <NUM>.

Decimation filter <NUM> is a filter that downsamples the signal output from compensation filter <NUM>. Since the input signal is, for example, <NUM> and the third digital signal is, for example, <NUM> as described above, decimation filter <NUM> converts into a feedback signal having the same frequency of <NUM> as the input signal by downsampling the output of compensation filter <NUM> of <NUM>, and outputs the feedback signal to subtractor <NUM>.

Switch <NUM> is a switch provided between power amplifier circuit <NUM> and speaker <NUM> that converts an analog signal output from power amplifier circuit <NUM> to sound. Switch <NUM> is, for example, a relay or a semiconductor switch. By putting switch <NUM> into the non-conductive state, it is possible to prevent the sound from being output from speaker <NUM>.

Selector <NUM> is a switch for switching a signal output to subtractor <NUM> (in other words, a signal input from subtractor <NUM> to signal processing circuit <NUM>). Selector <NUM> is, for example, a semiconductor switch. Selector <NUM> includes a common terminal connected to decimation filter <NUM>, a selection terminal connected to compensation filter <NUM>, a selection terminal connected to no-signal generator <NUM>, and a selection terminal connected to test signal generator <NUM>. Selector <NUM> switches the connection between subtractor <NUM> (decimation filter <NUM>) and any of compensation filter <NUM>, no-signal generator <NUM>, and test signal generator <NUM>.

Controller <NUM> is a processing unit for determining parameters (a first parameter, a second parameter, and a third parameter) of a circuit related to feedback in signal processing device <NUM>. Controller <NUM> includes first parameter determiner <NUM>, second parameter determiner <NUM>, and third parameter determiner <NUM> as functional components. Controller <NUM> includes, for example, a processor (microcomputer or the like), a memory, and the like, and first parameter determiner <NUM>, second parameter determiner <NUM>, and third parameter determiner <NUM> are realized by the processor executing a program stored in the memory.

First parameter determiner <NUM> determines the first parameter regarding the DC offset. Specifically, first parameter determiner <NUM> determines the offset amount in offset adjuster <NUM> as the first parameter.

Second parameter determiner <NUM> determines the second parameter regarding the amplitude. Specifically, second parameter determiner <NUM> determines the gain of amplitude adjuster <NUM> as the second parameter.

Third parameter determiner <NUM> determines the third parameter regarding the delay. Specifically, third parameter determiner <NUM> determines the delay amount in delay adjuster <NUM> as the third parameter.

In addition, controller <NUM> controls the conductive state and the non-conductive state of switch <NUM>.

In addition, controller <NUM> controls the connection state of selector <NUM>.

No-signal generator <NUM> is a circuit that generates a digital signal (referred to as no-signal) indicating <NUM>. No-signal generator <NUM> is connected to the selection terminal of selector <NUM>. It should be noted that as long as a no-signal can be input to signal processing circuit <NUM> in response to an instruction from controller <NUM>, the connection form of no-signal generator <NUM> is not limited thereto.

Test signal generator <NUM> is a circuit that generates a test signal such as a sine wave of an arbitrary frequency or the like. Test signal generator <NUM> generates, for example, a first test signal and a second test signal having different frequencies from each other in response to an instruction from controller <NUM>. Test signal generator <NUM> is connected to the selection terminal of selector <NUM>. It should be noted that if the test signal can be input to signal processing circuit <NUM> in response to the instruction from controller <NUM>, the connection form of test signal generator <NUM> is not limited thereto.

Speaker <NUM> converts the power of the analog signal output from power amplifier circuit <NUM> to sound energy.

Next, the operation at the time of determining the parameters (first parameter, second parameter, and third parameter) of signal processing device <NUM> will be described with reference to <FIG>.

<FIG> is a flowchart showing an example of an operation at the time of determining the parameters of signal processing device <NUM> according to the embodiment.

Controller <NUM> determines the first parameter regarding the DC offset based on the output of offset adjuster <NUM> which is output when no signal is input to signal processing circuit <NUM> by subtractor <NUM> (step S101). Details of step S101 will be described with reference to <FIG> and <FIG> described later.

Controller <NUM> determines the second parameter regarding the amplitude based on (i) an output of amplitude adjuster <NUM> which is output when the input signal and the feedback signal are not input to subtractor <NUM> and a first test signal is input to signal processing circuit <NUM> and (ii) the first test signal (step S102). Details of step S102 will be described with reference to <FIG> and <FIG> described later.

Controller <NUM> determines a third parameter regarding the delay determined based on the difference signal in a calculator (subtractor <NUM>) when the input signal and the feedback signal are not input to subtractor <NUM> and a second test signal is input to signal processing circuit <NUM> (step S103). Details of step S103 will be described with reference to <FIG>, <FIG> and <FIG> described later.

As shown in <FIG>, controller <NUM> determines each parameter in order of, for example, the first parameter, the second parameter, and the third parameter.

For example, controller <NUM> performs a process for determining each parameter when the power of the voice reproduction device equipped with signal processing device <NUM> is turned on. In addition, for example, controller <NUM> may perform the process for determining each parameter at a specific timing even after the power is turned on. This is because the circuits included in the audio reproduction device often have temperature characteristics, and the temperature rises after the power is turned on, so some cases are that the signal that is to be fed back cannot be adjusted correctly with the parameters determined when the power is turned on. For example, the process of determining each parameter may be performed at a timing such as when the CD or DVD is switched after the power is turned on.

The operation at the time of determining the first parameter regarding the DC offset will be described with reference to <FIG> and <FIG>.

<FIG> is a diagram for illustrating a signal flow at the time of determining the first parameter of signal processing device <NUM> according to the embodiment. In <FIG>, the signal flow is indicated by a thick dashed arrow.

<FIG> is a flowchart showing an example of the operation at the time of determining the first parameter of signal processing device <NUM> according to the embodiment. <FIG> is a flowchart showing the details of step S101 of <FIG>.

Controller <NUM> controls switch <NUM> so that it is in a non-conductive state (step S201). By making switch <NUM> in a non-conductive state, it is possible to prevent sound from being output from speaker <NUM> when determining the first parameter. It should be noted that since no signal is input to signal processing circuit <NUM> (in other words, a no-signal is input) at the time of determining the first parameter, switch <NUM> may remain in the conductive state.

Controller <NUM> changes the connection destination of selector <NUM> to no-signal generator <NUM> (step S202). In addition, it is assumed that the input signal is not input to subtractor <NUM> at the time of determining the first parameter. As shown in <FIG>, this creates a state in which no signal is input to signal processing circuit <NUM> by subtractor <NUM> (a state that a no-signal is input to signal processing circuit <NUM>). As shown in <FIG>, controller <NUM> (first parameter determiner <NUM>) determines the first parameter based on the output of offset adjuster <NUM> which is output when no signal is input to signal processing circuit <NUM> by subtractor <NUM>.

Specifically, controller <NUM> first calculates the average value of the output of offset adjuster <NUM> at a predetermined time (the predetermined time is not particularly limited) (step S203). When no signal is input to signal processing circuit <NUM>, the output of A/D converter <NUM> is ideally <NUM>, but in fact, the output corresponds to the DC offset error of A/D converter <NUM>. By preventing the signal from being input to signal processing circuit <NUM>, the DC offset error of A/D converter <NUM> can be confirmed as the output of A/D converter <NUM>. The first parameter is, for example, the offset amount of offset adjuster <NUM>. In the initial state, the offset amount is, for example, <NUM>, so the output of A/D converter <NUM> at this time becomes the output of offset adjuster <NUM> almost as it is. Since the output of A/D converter <NUM> may fluctuate depending on the time, the average value of the output of offset adjuster <NUM> in a predetermined time period is calculated.

Next, controller <NUM> determines whether the absolute value of the calculated average value is equal to or smaller than the first threshold (for example, A (positive number)) (step S204). That is, controller <NUM> determines whether the average value of the output of offset adjuster <NUM> is equal to or greater than -A and equal to or smaller than +A.

When the absolute value of the calculated average value is not equal to or smaller than A (No in step S204), controller <NUM> determines whether the average value is greater than <NUM> (step S205).

When the calculated average value is greater than <NUM> (Yes in step S205), controller <NUM> decreases the offset amount (step S206). That is, since the output of offset adjuster <NUM> has a value greater than A due to the DC offset error of A/D converter <NUM>, the offset amount in offset adjuster <NUM> is adjusted so that the output of offset adjuster <NUM> approaches <NUM> by decreasing the offset amount of offset adjuster <NUM>.

When the calculated average value is smaller than <NUM> (No in step S205), controller <NUM> increases the offset amount (first parameter) (step S207). That is, since the output of offset adjuster <NUM> is smaller than -A due to the DC offset error of A/D converter <NUM>, the offset amount in offset adjuster <NUM> is adjusted so that the output of offset adjuster <NUM> approaches <NUM> by increasing the offset amount of offset adjuster <NUM>.

Then, the processes from step S203 are performed again. That is, it is repeated until the absolute value of the average value of the output of offset adjuster <NUM> becomes equal to or smaller than A that after adjusting the offset amount in offset adjuster <NUM>, the output of offset adjuster <NUM> which is output when no signal is input to signal processing circuit <NUM> is confirmed, and according to the output, the offset amount in offset adjuster <NUM> is adjusted again.

When the absolute value of the calculated average value is equal to or smaller than A (Yes in step S204), controller <NUM> determines the current offset amount in offset adjuster <NUM> as the first parameter.

Then, controller <NUM> changes the connection destination of selector <NUM> to compensation filter <NUM> (step S208), and controls switch <NUM> so that it is in a conductive state (step S209). With this, offset adjuster <NUM> adjusts the DC offset for the third digital signal using the first parameter (offset amount) regarding the DC offset determined based on the output of offset adjuster <NUM> which is output when no signal is input to signal processing circuit <NUM> by subtractor <NUM>.

The operation at the time of determining the second parameter regarding the amplitude will be described with reference to <FIG> and <FIG>.

<FIG> is a diagram for illustrating a signal flow at the time of determining the second parameter of signal processing device <NUM> according to the embodiment. In <FIG>, the signal flow is indicated by a thick dashed arrow.

<FIG> is a flowchart showing an example of the operation at the time of determining the second parameter of signal processing device <NUM> according to the embodiment. <FIG> is a flowchart showing the details of step S102 of <FIG>.

Controller <NUM> controls switch <NUM> so that it is in a non-conductive state (step S301). By making switch <NUM> in a non-conductive state, it is possible to prevent sound from being output from speaker <NUM> at the time of determining the second parameter. Since the first test signal is input to signal processing circuit <NUM> at the time of determining the second parameter, switch <NUM> is put into a non-conductive state so that the sound corresponding to the first test signal is not output from speaker <NUM>.

Controller <NUM> changes the connection destination of selector <NUM> to test signal generator <NUM>, and causes test signal generator <NUM> to output a first test signal (for example, a sine wave) having a predetermined frequency (step S302). In addition, it is assumed that no input signal is input to subtractor <NUM> at the time of determining the second parameter. With this, as shown in <FIG>, it becomes in such a state that the input signal and the feedback signal are not input to subtractor <NUM>, and the first test signal is input to signal processing circuit <NUM>. As shown in <FIG>, controller <NUM> (second parameter determiner <NUM>) determines the second parameter regarding the amplitude based on (i) an output of amplitude adjuster <NUM> which is output when the input signal and the feedback signal are not input to subtractor <NUM> and a first test signal is input to signal processing circuit <NUM> and (ii) the first test signal (the first test signal before it is signal-processed by signal processing device <NUM>).

Specifically, controller <NUM> calculates the effective value for one cycle of the first test signal obtained directly from test signal generator <NUM> by controller <NUM> (step S303). It should be noted that if the effective value for one cycle of the first test signal is a fixed value and is stored in a memory or the like, the process of calculating the effective value is unnecessary.

Controller <NUM> calculates the effective value for one cycle of the output of amplitude adjuster <NUM> (step S304). Since the first test signal input to signal processing circuit <NUM> is amplified by power amplification circuit <NUM>, it is necessary to adjust the scale in order to subtract the signals before and after the amplification in subtractor <NUM>. The effective value for one cycle of the first test signal obtained directly from test signal generator <NUM> by controller <NUM> corresponds to the amplitude of the signal before the amplification in power amplifier circuit <NUM>, and the effective value for one cycle of the output of amplitude adjuster <NUM> corresponds to the amplitude of the signal after the amplification in power amplifier circuit <NUM>.

Next, controller <NUM> calculates the difference obtained by subtracting the effective value for one cycle of the first test signal from the effective value for one cycle of the output of amplitude adjuster <NUM> (step S305). The larger the difference between the amplitude of the output of amplitude adjuster <NUM> and the amplitude of the first test signal, the larger the absolute value of the difference.

Controller <NUM> determines whether the absolute value of the calculated difference is equal to or smaller than the second threshold (for example, B (positive value)) (step S306). That is, controller <NUM> determines whether the difference is equal to or greater than -B and equal to or smaller than +B.

When the absolute value of the calculated difference is not equal to or smaller than B (No in step S306), controller <NUM> determines whether the difference is greater than <NUM> (step S307).

When the calculated difference is greater than <NUM> (Yes in step S307), controller <NUM> decreases the gain of amplitude adjuster <NUM> (step S308). That is, since the amplitude of the output of amplitude adjuster <NUM> is greater than the amplitude of the first test signal due to the amplification by power amplifier circuit <NUM>, the gain of amplitude adjuster <NUM> is decreased and the difference is adjusted to approach <NUM>.

When the calculated difference is smaller than <NUM> (No in step S307), controller <NUM> increases the gain of amplitude adjuster <NUM> (step S309). Although the details will be described later, when the gain of amplitude adjuster <NUM> is made too small in step S308 and the amplitude of the output of amplitude adjuster <NUM> becomes smaller than the amplitude of the first test signal, the gain of amplitude adjuster <NUM> is increased and the difference is adjusted to approach <NUM>.

Then, the processes from step S304 are performed again. That is, it is repeated until the absolute value of the difference obtained by subtracting the effective value for one cycle of the first test signal from the effective value for one cycle of the output of amplitude adjuster <NUM> becomes equal to or smaller than B that after adjusting the gain of amplitude adjuster <NUM>, the output of amplitude adjuster <NUM> which is output when the first signal is input to signal processing circuit <NUM> is confirmed, and according to the output, the gain of amplitude adjuster <NUM> is adjusted again.

When the absolute value of the calculated difference is equal to or smaller than B (Yes in step S306), controller <NUM> determines the current gain of amplitude adjuster <NUM> as the second parameter.

Then, controller <NUM> changes the connection destination of selector <NUM> to compensation filter <NUM> (step S310), and controls switch <NUM> so that it is in a conductive state (step S311). With this, amplitude adjuster <NUM> adjusts the amplitude for the third digital signal using a second parameter regarding the amplitude determined based on (i) an output of amplitude adjuster <NUM> which is output when the input signal and the feedback signal are not input to subtractor <NUM> and a first test signal is input to signal processing circuit <NUM> and (ii) the first test signal.

It should be noted that an example of adjusting the second parameter by calculating the effective value for one cycle of the test signal has been described, but in order to simplify the calculation on the circuit, the second parameter may be adjusted using the maximum value of the amplitude for one cycle of the test signal.

The operation at the time of determining the third parameter regarding the delay will be described with reference to <FIG>, <FIG> and <FIG>.

<FIG> is a diagram for illustrating a signal flow at the time of determining the third parameter of signal processing device <NUM> according to the embodiment. In <FIG>, the signal flow is indicated by a thick dashed arrow.

<FIG> and <FIG> are flowcharts showing an example of the operation at the time of determining the third parameter of signal processing device <NUM> according to the embodiment. <FIG> and <FIG> are flowcharts showing the details of step S103 of <FIG>. The circled "A" in <FIG> indicates that the next process of step S407 is step S403. In addition, the circled "B1" and "B2" in <FIG> and <FIG> indicate that the next process in the case of Yes in step S405 is step S408, and indicate that the next process of step S410, step S411, step S413, and step S414 is step S407.

Controller <NUM> controls switch <NUM> so that it is in a non-conductive state (step S401). By making switch <NUM> in a non-conductive state, it is possible to prevent sound from being output from speaker <NUM> at the time of determining the third parameter. Since the second test signal is input to signal processing circuit <NUM> at the time of determining the third parameter, switch <NUM> is put into a non-conductive state so that the sound corresponding to the second test signal is not output from speaker <NUM>.

Controller <NUM> changes the connection destination of selector <NUM> to test signal generator <NUM>, and causes test signal generator <NUM> to output a second test signal (for example, a sine wave) having a predetermined frequency (step S402). For example, the frequency of the second test signal and the frequency of the first test signal are different, but they may be the same frequency, or the first test signal and the second test signal may be the same signal. In addition, it is assumed that the input signal is not input to subtractor <NUM> at the time of determining the third parameter. With this, as shown in <FIG>, it becomes in such a state that the input signal and the feedback signal are not input to subtractor <NUM>, and the second test signal is input to signal processing circuit <NUM>. As shown in <FIG>, controller <NUM> (third parameter determiner <NUM>) determines the third parameter regarding the delay based on a difference signal which is a difference between the second digital signal having the delay adjusted by delay adjuster <NUM> and the third digital signal having the DC offset adjusted by offset adjuster <NUM> and the amplitude adjusted by amplitude adjuster <NUM>, when the input signal and the feedback signal are not input to subtractor <NUM>, and the second test signal is input to signal processing circuit <NUM>.

Specifically, controller <NUM> calculates the effective value for one cycle of the difference signal (step S403). Since the second test signal input to signal processing circuit <NUM> is delayed (phase shifted) by A/D converter <NUM>, it is also necessary to delay the signal input from signal processing circuit <NUM> to subtractor <NUM> via delay adjuster <NUM> or the like to the same extent in order for subtractor <NUM> to subtract signals at the same timing.

Controller <NUM> determines whether the calculated effective value is equal to or smaller than the third threshold (for example, C (positive value)) (step S404).

When the calculated effective value is not equal to or smaller than C (No in step S404), controller <NUM> determines whether there is an effective value of the difference signal one cycle before (step S405). Specifically, when the determination in step S405 is performed for the first time after the start of the process of determining the third parameter, there is an effective value one cycle before, and when the determination in step S405 has already been performed after the start of the process of determining the third parameter (specifically, when the process in step S407 described later has been performed), there is an effective value one cycle before.

When there is not an effective value of the difference signal one cycle before (No in step S405), controller <NUM> increases or decreases the delay amount in delay adjuster <NUM> (step S406). Since it is not known whether the output of delay adjuster <NUM> is delayed or advanced from the output of A/D converter <NUM> depending on the initial value of the delay amount in delay adjuster <NUM>, first, the delay amount in delay adjuster <NUM> is either increased or decreased.

Next, controller <NUM> stores the calculated effective value as an effective value one cycle before in a memory or the like, and holds in the memory or the like whether the delay amount is increased or decreased (step S407). The information stored in the memory or the like is used in the processes after step S403 that are performed again.

Then, the process from step S403 is performed again.

When the effective value recalculated after the delay amount in delay adjuster <NUM> is adjusted (the effective value for the next one cycle after the one cycle at the time of the previous calculation) is not equal to or smaller than C (No in step S404), controller <NUM> determines whether the effective value one cycle before is stored in the memory or the like. Since the effective value one cycle before is stored in the memory or the like after the process in step S407, controller <NUM> determines that there is an effective value one cycle before (Yes in step S405).

Controller <NUM> determines whether the effective value calculated this time is smaller than the effective value one cycle before (step S408). If the phase difference between the output of delay adjuster <NUM> and the output of A/D converter <NUM> is smaller due to the adjustment of the delay amount performed after the calculation of the effective value one cycle before, it turns out that the previous adjustment of the delay amount is the correct adjustment.

When the effective value calculated this time is smaller than the effective value one cycle before (Yes in step S408), that is, when the adjustment of the delay amount one cycle before is the correct adjustment, controller <NUM> determines whether the delay amount was increased one cycle before (step S409).

When the delay amount was increased one cycle before (Yes in step S409), controller <NUM> further increases the delay amount (step S410) because the phase difference between the output of delay adjuster <NUM> and the output of A/D converter <NUM> is decreased by increasing the delay amount. When the delay amount was decreased one cycle before (No in step S409), controller <NUM> further decreases the delay amount (step S411) because the phase difference between the output of delay adjuster <NUM> and the output of A/D converter <NUM> is decreased by decreasing the delay amount.

When the effective value calculated this time is greater than the effective value one cycle before (No in step S408), that is, when the adjustment of the delay amount one cycle before is the erroneous adjustment, controller <NUM> determines whether the delay amount was increased one cycle before (step S412).

When the delay amount was increased one cycle before (Yes in step S412), controller <NUM> decreases the delay amount (step S413) because the phase difference between the output of delay adjuster <NUM> and the output of A/D converter <NUM> is increased by increasing the delay amount. When the delay amount was decreased one cycle before (No in step S412), controller <NUM> increases the delay amount (step S414) because the phase difference between the output of delay adjuster <NUM> and the output of A/D converter <NUM> is increased by decreasing the delay amount.

In this way, it is repeated until the effective value for one cycle of the difference signal becomes equal to or smaller than C that after adjusting the delay amount of delay adjuster <NUM>, the difference signal (output of subtractor <NUM>) when the second test signal is input to signal processing circuit <NUM> is confirmed, and the delay amount by delay adjuster <NUM> is adjusted again according to the difference signal.

When the calculated effective value is equal to or smaller than C (Yes in step S404), controller <NUM> determines the current delay amount in delay adjuster <NUM> as the third parameter.

Then, controller <NUM> changes the connection destination of selector <NUM> to compensation filter <NUM> (step S415), and controls switch <NUM> so that it is in a conductive state (step S416). With this, delay adjuster <NUM> adjusts the delay of the second digital signal using the third parameter regarding the delay determined based on the difference signal when the input signal and the feedback signal are not input to subtractor <NUM> and the second test signal is input to signal processing circuit <NUM>.

It should be noted that an example of adjusting the third parameter by calculating the effective value for one cycle of the test signal has been described, but in order to simplify the calculation on the circuit, the third parameter may be adjusted using the maximum value of the amplitude for one cycle of the test signal.

It should be noted that controller <NUM> may continuously determine each parameter when determining each parameter in order of the first parameter, the second parameter, and the third parameter. In this case, after the determination of the first parameter, the connection destination of selector <NUM> may not be changed to compensation filter <NUM> as shown in step S208 of <FIG>, and switch <NUM> may not be put into a conductive state as shown in step S209 of <FIG>. In addition, after the determination of the second parameter, the connection destination of selector <NUM> may not be changed to compensation filter <NUM> as shown in step S310 of <FIG>, and switch <NUM> may not be put into a conductive state as shown in step S311 of <FIG>.

In addition, for example, in the above embodiment, amplitude adjuster <NUM> adjusts the amplitude of the third digital signal having the DC offset adjusted by offset adjuster <NUM>, but the present invention is not limited thereto. For example, offset adjuster <NUM> may adjust the DC offset for the third digital signal having the amplitude adjusted by amplitude adjuster <NUM>. That is, the output of A/D converter <NUM> may be input to amplitude adjuster <NUM>, and the output of offset adjuster <NUM> may be input to subtractor <NUM> (calculator).

In addition, for example, in the above embodiment, each parameter is determined in order of the first parameter, the second parameter, and the third parameter, but it is not necessary to determine in this order.

In addition, for example, in the above embodiment, signal processing device <NUM> includes switch <NUM>, but it may not include switch <NUM>.

In addition, for example, in the above embodiment, a calculator that extracts a difference signal which is a difference between the third digital signal having the DC offset adjusted by offset adjuster <NUM> and the amplitude adjusted by amplitude adjuster <NUM> and the second digital signal having the delay adjusted by delay adjuster53, and outputs the feedback signal based on the difference signal includes subtractor <NUM>, compensation filter <NUM>, and decimation filter <NUM>, but is not limited thereto. For example, the calculator may include at least subtractor <NUM>.

The present disclosure can be realized as a program for causing a computer to execute the steps included in the method according to claim <NUM>. Furthermore, the present disclosure can be realized as a non-temporary computer-readable recording medium such as a CD-ROM on which the program is recorded.

For example, when the present disclosure is realized by a program (software), each step is executed by executing the program using hardware resources such as a CPU, a memory, and an input/output circuit of a computer. That is, each step is executed by the CPU obtaining data from the memory, the input/output circuit or the like and performs an operation, or outputs the operation result to the memory, the input/output circuit or the like.

In addition, the component included in signal processing device <NUM> of the above-described embodiment may be realized as a large scale integration (LSI) which is an integrated circuit (IC).

In addition, the integrated circuit is not limited to the LSI, and may be realized by a dedicated circuit or a general-purpose processor. A programmable field programmable gate array (FPGA) or a reconfigurable processor in which the connections and settings of circuit cells inside the LSI can be reconfigured may be used.

Furthermore, if an integrated circuit technology that replaces an LSI appears due to advances in semiconductor technology or another technology derived therefrom, it is natural that the circuit integration of the components included in signal processing device <NUM> may be performed using that technology.

As described above, an embodiment has been described as an example of the technology in the present disclosure. To that end, the accompanying drawings and detailed description have been provided.

Therefore, the components described in the attached drawings and the detailed description may include not only the components essential for problem solving but also the components not essential for problem solving. For that reason, the fact that these non-essential components are described in the accompanying drawings or detailed description should not immediately determine that those non-essential components are essential.

In addition, since the above-described embodiment is for exemplifying the technology in the present disclosure, various changes, replacements, additions, omissions or the like can be made within the scope of claims.

Claim 1:
A signal processing device (<NUM>), comprising:
a subtractor (<NUM>) that is configured to subtract
a feedback signal from an input signal that is a digital audio signal and to output a first digital signal;
a signal processing circuit (<NUM>) that is configured to perform signal processing on the first digital signal and to output a second digital signal;
a power amplifier circuit (<NUM>) that is configured to amplify the second digital signal, to output the second digital signal amplified into an analog signal, and to output the analog signal;
an A/D converter (<NUM>) that is configured to convert the analog signal into a third digital signal and to output the third digital signal;
an offset adjuster (<NUM>) that is configured to adjust a DC offset for the third digital signal;
an amplitude adjuster (<NUM>) that is configured to adjust an amplitude for the third digital signal;
a delay adjuster (<NUM>) that is configured to adjust a delay of the second digital signal; and
a calculator that is configured to extract
a difference signal which is a difference between the third digital signal having the DC offset adjusted by the offset adjuster (<NUM>) and the amplitude adjusted by the amplitude adjuster (<NUM>) and the second digital signal having the delay adjusted by the delay adjuster (<NUM>), and outputs the feedback signal based on the difference signal,
wherein the offset adjuster (<NUM>) is configured to adjust the DC offset using a first parameter regarding the DC offset determined based on an output of the offset adjuster (<NUM>) which is output when no signal is input to the signal processing circuit (<NUM>) by the subtractor (<NUM>),
the amplitude adjuster (<NUM>) is configured to adjust the amplitude using a second parameter regarding the amplitude determined based on (i) an output of the amplitude adjuster (<NUM>) which is output when the input signal and the feedback signal are not input to the subtractor (<NUM>) and a first test signal is input to the signal processing circuit (<NUM>) and (ii) the first test signal, and
the delay adjuster (<NUM>) is configured to adjust the delay using a third parameter regarding the delay determined based on the difference signal when the input signal and the feedback signal are not input to the subtractor (<NUM>) and a second test signal is input to the signal processing circuit (<NUM>).