Patent Description:
A Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers, and includes many repeated storage units. Each storage unit usually includes a capacitor and a transistor. A gate electrode of the transistor is connected with a Word Line (WL), a drain electrode of the transistor is connected with a Bit Line (BL), and a source electrode of the transistor is connected with the capacitor. Voltage signals on the WLs can control the transistors to be turned on or off, so that the data information stored in the capacitor can be read through the BLs, or the data information can be written into the capacitor through the BLs for storage.

For the DRAM, data errors often occur during data storage, therefore, an Error Checking and Correcting (ECC) technology is needed to ensure the correctness of data storage. Usually, check bits are added on the basis of a certain length of valid data bits to check and correct error data.

Related arts can be found in <CIT>, <CIT> and <CIT>. <CIT> discloses a semiconductor memory device and a method for correcting a data error therein. The device comprises a memory cell array that stores a plurality of data bits and a plurality of check bits corresponding to the plurality of data bits. A read circuit is further provided that performs an operation of reading out the plurality of data bits and the plurality of check bits from the memory cell array. The semiconductor memory device further comprises error circuits for correcting a first error in the data bits of the first group and a second error in the data bits of the second group, respectively. The error circuit receives in parallel odd-numbered and even-numbered data and check bits read out from the memory cell array during a first cycle of a read mode of operation and generates first syndrome bits and second syndrome bits. During a second cycle of the read mode of operation, the circuit corrects the error in the odd-numbered data bits and the error in the even-numbered data bits responsive to the first and the second syndrome bits, respectively.

<CIT> discloses a semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization. An error correction system composed of a data bit of <NUM> bits and a check bit of <NUM> bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

<CIT> discloses a memory cell array (<NUM>) divided into memory units (<NUM>-<NUM>) each having a predetermined number of bits arranged along the direction of a word line. ECC circuits (24a-24d) correct errors in bit data that are written into the memory units.

One or more embodiments are exemplarily described with the reference of pictures in the corresponding drawings. These exemplary descriptions do not constitute a limitation on the embodiments. Elements with the same reference signs in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

It can be seen from the Background that the ECC technology in the related art is still deficient.

The analysis revealed that if there is a one-bit error in data, the ECC technology can not only find the error but also correct the error. The ECC technology can further find <NUM> to <NUM> bit errors. However, it is difficult for the ECC technology to correct errors of <NUM> bits and more bits. In other words, although the ECC technology can check and correct a single-bit error at the same time, the current ECC technology can not help if errors in two or more bits of data are checked at the same time. Furthermore, further analysis revealed that at present, there is a higher probability of simultaneous errors in two bits that are in adjacent locations. Further analysis revealed that the main reasons for this problem are as follows.

<FIG> is a structural schematic diagram of top view of a layout of a memory. The memory includes: multiple active regions <NUM> arranged in an array, bit lines <NUM>, word lines <NUM>, and capacitors <NUM> electrically connected with the active regions. There is the defect of cell to cell bridge, or called adjacent two bit errors, in the memory. For example, a bridge connection occurs between a capacitor <NUM> and a capacitor <NUM> corresponding to adjacent active regions <NUM> respectively. As illustrated in a dashed box in <FIG>, the capacitor <NUM> is connected with a bit line BL3 through a transistor, and the capacitor <NUM> is connected with a bit line BL2 through a transistor. As the process size of the memory gets smaller, the probability of occurrence of such defect is increasing.

<FIG> is a structural schematic diagram of a memory. The memory includes storage arrays, column select signal units, local data buses, and block data buses.

The storage arrays include storage units <NUM>. Each storage unit <NUM> is connected with a bit line BL and a word line WL.

Column select signal units are marked as CSL<n-<NUM>>, CSL<n> and CSL<n+<NUM>> in <FIG>. Each column select signal unit includes multiple column select signal lines, and each column select signal line is connected with the corresponding bit line BL in the storage array through a switch. The control signal of the switches come from a column decoding circuit (not illustrated in <FIG>, but marked as YDEC in <FIG>) and is used to determine whether the data on the bit line BL is transmitted to local data buses. For example, the column select signal unit CSL<n> includes <NUM> column select signal lines, and the <NUM> column select signal lines are connected with <NUM> bit lines BL in the storage array through switches.

Local data buses are marked as LIO in <FIG>. Herein LIO:O<<NUM>:<NUM>> indicates odd-numbered local data buses, and LIO:E<<NUM>:<NUM>> indicates even-numbered local data buses.

Block data buses are marked as YIO in <FIG>. Herein YIO:O<<NUM>:<NUM>> indicates odd-numbered block data buses, and YIO:E<<NUM>:<NUM>> indicates even-numbered block data buses. The local data buses are connected with the block data buses through local switch circuits (such as local sensitive amplifying circuits, not illustrated in <FIG>). In <FIG>, arc curves indicate interaction between YIO:E<<NUM>:<NUM>> and LIO:E<<NUM>:<NUM>> and interaction between YIO:O<<NUM>:<NUM>> and LIO:O<<NUM>:<NUM>>.

In conjunction with <FIG> and <FIG>, the block data buses YIO:E<<NUM>:<NUM>> and YIO:O<<NUM>:<NUM>> are connected to the same error checking and correcting unit <NUM>. If two bit lines BL corresponding to two storage units <NUM> are connected to exactly the same column decoding circuit, two errors occur simultaneously at the same readout time point. For example, in <FIG>, errors occur at the storage unit <NUM> and the storage unit <NUM> (<NUM> and <NUM> in <FIG> represent capacitors, <NUM> and <NUM> in <FIG> represent storage units, the storage units usually include capacitors and transistors, which are marked as the same here to illustrate adjacent two bit errors in conjunction with <FIG> and <FIG>) simultaneously. The corresponding bit line BL2 and bit line BL3 transmit their data to the local data line LIO:O<<NUM>:<NUM>> and the local data line LIO:E<<NUM>:<NUM>> through the column select signal unit CSL<n>, then, the data is transmitted to the YIO:E<<NUM>:<NUM>> and the YIO:O<<NUM>:<NUM>> through the local switch circuits, and thus, two bit errors enter the error checking and correcting unit <NUM> at the same time. The currently used ECC technology (for example, the ECC technology for <NUM> bits (data bits)+<NUM> bits (check bits) can only implement one-bit correction) cannot correct the above two bit errors.

In order to solve the above problems, the embodiments of the present disclosure provide a memory. The memory includes a first error checking and correcting unit and a second error checking and correcting unit. The arrangement of the two error checking and correcting units enable that when a half bank outputs two data errors at the same time, the data errors can be corrected, thereby improving the error checking and correcting ability of the memory, and improving the reading and writing performance of the memory.

In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. However, those ordinary skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed for readers to better understand the present disclosure.

<FIG> is a structural schematic diagram of a memory provided by an embodiment of the present disclosure.

Referring to <FIG>, in this embodiment, the memory includes:.

The memory provided by this embodiment will be described in detail below in conjunction with the drawings.

For ease of illustration and description, only one bank <NUM> is illustrated in <FIG> as an example. In present embodiment, the output data of the U half bank <NUM> correspond to high bit data, and the output data of the V half bank <NUM> correspond to low bit data. In other embodiments, the bank may also be configured as that: the output data of the U half bank correspond to low bit data, and the output data of the V half bank correspond to high bit data. It should be understood that the high bit data and the low bit data are relative, and the high bit data and the low bit data are clearly defined in comparison.

Both the U half bank <NUM> and the V half bank <NUM> include multiple storage arrays arranged in an array (referring to <FIG> and <FIG>). In present embodiment, taking <NUM> bits of output data of the U half bank <NUM> as an example, herein <NUM> bits of data are valid data (the data that the memory needs to interact with an external controller through a memory interface), and <NUM> bits of data are check bits generated after processing by the first error checking and correcting unit <NUM> and/or the second error checking and correcting unit <NUM>.

It should be understood that the memory includes a data writing operation and a data reading operation. When the data writing operation is performed on the storage arrays in the memory, the data received by the memory interface is processed by an ECC module (such as the first error checking and correcting unit <NUM> and the second error checking and correcting unit <NUM> in <FIG>).

For example, the data entering the ECC module are <NUM> bits of data, and the <NUM> bits of data are also called valid data. The data output by the ECC module are <NUM> bits (<NUM> bits+<NUM> bits) of data in which <NUM> bits of data are valid data and <NUM> bits are check bits generated by the ECC module. These <NUM> bits are all stored in the storage arrays of the U half bank <NUM>. The operations for the writing data performed by the ECC module can be referred to as an encoding process.

When the data reading operation is performed on the storage arrays in the memory, the U half bank <NUM> also outputs <NUM> bits (<NUM> bits+<NUM> bits) of data. These <NUM> bits enter the ECC module simultaneously, and the ECC module executes an algorithm opposite to that of the writing operation. The operations for the reading data performed by the ECC module can be referred to as a decoding process. The ECC module performs a decoding operation on <NUM> bits of valid data and compares the result generated by the decoding operation with the <NUM> check bits, then whether the output 64bits of valid data have errors is determined. If only <NUM> bit in <NUM> bits has an error (one-bit error), the ECC module may also correct the one-bit error.

Continuing to refer to <FIG>, in present embodiment, for example, the U half bank <NUM> outputs <NUM> bits (<NUM> bits+<NUM> bits) of output data to the first error checking and correcting unit <NUM>, and the V half bank <NUM> also outputs <NUM> bits (<NUM> bits+<NUM> bits) of output data to the first error checking and correcting unit <NUM>; and the U half bank <NUM> outputs <NUM> bits (<NUM> bits+<NUM> bits) of output data to the second error checking and correcting unit <NUM>, and the V half bank <NUM> also outputs <NUM> bits (<NUM> bits+<NUM> bits) of output data to the second error checking and correcting unit <NUM>.

A comparative embodiment is provided, the U half bank <NUM> outputs <NUM> bits (<NUM> bits+<NUM> bits) of output data to the first error checking and correcting unit <NUM>, and the V half bank <NUM> outputs <NUM> bits (<NUM> bits+<NUM> bits) of output data to the second error checking and correcting unit <NUM>.

In comparison, part of the output data of the U half bank <NUM> (or the V half bank <NUM>) are input into the first error checking and correcting unit <NUM> for checking and correcting errors, and the remaining output data are input into the second error checking and correcting unit <NUM> for checking and correcting errors, so that when more than one error occurs (such as two bit errors)in the output data of the U half bank <NUM> (or the V half bank <NUM>) at the same time, different errors can be corrected by the first error checking and correcting unit <NUM> or the second error checking and correcting unit <NUM>. Therefore, the memory can correct more than one error, and the error checking and correcting ability of the memory is improved.

In this embodiment, the input bits number of the first error checking and correcting unit <NUM> is the same as the input bits number of the second error checking and correcting unit <NUM>. In an example, the input bits number of the first error checking and correcting unit <NUM> and the input bits number of the second error checking and correcting unit <NUM> are both <NUM> bits+<NUM> bits. <NUM> bits are valid data written or read by the U half bank <NUM> or the V half bank <NUM>, and <NUM> bits are the input bits of the first error checking and correcting unit <NUM> or the check bits generated by the second error checking and correcting unit <NUM>.

Furthermore, the first error checking and correcting unit <NUM> has a same internal error checking algorithm as the second error checking and correcting unit <NUM>, which helps to reduce the difficulty of the memory design.

Taking the first error checking and correcting unit <NUM> as an example, each time the data is written, the first error checking and correcting unit <NUM> uses the internal error checking algorithm to calculate the valid data (<NUM> bits) to obtain check bits (<NUM> bits) marked as first check bits. Then, the valid data (<NUM> bits) and the check bits (<NUM> bits) are written into the storage arrays <NUM> simultaneously. When these data are read from the storage arrays <NUM>, the same algorithm is used to calculate the valid data (<NUM> bits) again to obtain check bits (<NUM> bits) marked as second check bits. The second check bits are compared with the first check bits read directly, if the result is the same, it means that the data are correct, otherwise it means that there is an error, and the first error checking and correcting unit <NUM> can logically check the error. When only one bit error occurs, the first error checking and correcting unit <NUM> can correct the error without affecting the reading operation of the memory. For example, when "<NUM>" appearing in the third bit in <NUM> bits is an error bit, the first error checking and correcting unit <NUM> corrects "<NUM>" in the third bit to "<NUM>".

The working principle of the second error checking and correcting unit <NUM> refers to that of the first error checking and correcting unit <NUM>, and will not be elaborated below.

In some embodiments, part of the output data in the U half bank <NUM> are input into the first error checking and correcting unit <NUM> for checking and correcting errors, and the remaining output data are input into the second error checking and correcting unit <NUM> for checking and correcting errors. In this way, adjacent two bit errors that may occur in the same U half bank <NUM> are placed in different ECC units respectively. The two error data are processed by the first error checking and correcting unit <NUM> and the second error checking and correcting unit <NUM> respectively, that is, each of the first error checking and correcting unit <NUM> and the second error checking and correcting unit <NUM> only processes one error, but at the level of the memory, the memory can correct the two errors at the same time.

The error checking and correcting mechanism when an error occurs in the V half bank <NUM> can refer to the corresponding description of the U half bank <NUM>, and will not be elaborated here.

In present embodiment, the storage capacity of the U half bank <NUM> is the same as the storage capacity of the V half bank <NUM>. In other embodiments, the storage capacity of the U half bank may also be greater than or less than the storage capacity of the V half bank. For example, for an 8Gbit DRAM chip, there are a total of <NUM> banks <NUM>, and each bank <NUM> includes two half banks, so the storage capacity of one U half bank <NUM> and one V half bank <NUM> may both be <NUM> Mbit.

With reference to <FIG> and <FIG> is a schematic diagram of signal lines connection in a local region represented by a triangle <NUM> in a memory in <FIG>. Local data buses LIO are connected with an even number of sensitive amplifiers (not illustrated) through column select signal units <NUM>, and the sensitive amplifiers and the bit lines BL of the storage arrays <NUM> are disposed with one-to-one correspondence. The column select signal units <NUM> include gating switches, and Column Select Signals (CSS) control the gating switches to be switched on or off. When the gating switches are switched on, the sensitive amplifiers and the local data buses LIO perform data interaction. When the gating switches are switched off, the sensitive amplifiers and the local data buses do not perform data interaction.

Furthermore, the output data on adjacent bit lines BL enter local data buses O and local data buses E through the sensitive amplifiers and the column select signal units <NUM> respectively. For the convenience of distinction, in <FIG>, LIO:E indicates the local data buses E, LIO:O indicates the local data buses O, CSL<n-<NUM>>, CSL<n> and CSL<n+<NUM>> indicate the column select signal units, the gating switches are located in the column select signal units (not illustrated), and the sensitive amplifiers are located on two sides of the bit lines BL (not illustrated). The local data buses E and block data buses E perform data interaction through local switch circuits (not illustrated), and the local data buses O and block data buses O perform data interaction through local switch circuits (not illustrated). In <FIG>, a solid line YIO:E with arrows indicates the block data buses E, and a solid line YIO:O with arrows indicates the block data buses O.

Continuing to refer to <FIG>, YIO1_O indicates one of block data buses O, and YIO1_E indicates one of block data buses E. In an embodiment, YIO:E in <FIG> may be understood as YIO1_E, and YIO:O in <FIG> may be understood as YIO1_O. In an embodiment, one YIO1_O or YIO1_E may be connected with the YIO:O or YIO:E of multiple storage arrays <NUM>. The YIO1_O is connected to the first error checking and correcting unit <NUM> through a block amplifier <NUM>, and the YIO1_E is connected to the second error checking and correcting unit <NUM> through a block amplifier <NUM>.

Continuing to refer to <FIG>, the data of the YIO_O enter the first error checking and correcting unit <NUM>, and the data of the YIO_E enter the second error checking and correcting unit <NUM>. In this embodiment, the U half bank <NUM> includes local switch circuits (Local SA, not illustrated) and an even number of local data buses, and the V half bank <NUM> includes local switch circuits (not illustrated) and an even number of local data buses. The local data buses are divided into local data buses O and local data buses E, the local data buses O are connected with respective block data buses O through local switch circuits, and the local data buses E are connected with respective block data buses E through local switch circuits.

It should be understood that the local data buses are sequentially numbered from zero according to natural numbers, odd-numbered local data buses are defined as the local data buses O, and the even-numbered local data buses are defined as the local data buses E. In other words, in the local data buses corresponding to the storage arrays with adjacent physical locations, the local data buses in odd locations are defined as the local data buses O, and the local data buses in even locations are defined as the local data buses E.

Since physically adjacent data are placed in different error checking and correcting units, that is, the physically adjacent data enter the first error checking and correcting unit <NUM> and the second error checking and correcting unit <NUM> respectively, when adjacent two bit errors occur, since the two bit errors are corrected in different error checking and correcting units respectively, the two bit errors can be processed at the same time. It should be understood that even if the process size continues to reduce and the risk of occurring bridge connection between adjacent capacitors increases, since the data corresponding to adjacent capacitors enter different error checking and correcting units for correcting errors, it can still be ensured that the errors of physically adjacent two bit data can be corrected.

Continuing to refer to <FIG>, column decoding circuits YDEC and the column select signal CSL generated by the column decoding circuits YDEC are illustrated. The column select signal CSL is electrically connected with multiple storage arrays <NUM>, and the storage array <NUM> for a storage operation is selected through the column select signal CSL. Continuing to refer to <FIG>, in an embodiment, the column select signal CSL corresponds to CSL<n-<NUM>>, CSL<n> and CSL<n+<NUM>> in <FIG>.

Continuing to refer to <FIG>, the storage arrays <NUM> in the U half bank <NUM> are numbered from <NUM> according to natural numbers, and the block data buses are electrically connected with even-numbered storage arrays <NUM>. In some embodiments, the storage arrays <NUM> include storage units, local data buses E, local data buses O and local switch circuits. The block data buses are connected with the local data buses E through the local switch circuits, and the block data buses are connected with the local data buses O through the local switch circuits. In <FIG>, the connection relationship between the block data buses and the storage arrays <NUM> is indicated by triangular symbols. The description of the connection relationship of the block data buses of the V half bank <NUM> refers to the corresponding description of the U half bank <NUM>, and will not be elaborated below.

In present embodiment, in order to reduce the length of the column select signal line CSL1 to reduce the parasitic resistance of the column select signal line CSL1 so as to reduce the power consumption, for the U half bank <NUM>, the column decoding circuits YDEC are located on two opposite sides of multiple storage arrays <NUM> respectively, and for the V half bank <NUM>, the column decoding circuits YDEC are located on two opposite sides of multiple storage arrays <NUM> respectively. It should be noted that in other embodiments, for each U half bank or each V half bank, the number of the column decoding circuits may also be one.

It should be understood that in an example, the number of block data buses are <NUM>*<NUM>*(<NUM>*N), the number of local data buses are <NUM>*<NUM>*M*(<NUM>*N); the number of block data buses O are <NUM>*(<NUM>*N), the number of block data buses E are <NUM>*(<NUM>*N); the number of local data buses O are <NUM>*M*(<NUM>*N), and the number of local data buses E are <NUM>*M*(<NUM>*N). One block data bus O corresponds to M local data buses O, and one block data bus E corresponds to M local data buses E. The local data buses are divided into M*(<NUM>*N) groups of local data buses O and M*(<NUM>*N) groups of local data buses E by taking <NUM> adjacent local data buses as one group. M and N are natural numbers greater than or equal to <NUM>. Taking M and N both equal to <NUM> as an example, the number of block data buses are <NUM>*<NUM>*<NUM>, the number of local data buses are <NUM>*<NUM>*<NUM>, the number of block data buses O are <NUM>* <NUM>, the number of block data buses E are <NUM>* <NUM>, the number of local data buses O are <NUM>* <NUM>, the number of local data buses E are <NUM>* <NUM>, and there are a total of <NUM> groups of local data buses O and <NUM> groups of local data buses E.

In an example, as illustrated in <FIG>, the U half bank <NUM> includes an even number of block data buses, the block data buses are sequentially numbered from zero according to natural numbers, the odd-numbered block data buses O (marked as YIO1_O) are connected with the first error checking and correcting unit <NUM>, and the even-numbered block data buses E (marked as YIO1_E) are connected with the second error checking and correcting unit <NUM>. The V half bank <NUM> includes an even number of block data buses, the block data buses are sequentially numbered from zero according to natural numbers, the odd-numbered block data buses O (marked as YIO2_O) are connected with the first error checking and correcting unit <NUM>, and the even-numbered block data buses E (marked as YIO2_E) are connected with the second error checking and correcting unit <NUM>.

In this way, the data of the block data buses O (YIO1_O) of the U half bank <NUM> and the data of the block data buses O (YIO2_O) of the V half bank <NUM> enter the first error checking and correcting unit <NUM> for checking and correcting errors. The data of the block data buses E (YIO1_E) of the U half bank <NUM> and the data of the block data buses E (YIO2_E) of the V half bank <NUM> enter the second error checking and correcting unit <NUM> for checking and correcting errors.

In another example, as illustrated in <FIG>, the U half bank <NUM> includes an even number of block data buses. The block data buses are sequentially numbered from zero according to natural numbers, the odd-numbered block data buses O (YIO1_O) are connected with the first error checking and correcting unit <NUM>, and the even-numbered block data buses E (YIO1_E) are connected with the second error checking and correcting unit <NUM>. The V half bank <NUM> includes an even number of block data buses, the block data buses are sequentially numbered from zero according to natural numbers, the odd-numbered block data buses O (YIO2_O) are connected with the second error checking and correcting unit <NUM>, and the even-numbered block data buses E (YIO2_E) are connected with the first error checking and correcting unit <NUM>.

Continuing to refer to <FIG>, the data of the block data buses O (YIO1_O) of the U half bank <NUM> and the data of the block data buses E (YIO2_E) of the V half bank <NUM> enter the first error checking and correcting unit <NUM> for checking and correcting errors; and the data of the block data buses E (YIO1_E) of the U half bank <NUM> and the data of the block data buses O (YIO2_O) of the V half bank <NUM> enter the second error checking and correcting unit <NUM> for checking and correcting errors.

In another example, as illustrated in <FIG>, the U half bank <NUM> includes an even number of block data buses. The block data buses are sequentially numbered from zero according to natural numbers, the odd-numbered block data buses O (YIO1_O) are connected with the second error checking and correcting unit <NUM>, and the even-numbered block data buses E (YIO1_E) are connected with the first error checking and correcting unit <NUM>. The V half bank <NUM> includes an even number of block data buses, the block data buses are sequentially numbered from zero according to natural numbers, the odd-numbered block data buses O (YIO2_O) are connected with the first error checking and correcting unit <NUM>, and the even-numbered block data buses E (YIO2_E) are connected with the second error checking and correcting unit <NUM>.

Continuing to refer to <FIG>, the data of the block data buses E (YIO1_E) of the U half bank <NUM> and the data of the block data buses O (YIO2_O) of the V half bank <NUM> enter the first error checking and correcting unit <NUM> for checking and correcting errors; and the data of the block data buses O (YIO1_O) of the U half bank <NUM> and the data of the block data buses E (YIO2_E) of the V half bank <NUM> enter the second error checking and correcting unit <NUM> for checking and correcting errors.

In another example, as illustrated in <FIG>, the U half bank <NUM> includes an even number of block data buses. The block data buses are sequentially numbered from zero according to natural numbers, the odd-numbered block data buses O (YIO1_O) are connected with the second error checking and correcting unit <NUM>, and the even-numbered block data buses E (YIO1_E) are connected with the first error checking and correcting unit <NUM>. The V half bank includes an even number of block data buses. The block data buses are sequentially numbered from zero according to natural numbers, the odd-numbered block data buses O (YIO2_O) are connected with the second error checking and correcting unit <NUM>, and the even-numbered block data buses E (YIO2_E) are connected with the first error checking and correcting unit <NUM>.

Continuing to refer to <FIG>, the data of the block data buses E of the U half bank <NUM> and the data of the block data buses E of the V half bank <NUM> (YIO1_E and YIO2_E) enter the first error checking and correcting unit <NUM> for checking and correcting errors. The data of the block data buses O of the U half bank <NUM> and the data of the block data buses O of the V half bank <NUM> (YIO1_O and YIO2_O) enter the second error checking and correcting unit <NUM> for checking and correcting errors.

According to the memory provided by present embodiment, since the output data of the same half bank are input into different error checking and correcting units respectively, that is, part of the output data are input into the first error checking and correcting unit <NUM> for checking and correcting errors, and the remaining output data are input into the second error checking and correcting unit <NUM> for checking and correcting errors, if there are two bit data errors at the same time, the first error checking and correcting unit <NUM> and the second error checking and correcting unit <NUM> can respectively correct one bit of data in the two bits. Therefore the error checking and correcting ability of the memory may be improved.

Another embodiment of the present disclosure further provides a memory. The memory is substantially the same as the memory provided by the previous embodiment, and the main difference includes: in present embodiment, the output data of the U half bank include high bit data and low bit data, and the output data of the V half bank include high bit data and low bit data. The memory provided by present embodiment of the present disclosure will be described in detail below in conjunction with the drawings. It should be understood that the parts that are the same as or corresponding to the above embodiment refer to the detailed descriptions of the above embodiment, and will not be elaborated below.

<FIG> is a structural schematic diagram of a memory provided by another embodiment of the present disclosure. <FIG> is another structural schematic diagram of a memory provided by another embodiment of the present disclosure.

Referring to <FIG>, in this embodiment, the memory includes: multiple banks <NUM>, each bank includes a U half bank and a V half bank, a first error checking and correcting unit <NUM>, and a second error checking and correcting unit <NUM>.

The memory further includes column decoding circuits YDEC and block amplifiers <NUM>. The bank <NUM> includes multiple storage arrays <NUM>. In an example, part of the output data of the U half bank correspond to high bit data, and the remaining output data correspond to low bit data; and part of the output data of the V half bank correspond to high bit data, and the remaining output data correspond to low bit data. In an example, half of the output data of the U half bank correspond to high bit data, and the other half of the output data correspond to low bit data; and half of the output data of the V half bank correspond to high bit data, and the other half of the output data correspond to low bit data.

In this way, since the output data of the U half bank include low bit data and high bit data, a single access will only access part of the storage arrays in the U half bank, so as to reduce the power consumption of the memory. Similarly, since the output data of the V half bank include low bit data and high bit data, a single access will only access part of the storage arrays in the V half bank, so as to be also favorable for reducing the power consumption of the memory.

In an example, as illustrated in <FIG>, a U half bank includes a first U half bank <NUM> and a second U half bank <NUM>. The output data of the first U half bank <NUM> are high bit data, and the output data of the second U half bank <NUM> are low bit data. The V half bank includes a first V half bank <NUM> and a second V half bank <NUM>. The output data of the first V half bank <NUM> are high bit data, and the output data of the second V half bank <NUM> are low bit data.

The U half bank includes block data buses, which include block data buses YIO_U1_O (odd numbers) and block data buses YIO_U1_E (even numbers) corresponding to the first U half bank <NUM>, and block data buses YIO_U2_O (odd numbers) and block data buses YIO_U2_E (even numbers) corresponding to the second U half bank <NUM>. The V half bank includes block data buses, which include block data buses YIO_V1_O (odd numbers) and block data buses YIO_V1_E (even numbers) corresponding to the first V half bank <NUM>, and block data buses YIO_V2_O (odd numbers) and block data buses YIO_V2_E (even numbers) corresponding to the second V half bank <NUM>. The block data buses YIO_U1_E, the block data buses YIO_U2_E, the block data buses YIO_V1_E and the block data buses YIO_V2_E are connected with the first error checking and correcting unit <NUM>. The block data buses YIOU1_O, the block data buses YIO_U2_O, the block data buses YIO_V1_O and the block data buses YIO_V2_O are connected with the second error checking and correcting unit <NUM>. Triangles <NUM> in <FIG> indicate that the block data buses are electrically connected with the corresponding storage arrays <NUM>.

Continuing to refer to <FIG>, an embodiment is provided. For example, <NUM> bits (<NUM> bits of valid data + <NUM> check bits, corresponding to the block data buses YIO_U1_E) of the first U half bank <NUM>, <NUM> bits (<NUM> bits of valid data + <NUM> check bits, corresponding to the block data buses YIO_U2_E) of the second U half bank <NUM>, <NUM> bits (<NUM> bits of valid data + <NUM> check bits, corresponding to the block data buses YIO_V1_E) of the first V half bank <NUM> and <NUM> bits (<NUM> bits of valid data + <NUM> check bits, corresponding to the block data buses YIO_V2_E) of the second V half bank <NUM>, a total of <NUM> bits (<NUM> bits of valid data + <NUM> check bits), are input into the first error checking and correcting unit <NUM>. <NUM> bits (<NUM> bits of valid data + <NUM> check bits, corresponding to the block data buses YIO_U1_O) of the first U half bank <NUM>, <NUM> bits (<NUM> bits of valid data + <NUM> check bits, corresponding to the block data buses YIO_U2_O) of the second U half bank <NUM>, <NUM> bits (<NUM> bits of valid data + <NUM> check bits, corresponding to the block data buses YIO_V1_O) of the first V half bank <NUM> and <NUM> bits (<NUM> bits of valid data + <NUM> check bits, corresponding to the block data buses YIO_V2_O) of the second V half bank <NUM>, a total of <NUM> bits (<NUM> bits of valid data + <NUM> check bits), are input into the second error checking and correcting unit <NUM>. Since the output data of the same half bank (such as the first U half bank <NUM>) are input into different error checking and correcting units respectively, that is, part of the output data are input into the first error checking and correcting unit <NUM> for checking and correcting errors, and the remaining output data are input into the second error checking and correcting unit <NUM> for checking and correcting errors, if there are two bit data errors at the same time, the first error checking and correcting unit <NUM> and the second error checking and correcting unit <NUM> can correct one bit of data in the two bits respectively, so as to improve the error checking and correcting ability of the memory.

In another example, as illustrated in <FIG>, a U half bank includes a first U half bank <NUM>, a second U half bank <NUM>, a third U half bank <NUM> and a fourth U half bank <NUM> which are sequentially arranged. The output data of the first U half bank <NUM> and the third U half bank <NUM> are high bit data, and the output data of the second U half bank <NUM> and the fourth U half bank <NUM> are low bit data. The V half bank includes a first V half bank <NUM>, a second V half bank <NUM>, a third V half bank <NUM> and a fourth V half bank <NUM> which are sequentially arranged. The output data of the first V half bank <NUM> and the third V half bank <NUM> are high bit data, and the output data of the second V half bank <NUM> and the fourth V half bank <NUM> are low bit data. Triangles <NUM> in <FIG> indicate that the block data buses are electrically connected with the corresponding storage arrays <NUM>.

As described in the previous embodiment, the block data buses corresponding to the U half bank are divided into block data buses YIO_U_O1, block data buses YIO_U_O2, block data buses YIO_U_E1 and block data buses YIO_U_E2 according to odd and even locations. The block data buses corresponding to the V half bank are divided into block data buses YIO_V_O1, block data buses YIO_V_O2, block data buses YIO_V_E1 and block data buses YIO_V_E2 according to odd and even locations. The block data buses YIO_U_O1 are connected with the first U half bank <NUM> and the third U half bank <NUM>, and the block data buses YIO_U_O2 are connected with the second U half bank <NUM> and the fourth U half bank <NUM>. The block data buses YIO_V_O1 are connected with the first V half bank <NUM> and the third V half bank <NUM>, and the block data buses YIO_V_O2 are connected with the second V half bank <NUM> and the fourth V half bank <NUM>.

The connection relationship between the block data buses corresponding to the U half bank and the V half bank and the first error checking and correcting unit <NUM> and the second error checking and correcting unit <NUM> refers to the description of the above embodiment, and will not be elaborated here.

Compared with the above embodiment, the memory provided by present embodiment can correct errors of two bits at the same time. Moreover, since part of the output data in the U half bank and the V half bank are high bit data, and the remaining output data are low bit data, during a single access to the memory, only part of the storage arrays in the U half bank or the V half bank are accessed, so as to be favorable for reducing the power consumption of the memory.

Claim 1:
A memory comprising banks (<NUM>), each bank comprising a first half bank (U) (<NUM>) and a second half bank (V) (<NUM>);
a first error checking and correcting unit (<NUM>) connected with first half banks(<NUM>) and second half banks (<NUM>) and configured to check and correct errors of output data of the first half banks(<NUM>) and the second half banks (<NUM>); and
a second error checking and correcting unit (<NUM>) connected with the first half banks(<NUM>) and the second half banks (<NUM>) and configured to check and correct errors of output data of the first half banks(<NUM>) and the second half banks (<NUM>);
wherein each first half bank comprises an even number of block data buses, and the block data buses are sequentially numbered from zero according to natural numbers;
wherein odd-numbered block data buses are connected with the first error checking and correcting unit, and even-numbered block data buses are connected with the second error checking and correcting unit; or the odd-numbered block data buses are connected with the second error checking and correcting unit, and the even-numbered block data buses are connected with the first error checking and correcting unit;
the memory being characterized in that each first half bank and each second half bank corresponds to a different column decoding circuit respectively.