Patent Description:
An electronic device oftentimes integrates a system on a chip (SoC) with a power management integrated circuit (PMIC), communication ports, external memory or storage, and other peripheral function modules on a main logic board. The SoC includes one or more microprocessor or central processing unit (CPU) cores, memory, input/output ports, and secondary storage in a single package. The PMIC is typically disposed adjacent to the SoC on the main logic board and provides multiple direct current (DC) power supply rails to the SoC via conductive wires formed on the main logic board. The PMIC provides a plurality of power rails configured to drive operations of the SoC. Power characteristics (e.g., power consumption, current, and voltage) are monitored and controlled for each power rail and a corresponding portion of the SOC. It would be beneficial to have an efficient and flexible power management mechanism in the SoC to manage power provided by the PMIC.

<CIT> discloses a data processing system that includes a plurality of processor resources, a manager, and a power distributor. Each of the plurality of data processor cores is operable at a selected one of a plurality of performance states. The manager assigns each of a plurality of program elements to one of the plurality of processor resources, and synchronizing the program elements using barriers. The power distributor is coupled to the manager and to the plurality of processor resources, and assigns a performance state to each of the plurality of processor resources within an overall power budget, and in response to detecting that a program element assigned to a first processor resource is at a barrier, increases the performance state of a second processor resource that is not at the barrier within the overall power budget.

<CIT> discloses a system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally. <CIT> discloses a system including a plurality of processor cores connected to an energy source. The system further includes one or more budget creation circuits configured to determine respective portions of a total credit budget of the energy source. The system further includes a plurality of credit distribution circuits configured to distribute the respective portions of the total credit budget to respective subsets of the processor cores. The credit distribution circuits share energy credits in response to determining that at least some energy credits will be unused.

To address power management issues of an SoC-based electronic device, it would be highly desirable to provide a semiconductor device or system having a plurality of processor clusters, cluster memory or cache, PMIC, and system memory with a power management processor internal to each processor cluster. Various implementations of systems, methods and devices within the scope of the appended claims each having several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly after considering the section entitled "Detailed Description" one will understand how the aspects of various implementations are used to provide a semiconductor device with one or more clusters of processors each of which having a respective power management processor. For each cluster of processors, the respective power management processor is coupled to each processor in the respective cluster, and configured to control respective performance states (e.g., voltage and/or frequency), and/or perform debugging, of the processors of the cluster. In some implementations, the respective power management processor of each cluster of processors is further coupled to a system controller external to the one or more clusters of processors. By these means, the respective power management processor performs power, voltage, current, and thermal management for each cluster of processors on a firmware level, while the system controller enforces power allocations to different clusters of processors on a system level (e.g., using a performancecontrol software loop).

In one aspect, a power management method is implemented at an electronic device having a first processing cluster. The first processing cluster includes a plurality of processors and a power management processor distinct from the plurality of processors. The method includes obtaining performance information about the plurality of processors by the power management processor. The method further includes in accordance with the obtained performance information, executing first instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state, different from the first performance state, independently of respective performance states of other processors in the plurality of processors. The method further includes executing one or more debug instructions to perform debugging of a respective processor of the plurality of processors. In some embodiments, the one or more debug instructions are executed to perform debugging of the first processor when the first processor operates at the second performance state.

In some implementations, the power management processor is configured to execute second instructions to transition a second processor of the plurality of processors from a third performance state to a fourth performance state in accordance with the obtained performance information, independently of respective performance states of other processors in the plurality of processors. In some implementations, in accordance with the performance information indicating a third processor of the plurality of processors, different from the first processor, transitioning from an off state to an on state, the second performance state is a state that is associated with lower power consumption than the first performance state. In some implementations, in accordance with the performance information indicating a fourth processor of the plurality of processors, different from the first processor, transitioning from an on state to an off state, the second performance state is a state that is associated with higher power consumption than the first performance state.

In another aspect, an electronic device includes a first processing cluster having a plurality of processors and a power management processor that is distinct from the plurality of processors. The power management processor is configured to implement any of the above methods. Alternatively, in another aspect, an electronic device includes a first processing cluster having a plurality of processors, a power management processor, and memory having instructions stored thereon, which when executed by the power management processor cause the power management processor to perform any of the above methods.

These illustrative embodiments and implementations are mentioned not to limit or define the disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there. Other implementations and advantages may be apparent to those skilled in the art in light of the descriptions and drawings in this specification.

For a better understanding of the various described implementations, reference should be made to the Detailed Description below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures. Like reference numerals refer to corresponding parts throughout the drawings.

Reference will now be made in detail to specific embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth in order to assist in understanding the subject matter presented herein. But it will be apparent to one of ordinary skill in the art that various alternatives may be used without departing from the scope of claims and the subject matter may be practiced without these specific details.

<FIG> is a block diagram of an example system module <NUM> in a typical electronic device, in accordance with some implementations. System module <NUM> in this electronic device includes at least a system on a chip (SoC) <NUM> having one or more processors, memory modules <NUM> for storing programs, instructions and data, an input/output (I/O) controller <NUM>, one or more communication interfaces such as network interfaces <NUM>, and one or more communication buses <NUM> for interconnecting these components. In some implementations, I/O controller <NUM> allows SoC <NUM> to communicate with an I/O device (e.g., a keyboard, a mouse or a touch screen) via a universal serial bus interface. In some implementations, network interfaces <NUM> includes one or more interfaces for Wi-Fi, Ethernet and Bluetooth networks, each allowing the electronic device to exchange data with an external source, e.g., a server or another electronic device. In some implementations, communication buses <NUM> include circuitry (sometimes called a chipset) that interconnects and controls communications among various system components included in system module <NUM>.

In some implementations, memory modules <NUM> include high-speed random access memory, such as DRAM, SRAM, DDR RAM or other random access solid state memory devices. In some implementations, memory modules <NUM> include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some implementations, memory modules <NUM>, or alternatively the non-volatile memory device(s) within memory modules <NUM>, include a non-transitory computer readable storage medium. In some implementations, memory slots are reserved on system module <NUM> for receiving memory modules <NUM>. Once inserted into the memory slots, memory modules <NUM> are integrated into system module <NUM>.

In some implementations, system module <NUM> further includes one or more components selected from:.

It is noted that communication buses <NUM> also interconnect and control communications among various system components including components <NUM>-<NUM>.

One skilled in the art knows that other non-transitory computer readable storage media can be used, as new data storage technologies are developed for storing information in the non-transitory computer readable storage media in the memory modules <NUM> and in SSDs <NUM>. These new non-transitory computer readable storage media include, but are not limited to, those manufactured from biological materials, nanowires, carbon nanotubes and individual molecules, even though the respective data storage technologies are currently under development and yet to be commercialized.

In some implementations, SoC <NUM> is implemented in a semiconductor package including one or more integrated circuits, and each integrate circuit integrates a subset of: one or more microprocessor or CPU cores, memory, input/output ports and secondary storage on a single substrate. PMIC <NUM> is also implemented in a semiconductor package including one or more integrated circuits each of which is formed on a single substrate. SoC <NUM> is configured to receive one or more internal supply voltages (also called rail voltages) provided by PMIC <NUM> via one or more power rails. In some implementations, both SoC <NUM> and PMIC <NUM> are mounted on a main logic board, e.g., on two distinct areas of the main logic board, and electrically coupled to each other via conductive wires formed in the main logic board. This arrangement introduces parasitic effects and electrical noise that could compromise performance of the SoC, e.g., cause a voltage drop at an internal supply voltage. Alternatively, in accordance with various implementations described below, semiconductor dies of SoC <NUM> and PMIC <NUM> are vertically packaged in an integrated semiconductor device <NUM> (e.g., in <FIG>), such that they are electrically coupled to each other via electrical connections that are not formed in the main logic board. Such vertical arrangement of the semiconductor dies of SoC <NUM> and PMIC <NUM> reduces a length of electrical connections between SoC <NUM> and PMIC <NUM> and avoids performance degradation caused by routing conductive wires on the main logic board.

In some implementations, a generic PMIC <NUM> is configured to drive different types of SoC <NUM> in different types of electronic devices. Regardless of whether PMIC <NUM> and SoC <NUM> are arranged side by side or vertically, PMIC <NUM> occupies the same footprint with respect to the main circuit board, while SoC <NUM> may have a distinct footprint based on the electronic modules integrated therein. PMIC <NUM> includes a plurality of voltage regulator units that are arranged in a field programmable array. The plurality of voltage regulator units are identical to each other, or includes more than one type of voltage regulator units. In a specific electronic device, control signals are determined based on rail voltages and rail currents of power rails required to power SOC <NUM> and other electronic modules, if any. For each of these power rails, a corresponding control signal is used to select a subset of voltage regulator units in the field programmable array of PMIC <NUM>, and the selected voltage regulator units provide a rail current at a rail voltage to the respective power rail collectively. As such, PMIC <NUM> is reconfigured by these control signals to provide the rail voltages and currents to the power rails of SoC <NUM>, and each voltage regulator unit in a plurality of configurable voltage regulators in PMIC <NUM> is either redundant or selected to drive one of the power rails by one of the control signals.

<FIG> is a cross sectional view of an integrated semiconductor device <NUM> integrating an SoC die <NUM> and a PMIC die <NUM>, in accordance with some implementations. Semiconductor device <NUM> integrates at least one SoC die <NUM> and at least one PMIC die <NUM> in a semiconductor package, and includes at least a package substrate <NUM> having a first surface 124A and a second surface 124B that is opposite to first surface 124A. SoC die <NUM> is disposed on first surface 124A of package substrate <NUM>, and PMIC die <NUM> is coupled to second surface 124B of package substrate <NUM>. In some implementations, a first interposer <NUM> is disposed between SoC die <NUM> and first surface 124A of package substrate <NUM>. In some implementations, a second interposer <NUM> is disposed between PMIC die <NUM> and second surface 124B of package substrate <NUM>.

Package substrate <NUM> further includes a plurality of first via interconnects <NUM>, and PMIC die <NUM> is electrically coupled to SoC die <NUM> via the plurality of first via interconnects <NUM> of package substrate <NUM>. Specifically, PMIC die <NUM> includes a plurality of DC connections <NUM> configured to output a plurality of rail voltages, provided to power rails. When PMIC die <NUM> is mounted on second surface 124B of package substrate <NUM>, DC connections <NUM> are electrically coupled to the plurality of first via interconnects <NUM> of package substrate <NUM>. In some implementations, SoC die <NUM> includes a plurality of power connections <NUM> configured to receive the plurality of rail voltages via the plurality of first via interconnects <NUM> of package substrate <NUM>. As such, PMIC die <NUM> is configured to provide DC power (i.e., rail voltages and rail current of power rails) to SoC die <NUM> via DC connections <NUM> of PMIC die <NUM>, power connections <NUM> of SoC die <NUM>, and first via interconnects <NUM> of package substrate <NUM>. Further, by using very low impedance DC connections <NUM>, the quality of the DC power provided PMIC die <NUM> to SoC die <NUM> is substantially improved relative to systems in which PMIC die <NUM> and SoC die <NUM> are separately packaged and positioned side by side on a main circuit board.

In some implementations, a power management interface on PMIC die <NUM> is controlled by a master power management interface of SoC die <NUM>, e.g., which includes a system controller <NUM> in <FIG> and <FIG>, and configured to receive digital power control signals from SoC die <NUM>. A subset of first via interconnects <NUM> is configured to transfer digital power control signals from SoC die <NUM> to PMIC die <NUM>.

In some implementations, integrated semiconductor device <NUM> further includes a cover <NUM> coupled to first surface 124A of package substrate <NUM>. Cover <NUM> is configured to conceal SoC die <NUM> and at least part of first surface 124A of package substrate <NUM>, thereby protecting SoC die <NUM> and at least part of first surface 124A. In some implementations, semiconductor device <NUM> further includes a socket substrate <NUM>. Socket substrate <NUM> has a third surface 138A facing second surface 124B of package substrate <NUM>. Package substrate <NUM> is electrically coupled to socket substrate <NUM> via a plurality of electrical connectors <NUM>. Specifically, second surface 124B of package substrate <NUM> includes a first area (e.g., a central area) to which PMIC die <NUM> is mechanically coupled and a second area (e.g., a peripheral area) where the plurality of electrical connectors <NUM> are located. In some implementations, third surface 138A of socket substrate <NUM> is substantially flat, and PMIC die <NUM> is disposed between second surface 124B of package substrate <NUM> and third surface 138A of socket substrate <NUM>. Alternatively, in some implementations, socket substrate <NUM> includes a recessed portion <NUM> that is formed on third surface 138A and configured to receive PMIC die <NUM> when PMIC die <NUM> is mechanically and electrically coupled to second surface 124B of package substrate <NUM>. In some situations, PMIC die <NUM> is suspended in recessed portion <NUM>, i.e., separated from a bottom surface of recessed portion <NUM> by an air gap. Alternatively, in some situations, PMIC die <NUM> comes into contact with the bottom surface of recessed portion <NUM> directly or via an intermediate layer (e.g., an adhesive layer, a thermal spreader layer, or a layer that is both adhesive and a thermal spreader).

In some implementations, SoC die <NUM> and PMIC die <NUM> are vertically arranged in semiconductor device <NUM>. Power connections <NUM> of SoC die <NUM> and DC connections <NUM> of PMIC die <NUM> are aligned and positioned in proximity to each other, thereby reducing parasitic resistance and capacitance coupled to each power rail that provides a rail voltage to SoC die <NUM>. It is noted that in some implementations, a plurality of PMIC dies <NUM> can be disposed in recessed portion <NUM> of socket substrate <NUM> and electrically coupled to one or more SoC dies <NUM> disposed on first surface 124A of package substrate <NUM>. For example, two PMIC dies <NUM> are disposed in recessed portion <NUM> of socket substrate <NUM> to power four SoC dies <NUM> collectively. One of SoC dies <NUM> optionally corresponds to a microprocessor or CPU core or a cluster of microprocessor or CPU cores (e.g., a processor <NUM> or a processing cluster <NUM> in <FIG>).

Additionally, in some implementations of this application, PMIC die <NUM> includes a field programmable array of voltage regulators that is configurable by control signals to drive different types of SoC dies <NUM>. In some situations, the same PMIC die <NUM>, package substrate <NUM>, and socket substrate <NUM> are used to support the different types of SoC dies <NUM>. Recessed portion <NUM> formed on socket substrate <NUM> has a fixed size to accommodate the same PMIC die <NUM>, and first via interconnects <NUM> that pass through the body of package substrate <NUM> have fixed locations. Alternatively, in some situations, while footprint sizes of package substrate <NUM> and socket substrate <NUM> are varied for the different types of SoC dies, the same PMIC die <NUM> allows recessed portion <NUM> and first via interconnects <NUM> of package substrate <NUM> to remain unchanged, thereby avoiding custom designing PMIC die <NUM> and the entire package for each individual type of SoC die <NUM>. As such, application of the field programmable array of voltage regulators in PMIC die <NUM> simplifies an assembly process and enhances cost efficiency of the semiconductor device <NUM>.

<FIG> is a block diagram of an example electronic device <NUM> having one or more processing clusters <NUM> (e.g., first processing cluster <NUM>-<NUM>, Mth processing cluster <NUM>-M), in accordance with some implementations. Electronic device <NUM> includes an SoC <NUM>, a memory <NUM>, and a PMIC <NUM>. The SoC <NUM> includes the one or more processing clusters <NUM>, a system controller <NUM>, a system cache <NUM>, and an SoC interface <NUM>. The SoC interface <NUM> is interconnect architecture that facilitates data and control transmission across all linked components, i.e., communication between a subset of the processing clusters <NUM>, system controller <NUM>, system cache <NUM>, memory <NUM>, and PMIC <NUM>. The SoC interface <NUM> has a shared bus configuration or a point-to-point fabric configuration.

Each processing cluster <NUM> includes one or more processors (also called processing cores) <NUM>, a cluster cache <NUM>, a bus interface <NUM>, and a power management processor <NUM>. Cluster cache <NUM> is coupled to one or more processors <NUM>, and maintains one or more request queues for one or more processors <NUM>. In some implementations, each processor <NUM> further includes a core cache (not shown in <FIG>) that is optionally split into an instruction cache and a data cache, and the core cache stores instructions and data that can be immediately executed by the respective processor <NUM>. In an example, first processing cluster <NUM>-<NUM> includes first processor <NUM>-<NUM>,. , N-th processor <NUM>-N, and first cluster cache <NUM>-<NUM>, where N is an integer greater than <NUM>. In some implementations, SOC <NUM> only includes a single processing cluster <NUM>-<NUM>. Alternatively, in some implementations, SOC <NUM> includes at least an additional processing cluster <NUM>, e.g., M-th processing cluster <NUM>-M. M-th processing cluster <NUM>-M includes a first processor,. , an N'-th processor, and an M-th cluster cache, where N' is an integer greater than <NUM>.

In some implementations, the one or more processing clusters <NUM> are configured to provide a central processing unit for an electronic device and are associated with a hierarchy of caches. For example, the hierarchy of caches includes three levels that are distinguished based on their distinct operational speeds and sizes. For the purposes of this application, a reference to "the speed" of a memory (including a cache memory) relates to the time required to write data to or read data from the memory (e.g., a faster memory has shorter write and/or read times than a slower memory), and a reference to "the size" of a memory relates to the storage capacity of the memory (e.g., a smaller memory provides less storage space than a larger memory). The core cache, cluster cache <NUM>, and system cache <NUM> correspond to a first level (L1) cache, a second level (L2) cache, and a third level (L3) cache, respectively. Each core cache holds instructions and data to be executed directly by a respective processor <NUM>, and has the fastest operational speed and smallest size among the three levels of memory. For each processing cluster <NUM>, the cluster cache <NUM> is slower operationally than the core cache and bigger in size, and holds data that is more likely to be accessed by processors <NUM> of respective processing cluster <NUM>. The cache <NUM> is shared by the plurality of processing clusters <NUM>, and bigger in size and slower in speed than each core cache and cluster cache <NUM>.

The processing clusters <NUM> issue prefetch requests to extract the instructions and data to be held by each core cache from the cluster cache <NUM>, cache <NUM> or memory <NUM>. If the prefetch requests are satisfied by the cluster cache <NUM>, the cluster cache <NUM> provides the instructions and data to the respective core cache for execution by the processors <NUM>. Conversely, if the prefetch requests are not satisfied by the cluster cache <NUM>, the prefetch requests are sent to the cache <NUM> via the bus interface <NUM> to extract the instructions and data. If the prefetch requests are satisfied by the cache <NUM>, the cache <NUM> provides the instructions and data via the bus interface <NUM> to the cluster cache <NUM>, which further passes the instructions and data to the respective core cache for execution by the processors <NUM>. Conversely, if the prefetch requests are not satisfied by the cache <NUM>, the prefetch requests are sent to the memory <NUM> external to the SoC <NUM> to extract the instructions and data. The memory <NUM> provides the instructions and data to the cache <NUM>, which passes the instructions and data to the cluster cache <NUM> and then to the respective core cache.

Additionally, the processing clusters <NUM> issue memory access requests to write data into and read data from the cluster cache <NUM>, cache <NUM> or memory <NUM> during normal operation of each processing cluster <NUM>. Each memory access request is passed sequentially from the cluster cache <NUM>, cache <NUM>, and memory <NUM>, until the respective memory access request reaches a target cache or memory. Data to be written into the target cache or memory are passed sequentially from the cluster cache <NUM>, cache <NUM>, and memory <NUM>, until the respective data reach the target cache or memory. In contrast, data read from the target cache or memory are provided directly to the respective core caches to be used by the processors <NUM>.

For each processing cluster <NUM>, the power management processor <NUM> manages power consumption of the respective processing cluster <NUM> and performs debugging of the respective processing cluster <NUM>. Operations of the processing clusters <NUM>, PMIC <NUM>, cache <NUM>, and memory <NUM> consume power and create heat on the electronic device <NUM>. The power management processor <NUM> is applied to manage power consumptions of the electronic device <NUM> from a firmware level. Specifically, for each respective processing cluster <NUM>, the power management processor <NUM> is configured to obtain performance information about the one or more processors <NUM>, execute power instructions to transition a first processor <NUM>-<NUM> from a first performance state (also called P-state) PS1 to a second performance state PS2, and execute one or more debug instructions to perform debugging of a respective processor (e.g., the first processor <NUM>-<NUM> or a different processor) of the one or more processors <NUM> of the respective processing cluster <NUM>. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors <NUM> in the one or more processors <NUM>. In some embodiments, the one or more debug instructions are executed to perform debugging of the first processor <NUM>-<NUM> when the first processor operates at the second performance state S2.

In some implementations, the power management processor <NUM> manages power performance jointly with the system controller <NUM>, which is configured to define power allocations to the one or more processing clusters <NUM>. Optionally, the system controller <NUM> is external to any of the one or more processing clusters <NUM> of the electronic device, e.g., the first processing cluster <NUM>-<NUM>. Optionally, the system controller <NUM> define the power allocations of all processing clusters <NUM>, and however, is disposed internal within one of the one or more processing clusters <NUM>, (e.g., the first processing cluster <NUM>-<NUM>). The SoC <NUM> is further coupled to a PMIC <NUM>. The power management processor <NUM> of each processing cluster <NUM> is configured to communicate with the PMIC <NUM> having one or more voltage regulators, thereby enabling the respective processing cluster <NUM> to be powered by one or more power rails driven by the voltage regulators of the PMIC <NUM>. By these means, the power management processor <NUM> and system controller <NUM> form a hierarchical power management system that is configured to manage power consumption of a multiprocessor electronic device <NUM> from both a firmware level and a system level.

<FIG> is a block diagram of a first processing cluster <NUM>-<NUM> including one or more processors <NUM> and a power management processor <NUM>, in accordance with some implementations. Optionally, the one or more processors <NUM> only includes a single processor <NUM>-<NUM>. Optionally, the one or more processors <NUM> includes two or more processors <NUM>-<NUM>,. , and <NUM>-N, where N is a positive integer greater than <NUM>. The power management processor <NUM> is coupled to the one or more processors <NUM>, and is configured to manage power consumption and/or perform debugging of each processor <NUM> of the first processing cluster <NUM>-<NUM>. Cluster cache <NUM> is coupled to one or more processors <NUM>, and configured to maintain one or more request queues for one or more processors <NUM>, provide instructions and data to a respective core cache of each processor <NUM> for execution by the respective processor <NUM>, and fetch missing instructions or data from a system cache <NUM> and/or memory <NUM>. The bus interface <NUM> is coupled to one or more of the cluster cache <NUM>, power management processor <NUM>, one or more processors <NUM>, and configured to facilitate at least communication with external components, e.g., a different processing cluster <NUM>, system controller <NUM>, system cache <NUM>, memory <NUM>, and PMIC <NUM>.

In some implementations, the power management processor <NUM> obtains performance information <NUM> about a plurality of processors <NUM>-<NUM>,. , and <NUM>-N. The performance information <NUM> includes activity levels (e.g., instructions per clock cycle), energy consumption, temperature measurements, counts of performance limit breaches, and/or throttling instructions (e.g., clock throttling instructions) for one or more of the plurality of processors <NUM>. In some implementations, a count of performance limit breach is defined as a number of times a respective performance limit was breached in a respective time window, such as the number of times a processor <NUM> breached an overcurrent limit. For example, a current of a processor <NUM>-<NUM> is sampled <NUM>, and a count of current limit breach corresponds to a number of samples for which a respective current limit was reached in every <NUM> milliseconds. The overcurrent limit is <NUM>% for every <NUM> milliseconds. Thus, if the count of current limit breach exceeds <NUM> samples, the overcurrent limit is breached, and the processor <NUM> is determined to be operating at an overcurrent condition.

In accordance with the performance information <NUM> collected from different processors <NUM>, the power management processor <NUM> executes first instructions <NUM>-<NUM> to transition a first processor <NUM>-<NUM> of the plurality of processors <NUM> from a first performance state PS1 to a second performance state PS2, independently of respective performance states of other processors in the plurality of processors <NUM>. The second performance state PS2 is different from the first performance state PS1. In some implementations, the performance state of other processors <NUM> are not changed in response to the first instructions <NUM>-<NUM>, although the performance state of other processors <NUM> may be changed in coordination with changing the performance state of the first processor <NUM>-<NUM> to optimize performance states across the plurality of processors <NUM>, for example to satisfy an overall power allocation for the first processing cluster <NUM>-<NUM>. In some implementations, any instructions <NUM> to transition a performance state of a respective processor of the plurality of processors <NUM> are executed by the power management processor <NUM> of the first processing cluster <NUM>-<NUM>, and not by any processor <NUM> of the plurality of processors <NUM>.

In some implementations, the obtained performance information <NUM> includes temperatures of one or more processors <NUM> (e.g., the first processor <NUM>-<NUM>). In accordance with the performance information indicating an increase in a temperature of the first processor <NUM>-<NUM>, the power management processor <NUM> reduces power consumptions of the first processor <NUM>, thereby reducing the temperature of the first processor <NUM>-<NUM>. Stated another way, at a current time, the temperature of the first processor <NUM>-<NUM> is measured to be higher than a temperature of the first processor <NUM>-<NUM> previously received, be higher than a predefined temperature threshold, or increase at a rate faster than a predefined temperature increase rate. In response, the power management processor <NUM> controls the first processor <NUM>-<NUM> to transition to the second performance state PS2 that is associated with lower power consumption than the first performance state PS1. In an example, the second performance state PS2 is associated with a lower clock frequency <NUM>-<NUM> and/or a lower supply voltage <NUM>-<NUM>. Conversely, in some implementations, in accordance with the performance information indicating a drop in a temperature of the first processor <NUM>-<NUM> (e.g., the temperature is lower than the same or a lower predefined temperature threshold), the power management processor <NUM> increases power consumption of the first processor <NUM>-<NUM> by enabling the second performance state PS2 that is associated with a higher clock frequency <NUM>-<NUM> and/or a higher supply voltage <NUM>-<NUM> than the first performance state PS1.

In some implementations associated with performance breaches, in accordance with the performance information <NUM> indicating a respective number of performance limit breaches in a respective time period that exceeds a threshold number of performance limit breaches for the respective time period, the second performance state PS2 is a state that is associated with lower power consumption than the first performance state PS1. For example, if it is determined that the count of current limit breach exceeds a first overcurrent limit (e.g., <NUM>% of all samples) within <NUM> milliseconds, the power management processor <NUM> reduces power consumption of the first processor <NUM>-<NUM> by enabling the second performance state PS2 that is associated with a lower clock frequency <NUM>-<NUM> and/or a lower supply voltage <NUM>-<NUM> than the first performance state PS1. Conversely, in some implementations, in accordance with the performance information <NUM> indicating the respective number of performance limit breaches in the respective time period that drops below the same or a distinct threshold number of performance limit breaches for the respective time period, the second performance state PS2 is a state that is associated with higher power consumption than the first performance state PS1. For example, if it is determined that the count of current limit breach drops below a second overcurrent limit (e.g., <NUM>% of all samples) within a minute, the power management processor <NUM> increases power consumption of the first processor <NUM>-<NUM> by enabling the second performance state PS2 that is associated with a higher clock frequency <NUM>-<NUM> and/or a higher supply voltage <NUM>-<NUM> than the first performance state PS1.

Additionally, the power management processor <NUM> is configured to execute one or more debug instructions to perform debugging of a respective processor of the plurality of processors <NUM>, e.g., based on the obtained performance information <NUM>. The respective processor <NUM> is optionally the first processor <NUM>-<NUM> that executes the first instructions <NUM>-<NUM> or any other processor <NUM> different from the first processor <NUM>-<NUM>. Specifically, in some embodiments, the one or more debug instructions are executed to perform debugging of the first processor <NUM>-<NUM> when the first processor operates at the second performance state S2. In some situations, the power management processor <NUM> performs debugging of the respective processor <NUM> while the respective processor <NUM> is executing an application. In some implementations, the power management processor <NUM> includes a debugging module <NUM> dedicated to executing debug instructions for debugging any of the plurality of processors <NUM>. Each processor <NUM> optionally includes a respective debugging unit <NUM> configured to perform debugging of the respective processor <NUM> jointly with the debugging module <NUM> of the power management processor <NUM> in accordance with the one or more corresponding debug instructions.

In some implementations, transitioning the first processor <NUM>-<NUM> from the first performance state PS1 to the second performance state PS2 includes modifying a supply voltage <NUM>-<NUM> provided to the first processor <NUM>-<NUM> independently of respective voltages <NUM> provided to other processors <NUM> in the plurality of processors <NUM>. Additionally and alternatively, in some implementations, transitioning the first processor <NUM>-<NUM> from the first performance state PS1 to the second performance state PS2 includes modifying a clock frequency <NUM>-<NUM> of the first processor <NUM>-<NUM> independently of respective clock frequencies <NUM> of other processors <NUM> in the plurality of processors <NUM>.

In some implementations, the power management processor <NUM> is configured to execute second instructions <NUM>-<NUM> to transition a second processor <NUM>-<NUM> of the plurality of processors <NUM> from a third performance state PS3 to a fourth performance state PS4 in accordance with the obtained performance information <NUM>, independently of respective performance states PS of other processors in the plurality of processors <NUM>. The second processor <NUM>-<NUM> is different from the first processor <NUM>-<NUM>. The second instructions <NUM>-<NUM> are different from the first instructions <NUM>-<NUM>, and the third performance state PS3 is different from the fourth performance state PS4. In some scenarios, the third performance state PS3 is different from the first performance state PS1. In some scenarios, the fourth performance state PS4 is different from the second performance state PS2.

In some implementations, each processor <NUM> is operable at a plurality of P-states each of which corresponds to predefined set of power and performance settings (e.g., voltage supplies, clock frequency). For example, a high-performance P-state of a processor <NUM> reflects an absolute maximum performance the processor <NUM> may reach, assuming ideal conditions. This P-state does not sustain for long durations and may only be achievable by forcing other processors <NUM> or memory <NUM> into a specific state (e.g., an idle state, a standby state). A nominal P-state of a processor <NUM> reflects a maximum sustained performance level of the processor <NUM>, assuming ideal operating conditions. In the absence of an external constraint (power, thermal, etc.), this is the performance level that the SoC-based electronic device maintains continuously. In some implementations, all processors <NUM> sustain their nominal P-states simultaneously. A guaranteed P-state of a processor <NUM> reflects a current maximum sustained performance level of the processor <NUM>, taking into account all known external constraints (power budgeting, thermal constraints, DC or AC power source, etc.). In some implementations, all processors <NUM> sustain their guaranteed P-states simultaneously. The guaranteed P-state is required to fall in a performance range between a lowest performance level and a nominal performance level that corresponds to the nominal P-state, inclusive. In some situations, the guaranteed P-state is updated once per second to reflect thermal and power constraints.

In some implementations, the performance information <NUM> indicates a third processor <NUM>-<NUM> of the plurality of processors <NUM>, different from the first processor <NUM>-<NUM>, transitioning from an off state to an on state. The power management processor <NUM> executes the first instructions <NUM>-<NUM> to reduce power consumption of the first processor <NUM>-<NUM> to accommodate an increase of power consumption by the third processor <NUM>-<NUM>. The second performance state PS2 is a state that is associated with lower power consumption than the first performance state PS1. In an example, the first performance state PS1 is an active power state, and the second performance state PS2 is a standby or idle power state. In another example, both of the performance states PS1 and PS2 are active power states, and the second performance state PS2 is a lower power state than the first performance state PS1, e.g., has a lower clock frequency <NUM>-<NUM> and/or a lower supply voltage <NUM>-<NUM> than the first performance state PS1.

Conversely, in some implementations, the performance information <NUM> indicates a fourth processor <NUM>-N of the plurality of processors <NUM>, different from the first processor <NUM>-<NUM>, transitioning from an on state to an off state. The power management processor <NUM> executes the first instructions <NUM>-<NUM> to increase power consumption of the first processor <NUM>-<NUM> to balance a decrease of power consumption by the fourth processor <NUM>-N. The second performance state PS2 is a state that is associated with higher power consumption than the first performance state PS1. In an example, the first performance state PS1 is a standby or idle power state, and the second performance state PS2 is an active power state. In another example, both of the performance states PS1 and PS2 are active power states, and the second performance state PS2 is a higher power state than the first performance state PS1, e.g., has a higher clock frequency <NUM>-<NUM> and/or a higher supply voltage <NUM>-<NUM> than the first performance state PS1.

<FIG> is a power management environment <NUM> in which a first processing cluster <NUM>-<NUM> is coupled to a system controller <NUM>, in accordance with some implementations. As shown in <FIG>, an electronic device <NUM> includes one or more processing clusters including the first processing cluster <NUM>-<NUM>. The first processing cluster <NUM>-<NUM> includes a plurality of processors <NUM>, a cluster cache <NUM>, a power management processor <NUM>, and a bus interface <NUM>. The system controller <NUM> is coupled to the power management processor <NUM> of the first processing cluster <NUM>-<NUM>, e.g., via the bus interface <NUM>, and configured to manage power consumption and perform debugging of the first processing cluster <NUM>-<NUM> jointly with power management processor <NUM> of the first processing cluster <NUM>-<NUM>. Optionally, the system controller <NUM> is external to any of the one or more processing clusters <NUM> of the electronic device, i.e., external to this first processing cluster <NUM>-<NUM> in <FIG>. Optionally, the system controller <NUM> define the power allocations of all processing clusters <NUM>, and however, is disposed internal within one of the one or more processing clusters <NUM> (e.g., the first processing cluster <NUM>-<NUM>).

Specifically, in some implementations, the power management processor <NUM> is configured to provide cluster performance information <NUM> to the system controller <NUM> and receive, from the system controller <NUM>, a first power allocation 404A for the first processing cluster <NUM>-<NUM>. The first power allocation 404A is optionally determined by the system controller <NUM> based on the cluster performance information <NUM> and similar information from other processing clusters <NUM>. In some situations, the cluster performance information <NUM> includes a subset or all of the performance information <NUM> about the plurality of processors <NUM> of the first processing cluster <NUM>-<NUM>. Alternatively, in some situations, a subset of the cluster performance information <NUM> is derived based on the performance information <NUM> about the plurality of processors <NUM> of the first processing cluster <NUM>-<NUM>. In accordance with the first power allocation 404A for the first processing cluster <NUM>-<NUM>, the power management processor <NUM> assigns respective performance states PS to the plurality of processors <NUM>, e.g., assigns the first or second performance state P1 or P2 to the first processing unit <NUM>-<NUM> in <FIG>. The total power consumption of the plurality of processors <NUM> in the first processing cluster <NUM>-<NUM> does not exceed the first power allocation 404A, as long as the first processing cluster <NUM>-<NUM> is assigned the first power allocation 404A. For example, the transition of the first processor <NUM>-<NUM> to the second performance state PS2 is subject to the first power allocation 404A.

The system controller <NUM> manages systemwide performance and power consumption by assigning a respective power allocation <NUM> to each of the plurality of the processing clusters <NUM>. For each processing cluster <NUM>, the respective power allocation <NUM> is sometimes called a power budget, and specifies a maximum amount of power that a given processing cluster may consume. In some implementations, the plurality of the processing clusters <NUM>, cache <NUM>, and memory <NUM> are grouped to a plurality of power domains, and the system controller <NUM> assigns a respective power allocation to each of the plurality of power domain. For a power domain including a first processing cluster <NUM>-<NUM>, the respective power allocation to the power domain is optionally divided and assigned to the first processing cluster <NUM>-<NUM>, or utilized within the power domain and at least partially subject to a control of the power management processor <NUM> of the first processing cluster <NUM>-<NUM> that is included in the power domain.

In some implementations, after the performance information <NUM> is collected by the power management processor <NUM> of the first processing cluster <NUM>-<NUM>, the power management processor <NUM> and the system controller <NUM> jointly control a power performance state of a first processor <NUM>-<NUM> within the first processing cluster <NUM>-<NUM>. For the power management processor <NUM>, a first amount of time is detected between a time corresponding to the power management processor <NUM> obtaining the performance information <NUM> and a time corresponding to the first processor <NUM>-<NUM> transitioning from the first performance state P1 to the second performance state P2 in response to the power management processor <NUM> executing the first instructions <NUM>-<NUM> to transition performance state of the first processor <NUM>-<NUM>. For the system controller <NUM>, a second amount of time is detected between a time corresponding to the system controller <NUM> obtaining the performance information <NUM> (e.g., submitted in the cluster performance information <NUM>) and a time corresponding to the first processor <NUM>-<NUM> transitioning from the first performance state PS1 to the second performance state PS2 in response to the system controller <NUM> executing instructions to transition performance state of the first processor <NUM>-<NUM>. The first amount of time is less than the second amount of time. Stated another way, the power management processor <NUM> controls performance state transitions of the first processor <NUM>-<NUM> existing in the same first processing cluster <NUM>-<NUM> at a rate faster than the system controller <NUM>.

In some examples, transitioning a performance state of a processor <NUM> in response to instructions from the power management processor <NUM> local to the first processing cluster <NUM>-<NUM> that includes the processor <NUM> is faster than transitioning the performance state of the same processor <NUM> in response to instructions from the system controller <NUM>, by a factor of at least <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or other factor. This is due at least partially to faster communication between the processors <NUM> in the first processing cluster <NUM>-<NUM> and the local power management processor <NUM> than between the processors <NUM> in the first processing cluster <NUM>-<NUM> and the system controller <NUM>.

In some implementations, the power management processor <NUM> receives, from the system controller <NUM>, a second power allocation 404B for the first processing cluster <NUM>-<NUM>, e.g., after receiving the first power allocation 404A and after transitioning the first processor <NUM>-<NUM> to the second performance state PS2. The second power allocation 404B is different from the first power allocation 404A. The power management processor <NUM> determines respective performance states of the plurality of processors <NUM> of the first processing cluster <NUM>-<NUM> in accordance with the second power allocation 404B. The determined respective performance state of the first processor <NUM>-<NUM> is different from the second performance state PS2. The power management processor <NUM> executes instructions <NUM>' to transition the plurality of processors <NUM> to the respective performance states, e.g., for a subset of the respective processors <NUM> whose determined respective performance states are different from their current performance state. The instructions <NUM>' are executed to transition the first processor <NUM>-<NUM> from the second performance state PS2 to the determined respective performance state. In some situations, the system controller <NUM> assigns a lower power allocation to the first processing cluster <NUM>-<NUM>, which is less than a total power consumption of the processors <NUM> in the first processing cluster <NUM>-<NUM> based on their currently assigned performance states. In response, the power management processor <NUM> reduces the total power consumption of the first processing cluster <NUM>-<NUM> by assigning lower-power performance states to at least some of the processors <NUM> in the first processing cluster <NUM>-<NUM>.

<FIG> are structures of power management data <NUM> and <NUM> in a first processing cluster <NUM>-<NUM> and a system controller <NUM>, in accordance with some implementations, respectively. The power management data <NUM> are associated with operation of the power management processor <NUM> that is internal to the first processing cluster <NUM>-<NUM> and configured to manage power consumption and perform debugging of the first processing cluster <NUM>-<NUM>. The power management data <NUM> include information of a power state and performance information <NUM> of each processor <NUM> of a subset of the first processing cluster <NUM>-<NUM>. In some implementations, the power management data <NUM> further includes a respective power allocation <NUM> and comprehensive performance information <NUM> of the first processing cluster <NUM>-<NUM>, and the comprehensive performance information <NUM> is derived from the performance information <NUM> of the processors of the first processing cluster <NUM>-<NUM>. An example comprehensive performance information <NUM> includes a temperature increase rate of a processor <NUM>.

For each processor <NUM>, the power state includes information of one or more power supplies <NUM> and a clock frequency <NUM>. In some implementations, the power state is selected from a plurality of predefined P-states each of which corresponds to predefined set of power and performance settings (e.g., voltage supplies, clock frequency). Examples of the defined P-states include, but are not limited to, a high-performance P-state, a nominal P-state, a guaranteed P-state, and a standby or idle P-state. In some implementations, the power state is defined based on a combination of the one or more power supplies <NUM> and a clock frequency <NUM>. Each power supply <NUM> is dynamically selected from a predefined number of voltage level (e.g., <NUM>. 8V, 2V, <NUM>. 2V, and <NUM>. 4V) or defined in a range of voltage levels (e.g., <NUM>-<NUM>. 4V) based on the performance information <NUM>. Each clock frequency <NUM> is dynamically selected from a predefined number of frequencies (e.g., <NUM>, <NUM>, and <NUM>) or defined in a range of frequency (e.g., <NUM>-<NUM>) based on the performance information <NUM>. In DVFS, the voltage supplies <NUM> and clock frequency <NUM> are scaled dynamically to optimize resource utilization and conserve power consumption for different processor operations.

For each processor <NUM>, the performance information <NUM> includes one or more of: one or more activity levels <NUM>, energy consumption <NUM>, a temperature <NUM>, one or more performance breach counts <NUM>, one or more performance breach limits <NUM>, a peak power throttling setting <NUM>, and DVFS settings <NUM>. An activity level <NUM> is defined as a number of instructions executed by the respective processor <NUM> during each clock cycle. A count of performance limit breach <NUM> is defined as a number of times a respective performance breach limit is reached within a respective time period, e.g., a number of times the respective processor <NUM> breaches an overcurrent limit). In an example, the throttling settings <NUM> define conditions under which throttling instructions (e.g., a clock throttling instruction) are issued.

In some implementations, in accordance with the performance information <NUM> indicating an increase in a temperature of the first processor <NUM>-<NUM>, the second performance state PS2 is a state that is associated with lower power consumption than the first performance state PS1. The performance information <NUM> includes a temperature <NUM> of the first processor <NUM>-<NUM> that is higher than a temperature <NUM> of the first processor <NUM>-<NUM> previously received. In some situations, when the temperature increases beyond a predefined temperature threshold or at a rate that is faster than a predefined temperature increase rate, the power management processor <NUM> executes the first instructions <NUM>-<NUM> to transition the first processor <NUM>-<NUM> from the first performance state PS1 to the second performance state PS2 that has a lower clock frequency and/or a lower voltage than the first performance state PS1.

In some implementations, in accordance with the performance information <NUM> indicating a decrease in a temperature <NUM> of the first processor, the second performance state PS2 is a state that is associated with higher power consumption than the first performance state PS1. The temperature <NUM> of the first processor <NUM>-<NUM> is lower than a temperature <NUM> of the first processor previously received. In some situations, when the temperature <NUM> decreases beyond the same or distinct predefined temperature threshold, the power management processor <NUM> executes the first instructions <NUM>-<NUM> to transition the first processor <NUM>-<NUM> from the first performance state PS1 to the second performance state PS2 that has a higher clock frequency and/or a higher voltage than the first performance state PS1.

In some implementations, in accordance with the performance information <NUM> indicating a respective number of performance limit breaches <NUM> in a respective time period that exceeds a threshold number of performance limit breaches for the respective time period, the second performance state PS2 is a state that is associated with lower power consumption than the first performance state PS1, setting a lower clock frequency and/or a lower voltage. The power management processor <NUM> identifies an overcurrent, overvoltage, overpower, or over-temperature condition in which the first processor <NUM>-<NUM> is excessively driven, and avoids such a condition by decreasing power consumption of the first processor <NUM>-<NUM>. Conversely, in some implementations, in accordance with the performance information <NUM> indicating a respective number of performance limit breaches <NUM> in a respective time period that drops beyond a distinct threshold number of performance limit breaches for the respective time period, the second performance state PS2 is a state that is associated with higher power consumption than the first performance state PS1, setting a higher clock frequency and/or a higher voltage. The power management processor <NUM> identifies an undercurrent, undervoltage, underpower, or under-temperature condition in which the first processor <NUM>-<NUM> is insufficiently driven, and compensates such a condition by increasing power consumption of the first processor <NUM>-<NUM>.

In some implementations, the power management processor <NUM> is configured to initialize one or more settings for the plurality of processors by modifying a default hardware state (e.g., of the DVFS settings <NUM>) of the electronic device <NUM> prior to any of the plurality of processors <NUM> executing application instructions of applications. For example, if a default hardware state of the first processor <NUM>-<NUM> is different from a preferred operating state, the power management processor <NUM> is configurable to execute software instructions to change the default hardware state (e.g., of the DVFS settings <NUM>) to the preferred operating state for the first processor <NUM>-<NUM> during the course of initializing the plurality of processors <NUM>, prior to the plurality of processors <NUM> executing any application instructions. This prevents the plurality of processors <NUM> from executing instructions while the incorrect default hardware state of the first processor <NUM>-<NUM> is in place. Initialization of the plurality of processors <NUM> of the first processing cluster <NUM>-<NUM> by the power management processor <NUM> is typically faster, often significantly so, than initialization by the system controller <NUM> or other controller, e.g., SoC, external to the first processing cluster <NUM>-<NUM>.

Referring to <FIG>, the power management data <NUM> are associated with operation of a system controller <NUM> that is external to the first processing cluster <NUM>-<NUM> and configured to manage power consumption and perform debugging of the plurality of processing clusters <NUM> on a system level. The power management data <NUM> include cluster performance information <NUM> collected from the plurality of processing clusters <NUM> and power allocations <NUM> to the plurality of processing clusters <NUM>. In some situations, the cluster performance information <NUM> includes a subset or all of the performance information <NUM> about the plurality of processors <NUM> of the first processing cluster <NUM>-<NUM>. Further, in some situations, the cluster performance information <NUM> further includes the comprehensive performance data <NUM> derived based on a subset or all of the performance information <NUM> about the plurality of processors <NUM> of the first processing cluster <NUM>-<NUM>.

The system controller <NUM> manages systemwide performance and power consumption, and provides or assigns a power allocation <NUM> to one or more of the plurality of the processing clusters <NUM> (e.g., each processing cluster <NUM>, each power domain including one or more processing clusters <NUM>). The power allocation <NUM> specifies a maximum amount of power that a given processing cluster <NUM> may consume, and is also called a power budget. For a first processing cluster <NUM>-<NUM>, the total power consumption of the plurality of processors <NUM> in the first processing cluster <NUM>-<NUM> does not exceed the first power allocation 404A to the first processing cluster <NUM>-<NUM>, as long as this first power allocation 404A is assigned to the first processing cluster <NUM>-<NUM>. For example, the transitioning of the first processor <NUM>-<NUM> of the first processing cluster <NUM>-<NUM> to the second performance state PS2 is subject to the first power allocation 404A to the first processing cluster <NUM>-<NUM>.

The system controller <NUM> collaborates with the power management processor <NUM> of each processing cluster <NUM> to manage power management and perform debugging of the processors <NUM> of the respective processing cluster <NUM> jointly. In some implementations, when the first processing cluster <NUM>-<NUM> has a first power allocation 404A and after the first processor <NUM>-<NUM> has transitioned to the second performance state PS2, the power management processor <NUM> of the processing cluster <NUM>-<NUM> receives, from the system controller <NUM>, a second power allocation 404B for the first processing cluster <NUM>-<NUM>. The second power allocation 404B is different from the first power allocation 404A. The power management processor <NUM> determines respective performance states of the plurality of processors <NUM> in accordance with the second power allocation 404B. The determined respective performance state of the first processor <NUM>-<NUM> is different from the second performance state PS2. The power management processor <NUM> of the processing cluster <NUM>-<NUM> executes instructions to transition the plurality of processors <NUM> of the processing cluster <NUM>-<NUM> to the respective performance states, particularly for respective processors <NUM> whose determined respective performance states are different from their current performance state). For example, additional instructions <NUM> are executed to transition the first processor <NUM>-<NUM> from the second performance state PS2 to the determined respective performance state. For example, the system controller <NUM> assigns a lower power allocation to the first processing cluster <NUM>-<NUM>, and the lower power allocation is less than a total power consumption of the processors <NUM> in the first processing cluster <NUM>-<NUM> based on their currently assigned performance states. The power management processor <NUM> reduces the total power consumption of the first processing cluster <NUM>-<NUM> by assigning lower-power performance states to at least some of the processors <NUM> in the first processing cluster <NUM>-<NUM>.

<FIG> and <FIG> illustrate a flow diagram of a method <NUM> of managing power consumption of an SoC-based electronic device <NUM>, in accordance with some implementations. The electronic device <NUM> includes a plurality of processing clusters <NUM> including a first processing cluster <NUM>-<NUM>. The first processing cluster <NUM>-<NUM> includes a plurality of processors <NUM> and a power management processor <NUM> distinct from the plurality of processors <NUM>. The method <NUM> is implemented by the power management processor <NUM> to manage power consumption and perform debugging of the first processing cluster <NUM>-<NUM>. The power management processor <NUM> obtains (<NUM>) performance information <NUM> about the plurality of processors <NUM>. In some implementations, the performance information <NUM> includes (<NUM>) activity levels <NUM>, energy consumption <NUM>, temperature measurements <NUM>, counts of performance limit breaches <NUM>, and/or throttling instructions (e.g., peak power throttling setting <NUM>) for one or more of the plurality of processors <NUM>.

The power management processor <NUM> executes (<NUM>) first instructions to transition a first processor <NUM>-<NUM> of the plurality of processors <NUM> from a first performance state PS1 to a second performance state PS2, different from the first performance state PS1, in accordance with the obtained performance information, independently of respective performance states of other processors <NUM> in the plurality of processors <NUM>. In some implementations, transitioning the first processor <NUM>-<NUM> from the first performance state PS1 to the second performance state PS2 includes (<NUM>) modifying a supply voltage <NUM>-<NUM> provided to the first processor <NUM>-<NUM> independently of respective voltages <NUM> provided to other processors <NUM> in the plurality of processors <NUM>. Additionally and alternatively, in some implementations, transitioning the first processor <NUM>-<NUM> from the first performance state PS1 to the second performance state PS2 includes (<NUM>) modifying a clock frequency <NUM>-<NUM> of the first processor <NUM>-<NUM> independently of respective clock frequencies <NUM> of other processors <NUM> in the plurality of processors <NUM>. In some implementations, in accordance with the performance information indicating (<NUM>) an increase in a temperature of the first processor <NUM>-<NUM>, the second performance state PS2 is a state that is associated with lower power consumption than the first performance state PS1. In some implementations, in accordance with the performance information indicating (<NUM>) a respective number of performance limit breaches in a respective time period that exceeds a threshold number of performance limit breaches for the respective time period, the second performance state PS2 is a state that is associated with lower power consumption than the first performance state PS1.

Additionally, the power management processor <NUM> executes (<NUM>) one or more debug instructions to perform debugging of a respective processor <NUM> of the plurality of processors <NUM>. In some implementations, the power management processor <NUM> executes.

(<NUM>) the one or more debug instructions to perform debugging of the respective processor of the plurality of processors <NUM> while the respective processor executes application instructions. In some embodiments, the one or more debug instructions are executed to perform debugging of the first processor <NUM>-<NUM> when the first processor operates at the second performance state S2. In some implementations, the first processing cluster <NUM>-<NUM> includes (<NUM>) a cluster cache <NUM> coupled to one or more of the plurality of processors <NUM> in the first processing cluster <NUM>-<NUM>, and the power management processor <NUM> performs the debugging of the respective processor using the cluster cache <NUM> of the first processing cluster <NUM>-<NUM>.

In some implementations, the power management processor <NUM> executes (<NUM>) second instructions <NUM>-<NUM> to transition a second processor <NUM>-<NUM> of the plurality of processors <NUM> from a third performance state PS3 to a fourth performance state PS4 in accordance with the obtained performance information <NUM>, independently of respective performance states of other processors <NUM> in the plurality of processors <NUM>.

In some implementations, in accordance with the performance information indicating a third processor <NUM>-<NUM> of the plurality of processors <NUM>, different from the first processor <NUM>-<NUM>, the power management processor <NUM> transitions (<NUM>) from an off state to an on state, the second performance state PS2 is a state that is associated with lower power consumption than the first performance state PS1. In some implementations, in accordance with the performance information indicating a fourth processor <NUM>-<NUM> of the plurality of processors <NUM>, different from the first processor <NUM>-<NUM>, the power management processor <NUM> transitions (<NUM>) from an on state to an off state, the second performance state PS2 is a state that is associated with higher power consumption than the first performance state PS1.

In some implementations, the device <NUM> includes a plurality of processing clusters <NUM> including the first processing cluster <NUM>-<NUM>. The power management processor <NUM> receives (628A), from a system controller <NUM> that is distinct from the plurality of processing clusters <NUM>, a first power allocation 404A for the first processing cluster <NUM>-<NUM> and assigns (628B) respective performance states to the plurality of processors <NUM>, including the first processor <NUM>-<NUM>, in accordance with the first power allocation 404A for the first processing cluster <NUM>-<NUM>. Further, in some implementations, the power management processor <NUM> assigns (<NUM>) the respective performance states to the plurality of processors <NUM> in accordance with the first power allocation 404A such that aggregate power consumption of the plurality of processors <NUM> in the first processing cluster <NUM>-<NUM> does not exceed the first power allocation 404A.

Additionally, in some implementations, a first amount of time is between a time corresponding to the power management processor <NUM> obtaining the performance information <NUM> and a time corresponding to the first processor <NUM>-<NUM> transitioning from the first performance state PS1 to the second performance state PS2 in response to the power management processor <NUM> executing the first instructions <NUM>-<NUM> to transition performance state of the first processor <NUM>-<NUM>. a second amount of time is between a time corresponding to the system controller <NUM> obtaining the performance information <NUM> and a time corresponding to the first processor <NUM>-<NUM> transitioning from the first performance state PS1 to the second performance state PS2 in response to the system controller <NUM> executing instructions to transition performance state of the first processor <NUM>-<NUM>. The first amount of time is less than the second amount of time.

In some implementations, the power management processor <NUM> receives, from the system controller <NUM>, a second power allocation 404B for the first processing cluster <NUM>-<NUM> and determines respective performance states of the plurality of processors <NUM> in accordance with the second power allocation 404B. The second power allocation 404B is different from the first power allocation 404A, and the determined respective performance state of the first processor <NUM>-<NUM> is different from the second performance state PS2. The power management processor <NUM> executes instructions to transition the plurality of processors <NUM> to the respective performance states, including executing instructions to transition the first processor <NUM>-<NUM> from the second performance state PS2 to the determined respective performance state.

In some implementations, the power management processor <NUM> communicates (<NUM>) with power management circuitry (e.g., in the PMIC <NUM>) having one or more voltage regulators that supply power to the device <NUM>. In some implementations, the power management processor <NUM> initializes one or more settings for the plurality of processors <NUM> by modifying a default hardware state of the electronic device <NUM> prior to the plurality of processors <NUM> executing application instructions.

It should be understood that the particular order in which the operations in <FIG> and <FIG> have been described are merely exemplary and are not intended to indicate that the described order is the only order in which the operations could be performed. One of ordinary skill in the art would recognize various ways to manage power consumption of an SoC-based electronic device <NUM> as described herein. Additionally, it should be noted that details of other processes described above with respect to <FIG> are also applicable in an analogous manner to method <NUM> described above with respect to <FIG> and <FIG>. For brevity, these details are not repeated here.

The terminology used in the description of the various described implementations herein is for the purpose of describing particular implementations only and is not intended to be limiting. As used in the description of the various described implementations and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Additionally, it will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain principles of operation and practical applications, to thereby enable others skilled in the art.

Claim 1:
A method, comprising:
at a first processing cluster (<NUM>-<NUM>) with a plurality (<NUM>-<NUM>, ..., <NUM>-N) of processors and a power management processor (<NUM>) distinct from the plurality (<NUM>-<NUM>, ..., <NUM>-N) of processors, the first processing cluster (<NUM>-<NUM>) included in an electronic device (<NUM>):
obtaining performance information about the plurality (<NUM>-<NUM>, ..., <NUM>-N) of processors;
executing first instructions to transition a first processor (<NUM>-<NUM>) of the plurality (<NUM>-<NUM>, ..., <NUM>-N) of processors from a first performance state to a second performance state, different from the first performance state, in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality (<NUM>-<NUM>, ..., <NUM>-N) of processors; and
executing one or more debug instructions to perform debugging of a respective processor of the plurality (<NUM>-<NUM>, ..., <NUM>-N) of processors based on the obtained performance information;
wherein the performance information includes activity levels, energy consumption, temperature measurements, counts of performance limit breaches, and/or throttling instructions for one or more of the plurality (<NUM>-<NUM>, ..., <NUM>-N) of processors; and
wherein the obtained performance information includes temperatures for one or more of the plurality (<NUM>-<NUM>, ..., <NUM>-N) of processors, and
in accordance with the performance information indicating an increase in a temperature of the first processor (<NUM>-<NUM>), the second performance state is a state that is associated with lower power consumption than the first performance state.