Patent Description:
The invention concerns a PLL circuit as in claim <NUM>.

In one example, a circuit includes a first filter, a plurality of binary-weighted capacitors, and a current source device. The circuit also includes a first plurality of switches. Each of the first plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors. The first plurality of switches are connected together, and the first plurality of switches are not connected to the first filter. A second plurality of switches is also included, and each of the second plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors and to the first filter and to a control input of the current source device. The first plurality of switches are not connected to the control input. The circuit can be used as part of a phase-locked loop.

An analog PLL (APLL) is described. The described APLL includes, among other components, a charge pump, a loop filter, and a current controlled oscillator. In some examples, the output of the loop filter is used to control a current source device that provides current to the current controlled oscillator. In practice, parasitic capacitance is present on the control input to the current source device. The parasitic capacitance can cause noise on the power supply to impact the loop filter's signal to the current source device and thus the current to the current controlled oscillator. The loop filter described herein has architecture that addresses this problem.

<FIG> shows an example of APLL <NUM>. The example APLL <NUM> includes a phase and frequency detector <NUM>, a charge pump <NUM>, a loop filter <NUM>, a current controlled oscillator (ICO) <NUM> and a frequency divider <NUM>. The output signal from the ICO <NUM> is an output clock (OUTCLK) <NUM>. A reference clock (REFCLK) <NUM> is provided to an input of the phase and frequency detector <NUM>. In some examples, the phase and frequency detector <NUM> generates an error signal <NUM> based on the frequency and/or phase difference (error) between REFCLK <NUM> and OUTCLK <NUM>. In the example of <FIG>, the frequency of OUTCLK <NUM> is greater than the frequency of REFCLK <NUM>. The frequency divider <NUM> divides down the frequency of OUTCLK <NUM> to produce a feedback clock (FBCLK) <NUM> that is approximately of the same frequency as REFCLK <NUM>. Reference herein to the FBCLK <NUM> includes the output signal from a frequency divider (e.g., frequency divider <NUM>) as well as to the output clock from ICO <NUM> in the implementation in which the frequency of OUTCLK <NUM> is of the same frequency as REFCLK <NUM>.

The APLL <NUM> adjusts the frequency and phase of OUTCLK <NUM> so as to match the phase of REFCLK <NUM>. <FIG> shows an example of REFCLK <NUM> and FBCLK <NUM> where the rising and falling edges of FBCLK <NUM> are phase aligned to the edges of REFCLK <NUM>. FBCLK <NUM> is said to be "locked" on to REFCLK <NUM>. Accordingly, OUTCLK <NUM> also is phase aligned to REFCLK in the locked state, although the frequency of OUTCLK <NUM> may be the same or greater than that of REFCLK <NUM>.

In some examples, the error signal <NUM> comprises a series of UP pulses as well as a series of DOWN pulses. <FIG> also shows an example of UP pulses and DOWN pulses. Responsive to the edges of FBCLK <NUM> lagging the corresponding edges of REFCLK <NUM>, the phase and frequency detector <NUM> generates the width W1 of the UP pulses to be wider than the width W2 of the DOWN pulses. Conversely, responsive to the edges of FBCLK <NUM> leading the corresponding edges of REFCLK <NUM>, the phase and frequency detector <NUM> generates the width W1 of the UP pulses to be narrower than the width W2 of the DOWN pulses.

<FIG> provides an example of charge pump <NUM>. In this example, the charge pump <NUM> includes a current source device I1 coupled to a current device I2 through a selectable switch SWA. Switch SWB selectively couples I2 to ground. The DOWN pulses <NUM> of the error signal <NUM> control the on and off state of SWA and the UP pulses <NUM> control the on and off state of SWB. When SWA is closed by an active DOWN pulse <NUM>, current flows through SWA and to the loop filter <NUM>. When SWB is closed by an active UP pulse <NUM>, current flows from the loop filter <NUM> through SWB to ground. Charge pump signal <NUM> thus includes a series of positive and negative current pulses based on the UP and DOWN pulses of the error signal <NUM>.

<FIG> shows an example of the loop filter <NUM>. The illustrated loop filter <NUM> includes a first filter <NUM>, a capacitor array <NUM>, a control circuit <NUM>, and a current source device M1. The first filter <NUM> in this example includes a capacitor C1 (also referred to as a filter capacitor) connected in series to a resistor R1. Capacitor C1 connects to supply voltage node (VDD) and resistor R1 connects to a control input of M1. In this example M1 is a p-type metal oxide semiconductor field effect transistor (PFET) and, as such resistor R1 connects to the gate of M1. In other implementations, M1 may be implemented as an n-type metal oxide semiconductor field effect transistor (NFET), as a p-type or n-type bipolar junction transistor, or as another type of transistor. The signal line between R1 and the control input to M1 is labeled as VFILT and represents the filtered output voltage from the loop filter <NUM>, which is used to control the operating state of M1 and thus current magnitude to the ICO <NUM>.

The capacitor array <NUM> includes a plurality of capacitors C2, C3,. In some examples, the capacitor array <NUM> is implemented as a binary-weighted capacitor array which allows the PLL to operate over a wide range of input reference frequencies, although the capacitors need not be binary weighted in other implementations. As such, the capacitors C2, C3,. , Cn have different capacitance values that are binary weighted. For example, the weightings of the capacitance values of the capacitors C2, C3,. , Cn may be 16C, 8C, 4C, etc. Capacitor C2 may be 16C and capacitor C3 may be 8C meaning that capacitor C2's capacitance value is double that of capacitor C3. In some implementations, capacitor C1 also is implemented as a configurable capacitor array (similar to capacitor array <NUM>) to facilitate operability over a wide frequency range.

The loop filter <NUM> of <FIG> includes a plurality of first switches SW1, a plurality of second switches SW2, and a plurality of third switches SW3. Each capacitor C2, C3,. Cn connects to a set of first, second and third switches SW1-SW3 as shown. Each of first switches SW1 connects to each of the other second switches SW1 as well to the charge pump <NUM>. Current from the charge pump <NUM> flows through switches SW1 to their respective capacitors C2, C3,. , Cn and current from the capacitors C2, C3,. Cn flows through the respective switch SW1 and to the charge pump <NUM>. Each of the second switches SW2 connects to each of the other second switches SW2 and to the loop filter <NUM> (e.g., to the resistor R1) and to the control input of M1. Each of the third switches SW3 connects to each of the other third switches SW3 and either to a ground node as shown or another fixed voltage node to reduce their leakage current.

Node <NUM> connects to the charge pump <NUM> and first switches SW1, but not to the first filter <NUM> or the control input of M1. Instead, the control input of M1 is connected to second switches SW2 and the first filter <NUM>. As such, the charge pump <NUM> is not connected to M1.

In some examples, first switches SW1 are binary-weighted like their corresponding capacitors C2, C3,. The ratio of channel width (W) to channel length (L) of each switch SW1 is binary weighted. For example, SW1 connected to C2 has a W/L ratio (e.g., <NUM>*W/L) that is twice that of C3 (e.g., <NUM>*W/L), and so on. The W/L ratios of switches S2 and S3 need not be binary weighted and can be smaller than switches SW1. The W/L ratios of switches SW2 can all be the same and the W/L ratios of switches SW2 also can all be the same, albeit different than (or the same as) for switches SW2.

In practice, the switches create a parasitic capacitance to ground which injects supply noise into the ISO <NUM>. Referring to <FIG>, in the absence of any parasitic capacitance to ground, any noise on the voltage supply will also be directly coupled to the gate of M1 through the capacitors C2, C3,. Thus, the supply noise seen at the gate of M1 would be zero. However, if there is a parasitic capacitance to ground from either VFILT or the gate of M1, there will be a potential division between C2, C3,. , Cn and the parasitic capacitance resulting in a non-zero supply noise component on the gate-to-source voltage of M1. The size of the parasitic capacitance is directly proportional to the sizes of the switches.

An advantage of the described examples is that the size (W/L) of the switches can be small, for the following reasons. A direct consequence of reducing the W/L of a metal oxide semiconductor (MOS) switch is that its resistance increases. The described architecture has the advantage that a higher switch resistance can be tolerated. To explain this advantage, consider the three sets of switches in <FIG> separately. The switches SW1 connect C2, C3,. , Cn to the charge pump <NUM> which generally has a high output resistance. Thus, the resistance of the switches SW1 can be relatively large without any significant effect on performance. The switches SW2 connect C2, C3,. , Cn to the filter <NUM> which contains a resistor R1 whose value is relatively large. As such, the resistance of SW2 can be relatively large. The switches SW3 are used to connect C2, C3,. , Cn to a dummy node when they are not used. Thus, the resistance of SW3 is for all practical purposes inconsequential and SW3 can be made arbitrarily small. By making switches SW3 relatively small, the parasitic capacitance at the gate of M1 can be reduced. The injection of supply noise into the gate-to-source voltage of M1 is reduced which in turn minimizes the effect of supply noise on the oscillator frequency. The control circuit <NUM> may be implemented as a controller, a finite state machine or other type of hardware device that can assert control signals to control the on and off state of the switches SW1-SW3. The control circuit <NUM> receives configuration (CONFIG) which specifies which of the binary weighted capacitors C2, C3,. , Cn are to be included in operation of the loop filter <NUM>. The configuration information may be stored in a register within the control circuit <NUM>. Various combinations of capacitors C2, C3,. , Cn can be activated by the control circuit <NUM> based on the configuration information. For a given capacitor C2, C3,. , Cn to be activated, the control circuit <NUM> asserts control signals so as to turn on (close) the corresponding SW1 and SW2 switches for those particular capacitors and to turn off (opens) switch SW3 for those same capacitors. For all other capacitors not to be activated as part of the loop filter's operation, the control circuit <NUM> asserts control signals so as to turn off the corresponding SW1 and SW2 switches and turn on switch SW3 for those capacitors.

The current from M1 flows to the ICO <NUM>, which produces OUTCLK <NUM> with a frequency that is a function of the current from M1. The frequency and phase of OUTCLK <NUM> is repeatedly adjusted so as to maintain frequency and phase lock between FBCLK <NUM> and REFCLK <NUM>.

Claim 1:
A PLL circuit including a loop filter (<NUM>), the loop filter (<NUM>) comprising:
a first filter (<NUM>);
a plurality of binary-weighted capacitors (C<NUM>, C<NUM>, Cn) that each include a first terminal coupled to a supply voltage node and a second terminal;
a current source device (M1) coupled between the supply voltage node and an output and including a control input, wherein the output is coupled to a current controlled oscillator (<NUM>);
first switches (SW1), each of the first switches (SW1) connected between the second terminal of a respective capacitor of the plurality of binary-weighted capacitors (C<NUM>, C<NUM>, Cn) and the output of a charge pump (<NUM>); and
second switches (SW2), each of the second switches (SW2) connected between the second terminal of a respective capacitor of the plurality of binary-weighted capacitors (C<NUM>, C<NUM>, Cn) and the control input of the current source device (M1);
wherein the first filter (<NUM>) is connected between the supply voltage node and the control input of the current source device (M1);
wherein the first and second switches (SW1, SW2) are metal oxide semiconductor switches.