Patent Description:
Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

<NPL> teaches error syndrome measurement using Pauli frames.

<CIT> (<CIT>) teaches in-situ quantum error correction.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.

A quantum computer uses quantum-mechanical phenomena such as superposition and entanglement to perform computations. In contrast to digital computers which store data in one of two definite states (<NUM> or <NUM>), quantum computation uses quantum bits (qubits), which can be in superpositions of states. Qubits may be implemented using physically distinguishable quantum states of elementary particles such as electrons and photons. For example, the polarization of a photon may be used where the two states are vertical polarization and horizontal polarization. Similarly, the spin of an electron may have distinguishable states such as "up spin" and "down spin.

Qubit states are typically represented by the bracket notations |<NUM>〉 and <NUM>). In a traditional computer system, a bit is exclusively in one state or the other, i.e., a '<NUM>' or a '<NUM>. ' However, qubits in quantum mechanical systems can be in a superposition of both states at the same time, a trait that is unique and fundamental to quantum computing.

Quantum computing systems execute algorithms containing quantum logic operations performed on qubits. The sequence of operations is statically compiled into a schedule and the qubits are addressed using an indexing scheme. This algorithm is then executed a sufficiently large number of times until the confidence interval of the computed answer is above a threshold (e.g., ~<NUM>+%). Hitting the threshold means that the desired algorithmic result has been reached.

Qubits have been implemented using a variety of different technologies which are capable of manipulating and reading quantum states. These include, but are not limited to quantum dot devices (spin based and spatial based), trapped-ion devices, superconducting quantum computers, optical lattices, nuclear magnetic resonance computers, solid-state NMR Kane quantum devices, electrons-on-helium quantum computers, cavity quantum electrodynamics (CQED) devices, molecular magnet computers, and fullerene-based ESR quantum computers, to name a few. Thus, while a quantum dot device is described below in relation to certain embodiments of the invention, the underlying principles of the invention may be employed in combination with any type of quantum computer including, but not limited to, those listed above. The particular physical implementation used for qubits is orthogonal to the embodiments of the invention described herein.

Quantum dots are small semiconductor particles, typically a few nanometers in size. Because of this small size, quantum dots operate according to the rules of quantum mechanics, having optical and electronic properties which differ from macroscopic entities. Quantum dots are sometimes referred to as "artificial atoms" to connote the fact that a quantum dot is a single object with discrete, bound electronic states, as is the case with atoms or molecules.

<FIG> are various views of a quantum dot device <NUM>, which may be used with embodiments of the invention described below. <FIG> is a top view of a portion of the quantum dot device <NUM> with some of the materials removed so that the first gate lines <NUM>, the second gate lines <NUM>, and the third gate lines <NUM> are visible. Although many of the drawings and description herein may refer to a particular set of lines or gates as "barrier" or "quantum dot" lines or gates, respectively, this is simply for ease of discussion, and in other embodiments, the role of "barrier" and "quantum dot" lines and gates may be switched (e.g., barrier gates may instead act as quantum dot gates, and vice versa). <FIG>1F are side cross-sectional views of the quantum dot device <NUM> of <FIG>; in particular, <FIG> is a view through the section B-B of <FIG>, <FIG> is a view through the section C-C of <FIG>, <FIG> is a view through the section D-D of <FIG>, <FIG> is a view through the section E-E of <FIG>, and <FIG> is a view through the section F-F of <FIG>.

The quantum dot device <NUM> of <FIG> may be operated in any of a number of ways. For example, in some embodiments, electrical signals such as voltages, currents, radio frequency (RF), and/or microwave signals, may be provided to one or more first gate line <NUM>, second gate line <NUM>, and/or third gate line <NUM> to cause a quantum dot (e.g., an electron spin-based quantum dot or a hole spin-based quantum dot) to form in a quantum well stack <NUM> under a third gate <NUM> of a third gate line <NUM>. Electrical signals provided to a third gate line <NUM> may control the electrical potential of a quantum well under the third gates <NUM> of that third gate line <NUM>, while electrical signals provided to a first gate line <NUM> (and/or a second gate line <NUM>) may control the potential energy barrier under the first gates <NUM> of that first gate line <NUM> (and/or the second gates <NUM> of that second gate line <NUM>) between adjacent quantum wells. Quantum interactions between quantum dots in different quantum wells in the quantum well stack <NUM> (e.g., under different quantum dot gates) may be controlled in part by the potential energy barrier provided by the barrier potentials imposed between them (e.g., by intervening barrier gates).

Generally, the quantum dot devices <NUM> disclosed herein may further include a source of magnetic fields (not shown) that may be used to create an energy difference in the states of a quantum dot (e.g., the spin states of an electron spin-based quantum dot) that are normally degenerate, and the states of the quantum dots (e.g., the spin states) may be manipulated by applying electromagnetic energy to the gates lines to create quantum bits capable of computation. The source of magnetic fields may be one or more magnet lines, as discussed below. Thus, the quantum dot devices <NUM> disclosed herein may, through controlled application of electromagnetic energy, be able to manipulate the position, number, and quantum state (e.g., spin) of quantum dots in the quantum well stack <NUM>.

In the quantum dot device <NUM> of <FIG>, a gate dielectric <NUM> may be disposed on a quantum well stack <NUM>. A quantum well stack <NUM> may include at least one quantum well layer <NUM> (not shown in <FIG>) in which quantum dots may be localized during operation of the quantum dot device <NUM>. The gate dielectric <NUM> may be any suitable material, such as a high-k material. Multiple parallel first gate lines <NUM> may be disposed on the gate dielectric <NUM>, and spacer material <NUM> may be disposed on side faces of the first gate lines <NUM>. In some embodiments, a patterned hardmask <NUM> may be disposed on the first gate lines <NUM> (with the pattern corresponding to the pattern of the first gate lines <NUM>), and the spacer material <NUM> may extend up the sides of the hardmask <NUM>, as shown. The first gate lines <NUM> may each be a first gate <NUM>. Different ones of the first gate lines <NUM> may be electrically controlled in any desired combination (e.g., each first gate line <NUM> may be separately electrically controlled, or some or all the first gate lines <NUM> may be shorted together in one or more groups, as desired).

Multiple parallel second gate lines <NUM> may be disposed over and between the first gate lines <NUM>. As illustrated in <FIG>, the second gate lines <NUM> may be arranged perpendicular to the first gate lines <NUM>. The second gate lines <NUM> may extend over the hardmask <NUM>, and may include second gates <NUM> that extend down toward the quantum well stack <NUM> and contact the gate dielectric <NUM> between adjacent ones of the first gate lines <NUM>, as illustrated in <FIG>. In some embodiments, the second gates <NUM> may fill the area between adjacent ones of the first gate lines <NUM>/spacer material <NUM> structures; in other embodiments, an insulating material (not shown) may be present between the first gate lines <NUM>/spacer material <NUM> structures and the proximate second gates <NUM>. In some embodiments, spacer material <NUM> may be disposed on side faces of the second gate lines <NUM>; in other embodiments, no spacer material <NUM> may be disposed on side faces of the second gate lines <NUM>. In some embodiments, a hardmask <NUM> may be disposed above the second gate lines <NUM>. Multiple ones of the second gates <NUM> of a second gate line <NUM> are electrically continuous (due to the shared conductive material of the second gate line <NUM> over the hardmask <NUM>). Different ones of the second gate lines <NUM> may be electrically controlled in any desired combination (e.g., each second gate line <NUM> may be separately electrically controlled, or some or all the second gate lines <NUM> may be shorted together in one or more groups, as desired). Together, the first gate lines <NUM> and the second gate lines <NUM> may form a grid, as depicted in <FIG>.

Multiple parallel third gate lines <NUM> may be disposed over and between the first gate lines <NUM> and the second gate lines <NUM>. As illustrated in <FIG>, the third gate lines <NUM> may be arranged diagonal to the first gate lines <NUM>, and diagonal to the second gate lines <NUM>. In particular, the third gate lines <NUM> may be arranged diagonally over the openings in the grid formed by the first gate lines <NUM> and the second gate lines <NUM>. The third gate lines <NUM> may include third gates <NUM> that extend down to the gate dielectric <NUM> in the openings in the grid formed by the first gate lines <NUM> and the second gate lines <NUM>; thus, each third gate <NUM> may be bordered by two different first gate lines <NUM> and two different second gate lines <NUM>. In some embodiments, the third gates <NUM> may be bordered by insulating material <NUM>; in other embodiments, the third gates <NUM> may fill the openings in the grid (e.g., contacting the spacer material <NUM> disposed on side faces of the adjacent first gate lines <NUM> and the second gate lines <NUM>, not shown). Additional insulating material <NUM> may be disposed on and/or around the third gate lines <NUM>. Multiple ones of the third gates <NUM> of a third gate line <NUM> are electrically continuous (due to the shared conductive material of the third gate line <NUM> over the first gate lines <NUM> and the second gate lines <NUM>). Different ones of the third gate lines <NUM> may be electrically controlled in any desired combination (e.g., each third gate line <NUM> may be separately electrically controlled, or some or all the third gate lines <NUM> may be shorted together in one or more groups, as desired).

Although <FIG> illustrate a particular number of first gate lines <NUM>, second gate lines <NUM>, and third gate lines <NUM>, this is simply for illustrative purposes, and any number of first gate lines <NUM>, second gate lines <NUM>, and third gate lines <NUM> may be included in a quantum dot device <NUM>. Other examples of arrangements of first gate lines <NUM>, second gate lines <NUM>, and third gate lines <NUM> are possible. Electrical interconnects (e.g., vias and conductive lines) may contact the first gate lines <NUM>, second gate lines <NUM>, and third gate lines <NUM> in any desired manner.

Not illustrated in <FIG> are accumulation regions that may be electrically coupled to the quantum well layer of the quantum well stack <NUM> (e.g., laterally proximate to the quantum well layer). The accumulation regions may be spaced apart from the gate lines by a thin layer of an intervening dielectric material. The accumulation regions may be regions in which carriers accumulate (e.g., due to doping, or due to the presence of large electrodes that pull carriers into the quantum well layer), and may serve as reservoirs of carriers that can be selectively drawn into the areas of the quantum well layer under the third gates <NUM> (e.g., by controlling the voltages on the quantum dot gates, the first gates <NUM>, and the second gates <NUM>) to form carrier-based quantum dots (e.g., electron or hole quantum dots, including a single charge carrier, multiple charge carriers, or no charge carriers). In other embodiments, a quantum dot device <NUM> may not include lateral accumulation regions, but may instead include doped layers within the quantum well stack <NUM>. These doped layers may provide the carriers to the quantum well layer. Any combination of accumulation regions (e.g., doped or non-doped) or doped layers in a quantum well stack <NUM> may be used in any of the embodiments of the quantum dot devices <NUM> disclosed herein.

Control operations on quantum bits in a continuously operating quantum computer processor depend heavily on the fault tolerance of the system. For example, control operations may depend on the system remaining below the sub-fault tolerant threshold (e.g., < <NUM>% per operation). Over time, during multiple algorithm execution cycles, the system tends to drift due to charge noise in the semiconductor substrate, which in one embodiment comprises Silicon-Germanium (SiGe). In addition to the SiGe substrate, imperfect control pulse generation electronics, unclean continuous DC voltages, and even cosmic rays all increase the error rate during subsequent algorithm runs. This is a significant ongoing challenge to achieving scalable operation of a large system of qubits that will be useful for solving real world problems.

To mitigate the accumulative and ongoing drift in the system, one embodiment of the invention implements a just-in-time (JIT) quantum compiler and a quantum error correction (QEC) unit to adjust for the system drift during execution of a quantum algorithm. In particular, the QEC unit accumulates detected errors in a buffer during the error correction cycle of each algorithm run and a drift detection unit manages the buffer and triggers a corrective action once it reaches a preprogrammed error threshold.

In one embodiment, when the programmed correction threshold is reached, the system executes a diagnostic algorithm with a pre-known result to determine a noise correction for each qubit in the QEC tile. A just-in-time (JIT) compiler is then signaled to read the buffer and recompile the quantum algorithm with these precomputed compensation values. Once the average drift in the system is too large to correct, an automatic recalibration of the quantum computing system is performed and the DLAB is flushed.

<FIG> illustrates a quantum error correction cycle. At <NUM> the logical qubit state of the system is initialized. For example, if electron spin is used as the quantum state, then electrons within the quantum system may be prepared (e.g., initialized to a particular spin orientation and/or entangled using electromagnetic control signals from the quantum controller). At <NUM>, the state of the quantum system evolves in response to additional electromagnetic inputs specified by the quantum runtime and physically implemented by the quantum controller.

At <NUM>, a measurement of the quantum system is taken. For example, the current spin of one of the entangled electrons may be measured. The system may subsequently be re-initialized prior to the next measurement (i.e., given that taking a measurement or learning any information about the quantum system disrupts the quantum state). The physical qubits may be periodically measured for the error correction cycle. At <NUM>, error and drift detection is performed on the measured results to determine whether one or multiple errors have occurred (e.g., random flip(s) of one or more qubit(s)). An error correction operation is performed at <NUM>, which attempts to correct any detected errors. At <NUM>, if a drift threshold has been reached, drift correction is implemented as described herein. For example, in one embodiment, a JIT compiler generates a new quantum runtime based on the detected drift.

<FIG> illustrates an exemplary quantum controller <NUM> for performing quantum error/drift detection and correction on results generated by a quantum processor <NUM>. In operation, a decoder <NUM> takes a multi-qubit measurement from the quantum processor <NUM> which does not disturb the quantum information in the encoded state but contains information about the error. For example, the qubits <NUM> may include one or more ancilla qubits which are used to protect the integrity of the data encoded in the data qubits, which contain the underlying data resulting from a quantum operation. In one implementation, the error syndrome data from the ancilla qubits can be used by the quantum error correction (QEC) unit <NUM> to determine whether a data qubit has been corrupted, to identify the physical qubit which was affected and in some cases to determine which of several possible ways it was affected.

<FIG> illustrates additional detail of the drift detection/compensation unit <NUM>, in which the QEC unit <NUM> accumulates detected Z (Phase) and X (Bit-Flip) errors in a Drift Lookaside Buffer (DLAB) <NUM> during the error correction cycle of each algorithm run. A drift computation unit <NUM> determines a current system drift for the quantum processor <NUM>. This may comprise, for example, an average system drift. A threshold analysis unit <NUM> (e.g., which may implemented as a comparator) compares a pre-specified threshold <NUM> with the current system drift. If the threshold <NUM> has been reached or exceeded, then a compensation unit <NUM> executes diagnostics such as Hahn Echo read-out, Randomized Benchmarking, or any quantum algorithm with a pre-known result to determine a noise correction to be applied for each qubit in the QEC tile.

In one embodiment, the drift lookaside buffer <NUM> uses a table data structure with at least one entry for each qubit. If the compensation unit <NUM> determines a noise correction for a qubit, the associated correction values are stored in the table entry of the drift lookaside buffer <NUM> associated with that qubit.

Upon reaching/exceeding the threshold <NUM>, a recompile signal <NUM> is generated. In response, the quantum just-in-time (JIT) compiler <NUM> reads the DLAB <NUM> (e.g., using a qubit ID or other identifier as an index) and recompiles the quantum algorithm with these precomputed compensation values. The new quantum runtime <NUM> is then executed by the qubit control unit <NUM>, controlling the qubits in accordance with the new correction values. In one embodiment, once the average drift in the system is too large to correct, an automatic recalibration of the quantum computing system is performed and the drift lookaside buffer <NUM> is flushed.

A method is illustrated in <FIG>. The method may be implemented within the context of the quantum system architectures described herein, but is not limited to any particular type of quantum system.

At <NUM> the logical state of the qubits is initialized on the quantum processor. For example, the qubits may be initialized to a particular spin orientation and/or entangled using electromagnetic control signals from the quantum controller. At <NUM>, quantum operations are executed (e.g., in accordance with a quantum runtime). The state of the quantum system evolves in response to additional electromagnetic inputs specified by the quantum runtime and physically implemented by the quantum controller. As mentioned, the techniques described herein may be implemented once the quantum computer enters a quiescent state. A diagnostic mode may then be executed in which a specific set of representative quantum algorithms with known outcomes is executed. In addition, these learning techniques may be performed during normal system operation.

At <NUM> the state of the ancilla qubits is read and, at <NUM>, decoded to generate an error syndrome if an error is detected. At <NUM>, the error syndrome is decoded evaluated to perform error correction. As described above, detected Z (Phase) and X (Bit-Flip) errors may be collected in a Drift Lookaside Buffer (DLAB) during the error correction cycle of each algorithm run.

At <NUM>, a level of system drift is determined. For example, the average system drift may be determined based on the detected Z and X errors stored in the drift lookaside buffer. If a drift threshold is reached, determined at <NUM>, then correction values are generated to compensate for the drift and used to re-compile the quantum runtime at <NUM>.

The embodiments described herein may be used to improve fault tolerance and efficiently correct for system drift in quantum computing systems. This effectively reduces the costs associated with building and maintaining quantum computing hardware by moving complexity to software. These embodiments also add flexibility and scalability of the quantum computing system.

In the above detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the above detailed description is not to be taken in a limiting sense.

Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. Terms like "first," "second," "third," etc. do not imply a particular ordering, unless otherwise specified.

For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments.

Embodiments of the invention may include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals - such as carrier waves, infrared signals, digital signals, etc.).

Claim 1:
A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
executing quantum operations on a quantum processor (<NUM>) in accordance with a quantum runtime (<NUM>), the quantum operations physically implemented on a plurality of qubits (<NUM>);
measuring values from all or a subset of the plurality of qubits;
decoding the values to detect errors associated with the qubits;
determining a current system drift for the quantum processor based on the errors;
calculating compensation values by determining a noise correction value for each of the qubits;
regenerating the quantum runtime using the compensation values if the current system drift is determined to be above a threshold;
storing the compensation values in a drift lookaside buffer (<NUM>) having a plurality of entries with at least one entry for each qubit, the entry including a compensation value associated with its respective qubit;
storing the errors detected for each qubit in a drift compensation buffer entry associated with that qubit;
evaluating the errors to determine when the system drift has reached or risen above the threshold; and
wherein the compensation values comprise noise correction values generated by executing a sequence of operations with a predetermined result to determine a noise correction for each qubit.