Patent Description:
In accordance with the invention a circuit includes a first inductor having a first terminal configured to couple to a first node and a second terminal configured to couple to a second node. The circuit further includes a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PFET) having a source terminal coupled to the second node and a drain terminal coupled to a third node. The circuit further includes a second PFET having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the second node. The circuit further includes a third PFET having a source terminal coupled to a fourth node and a drain terminal coupled to the third node. The circuit further includes a fourth PFET having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fourth node. The circuit further includes a n-type MOSFET (NFET) having a source terminal coupled to a fifth node and a drain terminal coupled to the third node. The circuit further includes a second inductor having a first terminal configured to couple to the fourth node and a second terminal configured to couple to the fifth node. The circuit further includes a controller coupled to a gate terminal of the first PFET, a gate terminal of the second PFET, a gate terminal of the third PFET, a gate terminal of the fourth PFET, and a gate terminal of the NFET.

In at least one example, a system includes a circuit, a load and a battery. The circuit includes a first resistor configured to couple between a first node and a second node and a first inductor coupled between the second node and the third node. The circuit further includes first a PFET having a source terminal coupled to the third node and a drain terminal coupled to a fourth node. The circuit further includes a second PFET having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the third node. The circuit further includes a third PFET having a source terminal coupled to a fifth node and a drain terminal coupled to the fourth node. The circuit further includes a fourth PFET having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fifth node. The circuit further includes a NFET having a source terminal coupled to a sixth node and a drain terminal coupled to the fourth node. The circuit further includes a second inductor having a first terminal configured to couple to the fifth node and a second terminal configured to couple to the sixth node. The circuit further includes a controller coupled to a gate terminal of the first PFET, a gate terminal of the second PFET, a gate terminal of the third PFET, a gate terminal of the fourth PFET, and a gate terminal of the NFET. In at least one example, the load is configured to couple to the fourth node. In at least one example, the battery is configured to couple between the sixth node and the ground voltage potential.

In accordance with an alternative solution, a circuit includes a first inductor having a first terminal configured to couple to a first node and a second terminal configured to couple to a second node. The circuit further includes a first PFET having a source terminal coupled to the second node and a drain terminal coupled to a third node. The circuit further includes a second PFET having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the second node. The circuit further includes a third PFET having a source terminal coupled to a fourth node and a drain terminal coupled to the third node. The circuit further includes a fourth PFET having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fourth node. The circuit further includes a fifth PFET having a source terminal coupled to a fifth node and a drain terminal coupled to the third node. The circuit further includes a NFET having a source terminal coupled to a sixth node and a drain terminal coupled to the fourth node. The circuit further includes a second inductor having a first terminal configured to couple to the fourth node and a second terminal configured to couple to the sixth node. The circuit further includes a controller coupled to a gate terminal of the first PFET, a gate terminal of the second PFET, a gate terminal of the third PFET, a gate terminal of the fourth PFET, a gate terminal of the fifth PFET, and a gate terminal of the NFET.

A design consideration in designing a power management circuit is the efficiency with which the circuit provides power at an output of the circuit. Often, each component in a critical path of the circuit (e.g., a path through which energy flows to the output of the circuit) has an associated loss that reduces the power available at the output of the circuit. In one example of such components that are prevalent in power management circuits and fundamental to their operation, switches (e.g., transistors) have a switching loss and/or a conduction loss that reduces the voltage of signal switched by the switch (e.g., a signal passing from one terminal of the switch to another terminal of the switch). As a result, the more switches in the critical path of a power management circuit, the more power that will be lost due to operation of those switches and efficiency of the power management circuit is reduced.

Certain circuit architectures provide more optimal characteristics for particular use cases than other circuit architectures. For example, a direct power path system may operate efficiently in a power management circuit coupled to a battery and a load when an input voltage (Vin) to the power management circuit is greater than a voltage of the battery (Vbat). For example, such that the direct power path system provides Vin directly to a terminal providing an output voltage (Vout) of the power management circuit. However, when Vin is less than Vbat, the direct power path system is, in many cases, unable to provide Vin directly to the terminal providing Vout. Therefore, the direct power path system may have a limited operational voltage range. Similarly, a buck-boost system may have a wide operational voltage range but may operate inefficiently for a portion of that operational voltage range, such as when Vin is greater than Vbat. Individually, each circuit architecture provides advantages and disadvantages. By combining the two individual circuit architectures, a circuit that performs more efficiently for a greater number of use cases may be possible, however in doing so, challenges arise. Particularly, the two circuit architectures are each fully-functional circuits including a plurality of switches, each with an associated loss, that when combined adds additional switches into the critical path of the power management circuit and detrimentally effects efficiency of operation of the power management circuit.

At least some aspects provide for a circuit that includes both direct power path functionality and buck-boost functionality while including a minimal number of switches in a critical path of the circuit. In some examples, the circuit is implemented as a power management circuit, such as a dynamic buck-boost and power path management circuit. In at least some examples, the circuit includes a plurality of switches, at least some of which are shared between direct power path functionality and buck-boost functionality. Also, in various examples, the circuit includes a plurality of operation modes in which power is provided from a Vin terminal to a Vout terminal, power is provided from a Vbat terminal to the Vout terminal, power is provided from the Vin terminal and the Vbat terminal to the Vout terminal, power is provided from the Vin terminal to the Vout terminal and the Vbat terminal, and/or power is provided from the Vbat terminal to the Vin terminal. In at least some examples, a path between the Vin terminal and the Vout terminal includes no more than three switches, a path between the Vbat terminal and the Vout terminal includes no more than three switches, and/or a path between the Vin terminal and the Vbat terminal includes no more than three switches.

<FIG> shows a block diagram of an illustrative system <NUM>. In some examples, the system <NUM> is representative of at least a portion of circuitry in a consumer (or professional/enterprise) electronic device. In at least one example, the system <NUM> is representative of at least a portion of circuitry in a laptop (or notebook, netbook, etc.), a smartphone, a tablet, or a hybrid device having the functionality of any two or more of the above devices. In some example architectures, the system <NUM> includes a Vin terminal <NUM>, a controller <NUM>, a direct power path circuit <NUM>, a buck-boost circuit <NUM> (e.g., such as a buck-boost narrow output voltage direct current (DC) (NVDC) circuit), a Vbat terminal <NUM>, and a Vout terminal <NUM>. In at least some examples, the direct power path circuit <NUM> and the buck-boost circuit <NUM> share at least some components such that a component count and footprint of the system <NUM> is minimized. In some examples, the system <NUM> further includes, or is configured to couple to (e.g., at Vout terminal <NUM>), a load <NUM>. In yet other examples, the system <NUM> further includes, or is configured to couple to (e.g., at Vbat terminal <NUM>), a battery <NUM>.

The Vin terminal <NUM> is, in some examples, an input terminal of the system <NUM>. For example, when the system <NUM> is implemented in an electronic device, the Vin terminal <NUM> is a charging terminal of the system <NUM>. In at least some examples, the Vin terminal is a Universal Serial Bus (USB) type-C (USB-C) terminal (e.g., a USB-C receptacle). The Vout terminal <NUM> is, in some examples, configured to couple to the load <NUM> to provide power to the load <NUM>. For example, when the system <NUM> is implemented in an electronic device, the load <NUM> includes a plurality of circuits (not shown) configured to control operation, or implement functionality, or the electronic device.

In an example of operation of the system <NUM>, the controller <NUM> controls the flow of energy among the Vin terminal <NUM>, the Vbat terminal <NUM>, and/or the Vout terminal <NUM>, for example, to power the load <NUM>, to charge the battery <NUM>, and/or to power or charge an external device (not shown) coupled to the Vin terminal <NUM>. The controller <NUM> controls the flow of energy, in some examples, by controlling one or more switches (not shown) to conduct, or not conduct, energy between respective terminals of the switches. In one example, the controller <NUM> controls one or more switches to conduct energy between the Vin terminal <NUM> and the Vbat terminal <NUM> while also controlling one or more switches, at least some of which may be the same switches, to conduct energy between the Vin terminal <NUM> and the Vout terminal <NUM>. In another example, the controller <NUM> controls one or more switches to conduct energy between the Vin terminal <NUM> and the Vout terminal <NUM> while also controlling one or more switches, at least some of which may be the same switches, to conduct energy between the Vbat terminal <NUM> and the Vout terminal <NUM>. In another example, the controller <NUM> controls one or more switches to conduct energy between the Vbat terminal <NUM> and the Vout terminal <NUM>, in some examples via an inductor to boost a value of a signal present at the Vbat terminal <NUM> prior to delivery to the Vout terminal <NUM>. In another example, the controller <NUM> controls one or more switches to conduct energy between the Vbat terminal <NUM> and the Vin terminal <NUM>.

<FIG> shows a schematic diagram of an illustrative circuit <NUM> in accordance with the invention defined in the claims. In some examples, the circuit <NUM> is a power management circuit, for example, suitable for implementation as the controller <NUM> of the system <NUM> of <FIG>, described above. The circuit <NUM> includes, or is configured to couple to, an inductor <NUM>, a capacitor <NUM>, a resistor <NUM>, a p-type metal oxide semiconductor field effect transistor (MOSFET) (PFET) <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, a capacitor <NUM>, an inductor <NUM>, a n-type MOSFET (NFET) <NUM>, a resistor <NUM>, a capacitor <NUM>, and/or a charger controller <NUM>, along with a Vin terminal <NUM> at which a signal Vin is present, Vbat terminal <NUM> at which a signal Vbat is present, and Vout terminal <NUM> at which a signal Vout is present. In some examples, the circuit <NUM> further includes, or is configured to couple to, a battery <NUM>. In at least one example, the charger controller <NUM> is a processor or microprocessor suitable for monitoring one or more input signals and generating one or more output signals based on determinations made according to values of at least some of the one or more input signals. In other examples, the charger controller <NUM> is any analog, digital or mixed-signal circuit suitable for performing the signal monitoring and generation as described above. Also, while certain devices are described herein as PFET or NFET, in some examples not being in accordance with the invention the devices are replaced by another device of substantially similar functionality (e.g., replacing PFET with NFET, NFET with PFET, either PFET or NFET with bi-polar junction transistor (BJT), etc.), the scope of which is not limited herein. For example, in certain high-power applications, such as high-power switching converters, it may be desirable to replace PFET devices with NFET devices.

In the circuit <NUM>, the capacitor <NUM> is coupled between the Vin terminal <NUM> and a ground voltage potential <NUM>. The resistor <NUM> is coupled between the Vin terminal <NUM> and a first terminal of the inductor <NUM>, and a second terminal of the inductor <NUM> is coupled to a node <NUM>. A source terminal of the PFET <NUM> is coupled to the node <NUM> and a drain terminal of the PFET <NUM> is coupled to the Vout terminal <NUM>. A source terminal of the PFET <NUM> is coupled to the ground voltage potential <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. The capacitor <NUM> is coupled between the Vout terminal <NUM> and the ground voltage potential <NUM>. A source terminal of the PFET <NUM> is coupled to a node <NUM> and a drain terminal of the PFET <NUM> is coupled to the Vout terminal <NUM>. A source terminal of the PFET <NUM> is coupled to the ground voltage potential <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. The inductor <NUM> is coupled between the node <NUM> and a node <NUM>. A source terminal of the NFET <NUM> is coupled to the Vout terminal <NUM> and a drain terminal of the NFET <NUM> is coupled to the node <NUM>. The resistor <NUM> is coupled between the node <NUM> and the Vbat terminal <NUM>. The capacitor <NUM> is coupled between the Vout terminal <NUM> and the ground voltage potential <NUM>. In at least some examples, the battery <NUM> is coupled between the Vbat terminal <NUM> and the ground voltage potential <NUM>. Further, the charger controller <NUM> is coupled to gate terminals of each of the PFET <NUM>, PFET <NUM>, PFET <NUM>, and NFET <NUM>.

In operation of the circuit <NUM>, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and/or NFET <NUM> to operate the circuit <NUM> in one of a plurality of operation modes. For example, during a charging operation mode, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and/or NFET <NUM> to provide energy from the Vin terminal <NUM> to both the Vout terminal <NUM> (e.g., to power devices (not shown) coupled to the Vout terminal <NUM>) and the Vbat terminal <NUM> (e.g., to charge the battery <NUM>). The charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and/or NFET <NUM>, in some examples, at least partially based on a received control signal (Ctrl) (not shown). Ctrl indicates, in some examples, a value of Vin with respect to a value of Vbat. For examples, Ctrl indicates whether Vin is greater than or less than Vbat. Ctrl is received by the charger controller <NUM>, in some examples, from a device or component outside of, but coupled to, the circuit <NUM>. In other examples, Ctrl is received by the charger controller <NUM> from a component (not shown) within the circuit <NUM>. In yet other examples, Ctrl is determined by the charger controller <NUM> based on couplings (not shown) between the charger controller <NUM> and each of the Vin terminal <NUM> and the Vbat terminal <NUM>. In some examples, the charger controller <NUM> further controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and/or NFET <NUM> based on an additional received or generated signal (not shown) specifying an operation mode (e.g., such as one of the operation modes described below) for the circuit <NUM>.

During the charging operation mode when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and NFET <NUM> (e.g., based at least partially on a value of a signal provided to their respective gate terminals) to conduct (or not conduct) energy between their respective source and drain terminals. During the charging operation mode when Vin is less than Vbat, two current paths are formed in the circuit <NUM>. The first current path passes through the resistor <NUM>, inductor <NUM>, and PFET <NUM> and provides power from the Vin terminal <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes through the resistor <NUM>, inductor <NUM>, PFET <NUM>, NFET <NUM>, and resistor <NUM> and provides power from the Vin terminal <NUM> to the Vbat terminal <NUM> or from the Vin terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the ground voltage potential <NUM>.

In at least some examples, the charger controller <NUM> controls the PFET <NUM> and the PFET <NUM> to selectively activate and deactivate (e.g., conduct energy between their respective source and drain terminals and not conduct energy between their respective source and drain terminals) at a duty cycle selected such that the inductor <NUM>, PFET <NUM>, PFET <NUM>, capacitor <NUM>, and capacitor <NUM> form a boost converter. For example, when the PFET <NUM> is inactive and not conducting energy between its source and drain terminals and the PFET <NUM> is active and conducting energy between its source and drain terminals, the inductor <NUM> is charging (e.g., storing energy) and energy previously stored in the capacitor <NUM> and the capacitor <NUM> is discharged to the Vbat terminal <NUM> and the Vout terminal <NUM>. When the PFET <NUM> is active and the PFET <NUM> is inactive, the inductor <NUM> discharges to the Vbat terminal <NUM> and the Vout terminal <NUM>, also at least partially recharging the capacitor <NUM> and the capacitor <NUM>. Based on the duty cycle selected for control of the PFET <NUM> and the PFET <NUM> by the charger controller <NUM>, and an inductance value of the inductor <NUM>, a value of Vin is increased (e.g., boosted) prior to being provided to the Vbat terminal <NUM> and the Vout terminal <NUM>.

During the charging operation mode when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the charging operation mode when Vin is greater than Vbat, two current paths are formed in the circuit <NUM>. The first current path passes through the resistor <NUM>, inductor <NUM>, and PFET <NUM> and provides power from the Vin terminal <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes through the resistor <NUM>, inductor <NUM>, PFET <NUM>, PFET <NUM>, inductor <NUM>, and resistor <NUM> and provides power from the Vin terminal <NUM> to the Vbat terminal <NUM> or through the PFET <NUM>, inductor <NUM>, and resistor <NUM> to the Vbat terminal <NUM>.

In at least some examples, the charger controller <NUM> controls the PFET <NUM> and the PFET <NUM> to selectively activate and deactivate (e.g., conduct energy between its source and drain terminals and not conduct energy between its source and drain terminals) at a duty cycle selected such that the inductor <NUM>, PFET <NUM>, and PFET <NUM> form a buck converter. For example, when the PFET <NUM> is active and the PFET <NUM> is inactive, the inductor <NUM> is charging and power is not provided to the Vbat terminal <NUM>. When the PFET <NUM> is inactive and the PFET <NUM> is active, the inductor <NUM> discharges to the Vbat terminal <NUM>. Based on the duty cycle selected for control of the PFET <NUM> and the PFET <NUM> by the charger controller <NUM>, and an inductance value of the inductor <NUM>, a value of Vin is reduced (e.g., bucked) prior to being provided to the Vbat terminal <NUM>.

During a discharge operation mode (e.g., when Vin is not received by the circuit <NUM> at the Vin terminal <NUM>), the charger controller <NUM> controls the NFET <NUM> to conduct energy between its source and drain terminals. During the discharge operation mode one current path is formed in the circuit <NUM>. The current path passes from the Vbat terminal <NUM> through the resistor <NUM> and NFET <NUM> to the Vout terminal <NUM>.

During an on-the-go (OTG) operation mode when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and NFET <NUM> (e.g., based at least partially on a value of a signal provided to their respective gate terminals) to conduct (or not conduct) energy between their respective source and drain terminals. During the OTG operation mode when Vin is less than Vbat, a current path is formed from the Vbat terminal <NUM> to the Vin terminal <NUM>. The current path alternatingly passes from the Vbat terminal <NUM> through the resistor <NUM>, NFET <NUM>, PFET <NUM>, inductor <NUM>, and resistor <NUM> or through the PFET <NUM>, inductor <NUM>, and resistor <NUM> to the Vin terminal <NUM>.

In at least some examples, the charger controller <NUM> controls the PFET <NUM> and the PFET <NUM> to selectively activate and deactivate at a duty cycle selected such that the inductor <NUM>, PFET <NUM>, and PFET <NUM> form a buck converter. For example, when the PFET <NUM> is active and conducting energy between its source and drain terminals, the inductor <NUM> is charging. When the PFET <NUM> is active and the PFET <NUM> is inactive, the inductor <NUM> is charging and power is not provided to the Vin terminal <NUM> from the Vbat terminal <NUM>. When the PFET <NUM> is inactive and the PFET <NUM> is active, the inductor <NUM> discharges to the Vin terminal <NUM>. Based on the duty cycle selected for control of the PFET <NUM> and the PFET <NUM> by the charger controller <NUM>, and an inductance value of the inductor <NUM>, a value of Vbat is reduced prior to being provided to the Vin terminal <NUM>.

During the OTG operation mode when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the OTG operation mode when Vin is greater than Vbat, a current path is formed from the Vbat terminal <NUM> to the Vin terminal <NUM>. The current path passes from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, PFET <NUM>, PFET <NUM>, inductor <NUM>, and resistor <NUM>.

In at least some examples, the charger controller <NUM> controls the PFET <NUM> and the PFET <NUM> to selectively activate and deactivate at a duty cycle selected such that the inductor <NUM>, PFET <NUM>, PFET <NUM>, and capacitor <NUM> form a boost converter. For example, when the PFET <NUM> is active and the PFET <NUM> is inactive, the inductor <NUM> is charging and energy previously stored in the capacitor <NUM> is discharged to the Vin terminal <NUM>. When the PFET <NUM> is inactive and the PFET <NUM> is active, the inductor <NUM> discharges to the Vin terminal <NUM>, also at least partially recharging the capacitor <NUM>. Based on the duty cycle selected for control of the PFET <NUM> and the PFET <NUM> by the charger controller <NUM>, and an inductance value of the inductor <NUM>, a value of Vbat is increased prior to being provided to the Vin terminal <NUM>.

During a turbo operation mode (sometimes referred to as a hybrid operation mode or a turbo boost mode), a demand by a load (not shown) coupled to the Vout terminal <NUM> is greater than can be satisfied by Vin and the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the turbo operation mode, two current paths are formed in the circuit <NUM>. The first current path passes from the Vin terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the Vout terminal <NUM> or from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the ground voltage potential <NUM>.

In at least some examples, the charger controller <NUM> controls the PFET <NUM> and the PFET <NUM> to selectively activate and deactivate at a duty cycle selected such that the inductor <NUM>, PFET <NUM>, PFET <NUM>, capacitor <NUM>, and capacitor <NUM> form a boost converter. For example, when the PFET <NUM> is inactive and the PFET <NUM> is active, the inductor <NUM> is charging and, in some examples, energy previously stored in the capacitor <NUM> and the capacitor <NUM> is discharged to the Vout terminal <NUM>. When the PFET <NUM> is active and the PFET <NUM> is inactive, the inductor <NUM> discharges to the Vout terminal <NUM>, in some examples also at least partially recharging the capacitor <NUM> and the capacitor <NUM>. Based on the duty cycle selected for control of the PFET <NUM> and the PFET <NUM> by the charger controller <NUM>, and an inductance value of the inductor <NUM>, a value of Vbat is increased prior to being provided to the Vout terminal <NUM>.

During an uninterrupted power supply (UPS) operation mode, Vbat supplements power provided to the Vout terminal <NUM> by Vin, and provides power to the Vin terminal <NUM>. During the UPS operation mode, when Vin is less than a preset value, when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, or when the charger controller <NUM> detects that Vin is no longer being received at Vin terminal <NUM>, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and NFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the UPS operation mode when Vin is less than Vbat, two current paths are formed in the circuit <NUM> substantially the same as during the OTG operation mode when Vin is less than Vbat and during the discharge operation mode, the details of which are not repeated herein.

<FIG> shows a schematic diagram of an illustrative circuit <NUM> in accordance with the invention defined in the claims. In some examples, the circuit <NUM> is a power management circuit, for example, suitable for implementation as the controller <NUM> of the system <NUM> of <FIG>, described above. Further, in some examples, at least some elements of the circuit <NUM> are substantially similar in form and/or function to elements of the circuit <NUM> of <FIG>, and reference is made in <FIG> to the elements of circuit <NUM>. The circuit <NUM> includes the elements of circuit <NUM> and a PFET <NUM>. The addition of the PFET <NUM> to the architecture of circuit <NUM> to form circuit <NUM> provides for enhanced functionality including at least controlling an amount of inrush current conveyed by the circuit <NUM> from the Vin terminal <NUM> to the Vout terminal <NUM> and/or providing a mechanism for disconnecting the Vout terminal <NUM> from the Vin terminal <NUM>, for example, to protect the Vin terminal <NUM> from over current, over voltage, or an electrical short in a load (not shown) coupled to the Vout terminal <NUM>.

In an example architecture of the circuit <NUM>, a source terminal of the PFET <NUM> is coupled to a node <NUM> and a drain terminal of the PFET <NUM> is coupled to the Vin terminal <NUM>. The capacitor <NUM> is coupled between the node <NUM> and a ground voltage potential <NUM>. The resistor <NUM> is coupled between the node <NUM> and a first terminal of the inductor <NUM>, and a second terminal of the inductor <NUM> is coupled to a node <NUM>. A source terminal of the PFET <NUM> is coupled to the node <NUM> and a drain terminal of the PFET <NUM> is coupled to the Vout terminal <NUM>. A source terminal of the PFET <NUM> is coupled to the ground voltage potential <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. The capacitor <NUM> is coupled between the Vout terminal <NUM> and the ground voltage potential <NUM>. A source terminal of the PFET <NUM> is coupled to the node <NUM> and a drain terminal of the PFET <NUM> is coupled to the Vout terminal <NUM>. A source terminal of the PFET <NUM> is coupled to the ground voltage potential <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. The inductor <NUM> is coupled between the node <NUM> and a node <NUM>. A source terminal of the NFET <NUM> is coupled to the Vout terminal <NUM> and a drain terminal of the NFET <NUM> is coupled to the node <NUM>. The resistor <NUM> is coupled between the node <NUM> and the Vbat terminal <NUM>. The capacitor <NUM> is coupled between the Vout terminal <NUM> and the ground voltage potential <NUM>. In at least some examples, the battery <NUM> is coupled between the Vbat terminal <NUM> and the ground voltage potential <NUM>. Further, the charger controller <NUM> is coupled to gate terminals of each of the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and PFET <NUM>.

The charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and/or PFET <NUM> to operate the circuit <NUM> in one of a plurality of operation modes. For example, during a charging operation mode, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and/or PFET <NUM> to provide energy from the Vin terminal <NUM> to both the Vout terminal <NUM> (e.g., to power devices (not shown) coupled to the Vout terminal <NUM>) and the Vbat terminal <NUM> (e.g., to charge the battery <NUM>). The charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and/or PFET <NUM>, in some examples, at least partially based on Ctrl (not shown). Ctrl indicates, in some examples, a value of Vin with respect to a value of Vbat. For examples, Ctrl indicates whether Vin is greater than or less than Vbat. Ctrl is received by the charger controller <NUM>, in some examples, from a device or component outside of, but coupled to, the circuit <NUM>. In other examples, Ctrl is received by the charger controller <NUM> from a component (not shown) within the circuit <NUM>. In yet other examples, Ctrl is determined by the charger controller <NUM> based on couplings (not shown) between the charger controller <NUM> and each of the Vin terminal <NUM> and the Vbat terminal <NUM>. In some examples, the charger controller <NUM> further controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and/or PFET <NUM> based on an additional received or generated signal (not shown) specifying an operation mode (e.g., such as one of the operation modes described below) for the circuit <NUM>.

During the charging operation mode when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, NFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the charging operation mode when Vin is less than Vbat, two current paths are formed in the circuit <NUM>. The first current path passes through the PFET <NUM>, resistor <NUM>, inductor <NUM>, and PFET <NUM> and provides power from the Vin terminal <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes through the PFET <NUM>, resistor <NUM>, inductor <NUM>, PFET <NUM>, NFET <NUM>, and resistor <NUM> and provides power from the Vin terminal <NUM> to the Vbat terminal <NUM> or from the Vin terminal <NUM> through the PFET <NUM>, resistor <NUM>, inductor <NUM>, and PFET <NUM> to the ground voltage potential <NUM>.

During the charging operation mode when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the charging operation mode when Vin is greater than Vbat, two current paths are formed in the circuit <NUM>. The first current path passes through the PFET <NUM>, resistor <NUM>, inductor <NUM>, and PFET <NUM> and provides power from the Vin terminal <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes through the PFET <NUM>, resistor <NUM>, inductor <NUM>, PFET <NUM>, PFET <NUM>, inductor <NUM>, and resistor <NUM> and provides power from the Vin terminal <NUM> to the Vbat terminal <NUM> or through the PFET <NUM>, inductor <NUM>, and resistor <NUM> to the Vbat terminal <NUM>.

During an OTG operation mode when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, NFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the OTG operation mode when Vin is less than Vbat, a current path is formed from the Vbat terminal <NUM> to the Vin terminal <NUM>. The current path alternatingly passes from the Vbat terminal <NUM> through the resistor <NUM>, NFET <NUM>, PFET <NUM>, inductor <NUM>, and resistor <NUM> or through the PFET <NUM>, inductor <NUM>, resistor <NUM>, and PFET <NUM> to the Vin terminal <NUM>.

In at least some examples, the charger controller <NUM> controls the PFET <NUM> and the PFET <NUM> to selectively activate and deactivate at a duty cycle selected such that the inductor <NUM>, PFET <NUM>, PFET <NUM> form a buck converter. For example, when the PFET <NUM> is active and conducting energy between its source and drain terminals, the inductor <NUM> is charging. When the PFET <NUM> is active and the PFET <NUM> is inactive, the inductor <NUM> is charging and power is not provided to the Vin terminal <NUM> from the Vbat terminal <NUM>. When the PFET <NUM> is inactive and the PFET <NUM> is active, the inductor <NUM> discharges to the Vin terminal <NUM>. Based on the duty cycle selected for control of the PFET <NUM> and the PFET <NUM> by the charger controller <NUM>, and an inductance value of the inductor <NUM>, a value of Vbat is reduced prior to being provided to the Vin terminal <NUM>.

During the OTG operation mode when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the OTG operation mode when Vin is greater than Vbat, a current path is formed from the Vbat terminal <NUM> to the Vin terminal <NUM>. The current path passes from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, PFET <NUM>, PFET <NUM>, inductor <NUM>, resistor <NUM>, and PFET <NUM>.

During a turbo operation mode, a demand by a load (not shown) coupled to the Vout terminal <NUM> is greater than can be satisfied by Vin and the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the turbo operation mode, two current paths are formed in the circuit <NUM>. The first current path passes from the Vin terminal <NUM> through the PFET <NUM>, resistor <NUM>, inductor <NUM>, and PFET <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the Vout terminal <NUM> or from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the ground voltage potential <NUM>.

During an UPS operation mode, Vbat supplements power provided to the Vout terminal <NUM> by Vin, and provides power to the Vin terminal <NUM>. During the UPS operation mode, when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, NFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the UPS operation mode when Vin is less than Vbat, two current paths are formed in the circuit <NUM> substantially the same as during the OTG operation mode when Vin is less than Vbat and during the discharge operation mode, the details of which are not repeated herein.

During the UPS operation mode, when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the UPS operation mode when Vin is greater than Vbat, two current paths are formed in the circuit <NUM> substantially the same as during the OTG operation mode when Vin is greater than Vbat and during the turbo operation mode when Vin is greater than Vbat, the details of which are not repeated herein.

<FIG> shows a schematic diagram of an illustrative circuit <NUM> in accordance with an alternative solution. In some examples, the circuit <NUM> is a power management circuit, for example, suitable for implementation as the controller <NUM> of the system <NUM> of <FIG>, described above. At least some elements of the circuit <NUM> are substantially similar in form and/or function to elements of the circuit <NUM> of <FIG>, and reference is made in <FIG> to the elements of circuit <NUM>. The circuit <NUM> includes the elements of circuit <NUM> and a PFET <NUM>. In at least some examples, the addition of the PFET <NUM> to the architecture of circuit <NUM> to form circuit <NUM> provides for enhanced functionality including at least controlling an amount of inrush current conveyed by the circuit <NUM> from the Vin terminal <NUM> to the Vout terminal <NUM> and/or providing a mechanism for disconnecting the Vout terminal <NUM> from the Vin terminal <NUM>, for example, to protect the Vin terminal <NUM> from over current, over voltage, or an electrical short in a load (not shown) coupled to the Vout terminal <NUM>. Also, in some examples the PFET <NUM> provides for selectable isolation of the Vout terminal <NUM> from node <NUM> such that a signal present at node <NUM> may have a value (e.g., a voltage) higher than Vout, for example, when the Vbat terminal <NUM> is coupled to the Vin terminal <NUM> and the Vout terminal <NUM> and Vbat is boosted prior to delivery to the Vin terminal <NUM> but not prior to delivery to the Vout terminal <NUM>. Although not shown, in some examples the circuit <NUM> further includes the PFET <NUM> as shown and described with respect to the circuit <NUM> of <FIG>.

In the circuit <NUM>, the capacitor <NUM> is coupled between the Vin terminal <NUM> and a ground voltage potential <NUM>. The resistor <NUM> is coupled between the Vin terminal <NUM> and a first terminal of the inductor <NUM>, and a second terminal of the inductor <NUM> is coupled to a node <NUM>. A source terminal of the PFET <NUM> is coupled to the node <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. A source terminal of the PFET <NUM> is coupled to the ground voltage potential <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. The capacitor <NUM> is coupled between the node <NUM> and the ground voltage potential <NUM>. A source terminal of the PFET <NUM> is coupled to the node <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. A source terminal of the PFET <NUM> is coupled to the ground voltage potential <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. The inductor <NUM> is coupled between the node <NUM> and a node <NUM>. A source terminal of the NFET <NUM> is coupled to the Vout terminal <NUM> and a drain terminal of the NFET <NUM> is coupled to the node <NUM>. The resistor <NUM> is coupled between the node <NUM> and the Vbat terminal <NUM>. A source terminal of the PFET <NUM> is coupled to the Vout terminal <NUM> and a drain terminal of the PFET <NUM> is coupled to the node <NUM>. The capacitor <NUM> is coupled between the Vout terminal <NUM> and the ground voltage potential <NUM>. In at least some examples, the battery <NUM> is coupled between the Vbat terminal <NUM> and the ground voltage potential <NUM>. Further, the charger controller <NUM> is coupled to gate terminals of each of the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and PFET <NUM>.

In operation of the circuit <NUM>, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and/or PFET <NUM> to operate the circuit <NUM> in one of a plurality of operation modes. For example, during a charging operation mode, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and/or PFET <NUM> to provide energy from the Vin terminal <NUM> to both the Vout terminal <NUM> (e.g., to power devices (not shown) coupled to the Vout terminal <NUM>) and the Vbat terminal <NUM> (e.g., to charge the battery <NUM>). The charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and/or PFET <NUM>, in some examples, at least partially based on Ctrl (not shown). Ctrl indicates, in some examples, a value of Vin with respect to a value of Vbat. For examples, Ctrl indicates whether Vin is greater than or less than Vbat. Ctrl is received by the charger controller <NUM>, in some examples, from a device or component outside of, but coupled to, the circuit <NUM>. In other examples, Ctrl is received by the charger controller <NUM> from a component (not shown) within the circuit <NUM>. In yet other examples, Ctrl is determined by the charger controller <NUM> based on couplings (not shown) between the charger controller <NUM> and each of the Vin terminal <NUM> and the Vbat terminal <NUM>. In some examples, the charger controller <NUM> further controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and/or PFET <NUM> based on an additional received or generated signal (not shown) specifying an operation mode (e.g., such as one of the operation modes described below) for the circuit <NUM>.

During the charging operation mode when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, NFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the charging operation mode when Vin is less than Vbat, two current paths are formed in the circuit <NUM>. The first current path passes through the resistor <NUM>, inductor <NUM>, PFET <NUM>, and PFET <NUM> and provides power from the Vin terminal <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes through the resistor <NUM>, inductor <NUM>, PFET <NUM>, PFET <NUM>, NFET <NUM>, and resistor <NUM> and provides power from the Vin terminal <NUM> to the Vbat terminal <NUM> or from the Vin terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the ground voltage potential <NUM>.

In at least some examples, the charger controller <NUM> controls the PFET <NUM> and the PFET <NUM> to selectively activate and deactivate (e.g., conduct energy between their respective source and drain terminals and not conduct energy between their respective source and drain terminals) at a duty cycle selected such that the inductor <NUM>, PFET <NUM>, PFET <NUM>, capacitor <NUM>, and capacitor <NUM> (when the PFET <NUM> remains active) form a boost converter. For example, when the PFET <NUM> is inactive and not conducting energy between its source and drain terminals and the PFET <NUM> is active and conducting energy between its source and drain terminals, the inductor <NUM> is charging (e.g., storing energy) and energy previously stored in the capacitor <NUM> and the capacitor <NUM> is discharged to the Vbat terminal <NUM> and the Vout terminal <NUM>. When the PFET <NUM> is active and the PFET <NUM> is inactive, the inductor <NUM> discharges to the Vbat terminal <NUM> and the Vout terminal <NUM>, also at least partially recharging the capacitor <NUM> and the capacitor <NUM>. Based on the duty cycle selected for control of the PFET <NUM> and the PFET <NUM> by the charger controller <NUM>, and an inductance value of the inductor <NUM>, a value of Vin is increased (e.g., boosted) prior to being provided to the Vbat terminal <NUM> and the Vout terminal <NUM>.

During the charging operation mode when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the charging operation mode when Vin is greater than Vbat, two current paths are formed in the circuit <NUM>. The first current path passes through the resistor <NUM>, inductor <NUM>, PFET <NUM>, and PFET <NUM> and provides power from the Vin terminal <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes through the resistor <NUM>, inductor <NUM>, PFET <NUM>, PFET <NUM>, inductor <NUM>, and resistor <NUM> and provides power from the Vin terminal <NUM> to the Vbat terminal <NUM> or through the PFET <NUM>, inductor <NUM>, and resistor <NUM> to the Vbat terminal <NUM>.

During an OTG operation mode when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, NFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the OTG operation mode when Vin is less than Vbat, a current path is formed from the Vbat terminal <NUM> to the Vin terminal <NUM>. The current path alternatingly passes from the Vbat terminal <NUM> through the resistor <NUM>, NFET <NUM>, PFET <NUM>, PFET <NUM>, inductor <NUM>, and resistor <NUM> or through the PFET <NUM>, inductor <NUM>, and resistor <NUM> to the Vin terminal <NUM>.

During the OTG operation mode when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the OTG operation mode when Vin is greater than Vbat, a current path is formed from the Vbat terminal <NUM> to the Vin terminal <NUM>. The current path passes from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, PFET <NUM>, PFET <NUM>, inductor <NUM>, and resistor <NUM> to the Vin terminal <NUM>.

In a battery conservation operation mode, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals to establish a current path from the Vbat terminal <NUM> through the inductor <NUM> and PFET <NUM> to the node <NUM>. For example, the charger controller <NUM> controls the PFET <NUM> and the PFET <NUM> to not conduct energy between their respective source and drain terminals such that energy flowing into the node <NUM> charges the capacitor <NUM> without being passed to the Vin terminal <NUM> or the Vout terminal <NUM>. Charging the capacitor <NUM>, in some examples, enables use of the capacitor <NUM> to satisfy burst requirements (e.g., sudden spikes in demand from a load (not shown) coupled to the Vout terminal <NUM>) during operation of the circuit <NUM>. In some examples, the PFET <NUM> may be activated, or deactivated, to couple the node <NUM> to the Vin terminal <NUM> based on a desired function of the circuit <NUM> during the battery conservation operation mode. In at least one example, operation of the circuit <NUM> during the battery conservation operation mode is performed substantially similar to operation of the circuit <NUM> during the OTG operation mode when Vin is less than Vbat.

During a turbo operation mode, a demand by a load (not shown) coupled to the Vout terminal <NUM> is greater than can be satisfied by Vin and the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the turbo operation mode, two current paths are formed in the circuit <NUM>. The first current path passes from the Vin terminal <NUM> through, resistor <NUM>, inductor <NUM>, PFET <NUM>, and PFET <NUM> to the Vout terminal <NUM>. The second current path alternatingly passes from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the Vout terminal <NUM> or from the Vbat terminal <NUM> through the resistor <NUM>, inductor <NUM>, and PFET <NUM> to the ground voltage potential <NUM>.

During a UPS operation mode, Vbat supplements power provided to the Vout terminal <NUM> by Vin, and provides power to the Vin terminal <NUM>. During the UPS operation mode, when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, NFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the UPS operation mode when Vin is less than Vbat, two current paths are formed in the circuit <NUM> substantially the same as during the OTG operation mode when Vin is less than Vbat and during the discharge operation mode, the details of which are not repeated herein.

During the UPS operation mode, when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals. During the UPS operation mode when Vin is greater than Vbat, two current paths are formed in the circuit <NUM> substantially the same as during the OTG operation mode when Vin is greater than Vbat and during the turbo operation mode when Vin is greater than Vbat, the details of which are not repeated herein.

<FIG> shows a timing diagram <NUM> of illustrative signals. The diagram <NUM> is illustrative of at least one example architecture and operation of the circuit <NUM>, described above with reference to <FIG>. The diagram <NUM> illustrates a PFET <NUM> control signal, a PFET <NUM> control signal, a PFET <NUM> control signal, a PFET <NUM> control signal, an NFET <NUM> control signal, and a PFET <NUM> control signal. Each of the control signals, in some examples, exists in either an active state (in which the corresponding transistor is active and conducting) or inactive (in which the corresponding transistor is inactive and not conducting). In some examples, each of the control signals is generated by the charger controller <NUM> and is provided to a gate terminal of the respective transistor that is under control via the control signal. The diagram <NUM> further illustrates Vin, Vbat, and a Charge Status signal. The Charge Status signal, in some examples, indicates whether the battery <NUM> of <FIG> is charging. The Charge Status signal, in some examples, is generated by the charger controller <NUM> based at least partially on a status of one or more control signals generated and output by the charger controller <NUM> (e.g., such as the PFET <NUM> control signal, the PFET <NUM> control signal, the PFET <NUM> control signal, the PFET <NUM> control signal, the NFET <NUM> control signal, and/or the PFET <NUM> control signal).

As shown along the horizontal axis of the diagram <NUM> as described above with respect to <FIG>, each operation mode of the circuit <NUM> corresponds to a unique combination of states of the controls signals generated by the charger controller <NUM>. In some examples, by omitting the PFET <NUM> control signal, the diagram <NUM> is representative of operation of the circuit <NUM>. Also, in some examples, by modifying the PFET <NUM> control signal according to the descriptions of <FIG>, the diagram <NUM> is representative of operation of the circuit <NUM> and by maintaining the PFET <NUM> in a constant active state, the diagram <NUM> is representative of operations of the circuit <NUM>.

As illustrated in diagram <NUM>, the circuit <NUM> is configured to operate in a plurality of operation modes based on control signals provided to the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and NFET <NUM>, as well the value of Vin with respect to the value of Vbat. For each operation mode, one or more current paths are formed in the circuit <NUM>. For example, when Vin is greater than Vbat and the turbo boost mode is active in the circuit <NUM>, current paths as shown in <FIG> are formed. When Vin is greater than Vbat and the turbo boost mode is not active in the circuit <NUM>, in at least one example, current paths as shown in <FIG> are formed. Similarly, when Vin is approximately equal to Vbat (such as during operation while in a buck-boost region) and the circuit <NUM> is in a charging mode, in at least one example, current paths as shown in <FIG> are formed. When Vin is less than Vbat and the circuit <NUM> is in the charging mode, in at least one example, current paths as shown in <FIG> are formed. While during a discharging mode of the circuit <NUM>, when Vbat is greater than Vin, in at least one example, current paths as shown in <FIG> are formed. When Vbat is approximately equal to Vin (such as during operation while in a buck-boost region) and the circuit <NUM> is in the discharging mode, in at least one example, current paths as shown in <FIG> are formed. When Vbat is less than Vin and the circuit <NUM> is in the discharging mode, in at least one example, current paths as shown in <FIG> are formed. When the circuit <NUM> is discharging from Vbat terminal <NUM> to Vout terminal <NUM>, in at least one example, current paths as shown in <FIG> are formed.

<FIG> shows a schematic diagram of an illustrative circuit <NUM> not being in accordance with the invention defined in the claims. In some examples, the circuit <NUM> is a power management circuit, for example, suitable for implementation as the controller <NUM> of the system <NUM> of <FIG>, described above. In some examples, the circuit <NUM> includes, or is configured to couple to, an inductor <NUM>, a capacitor <NUM>, a resistor <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM> a capacitor <NUM>, a resistor <NUM>, and/or a charger controller <NUM>, along with a Vin terminal <NUM> at which a signal Vin is present, Node <NUM> at which a signal Vbat is present, and Vout terminal <NUM> at which a signal Vout is present. In some examples, the circuit <NUM> further includes, or is configured to couple to, a battery <NUM>. In at least one example, the charger controller <NUM> is a processor or microprocessor suitable for monitoring one or more input signals and generating one or more output signals based on determinations made according to values of at least some of the one or more input signals. In other examples, the charger controller <NUM> is any analog, digital or mixed-signal circuit suitable for performing the signal monitoring and generation as described above. Also, while certain devices are described herein as PFET, in some examples the devices are replaced by another device of substantially similar functionality (e.g., replacing PFET with NFET, either PFET or NFET with bi-polar junction transistor (BJT), etc.), the scope of which is not limited herein. For example, in certain high-power applications, such as high-power switching converters, it may be desirable to replace PFET devices with NFET devices.

In an example architecture of the circuit <NUM>, the capacitor <NUM> is coupled between the Vin terminal <NUM> and a ground voltage potential <NUM>. The resistor <NUM> is coupled between the Vin terminal <NUM> and a Vbat terminal <NUM>. A drain terminal of the PFET <NUM> is coupled to the Vbat terminal <NUM> and a source terminal of the PFET <NUM> is coupled to a node <NUM>. A drain terminal of the PFET <NUM> is coupled to the node <NUM> and a source terminal of the PFET <NUM> is coupled to the ground voltage potential <NUM>. A drain terminal of the PFET <NUM> is coupled to the Vbat terminal <NUM> and a source terminal of the PFET <NUM> is coupled to a node <NUM>. A source terminal of the PFET <NUM> is coupled to the node <NUM> and a drain terminal of the PFET <NUM> is coupled to the Vout terminal <NUM>. A drain terminal of the PFET <NUM> is coupled to the Vout terminal <NUM> and a source terminal of the PFET <NUM> is coupled to a node <NUM>. A drain terminal of the PFET <NUM> is coupled to the node <NUM> and a source terminal of the PFET <NUM> is coupled to the ground voltage potential <NUM>. The inductor <NUM> is coupled between the node <NUM> and the node <NUM>. A drain terminal of the PFET <NUM> is coupled to the node <NUM> and a source terminal of the PFET <NUM> is coupled to a node <NUM>. A source terminal of the PFET <NUM> is coupled to the node <NUM> and a drain terminal of the PFET <NUM> is coupled to the Node <NUM>. A drain terminal of the PFET <NUM> is coupled to the Vout terminal <NUM> and a source terminal of the PFET <NUM> is coupled to the Node <NUM>. The capacitor <NUM> is coupled between the Vout terminal <NUM> and the ground voltage potential <NUM>. The resistor <NUM> is coupled between the node <NUM> and the Vbat terminal <NUM>. In at least some examples, the battery <NUM> is coupled between the Vbat terminal <NUM> and the ground voltage potential <NUM>. Further, the charger controller <NUM> is coupled to gate terminals of each of the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM>, to the node <NUM>, and to the node <NUM>.

In an example of operation of the circuit <NUM>, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and/or PFET <NUM> to operate the circuit <NUM> in one of a plurality of operation modes. For example, during a charging operation mode, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and/or PFET <NUM> to provide energy from the Vin terminal <NUM> to both the Vout terminal <NUM> (e.g., to power devices (not shown) coupled to the Vout terminal <NUM>) and to the Vbat terminal <NUM> (e.g., to charge the battery <NUM>). The charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and/or PFET <NUM>, in some examples, at least partially based on Ctrl (not shown). Ctrl indicates, in some examples, a value of Vin with respect to a value of Vbat. For examples, Ctrl indicates whether Vin is greater than or less than Vbat. Ctrl is received by the charger controller <NUM>, in some examples, from a device or component outside of, but coupled to, the circuit <NUM>. In other examples, Ctrl is received by the charger controller <NUM> from a component (not shown) within the circuit <NUM>. In yet other examples, Ctrl is determined by the charger controller <NUM> based on couplings (not shown) between the charger controller <NUM> and each of the Vin terminal <NUM> and the Vbat terminal <NUM>. In some examples, the charger controller <NUM> further controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and/or PFET <NUM> based on an additional received or generated signal (not shown) specifying an operation mode (e.g., such as one of the operation modes described below) for the circuit <NUM>.

During the charging operation mode when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, in one example, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and PFET <NUM> (e.g., based at least partially on a value of a signal provided to their respective gate terminals) to conduct (or not conduct) energy between their respective source and drain terminals to form a path between the Vin terminal <NUM> and the Vout terminal <NUM>. In another example when Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> (e.g., based at least partially on a value of a signal provided to their respective gate terminals) to conduct (or not conduct) energy between their respective source and drain terminals to form a path between the Vin terminal <NUM> and the Vbat terminal <NUM>.

During the charging operation mode when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, in one example, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals to form a path between the Vin terminal <NUM> and the Vout terminal <NUM>. In another example, when Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> (e.g., based at least partially on a value of a signal provided to their respective gate terminals) to conduct (or not conduct) energy between their respective source and drain terminals to form a path between the Vin terminal <NUM> and the Vbat terminal <NUM>.

During a discharge operation mode (e.g., when Vin is not received by the circuit <NUM> at the Vin terminal <NUM>), the charger controller <NUM> controls the PFET <NUM> to conduct energy between its source and drain terminals. During the discharge operation mode a current path is formed passes from the Vbat terminal <NUM> through the resistor <NUM> and PFET <NUM> to the Vout terminal <NUM>.

During an OTG operation mode when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, or when in a battery reserve operation mode, in one example, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals to form a path from the Vbat terminal <NUM> to the Vin terminal <NUM>. In another example, when Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals to form a path from the Vbat terminal <NUM> to the Vin terminal <NUM>.

During a turbo operation mode (sometimes referred to as a hybrid operation mode or a turbo boost mode), a demand by a load (not shown) coupled to the Vout terminal <NUM> is greater than can be satisfied by Vin and the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM>, to conduct (or not conduct) energy between their respective source and drain terminals to form two current paths in the circuit <NUM>. The first current path passes from the Vin terminal <NUM> to the Vout terminal <NUM> and the second current path passes from the Vbat terminal <NUM> to the Vout terminal <NUM>.

During a UPS operation mode, Vbat supplements power provided to the Vout terminal <NUM> by Vin, and provides power to the Vin terminal <NUM>. During the UPS operation mode and when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals to form a current path between the Vbat terminal <NUM> and the Vin terminal <NUM>. During the UPS operation mode and when Ctrl indicates to the charger controller <NUM> that Vin is less than Vbat, the charger controller <NUM> also controls the PFET <NUM> to conduct (or not conduct) energy between its source and drain terminals to form a current path between the Vbat terminal <NUM> and the Vout terminal <NUM>. During the UPS operation mode and when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals to form a current path between the Vbat terminal <NUM> and the Vin terminal <NUM>. During the UPS operation mode and when Ctrl indicates to the charger controller <NUM> that Vin is greater than Vbat, the charger controller <NUM> also controls the PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, PFET <NUM>, and PFET <NUM> to conduct (or not conduct) energy between their respective source and drain terminals to form a current path between the Vbat terminal <NUM> and the Vout terminal <NUM>.

<FIG> shows a table <NUM> of illustrative circuit characteristics. In at least some examples, the table <NUM> compares characteristics of a typical circuit implementation (not shown herein) with the circuit <NUM>, circuit <NUM>, circuit <NUM>, and circuit <NUM> disclosed herein. For example, the table <NUM> compares a number of power components (e.g., such as switches and/or inductors) in a current path of the respective circuit <NUM>, circuit <NUM>, circuit <NUM>, and circuit <NUM> for a given mode of operation. As shown in <FIG>, the circuit <NUM>, circuit <NUM>, and circuit <NUM> each provide for a reduced number of transistors in at least some current paths for at least some modes of operation, thereby improving operational efficiency of the respective circuit <NUM>, circuit <NUM>, and/or circuit <NUM>.

A device that is "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

Also, in this description, the phrase "ground voltage potential" includes a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated herein, the terms "about", "approximately" or "substantially" preceding a value mean +/- ten (<NUM>) percent of the stated value.

Claim 1:
A power management circuit, comprising:
a first inductor (<NUM>) having a first terminal configured to couple to a first node and a second terminal configured to couple to a second node (<NUM>);
a first p-type metal oxide semiconductor field effect transistor MOSFET PFET (<NUM>) having a source terminal coupled to the second node (<NUM>) and a drain terminal coupled to a third node;
a second PFET (<NUM>) having a source terminal coupled to a ground voltage potential (<NUM>) and a drain terminal coupled to the second node (<NUM>);
a third PFET (<NUM>) having a source terminal coupled to a fourth node (<NUM>) and a drain terminal coupled to the third node;
a fourth PFET (<NUM>) having a source terminal coupled to the ground voltage potential (<NUM>) and a drain terminal coupled to the fourth node (<NUM>);
a n-type MOSFET NFET (<NUM>) having a drain terminal coupled to a fifth node (<NUM>) and a source terminal coupled to the third node;
a second inductor (<NUM>) having a first terminal configured to couple to the fourth node (<NUM>) and a second terminal configured to couple to the fifth node (<NUM>); and
a controller (<NUM>) coupled to a gate terminal of the first PFET (<NUM>), a gate terminal of the second PFET (<NUM>), a gate terminal of the third PFET (<NUM>), a gate terminal of the fourth PFET (<NUM>), and a gate terminal of the NFET (<NUM>).