Patent Description:
Prior art documents <CIT>, <CIT>, and <CIT> disclose various circuit arrangements where bias currents are checked by the circuits themselves.

Many safety-compliant implementations, such as systems employed in automotive or aeronautic systems, mandate frequent real-time monitoring of the bias generator and the voltages and bias currents generated therefrom. However, given the sheer number of bias currents often generated by a bias generator in such systems, it often can be difficult to adequately test the bias generator in a test period that is sufficiently short to avoid impacting the operating time or efficiency of the electronic system.

In accordance with one aspect, a method includes grouping a plurality of bias currents generated by a bias generator into a plurality of subsets, at least one subset having two or more bias currents of the plurality of bias currents, and testing the bias generator by successively testing each subset of bias currents as a corresponding single test bias current.

The method further can include one or more of the following features, individually or in combination. The method further can include for each subset of bias currents: configuring a variable resistor to have a corresponding resistance based on the number of bias currents represented in the subset; providing a corresponding test current to the variable resistor configured to the corresponding resistance, the test current representing a combination of all bias currents of the corresponding subset; and determining a test status for the subset of bias currents based on a voltage across the variable resistor resulting from conducting the corresponding test current. Determining the test status for the subset of bias currents can include: converting the voltage across the variable resistor to a corresponding test digital value; and determining the test status based on a comparison of the test digital value with at least one of a predetermined digital value or a predetermined range of digital values. Determining the test status for the subset of bias currents further can include identifying a failed test status responsive to at least one of the test digital value differing from the predetermined digital value by more than a specified threshold or exceeding the test digital value falling outside the predetermined range. Configuring the variable resistor to have a corresponding resistance can include configuring the variable resistor to have a resistance inversely proportional to the number of bias currents in the subset. Conducting the corresponding test current through the variable resistor can include conducting the corresponding test current from the bias generator to the variable resistor over a conductive bus used for other testing processes for a system having the bias generator. Providing the corresponding test current to the variable resistor further can include providing the corresponding test current from the bias generator to the variable resistor over a conductive bus used for other testing processes for a system having the bias generator. The method thus can further include generating the plurality of bias currents based on a plurality of drive voltages and testing the bias generator further by, for each drive voltage of at least a subset of the plurality of drive voltages, providing the drive voltage over the conductive bus to an input of an analog-to-digital converter (ADC), converting the provided drive voltage at the ADC to a corresponding test digital value, and determining a test status of the bias generator based on a comparison of the test digital value to at least one of predetermined digital value or a predetermined range of values. Each subset can have the same number of bias currents, or at least one subset can have a different number of bias currents than another subset.

In accordance with another aspect, a device includes a bias generator configured to generate a plurality of bias currents and a testing module configured to test the bias generator by successively testing each subset of bias currents of a plurality of subsets of bias currents grouped from the plurality of bias currents as a corresponding single test current.

The device further can include one or more of the following features, individually or in combination. The device further can include a variable resistor, and wherein the testing module is configured to test the bias generator by: for each subset of bias currents: configuring the variable resistor to have a corresponding resistance based on the number of bias currents represented in the subset; conducting a corresponding test current through the variable resistor configured to the corresponding resistance, the test current representing a combination of all bias currents of the corresponding subset; and determining a test status for the subset of bias currents based on a voltage across the variable resistor resulting from conducting the corresponding test current. The testing module can be configured to determine a test status for the subset of bias currents by: converting the voltage across the variable resistor to a corresponding test digital value; and determining the test status based on a comparison of the test digital value with at least one of a predetermined digital value or a predetermined range of values. The testing module can be further configured to determine a test status for the subset of bias currents further by identifying a failed test status responsive to at least one of the test digital value differing from the predetermined digital value by more than a specified threshold or the test digital value falling outside the predetermined range. The testing module can be configured to configure the variable resistor to have a corresponding resistance by configuring the variable resistor to have a resistance inversely proportional to the number of bias currents in the subset. The device further can comprise a conductive bus coupling the bias generator to the variable resistor, and wherein the bias generator is configured to generate the plurality of bias currents based on a plurality of drive voltages, and wherein the testing module is further configured to test the bias generator by: for each drive voltage of at least a subset of the plurality of drive voltages: receiving the drive voltage over the conductive bus at an input of an ADC of the testing module; converting the provided drive voltage at the ADC to a corresponding test digital value; and determining a test status of the bias generator based on a comparison of the test digital value to a predetermined digital value. Each subset can have the same number of bias currents, or at least one subset can have a different number of bias currents than another subset.

In accordance with yet another aspect, an electronic device includes a plurality of circuit blocks, a bias generator configured to provide a plurality of bias currents to the plurality of circuit blocks, and a testing module configured to perform a multi-stage test of the bias generator, the multi-stage test including a voltage test stage and a bias current test stage, wherein for the voltage test stage the testing module is configured to convert each drive voltage of a set of one or more drive voltages of the bias generator to a corresponding test digital value and determine a test status of the drive voltage based on a comparison of the test digital value to at least one of a predetermined digital value or a predetermined range of digital values, and wherein for the bias current test stage the testing module is configured to group a plurality of bias currents of the bias generator into a plurality of subsets, at least one subset having more than one bias current, and further configured to determine a corresponding test status for each subset by generating a test voltage for the subset using a single test current generated from the subset, the single test current representing a combination of all of the bias currents of the subset, and by comparing a test digital value generated from the test voltage with at least one of a predetermined digital value or a predetermined range of digital values. The electronic device further can include a bus comprising at least one conductive line, wherein the bias generator has an interface to the bus, the interface configurable to either provide a drive voltage of the bias generator to the bus or to provide the bias currents of a selected subset in parallel to the bus, and wherein the testing module has an ADC, a variable resistor, and a switch selectively coupling one terminal of the variable resistor to an input of the ADC, the input of the ADC further coupled to the bus, and wherein the switch is configured to connect the variable resistor to the input of the ADC for the bias current test stage and disconnect the variable resistor from the input of the ADC for the voltage test stage. Further, the circuit blocks can include circuit blocks of a radar device and the multi-stage test can be performed either prior to or following an operational radar transmit/receive stage using the circuit blocks.

The present disclosure is better understood, and its numerous features and advantages made apparent to those skilled in the art, by referencing the accompanying drawings.

Real-time, or during field operation, testing of a bias generator in an electronic system can negatively impact the functional efficacy of the electronic system depending on the duration needed to conduct such testing. For example, in an automotive millimeter wave (mmW) radar implementation, safety considerations often mandate performing safety functional checks of certain subsystems, including bias generators, for each transmit ("chirp") cycle of a radar device. As the radar device typically is unable to transmit or receive while this safety functional check is being conducted, the longer it takes to perform the safety functional test, the longer the transmit/receive cycle of the radar device needs to be, and thus the less frequently the mmW radar system can perform radar detection.

Conventionally, the testing process for the bias currents supplied by a bias generator involves testing each bias current in sequence. In a complex system in which many bias currents are generated by the bias generator, this sequential testing approach can require a significant amount of time to complete and thus impede efficient operation of the overall system since the time used for testing consequently is unavailable for radar detection operations. Accordingly, disclosed herein are systems and techniques for efficient bias current generation testing based on grouping of bias currents for testing. In at least one embodiment, a testing module configures the bias generator to supply a plurality of bias currents generated by the bias generator for testing by grouping subsets of the plurality of bias currents and sequentially testing the subsets of bias currents. In this approach, the bias currents of a given subset are combined into a single test current that is provided to a variable resistor to generate a test voltage across the resistor due to conduction of the test current through the variable resistor. The test voltage is converted to a test digital value, and this test digital value is compared to a specified, or predetermined, expected digital value for the test. If the test digital value is within a specified threshold of the expected digital value, the testing module identifies the test status for the corresponding subset of bias currents as "passed" and moves on to testing the next subset of bias currents in the same manner. Otherwise, if the test digital value differs from the expected digital value by more than the threshold amount, the testing module identifies the test status for the corresponding subset of bias currents as "failed" and asserts a flag that is then acted upon by the system. As some or all of the subsets of bias currents include multiple bias currents, this grouping-based testing process can be conducted faster than an individual current testing process, and thereby provide for more rapid and efficient real-time safe operation testing.

Further, in some embodiments this grouping-based bias current testing approach can be integrated into a two-phase bias generator testing process. In many instances, a bias generator utilizes voltage-based current generators to generate the bias currents, and thus if a drive voltage used for current generation are out of specification, it is unlikely that the bias currents generated from the out-of-specification drive voltage are likely to be within specification. As such, the drive voltages of the bias generator can be a common cause of failure of the bias generator. Accordingly, the test process can include a first phase for common cause failure testing in which the drive voltages are provided in sequence to the testing module and tested using the same or similar components used to perform the group-based bias testing. In the event that a drive voltage is determined to exceed an acceptable operating range, then a flag can be asserted. Otherwise, if the tested drive voltages are deemed to within their corresponding acceptable operating ranges, then the testing module moves on to the second phase, in which the grouping-based bias current testing is performed as described above and herein.

<FIG> illustrates an electronic device <NUM> employing current-grouping-based bias generator testing in accordance with some embodiments. In the illustrated example, the electronic device <NUM> is employed as an integrated circuit (IC) device, such as a system on a chip (SoC), and thus is also referred to herein as IC device <NUM>. However, it will be appreciated that the electronic device <NUM> may employ multiple ICs, and thus reference to IC device <NUM> in the singular is also understood to extend to a multiple-IC implementation unless otherwise specified. In the depicted embodiment, the IC device <NUM> includes a bias current generator <NUM> (hereinafter, "bias generator <NUM>" for brevity), a plurality of circuit blocks <NUM> (identified as circuit blocks <NUM>-<NUM> to <NUM>-M, M > <NUM>), a testing module <NUM>, and a fault collection and control unit (FCCU) <NUM>. The IC device <NUM> further can include additional components for performing various operations, such as one or more processors <NUM>, one or more memories <NUM>, one or more sensors <NUM>, transmitter (TX)/receiver (RX) components <NUM>, and the like. The circuit blocks <NUM> comprise digital, analog, and/or mixed digital/analog circuitry, which may comprise circuitry of the components of the IC device <NUM>, such as the sensors <NUM> and/or the TX/RX components <NUM>.

The bias current generator <NUM> is configured to generate a plurality of bias currents <NUM> (identified as bias currents <NUM>-<NUM> to <NUM>-N, or IBIAS1 to IBIASN, N><NUM>) that are provided to the circuit blocks <NUM>. Although <FIG> illustrates an example in which there is a one-to-one correspondence between generated bias current <NUM> and circuit block <NUM>, it will be appreciated that in implementation some or all of the circuit blocks <NUM> may receive multiple bias currents from the bias current generator <NUM>, and further the same bias current <NUM> may be supplied to multiple circuit blocks <NUM>. The circuit blocks <NUM> utilize the received bias currents to bias various circuit components (e.g., operational-amplifiers (op-amps), mixers, low noise amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog or mixed analog-digital circuits, individual transistors, and the like). As such, the bias generator <NUM> may be configured to provide various types of bias currents for the circuit blocks <NUM>, such as band-gap-based bias currents, PTAT-based bias currents, or CTAT bias currents, as well as to provide bias currents for a given type but with different slopes so as to facilitate reduced sensitivity to PVT variations.

The circuit blocks <NUM> may implement any of a variety of functions in which rapid bias generator testing would be advantageous or is required per specification or mandate. For example, the IC device <NUM> may implement some or all of the mixed analog and digital circuitry for an automotive radar system. Such systems may be subjected to certain standards for safety assurance, such as the International Organization for Standardization (ISO) <NUM> standard, which specifies an Automotive Safety Integrity Level (ASIL) B that applies to automotive radar systems. ASIL B (as well as higher ASIL levels) requires in-field, or operational, safety checking of bias generators to ensure that the bias currents supplied to the receiving circuit blocks of the IC have the correct, expected input currents. As such, the testing module <NUM> and bias current generator <NUM> cooperate to test, or verify, the operation of the bias generator <NUM> based on this requirement or similar requirements in other contexts.

As described below in greater detail with reference to <FIG>, this testing process can employ a current-grouping bias test process in which, rather than testing each bias current <NUM> individually and sequentially, the testing module <NUM> instead groups the N bias currents <NUM> into a plurality of subsets, with some or all of the subsets having two or more bias currents <NUM>, and then tests each subset of currents sequentially. In this approach, all of the bias currents <NUM> of a given subset under test are effectively "combined" into a single test current and this test current is then tested for compliance. If the test current is found to exceed a specified margin of error, then the testing module <NUM> issues a flag, such as flag <NUM>, which is then analyzed by the FCCU <NUM> in conjunction with other considerations to determine whether an error <NUM> should be asserted. Otherwise, if the test current is found to be within the specified margin of error, the next subset is tested in the same manner, and this process continues until all indicated subsets have been tested. Moreover, in some embodiments, in addition to performing this current-grouping process as one testing stage, another testing stage can be performed to test other common cause failure modes of the bias generator <NUM>, such as by testing the drive voltages generated by the bias generator <NUM> and used by the bias generator <NUM> in generating the bias currents <NUM>. This two-stage test process is described below with reference to <FIG>.

To facilitate testing of the bias generator <NUM>, in at least one embodiment the testing module <NUM> is coupled to the bias generator <NUM> via a conductive bus <NUM>, referred to herein as analog test bus (ATB) <NUM>. The ATB <NUM> comprises one or more conductive lines (e.g., wires or traces) via which the test currents of the bias generator <NUM> and/or the test voltages of the bias generator <NUM> are tested at the testing module <NUM>. In some embodiments, the ATB <NUM> is dedicated for bias generator testing only. In other embodiments, the ATB <NUM> is used for multiple testing procedures in the IC device <NUM>, such as other built-in self-test (BIST) functions, such that the use of the ATB <NUM> for bias generator testing is only one of multiple uses of the ATB <NUM>, thereby facilitating reuse of IC resources for different purposes.

<FIG> illustrates an example implementation of the bias generator <NUM> and the testing module <NUM> in accordance with some embodiments. In the depicted example, the bias generator <NUM> includes a plurality of output current (IOUT) stages <NUM>, such as the depicted output current stages <NUM>-<NUM> and <NUM>-<NUM>. Although two output current stages <NUM> are illustrated, it will be appreciated that any number of output current stages <NUM> may be employed. Each output current stage <NUM> is configured to generate one or more bias currents based on a corresponding drive voltage, and thus includes an input <NUM> to receive the corresponding drive voltage (e.g., Vd1 for output current stage <NUM>-<NUM>, Vd2 for output current stage <NUM>-<NUM>, etc.) and one or more voltage-based current generators <NUM> (such as the illustrated voltage-based current generators <NUM>-<NUM> to <NUM>-K, K >= <NUM>) configured to receive the input drive voltage and generate a corresponding bias current <NUM>,, such as the illustrated bias currents <NUM>-<NUM> to <NUM>-K, also designated as bias currents IBIAS1_SLP1 to IBIAS1_SLPK for the output current stage <NUM>-<NUM> and bias currents IBIAS2_SLP1 to IBIAS2_SLPK for the output current stage <NUM>-<NUM>. These bias currents <NUM> are embodiments of the bias currents <NUM> of <FIG>. Each output current stage <NUM> further includes a switch network <NUM> configured to selectively couple the output of each current generator <NUM> to either a single test output <NUM> common to all of the output current generators <NUM> of the same output current stage <NUM> or to a bias current-specific output that in turn is electrically coupled to an input of a corresponding circuit block <NUM>.

For example, in the illustrated embodiment, a pair of switches <NUM> and <NUM> is implemented at the output of each output current stage <NUM>. The switches <NUM>, <NUM> may be implemented using, for example, a set of one or more transistors. Switch <NUM> has one terminal connected to the output of the output current stage <NUM> and another terminal connected to the test output <NUM> and switch <NUM> has one terminal connected to the output of the output current stage <NUM> and another terminal connected to a corresponding output for providing the resulting bias current to the corresponding circuit block <NUM>. Each of switches <NUM> and <NUM> further includes a switch control input to receive a respective switch control signal that causes the corresponding switch to selectively "open" or "close" the corresponding switch; that is, to render the corresponding switch either non-conductive or conductive, respectively, between its two terminals. Thus, when switch <NUM> is open and switch <NUM> is closed, the output bias current from the corresponding output current generator <NUM> is routed from the output current stage <NUM> to the corresponding circuit block <NUM>, whereas when switch <NUM> is closed and switch <NUM> is open, the output bias current is instead routed to the test output <NUM>. The switch control inputs to the switch network <NUM> of a given output current stage <NUM> are identified using the designators "SWX_T" and "SWX_F", respectively, with "X" identifying the output current generator <NUM> having an output connected to the switch pair, "T" referencing "test" or "trimming" depending on mode, and "F" representing "functional". Thus, SW1_T and SW1_F identifies the switch control inputs to the switches <NUM> and <NUM>, respectively, at the output of the current generator <NUM>-<NUM>, SW2_T and SW2_F identifies the switch control inputs to the switches <NUM> and <NUM>, respectively, at the output of the current generator <NUM>-<NUM>, and so forth. Table <NUM> below illustrates a general configuration of the switch states for the switch network <NUM> depending on one of three modes: trimming; safety check; and functional. The trimming mode represents the configuration employed for the switch network <NUM> while the IC device <NUM> is being produced, a process which typically includes trimming the voltage-based current generators <NUM> due to production variations. The safety check mode represents the configuration employed for the switch network <NUM> for performing testing/validation of the bias generator <NUM> while in the field; and the functional mode represents the configuration employed for the switch network <NUM> while the IC device <NUM> is operational/functioning in the field (that is, when not being tested).

As noted above, each output current stage <NUM> includes one or more current generators <NUM> that generates a corresponding current based on the drive voltage received at the input <NUM> of the output current stage <NUM>. In at least one embodiment, each output current stage <NUM> receives a separate drive voltage, which may be generated as a particular type of reference voltage, such as a temperature-independent voltage, CTAT voltage, or PTAT voltage, and also may have its own slope, so that the bias currents generated by the plurality of output current stages <NUM> have different slopes and modes/types, and thus may provide for reduced bias current sensitivities for PVT variations. In the example of <FIG>, these drive voltages of different types and slopes are generated using a bandgap module <NUM> and a plurality of drive voltage generators <NUM>, such as the illustrated drive voltage generators <NUM>-<NUM> (drive voltage generator <NUM>) and <NUM>-<NUM> (drive voltage generator <NUM>). The bandgap module <NUM> generates a reference voltage <NUM> (VREF) that is intended to not vary in response to changes in temperature and a PTAT reference bias current <NUM> (IBIAS_PTAT) that is intended to be PTAT. One or both references are provided to each drive voltage generator <NUM>, which in turn generates, from the input one or both of VREF and/or IBIAS_PTAT, a corresponding drive voltage <NUM> that is provided to the voltage input <NUM> of a corresponding output current stage <NUM>. Each drive voltage generator <NUM> is configured to provide a separate slope response (or a flat temperature-independent response) and thus provide a drive voltage with a different temperature slope or temperature coefficient (that is, slope relative to temperature). For example, drive voltage generator <NUM>-<NUM> may generate a drive voltage <NUM>-<NUM> (Vd1) with one PTAT slope while drive voltage generator <NUM>-<NUM> may generate a drive voltage <NUM>-<NUM> (Vd2) with a different PTAT slope. Alternatively, these drive voltage generators <NUM>-<NUM> and <NUM>-<NUM>, or other drive voltage generators <NUM> (not shown), may, for example, generate a temperature-independent drive voltage, a CTAT drive voltage with one slope and another CTAT drive voltage with a different slope, and the like. Thus the plurality of drive voltage generators <NUM> provide a set of drive voltages with different slopes (including no slope, or flat) to the different output current generators <NUM> of the bias generator <NUM>. Any of a variety of circuits and combinations thereof may be employed for the drive voltage generators <NUM>, such as a voltage-to-current circuit, diode circuits, and the like. Although one approach to supplying different drive voltages to the output current stages <NUM> is illustrated, it will be appreciated that the bias generator <NUM> can utilize any of a variety of approaches for providing such drive voltages.

The test outputs <NUM> of the plurality of output current stages <NUM>, the drive voltage outputs of the drive voltage generators <NUM>, and the output reference currents of the bandgap module <NUM> are connected to respective inputs of an ATB interface (IF) <NUM>, which in turn has an output connected to a conductive line <NUM> of the ATB <NUM>. The ATB interface <NUM> further includes an input to receive control signaling that configures the ATB interface <NUM> to selectively connect one or more of its inputs to its output. That is, the ATB interface <NUM> acts as an analog multiplexer or switch network to selectively provide either a test voltage (representing one of the drive voltages <NUM>) or a test current (representing one or more of the bias currents <NUM> generated by one or more output current stages <NUM>) for transmission to the testing module <NUM> over the ATB <NUM> via line <NUM>, depending on the configuration of the received control signaling.

In the depicted example, the testing module <NUM> includes a safety monitor <NUM> and a microcontroller unit (MCU) <NUM>. The safety monitor <NUM> has an input <NUM> conductively connected to the line <NUM> of the ATB <NUM>, a variable, or programmable, resistor <NUM> selectively coupleable to the input <NUM> via a switch <NUM>, and an analog-to-digital converter (ADC) <NUM> having an input coupled to the input <NUM>. The variable resistor <NUM> can be implemented as, for example, a variable resistor ladder (e.g., a circuit of resistors and corresponding switches that can be controlled to provide an equivalent resistance) or other digitally-controlled potentiometer. The MCU <NUM> is implemented as hardcoded logic, programmable logic, one or more processors executing software, or a combination thereof, and operates to control/configure the bias generator <NUM> and safety monitor <NUM> for testing and to analyze the test results for purposes of selectively asserting the flag <NUM>. Accordingly, the MCU <NUM> has an input coupled to the output of the ADC <NUM> and an output to selectively assert the flag <NUM>. The MCU <NUM> further has an output to provide control signaling <NUM> for the safety monitor <NUM> and the bias generator <NUM>, including the control signaling for controlling the switch networks <NUM> of the output current stages <NUM>, the control signaling for controlling the ATB interface <NUM>, the control signaling for programming the variable resistor <NUM>, and the control signaling for controlling the switch <NUM> of the safety monitor <NUM>, and the like. Note that the switch <NUM> can either be one or more switches separate from the variable resistor <NUM>, or the functionality of the switch <NUM> can be implemented through the variable resistor <NUM>, such as controlling the internal switches of the variable resistor <NUM> such that the variable resistor <NUM> presents either a low impedance (i.e., "closing" the switch <NUM>) or a high impedance (i.e., "opening" the switch <NUM>) to the input of the ADC <NUM>.

As a general operational overview, either a voltage to be tested (a test voltage) or a current to be tested (a test current) is received at the input <NUM> of the safety monitor from the bias generator <NUM> via the ATB interface <NUM> through corresponding configuration of the ATB IF <NUM> and the switch networks <NUM> via control signaling <NUM> provided by the MCU <NUM>. In the event that a voltage is being tested, the control signaling <NUM> is configured to open the switch <NUM>, such that the test voltage is received at the input of the ADC <NUM>, which in turn converts the test voltage to a corresponding digital value <NUM>, which is then output to the MCU <NUM>. In the event that a current is being tested, the control signaling <NUM> is configured to close the switch <NUM> so that the test current received via input <NUM> is routed through the variable resistor <NUM> and thereby generating a test voltage across the variable resistor <NUM> that is then converted by the ADC <NUM> to a corresponding digital value <NUM> that is then output to the MCU <NUM>. The MCU <NUM> then uses the received digital value <NUM> to determine whether the test voltage or test current represented by the received digital value <NUM> is within an acceptable operating range.

This determination can be made by, for example, comparing the digital value <NUM> (or a modified representation thereof) to an expected digital value for the corresponding voltage or current being tested, and if the digital value <NUM> is within a specified threshold of the expected digital value, the voltage or current being tested is considered to be within an acceptable operating range. Otherwise, if the digital value <NUM> differs from the expected digital value by more than the specified threshold, the voltage or current being tested is considered to be outside an acceptable operating range. Alternatively, an acceptable digital value range can be specified, or a look-up table (LUT) or other data structure can be programmed with digital values and their corresponding within/outside of acceptable range statuses specified. To this end, the MCU <NUM> can employ a memory, cache, or other data storage <NUM> to store such expected values, specified thresholds, ranges, and the like.

In the event that the MCU <NUM> determines that the digital value <NUM> indicates that the voltage or current being tested is within an acceptable operating range, the MCU <NUM> maintains the flag <NUM> in an unasserted state. Conversely, if the MCU <NUM> determines that the digital value <NUM> indicates that the voltage or current being tested is outside of the acceptable operating range, the MCU <NUM> asserts the flag <NUM> (that is, puts the flag <NUM> in an asserted state). The flag <NUM> also may be configured with additional information indicating the cause of the asserted flag <NUM>, such as a code identifying which voltage or current being tested resulted in the assertion of the flag <NUM>. As described in greater detail below, the FCCU <NUM> or other component of the IC device <NUM> then evaluates the asserted flag <NUM> in conjunction with other information in deciding whether to trigger an error <NUM> that may lead to cessation of operation of certain functions of the IC device <NUM> or may lead to some corrective action to address the faulty operation of the bias generator <NUM> for the next phase of operation.

<FIG> illustrates a method <NUM> of operation of the IC device <NUM> that includes a two-stage bias generator testing process in accordance with some embodiments. To facilitate understanding, the method <NUM> is described in an example context in which the IC device <NUM> implements an automotive radar function. As illustrated by timing diagram <NUM>, the IC device <NUM> repeats an operational cycle <NUM> that sequences through a startup/calibration stage <NUM>, a safety test stage <NUM>, an operational chirp stage <NUM>, and then a power down stage <NUM>. The next operational cycle <NUM> then starts with the startup/calibration stage <NUM>, and so forth.

However, prior to in-field operation, the IC device <NUM> first must be produced. As represented by block <NUM>, during the production process the bias currents of the bias generator <NUM> of the IC device <NUM> are tested using the testing module <NUM> and the output current generators <NUM> of the bias generator <NUM> are trimmed so as to bring the generated bias currents into an acceptable operating range. In one embodiment, this trimming process includes, for each current generator <NUM> to be tested, the MCU <NUM> programming the variable resistor <NUM> to a specified resistance, the MCU <NUM> programming the switch networks <NUM> and the ATB interface <NUM> via control signaling to send the bias current generated by each current generator <NUM> to the test input <NUM> of the safety monitor <NUM> via the ATB interface <NUM> and the ATB <NUM>, the MCU <NUM> configuring the switch <NUM> via control signaling to directing the received bias current through the variable resistor <NUM>, and then, based on the digital value <NUM> generated by the ADC <NUM> from on the voltage across the variable resistor <NUM>, determining whether to trim the corresponding current by trimming the current generator <NUM>, retesting the resulting trimmed bias current, and repeating the test/trim process until a suitable bias current is generated. This process then may be repeated in sequence for some or all of the current generators <NUM>, with the resulting trimming code representing the trimming to be employed for the current generators <NUM> stored in a one-time-programmable (OTP) memory or other non-volatile storage element associated with the bias generator <NUM>.

Post-production, the IC device <NUM> is integrated into a larger electronic system (e.g., an automotive electronics suite) that is then deployed in the field. When operational in-field, as mentioned above the IC device <NUM>, in the example implementation, performs a series of operational cycles <NUM> to provide radar sensing functionality. The operational cycle <NUM> initiates with the startup/calibration stage <NUM> (represented by block <NUM> of <FIG>), in which the IC device <NUM> performs a start-up and calibration sequence in preparation for performing radar sensing operations. As part of this sequence, the IC device <NUM> may read the trimming code stored during production and trim the current generators <NUM> of the bias generator <NUM> accordingly.

After the start-up/calibration stage <NUM> is complete, the operational cycle <NUM> initiates (at block <NUM>) the safety test stage <NUM> in which a safety function check of various designated mission-critical or safety-critical components of the IC device <NUM> is performed. As part of this safety function check, the bias generator <NUM> may be tested via a two-stage test process. The two stages of this test process include a common cause failure test followed by a grouping-based bias current test. Accordingly, at block <NUM> the IC device <NUM> performs the common cause failure test. This test involves testing for the more common causes of failure of the bias generator <NUM> using the shared ATB <NUM> and testing module <NUM>.

For example, in the example implementation of <FIG> it is assumed that failure of the bandgap module <NUM> and plurality of drive voltage generators <NUM> to generate one or more drive voltages <NUM> within an acceptable operating range is the most likely point or cause of failure for the bias generator <NUM>. Accordingly, the testing module <NUM> coordinates with the bias generator <NUM> to sequentially test some or all of the drive voltages <NUM> via the ATB <NUM>. In this approach, the MCU <NUM> configures the control signaling provided to the ATB interface <NUM> to sequentially output each of the drive voltages <NUM> in turn to the ATB <NUM>. For each drive voltage <NUM> thus output, the MCU <NUM> configures the switch <NUM> to an open, or non-conductive state, so that the drive voltage <NUM> is received at the test input <NUM> and then conducted to the input of the ADC <NUM>, whereupon the ADC <NUM> converts the input drive voltage <NUM> to a corresponding digital value <NUM>. The MCU <NUM> then uses this digital value <NUM> to determine whether the drive voltage <NUM> is within an acceptable operating range, such as by determining whether a difference between the digital value <NUM> and an expected digital value is within a specified threshold, or whether the digital value <NUM> falls within a specified range of digital values.

If the MCU <NUM> determines at block <NUM> that a tested drive voltage is outside of a corresponding acceptable operating range, then at block <NUM> the MCU <NUM> asserts the flag <NUM> at block <NUM>. The assertion of the flag <NUM> can include the provision of a code or other indicator of the cause of the flag <NUM>, including an identifier of the drive voltage that failed the test. Otherwise, if all tested drive voltages are found to be within their corresponding acceptable operating ranges, then the IC device <NUM> concludes the common cause failure test stage and can proceed to the grouping-based bias current test represented by block <NUM>.

Referring briefly to <FIG>, an implementation of the grouping-based bias current test of block <NUM>, as well as examples thereof, are illustrated in accordance with some embodiments. As shown by <FIG>, the grouping-based bias current test initiates at block <NUM> with the MCU <NUM> grouping of the plurality of bias currents <NUM> generated by the bias generator <NUM> for testing purposes into a plurality of subsets. Each subset includes one or more bias currents <NUM>, with at least some or all of the subsets including two or more bias currents <NUM>. In some embodiments, the subsets are mutually exclusive, whereas in other embodiments there may be overlap between subsets (that is, a bias current <NUM> may be grouped into more than one subset). The number of bias currents <NUM> per subset may be constant, while some subsets may have more bias currents than others. The grouping may be based on the output current stages <NUM>. For example, a given subset may contain only those bias currents <NUM> generated by the same output current stage <NUM>. Alternatively, the grouping may span multiple output current stages <NUM>, such that a subset may contain bias currents <NUM> from different output current stages. As described in greater detail below, the number of subsets, and thus the size of the subsets, may be selected based on any of a variety of considerations. Generally, the smaller the subsets, and thus the larger total number of subsets, the longer the sequential testing of subsets will take, but with improved testing resolution. Conversely, a smaller number of subsets, and thus a larger number of bias currents <NUM> per subset, will result in faster testing of the sequence of subsets, but at the expense of testing resolution.

Moreover, the grouping may be predetermined and fixed, or the grouping may be determined ad hoc. For example, for a given operational mode the bias generator <NUM> may be configured to provide a predetermined number of bias currents <NUM> and the IC device <NUM> has a predetermined amount of time to perform the safety function test, and thus the MCU <NUM> may be configured to implement a predetermined grouping of the bias currents <NUM> into corresponding subsets based on this information. In other instances, the number of bias currents <NUM> to be employed in a given mode may vary, or the amount of time allocated to conduct bias generator testing may vary, and the MCU <NUM> in such situations can instead vary the number/size of the subsets based on these varying considerations.

Whether employing a fixed or ad hoc grouping, the bias current testing process involves testing of the plurality of subsets in sequence. Accordingly, at block <NUM> the MCU <NUM> selects the next (or initial) subset of M bias currents <NUM> to be tested, wherein M is greater than or equal to one. Concurrently, at block <NUM> the MCU <NUM> programs the variable resistor <NUM> to have a specified resistance Ratb based on the number M of bias currents <NUM> included in the selected subset. It will be appreciated that the ADC <NUM> utilized to convert the voltage across the variable resistor <NUM> (Vres) to a corresponding digital value <NUM> may have a particular input voltage operating range, and thus the specified resistance Ratb is programmed based on the expected input test current (which is the combination of the M bias currents <NUM> in the subset selected for testing) and this input voltage operating range. For example, because the voltage Vres is a product of the test current (Itest) and the programmed resistance Ratb (that is, Vres = Itest * Ratb), the programmed resistance Ratb can be configured to have an inversely proportional relationship to the number M of bias currents <NUM> being tested as a group. In particular, in some embodiments, the resistance Ratb is set as Ratb ≈ Rmax/M, wherein Rmax represents either a maximum programmable resistance of the variable resistor <NUM> or some other specified maximum resistance value.

With a subset of bias currents <NUM> selected and the variable resistor <NUM> programmed accordingly, at block <NUM> the bias currents of the selected subset are combined as a single test current and the test current is routed from the bias generator <NUM> to the test input <NUM> of the testing module <NUM> via the ATB <NUM>. To illustrate using the example implementation of <FIG>, the MCU <NUM> configures the switch networks <NUM> of the output current stages <NUM> to route the bias currents <NUM> of the selected subset to the ATB interface <NUM> via the test outputs <NUM> of the corresponding output current stage(s) <NUM> by, for example, closing the switch <NUM> and opening the switch <NUM> for each current generator <NUM> that provides a bias current <NUM> included in the subset while opening the switch <NUM> and closing the switch <NUM> for each current generator that provides a bias current <NUM> not included in the subset. The MCU <NUM> also configures the ATB interface <NUM> to output each of the received bias currents <NUM> of the subset in parallel to the line <NUM> of the ATB <NUM>, thereby forming a single test current from the combined parallel output of the M separate bias currents <NUM> onto the line <NUM> from the ATB interface <NUM>. At block <NUM>, this single test current representing the combination, or sum, of the M individual bias currents <NUM> is conducted over the ATB <NUM> to the test input <NUM> of the safety monitor <NUM>, and the MCU <NUM> configures the switch <NUM> into a closed state, thereby causing the test current (Itest) to pass through the variable resistor <NUM>, causing a voltage Vtest to form across the variable resistor <NUM> having the programmed resistance Ratb, where Vtest = Ratb * Itest.

At block <NUM>, the resulting test voltage Vtest is converted to a digital value (digital value <NUM>) by the ADC <NUM>, and the digital value is provided to the MCU <NUM> At block <NUM>, the MCU <NUM> evaluates, using a software-based process or hardware-based comparator, the digital value to determine whether the subset of bias currents <NUM> is within a corresponding acceptable operating range. As noted, this determination may be made based on a comparison of the digital value to an expected digital value in view of a specified threshold, comparison of the digital value to a corresponding range, performing a lookup using the digital value into a LUT, and the like. It will be appreciated that this evaluation is based on an averaging, or cumulative, expected operational range for the entire subset as the test current Itest represents the combination of all bias currents <NUM> in the subset. To illustrate, assume that there are eight bias currents <NUM> (M=<NUM>) in the subset and each bias current <NUM> is expected to be approximately <NUM> microamperes (uA) at the operating temperature of the bias generator <NUM> under test, with an acceptable operating range of <NUM> to <NUM> uA for each of these bias currents <NUM>. As such, the total test current Itest when each bias current <NUM> is within an acceptable operational range would range between <NUM> uA and <NUM> uA, with a nominal expected value of <NUM> uA. This range then can be slightly narrowed to exclude the statistically unlikely scenarios in which all eight bias currents <NUM> are operating at <NUM> uA or all eight bias currents are operating at <NUM> uA, arriving at a narrower range of, for example, <NUM>-<NUM> uA, or <NUM> +/- <NUM> uA. Thus, if a digital value representing a value within this range, or within a +/- <NUM> uA threshold of <NUM> uA is received, the MCU <NUM> determines that each of the bias currents <NUM> within the subset are within an acceptable operating range. However, if a digital value representing a value outside this range, or outside of a +/- <NUM> uA threshold of <NUM> uA, is received, the MCU <NUM> determines that at least one of the bias currents <NUM> within the subset is outside of an acceptable operating range. Note that although this example is described in terms of current, it will be appreciated that the testing is performed based on a digital representation of the voltage measured by the ADC <NUM> as a result of the test current and the resistance Ratb (that is, Vtest = Itest * Ratb), and thus the actual test values, ranges, and thresholds in implementation would be understood to be the voltage-equivalent counterparts based on the Ratb employed.

Thus, if at block <NUM> the digital value indicates that the test current Itest (=Vtest/Ratb) representing the combination of the M bias currents <NUM> of the subset is outside of an acceptable operating range, then the method <NUM> transitions from the testing process of block <NUM> to asserting a flag <NUM> at block <NUM> (<FIG>). As similarly explained above, the assertion of this flag <NUM> can include an indicator of the cause or trigger of the flag <NUM>, such as an identifier of the subset of bias currents <NUM> that failed the grouped bias current test. However, if at block <NUM> the digital value indicates that the test current Itest is within an acceptable operating range, then the bias currents <NUM> of the subset are deemed to be in compliance and no flag <NUM> is asserted. At block <NUM> the MCU <NUM> determines whether there are any subsets remaining that have not yet been tested. If so, the method <NUM> returns to blocks <NUM> and <NUM> for another iteration of the grouping-based bias current test represented by blocks <NUM> to <NUM> for the next subset in the sequence of subsets. Otherwise, if the MCU <NUM> determines at block <NUM> that all subsets have been tested (and no flags have been triggered during the testing of a subset), then the test process of block <NUM> concludes.

<FIG> illustrate two example scenarios for the grouping-based bias current testing process of block <NUM> for corresponding subsets. In the example of <FIG>, a subset <NUM> of three bias currents (M = <NUM>) from the output current stage <NUM>-<NUM> is selected for testing. Accordingly, the variable resistor <NUM> is programmed to a value Rtest1 = Rmax/<NUM> and the output current stage <NUM>-<NUM> is configured to output the three selected bias currents to the ATB interface <NUM> in parallel. The ATB <NUM> outputs these three bias currents in combination as a test current <NUM> (Itest1) to the ATB <NUM>. The test current <NUM> thus is conducted to the safety monitor <NUM> via the ATB <NUM>, and from there is conducted through the variable resistor <NUM>, resulting in the generation of a test voltage <NUM> (Vtest1 = Itest1*Rtest1) at the input to the ADC <NUM>. The ADC <NUM> converts the test voltage <NUM> to a corresponding digital value <NUM>, which is then evaluated by the MCU <NUM> to determine whether the test current <NUM> is within an acceptable operating range, and thus whether the three bias currents that constitute the test current <NUM> are presumably individually within their own acceptable operating ranges.

In the example of <FIG>, a subset <NUM> of four bias currents (M = <NUM>) from both the output current stage <NUM>-<NUM> and the output current stage <NUM>-<NUM> is selected for testing. Accordingly, the variable resistor <NUM> is programmed to a value Rtest2 = Rmax/<NUM> and the output current stages <NUM>-<NUM> and <NUM>-<NUM> are configured to output the four selected bias currents to the ATB interface <NUM> in parallel. The ATB <NUM> outputs these four bias currents in combination as a test current <NUM> (Itest2) to the ATB <NUM>. The test current <NUM> is conducted to the safety monitor <NUM> via the ATB <NUM>, and from there is conducted through the variable resistor <NUM>, resulting in generation of a test voltage <NUM> (Vtest2 = Itest2*Rtest2) at the input to the ADC <NUM>. The ADC <NUM> converts the test voltage <NUM> to a corresponding digital value <NUM>, which is then evaluated by the MCU <NUM> to determine whether the test current <NUM> is within an acceptable operating range, and thus whether the four bias currents that constitute the test current <NUM> are presumably individually within their own acceptable operating ranges.

Returning to <FIG>, as explained the grouping-based bias current test process of block <NUM> results in either a failed test status due to the test current formed from a subset of bias currents falling outside of an acceptable range or a passed test status in which the test current for every tested subset is within a corresponding acceptable range. In the event of the failed test status, at block <NUM> the MCU <NUM> asserts a flag <NUM> to signal the failed test status. Thus, as described above, a flag <NUM> may be asserted during the first stage of testing for the common cause failure testing of block <NUM> or, if no flag is asserted during the first state, during the second stage of testing using grouped bias current testing. In either case, in response to the assertion of a flag <NUM> at block <NUM>, the FCCU <NUM> (<FIG>) evaluates the asserted flag <NUM> and associated circumstances at block <NUM> for selectively triggering an error <NUM> that could in turn trigger deactivation of the bias generator <NUM> and some or all of the circuitry of the IC device <NUM> reliant on the bias currents <NUM> generated therefrom. Such circumstances may include, for example, the priority of the circuitry impacted by the bias generator <NUM> operating outside an acceptable margin of error, the cause of the flag <NUM> (e.g., a failed drive voltage vs. a failed bias current), the degree to which the failed voltage/current being tested deviated from the expected value, and the like.

However, in the event that a flag <NUM> is not asserted at both stages of the two-stage bias generator test performed as part of the safety test stage <NUM>, any other safety tests that have not yet been performed can be performed, and then the operational cycle <NUM> enters the operational chirp stage <NUM> of the operational cycle <NUM>. As represented by block <NUM>, this operational chirp stage <NUM> can include the operation, or performance, of one or more radar functions using the circuit blocks <NUM> that utilize the bias currents <NUM> from the now-verified bias generator <NUM>, such as the radio frequency (RF) transmission of one or more radar chirps and receipt and processing of any reflected RF signals for object detection. Following the operational chirp stage <NUM>, the operational cycle <NUM> enters the power down stage <NUM> (represented by block <NUM>), during which the IC device <NUM> shuts down and gates off certain circuitry so as to conserve power and reduce wear. In this example, the end of the power down stage <NUM> marks the end of the current operational cycle <NUM>, and the next operational cycle <NUM> then starts with another iteration of the startup/calibration stage <NUM>, and another iteration of the process of blocks <NUM>-<NUM> begins.

Note that although <FIG> illustrates a particular arrangement of the safety test stage <NUM> relative to the other stages of the operational cycle <NUM>, in other embodiments some of these stages may be implemented in a different order. For example, rather than implement the safety test stage <NUM>, and thus the two-stage bias generator test process, prior to the operational chirp stage <NUM>, in other embodiments, the operational chirp stage <NUM> is performed first, and then the safety test stage <NUM> is performed following the operational chirp stage <NUM>. In this order, any date or results from the operational chirp stage <NUM> are temporarily buffer and remain unused for downstream processing until the safety test stage <NUM> is completed and confirms that the bias generator <NUM> and other tested components of the IC device <NUM> are operating within acceptable ranges and therefore the results and data generated by these tested components can be trusted.

The operational cycle <NUM> of <FIG> illustrates an example of the utility of the grouping-based bias generator testing process. Ideally, either the operational cycle <NUM> is kept as short as practicable so as to permit more iterations of the operational cycle <NUM> per unit time or the duration of the stages other than the operational chirp stage <NUM> are kept as short as practicable to permit the operational chirp stage <NUM> to be longer for a given duration of the operational cycle <NUM>. Thus, a reduction in the time needed to perform the safety test stage <NUM> can increase the overall effectiveness or efficiency of the IC device <NUM> in performing its associated radar functions. The grouping of the bias currents into subsets for testing together as a single test current requires fewer current tests compared to conventional individual bias current test processes, and thus facilitates reduction of the overall time needed to perform the safety test stage.

To illustrate, assume an IC device with two different PTAT slopes and <NUM> bias currents, each of <NUM> uA. If a test resistor of Rmax = <NUM> kilohms (kΩ) is used, each such bias current would result in an expected test voltage of <NUM> volt (V) (<NUM> kΩ* <NUM> uA). A <NUM>% error in a given current would be +/- <NUM> mV, which is detectable by most built-in self-test (BIST)-type ADCs. Further assume that the time to test each of these bias currents is <NUM> microseconds (us), including program, settle, and measure times. A conventional bias current test process in which each bias current is tested individually and in sequence would thus require approximately <NUM> to complete (<NUM> to test the bias currents individually and <NUM> to test the drive voltages). Now assume a grouping-based test as described above, where the <NUM> bias currents are grouped in subsets of <NUM> bias currents each (M=<NUM>), resulting in <NUM> subsets to be tested, each subset having an expected combined test current of <NUM> uA (<NUM> uA * <NUM> bias currents). Assuming the same Rmax as the above conventional scenario, the resulting Rtest is <NUM> kΩ, and thus resulting in an expected test voltage Vtest of 1V (<NUM> kΩ * <NUM> uA test current). A <NUM>% deviation in one of the <NUM> bias currents thus is reflected in a <NUM> mV deviation in the test voltage Vtest, which is a value that is still detectable by many common BIST ADC implementations. However, using the same time to test a subset of <NUM> bias currents as a single test current of <NUM>, testing the <NUM> subsets would take only <NUM> (<NUM> to test the <NUM> subsets and <NUM> to test the two drive voltages). This represents a nearly <NUM>-fold reduction in the time to test the bias generator, and frees up <NUM> to either shorten the overall operational cycle <NUM> or expand the operational chirp stage <NUM> if the duration of the operational cycle is fixed. Alternatively, for a given safety test duration, additional testing can be performed, or a combination of increased testing and increased operational time can be achieved.

In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing software. The software comprises one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium can include, for example, a magnetic or optical disk storage device, solid-state storage devices such as Flash memory, a cache, random access memory (RAM) or other non-volatile memory device or devices, and the like. The executable instructions stored on the non-transitory computer-readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executable by one or more processors.

Claim 1:
A device (<NUM>) comprising:
a bias generator (<NUM>) configured to generate a plurality of bias currents; and
a testing module (<NUM>) configured to test the bias generator, characterized by successively testing each subset of bias currents of a plurality of subsets of bias currents grouped from the plurality of bias currents as a corresponding single test current, wherein at least one of said subsets of bias currents has two or more bias currents.