Patent Description:
Solid state storage devices (for example, solid state drives) may be comprised of one or more packages of non-volatile memory dies, where each die is comprised of storage cells, where storage cells are organized into pages and pages are organized into blocks. Each storage cell can store one or more bits of information. A multi-level cell non-volatile memory cell for example, MLC NAND representing two bits of information is programmed with four threshold voltage levels, E, P1, P2, and P3.

A retention error occurs when the stored voltage level for a cell experiences leakage and transitions or migrates to a lower threshold level, such as from P3 to P2, P2 to P1, or P1 to E. Retention errors may also occur as a result of operations that introduce a voltage shift (higher or lower), such as a read or write disturbance. Error correction code techniques identify the location of the errors by calculating a syndrome and using the syndrome along with parity information to correct errors in bits determined to have errors.

US patent application <CIT> relates to a method for storing information in a storage device comprising one or more multi-level memory cells. In said patent application, guard bands represent a difference in voltage levels that protect the data bit from drift caused by leakage or disturbances.

There is a need in the art for improved techniques for determining the location of the data experiencing the errors to calculate the syndrome and use with the parity information to correct retention errors.

Embodiments are described by way of example, with reference to the accompanying drawings, which are not drawn to scale, in which like reference numerals refer to similar elements.

Described embodiments provide techniques to group storage cells in a storage cell group of multiple storage cells to provide for invalid states for the states that may be programmed for the storage cells in the storage cell group using threshold voltage levels. By grouping storage cells into storage cell groups to store bits from received pages, there may be a number valid states used to represent the received bits that is fewer than all possible states because more storage cells, as grouped in a storage cell group, are being used to store the received bits. The invalid states are defined such that the threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels. In this way, storage cells of the storage cell group programmed in any valid state experiencing retention errors, such as leakage of one threshold voltage level, would transition to an invalid state. When reading a storage cell group having an invalid state, those read bits can be marked as invalid to provide to the error correction unit accurate information on the location of the invalid bits for use in calculating error correction information.

By only using a portion of the storage cell states and marking the rest as invalid, valid and invalid states are interleaved, so that the 'Hamming Distance', which equals to the number of migrations from one valid state to another valid state, becomes larger. This interleaved assignment of valid states allows immediate detection of errors upon decoding bits and determining they represent an invalid state. Such detection of the location of the bits and cells experiencing the errors is known as "erasure" According to coding theory, given a same Error Correction Code (ECC) code, the number of erasures that can be corrected is twice as many as the number of errors. The in-situ error detecting capability of the described embodiments improves the effectiveness of error correcting without adding ECC bits.

The described in-situ error detection programming methodology may be provided by compressing the bits to be stored so as to allow for states that may be marked as invalid to use to detect leakage.

In the following description, numerous specific details such as logic implementations, opcodes, means to specify operands, resource partitioning/sharing/duplication implementations, types and interrelationships of system components, and logic partitioning/integration choices are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures, gate level circuits and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.

Certain embodiments relate to storage device electronic assemblies. Embodiments include both devices and methods for forming electronic assemblies.

<FIG> illustrates an embodiment of a non-volatile memory storage device <NUM> having a controller channel <NUM>, a host interface <NUM> to transfer blocks of data between a connected host system, and a plurality of groups of storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n implementing storage cells that may be organized into pages of storage cells, where the pages are organized into blocks. The non-volatile memory storage device <NUM> may function as both a memory device and/or a storage device in a computing system, and may be used to perform the role of volatile memory devices and disk drives in a computing system. In an embodiment, the non-volatile memory storage device <NUM> may comprise a solid state drive (SSD) of NAND storage dies <NUM><NUM>, <NUM><NUM>. The controller channel <NUM> includes a central processing unit (CPU) <NUM> implementing certain control functions, such as a logical-to-physical mapping <NUM> provides a mapping of logical addresses to which I/O requests are directed and physical addresses in the storage dies <NUM><NUM>, <NUM><NUM>.

The controller channel <NUM> includes a plurality of storage die controllers <NUM><NUM>, <NUM><NUM>. <NUM>n that manage read and write requests to blocks of data in pages of storage cells to groups of the storage dies <NUM><NUM>, <NUM><NUM>. A transformation layer <NUM><NUM>, <NUM><NUM>. <NUM>n for each of the storage die controllers <NUM><NUM>, <NUM><NUM>. <NUM>n transforms a received number of bits (e.g., k bits) in pages of data from the host to write to storage cell groups of multiple storage cells (each storing m bits, where m is >= k) in the storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n and to transform a read m number of bits in a block to the fewer number of k bits of the block of data to return in pages to the host. A host operating system may code pages of data for the memory controller, where multiple of the pages provide the data for each of the multi-level storage cells, such as if each storage cell stores n bits, the host operating system would provide n pages to provide each of the n bits to code in a storage cell.

The transformation layer <NUM><NUM>, <NUM><NUM>. <NUM>n uses the state mappings <NUM><NUM>, <NUM><NUM>. <NUM>n to determine the translation functions to use to transform the fewer k bits to m bits and vice versa. In certain embodiments, the mapping operations for k bits in the received pages to the m bits stored in a storage cell group, and vice versa, are performed by the transformation layer <NUM>i. In alternative embodiments, the mapping operations may be performed by the I/O logic <NUM>, where the transformation layer <NUM>i is implemented in the I/O logic <NUM>.

For instance, if each multi-level cell comprises n bits, then storage device <NUM> provides <NUM>n different threshold voltage levels to program the <NUM>n different states for a storage cell. Storage cells are grouped into groups of p storage cells each, so each storage cell group has <NUM>np states of information, and allow storage of m bits of information for a block of data, where m = Log<NUM>(<NUM>np) bits of information. The controller channel <NUM> and transformation layers <NUM><NUM>, <NUM><NUM>. <NUM>n may be programmed to only use j threshold voltage levels, less than the <NUM>n available threshold voltage levels. A storage cell group of p storage cells programmed to only use j threshold voltage levels would be capable of representing jp states with k bits of information, where k < m and k is a largest integer less than or equal to Log<NUM>(jp).

The storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n may comprise electrically erasable and non-volatile memory cells. For instance, the storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n may comprise NAND dies of memory cells, also known as NAND chips or packages. In one embodiment, the NAND dies may comprise multilevel cell (MLC) NAND flash memories where each cell records two bit values, a lower bit value and an upper bit value. Alternatively, the NAND dies may comprise single level cell (SLC), multi-level cell (MLC), triple level cell (TLC) NAND memories, etc. The NAND dies, TLC, MLC, SLC, etc., may be organized in a three dimensional (3D) or two dimensional (2D) physical structure. The storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n may further comprise ferroelectric random-access memory (FeTRAM), nanowire-based non-volatile memory, three-dimensional (3D) crosspoint memory such as phase change memory (PCM), memory that incorporates memristor technology, Magnetoresistive random-access memory (MRAM), Spin Transfer Torque (STT)-MRAM, a single level cell (SLC) Flash memory and other electrically erasable programmable read only memory (EEPROM) type devices.

The non-volatile memory storage device <NUM> may include a data compression unit <NUM> to compress received data from the host interface <NUM>, a data encryption unit <NUM> to encrypt the compressed data, and an error correction unit <NUM> to perform error correction operations, and scrambler units <NUM><NUM>, <NUM><NUM>. <NUM>n to scramble the encrypted and compressed data before the controllers <NUM><NUM>, <NUM><NUM>. <NUM>n write the data to the storage dies <NUM><NUM>, <NUM><NUM>. The data provided to the controller <NUM><NUM>, <NUM><NUM>. <NUM>n may be compressed and include fewer bits of data than stored in the storage cells of the storage dies <NUM><NUM>, <NUM><NUM>. In alternative embodiments, there may be only the data compression unit <NUM> and error correction unit <NUM>, and not the encryption <NUM> and scrambler <NUM> units. In still further embodiments, the data compression unit <NUM>, encryption unit <NUM>, and/or scrambler units <NUM><NUM>, <NUM><NUM>. <NUM>n may be implemented in an external host system, such that fewer bits are provided to the host interface <NUM> to store than the number of bits stored in the storage cell.

The data from the host interface <NUM>, that is subject to the compression <NUM>, encryption <NUM>, and error correction <NUM> is stored in a transfer buffer <NUM> from where it is transferred to the controllers <NUM><NUM>, <NUM><NUM>. <NUM>n and scrambled by the scrambler units116<NUM>, <NUM><NUM>. <NUM>n to scramble before being written to the storage dies <NUM><NUM>, <NUM><NUM>.

The processing components in the non-volatile memory storage device <NUM>, including the controllers <NUM><NUM>, <NUM><NUM>. <NUM>n , compression unit <NUM>, encryption unit <NUM>, error correction unit <NUM>, and scrambler units116<NUM>, <NUM><NUM>. <NUM>n may be implemented as firmware or in one or more application specific integrated circuits (ASIC) within the non-volatile memory storage device <NUM>. Alternatively, these components may be implemented in a software program executed by a processor of the non-volatile memory storage device <NUM>.

The host interface <NUM> connects the memory device <NUM> to a host system (not shown). The memory device <NUM> may be installed or embedded within a host system, such as shown and described with respect to element <NUM> or <NUM> in <FIG>, or the memory device <NUM> may be external to the host system. The host interface <NUM> may comprise a bus interface, such as a Peripheral Component Interconnect Express (PCIe) interface, Serial AT Attachment (SATA), Non-Volatile Memory Express (NVMe), etc..

In certain embodiments, the storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n may comprise n-bit multi-level cells, where each cell can be programmed into <NUM>n states represented by <NUM>n different threshold voltage levels. For a multi-level cell (MLC) NAND flash memory storing <NUM> bits per cell, there may be four voltage thresholds, E, P1, P2, and P3 to represent the four states that may be programmed into cells. A tri-level cell (TLC) flash memory cell may be programmed with eight threshold voltage levels. In certain embodiments, the storage die controller <NUM>i may organize storage cells for writing into storage cell groups comprising p storage cells. According to the invention, for an n-bit cell organized into a cell group of p, each cell group can store m bits of information, where m = log2(<NUM>np), and each storage cell group may represent <NUM>np different states, which can be programmed with <NUM>np different voltage level combinations. The pages of cells may be organized into a block of pages, where an erase operation to restore the state of the cells to the E or erase state is performed on a block basis.

The transformation layers <NUM><NUM>, <NUM><NUM>. <NUM>n may receive a block of k bits of information to write, which is less than the m bits of information for a block in a storage cell group. The fewer k bits may result from compression or the host operating system being programmed to provide a block of data comprising k bits. To provide improved information on the location of an error to the error correction unit <NUM>, the transformation layers <NUM><NUM>, <NUM><NUM>. <NUM>n may map the received k bits to a subset of the <NUM>np states that may be programmed in a storage cell group comprising p storage cells. In this way the possible <NUM>np states are divided into valid and invalid. If bits programmed in a storage cell group experience retention errors and leakage and at least one of the storage cells in the storage cell group transitions to a lower threshold level, then that storage cell group may transition to an invalid state. The transformation layers <NUM><NUM>, <NUM><NUM>. <NUM>n can provide information on the bits mapping to an invalid state to the error correction unit <NUM> to use to correct the errors for the read invalid state.

<FIG> shows additional components that may be included in each storage die controller <NUM>i managing writes to a group of storage dies <NUM>i, including Input/Output (I/O) logic <NUM> processes read/write commands from an attached host (not shown) in a command queue (not shown), from which the commands are accessed and executed. The I/O logic <NUM> maintains a page pool <NUM> of a plurality of available pages <NUM> for the storage dies <NUM>i and device page information <NUM> having information on device pages configured to use pages <NUM> from the page pool <NUM>. Each device page having n bits per storage cell may be assigned n pages <NUM> from the page pool <NUM> to store the blocks of data. An MLC NAND having two bits per storage cell, has an upper and lower pages, a triple level cell (TLC), has three bits per storage cell and three pages for the three bits.

<FIG> illustrates an instance of device page information <NUM>i for a page of data storing the data for the n-bit storage cells, including a device page identifier <NUM>, an address range <NUM> of addresses stored in the page <NUM>i, a lower page identifier (ID) <NUM> identifying one of the pages <NUM> allocated as a lower page to store one bit of the storage cell; an upper page ID <NUM> to store one bit of the storage cell, where there may be n pages allocated to a device page for an n-bit storage cell; and a state mapping <NUM> indicating the state mapping providing the bit translation functions used to map the read data to the storage cell groups implemented in the pages <NUM>, <NUM>.

<FIG> illustrates upper and lower pages for an MLC NAND having two bits per storage cell. For a TLC, there would be three pages for the three bits per storage cell, and for a NAND having n bits per storage cell, there may be n pages. The pages map to address ranges in the storage dies <NUM><NUM>, <NUM><NUM>.

<FIG> illustrates an embodiment of a state mapping <NUM>i comprising one of the state mappings <NUM><NUM>, <NUM><NUM>. 400n, as including a state mapping ID <NUM> identifying the mapping; a number of storage cells in a storage cell group <NUM> (p); a number of bits <NUM> of a received block to write to the storage cells in the storage cell group, or k, which may be less than the total number of m bits in a storage cell group; a number of threshold voltages <NUM> used for each cell of a storage cell group, where the number of threshold voltages <NUM> may comprise a subset of the total threshold voltages available for use, which may comprise a subset of the lowest threshold voltages for a set of threshold voltages; a number of total states <NUM> that may be programmed in a storage cell group, which comprises <NUM>np; and bit translation functions <NUM>, which may include cell mapping, to map the k received bits <NUM>, or k, to valid states coded using the number of threshold voltages <NUM> per storage cell. The mapping may provide <NUM>k valid states and <NUM>np - <NUM>k invalid states. If less than all the threshold voltage levels are used, then the number of valid states comprises <NUM>jp, where j is the number of threshold voltage levels used, and j is less than <NUM>n, where <NUM>n is the number of threshold voltage levels needed to implement an n level cell, where n is the number of bits that may be programmed in each cell.

For instance for a storage cell group comprising a storage cell pair, i.e., p=<NUM>, the number of possible states or bits of information that may be stored in a storage cell pair group is sixteen states or four bits of information that can be programmed with <NUM> threshold voltage level combinations. If the number of received bits is k, such as <NUM>, then the number of valid states is <NUM>k, e.g., <NUM><NUM>=<NUM>, even though there are sixteen total possible states for a storage cell group of <NUM> storage cells and four threshold voltage levels E, P1, P2, P3, allowing for half valid and half invalid states.

<FIG> illustrates an embodiment where all possible states <NUM> in a storage cell group may comprise valid states ("VS"), for instances where the total number of states of the read bits k is four which is equal to the number of possible states that may be programmed with the four available threshold levels (E, P1, P2, P3), which is sixteen. If one of the storage cells, e.g., cell <NUM>, initially programmed at state <NUM>, or P1 and P3, experiences retention errors and leakage, which causes the state cell <NUM> to fall one threshold voltage level to transition <NUM> to state <NUM>, then the location error cannot be determined by reading cell <NUM> and cell <NUM> of a storage cell group, because the state <NUM> is a valid state, although not the state initially programmed state for cells<NUM>, <NUM>. The error correction unit <NUM> in such case will use additional parity bits to detect and correct the error, including the location of the false storage cell and correct value at that location by performing normal error correction.

<FIG> illustrate embodiments where there are valid and invalid states of the possible states. In the embodiments of <FIG>, a storage cell group of cells <NUM>, <NUM> programmed in a valid state experiencing a leakage of one threshold voltage level in either of its storage cells <NUM>, <NUM> would transition to an invalid state. In this way, each invalid state has a limited number of possibilities of the initial programmed state. This greatly eliminates the search space for error. With described embodiments, there is at least one invalid state between any two valid states in the horizontal and vertical directions such if there is cell leakage in any cell of the storage cell group by one threshold voltage level, the resulting leaked state is an invalid state.

<FIG> illustrates an embodiment of possible states <NUM> in which half the states are valid states ("VS"), and the other half are invalid states ("IS"). If one of the storage cells in the storage cell group of cell <NUM>, <NUM>, initially programmed at state <NUM>, or P1, P3, experiences leakage, then the state of cell <NUM> would fall one threshold voltage level to transition <NUM> to state <NUM>, which is an invalid state.

Upon reading a storage cell group of cells <NUM> and cell <NUM> having an invalid state <NUM> (P1, P2), then those bits can be marked as erroneous, and the error correction unit <NUM> can use that information with parity information to correct the data.

<FIG> illustrates an embodiment possible states <NUM> in which a quarter of the states are valid states ("VS"), and the remainder of invalid states ("IS"). If one of the storage cells, e.g., cell <NUM>, initially programmed at state <NUM>, or P1, P2, experiences leakage, then the state of cell <NUM> would to fall one threshold voltage level to transition <NUM> to invalid state <NUM> (P1, P1). <FIG> would allow errors to be determined with read data if a storage cell group experienced a loss of two threshold voltage levels because there are at least two threshold voltage levels between states in the horizontal direction.

The embodiments of <FIG> is most useful when the cells are most likely to experience a leakage of only one threshold voltage level. The embodiment of <FIG> may be useful when leakage can be one or two threshold voltage levels, so that an invalid state can result from cell leakage of two threshold voltage levels away. For instance, invalid state <NUM> (P1, P1) can be reached from a two threshold voltage level leakage from state <NUM> or from two single threshold voltage level leakages from state <NUM> (P2, E).

In certain embodiments, the multiple pages provide the bits to code in a storage cell group. In an MLC NAND, two pages provide the bits for each storage cell, where one page has the first most significant bits (MSB) and the other page has the least significant bits (LSBs) to another page, referred to as upper and lower pages. For a TLC NAND, the three bits for each storage cell are written to three different pages. In MLC NAND, data can be erased at a block at a time to set the storage cells to the E threshold voltage level. An entire page (usually 1kB, 2KB or 4kB) is written together.

<FIG> illustrates an embodiment of a cell-to-bit mapping <NUM> to map k = <NUM> bits of information supplied by multiple of the pages (upper and lower or first and second pages) to a storage cell pair (i,j), where there are two storage cells in a storage cell group (p=<NUM>), and there are two bits stored in a cell, i.e., a MLC storage cell. The mapping <NUM> may be implemented in the bit translation functions <NUM> that would determine from the mapping <NUM> the threshold voltages to use to program the received k bits. The mapping <NUM> provides an embodiment where half the states are valid and half invalid, where valid states show the possible values of the three bits and invalid states are shown blank. The first column 602a shows the different programming states E, P1, P2, and P3 for celli and the first row 602b shows the different programming states E, P1, and P2 for cellj of the storage cell pair. The second column 604a and second row 604b show the normal <NUM> bit coding for each storage cell, wherein the first bit is for a lower page and a second bit is for the upper page. The cells of the table show sixteen total states <NUM> and half valid states. Further, <FIG> as in <FIG> shows that leakage of one threshold voltage level from one valid state for any one cell i, j would result in an invalid state. The columns 602a and rows 602b show the threshold voltages to use for the first (celli) and second (cellj) cells of the pair, respectively.

<FIG> shows a truth table <NUM> based on the mapping <NUM> that shows the different threshold voltage levels for the first cell in the voltage column 622a and for the second cell in the voltage column 622b, the full four bits in the bit column <NUM> coded by the threshold voltages 622a, 622b and the MSB and LSBs for the three bit values represented by the threshold voltages in the voltage columns 622a, 622b in the bit columns 626a, 626b, respectively. The truth table <NUM> only provides mappings for all possible <NUM> states of three bits 626a, 626b into sixteen possible states for the four bits <NUM> in a storage cell pair i, j. The states not shown in the truth table <NUM> for the four bits <NUM> of the storage cell pair comprise invalid states.

From the truth table <NUM>, upon selecting three bits to write from pages in the transfer buffer <NUM>, the MSB and LSBs of the received three bits are coded using the three threshold voltage levels s as shown in the columns 622a, 622b for the received three bits in the columns 626a, 626b. The truth table <NUM> is used to determine how the read and decoded four bit state from a storage cell pair, represented in the bits in column <NUM> maps to the received three bits 626a, 626b that were written to the storage cell pair.

The four bits read from the pair of storage cells may be translated to the received three bits based on the truth table <NUM> as follows, where M<NUM> is the MSB bit, B<NUM>, B<NUM>, B<NUM>, B<NUM> correspond to the four bits read from a storage cell pair, L<NUM> is a first least significant bit of the three bits, L<NUM> is a second least significant bit: <MAT> <MAT> <MAT>.

Further, the bit B<NUM> can be presumed to be a parity bit and the read four bits B<NUM>, B<NUM>, B<NUM>, B<NUM> may be XOR'd to determine whether they are an invalid or valid state, such that states with even parity, i.e., have an even number of <NUM>, are valid.

In further embodiments, logical expressions or functions other than XOR may be applied to the decoded bits to determine whether the result of the function indicates that the read four bits comprise a valid or invalid sate.

Thus, the bit translation function <NUM> in a state mapping <NUM>i where the number of bits <NUM> in a block is three, the number of storage cells in a storage cell group <NUM> is two, the number of threshold voltages <NUM> is three, and the total number of states <NUM> is <NUM> implement the mappings <NUM> and truth table <NUM> of <FIG> to map the received k bits <NUM> to a valid state represented by m bits stored in the storage cell group and then map the read m bits from a storage cell group to the received k bits to return to a host if the read four bits are a valid state, e.g., have odd parity. For instance, to map the read block of four bits from a storage cell pair of MLC NAND cells (n=<NUM>) to the initially received <NUM> bits, the above three translation functions (<NUM>), (<NUM>), and (<NUM>) can be used to translate the read four bits from the storage cell pair to the received three bits to return to the requesting host. <FIG> illustrates an embodiment of a cell-to-bit mapping <NUM> to map k = <NUM> bits of information selected from two pages to a storage cell pair, where there are two storage cells in a storage cell group, and there are two bits stored in a cell (n=2_, i.e., a MLC storage cell. The mapping <NUM> provides an embodiment where one quarter of the states are valid and three quarters invalid, where valid states show the possible values of the two bits and invalid states are shown blank. The first column 702a shows the different programming states E and P1 for celli and the first row 702b shows the different programming states E and P1 for cellj of the storage cell pair. The second column 704a and second row 704b show the normal <NUM> bit coding for each storage cell, wherein the first bit is for a lower page and a second bit is for the upper page. The cells of the table show the four possible states of the received two bits to store, and rows and columns show the threshold voltages to use for the first (cell<NUM>) and second (cell<NUM>) cells of the pair.

In <FIG>, the valid states are one-quarter of the total number of states and configured such that the average voltage distance between any two valid states comprises at least two threshold voltage levels.

<FIG> shows a truth table <NUM> based on the mapping <NUM> that shows the different threshold voltages for the first cell in the voltage column 722a and for the second cell in the voltage column 722b, the full four bits in the bit column <NUM> coded by the threshold voltages 722a, 722b and the MSB and LSB for the two bit values represented by the threshold voltages in the voltage columns 722a, 722b in the bit columns 726a, 726b, respectively.

From the truth table <NUM>, upon receiving the two bits to store, the MSB and LSB of the received two bits are coded using the threshold voltage levels as shown in the columns 722a, 722b for the received two bits in the columns 726a, 726b. The truth table <NUM> is used to determine how the read and decoded four bit state from a storage cell pair, represented in the four bits in column <NUM> maps to the received two bits 726a, 726b that were written to the storage cell pair.

The four bits read for a block from the pair of storage cells may be translated to the received block of two bits based on the truth table <NUM> as follows, where M<NUM> is the MSB bit, B<NUM>, B<NUM>, B<NUM>, B<NUM> correspond to the four bits read from a storage cell pair, L<NUM> is the least significant bit of the two bits: <MAT> <MAT>.

The invalid state of the decoded four bits may be determined by comparing the read voltage states (B<NUM>, B<NUM>, B<NUM>, B<NUM> ) to the four valid states e.g. (V==<NUM>,<NUM>) or (V==<NUM>,<NUM>) or (V==<NUM>,<NUM>) or (V==<NUM>,<NUM>). This comparison may be performed using different logical operators, such as AND, OR, XOR, etc..

Thus, the bit translation function <NUM> in a state mapping <NUM>i where the number of bits <NUM> is two, the number of storage cells in a storage cell group <NUM> is two, the number of threshold voltages <NUM> is four, and the number of states <NUM> is sixteen, implement the mappings <NUM> and truth table <NUM> of <FIG> to map the received two bits <NUM> to the four bits stored in the storage cell group and then map the read four bits from a storage cell group to the received two bits to return to a host. For instance, to map the read four bits from a storage cell pair of MLC NAND cells (n=<NUM>) to the initially received two bits, the above translation functions (<NUM>) and (<NUM>) can be used to translate the read four bits from the storage cell pair to the received two bits to return to the requesting host.

<FIG> illustrates an embodiment of operations performed by the Input/Output (I/O) logic <NUM> and transformation layer <NUM>i to process pages in the transfer buffer <NUM> providing blocks of k bits of information to write to storage cell groups, where each storage cell group stores m bits of information, where m > k. The provided pages of k bits of information may comprise encrypted and compressed data of an original m bits, compressed by the compression unit <NUM> and then encrypted by the encryption unit <NUM>. Further, certain of the provided m bits in pages may comprise parity bits generated by the error correction unit <NUM> for error correction operations. Upon processing (at block <NUM>) multiple pages in a device page <NUM>i providing the k bits to write to storage ell groups, the I/O logic <NUM> or transformation layer <NUM>i determines (at block <NUM>) the state mapping <NUM>i to use. The determined state mapping <NUM>i may be based on the mapping 400i having a number of bits <NUM> equal to the number of bits k for each received write in the page. Alternatively, the memory device <NUM> may be programmed to operate using a programmed state mapping <NUM>i. The I/O logic <NUM> selects (at block <NUM>) n pages in the transfer buffer <NUM> to write, where the n pages provide the n bits for each multi-level storage cell, e.g., two pages provides two bits for an MLC NAND, three pages provides three bits for a TLC NAND, etc..

For each instance of k bits of information in the selected n pages a loop of operations is performed at blocks <NUM> through <NUM>. At block <NUM>, the transformation layer <NUM> selects (at block <NUM>) the significant bit sections, e.g., most significant bits (MSB), least significant bits (LSBs), etc., from the selected pages to form k bits of information to write. A storage cell group is selected (at block <NUM>) comprising a first selected storage cell group or following the previous storage cell group written. The transformation layer <NUM>i determines (at block <NUM>) from the cell mapping, e.g., <FIG>, <FIG>, the threshold voltage levels from the lower threshold voltage levels to use for each of the storage cells in the storage cell group to program the selected k bits. The selected threshold voltages may be from a subset of the lowest threshold voltage levels available for the storage cells. The transformation layer <NUM>i uses (at block <NUM>) the determined threshold voltage levels to program the storage cells in the storage cell group to program. Before programming the m bits of information, the scrambler units <NUM><NUM>, <NUM><NUM>. <NUM>n may scramble the bits before writing.

<FIG> provide an embodiment for programming three bits read from two pages to each storage cell group of two storage cells in two programming cycles. The storage cells each store two bits (n=<NUM>) and each storage cell group comprises a storage cell pair (p=<NUM>). The mappings show how to map the received three bits to the storage cells storing four bits, using the three lowest voltage levels. The arrows in <FIG> show the permissible voltage level changes to the state by programming one or both cells to one of the voltages P1, P2, P3 to produce valid states having at least one invalid state at the next threshold voltage in either the horizontal or vertical direction.

<FIG> shows the first step is to program one of the four values for the LSBs, to <NUM>, <NUM>, <NUM> or <NUM> during the first programming cycle, which would have been programmed during a block erase. During a first programming cycle, the first storage celli of the pair is not programmed, programmed to P1, P2, P3 and the second storage cellj of the pair can be programmed to P1 or P3. With the first programming cycle, an invalid state is left between every pair of valid states in the vertical direction.

<FIG> shows a second programming step to program the MSB bit to a <NUM> by not performing any programming of either of the cellsi,j or by programming just the second storage cellj two threshold voltage levels so the next valid state is two threshold voltage levels away, leaving an invalid state between two valid states in the horizontal direction. The direction of the arrows in <FIG> are always from a lower voltage level to a higher voltage level, which is a legal move in NAND programming.

<FIG> provides a table showing how the pair of storage cellsi,j are programmed during the first and second programming cycles for the different possible three bits when the LSBs are programmed first, based on the table mappings shown in <FIG>. The programming of <FIG> would be used when writing the LSBs first to one of the storage cell pairs. Different programming steps may be provided than those shown in <FIG> to program the LSB first.

<FIG> provide an embodiment for programming the received block (e.g., read and write unit) of three bits in the storage cell group when the MSB bit is programmed first to the storage cell pair, where the storage cells each store two bits (n=<NUM>) and each storage cell group comprises a storage cell pair (p=<NUM>). The arrows in <FIG> shows the permissible voltage level changes to the states in <FIG> by programming one or both cells to the available four threshold voltage levels P1, P2, and P3 in a way that leaves an invalid state between any two valid states in either the horizontal or vertical directions.

<FIG> shows that no voltage needs to be applied to program the MSB to the E threshold voltage or "<NUM>", which would have been programmed before during a block erase. During a first programming step, programming the first storage cellj and the second storage cellj of the pair to the P2 threshold voltage programs the MSB to "<NUM>".

<FIG> shows a second programming step to program the LSB bits with an MSB bit of <NUM> by setting the cellsi,j to one of the four threshold voltage levels E, P1, P2, and P3. No voltage needs to be applied to program the LSBs to the E threshold voltage to program a "<NUM>" when the MSBs is "<NUM>". <FIG> shows that the LSBs are programmed when the MSB is first programmed to "<NUM>" by: (<NUM>) programming the first cell<NUM> of the pair to the P2 threshold voltages to program the LSBs to "<NUM>"; (<NUM>) programming the first storage cell<NUM> to P1 and second storage cellj of the pair to the P1 threshold voltage to program the LSBs to "<NUM>"; and (<NUM>) programming the first cell<NUM> to P3 and the second cellj to the P1 threshold voltage to program the LSBs to "<NUM>". <FIG> further shows that the LSBs are programmed when the MSB is first programmed to "<NUM>" by: (<NUM>) programming the first celli to the P2 threshold to program the LSBs to "<NUM>"; (<NUM>) programming the storage cellsi,j to P3 to program the LSBs to "<NUM>"; and (<NUM>) programming the first storage celli of the pair to the P1 threshold voltage and the second storage cellj to P3 to program the LSBs to "<NUM>".

<FIG> provides a table showing how the pair of storage cellsi,j are programmed during the first and second programming cycles for the different possible three input bits when the MSB is programmed first, based on the table mappings shown in <FIG>, and 11c. The programming of <FIG> would be used when performing the writing of the MSBs and LSBs in <FIG>, where the MSB is programmed first.

<FIG>, <FIG> illustrate different embodiments for performing the operations at blocks <NUM> and <NUM> using the mappings shown in <FIG>, 9C, <FIG>, <FIG>, 11C, <FIG> in embodiments where each storage cell comprises a storage cell pair of two storage cells (p=<NUM>) and each storage cell has <NUM> bits (n=<NUM>), and each device page <NUM>i is allocated two pages, a lower <NUM> and upper <NUM>, such as the case for an MLC NAND.

<FIG> illustrates an embodiment of operations to program the storage cell pairs when the number of received bits <NUM> for each block to write from the selected two pages, upper and lower, is three and each storage cell group is a pair of two storage cells (n=<NUM>). A mentioned, the three selected bits from the pages may be compressed, encrypted, and include error correction codes. Upon initiating the write (at block <NUM>) for selected upper and lower pages, the transformation layer <NUM>i performs a loop of operations at blocks <NUM> through <NUM> for each <NUM> bits of information to write from the two pages. At block <NUM>, a determination is made as to whether the one MSB or the LSBs were selected to program first for the last storage cell pair written. If (at block <NUM>) the LSBs were programmed first for a previous storage cell pair or if the current storage cell to program is the first to program, the transformation layer <NUM>i selects (at block <NUM>) the MSB from the selected lower page and the two LSBs from the upper page. The mapping for the programming the MSB first (<FIG>, <FIG>) is used (at block <NUM>) to determine each threshold voltage for each storage cell of the storage cell pair being programming. In a first programming cycle to program the MSB first, each storage cell of the pair is programmed (at block <NUM>) with the determined threshold voltage for the storage cell. The transformation layer <NUM>i uses (at block <NUM>) the mapping for programming LSBs second (as in <FIG>, <FIG>) depending on whether the MSB was programmed to a <NUM> or <NUM> to determine each threshold voltage for each storage cell. In a second programming cycle to program the two LSBs second, the transformation layer <NUM>i programs (at block <NUM>) each storage cell with the determined threshold voltage for the storage cell.

If (at block <NUM>) the one MSB was programmed first for a previous storage cell pair or if the current storage cell to program is the first to program, the transformation layer <NUM>i selects (at block <NUM>) the MSB from the selected upper page and the two LSBs from the lower page. The mapping for the programming the LSBs first (<FIG>) is used (at block <NUM>) to determine each threshold voltage for each storage cell of the storage cell pair being programming. In a first programming cycle to program the LSBs first, each storage cell of the pair is programmed (at block <NUM>) with the determined threshold voltage for the storage cell. The transformation layer <NUM>i uses (at block <NUM>) the mapping for programming MSB second (as in <FIG>, <FIG>) depending on whether programmed LSB s are "<NUM>", "<NUM>", "<NUM>", or "<NUM>" to determine each threshold voltage for each storage cell. In a second programming cycle to program the one MSB second, the transformation layer <NUM>i programs (at block <NUM>) each storage cell with the determined threshold voltage for the storage cell.

<FIG> illustrates the operations of <FIG> in that the MSB and LSBs are alternately selected from the lower and upper pages between storage cell groups to alternate selecting the first MSB bit and two LSB bits between the lower <NUM> and upper <NUM> page. For instance as shown in <FIG>, for the first pair storage cells<NUM>,<NUM>, the MSB (M<NUM>) is selected from the lower page <NUM> and LSBs upper page <NUM> and then in cells<NUM>,<NUM> the MSB is alternately selected from the upper page <NUM> and the LSBs from the lower page <NUM>.

<FIG> illustrates an alternative embodiment for selecting the MSB and LSB bits when there are three bits to select from two pages by always selecting the MSB bit from the lower page <NUM> and always selecting the two LSB bits from the upper page <NUM>.

The selection of pages to program together, such as at step <NUM> of <FIG>, may be based on the page size after compression (i.e. compression ratio), e.g. to map two pages with similar size. <FIG> may be used to map two pages with a two-time size difference.

<FIG> illustrates an alternative embodiment for selecting the MSB and LSB bits when the writing the storage cell groups switch between half states and quarter states, such that every other storage cell group is a half state and every other is a quarter state.

<FIG> illustrates an embodiment of operations to perform the programming cycles when the two pages provide blocks of two bits to write and each storage cell group is a pair of two storage cells and where each of the selected pages <NUM> or <NUM> provides one bit for every other storage cell. Upon initiating (at block <NUM>) the writing, the transformation layer <NUM>i performs a loop of operations at blocks <NUM> through <NUM> to transform the received <NUM> bits per storage cell pair. The MSB and LSBs are selected (at block <NUM>) from the lower and upper pages, respectively. The mapping (<FIG>) for programming two bits, one from each of the pages, is used (at block <NUM>) to select the threshold voltage levels from each of the storage cells, where only the two lowest threshold voltage levels need to be used to program all possible states of the storage cell pair having just two bits.

Although <FIG>, <FIG>, and <FIG> are described with respect to an embodiment of storage cells storing two bits (n=<NUM>) and each storage cell group comprising a storage cell pair (p=<NUM>), the writing of the fewer number of received k bits to a group of storage cells storing m bits can be extended to other size storage cell groups and storage cells storing more than two bits by alternating the pages to which the fewer number of the MSB bits are written. Alternating the pages to which the smaller number of the MSB bits of the k bits are written distributes the smaller number of MSB bits and larger number of LSBs among the pages to provide wear leveling of the writing to the pages.

<FIG> illustrates an embodiment of operations performed by the I/O logic <NUM> and/or the transformation layer <NUM>i to read a page of blocks of data in storage cell groups, such as when each block is stored in a storage cell pair. Upon initiating (at block <NUM>) the read operation for a device page <NUM>i of storage cell groups, the I/O logic <NUM> determines (at block <NUM>) the state mapping <NUM>i to use, which may be indicated in the device page information <NUM>i for the page to read or may be determined from an operational mode of the memory storage device <NUM>. The state from the storage cell group in the device page <NUM>i is read (at block <NUM>), such as a threshold voltage level for each of the p storage cells in the storage cell group. The I/O logic <NUM> decodes (at block <NUM>) the read state represented by read threshold voltage levels from the p cells in the storage cell group. A determination is made (at block <NUM>) whether the read m bits are in a valid state, such as by performing an XOR of the read m bits to determine if they have odd parity, or an even number of <NUM>, which indicates a valid state.

If (at block <NUM>) the m bits are in a valid, then the transformation layer <NUM>i determines (at block <NUM>) the bit translation functions <NUM> for the read m bits of information for a device page <NUM>i, such as the translation functions (<NUM>), (<NUM>), and (<NUM>) described above with respect to a storage cell pair where k = <NUM> bits and where k = <NUM> bits. The transformation layer <NUM>i applies (at block <NUM>), for each storage cell group in the read page, the determined translation functions to translate the decoded m bits of information to a block of fewer k bits of information and returns (at block <NUM>) the block of k bits and indication of the k bits that are marked as erroneous to the host requesting the page of data. In returning the translated k (or <NUM> bits), the transformation layer <NUM>i may alternately write the MSB and LSBs read for each storage cell pair when writing the bits to upper and lower pages.

If (at block <NUM>) the m bits do not map to a valid state in the state mapping <NUM>i, then the m bits and the k bits translated therefrom are set (at block <NUM>) to a default invalid value, such as all <NUM>. The k bits set with the default error value are returned (at block <NUM>) with error decoding information, such as the location of the cell group, the value of the invalid voltage states, etc..

<FIG> illustrates an embodiment of operations performed by the components of the non-volatile memory storage device <NUM> to process a page of bits of information to store in the storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n, including the data compression unit <NUM>, data encryption unit <NUM>, error correction unit <NUM>, scrambler unit <NUM>i, and controller <NUM>i. Upon receiving (at block <NUM>) a page of data to store in the NAND storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n, the compression unit <NUM> compresses (at block <NUM>) the received page to produce instances of compressed bits of information and sends to the encryption unit <NUM>. The encryption unit <NUM> encrypts (at block <NUM>) the compressed bits of information in the page to produce encrypted and compressed bits of information. The error correction unit <NUM> calculates (at block <NUM>) parity information, e.g., error correction codes for the data, to store with the compressed/encrypted data and outputs the page to the controller channel <NUM>. The pages of the compressed/encrypted data with the parity information are stored (at block <NUM>) in the transfer buffer <NUM>. The storage die controller <NUM>i and transformation layer <NUM>i selects (at block <NUM>) the pages for a device page to translate instances of k bits from the selected pages to m bits of information to store in the storage cell groups of the device page according to operations of <FIG>, <FIG>, and <FIG> and sends to the scrambler unit <NUM>i. The scrambler unit <NUM>i scrambles (at block <NUM>) instances of the translated m bits in a device page which are then written to the storage cells in the storage die <NUM>i.

<FIG> illustrates an embodiment of operations performed by the components of the non-volatile memory storage device <NUM> to process data read from the storage dies <NUM><NUM>, <NUM><NUM>. <NUM>n, including the data compression unit <NUM>, data encryption unit <NUM>, scrambler unit <NUM>i, and controller <NUM>i. Upon reading (at block <NUM>) a page of data to return from storage cell pairs in a storage die <NUM>i, the page having instances of m bits is sent (at block <NUM>) to the corresponding scrambler unit <NUM>i for the storage die <NUM>i. The scrambler unit <NUM>i descrambles (at block <NUM>) the instances of m bits in the page and sends to the translation layer <NUM>i The translation layer <NUM>i translates (at block <NUM>) the instances of read m bits from the page into the instances of k bits and marks k bits as erroneous if translated from an invalid state according to the operations of <FIG>. The I/O logic <NUM> distributes (at block <NUM>) instances of the k bits to n pages associated with the device page <NUM>i. The error correction unit <NUM> uses (at block <NUM>) error information including information on the k bits having the invalid state and parity codes to correct erroneous k bits. The error correction unit <NUM> may perform erasure correction, which comprises error correction with the known location, or storage cell group, experiencing the error/invalid state. The encryption unit <NUM> decrypts (at block <NUM>) the error corrected bits for each page to produce the page having compressed bits of information and sends to the compression unit <NUM>. The compression unit <NUM> decompresses (at block <NUM>) the page to produce the decompressed pages to return (at block <NUM>).

With the described operations of <FIG>, <FIG>, and <FIG>, the transformation layer <NUM>i or I/O logic <NUM> uses the normal page mapping by writing to the same storage cells without requiring special translation to manage the page and track size, because the described embodiments read the data for all the storage cells on the page boundaries, but translates the read m bits of information into a block of fewer k bits provided by a host operating system. Further, the described embodiments improve error correction by providing exact information on the bits or storage cells experiencing an error, or erasure information.

<FIG> illustrates an embodiment of a system <NUM> in which the memory device <NUM> may be deployed as the system memory device <NUM> and/or a storage device <NUM>. The system includes a processor <NUM> that communicates over a bus <NUM> with a system memory device <NUM> in which programs, operands and parameters being executed are cached, and a storage device <NUM>, which may comprise a solid state drive (SSD) that stores programs and user data that may be loaded into the system memory <NUM> for execution. The processor <NUM> may also communicate with Input/Output (I/O) devices 1712a, 1712b, which may comprise input devices (e.g., keyboard, touchscreen, mouse, etc.), display devices, graphics cards, ports, network interfaces, etc. The memory <NUM> and storage device <NUM> may be coupled to an interface on the system <NUM> motherboard, mounted on the system <NUM> motherboard, or deployed in an external memory device or accessible over a network.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Furthermore, the particular features, structures or characteristics may be combined as suitable in one or more embodiments of the invention.

The reference characters used herein, such as i, j, m, n, and pare used to denote a variable number of instances of an element, which may represent the same or different values, and may represent the same or different value when used with different or the same elements in different described instances.

Similarly, it should be appreciated that in the foregoing description of embodiments of the invention, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed subject matter requires more features than are expressly recited in each claim. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description.

The following examples pertain to further embodiments.

Example <NUM> is an apparatus for programming states of storage cells to provide error location information for retention errors, comprising: a non-volatile memory having storage cells comprised in storage dies, wherein each storage cell is programmed with information using a plurality of threshold voltage levels, and wherein each storage cell is programmed from bits from a plurality of pages; and a memory controller configured to program the storage cells and to: organize the storage cells in the non-volatile memory into storage cell groups, wherein each storage cell group stores m bits of information, wherein each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels; select k bits from the pages to write for one storage cell group, wherein k < m, and wherein k and m are integer values greater than zero; and determine one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected k bits in the storage cell group, wherein each k bits are programmed with threshold voltage levels defining one of a plurality of valid states, wherein the threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels. The threshold voltage levels for the storage cells in a storage cell group are capable of programming a total number of states for a storage cell group including valid states in which the selected k bits are programmed and invalid states in which the selected k bits are not programmed. The threshold voltage levels for the storage cells in the storage cell groups define the valid states and the invalid states such that the storage cells of the storage cell group programmed in any valid state experiencing leakage of one threshold voltage level would transition to an invalid state. The memory controller is configured to map the k bits to a subset of valid states of the <NUM>np states that can be programmed in a storage cell group comprising p storage cells, with n being the number of levels supported by the storage cells, with m = Log<NUM>(<NUM>np).

In Example <NUM>, the subject matter of examples <NUM> and <NUM>-<NUM> can optionally include that the valid states are one-half of the total number of states and configured such that if the k bits programmed into the storage cells of one of the storage cell groups in one of the valid states experience leakage of one threshold voltage level, then the leakage would result in the storage cells representing the k bits transition to one of the invalid states.

In Example <NUM>, the subject matter of examples <NUM>, <NUM> and <NUM>-<NUM> can optionally include that the valid states are one-quarter of the total number of states and configured such that an average voltage distance between any two valid states comprises at least two threshold voltage levels.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>, <NUM> and <NUM>-<NUM> can optionally include that the memory controller is further to: read threshold voltage levels for the storage cells in one of the storage cell groups; decode the read threshold voltage levels to obtain decoded m bits; determine whether the decoded m bits comprise one of the valid states; translate the decoded m bits to k bits to return; and mark the k bits as erroneous in response to determining that the decoded m bits do not comprise one of the valid states.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>-<NUM> and <NUM>-<NUM> can optionally include that the determine whether the decoded m bits comprise one of the valid states comprises: perform a logical function on the decoded m bits, wherein the valid state is determined if a result of the logical function on the decoded m bits has a first value and wherein the invalid state is determined if the result of the logical function on the decoded m bits has a second value.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>-<NUM> and <NUM>-<NUM> can optionally include that an error correction unit to generate error correction information for the k bits, wherein in response to determining that the decoded m bits comprise one of the invalid states, the memory controller is further to: set the k bits to a default error value; and provide information to the error correction unit on the k bits having one of the invalid states to provide error correction to the k bits.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>-<NUM> and <NUM>-<NUM> can optionally include that the memory controller is further to: provide translation functions based on a truth table associating each possible k bits with the valid states; and use the translation functions to translate the selected k bits of information to the m bits to program in one of the storage cell groups and to translate a read m bits of information from one of the storage cell groups to the k bits of information.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>-<NUM> and <NUM> can optionally include that there are at least two significant bit sections of the k bits of information, wherein select the k bits from the pages for a current storage cell group comprises selecting significant bit sections from different pages from which the significant bit sections were selected for a previous storage cell group.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>-<NUM> can optionally include that the memory controller is further to: read the m bits of information from one of the storage cell groups; translate the read m bits of information to a translated k bits of information; and for each storage cell group, alternate writing the significant bit sections of the translated k bits of information to different pages to which the significant bit sections were written for a previous storage cell group.

Example <NUM> is a system for programming states of storage cells to provide error location information for retention errors, comprising: a processor; a bus, wherein the processor is coupled to the bus; and a non-volatile memory having: storage cells, wherein each storage cell is programmed with information using a plurality of threshold voltage levels, and wherein each storage cell is programmed from bits from a plurality of pages; and a memory controller configured to program the storage cells and to: organize the storage cells in the non-volatile memory into storage cell groups, wherein each storage cell group stores m bits of information, wherein each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels; select k bits from the pages to write for one storage cell group, wherein k < m, and wherein k and m are integer values greater than zero; and determine one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected k bits in the storage cell group, wherein each k bits are programmed with threshold voltage levels defining one of a plurality of valid states, wherein the threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels. The threshold voltage levels for the storage cells in a storage cell group are capable of programming a total number of states for a storage cell group including valid states in which the selected k bits are programmed and invalid states in which the selected k bits are not programmed. The threshold voltage levels for the storage cells in the storage cell groups define the valid states and the invalid states such that the storage cells of the storage cell group programmed in any valid state experiencing leakage of one threshold voltage level would transition to an invalid state. The memory controller is configured to map the k bits to a subset of valid states of the <NUM>np states that can be programmed in a storage cell group comprising p storage cells, with n being the number of levels supported by the storage cells, with m = Log<NUM>(<NUM>np).

In Example <NUM>, the subject matter of examples <NUM>, <NUM> and <NUM>-<NUM> can optionally include that the memory controller is further to: read threshold voltage levels for the storage cells in one of the storage cell groups; decode the read threshold voltage levels to obtain decoded m bits; determine whether the decoded m bits comprise one of the valid states; translate the decoded m bits to k bits to return; and mark the k bits as erroneous in response to determining that the decoded m bits do not comprise one of the valid states.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>, <NUM> and <NUM> can optionally include that the determine whether the decoded m bits comprise one of the valid states comprises: perform a logical function on the decoded m bits, wherein the valid state is determined if a result of the logical function on the decoded m bits has a first value and wherein the invalid state is determined if the result of the logical function on the decoded m bits has a second value.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>-<NUM> can optionally include that an error correction unit to generate error correction information for the k bits, wherein in response to determining that the decoded m bits comprise one of the invalid states, the memory controller is further to: set the k bits to a default error value; and provide information to the error correction unit on the k bits having one of the invalid states to provide error correction to the k bits.

Example <NUM> is a method for programming states of storage cells in a non-volatile memory to provide error location information for retention errors, comprising: programming storage cells in the non-volatile memory, the storage cells being comprised in storage dies, wherein each storage cell is programmed with information using a plurality of threshold voltage levels, and wherein each storage cell is programmed from bits from a plurality of pages; organizing the storage cells in the non-volatile memory into storage cell groups, wherein each storage cell group stores m bits of information, wherein each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels; selecting k bits from the pages to write for one storage cell group, wherein k < m, and wherein k and m are integer values greater than zero; and determining one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected k bits in the storage cell group, wherein each k bits are programmed with threshold voltage levels defining one of a plurality of valid states, wherein the threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels. The threshold voltage levels for the storage cells in a storage cell group are capable of programming a total number of states for a storage cell group including valid states in which the selected k bits are programmed and invalid states in which the selected k bits are not programmed. The threshold voltage levels for the storage cells in the storage cell groups define the valid states and the invalid states such that the storage cells of the storage cell group programmed in any valid state experiencing leakage of one threshold voltage level would transition to an invalid state. The method comprises mapping the k bits to a subset of valid states of the <NUM>np states that can be programmed in a storage cell group comprising p storage cells, with n being the number of levels supported by the storage cells, with m = Log<NUM>(<NUM>np).

In Example <NUM>, the subject matter of examples <NUM>, <NUM> and <NUM>-<NUM> can optionally include reading threshold voltage levels for the storage cells in one of the storage cell groups; decoding the read threshold voltage levels to obtain decoded m bits; determining whether the decoded m bits comprise one of the valid states; translating the decoded m bits to k bits to return; and marking the k bits as erroneous in response to determining that the decoded m bits do not comprise one of the valid states.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>,<NUM> and <NUM> can optionally include that the determining whether the decoded m bits comprise one of the valid states comprises: performing a logical function on the decoded m bits, wherein the valid state is determined if a result of the logical function on the decoded m bits has a first value and wherein the invalid state is determined if the result of the logical function on the decoded m bits has a second value.

In Example <NUM>, the subject matter of examples <NUM>, <NUM>-<NUM> can optionally include generating error correction information for the k bits, wherein in response to determining that the decoded m bits comprise one of the invalid states, further comprising: setting the k bits to a default error value; and providing information to an error correction unit on the k bits having one of the invalid states to provide error correction to the k bits.

In Example <NUM>, the subject matter of example <NUM> can optionally include at least any one of:.

Claim 1:
An apparatus for programming states of storage cells to provide error location information for retention errors, comprising:
a non-volatile memory (<NUM>) comprising storage cells comprised in storage dies (<NUM><NUM>... <NUM>n), wherein each storage cell is programmed with information using one of a plurality of threshold voltage levels, and wherein each storage cell is programmed from bits from a plurality of pages; and
a memory controller (<NUM>) configured to program the storage cells and to:
organize the storage cells in the non-volatile memory (<NUM>) into storage cell groups, wherein each storage cell group has a size corresponding to m bits of information, wherein each of the storage cells in each of the storage cell groups is programmed with one of the plurality of threshold voltage levels;
select a value of k bits from the plurality of pages to write to one storage cell group, wherein k < m, and wherein k and m are integer values greater than zero; and
determine one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected value of k bits in the storage cell group, wherein the selected value of k bits is programmed with threshold voltage levels defining one of a plurality of valid states, wherein the threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels,
wherein the threshold voltage levels for the storage cells in the storage cell group define a total number of states for the storage cell group including the plurality of valid states in which the storage cell group can be programmed and a plurality of invalid states in which the storage cell group cannot be programmed,
wherein the threshold voltage levels for the storage cells in the storage cell group define the valid states and the invalid states such that the storage cell group, after being programmed in the one of the plurality of valid states, when experiencing leakage of one threshold voltage level, transitions to one of the plurality of invalid states,
wherein the memory controller is configured to map the selected value of k bits to the one of the plurality of valid states, wherein the plurality of valid states is a subset of <NUM>np states corresponding to a size of the storage cell group comprising p storage cells, with n being the number of bits supported by each of the storage cells, with m = Log<NUM>(<NUM>np).