Patent Description:
Semiconductor memory devices are memory devices using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and/or the like. Semiconductor memory devices may be largely classified into volatile memory devices or nonvolatile memory devices.

The nonvolatile memory device is a memory device which can retain data even when the supply of power is interrupted. Examples of nonvolatile memory devices include read-only memory (ROM), programmable ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory device, phase-change random-access memory (PRAM), magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), ferroelectric random-access memory (FRAM), and the like. The flash memory device may be broadly classified into NOR flash memory and NAND flash memory.

The nonvolatile memory device may be included in, for example, an MP3 player, a digital camera, a smartphone, a camcorder, a flash card, a solid state disk (SSD), and/or the like. During operation of the nonvolatile memory device, a bit line operating voltage and a word line operating voltage are generated to control a memory cell. In these cases, if the bit line operating voltage and the word line operating voltage are not adjusted according to the temperature, an error may occur in data sensed by the memory cell.

<CIT> discloses a method for programming a memory device and a memory system, wherein the method for programming the memory device includes steps below. First, a program command is proposed. Second, a width of a pulse about to provide to strings of memory cells of the memory device is determined according to a temperature data of the memory device. Then, the pulse is provided to the strings of memory cells to start doing a program operation. The width of the pulse becomes narrower as a temperature of the memory device is raised.

Aspects of the present disclosure provide a nonvolatile memory device with improved operating performance by adaptively compensating an operating voltage for each operating temperature range, and an operating method thereof.

Aspects of the present disclosure provide a nonvolatile memory device that provides more reliable data by varying compensation for each temperature range while using a digital temperature sensor, and an operating method thereof.

However, aspects of the present disclosure are not restricted to those described herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to an aspect of the present disclosure, there is provided a nonvolatile memory device including: a memory cell array including a plurality of memory cells; an address decoder configured to decode a row address and a column address from an address signal; a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array according to the decoded row address; a second voltage generator configured to generate a bit line operating voltage of the memory cell array according to the decoded column address; a page buffer circuit configured to activate according to the bit line operating voltage and to store data to be stored in or read from at least one memory cell; and a temperature unit configured to determine, from a temperature range table storing a plurality of selection signals mapped to each of a plurality of temperatures ranges, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of at least one of the first or second voltage generator based on a selection signal mapped to the determined temperature range, wherein the page buffer circuit includes: a precharge circuit comprising at least one transistor controlled by a bit line setup signal output from a control circuit; and a shutoff circuit comprising at least one transistor controlled by a bit line shutoff signal, wherein the second voltage generator includes a bit line shutoff signal generator configured to adjust a voltage level of the bit line shutoff signal according to an output of the temperature unit.

It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent from the following description. The invention is defined in the appended independent claim. Further developments of the invention are specified in the dependent claims.

The above and other aspects and features of the present disclosure will become more apparent by describing in detail some example embodiments thereof with reference to the attached drawings, in which:.

Hereinafter, a memory device according to some example embodiments of the present disclosure will be described with reference to <FIG>. Unless otherwise noted, like reference characters denote like elements throughout the attached drawings and written description, and thus descriptions will not be repeated.

The functional blocks described this disclosure may denote elements that process (and/or perform) at least one function or operation and, unless indicated otherwise, may be included in (and/or implemented as) processing circuitry such hardware, software, or a combination of hardware and software. For example, the processing circuitry more specifically may include (and/or be included in), but is not limited to, a processor (and/or processors), Central Processing Unit (CPU), a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc..

Although terms like "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and/or sections, these terms are only used to distinguish one element, component, region, layer, or section, from another region, layer, or section. Thus, these elements, components, regions, layers, and/or sections should not be otherwise limited by these terms. Therefore, a first element, component, region, layer, or section, discussed below may be termed a second element, component, region, layer, or section, without departing from the scope of this disclosure.

<FIG> is a block diagram illustrating a memory system according to some example embodiments of the present disclosure. Referring to <FIG>, a memory system <NUM> may include a memory device <NUM> and a memory controller <NUM>. The memory system <NUM> may support a plurality of channels CH1 to CHm, and the memory device <NUM> and the memory controller <NUM> may be connected through the plurality of channels CH1 to CHm. For example, the memory system <NUM> may be implemented as a storage device of an electronic device, a storage device (such as a universal flash storage (UFS) and/or a solid state drive (SSD)), a storage device included in a data center, and/or the like.

The memory device <NUM> may include a plurality of nonvolatile memory devices <NUM> (e.g., NVM11 to NVMmn). Each of the nonvolatile memory devices <NUM> (e.g., NVM11 to NVMmn) may be connected to one of the plurality of channels CH1 to CHm through a corresponding way. For example, the nonvolatile memory devices NVM11 to NVM1n may be connected to the first channel CH1 through the ways W11 to W1n, and the nonvolatile memory devices NVM21 to NVM2n may be connected to the second channel CH2 through the ways W21 to W2n. In some example embodiments, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented in the form of an arbitrary memory unit capable of operating according to an individual command from the memory controller <NUM>. For example, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as a chip or a die, but the present disclosure is not limited thereto.

The memory controller <NUM> may transmit and receive signals to and from the memory device <NUM> through the plurality of channels CH1 to CHm. For example, the memory controller <NUM> may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device <NUM>, and/or receive the data DATAa to DATAm from the memory device <NUM>, through the channels CH1 to CHm.

Through each of the channels CH1 to CHm, the memory controller <NUM> may select one of the nonvolatile memory devices <NUM> connected to the corresponding channel CH1 to CHm and transmit and receive signals to and from the selected nonvolatile memory device. For example, as illustrated in <FIG>, the memory controller <NUM> may select nonvolatile memory device NVM11 from among the nonvolatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller <NUM> may transmit a command CMDa, an address ADDRa, and data DATAa to the selected nonvolatile memory device NVM11, and/ receive data DATAa from the selected nonvolatile memory device NVM11, through the first channel CH1.

The memory controller <NUM> may transmit and receive signals to and from the memory device <NUM> in parallel through different channels. For example, the memory controller <NUM> may transmit a command CMDb to the memory devices NVM21 to NVM2n through the second channel CH2 while transmitting a command CMDa to the memory devices NVM11 to NVM1n through the first channel CH1. For example, the memory controller <NUM> may receive data DATAb from the memory devices NVM21 to NVM2n through the second channel CH2 while receiving data DATAa from the memory devices NVM11 to NVM1n through the first channel CH1.

The memory controller <NUM> may control the overall operation of the memory device <NUM>. The memory controller <NUM> may transmit signals to the channels CH1 to CHm to control each of the nonvolatile memory devices <NUM> (e.g., NVM11 to NVMmn) connected to the channels CH1 to CHm. For example, the memory controller <NUM> may transmit the command CMDa and the address ADDRa to the first channel CH1 to control a selected one of the nonvolatile memory devices <NUM> (e.g., a selected one of NVM11 to NVM1n).

Each of the nonvolatile memory devices <NUM> (e.g., NVM11 to NVMmn) may operate under the control of the memory controller <NUM>. For example, the nonvolatile memory device NVM11 may program the data DATAa according to the command CMDa, the address ADDRa, and the data DATAa provided to the first channel CH1. For example, the nonvolatile memory device NVM21 may read the data DATAb according to the command CMDb and the address ADDRb provided to the second channel CH2, and may transmit the read data DATAb to the memory controller <NUM>.

Although it is illustrated in <FIG> that the memory device <NUM> communicates with the memory controller <NUM> through m channels, and that the memory device <NUM> includes n nonvolatile memory devices <NUM> corresponding to each channel CH, the present disclosure is not limited thereto, and the number of channels and the number of nonvolatile memory devices connected to one channel may vary.

<FIG> is a block diagram illustrating a nonvolatile memory device according to some example embodiments of the present disclosure. Referring to <FIG>, a nonvolatile memory device <NUM> may include a memory cell array <NUM>, an address decoder <NUM>, a control logic and voltage generator <NUM>, a page buffer circuit <NUM>, an input/output circuit <NUM>, and a temperature unit <NUM>.

The memory cell array <NUM> may include a plurality of memory blocks. Each memory block may include memory cells forming, e.g., a two-dimensional structure (e.g., an array) and/or a three-dimensional structure (e.g., a stack). For example, memory cells of each memory block may also be stacked in a direction perpendicular to a substrate to form a three-dimensional structure. Each memory block may include a plurality of cell strings, and each cell string may include a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL. Each memory cell may be provided as a single level cell (SLC) storing <NUM> bit and/or a multi level cell (MLC) storing at least <NUM> bits.

In some example embodiments, the address decoder <NUM> may be connected to the memory cell array <NUM> through the plurality of word lines WL, a string select line SSL, and a ground select line GSL. In some example embodiments, e.g., when the memory cell array <NUM> is formed in a three-dimensional structure, the address decoder <NUM> may be connected to the memory cell array <NUM> through a plurality of word lines WL, a plurality of string select lines SSL, and a plurality of ground select lines GSL. The address decoder <NUM> may receive an address ADDR from an external device (e.g., a memory controller, a host, an AP, etc.), and may decode the received address ADDR to select at least one word line from among the plurality of word lines WL. The address decoder <NUM> may control voltages of the plurality of word lines WL to perform a read and/or write operation on the selected word line. In some example embodiments, the address decoder <NUM> may decode a column address of the received address and transfer the decoded column address to the page buffer circuit <NUM>. The page buffer circuit <NUM> may control the bit line BL based on the received column address.

The control logic and voltage generator <NUM> may receive a command CMD and a control signal CTRL from an external device, and may control the address decoder <NUM>, the page buffer circuit <NUM>, and the input/output circuit <NUM> in response to the received signals. For example, the control logic and voltage generator <NUM> may control the address decoder <NUM>, the page buffer circuit <NUM>, and the input/output circuit <NUM> in response to the command CMD and the control signal CTRL such that data DATA is written to the memory cell array <NUM>. Alternatively, the control logic and voltage generator <NUM> may control the address decoder <NUM>, the page buffer circuit <NUM>, and/or the input/output circuit <NUM> in response to the command CMD and the control signal CTRL such that data DATA stored in the memory cell array <NUM> is output. Alternatively, the control logic and voltage generator <NUM> may control the address decoder <NUM>, the page buffer circuit <NUM>, and the input/output circuit <NUM> in response to the command CMD and the control signal CTRL such that a part of the memory cell array <NUM> is deleted.

The control logic and voltage generator <NUM> may generate various voltages used in the operation of the nonvolatile memory device <NUM>. For example, the control logic and voltage generator <NUM> may generate a plurality of read voltages, a plurality of verify voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of erase voltages, and so on, and may provide the generated voltages to the address decoder <NUM>.

According to some embodiments, the voltage generator <NUM> may be (and/or include) a plurality of voltage generators including a word line operating voltage generator for the word line operation of the memory cell array, a bit line operating voltage generator for the bit line operation, and a voltage generator for generating operating voltages for other components included in the nonvolatile memory device <NUM>. The bit line operating voltage generator may apply a different operating voltage to each of the page buffer circuits <NUM> of a selected column and an unselected column, respectively, according to the decoded column address. The word line operating voltage generator may apply a different word line operating voltage to each of the selected word line, adjacent word lines of the selected word line, and unselected non-adjacent word lines according to a decoded row address.

The temperature unit <NUM> may measure the temperature state of the nonvolatile memory device <NUM> in real time, and the control logic and voltage generator <NUM> may be controlled based on the measured temperature (e.g., to control the operating voltage of the memory device <NUM>). According to some embodiments, a read voltage when the nonvolatile memory device <NUM> is at a hot temperature and a read voltage when the nonvolatile memory device <NUM> is at a cold temperature may be adjusted to be different from each other. For example, by controlling the voltage generator <NUM>, a voltage level of a signal supplied to the page buffer circuit <NUM> may be adjusted according to the temperature. For example, by controlling the voltage generator <NUM>, a voltage level of a signal supplied to the address decoder <NUM> may be adjusted according to the temperature. Further details will be described with reference to <FIG>.

The page buffer circuit <NUM> may be connected to the memory cell array <NUM> through a plurality of bit lines BL. The page buffer circuit <NUM> may buffer signals transmitted to and/or from the memory cell array <NUM>. For example, the page buffer circuit <NUM> may temporarily store data DATA read from the memory cell array <NUM> and/or temporarily store data DATA to be written to the memory cell array <NUM>.

The input/output circuit <NUM> may receive data DATA from an external device and transfer the received data DATA to the page buffer circuit <NUM> under the control of the control logic and voltage generator <NUM>. The input/output circuit <NUM> may also transfer data DATA received from the page buffer circuit <NUM> to an external device under the control of the control logic and voltage generator <NUM>.

For example, during a program operation of the nonvolatile memory device <NUM>, data DATA to be programmed to the memory cell array <NUM> may be temporarily stored in the page buffer circuit <NUM>. The nonvolatile memory device <NUM> may program the data DATA stored in the page buffer circuit <NUM> to the memory cell array <NUM> by performing a plurality of program loops. Each of the plurality of program loops may include a program step for applying a program pulse and/or a verify step for applying a verify voltage.

<FIG> is a block diagram illustrating in more detail an example temperature unit <NUM> of <FIG>. <FIG> show graphs for explaining an operation of a temperature unit according to some example embodiments. <FIG> is a temperature range table according to some example embodiments.

Referring to <FIG>, according to some embodiments, the temperature unit <NUM> may include a temperature sensor <NUM>, temperature range determiners <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, a multiplier <NUM>, an adder <NUM>, a multiplexer MUX3 <NUM>, a resistor selector <NUM>, a comparator <NUM>, and a temperature compensation transistor <NUM>.

In some example embodiments, the temperature sensor <NUM> may be a digital temperature sensor (DTS). A digital temperature sensor may, for example, possess better current characteristics and linearity than an analogous analog temperature sensor. The temperature sensor <NUM> may be disposed in a peripheral circuit area of the nonvolatile memory device <NUM> to measure in real time a temperature state according to an operation of the nonvolatile memory device <NUM>. The temperature sensor <NUM> may output a temperature code TEMP code based on the measured temperature. According to some embodiments, each time the temperature changes by a predetermined (and/or otherwise determined) value, the temperature code may change by <NUM>. For example, in some embodiments if the temperature consistently changes by, e.g., <NUM>° C, the temperature code may also constantly and/or consistently change.

According to some embodiments, the temperature sensor <NUM> may sense a temperature state at least twice to increase accuracy and output a temperature code based on an average value of the sensed temperatures. Alternatively, according to some embodiments, the temperature sensor <NUM> may eliminate the variation associated with a location on the basis of pre-stored location information of a memory cell (e.g., a die on which the memory cell is disposed, the location of the die, and so on) and may output the temperature code.

The temperature range table <NUM> includes a plurality of temperature ranges. The temperature code TEMP code output from the temperature sensor <NUM> may be compared to the plurality of temperature ranges, and a temperature range which the temperature code TEMP code falls in may be selected and/or determined, and the range for the temperature code TEMP code is selected, accordingly.

Referring to <FIG>, in an ideal case, the temperature sensor <NUM> possesses linearity (e.g., y=b(x)+c) having a constant slope as seen in ideal the temperature-temperature code graph. Although not illustrated, operating voltage ranges for the word line operating voltage and the bit line operating voltage differ from each other, and thus the word line operating voltage and the bit line operating voltage may have different slope and intercept values in the temperature-temperature code relationship.

However, due to other environmental factors, the temperature code may not have a constant linearity, but may have a nonlinearity with a slope that varies depending on the temperature range. For example, when the temperature range is <NUM> to T1, the temperature code may approximate a linearity of y=b<NUM>(x)+c<NUM>, when the temperature range is T1 to T2, the temperature code may approximate a linearity of y=b<NUM>(x)+c<NUM>, and/or when the temperature range is T2 to T3, the temperature code may approximate a linearity of y=b<NUM>(x)+c<NUM>. In these cases, the coefficients b<NUM>, b<NUM>, and b<NUM> may have different values, and intercepts c<NUM>, c<NUM>, and c<NUM> may also have different values.

Therefore, an analog level of an operating voltage for accessing the memory cell needs to be controlled in a different manner depending on the temperature range in order to reduce an error. For example, the amount of cell current flowing at a cold temperature is small compared with that at a hot temperature. To compensate for this, the analog level of the memory cell operating voltage at a cold temperature should be raised compared to that at a hot temperature, and/or the degree of compensation should be increased as the temperature lowers.

Referring to <FIG>, according to some embodiments, the temperature sensor <NUM> outputs a real-time temperature state of the nonvolatile memory device <NUM> as temperature code TEMP code. For example, the temperature range may be divided into a plurality (e.g., four) ranges and the temperature code TEMP code may be a <NUM>n-bit (e.g., <NUM>-bit) code. In the following description, the temperature range is divided into four ranges and the temperature code TEMP code is an <NUM>-bit code, however the present disclosure is not limited thereto and the number of ranges and/or bits may be more (or less) than described. A selection signal Sel, a coefficient value, and a y-intercept value, which correspond to the temperature code TEMP code output from the temperature sensor <NUM> on the basis of boundary values (e.g., k1, k2, k3, and so on) of each temperature range, may be mapped and stored in the temperature range table <NUM>. For example, when the temperature code is a number greater than the boundary value k2 and smaller than k3 (k2<temp code<k3), the temperature range table <NUM> outputs selection signal Sel=<NUM>, and selects and outputs a coefficient value (coefficient=C) and an intercept value (Y-intercept=c) through the multiplexer MUX1 of <FIG>. In some embodiments the boundary values (e.g., k1, k2, k3, and so on) may be preset and/or otherwise determined and/or adjusted.

According to some embodiments, the temperature range table <NUM> may include only a mapping table for temperature ranges TEMP code based on a boundary value and a selection signal Sel. Alternatively, according to some embodiments, as shown in <FIG>, temperature ranges TEMP code, a selection signal Sel corresponding to each temperature range, a plurality of coefficients, and a plurality of intercepts may be mapped and stored, respectively.

According to some embodiments, the plurality of coefficients and the plurality of intercepts stored may be a plurality of bit line coefficients and a plurality of bit line intercepts associated with a bit line operation for each of the plurality of temperature ranges. Alternatively, according to some embodiments, the plurality of coefficient and the plurality of intercepts stored may be a plurality of word line coefficients and a plurality of word line intercepts associated with a word line operation for each of the plurality of temperature ranges.

According to some embodiments, when the temperature range table <NUM> includes only a mapping table for the temperature ranges TEMP code based on boundary values and selection signals Sel, the temperature unit <NUM> may further include a coefficient selector <NUM> and an intercept selector <NUM>. The coefficient selector <NUM> may be connected to a memory <NUM> including a plurality of coefficients respectively corresponding to the selection signals Sel, and may output any one coefficient based on the selection signal Sel. The intercept selector <NUM> may be connected to a memory <NUM> including a plurality of Y-intercepts respectively corresponding to the selection signals Sel, and may output any one intercept based on the selection signal Sel.

The multiplier <NUM> multiplies the temperature code TEMP code output from the temperature sensor <NUM> and the selected coefficient and outputs the multiplied result. The adder <NUM> adds the selected intercept to the multiplied value output from the multiplier <NUM> and outputs the added value. When the temperature sensor <NUM> is activated to operate, the multiplexer <NUM> selects and outputs the output value of the adder <NUM> (denoted as "DTS on" in <FIG>), and when the temperature sensor <NUM> is deactivated, selects and outputs a preset (and/or otherwise set) value Preset (denoted as "DTS off" in <FIG>).

The resistor selector <NUM> outputs a compensation level obtained by applying a predetermined (and/or otherwise determined) resistance component to the output value of the multiplexer <NUM>. For example, the resistor selector <NUM> may be a voltage divider in which a plurality of resistors are connected in series between a register voltage terminal and a ground terminal. The resistor selector <NUM> may output a reference voltage VREF obtained by dividing the output signal of the multiplexer <NUM> by a predetermined (and/or otherwise determined) ratio. The comparator <NUM> compares the current reference voltage VREF output from the resistor selector <NUM> and a previous compensation level T_Comp and outputs a current compensation level P_Temp. The temperature compensation transistor <NUM>, which may be a P-type transistor connected to a source voltage Vsource, is gated to the current compensation level P_Temp and outputs an output signal OUT, and the previous compensation level (temperature compensation level) for the next section is generated based on the output signal OUT. For example, the previous compensation level T_Comp may have a value in which a resistance ratio based on resistors R1 and R2 with respect to the output signal OUT is considered. In this case, the output signal OUT will be described with reference to <FIG> and <FIG> below.

Therefore, in order to improve performance of a memory device due to the nonlinearity according to temperature, when temperature compensation is performed for an operating voltage applied to each word line and each bit line, the entire temperature range measurable during the operation of the nonvolatile memory device <NUM> may be divided into a plurality of temperature ranges and linearity corresponding to each temperature range may be set. For example, as the temperature range table <NUM> includes coefficient/intercept values corresponding to each temperature range, data reliability and integrity of the nonvolatile memory device <NUM> may be further improved when a temperature compensation value is obtained.

According to some embodiments, the temperature range table <NUM> may store a plurality of coefficients and a plurality of intercepts corresponding to each of a plurality of temperature ranges, and according to some embodiments, the plurality of coefficients and the plurality of intercepts may be a plurality of bit line coefficients and a plurality of bit line intercepts associated with a bit line operation for each of the plurality of temperature ranges. Alternatively, according to some embodiments, a plurality of coefficients and a plurality of intercepts stored may be a plurality of word line coefficients and a plurality of word line intercepts associated with a word line operation for each of the plurality of temperature ranges.

Alternatively, according to some embodiments, the temperature range table <NUM> may set and/or preset a plurality of temperature ranges according to the trend line (e.g., linearity or, even when nonlinear, linearity at each temperature range) of the temperature-temperature code graph of <FIG>, and store a plurality of selection signals corresponding to each temperature range. In these cases, the temperature unit <NUM> may include memories <NUM> and <NUM> that store a plurality of coefficients and a plurality of intercepts, respectively, a coefficient selector <NUM>, and an intercept selector <NUM>. According to the selection signal Sel output from the temperature range table <NUM>, the coefficient selector <NUM> may output any one coefficient from the memory <NUM> and the intercept selector <NUM> may output any one intercept from the memory <NUM>. According to some example embodiments, the plurality of coefficients and the plurality of intercepts may be a plurality of bit line coefficients and a plurality of bit line intercepts associated with a bit line operation for each of the plurality of temperature ranges, or according to another embodiment, the plurality of coefficients and the plurality of intercepts may be a plurality of word line coefficients and a plurality of word line intercepts associated with an operation on a stored word line in each of the plurality of temperature ranges.

The coefficients and intercepts output in each embodiment may be stored (e.g., pre-stored) values by inferring in advance the trend line as in the right graph of <FIG> through machine learning.

<FIG> is a diagram for explaining a three-dimensional V-NAND structure applicable to a nonvolatile memory device according to some example embodiments. The memory cell array <NUM> illustrated in <FIG> may include a plurality of memory blocks, and each of the plurality of memory blocks may be represented by an equivalent circuit as illustrated in <FIG>.

The memory block BLKi shown in <FIG> represents a three-dimensional memory block formed on a substrate in a three-dimensional structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to <FIG>, the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2,. , and MC8, and a ground select transistor GST. Although it is illustrated in <FIG> that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2,. , and MC8, the present disclosure is not limited thereto.

The string select transistor SST may be connected to corresponding string select lines SSL1, SSL2, and SSL3. The plurality of memory cells MC1, MC2,. , and MC8 may be connected respectively to the corresponding gate lines GTL1, GTL2,. , and GTL8. The gate lines GTL1, GTL2,. , and GTL8 may correspond to word lines, and some of the gate lines GTL1, GTL2,. , and GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The string select transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST may be connected to the common source line CSL. The bit lines BL1, BL2, and BL3 may be connected respectively to the corresponding page buffer circuits PB1, PB2, and PB3. Each of the page buffer circuits PB1, PB2, and PB3 may be the page buffer circuit <NUM> of <FIG>. The page buffer circuit will be described in detail with reference to <FIG>.

The word line (e.g., WL1) at the same height may be connected in common, and the ground select lines GSL1, GSL2, and GSL3 and the string select lines SSL1, SSL2, and SSL3 may be separated from each other. Although it is illustrated in <FIG> that the memory block BLK is connected to eight gate lines GTL1, GTL2,. , and GTL8 and three bit lines BL1, BL2, and BL3, but the present disclosure is not limited thereto.

<FIG> is a block diagram illustrating in more detail an example of the page buffer circuit and control logic of <FIG>. The page buffer circuit <NUM> may operate as a write driver and/or a sense amplifier depending on an operation mode. For example, during a write operation, the page buffer circuit <NUM> may transmit a bit line voltage that corresponds to data to be written to the bit lines BL0,. , and BLm-<NUM> of the memory cell array <NUM>. During a read operation, the page buffer circuit <NUM> may sense data stored in a selected memory cell through a bit line. The page buffer circuit <NUM> may latch the sensed data and output the latched data to the outside.

The page buffer circuit <NUM> may include a precharge circuit <NUM> and a shutoff circuit <NUM>. The precharge circuit <NUM> may include at least one transistor controlled by a bit line setup signal BLSETUP, and the shutoff circuit <NUM> may include at least one transistor controlled by a bit line shutoff signal BLSHF.

A control logic <NUM> may output various control signals for controlling the page buffer circuit <NUM> and the address decoder <NUM> to perform a read operation in response to the command CMD. For example, the control logic <NUM> may transmit the bit line setup signal BLSETUP to the precharge circuit <NUM>.

The control logic <NUM> may output a shutoff signal control signal CBLSHF to the bit line shutoff signal generator <NUM> for controlling a bit line shutoff signal generator <NUM>. The control logic <NUM> may control the bit line shutoff signal generator <NUM> to change the bit line shutoff signal BLSHF from a first level (e.g., a precharge voltage V_PRE) to a second level (e.g., a development voltage V_DEV). In these cases, the temperature compensation unit <NUM> may adjust a power supply voltage that generates the bit line shutoff signal BLSHF on the basis of the temperature code TEMP code measured in real-time and output by the digital temperature sensor <NUM> for the nonvolatile memory device <NUM>. For example, the temperature compensation unit <NUM> may generate a power supply voltage OUT of a transistor circuit that generates the bit line shutoff signal BLSHF of the bit line shutoff signal generator <NUM>. For example, when the nonvolatile memory device <NUM> operates at a first temperature range (e.g., hot temperature), the bit line shutoff signal BLSHF generates a first bit line shutoff signal BLSHF1 based on a first power supply voltage OUT1. For example, when the nonvolatile memory device <NUM> operates at a second temperature range (e.g., cold temperature), the bit line shutoff signal BLSHF generates a second bit line shutoff signal BLSHF2 based on a second power supply voltage OUT2. In these cases, the first bit line shutoff signal BLSHF1 at a hot temperature may be adjusted to a logic high level voltage lower than the second bit line shutoff signal BLSHF2 at a cold temperature. For example, assuming that a logic high level voltage of an unadjusted bit line shutoff signal is <NUM> V, the logic high level voltage of the first bit line shutoff signal BLSHF1 may be adjusted to <NUM> V and the logic high level voltage of the second bit line shutoff signal BLSHF2 may be adjusted to <NUM> V.

The address decoder <NUM> may select one of the memory blocks of the memory cell array <NUM> in response to the address ADDR. The address decoder <NUM> may select one of word lines of the selected memory block. The address decoder <NUM> may transmit a word line voltage from the voltage generator to the selected word line WL of the memory block BLKi.

The bit line shutoff signal generator <NUM> may generate the bit line shutoff signal BLSHF based on the shutoff signal control signal CBLSHF received from the control logic <NUM> and output the generated signal to the page buffer circuit <NUM>. The bit line shutoff signal BLSHF may have a voltage level irrespective of a deviation of the power supply voltage provided to the nonvolatile memory device <NUM> from the outside. The bit line shutoff signal BLSHF may be provided to the shutoff circuit <NUM> of the page buffer circuit <NUM>. The bit line shutoff signal generator <NUM> may determine a voltage level of the bit line voltage control signal BLSHF according to the voltages supplied from the voltage generator under the control of the temperature unit <NUM> and output the determined voltage level.

<FIG> is a diagram illustrating one page buffer circuit PB included in the page buffer circuit of <FIG>, and <FIG> is a timing diagram of an operation of a data latch node SO node in the page buffer circuit PB of <FIG>.

Referring to <FIG>, a page buffer circuit PBa <NUM> may include a cache latch unit CLU and a data latch unit DLU. The cache latch unit CLU may include a cache latch <NUM>. For example, the cache latch <NUM> may store data DATA to be stored in a memory cell. Also, the cache latch <NUM> may store data DATA transmitted from a data latch <NUM>. The cache latch <NUM> may be connected to a cache latch node SOC. The cache latch <NUM> may transmit and receive data DATA through the cache latch node SOC. The cache latch unit CLU may include, for example, two or more cache latches.

The cache latch node SOC may be connected to a data latch node SO node through a pass transistor NMP. The pass transistor NMP may be turned on or off according to a pass signal SO_PASS. When the pass transistor NMP is turned on, the data DATA may be transmitted between the cache latch <NUM> and the data latch <NUM>.

The data latch unit DLU may include a data cache. For example, the data cache may store data DATA transmitted from the cache latch <NUM>. Also, the data cache may store data DATA read from a memory cell. The data latch <NUM> may be connected to the data latch node SO node. The data latch <NUM> may transmit and receive data DATA through the data latch node SO node. The data latch unit DLU may include, for example, two or more data latches.

The data latch node SO node may be precharged during a read, write, and/or erase operation of the nonvolatile memory device <NUM>. For example, the data latch node SO node may be precharged according to the internal supply voltage IVC through a setup transistor <NUM>. The setup transistor <NUM> may be turned on or off according to the bit line setup signal BLSETUP. The setup transistor <NUM> may be a P-type transistor. However, the type of the setup transistor <NUM> is not limited thereto. For example, the data latch node SO node may be connected to a bit line BL through a shutoff transistor <NUM>. The shutoff transistor <NUM> may be turned on or off according to the bit line shutoff signal BLSHF. The shutoff transistor <NUM> may gradually decrease the voltage of the data latch node SO node from the precharge voltage to the off level according to the voltage level of the bit line shutoff signal BLSHF and the state of the selected memory cell. The shutoff transistor <NUM> may be an N-type transistor. However, the type of the shutoff transistor <NUM> is not limited thereto.

Referring to <FIG>, the page buffer circuit PB is initialized (PBInit). While the page buffer circuit PB performs an initialization operation, the temperature sensor <NUM> senses the temperature of the memory cell array in real time. At this time, the bit line shutoff signal BLSHF has a logic high level and then transitions to a logic low level after initialization is completed, and the bit line setup signal BLSETUP maintains a logic high level during the initialization operation. In these cases, the bit line shutoff signal BLSHF may maintain a voltage level (e.g., <NUM> V), which is generated according to a preset power supply voltage, during the initialization operation PBInit. A set signal SET_S for moving the data of the memory cell to the data latch maintains a logic low level.

The data latch node SO node may be precharged according to an internal supply voltage IVC in a precharge operation period BLPrecharge. Also, in the precharge operation period BLPrecharge, the bit line setup signal BLSETUP may be at a logic high level, and the bit line shutoff signal BLSHF may be adjusted to a logic high level adjusted based on the measured temperature. For example, the logic high level of the bit line shutoff signal BLSHF may be adjusted from an L1 level to an L2 level according to the temperature state of the memory cell array. The L2 level is a value equal to or less than the L1 level or a value greater than the logic low level. For example, the L1 level may be a voltage level (<NUM> V) generated during the initialization operation, and the L2 level may be a logic high level adjusted to be smaller than the L1 level by means of temperature compensation. For example, at a hot temperature, the L2 level may be adjusted to approximately <NUM> V, and at a cold temperature, the L2 level may be adjusted to approximately <NUM> V. The setup transistor <NUM> may be turned off as the bit line setup signal BLSETUP has a logic high level, and the shutoff transistor <NUM> may be turned on according to bit line shutdown signal BLSHF of the adjusted logic high level. In these cases, the bit line BL may also be precharged together with the data latch node SO node.

The bit line setup signal BLSETUP may be changed to a logic low level in a dump closing period Dump Closing, and changed back to a logic high level in a development period SODev. Accordingly, the setup transistor <NUM> is turned off. In addition, during the development period SODev, the bit line shutoff signal BLSHF is continuously maintained at the logic high level adjusted by temperature compensation, the shutoff transistor <NUM> is turned on, and the voltage level of the data latch node SO node decreases according to the state of the selected memory cell. When a voltage lower than a threshold voltage of the selected memory cell is applied to the selected word line WL (when the selected memory cell is an on cell), the data latch node SO node maintains the initial voltage level intact or the voltage level will drop very slightly. When a voltage higher than the threshold voltage of the selected memory cell is applied to the selected word line WL (when the selected memory cell is an off cell), the voltage level of the data latch node SO node will drop gradually.

When the sensing set signal SET_S is activated in a sensing period SOSense, the changed voltage level of the changed data latch node SO node is sensed and amplified in the page buffer and the relevant data is stored in the data latch <NUM>. Accordingly, the nonvolatile memory device <NUM> may detect the state of the selected memory cell by comparing the voltage level of the data latch node SO node after a specific time with a set reference value Trip level.

In these cases, when the selected memory cell is an off cell, a voltage drop rate of the data latch node SO node varies according to temperature. In general, the voltage drop rate of the data latch node SO node reduces at a cold temperature. Therefore, if the same bit line development time BL Develop Time is applied regardless of the temperature, the probability of an operation error increases. When the selected memory cell is an on cell, the effect of temperature is relatively small because the voltage level of the data latch node SO only needs to be greater than a reference value A. The temperature unit <NUM> may adjust the voltage level of the bit line shutoff signal BLSHF to reduce an operation error when sensing the voltage level at the data latch node SO node. By adjusting the L1 level to the L2 level according to the temperature change, the amount of charge precharged in a data sensing node is adjusted. In this way, even when the operating temperature of the memory cell array <NUM> changes linearly or non-linearly, the data latch node SO node may have a constant voltage drop rate by adjusting the amount of precharged charge according to the temperature.

<FIG> are diagrams for explaining an operation of a memory device according to some example embodiments.

Referring to <FIG> first, a memory cell array <NUM> includes a plurality (e.g., first to fourth) cell strings S1 to S4, and each of the plurality of (e.g., the first to fourth cell strings S1 to S4) cell strings may include a plurality of memory cells MC1 to MC12 e.g., connected between the string select lines SSL1 to SSL4 and the ground select lines GSL1 to GSL4. The memory cell array of <FIG> may be a part of the memory cell array described with reference to <FIG> and <FIG>. Although it is illustrated in <FIG> that each of four cell strings S1 to S4 includes twelve memory cells MC1 to MC12, the present disclosure is not limited thereto.

The nonvolatile memory device <NUM> may select, as a barrier line B_WLs, at least one of a plurality of unselected word lines WL1 to WL11 connected to a second cell string S2 that is a selected cell string. A channel of each of unselected cell strings S1, S3, and S4 may be logically divided into a plurality of channels in at least a partial period of a read operation by the barrier line B_WLs.

The nonvolatile memory device <NUM> may determine a boosting level of a channel included in each of the unselected cell strings S1, S3, and S4 based on a read voltage input to a twelfth word line WL12 that is a selected word line. For example, the memory device may determine that a voltage level having a predetermined (and/or otherwise determined) voltage difference from the read voltage is a boosting level of a channel included in each of the unselected cell strings S1, S3, and S4. The nonvolatile memory device may select at least one of the plurality of unselected word lines WL1 to WL11 as a barrier line B_WLs based on the determined boosting level of the channel of each of the unselected cell strings S1, S3, and S4. For example, in the embodiment illustrated in <FIG>, fourth and fifth word lines WL4 and WL5 may be selected as the barrier lines B_WLs.

The nonvolatile memory device <NUM> may input a turn-on voltage to a selected string selection line SSL2 and a selected ground select line GSL2. The memory device may input a turn-off voltage, for example, a ground voltage, to the barrier lines B_WLs during a first period. Also, the memory device may input a turn-on voltage, for example, the same voltage as a read pass voltage, to the barrier lines B_WLs during a second period. The memory device may selectively input a pre-pulse voltage to the unselected string select lines SSL2 to SSL4 or the unselected ground select lines GSL2-GSL4 during the first period.

Referring to <FIG>, the channels of the unselected string selection lines SSL2 to SSL4 may be electrically divided into a plurality of channels by the barrier lines B_WLs during the first period. Potential of some of the plurality of channels electrically divided by a selectively input pre-pulse voltage may increase to a predetermined boosting level. Thereafter, during the second period, as a read pass voltage is input to the barrier lines B_WLs, the plurality of electrically divided channels may be electrically connected again. The boosting level of the electrically connected channels may be determined according to a boosting level of each of the channels divided by the barrier lines B_WLs, the ratio of the number of word lines corresponding to each of the divided channels, and the like.

Next, referring to <FIG>, a predetermined turn-on voltage (denoted as on) may be input to the second string select line SSL2 that is a selected string select line Sel_SSL and a second ground select line GSL2 that is a selected ground select line Sel_GSL.

A turn-off voltage, for example, a ground voltage, may be input to each of the first, third, and fourth string select lines SSL1, SSL3, and SSL4 that are unselected string select lines Unsel_SSLs. In addition, a pre-pulse voltage may be input to the first, third, and fourth ground select lines GSL1, GSL3, and GSL4 that are unselected ground select lines Unsel_GSLs.

A read pass voltage VPASS may be input to the first to third word lines WL1 to WL3 and the sixth to eleventh word lines WL6 to WL11 that are unselected word lines Unsel_WLs. In addition, a turn-off voltage, for example, a ground voltage, may be input to the fourth and fifth word lines WL4 and WL5, selected as the barrier lines B_WLs, during the first period, and a read pass voltage VPASS may be input to the fourth and fifth word lines WL4 and WL5 during the second period.

In addition, voltages input to the third and sixth word lines WL3 and WL6 that are the word lines BN1_WLs closest to the barrier lines B_WLs may be less than the read pass voltage VPASS in at least a portion of the first period and the second period. Further, voltages input to the second and seventh word lines WL2 and WL7 that are the unselected word lines BN2_WLs second closest to the barrier lines B_WLs may also be less than the read pass voltage VPASS in the sensing period.

In the sensing period during which the read voltage is input to the selected word lines WL4 and WL5 connected to the selected memory cell from data is to be read, a potential of the channel located above the barrier lines with respect to the selected word lines, e.g., the barrier lines, may be adjusted to suppress hot carrier injection or soft erase, thereby improving data reliability.

For example, referring to <FIG>, the nonvolatile memory device <NUM> may use temperature-compensated power supply voltage OUT as a power supply voltage required to generate at least one of the respective operating voltages described with reference to <FIG> and <FIG>, for example, at least one of the read voltage VREAD required to read data stored in the memory cell, the read pass voltage VPASS, the control voltages VCON1 to VCON2, the string select line (SSL) voltage, or the ground select line (GSL) voltage. For example, the temperature-compensated power supply voltage OUT may be the output signal described with reference to <FIG>.

<FIG> is a diagram illustrating a system to which a memory system in accordance with some example embodiments is applied.

A system <NUM> of <FIG> may be basically a mobile system, such as a mobile phone, a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, and/or an Internet-of-Things (IoT) device. However, the system <NUM> is not necessarily limited to a mobile system, and may be a personal computer, a laptop computer, a server, a media player, automotive equipment, such as a navigation system, and/or the like.

Referring to <FIG>, the system <NUM> may include a main processor <NUM>, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may additionally include one or more of an image capturing device <NUM>, a user input device <NUM>, a sensor <NUM>, a communication device <NUM>, a display <NUM>, a speaker <NUM>, a power supplying device <NUM>, and a connecting interface <NUM>.

The main processor <NUM> may control the overall operation of the system <NUM>, more specifically, the operation of other components constituting the system <NUM>. The main processor <NUM> may be implemented as a general-purpose processor, a dedicated processor, an application processor, and/or the like.

The main processor <NUM> may include one or more CPU cores <NUM>, and may further include a controller <NUM> configured to control the memories 1200a and 1200b and/or the storage devices 1300a and1300b. According to some example embodiment, the main processor <NUM> may further include an accelerator block <NUM> that is a dedicated circuit for high-speed data operation, such as artificial intelligence (AI) data operation. The accelerator block <NUM> may include a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), and/or the like, and may be implemented using a separate chip physically independent from other components of the main processor <NUM>.

The memories 1200a and 1200b may be used as main memory devices of the system <NUM> and may each include a nonvolatile memory such as an SRAM and/or a DRAM but may include a nonvolatile memory such as a flash memory, a PRAM, and/or a RRAM. The memories 1200a and 1200b may be implemented within the same package as the main processor <NUM>.

The storage devices 1300a and 1300b may function as nonvolatile storage devices that store data irrespective of whether power is supplied or not, and may have a relatively larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b, respectively, and nonvolatile memory (NVM) storages 1320a and 1320b storing data under the control of the storage controllers 1310a and 1310b, respectively. The nonvolatile memories 1320a and 1320b may include a V-NAND flash memory in a two-dimensional structure or a three-dimensional structure, but may include other types of nonvolatile memory, such as a PRAM and/or a RRAM. The storage devices 1300a and 1300b may be memory systems according to some embodiments described with reference to <FIG>.

The storage devices 1300a and 1300b may be included in the system <NUM> while being physically separated from the main processor <NUM>, or may be implemented within the same package as the main processor <NUM>. In addition, the storage devices 1300a and 1300b may be of a type, such as a solid-state device (SSD) or a memory card, and thus may be detachably coupled with other components of the system <NUM> through an interface, such as the connecting interface <NUM> which will be described below. The storage devices 1300a and 1300b may each be a device to which a standard rule is applied, such as universal flash storage (UFS), embedded multi-media card (eMMC), and/or nonvolatile memory express (NVMe), but the present disclosure is not limited thereto.

The image capturing device <NUM> may capture a still image or a moving picture, and may be, e.g., a camera, a camcorder, a webcam, and/or the like.

The user input device <NUM> may receive various types of data input by a user of the system <NUM>, and may be, e.g., a touch pad, a keypad, a keyboard, a mouse, a microphone, and/or the like.

The sensor <NUM> may sense various types of physical quantities detected from the outside of the system <NUM> and convert the sensed physical quantities into electrical signals. The sensor <NUM> may be, e.g., a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, a gyroscope, and/or the like.

The communication device <NUM> may transmit and receive signals to and from other devices outside the system <NUM> according to various communication protocols. The communication device <NUM> may be implemented by including an antenna, a transceiver, a MODEM, and/or the like.

The display <NUM> and the speaker <NUM> may function as output devices that output visual information and auditory information to the user of the system <NUM>, respectively.

The power supplying device <NUM> may convert power supplied from a power source (such as a battery) (not shown) built into the system <NUM> and/or an external power source and supply the converted power to each component of the system <NUM>.

The connecting interface <NUM> may provide a connection between the system <NUM> and an external device that is connected to the system <NUM> and capable of exchanging data with the system <NUM>.

<FIG> are cross-sectional views of a nonvolatile memory device according to some example embodiments.

A memory device <NUM> of <FIG> and a memory device <NUM> of <FIG> may have a chip to chip (C2C) structure. The C2C structure may be a structure in which a first chip, including a cell area CELL, is fabricated on a first wafer, a second chip, including a peripheral circuit area PERI, is fabricated on a second wafer, different from the first wafer, and then, the first second chip are connected to each other via bonding.

According to some embodiments, the bonding may refer to a method of electrically connecting a bonding metal formed on a topmost metal layer of an upper chip and a bonding metal formed on a topmost metal layer of a lower chip to each other. For example, the bonding metal may be at least one of copper (Cu), aluminum (Al), and/or tungsten (W), and/or the bonding may be Cu-Cu bonding.

Each of the peripheral circuit area PERI and the cell area CELL of the memory devices <NUM> and <NUM> may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit area PERI of <FIG> may include a first substrate <NUM>, an interlayer insulating layer <NUM>, a plurality of circuit devices 1220a, 1220b and 1220c formed on the first substrate <NUM>, first metal layers 1230a, 1230b and 1230c connected to the plurality of circuit devices 1220a, 1220b and 1220c, respectively, and second metal layers 1240a, 1240b and 1240c formed on the first metal layers 1230a, 1230b and 1230c, respectively. The peripheral circuit area PERI of <FIG> may include a first substrate <NUM>, an interlayer insulating layer <NUM>, a plurality of circuit devices 2220a, 2220b and 2220c formed on the first substrate <NUM>, first metal layers 2230a, 2230b and 2230c connected to the plurality of circuit devices 2220a, 2220b and 2220c, respectively, and second metal layers 2240a, 2240b and 2240c formed on the first metal layers 2230a, 2230b and 2230c, respectively. In some embodiments, the first metal layers 1230a, 1230b, 1230c, 2230a, 2230b, and/or 2230c may be formed of tungsten having relatively high resistance and/or the second metal layers 1240a, 1240b, 1240c, 2240a, 2240b, and/or 2240c may be formed of copper having relatively low resistance.

For brevity, only the first metal layers 1230a, 1230b, and 1230c, or 2230a, 2230b, and 2230c, and the second metal layers 1240a, 1240b, and 1240c, or 2240a, 2240b, and 2240c, are illustrated and described, but the example embodiments thereof are not limited thereto. For example, at least one metal layer may be further formed on the second metal layers. The at least one metal layer formed on the second metal layers 1240a, 1240b, and 1240c, or 2240a, 2240b, and 2240c, may be formed of aluminum that has lower resistance than that of copper forming the second metal layers.

The interlayer insulating layer <NUM> or <NUM> may be disposed on the first substrate <NUM> or <NUM> to cover the plurality of circuit devices 220a, 1220b, and 1220c, or 2220a, 2220b, and 2220c, the first metal layers 1230a, 1230b, and 1230c, or 2230a, 2230b, and 2230c, and the second metal layers 1240a, 1240b, and 1240c, or 2240a, 2240b, and 2240c. The interlayer insulating layer <NUM> or <NUM> may include an insulating material such as silicon oxide, silicon nitride, and/or the like.

Lower bonding metals 1127b and 1272b, or 2271b and 2272b, may be formed on the second metal layer 1240b or 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1127b and 1272b, or 2271b and 2272b, of the peripheral circuit area PERI may be electrically connected to upper bonding metals 1371b and 1372b, or 2371b and 2372b, of the cell area CELL via bonding. The lower bonding metals 1127b and 1272b, or 2271b and 2272b, and the upper bonding metals 1371b and 1372b, or 2371b and 2372b, may be formed of aluminum (Al), copper (Cu), tungsten (W), and/or the like.

The cell area CELL may provide at least one memory block. The cell area CELL may include the second substrate <NUM> or <NUM> and a common source line <NUM> or <NUM>. On the second substrate <NUM> or <NUM>, a plurality of word lines (<NUM> to <NUM>; collectively word lines <NUM> in <FIG>, or <NUM> to <NUM>; collectively word lines <NUM> in <FIG>) may be stacked in a direction (e.g., Z direction) perpendicular to an upper surface of the second substrate <NUM> or <NUM>. String select lines and a ground select line may be disposed above and below the word lines <NUM> or <NUM>, respectively. The plurality of word lines <NUM> or <NUM> may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, a channel structure CH may extend in the direction (e.g., the Z direction) perpendicular to the upper surface of the second substrate <NUM> or <NUM> to penetrate through the word lines, the string select lines, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, an embedded insulating layer, and the like, and the channel layer may be electrically connected to a first meal layer 1350c or 2350c and a second metal layer 1360c or 2360c. For example, the first metal layer 1350c or 2350c may be a bit line contact, and the second metal layer 1360c or 2360c may be a bit line. In some embodiments, the bit line 1360c or 2360c may extend in a first direction (Y direction) parallel to the upper surface of the second substrate <NUM> or <NUM>.

In the example embodiments illustrated in <FIG>, an area in which the channel structure CH, the bit line 1360c or 2360c and the like are disposed may be referred to as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line 1360c or 2360c may be electrically connected to the circuit devices 1220c or 2220c that provides a page buffer circuit <NUM> or <NUM> in the peripheral circuit area PERI. For example, the bit line 1360c or 2360c may be connected to upper bonding metals 1371c and 1372c, or 2371c and 2372c, in the peripheral circuit area PERI, the upper bonding metals 1371c and 1372c, or 2371c and 2372c, may be connected to lower bonding metals 1271c and 1272c, or 2271c and 2272c connected to the circuit devices 1220c or 2220c of the page buffer circuit <NUM> or <NUM>.

In the word line bonding area WLBA, the word lines <NUM> or <NUM> may extend in a second direction (e.g., X direction) parallel to the upper surface or a lower surface of the second substrate <NUM> or <NUM> and may be connected to a plurality of cell contact plugs <NUM> or <NUM>. The word lines <NUM> or <NUM> and the cell contact plugs <NUM> or <NUM> may be connected to each other on pads provided by at least some word lines <NUM> or <NUM> extending in the second direction. A first metal layer 1350b or 2350b and a second metal layer 1360b or 2360b may be sequentially connected above or below the cell contact plugs <NUM> or <NUM> connected to the word lines <NUM> or <NUM>. The cell contact plugs <NUM> or <NUM> may be connected to the peripheral circuit area PERI by upper bonding metals 1371b and 1372b, or 2371b and 2372b, of the cell area CELL and bonding metals 1271b and 1272b, or 2271b and 2272b, of the peripheral circuit area PERI in the word line bonding area WLBA.

In the peripheral circuit area PERI, the cell contact plugs <NUM> or <NUM> may be electrically connected to the circuit devices 1220b or 2220b that provides a row decoder <NUM>. In some embodiments, operating voltages of the circuit devices 1220b or 2220b providing a row address decoder may be different from operating voltages of the circuit devices 1220c or 2220c providing the page buffer circuit. For example, the operating voltages of the circuit devices 1220c or 220c providing the page buffer circuit may be greater than the operating voltages of the circuit devices 1220b or 2220b providing the row decoder.

A common source line contact plug <NUM> or <NUM> may be disposed in an external pad bonding area PA. The common source line contact plug <NUM> or <NUM> may be formed of a conductive material, such as a metal, a metal compound, polysilicon, or the like, and may be connected to a common source line <NUM> or <NUM>. A first metal layer 1350a or 2350a and a second metal layer 1360a or 2360a may be sequentially stacked on the common source line contact plug <NUM> or <NUM>. For example, an area in which the common source line contact plug <NUM> or <NUM>, the first metal layer 1350a or 2350b, and the second metal layer 1360a or 2360a are disposed may be defined as the external pad bonding area PA.

Input/output pads <NUM> and <NUM>, or <NUM> and <NUM>, may be disposed in the external pad bonding area PA. Referring to <FIG>, a lower insulating layer <NUM> or <NUM> that covers a lower surface of the first substrate <NUM> or <NUM> may be formed on a lower portion of the first substrate <NUM> or <NUM>, and a first input/output pad <NUM> or <NUM> may be formed on the lower insulating layer <NUM> or <NUM>. The first input/output pad <NUM> or <NUM> may be connected to at least one of the plurality of circuit devices 1220a, 1220b, and 1220c, or 2220a, 2220b, and 2220c, disposed in the peripheral circuit area PERI via the first input/output contact plug <NUM> or <NUM>, and may be separated from the first substrate <NUM> or <NUM> by the lower insulating layer <NUM>. In addition, a side insulating layer may be disposed between the first input/output contact plug <NUM> or <NUM> and the first substrate <NUM> or <NUM> to electrically disconnect the first input/output contact plug <NUM> or <NUM> from the first substrate <NUM> or <NUM>.

An upper insulating layer <NUM> or <NUM> that covers the upper surface of the second substrate <NUM> or <NUM> may be formed on the second substrate <NUM> or <NUM>, and a second input/output pad <NUM> or <NUM> may be disposed on the upper insulating layer <NUM> or <NUM>. The second input/output pad <NUM> or <NUM> may be connected to at least one of the plurality of circuit devices 1220a, 1220b, and 1220c, or 2220a, 2220b, and 2220c, disposed in the peripheral circuit area PERI via the second input/output contact plug <NUM> or <NUM>.

According to some example embodiments, the plurality of circuit devices may include the peripheral circuits described with reference to <FIG>. For example, the temperature unit <NUM>, the address decoder <NUM>, the control logic and voltage generator <NUM>, the page buffer <NUM>, and the input/output circuit <NUM> may be included on the second substrate. According to some embodiments, the temperature sensor <NUM> in the temperature unit <NUM> may be disposed on a lower portion (<FIG>) or on an upper portion (<FIG>) of the cell area and may measure a real-time temperature state of the memory cell array.

According to some embodiments, the second substrate <NUM> or <NUM> and the common source line <NUM> or <NUM> may not be disposed in the region where the second input/output contact plug <NUM> or <NUM> is disposed. Also, the second input/output pads <NUM> or <NUM> may not overlap the word lines <NUM> or <NUM> in a third direction (Z-axis direction). The second input/output contact plug <NUM> of <FIG> may be separated from the second substrate <NUM> in a direction parallel to the upper surface of the second substrate <NUM>, and may be connected to a contact plug 2272a on the first substrate <NUM>, passing through the interlayer insulating layer <NUM> of the cell area CELL.

According to some example embodiments, the first input/output pad <NUM> or <NUM> and the second input/output pad <NUM> or <NUM> may be selectively formed. For example, the memory device <NUM> of <FIG> may include only the first input/output pad <NUM> disposed below the first substrate <NUM>, or may include only the second input/output pad <NUM> disposed above the interlayer insulating layer <NUM>. Alternatively, the memory device <NUM> may include both the first input/output pad <NUM> and the second input/output pad <NUM>. In another example, the memory device <NUM> of <FIG> may include only the first input/output pad <NUM> disposed below the first substrate <NUM>, or may include only the second input/output pad <NUM> disposed above the second substrate <NUM>. Selectively, the memory device <NUM> may include both the first input/output pad <NUM> and the second input/output pad <NUM>.

In the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, a metal pattern of a topmost metal layer may exist as a dummy pattern, or the topmost metal layer may be empty.

In the external pad bonding area PA, the memory device <NUM> of <FIG> may form a lower metal pattern 2273a on the topmost metal layer of the peripheral circuit area PERI in correspondence with an upper metal pattern 2372a formed on the topmost metal layer of the cell area CELL, the lower metal pattern 2273a having the same shape as the upper metal pattern 2372a of the cell area CELL. The lower metal pattern 2273a formed in the topmost metal layer of the peripheral circuit area PERI is not connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, the memory device <NUM> may form an upper metal pattern on the topmost metal layer of the cell area CELL in correspondence with a lower metal pattern formed on the topmost metal layer of the peripheral circuit area PERI, the upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit area PERI.

The lower bonding metals 2271b and 2272b may be formed on the second metal layer <NUM> of the word line bonding area WLBA of <FIG>. In the word line bonding area WLBA, the lower bonding metals 1271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and <NUM> b of the cell area CELL via bonding.

In addition, in the bit line bonding area BLBA of <FIG>, the memory device <NUM> may form an upper metal pattern <NUM> on the topmost metal layer of the cell area CELL in correspondence with a lower metal pattern <NUM> formed on the topmost metal layer of the peripheral circuit area PERI, the upper metal pattern <NUM> having the same shape as the lower metal pattern <NUM> of the peripheral circuit area PERI. No contact may be formed on the upper metal pattern <NUM> formed on the topmost metal layer of the cell area CELL.

Claim 1:
A nonvolatile memory device (<NUM>) comprising:
a memory cell array (<NUM>) including a plurality of memory cells;
an address decoder (<NUM>) configured to decode a row address and a column address from an address signal;
a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array (<NUM>) according to the decoded row address;
a second voltage generator configured to generate a bit line operating voltage of the memory cell array (<NUM>) according to the decoded column address;
a page buffer circuit (<NUM>, <NUM>) configured to activate according to the bit line operating voltage and to store data to be stored in or read from at least one memory cell; and
a temperature unit (<NUM>) configured to determine, from a temperature range table storing a plurality of selection signals mapped to each of a plurality of temperatures ranges, a temperature range for a temperature code according to a real-time temperature of the memory cell array (<NUM>), and to adjust a power supply voltage (OUT) of at least one of the first or second voltage generator based on a selection signal mapped to the determined temperature range characterized in that
the page buffer circuit (<NUM>) includes:
a precharge circuit (<NUM>) comprising at least one transistor controlled by a bit line setup signal output from a control circuit; and
a shutoff circuit (<NUM>) comprising at least one transistor controlled by a bit line shutoff signal,
wherein the second voltage generator includes a bit line shutoff signal generator (<NUM>) configured to adjust a voltage level of the bit line shutoff signal according to an output of the temperature unit.