Patent Description:
Generally, photonic chips have interfaces to permit optical signals to be received from an optical source (e.g., a laser or an optical fiber) or transmitted to an optical fiber. One such method is edge coupling where the optical fiber is coupled to the edge of the photonic chip. As the level of integration, speed of operation, and functionality increase, photonic chips are running out of peripheral bond pad space to allow wire bond based interconnection to the underlying substrate or printed circuit board (PCB). Thus, photonic chips with Through Silicon Vias (TSVs) are highly desirable as they allow for higher density of interconnects and reduce the resistance as well as inductance associated with the wirebond connections.

<CIT> is directed to an optical assembly which allows for passive alignment of the various elements is described. A substrate with a cut out portion and an upper surface is utilized as a mount for an optical array and an imaging assembly. The optical array, which preferably includes a plurality of optical fibers is positioned on V-grooves located on the upper surface. The imaging assembly, which preferably includes a plurality of lenses, such as GRIN lenses, is lowered at least partially into the cut-out portion. The optical fibers are optically coupled with said lenses. A waveguide, having a plurality of waveguide cores within a cladding, may further be optically coupled with the lenses, or alternatively, directly to the optical fibers. An integrated optic chip may also be affixed to the substrate or mounted on the substrate.

<CIT> is directed to a V-groove substrate for using a fiber array block and a method for manufacturing the same are provided to prevent thermal deformation of a silicon substrate by bonding a quartz substrate at the lower part of the silicon substrate. In particular, a silicon substrate forms a plurality of first V-grooves in order to settle an optical fiber at the upper part of the silicon substrate. The silicon substrate and the quartz substrate are bonded through a room temperature bonding method. A silicon substrate comprises a crystal plane. A plurality of second V-grooves are formed on the lower part of the silicon substrate. The quartz substrate is directly bonded to the lower part of the silicon substrate.

There is described herein a method, comprising: disposing epoxy into an epoxy well in a photonic chip; aligning an optical interface of the photonic chip to an optical fiber mounted on a fiber array unit, FAU, wherein the FAU comprises a first layer disposed on a transparent substrate, wherein the first layer comprises an optical window, and wherein the transparent substrate and the optical window are disposed over the epoxy well when the optical fiber is aligned to the optical interface; and curing the epoxy by passing electromagnetic radiation through the transparent substrate and the optical window to reach the epoxy well.

There is also described herein a fiber array unit, FAU, comprising: a transparent substrate; a first layer disposed on the transparent substrate, wherein a material of the transparent substrate is transparent to UV light while a material of the first layer blocks UV light; an optical window in the first layer, wherein at least one side of the optical window is formed by the transparent substrate; a groove formed in the first layer; and an optical fiber disposed in the groove, wherein a first portion of the transparent substrate extends beyond a termination end of the optical fiber, wherein the optical window is disposed on the first portion of the transparent substrate.

The claimed invention relates to a method that includes disposing epoxy into an epoxy well in a photonic chip and aligning an optical interface of the photonic chip to an optical fiber mounted on a fiber array unit (FAU) where the FAU comprises a first layer disposed on a transparent substrate, wherein a material of the transparent substrate is transparent to UV light while a material of the first layer blocks UV light, wherein the first layer comprises an optical window, and where the transparent substrate and the optical window are disposed over the epoxy well when the optical fiber is aligned to the optical interface. The method includes curing the epoxy by passing UV electromagnetic radiation through the transparent substrate and the optical window to reach the epoxy well.

An embodiment presented herein is an optical system that includes a photonic chip with a waveguide, an optical interface optically coupled to the waveguide, and an epoxy well. The optical system also includes a FAU coupled with the photonic chip using cured epoxy in the epoxy well. The FAU includes a transparent substrate, a first layer disposed on the transparent substrate, wherein a material of the transparent substrate is transparent to UV light while a material of the first layer blocks UV light, the first layer comprising an optical window and a groove, an optical fiber disposed in the groove and aligned to the optical interface in the photonic chip, and a lid where the optical fiber is disposed between the lid and the transparent substrate. Moreover, the transparent substrate and the optical window are disposed over the epoxy well.

Another aspect of the claimed invention relates to a FAU that includes a transparent substrate, a first layer disposed on the transparent substrate, where a material of the transparent substrate is transparent to UV light while a material of the first layer blocks UV light, an optical window in the first layer where at least one side of the optical window is formed by the transparent substrate, a groove formed in the first layer, and an optical fiber disposed in the groove where a first portion of the transparent substrate extends beyond a termination end of the optical fiber, and where the optical window is disposed on the first portion of the transparent substrate.

Generally, photonic chips have an optical interface to transmit optical signals to an optical fiber, or to receive optical signals from an optical source such as a laser or optical fiber. Some optical interfaces include edge couplers disposed at the sides of the photonic chip, which makes edge couplers easier to manufacturer and improve optical coupling compared to other solutions. However, photonic chips with TSVs have several additional constraints on edge coupling. Wafers with TSVs are thinner (typically in the range of <NUM> to <NUM>). Hence, even though shallow trenches in a silicon substrate are possible, deep trenches (typically created by Deep Reactive Ion Etching (DRIE)) cannot be created to accommodate a lens or fiber placement for an edge coupler. In addition, TSVs constrain the overall optical packaging or assembly since photonic chips with TSVs are typically attached to a glass or silicon interposer or a ceramic or an organic substrate using conventional solder reflow or thermal compression bonding processes. As such, conventional edge coupling techniques cannot be used with a photonic chip that has TSVs.

In order for optical components (e.g., photonic chip, optical fiber, laser, etc.) to function properly, the optical components need to be aligned with each other. Optical alignment is the process of aligning optical elements with one another to maximize the accuracy and performance of transmitted signals. Active alignment requires a person to view and align the different components based on feedback when transmitting optical signals between the components, which increases the cost of manufacturing photonics chips. Passive alignment (also referred to as mechanical alignment) relies on strict manufacturing tolerance of components and optical based initial placement to ensure the components are aligned properly when the components are placed at their respective position without the need for aligning the components based on feedback - i.e., without transmitting optical signals between the components.

Embodiments herein describe a fiber array unit (FAU) configured to align a plurality of optical fibers to a photonic chip. The FAU has a plurality of grooves for receiving the plurality of optical fibers. In one embodiment, the FAU includes at least one alignment feature that correspond to an alignment feature in the photonic chip to achieve passive alignment. Epoxy is used to bond the FAU to the photonic chip when the optical fibers attached to the FAU are aligned with an optical interface in the photonic chip. However, curing the epoxy between the FAU and the photonic chip is difficult. As such, according to the claimed invention, the FAU includes one or more optical windows etched into a non-transparent layer (e.g., a silicon layer or first layer) that overlap epoxy wells in the photonic chip. Moreover, the FAU includes a transparent substrate (e.g., silicon dioxide) which permits UV light to pass therethrough. As such, during curing, UV light passes through the transparent substrate and through the optical windows in the non-transparent layer to cure the epoxy disposed between the FAU and the photonic chip.

<FIG> illustrates an optical system <NUM>, according to one embodiment herein. As shown, the optical system <NUM> has a substrate <NUM> and an interposer layer <NUM> connected via solder <NUM>. The interposer layer <NUM> is a layer with through electrical connections and routing layers on Silicon, Glass, Ceramic or organic material. The interposer layer <NUM> is coupled to a redistribution layer (RDL) <NUM>. Coupled to the RDL <NUM> are an application specific integrated circuit (ASIC) <NUM>, a high bandwidth memory (HBM) <NUM>, and a photonic chip <NUM> which includes a semiconductor material. The RDL <NUM> allows electrical connections to be made between electrical components coupled to it. Stated differently, the RDL <NUM> allows components (e.g., the ASIC <NUM>, the HBM <NUM>, the photonic chip <NUM>, etc.) to communicate electrically by minimizing external electrical connections. As shown, the interposer layer <NUM> has a plurality of Through Silicon Vias (TSVs) <NUM>, which couple the RDL <NUM> to the semiconductor substrate <NUM>. While the interposer layer <NUM> is shown with TSVs, the interposer layer <NUM> may be made of glass in which case the interposer layer <NUM> would be a through via or a through oxide via. In one embodiment, the TSVs <NUM> provide power to the RDL <NUM> which in turn routes the power to the ASIC <NUM>, the HBM <NUM>, and the photonic chip <NUM>.

As shown, the photonic chip <NUM> is coupled to a driver <NUM> and a FAU <NUM>. The driver <NUM> sends/receives signals to/from an optical fiber <NUM> via the FAU <NUM> and the photonic chip <NUM>. In another embodiment, the driver <NUM> is a transimpedance amplifier that amplifies the electrical signals generated by an optical detector (not shown) in the photonic chip <NUM> in response to photonic signals received from the optical fiber <NUM> mounted on the FAU <NUM>. As shown, the photonic chip <NUM> has a plurality of TSVs <NUM>. In one embodiment, the photonic chip <NUM> provides power from the Printed Circuit Board (PCB) or organic/ceramic substrate through the interposer layer <NUM> to the driver <NUM> via one of the TSVs <NUM>.

In one embodiment, the ASIC <NUM> and the driver <NUM> communicate via the TSVs <NUM> in the photonic chip <NUM>, as well as the interposer layer <NUM> and the RDL <NUM>. In one embodiment, the ASIC <NUM> includes logic for providing data to and from the photonic chip <NUM> from outside the system <NUM>. For example, the ASIC <NUM> can send signals to the driver <NUM> such that the driver <NUM> sends a signal to a modulator (not shown) in the photonic chip <NUM>, and the modulator encodes the data from the driver <NUM> onto an optical signal. In one embodiment, at high speed operation, the driver <NUM> is placed directly onto the photonic chip <NUM> to provide electrical connections that are as short as possible. In one embodiment, the optical detector in the photonic chip <NUM> outputs voltages based on a received optical signal to the driver <NUM>. The driver <NUM> in turn provides data to the ASIC <NUM> based on the received signal. In one embodiment, the HBM <NUM> stores settings for the ASIC <NUM> which dictate how the ASIC <NUM> communicates between the driver <NUM> and external devices and systems. In another embodiment, the HBM <NUM> stores settings for how the photonic chip <NUM> receives and transmits optical signals.

In one embodiment, the photonic chip <NUM> is a photonics transceiver that receives and transmits optical signals. For example, an optical signal may be transmitted along the optical fiber <NUM> where the photonic chip <NUM> receives the optical signal. As another example, the photonic chip <NUM> transmits an optical signal to the optical fiber <NUM>. In this manner, the photonic chip <NUM> can communicate using the optical fiber <NUM> to an external system. In one embodiment, the photonic chip <NUM> is an optical modulator that is controlled by electrical data signals received from the driver <NUM>. In another embodiment, the photonic chip <NUM> is an optical detector that transmits electrical signals to the ASIC <NUM> via the driver <NUM>. Specifically, the TSVs <NUM> of the photonic chip <NUM> and traces on the PCB or organic/ceramic substrate have an electrical signal that corresponds to an optical signal detected by the photonic chip <NUM>. In this manner, the optical system <NUM> may send and/or receive optical signals.

<FIG> illustrates alignment features for coupling the photonic chip <NUM> to a FAU, according to one embodiment disclosed herein. As shown, the features are formed in a top surface <NUM> of the photonic chip <NUM> on which the driver <NUM> is mounted. In this embodiment, the features include epoxy wells <NUM>, alignment slots <NUM>, and an optical interface <NUM>. The epoxy wells <NUM> may include etched portions of the top surface <NUM> that have been recessed for receiving epoxy for coupling the photonic chip <NUM> to the FAU (not shown). In this example, the two epoxy wells <NUM> furthest from the optical interface <NUM> include raised features (e.g., islands). The raised features may have the same height as the other portions of the top surface <NUM> of the photonic chip <NUM>. However, the area of the epoxy wells <NUM> surrounding the raised features is recessed relative to the top surface <NUM> to form a containment area for the epoxy.

The photonic chip <NUM> also includes seven epoxy wells <NUM> disposed near the optical interface <NUM> and between the alignment slots <NUM>. Although these epoxy wells <NUM> do not have raised features in <FIG>, in other embodiments, there may be raised features within these epoxy wells <NUM>. In one embodiment, all the epoxy wells <NUM> on the photonic chip <NUM> have the same depth and are formed during the same etching process.

The alignment slots <NUM> are designed to receive corresponding alignment features in the FAU. The arrangement of the slots <NUM> in the photonic chip <NUM> may enable passive alignment in at least one alignment direction. For example, by aligning the alignment features in the FAU to the alignment slots <NUM>, the optical fibers mounted to the FAU are aligned with the optical interface <NUM> in at least one of the X, Y, or Z directions such that optical signals can be transferred between the photonic chip <NUM> and the optical fibers via the optical interface <NUM>. The alignment slots <NUM> may have the same depth as the epoxy wells <NUM> or a different depth.

In one embodiment, the photonic chip <NUM> includes one or more TSVs, and thus, its thickness may be limited as explained above. However, the embodiments herein are not limited to edge coupling an FAU to a photonic chip <NUM> with TSVs but can be used in a photonic chip that does not includes TSVs.

<FIG> illustrates coupling the FAU <NUM> to the photonic chip <NUM>, according to one embodiment disclosed herein. As shown, the FAU <NUM> includes the optical fibers <NUM> which are mounted between a transparent substrate <NUM> and a lid <NUM>. The transparent substrate <NUM> is shown in ghosted lines so that the underlying details of the FAU <NUM> and the photonic chip <NUM> can be seen. As used herein, "transparent" when used in context of the substrate <NUM> refers to a material that permits UV electromagnetic radiation that can cure epoxy to pass therethrough. Put differently, the transparent substrate <NUM> can be formed from any material which is transmissive (or transparent) to UV radiation used to cure the epoxy disposed in the epoxy wells <NUM>. Suitable materials for the transparent <NUM> could be glass or silicon dioxide. For example, the transparent substrate <NUM> may be formed from a silicon-on-insulator (SOI) structure where the base crystalline substrate has been removed leaving only a thin silicon layer disposed on top of a thicker silicon oxide layer. As discussed below, optical windows can be formed in the thin silicon layer so that UV light can pass through an upper surface <NUM> of the silicon dioxide layer (e.g., the transparent substrate <NUM>) and through the optical windows to reach the epoxy wells <NUM>, thereby curing the epoxy. In another embodiment, the substrate <NUM> may be a transparent molded material.

In one embodiment, the optical fibers <NUM> are aligned to respective waveguide adapters (not shown here) which are between the alignment slots <NUM> and the epoxy wells <NUM> at the optical interface <NUM>. That is, the waveguide adapters can be exposed at the optical interface <NUM> (or recessed slightly away from the optical interface <NUM> - e.g., a few microns) so that light can be transferred between the optical fibers <NUM> and waveguides in the photonic chip <NUM>. In one embodiment, the FAU <NUM> is passively aligned to the photonic chip <NUM> using the alignments slots <NUM> and precise fabrication techniques so that active alignment is not needed.

<FIG> illustrates the FAU <NUM> with optical windows <NUM>, according to one embodiment disclosed herein. The FAU <NUM> is flipped relative to the state of the FAU <NUM> as shown in <FIG>. Moreover, the lid <NUM> has been omitted so that the underlying features can be seen.

The FAU <NUM> includes the transparent substrate <NUM> as well as a thin silicon layer <NUM> disposed on the transparent substrate <NUM>. Although crystalline silicon is described, the embodiments herein are not limited to such. For example, using silicon for the layer <NUM> may be preferred when the transparent substrate <NUM> is silicon dioxide since a SOI structure can be used to form the substrate <NUM> and the silicon layer <NUM>. However, if other materials are used for the transparent substrate <NUM>, then the layer <NUM> may be formed from a different material than silicon.

Generally, crystalline silicon in the silicon layer <NUM> is not transmissive to radiation that can be used to cure epoxy (e.g., UV light). As such, the silicon layer <NUM> is etched to include optical windows <NUM> where the silicon has been removed to expose the underlying transparent substrate <NUM>. As such, the optical windows <NUM> define areas in the silicon layer <NUM> where UV light transmitted through the transparent substrate <NUM> can pass through the silicon layer <NUM> and reach epoxy wells in the photonic chip as shown in <FIG>.

The optical windows <NUM> are disposed on a portion of the transparent substrate <NUM> that extends beyond a termination end of the optical fibers <NUM>. That is, the optical fibers <NUM> stop at a fiber stop <NUM> but a portion of the silicon layer <NUM> (which includes the optical windows <NUM> and the alignment features <NUM>) extends past the optical fibers <NUM>. This portion of the silicon layer <NUM> is used to bond the FAU <NUM> to the top surface of the photonic chip.

In addition to forming the optical windows <NUM>, the silicon layer <NUM> is etched to form grooves in which the optical fibers <NUM> are disposed. That is, when forming the FAU <NUM>, the silicon in these areas is removed to form grooves for securing and aligning the optical fibers <NUM>. The depth of the silicon layer <NUM> can be controlled such that the cores of the optical fibers <NUM> (e.g., the center portion of the optical fibers <NUM> which propagate the optical signals) are above the silicon layer <NUM> so that the cores can interface with the optical interface in the photonic chip. In one embodiment, the diameter of the fibers <NUM> may be around <NUM> microns thick (which include the core as well as the surrounding cladding). As such, in one embodiment, the thickness of the silicon layer <NUM> is less than <NUM> microns to ensure the core is above the silicon layer <NUM> but this thickness could change depending on the desired position of the fiber core relative to the substrate or the silicon layer <NUM>. The thickness of the core and cladding may change depending on whether the optical fibers <NUM> are single-mode fibers or multi-mode fibers which may affect the thickness of the silicon layer <NUM>.

The silicon layer <NUM> also includes the fiber stop <NUM>. When placing the optical fibers <NUM> in the grooves, the fiber stop <NUM> serves as an alignment feature. That is, after placing the fiber <NUM> in a groove, the technician (or automated machine) can slide the fiber <NUM> until it contacts the fiber stop <NUM>. In this manner, the fiber stop <NUM> can align the fibers <NUM> along the direction in which they extend, as well as ensure the fibers <NUM> terminate on the same plane. Thus, using the grooves and the fiber stop <NUM>, the technician can passively align the optical fibers <NUM> to the FAU <NUM>.

As shown, the fiber stop <NUM> has a smaller thickness than the other portions of the silicon layer <NUM>. That is, the fiber stop <NUM> may be etched to remove some of the silicon. This may be desired so that when the fibers <NUM> are moved to butt up against the fiber stop <NUM>, the stop <NUM> does not damage the core of the fibers <NUM>. That is, although the thickness of the silicon layer <NUM> is controlled to be below the cores in the fiber <NUM>, the thickness of the fiber stop <NUM> is further reduced so that the stop <NUM> is farther from the core, and thus, is less likely to damage the cores when aligning the fibers <NUM> in the FAU <NUM>. However, this is not a requirement and in other examples the fiber stop <NUM> may have the same thickness as the other portions of silicon layer <NUM>.

Alignment features <NUM> are disposed on the silicon layer <NUM> which are arranged on the FAU <NUM> to align with the alignment slots <NUM> shown in <FIG>. When the alignment features <NUM> contact the ends of the alignment slots <NUM> furthest from the optical interface <NUM>, this passively aligns the optical fibers <NUM> to the optical interface <NUM>. The alignment features <NUM> may be formed from any material such as a dielectric, metal, and the like. Although circles are shown, the alignment features <NUM> can be other shapes such as rectangles or triangles which passively align the FAU <NUM> to the photonic chip. Further, in another embodiment, the roles may be reversed where the alignment slots <NUM> are formed in the silicon layer <NUM> of the FAU <NUM> while the alignment features <NUM> are disposed on the top surface <NUM> of the photonic chip <NUM>.

One advantage of the FAU <NUM> is that the optical fibers <NUM> can be directly interfaced with the optical interface in the photonic chip. That is, some FAUs include internal waveguides (e.g., formed in a silicon substrate) which are optically coupled to the optical fibers mounted on the FAU. These internal waveguides are then routed through the FAU to an output interface where they are aligned to the optical interface in the photonic chip. The FAU <NUM>, however, avoids having intermediary waveguides for optically coupling the optical fibers <NUM> to the photonic chip. This reduces the complexity of the FAU <NUM> and also reduces the number of alignments that need to be performed. Instead of aligning (and epoxying) the optical fibers to internal waveguides in the FAU and then aligning (and epoxying) the internal waveguides to the optical interface in the photonic chip, the FAU <NUM> aligns the optical fibers <NUM> directly to the photonic chip.

<FIG> illustrate forming optical windows in the silicon layer <NUM> of the FAU <NUM>, according to embodiments disclosed herein. The left side of <FIG> illustrates the cross section A-A shown in <FIG> while the right side of <FIG> illustrates the cross section B-B in <FIG>. Moreover, <FIG> illustrates a time before the optical windows and the grooves have been formed in the FAU <NUM>. For example, the silicon layer <NUM> may be a continuous sheet of silicon disposed on the transparent substrate <NUM>.

<FIG> illustrates etching portions of the silicon layer <NUM> to form the optical windows <NUM> as well as a U-groove <NUM> in which an optical fiber is disposed. In one embodiment, the optical windows <NUM> and the U-groove <NUM> are formed in the same etching step or in separate etching steps. In one embodiment, DRIE is used to remove the silicon material to form the optical windows <NUM> and the U-groove <NUM>. As mentioned above, the thickness or height of the silicon layer <NUM> is controlled such that when the optical fiber is placed in the U-groove, the core of the fiber is above the silicon layer <NUM>.

In one embodiment, the material of the transparent substrate <NUM> forms an etch stop. That is, the etching technique used to etch the silicon in the silicon layer <NUM> may not remove the material of the transparent substrate <NUM> (e.g., the etching technique is selective). In this way, the height of the U-grooves can be tightly controlled to match the height of the silicon layer <NUM>.

<FIG> illustrates the FAU <NUM> with optical windows <NUM>, according to one embodiment disclosed herein. The FAU <NUM> in <FIG> has similar features as the FAU <NUM> in <FIG> such as the optical windows <NUM> and grooves for holding the optical fibers (e.g., V-grooves <NUM>) except these features have different shapes and can be formed using different fabrication techniques. For example, instead of using DRIE, the optical windows <NUM> and the V-grooves <NUM> are formed in a silicon layer <NUM> using an anisotropic etch such as a potassium hydroxide (KOH) etch. However, a fiber stop <NUM> may be formed using an isotropic etch such DRIE. That is, instead of using a KOH etch which forms slanted angles with the underlying substrate <NUM>, DRIE can be used to form the fiber stop <NUM> with a surface that is perpendicular to the transparent substrate <NUM> which may better align the termination ends of the optical fibers <NUM> relative to using a surface that is slanted.

<FIG> illustrate forming optical windows in a silicon layer of the FAU <NUM>, according to embodiments disclosed herein. The left side of <FIG> illustrates the cross section C-C shown in <FIG> while the right side of <FIG> illustrates the cross section D-D in <FIG>. Moreover, <FIG> illustrates a time before the optical windows and the grooves have been formed in the FAU <NUM>. For example, the silicon layer <NUM> may be a continuous sheet of silicon disposed on the transparent substrate <NUM>.

<FIG> illustrates etching portions of the silicon layer <NUM> to form the optical window <NUM> as well as the V-groove <NUM> in which an optical fiber is disposed. In one embodiment, the optical window <NUM> and the V-groove <NUM> are formed in the same anisotropic etching step or in separate etching steps. In one embodiment, a KOH etch is used to remove the silicon material to form the optical window <NUM> and the V-groove <NUM> which results in slanted sides. The angle of the slanted sides can vary depending on the crystalline orientation of the silicon layer <NUM>. One advantage of using an anisotropic etch in contrast to an isotropic etch as shown in <FIG> is that the height of the silicon layer <NUM> does not need to be controlled to ensure the proper depth of the V-grooves <NUM> for holding the optical fibers. Instead, a width of an aperture in a mask on the silicon layer <NUM> used during the KOH etch determines the depth of the V-grooves. Put differently, because a KOH etch has a known etch angle depending on the crystalline orientation, adjusting the width of the top opening of the V-groove <NUM> determines the depth of the V-groove. Because the KOH etch stops once the slanted sides of the V-groove <NUM> intersect, the thickness of the silicon layer <NUM> can be any thickness that is equal to, or greater than, the desired depth of the V-groove <NUM>.

As shown, the width of the optical window <NUM> is much larger than the width of the V-groove <NUM>, and as a result, the KOH etch exposes the underlying transparent substrate <NUM>. This provides substantial flexibility in regards to the thickness of the silicon layer <NUM> since it can be any value greater than the depth of the V-groove <NUM> so long as the etch can expose the underlying transparent substrate when forming the optical window <NUM>.

<FIG> illustrates the FAU <NUM> with optical windows, according to one embodiment disclosed herein. The FAU <NUM> in <FIG> is the same as the FAU <NUM> shown in <FIG> except that the lid <NUM> has been added. The lid <NUM> may be any suitable substrate which can be used to hold the optical fibers <NUM> in the grooves formed in the silicon layer <NUM>. For example, after aligning the optical fibers <NUM> in the grooves, epoxy may be deposited onto the fibers <NUM> and the lid <NUM> can be pressed down until it contacts the tops of the fibers <NUM>. Once cured, the lid <NUM> and the epoxy hold the optical fibers <NUM> in the grooves in the silicon layer <NUM>.

The lid <NUM> is not limited to any particular material. For example, the lid may be a transparent or non-transparent material, although it may be desirable to use a transparent material (e.g., glass) so that UV light can pass through the lid <NUM> to cure the epoxy used to hold the fibers <NUM> in the grooves.

<FIG> illustrate coupling an optical fiber in the FAU <NUM> to the photonic chip <NUM>, according to embodiments disclosed herein. <FIG> illustrates a view of the photonic chip <NUM> that includes an interlayer dielectric (ILD) layer <NUM> disposed on a substrate <NUM>. In one embodiment, the thickness or height of the ILD layer <NUM> is less than <NUM> microns.

The ILD layer <NUM> includes a waveguide adapter <NUM> that is optically coupled to a waveguide <NUM>. Although the waveguide <NUM> is shown as being in the ILD layer <NUM> (e.g., a second layer), in other embodiments the waveguide <NUM> may be formed in the underlying substrate <NUM>. In one embodiment, the waveguide adapter <NUM> changes the size of the optical mode of the optical signal passing therethrough to better match the mode size of the optical signal when traveling through the core of the optical fiber <NUM> versus the mode size when the optical signal travels through the waveguide <NUM>. For example, the waveguide <NUM> may be a submicron waveguide (which has a width and thickness that is less than one micron) while the core of the fiber <NUM> may be <NUM>-<NUM> microns. As such, the mode size of an optical signal in the core of the optical fiber <NUM> may be an order of magnitude larger than the mode size of an optical signal in the waveguide <NUM>. As such, directly interfacing the core of the optical fiber <NUM> with the waveguide <NUM> (without using the waveguide adapter <NUM>) may incur substantial optical losses when transferring optical signals between the photonic chip <NUM> and the optical fiber <NUM>. The waveguide adapter <NUM> converts or changes the mode size thereby providing a more efficient optical connection.

In one embodiment, the waveguide adapter <NUM> includes a plurality of prongs which have widths that vary along the length of the waveguide adapter <NUM> to change the mode size of the optical signal. For example, as the optical signal travels from the waveguide <NUM> to the optical interface <NUM>, the optical signal may propagate on the plurality of prongs which increases the mode size to better match the size of the core in the optical fiber. When receiving an optical signal from the optical fiber <NUM>, the shape of the prongs in the waveguide adapter <NUM> may constrain the optical signal into a single prong thereby reducing the mode size to better match the cross sectional area of the waveguide <NUM>. However, the embodiments herein are not limited to any particular structure of the waveguide adapter <NUM> and can be used with known or future structures which permit efficient transmission of optical signals between a waveguide with different dimensions than the core of the optical fiber <NUM>.

Moreover, the optical interface <NUM> has a slight angle relative to the substrate <NUM>. For example, the optical interface <NUM> may be etched at an <NUM> degree angle which may improve the efficiency at which optical signals are transmitted between the optical interface <NUM> and the optical fiber <NUM>.

The dotted line <NUM> indicates a plane along which the photonic chip <NUM> is diced or sawed to remove a portion of the substrate <NUM>. Removing some of the substrate <NUM> permits the optical fibers <NUM> in the FAU to be moved closer to the optical interface <NUM> and the waveguide adapter <NUM> thereby lower the optical loss when transferring the signals between the waveguide <NUM> in the photonic chip <NUM> and the optical fiber <NUM>. In one embodiment, the tolerance of the dice or sawing process may be +/- <NUM> microns. Thus, to ensure the waveguide adapter <NUM> is not cut, the line <NUM> may be at least <NUM> microns away from the closest point in the optical interface <NUM>. This avoids chipping or damaging the portion of the waveguide adapter <NUM> at the optical interface <NUM> and also permits the optical interface to be angled as shown. However, this means that the distance between the optical interface <NUM> and the optical fiber could be as much as <NUM> microns.

<FIG> illustrates bringing the optical fiber <NUM> in the FAU into contact with the diced or sawed edge of the substrate <NUM>. In one embodiment, an index matching epoxy is applied to the optical interface <NUM> before moving the optical fiber <NUM> into contact with the substrate <NUM> which can improve the efficiency of the optical connection between the optical interface <NUM> and the optical fiber <NUM> relative to using air.

<FIG> illustrate coupling the optical fiber <NUM> in a FAU to the photonic chip <NUM>, according to embodiments disclosed herein. <FIG> illustrates a view of the photonic chip <NUM> that includes the ILD layer <NUM> disposed on the substrate <NUM>. In one embodiment, the thickness or height of the ILD layer <NUM> is less than <NUM> microns.

Unlike in <FIG>, a dotted line <NUM> in <FIG> illustrates that the photonic chip <NUM> is diced or sawed through the waveguide adapter <NUM>. That is, in <FIG>, the chip <NUM> was diced to avoid cutting or damaging the waveguide adapter <NUM> and the optical interface <NUM>. Here, the dotted line <NUM> extends through the waveguide adapter <NUM> which, given the tolerances of the dicing technique, can result in cutting at least a portion of the optical interface <NUM> and the waveguide adapter <NUM>. As mentioned above, doing so may damage the structures in the waveguide adapter <NUM> (thereby reducing the efficiency of the optical connection) but this also means the optical fiber <NUM> can be brought closer to the optical interface <NUM> and the waveguide adapter <NUM> (thereby improving the optical efficiency).

<FIG> illustrates butt coupling the optical fiber <NUM> to the optical interface <NUM> and a cut waveguide adapter <NUM>. When compared to <FIG>, the optical fiber <NUM> is closer to the waveguide adapter <NUM> and the optical interface <NUM>, but the dicing step may have damaged the waveguide adapter <NUM>. Moreover, the optical interface <NUM> is perpendicular to the substrate <NUM> rather than having the slight slant as shown in <FIG>. Thus, there are tradeoffs between using the techniques in <FIG> versus the techniques in <FIG>. Like in <FIG>, an index matching epoxy may be disposed between the optical interface <NUM> and the optical fiber <NUM>.

<FIG> illustrates an optical system <NUM> that includes the FAU <NUM> coupled to the photonic chip <NUM>, according to one embodiment disclosed herein. As shown, the FAU <NUM> is flipped relative to the view shown in <FIG> and placed on the photonic chip <NUM>. Moreover, the alignment feature <NUM> is urged into one of the alignment slots (not labeled) in the photonic chip <NUM> in order to align the optical fibers <NUM> to the photonic chip <NUM>. That is, the alignment features <NUM> are locked into the alignment slots which can passively align the optical fibers <NUM> to the photonic chip <NUM> in multiple directions.

The silicon layer <NUM> is etched to form multiple optical windows <NUM> which are disposed over at least one epoxy wells (not labeled) in the photonic chip <NUM>. As a result, radiation emitted through the upper surface <NUM> of the transparent substrate <NUM> can pass through the optical windows <NUM> and cure the epoxy in the underlying epoxy wells.

In this embodiment, the optical windows <NUM> extend in a direction that is perpendicular to the longer sides of the rectangular epoxy wells <NUM> shown in <FIG>. However, in other embodiments, the optical windows <NUM> can extend in a direction that is parallel to the longer sides of the epoxy wells <NUM>. Moreover, the silicon sides in the silicon layer <NUM> that define the optical windows <NUM> may be arranged to contact the raised features or islands within the two epoxy wells <NUM> in <FIG> that are furthest from the optical interface <NUM>. In one embodiment, the silicon sides of the optical windows <NUM> form a zero bond line thickness with the raised features in the epoxy wells <NUM>. That is, only a very thin (essentially zero) layer of epoxy remains between the silicon sides of the optical windows <NUM> and the raised features after applying a force down onto the upper surface <NUM> of the transparent substrate <NUM>. The zero bond line thickness can align the optical fibers <NUM> to the photonic chip <NUM> in the vertical (e.g., Y direction) while locking the alignment feature <NUM> in the alignment slot can align the optical fibers to the photonic chip <NUM> in the X and Z directions thereby achieving passive alignment. The epoxy in the recessed portions of the epoxy wells also contact structures in the silicon layer <NUM> to provide a secure bond between the FAU <NUM> and the photonic chip <NUM>.

<FIG> illustrates a close up view of a portion <NUM> of <FIG>, according to one embodiment disclosed herein. The portion <NUM> illustrates in greater detail the alignment between the optical fibers <NUM> and the optical interface <NUM> in the ILD layer <NUM> of the photonic chip <NUM>. As shown, the portion <NUM> includes the transparent substrate <NUM> on the top with the silicon layer <NUM> arranged underneath. The dotted lines illustrate that the optical fiber <NUM> is recessed in the silicon layer <NUM> and contacts the transparent substrate <NUM>. That is, the optical fiber <NUM> may be disposed in a U-groove formed in the silicon layer <NUM> as shown in <FIG> and <FIG>.

The core of the optical fiber <NUM> is aligned with the optical interface <NUM> in the ILD layer <NUM>. As mentioned above, the ILD layer <NUM> may include a waveguide adapter which serves as an intermediary between the optical fiber <NUM> and a submicron waveguide in the ILD layer <NUM>. In one embodiment, the thickness of the ILD layer <NUM> is controlled so that when the silicon layer <NUM> is brought into contact with the ILD layer <NUM>, the core of the optical fiber <NUM> is aligned in the Y direction with a waveguide adapter in the ILD layer <NUM>. Moreover, <FIG> illustrates that the optical fiber <NUM> can be aligned to the optical interface <NUM> to directly optically connect the fiber <NUM> with the interface <NUM> without using any kind of intermediate optical device such as a ball lens or a silicon micro lens (although index matched epoxy may be disposed between the fiber <NUM> and the interface <NUM>).

In one embodiment, the epoxy wells and alignment slots shown in <FIG> extend through the ILD layer <NUM>, although at different location in the ILD layer <NUM> than the side view shown here. However, the epoxy wells and alignment slots may continue to extend through the underlying substrate in the photonic chip <NUM>. For example, the ILD layer <NUM> may be <NUM> microns thick but the epoxy wells and alignment slots may have a depth of <NUM> microns.

In one embodiment, the surface of the ILD layer <NUM> facing the silicon layer <NUM> may form a zero bond line thickness when epoxying the FAU to the photonic chip. Moreover, although the optical window <NUM> is shown as being hollow (e.g., an air gap), in one embodiment, epoxy from bonding the silicon layer <NUM> to the epoxy wells may extend up into the optical window <NUM>.

<FIG> is a flowchart of a method <NUM> for transmitting radiation through an FAU to cure an epoxy bond, according to the claimed invention. At block <NUM>, a technician dispenses epoxy into an epoxy well in a photonic chip - e.g., the epoxy wells <NUM> shown in <FIG>. In one embodiment, the photonic chip includes multiple epoxy wells where some of the wells include raised features or islands which form additional surfaces for contacting an FAU.

At block <NUM>, the technician disposes an FAU on the epoxy well. According to the claimed invention, the FAU includes at least one optical window disposed over the epoxy well (but can include multiple optical windows extending over a single well). The optical window forms an aperture in a non-transparent layer in the FAU (e.g., the silicon layer <NUM> or <NUM>) which permits electromagnetic radiation passing through a transparent substrate to reach the epoxy well.

At block <NUM>, the technician aligns the optical fibers mounted on the FAU to an optical interface on the photonic chip. In one embodiment, the FAU and photonic chip include interlocking or mating alignment features such as the alignment slots <NUM> shown in <FIG> and the alignment features <NUM> shown in <FIG>. By locking or mating the features, the optical fibers are aligned to the optical interface in the photonic chip to permit the fibers and photonic chip to transfer optical signals. In one embodiment, the alignment features permit the optical fibers to be aligned passively. However, in another embodiment, the optical fibers are actively aligned to the photonic chip. In yet another embodiment, the alignment features may permit passive alignment in one or more directions while active alignment is used in one or more other directions.

At block <NUM>, the epoxy is cured using UV radiation that passes through the transparent substrate <NUM> and at least one optical window to reach the epoxy well.

At block <NUM>, the epoxy is further cured using a thermal curing process. That is, the method <NUM> includes two curing steps which rely on electromagnetic radiation and heat to cure the epoxy. However, in another embodiment, the block <NUM> may be omitted and the epoxy is cured using only electromagnetic radiation.

Claim 1:
A method, comprising:
disposing (<NUM>) epoxy into an epoxy well in a photonic chip (<NUM>);
aligning (<NUM>) an optical interface of the photonic chip to an optical fiber (<NUM>) mounted on a fiber array unit, FAU, (<NUM>) wherein the FAU (<NUM>) comprises a first layer (<NUM>) disposed on a transparent substrate (<NUM>), wherein a material of the transparent substrate is transparent to UV light while a material of the first layer blocks UV light, wherein the first layer (<NUM>) comprises an optical window (<NUM>), and wherein the transparent substrate (<NUM>) and the optical window (<NUM>) are disposed over the epoxy well when the optical fiber (<NUM>) is aligned to the optical interface; and
curing (<NUM>) the epoxy by passing UV electromagnetic radiation through the transparent substrate and the optical window (<NUM>) to reach the epoxy well.