Patent Description:
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.

For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure. Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend them into the, e.g. <NUM> or sub-<NUM> range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes. <CIT> discloses a selective growth for high-aspect ration metal fill.

<CIT> describes a method of forming ruthenium conductive structures in a metallization layer. <CIT> discloses a chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants.

Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and integrated circuit structure including semiconductor structures having wrap-around metal contacts, are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than <NUM> metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

One or more embodiments described herein are directed to the use of metal chemical vapor deposition for wrap-around semiconductor contacts. Embodiments may be applicable to or include one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

Particular embodiments may include the fabrication of a titanium or like metallic layer using a low temperature (e.g., less than <NUM> degrees Celsius, or in the range of <NUM>-<NUM> degrees Celsius) chemical vapor deposition of a contact metal to provide a conformal source/drain contact. Implementation of such a conformal source/drain contact may improve three-dimensional (3D) transistor complementary metal oxide semiconductor (CMOS) performance.

To provide context, conventional metal to semiconductor contact layers are deposited using sputtering. Sputtering is a line of sight process and may not be well suited to 3D transistor fabrication. Known sputtering solutions have poor or incomplete metal-semiconductor junctions on device contact surfaces with an angle to the incidence of deposition.

In accordance with one or more embodiments of the present disclosure, a low temperature chemical vapor deposition process is implemented for fabrication of a contact metal to provide conformality in three dimensions and maximize the metal semiconductor junction contact area. The resulting greater contact area may reduce the resistance of the junction. Embodiments may include deposition on semiconductor surfaces having a non-flat topography, where the topography of an area refers to the surface shapes and features themselves, and a non-flat topography includes surface shapes and features or portions of surface shapes and features that are non-flat, i.e., surface shapes and features that are not entirely flat.

Embodiments described herein may include fabrication of wrap-around contact structures. In one such embodiment, the use of pure metal conformally deposited onto transistor source-drain contacts by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or plasma enhanced atomic layer deposition is described. Such conformal deposition may be used to increase the available area of metal semiconductor contact and reduce resistance, improving the performance of the transistor device. In an embodiment, the relatively low temperature of the deposition leads to a minimized resistance of the junction per unit area.

<FIG> illustrates a cross-sectional view of a semiconductor fin having a conductive contact formed thereon by sputter deposition.

Referring to <FIG>, a sputtered contact <NUM> is formed over a semiconductor feature <NUM>, such as a semiconductor fin, formed above a substrate <NUM>. The sputtered contact includes portions 104A covering lower flat surfaces, sidewall portions 104B covering non-flat surfaces, and portions 104C covering upper flat surfaces. The thickness X<NUM> of the portions 104B covering non-flat surfaces are substantially thinner than the thickness Yi of the portions 104C covering upper flat surfaces and substantially thinner than the portions 104A covering lower flat surfaces.

<FIG> illustrates a cross-sectional view of a semiconductor fin having a conductive contact formed thereon by chemical vapor deposition (CVD), in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a chemical vapor deposition (CVD) contact <NUM> is formed over a semiconductor feature <NUM>, such as a semiconductor fin, formed above a substrate <NUM>. The CVD contact includes portions 154A covering lower flat surfaces, sidewall portions 154B covering non-flat surfaces, and portions 154C covering upper flat surfaces. The thickness X<NUM> of the portions 154B covering non-flat surfaces are substantially the same as the thickness Y<NUM> of the portions 154C covering upper flat surfaces and substantially the same as the portions 154A covering lower flat surfaces.

It is to be appreciated that a variety of integrated circuit structures may be fabricated using an integration scheme involving a metallic layer deposition process as described herein. In accordance with an embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having a feature thereon. The method also includes reacting titanium tetrachloride (TiCl<NUM>) and hydrogen (H<NUM>) to form a titanium (Ti) layer on the feature of the substrate. In one embodiment, the reacting is performed at a temperature in the range of <NUM>-<NUM> degrees Celsius, at a pressure in the range of <NUM>-<NUM> Torr, and at an RF frequency of approximately <NUM> or approximately <NUM>.

In the invention, the titanium layer has a total atomic composition including <NUM>% or greater of titanium and <NUM>-<NUM>% of chlorine. In alternative embodiments, a similar process is used to fabricate a high purity metallic layer of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V). In an embodiment, there is relatively little film thickness variation, e.g., in an embodiment all coverage is greater than <NUM>% and nominal is <NUM>% or greater (i.e., thickness variation of <NUM>% or less). In an embodiment, thickness is measurably thicker on silicon (Si) or silicon germanium (SiGe) than other surfaces, as the Si or SiGe reacts during deposition and speeds uptake of the Ti. In an embodiment, the film composition includes approximately <NUM>% Cl (or less than <NUM>%) as an impurity, with essentially no other observed impurities. In an embodiment, the deposition process enables metal coverage on non-line of sight surfaces, such as surfaces hidden by a sputter deposition line of sight. Embodiments described herein may be implemented to improves transistor device drive by reducing the external resistance of current being driven through the source and drain contacts.

In accordance with an embodiment of the present disclosure, the feature of the substrate is a source/drain contact trench exposing a semiconductor source/drain structure. The titanium layer (or other high purity metallic layer) is a conductive contact layer for the semiconductor source/drain structure. Exemplary embodiments of such an implementation are described below in association with <FIG>, <FIG>, <FIG> and <FIG>.

In accordance with another embodiment of the present disclosure, the feature of the substrate is a conductive line trench of a back end-of-line (BEOL) metallization layer. The titanium layer (or other high purity metallic layer) is barrier layer for a conductive line. Exemplary embodiments of such an implementation are described below in association with <FIG>.

In accordance with another embodiment of the present disclosure, the feature of the substrate is a gate trench of a semiconductor device. The titanium layer (or other high purity metallic layer) is a workfunction layer of a metal gate electrode of the semiconductor device. Exemplary embodiments of such an implementation are described below in association with <FIG>.

As exemplified by various embodiments described below, an integrated circuit structure may include a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. In one such embodiment, the metallic contact material has a total atomic composition including <NUM>% or greater of a single metal species.

In the invention, the metallic contact material has a total atomic composition including <NUM>% or greater of titanium. In the invention, the total atomic composition of metallic contact material further includes <NUM>-<NUM>% of chlorine. In an embodiment, the metallic contact material has a thickness variation of <NUM>% or less along the non-flat topography of the portion of the semiconductor feature. In an embodiment, the non-flat topography of the portion of the semiconductor feature includes a raised central portion and lower side portions. In an embodiment, the non-flat topography of the portion of the semiconductor feature includes a saddle-shaped portion.

In an embodiment, the semiconductor feature includes silicon. In one such embodiment, the semiconductor feature further includes germanium. In an embodiment, the metallic contact material is further along sidewalls of the trench in the dielectric layer. In one such embodiment, a thickness of the metallic contact material along the sidewalls of the trench thins from the portion of the semiconductor feature to a location above the portion of the semiconductor feature. In an embodiment, a conductive fill material is on the metallic contact material within the trench.

<FIG> illustrates a cross-sectional view of a semiconductor device having a conductive contact on a source or drain region, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a semiconductor structure <NUM> includes a gate structure <NUM> above a substrate <NUM>. The gate structure <NUM> includes a gate dielectric layer 202A, a workfunction layer 202B, and a gate fill 202C. A source region <NUM> and a drain region <NUM> are on opposite sides of the gate structure <NUM>. Source or drain contacts <NUM> are electrically connected to the source region <NUM> and the drain region <NUM>, and are spaced apart of the gate structure <NUM> by one or both of an inter-layer dielectric layer <NUM> or gate dielectric spacers <NUM>. The source region <NUM> and the drain region <NUM> are regions of the substrate <NUM>.

In an embodiment, the source or drain contacts <NUM> include a high purity metallic layer 212A, such as described above, and a conductive trench fill material 212B. In the invention, the high purity metallic layer 212A has a total atomic composition including <NUM>% or greater of titanium. In the invention, the total atomic composition of the high purity metallic layer 212A further includes <NUM>-<NUM>% of chlorine. In an embodiment, the high purity metallic layer 212A has a thickness variation of <NUM>% or less. In an embodiment, the conductive trench fill material 212B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

<FIG> illustrates a cross-sectional view of another semiconductor device having a conductive on a raised source or drain region, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a semiconductor structure <NUM> includes a gate structure <NUM> above a substrate <NUM>. The gate structure <NUM> includes a gate dielectric layer 252A, a workfunction layer 252B, and a gate fill 252C. A source region <NUM> and a drain region <NUM> are on opposite sides of the gate structure <NUM>. Source or drain contacts <NUM> are electrically connected to the source region <NUM> and the drain region <NUM>, and are spaced apart of the gate structure <NUM> by one or both of an inter-layer dielectric layer <NUM> or gate dielectric spacers <NUM>. The source region <NUM> and the drain region <NUM> are epitaxial and/or embedded material regions formed in etched-out regions of the substrate <NUM>. As is depicted, in an embodiment, the source region <NUM> and the drain region <NUM> are raised source and drain regions. In a specific such embodiment, the raised source and drain regions are raised silicon source and drain regions or raised silicon germanium source and drain regions.

In an embodiment, the source or drain contacts <NUM> include a high purity metallic layer 262A, such as described above, and a conductive trench fill material 262B. In the invention, the high purity metallic layer 262A has a total atomic composition including <NUM>% or greater of titanium. In the invention, the total atomic composition of the high purity metallic layer 262A further includes <NUM>-<NUM>% of chlorine. In an embodiment, the high purity metallic layer 262A has a thickness variation of <NUM>% or less. In an embodiment, the conductive trench fill material 262B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

Accordingly, in an embodiment, referring collectively to <FIG>, an integrated circuit structure includes a feature having a surface (source or drain contact trench exposing a semiconductor source or drain structure). A high purity metallic layer 212A or 262A is on the surface of the source or drain contact trench. It is to be appreciated that contact formation processes can involve consumption of an exposed silicon or germanium or silicon germanium material of a source or drain regions. Such consumption can degrade device performance. In contrast, in accordance with an embodiment of the present disclosure, a surface (<NUM> or <NUM>) of the semiconductor source (<NUM> or <NUM>) or drain (<NUM> or <NUM>) structure is not eroded or consumed, or is not substantially eroded or consumed beneath the source or drain contact trench. In one such embodiment, the lack of consumption or erosion arises from the low temperature deposition of the high purity metallic contact layer.

<FIG> illustrates a plan view of a plurality of gate lines over a pair of semiconductor fins, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a plurality of active gate lines <NUM> is formed over a plurality of semiconductor fins <NUM>. Dummy gate lines <NUM> are at the ends of the plurality of semiconductor fins <NUM>. Spacings <NUM> between the gate lines <NUM>/<NUM> are locations where trench contacts may be formed as conductive contacts to source/drain regions, such as source/drain regions <NUM>, <NUM>, <NUM>, and <NUM>.

In an embodiment, the pattern of the plurality of gate lines <NUM>/<NUM> and/or the pattern of the plurality of semiconductor fins <NUM> is described as a grating structure. In an embodiment, the term "grating" for the plurality of gate lines <NUM>/<NUM> and/or the pattern of the plurality of semiconductor fins <NUM> is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have the plurality of gate lines <NUM>/<NUM> and/or the pattern of the plurality of semiconductor fins <NUM> spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach.

<FIG> illustrate cross-sectional views, taken along the a-a' axis of <FIG>, for various operations in a method of fabricating an integrated circuit structure, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a plurality of active gate lines <NUM> is formed over a semiconductor fin <NUM> formed above a substrate <NUM>. Dummy gate lines <NUM> are at the ends of the semiconductor fin <NUM>. A dielectric layer <NUM> is between the active gate lines <NUM>, between the dummy gate lines <NUM> and the active gate lines <NUM>, and outside of the dummy gate lines <NUM>. Embedded source/drain structures <NUM> are in the semiconductor fin <NUM> between the active gate lines <NUM> and between the dummy gate lines <NUM> and the active gate lines <NUM>. The active gate lines <NUM> include a gate dielectric layer <NUM>, a workfunction gate electrode portion <NUM> and a fill gate electrode portion <NUM>, and a dielectric capping layer <NUM>. Dielectric spacers <NUM> line the sidewalls of the active gate lines <NUM> and the dummy gate lines <NUM>.

Referring to <FIG>, the portion of the dielectric layer <NUM> between the active gate lines <NUM> and between the dummy gate lines <NUM> and the active gate lines <NUM> is removed to provide openings <NUM> in locations where trench contacts are to be formed. Removal of the portion of the dielectric layer <NUM> between the active gate lines <NUM> and between the dummy gate lines <NUM> and the active gate lines <NUM> may lead to erosion of the embedded source/drain structures <NUM> to provide eroded embedded source/drain structures <NUM> which may have an upper saddle-shaped topography, as is depicted in <FIG>.

Referring to <FIG>, trench contacts <NUM> are formed in openings <NUM> between the active gate lines <NUM> and between the dummy gate lines <NUM> and the active gate lines <NUM>. Each of the trench contacts <NUM> may include a metallic contact layer <NUM> and a conductive fill material <NUM>.

<FIG> illustrates a cross-sectional view, taken along the b-b' axis of <FIG>, for an integrated circuit structure, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, fins <NUM> are depicted above a substrate <NUM>. Lowe portions of the fins <NUM> are surrounded by a trench isolation material <NUM>. Upper portions of fins <NUM> have been removed to enable growth of embedded source and drain structures <NUM>. A trench contact <NUM> is formed in an opening of a dielectric layer <NUM>, the opening exposing the embedded source and drain structures <NUM>. The trench contact includes a metallic contact layer <NUM> and a conductive fill material <NUM>. It is to be appreciated that, in accordance with an embodiment, the metallic contact layer <NUM> extends to the top of the trench contact <NUM>, as is depicted in <FIG>. In another embodiment, however, the metallic contact layer <NUM> does not extend to the top of the trench contact <NUM> and is somewhat recessed within the trench contact <NUM>, e.g., similar to the depiction of metallic contact layer <NUM> in <FIG>.

Accordingly, referring collectively to <FIG>, <FIG> and <FIG>, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a semiconductor fin (<NUM>, <NUM>, <NUM>) above a substrate (<NUM>, <NUM>). The semiconductor fin (<NUM>, <NUM>, <NUM>) having a top and sidewalls. A gate electrode (<NUM>, <NUM>) is over the top and adjacent to the sidewalls of a portion of the semiconductor fin (<NUM>, <NUM>, <NUM>). The gate electrode (<NUM>, <NUM>) defines a channel region in the semiconductor fin (<NUM>, <NUM>, <NUM>). A first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) is at a first end of the channel region at a first side of the gate electrode (<NUM>, <NUM>), the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) having a non-flat topography. A second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) is at a second end of the channel region at a second side of the gate electrode (<NUM>, <NUM>), the second end opposite the first end, and the second side opposite the first side. The second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) has a non-flat topography. A metallic contact material (<NUM>, <NUM>) is directly on the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and directly on the second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>). The metallic contact material (<NUM>, <NUM>) is conformal with the non-flat topography of the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and conformal with the non-flat topography of the second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>). In the invention, the metallic contact material (<NUM>, <NUM>) has a total atomic composition including <NUM>% or greater of titanium. In the invention, the total atomic composition of metallic contact material (<NUM>, <NUM>) further includes <NUM>-<NUM>% of chlorine. In an embodiment, the metallic contact material (<NUM>, <NUM>) has a thickness variation of <NUM>% or less along the non-flat topography of the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and along the non-flat topography of the second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>).

In an embodiment, the non-flat topography of the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and the non-flat topography of the second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) both include a raised central portion and lower side portions, e.g., as is depicted in <FIG>. In an embodiment, the non-flat topography of the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and the non-flat topography of the second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) both include saddle-shaped portions, e.g., as is depicted in <FIG>.

In an embodiment, the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and the second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) both include silicon. In an embodiment, the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and the second semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) both further include germanium, e.g., in the form of silicon germanium.

In an embodiment, the metallic contact material (<NUM>, <NUM>) directly on the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) is further along sidewalls of a trench in a dielectric layer (<NUM>, <NUM>) over the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>), the trench exposing a portion of the first semiconductor source/drain structure (<NUM>, <NUM>, <NUM>). In one such embodiment, a thickness of the metallic contact material (<NUM>) along the sidewalls of the trench thins from the first semiconductor source/drain structure (436A at <NUM>) to a location (436B) above the first semiconductor source/drain structure (<NUM>), an example of which is illustrated in <FIG>. In an embodiment, a conductive fill material (<NUM>, <NUM>) is on the metallic contact material (<NUM>, <NUM>) within the trench, as is depicted in <FIG>.

In an embodiment, the integrated circuit structure further includes a second semiconductor fin (e.g., upper fin <NUM> of <FIG>, <NUM>, <NUM>) having a top and sidewalls. The gate electrode (<NUM>, <NUM>) is further over the top and adjacent to the sidewalls of a portion of the second semiconductor fin, the gate electrode defining a channel region in the second semiconductor fin. A third semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) is at a first end of the channel region of the second semiconductor fin at the first side of the gate electrode (<NUM>, <NUM>), the third semiconductor source/drain structure having a non-flat topography. A fourth semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) is at a second end of the channel region of the second semiconductor fin at the second side of the gate electrode (<NUM>, <NUM>), the second end opposite the first end, the fourth semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) having a non-flat topography. The metallic contact material (<NUM>, <NUM>) is directly on the third semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and directly on the fourth semiconductor source/drain structure (<NUM>, <NUM>, <NUM>), the metallic contact material (<NUM>, <NUM>) conformal with the non-flat topography of the third semiconductor source/drain structure (<NUM>, <NUM>, <NUM>) and conformal with the non-flat topography of the fourth semiconductor source/drain structure (<NUM>, <NUM>, <NUM>). In an embodiment, the metallic contact material (<NUM>, <NUM>) is continuous between the first semiconductor source/drain structure (<NUM>, <NUM>, left side <NUM>) and the third semiconductor source/drain structure (<NUM>, <NUM>, right side <NUM>) and continuous between the second semiconductor source/drain structure (<NUM>) and the fourth semiconductor source/drain structure (<NUM>).

<FIG> illustrates a plan view and corresponding cross-sectional view of a metallization layer of an integrated circuit structure, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a metallization layer <NUM> includes a pattern of conductive lines <NUM> and interlayer dielectric (ILD) lines <NUM>. The metallization layer <NUM> may be patterned in a grating-like pattern with conductive lines <NUM> spaced at a constant pitch and having a constant width, as is depicted in <FIG>. Although not shown, the conductive lines <NUM> may have interruptions (i.e., cuts or plugs) at various locations along the lines. Some of the conductive lines may be associated with underlying vias, such as line <NUM>' shown as an example in the cross-sectional view.

In an embodiment, the term "grating" for conductive lines <NUM> and ILD lines <NUM> is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have conductive lines <NUM> and/or ILD lines <NUM> spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach.

In an embodiment, the conductive lines <NUM> (and, possibly, underlying via structures) are composed of one or more metal or other conductive structures. The conductive lines <NUM> are also sometimes referred to in the art as traces, wires, lines, metal, interconnect lines or simply interconnects. In a particular embodiment, each of the conductive lines <NUM> includes a barrier layer <NUM> and a conductive fill material <NUM>.

In an embodiment, the barrier layer <NUM> is a high purity metallic layer, such as described above. In the invention, the high purity metallic barrier layer <NUM> has a total atomic composition including <NUM>% or greater of titanium. In the invention, the total atomic composition of the high purity metallic barrier layer <NUM> further includes <NUM>-<NUM>% of chlorine. In an embodiment, the high purity metallic barrier layer <NUM> has a thickness variation of <NUM>% or less. In an embodiment, the conductive fill material <NUM> is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

Accordingly, in an embodiment, an integrated circuit structure includes a feature having a surface (conductive line trench of a back end-of-line (BEOL) metallization layer). A high purity metallic barrier layer <NUM> is on the surface of the conductive line trench. In one such embodiment, the high purity metallic barrier layer <NUM> is a barrier layer for a conductive line <NUM>.

In an embodiment, ILD lines <NUM> are composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO<NUM>)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

It is to be appreciated that the layers and materials described in association with <FIG> are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, the structure depicted in <FIG> may be fabricated on underlying lower level back end of line (BEOL) interconnect layers.

One or more embodiments described herein are directed to fabricating semiconductor devices, such as for metal oxide semiconductor (MOS) device fabrication. As an example, <FIG> illustrates a cross-sectional view of a non-planar semiconductor device having a CVD-deposited layer as a workfunction layer of a gate electrode, in accordance with an embodiment of the present disclosure. <FIG> illustrates a plan view taken along the a-a' axis of the semiconductor device of <FIG>, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a semiconductor structure or device <NUM> includes a non-planar active region (e.g., a fin structure including protruding fin portion <NUM> and sub-fin region <NUM>) formed from substrate <NUM>, and within isolation region <NUM>. A gate line <NUM> is disposed over the protruding portions <NUM> of the non-planar active region as well as over a portion of the isolation region <NUM>. As shown, gate line <NUM> includes a gate electrode <NUM>/<NUM> and a gate dielectric layer <NUM>. In one embodiment, gate line <NUM> may also include a dielectric cap layer <NUM>. A gate contact <NUM>, and overlying gate contact via <NUM> are also seen from this perspective, along with an overlying metal interconnect <NUM>, all of which are disposed in inter-layer dielectric stacks or layers <NUM>. Also seen from the perspective of <FIG>, the gate contact <NUM> is, in one embodiment, disposed over isolation region <NUM>, but not over the non-planar active regions.

In accordance with an embodiment of the present disclosure, the layer <NUM> of gate electrode <NUM>/<NUM> is a high purity metallic layer, such as described above. In one embodiment, the high purity metallic layer <NUM> is in a gate trench, and is on or above gate dielectric layer <NUM>. In one such embodiment, the high purity metallic layer <NUM> is a workfunction layer of a metal gate electrode of a transistor <NUM> of the integrated circuit structure. In a particular embodiment, the transistor <NUM> is an N-type (NMOS) transistor, and the high purity metallic layer <NUM> has an N-type workfunction. In another particular embodiment, the transistor <NUM> is a P-type (PMOS) transistor, and the high purity metallic layer <NUM> has a P-type workfunction
Accordingly, in an embodiment, the semiconductor structure or device <NUM> has a feature (gate line <NUM>) having a surface (gate dielectric layer <NUM>). A CVD-deposited workfunction-setting layer <NUM> (layer <NUM> of gate electrode <NUM>/<NUM>) is formed on or proximate to a gate dielectric layer <NUM>. In the invention, the CVD-deposited workfunction-setting layer <NUM> has a total atomic composition including <NUM>% or greater of titanium. In the invention, the total atomic composition of the CVD-deposited workfunction-setting layer <NUM> further includes <NUM>-<NUM>% of chlorine. In an embodiment, the CVD-deposited workfunction-setting layer <NUM> has a thickness variation of <NUM>% or less.

Referring to <FIG>, the gate line <NUM> is shown as disposed over the protruding fin portions <NUM>. Source and drain regions 704A and 704B of the protruding fin portions <NUM> can be seen from this perspective. In one embodiment, the source and drain regions 704A and 704B are doped portions of original material of the protruding fin portions <NUM>. In another embodiment, the material of the protruding fin portions <NUM> is removed and replaced with another semiconductor material, e.g., by epitaxial deposition. In either case, the source and drain regions 704A and 704B may extend below the height of dielectric layer <NUM>, i.e., into the sub-fin region <NUM>.

In an embodiment, the semiconductor structure or device <NUM> is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode and gate electrode materials of gate lines <NUM> surround at least a top surface and a pair of sidewalls of the three-dimensional body.

Substrate <NUM> may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, substrate <NUM> is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, antimony, boron, gallium or a combination thereof, to form active region <NUM>. In one embodiment, the concentration of silicon atoms in bulk substrate <NUM> is greater than <NUM>%. In another embodiment, bulk substrate <NUM> is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. Bulk substrate <NUM> may alternatively be composed of a group III-V material. In an embodiment, bulk substrate <NUM> is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate <NUM> is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, magnesium, beryllium, zinc, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

Isolation region <NUM> may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the isolation region <NUM> is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

In an embodiment, the gate dielectric layer <NUM> is composed of a high-K material. For example, in one embodiment, the gate dielectric layer <NUM> is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate <NUM>. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer <NUM> is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride.

In an embodiment, layer <NUM> of the gate electrode <NUM>/<NUM> is composed of a non-workfunction-setting conductive fill material formed above the CVD-deposited workfunction-setting layer <NUM>. In one such embodiment, the conductive fill material <NUM> includes a material such as but not limited to, tungsten (W), aluminum (Al), or copper (Cu). In one embodiment, one or more conductive barrier layers (such as titanium nitride or tantalum nitride) is between layers <NUM> and <NUM> of the gate electrode. In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In an embodiment, the dielectric cap layer <NUM> and/or dielectric spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent or overlying conductive contacts, such as self-aligned contacts. For example, in one embodiment, the dielectric cap layer <NUM> and/or dielectric spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Gate contact <NUM>, overlying gate contact via <NUM>, and/or overlying metal interconnect <NUM> may be composed of a conductive material. In an embodiment, one or more of the contacts, interconnects or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material). In a particular embodiment, one or more of gate contact <NUM>, overlying gate contact via <NUM>, or overlying metal interconnect <NUM> includes a barrier layer and a conductive fill material. In one such embodiment, the barrier layer is a high purity metallic layer, such as described above. In the invention, the high purity metallic barrier layer has a total atomic composition including <NUM>% or greater of titanium. In the invention, the total atomic composition of the high purity metallic barrier layer further includes <NUM>-<NUM>% of chlorine. In an embodiment, the high purity metallic barrier layer has a thickness variation of <NUM>% or less. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

In an embodiment (although not shown), providing structure <NUM> involves formation of a contact pattern which is essentially perfectly aligned to an existing gate pattern while eliminating the use of a lithographic step with exceedingly tight registration budget. In one such embodiment, this approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

Furthermore, the gate stack structure <NUM> may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF<NUM>. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH<NUM>OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure <NUM>. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature greater than approximately <NUM> degrees Celsius. The anneal is performed prior to formation of the permanent contacts.

Referring again to <FIG>, the arrangement of semiconductor structure or device <NUM> places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space in certain applications. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region. In general, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separate patterning of contact features.

In a particular embodiment, each of the trench contacts includes a barrier layer and a conductive fill material. In one such embodiment, the barrier layer is a high purity metallic layer, such as described above. In the invention, the high purity metallic barrier layer has a total atomic composition including <NUM>% or greater of titanium. In the invention, the total atomic composition of the high purity metallic barrier layer further includes <NUM>-<NUM>% of chlorine. In an embodiment, the high purity metallic barrier layer has a thickness variation of <NUM>% or less. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a trigate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a <NUM> nanometer (<NUM>) or smaller technology node.

In an embodiment, as is also used throughout the present description, lithographic operations are performed using <NUM> immersion lithography (i <NUM>), extreme ultra-violet (EUV) and/or electron beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

<FIG> illustrates a computing device <NUM> in accordance with one implementation of the disclosure. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more structures fabricated to include a CVD-deposited metal film, in accordance with implementations of embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more structures fabricated to include CVD-deposited metal film, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes one or more structures fabricated to include a CVD-deposited metal film, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

<FIG> illustrates an interposer <NUM> that includes one or more embodiments of the disclosure. The interposer <NUM> is an intervening substrate used to bridge a first substrate <NUM> to a second substrate <NUM>. The first substrate <NUM> may be, for instance, an integrated circuit die. The second substrate <NUM> may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer <NUM> is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer <NUM> may couple an integrated circuit die to a ball grid array (BGA) <NUM> that can subsequently be coupled to the second substrate <NUM>. In some embodiments, the first and second substrates <NUM>/<NUM> are attached to opposing sides of the interposer <NUM>. In other embodiments, the first and second substrates <NUM>/<NUM> are attached to the same side of the interposer <NUM>. And in further embodiments, three or more substrates are interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer <NUM>. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer <NUM>.

Claim 1:
An integrated circuit structure, comprising:
a semiconductor feature (<NUM>) above a substrate (<NUM>);
a dielectric layer (<NUM>) over the semiconductor feature, the dielectric layer having a trench
exposing a portion of the semiconductor feature, the portion having a non-flat topography; and
a metallic contact material (<NUM>) directly on the portion of the semiconductor feature, the metallic contact material conformal with the non-flat topography of the portion of the semiconductor feature, and the metallic contact material having a total atomic composition comprising
<NUM>% or greater of titanium
and <NUM>-<NUM>% of chlorine.