Patent Description:
As a non-volatile memory, a flash memory may maintain stored data even when power is cut off. A storage device including NAND flash memory of a solid state disk (SSD) is useful to store or move a large amount of data.

By increasing a bandwidth through parallel processing between a host and the NAND flash memory, the performance of the SSD may be improved. At this time, a buffer memory is used to compensate for a performance difference between the host and the NAND flash memory. For high-speed performance, a static random access memory (SRAM) is used as the buffer memory. With the development of technology, a chip size is gradually reduced. However, as the required performance of the storage device increases, a role of the buffer memory may not be performed only by the SRAM and a dynamic RAM (DRAM) may additionally be introduced. Accordingly, a method of efficiently and simultaneously using the DRAM and the SRAM as the buffer memory is required.

<CIT> discloses a memory system comprising a memory controller having a main-buffer, a sub-buffer memory arranged outside of the controller and a buffer allocation circuit.

Provided is a memory controller that controls an allocation ratio among heterogeneous buffer memory components, a memory system including the same, and an operating method of the memory controller.

According to a first aspect of the invention, there is provided a memory system including a memory controller configured to control a memory device and a sub-buffer memory arranged outside the memory controller. The memory controller includes a processor configured to control a memory operation for the memory device, a main buffer memory that is different from the sub-buffer memory and arranged in the memory controller, and a buffer allocation circuit configured to control an allocation ratio between the sub-buffer memory and the main buffer memory. The processor sets an operation mode of the buffer allocation circuit and the buffer allocation circuit controls the allocation ratio based on the operation mode, wherein the main buffer memory is a static random access memory (SRAM), and wherein the sub-buffer memory is a dynamic random access memory (DRAM).

According to another aspect of the invention, there is provided a method including receiving a command from a host, determining an operation mode of a buffer allocation circuit in a memory controller as one of a first operation mode and a second operation mode, when the buffer allocation circuit is in the first operation mode, setting an allocation ratio between a main buffer memory arranged in the memory controller and a sub-buffer memory arranged outside the memory controller to a predefined ratio; and when the buffer allocation circuit is in the second operation mode, variably setting the allocation ratio based on a type of the command, wherein the main buffer memory is a static random access memory (SRAM), and wherein the sub-buffer memory is a dynamic random access memory (DRAM).

Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

<FIG> is a block diagram illustrating a memory system <NUM> according to an embodiment.

Referring to <FIG>, the memory system <NUM> may include a memory device <NUM>, a memory controller <NUM>, and sub-buffer memory <NUM>. The memory system <NUM> may communicate with a host HOST through various interfaces, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnection (PCI), a PCI-express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer small interface (SCSI), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), firewire, a universal flash storage (UFS), a non-volatile memory express (NVMe), and/or a compute Express Link™ (CXL).

In some embodiments, the memory system <NUM> may include memory that may be mounted in or detached from an electronic device in one of various forms, for example, an embedded universal flash storage (UFS) memory device, an embedded multimedia card (eMMC), a solid state drive (SSD), a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro-SD card, a mini-SD card, an extreme digital (xD) card, or a memory stick. In addition, the memory system <NUM> may be referred to as a storage device that stores data to be non-volatile.

According to various embodiments, the memory device <NUM> may include a memory cell array <NUM> and a control logic circuit <NUM>. The memory cell array <NUM> may include a plurality of memory cells. For example, the plurality of memory cells may respectively include flash memory cells. Hereinafter, some embodiments are described in detail taking a case in which the plurality of memory cells respectively include NAND flash memory cells as an example. However, embodiments are not limited thereto. In some embodiments, the plurality of memory cells may include resistive memory cells, such as resistive random access memory (ReRAM) memory cells, phase change RAM (PRAM) memory cells, or magnetic RAM (MRAM) memory cells. In an embodiment, the memory cell array <NUM> may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each of the plurality of NAND strings may include memory cells respectively connected to word lines perpendicularly stacked on a substrate. However, embodiments are not limited thereto. In some embodiments, the memory cell array <NUM> may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include the plurality of NAND strings arranged in rows and columns.

The control logic circuit <NUM> may control all operations of the memory device <NUM>. For example, the control logic circuit <NUM> may output various internal control signals for programming data in the memory cell array <NUM> or reading data from the memory cell array <NUM>, based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller <NUM>.

The memory controller <NUM> includes a processor <NUM>, a buffer allocation circuit <NUM>, and main buffer memory <NUM>.

The memory controller <NUM> may control the memory device <NUM> to read the data stored in the memory cell array <NUM> of the memory device <NUM> or to write the data in the memory cell array <NUM> of the memory device <NUM>, in response to a record/read request from the host HOST. For example, the memory controller <NUM> may include the processor <NUM> that may control all operations in the memory controller <NUM>. In some embodiments, the processor <NUM> may be a central processing unit (CPU), a microprocessor, a microcontroller, or hardware control logic. In some embodiments, plural processors <NUM> may be provided. The processor <NUM> may control a memory operation of the memory device <NUM>. Specifically, the memory controller <NUM> may provide the address ADDR, the command CMD, and the control signal CTRL to the memory device <NUM> to control write, read, and erase operations of the memory device <NUM>. For example, the memory controller <NUM> may provide a sequential write command or a random write command for recording the data in the memory device <NUM> to the memory device <NUM>. As another example, the memory controller <NUM> may provide a sequential read command or a random read command for reading the data stored in the memory device <NUM> to the memory device <NUM>.

The memory controller <NUM> includes a buffer allocation circuit <NUM> and main buffer memory <NUM>. The main buffer memory <NUM> as buffer memory mounted in the memory controller <NUM> is referred to as internal buffer memory. The main buffer memory <NUM> includes SRAM for a high speed operation. Because the main buffer memory <NUM> is mounted in the memory controller <NUM>, a gate count value of a chip of the memory controller <NUM> may increase. The sub-buffer memory <NUM> arranged outside the memory controller <NUM> is referred to as an external buffer memory. The sub-buffer memory <NUM> includes DRAM.

The buffer allocation circuit <NUM> controls an allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM>. The allocation ratio may be expressed in the form: [main buffer memory]:[sub-buffer memory]. According to an embodiment, the buffer allocation circuit <NUM> may control the allocation ratio based on a kind of a command received by the memory controller <NUM> from the host HOST. For example, the memory controller <NUM> may receive the sequential write command from the host HOST. The buffer allocation circuit <NUM> may request the main buffer memory <NUM> and the sub-buffer memory <NUM> to allocate a buffer based on a predefined first ratio, in response to the received sequential write command. The predefined first ratio may be expressed in the form: main buffer memory: sub-buffer memory and may be, for example, <NUM>:<NUM>. As another example, the memory controller <NUM> may receive one of the random write command, the sequential read command, and the random read command from the host HOST. The buffer allocation circuit <NUM> may request only the sub-buffer memory <NUM> to allocate a buffer based on a predefined second ratio in response to the received command. That is, the predefined second ratio may be, for example, <NUM>:<NUM>, or the predefined second ratio may be <NUM>:<NUM>.

According to another embodiment, the buffer allocation circuit <NUM> may control the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> based on a monitoring result value of the memory controller <NUM>. For example, the buffer allocation circuit <NUM> may further include a monitoring circuit for tracking a command processing speed of the memory controller <NUM>. The buffer allocation circuit <NUM> may receive the monitoring result value from the monitoring circuit and, when the monitoring result value is less than a threshold value, may control the allocation ratio of the main buffer memory <NUM> to increase in order to increase the command processing speed, as described below in detail.

<FIG> is a block diagram illustrating the memory device <NUM> according to an embodiment.

Referring to <FIG> and <FIG>, the memory device <NUM> may further include a page buffer circuit <NUM>, a voltage generator <NUM>, and a row decoder <NUM> in addition to the memory cell array <NUM> and the control logic circuit <NUM>. Although not shown, the memory device <NUM> may further include an interface circuit, and the interface circuit may include a data input/output circuit and a command/address input/output circuit.

The memory cell array <NUM> may include a plurality of memory blocks BLK1 to BLKz, where z is a positive integer. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of pages, each of which may include a plurality of memory cells. For example, a memory block may be an erase unit and a page may be a write and read unit. Each of the plurality of memory cells may store one or more bits. Specifically, each of the plurality of memory cells may be used as a single level cell (SLC), a multilevel cell (MLC), a triple level cell (TLC), or a quadruple level cell (QLC).

The memory cell array <NUM> may be connected to a plurality of word lines WL, a plurality of string selection lines SSL, a plurality of ground selection lines GSL, and a plurality of bit lines BL. The memory cell array <NUM> may be connected to the row decoder <NUM> through the plurality of word lines WL, the plurality of string selection lines SSL, and the plurality of ground selection lines GSL and may be connected to the page buffer circuit <NUM> through the plurality of bit lines BL. In some embodiments, the memory cell array <NUM> may be further connected to gate induced drain leakage (GIDL) erase control lines.

In an embodiment, the memory cell array <NUM> may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of cell strings or NAND strings. Each of the plurality of cell strings may include a plurality of memory cells respectively connected to the plurality of word lines perpendicularly stacked on a substrate. <CIT>; <CIT>; <CIT>; <CIT>; and <CIT> describe various aspects of three-dimensional memory devices.

The control logic circuit <NUM> may output various control signals for writing data in the memory cell array <NUM> or reading data from the memory cell array <NUM>, based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller <NUM>. The control logic circuit <NUM> may control all operations in the memory device <NUM>. Specifically, the control logic circuit <NUM> may provide a voltage control signal CTRL_vol to the voltage generator <NUM>, may provide a row address X_ADDR to the row decoder <NUM>, and may provide a column address Y_ADDR to the page buffer circuit <NUM>. However, embodiments are not limited thereto, and the control logic circuit <NUM> may further provide other control signals to the voltage generator <NUM>, the row decoder <NUM>, and the page buffer circuit <NUM>.

The voltage generator <NUM> may generate various kinds of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. Specifically, the voltage generator <NUM> may generate a word line voltage VWL, a string selection line voltage VSSL, and a ground selection line voltage VGSL and may provide the word line voltage VWL, the string selection line voltage VSSL, and the ground selection line voltage VGSL to the row decoder <NUM>. For example, the voltage generator <NUM> may generate a program voltage, a pass voltage, a read voltage, a program verification voltage, or an erase voltage as the word line voltage VWL. In addition, the voltage generator <NUM> may further generate a bit line voltage and a common source line voltage.

The row decoder <NUM> may select one of the plurality of word lines WL and one of the plurality of string selection lines SSL in response to the row address X_ADDR. For example, during the program operation, the row decoder <NUM> may apply the program voltage to a selection word line in a program execution section and may apply the program verification voltage to the selection word line in a program verification section. The page buffer circuit <NUM> may select at least one of the plurality of bit lines BL in response to the column address Y_ADDR. The page buffer circuit <NUM> may operate as a write driver or a sense amplifier in accordance with an operation mode.

<FIG> is a circuit diagram illustrating a memory block BLK according to an embodiment.

Referring to <FIG>, the memory block BLK may correspond to one of the plurality of memory blocks BLK1 to BLKz of <FIG>. The memory block BLK may include NAND strings or cell strings NS11 to NS33 that may be connected to bit lines BL1 to BL3, string selection lines SSL1 to SSL3, word lines WL1 to WL8, and ground selection lines GSL1 to GSL3 and extend in a vertical direction VD, respectively. Here, the number of cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may vary in accordance with an embodiment.

The bit lines BL1 to BL3 may extend in a first direction or a first horizontal direction HD1, and the word lines WL1 to WL8 may extend in a second direction or a second horizontal direction HD2. The cell strings NS11, NS21, and NS31 may be between the first bit line BL1 and a common source line CSL, the cell strings NS12, NS22, and NS32 may be between the second bit line BL2 and the common source line CSL, and the cell strings NS13, NS23, and NS33 may be between the third bit line BL3 and the common source line CSL.

For example, the cell string NS11 may include a string selection transistor SST, a plurality of memory cells MCs, and a ground selection transistor GST that are serially connected to one another. The string selection transistor SST may be connected to the string selection line SSL1, and the memory cells MCs may be respectively connected to the word lines WL1 to WL8. The ground selection transistor GST may be connected to the ground selection line GSL1.

In some embodiments, the memory block BLK may further include upper GIDL erase control lines between the bit lines BL1 to BL3 and the string selection lines SSL1 to SSL3, and each cell string may further include at least one upper GIDL erase control transistor connected to at least one upper GIDL erase control line. In some embodiments, the memory block BLK may further include lower GIDL erase control lines between the ground selection lines GSL1 to GSL3 and the common source line CSL, and each cell string may further include at least one lower GIDL erase control transistor connected to at least one lower GIDL erase control line.

<FIG> is a perspective view illustrating a memory block BLKa according to an embodiment.

Referring to <FIG>, the memory block BLKa may correspond to one of the plurality of memory blocks BLK1 to BLKz of <FIG>. The memory block BLKa is formed perpendicular to a substrate SUB.

The substrate SUB has a first conductive type (for example, p type) impurities extending in the second horizontal direction HD2. In an embodiment, a common source line CSL doped with a second conductive type (for example, n type) impurities may be provided to the substrate SUB. In an embodiment, the substrate SUB may include polysilicon and a planar (e.g. flat-plate) common source line CSL may be arranged on the substrate SUB. On the substrate SUB, a plurality of insulating layers IL extending in the second horizontal direction HD2 are sequentially provided in the vertical direction VD and are spaced apart from one another in the vertical direction VD. For example, the plurality of insulating layers IL may include an insulating material, such as silicon oxide.

On the substrate SUB, a plurality of pillars P sequentially arranged in the first horizontal direction HD1 and passing through the plurality of insulating layers IL in the vertical direction VD are provided. For example, the plurality of pillars P pass through the plurality of insulating layers IL and contact the substrate SUB. Specifically, a surface layer S of each of the plurality of pillars P may include a silicon material having a first type and may function as a channel region. Accordingly, in some embodiments, each of the plurality of pillars P may be referred to as a channel structure or a vertical channel structure. On the other hand, an internal layer I of each of the plurality of pillars P may include an insulating material, such as silicon oxide or an air gap.

A charge storage layer CS is provided along exposed surfaces of the plurality of insulating layers IL, the plurality of pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (or referred to as a 'tunneling insulating layer'), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, on the exposed surface of the charge storage layer CS, gate electrodes GE, such as ground selection lines GSL, word lines WL1 to WL8, and string selection lines SSL, are provided. The numbers of ground selection lines GSL, word lines WL1 to WL8, and string selection lines SSL may vary according to an embodiment.

On the plurality of pillars P, drain contacts or drains DR are respectively provided. For example, the drains DR may include a silicon material doped with second conductive type impurities. On the drains DR, the bit lines BL1 to BL3 extending in the first horizontal direction HD1 and spaced apart from one another by a certain distance in the second horizontal direction HD2 are provided.

<FIG> is a block diagram illustrating the memory controller <NUM> according to an embodiment.

Referring to <FIG>, the memory controller <NUM> may include the processor <NUM>, a host interface circuit <NUM>, the buffer allocation circuit <NUM>, and the main buffer memory <NUM>, and the host interface circuit <NUM> may be connected to the main buffer memory <NUM> arranged inside the memory controller <NUM> and to the sub-buffer memory <NUM> arranged outside the memory controller <NUM>.

The host interface circuit <NUM> may perform interfacing between the host HOST and the memory system <NUM>. For example, the host interface circuit <NUM> may provide a command received from the host HOST to the buffer allocation circuit <NUM>. Specifically, the host interface circuit <NUM> may provide the command to a command queue management circuit <NUM> of the buffer allocation circuit <NUM> so that received commands are sequentially processed. For example, the host interface circuit <NUM> may request buffer memory to be allocated and released. The host interface circuit <NUM> may request the buffer allocation circuit <NUM> to allocate a buffer to the main buffer memory <NUM> and the sub-buffer memory <NUM> as the buffer memory. The host interface circuit <NUM> may receive an operation done response from the buffer allocation circuit <NUM>, and may request the buffer allocation circuit <NUM> to release the allocated buffer memory.

According to various embodiments, the buffer allocation circuit <NUM> may include a special function register <NUM>, the command queue management circuit <NUM>, a buffer allocation handling circuit <NUM>, a buffer allocation checker circuit <NUM>, and a monitoring circuit <NUM>.

The special function register <NUM> may store set values of the buffer allocation circuit <NUM>. For example, the special function register <NUM> may store values corresponding to a plurality of ratios. The processor <NUM> may provide a control signal to the special function register <NUM> to control an allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> based on a value representing one of the plurality of ratios. More specifically, the special function register <NUM> may receive the control signal from the processor <NUM> and may determine an allocation ratio represented by the received control signal or corresponding to the control signal. The special function register <NUM> may provide the identified allocation ratio to the buffer allocation handling circuit <NUM>. The buffer allocation handling circuit <NUM> may return a buffer pointer value representing a starting point at which a write operation is to be performed on each of the main buffer memory <NUM> and sub-buffer memory <NUM> to the host interface circuit <NUM> based on the allocation ratio. When the processor <NUM> provides the control signal to the special function register <NUM>, the buffer allocation checker circuit <NUM> may be deactivated.

The special function register <NUM> may return a monitoring result to the processor <NUM>. The monitoring result may be a value obtained by digitizing the performance of the memory system <NUM>. For example, the performance may be a size of the buffer memory allocated per unit time. The processor <NUM> may provide the control signal representing a time interval for monitoring to the special function register <NUM>. The special function register <NUM> may receive the monitoring result from the monitoring circuit <NUM> and may store the received monitoring result at each time interval based on the control signal. The special function register <NUM> may receive a performance check request of the processor <NUM>, and may provide the monitoring result to the processor <NUM> in response to the performance check request. According to an embodiment, the processor <NUM> may return the control signal, changing the allocation ratio based on the monitoring result, to the special function register <NUM>.

The command queue management circuit <NUM> may store and manage the commands received from the host HOST. For example, the command queue management circuit <NUM> may store unprocessed commands among a plurality of commands received from the host interface circuit <NUM> in the order received. For example, the command queue management circuit <NUM> may manage a command queue so that the plurality of commands may be executed in accordance with first in first out (FIFO).

The buffer allocation checker circuit <NUM> may be activated or deactivated based on an operation mode of the memory controller <NUM>. For example, the memory controller <NUM> may operate in the first operation mode. In the first operation mode, the buffer memory may be allocated in accordance with a preset ratio regardless of the monitoring result. The first operation mode may be referred to as one of various terms including a fixed mode, a deterministic mode, and an immutable mode. That is, when the operation mode of the memory controller <NUM> is the first operation mode, the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> may be determined in accordance with the ratio designated by the processor <NUM> through the special function register <NUM>. In some embodiments, while the memory controller <NUM> operates in the first operation mode, although a performance result value output from the monitoring circuit <NUM> is lowered in real time, the preset ratio may not change. The buffer allocation checker circuit <NUM> may be deactivated while the memory controller <NUM> operates in the first operation mode. For example, the processor <NUM> may set the operation mode of the memory controller <NUM> as the first operation mode, and may provide an inactive (or disable) signal to the buffer allocation checker circuit <NUM> in response to the first operation mode. The buffer allocation checker circuit <NUM> may enter an inactive state or an idle state in response to the signal.

For example, the memory controller <NUM> may operate in the second operation mode. In the second operation mode, a ratio in which the buffer memory is allocated may change in accordance with the monitoring result. The second operation mode may be referred to as one of various terms including a floating mode, a flexible mode, and an adaptive mode. For example, the processor <NUM> may set the operation mode of the memory controller <NUM> as the second operation mode, and may provide an active (or enable) signal to the buffer allocation checker circuit <NUM> in response to the second operation mode. The buffer allocation checker circuit <NUM> may enter an active state in response to the signal. The buffer allocation checker circuit <NUM> may enter the active state and may receive the performance result value from the monitoring circuit <NUM>. When the performance result value is less than the threshold value, the buffer allocation checker circuit <NUM> may change the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> in order to improve the performance of the memory system <NUM>.

According to an embodiment, the processor <NUM> may change the operation mode in response to a trigger event. For example, the processor <NUM> may always operate in the first operation mode during initial operation. The processor <NUM> may request the performance result value at each time interval. In some embodiments, the time interval may be predefined or preset. The processor <NUM> may determine that the performance result value is less than a threshold value for the trigger event. When the performance result value is less than the threshold value, the processor <NUM> may change the operation mode of the memory controller <NUM> from the first operation mode to the second operation mode in order to improve the performance of the memory system <NUM>. For example, the processor <NUM> may provide the enable signal to the buffer allocation checker circuit <NUM> when the performance result value is less than the threshold value for the trigger event.

<FIG> is a flowchart illustrating an operation of the buffer allocation handling circuit <NUM> according to an embodiment.

Referring to <FIG>, in operation <NUM>, the buffer allocation handling circuit <NUM> may receive an allocation request. In response to a command received from the host HOST, the host interface circuit <NUM> may transmit the received command to the command queue management circuit <NUM> of the buffer allocation circuit <NUM>. The command queue management circuit <NUM> may receive the command received by the host interface circuit <NUM> and may calculate a buffer size required for processing the command to transmit the allocation request to the buffer allocation handling circuit <NUM>. For example, the command queue management circuit <NUM> may request buffer memory of (M + N).

In operation <NUM>, the buffer allocation handling circuit <NUM> may determine whether the operation mode of the memory controller <NUM> is the first operation mode. For example, the memory controller <NUM> may operate in one of the first operation mode in which the buffer allocation checker circuit <NUM> in the buffer allocation circuit <NUM> is deactivated and the second operation mode in which the buffer allocation checker circuit <NUM> in the buffer allocation circuit <NUM> is activated. The buffer allocation handling circuit <NUM> may transmit a request to determine the operation mode to the special function register <NUM> or may transmit a state request to the buffer allocation checker circuit <NUM> to determine the operation mode.

When the operation mode is the first operation mode (operation <NUM>, YES), in operation <NUM>, the buffer allocation handling circuit <NUM> may obtain information on the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> from the special function register <NUM>. In other words, when the operation mode determined in operation <NUM> is the first operation mode, a fixed allocation ratio must be obtained. Therefore, the buffer allocation handling circuit <NUM> may request the special function register <NUM> for the allocation ratio information and may obtain the allocation ratio information representing a ratio set by the processor <NUM>.

When the operation mode is not the first operation mode (operation <NUM>, NO), in operation <NUM>, the buffer allocation handling circuit <NUM> may obtain the information on the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> from the buffer allocation checker circuit <NUM>. In other words, when the operation mode determined in operation <NUM> is the second operation mode, the allocation ratio may vary depending on the performance result value output from the monitoring circuit <NUM>. Therefore, the buffer allocation handling circuit <NUM> may obtain the allocation ratio information by requesting the buffer allocation checker circuit <NUM> for the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM>.

In operation <NUM>, the buffer allocation handling circuit <NUM> may determine whether the main buffer memory <NUM> is to be allocated. When it is determined by the buffer allocation handling circuit <NUM> that the main buffer memory <NUM> is not to be allocated (operation <NUM>, NO), the sub-buffer memory <NUM> may be allocated and the process may proceed to operation <NUM>.

In operation <NUM>, the buffer allocation handling circuit <NUM> may determine whether the sub-buffer memory <NUM> is currently in a full occupancy state. In some embodiments, the full occupancy state may refer to a state in which all the buffer capacity allocated to the sub-buffer memory <NUM> is used. In some embodiments, the full occupancy state may refer to a state in which the write operation is previously performed by the size of the buffer memory allocated to the sub-buffer memory <NUM>. The buffer allocation handling circuit <NUM> may request the buffer allocation checker circuit <NUM> for information on an occupancy state of the sub-buffer memory <NUM>. The buffer allocation checker circuit <NUM> may monitor the size of previously allocated buffer memory whenever the buffer memory is allocated to the sub-buffer memory <NUM>. Therefore, when the size of the buffer memory previously allocated to the sub-buffer memory <NUM> is equal to the buffer capacity of the sub-buffer memory <NUM>, the buffer allocation checker circuit <NUM> may determine that the sub-buffer memory <NUM> is in the full occupancy state. According to an embodiment, the buffer allocation checker circuit <NUM> may respond with only whether the sub-buffer memory <NUM> is in the full occupancy state in response to the request for the information on the occupancy state of the sub-buffer memory <NUM> from the buffer allocation handling circuit <NUM>. For example, the buffer allocation checker circuit <NUM> may respond with one "logic high" bit when the sub-buffer memory <NUM> is in the full occupancy state and may respond with one "logic low" bit when the sub-buffer memory <NUM> is not in the full occupancy state but is in a partial occupancy state. According to an embodiment, the buffer allocation checker circuit <NUM> may also respond with a specific value of previously allocated buffer capacity of the sub-buffer memory <NUM>. In this case, a signal that the buffer allocation checker circuit <NUM> responds with the buffer allocation handling circuit <NUM> may include a plurality of bits. The buffer allocation handling circuit <NUM> may receive the information on the occupancy state of the sub-buffer memory <NUM> from the buffer allocation checker circuit <NUM>.

When the sub-buffer memory <NUM> is not in the full occupancy state (operation <NUM>, NO), because buffer capacity by which the write operation may be performed remains in the buffer capacity allocated to the sub-buffer memory <NUM>, the buffer memory may be allocated to the sub-buffer memory <NUM> in operation <NUM>. For example, the buffer allocation handling circuit <NUM> may generate a buffer pointer representing a position in which the write operation starts in the sub-buffer memory <NUM>. The host interface circuit <NUM> may receive the buffer pointer through the command queue management circuit <NUM> and may control the write operation to be performed from the address of the sub-buffer memory <NUM> represented by the buffer pointer. According to various embodiments, the buffer allocation handling circuit <NUM> may receive information representing that the sub-buffer memory <NUM> is in the full occupancy state from the host interface circuit <NUM> before requesting the buffer allocation checker circuit <NUM> for the information on the occupancy state of the sub-buffer memory <NUM>. For example, the sub-buffer memory <NUM> may transmit an occupancy flag to the host interface circuit <NUM> in response to occupancy of all the buffer memory. The occupancy flag may be a flag signal representing that the buffer memory (the main buffer memory <NUM> or the sub-buffer memory <NUM>) is in the full occupancy state and the buffer memory must be released. The host interface circuit <NUM> may provide the received occupancy flag to the buffer allocation handling circuit <NUM> and may represent that the sub-buffer memory <NUM> is in the full occupancy state.

In operation <NUM>, the buffer allocation handling circuit <NUM> may determine whether the main buffer memory <NUM> is currently in a full occupancy state. In some embodiments, the full occupancy state may refer to a state in which all the buffer capacity allocated to the main buffer memory <NUM> is used. In some embodiments, the full occupancy state may refer to a state in which a write operation is previously performed by the size of the buffer memory allocated to the main buffer memory <NUM>. The buffer allocation handling circuit <NUM> may request the buffer allocation checker circuit <NUM> for information on an occupancy state of the main buffer memory <NUM>. The buffer allocation checker circuit <NUM> may monitor the size of previously allocated buffer memory whenever the buffer memory is allocated to the main buffer memory <NUM>. Therefore, when the size of the buffer memory previously allocated to the main buffer memory <NUM> is equal to the buffer capacity of the main buffer memory <NUM>, the buffer allocation checker circuit <NUM> may determine that the main buffer memory <NUM> is in the full occupancy state. According to an embodiment, the buffer allocation checker circuit <NUM> may respond with only whether the main buffer memory <NUM> is in the full occupancy state in response to the request for the information on the occupancy state of the main buffer memory <NUM> from the buffer allocation handling circuit <NUM>. For example, the buffer allocation checker circuit <NUM> may respond with one "logic high" bit when the main buffer memory <NUM> is in the full occupancy state and may respond with one "logic low" bit when the main buffer memory <NUM> is not in the full occupancy state but is in a partial occupancy state. According to another embodiment, the buffer allocation checker circuit <NUM> may also respond with a specific value of previously allocated buffer capacity of the main buffer memory <NUM>. In this case, a signal that the buffer allocation checker circuit <NUM> responds with the buffer allocation handling circuit <NUM> may include a plurality of bits. When the main buffer memory <NUM> is not in the full occupancy state (operation <NUM>, NO), the buffer allocation handling circuit <NUM> may allocate the buffer memory to the main buffer memory <NUM> in operation <NUM>. For example, the buffer allocation handling circuit <NUM> may generate a buffer pointer representing a position in which the write operation starts in the main buffer memory <NUM>. The host interface circuit <NUM> may receive the buffer pointer through the command queue management circuit <NUM> and may control the write operation to be performed from the address of the main buffer memory <NUM> represented by the buffer pointer. According to various embodiments, the buffer allocation handling circuit <NUM> may receive information representing that the main buffer memory <NUM> is in the full occupancy state from the host interface circuit <NUM> before requesting the buffer allocation checker circuit <NUM> for the information on the occupancy state of the main buffer memory <NUM>. For example, the main buffer memory <NUM> may transmit an occupancy flag to the host interface circuit <NUM> in response to occupancy of all the buffer memory. The occupancy flag may be a flag signal representing that the buffer memory (the main buffer memory <NUM> or the sub-buffer memory <NUM>) is in the full occupancy state and the buffer memory must be released. The host interface circuit <NUM> may provide the received occupancy flag to the buffer allocation handling circuit <NUM> and may represent that the main buffer memory <NUM> is in the full occupancy state.

When the main buffer memory <NUM> is in the full occupancy state (operation <NUM>, YES), in operation <NUM>, the buffer allocation handling circuit <NUM> may delay a command until the main buffer memory <NUM> is released. For example, in operation <NUM>, the main buffer memory <NUM> may be determined to be in the full occupancy state. In other words, because the main buffer memory <NUM> is in the full occupancy state in operation <NUM>, there is no free space for allocating a buffer in the main buffer memory <NUM>. The buffer allocation handling circuit <NUM> may delay a command in the command queue management circuit <NUM> until the main buffer memory <NUM> is released. According to an embodiment, the buffer allocation handling circuit <NUM> may delay the command by a predefined time. The pre-defined time may be longer than an average time spent on transiting the main buffer memory <NUM> from a non-occupancy state to the full occupancy state and releasing the main buffer memory <NUM>. According to an embodiment, the processor <NUM> may delay the command by the predefined time and may allocate the delayed command to the main buffer memory <NUM> to improve the performance of the memory system <NUM>. The main buffer memory <NUM> is implemented in the chip of the memory controller <NUM>, and has a processing speed higher than that of the sub-buffer memory <NUM>. Therefore, when the buffer to be allocated to the main buffer memory <NUM> is allocated to the sub-buffer memory <NUM> only because the main buffer memory <NUM> is in the full occupancy state, the performance of the memory system <NUM> may deteriorate. The performance of the memory system <NUM> may improve when the buffer memory is allocated to the main buffer memory <NUM> even though the commands in the command queue management circuit <NUM> are delayed by a predefined time, when considering deterioration of the performance of the memory system <NUM> including a physical signal delay occurring by allocating the buffer memory to the sub-buffer memory <NUM> outside the chip of the memory controller <NUM> and processing delay occurring by the sub-buffer memory <NUM> with a low processing speed.

In operation <NUM>, the buffer allocation handling circuit <NUM> may determine whether the main buffer memory <NUM> is currently in a full occupancy state. The buffer allocation handling circuit <NUM> may request the buffer allocation confirmation circuit <NUM> for the information on the occupancy state of the main buffer memory <NUM> again in response to the lapse of the predefined time. When the main buffer memory <NUM> is released for the predefined time, the main buffer memory <NUM> may not be in the full occupancy state. When the main buffer memory <NUM> is not in the full occupancy state (operation <NUM>, NO), the buffer allocation handling circuit <NUM> may allocate the buffer memory to the main buffer memory <NUM> in operation <NUM>. For example, the buffer allocation handling circuit <NUM> may generate the buffer pointer representing the position in which the write operation starts in the main buffer memory <NUM>. The host interface circuit <NUM> may receive the buffer pointer through the command queue management circuit <NUM> and may control the write operation to be performed from the address of the main buffer memory <NUM> represented by the buffer pointer. In one embodiment, the buffer allocation handling circuit <NUM> may receive a flag representing that the main buffer memory <NUM> is fully occupied, instruct the command queue management circuit <NUM> to standby for a predefined time based on the flag, and after the predefined time has elapsed and the flag has not been subsequently received, allocate a buffer to the main buffer memory <NUM>.

According to another embodiment, after the predefined time has elapsed in operation <NUM>, the main buffer memory <NUM> may still be in the full occupancy state (operation <NUM>, YES). In this case, the buffer allocation handling circuit <NUM> may skip performing the write operation on the main buffer memory <NUM>, and may perform operation <NUM> of performing the write operation on the sub-buffer memory <NUM>.

<FIG> is a flowchart illustrating an operation of the processor <NUM> according to an embodiment.

Referring to <FIG>, in operation <NUM>, the processor <NUM> may set the operation mode of the memory controller <NUM> as the first operation mode. The processor <NUM> may set the first operation mode first during an initial operation of a process of allocating a buffer. In other words, the processor <NUM> may deactivate the buffer allocation checker circuit <NUM> by transmitting the disable signal to the buffer allocation checker circuit <NUM>.

In operation <NUM>, the processor <NUM> may transmit the control signal to the special function register <NUM>. According to an embodiment, the control signal may be for selecting one of the plurality of allocation ratios stored in the special function register <NUM>. For example, in some embodiments, the processor <NUM> may set the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> as <NUM>:<NUM> by providing the control signal to the special function register <NUM>. In some embodiments, the processor <NUM> may directly transmit the allocation ratio information directly representing the allocation ratio to the special function register <NUM>.

In operation <NUM>, the processor <NUM> may request a performance check at each time interval. The time interval may be preset. For example, the processor <NUM> may transmit the performance check request to the special function register <NUM> at each time interval. The special function register <NUM> may provide the performance result value received from the monitoring circuit <NUM> and stored therein to the processor <NUM>. According to another embodiment, the processor <NUM> may directly request the monitoring circuit <NUM> for a performance check at each preset time interval.

In operation <NUM>, the processor <NUM> may determine whether the number of occupancy flags of the sub-buffer memory <NUM> received from the monitoring circuit <NUM> for a unit time is greater than a threshold value. The occupancy flag may be for representing that the sub-buffer memory <NUM> is in the full occupancy state.

When the number of occupancy flags is greater than the threshold value (operation <NUM>, YES), in operation <NUM>, the processor <NUM> may change the operation mode of the memory controller <NUM> from the first operation mode to the second operation mode. When the number of occupancy flags received for the unit time is greater than the threshold value, it may mean that the occupancy flags are frequently generated because commands are not rapidly processed before the allocation ratio fixed to a current preset value makes the sub-buffer memory <NUM> in the full occupancy state. Therefore, the processor <NUM> may change the first operation mode in which the memory controller <NUM> operates in the fixed allocation ratio to the second operation mode.

In operation <NUM>, the processor <NUM> may variably set the allocation ratio in accordance with the monitoring result value. In response to the change of the operation mode of the memory controller <NUM> from the first operation mode to the second operation mode, the buffer allocation checker circuit <NUM> may be activated. The buffer allocation checker circuit <NUM> may monitor a remaining buffer size of the main buffer memory <NUM> and the sub-buffer memory <NUM> in real time. The buffer allocation checker circuit <NUM> may control the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> based on the monitoring result value and the remaining buffer size. For example, when the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> is <NUM>:<NUM> in the first operation mode, the buffer allocation checker circuit <NUM> may control the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> to be <NUM>:<NUM> in order to improve the performance of the memory system <NUM> in the second mode.

According to various embodiments, when the monitoring result value is less than target performance in the second operation mode, the processor <NUM> may change the allocation ratio. For example, when the monitoring result value is less than the target performance, the processor <NUM> may set the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> as <NUM>:<NUM>.

<FIG> is a flowchart illustrating an operation of the buffer allocation checker circuit <NUM> according to an embodiment.

Referring to <FIG>, in operation <NUM>, the buffer allocation checker circuit <NUM> may determine the first ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> based on a type of a command. For example, the buffer allocation checker circuit <NUM> may variably set the first ratio in accordance with the type of the command in the command queue management circuit <NUM>. For example, when the type of the command corresponds to the sequential write command, the buffer allocation checker circuit <NUM> may set the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> as <NUM>:<NUM>. As another example, when the type of the command corresponds to a random write command, the buffer allocation checker circuit <NUM> may set the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> as <NUM>:<NUM> because a minimum performance request may be satisfied although a large amount of buffer capacity is allocated to the sub-buffer memory <NUM>.

In operation <NUM>, the buffer allocation checker circuit <NUM> may receive the performance check request and may obtain the monitoring result value. For example, the processor <NUM> may transmit the performance check request to the buffer allocation checker circuit <NUM> at each time interval. The time interval may be predefined or preset. The buffer allocation checker circuit <NUM> may receive the performance result value from the monitoring circuit <NUM> in response to the performance check request.

In operation <NUM>, the buffer allocation checker circuit <NUM> may determine whether the performance result value is less than the threshold value. The threshold value may vary in depending on the type of the command in the command queue management circuit <NUM>. The buffer allocation checker circuit <NUM> may perform operation <NUM> when the performance result value is less than the threshold value (operation <NUM>, YES). Otherwise, when the performance result value is equal to or greater than the threshold value (operation <NUM>, NO), the process returns to operation <NUM>.

In operation <NUM>, the buffer allocation checker circuit <NUM> may determine the remaining buffer size. The buffer allocation checker circuit <NUM> may record the buffer allocation whenever a buffer is allocated to the main buffer memory <NUM> and the sub-buffer memory <NUM> to monitor the remaining buffer size of the main buffer memory <NUM> and sub-buffer memory <NUM>.

In operation <NUM>, the buffer allocation checker circuit <NUM> may change the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> from the first ratio to the second ratio. For example, when the first ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> is <NUM>:<NUM>, and the remaining buffer size of the sub-buffer memory <NUM> is small, the buffer allocation checker circuit <NUM> may variably increase a ratio of the main buffer memory <NUM>. For example, the buffer allocation checker circuit <NUM> may variably change the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> to <NUM>:<NUM> or <NUM>:<NUM>.

<FIG> is a signal exchange diagram corresponding to a first operation mode of a memory system according to an embodiment.

Referring to <FIG>, the processor <NUM> may provide a control signal instructing the buffer allocation checker circuit <NUM> to be deactivated to the buffer allocation circuit <NUM>. That is, the buffer allocation circuit <NUM> may allocate the main buffer memory <NUM> and the sub-buffer memory <NUM> in accordance with the fixed allocation ratio.

The host interface circuit <NUM> may provide a buffer allocation request to the buffer allocation circuit <NUM>. The host interface circuit <NUM> may receive a command from the host HOST and may request the buffer allocation circuit <NUM> to allocate buffer memory for executing the command.

The buffer allocation circuit <NUM> may determine that the operation mode is the first operation mode. Specifically, in some embodiments, the buffer allocation circuit <NUM> may determine that the current operation mode is the first operation mode in response to the inactive state of the buffer allocation circuit <NUM>. In some embodiments, the buffer allocation circuit <NUM> may request the special function register <NUM> to return the operation mode, and may determine the current operation mode based on a return value.

The buffer allocation circuit <NUM> may allocate buffer memory in a predefined allocation ratio. The buffer allocation circuit <NUM> may obtain the allocation ratio information through the special function register <NUM> in response to the buffer allocation request received from the host interface circuit <NUM>. The special function register <NUM> may receive information on the fixed allocation ratio from the processor <NUM> and may store the received information therein.

The buffer allocation circuit <NUM> may generate a buffer pointer for each of the main buffer memory <NUM> and the sub-buffer memory <NUM>, and may respond to the host interface circuit <NUM>. For example, the buffer allocation circuit <NUM> may generate a first buffer pointer designated as a buffer region of the main buffer memory <NUM> and representing a position in which the write operation starts. The buffer allocation circuit <NUM> may generate a second buffer pointer designated as a buffer region of the sub-buffer memory <NUM> and representing a position in which the write operation starts. The first buffer pointer and the second buffer pointer may be generated by the buffer allocation handling circuit <NUM> in the buffer allocation circuit <NUM>. The buffer allocation circuit <NUM> may provide the first buffer pointer and the second buffer pointer to the host interface circuit <NUM>.

The host interface circuit <NUM> may perform the write operation on each of the main buffer memory <NUM> and the sub-buffer memory <NUM> based on the first and second buffer pointers received from the buffer allocation circuit <NUM>. In some embodiments, the write operation for the main buffer memory <NUM> may be performed in parallel with the write operation for the sub-buffer memory <NUM>. For example, when the sequential write command is received from the host HOST, at least some of data of the sequential write command is programmed to the main buffer memory <NUM>, and the remaining data may be programmed to the sub-buffer memory <NUM>.

The processor <NUM> may transmit the performance check request to the buffer allocation circuit <NUM>. The performance check request may be transmitted from the processor <NUM> to the buffer allocation circuit <NUM> at each time interval. The time interval may be predefined or preset. Because the buffer allocation checker circuit <NUM> is deactivated in the first operation mode, the processor <NUM> may transmit the performance check request to the buffer allocation circuit <NUM> at each time interval in the first operation mode.

The buffer allocation circuit <NUM> may provide the monitoring result value to the processor <NUM> in response to the performance check request. Specifically, the monitoring circuit <NUM> in the buffer allocation circuit <NUM> may monitor and store a size of buffer memory allocated per unit time. For example, the monitoring circuit <NUM> may monitor the size of the buffer memory allocated per unit time and may store the monitoring result value in the special function register <NUM>. The buffer allocation circuit <NUM> may respond with the monitoring result value through the special function register <NUM> in response to the performance check request received from the processor <NUM>.

The processor <NUM> may receive the monitoring result value from the buffer allocation circuit <NUM>, and when the monitoring result value is less than the threshold value, may provide the changed allocation ratio information to the buffer allocation circuit <NUM>. For example, when the initially set allocation ratio is <NUM>:<NUM> and the sequential write command is input, the monitoring result value may be lowered to be less than the threshold value. Therefore, the processor <NUM> may provide the buffer allocation circuit <NUM> with the changed allocation ratio information representing the allocation ratio of <NUM>:<NUM> to improve performance.

The host interface circuit <NUM> may receive an occupancy flag from the main buffer memory <NUM>. The occupancy flag may be for representing that the main buffer memory <NUM> is in the full occupancy state. The host interface circuit <NUM> may transmit a buffer release request to the buffer allocation circuit <NUM> in order to release the main buffer memory <NUM>. The buffer allocation circuit <NUM> may release the buffer allocation of the main buffer memory <NUM> and may transmit a release completion response to the host interface circuit <NUM>. The host interface circuit <NUM> may transmit the buffer allocation request again based on the release completion response. The buffer allocation circuit <NUM> may generate a buffer pointer and may provide the generated buffer pointer to the host interface circuit <NUM>. In some embodiments, the buffer pointer may correspond to the first buffer pointer for the main buffer memory <NUM>. The host interface circuit <NUM> may program data again based on the buffer pointer.

The host interface circuit <NUM> may receive an occupancy flag from the sub-buffer memory <NUM>. The occupancy flag may be for representing that the sub-buffer memory <NUM> is in the full occupancy state. The host interface circuit <NUM> may transmit a buffer release request to the buffer allocation circuit <NUM> in order to release the sub-buffer memory <NUM>. The buffer allocation circuit <NUM> may release the buffer allocation of the sub-buffer memory <NUM> and may transmit a release completion response to the host interface circuit <NUM>. The host interface circuit <NUM> may transmit the buffer allocation request again based on the release completion response. The buffer allocation circuit <NUM> may generate a buffer pointer and may provide the generated buffer pointer to the host interface circuit <NUM>. In some embodiments, the buffer pointer may correspond to the second buffer pointer for the sub-buffer memory <NUM>. The host interface circuit <NUM> may program data again based on the buffer pointer.

<FIG> is a signal exchange diagram corresponding to a second operation mode of a memory system according to an embodiment.

Referring to <FIG>, the processor <NUM> may provide a control signal instructing the buffer allocation checker circuit <NUM> to be activated to the buffer allocation circuit <NUM>. That is, the buffer allocation circuit <NUM> may allocate the main buffer memory <NUM> and the sub-buffer memory <NUM> in accordance with a variable allocation ratio without intervention of the processor <NUM>.

The buffer allocation circuit <NUM> may determine that the operation mode is the second operation mode. Specifically, in some embodiments, the buffer allocation circuit <NUM> may determine that the current operation mode is the second operation mode in response to the active state of the buffer allocation circuit <NUM>. In some embodiments, the buffer allocation circuit <NUM> may request the special function register <NUM> to return the operation mode, and may determine the current operation mode based on a return value.

The buffer allocation circuit <NUM> may allocate buffer memory in an allocation ratio based on a type of a loaded command. The buffer allocation circuit <NUM> may determine the type of the command in the command queue management circuit <NUM> in response to the buffer allocation request received from the host interface circuit <NUM>. For example, when the sequential write command is to be processed by the command queue management circuit <NUM>, the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> may be <NUM>:<NUM>. As another example, when one of the random write command, the sequential read command, and the random read command is to be processed by the command queue management circuit <NUM>, the allocation ratio between the main buffer memory <NUM> and the sub-buffer memory <NUM> may be <NUM>:<NUM>.

The buffer allocation circuit <NUM> may track performance through the monitoring circuit <NUM>. That is, the buffer allocation circuit <NUM> may control the allocation ratio when the monitoring result value is less than the threshold value. For example, when the size of the buffer memory allocated per unit time is less than the threshold value while executing the random write command, the ratio of the main buffer memory <NUM> may be increased from the set allocation ratio of <NUM>:<NUM>.

<FIG> is a block diagram illustrating an example of applying a memory system to a solid state drive (SSD) system <NUM> according to embodiments.

Claim 1:
A memory system (<NUM>) comprising:
a memory controller (<NUM>) configured to control a memory device (<NUM>); and
a sub-buffer memory (<NUM>) arranged outside the memory controller (<NUM>),
wherein the memory controller (<NUM>) comprises:
a processor (<NUM>) configured to control a memory operation for the memory device (<NUM>);
a main buffer memory (<NUM>) that is different from the sub-buffer memory (<NUM>) and arranged in the memory controller (<NUM>); and
a buffer allocation circuit (<NUM>) configured to control an allocation ratio between the sub-buffer memory (<NUM>) and the main buffer memory (<NUM>),
wherein the processor (<NUM>) is configured to set an operation mode of the buffer allocation circuit (<NUM>) and the buffer allocation circuit (<NUM>) is configured to control the allocation ratio based on the operation mode;
wherein the main buffer memory (<NUM>) is a static random access memory, SRAM, and
wherein the sub-buffer memory (<NUM>) is a dynamic random access memory, DRAM.