Patent Description:
Memory devices incorporating variable resistance materials may be used in a wide range of electronic devices, such as computers, digital cameras, cellular telephones, personal digital assistants, etc. Electrical resistance of such variable resistance materials can change between a plurality of resistance states in response to electrical signals, such as, for example voltage or current pulses. In some variable resistance memory devices, sometimes referred to as unipolar memory devices, the electrical resistance of the memory cells can change in response to electrical signals having one polarity. In some other memory devices, sometimes referred to as bipolar memory devices, the electrical resistance of memory cells can change in response to electrical signals having one or two opposite polarities. For example, in a bipolar memory device, the resistance of a memory cell can change in one direction (e.g. from a high resistance to a low resistance) in response to a first electrical signal having a first polarity, and change in an opposite direction (for example, from the low resistance to the high resistance) in response to a second electrical signal having a second polarity opposite to the first polarity. Peripheral circuitry configured to support operation of bipolar memory devices can be larger and more complex compared to unipolar memory devices, due to a need to support current and/or voltage in opposite polarities. Thus, there is a need for apparatuses and methods for efficient accessing of the memory cells in opposite polarities. <CIT> describes an integrated circuit memory device including an array of non-volatile memory cells having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. <CIT> describes an apparatus having first conductive lines, second conductive lines, a memory array including memory cells, and a module configured to cause a first current and a second current to flow through a selected memory cell during an operation of storing information in the selected memory cell. <CIT> describes a bidirectional memory cell including an ovonic threshold switch and a bidirectional memory element.

According to a first aspect, there is provided an apparatus as recited in claim <NUM>.

According to a second aspect, there is provided a method as recited in claim <NUM>.

Only embodiments comprising all the features of independent claim <NUM> or of independent claim <NUM> fall under the scope of protection of the present invention.

Claimed subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, both as to organization and/or method of operation, together with objects, features, and/or advantages thereof, it may best be understood by reference to the following detailed description if read with the accompanying drawings in which:.

Devices, for example memory devices, incorporating materials that change resistance in operation may be found in a wide range of electronic devices, for example, computers, digital cameras, cellular telephones, personal digital assistants, etc. Such memory devices, sometimes referred to as resistive random access memory (RRAM) devices, can include an array of memory cells, which can be arranged in a cross-point memory array. A cross-point memory array includes columns and rows and a plurality of memory cells disposed at intersection of the columns and rows. In RRAM devices including a cross-point memory array, the resistance of memory cells can change in response to an electrical signal, such as, for example a voltage or a current signal.

In some RRAM devices, sometimes referred to as unipolar memory devices, the electrical resistance of the memory cells can change in response to electrical signals having one polarity. For example, in a unipolar RRAM device, the resistance of a memory cell can change in one direction (e.g. from a high resistance to a low resistance) in response to a first electrical signal having a first polarity, and change in an opposite direction (for example, from the low resistance to the high resistance) in response to a second electrical signal having the same polarity as the first polarity. In some other RRAM devices, sometimes referred to as bipolar memory devices, the electrical resistance of memory cells can change in response to electrical signals having one or two opposite polarities. For example, in a bipolar RRAM device, the resistance of a memory cell can change in one direction (e.g. from a high resistance to a low resistance) in response to a first electrical signal having a first polarity, and change in an opposite direction (for example, from the low resistance to the high resistance) in response to a second electrical signal having a second polarity opposite to the first polarity.

As used herein, the electrical signals that are applied to the memory cells to either write or read are referred to as access signals. Peripheral circuitry configured to support operations of bipolar RRAM devices in opposite polarities can be larger and more complex compared to unipolar RRAM devices, due to a need to support current and/or voltage in opposite polarities. This can be due to, for example, a need to support current and/or voltage for accessing the memory cells in opposite polarities.

While embodiments are described herein with respect to RRAM devices, in particular to RRAM devices, the embodiments can also have application outside the memory array context, for example, switches, antifuses, etc. Similarly, while embodiments are described with respect to memory cells incorporating Ovonic Threshold Switch (OTS) and/or chalcogenide materials, the principles and advantages of the techniques and structures taught herein may be useful for other materials.

<FIG> depicts a memory cell <NUM> in a cross-point memory array according to some embodiments. The memory cell <NUM> in <FIG> can change between first and second resistance states in response to electrical signals having same or opposite polarities. That is, the memory cell <NUM> can be a bipolar or a nonpolar memory cell.

While only one memory cell <NUM> is depicted in <FIG> for clarity, it will be appreciated that there can be a plurality of memory cells <NUM> in a cross-point memory array having a plurality of column lines <NUM> and a plurality of row lines <NUM>. In the illustrated embodiment, the memory cell <NUM> includes a storage element <NUM> and a selector element <NUM> that are configured to be electrically accessed through a column line <NUM>, which can be a bit line, and a row line <NUM>, which can be a word line. The memory cell <NUM> is in a stack configuration and can further include a first electrode <NUM> connecting the column line <NUM> and the storage element <NUM>, a middle electrode <NUM> connecting the storage element <NUM> and the selector element <NUM>, and a second electrode <NUM> connecting the selector element <NUM> and the row line <NUM>.

In some embodiments, one or both of the selector element <NUM> and the storage element <NUM> can comprise chalcogenide materials. When both the selector element <NUM> and the storage element <NUM> both comprise chalcogenide materials, the storage element <NUM> can comprise a chalcogenide material that can undergo a phase change that is stable and nonvolatile at room temperature. On the other hand, the selector element <NUM> can comprise a chalcogenide material that does not undergo a similar stable and nonvolatile phase change.

Examples of a phase change-based storage element <NUM> that can be included in bipolar or unipolar RRAM devices include a phase change material that includes chalcogenide compositions such as an alloy including at least two of the elements within the indium(In)-antimony(Sb)-tellurium(Te) (IST) alloy system, for example, In<NUM>Sb<NUM>Te<NUM>, In<NUM>Sb<NUM>Te<NUM>, In<NUM>Sb<NUM>Te<NUM>, etc., an alloy including at least two of the elements within the germanium(Ge)-antimony(Sb)-tellurium(Te) (GST) alloy system, for example, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, Ge<NUM>Sb<NUM>Te<NUM>, etc., among other chalcogenide alloy systems. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. Other chalcogenide alloy systems that can be used in phase change storage nodes include Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, In-Ge-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn-Pt, for example.

Other examples of the storage element <NUM> that can be included in unipolar or bipolar memory RRAM devices include a metal oxide-based memory storage element (for example, NiO, HfO<NUM>, ZrO<NUM>, Cu<NUM>O, TaO<NUM>, Ta<NUM>O<NUM>, TiO<NUM>, SiO<NUM>, Al<NUM>O<NUM>), a conductive bridge random access memory (CBRAM) storage element (for example, metal-doped chalcogenide), and/or a spin transfer torque random access memory (STT-RAM) storage element, among other types of storage elements.

Examples of the selector element <NUM> that can be included in an RRAM device include a two-terminal selector comprising a chalcogenide material, which can sometimes be referred to as an Ovonic Threshold Switch (OTS). An OTS may include a chalcogenide composition including any one of the chalcogenide alloy systems described above for the storage element <NUM>. In addition, the selector element <NUM> may further comprise an element such as As to suppress crystallization. Examples of OTS materials include Te-As-Ge-Si, Ge-Te-Pb, Ge-Se-Te, Al-As-Te, Se-As-Ge-Si, Se-As-Ge-C, Se-Te-Ge-Si, Ge-Sb-Te-Se, Ge-Bi-Te-Se, Ge-As-Sb-Se, Ge-As-Bi-Te, and Ge-As-Bi-Se, among others.

Still referring to <FIG>, the memory cell <NUM> may be in a resistance state that may be a relatively high resistance state (HRS), also known as the RESET state, or a relatively low resistance state (LRS), also known as the SET state. The RESET and SET states can have a resistance ratio between, for example, two and <NUM> million.

As used herein, a program access operation, which for an RRAM device can also be referred to as a RESET access operation, changes the memory cell from a SET state to an a RESET state. On the other hand, an erase operation, which for an RRAM device can also be referred to as a SET access operation, changes the memory cell from a RESET state to a SET state. However, the terms "program" and "erase" as they relate to RESET and SET access operations may be used interchangeably to mean the opposite.

In addition, while SET and RESET states may herein be used to refer to states of a memory cell (which may include storage and/or selector elements) as a whole, it will be understood that the distinction between SET and RESET states of the memory cell can originate from the resistance difference of the storage element.

<FIG> is a chart illustrating current-voltage (I-V) curves <NUM> of a memory cell undergoing SET and RESET transitions according to some embodiments. The x-axis represents voltage applied across a phase change memory cell and the y-axis represents absolute value of the current displayed in log scale. The I-V curves <NUM> can correspond to that of a bipolar memory cell, in which a SET operation can be performed in a first polarity (positive) and a RESET operation can be performed in a second polarity (negative). In addition, the I-V curves <NUM> can correspond to the memory cell similar to memory cell <NUM> of <FIG>, where at least one of the storage element <NUM> or the selector element <NUM> includes a chalcogenide material. When the memory cell includes a chalcogenide material, switching events (i.e., SET and/or RESET transitions) can include a thresholding event, which can be accompanied by a snap-back event, as described in more detail below.

A SET transition I-V curve <NUM> represents the memory cell undergoing a transition from a RESET state to a SET state, while a RESET transition I-V curve <NUM> represents a phase change memory cell undergoing a transition from a SET state to a RESET state. Although not captured in the IV curve, the transition from SET to RESET or RESET to SET state may involve a duration component or a waveform of voltage or current over time.

The SET transition I-V curve <NUM> includes a RESET state subthreshold region <NUM> characterized by a relatively slow-varying current versus voltage, followed by a SET transition threshold "nose" region <NUM> at about a positive threshold voltage of the RESET state (VTH RESET), around which point the SET transition I-V curve <NUM> undergoes a reversal of slope, followed by a SET transition snap back region <NUM> characterized by a rapid reduction in the voltage across the memory cell, followed by a SET transition hold region <NUM> around a hold voltage VH, followed by a SET access region <NUM>, in which either a stable current or voltage can be measured.

Still referring to <FIG>, the RESET transition I-V curve <NUM> includes a SET state subthreshold region <NUM> characterized by a relatively slow-varying current versus voltage, followed by a RESET transition threshold "nose" region <NUM> at about a negative threshold voltage of the SET state (VTH SET), around which point the RESET transition I-V curve <NUM> undergoes a reversal of slope, followed by a RESET transition snap back region <NUM> characterized by a rapid reduction in the voltage across the memory cell, followed by a RESET transition hold region <NUM> around a hold voltage VH, followed by a RESET cell access region <NUM>, in which either a stable current or voltage can be measured.

It will be appreciated that the RESET state has a higher threshold voltage VTH RESET compared to the VTH SET, because the contribution to the voltage drop from the storage element can be greater in the RESET state compared to the SET state. In addition, it will be appreciated that the RESET cell access region <NUM> has a higher level of voltage drop across the memory cell compared to the SET cell access region <NUM> for similar amount of current flowing (e.g., passing) through the memory cell, because the contribution to the voltage drop from the storage element can be greater in the RESET state compared to the SET state.

In the illustrated embodiment of <FIG>, both SET and RESET transition I-V curves <NUM> and <NUM> have snap back regions <NUM> and <NUM> characterized by rapid reduction in voltages across the memory cell. A snap-back event can be accompanied by a discharge current that flows through the memory cell. The amount discharge current can depend on the capacitance and the resistance of the column line and the row line connected to the memory cell undergoing the snap-back effect. Depending on the values of these capacitances and the resistances, the amount of current and/or the duration of the snap back event can be sufficient to induce a partial or a full phase change in a phase change memory under some circumstances.

In some embodiments, once thresholded, a memory cell such as the memory cell <NUM> of <FIG> can be maintained in the thresholded state represented by SET and RESET cell access regions <NUM> and <NUM> in <FIG>, so long as a current flowing through the memory cell can be maintained above a certain minimum level, which is sometimes referred to as a hold current (IH). On the other hand, when the current flowing through the memory cell is allowed to fall below IH, or "released," the memory cell may be extinguished, i.e., revert back to the unthresholded state. In some embodiments, when the memory cell is released, the threshold voltage (VTH RESET or VTH SET) may not return to the threshold voltage the memory cell had prior to being thresholded. Instead, the threshold voltage may recover gradually, and be characterized by a recovery time, as illustrated below in <FIG>.

<FIG> is a chart illustrating an example threshold recovery curve <NUM> of a memory cell whose magnitude of the threshold voltage depends on a time lapse (tR) from the moment memory cell is released from a thresholded state. In <FIG>, the y-axis represents the threshold voltage VTH and the x-axis represents the time lapse from being released from a thresholded state at t=<NUM>. The threshold voltage prior to being thresholded is represented as VTH,<NUM>. As illustrated, after the memory cell is released from the thresholded state at t=<NUM>, upon passage of the time lapse tR, the threshold voltage recovers to VTH,<NUM>, or nearly to VTH,<NUM>. In some embodiments, the magnitude of the threshold voltage recovers at least <NUM>% of a previous threshold voltage within about <NUM> microseconds, or within about <NUM> nanoseconds, or within about <NUM> nanoseconds.

<FIG> is a schematic circuit diagram of a memory apparatus <NUM> according to some embodiments. The memory apparatus <NUM> includes a memory array <NUM> which comprises a plurality of columns <NUM> and a plurality of rows <NUM>. The memory array <NUM> additionally comprises a plurality of memory cells <NUM> at intersections between columns <NUM> and rows <NUM>. The memory cells <NUM> can include, for example, a memory cell <NUM> described above with respect to <FIG>. In some implementations, the columns <NUM> may also be referred to as bit lines or digit lines, and rows <NUM> may also be referred to as word lines. At least some of the memory cells <NUM> can be accessed by application of a suitable electrical signal, including, for example, voltage, current or electric field, among others. The memory cells <NUM> may have an address defined by the row <NUM> and the column <NUM> coupled to the memory cell <NUM>.

The memory apparatus <NUM> additionally includes, according to some embodiments, a column selection circuit (COL SEL) <NUM> electrically connected to the memory array <NUM> though the columns <NUM>, and a row selection circuit (ROW SEL) <NUM> electrically connected to the memory array <NUM> through the rows <NUM>. In some embodiments, during an access operation, at least some of the rows <NUM> and at least some of the columns <NUM> are configured to be activated individually, such that each of the memory cells <NUM> can be selected in a bit-addressable manner.

The memory apparatus <NUM> additionally includes, according to some embodiments, a column deselection circuit (COL DESEL) <NUM> electrically connected to the memory array <NUM> though the COL SEL <NUM> and further through columns <NUM>. The memory apparatus <NUM> additionally includes a row deselection circuit (ROW DESEL) <NUM> electrically connected to the memory array <NUM> through the ROW SEL <NUM> and further through rows <NUM>. In some embodiments, for example during a selection phase (described more in detail with respect to <FIG>) of an access operation, one or more columns <NUM> to be selected can be activated via respective COL SEL <NUM> connected to the columns, and one or more rows <NUM> to be selected can be activated via respective ROW SEL <NUM>. In some embodiments, for example during an access phase (described more in detail with respect to <FIG>) of an access operation, one or more columns <NUM> to be selected can be activated via the COL DESEL <NUM> connected to the columns, and one or more rows <NUM> to be selected can be activated via the ROW DESEL <NUM> connected to the rows <NUM>. In some embodiments, during the selection phase or the access phase of an access operation, one or more columns <NUM> to be selected as well as one or more unselected columns <NUM> can be activated via the COL DESEL <NUM>, and one or more rows <NUM> to be selected as well as one or more unselected rows <NUM> can be activated via the ROW DESEL <NUM>.

While in <FIG>, for illustrative purposes only, the COL DESEL <NUM> is connected to a specific number of columns <NUM> and the ROW DESEL <NUM> is connected a specific number of rows <NUM>, in various embodiments, any suitable number of columns <NUM> can be connected to the COL DESEL <NUM>, and any suitable number of rows <NUM> can be connected to the ROW DESEL <NUM>. In addition, while in <FIG>, for illustrative purposes only, a COL SEL <NUM> is connected to each column <NUM> and a ROW SEL <NUM> is connected each row <NUM>, in various embodiments, any suitable number of columns <NUM> can be connected to a COL SEL <NUM>, and any suitable number of rows <NUM> can be connected to ROW SEL <NUM>.

Still referring to <FIG>, according to some embodiments, the memory apparatus <NUM> additionally includes a column decoder <NUM> electrically connected to the columns <NUM> through the COL SEL <NUM> and the COL DESEL <NUM>, and additionally includes a row decoder <NUM> electrically connected to the rows <NUM> through the ROW SEL <NUM> and the ROW DESEL <NUM>. In operation, for example, a physical address of a memory cell <NUM> to be accessed may be specified by a memory cell address, which may be included in a memory access command. The memory cell address can include a column address and/or a row address corresponding to the column and the row corresponding to a target memory cell on which an access operation is to be performed. Upon receiving the memory cell address, the column decoder <NUM> is configured to decode a column address and select or deselect the column by activating either or both the COL SEL <NUM> or/and the COL DESEL <NUM>. Similarly, upon receiving the memory cell address, the row decoder is configured to decode a row address and select or deselect the row by activating either or both the ROW SEL <NUM> or/and the ROW DESEL <NUM>.

Still referring to <FIG>, in some embodiments, the memory apparatus <NUM> further includes a memory controller <NUM>, which may be configured to control the various access operations performed on the memory array <NUM>, including RESET, SET and READ access operations. In operation, the memory controller <NUM> can be configured to receive signals from a processor to access one or more memory cells <NUM> in the memory array <NUM>. The memory controller <NUM> is in turn configured to transmit control signals to the memory array <NUM> through the column decoder <NUM> and the row decoder <NUM>. In some embodiments, the memory controller <NUM> is integrated as part of the memory apparatus <NUM> in a solid-state integrated circuit. In other embodiments, the memory controller <NUM> can be part of a host device.

Still referring to <FIG>, according to some embodiments, the memory cells <NUM> can include a variable resistance memory cell comprising a chalcogenide material, similar to the memory cell <NUM> of <FIG>. It will be understood that, although the memory apparatus <NUM> shows a particular number of cells <NUM>, the memory array <NUM> may contain any suitable number of memory cells <NUM>, and may not have the same number of columns as rows. The memory array <NUM> can contain, for example, at least many millions of memory cells <NUM>.

Still referring to <FIG>, the ROW SEL <NUM> includes a p-type field-effect transistor (PFET) <NUM> and an n-type field-effect transistor (NFET) <NUM>, according to some embodiments. The PFETs and NFETs can correspond to insulated-gate transistors, such as metal-oxide semiconductor field effect transistors (MOSFETs). While the terms "metal" and "oxide" are present in the name of the device, it will be understood that these transistors can have gates made out of materials other than metals, such as polycrystalline silicon, and can have dielectric "oxide" regions made from dielectrics other than silicon oxide, such as from silicon nitride or high-k dielectrics. The gates of the PFETs <NUM> and the NFETs <NUM> may be driven by the row decoder <NUM> through respective row selection lines <NUM>. The drains of the PFETs <NUM> and the drains of the NFETs <NUM> are connected to respective rows <NUM>. Additionally, the sources of the PFETs <NUM> may be coupled to the ROW DESEL <NUM>, while the sources of the NFETs <NUM> may be coupled to a row selection voltage source <NUM>.

Similarly, the COL SEL <NUM> includes a PFET <NUM> and an NFET <NUM>, according to some embodiments. Similar to ROW SEL <NUM>, the gates of the PFETs <NUM> and the NFETs <NUM> may be driven by the column decoder <NUM> through the respective column selection lines <NUM>. The drains of the PFETs <NUM> and the drains of the NFETs <NUM> are connected to the respective columns <NUM>. Additionally, the sources of the PFETs <NUM> may be coupled to a column selection voltage source <NUM>, while the sources of the NFETs <NUM> may be coupled to the COL DESEL <NUM>.

<FIG> is a schematic circuit diagram illustrating a memory device <NUM> in operation, according to some embodiments. The memory device <NUM> comprises similar components as the memory apparatus <NUM> of <FIG>, including a memory array <NUM>. The memory array <NUM> includes a plurality of memory cells under various bias configurations in operation. In operation, a target memory cell (T cell) 154T may be accessed through applying appropriate selection and access biases between a selected column <NUM> and a selected row <NUM>. As used herein, a memory cell such as a memory cell 154A. disposed along the selected row <NUM> and a deselected column 170D is referred to as an A cell. In addition, a memory cell such as a memory cell 154B disposed along the selected column <NUM> and a deselected row 172D is referred to as a B cell. In addition, a memory cell such as a memory cell 154C disposed along a deselected column 170D and a deselected row 172D is referred to as a C cell.

Also similar to <FIG>, the memory device <NUM> additionally includes a column selection circuit (COL SEL) <NUM> electrically connected to the memory array <NUM> though the columns <NUM> and 170D, and a row selection circuit (ROW SEL) <NUM> electrically connected to the memory array <NUM> through rows <NUM> and 172D. The memory device <NUM> additionally includes, according to some embodiments, a column deselection circuit (COL DESEL) <NUM> similar to the COL DESEL <NUM> of <FIG>. COL DESEL <NUM> is electrically connected to the memory array though the COL SEL <NUM> and further through columns <NUM> and 170D. In addition, while not illustrated for clarity, the memory device <NUM> can additionally include a row deselection circuit ROW DESEL similar to the ROW DESEL <NUM> of <FIG>.

Also similar to <FIG>, the COL SEL <NUM> includes a PFET <NUM> and an NFET <NUM>, whose gates are connected to a column decoder (not shown), and ROW SEL <NUM> includes a PFET <NUM> and an NFET <NUM>, whose gates are connected to a row decoder (not shown).

In some embodiments, as illustrated in <FIG>, the COL DESEL <NUM> includes a plurality of switches that may be configured to connect a given column to a suitable voltage source including, for example, a mid-bias column voltage source <NUM> or a reference voltage source (e.g., ground) <NUM>, depending on whether a memory cell connected to the given column is to be biased positively or negatively. In the illustrated embodiment, the switches include a first FET <NUM> and a second FET <NUM>, whose drains are connected to the source of the NFET <NUM> of the COL SEL <NUM>. In addition, the source of the second NFET <NUM> can be further connected to a mid-bias column voltage source <NUM> and the source of the first FET <NUM> may be connected to a reference voltage source, for example, zero volts. In <FIG>, the COL DESEL <NUM> including first and second switches is illustrated as having two FETs <NUM> and <NUM> that are NFETs. However, the embodiment is not so limited and in some other embodiments, one or both of the first and second FETs can be PFETs. In yet other embodiments, the COL DESEL <NUM> can include other suitable switching elements, for example, diodes or similar elements.

It will be appreciated that, while in <FIG>, all columns shown are connected to one COL DESEL <NUM> for illustrative purposes, the memory device <NUM> may include any suitable number of columns that can be connected to a COL DESEL <NUM>. For example, in an embodiment, there may be a COL DESEL <NUM> connected to each column of the memory device <NUM>. In other embodiments, there may be a COL DESEL <NUM> connected to a suitable fraction of the total number of columns of a given unit of an array, such as, for example, a tile, which can include, for example, about <NUM> columns. The number of columns connected to a COL DESET, <NUM>, and thus the number of COL DESEL <NUM> connected to the array can depend, among other things, the area footprint of the COL DESEL <NUM> and the amount of current the COL DESEL <NUM> can be configured to deliver.

In some embodiments, the mid-bias column voltage source <NUM> can be configured to supply a lower voltage to a column <NUM> or 170D through COL SEL <NUM> compared to the column selection voltage source <NUM>. For example, the mid-bias column voltage source <NUM> can be configured to supply between about <NUM>% and <NUM>% of the voltage supplied to columns <NUM> or 170D by the column selection voltage source <NUM>. By way of illustration, in some embodiments, the column selection voltage source <NUM> can be configured to supply a voltage of between about 4V and 8V, for instance about 6V, or between about 3V and 7V, for instance about 5V. In addition, the mid-bias column voltage source <NUM> can be configured to supply a voltage between about 1V and 5V, for instance about 3V, or between about <NUM>. 5V and <NUM>. 5V, for instance about <NUM>.

In addition, it will be appreciated that in some embodiments, although not shown in <FIG> for clarity, the memory device <NUM> can include, instead of or in addition to the COL DESEL <NUM>, a row deselection circuit (ROW DESEL similar to the ROW DESEL <NUM> of <FIG>) electrically connected to the memory array <NUM> through the ROW SEL <NUM> and further through rows <NUM> and <NUM>. In operation, the ROW DESEL can be connected to a mid-bias row voltage source (similar to mid-bias column voltage source <NUM>), and can operate in an analogous manner to the COL DESEL <NUM>.

Still referring to <FIG>, in operation, in some embodiments, the memory device <NUM> is configured such that a T cell 154T can be accessed via the selected column <NUM> and the selected row <NUM>, where the T cell 154T is configured to be switched between first and second resistance states in response to first and second access operations accompanied by currents flowing through the T cell 154T in opposite directions between the selected column <NUM> and the selected row <NUM>. For example, the first and second resistance states can be RESET and SET states, respectively, and the first and second access operations can be SET and RESET operations, respectively. Alternatively, the first and second resistance states can be SET and RESET states, respectively, and the first and second access operations can be RESET and SET operations, respectively.

In some embodiments, an access operation, which can be one of SET or RESET operations, comprises a selection phase and an access phase. In these embodiments, performing the access operation on the T cell 154T includes applying a first bias for the selection phase, removal of the first bias, and application of a second bias lower in magnitude than the first bias for the access phase. For example, the first bias, which can be a selection bias, can be applied using a selection phase circuit path <NUM>, by activating the PFET <NUM> of the COL SEL <NUM> such that the column selection voltage source <NUM> supplies a column selection voltage (VCOL SEL) to a first end of the T cell 154T, and activating the NFET <NUM> of the ROW SEL <NUM> such that a second end of the T cell 154T is electrically connected to a row selection voltage (VROW SEL), e.g., reference voltage <NUM>, through a current limiter <NUM>.

In addition, where the access operation is a SET operation, after removal of the first bias, the second bias, which can be a SET access bias, can be applied using a SET access circuit path <NUM>, by activating the second FET <NUM> of the COL DESEL <NUM> such that the mid-bias column voltage source <NUM> supplies a mid-bias column voltage as the column deselection voltage (VCOL DESEL) to the first end of the T cell 154T, and activating the NFET <NUM> of ROW SEL <NUM> such that the second end of the T cell 154T is electrically connected to the row selection voltage (VROW SEL), e.g., reference voltage <NUM>, through a current limiter <NUM>. It will be appreciated that where the access operation is a SET operation, the direction of the current flow through the T cell 154T is the same between the selection phase and the access phase.

In addition, where the access operation is a RESET operation, after removal of the first bias, the second bias, which can be a RESET access bias, can be applied using a RESET access circuit path <NUM>, by activating the first FET <NUM> of the COL DESEL <NUM> such that the first end of the T cell 154T is grounded, and activating the PFET <NUM> of ROW SEL <NUM> such that the row selection circuit <NUM> supplies a deselection voltage (VROW DESEL) to the second end of the T cell 154T. It will be appreciated that where the access operation is a RESET operation, the direction of the current flow through the T cell 154T is opposite between the selection phase and the access phase of the RESET operation.

In the following, SET and RESET access operations in opposite polarities for a memory device are described, according to various embodiments. <FIG> are charts illustrating voltage-time (V-T) curves of columns and rows of a memory array as a memory cell is accessed, according to various embodiments. In particular, <FIG> illustrate accessing a memory cell in a cross-point array, where the memory cell is configured to be switched in response to RESET and SET access operations, where the currents flow through the memory cell in opposite directions, wherein the access operations comprise application of a first bias for a selection phase, removal of the first bias, and application of a second bias lower in magnitude than the first bias for an access phase. In <FIG>, the x-axis represents time and the y-axis represents voltage.

<FIG> illustrates V-T curves of a cross-point memory array in which a SET access operation is performed on a memory cell via a column and a row, according to some embodiments. V-T curves <NUM> and <NUM> represent time evolutions of voltages applied on a selected column and a selected row. The SET access operation comprises a selection phase <NUM> followed by an access phase <NUM>. The selection phase <NUM> is initiated at a selection time (t=tSEL) by a BL selection signal <NUM> being activated from a deactivated state <NUM> to an activated state <NUM>, and by a WL selection signal <NUM> being activated from a deactivated state <NUM> to an activated state <NUM>. The selection phase <NUM> ends when the BL selection signal <NUM> is deactivated back to the deactivated state <NUM> at a release time (t=tREL). The access phase <NUM> is initiated by the BL selection signal <NUM> being deactivated at the tREL and ends by the WL selection signal <NUM> being deactivated at a deselection time (t=tDESEL).

Still referring to <FIG>, according to some embodiments, at time t=<NUM>, a plurality of columns and rows of the cross-point memory array, including a column and a row to be selected for accessing a target cell (for example, the T cell 154T in <FIG>), as well as columns and rows to be inhibited (e.g., for inhibiting the remaining cells, for example, A, B, and C cells 154A, 154B, and 154C in <FIG>), may be precharged to VCOL DESEL and VROW DESEL, respectively. The precharge voltages VCOL DESEL and VROW DESEL may be supplied, for example, by column and row selection voltage sources <NUM> and <NUM> described with respect to <FIG>.

At tSEL, a selection bias <NUM> can be applied across the T cell by, for example, applying VCOL SEL on the selected column as indicated by the V-T curve <NUM> and VROW SEL on the selected row as indicated by the V-T curve <NUM>. The VCOL SEL can be applied, for example, by using the COL SEL <NUM> (<FIG>) to connect the selected column to the column selection voltage source <NUM> (<FIG>). The VROW SEL can be applied, for example, by using the ROW SEL <NUM> (<FIG>) to connect the selected row to ground <NUM> (<FIG>). Upon application of the VCOL SEL and the VROW SEL to selected column and the selected row, respectively, the T cell may be under a selection bias <NUM> and a current flows from the selected column through the T cell to the selected row through the selection phase circuit path <NUM> (<FIG>). Under this condition, A cells and B cells may be under inhibit biases <NUM> and <NUM>, respectively. While in the illustrated embodiment, VCOL DESEL and VROW DESEL are at substantially the same voltage level such that C cells are essentially under zero bias, it will be appreciated that VCOL DESEL and VROW DESEL can be at different voltage levels such that C cells have a non-zero bias.

The relative magnitudes of VCOL SEL, VROW SEL, VCOL DESEL and VROW DESEL may be chosen to be at suitable voltages depending on the choice of memory and selection elements as well as the desired array biasing approach. In some embodiments, a T cell may be under a bias between about 4V and about 10V, while type A and B cells may be under about <NUM>% the bias of the T cell, for example between about 2V and 5V, and C cells may be under about 0V. In some embodiments, a biasing approach may be chosen such that any suitable selection bias may be applied across the T cell, while the sum of biases across A, B and C approximately equals the selection bias.

After a certain amount of time under which the memory cell has been placed under the selection bias <NUM>, the T cell may threshold at a threshold time (t=tTH), which may in turn cause a snap-back discharge current to flow through the memory cell. After the T cell thresholds, the bias across the T cell collapses to a hold level <NUM>, which may correspond to the hold voltage VH described with respect to <FIG>, and can have a magnitude of, for example between about <NUM>. 1V and about 2V, for example about 1V.

At the release time (t=tREL), the T cell may be released at least momentarily from the thresholded condition, according to some embodiments. In some embodiments, releasing includes allowing the current flowing though the T cell to fall below a minimum hold current similar to IH described with respect to <FIG>.

After releasing the T cell at least momentarily from the thresholded condition, a SET access bias <NUM> may be applied across the T cell according to some embodiments. The SET access bias <NUM> is applied such that the selected column is at higher potential relative to the selected row such that the current flows from the selected column through the T cell to the selected row. As described above with respect to <FIG>, after being released from the thresholded condition, the T cell may have a lowered threshold voltage having a magnitude which depends on a time lapsed from t=tREL such that the SET access bias <NUM> is lower in magnitude than the selection bias <NUM>. The magnitude of the SET access bias <NUM> can be, for example, less than about <NUM>% of the selection bias <NUM>, less than about <NUM>% of the selection bias <NUM>, or less than about <NUM>% of the of the selection bias <NUM>.

In some embodiments, as illustrated in <FIG>, the SET access bias <NUM> is applied immediately after releasing. In other embodiments, there may be a delay before the SET access bias <NUM> is applied after releasing the T cell. In some embodiments, the SET access bias <NUM> may be applied within about <NUM> microseconds, within about <NUM> nanoseconds, within about <NUM> nanoseconds, or within about <NUM> nanosecond.

The SET access bias <NUM> can be applied across the T cell by, for example, applying a voltage VCOL DESEL on the selected column and grounding the selected row through the SET access circuit path <NUM> (<FIG>). It will be appreciated that either of the column selection voltage source <NUM> or the mid-bias column voltage source <NUM> illustrated in <FIG> may be used for supplying the voltage to the selected column for biasing the T cell under the access bias <NUM>. The voltage can be applied to the selected column, for example, by using the COL SEL <NUM> (<FIG>) to connect the selected column to the column selection voltage source <NUM> (<FIG>), in which case the current flows through the selection phase circuit path <NUM> (<FIG>). Alternatively, the voltage can be applied to the selected column, for example, by using the COL DESEL <NUM> (<FIG>) to connect the selected column to the mid-bias column voltage source <NUM> (<FIG>), in which case the current flows through the SET access circuit path <NUM> (<FIG>). The illustrated embodiment in <FIG> corresponds to the current flowing through the SET access circuit path <NUM> during the access phase <NUM>. It will be appreciated that, during the illustrated SET access operation, the selected column is at a higher voltage relative the selected row during both the selection bias <NUM> and the access bias <NUM> such that the direction <NUM> of current flow is the same between the two biasing conditions, i.e., from the selected column to the selected row. At a deselection time t=tDESEL, the selected column and the selected row may be returned to the precharging condition, VCOL DESEL and VROW DESEL, respectively to complete the SET access operation.

<FIG> illustrates voltage-time curves of a cross-point memory array in which a RESET access operation is performed on a memory cell via a column and a row, according to some embodiments. Voltage-time curves (V-T) <NUM> and <NUM> represent time evolutions of voltages on a selected column and a selected row, respectively. The RESET access operation comprises a selection phase <NUM> followed by an access phase <NUM>. In the illustrated embodiment, the selection phase <NUM> is initiated at a selection time (t=tSEL) by a BL selection signal and a WL signal <NUM> and <NUM> being activated from deactivated states <NUM> and <NUM>, respectively, to activated states <NUM> and <NUM>, respectively. The selection phase <NUM> ends and the access phase <NUM> initiates at a release time (t=tREL), when the BL selection signal <NUM> and the WL signal <NUM> are deactivated to the deactivated states <NUM> and <NUM>, respectively. During the access phase <NUM> at t=tSEL2, the column deselection voltage <NUM> (VCOL DES) is changed from the mid-bias column supply <NUM> to a reference voltage <NUM>. The access phase <NUM> ends when the column deselection voltage <NUM> (VCOL DES) is changed back to the mid-bias column supply <NUM> at a deselection time (t=tDESEL).

Still referring to <FIG>, according to some embodiments, the V-T curves <NUM> and <NUM> corresponding to a selected column and a selected row, respectively, during the selection phase from time t=<NUM> to t=tREL, are qualitatively similar to the V-T curves <NUM> and <NUM> of selected column and row, respectively, for the selection phase of the SET access operation described with respect to <FIG>. Similar to <FIG>, at t=tTH, a target cell (e.g., the T cell 154T in <FIG>) may be thresholded, and at t=tREL, the T cell may be released at least momentarily from the thresholded condition. In some embodiments, the magnitudes of a selection bias <NUM> in a RESET access operation may be lower than the selection bias <NUM> (in <FIG>) in a SET access operation by a voltage difference of for example, between about <NUM>. 1V and 2V, or between about <NUM>. 5V and <NUM>. 5V, for instance about 1V.

Subsequently, a RESET access bias 348a may be applied across the T cell at a second selection time (t=tSEL2) according to some embodiments. According to the illustrated embodiment, there may be a delay between releasing the T cell at tREL and applying the RESET access bias 348a at tSEL2. Similar to the SET access operation described with respect to <FIG>, the RESET access bias 348a may be applied within about <NUM> microseconds, within about <NUM> nanoseconds, within about <NUM> nanoseconds, or within about <NUM> nanosecond at t=tSEL2, from the time of releasing the memory cell at tREL.

In some embodiments, after a certain amount of time under which the memory cell has been placed under the RESET access bias 348a, the T cell may threshold for a second time at a second threshold time (t=tTH2), which may in turn cause a second snap-back discharge current to flow through the memory cell, whose magnitude is smaller than the snap-back discharge occurring as a result of the snap-back event at t=tTH. During the second snap-back event at t=tTH2, the direction of current flow is opposite to the direction of current flow during the first snap-back event at t=tTH. After the T cell thresholds for the second time at t=tTH2, the bias across the T cell may reduce to a post-threshold RESET access bias 348b. Subsequently, similar to the SET access operation described with respect to <FIG>, at a deselection time t=tDESEL, the selected column and the selected row may be returned to the precharging condition, VCOL DESEL and VROW DESEL, respectively, to complete the RESET access operation.

In some embodiments, the voltage can be applied to the selected column, for example, by using the mid-bias column voltage source <NUM> and COL DESEL <NUM> (<FIG>), in which the current flows through the RESET access circuit path <NUM> (<FIG>). The illustrated embodiment in <FIG> corresponds to the current flowing through the RESET access circuit path <NUM>.

It will be appreciated that, unlike the SET access bias described with respect to <FIG>, the direction of the bias is reversed between the selection bias <NUM> and the RESET access bias <NUM>. During application of the selection bias <NUM>, the selected column is at a higher voltage relative to the selected row such that the current flows from the selected column to the selected row. During application of the RESET access bias <NUM>, the selected column is at a lower voltage relative to the selected row such that the current flow is from the selected row to the selected column. Such reversal of the current flow can be caused, for example, by dropping the voltage on the selected column to a low level (for example, grounded at zero volts) using a COL DESEL <NUM> (<FIG>) to connect the selected column to ground <NUM> (<FIG>) and applying a higher level VROW DESEL (e.g., relative to ground <NUM>) to the selected row. As discussed above, in addition to the selected column, other columns that are deselected can also be connected to the same mid-bias column voltage source <NUM> (<FIG>) using the COL DESEL <NUM> (<FIG>). The deselected columns can be dropped to the low voltage level <NUM> (e.g. VROW SEL). As discussed above, the number of deselected columns connected to the mid-bias column voltage source <NUM> can be any suitable number depending on the design of the memory device, for example between <NUM> and a fraction of columns in a tile. It will be appreciated that while a subset of type A cells along the selected column may also experience a reversal in bias, the subset of cells will experience a snap-back event, because unlike the T cell, the subset of type A cells have not experienced a previous snap-back event at tTH similar to that experienced by the T cell, and therefore the threshold voltages of the subset of type A cells have not been temporarily reduced as that of the T cell, according to the temporary threshold voltage reduction and its recovery effect as described above with respect to <FIG>.

In some embodiments, the memory controller may be configured to detect a snapback event occurring at tTH, and cause a switching of the column deselection voltage, VCOL DES, for the selected column, from a mid-bias column voltage (supplied by, for example, the mid-bias column voltage source <NUM> in <FIG>) to a reference voltage (e.g., ground <NUM>). The detection can be made by current detection or voltage detection circuits and/or using techniques that are designed to detect a voltage or a current event that lasts for a duration of time less than, for example, about <NUM> ns. In these embodiments where the memory controller can detect the snap back event, the switch from the mid-bias column voltage to the reference voltage can be made conditionally, based on whether or not the snap back event has been detected.

Claim 1:
An apparatus comprising:
a resistive random access memory (RRAM) array (<NUM>) comprising a resistive random access memory cell (<NUM>, 154T) having a first end and a second end, the memory cell (<NUM>, 154T) comprising a selector element (<NUM>) and a storage element (<NUM>) electrically arranged in series;
a first voltage source (<NUM>) electrically connected to the first end of the memory cell (<NUM>, 154T) via a first circuit path (<NUM>) that is associated with a selection phase (<NUM>) of an access operation; and
a second voltage source (<NUM>) electrically connected to the first end of the memory cell (<NUM>, 154T) via a second circuit path (<NUM>) that is associated with an access phase (<NUM>) setting a logic value of the memory cell during the access operation, wherein a second bias voltage magnitude of the second voltage source (<NUM>) is less than a first bias voltage magnitude of the first voltage source (<NUM>), the second voltage source being configured to apply the second bias voltage magnitude during the access phase (<NUM>) after removal of the first bias voltage magnitude of the first voltage source applied during the selection phase (<NUM>) and wherein a threshold voltage of the memory cell (<NUM>, 154T) is based at least in part on an elapsed time lapse (tR) from a moment (tREL) the memory cell has been released from a previous thresholding event experienced during the selection phase of the access operation in response to the application of the first bias voltage magnitude.