Patent Description:
The disclosure relates to the technical field of semiconductors, and relates, to a method for forming a semiconductor structure.

A Dynamic Random Access Memory (DRAM) is a semiconductor storage device commonly used in a computer. The DRAM is composed of many duplicate storage units. Each storage unit usually includes a capacitor and a transistor.

In a DRAM in a related art, the transistor is horizontal, and the capacitor is perpendicular to the transistor. With continuous development of process nodes, the integration degree of the DRAM is continuously improved and the size is continuously reduced, the aspect ratio of the capacitor is larger and larger, the size of transistors is smaller and smaller, and the process complexity and manufacturing cost of the DRAM are improved gradually. Related technologies are known from <CIT>, <CIT> and <CIT>. All of these documents disclose DRAM devices comprising laterally adjacent capacitors and gate-all-around transistors.

In the drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts/elements in different views. Similar reference numerals with different letter suffixes may represent different examples of similar parts. The drawings generally illustrate the various embodiments discussed herein by way of examples rather than limitation.

Reference numerals in the drawings are described as follows.

<NUM>-semiconductor substrate; <NUM>-stacked structure; <NUM>-first semiconductor layer; <NUM>-second semiconductor layer; <NUM>-active column; <NUM>-first isolation groove; 12a-second isolation groove; <NUM>-sacrificial layer; <NUM>-third isolation groove; 13a-fourth isolation groove; <NUM>-protective layer; <NUM>-support structure; <NUM>-first mask layer; <NUM>-second mask layer; <NUM>-third mask layer; <NUM>-first photoresist layer; <NUM>-second photoresist layer; <NUM>-third photoresist layer; <NUM>-fourth photoresist layer; <NUM>-fifth photoresist layer; <NUM>-sixth photoresist layer; <NUM>-seventh photoresist layer; <NUM>-gate-all-around structure; <NUM>-medium layer; <NUM>-first medium layer; <NUM>-second medium layer; <NUM>-dielectric layer; <NUM>-first metal layer; <NUM>-second metal layer; <NUM>-insulating medium layer; <NUM>-third metal layer; <NUM>-semi-capacitor structure; <NUM>-first isolation layer; <NUM>-capacitor structure; <NUM>-first opening; <NUM>-first gap; <NUM>-first connecting structure; <NUM>-second isolation layer; <NUM>-bit line structure; <NUM>-stepped word line structure; <NUM>-second connecting structure; <NUM>-third isolation layer; <NUM>-first metal wire; <NUM>-second metal wire; <NUM>-third metal wire; <NUM>-barrier layer; <NUM>-fifth isolation groove; <NUM>-isolation structure; and <NUM>-semiconductor structure.

Exemplary embodiments of the disclosure will be described below in more detail with reference to the drawings. Although the exemplary embodiments of the disclosure are shown in the drawings, it should be understood that, the disclosure may be implemented in various forms and should not be limited by the specific embodiments elaborated herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

In the following description, a large number of details are given to provide a more thorough understanding of the disclosure. However, it will be apparent to those skilled in the art that the disclosure may be implemented without one or more of these details. In other examples, in order to avoid confusion with the disclosure, some technical features known in the art are not described. That is, all the features of the actual embodiments are not described here, and the known functions and structures are not described in detail.

In the drawings, the dimensions of layers, areas, and elements and their relative dimensions may be exaggerated for clarity. Throughout, the same reference numerals represent the same elements.

It is to be understood that description that an element or layer is "above/on", "adjacent to", "connected to/with", or "coupled to" another element or layer may refer to that the element or layer is directly above, adjacent to, connected to or coupled to the other element or layer; or there may be an intermediate element or layer. On the contrary, description that an element is "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer refers to that there is no intermediate element or layer. It is to be understood that, although various elements, components, areas, layers, and/or parts may be described with terms first, second, third, etc., these elements, components, areas, layers, and/or parts should not be limited to these terms. These terms are used only to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, a first element, component, area, layer, or part discussed below may be represented as a second element, component, area, layer, or part without departing from the teaching of the disclosure. However, when the second element, component, area, layer, or part is discussed, it does not mean that the first element, component, area, layer, or part must exist in the disclosure.

The terms used herein are intended only to describe specific embodiments and are not a limitation of the disclosure. As used herein, singular forms "a/an", "one", and "the" may also be intended to include the plural forms, unless otherwise specified types in the context. It is also to be understood that, when terms "composed of" and/or "including" are used in this specification, the presence of the features, integers, steps, operations, elements, and/or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups is also possible. As used herein, terms "and/or" includes any and all combinations of the related listed items.

Before introducing the embodiments of the disclosure, three directions for describing a three-dimensional structure that is used in the following embodiments are defined first. Taking a Cartesian coordinate system as an example, the three directions include an X-axis direction, a Y-axis direction, and a Z-axis direction. The substrate may include a top surface located on a front side and a bottom surface located on a back side opposite to the front side. The direction perpendicular to the top surface and the bottom surface of the substrate is defined as the third direction in a case of ignoring the flatness of the top surface and the bottom surface. In the direction of the top surface and the bottom surface (that is, the plane on which the substrate is located) of the substrate, two directions that intersect each other (e.g., perpendicular to each other) are defined. For example, an extending direction of a first isolation groove may be defined as a first direction, an extending direction of a third isolation groove may be defined as a second direction, and a plane direction of the semiconductor substrate may be determined on the basis of the first direction and the second direction. Here, the first direction, the second direction, and the third direction are perpendicular to each other in pairs. In the embodiments of the disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

An embodiment of the disclosure provides a method for forming a semiconductor structure. <FIG> illustrates a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the disclosure. As shown in <FIG>, the method for forming the semiconductor structure includes as follows.

At S101, a substrate is provided. The substrate includes a first isolation groove extending in a first direction and a plurality of active columns arranged in an array along the first direction and a third direction. The substrate is divided by the first isolation groove into a first area and a second area along a second direction. The active columns are supported through support structures.

In the embodiments of the disclosure, the substrate at least includes a semiconductor substrate. The semiconductor substrate may be a silicon base substrate. The semiconductor substrate may also include other semiconductor elements such as germanium (Ge), or include semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or a combination thereof.

In the embodiments of the disclosure, the substrate is divided into the first area and the second area by the first isolation groove in the second direction. The first area and the second area are respectively configured to form different functional structures. The first area is configured to form a capacitor structure. The second area is configured to form a gate-all-around structure, a bit line structure, and a stepped word line structure.

In the embodiments of the disclosure, the substrate includes a plurality of active columns and the support structures arranged in an array in the first direction and the third direction. The plurality of active columns are supported through the support structures. Each active column is configured to form a transistor.

The support structure extends in the first direction and the third direction. The support structure may be located on a surface of the semiconductor substrate, or may also extend into the semiconductor substrate, so as to achieve a better supporting effect.

In the embodiments of the disclosure, the active columns may be square prisms (such as, quadrangular prisms, hexagonal prisms, and octagonal prisms) or cylinders.

At S102, semi-capacitor structures located in the first area and gate-all-around structures located in the second area are formed in gaps between the active columns.

In the embodiments of the disclosure, the first area is configured to form capacitor structures, and the second area is configured to from the gate-all-around structures. The semi-capacitor structure is not an incomplete capacitor structure, but a part of the capacitor structure, for example, a capacitor structure only including one electrode layer, or a capacitor structure only including a dielectric layer and an electrode layer.

In the embodiments of the disclosure, the formed gate-all-around structure has a wide channel area, so that a short channel effect can be reduced, and the control capacity of a gate electrode can further be improved, thereby improving the performance of the formed semiconductor structure.

At S103, the active columns and the semi-capacitor structures in the first area are processed to form capacitor structures extending in the second direction.

In the embodiments of the disclosure, the active columns in the first area are processed, for example, an electrode layer may be formed in the first area, or a dielectric layer and an electrode layer may be formed in the first area to convert a semi-capacitor structure into a complete capacitor structure.

In the embodiments of the disclosure, the formed capacitor structures are arranged at intervals in the first direction and the third direction, and extend in the second direction. That is to say, the capacitor structures formed in the embodiments of the disclosure are arranged horizontally, and the horizontal capacitor structures can reduce the possibility of tipping or breaking, so that the stability of the capacitor structure can be improved.

At S104, first connecting structures connecting the gate-all-around structures and the capacitor structures are formed in the first isolation groove.

During implementation, a wire can be grown on a channel surface in the gate-all-around structure by an epitaxy technology as the first connecting structure. The first connecting structure extends in the second direction and is electrically connected with an electrode layer of the capacitor structure.

In the embodiments of the disclosure, firstly, a first isolation groove extending in a first direction and a plurality of active columns arranged in an array along the first direction and a third direction are formed on the substrate first. The substrate is divided into a first area and a second area by the first isolation groove in the first direction, so as to prepare different functional devices in different areas. Secondly, semi-capacitor structures located in the first area and gate-all-around structures located in the second area are formed in gaps between the active columns. Thirdly, the active columns and the semi-capacitor structures in the first area are processed, so as to form capacitor structures extending in the second direction. The capacitor structure includes a semi-capacitor structure. Finally, first connecting structures connecting the gate-all-around structures and the capacitor structures are formed in the first isolation groove. Since the gate-all-around structures and the semi-capacitor structures constituting the capacitor structures are formed at the same time, so that a process for preparing the semiconductor structure can be simplified, and the manufacturing cost of the semiconductor structure can be reduced. In addition, since the capacitor structure in the embodiments of the disclosure extends in the second direction, that is, the capacitor structure in the embodiments of the disclosure is horizontal. Compared with a vertical capacitor structure with a large depth-to-width ratio, the horizontal capacitor structure can reduce the possibility of tipping or breaking, so that the stability of the capacitor structure can be improved. Moreover, the stacked structure formed by stacking a plurality of capacitor structures in the third direction can form a three-dimensional semiconductor structure, so as to improve the integration degree of the semiconductor structure and realize miniaturization.

<FIG> and <FIG> illustrate schematic structural diagrams in a process for forming a semiconductor structure according to embodiments of the disclosure. <FIG> illustrates a three-dimensional schematic structural diagram. <FIG> illustrates a sectional view of a stacked structure in <FIG> in a-a' and b-b'. In order to facilitate the detailed introduction of an internal structure of the formed semiconductor structure, <FIG> and <FIG> in a subsequent formation process are all shown in the perspective of sectional views of a-a 'and b-b'. A process for forming the semiconductor structure according to the embodiments of the disclosure is described in detail with reference to <FIG> and <FIG>.

First, S101 that a substrate is provided may be performed with reference to <FIG>. The substrate includes a first isolation groove <NUM> extending in a first direction and a plurality of active columns <NUM> arranged in an array along the first direction and a third direction. The substrate is divided into a first area A and a second area B by the first isolation groove <NUM> along a second direction. The active columns <NUM> are supported through support structures <NUM>.

In some embodiments, the forming the substrate includes: a semiconductor substrate <NUM> is provided. A stacked structure <NUM> is formed on the semiconductor substrate <NUM>. The stacked structure <NUM> includes first semiconductor layers <NUM> and second semiconductor layers <NUM> stacked alternately. The stacked structure <NUM> is etched to form the first isolation groove <NUM>. The first semiconductor layers <NUM> in the stacked structure <NUM> are removed.

As shown in <FIG> and <FIG>, the stacked structure <NUM> formed by stacking the first semiconductor layers <NUM> and second semiconductor layers <NUM> alternately is formed on the semiconductor substrate <NUM>. The material of the first semiconductor layer <NUM> may be germanium, silicon germanide, or silicon carbide, or may also be a Silicon-On-Insulator (SOI) or a Germanium-on-Insulator (GOI). The second semiconductor layer <NUM> may be a silicon layer, or may also include other semiconductor elements such as germanium, or include semiconductor compounds such as silicon carbide, gallium arsenide, gallium phosphide indium phosphide, indium arsenide or indium antimonide, or include other semiconductor alloys such as silicon germanium, arsenic gallium phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphate, or a combination thereof.

In the embodiments of the disclosure, since the first semiconductor layer <NUM> needs to be etched and removed subsequently and the second semiconductor layer <NUM> needs to be remained, the first semiconductor layer <NUM> has higher etching selectivity than the second semiconductor layer <NUM>. That is, under the same etching conditions, the first semiconductor layer <NUM> is more easily etched than the second semiconductor layer <NUM>. For example, the first semiconductor layer <NUM> may be a silicon germanide layer, and the second semiconductor layer <NUM> may be a silicon layer.

In the embodiments of the disclosure, the first semiconductor layer <NUM> and the second semiconductor layer <NUM> may be formed through an epitaxy process. The first semiconductor layers <NUM> and the second semiconductor layers <NUM> may be stacked alternately to form a semiconductor superlattice. The thickness of each semiconductor layer varies from a few atoms to dozens of atomic layers, and the main semiconductor properties of each layer, such as a band gap and a doping level, can be independently controlled. The number of layers of the first semiconductor layers <NUM> and the second semiconductor layers <NUM> in the stacked structure <NUM> may be set according to the required capacitance density (or storage density). The greater the number of layers of the first semiconductor layers <NUM> and the second semiconductor layers <NUM>, the higher the integration degree of the formed three-dimensional storage and the greater the capacitance density. For example, the number of layers of the first semiconductor layers <NUM> and the second semiconductor layers <NUM> may be <NUM> to <NUM> layers.

In some embodiments, before forming the first isolation groove <NUM>, the method for forming the semiconductor structure further includes: the stacked structure <NUM> and part of the semiconductor substrate <NUM> are etched to form a third isolation groove <NUM>.

As shown in <FIG>, the forming the third isolation groove <NUM> includes: firstly, a first mask layer <NUM>, a first anti-reflection layer <NUM>, and a first photoresist layer <NUM> with a specific pattern H are sequentially formed on a surface of the stacked structure <NUM>. Secondly, the first anti-reflection layer <NUM> and the first mask layer <NUM> are etched sequentially through the first photoresist layer <NUM> to transfer the specific pattern H to the first mask layer <NUM>. Finally, the stacked structure <NUM> and part of the semiconductor substrate <NUM> are etched through the first mask layer with the specific pattern H, so as to form the third isolation groove <NUM>. In an embodiment of the disclosure, the bottom of the third isolation groove <NUM> is located in the semiconductor substrate <NUM>. In other embodiments, the third isolation groove <NUM> may also be only located in the stacked structure <NUM> without extending into the semiconductor substrate <NUM>.

In the embodiments of the disclosure, the first anti-reflection layer <NUM> is configured to absorb the light reflected from the surface of the stacked structure <NUM> to avoid the interference between reflected light and incident light. The material of the first anti-reflection layer <NUM> may be silicon oxynitride or a spin coated carbon layer. The material of the first mask layer <NUM> may be one or more of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. Both the first mask layer <NUM> and the first anti-reflection layer <NUM> may be formed by any suitable deposition process.

In the embodiments of the disclosure, the second area B is divided into a first part B-<NUM> and a second part B-<NUM> by the third isolation groove <NUM> in the first direction. The first part B-<NUM> may be configured to form a gate-all-around structure, and the second part B-<NUM> may be configured to form a stepped word line structure.

In some embodiments, after the third isolation groove <NUM> is formed, the method for forming the semiconductor structure further includes: the first photoresist layer <NUM>, the first anti-reflection layer <NUM>, and the first mask layer <NUM> are removed. In the embodiments of the disclosure, the first photoresist layer <NUM>, the first anti-reflection layer <NUM>, and the first mask layer <NUM> may be removed by using a dry etching technology (such as a plasma etching technology, a reactive ion etching technology, or an ion milling technology) or a wet etching technology, so as to expose the surface of the stacked structure <NUM> (as shown in <FIG>).

<FIG> is a top view of the first area. As shown in <FIG>, after the third isolation groove <NUM> is formed and before the first isolation groove <NUM> is formed, the method for forming the semiconductor structure further includes: the stacked structure is etched to form a fifth isolation groove <NUM> extending in the second direction, the second semiconductor layers <NUM> are divided into a plurality of active columns <NUM> arranged in the first direction by the fifth isolation groove <NUM>; and an isolation structure <NUM> is formed in the fifth isolation groove <NUM>.

In the embodiments of the disclosure, the material for forming the isolation structure <NUM> may be silicon oxide, silicon nitride, or silicon oxynitride. The isolation structure <NUM> is configured to fill a gap between the adjacent active columns <NUM>, so as to facilitate the subsequent formation of other structures between the active columns <NUM> and the isolation structure <NUM>.

In some embodiments, after the isolation structure <NUM> is formed and before the first isolation groove <NUM> is formed, the method for forming the semiconductor structure further includes: part of the isolation structure <NUM> and part of the first semiconductor layers <NUM> are etched and removed to form a plurality of etched holes <NUM> extending in the first direction. The etched holes <NUM> expose the active columns <NUM>. The etched holes <NUM> are filled with a support material to form support structures <NUM> surrounding the active columns <NUM>.

In the embodiments of the disclosure, as shown in <FIG>, the forming the support structures <NUM> includes: firstly, a second mask layer <NUM>, a second anti-reflection layer <NUM>, and a second photoresist layer <NUM> with a specific pattern I are sequentially formed on the surface of the stacked structure <NUM>. The specific pattern I may be multiple openings extending in the X-axis direction. Secondly, the second anti-reflection layer <NUM> and the second mask layer <NUM> are etched sequentially through the second photoresist layer <NUM> to transfer the specific pattern I to the second mask layer <NUM>. Thirdly, part of the isolation structure <NUM> and part of the first semiconductor layer <NUM> are etched and removed through the second mask layer with the specific pattern I to form a plurality of etched holes <NUM> extending in the X-axis direction. Finally, the etched holes <NUM> are filled with a support material to form support structures <NUM> surrounding the active columns <NUM>. The material of the second mask layer <NUM> may be one or more of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The material of the second anti-reflection layer <NUM> may be silicon oxynitride or spin coated carbon. The support material may be silicon nitride or silicon carbonitride.

In the embodiments of the disclosure, the support structure(s) <NUM> may also extend into the semiconductor substrate <NUM> to achieve a more stable support effect.

In the embodiments of the disclosure, the support structures <NUM> may be configured to support the active columns <NUM>. A capacitor structure and a gate-all-around structure will be formed between adjacent active columns <NUM> subsequently. Therefore, the support structures <NUM> may also be configured to support the capacitor structure and the gate-all-around structure, so that the stability of the formed semiconductor structure is improved.

In some embodiments, after the etched holes <NUM> are formed, the method for forming the semiconductor structure further includes: the second photoresist layer <NUM>, the second anti-reflection layer <NUM>, and the second mask layer <NUM> are removed. During implementation, the second photoresist layer <NUM>, the second anti-reflection layer <NUM>, and the second mask layer <NUM> may be removed by using a dry etching technology or a wet etching technology to expose the surface of the stacked structure <NUM> (as shown in <FIG>).

As shown in <FIG>, the forming the first isolation groove <NUM> includes: firstly, a third mask layer <NUM> and a third photoresist layer <NUM> with a specific pattern C are sequentially formed on the surface of the stacked structure <NUM>. The specific pattern C may be an opening extending in the X-axis direction. The projection of the specific pattern C on the semiconductor substrate <NUM> is adjacent to the projection of one of the specific pattern I on the semiconductor substrate <NUM> in the Y-axis direction. Secondly, the third mask layer <NUM> is etched through the third photoresist layer <NUM> to transfer the specific pattern C to the third mask layer <NUM>. The stacked structure <NUM> and the isolation structure <NUM> are etched through the third mask layer with the specific pattern C to form the first isolation groove <NUM>. The first isolation groove <NUM> exposes adjacent support structures <NUM>. In the embodiments of the disclosure, the first isolation groove <NUM> extends into the semiconductor substrate <NUM> to achieve a better isolating effect.

In the embodiments of the disclosure, the substrate is divided into the first area A and the second area B by the first isolation groove <NUM> in the Y-axis direction. The first area A is configured to form a capacitor structure. The second area B is configured to form a gate-all-around structure, a bit line structure, and a stepped word line structure.

In other embodiments, the first isolation groove <NUM> may also be only located on the surface of the semiconductor substrate <NUM>.

In the embodiments of the disclosure, after the first isolation groove <NUM> is formed, the method for forming the semiconductor structure further includes: the third mask layer <NUM> and the third photoresist layer <NUM> are removed. During implementation, the third mask layer <NUM> and the third photoresist layer <NUM> may be removed by using a dry etching technology or a wet etching technology.

In some embodiments, as shown in <FIG>, after the first isolation groove <NUM> is formed, the method for forming the semiconductor structure further includes: the first isolation groove <NUM> is filled with a sacrificial material to form a sacrificial layer <NUM>.

In the embodiments of the disclosure, the sacrificial layer <NUM> may be silicon oxynitride. The sacrificial layer <NUM> is configured to protect a cross section of the second semiconductor layer <NUM> from being damaged in subsequent removal of the first semiconductor layer <NUM>, so as to facilitate subsequent epitaxial formation of a connecting structure for connecting a gate-all-around structure and a stepped word line structure on a cross section of the second semiconductor layer <NUM>.

As shown in <FIG>, the first semiconductor layer <NUM> in the stacked structure <NUM> is removed.

In the embodiments of the disclosure, the first semiconductor layer <NUM> in the stacked structure <NUM> may be removed by using a wet etching technology (for example, etching by using strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or a dry etching technology. The first semiconductor layer <NUM> has higher etching selectivity relative to the second semiconductor layer <NUM>, so that the second semiconductor layer <NUM> cannot be damaged when the first semiconductor layer <NUM> is removed.

In some embodiments, continuing to refer to <FIG>, after the first semiconductor layer <NUM> is removed, the method for forming the semiconductor structure further includes: the sacrificial layer <NUM>, a protective layer <NUM>, and the isolation structure <NUM> are removed. For example, the sacrificial layer <NUM>, the protective layer <NUM>, and the isolation structure <NUM> may be removed by using a wet etching technology.

In some embodiments, as shown in <FIG>, the method for forming the semiconductor structure further includes: a thinning process is performed on the active columns <NUM>. In the embodiments of the disclosure, the thinning process is performed on the active columns <NUM>, so that a gap between two adjacent active columns <NUM> becomes larger. On one hand, the effective area of the capacitor structure can be enlarged, so as to improve the capacity of the capacitor structure. On the other hand, a large space may be reserved for subsequent formation of the capacitor structure and the gate-all-around structure, so that the process complexity is reduced.

In the embodiments of the disclosure, the thinning process may be performed on the active columns <NUM> by the following two methods.

Method <NUM>: dry etching is directly performed on the active columns <NUM>, and the etching is stopped until the required thickness is formed.

Method <NUM>: the active columns <NUM> are oxidized in situ to oxidize part of the active columns <NUM> into silicon oxide layers, and the silicon oxide layers are removed by using the wet etching or dry etching technology.

It is to be noted that, in other embodiments, no thinning process may be performed on the active columns <NUM>.

Next, S102 that semi-capacitor structures <NUM> located in the first area A and gate-all-around structures <NUM> located in the second area B are formed in the gaps between the active columns <NUM> may be performed with reference to <FIG>.

According to the claimed invention, the forming the semi-capacitor structures <NUM> and the gate-all-around structures <NUM> includes: a medium layer <NUM> and a first metal layer <NUM> are sequentially formed on surfaces of the active columns <NUM> in the first area A and the second area B.

In some embodiments, there may be one or more medium layers <NUM>. For example, the medium layer <NUM> in the embodiments of the disclosure may include a first medium layer <NUM> and a second medium layer <NUM>. The material of the first medium layer <NUM> may be silicon oxide or other suitable materials. The material of the second medium layer <NUM> may be a high-K material, such as one or a combination of lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, niobium oxide, hafnium silicate, or zirconia. The material of the first metal layer may be a material with good conductivity, such as titanium nitride.

In the embodiments of the disclosure, when the second medium layer <NUM> can serve as a dielectric layer of the capacitor structure, the second medium layer <NUM> and the first metal layer <NUM> located in the first area A constitute the semi-capacitor structure <NUM>. In other embodiments, when the second medium layer <NUM> cannot serve as a dielectric layer of the capacitor structure, the semi-capacitor structure <NUM> includes the first metal layer <NUM>. The first medium layer <NUM>, the second medium layer <NUM>, and the first metal layer <NUM> located in the second area B constitute the gate-all-around structure <NUM>.

In the embodiments of the disclosure, the first medium layer <NUM>, the second medium layer <NUM>, and the first metal layer <NUM> may be formed by any one of the following deposition processes: a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a spin coating process, a coating process, a thin film process or the like.

In the embodiments of the disclosure, the first metal layer <NUM> located in the first area A constitutes a lower electrode layer of the capacitor structure. The medium layer <NUM> and the first metal layer <NUM> located in the second area B respectively constitute a gate medium layer and a gate metal layer of the gate-all-around structure <NUM>. Since the gate-all-around structure <NUM> and the lower electrode layer of the capacitor structure are formed at the same time in the embodiments of the disclosure, a process for preparing the semiconductor structure can be simplified, and the manufacturing cost of the semiconductor structure can be reduced.

In the embodiments of the disclosure, the gate-all-around structure <NUM> has a wide channel area, so that a short channel effect can be reduced, and the control capacity of a gate electrode can further be improved, thereby improving the performance of the formed semiconductor structure.

It is to be noted that the medium layer <NUM> and the first metal layer <NUM> are also formed on inner walls of the first isolation groove <NUM> and the third isolation groove <NUM> while forming the gate-all-around structure <NUM> and the semi-capacitor structure <NUM>.

Continuing to refer to <FIG>, after the first metal layer <NUM> is formed, the method for forming the semiconductor structure further includes: a first isolation material is filled on the surface of the first metal layer <NUM> and into the gap of the first metal layers <NUM> to form a first isolation layer <NUM>.

In the embodiments of the disclosure, the first isolation layer <NUM> may be configured to isolate adjacent first metal layers <NUM>, to prevent the first metal layer <NUM> from electric leakage. The first isolation material may be silicon oxide, silicon nitride, silicon oxynitride or other suitable materials.

Next, S103 that the active columns <NUM> and the semi-capacitor structures in the first area A are processed to form the capacitor structures <NUM> extending in the second direction may be performed with reference to <FIG>.

In some embodiments, when the second medium layer <NUM> can serve as a dielectric layer of the capacitor structure <NUM>, S103 may include the following steps: as shown in <FIG>, a first opening <NUM> extending in the X-axis direction is formed in the first area A; the first opening <NUM> exposes the semiconductor substrate <NUM>; the active column <NUM> and the first medium layer <NUM> in the first area A are removed through the first opening <NUM>, so as to form a first gap <NUM>; and a second metal material is deposited in the first opening <NUM> and the first gap <NUM> to form a second metal layer <NUM>.

In other embodiments, when the second medium layer <NUM> cannot serve as the dielectric layer of the capacitor structure <NUM>, S103 may also include the following steps: the first opening <NUM> extending in the X-axis direction is formed in the first area A; the first opening <NUM> exposes the semiconductor substrate <NUM>; the active column <NUM> and the medium layer <NUM> in the first area A are removed through the first opening <NUM>, so as to form a first gap <NUM>; and a dielectric material and a second metal layer are sequentially formed in the first opening <NUM> and the first gap <NUM> to form a dielectric layer <NUM> and the second metal layer <NUM>. At this moment, the second metal layer <NUM> constitutes an upper electrode of the capacitor structure <NUM>. The first metal layer <NUM>, the dielectric layer <NUM>, and the second metal layer <NUM> located in the first area A constitute the capacitor structure <NUM>.

In some embodiments, continuing to refer to <FIG>, the forming the first opening <NUM> includes: a fourth photoresist layer <NUM> with a specific pattern D is formed on a surface of the first isolation layer <NUM>. At this moment, the first isolation layer <NUM> may serve as a mask layer of the first opening <NUM>. The first isolation layer <NUM> is etched through the fourth photoresist layer <NUM>, so as to transfer the specific pattern D into the first isolation layer <NUM>. The stacked structure <NUM> is etched through the first isolation layer <NUM> with the specific pattern D until the semiconductor substrate <NUM> is exposed to form the first opening <NUM>.

In the embodiments of the disclosure, the material of the dielectric layer may be a high-K dielectric, for example, one or any combination of lanthanum oxide (La<NUM>O<NUM>), aluminum oxide (Al<NUM>O<NUM>), hafnium oxide (HfO<NUM>), hafnium oxynitride (HfON), niobium oxide (NbO), hafnium silicate (HfSiOx) or zirconium oxide (ZrO<NUM>). The second metal material may include titanium, tungsten, molybdenum, metal nitride, or metal silicide. The dielectric material and the second metal material may be formed by any deposition process.

Finally, S104 that first connecting structures <NUM> connecting the gate-all-around structures <NUM> and the capacitor structures <NUM> are formed in the first isolation groove <NUM> may be performed with reference to <FIG>.

In some embodiments, the forming the first connecting structure <NUM> includes: the first isolation layer <NUM> located in the first isolation groove <NUM> is removed, and the medium layer <NUM> and the first metal layer <NUM> located on a side wall of the second area B in the first isolation groove <NUM> are removed, so as to form a second isolation groove 12a extending in the first direction. The second isolation groove 12a exposes the active columns <NUM> in the second area B and the first metal layer <NUM> on a side wall of the first area A; the first connecting structure <NUM> is epitaxially grown on a surface of the exposed active column <NUM>. The first connecting structure <NUM> is in contact with the first metal layer <NUM> in the first area.

As shown in <FIG>, the forming the first connecting structure <NUM> includes: a fifth photoresist layer <NUM> with a specific pattern E is formed on the surface of the first isolation layer <NUM>. At this moment, the first isolation layer <NUM> can serve as a mask layer for forming the second isolation groove 12a. The first isolation layer <NUM> is etched through the fifth photoresist layer <NUM> to transfer the specific pattern E into the first isolation layer <NUM>. The first isolation layer <NUM>, the medium layer <NUM>, and the first metal layer <NUM> located in the first isolation groove <NUM> are etched and removed through the first isolation layer with the specific pattern E to form the second isolation groove 12a extending along the X-axis direction. The second isolation groove 12a exposes the active columns <NUM> in the second area B and the first metal layer <NUM> on the side wall of the first area A. A first semiconductor material is epitaxially grown on the surface of the exposed active column <NUM> to form the first connection structure <NUM>. The first connecting structure <NUM> is in contact with the first metal layer <NUM> in the first area A.

In the embodiments of the disclosure, the first connecting structure <NUM> may be a heteroepitaxial layer. Therefore, the first semiconductor material may be silicon germanium. The content of germanium in the silicon germanium may be <NUM>% to <NUM>%. The thickness of the first connecting structure <NUM> is <NUM> to <NUM>Å.

In the embodiments of the disclosure, the epitaxial growth may be vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, or metal organic chemical vapor deposition. Self-aligned connection of the gate-all-around structure <NUM> and the capacitor structure <NUM> can be realized by using the selectivity of an epitaxy growth process.

Continuing to refer to <FIG>, after the first connecting structure <NUM> is formed, the method for forming the semiconductor structure further includes: the second isolation groove 12a and a gap between the first connecting structures <NUM> are filled with a second isolation material to form a second isolation layer <NUM>. A surface of the second isolation layer <NUM> is flush with a surface of the first isolation layer <NUM>.

In the embodiments of the disclosure, the second isolation layer <NUM> may be configured to isolate adjacent first connecting structures <NUM>. The material of the second isolation layer <NUM> may be silicon oxide, silicon nitride, silicon oxynitride or other suitable materials.

In some embodiments, referring to <FIG>, after the second isolation layer <NUM> is formed, the method for forming the semiconductor structure further includes: a bit line structure <NUM> and a stepped word line structure <NUM> connected to the gate-all-around <NUM> are formed.

In some embodiments, the forming the bit line structure <NUM> includes: one end, far away from the capacitor structure <NUM>, of the active column <NUM> is etched to form a bit line trench extending in first direction, herein the bit line trench exposes the semiconductor substrate <NUM> in the second area; and the bit line trench is filled with a bit line metal material to form the bit line structure <NUM>.

As shown in <FIG>, a sixth photoresist layer <NUM> with a specific pattern F is formed on the surface of the first isolation layer <NUM>. At this moment, the first isolation layer <NUM> and the second isolation layer <NUM> may serve as mask layers for forming the bit line trench. The first isolation layer <NUM> is etched through the sixth photoresist layer <NUM>, so as to transfer the specific pattern F into the first isolation layer <NUM>. One end, far away from the capacitor structure <NUM>, of the active column <NUM> is etched through the first isolation layer <NUM> with the specific patter F, so as to form a bit line trench (not shown) extending in the X-axis direction. The bit line trench exposes the semiconductor substrate <NUM> in the second area B. The bit line trench is filled with a bit line metal material to form the bit line structure <NUM>.

In the embodiments of the disclosure, the bit line metal material includes: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), titanium containing metal layer, polycrystalline silicon, or any combination thereof.

In some embodiments, the relationships among the bit line structure <NUM>, the gate-all-around structure <NUM>, and the support structure <NUM> may include the following two conditions: the first one is that the support structure <NUM> is located in the center of the gate-all-around structure <NUM>, and the gate-all-around structure <NUM> is in contact with the bit line structure <NUM>, as shown in <FIG>; and the second one is that the support structure <NUM> is located at one end, far away from the capacitor structure, of the gate-all-around structure (that is, located at the rightmost end of the gate-all-around structure <NUM>). At this moment, the support structure is in contact with the bit line structure <NUM>, and the bit line structure <NUM> and the gate-all-around structure <NUM> are spaced through the support structures <NUM>.

In some embodiments, before the stepped word line structure <NUM> is formed, the method for forming the semiconductor structure further includes: the first isolation layer <NUM>, the medium layer <NUM>, and the first metal layer <NUM> located in the third isolation groove <NUM> are removed to form a fourth isolation groove 13a extending in the second direction. The fourth isolation groove 13a exposes the first metal layer <NUM> of the first part and the active column <NUM> of the second part. A second connecting structure <NUM> connecting the second part and the gate-all-around structure <NUM> is formed in the fourth isolation groove 13a.

In some embodiments, as shown in <FIG>, the forming the fourth isolation groove 13a includes: a seventh photoresist layer <NUM> with a specific pattern G is formed on the surface of the first isolation layer <NUM>. At this moment, the first isolation layer <NUM> and the second isolation layer <NUM> can serve as mask layers for forming the fourth isolation groove 13a. The first isolation layer <NUM> is etched through the seventh photoresist layer <NUM> to transfer the specific pattern G into the first isolation layer <NUM>. The first isolation layer <NUM> located in the third isolation groove <NUM> and the medium layer <NUM> and the first metal layer <NUM> located on the side wall of the second part B-<NUM> in the third isolation groove <NUM> are etched and removed through the first isolation layer <NUM> with the specific pattern G to form the fourth isolation groove 13a extending along the Y-axis direction. The fourth isolation groove 13a exposes the first metal layer <NUM> on the side wall of the first part B-<NUM> and the active columns <NUM> of the second part B-<NUM>.

In the embodiments of the disclosure, the fourth isolation groove 13a is configured to form the second connecting structure <NUM> connecting the second part B-<NUM> and the gate-all-around structure <NUM>. As shown in <FIG>, the forming the second connecting structure <NUM> includes: the second semiconductor material is epitaxially grown on a surface of the exposed active column <NUM> in the second part B-<NUM> to form the second connecting structure <NUM>. The second connecting structure <NUM> is in contact with the first metal layer <NUM> in the first part B-<NUM>.

In the embodiments of the disclosure, the second connecting structure <NUM> may be a homogeneity epitaxy layer. Therefore, the second semiconductor material may be silicon. The thickness of the second connecting structure <NUM> is <NUM> to <NUM>Å.

In the embodiments of the disclosure, the epitaxial growth may be vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, or metal organic chemical vapor deposition.

In some embodiments, continuing to refer to <FIG>, after the second connecting structure <NUM> is formed, the method for forming the semiconductor structure further includes: an insulating medium layer <NUM> is formed on a surface of the second connecting structure <NUM>. A surface of the insulating medium layer <NUM> is flush with a surface of the medium layer <NUM>. A third metal layer <NUM> is formed on the surface of the insulating medium layer <NUM>. A surface of the third metal layer <NUM> is flush with a surface of the first metal layer <NUM>. A third isolation material is filled on the surface of the third metal layer <NUM> and into the gap of the third metal layers <NUM> to form a third isolation layer <NUM>. A surface of the third isolation layer <NUM> is flush with the surface of the first isolation layer <NUM>.

In the embodiments of the disclosure, the material of the insulating medium layer <NUM> may be silicon oxide, silicon nitride, or silicon oxynitride, for example, silicon oxide. The third isolation layer <NUM> may be configured to isolate adjacent third metal layers <NUM> to prevent the third metal layer <NUM> from electric leakage. The material of the third isolation layer <NUM> may be silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. The material of the third metal layer <NUM> may be any material with good electrical conductivity, such as tungsten.

In some embodiments, the gate-all-around structure <NUM> is divided into a first part B-<NUM> and a second part B-<NUM> by the third isolation groove <NUM> in the X-axis direction. The forming the stepped word line structure <NUM> includes: a photoresist layer with a second opening is formed on a surface of the second part; the second opening exposes one end, far away from the first part, of the second part. The second part is etched for a plurality of times by the photoresist layer to form the stepped word line structure <NUM>. During etching for the plurality of times, the size of the second opening in the first direction increases sequentially.

In some embodiments, the forming the stepped word line step <NUM> includes: firstly, a photoresist layer with a second opening is formed on a surface of the second part B-<NUM>. The second opening exposes one end, far away from the first part, of the second part. The second part B-<NUM> is etched through the photoresist layer with the second opening to form a first stepped structure. The first stepped structure includes one step. Secondly, a photoresist layer with a third opening is formed on a surface of the first stepped structure; the third opening exposes part of the first stepped structure; the first stepped structure is etched by the photoresist layer with the third opening to form a second stepped structure. The second stepped structure includes two steps. The size of the third opening in the X-axis direction is greater than the size of the second opening. Thirdly, a photoresist layer with a fourth opening is formed on a surface of the second stepped structure. The fourth opening exposes part of the second stepped structure. The second stepped structure is etched by the photoresist layer with the fourth opening to form a third stepped structure. The third stepped structure includes three steps. The size of the fourth opening in the X-axis direction is greater than the size of the third opening. The abovementioned steps are cycled, and the stepped word line structure <NUM> is finally formed after a plurality of etching processes.

As shown in <FIG>, in the embodiments of the disclosure, the stepped word line structure <NUM> extending in the X-axis direction is formed on the semiconductor substrate <NUM>. The stepped word line structure <NUM> has a length reduced layer by layer from bottom to top in the Z-axis direction.

In other embodiments, the forming the stepped word line structure <NUM> may also include: firstly, a first word line with a first length is formed on a base substrate surface of the second part B-<NUM>. The first word line is electrically connected to a first layer of gate-all-around structure <NUM> at the bottommost layer in the third direction. Secondly, a first isolation unit with a second length is formed on a surface of the first word line. A second word line with a second length is formed on a surface of the first isolation unit. The second word line is electrically connected to a second layer of gate-all-around structure <NUM> at the sub-bottom layer in the third direction. The first length is greater than the second length. The first isolation unit is configured to isolate adjacent first word line and second word line. Thirdly, a second isolation unit with a third length is formed on a surface of the second word line. A third word line with the third length is formed on a surface of the second isolation unit. The third word line is electrically connected to a third layer of gate-all-around structure <NUM> in the third direction from bottom to top. The second length is greater than the third length. The second isolation unit is configured to isolate adjacent second word line and third word line. The abovementioned steps are cycled, and the stepped word line structure <NUM> composed of a plurality of word lines are formed after a plurality of forming processes.

In some embodiments, after the stepped word line structure <NUM> is formed, the method for forming the semiconductor structure further includes: a first metal wire <NUM> connected to the capacitor structure <NUM>, a second metal wire <NUM> connected to the bit line structure <NUM>, and a third metal wire <NUM> connected to the stepped word line structure <NUM> are formed.

In some embodiments, as shown in <FIG>, the forming the first metal wire <NUM>, the second metal wire <NUM>, and the third metal wire <NUM> includes: a barrier layer <NUM> is formed on the surfaces of the stepped word line structure <NUM>, the first isolation layer <NUM>, the second isolation layer <NUM>, and the third isolation layer <NUM>; the barrier layer <NUM> is etched to form a first through hole (not shown) exposing the second metal layer <NUM>, a second through hole (not shown) exposing the bit line structure <NUM>, and a third through hole (not shown) exposing the stepped word line structure <NUM>. The first metal wire <NUM> connected with the capacitor structure <NUM> is formed in the first through hole, the second metal wire <NUM> connected with the bit line structure <NUM> is formed in the second through hole, and the third metal wire <NUM> connected with the stepped word line structure <NUM> is formed in the third through hole.

In the embodiments of the disclosure, the materials of the first metal wire <NUM>, the second metal wire <NUM>, and the third metal wire <NUM> may be composed of any conductive metal material, such as titanium nitride. In other embodiments, the materials of the first metal wire <NUM>, the second metal wire <NUM>, and the third metal wire <NUM> may also be copper, aluminum, copper aluminum alloy, tungsten, or other conductive metals.

In the embodiments of the disclosure, the gate-all-around structure and the semi-capacitor structure are formed at the same time, so that a process for preparing the semiconductor structure can be simplified, and the manufacturing cost of the semiconductor structure can be reduced. In addition, since the capacitor structure in the embodiments of the disclosure extends in the second direction, that is, the capacitor structure in the embodiments of the disclosure is horizontal. Compared with a vertical capacitor structure with a large aspect ratio, the horizontal capacitor structure can reduce the possibility of tipping or breaking, so that the stability of the capacitor structure can be improved. Moreover, the stacked structure formed by stacking a plurality of capacitor structures in the third direction can form a three-dimensional semiconductor structure, so as to improve the integration degree of the semiconductor structure and realize miniaturization.

In addition, the embodiments of the disclosure further provide a semiconductor structure. <FIG> illustrates a sectional view of the semiconductor structure according to an embodiment of the disclosure, as shown in <FIG>, the semiconductor structure <NUM> includes: a substrate. The substrate includes a first area A and a second area B arranged in a Y-axis direction. The second area B includes a first part B-<NUM> and a second part B-<NUM> arranged in an X-axis direction. The second area B includes active columns <NUM> arranged in an array in the X-axis direction and a Z-axis direction. The semiconductor structure <NUM> further includes: capacitor structures <NUM> located in the first area A and extending in the Y-axis direction, and gate-all-around structures <NUM> located in the second area B. The gate-all-around structures <NUM> surround surfaces of the active columns <NUM>.

In some embodiments, the capacitor structure <NUM> includes a first metal layer <NUM>, a second medium layer <NUM>, and a second metal layer <NUM>. The gate-all-around structure <NUM> includes a medium layer <NUM> and a first metal layer <NUM>. The medium layer <NUM> includes a first medium layer <NUM> and a second medium layer <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: first isolation layers <NUM> located between adjacent first metal layers <NUM> and located on surfaces of the first metal layers <NUM>. The first isolation layers <NUM> are configured to isolate adjacent first metal layers <NUM> to prevent the first metal layers <NUM> from electric leakage.

In some embodiments, the semiconductor structure <NUM> further includes: first connecting structures <NUM> connecting the capacitor structures <NUM> and the gate-all-around structures <NUM>, and support structures <NUM> configured to support the capacitor structures <NUM> and the gate-all-around structures <NUM>. The support structure <NUM> is embedded into the semiconductor substrate <NUM> to achieve a more stable support effect.

In some embodiments, the semiconductor structure <NUM> further includes: a bit line structure <NUM> located in the second area B and extending in the first direction.

In some embodiments, the semiconductor structure <NUM> further includes: a second connecting structure <NUM> and a stepped word line structure <NUM>. The gate-all-around structure <NUM> is connected to the stepped word line structure <NUM> through the second connecting structure <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: first isolation layers <NUM> located between first metal layers <NUM> and located on the surfaces of the first metal layers <NUM>. The first isolation layers <NUM> are configured to isolate adjacent first metal layers <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: a second isolation layer <NUM> located between adjacent first connecting structures <NUM>. The second isolation layer <NUM> is configured to isolate adjacent first connecting structures <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: a second isolation layer <NUM> located between adjacent second connecting structures <NUM>. The second isolation layer <NUM> is configured to isolate adjacent second connecting structures <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: an insulating medium layer <NUM> located on a surface of the second connecting structure <NUM>. A surface of the insulating medium layer <NUM> is flush with a surface of the medium layer <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: a third metal layer <NUM> located on the surface of the insulating medium layer <NUM>. A surface of the third metal layer <NUM> is flush with the surface of the first metal layer <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: third isolation layers <NUM> located between third metal layers <NUM> and on the surfaces of the third metal layers <NUM>. The third isolation layers <NUM> are configured to isolate adjacent third metal layers <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: a first metal wire <NUM>, a second metal wire <NUM>, and a third metal wire <NUM>. The first metal wire <NUM> is located on a surface of the capacitor structure <NUM> and is electrically connected with the capacitor structure <NUM>. The second metal wire <NUM> is located on a surface of the bit line structure <NUM> and is electrically connected with the bit line structure <NUM>. The third metal wire <NUM> is located on a surface of the stepped word line structure <NUM> and is electrically connected with the stepped word line structure <NUM>.

In some embodiments, the semiconductor structure <NUM> further includes: a barrier layer <NUM>. The first metal wire <NUM>, the second metal wire <NUM>, and the third metal wire <NUM> are located in the barrier layer <NUM>.

The semiconductor structure according to the embodiments of the disclosure is similar to the method for forming the semiconductor structure provided by the abovementioned embodiments. The technical features not disclosed in detail in the embodiments of the disclosure refer to the abovementioned embodiments for understanding, and will not be elaborated herein. The semiconductor structure is not forming part of the claimed invention.

According to the semiconductor structure according to the embodiments of the disclosure, the capacitor structure extends in the second direction. That is to say, the capacitor structures are arranged horizontally, and the horizontal capacitor structure can reduce the possibility of tipping or breaking, so as to improve the stability of the capacitor structure. In addition, the capacitor structures are arranged in the first direction and the third direction. A stacked structure that is formed by stacking a plurality of capacitor structures in the third direction can form a three-dimensional semiconductor structure, so as to improve the integration degree of the semiconductor structure and realize miniaturization.

In several embodiments provided by the disclosure, it is to be understood that the disclosed device and method may be implemented in a non-target mode. The above described device embodiments are only schematic. For example, the division of the units is only logical function division. In actual implementation, there may be other division modes, for example, a plurality of units or components may be combined, or may be integrated into another system, or some features may be ignored or not implemented.

The characteristics disclosed in several method or device embodiments provided in the disclosure may be freely combined without conflicts to obtain new method embodiments or device embodiments.

Claim 1:
A method for forming a semiconductor structure (<NUM>), characterized by comprising:
providing a substrate, the substrate comprising a first isolation groove (<NUM>) extending in a first direction and a plurality of active columns (<NUM>) arranged in an array along the first direction (X) and a third direction (Z), the substrate being divided into a first area (A) and a second area (B) by the first isolation groove (<NUM>) along a second direction (Y), the active columns (<NUM>) being supported through support structures (<NUM>), the first direction, the second direction and the third direction being perpendicular to each other in pairs, the first direction and the second direction being parallel to an upper surface of the substrate;
forming semi-capacitor structures (<NUM>) located in the first area and gate-all-around structures (<NUM>) located in the second area in gaps between the active columns (<NUM>);
processing the active columns (<NUM>) and the semi-capacitor structures (<NUM>) in the first area to form capacitor structures (<NUM>) extending in the second direction; and
forming first connecting structures (<NUM>) connecting the gate-all-around structures (<NUM>) and the capacitor structures (<NUM>) in the first isolation groove (<NUM>).
wherein the forming semi-capacitor structures (<NUM>) and gate-all-around structures (<NUM>) comprises:
sequentially forming a medium layer (<NUM>) and a first metal layer (<NUM>) on surfaces of the active columns (<NUM>) in the first area and the second area;
the first metal layer (<NUM>) located in the first area constituting the semi-capacitor structure (<NUM>), and the medium layer (<NUM>) and the first metal layer (<NUM>) located in the second area constituting the gate-all-around structure (<NUM>).