Patent Description:
Various semiconductor devices such as, e.g., backside-illuminated (BSI) image sensors require a thin crystalline semiconductor layer with a low total thickness variation (TTV).

Conventionally, thin crystalline silicon layers with low TTVs are manufactured by processes including grinding and dopant selective chemical etching of a semiconductor substrate, e.g. a wafer.

While grinding offers high removal rates of semiconductor material, the TTV after the grinding process is too high for many devices such as, e.g., BSI image sensors. On the other hand, dopant selective chemical etching allows achieving thin crystalline semiconductor layers with small TTVs. However, dopant selective chemical etching requires the thin crystalline semiconductor layer (device layer) to have a low doping density (e.g. less than <NUM><NUM> cm-<NUM>) to be resistant to the chemical etchant used in the process. This prevents this method from being used for manufacturing devices having high doping densities in at least parts thereof in order to achieve a high device performance.

For instance, certain 3D image sensors require a high doping density in at least parts thereof to achieve good demodulation contrast and depth resolution. The low doping density constraint of the device layer when subjected to dopant selective chemical etching prevents such sensors from being fabricated in BSI geometry. This, in turn, limits the possibility to shrink the pixel size of such image sensors to achieve higher image resolution.

An additional challenge for BSI technology is the alignment of lithography processes done on the wafer backside after bonding and thinning to features defined on the front side before the device layer is manufactured. <CIT> describes a method of fabricating a semiconductor-on-insulator SOI substrate including a thin device layer of high evenness. The device layer was formed by etching a sacrificial substrate down to an etch stop layer, removing the etch stop layer and cyclically thinning the device layer. <CIT> describes a method of fabricating a SOI substrate including a thin device layer of high evenness. The device layer was formed by etching a sacrificial substrate down to an etch stop layer and by removing the etch stop layer using an etchant comprising hydrofluoric acid, hydrogen peroxide, and acetic acid. <CIT> describes a method of fabricating a semiconductor substrate including a device layer. The semiconductor substrate includes a III-V GaN etch stop layer on a surface of the device layer.

According to an aspect of the disclosure, a method of manufacturing a semiconductor device is described. The method comprises providing a semiconductor substrate. The semiconductor substrate comprises a high-doped semiconductor substrate layer having a doping density which is in a range between <NUM>×<NUM><NUM> cm-<NUM> to <NUM>×<NUM><NUM> cm-<NUM>, a high-doped semiconductor device layer, and a low-doped semiconductor etch stop layer of silicon arranged between the high-doped semiconductor substrate layer and the high-doped semiconductor device layer. A doping density of the high-doped semiconductor device layer is equal to or greater than <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, or <NUM>×<NUM><NUM> cm-<NUM>. A doping density of the low-doped semiconductor etch stop layer is less than <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>. The low-doped semiconductor etch stop layer has a thickness between <NUM> and <NUM>. The low-doped semiconductor etch stop layer borders the high-doped semiconductor device layer. The high-doped semiconductor substrate layer is removed, wherein the removing comprises dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer. Further, the low-doped semiconductor etch stop layer is thinned to generate an exposed surface of the high-doped semiconductor device layer.

According to another aspect of the disclosure, a semiconductor wafer comprises a low-doped semiconductor device layer, a high-doped semiconductor device layer arranged over the low-doped semiconductor device layer, and a low-doped semiconductor etch stop layer of silicon arranged over the high-doped semiconductor device layer. A doping density of the high-doped semiconductor device layer is equal to or greater than <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, or <NUM>×<NUM><NUM> cm-<NUM>. A doping density of the low-doped semiconductor etch stop layer is less than <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>. The low-doped semiconductor etch stop layer borders the high-doped semiconductor device layer. The low-doped semiconductor etch stop layer has a thickness between <NUM> and <NUM>, an exposed etch stop surface and a total thickness variation, TTV, of equal to or less than <NUM>.

The features of the various illustrated embodiments can be combined unless they exclude each other and/or can be selectively omitted if not described to be necessarily required. Embodiments are depicted in the drawings and are exemplarily detailed in the description which follows.

It is to be understood that the features of the various exemplary embodiments and examples described herein may be combined with each other, unless specifically noted otherwise.

Referring to <FIG>, a device semiconductor substrate <NUM> includes a high-doped semiconductor substrate layer <NUM>, a high-doped semiconductor device layer <NUM> and a low-doped semiconductor etch stop layer <NUM>, referred to as substrate <NUM>, substrate layer <NUM>, device layer <NUM> and etch stop layer <NUM> respectively hereinafter. The etch stop layer <NUM> is arranged between the substrate layer <NUM> and the device layer <NUM>.

The substrate <NUM> may, e.g., be a semiconductor wafer. The substrate <NUM> may be made of any semiconductor material, e.g., Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc. Without loss of generality, the following description relates to a substrate <NUM> which is a silicon wafer.

The substrate layer <NUM> has a doping density which is in a range between <NUM>×<NUM><NUM> cm-<NUM> to <NUM>×<NUM><NUM> cm-<NUM>, in particular <NUM>×<NUM><NUM> cm-<NUM> to <NUM>×<NUM><NUM> cm-<NUM> or e.g. <NUM>-<NUM>×<NUM><NUM> cm-<NUM>. The substrate layer <NUM> may be doped with boron, arsenic or phosphorus. In some applications arsenic may be advantageous as a dopant since it diffuses less and sharper doping profiles can be obtained. The substrate layer <NUM> may, e.g., have a thickness between about <NUM> and <NUM>. In the example shown in <FIG>, the thickness may, e.g., be <NUM>.

The doping density of the low-doped semiconductor etch stop layer <NUM> is less than <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>. The low-doped semiconductor etch stop layer <NUM> may be an epitaxial layer. It has a layer thickness of <NUM>-<NUM>, in particular <NUM>-<NUM>. The dopant type may, e.g., be of no relevance.

The doping density of the device layer <NUM> is equal to or greater than <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, or <NUM>×<NUM><NUM> cm-<NUM>. The device layer <NUM> may be doped with boron, arsenic, phosphorus, or antinomy. Generally, the dopant of the device layer <NUM> may be the same as the dopant of the substrate layer <NUM> or a different one. Further, the device layer <NUM> may have different doping levels and/or materials in different depths or different areas of the device layer <NUM>, i.e. may be structured in terms of doping levels and/or doping materials and/or doping depths and/or doping areas.

The substrate <NUM> may further include a low-doped semiconductor device layer <NUM>. Hence, a device layer <NUM> of the semiconductor substrate <NUM> may include solely the device layer <NUM> or the device layer <NUM> and the low-doped semiconductor device layer <NUM> as depicted in <FIG>.

In the latter case, the device layer <NUM> may, e.g., be a high-doped p-buried layer implant introduced into the low-doped semiconductor device layer <NUM>. More specifically, the device layer <NUM> may be fabricated by implanting a dopant such as, e.g., boron (implant energy of e.g. <NUM> keV). The implant impurities (e.g. boron impurities) may then be activated by annealing (e.g. at <NUM>). Implant damages of the low-doped semiconductor device layer <NUM> may, e.g., be removed, for example by surface oxidation and wet chemical oxide removal.

An alternative method may be to grow the full layer stack comprising the etch stop layer <NUM> and the high-doped and low-doped device layers <NUM>, <NUM> by epitaxy in one or more runs with in-situ doping.

Further, the substrate <NUM> may comprise a functional layer stack <NUM>. The design of the functional layer stack is dependent on the semiconductor device to be manufactured from the substrate <NUM>. For example, the functional layer stack <NUM> may include one or more metal contact layers 150_2, insulating (e.g. SiO) layers 150_1, 150_3 encapsulating the metal contact layer(s) 150_2 and a wafer bonding (e.g. SiO) layer 150_4 for wafer bonding.

The device layer <NUM> (in particular the low-doped semiconductor device layer <NUM>) and the functional layer stack <NUM> may be structured depending on the semiconductor device to be manufactured from the substrate <NUM>. In <FIG>, by way of example, the low-doped semiconductor device layer <NUM> is structured by (optional) insulation trenches 130L_t. The metal contact layer(s) 150_2 are structured by groups of metal electrodes 150_2e. As will be described in more detail further below, the groups of metal electrodes 150_2e together with the insulating trenches 130L_t form pixels of a BSI image sensor used here as an example of a semiconductor device in accordance with the disclosure. In other embodiments the functional layer stack <NUM> may include other semiconductor devices such as, e.g., power semiconductor chips (see e.g. <FIG>).

Substrate <NUM> may be formed by complementary metal-oxide-semiconductor (CMOS) technology. The growth direction of the various layers <NUM>, <NUM>, <NUM>, <NUM> atop the substrate layer <NUM> is indicated by arrow A.

As mentioned before, the low-doped semiconductor device layer <NUM> (in which the device layer <NUM> has been implanted) may be designed in various different ways in accordance with the characteristics and functionality of the semiconductor device to be manufactured. In the example described herein, the low-doped semiconductor device layer <NUM> may have been formed by Si epitaxy, may, e.g., have a thickness of about <NUM>-<NUM>, in particular <NUM>-<NUM> (which has been found to be preferable for high-performance time-of-flight (ToF) image sensors). Further, optionally desired doping profiles are generated in the low-doped semiconductor device layer <NUM>. For example, this may include creating a doping profile in epitaxy or by thermally induced interdiffusion from the buried device layer <NUM> into the epitaxial low-doped semiconductor device layer <NUM>. An exemplary doping profile of the (buried) device layer <NUM> in the low-doped semiconductor device layer <NUM> will be explained in more detail further below in conjunction with <FIG>.

The low-doped semiconductor device layer <NUM> and the semiconductor device layer <NUM> may have a total thickness of equal to or less than <NUM>, or <NUM>, or <NUM>, or <NUM>, or <NUM>. However, it is also possible that the device layer <NUM> is (much) thicker, e.g. has a thickness of equal to or greater than <NUM> or <NUM>.

The optional insulating trenches 130L_t may be formed to create optically and/or electrically isolated pixels in the low-doped semiconductor device layer <NUM>. Further, as mentioned above, the formation of groups of metal electrodes 150_2e, e.g. metal contacts and gates, may define a matrix of pixels on the low-doped semiconductor device layer <NUM>.

The wafer bonding layer 150_4 may be formed by silicon oxide deposition and polishing. The wafer bonding layer 150_4 may have a thickness between, e.g., <NUM> to <NUM> and may, e.g., create an atomically smooth (e.g. having an unevenness of below <NUM> root mean square (RMS)) oxide surface layer.

Further, a carrier semiconductor substrate <NUM> may be provided. The carrier semiconductor substrate <NUM> may be a semiconductor wafer, e.g. a silicon wafer. The carrier semiconductor substrate <NUM> may comprise a carrier substrate layer 180_1 and a wafer bonding layer 180_4. The carrier substrate layer 180_1 may have a thickness in the same range as the thickness of the substrate layer <NUM>, in this example, e.g., a thickness of <NUM>. The carrier semiconductor substrate <NUM> may (also) contain integrated circuits (ICs - not shown) and/or one or more metal wiring layer(s) (not shown) to interconnect the ICs either to integrated circuitry (e.g. specific pixels) on the substrate <NUM> or to electrodes or die pads (not shown) on the carrier semiconductor substrate <NUM> used as external terminals.

The wafer bonding layer 180_4 may, e.g., be a SiO layer having a layer thickness in a range between <NUM>-<NUM>. The wafer bonding layer 180_4 may be atomically smooth (e.g. having an unevenness below <NUM> RMS).

The carrier semiconductor substrate <NUM> may be used in a manufacturing process for devices featuring BSI geometry, e.g. for BSI image sensors, in particular for ToF image sensors employing BSI technology.

Referring to <FIG>, the substrate (e.g. device wafer) <NUM> and the carrier semiconductor substrate (e.g. carrier wafer) <NUM> are then bonded together with their respective front sides. Voids and particles in the bond interface <NUM> formed by the wafer bonding layers 150_4 and 180_4 should be avoided. Annealing may be used to make the bond stable and durable.

If the carrier semiconductor substrate <NUM> contains for instance ICs to be connected to specific integrated circuitry (e.g. specific pixels) on the substrate <NUM>, the bond between the substrate <NUM> and the carrier semiconductor substrate <NUM> should be generated with high spatial accuracy, preferably equal to or less than <NUM> or <NUM>. <FIG> illustrates an intermediate stage of fabrication after semiconductor substrate bonding (e.g. wafer bonding) and flipping the bonded device.

Referring to <FIG>, the substrate layer <NUM> of the substrate <NUM> is then partially removed by, e.g., grinding. A thickness of, e.g., <NUM>-<NUM> of the substrate layer <NUM> may be removed. The partial removal may stop at about <NUM>-<NUM>, in particular <NUM>-<NUM>, of the substrate layer <NUM> for subsequent wet chemical removal, as will be explained in more detail in conjunction with <FIG>. The TTV after the partial removal (e.g. grinding) process may, for example, be <NUM>-<NUM> on, e.g., a <NUM> wafer, which is too high for some devices, e.g. for image sensor products.

Referring to <FIG>, the substrate layer <NUM> may then be completely removed by dopant selective chemical etching until the etch stop layer <NUM> is reached. The removal by dopant selective chemical etching may remove a thickness between <NUM>-<NUM>, in particular <NUM>-<NUM> or <NUM>-<NUM>, of the remainder of the substrate layer <NUM>. For the dopant selective chemical etching process, a dopant selective wet chemical solution may be used, which will etch the remainder of the substrate layer <NUM> quickly at, e.g., a rate of <NUM>-<NUM> pm/min. The dopant selective chemical etching process will hold at the etch stop layer <NUM> before reaching the device layer <NUM>.

More specifically, a dopant selective etchant such as, e.g., HNA may be used. This is a mixture of hydrofluoric acid (HF), nitric acid (HNO<NUM>), acetic acid (CH<NUM>COOH) and water. A typical concentration may be HF at <NUM> wt%, HNO<NUM> at <NUM> wt%, and CH<NUM>COOH at 50wt%. The HNA mixture etches high-doped silicon quickly, e.g. with an etch rate of <NUM>-<NUM>/min. Low-doped materials are etched very slowly, e.g. at a rate of <NUM> pm/min. Thereby, the etchant removes the highly doped substrate and with it all roughness and on-substrate inhomogeneity brought in by the initial rough grinding process. The dopant selective chemical etching stops "inside" the etch stop layer <NUM> where the doping density falls below a certain limit (as described in more detail further below in conjunction with <FIG>).

The TTV of the remaining semiconductor layers on top of the carrier semiconductor substrate <NUM> (i.e. of the layers of the substrate <NUM> at the intermediate stage of fabrication shown in <FIG>) may, e.g., be between <NUM> and <NUM> on, e.g. a <NUM> wafer. It is much lower than the TTV of the remaining semiconductor layers on top of the carrier semiconductor substrate <NUM> at the intermediate stage of fabrication shown in <FIG>, and is thus suitable for, e.g., image sensor products. More specifically, referring to <FIG>, a TTV of e.g. <NUM> was achieved, which is sufficient and can be further improved by improving the homogeneity of the epitaxial layer thickness of the etch stop layer <NUM> and the low-doped semiconductor device layer <NUM>.

Referring to <FIG>, the etch stop layer <NUM> is then removed to expose the device layer <NUM>. An exposed surface of the device layer <NUM> is denoted by reference sign <NUM>. The device layer <NUM> may then have a low TTV since inhomogeneities from the grinding process (<FIG>) are neutralized by the etch stop layer <NUM>. At the same time the device layer <NUM> can be highly doped since it does not come in contact with a dopant selective etch chemistry.

The etch stop layer <NUM> should be thick enough to provide a reliable barrier for the dopant selective wet chemical etching solution to protect the device layer <NUM>. Dopant inter-diffusion from the substrate layer <NUM> and from the device layer <NUM> may reduce its effective thickness, especially when high temperature processes at temperatures equal to or greater than, e.g., <NUM> are applied to the substrate (device wafer) <NUM> and the carrier semiconductor substrate (carrier wafer) <NUM>.

On the other hand, the etch stop layer <NUM> should not be too thick since then the additional thickness variations caused during its removal (see <FIG>) would be too high to achieve the target of having a low TTV of, e.g., equal to or less than <NUM> after the removal of the etch stop layer <NUM>. The thickness of the etch stop layer <NUM> is selected to be between <NUM> and <NUM>, wherein a thickness of <NUM> ± <NUM> (or ± <NUM>, or ± <NUM>, or ± <NUM>) has shown to be a good compromise for both challenges mentioned above.

Differently put, the provision of the etch stop layer <NUM> allows for implementing a device layer <NUM> (as it is desired for device performance) and the small thickness of the etch stop layer <NUM> allows to preserve the small initial TTV at the onset of thinning throughout the thinning process until it ends at the exposed surface <NUM> of the device layer <NUM>.

The optimum thickness of the etch stop layer <NUM> may also depend on the type of dopant. The etch stop layer <NUM> may be made thinner (e.g. thinner than <NUM>) if heavy dopant atoms such as arsenic are used in the substrate layer <NUM> and/or in the device layer <NUM>. Those dopants show less inter-diffusion into the etch stop layer <NUM> during high temperature processing, resulting in that the effective thickness of the etch stop layer <NUM> is reduced by inter-diffusion to a lesser extent (and therefore the actual thickness can be designed smaller).

The removal of the etch stop layer <NUM> may be carried out by chemical etching or by chemical mechanical polishing (CMP). Chemical etching may be carried out by a wet chemical etching process or a dry chemical etching process.

CMP may be the preferred method since the CMP process has more degrees of freedom that can be controlled than the wet or dry chemical etching process (where additional unevenness may be caused by different etching rates). Using CMP the removal rate can be tuned to achieve a minimum total thickness variation across the wafer. For example, if the remaining etch stop layer <NUM> is typically thinner at the edge of the substrate (wafer) than in the middle of the substrate (wafer), which might be due to higher etch rates in the preceding steps due to heating of the etchant towards the substrate (wafer) edge, then the CMP removal rate can be reduced at the substrate (wafer) edge to compensate this thickness variation. An example of such improvement of TTV by CMP will be described further below in conjunction with <FIG>.

The total amount of material to be removed in one run is limited to < <NUM>, preferably < <NUM>. Also for this reason, it is desirable to have the etch stop layer <NUM> as thin as possible. This, however, opposes the requirement for a robust etch stop process without runaway etching as well as inter-diffusion of dopants from the neighboring substrate layer <NUM> and device layer <NUM>. To enable a thinner etch stop layer <NUM>, while at the same time maintaining a robust etch stopping behavior in presence of inter-diffusing dopants from the device layer <NUM>, the etch stop layer <NUM> may be counter-doped with a material of opposing dopant polarity, as will be described in more detail further below in conjunction with <FIG>.

Referring to <FIG>, at S1 a semiconductor substrate is provided comprising a substrate layer, a device layer and a etch stop layer arranged between the substrate layer and the device layer. As mentioned above, the etch stop layer has a thickness between <NUM> and <NUM>.

At S2 the substrate layer is removed. The removing comprises dopant selective chemical etching which stops at the etch stop layer. An exemplary intermediate stage of fabrication obtained by S2 is illustrated in <FIG>.

At S3 the etch stop layer is thinned to generate an exposed surface of the device layer. A stage of fabrication which may be obtained after carrying out S3 is illustrated in <FIG>.

<FIG> illustrates a simplified final ToF image sensor device as an example of a semiconductor device <NUM> manufactured in accordance with aspects of the disclosure. The semiconductor device <NUM> may include micro-lenses <NUM>, a metal grid <NUM>, a through semiconductor via <NUM> and an insulating layer <NUM>. The through semiconductor via <NUM> may be configured to electrically contact the buried metal contact layer(s) 150_2 beneath the low-doped semiconductor device layer <NUM> and the device layer <NUM>. The micro-lenses <NUM> may be fabricated on top of the pixel array and the metal grid <NUM> may be arranged to direct or shield incident light from certain parts of the pixels (as defined by the insulating trenches 130L_t and the groups of metal electrodes 150_2e). Electrode pads <NUM> (e.g. made of Al or Cu) may be placed on the through semiconductor vias <NUM>.

Finally, the semiconductor device <NUM> is tested, diced and placed in an adequate package which allows infrared light to reach the pixel array surface. To achieve ToF 3D imaging this package may be assembled in a system which includes an infrared light source such as laser diode to emit light in a temporarily modulated or pulsed way. The ToF of the reflections of these light pulses of a free-dimensional scene is then detected by the pixels of the semiconductor device <NUM>, and a 3D rendering of the scene may be reconstructed.

<FIG> illustrate an exemplary process flow to manufacture a semiconductor device in accordance with aspects of the disclosure. The exemplary stages illustrated in <FIG> can selectively be combined with manufacturing stages described above and vice versa. In particular, the process flow shown in <FIG> illustrates trimming of the wafer edge during grinding to reduce unwanted particle density due to chipping at the wafer edge and/or a deposition of an edge protection layer which protects the device layers <NUM>, <NUM> especially during wet etching (see <FIG>). Both these processes (trimming of the wafer edge and/or depositing of an edge protection layer) are generally available and not bound to the specific process flow of <FIG>.

<FIG> illustrates a device wafer <NUM> having the substrate layer <NUM>. This high-doped semiconductor wafer may be a <NUM> Si high-doped backside epitaxial sealing wafer.

In <FIG>, the etch stop layer <NUM> is generated. The etch stop layer <NUM> may be an epitaxial layer of a thickness of <NUM>-<NUM>.

In <FIG> the low-doped semiconductor device layer <NUM> (e.g. boron, doping density of <NUM>×<NUM><NUM> cm-<NUM>, thickness of <NUM> Si) may be generated as an epitaxial layer. Then, the device layer <NUM> may be formed as a buried implant layer (e.g. p-buried implant layer).

In <FIG> the deep trench isolation (i.e. insulating trenches 130L_t) may be generated. Further, zero layer deep trenches <NUM> may be produced.

In <FIG> the ToF metal contact layers 150_2 are applied.

In <FIG> the wafer bonding layer 150_4 is applied by, e.g., using an oxide formation and a CMP process.

In <FIG> the processed device wafer of <FIG> is wafer bonded to a carrier wafer <NUM> by, e.g., silicon direct bonding (SDB) and/or silicon fusion bonding (SFB).

<FIG> illustrate an exemplary two-stage grinding process and an edge trimming and protection step carried out between the two grinding stages. More specifically, in <FIG> a first stage grinding is performed to a target thickness of, e.g., <NUM> of the residual substrate layer <NUM>. Then, in <FIG> the wafer edges are trimmed (e.g. <NUM> wide) and a TEOS (tetraethyl orthosilicate) oxide <NUM> (or any other edge protection insulating material) is deposited by, e.g., plasma-enhanced chemical vapor deposition (PECVD).

In <FIG> a second stage grinding is performed to a target thickness of, e.g., <NUM> of the substrate layer <NUM>.

<FIG> illustrates wet etching which stops on the etch stop layer <NUM>. A cleaning of the surface of the etch stop layer <NUM> may follow. A TTV of about <NUM> may be obtained.

<FIG> illustrates CMP of the etch stop layer <NUM>. The TTV of <NUM> may substantially be preserved. Additionally, zero layer marks <NUM> may be revealed by this step so they are visible on the wafer surface in subsequent process steps.

<FIG> then illustrates process stages which are specifically used when a ToF BSI image sensor is fabricated. Briefly, in <FIG> a tungsten grid <NUM> may be applied and a lithography mask <NUM> (e.g. SiO/SiN) may be applied for TSV (through silicon via) formation.

<FIG> illustrates a TSV etch and a filling the etch hole with a metal, e.g. Cu.

In <FIG> and <FIG> an electrode pad (e.g. Al pad) <NUM> is applied and the micro-lenses <NUM> are fabricated.

<FIG> illustrates a simulated doping density profile in silicon of a wafer after forming the low-doped semiconductor (i.e. Si) etch stop layer <NUM> and the semiconductor (i.e. Si) device layers <NUM>, <NUM> on the high-doped semiconductor (i.e. Si) substrate layer <NUM> corresponding to the intermediate fabrication stage shown in <FIG>. The etch stop layer <NUM> is a Si epitaxial layer situated between the substrate layer <NUM> and the device layer <NUM>. Only semiconductor (i.e. Si) layers are shown, other materials such as SiO or metals are omitted. In this case, the substrate layer <NUM> is arsenic doped (n-type) and the device layers <NUM> and <NUM> are boron doped (p-type). This leads to a compensation of both dopants and thus to a low electrical carrier density in a certain range within the etch stop layer <NUM>. By way of example, etching has been done for <NUM> with an etch rate in the high-doped semiconductor (i.e. Si) device layer of about <NUM> pm/min.

<FIG> illustrates the doping density profile measured by spreading resistance profiling (SRP) on a device Si substrate (wafer) <NUM> after removing the substrate layer <NUM> with dopant selective HNA wet etch corresponding to the intermediate fabrication stage shown in <FIG>. Hence, in <FIG> the depth <NUM> corresponds to the surface of the low-doped Si etch stop layer <NUM>. The encircled area <NUM> in <FIG> corresponds to the encircled area <NUM> in <FIG>.

By comparing the measured doping density profile of <FIG> to the simulated doping density profile of <FIG> it can be inferred that the doping density limit at which HNA etching stops is about <NUM><NUM> cm-<NUM>. During etching, the temperature at the device Si substrate (wafer) surface has been monitored and it was observed that the temperature dropped from more than <NUM> to about room temperature at a certain point in time and stayed low. This is consistent with the exothermal etching process stopping at a certain depth in the layer stack.

Further, <FIG> shows that the doping density profile only slightly varies between the center of the substrate (wafer) <NUM> and its edge.

To illustrate the effect of a dedicated etch stop layer <NUM> for the thinning process for, e.g., BSI devices having a device layer <NUM>, doping profiles before and after thinning are shown in <FIG> with a dedicated etch stop layer <NUM> and in <FIG> without such dedicated etch stop layer <NUM>.

In <FIG> the hatched area A1 is removed in the first thinning step using dopant selective chemical etching while the hatched area A2 is removed in the second thinning stage using, e.g., non-selective dry or wet etching or CMP. In <FIG> relating to BSI image sensor fabrication without using a etch stop layer <NUM>, the hatched area A1 showing the first thinning step using dopant selective chemical etching is also depicted. The main difference between the BSI image sensor fabrication without (<FIG>) and with (<FIG>) using a etch stop layer <NUM> is that the device layer <NUM> is etched away by the HNA etchant in <FIG> while in <FIG> the etching stops clearly before reaching the device layer <NUM>. Hence, for a device, which should contain a high-doped layer at the surface, a dedicated etch stop layer <NUM> is needed.

Further, the layer thickness was measured after thinning with and without using a dedicated etch stop layer <NUM>. If a dedicated etch stop layer <NUM> was used the TTV of the substrate <NUM> after thinning was equal to or less than <NUM> (in this example, a TTV of <NUM> was measured). If no dedicated etch stop layer <NUM> was used, a TTV of
<NUM> was measured.

Referring to <FIG>, the rounded form R (indicated in <FIG>) of the doping profile within the etch stop layer <NUM> is attributed to dopant inter-diffusion both from the substrate layer <NUM> and from the device layer <NUM>. The effect of counter-doping the etch stop layer <NUM> is illustrated by a comparison of <FIG> (which corresponds to <FIG>) and <FIG> shows a doping profile of an etch stop layer <NUM> with implanted n-type counter-doping of a doping density C. In case of a p-type (e.g. boron) doped semiconductor device layer <NUM>, <NUM>, the etch stop layer <NUM> may be n-type doped, e.g. with arsenic, phosphorus or antinomy. This counter-doping compensates the dopant inter-diffusion at R. If the doping density C of counter-doping is close to the doping density of inter-diffusing atoms, the resulting electrical carrier density in the inter-diffused region R of the etch stop layer <NUM> is reduced, and thus it will have a lower etch rate in, e.g., HNA.

<FIG> illustrates a measured layer thickness at different stages of thinning, namely before CMP of the etch stop layer <NUM> at <NUM> and after CMP of the etch stop layer <NUM> at <NUM>. As apparent from <FIG>, in this example the thickness of the substrate <NUM> is reduced by CMP from about <NUM> to about <NUM> (i.e. the etch stop layer <NUM> had a thickness of about <NUM>). <FIG> illustrates the improvement of TTV by the CMP process (which could not be achieved by chemical etching). The improvement can mainly be attributed to the tuning of the removal rate across the wafer radius when using CMP as the method of thinning the etch stop layer <NUM>.

As mentioned earlier, some semiconductor devices as, e.g., BSI image sensors require a high doping density at least in parts of the device layer in order to achieve good device performance. An example of such doping profile required in those semiconductor devices is shown in <FIG>. As mentioned before, the TTV of the semiconductor device <NUM> may be equal to or less than <NUM>. In the example shown in <FIG>, the semiconductor device <NUM> includes the device layer <NUM> having the device layer <NUM> and the low-doped semiconductor device layer <NUM> followed by an insulating layer <NUM> (which may, e.g., correspond to the insulating layer 150_1) and by a semiconductor substrate layer <NUM> implementing, e.g., ICs or other semiconductor device structures.

<FIG> illustrates an exemplary semiconductor device <NUM> before grinding and etching, i.e. at a stage of fabrication similar to that shown in <FIG>. Semiconductor device <NUM> distinguishes from the semiconductor device shown in <FIG> and <FIG> in that the semiconductor device <NUM> implements power semiconductor transistors rather than an image sensor. More specifically, the semiconductor device <NUM> may include a first electrode (e.g. source pad) <NUM>, a second electrode (e.g. gate pad) <NUM> and an insulating layer (e.g. imide layer) <NUM>. Integrated circuitry such as, e.g., transistors, in particular power transistor, may be provided in the device layer <NUM> and electrically connected to the first and second electrodes <NUM>, <NUM>. Further, the semiconductor device <NUM> includes the etch stop layer <NUM> and the substrate layer <NUM>. In view of the device layer <NUM>, the etch stop layer <NUM> and the substrate layer <NUM> reference is made to the description above in order to avoid reiteration. In particular, the device layer <NUM> may include exclusively a device layer <NUM> (which is structured to implement the transistors) or a combination of the device layer <NUM> and the low-doped semiconductor device layer <NUM> as described above.

<FIG> further illustrates first type alignment features 1550A and second type alignment features 1550B. The first type alignment features 1550A may comprise low-doped regions protruding into the substrate layer <NUM>. The second type alignment features 1550B may comprise high-doped regions protruding into the device layer <NUM>.

The first type and second type alignment feature 1550A, 1550B may be generated by patterning the etch stop layer <NUM> to generate alignment features, which are configured to appear as visible alignment marks at a later stage of the fabrication of the semiconductor device <NUM>. More specifically, the first and second type alignment features 1550A, 1550B are configured to appear as visible alignment marks 1550A' and 1550B', respectively, in or on the exposed surface <NUM> of the device layer <NUM> after thinning.

<FIG> illustrates the semiconductor device <NUM> at a stage of fabrication after grinding and etching down to the etch stop layer <NUM>. Hence, the fabrication stage of <FIG> compares to the fabrication stage illustrated in <FIG> for the example of an image sensor. Again, reference is made to the above description for the sake of brevity and in order to avoid reiteration.

<FIG> illustrates a stage of fabrication of the semiconductor device <NUM> which compares to the stage of fabrication shown in <FIG>, i.e. after the removal of the etch stop layer <NUM>. At this stage of fabrication, the exposed surface <NUM> of the device layer <NUM> is laid bare. The alignment marks are preserved in the etch process removing the etch stop layer <NUM>. More specifically, the first type alignment marks 1550A' (which are, e.g., structured from the etch stop layer <NUM>) and the second type alignment marks 1550B' (which are, e.g., etched out of the device layer <NUM>) are clearly visible thereon. Again, reference is made to the above description for the sake of brevity and in order to avoid reiteration.

The alignment marks 1550A' and 1550B' facilitate backside to front side alignment of lithographic processes. Differently put, the alignment marks 1550A' and 1550B' allow to better align lithographic processes done on the wafer backside after bonding and thinning to features defined on the front side before those steps. For example, returning to the BSI image sensor described above, the alignment marks 1550A' and/or 1550B', if similarly be formed on the exposed surface <NUM> of the device layer <NUM> (compare <FIG>), allow to carry out all steps after wafer bonding (compare <FIG>) with significantly higher accuracy and process reliability.

All characteristics, features and manufacturing variations explained above in conjunction with different embodiments can be selectively combined if not stated to the contrary or excluded by technical constraints. This applies in particular to the semiconductor transistor embodiment and the semiconductor image sensor embodiment described herein.

Claim 1:
A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate (<NUM>) comprising
a high-doped semiconductor substrate layer (<NUM>) having a doping density which is equal to or greater than <NUM>×<NUM><NUM> cm-<NUM>,
a high-doped semiconductor device layer (<NUM>), wherein a doping density of the high-doped semiconductor device layer (<NUM>) is equal to or greater than <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, or <NUM>×<NUM><NUM> cm-<NUM>, and
a low-doped semiconductor etch stop layer (<NUM>) of silicon arranged between the high-doped semiconductor substrate layer (<NUM>) and the high-doped semiconductor device layer (<NUM>), wherein a doping density of the low-doped semiconductor etch stop layer (<NUM>) is less than <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, or <NUM><NUM> cm-<NUM>, the low-doped semiconductor etch stop layer (<NUM>) has a thickness between <NUM> and <NUM> and the low-doped semiconductor etch stop layer (<NUM>) borders the high-doped semiconductor device layer (<NUM>);
removing the high-doped semiconductor substrate layer (<NUM>), the removing comprises dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer (<NUM>); and
thinning the low-doped semiconductor etch stop layer (<NUM>) to generate an exposed surface of the high-doped semiconductor device layer (<NUM>).