Patent Description:
For next-generation <NUM> communication devices, a higher data rate is required for many applications such as augmented reality (AR)/virtual reality (VR), and <NUM> multiple-input and multiple-output (MIMO). A design shift towards millimeter-wave (mm-Wave) frequency supports this higher data rate. Meanwhile, a broader bandwidth is required to facilitate the higher data rate. For example, a broader bandwidth should cover the <NUM> spectrum including the <NUM>, <NUM>, <NUM>, and <NUM> bands.

Conventional RF frontend LNA circuits have a limited performance at high frequency operations due to high frequency parasitic effects of the LNA components. This often leads to a lower bandwidth, input impedance mismatches, and a degraded noise figure for the RF frontend circuit.

Prior art document <CIT> discloses a multi-stage amplifier is provided that uses tunable transmission lines, as well as a calibration method for the multi-stage amplifiers. A multi-stage amplifier comprises a plurality of tunable amplification stages, wherein each of the tunable amplification stages comprises a tunable resonator based on a transmission line having a tunable element. The tunable elements may vary a capacitance or an inductance to tune a frequency of an applied signal. A calibration method is provided for a multi-stage amplifier having a plurality of transmission lines, an input stage and an output stage. The multi-stage amplifier is calibrated by generating a signal to determine a frequency for a substantially maximum power; generating an error signal by comparing the frequency for the substantially maximum power with a desired frequency; varying a digital control code applied to each of the tunable transmission lines, input stage and output stage until the error signal satisfies predefined criteria.

Prior art document <CIT> discloses a receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a "common source" input stage and a "common gate" output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Prior art document <CIT> discloses an apparatus for reducing a harmonic response in an electronic circuit is provided. The apparatus includes an RF input configured to provide a first signal operating at a radio frequency. The apparatus includes a local oscillator configured to produce a second signal operating at a local oscillator (LO) frequency. The apparatus includes a switching mixer configured to mix the first and second signals. The apparatus includes a notch filter comprising an inductor and a capacitor connected in parallel. The notch filter is directly coupled to an input of the switching mixer in series. The notch filter is tuned such that its resonant frequency is a harmonic of the LO frequency signal. In an aspect, the apparatus also includes a transformer configured to provide the first signal. In an aspect the apparatus also includes a second notch filter comprising a second inductor and a second capacitor connected in parallel.

Prior art document <NPL>, discloses a high gain and linear wideband cascoded two stage Low Noise Amplifier (LNA) operating at <NUM> to <NUM>. Proposed CMOS LNA circuit design yields high gain of <NUM>. 7dB by forming high Q-Network at the input terminal of the amplifying NMOS device and a source degenerative inductor. Noise Figure (NF) of the first cascoded stage is set as low to reduce the NF of the LNA as <NUM>. Proper input and output impedance matching have performed to achieve the input return loss of -<NUM>. 3dB and output return loss of -<NUM>. This circuit has third order input intercept point (IIP3) at -<NUM>. 99dBm and requires <NUM> mW of power at <NUM>. The circuit was designed in Cadence Virtuoso <NUM> technology and simulated using spectre.

Prior art document <NPL>, discloses a wideband low noise amplifier (LNA) for <NUM> wireless applications. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than <NUM> ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries <NUM> RFCMOS technology. The measurement results show a maximum \(S_{<NUM>}\) gain of <NUM> dB gain with a \(-\)<NUM> dB bandwidth from <NUM> to <NUM>. Within this frequency range, the measured \(S_{<NUM>}\) and \(S_{<NUM>}\) are less than \(-\)<NUM> dB and the measured DC power consumption is only <NUM> mW from a single <NUM> V supply.

Prior art document <NPL>, discloses how integrated photonics and electronics, on silicon, can be used to design data communication systems. Various building blocks of such silicon-photonics systems are reviewed. The emphasis is on a <NUM> wireless system which could be suitable for the emerging 5th-generation (<NUM>) cellular networks. The implementation discussed here uses digital baseband optical transmission as opposed to the radio-over-fibre approach.

Prior art document <NPL>, discloses a low-power tunable-band sub-harmonic direct-conversion receiver covering the whole Unlicensed National Information Infrastructure band using <NUM>-µm CMOS technology. The RF band is selected by tuning varactors at the loads of the two-stage low-noise amplifier, while a wideband octet- phase generator is applied at the local oscillator (LO) port. The band tuning of both an LC tank and a transformer and the de- sign of an optimal transformer turn ratio are fully discussed in this paper. Vertical-NPN bipolar junction transistors in a standard CMOS process are used at the mixer switching core for excellent <NUM>/f noise performance. As a result, the receiver achieves a <NUM>/<NUM> voltage gain and <NUM>/<NUM>-dB noise figure with a <NUM>/f noise corner of <NUM> when the RF band is tuned to <NUM>/<NUM>, respectively. The dc current consumption of the RF front-end (including the LO buffer) is <NUM> mA at a <NUM>-V supply.

Prior art document <NPL>, discloses methods and apparatus for a resonant transmit/receive switch with transformer gate/source coupling. The resonant transmit/receive (T/R) switch includes a switchable inductor having a first inductance value for use in receive (Rx) mode and a second inductance value for use in transmit (Tx) mode. The first inductance value is used for input matching to a low noise amplifier in Rx mode. The second inductance value is selected to resonant with parasitic capacitance of the antenna port to produce a high impedance in Tx mode. In one implementation, the switchable inductor is gate sourced coupled to at least one of first and second inductors of a low noise amplifier (LNA), thereby allowing use of smaller inductors due to the resulting coupling factor.

Prior art document <NPL>, discloses a hybrid local positioning and communication system under development within the scope of the EU funded RESOLUTION project. Very stringent requirements to positioning accuracy combined with tight bandwidth limitations demand innovative approaches to combat channel multipath effects. Closely spaced multipath components are the dominant cause of error in the system. Results of system simulations utilizing indoor channel scenarios and measurements using a discrete prototype are presented to prove the possibility of achieving the design goals in spite of limiting spectral regulations.

Prior art document <NPL> discloses a staggered tuning technique in the design of multi-stage tuned amplifiers in which each stage is tuned to a slightly different frequency.

Prior art document <NPL>, discloses a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in <NUM> CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in centre frequency of <NUM>, with <NUM>. 9dB NF, 50Ω input impedance, <NUM> 3dB power bandwidth, <NUM>. 5dB power gain (S21), high reverse isolation (S12).

Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction.

Throughout the specification, and in the claims, the term "connected" means a direct electrical connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" means at least one current signal, voltage signal or data/clock signal. The meaning of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on".

As used herein, unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. The term "substantially" herein refers to being within <NUM>% of the target.

For purposes of the embodiments described herein, unless otherwise specified, the transistors are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. Source and drain terminals may be identical terminals and are interchangeably used herein. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors-BJT PNP/NPN, BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

The invention relates to a low noise amplifier in accordance with the appended independent claim <NUM>. Preferred embodiments are set forth in the appended dependent claims. According to a first aspect, a low noise amplifier (LNA) circuit includes a first amplifier stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with gate capacitance(s) (e.g., Cgs or Cgd) and/or source capacitance(s) (e.g., Cgs or Cds) of the first transistor respectively for a dual-resonance input matching. The LNA circuit includes a second amplifier stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second amplifier stages, where the capacitor transforms a gate capacitance of the third transistor and/or an impedance of the passive network to an optimal load for the first amplifier stage.

In one embodiment, the LNA circuit further includes a third inductor coupled in between the first transistor and the second transistor for a C-L-C transmission line for the first amplifier stage to deliver a signal from the first transistor to the second transistor. In one embodiment, the LNA circuit further includes a variable gain controller coupled to the first amplifier stage to control a gain of the first amplifier stage. In accordance with the invention the LNA circuit further includes a fourth inductor coupled to a drain of the second transistor to resonate with a drain capacitance of the second transistor at a first resonance. In one embodiment, wherein the passive network comprises a fifth inductor in parallel with a first resistor.

In one embodiment, the LNA circuit further includes a sixth inductor coupled in between the third transistor and the fourth transistor for a C-L-C transmission line for the second amplifier stage to deliver an amplifier signal from the third transistor to the fourth transistor. In accordance with the invention the LNA circuit further includes a transformer-based balun coupled between the output port and the fourth transistor, wherein a primary winding of a transformer of the transformer-based balun is to resonate with a drain capacitance of the fourth transistor at a second resonance.

In accordance with the invention the LNA circuit further includes a first capacitor bank coupled in parallel with the first inductor. In accordance with the invention the LNA circuit further includes a second capacitor bank coupled in parallel with the fourth inductor. In accordance with the invention the LNA circuit further includes a third capacitor bank coupled in parallel with the capacitor. In accordance with the invention the LNA circuit further includes a fourth capacitor bank coupled in parallel with the primary winding of the transformer of the transformer-based balun. In accordance with the invention the first, the second, the third, and the fourth capacitor banks are programmable capacitors or the first, the second, the third, and the fourth capacitor banks are digitally tunable capacitors.

<FIG> is a block diagram illustrating an example of a wireless communication device according one embodiment of the invention. Referring to <FIG>, wireless communication device <NUM>, also simply referred to as a wireless device, includes, amongst others, an RF frontend module <NUM> and a baseband processor <NUM>. Wireless device <NUM> can be any kind of wireless communication devices such as, for example, mobile phones, laptops, tablets, network appliance devices (e.g., Internet of thing or IOT appliance devices), etc..

In a radio receiver circuit, the RF frontend is a generic term for all the circuitry between the antenna up to and including the mixer stage. It consists of all the components in the receiver that process the signal at the original incoming radio frequency, before it is converted to a lower frequency, e.g., IF. In microwave and satellite receivers it is often called the low-noise block (LNB) or low-noise downconverter (LND) and is often located at the antenna, so that the signal from the antenna can be transferred to the rest of the receiver at the more easily handled intermediate frequency. A baseband processor is a device (a chip or part of a chip) in a network interface that manages all the radio functions (all functions that require an antenna).

In one embodiment, RF frontend module <NUM> includes one or more RF transceivers, where each of the RF transceivers transmits and receives RF signals within a particular frequency band (e.g., a particular range of frequencies such as non-overlapped frequency ranges) via one of a number of RF antennas. The RF frontend IC chip further includes an IQ generator and/or a frequency synthesizer coupled to the RF transceivers. The IQ generator or generation circuit generates and provides an LO signal to each of the RF transceivers to enable the RF transceiver to mix, modulate, and/or demodulate RF signals within a corresponding frequency band. The RF transceiver(s) and the IQ generation circuit may be integrated within a single IC chip as a single RF frontend IC chip or package.

<FIG> is a block diagram illustrating an example of an RF frontend integrated circuit according to one embodiment of the invention. Referring to <FIG>, RF frontend <NUM> includes, amongst others, an IQ generator and/or frequency synthesizer <NUM> coupled to a multi-band RF transceiver <NUM>. Transceiver <NUM> is configured to transmit and receive RF signals within one or more frequency bands or a broad range of RF frequencies via RF antenna <NUM>. In one embodiment, transceiver <NUM> is configured to receive one or more LO signals from IQ generator and/or frequency synthesizer <NUM>. The LO signals are generated for the one or more corresponding frequency bands. The LO signals are utilized to mix, modulate, demodulated by the transceiver for the purpose of transmitting and receiving RF signals within corresponding frequency bands. Although there is only one transceiver and antenna shown, multiple pairs of transceivers and antennas can be implemented, one for each frequency bands.

<FIG> is a block diagram illustrating an RF transceiver integrated circuit (IC) according to one embodiment. RF transceiver <NUM> may represent RF transceiver <NUM> of <FIG>. Referring to <FIG>, frequency synthesizer <NUM> may represent frequency synthesizer <NUM> as described above. In one embodiment, RF transceiver <NUM> can include frequency synthesizer <NUM>, transmitter <NUM>, and receiver <NUM>. Frequency synthesizer <NUM> is communicatively coupled to transmitter <NUM> and receiver <NUM> to provide LO signals. Transmitter <NUM> can transmit RF signals for a number of frequency bands. Receiver <NUM> can receive RF signals for a number of frequency bands.

Receiver <NUM> includes a low noise amplifier (LNA) <NUM>, mixer(s) <NUM>, and filter(s) <NUM>. LNA <NUM> is to receive RF signals from a remote transmitter via antenna <NUM> and to amplify the received RF signals. The amplified RF signals are then demodulated by mixer(s) <NUM> (also referred to as a down-convert mixer) based on an LO signal provided by IQ generator <NUM>. IQ generator <NUM> may represent an IQ generator of IQ generator/synthesizer <NUM> as described above. In one embodiment, IQ generator <NUM> is integrated into broadband receiver <NUM> as a single integrated circuit. The demodulated signals are then processed by filter(s) <NUM>, which may be a low-pass filter. In one embodiment, transmitter <NUM> and receiver <NUM> share antenna <NUM> via a transmitting and receiving (T/R) switch <NUM>. T/R switch <NUM> is configured to switch between transmitter <NUM> and receiver <NUM> to couple antenna <NUM> to either transmitter <NUM> or receiver <NUM> at a particular point in time. Although there is one pair of transmitter and receiver shown, multiple pairs of transmitters and receivers and/or a standalone receiver can be implemented.

<FIG> is a block diagram illustrating an example of a wideband LNA <NUM>, wideband IQ mixers <NUM>, and filter <NUM>. Filter <NUM> can be a two-stage resistors capacitors (e.g., RC-CR) poly-phase filter. Filter <NUM> can include one or more variable gain intermediate frequency (IF) amplifiers for additional power gain. Note wideband IQ mixers <NUM> can be co-designed with wideband IQ generation circuit <NUM> as a single unit. Wideband IQ mixers <NUM> can also include a matching network <NUM> for impedance matching between LNA <NUM> and mixers <NUM>.

<FIG> is a block diagram illustrating a mm-wave wideband IQ generation circuit according to one embodiment. Referring to <FIG>, wideband IQ generation circuit <NUM> can generate IQ signals (e.g., LO_Ip, LO_Qp, LO_In, and LO_Qn) based on a differential LO signal (e.g., LO_Ip and LO_In) over a wide range of frequencies. The IQ generation circuit <NUM> introduces <NUM> degrees phase shift to the LO signals to generate signals in the four phase quadrants. IQ signals can then be used by an IQ mixer to modulate RF signals having IQ data to a lower frequency signal (e.g., IF signal).

<FIG> is a block diagram illustrating broadband IQ mixers according to one embodiment. A mixer is a three port device that can perform a frequency conversion or modulation of a signal. For a receiver, a mixer down converts (or demodulates) an RF signal using an LO signal to generate an IF signal. Referring to <FIG>, mixers <NUM> includes two (or double) balanced Gilbert mixers <NUM>-<NUM>. Double balanced mixers <NUM>-<NUM> down convert (or demodulate) a differential RF signal using differential LO signals to generate differential IF signals. For example, mixer <NUM> receives RF_inp, RF_inn, and differential in-phase signals (e.g., LO_Ip and LO_In) generated by a mm-wave wideband IQ generation circuit, such as IQ generator <NUM> of <FIG>, to generate IF_Ip and IF_In. Similarly, mixer <NUM> receives RF_inp, RF_inn, and differential quadrature signals (e.g., LO_Qp and LO_Qn) generated by a mm-wave wideband IQ generation circuit, such as IQ generator <NUM> of <FIG>, to generate IF_Qp and IF_Qn. In some embodiments, each of mixers <NUM>-<NUM> can include one or more differential amplifier stages.

Referring to <FIG>, for a two stage differential amplifier, the amplifier can include a common source differential amplifier as the first stage and a gate-coupled differential amplifier as the second stage. The common source differential amplifier stage of mixers <NUM>-<NUM> each can receive differential signals RF_inp and RF_inn. The gate-coupled differential amplifier stage of mixer <NUM> receives differential signals LO_In and LO_Ip. The gate-coupled differential amplifier stage of mixer <NUM> receives differential signals LO_Qn and LO_Qp. The RF signal is then down converted by the LO signal to generate an IF signal. The second stage can include a low-pass filter which can be first order low-pass filters to minimize high frequency noise injections into mixers <NUM>-<NUM>. In one embodiment, the low-pass filter includes a passive low pass filter having a load resistor in parallel with a capacitor (e.g., capacitor <NUM>). In one embodiment, the first stage different amplifier is coupled to the second stage differential amplifier via differential inductors (e.g., differential inductors <NUM>). In one embodiment, mixers <NUM>-<NUM> is co-designed with a mm-wave IQ generation circuit such as mm-wave IQ generation circuit <NUM> of <FIG> on a single monolithic integrated circuit.

<FIG> illustrates a simulation graph for conversion gain versus local oscillator (LO) frequency between <NUM> to <NUM> for a co-designed mm-wave IQ generation circuit of <FIG> and broadband IQ mixer of <FIG> according to one embodiment. Referring to <FIG>, With a moderate differential power such as a LO signal with a differential power of about -<NUM> dBm at the input of the IQ generation circuit, IQ mixers <NUM> can yield a downconversion gain of approximately > 7dB and an amplitude mismatch of approximately < <NUM>. 7dB over a LO frequency range of <NUM> to <NUM>.

<FIG> illustrates a simulation graph for conversion gain versus intermediate frequency (IF) between <NUM> to <NUM> for a co-designed mm-wave IQ generation circuit of <FIG> and broadband IQ mixer of <FIG> according to one embodiment. Referring to <FIG>, output load resistors of the mixer <NUM>/<NUM> can be co-designed in parallel with input capacitors <NUM>, which may be parasitic capacitances seen at a next IF amplifier stage, e.g., IF variable gain amplifier stage <NUM> of <FIG>, to form a first-order low pass filter. Referring to <FIG>, based on the co-designed mm-wave IQ generation circuit and IQ mixers, a conversion gain degradation can be reduced to about <NUM> dB from a peak gain of about <NUM> dB for an IF frequency designed at about <NUM>.

Referring to <FIG>, differential inductor pair <NUM> is used to pick up a current gain between the two differential amplifier stages. Four inductors are included for good performance, e.g., two differential inductor pairs are used for each of the double IQ mixers. Four inductors, however, include a large foot. <FIG> illustrates a three dimensional model of a differential inductor pair according to one embodiment. Differential inductor pair <NUM> may be differential inductor pair <NUM> of <FIG>. In one embodiment, a differential inductor pair can be reduced to a single inductor footprint, such as differential inductor pair <NUM> of <FIG>. Referring to <FIG>, differential inductor pair <NUM> includes two spiral inductors folded together into a footprint of a single inductor due to the fact that there is a virtual ground between the inductor pairs, and thus, a ground plane (e.g., a ground plane surrounding the inductors) can be reused for the pair of inductors to reduce the inductor pair footprint. In one embodiment, differential inductor pair <NUM> can each have about 200pH of inductance. In one embodiment, the inductor pair has a footprint of about <NUM> by <NUM>.

<FIG> illustrates a layout model of a double balanced mixer each with a differential inductor pair of <FIG> according to one embodiment. Referring to <FIG>, double balanced mixer <NUM> can be IQ mixers <NUM>-<NUM> of <FIG>. As shown by <FIG>, two inductor pairs (e.g., <NUM> inductors in total) are each coupled between a first stage amplifier and a second stage amplifier. The inductor pair applies an inductance between the two stages to enhance a current gain over a mm-wave frequency range. The inductors of the differential inductor pair share a virtual ground and have a single inductor footprint. In one embodiment, the mixer footprint is approximately <NUM> by <NUM>. <FIG> is a block diagram illustrating a poly-phase filter (PPF) circuit according to one embodiment. PPF <NUM> can filter out higher frequency noise and can recombine the four in-phase and quadrature signals back into a differential pair of IF signals, e.g., IF_Ip and IF_In. In one embodiment, PPF <NUM> includes one or more amplifier stages to further amplify an IF signal. Referring to <FIG>, in one embodiment, PPF <NUM> includes three stages. A first stage includes differential amplifiers <NUM> to increase the power of the IQ IF signals, e.g., IF_Ip, IF_In, IF_Qp, and IF_Qn. A second stage includes a resistive-capacitive capacitive-resistive (RC_CR) PPF <NUM>. PPF <NUM> can filter out undesirable signal noise, e.g., high frequency noise outside the range of the IF frequencies, and can combine the four in-phase and quadrature signals, e.g., IF_Ip, IF_In, IF_Qp, and IF_Qn, into a differential pair of IF signals, e.g., IF_Ip and IF_In. Finally, a third stage includes an amplifier <NUM> to further amplify the differential IF signals IF_Ip and IF_In to generate IF_out+ and IF_out-. Amplifiers <NUM> and amplifiers <NUM> can be variable gain amplifiers to allow for gain adjustments for the PPF circuit <NUM>.

<FIG> is a simulation graph illustrating image rejection ratio vs RF frequency from <NUM> to <NUM> under an IF frequency of approximately <NUM> for the broadband receiver circuit (e.g., receiver <NUM>) of <FIG>, according to one embodiment. The simulation setup includes a differential LO with a driving power ranging from -<NUM> to +3dBm as the input. Under the IF frequency of approximately <NUM>, the wideband imaging rejection ratio (IRR) is approximately > 23dB for a frequency range of about <NUM> to <NUM>. Broadband receiver <NUM> occupies approximately <NUM> by <NUM> according to one embodiment.

<FIG> is a block diagram illustrating an RF transceiver integrated circuit according to one embodiment. RF transceiver <NUM> can be transceiver <NUM> of <FIG>. In one embodiment, RF transceiver <NUM> includes co-design matching network <NUM> which is coupled in between T/R switch <NUM> and LNA <NUM> of receiver <NUM>. Matching network <NUM> co-designed with T/R switch <NUM> and LNA <NUM> can improve a performance of receiver <NUM>.

<FIG> are block diagrams illustrating examples of transceiver T/R switches according to some embodiments. Referring to <FIG>, LNA <NUM> is directly coupled to T/R switches <NUM>. Here, an input impedance of LNA <NUM> is designed to match an output impedance of switches <NUM>. However, the loading capacitances of off-switches for switches <NUM> (e.g., Coff) and PA <NUM> can directly load on to the input of the LNA thus degrading a performance of receiver <NUM>. <FIG> illustrates LNA <NUM> coupled to T/R switches <NUM> via co-design matching network <NUM>. Network <NUM> can include an inductor (e.g., Lmatching) in series with an inductive transmission line (Tline) coupled in between LNA <NUM> and T/R switches <NUM>. The inductor(s) can resonate with loading and/or parasitic capacitances seen by the matching network to resonate at one or more resonant frequencies.

<FIG> is a block diagram illustrating an example wideband LNA circuit according to one embodiment. LNA is an amplifier that can amplify a low power RF signal without significantly degrading its signal to noise ratio. Referring to <FIG>, LNA <NUM> includes a first (amplifier) stage <NUM> and a second (amplifier) stage <NUM>. The first stage <NUM> can be implemented in a source inductive degeneration topology to achieve wideband input matching with high linearity, e.g., a source terminal of transistor M1 is coupled to inductor L2. An LNA based on the inductively degenerated common-source stage can achieve a low noise figure.

In one embodiment, inductor L1 is coupled in between a gate terminal of transistor M1 and an input port (IN). Referring to <FIG>, inductors L1, L2 together with a parasitic gate capacitance (e.g., Cgs and/or Cgd) and/or a source capacitance of transistor M1 can be configured to resonate at dual-resonance for a broadband input impedance matching. The inductive degeneration topology can include transistors M1 and M2 and a current gain peaking inductor (e.g., inductor L3) coupled in between transistors M1 and M2. Inductor L3 is selected to form a C-L-C like transmission line with parasitic capacitances of transistors M1 (e.g., Cds) and M2 (e.g., Cgs) to deliver a high frequency amplified signal from transistor M1 to transistor M2. Without inductor L3, parasitic capacitances Cds of M1 and Cgs of M2 would leak a RF current signal along M1-M2 which lowers a gain and degrades a noise figure of the overall LNA.

In one embodiment, first stage <NUM> can include a variable gain control to adjust a gain for the first stage to adjust an input linearity of LNA <NUM>. The variable gain control can include a pnp transistor (e.g., PMOS) coupled to a drain terminal of transistor M2. The pnp transistor receives a LNA_vctrl signal at the gate terminal for adjusting the gain control of the first stage. In one embodiment, inductor L4 is coupled to a drain terminal of transistor M2 (e.g., at a drain and a source terminal of the pnp transistor) to resonate at a first resonant frequency or first resonance.

For the second stage <NUM>, signal <NUM> is amplified by M3 and M4 transistors. Similar to L3 with transistors M1 and M2, current gain peaking inductor L6 is inserted between M3 and M4 transistors to form a C-L-C like transmission line with parasitic capacitances of transistors M3 (e.g., Cds) and M4 (e.g., Cgs) seen by inductor L6 to deliver a high frequency amplifier signal from M3 to M4. Similar to inductor L3, without inductor L6, parasitic capacitances Cds of M3 and Cgs of M4 would leak a RF current signal along M3-M4 which lowers a gain and degrades a noise figure of the overall LNA.

In one embodiment, transformer-based balun <NUM> is coupled to a drain terminal of M4 so high frequency signals at the drain terminal of M4 can be transformed from single-ended into differential (e.g., balanced) components (e.g., at ports Outp and Outn) by transformer-based balun <NUM>. A balun is a type of transformer used to convert an unbalanced signal to a balanced signal or vice versa. A balanced signal includes two signals carrying signals equal in magnitude but opposite in phase. An unbalanced signal includes a single signal working against a ground signal. A balanced signal allows for a balanced configuration for the next stages (e.g., mixer <NUM>) to guard against RF-LO, LO-IF, and RF-IF signal leakages. Here, the passive loss of transformer-based balun <NUM> is minimized because transformer-based balun <NUM> is coupled next to the output ports of LNA <NUM> (e.g., at second stage <NUM>, right before output ports Outp and Outn). Furthermore, a primary winding inductance of a transformer of the transformer-based balun can resonate with Cgs of transistor M4 at a second resonant frequency. The second resonant frequency of the second stage, along with the first resonant frequency of the first stage, can achieve a wideband frequency extension for a corresponding conversion gain bandwidth.

In one embodiment, a gate terminal of transistor M3 is coupled to a passive network circuit. The passive network circuit can include inductor L5 in parallel with resistor R1. In one embodiment, a C_conversion capacitor is coupled in between the first stage (e.g., drain terminal of transistor M2) and the second stage (e.g., gate terminal of transistor M3). The C_conversion can impedance transform a gate capacitance (e.g., Cgs) of M3 and/or the impedance of the passive network circuit (e.g., L5 in parallel with R1) to an optimal load for the first stage. Note that although the LNA is shown with only two stages, additional stages can be implemented, e.g., a three-stage LNA, etc..

<FIG> is a chart illustrating S-parameter (S11) for an example wideband LNA circuit according to one embodiment. Chart <NUM> can be a S11 plot for LNA <NUM> of <FIG>. As shown by the S11 plot, LNA <NUM> has dual resonance at <NUM> and <NUM>, which can be achieved by tuning inductors L1 and L2 of LNA <NUM> of <FIG>. S11 is approximate < -16dB at the two resonant frequencies and approximate < -<NUM> dB for a frequency range of approximately <NUM> to <NUM>.

<FIG> is a chart illustrating conversion gains (or S-parameters S21 and S31) for an example wideband LNA circuit according to an embodiment. Referring to <FIG>, chart <NUM> can be a conversion gain plot for LNA <NUM> of <FIG>. As show, the single-end to single-end gains are approximately <NUM> dB (e.g., S21 and S31 for input port <NUM> to output ports outp <NUM> and outn <NUM>). The differential to single-ended gain is thus approximately <NUM> dB from the single-end input port to the differential output ports. Referring to <FIG>, in one embodiment, the S11 (> -10dB) bandwidth and the <NUM>-dB S21 gain bandwidth covers a frequency range of approximately <NUM> to approximately <NUM>.

<FIG> is a block diagram illustrating an example wideband LNA circuit without a co-design matching network according to one embodiment. <FIG> is a block diagram illustrating S-parameter (S11) for input matching for a wideband LNA circuit without a co-design matching network according to one embodiment (e.g., <FIG>). In this case, once LNA <NUM> is loaded with T/R switches <NUM> and off-state power amplifier (PA) <NUM> as shown in <FIG>, the loading and/or parasitic capacitances of off-switches of T/R switches <NUM> and the off-state PA <NUM> degrade the overall receiver performance as shown by <FIG>. For T/R switches <NUM>, Ron models the on-resistance of switch transistors and Coff models the off-capacitance of the switch transistors. The overall receiver input matching S11 is > -<NUM> dB over a frequency range of approximately <NUM> - <NUM>, e.g., an entire band of interest for <NUM> MIMO communication. In other words, most of the received signals are reflected rather than received by the receiver leading to suboptimal performances (e.g., receiver bandwidth, conversion gain, sensitivity, and noise figure, etc.) at the mm-Wave frequencies.

<FIG> is a block diagram illustrating an example wideband LNA circuit with a co-design matching network according to one embodiment. <FIG> is a block diagram illustrating S-parameter (S11) for input matching for a wideband LNA circuit with a co-design matching network according to one embodiment (e.g., <FIG>). Referring to <FIG>, matching network <NUM> includes a transmission line (Tline) that bridges T/R switches <NUM> to LNA <NUM>.

In one embodiment, matching network <NUM> includes Lmatching to resonate with capacitances (e.g., Coff) of T/R switches <NUM> and capacitances for off-state PA <NUM>. Referring to <FIG>, capacitance C1 (approximately <NUM> pF) is typically coupled to an input of an LNA to block a DC signal received by the receiver, however, C1 can cause signal loss due to a capacitive voltage division between C1 and parasitic capacitors see at a gate node of transistor M1. Referring to <FIG>, in one embodiment, matching network <NUM> includes capacitance C2 coupled to Tline. Here, in contrast, capacitance C2 (approximately <NUM> fF) can (<NUM>) create a high-order resonance with Tline and series gate inductor L1 and (<NUM>) block a DC signal for the receiver front-end without a signal loss due to a capacitive voltage division.

In one embodiment, matching network <NUM> includes multiple resonating LC pairs, including (<NUM>) a first LC pair from Coff of T/R switch and load capacitor of the PA resonanting with Lmatching, (<NUM>) a second LC pair from C2 with Tline and L1, and (<NUM>) a third LC pair from gate-to-source parasitic capacitor of M1 with inductor L2. Having multiple resonating LC pairs, matching network <NUM> is similar to a high-order chebyshev filter that can achieve a broadband input matching at mm-Wave. For example, referring to <FIG>, in one embodiment, the input matching (S11) looking into the frontend switches of <FIG> can be approximately < -<NUM> dB for a frequency range of approximately <NUM> to <NUM>. Here, S11 of <FIG> includes multiple resonant frequencies in comparison with <FIG> extending a useful bandwidth of the receiver with the T/R switches.

<FIG> is a chart illustrating conversion gains for the first stage LC resonance and the second stage LC resonance for a wideband LNA circuit according to an embodiment. <FIG> is a chart illustrating a conversion gain for the combined first stage LC resonance and the second stage LC resonance for a wideband LNA circuit according to an embodiment. For example, <FIG> can be conversion gain charts for the wideband LNA circuit <NUM> of <FIG>.

Referring to <FIG>, chart <NUM> shows a gain bandwidth extension by the two-stage resonant points which include a first resonant frequency f1 and a second resonant frequency f2. Here, f1 can correspond to a frequency of the first stage LC resonance (e.g., <NUM>) and f2 can correspond to frequency of the second stage LC resonance (e.g., <NUM>). Frequency f1 can be coarsely adjusted by selecting inductor L4 and frequency f2 can be coarsely adjusted by selecting a size of the transformer of the transformer-based balun, e.g., adjusting a primary winding inductance of the transformer which is coupled to transistor M4. Referring to <FIG>, chart <NUM> shows the overall conversion gain bandwidth for the LNA for the two-stage resonant frequencies f1 and f2 of <FIG>. Referring to <FIG>, the conversion gain bandwidth covers a frequency range of approximately f1 to f2. Here, by shifting and separating the two resonant frequency f1 and <NUM>, the LNA can be reconfigured for a wideband operation to cover a wider bandwidth.

<FIG> is a block diagram illustrating an example EM model for a wideband LNA circuit according to one embodiment. <FIG> is a block diagram illustrating an example EM layout for a wideband LNA circuit according to one embodiment. Referring to <FIG>, the overall LNA model/layout including bypass capacitors can have an approximately size of <NUM> by <NUM>.

In one embodiment, capacitor banks can be inserted near resonance sources, e.g., near resonant inductors, to improve an operating frequency range for the LNA. <FIG> is a block diagram illustrating an example wideband LNA circuit according to one embodiment. Referring to <FIG>, LNA <NUM> can be LNA <NUM> of <FIG>. In accordance with the invention LNA <NUM> further includes a first capacitor bank coupled in parallel with inductor L1. In accordance with the invention LNA <NUM> includes a second capacitor bank coupled in parallel with inductor L4. In accordance with the invention LNA <NUM> includes a third capacitor bank coupled in parallel with C_conversion. In accordance with the invention LNA <NUM> includes a fourth capacitor bank coupled to two ends of a primary winding of the transformer of the transformer-based balun. In accordance with the invention the first, second, third, and fourth capacitor banks are programmable capacitors or digitally tunable capacitors. By tuning the capacitors, the input matching dual-resonance and/or the first and the second resonance frequencies can be shifted to reconfigure an operating frequency range for LNA <NUM>.

<FIG> is a chart illustrating conversion gains for a first amplifier stage, a second amplifier stage, and an impedance transformation stage of a wideband LNA circuit according to one embodiment. Chart <NUM> can be a conversion gain chart for LNA <NUM> of <FIG>. Referring to <FIG>, in one embodiment, tuning the first, second, third, and fourth capacitor banks can reconfigure the operating frequency of LNA <NUM> to a frequency range of approximately <NUM> to <NUM>, which can be a <NUM>% to a <NUM>% improvement over the frequency band of operation of LNA <NUM> of <FIG> as previously shown in <FIG>. Thus, the additional capacitor banks can reconfigure a frequency response of the LNA to operating the LNA at different frequency bands or ranges.

Claim 1:
A low noise amplifier "LNA" circuit (<NUM>) comprising:
a first amplifier stage (<NUM>), comprising:
a first transistor;
a second transistor having a source coupled to a drain of the first transistor;
a first inductor coupled in between an input port and a gate of the first transistor; and
a second inductor coupled between a source of the first transistor and ground, wherein the first inductor and the second inductor resonates with a gate capacitance of the first transistor respectively for a dual-resonance input matching;
a fourth inductor coupled in parallel with a second capacitor bank between a drain of the second transistor and a supply voltage (Vdd) and configured to resonate with a drain capacitance of the second transistor and a capacitance of the second capacitor bank at a first resonant frequency (f1);
a second amplifier stage (<NUM>), comprising:
a third transistor;
a fourth transistor having a source coupled to a drain of the third transistor and a drain coupled to an output port;
a passive network coupled to a gate of the third transistor; and
a transformer-based balun (<NUM>) coupled between the output port and the fourth transistor, wherein a primary winding of a transformer of the transformer-based balun (<NUM>) is coupled between a drain of the fourth transistor and the supply voltage (Vdd) and configured to resonate with a drain capacitance of the fourth transistor at a second resonant frequency (f2) and wherein an overall conversion gain bandwidth of the LNA circuit (<NUM>) covers a frequency range of approximately the first resonant frequency (f1) to the second resonant frequency (f2); and
a capacitor coupled in between a drain of the second transistor and a gate of the third transistor, wherein the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage;
a first capacitor bank coupled in parallel with the first inductor;
a third capacitor bank coupled in parallel with the capacitor; and
a fourth capacitor bank coupled in parallel with the primary winding of the transformer of the transformer-based balun (<NUM>), wherein the first, the second,
the third, and the fourth capacitor banks are programmable capacitors or digitally tunable capacitors.