Patent Description:
One example model for quantum computation is the quantum circuit model. In the quantum circuit model, a computation is a sequence of quantum gates - reversible transformations on a quantum mechanical analog of an n-bit register. This analogous structure is referred to as an n-qubit register. Example quantum gates include single qubit gates such as the Hadamard gate, Pauli X gate, Pauli Y gate, and Pauli Z gate, and multi qubit gates such as the SWAP gate or controlled X, Y or Z gates.

"<NPL>) discloses a "temporary logical AND" construction which uses four T gates to store the logical-AND of two qubits into an ancilla and zero T gates to later erase the ancilla.

This specification describes technologies for performing phase operations in quantum circuits.

Details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below.

Phase operations Zθ are single-qubit gates that leave the basis state |<NUM>〉 unchanged and map the basis state |<NUM>〉 to eiπθ|<NUM>〉, where θ represents a phase shift: <MAT>.

The probability of measuring a |<NUM>〉 or |<NUM>〉 after application of a phase operation does not change, but the phase of the quantum state is shifted.

Phase operations are common operations in quantum circuits. Phasing by <NUM> degrees (Z gates) or <NUM> degrees (S gates) is relatively straightforward to implement and has low cost. Phasing by <NUM> degrees (T gates) has increased cost. Furthermore, phasing by angles that are not multiples of <NUM> degrees is even more costly, since such phase operations typically require approximating the target operation with T gates, and the number of T gates required to obtain a good approximation of a target phase angle increases as the target precision becomes more exact. For example, in some cases performing a non-<NUM>-degree phasing operation may require up to <NUM> T gates.

This specification describes various techniques for reducing the number of T gates required for performing phase operations Zθ. The techniques include using addition operations to merge phasing operations, e.g., performing two <MAT> gates using five T gates, duplicating states when performing phase operations, and performing individual <MAT> or more generally (T)<NUM>-n gates with reduced T count.

<FIG> depicts an exemplary system <NUM> for performing phase operations. The system <NUM> is an example of a system implemented as quantum and/or classical computer programs on one or more quantum computing devices and/or classical computers in one or more locations, in which the systems, components, and techniques described below can be implemented.

The system <NUM> includes a quantum computing device <NUM> in data communication with one or more classical processors <NUM>. For convenience, the quantum computing device <NUM> and classical processors <NUM> are illustrated as separate entities, however in some implementations the one or more classical processors may be included in quantum computing device <NUM>.

The quantum computing device <NUM> includes components for performing quantum computation. For example, the quantum computing device <NUM> includes at least quantum circuitry <NUM> and control devices <NUM>.

The quantum circuitry <NUM> includes components for performing quantum computations, e.g., components for implementing the various quantum circuits and operations described below with reference to <FIG>. For example, the quantum circuitry may include a quantum system that includes one or more multi-level quantum subsystems, e.g., a register of qubits <NUM>. The type of multi-level quantum subsystems that the system <NUM> utilizes may vary. For example, in some implementations the multi-level quantum subsystems may be superconducting qubits, e.g., Gmon or Xmon qubits. In some cases it may be convenient to include one or more resonators attached to one or more superconducting qubits. In other cases ion traps, photonic devices or superconducting cavities (with which states may be prepared without requiring qubits) may be used. Further examples of realizations of multi-level quantum subsystems include fluxmon qubits, silicon quantum dots or phosphorus impurity qubits.

Quantum circuits comprising different quantum logic operations, e.g., single qubit gates, two qubit gates, and three qubit gates such as the NOT gates, CNOT gates, multi target CNOT gates, and logical AND operations described below with reference to <FIG>, may be constructed using the quantum circuitry <NUM>. Constructed quantum circuits can be operated/implemented using the control devices <NUM>. The type of control devices <NUM> included in the quantum system depend on the type of qubits included in the quantum computing device. For example, in some cases the control devices <NUM> may include devices that control the frequencies of qubits included in the quantum circuitry <NUM>, an excitation pulse generator and control lines that couple the qubits to the excitation pulse generator. The control devices may then cause the frequency of each qubit to be adjusted towards or away from a quantum gate frequency of an excitation pulse on a corresponding control driveline. The control devices <NUM> may further include measurement devices, e.g., readout resonators. Measurement results obtained via measurement devices may be provided to the classical processors <NUM> for processing and analyzing.

The quantum computing device <NUM> may include one or more quantum state factories, e.g., T factory <NUM>, for producing quantum states that may be consumed by the quantum circuitry when performing quantum computations. For example, as described below with reference to <FIG> and <FIG>, the T factory <NUM> may produce T states or <MAT> states and provide the produced states to the quantum circuitry <NUM>.

<FIG> is a flowchart of an example process <NUM> for performing a target phase operation Zθ on both a first qubit prepared in a first input state and a second qubit prepared in a second input state using a third qubit prepared in a phased plus state Zθ|+〉. The phased plus state specialized to the target angle of the target phase operation can be created using any of multiple existing techniques. For convenience, the process <NUM> will be described as being performed by a system of one or more classical or quantum computing devices located in one or more locations. For example, a quantum computation system, e.g., the system <NUM> of <FIG>, appropriately programmed in accordance with this specification, can perform the process <NUM>.

The system performs a first NOT operation on the third qubit (step <NUM>).

The system performs a controlled adder operation on the first, second and third qubit, which includes encoding the result of the controlled adder operation in a fourth qubit (step <NUM>). As shown in the example quantum circuit <NUM> described below with reference to <FIG>, computing the controlled adder operation on the first, second and third qubit includes performing a multi target CNOT operation on the first, second and third qubit, where the first qubit acts as a control for the multi target CNOT operation, computing a logical AND operation between the second and third qubit and encoding the result of the logical AND computation in the fourth qubit, and performing a CNOT operation between the first qubit and the fourth qubit, where the first qubit acts as a control for the CNOT operation. Example methods for computing and uncomputing logical AND operations are described in detail in "<CIT>.

The system performs a square of the target phase operation (Zθ)<NUM> = Z<NUM>θ on the fourth qubit (step <NUM>). This inner phasing operation that phases by twice as much as the target angle may be implemented in several possible ways. Example implementations include applying existing techniques such as repeat-until-success techniques, using a T gate (if the doubled angle is a multiple of <NUM> degrees), or recursively, by the same process used to perform the phasing operation by the desired angle (up to some maximum depth).

The system un-computes the controlled adder operation on the first, second and third qubit (step <NUM>). Un-computing the controlled adder operation includes performing a CNOT operation on the first qubit and the fourth qubit, where the first qubit acts as a control for the CNOT operation, un-computing the logical AND operation described above with reference to step <NUM>, and performing a multi target CNOT operation on the first, second and third qubit, where the first qubit acts as a control for the multi-target CNOT operation.

The system performs a CNOT operation between the first qubit and the third qubit, where the first qubit acts as a control for the CNOT operation (step <NUM>).

The system performs a CNOT operation between the second qubit and the third qubit, where the second qubit acts as a control for the CNOT operation (step <NUM>).

The system performs a second NOT operation on the third qubit (step <NUM>).

In some implementations, steps <NUM>-<NUM> may be replaced by the following steps: performing a CNOT operation on the first qubit and the fourth qubit, where the first qubit acts as a control for the CNOT operation, un-computing the logical AND operation between the second and third qubit, performing a CNOT operation on the second qubit and the third qubit, where the second qubit acts as a control for the CNOT operation, and performing a multi target CNOT operation on the first, second and third qubit, where the first qubit acts as a control for the multi target CNOT operation, as shown in the example quantum circuit <NUM> described below with reference to <FIG>.

Once the second NOT operation has been performed on the third qubit, the target phase operation has been applied to the first input state and to the second input state. The third qubit returns to its initial state - the phased plus state. One or more of these output states can then be provided for use in subsequent computations, as described in more detail below.

In some implementations a quantum circuit may include multiple applications of a phase operation to different qubits, e.g., three or more applications of a same phase operation to different qubits. In these implementations Hamming weight phasing may be applied to merge the identical phase operations into a smaller number of different phase operations.

For example, consider a quantum circuit where a same phasing operation Zθ is simultaneously applied to three different qubits. The action on the logical states of the three qubits is a different phase, depending only on the Hamming weight of that logical state. That is, the all-zero state <NUM> picks up the phase -<NUM>θ/<NUM>, the three states of Hamming weight one <NUM>, <NUM>, and <NUM> each pick up a phase -θ/<NUM>, the three states of Hamming weight two <NUM>, <NUM>, and <NUM> are all phased by θ/<NUM>, and the all-one state <NUM> picks up a phase <NUM>θ/<NUM>.

Rather than applying three rotations by the same angle θ, the Hamming weight of the input states can be computed, and <NUM> distinct rotations can be applied to the Hamming weight: θ to the <NUM> bit, and <NUM>θ to the <NUM> bit. In this case, the phase - is applied to the all-zero state <NUM> (Hamming weight <NUM>), <MAT> is applied to <NUM>, <NUM>, and <NUM> (Hamming weight <NUM> = <NUM>b in binary), <MAT> is applied to <NUM>, <NUM>, and <NUM> (Hamming weight <NUM> = <NUM>b), and <MAT> is applied to the all-one state <NUM> (Hamming weight <NUM> = <NUM>b). The phases on each logical state are identical for the two procedures. However, because arbitrary rotations must be synthesized using costly T gates, reducing the number of arbitrary rotation gates in the circuit reduces its fault-tolerant cost.

This concept can be extended to the case of n repeated equiangular rotations appearing in parallel in a circuit: rather than applying the n original arbitrary rotations, the Hamming weight of the relevant qubits can be computed, and instead <MAT> arbitrary rotations θ, <NUM>θ, <NUM>θ,. can be applied to the Hamming weight. This technique is called Hamming weight phasing.

Hamming weight phasing can appear to give an improvement for free. However, there are two primary sources of cost - an additional number of T gates and an ancilla qubit requirement, both arising from the use of adder circuits (circuits that include the above described logical AND computations and uncomputations) when computing the Hamming weight. However, by computing the Hamming weight of size <MAT> subsets of qubits at a time and summing these subset Hamming weights, rather than directly computing the full Hamming weight, the number of required ancilla qubits can be reduced from n - <NUM> to <MAT> or even to 2log<NUM> n.

For example, the system can group the n phase operations (or equivalently, n qubits on which the n phase operations are to be performed) into multiple groups of size <MAT> and prepare a full-total qubit register of size <MAT>. For each group, the system computes a Hamming weight of the qubits in the group using <MAT> ancilla qubits, and adds a computed group-total into the prepared full-total qubit register. The system then uncomputes the Hamming weight of the qubits in the group. The same <MAT> ancilla qubits can be used to compute the Hamming weight of each group. After the Hamming weight of all <MAT> groups has been computed and added to the total, phase operations can be applied to the total Hamming weight in the full-total register as described above. Then, for each group, the system re-computes the Hamming weight of the qubits in the group and subtracts a computed group total out of the full total register to uncompute the full total Hamming weight register. This reduces the number of ancilla qubits required from n - <NUM> to <MAT>. The number of ancilla qubits is reduced at the cost of requiring more T gates, however the number of T gates required to reduce the original n phase operations to <MAT> phase operations is approximately upper bounded by
<MAT>, which is only slightly more than existing applications of Hamming weight phasing methods that require 4n - <NUM> T gates but significantly more (i.e., n) ancilla qubits.

Further reductions can also be achieved by dividing the n phase operations into n/ log<NUM> n groups each of size log<NUM> n. For each of these groups the system can compute the Hamming weight of the qubits in the group, add this weight into an accumulator register full total qubit register), then uncompute the Hamming weight of the qubits in the group. The accumulator register then contains the Hamming weight of the entire set of qubits. Phase operations can be applied to the total Hamming weight in the accumulator register as described above. Then, for each group, the system performs a reverse of the computation process, e.g., the system re-computes the Hamming weight of the qubits in the group and subtracts a computed group total out of the accumulator register to uncompute the full total Hamming weight register. This doubles the number of addition operations that must be performed, but reduces the space requirements to 2log<NUM> n.

<FIG> show various applications of example process <NUM> and Hamming weight phasing. For example, <FIG> is a circuit diagram <NUM> of an example quantum circuit for performing a target phase operation Zθ on a first and second qubit using a third qubit prepared in a phased plus state Zθ|+〉.

In the example quantum circuit shown in circuit diagram <NUM>, the first qubit, second qubit and third qubit are represented by horizontal lines 302a-c. In the example quantum circuit <NUM>, qubits 302a and 302b represent the first and second qubit on which the target phase operation Zθ is to be performed. Qubits 302a and 302b are provided to the example quantum circuit <NUM> in input states |ψ<NUM>〉 and |ψ<NUM>〉, respectively. The input states |ψ<NUM>〉 and |ψ<NUM>〉 can be initial states of either of the qubits 302a or 302b, i.e., qubits 302a or 302b may have been prepared in arbitrary initial states, or can be states representing an output of a previous computation. Qubit 302c represents the third qubit that is prepared in a phased plus state Zθ|+〉. The qubit 302c can be prepared in the phased plus state using any one of existing techniques.

The example quantum circuit <NUM> includes a sequence of gates that are applied to the qubits 302a-302c. The sequence of gates includes a first NOT operation <NUM> that is applied to the third qubit 302c. A first collection of operations <NUM> are then applied to the qubits 302a-302c to compute a controlled adder operation on the qubits 302a-302c. The first collection of operations <NUM> includes a multi target CNOT gate 306a that is applied to the three qubits 302a-302c, where the first qubit acts as a control for the multi target CNOT gate. The first collection of operations <NUM> further includes a logical AND operation 306b that is performed between the second and third qubit. The result of the local AND operation is encoded in a fourth qubit 302d. The first collection of operations <NUM> further includes a CNOT gate 306c that is applied to the first qubit 302a and the fourth qubit 302d, where the first qubit 302a acts as a control for the CNOT gate.

The sequence of gates further includes a square of the target phase operation <NUM> that is applied to the fourth qubit 302d. A second collection of operations <NUM> is then applied to the qubits 302a-302d to uncompute the controlled adder operation performed by the first collection of operations <NUM>. The second collection of operations <NUM> includes a CNOT operation 310a that is applied to the first qubit 302a and to the fourth qubit 302d, where the first qubit 302a acts as a control for the CNOT operation 310a. The second collection of operations <NUM> further includes the uncomputation of a logical AND operation 310b between the second qubit 302b and the third qubit 302c.

The sequence of gates further includes a CNOT operation <NUM> that is applied to the second qubit 302b and the third qubit 302c, where the second qubit 302b acts as a control for the CNOT operation <NUM>. The sequence of gates further includes a multi target CNOT operation <NUM> that is applied to the first qubit 302a, second qubit 302b and third qubit 302c, where the first qubit 302a acts as a control for the multi target CNOT operation <NUM>. The sequence of gates includes a NOT operation <NUM> that is applied to the third qubit 302c. The NOT operation <NUM> returns the qubit to the original phased plus state Zθ|+〉.

After the example quantum circuit has been applied to the three qubits 302a-c (and fourth qubit 302d), the target phase operation Zθhas been applied to the first qubit 302a and second qubit 302b. That is, the example quantum circuit <NUM> operates on a resource state - a | +〉 state that has been phased by an angle equivalent to the target phase operation's angle - and two input states that are to be phased by the angle, phases the two inputs states in the target way, and returns the resource state.

<FIG> is a circuit diagram <NUM> of an unclaimed example quantum circuit for performing a target phase operation on a first and second qubit using a third qubit prepared in a phased plus state. The alterative quantum circuit shown in <FIG> produces output states that are the same as those produced by the quantum circuit shown in <FIG>, but does not require an ancilla (fourth) qubit. That is, the alternative quantum circuit includes a sequence of gates that are applied to the three qubits 302a-c. The sequence of gates includes a NOT operation applied to the third qubit, a multi target CNOT gate that is applied to all three qubits, where the third qubit acts as the control, a CNOT gate that is applied to the third qubit where the first and second qubits act as controls, a square phase operation applied to the third qubit, a CNOT operation that is applied to the third qubit where the first and second qubits act as controls, a multi target CNOT gate that is applied to all three qubits, where the third qubit acts as a control, a CNOT gate applied to the first and third qubit, where the first qubit acts as the control, a CNOT gate applied to the second and third qubit where the second qubit acts as the control, and a NOT operation performed on the third qubit.

The example process <NUM> may be used to perform a <MAT> gate on both a first qubit prepared in a first input state and a second qubit prepared in a second input state using a third qubit prepared in a <MAT> state. <FIG> is a circuit diagram <NUM> of an example quantum circuit for performing a <MAT> gate on a first qubit prepared in a first input state and a second qubit prepared in a second input state using a third qubit prepared in a <MAT> state. <FIG> shows how two <MAT> gates can be performed at a total cost of <NUM>T gates (four for the adder computations and uncomputations and one for the inner portion of the circuit, e.g., operation <NUM>), or <NUM> T gates per <MAT> operation. Since an initial cost of <NUM> T gates may be required to prepare a <MAT> state using existing methods (i.e., methods different to those described in this specification), the presently described techniques are an order of magnitude better than existing techniques in terms of cost.

The example process <NUM> described above with reference to <FIG> is used to perform an arbitrary target phase operation on both a first qubit prepared in a first input state and a second qubit prepared in a second input state using a third qubit prepared in a phased plus state, where the first input state and second input state can include any arbitrary initial states or states representing an output of a previous computation. The techniques described with reference to <FIG> can also be utilized to duplicate quantum states while applying target phase operations.

For example, in settings where a single phase operation Zθ is to be performed on the first qubit prepared in an arbitrary first input state, the second qubit may be prepared in a plus state (i.e., the second input state is a plus state) and the third qubit may be prepared in a phased plus state. Application of the example process <NUM> then maintains the state of the third qubit and duplicates the state of the third qubit by outputting the second qubit in a phased plus state. This duplicated state may then be provided for use in a subsequent quantum computation, e.g., as a resource state in a subsequent application of example process <NUM> for performing a same target phase operation on a fifth and sixth qubit, as a resource state in a subsequent application of example process <NUM> for duplicating a quantum state while applying a target phase operation, or as a resource state for performing another phase operation, as described below with reference to <FIG>.

<FIG> is a circuit diagram <NUM> of an example quantum circuit for duplicating a quantum state while performing a target phase operation Zθ. In the example quantum circuit shown in circuit diagram <NUM>, the first qubit, second qubit and third qubit are represented by horizontal lines 502a-c. Qubit 502a represents the first qubit on which the target phase operation Zθ is to be performed. Qubit 502c represents the third qubit whose state Zθ|+〉 is to be duplicated using qubit 502b.

As described above with reference to <FIG>, qubit 502a is provided to the example quantum circuit in an arbitrary input state |ψ〉. For example, the input state |ψ〉 can be an initially prepared state of the qubit 502a or can be a state representing an output of a previous computation. Qubit 502c is provided to the example quantum circuit in a phased plus state Zθ|+〉. Unlike the example circuit shown in <FIG>, qubit 502b is prepared in a plus state |+〉 <NUM>. That is, the second input state described above with reference to <FIG> and <FIG> is a plus state.

Operations performed by the example quantum circuit shown in <FIG> include a sequence of gates that is similar to that shown and described above with reference to <FIG> above. For convenience, a description of this sequence of gates is not repeated.

After the example quantum circuit shown in <FIG> has been applied to the three qubits 502a-c (and fourth qubit 502d), the target phase operation Zθ has been applied to the first qubit 502a. The target phase operation Zθ has also been applied to the second qubit 502b, which results in a phased plus state Zθ|+〉 <NUM>. The quantum state of the third qubit 502c has not been consumed and is also in a phased plus state Zθ|+〉. That is, a second copy <NUM> of the resource state Zθ|+〉 has been created and passed into the circuit instead of wasting the opportunity for applying a second phase operation and just applying a first phase operation.

Operating the hardware: An example method for performing individual <MAT> gates using <NUM> T gates.

The techniques described with reference to <FIG> can also be used to perform individual (Zθ)<NUM>/<NUM> phase operations, e.g., <MAT> gates. Performing a <MAT> gate using the above described techniques may include applying the circuit described above with reference to <FIG> with <MAT> to three qubits - a first qubit prepared in an arbitrary first input state |ψ〉, a second qubit prepared in a plus state and a third qubit prepared in a phased plus state - to put the first qubit in a <MAT> state, the second qubit in a phased plus state <MAT> and the third qubit in the same phased plus state <MAT>.

The third qubit in the <MAT> is a resource state and may be reused to perform subsequent gate teleportation operations, e.g., operations based on example process <NUM>. The second qubit in the <MAT> state may be used to generate a <MAT> through application of a subsequent circuit. Application of the subsequent circuit may include applying a CNOT operation between the second qubit that is now in a phased plus state and a fifth qubit prepared in an arbitrary input state, where the fifth qubit acts as a control for the CNOT operation. The second qubit may then be measured, and a squared phase operation (T operation/gate) may be performed on the fifth qubit if a generated measurement result from measuring the second qubit indicates that the second qubit is ON.

<FIG> is a circuit diagram <NUM> of an example quantum circuit for performing individual <MAT> gates. The example quantum circuit shown in <FIG> includes two sub-circuits <NUM> and <NUM>. Sub-circuit <NUM> is the same as the example quantum circuit shown in <FIG> with <MAT>, and for convenience is therefore not described again. Sub-circuit <NUM> operates on two qubits - a fifth qubit <NUM> prepared in an arbitrary input state |ψ〉 and the second qubit from sub-circuit <NUM> which is provided to the sub-circuit <NUM> in a phased plus state <MAT>.

The sub-circuit <NUM> includes a sequence of gates that may provide a phased input state <MAT> <NUM>. The sequence of gates includes a CNOT operation <NUM> between the fifth qubit <NUM> and the second qubit in the phased plus state, a measurement operation <NUM> that is applied to the second qubit and generates a respective measurement result, and a controlled phase operation <NUM> that applies a phase operation (a fix up operation) to the fifth qubit if the generated measurement result from operation <NUM> indicates that the second qubit is ON. Due to quantum superposition, there is a <NUM>% chance that the fixup operation will be performed. Therefore, the cost of performing the <MAT> operation when consuming the <MAT> state is <NUM> on average. By alternating between producing the extra state <MAT> and consuming the extra state <MAT>, any number of unpaired <MAT> operations can be performed with an average cost of (<NUM> + <NUM>)/<NUM> = <NUM> T gates.

It is noted that the costs for performing the <MAT> operation do not scale up with the amount of desired precision. Only the cost of producing the initial <MAT> state scales with the desired precision. But these setup costs are only paid once, and so can be amortized over the cost of every <MAT> operation performed.

The techniques described above with reference to <FIG> can be combined to provide an example method for performing individual (Zθ)<NUM>/<NUM> phase operations, e.g., <MAT> gates.

<FIG> is a circuit diagram <NUM> of an example quantum circuit for performing <MAT> operations. In this case, both a <MAT> state <NUM> and a <MAT> state <NUM> are provided as output from the example quantum circuit. <MAT> states are alternatively produced and consumed when performing lonely <MAT> operations, and in this case a <MAT> inner phasing operation is performed. The T-count of the <MAT> construction shown in <FIG> is therefore <MAT> <MAT>. In general, performing the <NUM>^k'th root of a T operation has a cost that satisfies the recurrence relation R(k) = <NUM>, R(k) = <NUM> + <NUM>/<NUM>*R(k) and is limited by an upper bound of <NUM>, no matter how fine the angle or the desired precision.

Three-quarters of the time, the above described phasing construction requires a second phasing operation with twice the angle of the target phasing operation to be performed. The second phasing operation may be performed using the same techniques. However, then the second phasing operation may also produce a third phasing operation by four times the angle of the original phasing operation. As long as the necessary states are prepared, this recursion can be continued as long as desired. (Although in practice, it may be terminated after a number of iterations determined by space-vs-time tradeoffs - more iterations saves more T gates, but more iterations requires more space.

The techniques described above with reference to <FIG> can be iterated to provide an example method that uses a ladder of phase operations to perform a target phase operation. For example, <FIG> is a circuit diagram of an example quantum circuit ladder construction <NUM> for iteratively performing (Zθ)<NUM>-n gates until a Zθ gate is performed. The example ladder construction <NUM> is shown as performing a T gate, but this is for convenience only and other phase operations may be performed.

As shown in <FIG>, the phasing operation to be performed delegates to an inner phasing operation, e.g., operation <NUM> of <FIG> and operations 802a-c of <FIG>, that phases by twice as much. When the starting point is an angle that becomes a multiple of <NUM> degrees after a reasonable number of multiplications by <NUM>, this process can be terminated with a T gate. A different approach is needed for angles with odd periods such as <NUM> degrees, angles that are irrational multiples of <NUM> degrees such as <NUM> radian, or angles that are so small that it would be unnecessarily costly to prepare all the necessary resource states reaching from the target angle all the way to the T gate. In these cases, a resource state can be prepared for the desired angle, twice the desired angle, four times the desired angle, etc. up to some finite length. In order to achieve a constant number of T gates, this length should scale asymptotically as lg(lg(<NUM>/epsilon)). In some cases, e.g., for practical purposes, the chain may have a length less than <NUM>. The phasing operation is then performed just as it would be for angles that terminate on a T gate, except when "the top of the chain is passed" an operation is applied "the hard way" with existing techniques. This changes the recurrence relation describing the cost from R(k) = <NUM>, R(k) = <NUM> + <NUM>/<NUM>*R(k) to R(k) = <NUM>*lg(<NUM>/epsilon), R(k) = <NUM> + <NUM>/<NUM>*R(k). Solving this recurrence relation and solving for length k for which R(k) <= <NUM> shows the lg(lg(<NUM>/epsilon)) scaling.

Once a chain of states has been prepared for a given angle, it can be used as much as possible before discarding. One particularly beneficial situation is when <NUM> or <NUM> operations need to be performed at the same time. For example, when there are two operations to perform, it is not necessary to produce an extra state or to consume an extra state. The example process <NUM> can be applied directly. This will cause a phasing operation of angle <NUM>θ to occur, but the cost of this underlying operation (and the adder) will be amortized over two desired operations instead of one. So instead of P[n] costing <NUM> + <NUM>/<NUM> R[n-<NUM>] as R[n] does, it costs (<NUM> + R[n-<NUM>])/<NUM> = <NUM> + <NUM>/<NUM> R[n-<NUM>]. A saving of <NUM>/<NUM> R[n-<NUM>] is achieved. Since R[k] converges to <NUM> for not-too-large k, this implies a saving of nearly ~<NUM> T gates. Furthermore, if θ<NUM>k happens to be a multiple of <NUM> degrees, then the process can be immediately terminated at the k-th level by applying a single T gate. <FIG> shows a first circuit diagram <NUM> of an example quantum circuit construction for amortizing gate costs over pairs of operations. <FIG> shows a second circuit diagram <NUM> of an example quantum circuit construction for amortizing gate costs over groups of <NUM> operations. Amortizing ladder climbing costs in this manner reduces the maximum average T-count from ~<NUM> to ~<NUM> or ~<NUM> respectively, because the apply-two-phasings-without-consuming-the-resource-state circuit can be used to its full potential, instead of having to alternate it with the circuit that consumes states.

Keeping extra states may be avoided through computing Hamming weights, as illustrated in <FIG> shows how interpolating further from iterative application of gates and closer to parallel application of gates causes expected costs to decrease. This is because the raw Hamming weight phasing technique is even more efficient than the iterative ladder based technique.

Implementations of the digital and/or quantum subject matter and the digital functional operations and quantum operations described in this specification can be implemented in digital electronic circuitry, suitable quantum circuitry or, more generally, quantum computational systems, in tangibly-embodied digital and/or quantum computer software or firmware, in digital and/or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term "quantum computational systems" may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

Implementations of the digital and/or quantum subject matter described in this specification can be implemented as one or more digital and/or quantum computer programs, i.e., one or more modules of digital and/or quantum computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The digital and/or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or a combination of one or more of them. Alternatively or in addition, the program instructions can be encoded on an artificially-generated propagated signal that is capable of encoding digital and/or quantum information, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode digital and/or quantum information for transmission to suitable receiver apparatus for execution by a data processing apparatus.

The term "data processing apparatus" refers to digital and/or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and/or quantum data, including by way of example a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing apparatus that is designed to simulate or produce information about a specific quantum system. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computation. The apparatus can optionally include, in addition to hardware, code that creates an execution environment for digital and/or quantum computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

A digital and/or quantum computer program may, but need not, correspond to a file in a file system. A digital and/or quantum computer program can be deployed to be executed on one digital or one quantum computer or on multiple digital and/or quantum computers that are located at one site or distributed across multiple sites and interconnected by a digital and/or quantum data communication network. A quantum data communication network is understood to be a network that may transmit quantum data using quantum systems, e.g. qubits. Generally, a digital data communication network cannot transmit quantum data, however a quantum data communication network may transmit both quantum data and digital data.

The processes and logic flows described in this specification can be performed by one or more programmable digital and/or quantum computers, operating with one or more digital and/or quantum processors, as appropriate, executing one or more digital and/or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA or an ASIC, or a quantum simulator, or by a combination of special purpose logic circuitry or quantum simulators and one or more programmed digital and/or quantum computers.

For a system of one or more digital and/or quantum computers to be "configured to" perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more digital and/or quantum computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by digital and/or quantum data processing apparatus, cause the apparatus to perform the operations or actions. A quantum computer may receive instructions from a digital computer that, when executed by the quantum computing apparatus, cause the apparatus to perform the operations or actions.

Digital and/or quantum computers suitable for the execution of a digital and/or quantum computer program can be based on general or special purpose digital and/or quantum processors or both, or any other kind of central digital and/or quantum processing unit. Generally, a central digital and/or quantum processing unit will receive instructions and digital and/or quantum data from a read-only memory, a random access memory, or quantum systems suitable for transmitting quantum data, e.g. photons, or combinations thereof.

The essential elements of a digital and/or quantum computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital and/or quantum data. The central processing unit and the memory can be supplemented by, or incorporated in, special purpose logic circuitry or quantum simulators. Generally, a digital and/or quantum computer will also include, or be operatively coupled to receive digital and/or quantum data from or transfer digital and/or quantum data to, or both, one or more mass storage devices for storing digital and/or quantum data, e.g., magnetic, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information. However, a digital and/or quantum computer need not have such devices.

Digital and/or quantum computer-readable media suitable for storing digital and/or quantum computer program instructions and digital and/or quantum data include all forms of non-volatile digital and/or quantum memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; CD-ROM and DVD-ROM disks; and quantum systems, e.g., trapped atoms or electrons. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Control of the various systems described in this specification, or portions of them, can be implemented in a digital and/or quantum computer program product that includes instructions that are stored on one or more non-transitory machine-readable storage media, and that are executable on one or more digital and/or quantum processing devices. The systems described in this specification, or portions of them, can each be implemented as an apparatus, method, or system that may include one or more digital and/or quantum processing devices and memory to store executable instructions to perform the operations described in this specification.

While operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Claim 1:
A method, performed by a quantum computing device, for applying a target phase to a first qubit of the quantum computing device and a second qubit of the quantum computing device by performing a phase operation on the first and second qubit using a third qubit of the quantum computing device prepared in a phased plus state, wherein the phased plus state comprises a plus state |+〉 = (|<NUM>〉 + <MAT> that has been phased by an angle equivalent to the target phase, where |o> and |<NUM>> are basis states,
wherein applying the target phase to the first and second qubits comprises:
performing a first NOT operation (<NUM>) on the third qubit;
computing a controlled adder operation (<NUM>) on the first, second and third qubits, comprising:
performing a multi target CNOT on the first, second and third qubits,
wherein the first qubit acts as the control;
computing a logical AND operation between the second and third qubits and encoding the result of the logical AND computation in a fourth qubit; and
performing a CNOT operation between the first qubit and the fourth qubit, wherein the first qubit acts as the control;
performing a square of the phase operation (<NUM>) on the fourth qubit;
uncomputing the controlled adder operation (<NUM>) on the first, second and third qubits, comprising:
performing a CNOT operation between the first qubit and the fourth qubit, wherein the first qubit acts as the control;
un-computing a logical AND operation between the second and third qubits; and
performing a multi target CNOT operation on the first, second and third qubits, wherein the first qubit acts as the control;
performing a CNOT operation (<NUM>) between the first qubit and the third qubit, wherein the first qubit acts as the control;
performing a CNOT operation (<NUM>) between the second qubit and the third qubit, wherein the second qubit acts as the control; and
performing a second NOT operation (<NUM>) on the third qubit.