Patent Description:
Examples of such multiple-access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, and orthogonal frequency division multiple access (OFDMA) systems, (e.g., a Long Term Evolution (LTE) system). A wireless multiple-access communications system may include a number of base stations, each simultaneously supporting communication for multiple communication devices, which may be otherwise known as user equipment (UE).

An error correcting code (ECC) may be used for improving throughput and reliability in channels with varying signal-to-noise ratio (SNR). Generally, an ECC adds redundancy information that allows a receiver to correctly reconstruct a transmitted signal in the presence of noise that may corrupt portions of the transmission. Types of ECCs include convolutional codes (CCs), turbo codes, low-density parity check (LDPC) codes, and the like. CCs are a family of codes that can be applied to a bit or symbol stream of arbitrary length. A terminated CC starts and ends at a known state. While terminated CCs have the benefit of starting and ending at the same known state (e.g., state <NUM>), they also require extra bits to be added, thereby reducing the effective data rate. Tail biting CCs (TBCCs) are a type of CC created by cyclic shifting the last few information bits (tail bits) in a CC to the beginning. Accordingly, the TBCC starts and ends at the same state (determined by these tail bits) without the impact to data rates of terminated CCs. A decoder employs a decoding technique that attempts to select a codeword (which may be, for example, encoded bits associated with a single same physical channel message) with a maximum likelihood of being the codeword that was sent, based at least in part on the received symbol information and properties of codewords inherent to the encoding scheme. The Viterbi algorithm (VA), which finds the most likely codeword (path), may be used for decoding codewords encoded with a terminated CC or TBCC. The list Viterbi algorithm (LVA) further reduces the codeword error rate by generating a list of the most likely paths, which are then tested in sequence against an error checking function to select the most likely candidate satisfying the error checking function.

<NPL> and <NPL> relate to rate-compatible punctured convolutional codes (RCPC codes) and their applications. <NPL> relates to a comparison of LDPC and convolutional codes. <NPL> and <NPL> relate to systematic LDPC convolutional codes and protograph based repeat accumulate codes, respectively.

An ECC may be employed to encode an input vector of known length to generate an encoded codeword. For example, an ECC may be used in combination with a checking function that takes a set of information bits of known length and adds a check code, which may be transmitted along with the information bits. A receiving device may detect errors in the received data based on checking the received information bits against the received check code. One commonly employed checking function is a cyclic redundancy check (CRC). In some cases, additional processing may be performed on an encoded codeword such as interleaving, rate matching, and symbol mapping prior to transmission. Use of larger encoded codewords reduces overhead and provides higher coding gain. However, larger encoded codewords result in a larger decoding delay and overall system latency. In contrast, smaller encoded codewords reduce latency or decoding delay but results in an increase in overhead and lower coding gain.

In the following, each of the described methods, apparatuses, examples and aspects which does not fully correspond to the invention as defined in the claims is thus not according to the invention and is, as well as the whole following description, present for illustration purposes only or to highlight aspects or features of the claims.

The described aspects relate to coding to improve transmission and reception processing time. Encoding of an input vector may begin prior to all bits of the input vector becoming available at the encoder. The encoder may output multiple sets of output bits, where each set of output bits corresponds to a set of input bits of the input vector. In some cases, the encoder may output a set of output bits prior to all bits of the input vector becoming available at the encoder. For a first set of output bits, the encoder may be initialized to a known state (e.g., where the encoder is a CC based encoder), while for subsequent sets of output bits, the encoder may be initialized based on one or more bits of a prior input vector. Each set of output bits may be individually processed for transmission in a transmission time interval or transmission symbol period. For example, a set of output bits may be separately interleaved and/or rate-matched to resources of the transmission time interval or transmission symbol period.

According to some aspects, a decoding delay may be reduced using a sliding-window for Viterbi decoding. A Viterbi decoder may identify path metrics over a sliding window, and employ back-tracking at each stage to generate hard decision bits for the trailing stage of the sliding window. The sliding window moves forward as additional branch metrics are available. The overall decoding delay is reduced as the complete trellis does not need to be back-tracked after the last input stage is received.

Aspects of the disclosure may increase performance in systems desiring or requiring high reliability and/or low latency traffic, for example traffic in ultra-reliable low latency communication (URLLC) systems. In some examples, latency for the transmission of data traffic may be reduced by beginning an encoding process for a set of data even before the complete set of data to be encoded is received at the encoder. In other examples, certain portions of a control message may be available for encoding, and received at the encoder, prior to other portions of a control message. It may be desirable to include the complete control message in a single codeword, and reduce latency. According to one or more aspects, portions of the control message to be encoded into a single codeword may commence encoding prior to the entire control message being available for encoding at the encoder, but the encoder may still be capable of generating a single encoded codeword for the entire control message.

Aspects of the disclosure are initially described in the context of a wireless communications system. Aspects of the disclosure are then described with reference to encoding configurations and processes. Aspects of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to coding to improve transmission and reception processing time.

<FIG> illustrates an example of a wireless communications system <NUM> that supports enhanced coding to improve transmission and reception processing time in accordance with one or more aspects of the present disclosure. The wireless communications system <NUM> includes base stations <NUM>, UEs <NUM>, and a core network <NUM>. In some examples, the wireless communications system <NUM> may be an LTE, LTE-Advanced, new radio (NR), or <NUM> network. In NR or <NUM> networks, the base stations <NUM> may include access nodes (ANs), central units (CUs), and/or distributed units (DUs). An AN may be an example of a new radio base station (NR BS), a new radio Node-B (NR NB), a network node (NN), or the like. A CU may be an example of a central node (CN), an access node controller <NUM>-a (ANC), or the like. Each of the DUs may be an example of an edge node (EN), an edge unit (EU), a radio head <NUM>-b (RH), a smart radio head (SRH), a transmission and reception point (TRP), or the like. The UEs <NUM>, base stations <NUM>, and other devices of wireless communications system <NUM> may have low-latency encoders that output codeword bits for transmission prior to loading all input bits. A base station <NUM> may include a base station transmission processor <NUM>, and a UE <NUM> may include a UE transmission processor <NUM>. These may be examples of a transmission processor <NUM>, <NUM>, or <NUM> as described with reference to <FIG>.

Base stations <NUM> (e.g., using ANCs <NUM>-a) may wirelessly communicate with UEs <NUM> via one or more RHs <NUM>-b, with each RH <NUM>-b having one or more base station antennas. Each base station <NUM> may provide communication coverage for a respective geographic coverage area <NUM>. A UE <NUM> may also be referred to as a mobile station, a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, a wireless communications device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. A UE <NUM> may also be a cellular phone, a personal digital assistant (PDA), a wireless modem, a wireless communication device, a handheld device, a tablet computer, a laptop computer, a cordless phone, a personal electronic device, a handheld device, a personal computer, a wireless local loop (WLL) station, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a machine type communication (MTC) device, an appliance, an automobile, or the like.

In some cases, a base station <NUM> and a UE <NUM> may communicate using carrier frequencies at <NUM> or less (sub-<NUM>), or higher such as <NUM>, <NUM>, etc. which is also known as millimeter wave communications. Each component can have a bandwidth of, e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. In some cases, a base station <NUM> and a UE <NUM> may communicate using more than one carrier in a carrier aggregation (CA) configuration. Each aggregated carrier is referred to as a component carrier. In some cases, the number of component carriers can be limited to, e.g., a maximum of five <NUM> carriers, giving maximum aggregated bandwidth of <NUM>. In frequency division duplexing (FDD), the number of aggregated carriers can be different in downlink and uplink. The number of uplink component carriers may be equal to or lower than the number of downlink component carriers. The individual component carriers can also be of different bandwidths. For time division duplexing (TDD), the number of component carriers as well as the bandwidths of each CC will normally be the same for downlink and uplink. Component carriers may be arranged in a number of ways. For example, a carrier aggregation (CA) configuration may be based at least in part on contiguous component carriers within the same operating frequency band, i.e., called intra-band contiguous CA. Non-contiguous allocations can also be used, where the component carriers may be either be intra-band, or inter-band.

Within a CA configuration, certain component carriers may be configured differently from other component carriers of the CA configuration. For example, the CA configuration may include a primary component carrier (PCC or PCell) and one or several secondary component carriers (SCC or SCell). The PCell may be configured to carry uplink and downlink control information on a physical uplink control channel (PUCCH) and a physical downlink control channel (PDCCH) or enhanced PDCCH (ePDCCH), respectively. PDCCH on a PCell may include scheduling information for resources of the PCell or for resources of one or more SCells, or both. An SCell may include PDCCH, which may include scheduling information for resources of that SCell or for one or more other SCells. Some SCells may be configured for downlink communications and may not be configured for uplink communications, while a PCell may be configured for both uplink and downlink communications. Various carriers of the CA may be TDD or FDD configured. A CA configuration may include both TDD and FDD configured carriers.

In some examples, NR or <NUM> networks may utilize eCCs, and the use of eCCs over a shared spectrum may be referred to as New Radio for Shared Spectrum (NR-SS). An SCell may, for instance, be an eCC. An eCC may be characterized by one or more features including: wider bandwidth, shorter symbol duration, shorter transmission time intervals (TTIs), and modified control channel configuration. An eCC may also be configured for use in unlicensed spectrum or shared spectrum (where more than one operator is allowed to use the spectrum). An eCC characterized by wide bandwidth may include one or more segments that may be utilized by UEs <NUM> that are not capable of monitoring the whole bandwidth or prefer to use a limited bandwidth (e.g., to conserve power). In some cases, an eCC may utilize a different symbol duration than other component carriers, which may include use of a reduced symbol duration as compared with symbol durations of the other component carriers. A shorter symbol duration is associated with increased subcarrier spacing. A device, such as a UE <NUM> or base station <NUM>, utilizing eCCs may transmit wideband signals (e.g., <NUM>, <NUM>, <NUM>, <NUM>, etc.) at reduced symbol durations (e.g., <NUM> microseconds). A TTI in eCC may consist of one or multiple symbols. In some cases, the TTI duration (that is, the number of symbols in a TTI) may be variable.

In some environments, reducing or minimizing system latency may be an important system performance factor. However, input bits of a single input vector may become available at different times. For example, an input vector may include information bits and check bits, where some or all information bits may be generated by or received from different sources. In addition, the check bits may not be available until sometime after all of the information bits are available. The input vector may be, for example, a physical channel message (e.g., control channel message). Additionally or alternatively, a codeword corresponding to a single input vector may not be transmitted in a single symbol period. For example, a physical channel message may span multiple symbol periods of a transmission.

System performance of transmission of information bits in low-latency environments may be determined by factors such as overhead, coding gain, transmission pipelining, and decoding delay. Some processing techniques may emphasize improving transmission pipelining and decoding delay at the expense of higher overhead and lower coding gain. Generally, use of larger encoded codewords reduces overhead and provides higher coding gain. However, larger encoded codewords may result in a larger decoding delay and overall system latency. In contrast, use of smaller encoded codewords may reduce latency or decoding delay but result in an increase in overhead and lower coding gain.

Components of the wireless communications system <NUM> including the base stations <NUM> or UEs <NUM> may implement enhanced coding techniques to improve transmission and reception processing time. Encoding of an input vector may begin prior to all bits of the input vector becoming available at the encoder. The encoder may output multiple sets of output bits, where each set of output bits corresponds to a set of input bits of the input vector. For a first set of output bits, the encoder may be initialized to a known state, while for subsequent sets of output bits, the encoder may be initialized based on one or more bits of a prior input vector. Each set of output bits may be individually processed for transmission in one or more transmission symbol periods, which may be a subset of a TTI. For example, each of multiple sets of output bits may be separately interleaved and/or rate-matched to resources of corresponding transmission symbol periods. An input vector includes information bits associated with a single message and may include check bits (e.g., CRC bits) used to implement a checking function. The encoder may implement, for example, a terminated CC, TBCC, turbo code, LDPC, and the like.

In some examples, decoding delay for components of the wireless communications system <NUM> including the base stations <NUM> or UEs <NUM> may be reduced using a sliding-window for Viterbi decoding. A Viterbi decoder may identify path metrics over a sliding window, and employ back-tracking at each stage to generate hard decision bits for the trailing stage of the sliding window. The sliding window moves forward as additional branch metrics are available. The overall decoding delay is reduced as the complete trellis does not need to be back-tracked after the last input stage is received.

<FIG> illustrates an example of a configuration <NUM> for enhanced coding to improve transmission and reception processing time, in accordance with one or more aspects of the present disclosure. Configuration <NUM> may include logic <NUM>, encoding processor <NUM>, and transmission component <NUM>. Configuration <NUM> may be included in a transmitting wireless device, and may be an example of aspects of one or more of the base stations <NUM> or the UEs <NUM> as described with reference to <FIG>.

Logic <NUM> may include an intelligent hardware device, such as a central processing unit (CPU), a microcontroller, an application specific integrated circuit (ASIC), etc. Logic <NUM> may determine input bits <NUM> to transmit to a receiving wireless device. The receiving wireless device may be a UE or base station, which may be examples of UEs <NUM> or base stations <NUM> as described with reference to <FIG>. As one example, logic <NUM> may be used by a base station <NUM> to determine specific information bits associated with a physical channel message (e.g., data bits, control bits, etc.) to send to a UE <NUM>. The input bits <NUM> may include both the information bits and CRC bits associated with those information bits. In some examples, logic <NUM> may receive information bits, organize such information bits, and generate CRC bits associated with the information bits. In some case, logic <NUM> may organize the input bits <NUM> as a single input vector made up of multiple sets of input bits <NUM>.

The sets of input bits <NUM> of the single input vector may be available at the output of logic <NUM> at the same time. However, availability for the sets of input bits <NUM> may also be non-concurrent. For example, some of the specific information bits may depend on feedback received from a receiving device (e.g., a UE <NUM>, where the transmitting device is a base station <NUM>). Logic <NUM> may perform response processing on the received feedback, and continue to append input bits <NUM> of the single input vector after at least a portion of input bits <NUM> are ready. Thus, the specific information bits may be determined by logic <NUM> over a time period, which may correspond, for example, to multiple transmission symbol periods. The time period may be, for example, a TTI including multiple symbol periods, one or more subframes, one or more slots, etc..

For example, base station <NUM> may receive multiple different sets of feedback (e.g., acknowledgement (ACK) or non-acknowledgement (NAK) information) from a UE <NUM>, over a period of time, that are used by logic <NUM> to determine input bits <NUM>. Logic <NUM> may determine a portion (e.g., a set) of the total number of information bits individually based on each set of feedback received from UE <NUM>. Therefore, the total number of input bits <NUM> that are associated with the same physical channel message may be broken up into multiple different input bit sets and made available by logic <NUM> to encoding processor <NUM> at different times. Additionally or alternatively, each of the sets of input bits <NUM> may be associated with transmission during a transmission symbol period. For example, a single input vector may be transmitted over multiple transmission symbol periods.

Encoding processor <NUM> may encode input bits <NUM> to transmit to a wireless device. In some examples, a base station <NUM> may use encoding processor <NUM> to encode input bits <NUM> determined by logic <NUM>. Encoding processor <NUM> may perform an encoding process (e.g., convolutional coding, tail-biting convolutional coding, LDPC coding, turbo coding, etc.). In some cases, only a portion of the total number of input bits <NUM> may be encoded at a given time (e.g., due to feedback from a UE <NUM>, processing time, etc.). As an example, after encoding a subset of the input bits <NUM> from a single input vector at a given time, encoding processor <NUM> may output the output bits of the codeword generated from the subset of the input bits <NUM> and wait for more input bits <NUM> of the input vector to become available before continuing the encoding process. In some cases, while encoding processor <NUM> is encoding a subsequent portion of input bits <NUM> or waiting for further input bits <NUM> to be available from logic <NUM>, interleaving and rate matching of the previously encoded bits may occur. For example, interleaving and rate matching may be performed on a subset of the encoded output bits for mapping to resources of a single symbol period. Encoding, interleaving, and rate matching may occur at different times (e.g., for different sets of output bits of the single codeword associated with the input vector). For example, a single CRC may be used for the single input vector, while interleaving and rate matching occurs separately and at different times for different subsets of the output bits associated with the codeword. The encoded, interleaved, and rate matched bits may then be output from encoding processor <NUM> as processed bits <NUM>.

Transmission component <NUM> may transmit encoded bits (e.g., processed bits <NUM> received from encoding processor <NUM>) to a receiving device (e.g., a UE <NUM> where the transmitting device is a base station <NUM>). In some examples, transmission component <NUM> may take processed bits <NUM> made available by encoding processor <NUM> and perform a number of operations before transmitting to the UE <NUM>. As an example, transmission component <NUM> may first modulate the processed bits <NUM>, then map the modulated bits to available time-frequency resources (e.g., symbols). Finally, information may be sent to one or multiple antennas that are a part of transmission component <NUM> for transmission to the UE <NUM>.

In some examples, transmission component <NUM> may begin wireless transmissions from configuration <NUM> prior to all input bits <NUM> of a single input vector having been received by encoding processor <NUM> and output as processed bits <NUM>. In some examples, transmission component <NUM> may transmit a first set of processed bits <NUM> associated with a single input vector in a first transmission symbol before a last input bit of the single input vector is received at encoding processor <NUM> of configuration <NUM>. In other examples, transmission component <NUM> may transmit the first set of processed bits <NUM> associated with a single input vector in a first transmission symbol before a last input bit of a second set of input bits (the second set of input bits immediately following the first set of input bits) of the single input vector is received at encoding processor <NUM>. In still other examples, transmission component <NUM> may transmit a first set of processed bits <NUM> associated with the single input vector in a transmission symbol before a first input bit of the second set of input bits is received at encoding processor <NUM>.

In further examples, transmission component <NUM> may begin wireless transmissions from configuration <NUM> (e.g., from a transmitting device such as base station <NUM> or UE <NUM>) prior to all input bits <NUM> of a single input vector having been processed by encoding processor <NUM> and output as processed bits <NUM>. In some examples, transmission component <NUM> may begin wireless transmissions from configuration <NUM> prior to all input bits <NUM> (including the last input bit) of a single input vector having been processed by encoding processor <NUM> and output as processed bits <NUM>. In yet other examples, transmission component <NUM> may begin transmitting prior to all input bits <NUM>, including the last input bit, of a second set of input bits <NUM> having been processed. In still other examples, transmission component <NUM> may begin transmitting prior to a first bit of a second set of input bits <NUM> having been processed by encoding processor <NUM> and output as processed bits <NUM>, the second set of input bits of the single input vector immediately following the first set of input bits of the single input vector.

<FIG> illustrates an example of an encoding processor <NUM> for enhanced coding to improve transmission and reception processing time, in accordance with one or more aspects of the present disclosure. Encoding processor <NUM> may be an example of encoding processor <NUM> as described with reference to <FIG>. Encoding processor <NUM> may include encoder <NUM>, interleaver <NUM>, and rate matcher <NUM>. In some cases, encoding processor <NUM> may include a plurality of different components used to perform aspects of an encoding process. The different components may be included in encoding processor <NUM> in an order as illustrated in <FIG> and as described below, or the components may have a different order or configuration. For example, rate matcher <NUM> may follow encoder <NUM>, while interleaver <NUM> may follow rate matcher <NUM>, or interleaver <NUM> may be a part of rate matcher <NUM>, and interleaving may be performed as part of a rate matching process.

Encoding processor <NUM> may include encoder <NUM>, which may perform a first operation in an encoding process. Encoder <NUM> may begin encoding (e.g., convolutional coding, tail-biting convolutional coding, LDPC coding, turbo coding, etc.) as input bits <NUM>-a become available. Input bits <NUM>-a may be an example of input bits <NUM> as described with reference to <FIG>. For example, an encoder may receive a portion (e.g., a set) of the total number of input bits <NUM>-a and begin encoding that set of input bits <NUM>-a. After encoding the available input bits <NUM>-a, encoder <NUM> may pause encoding to wait for more input bits <NUM>-a to become available. Encoder <NUM> may also pause encoding the input bits <NUM>-a prior to completing encoding, for example because the encoder may apply a sliding or shifting operation (e.g., CC) sequentially over the input bits while operating on more than one bit at a time for generating each bit or state output, such that one or more bits from a second portion of input bits <NUM>-a may be used by the encoder to complete encoding the last one or more bits of the first portion of input bits <NUM>-a. In some examples, while encoder <NUM> waits for more input bits <NUM>-a, the encoded output bits <NUM> may undergo additional processing in the encoding processor <NUM>, such as interleaving and rate matching.

Interleaver <NUM> may produce interleaved bits <NUM> from encoded output bits <NUM>. In some cases, interleaver <NUM> may perform an interleaving process to reduce the impact of burst errors, for example by increasing the likelihood that a burst error may be successfully corrected by a CRC process at a receiving device.

In some examples, a set of output bits associated with a single symbol period may be interleaved with other bits of the same set of output bits, but independent of other sets of output bits. For example, the bits for transmission in a single symbol period may be interleaved with other bits for transmission within that same symbol period, but not with bits of other symbol periods, even if the bits of other symbol periods are associated with the same single input vector that is being processed.

Rate matcher <NUM> may perform a rate matching process on interleaved bits <NUM>. In some cases, the rate matching process may include rate matcher <NUM> matching a number of bits to be transmitted (e.g., interleaved bits <NUM>) to transmission resources allocated for transmitting the bits as processed bits <NUM>-a. Processed bits <NUM>-a may be an example of processed bits <NUM> as described with reference to <FIG>. Rate matching may include one or more of puncturing, repetition, or pruning.

In some examples, the amount of resources available in each symbol period (e.g., of a TTI, slot, or subframe) may be different. In some examples, rate matcher <NUM> may match a single set of processed bits <NUM> to match the resources available in a single symbol period of a transmission. In some cases, a single input vector may be partitioned into sets of input bits <NUM>-a that are differently sized (e.g., by logic <NUM> as discussed with reference to <FIG>) so that each set of interleaved bits <NUM> may be rate matched at the same rate (e.g., substantially the same rate) into each symbol period by rate matcher <NUM>. Logic <NUM> may obtain information regarding the amount of resources available in a symbol period of a transmission when dividing the single input vector into sets of input bits <NUM>-a.

In other cases, the single input vector may be partitioned into uniformly-sized (e.g., substantially uniformly-sized) sets of input bits <NUM>-a, such that each set of interleaved bits <NUM> are correspondingly uniformly-sized (e.g., substantially uniformly-sized). Rate matcher <NUM> may then perform different levels of rate matching from symbol to symbol on the interleaved bits <NUM> to match the interleaved bits <NUM> to the amount of resources available in a given symbol period. Thus, rate matcher <NUM> may use information regarding the amount of resources available in a symbol to be transmitted when performing rate matching, while logic <NUM> may not use such information.

<FIG> illustrates an example of a transmission component <NUM> for coding to improve transmission and reception processing time, in accordance with one or more aspects of the present disclosure. Transmission component <NUM> may be an example of transmission component <NUM> as described with reference to <FIG>. Transmission component <NUM> may include a modulator <NUM>, resource mapper <NUM>, and antenna <NUM>. In some cases, transmission component <NUM> may include a plurality of different components used to perform aspects of a transmission process. The different components may be included in transmission component <NUM> in an order as illustrated in <FIG> and as described below, or the components may have a different order or configuration.

Modulator <NUM> may modulate the processed bits <NUM>-b. Information bits output from an encoding process (e.g., information bits that may be encoded, interleaved, and rate matched) may be made available to modulator <NUM> as processed bits <NUM>-b. Processed bits <NUM>-b may be an example of processed bits <NUM> or <NUM>-a as described with reference to <FIG> and <FIG>. In some cases, modulator <NUM> may modulate the processed bits <NUM>-b according to a specific modulation scheme (e.g., quadrature phase shift keying (QPSK), <NUM> quadrature amplitude modulation (<NUM>-QAM), etc.). Modulated information <NUM> may then be output by modulator <NUM>.

Modulator <NUM> may include a number of different components used to perform specific tasks. For example, modulator <NUM> may include inverse fast Fourier transform (IFFT) component <NUM>. IFFT component <NUM> may be used by modulator <NUM> to convert information bits from a frequency domain representation to a time domain representation. Modulator <NUM> may also include cyclic prefix (CP) component <NUM>. In some cases, CP component <NUM> may be used by modulator <NUM> to add a CP to a transmission. The CP may have a predetermined length (e.g., an extended length or normal length) and be used to provide protection against multi-path delay spread. As an example, CP component <NUM> may generate a CP for a transmission by copying the end of the main body of a symbol (e.g., an orthogonal frequency division multiplexing (OFDM) symbol) to the beginning of the symbol.

Resource mapper <NUM> may map the modulated information <NUM> (e.g., symbols) to available time-frequency resources in a transmission process. For example, resource mapper <NUM> may first receive modulated information <NUM> that is output by modulator <NUM>. Resource mapper <NUM> may then map the modulated information <NUM> to available resources in preparation for transmission. In some cases, resource mapper <NUM> may map the modulated information <NUM> that is associated with a set of information bits to a symbol. The output of resource mapper <NUM> may be referred to as mapped information <NUM>.

Antenna <NUM> may perform aspects of a transmission process for a wireless device. In some cases, transmission component <NUM> may include a single antenna <NUM> or multiple antennas <NUM>. As an example, a base station <NUM> may include multiple antennas <NUM> which may be capable of concurrently transmitting or receiving multiple wireless transmissions. Multiple antennas <NUM> may receive mapped information <NUM> from resource mapper <NUM> and send a transmission <NUM> to a receiving device (e.g., a UE <NUM> when transmission component <NUM> is part of the base station <NUM>). Transmission <NUM> may contain all or a portion of a message (e.g., a set of encoded information bits associated with a larger codeword).

<FIG> illustrates an example diagram <NUM> for coding to improve transmission and reception processing time, in accordance with one or more aspects of the present disclosure. In an example, a base station <NUM> may desire to transmit a single input vector <NUM> to a UE <NUM>, or the UE <NUM> may desire to transmit a single input vector <NUM> to the base station <NUM>. The single input vector <NUM> may be associated with a single physical channel message. The single input vector <NUM> may be encoded during a process into a single codeword (e.g., a process such as encoding process <NUM> as described with reference to <FIG> below).

In some examples, the single input vector <NUM> may include information bits <NUM>. Single input vector <NUM> may also include a CRC portion <NUM>. In some examples, the single input vector <NUM> may include multiple CRC portions, which may be at intermediate positions within the single input vector <NUM>. CRC portion <NUM> may, for example, provide redundancy to single input vector <NUM> and assist with error detection and correction. CRC portion <NUM> may include a number of bits that may be used to indicate redundancy information for all of the information bits <NUM>. In some examples, single input vector <NUM> may be interleaved, such that the CRC portion <NUM> may be interleaved among information bits <NUM>.

Prior to encoding, the single input vector <NUM> may be divided into multiple input bit sets <NUM>. In an example, the single input vector <NUM> may include a first input bit set <NUM>-a, a second input bit set <NUM>-b, a third input bit set <NUM>-c, and a fourth input bit set <NUM>-d. In some examples, each input bit set <NUM>-a may correspond to a single time period of a transmission (e.g., a transmission symbol period). It may be advantageous to transmit the bits of single input vector <NUM> together in a single encoded codeword, rather than encoding a codeword for each input bit set to be separately transmitted for the reasons described above (e.g., higher coding gain). However, it may also be advantageous to begin encoding the first input bit set <NUM>-a when it arrives at an encoding processor (e.g., encoding processor <NUM> or <NUM>, as described with reference to <FIG> and <FIG>) for a shorter decoding delay. In this way, the first input bit set <NUM>-a may be encoded before a later input bit set <NUM> (e.g., the fourth input bit set <NUM>-d) is received at the encoding processor.

A single input vector <NUM> is partitioned (e.g., by logic <NUM>) into multiple bit sets for processing based in part on the amount of resources available in a symbol in which the processed bit sets will be sent. For example, single input vector <NUM> may be partitioned into a first input bit set <NUM>-a, a second input bit set <NUM>-b, a third input bit set <NUM>-c, and a fourth input bit set <NUM>-d based in part on the amount of resources available in each of the respective symbol periods in which processed bits will be sent. In such case the first input bit set <NUM>-a, second input bit set <NUM>-b, third input bit set <NUM>-c, and fourth input bit set <NUM>-d may be of different bit length. In other examples, single input vector <NUM> may be partitioned into uniformly sized portions of bits. For example, single input vector <NUM> may be partitioned into a first input bit set <NUM>-a, a second input bit set <NUM>-b, a third input bit set <NUM>-c, and a fourth input bit set <NUM>-d, each having the same bit length. Processed bits, based on the input bit sets, may then be rate matched individually into the resources of each symbol period used for transmission.

<FIG> illustrates an example of encoding process <NUM> for enhanced coding to improve transmission and reception processing time, in accordance with one or more aspects of the present disclosure. In some cases, the encoding process may be performed by encoding processor <NUM> or encoding processor <NUM> as described with reference to <FIG> and <FIG>.

As an example, encoding process <NUM> may be used to encode single input vector <NUM>, which may be an example of a single input vector <NUM> as described with reference to <FIG>, into a single codeword. Single input vector <NUM> may be associated with a physical channel message (e.g., a control channel message) and may include one or more information bits and/or CRC bits. Logic <NUM>, as described with reference to <FIG>, may be used to determine single input vector <NUM> for transmission, and make bits associated with the single input vector <NUM> available to an encoding processor.

In some cases, single input vector <NUM> may be divided up into a number of different input bit sets <NUM>. For example, different input bit sets <NUM> may be made available at different times to encoding process <NUM> (e.g., due to feedback from a UE <NUM>, processing time, etc.). First input bit set <NUM>-a may include a number of bits <NUM> (e.g., bits <NUM>-a, <NUM>-b, <NUM>-c, <NUM>-d, and <NUM>-e) that are associated with a first portion of single input vector <NUM> made available at a first time period to encoding process <NUM>, while second input bit set <NUM>-b may include a number of bits that are associated with a second portion of single input vector <NUM> and made available at a subsequent time period to encoding process <NUM>.

Encoding process <NUM> may use window <NUM> to generate output bits for the codeword. Window <NUM> may have a predetermined size (e.g., <NUM> input bits as illustrated in <FIG>), which may be based on the constraint length of the code. In some cases, the input to the encoding process <NUM> is a single input vector (e.g., single input vector <NUM>) determined by logic <NUM>. Encoding commences before all input bits or input bit sets <NUM> associated with single input vector <NUM> are available. That is, encoding process <NUM> may start as soon as first input bit set <NUM>-a is made available, even if other input bit sets <NUM> that make up single input vector <NUM> (e.g., second input bit set <NUM>-b) are not yet available.

According tot he invention, a shift register is used. The shift register may be initialized (e.g., all bits set to <NUM> or another predetermined state) and at operation <NUM> first bit <NUM>-a of single input vector <NUM> (which may be a first bit of first input bit set <NUM>-a) may be an input to the shift register. Window <NUM> may be used to generate a number of encoded output bits associated with the information in the shift register. In some cases, the number of input bits is associated with a constraint length of the shift register. Additionally or alternatively, output bits may be interleaved and rate matched as they are output from the encoder, or a device may wait for a number of encoded bits to be output (e.g., all of the output bits associated with a certain input bit set <NUM>) before performing interleaving and rate matching (e.g., rate matching and interleaving may occur on a per symbol or per bit set basis, such as for input bit set <NUM>).

Operation <NUM> may be a second operation of encoding process <NUM>. At operation <NUM>, second bit <NUM>-b of single input vector <NUM> may be input to a shift register to output a next output bit. Subsequent bits <NUM> of the input bit set <NUM>-a of single input vector <NUM> may then be input to the shift register and subsequent output bits generated.

Operation <NUM> of encoding process <NUM> may occur a number of operations after operation <NUM>. At operation <NUM>, last bit <NUM>-e associated with first input bit set <NUM>-a, may be input to the shift register (e.g., the <NUM> stage shift register). In some cases, second input bit set <NUM>-b may not yet be available to encoding process <NUM> at the time that last bit <NUM>-e associated with first input bit set <NUM>-a has been input to the shift register. In such a case, encoding process <NUM> may stop and wait (e.g., pause) for the arrival of second input bit set <NUM>-b before resuming, so that the first input bit of the second input bit set <NUM>-b may be input into the shift register. In some examples, while encoding process <NUM> is waiting for the arrival of a second input bit set <NUM>-b associated with single input vector <NUM>, rate matching and interleaving may be performed on the already-generated output bits associated with first input bit set <NUM>-a. In further examples, modulation and transmission of the already generated output bits may also occur during the waiting period. To complete the encoding process for the single input vector <NUM>, known bits <NUM> may be provided to the shift register after the last input bit from the final input bit set <NUM> has been input to the shift register. For example, in the case of the <NUM> stage shift register, two known bits <NUM> (e.g., bits <NUM>-a and <NUM>-b) may be input into the shift register after the last input bit from the final input bit set <NUM>. This may allow the shift register to fully encode the last input bit from the final input bit set <NUM>. By providing termination states to the shift register, the encoder may output the final output bit or bits.

Aspects of the encoding process may be performed by various different encoding techniques. According to the invention, the encoding is carried out by applying one of a convolutional code or tail-biting convolutional code. For example, if tail-biting convolutional coding is used, a number of bits of single input vector <NUM> may be stored and appended at the end of an information bit-stream (e.g., at the end of single input vector <NUM>). In such a case, encoding process <NUM> may not begin until a number of bits are input into a shift register and may not stop when the last information bits are input to the shift register. For example, in the case of the <NUM> stage shift register, encoding process <NUM> may begin when the first three bits of single input vector <NUM> are input into the shift register, and the first two bits of single input vector <NUM> may be stored and appended at the end of single input vector <NUM>.

<FIG> illustrates an example of resources <NUM> for enhanced coding to improve transmission and reception processing time, in accordance with one or more aspects of the present disclosure. Resources <NUM> may be distributed over time and frequency resources and may be an example of a TTI, slot, or subframe.

Resources <NUM> may be divided up into a number of symbols <NUM>, including symbols <NUM> through N (e.g., <NUM> symbols), for example by resource mapper <NUM> as described with reference to <FIG>. During the symbol period for a symbol <NUM>, resource mapper <NUM> or a similar device may allocate a number of subcarriers (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.) of a carrier for transmission. In some cases, transmission of information such as a codeword (e.g., generated as a result of encoding process <NUM> as described with reference to <FIG>) for a single input vector may occur over multiple symbols <NUM>. Each portion of the encoded codeword may be transmitted in a separate symbol <NUM>. In some examples, a single codeword may be transmitted in a single symbol period, and may occupy fewer than all the resources of the symbol period.

In some cases, a first transmission portion <NUM> for the codeword may occur in first symbol <NUM>-a of resources <NUM>. The first transmission portion <NUM> may be for a first set of bits output from an encoder. In some examples, the first transmission portion <NUM> may be separately interleaved, rate matched, modulated, etc., from subsequent transmission portions. For example, bits of first transmission portion <NUM> within symbol <NUM> may be interleaved with other bits of first transmission portion <NUM>, but independent of any bits of transmission portions within other symbols, such as a second transmission portion <NUM>. As an example, first transmission portion <NUM> may include a first portion of a codeword as described with reference to <FIG>.

Second transmission portion <NUM> for the codeword may occur in a subsequent symbol <NUM> of resources <NUM>. The second transmission portion <NUM> may be for a second set of bits output from the encoder (e.g., after interleaving, rate matching, modulation, etc.). In some cases, the second transmission portion <NUM> may be sent in second symbol <NUM>-b of resources <NUM> (which may immediately follow first symbol <NUM>-a) or the second transmission portion <NUM> may be sent in later symbol <NUM>-c (which may occur a number of symbols after first symbol <NUM>-a). One or more subsequent transmission portions may follow until a last transmission portion <NUM> of the codeword in a symbol <NUM>, such as symbol <NUM>-d, of resources <NUM>. During transmission portion <NUM>, a final portion of the codeword may be transmitted.

<FIG> illustrates an example of a sliding window based Viterbi decoding process <NUM> for coding to improve transmission and reception processing time, in accordance with one or more aspects of the present disclosure. Trellis <NUM> represents transitions <NUM> between the various possible states <NUM> of an encoder as a function of time. In <FIG>, states <NUM> are represented by boxes and transitions <NUM> by arrows between states <NUM>. Each state <NUM> (e.g., state <NUM>, state <NUM>, state <NUM>, and state <NUM>) at a particular time is represented by a row in the trellis <NUM>. For example, every box in the top row of the trellis <NUM> represents state <NUM>. A path is made up of a series of transitions <NUM> between states <NUM>. The possible codewords are represented by paths through the trellis <NUM>. For a Viterbi decoder, as symbols are received, a metric associated with a distance between the symbols that were received and the possible symbols may be calculated. In the sliding window based Viterbi decoding process <NUM>, a finite sized trellis window <NUM> may be used to decode bits, frames, or other sets of data within the trellis window. The finite sized trellis window <NUM> shifts to the right as an encoded codeword is received and decoded. The codeword may be encoded according to the encoding processes described above with reference to <FIG>. In this example, finite sized trellis window <NUM>-a may begin to decode the received codeword as it is received and a sufficient number of bits have been received to fill the trellis window. In some examples, the size of the trellis window may be sufficiently small relative to the size of the codeword so that decoding may begin prior to receiving the entire codeword. For example, a codeword may be received in sets of bits to be decoded. Decoding accuracy may be increased by increasing the size of the trellis window, but an increase in the size of the trellis window may increase processing time and also increase the amount of latency until further decoding (e.g., error checking using CRC, etc.) of the received codeword may begin.

For the sliding window based Viterbi decoding process <NUM> illustrated in <FIG>, back tracking and decoding may occur with each advance of the finite sized trellis window <NUM>. For one advance of the trellis window, the bits associated with one stage are decoded. Viterbi decoding for the bits that fall within finite sized trellis window <NUM>-a may result in a decoded state <NUM> (i.e., hard decision bits) output (corresponding to one of state <NUM>, state <NUM>, state <NUM>, state <NUM> as determined by the Viterbi decoding). For example, finite sized trellis window <NUM>-a may output a hard decision bit of state <NUM> for the decoded state <NUM>. The trellis window then proceeds to encompass a new set of states <NUM> (e.g., finite sized trellis window <NUM>-a shifts to become finite sized trellis window <NUM>-b). This process continues until the trellis window has advanced to the end of the codeword and the decoder has output the decoded bits. The decoded state <NUM> for a previous stage may constrain the paths selected by a current back-tracking stage. For example, one or more best paths selected may be constrained to back-track to the decoded state <NUM> (e.g., state <NUM>).

In this implementation, the codeword corresponds to a single encoded input vector, such that if the encoded codeword is received in sets of bits, the sliding window based Viterbi decoder may output a continuous set of bits associated with the single input vector as sets of bits are received. For example, if a first set of bits from the codeword are received, the decoder may decode those bits, then pause until a second set of bits from the codeword are received, and so on until the end of the codeword.

<FIG> shows a block diagram <NUM> of a wireless device <NUM> that supports enhanced coding to improve transmission and reception processing time in accordance with one or more aspects of the present disclosure. Wireless device <NUM> may be an example of aspects of a UE <NUM> or base station <NUM> as described with reference to <FIG>. Wireless device <NUM> may include receiver <NUM>, transmission processor <NUM>, and transmitter <NUM>. Wireless device <NUM> may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses).

Receiver <NUM> may receive information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, and information related to coding to improve transmission and reception processing time, etc.). Information may be passed on to other components of the device. The receiver <NUM> may be an example of aspects of the transceiver <NUM> or <NUM> as described with reference to <FIG> and <FIG>.

Transmission processor <NUM> may be an example of aspects of the logic <NUM>, encoding processor <NUM> or <NUM>, transmission component <NUM> or <NUM>, base station transmission processor <NUM> or <NUM>, and UE transmission processor <NUM> or <NUM> as described with reference to <FIG>, <FIG>, and <FIG>. Transmission processor <NUM> and/or at least some of its various sub-components may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of the transmission processor <NUM> and/or at least some of its various sub-components may be executed by a general-purpose processor, a digital signal processor (DSP), an ASIC, an field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. The transmission processor <NUM> and/or at least some of its various sub-components may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations by one or more physical devices. In some examples, transmission processor <NUM> and/or at least some of its various sub-components may be a separate and distinct component in accordance with various aspects of the present disclosure. In other examples, transmission processor <NUM> and/or at least some of its various sub-components may be combined with one or more other hardware components, including but not limited to an I/O component, a transceiver, a network server, another computing device, one or more other components described in the present disclosure, or a combination thereof in accordance with various aspects of the present disclosure.

Transmission processor <NUM> may receive, at an encoder of the transmitting device, multiple sets of input bits associated with a single input vector to be encoded into a single codeword, process, by the encoder, the multiple sets of input bits, including a first set of input bits and a second set of input bits, to generate multiple sets of output bits, each set of output bits associated with one of a set of transmission symbol periods, and output, from the encoder, a first set of output bits of the multiple sets of output bits associated with a first transmission symbol period of the set of transmission symbol periods prior to receiving all input bits of the second set of input bits of the multiple sets of input bits, the second set of input bits being received at the encoder subsequent to the first set of input bits.

For example, the transmitter <NUM> may be an example of aspects of the transceiver <NUM> or <NUM> as described with reference to <FIG> and <FIG>.

<FIG> shows a block diagram <NUM> of a wireless device <NUM> that supports enhanced coding to improve transmission and reception processing time in accordance with one or more aspects of the present disclosure. Wireless device <NUM> may be an example of aspects of a wireless device <NUM> or a UE <NUM> or base station <NUM> as described with reference to <FIG> and <FIG>. Wireless device <NUM> may include receiver <NUM>, transmission processor <NUM>, and transmitter <NUM>. Wireless device <NUM> may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses).

Transmission processor <NUM> may be an example of the transmission processor <NUM> as described with reference to <FIG>. Transmission processor <NUM> may also include encoder reception component <NUM>, encoder <NUM>, and encoder output component <NUM>. Encoder reception component <NUM> may be an example of a portion of encoding processor <NUM> or <NUM> as described with reference to <FIG> and <FIG>. Encoder <NUM> may be an example of a portion of encoding processor <NUM> or <NUM> and encoder <NUM> as described with reference to <FIG> and <FIG>. Encoder output component <NUM> may be an example of a portion of encoding processor <NUM> or <NUM> as described with reference to <FIG> and <FIG>.

Encoder reception component <NUM> may receive multiple sets of input bits associated with a single input vector to be encoded into a single codeword. In some cases, at least one of the multiple sets of input bits includes a different number of bits than at least one other of the multiple sets of input bits.

Encoder <NUM> may process the multiple sets of input bits, including a first set of input bits and a second set of input bits, to generate multiple sets of output bits, each set of output bits associated with one of a set of transmission symbol periods. In some cases, an initial state of each of the multiple sets of output bits is determined based on one or more input bits from one of the multiple sets of input bits or an initial encoder <NUM> state. In some cases, the set of transmission symbol periods include contiguous transmission symbol periods. In some cases, the processing of the multiple sets of input bits includes: applying a convolutional code, tail-biting convolutional code, LDPC code, or turbo code to generate the multiple sets of output bits.

Encoder output component <NUM> may output a first set of output bits of the multiple sets of output bits associated with a first transmission symbol period of the set of transmission symbol periods prior to receiving all input bits of a second set of input bits of the multiple sets of input bits, the second set of input bits being received at the encoder <NUM> subsequent to the first set of input bits. Encoder <NUM> may pause the processing after outputting the first set of output bits to wait for the second set of input bits to be received at the encoder reception component <NUM>. In some cases, outputting the multiple sets of output bits is based at least in part on the first set of input bits and the second set of input bits, and is independent of subsequently received sets of input bits being associated with a second input vector to be encoded into a second codeword.

<FIG> shows a block diagram <NUM> of a transmission processor <NUM> that supports enhanced coding to improve transmission and reception processing time in accordance with one or more aspects of the present disclosure. The transmission processor <NUM> may be an example of aspects of a transmission processor <NUM> or <NUM>, a base station transmission processor <NUM> or <NUM>, and a UE transmission processor <NUM> or <NUM> as described with reference to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. The transmission processor <NUM> may include encoder reception component <NUM>, encoder <NUM>, encoder output component <NUM>, interleaver <NUM>, rate matcher <NUM>, and transmission component <NUM>. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses). Encoder reception component <NUM> may be an example of encoder reception component <NUM> and a portion of encoding processor <NUM> or <NUM> as described with reference to <FIG>, <FIG>, and <FIG>. Encoder <NUM> may be an example of encoder <NUM>, encoder <NUM>, and encoding processor <NUM> or <NUM> as described with reference to <FIG>, <FIG>, and <FIG>. Encoder output component <NUM> may be an example of encoder output component <NUM> and a portion of encoding processor <NUM> or <NUM> as described with reference to <FIG>, <FIG>, and <FIG>.

Encoder <NUM> may process the multiple sets of input bits, including a first set of input bits and a second set of input bits, to generate multiple sets of output bits, each set of output bits associated with one of a set of transmission symbol periods. In some cases, an initial state of each of the multiple sets of output bits is determined based on one or more input bits from one of the multiple sets of input bits or an initial encoder (e.g., encoder <NUM>) state. In some cases, the set of transmission symbol periods include contiguous transmission symbol periods. In some cases, the processing of the multiple sets of input bits includes: applying a convolutional code, tail-biting convolutional code, LDPC code, or turbo code to generate the multiple sets of output bits.

Encoder output component <NUM> may output a first set of output bits of the multiple sets of output bits associated with a first transmission symbol period of the set of transmission symbol periods prior to receiving all input bits of the second set of input bits of the multiple sets of input bits, the second set of input bits being received at the encoder subsequent to the first set of input bits and pause the processing after outputting the first set of output bits to wait for the second set of input bits to be received at the encoder reception component <NUM>. In some cases, outputting the multiple sets of output bits is based at least in part on the first set of input bits and the second set of input bits, and is independent of subsequently received sets of input bits being associated with a second input vector to be encoded into a second codeword.

Interleaver <NUM> may perform interleaving of each of the multiple sets of output bits independently of each other of the multiple sets of output bits and perform interleaving of a first of the multiple sets of output bits independently of each other of the multiple sets of output bits before receiving all the input bits associated with the single input vector at the encoder at the encoder reception component <NUM>.

Rate matcher <NUM> may perform rate matching on the first set of output bits to match a number of bits of the first set of output bits to a set of resources in the first transmission symbol period and perform rate matching on the first set of output bits to match the number of bits of the first set of output bits to the set of resources in the first transmission symbol period before receiving all the input bits associated with the single input vector at the encoder reception component <NUM>.

Transmission component <NUM> may transmit the first set of output bits in the first transmission symbol period before a last input bit of the set of sets of input bits is received at the encoder reception component <NUM> of the transmitting device. In some cases, the first set of output bits is transmitted in the first transmission symbol period before a last input bit of the second set of input bits is received at the encoder reception component <NUM> of the transmitting device. In some cases, the first set of output bits is transmitted in the first transmission symbol period before completing processing of all of the multiple sets of input bits.

<FIG> shows a diagram of a system <NUM> including a device <NUM> that supports coding to improve transmission and reception processing time in accordance with one or more aspects of the present disclosure. Device <NUM> may be an example of or include the components of configuration <NUM>, encoding processor <NUM>, transmission component <NUM>, wireless device <NUM>, wireless device <NUM>, or a UE <NUM> as described above, e.g., with reference to <FIG>, <FIG> and <FIG>. Device <NUM> may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including UE transmission processor <NUM>, processor <NUM>, memory <NUM>, software <NUM>, transceiver <NUM>, antenna <NUM>, and I/O controller <NUM>. These components may be in electronic communication via one or more busses (e.g., bus <NUM>). Device <NUM> may communicate wirelessly with one or more base stations <NUM> (e.g., base station <NUM>-a). The UE transmission processor <NUM> may be an example of aspects of a UE transmission processor <NUM>, a transmission processor <NUM>, a transmission processor <NUM>, or a transmission processor <NUM> as described with reference to <FIG> and <FIG>.

Processor <NUM> may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor <NUM> may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor <NUM>. Processor <NUM> may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting coding to improve transmission and reception processing time).

Software <NUM> may include code to implement aspects of the present disclosure, including code to improve transmission and reception processing time. Software <NUM> may be stored in a non-transitory computer-readable medium such as system memory or other memory. In some cases, the software <NUM> may not be directly executable by the processor but may cause a computer (e.g., when compiled and executed) to perform functions described herein.

<FIG> shows a diagram of a system <NUM> including a device <NUM> that supports coding to improve transmission and reception processing time in accordance with one or more aspects of the present disclosure. Device <NUM> may be an example of or include the components of configuration <NUM>, encoding processor <NUM>, transmission component <NUM>, wireless device <NUM>, wireless device <NUM>, or a base station <NUM> as described above, e.g., with reference to <FIG>, <FIG> and <FIG>. Device <NUM> may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including base station transmission processor <NUM>, processor <NUM>, memory <NUM>, software <NUM>, transceiver <NUM>, antenna <NUM>, network communications manager <NUM>, and base station communications manager <NUM>. These components may be in electronic communication via one or more busses (e.g., bus <NUM>). Device <NUM> may communicate wirelessly with one or more UEs <NUM> (e.g., UEs <NUM>-a and <NUM>-b). The base station transmission processor <NUM> may be an example of aspects of a base station transmission processor <NUM>, a transmission processor <NUM>, a transmission processor <NUM>, or a transmission processor <NUM> as described with reference to <FIG> and <FIG>.

Network communications manager <NUM> may manage communications with core network <NUM>-a (e.g., via one or more wired backhaul links).

Base station communications manager <NUM> may manage communications with other base stations <NUM> (e.g., base stations <NUM>-b and <NUM>-c), and may include a controller or scheduler for controlling communications with UEs <NUM> in cooperation with other base stations <NUM>. For example, the base station communications manager <NUM> may coordinate scheduling for transmissions to UEs <NUM> for various interference mitigation techniques such as beamforming or joint transmission. In some examples, base station communications manager <NUM> may provide an X2 interface within an LTE/LTE-A wireless communication network technology to provide communication between base stations <NUM>.

<FIG> shows a flowchart illustrating a method <NUM> for coding to improve transmission and reception processing time in accordance with one or more aspects of the present disclosure. The operations of method <NUM> may be implemented by a UE <NUM> or base station <NUM> or its components as described herein. For example, the operations of method <NUM> may be performed by a transmission processor as described with reference to <FIG>. In some examples, a UE <NUM> or base station <NUM> may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the UE <NUM> or base station <NUM> may perform aspects of the functions described below using special-purpose hardware.

At block <NUM> the UE <NUM> or base station <NUM> may receive, at an encoder of the transmitting device, a plurality of sets of input bits associated with a single input vector to be encoded into a single codeword. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>. In certain examples, aspects of the operations of block <NUM> may be performed by an encoder reception component as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may process, by the encoder, the plurality of sets of input bits, including a first set of input bits and a second set of input bits, to generate a plurality of sets of output bits, each set of output bits associated with one of a plurality of transmission symbol periods. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>. In certain examples, aspects of the operations of block <NUM> may be performed by an encoder as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may output, from the encoder, a first set of output bits of the plurality of sets of output bits associated with a first transmission symbol period of the plurality of transmission symbol periods prior to receiving all input bits of the second set of input bits of the plurality of sets of input bits, the second set of input bits being received at the encoder subsequent to the first set of input bits. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>. In certain examples, aspects of the operations of block <NUM> may be performed by an encoder output component as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may performing interleaving of each of the plurality of sets of output bits independently of each other of the plurality of sets of output bits. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>. In certain examples, aspects of the operations of block <NUM> may be performed by an interleaver as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may perform rate matching on the first set of output bits to match a number of bits of the first set of output bits to a set of resources in the first transmission symbol period. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>. In certain examples, aspects of the operations of block <NUM> may be performed by a rate matcher as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may transmit, from the transmitting device, the first set of output bits in the first transmission symbol period before a last input bit of the plurality of sets of input bits is received at the encoder of the transmitting device. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>. In certain examples, aspects of the operations of block <NUM> may be performed by a transmission component as described with reference to <FIG>.

At block <NUM> the UE <NUM> or base station <NUM> may pause the processing after outputting the first set of output bits to wait for the second set of input bits to be received at the encoder. The operations of block <NUM> may be performed according to the methods described with reference to <FIG>. In certain examples, aspects of the operations of block <NUM> may be performed by an encoder output component as described with reference to <FIG>.

It should be noted that the methods described above describe possible implementations, and that the operations and the operations may be rearranged or otherwise modified and that other implementations are possible.

Techniques described herein may be used for various wireless communications systems such as CDMA, TDMA, FDMA, OFDMA, single carrier frequency division multiple access (SC-FDMA), and other systems. The terms "system" and "network" are often used interchangeably.

An OFDMA system may implement a radio technology such as Ultra Mobile Broadband (UMB), Evolved UTRA (E-UTRA), Institute of Electrical and Electronics Engineers (IEEE) <NUM> (Wi-Fi), IEEE <NUM> (WiMAX), IEEE <NUM>, Flash-OFDM, etc. UTRA and E-UTRA are part of Universal Mobile Telecommunications system (UMTS). 3GPP LTE and LTE-A are new releases of UMTS that use E-UTRA. UTRA, E-UTRA, UMTS, LTE, LTE-A, and GSM are described in documents from the organization named "3rd Generation Partnership Project" (3GPP). While aspects an LTE system may be described for purposes of example, and LTE terminology may be used in much of the description, the techniques described herein are applicable beyond LTE applications.

In LTE/LTE-A networks, including such networks described herein, the term eNB may be generally used to describe the base stations. The wireless communications system or systems described herein may include a heterogeneous LTE/LTE-A network in which different types of eNBs provide coverage for various geographical regions. For example, each eNB or base station may provide communication coverage for a macro cell, a small cell, or other types of cell. The term "cell" may be used to describe a base station, a carrier or component carrier associated with a base station, or a coverage area (e.g., sector, etc.) of a carrier or base station, depending on context.

Base stations may include or may be referred to by those skilled in the art as a base transceiver station, a radio base station, an access point, a radio transceiver, a NodeB, eNodeB, Home NodeB, a Home eNodeB, or some other suitable terminology. The geographic coverage area for a base station may be divided into sectors making up only a portion of the coverage area. The wireless communications system or systems described herein may include base stations of different types (e.g., macro or small cell base stations). The UEs described herein may be able to communicate with various types of base stations and network equipment including macro eNBs, small cell eNBs, relay base stations, and the like. There may be overlapping geographic coverage areas for different technologies.

A UE may be able to communicate with various types of base stations and network equipment including macro eNBs, small cell eNBs, relay base stations, and the like.

Each communication link described herein-including, for example, wireless communications system <NUM> and configuration <NUM> of <FIG> and <FIG>-may include one or more carriers, where each carrier may be a signal made up of multiple sub-carriers (e.g., waveform signals of different frequencies).

For example, an exemplary operation that is described as "based on condition A" may be based on both a condition A and a condition B without departing from the scope of the present disclosure.

By way of example, and not limitation, non-transitory computer-readable media may comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

Claim 1:
A method (<NUM>) of wireless communication at a transmitting device, the method comprising:
receiving (<NUM>), at an encoder of the transmitting device, a plurality of sets of input bits associated with a single input vector to be encoded into a single codeword, the plurality of sets of input bits including a first set of input bits and a second set of input bits;
receiving information regarding the amount of resources available at least in a first symbol period of a plurality of symbol periods and in a second symbol period of the plurality of symbol periods;
processing (<NUM>), by the encoder via a shift register, by applying one of a convolutional code or a tail-biting convolutional code, the plurality of sets of input bits to generate a plurality of sets of output bits, each set of output bits associated with one of the plurality of symbol periods comprising the first symbol period and the second symbol period;
outputting (<NUM>), from the encoder via the shift register, a first set of output bits of the plurality of sets of output bits associated with the first set of input bits and the first symbol period prior to receiving all input bits of the second set of input bits corresponding to the second symbol period, the second set of input bits being received at the encoder subsequent to the first set of input bits, the second set of input bits for generating a second set of output bits associated with the first and second sets of input bits and the second symbol period; and
performing rate matching, utilizing said received information, on the first set of output bits to match the number of bits of the first set of output bits to the set of resources in the first symbol period before receiving all the input bits associated with the single input vector at the encoder.