Patent Description:
Currently, applications utilizing narrow-band radios for range estimations are gaining traction. By exchanging information about the radio channel between the over multiple channels, e.g., channel state information, the narrow-band radios can build up a virtual-wideband ranging system. The concatenation of narrow-band channels to virtual-wideband makes it possible for relatively simple half-duplex low power radios to achieve a very high ranging accuracy.

For example, <NPL>; discloses narrow-band ranging in BLE environment. The document especially shows that simple half-duplex Bluetooth low power radios operating in the Industrial, Scientific and Medical (ISM) radio bands can achieve ranging accuracies of <NUM> or better. However, due to multipath in non-line of sight channels, ambiguity in the virtual-wideband channel phase state information occurs when channels are concatenated.

In order to remove ambiguity on the channel phase state information, it is desirable to have phase coherent measurements over multiple channels as this vastly reduces the number of unknown parameters, which are needed to be estimated. Phase-coherency of the ranging procedure entails that both radios, especially both digital phase-locked loops (PLLs) respecting the radios, stay phase-coherent throughout the channel switching of the whole ranging procedure. The phase-coherency referred herein is not limited to maintaining the same phase of the PLL when switching back and forth through different frequencies. The invention is moreover targeting to achieve a predictable phase relationship over one or multiple frequency changes of the PLL, which does not necessarily require that the phase is the same when switching to a different frequency and back.

Publication <CIT> discloses an apparatus and a method according to the preamble of claims <NUM> and <NUM>, respectively.

Accordingly, an object of the invention is to provide an all-digital phase locked loop (ADPLL) and a method for coherent multi-carrier phase based ranging, which can achieve a predictable phase relationship over one or multiple frequency changes of the ADPLL.

The object is solved by the features of the first independent claim for the ADPLL and by the features of the second independent claim for the method. The dependent claims contain further developments.

According to a first aspect of the invention, an all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. Additionally, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. Furthermore, the ADPLL comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a control means adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

In this context, the ADPLL preferably further comprises a loop filter adapted to generate control signals towards the control means based on the phase error signal. Preferably, the output oscillation frequency is generated by a digitally controlled oscillator (DCO) within the ADPLL, where the DCO output is fed back to the phase comparator, thereby generating the phase error signal with respect to the phase trajectory translated from the FCW.

Therefore, the proposed solution allows for coherent phase based ranging in ranging applications by providing a predictable phase trajectory that is followed by the ADPLL. The pattern generator generates the FCW based on it's settings and the system clock. Preferably, the system clock is predictable and stable, and hence the FCW pattern can be programmed accurately. The output of the pattern generator, i.e., the pattern of the FCW can be, for instance, a staircase, a stepped pyramid, a linear frequency sweep, a frequency hopping pattern, etc. The FCW is then unambiguously translated into the phase trajectory, for instance, by an FM to PM translation.

In addition, the loop filter is further adapted to receive a modulating signal through a direct path, whereby the modulating signal is either generated by the pattern generator or calculated from the phase trajectory. Hence, the proposed ADPLL facilitates a two-point modulation scheme that takes advantage of the wideband frequency modulation capability by adjusting its digital FCW. The implemented modulation scheme is a digital two-point scheme with one modulating point, e.g., at the input of the phase accumulator, compensating for the developed excess phase error while the other modulating point, e.g., at the output of the loop filter, directly modulating the DCO frequency deviation.

According to a first preferred implementation form of said first aspect of the invention, the control means comprises a Process-Voltage-Temperature (PVT) capacitor bank, an Acquisition (ACQ) capacitor bank and a Tracking (TRK) capacitor bank. In this context, the control means is adapted to exchange capacitance between the PVT capacitor bank and the ACQ capacitor bank, and between the ACQ capacitor bank and the TRK capacitor bank in order to increase their effective range. The control means comprises the DCO control banks, i.e., a large PVT capacitor bank, a medium-sized ACQ capacitor bank and a fine TRK capacitor bank. By exchanging capacitance between the large PVT capacitor bank, the medium-sized ACQ capacitor bank and the fine TRK capacitor bank, i.e., by exchanging control codes over the DCO control banks, a phase lock for the ADPLL is maintained over the entire ISM band sweep without a relock. This advantageously increases the useful range without adding additional hardware in the DCO.

According to a second preferred implementation form of said first aspect of the invention, the phase trajectory translated from the FCW is predictable in both timing and amplitude over a number of channels to be measured. Advantageously, a more accurate narrow-band ranging can be achieved.

According to a further preferred implementation form of said first aspect of the invention, the phase accumulator is further adapted to receive a relock command in order to relock the ADPLL to the phase trajectory when switching over the number of channels to be measured. Advantageously, the ADPLL can be forced to lock to the desired programmed phase trajectory over multiple separate locks of the ADPLL. Hence, after changing the FCW for changing the channel, the relock command forces the ADPLL to relock to the phase trajectory.

According to a further preferred implementation form of said first aspect of the invention, the control means further comprises a modulation bank respecting the frequency span of the number of channels to be measured. Therefore, in addition to the existing DCO control banks or as an alternative, a dedicated DCO control bank can be utilized that spans all relevant RF channels in order to force the ADPLL to follow the programmed phase trajectory.

According to a further preferred implementation form of said first aspect of the invention, the phase accumulator further comprises a first phase accumulator and a second phase accumulator respectively operable on a transmit mode and a receive mode or vice versa. Advantageously, the proposed solution is applicable even for radio architectures where the frequency of the ADPLL is different between receive mode and transmit mode, e.g., low-IF and sliding-IF receivers.

According to a further preferred implementation form of said first aspect of the invention, the phase accumulator further comprises a compensation unit adapted to calculate a respective phase trajectory for a transmit mode and/or a receive mode. Therefore, it is further possible to implement the proposed solution for different ADPLL frequency between receive mode and transmit mode by having a phase accumulator dedicated to one mode (transmit/receive) and by calculating the phase trajectory for the other mode (receive/transmit).

According to a second aspect of the invention, a wireless communication system is provided. The system comprises a first radio node and a second radio node, where each node comprises an ADPLL according to the first aspect of the invention. In this context, the first radio node is operable on a transmit mode and the second radio node is operable on a receive mode or vice versa. In addition, the first radio node and the second radio node are adapted to switch between the transmit mode and the receive mode through a number of channels to be measured in order to measure a phase at each channel. Since both ADPLLs follow the predictable phase trajectory, both ADPLLs stay phase-coherent throughout the channel switching for the whole ranging procedure.

According to a third aspect of the invention, a method is provided for maintaining phase lock of an all-digital phase locked loop (ADPLL) along a predictable phase trajectory. The method comprises the step of generating a frequency control word (FCW) by a pattern generator based on a predefined setting and a system clock. The method additionally comprises the step of translating the FCW into a phase trajectory by a phase accumulator. Furthermore, the method comprises the step of generating a phase error signal by a phase comparator representing a difference between the phase trajectory and the phase of an output oscillation frequency.

Moreover, the method comprises the step of controlling a phase of the output oscillation frequency by a control means with respect to the phase trajectory. In this context, the method further preferably comprises the step of generating control signals by a loop filter towards the control means based on the phase error signal. In addition, the method further comprises the step of receiving a modulating signal by the loop filter through a direct path, whereby the modulating signal is either generated by the pattern generator or calculated from the phase trajectory. Hence, the proposed solution allows for coherent phase based ranging in ranging applications by providing a predictable phase trajectory that is followed by the ADPLL.

According to a first preferred implementation form of said third aspect of the invention, the control means comprises a Process-Voltage-Temperature (PVT) capacitor bank, an Acquisition (ACQ) capacitor bank and a Tracking (TRK) capacitor bank. In this regard, the method further comprises the step of exchanging capacitance between the PVT capacitor bank and the ACQ capacitor bank, and between the ACQ capacitor bank and the TRK capacitor bank by the control means, thereby increasing their effective range. Advantageously, the useful range for ranging measurement is significantly increased without adding additional hardware in the DCO.

According to a second preferred implementation form of said third aspect of the invention, the method further comprises the step of setting the phase comparator output to zero while exchanging capacitance in order to maintain a phase lock during the capacitance exchange. Therefore, the capacitance exchange is performed in a continuously on mode for the ADPLL. The ADPLL is put on hold by fixing the phase comparator output to zero for clock cycles where the capacitance exchange is performed, which further eliminates any analog switching spikes in the DCO.

According to a further preferred implementation form of said third aspect of the invention, the method further comprises the step of translating the phase trajectory from the FCW in a predictable manner in both timing and amplitude over a number of channels to be measured. Hence, a faster and more accurate narrow-band ranging can be achieved.

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the following embodiments of the present invention may be variously modified and the range of the present invention is not limited by the following embodiments.

In <FIG>, a first exemplary embodiment of the ADPLL <NUM> according to the first aspect of the invention is illustrated. The inputs to the ADPLL <NUM> comprise a system clock <NUM> and a predefined setting <NUM> for the FCW to be generated. The output of the ADPLL <NUM> is an RF oscillation frequency <NUM>, which is generated from a digitally controlled oscillator (DCO) <NUM> within the ADPLL <NUM>. The system clock <NUM> is a high precision clock, preferably generated from an external oscillator, for instance, a crystal-based oscillator, a microelectromechanical (MEMS) based oscillator and the like.

The ADPLL <NUM> comprises a pattern generator <NUM> that generates the FCW <NUM> based on the predefined setting <NUM> and the system clock <NUM>. Since the system clock <NUM> is a high precision clock, it is therefore predictable and stable. Consequently, the generated pattern for the FCW <NUM> can be programmed accurately. The pattern for the FCW <NUM> can be a staircase, a stepped pyramid, a linear frequency sweep, a frequency-hopping pattern, and so on. A phase accumulator <NUM> translates the FCW <NUM> into a phase trajectory <NUM> by means of FM to PM translation, i.e., by calculating the phase position of a point in time on the waveform cycle. As such, the phase trajectory <NUM> is also predictable in nature.

A phase comparator <NUM> within the ADPLL <NUM> then performs a comparison between the phase trajectory <NUM> and the output oscillation frequency <NUM>, thereby generating a phase error signal <NUM> when they differ from each other. Generally, the phase comparator <NUM> performs digital to time conversion, time to digital conversion and phase quantization in order to generate the phase error signal <NUM>, where the system clock <NUM> is taken as the reference for performing digital to time conversion. Such conversions and quantization techniques are known in the art, and hence they are not described here in detail in order to avoid unnecessarily obscuring the invention.

A loop filter <NUM> is adapted to perform digital filtration of the phase error signal <NUM>, representing an offset to the nominal FCW <NUM>. Normally the offset is centralized at zero and is extended to positive and negative extremes resulting the required overflow and/or underflow, which are translated as control signals for controlling the DCO <NUM> frequency. The ADPLL <NUM> further comprises a control means <NUM> that utilizes the control signals from the loop filter <NUM> in order to address the required overflow and/or underflow. The control means <NUM> comprises a large PVT capacitor bank <NUM>, a medium-sized ACQ capacitor bank <NUM> and a fine TRK capacitor bank <NUM>.

In order to overcome bandwidth restricted phase/frequency modulation of the ADPLL <NUM>, the solution further proposes a two-point modulation scheme. Preferably, at a first modulation point, a modulating data pattern or a modulating frequency or a modulating signal <NUM> from the pattern generator <NUM> is added via an adder <NUM> with the FCWbase in order to generate the FCW <NUM>.

For example, the pattern generator <NUM> may generate the FCW <NUM> by modulating a channel FCW with a data FCW, where both FCW settings are predefined. The modulating signal <NUM> is further fed to the loop filter <NUM> through a direct path, where at a second modulation point, e.g., at the output of the loop filter <NUM>, the modulating signal <NUM> is further utilized to modulate the loop filter <NUM> output. As such, the two-point modulation allows for a direct modulation of the DCO <NUM> while at the same time compensates the frequency reference and prevents the modulating data from affecting the phase error.

In a traditional digital PLL architecture, the PLL cannot go beyond the range of the TRK bank <NUM>, i.e., only the TRK bank <NUM> can be changed when the PLL is locked and the PVT bank <NUM> and the ACQ bank <NUM> remain static. In order to extend the effective range of the proposed ADPLL <NUM>, the control means <NUM> is adapted to exchange capacitance between the PVT bank <NUM> and the ACQ bank <NUM> as well as between the ACQ bank <NUM> and the TRK bank <NUM>. In other words, the control codes for the DCO control banks <NUM>,<NUM>,<NUM> are exchangeable. For instance, the required overflow and/or underflow can be addressed effectively by exchanging capacitance from the TRK bank <NUM> to the ACQ bank <NUM>, and further from the ACQ bank <NUM> to the PVT bank <NUM>. Hence, a sticky-lock mechanism is facilitated for maintaining a sticky-lock overflow and/or underflow between the DCO control banks <NUM>,<NUM>,<NUM>.

The sticky-lock mechanism is performed especially to carter for the programmed pattern that is likely to have a frequency span, which is multiples of the TRK bank <NUM> range. Moreover, the mechanism is performed in such a way that the ADPLL <NUM> maintains phase lock during capacitance exchange. Preferably, during the switchover, the ADPLL <NUM> is put on hold for the clock cycles used to switch to take care of any analog switching spikes in the DCO <NUM>. The ADPLL <NUM> is put on hold by fixing the phase comparator <NUM> output, especially the time to digital conversion output to zero for the clock cycles responsible for the capacitance exchange.

As a result, the ADPLL can be locked over a larger band of sweep, for instance, over the entire ISM band sweep without a relock. This vastly increases the useful range without adding additional hardware in the DCO <NUM>. Additionally or alternatively, the DCO <NUM> can be supported by a dedicated DCO control bank, for instance, a modulation bank that corresponds to the frequency span of all relevant RF channels. Although the implementation of the dedicated DCO bank allows for comprehensive control of the DCO <NUM> frequency, it also arises the necessity for additional hardware implementation in the DCO <NUM>. It is further possible to externally initiate a relock command to the ADPLL <NUM>, for instance, to the loop filter <NUM>, in order to force the ADPLL <NUM> to relock to the phase trajectory <NUM> after changing the FCW <NUM> for changing the channel.

In <FIG>, a second exemplary embodiment of the ADPLL <NUM> according to the first aspect of the invention is illustrated. The ADPLL <NUM> differs from the ADPLL <NUM> of <FIG> in that the ADPLL <NUM> indirectly generates the modulating signal <NUM> in order to facilitate the two-point modulation scheme. In this context, the ADPLL <NUM> comprises a differentiator <NUM> coupled to the output path of the phase accumulator <NUM>. The differentiator <NUM> performs a reverse operation of the phase accumulator <NUM>, thereby reconstructing the FCW <NUM> from the phase trajectory <NUM>. The predefined setting FCWbase <NUM> at the first modulation point, e.g., at the input of the phase accumulator <NUM> (not explicitly shown), is also fed to the differentiator <NUM>. Hence, the differentiator <NUM> is able to reconstruct the modulating signal <NUM> by subtracting FCWbase <NUM> from the reconstructed FCW <NUM> in order to modulate the DCO <NUM> directly by modulating the output of the loop filter <NUM> at the second modulation point. Such a modulation scheme considerably speeds up the adaptation of the ADPLL to the desired phase trajectory as well as significantly increases the speed with which the channel switching is performed.

Along <FIG>, traditional output frequency control in a digital PLL are illustrated. In particular, <FIG> shows a traditional capacitance allocation scheme with an increased target frequency. The numbers in boxes right to the designated DCO control banks corresponds to the total number of capacitors available at each bank. The further numbers to the right represents the number of capacitors utilized at each time instant for the respective DCO banks. The output frequency is determined by the total amount of used capacitance. This total capacitance can be constructed from the total amount of available capacitance. Traditional digital PLLs, one in lock, only use the TRK bank capacitances to track the target frequency.

For instance, the PVT bank comprises <NUM> capacitors, the ACQ bank comprises <NUM> capacitors and the TRK bank comprises <NUM> capacitors. Upon initiating the tracking of the target sweep, consider that the PVT bank uses <NUM> capacitor of its <NUM> capacitors, the ACQ bank uses <NUM> capacitors of its <NUM> capacitors and the TRK bank uses <NUM> capacitors of its <NUM> capacitors. Since the traditional PLL can only change the TRK bank capacitance usage while being locked, with an increasing target frequency sweep would cause an error when the TRK bank reaches to its maximum range. Hence, the PLL will not maintain its locked state for the entire sweep and is required to be relocked upon reaching the maximum range of the TRK bank.

Similarly, in <FIG>, the traditional capacitance allocation scheme is illustrated for a decreasing target frequency. Upon initiating the tracking, consider that the PVT bank uses <NUM> capacitors of its <NUM> capacitors, the ACQ bank uses <NUM> capacitors of its <NUM> capacitors and the TRK bank uses <NUM> capacitors of its <NUM> capacitors. However, when the variation of the decreasing target sweep is large, it causes an error even the TRK bank capacitance is decreased to zero. Hence, a traditional digital PLL that cannot go beyond the range of the TRK bank would fail to address the variation of the target frequency if it is too large.

Along <FIG>, the proposed capacitance allocation scheme for the ADPLL <NUM> are illustrated. Particularly, <FIG> shows the proposed capacitance allocation scheme for an increased target frequency. In an analogous manner illustrated in <FIG>, the numbers in boxes right to the designated DCO control banks corresponds to the total number of capacitors available at each bank. The further numbers to the right represents the number of capacitors utilized at each time instant for the respective DCO banks. As such, the PVT bank <NUM> comprises <NUM> large-sized capacitors, the ACQ bank <NUM> comprises <NUM> medium-sized capacitors and the TRK bank <NUM> comprises <NUM> fine capacitors.

It is further considered that one PVT bank <NUM> capacitor value approximately corresponds to the cumulative value for <NUM> ACQ bank <NUM> capacitors and one ACQ bank <NUM> capacitor value approximately corresponds to the cumulative value for <NUM> TRK bank <NUM> capacitors.

Upon initiating the tracking of the target sweep, consider that the PVT bank <NUM> uses <NUM> capacitor of its <NUM> capacitors, the ACQ bank <NUM> uses <NUM> capacitors of its <NUM> capacitors and the TRK bank <NUM> uses <NUM> capacitors of its <NUM> capacitors. While tracking the increased target frequency, the amount of available capacitors in the TRK bank <NUM> is increased until reaching a specified limit, herein illustrated as <NUM> in terms of total number of used capacitors. Upon reaching the specified limit for the TRK bank <NUM>, one capacitor of the ACQ bank <NUM> is added leading to <NUM> ACQ bank <NUM> capacitors in use, while the same amount of capacitance is subtracted, i.e., <NUM> TRK bank <NUM> capacitors, from the used TRK bank <NUM> capacitors to arrive at the same total capacitance.

Further into target tracking, not only the TRK bank <NUM> is set to a specified limit but also the ACQ bank <NUM>, e.g., <NUM> in terms of total number of used capacitors. In case the ACQ bank <NUM> reaches its limit as well as the TRK bank <NUM> (<NUM> and <NUM> respectively), one capacitor of the PVT bank <NUM> is added leading to <NUM> PVT bank <NUM> capacitors in use, while the same amount of capacitance is subtracted from the used ACQ bank <NUM> and the TRK bank <NUM> capacitors to arrive at the same total capacitance. Hence, the useful range of the target tracking is effectively increased. Therefore, the proposed invention uses all capacitor banks, i.e., PVT bank <NUM>, ACQ bank <NUM> and the TRK bank <NUM>, to compose the target capacitance value in order to address the variation in the target frequency, even if it is too large.

Similarly, <FIG> shows the proposed capacitance allocation scheme for a decreasing target frequency. Upon initiating the tracking, consider that the PVT bank <NUM> uses <NUM> capacitors of its <NUM> capacitors, the ACQ bank <NUM> uses <NUM> capacitors of its <NUM> capacitors and the TRK bank <NUM> uses <NUM> capacitors of its <NUM> capacitors. While tracking the decreased target frequency, the amount of available capacitors in the TRK bank <NUM> is correspondingly decreased until reaching a specified limit, herein illustrated as <NUM> in terms of total number of used capacitors.

Upon reaching the specified limit for the TRK bank <NUM>, one capacitor of the ACQ bank <NUM> is subtracted leading to <NUM> ACQ bank <NUM> capacitor in use, while the same amount of capacitance is added to the TRK bank <NUM> to arrive at the same total capacitance. Further into target tracking, not only the TRK bank <NUM> is set to a specified limit but also the ACQ bank <NUM>, e.g., <NUM> in terms of total number of used capacitors. In case the ACQ bank <NUM> reaches its limit as well as the TRK bank <NUM> (<NUM> and <NUM> respectively), one capacitor of the PVT bank <NUM> is subtracted leading to <NUM> PVT bank <NUM> capacitors in use, while the same amount of capacitance is added to the ACQ bank <NUM> and the TRK bank <NUM> respectively to arrive at the same total capacitance.

In <FIG>, a second exemplary embodiment of the ADPLL <NUM> according to the first aspect of the invention is illustrated. The ADPLL <NUM> is adapted to implement a predictable phase trajectory especially in the case where the frequency of the ADPLL <NUM> is different between receive mode RX and transmit mode TX. In this context, the FCW <NUM> to phase trajectory <NUM> translation scheme comprises a first phase accumulator <NUM>, hereinafter referred to as TX phase accumulator <NUM>, and a second phase accumulator <NUM>, hereinafter referred to as RX phase accumulator <NUM>. The TX phase accumulator <NUM> translates the FCW <NUM> into a TX phase trajectory <NUM> by means of FM to PM translation.

On the other hand, the FCW <NUM> is further multiplied with a specific modulation index or fRX/fTX ratio <NUM> at a multiplier <NUM>, and then is translated into a RX phase trajectory <NUM> by the RX phase accumulator <NUM> through FM to PM translation. The TX phase trajectory <NUM> and the RX phase trajectory <NUM> are switchable and are controlled through a switching means <NUM>, which is operated externally via a RX/TX control <NUM> based on the mode of operation. In any case, the TX phase trajectory <NUM> corresponds to the predictable phase trajectory <NUM> when the ADPLL <NUM> is operating on transmit mode. Analogously, the RX phase trajectory <NUM> corresponds to the predictable phase trajectory <NUM> when the ADPLL <NUM> is operating on receive mode.

In order to facilitate the two-point modulation scheme, the ADPLL <NUM> also generates the modulating signal <NUM> indirectly in the manner described for ADPLL <NUM>. Further to address the frequency difference between the receive mode RX and transmit mode TX, FCWbase <NUM>, fRX/fTX <NUM> and RX/TX control <NUM> signals are additionally fed to the differentiator <NUM>. By means of the control signals <NUM>, <NUM> and the FCWbase <NUM>, the differentiator <NUM> is able to calculate the modulating signal <NUM> from the reconstructed FCW <NUM>, thereby performing the modulation of the DCO <NUM> by modulating the output of the loop filter <NUM> at the second modulation point. Such a technique of subtracting a constant value after the differentiation function results in a simplified yet advantageous scheme to indirectly generate the modulating signal <NUM> in order to facilitate the two-point modulation scheme.

In <FIG>, a third exemplary embodiment of the ADPLL <NUM> according to the first aspect of the invention is illustrated. The ADPLL <NUM> differs from the ADPLL <NUM> of <FIG> in that the ADPLL <NUM> is adapted to generate a predictable phase trajectory for different TX and Rx frequency by means of a single phase accumulator. In this context, the FCW <NUM> to phase trajectory <NUM> translation scheme comprises a phase accumulator <NUM>, which can be the same phase accumulator <NUM> illustrated in <FIG> for the ADPLL <NUM>. The phase accumulator <NUM> translates the FCW <NUM> into a phase trajectory <NUM>, e.g., TX phase trajectory, specific to the frequency defined for the transmit mode.

In order to generate the phase trajectory specific to the frequency defined for the receive mode, the phase accumulator <NUM> is associated with a compensation unit <NUM>, which performs wrap compensation on the phase accumulator <NUM>. The compensated output and the phase accumulator <NUM> output, i.e., TX phase trajectory <NUM>, are added through an adder <NUM> and the result is then multiplied with the specific modulation index or fRX/fTX ratio <NUM> at a multiplier <NUM>, thereby outputting the RX phase trajectory <NUM>. The sequence of the addition, i.e., the adder <NUM>, and the multiplication, i.e., the multiplier <NUM>, can be swapped.

The TX phase trajectory <NUM> and the RX phase trajectory <NUM> are switchable and are controlled through a switching means <NUM>, which is operated externally via the RX/TX control <NUM> based on the mode of operation. In any case, the TX phase trajectory <NUM> corresponds to the predictable phase trajectory <NUM> when the ADPLL <NUM> is operating on transmit mode. Analogously, the RX phase trajectory <NUM> corresponds to the predictable phase trajectory <NUM> when the ADPLL <NUM> is operating on receive mode.

Therefore, when switching from receive mode to transmit mode and vice versa, the hypothetical phase trajectory of the ADPLL <NUM> resp. the ADPLL <NUM> if it would remain in receive or transmit mode should be stored. In this manner, the ADPLL <NUM> resp. the ADPLL <NUM> can lock to that trajectory when the it is required to be switched back from transmit mode to receive mode or vice versa. This can be stored in the second phase accumulator in the case of ADPLL <NUM> or can be calculated from a single phase accumulator in the case of ADPLL <NUM>. As such, the proposed invention facilitates generation and implementation of a predictable phase trajectory even when the TX and RX frequency are not identical.

In <FIG>, an exemplary embodiment of the system <NUM> according to the second aspect of the invention is illustrated. The system <NUM> comprises a first radio node <NUM> and a second radio node <NUM>, preferably communicating with each other wirelessly in a half-duplex manner. The first radio node <NUM> comprises a transceiver <NUM> followed by an ADPLL <NUM>, with the reference generated from a high precision system clock <NUM>. Similarly, the second radio node <NUM> comprises a transceiver <NUM> followed by an ADPLL <NUM>, with the reference generated from a high precision system clock <NUM>.

Each node <NUM>,<NUM> is operable on a transmit mode and/or a receive mode, where the mode of operation for each node <NUM>,<NUM> is switchable over the number of channels to be measured. The ADPLLs <NUM>,<NUM> are preferably the ADPLL <NUM> or ADPLL <NUM> as illustrated in <FIG> and <FIG> respectively, especially in the case where the frequency of the ADPLLs <NUM>,<NUM> are identical for transmit mode and for receive mode. Additionally or alternately, the ADPLLs <NUM>,<NUM> can be any of the ADPLL <NUM> or ADPLL <NUM> respectively illustrated in <FIG> and <FIG>, especially in the case where the frequency of the ADPLLs <NUM>,<NUM> are different for transmit mode and for receive mode.

During a ranging procedure, the first radio node <NUM> operates as an initiator and the second radio node <NUM> operates as a reflector or vice versa. The respective ADPLLs <NUM>,<NUM> generate a radio frequency each from their own reference frequency. While in receiving mode, the radio frequency is used by the nodes <NUM>,<NUM> to receive an RF signal. Analogously, while in transmit mode, the radio frequency is used by the nodes <NUM>,<NUM> to transmit an RF signal.

In a traditional ranging procedure, especially when switching between channels, there is a random phase relation between the PLL output signals for each channel. Hence, there is no phase-coherency when switching between channels.

As a result, both measuring nodes step through multiple channels to measure the phase at each channel. In each channel, first one node acts as a transmitter and the other node acts as a receiver while a phase measurement is performed. After that, the roles are swapped and a second phase measurement is performed. Thus, for ranging over N number of channels, at least N number of TX/RX switches are necessary.

By implementing a predictable phase trajectory for both transmit mode and receive mode, the unpredictability for switching is significantly minimized. Moreover, the phase trajectory is predictable in both timing and in amplitude over the number of channels to be measured. This effectively reduces the time requires to perform the whole ranging measurement, thereby reducing the overall energy consumption and further increases the update rate. Since, the ADPLLs <NUM>,<NUM> are forced to follow a predictable phase trajectory, phase based ranging can be achieved to be phase coherent over all channels of the ranging procedure. Therefore, the proposed invention reduces the number of TX/RX switches in extremes to only one instead of equal to the number of channels N.

In <FIG>, an exemplary embodiment of the method according to the third aspect of the invention is illustrated. In a first step S1, a frequency control word is generated by a pattern generator based on a predefined setting and a system clock. In a second step S2, the frequency control word is translated into a phase trajectory by a phase accumulator. In a third step S3, a phase error signal is generated by a phase comparator representing a difference between the phase trajectory and the phase of an output oscillation frequency. Finally, in a fourth step S4, a phase of the output oscillation frequency is controlled with respect to the phase trajectory by a control means.

As mentioned earlier, the concatenation of narrow-band channels to virtual-wideband makes it possible for relatively simple half-duplex low power radios to achieve a very high ranging accuracy. There are two reasons why it is advantageous to be phase coherent over all channels of the ranging procedure. Firstly, due to multipath in non-line of sight channels, ambiguity in the virtual-wideband channel phase state information occurs when channels are concatenated. Secondly, the time it takes to do the ranging measurement must be as short as possible to reduce energy consumption and/or increase update rate. The proposed solution warrants that the phase trajectory <NUM> that the ADPLL <NUM> follows is predictable in both timing and amplitude. Furthermore, the ADPLL <NUM> is forced to follow this phase trajectory <NUM> in a continuously on mode by a dedicated DCO control bank, or by exchanging control codes over existing DCO control banks <NUM>,<NUM>,<NUM>, or by forcing the ADPLL <NUM> to lock to the desired phase trajectory <NUM> over multiple separate locks of the ADPLL <NUM>.

Claim 1:
An all-digital phase locked loop (<NUM>) comprising:
a phase accumulator (<NUM>) adapted to translate a frequency control word (<NUM>) into a phase trajectory (<NUM>),
a phase comparator (<NUM>) adapted to generate a phase error signal (<NUM>) representing a difference between the phase trajectory (<NUM>) and the phase of an output oscillation frequency (<NUM>), and
a control means (<NUM>) adapted to control a phase of the output oscillation frequency (<NUM>) based on said phase error signal (<NUM>);
characterised in that it further comprises:
a pattern generator (<NUM>) adapted to generate the frequency control word (<NUM>) based on a predefined setting (<NUM>) and a system clock (<NUM>),
wherein the pattern generator (<NUM>) is adapted to program a pattern for the frequency control word (<NUM>) based on the system clock (<NUM>) and the predefined setting (<NUM>) for the frequency control word (<NUM>) to be generated.