Patent Description:
Computer processors, microprocessors, central processing units (CPUs), and any other type of processing circuits ("processors") execute computer software and firmware instructions that modify data. The instructions themselves, the data to be modified, and the resulting modified data can be stored in memory accessible to the processor. A processor is designed to process instructions and data quickly. In order to keep up with the execution speed of the processor and supply data at a sufficiently fast rate to avoid causing the processor to stall unnecessarily, a cache memory may be used. A cache memory is a small data storage area that may be dedicated to one or more processors and located physically closer to the processor(s) than to memory. Both the size of the cache memory and its proximity to the processor(s) allows the processor to access the cache memory very quickly. A cache memory system may include one or more levels of cache memory, with each level positioned increasingly farther from the processor and larger in storage capacity. However, a larger cache memory is slower in access time, because the speed with which data in a particular type of memory can be accessed is typically inversely related to its storage capacity. Therefore, the cache memories in a cache memory system are typically smaller in size than a main memory and thus have a more limited amount of space than the addressable size of the main memory. As data is read from the main memory for use by the processor, the data is stored in cache lines in a cache memory in the cache memory system. Similarly, data modified by the processor is stored in cache memory of the cache memory system. In this manner, the processor can quickly access the recently used or modified data, which is likely to be needed again soon. When the cache memory is full and the processor reads new data from the main memory, a cache controller must make room in the cache memory for the new data to be stored in a cache line. To this end, a cache line currently occupied with other data in the cache memory is removed or evicted to make room for new data to be stored in the cache line, which is referred to as "cache line eviction. " A cache controller receives the memory access requests (e.g., read requests and write requests) from a processor, controls the cache memory to execute the requests, and also performs the cache line eviction. A cache controller first decides which cache line will be evicted from a cache memory based on a number of cache control policies.

One cache control policy is a replacement policy. A cache line replacement policy is a policy that uses a ranking system to identify a next cache line to be evicted when the cache controller needs to make room in a cache memory in the cache memory system for a newly inserted cache line. A situation in which data in a cache line is evicted from the cache memory and is then requested again by the processor soon after eviction causes inefficient operation in the cache memory system because time is wasted re-fetching the data from main memory. A good cache line replacement policy attempts to avoid inefficiency. A cache line insertion policy and cache line promotion policy are the other cache control policies that can affect the cache line replacement policy. A cache line insertion policy determines whether a new cache line should be inserted in a cache memory and if so, where the new cache line is ranked compared to other lines in the cache memory. The promotion policy determines how the ranking of a cache line (and the ranking of other cache lines) changes in case of a hit on that cache line due to a memory request by a processor. It is these cache control policies that determine whether the cache memory is operating efficiently. More efficient operation of the cache memory improves processor performance. For example, if a first cache line is evicted according to the cache control policies while another cache line remains in the cache memory, and the data that was stored in the first cache line is needed again by the processor before the other data, the efficiency of the cache memory is reduced. In this case, the processor's operation is unnecessarily slowed while the cache controller evicts a cache line and reinserts the needed data back into the cache memory. In another example of inefficient operation, the cache controller may load, into the cache memory, data that will only be used once by the processor before being evicted. This is known as cache pollution. The cache memory would operate more efficiently if such data was never inserted into a cache line because that could have been available to other, more frequently used data. Cache control policies that improve cache efficiency can improve processor performance and the user experience. <CIT> describes systems and methods for selectively bypassing allocation of cache lines in a cache. A bypass predictor table is provided with reuse counters to track reuse characteristics of cache lines, based on memory regions to which the cache lines belong in memory. A contender reuse counter provides an indication of a likelihood of reuse of a contender cache line in the cache pursuant to a miss in the cache for the contender cache line, and a victim reuse counter provides an indication of a likelihood of reuse for a victim cache line that will be evicted if the contender cache line is allocated in the cache. A decision whether to allocate the contender cache line in the cache or bypass allocation of the contender cache line in the cache is based on the contender reuse counter value and the victim reuse counter value.

Exemplary aspects disclosed herein include a cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information. Cache lines are storage locations in a cache memory used for faster access by a processor to stored data than retrieval from main memory. Data that has been accessed in a memory request is stored in a cache line in the cache memory system under the assumption that it may be accessed again soon by the processor, thereby alleviating the need to access the data from main memory. Under a cache control policy, a cache controller in the cache memory system assigns retention ranks to each cache line when data is initially stored and updates the retention ranks each time a cache line is accessed. The retention ranks indicate recent access activity of a cache line, which is used to determine which data has a higher likelihood of being evicted to make space for caching new data for a memory request. Preferably, the evicted data is least likely to be used by the processor.

In exemplary aspects disclosed herein, a cache management circuit is provided that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's "usefulness. " Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted. After the data has been evicted from the cache memory and is later inserted into the cache memory again when it is accessed by a subsequent memory request, the persistently stored cache control information corresponding to that memory address increases the information available for determining the usefulness of data. In this regard, the cache management circuit can increase efficiency of a cache memory system to improve processor performance.

In this regard, in a first exemplary aspect, a cache management circuit for predictive adjustment of a cache control policy based on persistent cache control information is provided. The cache management circuit is configured to receive a memory request comprising a memory address to access data at the memory address. The cache management circuit is further configured to receive a hit-miss indicator from a cache memory, the hit-miss indicator indicating a cache hit in response to the data at the memory address being stored in the cache memory and indicating a cache miss in response to the data at the memory address not being stored in the cache memory. The cache management circuit is further configured to generate cache control information corresponding to the memory address based on the hit-miss indicator and the cache control policy, store the cache control information corresponding to the memory address persistently, independent of the data being evicted from the cache memory, and control generation of a retention rank of a cache line based on the stored cache control information.

In another exemplary aspect, a method for predictive adjustment of a cache control policy based on persistent cache control information is provided. The method comprises receiving a memory request comprising a memory address to access data at the memory address. The method further comprises receiving a hit-miss indicator from a cache memory, the hit-miss indicator indicating a cache hit in response to the data at the memory address being stored in the cache memory and indicating a cache miss in response to the data at the memory address not being stored in the cache memory. The method further comprises generating cache control information corresponding to the memory address based on the hit-miss indicator and the cache control policy. The method further comprises storing the cache control information corresponding to the memory address persistently, independent of whether the data is evicted from the cache memory. The method further comprises controlling generation of a retention rank of a cache line based on the stored cache control information.

<FIG> is a diagram of a processor-based system <NUM> that includes a central processing unit (CPU) or processor <NUM> configured to issue memory requests (i.e., data read and data write requests) to a memory system <NUM> that includes a cache memory system <NUM> and a main memory <NUM>. The main memory <NUM> may include dynamic random access memory (DRAM). The cache memory system <NUM> includes one or more cache memories <NUM>(<NUM>)-<NUM>(X) that may be at different levels of hierarchy in the processor-based system <NUM>. Any of the cache memories <NUM>(<NUM>)-<NUM>(X) may include an exemplary cache management circuit <NUM>, which is explained in further detail with reference to <FIG>, configured to generate predictive cache control information based on a cache hit-miss indicator and cache line retention ranks and employ persistently stored, history-based cache control information to improve efficiency of the cache memories <NUM>(<NUM>)-<NUM>(X) for improved performance of the processor <NUM>. The processor <NUM> includes one or more CPU cores <NUM>(<NUM>)-<NUM>(N), wherein 'N' is a positive whole number representing the number of CPU cores included in the processor <NUM>. The processor <NUM> can be packaged in an integrated circuit (IC) chip <NUM>. The cache memories <NUM>(<NUM>)-<NUM>(X) may be logically located between the CPU cores <NUM>(<NUM>)-<NUM>(N) and the main memory <NUM>, where 'N' is a positive whole number representing the number of CPU cores included in the processor <NUM>. The cache memories <NUM>(<NUM>)-<NUM>(X) store or cache a subset of data contained in the main memory <NUM> to provide the CPU cores <NUM>(<NUM>)-<NUM>(N) faster access to data in the main memory <NUM> for fulfilling memory requests. A memory controller <NUM> controls access to the main memory <NUM>.

For example, a CPU core <NUM>(<NUM>)-<NUM>(N) as a requesting device may issue a memory request to request data from the memory system <NUM> in response to processing a load instruction. The memory request includes a target address of the data to be read from memory. The memory request may also include an instruction identification (ID) identifying the instruction that caused the CPU core <NUM>(<NUM>)-<NUM>(N) to issue the memory request. Using CPU core <NUM>(<NUM>) as an example, if the requested data is not in a private cache memory <NUM>(<NUM>) (i.e., a cache miss to the cache memory <NUM>(<NUM>)) which may be considered a level one (L1) cache memory, the private cache memory <NUM>(<NUM>) sends the memory request over an interconnect bus <NUM> in this example to a shared cache memory <NUM>(X) shared to all the CPU cores <NUM>(<NUM>)-<NUM>(N), which may be a level three (L3) cache memory. Other shared cache memories <NUM>(<NUM>), <NUM>(<NUM>) within the processor <NUM>, which are only shared with a subset of the CPU cores <NUM>(<NUM>)-<NUM>(N), may each be considered a level two (L2) cache memory. The requested data is eventually obtained from a cache memory <NUM>(<NUM>)-<NUM>(X) or from the main memory <NUM>. If the requested data is not contained in a lower level cache memory (e.g., <NUM>(<NUM>)), a cache miss occurs and the data is received from a higher level cache memory (e.g., <NUM>(X)) or from the main memory <NUM>. A cache miss causes the receiving cache memory <NUM>(<NUM>)-<NUM>(N) to evict data from a cache line, which holds a block of data corresponding to a memory address. Since the data in the cache line may have been updated, the evicted data from the cache line is sent out to a higher level memory and the requested data is stored in the cache line from which the data was evicted. Each cache memory <NUM>(<NUM>)-<NUM>(X) has a cache control policy that governs which of its cache lines will be evicted to a higher level cache memory <NUM>(<NUM>)-<NUM>(X) or the main memory <NUM> to make room to store new data corresponding to a memory request that resulted in a cache miss. Data is retained in the remaining cache lines in the cache memory <NUM>(<NUM>)-<NUM>(X) when there is a cache miss.

<FIG> is a schematic diagram of an exemplary cache memory system <NUM> as part of a memory system <NUM> in a processor-based system <NUM>. The processor-based system <NUM> includes a processor or CPU <NUM> that executes instructions resulting in memory requests <NUM> to the memory system <NUM> to read data into or write data out from the CPU <NUM>. The memory system <NUM> includes a main memory <NUM>. The cache memory system <NUM> includes a plurality of cache memories <NUM> at different levels of hierarchy between the CPU <NUM> and the main memory <NUM>, each level typically having different storage capacity and access latency for responding to memory requests <NUM>. A cache memory <NUM> at any level of hierarchy in the cache memory system <NUM> may include a cache management circuit <NUM> configured to predictively adjust cache control policies based on persistent, history-based cache control information and manage the eviction and insertion of new data in the cache memory <NUM> in response to a cache miss. The cache memory <NUM> in the memory system <NUM> is more closely coupled to the CPU <NUM> than the main memory <NUM> in the memory system <NUM>. Thus, the cache memory <NUM> is able to provide faster access to data compared to the main memory <NUM>, which is accessible over a system bus <NUM>. The cache memory <NUM> in this example may be at any level in the memory system <NUM>. For example, the cache memory <NUM> may be a level one (L1) cache memory unless the CPU <NUM> includes an optional internal cache memory <NUM>, in which case the cache memory <NUM> would be a level two (L2) cache memory or higher.

The cache memory <NUM> in this example is an N-way, M-set associative cache, which means that the cache memory <NUM> is divided into M separately addressable sets SET(<NUM>)-SET(M-<NUM>), where M is a positive integer. Each of the sets SET(<NUM>)-SET(M-<NUM>) is addressed by a subset of the memory address such that many memory addresses correspond to each of the sets SET(<NUM>)-SET(M-<NUM>). Each of the sets SET(<NUM>)-SET(M-<NUM>) includes N ways WAY(<NUM>)-WAY(N-<NUM>), where N is also a positive integer. Each of the ways WAY(<NUM>)-WAY(N-<NUM>) is also referred to herein as a cache line <NUM>, which refers to a high-speed storage area capable of storing a block of sequential data (i.e., bytes of data) addressable at a memory address. The cache lines <NUM> are not directly mapped to particular memory addresses. Thus, any memory address that corresponds to a particular set SET(X) of the sets SET(<NUM>)-SET(M-<NUM>) can be stored in any of the N cache lines <NUM> therein.

A memory request <NUM> from the CPU <NUM> includes a memory address and an indication of whether data is to be accessed (i.e., read from or written into) by the CPU <NUM> from the memory system <NUM>. "Requested data" is a term that may be used herein to refer to data that is to be read into the CPU <NUM> from a memory address in a READ type memory request <NUM> or data at a storage location corresponding to the memory address where data is to be written (i.e., overwritten) in a WRITE type memory request <NUM>. In the processor-based system <NUM> in <FIG>, the memory request <NUM> is received at the cache management circuit <NUM>. The cache management circuit <NUM> includes a cache control circuit <NUM> in this example that receives from the cache memory <NUM> a hit-miss indicator <NUM> indicating whether any of the cache lines <NUM> in the set SET(X) addressed by the memory request <NUM> contain the requested data. In this example, the requested data is a portion or all of a data block that will fit into a cache line <NUM>. If the requested data is found in the cache memory <NUM>, the hit-miss indicator <NUM> will indicate a cache hit and will also identify the cache line <NUM> containing the requested data. If none of the cache lines <NUM> in the set SET(X) addressed by the memory address in the memory request <NUM> contains the requested data, the hit-miss indicator <NUM> will indicate a cache miss in the cache memory <NUM>.

When a cache miss occurs as the CPU <NUM> attempts to access a data block from the memory address contained in the memory request <NUM>, the cache management circuit <NUM> is configured to direct the memory request <NUM> to the system bus <NUM> to obtain the requested data from the main memory <NUM>. The cache management circuit <NUM> receives the requested data over the system bus <NUM> and stores the requested data in the cache memory <NUM>. If the cache memory <NUM> is full, there is no space for the requested data to be stored unless one of the cache lines <NUM> is evicted, which means that data stored in the cache line <NUM> is sent to a higher level memory in the memory system <NUM>, as discussed above. This allows the requested data to be stored in the evicted cache line <NUM>. In a typical cache memory system, no information pertaining to the data evicted from the cache line <NUM> is saved.

The cache control circuit <NUM> determines which of the cache lines <NUM> in a set SET(X) is to be evicted in case of a cache miss based on retention ranks <NUM>(<NUM>)-<NUM>(P), assigned to each of the cache lines <NUM> by a rank manager circuit <NUM>. The retention ranks <NUM>(<NUM>)-<NUM>(P) will be subsequently referred to herein individually or collectively as retention rank(s) <NUM>. P+<NUM> is an integer value equal to the number of cache lines <NUM> in the cache memory, such that there is a retention rank <NUM> for each cache line <NUM>. The rank manager circuit <NUM> maintains the retention ranks <NUM> for each of the cache lines <NUM> in the cache memory <NUM>. The cache line <NUM> with a lowest retention rank <NUM> will be evicted in a cache miss in this example. A lowest retention rank <NUM> assigned to a cache line <NUM> indicates that the cache line <NUM> may have the least usefulness to the processor compared to the data in the other cache lines <NUM>. The cache control circuit <NUM> checks the rank manager circuit <NUM> to determine which cache line <NUM> has the lowest retention rank <NUM> and evicts the corresponding cache line <NUM>. The rank manager circuit <NUM> generates a retention rank <NUM> for each cache line <NUM> based on a cache control policy. As a non-limiting example of a cache control policy, the rank manager circuit <NUM> may generate retention ranks <NUM> based on how recently cache lines <NUM> in a set SET(X) were inserted or accessed due to a cache hit. In this manner, the cache control policy indicates usefulness by assigning retention ranks according to how recently the data was accessed.

In an example, a set SET(X) with eight (<NUM>) ways or cache lines <NUM> may assign integer retention ranks <NUM> to the cache lines <NUM> in the range from <NUM> to <NUM>, where a highest retention rank (<NUM>) is assigned to the cache line <NUM> that is most-recently used (MRU). A lowest retention rank (<NUM>) is assigned to the least-recently used (LRU) cache line <NUM>, which means that all other cache lines <NUM> have been accessed more recently than the LRU cache line <NUM>. Under such cache control policy (MRU/LRU), the MRU cache line <NUM> is deemed to have the highest usefulness because it is the most recently accessed. The LRU cache line <NUM> is deemed to have the least usefulness to the processor because all other cache lines <NUM> have been accessed more recently. Thus, the cache line <NUM> with the lowest retention rank <NUM> (LRU) is selected for eviction in case of a cache miss. No information pertaining to the retention ranks or cache activity related to the data evicted from the cache line <NUM> is saved when the data is no longer stored in the cache memory <NUM>.

Continuing the above example of an underlying cache control policy, when the new data corresponding to the memory request <NUM> is stored, the rank manager circuit <NUM> generates new retention ranks <NUM>, and the LRU cache line <NUM> becomes the MRU cache line <NUM>. The retention ranks <NUM> for each of the other cache lines <NUM> are reduced, so there is a new LRU cache line <NUM> that may be the next evicted cache line <NUM> in case of a cache miss. If the CPU <NUM> issues a memory request <NUM> for which the requested data is in the LRU cache line <NUM>, the hit-miss indicator <NUM> will indicate a cache hit and identify the LRU cache line <NUM>. The rank manager circuit <NUM> will again generate new retention ranks <NUM> for each of the cache lines <NUM>, with the LRU cache line <NUM> becoming the new MRU cache line <NUM>, and the retention ranks <NUM> of each of the other cache lines <NUM> being reduced, so the cache line <NUM> that was assigned the retention rank <NUM> becomes the new LRU cache line <NUM> (i.e., with retention rank <NUM>). The retention ranks <NUM> to <NUM> are only an example. Other numerical or non-numerical retention ranks <NUM> may be used to achieve the same purpose. In addition, the retention ranks <NUM> may be generated based on a different underlying cache control policy that is not based on how recently a cache line <NUM> is accessed. Any other such cache control policy for determining retention ranks <NUM> to identify a cache line <NUM> that is to be evicted and overwritten in the case of a cache miss may be predictively adjusted as further described herein.

In an exemplary aspect, the cache management circuit <NUM> further includes a predictive adjustment circuit <NUM> to control aspects of the cache control circuit <NUM> and the rank manager circuit <NUM> based on persistently stored, history-based cache control information <NUM>(<NUM>)-<NUM>(T) corresponding respectively to T memory addresses, where T is an integer. One of the cache control information <NUM>(<NUM>)-<NUM>(T) may be referred to herein as cache control information <NUM>, unless otherwise noted. In some cases, controlling aspects of the cache control circuit <NUM> and the rank manager circuit <NUM> includes overriding normal operation of the cache control circuit <NUM> and the rank manager circuit <NUM>, disregarding the underlying cache control policy.

A flowchart illustrating an exemplary method <NUM> of predictive adjustment of cache control policy based on persistent, history-based cache control information, is shown in <FIG>. The method <NUM> includes receiving a memory request <NUM> for data from a memory address (block <NUM>). The method <NUM> also includes receiving a hit-miss indicator <NUM> from a cache memory <NUM> indicating whether the data is stored in the cache memory <NUM> (block <NUM>). The method <NUM> further includes generating cache control information <NUM> corresponding to the memory address based on the hit-miss indicator <NUM> and the cache control policy (block <NUM>). The method <NUM> includes storing the cache control information <NUM> corresponding to the memory address persistently, independent of whether the data from the memory address is evicted from the cache memory <NUM> (block <NUM>). The method <NUM> still further includes controlling generation of a retention rank <NUM> of a cache line <NUM> based on the stored cache control information <NUM> (block <NUM>).

Returning to <FIG>, in some cases, the history of previous cache activity preserved in the persistent cache control information <NUM> may enable the cache management circuit <NUM> to make a more informed determination of, for example, which cache line <NUM> has the lowest usefulness, or what retention rank <NUM> should be assigned to a newly-inserted cache line <NUM>. Thus, by overriding the existing cache control policy, the cache management circuit <NUM> can improve efficiency of the cache operation and correspondingly improve processor performance. In other cases, controlling aspects of the cache control circuit <NUM> and the rank manager circuit <NUM> involves merely allowing the cache control circuit <NUM> and the rank manager circuit <NUM> to follow the underlying cache control policy. In the case of cache control policies as described above (MRU/LRU), rather than assigning the highest retention rank <NUM> (MRU) to a cache line <NUM> in which new data is inserted, the cache management circuit <NUM> may assign a lower retention rank <NUM> to provide an opportunity for other useful data to remain in the cache for a longer period of time. In this regard, the cache control information <NUM> corresponding to a memory address may indicate a retention rank <NUM> of a cache line <NUM> the last time there was a cache hit on such data in the cache memory <NUM>. This information can be used to predictively adjust the retention rank <NUM> when the data is later reinserted into the cache line <NUM>. Alternatively, the cache management circuit <NUM> may determine that requested data should not be inserted into the cache memory <NUM> at all.

Further, the retention rank <NUM> assigned to a cache line <NUM> may not be set to the MRU when there is a cache hit on the cache line <NUM>, even though such cache line <NUM> is the most-recently used. In this regard, the underlying promotion policy may be overridden to improve cache efficiency. The cache management circuit <NUM> may override an existing cache control policy as discussed above to allow other useful cache lines <NUM> an opportunity to stay in the cache memory <NUM> longer, which improves cache efficiency and improves performance of the CPU <NUM>.

With reference to <FIG>, the predictive adjustment circuit <NUM> generates the cache control information <NUM> in response to a memory request <NUM>. The cache control information <NUM> is based on the hit-miss indicator <NUM> received from the cache memory <NUM> and on the retention rank <NUM> of a cache line <NUM> accessed by the memory request <NUM>. Whether the memory request <NUM> results in a cache hit or a cache miss, the requested data from the memory address is stored in an accessed cache line <NUM>. In the case of a cache hit, the accessed cache line <NUM> will be the cache line <NUM> identified by the hit-miss indicator <NUM> indicating where the data is stored. In the case of a cache miss, the accessed cache line <NUM> will be the evicted cache line <NUM> in which data from the memory address will be inserted.

In an optimal case, as described herein, the cache line <NUM> accessed in a cache hit will be the cache line <NUM> with the lowest retention rank <NUM>. This indicates efficient operation of the cache memory <NUM> because a cache hit occurring on a cache line <NUM> that is currently assigned the lowest retention rank <NUM> means that data blocks in the other cache lines <NUM>, which may still be useful, have a greater opportunity to remain in the cache memory <NUM> and be available for re-use by the CPU <NUM> compared to a case in which a cache hit occurs on a cache line <NUM> that is not assigned the lowest retention rank <NUM>.

Achieving cache hits that are the optimal case as described above is an objective of the cache management circuit <NUM>. To accomplish this exemplary objective, the predictive adjustment circuit <NUM> is configured to generate the cache control information <NUM> corresponding to a memory address and store the cache control information <NUM> persistently. Persistent storage of the cache control information <NUM> refers to retaining the cache control information <NUM> independent of whether data from the memory address is stored in any cache line <NUM> in the cache memory <NUM>. Thus, the cache control information <NUM> is stored in the predictive adjustment circuit <NUM> even after a cache line <NUM> storing the data for the memory address is evicted and the data is sent to a higher level of hierarchy in the cache memory system <NUM> or main memory <NUM>. The cache control information <NUM> is persistently stored, because it provides a history of accesses to the corresponding memory address and such history can be employed to make predictions about future accesses to the same memory address. In this manner, it is possible to increase a probability that cache hits to the memory address will be the optimal cases. In a particular aspect, the predictive adjustment circuit <NUM> can control the rank manager circuit <NUM> to set a retention rank <NUM> for a cache line <NUM> in which data from a memory address is inserted. The setting of the retention ranks <NUM> is based, at least in part, on the stored cache control information <NUM> corresponding to the memory address.

With continued reference to <FIG>, the cache control information <NUM> corresponding to a memory address is generated from the hit-miss indicator <NUM> and the retention ranks <NUM> of the cache line <NUM> accessed in a memory request <NUM> to the memory address. The cache control information <NUM> includes a did_hit (DH) indicator <NUM> and a replacement likelihood (REPL) <NUM> in this example. The DH indicator <NUM> may be implemented as a single binary bit in some examples. Thus, the DH indicator <NUM> may be referred to as DH bit <NUM> which is set to indicate that a cache hit occurred in response to a memory request <NUM> to the memory address. The DH bit <NUM> being in a reset state indicates no cache hit occurred on a cache line <NUM> in which the data is stored. The REPL <NUM> is a history-based retention rank that has a value of a retention rank <NUM> of a cache line <NUM> when a cache hit previously occurred on the corresponding memory address. The predictive adjustment circuit <NUM> provides such controls based on the DH bit <NUM> and the REPL <NUM>.

The predictive adjustment circuit <NUM> attempts to create the optimal case described above in the cache memory <NUM> based on a history of cache activity associated with a memory address. Such information can be helpful in this regard because of the repetitive nature of data accesses of the instructions in a software program, module, script, application, etc. However, a particular memory address may be accessed by more than one part of a program and by more than one program. Thus, the history of cache activity associated with the memory address alone may be insufficient. To provide more relevant information, it is helpful to identify a specific instance of a memory address being requested based on information available within the cache memory <NUM> or the cache management circuit <NUM>. In this regard, the predictive adjustment circuit <NUM> includes a replacement likelihood history (RLH) circuit <NUM> to record the retention ranks <NUM> of cache lines <NUM> accessed in the cache memory <NUM> in sequential order. The RLH circuit <NUM> may generate a single RLH pattern <NUM> of retention ranks <NUM> of all cache lines <NUM> accessed in the cache memory <NUM>. In this regard, the RLH pattern <NUM> changes with every cache hit. Alternatively, the RLH circuit <NUM> may generate a separate RLH pattern <NUM> for each one of the sets SET(<NUM>)-SET(M-<NUM>) that contains a record of retention ranks <NUM> for only the cache lines <NUM> within a single set SET(X). In this example, only the RLH pattern <NUM> of a set in which the cache hit occurs will be updated. The RLH patterns <NUM> for the other sets would be unchanged.

Each RLH pattern <NUM> may be indicative of a particular sequence of instructions in a program or application, and thereby provides some context for a memory request <NUM> to a particular memory address, as explained below. As an example, if the retention ranks <NUM> are in a range from <NUM> to <NUM>, an RLH pattern <NUM> of "<NUM><NUM><NUM><NUM><NUM>" means that cache lines <NUM> having the highest retention rank <NUM> of <NUM> were accessed three times in a row, followed by accessing a cache line <NUM> having a retention rank <NUM> of <NUM>, followed by accessing a cache line <NUM> having the lowest retention rank <NUM> of <NUM>.

Associating the cache control information <NUM> with both a memory address and the RLH pattern <NUM> existing at the time of an access to the memory address provides context that may make cache control information <NUM> more relevant to a particular point in a software application in which that memory address is accessed. Cache control information <NUM> for one occasion in which a memory address is accessed in a software application may be unhelpful, and potentially cause a reduction in efficiency, if used to predictively adjust the rank manager circuit <NUM> or the cache control circuit <NUM> when the memory address is accessed on another unrelated occasion within the software application.

Therefore, the predictive adjustment circuit <NUM> in this example also includes a hash circuit <NUM> that generates a hash <NUM> of a memory address of a memory request <NUM> and the RLH pattern <NUM> (e.g., as a numerical value) recorded when the memory request <NUM> is received. In this regard, each one of a plurality of entries <NUM>(<NUM>)-<NUM>(T) in a predictor table <NUM> stores one of the cache control information <NUM>(<NUM>)-<NUM>(T) related to both the memory address and an indication of recent activity in the cache memory <NUM> corresponding to the memory request <NUM>. The entries <NUM>(<NUM>)-<NUM>(T) may be referred to herein individually or collectively as entry <NUM> or entries <NUM>, respectively. The predictive adjustment circuit <NUM> allocates the entry <NUM> in the predictor table <NUM> to store the DH bit <NUM> and the REPL <NUM> corresponding to the memory address and the RLH pattern <NUM>. The entry <NUM> is identified by an index <NUM> matching the hash <NUM>. Thus, the cache control information <NUM> in each entry <NUM> corresponds to a memory address and to a sequence of memory accesses in a program prior to that memory address being accessed. When there is another occurrence of an access to a memory address with the same sequence, or RLH pattern <NUM>, the corresponding cache control information <NUM> is accessed and used for predictive control of the cache control circuit <NUM> and the rank manager circuit <NUM>.

As noted, an entry <NUM> in the predictor table <NUM> is indexed by the hash <NUM> of the RLH pattern <NUM> and the memory address of a memory request <NUM>. To evaluate the cache control information <NUM> corresponding to a memory address in a memory request <NUM>, the entry <NUM> is found in the predictor table <NUM>. The entry <NUM> is found by comparing the hash <NUM> to an index <NUM> of the entry <NUM>. The entry <NUM> corresponding to a memory request <NUM> and an RLH pattern <NUM> is found when the hash <NUM> matches the index <NUM> in an entry <NUM>. Matching, in this regard, means that at least a portion of the hash <NUM> is the same as at least a portion of the index <NUM>. For example, if the hash <NUM> and the index <NUM> are multibit binary values, at least some of the bits of the hash <NUM> and the index <NUM> are the same.

The predictor table <NUM>, according to the present disclosure, may be an untagged predictor table <NUM>, a tagged predictor table <NUM>, or a hybrid predictor table <NUM>. In a first example of the present cache management circuit <NUM>, the predictor table <NUM> is untagged. The cache management circuit finds an entry <NUM> by comparing the hash <NUM> of the memory request <NUM> to the indexes <NUM> of entries <NUM> in the predictor table <NUM>. An untagged predictor table <NUM> includes indexes <NUM> that may match many different hashes <NUM>, ensuring that the hash <NUM> generated for a memory request <NUM> will be matched with an index <NUM> of an entry <NUM> in the predictor table <NUM>. In other words, in an example with an untagged predictor table <NUM>, an entry <NUM> matching the hash <NUM> will be found. The index <NUM> of each entry <NUM> in an untagged predictor table <NUM> matching many different hashes <NUM> may be referred to as aliasing. In this regard, the cache control information <NUM> in the entry <NUM> having the matching index <NUM> may not be specific to the particular memory address and RLH pattern <NUM> that were the basis of the hash <NUM>. Rather, the cache control information <NUM> in the entry <NUM> may not pertain at all to the memory address corresponding to the hash <NUM>. In this regard, aliasing may cause constructive or destructive cache control information <NUM>.

In a second example described herein, the cache management circuit <NUM> includes a tagged predictor table <NUM>, in which a hash <NUM> may not match the index <NUM> of any entry <NUM>. As in the first example including an untagged predictor table <NUM>, the cache management circuit finds an entry <NUM> by comparing the hash <NUM> of the memory request <NUM> to the indexes <NUM> of entries <NUM> in the predictor table <NUM>. In a tagged predictor table, the index <NUM> of an entry <NUM> may only match a single hash <NUM> or a small set of hashes <NUM>, such that the cache control information <NUM> in each entry <NUM> may be more relevant and therefore more helpful in predictively adjusting the cache control policy. However, the hash <NUM> generated by the hash circuit <NUM> may not always correspond to an index <NUM> in the tagged predictor table <NUM>. When the cache management circuit <NUM> proceeds to find an entry <NUM> with an index <NUM> that matches a hash <NUM>, the cache management circuit <NUM> may be unsuccessful. After attempting to find the entry <NUM>, the second example of the cache management circuit <NUM> determines that no entry <NUM> is found. This is referred to as a predictor table miss. A predictor table miss cannot happen in an untagged predictor table <NUM>, as disclosed with regard to the first example of the cache management circuit <NUM> above. In the second example, including the tagged predictor table <NUM>, there are circumstances under which no predictive adjustment is provided because no relevant cache control information <NUM> is found. In this situation, the cache control circuit <NUM> and the rank manager circuit <NUM> are allowed to operate according to an underlying cache control policy. In addition, the cache management circuit <NUM> allocates an entry <NUM> with an index <NUM> that matches the hash <NUM> corresponding to the RLH pattern <NUM> and the memory address of the memory request <NUM>.

In a third example of the cache management circuit <NUM>, a hybrid predictor table <NUM> and some of the entries <NUM> may be tagged while others are untagged, providing some benefits and disadvantages of the first example and the second example.

In an example, a set in a set-associative cache may have eight (<NUM>) ways or cache lines <NUM>, and a cache control policy may have numerical integer retention ranks <NUM> in a range from <NUM> to <NUM>, one for each cache line <NUM>. In this example, the REPL <NUM> in an entry <NUM> having an index <NUM> that matches the hash <NUM> for a memory request <NUM> to a memory address may be any number from <NUM> to <NUM> requiring three (<NUM>) bits in each entry <NUM> for the REPL <NUM>. However, if each entry <NUM> only includes two (<NUM>) bits for the REPL <NUM>, each value of a REPL <NUM> will correspond to two different retention ranks <NUM> assigned to different cache lines <NUM>. For example, the REPL <NUM> value of "<NUM>" represented as two binary digits may correspond to retention ranks <NUM> and <NUM>, and the REPL value of "<NUM>" may correspond to retention ranks <NUM> and <NUM>, etc..

In the cache management circuit <NUM> herein, in an example, if a retention ranking policy employs integer values from a lowest retention rank of "<NUM>" to a highest retention rank of "HRR" and there is no entry <NUM> in the predictor table <NUM> that matches the hash <NUM> of a memory request <NUM>, a retention rank <NUM> of a cache line <NUM> is set to HRR by default (e.g., MRU). Similarly, if there is a matching entry <NUM> in which the cache control information <NUM> indicates a default state (e.g., DH bit <NUM> = <NUM> and REPL <NUM> = HRR), the retention rank <NUM> of a cache line <NUM> is also set to HRR. If the cache control information <NUM> in the entry <NUM> indicates that there was not a cache hit on the data from the memory address when previously stored in a cache line <NUM>, the insertion of the data into the cache line <NUM> is bypassed. If the cache control information <NUM> is not one of the above conditions, the cache control information <NUM> is assumed to be valid, and the selected cache line <NUM> is set to a retention rank <NUM> determined by the equation "HRR minus REPL <NUM>" (i.e., HRR - REPL <NUM>) under the object of achieving the optimal case described above.

For example, if requested data for a memory address is to be reinserted into the cache memory <NUM> due to a memory request <NUM> and the persistent cache control information <NUM> for the memory address includes REPL <NUM> = <NUM>, this means that the last time there was a cache hit on the requested data before it was evicted from the cache memory <NUM>, the retention rank <NUM> of the cache line <NUM> storing that requested data was "<NUM>. " Assuming data activity in the cache memory <NUM> is repetitive, the retention rank <NUM> of the cache line <NUM> in which the data is reinserted could be set two retention ranks lower, such that the next cache hit would occur when the retention rank <NUM> for the cache line <NUM> = "<NUM>. " This would allow data in two other cache lines <NUM> the opportunity to remain in the cache memory <NUM> longer, potentially making the cache memory system <NUM> operation more efficient. Specifically, in this example, if HRR = <NUM>, and REPL <NUM> = <NUM> for the requested data, the retention rank <NUM> of the cache line <NUM> upon insertion will be set to <NUM> - <NUM> = <NUM>. Thus, the retention rank <NUM> of the selected cache line <NUM> is set lower than the highest retention rank <NUM> (i.e., <NUM> by an amount (<NUM>) equal to a difference between the REPL <NUM> (<NUM>) and the lowest retention rank <NUM> (<NUM>). As a result, a cache hit should occur on the subject data when the retention rank <NUM> for the cache line <NUM> is at the lowest retention rank <NUM>, before the subject data is again evicted, as in the optimal case.

Descriptions of the operations of the cache management circuit <NUM>, and more particularly the predictive adjustment circuit <NUM>, under various circumstances of memory requests <NUM> to the cache memory <NUM> are provided below with reference to <FIG> and <FIG>-<NUM>.

<FIG> is a flowchart illustrating an exemplary process <NUM> that can be performed by the cache management circuit <NUM> of <FIG> in response to a memory request <NUM> to a memory address in which the hit-miss indicator <NUM> indicates a cache hit on a cache line <NUM> in a set SET(X) (block <NUM>). Flow of a cache management circuit <NUM> according to the first example, in which the predictor table <NUM> is untagged, is described first with reference to <FIG>. A cache management circuit <NUM> according to the second example, having a tagged predictor table, is described with reference to <FIG> below.

After the cache management circuit <NUM> receives the hit-miss indicator indicating a cache hit, the predictive adjustment circuit <NUM> finds an entry <NUM> in the predictor table <NUM>. with an index <NUM> matching the hash <NUM> that was generated for the memory request <NUM> (block <NUM>). An aliasing situation can be recognized by the predictive adjustment circuit <NUM> upon inspecting the cache control information <NUM> in the entry <NUM> found after a cache hit and determining that the DH bit <NUM> is reset and the REPL <NUM> is set to the lowest retention rank <NUM> (block <NUM>). Such combination of the DH bit <NUM> and the REPL <NUM> on a cache hit indicates an aliasing situation. In such case, the predictive adjustment circuit <NUM> responds as if there was not a hit on the predictor table <NUM>. Specifically, the predictive adjustment circuit <NUM> will control the rank manager circuit <NUM> to set the retention rank <NUM> of the cache line <NUM> that was "hit" by the memory request <NUM> to the highest retention rank <NUM>, and set the REPL <NUM> in the entry <NUM> to the highest retention rank <NUM> (block <NUM>). The predictive adjustment circuit <NUM> also sets the DH bit <NUM> in the entry <NUM> (block <NUM>).

If the predictive adjustment circuit <NUM> determines at block <NUM> that the DH bit <NUM> remains set (i.e., is not reset) or the REPL <NUM> is not set to the lowest retention rank <NUM>, the predictive adjustment circuit <NUM> determines that the information in the entry <NUM> does not indicate an aliasing situation. Subsequently, if the predictive adjustment circuit <NUM> determines that the retention rank <NUM> of the "hit" cache line <NUM> is lower than the REPL <NUM> in the entry <NUM> corresponding to the cache line <NUM>, the predictive adjustment circuit <NUM> controls the rank manager circuit <NUM> to generate the new retention rank <NUM> of the cache line <NUM> to equal the current REPL <NUM> in the entry <NUM> (block <NUM>). Also, if the predictive adjustment circuit <NUM> determines that retention rank <NUM> of the cache line <NUM> (at the time of the memory request <NUM>) is not equal to the lowest retention rank <NUM>, the predictive adjustment circuit <NUM> sets the REPL <NUM> in the entry <NUM> to the lower of the REPL <NUM> and the retention rank <NUM> of the cache line <NUM> (block <NUM>). Here also, the predictive adjustment circuit <NUM> sets the DH bit <NUM> in the entry <NUM> (block <NUM>).

A description of operation in the second example of the cache management circuit <NUM>, in which the predictor table <NUM> is tagged, continues with reference to <FIG>. In response to the hit-miss indicator <NUM> indicating a cache hit, the predictive adjustment circuit <NUM> compares the hash <NUM> to indexes <NUM> of the entries <NUM> in the predictor table <NUM> to find an entry <NUM> with an index <NUM> matching the hash <NUM> that was generated for the memory request <NUM> (block <NUM>). When a matching entry <NUM> is found, this is referred to in the context of a tagged predictor table as a hit in the predictor table <NUM>. This corresponds to the first example in which the predictor table is untagged because, in the first example, a matching entry <NUM> will be found. In this situation, operation of the cache management circuit <NUM> proceeds as discussed above with regard to the first example (blocks <NUM>-<NUM>).

In the second example, there may not be an entry <NUM> in a tagged predictor table <NUM> with an index <NUM> matching a hash <NUM>. Therefore, the following operations are only performed in the second example of the cache management circuit <NUM> because it includes a tagged predictor table <NUM>. Here, the cache management circuit <NUM> may be unsuccessful in finding an entry <NUM> in the predictor table <NUM> and must determine whether an entry <NUM> is found (block <NUM>). If not, this is referred to herein as a predictor table miss in which there is no entry <NUM> in the predictor table <NUM> matching the hash <NUM>, as discussed below with reference to <FIG>. In case it is determined that an entry <NUM> is not found in the predictor table <NUM> (block <NUM>), an entry <NUM> with an index <NUM> matching the hash <NUM> is allocated in the predictor table <NUM> (block <NUM>). Because there is a cache hit, the DH bit <NUM> is set (e.g., to <NUM>) in the created entry <NUM>, and the REPL <NUM> is set to the retention rank <NUM> of the cache line <NUM> in which the data block for the memory address of the memory request <NUM> was found (block <NUM>). Blocks <NUM>, <NUM>, and <NUM> are shown here as optional because they are not included in operation of the cache management circuit <NUM> with an untagged predictor table <NUM>.

<FIG> is a flowchart illustrating an exemplary process <NUM> of detailed operation of the cache management circuit <NUM> illustrated in <FIG> in the case of a cache miss. Flow of a the first example of the cache management circuit <NUM>, in which the predictor table <NUM> is untagged, is described first with reference to <FIG>. A cache management circuit <NUM> according to the second example, having a tagged predictor table, is described with further reference to <FIG> below.

The cache management circuit <NUM> determines the hit-miss indicator <NUM> indicating a cache miss in the set SET(X) corresponding to the memory address (block <NUM>). In the case of the cache miss, the predictive adjustment circuit <NUM> selects a cache line <NUM> for eviction, and the data block for the memory request <NUM> is inserted in the selected cache line <NUM>. After the cache management circuit <NUM> receives the hit-miss indicator indicating the cache miss, the predictive adjustment circuit <NUM> finds an entry <NUM> in the predictor table <NUM> with an index <NUM> that matches the hash <NUM> that was generated for the memory request <NUM> (block <NUM>). In this regard, the predictive adjustment circuit <NUM> accesses entries <NUM> in the predictor table <NUM> corresponding to each of the cache lines <NUM> in the set SET(X) for the memory request <NUM> (block <NUM>).

In some instances, particularly when aliasing occurs, the cache control information <NUM> in a previously existing entry <NUM> for a data block that is reinserted into the cache memory <NUM> upon a cache miss needs to be refreshed. Therefore, the predictive adjustment circuit <NUM> includes a determination of a probabilistic reset of the cache control information <NUM> in the entry <NUM> (block <NUM>). That is, the DH bit <NUM> may be reset according to a probability and, upon the DH bit <NUM> being reset, the REPL <NUM> may be set to be equal to the highest retention rank <NUM>. The probability determination for resetting the DH bit <NUM> may be in a range from zero (<NUM>), in which case the DH bit <NUM> is never reset, to one (<NUM>), in which case the DH bit <NUM> is always reset. The probability may be set statically or determined dynamically based on factors such as a number of entries <NUM> in the predictor table <NUM>, or based on conditions or circumstances, such as the size of the data footprint, and/or particular behaviors or characteristics of an application that is the source of the memory requests <NUM>. In this regard, in response to determining there will be a probabilistic reset of the entry <NUM>, the predictive adjustment circuit <NUM> may probabilistically reset the DH bit <NUM> and, in response to the DH bit <NUM> being reset, set the REPL <NUM> to the highest retention rank <NUM> (block <NUM>), according to the cache control policy. If the probabilistic reset is not performed, the cache control information <NUM> in the entry <NUM> remains unchanged for use by the cache management circuit <NUM>. The above steps are directed to the cache control information <NUM> for the data at the memory address in the memory request <NUM>. In addition, the cache management circuit <NUM> determines whether the new data will be inserted into a cache line <NUM> in the cache memory <NUM> and, if so, into which cache line.

Thus, the cache management circuit <NUM> determines if the DH bit <NUM> is reset and the REPL <NUM> is equal to the lowest retention rank <NUM> (block <NUM>). If so, the predictive adjustment circuit <NUM> controls the cache control circuit <NUM> to bypass inserting (i.e., no insert) the accessed data block of the memory request <NUM> into the selected cache line <NUM> that was selected for eviction (block <NUM>). That is, from the cache control information <NUM>, it appears that, if the data block from the memory address of the memory request <NUM> is inserted into the cache memory <NUM>, it is unlikely that it would be hit in a future memory request <NUM> before being evicted from the cache memory <NUM>. Thus, the predictive adjustment circuit <NUM>, based on the cache control information <NUM>, determines that the data block for the memory request <NUM> will not be inserted (stored) in the cache memory <NUM>. The cache line <NUM> selected for eviction is not evicted in this case.

The selection of a cache line <NUM> for eviction begins by accessing entries <NUM> for the memory addresses of data in every cache line <NUM> in the set SET(X) corresponding to the memory address (<NUM>). In response to determining the DH bit <NUM> in all of the accessed entries <NUM> are set (block <NUM>), the cache management circuit <NUM> selects a cache line <NUM> having a retention rank <NUM> equal to the lowest retention rank <NUM> for eviction (block <NUM>). On the other hand, in response to determining the DH bit <NUM> in at least one of the accessed entries <NUM> is reset (block <NUM>), the predictive adjustment circuit <NUM> selects for eviction a cache line <NUM> among the cache lines <NUM> having the DH bit <NUM> reset with the lowest REPL <NUM> (block <NUM>). In this case, the predictive adjustment circuit <NUM> also reduces the REPL <NUM> in the entry <NUM> of the cache line <NUM> selected for eviction (block <NUM>), because the cache line <NUM> selected for eviction was never hit after initially being stored in the cache memory <NUM>. Reducing the REPL <NUM> may mean decrementing the REPL <NUM> by one (<NUM>) or, if the REPL <NUM> is equal to the highest retention rank <NUM>, setting the REPL <NUM> equal to the lowest retention rank <NUM>.

After selection of the cache line <NUM> (blocks <NUM> or <NUM>), the cache management circuit <NUM> controls generation of the retention rank of the cache line <NUM> based on the cache control information <NUM> corresponding to the memory address of the memory request <NUM>. If the DH bit <NUM> is reset and the REPL <NUM> is equal to the highest retention rank <NUM> (block <NUM>), there is not sufficient information about the data block for the memory request <NUM> to alter the cache control policy. Thus, the predictive adjustment circuit <NUM> controls the rank manager circuit <NUM> to set the retention rank <NUM> of the selected cache line <NUM>, where the data block for the memory request <NUM> is inserted, to the highest retention rank <NUM> (block <NUM>), according to the cache control policy.

Otherwise, in response to determining the DH bit <NUM> in the entry <NUM> is set or the REPL <NUM> in the entry <NUM> is not equal to the highest retention rank <NUM> (block <NUM>), the predictive adjustment circuit <NUM> controls the rank manager circuit <NUM> to set the retention rank <NUM> of the selected cache line <NUM> lower than the highest retention rank <NUM> by a difference equal to a difference between the REPL <NUM> in the entry <NUM> and the lowest retention rank <NUM> (block <NUM>).

Operation of the second example of the cache management circuit <NUM>, in which the predictor table is tagged, continues with reference to <FIG>. In the case of a cache miss and a predictor table hit, operation proceeds as discussed above with regard to the first example with an untagged predictor table. However, in this example, there may be a miss on the tagged predictor table <NUM>. Thus, after the cache management circuit compares the hash <NUM> to the indexes of all entries <NUM> in the set SET(X) of the cache memory <NUM> corresponding to the memory address of the memory request <NUM>, the cache management circuit determines whether no entry <NUM> was found in the tagged predictor table <NUM>. This determination (bock <NUM>) and any subsequent steps performed in the second example in case of a predictor table miss are not performed in the first example with an untagged predictor table. In case it is determined that the hash <NUM> does not match an index <NUM> of an entry <NUM> in the predictor table <NUM> (block <NUM>), an entry <NUM> with an index <NUM> matching the hash <NUM> is allocated in the predictor table <NUM> (block <NUM>). Because there is a cache miss, the DH bit <NUM> is reset (e.g., to <NUM>) in the allocated entry <NUM>, and the REPL <NUM> is set to the highest retention rank <NUM> (block <NUM>). The predictive adjustment circuit <NUM> also controls the rank manager circuit <NUM> to set the retention rank <NUM> of the selected cache line <NUM>, where the data block for the memory request <NUM> is inserted, to the highest retention rank <NUM> (block <NUM>).

<FIG> is a block diagram of an exemplary processor-based system <NUM> that includes a processor <NUM> (e.g., a microprocessor) that includes an instruction processing circuit <NUM>. The processor-based system <NUM> can be the processor-based system <NUM> in <FIG> as an example. The instruction processing circuit <NUM> can be the CPU <NUM> in <FIG> as an example. The processor-based system <NUM> may be a circuit or circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server, or a user's computer. In this example, the processor-based system <NUM> includes the processor <NUM>. The processor <NUM> represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like. More particularly, the processor <NUM> may be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for communicating produced values resulting from execution of producer instructions. The processor <NUM> is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor <NUM> includes an instruction cache <NUM> for temporary, fast access memory storage of instructions accessible by the instruction processing circuit <NUM>. The instruction cache <NUM> can include the cache memory <NUM> and the cache management circuit <NUM> in <FIG>. Fetched or prefetched instructions from a memory, such as from a main memory <NUM> over a system bus <NUM>, are stored in the instruction cache <NUM>. The instruction processing circuit <NUM> is configured to process instructions fetched into the instruction cache <NUM> and process the instructions for execution. The processor <NUM> can include a register rename map table <NUM> for tracking logical to physical register mapping.

The processor-based system <NUM> can also include a cache memory <NUM>, which may be one or more of the cache memories <NUM>(<NUM>)-<NUM>(X) in <FIG> or the cache memory <NUM> in <FIG>. In this regard, the cache memory <NUM> may also include the cache management circuit <NUM> in <FIG>.

The processor <NUM> and the main memory <NUM> are coupled to the system bus <NUM> and can intercouple peripheral devices included in the processor-based system <NUM>. As is well known, the processor <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the processor <NUM> can communicate bus transaction requests to a memory controller <NUM> in the main memory <NUM> as an example of a slave device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller <NUM> is configured to provide memory access requests to a memory array <NUM> in the main memory <NUM>. The memory array <NUM> is comprised of an array of storage bit cells for storing data. The main memory <NUM> may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, static random access memory (SRAM), etc.), as non-limiting examples.

Other devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include the main memory <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, a modem <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem <NUM> can be configured to support any type of communications protocol desired. The processor <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display(s) <NUM> can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

The processor-based system <NUM> in <FIG> may include a set of instructions <NUM> to be executed by the processor <NUM> for any application desired according to the instructions. The instructions <NUM> may be stored in the main memory <NUM>, processor <NUM>, and/or instruction cache <NUM> as examples of a non-transitory computer-readable medium <NUM>. The instructions <NUM> may also reside, completely or at least partially, within the main memory <NUM> and/or within the processor <NUM> during their execution. The instructions <NUM> may further be transmitted or received over the network <NUM> via the modem <NUM>, such that the network <NUM> includes computer-readable medium <NUM>.

While the computer-readable medium <NUM> is shown in an exemplary embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that stores the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the processing device and that causes the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer-readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

The embodiments disclosed herein may be provided as a computer program product, or software, that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, flash memory devices, etc.); and the like.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna systems described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

Claim 1:
A cache management circuit for predictive adjustment of a cache control policy based on persistent cache control information, the cache management circuit configured to:
receive a memory request (<NUM>) comprising a memory address to access data at the memory address;
receive a hit-miss indicator (<NUM>) from a cache memory (<NUM>), the hit-miss indicator (<NUM>) indicating a cache hit in response to the data at the memory address being stored in the cache memory (<NUM>) and indicating a cache miss in response to the data at the memory address not being stored in the cache memory (<NUM>);
generate cache control information (<NUM>) corresponding to the memory address based on the hit-miss indicator (<NUM>) and the cache control policy;
store the cache control information (<NUM>) corresponding to the memory address persistently, independent of the data being evicted from the cache memory (<NUM>); and
control generation of a retention rank (<NUM>) of a cache line (<NUM>) based on the stored cache control information (<NUM>),
wherein the cache management circuit comprises a predictor table comprising a plurality of entries for storing the cache control information, each entry corresponding to a memory address, the cache management circuit further configured to store the cache control information in an entry in the predictor table corresponding to the memory address in the memory request; and
wherein the cache management circuit comprises a replacement likelihood history (RLH) circuit configured to store an RHL pattern comprising retention ranks of cache lines in the cache memory accessed in consecutive memory requests, the cache management circuit configured to:
record an RLH pattern corresponding to the received memory request;
generate a hash of the RLH pattern and the memory address of the memory request; and
store the cache control information in the entry of the predictor table corresponding to the memory address of the memory request, the entry comprising an index matching the hash.