Patent Description:
For clock generation circuit, a difficult task is how to form a phase locked loop (PLL) with ultra-large multiplier factor to generate high-frequency clock signal. In conventional clock circuit with PLL designs, the frequency multiplier/divide factor is basically set at <NUM>/<NUM>/<NUM>/<NUM>. Very few designs are based on complex cascading algorithms to set the frequency multiplier factor to be about <NUM>. Basically, as the frequency multiplier/divide factor is increased, jitter in the output of the PLL of the conventional clock circuit becomes larger and larger, quickly degrading the quality of the clock signal. In general, the jitter in a clock signal cannot exceed <NUM>% of the clock period, substantially limiting options of obtaining an ultra-large frequency multiplier/divider factor through the PLL design. Therefore, improved digital clock circuit is desired. Document "<NPL>, discloses a full digital fractional-N TAF-FLL for digital applications. Document "<NPL>, discloses a <NUM> Ppb/Step wide range DCXO based on time-average-frequency. Document "<NPL>, discloses a PVT tolerant <NUM> to <NUM> all-digital phase-locked loop with coupled TDC and DCO. Document "<NPL>, discloses <NUM> series FPGAs clocking resources.

The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

Conventional clock circuit based on phase locked loop (PLL) design has limitation in setting its frequency multiplier/divider factor no more than about <NUM> due to large jitters in the clock signals. Most clock circuits relied on a crystal oscillator or the like to provide an input clock signal, which requires high power consumption and large chip area for generating high-ratio frequency multiplication clock signal, and is hard to be integrated in chips.

Accordingly, the present disclosure provides, inter alia, a digital clock circuit for generating high-ratio frequency multiplication clock signal, an IC chip having the same, and a method thereof that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

In one aspect, the present disclosure provides a digital clock circuit based on free-running oscillation to generate high-ratio frequency multiplication clock signal. <FIG> shows a block diagram of a digital clock circuit for generating high-ratio frequency multiplication clock signal according to some embodiments of the present disclosure. Referring to <FIG>, the digital clock circuit is mainly formed with two parts. A first sub-circuit <NUM> contains a first digitally-controlled oscillator <NUM>. The first digitally-controlled oscillator <NUM> is configured to generate and output a high-frequency clock signal based on an oscillation signal from a free-running oscillation generator, and the first sub-circuit <NUM> is configured to supply a M-divided frequency signal to the second sub-circuit <NUM>. A second sub-circuit <NUM> includes a time-average-frequency frequency-locked loop (FLL) configured to receive a low-frequency input signal and use the loop of feedback to determine a frequency control word F to control a second digitally-controlled oscillator <NUM> to obtain a synthesized clock signal based on the M-divided frequency signal and to supply a N-divided frequency signal as a feedback signal in the FLL loop. The frequency control word F also is used to control the first digitally-controlled oscillator in the first sub-circuit <NUM>.

Referring to <FIG>, in particular, the first sub-circuit <NUM> includes a free-running oscillator <NUM> to generate a free-running oscillation frequency. The first sub-circuit <NUM> also includes a first digitally-controlled oscillator <NUM> having a control port <NUM> for receiving a control signal, multiple input ports <NUM> for receiving multiple input pulses, an output port <NUM> for outputting a first output signal, and being configured to be a high-frequency direct period synthesizer.

The free-running oscillator <NUM>, in an embodiment, uses a logic circuit based on cascaded NAND-gate units to realize generation of the free-running oscillation frequency without using any voltage pulse source or crystal oscillator. <FIG> shows a circuit diagram of a free-running multi-stage cascaded NAND-Gate oscillator according to an embodiment of the present disclosure. Referring to <FIG>, the circuit is constructed, as an example, by cross cascading <NUM>-stage of NAND-Gate units (P0, P1,. , through P15). Each stage includes a pair of NAND-Gate units. The whole oscillator circuit is configured to generate oscillations based on all noises and functional as a filter to gradually allow all oscillations to be stabilized at a fixed frequency value in a final equilibrium state. Additionally, each NAND-Gate unit (of all <NUM> units in <FIG>) is configured to output one periodic pulse with the same oscillation frequency but with a shifted phase that is equal to <NUM>/<NUM> of the period (of these pulses).

Assuming the phase shift is Δ for any two nearest neighboring NAND-Gate units of a K/<NUM>-stage cascaded structure in the free-running oscillator <NUM>, then K number of pulses with a first frequency f<NUM> is generated, as shown in an exemplary diagram of <FIG>. The first frequency f<NUM> is mainly depended on manufacture process of the NAND-gate unit in the free-running oscillator <NUM>. Optionally, the first frequency f1 is provided as an ultra-high frequency in a range as high as <NUM>. In particular, each NAND-Gate unit introduces one phase delay of Δ. Referring to <FIG>, in an example, K = Kh, Δ = Δh, the free-running oscillator <NUM> generates Kh number of first pulses of the first frequency f<NUM> with equally spaced phase shift of Δh. These Kh number of first pulses are provided to the input ports <NUM> of the first digitally-controlled oscillator <NUM>.

Referring to <FIG> again, in an embodiment, the first digitally-controlled oscillator <NUM> is provided as a time-average-frequency direct period synthesizer configured to use a control signal received from the control port <NUM>, which is a frequency control word Fh, to control a first output frequency of a synthesized periodic signal outputted to the output port <NUM> based on input of the Kh number of first pulses received via the input ports <NUM> from the free-running oscillator <NUM>. <FIG> shows a functional diagram of a logic circuit of the time-average frequency direct period synthesizer. The Kh number of first pulses are generated by the free-running oscillator <NUM> having evenly-spaced phase shift Δh in a first frequency f<NUM>, an ultra-high frequency.

Starting from the Kh number of first pulses with evenly-spaced phase shift Δh and a frequency control word Fh = I + r where I is an integer and r is a fraction of <NUM> < r <<NUM>, the time-average frequency direct period synthesizer associated with the first digitally-controlled oscillator <NUM> creates two types of cycles TA = I·Δh and TB = (I + <NUM>)·Δh in respective two timeframes. It then generates the output pulse train by using TA and TB in an interleaved fashion. The possibility of TA (and thus TB) occurrence is controlled by the value of r. The output frequency fTAF /period TTAF can be calculated by <NUM>/fTAF = TTAF = Fh·Δh. Given enough resource (the number of bits used in r), almost any frequency can be generated. Further, the output signal waveform can be instantly changed since each individual first pulse is directly constructed.

The Kh first pulses are inputted respectively to two K-to-<NUM> multiplexers. Here (<FIG>), K = Kh. A first K-to-<NUM> multiplexer (MUX_A) at a lower half of the figure is coupled to a <NUM>-pipeline register controlled by the frequency control word Fh via an accumulator to allow the Kh first pulses to pass through a lower path to be a first output MUXOUT_A. Here (<FIG>), F = Fh.

At a transition time t6, the accumulator associated with the lower path performs accumulation computation every rising edge of clock to handle that the frequency control word Fh is a real number including a fraction part r beyond an integer part I. The lower path K-to-<NUM> multiplexer dominates the length of logic '<NUM>' of output CLK1 at a low voltage level. At a first transition time t1, the SEL_LOW is fed into the first (or lower) K-to-<NUM> multiplexer MUX_A at a rising edge of CLK2. So, it will choose one pulse of the Kh first pulses to be the first output MUXOUT_A.

A second K-to-<NUM> multiplexer (MUX_B) is coupled to a <NUM>-pipeline register controlled by the half frequency control word Fh/<NUM> via an adder to input the Kh first pulses through an upper path for generating a high level of a second output MUXOUT_B. The adder associated with the upper path only is driven by the integer part I of the frequency control word Fh. The K-to-<NUM> multiplexer MUX_B in the upper path dominates the length of logic '<NUM>' of output CLK1 at a high voltage level.

Referring to <FIG>, additionally, a <NUM>-to-<NUM> multiplexer MUX_C controlled by CLK1 to control the transition of upper path and lower path. Now only one signal, from either upper path or lower path, arrives at a toggle flip-flop circuit which includes a D-type flip-flop and two inverters to toggle the output MUXOUT at every rising edge of clock, from '<NUM>' to '<NUM>' or from '<NUM>' to '<NUM>'.

At a second transition time t2, the chosen signal passes the first K-to-<NUM> multiplexer MUX_A and is fed into the <NUM>-to-<NUM> multiplexer MUX_C.

At a third transition time t3, which occurs simultaneously with t2, when CLK2 is at the state of logic '<NUM>' after rising edge, the CLK1 is at the state of logic '<NUM>'. So, the <NUM>-to-<NUM> multiplexer MUX_C chooses the second output MUXOUT_B from the upper path as MUXOUT sent to the toggle flip-flop.

At a fourth transition time t4, the rising edge of the second output MUXOUT_B arrives at the toggle flip-flop which finishes the transition from <NUM> to <NUM>.

At a fifth transition time t5, CLK1 now is transited to <NUM>. So the <NUM>-to-<NUM> multiplexer MUX_C chooses the first output MUXOUT_A of the lower path to send to the toggle flip-flop. The whole process repeats itself.

Therefore, the frequency control word Fh is employed by the first digitally-controller oscillator <NUM> select one pulse from the Kh first pulses as a first periodic signal with a first output frequency fh = Kh·f<NUM>/Fh = <NUM>/(Fh·Δh) at the output port <NUM>.

Referring back to <FIG>, the first sub-circuit <NUM> also includes a first frequency divider <NUM> coupled to the output port <NUM> to receive the first periodic signal with the first output frequency fh. In an embodiment, the first frequency divider is a divider with a divide factor of M, M being an integer. Optionally, the first frequency divider <NUM> is a high-frequency divider and is configured to use L-stage cascaded Toggle Flip-Flop circuit to divide the frequency stage-by-stage digitally. This type of frequency divider introduces very low noise even it works in high-frequency range as high as <NUM>. <FIG> shows a schematic diagram of the L-stage Toggle Flip-Flop (TFF) circuit cascaded in series. Each TFF stage has an input port and an output port. A first TFF stage has an input receiving the first output frequency fh from the output port <NUM> of the first digitally-controller oscillator <NUM>. When a signal passes a respective one stage, the frequency at its output port is reduced to a half of that at its input port. The last (L-th) TFF stage has an output port that outputs finally a M-divided signal having <NUM>/M = <NUM>/<NUM>L of original input frequency, i.e., fh/M.

Optionally, the M-divided signal is served as a trigger signal for inducing additional oscillation pulses. In an embodiment, referring further to <FIG>, the first sub-circuit <NUM> further includes a trigger oscillator <NUM> driven by the trigger signal to generate multiple second pulses of a second frequency with equally spaced phase shift. <FIG> shows an example of the trigger oscillator configured as a Kl/<NUM>-stage Johnson counter according to an embodiment of the present disclosure. The Kl/<NUM>-stage Johnson counter includes Kl/<NUM>-stage D-type flip-flops cascaded in series, each flip-flop stage has a clock input port receiving the trigger signal and a Q-output port outputting a pulse Pi and respectively a Qn-output port outputting a another pulse PKl/<NUM>+i. For the Kl/<NUM>-stage Johnson counter, all Q output ports sequentially output Kl/<NUM> number of pulses P<NUM>, P<NUM>, P<NUM>, up to PKl/<NUM>, all Qn-output ports sequentially output Kl/<NUM> number of pulses PKl/<NUM>+<NUM>, PKl/<NUM>+<NUM>, PKl/<NUM>+<NUM>, up to PKl. Functionally, the trigger oscillator <NUM> is substantially similar to the free-running oscillator <NUM> except that the trigger oscillator <NUM> needs the trigger signal inputted into the clock input port for generating Kl number of second pulses of a second frequency f<NUM> with equally-spaced phase shift Δl, where Kl·f<NUM> = <NUM>/Δl. In an embodiment, Kl·f<NUM> = fh/M, these Kl number of second pulses are ready to be loaded into a second digitally-controlled oscillator <NUM> in the second sub-circuit <NUM> configured as a frequency locked loop of feedback.

Referring to <FIG> again, the second sub-circuit <NUM> includes a frequency detector (FD) <NUM> having a first input port receiving an input signal with an input frequency fi and a second input port receiving a feedback signal with a feedback frequency fb. The frequency detector (FD) <NUM> serves as a first element in the FLL loop of feedback and is configured to compare the input frequency with the feedback frequency and output control signals based on comparison results about the input frequency fi with the feedback frequency fb.

In an embodiment, the frequency detector <NUM> is configured to compare the input frequency fi with the feedback frequency fb to generate a first control signal fast and a second control signal slow alternately for determining a frequency control word F in the FLL loop of feedback. <FIG> shows a schematic diagram of a logic circuit of the frequency detector according to an embodiment of the present disclosure. Referring to <FIG>, the frequency detector <NUM> includes a first input port receiving a first signal of f<NUM>, which can be the input signal of fi in <FIG>, a second input port receiving a second signal of f<NUM>, which can be the feedback signal of fb in <FIG>. Additionally, the frequency detector <NUM> includes a trigger sub-circuit <NUM> coupled to the first input port and the second input port and configured to detect a relationship between the first frequency f<NUM> and the second frequency f<NUM>. The frequency detector <NUM> further includes a combined logic sub-circuit <NUM> coupled to the trigger sub-circuit <NUM> to generate the first control signal fast to a first control port in a first timeframe and the second control signal slow to a second control port in a second timeframe. The first timeframe and second timeframe alternately appear one after other.

In an embodiment, the trigger sub-circuit <NUM> includes four D-type flip-flops coupled to the first input port via a frequency-divider and to the second input port partially via an inverter. The trigger sub-circuit <NUM> is configured to determine the first frequency f<NUM> being greater or smaller than the second frequency f<NUM>. The combined logic sub-circuit <NUM> includes two XOR gates, two inverters, and two AND gates configured to output either the first control signal fast to the first control port in the first timeframe based on determination that the first frequency f<NUM> is greater than the second frequency f<NUM> or the second control signal slow to the second control port in the second timeframe based on determination that the first frequency f<NUM> is smaller than the second frequency f<NUM>.

Additionally, the second sub-circuit <NUM> includes a controller <NUM> coupled to the frequency detector <NUM> to receive the first/second control signals. In the embodiment, the first control signal fast drives the controller <NUM> to reduce a frequency control word F by one and the second control signal slow drives the controller <NUM> to increase the frequency control word F by one in each loop operation. In case, no control signal is received from the frequency detector <NUM>, the controller <NUM> is configured to maintain the frequency control word F without change. Eventually, the whole loop of feedback can reach a dynamic equilibrium as the first control signal fast and the second control signal slow are alternately generated and the frequency control word F is switched between I and I+<NUM>. In this equilibrium state, the second frequency f<NUM> is substantially locked to the first frequency f<NUM>. When input frequency changes, i.e., the locking target is changed, the frequency detector <NUM> is operated to determine the frequency control word F which is used to accomplish the frequency locking in the loop of feedback associated with the second sub-circuit <NUM> of the digital clock circuit and also is used to drive the first digitally-controlled oscillator.

Furthermore, referring to <FIG>, the second sub-circuit <NUM> includes a second digitally-controlled oscillator <NUM> coupled to the controller <NUM> to receive a frequency control word Fl to drive a pulse selection from the Kl number of second pulses of a second frequency f<NUM> with equally spaced phase shift Δl received from the trigger oscillator <NUM> of the first sub-circuit <NUM>. The second digitally-controlled oscillator <NUM> is configured also as a time-average frequency direct period synthesizer substantially similar to the first digitally-controlled oscillator <NUM>. It has been illustrated in <FIG> and descriptions in associated paragraphs above. A difference is that the second digitally-controlled oscillator <NUM> is working at a relatively lower frequency as the second frequency f<NUM> is <NUM>/M of the first output frequency fh of the first digitally-controlled oscillator <NUM>. Here, M is selected as a large integer. For example, M = <NUM>. And, Kl is different from Kh and Δl is different from Δh. Another difference is that the frequency control word Fl of the second digitally-controlled oscillator <NUM> can be selected to be the frequency control word F (determined by the controller <NUM>) plus a constant C, i.e., Fl = F + C. Here the constant C is selected as a large integer, e.g., C = <NUM>. The second digitally-controlled oscillator <NUM> is configured to generate and output a second periodic signal with a second output frequency fl, substantially represented by fl = Kl·f<NUM>/Fl, based on time-average frequency direct period synthesis (in the loop of feedback).

Moreover, the second sub-circuit <NUM> includes a second frequency divider <NUM> coupled to the second digitally-controlled oscillator <NUM> to receive the second periodic signal of the second output frequency fl and divide it to <NUM>/N, where N is a divider factor. The second frequency divider <NUM> is configured to be substantially similar to the first frequency divider <NUM>. Optionally, it can be implemented with multi-stage digital counter or multiple delay-lines to generate the divider factor N. In order to make the time-average-frequency frequency-lock loop of the second sub-circuit <NUM> to lock the frequency faster, the divider factor N is selected to be an integer smaller than the integer M (the divider factor of the first frequency divider). For example, M = <NUM>, N = <NUM>. The output of the second frequency divider <NUM> is directly fed as the feedback frequency fb = fl/N back to the frequency detector <NUM> (see <FIG>).

When the loop of feedback through the time-average frequency direct period synthesizer associated with the second digitally-controlled oscillator <NUM> controlled by the control word Fl = F + C reaches a dynamic equilibrium, the feedback frequency fb is substantially locked with the input frequency fi. Because fb = fl/N, fl = fh/(M·Fl), therefore, a relationship of the first output frequency fh and the input frequency fi is obtained: <MAT>.

R is a multiplication ratio of the output frequency over the input frequency and is comprised of a product of three multipliers, divider factor M, divider factor N, and Fl. In particular, M > N, and the frequency control word Fl of the second digitally-controlled oscillator <NUM> is given by the control word F generated by the controller <NUM> plus a large constant C. For example, M = <NUM>, N = <NUM>, Fl = <NUM>, the multiplication ratio R equals <NUM>. In other words, the digital clock circuit of the present disclosure can turn an input pulse of a low frequency at <NUM> to a clock signal of an ultra-high frequency at <NUM>.

In another embodiment of the present disclosure, referring to <FIG>, the controller <NUM> is configured to supply the frequency control word F to both the first digitally-controlled oscillator <NUM> in the first sub-circuit <NUM> and the second digitally-controlled oscillator <NUM> in the second sub-circuit <NUM>. In other words, both the frequency control word Fh supplied to the first digitally-controlled oscillator <NUM> and the frequency control word Fl supplied to the second digitally-controlled oscillator <NUM> can be drawn from the frequency control word F generated by the controller <NUM>. Optionally, Fh = F, and Fl = F + C, here C is an integer substantially larger than F. Optionally, Fh is selected to be the least significant bit of Fl. For example, Fl is an <NUM>-bit control word, 1xxx-<NUM>. Fh is a <NUM>-bit control word, <NUM>. Fl can be expressed as Fh + <NUM>.

In the embodiment, the time-average-frequency locked loop (FLL) of feedback using the frequency control word F plus a substantially larger contact C to drive the second digitally-controlled oscillator <NUM> in the second sub-circuit is designed to enhance clock signal accuracy. In the FLL loop of feedback, the second output frequency fl is determined by a time-average frequency between two cycle frequencies fl1 and fl2 respectively associated with the frequency control word F at the dynamic equilibrium, i.e., fl = (<NUM> - r) · fl1 + r · fl2, where r is a weight of fl1 and fl2. For a nominal value F, fl1 and fl2 are very dissimilar. For example, fl1 = <NUM> and fl2 = <NUM>. In the embodiment with F+C used for driving the second digitally-controlled oscillator <NUM> in the loop of feedback, e.g., F = <NUM>, C = <NUM>, then, fl1 and fl2 become less dissimilar to each other. For example, fl1 = <NUM> and fl2 = <NUM>. Then the time-average frequency fl has a reduced error in this case. The accuracy of the (first) output frequency fh is relied on the accuracy of the (second) output frequency fl in the loop of feedback. Therefore, the outputted clock signal with the frequency fh can achieve an enhanced accuracy.

<FIG> shows a plot showing relationships between input/output frequencies and a frequency control word according to an embodiment of the present disclosure. Referring to <FIG>, it shows that a relationship between the input frequency and the output frequency versus the frequency control word F (with fixed divider factor M and N) is a monotonous relationship. When the frequency control word F has a large value, the relationship is substantially linear. Therefore, the output signal with the high-ratio multiplication frequency over the input frequency can be used as a high-frequency clock signal. In a specific experiment, an input signal of a frequency at <NUM> is loaded into a clock circuit implemented in a FPGA chip on a circuit board and measured by Keysight 53230A Frequency Meter, the output frequency obtained is <NUM> with a multiplication ratio R as large as <NUM>. In general, depending on selection of the divider factor M, N, and the frequency control word F plus the constant C for designing the digital clock circuit, the multiplication ratio R of the digital clock circuit of the present disclosure is at least greater than <NUM>, or greater than <NUM>, or greater than <NUM>, or greater than <NUM>, or greater than <NUM>, or greater than <NUM>, or greater than <NUM>.

In a specific embodiment, the present disclosure provides a digital clock generator for generating a high-ratio frequency multiplication clock signal. The digital clock generator includes a frequency detector configured to compare an input signal of an input frequency received from an input port with a feedback signal of a feedback frequency from a loop of feedback to generate control signals. The digital clock generator further includes a controller coupled to the frequency detector to adjust a frequency control word F in the loop of feedback based on the control signals. Additionally, the digital clock generator includes a first digitally-controlled oscillator coupled to the controller and a first oscillation generator to receive multiple first pulses of a first frequency with equally spaced phase shift, and configured to generate a first synthesized signal to an output port with a first output frequency controlled by the frequency control word F. The digital clock generator further includes a first frequency divider coupled to the output port to generate a trigger signal with <NUM>/M of the first output frequency. Furthermore, the digital clock generator includes a second oscillation generator induced by the trigger signal to generate multiple second pulses of a second frequency with equally spaced phase shift. The digital clock generator further includes a second digitally-controlled oscillator coupled to the controller and the second oscillation generator, and configured to generate a second synthesized signal to the loop of feedback with a second output frequency controlled by the frequency control word F plus a constant C. Moreover, the digital clock generator includes a second frequency divider in the loop of feedback to generate the feedback signal with the feedback frequency being <NUM>/N of the second output frequency. The loop of feedback makes the feedback frequency locked to the input frequency so as to make the first output frequency substantially linearly dependent on the input frequency multiplied by M·N·(F+C). The first synthesized signal is outputted as a clock signal with a high-ratio multiplication clock frequency over the input frequency.

In another aspect, the present disclosure provides a chip for generating high-ratio frequency multiplication clock signal comprising a digital clock circuit described herein. The digital clock circuit is based on pure digital circuity design with high efficiency and free-running oscillation generation architecture to achieve high-ratio multiplication clock frequency. The chip can be implemented in a FPGA or ASIC digital integrated circuit for various electronic applications.

In yet another aspect, the present disclosure provides a method for generating high-ratio frequency multiplication clock signal from a low-frequency input signal. The method includes a step of comparing a low-frequency input signal with a feedback signal in a loop of feedback to generate control signals. The method further includes a step of generating a frequency control word based on the control signals. Additionally, the method includes a step of using at least a least significant bit of the frequency control word F to drive a first digitally-controlled oscillator to generate a first synthesized signal of a first output frequency based on multiple first periodic pulses with equally spaced phase shift. The method further includes a step of dividing the first output frequency by M to obtain a trigger signal with <NUM>/M of the first output frequency. Furthermore, the method includes a step of using the frequency control word F plus a constant C to drive a second digitally-controlled oscillator to generate a second synthesized signal of a second output frequency based on multiple second periodic pulses with equally spaced phase shift induced by the trigger signal. The method further includes a step of dividing the second output frequency by N to obtain a feedback frequency with <NUM>/N of the second output frequency in the loop of feedback. Moreover, the method includes a step of outputting the first synthesized signal as a clock signal with the first output frequency being substantially linearly dependent on an input frequency of the low-frequency input signal multiplied by M·N·(F+C).

Further in the embodiment, the method also includes a step of using a digital free-running oscillator to generate the multiple first periodic pulses of a first frequency from random noise without any external clock signal.

Additionally in the embodiment, the method includes a step of using a Johnson counter to generate the multiple second periodic pulses of a second frequency equal to <NUM>/M of the first output frequency induced by the trigger signal.

Moreover, in the embodiment of executing the method, the constant C is selected to be substantially larger than the frequency control word F as the loop of feedback reaches a dynamic equilibrium with the frequency control word F being switched between I and I+<NUM>.

Claim 1:
A digital clock circuit for generating high-ratio frequency multiplication clock signal, wherein the digital clock circuit comprises:
a first sub-circuit (<NUM>) comprising a first digitally-controlled oscillator (<NUM>) configured to be driven by a frequency control word F
to control a first output frequency of a first periodic signal synthesized from multiple first pulses, and a first frequency divider (<NUM>) configured to generate a trigger signal having a frequency equal to <NUM>/M of the first output frequency;
a second sub-circuit (<NUM>) comprising a feedback loop including a frequency detector (<NUM>) configured to compare an input frequency with a feedback frequency, a controller configured to adjust the frequency control word F based on an output of the frequency detector (<NUM>), a second digitally-controlled oscillator (<NUM>) configured to be driven by the frequency control word F plus a constant C to control a second output frequency of a second periodic signal synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider configured to set the feedback frequency equal to <NUM>/N of the second output frequency in the feedback loop;
wherein the first output frequency is substantially higher than the input frequency by a few orders of magnitudes;
wherein said first and second digitally-controlled oscillators are of the type time-average frequency direct period synthesizer, TAF-DPS; and
wherein the first sub-circuit (<NUM>) further comprises a free-running ring oscillator (<NUM>) configured to generate oscillations based on noise and output the multiple first pulses having a first frequency with equally spaced phase shift Δh, Δh being the base time unit for the first digitally-controlled oscillator; and
wherein the trigger oscillator (<NUM>) driven by the trigger signal, comprises a Ki/<NUM>-stage Johnson counter configured to output Ki number of second pulses with equally spaced phase shift of <NUM>/Ki of a second period given by inverse of <NUM>/M of the first output frequency, said second pulses with equally spaced phase shift Δl, Δl being the base time unit for the second digitally-controlled oscillator; and
wherein the first output frequency is substantially equal to the input frequency multiplied by M.N.(F+C).