Patent Description:
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area.

Integrated circuits often include configuration memory bits that enable the customization of functional blocks by programming the configuration memory bits with configuration data. An increase in size of the integrated circuit often leads to an increase in the size of the functional blocks and thus to an increase in the amount of configuration data. Since the configuration data is often stored in a storage circuit, bigger storage circuits are required to store the increased amount of configuration data.

The problem of having increased amounts of configuration data is aggravated by partial reconfiguration that has recently emerged as a way of implementing multiple different circuit designs in the same partition of an integrated circuit at different times. Consider the example in which an integrated circuit partition includes configuration memory bits. A first configuration data set programs these configuration memory bits to implement a first circuit design; and the first circuit design implementation is operating on the integrated circuit partition during a first duration of time.

After the first duration of time, the configuration memory bits on the integrated circuit partition are reprogrammed using a second configuration data set. Thus, the first circuit design implementation is replaced by a second circuit implementation, and the second circuit design implementation operates on the integrated circuit partition during a second duration of time. In practice, more than two circuit design implementations are often sharing the same integrated circuit partition through partial reconfiguration.

In this example, the amount of configuration data that needs to be stored in the storage circuit significantly increases with each additional circuit design implementation; and the increased memory size requirements can have a significant impact on the cost of operating the integrated circuit.

<NPL> propose a self-reconfigurable platform which can reconfigure the architecture of discrete cosine transform (DCT) computations during run-time using dynamic partial reconfiguration. The scalable architecture of DCT computations can compute different numbers of DCT coefficients in a zig-zag scan order to adapt to different requirements, such as power consumption, hardware resources, and performance. We propose a configuration manager, which is implemented in the embedded processor in order to adaptively control the reconfiguration of scalable DCT architecture during run-time. In addition, we use the Lempel-Ziv-Storer-Szymanski algorithm for compression of the partial bitstreams and on-chip BlockRAM as a cache to reduce latency overhead for loading the partial bitstreams from the off-chip memory for run-time reconfiguration. A hardware module is designed for parallel reconfiguration of the partial bitstreams.

<NPL> presents an alternative approach for dynamic partial self-reconfiguration that enables a field programmable gate array (FPGA) to reconfigure itself at run-time partially through a parallel configuration access port (cPCAP) under the control of the stand alone cPCAP core within the FPGA instead of using an embedded processor.

The master thesis of <NPL>) studies different image processing applications to select suitable candidates that benefit if implemented on reconfigurable architectures using runtime partial reconfiguration. In this context, the author also notes the availability of difference based partial reconfiguration of a FPGA.

Advantageous embodiments of the invention are defined in the dependent claims and are outlined herein below.

Configuration circuitry for efficiently managing configuration data is presented. The configuration circuitry may include a decoding circuit, which may include first and second circuits. The decoding circuit may receive a base configuration data set and a first data set. The first circuit may receive the first data set, which may include compressed data differences between the base configuration data set and a decoded configuration data set. If desired, the first circuit may decompress the received first data set to create a second data set. The second circuit may receive the base configuration data set and the second data set from circuit design on the configurable circuit. If desired, the first circuit may receive a third data set that includes other compressed data differences between the base configuration data set and an additional decoded configuration data set. The first circuit may decompress the received third data set to create a fourth data set.

In some embodiments, the second circuit may receive the base configuration data set and the fourth data set from the first circuit. If desired, the second circuit may restore the additional decoded configuration data set using the base configuration data set and the fourth data set.

Further features of the invention, its nature and various advantages, will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.

The present embodiments relate to integrated circuits and, more particularly, to efficiently managing configuration data that determine the implementation of circuit designs in an integrated circuit.

As mentioned above, in the Background section, bigger storage circuits may be required to store the increased amount of configuration data that is used to program configuration memory bits in an integrated circuit. The increased amount of configuration data may stem from an increase in transistor density (i.e., the number of transistors per unit of area) in integrated circuits and/or the use of partial reconfiguration that has recently emerged as a way of implementing multiple different circuit designs in the same partition of an integrated circuit at different times.

The increased amount of configuration data that requires the use of bigger storage circuits may have a significant impact on the cost of operating the integrated circuit. Therefore, it may be desirable to more efficiently manage the configuration data that is used to program configuration memory bits without affecting the functionality of the integrated circuit.

It will be obvious to one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

Embodiments relate to methods for using computer-aided design (CAD) tools, which are sometimes also referred to as design automation (DA) tools or electronic design automation (EDA) tools, for optimizing circuit designs represented by configuration memory bits for implementation in integrated circuits. The integrated circuits may be any suitable type of integrated circuit, such as microprocessors, application-specific integrated circuits, digital signal processors, memory circuits, etc. If desired, the integrated circuits may be programmable. In other words, at least a portion of such an integrated circuit may be configured by a user to perform the functionality described in the circuit design using programmable circuitry. The programmable circuitry can be configured by adjusting the settings of configuration memory elements.

An illustrative embodiment of an integrated circuit such as a programmable logic device <NUM> in accordance with the present invention is shown in <FIG>.

Programmable logic device <NUM> has input/output circuitry <NUM> for driving signals off of device <NUM> and for receiving signals from other devices via input/output pins <NUM>. Interconnection resources <NUM> such as global and local vertical and horizontal conductive lines and buses may be used to route signals on device <NUM>.

Input/output circuitry <NUM> include conventional input/output circuitry, serial data transceiver circuitry, differential receiver and transmitter circuitry, or other circuitry used to connect one integrated circuit to another integrated circuit.

Interconnection resources <NUM> include conductive lines and programmable connections between respective conductive lines and are therefore sometimes referred to as programmable interconnects <NUM>.

Programmable logic region <NUM> may include programmable components such as digital signal processing circuitry, storage circuitry, arithmetic circuitry, or other combinational and sequential logic circuitry. The programmable logic region <NUM> may be configured to perform a custom logic function. The programmable logic region <NUM> may also include specialized blocks that perform a given application and have limited configurability. For example, the programmable logic region <NUM> may include specialized blocks such as configurable storage blocks, configurable processing blocks, programmable phase-locked loop circuitry, programmable delay-locked loop circuitry, or other specialized blocks with limited configurability. The programmable interconnects <NUM> may also be considered to be a type of programmable logic region <NUM>.

Programmable logic device <NUM> contains programmable memory elements <NUM>. Memory elements <NUM> can be loaded with configuration data (also called programming data) using pins <NUM> and input/output circuitry <NUM>. Once loaded, the memory elements each provide a corresponding static control signal that controls the operation of an associated logic component in programmable logic region <NUM>. In a typical scenario, the outputs of the loaded memory elements <NUM> are applied to the gates of metal-oxide-semiconductor transistors in programmable logic region <NUM> to turn certain transistors on or off and thereby configure the logic in programmable logic region <NUM> and routing paths. Programmable logic circuit elements that may be controlled in this way include parts of multiplexers (e.g., multiplexers used for forming routing paths in programmable interconnects <NUM>), look-up tables, logic arrays, AND, OR, NAND, and NOR logic gates, pass gates, etc..

Memory elements <NUM> may use any suitable volatile and/or non-volatile memory structures such as random-access-memory (RAM) cells, fuses, antifuses, programmable read-only-memory memory cells, mask-programmed and laser-programmed structures, combinations of these structures, etc. Because memory elements <NUM> are loaded with configuration data during programming, memory elements <NUM> are sometimes referred to as configuration memory, configuration memory elements, configuration memory bits, configuration RAM, or programmable memory elements.

The circuitry of device <NUM> may be organized using any suitable architecture. As an example, the logic of programmable logic device <NUM> may be organized in a series of rows and columns of larger programmable logic regions each of which contains multiple smaller logic regions. The smaller regions may be, for example, regions of logic that are sometimes referred to as logic elements (LEs), each containing one or more look-up tables, one or more registers, and programmable multiplexer circuitry. The smaller regions may also be, for example, regions of logic that are sometimes referred to as configurable logic blocks or adaptive logic modules. Each adaptive logic module (ALM) may include a pair of adders, a pair of associated registers and a look-up table or other block of shared combinational logic (i.e., resources from a pair of LEs -- sometimes referred to as adaptive logic elements or ALEs in this context). The larger regions may be, for example, logic array blocks (LABs) containing multiple logic elements or multiple ALMs.

During device programming, configuration data is loaded into device <NUM> that configures the programmable logic regions <NUM> so that their logic resources perform desired logic functions. Circuit design systems may generate configuration data based on a user description of an integrated circuit design.

An illustrative circuit design system <NUM> in accordance with an embodiment is shown in <FIG>. System <NUM> may be based on one or more processors such as personal computers, workstations, etc. The processor(s) may be linked using a network (e.g., a local or wide area network). Memory in these computers or external memory and storage devices such as internal and/or external hard disks may be used to store instructions and data.

Software-based components such as computer-aided design tools <NUM> and databases <NUM> reside on system <NUM>. During operation, executable software such as the software of computer aided design tools <NUM> runs on the processor(s) of system <NUM>. Databases <NUM> are used to store data for the operation of system <NUM>. In general, software and data may be stored on any computer-readable medium (storage) in system <NUM>. Such storage may include computer memory chips, removable and fixed media such as hard disk drives, flash memory, compact discs (CDs), digital versatile discs (DVDs), blu-ray discs (BDs), other optical media, and floppy diskettes, tapes, or any other suitable memory or storage device(s). When the software of system <NUM> is installed, the storage of system <NUM> has instructions and data that cause the computing equipment in system <NUM> to execute various methods (processes). When performing these processes, the computing equipment is configured to implement the functions of the circuit design system.

The computer aided design (CAD) tools <NUM>, some or all of which are sometimes referred to collectively as a CAD tool or an electronic design automation (EDA) tool, may be provided by a single vendor or by multiple vendors. Tools <NUM> may be provided as one or more suites of tools (e.g., a compiler suite for performing tasks associated with implementing a circuit design in a programmable logic device) and/or as one or more separate software components (tools). Database(s) <NUM> may include one or more databases that are accessed only by a particular tool or tools and may include one or more shared databases. Shared databases may be accessed by multiple tools. For example, a first tool may store data for a second tool in a shared database. The second tool may access the shared database to retrieve the data stored by the first tool. This allows one tool to pass information to another tool. Tools may also pass information between each other without storing information in a shared database if desired.

Tool <NUM> may receive any circuit design description. For example, a first circuit design description may be converted into a second integrated circuit design description which can be used to implement an integrated circuit (e.g., a mask set for fabrication of an application specific integrated circuit or a configuration bitstream for a programmable logic device).

Illustrative computer aided design tools <NUM> that may be used in a circuit design system such as circuit design system <NUM> of <FIG> are shown in <FIG>.

The design process may start with the formulation of functional specifications of the integrated circuit design (e.g., a functional or behavioral description of the integrated circuit design). A circuit designer may specify the functional operation of a desired circuit design using design and constraint entry tools <NUM>. Design and constraint entry tools <NUM> may include tools such as design entry aid <NUM> and design editor <NUM>. Design entry aid <NUM> may be used to help a circuit designer locate a desired portion of the design (e.g., an intellectual property (IP) component) from a library of existing circuit designs and may provide computer-aided assistance to the circuit designer for entering (specifying) the desired circuit design.

As an example, design entry aid <NUM> may be used to present screens of options for a user. The user may click on on-screen options to select whether the circuit being designed should have certain features. Design editor <NUM> may be used to enter a design (e.g., by entering lines of hardware description language code), may be used to edit a design obtained from a library (e.g., using a design and constraint entry aid), or may assist a user in selecting and editing appropriate prepackaged code/designs.

Design and constraint entry tools <NUM> may allow a circuit designer to provide a desired circuit design using any suitable format. For example, design and constraint entry tools <NUM> may include tools that allow the circuit designer to enter a circuit design using truth tables. Truth tables may be specified using text files or timing diagrams and may be imported from a library. Truth table circuit design and constraint entry may be used for a portion of a large circuit or for an entire circuit.

As another example, design and constraint entry tools <NUM> may include a schematic capture tool. A schematic capture tool may allow the circuit designer to visually construct integrated circuit designs from constituent parts such as logic gates and groups of logic gates. Libraries of preexisting integrated circuit designs may be used to allow a desired portion of a design to be imported with the schematic capture tools.

If desired, design and constraint entry tools <NUM> may allow the circuit designer to provide a circuit design to the circuit design system <NUM> using a hardware description language such as Verilog hardware description language (Verilog HDL) or Very High Speed Integrated Circuit Hardware Description Language (VHDL). The designer of the integrated circuit design can enter the circuit design by writing hardware description language code with editor <NUM>. Blocks of code may be imported from user-maintained or commercial libraries if desired.

After the design has been entered using design and constraint entry tools <NUM>, behavioral simulation tools <NUM> may be used to simulate the functional performance of the circuit design. If the functional performance of the design is incomplete or incorrect, the circuit designer can make changes to the circuit design using design and constraint entry tools <NUM>. The functional operation of the new circuit design may be verified using behavioral simulation tools <NUM> before synthesis operations have been performed using tools <NUM>. Simulation tools such as behavioral simulation tools <NUM> may also be used at other stages in the design flow if desired (e.g., after logic synthesis). The output of the behavioral simulation tools <NUM> may be provided to the circuit designer in any suitable format (e.g., truth tables, timing diagrams, etc.).

Once the functional operation of the circuit design has been determined to be satisfactory, logic synthesis and optimization tools <NUM> may generate a gate-level netlist of the circuit design, for example using gates from a particular library pertaining to a targeted process supported by a foundry, which has been selected to produce the integrated circuit. Alternatively, logic synthesis and optimization tools <NUM> may generate a gate-level netlist of the circuit design using gates of a targeted programmable logic device (i.e., in the logic and interconnect resources of a particular programmable logic device product or product family).

Logic synthesis and optimization tools <NUM> may optimize the design by making appropriate selections of hardware to implement different logic functions in the circuit design based on the circuit design data and constraint data entered by the logic designer using tools <NUM>.

After logic synthesis and optimization using tools <NUM>, the circuit design system may use tools such as placement and routing tools <NUM> to perform physical design steps (layout synthesis operations). Placement and routing tools <NUM> are used to determine where to place each gate of the gate-level netlist produced by tools <NUM>. For example, if two counters interact with each other, the placement and routing tools <NUM> may locate these counters in adjacent regions to reduce interconnect delays or to satisfy timing requirements specifying the maximum permitted interconnect delay. The placement and routing tools <NUM> create orderly and efficient implementations of circuit designs for any targeted integrated circuit (e.g., for a given programmable integrated circuit such as a field-programmable gate array (FPGA).

Tools such as tools <NUM> and <NUM> may be part of a compiler suite (e.g., part of a suite of compiler tools provided by a programmable logic device vendor). In accordance with an embodiment, tools such as tools <NUM>, <NUM>, and <NUM> automatically take into account the effects of crosstalk between interconnects while implementing a desired circuit design. Tools <NUM>, <NUM>, and <NUM> may also include timing analysis tools such as timing estimators. This allows tools <NUM> and <NUM> to satisfy performance requirements (e.g., timing requirements) before actually producing the integrated circuit.

After an implementation of the desired circuit design has been generated using placement and routing tools <NUM> the implementation of the design may be analyzed and tested using analysis tools <NUM>. After satisfactory optimization operations have been completed using tools <NUM>, tools <NUM> may produce a mask-level layout description of the integrated circuit and/or configuration data for programming the configuration memory elements on the integrated circuit.

In some embodiments, more than one circuit design may be implemented on the integrated circuit. For example, multiple instances of the same or substantially the same circuit design may be implemented at different locations on the integrated circuit. In other embodiments, variations of a base circuit design may be implemented on the integrated circuit. The example in which different variations of a base circuit design are implemented through the programming of configuration memory bits at a same location on the integrated circuit is also sometimes referred to as reconfiguration or as partial reconfiguration in the event that the reconfiguration is limited to a subset of the configuration memory bits on the integrated circuit.

As an example, consider <FIG> with circuit design A (<NUM>) and circuit design B (<NUM>) as two variations of base circuit design <NUM>. In this example, CAD tools <NUM> (e.g., CAD tools <NUM> of <FIG>) may generate base configuration data <NUM> for base circuit design <NUM>, and CAD tools <NUM> may generate configuration data A (<NUM>) for circuit design A (<NUM>) and configuration data B (<NUM>) for circuit design B(<NUM>), respectively.

In some embodiments, CAD tools <NUM> may perform the same operations as CAD tools <NUM> to generate configuration data A (<NUM>) and configuration data B (<NUM>), respectively. In other embodiments, CAD tools <NUM> may perform incremental operations (e.g., incremental synthesis, incremental placement, incremental routing, etc.) on new or changed components of circuit design A (<NUM>) and circuit design B (<NUM>) compared to base circuit design <NUM>. Incremental compilation may preserve portions of base configuration data <NUM> related to old or unchanged components of circuit design A (<NUM>) and circuit design B (<NUM>) compared to base configuration data <NUM> and generate new configuration data for new or changed components of circuit design A (<NUM>) and circuit design B (<NUM>) compared to base circuit design <NUM>.

Incremental operations are described in commonly assigned <CIT>, <CIT>, <CIT>, and <CIT> and <CIT>.

Encoding circuit <NUM> may receive configuration data A (<NUM>) and base configuration data <NUM>. Encoding circuit <NUM> may include circuitry <NUM> that determines the difference between configuration data A (<NUM>) and base configuration data <NUM> and circuitry <NUM> that compresses the determined difference between configuration data A (<NUM>) and base configuration data <NUM> to produce compressed configuration data A (<NUM>).

An embodiment of encoding circuit <NUM> is shown in <FIG>. As shown in <FIG>, circuitry <NUM> may be implemented by a bit-wise logic exclusive OR (XOR) operation <NUM> between configuration data <NUM> and base configuration data <NUM> to determine the bits that are different. In this example, bits that are different are logic '<NUM>' and bits that are the same are logic '<NUM>'.

If desired, circuitry <NUM> of <FIG> may perform other operations to determine the difference between configuration data A (<NUM>) and base configuration data <NUM>. For example, circuitry <NUM> may perform a subtraction, an addition, a bit-wise logic exclusive NOR (XNOR) operation, etc. of configuration data A (<NUM>) and base configuration data <NUM> to determine their difference.

As shown in <FIG>, encoding circuit <NUM> may include circuitry <NUM> that compresses the result of the difference operation to produce compressed configuration data A (<NUM>). Circuitry <NUM> may implement any lossless data compression technique. Lossless data compression techniques may take advantage of statistical redundancy in data to represent the information that is conveyed by the data with fewer bits, while preserving all the information and thereby ensuring that the compression operation is completely reversible. For example, circuitry <NUM> may implement grammar-based codes such as the Sequitur algorithm, Lempel-Ziv compression methods such as the DEFLATE algorithm. According to embodiments of the invention, circuitry <NUM> implements entropy encoding such as Huffman coding or arithmetic coding, just to name a few.

As shown in <FIG>, circuitry <NUM> performs an entropy encoding operation <NUM>. Entropy encoding operation <NUM> may compress the result of the bit-wise logic exclusive OR (XOR) operation <NUM> of configuration data <NUM> and base configuration data <NUM> and produce compressed configuration data <NUM>.

As an example, consider that entropy encoding operation <NUM> implements Huffman encoding. As with other entropy encodings, Huffman encoding may use fewer bits to represent more common symbols than less common symbols. In the example of using a bit-wise logic exclusive OR operation <NUM> of configuration data <NUM> and base configuration data <NUM>, logic '<NUM>' may be more common than logic '<NUM>' if configuration data <NUM> and base configuration data <NUM> are similar.

Similarly, encoding circuit <NUM> of <FIG> may receive configuration data B (<NUM>) and base configuration data <NUM>. Encoding circuit <NUM> may determine the difference between configuration data B (<NUM>) and base configuration data <NUM> using difference circuitry <NUM>. Encoding circuit <NUM> may further use compression circuitry <NUM> to compress the result of the difference operation to produce compressed configuration data B (<NUM>).

If desired, encoding circuit <NUM> may be implemented as a CAD tool such as CAD tool <NUM> of <FIG> and executed on computing equipment to generate compressed configuration data A (<NUM>) and B (<NUM>) using base configuration data <NUM> and configuration data A (<NUM>) or configuration data B (<NUM>), respectively. In some embodiments, encoding circuit <NUM> may be a dedicated circuit that is located on the integrated circuit or outside the integrated circuit and that performs the encoding of configuration data. In other embodiments, encoding circuit <NUM> may be a configurable circuit that is programed to encode configuration data.

There may be one encoding circuit <NUM> that handles the encoding of different configuration data at different times. If desired, there may be multiple instance of encoding circuit <NUM>, where each instance handles a separate set of configuration data. Alternatively, there may be some instances of encoding circuit <NUM> that handle the encoding of different configuration data at different times, while other instances of encoding circuit <NUM> handle a separate set of configuration data.

One or more storage circuits may store base configuration data <NUM> and compressed configuration data A (<NUM>) and B (<NUM>), respectively. The integrated circuit that implements circuit design A (<NUM>) may include the one or more storage circuits (e.g. in the same die or in the same package). If desired, the one or more storage circuits may be external to the integrated circuit. In some embodiments, the integrated circuit may include at least one storage circuit to store at least a portion of the compressed configuration data, while the remaining storage circuits that store the remainder of the compressed configuration data are located outside the integrated circuit.

For implementing circuit design A in an integrated circuit such as programmable logic device <NUM> of <FIG>, decoding circuit <NUM> of <FIG> may access the one or more storage circuits that store compressed configuration data A (<NUM>) and base configuration data <NUM>. Decoding circuit <NUM> may include circuitry <NUM> that decompresses the compressed configuration data A (<NUM>) and circuitry <NUM> that determines the difference between the decompressed version of compressed configuration data A (<NUM>) and base configuration data <NUM> to restore configuration data A (<NUM>).

Circuitry <NUM> may implement any lossless data decompression technique as long as the selected decompression technique reverses the data compression performed in circuitry <NUM>. As an example, consider the operations shown in <FIG>. As shown in <FIG>, according to embodiments of the invention, circuitry <NUM> performs entropy decoding operation <NUM>. Entropy decoding operation <NUM> decompresses compressed configuration data <NUM>. As an example, consider that entropy encoding operation <NUM> of <FIG> implements Huffman encoding. As a result, entropy decoding <NUM> of <FIG> may implement Huffman decoding.

Circuitry <NUM> of <FIG> may determine the difference between the decompressed configuration data generated by circuitry <NUM> and base configuration data <NUM>. Circuitry <NUM> may implement any difference operation as long as the selected difference operation inverses the difference operation performed in circuitry <NUM>. For example, difference operation <NUM> may perform a subtraction if difference operation <NUM> is an addition, an addition if difference operation <NUM> is a subtraction, a bit-wise logic exclusive NOR (XNOR) operation if difference operation <NUM> is a bit-wise logic exclusive NOR (XNOR) operation, etc..

As shown in <FIG>, circuitry <NUM> may implement a bit-wise logic exclusive OR (XOR) operation <NUM> between the decompressed configuration data generated by entropy decoding <NUM> and base configuration data <NUM> to reverse the bit-wise logic exclusive OR (XOR) operation <NUM> of <FIG> and to restore configuration data <NUM>, which is identical to configuration data <NUM> of <FIG>.

Similarly, decoding circuit <NUM> of <FIG> may receive compressed configuration data B (<NUM>) and base configuration data <NUM>. Decoding circuit <NUM> may use circuitry <NUM> to decompress the compressed configuration data B (<NUM>). Decoding circuit <NUM> may determine the difference between the result of the decompression operation <NUM> and base configuration data <NUM> using circuitry <NUM> to restore configuration data B (<NUM>).

Consider the scenario in which circuit design A and circuit design B implement the same functionality and that configuration data A (<NUM>) differs from configuration data B (<NUM>) in that configuration data A (<NUM>) targets a different location on the integrated circuit than configuration data B (<NUM>). In this scenario, decoding circuit <NUM> may retrieve compressed configuration data A (<NUM>) and compressed configuration data B (<NUM>) from the storage circuit and restore configuration data A (<NUM>) and configuration data B (<NUM>). The restored configuration data A (<NUM>) and B (<NUM>) may then serve to program configuration memory bits on the integrated circuit, thereby implementing circuit designs A (<NUM>) and B (<NUM>), respectively.

In another scenario, circuit designs A (<NUM>) and B (<NUM>) may represent variations of a base circuit design implemented in the framework of partial reconfiguration on the integrated circuit. In other words, circuit designs A (<NUM>) and B (<NUM>) may implement different functionalities, but target the same location on the integrated circuit. In this scenario, decoding circuit <NUM> may retrieve compressed configuration data A (<NUM>) from the storage circuit and restore configuration data A (<NUM>). The restored configuration data A (<NUM>) may then serve to program configuration memory bits at a given location on the integrated circuit, thereby implementing circuit designs A (<NUM>). Circuit design A may operate during a first duration of time.

After the first duration of time, decoding circuit <NUM> may retrieve compressed configuration data B (<NUM>) from the storage circuit and restore configuration data B (<NUM>). The restored configuration data B (<NUM>) may then serve to reprogram the configuration memory bits at the given location on the integrated circuit, thereby implementing circuit designs B (<NUM>). Circuit design B may operate during a second duration of time.

If desired, decoding circuit <NUM> may be implemented as a CAD tool such as CAD tool <NUM> of <FIG> and executed on computing equipment to restore configuration data A (<NUM>) and B (<NUM>) using base configuration data <NUM> and compressed configuration data A (<NUM>) or compressed configuration data B (<NUM>), respectively. In some embodiments, decoding circuit <NUM> may be a dedicated circuit that performs the decoding of compressed configuration data. In other embodiments, decoding circuit <NUM> may be a configurable circuit that is programed to decode configuration data.

There may be one decoding circuit <NUM> that handles the decoding of different compressed configuration data at different times. If desired, there may be multiple instance of decoding circuit <NUM> where each instance handles a separate set of compressed configuration data. Alternatively, there may be some instances of decoding circuit <NUM> that handle the decoding of different compressed configuration data at different times, while other instances of decoding circuit <NUM> handle a separate set of compressed configuration data.

<FIG> is a flow chart of illustrative steps for generating a compressed configuration data set based on a comparison of a variation with a base configuration data set in accordance with an embodiment. During step <NUM>, a CAD tool may generate a base configuration data set for a circuit design. For example, CAD tool <NUM> of <FIG> may generate base configuration data <NUM> of base circuit design <NUM>.

During step <NUM>, the CAD tool may generate a first configuration data set corresponding to a first circuit design that implements the first circuit design at a first location on the integrated circuit. For example, CAD tool <NUM> of <FIG> may generate configuration data A (<NUM>) of circuit design A (<NUM>).

During step <NUM>, the CAD tool may compare the first configuration data set and the base configuration data set to obtain a first configuration data difference set. For example, circuitry <NUM> of <FIG> may determine the difference between configuration data A (<NUM>) and base configuration data <NUM>.

During step <NUM>, the CAD tool may compress the first configuration data difference set to produce a compressed first configuration data difference set. For example, circuitry <NUM> of <FIG> may compress the output of circuitry <NUM> to produce compressed configuration data A (<NUM>).

<FIG> is a flow chart of illustrative steps for generating two compressed configuration data sets and storing those compressed data sets in a storage circuit in accordance with an embodiment of the invention. During step <NUM>, a CAD tool may generate a first configuration data set of a first circuit design. The first configuration data set may implement the first circuit design at a first location on the integrated circuit.

During step <NUM>, the CAD tool may derive a second configuration data set from the first configuration data set. The second configuration data set may include at least a portion that is identical to a portion of the first configuration data set. For example, the second configuration data set may implement the same functionality as the first configuration data set at a different location on the integrated circuit. In this example, the portions of the configuration data in the two configuration data sets that determine the functionality of the circuit design may be identical, while the portions of the configuration data in the two configuration data sets that determine the location of the circuit design implementations on the integrated circuit may be different.

During step <NUM>, the CAD tool may compress the first and second configuration data sets to produce compressed first and second configuration data sets. For example, the CAD tool may use entropy encoding such as Huffman encoding, arithmetic encoding, universal encoding, or Golomb encoding. During step <NUM>, the CAD tool may store the compressed first and second configuration data sets in a storage circuit.

The method and apparatus described herein may be incorporated into any suitable integrated circuit or system of integrated circuits. For example, the method and apparatus may be incorporated into numerous types of devices such as microprocessors or other ICs. Exemplary ICs include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable integrated circuits (EPLDs), electrically erasable programmable integrated circuits (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), just to name a few.

The programmable integrated circuit described herein may be part of a data processing system that includes one or more of the following components; a processor; memory; I/O circuitry; and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or reprogrammable logic is desirable. The programmable integrated circuit can be used to perform a variety of different logic functions. For example, the programmable integrated circuit can be configured as a processor or controller that works in cooperation with a system processor. The programmable integrated circuit may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable integrated circuit can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable integrated circuit may be one of the families of devices owned by the assignee.

Claim 1:
Configuration circuitry comprising:
a decoding circuit (<NUM>) configured to receive a base configuration data set (<NUM>, <NUM>) defining a base circuit design (<NUM>) for a configurable integrated circuit and a compressed first configuration data difference set (<NUM>, <NUM>),
wherein the compressed first configuration data difference set (<NUM>, <NUM>) includes compressed data differences between the base configuration data set (<NUM>, <NUM>) and a first configuration data set (<NUM>, <NUM>) defining a first circuit design (<NUM>) for the configurable integrated circuit and preserving portions of the base configuration data set (<NUM>, <NUM>), and
wherein the decoding circuit (<NUM>) comprises:
a first circuit (<NUM>) configured to receive the compressed first configuration data difference set (<NUM>, <NUM>) and to decompress (<NUM>) the compressed first configuration data difference set (<NUM>, <NUM>) to create a decompressed first configuration data difference set; and
a second circuit (<NUM>) configured to receive the base configuration data set (<NUM>, <NUM>) and the decompressed first configuration data difference set from the first circuit (<NUM>), and configured to perform a bit-wise exclusive OR or exclusive NOR operation (<NUM>) between the base configuration data set (<NUM>, <NUM>) and the decompressed first configuration data difference set to restore the first configuration data set (<NUM>, <NUM>).