Patent Description:
Different from stripe-shaped field plate designs, cell designs with a needle-shaped field plate trench at the center of the cell do not integrate the gate electrode in the field plate trench. Instead, the gate electrode is moved to a separate trench which surrounds the needle-shaped field plate trench in the center of the cell. To reduce the area-specific on-resistance, the gate trench must now form a grid across the chip (die) to use the additional semiconductor mesa area for current conduction.

As such, cell designs with a needle-shaped field plate trench at the center of the cell offer lower area-specific on-resistance and also reduce the output charge of the device which contributes significantly to overall losses in targeted applications. However, conventional cell designs with a needle-shaped field plate trench do not allow for an easy reduction of gate charge and gate-drain charge, as the overall gate area is significantly increased compared to a gate-stripe layout.

Thus, there is a need for a cell design with a needle-shaped field plate trench and lower gate charge and gate-drain charge with reduced impact on area-specific on-resistance.

<CIT> discloses a semiconductor device with needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area. A grid structure separates the transistor sections from each other and includes stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively, gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively, and one or more connection sections of the semiconductor portion.

The one or more connection sections extend between neighboring transistor sections.

<CIT> discloses a semiconductor device with stripe-shaped trench structures and rows of needle-shaped field plate structures extending from the top surface into a semiconductor body.

<CIT> discloses a semiconductor device with trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

<CIT> discloses a semiconductor device with a conductive layer at bottom of a gate trench. A Schottky junction is formed along a side wall of the gate trench by the conductive layer and an n-type current spreading region.

<CIT> discloses a power MOSFET cell includes an N+ silicon substrate having a drain electrode, a low dopant concentration N-type drift layer over the substrate and alternating N and P-type columns are formed over the drift layer with a higher dopant concentration.

<CIT> discloses a semiconductor device with an IGBT section and a freewheeling diode section. And includes an n+ accumulation region between a p-type base region and a n- drift region.

According to the invention, a semiconductor device is provided that comprises the features recited in claim <NUM> or claim <NUM> or claim <NUM> or claim <NUM>.

According to the invention, a method of producing a semiconductor device is provided that comprises the features recited in claim <NUM> or claim <NUM> or claim <NUM>.

The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.

<FIG> illustrate power transistor cells which are not part of the presently claimed invention.

The embodiments described herein provide a power transistor cell design with a needle-shaped field plate trench and lower gate charge and gate-drain charge with reduced impact on area-specific on-resistance. The power transistor device has rows of spicular-shaped field plate structures formed in the semiconductor substrate and stripe-shaped gate structures separating adjacent rows of the spicular-shaped field plate structures. A current spread region is formed in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures. The current spread region is configured to increase channel current distribution in the semiconductor mesas, thereby lowering gate charge and gate-drain charge with little to no adverse impact on area-specific on-resistance. The terms "needle-shaped" and "spicular-shaped" are used interchangeably herein to describe a trench structure formed in a semiconductor substrate and having a small or narrow circumference or width in proportion to its height / depth in the substrate, as opposed to a stripe-shaped trench structure which is longer than it is deeper.

<FIG> illustrates a partial cross-sectional view of a power transistor cell, and <FIG> illustrates a different partial cross-sectional view of the same power transistor cell. A semiconductor device may include dozens, <NUM>, <NUM> or even more of the power transistor cells integrated on the same die and electrically coupled in parallel to form a power transistor. The semiconductor device may be a power MOSFET, an IGBT (insulated gate bipolar transistor), a HEMT (high-electron mobility transistor), etc. In each case, the semiconductor device includes a semiconductor substrate <NUM> comprising a drift region <NUM> of a first conductivity type, a body region <NUM> of a second conductivity type formed above the drift region <NUM>, and a source region <NUM> of the first conductivity type separated from the drift region <NUM> by the body region <NUM>. The drain region <NUM> of the semiconductor device may be disposed at the opposite side of the semiconductor substrate <NUM> as the source region <NUM>. The term "source region" as used herein is intended to mean the source region of a power MOSFET or HEMT, or the emitter region of an IGBT. Similarly, term "drain region" as used herein is intended to mean the drain region of a power MOSFET or HEMT, or the collector region of an IGBT.

In the case of an n-channel device, the first conductivity type is n-type and the second conductivity type is p-type. Conversely in the case of a p-channel device, the first conductivity type is p-type and the second conductivity type is n-type.

For either an n-channel or p-channel device, the semiconductor device includes rows of spicular-shaped field plate structures <NUM> formed in the semiconductor substrate <NUM>. The semiconductor device also includes stripe-shaped gate structures <NUM> formed in the semiconductor substrate <NUM> and separating adjacent rows of the spicular-shaped field plate structures <NUM>. An interlayer dielectric <NUM> such as an oxide, nitride etc. insulates electrical connections to the stripe-shaped gate structures <NUM> from electrical connections to the spicular-shaped field plate structures <NUM>, and a highly doped contact region <NUM> may be provided for electrically contacting the body region <NUM>. As mentioned above, only part of one transistor cell is shown in <FIG>. However, <FIG> show different embodiments of the semiconductor device and in which stripe-shaped gate structures <NUM> separate adjacent rows of spicular-shaped field plate structures <NUM>.

The spicular-shaped field plate structures <NUM> extend through the source region <NUM> and the body region <NUM> into the drift region <NUM>. The main current flow path of the device shown in <FIG> is vertical, from the source region <NUM> to the drain region <NUM> and controlled by a voltage applied to a gate electrode <NUM> of the stripe-shaped gate structures <NUM>. Field plates <NUM> of the spicular-shaped field plate structures <NUM> shape the electric field that builds up in the semiconductor substrate <NUM> when the device is in a blocking state, protecting the gate dielectric <NUM> and enhancing the breakdown characteristics of the device.

The spicular-shaped field plate structures <NUM> each include a field electrode <NUM> disposed in a trench <NUM> and a field dielectric <NUM> insulating the field electrode <NUM> from the semiconductor substrate <NUM>. The stripe-shaped gate structures <NUM> each include a gate electrode <NUM> disposed in a trench <NUM> separate from the field plate trenches <NUM> and a gate dielectric <NUM> insulating the gate electrode <NUM> from the semiconductor substrate <NUM>. The stripe-shaped gate structures <NUM> run along at least two sides of the needle-shaped field plate structures <NUM> (e.g. parallel but not orthogonal), or may even run along all four sides of the needle-shaped field plate structures <NUM> but not in continuous grids. That is, even if the stripe-shaped gate structures <NUM> run along all four sides of the needle-shaped field plate structures <NUM>, there is a break or gap in some of the stripe-shaped gate structures <NUM> such that there are semiconductor mesas <NUM> located between adjacent ones of the spicular-shaped field plate structures <NUM> and which are devoid of the stripe-shaped gate structures <NUM>.

Due to the use of spicular-shaped field plate structures <NUM> and stripe-shaped gate structures <NUM>, the power transistor cell design has lower overall on-resistance. However, not all of the semiconductor material between adjacent spicular-shaped field plate structures <NUM> is influenced by the gate voltage, since the gate trenches <NUM> are formed as stripes and therefore do not completely surround individual ones of the spicular-shaped field plate structures <NUM> as explained above.

To reduce the area-specific on-resistance of the semiconductor device while also lowering the gate charge and gate-drain charge, the device also includes a current spread region <NUM> of the first conductivity type formed below the body region <NUM> in the semiconductor mesas <NUM> located between adjacent ones of the spicular-shaped field plate structures <NUM> and which are devoid of the stripe-shaped gate structures <NUM>. The current spread region <NUM> has a higher average doping concentration than the drift region <NUM>, and therefore increases the channel current distribution in the semiconductor mesas <NUM> which are devoid of the stripe-shaped gate structures <NUM>.

The current spread region <NUM> distributes the channel current in the semiconductor mesas <NUM> into which the gate trenches <NUM> do not extend. By including the current spread region at least in the semiconductor mesas <NUM> located between adjacent ones of the spicular-shaped field plate structures <NUM> and which are devoid of the stripe-shaped gate structures <NUM>, a less resistive region of the first conductivity type is provided just below the body region <NUM> in these mesa regions <NUM>, allowing the channel current to spread out laterally in a more distributed manner as the channel current flows into the upper part of the drift region <NUM> and vertically toward the drain region <NUM>.

<FIG> shows the voltage drop in electron quasi Fermi potential for the cell shown in <FIG> but without the current spread region <NUM>, and <FIG> shows the voltage drop for the cell shown in <FIG> with the current spread region <NUM>. <FIG> demonstrates that the semiconductor device with the current spread region <NUM> has better channel current spreading which yields a lower voltage drop for the device. For example, in some cases, the current spread region <NUM> may improve the area-specific on resistance (RxA) from <NUM> mill-Ohm mm<NUM> down to <NUM> mill-Ohm mm<NUM> or even lower while the breakdown voltage increases slightly. The amount of on-resistance improvement is based on the increase in doping of the current spread region <NUM>. In one embodiment, the current spread region <NUM> has a graded doping profile that increases towards the body region <NUM> for lowering the on-resistance.

However, a practical limitation on the doping concentration of the current spread region <NUM> is set by a corresponding reduction in VFPmax. This requires a careful optimization due to the changed field distribution compared to a device with a continuous gate grid surrounding the field plate structures, resulting in higher breakdown voltage (BVDSS) and VFPmax for the same epitaxial layer stack.

VFPmax is not directly measurable at the device, but can be determined on a test structure where the field electrode <NUM> is separated from the source. With such a test structure, the potential of the field electrode <NUM> can be changed. By varying the potential of the field electrode <NUM>, the blocking capability of the device changes. Therefore, the breakdown voltage may first rise with increasing the field electrode potential, reaching a maximum value which is defined as VFPmax. A further increase of the potential at the field electrode <NUM> results in a fast decline of the breakdown voltage, meaning the characteristic breakdown voltage over VFP is typically asymmetric. To provide a stable device behaviour that is robust against process tolerances, the device may be designed in a way that VFPmax is always positive.

If the field electrode potential is kept constant, e.g., typically at zero Volts as the field electrode <NUM> is connected to source potential, an increase of the doping yields the same behaviour - first a rising breakdown voltage and later a declining one. So VFPmax is a measure of how far away the device is from the theoretical maximum doping. VFPmax is also an indicator value for how much charge might be generated at the field-oxide interface in avalanche events. In such operation modes, some hot-carrier injection occurs at this interface and the generated charge does the same as an increased field electrode potential. To compare the performance including on-resistance of differently designed structures, not only the breakdown voltage but also VFPmax should be comparable.

Table <NUM> below demonstrates area-specific on-resistance (Ron X A) measured in milliohm per mm<NUM>, VFPmax measured in Volts, breakdown voltage (BVDSS) measured in Volts, FOM (figure of merit) for gate charge (FOMg) which is the product of on-resistance and gate charge and measured in milliohm-nC, and FOM for gate-drain charge (FOMgd) which is the product of on-resistance and gate-drain charge and also measured in milliohm-nC, for different cell designs including the cell design illustrated in <FIG>.

The cell designs each have a spicular-shaped field plate structure at the center of the cell and the same epitaxial layer stack. However, 'Cell Design <NUM>' has a gate trench which surrounds the needle-shaped field trench in a closed (continuous) grid-like manner. 'Cell Design <NUM>' is the cell shown in <FIG>, but without the current spread region <NUM>. 'Cell Design <NUM>' is the cell shown in <FIG> with the current spread region <NUM> formed by an implantation dose of 5e11cm-<NUM>. 'Cell Design <NUM>' is the cell shown in <FIG> with the current spread region <NUM> formed by an implantation dose of 1e12cm-<NUM>. 'Cell Design <NUM>' is the cell shown in <FIG> with the current spread region <NUM> formed by an implantation dose of <NUM>. 5e12cm-<NUM>. 'Cell Design <NUM>' is the cell shown in <FIG> with the current spread region <NUM> formed by an implantation dose of 2e12cm-<NUM>.

Setting the implantation dose for the current spread region <NUM> too high yields negative VFPmax and decreases BVDSS, where higher implantation dose translates to increased doping. The doping concentration of the current spread region <NUM> depends on the device construction and targeted voltage class. Hence, the current spread region <NUM> may have different base doping levels for different cell constructions and voltage classes.

The doping level of the current spread region <NUM> effects the on-state resistance (Ron) of the device. The on-state resistance Ron corresponds to a defined amount of dopants per area and stretches to a certain depth, so the change in doping in the current spread region <NUM> can be identified as compared to the base doping of the drift region <NUM> even though both regions <NUM>, <NUM> have the same conductivity type.

The current spread region <NUM> is formed under the body region <NUM> of the device, but preferably not too far under the gate trenches <NUM>. If the current spread region <NUM> extends too far under the gate trenches <NUM>, the electric field will increase at the bottom of the gate trenches <NUM> which can lead to gate dielectric degradation and eventually breakdown. The gate dielectric <NUM> may be thicker at the bottom of the gate trenches <NUM> to mitigate this risk. Ideally, the current spread region <NUM> does not extend at all under the gate trenches <NUM>. However, this may not be practical. Hence, the current spread region <NUM> may have some lateral extension under the gate trenches <NUM> which may be difficult to avoid. In the case of a thick bottom oxide, a deeper gate trench <NUM> may be used so that the gate electrode <NUM> is long enough to fully open the device channel.

The current spread region <NUM> has a higher average doping concentration than the drift region <NUM> as explained above. The current spread region <NUM> therefore has lower resistance that the drift region <NUM> , allowing the channel current to spread (distribute) faster in multiple dimensions. The maximum doping concentration of the current spread region <NUM> ideally is at the junction with the body region <NUM>, but this may not be practical. In one embodiment, the peak doping concentration of the current spread region <NUM> is at a depth in the semiconductor substrate <NUM> which is shallower than the bottom of the stripe-shaped gate structures <NUM>. The peak doping concentration of the current spread region <NUM> may be <NUM>. 5x to 5x higher than the average doping concentration, e.g., 2x to 4x higher.

By providing the current spread region <NUM> below the body region <NUM> in the semiconductor mesas <NUM> located between adjacent ones of the spicular-shaped field plate structures <NUM> and which are devoid of the stripe-shaped gate structures <NUM>, the spicular-shaped field plate structures <NUM> may be arranged in a grid whereas the gate structures <NUM> may be formed as stripes which run along two sides of each needle-shaped field plate <NUM> (e.g. parallel but not orthogonal) or even all <NUM> sides but without forming a closed (continuous) grid. The current spread region <NUM> increases the channel current distribution in the semiconductor mesas <NUM> between adjacent ones of the spicular-shaped field plate structures <NUM> and which are devoid of the stripe-shaped gate structures <NUM> and thereby lower gate charge and gate-drain charge, with little to no adverse impact on area-specific on-resistance.

Described next are various embodiments for the position, shape and formation of the current spread region <NUM> within each cell of a power semiconductor device. The current spread region <NUM> may abut a sidewall <NUM> of the spicular-shaped field plate structures <NUM>, e.g., as shown in <FIG>. The current spread region <NUM> may laterally extend from a sidewall <NUM> of each spicular-shaped field plate structure <NUM> to a sidewall <NUM> of the adjacent stripe-shaped gate structure <NUM>, also as shown in <FIG>.

<FIG> illustrates a partial cross-sectional view of a power transistor cell according to another embodiment. The power transistor cell embodiment shown in <FIG> is similar to the embodiment shown in <FIG>. Different, however, the spicular-shaped field plate structures <NUM> each have a connection region <NUM> connected to and which is narrower than the field electrode <NUM>. The connection region <NUM> is provided in the upper part of the field plate trenches <NUM>, and provides a point of electrical connection to the field electrode <NUM> which is located lower in the field plate trenches <NUM> than the connection region <NUM>. According to this embodiment, the current spread region <NUM> is formed adjacent the connection region <NUM> of the spicular-shaped field plate structures <NUM>. Also, a smaller semiconductor mesa width (Wm) is realized by using the connection region <NUM> to contact the wider buried field plates <NUM>. Hence, the mesa doping may be higher while the width into which the channel current spreads is lower.

Table <NUM> below demonstrates area-specific on-resistance (Ron X A), VFPmax, breakdown voltage (BVDSS), FOM (figure of merit) for gate charge (FOMg), and FOM for gate-drain charge (FOMgd), for different cell designs including the cell design illustrated in <FIG>.

The cell design simulation parameters summarized in Table <NUM> are identical to those summarized in Table <NUM>, except the 'Cell Design <NUM>' through 'Cell Design <NUM>' correspond to the cell embodiment shown in <FIG> instead of the cell embodiment of <FIG>. Comparing the simulation results in Tables <NUM> and <NUM> for 'Cell Design <NUM>' through 'Cell Design <NUM>' shows that the cell embodiment illustrated in <FIG> allows for a more efficient lateral spreading of the channel current which results in less negative impact on the on-resistance as compared to the cell embodiment illustrated in <FIG>.

<FIG> shows the voltage drop in electron quasi Fermi potential for the cell shown in <FIG> but without the current spread region <NUM>, and <FIG> shows the voltage drop for the cell shown in <FIG> with the current spread region <NUM>. Like <FIG>, <FIG> demonstrates that the semiconductor device with the current spread region <NUM> has better channel current spreading which yields a lower voltage drop for the device. The amount of on-resistance improvement corresponds to the level of doping of the current spread region <NUM>, as previously explained herein.

<FIG> illustrate respective plan views of additional embodiments of the current spread region <NUM>. The body and source regions <NUM>, <NUM> are obscured / out of view in <FIG> to provide an unobstructed view of the current spread region <NUM> in each case. The semiconductor devices shown in <FIG> may have the same or similar epitaxial layer stack construction as shown in <FIG> and <FIG>.

In <FIG>, the current spread region <NUM> abuts the sidewall <NUM> of each spicular-shaped field plate structure <NUM> and is confined by adjacent ones of the stripe-shaped gate structures <NUM>. The current spread region <NUM> may be formed by implanting a dopant species of the first conductivity type through the body region <NUM> using the same lithography mask for forming the source region <NUM>. Hence, no additional lithography process is needed and no degradation of the edge termination blocking capability of the device occurs. That is, the existing source lithography is used and only an additional implant step is needed over the whole area to form the current spread region <NUM>.

However, a relatively high energy implant is needed to form the current spread region <NUM> underneath the body region <NUM>, which may result in a large variation of the implanted ion depth. The implanted dopant species is activated, e.g., by annealing to form the current spread region <NUM>.

In <FIG>, the current spread region <NUM> is formed as stripes <NUM> which extend lengthwise (direction 'y' in <FIG>) between adjacent ones of the spicular-shaped field plate structures <NUM> and intersect neighboring ones of the stripe-shaped gate structures <NUM>. In one embodiment, the stripe-shaped gate structures <NUM> run orthogonal (direction 'x' in <FIG>) to the lengthwise extension direction of the stripes <NUM> of the current spread region <NUM>.

The current spread region <NUM> may be formed by, after forming the source region <NUM>, forming an additional lithography mask on the semiconductor substrate <NUM> and which has stripe-shaped openings extending lengthwise (direction 'y' in <FIG>) between adjacent ones of the spicular-shaped field plate structures <NUM> and intersect neighboring ones of the stripe-shaped gate structures <NUM>, and implanting a dopant species of the first conductivity type through the body region <NUM> using the additional lithography mask with the stripe-shaped openings. While an additional lithography step is needed according to this embodiment, the current spread region <NUM>/<NUM> is formed only in targeted regions, minimizing impact on breakdown voltage, DIBL (drain-induced barrier lowering) and avalanche.

In <FIG>, the stripe-shaped gate structures <NUM> have lateral extensions <NUM> which extend partly between adjacent ones of the spicular-shaped field plate structures110 so that a gap <NUM> is present between each lateral extension <NUM> and a neighboring one of the stripe-shaped gate structures <NUM>. For example, the stripe-shaped gate structures <NUM> may extend partly along an orthogonal direction (direction 'y' in <FIG>) but not from one stripe-shaped gate trench structure <NUM> to the adjacent (neighboring) stripe-shaped gate trench structure <NUM> which run lengthwise in direction 'x' in <FIG>. The current spread region <NUM> is confined to the gaps <NUM> in the lateral extensions <NUM> of the stripe-shaped gate structures <NUM>.

The current spread region <NUM> may be formed by, after forming the source region <NUM>, forming an additional lithography mask on the semiconductor substrate <NUM> and which has openings over the gaps <NUM> between the lateral extensions <NUM> of the stripe-shaped gate structures <NUM>. A dopant species of the first conductivity type is then implanted through the body region <NUM> using the additional lithography mask having the openings over the gaps <NUM>. Like the embodiment illustrated in <FIG>, the embodiment illustrated in <FIG> requires an additional lithography step and forms the current spread region <NUM> only in targeted regions to minimize impact on breakdown voltage, DIBL and avalanche. The embodiment illustrated in <FIG> provides the additional flexibility for the FOMg/FOMgd/Ron trade-off previously described herein in connection with Tables <NUM> and <NUM>.

In <FIG>, the current spread region <NUM> is formed as stripes <NUM> which extend lengthwise (direction 'y' in <FIG>) between adjacent ones of the spicular-shaped field plate structures <NUM> and terminate before reaching neighboring ones of the stripe-shaped gate structures <NUM>. In one embodiment, the stripe-shaped gate structures <NUM> run orthogonal (direction 'x' in <FIG>) to the lengthwise extension direction of the stripes <NUM> of the current spread region <NUM>.

The current spread region <NUM> may be formed by forming stripe-shaped grooves in the semiconductor substrate <NUM> which extend lengthwise (direction 'y' in <FIG>) between adjacent ones of the spicular-shaped field plate structures <NUM> and terminate before reaching neighboring ones of the stripe-shaped gate structures <NUM>, and implanting a dopant species of the first conductivity type into the stripe-shaped grooves. Like the embodiments illustrated in <FIG> and <FIG>, the embodiment illustrated in <FIG> also forms the current spread region <NUM> in targeted regions to minimize impact on breakdown voltage, DIBL and avalanche. However, by forming the stripe-shaped grooves in the semiconductor substrate <NUM> which run transverse to the stripe-shaped gate structures <NUM>, a lower ion implantation energy may be used to form the stripes <NUM> of the current spread region <NUM> since the implantation is not done through the body region <NUM> or only through a partial thickness of the body region <NUM>, thereby narrowing the distribution of the implanted ion depth.

The current spread ion implantation is not done over the stripe-shaped gate structures <NUM>. Instead, open contact grooves are used to do a tilted implant from the sidewall <NUM> of the spicular-shaped field plate trenches <NUM> without requiring an extra lithography step. The contact grooves can be opened over the entire length of the field plate trenches <NUM>. The current spread ion implantation can be performed using a twin-mode tilted implant on both sides of the spicular-shaped field plate trenches <NUM>, as indicated by the dashed lines in <FIG>.

In <FIG>, the current spread region <NUM> is defined by contact grooves <NUM> which run parallel (direction 'x' in <FIG>) with the stripe-shaped gate structures <NUM> and are aligned with the rows of spicular-shaped field plate structures <NUM>. The current spread region <NUM> may be formed by etching the contact grooves <NUM> into the semiconductor substrate <NUM>, each contact groove having unetched stripe-shaped regions <NUM> (direction 'y' in <FIG>) in parallel with one another, and implanting a dopant species of the first conductivity type into the contact grooves <NUM>.

A relatively low energy ion implantation may be used to form the current spread region <NUM> since the implant is done through contact grooves <NUM>. No extra lithography step is needed, and only a subsequent thermal budget for activating a highly-doped body contact region acts on the current spread implant, allowing for precise definition of the implanted ion depth. The contact grooves <NUM> have a stripe-like shape with bars <NUM> for easier fill with a metal, metal alloy, etc. to form a source/body contact <NUM>, with <NUM>° or tilted implant into the contact grooves <NUM> to form the current spread region <NUM>. The current spread region <NUM> is not shown in <FIG>, but the implantation process for the current spread region <NUM> is indicated by dashed lines in <FIG>. By keeping unetched stripe-shaped regions <NUM> in each contact groove <NUM>, there is no edge of contact which is better for lithographic processing in that identical open areas over the entire chip (die) provides for better control. The current spread ion implantation can be performed using a twin-mode tilted implant on both sides of the contact grooves <NUM>.

In general, the rows of spicular-shaped field plate structures <NUM> may be shifted with respect to one another so that the power transistor cell may have, for example, a hexagonal grid-like layout when viewed from above and some gate connections may be omitted so that in the top layout view, the stripe-shaped gate structures <NUM> run in zig-zag patterns over the chip. Hence, the stripe-shaped gate structures <NUM> may run lengthwise in straight or zig-zag patterns.

Terms such as "first", "second", and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

Claim 1:
A semiconductor device, comprising:
a semiconductor substrate (<NUM>) comprising a drift region (<NUM>) of a first conductivity type, a body region (<NUM>) of a second conductivity type formed above the drift region, and a source region (<NUM>) of the first conductivity type separated from the drift region by the body region;
rows of spicular-shaped field plate structures (<NUM>) formed in the semiconductor substrate (<NUM>), the spicular-shaped field plate structures (<NUM>) extending through the source region (<NUM>) and the body region (<NUM>) into the drift region (<NUM>);
stripe-shaped gate structures (<NUM>) formed in the semiconductor substrate (<NUM>) that extend parallel to one another, separate adjacent rows of the spicular-shaped field plate structures (<NUM>) and do not completely surround individual ones of the spicular shaped field plate structures (<NUM>), wherein semiconductor mesas (<NUM>) are located between adjacent ones of the spicular-shaped field plate structures (<NUM>) and are devoid of the strip-shaped gate structures (<NUM>); characterised in that the device further comprises
a current spread region (<NUM>) of the first conductivity type formed below the body region (<NUM>) in in the regions of the semiconductor mesas (<NUM>) which are devoid of the stripe-shaped gate structures (<NUM>), wherein the current spread region (<NUM>) has a higher average doping concentration that the drift region (<NUM>) and is configured to increase channel current distribution in the semiconductor mesas (<NUM>) which are devoid of the strip-shaped gate structures (<NUM>),
wherein the current spread region (<NUM>) consists of stripes (<NUM>) which extend lengthwise between adjacent ones of the spicular-shaped field plate structures (<NUM>) and intersect neighboring ones of the stripe-shaped gate structures (<NUM>)..