Patent Description:
With constant decrease in a feature size and a line width of a dynamic random access memory (DRAM), spacing between adjacent bit line structures becomes smaller and smaller. The smaller spacing between adjacent bit line structures may lead to continuous increase of parasitic capacitance between the adjacent bit line structures, which affects a saturation current in a DRAM array region and then affects the operation efficiency of the DRAM.

<CIT>discloses a method of fabricating a semiconductor device. This method includes forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a first conductive layer hole configured to expose the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures.

With the constant decrease in the line width of the DRAM, how to increase spacing between bit line structures is an urgent problem to be solved.

An objective of some embodiments of the present application is to provide a memory forming method and a memory, which increases spacing between the conductive layers in the bit line structures on the basis of not changing the arrangement of the bit line structures by forming conductive layers at different heights in bit line structures.

Compared with the prior art, in the embodiments of the present application, bit line contact layers at different heights are formed, so that conductive layers formed on top surfaces of the bit line contact layers are at different heights. Top surfaces of the conductive layers are at the same height in a direction perpendicular to an extension direction of the word line structures, and the top surfaces of the conductive layers are at different heights in the extension direction of the word line structures, that is, in discrete bit line structures subsequently formed, the conductive layers in the same bit line structure are at the same height, and the conductive layers in different bit line structures are at different heights. On the basis of not changing the arrangement of the bit line structures, the conductive layers in adjacent discrete bit line structures are at different heights, and compared with the conductive layers at the same height, a distance between the conductive layers at different heights changes from a horizontal distance to a slant distance, thus the spacing between the conductive layers is increased in the bit line structures. Further, parasitic capacitance between the bit line structures is reduced and a saturation current of the memory is increased. At the same time, the memory forming method according to the present embodiment features a simple process, a low cost, and easy implementation.

One or more embodiments are shown by way of exemplary description, and not by limitation, in the figures of the accompanying drawings. The figures in the drawings are not to scale, unless otherwise stated.

With constant decrease in a feature size and a line width of a DRAM, spacing between adjacent bit line structures becomes smaller and smaller. The smaller spacing between adjacent bit line structures may lead to continuous increase of parasitic capacitance between the adjacent bit line structures, which affects a saturation current in a DRAM array region and then affects the operation efficiency of the DRAM.

In order to make the objectives, technical solutions, and advantages of the present application clearer, some embodiments of the present application are described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that specific embodiments described herein are intended only to interpret the present application and are not intended to limit the present application.

A first embodiment of the present application provides a memory forming method, including: providing a substrate, including at least word line structures and active regions, and bottom dielectric layers and bit line contact layers located on a top surface of the substrate, the bottom dielectric layer having bit line contact openings exposing the active regions in the substrate, and the bit line contact layers covering the bottom dielectric layers and filling the bit line contact openings; etching part of the bit line contact layers to form the bit line contact layers of different heights; forming conductive layers on top surfaces of the bit line contact layers, top surfaces of the conductive layers being at the same height in a direction perpendicular to an extension direction of the word line structures; and the top surfaces of the conductive layers being at different heights in the extension direction of the word line structures; forming top dielectric layers on the top surfaces of the conductive layers; and sequentially etching part of the top dielectric layers, part of the conductive layers, and part of the bit line contact layers to form discrete bit line structures.

<FIG> are schematic structural diagrams corresponding to steps of a memory forming method according to a first embodiment of the present application.

Referring to <FIG>, a substrate <NUM> is provided. The substrate <NUM> includes at least word line structures <NUM> and active regions <NUM>, and bottom dielectric layers <NUM> and bit line contact layers <NUM> located on a top surface of the substrate <NUM>. The dielectric layers have bit line contact openings <NUM>. The bit line contact openings <NUM> expose the active regions <NUM> in the substrate <NUM>. The bit line contact layers <NUM> cover the bottom dielectric layers <NUM> and fill the bit line contact openings <NUM>.

Referring to <FIG>, a substrate <NUM> is provided. The substrate <NUM> includes at least word line structures <NUM> and active regions <NUM>.

<FIG> shows an extension direction <NUM> of the word line structures, that is, the dashed line <NUM> in the figure.

A plurality of active regions <NUM> are spaced parallel to each other, and for the active regions <NUM> in column i and the active regions <NUM> in column i+<NUM>, different active regions <NUM> are located at the same horizontal position in a direction perpendicular to the extension direction <NUM> of the word line structures. The active regions <NUM> in column i and the active regions <NUM> in adjacent columns (column i+<NUM> and column i-<NUM>) are located at different horizontal positions in the direction perpendicular to the extension direction <NUM> of the word line structures. Middle parts of the active regions <NUM> separated by the word line structures <NUM> arranged alternately are bit line contact points, which are used for connecting bit line structures subsequently formed.

It should be noted that the substrate <NUM> further includes other memory structures in addition to the word line structures <NUM> and the active regions <NUM>, such as shallow trench isolation structures. Since the other memory structures do not involve the core technology of the present application, they are not described in detail herein. Those skilled in the art can understand that the substrate <NUM> further includes other memory structures in addition to the word line structures <NUM> and the active regions <NUM>, which are used for normal operation of a memory.

The substrate <NUM> may be made of sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride, zinc oxide, or the like. In the present embodiment, the substrate <NUM> is made of a silicon material. It is understood by those skilled in the art that the use of the silicon material as the substrate <NUM> is intended to facilitate the understanding of subsequent formation methods by those skilled in the art and does not constitute any limitation. In an actual application process, an appropriate substrate material can be selected as required.

Referring to <FIG>, bottom dielectric layers <NUM> and bit line contact layers <NUM> are formed on a top surface of the substrate <NUM>. The bottom dielectric layers <NUM> have bit line contact openings <NUM>. The bit line contact openings <NUM> expose the active regions <NUM> in the substrate <NUM>. The bit line contact layers <NUM> cover the bottom dielectric layers <NUM> and fill the bit line contact openings <NUM>.

Referring to <FIG>, bottom dielectric layers <NUM> are formed on a top surface of the substrate <NUM>. The bottom dielectric layers <NUM> have bit line contact openings <NUM>. The bit line contact openings <NUM> are configured to expose the active regions <NUM> in the substrate <NUM>. Specifically, the bit line contact openings <NUM> are configured to expose bit line contact points, that is, expose middle parts of the active regions <NUM> separated by the word line structures <NUM>.

The bottom dielectric layers <NUM> are configured to isolate the bit line structures <NUM> at positions of non-bit line contact points from the active regions <NUM>. In the present embodiment, the bottom dielectric layer is made of silicon nitride. In other embodiments, the bottom dielectric layer may also be made of an insulating material such as silicon oxide or silicon oxynitride.

Referring to <FIG> is a schematic top view of the substrate <NUM>. On the basis of the bottom dielectric layers <NUM> formed in <FIG>, <FIG> shows positions where bit line structures <NUM> are required to be subsequently formed. <FIG> shows an extension direction <NUM> of the bit line structures, that is, the dashed line <NUM> in the figure. The bit line structures <NUM> are connected to bit line contact points of a column of active regions <NUM>.

Referring to <FIG>, bit line contact layers <NUM> are formed on a top surface of the substrate <NUM>. The bit line contact layers <NUM> cover the bottom dielectric layers110and fill the bit line contact openings <NUM>. <FIG> shows positions where bit line structures <NUM> are required to be subsequently formed. The bit lines connected to the active regions <NUM> and the bit lines located on the bottom dielectric layers <NUM> are arranged alternately in any section along the extension direction <NUM> of the word line structures.

In the present embodiment, the bit line contact layers <NUM> are made of a polysilicon material, which is used for the bit lines structure <NUM> subsequently formed to connect the active regions <NUM> in the substrate <NUM> through the bit line contact openings <NUM>.

Referring to <FIG>, part of the bit line contact layers <NUM> are etched to form bit line contact layers <NUM> of different heights.

The reason for forming the bit line contact layers <NUM> of different heights is as follows: the bit line contact layers <NUM> are used for subsequently forming conductive layers, the conductive layers are at different heights.

Specifically, referring to <FIG>, photolithographic mask layers <NUM> are formed on the top surfaces of the bit line contact layers <NUM>, and photoresists <NUM> are formed on top surfaces of the photolithographic mask layers <NUM>.

Referring to <FIG>, the photolithographic mask layers <NUM> are patterned, and patterns <NUM> arranged at intervals are formed in the direction perpendicular to the extension direction <NUM> of the word line structures. The patterns <NUM> arranged at intervals are extended strips arranged at intervals.

Referring to <FIG> shows positions of three kinds of patterns <NUM> arranged at intervals formed by patterning the photolithographic mask layers <NUM> based on the photoresists <NUM>, which are specifically as follows:
Positions of the first kind of patterns <NUM> arranged at intervals: Patterns I <NUM> expose only positions where bit line structures are required to be subsequently formed.

Specifically, the patterns I <NUM> cover at least one position where bit line structures are required to be subsequently formed and completely cover gaps between the bit line structures, only a position where at least one bit line structure is required to be subsequently formed is exposed between adjacent patterns I <NUM>, and the bit line structures covered by the patterns I <NUM> and the bit line structures not covered by the patterns I <NUM> are arranged alternately in the extension direction <NUM> of the word line structures.

Positions of the second kind of patterns <NUM> arranged at intervals: Patterns II <NUM> cover at least one bit line structure and positions of gaps between part of the bit line structures.

Specifically, the patterns II <NUM> cover at least one position where bit line structures are required to be subsequently formed and cover part of gaps between the bit line structures, only a position where at least one bit line structure is required to be subsequently formed and the part of gaps between the bit line structures are exposed between adjacent patterns II <NUM>, and the bit line structures covered by the patterns II <NUM> and the bit line structures not covered by the patterns II <NUM> are arranged alternately in the extension direction <NUM> of the word line structures.

Positions of the third kind of patterns <NUM> arranged at intervals: Patterns III <NUM> cover only a position of at least one bit line structure.

Specifically, the patterns III <NUM> cover at least one position where bit line structures are required to be subsequently formed, only gaps between the bit line structures and a position where at least one bit line structure is required to be subsequently formed are exposed between adjacent patterns III <NUM>, and the bit line structures covered by the patterns III <NUM> and the bit line structures not covered by the patterns III <NUM> are arranged alternately in the extension direction <NUM> of the word line structures.

Referring to <FIG>, part of the bit line contact layers <NUM> are etched based on the patterns <NUM> arranged at intervals to form bit line contact layers <NUM> of different heights.

Referring to <FIG>, the patterns <NUM> arranged at intervals are removed.

Directions of the dashed line <NUM> and the dashed line <NUM> in the figure are two section positions shown in <FIG>, for those skilled in the art to understand the principle of the present application.

<FIG> shows a schematic cross-sectional view in directions of the dashed line <NUM> and the dashed line <NUM>. The bit line contact layers <NUM> are at the same height in a direction perpendicular to the extension direction <NUM> of the word line structures (the same vertical position of the two figures). In the extension direction <NUM> of the word line structures (section direction illustrated), the bit line contact layers <NUM> are at different heights, and convex portions at the first height and concave parts at the second height are arranged alternately.

In other embodiments, masks may also be continuously formed to further etch the bit line contact layers of different heights, so that the heights of top surfaces of the remaining bit line contact layers may be arranged alternately in a preset height order.

Referring to <FIG>, conductive layers <NUM> are formed on top surfaces of the bit line contact layers <NUM> at different heights.

Specifically, referring to <FIG>, conductive films <NUM> are formed on top surfaces of the bit line contact layers <NUM> at different heights.

Referring to <FIG>, the conductive films <NUM> (refer to <FIG>) are etched to form conductive layers <NUM> with a uniform thickness on the top surfaces of the bit line contact layers <NUM> at different heights. The conductive layers <NUM> on the top surfaces of the bit line contact layers <NUM> at different heights are ensured to be at different heights by forming the conductive layers <NUM> with a uniform thickness.

In other embodiments, the thicknesses of the conductive layers on the top surfaces of the bit line contact layers at different heights may be different, but this needs to ensure that the top surfaces of the conductive layers are at different heights, so that a connecting line of the conductive layers between different bit line structures is oblique, thus the spacing of the conductive layers between the bit line structures is increased on the basis of not changing the arrangement of the bit line structures.

Top surfaces of the formed conductive layers <NUM> are at the same height in a direction perpendicular to the extension direction <NUM> of the word line structures; and the top surfaces are at different heights in the extension direction <NUM> of the word line structures.

In the present embodiment, the conductive layers <NUM> are made of one conductive material or multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and tungsten compounds.

Referring to <FIG>, top dielectric layers <NUM> are formed on the top surfaces of the conductive layers <NUM>.

Specifically, top dielectric films are formed on the top surfaces of the conductive layers, top surfaces of the top dielectric films are planarized to form the top dielectric layers <NUM>, and top surfaces of the top dielectric layers <NUM> are at a uniform height.

Specifically, the top surfaces of the top dielectric films are planarized by chemical mechanical polishing. Compared with etching, chemical mechanical polishing has a higher removal rate, which is conducive to shortening a process cycle.

In the present embodiment, the material of the top dielectric layers <NUM> includes silicon nitride, silicon oxynitride, silicon oxide, or other materials. In the present embodiment, the top dielectric layers <NUM> are made of a nitrogen-containing insulating material, that is, the top dielectric layers <NUM> are made of a silicon nitride material.

Referring to <FIG>, part of the top dielectric layers <NUM>, part of the conductive layers <NUM>, and part of the bit line contact layers <NUM> at different heights are sequentially etched to form discrete bit line structures <NUM>.

A connecting line of the conductive layers <NUM> in the discrete bit line structures <NUM> is straight in the direction perpendicular to the extension direction <NUM> of the word line structure, and conductive layers <NUM> in adjacent discrete bit line structures <NUM> are at different heights in the extension direction <NUM> of the word line structures.

Compared with the prior art, in the present embodiment, according to the memory forming method provided in the embodiment of the present application, bit line contact layers at different heights are formed, so that conductive layers formed on top surfaces of the bit line contact layers are at different heights. Top surfaces of the conductive layers are at the same height in a direction perpendicular to an extension direction of the word line structures, and the top surfaces of the conductive layers are at different heights in the extension direction of the word line structures, that is, in discrete bit line structures subsequently formed, the conductive layers in the same bit line structure are at the same height, and the conductive layers in different bit line structures are at different heights. On the basis of not changing the arrangement of the bit line structures, the conductive layers in adjacent discrete bit line structures are at different heights, and compared with the conductive layers at the same height, a distance between the conductive layers at different heights changes from a horizontal distance to a slant distance, thus the spacing between the conductive layers is increased in the bit line structures. Further, parasitic capacitance between the bit line structures is reduced and a saturation current of the memory is increased. At the same time, the memory forming method according to the present embodiment features a simple process, a low cost, and easy implementation.

The division of the above steps is only for clear illustration. In implementation, the steps may be combined into one step or some steps may be split into a plurality of steps. These steps, as long as observing the same logical relationship, all fall within the protection scope of the present application. Any non-mandatory modifications added to the flow or any optional designs introduced to the same shall fall within the protection scope of the present application provided that the core design of the procedures is not changed.

A second embodiment of the present application relates to a memory.

Referring to <FIG>, the memory according to the present embodiment will be described in detail below with reference to the drawings, and the parts the same as or corresponding to the first embodiment will not be described in detail below.

The memory includes: a substrate <NUM> including at least word line structures <NUM> and active regions <NUM>; bottom dielectric layers <NUM> located at the top of the substrate <NUM>, the bottom dielectric layers <NUM> having bit line contact openings <NUM> exposing the active regions <NUM> in the substrate; and discrete bit line structures <NUM>, top surfaces of the bit line structures <NUM> being at the same height, and the bit line structures <NUM> including: bit line contact layers <NUM> located at the top of the bottom dielectric layers <NUM> and the bit line contact openings <NUM>, conductive layers <NUM> located at the top of the bit line contact layers <NUM>, and top dielectric layers <NUM> located at the top of the conductive layers <NUM>; where the conductive layers <NUM> in the same bit line structure are at the same height in an extension direction <NUM> of the bit line structures, and the conductive layers <NUM> in adjacent bit line structures are at different heights in the extension direction <NUM> of the word line structures.

In the present embodiment, the thicknesses of the conductive layers <NUM> are uniform. In other embodiments, the thicknesses of the conductive layers <NUM> on the top surfaces of the bit line contact layers <NUM> at different heights may be different, but this needs to ensure that the top surfaces of the conductive layers <NUM> are at different heights, so that a connecting line of the conductive layers between different bit line structures is oblique, thus the spacing of the conductive layers between the bit line structures is increased on the basis of not changing the arrangement of the bit line structures.

In the present embodiment, in the extension direction of the bit line structures, the connecting line of the conductive layers <NUM> is straight, that is, in the same bit line structure <NUM>, the conductive layers <NUM> are at the same height (the same height at the bottom and the same height at the top).

In the present embodiment, the conductive layers <NUM> at the first height and the conductive layers <NUM> at the second height are arranged alternately in the extension direction <NUM> of the word line structures. In other embodiments, the conductive layers <NUM> may be arranged alternately in a preset height order.

Compared with the prior art, bit line contact layers at different heights are formed, so that conductive layers formed on top surfaces of the bit line contact layers are at different heights. Top surfaces of the conductive layers are at the same height in a direction perpendicular to an extension direction of the word line structures, and the top surfaces of the conductive layers are at different heights in the extension direction of the word line structures, that is, in discrete bit line structures subsequently formed, the conductive layers in the same bit line structure are at the same height, and the conductive layers in different bit line structures are at different heights. On the basis of not changing the arrangement of the bit line structures, the conductive layers in adjacent discrete bit line structures are at different heights, and compared with the conductive layers at the same height, a distance between the conductive layers at different heights changes from a horizontal distance to a slant distance, thus the spacing between the conductive layers is increased in the bit line structures. Further, parasitic capacitance between the bit line structures is reduced and a saturation current of the memory is increased. At the same time, the memory forming method according to the present embodiment features a simple process, a low cost, and easy implementation.

Since the first embodiment corresponds to the present embodiment, the present embodiment may be implemented in conjunction with the first embodiment. Related technical details mentioned in the first embodiment are still valid in the present embodiment, and a technical effect achieved in the first embodiment may also be achieved in the present embodiment, which is not described herein again to reduce repetition. Accordingly, related technical details mentioned in the present embodiment may also be applied to the first embodiment.

Claim 1:
A memory forming method, comprising providing a substrate (<NUM>), wherein the substrate (<NUM>) comprises at least word line structures (<NUM>) and active regions (<NUM>),
wherein bottom dielectric layers (<NUM>) and bit line contact layers (<NUM>) located on a top surface of the substrate (<NUM>), the bottom dielectric layers (<NUM>) have bit line contact openings (<NUM>) exposing the active regions (<NUM>) in the substrate (<NUM>), and the bit line contact layers (<NUM>) cover the bottom dielectric layers (<NUM>) and fill the bit line contact openings (<NUM>);
etching part of the bit line contact layers (<NUM>) to form the bit line contact layers of different heights (<NUM>);
forming conductive layers (<NUM>) on top surfaces of the bit line contact layers of different heights (<NUM>), top surfaces of the conductive layers (<NUM>) being at the same height in a direction perpendicular to an extension direction (<NUM>) of the word line structures; and the top surfaces of the conductive layers (<NUM>) being at different heights, at all positions in the bit line direction,
in the extension direction (<NUM>) of the word line structures:
forming top dielectric layers (<NUM>) on the top surfaces of the conductive layers (<NUM>); and
sequentially etching part of the top dielectric layers (<NUM>), part of the conductive layers (<NUM>), and part of the bit line contact layers of different heights (<NUM>) to form discrete bit line structures (<NUM>).