Patent Description:
Embodiments of the present technology relate to the field of semiconductor processing, including deposition technology.

Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for depositing material to be patterned. Physical, chemical, and plasma-enhanced deposition techniques are used to deposit different materials on substrates. In general, the layers should be deposited uniformly and smoothly across the substrate surface. In addition, different materials have different characteristics. Many layers of different materials can lead to different effects on the stack of layers or the substrate itself. These different effects can alter the performance and reliability of integrated circuits and other semiconductor devices.

As semiconductor devices become smaller, patterning these devices may become more challenging. Smaller features may be harder to define. This may be a result of the decreased size or of more stringent tolerances needed for performance, reliability, and manufacturing throughput. Structures, such as 3D NAND, vertical NMOS, and vertical PMOS, may have thin layers of different semiconductor materials across a large portion of the wafer. The layers should be uniform and have minimal roughness. The methods described below may provide an improved deposition process for multiple layers of semiconductor materials in part by managing the stress resulting from different layers of materials.

Embodiments of the present technology include a method of forming a stack of semiconductor layers. The method includes depositing a first silicon oxide layer on a substrate. The method also includes depositing a first silicon layer on the first silicon oxide layer. The method includes depositing a first silicon nitride layer on the first silicon layer. The method further includes depositing a second silicon layer on the first silicon nitride layer. In addition, the method includes depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer, wherein depositing the stress layer is after depositing the first silicon nitride layer and before depositing the second silicon layer.

Embodiments of the present technology include a method of forming a stack of semiconductor layers. The method includes depositing a first silicon oxide layer on a substrate. The method also includes depositing a first silicon layer on the first silicon oxide layer. The method further includes depositing a first silicon nitride layer on the first silicon layer. Depositing the first silicon nitride layer includes flowing a gas that includes helium and silane or disilane through a plasma to form plasma effluents. The plasma is sustained with an RF power. Depositing the first silicon nitride layer includes reducing stress in at least one of the first silicon layer, the first silicon oxide layer, or the substrate. In addition, the method includes depositing a second silicon layer on the first silicon nitride layer. The
operations form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer.

A method of managing stress in a silicon nitride layer on a semiconductor substrate may include determining a target stress level in the silicon nitride layer. The method may also include determining a flowrate of helium and an RF power to achieve the target stress level using a calibration curve. The method may further include flowing helium at the flowrate and silane or disilane through a plasma with the RF power. In addition, the method may include depositing the silicon nitride layer on the semiconductor substrate.

A stack of silicon oxide, polysilicon (or amorphous silicon, doped or undoped), silicon nitride, and polysilicon (or amorphous silicon) is called an OPNP stack. These OPNP stacks may be used for 3D NAND, vertical NMOS, vertical PMOS, and other semiconductor devices. <FIG> shows an example of an OPNP stack. The stack may include a substrate <NUM>, which may be a semiconductor wafer, including a silicon wafer. A silicon oxide layer <NUM> is on top of substrate <NUM>. On top of silicon oxide layer <NUM> is a polysilicon or amorphous silicon layer <NUM>. On top of polysilicon or amorphous silicon layer <NUM> is a silicon nitride layer <NUM>. On top of silicon nitride layer <NUM> is an additional polysilicon or amorphous silicon layer <NUM>.

The OPNP stack may be repeated. For example, <FIG> shows two OPNP stacks. The layers in <FIG> are as follows: substrate <NUM>, silicon oxide <NUM>, polysilicon or amorphous silicon layer <NUM>, silicon nitride <NUM>, polysilicon or amorphous silicon layer <NUM>, silicon oxide <NUM>, polysilicon or amorphous silicon layer <NUM>, silicon nitride <NUM>, and polysilicon or amorphous silicon layer <NUM>. <FIG> shows two stacks, but more than two OPNP stacks may be used.

These different layers in the OPNP stack cause stress on the wafer. The problem is exacerbated with multiple OPNP stacks. As a result of these stresses and other factors, conventional techniques result in wafer bow, which can lead to increased non-uniformity and surface roughness. Increased non-uniformity and surface roughness can lead to decreased device performance and reliability.

Embodiments of the present technology improve wafer bow, stress, uniformity, and roughness by managing the stress in the wafer. Some embodiments include depositing the layers with low pressure chemical vapor deposition (LPCVD). Other embodiments include depositing the layers with plasma enhanced chemical vapor deposition (PECVD).

Low pressure chemical vapor deposition (LPCVD) may be used to deposit layers for an OPNP stack, similar to those shown in <FIG>. Silicon oxide and silicon (whether polysilicon or amorphous silicon) layers may be compressive layers. Silicon nitride may be a tensile layer. The compressive stresses and the tensile stresses may not cancel out and result in a tensile force. As a result, the substrate or wafer may bow. To compensate for the stresses, LPCVD may be used to deposit a stress layer, which includes a silicon nitride layer or other tensile film on the back side of the wafer, resulting in a stack shown in <FIG>. Other tensile films may include SACVD oxide and LPCVD SiON. <FIG> has a substrate <NUM> with an OPNP stack of a silicon oxide layer <NUM>, a polysilicon or amorphous silicon layer <NUM>, a silicon nitride layer <NUM>, and a polysilicon or amorphous silicon layer <NUM>. On the bottom of substrate <NUM> is a stress layer <NUM>.

As shown in <FIG>, embodiments of the present technology may include a method <NUM> of forming a stack of semiconductor layers. Method <NUM> may include depositing a first silicon oxide layer on a substrate (block <NUM>). The substrate may be a semiconductor wafer, including a silicon wafer. In other embodiments, the substrate may include a wafer and additional layers on the wafer.

The first silicon oxide layer may be deposited on top of the substrate. The silicon oxide layer may include silicon dioxide. "Top" refers to the layer being deposited on the front side of the substrate and helps describe the orientation of the layers in the figures, but one of skill would recognize that "top" does not necessarily mean away from the center of the earth, as the substrate may be turned upside down. The first silicon oxide layer may be deposited to a thickness from <NUM> to <NUM> Angstroms, from <NUM> to <NUM> Angstroms, from <NUM> to <NUM> Angstroms, or over <NUM> Angstroms in embodiments. For example, the silicon oxide layer may be deposited to a thickness of <NUM> Angstroms. The first silicon oxide layer may be in contact with the substrate. The first silicon oxide layer may be deposited by low pressure chemical vapor deposition (LPCVD). All layers in the stack may be deposited by LPCVD and may exclude other deposition processes including PECVD.

Method <NUM> may also include depositing a first silicon layer on the first silicon oxide layer (block <NUM>). The first silicon layer may be in contact with the first silicon oxide layer. The first silicon layer may be deposited by LPCVD. The first silicon layer may include polysilicon or amorphous silicon. The first silicon layer may be doped or undoped. The doping may be performed in situ with the deposition by LPCVD by adding a dopant gas, including PH<NUM>, B<NUM>H<NUM>, or AsH<NUM>. The first silicon layer may be deposited to a thickness from <NUM> to <NUM> Angstroms, from <NUM> to <NUM> Angstroms, from <NUM> to <NUM> Angstroms, or over <NUM> Angstroms. For example, the first silicon layer may be deposited to a thickness of <NUM> Angstroms.

Method <NUM> may include depositing a first silicon nitride layer on the first silicon layer (block <NUM>). The first silicon nitride may be a tensile layer, and create tensile stress. The first silicon nitride layer may be deposited with a low ammonia flow to lower the tensile stress. For example, the flow of ammonia may be reduced from around <NUM>,<NUM> sccm to <NUM> sccm to reduce the tensile strength by half. In other examples, the flow of ammonia may be reduced to a range from <NUM> to <NUM> sccm, <NUM> to <NUM> sccm, <NUM> to <NUM> sccm, <NUM> to <NUM> sccm, or <NUM> to <NUM>,<NUM> sccm. The silicon oxide layer and the silicon layer may be compressive layers. The first silicon nitride layer may be deposited to a thickness from <NUM> to <NUM> Angstroms, from <NUM> to <NUM> Angstroms, from <NUM> to <NUM> Angstroms, from <NUM> to <NUM> Angstroms, or over <NUM> Angstroms. For example, the first silicon nitride layer may be deposited to a thickness of <NUM> Angstroms.

Method <NUM> may further include depositing a second silicon layer on the first silicon nitride layer (block <NUM>). The second silicon layer may be in contact with the first silicon nitride layer. The second silicon layer may be deposited by LPCVD. The second silicon layer may be any material and thickness described for the first silicon layer. The second silicon layer may be the same or different from the first silicon layer.

In addition, method <NUM> may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer (block <NUM>). In other words, the stress layer may be deposited on the back side of the substrate when the first silicon oxide layer is deposited on the front side of the substrate. The stress layer may be a second silicon nitride layer or another tensile layer. The stress layer may be a compressive layer, but methods may exclude either tensile layers or compressive layers. In order to deposit the stress layer on the back side of the substrate, the substrate may be processed in a chamber upside down compared to conventional operation. The substrate may be processed in a dedicated chamber or processing tool for back-side deposition. The stress layer may be in contact with the substrate. The stress layer may be deposited by LPCVD. The stress layer may be deposited to any thickness described for the first silicon nitride layer. The stress layer may have the same or different thickness as the first silicon nitride layer. Depositing the stress layer on the back side of the substrate may counteract the wafer bow created by layers on the front side of the substrate. For example, the layers on the front side of the substrate may create a tensile stress. The stress layer may also be tensile, but when deposited on the back side may pull the substrate to reduce the stress created by the front side layers.

Depositing the stress layer may be after the substrate is characterized by a bow exceeding a threshold value. Wafer bow may be the deviation of the center point of a median surface of an unclamped wafer from the median surface to the reference plane. The threshold value may be a value from +/-<NUM> to +/-<NUM>, from +/-<NUM> to +/-<NUM>, from <NUM> to <NUM>, or greater than <NUM>. For example, the threshold value may be <NUM>. After depositing the stress layer, the substrate may be characterized by a bow not exceeding the threshold value. The wafer bow may be reduced by <NUM>%, by <NUM>%, by <NUM>%, by <NUM>%, by <NUM>%, or by <NUM>% compared to the bow before depositing the stress layer. depositing the stress layer may result in a bow in the substrate in the opposite direction compared to before the stress layer was deposited.

Because depositing the stress layer may be based on a threshold value for wafer bow that may adversely affect deposition uniformity or other properties, depositing the stress layer may occur after any one of the layers is deposited. The different possibilities for depositing the stress layer are illustrated in <FIG> by dashed arrows. For example, depositing the second silicon nitride layer as the stress layer may be after depositing the first silicon oxide layer and before depositing the first silicon nitride layer. In fact, "first" and "second" may be
used to differentiate layers and not indicate the order of deposition. However, "first" and "second" may indicate the order of deposition. Depositing the stress layer is after depositing the first silicon nitride layer and before depositing the second silicon layer. In examples not covered by the claims, depositing the stress layer may be after depositing the second silicon layer and before a layer deposited on the second silicon layer. In further examples not covered by the claims, the stress layer may be deposited after depositing the second silicon layer and before patterning the second silicon layer.

The operations may form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer. This stack may be the OPNP stack. The stress layer may not be deposited until two, three, four, or more OPNP stacks are formed.

Method <NUM> may further include depositing a second silicon oxide layer on the second silicon layer. Method <NUM> may also include depositing a third silicon layer on the second silicon oxide layer. Method <NUM> may additionally include depositing a second silicon nitride layer on the third silicon layer. Furthermore, Method <NUM> may include depositing a fourth silicon layer on the second silicon nitride layer. Method <NUM> may also include depositing a second stress layer on the first stress layer previously deposited. The second stress layer may be any of the materials disclosed for the first stress layer. Depositing the second stress layer may be after the substrate is characterized by a bow exceeding the threshold value. The additional layers may then form two sets of OPNP stacks. Even more layers can be deposited to form multiple sets of OPNP stacks, which may number <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or more than <NUM>. Eight OPNP stacks may have a thickness of about <NUM>.

Method <NUM> may include depositing the first silicon oxide layer, the first silicon nitride layer, and the stress layer in a first chamber of a processing tool. In addition, the method may include depositing the first silicon layer and the second silicon layer in a second chamber of the processing tool. In other words, depositing silicon oxide layers and silicon nitride layers may be in one chamber of the processing tool, while depositing silicon layers may be in another chamber of a processing tool. Method <NUM> may include removing the substrate from the processing tool. The processing tool may be an Applied Materials® Centura® system. After removal, the substrate may be at atmospheric pressure. The substrate may be transferred into a FOUP. The stack of semiconductor layers may then undergo patterning processes including photolithography and etching processes.

After depositing the second silicon layer, the substrate and the layers may have a standard deviation in uniformity of less than <NUM>%, less than <NUM>%, or less than <NUM>%. The wafer substrate bow may be less than <NUM>, less than <NUM>, or less than <NUM> in magnitude, either compressive or tensile. The adhesion may be better than <NUM> J/m<NUM>, <NUM> J/m<NUM>, <NUM> J/m<NUM>, <NUM> J/m<NUM>, <NUM> J/m<NUM>, or <NUM> J/m<NUM>. The roughness may be better than <NUM> RMS, <NUM> RMS, or <NUM> RMS as measured by atomic force microscopy (AFM). The silicon nitride may be have a high wet rate, (e.g., greater than <NUM> Å/min, <NUM> Å/min, or <NUM> Å/min) in hot phosphoric acid nitride bath to be able to selectively partially remove some of the silicon nitride layer in a later process if needed.

Plasma enhanced chemical vapor deposition (PECVD) may be used instead of LPCVD to form a stack of semiconductor layers. PECVD may allow for all layers to be processed in a single chamber instead of multiple chambers. As a result, PECVD may be more efficient, cost effective, and have fewer defects. PECVD may also avoid handling the front side of a substrate. Instead of depositing a silicon nitride layer on the back side of a substrate, processes using PECVD may use different recipes to manage the stress caused by the silicon nitride layer. In this manner, wafer bow may be minimized. Including a helium flow while depositing silicon nitride and using a certain range of RF power was observed to affect the stress in the silicon nitride layer. In addition, a plasma with nitrogen and ammonia used when depositing silicon was observed to improve the adhesion of silicon to the underlying silicon nitride. All layers may be deposited with PECVD. processes may exclude layers deposited with other methods, including LPCVD.

As shown in <FIG>, methods of the present technology may include a method <NUM> of forming a stack of semiconductor layers. Method <NUM> may include depositing a first silicon oxide layer on a substrate (block <NUM>). The substrate may be any substrate described herein. The first silicon oxide layer may be any silicon oxide layer described herein. The first silicon oxide layer may be deposited by PECVD.

Method <NUM> may also include depositing a first silicon layer on the first silicon oxide layer (block <NUM>). The first silicon layer may be deposited by PECVD and may be any silicon layer described herein.

Method <NUM> may further include depositing a first silicon nitride layer on the first silicon layer (block <NUM>). The first silicon nitride layer may be deposited by PECVD. The first silicon nitride layer may be deposited to any thickness described herein. Depositing the first silicon nitride layer may include flowing a gas that includes helium and silane or disilane, through a plasma to form plasma effluents (block 506a). The flowing gas may also include at least one of nitrogen or ammonia. The gas may exclude one or more of the compounds. The helium may be flowed at a flow rate in a range from <NUM> slm (standard liter per minute) to <NUM> slm. The helium may be flowed at a rate in a range from <NUM> slm to <NUM> slm, <NUM> slm to <NUM> slm, <NUM> slm to <NUM> slm, <NUM> slm to <NUM> slm, <NUM> slm, to <NUM> slm, <NUM> slm to <NUM> slm, <NUM> slm to <NUM> slm, <NUM> slm to <NUM> slm, <NUM> slm to <NUM> slm, <NUM> slm to <NUM> slm, or more than <NUM> slm. The flow rate of silane may be from <NUM> sccm to <NUM> sccm, <NUM> sccm to <NUM> sccm, <NUM> sccm to <NUM> sccm, or greater than <NUM> sccm. The flow rate of silane may include about <NUM> sccm. The flow rate of nitrogen may be from <NUM>,<NUM> sccm to <NUM>,<NUM> sccm, from <NUM>,<NUM> sccm to <NUM>,<NUM> sccm, from <NUM>,<NUM> sccm to <NUM>,<NUM> sccm, or greater than <NUM>,<NUM> sccm. As an example, the flow rate of nitrogen may be about <NUM>,<NUM> sccm. The flow rate of ammonia may be from <NUM> sccm to <NUM>,<NUM> sccm, from <NUM>,<NUM> sccm to <NUM>,<NUM> sccm, from <NUM>,<NUM> sccm to <NUM>,<NUM> sccm, or over <NUM>,<NUM> sccm. The flow rate of ammonia may be about <NUM>,<NUM> sccm.

The plasma may be sustained with an RF power. The RF power may be in a range from <NUM> W to <NUM> W, from <NUM> W to <NUM> W, from <NUM> W to <NUM> W, from <NUM> W to <NUM> W, from <NUM> W to <NUM> W, from <NUM> W to <NUM> W, or greater than <NUM> W. The RF power may be at <NUM>.

Depositing the first silicon nitride layer may include reducing stress in at least one of the first silicon layer, the first silicon oxide layer, or the substrate (block 506b). The stress may be reduced overall for all the layers. The first silicon nitride layer may be characterized by a stress in a range from -<NUM>,<NUM> MPa to <NUM> MPa, where a negative value refers to compressive stress, and a positive value refers to tensile stress. The stress of the first silicon nitride layer may be tuned to be more tensile, in order to counteract the compressive stress of the underlying layers. The silicon nitride layer may be deposited with lower RF power and lower helium flowrates. The bow may be reduced by any amount described herein. As an example, the bow before for eight OPNP stacks without managing stress using the silicon nitride processes may be near +<NUM>, and the bow with depositing the stress layers with low RF power and low helium flow may be -<NUM>.

The silicon nitride may be have a high wet rate (e.g., greater than <NUM>,<NUM>Å/min) in a hot phosphoric acid nitride bath to be able to selectively removed (fully or partially) some of the silicon nitride layer in later process if needed.

In addition, method <NUM> may include depositing a second silicon layer on the first silicon nitride layer (block <NUM>). The second silicon layer may be any silicon layer and thickness described herein.

The operations may form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer. The operations may be repeated to form multiple stacks of the OPNP semiconductor layers, including any stacks described herein.

Depositing the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer may be performed in the same chamber of a processing tool. The processing tool may be Applied Materials® Producer® system. Method <NUM> may further include removing the substrate from the chamber after depositing the second silicon layer and before any other depositing or patterning occurs. In processes where the OPNP stack is repeated, the substrate may be removed from the processing tool. after the OPNP stack is repeated and before any patterning processes on the stack. The substrate may be transferred into a FOUP. The stack of semiconductor layers may then undergo patterning processes.

After depositing the second silicon layer, the substrate and the layers may have a standard deviation in uniformity of less than <NUM>%, less than <NUM>%, or less than <NUM>%. The wafer substrate bow may be less than <NUM>, less than <NUM>, or less than <NUM> in magnitude, either compressive or tensile. The adhesion may be better than <NUM> J/m<NUM>, <NUM> J/m<NUM>, <NUM> J/m<NUM>, <NUM> J/m<NUM>, <NUM> J/m<NUM>, or <NUM> J/m<NUM>.

The roughness may be better than <NUM> RMS, <NUM> RMS, <NUM> RMS, or <NUM> RMS as measured by (AFM).

As shown in <FIG>, processes may include a method <NUM> of managing stress in a silicon nitride layer on a semiconductor substrate. The semiconductor substrate may include a silicon layer on a silicon oxide layer on a silicon substrate. The silicon substrate may be a silicon wafer. The silicon layer may be any silicon layer described herein. The silicon oxide layer may be any silicon oxide layer described herein.

Method <NUM> may include determining a target stress level in the silicon nitride layer (block <NUM>). The target stress level may be in a range from -<NUM>,<NUM> MPa to <NUM> MPa. The target stress level may be selected based on the thickness of all layers in the stack and the stress for other film layers. The stress in the layers may be measured or may be calculated, and the target stress level may be determined based on the stress for the other layers. PECVD oxide and amorphous silicon may be compressive layers and may be deposited to a predetermined thickness. The compressive stress for these oxide and silicon layers can be measured or calculated. The target stress level to cancel out the compressive stress can be calculated using the thickness of the silicon nitride to be deposited. The target stress level in the silicon nitride layer may be calculated with Stoney's Equation. The target stress level may be selected so as to minimize bow in the substrate after the entire dielectric stack is formed.

Method <NUM> may also include determining a flowrate of helium and an RF power to achieve the target stress level using a calibration curve (block <NUM>). The calibration curve may include data from previous runs or experiments that relate stress in a silicon nitride layer to the flowrate of helium and/or the RF power used in the deposition process. The calibration curve may be in the form of a graph, a regression (e.g., a linear regression), an equation, or a set of data points. The calibration curve may need not be generated for each silicon nitride layer, and a previously generated calibration curve may be used for processing multiple substrates and/or multiple silicon nitride layers.

Method <NUM> may further include flowing helium at the flowrate, silane, nitrogen, and ammonium through a plasma with the RF power (block <NUM>). The flowrate of the helium may be in any range described herein, including a range from <NUM> slm to <NUM> slm. The RF power may be in any range described herein, including a range from <NUM> to <NUM> W.

In addition, method <NUM> may include depositing the silicon nitride layer on the semiconductor substrate (block <NUM>). The silicon nitride layer may be deposited by PECVD. The silicon nitride layer may be deposited to any thickness described herein. The silicon nitride layer, after deposited on the semiconductor substrate, may be characterized by a stress level that is the same as the target stress level, or within <NUM>%, <NUM>%, <NUM>%, <NUM>%, or <NUM>% of the target stress level.

Method <NUM> may also include depositing a silicon layer on the silicon nitride layer. The silicon layer may be any silicon layer described herein.

The stress level in a silicon nitride level was measured for different helium flowrates. The helium flowrate was varied from <NUM>,<NUM> sccm to <NUM>,<NUM> sccm. The RF power was constant at <NUM> W, the temperature was constant at <NUM>, the silane flow was <NUM> sccm, the nitrogen flow was <NUM>,<NUM> sccm, and the ammonia flow was <NUM>,<NUM> sccm. The thickness of the deposited silicon nitride layer ranged from about <NUM>,<NUM> Angstroms to about <NUM>,<NUM> Angstroms. The resulting stress in the nitride layer is shown in <FIG>. The stress ranged from about <NUM> MPa to about <NUM> MPa. Higher levels of helium flow resulted in less stress.

The stress level in a silicon nitride level was measured for different RF power without a helium flowrate. The RF power was varied from <NUM> W to <NUM> W. The helium flowrate was fixed at <NUM> sccm, the temperature was constant at <NUM>, the silane flow was <NUM> sccm, the nitrogen flow was <NUM>,<NUM> sccm, and the ammonia flow was <NUM>,<NUM> sccm. The thickness of the deposited silicon nitride layer ranged from about <NUM>,<NUM> Angstroms to about <NUM>,<NUM> Angstroms. The resulting stress in the nitride layer is shown in <FIG>. The stress ranged from about -<NUM> MPa to about <NUM> MPa. Higher RF power resulted in a lower level of absolute stress. Stress with the smallest magnitude was observed to be at about <NUM> W.

The stress level in a silicon nitride level was measured for different RF power at a helium flowrate of <NUM>,<NUM> sccm. The RF power was varied from <NUM> W to <NUM> W. The helium rate was fixed at <NUM>,<NUM> sccm, the temperature was constant at <NUM>, the silane flow was <NUM> sccm, the nitrogen flow was <NUM>,<NUM> sccm, and the ammonia flow was <NUM>,<NUM> sccm. The thickness of the deposited silicon nitride layer ranged from about <NUM>,<NUM> Angstroms to about <NUM>,<NUM> Angstroms. The resulting stress in the nitride layer is shown in <FIG>. The stress ranged from about -<NUM>,<NUM> MPa to about <NUM> MPa. Higher RF power resulted in a lower level of absolute stress. The trend for lower stress with higher RF power is present with both no flow of He and a <NUM>,<NUM> sccm flowrate of helium. As seen in <FIG> and <FIG>, the additional flowrate of helium lowered the stress in the silicon nitride layer further.

<FIG>, <FIG> show cross-section scanning electron microscope (SEM) images of eight sets of OPNP layers deposited with PECVD according processes of the present technology. The RF power was <NUM> W. The flowrate of helium was <NUM>,<NUM> sccm. The repeated stack was <NUM> Angstroms of undoped amorphous silicon on <NUM> Angstroms of silicon nitride on <NUM> Angstroms of undoped amorphous silicon on top of <NUM> Angstroms of silicon oxide. The top layers in rectangle <NUM> in <FIG> are imaged in <FIG>. The bottom layers in rectangle <NUM> in <FIG> are imaged in <FIG>. The estimated standard deviation for uniformity was <NUM>%.

<FIG>, and <FIG> show cross-section SEM images of eight sets of OPNP layers deposited with LPCVD according to methods of the present technology. The repeated stack was <NUM> Angstroms of undoped amorphous silicon on <NUM> Angstroms of silicon nitride on <NUM> Angstroms of undoped amorphous silicon on top of <NUM> Angstroms of silicon oxide. After depositing two sets of OPNP layers on the front side, <NUM>,<NUM> Angstroms of silicon nitride were deposited on the back side. For the eight sets of OPNP layers, the wafer was flipped a total of three times and <NUM>,<NUM> Angstroms of silicon nitride was deposited three times. The top layers in rectangle <NUM> in <FIG> are imaged in <FIG>. The bottom layers in rectangle <NUM> in <FIG> are imaged in <FIG>. The estimated standard deviation for uniformity was <NUM>%. The stack deposited by PECVD in <FIG>, <FIG> had better uniformity and roughness than the stack deposited by LPCVD in <FIG>, and <FIG>. Part of the worse uniformity and roughness with LPCVD was the presence of particles in the stack. Without these particle defects, the uniformity and roughness with LPCVD would be improved, though probably still not to the level of PECVD.

<FIG> shows a top plan view of one example not according to the invention of a processing system <NUM> of deposition, etching, baking, and curing chambers. The processing system <NUM> depicted in <FIG> may contain a plurality of process chambers, 1214A-D, a transfer chamber <NUM>, a service chamber <NUM>, an integrated metrology chamber <NUM>, and a pair of load lock chambers 1206A-B. The process chambers may include structures or components similar to those described in relation to LPCVD, as well as additional processing chambers.

To transport substrates among the chambers, the transfer chamber <NUM> may contain a robotic transport mechanism <NUM>. The transport mechanism <NUM> may have a pair of substrate transport blades 1213A attached to the distal ends of extendible arms 1213B, respectively. The blades 1213A may be used for carrying individual substrates to and from the process chambers. In operation, one of the substrate transport blades such as blade 1213A of the transport mechanism <NUM> may retrieve a substrate W from one of the load lock chambers such as chambers 1206A-B and carry substrate W to a first stage of processing, for example, an etching process as described below in chambers 1214A-D. If the chamber is occupied, the robot may wait until the processing is complete and then remove the processed substrate from the chamber with one blade 1213A and may insert a new substrate with a second blade (not shown). Once the substrate is processed, it may then be moved to a second stage of processing. For each move, the transport mechanism <NUM> generally may have one blade carrying a substrate and one blade empty to execute a substrate exchange. The transport mechanism <NUM> may wait at each chamber until an exchange can be accomplished.

Once processing is complete within the process chambers, the transport mechanism <NUM> may move the substrate W from the last process chamber and transport the substrate W to a cassette within the load lock chambers 1206A-B. From the load lock chambers 1206A-B, the substrate may move into a factory interface <NUM>. The factory interface <NUM> generally may operate to transfer substrates between pod loaders 1205A-D in an atmospheric pressure clean environment and the load lock chambers 1206A-B. The clean environment in factory interface <NUM> may be generally provided through air filtration processes, such as HEPA filtration, for example. Factory interface <NUM> may also include a substrate orienter/aligner (not shown) that may be used to properly align the substrates prior to processing. At least one substrate robot, such as robots 1208A-B, may be positioned in factory interface <NUM> to transport substrates between various positions/locations within factory interface <NUM> and to other locations in communication therewith. Robots 1208A-B may be configured to travel along a track system within factory interface <NUM> from a first end to a second end of the factory interface <NUM>.

The processing system <NUM> may further include an integrated metrology chamber <NUM> to provide control signals, which may provide adaptive control over any of the processes being performed in the processing chambers. The integrated metrology chamber <NUM> may include any of a variety of metrological devices to measure various film properties, such as thickness, roughness, composition, and the metrology devices may further be capable of characterizing grating parameters such as critical dimensions, sidewall angle, and feature height under vacuum in an automated manner.

Turning now to <FIG> is shown a cross-sectional view of an exemplary process chamber system <NUM> according to the present technology. Chamber <NUM> may be used, for example, in one or more of the processing chamber sections <NUM> of the system <NUM> previously discussed. Generally, the etch chamber <NUM> may include a first capacitively-coupled plasma source to implement an ion milling operation and a second capacitively-coupled plasma source to implement a deposition operation and to implement an optional etching operation. The chamber <NUM> may include grounded chamber walls <NUM> surrounding a chuck <NUM>. The chuck <NUM> may be an electrostatic chuck that clamps the substrate <NUM> to a top surface of the chuck <NUM> during processing, though other clamping mechanisms as would be known may also be utilized. The chuck <NUM> may include an embedded heat exchanger coil <NUM>. In this example, not according to the invention the heat exchanger coil <NUM> includes one or more heat transfer fluid channels through which heat transfer fluid, such as an ethylene glycol/water mix, may be passed to control the temperature of the chuck <NUM> and ultimately the temperature of the substrate <NUM>.

The chuck <NUM> may include a mesh <NUM> coupled to a high voltage DC supply <NUM> so that the mesh <NUM> may carry a DC bias potential to implement the electrostatic clamping of the substrate <NUM>. The chuck <NUM> may be coupled with a first RF power source and in one case the mesh <NUM> may be coupled with the first RF power source so that both the DC voltage offset and the RF voltage potentials are coupled across a thin dielectric layer on the top surface of the chuck <NUM>. In the illustrative example, not according to the invention, the first RF power source may include a first and second RF generator <NUM>, <NUM>. The RF generators <NUM>, <NUM> may operate at any industrially utilized frequency, however in the example, not according to the invention, the RF generator <NUM> may operate at <NUM> to provide advantageous directionality. Where a second RF generator <NUM> is also provided, the exemplary frequency may be <NUM>.

With the chuck <NUM> to be RF powered, an RF return path may be provided by a first showerhead <NUM>. The first showerhead <NUM> may be disposed above the chuck to distribute a first feed gas into a first chamber region <NUM> defined by the first showerhead <NUM> and the chamber wall <NUM>. As such, the chuck <NUM> and the first showerhead <NUM> form a first RF coupled electrode pair to capacitively energize a first plasma <NUM> of a first feed gas within a first chamber region <NUM>. A DC plasma bias, or RF bias, resulting from capacitive coupling of the RF powered chuck may generate an ion flux from the first plasma <NUM> to the substrate <NUM>, e.g., Ar ions where the first feed gas is Ar, to provide an ion milling plasma. The first showerhead <NUM> may be grounded or alternately coupled with an RF source <NUM> having one or more generators operable at a frequency other than that of the chuck <NUM>, e.g., <NUM> or <NUM>. In the illustrated example not according to the invention, the first showerhead <NUM> may be selectably coupled to ground or the RF source <NUM> through the relay <NUM> which may be automatically controlled during the etch process, for example by a controller (not shown). The chamber <NUM> may not include showerhead <NUM> or dielectric spacer <NUM>, and may instead include only baffle <NUM> and showerhead <NUM> described further below.

As further illustrated in the figure, the etch chamber <NUM> may include a pump stack capable of high throughput at low process pressures. At least one turbo molecular pump <NUM>, <NUM> may be coupled with the first chamber region <NUM> through one or more gate valves <NUM> and disposed below the chuck <NUM>, opposite the first showerhead <NUM>. The turbo molecular pumps <NUM>, <NUM> may be any commercially available pumps having suitable throughput and more particularly may be sized appropriately to maintain process pressures below or about <NUM> mTorr or below or about <NUM> mTorr at the desired flow rate of the first feed gas, e.g., <NUM> to <NUM> sccm of Ar where argon is the first feedgas. In the example, not according to the invention, illustrated, the chuck <NUM> may form part of a pedestal which is centered between the two turbo pumps <NUM> and <NUM>, however in alternate configurations chuck <NUM> may be on a pedestal cantilevered from the chamber wall <NUM> with a single turbo molecular pump having a center aligned with a center of the chuck <NUM>.

Disposed above the first showerhead <NUM> may be a second showerhead <NUM>. In one example, not according to the invention, during processing, the first feed gas source, for example, argon delivered from gas distribution system <NUM> may be coupled with a gas inlet <NUM>, and the first feed gas flowed through a plurality of apertures <NUM> extending through second showerhead <NUM>, into the second chamber region <NUM>, and through a plurality of apertures <NUM> extending through the first showerhead <NUM> into the first chamber region <NUM>. An additional flow distributor or baffle <NUM> having apertures <NUM> may further distribute a first feed gas flow <NUM> across the diameter of the etch chamber <NUM> through a distribution region <NUM>. In an alternate example, not according to the invention, the first feed gas may be flowed directly into the first chamber region <NUM> via apertures <NUM> which are isolated from the second chamber region <NUM> as denoted by dashed line <NUM>.

The chamber <NUM> may be configured to perform a deposition operation. A plasma <NUM> may be generated in the second chamber region <NUM> by an RF discharge which may be implemented in any of the manners described for the second plasma <NUM>. Where the first showerhead <NUM> is powered to generate the plasma <NUM> during a deposition, the first showerhead <NUM> may be isolated from a grounded chamber wall <NUM> by a dielectric spacer <NUM> so as to be electrically floating relative to the chamber wall. In this example, not according to the invention, an oxidizer feed gas source, such as molecular oxygen, may be delivered from gas distribution system <NUM>, and coupled with the gas inlet <NUM>. In examples, some being not according to the invention, where the first showerhead <NUM> is a multi-channel showerhead, any silicon-containing precursor, such as OMCTS for example, may be delivered from gas distribution system <NUM>, and directed into the first chamber region <NUM> to react with reactive species passing through the first showerhead <NUM> from the plasma <NUM>. Alternatively the silicon-containing precursor may also be flowed through the gas inlet <NUM> along with the oxidizer.

Chamber <NUM> may additionally be reconfigured from the state illustrated to perform an etching operation. A secondary electrode <NUM> may be disposed above the first showerhead <NUM> with a second chamber region <NUM> there between. The secondary electrode <NUM> may further form a lid or top plate of the etch chamber <NUM>. The secondary electrode <NUM> and the first showerhead <NUM> may be electrically isolated by a dielectric ring <NUM> and form a second RF coupled electrode pair to capacitively discharge a second plasma <NUM> of a second feed gas within the second chamber region <NUM>. Advantageously, the second plasma <NUM> may not provide a significant RF bias potential on the chuck <NUM>. At least one electrode of the second RF coupled electrode pair may be coupled with an RF source for energizing an etching plasma. The secondary electrode <NUM> may be electrically coupled with the second showerhead <NUM>. In an example, not according to the invention, the first showerhead <NUM> may be coupled with a ground plane or floating and may be coupled to ground through a relay <NUM> allowing the first showerhead <NUM> to also be powered by the RF power source <NUM> during the ion milling mode of operation. Where the first showerhead <NUM> is grounded, an RF power source <NUM>, having one or more RF generators operating at <NUM> or <NUM>, for example, may be coupled with the secondary electrode <NUM> through a relay <NUM> which may allow the secondary electrode <NUM> to also be grounded during other operational modes, such as during an ion milling operation, although the secondary electrode <NUM> may also be left floating if the first showerhead <NUM> is powered.

A second feed gas source, such as nitrogen trifluoride, and a hydrogen source, such as ammonia, may be delivered from gas distribution system <NUM>, and coupled with the gas inlet <NUM> such as via dashed line <NUM>. In this mode, the second feed gas may flow through the second showerhead <NUM> and may be energized in the second chamber region <NUM>. Reactive species may then pass into the first chamber region <NUM> to react with the substrate <NUM>. As further illustrated, for cases where the first showerhead <NUM> is a multi-channel showerhead, one or more feed gases may be provided to react with the reactive species generated by the second plasma <NUM>. In one such example, not according to the invention, a water source may be coupled with the plurality of apertures <NUM>. Additional configurations may also be based on the general illustration provided, but with various components reconfigured. For example, flow distributor or baffle <NUM> may be a plate similar to the second showerhead <NUM>, and may be positioned between the secondary electrode <NUM> and the second showerhead <NUM>. As any of these plates may operate as an electrode in various configurations for producing plasma, one or more annular or other shaped spacer may be positioned between one or more of these components, similar to dielectric ring <NUM>. Second showerhead <NUM> may also operate as an ion suppression plate in examples, some being not according to the invention, and may be configured to reduce, limit, or suppress the flow of ionic species through the second showerhead <NUM>, while still allowing the flow of neutral and radical species. One or more additional showerheads or distributors may be included in the chamber between first showerhead <NUM> and chuck <NUM>. Such a showerhead may take the shape or structure of any of the distribution plates or structures previously described. Also, in embodiments a remote plasma unit (not shown) may be coupled with the gas inlet to provide plasma effluents to the chamber for use in various processes.

In an example, not according to the invention, the chuck <NUM> may be movable along the distance H2 in a direction normal to the first showerhead <NUM>. The chuck <NUM> may be on an actuated mechanism surrounded by a bellows <NUM>, or the like, to allow the chuck <NUM> to move closer to or farther from the first showerhead <NUM> as a means of controlling heat transfer between the chuck <NUM> and the first showerhead <NUM>, which may be at an elevated temperature of <NUM> - <NUM>, or more. As such, an etch process may be implemented by moving the chuck <NUM> between first and second predetermined positions relative to the first showerhead <NUM>. Alternatively, the chuck <NUM> may include a lifter <NUM> to elevate the substrate <NUM> off a top surface of the chuck <NUM> by distance H1 to control heating by the first showerhead <NUM> during the etch process. In other cases where the etch process is performed at a fixed temperature such as about <NUM>-<NUM> for example, chuck displacement mechanisms may be avoided. A system controller (not shown) may alternately energize the first and second plasmas <NUM> and <NUM> during the etching process by alternately powering the first and second RF coupled electrode pairs automatically.

Chamber <NUM> is included as a general chamber configuration that may be utilized for various operations discussed in reference to the present technology. The chamber is not to be considered limiting to the technology, but instead to aid in understanding of the processes described. Several other chambers known in the art or being developed may be utilized with the present technology including any chamber produced by Applied Materials Inc. of Santa Clara, California, or any chamber that may perform the techniques described herein.

<FIG> shows a cross-sectional view of an exemplary substrate processing chamber <NUM> with a partitioned region within substrate processing chamber <NUM>. The partitioned region will be referred to herein as a remote chamber region owing to the partitioning relative to substrate processing region <NUM>. A remote plasma system (RPS) <NUM> may be present on and external to substrate processing chamber <NUM> as shown. RPS <NUM> may be used to excite an inert gas supplied through inert supply line <NUM>. The plasma effluents formed in RPS <NUM> then travel into effluent mixing region <NUM> and combine with an oxidizing precursor supplied through oxidizing precursor supply line <NUM>.

A cooling plate <NUM>, faceplate <NUM>, ion suppressor <NUM>, showerhead <NUM>, and a substrate support <NUM> (also known as a pedestal), having a substrate <NUM> disposed thereon, are shown and may each be included. Pedestal <NUM> may have a heat exchange channel through which a heat exchange fluid flows to control the temperature of the substrate. This configuration may allow the substrate <NUM> temperature to be cooled or heated to maintain relatively low temperatures, such as between -<NUM> to <NUM>. Pedestal <NUM> may also be resistively heated to relatively high temperatures, such as between <NUM> and <NUM>, using an embedded heater element.

Effluent mixing region <NUM> opens into a gas supply region <NUM> partitioned from the remote chamber region <NUM> by faceplate <NUM> so that the gases/species flow through the holes in the faceplate <NUM> into the remote chamber region <NUM>. Structural and operational features may be selected to prevent significant backflow of plasma from the remote chamber region <NUM> back into gas supply region <NUM>, effluent mixing region <NUM>, and fluid supply system <NUM>. The structural features may include the selection of dimensions and cross-sectional geometries of the apertures in faceplate <NUM> to deactivate back-streaming plasma in cases where a plasma is generated in remote chamber region <NUM>. The operational features may include maintaining a pressure difference between the gas supply region <NUM> and remote chamber region <NUM> that maintains a unidirectional flow of plasma effluents through the showerhead <NUM>. The faceplate <NUM>, or a conductive top portion of the chamber, and showerhead <NUM> are shown with an insulating ring <NUM> located between the features, which allows an AC potential to be applied to the faceplate <NUM> relative to showerhead <NUM> and/or ion suppressor <NUM>. The insulating ring <NUM> may be positioned between the faceplate <NUM> and the showerhead <NUM> and/or ion suppressor <NUM> enabling a capacitively coupled plasma (CCP) to be formed in the remote chamber region. Remote chamber region <NUM> may be referred to as a chamber plasma region when used to form the remote plasma. However, no plasma is present in remote chamber region <NUM>. The inert gas may only be excited in RPS <NUM>.

The plurality of holes in the ion suppressor <NUM> may be configured to control the passage of the activated gas, i.e., the ionic, radical, and/or neutral species, through the ion suppressor <NUM>. For example, the aspect ratio of the holes, or the hole diameter to length, and/or the geometry of the holes may be controlled so that the flow of ionically-charged species in the activated gas passing through the ion suppressor <NUM> is reduced. The holes in the ion suppressor <NUM> may include a tapered portion that faces remote chamber region <NUM>, and a cylindrical portion that faces the showerhead <NUM>. The cylindrical portion may be shaped and dimensioned to control the flow of ionic species passing to the showerhead <NUM>. An adjustable electrical bias may also be applied to the ion suppressor <NUM> as an additional means to control the flow of ionic species through the suppressor. The ion suppression element <NUM> may function to reduce or eliminate the amount of ionically charged species traveling from the plasma generation region to the substrate. Uncharged neutral and radical species may still pass through the openings in the ion suppressor to react with the substrate.

Plasma power can be of a variety of frequencies or a combination of multiple frequencies. In the exemplary processing system the remote plasma may be provided by RF power delivered to faceplate <NUM> relative to ion suppressor <NUM> and/or showerhead <NUM>. The RF power may alternatively or in combination be applied within RPS <NUM>. The RF power may be between <NUM> watts and <NUM>,<NUM> watts, between <NUM> watts and <NUM>,<NUM> watts, between <NUM> watts and <NUM> watts, between <NUM> watts and <NUM> watts, or between <NUM> watts and <NUM> watts to increase the longevity of chamber components (e.g. RPS <NUM>) or for processing considerations. The RF frequency applied in the exemplary processing system to the remote plasma region (chamber plasma region and/or the RPS) may be low RF frequencies less than <NUM>, higher RF frequencies between <NUM> and <NUM>, or microwave frequencies greater than or about <NUM>. The plasma power may be capacitively-coupled (CCP) or inductively-coupled (ICP) into the remote plasma region.

Excited species derived from the inert gas in RPS <NUM> and/or remote chamber region <NUM> may travel through apertures in the ion suppressor <NUM>, and/or showerhead <NUM> and react with an oxidizing precursor flowing into substrate processing region <NUM> from a separate portion of the showerhead in examples, some being not according to the invention. Little or no plasma may be present in substrate processing region <NUM> during the remote plasma etch process. Excited derivatives of the precursors and inert gases may combine in the region above the substrate and/or on the substrate to etch structures or remove species from the substrate.

Examples, some being not according to the invention, of the dry etch systems may be incorporated into larger fabrication systems for producing integrated circuit chips. <FIG> shows one such processing system (mainframe) <NUM> of deposition, etching, baking, and curing chambers. In the figure, a pair of front opening unified pods (FOUPs) (load lock chambers <NUM>) supply substrates of a variety of sizes that are received by robotic arms <NUM> and placed into a low pressure holding area <NUM> before being placed into one of the substrate processing chambers 1508a-f. A second robotic arm <NUM> may be used to transport the substrate wafers from the holding area <NUM> to the substrate processing chambers 1508a-f and back. Each substrate processing chamber 1508a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes described herein in addition to cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, degas, orientation, and other substrate processes.

The specific details of particular embodiments may be combined in any suitable manner, the scope of the invention being defined by the claims.

The above description of example embodiments of the invention has been presented for the purposes of illustration and description.

Having described several examples, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present invention.

Claim 1:
A method of forming a stack of semiconductor layers, the method comprising:
depositing a first silicon oxide layer on a substrate;
depositing a first silicon layer on the first silicon oxide layer;
depositing a first silicon nitride layer on the first silicon layer, wherein depositing the first silicon nitride layer comprises:
flowing a gas comprising helium and silane or disilane through a plasma to form plasma effluents, wherein the plasma is sustained with an RF power, and
reducing stress in at least one of the first silicon layer, the first silicon oxide layer, or the substrate; and
depositing a second silicon layer on the first silicon nitride layer and forming the stack of semiconductor layers comprising the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer.