Patent Description:
As is known, semiconductor materials that have a wide band gap (e.g., that have an energy value Eg of the band gap greater than <NUM> eV), low ON-state resistance (RON), a high value of thermal conductivity, a high operating frequency, and a high saturation velocity of charge carriers, are ideal for producing electronic components, such as diodes or transistors, in particular for power applications. A material having such features, and designed to be used for manufacturing electronic components, is silicon carbide (SiC). In particular, silicon carbide, in its various polytypes (for example, 3C-SiC, <NUM>-SiC, <NUM>-SiC), is preferable to silicon in regards to the properties listed previously.

Electronic devices provided on a silicon-carbide substrate, as compared to similar devices provided on a silicon substrate, have numerous advantages, such as low ON-state output resistance, low leakage current, high output power, high operating temperature and high operating frequencies.

However, development and manufacture of SiC-based electronic devices are limited by factors such as the electrical and mechanical properties of passivation layers (which are comprised in said electronic devices and extend, for example, over SiC semiconductor bodies of the electronic devices). In particular, it is known to provide passivation layers using polymeric materials (e.g., polyimide), which make it possible to withstand high operating temperatures of the electronic devices and have high dielectric strength, for example, higher than <NUM> kV/mm. In detail, the high dielectric strength of the polymeric materials guarantees that the passivation layers will withstand high electrical fields, and consequently high potential differences across them, without undergoing electrical breakdown, and therefore without becoming electrically conductive.

However, polymeric materials have high coefficients of thermal expansion (CTEs) (e.g., CTE = 43e-<NUM> <NUM>/K for the material polybenzobisoxazole - PIX), and this causes problems of adhesion of the passivation layer to the SiC, which has a lower coefficient of thermal expansion (CTE = <NUM>. 8e-<NUM><NUM>/K).

In particular, the above problems of adhesion between the passivation layer and the SiC may arise during thermal cycling tests (carried out, for example, between approximately -<NUM> and approximately +<NUM>) or during use of the electronic device, when the latter is subjected to large temperature variations (e.g., it is subjected to differences of operating temperature equal to, or greater than, approximately <NUM>). On account of the large difference in CTE between the passivation layer and the SiC, said large temperature variations generate mechanical stresses at an interface between the passivation layer and the SiC, which can lead to a (at least partial) delamination of the passivation layer with respect to the SiC semiconductor body.

In the case where said delamination is sufficiently extensive (e.g., if it were such that there is no longer any portion of the passivation layer interposed between two metallizations of the electronic device at different potentials, which are therefore separated from one another just by air), electrical discharges can generate at this interface, leading to damage to the electronic device itself. In particular, the risk of damage to the electronic device increases when the latter is used in reverse-biasing conditions, on account of the high-voltage difference (e.g., greater than <NUM> V) to be withstood.

Known solutions to the above problem comprise the use of a plurality of dielectric layers of materials that are different from one another (e.g., silicon nitride, silicon oxide and polyimide in succession) to form a passivation multi-layer adapted to limit the mechanical stresses at the interface with the SiC semiconductor body. However, these solutions prove ineffective when the electronic devices are subjected to large temperature variations and to high voltage differences in reverse-biasing conditions.

Document <CIT> relates to electronic devices including insulating structures and processes of forming such electronic devices.

Document <CIT> relates to a method and apparatus for providing conformal electrical isolation in vias and other patterned structures in microelectronic, nanoelectronic, Micro-electromechanical Systems (MEMS), nano-electromechanical systems (NEMS), optical devices, and other types of devices.

Document <CIT> relates to a semiconductor device that includes a Schottky barrier diode and relates to a method for manufacturing the semiconductor device.

Document <CIT> relates to an electronic component, which has a semiconductor chip with an upper side, with a rear side and with lateral sides and also a plastic housing. In this case, the semiconductor chip is embedded in the plastic housing in such a way that the rear side and the lateral sides of the semiconductor chip are surrounded by a plastic molding compound, while the upper side of the semiconductor chip remains free from plastic molding compound. In addition, the invention relates to a method for producing the electronic component.

The aim of the present invention is to provide a manufacturing method of an anchorage element of an electronic device, an anchorage element, an electronic device and an electronic apparatus that will overcome the drawbacks of the known art.

According to the present invention, a manufacturing method of an anchorage element of an electronic device, an anchorage element, an electronic device and an electronic apparatus are provided as defined in the annexed claims.

For a better understanding of the present invention, a preferred embodiment is now described, purely by way of nonlimiting example, with reference to the attached drawings, wherein:.

Elements that are common to the various embodiments of the present invention, described in what follows, are indicated with the same reference numbers.

<FIG> shows, in lateral sectional view in a (triaxial) cartesian reference system of axes X, Y, Z, an electronic device (in detail, a merged-PiN-Schottky, MPS, device or junction-barrier Schottky, JBS, device) <NUM> according to an aspect of the present invention. In particular, the MPS device <NUM> is shown in <FIG> in a plane XZ defined by the axes X and Z, and is comprised in an electronic apparatus (not shown, such as a notebook, a mobile phone, a photovoltaic system, a traction inverter for electrical vehicles, etc.).

The MPS device <NUM> includes: a substrate <NUM>, of SiC of an N type, having a first dopant concentration, provided with a surface 53a opposite to a surface 53b, and having a thickness between the surfaces 53a and 53b comprised, for example, between <NUM> and <NUM>, more in particular between <NUM> and <NUM>, for example, <NUM>; a drift layer (grown in an epitaxial way) <NUM>, of SiC of an N type, having a second dopant concentration lower than the first dopant concentration and having a top surface 52a and a bottom surface 52b opposite to one another, the drift layer <NUM> extending over the surface 53a of the substrate <NUM> (in detail, the surfaces 53a and 52b are in contact with one another) and having a thickness between the surfaces 52a and 52b comprised, for example, between <NUM> and <NUM>; an ohmic-contact region, or layer <NUM> (for example, of nickel silicide), which extends over the surface 53b of the substrate <NUM>; a cathode metallization <NUM>, for example, of Ti/NiV/Ag or Ti/NiV/Au, which extends over the ohmic-contact region <NUM>; at least one doped region <NUM>' of a P type in the drift layer <NUM>, facing the top surface 52a of the drift layer <NUM> and, for each doped region <NUM>', a respective ohmic contact (not shown and of a known type; for example, each ohmic contact extends in depth, along the axis Z, within the respective doped region <NUM>' starting from the top surface 52a for a depth comprised between one nanometre and some tens of nanometres, measured starting from the top surface 52a, so as to be physically isolated from the drift layer <NUM> by the doped region <NUM>') so that each doped region <NUM>' will form a respective junction-barrier (JB) element <NUM> with the drift layer <NUM>; an edge-termination region, or protection ring, <NUM>, in particular a further doped region of a P type, which extends in the drift layer <NUM> facing the top surface 52a of the drift layer <NUM> and completely surrounds (parallelly to a plane XY defined by the axes X and Y) the JB elements <NUM>; an insulating layer <NUM> (optional), which extends over the top surface 52a of the drift layer <NUM> so as to completely surround (parallelly to the plane XY) the JB elements <NUM> and so as to overlap at least partially the protection ring <NUM>; an anode metallization <NUM>, for example, of Ti/AlSiCu or Ni/AlSiCu, which extends over a first portion of the top surface 52a, delimited on the outside by the insulating layer <NUM>, and which moreover optionally extends partially over the insulating layer <NUM>; and a passivation layer <NUM> of polymeric material such as polyimide (e.g., PIX), which extends over the anode metallization <NUM>, over the insulating layer <NUM>, and over a second portion of the top surface 52a that does not face either the anode metallization <NUM> or the insulating layer <NUM>.

One or more Schottky diodes <NUM> are formed at the interface between the drift layer <NUM> and the anode metallization <NUM>, alongside the doped regions <NUM>'. In particular, (semiconductor-metal) Schottky junctions are formed by portions of the drift layer <NUM> in direct electrical contact with respective portions of the anode metallization <NUM>.

In addition, each ohmic contact extending in the respective doped region <NUM>' provides an electrical connection having a value of electrical resistivity lower than the value of electrical resistivity of the doped region <NUM>' that houses it. The JB elements <NUM> are therefore P-i-N diodes formed by the doped regions <NUM>', by the drift layer <NUM> and by the substrate <NUM>.

The region of the MPS device <NUM> that includes the JB elements <NUM> and the Schottky diodes <NUM> (i.e., the region delimited on the outside by the protection ring <NUM>) is an active area <NUM> of the MPS device <NUM>.

The substrate <NUM> and the drift layer <NUM> form a semiconductor body <NUM> of the MPS device <NUM>. In details, the semiconductor body <NUM> is entirely made of SiC.

Externally to the active area <NUM>, and at a distance (along the axis X) from the insulating layer <NUM>, a lateral surface 80a of the semiconductor body <NUM> is present, which extends, for example, in a direction substantially orthogonal to the top surface 52a of the drift layer <NUM>. The lateral surface 80a is provided during manufacture of the MPS device <NUM>, and in particular during dicing of an SiC wafer where the MPS device <NUM> is provided. In other words, the lateral surface 80a is provided at a scribe line (not shown) of the SiC wafer out of which the MPS device <NUM> is made; said scribe line surrounds at a distance, in the plane XY, the active region <NUM>, the protection ring <NUM>, and the insulating layer <NUM>.

The passivation layer <NUM> moreover has an anchorage element <NUM>, which protrudes and extends into the drift layer <NUM>, beyond the top surface 52a, so as to anchor and fix the passivation layer <NUM> to the semiconductor body <NUM>.

The anchorage element <NUM> is interposed, parallelly to the axis X, between the active region <NUM> and the lateral surface 80a (in greater detail, between the insulating layer <NUM> and the lateral surface 80a).

The anchorage element <NUM> is shaped so as to fix the passivation layer <NUM> to the semiconductor body <NUM> (in particular, to the drift layer <NUM>) and is adapted to prevent delamination and detachment, at the active area <NUM>, of the passivation layer <NUM> with respect to the semiconductor body <NUM>.

In particular, the anchorage element <NUM> is housed and arranged by interlocking into a cavity <NUM>, which extends in the drift layer <NUM> starting from the top surface 52a, so as to couple and jointly fixing with respect to one another the passivation layer <NUM> and the semiconductor body <NUM>. The cavity <NUM> is delimited on the outside by a wall 83a of the drift layer <NUM>, having a shape complementary to a shape of the anchorage element <NUM>.

In particular, the anchorage element <NUM> comprises a plurality of portions (in particular, a first portion and a second portion 82a, 82b in <FIG>), which are arranged in succession with respect to one another along the axis Z and have respective dimensions, measured parallelly to the axis X, that increase in a direction away from the top surface 52a (and therefore, towards the bottom surface 52b).

In detail, with reference to the embodiment of <FIG>, the passivation layer <NUM> comprises a main body <NUM>' (which extends over the top surface 52a of the drift layer <NUM>, over the insulating layer <NUM>, and over the anode metallization <NUM>) and the anchorage element <NUM> (which extends in the drift layer <NUM>). Said second portion 82b is interposed, parallelly to the axis Z, between the main body <NUM>' of the passivation layer <NUM> and the first portion 82a and is monolithic with the first portion 82a (as well as with the main body <NUM>'). In other words, the first portion 82a is at a distance (e.g., measured parallelly to the axis Z starting from a centroid of the first portion 82a) from the bottom surface 52b of the drift layer <NUM> that is less than a distance (e.g., measured parallelly to the axis Z starting from a respective centroid of the second portion 82b) of the second portion 82b from said bottom surface 52b. The first portion 82a has a first maximum dimension measured parallelly to the axis X and having a first value d<NUM>, and the second portion 82b has a second maximum dimension measured parallelly to the axis X and having a second value d<NUM> that is smaller than the first value d<NUM>. In detail, the first value d<NUM> is measured parallelly to the axis X between surfaces 82a' and 82a" of the first portion 82a opposite to one another along the axis X, and the second value d<NUM> is measured parallelly to the axis X between surfaces 82b' and 82b" of the second portion 82b opposite to one another along the axis X. Moreover, the first portion 82a has, parallel to the Z axis, a respective maximum dimension having a fourth value, and the second portion 82b has, parallel to the Z axis, a respective maximum dimension having a fifth value that is greater than, equal to or lower than the fourth value; moreover, for example, the first portion 82a has, parallel to the Y axis that is orthogonal to the X axis and to the Z axis, a respective maximum dimension having a sixth value, and the second portion 82b has, parallel to the Y axis, a respective maximum dimension having a seventh value that is greater than, equal to or lower than the sixth value.

In <FIG>, the first and the second portions 82a, 82b each have, in the plane XZ, a substantially rectangular shape (alternatively, each have a polygonal shape, such as an oval shape), with respective major sides arranged so as to be parallel to the axis X and with respective minor sides (i.e., the surfaces 82a', 82a", 82b', 82b") arranged so as to be parallel to the axis Z; the two rectangular shapes are joined together at two of said major sides (in greater detail, between one of the major sides of the first portion 82a and one of the major sides of the second portion 82b, which face one another and are in contact with one another). In other words, the anchorage element <NUM> is substantially T-shaped, with minor base at the top surface 52a and major base facing the bottom surface 52b.

According to a different embodiment of the MPS device <NUM> shown in <FIG>, the anchorage element <NUM> has a greater number of portions than the MPS device <NUM> of <FIG> (in particular, it has four portions 82c-82f in <FIG>). The portions 82c-82f are similar to the portions 82a, 82b and have, respectively, dimensions d<NUM>-d<NUM> measured parallelly to the axis X, with d<NUM>>d<NUM>>d<NUM>>d<NUM>. In other words, the anchorage element <NUM> has a substantially pyramidal shape (in particular, that of a stepped truncated pyramid), with minor base at the top surface 52a and major base facing the bottom surface 52b.

In addition, optionally, the MPS device <NUM> comprises an equipotential-ring (EQR) metallization <NUM> (shown by way of example in <FIG>) extending over the insulating layer <NUM> and, optionally, on the top surface 52a so as to be opposite, parallelly to the axis X, to the anode metallization <NUM> with respect to the insulating layer <NUM>. In detail, in <FIG> the insulating layer <NUM> has surfaces 61a and 61b opposite to one another in a direction parallel to the axis X; the anode metallization <NUM> extends at the surface 61a, and the EQR metallization <NUM> extends at the surface 61b. For instance, in a top view and parallelly to the plane XY, the EQR metallization <NUM> extends externally to the insulating layer <NUM> and the active region <NUM>, so as to surround the insulating layer <NUM>. In addition, the EQR metallization <NUM> and the anode metallization <NUM> are physically and electrically separated from one another by the passivation layer <NUM>. In use, the EQR metallization <NUM> is set at the same voltage as the cathode metallization <NUM>.

<FIG> show the MPS device <NUM> in top view (parallelly to the plane XY), according to respective embodiments.

With reference to <FIG>, the anchorage element <NUM> extends in the plane XY so as to surround the anode metallization <NUM> completely. In the view in the plane XY of <FIG>, the anchorage element <NUM> is annular and defines a closed polygonal shape, and more in particular a square shape with chamfered corners (even though different shapes are also possible, such as circular, rectangular or triangular).

With reference to <FIG>, the MPS device <NUM> comprises at least one further anchorage element (similar to the anchorage element <NUM> and therefore indicated with the same reference number). The anchorage element <NUM> and the at least one further anchorage element <NUM> extend at a distance from one another at the top surface 52a, i.e., they extend in respective areas of the top surface 52a separate from one another. For instance, the view in the plane XY of <FIG> shows four anchorage elements <NUM> arranged around the anode metallization <NUM> so as to be angularly equispaced with respect to the anode metallization <NUM>, and in greater detail arranged at corners of a square shape with chamfered corners of the anode metallization <NUM>.

The manufacturing steps of the MPS device <NUM> of <FIG> are described in what follows, with reference to <FIG>.

With reference to <FIG>, a wafer is arranged including the substrate <NUM> of SiC (in particular <NUM>-SiC, however other polytypes may be used, such as, though not exclusively, <NUM>-SiC, 3C-SiC and <NUM>-SiC). For instance, the substrate <NUM> has a concentration of dopants of an N type comprised between <NUM>·<NUM><NUM> at/cm<NUM> and <NUM>·<NUM><NUM> at/cm<NUM>, and has a thickness, measured along the axis Z between the surfaces 53a and 53b, comprised between <NUM> and <NUM>, and in particular of approximately <NUM>. Formed on the surface 53a of the substrate <NUM>, for example by means of epitaxial growth, is the drift layer <NUM>. The drift layer <NUM> is of SiC, in particular <NUM>-SiC, but it is possible to use other SiC polytypes, such as <NUM>, <NUM>, 3C, or 15R. The drift layer <NUM> and the substrate <NUM> form the semiconductor body <NUM>. In the drift layer <NUM> there are then formed, according to known techniques and at the top surface 52a, the doped regions <NUM>' with the respective ohmic contacts, and the protection ring <NUM>. In addition, a first hard mask <NUM> is formed on the top surface 52a of the drift layer <NUM>, obtained, for example, by deposition of a photoresist, or TEOS, or another material designed for the purpose. The first hard mask <NUM> has a thickness of between <NUM> and <NUM> or in any case a thickness such as to shield the implantation described hereinafter with reference to <FIG>. The first hard mask <NUM> extends over the top surface 52a so as to leave exposed, in top view in the plane XY, a first region <NUM>' of the semiconductor body <NUM> where, in subsequent steps, the anchorage element <NUM> will be formed. In detail, the first region <NUM>' overlaps, parallelly to the axis Z, the region of the drift layer <NUM> where, in subsequent steps, the first portion 82a of the anchorage element <NUM> will be formed. The first region <NUM>' extends, parallelly to the axis X, between the protection ring <NUM> and the lateral surface 80a of the semiconductor body <NUM> and has a first maximum width l<NUM>, measured parallelly to the axis X, which is equal to, or approximately equal to, the first value d<NUM>.

With reference to <FIG>, a step of high-energy implantation of dopant species (having conductivity of a P or N type, such as boron, arsenic or aluminium) is then carried out, exploiting the first hard mask <NUM> (the implantation is represented in the figure by the arrows <NUM>). In an embodiment provided by way of example, the implantation step <NUM> comprises one or more implantations of dopant species, with implantation energy comprised between <NUM> keV and <NUM> keV and with doses of between <NUM>·<NUM><NUM> at/cm<NUM> and <NUM>·<NUM><NUM> at/cm<NUM>, to form a first implanted region <NUM> having a dopant concentration higher than <NUM>·<NUM><NUM> at/cm<NUM> and having a depth, measured starting from the top surface 52a, comprised between <NUM> and <NUM>. The first implanted region <NUM> therefore extends in depth into the drift layer <NUM>, at a distance (parallelly to the axis Z) from the top surface 52a. The first hard mask <NUM> is then removed, leaving the top surface 52a exposed.

With reference to <FIG>, on the top surface 52a of the drift layer <NUM> a second hard mask <NUM> is formed, for example by deposition of a photoresist, or TEOS, or another material designed for the purpose. The second hard mask <NUM> has a thickness of between <NUM> and <NUM> or in any case a thickness such as to shield the implantation described hereinafter with reference to <FIG>. The second hard mask <NUM> extends over the top surface 52a so as to leave exposed, in the top view in the plane XY, a second region <NUM>' of the semiconductor body <NUM> where, in subsequent steps, the second portion 82b of the anchorage element <NUM> will be formed. The second region <NUM>' overlaps, parallelly to the axis Z, the first implanted region <NUM> and has a second maximum width l<NUM>, measured in a direction parallel to the axis X, that is less than the first width l<NUM> and is equal to, or approximately equal to, the second value d<NUM>.

With reference to <FIG>, a step of low-energy implantation of dopant species (having the same conductivity as the implantation step <NUM>) is then carried out, exploiting the second hard mask <NUM> (the implantation is indicated in the figure by the arrows <NUM>). In an embodiment provided by way of example, the implantation step <NUM> comprises one or more implantations of dopant species, with implantation energy comprised between <NUM> keV and <NUM> keV and with doses of between <NUM>·<NUM><NUM> at/cm<NUM> and <NUM>·<NUM><NUM> at/cm<NUM>, to form a second implanted region <NUM> at the top surface 52a, having a dopant concentration higher than <NUM>·<NUM><NUM> at/cm<NUM> and having a maximum depth, measured starting from the top surface 52a, comprised between <NUM> and <NUM>. The second implanted region <NUM> therefore extends starting from the top surface 52a until the first implanted region <NUM> is reached; the first and second implanted regions <NUM> and <NUM> therefore join together to form an implanted anchorage region <NUM> having a shape that is the same as the shape of the anchorage element <NUM>.

With reference to <FIG>, at the second hard mask <NUM> and at the implanted anchorage region <NUM>, a step of thermal oxidation is carried out in order to oxidize the implanted anchorage region <NUM>, transforming the latter into silicon oxide (SiO<NUM>) and forming a corresponding oxidized anchorage region <NUM>' coincident with the implanted anchorage region <NUM>. In fact, it has been shown that the oxidation rate of SiC increases the more the crystal lattice of the SiC is damaged, for example by implantation of dopant species.

Consequently, the implanted anchorage region <NUM> is oxidized during the oxidation step, whereas the drift layer <NUM> (further protected thanks to the presence of the second hard mask <NUM>) does not substantially undergo oxidation. The step of thermal oxidation is, for example, carried out at a temperature higher than, or equal to, <NUM> (for example, between <NUM> and <NUM>) for a time comprised between <NUM> and <NUM>.

Moreover, with reference to <FIG>, etching (not shown) of the second hard mask <NUM> is carried out to selectively remove a portion of the second hard mask <NUM> so as to expose the active area <NUM>. In detail, said etching exposes the portion of the top surface 52a delimited on the outside, in the plane XY, by the protection ring <NUM> (i.e., the portion of the top surface 52a comprising the doped regions <NUM>' and part of the protection ring <NUM>, identified in what follows as first portion <NUM>) and, at least partially, the protection ring <NUM>.

With reference to <FIG>, the anode metallization <NUM> is formed on the first portion <NUM> of the top surface 52a exposed by the etch of <FIG> and on part of the second hard mask <NUM>. Consequently, the anode metallization <NUM> contacts the doped regions <NUM>' (by the respective ohmic contacts) and the drift layer <NUM> so as to form the JB elements <NUM> and, respectively, the Schottky diodes <NUM>; moreover, the anode metallization <NUM> extends over the part of the protection ring <NUM> exposed by the etch of <FIG> and over the second hard mask <NUM> at the protection ring <NUM>. For instance, the anode metallization <NUM> is formed by deposition of Ti/AlSiCu or Ni/AlSiCu.

With reference to <FIG>, a further etching (not shown) of the second hard mask <NUM> is carried out to remove a further portion of the second hard mask <NUM> (which is placed at the oxidized anchorage region <NUM>' and moreover extends between the oxidized anchorage region <NUM>' and the lateral surface 80a of the semiconductor body <NUM>) and the oxidized anchorage region <NUM>' so as to form the cavity <NUM>. In detail, the wall 83a of the drift layer <NUM>, which is exposed by the etch due to removal of the oxidized anchorage region <NUM>' and which delimits the cavity <NUM>, has a shape complementary to the shape of the oxidized anchorage region <NUM>', and therefore to the shape of the anchorage element <NUM>. In addition, the region of the second hard mask <NUM> that is not removed by said etch forms said insulating layer <NUM> of the MPS device <NUM>. The etch of <FIG> is of an isotropic type, and is carried out by hydrofluoric acid - HF.

With reference to <FIG>, the passivation layer <NUM> is then formed: the polymeric material is applied on the semiconductor body <NUM> and distributed through spinning over the anode metallization <NUM>, the insulating layer <NUM> and the exposed portion of the drift layer <NUM>, and a thermal process is subsequently carried out so that the polymeric material will harden to form the passivation layer <NUM> (curing process). In particular, during the spinning step the polymeric material penetrates into the cavity <NUM> and fills it, thus forming the anchorage element <NUM>.

Next, a step of grinding (not shown) of the substrate <NUM> is carried out on the surface 53b so as to reduce the thickness of the substrate <NUM>. For instance, at the end of the grinding step the substrate <NUM> has a thickness, measured along the axis Z between the surfaces 53a and 53b, comprised between <NUM> and <NUM>, and in particular of approximately <NUM>. The ohmic-contact layer <NUM> starting from the surface 53b of the substrate <NUM>, and the cathode metallization <NUM> starting from the ohmic-contact layer <NUM>, are then formed according to known techniques and in succession with respect to one another, thus obtaining the MPS device <NUM> shown in <FIG>.

From an examination of the features of the invention provided according to the present disclosure, the advantages that it affords are evident.

In particular, the anchorage element <NUM> guarantees adhesion of the passivation layer <NUM> to the semiconductor body <NUM>. In this way, it is possible to make the passivation layer <NUM> of polymeric materials, thus guaranteeing the high levels of electrical performance of the electronic device <NUM> (due to the high dielectric strength of the passivation layer <NUM>) and, at the same time, eliminating the risk of delamination of the passivation layer <NUM> following upon thermal cycles or use of the electronic device <NUM>.

Consequently, the risk of damage to the electronic device <NUM> following upon electrical discharges between metallizations set at different potentials (e.g., between the EQR metallization <NUM> and the anode metallization <NUM>) is prevented, and therefore the reliability of the electronic device <NUM> is increased, in particular when it is subjected to high temperature variations and operated in a reverse-biasing condition.

In particular, the manufacturing steps described with reference to <FIG> make it possible to provide the electronic device <NUM> comprising the anchorage element <NUM> starting from an SiC wafer.

In addition, the etch carried out with reference to <FIG> is of an isotropic type, and this makes it possible to pattern the cavity <NUM> and the anchorage element <NUM> without any limitations deriving from anisotropic etching processes and from the crystallographic orientation of the SiC wafer from which the electronic device <NUM> is obtained.

Finally, it is clear that modifications and variations may be made to the disclosure described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.

In particular, even though the EQR metallization <NUM> has been described with reference to <FIG>, it may likewise be present also in the embodiment of the MPS device <NUM> shown in <FIG>.

Claim 1:
A manufacturing method of an anchorage element (<NUM>) formed by a passivation layer (<NUM>) for an electronic device (<NUM>), comprising the steps of:
arranging a semiconductor body (<NUM>) of silicon carbide, SiC;
forming, in the semiconductor body (<NUM>) and at a distance from a top surface (52a) of the semiconductor body (<NUM>), a first implanted region (<NUM>) having, parallelly to a first axis (X) parallel to the top surface (52a), a maximum dimension having a first value (d<NUM>);
forming, in the semiconductor body (<NUM>), a second implanted region (<NUM>), which is superimposed, along a second axis (Z) orthogonal to the first axis (X) and to the top surface (52a), to the first implanted region (<NUM>), extends from the top surface (52a) to the first implanted region (<NUM>), and has, parallelly to the first axis (X), a respective maximum dimension having a second value (d<NUM>) smaller than the first value (d<NUM>);
carrying out a process of thermal oxidation of the first (<NUM>) and of the second (<NUM>) implanted regions to form an oxidized region (<NUM>') at the first (<NUM>) and the second (<NUM>) implanted regions;
removing said oxidized region (<NUM>') to form, in the semiconductor body (<NUM>) and at the oxidized region (<NUM>'), a cavity (<NUM>); and
forming, on the top surface (52a), the passivation layer (<NUM>) protruding into the cavity (<NUM>) to form said anchorage element (<NUM>) fixing the passivation layer (<NUM>) to the semiconductor body (<NUM>).