Patent Description:
Current mirrors are one of the few building blocks that are fundamental to the general circuit designs. In particular, broadband, linear current mirrors are one of the major founding blocks of open loop broadband linear amplifiers utilized within wide range of markets, such as communication, military, automotive, and industrial.

Designing current mirrors that can mirror their input current with a constant current gain to their outputs within a wide operating bandwidth in a linear fashion and in presence of the ever increasing fundamental input signal frequency is not trivial. At a given operating frequency, linearity and signal bandwidth of a current mirror ultimately set an upper bound to the dynamic range of an amplifier, or any other circuit in which a current mirror is used. Classically, linearity is traded off with bandwidth and power. Consequently, having current mirrors that have both high linearity and wide signal bandwidth would provide a significant competitive advantage in differentiating products in a given market.

<CIT> relates to a differential output circuit including first and second current mirror circuits.

<CIT> relates to a unity gain buffer amplifier.

<CIT> relates to a unity gain amplifier.

<CIT> relates to a bootstrapped application arrangement and application to the unity gain follower.

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings. According to an aspect, there is provided a current mirror arrangement as set out in claim <NUM>.

In one aspect, current mirror arrangements with adjustable offset buffers are disclosed. An example arrangement includes a current mirror circuit, configured to receive an input signal (e.g., an input current signal) at an input and output a mirrored signal (e.g., a mirrored current signal) at an output. The current mirror circuit includes an input transistor Q1 and an output transistor Q2. The arrangement further includes a buffer amplifier circuit (or, simply, a "buffer," also known as a unity gain amplifier, a buffer amplifier, a voltage follower, or an isolation amplifier) that has an input coupled to the input transistor Q1 and an output coupled to the output transistor Q2. The offset of the buffer amplifier circuit, generally defined as a difference between the voltages at the input and the output (or vice versa) of the buffer amplifier circuit, can be adjusted by including circuitry for an input or an output side offset adjustment or by implementing the buffer amplifier circuit as a diamond stage with individually controlled current sources for each of the transistors of the diamond stage. Providing an adjustable offset buffer in a current mirror arrangement may advantageously allow benefiting from the use of a buffer outside of a feedback loop of a current mirror (which may help solve stability issues associated with buffers included within the feedback loop of current mirrors and provide bandwidth and linearity improvements), while being able to reduce, minimize, or eliminate the buffer offset due to mismatch between master and slave sidesof the current mirror circuit (which could, otherwise, significantly degrade linearity). In general, the "master side" of a current mirror may refer to a branch of a current mirror circuit where the input signal is received, and the "slave side" of a current mirror may refer to a branch of a current mirror circuit where the output signal is provided. Thus, by including adjustable offset buffers in current mirror arrangements, as described herein, advantages of improved stability buffers may be realized while reducing or eliminating the negative effects of the buffer offsets that may be introduced by the buffers.

The exact design of the current mirror arrangements with adjustable offset buffers may be realized in many different ways, all of which being within the scope of the present disclosure. In one example of design variations according to various embodiments of the present disclosure, a choice can be made, individually for each of the transistors of a current mirror arrangement with an adjustable offset buffer), to employ bipolar transistors (e.g., where various transistors may be NPN or PNP transistors), field-effect transistors (FETs), e.g., metal-oxide-semiconductor (MOS) technology transistors (e.g., where various transistors may be N-type MOS (NMOS) or P-type MOS (PMOS) transistors), or a combination of one or more FETs and one or more bipolar transistors. In view of that, in the following descriptions, transistors are described with reference to their first, second, and third terminals. The term "first terminal" of a transistor is used to refer to a base terminal if the transistor is a bipolar transistor or to a gate terminal if the transistor is a FET, the term "second terminal" of a transistor is used to refer to a collector terminal if the transistor is a bipolar transistor or to a drain terminal if the transistor is a FET, and the term "third terminal" of a transistor is used to refer to an emitter terminal if the transistor is a bipolar transistor or to a source terminal if the transistor is a FET. These terms remain the same irrespective of whether a transistor of a given technology is an N-type transistor (e.g., an NPN transistor if the transistor is a bipolar transistor or an NMOS transistor if the transistor is a FET) or a P-type transistor (e.g., a PNP transistor if the transistor is a bipolar transistor or a PMOS transistor if the transistor is a FET).

In another example, in various embodiments, a choice can be made, individually for each of the transistors of a current mirror arrangement with adjustable offset buffers, as to which transistors are implemented as N-type transistors (e.g., NMOS transistors for the transistors implemented as FETs, or NPN transistors for the transistors implemented as bipolar transistors) and which transistors are implemented as P-type transistors (e.g., PMOS transistors for the transistors implemented as FETs, or PNP transistors for the transistors implemented as bipolar transistors). In yet other examples, in various embodiments, a choice can be made as towhat type of transistor architecture to employ. For example, any of the transistors of the current mirror arrangements with adjustable offset buffers as described herein that are implemented as FETs may be planar transistors or non-planar transistors such as FinFETs, nanowire transistors or nanoribbon transistors. Some example implementations of current mirror arrangements with adjustable offset buffers are shown in <FIG>. However, any implementation of the current mirror arrangement with adjustable offset buffers in line with the descriptions provided herein is within the scope of the present disclosure.

In some embodiments, the current mirror arrangements with adjustable offset buffers may be implemented as single-ended current mirror arrangements. In other embodiments, the current mirror arrangements may be implemented as differential current mirror arrangements, meaning that an example current mirror arrangement may include what is referred to herein as a "first portion" and a "second portion" and each of the portions may include a current mirror circuit and an adjustable offset buffer as described herein. The current mirror circuit of each portion may be configured to receive a respective (i.e., different) input signal (e.g., current) at an input and provide a respective output signal (e.g., current) at an output The current mirror circuit of each portion may include the input transistor Q1 and the output transistor Q2, each of which includes a first, a second, and a third terminals. In each portion, the second terminal of Q1 is coupled to the input of the current mirror circuit for the portion (i.e., coupled to the input signal for the portion) and also coupled to its own first terminal (i.e., to the first terminal of Q1), and the second terminal of Q2 is coupled to the output of the current mirror circuit for the portion (i.e., coupled to the output signal for the portion). Each portion may further includes an adjustable offset buffer, that has an input coupled to the input transistor Q1 and an output coupled to the output transistor Q2 of the portion. In some embodiments, the first portion may receive the input signal in the form of a first input current IINP that is based on a sum of a bias current IBCMA for the current mirror arrangement and a signal current IIN (e.g., IINP= IBCMA+IIN), while the second portion may receive the input signal in the form of a second input current IINM that is based on a difference between the bias current IBCMA and the signal current IIN (e.g., IINM= IBCMA-IIN). In such embodiments, the output current of the first portion may be IOP=K*IINP, while the output current of the second portion may be IOM=K*IINM. Thus, for each portion of a differential current mirror arrangement, a ratio of the output signal to the input signal may be substantially equal to K, where K is a current gain which may be any positive number greater than <NUM>, which value may, but does not have to be, an integer. For the bipolar implementation embodiments, the value of K may be indicative of (e.g., be equal to or be based on) a ratio of an area of the emitter of the output transistor Q2 to an area of the emitter of the input transistor Q1. For the FET implementation embodiments, the value of K may be indicative of a ratio of the aspect ratio of the output transistor Q2 to the aspect ratio of the input transistor Q1, where an aspect ratio of a FET transistor may be defined as a channel width of the transistor divided by its' channel length. In the embodiments where K is greater than <NUM> but less than <NUM>, multiplying by a factor of K means attenuating the input signal to generate the output signal. In the embodiments where K is greater than <NUM>, multiplying by a factor of K means increasing, or gaining, the input signal to generate the output signal.

As will be appreciated by one skilled in the art, aspects of the present disclosure, in particular aspects of current mirror arrangements with adjustable offset buffers, as described herein, may be embodied in various manners- e.g., as a method or as a system. The following detailed description presents various descriptions of specific certain embodiments. However, the innovations described herein can be embodied in a multitude of different ways, for example, as defined and covered by the claims or select examples. For example, while some of the descriptions are provided herein with respect to either bipolar (e.g., NPN or PNP implementations) orfield-effect (e.g., NMOS or PMOS implementations) transistors, further embodiments of the current mirror arrangements described herein may include any combinations of bipolar transistors and FETs.

In the following description, reference is made to the drawings where like reference numerals can indicate identical or functionally similar elements. It will be understood that elements illustrated in the drawings are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

The description may use the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. Various aspects of the illustrative embodiments are described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term "connected" means a direct electrical connection between the things that are connected, without any intermediary devices/components, while the term "coupled" means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices/components. In another example, the term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms "substantially," "approximately," "about," etc., may be used to generally refer to being within +/- <NUM>% of a target value, e.g., within +/- <NUM>% of a target value, based on the context of a particular value as described herein or as known in the art. For the purposes of the present disclosure, the phrase "A and/or B" or notation "A/B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A, B, and/or C).

For purposes of illustrating current mirror arrangements with adjustable offset buffers, proposed herein, it might be useful to first understand phenomena that may come into play when current is mirrored. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

<FIG> provides an electric circuit diagram of a simple single-ended NPN bipolar transistor implementation of a current mirror <NUM> with a current gain of K, as known in the art. As shown in <FIG>, the current mirror <NUM> may include a first transistor Q1 (which may be referred to as an "input transistor") and a second transistor Q2 (which may be referred to as an "output transistor"). An input current <NUM> (IIN) (i.e., the current to be mirrored at the output of the current mirror <NUM> to generate an output current <NUM>) may be provided by an input current source <NUM>. The current mirror <NUM> may first generate a control voltage (voltage VN1) at a node <NUM> (node N1) by placing the transistor Q1 in feedback to force the current at a collector terminal <NUM> (or, simply, "collector" <NUM>) of the transistor Q1 to be equal to the input current <NUM>. An emitter terminal <NUM> (or, simply, "emitter" <NUM>) of the transistor Q1 may be connected to ground, as shown in <FIG>. A base terminal <NUM> (or, simply, "base" <NUM>) of the transistor Q1 may be coupled to a base <NUM> of the transistor Q2. The base <NUM> of the output transistor Q2 may be driven with the voltage VN1 carrying the input current information to generate the output current <NUM>. <FIG> also indicates a collector <NUM> of the transistor Q2 and an emitter <NUM> of the transistor Q2, where the emitter <NUM> may be coupled to ground and where the output current <NUM> is the current at the collector <NUM>, as shown in <FIG>. When the emitter area of the transistor Q2 is K times larger than that of the transistor Q1, the output current <NUM> (Io) may be equal to K · IIN.

The simplified model of a bipolar transistor collector current is given by <MAT> where IC, A, IS, VBE and Vt are collector current, emitter area, unit area saturation current, the base-emitter voltage and thermal voltage, respectively. Although the relation between collector current (IC) to base-emitter voltage (VBE), or, equivalently input current IIN and the voltage VN1, is strongly nonlinear, the input-output current mirroring relation is linear, i.e. IO = K · IIN.

The basic analysis given above has many shortcomings in understanding the performance degradation of current mirrors at high operating frequencies. <FIG> provides an electric circuit diagram of an NPN implementation of a current mirror <NUM>. The current mirror <NUM> is substantially the same as the current mirror circuit <NUM> of <FIG>, except that it additionally illustrates relevant parasitic components for high operating frequencies. In other words, <FIG> illustrates important parasitic devices that may degrade the bandwidth and the linearity of the circuit <NUM>. It is to be understood that parasitic components shown in the present drawings and discussed herein refer to components which are not deliberately fabricated in a circuit, but, rather, electric circuit diagram representations of inadvertent effects or behavior that may be exhibited by a circuit.

Elements of <FIG> having reference numerals shown in <FIG> are intended to illustrate the same or analogous elements as those described with respect to <FIG>, so that, in the interest of brevity, their descriptions are not repeated. This is applicable to other figures of the present disclosure - elements with reference numerals described with reference to one figure may be the same or analogous as elements with the same reference numerals shown in another figure, so that descriptions provided for one figure are applicable to the other figure and don't have to be repeated.

The current mirror <NUM> may be affected by one of more of a parasitic capacitance <NUM>, a parasitic capacitance <NUM>, a parasitic capacitance <NUM>, a parasitic capacitance <NUM>, and a resistance <NUM> (which may be used to convert the output current of the current mirror to voltage), each of which coupled as shown in <FIG>.

The parasitic capacitance <NUM> may represents all routing parasitic capacitances associated with the node <NUM>, parasitic capacitance of <NUM> input current source loading node <NUM>, as well as collector-substrate capacitance and extrinsic base terminal parasitic capacitors of the transistors Q1 and Q2. Note that the modern SOI process based bipolar transistor collector-substrate capacitor is relatively small and can be treated as being linear. The parasitic capacitance <NUM> may represent the intrinsic base-emitter forward-bias diffusion capacitance of the transistor Q1. The parasitic capacitance <NUM> may represent the intrinsic base-emitter forward-bias diffusion capacitance of the transistor Q2 (and may be K times larger than the parasitic capacitance <NUM> if the emitter area of the transistor Q2 is K times larger than that of the transistor Q1). The parasitic capacitance <NUM> may represent the intrinsic base-collector junction parasitic capacitance of the transistor Q2. The resistance <NUM> may represent an output resistance (RO) of the current mirror <NUM>/<NUM>.

Inventors of the present disclosure realized that, as can be seen from the analysis of the circuit in <FIG>, three distinct mechanisms degrading the bandwidth and/or the linearity of the current mirror may be identified for bipolar transistor implementations. One is bandwidth degradation due to the parasitic capacitors. Another one is linearity degradation due to nonlinearity of the intrinsic base-collector junction parasitic capacitance (e.g., the parasitic capacitance <NUM>, shown in <FIG>). The third one is linearity degradation due to linear parasitic capacitance <NUM>.

Similarly, a number of linearity degradation mechanisms may be identified for FET implementations of current mirror circuits. One degradation mechanism for the FET implementations is bandwidth degradation due to the parasitic capacitors, similar to the bipolar implementations. Another one is linearity degradation due to linear capacitive load on node <NUM>. The third one is linearity degradation due to gate-drain capacitance CGD.

Inventors of the present disclosure further realized that improving on at least some of these degradation mechanisms could provide an improvement in terms of designing linear broadband current mirrors.

A typical solution to overcome the limitation(s) associated with high operating frequencies (thus overcoming the bandwidth limitations) of a simple current-mirror is to add a buffer between the collector of the transistor Q1 and the bases of the transistors Q1 and Q2, as shown in <FIG>.

<FIG> provides an electric circuit diagram of an NPN implementation of a current mirror <NUM> with a buffer <NUM> in a feedback path (i.e., a path between the collector <NUM> of the transistor Q1 and the base <NUM> of the transistor Q1). The current mirror <NUM> is substantially the same as the current mirror circuit <NUM> of <FIG>, except that it additionally illustrates the buffer <NUM>. Such a modification of the current mirror <NUM> may drastically reduce capacitance across the diode-connected transistor Q1 and, therefore, significantly improve the bandwidth of the circuit. Buffering may also improve the linearity of the circuit by reducing the impacts of the parasitic capacitances portion of <NUM> associated with the transistor Q2 and the parasitic capacitance <NUM>. For example, buffering may lower the impact of the nonlinear currents associated with the parasitic capacitance <NUM> by (K + <NUM>) times. However, the non-idealities of the buffer <NUM> itself may make the stability of the circuit <NUM> challenging (note that node <NUM> may be a high impedance node for this configuration) such that by the time the circuit <NUM> is made stable, the high-frequency performance is not that much better than of the circuit <NUM>.

In some implementations, the buffer <NUM> can be moved outside the feedback loop such that the stability is no longer an issue. This is shown in <FIG>, providing an electric circuit diagram of an NPN implementation of a current mirror <NUM> with a buffer <NUM> between the base terminals of the transistors Q1 and Q2. The buffer <NUM> may be a unity gain amplifier, a buffer amplifier, a voltage follower, or an isolation amplifier.

In <FIG> and subsequent drawings, the "master side" may refer to components of a given current mirror shown to the left of the buffer between the base or gate terminals of the transistors Q1 and Q2 (the master side labeled in <FIG> as a portion <NUM> within a dotted contour), i.e., to the left of a vertical dashed line <NUM> shown in <FIG>, while the "slave side" may refer to components of a given current mirror shown to the right of that buffer (the slave side labeled in <FIG> as a portion <NUM> within a dotted contour), i.e., to the right of the line <NUM>. The current mirror <NUM> is substantially the same as the current mirror circuit <NUM> of <FIG>, except that it additionally illustrates the buffer <NUM> provided between the master side <NUM> and the slave side <NUM>. As shown in <FIG>, in such a configuration, the collector <NUM> and the base <NUM> of the transistor Q1 are shorted and connected to an input <NUM> of the buffer <NUM>, while an output <NUM> of the buffer <NUM> is connected to the base <NUM> of Q2. Compared to the buffer <NUM> shown in the arrangement of <FIG>, although moving the buffer out of the feedback loop to implement it as the buffer <NUM> may solve the stability issue and provide bandwidth and linearity improvements, the buffer <NUM> may be associated with an offset that may become an issue in this scenario since it may cause the standing current in the transistor Q2 to be off, degrading linearity due to mismatch between the master side and the slave side. As is known in the art, a buffer is, basically, a component that is supposed to regenerate an output voltage substantially identical to its input voltage (i.e., gain should be equal to <NUM>). As also known in the art, an offset error (or, simply, "offset" or a "buffer offset") is one type of non-idealities of buffers, where the offset error modifies the transfer function of a buffer from being desired y=x (where y is an output of the buffer and x is the input of the buffer) to y=x+off, where "off" is the buffer offset. Thus, in general, "buffer offset" refers to a DC quantity (i.e., not frequency-dependent) meaning that, assuming that a buffer has an infinite bandwidth, then when the input voltage is subtracted from the output voltage of the buffer then the difference will be equal to the offset voltage for any input frequency.

In general, different techniques may be implemented to improve on one or more of the problems described above, where some tradeoffs may have to be made, e.g., in trading performance with complexity. Embodiments of the present disclosure aim to address/limit the nonlinearity and the bandwidth degradation related to one or more of the base-emitter junction parasitic capacitance <NUM> of the transistor Q2, part of the parasitic capacitance <NUM> associated with the transistor Q2, and the miller-amplified base-collector junction parasitic capacitance <NUM> of the transistor Q2, described above. The nonlinear base-collector junction parasitic capacitance can be quite large due to the large quiescent current at the output of the current mirror, common for broadband designs. The base-collector junction parasitic capacitance may convert the output signal swing to a nonlinear current at the output node and load the diode side of the current mirror, hence degrading the overall linearity, as well as also reducing the current mirror bandwidth due to miller effect. Embodiments of the present disclosure are based on recognition that implementing buffering in current mirror arrangements may provide an improvement with respect to reducing nonlinearity related to the base-collector junction parasitic capacitance <NUM> of the transistor Q2 and the base-emitter junction parasitic capacitance <NUM>.

More specifically, embodiments of the present disclosure are based on recognition that the issue of the standing current and buffer offset, described above, may be addressed by reducing the buffer offset as much as possible for a given design (e.g., by eliminating the buffer offset altogether). In particular, embodiments of the present disclosure are based on providing means for adjusting (e.g., reducing) the buffer offset so that the impact of the buffer offset of the buffer <NUM> on the standing current of the transistor Q2 may be contained within acceptable limits (e.g., so that the current mirror arrangement's nonlinearity which, if no precautions are taken, may inadvertently be present due to inclusion of one or more buffers, may be reduced or eliminated). In the following sections, three different approaches to providing adjustable offset buffers in current mirror arrangements will be described. The first approach is described with reference to <FIG> and may be referred to as an adjustable offset buffer with a diamond stage. The second approach is described with reference to <FIG> and may be referred to as an adjustable offset buffer with an input side adjustment. The third approach is described with reference to <FIG> and may be referred to as an adjustable offset buffer with an output side adjustment. In various embodiments, a current mirror arrangement may implement any one or any combination of these approaches.

<FIG> provides an electric circuit diagram of a bipolar implementation of a current mirror arrangement <NUM> with a buffer amplifier circuit implemented as an adjustable offset buffer <NUM> with a diamond stage, according to some embodiments of the disclosure. In some embodiments, the buffer <NUM> may be implemented instead of the buffer <NUM> in a current mirror arrangement as shown in <FIG>, i.e., with the base <NUM> of the input transistor Q1 (or, more generally, with the first terminal of the input transistor Q1 of a current mirror circuit) coupled to an input <NUM> of the buffer <NUM>, while an output <NUM> of the buffer <NUM> is coupled to the base <NUM> of the output transistor Q2 (or, more generally, with the first terminal of the output transistor Q2 of the current mirror circuit). The input <NUM> of the buffer <NUM> may be coupled to the master side <NUM> of the current circuit arrangement <NUM>, with the details of the master side <NUM> not specifically shown in <FIG>, but which could be implemented similar to the master side <NUM> shown in <FIG>. The output <NUM> of the buffer <NUM> may be coupled to the slave side <NUM> of the current circuit arrangement <NUM>, with the details of the slave side <NUM> not specifically shown in <FIG>, but which could be implemented similar to the slave side <NUM> shown in <FIG>. Thus, the current mirror circuit of the current mirror arrangement <NUM> may include the input transistor Q1 and the output transistor Q2 as described with reference to <FIG>, and the buffer amplifier circuit of the current mirror arrangement <NUM> may be implemented as the buffer <NUM>, shown in <FIG>, the details of which will now be described.

In accordance with the invention, adjustable offset buffer is realized by implementing the buffer <NUM> as a diamond buffer that includes a plurality of transistors and by further including what may be referred to as a "buffer offset reduction circuit," configured to adjust bias currents provided by different current sources to individual transistors of the plurality of transistors of the diamond buffer so that a voltage difference between the output and the input of the buffer amplifier <NUM> (i.e., the buffer offset) is below a target value.

As shown in <FIG>, the plurality of transistors of the diamond buffer includes transistors QD1P and QD1N, forming what is referred to as a "first stage" of the diamond buffer, and further includes transistors QD2N and QD2P, forming what is referred to as a "second stage" of the diamond buffer. In some embodiments, as shown in <FIG>, the transistors of the first stage may be arranged to form an emitter follower, while the transistors of the second stage may be arranged to form a class-ab buffer. The transistors QD1P and QD2P may be P-type transistors, e.g., PNP transistors for the bipolar implementation such as the one shown in <FIG>, or may be PMOS transistors for the FET implementation of the buffer <NUM> (not specifically shown in the present drawings). The transistors QD1N and QD2N may be N-type transistors, e.g., NPN transistors for the bipolar implementation such as the one shown in <FIG>, or may be NMOS transistors for the FET implementation of the buffer <NUM> (not specifically shown in the present drawings). To be applicable to both bipolar and FET implementations, transistor terminals of the buffer <NUM> are referred to as first, second, and third terminals in accordance with the use of these terms that was described above. Thus, the first terminals of the transistors QD1P and QD1N may be coupled to one another and both be coupled to the input <NUM> of the buffer <NUM>, while the second terminals of the transistors QD1P and QD1N may be coupled to the supply and ground potential, as shown in <FIG>. The second terminals of the transistors QD2N and QD2P may be coupled to the supply and ground voltage, as shown in <FIG>, while the third terminals of the transistors QD2N and QD2P may be coupled to one another and to the output <NUM> of the buffer <NUM>. In some embodiments, the third terminal of the transistor QD2N may be coupled to the output <NUM> via a resistor R1N, while the third terminal of the transistor QD2P may be coupled to the output <NUM> via a resistor R1P, as shown in <FIG>. The first terminals of the transistors QD2N and QD2P may be coupled to the third terminals of the transistors QD1P and QD1N, respectively.

In some embodiments, the first terminal of the transistor QD2N may be coupled to the third terminal of the transistor QD1P via a resistor ROP, while the first terminal of the transistor QD2P may be coupled to the third terminal of the transistor QD1N via a resistor RON, as shown in <FIG>. In some embodiments, the values of the resistors R1N and R1P may be substantially equal, e.g., as denoted by a value RE illustrated near these resistors in the buffer <NUM> shown in <FIG>. In some embodiments, the values of the resistors RON and ROP may also be substantially equal and may be about <NUM> times than the value of the resistor R1N (or the resistor R2N), e.g., as denoted by a value <NUM>. RE illustrated near the resistors R1N and R2N in the buffer <NUM> shown in <FIG>. In such embodiments, M may be a positive number greater than <NUM>, indicative of a ratio of an area of the emitter of the transistor QD2N to an area of the emitter of the transistor QD1N when the transistors QD2N and QD1N are bipolar transistors, and indicative of a ratio of an aspect ratio of the transistor QD2N to an aspect ratio of the transistor QD1N when the transistors QD2N and QD1N are FETs. Similar relation may apply to the transistors QD2P and QD1P, i.e., M may be indicative of a ratio of an area of the emitter of the transistor QD2P to an area of the emitter of the transistor QD1P when the transistors QD2P and QD1P are bipolar transistors, and indicative of a ratio of an aspect ratio of the transistor QD2P to an aspect ratio of the transistor QD1P when the transistors QD2P and QD1P are FETs. Thus, although the emitter areas of PNP and NPN transistors of the diamond buffer of the buffer <NUM> may, and typically would be, different from one another, the relationship in the emitter area of the PNP transistors of the first and second stages of the diamond buffer (i.e., the emitter area of QD2P being M times the emitter area of QD1P) would be substantially the same as the relationship in the emitter area of the NPN transistors of the first and second stages of the diamond buffer (i.e., the emitter area of QD2N being M times the emitter area of QD1N). For the FET implementation of the transistors of the diamond buffer of the buffer <NUM> this means, that although the aspect ratios of PMOS and NMOS transistors of the diamond buffer of the buffer <NUM> may, and typically would be, different from one another, the relationship in the aspect ratio of the PMOS transistors of the first and second stages of the diamond buffer (i.e., the aspect ratio of QD2P being M times the aspect ratio of QD1P) would be substantially the same as the relationship in the aspect ratio of the NMOS transistors of the first and second stages of the diamond buffer (i.e., the aspect ratio of QD2N being M times the aspect ratio of QD1N). Coupled with the buffer offset reduction circuit, such dimensions of the P-type and N-type transistors of the diamond buffer and such relations between the resistors R1P, ROP, R1N, and RON in the buffer <NUM> may realize the adjustable buffer offset of the buffer <NUM>.

Turning to the buffer offset reduction circuit of the buffer <NUM>, such a circuit may include a plurality of current sources coupled to the plurality of the transistors of the diamond buffer of the buffer <NUM> and configured to provide bias currents to these transistors. In some embodiments, the current sources of the buffer offset reduction circuitof the buffer <NUM> may be implemented as transistors, e.g., as transistors having their base/gate voltage controlled to carefully control the current output by the transistors. This is illustrated in <FIG> with the current sources coupled to the transistor QD1P being implemented as a first current source in a form of a transistor QBPO and as a second current source in a form of a transistor QBP1 (i.e., both QBP0 and QBP1 are biasing the transistor QD1P, the sum of the currents from QBP0 and QBP1 being constant, hence, the current to QD1P is constant, and only the ratio of these currents changing depending on parameter α, as described herein). This is illustrated in <FIG> with the current sources coupled to the transistor QD1N being implemented as a first current source in a form of a transistor QBN0 and as a second current source in a form of a transistor QBN1 (i.e., both QBN0 and QBN1 are biasing the transistor QD1N, the sum of the currents from QBN0 and QBN1 being constant, hence, the current to QD1N is constant, and only the ratio of these currents changing depending on parameter α, as described herein). In some embodiments, the transistors QBP0 and QBP1 may be P-type transistors, e.g., PNP transistors as shown in <FIG>, where the first terminal of each of the transistors QBP0 and QBP1 is coupled to a respective different voltage source configured to apply, respectively, voltages VP0 and VP1 to the first terminals of the transistors QBP0 and QBP1. The second terminal of the transistor QBP0 may be coupled to the third terminal of the transistor QD1P, while the third terminal of the transistor QBP0 may be coupled to the supply voltage. The second terminal of the transistor QBP1 may be coupled to the first terminal of the transistor QD2N, while the third terminal of the transistor QBP1 may be coupled to the supply voltage. In some embodiments, the transistors QBN0 and QBN1 may be N-type transistors, e.g., NPN transistors as shown in <FIG>, where the first terminal of each of the transistors QBN0 and QBN1 is coupled to a respective different voltage source configured to apply, respectively, voltages VN0 and VN1 to the first terminals of the transistors QBN0 and QBN1. The second terminal of the transistor QBN0 may be coupled to the third terminal of the transistor QD1N, while the third terminal of the transistor QBN0 may be coupled to the ground potential. The second terminal of the transistor QBN1 may be coupled to the first terminal of the transistor QD2P, while the third terminal of the transistor QBN1 may be coupled to the ground potential. Thus, the current sources QBP0, QBN0, QBP1, and QBN2 can be configured to provide bias currents to the first stage transistors of the diamond buffer of the buffer <NUM>, with two different current sources coupled to each of the two first stage transistors. Coupling each of the first stage transistors of the diamond buffer to two different current sources allows modifying the distribution of the total bias current between the different current sources so that the buffer offset of the buffer <NUM> is below a target value. The resistor R0P may be coupled so that one terminal of the resistor R0P is coupled to the third terminal of the transistor QD1P and to the current source QBP0 (e.g., to the second terminal of the transistor QBP0), while the other terminal of the resistor R0P is coupled to the first terminal of the transistor QD2N and to the current source QBP1 (e.g., to the second terminal of the transistor QBP1). Similarly, the resistor RON may be coupled so that one terminal of the resistor R0N is coupled to the third terminal of the transistor QD1N and to the current source QBN0 (e.g., to the second terminal of the transistor QBN0), while the other terminal of the resistor RON is coupled to the first terminal of the transistor QD2P and to the current source QBN1 (e.g., to the second terminal of the transistor QBN1). By controlling the control signals VP0, VN0, VP1, and VN1 applied to, respectively, the transistors QBP0, QBN0, QBP1, and QBN1 may be configured to output currents such that a voltage difference between the output and the input of the buffer amplifier (i.e., the buffer offset) is below a target value.

In order to reduce the buffer offset of the buffer <NUM>, the current sources QBP0, QBN0, QBP1, and QBN2 are controlled to generate currents that have a certain relation between one another. In particular, considering that the current generated by the current source QBP0 may be denoted as IP0, the current generated by the current source QBN0 may be denoted as IN0, the current generated by the current source QBP1 may be denoted as IP1 and the current generated by the current source QBN1 may be denoted as IN1, the current sources QBP0, QBN0, QBP1, and QBN2 may be controlled so that <MAT> <MAT> <MAT> The current IBBAC in the equation (<NUM>) is a bias current for the buffer amplifier circuit <NUM>, which may, but in general, does not have to be, the same as the bias current IBCAM for the current mirror arrangement <NUM>. The current IBBAC is the current at the third terminal of the transistor QD1P and QD1N, which may also be the current at the second terminal of the transistor QD1P and QD1N.

Equations (<NUM>)-(<NUM>) make clear that a parameter α may be defined that sets the percentage of the bias current IBBAC being in each of IN0 and IN1, and in each of IP0 and IP1. For example, defining the parameter a as a portion of the bias current IBBAC provided as IN0, equations (<NUM>)-(<NUM>) may be re-written as follows: <MAT> <MAT> <MAT> <MAT>.

Analysis of the buffer <NUM> reveals that the buffer offset VN1,N3, i.e., the difference in the voltage VN1 at the input <NUM> (node N1, labeled in <FIG>) and the voltage VN3 at the output <NUM> (node N3, labeled in <FIG>) of the buffer <NUM> is a function of the parameter α and a function of the resistance values of the resistors R0P, R0N, R1P, and R1N, described above, and may be written as follows: <MAT> where VT is the thermal voltage (which is approximately <NUM> Volts at <NUM> degrees Kelvin and may be computed for other temperatures in terms of the temperature and the Boltzmann constant), IS_N is the reverse saturation current of the NPN transistors of the diamond buffer portion of the buffer <NUM> (i.e., transistors QD1N and QD2N), and IS_P is the reverse saturation current of the PNP transistors of the diamond buffer portion of the buffer <NUM> (i.e., transistors QD1P and QD2P). Analysis of the buffer <NUM> further reveals that, if the current IBBAC is the current of QD1P and QD1N of the buffer <NUM>, then the current at the output of the buffer <NUM>, e.g., the current at the second terminal of the transistor QD2N and QD2P is substantially equal to M times of the current IBBAC.

Analysis of the equation (<NUM>) reveals that if the NPN and the PNPtransistors of the diamond buffer portion of the buffer <NUM> are matched (i.e., if IS_N is equal to IS_P), then the buffer offset may be eliminated (i.e., VN1,N3=<NUM>) if α is equal to <NUM>. Since α is a value between (and including) <NUM> and <NUM> (i.e., <NUM> ≤ α ≤ <NUM>), when the NPN and the PNP transistors of the diamond buffer portion of the buffer <NUM> are matched, setting α to a particular value may be used to define the amount of buffer offset anywhere in the range between (and including) -RE·M·IBBAC and RE·M·IBBAC (i.e., -RE·M·IBBAC ≤ VN1,N3 ≤ RE·M·IBBAC). If, on the other hand, the NPN and the PNP transistors of the diamond buffer portion of the buffer <NUM> are not matched (i.e., if IS_N is not equal to IS_P), then the buffer offset may be eliminated by setting α to a value that would result in the buffer offset being equal to <NUM>. Thus, adjusting the value of α, i.e., adjusting how much of a total bias current IBBAC is in the current INO and how much is in the current IN1 (or, equivalently, how much of the total bias current IBBAC is in the current IP0 and how much is in the current IP1), can adjust the amount of the buffer offset of the buffer <NUM>. In turn, adjusting the current IN0, IN1, IP0, and IP1 may be done by controlling the voltages VN0, VN1, VP0, and VP1, respectively. In general, the voltages VN0, VN1, VP0, and VP1 of values corresponding to, respectively, the current sources QBN0, QBN1, QBP0, and QBP1 producing the currents IN0, IN1, IP0, and IP1 as described herein may be generated using any circuit or logic component. <FIG> illustrates one example circuit that may be used, in context of a differential current mirror arrangement of <FIG>, to generate the voltages VN0, VN1, VP0, and VP1 so that the currents IN0, IN1, IP0, and IP1 are defined so as to eliminate the buffer offset of the buffer <NUM>.

To summarize the above description of the relations between the currents, the current sources QBP0, QBN0, QBP1, and QBN1 are configured to output currents such that <NUM>) a current IP0, output by the current source QBP0, is substantially equal to a current IN1, output by the current source QBN1, <NUM>) a current IP1, output by the current source QBP1, is substantially equal to a current IN0, output by the current source QBN0, and <NUM>) a sum of the current IN0 and the current IN1 is substantially equal to a sum of the current IP0 and the current IP1 (where each of the sums is denoted as the bias current IBBAC). The bias current IBBAC is the bias current of the emitter follower first stage of the diamond buffer circuit of the buffer <NUM>. The degeneration resistors RE and <NUM>. RE may help ensure that the bias current of the class-AB second stage of the diamond buffer circuit of the buffer <NUM> is equal to M times IBBAC. In such configuration, a proportion of the current IP0 in the IBBAC (i.e., a proportion of the current IP0 in the sum of the current IP0 and the current IP1, or, equivalently, one or more of: a proportion of the current IP1 in the sum of the current IP0 and the current IP1, a proportion of the current IN0 in the sum of the current IN0 and the current IN1, and a proportion of the current IN1 in the sum of the current IN0 and the current IN1) may be selected so that a voltage difference between the output <NUM> and the input <NUM> of the buffer amplifier circuit <NUM> (the voltage difference being the buffer offset VN1,N3) is below a target value. The transistors QD1P, QD1N, QD2P, and QD2N may be coupled to one another so that <NUM>) the current IP0 is combined with the current IP1 at the third terminal of the transistor QD1P (i.e., the current at the third terminal of QD1P is the current IBAC), and <NUM>) the current IN0 is combined with the current IN1 at the third terminal of the transistor QD1N (i.e., the current at the third terminal of QD1N is also IBAC). Furthermore, <NUM>) the first terminal of the transistor QD2N may be coupled to the third terminal of the transistor QD1P and the current source QBP1 may be coupled to the third terminal of the transistor QD1P, and <NUM>) the first terminal of the transistor QD2P may be coupled to the third terminal of the transistor QD1N and the current source QBN1 may be coupled to the third terminal of the transistor QD1N.

<FIG> illustrates a single-ended current mirror arrangement. In some embodiments, current mirror arrangements with adjustable buffers between the transistors Q1 and Q2 of the current mirror may be implemented as differential-signal circuits. Some such embodiments are shown in <FIG> and <FIG>. The differential-signal embodiments may be particularly advantageous in that they may be particularly suitable for performing buffer offset adjustment by exploiting the differential nature of the signals.

<FIG> provides an electric circuit diagram of a differential current mirror arrangement <NUM> in which the adjustable offset buffer <NUM> as shown in <FIG> may be implemented, according to some embodiments of the disclosure. Since the current mirror arrangement <NUM> is differential, it includes two portions configured to receive complementary input signals, shown in <FIG> as a first portion <NUM> and a second portion <NUM>, illustrated in <FIG> to be, respectively, to the left and to the right of a vertical dashed-dotted line <NUM>. In some embodiments, the first portion <NUM> may receive the input signal <NUM> in the form of a first input current IINP that is based on a sum of a bias current IBCMA for the current mirror arrangement <NUM> and a signal current IIN (e.g., IINP= IBCMA+IIN), while the second portion <NUM> may receive the input signal <NUM> in the form of a second input current IINM that is based on a difference between the bias current IBCMA and the signal current IIN (e.g., IINM= IBCMA-IIN). Thus, the first portion <NUM> may be referred to as a "positive signal path side" and the second portion <NUM> may be referred to as a "negative signal path side. " In such embodiments, the output current <NUM> of the first portion <NUM> may be IOP=K*IINP, while the output current <NUM> of the second portion <NUM> may be IOM=K*IINM. Thus, for each portion <NUM>, <NUM> of the differential current mirror arrangement <NUM>, a ratio of the output signal <NUM> to the input signal <NUM> may be substantially equal to K, where K is a current gain as described above.

Each of the first and second portions <NUM>, <NUM> may include substantially the current mirror arrangement <NUM> as described with reference to <FIG>, except for a few differences which will now be described.

First of all, the portion <NUM> is shown in <FIG> to be a mirror reflection of the portion <NUM>. This may be done for the ease of illustration and, in general, the layout of the electric circuit diagram shown in <FIG>, as well as in other drawings of the present disclosure, may not have any relation to the layout of the actual components of an IC circuit in a product.

Second, in order to not clutter the drawing of <FIG>, the first terminal (base), the second terminal (collector), and third terminal (emitter) of various transistors are not specifically labeled with reference numerals (but which terminal is which is clear from the electrical circuit diagram notation used in <FIG>, as well as in other drawings of the present disclosure, to show the transistors).

Third, each of the first and second portions <NUM>, <NUM> includes a master side <NUM> and a slave side <NUM>, similar to the master side <NUM> and the slave side <NUM>, respectively, and further includes the adjustable offset buffer <NUM> having the input <NUM> coupled to the master side <NUM> and having the output <NUM> coupled to the slave side <NUM> (similar to the coupling shown in <FIG>). Thus, the first portion <NUM> includes a first instance of the adjustable offset buffer <NUM> as shown in <FIG>, the buffer <NUM> of the first portion <NUM> having the input <NUM> coupled to the master side <NUM> of the first portion <NUM> and having the output <NUM> coupled to the slave side <NUM> of the first portion <NUM>. Similarly, the second portion <NUM> includes a second instance of the adjustable offset buffer <NUM> as shown in <FIG>, the buffer <NUM> of the second portion <NUM> having the input <NUM> coupled to the master side <NUM> of the second portion <NUM> and having the output <NUM> coupled to the slave side <NUM> of the second portion <NUM>.

For each of the portions <NUM>, <NUM>, the master side <NUM> is similar to the master side <NUM>, described above, with a few differences. One difference is that the input transistor Q1 of the current mirror circuit of the current mirror arrangement <NUM> is labeled as an input transistor Q1P for the first portion <NUM> and as an input transistor Q1M for the second portion <NUM>. Another difference is that the master side <NUM> of the first portion <NUM> may further include a transistor QLVSP and the master side <NUM> of the second portion <NUM> may further include a transistor QLVSM. For each of the transistors QLVSP and QLVSM, their first terminal may be coupled to their second terminal, as shown in <FIG>. Such transistors QLVSP and QLVSM may be included in some embodiments to provide headroom to the transistors QBN0P and QBN1P by shifting the input voltage level one VBE level higher, where, in this context, the voltage VBE is the base-emitter voltage of the transistors QLVSP and QLVSM. Because of the differential nature of the input signal, the collector/second terminals of the transistors QLVSP and QLVSM is AC ground. Yet another difference is that the master side <NUM> in each of the portions <NUM>, <NUM> further includes a resistor RCM (where "RCM" stands for "Resistor Common-Mode"), having a first terminal coupled to the first terminal of the input transistor Q1 of the portion and the input <NUM> of the buffer <NUM> of that portion, and having a second terminal coupled to a first (e.g., positive) input <NUM> of an amplifier <NUM>, shared between the first and second portions <NUM>, <NUM>. Thus, for the first portion <NUM>, the first terminal of the input transistor Q1P and the input <NUM> of the buffer <NUM> of the portion <NUM> are coupled to the first input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> and <FIG> as a node NCMI), via the resistor RCM. Similarly, for the second portion <NUM>, the first terminal of the input transistor Q1M and the input <NUM> of the buffer <NUM> of the portion <NUM> are also coupled to the first input <NUM> of the amplifier <NUM> (also the node NCMI), via the resistor RCM. The second terminal of the resistor RCM of the master side <NUM> of the first portion <NUM> is coupled to the second terminal of the resistor RCM of the master side <NUM> of the second portion <NUM>, and both of them coupled to the first input <NUM> of the amplifier <NUM>, as shown in <FIG>.

For each of the portions <NUM>, <NUM>, the slave side <NUM> is similar to the slave side <NUM>, described above, also with a few differences. One difference is that the output transistor Q2 of the current mirror circuit of the current mirror arrangement <NUM> is labeled as an output transistor Q2P for the first portion <NUM> and as an output transistor Q2M for the second portion <NUM>. Another difference is that the slave side <NUM> in each of the portions <NUM>, <NUM> further includes a resistor RCM, having a first terminal coupled to the first terminal of the output transistor Q2 of the portion and the output <NUM> of the buffer <NUM> of that portion, and having a second terminal coupled to a second (e.g., negative) input <NUM> of the amplifier <NUM>. Thus, for the first portion <NUM>, the first terminal of the output transistor Q2P and the output <NUM> of the buffer <NUM> of the portion <NUM> are coupled to the second input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> and <FIG> as a node NCMO), via the resistor RCM. Similarly, for the second portion <NUM>, the first terminal of the output transistor Q2M and the output <NUM> of the buffer <NUM> of the portion <NUM> are also coupled to the second input <NUM> of the amplifier <NUM> (also the node NCMO), via the resistor RCM. The second terminal of the resistor RCM of the slave side <NUM> of the first portion <NUM> is coupled to the second terminal of the resistor RCM of the slave side <NUM> of the second portion <NUM>, and both of them coupled to the second input <NUM> of the amplifier <NUM>, as shown in <FIG>.

The resistors RCM are common-mode resistors, included to generate the common-mode voltages at the input and the output of the buffers <NUM>. In particular, the common-mode voltage VNCMI at the input of the buffers <NUM> may be generated through the resistors RCM at the node NCMI (where "NCMI" stands for "Node Common-Mode Input"), while the common-mode voltage VNCMO at the output of the buffers <NUM> may be generated through the resistors RCM at the node NCMO (where "NCMO" stands for "Node Common-Mode Output"). The NCMI and NCMO voltages are AC ground due to the differential nature of the current mirror arrangement <NUM>. The common-mode voltages VNCMI and VNCMO are provided to the amplifier <NUM>, namely, the common-mode voltage VNCMI may be provided to the first input <NUM> of the amplifier <NUM> while the common-mode voltage VNCMO may be provided to the second input <NUM> of the amplifier <NUM>. Thus, the amplifier <NUM> may detect the buffer offset as the difference between the common-mode voltages VNCMI and VNCMO.

<FIG> provides an electric circuit diagram of an amplifier arrangement <NUM> for providing control signals for the current mirror arrangements of <FIG> and/or <NUM>, according to some embodiments of the disclosure. The amplifier arrangement <NUM> may be used as the amplifier <NUM> in the current mirror arrangement of <FIG> to generate the voltages VN0, VN1, VP0, and VP1 so that the currents IN0, IN1, IP0, and IP1 are defined so as to reduce or eliminate the buffer offset of the buffer <NUM>. To that end, the amplifier arrangement <NUM> may include an amplifier <NUM>(which may be implemented using any known amplifier design), as well as a plurality of transistors and current sources, coupled to one another as shown in <FIG>, so that, when the amplifier <NUM> receives the common-mode voltages from the nodes NCMI and NCMO as the inputs <NUM>, <NUM> (e.g., receives the voltage VNCMI from the node NCMI at the positive input <NUM> and receives the voltage VNCMO from the node NCMO at the negative input <NUM>), the voltage VN0 is generated at the node labeled in <FIG> as VN0, the voltage VN1 is generated at the node labeled in <FIG> as VN1, the voltage VP0 is generated at the node labeled in <FIG> as VP0, and the voltage VP1 is generated at the node labeled in <FIG> as VP1.

Other differential-signal embodiments of adjustable offset buffers may be implemented using an input side offset adjustment, some examples of which are shown <FIG> and <FIG>.

<FIG> provides an electric circuit diagram of an NPN implementation of a differential current mirror arrangement <NUM> with an adjustable offset buffer with an input side offset adjustment, according to some embodiments of the disclosure.

Since the current mirror arrangement <NUM> is differential, it includes two portions configured to receive complementary input signals, shown in <FIG> as a first portion <NUM> and a second portion <NUM>, illustrated in <FIG> to be, respectively, to the left and to the right of a vertical dashed-dotted line <NUM>. Descriptions provided with respect to the portions <NUM> and <NUM> and the input and output currents of these portions provided with respect to <FIG> are applicable to the portions <NUM> and <NUM> and, therefore, in the interests of brevity, are not repeated.

Similar to the illustration of <FIG>, the portion <NUM> is shown in <FIG> to be a mirror reflection of the portion <NUM>. This may be done for the ease of illustration and, in general, the layout of the electric circuit diagram shown in <FIG>, as well as in other drawings of the present disclosure, may not have any relation to the layout of the actual components of an IC circuit in a product. Also similar to the illustration of <FIG>, in order to not clutter the drawing of <FIG>, the first terminal (base), the second terminal (collector), and third terminal (emitter) of various transistors are not specifically labeled with reference numerals (but which terminal is which is clear from the electrical circuit diagram notation used in <FIG> to show the transistors). Further similar to the illustration of <FIG>, the differential current mirror arrangement <NUM> includes an amplifier <NUM> (similar to the amplifier <NUM>, shown in <FIG>), shared between the first and second portions <NUM>, <NUM>.

As shown in <FIG>, each of the first and second portions <NUM>, <NUM> includes a master side <NUM> and a slave side <NUM>, and further includes a buffer coupled between the master side <NUM> and the slave side <NUM>. In each of the portions <NUM>, <NUM>, the buffer may be the buffer <NUM> as described with reference to <FIG>, having the input <NUM> coupled to the master side <NUM> and having the output <NUM> coupled to the slave side <NUM>. Thus, the first portion <NUM> includes a first instance of the buffer <NUM>, the buffer <NUM> of the first portion <NUM> having the input <NUM> coupled to the master side <NUM> of the first portion <NUM> and having the output <NUM> coupled to the slave side <NUM> of the first portion <NUM>. Similarly, the second portion <NUM> includes a second instance of the buffer <NUM>, the buffer <NUM> of the second portion <NUM> having the input <NUM> coupled to the master side <NUM> of the second portion <NUM> and having the output <NUM> coupled to the slave side <NUM> of the second portion <NUM>.

For each of the portions <NUM>, <NUM>, the master side <NUM> is similar to the master side <NUM>, described above, except that the master side <NUM> in each of the portions <NUM>, <NUM> further includes a resistor RCM and a voltage-controlled voltage source <NUM>. In each of the portions <NUM>, <NUM>, the voltage-controlled voltage source <NUM> may be seen as having a first terminal coupled to the first and second terminals of the transistor Q1 and having a second terminal coupled to the input <NUM> of the buffer <NUM>. The voltage-controlled voltage source <NUM> may be configured to receive a control signal from the amplifier <NUM>. The resistor RCM of the master side <NUM> in each of the portions <NUM>, <NUM> is similar to the resistor RCM of the master side <NUM> in each of the portions <NUM>, <NUM> of <FIG> in that, in <FIG>, that resistor also has a first terminal coupled to the first terminal of the input transistor Q1 of the portion and has a second terminal coupled to a first (e.g., positive) input <NUM> of the amplifier <NUM> via the node NCMI. Because the first terminal of the input transistor Q1 is coupled to the first terminal of the voltage-controlled voltage source <NUM>, the first terminal of the resistor RCM of the master side <NUM> in each of the portions <NUM>, <NUM> is also coupled to the first terminal of the voltage-controlled voltage source <NUM>. Thus, for the first portion <NUM>, the first terminal of the input transistor Q1 is coupled to the input <NUM> of the buffer <NUM> of the portion <NUM> via the voltage-controlled voltage source <NUM> in the portion <NUM>, and the first terminal of the input transistor Q1 is coupled to the first input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> as the node NCMI), via the resistor RCM of the master side <NUM> of the portion <NUM>. Similarly, for the second portion <NUM>, the first terminal of the input transistor Q1 is coupled to the input <NUM> of the buffer <NUM> of the portion <NUM> via the voltage-controlled voltage source <NUM> in the portion <NUM>, and the first terminal of the input transistor Q1 is coupled to the first input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> as the node NCMI), via the resistor RCM of the master side <NUM> of the portion <NUM>.

For each of the portions <NUM>,<NUM>, the slave side <NUM> is similar to the slave side <NUM>, described above, except that the slave side <NUM> in each of the portions <NUM>, <NUM> further includes a resistor RCM. The resistor RCM of the slave side <NUM> in each of the portions <NUM>, <NUM> is similar to the resistor RCM of the slave side <NUM> in each of the portions <NUM>, <NUM> of <FIG> in that, in <FIG>, that resistor also has a first terminal coupled to the first terminal of the output transistor Q2 of the portion and has a second terminal coupled to a second (e.g., negative) input <NUM> of the amplifier <NUM> via the node NCMO. Thus, for the first portion <NUM>, the first terminal of the output transistor Q2 is coupled to the second input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> as the node NCMO), via the resistor RCM of the slave side <NUM> of the portion <NUM>. Similarly, for the second portion <NUM>, the first terminal of the output transistor Q2 is coupled to the second input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> as the node NCMO), via the resistor RCM of the slave side <NUM> of the portion <NUM>.

Similar to the current mirror arrangement <NUM>, the resistors RCM of current mirror arrangement <NUM> are common-mode resistors, included to generate the common-mode voltages at the input and the output of the buffers <NUM>. In particular, the common-mode voltage VNCMI at the input of the buffers <NUM> may be generated through the resistors RCM at the node NCMI, while the common-mode voltage VNCMO at the output of the buffers <NUM> may be generated through the resistors RCM at the node NCMO. The NCMI and NCMO voltages are AC ground due to the differential nature of the current mirror arrangement <NUM>. The common-mode voltages VNCMI and VNCMO are provided to the amplifier <NUM>, namely, the common-mode voltage VNCMI may be provided to the first input <NUM> of the amplifier <NUM> while the common-mode voltage VNCMO may be provided to the second input <NUM> of the amplifier <NUM>. Thus, the amplifier <NUM> may detect the buffer offset as the difference between the common-mode voltages VNCMI and VNCMO. The amplifier <NUM> may then provide the detected buffer offset to the voltage-controlled voltage sources <NUM> in the first and second portions <NUM>, <NUM>. In particular, as shown in <FIG>, the amplifier <NUM> may provide the detected buffer offset to the voltage-controlled voltage source <NUM> in the first portion <NUM> via a control path <NUM>, and to the voltage-controlled voltage source <NUM> in the second portion <NUM> via a control path <NUM>. In response to receiving the buffer offset from the amplifier <NUM>, the voltage-controlled voltage source <NUM> may apply a compensation to the voltage at the first terminal of the input transistor Q1 (coupled to the first terminal of the voltage-controlled voltage source <NUM>) to generate the compensated voltage at the second terminal of the voltage-controlled voltage source <NUM>, coupled to the input <NUM> of the buffer <NUM>. In this manner, the voltage-controlled voltage source <NUM> can perform the buffer offset adjustment at the input side of the buffer <NUM> (i.e., at the input <NUM> of the buffer <NUM>).

To summarize, the above description makes clear that the "adjustable offset buffer with an input side offset adjustment" of <FIG> is realized by, or may be seen as, the buffer <NUM> which is made into an "adjustable offset buffer" by a combination of the resistors RCM at the nodes NCMI and NCMO and the voltage-controlled voltage source <NUM> in each of the first and second portions <NUM>, <NUM>, and the amplifier <NUM> configured to provide the voltage offset to be compensatedfor, at the input side of the buffer <NUM>, by the voltage-controlled voltage source <NUM>. In other words, the current mirror arrangement <NUM> may be seen as a differential circuit having the first portion <NUM> and the second portion <NUM>, where each portion includes a current mirror circuit, a buffer amplifier circuit, and a buffer offset reduction circuit. The current mirror circuit is a circuit formed by the input transistor Q1 and Q2. The buffer amplifier circuit is formed by the buffer <NUM>, the buffer amplifier circuit having the input <NUM> coupled to the first terminal of the transistor Q1 and the output <NUM> coupled to the first terminal of the transistor Q2. The buffer offset reduction is a circuit formed by the voltage-controlled voltage source <NUM>, the resistors RCM at the nodes NCMI and NCMO, and the amplifier <NUM>. Such a buffer offset reduction circuit is configured to adjust the voltage at the input <NUM> of the buffer amplifier circuit so that the voltage difference between the output <NUM> and the input <NUM> of the buffer amplifier circuit (i.e., the buffer offset) is zero, or, more generally, so that the voltage difference between the output <NUM> and the input <NUM> of the buffer amplifier circuit is below a target value. In some embodiments, the voltage at the input <NUM> of the buffer amplifier circuit may be adjusted based on the difference between the common-mode voltage at the inputs <NUM> of the buffer amplifier circuits of the first and second portions <NUM>, <NUM> (i.e., the voltage VNCMI) and the common-mode voltage at the outputs <NUM> of the buffer amplifier circuits of the first and second portions <NUM>, <NUM> (i.e., the voltage VNCMO).

While the descriptions of the adjustable offset buffer with the input side offset adjustment, provided above, refer to the NPN implementation of the transistors Q1 and Q2 (i.e., with the transistors Q1 and Q2 being implemented as NPN transistors), in other embodiments, the transistors Q1 and Q2 of the current mirror arrangement <NUM> may be implemented as PNP transistors. <FIG> provides an electric circuit diagram of a PNP implementation of a differential current mirror arrangement <NUM> with an adjustable offset buffer with an input side offset adjustment, according to some embodiments of the disclosure. The current mirror arrangement <NUM> is substantially analogous to the current mirror arrangement <NUM> except that each NPN transistor of the current mirror arrangement <NUM> (i.e., two transistors Q1 and Q2 in each of the first portion <NUM> and the second portion <NUM>) is replaced with a PNP transistor in the current mirror arrangement <NUM>. In such a configuration, the descriptions provided with reference to <FIG> are applicable to the current mirror arrangement <NUM> except that NPN and PNP transistors are swapped, and supply and current directions are reversed. The designations such as "first/base terminals," "semnd/collector terminals," and "third/emitter terminals" remain the same. In the interests of brevity, a detailed description of <FIG> is not provided because it's substantially analogous to that of <FIG> except for the changes identified above.

Still further differential-signal embodiments of adjustable offset buffers may be implemented using an output side offset adjustment, some examples of which are shown <FIG> and <FIG>.

<FIG> provides an electric circuit diagram of an NPN implementation of a differential current mirror arrangement <NUM> with an adjustable offset buffer with an output side offset adjustment, according to some embodiments of the disclosure. The current mirror arrangement <NUM> is substantially analogous to the current mirror arrangement <NUM> except that instead of implementing the
voltage-controlled voltage source <NUM> at the input side of the buffer <NUM>, the current mirror arrangement includes a voltage-controlled voltage source <NUM> at the output side of the buffer <NUM>, in each of the first and second portions <NUM>, <NUM>.

For each of the portions <NUM>, <NUM>, the master side <NUM> is similar to the master side <NUM>, described above, except that the master side <NUM> in each of the portions <NUM>, <NUM> further includes a resistor RCM. The resistor RCM of the master side <NUM> in each of the portions <NUM>, <NUM> is similar to the resistor RCM of the master side <NUM> in each of the portions <NUM>, <NUM> of <FIG> in that, in <FIG>, that resistor also has a first terminal coupled to the first terminal of the input transistor Q1 of the portion and has a second terminal coupled to a first (e.g., positive) input <NUM> of the amplifier <NUM> via the node NCMI. Thus, for the first portion <NUM>, the first terminal of the input transistor Q1 is coupled to the first input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> as the node NCMI), via the resistor RCM of the master side <NUM> of the portion <NUM>. Similarly, for the second portion <NUM>, the first terminal of the input transistor Q1 is coupled to the first input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> as the node NCMI), via the resistor RCM of the master side <NUM> of the portion <NUM>.

For each of the portions <NUM>,<NUM>, the slave side <NUM> is similar to the slave side <NUM>, described above, except that the slave side <NUM> in each of the portions <NUM>, <NUM> further includes a resistor RCM and a voltage-controlled voltage source <NUM>. The resistor RCM of the slave side <NUM> in each of the portions <NUM>, <NUM> is similar to the resistor RCM of the slave side <NUM> in each of the portions <NUM>, <NUM> of <FIG> in that, in <FIG>, that resistor also has a first terminal coupled to the first terminal of the output transistor Q2 of the portion and has a second terminal coupled to a second (e.g., negative) input <NUM> of the amplifier <NUM> via the node NCMO. In each of the portions <NUM>, <NUM>, the voltage-controlled voltage source <NUM> may be seen as having a first terminal coupled to the first terminal of the output transistor Q2 and having a first terminal coupled to the output <NUM> of the buffer <NUM>. The voltage-controlled voltage source <NUM> may be configured to receive a control signal from the amplifier <NUM>. Because the first terminal of the output transistor Q2 is coupled to the first terminal of the voltage-controlled voltage source <NUM>, the first terminal of the resistor RCM of the slave side <NUM> in each of the portions <NUM>, <NUM> is also coupled to the first terminal of the voltage-controlled voltage source <NUM>. Thus, for the first portion <NUM>, the first terminal of the output transistor Q2 is coupled to the output <NUM> of the buffer <NUM> of the portion <NUM> via the voltage-controlled voltage source <NUM> in the portion <NUM>, and the first terminal of the output transistor Q2 is coupled to the second input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> as the node NCMO), via the resistor RCM of the slave side <NUM> of the portion <NUM>. Similarly, for the second portion <NUM>, the first terminal of the output transistor Q2 is coupled to the output <NUM> of the buffer <NUM> of the portion <NUM> via the voltage-controlled voltage source <NUM> in the portion <NUM>, and the first terminal of the output transistor Q2 is coupled to the second input <NUM> of the amplifier <NUM> (said coupling labeled in <FIG> as the node NCM)), via the resistor RCM of the slave side <NUM> of the portion <NUM>.

Similar to the current mirror arrangements <NUM> and <NUM>, the resistors RCM of current mirror arrangement <NUM> are common-mode resistors, included to generate the common-mode voltages at the input and the output of the buffers <NUM>. In particular, the common-mode voltage VNCMI at the input of the buffers <NUM> may be generated through the resistors RCM at the node NCMI, while the common-mode voltage VNCMO at the output of the buffers <NUM> may be generated through the resistors RCM at the node NCMO. The NCMI and NCMO voltages are AC ground due to the differential nature of the current mirror arrangement <NUM>. The common-mode voltages VNCMI and VNCMO are provided to the amplifier <NUM>, namely, the common-mode voltage VNCMI may be provided to the first input <NUM> of the amplifier <NUM> while the common-mode voltage VNCMO may be provided to the second input <NUM> of the amplifier <NUM>. Thus, the amplifier <NUM> may detect the buffer offset as the difference between the common-mode voltages VNCMI and VNCMO. The amplifier <NUM> may then provide the detected buffer offset to the voltage-controlled voltage sources <NUM> in the first and second portions <NUM>, <NUM>. In particular, as shown in <FIG>, the amplifier <NUM> may provide the detected buffer offset to the voltage-controlled voltage source <NUM> in the first portion <NUM> via a control path <NUM>, and to the voltage-controlled voltage source <NUM> in the second portion <NUM> via a control path <NUM>. In response to receiving the buffer offset from the amplifier <NUM>, the voltage-controlled voltage source <NUM> may apply a compensation to the voltage at the output <NUM> of the buffer <NUM>, coupled to the first terminal of the voltage-controlled voltage source <NUM>, to generate a compensated voltage at the second terminal of the voltage-controlled voltage source <NUM>, coupled to the first terminal of the output transistor Q2. In this manner, the voltage-controlled voltage source <NUM> can perform the buffer offset adjustment at the output side of the buffer <NUM> (i.e., at the output <NUM> of the buffer <NUM>).

To summarize, the above description makes clear that the "adjustable offset buffer with an output side offset adjustment" of <FIG> is realized by, or may be seen as, the buffer <NUM> which is made into an "adjustable offset buffer" by a combination of the resistors RCM at the nodes NCMI and NCMO and the voltage-controlled voltage source <NUM> in each of the first and second portions <NUM>, <NUM>, and the amplifier <NUM> configured to provide the voltage offset to be compensated for, at the output side of the buffer <NUM>, by the voltage-controlled voltage source <NUM>. In other words, the current mirror arrangement <NUM> may be seen as a differential circuit having the first portion <NUM> and the second portion <NUM>, where each portion includes a current mirror circuit, a buffer amplifier circuit, and a buffer offset reduction circuit. The current mirror circuit is a circuit formed by the input transistor Q1 and Q2. The buffer amplifier circuit is formed by the buffer <NUM>, the buffer amplifier circuit having the input <NUM> coupled to the first terminal of the transistor Q1 and the output <NUM> coupled to the first terminal of the transistor Q2. The buffer offset reduction is a circuit formed by the voltage-controlled voltage source <NUM>, the resistors RCM at the nodes NCMI and NCMO, and the amplifier <NUM>. Such a buffer offset reduction circuit is configured to adjust the voltage at the output <NUM> of the buffer amplifier circuit so that the voltage difference between the output <NUM> and the input <NUM> of the buffer amplifier circuit (i.e., the buffer offset) is zero, or, more generally, so that the voltage difference between the output <NUM> and the input <NUM> of the buffer amplifier circuit is below a target value. In some embodiments, the voltage at the output <NUM> of the buffer amplifier circuit may be adjusted based on the difference between the common-mode voltage at the input <NUM> of the buffer amplifier circuits of the first and second portions <NUM>, <NUM> (i.e., the voltage VNCMI) and the common-mode voltage at the outputs <NUM> of the buffer amplifier circuits of the first and second portions <NUM>, <NUM> (i.e., the voltage VNCMO).

While the descriptions of the adjustable offset buffer with the output side offset adjustment, provided above, refer to the NPN implementation of the transistors Q1 and Q2 (i.e., with the transistors Q1 and Q2 being implemented as NPN transistors), in other embodiments, the transistors Q1 and Q2 of the current mirror arrangement <NUM> may be implemented as PNP transistors. <FIG> provides an electric circuit diagram of a PNP implementation of a differential current mirror arrangement <NUM> with an adjustable offset buffer with an output side offset adjustment, according to some embodiments of the disclosure. The current mirror arrangement <NUM> is substantially analogous to the current mirror arrangement <NUM> except that each NPN transistor of the current mirror arrangement <NUM> (i.e., two transistors Q1 and Q2 in each of the first portion <NUM> and the second portion <NUM>) is replaced with a PNP transistor in the current mirror arrangement <NUM>. In such a configuration, the descriptions provided with reference to <FIG> are applicable to the current mirror arrangement <NUM> except that NPN and PNP transistors are swapped, and supply and current directions are reversed. The designations such as "first/base terminals," "second/collector terminals," and "third/emitter terminals" remain the same. In the interests of brevity, a detailed description of <FIG> is not provided because it's substantially analogous to that of <FIG> except for the changes identified above.

While the descriptions provided above refer to the bipolar implementation of the transistors, in other embodiments, any of the current mirror arrangements with adjustable offset buffers as described herein may include FETs. In particular, in further embodiments of any of the current mirror arrangements with adjustable offset buffers as described herein, each NPN transistor may be replaced with an NMOS transistor and each PNP transistor may be replaced with a PMOS transistor. In such embodiments, the descriptions provided above with reference to the drawings with bipolar transistors are applicable except that the "first terminals" or "base terminals" of the bipolar transistors become "gate terminals" for the FETs, the "second terminals" or "collector terminals" of the bipolar transistors become "drain terminals" for the FETs, and the "third terminals" or "emitter terminals" of the bipolar transistors become "source terminals" for the FETs.

In one example embodiment, any number of electrical circuits of the present drawings may be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-transitory memory elements, etc. can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, etc. Other components such as external storage, additional sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself.

In another example embodiment, the electrical circuits of the present drawings may be implemented as stand-alone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices. Note that particular embodiments of the present disclosure related to current mirror arrangements with adjustable offset buffers may be readily included in a system on chip (SOC) package, either in part, or in whole. An SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio frequency functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), with a plurality of separate ICs located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the functionalities of current mirror arrangements with adjustable offset buffers, proposed herein, may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor chips.

Various embodiments of current mirror arrangements with adjustable offset buffers as described above may be implemented in any kind of system where current mirroring may be used. Such current mirror arrangements may be particularly useful in systems where current mirrors having both high linearity and wide signal bandwidth are needed. One example of such a system is shown in <FIG>, providing a schematic illustration of a system <NUM> implementing a current mirror arrangement <NUM>, according to some embodiments of the disclosure. As shown in <FIG>, the system <NUM> may include an ADC driver <NUM> and an ADC <NUM>. The ADC driver <NUM> may be used to provide drive signals to drive the ADC <NUM> so that the ADC <NUM> can translate analog electrical signals to digital form, e.g., for data processing purposes. In particular, the ADC driver <NUM> may include the current mirror arrangement <NUM> which can be implemented according to any embodiments of current mirror arrangements with adjustable offset buffers, described above. For example, the current mirror arrangement <NUM> may be implemented as the current mirror arrangement <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>, or as any further embodiments of these current mirror arrangements, as described above. The ADC driver <NUM> may then generate drive signals based on the output signal(s) generated by the current mirror arrangement <NUM>. In various embodiments, the drive signals generated by the ADC driver <NUM> may be used to drive a single or dual differential input of the ADC <NUM>.

In various embodiments, the drive signal generated by the ADC driver <NUM> may realize/implement functions such as buffering, amplitude scaling, single-ended-to-differential and differential-to-single-ended conversion, common-mode offset adjustment, and filtering. In other words, the ADC driver <NUM> may act as a signal conditioning element in a data conversion stage and may be a key factor in enabling the ADC <NUM> to achieve its desired performance. The ADC <NUM> may be any type of ADC, such as, but not limited to, a successive approximation register (SAR) converter, a pipeline converter, a flash converter, or a sigma-delta converter.

The system <NUM> shown in <FIG> provides just one non-limiting example where current mirror arrangements as described herein may be used and various teachings related to current mirror arrangements with adjustable offset buffers as described herein are applicable to a large variety of other systems. In some scenarios, various embodiments of current mirror arrangements with adjustable offset buffers as described herein can be used in automotive systems, safety-critical industrial applications, medical systems, scientific instrumentation, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which can be highly precise), and various digital-processing-based systems. In other scenarios, various embodiments of current mirror arrangements with adjustable offset buffers as described herein can be used in the industrial markets that include process control systems that help drive productivity, energy efficiency, and reliability. In yet further scenarios, various embodiments of current mirror arrangements with adjustable offset buffers may be used in consumer applications.

Claim 1:
A current mirror arrangement (<NUM>), comprising:
a current mirror circuit comprising an input transistor (Q1) and an output transistor (Q2);
a diamond buffer (<NUM>) having an input (<NUM>) coupled to a first terminal of the input transistor (Q1), and having an output (<NUM>) coupled to a first terminal of the output transistor (Q2), wherein the diamond buffer comprises a buffer amplifier circuit comprising a first transistor (QD1P), a second transistor (QD1N), a third transistor (QD2P) and a fourth transistor (QD2N) arranged in a diamond buffer configuration; and
a buffer offset reduction circuit comprising a plurality of current sources and configured to adjust bias currents provided by the plurality of current sources to the transistors of the buffer amplifier circuit so that a voltage difference between the output and the input of the diamond buffer (<NUM>) is below a target value, the plurality of current sources including a first current source (QBPO), a second current source (QBNO), a third current source (QBN1), and a fourth current source (QBP1),
wherein:
the input transistor (Q1), the output transistor (Q2) and each of the first to fourth transistors (QD1P, QD1N, QD2P, QD2N) has a first terminal, a second terminal, and a third terminal,
the input of the buffer amplifier circuit is coupled to the first terminal of the input transistor (Q1),
the output of the buffer amplifier circuit is coupled to the first terminal of the output transistor (Q2),
the first current source (QBP0) is coupled to the third terminal of the first transistor (QD1P),
the second current source (QBN0) is coupled to the third terminal of the second transistor (QD1N),
the third current source (QBN1) is coupled to the first terminal of the third transistor (QD2P),
the fourth current source (QBP1) is coupled to the first terminal of the fourth transistor (QD2N), and
wherein:
a first current (IP0), output by the first current source (QBP0), is substantially equal to a third current (IN1), output by the third current source (QBN1),
a fourth current (IP1), output by the fourth current source (QBP1), is substantially equal to a second current (IN0), output by the second current source (QBN0), and
a sum of the second current (IN0) and the third current (IN1) is substantially equal to a sum of the first current (IP0) and the fourth current (IP1).