Patent Description:
Various manufacturing methods are employed for creating wafer interconnections. Typical wafer bonding processes involve connecting wafers using direct bond hybridization (DBH or Direct Bond Interconnection). This involves first forming posts on two wafers by electroplating on a metal seed layer through a plating mold of patterned photoresist (PR). A layer of SiO2 is then deposited over the metal structure. The surfaces are then planarized (i.e. made planar), for example, by using a chemical-mechanical polishing (CMP) process. The planar surfaces of the wafers are then aligned and bonded together and annealed.

Certain metals with low melting points, such as Indium, have desirable attributes when used as interconnections, particularly in processes requiring a compliant interconnection metal and as a non-magnetic metal. However, typical DBH interconnection manufacturing processes tend to exceed a temperature of <NUM> degrees Celsius. Processes at such high temperatures tend to cause low melting point metals, such as Indium which has a melting point of roughly <NUM> degrees Celsius, to melt and/or deform prior to interconnection. Additionally, applying CMP on a surface which includes certain low melting point interconnections can contaminate the oxide bonding surface, rendering the surface incapable of the bond strength needed for DBH.

Additionally, typical plating techniques have uniformity challenges when filling in fine pitch arrays during the process of developing interconnections. Non-uniformity in the fine pitch arrays can lead to poor interconnectivity.

<CIT> discloses a circuit structure including a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between <NUM> and <NUM> microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than <NUM>. The distance between the center of the first bump and the center of the second bump is between <NUM> and <NUM> microns.

<CIT> discloses a method of manufacturing LSI chips, comprising the steps of: pasting on a substrate an adhesive sheet which retains its adhesive strength prior to a processing, then loses it after the processing; bonding non-defective LSI chips on the adhesive sheet, with their device surfaces facing downward; uniformly coating an insulating film on the non-defective LSI chips; uniformly grinding the insulating film to a level of the bottom surfaces of these LSI chips; applying a predetermined process to the adhesive sheet to weaken its adhesive strength thereof so as to peel off a pseudo wafer on which the non-defective LSI chips are bonded; and dicing the LSI chips into a discrete non-defective electronic component by cutting the pseudo wafer.

<CIT> discloses systems and methods of in-situ calibration of semiconductor material layer deposition and Removal processes are disclosed. Sets of test structures including one or more calibration vias or posts are used to precisely monitor processes such as plating and polishing, respectively. Known (e.g., empirically determined) relationships between the test structure features and product feature enable monitoring of wafer processing progress. Optical inspection of the calibration feature(s) during processing cycles permits dynamic operating condition adjustments and precise cessation of processing when desired product feature characteristics have been achieved.

<CIT> discloses a semiconductor device including a first semiconductor electronic component which includes a pad electrode, a solder bump, and a metal layer between a pad and solder that is configured to have an underlying metal layer formed between the pad electrode and the solder bump and connected to the pad electrode, and a main metal layer formed on the underlying metal layer, and in which the main metal layer has an eave portion at an outer edge portion thereof.

<CIT> discloses a method of preparing detectors for oxide bonding to an integrated hip,. g, a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon.

<CIT> discloses a device having a sensor die with a sensor and a control circuit die with at least one control circuit disposed therein, the control circuit die on the sensor die.

In light of the needs described above, in at least one aspect, there is a need for a process which allows for an effective method of manufacturing interconnections for DBH of wafers which can be practiced with low melting point materials while still delivering high yield fine pitch arrays for interconnections.

In at least one aspect, the subject technology relates to a method of manufacturing an array of planar wafer level metal posts comprising: providing, a metal seed layer for plating posts or interconnections on a substrate of a first wafer; applying a photoresist, PR, pattern mold over the metal seed layer; plating an array of posts within a photoresist 'PR' pattern mold on the metal seed layer; stripping the PR pattern mold from the substrate and array of posts; after the step of stripping the PR pattern mold, applying a PR layer around each of the posts; after the step of applying a PR layer, etching the metal seed layer on the substrate to isolate the posts from one another; after the step of etching the metal seed layer, stripping the PR layer; applying an oxide layer, at a temperature of below <NUM> degrees Celsius and below a melting point of the array of posts, over a surface of the first wafer and around the array of posts extending from the surface; applying chemical-mechanical polishing 'CMP' to planarize the oxide layer and the array of posts; after the step of applying CMP, protecting exposed surfaces of the array of posts with a second PR layer; and after the step of protecting exposed surfaces of the array of posts, cleaning a surface of the oxide layer.

In some embodiments, during the step of applying an oxide layer, the oxide layer is applied at a temperature of between <NUM> degrees Celsius and <NUM> degrees Celsius. In some cases, the oxide layer is applied at a temperature of between <NUM> degrees Celsius and <NUM> degrees Celsius. In some cases, the posts are comprised of Indium.

In at least one embodiment, the subject technology relates to a method of manufacturing a bonded wafer assembly with Indium interconnections comprising: a) providing a first wafer with a substrate layer, an insulating layer, and a metal seed layer, the metal seed layer connected to the substrate layer by vias extending through a first plurality of holes in the insulating layer; b) applying a photoresist 'PR' pattern mold over the metal seed layer such that a second plurality of holes through the PR pattern mold align with the vias; c) plating Indium within the second plurality of holes in the PR pattern mold to form an array of Indium posts on the first wafer; d) stripping the PR pattern mold; e) etching a portion of the metal seed layer to singulate the array of Indium posts; f) applying an oxide layer, at a temperature below <NUM> degrees Celsius, over a surface of the first wafer; g) applying chemical-mechanical polishing 'CMP' to form a planar surface, the planar surface including the array of Indium posts and the oxide layer; h) performing steps a)-g) to create a second wafer; i) aligning the Indium posts of the first and second wafers; and j) bonding the first wafer and the second wafer together to form the bonded wafer assembly.

In some embodiments, the bonding is done through a low temperature annealing process. In some embodiments, employing Indium posts, a PR layer is placed around each of the Indium posts. After etching the metal seed layer and before applying the oxide layer the PR layer is stripped. In some embodiments, after applying CMP, a second PR layer is placed over exposed surfaces of the array of Indium posts. After the step of placing a second PR layer an exposed surface of the oxide layer is cleaned. Cleaning an exposed surface of the oxide layer can be done by applying HCl. In some embodiments, the oxide layer is applied at a temperature of between <NUM> degrees Celsius and <NUM> degrees Celsius. In some embodiments, the oxide layer is applied at a temperature of between <NUM> degrees Celsius and <NUM> degrees Celsius.

So that those having ordinary skill in the art to which the disclosed system pertains will more readily understand how to make and use the same, reference may be had to the following drawings.

The subject technology overcomes many of the prior art problems associated with the fabrication of semiconductor devices. In brief summary, the subject technology provides a method of manufacturing a wafer or wafer assembly, particularly one that can include Indium based interconnections. The advantages, and other features of the systems and methods disclosed herein, will become more readily apparent to those having ordinary skill in the art from the following detailed description of certain preferred embodiments taken in conjunction with the drawings which set forth representative embodiments of the present invention. Like reference numerals are used herein to denote like parts. Further, words denoting orientation such as "upper", "lower", "distal", and "proximate" are merely used to help describe the location of components with respect to one another in the figures. For example, an "upper" surface of a part is merely meant to describe a surface that is separate from the "lower" surface of that same part, as shown in the figures. No words denoting orientation are used to describe an absolute orientation (i.e. where an "upper" part must always be on top).

Referring now to <FIG> a flowchart illustrating a method <NUM> for manufacturing wafer level interconnections in accordance with the subject technology is shown. The method <NUM> generally involves creating interconnections on a wafer device such as a III-V semiconductor device and optionally bonding with a separate wafer to form a wafer assembly. In the example shown, the method <NUM> starts at first step <NUM> which includes providing a first wafer <NUM> with a device layer <NUM>, an insulating layer <NUM>, and a metal seed layer <NUM>, as seen in <FIG>. Preliminary steps of manufacturing the first wafer <NUM> are understood in the art and therefore a thorough description thereof is omitted. The device layer <NUM> is typically a Silicon substrate and includes processing circuitry extending therethrough comprised of Al, Cu, implantation or the like. The insulating layer <NUM> is positioned over the upper surface <NUM> of the device layer <NUM> and can be comprised of materials such as SiO<NUM>, SiNx, or the like. The metal seed layer <NUM> is provided for plating posts or interconnections, as is discussed more fully below, and is comprised of materials such as TiW, Al, Sn, or the like. The insulating layer <NUM> is broken by a first plurality of holes or perforations <NUM> through which the metal seed layer <NUM> extends, forming vias <NUM>. The vias <NUM> are used to provide a connection between the device layer <NUM> and the posts or interconnections discussed below. Notably, both the insulating layer <NUM> and the metal seed layer <NUM> may additionally or alternatively be comprised of other materials known in the art to function in accordance with the insulating layer <NUM> and metal seed layer <NUM> described herein.

At step <NUM>, and referring now additionally to <FIG>, in order to create the interconnections, or posts <NUM>, a photoresist (PR) pattern mold <NUM> is applied over the metal seed layer <NUM>. The PR pattern mold <NUM> is patterned with a second plurality of holes or perforations <NUM> which correspond to the perforations <NUM> in the insulating layer <NUM>. At step <NUM>, the Indium is plated within the PR pattern mold <NUM> to form an array of posts <NUM>. The PR pattern mold <NUM> allows for improved Indium plating uniformity and reduces Indium contamination from bonding oxide, as the Indium is not dragged across oxide. The posts <NUM> are formed as a small dense array that grows from the metal seed layer <NUM> when current is provided and will eventually serve as high yield fine pitch array for interconnections for the first wafer <NUM>. The posts <NUM> are grown within the perforations <NUM> which align with the vias <NUM>, such that the vias <NUM> connect the posts <NUM> to the device layer <NUM>. Thus, the posts <NUM> eventually form the interconnections on the first wafer <NUM>. While Indium has been found to be effectively used to form the posts <NUM> within the disclosed method <NUM>, it should be noted that the methods discussed herein are applicable to other elements and/or materials which can be used in the formation of wafer interconnections. In particular, the method <NUM> and other methods discussed herein have been found to be effective when the posts <NUM> which form the interconnections are comprised materials/elements with a low melting point, such as below <NUM> degrees Celsius. This is because the method <NUM> is designed to avoid melting material with a low melting point, whereas other process of forming interconnections and bonding wafers will often melt and/or deform such material.

At step <NUM>, the PR pattern mold <NUM> is stripped as seen in <FIG>. Then, turning to <FIG>, a second PR layer <NUM> is placed surrounding the posts <NUM> at step <NUM>. At step <NUM>, the metal seed layer <NUM> is then etched to singulate the posts <NUM> such that the posts <NUM> are isolated from one another (i.e. not directly connected through the metal seed layer <NUM>). Etching can be accomplished, for example, by photolithographic techniques as are known in the art. The second PR layer <NUM> protects the posts <NUM> during the metal etching process and can be stripped, at step <NUM>, after the etching process is complete.

At step <NUM> a low temperature oxide is applied over a surface <NUM> of the first wafer <NUM> (and around the posts <NUM> extending from the surface <NUM>) as seen in <FIG>, to form an oxide layer <NUM>. In one example, where the posts <NUM> are comprised of Indium, the low temperature oxide is below the melting temperature of Indium, which is about <NUM> degrees Celsius. Therefore, the temperature of the low temperature oxide is applied at a temperature of below <NUM> degrees Celsius. In some embodiments, the low temperature oxide is applied at a temperature of substantially <NUM> degrees Celsius below the melting point of Indium, such as between <NUM> degrees Celsius and <NUM> degrees Celsius. In other embodiments, the temperature of the low temperature oxide is between <NUM> degrees Celsius and <NUM> degrees Celsius. If a material other than Indium is used for the posts <NUM>, corresponding oxide temperature ranges can be applied (e.g. substantially <NUM> degrees below a melting point of the other material). Alternatively, if the posts <NUM> are formed of a material with a higher melting point than Indium, the oxide can be applied within one of the temperature ranges described above. By applying the oxide at a temperature that is below (or well below) the melting point of the posts <NUM>, there is less of a risk that the posts <NUM> will be deformed during formation of the oxide layer <NUM>. In this way, the integrity of the wafer <NUM> is maintained.

After the oxide layer <NUM> is formed, a new surface <NUM> of the first wafer <NUM> is formed which is typically non-uniform. Therefore at step <NUM>, and as seen in <FIG>, chemical-mechanical polishing (CMP) is then applied to the non-uniform surface <NUM>. Applying CMP to the non-uniform surface <NUM> of the first wafer <NUM> removes excess post <NUM> and oxide layer <NUM> material to smooth and/or level the surface <NUM>. CMP is applied until the oxide layer <NUM> and posts <NUM> have been planarized, forming a flat and continuous upper surface <NUM> of the wafer <NUM>. A planarized surface <NUM> helps bond the first wafer <NUM> to a second wafer, as discussed below.

Next, at step <NUM>, the surface <NUM> of the oxide layer <NUM> is cleaned without also cleaning the surface of the posts <NUM>. <FIG> shows an intermediate step of placing a second PR layer <NUM> over the posts <NUM> to serve as a protective cap for the posts <NUM> during cleaning. Cleaning typically involves applying a substance, such as an acid, to the surface <NUM> of the oxide layer <NUM>. For example, HCl can be applied over to the surface <NUM> of the oxide layer <NUM>. Cleaning the surface <NUM> removes contamination created by the formation of the posts <NUM> (e.g. Indium contamination on the oxide layer <NUM>) and helps prepare the first wafer <NUM> for effective bonding with another wafer. After cleaning is complete, the second PR layer <NUM> is stripped from the posts <NUM> at <FIG> using any means known in the art. The first wafer <NUM> is now ready for bonding to another wafer.

Referring now to <FIG>, the first wafer <NUM> can be bonded to a second wafer <NUM> which is similar, or identical, to the first wafer <NUM> to form a wafer assembly <NUM>. For example, at step <NUM>, the steps described above (i.e. <NUM>-<NUM>) can be performed a second time to form the second wafer <NUM> and prepare it for bonding. To that end, the second wafer <NUM> can likewise include posts <NUM> comprised of Indium (or other low temperature material for forming interconnections) at a similar position within the second wafer <NUM> as the posts <NUM> within the first wafer <NUM>. Forming posts <NUM> at a similar position within the second wafer <NUM> allows for good alignment of the posts <NUM>, <NUM> of the first and second wafers <NUM>, <NUM>. For example, <FIG> shows the first wafer <NUM> and the second wafer <NUM> with similarly positioned posts <NUM>, <NUM>. At step <NUM>, the posts <NUM> of the first wafer <NUM> are then aligned with posts <NUM> of the second wafer <NUM> using a separate device (not shown in the figures). The wafers <NUM>, <NUM> are then bonded at step <NUM> to form the wafer assembly <NUM>. The bonding can be accomplished, for example, by a low temperature annealing process. Once bonded, the posts <NUM>, <NUM> provide interconnections between the wafers <NUM>, <NUM>.

Notably, and as mentioned above, not all steps of the method of manufacturing shown in <FIG> are absolutely necessary. While various steps shown in <FIG> may provide different benefits, the method shown in <FIG> can be simplified, if desired, by manufacturing a wafer with only some of the steps shown in <FIG>. To that end, a simplified method <NUM> of manufacturing a wafer according to an explanatory example, which does not fall under the scope of the present invention, is shown in <FIG>.

Referring now to <FIG>, the method <NUM> starts with plating an array of posts, such as posts <NUM>, on a substrate of first wafer <NUM>, such as is shown in <FIG>. As described with respect to method <NUM>, the posts <NUM> can be grown off the metal seed layer <NUM> of a substrate comprised of a metal seed layer <NUM>, an insulating layer <NUM>, and a device layer <NUM>. Further, the posts <NUM> can be grown within a PR pattern mold <NUM>. Alternatively, the post metal can be deposited using physical vapor deposition, Chemical vapor deposition, or the like.

At step <NUM>, after the posts <NUM> have formed, the PR pattern mold <NUM> can be stripped from the first wafer <NUM> as seen in <FIG>. A low temperature oxide is then applied over the surface of the first wafer <NUM>, a step <NUM>, to form an oxide layer <NUM> as seen in <FIG>. As discussed above, the low temperature oxide can be applied at a temperature of substantially <NUM> degrees Celsius below the melting point of the posts <NUM>. For example, if the posts <NUM> are Indium (which has a melting point of roughly <NUM> degrees Celsius), the low temperature can be applied between <NUM> degrees Celsius and <NUM> degrees Celsius, between <NUM> degrees Celsius and <NUM> degrees Celsius, or simply below <NUM> degrees Celsius. The low temperature oxide can be applied at a similar range below the melting temperature of other materials used to form the posts <NUM>, or alternatively, the aforementioned temperature ranges can be applied regardless of the material used. Finally, at step <NUM>, CMP is applied to the surface of the first wafer <NUM> to planarize a surface <NUM> formed by the posts <NUM> and oxide layer <NUM>, as seen in <FIG>. The first wafer <NUM> can then be optionally cleaned, as discussed with respect to step <NUM>, and then bonded to a second wafer <NUM> to form a wafer assembly <NUM>, as discussed in steps <NUM>-<NUM> and as shown in <FIG>. Notably, in different embodiments, any of the steps or combinations of steps disclosed in <FIG> with respect to method <NUM> and/or shown in the figures herein, can be combined with the steps disclosed in <FIG> with respect to method <NUM> to provide additional benefits if desired.

Claim 1:
A method of manufacturing an array of planar wafer level metal posts comprising:
providing, a metal seed layer (<NUM>) for plating posts or interconnections on a substrate of a first wafer (<NUM>);
applying a photoresist, PR, pattern mold (<NUM>) over the metal seed layer (<NUM>);
plating (<NUM>, <NUM>) an array of posts (<NUM>) within the PR pattern mold (<NUM>) on the metal seed layer (<NUM>);
stripping (<NUM>, <NUM>) the PR pattern mold from the substrate and array of posts;
after the step of stripping the PR pattern mold, applying (<NUM>) a PR layer (<NUM>) around each of the posts;
after the step of applying the PR layer, etching (<NUM>) the metal seed layer (<NUM>) on the substrate to isolate the posts from one another;
after the step of etching the metal seed layer (<NUM>), stripping (<NUM>) the PR layer;
applying (<NUM>, <NUM>) an oxide layer (<NUM>), at a temperature of below <NUM> degrees Celsius and below a melting point of the array of posts, over a surface of the first wafer and around the array of posts extending from the surface;
applying chemical-mechanical polishing 'CMP' to planarize (<NUM>, <NUM>) the oxide layer and the array of posts;
after the step of applying CMP, protecting exposed surfaces of the array of posts with a second PR layer (<NUM>); and
after the step of protecting exposed surfaces of the array of posts, cleaning (<NUM>) a surface of the oxide layer.