Patent Description:
Aspects of the present disclosure relate to performing machine learning tasks, and in particular, to computation-in-memory (CIM) architectures.

Machine learning is generally the process of producing a trained model (e.g., an artificial neural network, a tree, or other structures), which represents a generalized fit to a set of training data that is known a priori. Applying the trained model to new data produces inferences, which may be used to gain insights into the new data. In some cases, applying the model to the new data is described as "running an inference" on the new data.

As the use of machine learning has proliferated for enabling various machine learning (or artificial intelligence) tasks, the need for more efficient processing of machine learning model data has arisen. In some cases, dedicated hardware, such as machine learning accelerators, may be used to enhance a processing system's capacity to process machine learning model data. However, such hardware demands space and power, which is not always available on the processing device. For example, "edge processing" devices, such as mobile devices, always-on devices, Internet of Things (IoT) devices, and the like, typically have to balance processing capabilities with power and packaging constraints. Further, accelerators may move data across common data busses, which can cause significant power usage and introduce latency into other processes sharing the data bus. Consequently, other aspects of a processing system are being considered for processing machine learning model data.

Memory devices are one example of another aspect of a processing system that may be leveraged for performing processing of machine learning model data through so-called computation-in-memory (CIM) processes. Conventional CIM processes perform computation using analog signals, which may result in inaccuracy of computation results, adversely impacting neural network computations. Accordingly, systems and methods are needed for performing computation-in-memory with increased accuracy.

Attention is drawn to document <CIT> which relates to systems and methods for a memory device such as, for example, a Processing-In-Memory Device that is configured to perform multiplication operations in memory using a popcount operation. A multiplication operation may include a summation of multipliers being multiplied with corresponding multiplicands. The inputs may be arranged in particular configurations within a memory array. Sense amplifiers may be used to perform the popcount by counting active bits along bit lines. One or more registers may accumulate results for performing the multiplication operations.

The present invention is defined by the appended independent claims <NUM> and <NUM>. Further embodiments of the present invention are defined by the appended dependent claims. Certain aspects provide apparatus and techniques for performing machine learning tasks, and in particular, to computation-in-memory architectures.

One aspect provides a circuit for in-memory computation. The circuit generally includes: a memory having multiple columns; a plurality of memory cells on each column of the memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory; a plurality of digital counters, each digital counter of the plurality of digital counters being coupled to a respective column of the multiple columns of the memory; an adder circuit coupled to outputs of the plurality of digital counters; and an accumulator coupled to an output of the adder circuit.

One aspect provides a method for in-memory computation. The method generally includes: accumulating, via each digital counter of a plurality of digital counters, output signals on a respective column of multiple columns of a memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells storing multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory; adding, via an adder circuit, output signals of the plurality of digital counters; and accumulating, via an accumulator, output signals of the adder circuit.

One aspect provides an apparatus for in-memory computation. The apparatus generally includes: means for counting a quantity of logic highs of output signals on a respective column of multiple columns of a memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory; means for adding output signals of the plurality of digital counters; and means for accumulating output signals of the means for adding.

Other aspects provide processing systems configured to perform the aforementioned methods, as well as those described herein; non-transitory, computer-readable media comprising instructions that, when executed by one or more processors of a processing system, cause the processing system to perform the aforementioned methods, as well as those described herein; a computer program product embodied on a computer-readable storage medium comprising code for performing the aforementioned methods, as well as those further described herein; and a processing system comprising means for performing the aforementioned methods, as well as those further described herein.

The following description and the related drawings set forth in detail certain illustrative features of one or more aspects.

It is contemplated that elements and features of one aspect may be beneficially incorporated in other aspects without further recitation.

Aspects of the present disclosure provide apparatuses, methods, processing systems, and computer-readable mediums for performing computation in memory (CIM) to handle data-intensive processing, such as implementing machine learning models. Some aspects provide techniques for performing digital CIM (DCIM) using digital counters, each digital counter accumulating output signals on a respective one of multiple columns of memory. As used herein, an "accumulator" generally refers to circuitry used to accumulate output signals across multiple cycles. An "adder circuit" or "an adder tree" generally refers to digital adders used to add output signals of multiple memory cells (e.g., memory cells across word-lines or columns).

The aspects described herein provide a high-speed and energy-efficient accumulator for digital CIM applications. Word-lines of CIM circuitry may be sequentially activated, and a digital counter may be used to perform accumulation and provide an accumulation result after two or more of the word-lines are sequentially activated. For example, the digital counter may be used to count a quantity of logic highs generated on a column of the memory after multiple computation cycles.

The DCIM circuitry provided herein has an energy consumption per bit that does not scale with the number of activation rows of the memory array, reducing the total energy consumption of the DCIM circuitry as compared to conventional implementations. The aspects described herein also allow for a lowering of the area consumption for the overall CIM system as compared to conventional implementations by reusing an adder tree and accumulator for multiple weight column groups. Moreover, the DCIM circuitry provided herein has a self-timed operation that enables high-speed operation as the digital counters are timed using the signals on respective columns as opposed to using a clock signal. Partial sums from the digital counters may be accumulated on a global accumulator, which is operated at a slower clock, resulting in higher energy efficiency of the CIM system. In some aspects, electromagnetic interference (EMI) is reduced by a self-timed operation and phase-shifting of a local clock within the DCIM circuitry, as described in more detail herein.

CIM-based machine learning (ML)/artificial intelligence (AI) may be used for a wide variety of tasks, including image and audio processing and making wireless communication decisions (e.g., to optimize, or at least increase, throughput and signal quality). Further, CIM may be based on various types of memory architectures, such as dynamic random-access memory (DRAM), static random-access memory (SRAM) (e.g., based on an SRAM cell as in <FIG>), magnetoresistive random-access memory (MRAM), and resistive random-access memory (ReRAM or RRAM), and may be attached to various types of processing units, including central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), AI accelerators, and others. Generally, CIM may beneficially reduce the "memory wall" problem, which is where the movement of data in and out of memory consumes more power than the computation of the data. Thus, by performing the computation in memory, significant power savings may be realized. This is particularly useful for various types of electronic devices, such as lower power edge processing devices, mobile devices, and the like.

For example, a mobile device may include a memory device configured for storing data and performing computation-in-memory operations (also referred to as "compute-in-memory" operations). The mobile device may be configured to perform an ML/AI operation based on data generated by the mobile device, such as image data generated by a camera sensor of the mobile device. A memory controller unit (MCU) of the mobile device may thus load weights from another on-board memory (e.g., flash or RAM) into a CIM array of the memory device and allocate input feature buffers and output (e.g., output activation) buffers. The processing device may then commence processing of the image data by loading, for example, a layer in the input buffer and processing the layer with weights loaded into the CIM array. This processing may be repeated for each channel of the image data, and the outputs (e.g., output activations) may be stored in the output buffers and then used by the mobile device for an ML/AI task, such as facial recognition.

Neural networks are organized into layers of interconnected nodes. Generally, a node (or neuron) is where computation happens. For example, a node may combine input data with a set of weights (or coefficients) that either amplifies or dampens the input data. The amplification or dampening of the input signals may thus be considered an assignment of relative significances to various inputs with regard to a task the network is trying to learn. Generally, input-weight products are summed (or accumulated), and then the sum is passed through a node's activation function to determine whether and to what extent that signal should progress further through the network.

In a most basic implementation, a neural network may have an input layer, a hidden layer, and an output layer. "Deep" neural networks generally have more than one hidden layer.

Deep learning is a method of training deep neural networks. Generally, deep learning maps inputs to the network to outputs from the network and is thus sometimes referred to as a "universal approximator" because deep learning can learn to approximate an unknown function f(x) = y between any input x and any output y. In other words, deep learning finds the right f to transform x into y.

More particularly, deep learning trains each layer of nodes based on a distinct set of features, which is the output from the previous layer. Thus, with each successive layer of a deep neural network, features become more complex. Deep learning is thus powerful because it can progressively extract higher level features from input data and perform complex tasks, such as object recognition, by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building up a useful feature representation of the input data.

For example, if presented with visual data, a first layer of a deep neural network may learn to recognize relatively simple features, such as edges, in the input data. In another example, if presented with auditory data, the first layer of a deep neural network may learn to recognize spectral power in specific frequencies in the input data. The second layer of the deep neural network may then learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data, based on the output of the first layer. Higher layers may then learn to recognize complex shapes in visual data or words in auditory data. Still higher layers may learn to recognize common visual objects or spoken phrases. Thus, deep learning architectures may perform especially well when applied to problems that have a natural hierarchical structure.

Neural networks, such as deep neural networks (DNNs), may be designed with a variety of connectivity patterns between layers.

<FIG> illustrates an example of a fully connected neural network <NUM>. In a fully connected neural network <NUM>, each node in a first layer communicates its output to every node in a second layer, so that each node in the second layer will receive input from every node in the first layer.

<FIG> illustrates an example of a locally connected neural network <NUM>. In a locally connected neural network <NUM>, a node in a first layer may be connected to a limited number of nodes in the second layer. More generally, a locally connected layer of the locally connected neural network <NUM> may be configured so that each node in a layer will have the same or a similar connectivity pattern, but with connection strengths (or weights) that may have different values (e.g., values associated with local areas <NUM>, <NUM>, <NUM>, and <NUM> of the first layer nodes). The locally connected connectivity pattern may give rise to spatially distinct receptive fields in a higher layer, because the higher layer nodes in a given region may receive inputs that are tuned through training to the properties of a restricted portion of the total input to the network.

One type of locally connected neural network is a convolutional neural network (CNN). <FIG> illustrates an example of a convolutional neural network <NUM>. The convolutional neural network <NUM> may be configured such that the connection strengths associated with the inputs for each node in the second layer are shared (e.g., for local area <NUM> overlapping another local area of the first layer nodes). Convolutional neural networks are well suited to problems in which the spatial locations of inputs are meaningful.

One type of convolutional neural network is a deep convolutional network (DCN). Deep convolutional networks are networks of multiple convolutional layers, which may further be configured with, for example, pooling and normalization layers.

<FIG> illustrates an example of a DCN <NUM> designed to recognize visual features in an image <NUM> generated by an image-capturing device <NUM>. For example, if the image-capturing device <NUM> is a camera mounted in or on (or otherwise moving along with) a vehicle, then the DCN <NUM> may be trained with various supervised learning techniques to identify a traffic sign and even a number on the traffic sign. The DCN <NUM> may likewise be trained for other tasks, such as identifying lane markings or identifying traffic lights. These are just some example tasks, and many others are possible.

In the example of <FIG>, the DCN <NUM> includes a feature-extraction section and a classification section. Upon receiving the image <NUM>, a convolutional layer <NUM> applies convolutional kernels (for example, as depicted and described in <FIG>) to the image <NUM> to generate a first set of feature maps <NUM> (or intermediate activations). Generally, a "kernel" or "filter" comprises a multidimensional array of weights designed to emphasize different aspects of an input data channel. In various examples, "kernel" and "filter" may be used interchangeably to refer to sets of weights applied in a convolutional neural network.

The first set of feature maps <NUM> may then be subsampled by a pooling layer (e.g., a max pooling layer, not shown) to generate a second set of feature maps <NUM>. The pooling layer may reduce the size of the first set of feature maps <NUM> while maintaining much of the information in order to improve model performance. For example, the second set of feature maps <NUM> may be downsampled to a 14x14 matrix from a 28x28 matrix by the pooling layer.

This process may be repeated through many layers. In other words, the second set of feature maps <NUM> may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

In the example of <FIG>, the second set of feature maps <NUM> is provided to a fully connected layer <NUM>, which in turn generates an output feature vector <NUM>. Each feature of the output feature vector <NUM> may include a number that corresponds to a possible feature of the image <NUM>, such as "sign," "<NUM>," and "<NUM>. " In some cases, a softmax function (not shown) may convert the numbers in the output feature vector <NUM> to a probability. In such cases, an output <NUM> of the DCN <NUM> is a probability of the image <NUM> including one or more features.

A softmax function (not shown) may convert the individual elements of the output feature vector <NUM> into a probability in order that an output <NUM> of DCN <NUM> is one or more probabilities of the image <NUM> including one or more features, such as a sign with the number "<NUM>" thereon, as in image <NUM>. Thus, in the present example, the probabilities in the output <NUM> for "sign" and "<NUM>" should be higher than the probabilities of the other elements of the output <NUM>, such as "<NUM>," "<NUM>," "<NUM>," "<NUM>," "<NUM>," "<NUM>," and "<NUM>.

Before training the DCN <NUM>, the output <NUM> produced by the DCN <NUM> may be incorrect. Thus, an error may be calculated between the output <NUM> and a target output known a priori. For example, here the target output is an indication that the image <NUM> includes a "sign" and the number "<NUM>. " Utilizing the known target output, the weights of the DCN <NUM> may then be adjusted through training so that a subsequent output <NUM> of the DCN <NUM> achieves the target output (with high probabilities).

To adjust the weights of the DCN <NUM>, a learning algorithm may compute a gradient vector for the weights. The gradient vector may indicate an amount that an error would increase or decrease if a weight were adjusted in a particular way. The weights may then be adjusted to reduce the error. This manner of adjusting the weights may be referred to as "backpropagation" because this adjustment process involves a "backward pass" through the layers of the DCN <NUM>.

In practice, the error gradient of weights may be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient. This approximation method may be referred to as "stochastic gradient descent. " Stochastic gradient descent may be repeated until the achievable error rate of the entire system has stopped decreasing or until the error rate has reached a target level.

After training, the DCN <NUM> may be presented with new images, and the DCN <NUM> may generate inferences, such as classifications, or probabilities of various features being in the new image.

Convolution is generally used to extract useful features from an input data set. For example, in convolutional neural networks, such as described above, convolution enables the extraction of different features using kernels and/or filters whose weights are automatically learned during training. The extracted features are then combined to make inferences.

An activation function may be applied before and/or after each layer of a convolutional neural network. Activation functions are generally mathematical functions that determine the output of a node of a neural network. Thus, the activation function determines whether a node should pass information or not, based on whether the node's input is relevant to the model's prediction. In one example, where y = conv(x) (i.e., y is the convolution of x), both x and y may be generally considered as "activations. " However, in terms of a particular convolution operation, x may also be referred to as "pre-activations" or "input activations" as x exists before the particular convolution, and y may be referred to as "output activations" or a "feature map.

<FIG> depicts an example of a traditional convolution in which a <NUM>-pixel x <NUM>-pixel x <NUM>-channel input image is convolved using a <NUM> x <NUM> x <NUM> convolution kernel <NUM> and a stride (or step size) of <NUM>. The resulting feature map <NUM> is <NUM> pixels x <NUM> pixels x <NUM> channel. As seen in this example, the traditional convolution may change the dimensionality of the input data as compared to the output data (here, from <NUM> x <NUM> to <NUM> x <NUM> pixels), including the channel dimensionality (here, from <NUM> channels to <NUM> channel).

One way to reduce the computational burden (e.g., measured in floating-point operations per second (FLOPs)) and the number of parameters associated with a neural network comprising convolutional layers is to factorize the convolutional layers. For example, a spatial separable convolution, such as depicted in <FIG>, may be factorized into two components: (<NUM>) a depthwise convolution, where each spatial channel is convolved independently by a depthwise convolution (e.g., a spatial fusion); and (<NUM>) a pointwise convolution, where all the spatial channels are linearly combined (e.g., a channel fusion). An example of a depthwise separable convolution is depicted in <FIG>. Generally, during spatial fusion, a network learns features from the spatial planes, and during channel fusion, the network learns relations between these features across channels.

In one example, a depthwise separable convolution may be implemented using 5x5 kernels for spatial fusion, and 1x1 kernels for channel fusion. In particular, the channel fusion may use a 1x1xd kernel that iterates through every single point in an input image of depth d, where the depth d of the kernel generally matches the number of channels of the input image. Channel fusion via pointwise convolution is useful for dimensionality reduction for efficient computations. Applying 1x1xd kernels and adding an activation layer after the kernel may give a network added depth, which may increase the network's performance.

In particular, in <FIG>, the <NUM>-pixel x <NUM>-pixel x <NUM>-channel input image <NUM> is convolved with a filter comprising three separate kernels 304A-C, each having a <NUM> x <NUM> x <NUM> dimensionality, to generate a feature map <NUM> of <NUM> pixels x <NUM> pixels x <NUM> channels, where each channel is generated by an individual kernel among kernels 304A-C.

Then, feature map <NUM> is further convolved using a pointwise convolution operation with a kernel <NUM> having dimensionality <NUM> x <NUM> x <NUM> to generate a feature map <NUM> of <NUM> pixels x <NUM> pixels x <NUM> channel. As is depicted in this example, feature map <NUM> has reduced dimensionality (<NUM> channel versus <NUM> channels), which allows for more efficient computations therewith.

Though the result of the depthwise separable convolution in <FIG> is substantially similar to the traditional convolution in <FIG>, the number of computations is significantly reduced, and thus depthwise separable convolution offers a significant efficiency gain where a network design allows it.

Though not depicted in <FIG>, multiple (e.g., m) pointwise convolution kernels <NUM> (e.g., individual components of a filter) can be used to increase the channel dimensionality of the convolution output. So, for example, m = <NUM>1x1x3 kernels <NUM> can be generated, in which each output is an <NUM>-pixel x <NUM>-pixel x <NUM>-channel feature map (e.g., feature map <NUM>), and these feature maps can be stacked to get a resulting feature map of <NUM> pixels x <NUM> pixels x <NUM> channels. The resulting increase in channel dimensionality provides more parameters for training, which may improve a convolutional neural network's ability to identify features (e.g., in input image <NUM>).

Digital computation-in-memory (CIM) is used to solve the energy and speed bottlenecks arising from moving data between a processing unit and memory for logical operations. For example, digital CIM may be used to perform a logic operation in memory, such as bit-parallel/bit-serial logic operations (e.g., an AND operation). However, machine learning workloads still involve a final accumulation, which may be performed using circuitry external to the memory array. Since each row in the memory is read sequentially, a high-speed and energy-efficient accumulator near the memory may be implemented to achieve better performance (e.g., increase the tera-operations per second (TOPS)).

<FIG> illustrates an example memory cell <NUM> of a static random access memory (SRAM), which may be implemented in a CIM array. The memory cell <NUM> may be referred to as an "<NUM>-transistor (8T) SRAM cell" as the memory cell <NUM> is implemented with eight transistors.

As shown, the memory cell <NUM> may include a cross-coupled invertor pair <NUM> having an output <NUM> and an output <NUM>. As shown, the cross-coupled invertor pair output <NUM> is selectively coupled to a write bit-line (WBL) <NUM> via a pass-gate transistor <NUM>, and the cross-coupled invertor pair output <NUM> is selectively coupled to a complementary write bit-line (WBLB) <NUM> via a pass-gate transistor <NUM>. The WBL <NUM> and WBLB <NUM> are configured to provide complementary digital signals to be written (e.g., stored) in the cross-coupled invertor pair <NUM>. The WBL and WBLB may be used to store a bit for a neural network weight in the memory cell <NUM>. The gates of pass-gate transistors <NUM>, <NUM> may be coupled to a write word-line (WWL) <NUM>, as shown. For example, a digital signal to be written may be provided to the WBL (and a complement of the digital signal is provided to the WBLB). The pass-gate transistors <NUM>, <NUM>-which are implemented here as n-type field-effect transistors (NFETs)-are then turned on by providing a logic high signal to WWL <NUM>, resulting in the digital signal being stored in the cross-coupled invertor pair <NUM>.

As shown, the cross-coupled invertor pair output <NUM> may be coupled to a gate of a transistor <NUM>. The source of the transistor <NUM> may be coupled to a reference potential node (VSS or electrical ground), and the drain of the transistor <NUM> may be coupled to a source of a transistor <NUM>. The drain of the transistor <NUM> may be coupled to a read bit-line (RBL) <NUM>, as shown. The gate of transistor <NUM> may be controlled via a read word-line (RWL) <NUM>. The RWL <NUM> may be controlled via an activation input signal.

During a read cycle, the RBL <NUM> may be precharged to logic high. If both the activation input on the RWL <NUM> and the weight bit stored at the cross-coupled invertor pair output <NUM> are logic high, then transistors <NUM>, <NUM> are both turned on, electrically coupling the RBL <NUM> to VSS at the source of transistor <NUM> and discharging the RBL <NUM> to logic low. If either the activation input on RWL <NUM> or the weight stored at the cross-coupled invertor pair output <NUM> is logic low, then at least one of transistors <NUM>, <NUM> will be turned off, such that the RBL <NUM> remains logic high. Thus, the output of the memory cell <NUM> at RBL <NUM> is logic low only when both the weight bit and activation input are logic high, and is logic high otherwise, effectively implementing a NAND-gate operation.

<FIG> illustrates a circuit <NUM> for CIM, in accordance with certain aspects of the present disclosure. The circuit <NUM> includes a CIM array <NUM> having word-lines <NUM><NUM> to <NUM><NUM> (also referred to as "rows") and columns <NUM><NUM> to <NUM><NUM>. Word-lines <NUM><NUM> to <NUM><NUM> are collectively referred to as "word-lines (WLs) <NUM>," and columns <NUM><NUM> to <NUM><NUM> are collectively referred to as "columns <NUM>. " As shown, the CIM array <NUM> may include activation circuitry <NUM> configured to provide activation signals to word-lines <NUM>. While the CIM array <NUM> is implemented with <NUM> word-lines and <NUM> columns to facilitate understanding, the CIM array may be implemented with any number of word-lines or columns. As shown, memory cells <NUM><NUM>-<NUM> to <NUM><NUM>-<NUM> (collectively referred to as "memory cells <NUM>") are implemented at the intersections of the WLs <NUM> and columns <NUM>.

Each of the memory cells <NUM> may be implemented using the memory cell architecture described with respect to <FIG>. As shown, activation inputs a(<NUM>,<NUM>) to a(<NUM>,<NUM>) may be provided to respective word-lines <NUM>, and the memory cells <NUM> may store neural network weights w(<NUM>,<NUM>) to w(<NUM>,<NUM>). For example, memory cells <NUM><NUM>-<NUM> to <NUM><NUM>-<NUM> may store weight bits w(<NUM>,<NUM>) to w(<NUM>,<NUM>), memory cells <NUM><NUM>-<NUM> to <NUM><NUM>-<NUM> may store weight bits w(<NUM>,<NUM>) to w(<NUM>,<NUM>), and so on. Each word-line may store a multi-bit weight. For example, weight bits w(<NUM>,<NUM>) to w(<NUM>,<NUM>) may represent eight bits of a weight of a neural network.

As shown, each of the columns <NUM> is coupled to a sense amplifier (SA) <NUM><NUM> to <NUM><NUM>. The sense amplifiers <NUM><NUM>, <NUM><NUM>, to <NUM><NUM> are collectively referred to as "sense amplifiers <NUM>. " The input of each of the sense amplifiers <NUM> may be coupled to outputs of the memory cells on a respective column, as shown.

The outputs of the sense amplifiers <NUM> are coupled to a column accumulator circuit <NUM>. For example, the outputs of each of sense amplifiers <NUM> is coupled to one of accumulators <NUM><NUM>, <NUM><NUM>, to <NUM><NUM> (collectively referred to as "accumulators <NUM>") of the column accumulator circuit <NUM>. Each of the accumulators <NUM> performs accumulation of output signals of a respective one of the sense amplifiers <NUM> across multiple computation cycles. For example, during each computation cycle, computation is performed for a single word-line, and the output signal of the computation for the word line is accumulated with output signals during other computation cycles using a respective one of the accumulators <NUM>. After multiple computation cycles (e.g., <NUM> cycles for <NUM> word-lines), each of the accumulators <NUM> provides an accumulation result.

During operation of the circuit <NUM>, activation circuitry <NUM> provides a first set <NUM> of activation inputs a(<NUM>,<NUM>) to a(<NUM>,<NUM>) to the memory cells <NUM> for computation during a first activation cycle. The activation inputs a(<NUM>,<NUM>) to a(<NUM>,<NUM>) are provided one row at a time, and the outputs of each computation for each row is accumulated using a respective one of accumulators <NUM>, as described. The same operation is performed for other sets of activation inputs during subsequent activation cycles, such as activation inputs a(<NUM>,<NUM>) to a(<NUM>,<NUM>) representing the second most significant bits of the activation parameters, and so on until activation inputs representing the least-significant bits of the activation parameters are processed.

Once the multiple computation cycles have been completed during each activation cycle, the outputs of the accumulators <NUM> are provided to the weight-shift adder tree circuit <NUM> for addition across columns, and the output of the weight-shift adder tree circuit <NUM> is provided to the activation-shift accumulator circuit <NUM> for accumulation across activation cycles. In other words, the activation-shift accumulator circuit <NUM> accumulates the computation results after the activation cycles are completed.

The weight-shift adder tree circuit <NUM> includes multiple weight-shift adders (e.g., weight-shift adder <NUM>), each including a bit-shift-and-add circuit to facilitate the performance of a bit-shifting and addition operation. In other words, memory cells on column <NUM><NUM> may store the most significant bits (MSBs) for respective weights, and memory cells on column <NUM><NUM> may store the least significant bits (LSBs) for respective weights. Therefore, when performing the addition across columns <NUM>, a bit-shifting operation is performed to shift the bits to account for the significance of the bits on the associated column. In other words, once the bit-wise accumulation occurs at each of the accumulators <NUM> across multiple computation cycles, the weight-shift adder tree circuit <NUM> combines the eight columns of weighted sums (e.g., providing the accumulation result for a given activation bit position during each activation cycle), and the activation-shift accumulator circuit <NUM> combines the results from multiple (e.g., eight) activation cycles to output a final accumulation result.

The output of the weight-shift adder tree circuit <NUM> is provided to an activation-shift accumulator circuit <NUM>, as described. The activation-shift accumulator circuit <NUM> includes a bit-shift circuit <NUM> and an accumulator <NUM>. The bit-shift circuit <NUM> performs a bit-shifting operation based on the activation cycle. For example, for an <NUM>-bit activation parameter processed using eight activation cycles, the bit-shift circuit may perform an <NUM>-bit shift for the first activation cycle, a <NUM>-bit shift for the second activation cycle, and so on. After the activation cycles, the outputs of the bit-shift circuit <NUM> are accumulated using the accumulator <NUM> to generate a DCIM output signal.

In some aspects, the CIM array <NUM>, the activation circuitry <NUM> and the column accumulator circuit <NUM> operate at a higher frequency (e.g., eight times or more) than the weight-shift adder tree circuit <NUM> and activation-shift accumulator circuit <NUM>. As shown, half-latch circuits <NUM><NUM>, <NUM><NUM>, to <NUM><NUM> (collectively referred to as "half-latch circuits <NUM>") may be coupled to respective outputs of the accumulators <NUM>. Each half-latch circuit holds the output of a respective one of the accumulators <NUM>, and provides the output to a respective input of the weight-shift adder tree circuit <NUM> once the multiple computations cycles have been completed. In other words, a half-latch circuit generally refers to a latch circuit that holds a digital input (e.g., an output of one of accumulators <NUM>) at a beginning of a clock cycle and provides the digital input to an output of the latch circuit at the end of the clock cycle. The half-latch circuits <NUM> facilitate the transition from the higher frequency operation of the column accumulator circuit <NUM> to the lower frequency operation of the weight-shift adder tree circuit <NUM>. The half-latch circuits <NUM> allow synchronization between clock domains without using other components (e.g., extra buffers).

Certain aspects provide a digital counter (e.g., a ones counter configured to count a quantity of logic highs in the time domain) enabling adder-free partial sum generation, as described in more detail with respect to <FIG>. In other words, each of accumulators <NUM> may be implemented using a digital counter that counts a quantity of logic highs provided at the output of a respective one of sense amplifiers <NUM>.

<FIG> illustrates DCIM circuitry with an accumulator (e.g., one of accumulators <NUM>) implemented using a pulse generator <NUM> and digital counter <NUM>, in accordance with certain aspects of the present disclosure. As shown, a memory cell, such as memory cell <NUM><NUM>-<NUM> shown as a NAND gate in <FIG>, may provide a computation result based on an activation input and a stored weight-bit. Each of the activation input and the stored weight-bit may have a <NUM>% toggling probability. In other words, the activation input may have a <NUM>% probability of being logic high and a <NUM>% probability of being logic low. Similarly, the stored weight-bit may have a <NUM>% probability of being logic high and a <NUM>% probability of being logic low. As a result, the output of the NAND gate may have a <NUM>% toggling probability (e.g., a <NUM>% probability of being logic high and a <NUM>% probability of being logic low), due to the NAND operation.

The pulse generator <NUM> generates a pulse for each logic high output of the associated sense amplifier. For example, during a first computation cycle, if the output of memory cell <NUM><NUM>-<NUM> is logic high, the pulse generator <NUM> generates a pulse, and during a second computation cycle, if the output of the memory cell <NUM><NUM>-<NUM> is logic high, the pulse generator <NUM> generates a pulse, and so on. The output of the pulse generator <NUM> is provided to the digital counter <NUM>. The digital counter counts the number of pulses generated by the pulse generator <NUM>, and generates a digital counter output signal (e.g., a six-bit digital signal including bits q(<NUM>)-q(<NUM>)).

As shown, the digital counter <NUM> includes flip-flops <NUM><NUM> to <NUM><NUM> (collectively referred to as "flip-flops <NUM>") where the output of the pulse generator <NUM> is provided to the clock (CLK) input of flip-flop <NUM><NUM>. The complementary output (Q) of each flip-flop is fed back to the data (D) input of that flip-flop, and the output (Q) of each flip-flop is provided to the CLK of a subsequent flip-flop in the flip-flop chain.

As shown, flip-flop <NUM><NUM> has the highest energy consumption of flip-flops <NUM>, and flip-flop <NUM><NUM> has the lowest energy consumption of flip-flops <NUM>. For example, if the pulse generator <NUM> consumes <NUM> femtojoules (fJ) per step (e.g., per computation cycle), then flip-flop <NUM><NUM> consumes <NUM> fJ/step, flip-flop <NUM><NUM> consumes <NUM> fJ/step, flip-flop <NUM><NUM> consumes <NUM> fJ/step, flip-flop <NUM><NUM> consumes <NUM> fJ/step, flip-flop <NUM><NUM> consumes <NUM> fJ/step, and flip-flop <NUM><NUM> consumes <NUM> fJ/step. In other words, flip-flop <NUM><NUM> generates the least significant bit (LSB) q(<NUM>) of the digital counter output signal, and the flip-flop <NUM><NUM> generates the most significant bit (MSB) q(<NUM>) of the digital counter output signal. The energy consumption of flip-flop <NUM><NUM> is double the energy consumption of flip-flop <NUM><NUM> because the output of the flip-flop <NUM><NUM> has half the toggling probability as the output of flip-flop <NUM><NUM>. Similarly, the energy consumption of flip-flop <NUM><NUM> is double the energy consumption of flip-flop <NUM><NUM> because the output of the flip-flop <NUM><NUM> has half the toggling probability as the output of flip-flop <NUM><NUM>, and so on.

Each stage of the digital counter <NUM> is effectively a divide-by-two frequency divider with one flip-flop stage's toggling being controlled by the output signal of a preceding flip-flop stage. Implementing additional stages for the digital counter (e.g., increasing the number of bits of the digital counter output signal) has little impact on energy consumption of the DCIM circuitry since with additional stages, energy consumption increases asymptotically. Half-latch circuitry may be coupled to the output of the digital counter for each column to synchronize the counter's output to the slow-clock domain (DCIM clock). In other words, each of bits q(<NUM>)-q(<NUM>) may be provided to a half-latch circuit (e.g., one of half-latch circuits <NUM>). In some aspects, delay circuity may be used to reduce interference between columns of the memory, as described in more detail with respect to <FIG>.

<FIG> is a block diagram illustrating CIM circuitry implemented using delay circuitry to reduce electromagnetic interference (EMI), in accordance with certain aspects of the present disclosure. For example, as shown, <NUM>-bit weights may be stored in the memory cells <NUM> and processed using the sense amplifiers <NUM>, column accumulators <NUM>, weight-shift adder tree circuit <NUM>, and activation-shift accumulator circuit <NUM>, as described herein. Delay circuits <NUM> (e.g., being associated with different delays) may be implemented between the sense amplifiers <NUM> and the column accumulators <NUM>, implementing an offset to the phase of signals provided to the column accumulators <NUM>. For example, a single delay element (labeled as "1D") may be coupled between the sense amplifier <NUM><NUM> and the column accumulator <NUM><NUM>, two delay elements (labeled as "2D") may be coupled between the sense amplifier <NUM><NUM> and the column accumulator <NUM><NUM>, and so on. In this manner, falling/rising edges of signals provided to the column accumulators <NUM> are offset, reducing EMI between columns. In other words, a skew (e.g., via one or more delay cells) is added at the input of the digital counter <NUM> to reduce EMI due to what would otherwise be simultaneous switching noise.

As shown, a clock generator circuit <NUM> may be used to generate the DCIM clock and local clock. For example, the clock generator circuit <NUM> may include a clock generator <NUM> configured to generate the DCIM clock. The clock generator <NUM> may be implemented using any suitable clock generation circuit such as a phase-locked loop (PLL) or ring oscillator. The weight-shift adder tree circuit <NUM> may receive and operate on the DCIM clock. For certain aspects, the clock generator circuit <NUM> may include a frequency converter <NUM> that may be used to generate the local clock from the DCIM clock, based on which the activation circuitry <NUM> operates. While the frequency converter <NUM> is shown as being part of the clock generator circuit <NUM>, the frequency converter <NUM> may be separate from the clock generator circuit <NUM> in some implementations. A frequency converter generally refers to any circuit that receives a clock signal with a first frequency and generates a second clock signal with a second different frequency.

The frequency converter may be implemented using any suitable technique. For example, the frequency converter may be implemented as a ring oscillator (RO) modulated by system clock timing (e.g., modulated using the DCIM clock), or by generating pulses from rising or falling edges of a system clock, as described in more detail with respect to <FIG>. In this manner, the local clock may have a rising edge that is in sync with the DCIM clock.

<FIG> is a block diagram showing an example implementation of the frequency converter <NUM>, in accordance with certain aspects of the present disclosure. <FIG> is a graph showing an input signal <NUM> and an output signal <NUM> of an edge-to-pulse converter. The frequency converter <NUM> may include one or multiple edge-to-pulse converters <NUM><NUM>, <NUM><NUM> to <NUM>n (collectively referred to as "edge-to-pulse converters <NUM>"). Each of the edge-to-pulse converters <NUM> generates a pulse at each rising edge and each falling edge of an input signal presented to the edge-to-pulse converter. For example, as shown in <FIG>, the edge-to-pulse converter <NUM><NUM> generates a pulse <NUM> after detecting the rising edge <NUM> of the input signal <NUM> and another pulse <NUM> after detecting the falling edge <NUM> of the input signal <NUM>. In this manner, the output signal <NUM> of the edge-to-pulse converter is twice the frequency of the input signal <NUM> of the edge-to-pulse converter. Using multiple edge-to-pulse converters in series allows for upconversion of the frequency of the DCIM clock to generate the local clock, as described with respect to <FIG>. While edge-to-pulse converters are provided as one example of a frequency converter, any suitable type of frequency converter may be used.

<FIG> and <FIG> illustrate an integrated circuit (IC) layout <NUM> for implementing a DCIM circuit, in accordance with certain aspects of the present disclosure. As shown in <FIG>, each SRAM column may be implemented using fins (e.g., for implementing fin field-effect transistors (FinFETs)) and may have <NUM>-<NUM> fin pitches. A fin pitch refers to a distance from one fin to an adjacent fin. The memory cells of the SRAM column are coupled to a sense amplifier, as described herein. The output of the sense amplifier is coupled to a digital counter implemented using flip-flops cascaded along each column having fins, as shown. The counter design may have <NUM>-<NUM> fin pitches.

As shown in <FIG>, each column may include an eight-transistor (8T) SRAM column (e.g., a column of memory cells, each cell implemented using <NUM> transistors), a single-ended sense amplifier (e.g., sense amplifier <NUM><NUM>), a pulse generator (e.g., pulse generator <NUM>), one's counter circuitry (e.g., a respective one of flip-flops <NUM>) for generating each of bits q(<NUM>) to q(<NUM>) as shown in <FIG>, and a latch circuit for each of bits q(<NUM>) to q(<NUM>). A binary adder tree (e.g., weight-shift adder tree circuit <NUM>) and accumulator (e.g., activation-shift accumulator circuit <NUM>) are also coupled to the output of the latch circuits, as shown. In some aspects, a multiplexer may be used to facilitate reuse of the adder tree circuit <NUM> and accumulator circuit <NUM>, as described in more detail with respect to <FIG>.

<FIG> illustrates a DCIM circuit <NUM> implemented using a multiplexer <NUM> to facilitate reuse of an adder tree and accumulator, in accordance with certain aspects of the present disclosure. As shown, the CIM array <NUM> (e.g., including 8T SRAM cells) may include multiple weight column groups, each weight column group having a set of columns associated with a weight parameter having multiple bits. For example, the weight column group <NUM> may refer to columns <NUM> storing <NUM>-bit weights on each row. As shown, each weight column group may be coupled to eight accumulators (e.g., digital counters) and <NUM> (e.g., for the <NUM> accumulators x <NUM> bits per accumulator) half-latch circuits, as described herein.

In some aspects, a partial-sum operation may be implemented using a shared accumulator (e.g., accumulator circuit <NUM>) across weight column groups, providing one accumulation result at the end of each multiply-and-accumulate (MAC) cycle. The binary adder tree (e.g., weight-shift adder tree circuit <NUM>) and the <NUM>-bit accumulator (e.g., accumulator circuit <NUM>) consume a significant portion of the total area of the DCIM circuitry. Thus, sharing the binary adder tree and the activation-shift accumulator across multiple weight column groups reduces the total area consumption of the DCIM circuitry.

As shown, during each of eight activation cycles <NUM><NUM> to <NUM><NUM> (collectively referred to as "activation cycles <NUM>"), <NUM> computation cycles occur (C00 to C031), one computation cycle for each of <NUM> rows as shown in <FIG>. After the activation cycles <NUM>, the computation outputs for the weight column groups are available at the outputs of the half-latch circuits.

The multiplexer <NUM> may be used to select each weight column group separately for processing using the adder tree circuit <NUM> and accumulator circuit <NUM>. For example, during a first weight cycle, the half-latch output (e.g., <NUM>-bit output) on a first weight column group (e.g., weight column group <NUM>) may be selected by the multiplexer <NUM> and provided to the adder tree circuit <NUM> and accumulator circuit <NUM> for processing as described with respect to <FIG>.

During a second weight cycle, the half-latch output (e.g., <NUM>-bit output) on a second weight column group may be selected by the multiplexer and provided to the adder tree circuit <NUM> and accumulator circuit <NUM> for processing, and so on. Time multiplexing of latched partial sums enables reuse of the adder tree circuit <NUM> and accumulator circuit <NUM>. A multiplexer select signal may be generated every two clock cycles (e.g., of the DCIM clock shown in <FIG>) to select a new weight column group. In other words, one <NUM>-bit accumulation result is provided by the accumulator circuit <NUM> for each column after every two clock cycles, one clock cycle for performing the addition via adder tree circuit <NUM> and another clock cycle for the accumulation via the accumulator circuit <NUM>. In some aspects, a divide-by-two version of the DCIM clock may be used to operate the multiplexer <NUM>, adder tree circuit <NUM>, and accumulator circuit <NUM>, increasing the throughput of the addition and accumulation operations for the weight column groups.

The aspects of the present disclosure provide an innovative circuit and physical design enabling high-speed and energy-efficient accumulation for any DCIM product. The aspects described do not involve routing a clock signal to generate partial sums and are fully self-timed in nature, allowing a high-speed operation. In other words, the digital counters used to implement the accumulators <NUM> are timed using the output of the associated sense amplifiers <NUM> instead of a clock signal. Due to the data-divided clock (e.g., local clock shown in <FIG>), the aspects of the present disclosure provide a low energy implementation of DCIM circuitry as the energy consumption of the digital counter increases asymptotically, and the accumulation for each weight column group is performed at a rate associated with the divided clock without using fast toggling partial sum components. The aspects provided herein also allow for sharing the accumulator (e.g., accumulator circuit <NUM>) and binary adder tree (e.g., adder tree circuit <NUM>) across the weight column groups, allowing an area reduction at the DCIM system level. The DCIM circuitry described herein also provides a less complex design (e.g., as it does not include any full-adder cells nor carry generation cells used in conventional implementations), allowing for a compact implementation. The aspects described herein also may be implemented without modifications to the SRAM array used for the CIM application. Circuits are column-matched to the SRAM array providing full array efficiency, as described with respect to <FIG> and <FIG>. The self-timed clocking and skew (e.g., phase offset) between the processing of different columns reduce EMI caused by simultaneous switching noise, as described herein.

<FIG> is a flow diagram illustrating example operations <NUM> for in-memory computation, in accordance with certain aspects of the present disclosure. The operations <NUM> may be performed by a circuit for CIM, such as the circuit <NUM> described with respect to <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>.

At block <NUM>, the circuit may receive activation inputs at a plurality of memory cells (e.g., memory cells <NUM>) on each of multiple columns of a memory. At block <NUM> the circuit accumulates, via each digital counter of a plurality of digital counters (e.g., digital counter <NUM>), output signals on a respective column of the multiple columns of a memory. The plurality of memory cells store multiple bits representing weights of a neural network, and the plurality of memory cells of each of the multiple columns correspond to different word-lines (e.g., word-lines <NUM>) of the memory. In some aspects, the circuit counts, via the digital counter, a quantity of particular logic values (e.g., logic highs) of the output signals on the respective column of multiple columns. In some aspects, the circuit generates, via a pulse generator coupled to each column of the multiple columns, one or more pulses based on the output signals of the plurality of memory cells on the column, wherein accumulating the output signals via the digital counter is based on the one or more pulses.

At block <NUM>, the circuit adds, via an adder circuit (e.g., adder tree circuit <NUM>), output signals of the plurality of digital counters. At block <NUM>, the circuit accumulates, via an accumulator (e.g., accumulator circuit <NUM>), output signals of the adder circuit. At block <NUM>, the circuit may generate a DCIM output signal based on the accumulation of the output signals of the adder circuit. In some aspects, the circuit generates, via the plurality of memory cells of each of the multiple columns, output signals during multiple computation cycles, and the digital counter is configured to count a quantity of logic highs of the digital output signals.

In some aspects, the digital counter includes a set of flip-flops (e.g., flip-flops <NUM>), where a clock input of a first flip-flop (e.g., flip-flop <NUM><NUM>) of the set of flip-flops is coupled to the column, and wherein an output of the first flip-flop is coupled to a clock input of a second flip-flop (e.g., flip-flop <NUM><NUM>) of the set of flip-flops. In some aspects, the circuit generates, via each of the set of flip-flops, a bit of the output signal generated by the digital counter. A half-latch circuit may be coupled to an output of each of the set of flip-flops.

In some aspects, the circuit applies a first delay (e.g., via one of delay circuits <NUM>) to the output signals generated by the plurality of memory cells on a first column of the multiple columns, and applies a second delay (e.g., via another one of the delay circuits <NUM>) to the output signals generated by the plurality of memory cells on a second column of the multiple columns. The first delay may be different than the second delay.

In certain aspects, the circuit accumulates, via each digital counter of another plurality of digital counters, output signals on a respective column of multiple other columns of the memory, wherein another plurality of memory cells are on each of the multiple other columns, the other plurality of memory cells storing multiple bits representing weights of the neural network, wherein the other plurality of memory cells of each of the multiple other columns correspond to different word-lines of the memory. The circuit may select, via a multiplexer (e.g., multiplexer <NUM>), the output signals from the plurality of digital counters during a first weight cycle, the output signals being added via the adder circuit based on the selection of the output signals. The circuit may also select, via the multiplexer, other output signals from the other plurality of digital counters during a second weight cycle, and add, via the adder circuit, the other output signals based on the selection of the other output signals.

<FIG> illustrates an example electronic device <NUM>. Electronic device <NUM> may be configured to perform the methods described herein, including operations <NUM> described with respect to <FIG>.

Electronic device <NUM> includes a central processing unit (CPU) <NUM>, which in some aspects may be a multi-core CPU. Instructions executed at the CPU <NUM> may be loaded, for example, from a program memory associated with the CPU <NUM> or may be loaded from a memory <NUM>.

Electronic device <NUM> also includes additional processing blocks tailored to specific functions, such as a graphics processing unit (GPU) <NUM>, a digital signal processor (DSP) <NUM>, a neural processing unit (NPU) <NUM>, a multimedia processing block <NUM>, a multimedia processing block <NUM>, and a wireless connectivity processing block <NUM>. In one implementation, NPU <NUM> is implemented in one or more of CPU <NUM>, GPU <NUM>, and/or DSP <NUM>.

In some aspects, wireless connectivity processing block <NUM> may include components, for example, for third generation (<NUM>) connectivity, fourth generation (<NUM>) connectivity (e.g., <NUM> LTE), fifth generation connectivity (e.g., <NUM> or NR), Wi-Fi connectivity, Bluetooth connectivity, and wireless data transmission standards. Wireless connectivity processing block <NUM> is further connected to one or more antennas <NUM> to facilitate wireless communication.

Electronic device <NUM> may also include one or more sensor processors <NUM> associated with any manner of sensor, one or more image signal processors (ISPs) <NUM> associated with any manner of image sensor, and/or a navigation processor <NUM>, which may include satellite-based positioning system components (e.g., global positioning system (GPS) or global navigation satellite system (GLONASS)) as well as inertial positioning system components.

Electronic device <NUM> may also include one or more input and/or output devices <NUM>, such as screens, touch-sensitive surfaces (including touch-sensitive displays), physical buttons, speakers, microphones, and the like. In some aspects, one or more of the processors of electronic device <NUM> may be based on an advanced reduced instruction set computing (RISC) machine (ARM) instruction set.

Electronic device <NUM> also includes memory <NUM>, which is representative of one or more static and/or dynamic memories, such as a dynamic random access memory, a flash-based static memory, and the like. In this example, memory <NUM> includes computer-executable components, which may be executed by one or more of the aforementioned processors of electronic device <NUM> or a CIM controller <NUM> (also referred to as "control circuitry"). For example, the electronic device <NUM> may include a CIM circuit <NUM>, such as the circuit <NUM>, as described herein. The CIM circuit <NUM> may controlled via the CIM controller <NUM>. For instance, in some aspects, memory <NUM> may include code 1224A for storing (e.g., storing weights in memory cells), code 1224B for computing (e.g., performing a neural network computation by applying activation inputs). As illustrated, the CIM controller <NUM> may include a circuit 1228A for storing (e.g., storing weights in memory cells), and a circuit 1228B for computing (e.g., performing a neural network computation by applying activation inputs). The depicted components, and others not depicted, may be configured to perform various aspects of the methods described herein.

In some aspects, such as where the electronic device <NUM> is a server device, various aspects may be omitted from the example depicted in <FIG>, such as one or more of the multimedia processing block <NUM>, wireless connectivity processing block <NUM>, antenna <NUM>, sensor processors <NUM>, ISPs <NUM>, or navigation processor <NUM>.

The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. The examples discussed herein are not limiting of the scope, applicability, or aspects set forth in the claims. For example, changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. In addition, the scope of the disclosure is intended to cover such an apparatus or method that is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein.

For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining, and the like. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, "determining" may include resolving, selecting, choosing, establishing, and the like.

For example, means for adding may include an adder tree, such as adder trees <NUM> or weight-shift adder tree <NUM>, or an accumulator such as accumulators <NUM>. Means for accumulating may include an accumulator such as the activation shift accumulator <NUM>. Means for sensing may include an SA, such as the SAs <NUM>.

Claim 1:
A circuit for in-memory computation, comprising:
a memory having multiple columns;
a plurality of memory cells (<NUM>) on each column of the memory, the plurality of memory cells (<NUM>) being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells (<NUM>) of each of the multiple columns correspond to different word-lines of the memory;
a plurality of digital counters (<NUM>), each digital counter of the plurality of digital counters being coupled to a respective column of the multiple columns of the memory;
an adder circuit (<NUM>) coupled to outputs of the plurality of digital counters (<NUM>);
an accumulator (<NUM>) coupled to an output of the adder circuit;
characterised by
delay circuits (<NUM>), each delay circuit being coupled between the plurality of memory cells (<NUM>) of the respective column of the multiple columns and a respective one of the plurality of digital counters (<NUM>), wherein the delay circuits (<NUM>) of the multiple columns have different delays.