Patent Description:
Many electrical systems, including, for example, control systems and measurement devices, rely on Fully-Depleted Silicon-On-Insulator (FD-SOI) semiconductors for some aspect of operation. FD-SOI is a category of semiconductor devices manufactured such that a thin layer of insulator, often silicon oxide, is positioned between the silicon channel and the base silicon. The thin layer of insulator is generally referred to as the buried oxide, or BOX, and enables use of a very thin layer, or film, of un-doped silicon as the channel, which results in the channel being fully depleted during normal operation.

Certain physical phenomena, such as radiation, may introduce parametric shifts in semiconductors that can ultimately produce failures or, for example, errors in data. These parametric shifts are similar to those known to occur due to temperature and age. Although previously thought to be relatively insensitive to radiation, FD-SOI semiconductors accumulating a high-enough total ionizing dose (TID) of radiation may exhibit parametric shifts. At least some FD-SOI semiconductors include one or more wells positioned below the BOX that can be charged, or biased, to partially mitigate parametric shifts. However, biasing of the wells is generally fixed by design or is itself susceptible to parametric shifts, resulting in sub-optimized compensation. In certain applications, such as satellites, aerial vehicles, and long-range guided vehicles, the accuracy of FD-SOI circuits is desirable, because even small parametric shifts (i.e., errors) translate to errors in acceleration, position, and rotation. Accordingly, it would be desirable to enhance the degree of compensation against at least TID, aging, and temperature effects in FD-SOI semiconductors.

<NPL> in accordance with its abstract states that CMOS circuit hardness to total ionizing dose is improved by a circuit technique that dynamically adjusts well and/or substrate voltages to maintain constant device threshold voltages. Threshold voltage excursions below a reference value activate an oscillator driving a charge pump. Stabilization is demonstrated experimentally. Techniques for optimizing the circuitry for various CMOS technology implementations are provided and supported with simulations.

<CIT> in accordance with its abstract states a back-bias voltage regulator circuit for regulating a back-bias voltage used to control leakage current in at least one transistor within a primary circuit. In one embodiment, the back-bias voltage regulator circuit includes a voltage divider circuit configured to receive a back-bias voltage from a charge pump, and to generate a divided voltage signal by dividing the back-bias voltage based on a ratio of resistances of resistive elements within the voltage divider. In addition, the regulator circuit includes an output circuit configured to receive the back-bias voltage from the charge pump and having an output node for outputting the back-bias voltage, as well as a reference voltage circuit configured to generate a reference voltage signal based on a threshold voltage of the at least one transistor in the primary circuit. Also in such an embodiment, the regulator circuit includes a comparison circuit configured to compare the divided voltage signal to the reference voltage signal and to operate the output circuit to regulate the back-bias voltage level based on the comparison. Also disclosed is a related method of regulating a back-bias voltage to control leakage current in at least one transistor within a primary circuit.

<CIT> in accordance with its abstract states an improved substrate bias feedback circuit, and a method for operating the same.

<CIT> in accordance with its abstract states a body-bias voltage controller that includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal.

The present disclosure provides a self-optimizing circuit for a primary fully-depleted silicon-on-insulator (FD-SOI) device having a buried oxide layer (BOX) and a primary well disposed beneath the BOX device as defined by the independent claim <NUM>. The present disclosure further provides a method of compensating a primary fully-depleted silicon-on-insulator (FD-SOI) device for total ionizing dose (TID) effects as defined by the independent claim <NUM>. Preferred embodiments are defined in the appended dependent claims.

The features, functions, and advantages that have been discussed can be achieved independently in various embodiments or may be combined in yet other embodiments, further details of which can be seen with reference to the following description and drawings.

As used herein, an element or step recited in the singular and preceded by the word "a" or "an" should be understood as not excluding plural elements or steps unless such exclusion is explicitly recited. Furthermore, references to "one embodiment" of the present invention or the "example embodiment" are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

FD-SOI semiconductors exposed to the cumulative effects of radiation over time, as quantified by TID, exhibit parametric shifts due to the influence of charge trapped within the BOX on the channel region of active devices, such as Field Effect Transistors (FETs). Embodiments of the self-optimizing circuits described herein provide biasing, or "back biasing," of the well beneath the BOX to compensate for the effects of at least, for example, radiation, but also for temperature or age. At least some embodiments of the self-optimizing circuits provide both a static biasing and a dynamic biasing of the well that acts in a proportional and opposite manner to the trapped charge in the BOX, to compensate for the parametric shift.

Generally, known solutions provide a fixed, or static, biasing of the wells to compensate for parametric shifts. Some such solutions, devised, for example, to control device leakage rather than improve circuit performance, may include techniques of multiple discrete biasing steps, such as zero bias, reverse body bias (RBB), and RBB plus supply collapse (RBB+SC). Static biasing is generally determined to optimize for average leakage performance. However, the accumulation of TID influences parametric shifts dynamically over time, making the application of such static biasing alone sub-optimal. Embodiments of the self-optimizing circuits described herein mitigate parametric shifts due to TID dynamically, or adaptively, as they manifest in the integrated circuit.

Further, in some embodiments, PMOS and NMOS devices may utilize the same wells. In other embodiments, PMOS and NMOS devices utilize independent wells. In certain embodiments, different regions of devices or devices performing different functions utilize different wells, and in other embodiments, PMOS and NMOS devices utilize different wells and further utilize different wells for different regions of devices or devices performing different functions. Each of these different wells for different devices, different regions of devices, or devices performing different functions may be biased and optimized independently using one or more of the self-optimizing circuits described herein.

At least some known solutions utilize digital circuits, such as a DSP or an eFPGA, to make digital adjustments to static biasing of the wells. Embodiments of the self-optimizing circuits described herein utilize an analog feedback loop to regulate the potential of the wells to compensate for parametric shift dynamically, thereby eliminating the need for digital circuits and processing devices. The analog feedback includes a reference circuit to establish an optimal set-point for the overall self-optimizing circuit loop, and a TID dosimeter that replicates the FD-SOI devices under regulation to produce an "error" signal representing the parametric shift being experienced. Thus, the self-optimizing circuit continuously regulates the well potentials under the BOX based on the parametric shifts observed in the dosimeter devices.

At least some embodiments of the self-optimizing circuits described herein utilize a charge pump circuit out of the control loop to regulate the potential of the wells beneath the BOX. Some known techniques for body-biasing utilized charge pumping, but also either included the charge pump in the loop (which may experience longer recovery transients, with and without experiencing a radiation event), or utilized active components in the control feedback path (which would experience parametric shift themselves due to, for example, TID).

<FIG> is a cross-sectional view of one embodiment of a FD-SOI wafer <NUM> having an nMOS semiconductor device <NUM> and a pMOS semiconductor device <NUM>. FD-SOI wafer <NUM> includes a base silicon layer <NUM>, a buried oxide layer (BOX) <NUM>, and a silicon film <NUM>. BOX <NUM> is positioned on base silicon layer <NUM> between base silicon layer <NUM> and silicon film <NUM>. BOX <NUM> is an insulating layer formed on base silicon layer <NUM> for electrically isolating active semiconductor devices, such as nMOS semiconductor device <NUM> and pMOS semiconductor device <NUM>, from base silicon layer <NUM>. In certain embodiments, BOX <NUM> includes silicon dioxide and/or sapphire. In alternative implementations, BOX <NUM> may include any material that enables FD-SOI semiconductor <NUM> to operate as described herein.

Gates <NUM> are positioned over silicon film <NUM>. Silicon film <NUM> is doped to define a fully-depleted channel <NUM> between a source <NUM> and a drain <NUM>, thereby forming nMOS semiconductor device <NUM> and pMOS semiconductor device <NUM>, i.e., transistors. Within each of the transistors, BOX <NUM> reduces parasitic capacitance of source <NUM> and drain <NUM>, and efficiently confines electron flow from source <NUM> to drain <NUM>, thereby reducing performance-degrading leakage currents into base silicon layer <NUM>. FD-SOI wafer <NUM> also includes wells <NUM> and <NUM> defined within base silicon layer <NUM> beneath BOX <NUM>. Wells <NUM> and <NUM> are respectively doped to form well <NUM> as an N-well beneath pMOS semiconductor device <NUM>, and to form well <NUM> as a P-well beneath nMOS semiconductor device <NUM>. Wells <NUM> and <NUM> are charged, or biased, via respective contacts <NUM> and contact channels <NUM>. Notably, the type (e.g., p-type or n-type) and differentiation style of wells <NUM> and <NUM> may vary across different FD-SOI technologies. However, the manner in which wells <NUM> and <NUM> are biased according to the embodiments described herein applies equally across such FD-SOI technologies.

Wells <NUM> and <NUM> are biased against a change in the charge equilibrium (that results in parametric shifts) of nMOS semiconductor device <NUM> and pMOS semiconductor device <NUM>, due to charge trapped in BOX <NUM> as a result of TID. Generally, as TID accumulates over time, the level of biasing correction imparted over wells <NUM> and <NUM> necessary to mitigate the effects of the parametric shift increases. For example, as a voltage threshold of gate <NUM> for nMOS semiconductor device <NUM> shifts due to trapped charge at the interface of BOX <NUM> and fully-depleted channel <NUM>, an equal and opposite charge, i.e., biasing, is applied to well <NUM> via its respective contact <NUM> and contact channel <NUM>, thereby compensating for the parametric shift and returning the nMOS semiconductor device <NUM> to, or near to, its original calibrated state. Likewise, as the voltage threshold of gate <NUM> for nMOS semiconductor device <NUM> shifts due to trapped charge at the interface between gate <NUM> and fully-depleted channel <NUM>, a proportional and opposite biasing is applied to well <NUM> to compensate for the parametric shift. Notably, given the physical separation of gate <NUM> and BOX <NUM>, the level of biasing of well <NUM> is proportional - rather than equal to - the shift in threshold voltage, in order to produce a sufficient electric field in well <NUM> to counterbalance the charge at the interface of gate <NUM> and fully-depleted channel <NUM>.

<FIG> is a simplified illustrative schematic diagram of one implementation of a self-optimizing circuit <NUM> for a FD-SOI semiconductor device under optimization. The FD-SOI semiconductor device may be, for example, one or more semiconductor devices, such as nMOS semiconductor device <NUM> or pMOS semiconductor device <NUM> shown in <FIG>.

Self-optimizing circuit <NUM> includes a charge pump <NUM> or other voltage source, a dosimeter <NUM>, and a reference circuit <NUM>. Charge pump <NUM> is a clocked charge pump that generates a charge pump voltage at its output <NUM> that can be set to above the supply voltage (VDD) for self-optimizing circuit <NUM>, or below ground-level voltage (VSS) for self-optimizing circuit <NUM>. Notably, charge pump <NUM> is not actively controlled by any circuit other than a stationary clock or clocking circuit that may be incorporated within self-optimizing circuit <NUM> or provided independent thereof.

Dosimeter <NUM> and reference circuit <NUM> are connected in a bridge configuration between the supply voltage (VDD) and ground, and together produce a differential output to an operational transconductance amplifier (OTA) <NUM>. Dosimeter <NUM> includes a FD-SOI transistor <NUM>, having a well beneath its BOX (such as wells <NUM> and <NUM> and BOX <NUM> shown in <FIG> and not shown in <FIG>), that is similarly sensitive to TID as all of the FD-SOI semiconductor devices under optimization. Otherwise, the components of dosimeter <NUM> and reference circuit <NUM> are generally insensitive to radiation. The bridge configuration of dosimeter <NUM> and reference circuit <NUM> generally produces an equal voltage division of the supply voltage (VDD) under zero TID, which is to say an output from dosimeter <NUM>, or the dosimeter voltage <NUM>, is equal to an output from reference circuit <NUM>, or the reference voltage <NUM>. Reference circuit <NUM> includes a calibration resistance <NUM> to enable an initial calibration of the voltage divider within reference circuit <NUM> to the zero TID state of FD-SOI transistor <NUM> in dosimeter <NUM>. Otherwise, the voltage divider within reference circuit <NUM> produces a reference voltage <NUM> that is substantially invariant with respect to radiation, temperature, or age. As TID accumulates, reference voltage <NUM> functions as a set-point against which the dosimeter voltage <NUM> is compared to produce an error signal, or the differential voltage, that controls OTA <NUM>.

In the simplified illustrative embodiment shown in <FIG>, the gate of FD-SOI transistor <NUM> is coupled to its drain, thereby configuring it, functionally, as a diode having a gate-to-source voltage (VGS) that is sensitive to both MOS transistor voltage threshold shifts and mobility shifts within its fully-depleted channel. The voltage VGS, when FD-SOI transistor <NUM> is in saturation, is expressed as: <MAT> Where, VTH is the MOS threshold voltage, IDS is the drain-to-source (or, channel) current flowing in the device, W and L are respectively the width and length of the silicon channel (e.g. <NUM> in <FIG>), µN is the carrier mobility within the channel, and COX is the gate oxide capacitance per unit area, of transistor <NUM>.

Accordingly, due to the stability, or substantial invariance, of resistors within reference circuit <NUM> and dosimeter <NUM> to radiation (or aging, or temperature) effects as compared to FD-SOI transistor <NUM>, any imbalance exhibited between the respective outputs of dosimeter <NUM> and reference circuit <NUM>, i.e., between the dosimeter voltage <NUM> and the reference voltage <NUM>, can be attributed to parametric shifts experienced by FD-SOI transistor <NUM> as a result of radiation (or aging, or temperature) effects. Such imbalance, i.e., the differential output of the bridge configuration of dosimeter <NUM> and reference circuit <NUM>, is used by self-optimizing circuit <NUM> to control OTA <NUM> and thereby dynamically regulate the biasing of both the well of FD-SOI transistor <NUM> in dosimeter <NUM> and the well of the FD-SOI semiconductor devices under optimization (not shown in <FIG>, but optimized via biasing applied to node <NUM>). OTA <NUM> produces an output current, or bias, that is referenced to the charge pump voltage produced at the output <NUM> of charge pump <NUM>. The bias produced by OTA <NUM> is supplied to the wells (not shown in <FIG>) beneath FD-SOI transistor <NUM> and the FD-SOI semiconductor devices under optimization. Accordingly, the biasing of the well of FD-SOI transistor <NUM> restores the potential balance, or equilibrium between the dosimeter voltage <NUM>, or VGS, and the reference voltage <NUM>. Dosimeter <NUM> captures parametric aspects such as shifts due to radiation, temperature, or age that likewise are experienced over time by the FD-SOI semiconductor device in dosimeter <NUM>, or one or more other devices that are under optimization. The feedback loop as described is governed by dosimeter <NUM> output as compared to the output of reference circuit <NUM>, thereby enabling compensation for such shifts by dynamically regulating the potential of their respective wells (not shown in <FIG>) over that time.

Self-optimizing circuit <NUM> further includes a static biasing circuit <NUM> configured to produce an output current that is added to the output current generated by OTA <NUM> and supplied to wells (not shown in <FIG>) beneath FD-SOI transistor <NUM> and the FD-SOI semiconductor devices under optimization. Accordingly, even with a zero TID, static biasing circuit <NUM> enables self-optimizing circuit <NUM> to provide an optimal non-zero biasing of the wells (not shown in <FIG>) beneath FD-SOI transistor <NUM> and the FD-SOI semiconductor devices under optimization. For example, in one embodiment, static biasing circuit <NUM> applies a -<NUM>. 4V bias to the wells beneath FD-SOI transistor <NUM> and the FD-SOI semiconductor devices under optimization. In other embodiments, the optimal static bias may be set from about ±<NUM>. 5V to about ±<NUM>. 2V, depending on specific technology and circuit operation. Static biasing circuit <NUM> includes an OTA <NUM> controlled by a plurality of resistors coupled to supply a static reference voltage, defined by the supply voltage (VDD) and the ratios of resistive values of the plurality of resistors, to a negative input of OTA <NUM>; and a feedback signal from the static regulation loop, coupled to a positive input of OTA <NUM>. The output of OTA <NUM> is referenced to the charge pump voltage produced at the output <NUM> of charge pump <NUM>, and is coupled with the output of OTA <NUM>. The combined current produced by OTA <NUM> and OTA <NUM>, both referenced to the charge pump voltage, is supplied to the wells (not shown in <FIG>) beneath FD-SOI transistor <NUM> and the FD-SOI semiconductor devices under optimization.

Self-optimizing circuit <NUM> includes a low-dropout (LDO) regulator <NUM> configured to regulate the voltage applied to the well (not shown in <FIG>) beneath FD-SOI transistor <NUM> at a dosimeter well node <NUM>. LDO regulator <NUM> utilizes the charge pump voltage supplied at output <NUM> of charge pump <NUM> as a voltage input at the source of a transistor <NUM>, the gate of which is controlled by the combined output from OTA <NUM> and OTA <NUM> (not shown in <FIG>). The output voltage of LDO regulator <NUM>, at the source of transistor <NUM>, is supplied to the dosimeter well node <NUM>. LDO regulator <NUM> includes a feedback path <NUM> via a voltage divider <NUM> to OTA <NUM>. Accordingly, the output from OTA <NUM> functions as an error signal representing a differential between the voltage on feedback path <NUM> and the supply voltage (VDD) scaled through the radiation-insensitive resistive partition of static biasing circuit <NUM>.

Charge pump <NUM> is operated by a system clock such that it can normally supply a constant voltage above the supply voltage (VDD) or below ground voltage (GND). For example, in certain embodiments, charge pump <NUM> generates a constant + or - 3V. LDO regulator <NUM> subsequently regulates the charge pump voltage as it is applied to the dosimeter well node <NUM> by closing its feedback path <NUM> via the differential input to OTA <NUM> in static biasing circuit <NUM>.

In certain embodiments, self-optimizing circuit <NUM> includes a switch <NUM> that enables or disables the independent regulation of the well potential beneath FD-SOI transistor <NUM> in dosimeter <NUM>, and of the well potential in the FD-SOI semiconductor devices under optimization. When closed, switch <NUM> links the well potentials at dosimeter well node <NUM> and a device well node <NUM> that represents the potential of the well beneath the FD-SOI semiconductor device under optimization, enabling a precise regulation of the well node <NUM> as it remains closed in the loop.

When opened, switch <NUM> decouples the well potentials, forcing device well node <NUM> to track dosimeter well node <NUM> only indirectly, by virtue of device well node <NUM> being coupled at the output of a replica LDO regulator driver stage <NUM> having a transistor <NUM> and voltage divider <NUM>, precisely ratioed to transistor <NUM> and voltage divider <NUM>, i.e., the driver stage of LDO regulator <NUM>. Notably, voltage dividers <NUM> and <NUM> have identical ratios and are purely resistive to limit any TID, temperature, or age effects in the feedback path of LDO regulator <NUM> or LDO driver stage <NUM>, thereby maintaining feedback path <NUM>, and the operation of the overall self-optimizing circuit <NUM>, as insensitive to TID, temperature, and age effects as possible. Accordingly, LDO regulator <NUM> and replica LDO driver stage <NUM> regulate the biasing of the wells via dosimeter well node <NUM> (for the local well) and device well node <NUM> (for the larger well of the whole device under optimization), compensating for parametric shifts in the VGS voltage of FD-SOI transistor <NUM> in dosimeter <NUM>, and at least similarly in the FD-SOI semiconductor device under optimization.

When switch <NUM> is closed, the well (not shown in <FIG>) beneath the FD-SOI semiconductor device under optimization is incorporated into the control loop of self-optimizing circuit <NUM>, along with the well beneath FD-SOI transistor <NUM> of dosimeter <NUM>. Under such operation, although the voltage applied at device well node <NUM> is more tightly and directly controlled, the capacitive loading of the "combined" well is generally unknown. Therefore, it can destabilize the control loop by adding poles that subtract phase margin to the loop gain, causing undesired voltage ringing (e.g., upon Single Event Effect, or heavy-ion radiation strikes). These disadvantages can be addressed with a pole-zero cancellation technique, or via corresponding gain reductions in OTA <NUM> and OTA <NUM>. Additionally, the leakage current of the combined well may accumulate such that it may interfere with precision of feedback path <NUM>. In certain embodiments, the leakage current may grow to multiple microamperes, as it varies exponentially with temperature. Given the potential size of the well beneath the FD-SOI semiconductor device or devices under optimization, the leakage current can introduce a significant offset bias that may, in certain circumstances, overcome the capacity of charge pump <NUM> and render the biasing function of self-optimizing circuit <NUM> inoperative.

Conversely, when switch <NUM> is opened, LDO regulator <NUM> and replica LDO driver stage <NUM> operate independently. Moreover, replica LDO driver stage <NUM> itself can be replicated multiple times to provide an independent, more flexible regulation of the potential of fragmented wells of various FD-SOI semiconductor devices under optimization. Similarly, charge pump <NUM> may be replicated to further isolate the driving capacity of the wells beneath the FD-SOI semiconductor devices under optimization, from the local driving capacity for the well of FD-SOI transistor <NUM> in dosimeter <NUM>, reducing undesirable noise and interference effects. In an alternative embodiment, charge pump <NUM> may be designed such that it is rated for greater capacity, e.g., <NUM>-<NUM>% greater than the theoretical (±) VDS+Vwell voltage required for operating LDO regulator <NUM> and replica LDO driver stage <NUM>.

In an alternative embodiment, the driver stages of the LDO loop are modified to include a level-shifting servo driver operating as the voltage source. In certain embodiments, the level-shifting servo driver may simplify the implementation of OTA <NUM> and OTA <NUM>, because the correct voltage level coupled to the gates of transistors <NUM> and <NUM> is translated by the level shifters. Accordingly, simpler single-supply amplifiers can then be referenced to a common ground instead of to the charge pump voltage generated at output <NUM> of charge pump <NUM>.

<FIG> comprises plots <NUM> of the results of a simulation of self-optimizing circuit <NUM>, shown in voltage on vertical axis, <NUM>, <NUM>, and <NUM>. An arbitrary VGS shift ranging from -100mV to +100mV, shown on horizontal axis <NUM>, was imparted on dosimeter transistor <NUM> of dosimeter <NUM> to simulate the TID effects on a FD-SOI semiconductor device, such as nMOS semiconductor <NUM> or pMOS semiconductor <NUM>. A <NUM>:<NUM> linear relationship between the well bias and the same threshold voltage (VTH) of the semiconductor device was assumed for simplicity, and a voltage-controlled voltage source was added in series to the same device.

Plots <NUM> illustrate an original shift in voltage illustrated in plot <NUM> of the dosimeter voltage <NUM> from dosimeter <NUM> and plot <NUM> of reference voltage <NUM> from reference circuit <NUM>. Self-optimizing circuit <NUM> compensates the original shift when a bias <NUM> is supplied to the well of the semiconductor device <NUM>. The bias <NUM> applied to the well is in addition to the optimized static nominal voltage <NUM> applied to the well. The latter voltage would have been set upon the initial calibration of dosimeter <NUM> and reference circuit <NUM>.

Plot <NUM> shows the residual shift still present after the compensation enacted by the self-optimizing circuit on the VGS of the dosimeter transistor <NUM>. Again, assuming a <NUM>:<NUM> impact over the gate voltage effected by a back-bias well voltage modulation, out of ±100mV only a total of ~<NUM>. 3mV residual shift remains (plot <NUM>), showing > 40dB rejection of circuit <NUM>.

<FIG> is a plot <NUM> of the initial settling of self-optimizing circuit <NUM>. Plot <NUM> shows voltage represented by a vertical axis <NUM> and expressed in Volts, versus time represented on the horizontal axis <NUM> and expressed in microseconds. The initial settling of self-optimizing circuit <NUM> was simulated without initial conditions, when charge pump <NUM> had already settled down to -<NUM>. 4V, for example. The simulation was conducted assuming a small (approximately 100fF) local well capacitance, a 60dB OTA gain with Gain-Bandwidth Product (GBWP) of <NUM> Megahertz (MHz), followed by the driving stage of the LDO, and showed excellent stability. However, if a larger well under a large circuit was closed in the same loop, ringing on all waveforms could worsen. The stability test results shown in <FIG> indeed can be used to mimic the recovery of self-optimizing circuit <NUM> after an ion strike. In the simulation for which results are shown in <FIG>, the well beneath FD-SOI transistor <NUM> is separated from the wells beneath the devices under optimization, because the larger charge collection area, augmented by funnel effects beyond the BOX, may partially negate the SOI insulation benefit. Generally, ion strikes would still affect LDO regulator <NUM>, but at least would have less impact on the stability of the loop, nor engender long-duration ringing.

The final settling of the potential of the well beneath the device under optimization is shown as plot <NUM>, which is shifted by greater than -99mV from the original well voltage state (a constant shown in plot <NUM>, for ease of comparison). The shift in the differential output from dosimeter <NUM> and from reference circuit <NUM> are shown by plot <NUM> of dosimeter voltage <NUM>, and plot <NUM> of reference voltage <NUM>. Accordingly, plot <NUM> of residual shift in VGS illustrates almost complete compensation of a 100mV shift. Therefore, assuming <NUM>:<NUM> impact over VTH, in the simulation whose results are shown in <FIG>, only ~<NUM>. 7mV residual shift in the VGS remains from an original value of +100mV equivalent VTH shift imparted on FD-SOI transistor <NUM> in dosimeter <NUM>.

<FIG> is a schematic diagram of another embodiment of a dosimeter <NUM>. Dosimeter <NUM> is substantially similar to dosimeter <NUM> with the addition of an amplifier <NUM>, and connection of the resistive bridge to the output of amplifier <NUM> rather than to the supply VDD. Similar to the embodiment shown in <FIG>, reference circuit <NUM> and dosimeter <NUM> are coupled in a bridge configuration such that a differential voltage is supplied to an input of amplifier <NUM>. The output of amplifier <NUM> then becomes the dosimeter voltage output <NUM>, and another reference circuit, such as reference circuit <NUM>, likewise provides the reference voltage <NUM> to OTA <NUM> (shown in <FIG>). Notably, the resistors at the top of the bridge, or matched PMOS loads in the alternative, provide independence from supply variations by virtue of the amplifier's Power Supply Rejection (PSR) characteristics.

In another alternative implementation, dosimeter <NUM> may include inverter structures combining N and P FETs, rather than a single FD-SOI transistor. The single or multiple wells are still tuned continuously in such an implementation, but may require one or more feedback loops with LDO driving stages similar to LDO regulators <NUM> and replica LDO driver stage <NUM>. Such inverter structures would function as combined N/P shift monitors, for example, for applications where a more punctual discrimination N vs. P shift dosimetry may not be required. In yet another alternative implementation, oscillator type sensors, referred to as "silicon odometers," can be used. In such embodiments, rather than by more commonplace digital counters, the frequency of the oscillator-type sensors is converted back to current by way of a frequency-to-current converter, fed into a resistor or resistive divider, and used to generate a voltage analog error signal analogous to the one described for dosimeter <NUM>.

In yet another alternative implementation, an oscillator-based dosimeter may be implemented by enclosing a ring oscillator into a voltage reference with a topology similar to dosimeter <NUM>, but with dynamically tunable resistors, that has been designed to emphasize TID effects. This dosimeter embodiment is very compact, and automatically generates a voltage as a function of frequency. Also, as opposed to NMOS+PMOS complementary inverters, purely NMOS and/or PMOS-based inverter structures can be included in the ring, to construct an oscillator that is sensitive to N- and P- TID only; and therefore, the loop can be driven for the separate optimization of different wells.

If a diode and a resistor network are included in a voltage reference loop to act as a dosimeter, as shown in dosimeter <NUM>, an additional TID shift amplification can be built into the TID mitigation loop of the self-optimizing circuit. This increases the loop gain, and ultimately the efficacy of self-optimizing circuit <NUM> in minimizing, or compensating for, radiation variations. Since supply voltage VDD can be subjected to a lot of interference in a large IC, constructing a supply-independent dosimeter that exploits the high PSR of an amplifier also enables a much cleaner operation of self-optimizing circuit <NUM>, which otherwise would be led to track spurious supply transients, rather than long-term TID, aging, and temperature drifts.

The configuration of dosimeter <NUM> (shown in <FIG>) including a diode (rather than switched-capacitor resistors, as more suited to oscillator-based dosimeters), and retaining matched resistors on the top branches as illustrated in <FIG>, was simulated in the same fashion used to generate plots <NUM> shown in <FIG>. <FIG> is a plot <NUM> of the simulation results of an initial transient of the TID compensation loop, including the dosimeter shown in <FIG>. The transient settling is less stable than the corresponding trajectories in <FIG>, reflecting the additional gain contribution of the local loop that has been added through dosimeter <NUM>. Specifically, the local feedback topology shown in <FIG> includes a single-pole limitation imposed by the GBWP of the amplifier. The added singularity would contribute to destabilize the overall circuit. However, a Miller zero in LDO regulator <NUM> of self-optimizing circuit <NUM> shown in <FIG> retains stability (e.g., within <NUM>), as displayed in <FIG>. As a beneficial counterpart to this trade-off, the slope of the dosimeter output more than doubles, as compared to the same identical open-loop dosimeter built with resistors and an NMOS FET. This leads to a tighter effect mitigation by self-optimizing circuit <NUM>. For example, rather than <NUM>. 3mV variability upon ±100mV VTH change, dosimeter <NUM> closed in the loop now yields only 510µV shift, or 52dB rejection of TID shifts. While an additional dosimeter amplifier <NUM> must be included, it also helps significantly reduce the sensitivity to supply shifts of dosimeter <NUM>. Incidentally, if so desired, dosimeter <NUM> can be designed to desensitize the response to temperature variations of self-optimizing circuit <NUM>.

Self-optimizing circuit <NUM> may also be used to counter aging mechanisms, or other effects. The effects of oxide and channel lattice degradation in FET devices over time tend to shift the performance of circuits in at least a similar fashion as described with respect to radiation (which can be considered an "accelerated aging" equivalent mechanism). Such similarities support an effectiveness of self-optimizing circuit <NUM> to counter aging drifts as well as radiation drifts. That is, once the dosimeter (or, more properly in this new context, the "reference circuit") drifts away from its nominal setting initially established in the factory, the loop will attempt to correct for the shift acting on the back-bias, regardless of its origin. Rather than a TID dosimeter sensor, in this implementation, self-optimizing circuit <NUM> includes an "odometer" such as, for example, a ring oscillator. Additional circuitry may be designed, for example, around a frequency synthesizer inside the loop, to generate an output voltage with high sensitivity to the frequency of the oscillator, thus a sensitivity to aging effects.

Similarly, self-optimizing circuit <NUM> may also compensate for temperature drift effects. The temperature drift imparted on the dosimeter, or "reference circuit," would determine an error signal used to steer the well bias control to correct the shift.

Notably, the TID effects trap charge at the interface of the BOX, and the electric field engendered by the charge is physically countered by an opposite field, i.e., the one the self-optimizing circuit activates by moving an opposite quantity of charge in the underlying well (slightly adjusted to account for surface dielectric and geometrical discrepancies between the trapped charge and the countering charge). Accordingly, an undesirable effect is compensated directly by a reaction on the same physical quantities, i.e., the charge at or beneath BOX <NUM>. All electrical effects, or parametric shifts, caused by the original TID will thus be compensated for by a dynamically regulated counterbalance of the original trapped charge, rather than by a compensation of its symptoms only.

Aging effects result in structural modifications of the gate oxide or of the underlying carrier channel lattice as determined by silicon "wear-out. " Temperature drifts include work function shifts and depletion region thickness modulation. Neither of these processes reflects physical modifications of a well potential, such as that applied to wells <NUM> and <NUM> shown in <FIG>. Therefore, unlike TID compensation techniques, these effects are compensated by a "proxy" electrical reaction that leads to an indirect compensation of their symptoms through a different mechanism, while the original sources of drift are not physically reversed. In certain embodiments, dosimeters may be selected that are sensitive to TID only, or to TID and aging, but, e.g., can be made insensitive to supply voltage variations, as well as (less commonly) to temperature variations.

Claim 1:
A self-optimizing circuit (<NUM>) for a primary fully-depleted silicon-on-insulator, FD-SOI, device having a buried oxide layer, BOX, and a primary well disposed beneath the BOX, the self-optimizing circuit comprising:
a static biasing circuit (<NUM>) configured to supply a static bias;
a total ionizing dose, TID, dosimeter (<NUM>) comprising a dosimeter FD-SOI device, wherein the TID dosimeter is configured to generate a dosimeter voltage representing parametric shifts in the primary FD-SOI device;
a reference circuit (<NUM>) configured to supply an invariant reference voltage (Rref);
an operational transconductance amplifier, OTA, (<NUM>) coupled to the TID dosimeter and the reference circuit, wherein the operational transconductance amplifier is configured to supply a dynamic bias at an output of the static biasing circuit, wherein the dynamic bias is proportional to a difference between the dosimeter voltage and the reference voltage;
a voltage source (<NUM>) configured to generate a drive voltage to which the static bias and the dynamic bias are referenced; and
a feedback circuit configured to regulate supply of the drive voltage applied to a well of the dosimeter FD-SOI device based on a combination of the static bias and the dynamic bias.