Patent Description:
Conventionally, semiconductor devices have been known in which transistors such as insulated gate bipolar transistors (IGBTs) are provided (refer to Patent Document <NUM> to <NUM>, for example). Furthermore, Patent Document <NUM> discloses a semiconductor device, wherein a recovery effect of a gate threshold voltage by hydrogen annealing may be obtained in which a front electrode made of aluminum is embedded in a contact hole. This document discloses a moderately doped base region with a highly-doped base contact region thereon. The emitter electrode penetrates into the upper part of the highly-doped base contact region and a film of very highly doped semiconductor material is deposited in the recess in the highly doped base contact region.

Patent Document <NUM> also discloses a semiconductor device, wherein at least one of an accumulation region and a dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion. Eventually, Patent Document <NUM> also discloses a semiconductor device, wherein a p-type floating region is surrounded by an emitter groove and is not adjacent to a gate groove in order to reduce noise to the gate electrode GE during an operation of the IGBT.

A semiconductor device preferably has a small loss.

To solve the above problem, a semiconductor device having the features of independent claim <NUM> is provided. Preferable embodiments are claimed by the dependent claims.

A second aspect of the present invention provides a production method of a semiconductor device according to claim <NUM>.

A preferred embodiment is claimed in claim <NUM>.

Hereinafter, the present invention will be described with reference to embodiments of the invention. However, the following embodiments shall not be construed as limiting the claimed invention. Also, not all combinations of features described in the embodiments are essential for means to solve problems provided by aspects of the invention.

In this specification, one side of the semiconductor substrate in the direction parallel to the depth direction is referred to as "upper" and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is implemented.

In this specification, the orthogonal coordinate axes of the X, Y and Z axes may be used to describe technical matters. The orthogonal coordinate axes only identify the relative positions of the components and does not limit the specific direction. For example, the Z axis does not indicate a limited height direction with respect to the ground. Additionally, the +Z axis direction and the -Z axis direction are opposite directions to each other. When described as the Z axis direction without describing positive or negative, it means the direction parallel to the +Z and -Z axes. And in this specification, viewing from the +Z axis direction may be referred to as a top view.

In this specification, when referred to as "same" or "equal", it may also include cases with errors due to producing variation and so on. The errors in this case are, for example, within <NUM>%.

In this specification, the conductive type of the doping region doped with impurities is described as P type or N type. However, the conductive type of each doping region may also be of the opposite polarity. Also, in this specification, when described as P+ type or N+ type, it means the doping concentration is higher than P type or N type; when described as P- type or N- type, it means the doping concentration is lower than P type or N type. Also, in this specification, when described as P++ type or N++ type, it means the doping concentration is higher than P+ type or N+ type.

In this specification, the doping concentration refers to the concentration of impurity activated as the donor or acceptor. In this specification, the concentration difference of the donor and acceptor may be the doping concentration. The concentration difference in this case can be measured by voltage-capacitance measurement method (CV method). Also, the carrier concentration measured by spreading resistance measurement method (SR) may be the doping concentration. Also, when there is a peak in the doping concentration distribution, the peak value in this case may be the doping concentration in the region. In the case where the doping concentration is approximately uniform in a region where the donor or acceptor exists or the like, the average value of the doping concentration may be the doping concentration in the region. Also, the dopant concentration in this specification refers to the respective concentrations of the donor and acceptor.

<FIG> illustrates a top view showing one example of a semiconductor device <NUM> according to one embodiment of the present invention. In <FIG>, the projected position of each member on the upper surface of the semiconductor substrate <NUM> is shown. In <FIG>, only some of the members of the semiconductor device <NUM> are shown, and some of the members are omitted.

The semiconductor device <NUM> includes a semiconductor substrate <NUM>. The semiconductor substrate <NUM> is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate <NUM> has an end side <NUM> in a top view. In this specification, when simply referring to a top view, it means viewing from the upper surface side of the semiconductor substrate <NUM>. The semiconductor substrate <NUM> of this example has two pairs of end sides <NUM> facing each other in a top view. In <FIG>, the X axis and the Y axis are parallel to any of the end sides <NUM>. And the Z axis is perpendicular to the upper surface of the semiconductor substrate <NUM>.

An active portion <NUM> is provided in the semiconductor substrate <NUM>. The active portion <NUM> is the region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate <NUM>, when the semiconductor device <NUM> is controlled to the on-state. Although the emitter electrode is provided above the active portion <NUM>, it is omitted in <FIG>.

A transistor portion <NUM> including transistor elements such as IGBTs is provided in the active portion <NUM>. A diode portion <NUM> including diode elements such as freewheeling diodes (FWDs) may also be further provided in the active portion <NUM>.

In <FIG>, the region where the transistor portion <NUM> is arranged is marked with symbol "I" and the region where the diode portion <NUM> is arranged is marked with symbol "F". The transistor portion <NUM> and the diode portion <NUM> are arranged side-by-side along a predetermined array direction (the X axis direction in <FIG>). The transistor portion <NUM> and the diode portion <NUM> may be arranged alternately side-by-side in the X axis direction. In this specification, the direction perpendicular to the array direction in a top view may be referred to as an extending direction (the Y axis direction in <FIG>). Each of the transistor portion <NUM> and the diode portion <NUM> may have a longitudinal length in the extending direction. That is, the length in the Y axis direction of the transistor portion <NUM> is greater than the width in the X axis direction. Similarly, the length in the Y axis direction of the diode portion <NUM> is greater than the width in the X axis direction. The extending directions of the transistor portion <NUM> and the diode portion <NUM> may be the same as the longitudinal direction of the trench portion.

The diode portion <NUM> has an N+ type cathode region in the region in contact with the lower surface of the semiconductor substrate <NUM>. In this specification, the region where the cathode region is provided is referred to as the diode portion <NUM>. That is, the diode portion <NUM> is a region overlapping the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate <NUM>. In this specification, the extension region <NUM> that has extended the diode portion <NUM> to the gate runner described below in the Y axis direction may also be included in the diode portion <NUM>. A collector region is provided on the lower surface of the extension region <NUM>.

The semiconductor device <NUM> may have one or more pads above the semiconductor substrate <NUM>. The semiconductor device <NUM> of this example has a gate pad <NUM>. The semiconductor device <NUM> may also have pads such as anode pads, cathode pads and current detection pads. Each pad is arranged in the vicinity of the end side <NUM>. The vicinity of the end side <NUM> refers to a region between the end side <NUM> and the emitter electrode in a top view. During implementing the semiconductor device <NUM>, each pad may be connected to an external circuit via a wiring such as a wire.

A gate potential is applied to the gate pad <NUM>. The gate pad <NUM> is electrically connected to a conductive portion of a gate trench portion of an active portion <NUM>. The semiconductor device <NUM> includes a gate runner connecting the gate pad <NUM> and the gate trench portion. In <FIG>, the gate runner is marked by oblique hatched lines.

The gate runner of this example has an outer circumferential gate runner <NUM> and an active side gate runner <NUM>. The outer circumferential gate runner <NUM> is arranged between the active portion <NUM> and the end side <NUM> of the semiconductor substrate <NUM> in a top view. The outer circumferential gate runner <NUM> of this example encloses the active portion <NUM> in a top view. The region enclosed by the outer circumferential gate runner <NUM> in a top view may also be referred to as the active portion <NUM>. Also, the outer circumferential gate runner <NUM> is connected to the gate pad <NUM>. The outer circumferential gate runner <NUM> is arranged above the semiconductor substrate <NUM>. The outer circumferential gate runner <NUM> may be a metallic wiring.

The active side gate runner <NUM> is provided in the active portion <NUM>. By providing the active side gate runner <NUM> in the active portion <NUM>, it is possible to reduce the variation in the runner length from the gate pad <NUM> in each region of the semiconductor substrate <NUM>.

The active side gate runner <NUM> is connected to the gate trench portion of the active portion <NUM>. The active side gate runner <NUM> is arranged above the semiconductor substrate <NUM>. The active side gate runner <NUM> may be a runner formed of a semiconductor such as polysilicon doped with impurities.

The active side gate runner <NUM> may be connected to the outer circumferential gate runner <NUM>. The active side gate runner <NUM> of this example is provided to extend in the X axis direction from one outer circumferential gate runner <NUM> to the other outer circumferential gate runner <NUM> at substantially the center in the Y axis direction so as to cross the active portion <NUM>.

Also, the semiconductor device <NUM> may also include a not shown temperature sense portion that is a PN junction diode formed of polysilicon and so on, or a not shown current detection portion for simulating operations of the transistor portion provided in the active portion <NUM>.

The semiconductor device <NUM> of this example includes an edge termination structure portion <NUM> between the outer circumferential gate runner <NUM> and the end side <NUM>. The edge termination structure portion <NUM> relaxes the electric field concentration on the upper surface side of the semiconductor substrate <NUM>. The edge termination structure portion <NUM> has, for example, a guard ring, a field plate, a RESURF and a combination of these structures provided annularly enclosing the active portion <NUM>.

<FIG> illustrates an enlarged view of the region A in <FIG>. The region A is a region including the transistor portion <NUM>, the diode portion <NUM> and the active side gate runner <NUM>. In the semiconductor substrate <NUM> of this example, a gate trench portion <NUM>, a dummy trench portion <NUM>, a well region <NUM>, an emitter region <NUM>, a base region <NUM> and a contact region <NUM> are provided in contact with the upper surface of the semiconductor substrate <NUM>. Also, in the semiconductor substrate <NUM> of this example, a cathode region <NUM> and a collector region <NUM> are provided in contact with the lower surface of the semiconductor substrate <NUM>.

Also, an emitter electrode <NUM> and an active side gate runner <NUM> are provided above the semiconductor substrate <NUM>. The emitter electrode <NUM> is in contact with the emitter region <NUM>, the contact region <NUM> and the base region <NUM> on the upper surface of the semiconductor substrate <NUM>. Also, the emitter electrode <NUM> is connected with the dummy conductive portion of the dummy trench portion <NUM>. An interlayer dielectric film may also be provided between the emitter electrode <NUM> and the semiconductor substrate <NUM>. Contact holes for connecting the emitter electrode <NUM> and the semiconductor substrate <NUM> may be provided on the interlayer dielectric film.

An insulating film such as a thermal oxide film is provided between the active side gate runner <NUM> and the semiconductor substrate <NUM>. The active side gate runner <NUM> is connected with the gate conductive portion inside the gate trench portion <NUM> on the upper surface of the semiconductor substrate <NUM>. The active side gate runner <NUM> is not connected with the dummy conductive portion inside the dummy trench portion <NUM>. The gate trench portion <NUM> is provided extending in the Y axis direction to the bottom of the gate runner of the active side gate runner <NUM> and so on. The gate conductive portion of the gate trench portion <NUM> is connected with the gate runner.

The well region <NUM> is provided below the active side gate runner <NUM>. The well region <NUM> is a region with a higher doping concentration than the base region <NUM>, which is formed in contact with the upper surface of the semiconductor substrate <NUM>, and is formed to a position deeper than the bottom portion of the base region <NUM>. The width of the well region <NUM> in the Y axis direction may be larger than the width of the active side gate runner <NUM> in the Y axis direction.

A gate trench portion <NUM> is provided in the transistor portion <NUM>. A dummy trench portion <NUM> is provided in the diode portion <NUM>. A dummy trench portion <NUM> may also be provided in the transistor portion <NUM>. The gate trench portion <NUM> functions as a gate electrode on which a gate potential is applied in the transistor portion <NUM>. An emitter potential is applied on the dummy trench portion <NUM>.

The gate trench portion <NUM> and the dummy trench portion <NUM> have longitudinal lengths in the Y axis direction in a top view. That is, the gate trench portion <NUM> and the dummy trench portion <NUM> are provided to extend in the Y axis direction. The gate trench portion <NUM> and the dummy trench portion <NUM> may have linear portions parallel to the Y axis direction.

Each trench portion of the gate trench portions <NUM> and the dummy trench portions <NUM> are arranged with a predetermined interval in the X axis direction. It is noted that the array patterns of the gate trench portion <NUM> and the dummy trench portion <NUM> are not limited to the example of <FIG>. The group of one or more gate trench portions <NUM> and the group of one or more dummy trench portions <NUM> may be alternately arranged along the X axis direction.

At least one trench portion may have the edges of the two linear portions connected by the curve-shaped edge portion. In the example of <FIG>, the gate trench portion <NUM> has two linear portions <NUM> and one edge portion <NUM>. Also, the dummy trench portion <NUM> may also similarly have two linear portions <NUM> and one edge portion <NUM>. The dummy trench portion <NUM> may also only have a linear portion. The respective edges of the trench portions in the Y axis direction may be arranged in the interior of the well region <NUM>. In this way, the electric field concentration at the edges of the trench portions can be relaxed.

In this specification, in the X axis direction, the region of the semiconductor substrate <NUM> sandwiched by two linear portions of the trench portion may be referred to as a mesa portion. The mesa portion <NUM> is provided in the transistor portion <NUM>, and the mesa portion <NUM> is provided in the diode portion <NUM>. The mesa portion is a region in the portions of the semiconductor substrate <NUM> sandwiched by the trench portions on the upper surface side deeper than the deepest bottom portion of the trench portion.

A P- type base region <NUM> is provided in each mesa portion. The base region <NUM> is exposed on a part of the upper surface of the mesa portion. Contact regions <NUM> and emitter regions <NUM> are provided on the upper surface of the base region <NUM> of the transistor portion <NUM>. The contact regions <NUM> of this example are of a P+ type with a higher doping concentration than the base region <NUM>. The emitter regions <NUM> of this example are of an N+ type with a higher doping concentration than the drift region described below.

The emitter regions <NUM> are provided in contact with the gate trench portion <NUM> on the upper surface of the semiconductor substrate <NUM>. The emitter regions <NUM> and the contact regions <NUM> of this example are provided from one trench portion sandwiching the mesa portion <NUM> to the other trench portion. The contact regions <NUM> and the emitter regions <NUM> are arranged alternately along the Y axis direction on the upper surface of the mesa portion <NUM> of this example.

In another example, the contact regions <NUM> and the emitter regions <NUM> may also be provided in a striped pattern along the Y axis direction in the mesa portion <NUM>. For example, the emitter regions <NUM> are provided in the region adjacent to the trench portion, and the contact regions <NUM> are provided in the region sandwiched by the emitter regions <NUM>. On the upper surface of the mesa portion <NUM>, the base regions <NUM> may be arranged to sandwich the region where the contact regions <NUM> and the emitter regions <NUM> are provided in the Y axis direction.

The emitter regions <NUM> may not be provided in the mesa portion <NUM> of the diode portion <NUM>. The base region <NUM> is provided on the upper surface of the mesa portion <NUM> of this example. The base region <NUM> may occupy a half or more of the area of the upper surface of the mesa portion <NUM>. The contact regions <NUM> may be arranged on the upper surface of the mesa portion <NUM>. The contact region <NUM> of the mesa portion <NUM> may be provided in the position overlapping the end of the trench contact <NUM> in the Y axis direction. The base regions <NUM> may be provided to sandwich the contact region <NUM> in the Y axis direction on the upper surface of the mesa portion <NUM>.

In each of the mesa portions <NUM> and mesa portions <NUM>, a trench contact <NUM> is provided. The trench contact <NUM> includes a contact trench (groove portion) formed from the upper surface of the semiconductor substrate <NUM> to the interior of the semiconductor substrate <NUM>, and a conductive portion filled inside the trench. The conductive portion may be formed of the same material as the emitter electrode <NUM> continuously with the emitter electrode <NUM>, may also be formed of a different material from the emitter electrode <NUM>.

The trench contact <NUM> penetrates the contact regions <NUM> in the depth direction (the Z axis direction). That is, by providing the trench contact <NUM>, the volume of the contact regions <NUM> is reduced. In this way, when the gate of the transistor portion <NUM> is turned to be in the off-state and diode operations start, the hole injection from the contact regions <NUM> can be suppressed. Therefore, the reverse recovery loss in the diode portion <NUM> can be reduced.

Also, by providing the trench contact <NUM>, the contact area between the conductive portion and the semiconductor substrate <NUM> can be increased. Therefore, even if the widths in the X axis direction of the mesa portion <NUM> and the mesa portion <NUM> are miniaturized, increase in the contact resistance between the emitter electrode <NUM> and the semiconductor substrate <NUM> can be suppressed.

The width of the trench contact <NUM> in the X axis direction is less than the width in the X axis direction of each mesa portion. The both ends of the trench contact <NUM> in the Y axis direction may be provided in the contact regions <NUM> arranged in the both ends in the Y axis direction among the contact regions <NUM> of each mesa portion.

The lengths of the trench contact <NUM> provided in the mesa portion <NUM> and the trench contact <NUM> provided in the mesa portion <NUM> may be the same in the Y axis direction, or may be different. In the mesa portion <NUM>, the trench contact <NUM> is provided above each region of the contact regions <NUM> and the emitter regions <NUM>. The contact regions <NUM> and the emitter regions <NUM> may be arranged in the range where the trench contact <NUM> is provided. The trench contact <NUM> of this example is not provided in the regions corresponding to the base region <NUM> and the well region <NUM> of the mesa portion <NUM>. In the mesa portion <NUM>, the trench contact <NUM> is provided above the contact regions <NUM> and the base region <NUM>. However, the trench contact <NUM> is not provided above the base region <NUM> that is sandwiched by the contact regions <NUM> and the well region <NUM> in the mesa portion <NUM>.

In the diode portion <NUM>, an N+ type cathode region <NUM> is provided in the region in contact with the lower surface of the semiconductor substrate <NUM>. In the region where a cathode region <NUM> is not provided in the region in contact with the lower surface of the semiconductor substrate <NUM>, a collector region <NUM> is provided. In the Y axis direction, the cathode region <NUM> is arranged away from the well region <NUM>. At least one of the base region <NUM> and the contact regions <NUM> may be arranged between the cathode region <NUM> and the well region <NUM> in a top view. In this example, the distance in the Y axis direction between the cathode region <NUM> and the well region <NUM> is greater than the distance in the Y axis direction between the trench contact <NUM> and the well region <NUM>.

<FIG> illustrates another exemplary arrangement of the cathode region <NUM> in a top view. In the cathode region <NUM> of this example, the position of the end in the Y axis direction matches the position of the end of the trench contact <NUM>. Since the extraction of a carrier becomes easy by providing the trench contact <NUM>, even if the cathode region <NUM> is arranged closer to the well region <NUM>, the breakdown voltage becomes easy to secure.

The position of the end in the Y axis direction of the cathode region <NUM> may also not match the position of the end of the trench contact <NUM>. The end in the Y axis direction of the cathode region <NUM> may be provided in the position overlapping the contact regions <NUM>. The end in the Y axis direction of the cathode region <NUM> may also be arranged between the trench contact <NUM> and the well region <NUM>.

<FIG> illustrates one example of the b-b cross section in <FIG> and <FIG>. The b-b cross section is the XZ plane crossing the contact regions <NUM>. The semiconductor device <NUM> of this example has a semiconductor substrate <NUM>, an emitter electrode <NUM> and a collector electrode <NUM> in the cross section.

The emitter electrode <NUM> may be in contact with the upper surface <NUM> of the semiconductor substrate <NUM> in each mesa portion. That is, an insulating film is not provided between each mesa portion and the emitter electrode <NUM>. The insulating film is embedded in the trench portion without extending directly above each mesa portion. The emitter electrode <NUM> may be in contact with the upper surface <NUM> in the range including a plurality of mesa portions and a plurality of trench portions. According to such a configuration, even if the width in the X axis direction of the mesa portion is miniaturized, the contact area between the mesa portion and the emitter electrode <NUM> can be secured.

The collector electrode <NUM> may be provided throughout the lower surface <NUM> of the semiconductor substrate <NUM>. The collector electrode <NUM> and the emitter electrode <NUM> may be formed of metallic materials such as aluminum.

The P- type base regions <NUM> are provided on the upper surface <NUM> side of the semiconductor substrate <NUM> of the cross section. In the cross section, on the upper surface <NUM> side of the semiconductor substrate <NUM> in the transistor portion <NUM>, the P+ type contact regions <NUM> and the P- type base regions <NUM> are sequentially provided from the upper surface <NUM> of the semiconductor substrate <NUM>. In the cross section, the P-type base regions <NUM> are provided on the upper surface <NUM> side of the semiconductor substrate <NUM> in the diode portion <NUM>.

In each mesa portion, between the base region <NUM> and the drift region <NUM>, an N+ type accumulation region <NUM> may be provided with a higher doping concentration than the drift region <NUM>. The accumulation region <NUM> may also not be provided in the mesa portion <NUM>. By providing the accumulation region <NUM>, the carrier Injection-Enhancement effect (IE effect) can be improved, and the on-voltage of the transistor portion <NUM> can be reduced.

In the transistor portion <NUM> and the diode portion <NUM>, an N- type drift region <NUM> is provided below the base region <NUM>. In the transistor portion <NUM> and the diode portion <NUM>, an N+ type buffer region <NUM> is provided below the drift region <NUM>.

The doping concentration of the buffer region <NUM> is higher than the doping concentration of the drift region <NUM>. The buffer region <NUM> may function as a field stop layer that prevents the depletion layer expanding from the lower surface of the base region <NUM> from reaching the collector region <NUM> and the cathode region <NUM>.

In the transistor portion <NUM>, a P+ type collector region <NUM> is provided below the buffer region <NUM>. In the diode portion <NUM>, an cathode region <NUM> is provided below the buffer region <NUM>.

On the upper surface <NUM> side of the semiconductor substrate <NUM>, one or more gate trench portions <NUM> and one or more dummy trench portions <NUM> are provided. Each trench portion is provided to reach the drift region <NUM> by penetrating the base region <NUM> from the upper surface <NUM> of the semiconductor substrate <NUM>. In the region where at least any of the emitter region <NUM>, the contact region <NUM> and the accumulation region <NUM> is provided, each trench portion reaches the drift region <NUM> by penetrating these regions. The trench portion penetrating the doping region is not limited to those produced in the order, in which the doping region is formed and then the trench portion is formed. A doping region formed between the trench portions after the formation of the trench portions is also included in the trench portions penetrating the doping region.

The gate trench portion <NUM> has a gate insulating film <NUM> and a gate conductive portion <NUM> provided on the upper surface <NUM> side of the semiconductor substrate <NUM>. The gate insulating film <NUM> is provided to cover the inner wall of the gate trench portion <NUM>. The gate insulating film <NUM> may be formed of oxidizing or nitrifying the semiconductor on the inner wall of the gate trench portion <NUM>. The gate conductive portion <NUM> is provided inside the gate insulating film <NUM> in the interior of the gate trench portion <NUM>. That is, the gate insulating film <NUM> insulates the gate conductive portion <NUM> from the semiconductor substrate <NUM>. The gate conductive portion <NUM> is formed of conductive materials such as polysilicon.

The gate conductive portion <NUM> includes a region opposite the base region <NUM> sandwiching the gate insulating film <NUM>. The gate conductive portion <NUM> is insulated from the emitter electrode <NUM> by the interlayer dielectric film <NUM>. The interlayer dielectric film <NUM> is, for example, a silicate glass, such as PSG or PBSG. At least a part of the interlayer dielectric film <NUM> may be provided in the interior of the gate trench. At least a part of the interlayer dielectric film <NUM> may also be provided above the upper surface <NUM> of the semiconductor substrate <NUM>. When a predetermined voltage is applied to the gate conductive portion <NUM>, a channel with an inverted layer of electrons is formed on the surface layer of the interface in contact with the gate trench of the base region <NUM>.

In the cross section, the dummy trench portions <NUM> may have the same structure as the gate trench portion <NUM>. The dummy trench portions <NUM> has a dummy trench, a dummy insulating film <NUM> and a dummy conductive portion <NUM> provided on the upper surface <NUM> side of the semiconductor substrate <NUM>. The dummy insulating film <NUM> is provided to cover the inner wall of the dummy trench. The dummy conductive portion <NUM> is provided in the interior of the dummy trench, and is provided inside the dummy insulating film <NUM>. The dummy insulating film <NUM> insulates the dummy conductive portion <NUM> from the semiconductor substrate <NUM>. The dummy conductive portion <NUM> may be formed of the same materials as the gate conductive portion <NUM>. In the cross section, the dummy conductive portion <NUM> may be insulated from the emitter electrode <NUM> by the interlayer dielectric film <NUM>. In a cross section different from that in <FIG>, the dummy conductive portion <NUM> may be connected to the emitter electrode <NUM> by the contact holes provided on the interlayer dielectric film <NUM> and so on. At least a part of the interlayer dielectric film <NUM> may be provided in the interior of the dummy trench. At least a part of the interlayer dielectric film <NUM> may also be provided above the upper surface <NUM> of the semiconductor substrate <NUM>.

According to the present invention, in at least one mesa portion, the trench contact <NUM> of a conductive material is provided. The trench contact <NUM> may be formed of the same material as emitter electrode <NUM>, or may be formed of materials such as tungsten. By forming the trench contact <NUM> by materials including tungsten, a fine trench contact <NUM> can be easily formed. The trench contact <NUM> is connected to the emitter electrode <NUM>.

The trench contact <NUM> is provided to penetrate the contact region <NUM>. That is, the trench contact <NUM> is provided from the upper surface <NUM> of the semiconductor substrate <NUM>, to the position reaching the base region <NUM>. The lower end of the trench contact <NUM> may be in the same position as the lower end of the base region <NUM>, may also be arranged lower than the lower end of the base region <NUM>. The trench contact <NUM> may penetrate the emitter regions <NUM> in the cross section different from <FIG>.

As described above, since the trench contact <NUM> penetrates the contact regions <NUM>, the contact region <NUM> becomes small. Therefore, the hole injection from the contact regions <NUM> to the drift region <NUM> side can be suppressed.

According to the invention, in the region in contact with the bottom portion of the trench contact <NUM>, a P++ type high-concentration plug region <NUM> with a higher doping concentration than the contact region <NUM> is provided. The high-concentration plug region <NUM> may cover the entire of the bottom surface of the trench contact <NUM>. The doping concentration of the high-concentration plug region <NUM> may be twice or more of the doping concentration of the contact region <NUM>, may be five times or more, or may be ten times or more. By providing the high-concentration plug region <NUM>, the contact resistance between the trench contact <NUM> and the semiconductor substrate <NUM> can be reduced. Also, the extraction of a hole from the semiconductor substrate <NUM> becomes easy by the high-concentration plug region <NUM> and the trench contact <NUM>. Therefore, the reverse recovery loss can be further reduced. The thickness of the high-concentration plug region <NUM> in the depth direction is preferably less than the thickness in the depth direction of the contact regions <NUM>.

The transistor portion <NUM> may have a boundary portion <NUM> in contact with the diode portion <NUM>. The boundary portion <NUM> includes one or more mesa portions <NUM>. The mesa portion <NUM> of the boundary portion <NUM> may have the same configuration as the mesa portion <NUM> outside the boundary portion <NUM>.

The trench contact <NUM> and the high-concentration plug region <NUM> may be provided in the mesa portion <NUM> of the boundary portion <NUM>. In this way, the holes flowing from the contact region <NUM> of the boundary portion <NUM> to the diode portion <NUM> can be reduced. The trench contact <NUM> and the high-concentration plug region <NUM> may be provided only in the boundary portion <NUM>, may also be provided outside the boundary portion <NUM>.

The trench contact <NUM> and the high-concentration plug region <NUM> may also be provided in the mesa portion <NUM> outside the boundary portion <NUM>. The trench contacts <NUM> and the high-concentration plug regions <NUM> may be provided in all of the mesa portions <NUM> of the transistor portion <NUM>. The trench contacts <NUM> and the high-concentration plug regions <NUM> may also be provided in all of the mesa portions <NUM> having the contact regions <NUM> and the emitter regions <NUM>. In this way, the holes flowing from the entire transistor portion <NUM> to the diode portion <NUM> can be reduced.

The trench contact <NUM> and the high-concentration plug region <NUM> may also be provided in the diode portion <NUM>. The trench contacts <NUM> and the high-concentration plug regions <NUM> may also be provided in all of the mesa portions <NUM> of the diode portion <NUM>. The trench contact <NUM> provided in the mesa portion <NUM> may be formed with the same depth as the trench contact <NUM> provided in the mesa portion <NUM>, or may be formed with a different depth. In the mesa portion <NUM>, the trench contact <NUM> may also penetrate the contact region <NUM>.

<FIG> illustrates a perspective cross-sectional view showing the exemplary structure of the mesa portion <NUM>. In <FIG>, of the trench contacts <NUM>, the contact trench <NUM> is shown, and the conductive material filled in the contact trench <NUM> is omitted.

In this example, the contact region <NUM> is provided in a position deeper than the emitter region <NUM>. As shown in <FIG>, and according to the present invention, the contact trench <NUM> is provided to penetrate the contact regions <NUM> and the emitter regions <NUM>. When the emitter region <NUM> is provided in a position deeper than the contact region <NUM>, the contact trench <NUM> may be provided to a position deeper than the lower end of the emitter regions <NUM>, or may be provided to a position shallower than the lower end of the emitter regions <NUM>.

In the bottom portion of the contact trench <NUM>, a P++ type high-concentration plug region <NUM> is provided. The contact regions <NUM>, the emitter regions <NUM> and the base region <NUM> are exposed from the sides of the contact trench <NUM>. The high-concentration plug region <NUM> may be exposed from the bottom surface of the contact trench <NUM>. The trench contact <NUM> may contact the contact regions <NUM>, the emitter regions <NUM>, the base region <NUM> and the high-concentration plug region <NUM>.

<FIG> illustrates a cross sectional view showing an exemplary structure of the mesa portion <NUM>. In this example, in the depth direction of the semiconductor substrate <NUM>, the thickness of the high-concentration plug region <NUM> is referred to as T1, the thickness of the contact region <NUM> is referred to as T2, the protruding length of the contact trench <NUM> protruding below the lower end of the contact region <NUM> is referred to as T3, and the thickness of the base region <NUM> below the high-concentration plug region <NUM> is referred to as T4. The thickness or length of each member may use the maximum value of the thickness or length of each member.

In this example, the thickness T1 of the high-concentration plug region <NUM> may be less than the thickness T2 of the contact region <NUM>. The thickness T1 may be a half or less, may be <NUM>/<NUM> or less, or may be <NUM>/<NUM> or less of the thickness T2. In this way, the injection of the holes from the high-concentration plug region <NUM> can be suppressed. The product of the thickness T1 of the high-concentration plug region <NUM> and the doping concentration may be less than the product of the thickness T2 of the contact regions <NUM> and the doping concentration.

It is noted that the lower end of the high-concentration plug region <NUM> is provided above the lower end of the base region <NUM>. That is, the high-concentration plug region <NUM> is arranged inside the base region <NUM>, and not in contact with the accumulation region <NUM> or the drift region <NUM>. In this way, the trench contact <NUM> can be prevented from connecting to N type regions via the high-concentration plug region <NUM>.

The protruding length T3 of the contact trench <NUM> is less than the thickness T4 of the base region <NUM>. When the protruding length T3 becomes large, the distance between the high-concentration plug region <NUM> and the drift region <NUM> (or the accumulation region <NUM>) becomes less, and the breakdown voltage decreases. The protruding length T3 may be a half or less, may also be <NUM>/<NUM> or less of the thickness T4.

Also, when the thickness T1 of the high-concentration plug region <NUM> becomes large, the distance between the high-concentration plug region <NUM> and the drift region <NUM> (or the accumulation region <NUM>) becomes less, and the breakdown voltage decreases. The thickness T1 may be a half or less, may be <NUM>/<NUM> or less, or may be <NUM>/<NUM> or less of the thickness T4.

Also, the width in the X axis direction of the contact trench <NUM> (that is, the width of the trench contact <NUM>) is referred to as W1, and the distance in the X axis direction between the gate trench portion <NUM> and the contact trench <NUM> is referred to as W2. That is, the width W2 is the width of the contact regions <NUM>. The width W1 may be a half or more, or may be once or more of the width W2. By enlarging the width W1, the hole injection from the contact regions <NUM> can be suppressed.

The high-concentration plug region <NUM> may be formed by implanting P type impurities from the upper of the upper surface <NUM> of the semiconductor substrate <NUM> toward the contact trench <NUM>. In this case, the P type impurities are also implanted into the regions exposed from the sides of the contact trench <NUM> of the contact regions <NUM> and the emitter regions <NUM>. In the contact regions <NUM>, the impurity concentration of the boundary portion <NUM> in contact with the contact trench <NUM> may be higher than the impurity concentration of the region in contact with the gate trench portion <NUM>. With such a configuration, the contact resistance between the trench contact <NUM> and the contact regions <NUM> can be further reduced. Also, in the emitter regions <NUM>, the P type impurity concentration of the region in contact with the contact trench <NUM> may be higher than the P type impurity concentration of the region in contact with the gate trench portion <NUM>. The region of the emitter regions <NUM> in contact with the contact trench <NUM> may also be inverted to P type.

It is noted that the width W2 is preferably to have a thickness to an extent that the P type impurities implanted from the contact trench <NUM> to the emitter region <NUM> does not reach the gate trench portion <NUM>. The width W2 may be <NUM> or more, and may be <NUM> or more.

The step for forming the high-concentration plug region <NUM> is preferably a step after the steps for forming the emitter regions <NUM>, the base region <NUM>, the accumulation region <NUM>, the contact regions <NUM> and each trench portion. In this way, the thermal history with respect to the high-concentration plug region <NUM> and the boundary portion <NUM> can be reduced. Accordingly, the thickness T1 of the high-concentration plug region <NUM> can be small, and the P type impurities implanted to the boundary portion <NUM> can be inhibited from reaching the gate trench portion <NUM>.

<FIG> illustrates a perspective cross-sectional view showing an exemplary structure of the mesa portion <NUM>. In <FIG>, of the trench contact <NUM>, the contact trench <NUM> is shown, and the conductive material filled in the contact trench <NUM> is omitted.

As shown in <FIG>, the contact trench <NUM> is provided from the upper surface <NUM> of the semiconductor substrate <NUM> to the interior of the base region <NUM>. The contact trench <NUM> may penetrate the contact regions <NUM>. A P++ type high-concentration plug region <NUM> is provided in the bottom portion of the contact trench <NUM>. The contact regions <NUM> and the base region <NUM> may be exposed from the sides of the contact trench <NUM>. The high-concentration plug region <NUM> may be exposed from the bottom surface of the contact trench <NUM>. The trench contact <NUM> may contact the contact regions <NUM>, the base region <NUM> and the high-concentration plug region <NUM>.

<FIG> illustrates a perspective cross-sectional view showing another exemplary structure of the mesa portion <NUM>. The mesa portion <NUM> of this example on the upper surface <NUM> of the semiconductor substrate <NUM> has the same structure with the mesa portion <NUM>. That is, in the mesa portion <NUM> of this example, the contact regions <NUM> and the emitter regions <NUM> are alternately arranged along the Y axis direction. Also in this case, the contact trench <NUM> may be provided to penetrate the contact regions <NUM> and the emitter regions <NUM> from the upper surface <NUM> of the semiconductor substrate <NUM> to the base region <NUM>.

<FIG> illustrates a cross sectional view showing an exemplary structure of the end of the active portion <NUM> in the X axis direction. The cross section in <FIG> is a XZ cross section. The active portion <NUM> of this example is enclosed by the well region <NUM> in a top view. An outer circumferential gate runner <NUM> is provided above the well region <NUM>, but is omitted in <FIG>.

The active portion <NUM> of this example has an end region <NUM> between the transistor portion <NUM> arranged at the most end in the X axis direction (or the diode portion <NUM>) and the well region <NUM>. In the end region <NUM>, the gate trench portion <NUM> and the dummy trench portion <NUM> are not arranged. In the end region <NUM>, the base region <NUM> may be exposed from the upper surface <NUM> of the semiconductor substrate <NUM>.

In the end region <NUM>, one or more pairs of the trench contacts <NUM> and the high-concentration plug regions <NUM> may be provided. In the end region <NUM> of this example, a plurality of pairs of trench contacts <NUM> and high-concentration plug regions <NUM> are arranged with even intervals along the X axis direction and the like. The trench contact <NUM> and the high-concentration plug region <NUM> in the end region <NUM> may have the same structures as the trench contact <NUM> and the high-concentration plug region <NUM> in the transistor portion <NUM>. By providing the end region <NUM>, the carrier of the hole and the like flowing from the regions outside the active portion <NUM> to the active portion <NUM> can be extracted. In this way, the concentration of the carriers in the mesa portion arranged at the end of the active portion <NUM> can be suppressed.

<FIG> illustrates an XZ cross-sectional view showing one example of the mesa portion <NUM> included by the semiconductor device <NUM>. The mesa portion <NUM> may be provided in the transistor portion <NUM> or the diode portion <NUM>. The mesa portion <NUM> is a floating mesa that is electrically insulated from the emitter electrode <NUM> by the interlayer dielectric film <NUM>. By providing the mesa portion <NUM>, the carrier can be inhibited from being extracted by the emitter electrode <NUM>, and the IE effect can be further improved. The trench contact <NUM> is not provided in the mesa portion <NUM>.

<FIG> illustrates a figure describing a part of steps of the production method of the semiconductor device <NUM>. In <FIG>, the step for forming the trench contact is shown. In <FIG>, the accumulation region <NUM> is omitted. Before forming the trench contact, the contact regions <NUM>, the emitter regions <NUM>, the base region <NUM>, the gate trench portion <NUM> and the dummy trench portion <NUM> are formed in the semiconductor substrate <NUM>. In this example, the upper end of the gate conductive portion <NUM> of the gate trench portion <NUM> and the upper end of the dummy conductive portion <NUM> of the dummy trench portion <NUM> are arranged lower than the upper surface <NUM> of the semiconductor substrate <NUM>.

In S1000, an interlayer dielectric film <NUM> is formed on the upper of the conductive portion of each trench portion and the upper surface <NUM> of the semiconductor substrate <NUM>. As mentioned above, since the conductive portion of each trench portion is arranged lower than the upper surface <NUM> of the semiconductor substrate <NUM>, a part of the interlayer dielectric film <NUM> is also formed above the conductive portion inside each trench portion.

In S1002, the interlayer dielectric film <NUM> above the upper surface <NUM> of the semiconductor substrate <NUM> is removed by etching back. In this way, the interlayer dielectric film <NUM> in the interior of each trench portion remains, and the upper surfaces of the mesa portion <NUM> and the mesa portion <NUM> are exposed.

In S1004, a mask pattern <NUM> is formed on the upper surface <NUM> of the semiconductor substrate <NUM>, and a contact trench <NUM> is formed by etching the upper surface <NUM> of the semiconductor substrate <NUM>. The contact trench <NUM> penetrates the contact regions <NUM>.

In S1006, the high-concentration plug region <NUM> is formed in contact with the bottom portion of the contact trench <NUM>. The high-concentration plug region <NUM> may be formed by implanting P type impurities that are the same as the contact regions <NUM>. Also, in S1006, the acceleration energy of the impurity ions may be less than the acceleration energy when the impurity ions are implanted into the contact regions <NUM>. Also, in S1006, the heat treatment temperature may be lower than the heat treatment temperature when the contact regions <NUM> are formed. Also, in S1006, the heat treatment time may be shorter than the heat treatment time when the contact regions <NUM> are formed. Also, in S1006, the heat treatment may also be not performed.

As one example, the P type impurity is boron. As one example, when the contact regions <NUM> are formed, the accelerating voltage of the impurity ion may be from 100keV to 140keV. The implantation amount of the impurity ion may be from <NUM>×<NUM><NUM>(/cm<NUM>) to <NUM>×<NUM><NUM>(/cm<NUM>). The heat treatment temperature may be from <NUM> to <NUM>. The heat treatment time may be from <NUM> minutes to <NUM> minutes.

As one example, when the high-concentration plug region <NUM> is formed, the accelerating voltage of the impurity ion may be from 20keV to 80keV The implantation amount of the impurity ion may be from <NUM>×<NUM><NUM>(/cm<NUM>) to <NUM>×<NUM><NUM>(/cm<NUM>). The implantation amount of the impurity ion when the high-concentration plug region <NUM> is formed may be less than the implantation amount of the impurity ion when the contact regions <NUM> are formed. However, since the thickness of the high-concentration plug region <NUM> is small, the doping concentration per unit volume becomes high. The heat treatment temperature may be from <NUM> to <NUM>. The heat treatment time for forming the high-concentration plug region <NUM> may be a period of <NUM>/<NUM> or less of the heat treatment time for forming the contact regions <NUM>. The heat treatment time for forming the high-concentration plug region <NUM> may be from <NUM> seconds to <NUM> minute.

In S1008, the conductive material is formed in the interior of the contact trench <NUM>. In this example, the conductive material <NUM> is also formed above the mask pattern <NUM>. The conductive material formed in the interior of the contact trench <NUM> becomes the trench contact <NUM>.

In S1010, the mask pattern <NUM> is removed. In this way, the trench contact <NUM> can be formed. After the formation of the trench contact <NUM>, the emitter electrode <NUM> is formed on the upper surface <NUM> of the semiconductor substrate <NUM>. When the trench contact <NUM> is formed of the same material as the emitter electrode <NUM>, in S1008, the conductive material may be deposited after the mask pattern <NUM> being removed.

It is noted that after the formation of the high-concentration plug region <NUM>, it is preferable that there is no process with higher temperature than the heat treatment temperature when the high-concentration plug region <NUM> has been formed. In this way, the thickness of the high-concentration plug region <NUM> can be controlled with high accuracy.

<FIG> illustrates another example of the b-b cross section in <FIG> and <FIG>. In the semiconductor device <NUM> of this example, the structure of the interlayer dielectric film <NUM> is different from the example shown in <FIG>. The other structures are the same as the example shown in <FIG>.

In this example, the interlayer dielectric film <NUM> is provided above the upper surface <NUM> of the semiconductor substrate <NUM>. The interlayer dielectric film <NUM> is provided to cover each trench portion. That is, the width in the X axis direction of the interlayer dielectric film <NUM> is greater than the width of the trench portion. The interlayer dielectric film <NUM> may be or may not be provided in the interior of each trench portion.

Each of the mesa portions <NUM> and the mesa portions <NUM> has a part that is not covered by the interlayer dielectric film <NUM>. In the interlayer dielectric film <NUM>, contact holes <NUM> may be provided to expose the mesa portions <NUM> and the mesa portions <NUM>. The contact hole <NUM> may be provided to have a longitudinal length in the longitudinal direction (the Y axis direction) of each mesa portion <NUM>.

The trench contacts <NUM> of this example is provided on the upper surfaces of the mesa portion <NUM> and the mesa portion <NUM> that are exposed by the contact holes <NUM>. The trench contact <NUM> may be formed by etching the upper surface of the semiconductor substrate <NUM> using the interlayer dielectric film <NUM> provided with the contact holes <NUM> as the mask. In this case, on the upper surface <NUM> of the semiconductor substrate <NUM>, the position of the opening part of the contact hole <NUM> matches the position of the trench contact <NUM>. In another example, the position of the opening part of the contact hole <NUM> may be different from the position of the trench contact <NUM>.

<FIG> illustrates a figure comparing characteristics of the semiconductor device <NUM> according to an implementation example and a semiconductor device according to a comparative example. In <FIG>, the waveforms of the forward current If in the diode portion <NUM> when the transistor portion <NUM> is turned off and the anode-cathode voltage Vr of the diode portion <NUM> are shown. The structure of the semiconductor device of the comparative example are the same as the semiconductor device <NUM>, excepting for the point of being without the trench contact <NUM>.

As shown in <FIG>, the peak current Irp during reverse recovery of the semiconductor device <NUM> according to the implementation example becomes smaller than the peak current in the comparative example when compared with the comparative example. Therefore, the semiconductor device <NUM> can have the reverse recovery loss reduced. This is considered to be due to the injection of carriers from the contact regions <NUM> being suppressed by providing the trench contact <NUM>.

<FIG> illustrates the hole density distribution examples in a depth direction in the diode portions <NUM> of the implementation example and the comparative example. In <FIG>, of the diode portion <NUM>, the hole density of the region adjacent to the transistor portion <NUM> is shown. As shown in <FIG>, it can be seen that, by providing the trench contact <NUM>, the hole density of the implementation example particularly on the upper surface (anode) side is decreased.

The invention is solely defined by the subject-matter of the claims. While the embodiments of the present invention have been described, the technical scope of the invention is not limited to the above described embodiments. It is apparent to persons skilled in the art that various alterations or improvements can be added to the above-described embodiments. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the invention, as long as the resulting device and/or method falls within the scope of the claims.

Claim 1:
A semiconductor device (<NUM>), which comprises an insulated gate bipolar transistor and incorporates a freewheeling diode in antiparallel connection, comprising:
a semiconductor substrate (<NUM>), and
an emitter electrode (<NUM>) provided above an upper surface (<NUM>) of the semiconductor substrate (<NUM>), wherein
the semiconductor substrate (<NUM>) has:
a first conductive type drift region (<NUM>),
a second conductive type base region (<NUM>) provided between the drift region (<NUM>) and the upper surface (<NUM>) of the semiconductor substrate (<NUM>),
a first conductive type emitter region (<NUM>) provided between the base region (<NUM>) and the upper surface (<NUM>) of the semiconductor substrate (<NUM>), wherein the first conductive type emitter region (<NUM>) has a higher doping concentration than the drift region (<NUM>),
a second conductive type contact region (<NUM>) with a higher doping concentration than the base region (<NUM>), which is provided between the base region (<NUM>) and the upper surface (<NUM>) of the semiconductor substrate (<NUM>),
a trench contact (<NUM>) of a conductive material provided to connect to the emitter electrode (<NUM>), and
a second conductive type high-concentration plug region (<NUM>) with a higher doping concentration than the contact region (<NUM>), wherein the second conductive type high-concentration plug region (<NUM>) is provided in contact with a bottom portion of the trench contact (<NUM>), wherein
the trench contact (<NUM>) is provided to penetrate the contact region (<NUM>) and the emitter region (<NUM>) from the upper surface (<NUM>) of the semiconductor substrate (<NUM>), and to penetrate and directly contact part of the base region (<NUM>), wherein
in a depth direction of the semiconductor substrate (<NUM>), a thickness of the high-concentration plug region (<NUM>) is less than a thickness of the contact region (<NUM>) and a lower end of the high-concentration plug region (<NUM>) is arranged above a lower end of the base region (<NUM>) so that the high-concentration plug region (<NUM>) is only in contact with the base region (<NUM>) and not in contact with the contact region (<NUM>) and with the emitter region (<NUM>).