Patent Description:
Memory systems are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory.

Volatile memory requires power to maintain its data, and includes random-access memory (RAM), dynamic random-access memory (DRAM), or synchronous dynamic random-access memory (SDRAM), among others.

Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory, such as phase-change random-access memory (PCRAM), resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), or 3D XPoint™ memory, among others.

Flash memory is utilized as non-volatile memory for a wide range of electronic applications. Flash memory systems typically include one or more groups of one-transistor, floating gate or charge trap memory cells that allow for high memory densities, high reliability, and low power consumption.

Two common types of flash memory array architectures include NAND and NOR architectures, named after the logic form in which the basic memory cell configuration of each is arranged. The memory cells of the memory array are typically arranged in a matrix. In an example, the gates of each floating gate memory cell in a row of the array are coupled to an access line (e.g., a word line). In a NOR architecture, the drains of each memory cell in a column of the array are coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in series, source to drain, between a source line and a bit line.

Both NOR and NAND architecture semiconductor memory arrays are accessed through decoders that activate specific memory cells by selecting the word line coupled to their gates. In a NOR architecture semiconductor memory array, once activated, the selected memory cells place their data values on bit lines, causing different currents to flow depending on the state at which a particular cell is programmed. In a NAND architecture semiconductor memory array, a high bias voltage is applied to a drain-side select gate (SGD) line. Word lines coupled to the gates of the unselected memory cells of each group are driven at a specified pass voltage (e.g., Vpass) to operate the unselected memory cells of each group as pass transistors (e.g., to pass current in a manner that is unrestricted by their stored data values). Current then flows from the source line to the bit line through each series coupled group, restricted only by the selected memory cells of each group, placing current encoded data values of selected memory cells on the bit lines.

Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or a number of programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., <NUM> or <NUM>), representing one bit of data. However, flash memory cells can also represent one of more than two programmed states, allowing the manufacture of higher density memories without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit). Such cells can be referred to as multi-state memory cells, multi-digit cells, or multilevel cells (MLCs). In certain examples, MLC can refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), a triple-level cell (TLC) can refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and a quad-level cell (QLC) can store four bits of data per cell. MLC is used herein in its broader context, to can refer to any memory cell that can store more than one bit of data per cell (i.e., that can represent more than two programmed states).

Some memory arrays are two-dimensional (2D) structures arranged on a surface of a semiconductor substrate. To increase memory capacity for a given area, and to decrease cost, the size of the individual memory cells has decreased. However, there is a technological limit to the reduction in size of the individual memory cells, and thus, to the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as 3D NAND architecture semiconductor memory systems, are being developed to further increase memory density and lower memory cost.

Memory arrays or systems can be combined together to form a storage volume of a memory system, such as a solid-state drive (SSD), a Universal Flash Storage (UFS ™) device, a MultiMediaCard (MMC) solid-state storage device, an embedded MMC device (eMMC™), etc. An SSD can be used as, among other things, the main storage device of a computer, having advantages over traditional hard drives with moving parts with respect to, for example, performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, SSDs can have reduced seek time, latency, or other delay associated with magnetic disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells, such as flash memory cells to obviate internal battery supply requirements, thus allowing the drive to be more versatile and compact.

An SSD can include a number of memory devices, including a number of dies or logical units (e.g., logical unit numbers or LUNs), and can include one or more processors or other controllers performing logic functions required to operate the memory devices or interface with external systems. Such SSDs may include one or more flash memory die, including a number of memory arrays and peripheral circuitry thereon. The flash memory arrays can include a number of blocks of memory cells organized into a number of physical pages. In many examples, the SSDs will also include DRAM or SRAM (or other forms of memory die or other memory structures). The SSD can receive commands from a host in association with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, or erase operations to erase data from the memory devices.

United States patent application <CIT> describes memory devices and systems with command and control access. In one embodiment, a memory device includes a controller having a processor and a memory component operably coupled to the processor. The controller is configured to receive at least one command and control (C2) packet from a remote computer associated with a device vendor. The C2 packet includes a request for the controller to perform a restricted command, and a vendor signature. The memory component stores instructions executable by the processor to determine if the vendor signature is valid and to direct the controller to perform the restricted command if the vendor signature is determined to be valid.

United States patent application <CIT> describes a data storage client which may establish a virtual replay protected storage system with an agnostic data storage. The virtual replay protected storage system may maintain a trusted counter and a secret key in a trusted client environment. The virtual replay protected storage system may encode a hash message authentication code signature based on the trusted counter, the secret key, and a data set. The virtual replay protected storage system may send a write request of the data set with the hash message authentication code signature to an agnostic data storage.

United States patent application <CIT> describes an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) protected against user attacks-e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks. Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.

<NPL>et al. is a textbook describing smart card technology.

Aspects of the present disclosure are directed to secure memory system programming. During the production of memory systems and/or of host systems that utilize a memory system, it is often desirable to configure the memory system. A programming appliance can provide commands to the memory system that instruct the memory system to perform various operations and/or assume various configurations.

Some memory systems include security features that prevent the memory system from executing a command unless the command is accompanied by a valid digital signature. The memory system verifies the command by checking the validity of the digital signature. Memory system commands that are verified with a digital signature are referred to herein as signed commands. In some memory systems, all commands are signed commands. In other memory systems, less than all commands are signed commands. For example, commands that affect security features, device provisioning, and/or other sensitive areas of operation can be signed while routine commands, such as read or write requests, can be unsigned.

The digital signature accompanying a signed command can be created (and verified) using multiple input data elements including a cryptographic key and a memory system counter value. The digital signature can be created by a programming appliance or other suitable signing device, such as a hardware security module (HSM). The digital signature can be generated using a symmetric key arrangement or an asymmetric key arrangement. In a symmetric key arrangement, both the signing device that generates a digital signature and the memory system that verifies the digital signature use the same cryptographic key, which may be a server root key for the memory system. In an asymmetric key arrangement, the signing device utilizes a private key that may not be known to the memory system. The memory system utilizes a public key corresponding to the signing device's private key.

The digital signature can also be based on a counter value of a memory system counter. The signing device generating the digital signature can query the memory system to receive a current value of the memory system counter. The signing device generates the digital signature by executing a cryptographic function, such as a hash function, using a cryptographic key, the command, and the current memory system counter value. In a symmetric key arrangement, the signing device uses a secret cryptographic key that is known to the signing device and the memory device. In an asymmetric key arrangement, the signing device uses a private cryptographic key that is known to the signing device but may not be known to the memory system. A command message including the command and the digital signature is sent to the memory system.

The memory system verifies the digital signature by computing a cryptographic digest of the command from the command message, the current value of the memory system counter and a memory system cryptographic key. A cryptographic digest is the output of a hash function or other suitable cryptographic function that is executed at the memory system utilizing the command, the current value of the memory system counter, and the memory system cryptographic key.

In a symmetric key arrangement, the memory system cryptographic key is a copy of the cryptographic key used by the signing device. In an asymmetric key arrangement, the memory system cryptographic key is a public key of the signing device. If the cryptographic digest is equivalent to the digital signature included with the command message, then the digital signature is verified and the memory system executes the command. If the cryptographic digest is not equivalent to the digital signature included with the command message, then the digital signature is not verified and the memory system does not execute the command.

As described, a device, such as a programming appliance, can instruct a memory system to execute a signed command if the device and the memory system have a complimentary set of cryptographic keys, e.g., the device and memory system have the same symmetric key or the device has a private key and the memory system has the corresponding public key.

In some examples, however, providing the programming appliance with a copy of either a symmetric key known to the memory system or a private key associated with a public key known to the memory system can create challenges. For example, an unauthorized actor who steals the cryptographic key from the programming appliance (e.g., symmetric key or private key) can later compromise the memory system by generating signed commands with valid digital signatures. This challenge is multiplied in environments where a single programming appliance programs multiple memory systems, for example, at multiple host devices. In that case, the programming appliance manages multiple cryptographic keys for the multiple memory systems.

The programming appliance can be implemented with security features to limit unauthorized access to cryptographic keys. For example, the programming appliance may be or include a hardware security module (HSM) that limits physical and network access to the cryptographic keys that it stores. Increasing the security of the programming appliance, however, still generates challenges. For example, programming appliances with HSMs or other suitable security features can be costly to purchase, operate, and maintain. This can limit the feasibility of implementing programming appliances at distributed locations. Also, even if suitable security is used, providing the cryptographic keys to multiple programming appliances increases the number of people and facilities that should be trustworthy to avoid security breaches.

Various examples described herein address these and other challenges by providing secure memory system programming, for example, utilizing a command file including one or more pre-generated digital signatures. The pre-generated digital signatures can be used by the programming appliance to program one or more memory systems. In this way, the programming appliance may not need to receive a cryptographic key in order to program the memory system. Instead, the programming appliance uses the pre-generated digital signatures from the command file to send command messages to the memory system.

A pre-generated digital signature is generated by an HSM or other suitable generator device. The pre-generated digital signature corresponds to a particular memory system, a signed command, and a selected value of the memory system counter. The selected value of the memory system counter can be a value that the memory system counter is expected to have when the pre-generated digital signature is used. For example, as described herein, the selected value of the memory system counter can be a known initial value of the memory system counter, a predetermined number of increments greater than the known initial value, and/or a value to which the programming appliance is able to increment the memory system counter. The signed command is the command that can be executed using the pre-generated signal. The generator device creates the pre-generated digital signature by executing a cryptographic operation using the signed command, the selected memory system counter value, and the cryptographic key associated with the particular memory system (e.g., a symmetric key or private key).

The programming appliance receives the command file and uses the pre-generated digital signature to create a command message. The command message includes the signed command and the pre-generated digital signature. The memory system verifies the pre-generated digital signature using its memory system cryptographic key (e.g., a public key or symmetric key) and the signed command from the command message.

In some examples, the programming appliance determines that the current memory system counter value matches the selected memory system counter of the pre-generated digital signature, for example, by querying the memory system or incrementing the memory system counter, as described herein.

The command file, in some examples, includes more than one pre-generated digital signature. For example, the command file can include multiple pre-generated digital signatures for multiple memory systems at the same host device or at different host devices.

In some examples, the command file includes one or more sequences of pre-generated digital signatures for a particular memory system. The sequence of pre-generated digital signatures corresponds to a sequence of commands to be executed at the memory system. Successive pre-generated digital signatures can correspond to successive commands in the sequence of commands. Also, successive pre-generated digital signatures can correspond to increasing memory system counter values. In this way, the programming appliance can send command messages using the successive pre-generated digital signatures to execute the sequence of commands at the memory device.

In some examples, the command file includes multiple pre-generated signatures for the same memory system and signed command, but associated with different memory system counter values. The programming appliance can query the memory system to determine its current value and select the pre-generated digital signature associated with a memory system counter value that is equal to the current memory system counter value.

In some examples, the programming appliance is configured to increment the memory system counter until its current value is equal to the memory system counter value associated with a pre-generated digital signature. The programming appliance queries the memory system to receive the current value of the memory system counter. The programming appliance then increments the memory system counter until its value matches the memory system counter value associated with the pre-selected digital signature.

<FIG> illustrates an example of an environment <NUM> including a host device <NUM>, memory systems 110A, 110B, 110N, and a programming appliance <NUM> that includes a command file <NUM>. The host device <NUM> is in communication with one or more memory systems 110A, 110B, 110N via a communication interface <NUM>. The host device <NUM> and/or the memory systems 110A, 110B, 110N may be included in a variety of products, such as Internet of Things (IoT) devices (e.g., a refrigerator or other appliance, sensor, motor or actuator, mobile communication device, automobile, drone, etc.), network appliances (e.g., routers, switches, etc.), or any other suitable products to support processing, communications, or control of the product. In some examples, the host device <NUM> and memory systems 110A, 110B, 110N are included in a common board or package.

In the example environment <NUM> of <FIG>, the host device <NUM> includes a host controller <NUM>. The host controller <NUM> can include a processor, an application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other suitable component or components that may, among other functions, manage the memory devices 110A, 110B, 110N. One or more communication interfaces <NUM> can be used to transfer data between the memory systems 110A, 110B, 110N and one or more other components of the host device <NUM>, such as the host controller <NUM>. Examples of such communication interfaces include Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Express (PCle) interfaces, Universal Serial Bus (USB) interfaces, Universal Flash Storage (UFS) interfaces, eMMC™ interfaces, or one or more other connectors or interfaces. The host device <NUM> can include a host system, an electronic device, a processor, a memory card reader, or one or more other electronic devices external to the memory systems 110A, 110B, 110N. Although three memory systems 110A, 110B, 110N are shown as part of the host system <NUM>, in other examples, more or fewer memory systems can be included. In some examples, the host device <NUM> may be a machine having some portion, or all, of the components discussed with reference to the machine <NUM> of <FIG>. Also, additional examples of host devices <NUM> are discussed with reference to <FIG>.

The example of <FIG> includes various additional features of the memory system 110A. The other memory systems 110B, 110N may include the same features, or different features. In <FIG>, the memory system 110A includes a memory controller <NUM> and a memory array <NUM>. The memory array <NUM> includes a number of individual memory die (e.g., a stack of two-dimensional or three-dimensional (3D) NAND die, a stack of NOR die, etc.). In an example, the memory systems 110A, 110B, 110N can be discrete memory or storage device components of the host device <NUM>. In other examples, the memory systems 110A, 110B, 110N can be a portion of an integrated circuit (e.g., system on a chip (SOC), etc.), stacked or otherwise included with one or more other components of the host device <NUM>.

The memory controller <NUM> can receive instructions from the host device <NUM>, and can communicate with the memory array <NUM>, such as to transfer data to (e.g., write or erase) or from (e.g., read) one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array <NUM>. The memory controller <NUM> can include, among other things, circuitry or firmware, including one or more components or integrated circuits. For example, the memory controller <NUM> can include one or more memory control units, circuits, or components configured to control access across the memory array <NUM> and to provide a translation layer between the host device <NUM> and the memory system 110A. The memory controller <NUM> can include one or more input/output (I/O) circuits, lines, or interfaces to transfer data to or from the memory array <NUM>.

The memory controller <NUM> can include, among other things, circuitry or firmware, such as a number of components or integrated circuits associated with various memory management functions. Management functions for NAND storage units can include wear leveling (e.g., garbage collection or reclamation), error detection or correction, block retirement, or one or more other memory management functions.

The memory controller <NUM> may parse or format commands received from the host <NUM> into host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands (e.g., to accomplish various memory management functions) for the memory controller <NUM> or one or more other components of the memory system 110A.

For example, when the host controller <NUM> receives a command message from the programming appliance <NUM>, as described herein, the host controller <NUM> sends the command message to the memory controller <NUM> of the appropriate memory system 110A. The memory controller <NUM> can verify a digital signature included with the command message and, if the digital signature is verified, execute the command. For unsigned commands, the memory controller <NUM> can execute the command without first verifying a digital signature.

The memory controller <NUM> can manage a set of management tables configured to maintain various information associated with one or more components of the memory system 110A (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller <NUM>). For example, for a NAND memory system, the management tables can include information regarding block age, block erase count, error history, or one or more error counts (e.g., a write operation error count, a read bit error count, a read operation error count, an erase error count, etc.) for one or more blocks of memory cells coupled to the memory controller <NUM>. In certain examples, if the number of detected errors for one or more of the error counts is above a threshold, the bit error can be referred to as an uncorrectable bit error. The memory controller <NUM> can maintain at the management tables a count of correctable or uncorrectable bit errors, among other things.

Management tables can also include one or more logical-to-physical (L2P) tables including L2P pointers relating logical addresses to physical addresses at the memory array <NUM>. The management tables may be stored at a RAM of the memory controller <NUM>. In some examples, some or all of the management tables are stored at the memory array <NUM>. For example, the memory controller <NUM> may read the management tables from the memory array <NUM> and/or cache some or all of the management tables at RAM of the memory controller <NUM>.

The memory controller <NUM> can also include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory system 110A coupled to the memory controller <NUM>. The memory operations can be based on, for example, host commands received from the host device <NUM> (e.g., the host controller <NUM> thereof), or internally generated by the memory controller <NUM> (e.g., in association with wear leveling, error detection or correction, etc.).

The memory controller <NUM> can include an error correction code (ECC) component <NUM>, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory system 110A coupled to the memory controller <NUM>. The memory controller <NUM> can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host device <NUM> and the memory system 110A, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

In the example environment <NUM> of <FIG>, the memory controller <NUM> also includes a cryptographic engine <NUM>. The cryptographic engine <NUM> can be configured to execute cryptographic operations on data, for example, as described herein. The cryptographic engine <NUM> may include one or more key registers and one or more math engines. Key registers can store cryptographic keys used to execute cryptographic operations. For example, a key register can store the memory system cryptographic key for evaluating signed commands (e.g., a public key of the signing device and/or a symmetric key also known to the signing device). Although key registers are described as components of the cryptographic engine <NUM>, in some examples, key registers may be positioned elsewhere, for example, a secured location at the memory array <NUM>. The math engine can be configured to perform cryptographic operations, for example, utilizing one or more cryptographic keys stored at a key register.

The cryptographic engine <NUM> can be configured to execute one or more cryptographic operations to generate digital signatures as described herein. The cryptographic engine <NUM> can be configured to generate digital signatures using any suitable cryptographic algorithm such as, for example, a cryptographic hash function such as an SHA algorithm (e.g., SHA256), the MD5 algorithm, etc. A cryptographic has function maps an input value to a, usually shorted, hash value. The hash function can be selected such that it is unlikely that two different input values will map to the same hash value. The cryptographic engine <NUM> can be configured to generate a digital signature by executing a hash function on an input value related to the thing being digitally signed. For example, the cryptographic engine <NUM> can concatenate a signed command to be executed, a memory system counter value, and a cryptographic key to form an input value. The cryptographic engine <NUM> can then execute the has function on the input value to generate a digital signature.

In some examples, the cryptographic engine <NUM> is configured to operate in conjunction with a communication interface between the host device <NUM> and the memory system 110A. For example, the cryptographic engine <NUM> may comprise a key register or other suitable storage location for storying a cryptographic key that is used for encrypting and/or generating digital signatures related to communications between the memory system 110A and host device <NUM>, for example, according to the PCle or other suitable interface.

In some examples, the memory controller <NUM> also comprises a memory device counter <NUM>. The memory device counter <NUM> includes software or hardware for incrementing counter values. The memory device counter <NUM> can be a monotonic counter that is configured such that the counter values always move in a particular direction along a counter sequence. For example, the memory device counter <NUM> begins at a known initial value (e.g., when the memory system 110A is manufactured). When an incrementing event occurs, the monotonic counter <NUM> increments from the known initial value to a next value along the counter sequence in the counter sequence direction. When a subsequent incrementing event occurs, the monotonic counter <NUM> increments to the next value along the counter sequence, and so on. The counter sequence can include, for example, a set of rising integers, a set of declining integers, a set of prime integers, a set of even integers, or any other suitable sequence. As used herein, a first counter value is said to be larger than a second counter value if the first counter value is encountered along the counter sequence after incrementing the counter one or more times from the second counter value along the counter sequence direction.

Incrementing events can include any suitable event at the memory system 110A. For example, an incrementing event can occur when the memory system 110A executes a command. Another example incrementing event can occur when the memory system 110A receives an instruction to increment the monotonic counter <NUM>. Another example incrementing event can occur when the memory system 110A is reset or restarted.

The memory array <NUM> can include several memory cells arranged in, for example, one or more devices, one or more planes, one or more sub-blocks, one or more blocks, one or more pages, etc. As one example, a <NUM> GB TLC NAND memory device can include <NUM>,<NUM> bytes (B) of data per page (<NUM>,<NUM> + <NUM> bytes), <NUM> pages per block, <NUM> blocks per plane, and <NUM> or more planes per device. As another example, a <NUM> GB MLC memory device (storing two bits of data per cell (i.e., <NUM> programmable states)) can include <NUM>,<NUM> bytes (B) of data per page (<NUM>,<NUM> + <NUM> bytes), <NUM> pages per block, <NUM> blocks per plane, and <NUM> planes per device, but with half the required write time and twice the program/erase (P/E) cycles as a corresponding TLC memory device. Other examples can include other numbers or arrangements. In some examples, a memory device, or a portion thereof, may be selectively operated in SLC mode, or in a desired MLC mode (such as TLC, QLC, etc.).

The memory array <NUM> includes physical address locations 150A, 150B, 150N. A physical address location 150A, 150B, 150N is a location at the memory array <NUM> that is uniquely associated with a physical address. In operation, data is typically written to or read from a NAND memory array <NUM> in pages, and erased in blocks. For example, a physical address location 150A, 150B, 150N may correspond to a page. However, some memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells, as desired. Accordingly, in some examples (e.g., for some operations) a physical address location 150A, 150B, 150N includes more or less than one page. The data transfer size of the memory system 110A is typically referred to as a page, whereas the data transfer size of a host device <NUM> is typically referred to as a sector.

Although a page of data can include a number of bytes of user data (e.g., a data payload including a number of sectors of data) and its corresponding metadata, the size of the page often refers only to the number of bytes used to store the user data. As an example, a page of data having a page size of <NUM> KB may include <NUM> KB of user data (e.g., <NUM> sectors assuming a sector size of <NUM> B) as well as a number of bytes (e.g., <NUM> B, <NUM> B, <NUM> B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detecting or correcting code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data. Physical address locations 150A, 150B, 150N with storage for metadata, etc. may be referred to as over-provisioned physical address locations.

Different types of memory cells or memory arrays <NUM> can provide for different page sizes, or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which can lead to different amounts of metadata necessary to ensure integrity of the page of data (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, a multilevel cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. As such, the MLC device may require more metadata bytes for error data than the corresponding SLC device.

<FIG> also shows the programming appliance <NUM> in communication with the host device <NUM>. The programming appliance <NUM> can be or include any suitable computing device or component such as, for example, one or more servers, one or more processors, one or more ASICs, one or more FPGAs, etc. The programming appliance <NUM> includes a programming appliance data storage <NUM> that can include any suitable volatile or nonvolatile data storage. The data storage <NUM> stores a command file <NUM>. The command file <NUM> includes one or more pre-generated digital signatures, as described herein.

The command file <NUM> is created by a generator device <NUM>. The generator device <NUM> can include any suitable computing device or component such as, for example, one or more servers, one or more HSMs, etc. The generator device <NUM> has access to the cryptographic keys for the memory systems 110A, 110B, 110N and creates the pre-generated digital signature or signatures included with the command file <NUM>. For example, in symmetric arrangements, the generator device <NUM> has access to symmetric cryptographic keys shared with the respective memory systems 110A, 110B, 110N. In asymmetric arrangements, the generator device <NUM> has access to private keys corresponding to public keys stored at the respective memory devices 110A, 110B, 110N.

The generator device <NUM> provides the command file <NUM> to the programming appliance <NUM> in any suitable manner for example, by a wired or wireless network connection, by a physical medium that is mailed or otherwise physically transported to the location of the programming appliance <NUM>, etc..

The programming appliance <NUM> uses the command file <NUM> to program one or more of the memory systems 110A, 110B, 110N, as described herein. For example, the programming appliance <NUM> selects from the command file <NUM> a pre-generated digital signature associated with a memory system 110A, 110B, 110N, a signed command and a selected value of the memory device counter <NUM>. The selected value of the memory device counter <NUM> may be the known initial value of the counter <NUM> or another value. The programming appliance <NUM> generates a command message <NUM> including the pre-generated digital signature and the command that is associated with the pre-generated digital signature.

The command message <NUM> is provided to the host controller <NUM> that, in turn, provides the command message to the memory system 110A. The memory system 110A (e.g., the controller <NUM> thereof) generates a cryptographic digest using the command from the command message <NUM>, a current value of the memory device counter <NUM>, and the memory system's cryptographic key. For example, the cryptographic digest can be generated using the cryptographic engine <NUM> to execute a cryptographic operation on the command, memory device counter value, and the cryptographic key for the memory system 110A. If the check digital signature is equivalent to the pre-generated digital signature, then the memory system 110A executes the indicated command.

<FIG> illustrates another example environment <NUM> including a programming appliance <NUM> configured to program memory systems through a number of host devices 205A, 205B, 205N. Each host device 205A, 205B, 205N can be in communication with one or more memory systems, similar to the memory systems 110A, 110B, 110N of the host device <NUM> of <FIG>. Three host devices 205A, 205B, 205N are shown in <FIG>, however, a single programming appliance may program memory systems at more or fewer host devices 205A, 205B, 205N than are shown. The programming appliance <NUM> sends command messages 228A, 228B, 228N to the respective host devices 205A, 205B, 205N. The command messages 228A, 228B 228N include commands and pre-generated signatures from a command file <NUM> stored at the data storage <NUM> of the programming appliance <NUM>. Each of the command messages 228A, 228B, 228N can be directed to a host devices 205A, 205B, 205N, which directs the command message 228A, 228B, 228N to a particular memory system.

In some examples, a command file, such as the command files <NUM>, <NUM>, include multiple pre-generated digital signatures that can be referenced by memory system, signed command, and/or memory system counter values. TABLE <NUM> below shows one arrangement of an example command file including pre-generated digital signatures for various memory systems described by unique identifiers (UIDs): UID0, UID1, UIDN:.

In TABLE <NUM>, the pre-generated digital signatures are not provided but, instead, are represented by "---. " In this example, the command file includes, for each memory system (UIDO, UID1. , UIDN), digital signatures generated for a first signed command (CMDO) for a number of different memory device counter values (MTCO-MTCN). In use, the programming appliance queries the appropriate host device to provide current memory system counter values for one or more memory systems in communication with the host device. For each memory system (UIDO, UID1. , UIDN), the programming appliance selects the pre-generated digital signature associated with that memory appliance, the first signed command (CMDO) and the current memory system counter value for that memory system. The programming appliance then generates command messages for the respective memory systems (UIDO, UID1. , UIDN) including the first command (CMDO) and the selected pre-generated digital signatures.

TABLE <NUM> shows another example arrangement of a command file, such as the command file <NUM>, <NUM> including sequences of pre-generated digital signatures for the memory systems (UIDO, UID1.

The sequence of pre-generated digital signatures for each memory system corresponds to a sequence of signed commands (CMDO, CMD1. For example, a sequence of pre-generated digital signatures for a first memory system (UIDO) includes a first pre-generated digital signature associated with a first command (CMDO) and a first memory system counter value (MTCO); a second pre-generated digital signature associated with a second command (CMD1) and a second memory system counter value (MTC1) greater than the first memory system counter value; and so on. The programming device can (via the appropriate host device) execute the sequence of signed commands at a memory system (UID0) by sending a command message including the pre-generated digital signature associated with (UID0, CMD0, MTC0) to the memory system (UID0). Executing the first command (UID0) at the memory system may cause the memory system counter to increment from the memory system counter value (MTC0) to the memory system counter value (MTC1). The programming applicance then sends a second command message to the memory system (UIDO) including the pre-generated digital signature associated with (UIDO, CMD1, MTC1), and so on.

In some examples, a command file can include pre-generated digital signatures to support more than one command sequence per memory system. For example, TABLE <NUM> shows sequences of pre-generated digital signatures beginning at memory system counter value (MTCO) to execute the command sequence (CMD0, CMD1. An example command file can also include additional sequences of pre-generated digital signatures for one or more of the memory systems to execute additional command sequences. Additional sequences of pre-generated digital signatures can begin at the same memory system counter value (e.g., MTC0 in the example of TABLE <NUM>) or at different memory system counter values.

In some examples, sequences of pre-generated digital signatures for different command sequences can share common pre-generated digital signatures. Referring to the example of TABLE <NUM>, consider an example command sequence (CMDX, CMD1. , CMDZ) beginning at memory system counter value (MTCO). Both this command sequence and the command sequence shown in TABLE <NUM> include a pre-generated digital signature for the signed command (CMD1) at memory system counter value MTC1. In some examples, the command file includes one copy of pre-generated signatures, such as this, that can be part of multiple command sequences. The single copy of the pre-generated digital signature can be referenced to multiple command sequences. For example, the command file can include command sequence data describing command sequences supported by the command file and referencing sequences of pre-generated digital signatures for the respective command sequences.

TABLE <NUM> shows yet another example arrangement of a command file, such as the command file <NUM>, <NUM>, including sequences of pre-generated signatures starting at different memory system counter values. The sequences of pre-generated digital signatures in TABLE <NUM> corresponds to a sequence of signed commands (CMD0, CMD1. In the example of TABLE <NUM>, the command file includes multiple sequences of pre-generated digital signatures for each memory system and command sequence. For example, as shown below, different sequences of pre-generated digital signatures for a memory system and command sequence can begin at different memory system counter values. The programming appliance can query the memory system for its current memory system counter value and select a sequence of pre-generated digital signatures that begin at the current memory system counter value.

<FIG> is a flowchart showing one example of a process flow <NUM> that can be executed by a programming appliance to send a command to a memory system. At operation <NUM>, the programming appliance receives a command file including at least one pre-generated digital signature. The command file can be received from a generator device, such as an HSM. The command file can be received in any suitable manner. For example, the command file can be received via an electronic medium such as e-mail. The command file, in some examples, can also be received in physical form such as, for example, on a storage device that is mailed or shipped to a location of the programming appliance.

At operation <NUM>, the programming appliance selects a pre-generated digital signature from the command file. The selected pre-generated digital signature corresponds to a memory system (e.g., at a host), a signed command, and a memory system counter value. The programming appliance may select the pre-generated digital signature based on a signed command to be sent, the memory system to which the pre-generated digital signature will be sent, and an expected value of the memory system counter. The expected value of the memory system counter is the value that the programming appliance expects the memory system counter to have. For example, if the memory system is newly manufactured, the expected value of the memory system counter can be the known initial value or a predetermined memory system counter value greater than the known initial value. , the memory system may be known to experience a known number of incrementing events during manufacture. ) Also, in some examples, the programming appliance queries the memory system to receive the current memory system counter value and selects the pre-generated digital signature based on the memory system's reply.

At operation <NUM>, the programming appliance sends to the memory system a command message. The command message includes the selected pre-generated digital signature and a signed command associated with the pre-generated digital signature. Sending the command message to the memory system can include sending the command message to a host device including the memory system. A host controller may forward the command message to the memory system.

<FIG> is a flowchart showing one example of a process flow <NUM> that can be executed by a programming appliance to send a command sequence to a memory system. At operation <NUM>, the programming appliance receives a command file including at least one pre-generated digital signature. At operation <NUM>, the programming appliance selects a pre-generated digital signature from the command file. For a first memory system, the first selected pre-generated digital signature corresponds to a first command of the command sequence, the first memory system, and a first memory system counter value. At operation <NUM>, the programming appliance sends a command message including the pre-generated digital signature selected at operation <NUM> and the signed command associated with pre-generated digital signature.

At operation <NUM>, the programming appliance determines, at operation <NUM>, whether there are more commands in the command sequence. For example, the programming appliance can consult command sequence data, which may be included in the command file. The command sequence data indicates the commands in the command sequence and/or pre-generated digital signatures in a sequence of pre-generated digital signatures that correspond to the command sequence. If all of the commands of the command sequence have been sent to the memory system, then the program is complete at operation <NUM>. If there are additional commands in the command sequence, the programming appliance moves to the next command at operation <NUM>, and then returns to operation <NUM> to select the pre-generated digital signature associated with the next command.

<FIG> is a flowchart showing one example of a process flow <NUM> that can be executed by a programming appliance to send a command to a memory system. At operation <NUM>, the programming appliance receives a command file including at least one pre-generated digital signature. At operation <NUM>, the programming appliance queries a memory system for its current memory system counter value. The query may be sent directly to the memory system or to a host device or host controller in communication with the memory system. The memory system responds by providing its current memory system counter value.

At operation <NUM>, the programming appliance selects from the command file a pre-generated digital signature associated with a signed command and the current memory system counter value. At operation <NUM>, the programming appliance sends to the memory system a command message including the selected pre-generated digital signature and the signed command.

<FIG> is a flowchart showing one example of a process flow <NUM> for sending a command message with a pre-generated digital signature to a memory system. The process flow <NUM> includes two columns <NUM>, <NUM>. The column <NUM> includes operations that can be executed by a programming appliance. The column <NUM> includes features that can be executed by a memory system. The programming appliance can possess the pre-generated digital signature at the beginning of the process flow <NUM>. Communications between the memory system and the programming appliance, in some examples, are facilitated by a host device in communication with the memory system.

At operation <NUM>, the programming appliance queries the memory system for its current memory system counter value, for example, by sending a query <NUM>. The memory system receives the query <NUM> at operation <NUM>. At operation <NUM>, the memory device provides a counter value message <NUM> including the current memory system counter value.

The programming appliance receives the counter value message <NUM> and determines, at operation <NUM>, if the current memory system counter value is equivalent to the memory system counter value that is associated with the pre-generated digital signature. If the current memory system counter value does not match the memory system counter value that is associated with the pre-generated digital signature, the programming appliance enters error processing at operation <NUM>. Accordingly, the process flow enters error processing at operation <NUM>. Error processing can include, for example, ending the process flow <NUM> and/or selecting a different pre-generated digital signature associated with a memory system counter value that matches the current memory system counter value.

If the current memory system counter value matches the memory system counter value that is associated with the pre-generated digital signature, the programming appliance sends a command message <NUM> to the memory system at operation <NUM>. The command message <NUM> includes the signed command associated with the pre-generated digital signature and the pre-generated digital signature.

The memory system verifies the command message <NUM> at operation <NUM>. Verifying the command message can include generating a check digital signature from the command, the current value of the memory system counter, and the cryptographic key. If the check digital signature matches the pre-generated digital signature, the memory system executes the command at operation <NUM>.

<FIG> is a flowchart showing one example of a process flow <NUM> for sending a command message with a pre-generated digital signature to a memory system. The process flow <NUM> includes two columns <NUM>, <NUM>. The column <NUM> includes operations that can be executed by a programming appliance. The column <NUM> includes features that can be executed by a memory system. Communications between the memory system and the programming appliance, in some examples, are facilitated by a host device in communication with the memory system.

In the process flow <NUM>, the programming appliance increments the memory system counter until the memory system counter value matches the memory system counter value associated with a pre-generated signature. The pre-generated signature can be associated with a single command. In some examples, the pre-generated signature can be associated with a sequence of commands (e.g., it may be the first pre-generated signature of the sequence). Incrementing the memory system counter, as described with respect to the process flow <NUM>, may allow the programming appliance to use command files with fewer pre-generated signatures. For example, the programming appliance may not need to use a command file, such as the examples of TABLES <NUM> and <NUM> above, that include more than one pre-generated digital signature for a given combination of a memory device and a signed command.

At the outset of the process flow <NUM>, the programming appliance possesses a pre-generated digital signature. The pre-generated digital signature can be associated with a stand-alone signed command or, in some examples, is associated with a first command of a command sequence. At operation <NUM>, the programming appliance queries the memory system for its current memory system counter value, for example, by sending a query <NUM>. The query <NUM> can be directed to a host device or host controller thereof that is associated with the memory device. The memory system receives the query <NUM> at operation <NUM>. At operation <NUM>, the memory device provides a counter value message <NUM> including the current memory system counter value.

At operation <NUM>, the programming appliance determines if the current memory system counter value matches the memory system counter value associated with the pre-generated digital signature. If there is no match, the programming appliance determines, at operation <NUM>, whether the current value of the memory system counter is greater than the memory system counter value associated with the pre-generated digital signature.

If the current memory system counter value is higher than the pre-generated digital signature (e.g., farther along the counter sequence), it indicates that the pre-generated digital signature may not be suitable for use. For example, because the memory system counter is monotonic, if it has already incremented past the memory counter value associated with the pre-generated digital signature, it may not be possible to use the pre-generated digital signature. The programming appliance enters error processing at operation <NUM>. Error processing can include ending the process flow <NUM>. In some examples, error processing includes selecting a different pre-generated digital signature from the command file and beginning the process flow <NUM> again.

Consider an example using the command file arrangement of TABLE <NUM> above where the pre-generated digital signature used with the process flow <NUM> was associated with the memory device (UID0), the signed command (CMDO), and the memory system counter value (MTCO). If the current memory system counter value is greater than the memory system counter value (MTCO), the programming appliance can select a different pre-generated digital signature from the command file associated with a higher memory system counter value. For example, the programming appliance can select a different pre-generated digital signature associated with a memory system counter value that is greater than or equal to the current memory system counter value provided by the memory device at operation <NUM>.

Consider another example using the command file arrangement of TABLE <NUM> above where the pre-generated digital signature used with the process flow <NUM> is the first pre-generated digital signature corresponds to the memory system counter value (MTCO) and is the first pre-generated digital signature of a sequence of pre-generated digital signatures corresponding to the command sequence (CMD0, CMD1. If the current memory system counter value is greater than the memory system counter value (MTCO), the programming appliance can select a different sequence of pre-generated digital signatures that correspond to the command sequence (CMD0, CMD1. For example, the programming appliance can re-execute the process flow <NUM> using the first pre-generated digital signature from another sequence of pre-generated digital signatures that also corresponds to the command sequence (CMD0, CMD1.

Referring now back to operation <NUM>, if the current value of the memory system counter is not greater than the memory system counter associated with the pre-generated digital signature, then the programming appliance causes the memory system to increment the memory system counter at operation <NUM>. The programming appliance can send an incrementing instruction <NUM>. The incrementing instruction <NUM> can be any action that prompts an incrementing event at the memory system. For example, the incrementing instruction <NUM> can be an explicit instruction to the memory system to increment its memory system counter. In another example, the incrementing instruction can be an instruction to the host device or host controller to reset the memory system. In response to the incrementing instruction <NUM>, the memory system increments its memory system counter at operation <NUM>.

After instructing the memory system to increment its memory system counter, the programming appliance returns to operation <NUM> and queries the memory system for its current counter value as described. In some examples, the programming appliance can predict the new current value of the memory system counter after incrementing from the previously-provided current value and the counter sequence. If the programming appliance predicts the new current value of the memory system counter, it may skip operation <NUM> and proceed to operation <NUM> instead (e.g., without re-querying the memory system for its current counter value).

The process flow <NUM> can execute until the current value of the memory system counter matches the selected value of the memory system counter associated with the pre-generated digital signature at operation <NUM>. When that occurs, the programming appliance sends a command message <NUM> to the memory system at operation <NUM>. The command message <NUM> includes the signed command associated with the pre-generated digital signature and the pre-generated digital signature.

The memory system verifies the command message <NUM> at operation <NUM>. Verifying the command message can include generating a check digital signature from the command, the current value of the memory system counter, and the cryptographic key. If the check digital signature matches the pre-generated digital signature, the memory system executes the command.

In some example arrangements, the command file includes multiple pre-digital signatures for the same combination of memory system and signed command. TABLES <NUM> and <NUM> above describe example command files with this arrangement. As described herein, this can increase the flexibility of the programming appliance if the current memory system counter value can take a range of values. It may also create opportunities for an unauthorized actor who has obtained the command file to exploit the pre-generated digital signatures in it to cause unintended changes at the memory system.

Consider an example using the command file arrangement shown in TABLE <NUM> where the programming appliance causes the memory system (UIDO) to execute the command (CMDO) using the pre-generated signature associated with memory device counter value (MTCO). The command file also includes pre-generated signatures for the signed command (CMDO) that correspond to other, greater memory system counter values (MTC1, MTC2. Accordingly, an unauthorized actor with possession of the command file could cause the memory system to execute the signed command (CMDO) again as long as the memory counter value at the memory system remains below (MTCN).

Consider another example using the command file configuration of TABLE <NUM> above where a programming appliance completes the command sequence (CMDO, CMD1, CMDN) at the memory device (CMDO) using the sequence of pre-generated digital signatures beginning at memory system counter value (MTCO). At the conclusion of the command sequence, it is possible that the current memory system counter value will still be below the memory system counter values associated with some of the pre-generated digital signatures. This means that an unauthorized actor with possession of the command file may be able to cause the memory system to execute additional signed commands. For example, after executing the command (CMDN) at memory system counter value (MTCN), an unauthorized actor may be able to cause the memory system to execute the signed command (CMDN) again using the pre-generated digital signature that corresponds to the memory counter value (MTCN+<NUM>).

<FIG> shows an example host device <NUM> (e.g., host <NUM>) with a memory system <NUM> (e.g., any of the memory devices described herein) as part of one or more apparatuses <NUM>-<NUM>. Apparatuses include any device that may include a host device, such as host device <NUM>. The host device <NUM> may be any device capable of executing instructions (sequential or otherwise). Example apparatuses include a vehicle <NUM> (e.g., as part of an infotainment system, a control system, or the like), a drone <NUM> (e.g., as part of a control system), furniture or appliances <NUM> (e.g., as part of a sensor system, an entertainment or infotainment system), or the like. In other examples, although not shown, apparatuses may include aeronautical, marine, Internet of Things (IOT), and other devices.

<FIG> illustrates a block diagram of an example machine <NUM> upon which any one or more of the techniques (e.g., methodologies) discussed herein may perform. The machine <NUM> may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, an loT device, automotive system, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine.

Examples, as described herein, may include, or may operate by, logic, components, devices, packages, or mechanisms. Circuitry is a collection (e.g., set) of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership may be flexible over time and underlying hardware variability. Circuitries include members that may, alone or in combination, perform specific tasks when operating. In an example, hardware of the circuitry may be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a non-transitory computer readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to encode instructions of the specific operation. In connecting the physical components, the underlying electrical properties of a hardware constituent are changed, for example, from an insulator to a conductor or vice versa. The instructions enable participating hardware (e.g., the execution units or a loading mechanism) to create members of the circuitry in hardware via the variable connections to carry out portions of the specific tasks when in operation. Accordingly, the computer readable medium is communicatively coupled to the other components of the circuitry when the device is operating. In an example, any of the physical components may be used in more than one member of more than one circuitry. For example, under operation, execution units may be used in a first circuit of a first circuitry at one point in time and reused by a second circuit in the first circuitry, or by a third circuit in a second circuitry at a different time.

The machine (e.g., computer system) <NUM> (e.g., the programming appliance <NUM>, generator device <NUM>, host device <NUM>, the memory system 110A, etc.) may include a hardware processor <NUM> (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as the memory controller <NUM>, etc.), a main memory <NUM> and a static memory <NUM>, some or all of which may communicate with each other via an interlink (e.g., bus) <NUM>. The machine <NUM> may include an output controller <NUM>, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

In an example, one or any combination of the hardware processor <NUM>, the main memory <NUM>, the static memory <NUM>, or the storage device <NUM> may constitute the machine readable medium <NUM>.

While the machine readable medium <NUM> is illustrated as a single medium, the term "machine readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions <NUM>.

The term "machine readable medium" may include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine <NUM> and that cause the machine <NUM> to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Nonlimiting machine readable medium examples may include solid-state memories, and optical and magnetic media. In an example, a massed machine readable medium comprises a machine-readable medium with a plurality of particles having invariant (e.g., rest) mass. Accordingly, massed machine-readable media are not transitory propagating signals. Specific examples of massed machine readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

The instructions <NUM> (e.g., software, programs, an operating system (OS), etc.) or other data are stored on the storage device <NUM>, can be accessed by the memory <NUM> for use by the processor <NUM>. The memory <NUM> (e.g., DRAM) is typically fast, but volatile, and thus a different type of storage than the storage device <NUM> (e.g., an SSD), which is suitable for long-term storage, including while in an "off" condition. The instructions <NUM> or data in use by a user or the machine <NUM> are typically loaded in the memory <NUM> for use by the processor <NUM>. When the memory <NUM> is full, virtual space from the storage device <NUM> can be allocated to supplement the memory <NUM>; however, because the storage <NUM> device is typically slower than the memory <NUM>, and write speeds are typically at least twice as slow as read speeds, use of virtual memory can greatly reduce user experience due to storage device latency (in contrast to the memory <NUM>, e.g., DRAM). Further, use of the storage device <NUM> for virtual memory can greatly reduce the usable lifespan of the storage device <NUM>.

In contrast to virtual memory, virtual memory compression (e.g., the Linux® kernel feature "ZRAM") uses part of the memory as compressed block storage to avoid paging to the storage device <NUM>. Paging takes place in the compressed block until it is necessary to write such data to the storage device <NUM>. Virtual memory compression increases the usable size of memory <NUM>, while reducing wear on the storage device <NUM>.

Storage devices optimized for mobile electronic devices, or mobile storage, traditionally include MMC solid-state storage devices (e.g., micro Secure Digital (microSD™) cards, etc.). MMC devices include a number of parallel interfaces (e.g., an <NUM>-bit parallel interface) with a host device, and are often removable and separate components from the host device. In contrast, eMMC™ devices are attached to a circuit board and considered a component of the host device, with read speeds that rival serial ATA™ (Serial AT (Advanced Technology) Attachment, or SATA) based SSD devices. However, demand for mobile device performance continues to increase, such as to fully enable virtual or augmented-reality devices, utilize increasing networks speeds, etc. In response to this demand, storage devices have shifted from parallel to serial communication interfaces. Universal Flash Storage (UFS) devices, including controllers and firmware, communicate with a host device using a low-voltage differential signaling (LVDS) serial interface with dedicated read/write paths, further advancing greater read/write speeds.

The instructions <NUM> may further be transmitted or received over a communications network <NUM> using a transmission medium via the network interface device <NUM> utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) <NUM> family of standards known as Wi-Fi®, IEEE <NUM> family of standards known as WiMax®), IEEE <NUM>. <NUM> family of standards, peer-to-peer (P2P) networks, among others. In an example, the network interface device <NUM> may include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communications network <NUM>. In an example, the network interface device <NUM> may include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine <NUM>, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.

These embodiments are also referred to herein as "examples". Such examples can include elements in addition to those shown or described.

" In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" may include "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein". Also, in the following claims, the terms "including" and "comprising" are openended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim.

In various examples, the components, controllers, processors, units, engines, or tables described herein can include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or multi-core devices.

The term "horizontal" as used in this document is defined as a plane parallel to the conventional plane or surface of a substrate, such as that underlying a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as "on," "over," and "under" are defined with respect to the conventional plane or surface being on the top or exposed surface of the substrate, regardless of the orientation of the substrate; and while "on" is intended to suggest a direct contact of one structure relative to another structure which it lies "on"(in the absence of an express indication to the contrary); the terms "over" and "under" are expressly intended to identify a relative placement of structures (or layers, features, etc.), which expressly includes--but is not limited to--direct contact between the identified structures unless specifically identified as such. Similarly, the terms "over" and "under" are not limited to horizontal orientations, as a structure may be "over" a referenced structure if it is, at some point in time, an outermost portion of the construction under discussion, even if such structure extends vertically relative to the referenced structure, rather than in a horizontal orientation.

The terms "wafer" and "substrate" are used herein to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication.

Various embodiments according to the present disclosure and described herein include memory utilizing a vertical structure of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives will be taken relative a surface of a substrate upon which the memory cells are formed (i.e., a vertical structure will be taken as extending away from the substrate surface, a bottom end of the vertical structure will be taken as the end nearest the substrate surface and a top end of the vertical structure will be taken as the end farthest from the substrate surface).

As used herein, directional adjectives, such as horizontal, vertical, normal, parallel, perpendicular, etc., can refer to relative orientations, and are not intended to require strict adherence to specific geometric properties, unless otherwise noted. For example, as used herein, a vertical structure need not be strictly perpendicular to a surface of a substrate, but may instead be generally perpendicular to the surface of the substrate, and may form an acute angle with the surface of the substrate (e.g., between <NUM> and <NUM> degrees, etc.).

In some embodiments described herein, different doping configurations may be applied to a source-side select gate (SGS), a control gate (CG), and a drain-side select gate (SGD), each of which, in this example, may be formed of or at least include polysilicon, with the result such that these tiers (e.g., polysilicon, etc.) may have different etch rates when exposed to an etching solution. For example, in a process of forming a monolithic pillar in a 3D semiconductor device, the SGS and the CG may form recesses, while the SGD may remain less recessed or even not recessed. These doping configurations may thus enable selective etching into the distinct tiers (e.g., SGS, CG, and SGD) in the 3D semiconductor device by using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

Operating a memory cell, as used herein, includes reading from, writing to, or erasing the memory cell. The operation of placing a memory cell in an intended state is referred to herein as "programming," and can include both writing to or erasing from the memory cell (e.g., the memory cell may be programmed to an erased state).

According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, controller, firmware, etc.) located internal or external to a memory device, is capable of determining (e.g., selecting, setting, adjusting, computing, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) a quantity of wear cycles, or a wear state (e.g., recording wear cycles, counting operations of the memory device as they occur, tracking the operations of the memory device it initiates, evaluating the memory device characteristics corresponding to a wear state, etc.).

According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to the memory device with each memory operation. The memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance changes corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., a value, characteristic) in response to the wear cycle information.

It will be understood that when an element is referred to as being "on," "connected to" or "coupled with" another element, it can be directly on, connected, or coupled with the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled with" another element, there are no intervening elements or layers present. If two elements are shown in the drawings with a line connecting them, the two elements can be either be coupled, or directly coupled, unless otherwise indicated.

Method examples described herein can be machine or computerimplemented at least in part. Further, the code can be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), solid state drives (SSDs), Universal Flash Storage (UFS) device, embedded MMC (eMMC) device, and the like.

Claim 1:
A method for memory system programming, comprising:
Receiving (<NUM>), by a programming appliance (<NUM>), a command file (<NUM>) comprising a plurality of pre-generated digital signatures, the plurality of pre-generated digital signatures comprising a first pre-generated digital signature, the first pre-generated digital signature associated with a memory system (110A), and generated by a signing device executing a cryptographic function, using a memory system cryptographic key associated with the memory system, the first pre-generated digital signature also being associated with a first command and a first memory system counter value;
selecting (<NUM>), by the programming appliance, the first pre-generated digital signature of the plurality of pre-generated digital signatures for the memory system based on the first command, the memory system to which the pre-generated digital signature will be sent, and an expected value of a memory system counter of the memory system which the programming appliance expects the memory system counter to have; and
sending (<NUM>), by the programming appliance and to the memory system, a first command message (<NUM>) comprising the first command and the first pre-generated digital signature.