Patent Description:
Since the invention of the integrated circuit, the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components. The improvement in integration density has come from continuous reductions in minimum feature size. The reduced feature size allows more components to be integrated into a given semiconductor area. As the demand for further reducing the size of the electronic device has grown recently, there has grown a need for more creative packaging techniques of semiconductor dies.

As semiconductor technologies evolve, fan-out wafer-level packaging has emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a semiconductor device having a fan-out signal routing layout, the input and output pads of a semiconductor die can be redistributed to an area outside the area under the semiconductor die. As such, the input and output pads can spread signals to a larger area than the area under the semiconductor die and provide additional space for interconnects. As a result of having the fan-out signal routing layout, the number of input and output pads of the semiconductor device can be increased.

In a fan-out wafer-level package, the semiconductor die may comprise radio-frequency integrated circuits (RFICs). An example of such a semiconductor device is an antenna-in-package (AiP) device. The AiP device includes an RFIC and an antenna. The RFIC and the antenna are included in a same package. The AiP device allows integration of RF components (e.g., an antenna) with active circuits (e.g., RFIC) into a same module. The AiP device is able to reduce the footprint of a radio frequency semiconductor device.

In some high frequency applications such as RFICs operating at millimeter wave frequencies, a variety of challenges exist. For example, the limiting factors for further reducing the size of the AiP device may come from how to route the antenna feeding structure so as to better isolate and/or shield the feedline and antenna layer. It is desirable to have new AiP structures to further improve the performance of the RFICs.

Publication <CIT> relates to a semiconductor package having an antenna. The semiconductor package includes a substrate, a chip, a molding compound and an antenna. The substrate has a first surface and a second surface. The chip is disposed on the first surface of the substrate, and electrically connected to the substrate. The molding compound encapsulates the whole or a part of the chip. The antenna is disposed on the molding compound, and electrically connected to the chip.

Publication <CIT> relates to an apparatus including a die width through-silicon via and radio frequency integrated circuits capabilities which is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate Where each of the plurality of antenna elements is coupled to the through-silicon Vias and radio frequency integrated circuit through a plurality of through-silicon Vias.

Publication <CIT> relates to a semiconductor package integrated with a conformal shield and an antenna. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element.

There may be a demand for providing an improved concept for a semiconductor device and a method.

Such demand may be satisfied by a semiconductor device as defined in claim <NUM> and a method as defined in claim <NUM>.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure.

The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

The present disclosure will be described with respect to preferred embodiments in a specific context, namely an antenna-in-package semiconductor device. The present disclosure may also be applied, however, to a variety of radio frequency semiconductor devices. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

<FIG> illustrates a block diagram of a radio frequency semiconductor device in accordance with various embodiments of the present disclosure. The radio frequency semiconductor device <NUM> comprises a radio frequency integrated circuit (RFIC). For simplicity, the functional blocks of the radio frequency semiconductor device <NUM> are not illustrated in <FIG>. A person skilled in the art would understand the radio frequency semiconductor device <NUM> may comprise a variety of functional blocks such as a baseband processor, a transmitter, a receiver and the like. Throughout the description, the radio frequency semiconductor device <NUM> may be alternatively referred to as a RFIC <NUM>.

The radio frequency semiconductor device <NUM> comprises various active circuits. The radio frequency semiconductor device <NUM> is implemented on a semiconductor die (shown in <FIG>). The active circuits (e.g., RFIC) are formed adjacent to a second side of the semiconductor die. The side for instance corresponds to a front side of the semiconductor die. A first side of the semiconductor die is known as a backside of the semiconductor die. The front side and the backside are two opposite sides of the semiconductor die.

As shown in <FIG>, the radio frequency semiconductor device <NUM> comprises a plurality of input/output pads <NUM>. The input/output pads <NUM> are employed to electrically couple the RFIC to external circuits. In some embodiments, the input/output pads <NUM> are placed adjacent to the front side of the semiconductor die. A plurality of conductive features may be formed on the backside of the semiconductor die. Furthermore, a plurality of vias may be formed in the semiconductor die. The RFIC may be electrically coupled to the conductive feature through at least one of the plurality of vias. The detailed structure of the radio frequency semiconductor device <NUM> will be described below with respect to <FIG>.

The radio frequency semiconductor device <NUM> may be integrated into a package along with a plurality of antenna structures (e.g., antenna layers). A semiconductor package including both RFIC and the antenna structures is known as an antenna-in-package (AiP) device. The detailed structure of the AiP device will be described below with respect to <FIG>.

<FIG> illustrates a cross sectional view of a first implementation of an AiP device including the radio frequency semiconductor device shown in <FIG> in accordance with various embodiments of the present disclosure. The AiP device <NUM> is also referred to generically as a semiconductor device <NUM>. The AiP device <NUM> comprises the radio frequency semiconductor device <NUM> embedded in a first dielectric layer <NUM>. In some embodiments, the first dielectric layer <NUM> is formed of suitable dielectric materials such as epoxy resin, glass fiber (e.g., pre-preg), mold compound materials and the like. In some embodiments, the first dielectric layer may be implemented as a molding compound layer. As shown in <FIG>, the radio frequency semiconductor device <NUM> is formed in a semiconductor die. Throughout the description, the radio frequency semiconductor device <NUM> may be alternatively referred to as a semiconductor die <NUM>.

The semiconductor die <NUM> comprises a plurality of input/output pads <NUM> formed on a second side of the semiconductor die <NUM>, and conductive features <NUM> and <NUM> formed on a first side of the semiconductor die <NUM>. As described above with respect to <FIG>, the second side of the semiconductor die <NUM> is a front side of the semiconductor die. The first side of the semiconductor die <NUM> is a backside of the semiconductor die. The semiconductor die <NUM> further comprises a plurality of vias <NUM> and <NUM> arranged therethrough. The vias <NUM>, <NUM> are formed using corresponding openings arranged in the semiconductor die <NUM>. As shown in <FIG>, the vias <NUM> and <NUM> extends from the backside to the front side of the semiconductor die <NUM>. In alternative embodiments, the vias <NUM>, <NUM> may be blind vias that extend to the backside (first side) of the semiconductor die <NUM>, the openings being correspondingly blind openings arranged in the backside of the semiconductor die <NUM>.

It should be noted that <FIG> illustrates only two input/output pads of the semiconductor die <NUM> that may include a large number, e.g. hundreds, of such input/output pads. The number of input/output pads illustrated herein is limited solely for the purpose of clearly illustrating the inventive aspects of the various embodiments. The present disclosure is not limited to any specific number of input/output pads. Likewise, the number of the vias (e.g., vias <NUM> and <NUM>) of the semiconductor die <NUM> illustrated herein is limited solely for the purpose of clearly illustrating the inventive aspects of the various embodiments. Furthermore, while <FIG> illustrates the semiconductor die <NUM> with two conductive features <NUM> and <NUM>, the semiconductor die <NUM> could accommodate any number of conductive features.

As shown in <FIG>, there may be a plurality of vias formed in the first dielectric layer <NUM>. More particularly, a first via <NUM> extends from a surface of a first side (top side on <FIG>) of the first dielectric layer <NUM> to a surface of the conductive feature <NUM>. A second via <NUM> extends from the surface of the first side of the first dielectric layer <NUM> to a surface of the conductive feature <NUM>. A third via <NUM> extends from a surface of a second side (bottom side on <FIG>) of the first dielectric layer <NUM> to a surface of the input/output pad <NUM>. A fourth via <NUM> extends from the surface of the second side of the first dielectric layer <NUM> to a surface of the input/output pad <NUM>. In some embodiments, the third via <NUM> and the fourth via <NUM> are implemented as micro vias. As shown in <FIG>, the first side and the second side described above are two opposite sides of the first dielectric layer <NUM>. It should be noted while <FIG> shows the vias (e.g., <NUM>) have a rectangular shape from the cross sectional view, the shape of the vias may vary depending on different via formation processes. For example, when a laser drilling process is employed to form the vias, the vias may be of a frustoconical shape.

Furthermore, a second dielectric layer <NUM> is deposited over the first side of the first dielectric layer <NUM>. A plurality of antenna layers <NUM> and <NUM> are embedded in the second dielectric layer <NUM>. As shown in <FIG>, a first antenna layer <NUM> is formed on the surface of the first side of the first dielectric layer <NUM>. The first antenna layer <NUM> is electrically coupled to the first via <NUM>. Likewise, a second antenna layer <NUM> is formed on the surface of the first side of the first dielectric layer <NUM>. The second antenna layer <NUM> is electrically coupled to the second via <NUM>.

In addition, a third dielectric layer <NUM> is deposited over the second side of the first dielectric layer <NUM>. One or more redistribution layers, e.g. a plurality of redistribution layers <NUM> and <NUM> is embedded in the third dielectric layer <NUM>. The redistribution layers <NUM> and <NUM> and the third dielectric layer <NUM> form a redistribution structure. A plurality of metal bumps <NUM> are formed over the third dielectric layers <NUM>. The metal bumps <NUM> are coupled to the semiconductor die <NUM> as well as the antenna layers <NUM> and <NUM>. Throughout the description, the metal bumps <NUM> may be alternatively referred to as the input/output connectors of the AiP device <NUM>.

As shown in <FIG>, the antenna layers <NUM> and <NUM> are electrically coupled to the active circuits of the semiconductor die <NUM> through a conductive channel formed by vias <NUM>, <NUM>, the conductive features <NUM>, <NUM>, and vias <NUM>, <NUM> within semiconductor die <NUM>. It should be noted that the via used in this disclosure is formed by filling a conductive material in an opening. The via is a conductive via after the conductive material has been filled into the opening. Throughout the description, the conductive channel may be alternatively referred to as an antenna feeding structure, which is used to convey RF signals between the semiconductor die <NUM>, and the antenna layers <NUM> and <NUM>.

As shown in <FIG>, the antenna feeding structure comprises three portions. A first portion of the antenna feeding structure is formed by the via (e.g., via <NUM>) of the semiconductor die <NUM>. In other words, the first portion of the antenna feeding structure is arranged inside the semiconductor die <NUM>, and is connected to the active circuits thereof within the semiconductor die <NUM>. A second portion of the antenna feeding structure is formed by the via (e.g., via <NUM>) in the first dielectric layer <NUM>. A third portion of the antenna feeding structure is arranged within the conductive feature (e.g., conductive feature <NUM>). As shown in <FIG>, the third portion (e.g., conductive feature <NUM>) of the antenna feeding structure is coupled between the first portion (e.g., via <NUM>) and the second portion (e.g., via <NUM>) of the antenna feeding structure. The third portion is shown arranged along the first surface (backside) of the semiconductor die <NUM>. In <FIG>, the antenna feeding structure only comprises these three portions.

One advantageous feature of integrating the antenna structure (e.g., antenna layers <NUM> and <NUM>) into a fan-out wafer level package is that the antenna structures shown in <FIG> provide a small form factor, low cost and low signal loss solution for radio frequency applications. The formation processes of the AiP device <NUM> will be described in detail with respect to <FIG>.

<FIG> illustrates a top view of the AiP device shown in <FIG> in accordance with various embodiments of the present disclosure. <FIG> shows the boundary of the second dielectric layer <NUM>. <FIG> also illustrates vias <NUM>, <NUM>, antenna layers <NUM>, <NUM> and vias <NUM>, <NUM>. Referring back to <FIG>, vias <NUM> and <NUM> are formed in the first dielectric layer <NUM>. Antenna layers <NUM> and <NUM> are formed in the second dielectric layer <NUM>. Vias <NUM> and <NUM> are formed in the semiconductor die <NUM>.

It should be noted that not all features of the AiP device <NUM> are illustrated in <FIG>. Furthermore, the features illustrated in <FIG> may not be along a same cross sectional view.

As shown in <FIG>, the antenna layers <NUM> and <NUM> are rectangular in shape. In operation, RF signals generated by the RFIC flow through a conductive path comprising vias <NUM>, <NUM>, the conductive features <NUM>, <NUM>, vias <NUM>, <NUM> and antenna layers <NUM>, <NUM>. Vias <NUM>, <NUM>, the conductive features <NUM>, <NUM>, and vias <NUM>, <NUM> form an antenna feeding structure between the RFIC and the antenna layers <NUM>, <NUM>.

In some embodiments, the antenna layers <NUM> and <NUM> may be part of a transmitter. The antenna layers <NUM> and <NUM> may be configured to transmit the RF signals to a receiving circuit (not shown). In alternative embodiments, the antenna layers <NUM> and <NUM> may be part of a receiver. The antenna layers <NUM> and <NUM> may be configured to receive RF signals. The RF signals flow from the antenna layers <NUM> and <NUM> to the RFIC through the same conductive path. Furthermore, the antenna layers <NUM> and <NUM> may be part of a monostatic radar system in which both the transmitter and the receiver are collocated. The antenna layers <NUM> and <NUM> may be configured to transmit and/or receive RF signals.

It should be noted that while <FIG> shows the antenna layers are substantially rectangular in shape, it is merely an example. It is within the scope and spirit of the disclosure for the antenna layers <NUM> and <NUM> to comprise other shapes, such as, but not limited to oval, square, or circular. Furthermore, depending on different applications and design needs, the shape as well as the dimension of the antenna layers <NUM> and <NUM> may vary accordingly. For example, the shape and/or the dimension of the antenna layers may be modified to accommodate different RF communication frequencies.

In operation, the antenna feeding structure described above is sensitive electrically and mechanically. If the antenna feeding structure is routed within the AiP device <NUM> by the front side of the semiconductor die, the input/output connectors <NUM> cannot be placed under the semiconductor die <NUM>. Referring back to <FIG>, the antenna feeding structure is routed along the backside of the semiconductor die <NUM>. Since the antenna feeding structure has been moved from the front side to the backside of the semiconductor die <NUM> using the via <NUM>, <NUM>, the input/output connectors <NUM> can be placed adjacent to the front side of the semiconductor die <NUM>. For example, as shown in <FIG>, at least four input/output connectors <NUM> are placed under the semiconductor die <NUM>. One advantageous feature of placing the input/output connectors under the semiconductor die <NUM> is the total package size of the AiP device <NUM> can be reduced.

<FIG> illustrates a cross sectional view of a second implementation of the AiP device including the radio frequency semiconductor device shown in <FIG> in accordance with various embodiments of the present disclosure. The structure of the AiP device <NUM> is similar to that of the AiP device <NUM> shown in <FIG> except that the antenna feeding structure only comprises two portions. A first portion is arranged within the via (e.g., via <NUM>) of the semiconductor die <NUM>. A second portion (e.g., via <NUM>) is arranged within the via in the first dielectric layer <NUM>.

As shown in <FIG>, the first portion (e.g., via <NUM>) of the antenna feeding structure is in direct contact with the second portion (e.g., via <NUM>), i.e. the first portion prolongs the second portion directly. The antenna layer (e.g., antenna layer <NUM>) is electrically coupled to the semiconductor die <NUM> through the second portion (e.g., via <NUM>) formed in the first dielectric layer <NUM> and the first portion (e.g., via <NUM>) formed in the semiconductor die <NUM>. As shown in <FIG>, the width (the diameter of the via) of the second portion (e.g., via <NUM>) is greater than the width of the first portion (e.g., via <NUM>).

It should be noted that the dimensions of the first portion and the second portion of the antenna feeding structure shown in <FIG> are merely an example. Depending on different applications and design needs, the dimensions of the first portion and the second portion of the antenna feeding structure may vary accordingly. For example, the width of the first portion (e.g., via <NUM>) is greater than the width of the second portion (e.g., via <NUM>).

<FIG> illustrates a cross sectional view of a third implementation of the AiP device including the radio frequency semiconductor device shown in <FIG> in accordance with various embodiments of the present disclosure. The structure of the AiP device <NUM> is similar to that of the AiP device <NUM> shown in <FIG> except that the width of the second portion (e.g., via <NUM>) is equal to the width of the first portion (e.g., via <NUM>).

One advantageous feature of having the width of the second portion equal to the width of the first portion is these two vias (e.g., vias <NUM> and <NUM>) can be formed in a same via forming process such as a laser drilling process.

<FIG> illustrates a cross sectional view of a fourth implementation of the AiP device including the radio frequency semiconductor device shown in <FIG> in accordance with various embodiments of the present disclosure. The structure of the AiP device <NUM> is similar to that of the AiP device <NUM> shown in <FIG> except that the antenna layers <NUM> and <NUM> extend over the sidewalls of the AiP device <NUM>. In other words, the antenna layers <NUM> define antennas which extend over the sidewalls of the AiP device <NUM>. As shown in <FIG>, the antenna layer <NUM> partially covers the leftmost sidewall of the AiP device <NUM>. Likewise, the antenna layer <NUM> partially covers the rightmost sidewall of the AiP device <NUM>.

Extending the antenna layers over the sidewalls of the AiP device <NUM> shown in <FIG> is merely an example. Depending on different applications and design needs, there may be many variations, modifications and alternatives. For example, the antenna layer <NUM> may fully cover the sidewall of the first dielectric layer <NUM>, or only one of the antenna layers may extend over the sidewall of the first dielectric layer <NUM>.

<FIG> illustrates a cross sectional view of a fifth implementation of the AiP device including the radio frequency semiconductor device shown in <FIG> in accordance with various embodiments of the present disclosure. The structure of the AiP device <NUM> is similar to that of the AiP device <NUM> shown in <FIG> except that the vias <NUM> and <NUM> are not through vias.

As shown in <FIG>, the semiconductor die <NUM> comprises conductive contacts <NUM> and <NUM>. The conductive contacts <NUM> and <NUM> are embedded in the semiconductor die <NUM>. As shown in <FIG>, the via <NUM> extends partially through the semiconductor die <NUM>. The first terminal of the via <NUM> is in direct contact with the conductive feature <NUM>. The second terminal of the via <NUM> is in direct contact with the conductive contact <NUM>. Likewise, The via <NUM> extends partially through the semiconductor die <NUM>. The first terminal of the via <NUM> is in direct contact with the conductive feature <NUM>. The second terminal of the via <NUM> is in direct contact with the conductive contact <NUM>.

<FIG> illustrates a cross sectional view of a sixth implementation of the AiP device including the radio frequency semiconductor device shown in <FIG> in accordance with various embodiments of the present disclosure not forming part of the claimed invention. The structure of the AiP device <NUM> is similar to that of the AiP device <NUM> shown in <FIG> except that the semiconductor die <NUM> is connected to the redistribution structure directly. In contrast with the AiP device <NUM> shown in <FIG>, the semiconductor die <NUM> is in direct contact with the third dielectric layer <NUM>. As shown in <FIG>, the input/output pads <NUM> of the semiconductor die <NUM> are electrically coupled to the redistribution layer <NUM> and <NUM> directly. Compared with the AiP device <NUM> shown in <FIG>, no vias <NUM> and <NUM> are needed to electrically couple the redistribution layer <NUM> and <NUM> with the input/output pads <NUM> of the semiconductor die <NUM>.

<FIG> illustrates a cross sectional view of a seventh implementation of the AiP device including the radio frequency semiconductor device shown in <FIG> in accordance with various embodiments of the present disclosure. The structure of the AiP device <NUM> is similar to that of the AiP device <NUM> shown in <FIG> except that the antenna structure has multiple metal and dielectric layers. As shown in <FIG>, an additional dielectric layer <NUM> is formed between the first dielectric layer <NUM> and the second dielectric layer <NUM>.

The dielectric layer <NUM> may be formed of a high performance RF material such as Rogers <NUM>. The antenna layers <NUM> and <NUM> are formed on a first surface of the dielectric layer <NUM>. The antenna layers <NUM> and <NUM> are embedded in the second dielectric layer <NUM>. As shown in <FIG>, the antenna layers <NUM> and <NUM> are not electrically coupled to the semiconductor die <NUM>. Instead, the antenna layers <NUM> and <NUM> are magnetically coupled to conductive features <NUM> and <NUM> respectively.

As shown in <FIG>, the AiP device <NUM> comprises a plurality of metal structures comprising horizontal metal lines <NUM> and vertical metal lines <NUM>. In some embodiments, the horizontal metal lines <NUM> and the vertical metal lines <NUM> are electrically grounded. As shown in <FIG>, the vertical metal lines <NUM> extend through the dielectric layer <NUM>. The vertical metal lines <NUM> are between the second dielectric layer <NUM> and the first dielectric layer <NUM>.

As shown in <FIG>, openings <NUM> may be formed in the horizontal metal lines <NUM>. A first opening (opening <NUM> on the left) is between the antenna layer <NUM> and the conductive feature <NUM>. A second opening (opening <NUM> on the right) is between the antenna layer <NUM> and the conductive feature <NUM>. The conductive features <NUM> and <NUM> are electrically coupled to the semiconductor die <NUM> through the antenna feeding structure. The RF signals generated by the semiconductor die <NUM> are sent to the conductive features <NUM> and <NUM> first, and then are electromagnetically coupled to the antenna layers <NUM> and <NUM> through the openings <NUM>.

<FIG> illustrates a cross sectional view of an eighth implementation of the AiP device including the radio frequency semiconductor device shown in <FIG> in accordance with various embodiments of the present disclosure. The structure of the AiP device <NUM> is similar to that of the AiP device <NUM> shown in <FIG> except that the input/output connectors of the AiP device <NUM> are implemented as land grid array (LGA) pads. The LGA pads are well known in the art, and hence are not discussed in further detail to avoid repetition.

It should be noted that that features and embodiments described above with respect to one particular AiP device may be applicable to any other AiP devices described in <FIG>. For example, depending on different applications and design needs, the antenna feeding structure (e.g., vias <NUM> and <NUM>) shown in <FIG> may be used to replace the antenna feeding structure (e.g., via <NUM>, conductive feature <NUM> and via <NUM>) shown in <FIG>.

<FIG> illustrate intermediate steps of fabricating the AiP device shown in <FIG> in accordance with various embodiments of the present disclosure. It should be noted that the fabrication steps as well as the AiP structure shown in <FIG> are merely an example. A person skilled in the art will recognize there may be many alternatives, variations and modifications.

<FIG> illustrates a cross sectional view of a carrier in accordance with various embodiments of the present disclosure. The carrier <NUM> may be formed of silicon, glass, ceramic aluminum oxide, silicon oxide, any combinations thereof and/or the like. A release layer (not shown) may be formed over the carrier <NUM>. In some embodiments, the release layer is formed of an epoxy-based thermal-release material. In alternative embodiments, the release layer may be formed of an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. Furthermore, the release layer may be formed of a light-to-heat conversion layer, which loses its adhesive property after the release layer has been exposed to laser light.

<FIG> illustrates a cross sectional view of a semiconductor device after a semiconductor die has been mounted on the carrier in accordance with various embodiments of the present disclosure. The semiconductor die <NUM> comprises a plurality of input/output pads <NUM> formed on a front side of the semiconductor die <NUM>, a plurality of vias <NUM>, <NUM> extending through the semiconductor die <NUM>, and a plurality of conductive features <NUM>, <NUM> formed on a backside of the semiconductor die <NUM>.

As shown in <FIG>, the front side of the semiconductor die <NUM> is mounted on the carrier <NUM>. The input/output pads <NUM> are in direct contact with the carrier <NUM>. The conductive features <NUM> and <NUM> are formed on the backside of the semiconductor die <NUM>. The conductive features <NUM> and <NUM> may be formed by suitable semiconductor fabrication processes such as plating and the like.

It should be noted that the semiconductor die <NUM> is drawn without details. The semiconductor die <NUM> may comprise a substrate, active circuits (e.g., RFIC), a plurality of inter-layer dielectric (ILD) layers and inter-metal dielectric (IMD) layers.

The substrate of the semiconductor die <NUM> may be formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof. The substrate may also be in the form of silicon-on-insulator (SOI). The SOI substrate may comprise a layer of a semiconductor material (e.g., silicon, germanium and/or the like) formed over an insulator layer (e.g., buried oxide or the like), which is formed in a silicon substrate. In addition, other substrates that may be used include multilayered substrates, gradient substrates, hybrid orientation substrates and/or the like.

The active circuits formed on the substrate may be any type of circuitry suitable for a particular application. In accordance with an embodiment, the active circuits may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and/or the like. The active circuits may be interconnected to perform one or more functions. The functions may include radio frequency circuits, memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry and/or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only and are not intended to limit the various embodiments to any particular applications.

Throughout the description, the side of the semiconductor die having active circuits is alternatively referred to as the front side of the semiconductor die <NUM>. On the other hand, the side of the semiconductor die not having active circuits is referred to as the backside of the semiconductor die <NUM>.

It should be noted that while <FIG> illustrates a single semiconductor die mounted on the carrier <NUM>, the carrier <NUM> may accommodate any number of semiconductor dies.

<FIG> illustrates a cross sectional view of the semiconductor device shown in <FIG> after a first dielectric layer is formed over the semiconductor device in accordance with various embodiments of the present disclosure. In some embodiments, the first dielectric layer <NUM> is formed of suitable dielectric materials such as epoxy resin, glass fiber (e.g., pre-preg), mold compound materials and the like. In some embodiments, the first dielectric layer <NUM> is a molding compound layer. The molding compound layer <NUM> may be formed of epoxy based resins and the like. Alternatively, the molding compound layer <NUM> may be replaced by photo-sensitive materials including polybenzoxazole (PBO), SU-<NUM> photo-sensitive epoxy, film type polymer materials and/or the like. Throughout the description, the first dielectric layer <NUM> may be alternatively referred to as a molding compound layer.

In accordance with an embodiment, the molding compound layer <NUM> is either laminated or coated over the semiconductor die <NUM>. One advantageous feature of having a molding compound layer laminated or coated on top of the semiconductor die <NUM> is that the effective die area of the semiconductor die <NUM> can be expanded so that a fan-out package can be formed based upon the molding compound layer <NUM>.

<FIG> illustrates a cross sectional view of the semiconductor device shown in <FIG> after the carrier has been removed and additional dielectric materials have been deposited over the semiconductor die in accordance with various embodiments of the present disclosure. The carrier <NUM> shown in <FIG> can be detached from the semiconductor device. A variety of detaching processes may be employed to separate the semiconductor device from the carrier <NUM>. The variety of detaching processes may comprise a chemical solvent, a UV exposure, a laser de-bonding process and the like.

After the carrier <NUM> has been detached, additional dielectric materials have been deposited over the semiconductor die <NUM>. The additional dielectric materials are similar to that of the first dielectric layer <NUM>. The additional dielectric materials may be formed over the front side of the semiconductor die <NUM> using a same or similar formation process discussed above. As a result of depositing more dielectric materials over the semiconductor die <NUM>, the semiconductor die <NUM> is fully covered by the first dielectric layer <NUM>.

<FIG> illustrates a cross sectional view of the semiconductor device shown in <FIG> after two seed layers have been formed over the first dielectric layer in accordance with various embodiments of the present disclosure. A first seed layer <NUM> is formed on a first surface of the first dielectric layer <NUM>. A second seed layer <NUM> is formed on a second surface of the first dielectric layer <NUM>. The seed layers <NUM> and <NUM> may comprise a suitable conductive material such as copper. In some embodiments, the seed layers <NUM> and <NUM> are formed using a suitable formation method such as chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like.

<FIG> illustrates a cross sectional view of the semiconductor device shown in <FIG> after two openings have been formed in the first dielectric layer in accordance with various embodiments of the present disclosure. A first opening <NUM> and a second opening <NUM> are formed in the first dielectric layer <NUM>. As shown in <FIG>, the openings <NUM> and <NUM> extend from the first seed layer <NUM> to the conductive features on the backside of the semiconductor die <NUM>. The openings <NUM> and <NUM> may be formed by a suitable drilling process such as a laser drilling process. After the openings <NUM> and <NUM> have been formed, the top surfaces of the conductive features are exposed.

<FIG> illustrates a cross sectional view of the semiconductor device shown in <FIG> after a conductive material has been filled in the openings in accordance with various embodiments of the present disclosure. A conductive material (e.g., copper) has filled the openings <NUM> and <NUM> (shown in <FIG>) to form the vias <NUM> and <NUM>. Furthermore, the conductive material is used to form the antenna layers <NUM> and <NUM> using a suitable formation method such as plating.

The formation process of the antenna layers <NUM> and <NUM> comprises depositing a first photoresist layer over the first seed layer <NUM> (shown in <FIG>), plating the conductive material over exposed portions of the first seed layer to form the antenna layers <NUM> and <NUM>, removing the first photoresist layer to expose the first seed layer under the first photoresist layer, and after removing the first photoresist layer, applying a first etching process to remove exposed portions of the first seed layer. The first photoresist layer is of a first predetermined pattern, which matches the shape of the antenna layers <NUM> and <NUM>.

<FIG> illustrates a cross sectional view of the semiconductor device shown in <FIG> after the redistribution layer has been formed in accordance with various embodiments of the present disclosure. Similar to the process of forming the antenna layers shown in <FIG>, two openings are formed in the first dielectric layer <NUM> and under the semiconductor die <NUM>. The conductive material (e.g., copper) is filled in the openings to form the vias <NUM> and <NUM>. Furthermore, the conductive material is used to form the redistribution layers <NUM> and <NUM> using a suitable formation method such as plating.

The formation process of the redistribution layers <NUM> and <NUM> comprises depositing a second photoresist layer over the second seed layer <NUM> (shown in <FIG>), plating the conductive material over exposed portions of the second seed layer to form the redistribution layers <NUM> and <NUM>, removing the second photoresist layer to expose the second seed layer under the second photoresist layer, and after removing the second photoresist layer, applying a second etching process to remove exposed portions of the second seed layer. The second photoresist layer is of a second predetermined pattern, which matches the shape of the redistribution layers <NUM> and <NUM>.

<FIG> illustrates a cross sectional view of the semiconductor device shown in <FIG> after additional dielectric layers have been formed in accordance with various embodiments of the present disclosure. The second dielectric layer <NUM> is formed over the upper surface of the first dielectric layer <NUM>. After the second dielectric layer <NUM> has been formed, the antenna layers <NUM> and <NUM> are embedded in the second dielectric layer <NUM>. In some embodiments, the second dielectric layer <NUM> may be formed of a different dielectric material than that of the first dielectric layer <NUM>. For example, the second dielectric layer <NUM> may be a solder resist layer. Alternatively, the second dielectric layer <NUM> may be formed of a same material as the first dielectric layer <NUM>.

Furthermore, the third dielectric layer <NUM> is formed over the lower surface of the first dielectric layer <NUM>. After the third dielectric layer <NUM> has been formed, the redistribution layers <NUM> and <NUM> are embedded in the third dielectric layer <NUM>. In some embodiments, the third dielectric layer <NUM> may be formed of a suitable polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), any combinations thereof and the like. In alternative embodiments, the third dielectric layer <NUM> may be formed of a suitable nitride based material such as silicon nitride. Furthermore, other suitable dielectric materials such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG) may be used to form the third dielectric layer <NUM>.

The dielectric layers <NUM> and <NUM> may be formed by suitable deposition processes such as spin coating, laminating, CVD, PVD and the like. The redistribution layers <NUM>, <NUM> and the third dielectric layer <NUM> may be collectively referred to as a redistribution structure.

It should be noted that while <FIG> shows the redistribution structure comprises one dielectric layer and one layer of conductive metal lines, the redistribution structure may include multiple layers of conductive features (e.g., conductive metal lines and vias) formed in multiple dielectric layers.

<FIG> illustrates a cross sectional view of the semiconductor device shown in <FIG> after a plurality of input/output connectors has been formed in accordance with various embodiments of the present disclosure. The input/output connectors <NUM> extend into the third dielectric layer <NUM>. The input/output connectors <NUM> are mechanically and electrically coupled with the redistribution layers <NUM> and <NUM>. In some embodiments, the input/output connectors <NUM> are conductive bumps such as controlled collapse chip connection (C4) bumps. The C4 bumps comprise a suitable conductive material such as tin. In alternative embodiments, the input/output connectors <NUM> may be implemented as solder bumps.

One advantageous feature of the AiP device shown in <FIG> is at least one input/output connector is laterally between two sidewalls of the semiconductor die <NUM>. In a conventional AiP device, the antenna feeding structure is routed along the front side of the semiconductor die. In order to prevent the input/output connectors from interfering with the antenna feeding structure, the input/output connectors cannot be placed under the semiconductor die. In other words, the input/output connectors cannot be placed between two sidewalls of the semiconductor die. In the present disclosure, the antenna feeding structure is routed along the backside of the semiconductor die <NUM>. As a result of having this antenna feeding structure arrangement, the input/output connectors <NUM> can be placed between two sidewalls of the semiconductor die <NUM>.

<FIG> illustrates a flow chart of a method for fabricating the AiP device shown in <FIG> in accordance with various embodiments of the present disclosure. This flowchart shown in <FIG> is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated in <FIG> may be added, removed, replaced, rearranged and repeated.

At step <NUM>, a via is formed in a semiconductor die. The semiconductor die comprises a plurality of radio frequency circuits and a plurality of vias. The semiconductor die further comprises a plurality of input/output pads formed on a front side of the semiconductor die. A plurality of conductive features is formed on a backside of the semiconductor die. The conductive features are electrically coupled to the plurality of radio frequency circuits through the vias formed in the semiconductor die.

At step <NUM>, a first dielectric layer is deposited over the backside of the semiconductor die. The first dielectric layer is a molding compound layer. The backside of the semiconductor die is fully covered by the first dielectric layer.

At step <NUM>, a first via is formed in the first dielectric layer. The formation of the first via comprises forming a first opening in the first dielectric layer and filling the first opening to form the first via a conductive material. In some embodiments, the conductive material is copper.

At step <NUM>, an antenna layer is formed on a first surface of the first dielectric layer. The antenna layer is formed by suitable semiconductor fabrication processes such as plating. The via in the semiconductor die, the conductive feature on the backside of the semiconductor and the first via in the first dielectric layer form an antenna feeding structure. The antenna feeding structure is configured to couple the plurality of radio frequency circuits to the antenna layer.

Claim 1:
A semiconductor device comprising:
a semiconductor die (<NUM>) comprising a radio frequency, RF, circuit embedded in a first dielectric layer (<NUM>); the first dielectric layer (<NUM>) being disposed over a first surface of the semiconductor die (<NUM>), the first surface being a backside of the semiconductor die (<NUM>) and over a second surface of the semiconductor die (<NUM>), the second surface being a front side of the semiconductor die (<NUM>) on an opposite side of the semiconductor die (<NUM>)
an antenna layer (<NUM>, <NUM>) disposed over a surface of the first dielectric layer (<NUM>); and
an antenna feeding structure coupling the antenna layer (<NUM>, <NUM>) to the radio frequency circuit of the semiconductor die (<NUM>), wherein:
the semiconductor die (<NUM>) comprises an opening comprising a via (<NUM>, <NUM>) in the semiconductor die (<NUM>); and
the antenna feeding structure comprises a first portion formed by the via (<NUM>, <NUM>) in the semiconductor die (<NUM>) and extending to the first surface of the semiconductor die (<NUM>), and a second portion (<NUM>, <NUM>) formed by a via (<NUM>, <NUM>) through the first dielectric layer; a redistribution structure (<NUM>, <NUM>, <NUM>) opposite the second surface of the semiconductor die (<NUM>), wherein the redistribution structure is electrically coupled to the radio frequency circuit using vias (<NUM>, <NUM>) through the first dielectric layer; and
a plurality of input/output connectors (<NUM>) electrically coupled to the semiconductor die (<NUM>) through the redistribution structure.