Patent Description:
Modem DRAM chips typically store one to eight gigabits (Gb) of data using deep sub-micron technology. Because of the high density and small feature size, rows of the memory are so physically close to other rows that the activation of a particular row can upset data stored in adjacent rows by changing the charge on the memory cell capacitors. In the past, these upsets were typically harmless because the memory cells are refreshed periodically. However, occasionally some memory access patterns cause certain rows to be activated and precharged so many times before the next refresh cycle that the memory cells in adjacent rows become corrupted and reverse logic state. After being corrupted, the original data is lost and cannot be restored in subsequent refresh cycles. As feature sizes become smaller, this problem, known as "row hammer", becomes harder to mitigate because the number of row activates required to cause the problem becomes smaller.

One known technique to address the data upset problem is known as targeted row refresh (TRR). In order to ensure that a DRAM row is not activated too many times within a refresh period, a memory controller places the DRAM into a TRR mode by setting certain mode register bits. In the TRR mode, successive activate and precharge commands are sent to the target row as well as the two physically adjacent rows. Once TRR mode is enabled, no other mode register commands are allowed until the TRR mode is completed. TRR mode is self-clearing and the mode register bit is set after the completion of TRR mode. While TRR allows the memory controller to avoid excessive activates to a certain row within a certain time period, it is entered by setting the mode register, which requires a substantial amount of time since all banks must be in the idle state before the controller can issue a Mode Register Set command. Document <CIT> (<NUM>-<NUM>-<NUM>), discloses a memory controller receiving and dispatching the memory requests in <FIG>; furthermore, it discloses activation counting and scheduling RFM commands based on <NUM> thresholds in <FIG>.

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word "coupled" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module. The memory controller includes a refresh control circuit that monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM module. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issues a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

A method includes receiving a plurality of memory access requests including memory reads and memory writes. Memory access commands for fulfilling the memory access requests are selectively placed in a memory interface queue and transmitted from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). At an activate counter, the method counts a rolling number of activate commands sent over the memory channel to a memory region. In response to the activate counter being above an intermediate management threshold value and at or below a maximum management threshold value, the method only issues a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

A data processing system includes a data processor, a data fabric coupled to the central processing unit, and a memory controller coupled to the data fabric for fulfilling memory requests from the central processing unit. The memory controller includes a command queue, a memory interface queue, an arbiter, and a refresh control circuit. The command queue has a first input for receiving memory access requests. The memory interface queue has an output for coupling to a memory channel adapted for coupling to at least one dynamic random access memory (DRAM) module. The arbiter is connected to the command queue for selecting entries from the command queue, and placing them in the memory interface queue causing them to be transmitted over the memory channel. The refresh control circuit is connected to the arbiter and operates to monitor an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

<FIG> illustrates in block diagram form an accelerated processing unit (APU) <NUM> and memory system <NUM> known in the prior art. APU <NUM> is an integrated circuit suitable for use as a processor in a host data processing system, and includes generally a central processing unit (CPU) core complex <NUM>, a graphics core <NUM>, a set of display engines <NUM>, a memory management hub <NUM>, a data fabric <NUM>, a set of peripheral controllers <NUM>, a set of peripheral bus controllers <NUM>, and a system management unit (SMU) <NUM>.

CPU core complex <NUM> includes a CPU core <NUM> and a CPU core <NUM>. In this example, CPU core complex <NUM> includes two CPU cores, but in other embodiments CPU core complex <NUM> can include an arbitrary number of CPU cores. Each of CPU cores <NUM> and <NUM> is bidirectionally connected to a system management network (SMN), which forms a control fabric, and to data fabric <NUM>, and is capable of providing memory access requests to data fabric <NUM>. Each of CPU cores <NUM> and <NUM> may be unitary cores, or may further be a core complex with two or more unitary cores sharing certain resources such as caches.

Graphics core <NUM> is a high performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, texture blending, and the like in a highly integrated and parallel fashion. Graphics core <NUM> is bidirectionally connected to the SMN and to data fabric <NUM>, and is capable of providing memory access requests to data fabric <NUM>. In this regard, APU <NUM> may either support a unified memory architecture in which CPU core complex <NUM> and graphics core <NUM> share the same memory space, or a memory architecture in which CPU core complex <NUM> and graphics core <NUM> share a portion of the memory space, while graphics core <NUM> also uses a private graphics memory not accessible by CPU core complex <NUM>.

Display engines <NUM> render and rasterize objects generated by graphics core <NUM> for display on a monitor. Graphics core <NUM> and display engines <NUM> are bidirectionally connected to a common memory management hub <NUM> for uniform translation into appropriate addresses in memory system <NUM>, and memory management hub <NUM> is bidirectionally connected to data fabric <NUM> for generating such memory accesses and receiving read data returned from the memory system.

Data fabric <NUM> includes a crossbar switch for routing memory access requests and memory responses between any memory accessing agent and memory management hub <NUM>. It also includes a system memory map, defined by basic input/output system (BIOS), for determining destinations of memory accesses based on the system configuration, as well as buffers for each virtual connection.

Peripheral controllers <NUM> include a universal serial bus (USB) controller <NUM> and a Serial Advanced Technology Attachment (SATA) interface controller <NUM>, each of which is bidirectionally connected to a system hub <NUM> and to the SMN bus. These two controllers are merely exemplary of peripheral controllers that may be used in APU <NUM>.

Peripheral bus controllers <NUM> include a system controller or "Southbridge" (SB) <NUM> and a Peripheral Component Interconnect Express (PCIe) controller <NUM>, each of which is bidirectionally connected to an input/output (I/O) hub <NUM> and to the SMN bus. I/O hub <NUM> is also bidirectionally connected to system hub <NUM> and to data fabric <NUM>. Thus for example a CPU core can program registers in USB controller <NUM>, SATA interface controller <NUM>, SB <NUM>, or PCIe controller <NUM> through accesses that data fabric <NUM> routes through I/O hub <NUM>. Software and firmware for APU <NUM> are stored in a system data drive or system BIOS memory (not shown) which can be any of a variety of non-volatile memory types, such as read-only memory (ROM), flash electrically erasable programmable ROM (EEPROM), and the like. Typically, the BIOS memory is accessed through the PCIe bus, and the system data drive through the SATA interface.

SMU <NUM> is a local controller that controls the operation of the resources on APU <NUM> and synchronizes communication among them. SMU <NUM> manages power-up sequencing of the various processors on APU <NUM> and controls multiple off-chip devices via reset, enable and other signals. SMU <NUM> includes one or more clock sources (not shown), such as a phase locked loop (PLL), to provide clock signals for each of the components of APU <NUM>. SMU <NUM> also manages power for the various processors and other functional blocks, and may receive measured power consumption values from CPU cores <NUM> and <NUM> and graphics core <NUM> to determine appropriate power states.

Memory management hub <NUM> and its associated physical interfaces (PHYs) <NUM> and <NUM> are integrated with APU <NUM> in this embodiment. Memory management hub <NUM> includes memory channels <NUM> and <NUM> and a power engine <NUM>. Memory channel <NUM> includes a host interface <NUM>, a memory channel controller <NUM>, and a physical interface <NUM>. Host interface <NUM> bidirectionally connects memory channel controller <NUM> to data fabric <NUM> over a serial presence detect link (SDP). Physical interface <NUM> bidirectionally connects memory channel controller <NUM> to PHY <NUM>, and conforms to the DDR PHY Interface (DFI) Specification. Memory channel <NUM> includes a host interface <NUM>, a memory channel controller <NUM>, and a physical interface <NUM>. Host interface <NUM> bidirectionally connects memory channel controller <NUM> to data fabric <NUM> over another SDP. Physical interface <NUM> bidirectionally connects memory channel controller <NUM> to PHY <NUM>, and conforms to the DFI Specification. Power engine <NUM> is bidirectionally connected to SMU <NUM> over the SMN bus, to PHYs <NUM> and <NUM> over the APB, and is also bidirectionally connected to memory channel controllers <NUM> and <NUM>. PHY <NUM> has a bidirectional connection to memory channel <NUM>. PHY <NUM> has a bidirectional connection memory channel <NUM>.

Memory management hub <NUM> is an instantiation of a memory controller having two memory channel controllers and uses a shared power engine <NUM> to control operation of both memory channel controller <NUM> and memory channel controller <NUM> in a manner that will be described further below. Each of memory channels <NUM> and <NUM> can connect to state-of-the-art DDR memories such as DDR version four (DDR4), low power DDR4 (LPDDR4), graphics DDR version five (gDDR5), and high bandwidth memory (HBM), and can be adapted for future memory technologies. These memories provide high bus bandwidth and high speed operation. At the same time, they also provide low power modes to save power for battery-powered applications such as laptop computers, and also provide built-in thermal monitoring.

Memory system <NUM> includes a memory channel <NUM> and a memory channel <NUM>. Memory channel <NUM> includes a set of dual inline memory modules (DIMMs) connected to a DDRx bus <NUM>, including representative DIMMs <NUM>, <NUM>, and <NUM> that in this example correspond to separate ranks. Likewise, memory channel <NUM> includes a set of DIMMs connected to a DDRx bus <NUM>, including representative DIMMs <NUM>, <NUM>, and <NUM>.

APU <NUM> operates as the central processing unit (CPU) of a host data processing system and provides various buses and interfaces useful in modern computer systems. These interfaces include two double data rate (DDRx) memory channels, a PCIe root complex for connection to a PCIe link, a USB controller for connection to a USB network, and an interface to a SATA mass storage device.

APU <NUM> also implements various system monitoring and power saving functions. In particular one system monitoring function is thermal monitoring. For example, if APU <NUM> becomes hot, then SMU <NUM> can reduce the frequency and voltage of CPU cores <NUM> and <NUM> and/or graphics core <NUM>. If APU <NUM> becomes too hot, then it can be shut down entirely. Thermal events can also be received from external sensors by SMU <NUM> via the SMN bus, and SMU <NUM> can reduce the clock frequency and/or power supply voltage in response.

<FIG> illustrates in block diagram form a memory controller <NUM> that is suitable for use in an APU like that of <FIG>. Memory controller <NUM> includes generally a memory channel controller <NUM> and a power controller <NUM>. Memory channel controller <NUM> includes generally an interface <NUM>, a memory interface queue <NUM>, a command queue <NUM>, an address generator <NUM>, a content addressable memory (CAM) <NUM>, replay control logic <NUM> including a replay queue <NUM>, a refresh logic block <NUM>, a timing block <NUM>, a page table <NUM>, an arbiter <NUM>, an error correction code (ECC) check circuit <NUM>, an ECC generation block <NUM>, and a data buffer <NUM>.

Interface <NUM> has a first bidirectional connection to data fabric <NUM> over an external bus, and has an output. In memory controller <NUM>, this external bus is compatible with the advanced extensible interface version four specified by ARM Holdings, PLC of Cambridge, England, known as "AXI4", but can be other types of interfaces in other embodiments. Interface <NUM> translates memory access requests from a first clock domain known as the FCLK (or MEMCLK) domain to a second clock domain internal to memory controller <NUM> known as the UCLK domain. Similarly, memory interface queue <NUM> provides memory accesses from the UCLK domain to a DFICLK domain associated with the DFI interface.

Address generator <NUM> decodes addresses of memory access requests received from data fabric <NUM> over the AXI4 bus. The memory access requests include access addresses in the physical address space represented in a normalized format. Address generator <NUM> converts the normalized addresses into a format that can be used to address the actual memory devices in memory system <NUM>, as well as to efficiently schedule related accesses. This format includes a region identifier that associates the memory access request with a particular rank, a row address, a column address, a bank address, and a bank group. On startup, the system BIOS queries the memory devices in memory system <NUM> to determine their size and configuration, and programs a set of configuration registers associated with address generator <NUM>. Address generator <NUM> uses the configuration stored in the configuration registers to translate the normalized addresses into the appropriate format. Command queue <NUM> is a queue of memory access requests received from the memory accessing agents in APU <NUM>, such as CPU cores <NUM> and <NUM> and graphics core <NUM>. Command queue <NUM> stores the address fields decoded by address generator <NUM> as well other address information that allows arbiter <NUM> to select memory accesses efficiently, including access type and quality of service (QoS) identifiers. CAM <NUM> includes information to enforce ordering rules, such as write after write (WAW) and read after write (RAW) ordering rules.

Error correction code (ECC) generation block <NUM> determines the ECC of write data to be sent to the memory. ECC check circuit <NUM> checks the received ECC against the incoming ECC.

Replay queue <NUM> is a temporary queue for storing selected memory accesses picked by arbiter <NUM> that are awaiting responses, such as address and command parity responses. Replay control logic <NUM> accesses ECC check circuit <NUM> to determine whether the returned ECC is correct or indicates an error. Replay control logic <NUM> initiates and controls a recovery sequence in which accesses are replayed in the case of a parity or ECC error of one of these cycles. Replayed commands are placed in the memory interface queue <NUM>.

Refresh control logic <NUM> includes state machines for various powerdown, refresh, and termination resistance (ZQ) calibration cycles that are generated separately from normal read and write memory access requests received from memory accessing agents. For example, if a memory rank is in precharge powerdown, it must be periodically awakened to run refresh cycles. Refresh control logic <NUM> generates refresh commands periodically and in response to designated conditions to prevent data errors caused by the leaking of charge off storage capacitors of memory cells in DRAM chips. The memory regions are memory banks in some embodiments, and memory sub-banks in other embodiments as further discussed below. Refresh control logic <NUM> also generates refresh commands, which include both refresh (REF) commands and refresh management (RFM) commands, in which the RFM commands direct the memory to perform refresh functions for mitigating row hammer issues as further described below. In addition, refresh control logic <NUM> periodically calibrates ZQ to prevent mismatch in on-die termination resistance due to thermal changes in the system.

Arbiter <NUM> is bidirectionally connected to command queue <NUM> and is the heart of memory channel controller <NUM>. Arbiter <NUM> improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus. Arbiter <NUM> uses timing block <NUM> to enforce proper timing relationships by determining whether certain accesses in command queue <NUM> are eligible for issuance based on DRAM timing parameters. For example, each DRAM has a minimum specified time between activate commands, known as "tRC". Timing block <NUM> maintains a set of counters that determine eligibility based on this and other timing parameters specified in the JEDEC specification, and is bidirectionally connected to replay queue <NUM>. Page table <NUM> maintains state information about active pages in each bank and rank of the memory channel for arbiter <NUM>, and is bidirectionally connected to replay queue <NUM>. Arbiter <NUM> includes an activate counter <NUM>, which includes a counter for each memory region which counts a rolling number of activate commands sent over the memory channel to a memory region. To provide a rolling count, each activate command is counted, but the coutner is reduced as described below when refresh commands or refresh management commands are issued for the memory region. Arbiter <NUM> is bidirectionally connected to refresh control logic <NUM> to monitor refresh commands and direct refresh activities.

In response to write memory access requests received from interface <NUM>, ECC generation block <NUM> computes an ECC according to the write data. Data buffer <NUM> stores the write data and ECC for received memory access requests. It outputs the combined write data/ECC to memory interface queue <NUM> when arbiter <NUM> picks the corresponding write access for dispatch to the memory channel.

Power controller <NUM> generally includes an interface <NUM> to an advanced extensible interface, version one (AXI), an advanced peripheral bus (APB) interface <NUM>, and a power engine <NUM>. Interface <NUM> has a first bidirectional connection to the SMN, which includes an input for receiving an event signal labeled "EVENT_n" shown separately in <FIG>, and an output. APB interface <NUM> has an input connected to the output of interface <NUM>, and an output for connection to a PHY over an APB. Power engine <NUM> has an input connected to the output of interface <NUM>, and an output connected to an input of memory interface queue <NUM>. Power engine <NUM> includes a set of configuration registers <NUM>, a microcontroller (µC) <NUM>, a self refresh controller (SLFREF/PE) <NUM>, and a reliable read/write timing engine (RRW/TE) <NUM>. Configuration registers <NUM> are programmed over the AXI bus, and store configuration information to control the operation of various blocks in memory controller <NUM>. Accordingly, configuration registers <NUM> have outputs connected to these blocks that are not shown in detail in <FIG>. Self refresh controller <NUM> is an engine that allows the manual generation of refreshes in addition to the automatic generation of refreshes by refresh control logic <NUM>. Reliable read/write timing engine <NUM> provides a continuous memory access stream to memory or I/O devices for such purposes as DDR interface maximum read latency (MRL) training and loopback testing.

Memory channel controller <NUM> includes circuitry that allows it to pick memory accesses for dispatch to the associated memory channel. In order to make the desired arbitration decisions, address generator <NUM> decodes the address information into predecoded information including rank, row address, column address, bank address, and bank group in the memory system, and command queue <NUM> stores the predecoded information. Configuration registers <NUM> store configuration information to determine how address generator <NUM> decodes the received address information. Arbiter <NUM> uses the decoded address information, timing eligibility information indicated by timing block <NUM>, and active page information indicated by page table <NUM> to efficiently schedule memory accesses while observing other criteria such as quality of service (QoS) requirements. For example, arbiter <NUM> implements a preference for accesses to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank. In particular during normal operation, arbiter <NUM> normally keeps pages open in different banks until they are required to be precharged prior to selecting a different page. Arbiter <NUM>, in some embodiments, determines eligibility for command selection based on at least on respective values of activate counter <NUM> for target memory regions of the respective commands.

<FIG> is a flow diagram of a process <NUM> for handling refresh management according to some embodiments. Process <NUM> is performed by refresh control logic <NUM> (<FIG>) in some embodiments, and or by memory controller digital logic or a controller having similar functionality in other embodiments. In this embodiment, refresh control logic <NUM> is connected to arbiter <NUM> and operates to monitor an activate counter <NUM>, which counts a rolling number of activate commands sent over the memory channel to a memory region as shown at block <NUM>. The memory regions are memory banks in some embodiments, but are memory sub-banks in other embodiments as further discussed below. Process <NUM> is repeated for each memory region. At block <NUM>, process <NUM> manages the counter by decrementing the counter by a first designated amount if a refresh (REF) command issues to the respective monitored region. Block <NUM> accounts for "per bank" REF commands which are directed to particular memory banks, and "all bank" REF commands which are directed to all the banks in a particular memory rank. For example, an activate counter for a memory bank is decremented by <NUM> in response to an REF command being issued to the memory bank in one embodiment, whether it is a per bank REF or an all bank REF. As such, an all bank REF command causes multiple activate counters to be decremented, for all the affected banks. Process <NUM> also accounts for issuance of refresh management (RFM) commands by decrementing the counter by a second designated amount when an RFM command issues to the memory region, as shown at block <NUM>. For example, the activate counter for a memory banks is decremented by <NUM> in response to an RFM command issuing to the memory bank in one embodiment.

While activate counter <NUM> is updated by blocks <NUM>, <NUM>, and <NUM>, the value is monitored by process <NUM> as shown at blocks <NUM>-<NUM>, which take various refresh management actions in addition to the normal REF commands which issue to the memory region. Generally, process <NUM> works to provide a refresh command of some type (REF or RFM), while preferring REF commands created by periodic refresh functions of refresh control logic <NUM> (<FIG>). This preference is accomplished by, in response to the activate counter being above an intermediate management threshold value and below a maximum management threshold value, determining if a pending refresh (REF) command is currently held at the refresh control circuit for the memory region and, if not, causing a refresh management (RFM) command to be sent to the memory region. If so, the pending REF command is allowed to issue with no RFM command being issued. In response to the activate counter being at or above the maximum management threshold, the process causes an RFM command to be scheduled for the memory region, and prevents any new activate commands from being scheduled to the memory region until the RFM command is scheduled or a pending REF command is scheduled. Different logical processes are used to accomplish this in different embodiments.

In the depicted process <NUM>, block <NUM> monitors the value of activate counter <NUM>. If the value is at or above a maximum management threshold at block <NUM>, process <NUM> goes to block <NUM> where it checks if an REF command is pending at arbiter <NUM> for the memory region. Block <NUM> checks for "per bank" REF commands and "all bank" REF commands that apply to the bank in question. If one of either type REF commands is pending which covers the bank in question, the process goes to block <NUM> where it signals the arbiter to prioritize the pending REF command to require it to be scheduled and issued. If no pending REF command is found at block <NUM>, process <NUM> goes to block <NUM>, where it creates a new RFM command to be scheduled by the arbiter. After either of blocks <NUM> or <NUM>, process <NUM> goes to block <NUM> where it prevents any activate commands being scheduled at arbiter <NUM> until either the newly-created RFM command is scheduled or a pending REF is scheduled. In some alternative embodiments, the refresh control circuit is further operable to, in response to a designated condition of activate counter <NUM> such as crossing the maximum threshold at block <NUM>, cause a refresh rate to double for the memory region until the designated condition is remedied. Such a rate increase may be performed in addition to or instead of creating an RFM command at block <NUM>. In some embodiments, the refresh control logic is configurable to include the rate increase.

If activate counter <NUM> is not above the maximum management threshold at block <NUM>, block <NUM> checks if activate counter <NUM> is at or above the intermediate management threshold. If not, block <NUM> simply returns to block <NUM> to continue monitoring the activate counter. If so, process <NUM> goes to block <NUM> where it checks if an REF command is pending at arbiter <NUM> for the memory region. Block <NUM> checks for "per bank" REF commands and "all bank" REF commands that apply to the bank in question. If one of either type REF commands is pending which covers the bank in question, the process goes to block <NUM> where it signals the arbiter to prioritize the pending REF command to require it to be scheduled and issued. If not, process <NUM> goes to block <NUM>, where it creates a new RFM command to be scheduled by the arbiter.

While the depicted process blocks are shown in order, this order is not limiting, and the depicted logical functionality, is typically accomplished by various digital logic circuits operating in parallel. In various embodiments, digital logic circuits perform the activate counter monitoring in various ways, such as by responding to changes in the activate counter or repeatedly comparing the activate counter value to one or both of the intermediate threshold value and the maximum threshold value. The monitoring at block <NUM> continues after each depicted branch of logical functionality is finished.

The intermediate management threshold and the maximum management threshold are preferably adjustable to allow the memory controller to work well with different DRAM modules from various manufacturers, for which REF and RFM commands often vary in their implementation. In some embodiments, the intermediate management threshold and the maximum management threshold are allowed to be set to the same value to implement a simplified version of the monitoring process. Setting these two threshold values to be equal preferably functions to disable the maximum management threshold logic (block <NUM>), and allow the logic implementing the intermediate management threshold comparison (blocks <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) to handle situations in which the counter exceeds the equal threshold values. Such implementations thereby function to prefer pending REF commands when they exist rather than creating new RFM commands. This preference often improves efficiency because REF commands are often faster than RFM commands among various DRAM module implementations. In other implementations, only the intermediate management threshold is used.

In various embodiments, the memory region for which an activate counter is monitored is a memory bank or a sub-bank. When the memory region is a sub-bank of a memory bank, and the refresh control circuit is operable to monitor multiple activate counters for respective multiple sub-banks of the memory bank and apply REF and RFM commands at the bank level. Such commands cause an update of all the sub-bank activate counters for sub-banks within the bank. Similarly, all bank REF commands cause an update of sub-bank activate counters for all sub-banks within the respective rank. As such, process <NUM> is operable to monitor the activate counters at a granularity level of the multiple sub-banks, and allow or cause the REF and RFM commands to issue at a granularity level of the selected memory bank. The refresh control circuit may be configurable to provide activate counters for memory banks or sub-banks, with the refresh management process also adjustable to account for banks or sub-banks.

<FIG> illustrates in block diagram form a flexible address decoder <NUM> according to some embodiments. Flexible address decoder <NUM> is included in address generator <NUM> (<FIG>) for some embodiments in order to spread consecutive memory addresses across the multiple sub-banks and provide memory address bits for addressing the multiple sub-banks. Flexible address decoder <NUM> receives an incoming logical address ADDR associated with the memory command being decoded, and applies a hash function or other suitable mathematical spreading function which maps the address to a physical memory location in the respective DRAM module by mapping the incoming logical address bits to outgoing physical address bits in the DRAM module. As depicted, in this version the outgoing address bits include one or more RANK bits selecting a memory rank, one or more BANK bits selecting a memory bank, one or more SUB-BANK bits selecting a sub-bank, one or more ROW bits selecting a row, and one or more COL bits selecting a column.

<FIG> illustrates in diagram form a process <NUM> of mapping logical memory addresses to physical memory locations using a flexible address decoder such as that of <FIG>. Process <NUM> helps to mitigate "row hammer" issues by spreading consecutive logical addresses to rows across different sub-banks within a memory bank. As depicted, a memory rank of the DRAM module includes a number of memory banks, BANK <NUM> through BANK n. In this embodiment, four sub-banks are used within each bank of the DRAM module, SUB-BANK <NUM>, SUB-BANK <NUM>, SUB-BANK <NUM>, and SUB-BANK <NUM>. In other embodiments, two sub-banks may be used, or more than four sub-banks may be used. A range of sequential logical memory locations A through D are depicted, which are shown by the arrow as being mapped according to flexible address decoding to different sub-banks within a bank. The refresh management techniques described herein are used, in some embodiments, in combination with an address mapping process like that of <FIG>, providing activate counters for each sub-bank rather than at the memory bank level.

<FIG> illustrates in block diagram form a circuit <NUM> for performing refresh management of memory sub banks according to some embodiments. Circuit <NUM> implements the refresh management techniques discussed above with respect to <FIG>, and provides activate counting at a sub-bank level of granularity. In this example embodiment, the memory bank for which refresh management is conducted includes four sub-banks. Activate (ACT) commands for each sub-bank, SUB-BANK <NUM> through SUB-BANK <NUM>, are tracked with a respective activate counter <NUM> for each sub-bank as depicted. A refresh management circuit <NUM> is provided for each sub-bank to perform the refresh management process such as the process of <FIG>. While in this embodiment a separate refresh management circuit <NUM> is provided for each sub bank, in other embodiments a single refresh management circuit may manage all of the sub-banks by cycling through them to check the relevant conditions.

Each refresh management circuit <NUM> has an input for the respective activate counter <NUM> value, and additional inputs for adjustable configuration values such as the depicted management threshold input "MGMNT THRESHOLD", through which adjustable values such as the intermediate management threshold and the maximum management threshold are provided. The outputs of the four refresh management circuit <NUM> signal whether an RFM commands should issue for the respective sub-bank according to the refresh management process employed, such as, for example, the process of <FIG>. These four outputs are fed to a four-input OR gate <NUM>, which produces an output "BANK RFM" indicating a RFM command should be issued for the memory bank being monitored. Circuit <NUM> thereby provides refresh management at the sub-bank granularity level, but activates RFM commands at the granularity level of a memory bank.

Memory controller <NUM> of <FIG> or any portions thereof, such as arbiter <NUM> and refresh control circuit <NUM>, may be described or represented by a computer accessible data structure in the form of a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate integrated circuits. For example, this data structure may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including integrated circuits. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce the integrated circuits. Alternatively, the database on the computer accessible storage medium may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data.

Claim 1:
An apparatus comprising:
a memory controller, comprising:
a command queue having a first input for receiving memory access requests;
a memory interface queue having an output for coupling to a memory channel adapted for coupling to at least one dynamic random access memory, DRAM;
an arbiter coupled to the command queue for selecting entries from the command queue, and placing them in the memory interface queue causing them to be transmitted over the memory channel; and
a refresh control circuit coupled to the arbiter and operable to:
monitor an activate counter which counts a number of activate commands sent over the memory channel to a memory region; and
in response to the activate counter being above an intermediate management threshold value and at or below a maximum management threshold value, only issue a refresh management, RFM, command if there is no refresh, REF, command currently held at the refresh control circuit for the memory region.