Patent Description:
The present disclosure is generally related to voltage droop control.

Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless telephones such as mobile and smart phones, tablets and laptop computers that are small, lightweight, and easily carried by users. These devices can communicate voice and data packets over wireless networks. Further, many such devices incorporate additional functionality such as a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such devices can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these devices can include significant computing capabilities.

As computing capabilities increase, power usage may also increase. Power usage may be reduced by deactivating components of an electronic device that are not in use. When components are activated, in-rush conditions may cause a power supply voltage to drop below a target voltage level. The components may be activated sequentially with a delay in between activation of each component. For example, a signal may be passed from a particular component via a chain of inverters to a subsequent component. The chain of inverters may cause the delay between activation of the particular component and activation of the subsequent component. The power supply voltage may partially recover during the delay. The delay is dependent on operating conditions (e.g., voltage, temperature, or both). Under particular operating conditions, the delay may be too short for the power supply voltage to recover to a sufficient level before the subsequent component is activated, and the power supply voltage may drop below the target voltage level upon activation of the subsequent component. Increasing a number of inverters in the chain of inverters so that the delay is long enough to account for a wide range of operating conditions may create unnecessary delay during normal operating conditions.

<CIT> discloses an apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

<CIT> discloses a circuit having a section provided in stand-by or active operating modes. Switches e.g. metal oxide semiconductor transistors, electrically connect a supply line with a supply line. A control unit is designed in such a manner that the switches are controlled based on a ground potential determined by a determination unit when changing the section from the stand-by mode into active operating mode. An independent claim is also included for a method of switching an operating mode of a part of a circuit from a stand-by mode into an active operating mode.

<CIT> discloses a integrated circuit with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.

Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.

Referring to <FIG>, a particular illustrative aspect of a device is disclosed and generally designated <NUM>. For example, the device <NUM> may include or correspond to at least one of a communications device, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a mobile device, a computer, a decoder, or a set top box. The device <NUM> includes a first component <NUM> coupled to a second component <NUM>. The first component <NUM>, the second component <NUM>, or both, may correspond to a memory component or a processor component. The device <NUM> includes an external power supply <NUM> coupled to the first component <NUM>, the second component <NUM>, or both.

The first component <NUM> includes a first voltage droop controller <NUM> and a first internal power supply <NUM>. The first voltage droop controller <NUM> is coupled to a first input <NUM> that is configured to receive a signal, such as a first voltage <NUM>. The first component <NUM> may be activated (e.g., powered up) responsive to the first voltage <NUM> corresponding to a first logical value and may be deactivated (e.g., powered down) responsive to the first voltage <NUM> corresponding to a second logical value. For purposes of illustration, the first logical value is generally described herein as corresponding to a high voltage (e.g., a "<NUM>"), and the second logical value is generally described herein as corresponding to a low voltage (e.g., a "<NUM>"). However, such descriptions are merely for illustration and are not limiting.

The first component <NUM> also includes a first output <NUM> coupled to a second input <NUM> of the second component <NUM>. The first output <NUM> provides a second voltage <NUM> to the second input <NUM> of the second component <NUM> based on a voltage level of the first internal power supply <NUM>. The first voltage droop controller <NUM> includes a voltage detector <NUM> that is coupled to the first internal power supply <NUM>. A logical value of the second voltage <NUM> is determined by the first voltage droop controller <NUM> based on a voltage level of the first internal power supply <NUM> detected by the voltage detector <NUM>.

The first internal power supply <NUM> is configured to be charged by the external power supply <NUM> when the first voltage <NUM> corresponds to the first logical value. The first internal power supply <NUM> is not charged by the external power supply <NUM> when the first voltage <NUM> corresponds to the second logical value. Additionally, the first voltage droop controller <NUM> is configured to set a logical value of the second voltage <NUM> based on whether a first voltage level of the first internal power supply <NUM> satisfies a second voltage level (e.g., a target voltage level), as described further below.

The voltage detector <NUM> may be activated in response to the first input <NUM> receiving the first voltage <NUM> corresponding to the first logical value. The voltage detector <NUM> may generate an output that indicates whether the first voltage level of the first internal power supply <NUM> is greater than or equal to the second voltage level (e.g., the target voltage level associated with the first component <NUM>). To illustrate, the voltage detector <NUM> may generate a first output to indicate that the first voltage level satisfies the second voltage level while the first input <NUM> is receiving the first voltage <NUM> corresponding to the first logical value. The voltage detector <NUM> may generate a second output to indicate that the first voltage level fails to satisfy the second voltage level. The voltage detector <NUM> may also generate the second output when the first input <NUM> receives the first voltage <NUM> corresponding to the second logical value.

The first voltage droop controller <NUM> is configured to provide the second voltage <NUM> based on the output of the voltage detector <NUM>, as described further below. For example, the first voltage droop controller <NUM> may set a value of the second voltage <NUM> to the first logical value or the second logical value depending on the output of the voltage detector.

The second component <NUM> may include a second voltage droop controller <NUM> and includes a second internal power supply <NUM>. The second voltage droop controller <NUM> is coupled to the second input <NUM> and configured to receive the second voltage <NUM> from the first voltage droop controller <NUM>. The second internal power supply <NUM> is configured to be charged by the external power supply <NUM> in response to the second voltage droop controller <NUM> receiving the second voltage <NUM> corresponding to the first logical value. The second internal power supply <NUM> may not be charged by the external power supply <NUM> while the second voltage <NUM> corresponds to the second logical value.

Although the device <NUM> is illustrated as including two components forming a charging sequence. In some implementations, the device <NUM> may include more than two components in the charging sequence. For example, in some implementations, an output (not illustrated) of the second voltage droop controller <NUM> may be coupled to another component (e.g., a next component in the charging sequence) of the device <NUM> to provide another voltage to the next component. In these implementations, a logical value output by the second voltage droop controller <NUM> via the third voltage may control activation of the next component. To illustrate, the second voltage droop controller <NUM> may output the third voltage corresponding to the first logical value while the second voltage droop controller <NUM> is receiving the second voltage <NUM> corresponding to the first logical value and when a voltage level of the second internal power supply <NUM> is greater than or equal to a particular voltage level (e.g., a target voltage level associated with the second component <NUM>). Likewise, the second voltage droop controller <NUM> may output the third voltage corresponding to the second logical value if the second voltage droop controller <NUM> is receiving the second voltage <NUM> corresponding to the second logical value or if the voltage level of the second internal power supply <NUM> is less than the particular voltage level.

During operation, a processor or controller (not illustrated) of the device <NUM> may send a signal that causes the device <NUM> to enter a sleep (or standby) mode (e.g., a low-power operating mode). Based on the signal, the first component <NUM> may receive the first voltage <NUM>, and the first voltage <NUM> may correspond to the second logical value. Responsive to the first voltage <NUM> corresponding to the second logical value, one or more components of the device <NUM> may enter and remain in a sleep mode. When the device <NUM> is in the sleep mode, the first internal power supply <NUM> may be decoupled from the external power supply <NUM> and may discharge (or remain in an uncharged or reduced voltage state). For example, the first voltage droop controller <NUM> may selectively couple or decouple the first internal power supply <NUM> to the external power supply <NUM> based on the logical value of the first voltage <NUM>.

Additionally, the first voltage droop controller <NUM> may output the second voltage <NUM> corresponding to the second logical value to the second component <NUM>. The second voltage droop controller <NUM> may selectively couple or decouple the second internal power supply <NUM> to the external power supply <NUM> based on the logical value of the second voltage <NUM>. For example, the second internal power supply <NUM> may be decoupled from the external power supply <NUM> and may discharge (or remain in an uncharged or reduced voltage state) when the second voltage <NUM> corresponds to the second logical value.

The processor or controller (not illustrated) of the device <NUM> may send a second signal that causes the device <NUM> to enter an active mode (e.g., a high-power operating mode). For example, the device <NUM> may transition to the active mode in response to receiving a user input. Based on the second signal, the first voltage droop controller <NUM> may receive the first voltage <NUM> corresponding to the first logical value, and the first internal power supply <NUM> may begin to be charged by the external power supply <NUM>. Due to transitioning from an uncharged or low-voltage state, a first voltage level of the first internal power supply <NUM> may initially be less than a particular voltage level that indicates a charged or mostly-charged state of the first internal power supply <NUM> (e.g., a second voltage level). While the first voltage level is less than the second voltage level, the first voltage droop controller <NUM> may output the second voltage <NUM> corresponding to the second logical value. As the first internal power supply <NUM> charges, the first voltage level may rise to be greater than or equal to the second voltage level. The first voltage droop controller <NUM> outputs the second voltage <NUM> corresponding to the first logical value when the first voltage level is greater than or equal to the second voltage level. When the second voltage droop controller <NUM> detects that the second voltage <NUM> corresponds to the first logical value, the second internal power supply <NUM> begins to be charged by the external power supply <NUM>.

Thus, the device <NUM> may reduce voltage droop at the external power supply by delaying activation of the second component <NUM> until the voltage level of the first internal power supply <NUM> satisfies a threshold (e.g., the second voltage level). The delay may accommodate a wide range of operating conditions, without being unnecessarily long during normal operating conditions.

The device <NUM> is illustrated for convenience and the particular illustrated details are not limiting. For example, in other aspects, the device <NUM> may include more components or fewer components than illustrated in <FIG>. As another example, operations described as being performed by a particular component of the device <NUM> may be performed by multiple components of the device <NUM>. Although the first component <NUM> is described as being activated based on a logical value of the first voltage <NUM>, in other implementations, the first component <NUM> may be activated based on a different signal, a set of signals, or a different logical value. Similarly, although the second component <NUM> is described as being activated based on a logical value of the second voltage <NUM>, in other implementations, the second component <NUM> may be activated based on a different signal, a set of signals, or a different logical value. Further, the first component <NUM> may be activated based on a different criterion than the second component <NUM>. To illustrate, the first component <NUM> may be activated when the first voltage <NUM> corresponds to the first logical value, and the second component <NUM> may be activated when the second voltage <NUM> corresponds to the second logical value.

Referring to <FIG>, a timing diagram is shown and generally designated <NUM>. In a particular aspect, the timing diagram <NUM> illustrates operation of the device <NUM> of <FIG>. For example, the timing diagram <NUM> illustrates the first voltage <NUM>, the second voltage <NUM>, and the first voltage level of the first internal power supply <NUM> at various times during operation of the device <NUM>.

In <FIG>, the device <NUM> is in an active mode (e.g., a higher-power mode) prior to a time t0, in a sleep mode (e.g., a lower-power mode) from the time t0 to a time t1, and in the active mode subsequent to the time t1. Additionally, in <FIG>, the first logical value is represented by a high voltage level, and the second logical value is represented by a low voltage level. For example, the first voltage <NUM> corresponds to the first logical value when the first voltage <NUM> is high and corresponds to the second logical value when the first voltage <NUM> is low. Likewise, in this example, the second voltage <NUM> corresponds to the first logical value when the second voltage <NUM> is high and corresponds to the second logical value when the second voltage <NUM> is low. Thus, in the timing diagram <NUM>, the first voltage <NUM> corresponds to the first logical value before time t0 and corresponds to the second logical value after the time t0 and before the time t1.

While the first voltage <NUM> corresponds to the first logical value and the first internal power supply <NUM> is charged (e.g., has a voltage level greater than or equal to a particular voltage level, such as a voltage level of the external power supply <NUM>), the second voltage <NUM> output by the first voltage droop controller <NUM> corresponds to the first logical value. While the second voltage <NUM> corresponds to the first logical value, the second internal power supply <NUM> of the second component <NUM> of <FIG> is charged by the external power supply <NUM>.

When the device <NUM> enters the sleep mode (e.g., at or about time t0), the first voltage <NUM> received by the first voltage droop controller <NUM> may correspond to the second logical value. When the first voltage <NUM> corresponds to the second logical value, the first internal power supply <NUM> may be decoupled from the external power supply <NUM>. The first internal power supply <NUM> may begin to discharge at about the time t0 (e.g., due to leakage currents in the first component <NUM>). Additionally, when the first voltage <NUM> corresponds to the second logical value, the first output <NUM> may provide the second voltage <NUM> corresponding to the second logical value to the second component <NUM> of <FIG>. Based on the second voltage <NUM> corresponding to the second logical value, the second internal power supply <NUM> of the second component <NUM> of <FIG> may be decoupled from the external power supply <NUM>.

When the device <NUM> transitions from the sleep mode to the active mode, at or about the time t1, the first voltage <NUM> may transition from corresponding to the second logical value to corresponding to the first logical value. Based on the first voltage <NUM> corresponding to the first logical value, the first internal power supply <NUM> may be coupled to the external power supply <NUM> to be charged. As the first internal power supply <NUM> charges, the voltage level of the first internal power supply <NUM> may increase to the particular voltage level (e.g., at or about the time t2). Based on the voltage level of the first internal power supply <NUM> satisfying a threshold (e.g., being equal to or greater than the particular voltage level), the second voltage <NUM> may transition from corresponding to the second logical value to corresponding to the first logical value. Based on the second voltage <NUM> corresponding to the first logical value, the second internal power supply <NUM> of the second component <NUM> of <FIG> may be coupled to the external power supply <NUM> to be charged.

The first voltage droop controller <NUM> may thus enable a delay <NUM> between activation of the first component <NUM> (e.g., at about the time t1 when the first voltage <NUM> transitions to corresponding to the first logical value) and activation of the second component <NUM> (e.g., at about the time t2 when the second voltage <NUM> transitions to corresponding to the first logical value). The delay <NUM> may enable a voltage of the first internal power supply <NUM> to recover to a sufficient level before the second component <NUM> of <FIG> begins charging.

Referring to <FIG>, a particular implementation of the first component <NUM> is shown. The second component <NUM> of <FIG> may include similar circuitry to the circuitry described below with reference to <FIG>. Thus, the details of various aspects and operations associated with the first component <NUM> described with reference to <FIG> may also apply to the second component <NUM> or to other components of a charging sequence of the device <NUM>.

In <FIG>, the first component <NUM> includes the first voltage droop controller <NUM> and the first internal power supply <NUM>. The first voltage droop controller <NUM> includes power supply charging circuitry <NUM>, voltage detection circuitry <NUM>, and output signal circuitry <NUM>. The power supply charging circuitry <NUM> may be coupled to the first input <NUM>, to the external power supply <NUM>, to the first internal power supply <NUM>, to the voltage detection circuitry <NUM>, and to a core unit <NUM> (represented by a capacitance in <FIG>). The voltage detection circuitry <NUM> is coupled to the first internal power supply <NUM> and to the output signal circuitry <NUM>. The output signal circuitry <NUM> is coupled, via the first output <NUM>, to a second component (not illustrated), such as the second component <NUM> of <FIG>.

In a particular aspect, the first voltage droop controller <NUM> includes a set of 'header' transistors to couple the first internal power supply <NUM> to the external power supply <NUM>. For example, in <FIG>, the power supply charging circuitry <NUM> includes a first transistor <NUM> (e.g., a p-channel field-effect transistor (PFET)) and a second transistor <NUM>. Gates of the first transistor <NUM> and the second transistor <NUM> may be coupled to the first input <NUM> via an inverter <NUM>. The first transistor <NUM>, the second transistor <NUM>, or both, may have a source that is coupled to the external power supply <NUM>. A drain of the first transistor <NUM>, the second transistor <NUM>, or both, may be coupled, via the first internal power supply <NUM> (e.g., a core_vdd grid), to the core unit <NUM>. In <FIG>, when the first transistor <NUM>, the second transistor <NUM>, or both, are activated, the core unit <NUM> is electrically connected to the external power supply <NUM> to enable charging of the core unit <NUM>.

In a particular aspect, the power supply charging circuitry <NUM> may be configured to have a delay between a first time at which the first transistor <NUM> (or a first set of header transistors) is activated and a second time at which the second transistor <NUM> (or second set of header transistors) is activated. The delay may reduce voltage droop of the external power supply <NUM> as compared to a voltage droop caused by the second transistor <NUM> being activated at the same time as the first transistor <NUM>. The first transistor <NUM> may have different characteristics (such as resistance, a threshold voltage, etc.) than the second transistor <NUM>. Additionally, although only two header transistors are illustrated in <FIG>, the power supply charging circuitry <NUM> may include more than two header transistors.

The voltage detection circuitry <NUM> in <FIG> includes an inverter <NUM>, a third transistor <NUM> (e.g., an n-channel field-effect transistor (NFET)), a fourth transistor <NUM> (e.g., a passgate NFET), and a voltage detector <NUM> (e.g., a Schmitt trigger). The third transistor <NUM> has a source coupled to a power supply (Vss) <NUM>. The third transistor is configured to operate as a pull-down device coupled to an input of the voltage detector <NUM> and responsive to the output of the inverter <NUM>. The fourth transistor <NUM> is responsive to the output of the inverter <NUM> to selectively connect or disconnect the first internal power supply <NUM> to the input of the voltage detector <NUM>.

The output of the inverter <NUM> may be coupled to the third transistor <NUM> to selectively activate the third transistor <NUM>. While the third transistor <NUM> is activated, the input of the voltage detector <NUM> is discharged or coupled to a ground voltage (e.g., to Vss <NUM>). While the third transistor <NUM> is deactivated, the fourth transistor <NUM> may selectively connect the first internal power supply <NUM> to the input of the voltage detector <NUM>. The voltage detector <NUM> may be configured to indicate whether a voltage at the input of the voltage detector <NUM> is greater than or equal to a particular voltage level (e.g., <NUM> volts). For example, the voltage detector <NUM> may be configured to output a voltage corresponding to a particular logical value (e.g., <NUM>) to indicate that the input of the voltage detector <NUM> is greater than or equal to the particular voltage level (e.g., a target voltage) and to output a voltage corresponding to a second particular logical value (e.g., <NUM>) to indicate that the input of the voltage detector <NUM> is less than the particular voltage level. In a particular aspect, the voltage detector <NUM> is configured to compare the input of the voltage detector <NUM> to multiple different target voltages (such as a high target voltage and low target voltage) to reduce erroneous outputs due to noise at the input. For example, the voltage detector <NUM> may be configured to continue to output the first logical value as the input to the voltage detector <NUM> falls from at or above the high target voltage to the low target voltage and to output the second logical value when the input falls below the low target voltage. As another example, the voltage detector <NUM> may be configured to continue to output the second logical value as the input to the voltage detector <NUM> rises from below the low target voltage to the high target voltage and to output the first logical value when the input rises above the high target voltage.

The output signal circuitry <NUM> includes output selection circuitry (such as an inverter, an OR gate, and an AND gate) and a delay buffer <NUM>. An output of the delay buffer <NUM> may be coupled to the first output <NUM>. The output signal circuitry <NUM> may also include a bypass input <NUM>, which may be used to bypass (e.g., override) the functionality of the voltage detection circuitry <NUM>.

There may be a delay between a change in the input of the delay buffer <NUM> and a corresponding change in the output (e.g., the first output <NUM>) of the delay buffer <NUM>. The delay of the delay buffer <NUM> may function as a threshold (e.g., minimum) delay between receiving a change in the logical value of the first voltage <NUM> and a change in the in the logical value of the second voltage <NUM>.

During operation, the first voltage <NUM> may correspond to the second logical value (e.g., a "<NUM>" value) during operation in a sleep mode (e.g., a low-power operating mode) and may correspond to the first logical value (e.g., a "<NUM>" value) during operation in the active mode. When the first voltage <NUM> transitions to correspond to the second logical value (e.g., when the sleep mode is activated), the first internal power supply <NUM> is decoupled from the external power supply <NUM> (e.g., by the first and second transistors <NUM>, <NUM>) and may be allowed to discharge. The output of the inverter <NUM> may deactivate the fourth transistor <NUM> to isolate the first internal power supply <NUM> from the voltage detector <NUM>, and the voltage detector <NUM> may output a voltage corresponding to the first logical value (e.g., a <NUM>). The output selection circuitry of the output signal circuitry <NUM> may provide the second logical value (e.g., a <NUM>) to the delay buffer <NUM>, and, after the minimum delay, the second voltage <NUM> may transition to correspond to the second logical value.

When the first voltage <NUM> transitions to correspond to the first logical value (e.g., when the active mode is activated), the first transistor <NUM>, the second transistor <NUM>, or both, may be activated to couple the first internal power supply <NUM> to the external power supply <NUM>. Additionally, the fourth transistor <NUM> may be activated, and the third transistor <NUM> may be deactivated. Thus, the first internal power supply <NUM> may be connected to the input of the voltage detector <NUM>.

When the voltage at the input to the voltage detector <NUM> is approximately equal to or greater than the particular voltage level (e.g., a first target voltage, such as the high target voltage), the output of the voltage detector <NUM> may transition from the first logical value (e.g., a <NUM>) to the second logical value (e.g., a <NUM>), causing the output selection circuitry to provide a voltage corresponding to the first logical value (e.g., a <NUM>) to the delay buffer <NUM>. After a particular time delay (e.g., <NUM> nanoseconds), the second voltage <NUM> transitions from the second logical value (e.g., a <NUM>) to the first logical value (e.g., a <NUM>). The first voltage droop controller <NUM> of <FIG> may thus generate a delay between activation of the first component <NUM> and providing an output to cause activation of a next component in a charging sequence.

Referring to <FIG>, another particular implementation of the first component <NUM> is shown. The second component <NUM> of <FIG> may include similar circuitry to the circuitry described below with reference to <FIG>. Thus, the details of various aspects and operations associated with the first component <NUM> described with reference to <FIG> may also apply to the second component <NUM> or to other components of a charging sequence of the device <NUM>.

In <FIG>, the first component <NUM> includes the first voltage droop controller <NUM>. The first voltage droop controller <NUM> includes an inverter <NUM> coupled to the first input <NUM> and coupled to voltage detection circuitry <NUM> and to output signal circuitry <NUM>. The voltage detection circuitry <NUM> generates an output <NUM> based on a voltage level of the first internal power supply <NUM> and based on an output of the inverter <NUM>. The output signal circuitry <NUM> is responsive to the output of the inverter <NUM> and to the output <NUM> of the voltage detection circuitry <NUM> to generate the first output <NUM>.

Logic (e.g., an inverter <NUM> and a NOR gate in <FIG>) of the voltage detection circuitry <NUM> may provide a detector enable signal to a voltage detector <NUM> based on a logical value of the first voltage <NUM>. The voltage detector <NUM> may correspond to the voltage detector <NUM> of <FIG>, and is described in more detail with reference to <FIG>. The voltage detector <NUM> may be coupled to the first internal power supply <NUM> (vddhx). While activated (based on the detector enable signal), the voltage detector <NUM> may provide an output to the output signal circuitry <NUM> indicating whether a first voltage of first internal power supply <NUM> satisfies (e.g., is greater than or equal to) a second voltage of the external power supply <NUM> (vddmx) (e.g., a power rail).

The output signal circuitry <NUM> may include a reset-set (RS) latch <NUM> and a chain of inverters (inverter chain <NUM>). A delay generated by the inverter chain <NUM> may function as a threshold (e.g., minimum) delay between activation of the first component <NUM> (e.g., responsive to the first voltage <NUM>) and generating the second voltage <NUM> corresponding to the first logical value. The first voltage droop controller <NUM> of <FIG> may thus generate a delay between activation of the first component <NUM> and providing an output to cause activation of a next component in a charging sequence.

Referring to <FIG>, a particular aspect of the voltage detector <NUM> of <FIG> is disclosed. In <FIG>, the voltage detector <NUM> includes first pull up circuitry <NUM> and second pull up circuitry <NUM>, which are configured to receive a detector enable signal <NUM>. The detector enable signal <NUM> may correspond to the detector enable signal of <FIG>. The voltage detector <NUM> also includes first pull down circuitry <NUM> and second pull down circuitry <NUM> coupled to receive a voltage from the external power supply <NUM> (vddmx).

The first pull up circuitry <NUM> and the first pull down circuitry <NUM> are configured to operate as a first inverter responsive to the detector enable signal <NUM> and to the external power supply <NUM>. An output <NUM> (Vddmx_vt) of the first inverter may be provided as input to the second pull up circuitry <NUM>. The second pull up circuitry <NUM> and the second pull down circuitry <NUM> are configured to operate as a second inverter responsive to the detector enable signal <NUM>, the output <NUM> of the first inverter and the external power supply <NUM>. When a voltage differential between the first internal power supply <NUM> and the output <NUM> of the first inverter is sufficient, a state of the output of the second inverter changes (e.g., from the second logical value to the first logical value). Thus, the voltage detector <NUM>, when activated, may indicate whether a first voltage level of the first internal power supply <NUM> satisfies a target voltage level (e.g., is approximately equal to a second voltage level of the external power supply <NUM>).

Referring to <FIG>, a timing diagram is disclosed and generally designated <NUM>. The timing diagram <NUM> may differ from the timing diagram <NUM> of <FIG> in that the timing diagram <NUM> illustrates exemplary values of the detector enable signal <NUM> and an output signal <NUM> of the voltage detector <NUM>. As in the timing diagram <NUM> of <FIG>, the device <NUM> of <FIG> may be in an active mode (e.g., a high-power operating mode) prior to a time t0, in a sleep mode (e.g., a low-power operating mode) from the time t0 to a time t1, and in the active mode subsequent to the time t1.

At the time t1, the inverted first voltage <NUM> transitions from corresponding to the second logical value to corresponding to the first logical value. The detector enable signal <NUM> may activate the voltage detector <NUM> based on the first voltage <NUM> transitioning to corresponding to the first logical value. Additionally, the first internal power supply <NUM> may begin to charge using the external power supply <NUM> based on the first voltage <NUM> transitioning to corresponding to the first logical value. The output signal <NUM> may have the second logical value (e.g., <NUM>) while the voltage level of the first internal power supply <NUM> is less than a target voltage level (e.g., the voltage level of the external power supply <NUM>).

At or about a time tA, the first voltage level of the first internal power supply <NUM> may satisfy (e.g., be approximately equal to) the target voltage level, and the output signal <NUM> may transition to corresponding to the first logical value (e.g., <NUM>). After a delay (e.g., at or about the time t2), the second voltage <NUM> (corresponding to the first output <NUM> of <FIG>) may begin to transition to corresponding to the first logical value (e.g., <NUM>). The delay between tA and t2 may be due, at least in part, to latching at the RS latch <NUM> and delay of inverter chain <NUM> of <FIG>.

The detector enable signal <NUM> may subsequently transition to corresponding to the second logical value (e.g., <NUM>) to disable the voltage detector <NUM> in response to the first output <NUM> transitioning to corresponding to the first logical value.

Referring to <FIG>, a particular aspect of a method of operation is shown and generally designated <NUM>. In a particular aspect, the method <NUM> may be performed by the device <NUM>, the first component <NUM>, the second component <NUM>, the first voltage droop controller <NUM>, the second voltage droop controller <NUM>, the voltage detector <NUM> of <FIG>, the voltage detector <NUM> of <FIG>, or a combination thereof.

The method <NUM> includes receiving a first voltage at a first input of a first component of a device, at <NUM>. For example, the first component <NUM> of the device <NUM> may receive the first voltage <NUM>, as described with reference to <FIG>.

A first internal power supply of the first component is charged using an external power supply in response to the first voltage corresponding to a first logical value, at <NUM>. For example, the external power supply <NUM> may charge the first internal power supply <NUM> of the first component <NUM> in response to the first voltage <NUM> corresponding to the first logical value, as described with reference to <FIG>.

A second voltage corresponding to the first logical value is provided from the first component to a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level, at <NUM>. For example, the first component <NUM> of <FIG> may provide the second voltage <NUM> corresponding to the first logical value to the second component <NUM> of the device <NUM> in response to a first voltage level of the first internal power supply <NUM> satisfying a second voltage level, as described with reference to <FIG>.

A second internal power supply of the second component of the device is charged using the external power supply in response to the second component receiving the second voltage corresponding to the first logical value from the first component. For example, the external power supply <NUM> of <FIG> may charge the second internal power supply <NUM> of the second component <NUM> of the device <NUM> in response to the second voltage <NUM> corresponding to the first logical value. The method <NUM> may thus enable generation of a delay between activation of the first component and providing a signal to activate the second component.

Referring to <FIG>, a block diagram of a particular illustrative aspect of a communication device is depicted and generally designated <NUM>. The device <NUM> includes a processor <NUM> (e.g., a digital signal processor (DSP)) coupled to a memory <NUM>. The processor <NUM> may be coupled to (or include) the first component <NUM>, the second component <NUM>, or both. Alternatively or additionally, the memory <NUM> may be coupled to (or include) the first component <NUM>, the second component <NUM>, or both. In a particular aspect, one or more components of the device <NUM> may perform one or more operations described with reference to systems and methods of <FIG>.

The memory <NUM> may be a non-transient computer readable medium storing computer-executable instructions <NUM> that are executable by the processor <NUM> to cause the processor <NUM> to control voltage droop of the external power supply <NUM> of <FIG> during transition from a low power state (e.g., a sleep mode) to a higher power state (e.g., an active mode). For example, the instructions may be executable by the processor <NUM> to cause the first voltage <NUM> of <FIG> to correspond to the first logical value, such that first component <NUM> provides the second voltage <NUM> corresponding to the first logical value to the second component <NUM> when a voltage level of the first internal power supply <NUM> satisfies a target voltage, as described above. The external power supply <NUM> of <FIG> may correspond to the power supply <NUM> of <FIG>.

<FIG> also indicates that a wireless controller <NUM> can be coupled to the processor <NUM> and to an antenna <NUM>. In a particular aspect, the processor <NUM>, a display controller <NUM>, the memory <NUM>, a CODEC <NUM>, and the wireless controller <NUM> are included in a system-in-package or system-on-chip device <NUM>. In a particular aspect, an input device <NUM> and the power supply <NUM> are coupled to the system-on-chip device <NUM>. Moreover, in a particular aspect, as illustrated in <FIG>, a display <NUM>, the input device <NUM>, a speaker <NUM>, a microphone <NUM>, the antenna <NUM>, and the power supply <NUM> are external to the system-on-chip device <NUM>. However, each of the display <NUM>, the input device <NUM>, the speaker <NUM>, the microphone <NUM>, the antenna <NUM>, and the power supply <NUM> can be coupled to a component of the system-on-chip device <NUM>, such as an interface or a controller.

In conjunction with the described aspects, an apparatus includes means for controlling voltage droop at a first component of a device configured to receive a first voltage at a first input of the first component, to charge a first internal power supply of the first component using an external power supply in response to the first voltage corresponding to a first logical value, and to provide a second voltage corresponding to the first logical value from a first output of the first component to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. For example, the means for controlling voltage droop at the first component may include the first voltage droop controller <NUM> of <FIG>, <FIG>, <FIG> and <FIG>, the first component <NUM> of <FIG> and <FIG>, the device <NUM> of <FIG>, the device <NUM> of <FIG>, one or more other devices, circuits, modules, or instructions configured to receive a first voltage at a first input of the first component, to charge a first internal power supply of the first component using an external power supply in response to the first voltage corresponding to a first logical value, and to provide a second voltage corresponding to the first logical value from a first output of the first component to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level, or a combination thereof.

The apparatus also includes means for controlling voltage droop at the second component configured to charge a second internal power supply of the second component using the external power supply in response to the second voltage corresponding to the first logical value. For example, the means for controlling voltage droop at the second component may include the second voltage droop controller <NUM> of <FIG>, the second component <NUM> of <FIG> and <FIG>, the device <NUM> of <FIG>, the device <NUM> of <FIG>, one or more other devices, circuits, modules, or instructions configured to charge a second internal power supply of the second component using the external power supply in response to the second voltage corresponding to the first logical value, or a combination thereof.

The apparatus may also include means for introducing a delay between a time of determining that the first voltage level of the first internal power supply satisfies the second voltage level and a second time of providing the second voltage corresponding to the first logical value to the second component. For example, the means for introducing the delay may include the delay buffer <NUM> of <FIG>, the output signal circuitry <NUM> of <FIG>, the inverter chain <NUM> of <FIG>, the output signal circuitry <NUM> of <FIG>, the device <NUM> of <FIG>, the device <NUM> of <FIG>, one or more other devices, circuits, modules, or instructions configured to introduce a delay between a time of determining that the first voltage level of the first internal power supply satisfies the second voltage level and a second time of providing the second voltage corresponding to the first logical value to the second component, or a combination thereof.

The apparatus may also include means for detecting the first voltage level of the first internal power supply. For example, the means for detecting the first voltage level of the first internal power supply may include the voltage detector <NUM> of <FIG> and <FIG>, the voltage detector <NUM> of <FIG> and <FIG>, the voltage detection circuitry <NUM> of <FIG>, the voltage detection circuitry <NUM> of <FIG>, the device <NUM> of <FIG>, the device <NUM> of <FIG>, one or more other devices, circuits, modules, or instructions configured to detect the first voltage level of the first internal power supply, or a combination thereof.

Those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality.

The steps of a method or algorithm described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary non-transitory (e.g. tangible) storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.

Claim 1:
A device comprising:
a first component (<NUM>) coupled to an external power supply, the first component including:
a first input (<NUM>) configured to receive a first voltage (<NUM>);
a first internal power supply (<NUM>) configured to be charged by the external power supply (<NUM>) in response to the first voltage (<NUM>) corresponding to a first logical value;
a voltage droop controller (<NUM>) configured to output a second voltage (<NUM>) via a first output (<NUM>), the second voltage corresponding to the first logical value in response to a first voltage level of a voltage of the first internal power supply (<NUM>) being equal to or greater than a second voltage level; wherein the voltage droop controller includes a voltage detector (<NUM>) configured to receive via an input of the voltage detector, said voltage of the first internal power supply from the first internal power supply in response to the first voltage corresponding to the first logical value, wherein the input of the voltage detector is coupled to a ground voltage in response to the first voltage corresponding to a second logical value; and wherein the voltage droop controller further comprises output signal circuitry (<NUM>) coupled to the output of the voltage detector (<NUM>), wherein the output signal circuitry (<NUM>) is configured to provide the second voltage (<NUM>) corresponding to the first logical value to the second component based on the output of the voltage detector (<NUM>) and based on the first voltage (<NUM>) corresponding to the first logical value; and
a second component (<NUM>) coupled to the external power supply (<NUM>), the second component (<NUM>) including a second input (<NUM>) configured to receive the second voltage (<NUM>) from the first output (<NUM>) and a second internal power supply configured to be charged by the external power supply in response to the second voltage corresponding to the first logical value.