Patent Description:
Processors need to process interrupts coming from interrupt sources such as I/O devices and timers. Processors process interrupts by executing interrupt service routines. Because processors need to process different interrupts from a plurality of interrupt sources, each interrupt has a corresponding interrupt priority. Typically, a high-performance platform has a sophisticatedly designed system, and the system has a very large quantity of interrupt sources, usually more than <NUM>. For the platform, an interrupt controller needs to identify through arbitration, from a large quantity of interrupts, an interrupt with the highest priority and report information and the like of the interrupt. The interrupt controller needs to compare priorities of various interrupts to select the interrupt with the highest priority, and respond with the interrupt.

In traditional interrupt control, resources for priority arbitration expand rapidly with an increase of the quantity of interrupt sources. Each additional interrupt source requires an additional interrupt arbitration resource. The arbitration logic includes priority comparators, selectors, and the like. In addition, in a high-performance interrupt controller, timing phasing is required for the design as the quantity of interrupt sources increases, which makes the design highly complicated.

When the quantity of interrupt sources is very large, there is a huge quantity of logical resources of the interrupt controller and timing phasing is complicated. Therefore, traditional interrupt controllers will affect the timing performance and size of the entire chip.

<CIT> describes an interrupt controller which includes a priority level arbitrator including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator using priority level data associated with the respective interrupt signals.

For this reason, a novel interrupt controller solution in processors is needed, to implement a more efficient interrupt processing manner and support different interrupt source configurations by using only a small quantity of resources.

In view of this, the present invention provides a novel processor and an interrupt controller therein, so as to solve or at least alleviate at least one of the above problems.

According to one aspect of the present invention, the present invention provides an interrupt controller, including: a sampling unit adapted to sample interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts to produce sampled interrupts; and a priority arbitration unit adapted to split the sampled interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, for each interrupt segment, an highest priority interrupt, and identify the highest priority interrupt among all interrupt segments that is designated to be an to-be-responded-to interrupt. The interrupt controller further comprises an arbitration iteration control unit adapted to: control the priority arbitration unit to perform arbitration on the interrupts and complete the arbitration after all interrupts are traversed; control the priority arbitration unit to perform arbitration on interrupts that meet a preset condition and complete the arbitration after all the interrupts that meet the preset condition are traversed, where the preset condition is that an interrupt processing state is a pending state; and trigger the priority arbitration unit to perform iterative arbitration when the interrupts include an interrupt in the pending state and the priority arbitration unit is not performing arbitration.

Optionally, in the interrupt controller according to the present invention, the priority arbitration unit includes: a selection module adapted to select one of the plurality of interrupt segments one by one, and send an interrupt in the selected interrupt segment to an arbitration module; and the arbitration module adapted to identify, through arbitration from the interrupt selected by the selection module and an intermediate arbitration result of a previous round of arbitration, an interrupt with a highest priority as the intermediate arbitration result of a current round of arbitration, where the arbitration module completes a last round of arbitration when the arbitration module performs arbitration on interrupts in a last interrupt segment selected by the selection module and uses a result of the last round of arbitration as the to-be-responded-to interrupt.

Optionally, the interrupt controller according to the present invention further includes an interrupt configuration unit coupled to the sampling unit and adapted to store configuration information of the interrupts, where the configuration information includes one or more the following information: interrupt priority, interrupt processing status, and interrupt enable.

Optionally, in the interrupt controller according to the present invention, a quantity of input multi-channel selections supported by the selection module is determined by a quantity of received interrupts and a quantity of input multi-channel selections supported by the arbitration module; and the quantity of input multi-channel selections supported by the arbitration module is determined by the quantity of received interrupts.

Optionally, in the interrupt controller according to the present invention, the priority arbitration unit is further adapted to split the received various interrupts into a plurality of interrupt segments in an orderly or a random manner, and select one of the plurality of interrupt segments for arbitration.

Optionally, in the interrupt controller according to the present invention, the priority arbitration unit is further adapted to, before splitting the received interrupts into the plurality of interrupt segments, block interrupt sources that include no interrupts and splitting interrupts in interrupt sources that include interrupts.

Optionally, the interrupt controller according to the present invention further includes: a threshold comparison unit coupled to the interrupt configuration unit and adapted to compare a priority of the interrupt and a preset priority, and when the priority of the interrupt is higher than the preset priority, input the interrupt to the priority arbitration unit.

According to another aspect of the present invention, the present invention provides a processor, including: the interrupt controller described above and adapted to sample the interrupts from the various interrupt sources coupled to the interrupt controller and select the to-be-processed interrupt; and a processor core coupled to the interrupt controller and processing the interrupt selected by the interrupt controller.

Optionally, in the processor according to the present invention, the processor core is adapted to, when an interrupt priority of the interrupt selected by the interrupt controller is higher than an interrupt priority of an interrupt being processed in the processor core, suspend processing the interrupt being processed and start to process the interrupt selected by the interrupt controller.

Optionally, in the processor according to the present invention, the processor core is adapted to, when the interrupt priority of the interrupt selected by the interrupt controller is not higher than the interrupt priority of the interrupt being processed in the processor core, skip processing the interrupt selected by the interrupt controller.

According to still another aspect of the present invention, the present invention provides a system-on-chip, including: the processor described above; and the various interrupt sources coupled to the processor and generating interrupts to be processed by the processor.

According to some embodiments of the present invention, the priority arbitration unit identifies, through arbitration, the to-be-responded-to interrupt in a manner of iterative arbitration, so as to reduce arbitration logic resources. The major principle is that in terms of arbitration logic, only a small amount of arbitration logic may be used. During each round of arbitration, the arbitration logic may only perform arbitration on some of all interrupts. An interrupt obtained through arbitration may be saved as an intermediate arbitration result. Then, a plurality of rounds of arbitration may be performed until all the interrupts go through the priority arbitration unit. In the end, a result output by the priority arbitration unit may be a final interrupt result.

Throughout the present disclosure, the same reference numeral generally represents the same part or element.

<FIG> illustrates a schematic diagram of a processor <NUM> according to one embodiment of the present invention. As illustrated in <FIG>, a processing system <NUM> includes the processor <NUM> and various interrupt sources <NUM> (the interrupt sources <NUM> are, for example, external I/O devices and timers) coupled to the processor <NUM>. The interrupt sources <NUM> generate interrupts of various types that are processed by the processor <NUM>. The processor <NUM> includes a processor core <NUM> and an interrupt controller <NUM>. The processor core <NUM> is coupled to the interrupt controller <NUM> and processes interrupts selected by the interrupt controller <NUM>.

The processor core <NUM> further includes an instruction processing device <NUM> and a processor resource <NUM>. The instruction processing device <NUM> is an instruction processing component in the processor <NUM> and performs processing including fetching instructions for decoding and then executing various instructions obtained after the decoding. The instruction processing device <NUM> responds to the interrupts at the same time, modifies a procedure flow for instruction execution in the processor <NUM>, and executes a corresponding interrupt processing routine. It should be noted that the instruction processing device <NUM> is a logical division of functions of the processor <NUM>. All instruction-related parts in the processor <NUM> may be classified as a part of the instruction processing device <NUM> without going beyond the protection scope of the present invention.

According to one embodiment, the instruction processing device <NUM> includes an instruction fetch unit <NUM>, an instruction decode unit <NUM>, and an instruction execution unit <NUM>. The instruction fetch unit <NUM> acquires to-be-executed instructions from an instruction storage area <NUM> and sends the acquired instructions to the instruction decode unit <NUM>.

An instruction typically includes an operation code and an address code, where the operation code indicates a to-be-performed operation and the address code indicates the address or content of an operation object when the operation code is executed. The instruction decode unit <NUM> can decode and analyze the instruction to determine the operation code of the instruction and further determine an operation nature and method.

Then, the instruction decode unit <NUM> sends the decoded instruction to the instruction execution unit <NUM>. The instruction is executed in the instruction execution unit <NUM>. According to one embodiment of the present invention, the instruction execution unit <NUM> includes various execution units used to execute specific instructions. Specific forms of instruction execution units that execute specific instructions are not limited in the present invention. All instruction execution units <NUM> capable of executing instructions are included in the protection scope of the present invention.

When executing instructions, the instruction execution unit <NUM> accesses the processor resource <NUM> such as various registers and a data storage area <NUM>, for example, to acquire data from these registers and the data storage area <NUM>, and write execution results to the registers or a data storage space.

The processor core <NUM> further includes an interrupt processing module <NUM>. During instruction processing by the instruction processing device <NUM>, the interrupt processing module <NUM> responds to an external interrupt so as to change a procedure being executed in the processor via the instruction processing unit <NUM> and run an interrupt service routine corresponding to the external interrupt to process the interrupt.

According to one embodiment, when responding to an interrupt, the processor core <NUM> first stores a current processor status and a processor execution site (a program counter (PC) of the processor), obtains an entry address of the interrupt service routine based on interrupt information of the responded-to interrupt, and jumps to this address to start an interrupt processing task. After completing the interrupt processing task, the processor core <NUM> executes an interrupt return instruction. The processor restores to the previously stored processor status and returns to the previous site (the stored PC) to continue execution. The interrupt processing module <NUM> can performs the above interrupt response processing by using the instruction processing device <NUM>.

The interrupt controller <NUM> is coupled to the processor core <NUM> and selects a to-be-processed interrupt to send to the processor core <NUM> for processing. Each interrupt has a corresponding interrupt priority. The processor <NUM> determines an interrupt processing order based on interrupt priorities of interrupts. When a plurality of interrupts occur at the same time, an interrupt with the highest priority is processed first.

When an interrupt priority of the interrupt selected by the interrupt controller <NUM> is higher than an interrupt priority of an interrupt being processed in the processor core <NUM>, the processor core <NUM> suspends processing the interrupt being processed and starts to process the interrupt selected by the interrupt controller <NUM>. Likewise, when the interrupt priority of the interrupt selected by the interrupt controller <NUM> is not higher than the interrupt priority of the interrupt being processed in the processor core <NUM>, the processor core <NUM> skips processing the interrupt selected by the interrupt controller <NUM>.

The interrupt controller <NUM> classifies the received interrupts to obtain a plurality of interrupt segments, and then selects one interrupt from each of the interrupt segments for arbitration to identify an interrupt with the highest priority. The interrupt controller <NUM> repeats the arbitration process for a plurality of times iteratively, and after all interrupts are traversed, complete the arbitration and determines an interrupt with the highest priority. The instruction processing device <NUM> executes the interrupt service routine.

<FIG> illustrates a schematic diagram of an interrupt controller <NUM> according to one embodiment of the present invention. The interrupt controller <NUM> acquires interrupts from a plurality of interrupt sources <NUM> coupled to the interrupt controller <NUM> and selects an interrupt to be sent to a processor core <NUM> for processing.

As illustrated in <FIG>, the interrupt controller <NUM> includes a sampling unit <NUM> and a priority arbitration unit <NUM>. The sampling unit <NUM> receives various interrupts from the interrupt sources <NUM> coupled to the interrupt controller <NUM>. Typically, a clock of the external interrupt source <NUM> is in an asynchronous relationship with a processor clock. The sampling unit <NUM> synchronizes the external interrupt source <NUM> to the processor clock and performs sampling to generate valid interrupt information, In addition, the interrupt source <NUM> has two different trigger attributes: level trigger and edge trigger (or pulse trigger). The sampling unit <NUM> samples these two different trigger manners and unifies them into one processing manner.

The priority arbitration unit <NUM> determines an interrupt with the highest priority from the interrupts received from the sampling unit <NUM> and uses the interrupt as an interrupt to be sent to the processor core <NUM> for response processing. The priority arbitration unit <NUM> first classifies the received various interrupts into a plurality of interrupt segments, Generally, each interrupt segment includes one or more sampled interrupts. According to this embodiment of the present invention, a quantity of interrupts included in each classified interrupt segment may be a fixed quantity or may be dynamically adjusted. This is not limited in this embodiment of the present invention, Then, the priority arbitration unit <NUM> determines, segment by segment, an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as a to-be-responded-to interrupt.

<FIG> illustrates a schematic diagram of a priority arbitration unit <NUM> according to one embodiment of the present invention. As illustrated in <FIG>, the priority arbitration unit <NUM> includes a selection module <NUM> and an arbitration module <NUM>.

In one embodiment, the selection module <NUM> is responsible for selecting, from received interrupts, an interrupt to be sent to the arbitration module <NUM> for arbitration. Specifically, the selection module <NUM> selects one of a plurality of interrupt segments one by one, and sends an interrupt in the selected interrupt segment to the arbitration module <NUM> for arbitration.

Each arbitration performed by the arbitration module <NUM> on an interrupt segment is called a round of arbitration. In each round of arbitration, the arbitration module <NUM> identifies, through arbitration, an interrupt with the highest priority in the interrupt segment as an intermediate arbitration resull. According to this embodiment of the present invention, the arbitration module <NUM> identifies, through arbitration from the interrupt selected by the selection module <NUM> and an intermediate arbitration result of a previous round of arbitration, an interrupt with the highest priority as an intermediate arbitration result of this round of arbitration. The arbitration module <NUM> completes the last round of arbitration when the arbitration module <NUM> performs arbitration on interrupts in the last interrupt segment selected by the selection module <NUM> and uses a result of the last round of arbitration as the to-be-responded-to interrupt.

It should be noted that a quantity of interrupts illustrated in <FIG> and a quantity of input/output signals of a selector used for multi-channel selection that is deployed in the selection module <NUM> and the arbitration module <NUM> are merely examples. This embodiment of the present invention is not limited thereto. An implementation of the selector used for multi-channel selection is not limited in this embodiment of the present invention.

In addition, the priority arbitration unit <NUM> identifies, through arbitration based on preconfigured configuration information of the interrupts, an interrupt with the highest priority. The configuration information includes one or more the following information: interrupt priority, interrupt processing state, and interrupt enable.

Optionally, the interrupt controller <NUM> further includes an interrupt configuration unit <NUM> adapted to store the configuration information of the interrupts. As illustrated in <FIG>, the interrupt configuration unit <NUM> is coupled to the sampling unit <NUM>. The interrupt configuration unit <NUM> stores the configuration information (including interrupt priority, interrupt processing state, and interrupt enable) of the interrupts. Depending on a status of processing by the processor, an interrupt has a plurality of processing states, including an interrupt pending (pending) state and an interrupt active (active) state. The interrupt pending (pending) state indicates that the interrupt is generated by the interrupt source <NUM> and received by the sampling unit <NUM>, but not responded to and processed by the processor core <NUM>. The interrupt active (active) state indicates that the interrupt is not only received by the sampling unit <NUM>, but also processed by the processor core <NUM>, but the processing is not complete yet. This includes not only a case of being processed by the processor core <NUM>, but also a case of execution suspension due to interrupt nesting that causes the processor core <NUM> to execute an interrupt with a higher priority.

Interrupt nesting refers to that when the processor core <NUM> is processing an interrupt with a lower priority, the processor core <NUM> receives a new interrupt with a higher priority. In this case, the processor core <NUM> needs to suspend the processing of the interrupt with a lower priority, store a site of the interrupt (including a program counter PC), push the content of related registers to a corresponding stack, and start to execute processing corresponding to the interrupt with a higher priority. In this way, interrupt nesting is generated. When interrupt nesting has a relatively large quantity of layers, a large quantity of resources of the processor may be consumed because information about a relatively large quantity of interrupts needs to be stored.

According to one embodiment, the interrupt configuration unit <NUM> can use registers to store the configuration information of the interrupts and modify states of the interrupts by changing values of corresponding locations of these registers.

Optionally, the interrupt configuration unit <NUM> further stores an enable bit of each interrupt to instruct whether to adopt and process the interrupt. The sampling unit <NUM> can determine whether to adopt the interrupt based on a value of the enable bit of the interrupt.

The interrupt controller <NUM> further includes an arbitration iteration control unit <NUM>. Still as illustrated in <FIG>, the arbitration iteration control unit <NUM> is coupled to the priority arbitration unit <NUM> and is adapted to control the priority arbitration unit <NUM> to perform arbitration on the received various interrupts and complete the arbitration after all the interrupts are traversed.

The arbitration iteration control unit <NUM> controls the priority arbitration unit <NUM> to perform arbitration on interrupts that meet a preset condition and complete the arbitration after all the interrupts that meet the preset condition are traversed, where the preset condition is that the interrupt processing state is a pending (pending) state.

The arbitration iteration control unit <NUM> controls the triggering of interrupt arbitration, interrupt selection for intermediate arbitration, and judgment of arbitration completion.

For the triggering of interrupt arbitration, the arbitration iteration control unit <NUM> controls the priority arbitration unit <NUM> and triggers the priority arbitration unit <NUM> to perform iterative arbitration when the received various interrupts include an interrupt in the pending (pending) state and the priority arbitration unit <NUM> is not performing arbitration,.

For the interrupt selection for intermediate arbitration, the arbitration iteration control unit <NUM> controls the priority arbitration unit <NUM> to classify the received various interrupts into a plurality of interrupt segments in an orderly or a random manner, and select one of the plurality of interrupt segments for arbitration until all the interrupts are traversed. It is assumed that a total of nine interrupts are received and classified into three interrupt segments. A quantity of interrupts in each interrupt segment can be fixed in an orderly manner. Specifically, the first three interrupts are used as one interrupt segment, the middle three interrupts are used as one interrupt segment, and the last three interrupts are used as one interrupt segment. (Certainly, the quantity of interrupts in each interrupt segment may be alternatively dynamically adjusted. For example, the first four interrupts are used as one interrupt segment, the middle three interrupts are used as one interrupt segment, and the last two interrupts are used as one interrupt segment. This is not limited herein. ) In addition, the interrupts may be alternatively classified into three interrupt segments in a random manner. A manner of specifying interrupt numbers may even be used to use the first, fourth, and seventh interrupts as one interrupt segment, the second, fifth, and eighth interrupts as one interrupt segment, and the third, sixth, and ninth interrupts as one interrupt segment. A manner of classifying interrupts into a plurality of interrupt segments to complete traversing the interrupts is not limited in the embodiments of the present invention.

The arbitration iteration control unit <NUM> controls the priority arbitration unit <NUM> to traverse only those interrupts in the pending state.

For the judgment of arbitration completion, the arbitration iteration control unit <NUM> controls the priority arbitration unit <NUM> to complete arbitration as long as all interrupts are iterated in an iteration cycle.

An example is provided below to further describe a logic of iterative arbitration performed by the priority arbitration unit <NUM>.

A quantity of interrupt sources is <NUM> and the arbitration module <NUM> supports priority arbitration of selecting <NUM> from <NUM>+<NUM> interrupts (where <NUM> is an intermediate arbitration result). The selection module <NUM> needs to support <NUM> selectors that select <NUM> from <NUM> interrupts. A relatively simple iterative arbitration execution logic may be designed as follows: Classify the <NUM> interrupts sequentially into <NUM> interrupt segments, each interrupt segment including <NUM> interrupts. Select one interrupt segment each time for arbitration, that is, iterate a total of <NUM> rounds in an iteration cycle. Then, a selection signal of the <NUM> selectors in the selection module <NUM> is the quantity of rounds. Each selector selects an interrupt to be iterated in the current round. After the last round, an interrupt output by the arbitration module <NUM> is an interrupt obtained from the final arbitration.

It should be noted that an example in which both the selection module <NUM> and the arbitration module <NUM> use selectors (that is, multiple-to-one data selectors) is used herein for ease of description. This is not limited in this embodiment of the present invention. The selection module <NUM> and the arbitration module <NUM> may use any type of devices having a multi-channel selection function (such as multiplexers) to receive multi-channel interrupt signals and select one from the received interrupts for output.

It can be learned from the above example that when a quantity of received interrupts is N, a quantity of interrupts supported by the arbitration module <NUM> is M+<NUM> (that is, a quantity of input multi-channel selection signals supported by the arbitration module <NUM>). Then, the selection module <NUM> needs M selectors having the multi-channel selection function. Each selector has a specification of [N/M]-to-<NUM>, that is, supports input of [N/M] interrupt signals and output of <NUM> interrupt signal. [N/M] indicates rounding-up. That is, if N/M is an integer, then [N/M]=N/M; if N/M is not an integer, then [N/M]=N/M+<NUM>. In other words, the quantity (that is, [N/M]) of input multi-channel selections supported by the selection module <NUM> is determined by the quantity (that is, N) of received interrupts and the quantity (that is, M) of input multi-channel selections supported by the arbitration module <NUM>.

The quantity (that is, M) of input multi-channel selections supported by the arbitration module <NUM> is determined by the quantity (that is, N) of received interrupts. Generally, M may be any number, as long as it is smaller than N.

As described above, the priority arbitration unit <NUM> traverses only interrupts in the pending state instead of all interrupts, that is, select only any round for iteration in an iteration cycle. To optimize an iterative arbitration speed of the priority arbitration unit <NUM> and implement fast processing, in still some embodiments of the present invention, the priority arbitration unit <NUM> may further block, before classifying the received interrupts into a plurality of interrupt segments, interrupt sources that include no interrupts and classify interrupts only in interrupt sources that include interrupts, For example, if a quantity of interrupt sources is <NUM> but only <NUM> interrupts are actually received, the priority arbitration unit <NUM> may block the rest <NUM>,<NUM> interrupt sources and classify only these <NUM> interrupts for subsequent iterative arbitration,.

According to another embodiment, the interrupt controller <NUM> further includes a threshold comparison unit <NUM> coupled to the interrupt configuration unit <NUM>. The threshold comparison unit <NUM> compares a priority of an interrupt with a preset priority, and when the priority of the interrupt is higher than the preset priority, inputs the interrupt to the priority arbitration unit <NUM> for iterative arbitration.

The preset priority may be stored in a threshold register and may be configured and modified. A specific storage form of the preset priority is not limited in the present invention. All manners capable of reading and modifying the preset priority are included in the protection scope of the present invention.

According to still some embodiments, the interrupt configuration unit <NUM> sets an interrupt priority of a specific interrupt is the highest. When the specific interrupt enters the priority arbitration unit <NUM>, iterative arbitration is not required and the specific interrupt is output directly as a to-be-responded-to interrupt. This manner implements rapid response to the specific interrupt.

Certainly, the threshold comparison unit <NUM> may be alternatively used to set a preset priority for the specific interrupt, so that iterative arbitration is no longer performed on a specific interrupt with a priority higher than the preset priority and the specific interrupt is responded to and processed directly. This implements rapid response to the specific interrupt without affecting processing for other interrupts.

The interrupt controller <NUM> according to the present invention uses the priority arbitration unit <NUM> to identify, through arbitration, the to-be-responded-to interrupt in a manner of iterative arbitration, so as to reduce arbitration logic resources. The major principle is that in terms of arbitration logic, only a small amount of arbitration logic is used. During each round of arbitration, the arbitration logic only performs arbitration on some of all interrupts. An interrupt obtained through arbitration is saved as an intermediate arbitration result. Then, a plurality of rounds of arbitration are performed until all the interrupts go through the priority arbitration unit <NUM>. In the end, a result output by the priority arbitration unit <NUM> is a final interrupt result. At the same time, the interrupt controller <NUM> further uses the arbitration iteration control unit <NUM> to control the arbitration logic of the priority arbitration unit <NUM> to complete arbitration for all traversed interrupts that meet a condition. The condition is set based on actual requirements such as interrupts in the pending state, so that the arbitration processing is more efficient and flexible.

In conclusion, the interrupt controller <NUM> according to the present invention can support arbitration for a large quantity of interrupt sources by using only a small quantity of resources. In addition, the interrupt controller <NUM> is highly scalable and can support configurations for different types of interrupt sources.

<FIG> illustrates a schematic diagram of a computer system <NUM> according to one embodiment of the present invention. The computer system <NUM> shown in <FIG> may be applied to laptops, desktop computers, hand-held PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, hand-held devices, and various other electronic devices. The present invention is not limited thereto, and all systems that include the processors and/or other execution logic disclosed in the description are included in the protection scope of the present invention,.

As shown in <FIG>. the system <NUM> may include one or more processors <NUM> and <NUM>, These processors are coupled to a controller hub <NUM>. In one embodiment, the controller hub <NUM> includes a Graphics Memory Controller Hub (GMCH) <NUM> and an Input/Output Hub (IOH) <NUM> (which may be located on separate chips). The GMCH <NUM> includes a memory controller and a graphics controller that are coupled to a memory <NUM> and a coprocessor <NUM>. The IOH <NUM> couples an input/Output (I/O) device <NUM> to the GMCH <NUM>. Alternatively, the memory controller and the graphics controller are integrated in the processor, so that the memory <NUM> and the coprocessor <NUM> are directly coupled to the processor <NUM>. In this case, the controller hub <NUM> includes only the IOH <NUM>.

The optional nature of the additional processor <NUM> is denoted by dashed lines in <FIG>. Each processor <NUM> or <NUM> may include one or more the processor cores described herein, and may be a specific version of the processor <NUM> illustrated in <FIG>,.

The memory <NUM> may be, for example, a Dynamic Random-Access Memory (DRAM), a Phase Change Memory (PCM), or a combination thereof. In at least one embodiment, the controller hub <NUM> communicates with the processors <NUM> and <NUM> via a multi-drop bus such as a Front Side Bus (FSB), a point-to-point interface such as a Quick Path Interconnect (QPI), or a similar connection <NUM>,.

In one embodiment, the coprocessor <NUM> is a dedicated processor, such as a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processing unit, a general purpose graphics processing unit (GPGPU), or an embedded processor. In one embodiment, the controller hub <NUM> may include an integrated graphics accelerator.

In one embodiment, the processor <NUM> executes instructions that control data processing operations of a general type. What are embedded in these instructions may be coprocessor instructions. The processor <NUM> identifies, for example, these coprocessor instructions of types that should be executed by the attached coprocessor <NUM>. Therefore, the processor <NUM> issues these coprocessor instructions (or control signals representing coprocessor instructions) to the coprocessor <NUM> over a coprocessor bus or other interconnects. The coprocessor <NUM> receives and executes the received coprocessor instructions.

<FIG> illustrates a schematic diagram of a system-on-chip (SoC) <NUM> according to one embodiment of the present invention. As illustrated in <FIG>, an interconnection unit <NUM> is coupled to an application processor <NUM> (for example, the processor <NUM> illustrated in <FIG>, which is not shown in <FIG>), a system agent unit <NUM>, a bus controller unit <NUM>, an integrated memory controller unit <NUM>, one or more coprocessors <NUM>, a Static Random Access Memory (SRAM) unit <NUM>, a Direct Memory Access (DMA) unit <NUM>, and a display unit <NUM> for being coupled to one or more external displays. The application processor <NUM> may further include a set of one or more cores 1102A-N, and a shared cache unit <NUM>, The coprocessor <NUM> includes an integrated graphics logic, an image processor, an audio processor, and a video processor. In one embodiment, the coprocessor <NUM> includes a dedicated processor, such as a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor.

The system-on-chip described above may be included in an intelligent device to implement corresponding functions in the intelligent device including but not limited to executing related control programs, data analysis, computing and processing, network communication, controlling peripherals of the intelligent device, and so on.

Such intelligent devices include dedicated intelligent devices such as mobile terminals and personal digital terminals. The devices include one or more system-on-chips of the present invention to perform data processing or control peripherals of the device.

Such intelligent devices also include dedicated devices designed for specific functions, for example, smart speakers and smart display devices. These devices include the system-on-chip of the present invention to control a speaker or a display device, so as to provide the speaker or the display device with additional functions of communication, perception, data processing, and the like.

Such intelligent devices also include various IoT and AIoT devices. These devices include the system-on-chip of the present invention to perform data processing, for example, AI computing or data communication and transmission, thereby implementing denser and more intelligent device distribution.

Such intelligent devices may also be used in a vehicle, for example, may be implemented as a vehicle-mounted device or may be built into the vehicle, so as to provide a data-processing capability for intelligent driving of the vehicle,.

Such intelligent devices may also be used in the home and entertainment field, for example, may be implemented as a smart speaker, a smart air conditioner, a smart refrigerator a smart display device, or the like. These devices include the system-on-chip of the present invention to perform data processing and peripheral control, making home and entertainment devices intelligent,.

In addition, such intelligent devices may also be used in the industrial field, for example, may be implemented as an industrial control device, a sensing device, an IoT device, an AIoT device, a braking device, or the like. These devices include the system-on-chip of the present invention to perform data processing and peripheral control, making industrial equipment intelligent.

"The foregoing description of intelligent devices is merely exemplary, and the intelligent device according to the present invention is not limited thereto. All intelligent devices capable of performing data processing by using the systent-on-chip of the present invention fall within the protection scope of the present invention.

in addition, some of the embodiments are described herein as a combination of methods or method elements that can be implemented by a processor of a computer system or by other devices that execute the functions. Therefore, a processor having necessary instructions for implementing the methods or method elements forms a device for implementing the methods or method elements.

Claim 1:
An interrupt controller (<NUM>), comprising:
a sampling unit (<NUM>) adapted to sample interrupts received from various interrupt sources (<NUM>) to produce sampled interrupts;
a priority arbitration unit (<NUM>) adapted to
split the sampled interrupts into a plurality of interrupt segments;
determine, for each interrupt segment, a highest priority interrupt;
identify the highest priority interrupt among the plurality of interrupt segments that is designated to be an to-be-responded-to interrupt; and
an arbitration iteration control unit (<NUM>) adapted to: control the priority arbitration unit (<NUM>) to perform arbitration on the interrupts and complete the arbitration after all interrupts are traversed;
control the priority arbitration unit (<NUM>) to perform arbitration on interrupts that meet a preset condition and complete the arbitration after all the interrupts that meet the preset condition are traversed, wherein the preset condition is that an interrupt processing state is a pending state; and
trigger the priority arbitration unit (<NUM>) to perform iterative arbitration when the interrupts comprise an interrupt in the pending state and the priority arbitration unit (<NUM>) is not performing arbitration.