Patent Description:
The accuracy of GNSS receivers has improved drastically over the past few decades due to several technological improvements. One such improvement is the use of differential measurement techniques, in which GNSS signals received by a fixed receiver are used to generate correction data that is communicated to a mobile receiver. Typically, a roving receiver (or simply "rover") receives the correction data from a reference source or base station that already knows its exact location, in addition to receiving signals from GNSS satellites. To generate the correction data, the base station first tracks all the satellites in view and measures their pseudoranges. Next, the base station computes its position and compares the computed position to its known position to generate a list of corrections needed to make the measured pseudorange values accurate for all visible satellites. Last the correction data is communicated to the rover. The rover applies these corrections to its computed pseudoranges to produce a much more accurate position.

Another improvement to GNSS accuracy came through the use of real-time kinematic (RTK) measurement techniques, in which the rover determines its position relative to the base station by measuring the phase of the carrier wave. The carrier signal has a much shorter wavelength than the width of a PRN code (a hundred to a thousand times shorter), therefore allowing the ability to measure distance to improve proportionally. RTK networks offer several advantages to users, including (<NUM>) fast, centimeter-level positioning anywhere over a large area, (<NUM>) a common coordinate reference frame, and (<NUM>) elimination of the need to set up a private base station for a project.

<CIT> discloses a system and method of achieving a reduced time for first fix in a global positioning system receiver (GPS). The GPS receiver includes a low gate count sequential multitap correlator in combination with a digital signal processor and a down converter. The low gate count sequential multitap correlator conducts sequential correlation on the incoming GPS signals using a multitapping and pipelining scheme. The multitapping process involves tapping the shift register and simultaneously correlating the signal samples and tapped chips. The pipelining process includes sampling data, mapping incoming samples, shifting carrier acquisition code, multiplying and accumulating the code and signal products. The digital signal processor conducts the frequency search.

The present invention provides a method according to claim <NUM>, and a correlator according to claim <NUM>. There is also provided a non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to perform the method. The dependent claims relate to specific embodiments.

The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the detailed description serve to explain the principles of the invention. No attempt is made to show structural details of the invention in more detail than may be necessary for a fundamental understanding of the invention and various ways in which it may be practiced.

In the appended figures, similar components and/or features may have the same numerical reference label. Further, various components of the same type may be distinguished by following the reference label with a letter or by following the reference label with a dash followed by a second numerical reference label that distinguishes among the similar components and/or features. If only the first numerical reference label is used in the specification, the description is applicable to any one of the similar components and/or features having the same first numerical reference label irrespective of the suffix.

<FIG> illustrate an example trilateration technique performed by a global navigation satellite system (GNSS) receiver operating within a GNSS to generate a position estimate, according to some embodiments of the present disclosure. <FIG> shows a first scenario in which a GNSS receiver receives GNSS signals from a first satellite <NUM>-<NUM> and generates a distance estimate (e.g., <NUM>,<NUM>) for that satellite. This informs the GNSS receiver that it is located somewhere on the surface of a sphere with a radius of <NUM>,<NUM>, centered on first satellite <NUM>-<NUM>. <FIG> shows a second scenario in which the GNSS receiver receives GNSS signals from a second satellite <NUM>-<NUM> and generates a distance estimate (e.g., <NUM>,<NUM>) for the additional satellite. This informs the GNSS receiver that it is also located somewhere on the surface of a sphere with a radius of <NUM>,<NUM>, centered on second satellite <NUM>-<NUM>. This limits the possible locations to somewhere on the region <NUM> where the first sphere and second sphere intersect.

<FIG> shows a third scenario in which the GNSS receiver receives GNSS signals from a third satellite <NUM>-<NUM> and generates a distance estimate (e.g., <NUM>,<NUM>) for the additional satellite. This informs the GNSS receiver that it is also located somewhere on the surface of a sphere with a radius of <NUM>,<NUM>, centered on third satellite <NUM>-<NUM>. This limits the possible locations to two points <NUM> where first sphere <NUM>-<NUM>, second sphere <NUM>-<NUM>, and third sphere <NUM>-<NUM> intersect. <FIG> shows a fourth scenario in which the GNSS receiver receives GNSS signals from a fourth satellite <NUM>-<NUM>. Fourth satellite <NUM>-<NUM> can be used to resolve which of points <NUM> is a correct point <NUM> (by generating a fourth sphere) and/or to synchronize the receiver's clock with the satellites' time.

<FIG> illustrates an example of a rover <NUM> (containing a GNSS receiver <NUM>), a mobile base station <NUM>-<NUM>, and a stationary base station <NUM>-<NUM> operating within a GNSS <NUM>, according to some embodiments of the present disclosure. GNSS <NUM> includes one or more GNSS satellites <NUM>, i.e., space vehicles (SV), in orbit above rover <NUM> and base stations <NUM>. GNSS satellites <NUM> may continuously, periodically, or intermittently broadcast wireless signals <NUM> containing PRN codes modulated onto carrier frequencies (e.g., L1 and/or L2 carrier frequencies). Wireless signals <NUM> corresponding to different GNSS satellites <NUM> may include different PRN codes that identify a particular GNSS satellite <NUM> such that receivers may associate different distance estimates (i.e., pseudoranges) to different GNSS satellites <NUM>. For example, GNSS satellite <NUM>-<NUM> may broadcast wireless signals <NUM>-<NUM> which contain a different PRN code than the PRN code contained in wireless signals <NUM>-<NUM> broadcasted by GNSS satellite <NUM>-<NUM>.

Similarly, GNSS satellite <NUM>-<NUM> may broadcast wireless signals <NUM>-<NUM> which contain a different PRN code than the PRN codes contained in wireless signals <NUM>-<NUM> and <NUM>-<NUM> broadcasted by GNSS satellites <NUM>-<NUM> and <NUM>-<NUM>, respectively. One or more of wireless signals <NUM> may be received by a GNSS antenna <NUM> of GNSS receiver <NUM>. GNSS antenna <NUM> may be a patch antenna, a turnstile antenna, a helical antenna, a parabolic antenna, a phased-array antenna, a resistive plane antenna, a choke ring antenna, a radome antenna, among other possibilities.

Each of GNSS satellites <NUM> may belong to one or more of a variety of system types, such as Global Positioning System (GPS), Satellite-based Augmentation System (SBAS), Galileo, Global Navigation Satellite System (GLONASS), or BeiDou, and may transmit wireless signals having one or more of a variety of signal types (e.g., GPS L1 C/A, GPS L2C, Galileo E1, Galileo E5A, etc.). For example, GNSS satellite <NUM>-<NUM> may be a GPS satellite and may transmit wireless signals having a GPS L1 C/A signal type (i.e., wireless signals having frequencies within the GPS L1 band and having been modulated using C/A code). GNSS satellite <NUM>-<NUM> may additionally or alternatively transmit wireless signals having a GPS L2C signal type (i.e., wireless signals having frequencies within the GPS L2 band and having been modulated using L2 civil codes). In some embodiments, GNSS satellite <NUM>-<NUM> may additionally be a Galileo satellite and may transmit wireless signals having a Galileo signal type (e.g., Galileo E1). Accordingly, a single satellite may include the ability to transmit wireless signals of a variety of signal types.

GNSS receiver <NUM> may use the distance estimates between itself and GNSS satellites <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM> to generate a position estimate through trilateration as described in reference to <FIG>. For example, multiple spheres may be generated having center locations corresponding to the locations of GNSS satellites <NUM> and radii corresponding to the distance estimates (i.e., pseudoranges), with the intersection point(s) of the spheres used to determine the position estimate for GNSS receiver <NUM>. The position estimate may be continuously, periodically, or intermittently updated by generating new distance estimates and performing trilateration using the new distance estimates. Subsequent position estimates may benefit from previous position estimates through filtering processes (e.g., Kalman filtering) capable of improving position estimate accuracy. Position estimates may also be determined using other techniques. In practice, a fourth satellite may be observed to estimate the receiver clock error with respect to the satellite system time.

Mobile base station <NUM>-<NUM> and stationary base station <NUM>-<NUM> may include GNSS antennas <NUM>-<NUM> and <NUM>-<NUM>, respectively, where GNSS antenna <NUM>-<NUM> is positioned at a known position (e.g., XK,YK,ZK). Mobile base station <NUM>-<NUM> may be movable such that multiple mobile base stations <NUM>-<NUM> may be brought within or surrounding a project site so as to provide high-accuracy position estimates. Each of GNSS antennas <NUM> may be similar to GNSS antenna <NUM> and may be configured to receive one or more of wireless signals <NUM>. For example, each of GNSS antennas <NUM> may be a patch antenna, a turnstile antenna, a helical antenna, a parabolic antenna, a phased-array antenna, a resistive plane antenna, a choke ring antenna, a radome antenna, among other possibilities.

Each of base stations <NUM> may send a correction signal <NUM> containing correction data to GNSS receiver <NUM>. The correction data is used by GNSS receiver <NUM> to improve the accuracy of its position estimate. In some embodiments, the correction data includes a plurality of carrier phases Φ<NUM> ,Φ<NUM>,. , ΦJ, where J is the number of GNSS satellites. In some embodiments, the correction data includes a 3D offset amount (e.g., XC,YC,ZC) for modifying the position estimate of GNSS receiver <NUM>. In one example, position estimates of stationary base station <NUM>-<NUM> made using GNSS antenna <NUM>-<NUM> are compared to the known position and the correction data may be generated based on the comparison. In some embodiments, the correction data includes any one of various types of raw or processed satellite data.

Correction signals <NUM> containing the correction data may be wirelessly transmitted by base stations <NUM> using correction antennas <NUM> and may be received by GNSS receiver <NUM> using a correction antenna <NUM>. The correction signals <NUM> may be transmitted continuously, periodically, or intermittently by base stations <NUM>. In some embodiments, correction signals <NUM> are transmitted over a set of wireless frequencies outside the GNSS frequencies (e.g., lower than the GNSS frequencies). In some embodiments, correction antennas <NUM> may be used for transmission only and correction antenna <NUM> may be used for reception only, although in some embodiments additional handshaking between GNSS receiver <NUM> and base stations <NUM> may occur.

<FIG> illustrates an example block diagram of GNSS receiver <NUM>, according to some embodiments of the present disclosure. GNSS receiver <NUM> includes antenna <NUM> for receiving wireless signals <NUM> and sending/routing wireless signals <NUM> to a radio-frequency (RF) front end <NUM>. RF front ends are well known in the art, and in some instances include a band-pass filter <NUM> for initially filtering out undesirable frequency components outside the frequencies of interest, a low-noise amplifier (LNA) <NUM> for amplifying the received signal, a local oscillator <NUM> and a mixer <NUM> for down converting the received signal from RF to intermediate frequencies (IF), a band-pass filter <NUM> for removing frequency components outside IF, and an analog-to-digital (A/D) converter <NUM> for sampling the received signal to generate digital samples <NUM>.

In some instances, RF front end <NUM> includes additional or fewer components than that shown in <FIG>. For example, RF front end <NUM> may include a second local oscillator (<NUM> degrees out of phase with respect to the first), a second mixer, a second band-pass filter, and a second A/D converter for generating digital samples corresponding to the quadrature component of wireless signals <NUM>. Digital samples corresponding to the in-phase component of wireless signals <NUM> and digital samples corresponding to the quadrature component of wireless signals <NUM> may both be sent to a correlator <NUM>. In some embodiments, digital samples corresponding to both in-phase and quadrature components may be included in digital samples <NUM>.

Other components within RF front end <NUM> may include a phase-locked loop (PLL) for synchronizing the phase of local oscillator <NUM> with the phase of the received signal, and a phase shifter for generating a second mixing signal using local oscillator <NUM> that is <NUM> degrees out of phase with local oscillator <NUM>. In some embodiments, RF front end <NUM> does not include band-pass filter <NUM> and LNA <NUM>. In some embodiments, A/D converter <NUM> is coupled directly to antenna <NUM> and samples the RF signal directly without down-conversion to IF. In some embodiments, RF front end <NUM> only includes band-pass filter <NUM> and A/D converter <NUM>. Other possible configurations of RF front end <NUM> are possible.

Digital samples <NUM> generated by RF front end <NUM> may be sent to a correlator <NUM>, which may perform one or more correlations on digital samples <NUM> using local codes. Operation of correlator <NUM> may be controlled by control parameters <NUM> generated by a receiver processor <NUM>. Correlator <NUM> may generate correlation results <NUM> based on digital samples <NUM> and control parameters <NUM> and send these results to receiver processor <NUM>. In some embodiments, one or more operations performed by correlator <NUM> may alternatively be performed by receiver processor <NUM>. In some embodiments, correlator <NUM> is a specific piece of hardware, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). In some embodiments, operations performed by correlator <NUM> are performed entirely in software using digital signal processing (DSP) techniques.

Based on multiple distance estimates corresponding to multiple GNSS satellites <NUM>, as well as correction data <NUM> generated by a correction receiver <NUM> having correction hardware <NUM>, receiver processor <NUM> may generate and output position data <NUM> comprising a plurality of GNSS points. Each of the plurality of GNSS points may be a 3D coordinate represented by three numbers. In some embodiments, the three numbers may correspond to latitude, longitude, and elevation/altitude. In other embodiments, the three numbers may correspond to X, Y, and Z positions. Position data <NUM> may be outputted to be displayed to a user, transmitted to a separate device (e.g., computer, smartphone, server, etc.) via a wired or wireless connection, or further processed, among other possibilities.

<FIG> illustrates an example block diagram of GNSS receiver <NUM> implemented as a multi-channel GNSS receiver, according to some embodiments of the present disclosure. In the illustrated example, GNSS receiver <NUM> includes M front ends <NUM>, each configured to generate and output N I/Q digital samples <NUM>. Correlator <NUM> may include L baseband channels <NUM>, each configured to receive each of the sets of I/Q samples <NUM>. Each of baseband channels <NUM> may include an input multiplexer <NUM> that selects one of the inputs based on control parameters <NUM>. For example, control parameters <NUM> may cause input multiplexer <NUM>-<NUM> to select I/Q samples <NUM>-<NUM> and input multiplexer <NUM>-<NUM> to select I/Q samples <NUM>-<NUM>. Each of baseband channels <NUM> may generate and output results <NUM> that are fed into receiver processor <NUM>.

Each of front ends <NUM> and baseband channels <NUM> may be configured to process different frequencies and/or GNSS signal types. In one implementation, GNSS receiver <NUM> may be configured to process GPS L1/L2/L5, GLONASS L1/L2/L3, and BeiDou B1, B2 signals. In various embodiments, such signals may be processed sequentially, concurrently, or simultaneously. In some embodiments, each of front ends <NUM> may be configured to process a single GNSS signal type while each of baseband channels <NUM> may be configured to process any GNSS signal type. For example, in one implementation, front end <NUM>-<NUM> may be configured to process only GPS L1 signals and front end <NUM>-<NUM> may be configured to process only GPS L2 signals while each of baseband channels <NUM>-<NUM> and <NUM>-<NUM> may be configured to process both GPS L1 signals and GPS L2 signals. Other possibilities are contemplated.

<FIG> illustrates an example block diagram of a correlator <NUM>, according to some embodiments of the present disclosure. A single sample from I/Q samples <NUM>-<NUM> is labeled in <FIG> as {Q,I} sample, RF #<NUM>, a single sample from I/Q samples <NUM>-<NUM> is labeled as {Q,I} sample, RF #<NUM>, and a single sample from I/Q samples <NUM>-M is labeled as {Q,I} sample, RF #M. Each of the {Q,I} samples are provided to each of baseband channels <NUM>, and a particular {Q,I} sample is selected by each of input multiplexers <NUM>.

Each of baseband channels <NUM> includes a similar internal architecture which includes an input multiplexer to select the specified RF front-end output. Each baseband channel also includes a carrier NCO that generates samples of "Carrier + Doppler" phase, which are used to drive a sine-cosine look-up table (LUT) to get sin() and cos() waves. These waves are used as one input of a complex multiplier, referred to as a carrier rotator, which may complete down conversion from relatively low IF to baseband. Each baseband channel also includes a PRN NCO that generates samples of pseudo random noise phase, which are used to drive the PRN generator to obtain a PRN wave.

Early, punctual, and late delay lines (denoted as "E", "P", and "L", respectively) form copies of the PRN wave spaced by <NUM> PRN element (PRN-chip). The punctual output of the delay line goes directly to a multiplier. If the punctual output is aligned to the PRN of the received signal, this operation converts the received PRN alternations to constant level which are accumulated by an accumulator (denoted by the summation symbol) over one or several PRN periods. Output of the accumulator is treated as a metric of misalignment between the locally generated carrier and the received carrier. The early and late outputs go to a strobe former, which serves to create a kind of PRN sequence derivative. The resulting early-minus-late sequence includes a series of short pulses at places where the PRN wave changes. By multiplying the sequence with the received signal and accumulating the result over one or several PRN periods, a metric of misalignment is obtained between the locally generated PRN and the received PRN.

In some embodiments, baseband processing is controlled by receiver processor <NUM> by algorithms implemented in firmware, through control registers, with one goal being to achieve as good alignment as possible between the locally generated PRNs and the received PRNs. The alignment precision may be limited by various factors such as the presence of thermal noise, jamming, multi-path propagation, and so on. In some embodiments, correlator <NUM> may be implemented as an ASIC, which incorporates the whole set of parallel baseband channels.

As the number of GNSS constellations, the number of GNSS satellites in each constellation, and the number of signals transmitted by each GNSS satellite grows, more and more baseband channels are utilized. To keep reasonable values of power consumption and silicon die area, the feasibility of the various modern silicon fabrication technologies have been considered. FPGAs can be produced in high volumes and offer fast operation speeds at reasonable power consumption. One modern trend in the FPGA industry is to produce system on a chips (SoCs) which combine one or several central processing unit (CPU) cores, some peripheral components, and an FPGA on a single silicon die. While GNSS receivers can be fabricated with such designs, FPGAs still have their classic drawbacks, including having programmable slices which are much less effective in terms of consumed area compared to ASIC custom logic.

One technique to compensate for the inefficiencies of FPGAs is to increase the processing clock rate. By configuring the processing clock rate to be several times faster than the GNSS signal sampling frequency, the same logic circuits (e.g., the same FPGA slices) can be re-used as many times as the "processing clock rate"-to-"sampling frequency" ratio.

<FIG> illustrates an example block diagram of a correlator <NUM>, according to some embodiments of the present disclosure. In the illustrated example, M sets of I/Q samples <NUM> are provided to M double buffers <NUM>. After passing through double buffers <NUM>, the I/Q samples are provided to input multiplexers <NUM> which select which samples are provided to N pipelines <NUM>. Each of pipelines <NUM> comprises <NUM> stages which are separated by stage latches <NUM>. A first pipeline <NUM>-<NUM> receives control data <NUM> from receiver processor <NUM> and generates a first set of interconnect data <NUM>-<NUM> based on control data <NUM> and a first selected set of I/Q samples <NUM>. Concurrently with operation of first pipeline <NUM>-<NUM>, a second pipeline <NUM>-<NUM> receives interconnect data <NUM>-<NUM> from first pipeline <NUM>-<NUM> and generates a second set of interconnect data <NUM>-<NUM> based on first interconnect data <NUM>-<NUM> and a second selected set of I/Q samples <NUM>. Concurrently with operation of first pipeline <NUM>-<NUM> and second pipeline <NUM>-<NUM>, an Nth pipeline <NUM>-N receives interconnect data <NUM>-N-<NUM> from a preceding pipeline and generates results <NUM> based on interconnect data <NUM>-N-<NUM> and an Nth selected set of I/Q samples <NUM>.

<FIG> illustrate an example block diagram of correlator <NUM> in greater detail, according to some embodiments of the present disclosure. In some embodiments, each of pipelines <NUM> can be considered as a pipelined version of a single baseband channel of correlator <NUM>. For example, each pipeline may consist of essentially the same set of modules (NCOs, generators, etc.) as each of baseband channels <NUM>. One notable difference is that all the modules are separated from each other with stage latches <NUM>, which allow the states of pipelines <NUM> to be updated with a rate much faster than in the original scheme due to the fewer number of logic gates between latches, providing shorter signal propagation paths. For example, let FOP be the pipeline operation frequency, Fs be the sampling frequency, and TS = <NUM>/FS be the corresponding sampling frequency, resulting in OF = FOP/FS as the overclock factor, which may be a value greater than <NUM>.

Each of double buffers <NUM> is utilized for {Q,I} samples for each of pipelines <NUM>. Each buffer consists of two parts, each of which can store N number of {Q,I}-samples. While the first part of each buffer (indicated by latches "D") accumulates a stream of input {Q,I}-samples incoming at a rate of FS, the second part (indicated by latches "L") contains N number of {Q,I}-samples collected over the previous operational period(s). Thus each operational period P is (N × TS) length. The number of overall buffered {Q,I}-samples is (N × M), where M is the number of RF front ends and therefore the number of double buffers <NUM>. These previously collected {Q,I}-samples may stay unchanged during each operation period P and are available for subsequent processing performed by any of pipelines <NUM>. Because each of the pipelines operate OF times faster than FS, a particular N-length subset of (N × M) previously collected {Q,I}-samples from the second part of the double buffer can be provided as inputs to a pipeline <NUM> OF times during the current operational period P. Thus, each of the pipelines <NUM> (e.g., same logic circuits) can be reused OF times but just serve a single RF channel. Thus, the processing done by a single pipeline is comparable to OF traditional baseband channels connected to a single RF front end.

In some embodiments, correlator <NUM> combines multiple pipelines <NUM> into a large convolution computation engine that can be applied to GNSS signal processing. Such a configuration increases the number of equivalent traditional baseband channels available with the same amount of FPGA logic up to (N × OF), with N being the number of pipelines.

In some embodiments, the second part of the double buffer copies {Q,I}-samples from the first part of the double buffer with a rate N times slower than FS. The counter modulo N counter performs N-times division of the FS clock and generates a latch enable signal for the "L" latches to copy the collected {Q,I}-samples from the first part to the second part of the double buffers. There are M buffers in this scheme, where Mis number of front-ends used in the RF section of the receiver.

Pipelines <NUM> are preceded by input multiplexers <NUM> that are controlled by an "RF-Input Select" word which comes from a double buffer storage for controls coming from receiver processor <NUM>. The storage is addressed by the channel ID cyclic counter, which updates its state with (OF × FS) rate and provides all (N × OF) channel identifiers to control stores, while {Q,I}-samples stay unchanged at outputs of the second stage of the double buffers. The counter output can be used for addressing the read port of control stores. In some instances, as the scheme operates continuously, a read-to-write collision could otherwise occur when the controls are be updated from the CPU side but for the set of control double buffers.

In accordance with some embodiments, multiplexed {Q,I}-sample #<NUM> may enter into and propagate through Stage <NUM> and Stage <NUM> of the pipeline <NUM>-<NUM> without changes. In parallel, these pipeline stages update carrier and code NCO phases (at Stage <NUM>) and carrier and code generators outputs (at Stage <NUM>). The resulting NCO phases and generators outputs correspond to {Q,I}-sample #<NUM> multiplexed for the equivalent baseband channel identified by output of the channel ID cyclic counter. At Stage <NUM>, the carrier rotator completes the conversion of the input signal to baseband. In parallel, early, punctual, and late copies of the reference PRN are computed. At Stage <NUM>, the early-minus-late strobe is computed while the carrier rotator output goes through the stage without change. At Stage <NUM>, the carrier rotator output is multiplied by the reference PRN and the early-minus-late strobe. At Stage <NUM>, the pipeline processing is completed by accumulating the results of the multipliers.

As the channel ID cyclic counter is updated each (OF × FS) clock, the particular control word for the next equivalent baseband channel is read. Next, the input multiplexer selects the {Q,I}-sample in accordance with the setting for each equivalent baseband channel each such clock. The (OF × FS) clock also drives stage latches <NUM> of each pipeline, allowing each stage of each pipeline to process data for different equivalent baseband channels concurrently. For example, consider pipeline <NUM>-<NUM> after <NUM> clocks from the moment {Q,I}-samples were copied from the first part to the second part of the input samples buffer:.

While a single pipeline is equivalent to OF number of traditional baseband channels (as described above), the equivalency is enlarged by N times with the additional (N-<NUM>) pipelines and appropriate interconnect data <NUM>, which behave as inter-pipe connections. In some embodiments, interconnect data <NUM> may be organized by storing, for each of pipelines <NUM>-<NUM> through <NUM>-N-<NUM>, the updated states of the accumulating values in stage latches <NUM> and providing these states as inputs for the same stages of pipelines <NUM>-<NUM> through <NUM>-N, respectively.

In some embodiments, dual port RAM blocks are used to store states of all processing units (e.g., the carrier NCO phase, the PRN NCO phase, the content of PRN generator registers and so on) from one operational period P to another. These states are output from the stage latches of pipeline <NUM>-N. The RAM storing ports (labeled as "a", "b",. "f" in circles) are addressed by appropriately delayed values of the channel ID cyclic counter (e.g., the delay latches may be part of pipeline stage latches and are not shown in the scheme). The RAM read ports (the upper ports in the illustrated example) are used for reading the states for units of the appropriate equivalent baseband channel. These ports are addressed either by the channel ID cyclic counter directly or by a corresponding delayed value of the counter. The RAM outputs are fed into stages of pipeline <NUM>-<NUM> where they are used for the first time for processing the first {Q,I}-sample of the newly copied {Q,I}-samples.

In some embodiments, {Q,I}-sample #<NUM> may pass through a single delay latch (pre-pipeline latch <NUM>-<NUM>) prior to entry into Stage <NUM> of pipeline <NUM>-<NUM>. The sample then passes through the stage without changing similar to {Q,I}-sample #<NUM> in pipeline <NUM>-<NUM>. In parallel, the code and carrier NCOs of pipeline <NUM>-<NUM> update their phases at this stage. As a result, the output of the NCOs phases at Stage <NUM> of pipeline <NUM>-<NUM> corresponds to {Q,I}-sample #<NUM> similar to how the NCOs phases at Stage <NUM> of pipeline <NUM>-<NUM> corresponded to {Q,I}-sample #<NUM> at one pipeline operation clock before. Similarly, {Q,I}-sample #<NUM> may pass through <NUM> delay latches prior to entry into Stage <NUM> of the third pipeline. This continues until {Q,I}-sample #N passes through N-<NUM> delay latches prior to entry into Stage <NUM> of pipeline <NUM>-N. Thus, Stage <NUM> for all pipelines <NUM> generate NCOs phases corresponding to {Q,I}-samples #<NUM>. The same applies to all stages of each pipeline: units in the stages update their states synchronously to the {Q,I}-samples which should be processed using the outputs of the units.

As mentioned above, {Q,I}-samples (at the double buffer samples output) stay unchanged during the operational period P. At each of the pipeline operation clocks corresponding to (OF × FS), all N input multiplexers <NUM> select a N-length subset of (N × M) buffered {Q,I}-samples in accordance with the RF-input select control word for one of the (N × OF) equivalent baseband channels. During the whole {Q,I}-samples stability interval, (N × OF) pipe operational clocks occur and therefore (N × OF) bunches (N-length subsets) of (N × M) buffered {Q,I}-samples are provided to pipelines <NUM>. Thus, during each operational period P, the number of processed bunches of {Q,I}-samples are equal to the number of equivalent channels (N × OF). Once all (N × OF) bunches of {Q,I}-samples have been sent to pipelines <NUM> (e.g. the current operational period P has been completed), the {Q,I}-samples can be copied from the buffer's first part to the second part, and the same processing may be accomplished.

Results <NUM> may correspond to correlation values computed over N samples for each of the (N × OF) equivalent baseband channels. Results <NUM> appear at the output of Stage <NUM> of pipeline <NUM>-N. In some embodiments, they have a latency equal to (<NUM> × N) of the pipeline operation clocks. As the latency is the same for each of the (N × OF) equivalent baseband channels, the latency may be ignored or accounted for in subsequent processing by receiver processor <NUM>. During the (N × OF) pipeline operation clocks, pipelines <NUM> may compute correlation values for each of the (N × OF) equivalent baseband channels.

<FIG> illustrates a method <NUM> for operating a GNSS receiver (e.g., GNSS receiver <NUM>), according to some embodiments of the present disclosure. One or more steps of method <NUM> may be omitted during performance of method <NUM>, and steps of method <NUM> need not be performed in the order shown. Method <NUM> may be implemented as a computer-readable medium or computer program product comprising instructions which, when the program is executed by one or more computers, cause the one or more computers to carry out one or more steps of the method. Such computer program products can be transmitted, over a wired or wireless network, in a data carrier signal carrying the computer program product.

At step <NUM>, sets of digital samples (e.g., I/Q samples <NUM>) associated with received wireless signals are received. In some embodiments, the sets of digital samples may be received by a component of the GNSS receiver such as a correlator (e.g., correlators <NUM>, <NUM>). In some embodiments, the sets of digital samples are received from at least one front end (e.g., front end <NUM>) of the GNSS receiver. In some embodiments, each of the sets of digital samples corresponds to a particular RF path.

At step <NUM>, the sets of digital samples are provided to a plurality of pipelines (e.g., pipelines <NUM>). In some embodiments, each of the plurality of pipelines includes a plurality of stages (e.g., Stages <NUM>-<NUM>). In some embodiments, each of the plurality of stages includes one or more digital logic circuits. In some embodiments, the plurality of stages are separated by a plurality of latches (e.g., stage latches <NUM>). In some embodiments, the one or more digital logic circuits of a particular stage of the plurality of stages are identical to the one or more digital logic circuits of corresponding stages between different pipelines of the plurality of pipelines.

At step <NUM>, sets of interconnect data (e.g., interconnect data <NUM>) are generated by the plurality of pipelines based on the sets of digital samples. In some embodiments, the sets of interconnect data include at least one accumulating value (e.g., the output of addition/summation blocks in Stage <NUM> of pipelines <NUM>). In some embodiments, the sets of interconnect data are generated by one or more of the plurality of pipelines. For example, the sets of interconnect data may be generated by each of the plurality of pipelines except for a last pipeline. In some embodiments, each of the sets of interconnect data are generated by a particular pipeline based on the set of digital samples provided to the particular pipeline and the set of interconnect data passed to the particular pipeline.

In some embodiments, generating the sets of interconnect data based on the sets of digital samples includes generating, by the first pipeline, a first set of interconnect data based on a first set of digital samples of the sets of digital samples and control data provided by a receiver processor, generating, by a second pipeline of the plurality of pipelines, a second set of interconnect data based on a second set of digital samples of the sets of digital samples and the first set of interconnect data, and generating, by a third pipeline of the plurality of pipelines, a third set of interconnect data based on a third set of digital samples of the sets of digital samples and the second set of interconnect data.

At step <NUM>, the sets of interconnect data are passed between adjacent pipelines of the plurality of pipelines. In some embodiments, the sets of interconnect data are passed between adjacent pipelines of the plurality of pipelines along a direction. For example, the first pipeline may generate and pass the first set of interconnect data to the second pipeline, which may generate and pass the second set of interconnect data to the third pipeline.

At step <NUM>, a result may be generated based on the at least one accumulating value. In some embodiments, the last pipeline of the plurality of pipelines may generate the result based on the at least one accumulating value. For example, the output(s) of an accumulator (e.g., addition/summation block) of the last pipeline may be generated and provided to the receiver processor.

Specific details are given in the description to provide a thorough understanding of exemplary configurations including implementations. However, configurations may be practiced without these specific details. For example, well-known circuits, processes, algorithms, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the configurations. The preceding description of the configurations will provide those skilled in the art with an enabling description for implementing described techniques. Various changes may be made in the function and arrangement of elements without departing from the scope of the disclosure.

Also, configurations may be described as a process which is depicted as a schematic flowchart or block diagram. Although each may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional steps not included in the figure. Furthermore, examples of the methods may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments to perform the necessary tasks may be stored in a non-transitory computer-readable medium such as a storage medium. Processors may perform the described tasks.

Having described several example configurations, various modifications, alternative constructions, and equivalents may be used without departing from the scope of the disclosure. For example, the above elements may be components of a larger system, wherein other rules may take precedence over or otherwise modify the application of the technology. Also, a number of steps may be undertaken before, during, or after the above elements are considered.

Claim 1:
A method (<NUM>) comprising:
receiving (<NUM>) sets of digital samples associated with received wireless signals, wherein each of the sets of digital samples corresponds to a particular radio-frequency (RF) path;
providing (<NUM>) the sets of digital samples to a plurality of pipelines, wherein each of the plurality of pipelines includes a plurality of stages, and wherein each of the plurality of stages includes one or more digital logic circuits;
receiving, from a receiver processor, control data for the plurality of pipelines;
providing the control data to a first pipeline of the plurality of pipelines;
generating (<NUM>), by one or more of the plurality of pipelines, sets of interconnect data based on the sets of digital samples, wherein the sets of interconnect data include at least one accumulating value;
passing (<NUM>) the sets of interconnect data between adjacent pipelines of the plurality of pipelines along a direction; and
generating (<NUM>), by a last pipeline of the plurality of pipelines, a result based on the at least one accumulating value;
characterized in that generating the sets of interconnect data based on the sets of digital samples includes:
generating, by the first pipeline, a first set of interconnect data based on a first set of digital samples of the sets of digital samples and the control data;
generating, by a second pipeline of the plurality of pipelines, a second set of interconnect data based on a second set of digital samples of the sets of digital samples and the first set of interconnect data; and
generating, by a third pipeline of the plurality of pipelines, a third set of interconnect data based on a third set of digital samples of the sets of digital samples and the second set of interconnect data.