Patent Description:
Computing devices often utilize a graphics processing unit (GPU) to accelerate the rendering of graphical data for display. Such computing devices may include, for example, computer workstations, mobile phones such as so-called smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of concurrently executing multiple applications, each of which may need to utilize the GPU during execution. A device that provides content for visual presentation on a display generally includes a GPU.

Typically, a GPU of a device is configured to perform the processes in a graphics processing pipeline. However, with the advent of wireless communication and smaller, handheld devices, there has developed an increased need for improved graphics processing.

<NPL>, proposes a Command Processor Networking (ComP-Net), which moves the network service thread from the host CPU to the GPU-resident CP. Modern GPUs are embedded, programmable microprocessors that are typically referred to as Command Processors (CPs). These processors exist on the GPU device itself and are utilized to perform the serial tasks involved with launching and tearing down a GPU kernel. Further, an experiment is proposed to use a simple producer/consumer queue for communication between the CPU and the GPU. No matter where the queue is placed, latencies are high.

<NPL>) discloses a micro-architecture of a core. To execute a wavefront, the fetch unit first fetches the next instruction from instruction cache based on the program counter (PC). The fetched instruction is decoded and placed into an instruction buffer for execution. This buffer is hard partitioned for each wavefront, and the decoded instructions are stored on a per-wavefront basis. The fetch-decode happens in a roundrobin manner for all the wavefronts in a core. This keeps the pipeline full so that on a context switch, a new wavefront is ready to be issued immediately. In our baseline configuration, the buffer can hold two decoded instructions per wavefront, limiting only two instructions from a particular wavefront that can be issued continuously for execution. Also, when a wavefront encounters an L1 miss, the wavefront scheduler will switch out the current wavefront with another ready wavefront to hide the memory latency.

<CIT> proposes that a scheduler manages and schedules event-driven sub-waves based on incoming messages received in host message queue or vector I/O return queue. An incoming message is a host message, I/O message, vector return signal, or other message. Depending on the embodiment, a single event or multiple event combinations invoke a subwave procedure. In one embodiment, scheduler schedules instructions based on the priority of each sub-wave procedure, and the scheduler maintains data coherence and atomic operations across sub-waves. Once a sub-wave procedure is finished, the private VGPR space allocated for that sub-wave is released and can be used by a new sub-wave procedure.

Advantageous embodiments are subject to the dependent claims. In the following, each of the described methods, apparatuses, systems, examples and aspects, which does not fully correspond to the invention as defined in the appended claims, is thus not according to the invention and is, as well as the whole following description, present for illustration purposes only or to highlight specific aspects or features of the appended claims.

In general, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphical content, and/or reducing the load of a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU. For example, this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

As used herein, instances of the term "content" may refer to "graphical content," "image," and vice versa. This is true regardless of whether the terms are being used as an adjective, noun, or other parts of speech. In some examples, as used herein, the term "graphical content" may refer to a content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphical content" may refer to a content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphical content" may refer to a content produced by a graphics processing unit.

In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform displaying processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphical content may be processed to become display content. For example, a graphics processing unit may output graphical content, such as a frame, to a buffer (which may be referred to as a framebuffer). A display processing unit may read the graphical content, such as one or more frames from the buffer, and perform one or more display processing techniques thereon to generate display content. For example, a display processing unit may be configured to perform composition on one or more rendered layers to generate a frame. As another example, a display processing unit may be configured to compose, blend, or otherwise combine two or more layers together into a single frame. A display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on a frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form the frame, i.e., the frame includes two or more layers, and the frame that includes two or more layers may subsequently be blended.

<FIG> is a block diagram that illustrates an example content generation system <NUM> configured to implement one or more techniques of this disclosure. The content generation system <NUM> includes a device <NUM>. The device <NUM> may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device <NUM> may be components of an SOC. The device <NUM> may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, the device <NUM> may include a processing unit <NUM>, and a system memory <NUM>. In some aspects, the device <NUM> can include a number of optional components, e.g., a communication interface <NUM>, a transceiver <NUM>, a receiver <NUM>, a transmitter <NUM>, a display processor <NUM>, and one or more displays <NUM>. Reference to the display <NUM> may refer to the one or more displays <NUM>. For example, the display <NUM> may include a single display or multiple displays. The display <NUM> may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first and second display may receive different frames for presentment thereon. In other examples, the first and second display may receive the same frames for presentment thereon. In further examples, the results of the graphics processing may not be displayed on the device, e.g., the first and second display may not receive any frames for presentment thereon. Instead, the frames or graphics processing results may be transferred to another device. In some aspects, this can be referred to as split-rendering.

The processing unit <NUM> may include an internal memory <NUM>. The processing unit <NUM> may be configured to perform graphics processing, such as in a graphics processing pipeline <NUM>. In some examples, the device <NUM> may include a display processor, such as the display processor <NUM>, to perform one or more display processing techniques on one or more frames generated by the processing unit <NUM> before presentment by the one or more displays <NUM>. The display processor <NUM> may be configured to perform display processing. For example, the display processor <NUM> may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit <NUM>. The one or more displays <NUM> may be configured to display or otherwise present frames processed by the display processor <NUM>. In some examples, the one or more displays <NUM> may include one or more of: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

Memory external to the processing unit <NUM>, such as system memory <NUM>, may be accessible to the processing unit <NUM>. For example, the processing unit <NUM> may be configured to read from and/or write to external memory, such as the system memory <NUM>. The processing unit <NUM> may be communicatively coupled to the system memory <NUM> over a bus. In some examples, the processing unit <NUM> may be communicatively coupled to each other over the bus or a different connection.

The internal memory <NUM> or the system memory <NUM> may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory <NUM> or the system memory <NUM> may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, a magnetic data media or an optical storage media, or any other type of memory.

The internal memory <NUM> or the system memory <NUM> may be a non-transitory storage medium according to some examples. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term "non-transitory" should not be interpreted to mean that internal memory <NUM> or the system memory <NUM> is non-movable or that its contents are static. As one example, the system memory <NUM> may be removed from the device <NUM> and moved to another device. As another example, the system memory <NUM> may not be removable from the device <NUM>.

The processing unit <NUM> may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit <NUM> may be integrated into a motherboard of the device <NUM>. In some examples, the processing unit <NUM> may be present on a graphics card that is installed in a port in a motherboard of the device <NUM>, or may be otherwise incorporated within a peripheral device configured to interoperate with the device <NUM>. The processing unit <NUM> may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit <NUM> may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory <NUM>, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

In some aspects, the content generation system <NUM> can include an optional communication interface <NUM>. The communication interface <NUM> may include a receiver <NUM> and a transmitter <NUM>. The receiver <NUM> may be configured to perform any receiving function described herein with respect to the device <NUM>. Additionally, the receiver <NUM> may be configured to receive information, e.g., eye or head position information, rendering commands, or location information, from another device. The transmitter <NUM> may be configured to perform any transmitting function described herein with respect to the device <NUM>. For example, the transmitter <NUM> may be configured to transmit information to another device, which may include a request for content. The receiver <NUM> and the transmitter <NUM> may be combined into a transceiver <NUM>. In such examples, the transceiver <NUM> may be configured to perform any receiving function and/or transmitting function described herein with respect to the device <NUM>.

Referring again to <FIG>, in certain aspects, the graphics processing pipeline <NUM> may include a determination component <NUM> configured to determine one or more context states of at least one context register in each of multiple wave slots. The determination component <NUM> can also be configured to send information corresponding to the one or more context states in one of the multiple wave slots to a context queue. Additionally, the determination component <NUM> can be configured to convert the information corresponding to the one or more context states to context information compatible with the context queue. The determination component <NUM> can also be configured to store the context information compatible with the context queue in the context queue. In some aspects, the determination component <NUM> can be configured to remove the one or more context states of at least one context register from the one of the wave slots when the information corresponding to the one or more context states is sent to the context queue. In further aspects, the determination component <NUM> can be configured to send the context information compatible with the context queue to one of the multiple wave slots. Moreover, the determination component <NUM> can be configured to convert the context information compatible with the context queue to the information corresponding to the one or more context states. The determination component <NUM> can also be configured to copy the information corresponding to the one or more context states when the information corresponding to the one or more context states is sent to the context queue. In some aspects, the determination component <NUM> can also be configured to convert the multiple wave slots to multiple execution slots. Further, the determination component <NUM> can be configured to send wave data corresponding to the one of the wave slots to one of multiple execution units. The determination component <NUM> can also be configured to receive wave data corresponding to the one of the multiple wave slots from one of multiple execution units.

As described herein, a device, such as the device <NUM>, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, user equipment, a client device, a station, an access point, a computer, e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device, e.g., a portable video game device or a personal digital assistant (PDA), a wearable computing device, e.g., a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-car computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described as performed by a particular component (e.g., a GPU), but, in further embodiments, can be performed using other components (e.g., a CPU), consistent with disclosed embodiments.

GPUs can process multiple types of data or data packets in a GPU pipeline. For instance, in some aspects, a GPU can process two types of data or data packets, e.g., context register packets and draw call data. A context register packet can be a set of global state information, e.g., information regarding a global register, shading program, or constant data, which can regulate how a graphics context will be processed. For example, context register packets can include information regarding a color format. In some aspects of context register packets, there can be a bit that indicates which workload belongs to a context register. Also, there can be multiple functions or programming running at the same time and/or in parallel. For example, functions or programming can describe a certain operation, e.g., the color mode or color format. Accordingly, a context register can define multiple states of a GPU.

Context states can be utilized to determine how an individual processing unit functions, e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor, and/or in what mode the processing unit functions. In order to do so, GPUs can use context registers and programming data. In some aspects, a GPU can generate a workload, e.g., a vertex or pixel workload, in the pipeline based on the context register definition of a mode or state. Certain processing units, e.g., a VFD, can use these states to determine certain functions, e.g., how a vertex is assembled. As these modes or states can change, GPUs may need to change the corresponding context. Additionally, the workload that corresponds to the mode or state may follow the changing mode or state.

<FIG> illustrates an example GPU <NUM> in accordance with one or more techniques of this disclosure. As shown in <FIG>, GPU <NUM> includes command processor (CP) <NUM>, draw call packets <NUM>, VFD <NUM>, VS <NUM>, vertex cache (VPC) <NUM>, triangle setup engine (TSE) <NUM>, rasterizer (RAS) <NUM>, Z process engine (ZPE) <NUM>, pixel interpolator (PI) <NUM>, fragment shader (FS) <NUM>, render backend (RB) <NUM>, L2 cache (UCHE) <NUM>, and system memory <NUM>. Although <FIG> displays that GPU <NUM> includes processing units <NUM>-<NUM>, GPU <NUM> can include a number of additional processing units. Additionally, processing units <NUM>-<NUM> are merely an example and any combination or order of processing units can be used by GPUs according to the present disclosure. GPU <NUM> also includes command buffer <NUM>, context register packets <NUM>, and context states <NUM>.

As shown in <FIG>, a GPU can utilize a CP, e.g., CP <NUM>, or hardware accelerator to parse a command buffer into context register packets, e.g., context register packets <NUM>, and/or draw call data packets, e.g., draw call packets <NUM>. The CP <NUM> can then send the context register packets <NUM> or draw call data packets <NUM> through separate paths to the processing units or blocks in the GPU. Further, the command buffer <NUM> can alternate different states of context registers and draw calls. For example, a command buffer can be structured as follows: context register of context N, draw call(s) of context N, context register of context N+<NUM>, and draw call(s) of context N+<NUM>.

In some aspects, for each GPU processing unit or block, a context register may need to be prepared before any draw call data can be processed. As context registers and draw calls can be serialized, it can be helpful to have an extra context register prepared before the next draw call. In some instances, draw calls of the next context can be fed through the GPU data pipeline in order to hide context register programming latency. Further, when a GPU is equipped with multiple sets of context registers, each processing unit can have sufficient context switching capacity to manage smooth context processing. In turn, this can enable the GPU to cover pipeline latency that can result from unpredictable memory access latency and/or extended processing pipeline latency.

<FIG> illustrates an example GPU <NUM> in accordance with one or more techniques of this disclosure. More specifically, <FIG> illustrates a streaming processor (SP) system in GPU <NUM>. As shown in <FIG>, GPU <NUM> includes high level sequencer (HLSQ) <NUM>, VPC <NUM>, thread processor (TP) <NUM>, UCHE <NUM>, RB <NUM>, and VPC <NUM>. GPU <NUM> also includes SP <NUM>, master engine <NUM>, sequencer <NUM>, local memory <NUM>, wave scheduler and context register <NUM>, texture unit (TEX) or load controller <NUM>, instruction cache <NUM>, execution units (EUs) <NUM>, general purpose register (GPR) <NUM>, distributor <NUM>, constant RAM <NUM>, and distributor <NUM>. The wave scheduler and context register <NUM> can also include one or more wave slots.

As shown in <FIG>, the SP <NUM> can include traditional function units or blocks, e.g., EUs <NUM> or sequencer <NUM>. EUs <NUM> can execute or process some of the desired functions of the GPU. The sequencer <NUM> can allocate resources and local memory, as well as store local memory. Also, the sequencer <NUM> can allocate wave slots and any associated GPR <NUM> space. For example, the sequencer <NUM> can allocate wave slots or GPR <NUM> space when the HLSQ <NUM> issues a pixel tile workload to the SP <NUM>. In some aspects, the wave scheduler <NUM> can execute a pixel shader or issue instructions to the EUs <NUM>. The EUs <NUM> can also include an arithmetic logic unit (ALU) and/or an elementary function unit (EFU). Further, the TEX or load controller <NUM> can be considered an execution unit.

Additionally, the TEX or load controller <NUM> can correspond to one or multiple units. For instance, the TEX <NUM> can perform a texture fetch and/or the load controller <NUM> can perform a memory fetch. In some aspects, the instruction cache <NUM> can store a workload or program to be executed. Also, the constant RAM <NUM> can store the constant that is needed for a constant or uniform formation. As further shown in <FIG>, the SP <NUM> can interface with the outside blocks, e.g., HLSQ <NUM>, VPC <NUM>, TP <NUM>, UCHE <NUM>, RB <NUM>, and VPC <NUM>. These blocks <NUM>-<NUM> can utilize user provided input and/or the SP can output results to these blocks or memory access.

As shown in <FIG>, each unit or block in GPU <NUM> can send data or information to other blocks. For instance, HLSQ <NUM> can send commands to the master engine <NUM>. Also, HLSQ <NUM> can send vertex threads, vertex attributes, pixel threads, and/or pixel attributes to the sequencer <NUM>. VPC <NUM> can send certain coefficients to local memory <NUM>. TP <NUM> can send texture data to the TEX <NUM>. TP <NUM> can also receive texture requests from TEX <NUM>, e.g., via distributor <NUM>, and bypass requests from local memory <NUM>. Further, TP <NUM> can send requests to and receive texture elements (texels) from UCHE <NUM>. UCHE <NUM> can also send memory to and receive memory from TEX <NUM>, as well as send memory to and receive memory from RB <NUM>. Also, RB <NUM> can receive an output in the form of color from GPR <NUM>, e.g., via distributor <NUM>. VPC <NUM> can also receive output in the form of vertices from GPR <NUM>, e.g., via distributor <NUM>. GPR <NUM> can also send temporary data to and receive temporary data from EUs <NUM>. Moreover, EUs <NUM> can send address or predicate information to the wave scheduler <NUM>, as well as receive constant data from constant RAM <NUM>. TEX or load controller <NUM> can also send/receive load or store data to/from GPR <NUM>, as well as send store data to and receive load data from local memory <NUM>. Further, TEX or load controller <NUM> can send global data to constant RAM <NUM> and update information to the instruction cache <NUM>. TEX or load controller <NUM> can also receive attribute data from sequencer <NUM> and synchronization information from wave scheduler <NUM>. Additionally, wave scheduler <NUM> can receive decode information from instruction cache <NUM> and thread data from sequencer <NUM>.

As mentioned above, the GPU <NUM> can process workloads, e.g., a pixel or vertex workload. In some aspects, these workloads can correspond to, or be referred to as, waves or wave formations. For instance, each workload or operation can use a group of vertices or pixels as a wave. For example, each wave can include a number of different components to perform a workload or operation, e.g., <NUM> or <NUM> components. In some instances, GPU <NUM> can send a wave formation, e.g., a pixel or vertex workload, to the wave scheduler <NUM> for execution. For a vertex workload, the GPU can perform a vertex transformation. For a pixel workload, the GPU can perform a pixel shading or lighting.

As indicated above, each of the aforementioned processes or workloads, e.g., the processes or workloads in the SP <NUM>, can include a wave formation. For example, during a vertex workload, a number of vertices, e.g., three vertices, can form a triangle or primitive. The GPU can then perform a transformation of these vertices, such that the vertices can transform into a wave. In order to perform this transformation, GPUs can utilize a number of a wave slots, e.g., to help transform the vertices into a wave. Further, in order to execute a workload or program, the GPU can also allocate the GPR space, e.g., including a temporary register to store any temporary data. Additionally, the sequencer <NUM> can allocate the GPR <NUM> space and one or more wave slots in order to execute a wave. For example, the GPR <NUM> space and one or more wave slots can be allocated when a pixel or vertex workload are issued.

In some aspects, the wave scheduler <NUM> can process a pixel workload and/or issue instructions to various execution units, e.g., EUs <NUM>. The wave scheduler <NUM> can also help to ensure data dependency between instructions, e.g., data dependency between ALU operands due to the pipeline latency and/or texture sample return data dependency based on a synchronization mechanism. Additionally, the wave scheduler <NUM> can have a load reference counter (LRC) to count outstanding texture or memory requests that are issued to the TP <NUM> or UCHE <NUM>, as well as a corresponding data return request. In some aspects, if the LRC value is greater than zero, this can indicate there is outstanding data. As such, instructions that are dependent on the return of the outstanding data may not be able to execute until the LRC value decreases to zero.

As mentioned above, GPUs can experience memory or pipeline latency when processing various instructions. In some aspects, latency can be categorized based on data dependency that occurs within or outside of the SP. For instance, data dependency that occurs within the SP, i.e., SP internal data dependency, can be data dependency between ALUs or between an EFU and an ALU. This type of latency can be relatively short compared to other memory latency, e.g., less than <NUM> processing cycles. Additionally, data dependency that occurs outside the SP, i.e., SP external data dependency, can be data dependency based on texture sample or memory return data. This type of latency can be relatively long compared to other memory latency, e.g., greater than <NUM> processing cycles. As the SP internal data latency is relatively short compared to other memory latency, it can account for internal data latency and/or enable a high efficiency parallel EU execution with a low number of wave slots, e.g., four to six wave slots. However, for longer SP external data latency, the number of wave slots needed to account for the latency can be larger, e.g., <NUM> to <NUM> wave slots.

In some aspects, GPUs can experience memory or pipeline latency when a wave instruction is issued. In order to account for this latency, GPUs may issue more instructions, e.g., texture sample instructions, to ensure that the pipeline is fully utilized. Additionally, the processing time for a group of pixels may depend on the throughput. For example, a group pixels may take a number of cycles, e.g., <NUM> cycles, to process. In some instances, the memory latency can be greater than this amount of cycles, e.g., up to <NUM> cycles. As a result, the data may return from processing even more cycles after this, e.g., <NUM> cycles later. Accordingly, processing a group pixels, e.g., <NUM> pixels, may not be sufficient to cover the pipeline latency. Further, the SP capacity to process more pixel tiles, as well as more texture sample instructions, can be limited by the amount of wave slots and/or GPR size. For instance, if there is one wave slot, then GPUs may have to wait for the data to process and cycle through the system before processing the next wave. In some aspects, a GPU can accept new pixels to form another wave, but the GPU may have to wait to fill the pipeline to account for the latency.

In order to account for increased pipeline latency, aspects of the present disclosure may increase the amount of wave slots. For example, for the waves to be processed at the same time, i.e., processed in parallel, aspects of the present disclosure may need a certain amount of wave slots, e.g., four, eight, or <NUM> wave slots. When adding wave slots, aspects of the present disclosure may also need additional GPR space to account for the processing completion time. Accordingly, the amount of wave slots and GPR space can be important resources to allow for more waves to process simultaneously, e.g., in order to account for pipeline latency. So aspects of the present disclosure may utilize an increased number of wave slots in order to allow the waves to be processed simultaneously or in parallel.

In order to increase the wave processing capacity of the system, or the ability to cover pipeline latency, GPUs may include an increased number of wave slots. However, one problem with increasing the amount of wave slots and/or GPR size is that both resources are expensive. For example, GPUs may need information, e.g., the number of pixels, or instructions in order to execute a wave at a wave slot, such that each additional wave slot increases the system operation cost. Further, wave slots can log the information for the wave execution status, so the system can proceed with the wave processing, which can also increase operation costs. Additionally, in order to increase the amount of wave slots, GPUs may need to increase the corresponding storage space for the wave slots. For example, in order to double the wave slot capacity, GPUs may need to double the size of the storage. As such, increasing the amount of wave slots can increase both the operation cost and the amount of required storage space.

<FIG> illustrates an example GPU <NUM> in accordance with one or more techniques of this disclosure. More specifically, <FIG> illustrates components or units within SP <NUM> in GPU <NUM>. As shown in <FIG>, GPU <NUM> includes a number of execution units, e.g., flow control branch <NUM>, EFU <NUM>, ALU <NUM>, TEX <NUM>, and load store (LDST) <NUM>. GPU <NUM> can include a number of additional execution units, as execution units <NUM>-<NUM> are merely an example and any combination or order of execution units can be used by GPUs herein. GPU <NUM> can also include data cross bar <NUM>, which can also be referred to as multiple thread manager <NUM>, as well as level zero (L0) cache <NUM>. Further, GPU <NUM> includes a number of wave slots, e.g., wave slots <NUM>-<NUM>. For ease of illustration, wave slots <NUM>-<NUM> are not shown in <FIG>. GPU <NUM> can include any number of different wave slots, as wave slots <NUM>-<NUM> are merely an example. In some aspects, wave slots <NUM>-<NUM> can be part of a wave scheduler.

As shown in <FIG>, each component in GPU <NUM> can communicate with a number of other components. For instance, each of the execution units <NUM>-<NUM> can send or receive data or instructions, e.g., requests or grants, to/from the data cross bar <NUM>. Also, each of the wave slots <NUM>-<NUM> can send or receive data or instructions, e.g., requests or grants, to/from the data cross bar <NUM>. Further, data cross bar <NUM> can store data in, or receive data from, the L0 cache <NUM>. Each of the execution units <NUM>-<NUM>, e.g., flow control branch <NUM>, EFU <NUM>, ALU <NUM>, TEX <NUM>, and LDST <NUM>, can also send or receive data or instructions to/from the wave slots <NUM>-<NUM>. In some aspects, each of the wave slots <NUM>-<NUM> can issue instructions simultaneously to each of the execution units <NUM>-<NUM>.

<FIG> illustrates that GPU <NUM> includes ten wave slots <NUM>-<NUM>. In some aspects, the wave slots <NUM>-<NUM> can be referred to as flat wave slots, as each of the wave slots <NUM>-<NUM> can execute wave instructions on an individual basis without regard for the other wave slots. When an individual wave instruction is processing through the system, the corresponding wave slot can wait for the wave instruction to return, i.e., the wave slot can be in standby mode. Additionally, the context registers used in the wave slot logic can control wave execution and be flop-based, such as to enable switching between wave slots in order to access different EUs. As such, these context registers may need updating frequently. Also, as discussed previously, increasing the number of wave slots can be expensive.

In some aspects, increasing the number of wave slots can utilize a cross bar with an increased scaling ability between the wave slots and the execution units, which may cause a number of problems, e.g., clock speed degradation and/or wire congestion in the design. For example, in GPU <NUM>, data cross bar <NUM> may need an increased scaling ability to increase the number of wave slots <NUM>-<NUM>, which may result in a larger data cross bar <NUM> and wire congestion or clock speed degradation. For example, GPU <NUM> includes ten wave slots <NUM>-<NUM> and five execution units <NUM>-<NUM>, so the data cross bar <NUM> helps to convert and manage this ten-to-five wave slot to execution unit ratio. Accordingly, the data cross bar <NUM> can convert the ten wave slot instructions to the five execution units. So the data cross bar <NUM> can scale two wave instructions for every one execution unit. In order to double the amount of wave slots <NUM>-<NUM>, e.g., from <NUM> to <NUM> wave slots, then data cross bar <NUM> may need to be adjusted to access and manage the execution units <NUM>-<NUM>. Accordingly, if the number of wave slots is increased to <NUM>, then the data cross bar <NUM> may need to be adjusted to convert <NUM> wave slot instructions to the five execution units. However, as mentioned above, adjusting the cross bar can incur a number of utilization issues, e.g., wire congestions and clock speed degradation. Indeed, the space around the execution units may be limited, so there may not be enough room for an increased amount of wire. For example, if the number of wave slots is doubled, the amount of wire may also double, but the size of the space remains the same, so the GPU may experience a wire congestion issue. Accordingly, there is a need for increasing the wave slot capacity without experiencing the aforementioned issues.

As mentioned above, in some aspects, some wave slots may not be actively issuing wave instructions. For example, out often wave slots, there may be four to six wave slots that are waiting on external wave data to be processed, e.g., after issuing a data fetch instruction. These wave slots may not be executing instructions nor updating a context register, i.e., these wave slots are in standby mode. Because these standby wave slots may not need updates to a corresponding context register, it may be possible to use another form of memory to store the context register information of wave slots in standby mode. One form of memory that may be cheaper than the flopped-based storage at wave slots is RAM memory. For example, flopped-based memory storage may be three times more expensive than RAM-based memory. Accordingly, a context queue, as described herein, can be stored in RAM memory which is cheaper than flopped-based memory.

As mentioned above, increasing the number of wave slots may mitigate memory or pipeline latency issues. For instance, as latency issues increase, the amount of data or instructions to account for the latency may likewise increase. In order to increase the wave processing capacity, or the ability to cover pipeline latency, the number of wave slots can also be increased. In some aspects, once a wave slot issues an instruction, it can wait for the instruction to be processed, i.e., remain in standby mode. The aforementioned latency issues may cause the wave slot to wait in standby mode longer than usual. As wave slots are valuable resources, it can be a waste of resources if wave slots are in standby mode waiting on return data. In some aspects, wave slots may even be idle or in standby mode a majority of the time. Accordingly, this may not be an efficient way to implement the wave slot resources.

In order to address the aforementioned wave slot issues, aspects of the present disclosure can take information, e.g., context information, from wave slots that would otherwise be in standby mode and store it in a data or context queue and/or RAM-based storage. By doing so, the idle wave slots can be utilized for executing another wave instruction while waiting on the previous wave data to be processed. Once the wave data is processed and returns to the wave slots, the context information corresponding to the wave data can be sent to one of the wave slots. Additionally, in some aspects, instead of using flat wave slots, e.g., which may store context information unnecessarily while in standby mode, aspects of the present disclosure can use a type of wave slot, which can be referred to as execution slots, that can send the context information to a data or context queue while waiting on wave information to be processed. In some aspects, an execution slot is a type of wave slot that can execute other wave instructions while a previously executed wave instruction is being processed. Accordingly, in some aspects, an execution slot can allow a GPU to execute more wave instructions compared to a typical wave slot. By utilizing execution slots, aspects of the present disclosure may utilize a reduced amount of execution slots in order to execute a similar amount of wave instructions compared to traditional wave slots. Further, aspects of the present disclosure can build a hierarchical wave slot structure, e.g., with execution slots and a data or context queue to store context information for wave data being processed. In some aspects, these wave slots can be referred to as execution slots, execution wave slots, execution-based wave slots, or any similar phrase. For example, aspects of the present disclosure can perform at the same efficiency level by using a reduced amount of execution slots compared to wave slots. By utilizing execution slots, aspects of the present disclosure can utilize a reduced amount of wave slots, e.g., six execution slots compared to ten wave slots, and maintain the same efficiency level. Additionally, aspects of the present disclosure can include a RAM-based data or context queue to store context information for wave slots that previously executed wave instructions. Aspects of the present disclosure can introduce a hierarchy wave queue, such that wave slots that would otherwise be idle can be used to execute wave data that returns from processing. In turn, this can be an efficient way to increase the wave slot capacity to account for latency issues.

In some aspects, when processing units, e.g., GPUs, herein execute a wave instruction that has finished processing, aspects of the present disclosure can send the context information corresponding to the wave instruction that was stored in the context queue to one of the wave or execution slots. By doing so, the wave or execution slot can execute the wave instruction with the corresponding context information. After performing this wave instruction, e.g., generating coordinates or vertices for a triangle or primitive, aspects of the present disclosure can send the context information for the next wave instruction to one of the wave slots from the context queue. Additionally, by utilizing a reduced number of wave or execution slots, e.g., six execution slots compared to ten wave slots, aspects of the present disclosure can still have enough wave slots to cover instructions for up to six execution units at the same time, which is enough to cover the five execution units illustrated in <FIG>. In some aspects, there may be at least the same amount of wave or execution slots as execution units. Also, based on the hierarchy wave structure where idle wave slots are utilized to execute incoming wave instructions, the wave or execution slots may not remain inactive for many cycles after they send a corresponding wave instruction to cycle through the system. Accordingly, aspects of the present disclosure can utilize a reduced number of wave of execution slots, and correspondingly reduce the amount of wasted wave slot resources, e.g., as fewer wave slots will be waiting on wave instructions to be processed. As such, aspects of the present disclosure can partition or convert a group of individually functioning wave slots into a more efficient group of hierarchy based wave slots.

In some instances, aspects of the present disclosure can maintain the existing implementation and functionality of the previous flat-based wave slots, but when a wave slot would otherwise be in standby mode waiting for a corresponding wave instruction to be processed, the wave slot can become available to execute other wave instructions. As such, the wave slot can access the context queue for context information corresponding to any incoming wave instruction. By doing so, aspects of the present disclosure can optimize the performance of the wave slots. As mentioned previously, the context queue can utilize RAM-based memory to store the context information of wave slots. In some aspects, the context queue may assign some types of RAM-based memory to certain ports or slots in the context queue.

In some aspects, when a corresponding wave instruction is being processed, a wave or execution slot can copy the corresponding context register information to the RAM-based memory in the context queue. The wave slot can also temporarily surrender its ability to execute the corresponding wave instruction, and gain the ability to execute another wave instruction. By doing so, the wave slot will not be occupied while waiting for the corresponding wave instruction to be processed, e.g., at an execution unit. In this sense, the wave slot is no longer in a standby state, as it is capable of executing another wave instruction. Accordingly, aspects of the present disclosure can copy or convert the context register information associated with a particular wave instruction to the data or context queue and free up the wave slot for other wave execution during the time the wave slot would otherwise be waiting for the wave instruction to be processed. Further, when the wave instruction returns from processing, aspects of the present disclosure can copy the context data from the context queue to one of the wave or execution slots to continue executing the wave instruction.

As indicated above, aspects of the present disclosure can utilize a hierarchy-based data access procedure to copy and/or save context information into the context queue, e.g., with RAM-based memory storage. GPUs herein can also optimize the execution capability of wave slots that would otherwise be in an idle or standby state. Moreover, aspects of the present disclosure can utilize a reduced number of wave or execution slots while still optimizing or maintaining the same execution capability of these wave or execution slots. In some aspects, aspects of the present disclosure can utilize a reduced number of wave slots, e.g., six execution slots compared to ten wave slots, and/or utilize more efficient wave or execution slots while maintaining the same level of efficiency. Accordingly, the wave slots can execute more wave data and no longer be in an idle state waiting on wave data to be processed. For instance, if a wave slot is not being utilized to execute data, then aspects of the present disclosure can store the context register information of the wave slot in a context queue. In some instances, the context information for each wave instruction that is waiting to be executed may be stored in the context queue.

As indicated herein, aspects of the present disclosure can convert wave slots into a wave slot hierarchy. Further, aspects of the present disclosure can partition the wave slots into a hierarchy of different levels. For example, a first level of the hierarchy can be the wave slots, each of which can be accessed in parallel or at the same time as other wave slots. The second level of the hierarchy can be the context queue, which can track the wave instructions that are being processed, e.g., by execution units. As the data or wave instructions are processed and cycle back sequentially, the context information stored in the context queue can be copied and sent to the wave or execution slots.

As indicated above, the wave hierarchy can optimize the execution capability of the wave slots, such that idle or standby time at each wave slot is minimized. Aspects of the present disclosure could allow for the reduction of the ratio of wave slots to execution units, e.g., from a ratio of ten-to-five to a ratio of six-to-five. Aspects of the present disclosure can also introduce a data cross bar for the transfer or conversion of context information from the wave slots to the context queue. In some aspects, the size of this data cross bar may not be very large compared to other data cross bars, as the conversion of context information from the wave slots to the context queue does not have a high throughput. Additionally, this wave hierarchy can reduce the size of other data cross bars, as the number of wave slots can be reduced.

As indicated herein, the aforementioned wave hierarchy can send context information from the wave slots to a context queue, store context information in the context queue, and then send the context information back to the wave slots when it is ready to be executed. Accordingly, in some aspects, this can be a first-in-first-out (FIFO) hierarchy of wave data. By forming this wave hierarchy, aspects of the present disclosure can address the aforementioned congestion problems. For instance, aspects of the present disclosure can increase the capacity of each wave slot, so that each wave slot can execute more wave instructions and better account for any latency issues. Further, aspects of the present disclosure can allow for the reduction of the wave instruction ratio between the wave slots and the execution units, while still maintaining the same amount of functionality or execution ability.

<FIG> and <FIG> illustrate an example GPU <NUM> in accordance with one or more techniques of this disclosure. More specifically, <FIG> and <FIG> show components or units within SP <NUM> in GPU <NUM>. As shown in <FIG> and <FIG>, GPU <NUM> includes a number of execution units, e.g., flow control branch <NUM>, EFU <NUM>, ALU <NUM>, TEX <NUM>, and LDST <NUM>. GPU <NUM> can also include a number of additional execution units, as execution units <NUM>-<NUM> are merely an example and any combination or order of execution units can be used by processing units, e.g., GPUs, herein. GPU <NUM> can also include data cross bar <NUM>, which can also be referred to as multiple thread manager <NUM>, as well as L0 cache <NUM>. Further, GPU <NUM> includes a number of wave slots, e.g., wave slots <NUM>-<NUM>. GPU <NUM> can include any number of different wave slots, as wave slots <NUM>-<NUM> are merely an example. Additionally, wave slots <NUM>-<NUM> can be part of a wave scheduler.

As illustrated in <FIG>, GPU <NUM> can also include data cross bar <NUM> and context queue <NUM>, which includes context queue slots <NUM>-<NUM>. <FIG> can be an extension of <FIG>, as shown using extension point A. For example, GPU <NUM> in <FIG> is the same as GPU <NUM> in <FIG>, where <FIG> is a more detailed close-up view of the dashed line section of GPU <NUM>. <FIG> was added for ease of illustration to show the detail surrounding wave slots <NUM>-<NUM>, e.g., data cross bar <NUM> and context queue <NUM> including context queue slots <NUM>-<NUM>.

As shown in <FIG> and <FIG>, each component in GPU <NUM> can communicate with a number of other components. For example, each of the execution units <NUM>-<NUM> can send or receive data or instructions, e.g., requests or grants, to/from the data cross bar <NUM>. Further, each of the wave slots <NUM>-<NUM> can send or receive data or instructions, e.g., requests or grants, to/from the data cross bar <NUM>. Also, data cross bar <NUM> can store data in, or receive data from, the L0 cache <NUM>. Each of the execution units <NUM>-<NUM>, e.g., flow control branch <NUM>, EFU <NUM>, ALU <NUM>, TEX <NUM>, and LDST <NUM>, can also send or receive data or instructions to/from the wave slots <NUM>-<NUM>. In some aspects, each of the wave slots <NUM>-<NUM> can issue instructions simultaneously to each of the execution units <NUM>-<NUM>. Additionally, each of the wave slots <NUM>-<NUM> can send or receive data or instructions, e.g., requests or grants, to/from the data cross bar <NUM>. Moreover, data cross bar <NUM> can send or receive data or instructions, e.g., requests or grants, to/from the context queue <NUM>. Each of the wave slots <NUM>-<NUM> can also send or receive data or instructions to/from the context queue <NUM>.

<FIG> and <FIG> illustrate that GPU <NUM> includes six wave slots, e.g., wave slots <NUM>-<NUM>. In some aspects, the wave slots <NUM>-<NUM> can be referred to as execution slots <NUM>-<NUM>. As mentioned above, each of the wave slots <NUM>-<NUM> can execute wave instructions on a hierarchical basis with the group of wave slots. For instance, when an individual wave instruction is processing through the system, the corresponding wave slot may not need to wait for the particular wave instruction to return from being processed, e.g., at one of the execution units <NUM>-<NUM>. Rather than being in idle or standby mode waiting for a wave instruction to return from being processed, each of the wave slots <NUM>-<NUM> may execute another wave instruction.

Additionally, when an individual wave instruction is processing through the system, e.g., at one of execution units <NUM>-<NUM>, the context information for the corresponding wave slot, e.g., one of wave slots <NUM>-<NUM>, can be sent to the context queue <NUM>, e.g., via the data cross bar <NUM>. This context information can be stored in the context queue <NUM>, e.g., in one of the context queue slots <NUM>-<NUM>. When the corresponding wave instruction is finished processing, e.g., at one of the execution units <NUM>-<NUM>, the context information can be sent from the context queue <NUM>, e.g., via the data cross bar <NUM>, to one of the wave slots <NUM>-<NUM> to be executed. The data cross bar <NUM> can convert the context information from one of the wave slots <NUM>-<NUM> being sent to the context queue <NUM> into context information compatible with the context queue <NUM>. Likewise, the data cross bar <NUM> can convert the context information compatible with the context queue <NUM> being sent to the wave slots <NUM>-<NUM> into context information that is compatible with the wave slots <NUM>-<NUM>.

As mentioned herein, aspects of the present disclosure can replace flat-based wave slots with a wave hierarchy structure, e.g., execution slots <NUM>-<NUM>, data cross bar <NUM>, and context queue <NUM>. In order to do so, aspects of the present disclosure can copy and/or send the context register information for certain execution slots <NUM>-<NUM> to the context queue <NUM>. For example, execution slot <NUM> may have a certain context value when a corresponding wave instruction is sent to an execution unit to be processed. GPU <NUM> can then copy and send that context value to the context queue <NUM>, and then copy and send the context value back to one of the execution slots <NUM>-<NUM> when the wave instruction is finished processing. There is no need for the context value to be sent back to execution slot <NUM>, as any one of the execution slots <NUM>-<NUM> is capable of executing the wave instruction with the context information. As any of the execution slots <NUM>-<NUM> is capable of execution a wave instruction with context information, a reduced amount of wave slots can be utilized while maintaining the same level of efficiency, e.g., utilizing six execution slots compared to ten wave slots.

Aspects of the present disclosure can execute a number of wave instructions, e.g., an ALU instruction. For example, an ALU instruction can go through multiple processing steps: <NUM>) interpretation, <NUM>) texture sampling pre-processing, <NUM>) waiting for the texture sampling to return from processing, <NUM>) post-processing. Some example waiting times using flat-based wave slots are: texture sampling pre-processing = <NUM> cycles, waiting for the texture sampling to return from processing = <NUM> cycles, post-processing = <NUM> cycles. Accordingly, using flat-based wave slots, a wave slot can be waiting for <NUM> cycles out of <NUM> cycles and executing for <NUM> cycles. By utilizing the execution slots mentioned herein with a hierarchical wave structure, the context information can be stored in the context queue. In turn, this can open up the execution slot for executing another wave instruction and improve utilization of the execution slots in the <NUM> cycles that would otherwise be wasted. Accordingly, the wave slots herein can process an increased amount of wave instructions, e.g., ten times more wave instructions, as the wave slots are no longer wasting time waiting. Indeed, because the wave slots in the present disclosure are more efficient, aspects of the present disclosure can operate as efficiently with fewer wave slots, e.g., GPUs that use the techniques herein can operate with <NUM> wave slots as efficiently as GPUs with <NUM> wave slots.

Some aspects of the present disclosure can include a number of wave slots that are greater than or equal to the number of execution units, in order to fill or utilize each of the execution units. In some aspects, processing units, e.g., GPUs, herein can have fewer wave slots than execution units, as long as the execution units that are the busiest, e.g., ALU <NUM> or TEX <NUM>, are generally filled or utilized. However, some processing units, e.g., GPUs, herein can have at least as many wave slots as execution units, so the utilization of the execution units can be optimized.

As shown in <FIG> and <FIG>, GPU <NUM> can determine one or more context states of at least one context register in each of wave slots <NUM>-<NUM>. GPU <NUM> can send wave data corresponding to one of the wave slots <NUM>-<NUM>, e.g., wave data or instruction <NUM> corresponding to wave slot <NUM>, to one of execution units <NUM>-<NUM>, e.g., ALU <NUM>. GPU <NUM> can also send information corresponding to the one or more context states in one of the wave slots, e.g., context state or information <NUM> corresponding to wave slot <NUM>, to the context queue <NUM>. In some aspects, the information corresponding to the one or more context states, e.g., context state or information <NUM>, can be sent to the context queue <NUM> when the wave data corresponding to one of the wave slots, e.g., wave data or instruction <NUM> corresponding to wave slot <NUM>, is sent to one of the execution units, e.g., ALU <NUM>. Also, wave data or instruction <NUM> can be converted by data cross bar <NUM>, so it can be referred to as wave data or instruction <NUM>.

GPU <NUM> can also copy the information corresponding to the one or more context states in one of the wave slots when the information corresponding to the one or more context states, e.g., context state or information <NUM>, is sent to the context queue <NUM>. GPU <NUM> can also remove the one or more context states from one of the wave slots when the information corresponding to the one or more context states, e.g., context state or information <NUM>, is sent to the context queue <NUM>. Additionally, GPU <NUM> can convert the information corresponding to the one or more context states in one of the wave slots, e.g., context state or information <NUM>, to context information compatible with the context queue <NUM>, e.g., context state or information <NUM>. GPU <NUM> can also store the context information compatible with the context queue <NUM>, e.g., context state or information <NUM>, in the context queue <NUM>.

GPU <NUM> can also receive wave data corresponding to one of the wave slots, e.g., wave data <NUM>, from one of the execution units, e.g., ALU <NUM>. In some aspects, the context information compatible with the context queue <NUM>, e.g., context state or information <NUM>, can be sent to one of the wave slots when the wave data corresponding to one of the wave slots, e.g., wave data <NUM>, is received from the one of the execution units, e.g., ALU <NUM>. GPU <NUM> can also send the context information compatible with the context queue <NUM>, e.g., context state or information <NUM>, to one of the wave slots, e.g., wave slot <NUM>. GPU <NUM> can also convert the context information compatible with the context queue <NUM>, e.g., context state or information <NUM>, to information corresponding to the one or more context states, e.g., context state or information <NUM>, when sending the information to wave slot <NUM>.

In some instances, wave slots <NUM>-<NUM> can be execution slots <NUM>-<NUM>. GPU <NUM> can also replace wave slots <NUM>-<NUM> with execution slots and/or convert the wave slots <NUM>-<NUM> to execution slots. In some aspects, converting a wave slot to an execution slot can result in a particular wave slot being able to execute multiple wave instructions, e.g., after a previous wave instruction is executed. Moreover, the number of execution slots <NUM>-<NUM> can be less than or equal to the number of wave slots <NUM>-<NUM>. In further aspects, the information corresponding to the one or more context states in one of the wave slots, e.g., context state or information <NUM>, can be converted using data cross bar <NUM>. GPU <NUM> can also store the information corresponding to the one or more context states of at least one context register in one of multiple wave slots, e.g., wave slots <NUM>-<NUM>. Also, the multiple wave slots can be in a graphics processing pipeline of a GPU. In some aspects, the wave slots and the execution units can be in a SP, e.g., SP <NUM>. Further, in some aspects, the number of wave slots <NUM>-<NUM> can be greater than or equal to the number of execution units <NUM>-<NUM>.

As illustrated in <FIG> and <FIG>, aspects of the present disclosure can include context queue <NUM> to store the context information of the wave slots <NUM>-<NUM>. For example, context queue <NUM> can include <NUM> context queue slots <NUM>-<NUM>. However the number of context queue slots can be scalable to include other amounts, e.g., <NUM> context queue slots. In some aspects, if wave slots <NUM>-<NUM> have pending wave data being processed, they can issue a request to acquire an execution slot with a wave identification (ID), which each context register can include. Further, upon granting the execution slot, a scheduler can copy active or frequently changed context registers from the context queue <NUM> to the granted execution slot in a few cycles, fetch the wave instruction, and then start executing the instruction. Additionally, if a wave or execution slot is in a waiting state, it can copy the active context register information to the context queue <NUM> in a few cycles and surrender its execution slot. In some aspects, if wave input data and/or output results are considered to be in a waiting state, they may not occupy wave or execution slots. Moreover, the context queue <NUM> can include a wide bandwidth for reduced latency issues. For example, latency may occur during wave instruction switching between the execution slots and the context queue.

As mentioned herein, aspects of the present disclosure can optimize the execution of wave instruction and/or context storage. For instance, aspects of the present disclosure can reduce the amount of space in a GPU, e.g., in SP <NUM>, and/or reduce the cost of memory performance. As mentioned above, aspects of the present disclosure can include a data cross bar to help convert data from the execution slots to the context queue. Accordingly, the data cross bar can be considered a data conversion bar that converts the context data from the wave slots to the context queue. As mentioned above, aspects of the present disclosure can store and copy context information into a context queue when a wave slot is waiting on a wave instruction to return from processing. This can provide an efficient way to increase wave slot capacity to better account for latency and result in improved performance. Additionally, this can reduce the data cross bar size between the wave slots and execution units, which can mitigate congestion and/or clock speed degradation at the GPU.

<FIG> illustrates an example flowchart <NUM> of an example method in accordance with one or more techniques of this disclosure. The method may be performed by a GPU or apparatus for graphics processing. At <NUM>, the apparatus can determine one or more context states of at least one context register in each of multiple wave slots, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. At <NUM>, the apparatus can send wave data corresponding to the one of the multiple wave slots to one of multiple execution units, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. At <NUM>, the apparatus can send information corresponding to the one or more context states of at least one context register in one of the multiple wave slots to a context queue, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. In some aspects, the information corresponding to the one or more context states of at least one context register can be sent to the context queue when the wave data corresponding to the one of the multiple wave slots is sent to one of the execution units, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>.

At <NUM>, the apparatus can copy the information corresponding to the one or more context states of at least one context register in one of the wave slots when the information corresponding to the one or more context states is sent to the context queue, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. At <NUM>, the apparatus can remove the one or more context states of at least one context register from the one of the wave slots when the information corresponding to the one or more context states is sent to the context queue, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. At <NUM>, the apparatus can convert the information corresponding to the one or more context states of at least one context register in one of the wave slots to context information compatible with the context queue, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. At <NUM>, the apparatus can store the context information compatible with the context queue in the context queue, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>.

At <NUM>, the apparatus can receive wave data corresponding to the one of the wave slots from one of the execution units, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. In some aspects, the context information compatible with the context queue can be sent to one of the wave slots when the wave data corresponding to one of the wave slots is received from the one of the execution units, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. At <NUM>, the apparatus can send the context information compatible with the context queue to one of the wave slots, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. At <NUM>, the apparatus can convert the context information compatible with the context queue to the information corresponding to the one or more context states of at least one context register, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. At <NUM>, the apparatus can store the information corresponding to the one or more context states of at least one context register in one of the wave slots, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>.

In some aspects, the apparatus can replace the multiple wave slots with multiple execution slots and/or convert the multiple wave slots to multiple execution slots, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. As mentioned above, converting a wave slot to an execution slot can result in a particular wave slot being able to execute multiple wave instructions while a previously executed wave instruction is being processed. Moreover, the number of execution slots can be less than or equal to the number of wave slots, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. In further aspects, the information corresponding to the one or more context states of at least one context register in one of the wave slots can be converted using a data cross bar, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. Also, the multiple wave slots can be in a graphics processing pipeline of a GPU, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. In some aspects, the wave slots and the execution units can be in a streaming processor (SP), as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>. Further, in some aspects, the number of wave slots can be greater than or equal to the number of execution units, as described in connection with the examples in <FIG>, <FIG>, <FIG>, and <FIG>.

In one configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU or some other processor that can perform graphics processing. In one aspect, the apparatus may be the processing unit <NUM> within the device <NUM>, or may be some other hardware within device <NUM> or another device. The apparatus may include means for determining one or more context states of at least one context register in each of multiple wave slots. The apparatus may also include means for sending, to a context queue, information corresponding to the one or more context states of at least one context register in one of the wave slots. Also, the apparatus may include means for converting the information corresponding to the one or more context states of at least one context register to context information compatible with the context queue. The apparatus may also include means for storing the context information compatible with the context queue in the context queue. Additionally, the apparatus can include means for removing the one or more context states of at least one context register from the one of the wave slots when the information corresponding to the one or more context states is sent to the context queue. The apparatus may also include means for sending the context information compatible with the context queue to one of the wave slots. The apparatus may also include means for converting the context information compatible with the context queue to the information corresponding to the one or more context states of at least one context register. The apparatus can also include means for storing the information corresponding to the one or more context states of at least one context register in one of the wave slots. Moreover, the apparatus can include means for copying the information corresponding to the one or more context states of at least one context register in one of the wave slots when the information corresponding to the one or more context states is sent to the context queue. Also, the apparatus can include means for sending wave data corresponding to the one of the wave slots to one of multiple execution units. The apparatus may also include means for receiving wave data corresponding to the one of the wave slots from one of the execution units. Further, the apparatus can include means for converting the wave slots to execution slots.

The subject matter described herein can be implemented to realize one or more benefits or advantages. For instance, the described graphics processing techniques can be used by GPUs or other graphics processors to enable increased wave data processing or execution. This can also be accomplished at a low cost compared to other graphics processing techniques. Moreover, the graphics processing techniques herein can improve or speed up the data processing or execution. Further, the graphics processing techniques herein can improve a GPU's resource or data utilization and/or resource efficiency. Additionally, aspects of the present disclosure can mitigate congestion and/or clock speed degradation in a GPU.

In accordance with this disclosure, the term "or" may be interrupted as "and/or" where context does not dictate otherwise. Additionally, while phrases such as "one or more" or "at least one" or the like may have been used for some features disclosed herein but not others, the features for which such language was not used may be interpreted to have such a meaning implied where context does not dictate otherwise.

The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry.

The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.

Claim 1:
A method for graphics processing, comprising:
determining (<NUM>) one or more context states of at least one context register in each of a plurality of wave slots,
wherein each of the plurality of wave slots, when not waiting for data or instructions to be processed, is capable of executing data or instructions and sending/receiving data or instructions to/from one of a plurality of execution units;
sending (<NUM>) information corresponding to the one or more context states of at least one context register in at least one of the plurality of wave slots to a context queue when data or instructions corresponding to one of the plurality of wave slots are sent to one of a plurality of execution units for processing;
converting (<NUM>) the information corresponding to the one or more context states of at least one context register in the at least one of the plurality of wave slots to context information compatible with the context queue;
storing (<NUM>) the context information compatible with the context queue in the context queue; and
sending (<NUM>) the context information compatible with the context queue to one of the plurality of wave slots when processed data or instructions corresponding to the one of the plurality of wave slots are pending to be processed from the one of the plurality of execution units.