Patent Description:
Nonvolatile memory devices, which are semiconductor memory devices, maintain information stored thereon even when the power is turned off, and thus may allow the stored information to be accessed and/or used again when power is supplied thereto. Nonvolatile memory devices may be used in cell phones, digital cameras, personal digital assistants (PDAs), mobile computers, fixed computers, and other devices.

Recently, researches have been carried out to use nonvolatile memory devices in chips included in next-generation neuromorphic computing platforms or neural networks.

In particular, there is a need for nonvolatile memory devices having photoconductivity (PC).

Document <CIT> discloses a nonvolatile memory device including graphene and a phase change material provided to access data by measuring a photo current generated in a graphene layer to read the data.

Document <CIT> discloses an electronic device including a substrate, a gate electrode a dielectric layer, a source electrode, a drain electrode and a semiconducting layer formed from an organic semiconductor compound and a photo-responsive polymer.

Document <CIT> discloses a crossbar array including a number of memory elements.

Provided are a crossbar array of nonvolatile memory devices and operating methods of the same. Provided are computer-readable recording media having recorded thereon a program for executing the methods on a computer. The technical problems to be solved are not limited to the above technical problems, and thus other technical problems may be solved.

According to a first aspect of some example embodiments, there is provided a crossbar array according to claim <NUM>.

According to a second aspect of another example embodiment, there is provided a method according to claim <NUM>.

According to a third aspect of another example embodiment, a non-transitory computer-readable recording medium has recorded thereon a program, which when executed by a computer, causes the computer to perform the method of the second aspect on a computer.

The terms "in some example embodiments" and "in an example embodiment" used herein do not necessarily indicate the same embodiment.

Some example embodiments of the present disclosure may be represented by functional blocks and various processing operations. Some or all of such functional blocks may be implemented as various numbers of hardware and/or software components for performing specific functions. For example, the functional blocks of the present disclosure may be implemented using one or more microprocessors, or may be implemented using circuits for predetermined functions. Furthermore, for example, the functional blocks of the present disclosure may be implemented with various programming or scripting languages. The functional blocks may be implemented as algorithms to be executed by one or more processors. Furthermore, the present disclosure may employ typical technologies for electronic environment setting, signal processing, and/or data processing. The terms such as "mechanism," "element," "means", "configuration," and the like may be widely used herein, and are not limited to mechanical and physical configurations.

Although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections, should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section, from another region, layer, or section. Thus, a first element, component, region, layer, or section, discussed below may be termed a second element, component, region, layer, or section, without departing from the scope of this disclosure.

When an element is referred to as being "on," another element, the element may be directly on the other element, and/or one or more other intervening elements may be present. In contrast, when an element is referred to as being "directly on," another element there are no intervening elements present. In addition, when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more other intervening elements may be present.

Furthermore, the connection lines or connection members between elements illustrated in the drawings are merely examples of functional connections and/or physical or circuit connections. In actual applications, they may be replaced or embodied as various additional functional connections, physical connections, or circuit connections.

Generally speaking, a computer-accessible medium may include any tangible and/or non-transitory storage media and/or memory media. The term "non-transitory," as used herein, is a limitation of the medium itself (e.g., as tangible, and not a signal) as opposed to a limitation on data storage persistency (e.g., RAM vs. ROM).

<FIG>and <FIG> are diagrams for describing a method of operating a crossbar array including a plurality of nonvolatile memory devices according to some example embodiments.

Referring to <FIG>, the crossbar array may include a plurality of presynaptic neurons <NUM>, a plurality of postsynaptic neurons <NUM>, and synapses <NUM> for providing a connection between the plurality of presynaptic neurons <NUM> and the plurality of postsynaptic neurons <NUM>. The synapse <NUM> may represent, for example, a nonvolatile memory device.

In some example embodiments, the crossbar array may include four presynaptic neurons <NUM>, four postsynaptic neurons <NUM>, and <NUM> synapses <NUM>, but the numbers of the foregoing elements may be variously changed. When the number of the presynaptic neurons <NUM> is N (where N is a natural number greater than or equal to <NUM>) and the number of the postsynaptic neurons <NUM> is M (where M is a natural number greater than or equal to <NUM>, and may be equal to or different from N), N*M number of synapses <NUM> may be arranged in a matrix form.

A line <NUM> may be connected to each of the plurality of presynaptic neurons <NUM> and may extend in a first direction (for example, a horizontal direction) and a line <NUM> may be connected to each of the plurality of postsynaptic neurons <NUM> and may extend in a second direction (for example, a vertical direction) intersecting with the first direction. Hereinafter, for convenience, the line <NUM> extending in the first direction is referred to as a row line, and the line <NUM> extending in the second direction is referred to as a column line. The plurality of synapses <NUM> may be arranged at each intersection point of the row line <NUM> and the column line <NUM> to connect the corresponding row line <NUM> and corresponding column line <NUM> to each other.

The presynaptic neuron <NUM> may be configured to generate and to send a signal, for example, a signal corresponding to specific data, to the row line <NUM>, and the postsynaptic neuron <NUM> may be configured to receive, via the column line <NUM>, a synaptic signal that has passed through the synapse <NUM>, and may process the synaptic signal. The presynaptic neuron <NUM> may correspond to an axon, and the postsynaptic neuron <NUM> may correspond to a neuron. However, whether a neuron is a presynaptic neuron <NUM> or a postsynaptic neuron <NUM> may be determined according to a relative relationship with another neuron. For example, when the presynaptic neuron <NUM> receives a synaptic signal from another neuron, the presynaptic neuron <NUM> may function as a postsynaptic neuron <NUM>. Likewise, when the postsynaptic neuron <NUM> sends a signal to another neuron, the postsynaptic neuron <NUM> may function as a presynaptic neuron <NUM>. The presynaptic neuron <NUM> and the postsynaptic neuron <NUM> may be implemented as various circuits such as a complementary metal-oxide-semiconductor (CMOS) or the like.

A connection between the presynaptic neuron <NUM> and the postsynaptic neuron <NUM> may be established through the synapse <NUM>. The synapse <NUM> may be a device configured to vary a weight or electrical conductance with an electrical pulse applied to the two ends of the synapse <NUM>, for example, a voltage and/or current.

The synapse <NUM> may include, for example, a variable resistance device. The variable resistance device, which may be configured to switch between different resistance states according to a voltage or current applied to the two ends of the variable resistance device, may have a single-layer structure or multi-layer structure including various materials that may have a plurality of resistance states, for example, a metal oxide such as a transition metal oxide; perovskite-based material or the like; a phase-change material such as a chalcogenide-based material or the like; and/or a ferroelectric material, a ferromagnetic material, or the like. An operation in which the variable resistance element and/or the synapse <NUM> changes from a higher resistance state (e.g., a high-resistance state) to a lower resistance state (e.g., a low-resistance state) may be referred to as a set operation, and an operation in which the variable resistance element and/or the synapse <NUM> changes from a lower resistance state to a higher resistance state may be referred to as a reset operation.

However, the synapse <NUM> may be implemented to have various characteristics that are different from those of variable resistance devices of memories. For example, unlike the variable resistance devices used in memory devices such as resistance random access memory (RRAM), parameter RAM (PRAM), ferroelectric RAM (FRAM), magnetoresistive RAM (MRAM), and the like, the synapse <NUM> may exhibit analog behavior in which there is no abrupt change in resistance and the conductance may gradually change according to the number of input electrical pulses during the set operation and reset operation.

Operation of the crossbar array is described below with reference to <FIG>. For convenience, the row lines <NUM> may be sequentially referred to as a first row line 12A, a second row line 12B, a third row line 12C, and a fourth row line 12D from up to down, and the column lines <NUM> may be sequentially referred to as a first column line 22A, a second column line 22B, a third column line 22C, and a fourth column line 22D from left to right.

Referring to <FIG>, in an initial state, all of the synapses <NUM> may be in a state in which conductance is relatively low, e.g., a high-resistance state. When at least a portion of the plurality of synapses <NUM> are in a low-resistance state, an initialization operation may switch the portion of the plurality of synapses <NUM> to the high-resistance state. Each of the plurality of synapses <NUM> may have a threshold for changing its resistance and/or conductance. For example, a synapse <NUM> may have a desired (or, alternatively predetermined) threshold for changing its resistance and/or conductance. , The synapse <NUM> may be configured to, for example, not change its conductance when a voltage and/or current less than the threshold is applied to two ends of the synapse <NUM>, and to change its conductance when a voltage and/or current greater than the threshold is applied to the two ends of the synapse <NUM>.

In this state, an input signal corresponding to specific data may be input to the row lines <NUM> to perform an operation of outputting the specific data as a result of a specific column line <NUM>. Here, the input signal may be indicated by applying electrical pulses to the row lines <NUM>. For example, when the input signal corresponding to data '<NUM>' is input to the row lines <NUM>, an electrical pulse may not be applied to the row lines <NUM> corresponding to the digit '<NUM>' (e.g., the first and second row lines 12Aand 12B), and may be applied to the row lines <NUM> corresponding to the digit '<NUM>' (e.g., the third and fourth row lines 12C and 12D). The column line <NUM> may be driven with an appropriate voltage and/or current to perform the output.

For example, when a column line <NUM> for outputting the specific data is determined, this column line <NUM> may be driven so that the synapse <NUM> located at an intersection point with the row line <NUM> and the column line <NUM> and corresponding to the digit '<NUM>' may receive a voltage equal to or higher than a voltage required for a set operation (hereinafter referred to as a set voltage Vset), and the remaining column lines <NUM> may be driven so that the remaining synapses <NUM> may receive a voltage lower than the set voltage Vset. For example, when the set voltage is Vset, and the column line <NUM> for outputting the data '<NUM>' is determined as the third column line 22C, a magnitude of an electrical pulse applied to the third and fourth row lines 12C and 12D may be at least Vset and a voltage applied to the third column line 22C may be <NUM> V so that first and second synapses 30A and 30B located at intersection points between the third column line 22C and the third and fourth row lines 12C and 12D may receive a voltage of at least Vset. Accordingly, the first and second synapses 30A and 30B may be in a lower resistance state. The conductance of the first and second synapses 30A and 30B which are in a lower resistance state may gradually increase as the number of electrical pulses increases. A magnitude and width of an applied electrical pulse may be substantially constant. A voltage applied to the remaining column lines (e.g., the first, second, and fourth lines 22A, 22B, and 22D) may have a value between <NUM> V and Vset, for example, <NUM>/2Vset, so that the synapses <NUM> except for the first and second synapses 30A and 30B may receive a relative voltage lower than Vset. Accordingly, the resistance state of the synapses <NUM> except for the first and second synapses 30A and 30B may not change. A flow of current and/or electrons for this case is indicated by a dotted arrow in <FIG>.

In another example, the column line <NUM> for outputting specific data may not yet be determined. In this case, a current flowing through each column line <NUM> may be measured while applying an electrical pulse corresponding to specific data to the row line <NUM>, and the column line <NUM> of which the current reaches a threshold current earliest, for example, the third column line 22C, may be determined to output the specific data.

In this manner, different pieces of data may be output to different column lines <NUM> respectively.

<FIG> is a diagram illustrating an architecture of a neural network according to some example embodiments.

Referring to <FIG>, a neural network <NUM> may have an architecture of a deep neural network (DNN) and/or n-layer neural network. The DNN and/or n-layer neural network may correspond to a convolution neural network (CNN), recurrent neural network (RNN), deep belief network, restricted Boltzmann machine, or the like. For example, the neural network <NUM> may be implemented as a CNN, an artificial neural network (ANN) system, a deep learning system, deconvolutional neural networks (DCNN), stacked neural networks (SNN), state-space dynamic neural networks (SSDNN), deep belief networks (DBN), generative adversarial networks (GANs), and/or restricted Boltzmann machines (RBM), but is not limited thereto. Alternatively and/or additionally, such machine learning systems may include other forms of machine learning models, such as, for example, linear and/or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and/or combinations thereof, including ensembles such as random forests. Although <FIG> illustrates some of convolution layers of a convolution neural network which is an example of the neural network <NUM>, the convolution neural network may further include a pooling layer, a fully connected layer, or the like in addition to the illustrated convolution layers.

The neural network <NUM> may be implemented with an architecture having a plurality of layers including an input image, feature maps, and output. In the neural network <NUM>, a convolution operation between the input image and a filter referred to as a weight is performed, and feature maps are output as a result of the convolution operation. A convolution operation between the output feature maps as input feature maps and a weight is performed, and new feature maps are output. As a result of repeatedly performing this convolution operation, a result of recognizing features of the input image through the neural network <NUM> may be output.

For example, when an image having a 24x24 pixel size is input to the neural network <NUM> of <FIG>, the input image may be output as <NUM>-channel feature maps having a 20x20 size through a convolution operation between the input image and a weight. Thereafter, the 20x20 feature maps may be reduced in size through a repeated convolution operation between the feature maps and a weight, and features having a 1x1 size may be output finally. The neural network <NUM> may filter and output robust features capable of representing an entire image from the input image by repeatedly performing a convolution operation and a subsampling (e.g., pooling) operation in multiple layers, and may therefrom derive a result of recognizing the input image through output final features.

<FIG> is a diagram illustrating a relationship between an input feature map and an output feature map in a neural network according to some example embodiments.

Referring to <FIG>, in a layer <NUM> of a neural network, a first feature map FM1 may correspond to an input feature map, and a second feature map FM2 may correspond to an output feature map. A feature map may represent a data set in which various features of input data are expressed. The feature maps FM1 and FM2 may have elements of a two-dimensional matrix or elements of a three-dimensional matrix, wherein a pixel value may be defined in each element. The feature maps FM1 and FM2 have a width W (e.g., column), a height H (e.g., row), and a depth D. The depth D may correspond, for example, to the number of channels.

A convolution operation may be performed on the first feature map FM1 and a weight, and the second feature map FM2 may be generated as a result of the convolution operation. The weight filters features of the first feature map FM1 through a convolution operation between the weight and the first feature map FM1. The weight is convoluted with windows (and/or tiles) of the first feature map FM1 while shifting the first feature map FM1 in a sliding window manner. During each shift, the weight may be multiplied by each of pixel values of overlapped windows in the first feature map FM1 and may be added up. Since the first feature map FM1 and the weight are convoluted, one channel of the second feature map FM2 may be generated. Although a single weight is illustrated in <FIG>, a plurality of weights may be convoluted with the first feature map FM1 in practice so that the second feature map FM2 of a plurality of channels may be generated.

The second feature map FM2 may correspond to an input feature map of a next layer. For example, the second feature map FM2 may be an input feature map of a pooling (or subsampling) layer.

For convenience, <FIG> and <FIG> illustrate only a schematic architecture of the neural network <NUM>. However, the neural network <NUM> may include more or fewer layers, feature maps, and weights, and those of ordinary skill in the art could understand that sizes of the layers, feature maps, and weights may be variously modified.

<FIG> are diagrams for comparing an operation performed in a crossbar array and vector-matrix multiplication according to some example embodiments.

Referring to <FIG>, a convolution operation between an input feature map and a weight may be performed using vector-matrix multiplication. For example, pixel data of an input feature map may be expressed as a matrix X <NUM>, and weight values may be expressed as a matrix W <NUM>. Pixel data of an output feature map may be expressed as a matrix Y <NUM>, which may represent a result of multiplication between the matrix X <NUM> and the matrix W <NUM>.

Referring to <FIG>, a vector-matrix multiplication operation may be performed using a nonvolatile memory device of a crossbar array. Comparing with <FIG>, the pixel data of the input feature map may be received as an input value of a nonvolatile memory device, wherein the input value may be a voltage <NUM>. Furthermore, the weight values may be stored in synapses of the nonvolatile memory device (e.g., memory cells) and the weight values stored in the memory cells may be a conductance <NUM> of the synapses. Therefore, an output value of the nonvolatile memory device may be expressed as a current <NUM> that is a result of interaction between the voltage <NUM> and the conductance <NUM>.

<FIG> is a diagram for describing an example of performing a convolution operation in a crossbar array according to some example embodiments.

A crossbar array <NUM> may receive pixel data of an input feature map <NUM>. The crossbar array <NUM> may include a plurality of nonvolatile memory devices.

In some example embodiments, in the case where the crossbar array <NUM> is an NxM matrix (wherein N and M are natural numbers equal to or greater than <NUM>), the number of pieces of pixel data of the input feature map <NUM> may be equal to or less than the number of columns M of the crossbar array <NUM>. The pixel data of the input feature map <NUM> may represent a parameter having a floating point format and/or fixed point format. In other example embodiments, the number of pieces of pixel data of the input feature map <NUM> may be greater than the number of columns M of the crossbar array <NUM>, and relevant detailed descriptions will be provided with reference to <FIG>.

A digital-to-analog converter (DAC) <NUM> may configured to receive digital signal-type pixel data and to convert the pixel data into an analog signal-type voltage. The pixel data of the input feature map <NUM> may have various bit resolution values such as <NUM>-bit, <NUM>-bit, or <NUM>-bit resolution. In some example embodiments, the crossbar array <NUM> may be configured to receive a voltage <NUM> as an input value for the crossbar array <NUM> after converting the pixel data into a voltage using the DAC <NUM>.

Furthermore, trained weight values may be respectively stored in the plurality of nonvolatile memory devices included in the crossbar array <NUM>. The weight values may be stored in memory cells of the nonvolatile memory devices, wherein the weight values stored in the memory cells may be conductance <NUM>. Here, the crossbar array <NUM> may calculate an output value by performing multiplication between the voltage <NUM> and the conductance <NUM>, and the output value may be expressed as a current <NUM>. For example, the crossbar array <NUM> may output the same result value as a result of a convolution operation between an input feature map and a weight using the plurality of nonvolatile memory devices.

Since the current <NUM> output from the crossbar array <NUM> is an analog signal, an analog-to-digital converter (ADC) <NUM> may be used to convert the current <NUM> to input data for another crossbar array <NUM>. The current <NUM> output from the crossbar array <NUM> may be converted into a digital signal by the ADC <NUM>. In some example embodiments, the current <NUM> may be converted into a digital signal so as to have the same bit resolution as the pixel data of the input feature map <NUM> by using the ADC <NUM>. For example, when the pixel data of the input feature map <NUM> has a <NUM>-bit resolution, the current <NUM> may be converted into a <NUM>-bit resolution digital signal by the ADC <NUM>.

An activator <NUM> may apply an activation function to the digital signal achieved through conversion by the ADC <NUM>. The activation function may include a sigmoid function, a tanh function, and/or a rectified linear unit (ReLU) function, but the activation functions that may be applied to a digital signal is not limited thereto.

The digital signal to which the activation function is applied may be used as an input value for another crossbar array <NUM>. When the digital signal to which the activation function is applied is used as an input value for another crossbar array <NUM>, the same process as described above may apply to the other crossbar array <NUM>.

<FIG> is a diagram for describing an example of matching between a crossbar array and a sub feature map according to some example embodiments.

An input feature map <NUM> used for training and inference may have various sizes. Here, since the size of a crossbar array <NUM> is limited, the number of pieces of pixel data of the single input feature map <NUM> may be greater than the number of input values that the crossbar array <NUM> may receive.

Referring to <FIG>, the size of the input feature map <NUM> is 8x8, and the size of the crossbar array <NUM> is 16x16. In this case, the number of pieces of pixel data of the 8x8 input feature map <NUM> is <NUM> (= 8x8) and is thus greater than <NUM> which is the number of input values that the crossbar array <NUM> may receive.

When the number of pieces of pixel data of the input feature map <NUM> is greater than the number of input values of the crossbar array <NUM> (e.g., the number of rows m) the input feature map <NUM> may be divided into sub feature maps <NUM>. The input feature map <NUM> may be divided into the sub feature maps <NUM> based on size information about the crossbar array <NUM>.

In detail, when the size of the input feature map <NUM> is 8x8 and the size of the crossbar array <NUM> is 16x16, the input feature map <NUM> may be divided into four sub feature maps so that the number of pieces of pixel data of each sub feature map may be <NUM>. Each of the sub feature maps may match the crossbar array <NUM>.

For example, the crossbar array <NUM> may be configured to receive a piece of pixel data as an input value, for example, to receive 'aa' of the sub feature map <NUM> as a first input value 'V1', 'ab' of the sub feature map <NUM> as a second input value 'V2', and 'dd' of the sub feature map <NUM> as a 16th input value 'V16'.

As described above with reference to <FIG>, pieces of pixel data of the sub feature map <NUM> may be a digital signal (for example, <NUM>-bit signal, <NUM>-bit signal, or the like) and may be input to the crossbar array <NUM> after being converted into analog voltage signals V<NUM> to V<NUM> by passing through a DAC.

Furthermore, currents I<NUM> to I<NUM> output from the crossbar array <NUM> may be an analog signal, and may be converted into a digital signal by passing through an ADC.

<FIG> are side views illustrating a nonvolatile memory device having phototransistor and memory characteristics according to some example embodiments.

Nonvolatile memory devices <NUM> and <NUM> may include resistance switching layers <NUM> and <NUM>. Gates <NUM> and <NUM> may be on the resistance switching layers <NUM> and <NUM> (e.g., above and/or under the resistance switching layers <NUM> and <NUM>). Gate oxide layers <NUM> and <NUM> may be between the resistance switching layers <NUM> and <NUM> and the gates <NUM> and <NUM>. Furthermore, sources <NUM> and <NUM> and drains <NUM> and <NUM> may be on the resistance switching layers <NUM> and <NUM> and may be spaced apart from each other. The nonvolatile memory devices <NUM> and <NUM> may include the synapses <NUM>, as described above, with the gates <NUM> and <NUM> and the drains <NUM> and <NUM> connected to the presynaptic neuron <NUM> and the postsynaptic neuron <NUM>, respectively.

In some example embodiments, an off-voltage is applied to the gates <NUM> and <NUM> when light is irradiated to the resistance switching layers <NUM> and <NUM>, and relevant detailed descriptions will be provided with reference to <FIG>.

A resistance value of the resistance switching layers <NUM> and <NUM> may be changed based on illumination of light irradiated to the resistance switching layers <NUM> and <NUM>, and may be maintained as a changed resistance value.

For example, since light is irradiated to the resistance switching layers <NUM> and <NUM>, charges (e.g., electrons and/or holes) may be trapped in an internal defect of the resistance switching layers <NUM> and <NUM>. For example, the charges generated in the resistance switching layers <NUM> and <NUM> by a photoelectric response between the resistance switching layers <NUM> and <NUM> to the light. Since the charges are trapped in the internal defects of the resistance switching layers <NUM> and <NUM>, the resistance value of the resistance switching layers <NUM> and <NUM> may be changed, and, thereafter, the resistance value of the resistance switching layers <NUM> and <NUM> may be maintained as a changed resistance value even if light is not irradiated to the resistance switching layers <NUM> and <NUM>.

As the illumination of light irradiated to the resistance switching layers <NUM> and <NUM> increases, a reduction rate of the resistance value of the resistance switching layers <NUM> and <NUM> may increase. In detail, as the illumination of light irradiated to the resistance switching layers <NUM> and <NUM> increases, charges trapped in an internal defect of the resistance switching layers <NUM> and <NUM> may increase. When charges trapped in the resistance switching layers <NUM> and <NUM> increase, the resistance value of the resistance switching layers <NUM> and <NUM> may decrease.

In some example embodiments, the light irradiated to the resistance switching layers <NUM> and <NUM> may be light of a visible light region. The resistance switching layers <NUM> and <NUM> may include the materials described below so that the resistance value of the resistance switching layers <NUM> and <NUM> may change even if light of a visible light region rather than high-energy light such as ultraviolet (UV) light is irradiated to the resistance switching layers <NUM> and <NUM>.

In some example embodiments, the resistance switching layers <NUM> and <NUM> may include a <NUM>-dimension (2D) material. The resistance switching layers <NUM> and <NUM> may include a single-layer 2D material or multi-layer 2D material. For example, the resistance switching layers <NUM> and <NUM> may include at least one of a transition metal dichalcogenide (TMD), phosphorene (black phosphorus), silicene, and/or graphene. The TMD, for example, may include at least one of MoS<NUM>, MoSe<NUM>, MoTe<NUM>, WS<NUM>, WSe<NUM>, WTe<NUM>, TaS<NUM>, TaSe<NUM>, TiS<NUM>, TiSe<NUM>, ZrS<NUM>, ZrSe<NUM>, HfS<NUM>, HfSe<NUM>, SnS<NUM>, SnSe<NUM>, GeS<NUM>, GeSe<NUM>, GaS<NUM>, GaSe<NUM>, GaSe, GaTe, InSe, In<NUM>Se<NUM>, Bi<NUM>S<NUM>, Bi<NUM>Se<NUM> Bi<NUM>Te<NUM>, and/or a combination there.

In other example embodiments, the resistance switching layers <NUM> and <NUM> may include a <NUM>-dimension (3D) material. For example, the resistance switching layers <NUM> and <NUM> may include at least one of germanane, silicon, group III-V semiconductors, an indium based semiconductor such as Indium gallium zinc oxide (IGZO), and/or a combination thereof.

In some example embodiments, the gate oxide layers <NUM> and <NUM> may be formed as a single layer. For example, the gate oxide layers <NUM> and <NUM> may be formed as a single-layer aluminum oxide.

In other example embodiments, the gate oxide layers <NUM> and <NUM> may be formed as a multi-layer. The gate oxide layers <NUM> and <NUM> may include a charge trapping layer. For example, the gate oxide layers <NUM> and <NUM> may have a structure in which a charge trapping layer is between two aluminum oxide layers. The charge trapping layer may include at least one of hafnium oxide and/or silicon nitride, but is not limited thereto.

<FIG> illustrates the nonvolatile memory device <NUM> using the back-gate <NUM>. The back-gate <NUM> may be under the resistance switching layer <NUM>. For example, the back-gate <NUM> may be implemented using an appropriate technology such as silicon on insulator (SOI) substrate technology.

The gate oxide layer <NUM> may be arranged under the resistance switching layer <NUM> and between the resistance switching layer <NUM> and the back-gate <NUM>.

<FIG> illustrates the nonvolatile memory device <NUM> using a transparent conducting electrode (TCE) gate <NUM>. The TCE gate <NUM> may be arranged above the resistance switching layer <NUM>. In <FIG>, "above" and "under" may refer to the position of the gate relative to a potential source of light.

Since light is irradiated to the resistance switching layer <NUM> from above the resistance switching layer <NUM>, the light arrives at the TCE gate <NUM> before reaching the resistance switching layer <NUM>. Since the TCE gate <NUM> capable of transmitting light is used in the nonvolatile memory device <NUM>, light may arrive at the resistance switching layer <NUM> from above the resistance switching layer <NUM>.

The gate oxide layer <NUM> may be arranged above the resistance switching layer <NUM> and between the resistance switching layer <NUM> and the TCE gate <NUM>.

<FIG> is a diagram for describing a phenomenon in which a resistance value of a nonvolatile memory device changes before and after light is irradiated to the nonvolatile memory device.

The nonvolatile memory device may include a resistance switching layer. A gate may be arranged above and/or under the resistance switching layer. A gate oxide layer may be between the resistance switching layer and the gate. Furthermore, a source and a drain may be formed on the resistance switching layer and may be spaced apart from each other.

When an off-voltage is applied to the gate of the nonvolatile memory device, the nonvolatile memory device may operate as a device having phototransistor and memory characteristics. Hereinafter, it is assumed that the nonvolatile memory device is an N-type metal-oxide-semiconductor (NMOS) device, but it would be obvious to those of ordinary skill in the art that the nonvolatile memory device may be implemented as various types of field effect transistors (FETs), for example a variable resistance FET.

A first graph <NUM> indicates a current IS detected from the source of the nonvolatile memory device according to a gate voltage VG before light is irradiated to the nonvolatile memory device.

A second graph <NUM> indicates the current IS detected from the source of the nonvolatile memory device according to the gate voltage VG after light is irradiated to the nonvolatile memory device.

With regard to the first graph <NUM> and the second graph <NUM>, a voltage VD is applied to the drain of the nonvolatile memory device.

Since charges are trapped in an internal defect of the resistance switching layer of the nonvolatile memory device, the current IS having a constant value may be detected from the source even when the gate voltage VG of the nonvolatile memory device is an off-voltage.

The resistance value of the resistance switching layer may be reduced since more charges are trapped in the defect when light is irradiated to the resistance switching layer of the nonvolatile memory device. Thereafter, the resistance value of the resistance switching layer may be maintained as a reduced value even if light is not irradiated to the resistance switching layer.

Referring to the first graph <NUM>, the current detected from the source is I<NUM> when an off-voltage is applied to the gate of the nonvolatile memory device.

Referring to the second graph <NUM> indicating the current detected from the source of the nonvolatile memory device after light is irradiated to the nonvolatile memory device, the current detected from the source may increase from I<NUM> to I<NUM> when an off-voltage is applied to the gate of the nonvolatile memory device. The resistance value of the resistance switching layer reduces since light is irradiated to the resistance switching layer of the nonvolatile memory device, and, accordingly, the current detected from the source of the nonvolatile memory device may increase. Thereafter, the resistance value of the resistance switching layer may be maintained as a changed value even if light is not irradiated to the resistance switching layer of the nonvolatile memory device, and the current detected from the source may also be maintained as I<NUM> when an off-voltage is applied to the gate of the nonvolatile memory device.

In some example embodiments, as the illumination of light irradiated to the resistance switching layer of the nonvolatile memory device increases, charges trapped in the resistance switching layer may increase, and thus the resistance value of the resistance switching layer may be reduced. As a result, the current detected from the source of the nonvolatile memory device may increase above I<NUM>.

Furthermore, when an on-voltage that is equal to or greater than a threshold is applied to the gate of the nonvolatile memory device, the resistance value of the resistance switching layer of the nonvolatile memory device may be reset. For example, a voltage of <NUM> V may be applied to the gate for <NUM> seconds to reset the resistance value of the resistance switching layer.

When the source current has increased from I<NUM> to I<NUM> at an off-voltage of the gate since light is irradiated to the resistance switching layer of the nonvolatile memory device, the source current may decrease from I<NUM> back to I<NUM> when an on-voltage that is equal to or greater than a threshold is applied to the gate of the nonvolatile memory device.

<FIG> and <FIG> are diagrams for describing a process of storing an image and obtaining a stored image using a crossbar array including a plurality of nonvolatile memory devices according to some example embodiments.

Although <FIG> and <FIG> illustrate that an image <NUM> has a 4x4 size, and a crossbar array <NUM> has a 4x4 size, those of ordinary skill in the art could understand that the size of the image <NUM> and the size of the crossbar array <NUM> may be variously modified.

The crossbar array <NUM> may include a plurality of nonvolatile memory devices. In <FIG> and <FIG>, the nonvolatile memory device is expressed as a location (a, b) in which a row and column of the crossbar array <NUM> intersect.

Referring to <FIG>, an image may be stored using the crossbar array <NUM> including the plurality of nonvolatile memory devices.

An off-voltage may be applied to the gate of the plurality of nonvolatile memory devices and a drain voltage VD may be applied to the drain of the plurality of nonvolatile memory devices to store an image using the crossbar array <NUM>.

Light having illumination corresponding to an image may be irradiated to each of the plurality of nonvolatile memory devices to change the resistance value of the resistance switching layer of each of the plurality of nonvolatile memory devices.

Light corresponding to each of a plurality of pixels P<NUM> to P<NUM>, P<NUM> to P<NUM>, P<NUM> to P<NUM>, and P<NUM> to P<NUM> included in the image <NUM> may be irradiated to the plurality of nonvolatile memory devices. For example, light having illumination corresponding to the pixel P<NUM> of the image <NUM> may be irradiated to a nonvolatile memory device (<NUM>, <NUM>), light having illumination corresponding to the pixel P<NUM> of the image <NUM> may be irradiated to a nonvolatile memory device (<NUM>, <NUM>), light having illumination corresponding to the pixel P<NUM> of the image <NUM> may be irradiated to a nonvolatile memory device (<NUM>, <NUM>), and/or light having illumination corresponding to the pixel P<NUM> of the image <NUM> may be irradiated to a nonvolatile memory device (<NUM>, <NUM>).

The brightness of each of the plurality of pixels included in the image <NUM> may be different from each other, and, thus, the illumination of the light irradiated to each of the plurality of nonvolatile memory devices may be different from each other. As a result, variations of the resistance value of the resistance switching layer of each of the plurality of nonvolatile memory devices may be different from each other. The resistance value of the resistance switching layer may be maintained as a changed value even if the light is not being irradiated to the plurality of nonvolatile memory devices.

For example, even if light is not irradiated any more after the resistance value of each of the plurality of nonvolatile memory devices is changed according to the brightness of each of the plurality of pixels included in the image <NUM>, the resistance value of each of the plurality of nonvolatile memory devices is maintained as a changed value, and, thus, the image <NUM> may be stored in the crossbar array <NUM>.

Furthermore, R<NUM> to R<NUM>, R<NUM> to R<NUM>, R<NUM> to R<NUM>, and R<NUM> to R<NUM> shown on the crossbar array <NUM> represent the resistance value of each of the plurality of nonvolatile memory devices.

Referring to <FIG>, a stored image may be obtained using the crossbar array <NUM> including the plurality of nonvolatile memory devices.

A gate off-voltage may be applied to each row of the crossbar array <NUM> to obtain an image stored in the crossbar array <NUM>. In the crossbar array <NUM> illustrated in <FIG>, a nonvolatile memory device to which the gate off-voltage is applied is marked with a circle.

For example, the gate off-voltage may be applied to a first row 901a of the crossbar array <NUM> to obtain the pixels P<NUM> to P<NUM> included in a first row of the image <NUM>. The gate on-voltage may be, subsequently, applied to the second to fourth rows 901b to 901d.

Each of source currents IS11 to IS14 obtained from each column of the crossbar array <NUM> may be determined according to resistance values R<NUM> to R<NUM> of nonvolatile memory devices (<NUM>, <NUM>) to (<NUM>, <NUM>). The resistance values R<NUM> to R<NUM> of the nonvolatile memory devices are determined according to the illumination of light corresponding to the pixels P<NUM> to P<NUM> included in the first row of the image <NUM>. Therefore, the pixels P<NUM> to P<NUM> included in the first row of the image <NUM> may be obtained using the source currents IS11 to IS14 obtained from each column of the crossbar array <NUM>.

Likewise, pixels included in second to fourth rows of the image <NUM> may be sequentially obtained by applying the gate off-voltage to each of second to fourth rows 901b to 901d of the crossbar array <NUM> and applying the gate on-voltage to remaining rows.

In some example embodiments, color filters may be sequentially arranged on the crossbar array <NUM> to obtain a color image from the crossbar array <NUM>.

For example, a color image may be obtained from the crossbar array <NUM> using three color filters including red, green, and/or blue color filters.

For example, after arranging a red color filter on the crossbar array <NUM>, light having illumination corresponding to each of a plurality of pixels included in a color image may be irradiated to each of a plurality of nonvolatile memory devices. A red image may be obtained by applying the gate off-voltage to each row of the crossbar array <NUM> and obtaining the source current from each column of the crossbar array <NUM>.

A green image and a blue image may be obtained by repeating the above-described operation using a green color filter and a blue color filter after resetting the crossbar array <NUM> by applying the gate on-voltage thereto. After the red image, the green image, and the blue image are obtained, a color image may be finally obtained by synthesizing the three images.

The crossbar array <NUM> including the plurality of nonvolatile memory devices according to the present disclosure may have photoconductivity (PC) characteristics and thus may be used in an imaging mode (image storing/acquisition) due to the characteristics.

<FIG> is a diagram for describing a process of performing a pooling operation of a neural network using a crossbar array including a plurality of nonvolatile memory devices according to some example embodiments.

Although <FIG> illustrate that an image <NUM> has a 8x8 size, and a crossbar array <NUM> has a 16x16 size, those of ordinary skill in the art could understand that the size of the image <NUM> and the size of the crossbar array <NUM> may be variously modified. For example, the image <NUM> may be an image representing either the number '<NUM>' or '<NUM>', but is not limited thereto.

In some example embodiments, a window <NUM> may be shifted by a stride on the image <NUM>. The stride may be, for example, predetermined. A size of the window <NUM> may be determined based on the size of the crossbar array <NUM>. In some example embodiments, the size of the window <NUM> may be determined based on the number of rows of the crossbar array <NUM>. For example, in the case where the number of rows of the crossbar array <NUM> is <NUM>, the size of the window <NUM> may be 4x4.

Hereinafter, the window <NUM> is shifted by '<NUM> stride', and the size of the window <NUM> is 4x4, but those of ordinary skill in the art could understand that shift and size of the window <NUM> may be variously modified.

A plurality of pixels may be included in the window <NUM> in each location on the image <NUM>. For example, in a first location, the window <NUM> may include pixels P<NUM> to P<NUM>, P<NUM> to P<NUM>, P<NUM> to P<NUM>, and P<NUM> to P<NUM>. Furthermore, the window <NUM> may include pixels P<NUM> to P<NUM>, P<NUM> to P<NUM>, P<NUM> to P<NUM>, and P<NUM> to P<NUM> in a location shifted by <NUM> stride from the first location.

Light having illumination corresponding to the plurality of pixels included in the window <NUM> may be irradiated to each column of the crossbar array <NUM>. For example, light having illumination corresponding to the plurality of pixels P<NUM> to P<NUM>, P<NUM> to P<NUM>, P<NUM> to P<NUM>, and P<NUM> to P<NUM> included in the window <NUM> at the first location may be irradiated to a first column 1002a of the crossbar array <NUM>. That is, light having illumination corresponding to each of <NUM> pixels included in the window <NUM> at the first location may be irradiated to <NUM> nonvolatile memory devices included in the first column 1002a.

Likewise, light having illumination corresponding to a plurality of pixels included in the window <NUM> at an nth location may be irradiated to an nth column of the crossbar array <NUM>.

A gate off-voltage may be applied to the first to 16th rows 1001a to 1001p of the crossbar array <NUM>. Furthermore, drain voltages V<NUM> to V<NUM> may be applied to the first to 16th rows 1001a to 1001p of the crossbar array <NUM>. The drain voltages V<NUM> to V<NUM> may be set as a mask used for the pooling operation.

The pooling operation may be performed by obtaining a source current from each column of the crossbar array <NUM>. For example, a first-first source current IS11 obtained from the first column 1002a may be a result of pooling performed on the plurality of pixels P<NUM> to P<NUM>, P<NUM> to P<NUM>, P<NUM> to P<NUM>, and P<NUM> to P<NUM> included in the window <NUM> at the first location.

Likewise, first-second source current to first-fifth source current IS12 to IS15 obtained from second to fifth columns 1002b to 1002e may be results of pooling performed on the window <NUM> at second to fifth locations.

Furthermore, since the window <NUM> may be positioned at <NUM> locations on the image <NUM>, a pooling operation of a neural network may be completed by obtaining results of pooling performed on the plurality of pixels included in the window <NUM> at first to 25th locations through the above-described method.

The crossbar array <NUM> including the plurality of nonvolatile memory devices according to the present disclosure may perform a vector-matrix operation (e.g., pooling operation), and the crossbar array <NUM> may be used for in-memory computing by using this characteristic.

<FIG> is a diagram for describing a process of performing a convolution operation of a neural network using a crossbar array including a plurality of nonvolatile memory devices according to some example embodiments.

The crossbar array <NUM> may store a plurality of weights included in a specific layer of a neural network. A plurality of weights may be stored in the crossbar array <NUM> by irradiating light having illumination corresponding to each of the plurality of weights included in a specific layer to each of the plurality of nonvolatile memory devices of the crossbar array <NUM>. A specific method of this operation is described above with reference to <FIG> and is thus omitted here.

In some example embodiments, a fully-connected convolution operation may be performed using the crossbar array <NUM>. In <FIG>, a fully-connected convolution operation for recognizing the image <NUM> of <FIG> is performed. For example, the fully-connected convolution operation may be performed using the crossbar array <NUM> to determine which number among numbers <NUM> to <NUM> the image <NUM> corresponds to.

The crossbar array <NUM> may be reset to perform the fully-connected convolution operation.

A drain voltage of the crossbar array <NUM> may correspond to an input value for a fully-connected layer. The first-first source current to first-fifth source current IS11 to IS15 obtained from the crossbar array <NUM> and corresponding to the window <NUM> at the first to fifth locations may correspond to an input value for a fully-connected layer.

For example, the first-first source current to first-fifth source current IS11 to IS15 may be converted into first to fifth drain voltages VD11 to VD15. Furthermore, the first to fifth drain voltages VD11 to VD15 may be respectively applied to the first to fifth rows 1001a to 1001e.

The image <NUM> may be recognized by obtaining a source current from each column of the crossbar array <NUM>. For example, a second-first source current I<NUM> may be obtained from the first column 1002a indicates a probability that the image <NUM> will correspond to the number '<NUM>'. Furthermore, second-second source current to second-ninth source current I<NUM> to I<NUM> may be obtained from the second to ninth columns 1002b to 1002i respectively indicate probabilities that the image <NUM> will correspond to the numbers '<NUM>' to '<NUM>'.

The window <NUM> may be positioned at <NUM> locations on the image <NUM>, and the second-first source current to second-ninth source current I<NUM> to I<NUM> obtained from the crossbar array <NUM> are merely results of fully-connected operations performed on the window <NUM> at the first to fifth locations. That is, the image <NUM> may be finally recognized by obtaining results of fully-connected operations performed on the window <NUM> at remaining locations on the image <NUM>.

The above-described process may be repeated to obtain, from the crossbar array <NUM>, the second-first source current to second-ninth source current I<NUM> to I<NUM> for the first to ninth columns 1002a to 1002i based on <NUM> source currents corresponding to the window <NUM> at the first to 25th locations.

The second-first source current to second-ninth source current I<NUM> to I<NUM> obtained from the first to ninth columns 1002a to 1002i of the crossbar array <NUM> may indicate probabilities that the image <NUM> will correspond to the numbers '<NUM>' to '<NUM>'. The image <NUM> may be finally recognized as a number having a highest probability value among the numbers '<NUM>' to '<NUM>'. For example, when a value of the second-first source current I<NUM> is greatest, the image <NUM> may be finally recognized as the number '<NUM>'.

The plurality of weights stored in a specific layer of the neural network may be updated as training of the neural network progresses. When the weights are updated, the updated weights may be stored in the crossbar array <NUM> by irradiating light having illumination corresponding to each of the updated weights to each of the plurality of nonvolatile memory devices after resetting the crossbar array <NUM>. The crossbar array <NUM> may be widely used for training and inference processes of a neural network.

The crossbar array <NUM> including the plurality of nonvolatile memory devices according to the present disclosure may perform a vector-matrix operation, and the crossbar array <NUM> may be used for training and inference processes for image recognition by using this characteristic.

In some example embodiments, a crossbar array used in an imaging mode (image storing/acquisition) may be used in a recognition mode (neural network training/inference) after being reset. Therefore, a single crossbar array may be used both in the imaging mode and in the recognition mode.

<FIG> is a flowchart for describing a method of performing a predetermined operation using a crossbar array according to some example embodiments. The method of performing a predetermined operation, illustrated in <FIG>, is related to the embodiments described above with reference to the above-mentioned drawings. Thus, although omitted below, the descriptions provided above with reference to the above-mentioned drawings may apply to the method of <FIG>.

The crossbar array described below may include a plurality of nonvolatile memory devices. The nonvolatile memory device may include a resistance switching layer. A gate may be arranged above or under the resistance switching layer. A gate oxide layer may be formed between the resistance switching layer and the gate. Furthermore, a source and a drain may be formed on the resistance switching layer and may be spaced apart from each other.

Referring to <FIG>, an off-voltage may be applied to a gate of each of the plurality of nonvolatile memory devices in operation <NUM>.

When the off-voltage is applied to the gate of the nonvolatile memory device, the nonvolatile memory device may operate as a device having phototransistor and memory characteristics. The gate off-voltage may be -<NUM> V but is not limited thereto.

Furthermore, when an on-voltage is applied to the gate of the nonvolatile memory device, the nonvolatile memory device may be reset.

In operation <NUM>, light having illumination corresponding to each of a plurality of elements may be irradiated to each of the plurality of nonvolatile memory devices to change the resistance value of the resistance switching layer of each of the plurality of nonvolatile memory devices.

The resistance value of the resistance switching layer may be changed based on the illumination of light irradiated to the resistance switching layer, and may be maintained as a changed resistance value. In detail, since charges are trapped in an internal defect of the resistance switching layer when light is irradiated to the resistance switching layer, the resistance value of the resistance switching layer may be changed, and, thereafter, the resistance value of the resistance switching layer may be maintained as a changed resistance value even if light is not irradiated to the resistance switching layer.

As the illumination of light irradiated to the resistance switching layer increases, a reduction rate of the resistance value of the resistance switching layer may increase. As the illumination of light irradiated to the resistance switching layer increases, charges trapped in internal defects of the resistance switching layer may increase. When charges trapped in the resistance switching layer increase, the resistance value of the resistance switching layer may decrease.

As noted above, in some example embodiments, the resistance switching layer may include a 2D material. For example, the resistance switching layer may include at least one selected from the group consisting of transition metal dichalcogenide (TMD), silicene, phosphorene (black phosphorus), and graphene.

Furthermore, the resistance switching layer may include a 3D material. For example, the resistance switching layer may include at least one selected from the group consisting of germanane, silicon, groups III-V semiconductors, and/or IGZO.

In operation <NUM>, a gate off-voltage may be applied to at least one row of the crossbar array and obtaining a source current from each column of the crossbar array.

In some example embodiments, a processor <NUM> may be configured to operate and/or control the method of performing a predetermined operation using a crossbar array, described above. The processor <NUM> may further be configured obtain an image using the crossbar array. In this case, the plurality of elements may be a plurality of pixels included in the image.

Light having illumination corresponding to each of the plurality of pixels included in the image may be irradiated to each of the plurality of nonvolatile memory devices. The processor <NUM> may obtain the image by applying the gate off-voltage to each row of the crossbar array and obtaining the source current from each column of the crossbar array.

Furthermore, color filters may be sequentially arranged on the crossbar array to obtain a color image from the crossbar array.

In some example embodiments, the processor <NUM> may perform an operation of a neural network using the crossbar array. In this case, the plurality of elements may be a plurality of weights included in a specific layer of the neural network.

Light having illumination corresponding to each of the plurality of weights included in a specific layer of the neural network may be irradiated to each of the plurality of nonvolatile memory devices. The processor <NUM> may perform an operation of the neural network by applying a gate off-voltage to at least one row of the crossbar array and obtaining a source current from each column of the crossbar array. For example, the operation of the neural network may include a pooling operation, a convolution operation, and a full-connected convolution operation, but is not limited thereto.

In the present disclosure, an image may be stored using the crossbar array, or a stored image may be obtained from the crossbar array. Furthermore, in the present disclosure, an image may be recognized by performing an operation of a neural network using the crossbar array.

<FIG> is a block diagram illustrating a memory system according to some example embodiments.

Referring to <FIG>, a memory system <NUM> may include a processor <NUM> and at least one crossbar array <NUM>. The processor <NUM> may perform a control operation on the crossbar array <NUM> and, for example, may provide an address ADD and a command CMD to the crossbar array <NUM> to perform data storing, reading, and erasing operations on the crossbar array <NUM>. Furthermore, data to be stored or read may be transmitted/received between the processor <NUM> and the crossbar array <NUM>.

The crossbar array <NUM> may include a plurality of nonvolatile memory devices arranged in regions in which a plurality of rows and a plurality of columns intersect. In some example embodiments, the nonvolatile memory device may include a resistance switching layer. A gate may be above and/or under the resistance switching layer. A gate oxide layer may be between the resistance switching layer and the gate. Furthermore, a source and a drain may be on the resistance switching layer and may be spaced apart from each other.

The processor <NUM> may include a storing/reading controller <NUM>, a voltage controller <NUM>, and a data discriminator <NUM>. However, the above-mentioned elements included in the processor <NUM> are merely examples, and it would be obvious to those of ordinary skill in the art that some elements may be excluded or other elements may be further included.

The storing/reading controller <NUM> may be configured to generate the address ADD and the command CMD for performing data storing, reading, and erasing operations on the crossbar array <NUM>. The voltage controller <NUM> may be configured to generate a voltage control signal for controlling at least one voltage level used in the crossbar array <NUM>. For example, the voltage controller <NUM> may generate a voltage control signal for controlling a level of a voltage applied to a row of the crossbar array <NUM> to read data from the crossbar array <NUM> or store data in the crossbar array <NUM>.

The data discriminator <NUM> may be configured to discriminate data read from the crossbar array <NUM>. For example, the data discriminator <NUM> may discriminate data read from the crossbar array <NUM> to determine whether each of the plurality of nonvolatile memory devices included in the crossbar array <NUM> is in an on state or off state. For example, once data is stored in the crossbar array <NUM>, the data discriminator <NUM> may discriminate a state of data of the plurality of nonvolatile memory devices included in the crossbar array <NUM> using a reading voltage to determine whether the data has been stored normally in the nonvolatile memory devices.

The processor <NUM>, and/or the included storing/reading controller <NUM>, voltage controller <NUM>, and data discriminator <NUM>. may include, for example, processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuity more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), and programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc..

The present embodiments may be implemented as a form of recording medium containing computer-executable instructions, such as program modules executed by a computer. A computer-readable medium may include any available medium accessible by a computer, and may include all of volatile and non-volatile media and detachable and non-detachable media. Furthermore, the computer-readable medium may include all of computer storage media and communication media. The computer storage media include all of volatile and non-volatile media and detachable and non-detachable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules, and/or other data. The communication media may typically include other data of modulated data signals such as computer-readable instructions, data structures, and program modules, or other transmission mechanisms, and include any information delivery media.

The above description is merely illustrative, and it would be easily understood that those of ordinary skill in the art could easily make modifications without departing from the technical concept of the present disclosure or changing essential features. Therefore, the above embodiments should be considered illustrative and should not be construed as limiting. For example, each component described as a single type may be distributed, and likewise, components described as being distributed may be implemented as a combined form.

According to the present disclosure, a crossbar array including a plurality of nonvolatile memory devices may have photoconductivity characteristics, and thus may be used to store/acquire an image due to the characteristics.

Furthermore, according to the present disclosure, a crossbar array used in an imaging mode (image storing/acquisition) may be used in a recognition mode (neural network training/inference) after being reset. Accordingly, the imaging mode and the recognition mode may be performed using a single crossbar array.

Claim 1:
A crossbar array (<NUM>) adapted to store an image based on an illumination of light irradiated thereto, the crossbar array comprising a plurality of nonvolatile memory devices (<NUM>, <NUM>) comprising:
a resistance switching layer (<NUM>, <NUM>) having a resistance value, the resistance switching layer being configured to change the resistance value based on an illumination of light irradiated thereto from above, and the resistance switching layer being configured to maintain the changed resistance value,
a gate on the resistance switching layer;
a gate oxide layer (<NUM>, <NUM>) between the resistance switching layer and the gate; and
a source (<NUM>, <NUM>) and a drain (<NUM>, <NUM>), spaced apart from each other, on the resistance switching layer, wherein
the gate includes a transparent conducting electrode gate (<NUM>) above the resistance switching layer and configured to transmit the irradiated light, or
the gate includes a back-gate (<NUM>) under the resistance switching layer; and
wherein the crossbar array is adapted to store the image based on an illumination of light irradiated thereto by way of the change in a resistance value of a resistance switching layer of each of the plurality of nonvolatile memory devices when light having illumination corresponding to a plurality of elements to the plurality of nonvolatile memory devices is irradiated thereto, and wherein the irradiated light corresponds to a plurality of pixels included in an image.