Patent Description:
Power semiconductor devices (such as an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), silicon carbide (SiC), gallium nitride (GaN), and the like) are widely applied to power supplies and power electronic converters. Therefore, module packaging is generally used in a high-power scenario. A power module mainly includes a metal bottom plate, a welding layer, double-sided direct bonding copper (DBC) ceramic substrate, active metal bonding (AMB) ceramic substrate, an insulating heat dissipation resin film or other insulating heat dissipation materials, a copper frame, an outer housing, and silica gel, as shown in <FIG> and <FIG>. Copper has strong conductivity, which can reduce turn-on resistance and parasitic inductance. In addition, the contact area between the copper frame and a chip is large, and the thermal expansion coefficient of the copper is <NUM>×<NUM>-<NUM>/K, which is much less than the thermal expansion coefficient of aluminum (namely, <NUM>×<NUM>-<NUM> /K) and closer to a thermal expansion coefficient of the chip (namely, <NUM>×<NUM>-<NUM>/K to <NUM>×<NUM>-<NUM>/K), thereby achieving a longer power cycle life. The bonding with the copper frame also has a series of disadvantages. First, the copper frame is generally made through stamping by using a special die, resulting in a high cost. Second, a relatively thick copper frame needs to be used to reduce the turn-on resistance. However, relatively large mechanical stress is generated on the chip when the temperature on the contact surface between the relatively thick copper frame and the chip changes, which may break or damage the chip in serious cases. Third, when a plurality of chips is connected to the DBC ceramic substrate or other insulating heat dissipation materials, the position of each chip may have a deviation. However, the position of each contact surface of the copper frame cannot be adjusted after the copper frame is processed, which may cause a position deviation during processing, resulting in defective products. To reduce defective products, accurate chip and frame positioning processes are required.

The US patent publication no. <CIT> discloses a power module, specifically an interconnect structure and a package structure of a power module. The power module includes: a base portion having one surface on which an electrode portion is formed; a conductor portion disposed to face the one surface of the base portion on which the electrode portion is formed, for making electrical connection with the outside; and an interconnect portion connected to the electrode portion formed on the one surface of the base portion and to the surface of the conductor portion facing the one surface of the base portion for electrically connecting the electrode portion to the conductor portion.

The US patent publication no. <CIT> discloses an electrode terminal for connecting a main electrode on the front face side of a semiconductor element for electrical power with an external circuit, a semiconductor device for electrical power using the same, and a manufacturing method of that device. The electrode terminal includes: a first drawn-out part to be bonded to a main electrode; and a second drawn-out part that is formed of a plate member in a continuous fashion from one end portion to be positioned opposite to the main electrode with a gap therebetween until another end portion to be connected to an external circuit, so that a portion in the first drawn-out part that is adj acent to a portion therein to be bonded to the main electrode, is bonded to an opposing surface to the main electrode in said one end portion; wherein the first drawn-out part is formed so that the portion to be bonded to the main electrode is away from the opposing surface; and wherein an opening portion corresponding to the main electrode is formed in the second drawn-out part.

The US patent application publication <CIT> discloses a power semiconductor module with a metal connecting plate connecting an internal circuit portion and a semiconductor element. The metal connecting plate does not touch the outer housing of the power semiconductor module.

Although the above-mentioned prior art documents provide improvements in the connection of components in power semiconductor modules, there is still a need for enhancement of thermal management and for reducing the risk of cracking or failure due to thermal cycling or mechanical stress.

The present disclosure provides a power semiconductor module to resolve the prior-art problem of mechanical stress generated on a chip in the case of a temperature change when a relatively thick copper frame is applied to the packaging of the power semiconductor module.

To resolve the above technical problem, the present disclosure provides a power semiconductor as defined in claim <NUM>.

The dependent claims define preferred embodiments of the invention.

The present disclosure has the following beneficial effects: <NUM>. Compared with the prior art, in the power semiconductor module in the present disclosure, the copper strap in contact with the chip generates small mechanical stress on the chip when a temperature change occurs on the copper strap so it does not break or damage the chip. Most of the current of the circuit passes through the relatively thick copper plate, which greatly reduces turn-on resistance and parasitic inductance. The position deviation of the chip can be compensated for by adjusting the position of the copper strap, thus lowering the requirement for a positioning process. This simplifies the processing technology and improves the yield of products.

Reference numerals: <NUM>: metal bottom plate; <NUM>: insulating heat dissipation material layer; <NUM>: chip; <NUM>: binding plate; <NUM>: silica gel; <NUM>: outer housing; <NUM>: copper plate; <NUM>: copper strap.

To make the objective, technical solutions, and advantages of the present disclosure clear, the present disclosure will be further described in detail below by referring to the accompanying drawings and specific embodiments.

As shown in <FIG>, <FIG>, and <FIG>, the present disclosure provides a power semiconductor module, including metal bottom plate <NUM>, insulating heat dissipation material layer <NUM>, chip <NUM>, binding plate <NUM>, silica gel <NUM>, and outer housing <NUM>. The binding plate <NUM> includes copper plate <NUM> and a plurality of copper straps <NUM>. The copper plate <NUM> is connected to the plurality of copper straps <NUM> through welding, and the binding plate <NUM> is configured to connect circuits of various components. The metal bottom plate <NUM> is connected to the insulating heat dissipation material layer <NUM> through tin soldering. The chip <NUM> is connected to the insulating heat dissipation material layer <NUM> through tin soldering. The chip <NUM> is also connected to a part of the plurality of copper straps <NUM>, and the other part of the plurality of copper straps <NUM> is connected to the insulating heat dissipation material layer <NUM>.

Further, preferably, the outer housing <NUM> is connected to the metal bottom plate <NUM> by using a dispensing process.

Further, preferably, the silica gel <NUM> fills the outer housing <NUM> to prevent corrosion and moisture, protect an internal circuit, and isolate internal components with a high voltage.

Further, preferably, the copper plate <NUM> is connected to the plurality of copper straps <NUM> through laser welding and ultrasonic welding.

The thickness of the copper plate <NUM> ranges from <NUM> to <NUM>, and the thickness of the copper strap <NUM> ranges from <NUM> to <NUM>.

As shown in <FIG> and <FIG>, the present disclosure provides a power semiconductor module, including metal bottom plate <NUM>, insulating heat dissipation material layer <NUM>, chip <NUM>, binding plate <NUM>, silica gel <NUM>, and outer housing <NUM>, where the binding plate <NUM> includes copper plate <NUM> and a plurality of copper straps <NUM>. The copper plate <NUM> is connected to the plurality of copper straps <NUM> through welding. The binding plate <NUM> is configured to connect circuits of various components. The metal bottom plate <NUM> is connected to the insulating heat dissipation material layer <NUM> through tin soldering. The chip <NUM> is connected to the insulating heat dissipation material layer <NUM> through tin soldering and, the chip <NUM> is connected to a part of the plurality of copper straps <NUM>, and the other part of the plurality of copper straps <NUM> is connected to the insulating heat dissipation material layer <NUM>.

A contact surface between the copper strap <NUM> and the chip <NUM> is ground to eliminate a deviation, thereby increasing the contact area between the copper strap <NUM> and the chip <NUM>. In addition, the thickness of the copper strap <NUM> on the contact surface between the copper strap <NUM> and the chip <NUM> is further reduced to reduce mechanical stress when the copper strap <NUM> is combined with the chip <NUM>, thereby further improving reliability.

As shown in <FIG> and <FIG>, the present disclosure provides a power semiconductor module, including metal bottom plate <NUM>, insulating heat dissipation material layer <NUM>, chip <NUM>, binding plate <NUM>, silica gel <NUM>, and outer housing <NUM>, where the binding plate <NUM> includes copper plate <NUM> and a plurality of copper straps <NUM>. The copper plate <NUM> is connected to the plurality of copper straps <NUM> through welding, and the binding plate <NUM> is configured to connect circuits of various components. The metal bottom plate <NUM> is connected to the insulating heat dissipation material layer <NUM> through tin soldering, the chip <NUM> is connected to the insulating heat dissipation material layer <NUM> through tin soldering, the chip <NUM> is connected to a part of the plurality of copper straps <NUM>, and the other part of the plurality of copper straps <NUM> is connected to the insulating heat dissipation material layer <NUM>.

In accordance with an embodiment not according to the invention, the copper plate <NUM> and a main electrode terminal form an integrated structure.

In <FIG>, the copper plate <NUM> is separated from an electrode terminal for connecting an external circuit, which generates additional resistance and parasitic inductance. In this embodiment, the copper plate <NUM> and the main electrode terminal form the integrated structure, thereby further reducing the resistance and parasitic inductance.

As shown in <FIG>, the present disclosure provides, in an embodiment not forming part of the invention as claimed, a power semiconductor module, including metal bottom plate <NUM>, insulating heat dissipation material layer <NUM>, chip <NUM>, and binding plate <NUM>. The binding plate <NUM> includes copper plate <NUM> and a plurality of copper straps <NUM>, and the copper plate <NUM> is connected to the plurality of copper straps <NUM> through welding. The binding plate <NUM> is configured to connect circuits of various components. The metal bottom plate <NUM> is connected to the insulating heat dissipation material layer <NUM> through tin soldering, the chip <NUM> is connected to the insulating heat dissipation material layer <NUM> through tin soldering, the chip <NUM> is connected to a part of the plurality of copper straps <NUM>, and the other part of the plurality of copper straps <NUM> is connected to the insulating heat dissipation material layer <NUM>.

The semiconductor module is plastically packaged using a resin material. Based on the shape and parameter design needs, a special die is used to fill the resin into the semiconductor module. The chip <NUM>, the insulating heat dissipation material layer <NUM>, and the binding plate <NUM> of the semiconductor module are packaged and fixed, for example, <NUM> and <NUM> in <FIG> are replaced by an integrated resin material. In accordance with an embodiment outside the scope of the invention as claimed, this integrated plastic packaging method does not require silica gel or an outer housing, thereby simplifying the production process and achieving higher production efficiency and higher product reliability.

In conclusion, in the power semiconductor module in the present disclosure, the copper strap in contact with the chip generates small mechanical stress on the chip when a temperature change occurs on the copper strap so it does not break or damage the chip. Most of the current of the circuit passes through the relatively thick copper plate, which greatly reduces turn-on resistance and parasitic inductance. In addition, the position deviation of the chip can be compensated for by adjusting the position of the copper strap, thus lowering the requirement for a positioning process. This simplifies the processing technology and improves the yield of the product.

The above description describes merely preferred embodiments of the present disclosure and is not intended to limit the present disclosure, and various changes and modifications of the present disclosure may be made by those skilled in the art.

Claim 1:
A power semiconductor module, comprising a metal bottom plate (<NUM>), an insulating heat dissipation material layer (<NUM>), a chip (<NUM>), a binding plate (<NUM>), silica gel (<NUM>), and an outer housing (<NUM>), wherein
the binding plate (<NUM>) comprises a copper plate (<NUM>) and a copper strap (<NUM>), the copper plate (<NUM>) is connected to the copper strap (<NUM>) through welding,
the binding plate (<NUM>) is configured to connect circuits of various components,
the metal bottom plate (<NUM>) is connected to the insulating heat dissipation material layer (<NUM>) through tin soldering,
the chip (<NUM>) is connected to the insulating heat dissipation material layer (<NUM>) through tin soldering,
the copper plate (<NUM>) is connected to the chip (<NUM>) via the copper strap (<NUM>), and the copper plate (<NUM>) is connected to the insulating heat dissipation material layer (<NUM>) via the copper strap (<NUM>),
characterized in that the copper plate (<NUM>) does not touch with the outer housing (<NUM>).