Patent Description:
The scope of protection is defined according to the independent claims. Additional advantageous embodiments are disclosed according to the appended dependent claims.

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. Views labeled "cross-sectional", "profile", "plan", and "isometric" correspond to orthogonal planes within a Cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z plane, plan views are taken in the x-y plane, and isometric views are taken in a <NUM>-dimensional Cartesian coordinate system (x-y-z). Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.

The term "microprocessor" generally refers to an integrated circuit (IC) package comprising a central processing unit (CPU) or microcontroller. The microprocessor package is referred to as a "microprocessor" in this disclosure. A microprocessor socket receives the microprocessor and couples it electrically to a printed circuit board (PCB).

Here, the term "back end of the line (BEOL) generally refers to post-device fabrication operations on a semiconductor wafer. After formation of the active and passive devices within a circuit layer on the semiconductor wafer in a front-end of the fabrication line (e.g., front-end-of-the line or FEOL), a series of operations where metal features are formed (metallization) over the semiconductor devices comprise the BEOL portion of the fabrication line.

The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on. " The vertical orientation is in the z-direction and it is understood that recitations of "top", "bottom", "above" "over" and "below" refer to relative positions in the z-dimension with the usual meaning. Generally, "top", "above", and "over" refer to a superior position on the z-dimension, whereas "bottom", "below" and "under" refer to an inferior position on the z-dimension. The term "on" is used in this disclosure to indicate that one feature or object is in a superior position relative to an inferior feature or object, and in direct contact therewith. However, it is understood that embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.

The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B).

Described herein is a vertically integrated composite integrated circuit (IC) device structure formed by hybrid bonding of two or more stacked IC dies. The top level metallization of the dies comprise recessed test pads. The pads are recessed below the level of the metallization stack surface so that increased surface topography caused by contact with test probes during back-end die testing is confined below the surface of the metallization stack.

<FIG> illustrates a cross sectional view in the x-z plane of composite die structure <NUM>, according to some embodiments of the disclosure.

Composite IC die structure <NUM> comprises upper IC die <NUM> vertically integrated with lower IC die <NUM>. Upper and lower IC dies <NUM> and <NUM> are bonded together at bonding interface <NUM>. IC die <NUM> is shown in an inverted orientation relative to IC die <NUM>, where substrate <NUM> is above device layer <NUM>. IC die <NUM> comprises substrate <NUM>, device layer <NUM> on substrate <NUM>, and metallization stack <NUM> over device layer <NUM>. Metallization stack <NUM> extends from surface <NUM> of substrate <NUM> (e.g., front side of device layer <NUM>) to bonding interface <NUM>. Device layer <NUM> comprises active devices, passive devices or a combination of active and passive devices. Active devices may include arrays of field-effect (FET) or bipolar junction transistors arranged in logic circuits, for example, to form memory, field programmable gate arrays, and other logic circuits. Transistors may also be combined with passive components to form analog circuits, such as amplifiers and the like. In some embodiments, dies <NUM> and <NUM> comprise a microprocessor and/or memory logic circuits. As an example, die <NUM> may be a memory chip and die <NUM> may be a microprocessor, where dies <NUM> and <NUM> are coupled together by bonding of the interfaced metallization stacks, as described below. Feature pitches, defined as distances between like interconnect terminals over gate, source or drain regions of individual transistors may range between <NUM> and <NUM> nanometers (nm). For example, gate-to-gate pitches may be between <NUM>-<NUM>.

Metallization stack <NUM> comprises conductive layers <NUM>, <NUM> and <NUM> embedded within interlayer dielectric (ILD) <NUM> at progressively increasing heights within metallization stack <NUM>. While three conductive layers <NUM>-<NUM> are shown, metallization stack <NUM> may comprise any suitable number of conductive layers. ILD <NUM> may comprise multiple layers, as may be formed, for example, during a damascene build-up process of stack <NUM>. For clarity, boundaries between adjacent ILD layers are not shown in the figure. In some embodiments, ILD <NUM> comprises materials such as, but are not limited to, silicon oxides (e.g., SixO<NUM>-x), silicon nitrides (e.g., SixN(<NUM>-x)), silicon oxynitrides (e.g., SixOyN(<NUM>-x-y)), silicon carbide (e.g., SiC) and silicon carbide nitrides (e.g., SixCyN<NUM>-x-y), aluminum oxides, and aluminum nitrides. In some embodiments, ILD layers <NUM> comprise low-k materials ha ving a relative permittivity below that of SiO<NUM> (e.g., k ≤ <NUM>). ILD layer(s) <NUM> may comprise any of the above materials or a silicate glass, such as, but not limited to, fluorosilicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BSG) or undoped silicate glass (USG), organosilicate glass (OSG - e.g., carbon-doped oxide, CDO) porous OSG, and porous silicon dioxide. In some embodiments, one or more of ILD layers <NUM> may comprise low-k organic polymeric materials such as polyimides, hydrogen silsesquioxane and methyl silsesqjuioxane. The above dielectric materials may be formed by spin coating methods (e.g., spin-on glass, SOG), chemical vapor deposition (CVD) or sol gel techniques.

Layer thicknesses for both conductive layers <NUM>, <NUM> and <NUM>, as well as layers of dielectric <NUM> (not shown), may range from <NUM>, or less, in the lower levels proximal to substrate <NUM>, to <NUM> microns, or more, in the upper levels near the top of metallization stack <NUM>. Metallization features within the conductive layers <NUM>-<NUM> may include horizontal traces, for example. In the figure, metallization structures (e.g., structures <NUM>, <NUM>, <NUM> and <NUM>) are represented as traces shown in cross-section. Inter-level vias (not shown) may extend between and vertically interconnect metallization features in conductive layers <NUM>, <NUM> and <NUM>. In some embodiments, minimum feature size and pitch may fan out (e.g., increase with increasing distance) from device layer <NUM>.

Conductive layers <NUM>-<NUM> comprise metallization structures <NUM>, <NUM>, <NUM> and <NUM>, respectively. In some embodiments, metallization structures <NUM>-<NUM> comprise conductive materials such as, but not limited to, copper, copper-aluminum alloy, aluminum, silver, gold, nickel, indium, and tungsten, cobalt, tungsten, tantalum, and titanium. A thin conformal barrier layer (not shown) comprising titanium, tungsten or tantalum may line the interface between ILD <NUM> and the bulk conductive material within the metallization structures. Lowest (e.g., proximal to device layer <NUM>) conductive level <NUM> is labelled 'metal <NUM>' (e.g., M1). Interconnect structures <NUM> within M1 may have the smallest CD of metallization structures within metallization stack <NUM>, to match feature pitches of active and passive components within device layer <NUM>. Feature pitches, defined as distances between like interconnect terminals over gate, source or drain regions of individual transistors may range between <NUM> and <NUM> nanometers (nm). For example, gate-to-gate pitches may be between <NUM>-<NUM>.

The higher conductive layers <NUM> and <NUM> are labelled M2 and M3, respectively. Metallization structures <NUM> may be vertically interconnected to metallization structures <NUM> in M2 through interlevel vias (not shown). Although not explicitly shown in the illustrated embodiments, interlevel vias generally provide vertical interconnection of metallization features in adjacent conductive layers within a metallization stack such as stack <NUM>. In some embodiments, metallization features (e.g., metallization structures <NUM>-<NUM>) progressively increase in feature size (e.g., critical dimension, CD) and pitch in progressively higher conductive levels. In some embodiments, metallization features have substantially constant CD at all or most levels within stack <NUM>.

Top-level metallization M3 includes metallization structures <NUM> and metallization structures <NUM>, which in some embodiments are interspersed as shown between metallization structures <NUM>. In some embodiments, CDs of metallization structures <NUM> are greater than CDs of metallization structures <NUM>.

Lower IC die <NUM> is shown in an opposing orientation relative to IC die <NUM>. Lower IC die <NUM> comprises substrate <NUM>, device layer <NUM> in the top surface region of substrate <NUM>, and metallization stack <NUM>, shown over device layer <NUM>. Metallization stack <NUM> extends between bond interface <NUM> and device layer <NUM>. Device layer <NUM> comprises active devices, passive devices or a combination of active and passive devices. Metallization stack <NUM> comprises conductive layers <NUM>, <NUM> and <NUM>, labelled M'<NUM>, M'<NUM> and M'<NUM>, respectively, at progressively increasing distances within ILD <NUM>. In some embodiments, ILD <NUM> comprises substantially the same materials as ILD <NUM>. Conductive layers <NUM>, <NUM> and <NUM> extend parallel to substrate <NUM> within metallization stack <NUM>, at progressively increasing distances from device layer <NUM>. Metallization structures <NUM> (in M'<NUM>), <NUM> (in M'<NUM>), <NUM> and <NUM> (in M'<NUM>) increase in CD and pitch at progressively higher levels (e.g., increasing distance from device layer <NUM>) within metallization stack <NUM>. Metallization structures <NUM> and <NUM> have maximal CDs and feature pitch. In some embodiments, metallization structures <NUM> have a larger CD than metallization features <NUM>.

Upper IC die <NUM> and lower IC die <NUM> are bonded to one another at bond interface <NUM>. Top level metallization structures <NUM> of lower stack <NUM> oppose top level metallization structures <NUM> of upper stack <NUM>, sharing metallic diffusion bonds at bond interface <NUM>. Diffusion bonds may be characterized by metallic interdiffusion of metal atoms between adjacent pads. Similarly, inter-stack ILD bonds may be covalent bonds (e.g., Si-O-Si bonds) between ILDs <NUM> and <NUM> at bond interface <NUM>.

Metallization structures <NUM> and <NUM> may be employed as bonding structures for vertical integration of upper and lower dies <NUM> and <NUM>, respectively. ILD <NUM> may be directly bonded to ILD <NUM> at bond interface <NUM>. In some embodiments, both metallic bonds and dielectric bonds may be formed by hybrid bonding, as described below. The relatively larger feature sizes and pitch of top level metallization features may mitigate reduction in metal-to-metal bonding contact area resulting from die-to-die or wafer-to-wafer lateral offsets. Such offsets may result from positioning inaccuracies. An example of lateral offset between dies <NUM> and <NUM> is indicated in the inset of <FIG> by the distance x.

Top-level metallization M'<NUM> includes metallization structures <NUM> and metallization structures <NUM>, which in some embodiments may be interspersed, as shown, between metallization structures <NUM>. In some embodiments, CDs of metallization structures <NUM> are greater than CDs of metallization structures <NUM>. Similarly, CDs of metallization structures <NUM> may be greater than CDs of metallization structures <NUM>. Metallization structures <NUM> and <NUM> may be pads, either or both of which be employed as probe pads for electrical testing of IC dies <NUM> and <NUM>, respectively. As described further below, metallization structures <NUM> and/or <NUM> may, at some point in a manufacturing process, be employed as test pads upon which probes for testing the IC die are landed. Such probing may lead to surface damage in a metallization structure. In exemplary embodiments, to mitigate detrimental effects such surface damage might otherwise have on the bond between IC dies <NUM> and <NUM>, at least one of metallization structures <NUM> and <NUM> is recessed away from the plane of bonding interface <NUM>, leaving void <NUM> and/or void <NUM> between free surface <NUM> of metallization structures <NUM> and the bonding interface <NUM>. The amount of recess may be predetermined to accommodate any expected level of probe-induced pad topography. For example, the cumulative relief provided by void <NUM> and/or void <NUM> may exceed probe-induced topography by any suitable margin. With at least one of metallization structures <NUM> and <NUM> recessed, metallization structures <NUM> and <NUM> may not be directly bonded to each other (i.e., do not participate in the IC die bond).

In the exemplary embodiments illustrated by <FIG>, metallization structures <NUM> and metallization structures <NUM> are both recessed away from the plane of bonding interface <NUM>, leaving voids <NUM> and <NUM> between free surfaces <NUM>,<NUM> and bond interface <NUM>. Metallization structures <NUM> may oppose similarly deployed metallization structures <NUM> along bond interface <NUM>, as illustrated. In some embodiments, metallization structures <NUM> may also be employed as test pads for landing probes for testing lower IC die <NUM> before vertical integration with upper IC die <NUM>. In some embodiments of composite IC die structure <NUM> comprising hybrid bonded dies, a surface roughness of less than <NUM> may facilitate direct hybrid bonding. Such minimal surface roughness may be achieved by chemical mechanical polishing (CMP) of metallization stacks <NUM> and <NUM>. However, subsequent contact with test probes may damage test pads (e.g., respective metallization structures <NUM> and <NUM>), deforming free surfaces <NUM> and <NUM> into a highly non-planar surface topography, that may, for example, display an average surface roughness of one to two microns. While the non-planar topography of a probed test pad might interfere with subsequent hybrid bonding of IC die <NUM> to <NUM>, such damage to metallization structures <NUM> and <NUM> may be compensated, at least in part, by recessing the test pad structures relative to bonding interface <NUM>. In the illustrated example, both the free opposing metal surfaces (e.g., free surfaces <NUM> and <NUM>) of the structures are recessed back from bonding interface <NUM>, leaving voids <NUM> and <NUM> having average z-heights <NUM> to <NUM> microns to intervene between metallization structures <NUM> and <NUM>, respectively, and bond interface <NUM> (e.g. as described in <FIG>). In other embodiments, however, only one of two opposing metallization structures is recessed from a bonding interface between two IC die of a composite IC die structure. An example is shown in <FIG>.

<FIG> illustrates a magnified cross-sectional view in the x-z plane of the portion of composite IC die structure <NUM> delineated by the dashed box in <FIG>, according to some embodiments of the disclosure.

<FIG> illustrates structural details of recessed test pads (e.g., metallization structures <NUM> and <NUM>). The region of bonded metallization stacks <NUM> and <NUM> in the vicinity of test pads comprising opposing metallization structures <NUM> and <NUM> is delineated in <FIG>, and shown in magnified view. In the illustrated embodiment, upper test pad (e.g., metallization structure <NUM>) has not been damaged by contact with a test probe. Free surface <NUM> of the upper test pad (e.g., metallization structure <NUM>) is recessed back from bond interface <NUM> by a distance d1. In some embodiments, d1 is <NUM> to <NUM> microns. Free surface <NUM> is shown to be substantially flat, although in some embodiments a small degree of concavity or dishing may be present. Free surface <NUM> may exhibit an average surface roughness that is <NUM> or less. In contrast, free surface <NUM> of the lower test pad (e.g., metallization structure <NUM>) exhibits substantially greater surface roughness that may have resulted from pre-assembly probing of lower IC die <NUM>. In some embodiments, upper test pad (e.g., metallization <NUM> may also exhibit similar surface damage from test probe contact. Before or after probing, metallization structure <NUM> may have been recessed back from bond interface <NUM> by substantially the same recess depth (e.g., distance d1) of metallization structure <NUM>. Probing- induced damage may increase average surface roughness, indicated by distance d2 between free surface <NUM> to bond interface <NUM>, for example, to <NUM> micron, or greater. Distances d3 and d4 represent minimum and maximum topography, respectively, of free surface <NUM>, as measurable distances from bond interface <NUM>.

In some embodiments, the CD of metallization structures <NUM> and <NUM> is greater than that of metallization structures <NUM> and <NUM>. CDs of metallization structures <NUM> and <NUM>, represented by feature width w1, are greater than CDs of metallization structures <NUM> and <NUM> represented by width w2 (e.g., w1 > w2). Any alignment inaccuracy between metallization structures on both sides of bond interface <NUM> is indicated by offset x.

<FIG> illustrates a magnified cross-sectional view in the x-z plane of the portion of composite IC die structure <NUM> delineated by the dashed box in <FIG>, showing recess only of test pads <NUM>, not forming part of the invention as claimed.

<FIG> illustrates structural details of composite IC die structure <NUM> having recessed test pads only in one of the two dies. In the illustrated example, the upper test pads (e.g., metallization structures <NUM>) in upper die <NUM> are not recessed. Free surface <NUM> of metallization is flush with bond interface <NUM>. Lower test pads <NUM> in lower die <NUM> exhibit damage topography resulting from probe contact, as described above. During processing, lower test pads may have been recessed below bond interface <NUM> to a depth similar to d1 in <FIG>. Recess depth may have been predetermined by prior knowledge of maximal topography heights, for example, height d4, not rising above distance d5, the full depth of metallization structures <NUM>.

<FIG> illustrates a cross-sectional view in the x-z plane of composite die structure <NUM>, according to some embodiments of the disclosure.

Composite die structure <NUM> comprises upper IC die <NUM> vertically integrated with lower IC die <NUM>. Upper and lower dies <NUM> and <NUM> are bonded together at bonding interface <NUM>. Upper IC die <NUM> comprises substrate <NUM>, device layer <NUM> and metallization stack <NUM>. Upper IC die <NUM> is shown in an inverted orientation relative to IC die <NUM>. Lower IC die <NUM> is substantially as shown in <FIG>. The structure of upper metallization stack <NUM> is substantially the same as upper metallization stack <NUM> in <FIG>, with the exception of the absence of test pad metallization (e.g., metallization structures <NUM>), leaving recessed regions of dielectric <NUM> at bond interface <NUM>. In the illustrated embodiment, test pads may have been recessed back substantially to ILD <NUM>, leaving void <NUM> over metallization structure <NUM> in lower metallization stack <NUM>.

<FIG> illustrates a magnified cross-sectional view in the x-z plane of the portion of composite die structure <NUM> delineated by the dashed box in <FIG>, according to some embodiments of the disclosure.

<FIG> illustrates structural details of the region delineated in <FIG> in the vicinity of the lower test pad (metallization structure <NUM>). Void <NUM> may be a trench or other recessed structure in dielectric <NUM> of upper metallization stack <NUM>, for example, etched in ILD <NUM> during damascene build-up of metallization stack <NUM>. Void <NUM> may result from a complete removal of the test pad (e.g., metallization structure <NUM>) formed previously within the recess, exposing void sidewalls <NUM> and bottom wall <NUM>. Void <NUM> has a z-height d5 extending from bond interface <NUM> to void bottom wall <NUM>. Z-height d5 may be between <NUM> and <NUM> microns.

The lower test pad example (e.g., metallization structure <NUM>) is substantially the same as described in <FIG>, with the exception of exhibiting larger-scale deformation topography. Metallization structure <NUM> may be significantly damaged by prior interaction with a test probe. In an exemplary illustration, bumps <NUM>, formed by deformation of free surface <NUM>, may extend a significant distance (e.g., a large fraction of depth d5) into void <NUM>. For example, bump <NUM> extends into void <NUM> by a distance d6 of several microns above bond interface <NUM>, a significant portion of the recess depth d5 of void <NUM>. Enough clearance for large-scale topography of a heavily damaged test pad may be afforded by extending depth d5 by the full z-height of the test pad (e.g., metallization structure <NUM>). In some embodiments, d5 may be <NUM> to <NUM> microns.

<FIG> illustrates a cross-sectional view in the x-z plane of composite die structure <NUM>, not forming part of the invention as claimed.

Composite die structure <NUM> comprises upper IC die <NUM> vertically integrated with lower IC die <NUM>. Upper and lower dies <NUM> and <NUM> are directly bonded together at bonding interface <NUM>. Upper IC die <NUM> comprises substrate <NUM>, device layer <NUM> and metallization stack <NUM>. Although the structure of upper metallization stack <NUM> is substantially the same as upper metallization stacks <NUM> in <FIG> and <NUM> in <FIG>, in some embodiments, conductive layer <NUM> comprises only upper bonding pads (e.g., metallization structures <NUM>). In some embodiments, at least some of the upper test pads (e.g., metallization structures <NUM>, see <FIG>) are omitted at locations along bond interface <NUM> where lower test pads (e.g., metallization structures <NUM>) are present. Level M3 of metallization stack <NUM> comprises metallization structures <NUM>. In metallization stack <NUM>, ILD <NUM> replaces test pads (e.g., metallization structures <NUM>, see <FIG>) at the locations along bonding interface <NUM> described embodiments shown in <FIG> and <FIG>.

<FIG> illustrates a magnified cross-sectional view in the x-z plane of the portion of composite die structure <NUM> delineated by the dashed box in <FIG>.

<FIG> illustrates structural details of the region delineated in <FIG> in the vicinity of the lower test pad (metallization structure <NUM>). Damage topography of metallization structure <NUM> may not surpass maximal z-height d4, and entirely confined within void <NUM> below bond interface <NUM>. Z-height d2 of bump <NUM> may be <NUM> to <NUM> microns above average recess depth d6 of metallization structure <NUM>.

Void <NUM> is sealed above bond interface <NUM> by dielectric <NUM>. Average recess depth d6 below bond interface <NUM> of metallization structure <NUM> may be <NUM> to <NUM> microns. Feature depth d5 may be adjusted to allow for a target feature z-height d3 of the test pad (e.g., metallization structure <NUM>) and any predetermined level oftopography that may be induced through a potential electrical test probing.

<FIG> illustrates process flow chart <NUM> summarizing an exemplary method for making composite die structure <NUM>, where test pads are recessed by a wet chemical etch, according to some embodiments of the disclosure.

At operation <NUM>, one or more die wafers are received from a back-end-of-line (BEOL) metallization stack (e.g., metallization stack <NUM>) build-up process, where BEOL metallization is completed. The wafers may comprise multiple dies having common BEOL metallization. BEOL metallization top level interconnects comprise test pads (e.g., metallization structures <NUM>, <NUM>) and bonding pads (e.g., metallization structures <NUM>, <NUM>). CDs of test pads may be larger than CDs of bonding pads.

At operation <NUM>, the BEOL stack is prepared for a through-mask metal etch to recess selected test pads below the top surface of the ILD. In some embodiments, an etch mask comprising a photoresist is deposited over the top of the BEOL stack on the wafer. The photoresist may be deposited by spin or spray coating. The photoresist layer may have a thickness of <NUM> to <NUM> microns. A positive or negative tone photoresist mask may be employed as the etch mask.

At operation <NUM>, the photoresist etch mask is patterned to form openings over the test pads. After through-mask exposure of the photoresist in a mask aligner, the photoresist layer is treated in a developer bath to form openings over selected test pads. A bake step may follow to harden the photoresist layer.

At operation <NUM>, the wafer is subjected to any metal etch process suitable for the metal composition. In some examples, a wet chemical bath may be employed to etch back selected test pads. An etch bath, for example, comprising potassium iodide and iodine, or ferric chloride, for dissolving copper, or other suitable oxidizing etch chemistry for copper and/or other metals, may be employed. Test pads may be recessed back by <NUM> to <NUM> microns.

At operation <NUM>, the photoresist mask is removed. The wafer may be further processed by deionized water rinse and dry. At operation <NUM>, the wafer is electrically tested. Recessed test pads may be contacted by tester probes, where the probe contact may damage the test pads, for example as described above.

At operation <NUM>, the wafer may be singulated to liberate dies after testing. IC dies with poor electrical testing performance may be rejected. Functional dies from the same wafer may be vertically integrated, for example where they are stacked and directly bonded together. Bonding pads and test pads from opposing die pairs may be interfaced, for example by a pick and place tool. A small degree of alignment error may occur due to tool inaccuracy, resulting in a degree of centering offset (e.g., offset x) between opposing pads that may be significantly larger than misregistration between two adjacent levels of damascene metallization, for example as shown in <FIG>. Alternatively, a second wafer that has undergone similar processing is introduced for vertical integration of dies from the second wafer on dies of the first wafer.

Dies on opposing wafers may be interfaced at wafer level by wafer-to-wafer alignment. The second wafer is interfaced to the first wafer such that the bonding pads (e.g., metallization structures <NUM>/<NUM>) and test pads (metallization structures <NUM>/<NUM>) are interfaced. Some alignment offset between opposing structures may be present. Stacked singulated or unsingulated dies may be hybrid bonded by clamping together and/or thermally treating the stacked dies.

<FIG> illustrate a series of cross-sectional views in the x-z plane of an exemplary method for making composite die structure <NUM>, according to some embodiments of the disclosure.

In <FIG>, a wafer comprising multiple unsingulated dies <NUM> (or <NUM>) is received after back-end-of-the-line (BEOL) processing. A single IC die <NUM> is shown to represent the wafer carrying the unsingulated dies. In some embodiments, the wafer may carry a single type of die, following design rules shown for IC die <NUM> in <FIG>. In some embodiments, the wafer may comprise two or more subsets of dies. Individual die subsets may follow specific design rules unique to that die subset. For example, a wafer may carry a die subset exemplified by upper IC die <NUM> shown in <FIG>, and/or a subset exemplified by upper IC die <NUM>, shown in <FIG>.

In alternative embodiments, multiple wafers may be received, where individual wafers carry single sets of identical dies, for example, dies <NUM>, <NUM> or <NUM>. Metallization stack <NUM> is built up to top-level metallization, for example, metallization level M3, comprising metallization features <NUM> (e.g., test pads) and <NUM> (e.g., bonding pads). Test pads and bonding pads are separated by ILD <NUM>. Metallization features <NUM> may have a larger width than metallization features <NUM>, for example of up to <NUM> microns and <NUM> microns, respectively. , The larger CD of test pads (e.g., metallization structures <NUM>) to accommodate contact with a relatively large diameter test probe tip. Bonding pads (metallization features <NUM>) may, for example, have widths (or diameters) of up to <NUM> microns.

In some embodiments, metallization stack <NUM> may have undergone a planarization process by, for example, chemical mechanical polishing (CMP). The planarization operation may reduce surface roughness of the top surface of metallization stack <NUM> comprising ILD <NUM> and metallization structures <NUM> and <NUM>, in preparation for hybrid bonding. For example, surface roughness of top level metallization stack structures, including metallization structures <NUM> and <NUM>, may be <NUM> or less.

In <FIG>, the wafer is prepared for a through-mask wet metal etch to recess test pads (e.g., metallization structures <NUM>). A photoresist layer <NUM> is deposited over the top of BEOL stack <NUM>, covering metallization structures <NUM> and <NUM> and ILD <NUM>. In some embodiments, the etch mask is a photoresist layer. The photoresist layer may be deposited by spin coating or spray coating, forming a layer of photoresist of up to <NUM> microns, for example. To withstand an oxidative and/or acidic etch bath, a polymeric photoresist comprising, for example, Novolak, acrylic or epoxy (e.g., SU8) resins may be employed. The photoresist material may be positive tone or negative tone resist materials. Thermal cross-linking of photoresist layer <NUM> may be necessary to stabilize the photoresist mask against chemical attack in a highly acidic/oxidizing environment.

In <FIG>, the photoresist layer <NUM> is patterned to reveal metallization structures <NUM> (e.g., test pads). Openings <NUM> are formed over metallization structures <NUM> by through-mask light exposure (for example, in a mask alignment tool), and subsequent treatment in an appropriate developer bath. Development of features (e.g., openings <NUM>) in photoresist layer <NUM> may be followed by a hard bake to harden the photoresist by further thermal cross-linking.

IC die <NUM> is subsequently treated in an etch bath at wafer level to recess exposed test pads (e.g., metallization features <NUM>). Test pads may comprise metals such as, but not limited to, copper, gold, silver, nickel or aluminum. The etch bath may comprise oxidizing acids, iodine and iodide couples, ferric chloride, acidic hydrogen peroxide, etc., capable of attacking the above-noted metals. Etching may be conducted at room temperature. Metallization structures <NUM> may be partially recessed back a distance d1 below the surface of ILD <NUM>, where d1 may be <NUM> to <NUM> microns. The electrochemical etch of the test pad may further smooth or slightly increase the surface roughness of the test pad relative to the CMP surface finish.

Subsequent to the etch process, the photoresist mask is removed in a suitable stripping bath. IC die <NUM> may be further cleaned in one or more DI water rinse/dry cycles.

In <FIG>, IC die <NUM> is prepared for back-end testing. IC die <NUM> may be tested for functionality at wafer level or first singulated as individual dies, then probed at die level. IC die <NUM> may be placed on a probing tool, where a probe tip or card having multiple probe tips is lowered onto IC die <NUM>. As illustrated in <FIG>, probe tip <NUM> is lowered, as indicated by the downward pointing arrow, over a recessed test pad (metallization structure <NUM>). Metallization structures <NUM> may have a CD (e.g., diameter) to accommodate the radius of probe tip <NUM>.

In <FIG>, probe tip <NUM> is shown to be in contact with a test pad (metallization structure <NUM>), causing damage to the test pad by mechanical disruption of the surface finish of the test pad. The pre-contact surface finish may have very small topography, having a surface roughness of <NUM> (measured in surface height variations) or less. Damage may be in the form of increased surface topography, where surface roughness may be increased to <NUM> to <NUM> microns, indicated by the formation of large-scale surface roughness bumps <NUM>. Z-heights are not indicated in the figure, and details of relative z-heights are referred to <FIG>. Probe <NUM> is moved between multiple test pads, as indicated.

In <FIG>, IC die <NUM> is prepared for vertical integration with a second IC die <NUM>. IC die <NUM> may be identical to IC die <NUM>. In some embodiments, IC die <NUM> may differ from IC die <NUM>. Dies <NUM> and <NUM> are mated, where metallization structures <NUM> on IC die <NUM> are interfaced and contacted to metallization structures <NUM> on IC die <NUM>. Recessed metallization structures <NUM> in IC die <NUM> are opposed to recessed metallization structures <NUM> on IC die <NUM>, but not in direct contact with each other. Although, IC die <NUM> test pads (e.g., metallization structures <NUM>) do not exhibit surface damage as large-scale surface roughness in the illustrated embodiment as do IC die <NUM> test pads (metallization structures <NUM>), metallization structures <NUM> may exhibit similar large scale surface roughness. The arrows in the figure indicate that opposing dies <NUM> and <NUM> are aligned and contacted. In some embodiments, dies <NUM> and <NUM> are interfaced at wafer level using lithographic alignment (e.g., in a pattern alignment tool). In some embodiments, singulated dies <NUM> and <NUM> are interfaced using a pick-and-place tool.

In <FIG>, mated dies <NUM> and <NUM> are bonded to form composite die structure <NUM>. In some embodiments, dies <NUM> and <NUM> are bonded by hybrid bonding. Hybrid bonding is a direct bonding of mated materials, where need for intermediate bonding materials such as solder and adhesives is obviated. Metal-to-metal bonds are formed across bond interface <NUM> between mated metal structures. Covalent bonds are formed between mated dielectric materials across the same bond interface <NUM>. Hybrid bonding may enable bonding of metallization structures having CD under <NUM> microns, including CDs under <NUM> micron. Errors in alignment of metallization structures <NUM> and <NUM> may be observable about the bond interface <NUM>, as shown in the figure by offset x.

<FIG> illustrates process flow chart <NUM> summarizing an alternative exemplary method for making composite die structure <NUM>, where test pads are recessed by CMP, according to some embodiments of the disclosure.

At operation <NUM>, the BEOL stack is subject to chemical mechanical planarization (CMP) to recess test pads (e.g., metallization structures <NUM> or <NUM>). CMP may cause dishing of exposed metallization structures, where the surfaces of the metallization structures are eroded by mechanical abrasion, causing recessing away from the ILD surface. A degree of concavity may be introduced to the recessed surface, referred to as dishing. Larger structures often display greater dishing than smaller structures. Test pads may have a significant size differential with bonding pads (e.g., metallization structures <NUM>) so that CMP-induced dishing of top-level interconnects may be sufficient to selectively recess pads that may be electrically probed (and thus become damaged) to such an extent that a further probe pad mask and pad recess etch is not needed.

At operation <NUM>, the wafers are placed in a test jig for back-end testing. Recessed test pads may be contacted by probes, where the probe contact may damage the test pads as described above.

At operation <NUM>, the processed wafers may be singulated to liberate the good dies after testing. Dies may be singulated before testing. Defective dies may be rejected. Functional dies from the same wafer may be vertically integrated, where functional dies are stacked together by a pick and place operation. Bonding pads and test pads from opposing die pairs are interfaced by a pick and place tool. A small degree of alignment error may occur due to tool inaccuracy, resulting in a degree of centering offset (e.g., offset x) between opposing pads, as shown in <FIG>. Alternatively, a second wafer that has undergone similar processing is introduced for vertical integration of dies from the second wafer on dies of the first wafer.

Dies on opposing wafers may be interfaced at wafer level by wafer-to-wafer alignment. The second wafer is interfaced to the first wafer such that the bonding pads (e.g., metallization structures <NUM>/<NUM>) and test pads (metallization structures <NUM>/<NUM>) are interfaced. Some alignment offset between opposing structures may be present. Stacked singulated or unsingulated dies may be hybrid bonded by subjecting the stacked dies to thermal treatment.

In <FIG>, a wafer comprising multiple unsingulated dies <NUM> is received after back-end-of-the-line (BEOL) processing. A single IC die <NUM> (or <NUM>) is shown to represent the wafer carrying the unsingulated dies. In some embodiments, the wafer may carry a single type of die, following design rules shown for IC die <NUM> in <FIG>. In some embodiments, the wafer may comprise two or more subsets of dies. Individual die subsets may follow specific design rules unique to that die subset. For example, a wafer may carry a die subset exemplified by upper IC die <NUM> shown in <FIG>, and/or a subset exemplified by upper IC die <NUM>, shown in <FIG>.

In alternative embodiments, multiple wafers may be received, where individual wafers carry single sets of identical dies, for example, dies <NUM>, <NUM> or <NUM>. Metallization stack <NUM> is built up to top-level metallization, for example, metallization level M3, comprising metallization features <NUM> (e.g., test pads) and <NUM> (e.g., bonding pads). Test pads and bonding pads are separated by ILD <NUM>. Metallization features <NUM> may have a larger width (e.g., up to <NUM> microns) than metallization features <NUM> of up to <NUM> microns to accommodate contact with a relatively large diameter test probe tip. Bonding pads (metallization features <NUM>) may have widths (or diameters) of up to <NUM> microns.

In some embodiments, metallization stack <NUM> may have undergone a planarization process by, for example, chemical mechanical polishing (CMP). The planarization operation may reduce surface roughness of the top surface of metallization stack <NUM>, comprising ILD <NUM> and metallization structures <NUM> and <NUM>, in preparation for hybrid bonding. For example, surface roughness of top level metallization stack structures, including metallization structures <NUM> and <NUM>, may be less than <NUM>.

In <FIG>, IC die <NUM> is subject to a CMP planarization operation to recess test pads (metallization structures <NUM>). CMP-induced recessing (e.g., dishing) of metal interconnect features increases as feature CD increases. Design rules may require a significantly larger CD for test pads (e.g., metallization structures <NUM>) than for bond pads (e.g., metallization structures <NUM>) to enhance CMP-induced recessing of metallization structures <NUM>. Free surface <NUM> of dished metallization structures <NUM> may exhibit a degree of concavity, as shown in the figure. The amount of recess may be characterized by setback d1, which may depend on any combination of the type of chemical agent used for chemical polishing, the abrasive medium, and length of time of the CMP processing.

In <FIG>, IC die <NUM> has been subjected to back-end testing probing as shown in <FIG>, having caused large-scale topology bumps <NUM> of metallization structures <NUM>. IC die <NUM>, is prepared for vertical integration with IC die <NUM>. As noted above, IC die <NUM> may be identical to IC die <NUM>, or may be substantially different from IC die <NUM>. Dies <NUM> and <NUM> may be singulated. IC die <NUM> may be mated to IC die <NUM> by a pick-and-place tool, which may align metallization structures <NUM> and <NUM> to metallization structures <NUM> and <NUM> before contacting IC die <NUM> to IC die <NUM>.

Alternatively, dies <NUM> and <NUM> may be aligned and mated at wafer level after back-end testing. A lithographic tool, for example, a mask aligner, may be employed to align unsingulated dies <NUM> and <NUM>.

In <FIG>, mated dies <NUM> and <NUM> are bonded to form composite die structure <NUM>. In some embodiments, dies <NUM> and <NUM> are bonded by hybrid bonding.

<FIG> illustrates process flow chart <NUM> summarizing an exemplary method for making composite die structure <NUM>, according to some embodiments of the disclosure.

At operation <NUM>, first and second die wafers are received from a back-end-of-line (BEOL) metallization stack build-up process, where BEOL metallization is completed. The first and second wafers may each comprise multiple dies (e.g., dies <NUM> and/or <NUM>). In some embodiments, the first and second wafers may be identical wafers. First and second wafers are distinguished from each other for separate downstream processing.

At operation <NUM>, the BEOL stacks of both first and second wafers are prepared for a through-mask metal etch to recess selected test pads below the top surface of the ILD. In some embodiments, an etch mask comprising a photoresist is deposited over the top of the BEOL stack on the wafer. The photoresist may be deposited by spin or spray coating. The photoresist layer may have a thickness of <NUM>. A positive or negative tone photoresist mask may be employed as the etch mask.

At operation <NUM>, the photoresist etch mask is patterned to form openings over the test pads. After through-mask exposure of the photoresist in a photolithographic exposure tool, the photoresist layer is treated in a developer bath to form openings over selected test pads. A bake step may follow to harden the photoresist layer.

At operation <NUM>, the first and second wafers are subject to a separate metal wet etches to attack selected test pads to differing degrees. As described above, a copper etch bath, for example, a bath comprising potassium iodide and iodine for dissolving copper, or other suitable oxidizing etch chemistry for copper and/or other metals, may be employed. Test pads on the first wafer may be completely removed to expose underlying ILD, for example, to produce dies <NUM>. Test pads on the second wafer may be partially etched back as described in the process flow in <FIG>, for example, to produce dies <NUM>.

At operation <NUM>, the photoresist mask is removed by dissolution in a remover bath. The wafer may be further processed by deionized water rinse and dry. Dies <NUM> and <NUM> on first and second wafers may be tested for functionality by test probe contact with selected test pads on the second wafer, as shown in <FIG>.

At operation <NUM>, the wafer may be singulated to liberate dies after testing. Defective dies are rejected. Functional dies from the first and second wafers may be vertically integrated with each other, where functional dies from the first wafer (e.g., dies <NUM>) are stacked over dies from the second wafer (e.g., dies <NUM>) by a pick and place operation. Bonding pads and test pads from opposing die pairs are interfaced by a pick and place tool. A small degree of alignment error may occur due to tool inaccuracy, resulting in a degree of centering offset (e.g., offset x) between opposing pads, as shown in <FIG>. Following alignment, mated dies may be hybrid bonded. Offset x may not be constant over the length over die <NUM> or the length of the wafer.

Alternatively, dies <NUM> and <NUM> on first and second wafers, respectively, may be interfaced at wafer level by wafer-to-wafer alignment. The second wafer is interfaced to the first wafer such that the bonding pads (e.g., metallization structures <NUM>/<NUM>) are interfaced. Due to some recessing, bonding pads may not touch initially. Some alignment offset between opposing structures may be present. Wafer-level hybrid bonding may follow alignment.

In <FIG>, IC die <NUM> from a first wafer is prepared for a through-mask wet metal etch to deeply recess test pads (e.g., metallization structures <NUM>), or completely remove them. A photoresist layer <NUM> is deposited over the top of BEOL stack <NUM>, covering metallization structures <NUM> and <NUM> and ILD <NUM>. In some embodiments, the etch mask is a photoresist layer. Photoresist layer <NUM> is patterned to reveal metallization structures <NUM> (e.g., test pads). Openings <NUM> are formed over metallization structures <NUM>.

In <FIG>, IC die <NUM> is subsequently treated in an etch bath at wafer level to recess exposed test pads (e.g., metallization features <NUM>). Metallization structures <NUM> may be completely etched to underlying ILD <NUM>, leaving void <NUM>. Alternatively, metallization structures <NUM> may be etched to a very small thickness relative to depth d5 of void <NUM>, where d5 may up to <NUM> microns. The electrochemical etch of the test pad may further smooth or slightly increase the surface roughness of the test pad relative to the CMP surface finish.

Subsequent to the etch process, the photoresist layer <NUM> is removed in a suitable stripping bath, as shown in <FIG>. IC die <NUM> may be further cleaned in one or more DI water rinse/dry cycles.

In <FIG>, IC die <NUM> is mated to IC die <NUM> from a second wafer. IC die <NUM> may be fabricated in the process illustrated in <FIG>. Metallization structures <NUM> on IC die <NUM> are shown with large scale topography due to probe damage (illustrated in <FIG>). Damaged metallization structures <NUM> are opposed to voids <NUM>.

<FIG> illustrates a cross-sectional view in the x-z plane of composite die structure <NUM> bonded to external substrate <NUM>, according to some embodiments of the disclosure.

Composite die structure <NUM> comprises upper IC die <NUM> sharing bond interface <NUM> with lower IC die <NUM>. Lower IC die <NUM> comprises metallization stack <NUM> on frontside of substrate <NUM>, having direct interconnection to device layer <NUM>. Metallization stack <NUM> is on the backside of substrate <NUM>. Through-silicon vias (TSVs) <NUM> extend through substrate <NUM> to interconnect transistors in device layer <NUM> to inner-most metallization structures <NUM> (e.g., at level M"<NUM>) within metallization stack <NUM>. Interconnect structures <NUM> are joined to pads <NUM> on external substrate <NUM> by solder joints <NUM>. In some embodiments, external substrate <NUM> is a package substrate. In some embodiments, external substrate <NUM> is an interposer substrate. In some embodiments, external substrate <NUM> is a printed circuit board.

External substrate <NUM> may comprise power routing <NUM> and <NUM> and signal routing <NUM> coupled to device layer <NUM> through inter-level vias (not shown) in metallization stack <NUM>. Power and data signals may be routed to device layer <NUM> of upper IC die <NUM> though vertical interconnects (e.g., interlayer vias, not shown) in bonded metallization stacks <NUM> and <NUM>.

<FIG> illustrates a block diagram of computing device <NUM> as part of a system-on-chip (SoC) package comprising a composite die (e.g., any of composite die structure <NUM>, <NUM>, <NUM> or <NUM> disclosed herein) in an implementation of a computing device, according to some embodiments of the disclosure.

According to some embodiments, computing device <NUM> represents a server, a desktop workstation, or a mobile workstation, such as, but not limited to, a laptop computer, a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. An IC package, such as, but not limited to, a single- or multi-core microprocessor (e.g., representing a central processing unit. In some embodiments, the IC package comprises a composite die structure (e.g., any of composite die structures <NUM>, <NUM>, <NUM> or <NUM>), according to the embodiments of the disclosure.

In some embodiments, computing device has wireless connectivity (e.g., Bluetooth, WiFi and <NUM> network). It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device <NUM>.

The various embodiments of the present disclosure may also comprise a network interface within <NUM> such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. The wireless interface includes a millimeter wave generator and antenna array.

According to some embodiments, processor <NUM> represents a CPU or a GPU, and can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor <NUM> include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device <NUM> to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device <NUM> includes audio subsystem <NUM>, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device <NUM>, or connected to the computing device <NUM>. In one embodiment, a user interacts with the computing device <NUM> by providing audio commands that are received and processed by processor <NUM>.

Display subsystem <NUM> represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device <NUM>. Display subsystem <NUM> includes display interface <NUM> which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface <NUM> includes logic separate from processor <NUM> to perform at least some processing related to the display. In one embodiment, display subsystem <NUM> includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller <NUM> represents hardware devices and software components related to interaction with a user. I/O controller <NUM> is operable to manage hardware that is part of audio subsystem <NUM> and/or display subsystem <NUM>. Additionally, I/O controller <NUM> illustrates a connection point for additional devices that connect to computing device <NUM> through which a user might interact with the system. For example, devices that can be attached to the computing device <NUM> might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller <NUM> can interact with audio subsystem <NUM> and/or display subsystem <NUM>. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device <NUM>. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem <NUM> includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller <NUM>. There can also be additional buttons or switches on the computing device <NUM> to provide I/O functions managed by I/O controller <NUM>.

In one embodiment, I/O controller <NUM> manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device <NUM>. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In one embodiment, computing device <NUM> includes power management <NUM> that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem <NUM> includes memory devices for storing information in computing device <NUM>. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem <NUM> can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device <NUM>.

Elements of embodiments are also provided as a machine-readable medium (e.g., memory <NUM>) for storing the computer-executable instructions. The machine-readable medium (e.g., memory <NUM>) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

Connectivity via network interface <NUM> includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device <NUM> to communicate with external devices. The computing device <NUM> could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Network interface <NUM> can include multiple different types of connectivity. To generalize, the computing device <NUM> is illustrated with cellular connectivity <NUM> and wireless connectivity <NUM>. Cellular connectivity <NUM> refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) <NUM> refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

Peripheral connections <NUM> include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device <NUM> could both be a peripheral device ("to" <NUM>) to other computing devices, as well as have peripheral devices ("from" <NUM>) connected to it. The computing device <NUM> commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device <NUM>. Additionally, a docking connector can allow computing device <NUM> to connect to certain peripherals that allow the computing device <NUM> to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, the computing device <NUM> can make peripheral connections <NUM> via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

Claim 1:
An Integrated Circuit, IC, device, comprising:
a first component (<NUM>) comprising a first dielectric (<NUM>) and a plurality of adjacent first interconnect structures (<NUM>, <NUM>) within the first dielectric;
a second component (<NUM>) comprising a second dielectric (<NUM>) and a plurality of adjacent second interconnect structures (<NUM>, <NUM>) within the second dielectric, wherein a first (<NUM>) of the second interconnect structures is in direct contact with a first (<NUM>) of the first interconnect structures at a bond interface (<NUM>) between the first and second components;
wherein a second (<NUM>) of the first interconnect structures is set back a first distance, d1, from a plane of the bond interface; and
wherein a second (<NUM>) of the second interconnect structures is set back a second distance from the plane of the bond interface.