Patent Description:
This application relates to the field of semiconductor technologies, and in particular, to a wafer carrier for metal organic chemical vapor deposition.

Metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD) devices are widely used in light emitting diode (Light Emitting Diode, LED) epitaxy (Epitaxy) and device epitaxy. An MOCVD device includes a wafer carrier (Wafer Carrier), and a plurality of wafer sub-carriers are distributed on the wafer carrier. The wafer sub-carrier is configured to place the epitaxial wafer substrate. An LED epitaxial growth process using MOCVD usually includes the following steps: An epitaxial wafer substrate is placed on a wafer sub-carrier. The substrate and the wafer sub-carrier are heated to <NUM> to <NUM> by a resistance wire or radio frequency. An organic source is brought into a reaction chamber through carrier gases H<NUM>, N<NUM>, and the like, and grows on the epitaxial wafer substrate to form a thin film. As technologies advance, a size of the epitaxial wafer substrate becomes larger (<NUM> inches, <NUM> inches, and <NUM> inches), increasing stress and warpage of an epitaxial wafer. As the stress and warpage of the epitaxial wafer increase, crystal quality of a flat edge and a border of the epitaxial wafer is greatly affected.

<CIT> discloses a graphite bearing plate for processing LED epitaxial wafer. <CIT> discloses a tray, MOCVD reaction chamber and MOCVD device. <CIT> discloses a graphite bearing tray capable of regulating and controlling local temperature field. <CIT> relates to a susceptor for a reactor for epitaxial growth.

Embodiments of this application provide a wafer carrier for metal organic chemical vapor deposition, to improve crystal quality of a flat edge or a border of an epitaxial wafer. Embodiments not falling within the scope of the claims are for illustration only.

According to a first aspect, an embodiment of this application provides a wafer carrier for metal organic chemical vapor deposition, including at least one wafer sub-carrier that is in a groove structure and that is configured to place an epitaxial wafer substrate. A thermal conductivity of a side wall (<NUM>) of the wafer sub-carrier is higher than a thermal conductivity of a bottom wall (<NUM>) of the wafer sub-carrier.

A first space in the wafer sub-carrier is filled with a first thermally conductive material. The first space is a space between a flat edge of the epitaxial wafer substrate and a side wall of the wafer sub-carrier when the epitaxial wafer substrate is placed on the wafer sub-carrier. A thermal conductivity of the first thermally conductive material is not lower than a thermal conductivity of the wafer sub-carrier.

With reference to the first aspect, in a first possible implementation of the first aspect, a height of the first thermally conductive material filled in the first space is not higher than a height of the side wall of the wafer sub-carrier.

In this implementation, a risk of the first thermally conductive material being thrown off due to rotation of the wafer carrier and rotation of the wafer sub-carrier can be avoided.

With reference to the first aspect, in a second possible implementation of the first aspect, a material of the wafer sub-carrier is graphite, and the first thermally caonductive material is any one or a combination of at least two of the following:
graphite, silicon carbide, graphene, titanium metal, and tungsten metal.

In this implementation, the first thermally conductive material is selected for the material of the wafer sub-carrier, so that a thermal radiation heating effect at a position of the flat edge of the epitaxial wafer substrate can be improved, and crystal quality of a flat edge of the epitaxial wafer is improved, thereby improving an overall yield of the epitaxial wafer.

With reference to the second possible implementation of the first aspect, in a third possible implementation of the first aspect, a surface of the wafer sub-carrier is coated with silicon carbide, and a surface of the first thermally conductive material filled in the first space is coated with silicon carbide.

In this implementation, strength and hardness of the surface of the wafer sub-carrier and the surface of the first thermally conductive material filled in the first space can be increased, and gas corrosion can be mitigated.

In this implementation, a thermal radiation heating effect at a position of a border of the epitaxial wafer substrate can be improved, and a temperature at the position of the border of the epitaxial wafer substrate is compensated for, so that generation of defects such as black spots, blurred edges, and cracks on a border of an epitaxial wafer is avoided, and crystal quality of a border of the epitaxial wafer is improved, thereby improving an overall yield of the epitaxial wafer.

With reference to the fourth possible implementation of the first aspect, in a fifth possible implementation of the first aspect, a material of the bottom wall of the wafer sub-carrier is graphite, and a material of the side wall of the wafer sub-carrier is graphene.

In this implementation, the first thermally conductive material is selected for the material of the bottom wall of the wafer sub-carrier, so that a thermal radiation heating effect at a position of the flat edge of the epitaxial wafer substrate can be improved, and crystal quality of a flat edge of an epitaxial wafer is improved, thereby improving an overall yield of the epitaxial wafer.

With reference to the fourth possible implementation of the first aspect, in a sixth possible implementation of the first aspect, the side wall of the wafer sub-carrier includes a first layer and a second layer, and a thermal conductivity of the second layer is higher than the thermal conductivity of the bottom wall of the wafer sub-carrier.

In this implementation, the side wall of the wafer sub-carrier includes a high thermal conductivity layer whose thermal conductivity is higher than the thermal conductivity of the bottom wall of the wafer sub-carrier, so that a thermal radiation heating effect at a position of a border of the epitaxial wafer substrate can be improved, and a temperature at the position of the border of the epitaxial wafer substrate can be compensated for.

With reference to the sixth possible implementation of the first aspect, in a seventh possible implementation of the first aspect, the second layer includes a second thermally conductive material attached to an inner periphery of the first layer, and a thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the bottom wall of the wafer sub-carrier.

In this implementation, the second thermally conductive material is attached to the inner periphery of the first layer, to form the second layer. A process flow is simple and easy to operate. In addition, the existing wafer sub-carrier can be modified to obtain a wafer sub-carrier capable of compensating for the temperature at the position of the border of the epitaxial wafer substrate.

With reference to the sixth possible implementation of the first aspect, in an eighth possible implementation of the first aspect, a material of the second layer is graphene, a material of the first layer is graphite, and a material of the bottom wall of the wafer sub-carrier is graphite.

In this implementation, the material of the second layer is selected for the material of the bottom wall of the wafer sub-carrier and the material of the first layer of the side wall, so that a thermal radiation heating effect at a position of a border of the epitaxial wafer substrate can be improved, and crystal quality of a border of an epitaxial wafer is improved, thereby improving an overall yield of the epitaxial wafer.

With reference to the first aspect, in a ninth possible implementation of the first aspect, the wafer carrier is a graphite carrier, and the wafer sub-carrier is a groove on the graphite carrier.

In this implementation, filling of the first thermally conductive material becomes easier, production efficiency is improved, and a process flow is simple.

With reference to the first aspect, in a tenth possible implementation of the first aspect, the wafer carrier is a large graphite carrier, and the wafer sub-carrier is a small graphite carrier disposed on the large graphite carrier.

With reference to the first aspect, in an eleventh possible implementation of the first aspect, a diameter of the epitaxial wafer is greater than or equal to <NUM> inches.

In this implementation, an overall yield of a large-sized epitaxial wafer can be improved.

According to a second aspect, a wafer carrier for metal organic chemical vapor deposition is provided, including at least one wafer sub-carrier that is in a groove structure and that is configured to place an epitaxial wafer substrate. The wafer sub-carrier has a side wall whose thermal conductivity is higher than a thermal conductivity of a bottom wall of the wafer sub-carrier.

With reference to the second aspect, in a first possible implementation of the second aspect, a material of the bottom wall of the wafer sub-carrier is graphite; and a material of the side wall of the wafer sub-carrier is graphene.

In this implementation, the first thermally conductive material is selected for the material of the bottom wall of the wafer sub-carrier, so that a thermal radiation heating effect at a position of a flat edge of the epitaxial wafer substrate can be improved, and crystal quality of a flat edge of an epitaxial wafer is improved, thereby improving an overall yield of the epitaxial wafer.

With reference to the second aspect, in a second possible implementation of the second aspect, the side wall of the wafer sub-carrier includes a first layer and a second layer, and a thermal conductivity of the second layer is higher than the thermal conductivity of the bottom wall.

With reference to the second possible implementation of the second aspect, in a third possible implementation of the second aspect, the second layer includes a second thermally conductive material attached to an inner periphery of the first layer, and a thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the bottom wall of the wafer sub-carrier.

With reference to the third possible implementation of the second aspect, in a fourth possible implementation of the second aspect, the wafer carrier is a graphite carrier, the wafer sub-carrier is a groove on the graphite carrier, and the second thermally conductive material is graphene.

In this implementation, filling of the second thermally conductive material can be facilitated, production efficiency is improved, and a process flow is simple. In addition, the material of the second layer is selected for the material of the wafer sub-carrier, so that a thermal radiation heating effect at a position of a border of the epitaxial wafer substrate can be improved, crystal quality at a border of an epitaxial wafer is improved, and an overall yield of the epitaxial wafer is improved. In addition, a gap between the wafer sub-carrier and the epitaxial wafer substrate is filled by the second thermally conductive material, so that the epitaxial wafer substrate is more stable in the wafer sub-carrier, and a risk of flying pieces caused by a centrifugal force generated due to rotation of the wafer carrier or rotation of the wafer sub-carrier is reduced.

With reference to the second possible implementation of the second aspect, in a fifth possible implementation of the second aspect, a material of the second layer is graphene, a material of the first layer is graphite, and a material of the bottom wall of the wafer sub-carrier is graphite.

With reference to the second aspect, in a sixth possible implementation of the second aspect, a first space in the wafer sub-carrier is filled with a first thermally conductive material. The first space is a space between a flat edge of the epitaxial wafer substrate and the side wall of the wafer sub-carrier when the epitaxial wafer substrate is placed on the wafer sub-carrier. A thermal conductivity of the first thermally conductive material is not lower than a thermal conductivity of the wafer sub-carrier.

In this implementation, a thermal radiation heating effect at a position of the flat edge of the epitaxial wafer substrate can be improved, and a temperature at the position of the flat edge of the epitaxial wafer substrate is compensated for, so that generation of defects such as black spots, blurred edges, and cracks on a border of an epitaxial wafer is avoided, and crystal quality of a flat edge of the epitaxial wafer is improved, thereby improving an overall yield of the epitaxial wafer.

With reference to the sixth possible implementation of the second aspect, in a seventh possible implementation of the second aspect, a height of the first thermally conductive material filled in the first space is not higher than a height of the side wall of the wafer sub-carrier.

With reference to the sixth possible implementation of the second aspect, in an eighth possible implementation of the second aspect, a material of the wafer sub-carrier is graphite; and the first thermally conductive material is any one or a combination of at least two of the following:
graphite, silicon carbide, graphene, titanium metal, and tungsten metal.

With reference to the eighth possible implementation of the second aspect, in a ninth possible implementation of the second aspect, a surface of the wafer sub-carrier is coated with silicon carbide, and a surface of the first thermally conductive material filled in the first space is coated with silicon carbide.

With reference to the second aspect, in a tenth possible implementation of the second aspect, the wafer carrier is a large graphite carrier, and the wafer sub-carrier is a small graphite carrier disposed on the large graphite carrier.

With reference to the second aspect, in an eleventh possible implementation of the second aspect, a diameter of the epitaxial wafer is greater than or equal to <NUM> inches.

According to the wafer carrier provided in the embodiments of this application, the thermal radiation heating effect at the position of the flat edge or the border of the epitaxial wafer substrate can be improved, and the temperature at the position of the flat edge or the border of the epitaxial wafer substrate can be compensated for, so that a temperature of the entire epitaxial wafer substrate can be more even. In this way, the generation of defects such as black spots, blurred edges, and cracks on the flat edge or the border of the epitaxial wafer is avoided, the crystal quality of the flat edge of the epitaxial wafer is improved, and the overall yield of the epitaxial wafer is improved.

In the figures: <NUM>. Wafer carrier; <NUM>. Shaft hole; <NUM>. Wafer sub-carrier; <NUM>. Epitaxial wafer substrate; <NUM>. First space; <NUM>. Wafer sub-carrier bottom wall; <NUM>. Wafer sub-carrier side wall; <NUM>. First layer; <NUM>. Second layer.

The following describes technical solutions of embodiments in this application with reference to accompanying drawings. Apparently, the described embodiments are merely some but not all of the embodiments of this application. In addition, it should be noted that, in the embodiments of this application, unless otherwise specified, "a plurality of means two or more.

<FIG> shows a wafer carrier for metal organic chemical vapor deposition. As shown in <FIG>, a center of the wafer carrier is a shaft hole <NUM>. In a growing process of an epitaxial wafer, the wafer carrier <NUM> can rotate at a high speed driven by a rotating shaft corresponding to the shaft hole <NUM>. A plurality of wafer sub-carriers <NUM> are distributed on the wafer carrier <NUM>, and the plurality of wafer sub-carriers <NUM> are arranged on the wafer carrier along a loop. The loop passes through centers of the wafer sub-carriers <NUM> and is in a concentric relationship with an outer periphery of the wafer carrier.

The wafer sub-carrier <NUM> is in a groove structure and is configured to place the epitaxial wafer substrate <NUM>. The wafer carrier <NUM> may be a large graphite carrier, and the wafer sub-carrier <NUM> may be a small graphite carrier. A surface of the large graphite carrier and a surface of the small graphite carrier are both coated with a silicon carbide material. The small graphite carrier can rotate in the growing process of the epitaxial wafer.

The small graphite carrier is usually circular, and when an epitaxial wafer substrate is placed on the small graphite carrier, a relatively large gap is left between a flat edge of the epitaxial wafer substrate and a side wall of the small graphite carrier. During growth of the epitaxial wafer, because an airflow of a carrier gas can quickly take away heat, a temperature at a position of the flat edge of the epitaxial wafer substrate is lower than a temperature at a position of a center of the epitaxial wafer substrate. In other words, a flat edge and a center of the epitaxial wafer may be unevenly heated. Consequently, crystal quality of the flat edge of epitaxial wafer is poor, and a large quantity of defects such as black spots, blurred edges, and cracks occur.

In addition, for epitaxial wafer substrates of larger sizes (for example, <NUM> inches, <NUM> inches, and <NUM> inches), warpage of an epitaxial wafer grown on the epitaxial wafer substrate is relatively large. Consequently, a border of the epitaxial wafer is warped by a particular height, causing a temperature of the border of the epitaxial wafer to be lower than that of a center of the epitaxial wafer, and resulting in poor crystal quality of the border of the epitaxial wafer and a large quantity of defects such as black spots, blurred edges, and cracks.

An embodiment of this application provides a wafer carrier for metal organic chemical vapor deposition. As shown in <FIG>, the wafer carrier includes at least one wafer sub-carrier <NUM>. The wafer sub-carrier <NUM> is in a groove structure and is configured to place the epitaxial wafer substrate <NUM>.

The wafer carrier may be a graphite carrier, and the wafer sub-carrier <NUM> is a groove on the graphite carrier. A structure of the wafer sub-carrier <NUM> is shown in <FIG>. It can be learned that the wafer sub-carrier <NUM> is integrally formed. Specifically, the wafer sub-carrier <NUM> may be formed in a form of a groove carved in the wafer carrier. The wafer sub-carrier <NUM> has a bottom wall <NUM> and a side wall <NUM>.

Alternatively, the wafer carrier may be a large graphite carrier, and the wafer sub-carrier <NUM> is a small graphite carrier disposed on the large graphite carrier. Specifically, as shown in <FIG>, it can be learned that the wafer sub-carrier <NUM> and the wafer carrier are independent of each other, and the wafer sub-carrier <NUM> is located on the wafer carrier. In an example, the wafer sub-carrier <NUM> can rotate during growth of an epitaxial wafer.

The epitaxial wafer substrate <NUM> may be a substrate with a diameter greater than or equal to <NUM> inches. Specifically, the epitaxial wafer substrate <NUM> may be a substrate with a diameter of <NUM> inches, or may be a substrate with a diameter of <NUM> inches, or may be a substrate with a diameter of <NUM> inches.

As shown in <FIG>, a first space <NUM> in any wafer sub-carrier <NUM> is filled with a first thermally conductive material. The first space <NUM> is a space between a flat edge of the epitaxial wafer substrate <NUM> and a side wall of the wafer sub-carrier <NUM> when the epitaxial wafer substrate <NUM> is placed on the wafer sub-carrier <NUM>. A thermal conductivity of the first thermally conductive material is not lower than a thermal conductivity of the wafer sub-carrier <NUM>. A surface that is of the first space <NUM> in any wafer sub-carrier <NUM> and that faces the flat edge of the epitaxial wafer substrate <NUM> is a plane. The plane is perpendicular to a radial direction of the wafer carrier. In an example, the first space <NUM> in any wafer sub-carrier <NUM> may be located on a side that is of the wafer sub-carrier <NUM> and that is away from a shaft hole <NUM>.

In an example, a height of the first thermally conductive material filled in the first space <NUM> is not higher than a height of the side wall of the wafer sub-carrier <NUM>.

To avoid a risk of the first thermally conductive material being thrown off due to rotation of the wafer carrier and rotation of the wafer sub-carrier <NUM>, the height of the filled first thermally conductive material is not higher than that of the side wall of the wafer sub-carrier <NUM>.

In a case of this example, the height of the first thermally conductive material filled in the first space <NUM> is equal to the height of the side wall of the wafer sub-carrier <NUM>.

In another case of this example, the height of the first thermally conductive material filled in the first space <NUM> is not higher than the height of the side wall of the wafer sub-carrier <NUM>, and is not lower than a thickness of the epitaxial wafer substrate <NUM>.

In an example, a material of the wafer sub-carrier <NUM> is graphite, and the first thermally conductive material is any one or a combination of at least two of the following:
graphite, silicon carbide, graphene, titanium metal, and tungsten metal.

In a case of this example, the first thermally conductive material may be coated or bonded to the first space <NUM>.

In another case of this example, a surface of the wafer sub-carrier <NUM> is coated with silicon carbide, and a surface of the first thermally conductive material filled in the first space <NUM> is coated with silicon carbide. Coating silicon carbide can increase strength and hardness of the surface of the wafer sub-carrier <NUM> and the surface of the first thermally conductive material, and can mitigate gas corrosion.

The wafer sub-carrier <NUM> has a side wall whose thermal conductivity is higher than a thermal conductivity of the bottom wall of the wafer sub-carrier <NUM>.

In this example, the thermal conductivity of the side wall of the wafer sub-carrier <NUM> is relatively high, so that during growth of an epitaxial wafer, a thermal radiation heating effect on a border of the epitaxial wafer is better, thereby avoiding poor crystal quality at the border of the epitaxial wafer, and a large quantity of defects such as black spots, blurred edges, and cracks.

In a first case of this example, a material of the bottom wall of the wafer sub-carrier <NUM> may be graphite, and a material of the side wall of the wafer sub-carrier <NUM> is graphene.

Specifically, a structure of the wafer sub-carrier <NUM> may be shown in <FIG>. The wafer sub-carrier <NUM> includes a bottom wall <NUM> and a side wall <NUM>. A component material of the bottom wall <NUM> is graphite, and a component material of the side wall <NUM> is graphene. A surface of the bottom wall <NUM> and a surface of the side wall <NUM> are coated with silicon carbide, to increase strength and hardness, and to mitigate gas corrosion.

In a second case of this example, the side wall of the wafer sub-carrier includes a first layer and a second layer, and a thermal conductivity of the second layer is higher than the thermal conductivity of the bottom wall of the wafer sub-carrier.

In a specific implementation solution of the second example, the structure of the wafer sub-carrier <NUM> may be shown in <FIG>. The wafer sub-carrier <NUM> includes a bottom wall <NUM> and a side wall. The side wall includes a first layer <NUM> and a second layer <NUM>. The second layer <NUM> is made of a second thermally conductive material attached to an inner periphery of the first layer <NUM>. A thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the bottom wall <NUM> of the wafer sub-carrier. Specifically, the second thermally conductive material may be coated or bonded to the inner periphery of the first layer <NUM>, to form the second layer <NUM>.

Composition materials of the bottom wall <NUM> and the first layer <NUM> may be graphite, and a composition material of the second layer <NUM> may be graphene. A surface of the bottom wall <NUM>, a surface of the first layer <NUM>, and a surface of the second layer <NUM> are coated with silicon carbide, to increase strength and hardness, and to mitigate gas corrosion.

In another specific implementation solution of the second example, the structure of the wafer sub-carrier <NUM> may be shown in <FIG>. The wafer sub-carrier <NUM> is a groove of the wafer carrier, and the wafer sub-carrier <NUM> and the wafer carrier are integrated. The side wall of the wafer sub-carrier <NUM> includes a first layer <NUM> and a second layer <NUM>. The first layer <NUM> is a wall formed by a body of the wafer carrier. The second layer <NUM> is made of a second thermally conductive material attached to an inner periphery of the first layer <NUM>. A thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the bottom wall <NUM> of the wafer sub-carrier. Specifically, the second thermally conductive material may be coated or bonded to the inner periphery of the first layer <NUM>, to form the second layer <NUM>.

A composition material of the wafer carrier may be graphite. To be specific, composition materials of the bottom wall <NUM> and the first layer <NUM> may be graphite, and a composition material of the second layer <NUM> may be graphene. A surface of the bottom wall <NUM> and a surface of the second layer <NUM> are coated with silicon carbide, to increase strength and hardness, and to mitigate gas corrosion.

In still another specific implementation solution of the second example, referring to <FIG>, the second layer <NUM> is formed by filling a second space with a second thermally conductive material, the filled second thermally conductive material is attached to an inner periphery of the first layer, and the first layer is an original side wall of the wafer sub-carrier <NUM>. The second layer <NUM> is formed by filling the second thermally conductive material, and the second layer <NUM> and the first layer together form a new side wall of the wafer sub-carrier <NUM>. A thermal conductivity of the first layer of the wafer sub-carrier <NUM> is the same as the thermal conductivity of the bottom wall of the wafer sub-carrier <NUM>, and a thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the bottom wall of the wafer sub-carrier <NUM>, so that a thermal conductivity of the new side wall is higher than the thermal conductivity of the bottom wall. A gap between the wafer sub-carrier and the epitaxial wafer substrate is filled with the second thermally conductive material, so that the epitaxial wafer substrate is more stable in the wafer sub-carrier, thereby reducing a risk of flying pieces caused by a centrifugal force generated due to rotation of the wafer carrier or rotation of the wafer sub-carrier.

Materials of the first layer and the bottom wall may be graphite, and the second thermally conductive material may be graphene. A surface of the second layer <NUM> and a surface of the bottom wall are coated with silicon carbide, to increase strength and hardness, and to mitigate gas corrosion.

In a third case of this example, the first thermally conductive material and the second thermally conductive material may be the same, for example, both may be graphene, and may be filled at the same time during filling, thereby improving production efficiency, and a process flow is simple.

According to the wafer carrier provided in this embodiment of this application, the thermal radiation heating effect at the position of the flat edge or the border of the epitaxial wafer substrate can be improved, and the temperature at the position of the flat edge of the epitaxial wafer substrate can be compensated for, so that a temperature of the entire epitaxial wafer substrate can be more even. In this way, generation of defects such as black spots, blurred edges, and cracks on the flat edge of the epitaxial wafer is avoided, and the crystal quality of the flat edge of the epitaxial wafer is improved, thereby improving an overall yield of the epitaxial wafer.

An embodiment of this application provides a wafer carrier for metal organic chemical vapor deposition. As shown in <FIG>, the wafer carrier includes at least one wafer sub-carrier <NUM>. The wafer sub-carrier <NUM> is in a groove structure and is configured to place the epitaxial wafer substrate <NUM>. The wafer sub-carrier has a side wall whose thermal conductivity is higher than a thermal conductivity of a bottom wall of the wafer sub-carrier.

The wafer carrier may be a large graphite carrier, and the wafer sub-carrier <NUM> is a small graphite carrier disposed on the large graphite carrier. Specifically, as shown in <FIG>, it can be learned that the wafer sub-carrier <NUM> and the wafer carrier are independent of each other, and the wafer sub-carrier <NUM> is located on the wafer carrier. In an example, the wafer sub-carrier <NUM> can rotate during growth of an epitaxial wafer.

In an example, a material of the bottom wall of the wafer sub-carrier <NUM> may be graphite, and a material of the side wall of the wafer sub-carrier <NUM> is graphene.

In an example, the side wall of the wafer sub-carrier includes a first layer and a second layer, and a thermal conductivity of the second layer is higher than the thermal conductivity of the bottom wall of the wafer sub-carrier.

In a case of this example, the structure of the wafer sub-carrier <NUM> may be shown in <FIG>. The wafer sub-carrier <NUM> includes a bottom wall <NUM> and a side wall. The side wall includes a first layer <NUM> and a second layer <NUM>. The second layer <NUM> is made of a second thermally conductive material attached to an inner periphery of the first layer <NUM>. A thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the bottom wall <NUM> of the wafer sub-carrier. Specifically, the second thermally conductive material may be coated or bonded to the inner periphery of the first layer <NUM>, to form the second layer <NUM>.

In another case of this example, the structure of the wafer sub-carrier <NUM> may be shown in <FIG>. The wafer sub-carrier <NUM> is a groove of the wafer carrier, and the wafer sub-carrier <NUM> and the wafer carrier are integrated. The side wall of the wafer sub-carrier <NUM> includes a first layer <NUM> and a second layer <NUM>. The first layer <NUM> is a wall formed by a body of the wafer carrier. The second layer <NUM> is made of a second thermally conductive material attached to an inner periphery of the first layer <NUM>. A thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the bottom wall <NUM> of the wafer sub-carrier. Specifically, the second thermally conductive material may be coated or bonded to the inner periphery of the first layer <NUM>, to form the second layer <NUM>.

In a specific implementation of this example, the wafer carrier is a graphite carrier, the wafer sub-carrier <NUM> is a groove on the graphite carrier, and the second thermally conductive material is graphene. In other words, composition materials of the bottom wall <NUM> and the first layer <NUM> are both graphite, and a composition material of the second layer <NUM> is graphene. A surface of the bottom wall <NUM> and a surface of the second layer <NUM> are coated with silicon carbide, to increase strength and hardness, and to mitigate gas corrosion.

In still another case of this example, referring to <FIG>, the second layer <NUM> is formed by filling a second space with a second thermally conductive material, the filled second thermally conductive material is attached to an inner periphery of the first layer, and the first layer is an original side wall of the wafer sub-carrier <NUM>. The second layer <NUM> is formed by filling the second thermally conductive material, and the second layer <NUM> and the first layer together form a new side wall of the wafer sub-carrier <NUM>. A thermal conductivity of the first layer of the wafer sub-carrier <NUM> is the same as the thermal conductivity of the bottom wall of the wafer sub-carrier <NUM>, and a thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the bottom wall of the wafer sub-carrier <NUM>, so that a thermal conductivity of the new side wall is higher than the thermal conductivity of the bottom wall. A gap between the wafer sub-carrier and the epitaxial wafer substrate is filled with the second thermally conductive material, so that the epitaxial wafer substrate is more stable in the wafer sub-carrier, thereby reducing a risk of flying pieces caused by a centrifugal force generated due to rotation of the wafer carrier or rotation of the wafer sub-carrier.

In an example, as shown in <FIG>, a first space <NUM> in any wafer sub-carrier <NUM> is filled with a first thermally conductive material. The first space <NUM> is a space between a flat edge of the epitaxial wafer substrate <NUM> and a side wall of the wafer sub-carrier <NUM> when the epitaxial wafer substrate <NUM> is placed on the wafer sub-carrier <NUM>. A thermal conductivity of the first thermally conductive material is not lower than a thermal conductivity of the wafer sub-carrier <NUM>. A surface that is of the first space <NUM> in any wafer sub-carrier <NUM> and that faces the flat edge of the epitaxial wafer substrate <NUM> is a plane. The plane is perpendicular to a radial direction of the wafer carrier. In an example, the first space <NUM> in any wafer sub-carrier <NUM> may be located on a side that is of the wafer sub-carrier <NUM> and that is away from a shaft hole <NUM>.

In a first case of this example, a height of the first thermally conductive material filled in the first space <NUM> is not higher than a height of the side wall of the wafer sub-carrier <NUM>.

In a specific implementation solution of the first example, the height of the first thermally conductive material filled in the first space <NUM> is equal to the height of the side wall of the wafer sub-carrier <NUM>.

In another specific implementation solution of the first example, the height of the first thermally conductive material filled in the first space <NUM> is not higher than the height of the side wall of the wafer sub-carrier <NUM>, and is not lower than a thickness of the epitaxial wafer substrate <NUM>.

In a second case of this example, a material of the wafer sub-carrier <NUM> is graphite, and the first thermally conductive material is any one or a combination of at least two of the following:
graphite, silicon carbide, graphene, titanium metal, and tungsten metal.

In this example, the first thermally conductive material may be coated or bonded to the first space <NUM>. A surface of the wafer sub-carrier <NUM> may be coated with silicon carbide, and a surface of the first thermally conductive material filled in the first space <NUM> may be coated with silicon carbide. Coating silicon carbide can increase strength and hardness of the surface of the wafer sub-carrier <NUM> and the surface of the first thermally conductive material, and can mitigate gas corrosion.

Claim 1:
A wafer carrier for metal organic chemical vapor deposition, comprising:
at least one wafer sub-carrier (<NUM>) that is in a groove structure and that is configured to place a substrate for an epitaxial wafer (<NUM>); and
wherein a thermal conductivity of a side wall (<NUM>) of the wafer sub-carrier is higher than a thermal conductivity of a bottom wall (<NUM>) of the wafer sub-carrier;
characterized in that the wafer carrier further comprises:
a first space (<NUM>) in the wafer sub-carrier (<NUM>) is filled with a first thermally conductive material, the first space (<NUM>) is a space between a flat edge of the substrate for an epitaxial wafer (<NUM>) and a side wall (<NUM>) of the wafer sub-carrier when the substrate for an epitaxial wafer (<NUM>) is placed on the wafer sub-carrier (<NUM>), a thermal conductivity of the first thermally conductive material is not lower than a thermal conductivity of the wafer sub-carrier (<NUM>).