Patent Description:
Radar systems are becoming increasingly common in the automotive industry, being used, for example, as sensors for assisted parking, automatic cruise control speed adjustment (adaptive cruise control), headway alert, collision warning and mitigation, and brake support. Radar systems perform detection and ranging by transmitting an electromagnetic wave, such as a pulse, from a transmission antenna and measuring the time taken for the reflected signal to be detected at a receiving sensor. The amount of time taken for a reflected signal to reach an obstacle and be reflected back provides an indication of the range of that obstacle from the radar system.

Frequency modulated continuous wave radar (FMCW) systems emit series of pulses (detection signals) to obtain a time resolved range profile of the space around the radar systems. Each detection signal comprises a continuous electromagnetic signal that varies between an initial frequency and a final frequency over a period of time. The bandwidth of the detection signals is the difference between the initial frequency and the final frequency. The detection signals are reflected off of objects in the detection space around the FMCW radar systems. The reflected signals are detected by receivers of the FMCW radar systems. International patent application, publication number <CIT> discloses a method for phase calibration of high frequency components of a radar sensor. This document discloses a method for calibrating two receiving units of a radar sensor, which has an array of receiving antennas formed by two part-arrays and an evaluation device, which is designed to perform an angle estimation for localised radar targets by means of phase differences between the signals received by the receiving antennas, each receiving unit having parallel reception paths for the signals of the receiving antennas of one of the part-arrays, characterised by the following steps: analysing the received signals and deciding whether a multi-target or a single-target scenario is present, in the event of a single-target scenario measuring phases of the signals received in the part-array, and calculating a phase offset between the two part-arrays, and calibrating the phases in the two receiving units by means of the calculated phase offset.

A frequency modulated continuous wave (FMCW) radar system includes an antenna array having (C = A + B - <NUM>) antennas, a first integrated circuit (IC) device including A first sensor inputs, and a second IC device including B second sensor inputs. The first sensor inputs are coupled to a first A of the antennas, and the second sensor inputs are coupled to a last B of the antennas such that a common one of the first sensor inputs and a common one of the second sensor inputs are both coupled to a common antenna. Each IC device receives reflected signals on each sensor input, and mixes the reflected signals to associated baseband signals based upon a local oscillator (LO) signal. Each LO signal has a different phase shift. The LO signals are based upon a common LO signal.

The FMCW radar system includes a processor configured to receive the baseband signals, to determine a difference between the phase shifts based upon the common baseband signals, and to correct at least one of the sets of baseband signals based upon the difference between the phase shifts.

In determining the difference between the phase shifts, the processor may be further configured to determine a delay time between the first common baseband signal and the second common baseband signal.

In correcting the at least one of the sets of baseband signals, the processor may be further configured to delay the at least one of the first baseband signals and the second baseband signals by the delay time.

The IC device devices may be further configured to digitize the baseband signals, where outputting the baseband signals may comprise outputting the digitized signals.

The processor may be further configured to perform a Fast Fourier Transform (FFT) on the digitized baseband signals to obtain transformed signals including common transformed signal associated with the common sensor inputs.

In determining the difference between the phase shifts, the processor may be further configured to determine a complex phase shift between common first transformed signal and the common second transformed signal in a frequency domain.

In correcting the at least one of the sets of baseband signals, the processor may be further configured to shift a phase of at least one of the sets of transformed baseband signals based upon the complex phase shift.

The first IC device may be further configured to generate the first LO signal, and the second IC device may be further configured to receive the second LO signal from the first ICdevice.

The antennas of the antenna array may be arranged in a line and each antenna is spaced apart from a next antenna at a distance of lambda/<NUM> or more, where lambda is a wavelength of a carrier wave of a FMCW chirp of the FMCW radar system.

It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures have not necessarily been drawn to scale. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the drawings presented herein,in which:.

The following description in combination with the Figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings, and should not be interpreted as a limitation on the scope or applicability of the teachings.

In this ID, we propose a technique to estimate and compensate the LO phase difference between a Master and Slave ICs in cascaded systems using MMICs that have a shared LO input and output port. After measurement, the systematic LO phase offset can be compensated on one of the two sets of IF signals, so that the resulting sets of 2x <NUM> RX signals are free of LO offsets. The concept can be expanded to any number of slaves.

<FIG> illustrates a radar system <NUM> configured to provide for detection and ranging of an object <NUM> in a space <NUM> around the radar system. Radar system <NUM> is a MIMO radar system, including multiple transmit antennas and multiple receive antennas. Radar system <NUM> is configured to emit a series of encoded detection signals on each transmit antenna, to receive the reflected signals from object <NUM>, and to determine the range to the object and the incident angle to the object. The angular resolution of radar system <NUM> is directly related to the total antenna aperture, which is determined by the number of receive antennas and their localization with respect to each other.

In order to avoid so-called grating lobes in the angular response (i.e. false target detection at certain angular positions), the receive antennas of radar system <NUM> are typically located at a distance of lambda/<NUM> (λ/<NUM>) apart, or less, where λ is the wavelength of the carrier signal of the detection signal, that is, the wavelength associated with the middle frequency of the detection signals. Typical MIMO radar systems may have apertures in the range of <NUM> to <NUM> lambda, which,in combination with the lambda/w criteria for antenna placement, leads to antenna arrays of <NUM> to <NUM> receive antennas. It will be understood that in practice, a distance of more than lambda/<NUM> (λ/<NUM>) may be utilized as needed or desired.

The detection signal from each receive antenna is down-converted to an intermediate frequency (IF) baseband frequency and translated to the digital domain by analog-to-digital converters (ADCs) before being further processed to determine distance information, speed information, and incident angle information for object <NUM>. In a particular embodiment, radar system <NUM> is implemented using one or more radio frequency (RF) integrated circuits (IC) or monolithic microwave integrated circuits (MMICs). Here, a particular IC or MMIC may provide a transmit (TX) capability with a number of transmit channels, provides a receive (RX) capability with a number of receive channels, or may provide a transmit and receive (TX/RX) capability. By utilizing various ICs and MMICs, a designer of radar system <NUM> can adapt the design as needed or desired.

<FIG> illustrates various embodiments of cascaded radar systems <NUM> and <NUM>, similar to radar system <NUM>. Radar systems <NUM> and <NUM> are designed utilizing a transmit IC <NUM>, and one or more receive ICs <NUM>. For example, transmit IC <NUM> may be configured to include two transmit channels and to provide an output for a local oscillator (LO) signal, and receive IC <NUM> may be configured to include four receive channels and to provide an input for the LO signal from the transmit IC. Radar system <NUM> has an antenna array <NUM> with six antennas. Antenna array <NUM> includes two transmit antennas to emit detection signals from the two transmit channels of transmit IC <NUM>, and includes four receive antennas to receive reflected signals from the four receive channels of receive IC <NUM>. Receive IC <NUM> receives the LO signal from transmit IC <NUM>. Radar system <NUM> has an antenna array <NUM> with <NUM> antennas. Antenna array <NUM> includes a single transmit antenna to emit a detection signal from one of the transmit channels of transmit IC <NUM>, and includes <NUM> receive antennas. Here, four receive antennas are connected to a first receive IC 204A, four receive antennas are connected to a second receive IC 204B, and four receive antennas are connected to a third receive IC 204C. Receive ICs 204A, 204B, and 204C each receive the LO signal from transmit IC <NUM>. It will be understood that transmit IC <NUM> will include other connections and interfaces (not illustrated), such as a crystal or clock input, one or more synchronization signal to synchronize the operation of the transmit IC with the one or more receive ICs <NUM>, and other inputs or outputs, as needed or desired. It will be understood that receive IC <NUM> will include other connections and interfaces (not illustrated), such as one or more RF signal output, one or more IF signal output, for example where the receive IC includes down-converters to mix the received signals from the receive channels to the IF frequency, one or more data output, for example where the receive IC includes ADCs to digitize the IF signals, one or more synchronization signal to synchronize the operation of the receive IC with transmit IC <NUM> and with other receive ICs if present, and other inputs or outputs,as needed or desired.

<FIG> illustrates a radar system <NUM> similar to radar system <NUM>. Radar system <NUM> includes a first transmit/receive IC <NUM>, a second transmit/receive IC <NUM>, and a signal processing IC <NUM>. Transmit/receive ICs <NUM> and <NUM> represent RF ICs or MMICs which may more may not be identically specified, as needed or desired. Transmit/receive ICs <NUM> and <NUM> each include at least one transmit channel, and at least four receive channels. The transmit channel of IC <NUM> is connected to a transmission antenna <NUM>, and the four receive channels of IC <NUM> are connected to an antenna array <NUM> of four receive antennas. In particular, the four receive antennas of antenna array <NUM> are designated, from left to right, as RX(M. <NUM>), RX(M. <NUM>), RX(M. <NUM>), and RX(M. <NUM>), and each antenna located at a lambda/<NUM> spacing from the next antenna,as described above. Similarly, the transmit channel of IC <NUM> is connected to a transmission antenna <NUM>, and the four receive channels of IC <NUM> are connected to an antenna array <NUM> of four receive antennas. In particular, the four receive antennas of antenna array <NUM> are designated, from left to right, as RX(S. <NUM>), RX(S. <NUM>), RX(S. <NUM>), and RX(S. <NUM>), and each antenna is located at a lambda/<NUM> spacing from the next antenna. Moreover, antenna RX(M. <NUM>) is located at the lambda/<NUM> spacing from antenna RX(S. <NUM>), such that the antennas of antenna arrays <NUM> and <NUM> are together configured as a single receive antenna array <NUM> of eight antennas.

IC <NUM> further includes a clock or crystal input to which, in the illustrated example, a crystal is connected. The crystal is utilized by IC <NUM> as an input to derive a LO signal. The LO signal derived from the crystal is utilized internally in IC <NUM> to generate a detection signal to be emitted on transmit antenna <NUM>, and in the down-converting of the detected signals from receive antenna array <NUM> to the baseband frequency. The LO signal is also provided to a LO output (LO_OUT) of IC <NUM>. In this regard, IC <NUM> may be referred to as a "master" IC. IC <NUM> includes a LO input (LO_IN) to receive the LO signal from IC <NUM>. In this regard, IC <NUM> may be referred to as a "slave" IC. The LO signal from LO_IN is utilized internally in IC <NUM> to generate a detection signal to be emitted on transmit antenna <NUM>, and in the down-converting of the detected signals from receive antenna array <NUM> to the baseband frequency. IC <NUM> includes a chirp_start output that is provided to a chirp_start input of IC <NUM> to synchronize the start of the detection signals by IC <NUM> with the start of the detection signals by IC <NUM>. The details of generating FMCW detection signals and the down-converting of detected signals are known in the art, and will not be further described herein except as needed to illustrate the current embodiments.

The crystal is further utilized by IC <NUM> to derive a <NUM> clock for the operation of ADCs in the IC that digitize the down-converted detected signals from antenna array <NUM>. IC <NUM> includes a <NUM> output that is connected to a <NUM> input of IC <NUM> for the operation ofADCs in IC <NUM> that digitize the down-converted detected signals from antenna array <NUM>, and to synchronize the digitization operations of the ADCs in ICs <NUM> and <NUM>. ICs <NUM> and <NUM> each include a high-speed digital communication interface for the communication of the digitized detected signals from respective antenna arrays <NUM> and <NUM> to processing IC <NUM> for processing. An example of a high-speed digital communication interface may include a Mobile Industry Processor Interface (MIPI) Camera Serial Interface-<NUM> (CSI-<NUM>) interface, a Low Voltage Differential Signaling (LVDS) interface, or the like, as needed of desired. The details of digitizing detected signals and communicating digitized signals via digital communication interfaces are known in the art, and will not be further described herein except as needed to illustrate the current embodiments. ICs <NUM> and <NUM> each include a low-speed digital communication interface that is connected to processing IC <NUM>, whereby processing IC <NUM> communicates with ICs <NUM> and <NUM> to set up the operating parameters of ICs <NUM> and <NUM>, to monitor the operations of ICs <NUM> and <NUM>, and to modify the operating parameters of ICs <NUM> and <NUM>, as needed or desired. An example of a low-speed digital communication interface may include a Serial Peripheral Interface (SPI), or the like, as needed or desired. The details of management and control of ICs via a low-speed digital communication interface are known in the art, and will not be further described herein except as needed to illustrate the current embodiments.

Processing IC <NUM> represents a digital signal processing device configured to extract object detection, range, speed, and incident angle information from the digitized detected signals from ICs <NUM> and <NUM>. An example of processing IC <NUM> may include a microcontroller unit (MCU), a digital signal processor (DSP), a field-programmable gate array (FPGA) device, or the like. The details of processing digitized detected signals into object detection, range, speed, and incident angle information are known in the art, and will not be further described herein except as needed to illustrate the current embodiments.

It has been understood by the inventor to the present invention that, where multiple ICs or MMICs are utilized in the design of a radar system, the signals between the ICs or MMICs need to be highly phase coherent. In particular, the signals utilized to down-convert the detection signals (the LO signals) should be in phase, not only within each IC or MMIC, but also between the various ICs or MMICs, in order to reduce angular errors in the determination of the angle of incidence of the detected objects. As such, the signals utilized to down-convert the detection signals (the LO signals) should be in phase, not only within each of ICs <NUM> and <NUM>, but also between the ICs. In a particular embodiment, ICs <NUM> and <NUM> represent identically specified ICs, such as were each IC is of a same type and part number, or where the ICs are of different types, but are from a common family of components.

Here, the placement of, and interconnections between ICs <NUM> and <NUM> may be specified, such as by a design rule or a design recommendation. Here further, ICs <NUM> and <NUM> may be configured such that, if the specified placement and interconnections are followed, the ICs are designed to ensure that the LO signals as used internally to the ICs are synchronized with each other, such as by providing an internal delay of a known duration to the internal LO in one or the other of the ICs. Here, the phase coherence of the detected signals from IC <NUM> will be understood to be high, that is, within a specified tolerance, the coherence of the detected signals from IC <NUM> will be understood to be high, and the coherence between the detected signals from IC <NUM> and the detected signals form IC <NUM> will be understood to also be high. Thus, the configuration illustrated by radar system <NUM> provides a simple and compact design.

However, even with such a configuration, and even where the design rules or design recommendations are followed, the phase coherence of the LO signal may not be adequate. As a first matter, thermal variations between IC <NUM> and IC <NUM>, and between the ICs and a printed circuit board (PCB) or other circuit board upon which the ICs are mounted, may lead to uncompensated decoherence of the LO signal as used each IC. Moreover, it will be understood that radar system <NUM> may be representative of radar systems with more than one slave IC, and where the LO_OUT output from IC <NUM> is provided to the LO_IN inputs of two or more slave ICs. Here, additional slave ICs may be understood to be placed to the right of IC <NUM>. Here, further, the signal traces between the LO-OUT output of IC <NUM>, and a LO_IN input of the additional slave IC will be understood to be longer than the signal trace between IC <NUM> and IC <NUM>. Here, each additional slave IC will be seen to have a longer trace length, and hence the LO signal to each additional IC will be understood to be more out of phase with the LO signal as used by IC <NUM>.

<FIG> illustrates a radar system <NUM> similar to radar systems <NUM> and <NUM>. Radar system <NUM> includes a first transmit/receive IC <NUM>, a second transmit/receive IC <NUM>, and a signal processing IC <NUM>. Transmit/receive ICs <NUM> and <NUM> represent RF ICs or MMICs which may more may not be identically specified, as needed or desired. Transmit/receive ICs <NUM> and <NUM> each include at least one transmit channel, and at least four receive channels. The transmit channel of IC <NUM> is connected to a transmission antenna <NUM>, and the four receive channels of IC <NUM> are connected to an antenna array <NUM> of four receive antennas. In particular, the four receive antennas of antenna array <NUM> are designated, from left to right, as RX(M. <NUM>), RX(M. <NUM>), RX(M. <NUM>), and RX(M. <NUM>), and each antenna located at a lambda/<NUM> spacing from the next antenna, as described above. Similarly, the transmit channel of IC <NUM> is connected to a transmission antenna <NUM>, and the four receive channels of IC <NUM> are connected to an antenna array <NUM> of four receive antennas. In particular, the four receive antennas of antenna array <NUM> are designated, from left to right, as RX(S. <NUM>), RX(S. <NUM>), RX(S. <NUM>), and RX(S. <NUM>), and each antenna is located at a lambda/<NUM> spacing from the next antenna. Moreover, antenna RX(M. <NUM>) is located at the lambda/<NUM> spacing from antenna RX(S. <NUM>), such that the antennas of antenna arrays <NUM> and <NUM> are together configured as a single receive antenna array <NUM> of eight antennas.

IC <NUM> further includes a clock or crystal input to which, in the illustrated example, a crystal is connected. The crystal is utilized by IC <NUM> as an input to derive a LO signal. The LO signal derived from the crystal provided to a LO output (LO_OUT) of IC <NUM>. As such, here, IC410 is the master IC. IC <NUM> further includes a LO input (LO_IN) to receive the LO signal. IC <NUM> does not use the internal LO signal, but instead utilizes the LO signal from the LO input to generate a detection signal to be emitted on transmit antenna <NUM>, and in the down-converting of the detected signals from receive antenna array <NUM> to the baseband frequency. The LO signal is also provided to a LO input (LO_IN) of IC <NUM>. Here, IC <NUM> is the slave IC. The LO signal from LO_IN is utilized internally in IC <NUM> to generate a detection signal to be emitted on transmit antenna <NUM>, and in the down-converting of the detected signals from receive antenna array <NUM> to the baseband frequency. IC <NUM> includes a chirp_start output that is provided to a chirp_start input of IC <NUM> to synchronize the start of the detection signals by IC <NUM> with the start of the detection signals by IC <NUM>.

The crystal is further utilized by IC <NUM> to derive a <NUM> clock for the operation of ADCs in the IC that digitize the down-converted detected signals from antenna array <NUM>. IC <NUM> includes a <NUM> output that is connected to a <NUM> input of IC <NUM> for the operation ofADCs in IC <NUM> that digitize the down-converted detected signals from antenna array <NUM>, and to synchronize the digitization operations of the ADCs in ICs <NUM> and <NUM>. ICs <NUM> and <NUM> each include a high-speed digital communication interface for the communication of the digitized detected signals from respective antenna arrays <NUM> and <NUM> to processing IC <NUM> for processing. ICs <NUM> and <NUM> each include a low-speed digital communication interface that is connected to processing IC <NUM>, whereby processing IC <NUM> communicates with ICs <NUM> and <NUM> to set up the operating parameters of ICs <NUM> and <NUM>, to monitor the operations of ICs <NUM> and <NUM>, and to modify the operating parameters of ICs <NUM> and <NUM>, as needed or desired. Processing IC <NUM> represents a digital signal processing device configured to extract object detection, range, speed, and incident angle information from the digitized detected signals from ICs <NUM> and <NUM>.

Note here that both ICs <NUM> and <NUM> use the common LO signal from the LO output of IC <NUM> via their respective LO inputs. In this way, the LO signal received by both ICs <NUM> and <NUM> have a common phase shift because the length of the signal trace between the LO output (LO_OUT) and the LO input (LO_IN) of IC <NUM> is the same as the length of the signal trace between the LO output (LO_OUT) and the LO input (LO_IN) of IC <NUM>. As such, both signal traces will be subjected to common thermal environments, so that any drift in the LO signal as seen by the LO input of IC <NUM> will be the same as the drift in the LO signal as seen by the LO input of IC <NUM>. Here, the pair of ICs <NUM> and <NUM> can be simplified, in that the need for internal compensation for LO signal phase variations may be reduced or eliminated. However, this advantage comes at the cost of an additional output pin on IC <NUM> to accommodate the LO output(LO_OUT). Further, where radar system <NUM> is representative of radar systems with more than one slave IC, the need to ensure that all LO signal traces between the LO output (LO_OUT) of IC <NUM> and the various LO inputs (LO_IN) are as long as the longest trace, resulting in a greater portion of the PCB or other circuit board upon which the ICs are mounted being utilized for LO signal trace routing. Further, the signal trace for the closest IC may need to be routed via a circuitous routing to ensure that the length of the signal trace to the closest IC is as long as the signal trace to the farthest IC.

<FIG> illustrates a radar system <NUM> similar to radar systems <NUM>, <NUM>, and <NUM>. Radar system <NUM> includes a first transmit/receive IC <NUM>, a second transmit/receive IC <NUM>, and a signal processing IC <NUM>. Transmit/receive ICs <NUM> and <NUM> represent RF ICs or MMICs which may more may not be identically specified, as needed or desired. Transmit/receive ICs <NUM> and <NUM> each include at least one transmit channel, and at least four receive channels. The transmit channel of IC <NUM> is connected to a transmission antenna <NUM>, three of the four receive channels of IC <NUM> are connected to an antenna array <NUM> of three receive antennas, and the fourth receive channel of IC <NUM> is connected to an antenna <NUM>. In particular, the three receive antennas of antenna array <NUM> are designated, from left to right, as RX(M. <NUM>), RX(M. <NUM>), and RX(M. <NUM>), and antenna <NUM> is designated RX(M. <NUM>), and each antenna located at a lambda/<NUM> spacing from the next antenna, as described above. Similarly, the transmit channel of IC <NUM> is connected to a transmission antenna <NUM>, a first one of the four receive channels of IC <NUM> is connected to antenna <NUM>, and three of the four receive channels of IC <NUM> are connected to an antenna array <NUM> of three receive antennas. In particular, the three receive antennas of antenna array <NUM> are designated, from left to right, as RX(S. <NUM>), RX(S. <NUM>), and RX(S. <NUM>), and each antenna is located at a lambda/<NUM> spacing from the next antenna. Moreover, antenna RX(S. <NUM>) is located at the lambda/<NUM> spacing from antenna RX(S. <NUM>), such that the antennas of antenna array <NUM>, antenna <NUM>, and antenna array <NUM> are together configured as a single receive antenna array <NUM> of seven antennas.

IC <NUM> further includes a clock or crystal input to which, in the illustrated example, a crystal is connected. The crystal is utilized by IC <NUM> as an input to derive a LO signal. The LO signal derived from the crystal is utilized internally in IC <NUM> to generate a detection signal to be emitted on transmit antenna <NUM>, and in the down-converting of the detected signals from receive antenna array <NUM> to the baseband frequency. The LO signal is also provided to a LO output (LO_OUT) of IC <NUM>. In this regard, IC <NUM> may be referred to as a "master" IC. IC <NUM> includes a LO input (LO_IN) to receive the LO signal from IC <NUM>. In this regard, IC <NUM> may be referred to as a "slave" IC. The LO signal from LO_IN is utilized internally in IC <NUM> to generate a detection signal to be emitted on transmit antenna <NUM>, and in the down-converting of the detected signals from receive antenna array <NUM> to the baseband frequency. IC <NUM> includes a chirp_start output that is provided to a chirp_start input of IC <NUM> to synchronize the start of the detection signals by IC <NUM> with the start of the detection signals by IC <NUM>.

The crystal is further utilized by IC <NUM> to derive a <NUM> clock for the operation of ADCs in the IC that digitize the down-converted detected signals from antenna array <NUM>. IC <NUM> includes a <NUM> output that is connected to a <NUM> input of IC <NUM> for the operation of ADCs in IC <NUM> that digitize the down-converted detected signals from antenna array <NUM>, and to synchronize the digitization operations of the ADCs in ICs <NUM> and <NUM>. ICs <NUM> and <NUM> each include a high-speed digital communication interface for the communication of the digitized detected signals from respective antenna arrays <NUM> and <NUM> to processing IC <NUM> for processing. ICs <NUM> and <NUM> each include a low-speed digital communication interface that is connected to processing IC <NUM>, whereby processing IC <NUM> communicates with ICs <NUM> and <NUM> to set up the operating parameters of ICs <NUM> and <NUM>, to monitor the operations of ICs <NUM> and <NUM>, and to modify the operating parameters of ICs <NUM> and <NUM>, as needed or desired. Processing IC <NUM> represents a digital signal processing device configured to extract object detection, range, speed, and incident angle information from the digitized detected signals from ICs <NUM> and <NUM>.

In a particular embodiment, ICs <NUM> and <NUM> represent identically specified ICs, such as were each IC is of a same type and part number, or where the ICs are of different types, but are from a common family of components. As such, and similarly to radar system <NUM>, the placement of, and interconnections between ICs <NUM> and <NUM> may be specified, such as by a design rule or a design recommendation. Here, the fact that antenna <NUM> is connected to both the receive channel RX(M. <NUM>) and the receive channel RX(S. <NUM>) results in IC <NUM> receiving two sets of four digitized detected signals: a first set from IC <NUM> (i.e., RX(M. <NUM>)-RX(M. <NUM>)) and as second set from IC <NUM> (i.e., RX(S. <NUM>)-RX(S. However, because the reflected signal received by receive channel RX(M. <NUM>) in IC <NUM> is also the reflected signal received by receive channel RX(S. <NUM>) in IC520, any phase difference between the digitized detected signal from RX(M. <NUM>) and the digitized detected signal from RX(S. <NUM>), as seen by IC <NUM>, will not be understood to represent an actual phase difference in the reflected signals from those channels, but will instead be understood to represent an estimate in the phase difference between the LO signal in IC <NUM> and the LO signal in IC <NUM>.

Here, IC <NUM> operates to detect the phase difference between the digitized detected signal from RX(M. <NUM>) and the digitized detected signal from RX(S. <NUM>), and to compensate for the phase difference in the digital domain, thereby aligning the digitized detected signals from ICs <NUM> and <NUM>. In a particular embodiment, IC <NUM> operates to perform a time domain correlation of the IF signals from RX(M. <NUM>) and RX(S. <NUM>) to yield a time offset between the signals, and utilizes the time offset to correct the sets of values as needed. In another embodiment, IC <NUM> operates to perform a Fast Fourier Transform (FFT) on the IF signals received from ICs <NUM> and <NUM>. The FFT will result in expected frequency peaks associated with the objects in the detection field. The frequencies of the peaks from all of the receive channels RX(M. <NUM>)-RX(M. <NUM>) and RX(S. <NUM>)- RX(S. <NUM>) will be the same. Moreover, the phase offsets between the receive channels RX(M. <NUM>)- RX(M. <NUM>) will each be expected to have a phase offset indicative of the incident angle of the objects detected, as will the phase offsets between the receive channels RX(S. <NUM>)-RX(S. However, because the reflected signal for each object, as received by receive channel RX(M. <NUM>) and by receive channel RX(S. <NUM>) is the same, the phase offsets for each object (i.e., each frequency peak) between receive channels RX(M. <NUM>) and RX(S. <NUM>) is representative of the phase offset in the LO signals in respective ICs <NUM> and <NUM>. Here, IC <NUM> utilizes the phase offset between receive channels RX(M. <NUM>) and RX(S. <NUM>) to correct the sets of values as needed.

In a particular embodiment, radar system <NUM> operates to set up the correction values (i.e., the time offset in the time-domain IF signals, or the phase offset in the frequency-domain signals) in an initial operation, such as during a calibration phase in the operation of radar system <NUM>. The correction values can then be utilized for subsequent signal processing by IC <NUM>. In a variation radar system <NUM> can detect a temperature difference between ICs <NUM> and <NUM>, such as during a normal operation phase in the operation of radar system <NUM>, and can recalculate the correction values when the temperature difference exceeds a threshold value. In another variation, radar system <NUM> can periodically set up the correction values. For example, IC <NUM> can be configured to recalculate the correction values at a predetermined rate, such as every second, every <NUM> milliseconds, or at another predetermined rate as needed or desired. This embodiment may provide advantages in that, where the signal processing resources of IC <NUM> are sparse, the additional processing needed to calculate the correction values can be reduced. In another embodiment, radar system <NUM> operates to continuously calculate the correction values. Here, where the signal processing resources of IC <NUM> are more abundant, the additional processing needed to continuously calculate the correction values may not present an excessive burden on the IC.

It will be understood that the LO signal phase offset between multiple ICs may be estimated and corrected as needed or desired. For example, where a radar system includes three ICs, each with four receive channels, then a single antenna that is shared between the first and second ICs can provide an estimate of the LO phase offset between the first and second ICs, and a single antenna that is shared between the second and third ICs can provide an estimate of the LO phase offset between the second and third ICs. The LO phase offsets between additional ICs can similarly be estimated and corrected as needed or desired. Note that the theoretical virtual aperture of radar systems <NUM> and <NUM> will be equal to an equivalent SIMO radar system with <NUM> antennas (i.e., <NUM> (transmit antennas) x <NUM> (receive antennas) = <NUM>). In contrast, the theoretical virtual aperture of radar system <NUM> will be equal to an equivalent SIMO radar system with <NUM> antennas (i.e., <NUM> (transmit antennas) x <NUM> (receive antennas) = <NUM>). As such, the theoretical angular resolution of radar systems <NUM> and <NUM> is greater than the theoretical angular resolution of radar system <NUM>. However, in practice, the more accurate measure of the LO signal phase differences between ICs <NUM> and <NUM>, as provided by radar system <NUM> may offset any loss in resolution from the smaller theoretical virtual aperture.

<FIG> illustrates a method for local oscillator (LO) drift estimation and compensation in a cascaded radar system, starting at block <NUM>. A single antenna is connected to the receiver inputs of two receiver ICs in block <NUM>. For example, where each receiver IC includes four receiver channels, an array of seven antennas can be provided that are spaced with spacing of lambda/<NUM> or less. Here three of the receiver channels on each receiver IC can be connected to an associated antenna. The fourth receiver channel of each receiver IC can be connected to a shared antenna. Typically, a middle antenna of the array of seven antennas will be the shared antenna.

A reflected FMCW chirp is received on the shared antenna in block <NUM>. Here, the cascaded radar system can include one or more transmit channels, either on one or more separate transmit IC, or on one or both of the first and second receiver ICs. The transmit channels can emit encoded FMCW chirps that can be reflected off of objects in a detection space of the radar system. The reflected FMCW chirps can be detected by the shared antenna.

The FMCW chirp received by the first receiver IC is mixed with a first LO signal to obtain a first IF signal, and the first IF signal is digitized in block <NUM>. For example, the first receiver IC can generate the first LO signal, or can receive the first LO signal from another external source. The resulting IF signal will have a phase shift that is related to the phase shift of the first LO signal. The first IF signal can be digitized using an ADC.

The FMCW chirp received by the second receiver IC is mixed with a second LO signal to obtain a second IF signal, and the second IF signal is digitized in block <NUM>. For example, the second receiver IC can generate the second LO signal, or can receive the second LO signal from another external source. The resulting IF signal will have a phase shift that is related to the phase shift of the second LO signal. The first and second LO signals may be based upon a common LO signal, for example where one of the receiver ICs generates the common LO signal,and provides the common LO signal to the other receiver IC. The second IF signal can be digitized using an ADC.

The first and second digitized IF signals are received in block <NUM>. For example, a digital signal processing IC can receive the digitized IF signals from the first and second receiver ICs.

A phase difference between the first and second digitized IF signals is determined in block <NUM>. For example, the digital signal processing IC can determine the phase difference in the time-domain or in the frequency-domain, as needed or desired.

The phase difference is corrected in one of the receiver outputs of one of the first and second ICs in block <NUM>, and the method ends in block <NUM>.

<FIG> illustrates an automobile <NUM> that includes one or more radar system <NUM>. Automobile <NUM> represents any kind of vehicle that utilizes a radar system for object detecting objects, and providing range, speed, and incident angle information related to the object. An example of automobile <NUM> may include a car, a self-driving car, a truck, a van, a motorcycle, a utility vehicle, a boat, a ship, a drone, an aircraft, an emergency services vehicle, or the like. Radar system <NUM> may be in communication with an automatic braking system, an adaptive cruise control system, a collision avoidance system, or another system of automobile <NUM>, as needed or desired to affect the operation of the automobile. Radar system <NUM> may be similar to the radar systems described herein, an may operate in accordance with the teaching disclosed herein.

Claim 1:
A frequency modulated continuous wave, FMCW radar system, comprising:
an antenna array (<NUM>) including C antennas, where C = A + B - <NUM>, and where A, B, and C are integers greater than one;
a first integrated circuit (IC) device (<NUM>) including A first sensor inputs, each first sensor input coupled to a first A (<NUM>, <NUM>) of the antennas, the first IC device configured to receive on each first sensor input an associated first reflected signal, to mix the first reflected signals to associated first baseband signals based upon a first local oscillator, LO signal, and to output the first baseband signals, wherein the first LO signal has a first phase shift;
a second IC device (<NUM>) including B second sensor inputs, each second sensor input coupled to a last B (<NUM>, <NUM>) of the antennas such that a common one of the first sensor inputs and a common one of the second sensor inputs are both coupled to a common antenna (<NUM>), the second IC device configured to receive on each second sensor input an associated second reflected signal, to mix the second reflected signals to associated second baseband signals based upon a second local oscillator, LO signal, and to output the second baseband signals, wherein the second LO signal has a second phase shift, wherein the first and second LO signals are based upon a common LO signal, and wherein a common first baseband signal is associated with the common first sensor input and a common second baseband signal is associated with the common second sensor input; and
a processor (<NUM>) configured to receive the first baseband signals and the second baseband signals, to determine a difference between the first phase shift and the second phase shift based upon the common first baseband signal and the common second baseband signal, and to correct at least one of the first baseband signals and the second baseband signals based upon the difference between the first phase shift and the second phase shift.