Patent Description:
When a file system stores a file in a storage device, the file system stores file data and metadata in the storage device. The file data includes the contents of a file to be stored by a user application, and the metadata includes attributes of the file and the location of a block in which the file data is stored. In addition, when the file system reads a file from the storage device, the stored file data and metadata must be read from the storage device.

Meanwhile, the file system may support a checkpointing function to support sudden power-off of the storage device. Using the checkpointing function, the file system may quickly help guarantee, or more quickly help safeguard consistency, when power is applied again after sudden power-off.

Some example embodiments provide a storage device which performs checkpointing by remapping a flash mapping table. In one aspect, a storage system comprising a storage device and a host is provided in accordance with claim <NUM>. Further aspects and preferred embodiments are set out in claim <NUM> et seq.

Some example embodiments also provide a storage system which comprises a storage device performing checkpointing by remapping a flash mapping table and/or a method of operating the storage system.

However, example embodiments are not restricted to the one set forth herein. The above and other aspects of inventive concepts will become more apparent to one of ordinary skill in the art to which example embodiments pertains by referencing the detailed description of inventive concepts given below.

According to some example embodiments, a storage system includes a storage device comprising a nonvolatile memory, the nonvolatile memory configured to store data at physical addresses, the physical addresses including a first physical address and a second physical address, and a host comprising a host processing circuitry configured to (A) insert a first journal logical address and a first target logical address into a journal mapping table, to (B) generate a journaling command by arranging first journal data in a log page in sectors, the sectors addressed to the first target logical address, and to (C) generate a checkpointing command comprising the first target logical address and the first journal logical address. The storage device includes a flash mapping table configured to store a first mapping state in which the first journal logical address maps to the first physical address, and the first target logical address maps to the second physical address, and a storage device processing circuitry configured to (D) write the first journal data arranged in sectors to an area of the nonvolatile memory, which is addressed to the first physical address corresponding to the first journal logical address according to the first mapping state, the writing in response to the journaling command, and to (E) change the first mapping state of the flash mapping table to a second mapping state, in which the first target logical address is remapped to the first physical address, the changing in response to the checkpointing command.

According to some example embodiments, a method of operating a storage system includes inserting a first journal logical address, a first target logical address, a second journal logical address, and a second target logical address into a journal mapping table in a host, generating a log page by arranging first journal data and second journal data in sectors, the sectors addressed to the first target logical address and the second target logical address, writing the first journal data included in the log page to an area of a nonvolatile memory which is addressed to a first physical address that is mapped to the first journal logical address according to a flash mapping table, writing the second journal data included in the log page to an area of the nonvolatile memory which is addressed to a second physical address that is mapped to the second journal logical address according to the flash mapping table, generating a checkpointing command which comprises the first target logical address, the first journal logical address, the second target logical address, and the second journal logical address, and in response to the checkpointing command, updating the flash mapping table by remapping the first physical address to the first target logical address and remapping the second physical address to the second target logical address.

According to some example embodiments, a storage device includes a nonvolatile memory configured to store data at physical addresses, the physical addresses including a first physical address and a second physical address, and a memory controller circuitry comprising a flash mapping table storing a first mapping state in which a first journal logical address is mapped to the first physical address, and a first target logical address is mapped to the second physical address. The nonvolatile memory is configured to receive a log page comprising first journal data and to write the first journal data to the first physical address which corresponds to the first journal logical address according to the first mapping state stored in the flash mapping table, and the memory controller circuitry is configured to receive a checkpointing command comprising the first journal logical address and the first target logical address and to change the first mapping state of the flash mapping table to a second mapping table in which the first target logical address is remapped to the first physical address, the changing being in response to the checkpointing command.

These and/or other aspects will become apparent and more readily appreciated from the following description of some example embodiments, taken in conjunction with the accompanying drawings in which:.

<FIG> is a block diagram of a storage system according to some example embodiments.

Referring to <FIG>, the storage system according to some example embodiments may include a host <NUM> and a storage device <NUM>.

The host <NUM> may include a storage engine <NUM>. The storage engine <NUM> may generate a command according to a query for reading data from the storage device <NUM> and/or writing data to the storage device <NUM>. The host <NUM> may provide the command to the storage device <NUM>.

The storage device <NUM> may include a memory controller <NUM>, a buffer memory <NUM>, and a nonvolatile memory <NUM>.

The storage device <NUM> may include storage media for storing data according a request from the host <NUM>. The storage device <NUM> may include, for example, at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. When the storage device <NUM> is or includes an SSD, the storage device <NUM> may be or include a device that conforms to a nonvolatile memory express (NVMe) standard. When the storage device <NUM> is or includes an embedded memory or an external memory, the storage device <NUM> may be a device that conforms to a universal flash storage (UFS) or embedded multimedia card (eMMC) standard. Each of the host <NUM> and the storage device <NUM> may generate and/or transmit a packet according to an employed standard protocol.

The memory controller <NUM> may be connected, e.g. connected by wires and/or wirelessly connected, to the host <NUM> and the nonvolatile memory <NUM>. The memory controller <NUM> may be configured to access the nonvolatile memory <NUM> in response to the command of the host <NUM>.

The buffer memory <NUM> may temporarily store data to be recorded in the nonvolatile memory <NUM> or data read from the nonvolatile memory <NUM>. The buffer memory <NUM> may be provided outside the memory controller <NUM> and/or be provided in the memory controller <NUM>. The buffer memory <NUM> may be or include a volatile memory serving as a buffer, but may also be or include a nonvolatile memory.

The nonvolatile memory <NUM> may be or include, for example, a flash memory. The flash memory may include a 2D NAND memory array and/or a 3D (or vertical) NAND (VNAND) memory array. Alternatively or additionally, the storage device <NUM> may include various other types of nonvolatile memories. For example, the storage device <NUM> may include at least one of a magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, and various other types of memories.

<FIG> is a block diagram of the host <NUM> of <FIG>.

Referring to <FIG>, the host <NUM> may include a host processor <NUM>, a host memory <NUM>, a ROM <NUM>, and a host interface <NUM>. The host processor <NUM>, the host memory <NUM>, and the ROM <NUM> may be electrically connected to each other through a bus <NUM>.

The host processor <NUM> may control the overall operation of the host <NUM>. The host processor <NUM> may drive an operating system (OS) <NUM>, an application <NUM> and a storage engine <NUM> for driving the host <NUM>.

The host memory <NUM> may be used as a driving memory for driving software or firmware. Application programs and/or data to be processed by the host processor <NUM> may be loaded into the host memory <NUM>. For example, the host memory <NUM> may be loaded with the OS <NUM>, the application <NUM>, and the storage engine <NUM>.

The ROM <NUM> may store code data required for or used during initial booting.

The host interface <NUM> may provide an interface between the host <NUM> and the storage device <NUM>. For example, the host <NUM> and the storage device <NUM> may be connected through at least one of various standardized interfaces. The standardized interfaces may include various interfaces such as at least one of advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCI-E), universal serial bus (USB), IEEE <NUM>, and a card interface.

<FIG> is a block diagram of the memory controller <NUM> of <FIG>.

Referring to <FIG>, the memory controller <NUM> may include at least one processor <NUM>, a working memory <NUM>, a host interface <NUM>, a buffer manager <NUM>, and a nonvolatile memory interface <NUM>. The at least one processor <NUM>, the working memory <NUM>, and the buffer manager <NUM> may be electrically connected to each other through a bus <NUM>.

The processor <NUM> may include at least one of a central processing unit (CPU), a controller, or an application specific integrated circuit (ASIC). The processor <NUM> may control the overall operation of the memory controller <NUM>. The processor <NUM> may control the memory controller <NUM> by driving firmware loaded into the working memory <NUM>.

The working memory <NUM> may be loaded with software and/or firmware for controlling the memory controller <NUM>. For example, a flash translation layer (FTL) may be loaded into and driven in the working memory <NUM>. The working memory <NUM> may be implemented as at least one of a cache memory, a DRAM, an SRAM, or a flash memory.

The FTL may perform various functions such as at least one of address mapping, wear-leveling, and garbage collection.

The address mapping operation is or includes an operation of converting a logical address received from the host <NUM> into a physical address used to actually or physically store data in the nonvolatile memory <NUM>. The FTL may convert a logical address into a physical address using a flash mapping table <NUM> in the working memory <NUM> and may provide the physical address to the nonvolatile memory <NUM>.

The wear-leveling is or includes a technology for preventing or reducing the amount of excessive deterioration of a specific block by allowing blocks in the nonvolatile memory <NUM> to be used uniformly, and may be implemented through, e.g., a firmware technology that balances erase counts of physical blocks. The garbage collection is or includes a technology for securing usable capacity in the nonvolatile memory <NUM> by copying valid data of a block to a new block and then erasing the existing block.

A storage device checkpointing engine <NUM> may write journal data received from the host <NUM> to the nonvolatile memory <NUM>. The checkpointing engine <NUM> may perform a checkpointing operation in response to a checkpoint command received from the host <NUM>. The storage device checkpointing engine <NUM> may perform the checkpointing operation by updating the flash mapping table <NUM>. This will be described in detail below with reference to <FIG>. Although the storage device checkpointing engine <NUM> is illustrated as being a component of the working memory <NUM>, example embodiments are not limited thereto. For example, functions performed by the storage device checkpointing engine <NUM> may be performed by other components within the memory controller <NUM> or other components within the storage device <NUM>.

The host interface <NUM> may transmit and receive packets to and from the host <NUM>. A packet transmitted from the host <NUM> to the host interface <NUM> may include a command or data to be recorded in the nonvolatile memory <NUM>. A packet transmitted from the host interface <NUM> to the host <NUM> may include a response to a command or data read from the nonvolatile memory <NUM>. The host interface <NUM> may provide an interface between the host <NUM> and the memory controller <NUM>. For example, the host <NUM> and the memory controller <NUM> may be connected through at least one of various standardized interfaces. The standardized interfaces may include various interfaces such as the host interface <NUM> described above in <FIG>.

The buffer manager <NUM> may provide an interface between the memory controller <NUM> and the buffer memory <NUM>. Data to be recorded in the nonvolatile memory <NUM> and/or data read from the nonvolatile memory <NUM> may be temporarily stored in the buffer memory <NUM> through the buffer manager <NUM>. Although the buffer manager <NUM> is illustrated as being separate from other components of the memory controller <NUM>, example embodiments are not limited thereto. For example, functions performed by the buffer manager <NUM> may be performed by other components within the memory controller <NUM> and/or other components within the storage device <NUM>.

The nonvolatile memory interface <NUM> may transmit data to be recorded in the nonvolatile memory <NUM> to the nonvolatile memory <NUM> and/or may receive data read from the nonvolatile memory <NUM>. The nonvolatile memory interface <NUM> may be implemented to comply with a standard protocol such as Toggle and/or ONFI.

<FIG> is a block diagram of the nonvolatile memory <NUM> of <FIG>. Referring to <FIG>, the nonvolatile memory <NUM> may include a control logic circuit <NUM>, a memory cell array <NUM>, a page buffer unit <NUM>, a voltage generator <NUM>, and a row decoder <NUM>. Although not illustrated in <FIG>, the nonvolatile memory <NUM> may further include a memory interface circuit <NUM> and may further include at least one of a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

The control logic circuit <NUM> may generally control various operations in the nonvolatile memory <NUM>. The control logic circuit <NUM> may output various control signals in response to a command CMD and/or an address ADDR from the memory interface circuit <NUM>. For example, the control logic circuit <NUM> may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array <NUM> may include a plurality of memory blocks BLK1 through BLKz (where z is a positive integer), and each of the memory blocks BLK1 through BLKz may include a plurality of memory cells. Each of the plurality of memory cells may store at least one bit. The memory cell array <NUM> may be connected to the page buffer unit <NUM> through bit lines BL and may be connected to the row decoder <NUM> through word lines WL, string select lines SSL and ground select lines GSL.

In some example embodiments, the memory cell array <NUM> may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each of the NAND strings may include memory cells respectively connected to word lines stacked vertically on a substrate. Alternatively or additionally, in some example embodiments, the memory cell array <NUM> may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings disposed along row and column directions.

The page buffer unit <NUM> may include a plurality of page buffers PB1 through PBn (where n is an integer of <NUM> or more), and the page buffers PB <NUM> through PBn may be connected to the memory cells through the bit lines BL, respectively. The page buffer unit <NUM> may select at least one of the bit lines BL in response to the column address Y-ADDR. The page buffer unit <NUM> may operate as a program or write driver and/or a sense amplifier according to an operating mode. For example, during a write/program operation, the page buffer unit <NUM> may apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer unit <NUM> may sense data stored in a memory cell by sensing a current or voltage of a selected bit line. Although the page buffer unit <NUM> is illustrated as being separate from the nonvolatile memory <NUM>, example embodiments are not limited thereto. For example, functions performed by the page buffer unit <NUM> may be performed by other components within the nonvolatile memory <NUM>, or may be performed by components separate from the nonvolatile memory <NUM>.

The voltage generator <NUM> may generate various types of voltages such as various types of DC voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator <NUM> may generate at least one of a program voltage, a read voltage, a program verify voltage, an erase voltage, or the like as a word line voltage VWL.

The row decoder <NUM> may select one of the word lines WL in response to the row address X-ADDR, and may select one of the string select lines SSL. For example, the row decoder <NUM> may apply a program voltage and a program verify voltage to a selected word line during a program operation and may apply a read voltage to a selected word line during a read operation.

<FIG> illustrates a 3D V-NAND structure applicable to the nonvolatile memory <NUM> of <FIG>. When the nonvolatile memory <NUM> of <FIG> is implemented as a 3D V-NAND type flash memory, each of the memory blocks BLK1 through BLKz constituting/included in the memory cell array <NUM> of the nonvolatile memory <NUM> can be expressed as an equivalent circuit as illustrated in <FIG>.

A memory block BLKi illustrated in <FIG> is or includes a 3D memory block formed in a 3D structure on a substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to a surface of the substrate.

Referring to <FIG>, the memory block BLKi may include a plurality of memory NAND strings NS11 through NS33 connected between bit lines BL1 through BL3 and a common source line CSL. Each of the memory NAND strings NS11 through NS33 may include a string select transistor SST, a plurality of memory cells MC1 through MC8, and a ground select transistor GST. Although each of the memory NAND strings NS11 through NS33 includes eight memory cells MC1 through MC8 in <FIG>, inventive concepts are not limited thereto.

The string select transistor SST may be connected to a corresponding string select line SSL1, SSL2 or SSL3. The memory cells MC1 through MC8 may be connected to corresponding gate lines GTL1 through GTL8, respectively. The gate lines GTL1 through GTL8 may be or correspond to word lines, and some of the gate lines GTL1 through GTL8 may be or correspond to dummy word lines (e.g., to dummy word lines that are not electrically active during operation of the nonvolatile memory <NUM>). The ground select transistor GST may be connected to a corresponding ground select line GSL1, GSL2 or GSL3. The string select transistor SST may be connected to a corresponding bit line BL1, BL2 or BL3, and the ground select transistor GST may be connected to the common source line CSL.

Word lines (e.g., WL1) at the same level may be connected in common, and the ground select lines GSL1 through GSL3 and the string select lines SSL1 through SL3 may be separated from each other. Although the memory block BLKi is connected to eight gate lines GTL1 through GTL8 and three bit lines BL1 through BL3 in <FIG>, the inventive concept is not limited thereto.

<FIG> illustrates a BVNAND structure applicable to the nonvolatile memory <NUM> of <FIG>. Referring to <FIG>, the nonvolatile memory <NUM> may have a chip-to-chip (C2C) structure. The C2C structure may be formed by manufacturing (or fabricating) an upper chip including a cell area CELL on a first wafer, manufacturing (or fabricating) a lower chip including a peripheral circuit area PERI on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip using a bonding method such as a wafer-bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metals are made of or include copper (Cu), the bonding method may be a Cu-Cu bonding method. The bonding metals may also be made of or include aluminum and/or tungsten.

Each of the periphery circuit area PERI and the cell area CELL of the nonvolatile memory <NUM> according some example embodiments may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit area PERI may include a first substrate <NUM>, an interlayer insulating layer <NUM>, a plurality of circuit elements 1220a through 1220c formed on the first substrate <NUM>, first metal layers 1230a through 1230c respectively connected to the circuit elements 1220a through 1220c, and second metal layers 1240a through 1240c formed on the first metal layers 1230a through 1230c. In some example embodiments, the first metal layers 1230a through 1230c may be made of or include tungsten having a relatively high resistance, and the second metal layers 1240a through 1240c may be made of or include copper having a relatively low resistance.

Although only the first metal layers 1230a through 1230c and the second metal layers 1240a through 1240c are illustrated and described herein, inventive concepts are not limited thereto. One or more metal layers may also be further formed on the second metal layers 1240a through 1240c. At least some of one or more memory layers formed on the second metal layers 1240a through 1240c may be made of or include aluminum having a lower resistance than copper that forms the second metal layers 1240a through 1240c.

The interlayer insulating layer <NUM> may be disposed on the first substrate <NUM> to cover the circuit elements 1220a through 1220c, the first metal layers 1230a through 1230c and the second metal layers 1240a through 1240c and may include an insulating material such as silicon oxide or silicon nitride.

Lower bonding metals 1271b and 1272b may be formed on the second metal layers 1240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit area PERI may be electrically connected to upper bonding metals 1371b and 1372b of the cell area CELL by a bonding method, and the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b may be made of aluminum, copper or tungsten.

The cell area CELL may provide at least one memory block. The cell area CELL may include a second substrate <NUM> and a common source line <NUM> (corresponding to CSL of <FIG>). A plurality of word lines <NUM> through <NUM> (<NUM>, corresponding to GTL1 through GTL8 of <FIG>) may be stacked on the second substrate <NUM> along a third direction z perpendicular to an upper surface of the second substrate <NUM>. String select lines and a ground select line may be disposed on and under the word lines <NUM>, and the word lines <NUM> may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, channel structures CH may extend in the direction perpendicular to the upper surface of the second substrate <NUM> to penetrate the word lines <NUM>, the string select lines, and the ground select line. Each of the channel structures CH may include a data storage layer, a channel layer and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer 1350c and a second metal layer 1360c. For example, the first metal layer 1350c may be or correspond to or include a bit line contact, and the second metal layer 1360c may be a bit line or correspond to or include (corresponding to BL1 through BL3 of <FIG>). In some example embodiments, the bit line 1360c may extend along a second direction y parallel to the upper surface of the second substrate <NUM>.

In some example embodiments illustrated in <FIG>, an area where the channel structures CH and the bit lines 1360c are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line 1360c may be electrically connected to the circuit elements 1220c, which provide a page buffer <NUM> in the peripheral circuit area PERI. For example, the bit line 1360c may be connected to upper bonding metals 1371c and 1372c in the cell area CELL, and the upper bonding metals 1371c and 1372c may be connected to lower bonding metals 1271c and 1272c connected to the circuit elements 1220c of the page buffer <NUM>.

In the word line bonding area WLBA, the word lines <NUM> may extend along a first direction x parallel to the upper surface of the second substrate <NUM> and may be connected to a plurality of cell contact plugs <NUM> through <NUM> (<NUM>). The word lines <NUM> and the cell contact plugs <NUM> may be connected to each other by pads provided by at least some of the word lines <NUM>, which extend to different lengths along the first direction x. First metal layers 1350b and second metal layers 1360b may be sequentially connected to the cell contact plugs <NUM> connected to the word lines <NUM>. In the word line bonding area WLBA, the cell contact plugs <NUM> may be connected to the peripheral circuit area PERI through the upper bonding metals 1371b and 1372b of the cell area CELL and the lower bonding metals 1271b and 1272b of the peripheral circuit area PERI.

The cell contact plugs <NUM> may be electrically connected to the circuit elements 1220b which provide a row decoder <NUM> in the peripheral circuit area PERI. In some example embodiments, an operating voltage (e.g. a DC operating voltage) of the circuit elements 1220b which provide the row decoder <NUM> may be different from an operating voltage (e.g. a DC operating voltage) of the circuit elements 1220c which provide the page buffer <NUM>. For example, the operating voltage of the circuit elements 1220c which provide the page buffer <NUM> may be greater than, or greater in magnitude than, the operating voltage of the circuit elements 1220b which provide the row decoder <NUM>.

Common source line contact plugs <NUM> may be disposed in the external pad bonding area PA. The common source line contact plugs <NUM> may be made of or include a conductive material such as a metal, a metal compound or polysilicon such as doped polysilicon and may be electrically connected to the common source line <NUM>. First metal layers 1350a and second metal layers 1360a may be sequentially stacked on the common source line contact plugs <NUM>. For example, an area where the common source line contact plugs <NUM>, the first metal layers 1350a, and the second metal layers 1360a are disposed may be defined as the external pad bonding area PA.

Input/output pads <NUM> and <NUM> may be disposed in the external pad bonding area PA. A lower insulating layer <NUM> may be formed under the first substrate <NUM> to cover a lower surface of the first substrate <NUM>, and a first input/output pad <NUM> may be formed on the lower insulating layer <NUM>. The first input/output pad <NUM> may be connected to at least one of the circuit elements 1220a through 1220c disposed in the peripheral circuit area PERI through a first input/output contact plug <NUM>, and may be separated from the first substrate <NUM> by the lower insulating layer <NUM>. Alternatively or additionally, a side insulating layer may be disposed between the first input/output contact plug <NUM> and the first substrate <NUM> to electrically separate the first input/output contact plug <NUM> and the first substrate <NUM>.

An upper insulating layer <NUM> may be formed on the second substrate <NUM> to cover the upper surface of the second substrate <NUM>, and a second input/output pad <NUM> may be disposed on the upper insulating layer <NUM>. The second input/output pad <NUM> may be connected to at least one of the circuit elements 1220a through 1220c disposed in the peripheral circuit area PERI through a second input/output contact plug <NUM>.

According some example embodiments, the second substrate <NUM> and the common source line <NUM> may not be disposed in an area where the second input/output contact plug <NUM> is disposed. Alternatively or additionally the second input/output pad <NUM> may not overlap the word lines <NUM> in the third direction z. Referring to <FIG>, the second input/output contact plug <NUM> may be separated from the second substrate <NUM> in a direction parallel to the upper surface of the second substrate <NUM> and may be connected to the second input/output pad <NUM> by penetrating an interlayer insulating layer <NUM> of the cell area CELL.

According some example embodiments, the first input/output pad <NUM> and the second input/output pad <NUM> may be selectively formed. For example, the nonvolatile memory <NUM> according to some example embodiments may include only the first input/output pad <NUM> disposed on the first substrate <NUM> or may include only the second input/output pad <NUM> disposed on the second substrate <NUM>. Alternatively or additionally, the nonvolatile memory <NUM> may include both the first input/output pad <NUM> and the second input/output pad <NUM>.

In each of the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, a metal pattern of an uppermost metal layer may exist as a dummy pattern, or the upper metal layer may be empty.

In the external pad bonding area PA of the nonvolatile memory <NUM> according to some example embodiments, lower metal patterns 1272a and 1273a having the same shape as upper metal patterns 1372a of the cell area CELL may be formed in an uppermost metal layer of the peripheral circuit area PERI to correspond to the upper metal patterns 1372a formed in an uppermost metal layer of the cell area CELL. The lower metal patterns 1272a and 1273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to separate contacts in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, upper metal patterns having the same shape as lower metal patterns of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL to correspond to the lower metal patterns formed in the uppermost metal layer of the peripheral circuit area PERI.

The lower bonding metals 1271b and 1272b may be formed on the second metal layers 1240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 1371b and 1372b of the cell area CELL by a bonding method.

Alternatively or additionally, in the bit line bonding area BLBA, an upper metal pattern <NUM> having the same shape as a lower metal pattern <NUM> and <NUM> of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL to correspond to the lower metal pattern <NUM> and <NUM> formed in the uppermost metal layer of the peripheral circuit area PERI. A contact may not be formed on the upper metal pattern <NUM> formed in the uppermost metal layer of the cell area CELL.

<FIG> are diagrams for explaining the storage system according to some example embodiments.

Referring to <FIG>, in some example embodiments, the application <NUM> may provide a query to the storage engine <NUM> within the host <NUM>. The query may be or include, for example, a put query including data to be written into the storage device <NUM> and a logical address and/or a get query including a logical address to be read from the storage device <NUM>. The application <NUM> may be or include, for example, a key-value store database (DB). The key-value store DB may be, for example, at least one of a Rocks DB, a Level DB, or a Mongo DB. In one example, a host processing circuitry may be configured to generate an input query comprising first journal data and a first key corresponding to the first journal data; to map the first key to the first target logical address; and to generate the log page in response to the input query. The host processing circuitry may be configured to generate an input query as a key-value structure in which a value is stored in a key corresponding to the value.

The storage engine <NUM> within the host <NUM> may include a query interface layer <NUM>, a key-value mapping layer <NUM>, a journaling layer <NUM>, and a block interface layer <NUM>. The query interface layer <NUM> may receive a query from the application <NUM>. When the application <NUM> is a key-value store, the storage engine <NUM> may receive a query including a key-value pair from the application <NUM>, instead of data and a logical address. The key-mapping layer <NUM> may convert a key-value pair into a logical address and a value. Although <FIG> illustrates that each of the components of the storage engine <NUM> within the host <NUM> are separate, example embodiments are not limited thereto. For example, some functions of the query interface layer <NUM>, the key-value mapping layer <NUM>, the journaling layer <NUM>, and the block interface layer <NUM> that are described herein may be performed by others of the query interface layer <NUM>, the key-value mapping layer <NUM>, the journaling layer <NUM>, and the block interface layer <NUM>.

The journaling layer <NUM> includes a journal manager <NUM> and a host checkpointing manager <NUM>. When receiving a query from the application <NUM>, the journal manager <NUM> may write a pair of a target logical address and a journal logical address included in the query to a journal mapping table <NUM>. The journal manager <NUM> may temporarily store journal data included in a query in a journal buffer <NUM>. When queries provided from the application <NUM> gather to generate a transaction, a block aligner <NUM> may generate a journaling command Request. The transaction is or includes a unit of work in which the journal manager <NUM> can simultaneously perform a plurality of queries. Although as described herein the journal manager <NUM> performs different functions from that of the host checkpointing manager <NUM>, example embodiments are not limited thereto. For example, some of the functions described as being performed by the journal manager <NUM> may be performed by other processing circuitry such as the host checkpointing manager <NUM>, and vice-versa. A host processing circuitry may perform the actions of both the host checkpointing manager <NUM> and the journal manager <NUM>.

Referring to <FIG>, a transaction <NUM> may include, e.g. may consist of, a header, metadata, data, and a tail. The header may indicate a start point of the transaction <NUM>, and the tail may indicate an end point of the transaction <NUM>. The metadata may include attributes of journal data DATA and a logical address at which the journal data DATA is stored. The journal manager <NUM> arranges journal data DATA included in the transaction <NUM> in a log page Log Page <NUM> in units of sectors, e.g. of sectors having a fixed length. The journal manager <NUM> may generate the journaling command Request including the log page Log Page <NUM>. For example, when the size of each of first journal data DATA A and second journal data DATA B included in the transaction <NUM> is less than the size of each sector and the size of third journal data DATA C is greater than the size of each sector, the first journal data DATA A may be arranged at a start point <NUM> of a first sector of the log page Log Page <NUM>, the second journal data DATA B may be arranged at a start point <NUM> of a second sector of the log page, and the third journal data DATA C may be arranged at a start point <NUM> of a third sector of the log page. In one example, a host processing circuitry may be configured to generate an input query comprising first journal data and a first target logical address, and a journal manager may generate a log page in response to the input query.

Referring to <FIG>, the journal data DATA included in the transaction <NUM> may be arranged at a start point of each sector and may be arranged in a plurality of log pages Log Page <NUM> through Log Page <NUM> according to the size of the journal data DATA.

Referring to <FIG>, the size of each of the first and second journal data DATA A and DATA B may be less than half the size of each sector. In this case, the first and second journal data DATA A and DATA B may be arranged in one sector. The first journal data DATA A may be arranged at the start point <NUM> of the first sector of the log page Log Page <NUM>, and the second journal data DATA B may be arranged at a <NUM>/<NUM> point <NUM> of the first sector. In one example, a size of the first journal data may not be a multiple of a size of each sector. In one example, the first journal data may have a larger size than each sector, and the host processing circuitry may be configured to arrange the first journal data at a start point of the first sector. In one example, the host processing circuitry may be configured to arrange the second journal data at a start point of the second sector. In one example, the second journal data may have a larger size than each of the first through third sectors, and the host processing circuitry may be configured to arrange the second journal data in the second sector and the third sector. In one example, the first journal data may have a size larger than the size of each of the first through third sectors and smaller than twice the size of each of the first through third sectors, and the second journal data may have a larger size than each of the first through third sectors, and the host processing circuitry may be configured to generate the log page arranging the first journal data in the first sector and the second sector and arranging the second journal data in the third sector.

One sector may be divided into <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM> and <NUM>/<NUM> points of the size of the sector, and the journal data DATA may be arranged at the <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, and <NUM>/<NUM> points in the sector according to the size of the journal data DATA. Accordingly, since the journal data DATA is arranged in the log page Log Page <NUM> in units of sectors, an amount of an empty area in which data are not arranged between the journal data DATA may be reduced, and performance of the storage device <NUM> may be improved.

For example, the storage device <NUM> according to some example embodiments may write data in units of pages, and the block aligner <NUM> may provide journal data in units of log pages. Therefore, write amplification of the storage device <NUM> can be improved. Alternatively or additionally, the size of data addressed to one logical address is a sector unit, and the flash mapping table <NUM> maps a physical address to a logical address. Therefore, since the block aligner <NUM> arranges journal data at a start point of a sector in a log page, the efficiency of remapping a logical address to a physical address in an area of a nonvolatile memory to which the journal data has been written can be increased. Alternatively or additionally, the written journal data can be reused as it is during journaling.

When the application <NUM> is a key-value store, e.g. an application for storing key-value pairs, the storage engine <NUM> may receive a query including a key-value pair. Since key-value pairs have various sizes, key-value pairs not usually arranged in units of sectors. In particular, when a small key-value pair is written to the storage device <NUM>, since the storage device <NUM> is written in units of pages, the write amplification of the storage device <NUM> may be increased. Alternatively or additionally, frequent update of key-value pairs may increase generation of invalid pages in the storage device <NUM> and/or may increase the frequency of garbage collection.

However, in some example embodiments, key-value pairs are arranged in a log page in units of sectors and journaled accordingly. Therefore, the load of the storage device <NUM> can be reduced. Alternatively or additionally, since key-value pairs are arranged in units of sectors, e.g. of sectors having a fixed or constant size, a physical address indicating an area to which a key-value pair has been written in the nonvolatile memory <NUM> may be mapped to a target logical address by the flash mapping table <NUM>. Therefore, journal data of the key-value pair can be reused during checkpointing.

Referring back to <FIG>, the host checkpointing manager <NUM> may include a checkpoint scheduler <NUM> and a checkpointing command queue <NUM>. The checkpoint scheduler <NUM> may generate a checkpointing command CoW Command by receiving a pair of a journal logical address and a target logical address from the journal mapping table <NUM>. The checkpoint scheduler <NUM> may generate the checkpointing command CoW Command for each pair of the journal logical address and the target logical address, and the checkpointing command queue <NUM> may provide a plurality of checkpointing commands CoW Command as one set to the storage device <NUM>. For example, when data cannot be written to the journal mapping table <NUM>, the checkpoint scheduler <NUM> may generate the checkpointing command CoW Command according to a specific (or, alternatively, predetermined) cycle and/or when receiving a checkpointing query from the application <NUM>. This will be described in detail below with reference to <FIG>. Although as described herein the checkpoint scheduler <NUM> performs different functions from that of the checkpointing command queue <NUM>, example embodiments are not limited thereto. For example, some of the functions described as being performed by the journal manager <NUM> may be performed by other processing circuitry such as the host checkpointing manager <NUM>, and vice-versa. In one example, host processing circuitry may be configured to generate a checkpointing command in response to an insertable capacity of a journal mapping table being equal to or greater than a set capacity value or according to a set cycle.

Within the storage device <NUM>, the storage device checkpointing engine <NUM> may include a log manager <NUM>, a checkpoint processor <NUM>, and a garbage collection checker <NUM>. Although as described herein the log manager <NUM>, the checkpoint processor <NUM>, and the garbage collection checker <NUM> perform different functions, example embodiments are not limited thereto. For example, some of the functions described as being performed by one of the components of the storage device checkpointing engine <NUM> may be performed by other components of the storage device checkpointing engine <NUM>. A storage device processing circuitry may perform some or all of the actions described with reference to the log manager <NUM>, the checkpoint processor <NUM>, and the garbage collection checker <NUM> perform different functions.

The log manager <NUM> may perform journaling in response to the journaling command Request. The log manager <NUM> may write journal data to a physical address to which a journal logical address included in the journaling command Request has been mapped by the flash mapping table <NUM>. Accordingly, journaling may be performed. When the journaling is finished/completed, the log manager <NUM> may inform the storage engine <NUM> that the journaling has been finished.

The checkpoint processor <NUM> may perform checkpointing in response to the checkpointing command CoW Command. The checkpoint processor <NUM> may remap the flash mapping table <NUM> using a journal logical address and a target logical address included in the checkpointing command CoW Command.

After the flash mapping table <NUM> is remapped, the garbage collection checker <NUM> may change a page of the nonvolatile memory <NUM>, which is addressed to a physical address mapped to the journal logical address, to an invalid page (e.g. to indicate that the page is no longer valid). Accordingly, the checkpointing may be finished, and the storage device checkpointing engine <NUM> may inform the storage engine <NUM> that the checkpointing has been finished. The garbage collection checker <NUM> may perform garbage collection according to the number of valid pages and the number of invalid pages in the nonvolatile memory <NUM>. This will be described in detail below with reference to <FIG>.

<FIG> are block diagrams for explaining the operation of the storage device <NUM> according to some example embodiments.

Referring to <FIG> and <FIG>, the application <NUM> may provide a query, e.g. a query such as PUT(0x100, A') including a target logical address 0x100 and journal data A' to the storage engine <NUM> (see ① in <FIG>). Data A, B, C, D and E are stored in an area <NUM> of the nonvolatile memory <NUM> which is addressed to physical addresses respectively mapped to logical addresses 0x100, 0x102, 0x104, 0x106 and 0x108 by the flash mapping table <NUM>. The journal data A' indicates updated data of the data A stored in the area <NUM> of the nonvolatile memory <NUM>, which is addressed to the physical address mapped to the target logical address 0x100 by the flash mapping table <NUM>. In addition, the data A' is assumed to generate a transaction.

The journal manager <NUM> within the host <NUM> may write a pair of the target logical address 0x100 and a journal logical address 0x000 to the journal mapping table <NUM> (②). The block aligner <NUM> within the host <NUM> may generate a journaling command REQUEST(0x000, A') by arranging the journal data A' at a start point of a sector (③).

In response to the journaling command REQUEST(0x000, A'), the log manager <NUM> within the storage device <NUM> may write (④) the journal data A' to an area <NUM> of the nonvolatile memory <NUM> which is addressed to a physical address mapped to the journal logical address 0x000 by the flash mapping table <NUM>.

Referring now to <FIG> and <FIG>, the application <NUM> may provide a query PUT(0x106, D') including a target logical address 0x106 and journal data D' and a query PUT(0x108, E') including a target logical address 0x108 and journal data E' to the storage engine <NUM>. Accordingly, as described above, a pair of the target logical address 0x106 and a journal logical address 0x002 and a pair of the target logical address 0x108 and a journal logical address 0x004 may be written to the journaling mapp table <NUM>, e.g. the journal mapping table <NUM> within the storage engine <NUM> of the host <NUM>. The journal data D' may be written to the area <NUM> of the nonvolatile memory <NUM>, which is addressed to a physical address mapped to the journal logical address 0x002 by the flash mapping table <NUM>, and the journal data E' may be written to the area <NUM> of the nonvolatile memory <NUM> which is addressed to a physical address mapped to the journal logical address 0x004 by the flash mapping table <NUM>.

When receiving a query such as PUT(0x100, A") including the target logical address 0x100 already written to the journal mapping table <NUM> and journal data A" from the application <NUM> (①), the journal manager <NUM> may delete, remove, or replace the pair of the target logical address 0x100 and the journal logical address 0x000 previously written to the journal mapping table <NUM> (②) and write a new pair of the target logical address 0x100 and a journal logical address 0x006 to the journal mapping table <NUM> (③).

The block aligner <NUM> within the host <NUM> may generate a journaling command REQUEST(0x006, A") by arranging the journal data A" at a start point of a sector (④). The log manager <NUM> within the storage device <NUM> may write the journal data A" to the area <NUM> of the nonvolatile memory <NUM> which is addressed to a physical address mapped to the journal logical address 0x006 by the flash mapping table <NUM>.

<FIG> is a block diagram for explaining a conventional checkpointing method.

Referring to <FIG>, in the conventional checkpointing, when receiving a checkpointing command from the application <NUM> (①), the storage engine <NUM>, e.g. a storage engine within a host, reads journal logical addresses 0x002, 0x004 and 0x008 from the journal mapping table <NUM> (②). Then, the storage engine <NUM> provides a command such as REQUEST(0x002, 0x004, 0x008) for reading data stored in the journal logical addresses 0x002, 0x004 and 0x008 to the storage device <NUM> (③). In response to the command REQUEST(0x002, 0x004, 0x008), the storage device <NUM> reads an area <NUM> of the nonvolatile memory <NUM> which is addressed to physical addresses mapped to the journal logical addresses 0x002, 0x004 and 0x008 by the flash mapping table <NUM> and provides read data D', E' and A‴ to the storage engine <NUM> (④). The storage engine <NUM> temporarily stores the read data D', E' and A‴ in a buffer and provides a command for writing the read data D', E' and A‴ to target logical addresses 0x106, 0x108 and 0x100 to the storage device <NUM>. Accordingly, the data D', E' and A‴ are written to the storage device <NUM> (⑤). The storage engine <NUM> provides a command for deleting the data A', D', E', A" and A‴ written to the journal logical addresses 0x000, 0x002, 0x004, 0x006 and 0x008 to the storage device <NUM>. In response to the command, the storage device <NUM> deletes the data A', D', E', A" and A‴ (⑥). Accordingly, the checkpointing operation is completed.

In the conventional checkpointing, data written to a journal logical address is read again, and written to a target logical address again. Therefore, the checkpointing operation takes a long time, redundant writing of journal data is inevitable, and/or a lot of commands are provided to the storage device <NUM>.

<FIG> is a block diagram for explaining a checkpointing method according some example embodiments. <FIG> is a case where the same pairs of target logical address and a journal logical address are written to the journal mapping table <NUM> illustrated in <FIG>.

Referring to <FIG> and <FIG>, the checkpoint scheduler <NUM> within host <NUM> may read a pair of a target logical address 0x106 and a journal logical address 0x002, a pair of a target logical address 0x108 and a journal logical address 0x004, and a pair of a target logical address 0x100 and a journal logical address 0x008 from the journal mapping table <NUM> (②).

The checkpoint scheduler <NUM> within the host <NUM> may generate checkpointing commands CoW(0x002, 0x106), CoW(0x004, 0x108) and CoW(0x008, 0x100) respectively including the read pair of the target logical address 0x106 and the journal logical address 0x002, the read pair of the target logical address 0x108 and the journal logical address 0x004, and the read pair of the target logical address 0x100 and the journal logical address 0x008 (③).

The checkpointing command queue <NUM> may provide the checkpointing commands CoW(0x002, 0x106), CoW(0x004, 0x108) and CoW(0x008, 0x100) as one set CoW Command Set to the storage device <NUM> (④).

The checkpoint processor <NUM> within the storage device <NUM> may remap the flash mapping table <NUM> in response to the checkpointing command CoW Command Set (⑤). Accordingly, the checkpointing operation may be finished.

<FIG> illustrates the nonvolatile memory <NUM> before checkpointing is performed, and <FIG> illustrates the nonvolatile memory <NUM> after checkpointing is performed, according to some example embodiments.

Referring to <FIG>, from a physical view or perspective, journal data A', D', E', A" and A‴ are written to a journal area <NUM> of the nonvolatile memory <NUM> which is addressed to physical addresses mapped to journal logical addresses 0x000, 0x002, 0x004, 0x006 and 0x008 according to a first mapping state of the flash mapping table <NUM>.

Referring to <FIG>, the flash mapping table <NUM> may be updated from the first mapping state to a second mapping state. From a logical view, target logical addresses 0x106, 0x108 and 0x100 may be mapped to physical addresses addressed to a data area <NUM> of the nonvolatile memory <NUM> according to the second mapping state of the flash mapping table <NUM>. In addition, physical addresses mapped to the journal logical addresses 0x000, 0x002, 0x004, 0x006 and 0x008 according to the second mapping state of the flash mapping table <NUM> may be changed to invalid pages. For example, the journal area <NUM> and a data area <NUM> of the nonvolatile memory <NUM> may not be separated. According to the checkpointing, the journal area <NUM> may be changed to the data area <NUM>, and the data area <NUM> may be changed to the journal area <NUM>.

The storage system according to some example embodiments may off-load checkpointing from the host <NUM> to the storage device <NUM>. Accordingly, there is no need or expectation to read data from the storage device <NUM> to the host <NUM> and write data from the host <NUM> to the storage device <NUM> again. Thus, the checkpointing time can be shortened. Alternatively or additionally, the storage device <NUM> may perform checkpointing by remapping the flash mapping table <NUM>. Therefore, redundant writing of data does not occur, and generation of invalid pages due to checkpointing can be reduced, which, in turn, reduces the frequency of garbage collection.

For example, the storage device <NUM> may perform checkpointing by reusing journal data written according to a journaling command.

<FIG> are graph for explaining effects of the storage system according to some example embodiments. In <FIG> and <FIG>, Baseline indicates a storage device not included in the storage system according to some example embodiments, and Check-In indicates a storage device included in the storage system according to some example embodiments. Zipfian indicates a case where the probability that a query will be generated for each logical address follows a normal distribution and may be associated with compression such as Zipf compression, and Uniform indicates a case where the probability that a query will be generated for each logical address is the same.

<FIG> illustrates the number of normalized redundant write operations of a storage device according to a checkpoint interval (s), and <FIG> illustrates the number of garbage collection operations (GC counts) according to the number of write queries (Write querycounts).

Referring to <FIG>, the number of redundant write operations in the storage device included in the storage system according to some example embodiments may be reduced compared with the number of redundant write operations in the storage device not included in the storage system according to some example embodiments. In the case of Uniform, the number of redundant write operations (arbitrary units) in the storage device included in the storage system according to some example embodiments may be reduced by about <NUM>% compared with the number of redundant write operations in the storage device not included in the storage system according to some example embodiments. Since the storage device included in the storage system according to some example embodiments performs checkpointing by reusing written journal data by remapping a physical address to a logical address, write amplification due to checkpointing can be improved, and/or the life of the storage device can be improved or increased.

Referring to <FIG>, the number of garbage collection operations with respect to the number of write queries in the storage device included in the storage system according to some example embodiments may be reduced compared with the number of garbage collection operations with respect to the number of write queries in the storage device not included in the storage system according to some example embodiments. Since the storage device included in the storage system according to some example embodiments performs checkpointing by reusing written journal data by remapping a physical address to a logical address, a reduced number of invalid pages may be generated. Therefore, the number of garbage collection operations of the storage device may be reduced, thus reducing the consumption of program/erase (P/E) cycles. Accordingly, the life of the storage device can be improved and/or increased.

<FIG> illustrates a normalized query response time according to tail latency in the case of Uniform. <FIG> illustrates a normalized query response time according to tail latency in the case of Zipfian.

Referring to <FIG>, in the storage device included in the storage system according to some example embodiments, a normalized query response time corresponding to <NUM>-percentail tail latency may be reduced by about <NUM>% in the case of Uniform. Referring to <FIG>, in the storage device included in the storage system according to some example embodiments, the normalized query response time corresponding to <NUM>-percentail tail latency may be reduced by about <NUM>% in the case of Zipfian.

When the checkpointing time increases, the speed of response to a query input to the storage system during checkpointing increases. This leads to tail latency that increases the response time to a query. However, since the checkpointing time is reduced in the storage system according to some example embodiments, the tail latency can be improved.

<FIG> illustrates a data center <NUM> to which a storage device according some example embodiments is applied.

Referring to <FIG>, the data center <NUM> is or includes a facility that collects various data and provides services and may also be referred to as a data storage center. The data center <NUM> may be or include a system for operating a search engine and a database and may be a computing system used by companies such as banks or government agencies. The data center <NUM> may include application servers <NUM> through 1100n and storage servers <NUM> through <NUM>. The number of application servers <NUM> through 1100n and/or the number of storage servers <NUM> through <NUM> may be variously selected depending on example embodiments. The number of application servers <NUM> through 1100n may be different from the number of storage servers <NUM> through <NUM>.

The application server <NUM> and/or the storage server <NUM> may include at least one of a processor <NUM> or <NUM> and a memory <NUM> or <NUM>. For example, in the case of the storage server <NUM>, the processor <NUM> may control the overall operation of the storage server <NUM> and access the memory <NUM> to execute a command and/or data loaded in the memory <NUM>. According to some embodiments, the memory <NUM> may include a count table. The memory <NUM> may be or include at least one of a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a nonvolatile DIMM (NV[M]DIMM).

Depending on example embodiments, the number of processors <NUM> and the number of memories <NUM> included in the storage server <NUM> may be variously selected. In some example embodiments, the processor <NUM> and the memory <NUM> may provide a processor-memory pair. In some example embodiments, the number of processors <NUM> may be different from the number of memories <NUM>. The processor <NUM> may include a single-core processor or a multi-core processor. The above description of the storage server <NUM> may be similarly applied to the application server <NUM>.

Depending on example embodiments, the application server <NUM> may not include a storage device <NUM>. The storage server <NUM> may include one or more storage devices <NUM>. The number of storage devices <NUM> included in the storage server <NUM> may be variously selected depending on embodiments.

The application servers <NUM> through 1100n and the storage servers <NUM> through <NUM> may communicate with each other through a network <NUM>. The network <NUM> may be implemented using Fibre Channel (FC) and/or Ethernet. Here, the FC may be a medium used for relatively high-speed data transmission and may use an optical switch that provides high performance/high availability. The storage servers <NUM> through <NUM> may be provided as at least one of file storage, block storage, or object storage according to an access method of the network <NUM>.

In some example embodiments, the network <NUM> may be a storage dedicated network such as a storage area network (SAN). For example, the SAN may be an FC-SAN using an FC network and implemented according to an FC protocol (FCP). For another example, the SAN may be an IP-SAN using a TCP/IP network and implemented according to an SCSI over TCP/IP or Internet SCSI (iSCSI) protocol. Alternatively or additionally in some example embodiments, the network <NUM> may be a general network such as a TCP/IP network. For example, the network <NUM> may be implemented according to a protocol such as FC over Ethernet (FCoE), network attached storage (NAS), or NVMe over Fabrics (NVMe-oF).

The application server <NUM> and the storage server <NUM> will hereinafter be mainly described. The description of the application server <NUM> may also be applied to another application server 1100n, and the description of the storage server <NUM> may also be applied to another storage server <NUM>.

The application server <NUM> may store data requested to be stored by a user or a client in one of the storage servers <NUM> through <NUM> through the network <NUM>. In addition, the application server <NUM> may obtain data requested to be read by a user or a client from one of the storage servers <NUM> through <NUM> through the network <NUM>. For example, the application server <NUM> may be implemented as a web server or a database management system (DBMS). The application server <NUM> may be or correspond to or include the host of <FIG> described according to some embodiments.

The application server <NUM> may access a memory 1120n or a storage device 1150n included in another application server 1100n through the network <NUM> or may access memories <NUM> through <NUM> or storage devices <NUM> through <NUM> included in the storage servers <NUM> through <NUM> through the network <NUM>. Accordingly, the application server <NUM> can perform various operations on data stored in the application servers <NUM> through 1100n and/or the storage servers <NUM> through <NUM>.

For example, the application server <NUM> may execute a command for transferring and/or copying data between the application servers <NUM> through 1100n and/or the storage servers <NUM> through <NUM>. Here, the data may be transferred from the storage devices <NUM> through <NUM> of the storage servers <NUM> through <NUM> to the memories <NUM> through 1120n of the application servers <NUM> through 1100n via the memories <NUM> through <NUM> of the storage servers <NUM> through <NUM> or directly. The data transferred through the network <NUM> may be data encrypted for security or privacy.

In the storage server <NUM>, for example, an interface <NUM> may provide a physical connection between the processor <NUM> and a controller <NUM> and a physical connection between an NIC <NUM> and the controller <NUM>. For example, the interface <NUM> may be implemented as a direct attached storage (DAS) interface that connects the storage device <NUM> directly to a dedicated cable. In addition, for example, the interface <NUM> may be implemented as various interfaces such as at least one of advanced technology attachment (ATA), serial-ATA (SATA), external SATA (e-SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVM express (NVMe), IEEE <NUM>, universal serial bus (USB), secure digital (SD) card, multi-media card (MMC), embedded multi-media card (eMMC), universal flash storage (UFS), embedded universal flash storage (eUFS), compact flash (CF), and a card interface.

The storage server <NUM> may further include a switch <NUM> and the NIC <NUM>. The switch <NUM> may selectively connect the processor <NUM> and the storage device <NUM> or may selectively connect the NIC <NUM> and the storage device <NUM> under the control of the processor <NUM>.

In some example embodiments, the NIC <NUM> may include at least one of a network interface card, a network adapter, or the like. The NIC <NUM> may be connected to the network <NUM> by a wired interface, a wireless interface, a Bluetooth interface, an optical interface, or the like. The NIC <NUM> may include an internal memory, a digital signal processor (DSP), a host bus interface, etc. and may be connected to the processor <NUM> and/or the switch <NUM> through the host bus interface. The host bus interface may be implemented as one of the above-described examples of the interface <NUM>. In some example embodiments, the NIC <NUM> may be integrated with at least one of the processor <NUM>, the switch <NUM>, and the storage device <NUM>.

In a storage server (<NUM>-<NUM>) or an application server (<NUM>-1100n), a processor may send a command to a storage device (<NUM>-1150n, <NUM>- <NUM>) and/or a memory (<NUM>-1120n, <NUM>-<NUM>) to program and/or read data. Here, the data may be data that has been error-corrected through an error correction code (ECC) engine. The data may be data processed by data bus inversion (DBI) or data masking (DM) and may include cyclic redundancy code (CRC) information. The data may be data encrypted for security and/or privacy.

The storage device (<NUM>-1150n, <NUM>-<NUM>) may send a control signal and a command/address signal to a NAND flash memory device (<NUM>-<NUM>) in response to the read command received from the processor. Accordingly, when data is read from the NAND flash memory device (<NUM>-<NUM>), a read enable (RE) signal may be input as a data output control signal, and thus the data to be output to a DQ bus. Data strobe (DQS) may be generated using the RE signal. The command and address signal may be latched in a page buffer according to a rising edge or a falling edge of a write enable (WE) signal.

The controller <NUM> may control the overall operation of the storage device <NUM>. In some example embodiments, the controller <NUM> may include an SRAM. The controller <NUM> may write data to a NAND flash memory device <NUM> in response to a write command or may read data from the NAND flash memory device <NUM> in response to a read command. For example, the write command and/or the read command may be provided from the processor <NUM> in the storage server <NUM>, a processor <NUM> in another storage server <NUM>, or processors <NUM> and 1110n in the application servers <NUM> and 1100n. A DRAM <NUM> may temporarily store (buffer) data to be written to the NAND flash memory device <NUM> or data read from the NAND flash memory device <NUM>. In addition, the DRAM <NUM> may store metadata. Here, the metadata is user data or data generated by the controller <NUM> to manage the NAND flash memory device <NUM>. The storage device <NUM> may include a secure element (SE) for security or privacy. The metadata may include a count table according to some embodiments.

Any or all of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU) , an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc..

Claim 1:
A storage system comprising:
a storage device (<NUM>) comprising a nonvolatile memory (<NUM>), the nonvolatile memory configured to store data at physical addresses, the physical addresses including a first physical address and a second physical address; and
a host (<NUM>) comprising a host processing circuitry configured to (A) insert a first journal logical address and a first target logical address into a journal mapping table (<NUM>), to (B) generate a journaling command by arranging first journal data in a log page in sectors, the sectors addressed to the first target logical address, and to (C) generate a checkpointing command (CoW) comprising the first target logical address and the first journal logical address,
wherein the storage device includes,
a flash mapping table (<NUM>) configured to store a first mapping state in which the first journal logical address maps to the first physical address, and the first target logical address maps to the second physical address, and
a storage device processing circuitry configured to (D) write, in response to the journaling command, the first journal data arranged in sectors to an area of the nonvolatile memory, which is addressed to the first physical address corresponding to the first journal logical address according to the first mapping state, and to (E) change, in response to the checkpointing command, the first mapping state of the flash mapping table to a second mapping state, in which the first target logical address is remapped to the first physical address;
wherein the host (<NUM>) processing circuitry is configured to generate an input query comprising the first journal data and the first target logical address, and a journal manager (<NUM>) is configured to generate the log page in response to the input query;
wherein the journal manager arranges journal data included in a transaction in a log page in units of sectors and the journal data included in the transaction is arranged at a start point of each sector and in a plurality of log pages according to the size of the journal data; and
wherein the transaction includes a unit of work in which the journal manager simultaneously performs a plurality of queries.