Patent Description:
As microelectronic devices become denser and operate at higher speeds, metal interconnects, such as damascene copper, have difficulty providing low electrical resistance while attaining desired narrow linewidths. Reduced linewidth and resistance requirements require thicker metal interconnects which undesirably increases capacitance between adjacent interconnects. <CIT> discloses graphene and hexagonal boron nitride devices. <CIT> discloses a graphene double-barrier resonant tunneling device.

The invention is defined in independent claims <NUM> and <NUM>. In described examples, a microelectronic device includes an electrical conductor, which includes a graphene heterolayer. The graphene heterolayer includes alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride and/or aluminum nitride.

A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of graphene has one to two atomic layers of graphene. Each layer of barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The graphene heterolayer is disposed in a nanoparticle film.

The layers of barrier material may match the crystal structure of the graphene so that the graphene has a high electron mobility. Alternating the layers of graphene and the layers of barrier material may enable forming an electrical conductor with the high mobility of the graphene, contacting materials of the microelectronic device which would otherwise degrade the graphene mobility if these materials contacted the planar surfaces of the graphene directly. Furthermore, alternating the layers of graphene and the layers of barrier material may enable each of the graphene layers in the graphene heterolayer to have an electron mobility close to a mobility of a single atomic layer of graphene. Electron mobility tends to degrade when multiple atomic layers of graphene are stacked together.

The graphene may be doped to attain a desired conductivity type and sheet resistance. For example, the graphene may be doped with boron, gallium, indium, silicon, germanium, nitrogen, phosphorus, arsenic, antimony, and/or oxygen. The graphene may be functionalized to provide a desired physical or chemical sensitivity. For example, the graphene may be functionalized with chemical reagents such as halogens, noble metals, hydroxyl groups, and/or organic molecules. The electrical conductor may include other electrically conductive material in addition to the graphene heterolayer.

For the purposes of this description, the term "instant top surface" of a microelectronic device refers to a top surface of the microelectronic device, which exists at the particular step being described. The instant top surface may change from step to step in the formation of the microelectronic device.

For the purposes of this description, the term "lateral" refers to a direction parallel to a plane of the instant top surface of the microelectronic device, and the term "vertical" refers to a direction perpendicular to the plane of the instant top surface of the microelectronic device.

Terms such as top, bottom, front, back, over, above, under, and below may be used in this description. These terms do not limit the position or orientation of a structure or element, but they provide spatial relationship between structures or elements.

<FIG> is a cross-section of an example microelectronic device containing an electrical conductor including a graphene heterolayer. The microelectronic device <NUM> includes a substrate <NUM> which may include a dielectric material of an interconnect region. The dielectric material may include one or more sublayers of silicon dioxide-based dielectric material such as silicon dioxide formed from tetraethyl orthosilicate (TEOS), low-k dielectric material formed from methyl silsesquioxane (MSQ) or hydrogen silsesquioxane (HSQ), organo-silicate glass (OSG), phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), or the like. The dielectric material may further include one or more sublayers of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, or the like, as cap layers and/or etch stop layers. The dielectric material may include one or more sublayers of organic dielectric material such as polyimide, benzo-cyclobutene (BCB) or the like.

A lower interconnect <NUM> may optionally be disposed in the substrate <NUM>. The lower interconnect <NUM> may be, for example, an aluminum interconnect, a damascene copper interconnect, or a plated copper interconnect. An aluminum lower interconnect <NUM> may include an aluminum layer with a few percent silicon, titanium, and/or copper, possibly on an adhesion layer including titanium, and possibly with an anti-reflection layer of titanium nitride on the aluminum layer. A damascene copper lower interconnect <NUM> may include copper on a barrier layer of tantalum and/or tantalum nitride, disposed in a trench in the dielectric material. A plated copper lower interconnect <NUM> may include an adhesion layer at a bottom of the lower interconnect <NUM>, and may have a barrier layer disposed on the sides of the lower interconnect <NUM>. Other structures and metals for the lower interconnect <NUM> are within the scope of this example.

An electrical conductor <NUM>, that includes a graphene heterolayer <NUM>, is disposed over the substrate <NUM>. The graphene heterolayer <NUM> includes alternating layers of graphene <NUM> and layers of a barrier material <NUM>. Each layer of graphene <NUM> has one to two atomic layers of graphene. Each layer of the barrier material <NUM> has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. A thickness of the graphene heterolayer <NUM> is exaggerated in <FIG> to show the alternating layers of graphene <NUM> and layers of a barrier material <NUM>. The layers of graphene <NUM> and the layers of barrier material <NUM> may be continuous across the electrical conductor <NUM>, as depicted in <FIG>. The electrical conductor <NUM> may be located over the lower interconnect <NUM>, as depicted in <FIG>.

A lower via <NUM> may be disposed through the graphene heterolayer <NUM> and extend to the lower interconnect <NUM>, thus providing an electrical connection between the electrical conductor <NUM> and the lower interconnect <NUM>. By extending through the graphene heterolayer <NUM>, the lower via <NUM> makes electrical contact to the layers of graphene <NUM>. The lower via <NUM> may include a liner of titanium and titanium nitride, and a fill metal of tungsten. Alternatively, the lower via <NUM> may include a liner of tantalum or tantalum nitride, and a fill metal of copper. Other structures and metals for the lower via <NUM> are within the scope of this example.

An upper dielectric layer <NUM> may be disposed over the electrical conductor <NUM> and the substrate <NUM>. The upper dielectric layer <NUM> may include similar sublayers as described for the substrate <NUM>. An upper interconnect <NUM> may be disposed in the upper dielectric layer <NUM>, over the electrical conductor <NUM>. The upper interconnect <NUM> may have a similar structure and composition as the lower interconnect <NUM>. An upper via <NUM> may be disposed from the upper interconnect <NUM> through the graphene heterolayer <NUM>, thus providing an electrical connection between the upper via <NUM> and the electrical conductor <NUM>. By extending through the graphene heterolayer <NUM>, the upper via <NUM> makes electrical contact to the layers of graphene <NUM>. The upper via <NUM> may have a similar structure and composition as the lower via <NUM>.

One or more of the layers of graphene <NUM> may be doped to attain a desired conductivity type and sheet resistance. One or more of the layers of graphene <NUM> may be functionalized to provide a desired physical or chemical sensitivity.

The graphene heterolayer <NUM> may provide a lower resistance for the electrical conductor <NUM> than metals used in the lower interconnect <NUM> and/or the upper interconnect <NUM>, due to the high mobility of the layers of graphene <NUM>. The electrical conductor <NUM> may provide an interconnect of the microelectronic device <NUM>, a component such as an inductor, an antenna, an electromagnetic shield, or other function.

<FIG> are cross-sections of a microelectronic device depicting successive stages of an example method of forming an electrical conductor containing a graphene heterolayer. Referring to <FIG>, the microelectronic device <NUM> includes a substrate <NUM>. The substrate <NUM> may include dielectric material of an interconnect region of the microelectronic device <NUM> at a top surface <NUM> of the substrate <NUM>. A boron reagent gas, designated as BORON REAGENT GAS in <FIG>, is flowed over the top surface <NUM>. The boron reagent gas may include, for example, boron trichloride gas. The boron reagent gas forms a boron-containing layer <NUM> over the top surface <NUM> of the substrate <NUM>. The boron-containing layer <NUM> may be, for example, substantially a monolayer of boron-containing molecules. Flow of the boron reagent gas is ceased after the boron-containing layer <NUM> is formed.

Referring to <FIG>, a nitrogen reagent gas, designated as NITROGEN REAGENT GAS in <FIG>, is flowed over the boron-containing layer <NUM> of <FIG>. The nitrogen reagent gas may include, for example, ammonia gas. Nitrogen atoms in the nitrogen reagent gas react with boron atoms in the boron-containing layer <NUM> to form a layer of boron nitride <NUM> over the top surface <NUM> of the substrate <NUM>. The layer of boron nitride <NUM> may include hexagonal boron nitride and/or cubic boron nitride. The layer of boron nitride <NUM> may be, for example, substantially one molecule thick. Flow of the nitrogen reagent gas is ceased after the layer of boron nitride <NUM> is formed.

The steps described in reference to <FIG> may optionally be repeated to increase the layer of boron nitride <NUM> to substantially two molecules thick, or possibly three molecules thick. Alternatively, formation of the microelectronic device <NUM> may be continued with the layer of boron nitride <NUM> being substantially one molecule thick.

Referring to <FIG>, the substrate <NUM> may be heated, for example to a temperature of <NUM> to <NUM>. A carbon-containing reagent gas, designated in <FIG> as "CARBON REAGENT GAS" is flowed over layer of boron nitride <NUM> and radio frequency (RF) power, designated in <FIG> as "RF POWER" is applied to the carbon-containing reagent gas to generate carbon radicals above the layer of boron nitride <NUM>. The carbon-containing reagent gas may include methane, straight chain alkanes such as ethane, propane and/or butane, alcohols such as ethanol, and/or cyclic hydrocarbons such as cyclobutane or benzene. Additional gases such as hydrogen, argon and/or oxygen may also be flowed over the layer of boron nitride <NUM>. Some carbon-containing molecules in the carbon-containing reagent gas are dissociated by the RF power, producing carbon radicals. A portion of the carbon radicals form a layer of graphene <NUM> on the layer of boron nitride <NUM>. The layer of graphene <NUM> may be one atomic layer thick, or may be two atomic layers thick. The RF power and the flow of the carbon-containing reagent gas are ceased after the layer of graphene <NUM> is formed.

Alternatively, the layer of graphene <NUM> may be formed by a transfer process, in which graphene is formed on a suitable substrate and subsequently transferred to the microelectronic device <NUM>. The transfer process allows a higher formation temperature for the graphene, which may provide reduced defects.

The layer of boron nitride <NUM> and the layer of graphene <NUM> are part of a graphene heterolayer <NUM>, which is part of an electrical conductor <NUM> of the microelectronic device <NUM>. The steps described in reference to <FIG> are repeated in sequence to form additional alternating layers of the boron nitride <NUM> and the layer of graphene <NUM> to complete the graphene heterolayer <NUM>. The layers of graphene <NUM> and the layers of boron nitride <NUM> formed by the methods of this example may be continuous across the electrical conductor containing the graphene heterolayer <NUM>.

The layers of boron nitride <NUM> provide a barrier material between the layers of graphene <NUM>. In an alternate version of this example, the barrier material may be provided by another suitable material, that is, a material which is substantially electrically nonconductive or has a bandgap energy greater than <NUM> electron-volts, and has a lattice spacing close to a lattice spacing of graphene. For example, the barrier material may be provided by aluminum nitride. The method described in reference to <FIG> may be considered an atomic layer deposition (ALD) method. Other methods of forming the layers of barrier material are within the scope of this example.

The graphene heterolayer <NUM> may be subsequently patterned, for example by a mask and etch process, or by other methods. The graphene heterolayer <NUM> may provide substantially all of the electrical conductor <NUM>.

<FIG> and <FIG> are cross-sections of another example microelectronic device containing an electrical conductor including a graphene heterolayer. Referring to <FIG>, the microelectronic device <NUM> includes a substrate <NUM>, for example as described in reference to <FIG>. An electrical conductor <NUM> is disposed over the substrate <NUM>. An upper dielectric layer <NUM> may be disposed over the electrical conductor <NUM> and the substrate <NUM>. The electrical conductor <NUM> may be a shielded conductor, with shield lines <NUM> disposed laterally adjacent to the electrical conductor <NUM>.

Referring to <FIG>, according to embodiments of the invention, the electrical conductor <NUM> includes nanoparticles <NUM> that include graphene heterolayers. The graphene heterolayers includes alternating layers of graphene and layers of a barrier material. Each layer of graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The structure of the graphene heterolayers is similar to that depicted in <FIG>. The nanoparticles <NUM> may be less than <NUM> micron in size. The electrical conductor <NUM> is substantially free of organic binder material between the nanoparticles <NUM>. The graphene heterolayers may provide a lower electrical resistivity for the electrical conductor <NUM> than a metal interconnect of comparable thickness.

The shield lines <NUM> may have a structure similar to the structure of the electrical conductor <NUM>. Having additional conductive lines with structures similar to the electrical conductor <NUM> may enable a desired circuit element, such as the shielded line depicted in <FIG>, without introducing significant topography in the microelectronic device <NUM>.

<FIG> and <FIG> are cross-sections of a microelectronic device depicting successive stages of a method of forming an electrical conductor containing a graphene heterolayer, according to embodiments of the invention. Referring to <FIG>, the microelectronic device <NUM> includes a substrate <NUM>. The substrate <NUM> may include dielectric material of an interconnect region of the microelectronic device <NUM> at a top surface <NUM> of the substrate <NUM>. A nanoparticle ink film <NUM> is formed over the top surface <NUM> by dispensing a nanoparticle ink <NUM> by an additive process <NUM>. For the purposes of this description, an additive process disposes the nanoparticles in a desired area and does not dispose the nanoparticles outside of the desired area, so that it is not necessary to remove a portion of the dispensed nanoparticles to produce a final desired shape of the nanoparticles. Additive processes may enable forming films in desired areas without photolithographic processes and subsequent etch processes, thus advantageously reducing fabrication cost and complexity. The nanoparticle ink <NUM> includes nanoparticles and a carrier fluid. The nanoparticles include graphene heterolayers, as described in reference to <FIG>. The nanoparticle ink <NUM> may be, for example, an ink, a slurry, or a sol gel. The nanoparticle ink <NUM> is dispensed onto the microelectronic device <NUM> in an area for the subsequently-formed electrical conductor, and is not dispensed over the entire instant top surface of the substrate <NUM>.

The additive process <NUM> may include, for example, a continuous extrusion process, using a continuous dispensing apparatus <NUM>. The continuous dispensing apparatus <NUM> may be configured so that the microelectronic device <NUM> and the continuous dispensing apparatus <NUM> may be moved laterally with respect to each other to provide a desired dispensing pattern for the nanoparticle ink film <NUM>. The discrete continuous dispensing apparatus <NUM> may have a plurality of dispensing ports which may be independently activated in parallel to provide a desired throughput for the additive process <NUM>. In an alternate version of this example, the additive process <NUM> may include a discrete droplet process (sometimes referred to as an inkjet process), a direct laser transfer process, an electrostatic deposition process, or an electrochemical deposition process.

Referring to <FIG>, the nanoparticle ink film <NUM> of <FIG> is heated by a heating process <NUM> to remove at least a portion of a volatile material from the nanoparticle ink film <NUM>, to form a nanoparticle film <NUM> which is electrically conductive. The heating process <NUM> may include, for example, a blanket radiant heating step using an incandescent light source, a selective radiant heating step using infrared light emitting diodes (IR LEDs) which may be programmed to apply infrared radiation to the nanoparticle ink film <NUM> and not to other areas of the microelectronic device <NUM>, a hot plate heating step, and/or a forced convection heating step. The heating process <NUM> may be ramped from a low power to a high power, in order to remove more of the volatile material without degrading the structural integrity of the nanoparticle film <NUM>. The nanoparticle film <NUM> may be further heated by a flash heating step or a spike heating step, which may further improve the electrical conductivity of the nanoparticle film <NUM>. The nanoparticle film <NUM> may provide the entirety of the electrical conductor <NUM>, as indicated in <FIG>. Alternatively, other electrically conductive layers may be formed on the nanoparticle film <NUM> to provide the electrical conductor <NUM>.

<FIG> is a perspective view of bilayer graphene. Bilayer graphene has two atomic layers of graphene. The layers of graphene in the examples described herein may include Bernal bilayer graphene. A first atomic layer of graphene, designated FIRST ATOMIC LAYER in <FIG>, contains carbon atoms, designated CARBON ATOM in <FIG>, in a hexagonal configuration. A second atomic layer of graphene, designated SECOND ATOMIC LAYER in <FIG>, also contains carbon atoms in a hexagonal configuration. In Bernal bilayer graphene half of the carbon atoms in the first atomic layer are located directly over carbon atoms in the second atomic layer. Including Bernal bilayer graphene in the graphene layers of the graphene heterolayers may advantageously improve electrical conductivity of the graphene heterolayers compared to dual layers of graphene having other configurations.

<FIG> is a cross-section of an example microelectronic device containing an electrical conductor including a graphene heterolayer in a thin film transistor. The microelectronic device <NUM> includes a substrate <NUM>, for example as described in reference to <FIG>. A semiconductor layer <NUM> is formed over the substrate <NUM>. The semiconductor layer <NUM> may include, for example, polycrystalline silicon. The semiconductor layer <NUM> includes a body region <NUM>, a first source/drain region <NUM> laterally adjacent to the body region <NUM>, and a second source/drain region <NUM> laterally adjacent to the body region <NUM> and opposite to the first source/drain region <NUM>. An electrical conductor <NUM> including a graphene heterolayer <NUM> is formed over the body region <NUM> of the semiconductor layer <NUM>. The graphene heterolayer <NUM> includes alternating layers of graphene <NUM> and layers of barrier material <NUM>, as described in reference to <FIG>. The graphene heterolayer <NUM> extends over the body region <NUM>, but does not extend over the first source/drain region <NUM> or the second source/drain region <NUM>. The body region <NUM>, the first source/drain region <NUM>, the second source/drain region <NUM>, and the graphene heterolayer <NUM> over the body region <NUM> provide the thin film transistor <NUM>. The graphene heterolayer <NUM> over the body region <NUM> provides a gate of the thin film transistor <NUM>. Forming the thin film transistor <NUM> as described in this example may enable transistor functionality in an interconnect region of the microelectronic device <NUM> without significant increase in fabrication cost and complexity.

<FIG> is a cross-section of an example microelectronic device containing an electrical conductor including a graphene heterolayer as an antenna for a bandgap convertor. The microelectronic device <NUM> includes a substrate <NUM> that includes a semiconductor layer <NUM> having a top surface <NUM>. The semiconductor layer <NUM> includes one or more semiconductor materials with desired bandgaps. For example, the semiconductor materials may include type IV semiconductors such as silicon, germanium, silicon germanium and/or silicon carbide. The semiconductor materials may include type III-V semiconductors such as gallium nitride and/or gallium aluminum nitride. Other semiconductor materials are within the scope of this example. The semiconductor layer <NUM> includes a lower semiconductor region <NUM> which may be p-type as indicated in <FIG>. A cathode well <NUM> is formed in the semiconductor layer <NUM>; in this example, the cathode well <NUM> may be n-type with an average dopant density of <NUM>×<NUM><NUM> cm-<NUM> to <NUM>×<NUM><NUM> cm-<NUM>. The cathode well <NUM> may extend <NUM> nanometers to <NUM> microns below the top surface <NUM> of the semiconductor layer <NUM>. Optional n-type well contact regions <NUM> which may have average dopant densities of <NUM> to <NUM> times higher than the cathode well <NUM>, may be formed in the semiconductor layer <NUM>, contacting the cathode well <NUM> and extending to the top surface <NUM> of the semiconductor layer <NUM>. A p-type anode <NUM> is formed in the semiconductor layer <NUM>, contacting the cathode well <NUM> and extending to the top surface <NUM> of the semiconductor layer <NUM>. The anode <NUM> may have an average dopant density of <NUM>×<NUM><NUM> cm-<NUM> to <NUM>×<NUM><NUM> cm-<NUM>. The anode <NUM> may be laterally isolated from the well contact regions <NUM> by isolation oxide <NUM> such as field oxide, formed at the top surface <NUM>. The isolation oxide <NUM> may be formed, for example, by a shallow trench isolation (STI) process, or by a local oxidation of silicon (LOCOS) process. The anode <NUM> and the cathode well <NUM> provide the bandgap converter <NUM> of the microelectronic device <NUM>.

An interconnect region <NUM> is formed over the semiconductor layer <NUM>. The interconnect region <NUM> includes a dielectric layer stack <NUM> which may include one or more sublayers of silicon dioxide-based dielectric material to provide interlevel dielectric (ILD) sublayers and intrametal dielectric (IMD) sublayers. The dielectric layer stack <NUM> may further include one or more sublayers of other dielectric materials as cap layers and/or etch stop layers.

A plurality of contacts are formed in the dielectric layer stack <NUM> to provide electrical connections to components of the microelectronic device <NUM> disposed in the semiconductor layer <NUM>. The contacts include an anode contact <NUM> that makes an electrical connection to the anode <NUM> of the bandgap converter <NUM>. The contacts further include cathode contacts <NUM> that make electrical connections to the cathode well <NUM> of the bandgap converter <NUM> through the well contact regions <NUM>.

A plurality of interconnects are formed in the dielectric layer stack <NUM> which make electrical connections to the contacts. The interconnects include an anode interconnect <NUM> on the anode contact <NUM>, and cathode interconnects <NUM> on the cathode contacts <NUM>.

An electrical conductor <NUM> is formed on the dielectric layer stack <NUM> to provide an antenna <NUM> for the bandgap converter <NUM>. The electrical conductor <NUM> includes a graphene heterolayer <NUM> with alternating layers of graphene <NUM> and layers of a barrier material <NUM>. The graphene heterolayer <NUM> may be formed according to any of the examples described herein. A via <NUM> is formed through the graphene heterolayer <NUM> and through a portion of the dielectric layer stack <NUM> to make an electrical connection to the anode interconnect <NUM>, so that the antenna <NUM> is electrically coupled to the anode <NUM>. During operation of the microelectronic device <NUM>, electromagnetic waves may be converted to oscillating electrical signals by the antenna <NUM>, coupled to the bandgap converter <NUM> by the via <NUM>, the anode interconnect <NUM> and the anode contact <NUM>; the bandgap converter subsequently converts the oscillating electrical signals to rectified electrical signals, which may be processed by other circuits of the microelectronic device <NUM>.

<FIG> and <FIG> are cross-sections of an example microelectronic device containing a plurality of electrical conductors, each including a graphene heterolayer, providing a capacitor. Referring to <FIG>, the microelectronic device <NUM> includes a substrate <NUM>. The substrate <NUM> may include a semiconductor layer with active components. The substrate <NUM> includes dielectric material <NUM> extending to a top surface <NUM> of the substrate <NUM>. The dielectric material <NUM> may include isolation oxide such as field oxide, or may include one or more dielectric sublayers of a dielectric layer stack of an interconnect region of the microelectronic device <NUM>. A plurality of electrical conductors <NUM> are formed over the substrate <NUM> to provide a capacitor <NUM>.

The structure of the electrical conductors <NUM> is shown in more detail in <FIG>. Each electrical conductor <NUM> includes a graphene heterolayer <NUM>. Each graphene heterolayer <NUM> includes a plurality of alternating layers of graphene <NUM> and layers of a barrier material <NUM>. Each layer of graphene <NUM> has one to two atomic layers of graphene. Each layer of barrier material <NUM> has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The graphene heterolayers <NUM> may be continuous, as depicted in <FIG>, or may be disposed in a nanoparticle film. The graphene heterolayers <NUM> may be formed according to any of the examples described herein. A first subset <NUM> of the graphene heterolayers <NUM> provides a first set of plates of the capacitor <NUM>, and a second subset <NUM> of the graphene heterolayers <NUM> provides a second set of plates of the capacitor.

Referring back to <FIG>, an upper dielectric layer stack <NUM> is formed over the capacitor <NUM>. Electrical connections to the capacitor <NUM> may be provided by vias. For example, a first via <NUM> may be formed through the first subset <NUM> of the graphene heterolayers <NUM>, and extend down to a first interconnect <NUM> formed in the substrate <NUM>, and a second via <NUM> may be formed through the second subset <NUM> of the graphene heterolayers <NUM>, and extend up to a second interconnect <NUM> formed in the upper dielectric layer stack <NUM>. Forming the first via <NUM> to extend through the graphene heterolayers <NUM> in the first subset <NUM> may advantageously provide electrical connections to each graphene layer <NUM>, and similarly for the second via <NUM>, may thus provide a desired total capacitance for the capacitor <NUM>. Other structures for making electrical connections to the capacitor <NUM> are within the scope of this example.

<FIG> and <FIG> are cross-sections of an example microelectronic device containing a plurality of electrical conductors, each including a graphene heterolayer, to provide a meta-material structure. Referring to <FIG>, the microelectronic device <NUM> includes a substrate <NUM>, which may include a dielectric material extending to a top surface <NUM> of the substrate <NUM>. The meta-material structure <NUM> is formed over the top surface <NUM>. A first level of split-ring resonators <NUM> is formed over the top surface <NUM>. Each split-ring resonator <NUM> is an electrical conductor <NUM> having a graphene heterolayer. Each graphene heterolayer includes alternating layers of graphene and layers of a barrier material. Each layer of graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The split-ring resonators <NUM> may be referred to as meta-atoms.

A first dielectric isolation layer <NUM> is formed over the first level of split-ring resonators <NUM> and the substrate <NUM>. The first dielectric isolation layer <NUM> may include inorganic material such as silicon dioxide-based material, and/or may include organic material such as polyimide or BCB. The first dielectric isolation layer <NUM> may be formed using a spin coat process to produce a substantially planar layer, or may be formed using a conformal deposition process and subsequently planarized, for example using a chemical mechanical polish (CMP) process.

A second level of split-ring resonators <NUM> is formed over the first dielectric isolation layer <NUM> and over the first level of split-ring resonators <NUM>. Each split-ring resonator <NUM> is an electrical conductor <NUM> having a graphene heterolayer. Each graphene heterolayer includes alternating layers of graphene and layers of a barrier material. The layers of graphene and the layers of the barrier material have the properties described in reference to the first level of split-ring resonators <NUM>.

A second dielectric isolation layer <NUM> is formed over the second level of split-ring resonators <NUM> and the first dielectric isolation layer <NUM>. The second dielectric isolation layer <NUM> may be formed by a similar process as the first dielectric isolation layer <NUM>, and may have a similar composition and a similar structure.

A third level of split-ring resonators <NUM> is formed over the second dielectric isolation layer <NUM> and over the second level of split-ring resonators <NUM>. Each split-ring resonator <NUM> is an electrical conductor <NUM> having a graphene heterolayer. Each graphene heterolayer includes alternating layers of graphene and layers of a barrier material. The layers of graphene and the layers of the barrier material have the properties described in reference to the first level of split-ring resonators <NUM>.

Additional dielectric isolation layers and additional levels of split-ring resonators may be formed over the third level of split-ring resonators <NUM>. The levels of split-ring resonators provide the meta-material structure <NUM>. The meta-material structure <NUM> may absorb electromagnetic radiation in a desired band of wavelengths, or may exhibit a desired response to the electromagnetic radiation, such as negative refraction. Other types of meta-atoms may be used in the meta-material structure <NUM> besides the split-ring resonators <NUM>, <NUM>, and <NUM> to achieve desired properties of the meta-material structure <NUM>.

Referring to <FIG>, which is a cross-section of one of the third level of split-ring resonators <NUM>, the electrical conductor <NUM> includes nanoparticles <NUM> that include graphene heterolayers. The graphene heterolayers includes alternating layers of graphene and layers of a barrier material. Each layer of graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The structure of the graphene heterolayers is similar to that depicted in <FIG>. The nanoparticles <NUM> may be less than <NUM> micron in size. The electrical conductor <NUM> is substantially free of organic binder material between the nanoparticles <NUM>.

The split-ring resonators <NUM> of the first level, the split-ring resonators <NUM> of the second level, the split-ring resonators <NUM> of the third level, and split-ring resonators in subsequent levels, may be formed by an additive process as described in reference to <FIG> and <FIG>. Using the additive process to form a plurality of levels of split-ring resonators may significantly reduce fabrication cost and complexity for the microelectronic device <NUM> compared to using a photolithographic process and etch process for each level.

Claim 1:
A microelectronic device, comprising:
a substrate; and
an electrical conductor disposed over the substrate, the electrical conductor comprising a graphene heterolayer, the graphene heterolayer comprising of a plurality of alternating layers of graphene and layers of a barrier material, wherein each layer of graphene has one to two atomic layers of graphene, and each layer of the barrier material has one to three monolayers selected from the group consisting of hexagonal boron nitride, cubic boron nitride, and aluminum nitride; characterized in that the graphene heterolayer comprising the layers of graphene and the layers of the barrier material is disposed in nanoparticles.