Patent Description:
As microprocessors become faster and smaller, integrated circuitry, IC, becomes more complex and components become more densely packed. The use of non-planar fin based transistor devices has enabled increased performance with a smaller device footprint. Fins that are substantially rectangular in shape have improved short channel effects compared to fins with trapezoidal or triangular shapes. This leads to higher performance for a given voltage overdrive. Rectangular fins also enable consistent device performance across the fin height with no degradation in current.

However, as the aspect ratio of transistor devices continues to increase, the challenge of maintaining uniform widths and rectangular cross-sections of the fins across the substrate becomes more difficult. Specifically, when the critical dimension, CD, and pitch of the devices decrease, micro loading effects become a significant problem. Micro loading effects occur when the CD and pitch of the fins is small enough to create different active ion accessibility at the surface of the substrate during an etching process. This results in a structurally dependent etch bias due to localized enhanced etching or plasma deposition. Additionally, the micro loading effect becomes a more significant problem when the pitch between fin based structures is non-uniform. As an example, when nested fins and isolated fins are formed with a single etching process, the widths of the nested fins will not be equal to the widths of the isolated fins, because the micro loading effect will be different for each type of fin. Accordingly, it becomes increasingly difficult to design circuitry that includes fin based transistor devices that require non-uniform spacing. As a result of the different pitches, nested fins will have different metrics, such as leakage current and threshold voltage, than isolated fins, even though both fins are designed to perform equivalently.

<CIT> discloses a semicondctor device comprising a monocrystalline silicon substrate including a first group of densely spaced fins and a second group of isolated fins. The spacing between the fins of second group is larger spacing than the spacing between the fins of the first group.

Embodiments of the invention prevent micro loading effects from causing a significant difference in the widths of isolated fins and nested fins. Embodiments of the invention utilize multiple substrate etching processes to produce uniform fin widths with rectangular cross sections in both nested and isolated fin structures formed on the same substrate. Uniform fin width allows for the use of multi-fin devices that have uniform metrics, such as threshold voltage and leakage current, in the nested and isolated fin structures. Furthermore, uniform width in isolated and nested fins allows for the use of isolated fins in circuitry, such as an IC device.

In particular, a hard mask patterning process may be included that transfers the fin shapes formed in a dummy hard mask into a hard mask layer. In order to maintain uniform fin widths between isolated and nested fins while transferring the shape of the fins into the hard mask, the hard mask etching process utilizes an etching chemistry with a high ratio of hydrogen to oxygen. According to an embodiment, the increased hydrogen concentration is obtained by utilizing an etching chemistry comprising CH<NUM>F. After the hard mask layer is patterned, a breakthrough etch may be utilized to remove portions of an etchstop layer above the substrate in which the fins will be formed.

Multiple substrate etching processes also may be included to provide uniform fin width for the high aspect ratio fins. A first substrate etching process etches the substrate to a first depth. Embodiments of the invention include fin based devices with a first depth between <NUM> and <NUM>. Embodiments of the first etching process utilize a chemistry that passivates the sidewalls to preserve the fin width. By way of example, the first etching process may utilize a chemistry comprising HBr, O<NUM> and CF<NUM>. The first substrate etching process may have a lateral passivation rate that is greater for isolated fins than the lateral passivating rate for nested fins. As such, a first substrate etching process may result in the nested fins having a smaller width 'than the width of the isolated fins. Accordingly, embodiments of the invention may utilise a second etching process may be included to equalize the widths of the isolated fins and the nested fins. The second etching process may equalize the widths of the fins by utilizing an etching chemistry that has a lateral etch rate that is greater for isolated fins than the lateral etch rate for nested fins. Embodiments of the invention utilize a chemistry comprising Cl<NUM>, Ar, and CH<NUM> for the second substrate etching process. During the second etching process, the substrate is etched to a second depth.

Embodiments of the invention may include a second depth that is between <NUM> and <NUM>.

The high aspect ratio fins of certain embodiments of the present invention include fins that have a pitch of <NUM> and below A CD of <NUM> and below may be included.

<FIG> is a flow diagram that illustrates a method <NUM> of forming high aspect ratio fins with uniform widths.

Cross-sectional views of the fin based device <NUM> shown in <FIG> are used in conjunction with <FIG> to illustrate a method of forming uniform high aspect ratio fins.

Referring now to <FIG>, the method of forming high aspect ratio fins <NUM> may begin at block <NUM> according to an embodiment. At block <NUM> a masking stack <NUM> is formed over a semiconductor substrate. <FIG> is a cross-sectional view of substrate <NUM> after a masking stack <NUM> has been disposed over its top surface. The masking stack <NUM> may comprise a dummy hard mask <NUM>, a hard mask layer <NUM>, and an etchstop layer <NUM>, as shown in <FIG>.

Dummy hard mask <NUM> may include one or more isolated features <NUM> and one or more nested features <NUM>. Isolated features <NUM> are disposed above portions of the substrate <NUM> where isolated fins <NUM> li will be formed during subsequent processing, and nested features <NUM> are disposed above portions of the substrate <NUM> where nested fins <NUM> I will be formed during subsequent processing. According to an embodiment, the dummy hard mask <NUM> may be composed of a typical masking material, such as an oxide.

The width WD of the isolated and nested features <NUM>, <NUM> are chosen such that they are larger than the desired fin widths of the nested and isolated fins. Forming isolated and nested features <NUM>, <NUM> with a width WD greater than the desired width of the fins <NUM> allows for subsequent etching processes to have a non-zero lateral etch rate that reduces the width of the fins. The width WD of the features <NUM>, <NUM> may be less than <NUM>. A dummy hard mask <NUM> may be included with features <NUM>, <NUM> that have a width WD less than <NUM>.

A multiple patterning process may be used to form the dummy hard mask <NUM>. A multiple patterning process may be desirable when the pitches P and Pi between features are sufficiently small, such that the resolution of lithography techniques are insufficient to pattern the dummy hard mask. A double patterning process may be included in which spacers are formed on the sidewalls of pre-patterned features, as is known in the art. The spacers may be an oxide material and the pre-patterned features may be a polysilicon material. The pre-patterned features may be formed with a lithography process known in the art, such as photolithography. The spacers may be formed by disposing a layer of material, such as an oxide, over the pre-patterned features and the exposed surfaces of the hard mask layer <NUM>. An anisotropic spacer etching process may then be used to remove the oxide material disposed on the horizontal surfaces of the exposed hard mask layer <NUM> and the pre-patterned features, leaving only spacers disposed on the sidewalls of the pre-patterned features. The pre-patterned features may be selectively removed, thereby leaving only the spacers behind. The pitch between each of the spacers may be adjusted by changing the width of the pre-patterned material.

The remaining spacers may be used as the isolated features <NUM> and the nested features <NUM> that form the dummy hard mask <NUM>. The double patterning process may be repeated one or more times, with the final remaining set of spacers being utilized as the isolated and nested features <NUM>, <NUM> of the dummy hard mask <NUM>.

In particular, the dummy hard mask <NUM> is formed from a material that is resistant to an etching process that will selectively etch through the hard mask layer <NUM> that is disposed below it, as shown in <FIG>. In particular, the dummy hard mask <NUM> may be an oxide material, such as silicon dioxide. In particular, the hard mask layer <NUM> is a material that is resistant to an etchant that will selectively etch the substrate <NUM>.

In particular, the hard mask layer <NUM> is a nitride. In particular, a hard mask layer <NUM> is a thermally grown nitride, such as S1<NUM>N<NUM>. In particular, a hard mask layer <NUM> has a thickness between <NUM> and <NUM>. It is possible to include forming the hard mask layer <NUM> with processes such as, chemical vapor deposition, CVD, physical vapor deposition, PVD, or atomic layer deposition , ALD.

As shown in <FIG>, it is possible to include a hard mask layer <NUM> that is disposed above an etch stop layer <NUM>. The etch stop layer may be a suitable oxide layer, such as a silicon dioxide layer. In particular, a thermally grown oxide layer may be included that is less than <NUM> thick. An etchstop layer <NUM> may be included that is a silicon dioxide layer that is thermally grown and approximately <NUM> thick.

In particular, forming the etch stop layer <NUM> with processes such as, CVD, PVD, or ALD may be included.

In particular, the etch stop layer <NUM> is disposed on a top surface of the semiconductor substrate <NUM>, as shown in <FIG>.

Referring back to <FIG>, the method of forming high aspect ratio fins <NUM> proceeds to block <NUM>. At block <NUM>, a hard mask etching process is implemented to etch through the hard mask layer <NUM>. In particular, the hard mask etching process utilizes the dummy hard mask <NUM> as a mask in order to transfer the isolated and nested features <NUM>, <NUM> into the hard mask layer <NUM> to form isolated hard mask features <NUM> and nested hard mask features <NUM>. Accordingly, the isolated hard mask features <NUM> and the nested hard mask features <NUM> are aligned with the isolated and nested dummy hard mask features <NUM> and <NUM>, respectively. <FIG> is an illustration of the hard mask layer <NUM> after it has been patterned with a hard mask etching process in order to form the isolated hard mask features <NUM> and the nested hard mask features <NUM>.

Due to the variability in the micro loading effects resulting from the non-uniform pitch, the hard mask etching process must be controlled to ensure that the lateral etching rate of the isolated features <NUM> and the nested features <NUM> are uniform. The lateral etching rate of the hard mask etching process is dependent on the passivation of the sidewalls and the rate at which the active species from the plasma can etch away the hard mask material. The variable pitch across the substrate <NUM> results in there being fins that are more accessible to the active species thereby causing these fins to etch faster. Additionally, the polymer deposition rate along the sidewalls of the fins is also dependent on pitch. Accordingly, without control of the polymer deposition, the width of the isolated features and nested features may be non-uniform as a result of different lateral etch rates.

In a fluorine based plasma, increases in the concentration of hydrogen in the plasma result in an increase in the rate of polymerization. Increased polymerization improves the passivation of the sidewalls of the hard mask fins that are formed during the hard mask etching process. The additional hydrogen present in the plasma scavenges fluorine from the plasma and results in a more carbon-rich plasma. The excess carbon in the plasma is able to form nonvolatile molecules that passivate the surfaces and prevent etching. The passivation layer forms primarily on the sidewalls because the portions of the passivation layer that are disposed on horizontal surfaces are removed by ion bombardment. Accordingly, the increase in polymerization will increase the sidewall passivation and improve the anisotropic nature of the etching chemistry. The improvement in the anisotropic nature of the etching process improves the uniformity in the width of the isolated hard mask features WHM-I and the nested hard mask features WHM-N.

However, increases in the concentration of hydrogen in the plasma also results in a decrease in the etch selectivity of the hard mask layer <NUM> over the dummy hard mask <NUM> according to embodiments with a nitride hard mask layer <NUM> and an oxide dummy hard mask <NUM>. Since the presence of excess hydrogen scavenges fluorine, the fluorine concentration drops. At lower concentrations of fluorine, the etch rates of the nitride hard mask <NUM> and the oxide dummy hard mask <NUM> become less selective to each other. Accordingly, oxygen can be added into the plasma to counteract this effect. When there is an increase in the oxygen content of the plasma, the oxygen scavenges carbon atoms to produce volatile CO and C0<NUM> which can be pumped out of the chamber. As such, the fluorine concentration of the plasma is increased and the additional reactive ions increase the etch rate of the nitride hard mask layer <NUM> greater than they increase the etch rate of the oxide dummy hard mask <NUM>. Therefore, in order to transfer the pattern of the dummy hard mask <NUM> into the hard mask layer <NUM> without causing the micro loading effects to result in different widths of the isolated and nested features, a proper ratio of hydrogen to oxygen must be maintained within the plasma.

Under typical etching conditions, such as an etching chemistry that utilizes CHF<NUM> as the fluorine source, the micro loading effects generally cause the width of nested hard mask fins <NUM> to be smaller than the width of the isolated hard mask fins <NUM>. Accordingly, the amount of passivation on the sidewalls of the nested hard mask fins is less than the amount of passivation on the sidewalls of the isolated hard mask fins. This problem may be overcome by providing an etching chemistry that increases the sidewall passivation. Therefore, embodiments of the invention utilizes an etching chemistry comprising a higher concentration of hydrogen than the concentration oxygen. It is possible to utilize gases such as CH<NUM>F or CH<NUM>F<NUM> in order to increase the hydrogen concentration of the plasma relative to etching chemistries that utilize CHF<NUM> as the fluorine source. As explained above, the increase in hydrogen causes fluorine to be scavenged from the plasma and allows for an increase in the carbon concentration. The increased carbon concentration increases the amount of passivation on the sidewalls.

However, it should be noted that if the hydrogen concentration is increased too much, then the opposite effect on the widths of features <NUM>, <NUM> will be seen. In these instances, the nested features <NUM> will have a lower lateral etch rate than the lateral etch rate of the isolated features <NUM>, because the passivation rate of the nested features will increase. This will result in thicker nested features <NUM> and thinner isolated features <NUM>. Therefore, in order to balance the etching rates and produce uniform widths WHM-I and WHM-N , it is desirable to balance the increase in the hydrogen content by also incorporating oxygen into the plasma. In particular, uniform widths WHM-I and WHM-N for isolated and nested features <NUM>, <NUM> may be obtained when the ratio of hydrogen to oxygen (H:<NUM>) in the plasma is maintained between approximately <NUM>: <NUM> and <NUM>: <NUM>. In order to achieve the hydrogen to oxygen ratios described by embodiments of the invention, a gas mixture including <NUM><NUM>, Ar, and CH<NUM>F may be used where the flow rate of the <NUM><NUM> is between approximately <NUM> sccm and sccm the flow rate of the CH<NUM>F is between approximately <NUM> sccm and <NUM> sccm, and the flow rate of the Ar is between approximately <NUM> sccm and <NUM> sccm.

Embodiments of the invention utilize a total pressure between <NUM> mTorr and <NUM> mTorr, whereby <NUM> Torr = (<NUM>/<NUM>) Pa, in the processing chamber during the hard mask etching process. Additional embodiments of the invention may utilize a total pressure of approximately <NUM> mTorr in the processing chamber during the hard mask etching process.

It is possible to include utilizing different process gas flow rates across the surface of the substrate during processing. It is possible to include a process gas flow rate that is higher proximate to the center of the substrate relative to the flow rate proximate to the edge of the substrate. The ratio of the center gas flow rate to the edge gas flow rate may be approximately <NUM>%. By way of example, and not by way of limitation, if the <NUM><NUM> flow rate is <NUM> seem total, then the center <NUM><NUM> flow rate may be <NUM> sccm and the edge <NUM><NUM> flow rate may be <NUM> sccm.

It also is possible to control the widths WHM-I and WHM-N of the hard mask features <NUM>, <NUM> by controlling the temperature of the chuck that supports the substrate during the hard mask etching process. It is possible to include maintaining the temperature of the chuck between <NUM> and <NUM> during the hard mask etching process.

Additionally , it is possible to include maintaining the temperature of the chuck at approximately <NUM> during the hard mask etching process.

Referring back to <FIG>, the method of forming high aspect ratio fins <NUM> proceeds to block <NUM> where a break through etching process is performed.

The break through etching process selectively removes portions of etch stop layer <NUM> between the hard mask features <NUM>, <NUM> in order to expose the top surface of the semiconductor substrate <NUM>. According to an embodiment of the invention, the break through etching process may include a chemistry comprising CF<NUM>, Cl<NUM>, and an Ar-CH<NUM> mixture. By way of example, and not by way of limitation, the CF<NUM> may have a flow rate of approximately <NUM> sccm, the Cl<NUM> may have a flow rate of approximately <NUM> scccm, seem, and the Ar-CH<NUM> mixture may be approximately <NUM>% CH<NUM> and have a flow rate of approximately <NUM> sccm.

According to an embodiment, the total pressure during the break through etching process may be approximately <NUM> mTorr.

After the break through etching process has been performed the method of forming the high aspect ratio fins <NUM> proceeds to block <NUM> where a first substrate etching process is performed to etch into the substrate <NUM> to a first depth Di according to an embodiment of the invention. As shown in <FIG>, the first depth Di is measured from the top surface of the substrate <NUM> to the bottom of the trench between each of the fins <NUM>. Embodiments of the invention include a first depth Di that is between <NUM> and <NUM>. Also, it is possible to include a first depth Di that is between <NUM> and <NUM>. According to an embodiment of the invention, the etching process is highly anisotropic and the widths of the isolated and nested fins Wi and W are substantially preserved. However, micro loading effects present due to the smaller pitch in the nested fins <NUM>N may produce differences in the fin widths WN and WI between the nested fins <NUM>N and the isolated fins <NUM>I.

Therefore, it is possible to utilize an etching chemistry comprising HBr, <NUM><NUM> and CF<NUM> to minimize this effect. The HBr may have a flow rate of approximately <NUM> sccm, the <NUM><NUM> may have a flow rate of approximately <NUM> sccm, and the CF<NUM> may have a flow rate of approximately <NUM> sccm.

According to an embodiment of the invention the total pressure of during the first substrate etching process may be approximately <NUM> mTorr. The <NUM><NUM> functions as a passivating agent that improves the polymerization of the sidewalls. Even though the sidewalls are passivated by the <NUM><NUM>, the sidewalls of the nested fins etch at a faster rate than the sidewalls of the isolated fins, because the lateral passivation rate is greater for isolated fins <NUM>I than the lateral passivating rate for nested fins <NUM>N.

By way of example, and not by way of limitation, the isolated fins may be approximately <NUM> thicker after the first substrate etching process.

Referring back to <FIG>, after the first depth D<NUM> has been reached, the method for forming high aspect ratio fins <NUM> then proceeds to block <NUM> where a second substrate etching process is implemented, wherein the second substrate etching process etches through the substrate <NUM> to a second depth D<NUM> from the top surface of the substrate, as shown in <FIG>. Embodiments of the invention include a second depth that is between <NUM> and <NUM>. Also, it is possible to include a second depth that is between <NUM> and <NUM>. In addition to providing the desired depth, the second substrate etching process also equalizes the widths WN, Wi of the nested fins <NUM> IN and the isolated fins <NUM>I. It is possible that the second substrate etching process equalizes the widths WN and Wi by utilizing an etching chemistry that has a slower lateral etch rate for the nested fins <NUM>N than the lateral etch rate for the isolated fins l l li. Embodiments of the invention utilize an etching chemistry comprising Cl<NUM>, Ar, and CH<NUM>. It is possible to utilize a process gas flow rate that provides a greater concentration of Cl<NUM> compared to the concentration of the Ar and CH<NUM> in order to ensure that the sidewalls of the nested fins <NUM>N are etched at a slower rate than the sidewalls of the isolated fins <NUM>I. The isolated fins <NUM>I are more accessible to the chlorine species, and as such, they have a greater lateral etch rate. Embodiments of the invention utilize a flow rate of approximately <NUM> seem for the Cl<NUM> and approximately <NUM> sccm for the combination of Ar and CH<NUM> in order to maintain the proper ratio of Cl<NUM> to Ar/CH<NUM>. The total pressure of the processing chamber may be maintained between approximately <NUM> mTorr and <NUM> mTorr.

As noted above, the first substrate etching process may passivate the sidewalls of the isolated fins <NUM>I faster than the sidewalls of the nested fins <NUM>N, and the second etching process may etch the sidewalls of the isolated fins <NUM>I faster than the sidewalls of the nested fins <NUM>N.

Accordingly, if the first depth D<NUM> is chosen too shallow, then the fins may have an undercut, because the second substrate etching process will etch the sidewalls for a longer period before the second depth D<NUM> is reached. Alternatively, if the first depth is chosen to be too deep, then the fins may have a footing. The presence of a footing may result from there not being sufficient time to allow the fins <NUM> to have their sidewalls etched to the proper thickness before the second depth D<NUM> is reached. Therefore, according to various embodiments, the first depth is chosen to be between <NUM> and <NUM> in order to ensure that the fins <NUM> have widths WI and WN that are substantially equal to each other.

Furthermore, it is possible to control s the uniformity of widths WI and WN of the high aspect ratio fins by controlling the RF power source of the plasma etching chamber during the first and second substrate etching processes. It is possible that the RF power source is pulsed during the first and second substrate etching processes. Pulsing the RF power source allows for improved control of the desired anisotropic behavior of the etching processes. During the formation of high aspect ratio fins <NUM>, the reactive etchant species may be quickly depleted at the bottom of the trenches between the fins <NUM>. Pulsing the RF power source allows for more reactive etchant species to reach the bottom of the trench and prevents micro-trenching. The etchant species are drawn down into the trench when the RF power source is on. When the RF power source is off, the bi-products from the etching process are able to escape from the trench. Accordingly, reactant species at the bottom surface of the trench do not become depleted. It is possible that the RF power is pulsed with a duty cycle that includes the RF power being on between <NUM>- <NUM>% of the time and off for the remainder of the time, and at frequency between approximately <NUM> and <NUM>. According to an embodiment of the invention, the duty cycle and frequency used for the first substrate etching process may be different than the duty cycle and frequency used for the second substrate etching process.

The temperature of the chuck supporting the substrate may also be controlled during the first and second substrate etching processes of the in order to improve the uniformity in the width of the fins across the surface of the substrate. The fins that are proximate to the edge of the substrate typically experience different etch rates than the fins proximate to the center of the substrate. Accordingly, the temperature across the substrate may be varied to account for these differences. It is possible that the temperature of the chuck supporting the substrate is maintained at a higher temperature proximate to the center of the substrate relative to the temperature of the chuck proximate to the edge of the substrate. The temperature of the chuck proximate to the center of the substrate may be maintained at a temperature that is approximately <NUM> greater than the temperature of the chuck proximate to the edge of the substrate. According to an embodiment of the invention, the chuck may be maintained at approximately <NUM> proximate to the center of the substrate, and the chuck may be maintained at approximately <NUM> proximate to the edge of the substrate.

It is possible that the uniformity of the fins formed across a substrate further improved by controlling the plasma density during the first and second substrate etching processes. As used herein, plasma density refers to the density of the ions and radicals present in the plasma. By way of example, a high density plasma would have a greater concentration of ions and radicals per unit area than a low density plasma. In order to account for differences in the etch rates across the surface of the substrate, the plasma density may be varied above different portions of the substrate. The plasma density may be varied by altering the magnetic field of the plasma processing chamber. The plasma density above the center of the substrate may be higher than a plasma density above the edge of the substrate. According to an embodiment of the invention the plasma density may be approximately <NUM>% to <NUM>% higher above the center of the substrate.

Referring now to <FIG>, a cross-sectional view of a high aspect ratio fin based semiconductor device <NUM> is shown Fin based device <NUM> includes a plurality of fins <NUM> formed on a semiconductor substrate <NUM>.

The semiconductor substrate <NUM> is composed of a material suitable for semiconductor device fabrication. In an embodiment, the semiconductor substrate <NUM> is a monocrystalline silicon substrate. In an embodiment, the structure is formed using a bulk semiconductor substrate. Substrate <NUM> may also be, but is not limited to, germanium, silicon-germanium, or a III-V compound semiconductor material. In another embodiment, the structure is formed using a silicon-on-insulator (SOI) substrate.

Fins <NUM> are high aspect ratio fins. It is possible to include fins with heights if that are <NUM> or greater.

Additionally, is possible to include fin widths W that are less than <NUM>. Embodiments of the invention further include fin widths that are less than <NUM>.

As shown in <FIG>, embodiments of the invention include one or more isolated fins <NUM>I and one or more nested fins <NUM>N. A nested fin is a fin that has neighboring fins <NUM> that are formed close enough to have an effect on the etching rate (in the lateral and/or vertical direction) of the nested fin 11I. By way of example, and not by way of limitation, neighboring fins may alter the etch rate of a fin by producing different active ion accessibility at the surface of the substrate during an etching process, or by changing the polymer deposition rate along the sidewalls of the fin. A group of nested fins may have a non-uniform pitch, so long as the fins are spaced close enough together to effect the etching rate of neighboring fins.

An isolated fin fin does not have neighboring fins formed close enough to have an effect on the etching rate of the isolated fin.

As shown in <FIG>, nested fins are formed with a pitch PN, and the isolated fin is formed with a pitch Pi.

It is possible that Pi is at least one and a half times as large as PN.

By way of example, and not by way of limitation, PN may be approximately <NUM> and Pi may be approximately <NUM>. The outermost fins of a set of nested fins, such as fin <NUM> in <FIG>, may be considered semi-nested. As such, the sidewall proximate to the nested fins 11IN has similar etching characteristics to the nested fins, and the sidewall proximate to the isolated fin 11li has similar etching characteristics to the isolated fins.

Isolated fins and nested fins are alike, with the exception of their spacing from adjacent fins <NUM>.

The uniform shape and width of the isolated and the nested fins <NUM><NUM>, 11IN allows for the use of multi-fin devices that have uniform metrics, such as threshold voltage and leakage current. As such, uniform width in nested and isolated fins allows for the use of isolated fins in circuitry, such as an IC device.

Referring now to <FIG>, one or more transistor devices are shown formed on the isolated and nested. The transistor devices may include fin-FET devices, such as a tri-gate device, formed on the fins <NUM>. As shown in <FIG>, a shallow trench isolation (STI) layer <NUM> is disposed above the substrate <NUM> and between the fins <NUM>. The STI layer <NUM> may be a silicon dioxide, or the like, as is known in the art. A gate dielectric <NUM> may be disposed over the portions of the fins <NUM> that extend above the STI layer <NUM>. A gate metal <NUM>, may be disposed over each fin <NUM>. As shown in in <FIG>, It is possible to include a single block of gate metal <NUM> disposed over the nested fins.

The gate metal <NUM> over the isolated fin is isolated from other gates.

Therefore, the transistor device formed on the isolated fin <NUM> li can be controlled independent of the nested fins.

Though not shown in the cross-sectional view of <FIG>, those skilled in the art will recognize that source/drain (S/D) regions may be formed in the fins <NUM> on opposing sides of the gate metal (i.e., into the plane of the page and out of the plane of the page). The fins may be suitably doped with n-type and/or p-type dopants in order to form n-MOS and/or P-MOS devices.

Furthermore, those skilled in the art will recognize that high aspect ratio fins described are not limited to use with electrical devices and may also be utilized in nanostructures such as those used in nanoelectromechanical systems (NEMS).

<FIG> illustrates a computing device <NUM> in accordance with one implementation.

The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors formed on high aspect ratio fins formed in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors formed on high aspect ratio fins formed in accordance with implementations of the invention.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors formed on high aspect ratio fins formed in accordance with implementations of the invention.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.

In further implementations, the computing device <NUM> may be any other electronic device that processes data.

Claim 1:
A semiconductor structure obtained by the method of claim <NUM>, comprising:
a monocrystalline silicon substrate (<NUM>);
a nested grouping of monocrystalline silicon fins (<NUM>N), and a monocrystalline silicon isolated fin (<NUM>I), the nested groping of fins and the isolated fin extending from the monocrystalline silicon substrate, and a shallow trench isolation layer (<NUM>) being deposited on the substrate and between all the fins; the nested grouping of monocrystalline silicon fins comprising:
a first monocrystalline silicon fin having a top and laterally opposite sidewalls and having a shape, a width, a height, and a height to width aspect ratio, wherein the width is less than <NUM> nanometers, the height is greater than <NUM> nanometers, and wherein the height to width aspect ratio is greater <NUM>:<NUM>;
a second monocrystalline silicon fin having a top and laterally opposite sidewalls and having the shape, the width, the height and the height to width aspect ratio; and
a third monocrystalline silicon fin having a top and laterally opposite sidewalls and having the shape, the width, the height and the height to width aspect ratio; wherein the third monocrystalline silicon fin is laterally directly adjacent the second monocrystalline silicon fin at the first pitch PN, and wherein the second monocrystalline silicon fin is laterally directly adjacent the first monocrystalline silicon fin at the pitch PN; and
the isolated monocrystalline silicon fin having the shape, the width, the height and the height to width aspect ratio, and the isolated monocrystalline silicon fin laterally directly adjacent the first monocrystalline silicon fin at a second pitch PI greater than <NUM> times the first pitch PN.