Patent Description:
A SAR ADC converts an analog input voltage signal to a digital output value, sometimes referred to as a code, by successively comparing the input to an internally-generated and changing reference voltage. For each successive comparison, the reference voltage is adjusted to converge toward the value of the analog input voltage signal, while each such adjustment and comparison determines a respective bit of the SAR ADC output code. Further, as the differential between the input and reference voltage thus converges, the reference voltage change is smaller in each successive comparison, and the smaller reference voltage and differential is therefore more susceptible to error.

A SAR ADC may be embodied as, or part of, an integrated circuit (IC). Accordingly, IC design considerations are factors for the SAR ADC, such as area and power consumed by the device. Further, as SAR ADCs have advanced, for example operating at higher speed and with a greater number of output bits, additional design considerations are directed to output accuracy. For example, noise impacts the SAR ADC input signal, its components that process the input signal, and the proper assessment of the converging differential between the input signal and reference voltage. Accordingly, noise effects may be considered to the extent those can cause a signal state change greater than the least significant bit (LSB) resolution of the device, potentially producing an error in the output or limiting the resolution of the output code.

While the preceding considerations are generally common to most SAR ADCs, different designers may prioritize different design considerations, for example considering different sources of noise and designs to mitigate nose effects. Accordingly, examples are provided in this document that may improve on various of such noise considerations as well as other concepts, as further described below. <CIT> discloses a successive approximation A/D converter circuit and a semiconductor integrated circuit. Further, <CIT> discloses an analog to digital converter adapted to perform a first part of a conversion as a successive approximation conversion and a second part of a conversion as a sigma-delta conversion. Moreover, <CIT> discloses methods and apparatus for reducing thermal noise.

Other aspects are also described and claimed.

<FIG> illustrates a schematic of an example embodiment SAR ADC <NUM>. SAR ADC receives an analog input voltage VIN at an input node <NUM> and ultimately produces, in an N-bit register <NUM>, a CODE corresponding to the magnitude of VIN. Particularly, VIN is connected to the input node <NUM>, which is a first of two switch throws of an input switch <NUM>. The input switch <NUM> has a pole connected to a first plate of a sample capacitor <NUM>, and the input switch <NUM> has a second throw connected to an output node <NUM> of a digital-to-analog converter (DAC) <NUM>. A second plate of the sampling capacitor <NUM> is connected to a throw of a first bias switch <NUM>, and the throw of the first bias switch <NUM> is connected to receive a bias voltage Vbias through the first bias switch <NUM>. The throw of the first bias switch <NUM> also is connected as an input to a comparator <NUM>. The output of the comparator <NUM> is connected to the register <NUM>. A first output <NUM> of the register <NUM> provides the CODE output once the SAR ADC <NUM> completes its conversion of VIN, and a second output <NUM> of the register <NUM> provides the CODE output, as it is being determined in its entirety, to the input of the DAC <NUM>. It is noted that the capacitance of the sampling capacitor <NUM> may be implemented as part of the same capacitor, or capacitive element(s), as the DAC <NUM>, although for sake of simplification in this document those are shown as separate structures. It is further noted that the illustrated switches (including the input switch <NUM> and the first bias switch <NUM>) are functional representations that may be implemented using a variety of circuit elements, such as transistors.

The general operation of the SAR ADC <NUM> is as follows, with additional structural and operational details provided later. The SAR ADC <NUM> in a first phase samples VIN and then in a second phase performs conversion by iteratively comparing the sampled VIN to different internally-generated reference voltages, provided from the DAC <NUM>. Transitions between the sample phase and iterative conversion phase are executed in part by the input switch <NUM> and the first bias switch <NUM>, as described later. Further, the overall SAR ADC <NUM> operation is improved by implementing into the sample phase an auto zeroing (AZ) sample phase noise suppression (AZSPNS) aspect, shown generally in <FIG> as a control input to the comparator <NUM> and also described later. Together, the sample phase and one or more iterative conversion phases determine a successive bit stored in the N-bit register <NUM>, where completion of all iterations completes the total number of N bits in the register <NUM> as the CODE at the output <NUM>. For example, VIN is sampled in a sample phase and then in a first iteration of the conversion phase, the sample VIN is compared, by the comparator <NUM>, to an analog reference voltage Varef, where Varef is output by the DAC <NUM> in response to a CODE then in the register <NUM>. For instance, in the first iteration of the conversion phase, the most significant bit (MSB) of the N-bit value in the register <NUM> is set high, while all lesser significant bits in the register <NUM> are low. So, in this conversion phase first iteration, the SAR ADC <NUM> compares VIN to the voltage Varef which corresponds to the MSB-high value in the N-bit register <NUM>. If VIN is greater in that comparison, then the MSB is left (or overwritten) high and the next lesser significant bit is set for the next conversion phase iteration. If VIN is lesser in that comparison, then the MSB is zeroed and the next lesser significant bit is set for the next conversion phase iteration. The above process repeats for each successive iteration, until all Nbits in the N-bit register <NUM> have been set to establish a corresponding Varef that is compared to VIN as has been described. Upon completion of all iterations, the N-bit value in the N-bit register <NUM> is output as the CODE and is representative of the magnitude of VIN.

<FIG> illustrates a schematic of the SAR ADC <NUM>, with additional details shown for the comparator <NUM>. The comparator <NUM> includes an amplification stage <NUM>, which by way of example is shown to include a single amplifier <NUM>. The amplifier <NUM> is shown to receive AZSPNS, as the electrical attributes of the amplifier <NUM> are selectively adjusted as described later, for example to be different during the sample phase as compared to the conversion phase, where the adjustment further improves the AZ performance of the SAR ADC <NUM>. An input of the amplifier <NUM> is connected to the throw of the first bias switch <NUM>, and an output of the amplifier <NUM> is connected to a first plate of an AZ capacitor <NUM>. The second plate of the AZ capacitor <NUM> is connected to a throw of an AZ switch <NUM>. The AZ switch <NUM> pivots in the direction shown, by an AZSPNS arrow, during sample phase auto zeroing. The pole of the AZ switch <NUM> is connected to Vbias. The throw of the AZ switch <NUM> also is connected as an input to a latch <NUM>. An output of the latch <NUM> is the output of the comparator <NUM> and, as introduced earlier, is connected to the N-bit register <NUM>. The latch <NUM> may operate as a threshold detector, so that if its input is below a threshold, then the latch output is a logic low, or if its input is above that threshold then the latch output is a logic high. Alternatively, the amplifier <NUM> may consist of multiple capacitively coupled stages connected in cascade, with each stage having an AZ switch at its input. The coupling capacitor of the last of these cascaded stages is connected to the input of the latch <NUM>.

<FIG> illustrates the <FIG> schematic of the SAR ADC <NUM>, with its three switches positioned to operate in the sample phase. In the sample phase, two different voltages are sampled and stored on respective capacitors. Specifically, the input switch <NUM> connects VIN to the first plate of the sampling capacitor <NUM>, while the first bias switch <NUM> connects Vbias both to amplifier <NUM> (or multiplier amplifiers, if applicable) and to the second plate of the sampling capacitor <NUM>, thereby providing a low impedance to that capacitor plate. Thus, Vbias serves the dual purpose of biasing the amplifier <NUM> and providing a low impedance to the capacitor <NUM>. Accordingly, VIN is sampled to the sampling capacitor <NUM>. AZSPNS is also asserted during the sample phase, to position (close) the AZ switch <NUM> and to control the amplifier <NUM>, the latter selectively adjusting electrical attributes during the sample phase to further improve noise immunity, as described later. Particularly, during the sample phase, the AZSPNS-controlled amplifier <NUM> outputs an AZ voltage Vaz to the first plate of the of the AZ capacitor <NUM> that, with the AZ switch <NUM> closed and thereby connecting the low impedance of Vbias to the second plate of that capacitor, then Vaz is sampled to that AZ capacitor <NUM>. The closed AZ switch <NUM> also connects Vbias to the input of the latch <NUM>, to bias the input of the latch <NUM> for correct operation during the conversion phase. By virtue of the fact that the input of the amplifier <NUM> is connected to a constant voltage Vbias during the sampling phase, Vaz represents the offset plus noise of the amplifier <NUM>.

<FIG> illustrates the <FIG> schematic of the SAR ADC <NUM>, with its three switches positioned opposite to that in <FIG>, so that in <FIG> the SAR ADC <NUM> operates iteratively in the conversion phase. In the conversion phase, the input switch <NUM> connects the DAC <NUM> analog reference voltage Varef to the sampled voltage VIN already on the sampling capacitor <NUM> from the immediately-preceding sample phase. Accordingly, the difference of those two voltages, Varef-VIN, is input to the comparator <NUM> and thereby to its amplifier <NUM>. Recalling from the above that in the first conversion phase iteration Varef is approximately one-half the voltage capacity of the DAC <NUM>, then the difference provided by Varef- VIN is essentially a comparison of those two voltages, whereby if the difference is positive then Varef is larger than VIN, and if the difference is negative then VIN is larger than Varef. At the same time, AZSPNS is de-asserted, thereby selectively adjusting conversion phase electrical attributes of the amplifier <NUM> to differ from those of the sample phase. Accordingly, the amplifier <NUM> operates under the conversion phase electrical attributes to output a voltage G(VIN-Vref), where G is the gain of the amplifier <NUM> and (VIN-Vref) is the input voltage to the amplifier <NUM>. The output voltage G(VIN-Vref) is coupled to the AZ capacitor <NUM>, which recall in the preceding sample phase stored an AZ voltage, Vaz. Accordingly, in the conversion phase, Vaz is subtracted from G(VIN-Vref), thereby essentially zeroing the effect that the offset and noise of the amplifier <NUM> otherwise would have on the operation of the SAR ADC <NUM>. Further, the differential voltage (G(VIN-Vref) - Vaz) from the AZ capacitor <NUM> is connected to the input of the latch <NUM>. The latch <NUM> outputs either a logic low or high based on whether (G(VIN-Vref) - Vaz) exceeds a threshold limit of the latch <NUM>, and that logic value is written to the bit position in the N-bit register <NUM> that was originally high for the current conversion phase iteration.

The preceding description of the first conversion phase iteration of the SAR ADC <NUM> repeats so that in total N conversion phase iterations occur, each iteration corresponding to a respective bit in the N bits of the N-bit register <NUM>. Accordingly, following the first iteration, N-<NUM> successive iterations occur, where each iteration is for a next less significant bit in the N-bit register <NUM> and until all N bits in the register <NUM> have been processed through respective conversion phase iterations. At the completion of those operations, the N bits in the N-bit register <NUM> present a digital approximation of VIN, and are provided to the output <NUM> as the CODE.

<FIG> illustrates a schematic of the amplifier <NUM> (<FIG>) in greater detail, further elaborating on an example embodiment for the structure for, and method of operation of, the selective adjustment of the amplifier <NUM> electrical attributes to be different during the sample phase versus the conversion phase. For reference to prior Figures, <FIG> also includes, outside of the amplifier <NUM>, the first bias switch <NUM> and the AZ capacitor <NUM>. The throw of the first bias switch <NUM> is connected to the input of 202IN of the amplifier <NUM>. The input 202IN is connected to an input of a transconductor <NUM>, which in conjunction with a resistor <NUM>, provides the earlier-introduced gain G. The output of the transconductor <NUM> is connected to a node <NUM>. The node <NUM> is connected through the resistor <NUM> to ground. The node <NUM> is also connected to a pole of a noise-suppression switch <NUM>. The noise-suppression switch <NUM> closes during sample phase auto zeroing when AZSPNS is asserted (and opens when de-asserted). The throw of the noise-suppression switch <NUM> is connected through a capacitor <NUM> to ground. The node <NUM> is also connected to the input of a zero-unity buffer <NUM>, and the output of the zero-unity buffer <NUM> provides the output of the amplifier <NUM>.

The operation of the <FIG> amplifier <NUM> in general is described earlier, with additional description now regarding the selective adjustment of its electrical attributes during the sample phase versus the conversion phase.

During the sample phase, recall that AZ is concurrently implemented and AZSPNS is asserted. Accordingly in <FIG>, during the sample phase, the capacitor <NUM> is connected through the noise-suppression switch <NUM> to the node <NUM>, (e.g., connected in the amplifier output and in parallel with the resistor <NUM> to ground). With both the resistor <NUM> and the capacitor <NUM> connected to the output of the transconductance <NUM>, the electrical attributes of the amplifier <NUM> are selectively adjusted, namely, the 3dB cutoff corner of the amplifier <NUM> is reduced. Accordingly, the lower 3dB cutoff corner reduces the amplifier bandwidth (excludes higher frequencies), as compared to an instance where the node <NUM> is not capacitively coupled to ground in this manner. Relatedly, as known in the art, the transconductance of an amplifier (e.g., the transconductance <NUM>) provides thermal noise. In the illustrated embodiment, however, the sample phase selectively-reduced bandwidth, provided here by including the capacitance of the capacitor <NUM> during the sample phase AZ operation, filters out a higher-frequency portion of the amplifier thermal noise. This in turn reduces the amount of thermal noise energy that otherwise would appear in Vaz (see <FIG>). Accordingly, with the <FIG> switched-in capacitance, Vaz is generated as and represents a thermal noise suppressed AZ voltage, that is buffered by the buffer <NUM> and then stored, as shown in <FIG>, to the AZ capacitor <NUM>.

As described above, a number N of conversion phase iterations follow the sample phase. In the conversion phase iterations, recall that AZSPNS is de-asserted, and as a result in <FIG> the noise-suppression switch <NUM> opens and the capacitor <NUM> is disconnected from the node <NUM>, thereby increasing the bandwidth of the amplifier <NUM> and also allowing the conversion phase iterations to occur at a speed not reduced as it would be were the capacitor <NUM> part of the amplification output during that phase. Accordingly, the conversion phase proceeds as described earlier, with the improvement that the AZ functionality provided by the voltage Vaz, stored on the AZ capacitor <NUM>, will offset the output of the amplifier <NUM> more favorably due to the noise suppression of reduced bandwidth during the immediately preceding sample phase. More particularly, traditional AZ is directed to either DC or relatively low frequency (e.g., <NUM> or less, sometimes referred to as flicker) noise, which noise is relatively constant over relatively long periods of time, as compared to the sample rate of the SAR ADC which may be on the order of hundreds of KHz to several MHz. Accordingly, such traditional AZ approaches may store such noise to an offset capacitor, which is then auto-zeroed in a subsequent phase. At the same time as the longer duration noise, however, higher frequency noise also can appear from thermal noise, and the long duration period of storing the traditional AZ offset can or will include the higher-frequency thermal noise, which indeed can be fairly inconsistent from phase to phase given the relatively high frequency nature of thermal noise, as compared to DC and flicker noise. In other words, the higher frequency thermal noise during sampling does not necessarily correlate to the same noise, and its offset, during conversion. The example embodiment, therefore, reduces the storage of high frequency noise during AZ by selectively adjusting the electrical attributes of the amplification stage <NUM> during AZ, thereby improving the signal-to-noise ratio (SNR) of the SAR ADC <NUM> when it switches to the conversion phase. Accordingly, device operation, such as data conversion accuracy, is improved.

Claim 1:
A successive approximation analog-to-digital converter (<NUM>), comprising:
an input (<NUM>) for receiving an input analog voltage (VIN);
a first capacitor (<NUM>) including a first plate and a second plate, the first plate coupled to the output of an input switch (<NUM>) and the second plate coupled to a first switch (<NUM>); and
the first switch (<NUM>);
a comparator (<NUM>) including:
a third switch (<NUM>) that includes:
an input coupled to receive a bias voltage (Vbias); and
an output coupled to a latch (<NUM>) of the comparator (<NUM>);
a third capacitor (<NUM>) including a first plate and a second plate, the first plate coupled to an output of an amplifier (<NUM>) and the second plate coupled to the third switch (<NUM>); wherein the latch (<NUM>) is coupled to the third capacitor (<NUM>);
and
the amplifier (<NUM>) that includes:
a transconductor (<NUM>) coupled to the first capacitor (<NUM>);
a buffer (<NUM>) coupled to the transconductor (<NUM>);
a second capacitor (<NUM>); and
a second switch (<NUM>) including a first and a second terminal, the first terminal being coupled to the buffer (<NUM>) and to the transconductor (<NUM>) and the second terminal being coupled to the second capacitor (<NUM>);
sample phase circuitry comprising the amplifier (<NUM>) and for providing the bias voltage (Vbias) to the second plate of the first capacitor (<NUM>) through the first switch (<NUM>) and to the second plate of the third capacitor (<NUM>) through the third switch (<NUM>) in a sample phase and for providing the amplifier (<NUM>) with a first set of electrical attributes and for sampling the input analog voltage (VIN) in the sample phase, the amplifier (<NUM>) configured to close the second switch (<NUM>) to connect the second capacitor (<NUM>) to the transconductor (<NUM>) in the sample phase; and
conversion phase circuitry comprising the amplifier (<NUM>), and for providing the amplifier (<NUM>) with a second set of electrical attributes differing from the first set of electrical attributes and for converting a comparison, of the sampling of the input analog voltage (VIN) relative to a reference voltage (Varef), to a digital value (CODE) in a conversion phase, the amplifier (<NUM>) configured to open the second switch (<NUM>) to disconnect the second capacitor (<NUM>) from the transconductor (<NUM>) in the conversion phase.