Patent Description:
Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, <CIT> discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published <CIT> discloses a CMOS inverter also based upon similar strained silicon technology.

<CIT> discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.

<CIT> discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

<CIT> discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, <CIT> discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.

<CIT> discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO2/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.

An article entitled "<NPL> discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices. In particular, a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a <NUM> thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to <NPL>) further discusses the light emitting SAS structures of Tsu.

<CIT> discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.

Published Great Britain Patent Application <CIT> discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.

Furthermore, <CIT> discloses a method for producing an insulating or barrier layer for semiconductor devices which includes depositing a layer of silicon and at least one additional element on the silicon substrate whereby the deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite.

<CIT> discloses a semiconductor device which includes a superlattice that, in turn, includes a plurality of stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon.

<CIT> discloses a silicon-on-insulator device with a buried depletion shield layer.

Despite the existence of such approaches, further enhancements may be desirable for using advanced semiconductor materials and processing techniques to achieve improved performance in semiconductor devices.

A semiconductor device according to the invention includes a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device includes a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice within the semiconductor layer and extending through the body contact to divide the body contact into a first body contact region and a second body contact region, with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The semiconductor device further includes a metal contact on the second body contact region. The body contact dopant diffusion blocking superlattice includes a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

In one example embodiment, the source and drain regions and the body contact may be on a top side of the semiconductor layer. In accordance with another example embodiment, the source and drain regions may be on the top side of the semiconductor layer, and the body contact may be on a back side of the semiconductor layer opposite the top side.

The second body contact region may be level with a second surface of the semiconductor layer in one example embodiment. In accordance with another example, the second body contact region may be raised above a second surface of the semiconductor layer. Furthermore, the first body contact region may comprise a different material than the second body contact region. For example, the first body contact region may comprise silicon, and the second body contact region may comprise silicon germanium. In accordance with another example, the first body contact region may comprise silicon germanium, and the second body contact region may comprise silicon.

By way of example, the metal contact may comprise at least one of titanium, cobalt, nickel and platinum. Also by way of example, the base semiconductor monolayers may comprise silicon, and the at least one non-semiconductor monolayer may comprise oxygen.

A method for making a semiconductor device according to the invention includes forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method further includes forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice within the semiconductor layer and extending through the body contact to divide the body contact into a first body contact region and a second body contact region, with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The method further includes forming a metal contact on the second body contact region. The body contact dopant diffusion blocking superlattice includes a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which the example embodiments are shown. The embodiments may, however, be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime and multiple prime notation are used to indicate similar elements in different embodiments.

Generally speaking, the present disclosure relates to utilizing enhanced superlattice materials within source and drain regions to reduce Schottky barrier height and thereby decrease source and drain contact resistance. The enhanced semiconductor superlattice is also referred to as an "MST" layer or "MST technology" in this disclosure and the accompanying drawings.

More particularly, the MST technology relates to advanced semiconductor materials such as the superlattice <NUM> described further below. Applicant theorizes, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a "conductivity reciprocal effective mass tensor", <MAT> and <MAT> for electrons and holes respectively, defined as: <MAT> for electrons and: <MAT> for holes, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B. ), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.

Applicant's definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicant theorizes without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.

Applicant has identified improved materials or structures for use in semiconductor devices. More specifically, Applicant has identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

Referring now to <FIG> and <FIG>, the materials or structures are in the form of a superlattice <NUM> whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice <NUM> includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of <FIG>.

Each group of layers 45a-45n of the superlattice <NUM> illustratively includes a plurality of stacked base semiconductor monolayers <NUM> defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer <NUM> thereon. The energy band-modifying layers <NUM> are indicated by stippling in <FIG> for clarity of illustration.

The energy band-modifying layer <NUM> illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By "constrained within a crystal lattice of adjacent base semiconductor portions" it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer <NUM> therebetween, as seen in <FIG>. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions 46a-46n through atomic layer deposition techniques so that not all (i.e., less than full or <NUM>% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers <NUM> of semiconductor material are deposited on or over a non-semiconductor monolayer <NUM>, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

Applicant theorizes without wishing to be bound thereto that energy band-modifying layers <NUM> and adjacent base semiconductor portions 46a-46n cause the superlattice <NUM> to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers <NUM> may also cause the superlattice <NUM> to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice <NUM>. These properties may thus advantageously allow the superlattice <NUM> to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

It is also theorized that semiconductor devices including the superlattice <NUM> may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice <NUM> may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.

The superlattice <NUM> also illustratively includes a cap layer <NUM> on an upper layer group 45n. The cap layer <NUM> may comprise a plurality of base semiconductor monolayers <NUM>. The cap layer <NUM> may have between <NUM> to <NUM> monolayers of the base semiconductor, and, more preferably between <NUM> to <NUM> monolayers.

Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

Each energy band-modifying layer <NUM> may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer <NUM> provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or <NUM>% coverage). For example, with particular reference to the atomic diagram of <FIG>, a <NUM>/<NUM> repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.

In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice <NUM> in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

It is theorized without Applicant wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The <NUM>/<NUM> repeating structure shown in <FIG> and <FIG>, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is <NUM> and for the <NUM>/<NUM> SiO superlattice in the X direction it is <NUM> resulting in a ratio of <NUM>. Similarly, the calculation for holes yields values of <NUM> for bulk silicon and <NUM> for the <NUM>/<NUM> Si/O superlattice resulting in a ratio of <NUM>.

While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons and holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.

The lower conductivity effective mass for the <NUM>/<NUM> Si/O embodiment of the superlattice <NUM> may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice <NUM> may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.

Indeed, referring now additionally to <FIG>, another embodiment of a superlattice <NUM>' in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of <NUM>/<NUM>/<NUM>/<NUM> is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice <NUM>'. The energy band-modifying layers <NUM>' may each include a single monolayer. For such a superlattice <NUM>' including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements of <FIG> not specifically mentioned are similar to those discussed above with reference to <FIG> and need no further discussion herein.

In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

In <FIG>, band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction. " However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.

<FIG> shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the <NUM>/<NUM> Si/O superlattice <NUM> shown in <FIG> (represented by dotted lines). The directions refer to the unit cell of the <NUM>/<NUM> Si/O structure and not to the conventional unit cell of Si, although the (<NUM>) direction in the figure does correspond to the (<NUM>) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum. The (<NUM>) and (<NUM>) directions in the figure correspond to the (<NUM>) and (-<NUM>) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the <NUM>/<NUM> Si/O structure.

It can be seen that the conduction band minimum for the <NUM>/<NUM> Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (<NUM>) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the <NUM>/<NUM> Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.

<FIG> shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the <NUM>/<NUM> Si/O superlattice <NUM> (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (<NUM>) direction.

<FIG> shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the <NUM>/<NUM>/<NUM>/<NUM> Si/O structure of the superlattice <NUM>' of <FIG> (dotted lines). Due to the symmetry of the <NUM>/<NUM>/<NUM>/<NUM> Si/O structure, the calculated band structures in the (<NUM>) and (<NUM>) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (<NUM>) stacking direction. Note that in the <NUM>/<NUM>/<NUM>/<NUM> Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.

Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicant to further theorize that the <NUM>/<NUM>/<NUM>/<NUM> superlattice <NUM>' should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.

Having now described the structure and formation of example MST materials, various embodiments of semiconductor devices and method for their manufacture will now be described which advantageously provide for metal-silicon contacts with proximate dopants using the above-described MST materials. By way of background, it is typical in semiconductor devices for electrons to be transferred between a semiconductor (such as silicon) and conducting metal "interconnects" which transfer charge between semiconductor devices. Electrical resistance between the semiconductor and metal increases the energy required and reduces the maximum speed of computations and other functions performed by circuits using the devices. It is thus advantageous to minimize this electrical resistance.

When electrons are transferred between a metal and a semiconductor such as silicon, there is a potential barrier encountered by the electron. This barrier is typically referred to as the "Schottky barrier. " Electrons can either have sufficient kinetic energy to overcome the Schottky barrier directly, or electrons with lower kinetic energy may pass between the metal and semiconductor via quantum mechanical tunneling. Such tunneling is more likely the spatially thinner the Schottky barrier. A typical way to attain a reduced barrier is to increase the electric field. Higher levels of ionized impurities ("dopants") typically yield higher electric fields and thus increase the tunneling probability, increasing the electron flux between the metal and the semiconductor, thus reducing the effective electrical resistance. But in addition to increasing the electric field, high levels of impurities may additionally reduce the Schottky barrier itself, by reducing the effective band gap of the semiconductor immediately adjacent to the metal-semiconductor interface (and via other chemical effects). This effect is evident from density functional theory calculations.

Oxygen insertion (OI) layers (or other non-semiconductor layers), such as provided in an MST film, for example, may contribute to a lower Schottky and/or thinner barrier by trapping dopants. Density functional theory calculations have shown that OI layers provide for the favorable substitution of specific dopant atoms for silicon atoms within one or two atomic layers of the OI layer. By trapping dopants immediately proximate to, for example, separated by one or two atomic layers from, a metal-semiconductor interface, OI layers may thus contribute to a relatively higher concentration of dopants immediately adjacent to the metal-semiconductor interface, increasing the electric field, and additionally reducing the Schottky barrier.

In addition to trapping dopants, OI layers may immobilize them by trapping point defects that would otherwise aid the diffusion of dopants. So, while an OI layer proximate to a metal-semiconductor layer may trap dopants immediately adjacent to that interface, additional OI layers further from but still proximate to the interface may trap point defects that would otherwise aid in the diffusion of dopants away from the interface. Thus, it may be beneficial to have more than one, for example two, three, or four, OI layers proximate to the interface.

Generally speaking, the embodiments described herein utilize one or more oxygen insertion ("OI" or "MST") layers in close proximity to a metal-semiconductor interface in conjunction with a high (for example, in excess of <NUM><NUM>/cm<NUM>, or <NUM>% of crystalline sites in the silicon lattice) of ionized impurities such as boron, phosphorus, arsenic, antimony, indium, or gallium in the near proximity (for example, closer than <NUM>) to the metal-silicon interface. Examples of metals include aluminum, tungsten, nickel, titanium, copper, cobalt, indium, gold, platinum, erbium, ytterbium, and compounds of any of these metals with silicon or germanium.

Since the OI layers may provide for favorable substitution by dopant atoms of silicon atoms one or two atomic layers away, the most favorable separation of an OI layer from a metal-semiconductor interface is one or two atomic layers, allowing for the trapping of a high concentration of dopants up to and immediately adjacent to the metal-semiconductor interface. But benefits may also be provided with other separations, for example three, or four atomic layers. Additionally, there may be a benefit in including additional oxygen insertion layers in addition to this first oxygen insertion layer.

Examples of this approach are represented in the graph <NUM> of <FIG>, in which: Si = Silicon atom; M = Metal atom (e.g. titanium); O = Oxygen atom; and D = Dopant atom (e.g. boron). The oxygen atoms as drawn are part of oxygen insertion layers, where the oxygen is bonded with adjacent silicon atoms. While oxygen atoms are necessarily present in the OI layers, there may also additionally be nitrogen atoms, which are not represented in the figure. The presence of nitrogen may be beneficial for the trapping of dopants or for the thermal stability of the OI layers, for example.

Similarly, the represented dopants are replacing silicon atoms in the crystalline lattice, as opposed to occupying "interstitial" positions or in dopant clusters where they will fail to contribute to free carriers in the semiconductor. However, while substitutional dopants are represented in the figure, a high concentration of dopants trapped near the metal-semiconductor interface may reduce a Schottky barrier with alternate atomic configurations. The positions of dopants in the diagram are a schematic representative for illustrational purposes. An actual distribution of dopant atoms will be in part random, influenced by the specific atomic configuration of oxygen atoms, and the local bonding of atoms. The illustrated configurations represent the distance of atoms from the metal-semiconductor interface, not specific positions of atoms within layers. The illustrated configurations are as follows:.

In addition to these configurations, additional configurations with multiple OI layers are also possible, for example one layer separated from the metal-semiconductor interface by two silicon layers, and an additional layer separated by an additional four atomic layers. These multiple layers may provide for dopant trapping both at the metal-semiconductor interface, and additionally below the metal-semiconductor interface, the former contributing to chemical Schottky barrier lowering and a higher electric field, the latter contributing primarily through higher electric field. The embodiments set forth herein are generally defined by the presence of a layer proximate to the metal-semiconductor interface in conjunction with a high concentration of dopants, but does not exclude additional layers or dopant atoms not proximate to OI layer(s). A specific advantage of additional OI layers is these additional layers may increase the stability of the structure, for example blocking the loss of oxygen from the layer closest to the metal-semiconductor interface, or trapping point defects which otherwise would contribute to a loss of dopant atoms from the region proximate to the metal-semiconductor interface.

Referring now to <FIG>, the above-described superlattice structures may advantageously be used in semiconductor devices to provide reduced source/drain contact resistance by applying the above-described principles. In typical semiconductor processes, the reduction of metal to semiconductor contact area requires lower contact resistivity (e.g., ρc<1E-<NUM> ohm. Contact resistivity is determined by two parameters, which are:.

Furthermore, the metal-semiconductor Schottky barrier height is "pinned" for different metals. Moreover, an interfacial insulator can "de-pin" the Fermi level depending on thickness, bandgap, and permittivity.

In the semiconductor device <NUM> shown in <FIG> (a FET), a dopant diffusion blocking superlattice <NUM> (such as those described above in <FIG>) is used to advantageously increase surface dopant concentration to allow a higher ND during in-situ doped epitaxial processing by preventing diffusion into a channel region <NUM> of the device. More particularly, the device <NUM> illustratively includes a semiconductor layer or substrate <NUM>, and spaced apart source and drain regions <NUM>, <NUM> formed in the semiconductor layer with the channel region <NUM> extending therebetween. The dopant diffusion blocking superlattice <NUM> illustratively extends through the source region <NUM> to divide the source region into a lower source region <NUM> and an upper source region <NUM>, and also extends through the drain region <NUM> to divide the drain region into a lower drain region <NUM> and an upper drain region <NUM>.

The dopant diffusion blocking superlattice <NUM> may also conceptually be considered as a source dopant blocking superlattice within the source region <NUM>, a drain dopant blocking superlattice within the drain region <NUM>, and a body dopant blocking superlattice beneath the channel <NUM>, although in this configuration all three of these are provided by a single blanket deposition of the MST material across the substrate <NUM> as a continuous film. The semiconductor material above the dopant blocking superlattice <NUM> in which the upper source/drain regions <NUM>, <NUM> and channel region <NUM> are defined may be epitaxially grown on the dopant blocking superlattice <NUM> either as a thick superlattice cap layer or bulk semiconductor layer, as discussed further above. In the illustrated example, the upper source/drain regions <NUM>, <NUM> may each be level with an upper surface of this semiconductor layer (i.e., they are implanted within this layer).

As such, the upper source/drain regions <NUM>, <NUM> may advantageously have a same conductivity as the lower source/drain regions <NUM>, <NUM>, yet with a higher dopant concentration. In the illustrated example, the upper source/drain regions <NUM>, <NUM> and the lower source/drain regions <NUM>, <NUM> are N-type for a N-channel device, but these regions may also be P-type for an P-channel device as well (this applies to other configurations described herein as well). Surface dopant may be introduced by ion implantation, for example. Yet, the dopant diffusion is reduced by the MST film material of the diffusion blocking superlattice <NUM> because it traps point defects/interstitials introduced by ion implantation which mediate dopant diffusion.

The semiconductor device <NUM> further illustratively includes a gate <NUM> on the channel region <NUM>. The gate illustratively includes a gate insulating layer <NUM> gate electrode <NUM>. Sidewall spacers <NUM> are also provided in the illustrated example.

Referring now to <FIG>, in accordance with another example implementation a semiconductor device <NUM> (FET) illustratively includes a semiconductor layer or substrate <NUM>, and spaced apart source and drain regions <NUM>, <NUM> with a channel region <NUM> extending therebetween. In the illustrated embodiment, a source diffusion blocking superlattice <NUM> illustratively extends through the source region <NUM> to divide the source region into a lower source region <NUM> and an upper source region <NUM>. Similarly, a drain diffusion blocking superlattice 225d extends through the drain region <NUM> to divide the drain region into a lower drain region <NUM> and an upper drain region <NUM>. Considered alternatively, the upper source and drain regions <NUM>, <NUM> are each raised above an upper surface of the semiconductor layer <NUM>, and there is no superlattice extending between the source and drain regions <NUM>, <NUM> as in the example of <FIG> (i.e., beneath gate <NUM>). The gate <NUM> illustratively includes a gate insulator <NUM> and gate electrode <NUM>, and gate sidewall spacers <NUM> may also be provided.

In this implementation, the surface dopant in the upper source/drain regions <NUM>, <NUM> may be introduced by selectively growing MST films, followed by in-situ doped epi film formation. Here again, the MST material of the source/drain dopant diffusion blocking superlattices <NUM>, 225b advantageously helps prevent dopant diffusion into the channel region <NUM>, and thus allows higher surface dopant concentration as noted above.

In accordance with another example implementation now described with reference to <FIG>, further processing steps may be performed to the semiconductor device <NUM> shown in <FIG> to perform Schottky barrier height modulation by controlling a thickness and composition of an interfacial insulator. With traditional metal contacts, too thick of a source/drain insulator results in high contact resistivity due to high tunneling resistance. However, the superlattice <NUM>' advantageously provides desired non-semiconductor (e.g., oxygen) dose control for Fermi-level de-pinning and tunneling resistance. After formation of the gate <NUM>' on the channel region <NUM>', co-implantation of N, C, or F may further modulate insulator composition for lower permittivity (e.g., C and F used for low-k ILD film to modulate SiO<NUM> composition), as illustrated in <FIG>. The MST film of the superlattice <NUM>' effectively accumulates these elements into the surface region. It should be noted that in some embodiments N and C may be incorporated into silicon surface by gaseous form (e.g., N<NUM> anneal or CO, CH<NUM> anneal) instead of co-implantation.

A thermal treatment and metal deposition may then be performed (<FIG>). The thermal treatment moves upward non-semiconductor atoms (oxygen in the present example) from the non-semiconductor monolayers of the dopant diffusion blocking superlattices <NUM>' which react with the metal to form respective source and drain contact insulating interfaces <NUM>', <NUM>' between the upper source and drain regions and adjacent portions of metal layers <NUM>', <NUM>' formed by the metal deposition. Stated alternatively, as the oxygen atoms disassociate from the superlattice <NUM>' in the source and drain regions and move upward to form the contact insulating interfaces <NUM>', <NUM>' so that there is no longer a defined superlattice layer separating the lower/upper source regions <NUM>', <NUM>' and lower/upper drain regions <NUM>', <NUM>' (see <FIG>).

In accordance with one example implementation, a Co/Co<NUM>Ti<NUM> (<NUM>) metal deposition may be performed at a temperature in a range of about +<NUM>-400C for approximately <NUM>. to form the source and drain contact insulating interfaces <NUM>', <NUM>' and metal layers <NUM>', <NUM>'. Moreover, in some implementations, an additional metal deposition (e.g., Co) may be performed to form upper source/drain metal contact layers <NUM>', <NUM>' in the semiconductor device <NUM>'.

Another example embodiment similar to the semiconductor device <NUM> is now described with reference to <FIG>. In this illustrated example, the source and drain dopant diffusion blocking superlattices <NUM>', 225d' advantageously provide for Schottky barrier height modulation via hetero-epitaxial film integration. More particularly, the lower source and drain regions <NUM>', <NUM>' include a different material than the upper source and drain regions <NUM>', <NUM>'. In this example, the lower source and drain regions <NUM>', <NUM>' are silicon, and the upper source and drain regions <NUM>', <NUM>' are SiGeC, although different materials may be used in different embodiments.

Because the MST material is effective in integrating hetero-epitaxial semiconductor material, incorporation of C(<NUM>-<NUM>%) to Si or SiGe on Si may induce a positive conduction band offset. More particularly, this is a SiGeC/MST/n+ Si structure that is effective for reducing Schottky barrier height.

Referring additionally to <FIG>, another similar semiconductor device <NUM>" advantageously provides for Schottky barrier height modulation via hetero-epitaxial film integration. In the illustrated example, the semiconductor layer/substrate <NUM>" is silicon germanium, and the lower source/drain regions <NUM>", <NUM>" are P+ SiGe. Moreover, the upper source/drain regions <NUM>", <NUM>" are also silicon, and a respective platinum contact layer <NUM>", <NUM>" is formed on each of the upper source/drain regions. The upper source/drain regions <NUM>", <NUM>" may be formed in a relatively thin epitaxial silicon layer (e.g., <NUM>-<NUM>). Here again, the MST material is effective in integrating hetero-epitaxial semiconductor material, and strained Si on SiGe (or Ge) may advantageously induce negative valence band offset. As a result, the illustrated s-Si/MST/p+ SiGe structure may be effective for reducing Schottky barrier height as well.

Turning now additionally to <FIG>, certain of the above-described planar FET configurations may also advantageously be implemented in vertical semiconductor devices as well. An example FINFET <NUM> illustratively includes a semiconductor layer or substrate <NUM> (e.g., silicon), an insulating layer <NUM> on the substrate (e.g., SiO<NUM>), and one or more semiconductor fins <NUM> extending vertically upward from the substrate through the insulating layer.

Spaced apart source and drain regions <NUM>, <NUM> are formed in each semiconductor fin <NUM> with a channel region <NUM> extending therebetween. A source dopant diffusion blocking superlattice <NUM> extends through the source region <NUM> to divide the source region into a lower source region <NUM> and an upper source region <NUM>, and a drain dopant diffusion blocking superlattice 325d extends through the drain region <NUM> to divide the drain region into a lower drain region <NUM> and an upper drain region <NUM>. Similar to the embodiment of <FIG>, the upper source/drain regions <NUM>, <NUM> have a same conductivity and higher dopant concentration (N++) than the lower source/drain regions <NUM>, <NUM> (N+). Moreover, the upper source/drain regions <NUM>, <NUM> extend above an upper surface of the semiconductor fin <NUM>. That is, superlattices <NUM>, 325d may be formed on the top of the semiconductor fin <NUM>, and the upper source/drain regions <NUM>, <NUM> may be epitaxially grown on the respective superlattices. In this regard, the upper source/drain regions <NUM>, <NUM> may implanted with a dopant, or they may be in-situ doped epitaxial layers as described above.

The FINFET <NUM> also illustratively includes a gate <NUM> overlying the channel regions <NUM> of the fins <NUM>. The gate <NUM> illustratively includes a gate insulator <NUM> and a gate electrode <NUM> on the gate insulator.

In accordance with another example implementation, a FINFET <NUM>' may be fabricated using a similar process to that described above with respect to <FIG>, i.e., involving a thermal treatment and metal deposition to define source/drain insulating layers <NUM>', <NUM>' between the upper source/drain regions <NUM>', <NUM>' and metal layers <NUM>', <NUM>' (e.g., CoTix) respectively. Upper metal layers <NUM>', <NUM>' (e.g., Co) may also be formed on the lower metal layers <NUM>', <NUM>' in some embodiments. Here again, the heat treatment causes the non-semiconductor atoms in the source/drain dopant blocking superlattice layers to move upward, leaving no superlattice between the upper source/drain regions <NUM>', <NUM>' and the lower source/drain regions <NUM>', <NUM>' in the final FINFET <NUM>'. Here again, this approach advantageously provides for Schottky barrier height modulation by controlling the thickness and composition of the interfacial insulators <NUM>', <NUM>'.

Referring additionally to <FIG>, a FINFET <NUM>" is provided which is similar to embodiment of <FIG> above, in that the source and drain dopant blocking superlattices <NUM>", 325d" advantageously provide for Schottky barrier height modulation via hetero-epitaxial film integration. More particularly, the lower source and drain regions <NUM>", <NUM>" include a different material than the upper source and drain regions <NUM>", <NUM>". In this example, the lower source and drain <NUM>", <NUM>" regions are silicon, and the upper source and drain regions <NUM>", <NUM>" are SiGeC, although different materials may be used in different embodiments. Also, the lower metal layers <NUM>", <NUM>" are titanium, and the upper metal layers <NUM>", <NUM>" are cobalt in the illustrated example.

In still another example shown in <FIG>, similar to the embodiment of <FIG> the FINFET <NUM>‴ may also provide for Schottky barrier height modulation via hetero-epitaxial film integration. In the illustrated example, the semiconductor fin <NUM>' is silicon germanium, and the lower source/drain regions <NUM>", <NUM>" are P+ SiGe. Moreover, the upper source/drain regions <NUM>", <NUM>" are silicon, and a respective platinum contact layer <NUM>", <NUM>" is formed on each of the upper source/drain regions. Here again, the upper source/drain regions <NUM>", <NUM>" may be formed in a relatively thin epitaxial silicon layer (e.g., <NUM>-<NUM>).

In the above-described examples, a dopant blocking superlattice is shown in both of the source and drain regions of the illustrated devices. However, it should be noted that in some embodiments both of the source and drain regions need not have a dopant blocking superlattice. That is, the dopant blocking superlattice may be in just one of the source or drain regions in some embodiments.

Furthermore, turning now to <FIG>, a dopant blocking superlattice is incorporated in a body contact to provide reduced body contact resistance in addition to, or instead of, in the source/drain regions. A semiconductor device <NUM> (here a planar FET) includes a semiconductor layer or substrate <NUM>, spaced apart source and drain regions <NUM>, <NUM> (which have respective lightly doped source/drain extensions <NUM>, <NUM> in this example) in the semiconductor layer <NUM> with a channel region <NUM> extending therebetween, and a gate <NUM> on the channel region with sidewall spacers <NUM>. As similarly described above, the gate <NUM> illustratively includes a gate insulator <NUM> and a gate electrode <NUM>. The semiconductor device <NUM> further illustratively includes a body contact <NUM> in the semiconductor layer <NUM> and comprising a body contact dopant diffusion blocking superlattice <NUM> extending through the body contact to divide the body contact into a first body contact region <NUM> and a second body contact region <NUM>. As similarly described above, the second body contact region <NUM> has a same conductivity and higher dopant concentration than the first body contact region <NUM>. Here again, the body contact dopant diffusion blocking superlattice <NUM> may be similar to those superlattice structures described above, and the materials used for, and dopant concentrations within, the first and second body contact regions <NUM>, <NUM> may also be similar to those described above to provide desired contact resistance reduction.

In another example device <NUM>' shown in <FIG>, a similar configuration is provided which has a back-side body contact <NUM>' instead of the topside or front-side body contact <NUM> shown in <FIG>. The remaining components are similar to those discussed with reference to <FIG> and accordingly require no further discussion herein. It should be noted that in the back-side implementation the first and second regions <NUM>', <NUM>' are flipped vertically with respect to the first and second regions <NUM>, <NUM> in the device <NUM>, as they are on the opposite side of the device <NUM>'.

Turning now to <FIG>, another example contact structure <NUM> is now described which may be also be used in certain implementations of source/drain, body, or other contacts to provide reduced Schottky barrier height and thereby decreased contact resistance. The contact <NUM> is formed in a semiconductor layer <NUM>. The contact illustratively includes one or more oxygen monolayers <NUM> constrained within a crystal lattice of adjacent semiconductor portions 546a, 546b of the semiconductor layer <NUM>. The oxygen monolayer(s) <NUM> is and spaced apart from a surface of the semiconductor layer <NUM> by between one and four monolayers (a four monolayer spacing is shown in the semiconductor portion 546b in the illustrated example). Furthermore, a metal layer <NUM> (which may include the same metals discussed above) is formed on the surface of the semiconductor layer <NUM> above the oxygen monolayer(s) <NUM>. The contact <NUM> may be formed on a semiconductor layer or substrate <NUM>.

By way of example, a dopant concentration within the portion 546b (i.e., between the oxygen monolayer(s) <NUM> and the metal layer <NUM>) may be 1x10<NUM> atoms/cm<NUM> or greater (although lower concentrations may also be used in different embodiments). Considered alternatively, a dopant concentration equivalent to approximately <NUM>% of the crystalline sites in a silicon lattice may advantageously be occupied by dopant atoms in an example configuration. This is based upon an estimate for the maximum distance range over which the oxygen monolayer can directly trap dopants (e.g., boron) sufficiently close to the metal to directly reduce the Schottky barrier of the contact, as opposed to reducing diffusion, yet while otherwise retaining a conventional doped metal-semiconductor interface with a bulk-line environment for the dopant atoms, and the minimum concentration of dopants where a benefit will be realized.

Claim 1:
A semiconductor device (<NUM>) comprising:
a semiconductor layer (<NUM>);
spaced apart source and drain regions (<NUM>, <NUM>) in the semiconductor layer with a channel region (<NUM>) extending therebetween;
a gate (<NUM>) on the channel region;
a body contact (<NUM>) in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice (<NUM>) within the semiconductor layer (<NUM>) and extending through the body contact to divide the body contact into a first body contact region (<NUM>) and a second body contact region (<NUM>) with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region; and
a metal contact on the second body contact region;
the body contact dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers (45a-45n), each group of layers comprising a plurality of stacked base semiconductor monolayers (<NUM>) defining a base semiconductor portion (46a-46n), and at least one non-semiconductor monolayer (<NUM>) constrained within a crystal lattice of adjacent base semiconductor portions.