Patent Description:
Neural networks are machine learning models that employ one or more layers of models to generate an output, e.g., a classification, for a received input. Some neural networks include one or more hidden layers in addition to an outer layer. The output of each hidden layer is used as input to the next layer in the network, i.e., the next hidden layer or the output layer of the network.

Some neural networks include one or more convolutional neural network layers. Each convolutional neural network layer has an associated set of kernels. Kernels can be represented as a matrix structure of weight inputs. Each convolutional layer uses the kernels to process inputs to the layer. A set of inputs to the layer can also be represented as a matrix structure.

<CIT> is concerned with providing a multi-dimensional data structure and providing an address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern.

This specification describes technologies relating to accessing a N-dimensional tensor using one or more hardware adders for determining memory addresses of the tensor elements.

Other potential features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

In general, when a software algorithm processes a N-dimensional tensor, a nested loop may be used. Each loop can be responsible for traversing a respective dimension of the N-dimensional tensor. A multi-dimensional tensor may be a matrix or a multi-dimensional matrix. For example, a <NUM>-dimesional tensor is a matrix, while a <NUM>-dimensional tensor is a three-dimensional matrix made up of multiple two-dimensional matrices. Each dimension of the N-dimensional tensor may include one or more elements, where each element may store a respective data value. For example, a tensor may be a variable in a program, where the variable may have three dimensions. The first dimension may have a length of three hundred elements, the second dimension may have a length of a thousand elements, and the third dimension may have a length of twenty elements. Of course, other numbers of elements in each dimension are possible.

Traversing the tensor in a nested loop can include a computation of a memory address value of an element to load or store the corresponding data value of the element. A for-loop is an example of a nested loop, where three loops tracked by three loop index variables (e.g., i, j, and k) can be nested to traverse through a three-dimensional tensor. In a neural network, a value of an element may be used in one or more dot product computations associated with the tensor. For example, the value of the element may be multiplied with a corresponding parameter or weight. The elements of the tensor may be traversed in order using nested for-loops to access the element and perform one or more computations using the value of the element. Continuing the three dimensional tensor example, an outer for-loop may be used to traverse the loop tracked by variable i, a middle for-loop loop may be used to traverse the loop tracked by variable j, and an inner for-loop may be used to traverse the loop tracked by variable k. In this example, the first element accessed may be (i=<NUM>, j=<NUM>, k=<NUM>), the second element may be (i=<NUM>; j=<NUM>, k=<NUM>), and so on. As described below, a tensor traversal unit can be used to determine the memory address for each element in order using nested loops so that a processing unit can access the value of the element and perform the one or more computations using the value of the element. The values of weights or parameters can also be accessed similarly using nested for-loops. The tensor traversal unit can also be used to determine the addresses for weights or parameters used in the computations and/or for the outputs of the computations, which may be used as inputs to a hidden layer of the neural network.

In some cases, a processor may need to execute a loop bound condition, such as setting a loop bound of an inner loop with an outer loop index variable. For example, in determining whether to exit the inner-most loop of a nested loop, the program may compare the current value of the loop index variable of the inner-most loop with the current value of the loop index variable of the outer-most loop of the nested loop.

These tasks may require a significant number of instructions such as branch instructions and integer arithmetic instructions. When each loop bound is small and the number of loops is large, the computation may take a significant portion of the overall execution time, and seriously degrade overall performance. A hardware tensor traversal unit for a processor may increase the computation bandwidth of the processor by reducing the number of dimensions that the processor is required to process when traversing a tensor.

<FIG> shows a block diagram of an example computing system <NUM> for traversing a tensor. In general, the computing system <NUM> processes an input <NUM> to generate an output <NUM>. The computing system <NUM> may be configured to perform linear algebra computations. The input <NUM> may be any suitable data that can be processed by the computing system <NUM>. The computing system <NUM> includes a processing unit <NUM>, a storage medium <NUM>, and a tensor traversal unit <NUM>.

In general, when the processing unit <NUM> executes an instruction for accessing a particular element of a tensor, the tensor traversal unit <NUM> determines the address of the particular element of the tensor, such that the processing unit <NUM> may access the storage medium <NUM> to read data <NUM> representing the value of the particular element. For example, a program may include a nested loop and the processing unit <NUM> may execute an instruction to access an element of a two-dimensional array variable within the nested loop according to current index variable values associated with the nested loop. Based on the current index variable values associated with the nested loop, the tensor traversal unit <NUM> may determine an address offset value that represents an offset from a memory address for a first element of the two-dimensional array variable. The processing unit <NUM> may then access, using the address offset value and from the storage medium, the particular element of the two-dimensional array variable.

The processing unit <NUM> is configured to process instructions for execution within the computing system <NUM>, including instructions <NUM> stored in the storage medium <NUM> or other instructions stored in another storage device. The processing unit <NUM> may include one or more processors. The storage medium <NUM> stores information within the computing system <NUM>. In some implementations, the storage medium <NUM> is a volatile memory unit or units. In some other implementations, the storage medium <NUM> is a non-volatile memory unit or units. The storage medium <NUM> may also be another form of computer-readable medium, such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, a flash memory or other similar solid state memory device, or an array of devices, including devices in a storage area network or other configurations. The instructions, when executed by the processing unit <NUM>, cause the processing unit <NUM> to perform one or more tasks.

The tensor traversal unit <NUM> may be implemented as an application-specific integrated circuit. The tensor traversal unit <NUM> may be configured to determine a status associated with one or more tensors. The status may include loop bound values, current loop index variable values, partial address offset values for determining a memory address value, and/or program counter values for handling branch loop bounds.

The tensor traversal unit <NUM> translates tensor indices into memory addresses. For example, the tensor traversal unit <NUM> may translate a set of N-dimensional tensor indices into a one-dimensional address space. The tensor traversal unit can perform such translations by making a tensor element's memory address a combination (e.g., a linear combination) of the element's dimension indices.

The tensor traversal unit <NUM> can efficiently and programmatically generate a sequence of addresses which reference a sequence of tensor elements. The address sequence corresponds to the sequence of tensor elements that would be accessed by a loop nest in a software traversal routine. The sequence of elements accessed during the traversal may or may not be physically contiguous in memory. The example illustrated in <FIG> and described below provide an example of how the sequence of elements are not physically contiguous in memory.

The tensor traversal unit <NUM> includes tensor address value elements <NUM> and a hardware adder unit <NUM>. Each of the tensor address value elements <NUM> may be a storage element, for example a register or any other suitable storage circuitry. In some implementations, the tensor address value elements <NUM> may be physically or logically arranged into different groups, as described in more detail below with reference to <FIG>. In some implementations, a group of the tensor address value elements <NUM> may be physically or logically arranged into a multi-dimensional array. For example, each group of the tensor address value elements <NUM> may be physically or logically arranged into a two-dimensional array.

The hardware adder unit <NUM> can include one or more hardware adders. Each adder may include digital circuitry that is configured to perform addition operations. For example, as described below, the one or more adders may add partial address offset values to determine a total address offset value for an element of a tensor. As hardware adders require fewer circuit components than arithmetic logic units (ALUs) and hardware multipliers, the size of the circuitry of the hardware adder unit <NUM> (and thus the size of the tensor traversal unit <NUM>) can be smaller than a tensor traversal unit that includes ALUs and/or multipliers. In addition, the cost of fabricating a tensor traversal unit with hardware adders may be less than the cost of fabricating a tensor traversal unit with ALUs and/or multipliers. In some implementations, the hardware adder unit <NUM> includes only adders and no other mathematical or logic circuitry.

<FIG> shows an example set of tensor address value elements <NUM> of a tensor traversal unit. The tensor address value elements <NUM> may correspond to the tensor address value elements <NUM> of the tensor traversal unit <NUM>. The tensor traversal unit <NUM> includes a group of initial value elements <NUM>, a group of step value elements <NUM>, a group of end value elements <NUM>, and a group of partial address offset value elements <NUM>.

The initial value elements <NUM> may be physically or logically arranged as a <NUM>-D array having M rows and N columns, where M and N are integers greater than or equal to one. The initial value elements <NUM> may store initial values of partial address offsets used to determine a memory address for a tensor element. In some implementations, each row of the initial value elements <NUM> may represent initial values for a tensor. For example, if a program defines two array variables V1 and V2, the tensor traversal unit may assign rows 202a and 202b to store the initial values for array variables V1 and V2, respectively. In some implementations, each column of the initial value elements <NUM> may represent initial values for nested loop index variable values that are associated with a tensor. For example, if the program defines a nested loop having three loops for accessing the variable V1, where each loop of the nested loop is indexed by nested loop index variables i, j, and k, the tensor traversal unit may assign initial value elements V<NUM>,<NUM>, V<NUM>,<NUM>, and V<NUM>,<NUM> to store the initial value for the nested loop index variable i, j, and k, respectively. The initial value elements <NUM> are described in more detail below with reference to <FIG>.

The step value elements <NUM> may be physically or logically arranged as a <NUM>-D array having the same dimensions as the initial value elements <NUM>, where each element of the step value elements <NUM> has a corresponding element in the initial value elements <NUM>. The step value elements <NUM> may store step values of partial address offsets used to determine a memory address for a tensor element. In some implementations, each row of the step value elements <NUM> may represent step values for a tensor. For example, if a program defines two array variables V1 and V2, the tensor traversal unit may assign rows 204a and 204b to store the step values for array variables V1 and V2, respectively. In some implementations, each column of the step value elements <NUM> may represent step values for nested loop index variable values that are associated with a tensor. For example, if the program defines a nested loop having three loops for accessing the variable V1, where each loop of the nested loop is indexed by nested loop index variables i, j, and k, the tensor traversal unit may assign step value elements X<NUM>,<NUM>, X<NUM>,<NUM>, and X<NUM>,<NUM> to store the step value for the nested loop index variable i, j, and k, respectively. The step value elements <NUM> are described in more detail below with reference to <FIG>.

The end value elements <NUM> may be physically or logically arranged as a <NUM>-D array having the same dimensions as the initial value elements <NUM>, where each element of the end value elements <NUM> has a corresponding element in the initial value elements <NUM>. The end value elements <NUM> may store ends values of partial address offsets used to determine a memory address for a tensor element. In some implementations, each row of the end value elements <NUM> may represent end values for a tensor. For example, if a program defines two array variables V1 and V2, the tensor traversal unit may assign rows 206a and 206b to store the end values for array variables V1 and V2, respectively. In some implementations, each column of the end value elements <NUM> may represent end values for nested loop index variable values that are associated with a tensor. For example, if the program defines a nested loop having three loops for accessing the variable V1, where each loop of the nested loop is indexed by nested loop index variables i, j, and k, the tensor traversal unit may assign end value elements Y<NUM>,<NUM>, Y<NUM>,<NUM>, and Y<NUM>,<NUM> to store the end value for the nested loop index variable i, j, and k, respectively. The end value elements <NUM> are described in more detail below with reference to <FIG>.

The partial address offset value element <NUM> may be physically or logically arranged as a <NUM>-D array having the same dimensions as the initial value elements <NUM>, where each element of the partial address offset value elements <NUM> has a corresponding element in the initial value elements <NUM>. The partial address offset value elements <NUM> may store partial address offset values used to determine a memory address for a tensor element. In some implementations, each row of the partial address offset value elements <NUM> may represent partial address offset values for a tensor. For example, if a program defines two array variables V1 and V2, the tensor traversal unit may assign rows 208a and 208b to store the partial address offset values for array variables V1 and V2, respectively. In some implementations, each column of the partial address offset value elements <NUM> may represent partial address offset values for nested loop index variable values that are associated with a tensor. For example, if the program defines a nested loop having three loops for accessing the variable V1, where each loop of the nested loop is indexed by nested loop index variables i, j, and k, the tensor traversal unit may assign partial address offset value elements Z<NUM>,<NUM>, Z<NUM>,<NUM>, and Z<NUM>,<NUM> to store the partial address offset value for the nested loop index variable i, j, and k, respectively. The partial address offset value elements <NUM> are described in more detail below with reference to <FIG>.

<FIG> show an example of how the tensor address value elements <NUM> may be used by a tensor traversal unit to process a tensor, including determining memory address values for tensor elements of the tensor. Referring to <FIG>, a program <NUM> may be stored in the storage medium <NUM> or another storage medium that can be executed by the processing unit <NUM>. The program <NUM> specifies a character array variable V1 having a first dimension of <NUM>, a second dimension of <NUM>, and a third dimension of <NUM>. The program <NUM> specifies a nested for-loop for traversing the variable V1, where the for-loop traverses the first dimension of V1 in an outer loop tracked by a nested loop index variable i; traverses the second dimension of V1 in a middle loop tracked by a nested loop index variable j; and traverses the third dimension of V1 in an inner loop tracked by a nested loop index variable k. Although the illustrated example of <FIG> described herein includes three dimensions, memory address values for tensors having different numbers of dimensions (e.g., <NUM>, <NUM>, <NUM>, or some other number of dimensions) can be determined in a similar manner. For example, a tensor having eight dimensions may be traversed and the memory addresses for the tensor elements can be determined using an <NUM>-deep loop nest.

In some implementations, the tensor address value elements <NUM> may be initialized at the beginning of a program. For example, a processor may execute an instruction "InitializeElements" that initializes the tensor address value elements <NUM>. The instruction may be a hardware instruction of an instruction set executable by a processor. In some implementations, after initialization, each element of the tensor address value elements <NUM> is set to a predetermined value. In some implementations, the processor may execute a separate instruction for each group of tensor address value elements, e.g., one for the initial value elements <NUM>, one for the step values, elements, and so on. Each separate instruction may set each element of its group to a predetermined value for that element.

In this example, each initial value element <NUM> is set to a value of zero. The initial value for a dimension is a value to which the partial address offset value for the dimension is set for a first iteration of the for-loop that traverses the dimension. Thus, in this example, the partial address offset value for each dimension will be set to a value of zero for the first iteration of the for-loop for the dimension.

The step value elements may store step values of partial address offsets used to determine a memory address for a tensor element. The step value for a dimension is a value that is added to the partial address offset value for the dimension after each iteration of the for-loop that traverses the dimension. In this example, the inner nested loop index variable k has a step value of <NUM>, the middle nested loop index variable j has a step value of <NUM>, and the outer nested loop index variable i has a step value of <NUM>.

In some implementations, the processor, a user, or a compiler that compiles a program for traversing a tensor determines the step value and/or end value for each dimension based on a number of elements in one or more of the dimensions of the tensor. In one example, the step value and/or end value for each dimension depends on the memory layout of the tensor. For a two-dimensional tensor, the memory layout may, for example, follow row-major or column major order. In this way, the memory addresses computed for each tensor element is different from the memory address for each other tensor element. In some implementations, the memory addresses are determined such that the sequence of elements accessed during the traversal are physically contiguous in memory. In this example, the first tensor element may be stored at a first memory location with a first address, the second tensor element may be stored at a second memory location directly next to the first memory location, the third tensor element may be stored at a third memory location directly next to the second memory location, and so on. In some implementations, the memory addresses are determined such that the sequence of elements accessed during the traversal are not physically contiguous in memory. In this example, the second tensor element may not be stored directly next to the first tensor element.

The end value elements may store end values for the dimensions. The end value for a dimension represents a value at which the partial address offset value is reset to the initial value for the dimension. In addition, when the partial address offset value of a first loop equals the end value for the first loop, the step value for a second loop in which the first loop is nested is added to the partial address offset value of the second loop. In this example, the inner nested loop index variable i has an end value of <NUM>, the middle nested loop index variable i has a step value of <NUM>, and the outer nested loop index variable k has an end value of <NUM>. Thus, when the partial address offset value for the inner nested loop index variable i reaches a value of <NUM>, the processor may reset the partial address offset value for the inner nested loop index variable i to zero and add the step value (<NUM>) for the middle nested loop index variable j to the partial address offset value for the middle nested loop index variable j. If this is the first iteration of the loop tracked by the middle nested loop index variable j, the partial address offset value for the middle nested loop index variable j would be <NUM> (<NUM>+<NUM>).

The partial address offset value elements <NUM> store partial address offset values for the dimensions. In this example, the processor set the partial address offset values to zero. The partial address offset values are used to determine a memory address offset for a tensor element. In some implementations, the memory address for a particular tensor element for a particular variable is based on a sum of a pre-specified base address for the tensor elements and the partial address offset values for dimensions of the tensor element, as shown in the equation <NUM>. For variable V1, the memory address for a particular tensor element is equal to the sum of the base address for the tensor elements and the partial address offset values in row 208a (top row). Thus, for the tensor element corresponding to the first element of each dimension of variable V1 (i=<NUM>, j=<NUM>, k=<NUM>), the memory address is equal to the base address plus zero as the partial address offset values are all zero.

The memory address for the tensors elements can be determined using the hardware adder unit <NUM> of <FIG>. For example, the input to an adder for a particular variable (e.g., variable V1) may be the base address and the values of each partial address offset value element in the row for the variable (e.g., row 208a for variable V1). The output is the memory address for the variable.

<FIG> illustrates accessing the element V1[<NUM>][<NUM>][<NUM>] according to the program <NUM>. For example, the processor may execute an instruction "LocateTensor" that locates a memory address that corresponds to the element being accessed. In some implementations, the instruction may include a base memory address. For example, the instruction "Locate Tensor" may include a memory address of the element V1[<NUM>][<NUM>][<NUM>] that is the first element of the variable V1. In some implementations, the instruction may include a row number corresponding to a tensor to be accessed. For example, the instruction "LocateTensor" may include a row number corresponding to the variable V1. Here, the row number is <NUM>.

In some implementations, a computing system that includes the tensor traversal unit may include a finite-state machine (FSM) that queries memory address values from the tensor traversal unit. For example, the FSM may query the memory address values for the processor rather than the processor executing instructions such as the "Locate Tensor" and "IterateTensor" instructions described with respect to <FIG>. The FSM may iteratively traverse the nested loops and iterate the partial address values while traversing the loops as described below with reference to the processor. The processor can then receive the determined memory address values from the hardware counter or from the FSM as they are determined.

In some implementations, in response to receiving the instruction, a hardware adder unit (e.g., the hardware adder unit <NUM> of <FIG>) determines a memory address offset by calculating a sum of the values stored in each of the partial address offset value elements <NUM> in row <NUM> (row 208a) of the partial address value elements <NUM>. Here, the hardware adder unit determines a sum of the values stored in elements Z<NUM>,<NUM>, Z<NUM>,<NUM>, and Z<NUM>,<NUM>. The processor can then access the element V1[<NUM>][<NUM>][<NUM>] by adding the base memory address to the determined memory address offset (i.e., <NUM> in this example) to determine a memory address, and accessing the stored data in the storage medium based on the determined memory address. In another example, the hardware adder may determine the memory address for the element V1[<NUM>][<NUM>][<NUM>] by determining a sum of the base memory address and the values stored in elements Z<NUM>,<NUM>, Z<NUM>,<NUM>, and Z<NUM>,<NUM>. The processor can then access the stored in the storage medium based on the determined memory address.

<FIG> illustrates accessing the element V1[<NUM>][<NUM>][<NUM>] according to the program <NUM>. For example, after the program has completed the first iteration of the inner loop, the processor may execute an instruction "IterateTensor" that updates the partial address offset values as the program enters the second iteration of the inner loop (i.e., i=<NUM>, j=<NUM>, k=<NUM>). In some implementations, the tensor traversal unit updates partial address offset values by incrementing the partial address offset value element <NUM> for the dimension corresponding to the inner loop (the loop tracked by inner nested loop index variable i) by the step value for the dimension corresponding to the inner loop. In this example, the partial address offset value stored in partial address offset value element Z<NUM>,<NUM> is incremented by the step value stored in step value element X<NUM>,<NUM> using the hardware adder unit. The resulting updated partial address offset value stored for the inner loop is the sum of the previous value stored in Z<NUM>,<NUM> and the value stored in X<NUM>,<NUM>, i.e., <NUM>+<NUM> = <NUM>.

In some implementations, the tensor traversal unit compares the updated partial offset address value stored in element Z<NUM>,<NUM> to the end value for the inner loop stored in element Y<NUM>,<NUM>. If the updated partial offset address value stored in Z<NUM>,<NUM> equals the end value for the inner loop stored in element Y<NUM>,<NUM>, the tensor traversal unit may reset the value of the partial offset address value stored in element Z<NUM>,<NUM> to the initial value for the inner loop stored in element V<NUM>,<NUM>. In addition, the tensor traversal unit may increment the partial address offset value for the dimension corresponding to the middle loop stored in element Z<NUM>,<NUM> by the step value for the middle loop stored in X<NUM>,<NUM>, as described in more detail below.

If the updated partial offset address value stored in element Z<NUM>,<NUM> is less than the end value for the inner loop stored in element Y<NUM>,<NUM>, the tensor traversal unit may keep the updated partial address value for the inner loop stored in element Z<NUM>,<NUM>. In this example, the updated partial address offset value for the inner loop (<NUM>) is less than the end value for the inner loop (<NUM>). Thus, the tensor traversal unit keeps the updated partial address offset value stored in the partial address offset element Z<NUM>,<NUM> for the inner loop without incrementing the partial address offset value for the middle loop.

The processor can then access the element V1[<NUM>][<NUM>][<NUM>] by executing the instruction "Locate Tensor" to locate the memory address that corresponds to V1[<NUM>][<NUM>][<NUM>]. In response to receiving the instruction, the hardware adder unit determines a memory address offset by calculating a sum of the values stored in each of the partial address offset value elements <NUM> in row <NUM> (row 208a) of the partial address value elements <NUM>. Here, the hardware adder unit determines a sum of the values stored in elements Z<NUM>,<NUM>, Z<NUM>,<NUM>, and Z<NUM>,<NUM>. The processor can then access the element V1[<NUM>][<NUM>][<NUM>] by adding the base memory address to the determined memory address offset (i.e., <NUM> in this example) to determine a memory address, and accessing the stored data in the storage medium based on the determined memory address. In another example, the hardware adder may determine the memory address for the element V1[<NUM>][<NUM>][<NUM>] by determining a sum of the base memory address and the values stored in elements Z<NUM>,<NUM>, Z<NUM>,<NUM>, and Z<NUM>,<NUM>. The processor can then access the stored in the storage medium based on the determined memory address.

<FIG> illustrates accessing the element V1[<NUM>][<NUM>][<NUM>] according to the program <NUM>. For example, after the program has completed the second iteration of the inner loop, the processor may execute an instruction "Iterate Tensor" that updates the partial address offset values as the program enters the second iteration of the middle loop (i.e., i=<NUM>, j=<NUM>, k=<NUM>). In some implementations, the tensor traversal unit updates partial address offset values by incrementing the partial address offset value element <NUM> for the dimension corresponding to the inner loop (the loop tracked by inner nested loop index variable i) by the step value for the dimension corresponding to the inner loop. In this example, the partial address offset value stored in partial address offset value element Z<NUM>,<NUM> is incremented by the step value stored in step value element X<NUM>,<NUM> using the hardware adder unit. The resulting updated partial address offset value stored for the inner loop is the sum of the previous value stored in Z<NUM>,<NUM> and the value stored in X<NUM>,<NUM>, i.e., <NUM>+<NUM> = <NUM>.

In some implementations, the tensor traversal unit compares the updated partial offset address value stored in element Z<NUM>,<NUM> to the end value for the inner loop stored in element Y<NUM>,<NUM>. If the updated partial offset address value stored in Z<NUM>,<NUM> equals the end value for the inner loop stored in element Y<NUM>,<NUM>, the tensor traversal unit may reset the value of the partial offset address value stored in element Z<NUM>,<NUM> to the initial value for the inner loop stored in element V<NUM>,<NUM>. In addition, the tensor traversal unit may increment the partial address offset value for the dimension corresponding to the middle loop stored in element Z<NUM>,<NUM> by the step value for the middle loop stored in X<NUM>,<NUM>.

If the updated partial offset address value stored in element Z<NUM>,<NUM> is less than the end value for the inner loop stored in element Y<NUM>,<NUM>, the tensor traversal unit may keep the updated partial address value for the inner loop stored in element Z<NUM>,<NUM>. In this example, the updated partial address offset value for the inner loop (<NUM>) equals the end value for the inner loop (<NUM>). Thus, the tensor traversal unit resets the partial offset address value stored in element Z<NUM>,<NUM> to the initial value stored in element V<NUM>,<NUM>. In addition, the tensor traversal unit increments the partial address offset value for the middle loop stored in element Z<NUM>,<NUM> by the step value for the middle loop stored in X<NUM>,<NUM>. In this example, the updated partial address offset value for the middle loop is <NUM> (<NUM>+<NUM>).

In some implementations, the tensor traversal unit compares the updated partial offset address value for the middle loop stored in element Z<NUM>,<NUM> to the end value for the middle loop stored in element Y<NUM>,<NUM> in response to determining the updating the partial offset address value for the middle loop. If the updated partial offset address for the middle loop value stored in Z<NUM>,<NUM> equals the end value for the middle loop stored in element Y<NUM>,<NUM>, the tensor traversal unit may reset the value of the partial offset address value stored in element Z<NUM>,<NUM> to the initial value for the middle loop stored in element V<NUM>,<NUM>. In addition, the tensor traversal unit may increment the partial address offset value for the dimension corresponding to the outer loop stored in element Z<NUM>,<NUM> by the step value for the outer loop stored in X<NUM>,<NUM>, as described below.

If the updated partial offset address value for the middle loop stored in element Z<NUM>,<NUM> is less than the end value for the middle loop stored in element Y<NUM>,<NUM>, the tensor traversal unit may keep the updated partial address value for the middle loop stored in element Z<NUM>,<NUM>. In this example, the updated partial address offset value for the middle loop (<NUM>) is less than the end value for the inner loop (<NUM>). Thus, the tensor traversal unit keeps the updated partial address offset value stored in the partial address offset element Z<NUM>,<NUM> for the middle loop without incrementing the partial address offset value for the outer loop.

<FIG> illustrates accessing the element V1[<NUM>][<NUM>][<NUM>] according to the program <NUM>. For example, after the program has completed the first iteration of the inner loop for the second iteration of the middle loop, the processor may execute an instruction "IterateTensor" that updates the partial address offset values as the program enters the second iteration of the inner loop for the second iteration of the middle loop (i.e., i=<NUM>, j=<NUM>, k=<NUM>). In some implementations, the tensor traversal unit updates partial address offset values by incrementing the partial address offset value element <NUM> for the dimension corresponding to the inner loop (the loop tracked by inner nested loop index variable i) by the step value for the dimension corresponding to the inner loop. In this example, the partial address offset value stored in partial address offset value element Z<NUM>,<NUM> is incremented by the step value stored in step value element X<NUM>,<NUM> using the hardware adder unit. The resulting updated partial address offset value stored for the inner loop is the sum of the previous value stored in Z<NUM>,<NUM> and the value stored in X<NUM>,<NUM>, i.e., <NUM>+<NUM> = <NUM>.

<FIG> illustrates accessing the element V1[<NUM>][<NUM>][<NUM>] according to the program <NUM>. For example, after the program has completed the second iteration of the inner loop for the second iteration of the middle loop, the processor may execute an instruction "IterateTensor" that updates the partial address offset values as the program enters the second iteration of the outer loop (i.e., i=<NUM>, j=<NUM>, k=<NUM>). In some implementations, the tensor traversal unit updates partial address offset values by incrementing the partial address offset value element <NUM> for the dimension corresponding to the inner loop (the loop tracked by inner nested loop index variable i) by the step value for the dimension corresponding to the inner loop. In this example, the partial address offset value stored in partial address offset value element Z<NUM>,<NUM> is incremented by the step value stored in step value element X<NUM>,<NUM> using the hardware adder unit. The resulting updated partial address offset value stored for the inner loop is the sum of the previous value stored in Z<NUM>,<NUM> and the value stored in X<NUM>,<NUM>, i.e., <NUM>+<NUM> = <NUM>.

In some implementations, the tensor traversal unit compares the updated partial offset address value for the middle loop stored in element Z<NUM>,<NUM> to the end value for the middle loop stored in element Y<NUM>,<NUM> in response to determining the updating the partial offset address value for the middle loop. If the updated partial offset address for the middle loop value stored in Z<NUM>,<NUM> equals the end value for the middle loop stored in element Y<NUM>,<NUM>, the tensor traversal unit may reset the value of the partial offset address value stored in element Z<NUM>,<NUM> to the initial value for the middle loop stored in element V<NUM>,<NUM>. In addition, the tensor traversal unit may increment the partial address offset value for the dimension corresponding to the outer loop stored in element Z<NUM>,<NUM> by the step value for the outer loop stored in X<NUM>,<NUM>.

If the updated partial offset address value for the middle loop stored in element Z<NUM>,<NUM> is less than the end value for the middle loop stored in element Y<NUM>,<NUM>, the tensor traversal unit may keep the updated partial address value for the middle loop stored in element Z<NUM>,<NUM>. In this example, the updated partial address offset value for the middle loop (<NUM>) equals the end value for the middle loop (<NUM>). Thus, the tensor traversal unit resets the partial offset address value stored in element Z<NUM>,<NUM> to the initial value stored in element V<NUM>,<NUM>. In addition, the tensor traversal unit increments the partial address offset value for the outer loop stored in element Z<NUM>,<NUM> by the step value for the outer loop stored in X<NUM>,<NUM>. In this example, the updated partial address offset value for the outer loop is <NUM> (<NUM>+<NUM>).

<FIG> illustrates accessing the element V1[<NUM>][<NUM>][<NUM>] according to the program <NUM>. For example, after the program has completed the first iteration of the inner loop for the second iteration of the outer loop, the processor may execute an instruction "IterateTensor" that updates the partial address offset values as the program enters the second iteration of the inner loop for the second iteration of the outer loop (i.e., i=<NUM>, j=<NUM>, k=<NUM>). In some implementations, the tensor traversal unit updates partial address offset values by incrementing the partial address offset value element <NUM> for the dimension corresponding to the inner loop (the loop tracked by inner nested loop index variable i) by the step value for the dimension corresponding to the inner loop. In this example, the partial address offset value stored in partial address offset value element Z<NUM>,<NUM> is incremented by the step value stored in step value element X<NUM>,<NUM> using the hardware adder unit. The resulting updated partial address offset value stored for the inner loop is the sum of the previous value stored in Z<NUM>,<NUM> and the value stored in X<NUM>,<NUM>, i.e., <NUM>+<NUM> = <NUM>.

The tensor traversal unit can continue determining memory addresses for remaining iterations of the nested loops to access the remaining tensor elements in a similar manner. Table <NUM> below shows the memory address offset values for the tensor elements using the step values illustrated in <FIG>.

<FIG> is a flow diagram that illustrates an example process <NUM> for determining an address of a multi-dimensional tensor variable. The process <NUM> may be performed by a system of one or more computers, e.g., the computing system <NUM> of <FIG>. The system includes a tensor traversal unit having tensor address value elements including initial value elements, step value elements, end value elements, and partial address offset elements. The tensor traversal unit also includes a hardware adder unit having one or more hardware adders.

The system obtains an instruction to access a particular element of a N-dimensional tensor (<NUM>). The N-dimensional tensor can include multiple elements arranged across each of the N dimensions, where N is an integer that is equal to or greater than one. For example, the system may include a processing unit (e.g., the processing unit <NUM>) that executes an instruction for accessing a particular element of a tensor.

In some implementations, the instruction may represent an instruction for processing a nested loop that includes a first loop, a second loop, and a third loop. The first loop may be an inner loop nested within the second loop and the second loop may be a middle loop nested within the third loop. The first loop may be iterated using a first index variable. Similarly, the second loop may be iterated using a second index variable and the third loop may be iterated using a third index variable. For example, a program may be stored in a storage medium that can be executed by the processing unit. The program may specify a character array variable V1 (or another type of array) a first dimension of <NUM>, a second dimension of <NUM>, and a third dimension of <NUM>. The program may specify a nested for-loop for traversing the variable V1. The for-loop may traverse the third dimension of V1 in an outer loop tracked by a nested loop index variable i. The for-loop may also traverse the second dimension of V1 in a middle loop tracked by a nested loop index variable j and traverse the first dimension in an inner loop tracked by the nested loop index variable k.

The system determines, using one or more hardware adders and partial address offset elements, an address of the particular element (<NUM>). In some implementations, the address of the particular element may be an address offset from another element of the N-dimensional tensor. For example, the address of the particular element may be an address offset from a base memory address of another element of the N-dimensional tensor. For each tensor index element of the one or more tensor index elements, the system may determine the memory address by adding the current values of the partial address offset elements together with the base memory address using the hardware adder(s). The current values of the partial address offset elements are based on the current iteration of the loops.

In some implementations, prior to determining the address offsets for any of the elements of the tensor, the system may set values stored in the tensor address value elements. For example, a processor may execute an instruction "InitializeElements" that initializes the tensor address value elements.

For each iteration of the inner loop, the system may update the partial address offset value for the inner loop using the step value for the inner loop. Before the first iteration of the inner loop for the first iterations of the middle and outer loop (i.e., i=<NUM>, j=<NUM>, k=<NUM>), the partial address offset value for the inner loop may be set to the initial value for the inner loop.

After each iteration of the inner loop, the system may update the partial address offset value for the inner loop to the sum of the previous partial address offset value for the inner loop and the step value for the inner loop. The system may then compare the updated partial address offset value for the inner loop to the end value for the inner loop. If the updated partial address offset value for the inner loop is less than the end value for the inner loop, the system may maintain the updated partial address offset value for the inner loop in its partial address offset value element without modifying any of the other partial address offset values at least until the next iteration of the inner loop.

If this updated partial address offset value is equal to the end value for the inner loop, the system may reset the partial address offset value to the initial value for the inner loop and increment the partial address offset value for the middle loop using the step value for the inner loop. For example, the system may update the partial address offset value for the middle loop to the sum of the previous partial address offset value for the middle loop and the step value for the middle loop. The system may then compare the updated partial address offset value for the middle loop to the end value for the middle loop. If the updated partial address offset value for the middle loop is less than the end value for the inner loop, the system may maintain the updated partial address offset value for the middle loop in its partial address offset value element without modifying any of the other partial address offset values at least until the next iteration of the middle loop.

If this updated partial address offset value is equal to the end value for the middle loop, the system may reset the partial address offset value to the initial value for the middle loop and increment the partial address offset value for the outer loop using the step value for the outer loop. For example, the system may update the partial address offset value for the outer loop to the sum of the previous partial address offset value for the outer loop and the step value for the outer loop. The system may then compare the updated partial address offset value for the outer loop to the end value for the outer loop.

If the updated partial address offset value for the outer loop is less than the end value for the outer loop, the system may maintain the updated partial address offset value for the outer loop in its partial address offset value element. If this updated partial address offset value is equal to the end value for the outer loop, the system may reset the partial address offset values for each loop to their respective initial value as each element of the tensor has been accessed.

The system outputs data indicating the determined address for accessing the particular element of the N-dimensional tensor (<NUM>). For example, the tensor traversal unit may output the determined address based on a sum of the current partial address offset values and the base memory address. The processing unit of the system may access, using a memory address offset value, a particular element of an N-dimensional array variable in the storage medium.

Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non transitory program carrier for execution by, or to control the operation of, data processing apparatus.

The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or a GPGPU (General purpose graphics processing unit).

Claim 1:
An apparatus for processing an instruction for accessing an N-dimensional tensor, the apparatus comprising:
for each dimension of the N-dimensional tensor, a partial address offset value element (<NUM>) that stores a partial address offset value for the dimension based at least on an initial value for the dimension, a step value for the dimension, a number of iterations of a loop for the dimension, and a limit value for the dimension;
one or more processors (<NUM>) configured to obtain an instruction to access a particular element of the N-dimensional tensor, wherein the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and wherein N is an integer that is equal to or greater than one,
one or more hardware adders (<NUM>);
characterized by
the one or more processors (<NUM>) being further configured to:
determine, for each dimension, the partial address offset value for the dimension after each iteration of a nested loop for the dimension by adding the step value to a previous address offset value for the dimension; and
determine, for each dimension, whether the determined partial address offset value for a dimension equals the limit value for the dimension and, in response to determining that the determined partial address offset value for a first dimension that corresponds to a first nested loop equals the limit value for the first dimension,
resetting the partial address offset value for the first dimension to the initial value for the first dimension, and
updating, for a second dimension that corresponds to a second nested loop in which the first nested loop is nested and using the one or more hardware adders, the partial address offset value for the second dimension to equal a sum of the step value for the second dimension and the partial address offset value for the second dimension, and
determine, using the one or more hardware adders (<NUM>), an address of the particular element by determining a sum of the partial address offset values for each dimension stored in the respective partial address offset value elements (<NUM>), and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.