Patent Description:
The present invention is related to phase-locked loop (PLL), and more particularly, to a fast-locking PLL and an associated fast-locking method thereof.

In order to implement a fast-locking PLL, at least one parameter of the fast-locking PLL can be configured to be variable. In a related art, a charge pump current of a PLL can be dynamically switched during a locking operation of this PLL, thereby accelerate the locking operation without sacrificing noise-related performance of the PLL. For example, at the beginning of the locking operation of the PLL, the charge pump current is controlled to have an initial current that is greater than a final current, where the initial current makes the locking operation faster but the noise-related performance is worse in comparison with having the final current; and when the locking operation is almost completed (e.g. output frequency of the PLL is close to a target frequency), the charge pump current can be controlled to have the final current, in order to guarantee the noise-related performance.

The manner of dynamically switching the charge pump current indeed improves the speed of the locking operation. There are some disadvantages, however. In general, a unit cell of a charge pump current source is designed to have a big size for better noise-related performance. When enhancing the speed of the locking operation, the number of unit cells has to be increased, and thereby greatly increase an overall circuit area and current consumption. Thus, there is a need for a novel mechanism for fast-locking operation and an associated architecture thereof, to implement a fast-locking PLL without introducing any side effect or in a way that is less likely to introduce side effects.

<CIT> describes a loop filter which is a component of a PLL circuit, which includes a switching element for switching a capacitance value which connects and disconnects a second capacitive element to a first capacitive element according to a natural angular frequency switching signal, and a switching element for switching a resistance value which short-circuits and opens between both ends of a resistance element according to a natural angular frequency switching signal in order to keep a damping factor at a constant value.

<CIT> describes a variable capacitance circuit comprising a first capacitance coupled between a first terminal and a reference potential terminal, a second capacitance coupled between a second terminal and the reference potential terminal, and a switchable connection between the first terminal and the second terminal, such that in a first mode of operation the value of the first capacitance is provided at the first terminal and that in a second mode of operation a sum of the values of the first and the second capacitances is provided at the first terminal.

<CIT> describes a switched low pass filter which minimizes transients generated during filter switching events and eliminates active circuit random noise.

<CIT> an integrated circuit radio frequency transmitter which includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a longer settle time but with improved filtering in a steady state mode of operation according to one embodiment of the invention.

<NPL>, describes the theory, design and realization of dynamic offset compensated CMOS amplifiers.

<NPL>, describes an APS circuits architecture by which TDI function is implemented in the analog voltage domain, to overcome the problem of CMOS APS sensors suffering from the SNR reduction caused by the decrease in integration time, especially under the case of low light condition and high relative velocity between objects and sensors.

This in mind, the present invention provides a fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof, as defined by the independent claims <NUM> and <NUM> respectively. Such a fast-locking PLL based on gear-shifting loop filter for dynamic bandwidth control, which can implement a fast-locking operation without greatly increase additional costs.

Embodiments of the present invention can enhance the speed of a locking operation of a PLL without sacrificing the noise-related performance by switching resistance and capacitance(s) of a loop filter within the PLL, which dynamically switches bandwidth of the loop filter during the locking operation. In addition, the embodiments of the present invention will not greatly increase additional costs. Thus, the present invention can improve overall performance without introducing any side effect or in a way that is less likely to introduce side effects.

Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

A phase-locked loop (PLL) may comprise a phase detector (e.g. a phase frequency detector), a charge pump, a loop filter, a voltage control oscillator (VCO) and a divider. In order to implement a fast-locking PLL, a gear-shifting bandwidth (e.g. a dynamic bandwidth) of the PLL can be employed. For example, the gear-shifting bandwidth comprises a first bandwidth and a second bandwidth, which are sequentially adopted during a locking operation of the PLL. For example, the first bandwidth is adopted in a first mode, and the second bandwidth is adopted in a second mode following the first mode, where the first bandwidth benefits locking speed (e.g. arranged for locking frequency error and phase error) in comparison with the second bandwidth, and the second bandwidth can be designed for optimizing noise-related performance such as that related to integrated phase noise (IPN). For better illustration of a fast-locking operation of the PLL, please refer to the following equations, which present an open loop bandwidth (illustrated by "BWPLL(open loop)") K, a damping factor δ, and a close loop bandwidth ωn of the PLL: <MAT> <MAT> and <MAT> It should be noted that ICP represents a charge pump current of the charge pump, KVCO represents a VCO gain of the VCO, RP represents a resistance of a resistor within the loop filter, CP represents a capacitance of a capacitor within the loop filter, and N represents a divisor of the divider. According to the above expressions, a method of changing a bandwidth (e.g. the open loop bandwidth K or the close loop bandwidth ωn) can be implemented by changing ICP, RP, CP, KVCO and N. In general, the damping factor δ may be designed to be unchanged when varying the bandwidth between the first bandwidth and the second bandwidth.

For example, ICP in the first mode can be designed to be <NUM> times that in the second mode, and the first bandwidth can be <MAT> times the second bandwidth if the damping factor δ is unchanged (e.g. RP in the first mode is designed to be <MAT> times that in the second mode). As a current source unit of the charge pump usually requires a large circuit area, the method of changing ICP for the gear-shifting bandwidth may greatly increase additional costs. Thus, the present invention provides another mechanism to implement the gear-shifting bandwidth. For example, RP in the first mode can be designed to be <NUM> times that in the second mode, and the first bandwidth can be <NUM> times the second bandwidth if the damping factor δ is unchanged (e.g. CP in the first mode is designed to be <NUM>/<NUM> times that in the second mode).

<FIG> is a diagram illustrating a fast-locking PLL <NUM> according to an embodiment of the present invention, where the fast-locking PLL <NUM> may be an example of the aforementioned PLL. As shown in <FIG>, the fast-locking PLL <NUM> comprises a gear-shifting loop filter <NUM>, a phase frequency detector with charge pump (which may be referred to as "PFD/CP" for brevity) <NUM>, a voltage control oscillator (VCO) <NUM> and a divider such as a multi-modulus divider (MMD) <NUM>. In this embodiment, the PFD/CP <NUM> generates a voltage signal according to phase or frequency difference between a reference clock signal CKREF from a reference clock source (not shown) and a divided clock signal CKMMD from the MMD <NUM>. This voltage signal is transmitted to the VCO <NUM> via a path coupled to the gear-shifting loop filter. The VCO <NUM> then generates an output clock signal CKVCO according to the received voltage signal, and the MMD <NUM> performs a frequency dividing operation upon the output clock signal CKVCO, e.g. a frequency of the output clock signal CKVCO is divided by a certain value (e.g. an integer of a fractional value greater than one), in order to generate the divided clock signal CKMMD. It should be noted that embodiments of the present invention aim at providing implementations of the gear-shifting loop filter <NUM> (which will be described in detail later), where the other components such as the PFD/CP <NUM>, the VCO <NUM> and the MMD <NUM> may be implemented or replaced by any suitable circuit architecture, and related details regarding to these components are omitted here for brevity. Furthermore, the architecture of the fast-locking PLL <NUM> shown in <FIG> is for illustrative purpose only, and is not meant to be a limitation of the present invention, that is, the gear-shifting loop filter <NUM> can be applied to any architecture of a fast-locking PLL which comprises a loop filter comprising resistors and/or capacitors.

In this embodiment, the gear-shifting loop filter <NUM> is configured to have a dynamic bandwidth (e.g. either a bandwidth BW1 or a bandwidth BW2) in order to perform a gear-shifting operation (e.g. switching the dynamic bandwidth from the bandwidth BW1 to the bandwidth BW2). More specifically, the gear-shifting loop filter <NUM> comprises a capacitor set CS1, a resistor set RS2 and a capacitor set CS2 coupled to the resistor set RS2. Assume that the bandwidth BW1 is designed to be γ times the bandwidth BW2 in the embodiment of <FIG>, where γ is a positive value greater than one. In this embodiment, the resistor set RS2 is configured to have a fixed capacitance (e.g. implemented by a single capacitor C<NUM> having a capacitance "C<NUM>", which is expressed by italics of the symbol "C<NUM>"), the resistor set RS2 is configured to have a dynamic resistance (e.g. either a resistance "γ × R<NUM>" or a resistance "R<NUM>", which is expressed by italics of the symbol "R<NUM>"), and the capacitor set CS2 is configured to have a dynamic capacitance (e.g. either a capacitance "α × C<NUM>" or a capacitance "C<NUM>", which is expressed by italics of the symbol "C<NUM>"), where α is preferably designed as <NUM> / γ<NUM>,but the present invention is not limited thereto. The dynamic resistance of the resistor set RS2 and the dynamic capacitance of the capacitor set CS2 are examples of the resistance RP and the capacitance CP mentioned above, respectively. For example, the dynamic resistance of the resistor set RS2 is switched from "γ × R<NUM>" to "R<NUM>" and the dynamic capacitance of the capacitor set CS2 is switched from "α × C<NUM>" to "C<NUM>", to make the dynamic bandwidth be switched from the bandwidth BW1 to the bandwidth BW2.

In detail, the resistor set RS2 is coupled between a first common node such as a node N1 and a second common node such as a node N2 of the gear-shifting loop filter <NUM>. As shown in <FIG>, the resistor set RS2 comprises a resistor (γ-<NUM>)R<NUM> (which has a resistance "(γ - <NUM>) × R<NUM>" and a resistor R<NUM> (which has the resistance "R<NUM>"), where the resistors (γ-<NUM>)R<NUM> and R<NUM> are coupled in series, and a switch controlled by a gear-shifting control signal Ø2 is coupled across the resistors (γ-<NUM>)R<NUM>, e.g. the dynamic resistance of the resistor set RS2 is switched from "γ × R<NUM>" to "R<NUM>" by turning on this switch, but the present invention is not limited thereto. In some embodiments, the resistor set RS2 having the dynamic resistance may be implemented by different way (e.g. a variable resistor, or multiple resistors with at least one switch for controlling connection of the multiple resistors). In addition, the capacitor set CS2 comprises a capacitor αC<NUM> (which has the capacitance "α × C<NUM>") and a capacitor (<NUM>-α)C<NUM> (which has a capacitance "(<NUM> - α) × C<NUM>"), where the capacitor αC<NUM> is coupled to the resistor set RS2 via the node N2, and the dynamic capacitance of the capacitor set CS2 is switched from "α × C<NUM>" to "C<NUM>" by coupling the capacitor (<NUM>-α)C<NUM> to the node N2.

In some embodiment, the capacitor (<NUM>-α)C<NUM> may be coupled to the node N2 without any processing in advance when performing the gear-shifting operation. This may cause some disadvantage, however. For example, when a locking operation of the fast-locking PLL <NUM> is almost completed, a voltage level on the node N2 is expected to be around a target level, where a voltage level on the capacitor (<NUM>-α)C<NUM> may be different from that on the node N2, and therefore the voltage level on the node N2 may be pulled away from this target level when coupling the capacitor (<NUM>-α)C<NUM> to the node N2. Under this condition, the locking operation will need to spend extra time for recovering the voltage level on the node N2 back to this target level via the bandwidth BW2. As the bandwidth BW2 is designed for optimizing the noise-related performance, and may be relatively disadvantageous on the speed of the locking operation in comparison with the bandwidth BW <NUM>, this extra time for recovering the voltage level on the node N2 may be quite long and is therefore unwanted.

In the embodiment shown in <FIG>, a voltage buffer <NUM> within the gear-shifting loop filter <NUM> is coupled between the node N2 and the capacitor (<NUM>-α)C<NUM>, where <FIG> is a diagram illustrating some details of the voltage buffer <NUM> shown in <FIG> according to an embodiment of the present invention. An input terminal Vin and an output terminal Vout of the voltage buffer are coupled to the node N2 and the capacitor (<NUM>-α)C<NUM> shown in <FIG>, respectively, and with aid of the voltage buffer <NUM>, a voltage level on the capacitorαC<NUM> (or on the node N2) can be copied to the capacitor (<NUM>-α)C<NUM> before coupling the capacitor (<NUM>-α)C<NUM> to the node N2. As shown in <FIG>, the voltage buffer <NUM> comprises a unit gain buffer (UGB) 110U, a first switch controlled by a gear-shifting control signal Ø1, and a second switch controlled by the gear-shifting control signal Ø2. As shown in <FIG>, the UGB 110U and the first switch coupled in series represents a first signal path between an input terminal Vin and an output terminal Vout of the voltage buffer <NUM>, and the second switch represents a second signal path between the input terminal Vin and the output terminal Vout of the voltage buffer <NUM>.

For better comprehension, please refer to <FIG> in conjunction with <FIG>, where the input terminal Vin is coupled to the node N2, and the output terminal Vout is coupled to the capacitor (<NUM>-α)C<NUM>. For example, at the beginning of the locking operation, the fast-locking PLL <NUM> operates under a first bandwidth mode (which relatively benefits the locking speed), where the first switch is turned on and the second switch is turned off, to enable the first signal path between the input terminal Vin and the output terminal Vout, so the voltage level on the capacitor αC<NUM> (or on the node N2) can be copied to the capacitor (<NUM>-α)C<NUM> by the UGB 110U at certain time point(s) before coupling the capacitor (<NUM>-α)C<NUM> to the node N2; and after the locking operation is almost completed (e.g. frequency error or phase error detected by the PFD/CP <NUM> is less than a predetermined value, or a time period starting from the beginning of the locking operation reaches a predetermined time period), the fast-locking PLL <NUM> enters a second bandwidth mode (which relatively benefits the noise-related performance) from the first bandwidth mode, where the first switch is turned off and the second switch is turned on, to enable the second signal path between the input terminal Vin and the output terminal Vout, so the capacitor (<NUM>-α)C<NUM> can be coupled to the node N2, to switch the dynamic bandwidth from the bandwidth BW1 to the bandwidth BW2. In some embodiments, the UGB 110U shown in <FIG> is disabled or turned off after the fast locking PLL <NUM> enters the second bandwidth mode from the first bandwidth mode, but the present invention is not limited thereto. As the voltage level on the capacitor (<NUM>-α)C<NUM> is similar or identical to that on the capacitor αC<NUM>, any possible problem that may occur in an embodiment without using the voltage buffer <NUM> can be solved, and overall performance (e.g. the speed of the locking operation) can be optimized.

As the capacitance of the capacitor set CS1 is fixed while performing the gear-shifting operation, phase margin of the fast-locking PLL may change. The following equations illustrate phase margin øP1 of the fast-locking PLL <NUM> in the first bandwidth mode and phase margin øP2 of the fast-locking PLL <NUM> in the second bandwidth mode: <MAT> and <MAT> Although the phase margin of the fast-locking PLL <NUM> is not fixed during the gear-shifting operation, it is allowable as long as the phase margin falls in an acceptable range which does not greatly degrade the overall performance.

In other embodiment, the phase margin can be kept unchanged with aid of switching the capacitor set CS1 shown in <FIG>, to optimize the overall performance of a fast-locking PLL. For better illustration, please refer to the following equations, which present a bandwidth ωC (e.g. the bandwidth BW2 mentioned above), a zero frequency wZ, a pole frequency ωP, and phase margin ϕ(ω) with respect to a frequency variable ω of a fast-locking PLL (e.g. the fast-locking PLL <NUM> shown in <FIG>) operating under the second bandwidth mode: <MAT> <MAT> <MAT> and <MAT> For the purpose of optimizing the overall performance of this fast-locking PLL, the phase margin ϕ(ω) of this fast-locking PLL operating under the first bandwidth mode is preferably the same as that operating under the second bandwidth mode. In order to keep the phase margin ϕ(ω) (i.e. making ϕ(ωC) = ϕ(ωC1), where ωC1 represents the bandwidth of this fast-locking PLL such as the bandwidth BW1 mentioned above), it is required to make ωC / ωZ = ωC1 / ωZ and ωC / ωP = ωC1 / ωP. For example, in the first bandwidth mode, when the resistance "R<NUM>" is doubled to make the bandwidth ωC doubled (e.g. ωC1 = <NUM> × ωC), the capacitance "C<NUM>" needs to be reduced to <NUM>/<NUM>, and the capacitance "C<NUM>" needs to be reduced to <NUM>/<NUM>, to make ωC / ωZ = ωC1 / ωZ and ωC / ωP = ωC1 / ωP.

<FIG> is a diagram illustrating a fast-locking PLL <NUM> according to an embodiment of the present invention, where the fast-locking PLL <NUM> is obtained by modifying the architecture of the fast-locking PLL <NUM> shown in <FIG>, and more particularly, by modifying implementation of the capacitor set CS1. In the embodiment of <FIG>, the capacitor set CS1 is configured to have a dynamic capacitance (e.g. either a capacitance "β × C<NUM>" or a capacitance "C<NUM>"), where α = β = <NUM>/γ<NUM>. When the dynamic bandwidth is switched from the bandwidth BW1 to the bandwidth BW2, the dynamic capacitance of the capacitor set CS1 can be switched from "β × C<NUM>" to "C<NUM>", to make phase margin of the fast-locking PLL <NUM> unchanged during the gear-shifting operation. As shown in <FIG>, the capacitor set CS1 may comprise a capacitor βC<NUM> (which has the capacitance "β × C<NUM>") and a capacitor (<NUM>-β)C<NUM> (which has a capacitance "(<NUM> - β) × C<NUM>"), where the capacitor βC<NUM> is coupled to the node N1. For example, the dynamic capacitance of the capacitor set CS1 can be switched from "β × C<NUM>" to "C<NUM>" by coupling the capacitor (<NUM>-β)C<NUM> to the node N1, to make the phase margin of the fast-locking PLL <NUM> unchanged.

In some embodiment, the capacitor (<NUM>-β)C<NUM> is coupled to the node N1 without any processing in advance when performing the gear-shifting operation. Due to the similar reason mentioned above, this may cause some disadvantage. For example, when a locking operation of the fast-locking PLL <NUM> is almost completed, a voltage level on the node N1 is expected to be around a target level, where a voltage level on the capacitor (<NUM>-β)C<NUM> may be different from that on the node N1, and therefore the voltage level on the node N1 may be pulled away from this target level when coupling the capacitor (<NUM>-β)C<NUM> to the node N1. Thus, the locking operation will need to spend extra time for recovering the voltage level on the node N1 back to this target level via the bandwidth BW2. More particularly, as the bandwidth BW2 is designed for optimizing the noise-related performance, and may be relatively disadvantageous on the speed of the locking operation in comparison with the bandwidth BW1, this extra time for recovering the voltage level on the node N2 is especially unwanted. This in mind, a voltage buffer <NUM> within the gear-shifting loop filter <NUM> may be coupled between the node N1 and the capacitor (<NUM>-β)C<NUM> in the embodiment of <FIG>. With aid of the voltage buffer <NUM>, the voltage level on the capacitor βC<NUM> can be copied to the capacitor (<NUM>-β)C<NUM> before coupling the capacitor (<NUM>-β)C<NUM> to the node N1. The implementation of the voltage buffer <NUM> may be similar or identical to the voltage buffer <NUM>, where implementation details of the voltage buffer <NUM> are not repeated here for brevity, but the present invention is not limited thereto. As long as the voltage buffer <NUM> is capable of copying the voltage level on the capacitor βC<NUM> to the capacitor (<NUM>-β)C<NUM> before coupling the capacitor (<NUM>-β)C<NUM> to the node N1, any other implementation also belongs to the scope of the present invention.

To further improve overall performance, hardware of the gear-shifting loop filter can be further modified. In practice, the voltage level on the node N1 and the voltage level on the node N2 may be substantially similar or identical to each other when the locking operation is completed or almost completed. Thus, the voltage buffer <NUM> and the voltage buffer <NUM> can share the same hardware to reduce additional costs. For better comprehension, please refer to <FIG>, which is a diagram illustrating a fast-locking PLL <NUM> according to an embodiment of the present invention, where the fast-locking PLL <NUM> may be obtained by modifying the architecture of the fast-locking PLL <NUM> shown in <FIG>, and more particularly, by merely utilizing a single voltage buffer such as a voltage buffer <NUM>, to achieve the same function or effect as that of the voltage buffers <NUM> and <NUM>. For brevity, the dashed boxes labeled CS1, CS2 and RS2 are omitted in <FIG>. In this embodiment, with aid of the voltage buffer <NUM>, the voltage level on the capacitor αC<NUM> (or the node N2) can be copied to both of the capacitors (<NUM>-α)C<NUM> and (<NUM>-β)C<NUM> before respectively coupling the capacitors (<NUM>-α)C<NUM> and (<NUM>-β)C<NUM> to the nodes N2 and N1.

<FIG> is a diagram illustrating some details of the voltage buffer <NUM> shown in <FIG> according to an embodiment of the present invention. The voltage buffer <NUM> may be obtained by modifying the voltage buffer <NUM> shown in <FIG>. As shown in <FIG>, in addition to the UGB 110U, the first switch (which is labeled "SW51" in <FIG> for better comprehension) controlled by the gear-shifting control signal Ø1, and the second switch (which is labeled "SW52" in <FIG> for better comprehension) controlled by the gear-shifting control signal Ø2, the voltage buffer <NUM> may further comprise a third switch (which is labeled "SW53" in <FIG> for better comprehension) controlled by the gear-shifting control signal Ø1 and a fourth switch (which is labeled "SW54" in <FIG> for better comprehension) controlled by the gear-shifting control signal Ø2. In detail, the UGB 110U and the first switch coupled in series may represent a first signal path between an input terminal Vin_C2 and an output terminal Vout_C2 of the voltage buffer <NUM>, the second switch may represent a second signal path between the input terminal Vin_C2 and the output terminal Vout_C2 of the voltage buffer <NUM>, the UGB 110U and the third switch coupled in series may represent a third signal path between the input terminal Vin_C2 and an output terminal Vout_C1 of the voltage buffer <NUM>, and the fourth switch may represent a fourth signal path between the input terminal Vin_C1 and the output terminal Vout_C1 of the voltage buffer <NUM>.

For better comprehension, please refer to <FIG> in conjunction with <FIG>. In the embodiment of <FIG>, the input terminal Vin_C2 is coupled to the node N2, the input terminal Vin_C1 is coupled to the node N1, the output terminal Vout_C2 is coupled to the capacitor (<NUM>-α)C<NUM>, and the output terminal Vout_C1 is coupled to the capacitor (<NUM>-β)C<NUM>. For example, at the beginning of the locking operation, the fast-locking PLL <NUM> may operate under the first bandwidth mode (which relatively benefits the locking speed), where the second switch and the fourth switch are turned off, the first switch is turned on to enable the first signal path between the input terminal Vin_C2 and the output terminal Vout_C2, and the third switch is turned on to enable the third signal path between the input terminal Vin_C2 and the output terminal Vout_C1, so the voltage level on the capacitor αC<NUM> (or on the node N2) can be copied to both of the capacitors (<NUM>-α)C<NUM> and (<NUM>-β)C<NUM> by the UGB 110U at certain time point(s) before respectively coupling the capacitors (<NUM>-α)C<NUM> and (<NUM>-β)C<NUM> to the nodes N2 and N1; and after the locking operation is almost completed (e.g. frequency error or phase error detected by the PFD/CP <NUM> is less than a predetermined value, or a time period starting from the beginning of the locking operation reaches a predetermined time period), the fast-locking PLL <NUM> may enter the second bandwidth mode (which relatively benefits the noise-related performance) from the first bandwidth mode, where the first switch and the third switch are turned off, the second switch is turned on to enable the second signal path between the input terminal Vin_C2 and the output terminal Vout_C2, and the fourth switch is turned on to enable the fourth signal path between the input terminal Vin_C1 and the output terminal Vout_C1, so the capacitors (<NUM>-α)C<NUM> and (<NUM>-β)C<NUM> can be coupled to the nodes N2 and N1, respectively, to switch the dynamic bandwidth from the bandwidth BW1 to the bandwidth BW2. In some embodiments, the UGB 110U shown in <FIG> may be disabled or turned off after the fast locking PLL <NUM> enters the second bandwidth mode from the first bandwidth mode, but the present invention is not limited thereto.

As long as the capacitors (<NUM>-α)C<NUM> and (<NUM>-β)C<NUM> can obtain the voltage levels of the nodes N2 and/or N1 with aid of the voltage buffer <NUM>, connection of the voltage buffer <NUM> in the gear-shifting loop filter <NUM> may vary. For example, the input terminal Vin_C2, the input terminal Vin_C1, the output terminal Vout_C2 and the output terminal Vout_C1 of the voltage buffer <NUM> shown in <FIG> may be coupled to the node N2, the node N1, the capacitor (<NUM>-α)C<NUM> and the capacitor (<NUM>-β)C<NUM>, respectively, as shown in <FIG>, but the present invention is not limited thereto. In another example, the input terminal Vin_C2, the input terminal Vin_C1, the output terminal Vout_C2 and the output terminal Vout_C1 of the voltage buffer <NUM> shown in <FIG> may be coupled to the node N1, the node N2, the capacitor (<NUM>-β)C<NUM> and the capacitor (<NUM>-α)C<NUM>, respectively, since the voltage level on the node N1 may be substantially similar or identical to the voltage level on the node N2 when the locking operation is completed or almost completed (which corresponds to the time point of performing the gear-shifting operation), but the present invention is not limited thereto.

<FIG> is a diagram illustrating an UGB <NUM> according to an embodiment of the present invention, where the UGB <NUM> is implemented by an operational amplifier with negative feedback configuration, and may be an example of the UGB 110U, but the present invention is not limited thereto. In practice, the operational amplifier may has some non-ideal effect (e.g. non-linearity) such as a finite gain (e.g. finite voltage gain) and mismatch; for example, input terminals VP and VN or input components (e.g. input stage transistors) of the operational amplifier may not be completely identical to each other due to process variation. In view of the above, the operational amplifier may have an offset voltage VOS (may correspond to a voltage difference between an input voltage VIN,UGB and an output voltage VOUT,UGB of the UGB 110U, e.g. VOUT,UGB = VIN,UGB + VOS) caused by the finite gain and/or input mismatch of the operational amplifier, and at the moment of the gear-shifting operation (the moment at which the gear-shifting control signal Ø1 turns to low and the gear-shifting control signal Ø2 turns to high, illustrated by a dashed line labeled "Gear-shifting BW"), the offset voltage VOS may pull the voltage level on any of the nodes N1 and N2 (e.g. VIN,UGB) away from a target level which is obtained before the gear-shifting operation as shown in <FIG>, so the locking operation needs to spend extra time to pull back the voltage level to this target level (e.g. spend longer time to lock). In order to minimize the impact of the offset voltage VOS when implementation of the UGB 110U shown in <FIG> is applied, specification requirement of the operational amplifier may be extremely high, e.g. a high direct-current (DC) gain, large sizes of input components (e.g. large dimensions of channel width and/or channel length of input transistors may be required), in order to reduce the offset voltage VOS, and this may greatly increase overall costs. More particularly, to guarantee that a transconductance of the operational amplifier is large enough, the ratio of the channel width and the channel length needs to be large enough, which means both the dimensions of the channel width and the channel length need to be increased in order to minimize the offset voltage VOS without sacrificing the transconductance.

<FIG> is a diagram illustrating an auto-zero UGB <NUM> according to an embodiment of the present invention, where the auto-zero UGB <NUM> may be an example of the UGB 110U, but the present invention is not limited thereto. As shown in <FIG>, the auto-zero UGB <NUM> may comprise an amplifier circuit 80A (e.g. an operational amplifier) and a storage capacitor 80C coupled to the amplifier circuit 80A, where the amplifier circuit 80A may have an offset voltage (e.g. VOS) caused by a finite gain or input mismatch of the amplifier circuit 80A, and the storage capacitor 80C may be configured to store the offset voltage VOS. For example, the auto-zero UGB <NUM> may operate under a calibration mode and a buffer mode, alternately, where in the calibration mode of the auto-zero UGB <NUM>, the offset voltage VOS can be stored on the storage capacitor 80C; and in the buffer mode of the auto-zero UGB <NUM>, an input voltage level on an input terminal (e.g. the input voltage VIN,UGB) of the auto-zero UGB is copied to an output terminal of the auto-zero UGB to be the output voltage VOUT,UGB. More specifically, the auto-zero UGB <NUM> may comprise a first control switch (which is labeled "SW81" in <FIG> for better comprehension) and a second control switch (which is labeled "SW82" in <FIG> for better comprehension) controlled by a mode control signal Ø3, and further comprise a third control switch (which is labeled "SW83" in <FIG> for better comprehension) and a fourth control switch (which is labeled "SW84" in <FIG> for better comprehension) controlled by a mode control signal Ø4. In detail, the first control switch is coupled between a first input terminal (which is labeled "+" in <FIG>) of the amplifier circuit 80A and a first end of the storage capacitor 80C, the second control switch is coupled between an output terminal of the amplifier circuit 80A (which is coupled to the output terminal of the auto-zero UGB <NUM>) and a second input terminal (which is labeled "-" in <FIG>), the third control switch is coupled between the input terminal of the auto-zero UGB and the first input terminal of the amplifier circuit 80A, and the fourth control switch is coupled between the first end of the storage capacitor 80C and the output terminal of the amplifier circuit 80A, where a second end of the storage capacitor 80C is coupled to the second input terminal of the amplifier circuit 80A.

<FIG> illustrates waveforms of the input voltage VIN,UGB (or the voltage level on any of the nodes N1 and N2) and the output voltage VOUT,UGB in conjunction with timing of the gear-shifting control signals {Ø1, Ø2} and the mode control signals {Ø3, Ø4} according to an embodiment of the present invention. For better comprehension, please refer to <FIG> in conjunction with <FIG>. When the mode control signal Ø3 is high (e.g. having a logic value "<NUM>") and the mode control signal Ø4 is low (e.g. having a logic value "<NUM>"), the first control switch and the second control switch are turned on, and the third control switch and the fourth control switch are turned off, where the auto-zero UGB <NUM> may operate under the calibration mode (labeled "CAL"). In the calibration mode, the storage capacitor 80C is coupled between the first input terminal and the second input terminal of the amplifier circuit 80A, and an output terminal of the amplifier circuit is coupled to the second input terminal of the amplifier circuit, to store the offset voltage VOS on the storage capacitor 80C. When the mode control signal Ø4 is high and the mode control signal Ø3 is low, the third control switch and the fourth control switch are turned on, and the first control switch and the second control switch are turned off, where the auto-zero UGB <NUM> may operate under the buffer mode (labeled "BUF"). In the buffer mode, the input terminal of the auto-zero UGB <NUM> is coupled to the first input terminal of the amplifier circuit 80A, and the storage capacitor 80C is coupled between the second input terminal of the amplifier circuit 80A and the output terminal of the auto-zero UGB <NUM>, to copy the input voltage level on the input terminal of the auto-zero UGB <NUM> to the output terminal of the auto-zero UGB (e.g. VIN,UGB = VOUT,UGB). It should be note that a time point of the dynamic bandwidth being switched from the bandwidth BW1 to the bandwidth BW2 (e.g. the time point of performing the gear-shifting operation, which is labeled "Gear-shifting BW" in <FIG>) is in a period at which the auto-zero UGB operates in the buffer mode. In comparison with the embodiment shown in <FIG>, as the offset voltage VOS can be canceled or reduced on the output terminal of the auto-zero UGB <NUM>, the speed of the locking operation can be improved.

It should be noted that the connection shown in <FIG> is for illustrative purpose only, and is not meant to be a limitation of the present invention. As long as the auto-zero UGB <NUM> can cancel the impact of the offset voltage VOS to make VIN,UGB = VOUT,UGB, detailed circuit implementation of the auto-zero UGB <NUM> may vary.

<FIG> is a working flow illustrating a fast-locking method of a fast-locking PLL (e.g. any of the fast-locking PLLs <NUM>, <NUM> and <NUM>) according to an embodiment of the present invention. It should be noted that the working flow shown in <FIG> is for illustrative purposes only, and is not meant to be a limitation of the present invention. One or more steps may be added, deleted or modified in the working flow shown in <FIG>. In addition, if a same result may be obtained, these steps do not have to be executed in the exact order shown in <FIG>.

In Step <NUM>, the fast-locking PLL may utilize a resistor set of a gear-shifting loop filter within the fast-locking PLL to control a dynamic resistance and utilize a capacitor set of the gear-shifting loop filter to control a dynamic capacitance, to make the gear-shifting loop filter have a dynamic bandwidth.

In Step <NUM>, the fast-locking PLL may switch the dynamic resistance from a first resistance to a second resistance, and switch the dynamic capacitance from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.

Briefly summarized, the fast-locking PLL and the associated fast-locking method provided by the embodiments of the present invention can switch resistor(s) and capacitor(s) within a loop filter within the fast-locking PLL, to utilized different bandwidths for different periods of a locking operation, thereby optimizing the overall performance. As at least one voltage buffer may be required for the proposed gear-shifting operation, and any offset voltage of an amplifier circuit within the voltage buffer may impact the overall performance of the fast-lock PLL, an auto-zero UGB is provided in order to guarantee an input voltage and an output voltage of the voltage buffer is identical or almost identical without being hindered by any offset. In comparison with the related art, the embodiments of the present invention will not greatly increase additional costs. Thus, the present invention can improve the overall performance without introducing any side effect or in a way that is less likely to introduce side effects.

Claim 1:
A fast-locking phase-locked loop, PLL, (<NUM>, <NUM>, <NUM>) comprising:
a gear-shifting loop filter (<NUM>), configured to have a dynamic bandwidth, wherein the gear-shifting loop filter (<NUM>) comprising:
a resistor set (RS2 ), configured to have a dynamic resistance;
a capacitor set (CS1, CS2), coupled to the resistor set (RS2), configured to have a dynamic capacitance;
wherein the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth,
characterized in that the gear-shifting loop filter (<NUM>) further comprises:
another capacitor set (CS1, CS2), coupled to the resistor set (RS2), configured to have another dynamic capacitance;
wherein when the dynamic bandwidth is switched from the first bandwidth, set at the beginning of the locking operation, to the second bandwidth, bandwidth when locking operation is almost completed, said another dynamic capacitance is switched from another first capacitance to another second capacitance, to keep the phase margin of the fast-locking PLL (<NUM>, <NUM>, <NUM>) unchanged.