Patent Description:
<NPL>, (<NUM>-<NUM>-<NUM>) gives test results related to alternative Luma filter sets and alternative Chroma filters signaling at tile group level, so that more than one luma filter set and more than one chroma filter can be signaled once per tile group, (i.e., they could be put in the same APS). The encoder selection of luma filters and of one chroma filter is signaled at CTU level.

<NPL>proposes to introduce a group parameter set (GPS) that groups an SPS, a PPS and zero or more APSs such that a slice can refer to an SPS, a PPS and zero or more APSs through referencing a GPS. The group parameter set RBSP syntax includes one or more syntax elements that respectively identify the i-th APS reference by the GPS.

In general, this disclosure describes techniques for coding an adaptation parameter sets (APSs) for video data in accordance with one or more memory constraints. In particular, the techniques of this disclosure may reduce the amount of memory needed at a video decoder to store adaptive loop filter (ALF) parameters and/or luma mapping with chroma scaling (LMCS) parameters that are transmitted in APSs without losing flexibility in adjusting ALF and LMCS parameters for particular video content.

In one example of the disclosure, multiple APSs, which each contain a set of ALF or LMCS parameters, may be signaled for a picture. The indices of each of the APSs available to be used for the picture are also signaled at the picture level. Instead of further signaling APS indices indicating the APSs that may be used at each sub-picture (e.g., slice, tile group, tile, brick, etc.) of the picture at a sub-picture level, a video encoder may signal a single syntax element that indicates that all APSs signaled for the picture at the picture level are available for use at each sub-picture without further sub-picture level signaling. As such, signaling overhead is reduced and coding efficiency may be increased.

In general, this disclosure describes techniques for coding an adaptation parameter sets (APSs) for video data in accordance with one or more memory constraints. In one example of the disclosure, multiple APSs, which each contain a set of adaptive loop filter (ALF) and/or luma mapping with chroma scaling (LMC) parameters, may be signaled for a picture. The indices of each of the APSs available to be used for the picture are also signaled at the picture level. Instead of further signaling APS indices indicating the APSs that may be used at each sub-picture (e.g., slice, tile group, tile, brick, etc.) of the picture at a sub-picture level, a video encoder may signal a single syntax element that indicates that all APSs signaled for the picture at the picture level are available for use at each sub-picture without further sub-picture level signaling. Alternatively, this syntax element is not signaled, such that all APSs signaled for the picture at the picture level are available for use at each sub-picture without further sub-picture level signaling. As such, signaling overhead is reduced and coding efficiency may be increased.

<FIG> is a block diagram illustrating an example video encoding and decoding system <NUM> that may perform the techniques of this disclosure. The techniques of this disclosure are generally directed to coding (encoding and/or decoding) video data. In general, video data includes any data for processing a video. Thus, video data may include raw, unencoded video, encoded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

As shown in <FIG>, system <NUM> includes a source device <NUM> that provides encoded video data to be decoded and displayed by a destination device <NUM>, in this example. In particular, source device <NUM> provides the video data to destination device <NUM> via a computer-readable medium <NUM>. Source device <NUM> and destination device <NUM> may comprise any of a wide range of devices, including desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, telephone handsets such smartphones, televisions, cameras, display devices, digital media players, video gaming consoles, video streaming device, or the like. In some cases, source device <NUM> and destination device <NUM> may be equipped for wireless communication, and thus may be referred to as wireless communication devices.

In the example of <FIG>, source device <NUM> includes video source <NUM>, memory <NUM>, video encoder <NUM>, and output interface <NUM>. Destination device <NUM> includes input interface <NUM>, video decoder <NUM>, memory <NUM>, and display device <NUM>. In accordance with this disclosure, video encoder <NUM> of source device <NUM> and video decoder <NUM> of destination device <NUM> may be configured to apply techniques for coding an adaptation parameter set (APS) for video data in accordance with one or more memory constraints. Thus, source device <NUM> represents an example of a video encoding device, while destination device <NUM> represents an example of a video decoding device. In other examples, a source device and a destination device may include other components or arrangements. For example, source device <NUM> may receive video data from an external video source, such as an external camera. Likewise, destination device <NUM> may interface with an external display device, rather than including an integrated display device.

System <NUM> as shown in <FIG> is merely one example. In general, any digital video encoding and/or decoding device may perform techniques for coding an adaptation parameter set for video data in accordance with one or more memory constraints. Source device <NUM> and destination device <NUM> are merely examples of such coding devices in which source device <NUM> generates coded video data for transmission to destination device <NUM>. This disclosure refers to a "coding" device as a device that performs coding (encoding and/or decoding) of data. Thus, video encoder <NUM> and video decoder <NUM> represent examples of coding devices, in particular, a video encoder and a video decoder, respectively. In some examples, devices <NUM>, <NUM> may operate in a substantially symmetrical manner such that each of devices <NUM>, <NUM> include video encoding and decoding components. Hence, system <NUM> may support one-way or two-way video transmission between video devices <NUM>, <NUM>, e.g., for video streaming, video playback, video broadcasting, or video telephony.

In general, video source <NUM> represents a source of video data (i.e., raw, unencoded video data) and provides a sequential series of pictures (also referred to as "frames") of the video data to video encoder <NUM>, which encodes data for the pictures. Video source <NUM> of source device <NUM> may include a video capture device, such as a video camera, a video archive containing previously captured raw video, and/or a video feed interface to receive video from a video content provider. As a further alternative, video source <NUM> may generate computer graphics-based data as the source video, or a combination of live video, archived video, and computer-generated video. In each case, video encoder <NUM> encodes the captured, pre-captured, or computer-generated video data. Video encoder <NUM> may rearrange the pictures from the received order (sometimes referred to as "display order") into a coding order for coding. Video encoder <NUM> may generate a bitstream including encoded video data. Source device <NUM> may then output the encoded video data via output interface <NUM> onto computer-readable medium <NUM> for reception and/or retrieval by, e.g., input interface <NUM> of destination device <NUM>.

Memory <NUM> of source device <NUM> and memory <NUM> of destination device <NUM> represent general purpose memories. In some examples, memories <NUM>, <NUM> may store raw video data, e.g., raw video from video source <NUM> and raw, decoded video data from video decoder <NUM>. Additionally or alternatively, memories <NUM>, <NUM> may store software instructions executable by, e.g., video encoder <NUM> and video decoder <NUM>, respectively. Although shown separately from video encoder <NUM> and video decoder <NUM> in this example, it should be understood that video encoder <NUM> and video decoder <NUM> may also include internal memories for functionally similar or equivalent purposes. Furthermore, memories <NUM>, <NUM> may store encoded video data, e.g., output from video encoder <NUM> and input to video decoder <NUM>. In some examples, portions of memories <NUM>, <NUM> may be allocated as one or more video buffers, e.g., to store raw, decoded, and/or encoded video data.

Computer-readable medium <NUM> may represent any type of medium or device capable of transporting the encoded video data from source device <NUM> to destination device <NUM>. In one example, computer-readable medium <NUM> represents a communication medium to enable source device <NUM> to transmit encoded video data directly to destination device <NUM> in real-time, e.g., via a radio frequency network or computer-based network. Output interface <NUM> may modulate a transmission signal including the encoded video data, and input interface <NUM> may demodulate the received transmission signal, according to a communication standard, such as a wireless communication protocol. The communication medium may comprise any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful to facilitate communication from source device <NUM> to destination device <NUM>.

In some examples, source device <NUM> may output encoded data from output interface <NUM> to storage device <NUM>. Similarly, destination device <NUM> may access encoded data from storage device <NUM> via input interface <NUM>. Storage device <NUM> may include any of a variety of distributed or locally accessed data storage media such as a hard drive, Blu-ray discs, DVDs, CD-ROMs, flash memory, volatile or non-volatile memory, or any other suitable digital storage media for storing encoded video data.

In some examples, source device <NUM> may output encoded video data to file server <NUM> or another intermediate storage device that may store the encoded video generated by source device <NUM>. Destination device <NUM> may access stored video data from file server <NUM> via streaming or download. File server <NUM> may be any type of server device capable of storing encoded video data and transmitting that encoded video data to the destination device <NUM>. File server <NUM> may represent a web server (e.g., for a website), a File Transfer Protocol (FTP) server, a content delivery network device, or a network attached storage (NAS) device. Destination device <NUM> may access encoded video data from file server <NUM> through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., digital subscriber line (DSL), cable modem, etc.), or a combination of both that is suitable for accessing encoded video data stored on file server <NUM>. File server <NUM> and input interface <NUM> may be configured to operate according to a streaming transmission protocol, a download transmission protocol, or a combination thereof.

Output interface <NUM> and input interface <NUM> may represent wireless transmitters/receivers, modems, wired networking components (e.g., Ethernet cards), wireless communication components that operate according to any of a variety of IEEE <NUM> standards, or other physical components. In examples where output interface <NUM> and input interface <NUM> comprise wireless components, output interface <NUM> and input interface <NUM> may be configured to transfer data, such as encoded video data, according to a cellular communication standard, such as <NUM>, <NUM>-LTE (Long-Term Evolution), LTE Advanced, <NUM>, or the like. In some examples where output interface <NUM> comprises a wireless transmitter, output interface <NUM> and input interface <NUM> may be configured to transfer data, such as encoded video data, according to other wireless standards, such as an IEEE <NUM> specification, an IEEE <NUM> specification (e.g., ZigBee™), a Bluetooth™ standard, or the like. In some examples, source device <NUM> and/or destination device <NUM> may include respective system-on-a-chip (SoC) devices. For example, source device <NUM> may include an SoC device to perform the functionality attributed to video encoder <NUM> and/or output interface <NUM>, and destination device <NUM> may include an SoC device to perform the functionality attributed to video decoder <NUM> and/or input interface <NUM>.

Input interface <NUM> of destination device <NUM> receives an encoded video bitstream from computer-readable medium <NUM> (e.g., storage device <NUM>, file server <NUM>, or the like). The encoded video bitstream may include signaling information defined by video encoder <NUM>, which is also used by video decoder <NUM>, such as syntax elements having values that describe characteristics and/or processing of video blocks or other coded units (e.g., slices, pictures, groups of pictures, sequences, or the like). Display device <NUM> displays decoded pictures of the decoded video data to a user. Display device <NUM> may represent any of a variety of display devices such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

Video encoder <NUM> and video decoder <NUM> may operate according to a video coding standard, such as ITU-T H. <NUM>, also referred to as High Efficiency Video Coding (HEVC) or extensions thereto, such as the multi-view and/or scalable video coding extensions. Alternatively, video encoder <NUM> and video decoder <NUM> may operate according to other proprietary or industry standards, such as the Joint Exploration Test Model (JEM) or ITU-T H. <NUM>, also referred to as Versatile Video Coding (VVC). A draft of the VVC standard is described in <NPL>"). The techniques of this disclosure, however, are not limited to any particular coding standard.

As another example, video encoder <NUM> and video decoder <NUM> may be configured to operate according to VVC. According to VVC, a video coder (such as video encoder <NUM>) partitions a picture into a plurality of coding tree units (CTUs). Video encoder <NUM> may partition a CTU according to a tree structure, such as a quadtree-binary tree (QTBT) structure or Multi-Type Tree (MTT) structure. The QTBT structure removes the concepts of multiple partition types, such as the separation between CUs, PUs, and TUs of HEVC. A QTBT structure includes two levels: a first level partitioned according to quadtree partitioning, and a second level partitioned according to binary tree partitioning. A root node of the QTBT structure corresponds to a CTU. Leaf nodes of the binary trees correspond to coding units (CUs).

In an MTT partitioning structure, blocks may be partitioned using a quadtree (QT) partition, a binary tree (BT) partition, and one or more types of triple tree (TT) (also called ternary tree (TT)) partitions. A triple or ternary tree partition is a partition where a block is split into three sub-blocks. In some examples, a triple or ternary tree partition divides a block into three sub-blocks without dividing the original block through the center. The partitioning types in MTT (e.g., QT, BT, and TT), may be symmetrical or asymmetrical.

In some examples, a CTU includes a coding tree block (CTB) of luma samples, two corresponding CTBs of chroma samples of a picture that has three sample arrays, or a CTB of samples of a monochrome picture or a picture that is coded using three separate color planes and syntax structures used to code the samples. A CTB may be an NxN block of samples for some value of N such that the division of a component into CTBs is a partitioning. A component is an array or single sample from one of the three arrays (luma and two chroma) that compose a picture in <NUM>:<NUM>:<NUM>, <NUM>:<NUM>:<NUM>, or <NUM>:<NUM>:<NUM> color format or the array or a single sample of the array that compose a picture in monochrome format. In some examples, a coding block is an MxN block of samples for some values of M and N such that a division of a CTB into coding blocks is a partitioning.

The blocks (e.g., CTUs or CUs) may be grouped in various ways in a picture. As one example, a brick may refer to a rectangular region of CTU rows within a particular tile in a picture. A tile may be a rectangular region of CTUs within a particular tile column and a particular tile row in a picture. A tile column refers to a rectangular region of CTUs having a height equal to the height of the picture and a width specified by syntax elements (e.g., such as in a picture parameter set). A tile row refers to a rectangular region of CTUs having a height specified by syntax elements (e.g., such as in a picture parameter set) and a width equal to the width of the picture.

In some examples, a tile may be partitioned into multiple bricks, each of which may include one or more CTU rows within the tile. A tile that is not partitioned into multiple bricks may also be referred to as a brick. However, a brick that is a true subset of a tile may not be referred to as a tile.

The bricks in a picture may also be arranged in a slice. A slice may be an integer number of bricks of a picture that may be exclusively contained in a single network abstraction layer (NAL) unit. In some examples, a slice includes either a number of complete tiles or only a consecutive sequence of complete bricks of one tile.

Some examples of VVC also provide an affine motion compensation mode, which may be considered an inter-prediction mode. In affine motion compensation mode, video encoder <NUM> may determine two or more motion vectors that represent non-translational motion, such as zoom in or out, rotation, perspective motion, or other irregular motion types.

To perform intra-prediction, video encoder <NUM> may select an intra-prediction mode to generate the prediction block. Some examples of VVC provide sixty-seven intra-prediction modes, including various directional modes, as well as planar mode and DC mode. In general, video encoder <NUM> selects an intra-prediction mode that describes neighboring samples to a current block (e.g., a block of a CU) from which to predict samples of the current block. Such samples may generally be above, above and to the left, or to the left of the current block in the same picture as the current block, assuming video encoder <NUM> codes CTUs and CUs in raster scan order (left to right, top to bottom).

As noted above, following any transforms to produce transform coefficients, video encoder <NUM> may perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, providing further compression. By performing the quantization process, video encoder <NUM> may reduce the bit depth associated with some or all of the transform coefficients. For example, video encoder <NUM> may round an n-bit value down to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, video encoder <NUM> may perform a bitwise right-shift of the value to be quantized.

Following quantization, video encoder <NUM> may scan the transform coefficients, producing a one-dimensional vector from the two-dimensional matrix including the quantized transform coefficients. The scan may be designed to place higher energy (and therefore lower frequency) transform coefficients at the front of the vector and to place lower energy (and therefore higher frequency) transform coefficients at the back of the vector. In some examples, video encoder <NUM> may utilize a predefined scan order to scan the quantized transform coefficients to produce a serialized vector, and then entropy encode the quantized transform coefficients of the vector. In other examples, video encoder <NUM> may perform an adaptive scan. After scanning the quantized transform coefficients to form the one-dimensional vector, video encoder <NUM> may entropy encode the one-dimensional vector, e.g., according to context-adaptive binary arithmetic coding (CABAC). Video encoder <NUM> may also entropy encode values for syntax elements describing metadata associated with the encoded video data for use by video decoder <NUM> in decoding the video data.

In general, video decoder <NUM> performs a reciprocal process to that performed by video encoder <NUM> to decode the encoded video data of the bitstream. For example, video decoder <NUM> may decode values for syntax elements of the bitstream using CABAC in a manner substantially similar to, albeit reciprocal to, the CABAC encoding process of video encoder <NUM>. The syntax elements may define partitioning information for partitioning of a picture into CTUs, and partitioning of each CTU according to a corresponding partition structure, such as a QTBT structure, to define CUs of the CTU. The syntax elements may further define prediction and residual information for blocks (e.g., CUs) of video data.

In accordance with the techniques of this disclosure, video encoder <NUM> and video decoder <NUM> may be configured to code an APS according to a memory constraint, wherein the APS includes one or more of parameters for an adaptive loop filter or parameters for luma mapping with chroma scaling, and code one or blocks of video data in accordance with the APS.

In another example of the disclosure, video encoder <NUM> may be configured to encode one or more first adaptation parameter set (APS) indices for a current picture that indicate one or more first APSs that may be used for decoding the current picture. In some examples, video encoder <NUM> may encode the first APS indices at the picture level. Video decoder <NUM> may decode the one or more first APS indices for a current picture that indicate one or more first APSs that may be used for decoding the current picture, determine, for a block of a sub-picture of the current picture, an APS from the one or more first APSs indicated for the current picture, and decode the block of the sub-picture using the determined APS. In one example, video decoder <NUM> may determine, for the block of the sub-picture of the current picture, the APS from the one or more first APSs indicated for the current picture without decoding any syntax elements, at a sub-picture level, indicating APSs that may be used for decoding the sub-picture.

This disclosure may generally refer to "signaling" certain information, such as syntax elements. The term "signaling" may generally refer to the communication of values for syntax elements and/or other data used to decode encoded video data. That is, video encoder <NUM> may signal values for syntax elements in the bitstream. In general, signaling refers to generating a value in the bitstream. As noted above, source device <NUM> may transport the bitstream to destination device <NUM> substantially in real time, or not in real time, such as might occur when storing syntax elements to storage device <NUM> for later retrieval by destination device <NUM>.

<FIG> are conceptual diagrams illustrating an example quadtree binary tree (QTBT) structure <NUM>, and a corresponding coding tree unit (CTU) <NUM>. The solid lines represent quadtree splitting, and dotted lines indicate binary tree splitting. In each split (i.e., non-leaf) node of the binary tree, one flag is signaled to indicate which splitting type (i.e., horizontal or vertical) is used, where <NUM> indicates horizontal splitting and <NUM> indicates vertical splitting in this example. For the quadtree splitting, there is no need to indicate the splitting type, because quadtree nodes split a block horizontally and vertically into <NUM> sub-blocks with equal size. Accordingly, video encoder <NUM> may encode, and video decoder <NUM> may decode, syntax elements (such as splitting information) for a region tree level of QTBT structure <NUM> (i.e., the solid lines) and syntax elements (such as splitting information) for a prediction tree level of QTBT structure <NUM> (i.e., the dashed lines). Video encoder <NUM> may encode, and video decoder <NUM> may decode, video data, such as prediction and transform data, for CUs represented by terminal leaf nodes of QTBT structure <NUM>.

In one example of the QTBT partitioning structure, the CTU size is set as 128x128 (luma samples and two corresponding 64x64 chroma samples), the MinQTSize is set as 16x16, the MaxBTSize is set as 64x64, the MinBTSize (for both width and height) is set as <NUM>, and the MaxBTDepth is set as <NUM>. The quadtree partitioning is applied to the CTU first to generate quad-tree leaf nodes. The quadtree leaf nodes may have a size from 16x16 (i.e., the MinQTSize) to 128x128 (i.e., the CTU size). If the quadtree leaf node is 128x128, the leaf quadtree node will not be further split by the binary tree, because the size exceeds the MaxBTSize (i.e., 64x64, in this example). Otherwise, the quadtree leaf node will be further partitioned by the binary tree. Therefore, the quadtree leaf node is also the root node for the binary tree and has the binary tree depth as <NUM>. When the binary tree depth reaches MaxBTDepth (<NUM>, in this example), no further splitting is permitted. When the binary tree node has a width equal to MinBTSize (<NUM>, in this example), it implies that no further vertical splitting is permitted. Similarly, a binary tree node having a height equal to MinBTSize implies that no further horizontal splitting is permitted for that binary tree node. As noted above, leaf nodes of the binary tree are referred to as CUs, and are further processed according to prediction and transform without further partitioning.

<FIG> is a block diagram illustrating an example video encoder <NUM> that may perform the techniques of this disclosure. <FIG> is provided for purposes of explanation and should not be considered limiting of the techniques as broadly exemplified and described in this disclosure. For purposes of explanation, this disclosure describes video encoder <NUM> according to the techniques of VVC (ITU-T H. <NUM>, under development), and HEVC (ITU-T H. However, the techniques of this disclosure may be performed by video encoding devices that are configured to other video coding standards.

In the example of <FIG>, video encoder <NUM> includes video data memory <NUM>, mode selection unit <NUM>, residual generation unit <NUM>, transform processing unit <NUM>, quantization unit <NUM>, inverse quantization unit <NUM>, inverse transform processing unit <NUM>, reconstruction unit <NUM>, filter unit <NUM>, decoded picture buffer (DPB) <NUM>, and entropy encoding unit <NUM>. Any or all of video data memory <NUM>, mode selection unit <NUM>, residual generation unit <NUM>, transform processing unit <NUM>, quantization unit <NUM>, inverse quantization unit <NUM>, inverse transform processing unit <NUM>, reconstruction unit <NUM>, filter unit <NUM>, DPB <NUM>, and entropy encoding unit <NUM> may be implemented in one or more processors or in processing circuitry. For instance, the units of video encoder <NUM> may be implemented as one or more circuits or logic elements as part of hardware circuitry, or as part of a processor, ASIC, of FPGA. Moreover, video encoder <NUM> may include additional or alternative processors or processing circuitry to perform these and other functions.

The various units of <FIG> are illustrated to assist with understanding the operations performed by video encoder <NUM>. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide particular functionality, and are preset on the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks, and provide flexible functionality in the operations that can be performed. For instance, programmable circuits may execute software or firmware that cause the programmable circuits to operate in the manner defined by instructions of the software or firmware. Fixed-function circuits may execute software instructions (e.g., to receive parameters or output parameters), but the types of operations that the fixed-function circuits perform are generally immutable. In some examples, one or more of the units may be distinct circuit blocks (fixed-function or programmable), and in some examples, one or more of the units may be integrated circuits.

Video encoder <NUM> may include arithmetic logic units (ALUs), elementary function units (EFUs), digital circuits, analog circuits, and/or programmable cores, formed from programmable circuits. In examples where the operations of video encoder <NUM> are performed using software executed by the programmable circuits, memory <NUM> (<FIG>) may store the instructions (e.g., object code) of the software that video encoder <NUM> receives and executes, or another memory within video encoder <NUM> (not shown) may store such instructions.

Mode selection unit <NUM> includes a motion estimation unit <NUM>, a motion compensation unit <NUM>, and an intra-prediction unit <NUM>. Mode selection unit <NUM> may include additional functional units to perform video prediction in accordance with other prediction modes. As examples, mode selection unit <NUM> may include a palette unit, an intra-block copy unit (which may be part of motion estimation unit <NUM> and/or motion compensation unit <NUM>), an affine unit, a linear model (LM) unit, or the like.

Video encoder <NUM> may partition a picture retrieved from video data memory <NUM> into a series of CTUs, and encapsulate one or more CTUs within a slice. Mode selection unit <NUM> may partition a CTU of the picture in accordance with a tree structure, such as the QTBT structure or the quad-tree structure of HEVC described above. As described above, video encoder <NUM> may form one or more CUs from partitioning a CTU according to the tree structure. Such a CU may also be referred to generally as a "video block" or "block.

Motion estimation unit <NUM> may form one or more motion vectors (MVs) that defines the positions of the reference blocks in the reference pictures relative to the position of the current block in a current picture. Motion estimation unit <NUM> may then provide the motion vectors to motion compensation unit <NUM>. For example, for uni-directional inter-prediction, motion estimation unit <NUM> may provide a single motion vector, whereas for bi-directional inter-prediction, motion estimation unit <NUM> may provide two motion vectors. Motion compensation unit <NUM> may then generate a prediction block using the motion vectors. For example, motion compensation unit <NUM> may retrieve data of the reference block using the motion vector. As another example, if the motion vector has fractional sample precision, motion compensation unit <NUM> may interpolate values for the prediction block according to one or more interpolation filters. Moreover, for bi-directional inter-prediction, motion compensation unit <NUM> may retrieve data for two reference blocks identified by respective motion vectors and combine the retrieved data, e.g., through sample-by-sample averaging or weighted averaging.

Mode selection unit <NUM> provides the prediction block to residual generation unit <NUM>. Residual generation unit <NUM> receives a raw, unencoded version of the current block from video data memory <NUM> and the prediction block from mode selection unit <NUM>. Residual generation unit <NUM> calculates sample-by-sample differences between the current block and the prediction block. The resulting sample-by-sample differences define a residual block for the current block. In some examples, residual generation unit <NUM> may also determine differences between sample values in the residual block to generate a residual block using residual differential pulse code modulation (RDPCM). In some examples, residual generation unit <NUM> may be formed using one or more subtractor circuits that perform binary subtraction.

In examples where mode selection unit <NUM> does not further partition a CU into PUs, each CU may be associated with a luma coding block and corresponding chroma coding blocks. As above, the size of a CU may refer to the size of the luma coding block of the CU. The video encoder <NUM> and video decoder <NUM> may support CU sizes of 2Nx2N, 2NxN, or Nx2N.

For other video coding techniques such as an intra-block copy mode coding, an affine-mode coding, and linear model (LM) mode coding, as a few examples, mode selection unit <NUM>, via respective units associated with the coding techniques, generates a prediction block for the current block being encoded. In some examples, such as palette mode coding, mode selection unit <NUM> may not generate a prediction block, and instead generate syntax elements that indicate the manner in which to reconstruct the block based on a selected palette. In such modes, mode selection unit <NUM> may provide these syntax elements to entropy encoding unit <NUM> to be encoded.

Quantization unit <NUM> may quantize the transform coefficients in a transform coefficient block, to produce a quantized transform coefficient block. Quantization unit <NUM> may quantize transform coefficients of a transform coefficient block according to a quantization parameter (QP) value associated with the current block. Video encoder <NUM> (e.g., via mode selection unit <NUM>) may adjust the degree of quantization applied to the transform coefficient blocks associated with the current block by adjusting the QP value associated with the CU. Quantization may introduce loss of information, and thus, quantized transform coefficients may have lower precision than the original transform coefficients produced by transform processing unit <NUM>.

Filter unit <NUM> may perform one or more filter operations on reconstructed blocks. For example, filter unit <NUM> may perform deblocking operations to reduce blockiness artifacts along edges of CUs. Operations of filter unit <NUM> may be skipped, in some examples.

Video encoder <NUM> stores reconstructed blocks in DPB <NUM>. For instance, in examples where operations of filter unit <NUM> are not needed, reconstruction unit <NUM> may store reconstructed blocks to DPB <NUM>. In examples where operations of filter unit <NUM> are needed, filter unit <NUM> may store the filtered reconstructed blocks to DPB <NUM>. Motion estimation unit <NUM> and motion compensation unit <NUM> may retrieve a reference picture from DPB <NUM>, formed from the reconstructed (and potentially filtered) blocks, to inter-predict blocks of subsequently encoded pictures. In addition, intra-prediction unit <NUM> may use reconstructed blocks in DPB <NUM> of a current picture to intra-predict other blocks in the current picture.

In some examples, operations performed with respect to a luma coding block need not be repeated for the chroma coding blocks. As one example, operations to identify a motion vector (MV) and reference picture for a luma coding block need not be repeated for identifying an MV and reference picture for the chroma blocks. Rather, the MV for the luma coding block may be scaled to determine the MV for the chroma blocks, and the reference picture may be the same. As another example, the intra-prediction process may be the same for the luma coding block and the chroma coding blocks.

Video encoder <NUM> represents an example of a device configured to encode video data including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to code an APS according to a memory constraint, wherein the APS includes one or more of parameters for an adaptive loop filter or parameters for luma mapping with chroma scaling, and code one or blocks of video data in accordance with the APS. In another example of the disclosure, as will be explained in more detail below, video encoder <NUM> may be configured to encode one or more first APS indices for a current picture that indicate one or more first APSs that may be used for decoding the current picture. In some examples, video encoder <NUM> may encode the first APS indices at the picture level.

<FIG> is a block diagram illustrating an example video decoder <NUM> that may perform the techniques of this disclosure. <FIG> is provided for purposes of explanation and is not limiting on the techniques as broadly exemplified and described in this disclosure. For purposes of explanation, this disclosure describes video decoder <NUM> according to the techniques of VVC (ITU-T H. <NUM>, under development), and HEVC (ITU-T H. However, the techniques of this disclosure may be performed by video coding devices that are configured to other video coding standards.

In the example of <FIG>, video decoder <NUM> includes coded picture buffer (CPB) memory <NUM>, APS memory <NUM>, entropy decoding unit <NUM>, prediction processing unit <NUM>, inverse quantization unit <NUM>, inverse transform processing unit <NUM>, reconstruction unit <NUM>, filter unit <NUM>, and decoded picture buffer (DPB) <NUM>. Any or all of CPB memory <NUM>, entropy decoding unit <NUM>, prediction processing unit <NUM>, inverse quantization unit <NUM>, inverse transform processing unit <NUM>, reconstruction unit <NUM>, filter unit <NUM>, and DPB <NUM> may be implemented in one or more processors or in processing circuitry. For instance, the units of video decoder <NUM> may be implemented as one or more circuits or logic elements as part of hardware circuitry, or as part of a processor, ASIC, of FPGA. Moreover, video decoder <NUM> may include additional or alternative processors or processing circuitry to perform these and other functions.

Prediction processing unit <NUM> includes motion compensation unit <NUM> and intra-prediction unit <NUM>. Prediction processing unit <NUM> may include additional units to perform prediction in accordance with other prediction modes. As examples, prediction processing unit <NUM> may include a palette unit, an intra-block copy unit (which may form part of motion compensation unit <NUM>), an affine unit, a linear model (LM) unit, or the like. In other examples, video decoder <NUM> may include more, fewer, or different functional components.

CPB memory <NUM> may store video data, such as an encoded video bitstream, to be decoded by the components of video decoder <NUM>. The video data stored in CPB memory <NUM> may be obtained, for example, from computer-readable medium <NUM> (<FIG>). CPB memory <NUM> may include a CPB that stores encoded video data (e.g., syntax elements) from an encoded video bitstream. Also, CPB memory <NUM> may store video data other than syntax elements of a coded picture, such as temporary data representing outputs from the various units of video decoder <NUM>. DPB <NUM> generally stores decoded pictures, which video decoder <NUM> may output and/or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. CPB memory <NUM> and DPB <NUM> may be formed by any of a variety of memory devices, such as DRAM, including SDRAM, MRAM, RRAM, or other types of memory devices. CPB memory <NUM> and DPB <NUM> may be provided by the same memory device or separate memory devices. In various examples, CPB memory <NUM> may be on-chip with other components of video decoder <NUM>, or off-chip relative to those components.

Additionally or alternatively, in some examples, video decoder <NUM> may retrieve coded video data from memory <NUM> (<FIG>). That is, memory <NUM> may store data as discussed above with CPB memory <NUM>. Likewise, memory <NUM> may store instructions to be executed by video decoder <NUM>, when some or all of the functionality of video decoder <NUM> is implemented in software to be executed by processing circuitry of video decoder <NUM>.

The various units shown in <FIG> are illustrated to assist with understanding the operations performed by video decoder <NUM>. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Similar to <FIG>, fixed-function circuits refer to circuits that provide particular functionality, and are preset on the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks, and provide flexible functionality in the operations that can be performed. For instance, programmable circuits may execute software or firmware that cause the programmable circuits to operate in the manner defined by instructions of the software or firmware. Fixed-function circuits may execute software instructions (e.g., to receive parameters or output parameters), but the types of operations that the fixed-function circuits perform are generally immutable. In some examples, one or more of the units may be distinct circuit blocks (fixed-function or programmable), and in some examples, one or more of the units may be integrated circuits.

After inverse quantization unit <NUM> forms the transform coefficient block, inverse transform processing unit <NUM> may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, inverse transform processing unit <NUM> may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse directional transform, or another inverse transform to the transform coefficient block.

Filter unit <NUM> may perform one or more filter operations on reconstructed blocks. For example, filter unit <NUM> may perform deblocking operations to reduce blockiness artifacts along edges of the reconstructed blocks. Operations of filter unit <NUM> are not necessarily performed in all examples.

APS memory <NUM> may store data associated with one or more APSs, including parameters for ALF and/or LMCS. Video decoder <NUM> may use the ALF parameters and/or the LMCS parameters in a particular APS from the one more APSs stored in APS memory <NUM> to decode blocks of video data. In other examples, the APSs may store parameters for a scaling matrix. APS memory <NUM> may be configured to store other video data that may be communicated in an APS. APS memory <NUM> may be formed by any of a variety of memory devices, such as DRAM, including SDRAM, MRAM, RRAM, or other types of memory devices. APS memory <NUM> may be provided by the same memory device as CPB memory <NUM> and/or DPB <NUM>, or APS memory <NUM> may be a separate memory device. In various examples, APS memory <NUM> may be on-chip with other components of video decoder <NUM>, or off-chip relative to those components.

As will be explained in more detail below, video decoder <NUM> may receive and store one or more APSs in APS memory <NUM>. Video decoder <NUM> may be further configured to decode one or more APS indices (e.g., from a picture header) for a current picture that indicate one or more APSs that may be used for decoding the current picture. That is, the APS indices indicate the particular APSs of a plurality of APSs that are used to decode the current picture. Video decoder <NUM> may then determine, for a block of a sub-picture of the current picture, an APS from the one or more APSs indicated for the current picture. Sub-picture may include one or more of a slice, a tile group, a tile, a brick, or any other subset of a picture. Video decoder <NUM> may then decode the block of the sub-picture using the determined APS.

In other examples, video decoder <NUM> may first decode a syntax element (e.g., a flag) that indicates whether the one or more APSs indicated by the one or more APS indices for the current picture (e.g., from the picture header) may be used for sub-pictures of the current picture. Based on this syntax element indicating that the one or more APSs indicated by the one or more APS indices for the current picture may be used at sub-pictures of the current picture, video decoder <NUM> may determine, for the block of the sub-picture of the current picture, the APS from the one or more APSs indicated for the current picture without decoding any syntax elements, at a sub-picture level, indicating APSs that may be used for decoding the sub-picture. As such, signaling overhead is reduced and coding efficiency may be increased. At the block level, video decoder <NUM> may decode an index for the APS for the block of the sub-picture of the current picture.

In other examples, video encoder <NUM> does not signal a syntax element that indicates whether the one or more APSs indicated by the one or more APS indices for the current picture (e.g., from the picture header) may be used at sub-pictures of the current picture. Rather, video decoder <NUM> may use all APSs signaled for the picture at the picture level at each sub-picture without further sub-picture level signaling.

Based on the syntax element (e.g., flag) indicating that the one or more APSs indicated by the one or more APS indices for the current picture may not be used at sub-pictures of the current picture, video decoder <NUM> may decode, at the sub-picture level, one or more additional APS indices indicating the one or more APSs that may be used at the sub-picture of the current picture.

Video decoder <NUM> may store the reconstructed blocks in DPB <NUM>. For instance, in examples where operations of filter unit <NUM> are not performed, reconstruction unit <NUM> may store reconstructed blocks to DPB <NUM>. In examples where operations of filter unit <NUM> are performed, filter unit <NUM> may store the filtered reconstructed blocks to DPB <NUM>. As discussed above, DPB <NUM> may provide reference information, such as samples of a current picture for intra-prediction and previously decoded pictures for subsequent motion compensation, to prediction processing unit <NUM>. Moreover, video decoder <NUM> may output decoded pictures (e.g., decoded video) from DPB <NUM> for subsequent presentation on a display device, such as display device <NUM> of <FIG>.

In this manner, video decoder <NUM> represents an example of a video decoding device including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to decode an APS according to a memory constraint, wherein the APS includes one or more of parameters for an adaptive loop filter or parameters for luma mapping with chroma scaling, and decode one or blocks of video data in accordance with the APS.

In another example, video decoder <NUM> may be configured to decode one or more first APS indices for a current picture that indicate one or more first APSs that may be used for decoding the current picture, determine, for a block of a sub-picture of the current picture, an APS from the one or more first APSs indicated for the current picture, and decode the block of the sub-picture using the determined APS.

In some examples, video encoder <NUM> may be configured to store and transmit filter parameters of an ALF and one or more parameters for LMCS techniques in one or more APSs. Video encoder <NUM> may be configured to encode and signal one or more APSs at the picture level or higher. When decoding a block of video data, video decoder <NUM> may be configured to receive an index (e.g., at a slice header) indicating the particular APS (e.g., an APS index called adaptation_parameter set id) to use, and determine one or more filters (e.g., an ALF) to use from the determined APS. For example, video decoder <NUM> may be configured to receive the APS index, decode the parameters, and apply the parameters in an ALF and/or LMCS process.

In VVC Draft <NUM>, an APS is defined as a syntax structure containing syntax elements that apply to zero or more slices as determined by zero or more syntax elements found in slice headers. Section <NUM>. <NUM> of VVC Draft <NUM> defines the following syntax elements and semantics for an APS.

In VVC Draft <NUM>, at the slice header level, the video encoder would further signal the number of ALF APSs (slice_num_alf_aps_ids_luma) that the slice may use, as well as an ALF APS index (slice_alf_aps_id_luma[ i ]) for each of the number of ALF APSs for the slice. Similar syntax elements are signaled for LMCS APSs. slice_num_alf_aps_ids_luma specifies the number of ALF APSs that the slice refers to. The value of slice_num_alf_aps_ids_luma shall be in the range of <NUM> to <NUM>, inclusive.

The maximum value maxVal of the truncated binary binarization tb(v) is set equal to <NUM> for intra slices and slices in an IRAP picture, and set equal to <NUM> otherwise. slice_alf_aps_id_luma[ i ] specifies the adaptation_parameter_set_id of the i-th ALF APS that the slice refers to. The TemporalId of the ALF APS NAL unit having adaptation_parameter_set_id equal to slice_alf_aps_id_luma[ i ] shall be less than or equal to the TemporalId of the coded slice NAL unit.

In VVC Test Model <NUM> (VTM-<NUM>) and<NPL>), an APS can contain up to <NUM> luma filters and <NUM> chroma filters for ALF. A picture may use multiple APSs and these APSs will be loaded to on-chip memory (e.g., an on-chip memory of video decoder <NUM>). In some examples, the amount of memory available on video decoder <NUM> may be limited and some implementations of video decoder <NUM> may lack memory overhead for APSs. In view of this potential drawback of increased memory usage for larger APSs, this disclosure proposes the following techniques, including techniques that apply memory constraints for storing APSs. The following techniques may be used individually or may be used together in any combination.

In general, the memory (e.g., APS memory <NUM> of <FIG>) that video decoder <NUM> may use to store an APS is variable. For example, video decoder <NUM> may be configured to variably allocate memory for APS memory <NUM> for storing APSs based on certain video characteristics and/or based on signalled syntax elements. Since the number of luma filters and chroma filters (e.g., for ALF) are not constant across slices and/or pictures, the actual memory allocated for APS memory <NUM> to store APSs may depend on the actual numbers of luma and chroma filters. In this case, the memory is constrained by a number of filters in all APSs instead of the number of APSs.

In one example of the disclosure, video decoder <NUM> may be configured to operate according to a pre-defined memory constraint and/or operate according to a memory constraint signaled in the encoded video bitstream at one or more of a sequence/picture/slice/tile group/tile/brick level, such that the memory allocated to APS memory <NUM> for the APSs used for one or more of a picture/slice/tile group/tile/brick cannot be larger than this memory constraint. Video decoder <NUM> may be configured to allocate memory to APS memory <NUM> for APSs based on this memory constraint.

Some example techniques may limit the total number of APSs. In some examples, APSs could include filter information for up to <NUM> luma ALFs and <NUM> chroma ALFs. In this scenario, video decoder <NUM> would be implemented with APS memory <NUM> having a size that would accommodate the total number of allowed APSs under the assumption that each of the APSs included filter information for the maximum number of filters. By applying a constraint to the amount of memory that may be used to store APSs, rather than limiting the total number of APSs, the techniques of this disclosure allow for the possibility of transmitting and storing a larger number of APSs (e.g., more than the previous limits) that each contain a smaller amount of filter information. More APSs, each with different parameters for ALFs, may provide for more flexibility in assigning ALFs to blocks of video data exhibiting different characteristics. As such, coding efficiency and/or distortion may be improved.

Accordingly, in one example of the disclosure, video decoder <NUM> may be configured to decode an APS according to a memory constraint, wherein the APS includes one or more of parameters for an ALF or parameters for LMCS, and decode one or blocks of video data in accordance with the APS.

In another example of the disclosure, video encoder <NUM> and video decoder <NUM> may be configured to code (e.g., encode and decode, respectively) a syntax element indicating the number of APSs used for a picture. Video encoder <NUM> and video decoder <NUM> may be configured to code (e.g., video encoder <NUM> may encode and signal and video decoder <NUM> may receive and decode), before the bitstream of a picture, a syntax element indicating the number of APSs in a picture level or higher syntax structure, such as in a picture header and/or picture parameter set (PPS). In one example, this number cannot be larger than a maximum number of APSs that could be used for a picture. This maximum number may be a fixed number or may be signaled (e.g., coded by video encoder <NUM> and received and decoded by video decoder <NUM>) in a sequence level header, such as a Video Parameter Set (VPS) and/or a Sequence Parameter Set (SPS). When coding a picture, after coding the number of APSs that are actually used for the picture, video encoder <NUM> and video decoder <NUM> may code the indices of all used APSs.

In another example of the disclosure and in accordance with the protected invention, based on the signaled and decoded APS indices for a current picture (e.g., signaled at a picture header), video decoder <NUM> may be configured to use those APSs indicated by the APS indices as available in the current picture, without further signaling at the sub-picture level, for all sub-pictures of the current picture. That is, rather than signaling the number of APSs and the indices for each APS that are used at the sub-picture level (e.g., at the slice header, as in VVC Draft <NUM>), every sub-picture in a current picture may use any of the ALF or LMCS data from any APS signaled at a picture level syntax structure as being available for the current picture. In this way, signaling overhead may be reduced and coding efficiency may be increased. Sub-pictures may include one or more of slices, tile groups, tiles, bricks, CTUs, and/or any other subset of a picture. In accordance with the protected invention a sub-picture comprise one or more of a slice, a tile group, a tile, or a brick. This inheritance (e.g., the reuse of APSs signaled at the picture level) can be achieved explicitly (e.g., through explicit signaling of a syntax element) or implicitly (e.g., determined without signaling a syntax element).

Accordingly, in one example of the disclosure and in accordance with the protected invention, video decoder <NUM> is configured to decode one or more first APS indices for a current picture that indicate one or more first APSs that may be used for decoding the current picture. For example, the first APS indices may be decoded from a picture header. Video decoder <NUM> is further configured to determine, for a block of a sub-picture of the current picture, an APS from the one or more first APSs indicated for the current picture. In some examples and in accordance with the protected invention, video decoder <NUM> is configured to determine, for the block of the sub-picture of the current picture, the APS from the one or more first APSs indicated for the current picture without decoding any syntax elements, at a sub-picture level, indicating APSs that may be used for decoding the sub-picture. That is, video encoder <NUM> would not signal the specific APS indices that are available for each specific sub-picture at a sub-picture level syntax structure (e.g., a slice header). Rather, all sub-pictures of a picture would be configured to use any of the APSs indicated at the higher, picture level syntax structure.

Video decoder <NUM> then decodes, in accordance with the protected invention, a specific APS index at the block level to determine the APS to use when decoding the block. That is, video decoder <NUM> is configured to decode the block of the sub-picture using the determined APS. When decoding the block of the sub-picture using the determined APS, video decoder <NUM> may be configured to apply one or more of an ALF associated with the determined APS or LMCS associated with the determined APS to the block of the sub-picture.

In another example of the disclosure, video encoder <NUM> and video decoder <NUM> may code one or more of multiple APS's for one or more of a slice/tile group/tile/brick that are used in that slice/tile group/tile/brick. That is, rather than using the technique described above for only signaling APS indices at the picture level, for other pictures, video encoder <NUM> and video decoder <NUM> may be configured to code APS indices at sub-picture level syntax. In this example, video decoder <NUM> may be configured to determine whether to decode APS indices at only the picture level, or whether to decode APS indices at both the picture level and the sub-picture level based on a separately signaled syntax element (e.g., a flag). In other examples, video decoder <NUM> may be configured to determine whether to decode APS indices at only the sub-picture level. That is, video encoder <NUM> and video decoder <NUM> may code a flag to indicate whether or not all picture-level APSs can be applied to one or more of a slice/tile group/tile/brick (e.g., a sub-picture of a picture).

Accordingly, in this example, video decoder <NUM> may be configured to decode a first syntax element (e.g., the flag discussed above) that indicates whether the one or more first APSs indicated by the one or more first APS indices for the current picture may be used at sub-pictures of the current picture. Based on the first syntax element indicating that the one or more first APSs indicated by the one or more first APS indices for the current picture may be used at sub-pictures of the current picture, video decoder <NUM> may be further configured to determine, for the block of the sub-picture of the current picture, the APS from the one or more first APSs indicated for the current picture without decoding any syntax elements, at a sub-picture level, indicating APSs that may be used for decoding the sub-picture. Video decoder <NUM> may then be further configured to decode an index for the APS for the block of the sub-picture of the current picture. In another example, video decoder <NUM> may be configured to implicitly determine, without decoding a syntax element, that the one or more first APSs indicated by the one or more first APS indices for the current picture may be used at sub-pictures of the current picture.

For a different picture, video decoder <NUM> may be configured to decode a second syntax element (e.g., the flag discussed above) that indicates whether one or more second APSs indicated by one or more second APS indices for a second picture may be used at sub-pictures of the second picture. In this case, the second syntax element indicates that the one or more second APSs indicated by the one or more second APS indices for the second picture may not be used at the sub-pictures of the second picture. As such, video decoder <NUM> may be configured to decode, based on the second syntax element indicating that the one or more second APSs indicated by the one or more second APS indices for the second picture may not be used at the sub-pictures of the second picture, one or more third APS indices indicating one or more third APSs that may be used at a sub-picture of the second picture. In this context, the one or more third APS indices are a subset of the one or more second APS indices.

In the example above, where not all picture-level APSs can be applied to one or more of a sub-picture slice/tile group/tile/brick, video encoder <NUM> and video decoder <NUM> may code the IDs (e.g., the indices) of those used APSs at the sub-picture level (e.g., the third APS indices described above). These third APSs may be a subset of those APSs available in a current picture (e.g., the second APSs described in the example above). For an APS type ti, let n(ti) be the number of APSs used for a picture and APSid(ti, j) with <NUM> <= j <= n(ti) - <NUM>) are the APS IDs of type ti used for the current picture. At the sub-picture level, video encoder <NUM> may signal a number <NUM> < n'(ti) < n(ti) - <NUM> to indicate how many APSs with type ti are used for a sub-picture. For each used APS of type ti, video encoder <NUM> may signal an index k ( <NUM><= k <= n'(ti) - <NUM>), such that the corresponding APS ID could be derived as APSid(ti , k). To signal this k, video encoder <NUM> may apply a fixed-length code with codeword length ceiling(log2(n'(ti)) + <NUM>). In other examples, truncated unary or truncated binary codes may be applied with maximum value equal to n'(ti) - <NUM>. Alternatively, other codewords could be used. Of course, video decoder <NUM> may be configured to decode the APS IDs (e.g., indices) signaled by video encoder <NUM>.

<FIG> is a flowchart illustrating an example method for encoding a current block. The current block may comprise a current CU. Although described with respect to video encoder <NUM> (<FIG> and <FIG>), it should be understood that other devices may be configured to perform a method similar to that of <FIG>.

In this example, video encoder <NUM> initially predicts the current block (<NUM>). For example, video encoder <NUM> may form a prediction block for the current block. Video encoder <NUM> may then calculate a residual block for the current block (<NUM>). To calculate the residual block, video encoder <NUM> may calculate a difference between the original, unencoded block and the prediction block for the current block. Video encoder <NUM> may then transform and quantize coefficients of the residual block (<NUM>). Next, video encoder <NUM> may scan the quantized transform coefficients of the residual block (<NUM>). During the scan, or following the scan, video encoder <NUM> may entropy encode the coefficients (<NUM>). For example, video encoder <NUM> may encode the coefficients using CAVLC or CABAC. Video encoder <NUM> may then output the entropy coded data of the block (<NUM>).

<FIG> is a flowchart illustrating an example method for decoding a current block of video data. The current block may comprise a current CU. Although described with respect to video decoder <NUM> (<FIG> and <FIG>), it should be understood that other devices may be configured to perform a method similar to that of <FIG>.

Video decoder <NUM> may receive entropy coded data for the current block, such as entropy coded prediction information and entropy coded data for coefficients of a residual block corresponding to the current block (<NUM>). Video decoder <NUM> may entropy decode the entropy coded data to determine prediction information for the current block and to reproduce coefficients of the residual block (<NUM>). Video decoder <NUM> may predict the current block (<NUM>), e.g., using an intra- or inter-prediction mode as indicated by the prediction information for the current block, to calculate a prediction block for the current block. Video decoder <NUM> may then inverse scan the reproduced coefficients (<NUM>), to create a block of quantized transform coefficients. Video decoder <NUM> may then inverse quantize and inverse transform the coefficients to produce a residual block (<NUM>). Video decoder <NUM> may ultimately decode the current block by combining the prediction block and the residual block (<NUM>).

<FIG> is a flowchart illustrating another example decoding method of the disclosure. The techniques of <FIG> may be performed by one or more structural components of video decoder <NUM>. In one example of the disclosure, video decoder <NUM> may be configured to decode one or more first adaptation parameter set (APS) indices for a current picture that indicate one or more first APSs that may be used for decoding the current picture (<NUM>). Video decoder <NUM> may determine, for a block of a sub-picture of the current picture, an APS from the one or more first APSs indicated for the current picture (<NUM>), and decode the block of the sub-picture using the determined APS (<NUM>).

In another example, to decode the one or more first APS indices for the current picture that indicate the one or more first APSs that may be used for decoding the current picture, video decoder <NUM> may be configured to decode the one or more first APS indices from a picture header.

In another example, the sub-picture comprises one or more of a slice, a tile group, a tile, or a brick.

In another example, video decoder <NUM> may be configured to decode a first syntax element that indicates whether the one or more first APSs indicated by the one or more first APS indices for the current picture may be used at sub-pictures of the current picture.

In another example, based on the first syntax element indicating that the one or more first APSs indicated by the one or more first APS indices for the current picture may be used at sub-pictures of the current picture, video decoder <NUM> may be configured to determine (e.g., explicitly or implicitly), for the block of the sub-picture of the current picture, the APS from the one or more first APSs indicated for the current picture without decoding any syntax elements, at a sub-picture level, indicating APSs that may be used for decoding the sub-picture. To determine, for the block of the sub-picture of the current picture, the APS from the one or more first APSs indicated for the current picture, video decoder <NUM> may be configured to decode an index for the APS for the block of the sub-picture of the current picture.

In another example, video decoder <NUM> may be configured to decode a second syntax element that indicates whether one or more second APSs indicated by one or more second APS indices for a second picture may be used at sub-pictures of the second picture, and decode, based on the second syntax element indicating that the one or more second APSs indicated by the one or more second APS indices for the second picture may not be used at the sub-pictures of the second picture, one or more third APS indices indicating one or more third APSs that may be used at a sub-picture of the second picture. In this example, the one or more third APS indices are a subset of the one or more second APS indices.

In another example, to decode the block of the sub-picture using the determined APS, video decoder <NUM> may be configured to apply one or more of an adaptive loop filter (ALF) associated with the determined APS or luma mapping with chroma scaling (LMCS) associated with the determined APS to the block of the sub-picture.

Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the terms "processor" and "processing circuitry," as used herein may refer to any of the foregoing structures or any other structure suitable for implementation of the techniques described herein.

Claim 1:
An apparatus configured to decode video data, the apparatus comprising:
a memory configured to store one or more blocks of video data; and
one or more processors implemented in circuitry and in communication with the memory, the one or more processors configured to:
decode (<NUM>) one or more first adaptation parameter set, APS, indices for a current picture that indicate one or more first APSs that may be used for decoding the current picture;
decode, at block level, an APS index for a block of a sub-picture of the current picture, to determine (<NUM>), for the block of a sub-picture of the current picture, an APS from the one or more first APSs indicated for the current picture, without decoding any syntax elements, at a sub-picture level, indicating APSs that may be used for decoding the sub-picture, wherein the sub-picture comprises one or more of a slice, a tile group, a tile, or a brick; and
decode (<NUM>) the block of the sub-picture using the determined APS.