Patent Description:
In a wireless communication device, a communication processor may perform communication-related control. A signal generated by the communication processor may be used to control a transceiver and radio frequency (RF) components. The transceiver, a device configured to transmit and receive wireless communication signals, may implement the functions of a transmitter and a receiver as a single module. The RF components may include an RF front end. In general, the RF front end refers to all the components between an antenna and the transceiver and may perform functions such as networking, file transfer, communication, card swipe, and/or positioning.

<CIT>, is about an electronic device which may include an antenna, a duplexer, a power amplification circuit, a processor, and a transceiver coupled to the processor and the power amplification circuit. The transceiver may include: a first phase locked loop (PLL) circuit; a first mixer; a detection circuit; a second phase locked loop (PLL) circuit; a second mixer; a first filter; and a second filter.

<CIT>, is about a digital phase lock loop (digital PLL) for an ultra-low power transceiver. According to an embodiment, a phase lock loop (PLL) includes a counter which measures voltage controlled oscillator (VCO) information on an oscillator during mask time, and a frequency tuner which controls a target frequency with the frequency of the oscillator according to a comparison result of the VOC and the target frequency information previously stored in a mapping table.

When there is a control problem such as a software code error or a timing alignment error in a process of controlling a transceiver by a communication processor, a failure may occur in performing wireless communication. When there is such a problem in a control process relating to a radio frequency (RF) transmission signal, RF components may be damaged.

A wireless communication device and a method for controlling activation of an RF transmission signal generation circuit according to an embodiment may employ a hardware control method for a transceiver and may therefore reduce the damage that may occur in RF components due to an issue occurring in a control process relating to an RF transmission signal.

According to an embodiment, there is provided a wireless communication device including: a communication processor; and a transceiver configured to be controlled by the communication processor to perform wireless communication, wherein the transceiver includes: a phase locked loop (PLL) circuit configured to generate a first oscillator signal based on a clock frequency signal; a radio frequency (RF) transmission signal generation circuit configured to generate an RF transmission signal based on the first oscillator signal received from the PLL circuit and a baseband transmission signal received from the communication processor; and a first decision circuit configured to receive a first phase comparison signal indicating whether a phase of the first oscillator signal is locked from a first phase comparator in the PLL circuit, and control activation of at least one component included in the RF transmission signal generation circuit based on the first phase comparison signal.

According to an embodiment, there is provided a method of controlling activation of an RF transmission signal generation circuit included in a transceiver of a wireless communication device configured to perform wireless communication, the method including: comparing, by a first phase comparator in a PLL circuit of the transceiver, a phase of a clock frequency signal and a phase of a first oscillator signal that is an output signal of the PLL circuit, and generating a first phase comparison signal indicating whether the phase of the first oscillator signal is locked; transferring, by the first phase comparator, the first phase comparison signal to a first decision circuit of the transceiver; controlling, by the first decision circuit, activation of at least one component included in the RF transmission signal generation circuit based on whether the phase of the first oscillator signal indicated in the first phase comparison signal is locked; in response to the at least one component being activated, generating, by the RF transmission signal generation circuit, an RF transmission signal from the first oscillator signal and a baseband transmission signal generated by a communication processor of the wireless communication device; and outputting, by the RF transmission signal generation circuit, the generated RF transmission signal.

A wireless communication device and a method for controlling activation of a radio frequency (RF) transmission signal generation circuit according to an embodiment may control activation of the RF transmission signal generation circuit when a transmission signal of a frequency out of a normal range is generated due to an error generated in a control process relating to an RF transmission signal, and may therefore reduce damage to components of the RF transmission signal generation circuit.

Hereinafter, examples/embodiments will be described in detail with reference to the accompanying drawings. When describing the embodiments with reference to the accompanying drawings, like reference numerals refer to like elements and a repeated description related thereto will be omitted.

The person skilled in the art will understand that the features described above and/or below may be combined in any way deemed useful. The drawings of the present disclosure show examples/embodiments of the invention, which will be described in detail hereinafter. It is to be understood that one or more of elements / components shown and/or described in one or more of these examples/embodiments and not in others may be used in those others too unless mechanical or other limitations prevent such an implementation. Moreover, describing features of different examples/embodiments in a single passage does not automatically mean that those features are inextricably linked. They may be applied separately from one another.

<FIG> is a diagram illustrating a configuration of a wireless communication device.

Referring to <FIG>, a wireless communication device <NUM> may include a communication processor <NUM>, a transceiver <NUM> configured to be controlled by the communication processor <NUM> to perform wireless communication, a radio frequency (RF) front-end circuit <NUM> configured to amplify an RF transmission signal and an RF reception signal, a power modulator <NUM> configured to supply power to an amplifier <NUM> of the RF front-end circuit <NUM>, and an antenna <NUM> configured to transmit and receive RF signals. The RF front-end circuit <NUM> may include, for example, the amplifier <NUM>, a duplexer <NUM>, and/or a coupler <NUM>.

The transceiver <NUM> may include a phase locked loop (PLL) circuit configured to generate an oscillator signal based on a clock frequency signal and an RF transmission signal generation circuit configured to generate an RF transmission signal Tx based on the oscillator signal received from the PLL circuit and a baseband transmission signal received from the communication processor <NUM>. Such components and/or functionalities are described/illustrated in more detail below with references being made to <FIG>.

In the wireless communication device <NUM>, the transceiver <NUM> may be controlled by the communication processor <NUM> based on software. However, when such software-based control is performed, the transceiver <NUM> may operate abnormally due to a human error leading for example to a software inaccuracy. For example, if the control of the transceiver <NUM> is not properly performed in a case of transmitting the RF transmission signal, an RF transmission signal of a frequency that is out of a normal range may be generated. For example, there may be a case in which, before a phase of an oscillator signal is locked, the transceiver <NUM> may generate an RF signal using the oscillator signal, and in this case, an RF transmission signal of an unintended frequency may be generated. There may be a frequency range of an RF transmission signal that is normally amplifiable by the RF front-end circuit <NUM> according to circuit characteristics of the wireless communication device <NUM>. When an RF transmission signal of an abnormal frequency that is out of such a normally amplifiable range by the RF front-end circuit <NUM> is amplified by the RF front-end circuit <NUM>, this may cause damage to components included in the RF front-end circuit <NUM>.

For example, the PLL circuit of the wireless communication device <NUM> may determine whether the phase of the oscillator signal is locked by comparing a clock frequency signal and the oscillator signal that is an output signal of the PLL circuit. In general, the PLL circuit may be configured to adjust the frequency of the oscillator signal to match the frequency of the clock frequency signal. In that sense, the clock frequency signal may be referred to as a reference signal having a reference frequency, for example generated by the wireless communication device <NUM> or received by the wireless communication device <NUM>. The wireless communication device <NUM> may include a decision circuit configured to control activation (or enable) of at least one component included in the RF transmission signal generation circuit based on whether the phase of the oscillator signal is locked. The decision circuit may activate at least one component included in the RF transmission signal generation circuit when the phase of the oscillator signal is locked and may deactivate at least one component included in the RF transmission signal generation circuit when the phase of the oscillator signal is not locked. The at least one component included in the RF transmission signal generation circuit may be, for example, an active component such as an amplifier, a voltage converter, and a mixer. When the at least one component included in the RF transmission signal generation circuit is deactivated, the RF transmission signal may not be generated in the RF transmission signal generation circuit. The wireless communication device <NUM> may be configured to activate the RF transmission signal generation circuit only when the phase of the oscillator signal is locked, thereby preventing the generation of an RF transmission signal of an abnormal frequency that may be generated by the oscillator signal with the phase not locked.

<FIG> is a diagram illustrating a first decision circuit configured to control activation of a RF transmission signal generation circuit. One or more of such components may be the same as and/or may be implemented together with components illustrated in and/or described with references being made to <FIG>, <FIG>.

Referring to <FIG>, an example block diagram of the transceiver <NUM> is shown. The transceiver <NUM> of the wireless communication device <NUM> may include a PLL circuit <NUM> configured to generate an oscillator signal based on a clock frequency signal. The PLL circuit <NUM> may include: a first buffer <NUM> configured to amplify the clock frequency signal and transfer it to a first phase comparator <NUM>; the first phase comparator <NUM> configured to compare phases of the clock frequency signal and a first oscillator signal <NUM>; a first oscillator <NUM> configured to generate the first oscillator signal <NUM> based on an output signal of the first phase comparator <NUM>; a first divider <NUM> configured to lower a frequency of the first oscillator signal <NUM> and transfer it (the first oscillator signal <NUM> with a lowered frequency) to the first phase comparator <NUM>; and/or a first loop filter <NUM> configured to remove noise included in the output signal of the first phase comparator <NUM>.

The PLL circuit <NUM> may also include : a second buffer <NUM> configured to amplify the clock frequency signal and transfer it to a second phase comparator <NUM>; the second phase comparator <NUM> configured to compare phases of the clock frequency signal and a second oscillator signal <NUM>; a second oscillator <NUM> configured to generate the second oscillator signal <NUM> based on an output signal of the second phase comparator <NUM>; a second divider <NUM> configured to lower a frequency of the second oscillator signal <NUM> and transfer it to the second phase comparator <NUM>; and/or a second loop filter <NUM> configured to remove noise included in the output signal of the second phase comparator <NUM>.

The transceiver <NUM> may also include an RF transmission signal generation circuit <NUM> configured to generate an RF transmission signal Tx based on the first oscillator signal <NUM> received from the PLL circuit <NUM> and a baseband transmission signal received from the communication processor <NUM>. The transceiver <NUM> may also include an RF reception signal processing circuit <NUM> configured to generate a baseband reception signal based on the second oscillator signal <NUM> received from the PLL circuit <NUM> and an RF reception signal Rx received from the outside.

The RF reception signal Rx received from the outside through the antenna <NUM> may be combined with the second oscillator signal <NUM> in a mixer <NUM>. The combined signal may be converted to the baseband reception signal, passing through a transimpedance amplifier (TIA) <NUM>, a low-pass filter (LPF)/variable gain amplifier (VGA) <NUM>, and a voltage analog-to-digital converter (ADC) <NUM>. The baseband reception signal may be transferred to the communication processor <NUM>. The baseband transmission signal and the baseband reception signal may each be complex signals that may include an I signal of an in-phase component and a Q signal of a quadrature component.

The communication processor <NUM> may transfer, to the transceiver <NUM>, the baseband transmission signal including data that is to be transmitted to the outside. The transmission signal generated by the communication processor <NUM> may be a digital signal. The baseband transmission signal input to the transceiver <NUM> may be converted to an analog signal through a voltage digital-to-analog converter (DAC) <NUM> of the RF transmission signal generation circuit <NUM> and be filtered to a signal of a set bandwidth through an LPF <NUM>. The filtered signal may be combined with the first oscillator signal <NUM> in a mixer <NUM>, after passing through a voltage-to-current (V2I) amplifier <NUM>. The RF transmission signal generated as combined in the mixer <NUM> may be a voltage signal. The RF transmission signal may be amplified by an RF signal amplifier <NUM> and then be output. The RF signal amplifier <NUM> may include, for example, a VGA and a drive amplifier (DA).

The RF transmission signal Tx may be generated by a baseband transmission signal being combined with the first oscillator signal <NUM>, and thus a frequency and phase of the RF transmission signal Tx may also become unstable when the frequency and phase of the first oscillator signal <NUM> are unstable. The wireless communication device <NUM> may first determine whether phases of oscillator signals output from the PLL circuit <NUM> are locked to stably transmit the RF transmission signal Tx, and then activate the RF transmission signal generation circuit <NUM> when the phases of the oscillator signals are locked.

The first phase comparator <NUM> in the PLL circuit <NUM> may compare the clock frequency signal and the first oscillator signal <NUM> and generate the first oscillator signal <NUM> indicating whether the phase of the first oscillator signal <NUM> is locked. The second phase comparator <NUM> in the PLL circuit <NUM> may compare the clock frequency signal and the second oscillator signal <NUM> and generate the second oscillator signal <NUM> indicating whether the phase of the second oscillator signal <NUM> is locked.

The transceiver <NUM> may also include a first decision circuit <NUM> configured to control activation of at least one component included in the RF transmission signal generation circuit <NUM> based on at least one of the first oscillator signal <NUM> or the second oscillator signal <NUM>. The first decision circuit <NUM> may receive a first phase comparison signal <NUM> from the first phase comparator <NUM>. The first decision circuit <NUM> may receive a second phase comparison signal <NUM> from the second phase comparator <NUM>. The first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM> for example when both the phase of the first oscillator signal <NUM> and the phase of the second oscillator signal <NUM> are locked, and may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when at least one of the phase of the first oscillator signal <NUM> or the phase of the second oscillator signal <NUM> is not locked, based on at least one of the first phase comparison signal <NUM> or the second phase comparison signal <NUM>. When for example only the first phase comparator <NUM>, configured to generate the first oscillator signal <NUM>, is implemented, then the first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is locked. Similarly for the case when only the second phase comparator <NUM> is implemented.

In a wireless communication operation, when transmitting an RF transmission signal using a communication network, the wireless communication device <NUM> may need to receive a signal for establishing a communication channel with a base station, and the phase of the second oscillator signal <NUM> supplied to the RF reception signal processing circuit <NUM> may need to be locked prior to the phase of the first oscillator signal <NUM> supplied to the RF transmission signal generation circuit <NUM> in order to receive the corresponding signal. In this case, an RF transmission signal that is generated without the phase of the second oscillator signal <NUM> being locked may be an unnecessary signal. For example, to stably generate an RF transmission signal, the wireless communication device <NUM> may control the activation of the RF transmission signal generation circuit <NUM> in consideration of both whether the phase of the second oscillator signal <NUM> is locked and whether the phase of the first oscillator signal <NUM> is locked.

<FIG> is a diagram illustrating components of an RF transmission signal generation circuit for which a first decision circuit controls activation and/or deactivation. One or more of such components may be the same as and/or may be implemented together with components illustrated in and/or described with references being made to <FIG>, <FIG>, <FIG>.

Referring to <FIG>, components of the RF transmission signal generation circuit <NUM> that may be controlled by the first decision circuit <NUM> are shown.

The first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM> based on, for example, a first phase comparison signal <NUM> and a second phase comparison signal <NUM>. The component controlled by the first decision circuit <NUM> may be, for example, an active component included in an RF transmission circuit. For example, the first decision circuit <NUM> may control activation of one or more of an amplifier, a voltage converter, and a mixer, e.g., based on the first phase comparison signal <NUM> and the second phase comparison signal <NUM>.

For example, the first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM> when a phase of a first oscillator signal <NUM> and a phase of a second oscillator signal <NUM> are both locked. According to another example, the first decision circuit <NUM> may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> and the phase of the second oscillator signal <NUM> are not locked. According to another example, the first decision circuit <NUM> may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when at least one of the phase of the first oscillator signal <NUM> and the phase of the second oscillator signal <NUM> is not locked.

When the at least one component included in the RF transmission signal generation circuit <NUM> is deactivated, an RF transmission signal may not be generated in the RF transmission signal generation circuit <NUM>. When at least one of the phases of the first oscillator signal <NUM> and the second oscillator signal <NUM> is not locked, the first decision circuit <NUM> may deactivate the RF transmission signal generation circuit <NUM>, thereby preventing the generation of an RF transmission signal of an abnormal frequency that may be generated by an oscillator signal of which a phase is not locked.

The first decision circuit <NUM> may control the at least one component of the RF transmission signal generation circuit <NUM> for example by controlling power to be supplied to the at least one component or controlling a bias voltage or bias current to be supplied to the at least one component.

<FIG> is a diagram illustrating an input and output of a first decision circuit. One or more of components illustrated in and/or described with reference to <FIG> may be the same as and/or may be implemented together with components illustrated in and/or described with references being made to <FIG>, <FIG>.

Referring to <FIG>, an example logic circuit of the first decision circuit <NUM> is shown.

As an example, one or more of power, ground (or GND), a first phase comparison signal <NUM>, and a second phase comparison signal <NUM> may be input to the first decision circuit <NUM>. For example, the logic circuit of the first decision circuit <NUM> may include a multiplexer <NUM> to which the power and the ground are input and an AND gate <NUM> to which the first phase comparison signal <NUM> and the second phase comparison signal <NUM> are input.

The first decision circuit <NUM> may output the input power or ground based on at least one of the first phase comparison signal <NUM> and the second phase comparison signal <NUM>. The output of the first decision circuit <NUM> may be connected to at least one component of the RF transmission signal generation circuit <NUM> to activate or deactivate the respective component.

The first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM> when a phase of a first oscillator signal <NUM> and a phase of a second oscillator signal <NUM> are locked, and may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when at least one of the phase of the first oscillator signal <NUM> or the phase of the second oscillator signal <NUM> is not locked.

For example, the first phase comparator <NUM> of the PLL circuit <NUM> may output the first phase comparison signal <NUM> of a first value when a phase difference between a clock frequency signal and the first oscillator signal <NUM> is maintained within a set range for a set time, and may output the first phase comparison signal <NUM> of a second value when the phase difference between the clock frequency signal and the first oscillator signal <NUM> is not maintained within the set range for the set time. A phase comparison signal of a certain value may mean that the phase comparison signal corresponds to the certain value, or can be measured and/or identified with the certain value. The second phase comparator <NUM> of the PLL circuit <NUM> may output the second phase comparison signal <NUM> of a first value when a phase difference between the clock frequency signal and the second oscillator signal <NUM> is maintained within a set range for a set time, and may output the second phase comparison signal <NUM> of a second value when the phase difference between the clock frequency signal and the second oscillator signal <NUM> is not maintained within the set range for the set time. Each of the set range and set time may be configured differently for each of the first and second phase comparator, respectively, or may be configured similarly or the same. Each may be pre-set, configurable, and/or pre-determined. The set range may refer to an interval or a set range of values for the phase difference. The set time may refer to a time interval with a pre-determined, pre-set, and/or configurable length. For convenience of description, the expressions "set range", "set time" etc. are used herein below.

A phase comparator (e.g., the first phase comparator <NUM> and/or the second phase comparator <NUM>) may include either an analog circuit or a digital circuit. For example, if the phase comparator includes the analog circuit, a phase difference between a clock frequency signal and an oscillator signal (e.g., the first oscillator signal <NUM> or the second oscillator signal <NUM>) may be represented as an analog voltage. In this case, when the analog voltage indicating the phase difference is maintained within a set voltage range for a set time, the phase comparator may determine that a phase of the oscillator signal is locked and can generate a phase comparison signal (e.g., the first phase comparison signal <NUM> or the second phase comparison signal <NUM>) of a first value. For another example, if the phase comparator is the digital circuit, the phase difference between the clock frequency signal and the oscillator signal (e.g., the first oscillator signal <NUM> or the second oscillator signal <NUM>) may be represented as a digital bit. In this case, when a value of the digital bit is maintained within a set value range for a set time, the phase comparator may determine that a phase of the oscillator signal is locked and generate a phase comparison signal of a first value.

For example, the first decision circuit <NUM> may output the input power when a value of the first phase comparison signal <NUM> is the first value and a value of the second phase comparison signal <NUM> is the first value, and may output the input ground when at least one of the value of the first phase comparison signal <NUM> or the value of the second phase comparison signal <NUM> is the second value.

<FIG> is a diagram illustrating a first decision circuit. One or more of components illustrated in and/or described with reference to <FIG> may be the same as and/or may be implemented together with components illustrated in and/or described with references being made to <FIG>, <FIG>.

In terms of circuit design, it may be difficult to include (or add) a wiring line that transfers a second phase comparison signal <NUM> to the first decision circuit <NUM> into a circuit of the transceiver <NUM> as shown in <FIG>. Referring to <FIG>, an example of the first decision circuit <NUM> configured to control activation of the RF transmission signal generation circuit <NUM> based on a first phase comparison signal <NUM> is shown.

The first phase comparator <NUM> in the PLL circuit <NUM> may compare a clock frequency signal and a first oscillator signal <NUM> to generate the first oscillator signal <NUM> indicating whether a phase of the first oscillator signal <NUM> is locked. The transceiver <NUM> may include the first decision circuit <NUM> configured to control activation of at least one component included in the RF transmission signal generation circuit <NUM> based on the first oscillator signal <NUM>. For example, the first decision circuit <NUM> may receive the first phase comparison signal <NUM> from the first phase comparator <NUM>. The first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is locked, and may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is not locked, based on the first phase comparison signal <NUM>. Substantially the same description of the first decision circuit <NUM> provided above with reference to <FIG> may apply to the description of components of the RF transmission signal generation circuit <NUM> to be controlled by the first decision circuit <NUM>.

Referring to <FIG>, an example logic circuit of a first decision circuit <NUM> (e.g., the first decision circuit <NUM> of <FIG> and <FIG>) is shown.

As an example, one or more of power, ground (or GND), and a first phase comparison signal <NUM> may be input to the first decision circuit <NUM>. For example, the logic circuit of the first decision circuit <NUM> may include a multiplexer <NUM> to which the power and the ground are input.

The first decision circuit <NUM> may output the input power or ground based on the first phase comparison signal <NUM>. The output of the first decision circuit <NUM> may be connected to at least one component of the RF transmission signal generation circuit <NUM> to activate or deactivate the respective component.

The first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM> when a phase of a first oscillator signal <NUM> is locked, and may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is not locked.

For example, the first phase comparator <NUM> of the PLL circuit <NUM> may output the first phase comparison signal <NUM> of a first value when a phase difference between a clock frequency signal and the first oscillator signal <NUM> is maintained within a set range for a set time, and may output the first phase comparison signal <NUM> of a second value when the phase difference between the clock frequency signal and the first oscillator signal <NUM> is not maintained within the set range for the set time.

For example, the first decision circuit <NUM> may output the input power when a value of the first phase comparison signal <NUM> is the first value, and may output the input ground when the value of the first phase comparison signal <NUM> is the second value.

<FIG> is a diagram illustrating a first decision circuit and a second decision circuit.

Referring to <FIG>, examples of the communication processor <NUM> and the transceiver <NUM> are shown in a block diagram. One or more of components illustrated in and/or described with reference to <FIG> may be the same as and/or may be implemented together with components illustrated in and/or described with references being made to <FIG>, <FIG>.

The transceiver <NUM> may include a first decision circuit <NUM> configured to control activation of an RF transmission signal generation circuit <NUM> based on a first phase comparison signal <NUM> received from a first phase comparator <NUM>, a second phase comparison signal <NUM> received from a second phase comparator <NUM>, and a signal received from a second decision circuit <NUM>.

The communication processor <NUM> may include at least one of a complex signal generator <NUM> configured to generate a complex signal, a first frequency shifter <NUM> configured to shift a frequency of the complex signal to generate a baseband transmission signal, a modulator <NUM> configured to modulate the complex signal, a second frequency shifter <NUM> configured to shift a frequency of a complex signal modulated by the modulator <NUM> to generate the baseband transmission signal, and/or the second decision circuit <NUM> configured to detect whether the first frequency shifter <NUM> operates and whether the second frequency shifter <NUM> operates, and transfer a detection result signal <NUM> to the first decision circuit <NUM>.

The communication processor <NUM> may generate the baseband transmission signal from the complex signal using any one of the first frequency shifter <NUM> and the second frequency shifter <NUM>. The communication processor <NUM> may select a frequency resource block to be used for RF signal transmission, using a frequency shifter (e.g., the first frequency shifter <NUM> and the second frequency shifter <NUM>). The communication processor <NUM> may use one of the first frequency shifter <NUM> and the second frequency shifter <NUM> according to a communication protocol used for transmission of an RF transmission signal. For example, when transmitting a physical random-access channel (PRACH) protocol signal, the communication processor <NUM> may generate the baseband transmission signal using a complex signal of a Zadoff-chu sequence and the first frequency shifter <NUM>. When transmitting data such as a physical uplink shared channel (PUSCH), the communication processor <NUM> may generate the baseband transmission signal using the modulator <NUM> and the second frequency shifter <NUM>.

As described above, one of the first frequency shifter <NUM> and the second frequency shifter <NUM> may be used as needed. However, when both the first frequency shifter <NUM> and the second frequency shifter <NUM> are used, a frequency of the baseband transmission signal may be changed to an unintended frequency.

For example, referring to <FIG>, an example case in which a baseband signal frequency is out of a normal range by the first frequency shifter <NUM> and the second frequency shifter <NUM> is shown.

For example, when the communication processor <NUM> generates a baseband transmission signal using the first frequency shifter <NUM>, the generated baseband transmission signal may be a first-frequency baseband transmission signal <NUM>. When both the first frequency shifter <NUM> and the second frequency shifter <NUM> operate to generate a baseband transmission signal, the generated baseband transmission signal may be a second-frequency baseband transmission signal <NUM>. In this example, a second frequency may be a frequency that is out of a normal frequency range <NUM> according to a circuit design of a wireless communication device, and a baseband transmission signal of this frequency may damage the RF front-end circuit <NUM> during signal processing.

The second decision circuit <NUM> may detect whether the first frequency shifter <NUM> and the second frequency shifter <NUM> operate or not, and may transfer a detection result signal <NUM> to the first decision circuit <NUM>. For example, the detection result signal <NUM> may be converted to a digital signal in a communication processor controller <NUM> that controls the operations performed by the communication processor <NUM>, and the digital signal may be transferred to a transceiver controller <NUM> through a digital interface <NUM> connecting the communication processor <NUM> and the transceiver <NUM>. The transferred signal may be transferred to the first decision circuit <NUM> through the transceiver controller <NUM> that controls the operations performed by the transceiver <NUM>. The detection result signal <NUM> may also be transferred to the first decision circuit <NUM> through a dedicated interface for transmitting the detection result signal <NUM> that is formed separately from the digital interface <NUM>.

The first decision circuit <NUM> may control activation of at least one component of the RF transmission signal generation circuit <NUM> based on the detection result signal <NUM> received from the second decision circuit <NUM>, the first phase comparison signal <NUM>, and the second phase comparison signal <NUM>. As the first decision circuit <NUM> controls the activation of at least one component of the RF transmission signal generation circuit <NUM>, further using a result of the detection of the second decision circuit <NUM>, in addition to the first phase comparison signal <NUM> and the second phase comparison signal <NUM>, it may prevent damage that may be caused by a baseband transmission signal out of a normal frequency range. Substantially the same description of the first decision circuit <NUM> provided above with reference to <FIG> may apply to the description of components of the RF transmission signal generation circuit <NUM> to be controlled by the first decision circuit <NUM>.

When any one of the first frequency shifter <NUM> and the second frequency shifter <NUM> operates and the phase of the first oscillator signal <NUM> and the phase of the second oscillator signal <NUM> are locked, based on the detection result signal <NUM>, the first phase comparison signal <NUM>, and the second phase comparison signal <NUM>, the first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM>. When the first frequency shifter <NUM> and the second frequency shifter <NUM> both operate, or at least one of the phase of the first oscillator signal <NUM> or the phase of the second oscillator signal <NUM> is not locked, based on the detection result signal <NUM>, the first phase comparison signal <NUM>, and the second phase comparison signal <NUM>, the first decision circuit <NUM> may deactivate at least one component included in the RF transmission signal generation circuit <NUM>.

<FIG> is a diagram illustrating an input and output of a first decision circuit. One or more of components illustrated in and/or described with reference to <FIG> may be the same as and/or may be implemented together with components illustrated in and/or described with references being made to <FIG>, <FIG>, <FIG>.

Referring to <FIG>, an example logic circuit of a first decision circuit is shown.

For example, power, ground (or GND), a first phase comparison signal <NUM>, a second phase comparison signal <NUM>, and a detection result signal <NUM> transferred from the second decision circuit <NUM> may be input to the first decision circuit <NUM>. For example, the logic circuit of the first decision circuit <NUM> may include a multiplexer <NUM> to which the power and the ground are input, a first AND gate <NUM> to which the first phase comparison signal <NUM> and the detection result signal <NUM> are input, and a second AND gate <NUM> to which the second phase comparison signal <NUM> and an output of the first AND gate <NUM> are input.

The first decision circuit <NUM> may output the input power or ground based on the detection result signal <NUM>, the first phase comparison signal <NUM>, and the second phase comparison signal <NUM>. The output of the first decision circuit <NUM> may be connected to at least one component of the RF transmission signal generation circuit <NUM> to activate or deactivate the respective component.

When any one of the first frequency shifter <NUM> and the second frequency shifter <NUM> operates, and a phase of a first oscillator signal <NUM> and a phase of a second oscillator signal <NUM> are locked, the first decision circuit <NUM> may activate at least one component included in the RF transmission signal generation circuit <NUM>. When the first frequency shifter <NUM> and the second frequency shifter <NUM> operate simultaneously, or at least one of the phase of the first oscillator signal <NUM> or the phase of the second oscillator signal <NUM> is not locked, the first decision circuit <NUM> may deactivate at least one component included in the RF transmission signal generation circuit <NUM>.

For example, the first phase comparator <NUM> of the PLL circuit <NUM> may output the first phase comparison signal <NUM> of a first value when a phase difference between a clock frequency signal and the first oscillator signal <NUM> is maintained within a set range for a set time, and may output the first phase comparison signal <NUM> of a second value when the phase difference between the clock frequency signal and the first oscillator signal <NUM> is maintained within the set range for the set time. The second phase comparator <NUM> of the PLL circuit <NUM> may output the second phase comparison signal <NUM> of a first value when a phase difference between the clock frequency signal and a second oscillator signal <NUM> is maintained within a set range for a set time, and may output the second phase comparison signal <NUM> of a second value when the phase difference between the clock frequency signal and the second oscillator signal <NUM> is not maintained within the set range for the set time. The second decision circuit <NUM> may output the detection result signal <NUM> of a first value when any one of the first frequency shifter <NUM> and the second frequency shifter <NUM> operates, and may output the detection result signal <NUM> of a second value when the first frequency shifter <NUM> and the second frequency shifter <NUM> operate.

For example, the first decision circuit <NUM> may output the input power when a value of the detection result signal <NUM> is the first value, a value of the first phase comparison signal <NUM> is the first value, and a value of the second phase comparison signal <NUM> is the first value, and may output the input ground when at least one of the value of the detection result signal <NUM>, the value of the first phase comparison signal <NUM>, or the value of the second phase comparison signal <NUM> is the second value.

<FIG> is a flowchart illustrating a method of controlling activation of an RF transmission signal generation circuit. One or more of components illustrated in and/or described with reference to <FIG> may be the same as and/or may be implemented together with components illustrated in and/or described with references being made to <FIG>, <FIG>.

Referring to <FIG>, in operation <NUM>, the first phase comparator <NUM> may generate a first phase comparison signal <NUM> indicating whether a phase of a first oscillator signal <NUM> is locked by comparing a phase of a clock frequency signal and the phase of the first oscillator signal <NUM> that is an output signal of the PLL circuit <NUM>.

For example, the first phase comparator <NUM> may generate the first oscillator signal <NUM> of a first value when a value of the first phase comparison signal <NUM> is maintained within a set range for a set time, and may generate the first oscillator signal <NUM> of a second value when the value of the first phase comparison signal <NUM> is not maintained within the set range for the set time.

An oscillator (e.g., the first oscillator <NUM> or the second oscillator <NUM>) of the PLL circuit <NUM> may generate an oscillator signal (e.g., the first oscillator signal <NUM> or the second oscillator signal <NUM>) based on an output signal of a phase comparator (e.g., the first phase comparator <NUM> or the second phase comparator <NUM>). A divider (e.g., the first divider <NUM> or the second divider <NUM>) of the PLL circuit <NUM> may lower a frequency of the oscillator signal (e.g., the first oscillator signal <NUM> or the second oscillator signal <NUM>) and may transfer it to the phase comparator (e.g., the first phase comparator <NUM> or the second phase comparator <NUM>). A loop filter (e.g., the first loop filter <NUM> or the second loop filter <NUM>) of the PLL circuit <NUM> may remove noise included in an output signal of the phase comparator (e.g., the first phase comparator <NUM>).

In operation <NUM>, the first phase comparator <NUM> may transfer the generated first phase comparison signal <NUM> to a first decision circuit (e.g., the first decision circuit <NUM>, the first decision circuit <NUM>, or the first decision circuit <NUM>).

In operation <NUM>, the first decision circuit (e.g., the first decision circuit <NUM>) may control activation of at least one component included in the RF transmission signal generation circuit <NUM>, based on whether the phase of the first oscillator signal <NUM> indicated in the first phase comparison signal <NUM> is locked.

For example, the first decision circuit (e.g., the first decision circuit <NUM>) may activate at least one component included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is locked, and may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is not locked. The at least one component of the RF transmission signal generation circuit <NUM> for which the activation may be controlled by the first decision circuit (e.g., the first decision circuit <NUM>) may be an active component. For example, the first decision circuit (e.g., the first decision circuit <NUM>) may activate at least one of an amplifier, a voltage converter, or a mixer included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is locked, and may deactivate at least one of the amplifier, the voltage converter, or the mixer included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is not locked.

The second phase comparator <NUM> in the PLL circuit <NUM> may generate a second phase comparison signal <NUM> indicating whether a phase of a second oscillator signal <NUM> is locked by comparing the phase of the clock frequency signal and the phase of the second oscillator signal <NUM> that is an output signal of the PLL circuit <NUM>, and may transfer the second phase comparison signal <NUM> to the first decision circuit (e.g., the first decision circuit <NUM>) of the transceiver <NUM>.

The first decision circuit (e.g., the first decision circuit <NUM>) may activate at least one component included in the RF transmission signal generation circuit <NUM> when the phase of the first oscillator signal <NUM> is locked and the phase of the second oscillator signal <NUM> indicated in the second phase comparison signal <NUM> is locked, and may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when at least one of the phase of the first oscillator signal <NUM> or the phase of the second oscillator signal <NUM> is not locked.

The second decision circuit <NUM> included in the communication processor <NUM> may detect whether the first frequency shifter <NUM>, which is configured to shift a frequency of a complex signal generated in the communication processor <NUM> to generate a baseband transmission signal, operates and detect whether the second frequency shifter <NUM>, which is configured to shift a frequency of a complex signal modulated in the communication processor <NUM> to generate the baseband transmission signal, operates. The second decision circuit <NUM> may transfer, to the first decision circuit (e.g., the first decision circuit <NUM>), a detection result signal indicating a result of detecting whether the first frequency shifter <NUM> and/or the second frequency shifter <NUM> operate. The detection result signal may be transferred through a digital interface between the communication processor <NUM> and the transceiver <NUM>.

The first decision circuit (e.g., the first decision circuit <NUM>) may activate at least one component included in the RF transmission signal generation circuit <NUM> when any one of the first frequency shifter <NUM> and the second frequency shifter <NUM> is detected to operate, and the phase of the first oscillator signal <NUM> and the phase of the second oscillator signal <NUM> are locked, based on the detection result signal, the first phase comparison signal <NUM>, and the second phase comparison signal <NUM>. The first decision circuit (e.g., the first decision circuit <NUM>) may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when the first frequency shifter <NUM> and the second frequency shifter <NUM> operate, or the phase of the first oscillator signal <NUM> is not locked or the phase of the second oscillator signal <NUM> is not locked, based on the detection result signal, the first phase comparison signal <NUM>, and the second phase comparison signal <NUM>.

The first decision circuit (e.g., the first decision circuit <NUM>) may control the activation of the at least one component by controlling power to be supplied to the at least one component of the RF transmission signal generation circuit <NUM> or controlling a bias voltage or bias current of the at least one component.

In operation <NUM>, when the at least one component of the RF transmission signal generation circuit <NUM> is activated in operation <NUM>, the RF transmission signal generation circuit <NUM> may generate an RF transmission signal from the first oscillator signal <NUM> and the baseband transmission signal generated by the communication processor <NUM> of the wireless communication device <NUM>. In operation <NUM>, the RF transmission signal generation circuit <NUM> may output the generated RF transmission signal.

A wireless communication device <NUM> may include a communication processor <NUM> and a transceiver <NUM> controlled by the communication processor <NUM> to perform wireless communication. The transceiver <NUM> may include at least one of: a PLL circuit <NUM> configured to generate a first oscillator signal <NUM> based on a clock frequency signal; an RF transmission signal generation circuit <NUM> configured to generate an RF transmission signal based on the first oscillator signal <NUM> received from the PLL circuit <NUM> and a baseband transmission signal received from the communication processor <NUM>; and a first decision circuit (e.g., a first decision circuit <NUM>) configured to receive a first phase comparison signal <NUM> indicating whether a phase of the first oscillator signal <NUM> is locked from a first phase comparator <NUM> in the PLL circuit <NUM>, and control activation of at least one component included in the RF transmission signal generation circuit <NUM> based on the first phase comparison signal <NUM>.

The first phase comparator <NUM> may compare a phase of the clock frequency signal and the phase of the first oscillator signal <NUM> which is an output signal of the PLL circuit <NUM> to generate the first phase comparison signal <NUM> indicating whether the phase of the first oscillator signal <NUM> is locked.

For example, the first phase comparator <NUM> may generate the first oscillator signal <NUM> of a first value when a value of the first phase comparison signal <NUM> is maintained within a set range for a set time, and may generate the generate the first oscillator signal <NUM> of a second value when the value of the first phase comparison signal <NUM> is not maintained within the set range for the set time.

An oscillator (e.g., a first oscillator <NUM> or a second oscillator <NUM>) of the PLL circuit <NUM> may generate an oscillator signal (e.g., the first oscillator signal <NUM> or a second oscillator signal <NUM>) based on an output signal of a phase comparator (e.g., the first phase comparator <NUM> or the second phase comparator <NUM>). A divider (e.g., a first divider <NUM> or a second divider <NUM>) of the PLL circuit <NUM> may lower a frequency of the oscillator signal (e.g., the first oscillator signal <NUM> or the second oscillator signal <NUM>) and transfer it to the phase comparator (e.g., the first phase comparator <NUM> or the second phase comparator <NUM>). A loop filter (e.g., a first loop filter <NUM> or a second loop filter <NUM>) of the PLL circuit <NUM> may remove noise included in an output signal of the phase comparator (e.g., the first phase comparator <NUM>).

The first phase comparator <NUM> may transfer the generated first phase comparison signal <NUM> to the first decision circuit (e.g., the first decision circuit <NUM>, a first decision circuit <NUM>, or a first decision circuit <NUM>).

The first decision circuit (e.g., the first decision circuit <NUM>) may control activation of at least one component included in the RF transmission signal generation circuit <NUM> based on whether the phase of the first oscillator signal <NUM> indicated in the first phase comparison signal <NUM> is locked.

A second phase comparator <NUM> in the PLL circuit <NUM> may compare the phase of the clock frequency signal and a phase of a second oscillator signal <NUM> which is an output signal of the PLL circuit <NUM> to generate a second phase comparison signal <NUM> indicating whether the phase of the second oscillator signal <NUM> is locked, and may transfer the second phase comparison signal <NUM> to the first decision circuit (e.g., the first decision circuit <NUM>) of the transceiver <NUM>.

A second decision circuit <NUM> included in the communication processor <NUM> may detect whether a first frequency shifter <NUM>, which is configured to shift a frequency of a complex signal generated in the communication processor <NUM> to generate a baseband transmission signal, operates, and may detect whether a second frequency shifter <NUM>, which is configured to shift a frequency of a complex signal modulated in the communication processor <NUM> to generate the baseband transmission signal, operates. The second decision circuit <NUM> may transfer a detection result signal indicating a result of detecting whether the first frequency shifter <NUM> and the second frequency shifter <NUM> operate to the first decision circuit (e.g., the first decision circuit <NUM>). The detection result signal may be transferred through a digital interface between the communication processor <NUM> and the transceiver <NUM>.

The first decision circuit (e.g., the first decision circuit <NUM>) may activate at least one component included in the RF transmission signal generation circuit <NUM> when any one of the first frequency shifter <NUM> and the second frequency shifter <NUM> is detected to operate, and the phase of the first oscillator signal <NUM> and the phase of the second oscillator signal <NUM> are locked, based on the detection result signal, the first phase comparison signal <NUM>, and the second phase comparison signal <NUM>. The first decision circuit (e.g., the first decision circuit <NUM>) may deactivate at least one component included in the RF transmission signal generation circuit <NUM> when the first frequency shifter <NUM> and the second frequency shifter <NUM> operate, the phase of the first oscillator signal <NUM> is not locked, or the phase of the second oscillator signal <NUM> is not locked, based on the detection result signal, the first phase comparison signal <NUM>, and the second phase comparison signal <NUM>.

The first decision circuit (e.g., the first decision circuit <NUM>) may control the activation of the at least one component of the RF transmission signal generation circuit <NUM> by controlling power to be supplied to the at least one component or controlling a bias voltage or bias current of the at least one component.

When the at least one component of the RF transmission signal generation circuit <NUM> is activated, the RF transmission signal generation circuit <NUM> may generate an RF transmission signal from the first oscillator signal <NUM> and the baseband transmission signal generated by the communication processor <NUM> of the wireless communication device <NUM>. The RF transmission signal generation circuit <NUM> may then output the generated RF transmission signal in operation <NUM>.

<FIG> is a block diagram illustrating an example electronic device including a wireless communication device. One or more of components illustrated in and/or described with reference to <FIG> may be the same as and/or may be the same as or may be implemented together with components illustrated in and/or described with references being made to <FIG>.

Referring to <FIG>, an electronic device <NUM> in a network environment <NUM> may communicate with an electronic device <NUM> via a first network <NUM> (e.g., a short-range wireless communication network), or communicate with at least one of an electronic device <NUM> and a server <NUM> via a second network <NUM> (e.g., a long-range wireless communication network). According to an embodiment, the electronic device <NUM> may include a processor <NUM>, a memory <NUM>, an input module <NUM>, a sound output module <NUM>, a display module <NUM>, an audio module <NUM>, and a sensor module <NUM>, an interface <NUM>, a connecting terminal <NUM>, a haptic module <NUM>, a camera module <NUM>, a power management module <NUM>, a battery <NUM>, a communication module <NUM>, a subscriber identification module (SIM) <NUM>, or an antenna module <NUM>. In various embodiments, at least one (e.g., the connecting terminal <NUM>) of the above components may be omitted from the electronic device <NUM>, or one or more other components may be added to the electronic device <NUM>. In various embodiments, some (e.g., the sensor module <NUM>, the camera module <NUM>, or the antenna module <NUM>) of the components may be integrated as a single component (e.g., the display module <NUM>).

The processor <NUM> may execute, for example, software (e.g., a program <NUM>) to control at least one other component (e.g., a hardware or software component) of the electronic device <NUM> connected to the processor <NUM> and may perform various data processing or computations. According to an embodiment, as at least a part of data processing or computations, the processor <NUM> may store a command or data received from another component (e.g., the sensor module <NUM> or the communication module <NUM>) in a volatile memory <NUM>, process the command or data stored in the volatile memory <NUM>, and store resulting data in a non-volatile memory <NUM>. According to an embodiment, the processor <NUM> may include a main processor <NUM> (e.g., a central processing unit (CPU) or an application processor (AP)) or an auxiliary processor <NUM> (e.g., a graphics processing unit (GPU), a neural processing unit (NPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operable independently from or in conjunction with, the main processor <NUM>. For example, when the electronic device <NUM> includes the main processor <NUM> and the auxiliary processor <NUM>, the auxiliary processor <NUM> may be adapted to consume less power than the main processor <NUM> or to be specific to a specified function. The auxiliary processor <NUM> may be implemented separately from the main processor <NUM> or as a part of the main processor <NUM>.

The auxiliary processor <NUM> may control at least some of functions or states related to at least one (e.g., the display device <NUM>, the sensor module <NUM>, or the communication module <NUM>) of the components of the electronic device <NUM>, instead of the main processor <NUM> while the main processor <NUM> is in an inactive (e.g., sleep) state or along with the main processor <NUM> while the main processor <NUM> is an active state (e.g., executing an application). According to an embodiment, the auxiliary processor <NUM> (e.g., an ISP or a CP) may be implemented as a portion of another component (e.g., the camera module <NUM> or the communication module <NUM>) that is functionally related to the auxiliary processor <NUM>. According to an embodiment, the auxiliary processor <NUM> (e.g., an NPU) may include a hardware structure specifically for artificial intelligence (AI) model processing. An AI model may be generated by machine learning. The machine learning may be performed by, for example, the electronic device <NUM>, in which the AI model is performed, or performed via a separate server (e.g., the server <NUM>). Learning algorithms may include, but are not limited to, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning. The AI model may include a plurality of artificial neural network layers. An artificial neural network may include, for example, a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), and a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more thereof, but is not limited thereto. The AI model may alternatively or additionally include a software structure other than the hardware structure.

The memory <NUM> may store various pieces of data used by at least one component (e.g., the processor <NUM> or the sensor module <NUM>) of the electronic device <NUM>. The various pieces of data may include, for example, software (e.g., the program <NUM>) and input data or output data for a command related thereto. The non-volatile memory <NUM> may include an internal memory <NUM> and/or an external memory <NUM>.

The program <NUM> may be stored as software in the memory <NUM> and may include, for example, an operating system (OS) <NUM>, middleware <NUM>, or an application <NUM>.

The input module <NUM> may receive, from outside (e.g., a user) the electronic device <NUM>, a command or data to be used by another component (e.g., the processor <NUM>) of the electronic device <NUM>.

The sound output module <NUM> may output a sound signal to the outside of the electronic device <NUM>. The speaker may be used for general purposes, such as playing multimedia or playing a recording. The receiver may be used to receive an incoming call. According to an embodiment, the receiver may be implemented separately from the speaker or as a part of the speaker.

The display module <NUM> may include, for example, a display, a hologram device, or a projector, and a control circuitry for controlling a corresponding one of the display, the hologram device, and the projector. According to an embodiment, the display module <NUM> may include a touch sensor adapted to sense a touch, or a pressure sensor adapted to measure an intensity of a force of the touch.

The audio module <NUM> may convert sound into an electric signal or vice versa. According to an embodiment, the audio module <NUM> may obtain the sound via the input module <NUM> or output the sound via the sound output module <NUM> or an external electronic device (e.g., the electronic device <NUM>, such as a speaker or headphones) directly or wirelessly connected to the electronic device <NUM>.

The sensor module <NUM> may detect an operational state (e.g., power or temperature) of the electronic device <NUM> or an environmental state (e.g., a state of a user) external to the electronic device <NUM> and generate an electric signal or data value corresponding to the detected state. According to an embodiment, the sensor module <NUM> may include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, an illuminance sensor, or a fingerprint sensor.

The interface <NUM> may support one or more specified protocols to be used by the electronic device <NUM> to couple with an external electronic device (e.g., the electronic device <NUM>) directly (e.g., by wire) or wirelessly. According to an embodiment, the interface <NUM> may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

The connecting terminal <NUM> may include a connector via which the electronic device <NUM> may physically connect to an external electronic device (e.g., the electronic device <NUM>). According to an embodiment, the connecting terminal <NUM> may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphones connector).

The haptic module <NUM> may convert an electric signal into a mechanical stimulus (e.g., a vibration or a movement) or an electrical stimulus, which may be recognized by a user via their tactile sensation or kinesthetic sensation.

The camera module <NUM> may capture a still image and moving images. According to an embodiment, the camera module <NUM> may include one or more lenses, image sensors, ISPs, and flashes.

According to an embodiment, the power management module <NUM> may be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

According to an embodiment, the battery <NUM> may include, for example, a primary cell, which is not rechargeable, a secondary cell, which is rechargeable, or a fuel cell.

The communication module <NUM> may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device <NUM> and an external electronic device (e.g., the electronic device <NUM>, the electronic device <NUM>, or the server <NUM>) and performing communication via the established communication channel. The communication module <NUM> may include one or more CPs that are operable independently from the processor <NUM> (e.g., an AP) and that support direct (e.g., wired) communication or wireless communication. A corresponding one of these communication modules may communicate with the external electronic device, for example, the electronic device <NUM>, via the first network <NUM> (e.g., a short-range communication network, such as Bluetooth™, wireless-fidelity (Wi-Fi) direct, or infrared data association (IrDA)) or the second network <NUM> (e.g., a long-range communication network, such as a legacy cellular network, a <NUM> network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single chip), or may be implemented as multiple components (e.g., multiple chips) separate from each other. The wireless communication module <NUM> may identify and authenticate the electronic device <NUM> in a communication network, such as the first network <NUM> or the second network <NUM>, using subscriber information (e.g., international mobile subscriber identity (IMSI)) stored in the SIM <NUM>.

The wireless communication module <NUM> may support a <NUM> network after a <NUM> network and next-generation communication technology (e.g., new radio (NR) access technology). The wireless communication module <NUM> may support a high-frequency band (e.g., a mmWave band) to achieve, e.g., a high data transmission rate. The wireless communication module <NUM> may support various technologies for securing performance on a high-frequency band, such as, e.g., beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), an antenna array, analog beamforming, or a large-scale antenna. According to an embodiment, the wireless communication module <NUM> may support a peak data rate (e.g., <NUM> Gbps or more) for implementing eMBB, loss coverage (e.g., <NUM> dB or less) for implementing mMTC, or U-plane latency (e.g., <NUM> or less for each of downlink (DL) and uplink (UL), or a round trip of <NUM> or less) for implementing URLLC.

The antenna module <NUM> may transmit or receive a signal or power to or from the outside (e.g., an external electronic device) of the electronic device <NUM>. According to an embodiment, the antenna module <NUM> may include an antenna including a radiating element including a conductive material or a conductive pattern formed in or on a substrate (e.g., a printed circuit board (PCB)). According to an embodiment, the antenna module <NUM> may include a plurality of antennas (e.g., an antenna array). In such a case, at least one antenna appropriate for a communication scheme used in a communication network, such as the first network <NUM> or the second network <NUM>, may be selected by, for example, the communication module <NUM> from the plurality of antennas. The signal or power may be transmitted or received between the communication module <NUM> and the external electronic device via the at least one selected antenna. According to an embodiment, another component (e.g., a radio frequency integrated circuit (RFIC)) other than the radiating element may be additionally formed as a part of the antenna module <NUM>.

According to an embodiment, the mmWave antenna module may include a PCB, an RFIC on a first surface (e.g., a bottom surface) of the PCB, or adjacent to the first surface of the PCB and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an antenna array) disposed on a second surface (e.g., a top or a side surface) of the PCB, or adjacent to the second surface of the PCB and capable of transmitting or receiving signals in the designated high-frequency band.

At least some of the above-described components may be coupled mutually and exchange signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme (e.g., a bus, general-purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)).

According to an embodiment, commands or data may be transmitted or received between the electronic device <NUM> and the external electronic device (e.g., the electronic device <NUM>) via the server <NUM> coupled with the second network <NUM>. Each of the external electronic devices (e.g., the electronic device <NUM> and <NUM>) may be a device of the same type as or a different type from the electronic device <NUM>. According to an embodiment, all or some of operations to be executed by the electronic device <NUM> may be executed by one or more of the external electronic devices (e.g., the electronic devices <NUM> and <NUM>, and the server <NUM>). For example, if the electronic device <NUM> needs to perform a function or a service automatically, or in response to a request from a user or another device, the electronic device <NUM>, instead of, or in addition to, executing the function or the service, may request one or more external electronic devices to perform at least a part of the function or service. The one or more external electronic devices receiving the request may perform the at least part of the function or service requested, or an additional function or an additional service related to the request, and may transfer a result of the performance to the electronic device <NUM>. The electronic device <NUM> may provide the result, with or without further processing of the result, as at least a part of a response to the request. To that end, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device <NUM> may provide ultra-low latency services using, e.g., distributed computing or MEC. In an embodiment, the external electronic device (e.g., the electronic device <NUM>) may include an Internet-of-things (IoT) device. According to an embodiment, the external electronic device (e.g., the electronic device <NUM>) or the server <NUM> may be included in the second network <NUM>. The electronic device <NUM> may be applied to intelligent services (e.g., a smart home, a smart city, a smart car, or healthcare) based on <NUM> communication technology or IoT-related technology.

According to various embodiments described herein, an electronic device may be a device of one of various types. The electronic device may include, as non-limiting examples, a portable communication device (e.g., a smartphone, etc.), a computing device, a portable multimedia device, a portable medical device, a camera, a wearable device, a home appliance, or the like. However, the electronic device is not limited to the examples described above.

It should be appreciated that various embodiments of the present disclosure and the terms used therein are not intended to limit the technological features set forth herein to particular embodiments. The scope of protection is defined in the appended claims. In connection with the description of the drawings, like reference numerals may be used for similar or related components. It is to be understood that a singular form of a noun corresponding to an item may include one or more of the things unless the relevant context clearly indicates otherwise. As used herein, "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "A, B, or C," each of which may include any one of the items listed together in the corresponding one of the phrases, or all possible combinations thereof. Terms such as "first," "second," or "initial" or "next" or "subsequent" may simply be used to distinguish the component from other components in question, and do not limit the components in other aspects (e.g., importance or order). It is to be understood that if an element (e.g., a first element) is referred to, with or without the term "operatively" or "communicatively," as "coupled with," "coupled to," "connected with," or "connected to" another element (e.g., a second element), the element may be coupled with the other element directly (e.g., by wire), wirelessly, or via a third element.

As used in connection with various embodiments of the disclosure, the term "module" may include a unit implemented in hardware, software, or firmware, or any combination thereof, and may interchangeably be used with other terms, for example, "logic," "logic block," "part," or "circuitry. " A module may be a single integral component, or a minimum unit or part thereof, adapted to perform one or more functions. For example, according to an embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

Various embodiments set forth herein may be implemented as software (e.g., the program <NUM>) including one or more instructions that are stored in a storage medium (e.g., the internal memory <NUM> or the external memory <NUM>) that is readable by a machine (e.g., the electronic device <NUM>). For example, a processor (e.g., the processor <NUM>) of the machine (e.g., the electronic device <NUM>) may invoke at least one of the one or more instructions stored in the storage medium and execute it. The one or more instructions may include code generated by a compiler or code executable by an interpreter. Here, the "non-transitory" storage medium is a tangible device, and may not include a signal (e.g., an electromagnetic wave), but this term does not differentiate between where data is semi-permanently stored in the storage medium and where the data is temporarily stored in the storage medium.

According to various embodiments, a method according to an embodiment of the disclosure may be included and provided in a computer program product. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)), or be distributed (e.g., downloaded or uploaded) online via an application store (e.g., PlayStore™) or between two user devices (e.g., smart phones) directly. If distributed online, at least part of the computer program product may be temporarily generated or at least temporarily stored in the machine-readable storage medium, such as a memory of the manufacturer's server, a server of the application store, or a relay server.

Claim 1:
A wireless communication device (<NUM>), comprising:
a communication processor (<NUM>); and
a transceiver (<NUM>) configured to be controlled by the communication processor (<NUM>) to perform wireless communication,
wherein the transceiver (<NUM>) comprises:
a phase locked loop, PLL, circuit (<NUM>) configured to generate a first oscillator signal (<NUM>) based on a clock frequency signal;
a radio frequency, RF, transmission signal generation circuit (<NUM>) configured to generate an RF transmission signal (Tx) based on the first oscillator signal received from the PLL circuit and a baseband transmission signal received from the communication processor; and
a first decision circuit (<NUM>) configured to receive, from a first phase comparator (<NUM>) comprised in the PLL circuit (<NUM>), a first phase comparison signal (<NUM>) indicating whether a phase of the first oscillator signal (<NUM>) is locked, and control activation of at least one component comprised in the RF transmission signal generation circuit (<NUM>) based on the first phase comparison signal (<NUM>).