Patent Description:
Semiconductor devices having a super junction (SJ) structure have been developed that include drift regions of n-type and column regions of p-type alternately arranged to regularly provide p-n junctions so as to achieve a high breakdown voltage and a low ON resistance (refer to Patent Literature <NUM>). Such a semiconductor device is provided with the SJ structure between main electrodes via semiconductor regions (referred to below as "electrode-connection regions") electrically connected to the main electrodes. Upon reverse bias, the drift region is depleted due to a depletion layer extending from the p-n junction at a boundary between the drift region and the column region, while a concentration of n-type impurities in the drift region through which main current flows is increased so as to reduce an ON resistance. This can ensure a high breakdown voltage of the semiconductor device.

<CIT> describes a field effect transistor and a semiconductor device that are provided, which enable a drain breakdown voltage in an off state and a drain breakdown voltage in an on state to be improved respectively. There are provided therein a field oxide film disposed on an N-type drift region positioned between a channel region of a silicon substrate and an N-type drain, an N-type drift layer disposed beneath the drift region of the silicon substrate and the drain, and an embedded layerhigher in P-type impurity concentration than the silicon substrate. The embedded layer is disposed beneath the drift layer except for below at least a portion of the drain in the silicon substrate.

<CIT> discloses as a semiconductor device a lateral MISFET with a column region on top of a drift region and with a drain region as a second electrode-connection region, which is laterally spaced from the column region. The semiconductor device may also be realised as a diode.

The SJ structure described above has a uniform electric field at the boundary between the respective drift regions and the column regions. The conventional semiconductor devices, however, cause a reduction in the breakdown voltage during the reverse bias because the electric field concentrates at the edge of the respective p-type column regions opposed to the n-type electrode-connection regions having a high impurity concentration.

In view of the foregoing problem, the present invention provides a semiconductor device having a super junction structure capable of avoiding a reduction in breakdown voltage, and a method of manufacturing the semiconductor device.

The dependent claims contain advantageous embodiments of the present invention.

The present invention can provide a semiconductor device having a super junction structure capable of avoiding a reduction in breakdown voltage, and a method of manufacturing the semiconductor device.

Hereinafter, embodiments of the present invention and examples not falling under the scope of the present invention are described with reference to the drawings. The same elements illustrated in the drawings are denoted by the same reference numerals, and overlapping explanations are not repeated below. The drawings are illustrated schematically, and relationships between thicknesses and planar dimensions, and proportions of the thicknesses of the respective layers are not drawn to scale. It should also be understood that the relationships or proportions of the dimensions between the respective drawings can differ from each other.

A semiconductor device according to a first embodiment of the present invention includes a substrate <NUM>, a semiconductor base body <NUM> deposited on a main surface of the substrate <NUM>, and a second main electrode <NUM> and a first main electrode <NUM> arranged separately from each other over the main surface of the substrate <NUM> via the semiconductor base body <NUM>, as illustrated in <FIG>. The second main electrode <NUM> and the first main electrode <NUM> serve as both ends of a current passage of a main current flowing through the semiconductor device in the ON state. An insulation film <NUM> is deposited on the top surface of the semiconductor base body <NUM>. <FIG> illustrates the configuration of the semiconductor device with the insulation film <NUM> in a transparent state for brevity. <FIG> illustrates only the outer frame of the insulation film <NUM> (the same in the following illustrations).

The semiconductor substrate <NUM> includes a drift region <NUM> of a first conductivity type through which the main current flows, and a column region <NUM> of a second conductivity type arranged adjacent to the drift region <NUM> in parallel to the current passage of the main current. The drift region <NUM> and the column region <NUM> implement a super junction (SJ) structure. One end of the drift region <NUM> is connected to a first electrode-connection region <NUM> of the second conductivity type electrically connected to the first main electrode <NUM>. The other end of the drift region <NUM> is connected to a second electrode-connection region <NUM> of the first conductivity type electrically connected to the second main electrode <NUM>. The semiconductor device illustrated in <FIG> has a configuration in which the drift region <NUM> and the column region <NUM> are stacked together in the thickness direction of the semiconductor base body <NUM>.

The semiconductor base body <NUM> further includes a low-density electric-field relaxation region <NUM> of the first conductivity type having a lower impurity concentration than the drift region <NUM> and deposited between the column region <NUM> and the second electrode-connection region <NUM>. The semiconductor device illustrated in <FIG> has a configuration in which the low-density electric-field relaxation region <NUM> is continuously arranged next to the column region <NUM> on a main surface of the drift region <NUM>. One end of the column region <NUM> is connected to the first electrode connection region <NUM>, and the other end is connected to the low-density electric-field relaxation region <NUM>.

The first conductivity type is a reverse conductivity type of the second conductivity type. When the first conductivity type is n-type, the second conductivity type is p-type. When the first conductivity type is p-type, the second conductivity type is n-type. The present embodiment is illustrated with the case in which the first conductivity type is n-type, and the second conductivity type is p-type.

The semiconductor device illustrated in <FIG> is a diode in which the first main electrode <NUM> serves as an anode, and the second main electrode <NUM> serves as a cathode.

The semiconductor device illustrated in <FIG> has the SJ structure between the first electrode-connection region <NUM> and the second electrode-connection region <NUM>. The SJ structure causes the drift region <NUM> and the column region <NUM> to be depleted due to a depletion layer extending from the p-n junction at the boundary between the drift region <NUM> and the column region <NUM> upon reverse-direction voltage application (upon reverse bias), so as to achieve a high breakdown voltage of the semiconductor device.

In the semiconductor device as illustrated in <FIG>, an edge of a main surface of the column region <NUM> (referred to below as an "opposed main surface) opposed to another main surface in contact with the drift region <NUM> is connected to the low-density electric-field relaxation region <NUM> arranged between the column region <NUM> and the second electrode-connection region <NUM>. A depletion layer also extends from the edge of the column region <NUM> toward the second electrode-connection region <NUM> at a low voltage. This relaxes a concentration of an electric field at the edge of the column region <NUM> on the second main electrode side. The semiconductor device thus can increase a maximum application voltage.

The main operations of the semiconductor device illustrated in <FIG> are described below.

A low voltage (a forward-direction voltage) is applied to the second main electrode <NUM> during the ON operation on the basis of the first main electrode <NUM> as a reference potential. The voltage application lowers an energy barrier between the drift region <NUM> and the first electrode-connection region <NUM>. This allows electrons to flow from the drift region <NUM> to the first electrode-connection region <NUM> to cause the forward-direction current to flow between the first main electrode <NUM> and the second main electrode <NUM>.

A high voltage (a reverse-direction voltage) is applied to the second main electrode <NUM> during the OFF operation on the basis of the first main electrode <NUM> as a reference potential, so as to increase the energy barrier between the drift region <NUM> and the first electrode-connection region <NUM>. This stops the flow of the electrons from the drift region <NUM> to the first electrode-connection region <NUM>. The depletion layer then spreads from the interface between the drift region <NUM> and the column region <NUM>, and the drift region <NUM> and the column region <NUM> are led to a completely-depleted state (a pinch-off state) when the reverse-direction voltage is increased to some extent.

To completely deplete the SJ structure in the OFF state to achieve a high breakdown voltage, a ratio of the total amount of n-type impurities in an n-type semiconductor region and the total amount of p-type impurities in a p-type semiconductor region needs to approximate to one. A concentration Nd of n-type impurities in the drift region <NUM>, a concentration Na of p-type impurities in the column region <NUM>, a width Wn of the drift region <NUM>, and a width Wp of the column region <NUM> are then set to fulfill the following formula (<NUM>): <MAT> where the width Wn and the width Wp are each defined in a direction in which the drift region <NUM> and the column region <NUM> are arranged adjacent to each other.

Setting the respective impurity concentrations of the drift region <NUM> and the column region <NUM> to fulfill the formula (<NUM>) causes the drift region <NUM> and the column region <NUM> to be depleted due to the depletion layer extending from the p-n junction to achieve a high breakdown voltage. The increase in the concentration of the n-type impurities in the drift region <NUM> can decrease a resistance value of the drift region <NUM>.

Ideally, the drift region <NUM> and the column region <NUM> are caused to be in the pinch-off state to lead an electric field distribution in each of the drift region <NUM> and the column region <NUM> to have a uniform rectangular shape so as to greatly decrease a maximum electric field. As a result, the breakdown voltage of the semiconductor device is improved. If the low-density electric-field relaxation region <NUM> would not be provided between the column region <NUM> and the second electrode-connection region <NUM>, the electric field is concentrated at the edge on the second main electrode side of the column region <NUM> opposed to the second electrode-connection region <NUM> having a high impurity concentration.

The semiconductor device illustrated in <FIG>, which includes the low-density electric-field relaxation region <NUM> arranged between the column region <NUM> and the second electrode-connection region <NUM>, can relax the concentration of the electric field at the edge of the column region <NUM> on the second main electrode side. The effects of relaxing the concentration of the electric field due to the low-density electric-field relaxation region <NUM> are described in detail below with reference to calculation models as illustrated in <FIG>.

The calculation model illustrated in <FIG> is a model of a comparative example (a comparative example model) without the low-density electric-field relaxation region <NUM> provided between the column region <NUM> and the second electrode-connection region <NUM>. The comparative example model has a structure in which part of the drift region <NUM> is located between the column region <NUM> and the second electrode-connection region <NUM>. This comparative example model is a calculation model equivalent to a configuration in which the n-type semiconductor region having substantially the same impurity concentration as the drift region <NUM> is provided between the column region <NUM> and the second electrode-connection region <NUM>.

The calculation model illustrated in <FIG> is a model according to the first embodiment (a first embodiment model) provided with the low-density electric-field relaxation region <NUM> between the column region <NUM> and the second electrode-connection region <NUM>, as in the case of the semiconductor device illustrated in <FIG>. A width W1 of the drift region <NUM> in a direction perpendicular to the flowing direction of the main current (referred to below as a "width direction") is set to <NUM> at a plane level equal to the interface between the column region <NUM> and the low-density electric-field relaxation region <NUM>. A width W2 of each of the column region <NUM> and the low-density electric-field relaxation region <NUM> is set to <NUM>. The calculation model is configured such that the column region <NUM> and the drift region <NUM> each have an impurity concentration set to 8E16/cm<NUM> and the low-density electric-field relaxation region <NUM> has an impurity concentration set to 4E16/cm<NUM>.

<FIG> illustrates results of calculating electric field intensity of the comparative example model illustrated in <FIG> and the first embodiment model illustrated in <FIG> upon the reverse bias. <FIG> indicates the electric field of the comparative example model by property E0, and the electric field of the first embodiment model by property E1.

As shown in <FIG>, the electric field intensity is highest at a position (Y = <NUM>) on the opposed main surface of the column region <NUM>. The electric field intensity gradually decreases in the width direction Y between the region with the width W2 in which the column region <NUM> and the low-density electric-field relaxation region <NUM> is in contact with each other and the region with the width W1 in the drift region <NUM>. The first embodiment model, which is provided with the low-density electric-field relaxation region <NUM> adjacent to a position at which the electric field intensity is highest, has a decreased peak value of the electric field intensity.

As described above, the semiconductor device according to the first embodiment of the present invention includes the low-density electric-field relaxation region <NUM> between the column region <NUM> and the second electrode-connection region <NUM>, so as to relax the concentration of the electric field at the edge of the second column region <NUM> opposed to the second electrode-connection region <NUM>. This configuration can void a decrease in the breakdown voltage of the semiconductor device having the SJ structure. The low-density electric-field relaxation region <NUM> may also be located between the drift region <NUM> and the second electrode-connection region <NUM> such that part of the low-density electric-field relaxation region <NUM> extends toward the substrate. This arrangement can lead the electric field to spread in the low-density electric-field relaxation region <NUM> toward the substrate, so as to further relax the concentration of the electric field at the edge of the column region <NUM>.

The semiconductor device illustrated in <FIG> includes the first main electrode <NUM> and the second main electrode <NUM> on the same main surface of the substrate <NUM>. This configuration facilitates the formation of a plurality of semiconductor elements on the single substrate so as to integrate a plurality of semiconductor devices.

The substrate <NUM> used may be a semi-insulating substrate or an insulating substrate. The use of the substrate of this type can simplify an element-separation process when integrating a plurality of semiconductor devices on the common substrate <NUM>. The use of such a substrate in the semiconductor device, when mounted on a refrigerator, can eliminate an additional insulating substrate to be provided between the substrate <NUM> and the refrigerator. The insulating substrate as used herein is a substrate having a resistivity of several kΩ·cm or greater.

For example, a silicon carbide substrate (a SiC substrate) having insulation properties may be used as the substrate <NUM>. The SiC is a wide bandgap semiconductor having a small number of intrinsic carriers, and thus can easily ensure high insulating properties to achieve a semiconductor device having a high breakdown voltage. While the SiC can be selected from several polycrystalline types, a typical <NUM>-SiC substrate may be used as the substrate <NUM>. The use of the SiC substrate as the substrate <NUM> can ensure high insulating properties and high thermal conductivity. The substrate <NUM> thus can be mounted on a cooling mechanism with the bottom surface directly attached, so as to cool the semiconductor device efficiently. The configuration including the SiC substrate having high thermal conductivity can efficiently release generated heat derived from the main current in the state in which the semiconductor device is in the ON state.

A method of manufacturing the semiconductor device according to the first embodiment of the present invention is described below with reference to the drawings. The method of manufacturing the semiconductor device described below is an example, and the semiconductor device can be manufactured by any other methods including modified examples of this embodiment. The method of the present embodiment is illustrated below with a case in which an undoped SiC substrate is used as the substrate <NUM>.

First, as illustrated in <FIG>, the substrate <NUM> is doped with p-type impurities by ion implantation by use of a delineated mask material <NUM> as a mask so as to selectively form the first electrode-connection region <NUM>.

A silicon oxide film may be used as a typical mask material, and a thermal chemical vapor deposition (CVD) method or a plasma CVD method may be used as a deposition method. A method of delineation may be photolithography. In particular, the mask material is subjected to etching by use of a delineated photoresist film as a mask. The etching method used may be wet etching using hydrofluoric acid or dry etching such as reactive ion etching. The photoresist film is then removed with oxygen plasma or sulfuric acid. The mask material is thus delineated.

Next, as illustrated in <FIG>, the upper part of the substrate <NUM> is doped with n-type impurities by ion implantation by use of a delineated mask material <NUM> as a mask so as to form the drift region <NUM> and the low-density electric-field relaxation region <NUM>. The low-density electric-field relaxation region <NUM> is formed next to the drift region <NUM>. For example, the drift region <NUM> and the low-density electric-field relaxation region <NUM> are formed by single continuous ion implantation in which an ion implantation condition of doping with ions having a high impurity concentration at high implantation energy is switched to an ion implantation condition of doping with ions having a low impurity concentration at low implantation energy.

Next, as illustrated in <FIG>, the column region <NUM> connected to the low-density electric-field relaxation region <NUM> and extending parallel to the drift region <NUM> is formed by ion implantation with p-type impurities by use of a delineated mask material <NUM> as a mask. The column region <NUM> is arranged between the first electrode-connection region <NUM> and the low-density electric-field relaxation region <NUM>.

Next, as illustrated in <FIG>, the second electrode-connection region <NUM> is formed at a predetermined position by ion implantation with n-type impurities by use of a delineated mask material <NUM> as a mask. The second electrode-connection region <NUM> is arranged so as to be connected to the edge of the drift region <NUM> such that the low-density electric-field relaxation region <NUM> is located between the column region <NUM> and the second electrode-connection region <NUM>.

For example, the ion implantation uses nitrogen (N) as n-type impurities, and aluminum or boron as p-type impurities. The execution of the ion implantation in a state in which the substrate <NUM> is heated to a temperature of about <NUM> can avoid a cause of a crystal defect in the region in which ions are implanted. The impurities implanted by the ion implantation are then subjected to annealing so as to be activated. For example, the annealing is executed at a temperature of about <NUM> in an argon atmosphere or a nitrogen atmosphere.

The respective impurity concentrations in the column region <NUM> and the drift region <NUM> are set in a range of about 1E15/cm<NUM> to 1E19/cm<NUM>, for example. The respective impurity concentrations in the column region <NUM> and the drift region <NUM> are set to fulfil the relation given by the formula (<NUM>) so as to cause the column region <NUM> and the drift region <NUM> to be depleted due to the depletion layer extending from the interface between the drift region <NUM> and the column region <NUM> in the OFF state.

The impurity concentration of the low-density electric-field relaxation region <NUM> is about half of the impurity concentration of the drift region <NUM>, for example. The present inventors have confirmed that setting the impurity concentration of the low-density electric-field relaxation region <NUM> to about half of the impurity concentration of the drift region <NUM> can achieve the effects of effectively relaxing the concentration of the electric field. As described above, the switch between the ion implantation conditions such as the implantation energy and the impurity concentration in the middle of the ion implantation can provide the drift region <NUM> and the low-density electric-field relaxation region <NUM> having different impurity concentrations by the single continuous ion implantation. The switch between the ion implantation conditions thus can vary the impurity concentration in the depth direction to expand the flexibility of setting of the impurity concentrations so as to further improve the maximum application voltage of the semiconductor device.

In the configuration in which the column region <NUM> and the low-density electric-field relaxation region <NUM> are connected to each other along the drift region <NUM>, a concentration distribution of the impurity concentration of the low-density electric-field relaxation region <NUM> is inclined in the film thickness direction so as to have a higher impurity concentration in a region closer to the drift region <NUM>. The continuous variation in the impurity concentration of the low-density electric-field relaxation region <NUM> can further equalize the electric field at the edge of the column region <NUM>. This can improve the maximum application voltage of the semiconductor device accordingly.

The impurity concentration in the first electrode-connection region <NUM> is set in a range of about 1E15/cm<NUM> to 1E19/cm<NUM>, for example. The impurity concentration in the second electrode-connection region <NUM> is set in a range of about 1E18/cm<NUM> to 1E21/cm<NUM>, for example.

The formation of each of the drift region <NUM>, the column region <NUM>, the first electrode-connection region <NUM>, the second electrode-connection region <NUM>, and the low-density electric-field relaxation region <NUM> by the ion implantation can eliminate an epitaxial growth process, so as to reduce the manufacturing costs.

After the second electrode-connection region <NUM> is formed as illustrated in <FIG>, the insulation film <NUM> is formed on the semiconductor base body <NUM>. The insulation film <NUM> used may be a silicon oxide film or a silicon nitride film. For example, the insulation film <NUM> is provided by a thermal CVD method or a plasma CVD method. A first contact hole <NUM> and a second contact hole <NUM> are then formed in the insulation film <NUM> by dry etching or wet etching by use of a photoresist film (not illustrated) as a mask, as illustrated in <FIG>.

Next, the first main electrode <NUM> is buried to fill the first contact hole <NUM>, and the second main electrode <NUM> is buried to fill the second contact hole <NUM>. The semiconductor device as illustrated in <FIG> is thus completed.

A material used for the first main electrode <NUM> and the second main electrode <NUM> may be a metal material such as titanium (Ti), nickel (Ni), and molybdenum (Mo), or a stacked film of Ti-Ni-Ag. For example, the first main electrode <NUM> and the second main electrode <NUM> are formed such that the metal material is deposited on the entire surface by a sputtering method or an electron beam (EB) vapor deposition method, and the metal material is then etched by dry etching by use of as a delineated photoresist film and the like as a mask. Alternatively, the first main electrode <NUM> and the second main electrode <NUM> may be formed by a plating process.

According to the method of manufacturing the semiconductor device described above, the low-density electric-field relaxation region <NUM> is arranged between the column region <NUM> and the second electrode-connection region <NUM>. This can relax the concentration of the electric field at the edge of the column region <NUM> on the second main electrode side during the reverse bias. The semiconductor device having the SJ structure thus can avoid a reduction in the breakdown voltage.

A length of the low-density electric-field relaxation region <NUM> along the current passage is in a range of about <NUM>% to <NUM>% of the entire length of the column region <NUM> and the low-density electric-field relaxation region <NUM> connected together, for example. If the length of the low-density electric-field relaxation region <NUM> is too short, the low-density electric-field relaxation region <NUM> is led to the pinch-off state, and the effects of relaxing the concentration of the electric field at the edge of the column region <NUM> is decreased. If the length of the low-density electric-field relaxation region <NUM> is too long, the ratio of the SJ structure in the drift region <NUM> is decreased, reducing the breakdown voltage accordingly.

While the present embodiment is illustrated above with the case of using the SiC substrate as the substrate <NUM>, the substrate <NUM> may be any other semi-insulating substrate or insulating substrate instead of the SiC substrate. For example, a GaN substrate, a diamond substrate, a zinc oxide (ZnO) substrate, or an AlGaN substrate of a wide bandgap substrate may be used as the substrate <NUM>.

The semiconductor base body <NUM> may be a wide bandgap semiconductor. Such a semiconductor can increase the impurity concentration while ensuring a high breakdown voltage. Using the wide bandgap semiconductor having a high insulation breakdown electric field as the drift region <NUM> can achieve the semiconductor device having a high breakdown voltage at a low ON resistance.

The semiconductor base body <NUM> using the same material for the respective regions can lead the semiconductor device to include the respective active regions formed of the same semiconductor material. This can avoid a fault derived from a defect caused upon connection between different semiconductor materials, and improve the reliability of the semiconductor device accordingly.

The substrate <NUM> and the semiconductor base body <NUM> such as the drift region <NUM> may be formed of the same material. The use of the same material for the substrate <NUM> and the semiconductor base body <NUM> can prevent deterioration in performance of the semiconductor device derived from lattice incompatibility due to the use of different materials. For example, when the SiC substrate is used as the substrate <NUM>, the semiconductor base body <NUM> in which the SiC is doped with impurities is deposited on the substrate <NUM>.

A semiconductor device according to a second embodiment of the present invention further includes a high-density electric-field relaxation region <NUM> of the first conductivity type arranged on the low-density electric-field relaxation region <NUM> to be stacked together in a direction perpendicular to the extending direction of the column region <NUM>, as illustrated in <FIG>. The high-density electric-field relaxation region <NUM> has a higher impurity concentration than the low-density electric-field relaxation region <NUM>, and is connected to the edge of the main surface of the column region <NUM> in contact with the drift region <NUM>. The impurity concentration of the high-density electric-field relaxation region <NUM> is one and a half times higher than the drift region <NUM>, for example.

The semiconductor device illustrated in <FIG> has a configuration in which the high-density electric-field relaxation region <NUM> is deposited on the top surface of the drift region <NUM>, and the low-density electric-field relaxation region <NUM> is further deposited on the top surface of the high-density electric-field relaxation region <NUM>. The other configurations are the same as in the first embodiment illustrated in <FIG>. The high-density electric-field relaxation region <NUM> and the low-density electric-field relaxation region <NUM> can be continuously provided by the single ion implantation such that the ion implantation conditions are switched in the middle of the ion implantation.

<FIG> is a model according to the second embodiment (a second embodiment model) for calculating electric field intensity of the structure of the low-density electric-field relaxation region <NUM> and the high-density electric-field relaxation region <NUM> stacked together. The second embodiment model is configured such that the drift region <NUM> has a width W1 in the width direction Y set to <NUM>, the low-density electric-field relaxation region <NUM> has a width W21 set to <NUM>, and the high-density electric-field relaxation region <NUM> has a width W22 set to <NUM>. The second embodiment model is also configured such that the column region <NUM> and the drift region <NUM> each have an impurity concentration set to 8E16/cm<NUM>, the low-density electric-field relaxation region <NUM> has an impurity concentration set to 4E16/cm<NUM>, and the high-density electric-field relaxation region <NUM> has an impurity concentration set to <NUM>. 5E17/cm<NUM>.

<FIG> illustrates the results of calculating the electric field intensity for the comparative example model as illustrated in <FIG>, for the first embodiment model as illustrated in <FIG>, and for the second embodiment model as illustrated in <FIG>. <FIG> indicates the electric field of the comparative example model by property E0, the electric field of the first embodiment model by property E1, and the electric field of the second embodiment model by property E2. <FIG> is a partly enlarged graph of the calculation results shown in <FIG> while showing a region including the low-density electric-field relaxation region <NUM> and the high-density electric-field relaxation region <NUM>.

As shown in <FIG>, the second embodiment model shows a peak value of the electric field intensity decreased from a position at which the electric field intensity is highest (Y = <NUM>). The reason for this is because the arrangement of the stacked structure of the low-density electric-field relaxation region <NUM> and the high-density electric-field relaxation region <NUM> between the column region <NUM> and the second electrode-connection region <NUM> disperses the electric field around the high-density electric-field relaxation region <NUM> having a higher impurity concentration. The dispersion of the electric field relaxes the concentration at the edge of the opposed main surface of the column region <NUM> at which the electric field is concentrated most.

As described above, the semiconductor device according to the second embodiment of the present invention has the configuration including the low-density electric-field relaxation region <NUM> and the high-density electric-field relaxation region <NUM> stacked together. This configuration leads the electric field to be concentrated around the high-density electric-field relaxation region <NUM> having a higher impurity concentration than the low-density electric-field relaxation region <NUM> to equalize the distribution of the electric field at the edge of the column region <NUM>. The semiconductor device thus can increase the maximum application voltage.

Alternatively, as illustrated in <FIG>, a part of the high-density electric-field relaxation region <NUM> may be arranged between the drift region <NUM> and the second electrode-connection region <NUM>. The configuration illustrated in <FIG> spreads the electric field toward the substrate between the drift region <NUM> and the second electrode-connection region <NUM>. The spread of the electric field can further relax the concentration of the electric field at the edge of the opposed main surface of the column region <NUM>. The effect described above can be achieved also by a configuration in which the high-density electric-field relaxation region <NUM> is arranged to further extend along the entire side surface of the drift region <NUM>, as illustrated in <FIG>.

A semiconductor device according to a first example has a configuration in which the semiconductor base body <NUM> further includes a source region <NUM> of the first conductivity type arranged between the first electrode-connection region <NUM> and the first main electrode <NUM>, as illustrated in <FIG>. The semiconductor base body <NUM> is provided on the top surface with gate trenches having openings along the column region <NUM>, the first electrode-connection region <NUM>, and the source region <NUM> to have a depth reaching the substrate <NUM>. The gate trenches are each provided with a gate insulation film <NUM> to cover the inner wall surface, and the control electrodes <NUM> are arranged inside the gate trenches. The electrodes <NUM> are arranged to be opposed to the drift region <NUM>, the column region <NUM>, the first electrode-connection region <NUM>, and the source region <NUM> via the gate insulation films <NUM>.

The control electrodes <NUM> are located on the current passage of the main current flowing between the first main electrode <NUM> and the second main electrode <NUM>. The semiconductor device as illustrated in <FIG> functions as a transistor in which the control electrodes <NUM> control the main current while the first main electrode <NUM> serves as a source electrode and the second main electrode <NUM> serves as a drain electrode. An inversion layer is formed during the ON operation in a channel region in which the first electrode-connection region <NUM> is in contact with the gate insulation films <NUM>.

The first main electrode <NUM> is connected to the source region <NUM> by an ohmic contact, and the second main electrode <NUM> is connected to the second electrode-connection region <NUM> by the ohmic contact. A control electrode wire <NUM> is provided on the top surfaces of the control electrodes <NUM> to as to electrically connect the respective control electrodes <NUM> to each other. <FIG> illustrates only the outer frame of the control electrode wire <NUM> for brevity.

The other configurations are the same as in the first embodiment as illustrated in <FIG>. The semiconductor substrate illustrated in <FIG> also has the configuration in which the semiconductor base body <NUM> has the SJ structure, and the low-density electric-field relaxation region <NUM> of the first conductivity type having a lower impurity concentration than the drift region <NUM> is arranged between the second electrode-connection region <NUM> and the column region <NUM>. The main operations of the semiconductor device illustrated in <FIG> are described below.

A potential of the control electrodes <NUM> (gate electrodes) is controlled during the ON operation in a state in which a positive potential is applied to the second main electrode <NUM> (the drain electrode) on the basis of the first main electrode <NUM> (the source electrode) as a reference potential, so that the semiconductor device serves as a transistor. In particular, a voltage between the respective control electrodes <NUM> and the first main electrode <NUM> is set to be a predetermined threshold or greater, so that the inversion layer is formed in the channel region in the first electrode-connection region <NUM> on the side surface of the respective control electrodes <NUM>. This leads the semiconductor device to be in the ON state so that the main current flows between the first main electrode <NUM> and the second main electrode <NUM>.

The voltage between the respective control electrodes <NUM> and the first main electrode <NUM> is set to be the predetermined threshold or smaller during the OFF operation. The inversion layer then disappears to lead the main current to stop. The depletion layer spreads from the interface between the drift region <NUM> and the column region <NUM>, and the drift region <NUM> and the column region <NUM> are thus in the pinch-off state. The concentration of the electric field at the edge of the column region <NUM> on the second main electrode side is also relaxed by the low-density electric-field relaxation region <NUM> in the semiconductor device as illustrated in <FIG>. The semiconductor device thus can improve the breakdown voltage accordingly.

A method of manufacturing the semiconductor device according to the first example is described below with reference to the drawings. The method of manufacturing the semiconductor device described below is an example, and the semiconductor device can be manufactured by any other methods including modified examples of this example. The method of the present example is illustrated below with the case in which an undoped SiC substrate is used as the substrate <NUM>.

Next, as illustrated in <FIG>, the upper part of the substrate <NUM> is doped with n-type impurities by ion implantation by use of a delineated mask material <NUM> as a mask so as to form the drift region <NUM> and the low-density electric-field relaxation region <NUM>. The drift region <NUM> and the low-density electric-field relaxation region <NUM> can be continuously formed by the switch between the ion implantation conditions, in the same manner as in the first embodiment.

Next, as illustrated in <FIG>, the column region <NUM> is formed between the first electrode-connection region <NUM> and the low-density electric-field relaxation region <NUM> by ion implantation with p-type impurities by use of a delineated mask material <NUM> as a mask.

Next, as illustrated in <FIG>, the second electrode-connection region <NUM> and the source region <NUM> are formed at predetermined positions by ion implantation of doping with n-type impurities by use of a delineated mask material <NUM> as a mask. In particular, the second electrode-connection region <NUM> is formed such that the second electrode-connection region <NUM> is connected to the edge of the drift region <NUM> and the low-density electric-field relaxation region <NUM> is arranged between the column region <NUM> and the second electrode-connection region <NUM>. The source region <NUM> is arranged in contact with the side surface of the first electrode-connection region <NUM>.

Next, gate trenches <NUM> are formed by dry etching by use of a delineated mask material (not illustrated) as a mask, as illustrated in <FIG>. The gate trenches <NUM> are provided at the positions to be in contact with the drift region <NUM>, the column region <NUM>, the first electrode-connection region <NUM>, and the source region <NUM> so as to have a depth reaching the substrate <NUM>.

Next, the gate insulation films <NUM> are formed on the inner wall surfaces of the gate trenches <NUM>. A method of forming the insulation films <NUM> can be either a thermal oxidation method or a deposition method. For example, in the case of the thermal oxidation method, the semiconductor base body <NUM> is heated to a temperature of about <NUM> in an oxygen atmosphere. All of the parts in contact with oxygen in the semiconductor base body <NUM> are thus provided with a silicon oxide film.

The gate insulation films <NUM>, after being provided, may be subjected to annealing at a temperature of about <NUM> in an atmosphere of nitrogen, argon, or N<NUM>O, for example, so as to reduce an interface level at the interface between the first electrode-connection region <NUM> and the gate insulation films <NUM>. The gate insulation films <NUM> may be subjected to thermal oxidation in an atmosphere of NO or N<NUM>O. An appropriate temperature during the thermal oxidation is in a range of <NUM> to <NUM>. The thickness of the insulation films <NUM> is set to about several tens of nanometers.

Next, a conductive material is buried in the gate trenches <NUM> to form the control electrodes <NUM>. Atypical material used for the control electrodes <NUM> is a polysilicon film. The present example is illustrated below with the case of using the polysilicon film for the control electrodes <NUM>.

The deposition method used for the polysilicon film may be a decompression CVD method, for example. For example, the gate trenches <NUM> are filled with the polysilicon film such that a thickness of the polysilicon film to be buried is set to be greater than half of the width of the respective gate trenches <NUM>. Setting the thickness of the polysilicon film as described above can completely fill the gate trenches <NUM> with the polysilicon film, since the polysilicon film is gradually deposited on the inner wall surfaces of the respective gate trenches <NUM>. For example, when the width of the respective gate trenches <NUM> is <NUM>, the polysilicon film is deposited so as to have the thickness of greater than <NUM>. The gate trenches <NUM> are subjected to annealing at a temperature of <NUM> in phosphorus oxychloride (POCl3) after the deposition of the polysilicon film so as to provide the n-type polysilicon films and lead the control electrodes <NUM> to have conductivity.

Next, as illustrated in <FIG>, the polysilicon films are subjected to etching to be flattened. The etching method may be either isotropic etching or anisotropic etching. The amount of etching is set so as to cause the polysilicon films to remain inside the gate trenches <NUM>. For example, when the polysilicon films with the thickness of <NUM> are deposited on the gate trenches <NUM> with the width of <NUM>, the amount of etching of the polysilicon films is set to <NUM>. Several percent of overetching is an available level upon controlling the amount of etching of <NUM>. Next, as illustrated in <FIG>, the control electrode wire <NUM> is formed of a polysilicon film as the same material used for the control electrodes <NUM> or a metallic film so as to electrically connect the respective gate electrodes to each other.

Next, the insulation film <NUM> is formed on the entire surface. A material used for the insulation film <NUM> is a silicon oxide film or a silicon nitride film. Next, the first contact hole <NUM> and the second contact hole <NUM> are formed in the insulation film <NUM> by dry etching or wet etching by use of a photoresist film (not illustrated) as a mask, as illustrated in <FIG>.

While the present example is illustrated above with the case of using the n-type polysilicon film for the control electrodes <NUM>, a p-type polysilicon film may be used for the control electrodes <NUM>. Any other semiconductor material may be used for the control electrodes <NUM>, or any other conductive material such as metallic material may be used for the control electrodes <NUM>. For example, any of p-type polysilicon carbide, SiGe, or Al may be used as a material for the control electrodes <NUM>.

While the present example is illustrated above with the case of using the silicon oxide film as the gate insulation films <NUM>, a silicon nitride film may be used as the gate insulation films <NUM>. Alternatively, a stacked film of a silicon oxide film and a silicon nitride film may be used as the respective gate insulation films <NUM>. The isotropic etching upon the use of the silicon nitride film as the gate insulation films <NUM> may be executed by cleaning with hot phosphoric acid at a temperature of <NUM>.

The semiconductor device is illustrated above with a MOS transistor in which the first main electrode <NUM> serves as a source electrode, the second main electrode <NUM> serves as a drain electrode, and the respective control electrodes <NUM> serve as a gate electrode. The semiconductor device of the present example may be any other transistor. For example, a bipolar transistor in which the first main electrode <NUM> serves as an emitter electrode, the second main electrode <NUM> serves as a collector electrode, and the respective control electrodes <NUM> serve as a base electrode, can also relax the concentration of the electric field at the edge of the column region <NUM> on the second main electrode side due to the low-temperature electric-field relaxation region <NUM>.

A semiconductor device according to a second example has a configuration, as illustrated in <FIG>, in which the drift region <NUM> is also provided along the side surface of the column region <NUM> on the second main electrode side, and the second electrode-connection region <NUM> and the low-density electric-field relaxation region <NUM> are arranged adjacent to each other on the top surface of the drift region <NUM> at the end on the second main electrode side in a plan view. The other configurations are the same as in the first embodiment illustrated in <FIG>.

The semiconductor device illustrated in <FIG>, which includes the low-density electric-field relaxation region <NUM> adjacent to the edge of the column region <NUM> at which the electric field is concentrated most, can decrease the peak value of the electric field intensity. The semiconductor device illustrated in <FIG> has a configuration in which the second electrode-connection region <NUM> and the low-density electric-field relaxation region <NUM> have no surfaces opposed to the column region <NUM>. The decrease in the area on which the column region <NUM> and the second electrode-connection region <NUM> are opposed, or the elimination of the opposed surface therebetween can reduce a stray capacitance derived from the capacitance of the depletion layer extending between the column region <NUM> and the second electrode-connection region <NUM>.

A method of manufacturing the semiconductor device according to the second example is described below with reference to the drawings. The method of manufacturing the semiconductor device described below is an example, and the semiconductor device can be manufactured by any other methods including modified examples of this example. The method of the present example is illustrated below with the case in which an undoped SiC substrate is used as the substrate <NUM>.

Next, as illustrated in <FIG>, the upper part of the substrate <NUM> is doped with n-type impurities by ion implantation by use of a delineated mask material <NUM> as a mask so as to form the drift region <NUM> and the low-density electric-field relaxation region <NUM>. The drift region <NUM> and the low-density electric-field relaxation region <NUM> can be continuously formed by the switch between the ion implantation conditions.

Next, as illustrated in <FIG>, the upper part of the first electrode-connection region <NUM> and the low-density electric-field relaxation region <NUM> on the first main electrode side are partly removed by etching by use of a delineated mask material <NUM> as an etching mask. The top surface of the drift region <NUM> and the side surface of the low-density electric-field relaxation region <NUM> on the first main electrode side are exposed to the outside.

Next, as illustrated in <FIG>, the top surface of the drift region <NUM> from which the low-density electric-field relaxation region <NUM> is removed by etching is subjected to ion implantation with p-type impurities by use of a mask material <NUM> as a mask, so as to form the column region <NUM>.

Next, as illustrated in <FIG>, the second electrode-connection region <NUM> is formed at a predetermined position by ion implantation of doping with n-type impurities by use of a mask material <NUM> as a mask. Next, the insulation film <NUM>, the first main electrode <NUM>, and the second main electrode <NUM> are formed in the same manner as in the first embodiment. The semiconductor device as illustrated in <FIG> is thus completed.

A semiconductor device according to a third example has a configuration in which the first main electrode <NUM> is deposited on a first main surface <NUM> of the semiconductor base body <NUM>, and the second main electrode <NUM> is deposited on a second main surface <NUM> of the semiconductor base body <NUM> opposed to the first main surface <NUM>, as illustrated in <FIG>. The semiconductor device as illustrated in <FIG> is configured such that the drift region <NUM> and the column region <NUM> extend in the film thickness direction of the semiconductor base body <NUM> so as to cause the main current to flow in the film thickness direction of the semiconductor base body <NUM>. Namely, the first main electrode <NUM> is arranged on the top surface of the first electrode-connection region <NUM>, and the second main electrode <NUM> is arranged on the bottom surface of the second electrode-connection region <NUM>.

In the semiconductor device as illustrated in <FIG>, the low-density electric-field relaxation region <NUM> is also arranged between the column region <NUM> and the second electrode-connection region <NUM>. This configuration can relax the concentration of the electric field at the edge of the column region <NUM> on the second main electrode side, so as to improve the breakdown voltage.

A method of manufacturing the semiconductor device according to the third example is described below with reference to the drawings. The method of manufacturing the semiconductor device described below is an example, and the semiconductor device can be manufactured by any other methods including modified examples of this example. The method of the present example is illustrated below with the case in which an undoped SiC substrate is used as the substrate <NUM>.

As illustrated in <FIG>, the drift region <NUM> is deposited on the second electrode-connection region <NUM> as a conductive substrate. Next, as illustrated in <FIG>, the drift region <NUM> is doped with n-type impurities by ion implantation by use of a delineated mask material <NUM> as a mask so as to form the low-density electric-field relaxation region <NUM>. Adjusting implantation energy of impurities can provide the low-density electric-field relaxation region <NUM> at a depth so as to be in contact with the second electrode-connection region <NUM>.

Next, as illustrated in <FIG>, the top surface of the drift region <NUM> is subjected to ion implantation with p-type impurities by use of the mask material <NUM> as a mask to form the column region <NUM> so as to be in contact with the top surface of the low-density electric-field relaxation region <NUM>. Next, as illustrated in <FIG>, the entire top surfaces of the drift region <NUM> and the column region <NUM> are subjected to ion implantation with p-type impurities so as to form the first electrode-connection region <NUM>.

Next, the first main electrode <NUM> is deposited on the top surface of the first electrode-connection region <NUM>, and the second main electrode <NUM> is deposited on the bottom surface of the second electrode-connection region <NUM>. The semiconductor device as illustrated in <FIG> is thus completed.

The semiconductor device according to the third example, which is configured such that the main current flows in the film thickness direction of the semiconductor base body <NUM>, can increase a current density of the main current to reduce the ON resistance per unit area. The semiconductor device according to the third example can also relax the concentration of the electric field at the edge of the column region <NUM> on the second main electrode side, so as to improve the breakdown voltage accordingly.

The semiconductor device as illustrated in <FIG> has the super junction structure in which the plural drift regions <NUM> and the plural column regions <NUM> are alternately arranged in the direction perpendicular to the current passage. Increasing the structure in which the drift regions <NUM> and the column regions <NUM> are arranged adjacent to each other can increase the current density per unit area.

While the present invention has been described above by reference to the respective embodiments, it should be understood that various alternative embodiments, and technical applications will be apparent according to this disclosure.

It is useful for understanding the present invention, but not falling under the scope of the claims that the semiconductor device may be a Schottky barrier diode (SBD) in which the drift region <NUM> and the first main electrode <NUM> are connected to each other. The drift region <NUM> and the first main electrode <NUM> are electrically connected to each other to have an energy barrier provided at the interface. A Schottky junction is provided between the drift region <NUM> and the first main electrode <NUM> while a metal material having a high work function such as nickel or platinum is used for the first main electrode <NUM>. A material having a low work function such as titanium to be in ohmic contact with the second electrode-connection region <NUM> is used for the second main electrode <NUM>. The semiconductor device, when using the SBD but including the low-density electric-field relaxation region <NUM> arranged between the column region <NUM> and the second electrode-connection region <NUM>, can relax the concentration of the electric field at the edge of the column region <NUM> on the second main electrode side.

The case has been described above in which the single drift region <NUM> and the single column region <NUM> are stacked in the film thickness direction. Alternatively, the plural drift regions <NUM> and the plural column regions <NUM> may be alternately arranged in the film thickness direction perpendicular to the current passage so as to implement the super junction structure. The structure in which the drift region <NUM> and the column region <NUM> are stacked in the film thickness direction adjusts the intensity of the implementation energy for doping with impurities, so as to accurately regulate the width of each of the drift region <NUM> and the column region <NUM>. The SJ structure in which a plurality of p-n junctions are arranged at regular intervals in the film thickness direction can further improve the breakdown voltage of the semiconductor device.

The stacked structure of the low-density electric-field relaxation regions <NUM> and the high-density electric-field relaxation regions <NUM> may be applied to the case of the SJ structure in which a plurality of p-n junctions are arranged regularly in the film thickness direction. When this case is applied, the plural high-density electric-field relaxation regions <NUM> are arranged in regions adjacent to the p-n junctions, while the low-density electric-field relaxation regions <NUM> are interposed between the respective high-density electric-field relaxation regions <NUM>, as illustrated in <FIG>. This structure can lead the concentration of the electric field, which has a peak in the regions away from the p-n junctions between the drift regions <NUM> and the column regions <NUM>, to be relaxed in the column regions <NUM>.

Claim 1:
A semiconductor device comprising:
a semiconductor base body (<NUM>); and
a first main electrode (<NUM>) and a second main electrode (<NUM>) provided on the semiconductor base body (<NUM>) to serve as both ends of a current passage of a main current flowing in an ON state,
the semiconductor base body (<NUM>) including:
a drift region (<NUM>) of a first conductivity type through which the main current flows;
a column region (<NUM>) of a second conductivity type arranged on top of the drift region (<NUM>) in parallel to the current passage of the main current, a main surface of the column region (<NUM>) being in contact with the drift region (<NUM>);
a first electrode-connection region (<NUM>) of the second conductivity type between the first main electrode (<NUM>) and the drift region (<NUM>);
a second electrode-connection region (<NUM>) of the first conductivity type electrically connected to the second main electrode (<NUM>) and connected to the drift region (<NUM>), wherein one end of the drift region (<NUM>) is connected to the first electrode-connecting region (<NUM>) electrically connected to the first main electrode (<NUM>) and another end of the drift region (<NUM>) is connected to the second electrode-connection region (<NUM>) connected to the second main electrode (<NUM>);
a low-density electric-field relaxation region (<NUM>) of the first conductivity type having a lower impurity concentration than the drift region (<NUM>), and arranged between the second electrode-connection region (<NUM>) and the column region (<NUM>), the low-density electric-field relaxation region (<NUM>) extending above the drift region (<NUM>) in parallel to the current passage of the main current; and
a high-density electric-field relaxation region (<NUM>) of the first conductivity type having a higher impurity concentration than the low-density electric-field relaxation region (<NUM>), and arranged below the low-density electric-field relaxation region (<NUM>) parallel to the current passage and above the drift region (<NUM>), the low-density electric-field relaxation region (<NUM>) and the high-density electric-field relaxation region (<NUM>) being stacked together in a direction perpendicular to an extending plane of the column region (<NUM>) such that the high-density electric-field relaxation region (<NUM>) is in contact with an edge of the main surface of the column region (<NUM>).