Patent Description:
Various features relate to packages and substrates, but more specifically to packages that includes substrate and integrated devices.

A package may include a substrate and an integrated device. Power to the integrated device may be provided through interconnects of the substrate. How the power to the integrated device is routed through the substrate may affect the performance of the integrated device and the packages. There is an ongoing need to provide packages that take full advantage of the capabilities of the integrated devices. Attention is drawn to document <CIT> which relates to an integrated circuit package including a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

Further embodiments of the invention are defined by the appended dependent claims. Various features relate to packages and substrates, but more specifically to packages that includes substrate and integrated devices.

One example provides a package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power source to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power source to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power from the second power source to travel to the first core of the integrated device.

Another example provides a package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes a first power interconnect configured to provide a first electrical path for a first power source to the first integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power source to the second integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power from the second power source to travel to the first integrated device.

Another example provides a method that comprises operating an integrated device that includes a first core and a second core, wherein a first power resource is directed to the first core and a second power resource is directed to the second core. The method determines that the first core of the integrated device needs more power. The method turns on at least one switch to reroute some of the second power resource to the first core of the integrated device.

Another example provides a method that comprises operating a first integrated device, where a first power resource is directed to the first integrated device. The method operates a second integrated device, wherein a second power resource is directed to the second integrated device. The method determines that the first integrated device needs more power. The method turns on at least one switch to reroute some of the second power resource to the first integrated device.

Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.

The present disclosure describes a package that includes a substrate and an integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to travel to the first core of the integrated device. The sharing of power resources helps enable the integrated device to perform optimally by providing additional power to one or more cores that may need it and/or want it, if another core may not need as much power.

<FIG> illustrates a package <NUM> that includes a substrate <NUM>, an integrated device <NUM> and an encapsulation layer <NUM>. As will be further described below, the integrated device <NUM> is configured for shared power resource. The package <NUM> is coupled to a board <NUM> through a plurality of solder interconnects <NUM>. The integrated device <NUM> is coupled to the substrate <NUM> through a plurality of solder interconnects <NUM>. The encapsulation layer <NUM> is coupled to the substrate <NUM>. The encapsulation layer <NUM> is located over the substrate <NUM> and the integrated device <NUM>. The encapsulation layer <NUM> encapsulates the integrated device <NUM>. A passive device <NUM> is coupled to the substrate <NUM>. The passive device <NUM> may include a capacitor. An interconnect <NUM> may extend through the encapsulation layer <NUM>. The interconnect <NUM> may include a through mold via (TMV). The interconnect <NUM> may be coupled to the substrate <NUM>.

The integrated device <NUM> is coupled to the substrate <NUM> through the plurality of solder interconnects <NUM>. In some implementations, the integrated device <NUM> may be coupled to the substrate <NUM> through the plurality of solder interconnects <NUM> and pillar interconnects. An underfill <NUM> is located between the integrated device <NUM> and the substrate <NUM>. The underfill <NUM> may be located around the plurality of solder interconnects <NUM>. The integrated device <NUM> includes at least two cores. For example, the integrated device <NUM> includes a first core <NUM> and a second core <NUM>. A core may be a processing unit of an integrated device, that is configured to read and execute program instructions. Each core of an integrated device may be a separate processing unit of the integrated device. In some implementations, each core may be configured to perform separate and/or different functions for the integrated device <NUM>.

The substrate <NUM> includes at least one dielectric layer <NUM> and a plurality of interconnects <NUM>. As will be further described below in at least <FIG>, the plurality of interconnects <NUM> includes interconnects that are configured to provide electrical paths for power resource to the cores of the integrated device <NUM>. The substrate <NUM> also includes at least one switch <NUM>. The at least one switch <NUM> may include at least one transistor. The at least one switch <NUM> includes a gate interconnect <NUM>, a source interconnect <NUM>, a drain interconnect <NUM>, a gate dielectric layer <NUM>, and a channel <NUM>. When a voltage is applied at the gate interconnect <NUM>, a current may be induced from the source interconnect <NUM> to the drain interconnect <NUM> through the channel <NUM>. The at least one switch <NUM> may be used to provide shareable power resources to the cores of the integrated device <NUM>. The at least one switch <NUM> may be located in different portions of the substrate <NUM>. In some implementations, the at least one switch <NUM> may be located near a top metal layer of the substrate <NUM> (e.g., metal layer near an integrated device coupled to the substrate <NUM>). In some implementations, the at least one switch <NUM> may be located near a bottom metal layer of the substrate <NUM> (e.g., metal layer that is coupled to a solder interconnect (e.g., ball grid array)). In some implementations, the at least one switch <NUM> may be located in the substrate <NUM>, near where the passive device <NUM> is coupled to the substrate <NUM>.

The plurality of interconnects <NUM> may include several power interconnects (e.g., power planes) that are each configured to provide an electrical path for a power resource (e.g., power) to one or more integrated devices (e.g., core of an integrated device). For example, a first power interconnect (e.g., first power plane) may be used to provide an electrical path for power to the first core <NUM>, and a second power interconnect (e.g., second power plane) may be used to provide an electrical path for power to the second core <NUM>. The various power resources may be coupled to one or more power management integrated devices (e.g., power management integrated circuit (PMIC)). Thus, the various power resources may travel through one or more power management integrated devices. The various power resources may be part of a power grid resource. A power grid resource may include at least one power resource and a ground. Although not shown, the one or more power management integrated devices may be coupled to the substrate <NUM>, the package <NUM>, another substrate and/or the board <NUM>. In one example, a power source (e.g., battery) may be coupled to one or more power management integrated devices. Energy (e.g., electrical current) from the power source may travel through the one or more power management integrated devices, and may get redistributed to various integrated devices and/or cores of integrated devices through a power grid resource that includes several power resource electrical paths (e.g., first power resource electrical path, second power resource electrical path, third power resource electrical path). In another example, a first power resource may be from a first power source (e.g., first battery) and a second power resource may be from a second power source (e.g., second battery).

Different implementations may use different materials for the package <NUM>. The at least one dielectric layer <NUM> may include glass, polyimide, oxide and/or combinations thereof. The gate dielectric layer <NUM> may include HfO<NUM> (hafnium oxide), SiO<NUM> (silicon dioxide) Al<NUM>O<NUM> (aluminum oxide) and/or combinations thereof. The channel <NUM> may include polycrystalline SiGe (silicon germanium), CdSe (Cadmium selenide), IgZo (indium gallium zinc oxide), tungsten (W)-Doped In<NUM>O<NUM> (indium oxide) and/or combinations thereof. The gate interconnect <NUM>, a source interconnect <NUM>, a drain interconnect <NUM> may include copper, cobalt, tungsten (W) and/or combinations thereof.

Packages for high performance devices need to have redundancy and a high grade of robustness built into the packages. From a design perspective, power interconnects (e.g., power planes) in substrates of a package need to be separated to optimize the power consumption of the integrated devices of a package. However, separating power planes of a package weakens the power distribution network (PDN). This can result in sub allocation of power resources for different integrated devices and/or portions of an integrated devices. The end result is that integrated devices are not able to perform optimally. To help provide optimal integrated device performances in packages, switches may be implemented in substrates to allow the sharing of power resources.

<FIG> illustrates a plan view of metal layer of the substrate <NUM>. The substrate <NUM> includes a first power plane <NUM>, a second power plane <NUM>, a third power plane <NUM>, a fourth power plane <NUM>, a fifth power plane <NUM> and a sixth power plane <NUM>. The first power plane <NUM>, the second power plane <NUM>, the third power plane <NUM>, the fourth power plane <NUM>, the fifth power plane <NUM> and the sixth power plane <NUM> are examples of interconnects. Each of the power plane is configured to provide an electrical path for an integrated device (e.g., core of an integrated device). For example, the first power plane <NUM> may be configured to be coupled to the first core <NUM> of the integrated device <NUM>, and the second power plane <NUM> may be configured to be coupled to the second core <NUM> of the integrated device <NUM>. Each particular power plane is configured to be electrically coupled to a particular power resource. A power plane may be located on any metal layer of the substrate <NUM>. In some implementations, a power plane may be located on a metal layer of the substrate <NUM> that is closest to the integrated device <NUM>. Each of the power planes may be configured to be electrically coupled to one or more power management integrated devices. Thus, each of the power planes may be configured to as an electrical path for a particular electrical current through one or more power management integrated devices.

<FIG> illustrates the substrate <NUM> that includes a plurality of switches <NUM>. The plurality of switches <NUM> is coupled to the first power plane <NUM> and the second power plane <NUM>. The plurality of switches <NUM> is configured to allow a current traveling through the second power plane <NUM> to be shared with the first power plane <NUM>. When/if a switch is off, then a current may not flow through that particular switch. When/if a switch is on, then a current may flow through that particular switch. The more switches that are turned on, the more current may flow from the second power plane <NUM> to the first power plane <NUM>. Thus, the amount of power that is shared may be controlled by controlling the number of switches from the plurality of switches <NUM> that are turned on. If all the switches are off, then there is no sharing from the second power plane <NUM> to the first power plane <NUM>. <FIG> illustrates switches are coupled to the first power plane <NUM> (e.g., first interconnect) and the second power plane <NUM> (e.g., <NUM>). However, the switches may be coupled between any of the different power planes illustrated and described in the disclosure. Moreover, the substrate <NUM> may include power rails and switches may be coupled between power planes and/or power rails. The plurality of interconnects <NUM> may include the power planes (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) and/or the power rails.

<FIG> illustrates exemplary electrical paths in the package <NUM> with the switch <NUM> turned off. As shown in <FIG>, an electrical path <NUM> is coupled to the core <NUM> of the integrated device <NUM>, and an electrical path <NUM> is coupled to the core <NUM> of the integrated device <NUM>. The electrical path <NUM> (e.g., first electrical path) includes a first solder interconnect from the plurality of solder interconnects <NUM>, a first plurality of interconnects from the plurality of interconnects <NUM> (which includes the first power plane <NUM> (e.g., first power interconnect)), a first solder interconnect from the plurality of solder interconnects <NUM> and the first core <NUM>. The electrical path <NUM> (e.g., second electrical path) includes a second solder interconnect from the plurality of solder interconnects <NUM>, a second plurality of interconnects from the plurality of interconnects <NUM> (which includes the second power plane <NUM> (e.g., second power interconnect)), a second solder interconnect from the plurality of solder interconnects <NUM> and the second core <NUM>. The electrical path <NUM> may also include the passive device <NUM>.

<FIG> illustrates exemplary electrical paths in the package <NUM> with the switch <NUM> turned on. The switch <NUM> may be part of the electrical path <NUM>. The switch <NUM> may be coupled to the plurality of interconnects <NUM>. The switch <NUM> may be coupled to the integrated device <NUM> (e.g., configured to be electrically coupled to the core <NUM> of the integrated device). When/if the switch <NUM> is turned on, some power from the second power resource travelling through the electrical path <NUM> is shared and diverted to the first core <NUM> through the switch <NUM>. Some power from the second power resource may travel through the second power plane <NUM> and the first power plane <NUM>. The switch <NUM> is controllable by the integrated device <NUM> (e.g., controllable by the first core <NUM> and/or the second core <NUM>). Thus, the switch <NUM> may be turned on and off by the integrated device <NUM>. More power may be shared with the first power plane <NUM> and the first core <NUM> by turning on additional switches, which provides additional electrical paths for power to travel to the first core <NUM>.

<FIG> illustrates an electrical circuit diagram <NUM> for the package <NUM>. The electrical circuit diagram <NUM> includes a first circuit <NUM> and a second circuit <NUM>. The first circuit <NUM> may be an electrical representation of the electrical path <NUM>. The second circuit <NUM> may be an electrical representation of the electrical path <NUM>. The first circuit <NUM> is configured to be electrically coupled to the second circuit <NUM> through at least one switch <NUM>. The first circuit <NUM> may include first interconnects from the board <NUM>, a first power plane <NUM> and the first core <NUM>. The second circuit <NUM> may include second interconnects from the board <NUM>, a second power plane <NUM>, the passive device <NUM>, and the second core <NUM>. The at least one switch <NUM> is part of the second circuit <NUM>, which is located in the substrate <NUM>. The at least one switch <NUM> may be located near the solder interconnects <NUM> (e.g., ball grid array). The at least one switch <NUM> may part of the substrate <NUM> where the passive device <NUM> is coupled to the substrate <NUM>.

<FIG> illustrates an example of the integrated device <NUM> that includes the first core <NUM>, the second core <NUM>, a third core <NUM>, a fourth core <NUM>, a fifth core <NUM>, a sixth core <NUM>, a seventh core <NUM> and an eighth core <NUM>. The first core <NUM> is coupled to the first electrical path <NUM>, which is coupled to a first power resource. The second core <NUM> is coupled to the second electrical path <NUM>, which is coupled to a second power resource. The second power resource is a shareable power resource. The third core <NUM> is coupled to the third electrical path <NUM>, which is coupled to a third power resource. The fourth core <NUM> is coupled to the fourth electrical path <NUM>, which is coupled to a fourth power resource. The second power resource is shareable with the first core <NUM>, the third core <NUM> and/or the fourth core <NUM>. Several switches (e.g., <NUM>) may be used to allow the second power resource to be shareable with the first core <NUM>, the third core <NUM> and/or the fourth core <NUM>.

The fifth core <NUM> is coupled to the fifth electrical path <NUM>, which is coupled to a fifth power resource. The sixth core <NUM> is coupled to the sixth electrical path <NUM>, which is coupled to a sixth power resource. The seventh core <NUM> is coupled to the seventh electrical path <NUM>, which is coupled to a seventh power resource. The eighth core <NUM> is coupled to the eighth electrical path <NUM>, which is coupled to an eighth power resource. The eighth power resource is a shareable power resource. The eighth power resource is shareable with the fifth core <NUM>, the sixth core <NUM> and/or the seventh core <NUM>. Several switches (e.g., <NUM>) may be used to allow the eighth power resource to be shareable with the fifth core <NUM>, the sixth core <NUM> and/or the seventh core <NUM>.

Different implementations may have different numbers of cores with different configurations and designs for the power resources. Any of the cores (e.g., processing cores) may be replaced with a memory (e.g., memory unit). The use of sharing power resources may be applicable between memory and/or cores of an integrated device. (e.g., between two memories, between memory and core of an integrated devices). The use of shareable power resources may be applicable between integrated devices of a package. For example, a power resource that is allocated to be used by a first integrated device may be shared with a second integrated device. The integrated device (e.g., <NUM>, <NUM>, <NUM>) may include a die (e.g., semiconductor bare die). The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filters, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a memory, power management processor, and/or combinations thereof. An integrated device (e.g., <NUM>, <NUM>, <NUM>) may include at least one electronic circuit (e.g., first electronic circuit, second electronic circuit, etc..

<FIG> illustrate a package <NUM> that includes a first integrated device <NUM> and a second integrated device <NUM>. The package <NUM> is similar to the package <NUM> of <FIG> and <FIG>, and thus may include the same components and/or similar components, as the package <NUM>. The first integrated device <NUM> may include at least one core. The second integrated device <NUM> may include at least one core. The first integrated device <NUM> and the second integrated device <NUM> are coupled to the substrate <NUM>. The first integrated device <NUM> is coupled to the substrate <NUM> through the plurality of solder interconnects <NUM>. In some implementations, the first integrated device <NUM> may be coupled to the substrate <NUM> through the plurality of solder interconnects <NUM> and pillar interconnects. The second integrated device <NUM> is coupled to the substrate <NUM> through the plurality of solder interconnects <NUM>. In some implementations, the second integrated device <NUM> may be coupled to the substrate <NUM> through the plurality of solder interconnects <NUM> and pillar interconnects.

<FIG> illustrates exemplary electrical paths in the package <NUM> with the switch <NUM> turned off. As shown in <FIG>, an electrical path <NUM> is coupled to the first integrated device <NUM>, and an electrical path <NUM> is coupled to the second integrated device <NUM>. The electrical path <NUM> (e.g., first electrical path) includes a first solder interconnect from the plurality of solder interconnects <NUM>, a first plurality of interconnects from the plurality of interconnects <NUM> (which includes the first power plane <NUM> (e.g., first power interconnect)), a first solder interconnect from the plurality of solder interconnects <NUM> and the first integrated device <NUM>. The electrical path <NUM> (e.g., second electrical path) includes a second solder interconnect from the plurality of solder interconnects <NUM>, a second plurality of interconnects from the plurality of interconnects <NUM> (which includes the second power plane <NUM> (e.g., second power interconnect)), a second solder interconnect from the plurality of solder interconnects <NUM> and the second integrated device <NUM>. The electrical path <NUM> may also include the passive device <NUM>.

<FIG> illustrates exemplary electrical paths in the package <NUM> with the switch <NUM> turned on. The switch <NUM> may be part of the electrical path <NUM>. The switch <NUM> may be coupled to the plurality of interconnects <NUM>. The switch <NUM> may be coupled to the integrated device <NUM> (e.g., configured to be electrically coupled to the integrated device <NUM> of the integrated device). When/if the switch <NUM> is turned on, some power from the second power resource travelling through the electrical path <NUM> is shared and diverted to the first integrated device <NUM> through the switch <NUM>. Some power from the second power resource may travel through the second power plane <NUM> and the first power plane <NUM>. The switch <NUM> is controllable by the first integrated device <NUM> and/or the second integrated device <NUM>. Thus, the switch <NUM> may be turned on and off by the first integrated device <NUM> and/or the second integrated device <NUM>. More power may be shared with the first power plane <NUM> and the first integrated device740 by turning on additional switches, which provides additional electrical paths for power to travel to the first core <NUM>.

<FIG> illustrates an exemplary flow diagram of a method <NUM> for sharing power resources in a package. The method <NUM> may be implemented by one or more integrated devices. The method <NUM> may be implemented by one or more cores of an integrated devices. For example, the method <NUM> may be implemented by the integrated device <NUM> of the package <NUM>. In another example, the method <NUM> may be implemented by the integrated devices <NUM> and/or <NUM> of the package <NUM>.

The method operates (at <NUM>) one or more cores (e.g., <NUM>, <NUM>) of an integrated device (e.g., <NUM>). Operating one or more cores includes reading and executing instructions. Each core may perform separate and/or different functions. In some implementations, the cores may be part of separate integrated devices. Operating one or more cores may also include utilizing one or more memory.

The method determines (at <NUM>) that at least one core of an integrated device needs and/pr wants more power. Different implementations may have different criteria / criterion for determining whether one or more core needs and/or wants more power. For example, when the amount of power that is provided to a core is less than the maximum allowable power, the method may determine that the core needs and/or wants more power. Whether a core needs more power may mean whether a core wants more power and/or may benefit from more power. For example, a core may need and/or want more power when the core is operating at a lower frequency than the maximum frequency. In some implementations, more than one core may need and/or want more power. In addition to determining that a core may want and/or need more power, the method <NUM> may also determine whether there is available shareable power that is allocated for another core. It is noted that not all power that is allocated to a core is shareable to another core. In some implementations, power allocated to a particular core is shareable with another core, when the particular core is operating at less than maximum capacity and/or the particular core is not being utilized. Thus, even if one or more core may need and/or want more power, there may not be power to share from a power resource allocated to another core.

The method turns on (at <NUM>) at least one switch to share power resource allocated to a particular core to another core of the integrated device. The switch may include a transistor. In some implementations, turning on a switch may include applying a voltage to a gate interconnect of a transistor. In some implementations, the more switches that are turned on the more power is shared with another core of the integrated devices. In some implementations, the number of switches that is turned on may vary in real time. That is, the number of switches that are turned on may be different during different times of the operations of one or more cores of the integrated devices. It is noted that none of the switches may be turned on when there is no available power to share. As mentioned above, in some implementations, even if a core needs and/or wants more power, the method may determine that no additional power is available to be shared from another core. In such instance, the method may not turn on a switch and/or any additional switches. As an example, the method may turn on a first switch and a second switch. The first switch and the second switch are coupled to a first power interconnect and a second power interconnect of a substrate. The first power interconnect may be coupled to a first core and the second power interconnect may be coupled to a second core. Turning on the first switch and the second switch may result in some of the second power resource to travel from the second power interconnect to the first power interconnect through the first switch and the second switch. Thus, some power from a second power resource that is allocated to the second core may be redirected to the first core through the first switch and the second switch. In some implementations, turning on at least one switch includes turning on some switch and/or all switches between two different power interconnects (e.g., power planes).

The method may turn off (at <NUM>) at least one switch to stop sharing power resources and/or reduce the sharing of power resources. The switch may include a transistor. In some implementations, turning off a switch may include stopping a voltage from being applied to a gate interconnect of a transistor. Turning off a particular switch may mean that power may not flow through that particular switch. However, power may still flow between different power interconnects through another switch that is still turned on. In some implementations, the method <NUM> may continually and iteratively check in real time the power requirements of integrated devices and/or cores of integrated devices, and turn on and off one or more switches to provide power resources as needed to the various integrated devices and/or the various cores of integrated devices. The criteria / criterion for determining whether or not an integrated device (e.g., core of an integrated device) needs and/or wants additional power may vary with different implementations. Examples of what may be used to determine whether more power is needed for an integrated device is the strength of the voltage, the strength of the current of the power that is provided to the integrated devices, and/or the operating frequency of the core(s).

For example, the method <NUM> may operate an integrated device that includes a first core and a second core, where a first power resource is directed to the first core and a second power resource is directed to the second core. The method <NUM> may determine that the first core of the integrated device needs and/or wants more power. The method <NUM> may turn on at least one switch to reroute some of the second power resource to the first core of the integrated device (when there is available power from the second power resource). In some implementations, turning on at least one switch includes turning on some but not all of the switches coupled between a first power interconnect coupled to the first core and a second power interconnect coupled to the second core. The method <NUM> may further determine that the first core of the integrated device does not need more power (e.g., does not need all the power than is provided by the first power resource and some power from the second power resource). The method <NUM> may turn off the at least one switch to stop the rerouting of some of the second power resource to the first core of the integrated device. The method <NUM> may further determine that the first core of the integrated device needs further power (e.g., needs further power than what is already provided by the first power resource and some power from the second power resource). The method <NUM> may turn on more or all of the switches coupled between the first power interconnect coupled to the first core and the second power interconnect coupled to the second core, to reroute more of the second power resource to the first core of the integrated device.

The method <NUM> may be applicable to cores of the same integrated device, cores of different integrated devices and/or different integrated devices. The method <NUM> may also be applicable to memories of an integrated devices (e.g., between two memories, between a memory and a core of an integrated device). Thus, one or more core as described above in <FIG> may be applicable to one memory. The method <NUM> may be applicable to two or more integrated devices.

For example, the method <NUM> may operate a first integrated device and a second integrated device, where a first power resource is directed to the first integrated device and a second power resource is directed to the second integrated device. The method <NUM> may determine that the first integrated device needs and/or wants more power. The method <NUM> may turn on at least one switch to reroute some of the second power resource to the first integrated device. In some implementations, turning on at least one switch includes turning on some but not all of the switches coupled between a first power interconnect coupled to the first integrated device and a second power interconnect coupled to the second integrated device. The method <NUM> may further determine that the first integrated device does not need more power (e.g., does not need all the power than is provided by the first power resource and some power from the second power resource). The method <NUM> may turn off the at least one switch to stop the rerouting of some of the second power resource to the first integrated device. The method <NUM> may further determine that the first integrated device needs further power (e.g., needs further power than what is already provided by the first power resource and some power from the second power resource). The method <NUM> may turn on more or all of the switches coupled between the first power interconnect coupled to the first integrated device and the second power interconnect coupled to the second integrated device, to reroute more of the second power resource to the first integrated device.

In some implementations, fabricating a substrate includes several processes. <FIG> illustrate an exemplary sequence for providing or fabricating a substrate that includes a switch for sharing power resources. In some implementations, the sequence of <FIG> may be used to provide or fabricate the substrate <NUM> that includes at least one switch.

It should be noted that the sequence of <FIG> may combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted.

Stage <NUM>, as shown in <FIG>, illustrates a state after a carrier <NUM> is provided and a metal layer is formed over the carrier <NUM>. The metal layer may be patterned to form interconnects <NUM>. A plating process may be used to form the metal layer and interconnects. Some of the interconnects <NUM> may define a gate interconnect <NUM>, a source interconnect <NUM> and/or a drain interconnect <NUM>.

Stage <NUM> illustrates a state after a dielectric layer <NUM> is formed over the carrier <NUM> and the interconnects. The dielectric layer <NUM> may include polyimide. A deposition process may be used to form the dielectric layer <NUM>.

Stage <NUM> illustrates a state after a gate dielectric layer <NUM> is formed over the interconnect <NUM>. A deposition process may be used to form the gate dielectric layer <NUM>. Different implementations may use different materials for the gate dielectric layer <NUM>. For example, the gate dielectric layer <NUM> may include HfO<NUM> (hafnium oxide), SiO<NUM> (silicon dioxide) Al<NUM>O<NUM> (aluminum oxide) and/or combinations thereof.

Stage <NUM> illustrates a state after portions of the gate dielectric layer <NUM> are removed. Removing portions of the gate dielectric layer <NUM> may reveal the source interconnect <NUM> and the drain interconnect <NUM>. The source interconnect <NUM> and the drain interconnect <NUM> may be formed from portions of the interconnects <NUM>.

Stage <NUM> illustrates a state after a channel <NUM> is formed over the gate dielectric layer <NUM>, the source interconnect <NUM> and the drain interconnect <NUM>. Different implementations may use different materials for the channel <NUM>. The channel <NUM> may include polycrystalline SiGe (silicon germanium), CdSe (Cadmium selenide), IgZo (indium gallium zinc oxide), tungsten (W)-Doped In<NUM>O<NUM> (indium oxide) and/or combinations thereof. The materials that are used for the channel <NUM> may be formed using low temperatures (e.g., less than <NUM> Celsius). Stage <NUM> may illustrate a switch <NUM> that includes a gate interconnect <NUM>, a source interconnect <NUM>, a drain interconnect <NUM>, a gate dielectric layer <NUM> and a channel <NUM>. The switch <NUM> may be configured as a transistor.

Stage <NUM> illustrates a state after a dielectric layer <NUM> is formed over the carrier <NUM>, the switch <NUM> and the interconnects <NUM>. The dielectric layer <NUM> may include polyimide. However, different implementations may use different materials for the dielectric layer <NUM>. The dielectric layer <NUM> may include the dielectric layer <NUM>. A deposition process may be used to form the dielectric layer <NUM>.

Stage <NUM>, as shown in <FIG>, illustrates a state after a plurality of cavities <NUM> is formed in the dielectric layer <NUM>. The plurality of cavities <NUM> may be formed using an etching process or laser process.

Stage <NUM> illustrates a state after interconnects <NUM> are formed in and over the dielectric layer <NUM>. For example, a via, pad and/or traces may be formed. A plating process may be used to form the interconnects.

Stage <NUM> illustrates a state after another dielectric layer <NUM> is formed over the dielectric layer <NUM>. A deposition process may be used to form the dielectric layer <NUM>.

Stage <NUM>, as shown in <FIG>, illustrates a state after a cavity <NUM> is formed in the dielectric layer <NUM>. An etching process or laser process may be used to form the cavities <NUM>.

Stage <NUM> illustrates a state after interconnects <NUM> are formed in and over the dielectric layer <NUM>. For example, via, pad and/or trace may be formed. A plating process may be used to form the interconnects.

Stage <NUM> illustrates after the carrier <NUM> is decoupled (e.g., removed, grinded out) from the dielectric layer <NUM>, leaving the substrate <NUM> (e.g., coreless substrate). In some implementation, the coreless substrate is an embedded trace substrate (ETS). Stage <NUM> illustrates the substrate <NUM> that includes the dielectric layer <NUM>, the dielectric layer <NUM>. In some implementations, the dielectric layer <NUM> and the dielectric layer <NUM> may be considered as one dielectric layer (e.g., single dielectric layer). The substrate <NUM> includes the plurality of interconnects <NUM>, the plurality of interconnects <NUM>, and the plurality of interconnects <NUM>. The plurality of interconnects <NUM>, the plurality of interconnects <NUM>, and the plurality of interconnects <NUM> may be represented by the plurality of interconnects <NUM>. Some of the interconnects from the substrate <NUM> may be configured as power interconnects (e.g., power planes) as described in the disclosure.

Different implementations may use different processes for forming the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and/or a physical vapor deposition (PVD) process for forming the metal layer(s). For example, a sputtering process, a spray coating process, and/or a plating process may be used to form the metal layer(s).

<FIG> illustrates an exemplary flow diagram of a method <NUM> for providing or fabricating a substrate with a switch. In some implementations, the method <NUM> of <FIG> may be used to provide or fabricate the substrate of <FIG>. For example, the method of <FIG> may be used to fabricate the substrate <NUM>.

It should be noted that the sequence of <FIG> may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified.

The method provides (at <NUM>) a carrier <NUM>. The method forms (at <NUM>) a metal layer over the carrier <NUM>. The metal layer may be patterned to form interconnects <NUM>. Some of the interconnects <NUM> may define a gate interconnect <NUM>, a source interconnect <NUM> and/or a drain interconnect <NUM>. A plating process may be used to form the metal layer and interconnects. A dielectric layer may be formed after the interconnects <NUM> are formed. Stage <NUM> of <FIG> illustrates and describes an example of providing a carrier and forming interconnects.

The method forms (at <NUM>) at least one switch <NUM> that includes a gate dielectric layer <NUM> and a channel <NUM>. One or more deposition process may be used to form the gate dielectric layer <NUM> and the channel <NUM>. The gate dielectric layer <NUM> may include HfO<NUM> (hafnium oxide), SiO<NUM> (silicon dioxide) Al<NUM>O<NUM> (aluminum oxide) and/or combinations thereof. The channel <NUM> may include polycrystalline SiGe (silicon germanium), CdSe (Cadmium selenide), IgZo (indium gallium zinc oxide), tungsten (W)-Doped In<NUM>O<NUM> (indium oxide) and/or combinations thereof. In some implementations, the source interconnect <NUM> and/or the drain interconnect <NUM> may be doped. The switch may include a transistor. Stages <NUM>-<NUM> of <FIG> illustrate and describe an example of forming a channel and a gate dielectric layer.

The method forms (at <NUM>) a dielectric layer <NUM> over the carrier <NUM>, the interconnects <NUM> and the switch <NUM>. The dielectric layer <NUM> may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., <NUM>) in the dielectric layer <NUM>. The plurality of cavities may be formed using an etching process or laser process. Stage 56of <FIG> and stage <NUM> of <FIG> illustrates and describes an example of forming a dielectric layer and cavities.

The method forms (at <NUM>) interconnects in and over the dielectric layer. For example, the interconnects <NUM> may formed. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer over and/or in the dielectric layer. Stage <NUM> of <FIG> illustrates and describes an example of forming an interconnect.

The method forms (at <NUM>) a dielectric layer <NUM> over the dielectric layer <NUM> and the interconnects <NUM>. The dielectric layer <NUM> may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., <NUM>) in the dielectric layer <NUM>. The plurality of cavities may be formed using an etching process or laser process. Stage <NUM> of <FIG> and stage <NUM> of <FIG> illustrate and describe examples of forming a dielectric layer and a cavity.

The method forms (at <NUM>) interconnects in and/or over the dielectric layer. For example, the interconnects <NUM> may be formed. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer over an in the dielectric layer. Stage <NUM> of <FIG> illustrates and describes examples of forming interconnects.

The method may form additional dielectric layer(s) and additional interconnects as described at <NUM> and <NUM>.

Once all the dielectric layer(s) and additional interconnects are formed, the method may decouple (e.g., remove, grind out) the carrier (e.g., <NUM>) from the dielectric layer <NUM>, leaving the substrate. In some implementation, the coreless substrate is an embedded trace substrate (ETS). Stage <NUM> of <FIG> illustrates and describes an example after a substrate is decoupled from a carrier.

<FIG> illustrates various electronic devices that may be integrated with any of the aforementioned device, integrated device, integrated circuit (IC) package, integrated circuit (IC) device, semiconductor device, integrated circuit, die, interposer, package, package-on-package (PoP), System in Package (SiP), or System on Chip (SoC). For example, a mobile phone device <NUM>, a laptop computer device <NUM>, a fixed location terminal device <NUM>, a wearable device <NUM>, or automotive vehicle <NUM> may include a device <NUM> as described herein. The device <NUM> may be, for example, any of the devices and/or integrated circuit (IC) packages described herein. The devices <NUM>, <NUM>, <NUM> and <NUM> and the vehicle <NUM> illustrated in <FIG> are merely exemplary. Other electronic devices may also feature the device <NUM> including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, processes, features, and/or functions illustrated in <FIG>, <FIG>, and/or <FIG> may be rearranged and/or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be noted <FIG>, <FIG>, and/or <FIG> and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations, <FIG>, <FIG>, and/or <FIG> and its corresponding description may be used to manufacture, create, provide, and/or produce devices and/or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipating device and/or an interposer.

It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.

One or more processors (e.g., core, integrated device) in the processing system may execute software. The software may reside on a computer-readable medium.

The computer-readable medium may be a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium may reside in a processing system, external to the processing system, or distributed across multiple entities including the processing system. The computer-readable medium may be embodied in a computer program product. In some examples, the computer-readable medium may be part of a memory. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The term "coupled" is used herein to refer to the direct or indirect coupling (e.g., mechanical coupling) between two objects. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The use of the terms "first", "second", "third" and "fourth" (and/or anything above fourth) is arbitrary. Any of the components described may be the first component, the second component, the third component or the fourth component. For example, a component that is referred to a second component, may be the first component, the second component, the third component or the fourth component. The term "encapsulating" means that the object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component that is located on top may be located over a component that is located on a bottom. A top component may be considered a bottom component, and vice versa. As described in the disclosure, a first component that is located "over" a second component may mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located over (e.g., above) a first surface of the second component, and a third component may be located over (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is further noted that the term "over" as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (<NUM>) the first component is over the second component, but not directly touching the second component, (<NUM>) the first component is on (e.g., on a surface of) the second component, and/or (<NUM>) the first component is in (e.g., embedded in) the second component. A first component that is located "in" a second component may be partially located in the second component or completely located in the second component. The term "about 'value X'", or "approximately value X", as used in the disclosure means within <NUM> percent of the 'value X'. For example, a value of about <NUM> or approximately <NUM>, would mean a value in a range of <NUM>-<NUM>.

In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and/or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground and/or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and/or sequences for forming the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.

Also, it is noted that various disclosures contained herein may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. A process is terminated when its operations are completed.

The following aspects are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

Aspect <NUM>: A package comprising an integrated device and a substrate coupled to the integrated device. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device; a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device; and a switch coupled to the first power interconnect and the second power interconnect, wherein if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

Aspect <NUM>: The package of aspect <NUM>, wherein if the switch is turned off, the switch is configured such that the power from the second power resource does not contribute to the first core through the switch.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the switch includes at least one transistor.

Aspect <NUM>: The package of aspect <NUM>, wherein the at least one transistor comprises a source interconnect, a drain interconnect, a channel, and a gate interconnect.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the first power interconnect includes a first power plane, and wherein the second power interconnect includes a second power plane.

Aspect <NUM>: The package of aspect <NUM>, wherein the first power plane and the second power plane are located on a same metal layer of the substrate.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the switch is configured to be controlled by the integrated device.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, further comprising a second switch coupled to the first power interconnect and the second power interconnect, wherein if the second switch is turned on, the second switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the integrated device further comprises a third core, wherein the substrate further comprises: a third power interconnect configured to provide a third electrical path for a third power resource to the third core of the integrated device; and a second switch coupled to the third power interconnect and the second power interconnect, wherein if the second switch is turned on, the second switch is configured to enable at least some of the power resource from the second power resource to contribute to the third core of the integrated device.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the first power resource and the second power resource are part of a power grid resource that is configured to be coupled to one or more power management integrated devices.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the first power resource includes a first electrical current from a power management integrated device, and wherein the second power resource includes a second electrical current from the power management integrated device.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the integrated device is configured to: determine whether the first core of the integrated device needs more power; and if it is determined that the first core needs more power, turn on the switch to reroute some of the second power resource to the first core of the integrated device.

Aspect <NUM>: The package of aspect <NUM>, wherein the integrated device is further configured to: determine whether the first core of the integrated device does not need more power; and if it is determined that the first core does not need more power, turn off the switch to stop the rerouting of some of the second power resource to the first core of the integrated device through the switch.

Aspect <NUM>: The package of aspect <NUM>, wherein the integrated device is further configured to: determine whether the first core of the integrated device needs further power; and if it is determined that the first core needs further power, turn on a second switch coupled between the first power interconnect coupled to the first core and the second power interconnect coupled to the second core, to reroute more of the second power resource to the first core of the integrated device.

Aspect <NUM>: A package comprising: a first integrated device; a second integrated device; and a substrate coupled to the first integrated device and the second integrated device, the substrate comprising: a first power interconnect configured to provide a first electrical path for a first power resource to the first integrated device; and a second power interconnect configured to provide a second electrical path for a second power resource to the second integrated device; and a switch coupled to the first power interconnect and the second power interconnect, wherein if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first integrated device.

Aspect <NUM>: The package of aspect <NUM>, wherein if the switch is turned off, the switch is configured such that the power from the second power resource does not contribute to the first integrated device through the switch.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the switch is configured to be controlled by the first integrated device and/or the second integrated device.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the first integrated device is configured to: determine whether the integrated device needs more power; and if it is determined that the first integrated device needs more power, turn on the switch to reroute some of the second power resource to the first integrated device.

Aspect <NUM>: The package of aspect <NUM>, wherein the first integrated device is further configured to: determine whether the first integrated device does not need more power; and if it is determined that the first integrated device does not need more power, turn off the switch to stop the rerouting of some of the second power resource to the first integrated device through the switch.

Aspect <NUM>: The package of aspect <NUM>, wherein the first integrated device is further configured to: determine whether the first integrated device needs further power; and if it is determined that the first integrated device needs further power, turn on a second switch coupled between the first power interconnect coupled to the first integrated device and the second power interconnect coupled to the second integrated device, to reroute more of the second power resource to the first integrated device.

Aspect <NUM>: The package of aspects <NUM> through <NUM>, wherein the package is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.

Aspect <NUM>: A method comprising: operating an integrated device that includes a first core and a second core, wherein a first power resource is directed to the first core and a second power resource is directed to the second core; determining that the first core of the integrated device needs more power; and turning on at least one switch to reroute some of the second power resource to the first core of the integrated device.

Aspect <NUM>: The method of aspect <NUM>, further comprising: determining that the first core of the integrated device does not need more power; and turning off the at least one switch to stop the rerouting of some of the second power resource to the first core of the integrated device through the at least one switch.

Aspect <NUM>: The method of aspects <NUM> through <NUM>, wherein turning on at least one switch includes turning on some but not all of the switches coupled between a first power interconnect coupled to the first core and a second power interconnect coupled to the second core.

Aspect <NUM>: The method of aspect <NUM>, further comprising: determining that the first core of the integrated device needs further power; and turning on all of the switches coupled between the first power interconnect coupled to the first core and the second power interconnect coupled to the second core, to reroute more of the second power resource to the first core of the integrated device through the at least one switch.

Aspect <NUM>: The method of aspects <NUM> through <NUM>, wherein the first power resource and the second power resource travel through a power management integrated device.

Aspect <NUM>: A method comprising: operating a first integrated device, wherein a first power resource is directed to the first integrated device; operating a second integrated device, wherein a second power resource is directed to the second integrated device; determining that the first integrated device needs more power; and turning on at least one switch to reroute some of the second power resource to the first integrated device through the at least one switch.

Aspect <NUM>: The method of aspect <NUM>, further comprising: determining that the first integrated device does not need more power; and turning off the at least one switch to stop the rerouting of some of the second power resource to the first integrated device through the at least one switch.

Aspect <NUM>: The method of aspects <NUM> through <NUM>, wherein turning on at least one switch includes turning on some but not all of the switches coupled between a first power interconnect coupled to the first integrated device and a second power interconnect coupled to the second integrated device.

Aspect <NUM>: The method of aspect <NUM>, further comprising: determining that the first integrated device needs further power; and turning on all of the switches coupled between the first power interconnect coupled to the first integrated device and the second power interconnect coupled to the second integrated device, to reroute more of the second power resource to the first integrated device through the at least one switch.

Claim 1:
A package (<NUM>) comprising:
an integrated device (<NUM>) comprising:
a first core (<NUM>); and
a second core (<NUM>); and
a substrate (<NUM>) coupled to the integrated device (<NUM>), the substrate (<NUM>) comprising:
a first power interconnect configured to provide a first electrical path (<NUM>) for a first power resource to the first core (<NUM>) of the integrated device (<NUM>);
a second power interconnect configured to provide a second electrical path (<NUM>) for a second power resource to the second core (<NUM>) of the integrated device (<NUM>); and
a switch (<NUM>) coupled to the first power interconnect and the second power interconnect, wherein if the switch (<NUM>) is turned on, the switch (<NUM>) is configured to enable at least some of the power resource from the second power resource to contribute to the first core (<NUM>) of the integrated device (<NUM>).