Patent Description:
With graphics intensive applications, memory bandwidth represents a significant constraint. Displays featuring Panel Self-Refresh (PSR) capability are equipped with local frame buffers that can be used to provide frame replays. PSR version <NUM> (PSR2) adds the capability to perform a selective update of specific portions of the display area. Displays equipped with active synchronization technology provide variable vertical blanking duration determined based on the availability of data for the subsequent frame - providing for a variable refresh rate. Current systems provide Adaptive Synchronization to achieve low latency and provide performance benefits in graphics intensive applications where frame rendering may vary. Thus, Adaptive Synchronization systems assist in minimizing tearing and judder effects typically seen on displays having a fixed refresh rate. Panel Self-Refresh technology is typically implemented on systems to reduce power consumption of the device.

From <CIT> an apparatus is known for implementing a display port interface. The apparatus may include a source processor and a sink processor coupled through an interface. The sink processor may be operable to send a synchronization signal to the source processor through the interface. The source processor may be operable, dependent upon the synchronization signal, to send data to the sink processor.

In <CIT>, a method of controlling the sparse refresh of a self-refreshing display device coupled to a graphics controller is described.

Features and advantages of various embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals designate like parts, and in which:.

The systems and methods described herein provide systems and methods that take advantage of both: the power saving benefits associated with Panel Self-Refresh (PSR) and the performance benefits of a display device using adaptive synchronization. Panel Self-Refresh (PSR) makes use of a frame buffer disposed in the display device to store image data. When the graphics control circuitry determines that the display image is unchanging, the graphics control circuitry enters a PSR operating mode in which the display device uses the image data stored in the frame buffer. Since the graphics control circuitry no longer generates frame data, the relatively high bandwidth communications link between the graphics control circuitry and the display device may be placed in a standby mode, beneficially reducing power consumption of the device. PSR with selective update (PSR2) adds the capability to selectively update portions of the display image while in the PSR operating mode.

Adaptive synchronization is a technology included in display control circuitry that attempts to match the detected frame generation rate of the graphics control circuitry to the frame refresh rate of the display device. In operation, adaptive synchronization adjusts determines the duration of vertical blanking associated with each frame based on the availability of data associated with the next frame. Entry into the PSR/PSR2 operating mode tends to disrupt the synchronization between the graphics control circuitry and the display device control circuitry. The disruption of synchronization between the graphics control circuitry and the display device control circuitry has heretofore precluded the contemporaneous use of both PSR/PSR2 and adaptive synchronization technologies on a single system.

The systems and methods disclosed herein beneficially provide for the implementation of a PSR/PSR2 operating mode on a system including a display featuring adaptive synchronization technology. The systems and methods disclosed herein either maintain graphics control circuitry/display control circuitry synchronization when in the PSR/PSR2 operating mode or re-establish synchronization upon exiting the PSR/PSR2 operating mode. The systems and methods described herein maintain frame-level synchronization between a source device and an adaptive sync sink device when in PSR/PSR2 operating mode using AUX_FRAME_SYNC to maintain GTC-based synchronization using sideband (AUX) transactions. The systems and methods described herein maintain frame-level synchronization between a source device and an adaptive sync sink device when in PSR/PSR2 operating mode using bidirectional FS_HDP. The systems and methods described herein maintain frame-level synchronization between a source device and an adaptive sync sink device when in PSR/PSR2 operating mode using AUX_FRAME_SYNC to maintain GTC-based synchronization using sideband (AUX) transactions. The systems and methods described herein maintain frame-level synchronization between a source device and an adaptive sync sink device when in PSR/PSR2 operating mode using one or more secondary sideband communication pathways, such as one or more in-silicon communication pathways using a SoC architecture. The systems and methods described herein maintain frame-level synchronization between a source device and an adaptive sync sink device when in PSR/PSR2 operating mode using GTC-based presentation time stamps. The systems and methods described herein maintain frame- or line-level synchronization between a source device and an adaptive sync sink device when in PSR/PSR2 by communicating line and/or frame timing markers (BSBE) via high-bandwidth connection between the source device and the sink device. The systems and methods described herein maintain frame- or line-level synchronization between a source device and an adaptive sync sink device when in PSR/PSR2 by storing, in the sink device a value indicative of the number of frames required for the sink device to re-synchronize timing upon exiting PSR/PSR2 operating mode.

A data transmission system is provided. The system may include: a source device comprising: high-bandwidth transmitter circuitry; sideband transceiver circuitry; control circuitry to: generate a plurality of frames at one or more frame generation rates; provide the plurality of frames to the high-bandwidth transmitter circuitry; disable at least the high-bandwidth transmitter circuitry responsive to entering a Panel Self-Refresh (PSR) operating mode; synchronize the source device and the sink device responsive to exiting the PSR operating mode; and adjust, by the sink device control circuitry. The system may additionally include: high-bandwidth receiver circuitry to receive the plurality of frames from the source device; sideband transceiver circuitry communicatively coupled to the source device sideband transceiver circuitry; memory circuitry; control circuitry to: cause a storage of at least one frame included in the plurality of frames in the memory circuitry; and adjust a refresh rate of a communicatively coupled display device to the frame generation rate of the source device.

A data transmission method is provided. The method may include: generating, by source device graphics circuitry, a plurality of frames at one or more frame generation rates; providing, by source device control circuitry, each of the plurality of frames to high-bandwidth transmitter circuitry; disabling, by the source device control circuitry, at least the high-bandwidth transmitter circuitry responsive to entering a Panel Self-Refresh (PSR) operating mode; causing, by sink device control circuitry, a storage of at least one frame included in the plurality of frames in sink device memory circuitry; temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode; and adjusting, by the sink device control circuitry, a refresh rate of a communicatively coupled display device to the frame generation rate of the source device.

A non-transitory storage device is provided. The non-transitory storage device may include instructions that, when executed by circuitry, causes the control circuitry to: cause graphics circuitry to generate a plurality of frames at one or more frame generation rates; provide each of the plurality of frames to high-bandwidth transmitter circuitry; and disable at least the high-bandwidth transmitter circuitry responsive to entering a Panel Self-Refresh (PSR) operating mode; cause a storage of at least one frame included in the plurality of frames in sink device memory circuitry; temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode; and adjust a refresh rate of a communicatively coupled display device to the frame generation rate of the source device.

As used herein the terms "high-bandwidth" and "low-bandwidth" are relative terms to indicate a relatively high-speed communication pathway (e.g., a "high-bandwidth" or a communication pathway having a high data transfer rate relative to the low-bandwidth communication pathway) and a relatively low-speed communication pathway (e.g., a "low-bandwidth" or a communication pathway having a low data transfer rate relative to the high-bandwidth communication pathway).

<FIG> is a block diagram of an illustrative system <NUM> that includes a source device <NUM> with control circuitry <NUM> having instructions <NUM> capable of placing the system <NUM> in a Panel Self-Refresh (PSR) or PSR with Selective Update (PSR2) operating mode and s sink device <NUM> with control circuitry <NUM> having instructions <NUM> that implement adaptive synchronization win a communicatively coupled display device <NUM>, in accordance with at least one embodiment described herein. A high-bandwidth communications link <NUM> bidirectionally communicatively couples a high-bandwidth transmitter circuit <NUM> in the source device <NUM> with a high-bandwidth receiver circuit <NUM> in the sink device <NUM>. A low-bandwidth communications link <NUM> communicably couples a side-channel transceiver circuit <NUM> in the source device <NUM> with a side-channel transceiver circuit <NUM> in the sink device <NUM>.

The source device <NUM> includes graphics circuitry <NUM>, high-bandwidth transmitter circuitry <NUM>, side-channel transceiver circuitry <NUM>, and the control circuitry <NUM>. The control circuitry <NUM> may include one or more instructions and/or instruction sets capable of placing the system <NUM> in a PSR/PSR2 operating mode. When in the PSR/PSR2 operating mode, in some embodiments, when in the PSR/PSR2 operating mode, the control circuitry <NUM> may place the high-bandwidth transmitter circuit <NUM>, high-bandwidth receiver circuit <NUM>, and the high-bandwidth communications link <NUM> in a standby or other low power consumption mode.

The sink device <NUM> includes control circuitry <NUM>, memory circuitry <NUM>, one or more display devices <NUM>, the high-bandwidth receiver circuit <NUM>, and the side-channel transceiver circuitry <NUM>. In embodiments, the sink device control circuitry <NUM> may execute adaptive synchronization instructions <NUM> that adjust the vertical blanking (VB) interval between display image frames to match the frame rate of the display device <NUM> to the frame generation rate of the graphics circuitry <NUM>. The memory circuitry <NUM> may include frame buffer circuitry <NUM> and may also include one or more register circuits <NUM> to store data.

In operation, the graphics circuitry <NUM> generates a sequence containing a plurality of frames 132A-132n (collectively, "frames <NUM>"). Each of the frames <NUM> is communicated to the sink device <NUM> via the high-bandwidth communications link <NUM>. In embodiments, each of the frames <NUM> may include data representative of a display image for presentation by the display device <NUM>. In embodiments, the graphics circuitry <NUM> may generate the frames at a fixed rate (e.g., <NUM> frames per second - "fps") or at a variable rate (e.g., between <NUM> fps and <NUM> fps) dependent on the frame content, frame complexity and/or frame computational demand placed on the graphics circuitry <NUM>. Where the display image data in consecutive frames <NUM> remains unchanged or minimally changed, the graphics circuitry <NUM> may place the system <NUM> in a PSR/PSR2 operational mode that: stores image data carried by a current frame 132A in the frame buffer <NUM> of the sink memory circuitry <NUM> and replays the display image stored in the frame buffer <NUM> on the display device <NUM> until the graphics circuitry <NUM> exits the PSR/PSR2 operating mode. In the PSR/PSR2 operating mode, the control circuitry <NUM> causes the high-bandwidth transmitter circuit <NUM>, the high-bandwidth receiver circuit <NUM>, and the high-bandwidth communications link <NUM> to enter a standby or similar low power consumption mode.

Within the sink device <NUM>, the sink control circuitry <NUM> causes the display device <NUM> to sequentially present the image data included in each of the frames <NUM>. A VB interval temporally separates each of the frames 132A-132n. In embodiments, the VB interval is a variable temporal interval continuously, selectively adjustable between a minimum value and a maximum value by the sink control circuitry <NUM>. In embodiments, the sink control circuitry <NUM> may execute adaptive synchronization instructions <NUM> that selectively adjust the VB interval such that the frame display rate of the sink device <NUM> matches the frame generation rate of the source device <NUM>. However, when the source control circuitry <NUM> places the system <NUM> in PSR/PSR2 operating mode, the timing data that synchronizes the frame transfers from the source device <NUM> to the sink device <NUM> may be lost.

In some embodiments, synchronization between the source device <NUM> and the sink device <NUM> may be maintained through the duration of the PSR/PSR2 operating mode. In other embodiments, synchronization between the source device <NUM> and the sink device <NUM> may be interrupted and at least one of the source device <NUM> and/or the sink device <NUM> may store information and/or data used to resynchronize the source device <NUM> with the sink device <NUM> upon exiting the PSR/PSR2 operating mode.

The source device <NUM> may include any number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of generating a plurality of frames 132A-132n and communicating the frames <NUM> to the sink device <NUM>. In embodiments, the source device <NUM> may include a System-on-Chip (SoC) or similar semiconductor device architecture. In embodiments, some or all of the graphics circuitry <NUM>, source control circuitry <NUM>, high-bandwidth transmitter circuitry <NUM>, and the side-channel transceiver circuitry <NUM> may included integrated circuit chiplets that together form a SoC. In embodiments, the source device <NUM> may form at least a portion of a portable computing device, such as a smartphone, wearable computer, portable computer, laptop computer, or similar.

The graphics circuitry <NUM> may include any number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of generating image data for communication to the sink device <NUM> via the plurality of frames 132A-132n. In at least some embodiments, the graphics circuitry <NUM> may include a graphics processing unity (GPU) or similar. In embodiments, the graphics circuitry <NUM> may include any number and/or combination of processing units, microprocessors, vector or tensor mathematical units, accelerators, and the like.

The source control circuitry <NUM> may include number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of executing a PSR/PSR2 instruction set <NUM> that causes the system <NUM> to enter/exit a PSR/PSR2 operating mode. In at least some embodiments, the high-bandwidth communications link <NUM>, the high-bandwidth transmitter circuit <NUM>, and/or the high-bandwidth receiver circuit <NUM> may be placed in a standby or low power consumption operating mode for at least a portion of the duration of the PSR/PSR2 operating mode. In embodiments, the source control circuitry <NUM> may maintain temporal synchronization with the sink control circuitry <NUM> contemporaneous with at least a portion of the duration of the PSR/PSR2 operating mode.

The high-bandwidth transmitter circuit <NUM> may include any number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of communicating relatively high-bandwidth signals that include image data generated by the graphics circuitry <NUM> to the sink device <NUM> via the high-bandwidth communications link <NUM>. In embodiments, the high-bandwidth transmitter circuit <NUM> may include a high-bandwidth transceiver. In embodiments, the high-bandwidth transmitter circuit <NUM> may include DisplayPort compliant transceiver circuitry.

The side-channel transceiver circuitry <NUM> may include any number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of communicating relatively low bandwidth signals that include commands, control, and/or timing data generated by the source control circuitry <NUM> to the sink device <NUM> via the low-bandwidth communications link <NUM>. In embodiments, the graphics circuitry <NUM>, the control circuitry <NUM>, the high-bandwidth transmitter circuit <NUM>, and the side-channel transceiver circuitry <NUM> may be communicatively coupled to each other via one or more communications structures, busses, or similar.

The sink device <NUM> may include one or more display systems that include but are not limited to one or more light emitting diode (LED) display systems, one or more liquid crystal display (LCD) systems, one or more organic LED (OLED) systems; one or more polymer LED (PLED) systems, one or more transparent OLED (TOLED) systems, or similar. In some embodiments, the source device <NUM> and the sink device <NUM> may be disposed in a common enclosure or housing - such as a smartphone, portable computer, or wearable computer. In other embodiments, the source device <NUM> may be tethered to the sink device <NUM> via one or more serial busses or one or more parallel busses.

The sink control circuitry <NUM> may include number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of executing an adaptive synchronization instruction set <NUM> that adjusts the VB interval of the display device <NUM> to synchronize the frame rate of the display device <NUM> to the frame generation rate of the source device <NUM>. In embodiments, the sink control circuitry <NUM> may implement adaptive synchronization contemporaneous with the source control circuitry <NUM> placing the system in a PSR/PSR2 operating mode. In one or more embodiments, temporal synchronization between the source device <NUM> and the sink device <NUM> may be maintained throughout all or a portion of the PSR/PSR2 operating mode. In one or more embodiments, temporal synchronization between the source device <NUM> and the sink device <NUM> may be interrupted during at least a portion of the PSR/PSR2 operating mode and re-established after the system <NUM> exits the PSR/PSR2 operating mode.

The sink memory circuitry <NUM> may include number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of storing frame data in one or more frame buffer circuits <NUM>. In embodiments, the frame data stored in the one or more frame buffer circuits <NUM> may be presented by the display device <NUM> when the sink device <NUM> is placed in PSR/PSR2 operating mode by the source control circuitry <NUM>. In embodiments, the sink memory circuitry <NUM> may have any storage capacity. For example, the sink memory circuitry <NUM> may have a capacity of <NUM> Megabytes (MB) or greater; 500MB or greater; <NUM> Gigabyte (GB) or greater; 5GB or greater; 10GB or greater; 50GB or greater; or 100GB or greater. The sink memory circuitry <NUM> may include one or more register circuits <NUM> to store information and/or data.

The high-bandwidth receiver circuit <NUM> may include any number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of receiving relatively high-bandwidth signals that include image data generated by the graphics circuitry <NUM> via the high-bandwidth communications link <NUM>. In embodiments, the high-bandwidth receiver circuit <NUM> may include a high-bandwidth transceiver. In embodiments, the high-bandwidth receiver circuit <NUM> may include DisplayPort compliant transceiver circuitry.

The side-channel transceiver circuitry <NUM> may include any number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor devices, and/or logic elements capable of bi-directionally communicating relatively low bandwidth signals that include commands, control, and/or timing data generated by the sink control circuitry <NUM> to the source device <NUM> via the low-bandwidth communications link <NUM>. In embodiments, the control circuitry <NUM>, the memory circuitry <NUM>, the high-bandwidth receiver circuit <NUM>, the side-channel transceiver circuitry <NUM>, and the display device <NUM> may be communicatively coupled to each other via one or more communications structures, busses, or similar.

<FIG> is a timing diagram <NUM> depicting an illustrative system in a "Panel Replay Mode" in which the sink device <NUM> includes adaptive synchronization, in accordance with at least one embodiment described herein. In embodiments, temporal synchronization between the source device <NUM> and the sink device <NUM> may be maintained during all or a portion of the PSR/PSR2 operating mode. In the Panel Replay Mode, the source device <NUM> controls the display timing and temporal synchronization between the source device <NUM> and the sink device <NUM>. <FIG> also depicts the variable VB interval used by the sink device <NUM> to synchronize to the source device <NUM>. As depicted in <FIG>, the source device <NUM> generates Frame <NUM> (<NUM>), Frame <NUM> (<NUM>), Frame <NUM> (<NUM>), and Frame <NUM> (<NUM>), each of which may be rendered at different frame rates. The sink device <NUM> attempts to match the frame generation rate of the source <NUM> by varying the VB interval <NUM> associated with each image display frame. The source device <NUM> requires an extended time Frame <NUM> (<NUM>). While the source is generating Frame <NUM> (<NUM>), the sink device <NUM> displays Frame <NUM> (212A) and waits the maximum VB interval 260B. When Frame <NUM> is not available to the sink device <NUM> after the maximum VB Interval 260B, the sink device <NUM> again displays Frame <NUM> (212B). Frame <NUM> (<NUM>) becomes available while the sink device <NUM> is displaying Frame <NUM> (212B), thus, after the minimum VB interval 260C, the sink device <NUM> begins displaying Frame <NUM> (<NUM>). As depicted in <FIG>, the source control circuitry <NUM> may place the high bandwidth communications link <NUM> in a standby or low power consumption mode over interval <NUM>, contemporaneous with the display of Frame <NUM> (212B) by the sink device <NUM>.

The temporal synchronization between the source device <NUM> and the sink device <NUM> may be maintained through all or a portion of the PSR/PSR2 operating mode. For example, the relatively low bandwidth side-channel communicative link <NUM> may be used for the bidirectional communication of timing information and/or data between the source device <NUM> and the sink device <NUM>. In the Panel Replay Mode, the sink device updates without delay upon receipt of a full or partial frame. When the source device <NUM> does not communicate a frame (e.g., when the source control circuitry <NUM> enters the PSR/PSR2 operating mode), the sink control circuitry <NUM> causes a presentation of the image data stored in the frame buffer circuitry <NUM> at the frame time determined by the source device <NUM>. In embodiments, the sink control circuitry <NUM> may replay the image data stored in the frame buffer circuitry <NUM> after the maximum BB interval <NUM>. As depicted in <FIG>, the system <NUM> maintains a variable temporal synchronization (by adjusting the duration of the VB intervals 260A-260E) at times T<NUM> through T<NUM>.

The system <NUM> may maintain temporal synchronization by maintaining one or more communication links between the source device <NUM> and the sink device <NUM> contemporaneous with all or a portion of the PSR/PSR2 operating mode. Such communication may occur via the high-bandwidth communications link <NUM>, the side-channel communications link <NUM>, another direct communication link (i.e., a link between the source device <NUM> and the sink device <NUM> that does not include intervening structures), indirect communication link (i.e., a link between the source device <NUM> and the sink device <NUM> that includes one or more intervening structures) communication link, or combinations thereof. The following example communications links are provided as illustrative examples, those of skill in the art will readily appreciate that there may be other, system specific, communications links that may directly or indirectly communicatively couple the source device <NUM> to the sink device <NUM>.

In at least some embodiments, the source control circuitry <NUM> may be communicatively coupled to the sink control circuitry <NUM> via the low-bandwidth side-channel communications link <NUM> and may maintain frame-level temporal synchronization using AUX_FRAME_SYNC. In such embodiments, the high-bandwidth communications link <NUM> may be placed in a standby or low power mode and communication may be maintained via the low-bandwidth side-channel communications link <NUM>. In such embodiments, the source control circuitry <NUM> may cause the high bandwidth communications link to remain active and may instead cause the generation and transmission of one or more idle patterns from the source device <NUM> to the sink device <NUM> via the high-bandwidth communications link <NUM>.

In at least some embodiments, the source control circuitry <NUM> may be communicatively coupled to the sink control circuitry <NUM> via an external communications link and may maintain frame-level temporal synchronization using bidirectional FS_HDP. In such embodiments, HDP may be reused as a bidirectional signal. In such embodiments, the high-bandwidth communications link <NUM> may be placed in a standby or low power mode and communication may be maintained via the external communications link. In such embodiments, the source control circuitry <NUM> may cause the high bandwidth communications link to remain active and may instead cause the generation and transmission of one or more idle patterns from the source device <NUM> to the sink device <NUM> via the high-bandwidth communications link <NUM>.

In at least some embodiments, the source control circuitry <NUM> may communicate frame updates that include Presentation Time Stamps based on a Global Time code via the high-bandwidth communications link <NUM> to maintain frame-level temporal synchronization. In such embodiments, in the absence of frame update transmissions, the source control circuitry <NUM> may place the high-bandwidth communications link <NUM> in a standby or low power mode. In such embodiments, in the absence of frame update transmissions, the source control circuitry <NUM> may cause the high bandwidth communications link to remain active and may instead cause the generation and transmission of one or more idle patterns from the source device <NUM> to the sink device <NUM>.

In at least some embodiments, the source control circuitry <NUM> may maintain the high-bandwidth communications link <NUM> and may communicate line and/or frame timing markers (BSBE) to maintain line-level and/or frame-level temporal synchronization.

<FIG> is a timing diagram <NUM> depicting an illustrative system in Panel Self-Refresh Mode in which the sink device <NUM> includes adaptive synchronization, in accordance with at least one embodiment described herein. In embodiments, temporal synchronization between the source device <NUM> and the sink device <NUM> is not maintained during all or a portion of the PSR/PSR2 operating mode. In the PSR operating mode, the sink device <NUM> will present image data stored locally in the frame buffer circuitry <NUM>. In the PSR operating mode as depicted in <FIG>, the source device <NUM> and the sink device <NUM> will temporally resynchronize upon exiting the PSR/PSR2 operating mode.

As depicted in <FIG>, the source device <NUM> generates Frame <NUM> (<NUM>), Frame <NUM> (<NUM>), Frame <NUM> (<NUM>), Frame <NUM> (<NUM>), and Frame <NUM> (<NUM>) each of which may be rendered at different frame rates. As depicted in <FIG>, upon completing the rendering of a frame, the source device <NUM> communicates the respective frame to the sink device <NUM> via the high-bandwidth link <NUM>. As depicted in <FIG>, the sink device <NUM> initially presents the image data from Frame "<NUM>. " Contemporaneous with the display of Frame "<NUM>," the sink device <NUM> completes the receipt of image data associated with Frame <NUM> (<NUM>) via the high-bandwidth communications link <NUM>. After the minimum VB interval 260B, the sink device displays the image data associated with Frame <NUM> (<NUM>). Contemporaneous with the display of Frame <NUM> (<NUM>), the sink device <NUM> completes the receipt of image data associated with Frame <NUM> (<NUM>) via the high-bandwidth communications link <NUM> and, after a minimum VB interval 260C begins displaying the image data associated with Frame <NUM> (<NUM>). Frame <NUM> (<NUM>) data requires an extended time to generate, consequently after waiting the maximum VB interval 260D, the sink device again displays image data associated with Frame <NUM> (<NUM>). Contemporaneous with the display of Frame <NUM> (<NUM>) data, the source control circuitry <NUM> may place the high-bandwidth communications link <NUM> in a standby or low power consumption mode.

<FIG> is a schematic diagram of an illustrative electronic, processor-based, device <NUM> that includes a graphics processing unit ("GPU")/source device <NUM> and an OLED display/sink device <NUM>, in accordance with at least one embodiment described herein. The processor-based device <NUM> may additionally include one or more of the following: processor circuitry <NUM>, a wireless input/output (I/O) interface <NUM>, a wired I/O interface <NUM>, system memory <NUM>, power management circuitry <NUM>, a non-transitory storage device <NUM>, and a network interface <NUM>. The following discussion provides a brief, general description of the components forming the illustrative processor-based device <NUM>. Example, non-limiting processor-based devices <NUM> may include, but are not limited to: smartphones, wearable computers, portable computing devices, handheld computing devices, desktop computing devices, blade server devices, workstations, and similar.

In some embodiments, the processor-based device <NUM> includes processor circuitry <NUM> capable of executing machine-readable instruction sets and generating an output signal capable of providing a display output to a system user via the OLED display <NUM>. Those skilled in the relevant art will appreciate that the illustrated embodiments as well as other embodiments may be practiced with other processor-based device configurations, including portable electronic or handheld electronic devices, for instance smartphones, portable computers, wearable computers, consumer electronics, personal computers ("PCs"), network PCs, minicomputers, server blades, mainframe computers, and the like. The processor circuitry <NUM> may include any number of hardwired or configurable circuits, some or all of which may include programmable and/or configurable combinations of electronic components, semiconductor devices, and/or logic elements that are disposed partially or wholly in a PC, server, or other computing system capable of executing machine-readable instructions.

The processor-based device <NUM> includes a bus or similar communications link <NUM> that communicably couples and facilitates the exchange of information and/or data between various system components including the processor circuitry <NUM>, the source device/GPU circuitry <NUM>, one or more wireless I/O interfaces <NUM>, one or more wired I/O interfaces <NUM>, the system memory <NUM>, the power management circuitry <NUM>, one or more storage devices <NUM>, and/or one or more network interfaces <NUM>. The processor-based device <NUM> may be referred to in the singular herein, but this is not intended to limit the embodiments to a single processor-based device <NUM>, since in certain embodiments, there may be more than one processor-based device <NUM> that incorporates, includes, or contains any number of communicably coupled, collocated, or remote networked circuits or devices.

The processor circuitry <NUM> may include any number, type, or combination of currently available or future developed devices capable of executing machine-readable instruction sets. The processor circuitry <NUM> may include but is not limited to any current or future developed single- or multi-core processor or microprocessor, such as: on or more systems on a chip (SOCs); central processing units (CPUs); digital signal processors (DSPs); graphics processing units (GPUs); application-specific integrated circuits (ASICs), programmable logic units, field programmable gate arrays (FPGAs), and the like. Unless described otherwise, the construction and operation of the various blocks shown in <FIG> are of conventional design. Consequently, such blocks need not be described in further detail herein, as they will be understood by those skilled in the relevant art. The bus <NUM> that interconnects at least some of the components of the processor-based device <NUM> may employ any currently available or future developed serial or parallel bus structures or architectures.

The system memory <NUM> may include read-only memory ("ROM") <NUM> and random access memory ("RAM") <NUM>. A portion of the ROM <NUM> may be used to store or otherwise retain a basic input/output system ("BIOS") <NUM>. The BIOS <NUM> provides basic functionality to the processor-based device <NUM>, for example by causing the processor circuitry <NUM> to load and/or execute one or more machine-readable instruction sets, such as the operating system instructions, and/or one or more applications. In embodiments, at least some of the one or more machine-readable instruction sets cause at least a portion of the processor circuitry <NUM> to provide, create, produce, transition, and/or function as a dedicated, specific, and particular machine, for example a word processing machine, a digital image acquisition machine, a media playing machine, a gaming system, a communications device, a smartphone, or similar.

The processor-based device <NUM> may include at least one wireless input/output (I/O) interface <NUM>. The at least one wireless I/O interface <NUM> may be communicably coupled to one or more physical output devices <NUM> (tactile devices, video displays, audio output devices, hardcopy output devices, etc.). The at least one wireless I/O interface <NUM> may communicably couple to one or more physical input devices <NUM> (pointing devices, touchscreens, keyboards, tactile devices, etc.). The at least one wireless I/O interface <NUM> may include any currently available or future developed wireless I/O interface. Example wireless I/O interfaces include, but are not limited to: BLUETOOTH°, near field communication (NFC), and similar.

The processor-based device <NUM> may include one or more wired input/output (I/O) interfaces <NUM>. The at least one wired I/O interface <NUM> may be communicably coupled to one or more physical output devices <NUM> (tactile devices, video displays, audio output devices, hardcopy output devices, etc.). The at least one wired I/O interface <NUM> may be communicably coupled to one or more physical input devices <NUM> (pointing devices, touchscreens, keyboards, tactile devices, etc.). The wired I/O interface <NUM> may include any currently available or future developed I/O interface. Example wired I/O interfaces include but are not limited to: universal serial bus (USB), IEEE <NUM> ("FireWire"), and similar.

The processor-based device <NUM> may include one or more communicably coupled, non-transitory, data storage devices <NUM>. The data storage devices <NUM> may include one or more hard disk drives (HDDs) and/or one or more solid-state storage devices (SSDs). The one or more data storage devices <NUM> may include any current or future developed storage appliances, network storage devices, and/or systems. Non-limiting examples of such data storage devices <NUM> may include, but are not limited to, any current or future developed non-transitory storage appliances or devices, such as one or more magnetic storage devices, one or more optical storage devices, one or more electro-resistive storage devices, one or more molecular storage devices, one or more quantum storage devices, or various combinations thereof. In some implementations, the one or more data storage devices <NUM> may include one or more removable storage devices, such as one or more flash drives, flash memories, flash storage units, or similar appliances or devices capable of communicable coupling to and decoupling from the processor-based device <NUM>.

The one or more data storage devices <NUM> may include interfaces or controllers (not shown) communicatively coupling the respective storage device or system to the bus <NUM>. The one or more data storage devices <NUM> may store, retain, or otherwise contain machine-readable instruction sets, data structures, program modules, data stores, databases, logical structures, and/or other data useful to the processor circuitry <NUM> and/or source device/GPU circuitry <NUM> and/or one or more applications executed on or by the processor circuitry <NUM> and/or source device/GPU circuitry <NUM>. In some instances, one or more data storage devices <NUM> may be communicably coupled to the processor circuitry <NUM>, for example via the bus <NUM> or via one or more wired communications interfaces <NUM> (e.g., Universal Serial Bus or USB); one or more wireless communications interfaces <NUM> (e.g., Bluetooth®, Near Field Communication or NFC); and/or one or more network interfaces <NUM> (IEEE <NUM> or Ethernet, IEEE <NUM>, or WiFi®, etc.).

The one or more data storage devices <NUM> stores all or a portion of the instructions executed, at least in part, by the processor circuitry <NUM>. The one or more data storage devices <NUM> may store, include, or otherwise retain operating system instructions. The operating system instructions may include but are not limited to any version up to the latest release of: Windows®; OSx®; iOS®; Android®; Linux®; and similar. The one or more storage devices <NUM> may store, include, or otherwise retain application instructions executed by the processor circuitry <NUM>. Such applications may include but are not limited to: productivity software; communications software; entertainment software; audio and/or video playback software; or similar.

The processor-based device <NUM> may include power management circuitry <NUM> that controls one or more operational aspects of the energy storage device <NUM>. In embodiments, the energy storage device <NUM> may include one or more primary (i.e., non-rechargeable) or secondary (i.e., rechargeable) batteries or similar energy storage devices. In embodiments, the energy storage device <NUM> may include one or more supercapacitors or ultracapacitors. In embodiments, the power management circuitry <NUM> may alter, adjust, or control the flow of energy from an external power source <NUM> to the energy storage device <NUM> and/or to the processor-based device <NUM>. The power source <NUM> may include, but is not limited to, a solar power system, a commercial electric grid, a portable generator, an external energy storage device, or any combination thereof.

For convenience, the processor circuitry <NUM>, the storage device <NUM>, the system memory <NUM>, the source device/GPU circuitry <NUM>, the wireless I/O interface <NUM>, the wired I/O interface <NUM>, the power management circuitry <NUM>, and the network interface <NUM> are illustrated as communicatively coupled to each other via the bus <NUM>, thereby providing connectivity between the above-described components. In alternative embodiments, the above-described components may be communicatively coupled in a different manner than illustrated in <FIG>. For example, one or more of the above-described components may be directly coupled to other components, or may be coupled to each other, via one or more intermediary components (not shown). In another example, one or more of the above-described components may be integrated into the processor circuitry <NUM> and/or the graphics processor circuitry <NUM>. In some embodiments, all or a portion of the bus <NUM> may be omitted and the components are coupled directly to each other using suitable wired or wireless connections.

<FIG> is a high-level block flow diagram of an illustrative method <NUM> that communicatively couples a source device <NUM> having Panel Self-Refresh (PSR/PSR2) equipped source control circuitry <NUM> with a sink device <NUM> having adaptive synchronization equipped sink control circuitry <NUM>, in accordance with at least one embodiment described herein. The method <NUM> commences at <NUM>.

At <NUM>, the graphics circuitry <NUM> disposed in the source device <NUM> generates a plurality of frames 132A-132n. In embodiments, each of the frames <NUM> may have the same or a different frame generation rate.

At <NUM>, the source control circuitry <NUM> causes the graphics circuitry <NUM> to transfer the frames 132A-132n to the high-bandwidth transmitter circuit <NUM> for transmission, via the high-bandwidth communications link <NUM>, to the high-bandwidth receiver circuit <NUM> in the sink device <NUM>. The sink control circuitry <NUM> attempts to synchronize the frame refresh rate of a display device <NUM>, such as an OLED display, to the frame generation rate of the source device <NUM>.

At <NUM>, the source control circuitry <NUM> places the system into a Panel Self Refresh (PSR/PSR2) operating mode in response to detecting unchanging (PSR) or minimally changing (PSR2) image data included in each of a plurality of frames generated by the graphics circuitry <NUM>. In the PSR/PSR2 operating mode, the high-bandwidth transmitter circuit <NUM>, the high-bandwidth receiver circuit <NUM>, and the high-bandwidth communications link <NUM> may be placed in a standby or similar low-power consumption mode. When the high-bandwidth communications link <NUM> is placed in standby mode, temporal synchronization between the source control circuitry <NUM> and the sink control circuitry <NUM> via the high-bandwidth communications link <NUM> may be impacted or even interrupted completely.

At <NUM>, in response to entering the PSR/PSR2 operating mode, the sink control circuitry <NUM> causes a storage of at least one frame in the frame buffer circuitry <NUM> disposed in the sink device <NUM>. The sink control circuitry <NUM> will continue to display the image stored in the frame buffer circuitry <NUM> for at least a portion of the duration of the PSR/PSR2 operating mode.

At <NUM>, the source control circuitry <NUM> and/or the sink control circuitry <NUM> temporally synchronize the source device <NUM> and the sink device <NUM> in response to exiting the PSR/PSR2 operating mode. In embodiments, the source device <NUM> and the sink device <NUM> may maintain temporal synchronization contemporaneous with all or a portion of the PSR/PSR2 operating mode. In other embodiments, the source device <NUM> and the sink device <NUM> may lose temporal synchronization during at least a portion of the PSR/PSR2 operating mode and may re-synchronize after exiting the PSR/PSR2 operating mode.

At <NUM>, the sink control circuitry <NUM> adjusts the refresh rate of the communicatively coupled display device <NUM> based, at least in part, on the frame generation rate of the source device <NUM>. The method <NUM> concludes at <NUM>.

<FIG> is a high-level flow diagram of an illustrative method <NUM> of maintaining temporal synchronization between a source device <NUM> and a sink device <NUM> contemporaneous with at least a portion of the PSR/PSR2 operating mode, in accordance with at least one embodiment described herein. The method <NUM> may be used in conjunction with the method <NUM> depicted in <FIG>. The method <NUM> commences at <NUM>.

At <NUM>, the source control circuitry <NUM> and/or the sink control circuitry <NUM> determines whether the system has been placed in the PSR/PSR2 operating mode. Responsive to a determination that the system has not been placed in PSR/PSR2 operating mode, the method <NUM> returns to <NUM>.

At <NUM>, responsive to a determination that the system has been placed in PSR/PSR2 operating mode, the source control circuitry <NUM> and/or the sink control circuitry <NUM> may communicate synchronization signals via one or more sideband channels. In some implementations, the source control circuitry <NUM> and/or the sink control circuitry <NUM> may establish a sideband connection via the side-channel transceiver circuitry <NUM>, the side-channel transceiver circuitry <NUM>, and the low bandwidth communications link <NUM>.

At <NUM>, the source control circuitry <NUM> determines whether to place the high-bandwidth communications link <NUM> in a standby or low power consumption mode. Responsive to a determination that the high-bandwidth communications link <NUM> should be placed in a standby or low power consumption mode, the method <NUM> continues at <NUM>. Responsive to a determination that the high-bandwidth communications link <NUM> should not be placed in a standby or low power consumption mode, the method <NUM> continues at <NUM>.

At <NUM>, the source control circuitry <NUM> places the high-bandwidth communications link <NUM> in a standby or low power consumption mode. The method <NUM> concludes at <NUM>.

At <NUM>, the source control circuitry <NUM> maintains the high-bandwidth communications link <NUM> and generates an idle pattern image for transmission to the sink device <NUM>. The method <NUM> concludes at <NUM>.

At <NUM>, responsive to a determination that the system has been placed in PSR/PSR2 operating mode, the source control circuitry <NUM> and/or the sink control circuitry <NUM> may communicate synchronization signals via one or more sideband channels, such as via bidirectional FS_HDP.

At <NUM>, the source control circuitry <NUM> and/or the sink control circuitry <NUM> determines whether the system has been placed in the PSR/PSR2 operating mode. Responsive to a determination that the system has not been placed in PSR/PSR2 operating mode, the method <NUM> returns to <NUM>. Responsive to a determination that the system has been placed in PSR/PSR2 operating mode, the method <NUM> continues to <NUM>.

At <NUM>, responsive to a determination that the system has been placed in PSR/PSR2 operating mode, the source control circuitry <NUM> maintains the high-bandwidth communications link <NUM> linking the high-bandwidth transmitter circuit <NUM> with the high-bandwidth receiver circuit <NUM>.

At <NUM>, the source control circuitry <NUM> communicates timing marker data to the sink device <NUM> to maintain synchronization between the source device and the sink device. The method <NUM> concludes at <NUM>.

<FIG> is a high-level flow diagram of an illustrative method <NUM> of resynchronizing a source device <NUM> and a sink device <NUM> upon exiting the PSR/PSR2 operating mode, in accordance with at least one embodiment described herein. The method <NUM> may be used in conjunction with the method <NUM> depicted in <FIG>. The method <NUM> commences at <NUM>.

At <NUM>, the sink control circuitry <NUM> determines a duration and/or an equivalent number of frames needed to resynchronize the sink device <NUM> upon the system exiting the PSR/PSR2 operating mode.

At <NUM>, the sink control circuitry <NUM> causes the storage of data and/or information indicative of the number of frames determined at <NUM> in one or more register circuits <NUM> included in memory circuitry local to the sink device <NUM>.

At <NUM>, the source control circuitry <NUM> places the system in a PSR/PSR2 operating mode in which the high-bandwidth transmitter circuit <NUM>, high-bandwidth receiver circuit <NUM>, and high-bandwidth communications link <NUM> are placed in a standby or similar low power consumption operating mode.

At <NUM>, responsive to exiting the PSR/PSR2 operating mode, the source control circuitry <NUM> reads the data indicative of the number of frames in the one or more register circuits <NUM> included in memory circuitry local to the sink device <NUM>.

At <NUM>, to re-synchronize the source device <NUM> with the sink device <NUM>, the source control circuitry <NUM> causes a delay equal to the number of frames received at <NUM>. The method <NUM> concludes at <NUM>.

While <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> illustrate various operations according to one or more embodiments, it is to be understood that not all of the operations depicted in <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are necessary for other embodiments. Indeed, it is fully contemplated herein that in other embodiments of the present disclosure, the operations depicted in <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> and/or other operations described herein, may be combined in a manner not specifically shown in any of the drawings, but still fully consistent with the present disclosure. Thus, claims directed to features and/or operations that are not exactly shown in one drawing are deemed within the scope and content of the present disclosure.

As used in any embodiment herein, the terms "system" or "module" may refer to, for example, software, firmware and/or circuitry configured to perform any of the aforementioned operations. Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on non-transitory computer readable storage mediums. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices.

As used in any embodiment herein, the term "circuitry" may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry or future computing paradigms including, for example, massive parallelism, analog or quantum computing, hardware embodiments of accelerators such as neural net processors and non-silicon implementations of the above. The circuitry may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smartphones, etc..

Any of the operations described herein may be implemented in a system that includes one or more mediums (e.g., non-transitory storage mediums) having stored therein, individually or in combination, instructions that when executed by one or more processors perform the methods. Here, the processor may include, for example, a server CPU, a mobile device CPU, and/or other programmable circuitry. Also, it is intended that operations described herein may be distributed across a plurality of physical devices, such as processing structures at more than one different physical location. The storage medium may include any type of tangible medium, for example, any type of disk including hard disks, floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, Solid State Disks (SSDs), embedded multimedia cards (eMMCs), secure digital input/output (SDIO) cards, magnetic or optical cards, or any type of media suitable for storing electronic instructions. Other embodiments may be implemented as software executed by a programmable control device.

Thus, the present disclosure is directed to systems and methods of maintaining source device to sink device synchronization in systems in which the source device enters a Panel Self-Refresh (PSR/PSR2) mode and the sink device enables adaptive synchronization with the source device. To maintain synchronization, in some instances the source device and the sink device may maintain synchronization contemporaneous with at least a portion of the PSR/PSR2 operating mode. To maintain synchronization, in some instances, a high-bandwidth communications link may be maintained between the source device and the sink device. In some instances, synchronization between the source device and the sink device may be interrupted upon the source device entering the PSR/PSR2 operating mode and may be re-established upon the source device exiting the PSR/PSR2 operating mode.

The following examples pertain to further embodiments. The following examples of the present disclosure may comprise subject material such as at least one device, a method, at least one machine-readable medium for storing instructions that when executed cause a machine to perform acts based on the method, means for performing acts based on the method and/or a system for maintaining source device to sink device synchronization in systems in which the source device enters a Panel Self-Refresh (PSR/PSR2) mode and the sink device enables adaptive synchronization with the source device.

According to example <NUM>, there is provided a data transmission system. The system may include: a source device comprising: high-bandwidth transmitter circuitry; sideband transceiver circuitry; control circuitry to: generate a plurality of frames at one or more frame generation rates; provide the plurality of frames to the high-bandwidth transmitter circuitry; disable at least the high-bandwidth transmitter circuitry responsive to entering a Panel Self-Refresh (PSR) operating mode; synchronize the source device and the sink device responsive to exiting the PSR operating mode; and adjust, by the sink device control circuitry. The system may additionally include: high-bandwidth receiver circuitry to receive the plurality of frames from the source device; sideband transceiver circuitry communicatively coupled to the source device sideband transceiver circuitry; memory circuitry; control circuitry to:
cause a storage of at least one frame included in the plurality of frames in the memory circuitry; and adjust a refresh rate of a communicatively coupled display device to the frame generation rate of the source device.

Example <NUM> may include elements of example <NUM> and the system may further include: a high-bandwidth communications link to communicatively couple the source device high-bandwidth transmitter circuitry to the sink device high-bandwidth receiver circuitry.

Example <NUM> may include elements of any of examples <NUM> or <NUM> and the sink device control circuitry to further: cause a display of the at least one frame in the memory circuitry responsive to the source device entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where to adjust a refresh rate of a communicatively coupled display device, the sink device control circuitry to: adjust a duration of a respective vertical blank (VB) interval associated with each frame included in the plurality of frames over a defined VB range.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry to further: communicate, via the source device sideband transceiver circuitry, one or more timing signals to the sink device sideband transceiver circuitry, the one or more timing signals to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the source device control circuitry to further: disable the high-bandwidth communications link responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the source device control circuitry to further: communicate data representative of an idle pattern to the sink device via the high-bandwidth communications link responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry to further: bidirectionally communicate, via a second sideband communications link, one or more timing signals to the sink device, the one or more timing signals to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM>, the source device control circuitry to further: disable the high-bandwidth communications link responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM>, the source device control circuitry to further: communicate data representative of an idle pattern to the sink device via the high-bandwidth communications link responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry to further: determine, using a universal time standard, a Presentation Time Stamp (PTS) value associated with a frame; and communicate, via the high-bandwidth communications link and in response to exiting the PSR operating mode, the frame having associated therewith the PTS value to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry to further: maintain the high-bandwidth communications link responsive to entering the PSR operating mode; and communicate, via the high-bandwidth communications link for the duration of the PSR operating mode, to the sink device at least one of: line timing marker data to maintain a line-level temporal synchronization between the source device and the sink device or frame timing marker data to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the sink device control circuitry may further: determine a number of frames to display to resynchronize sink device timing with source device timing upon exiting the PSR operating mode; store a value indicative of the determined number of frames in a sink device memory register circuit;
wherein to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry to further: disable the high-bandwidth communications link responsive to entering the PSR operating mode; responsive to exiting the PSR operating mode, read the value indicative of the determined number of frames in the sink device memory register circuit; and resynchronize the source device control circuitry with the sink device control circuitry responsive to exiting the PSR operating mode.

According to example <NUM>, there is provided a data transmission method. The method may include: generating, by source device graphics circuitry, a plurality of frames at one or more frame generation rates; providing, by source device control circuitry, each of the plurality of frames to high-bandwidth transmitter circuitry; disabling, by the source device control circuitry, at least the high-bandwidth transmitter circuitry responsive to entering a Panel Self-Refresh (PSR) operating mode; causing, by sink device control circuitry, a storage of at least one frame included in the plurality of frames in sink device memory circuitry; temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode; and adjusting, by the sink device control circuitry, a refresh rate of a communicatively coupled display device to the frame generation rate of the source device.

Example <NUM> may include elements of example <NUM> and the method may further include: causing, by the sink device control circuitry, a display of the at least one frame in the memory circuitry responsive to an entry of the source device into the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> or <NUM> where adjusting the refresh rate of the communicatively coupled display device to the frame generation rate of the source device further comprising: adjusting, by the sink device control circuitry, a duration of a respective vertical blank (VB) interval associated with each frame included in the plurality of frames over a defined VB range.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode further comprises: communicating, by source device sideband transceiver circuitry, one or more timing signals to the sink device sideband transceiver circuitry contemporaneous with at least a portion of the PSR operating mode, the one or more timing signals to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode further comprises: disabling, by the source device control circuitry, a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode further comprises: communicating, by the source device control circuitry, data representative of an idle pattern to the sink device via a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode further comprises: bidirectionally communicating, by the source device control circuitry via a sideband communications link, one or more timing signals to the sink device, the one or more timing signals to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode further comprises: determining, by the source device control circuitry, a universal Presentation Time Stamp (PTS) value associated with a frame; and communicating, the source device control circuitry via the high-bandwidth communications link between the source device and the sink device, and in response to exiting the PSR operating mode, the frame having associated therewith the PTS value to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode further comprises: disabling, the source device control circuitry, a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode further comprises: maintaining, by the source device control circuitry, a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode; and communicating, by the source device control circuitry via the high-bandwidth communications link to the sink device for the duration of the PSR operating mode, at least one of: line timing marker data to maintain a line-level temporal synchronization between the source device and the sink device or frame timing marker data to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where temporally synchronizing the source device and the sink device responsive to exiting the PSR operating mode further comprises: determining, by the sink device control circuitry, a number of frames to display to resynchronize sink device timing with source device timing upon exiting the PSR operating mode; storing, by the sink device control circuitry, a value indicative of the determined number of frames in a sink device memory register circuit; disabling, by the source device control circuitry, a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode; reading, by the source device control circuitry, the value indicative of the determined number of frames in the sink device memory register circuit responsive to exiting the PSR operating mode; and resynchronizing the source device control circuitry with the sink device control circuitry responsive to exiting the PSR operating mode.

According to example <NUM>, there is provided a non-transitory storage device. The non-transitory storage device may include instructions that, when executed by circuitry, causes the control circuitry to: cause graphics circuitry to generate a plurality of frames at one or more frame generation rates; provide each of the plurality of frames to high-bandwidth transmitter circuitry; and disable at least the high-bandwidth transmitter circuitry responsive to entering a Panel Self-Refresh (PSR) operating mode; cause a storage of at least one frame included in the plurality of frames in sink device memory circuitry; temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode; and adjust a refresh rate of a communicatively coupled display device to the frame generation rate of the source device.

Example <NUM> may include elements of example <NUM> where the instructions further cause the control circuitry to: cause the sink device control circuitry to display of the at least one frame in the memory circuitry responsive to an entry of the source device into the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> or <NUM> where the instructions that cause the control circuitry to cause the sink control circuitry to adjust the refresh rate of the communicatively coupled display device to the frame generation rate of the source device further comprising: cause the sink control circuitry to adjust a duration of a respective vertical blank (VB) interval associated with each frame included in the plurality of frames over a defined VB range.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuitry to: cause the source device sideband transceiver circuitry to communicate one or more timing signals to the sink device sideband transceiver circuitry contemporaneous with at least a portion of the PSR operating mode, the one or more timing signals to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuitry to:
cause the source device control circuitry to disable a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuitry to: cause the source device control circuitry to communicate data representative of an idle pattern to the sink device via a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuitry to: cause the source device control circuitry to bidirectionally communicate, via a sideband communications link, one or more timing signals to the sink device, the one or more timing signals to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further causes the control circuitry to: cause the source device control circuitry to communicate data representative of an idle pattern to the sink device via a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuitry to:
cause the source device control circuitry to determine a universal Presentation Time Stamp (PTS) value associated with a frame; and cause the source device control circuitry to communicate, via the high-bandwidth communications link between the source device and the sink device, the frame having associated therewith the PTS value to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuity to: cause the source device control circuitry to disable a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuitry to:
cause the source device control circuitry to communicate data representative of an idle pattern to the sink device via a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuitry to: cause the source device control circuitry to maintain a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode and cause the source device control circuitry to communicate, via the high-bandwidth communications link to the sink device for the duration of the PSR operating mode, at least one of: line timing marker data to maintain a line-level temporal synchronization between the source device and the sink device or frame timing marker data to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the instructions that cause the control circuitry to temporally synchronize the source device and the sink device responsive to exiting the PSR operating mode further cause the control circuitry to:
cause the sink device control circuitry to determine a number of frames to display to resynchronize sink device timing with source device timing upon exiting the PSR operating mode; cause the sink device control circuitry to store a value indicative of the determined number of frames in a sink device memory register circuit; cause the source device control circuitry to disable a high-bandwidth communications link between the source device and the sink device responsive to entering the PSR operating mode; cause the source device control circuitry to read the value indicative of the determined number of frames in the sink device memory register circuit responsive to exiting the PSR operating mode; and cause source device control circuitry to resynchronize with the sink device control circuitry responsive to exiting the PSR operating mode.

According to example <NUM>, there is provided an electronic device. The electronic device may include: a source device comprising: high-bandwidth transmitter circuitry; sideband transceiver circuitry; graphics circuitry; control circuitry to: generate a plurality of frames at one or more frame generation rates; provide the plurality of frames to the high-bandwidth transmitter circuitry; disable at least the high-bandwidth transmitter circuitry responsive to entering a Panel Self-Refresh (PSR) operating mode; synchronize the source device and the sink device responsive to exiting the PSR operating mode; a sink device comprising: a display device.

Example <NUM> may include elements of example <NUM> and the electronic device may further include: a high-bandwidth communications link to communicatively couple the source device high-bandwidth transmitter circuitry to the sink device high-bandwidth receiver circuitry.

Example <NUM> may include elements of any of examples <NUM> or <NUM> wherein the sink device control circuitry may further: cause a display of the at least one frame in the memory circuitry responsive to the source device entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where, to adjust a refresh rate of a communicatively coupled display device, the sink device control circuitry may: adjust a duration of a respective vertical blank (VB) interval associated with each frame included in the plurality of frames over a defined VB range.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry may: communicate, via the source device sideband transceiver circuitry, one or more timing signals to the sink device sideband transceiver circuitry, the one or more timing signals to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the source device control circuitry may further: disable the high-bandwidth communications link responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the source device control circuitry may further: communicate data representative of an idle pattern to the sink device via the high-bandwidth communications link responsive to entering the PSR operating mode.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where, to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry may further: bidirectionally communicate, via a second sideband communications link, one or more timing signals to the sink device, the one or more timing signals to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry may further: determine, using a universal time standard, a Presentation Time Stamp (PTS) value associated with a frame; and communicate, via the high-bandwidth communications link and in response to exiting the PSR operating mode, the frame having associated therewith the PTS value to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry may further: maintain the high-bandwidth communications link responsive to entering the PSR operating mode; and communicate, via the high-bandwidth communications link for the duration of the PSR operating mode, to the sink device at least one of: line timing marker data to maintain a line-level temporal synchronization between the source device and the sink device or frame timing marker data to maintain a frame-level temporal synchronization between the source device and the sink device.

Example <NUM> may include elements of any of examples <NUM> through <NUM> where the sink device control circuitry may further: determine a number of frames to display to resynchronize sink device timing with source device timing upon exiting the PSR operating mode; store a value indicative of the determined number of frames in a sink device memory register circuit; wherein to synchronize the source device and the sink device responsive to exiting the PSR operating mode, the source control circuitry to further: disable the high-bandwidth communications link responsive to entering the PSR operating mode; responsive to exiting the PSR operating mode, read the value indicative of the determined number of frames in the sink device memory register circuit; and resynchronize the source device control circuitry with the sink device control circuitry responsive to exiting the PSR operating mode.

According to example <NUM>, there is provided a system to maintaining source device to sink device synchronization in systems in which the source device enters a Panel Self-Refresh (PSR/PSR2) mode and the sink device enables adaptive synchronization with the source device, the system being arranged to perform the method of any of examples <NUM> through <NUM>.

According to example <NUM>, there is provided a chipset arranged to perform the method of any of examples <NUM> through <NUM>.

According to example <NUM>, there is provided at least one machine readable medium comprising a plurality of instructions that, in response to be being executed on a computing device, cause the computing device to carry out the method according to any of examples <NUM> through <NUM>.

According to example <NUM>, there is provided a device configured to maintaining source device to sink device synchronization in systems in which the source device enters a Panel Self-Refresh (PSR/PSR2) mode and the sink device enables adaptive synchronization with the source device, the device being arranged to perform the method of any of examples <NUM> through <NUM>.

Claim 1:
A data transmission system, comprising:
a source device (<NUM>) comprising:
high-bandwidth transmitter circuitry (<NUM>);
sideband transceiver circuitry (<NUM>);
control circuitry to (<NUM>):
generate a plurality of frames (<NUM>) at one or more frame generation rates;
provide the plurality of frames to the high-bandwidth transmitter circuitry; and
disable at least the high-bandwidth transmitter circuitry responsive to entering a Panel Self-Refresh, PSR, operating mode;
a sink device comprising:
high-bandwidth receiver circuitry (<NUM>) to receive the plurality of frames from the source device;
sideband transceiver circuitry (<NUM>) communicatively coupled to the source device sideband transceiver circuitry to form a low bandwidth side-channel communicative link (<NUM>);
memory circuitry (<NUM>);
control circuitry (<NUM>) to:
cause a storage of at least one frame included in the plurality of frames in the memory circuitry; and
adjust a refresh rate of a communicatively coupled display device to the frame generation rate of the source device;
characterized in that to maintain a temporal synchronization between the source device (<NUM>) and the sink device (<NUM>) through all or a portion of the PSR operating mode, the source device (<NUM>) and the sink device (<NUM>) are configured to use the low bandwidth side-channel communicative link (<NUM>) for bidirectional communication of timing information between the source device (<NUM>) and the sink device (<NUM>).