Patent Description:
Electronic devices generally include a variety of components, including capacitors, mounted to a PWB. At least some known PWBs include an embedded capacitor that uses conductive layers of the PWB (e.g., a ground plane and a power plane) as capacitor plates. Such an embedded capacitor may eliminate the need to mount a capacitor to a surface of the PWB. However, at least some known embedded capacitors require a relatively large portion of the PWB to be dedicated to the capacitor, or require that the PWB be sized sufficiently to achieve a desired capacitance. Such a design may be infeasible for a smaller-sized PWB, such as a PWB designed for use in a mobile electronic device. In such a PWB, the capacitor may occupy so much of the PWB that insufficient space remains for other electronic components to be mounted on the PWB. Moreover, known embedded capacitors may exhibit a relatively high inductance, such that the capacitor becomes ineffective at high frequencies (e.g., above <NUM> megahertz). In addition, a conventional surface-mounted capacitor may be subjected to physical stress as the surface-mounted capacitor and the underlying PWB expand at different rates, whereas a capacitor embedded within a PWB may expand at substantially the same rate as the PWB to which it is mounted.

<CIT> concerns a low inductance grid array capacitor. The chip design, which is compatible with ball grid array and land grid array packaging, includes interleaved dielectric and electrode layers, with electrode tabs alternately extending from the electrode layers through which a via is formed for their interconnection.

<CIT> concerns a substrate for electronic components and <CIT> concerns a multi-component substrate with a core of high dielectric constant ceramic material.

<CIT> concerns a wiring board comprising a core board having a buildup layer forming a laminated wiring portion thereon defining a component mounting region for a multi chip module. A ceramic capacitor is embedded in an accommodation hole in the core board under the component mounting area.

<CIT> discloses a capacitor-incorporated substrate. First and second dielectric layers are formed by firing two kinds of inorganic compositions having different composition alternately.

<CIT> discloses a ceramic electronic component.

<CIT> discloses a multilayered capacitor board with a ceramic dielectric layer.

<CIT> discloses a multilayer board with a built-in LC resonator.

<CIT> discloses a printed wiring board and method for manufacturing the same.

<CIT> discloses a laser trimmable capacitor and its manufacturing method.

This Brief Description is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Brief Description is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

The embodiments described herein may be better understood by referring to the following description in conjunction with the accompanying drawings.

As used herein, a printed wiring board (PWB), also known as a printed circuit board (PCB), is a structure including one or more layers of non-conductive material. Electronic components, such as integrated circuits (ICs), logic gates, transistors, and/or capacitors may be coupled (e.g., by soldering) to a surface of the PWB. Such electronic components may be electrically coupled to each other using conductors, known as "traces", that are positioned on the non-conductive material. Some PWBs include multiple layers of non-conductive material, such that multiple layers of traces may be stacked by positioning the traces on the different layers of the PWB, with the non-conductive material insulating the traces on different layers from each other. In addition, one or more conductors, known as "vias", may extend between different layers of the PWB to couple a trace to another trace on a different layer and/or to an electronic component.

The embodiments described herein provide multi-plate capacitors that are embedded within a PWB. Two sets of interleaved, or alternately stacked, conductive plates may be created on layers of non-conductive material within the PWB. The conductive plates of each set may be electrically coupled to each other (e.g., using a conductive via). Accordingly, when an electrical potential difference (i.e., a voltage) is applied across the two sets of conductive plates, the non-conductive material acts as a dielectric, and electrical energy may be stored in a static electric field within the dielectric.

Embedding a multi-plate capacitor within a PWB as described herein facilitates reducing the effect of thermal expansion on the performance and/or longevity of a capacitor. At least in part because of the physical characteristics (e.g., permittivity) of the non-conductive material within the PWB and/or because of multiple conductive vias are included, providing an embedded capacitor as described herein may facilitate reducing the inductance exhibited by a capacitor and enable the use of such a capacitor at higher switching rates (i.e., frequencies) than are feasible with conventional capacitors. For example, a multi-plate embedded capacitor may be effective above <NUM> megahertz.

<FIG> is a diagram of a cross-sectional view of an example embedded capacitor <NUM>. In the illustrative example not according to the invention, capacitor <NUM> is embedded within a PWB <NUM> that defines a planar area <NUM> (indicated by a horizontal plane in <FIG>). Capacitor <NUM> includes a plurality of first conductive plates <NUM> and at least one second conductive plate <NUM> that are aligned substantially parallel to planar area <NUM>. More specifically, first conductive plates <NUM> extend from a first normal axis <NUM> towards a second normal axis <NUM>. Each second conductive plate <NUM> extends from second normal axis <NUM> towards first normal axis <NUM>. Both first normal axis <NUM> and second normal axis <NUM> are substantially perpendicular to planar area <NUM>.

Each second conductive plate <NUM> is positioned between a respective pair of first conductive plates <NUM>. In an illustrative example not according to the invention, capacitor <NUM> includes a plurality of second conductive plates <NUM> that are interleaved with (e.g., alternately positioned with) first conductive plates <NUM>. In one illustrative example not according to the invention, capacitor <NUM> includes n first conductive plates and n second conductive plates <NUM>. In such an illustrative example not according to the invention, n-<NUM> second conductive plates <NUM> are positioned between each respective pair of first conductive plates <NUM>, and a single second conductive plate <NUM> is positioned adjacent to a single first conductive plate <NUM>. In another illustrative example not according to the invention, capacitor <NUM> includes n first conductive plates <NUM> and n-<NUM> second conductive plates <NUM>. In such an illustrative example not according to the invention, each second conductive plate <NUM> is positioned between a pair of first conductive plates <NUM>.

A non-conductive material <NUM> extends between first conductive plates <NUM> and second conductive plates <NUM>. Non-conductive material <NUM> may also be positioned between first conductive plates <NUM> and second normal axis <NUM>, and/or between second conductive plates <NUM> and first normal axis <NUM>. Accordingly, in each illustrative example not according to the invention, first conductive plates <NUM> are not direct against and/or do not contact second conductive plates <NUM>. In an example embodiment, non-conductive material <NUM> is FR-<NUM>, and first conductive plates <NUM> and second conductive plates <NUM> are composed of copper. Alternatively first conductive plates <NUM> and second conductive plates <NUM> may be composed of any suitable electrically conductive material.

In the example embodiment, capacitor <NUM> also includes at least one first conductive via <NUM> that is aligned substantially collinear with first normal axis <NUM> and that contacts first conductive plates <NUM>, and at least one second conductive via <NUM> that is aligned substantially collinear with second normal axis <NUM> and that contacts second conductive plates <NUM>.

The quantity, shape, dimensions, and/or spacing of first conductive plates <NUM> and/or second conductive plates <NUM> may be variably selected based on a desired capacitance level for capacitor <NUM>. For example, increasing the quantity and/or size of first conductive plates <NUM> and/or second conductive plates <NUM> generally facilitates increasing the capacitance of capacitor <NUM>. In some embodiments, capacitor <NUM> includes between <NUM> and <NUM> first conductive plates <NUM> and between four and forty second conductive plates <NUM>.

Capacitor <NUM> occupies at least a portion of the thickness or height <NUM> of PWB <NUM>. In some embodiments, first conductive plates <NUM> and second conductive plates <NUM> are stacked approximately to PWB thickness <NUM>. The outermost conductive plates <NUM> of capacitor <NUM> may be covered by non-conductive material <NUM> to facilitate reducing the risk of accidental electrical contact with capacitor <NUM>.

In some embodiments, a capacitor is created that includes layers of non-conductive material <NUM> with conductive plates positioned thereon. <FIG> is a diagram showing an example of a plurality of layers <NUM> within PWB <NUM>. <FIG> is a flowchart of an example method <NUM> that may be used to create capacitors <NUM> that are embedded within PWB <NUM>. In the example embodiment, initially, one or more available areas <NUM> (shown in <FIG>) of a PWB to which capacitor <NUM> will be mounted are determined <NUM>, as described in more detail below. If no portion of the PWB is allocated for mounting electronic components, the entirety of the PWB may be considered available. Otherwise, available areas <NUM> may be selected depending on the position and/or the size of electronic components to be coupled to PWB <NUM>.

The dimensions, quantities, and/or spacing of conductive plates <NUM>, <NUM> to include in a capacitor <NUM> are then determined <NUM>. For example, if a desired capacitance is known, the dimensions, quantities, and/or spacing of the conductive plates <NUM>, <NUM> may be determined <NUM> based at least in part on the desired capacitance, the available areas of the PWB to which capacitor <NUM> will be mounted, the quantity of layers within PWB <NUM>, and/or physical characteristics (e.g., permittivity) of the non-conductive material <NUM> within PWB <NUM>.

In the example embodiment, a first non-conductive layer <NUM> is created <NUM>, and a first conductive plate <NUM> is extended across <NUM> at least a portion of first non-conductive layer <NUM>. For example, first conductive plate <NUM> may be created <NUM> by applying a copper material across a portion of first non-conductive layer <NUM>. First conductive plate <NUM> extends from first normal axis <NUM> towards second normal axis <NUM>. A second non-conductive layer <NUM> may be created <NUM>. For example, a dielectric may be applied over first conductive plate <NUM> to create <NUM> second non-conductive layer <NUM>.

A second conductive plate <NUM> is created <NUM> on second non-conductive layer <NUM>. In the example embodiment, second conductive plate <NUM> extends from second normal axis <NUM> towards first normal axis <NUM>.

First conductive plate <NUM> and second conductive plate <NUM> form a pair of conductive plates that may be used by themselves as a capacitor. Alternatively, multiple pairs of conductive plates may be stacked by creating <NUM> another conductive layer over second conductive plate <NUM>, creating <NUM> another first conductive plate <NUM>, creating <NUM> another non-conductive layer, and creating <NUM> another second conductive plate <NUM>. This process may be repeated to create any desired quantity of conductive plates. Optionally, a third non-conductive layer <NUM> may be applied over the topmost conductive plate (e.g., second conductive plate <NUM>). Such an embodiment facilitates insulating the topmost conductive plate from accidental electrical contact.

In an example embodiment, first conductive plates <NUM> are electrically coupled <NUM> to each other, and second conductive plates <NUM> are electrically coupled <NUM> to each other. For example, first conductive plates <NUM> may be electrically coupled <NUM> by extending one or more first conductive vias <NUM> (shown in <FIG> and <FIG>) substantially along, or adjacent to, first normal axis <NUM>, such that the first conductive via <NUM> physically contacts first conductive plates <NUM>. Similarly, second conductive plates <NUM> may be electrically coupled <NUM> by extending second conductive vias <NUM> (shown in <FIG> and <FIG>) substantially along, or adjacent to, second normal axis <NUM>.

As described in more detail below, some embodiments facilitate creating multiple embedded capacitors <NUM> in a single PWB <NUM>. For example, multiple embedded capacitors <NUM> may be stacked in PWB <NUM>. In some embodiments, stacked embedded capacitors <NUM> are separated by one or more non-conductive layers. Such separation may reduce propagation of an electric charge from one embedded capacitor <NUM> to another. In addition to, or in the alternative, multiple sets of first conductive plates <NUM> and second conductive plates <NUM> may be created in different portions of the planar area <NUM> of PWB <NUM>. In such an embodiment, a conductive plate for each embedded capacitor <NUM> may be created <NUM> on first non-conductive layer <NUM> prior to creating <NUM> second non-conductive layer <NUM>.

<FIG> is a plan view of a PWB <NUM> that includes a plurality of PWB-embedded capacitors <NUM>. In the example embodiment, a portion <NUM> of PWB <NUM> is allocated to electronic components <NUM>, such as memory devices, logic gates, and/or integrated circuits (ICs). Available areas in PWB <NUM> may be determined <NUM> (shown in <FIG>) at least in part by identifying one or more portions of PWB <NUM> that are not allocated to electronic components <NUM>. Available areas may therefore represent portions of PWB <NUM> that are unused.

Each embedded capacitor <NUM> occupies a portion of the planar area of PWB <NUM> and is mounted (e.g., soldered) to a surface of PWB <NUM>. In an example embodiment, first conductive plates <NUM> (shown in <FIG>) of a first embedded capacitor <NUM> are electrically coupled to each other by first conductive vias <NUM>. Second conductive plates <NUM> (shown in <FIG>) are electrically coupled to each other by second conductive vias <NUM>. Coupling conductive plates <NUM>, <NUM> with multiple vias <NUM>, <NUM> facilitates reducing the inductance of embedded capacitor <NUM> and may therefore enable the use of capacitor <NUM> at frequencies higher than the frequencies at which conventional capacitors are operable.

First conductive vias <NUM> are electrically coupled to an electronic component <NUM> by a first conductor <NUM>, and second conductive vias <NUM> are electrically coupled to the electronic component <NUM> by a second conductor <NUM>. In one embodiment, first conductor <NUM> and second conductor <NUM> are traces extending across a portion of an internal non-conductive layer or a portion of the external surface of PWB <NUM>. Such traces may electrically couple any number of electronic components <NUM> and/or embedded capacitors <NUM> to each other.

In the example embodiment, first embedded capacitor <NUM> stores an electric charge provided by first conductor <NUM> and/or second conductor <NUM> as an electric field between first conductive plates <NUM> and second conductive plates <NUM>. First embedded capacitor <NUM> may subsequently discharge an electric charge through first conductor <NUM> and/or second conductor <NUM>.

Embedded capacitors <NUM> may have any shape suitable for use with the methods described herein. For example, first embedded capacitor <NUM> is rectangular. A second embedded capacitor <NUM> is L-shaped, enabling second embedded capacitor <NUM> to provide substantially a maximum possible capacitance within an available area outside the portion <NUM> of PWB allocated to electronic components <NUM>.

Embedded capacitors <NUM> are created using materials that are similar or identical to the materials used to create PWB <NUM>. As a result, embedded capacitors <NUM> exhibit thermal expansion that is similar or identical to the thermal expansion exhibited by PWB <NUM>. Accordingly, embedded capacitors <NUM> facilitate reducing the physical stress applied to first conductor <NUM> and second conductor <NUM> as the operating temperature of PWB <NUM> changes.

Some embodiments facilitate stacking embedded capacitors <NUM>. <FIG> is a diagram of a cross-section of an alternate PWB <NUM> with a plurality of embedded capacitors <NUM> in accordance with one embodiment. PWB <NUM> has a top surface <NUM> and a bottom surface <NUM>, with a thickness <NUM> defined therebetween. A first embedded capacitor <NUM> occupies a planar area <NUM> within PWB <NUM> and extends from bottom surface <NUM> to approximately half the thickness <NUM> of PWB <NUM>.

A second embedded capacitor <NUM> occupies substantially the same planar area <NUM> that is occupied by first embedded capacitor <NUM>. Second embedded capacitor <NUM> extends from top surface <NUM> approximately half the thickness <NUM> of PWB <NUM> but is not in direct contact with first embedded capacitor <NUM>. For example, one or more layers of non-conductive material may separate second embedded capacitor <NUM> from first embedded capacitor <NUM>. First embedded capacitor <NUM> may occupy any portion of thickness <NUM>, and second embedded capacitor <NUM> may extend approximately up to the remainder of thickness <NUM>.

In another embodiment, first embedded capacitor <NUM> extends through substantially all of thickness <NUM>, thereby occupying substantially all of PWB <NUM>. Second capacitor <NUM> is embedded within a second PWB (not shown) similar to PWB <NUM>, the conductive vias of first capacitor <NUM> are electrically coupled to the conductive vias of capacitor <NUM>. For example, second capacitor <NUM> may be mounted to top surface <NUM> of first capacitor <NUM>, and bottom surface <NUM> of first capacitor <NUM> may be mounted to a PWB including electronic components, such as PWB <NUM> (shown in <FIG>).

Embodiments provided herein facilitate embedding within a PWB one or more multi-plate capacitors with multiple conductive vias. Such capacitors may be mounted to another PWB, and the attributes of such an embedded capacitor may be selected to achieve a desired capacitance. Further, multiple capacitors, each embedded in a PWB, may be stacked and mounted to a PWB that includes electronic components, such as integrated circuits, and the electronic components may be electrically coupled to the embedded capacitors. Accordingly, embodiments described herein enable inexpensively and efficiently packaging capacitors that exhibit low inductance and thermal properties similar to those of the PWBs to which the capacitors are mounted. Embodiments provided herein further facilitate creating a PWB-embedded capacitor of a shape and size that are based on unallocated area within a PWB to which the capacitor is to be mounted.

The methods and systems described herein are not limited to the specific embodiments described herein. For example, components of each system and/or steps of each method may be used and/or practiced independently and separately from other components and/or steps described herein. In addition, each component and/or step may also be used and/or practiced with other apparatus and methods.

Claim 1:
A printed wiring board (PWB) (<NUM>) defining a substantially planar area (<NUM>) and a PWB-embedded capacitor (<NUM>) mounted to the planar area, the PWB-embedded capacitor (<NUM>) comprising:
a plurality of first conductive plates (<NUM>) oriented substantially parallel to the planar area and extending from a first normal axis (<NUM>) towards a second normal axis (<NUM>), wherein the first and second normal axes are oriented substantially perpendicular to the planar area;
a plurality of second conductive plates (<NUM>) that are interleaved with said plurality of first conductive plates (<NUM>) and oriented substantially parallel to the planar area and extending from the second normal axis (<NUM>) towards the first normal axis (<NUM>), wherein at least one second conductive plate (<NUM>) extends between an adjacent pair of said first conductive plates (<NUM>);
a non-conductive material (<NUM>) extending between said second conductive plates (<NUM>) and said first conductive plates (<NUM>); and
a plurality of first conductive vias (<NUM>) aligned substantially collinear with the first normal axis and in contact with at least one of said first conductive plates (<NUM>), and a plurality of second conductive vias (<NUM>) aligned substantially collinear with the second normal axis (<NUM>) and in contact with said second conductive plate (<NUM>);
the PWB-embedded capacitor (<NUM>) being mounted to a surface of a first portion of the planar area of the PWB (<NUM>);
one or more electronic components (<NUM>) mounted on a surface of a second portion (<NUM>) of the planar area of said PWB (<NUM>), the area of the first portion being outside the second portion (<NUM>);
the first normal axis (<NUM>) and the second normal axis (<NUM>) being within the first portion of the planar area;
a first conductor (<NUM>) electrically coupling said one or more electronic components (<NUM>) to said plurality of first conductive vias; and
a second conductor (<NUM>) electrically coupling said one or more electronic components (<NUM>) to said plurality of second conductive vias;
characterized in that
said non-conductive material (<NUM>) is FR-<NUM>, and
wherein the PWB-embedded capacitor (<NUM>) is created using materials that are similar or identical to the materials used to create the printed wiring board (<NUM>), such that the PWB-embedded capacitor (<NUM>) exhibits thermal expansion that is similar or identical to the thermal expansion exhibited by the printed wiring board (<NUM>).