Patent Description:
One or more embodiments may be applied to multichannel audio systems, e.g. for sound systems mounted on board of vehicles such as motor cars.

Various audio applications may involve interfacing equipment capable of providing multiple audio streams (e.g. multichannel audio) with a device designed to receive these audio streams by using a single TDM serial audio interface.

Such an application may involve transporting signals from an arbitrary number of audio sources over a serial port in the presence of respective, different clock signals.

A desirable feature in this context is being able to derive these clock signals from sources such as PLL/Crystal generators without compromising accuracy of operation.

Document <CIT> discloses a method for transmitting and/or receiving a potential aggressor audio signal. The method includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.

Document <CIT> discloses a vehicle computer system having an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits to transfer data between different audio devices. Audio data is exchanged using a mapping overlay technique, in which the DMA circuits for two audio devices read and write to the same memory buffer.

Despite the extensive activity in the area, further improved solutions are desirable capable of providing such a feature.

An object of one or more embodiments is to contribute in providing such an improved solution.

According to one or more embodiments, such an object can be achieved by means of a method having the features set forth in the claims that follow.

One or more embodiments may relate to a corresponding circuit (e.g. an integrated circuit for use in implementing the method according to embodiments).

One or more embodiments may relate to a corresponding system (e.g. a sound system installed on board a motor vehicle).

One or more embodiments may relate to a corresponding computer program product loadable in the memory of at least one processing circuit (e.g., a MCU/CPU) and comprising software code portions for executing the acts of the method when the product is run on at least one processing circuit. As used herein, reference to such a computer program product is understood as being equivalent to reference to a computer-readable medium containing instructions for controlling the processing system in order to coordinate implementation of the method according to one or more embodiments. Reference to "at least one" processing circuit is intended to highlight the possibility for one or more embodiments to be implemented in modular and/or distributed form.

The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

One or more embodiments facilitate transporting signals from an arbitrary number of audio sources over a serial port in the presence of respective, different clock signals.

One or more embodiments make it possible to adopt a same approach when the serial interface acts as a slave interface (receiving clock from outside).

One or more embodiments can be implemented via software, requiring few MIPS (million instructions per second) with the capability of being implemented in an inexpensive CPU such as a micro computer unit (MCU).

One or more embodiments can use the direct memory access (DMA) end of transfer time (EOT) to evaluate relative speed and buffer positions between the receiver (RX) and the transmitter (TX) flow.

In one or more embodiments, the DMA EOT can be increased, by increasing the buffering in the RX and TX flow; a resulting EOT rate, with an acceptable audio latency, can be in the order of the milliseconds, which is compatible with running a tuning algorithm on a low-end MPU/CPU.

One or more embodiments make it possible to change the TDM slots number at the serial interface towards an external DSP and/or power amplifier without affecting the stream engine.

One or more embodiments may avoid using different PLL's for the serial interface and the audio subsystem, facilitating long-term audio flow with no buffer underrun/overrun.

The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

Various audio applications may involve using a single TDM (time domain multiplex) serial audio interface <NUM> in order to interface equipment capable of providing multiple audio streams (e.g. multichannel audio) with a device designed to receive these audio streams.

As exemplified in <FIG>, equipment capable of providing multiple audio streams can comprise an "audio source" AS comprising, e.g.:.

Of course, this list of possible sound sources is merely exemplary. The audio source AS may in fact comprise any number and types of sound signal sources.

Also, an audio source AS as exemplified herein may comprise "effect" circuitry E (of a type known per se) in order to apply effects to the sound signals e.g. CDS, TS, BTS.

Many such effects are currently used in the audio sector. A surround effect e.g. involving feeding a left/right difference signal to the rear speakers in a car audio system is a simple example of such an effect.

Whatever the specific details of implementation of the audio source AS, for the purposes herein it may be assumed that operation thereof is clocked by an input clock signal AUDIOclk. This may also apply, e.g. to clocking the operation of the effect circuitry E by an effects_rate clock signal derived from AUDIOclk.

As exemplified in <FIG>, the device designed to receive the audio streams CDS, TS, BTS from the audio source AS via a (single) TDM serial audio interface <NUM> can be and "audio receiver" AR comprising an (e.g. multichannel) amplifier, comprising a DAC for converting to analog the digital audio streams from the source AS and driving a set of speakers S (e.g. front, rear, and so on).

Again, whatever the specific details of implementation of the audio receiver AR, for the purposes herein it may be assumed that the audio samples CDS, TS, BTS (with possible effects applied thereto at E) are transported from the audio source to the audio receiver AR (which may be a distinct device from the source AS) by means of an audio serial interface <NUM> in a TDM configuration operated with a TDM output clock signal TDMclk.

Due to the synchronous nature of the audio signals, a serial clock capable of adequately transporting the signals from the audio source AS (received at an input end 10A of the interface <NUM>) to the audio receiver AR (coupled to the output end 10B of interface <NUM>) is desirable, without having to implement complex and expensive sample rate conversion (SRC) and without adversely affecting the sound signals (e.g. avoiding underrun/overrun at the boundary between the two clock domains AUDIOclk and TDMclk).

In that respect one may also note that an effects block as E, if present, may be clocked to work "over" samples at a clock rate e.g. effects _rate.

A way to avoid underrun/overrun at the boundary between the two clock domains (assuming the TDM serial clock TDMclk has a rate tdm_rate) may involve the following relationship: <MAT> where number _of_channels is the number of audio channels involved (e.g., the number of speakers S).

For that purpose, one may consider the possibility using a single clock generator (e.g. a phase-locked loop - or PLL generator) for clocking both the audio source AS (at the "input" rate AUDIOclk) and the TDM serial interface <NUM> (at the "output" rate TDMclk).

This may occur according to the general layout exemplified in <FIG>, that is with a (high frequency) clock signal from a PLL generator fed (in manner known per se) to a clock frequency divider chain comprising a first common divider stage <NUM> applying a first divider value DIV to obtain a (first) frequency divided signal PLLDIV followed by two further divider stages <NUM> and <NUM> applying to PLLDIV respective divider values TDMdiv and AUDIOdiv to generate TDMclk and AUDIOclk.

A way of avoiding jitter and underrun/overrun issues may involve applying certain constraints on the values DIV, TDMdiv, AUDIOdiv applied in PLL divider chain <NUM>, <NUM>, <NUM>, namely: <MAT> where SMPLsize denotes the size of the samples CDS, TS, BTS (e.g. <NUM> bit or <NUM> bit). For the sake of simplicity this may be assumed to be the same for the CDS, TS, BTS, which however is not a mandatory requirement.

In that respect it will also be noted that "effects rate" (and "tdm rate" as well) can be regarded just as particular values for AUDIOclk (and TDMclk), so that the expressions given above for tdm_rate and TDMclk apply.

If the ratio AUDIOdiv/TDMdiv is not an integer, the fractional, non-integer part will result in an offset between the TDM and AUDIO rates, in turn leading to an underrun/overrun.

A possible option might involve setting TDMdiv and obtaining therefrom AUDIOdiv = SMPLsize x Nch x TDMdiv in such a way to avoid any non-integer ratio problem.

In various audio applications AUDIOdiv admits (only) a limited set of values since audio sampling rates are standard (e.g. <NUM>, <NUM>, <NUM>, and so on).

The resulting value for AUDIOdiv thus obtained may be unsuited to be applied in a PLL divide logic as exemplified in <FIG>.

At least notionally, that issue may be addressed in various ways.

A first approach may involve increasing the complexity of the clock generator of the audio source AS, so that AUDIOclk can be set to any arbitrary value as desired.

Another approach may involve using two PLLs and implementing sample rate conversion to adapt the "source" clock to the "sink" serial clock.

Sample rate conversion may be complex to implement as an hardware device, thus taking silicon space (e.g. at the SoC level). A software implementation can be CPU consuming, and may also undesirably affect the overall audio quality.

One or more embodiments may overcome these drawbacks by resorting to a buffering mechanism between the two clock domains (e.g. AUDIOclk and TDMclk) and a state machine, which may be implemented as a software component.

As exemplified in <FIG>, in one or more embodiments, buffers <NUM> (e.g. BUFF0, BUFF1, BUFF2, BUFF3,. ) are written by one clock domain (e.g. AUDIOclk) and read by the other (e.g. TDMclk), with the data written and read in a DMA (direct memory access) act.

An advantage of such an approach may lie in that DMA can be run when samples are actually ready (in write acts: see DMA-write data in <FIG>) and when they are actually required (in read acts: see DMA-read data in <FIG>).

The DMA EOT (end of transfer) time is a function of (e.g. proportional to) the rate of the data source (in write acts) and the rate of the data sink (in read acts).

For instance, the DMA function will write data to the buffer at the AUDIOclk rate, and read data from the buffer at the TDMclk rate.

As exemplified in <FIG>, the software (MCU/CPU SW) running the system (e.g. at SoC level) monitors completion of the buffer read and write acts (DMA EOT) e.g. under the control of a DMA controller <NUM> providing DAM/EOT interrupts to a DMA driver <NUM>.

This will comprise the capability of identifying a buffer ID that is currently written (e.g. BUFFER = y with EOT = t1) and a buffer ID that is read (e.g. BUFFER = x with EOT = t0).

A state machine <NUM> may be provided configured to align the read/write buffer IDs with at least one buffer of distance (that is, |y-x|≥ <NUM>): in that way concurrent read/write acts on the same memory location can be avoided.

Also, EOT time are monitored with the state machine <NUM> configured to compensate PLL jitter and drift (e.g. via a "correction" signal sent to the PLL circuit) so that EOT time difference is less than a certain threshold dt (that is, |t1-t0|< dt).

For instance the correction signal may act on the PLL e.g. by changing the fractional part of the PLL divider (that is DIV in block <NUM> in <FIG>) producing the signal PLLDIV, thus causing a corresponding clock in the blocks shown (which can be either TDMclk or AUDIOclk: see again <FIG>) to run slower/faster, so that the buffers <NUM> and the respective delays can be adjusted to match an expected goal.

One or more embodiments are applicable to an interface point in an otherwise conventional serial audio port (e.g. MSP), within the framework of a single, low power, MPU/CPU circuit, with the capability of running different TDM schemes.

A method according to one or more embodiments may comprise:.

One or more embodiments may comprise writing resp. reading audio signal samples into resp. from buffers in the set of memory buffers during direct memory access, DMA, to said buffers.

One or more embodiments may comprise selecting (e.g. <NUM>) non-coincident memory buffers in the set of memory buffers for concurrently writing (see e.g. y in <FIG>) resp. reading (see e.g. x in <FIG>) audio signal samples into resp. from buffers in the set of memory buffers, wherein concurrent read/write acts on a same memory location are avoided.

One or more embodiments may comprise obtaining (see e.g. <FIG>) the TDM output clock frequency and the input clock frequency from:.

One or more embodiments may comprise controlling the clock frequency division of said master clock frequency by controlling the clock frequency divider value in said clock frequency division act providing said frequency divided clock signal.

In one or more embodiments, a circuit (e.g. <NUM>) may comprise:.

One or more embodiments may comprise a clock generator (see e.g. <NUM>, <NUM>, <NUM> in <FIG>) configured to produce the input clock frequency and the TDM output clock frequency by clock frequency division of a master clock frequency.

In one or more embodiments an audio system may comprise:.

One or more embodiments may comprise a computer program product (see e.g. MCU/CPU SW in <FIG>) loadable in the memory of at least one processing circuit (e.g. a MCU/CPU) and comprising software code portions for executing the acts of the method of one or more embodiments as a result of the product being run on at least one processing circuit.

Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

Claim 1:
A method, comprising:
- receiving plural input audio signal streams (CDS, TS, BTS, E) from an audio source (AS) clocked at an input clock frequency (AUDIOclk) and producing therefrom a time domain multiplex, TDM, serial output stream clocked at a TDM output clock frequency (TDMclk),
- obtaining the input clock frequency (AUDIOclk) and the TDM output clock frequency (TDMclk) from clock frequency division (DIV, TDMdiv, AUDIOdiv; <NUM>, <NUM>, <NUM>) of a master clock frequency (PLL),
- providing a set of memory buffers (<NUM>; BUFF0, BUFF1, BUFF2, BUFF3),
- writing audio signal samples from said input audio signal streams into buffers in the set of memory buffers (<NUM>; BUFF0, BUFF1, BUFF2, BUFF3) with said writing clocked at the input clock frequency (AUDIOclk),
- producing said TDM serial output stream from audio signal samples buffered in said set of memory buffers (<NUM>; BUFF0, BUFF1, BUFF2, BUFF3) by reading the buffered audio signal samples with said reading clocked at said TDM output clock frequency (TDMclk),
- providing a state machine (<NUM>) configured to monitor end of transfer, EOT, times (t1, t0) of said writing audio signal samples into buffers in the set of memory buffers (<NUM>; BUFF0, BUFF1, BUFF2, BUFF3) and of said reading audio signal samples from buffers in the set of memory buffers (<NUM>; BUFF0, BUFF1, BUFF2, BUFF3),
- producing, at said state machine (<NUM>), a correction signal as a function of said monitored end of transfer times (t1, t0) and controlling the clock frequency division (DIV, TDMdiv, AUDIOdiv; <NUM>, <NUM>, <NUM>) of said master clock frequency (PLL) via said correction signal by maintaining within a certain range the difference between the end of transfer times of writing audio signal samples into buffers in the set of memory buffers (<NUM>; BUFF0, BUFF1, BUFF2, BUFF3) and reading audio signal samples from buffers in the set of memory buffers (<NUM>; BUFF0, BUFF1, BUFF2, BUFF3).