Patent Description:
As an integration density of the image sensor increases, a size of each of the plurality of photodiodes, and an area of the optical black region, may decrease. If undesired light penetrates into the optical black region, however, then signal distortion may occur as a result of dark current generated in the optical black region.

<CIT> discloses methods for forming backside illuminated (BSI) image sensors having vertical light shields. Vertical light shields may be configured such that incoming light is blocked from reaching a portion of a pixel array formed on the backside illuminated image sensor. Vertical light shields may include horizontal portions that block direct illumination of dark pixels in the pixel array and vertical portions that block illumination of the dark pixels by reflected light. Vertical light shields may be formed from a dielectric layer, a layer of patterned light shield material formed over the dielectric layer and a passivation layer formed over the patterned light shield material. Vertical light shields may be formed by first etching a vertical trench in a device wafer layer over a portion of the pixel array and filling the vertical trench with light shield material to form the vertical light shield.

<CIT> discloses an optical isolation for optically black pixels in image sensors. Image sensors, such as backside illumination (BSI) image sensors, may have an active pixel array and an array having optically black pixels. Isolation structures such as a metal wall may be formed in a dielectric stack between an active pixel array and optically black pixels. Patterned shallow trench isolation regions or polysilicon regions may be formed in a substrate between an active pixel array and optically black pixels. An absorption region such as a germanium-doped absorption region may be formed in a substrate between an active pixel array and optically black pixels. Optical isolation and absorption regions may be formed in a ring surrounding an active pixel array.

<CIT> discloses an image sensor including a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region.

According to example embodiments of the inventive concepts, an image sensor as defined in claim <NUM> is disclosed. Further advantageous embodiments of the invention are disclosed in the dependent claims.

Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application.

<FIG> is a layout diagram of an image sensor according to example embodiments. <FIG> is a cross-sectional view taken along line II-II' of <FIG>, illustrating an image sensor according to example embodiments. <FIG> is an enlarged view of portion III of <FIG>. <FIG> is an enlarged view of portion IV of <FIG>. In <FIG>, a configuration element, e.g., a light shielding layer, of the image sensor is omitted for the brevity of illustration.

Referring to <FIG>, an image sensor <NUM> includes a pixel region APR, a dummy pixel region DR, an optical black region OBR, and a peripheral region PR.

The pixel region APR includes a plurality of photoelectric conversion regions <NUM>. The optical black region OBR is disposed on at least one side of the pixel region APR. The dummy pixel region DR is disposed between the pixel region APR and the optical black region OBR. The peripheral region PR surrounds the pixel region APR and the optical region OBR. The optical black region OBR and the peripheral region PR may not include (i.e., may be free of) the plurality of photoelectric conversion regions <NUM>.

The pixel region APR may be arranged in any shape or configuration. For example, as shown in <FIG>, in the pixel region APR, the plurality of photoelectric conversion regions <NUM> may be arranged in a matrix/array having rows and columns along a first direction (e.g., an X direction) parallel to an upper surface of a semiconductor substrate <NUM> and a second direction (e.g., a Y direction) parallel to the upper surface of the semiconductor substrate <NUM> and crossing the first direction (X direction). In the dummy pixel region DR, a first light shielding wall structure <NUM> extends in the second direction (Y direction). In plan view (e.g., as illustrated in <FIG>), the first light shielding wall structure <NUM> may extend in the second direction (Y direction) between the optical black region OBR and the pixel region APR by a length (i.e., the entire length) of the optical black region OBR in the second direction (Y direction).

A peripheral circuit region PCR and a conductive pad <NUM> are disposed in the peripheral region PR. The peripheral circuit region PCR may be disposed on one side of the pixel region APR, in plan view, but is not limited thereto. In some embodiments, the peripheral circuit region PCR may surround the pixel region APR and the optical black region OBR. The conductive pad <NUM> may be disposed in an edge region of the peripheral region PR. The peripheral region PR may be beside (e.g., on a side of) the optical black region OBR.

The semiconductor substrate <NUM> has a first surface 110F and a second surface 110B that are opposite to each other. Herein, a surface of the semiconductor substrate <NUM> on which a color filter <NUM> is disposed refers to the second surface 110B, and another surface of the semiconductor substrate <NUM> that is opposite to the second surface 110B refers to the first surface 110F. However, the inventive concepts are not limited thereto. The semiconductor substrate <NUM> may include a p-type semiconductor substrate. For example, the semiconductor substrate <NUM> may include a p-type silicon substrate. In some embodiments, the semiconductor substrate <NUM> may include a p-type bulk substrate and a p- or n- type epitaxial layer thereon. In some embodiments, the semiconductor substrate <NUM> may include an n-type bulk substrate and a p- or n- type epitaxial layer thereon. In some embodiments, the semiconductor substrate <NUM> may include an organic plastic substrate.

The plurality of photoelectric conversion regions <NUM> is disposed in the semiconductor substrate <NUM> in the pixel region APR. Each of the plurality of photoelectric conversion regions <NUM> includes a photodiode region <NUM> and a well region PW (<FIG>).

A device isolation region <NUM> is disposed between each of the plurality of photoelectric conversion regions <NUM>. The device isolation region <NUM> may be disposed between each of the plurality of photoelectric conversion regions <NUM> arranged in a matrix/array form and have a grid or mesh shape in plan view. The device isolation region <NUM> may be disposed in a device isolation trench 124T in (e.g., partly penetrating) the semiconductor substrate <NUM>. In some embodiments, a plurality of device isolation regions <NUM> may be respectively disposed between the plurality of photoelectric conversion regions <NUM> arranged in a matrix/array form and be arranged in a grid or mesh shape in plan view. For example, each device isolation region <NUM> may be between a respective pair of the photoelectric conversion regions <NUM>.

In some embodiments, the device isolation region <NUM> includes a backside insulation layer 124I that conformally extends along an inner surface of the device isolation trench 124T and a buried insulation layer <NUM> that is disposed on the backside insulation layer 124I and is in (e.g., partially or completely fills) the device isolation trench 124T. The backside insulation layer 124I may include metal oxide (e.g., hafnium oxide, aluminum oxide, or tantalum oxide). The backside insulation layer 124I may act as a negative fixed charge layer, but is not limited thereto. In some embodiments, the backside insulation layer 124I may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The buried insulation layer <NUM> may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

Referring to <FIG>, the backside insulation layer 124I and the buried insulation layer <NUM> may extend from the inside of the device isolation trench 124T to the second surface 110B of the semiconductor substrate <NUM>. For example, the backside insulation layer 124I may conformally extend along the inner surface of the device isolation trench 124T and along the second surface 110B of the semiconductor substrate <NUM>, and the buried insulation layer <NUM> may be disposed on the backside insulation layer 124I and cover the entirety of the second surface 110B of the semiconductor substrate <NUM>.

In some embodiments, the backside insulation layer 124I may be formed with a sufficient thickness to fill the device isolation trench 124T. In this case, the buried insulation layer <NUM> may not be formed in the device isolation trench 124T but cover the backside insulation layer 124I on the second surface 110B of the semiconductor substrate <NUM>.

A wiring structure, such as a first inner wiring structure <NUM>, is disposed on the first surface 110F of the semiconductor substrate <NUM>. The first inner wiring structure <NUM> may be formed of a stack of a plurality of conductive layers. The first inner wiring structure <NUM> may include, for example, polysilicon, metal, metal silicide, metal nitride, and/or a metal-containing layer. For example, the first inner wiring structure <NUM> may include tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, or doped polysilicon.

A first interlayer insulation layer <NUM> is disposed on the first surface 110F of the semiconductor substrate <NUM> to cover the first inner wiring structure <NUM>. The first interlayer insulation layer <NUM> may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

Referring to <FIG>, a device isolation layer STI that defines an active region <NUM> and a floating diffusion region FD is formed in/on the first surface 110F of the semiconductor substrate <NUM>. Gate electrodes constituting a plurality of transistors may be formed on the first surface 110F of the semiconductor substrate <NUM>. The first inner wiring structure <NUM> may be electrically connected to the gate electrodes and/or the active region <NUM>. The gate electrodes may be covered by the first interlayer insulation layer <NUM>.

For example, the plurality of transistors may include a transfer transistor TG, which transfers charges generated by each photoelectric conversion region <NUM> to a floating diffusion region FD, a reset transistor which periodically resets the charges stored in the floating diffusion region FD, a drive transistor which serves as a source follower buffer amplifier and buffers signals based on the charges stored in the floating diffusion region FD, and a selection transistor which performs switching and addressing to select the pixel region APR. However, the plurality of transistors are not limited thereto.

A guide pattern <NUM> is disposed on the buried insulation layer <NUM> in the pixel region APR. The guide pattern <NUM> may have a mesh or grid shape. The guide pattern <NUM> may inhibit/prevent light that is obliquely incident into one of the plurality of photoelectric conversion regions <NUM> from penetrating into another one of the plurality of photoelectric conversion regions <NUM> adjacent thereto. The guide pattern <NUM> may include metal (e.g., tungsten, aluminum, titanium, ruthenium, cobalt, nickel, copper, gold, silver, or platinum).

A passivation layer <NUM> is disposed on the second surface 110B of the semiconductor substrate <NUM> to overlap/cover the buried insulation layer <NUM> and the guide pattern <NUM>. A color filter <NUM> and a micro-lens <NUM> are disposed on the passivation layer <NUM>. A supporting substrate <NUM> is selectively disposed on the first surface 110F of the semiconductor substrate <NUM>.

The optical black region OBR is disposed on a side of the pixel region APR. The optical black region OBR may have a structure similar to that of the pixel region APR. For example, the device isolation region <NUM> partly penetrating the semiconductor substrate <NUM> may be disposed in the optical black region OBR. In the optical black region OBR, the device isolation region <NUM> may include the device isolation trench 124T partly penetrating the semiconductor substrate <NUM>, the backside insulation layer 124I on the inner surface of the device isolation trench 124T, and the buried insulation layer <NUM> filling the device isolation trench 124T. As shown in <FIG>, the photodiode region <NUM>, which is in the photoelectric conversion region <NUM> in the pixel region APR, may be omitted from the optical black region OBR, but the inventive concepts are not limited thereto. For example, the photodiode region <NUM> may, in some embodiments, be formed in the semiconductor substrate <NUM> in the optical black region OBR.

A light shielding layer <NUM> is disposed on the second surface 110B of the semiconductor substrate <NUM> in the optical black region OBR. The light shielding layer <NUM> may include metal (e.g., tungsten, aluminum, titanium, ruthenium, cobalt, nickel, copper, gold, silver, or platinum). The light shielding layer <NUM> may be disposed on the buried insulation layer <NUM> and overlap/cover the entirety of the optical black region OBR. The passivation layer <NUM> is disposed on the light shielding layer <NUM>.

The optical black region OBR may act as a reference pixel with respect to the pixel region APR and act to automatically compensate a dark current signal. For example, the light shielding layer <NUM> may block incidence of light into the reference pixel in the optical black region OBR. By measuring a reference charge quantity generated in the reference pixel shielded from light and comparing the quantity of reference charge to a sensed charge quantity generated from the pixel region APR, a light signal input from the pixel region APR may be calculated from a difference between the sensed charge quantity and the reference charge quantity.

The dummy pixel region DR is disposed between the optical black region OBR and the pixel region APR. The dummy pixel region DR may be configured to inhibit/prevent a patterning failure from occurring during a process of forming the color filter <NUM> on the pixel region DR, and also inhibit/prevent the light from penetrating into the optical black region OBR.

The first light shielding wall structure <NUM> is disposed in the dummy pixel region DR. The first light shielding wall structure <NUM> may completely penetrate the semiconductor substrate <NUM>. For example, the first light shielding wall structure <NUM> may continuously extend from the second surface 110B of the semiconductor substrate <NUM> to the first surface 110F of the semiconductor substrate <NUM>. The light shielding layer <NUM> may extend from the optical black region OBR to the dummy pixel region DR to be connected to the first light shielding wall structure <NUM>.

The first light shielding wall structure <NUM> includes a light shielding insulation layer <NUM> on an inner surface of a first light shielding trench 150T that penetrates the semiconductor substrate <NUM> and a light shielding metal layer <NUM> on the light shielding insulation layer <NUM> to partially or completely fill the first light shielding trench 150T. Moreover, the first light shielding wall structure <NUM> is physically spaced apart, and electrically isolated, from the first inner wiring structure <NUM>.

Referring to <FIG>, the first light shielding trench 150T is in and completely penetrates the semiconductor substrate <NUM> and extends in the second direction (Y direction). The first light shielding trench 150T may have a first width 150W1 in the first direction (X direction) at the same level as (i.e., at a level coplanar with) the second surface 110B of the semiconductor substrate <NUM> and a second width 150W2 in the first direction (X direction) at the same level as (i.e., at a level coplanar with) the first surface 110F of the semiconductor substrate <NUM>. The first width 150W1 may be greater than the second width 150W2. For example, the first light shielding wall structure <NUM> may have the first width 150W1 in the first direction (X direction) at the same level as the second surface 110B of the semiconductor substrate <NUM> and the second width 150W2, that is less than the first width 150W1, in the first direction (X direction) at the same level as the first surface 110F of the semiconductor substrate <NUM>. Accordingly, the width of the first light shielding wall structure <NUM> may be tapered toward the first surface 110F of the semiconductor substrate <NUM>.

The light shielding insulation layer <NUM> conformally extends along the inner surface of the first light shielding trench 150T and contacts the first interlayer insulation layer <NUM> on a lower surface of the first light shielding trench 150T. The light shielding insulation layer <NUM> may extend onto the second surface 110B of the semiconductor substrate <NUM> to be connected to the backside insulation layer 124I, such that the light shielding insulation layer <NUM> is integrally coupled/connected to the backside insulation layer 124I.

In some embodiments, the light shielding insulation layer <NUM> may include metal oxide (e.g., hafnium oxide, aluminum oxide, or tantalum oxide). In some embodiments, the light shielding insulation layer <NUM> may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). In some embodiments, the light shielding insulation layer <NUM> may include the same material as the backside insulation layer 124I. The light shielding insulation layer <NUM> may be formed by the same process as forming the backside insulation layer 124I. However, the inventive concepts are not limited thereto. For example, the light shielding insulation layer <NUM> and the backside insulation layer 124I may be formed of different materials.

The light shielding metal layer <NUM> completely fills the first light shielding trench 150T and contacts the light shielding layer <NUM>. The light shielding metal layer <NUM> may include metal (e.g., tungsten, aluminum, titanium, ruthenium, cobalt, nickel, copper, gold, silver, or platinum). In some embodiments, the light shielding metal layer <NUM> may include the same material (e.g., the same metal) as the light shielding layer <NUM> and be formed by the same process as forming the light shielding layer <NUM>. For example, the light shielding metal layer <NUM> and the light shielding layer <NUM> may be formed of a continuous material layer, and/or be integrally coupled/connected to each other. In some embodiments, the light shielding metal layer <NUM> may include a different material from the light shielding layer <NUM>.

Referring to <FIG>, the optical black region OBR is arranged on opposite sides of the pixel region APR. The first light shielding wall structure <NUM> extends in the second direction (Y direction) between the optical black region OBR and pixel region APR by a length (i.e., the entire length) of the dummy pixel region DR in the second direction (Y direction). In addition, referring to <FIG>, the first light shielding wall structure <NUM> may have a first side 150S1 facing the pixel region APR and a second side 150S2 facing the optical black region OBR, that extend in a longitudinal direction (i.e., the second direction (Y direction)).

The first light shielding wall structure <NUM> continuously extends from the second surface 110B of the semiconductor substrate <NUM> to the first surface 110F of the semiconductor substrate <NUM> and may include the same metal material as the light shielding layer <NUM>. Thus, undesired stray light may be inhibited/prevented from penetrating from the pixel region APR into the optical black region OBR. For example, the long wavelength light that is obliquely incident into the pixel region APR may be blocked by the first side 150S1 of the first light shielding wall structure <NUM>, thus inhibiting/preventing the undesired light penetration or leakage into the optical black region OBR. In addition, electrons generated by the light received in the pixel region APR may be blocked by the first side 150S1 of the first light shielding wall structure <NUM>, such that a dark current signal may be inhibited/prevented from entering in the optical black region OBR.

The color filter <NUM> and the micro-lens <NUM> are disposed on the passivation layer <NUM> in the dummy pixel region DR adjacent to the pixel region APR. Thus, a patterning failure of the color filter <NUM> in the pixel region APR caused by a difference in a thickness of the passivation layer <NUM> in the pixel region APR and the optical black region OBR may be inhibited/prevented.

A through via trench 172T is disposed in the peripheral region PR and penetrates the semiconductor substrate <NUM>. A through via <NUM> is disposed in the through via trench 172T to be electrically connected to the first inner wiring structure <NUM>. The through via <NUM> may provide a conductive pathway through the semiconductor substrate <NUM> from the second surface 110B of the semiconductor substrate <NUM> to the first surface 110F of the semiconductor substrate <NUM>. A conductive pad <NUM> is disposed on the through via <NUM>. A pad isolation region <NUM> penetrates the semiconductor substrate <NUM> and surrounds the through via <NUM> and the conductive pad <NUM>. The pad isolation region <NUM> includes the backside insulation layer 124I on an inner surface of a pad isolation trench 128T which penetrates the semiconductor substrate <NUM>, and includes the buried insulation layer <NUM> on the backside insulation layer 124I to partially or completely fill the pad isolation trench 128T. The through via <NUM> and/or the conductive pad <NUM> may be electrically insulated from a portion of the semiconductor substrate <NUM> in the optical black region OBR or the pixel region APR by the pad isolation region <NUM>.

Referring to <FIG>, the conductive pad <NUM> is disposed on the through via <NUM>. The conductive pad <NUM> and the through via <NUM> may vertically overlap each other in a third direction (e.g., a Z direction) perpendicular to the second surface 110B of the semiconductor substrate <NUM>, but are not limited thereto. For example, the through via <NUM> and the conductive pad <NUM> may, in some embodiments, be disposed not to vertically overlap each other, but a conductive layer may be further provided on the second surface 110B of the semiconductor substrate <NUM> to electrically connect the through via <NUM> and the conductive pad <NUM>. In addition, an outer connection terminal may be disposed on the conductive pad <NUM>, and an image signal, a control signal, and/or a power voltage may be provided or transmitted to the first inner wiring structure <NUM> through the outer connection terminal.

In the image sensor <NUM> according to example embodiments, as the first light shielding wall structure <NUM> continuously extends from the second surface 110B of the semiconductor substrate <NUM> to the first surface 110F of the semiconductor substrate <NUM> in the dummy pixel region DR, the optical black region OBR may be protected from penetration of undesired stray light or electrons. Thus, a dark current signal may be inhibited/prevented from entering in the optical black region OBR such that a noise signal variation of the image sensor <NUM> may be reduced.

<FIG> is a layout diagram of an image sensor according to example embodiments. <FIG> is a cross-sectional view taken along line VI-VI' of <FIG>. In <FIG> and <FIG>, the same reference numerals are used to denote the same elements as in <FIG>.

Referring to <FIG> and <FIG>, in an image sensor 100A, a pair of first light shielding wall structures 150A are disposed in a dummy pixel region DR1 between the optical black region OBR and the pixel region APR. The pair of first light shielding wall structures 150A may be spaced a predetermined distance apart from each other and extend in the second direction (Y direction) by a length (i.e., the entire length) of the dummy pixel region DR1 in the second direction (Y direction). The light shielding layer <NUM> may be disposed to vertically overlap the pair of first light shielding wall structures 150A in the dummy pixel region DR1.

In some embodiments, the semiconductor substrate <NUM> further includes a guard ring region DR2 between the peripheral region PR and the optical black region OBR. The guard ring region DR2 may be adjacent to the optical black region OBR and extend in the second direction (Y direction). A second light shielding wall structure <NUM> may extend in the second direction (Y direction) in the guard ring region DR2. The second light shielding wall structure <NUM> may be formed of a structure similar to that of any of the pair of first light shielding wall structures 150A. For example, the second light shielding wall structure <NUM> includes the light shielding insulation layer <NUM> on an inner surface of a second light shielding trench 156T which penetrates the semiconductor substrate <NUM>, and includes the light shielding metal layer <NUM> disposed on the light shielding insulation layer <NUM> to partially or completely fill the second light shielding trench 156T.

The second light shielding wall structure <NUM> may be disposed between the optical black region OBR and the conductive pad <NUM> or between the optical black region OBR and the peripheral circuit region PCR. The second light shielding wall structure <NUM> may inhibit/prevent light or electrons generated in a certain circuit in the peripheral circuit region PCR from penetrating into the optical black region OBR.

In the image sensor 100A according to example embodiments, as the pair of first light shielding wall structures 150A are disposed between the optical black region OBR and the pixel region APR, undesired stray light or electrons may be inhibited/prevented from penetrating from the pixel region APR into the optical black region OBR by the pair of first light shielding wall structures 150A. Light that is obliquely incident into the optical black region OBR may be blocked by the pair of first light shielding wall structures 150A. In addition, light that is irradiated into the first interlayer insulation layer <NUM> and then is reflected or scattered from the first inner wiring structure <NUM> in the first interlayer insulation layer <NUM>, may be inhibited/prevented from being incident into the optical black region OBR by the pair of first light shielding wall structures 150A. The second light shielding wall structure <NUM> may inhibit/prevent light or electrons generated in a certain circuit in the peripheral circuit region PCR from penetrating into the optical black region OBR. Thus, a noise signal variation of the image sensor 100A may be reduced.

<FIG> is a cross-sectional view of an image sensor according to example embodiments. <FIG> is a cross-sectional view taken along line VI-VI' of <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG>.

Referring to <FIG>, in an image sensor 100B, a third light shielding wall structure <NUM> is disposed spaced apart from the first light shielding wall structure 150A in the dummy pixel region DR1. The third light shielding wall structure <NUM> includes the light shielding metal layer <NUM> in a third light shielding trench 158T penetrating the semiconductor substrate <NUM>. The backside insulation layer 124I (and the light shielding insulation layer <NUM>) may not be disposed in the third light shielding trench 158T, such that the light shielding metal layer <NUM> may directly contact the semiconductor substrate <NUM> in the third light shielding trench 158T.

The third light shielding wall structure <NUM> may penetrate the semiconductor substrate <NUM> and extend into the first interlayer insulation layer <NUM> on the first surface 110F of the semiconductor substrate <NUM>. For example, a bottom portion of the third light shielding wall structure <NUM> may be surrounded by the first interlayer insulation layer <NUM>. A lower surface of the third light shielding wall structure <NUM> may be substantially at the same level as (e.g., at a level coplanar with) a lower surface of the through via <NUM>. In some embodiments, the third light shielding wall structure <NUM> may be connected to the first inner wiring structure <NUM>. In some embodiments, the first interlayer insulation layer <NUM> may physically and electrically separate the third light shielding wall structure <NUM> from the first inner wiring structure <NUM>.

In some embodiments, the third light shielding trench 158T may be formed by the same process as forming the through via trench 172T. An upper portion of the third light shielding trench 158T may penetrate the backside insulation layer 124I and the buried insulation layer <NUM>. A sidewall of an upper portion of the third light shielding wall structure <NUM> may be surrounded by the backside insulation layer 124I and the buried insulation layer <NUM>.

In the image sensor 100B according to example embodiments, as the first light shielding wall structure 150A and the third light shielding wall structure <NUM> are disposed between the optical black region OBR and the pixel region APR, undesired stray light or electrons may be inhibited/prevented from penetrating from the pixel region APR into the optical black region OBR by the first light shielding wall structure 150A and the third light shielding wall structure <NUM>. Light that is obliquely incident into the optical black region OBR may be blocked by the first light shielding wall structure 150A and the third light shielding wall structure <NUM>. In addition, light that is irradiated into the first interlayer insulation layer <NUM> and then is reflected or scattered from the first inner wiring structure <NUM> in the first interlayer insulation layer <NUM>, may be inhibited/prevented from being incident into the optical black region OBR by the first light shielding wall structure 150A and the third light shielding wall structure <NUM>. Thus, a noise signal variation of the image sensor 100B may be reduced.

Referring to <FIG>, in an image sensor 100C, a reflection blocking/prevention metal layer <NUM> is further disposed on the light shielding layer <NUM>, the guide pattern <NUM>, and the conductive pad <NUM>. The reflection blocking/prevention metal layer <NUM> may include metal (e.g., titanium nitride, tantalum nitride, titanium, or tantalum).

In some embodiments, after the first light shielding trench 150T, the second light shielding trench 156T, and the through via trench 172T are formed, a metal layer is formed on the second surface 110B of the semiconductor substrate <NUM> in (e.g., to fill) the first light shielding trench 150T, the second light shielding trench 156T, and the through via trench 172T. In some embodiments, a reflection blocking/prevention preliminary metal layer is formed on the metal layer, and then the reflection blocking/prevention preliminary layer and the metal layer are simultaneously or sequentially patterned to form the light shielding layer <NUM>, the guide pattern <NUM>, the conductive pad <NUM>, and the reflection blocking/prevention metal layer <NUM>.

Referring to <FIG>, in an image sensor 100D, a device isolation region 124A is disposed to penetrate the semiconductor substrate <NUM> from the first surface 110F of the semiconductor substrate <NUM> to the second surface 110B of the semiconductor substrate <NUM>. The device isolation region 124A includes a device isolation trench 124TA and a device isolation insulation layer 124IA in (e.g., partially or completely filling) the device isolation trench 124TA. In the pixel region APR, the buried insulation layer <NUM> may not be formed in the device isolation trench 124TA, but be formed on the entire second surface 110B of the semiconductor substrate <NUM>.

In some embodiments, the device isolation insulation layer 124IA may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). In some embodiments, an insulation liner may be conformally formed on an inner surface of the device isolation trench 124TA, and the device isolation insulation layer 124IA may be disposed on the insulation liner and fill the device isolation trench 124TA.

In some embodiments, the device isolation region 124A may include an insulation liner that is conformally formed on the inner surface of the device isolation trench 124TA and include a conductive buried layer which is on the insulation liner and fills the device isolation trench 124TA.

<FIG> is a layout diagram of an image sensor according to example embodiments. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG>.

Referring to <FIG>, in an image sensor 100E, the optical black region OBR entirely (e.g., continuously, on four sides) surrounds the pixel region APR. The dummy pixel region DR is disposed between the optical black region OBR and the pixel region APR and entirely surrounds the pixel region APR. For example, when the pixel region APR has a rectangular shape, the optical black region OBR may surround four sides of the pixel region APR with the dummy pixel region DR therebetween.

A first light shielding wall structure 150B is disposed in the dummy pixel region DR and defines a boundary of (e.g., surrounds) the pixel region APR. For example, the first light shielding wall structure 150B may face the four sides of the pixel region APR. A first side 150S1 of the first light shielding wall structure 150B faces the pixel region APR. A second side 150S2 of the first light shielding wall structure 150B is opposite to the first side 150S1 thereof and faces the optical black region OBR. Since the first light shielding wall structure 150B surrounding the pixel region APR penetrates the semiconductor substrate <NUM> (see <FIG>), a portion of the semiconductor substrate <NUM> in the pixel region APR and another portion of the semiconductor substrate <NUM> in the optical black region OBR may be completely physically and electrically separated from each other. Thus, undesired stray light or electrons may be inhibited/prevented from penetrating from the pixel region APR to the optical black region OBR, such that a noise signal variation of the image sensor 100E may be reduced.

Referring to <FIG>, in an image sensor 100F, a dummy pixel region DR3 surrounds the optical black region OBR. A first light shielding wall structure 150C and a second light shielding wall structure 156A are disposed in the in the dummy pixel region DR3 and are connected to each other. For example, the first light shielding wall structure 150C may extend in the second direction (Y direction) between the pixel region APR and the optical black region OBR. The second light shielding wall structure 156A may extend in the second direction (Y direction) between the optical black region OBR and the peripheral region PR. An extension portion 156AE of the second light shielding wall structure 156A may extend in the first direction (X direction) to be connected to an end portion of the first light shielding wall structure 150C.

Since the first light shielding wall structure 150C and the second light shielding wall structure 156A collectively completely surround the optical black region OBR, undesired stray light or electrons may be inhibited/prevented from penetrating from the pixel region APR to the optical black region OBR. Thus, a noise signal variation of the image sensor 100E may be reduced.

Referring to <FIG>, in an image sensor <NUM>, a pair of first light shielding wall structures 150D and a second light shielding wall structure 156A are disposed in the dummy pixel region DR3. One of the pair of first light shielding wall structures 150D and the second light shielding wall structure 156A are connected to each other. For example, the pair of first light shielding wall structures 150D may extend in the second direction (Y direction) between the pixel region APR and the optical black region OBR. The second light shielding wall structure 156A may extend in the second direction (Y direction) between the optical black region OBR and the peripheral region PR. The extension portion 156AE of the second light shielding wall structure 156A may extend in the first direction (X direction) to be connected to an end portion of one of the pair of first light shielding wall structures 150D.

Since the pair of first light shielding wall structures 150D and the second light shielding wall structure 156A collectively completely surround the optical black region OBR, undesired stray light or electrons may be inhibited/prevented from penetrating from the pixel region APR and the peripheral region PR to the optical black region OBR. Thus, a noise signal variation of the image sensor <NUM> may be reduced.

Referring to <FIG>, in an image sensor <NUM>, the optical black region OBR surrounds four sides of the pixel region APR. The dummy pixel region DR1 is disposed between the optical black region OBR and the pixel region APR. The guard ring region DR2 is disposed between the optical black region OBR and the peripheral region PR and surrounds four sides of the optical black region OBR. The first light shielding wall structure 150B is disposed in the dummy pixel region DR1. A second light shielding wall structure 156B is disposed in the guard ring region DR2.

Referring to <FIG>, an image sensor 100I has a stack structure in which the semiconductor substrate <NUM> and a lower substrate <NUM> are bonded to each other.

An active region defined by a device isolation layer <NUM> may be formed in the lower substrate <NUM>. A gate structure <NUM> is disposed on the lower substrate <NUM>. The gate structure <NUM> may constitute each of a plurality of CMOS transistors that provides a certain signal to each photoelectric conversion region <NUM> of the pixel region APR and controls an output signal from each photoelectric conversion region <NUM>. For example, the transistors may constitute various kinds of logic circuits (e.g., a timing generator, a row decoder, a column driver, a correlated double sampler (CDS), an analog to digital converter (ADC), a latch, a column decoder), but are not limited thereto.

A second inner wiring structure <NUM> is disposed on the lower substrate <NUM>. The second inner wiring structure <NUM> may be formed of a multi-layered stack structure. A second interlayer insulation layer <NUM> is disposed on the lower substrate <NUM> to cover the gate structure <NUM> and the second inner wiring structure <NUM>.

The first interlayer insulation layer <NUM> may be bonded to the second interlayer insulation layer <NUM>. In some embodiments, the first and second interlayer insulation layers <NUM> and <NUM> may be bonded to each other by an oxide-oxide direct bonding method. In some embodiments, an adhesive may be interposed between the first interlayer insulation layer <NUM> and the second interlayer insulation layer <NUM>.

A through via trench 172TA penetrates the semiconductor substrate <NUM> and the first interlayer insulation layer <NUM> and is connected to a portion of the second inner wiring structure <NUM>. A through via 172A is connected to both of the first inner wiring structure <NUM> and the second inner wiring structure <NUM>. A bottom portion of the through via 172A may be surrounded by the second interlayer insulation layer <NUM>.

<FIG> are cross-sectional views of a method of manufacturing an image sensor according to example embodiments. <FIG> are cross-sectional views taken along line VI-VI' of <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG>.

Referring to <FIG>, the semiconductor substrate <NUM> having the first surface 110F and the second surface 110B that are opposite to each other are provided/prepared.

The photoelectric conversion region <NUM> and a well region may be formed in the semiconductor substrate <NUM> by performing an ion implantation process on the first surface 110F of the semiconductor substrate <NUM>. For example, the photoelectric conversion region <NUM> may be formed by doping an n-type impurity, and the well region may be formed by doping a p-type impurity.

The first inner wiring structure <NUM> and the first interlayer insulation layer <NUM> covering the first inner wiring structure <NUM> may be formed on the first surface 110F of the semiconductor substrate <NUM>. For example, the first inner wiring structure <NUM> and the first interlayer insulation layer <NUM> may be formed by repeatedly performing process steps in which a conductive layer is formed on the first surface 110F of the semiconductor substrate <NUM>, the conductive layer is patterned, and an insulating layer is formed to cover the patterned conductive layer.

A supporting substrate <NUM> is bonded to the first surface 110F of the semiconductor substrate <NUM>.

A first mask pattern may be formed on the second surface 110B of the semiconductor substrate <NUM>. The semiconductor substrate <NUM> may be etched from the second surface 110B thereof using the first mask pattern as an etch mask, thus forming the first light shielding trench 150T, the second light shielding trench 156T, and the pad isolation trench 128T.

The first light shielding trench 150T, the second light shielding trench 156T, and the pad isolation trench 128T may completely penetrate the semiconductor substrate <NUM>. Thus, an upper surface of the first interlayer insulation layer <NUM> may be exposed on/as lower surfaces of the first light shielding trench 150T, the second light shielding trench 156T, and the pad isolation trench 128T.

Referring to <FIG>, a second mask pattern may be formed on the second surface 110B of the semiconductor substrate <NUM>. The semiconductor substrate <NUM> may be etched from the second surface 110B thereof using the second mask pattern as an etch mask, thus forming the device isolation trench 124T.

In some embodiments, the device isolation trench 124T may be formed to partly penetrate the semiconductor substrate <NUM> to expose a portion of the semiconductor substrate <NUM> at/as a lower surface thereof.

In some embodiments, the device isolation trench 124T may be formed to partly penetrate the semiconductor substrate <NUM>, and an ion implantation process may be performed on a portion of the semiconductor substrate <NUM> exposed on/as a lower surface of the device isolation trench 124T to form an additional impurity region below the device isolation trench 124T.

Referring to <FIG>, an insulation material may be deposited on the second surface 110B of the semiconductor substrate <NUM> and inner surfaces of the device isolation trench 124T, the pad isolation trench 128T, the first light shielding trench 150T, and the second light shielding trench 156T, by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, thus forming the backside insulation layer 124I on the second surface 110B of the semiconductor substrate <NUM> and inner surfaces of the device isolation trench 124T and the pad isolation trench 128T, and forming the light shielding insulation layer <NUM> on the inner surfaces of the first light shielding trench 150T and the second light shielding trench 156T. Accordingly, the backside insulation layer 124I and the light shielding insulation layer <NUM> may be the same insulation layer/material.

An insulation layer may be formed on the second surface 110B of the semiconductor substrate <NUM> to fill the device isolation trench 124T, the pad isolation trench 128T, the first light shielding trench 150T, and the second light shielding trench 156T, thus forming the buried insulation layer <NUM> that fills the device isolation trench 124T, the pad isolation trench 128T, the first light shielding trench 150T, and the second light shielding trench 156T. The buried insulation layer <NUM> may be formed on the second surface 110B of the semiconductor substrate <NUM> with a predetermined thickness.

In some embodiments, an etch back process may be performed on the inner surfaces of the first light shielding trench 150T and the second light shielding trench 156T, thus removing the portions of the buried insulation layer <NUM> that fill the first light shielding trench 150T and the second light shielding trench 156T.

In some embodiments, the backside insulation layer 124I may be formed with a sufficient thickness to completely fill the device isolation trench 124T and the pad isolation trench 128T. The buried insulation layer <NUM> may be formed on the second surface 110B of the semiconductor substrate <NUM> using a low or poor step coverage material. In this case, since the buried insulation layer <NUM> is mainly formed on the second surface 110B of the semiconductor substrate <NUM> and does not fill the first and second light shielding trenches 150T and 156T, the aforementioned etch back process may be omitted.

Referring to <FIG>, a third mask pattern may be formed on the buried insulation layer <NUM>. The buried insulation layer <NUM>, the backside insulation layer 124I, the semiconductor substrate <NUM>, and the first interlayer insulation layer <NUM> are etched using the third mask pattern as an etch mask to form the through via trench 172T. The first inner wiring structure <NUM> may be exposed on/as a lower surface of the through via trench 172T.

Referring to <FIG>, a metal layer 160P is formed to fill the first light shielding trench 150T, the second light shielding trench 156T, and the through via trench 172T. The metal layer 160P may be formed by sequentially forming a first metal layer and a second metal layer. The first metal layer may be conformally formed on the inner surface of the first light shielding trench 150T, the inner surface of the second light shielding trench 156T, and an inner surface of the through via trench 172T. The second metal layer may be formed on the first metal layer to completely fill the first light shielding trench 150T, the second light shielding trench 156T, and the through via trench 172T.

For example, the first metal layer may be formed using metal (e.g., titanium, titanium nitride, tantalum, tantalum nitride, titanium tungsten, tungsten, aluminum, cobalt, nickel, or copper) by a CVD process or an ALD process. The second metal layer may be formed using metal (e.g., tungsten, aluminum, cobalt, nickel, or copper) by a CVD process, an ALD process, or a plating process.

As the first light shielding trench 150T, the second light shielding trench 156T, and the through via trench 172T are completely filled with the metal layer 160P, the first light shielding wall structure 150A, the second light shielding wall structure <NUM>, and the through via <NUM> are formed in the first light shielding trench 150T, the second light shielding trench 156T, and the through via trench 172T, respectively.

Referring to <FIG>, a fourth mask pattern may be formed on the metal layer 160P. The metal layer 160P is patterned using the fourth mask pattern as an etch mask to form the light shielding layer <NUM>, the guide pattern <NUM>, and the conductive pad <NUM>.

Referring to <FIG>, the passivation layer <NUM> is formed on the second surface 110B of the semiconductor substrate <NUM> on (e.g., to partially or completely cover) the light shielding layer <NUM>, the guide pattern <NUM>, and the conductive pad <NUM>. The passivation layer <NUM> is patterned to expose an upper surface of the conductive pad <NUM>.

Claim 1:
An image sensor comprising:
a semiconductor substrate (<NUM>) comprising a pixel region (APR) and an optical black region (OBR);
a plurality of photoelectric conversion regions (<NUM>) in the pixel region (APR);
a wiring structure (<NUM>) on a first surface (110F) of the semiconductor substrate (<NUM>);
a light shielding layer (<NUM>) on a second surface (110B) of the semiconductor substrate <NUM>) in the optical black region (OBR); and
a first light shielding wall structure (<NUM>; 150A; 150B; 150C; 150D) penetrating the semiconductor substrate (<NUM>) in a third direction (Z-direction) which is perpendicular to the second surface (110B) between the pixel region (APR) and the optical black region (OBR),
wherein the light shielding layer (<NUM>) vertically overlaps and connects to the first light shielding wall structure (<NUM>; 150A; 150B; 150C; 150D), wherein the first light shielding wall structure (<NUM>; 150A; 150B; 150C; 150D) comprises:
an insulation layer (<NUM>) in a trench (152T) that extends in the semiconductor substrate (<NUM>) from the first surface (110F) of the semiconductor substrate (<NUM>) to the second surface (110B) of the semiconductor substrate (<NUM>); and
a metal layer (<NUM>) on the insulation layer (<NUM>) in the trench (152T) and
characterized in that the first light shielding wall structure (<NUM>; 150A; 150B; 150C; 150D) continuously extends from the first surface (110F) of the semiconductor substrate (<NUM>) to the second surface (110B) of the semiconductor substrate (<NUM>).