Patent Description:
Some integrated circuit (IC) devices include one or more dies manufactured on a substrate. The substrate typically comprises one or more semiconductor materials. In IC devices that comprise multiple transceivers and/or transmitter/receiver pairs, the transceivers must typically be electrically isolated from one another.

In semiconductor production, "doping" refers to the intentional introduction of impurities into a semiconductor material. Such impurities modulate the electrical properties of the semiconductor. In general, an increase in dopant concentration leads to an increase in conductivity.

In practice, an "intrinsic" semiconductor may refer to a rather pure semiconductor material. An "extrinsic" semiconductor may refer to a lightly or moderately doped semiconductor. A "degenerate" semiconductor may refer to a semiconductor so highly doped that it appears to be a conductor rather than a semiconductor. Such degenerate semiconductors may be used in place of metal materials in modem IC devices. As an example, silicon may be considered degenerate at room temperature when doped at concentrations above about <NUM><NUM> cm-<NUM> and/or a proportion of impurity to silicon on the order of parts per thousand.

A method for manufacturing a capacitor is disclosed as recited in claim <NUM>. A capacitor is disclosed as recited in claim <NUM>.

The teachings of the present disclosure are applied to the manufacture and design of capacitors. According to the claimed invention, a capacitor is formed on a heavily doped substrate. A method for manufacturing a capacitor includes: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

According to the claimed invention, the method include depositing a passivation layer on the first metal layer and patterning and etching the passivation layer to expose a portion of the first metal layer.

According to the claimed invention, the method include: depositing a passivation layer on the first metal layer; patterning and etching the passivation layer to expose a portion of the first metal layer; and depositing bumps on the exposed portion of the first metal layer to support flip-chip mounting.

In some embodiments, the oxide layer has a thickness greater than or equal to <NUM>.

Some embodiments of the method may include backgrinding the heavily doped substrate before depositing the second metal layer.

Some embodiments of the method may include sawing through the substrate, the oxide layer, the first metal layer, and the second metal layer to define a size and shape of the capacitor.

Some embodiments of the method may include: depositing a passivation layer on the first metal layer; patterning and etching the passivation layer to expose a portion of the first metal layer; and backgrinding the heavily doped substrate after patterning and etching the passivation layer and before depositing the second metal layer.

Some embodiments of the method may include: patterning and etching the first metal layer; depositing a passivation layer on the first metal layer; and patterning and etching the passivation layer to expose a portion of the first metal layer.

Some embodiments of the method may include: patterning and etching the first metal layer; depositing a passivation layer on the first metal layer; patterning and etching the passivation layer to expose a portion of the first metal layer; and depositing bumps on the exposed portion of the first metal layer to support flip-chip mounting.

As another example, a method for manufacturing a transmitter/receiver integrated circuit device may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; depositing a second metal layer on a second side of the heavily doped substrate; connecting the first metal layer to a contact point of a first die; and connecting the second metal layer to a contact point of a second die.

In some embodiments, the first die may comprise at least one transceiver, receiver, or transmitter circuit and the second die comprises at least one transceiver, receiver, or transmitter circuit.

In some embodiments, the first metal layer is connected to the contact point of the first die by flip-chip mounting and the second metal layer is connected to the contact point of the second die by wire bonding.

In some embodiments, the first metal layer is connected to the contact point of the first die by conductive epoxy and the second metal layer is connected to the contact point of the second die by wire bonding.

As another example, a method for manufacturing a transmitter/receiver integrated circuit device may include: forming a first capacitor by: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate; forming a second capacitor by repeating the deposition; connecting the first metal layer of the first capacitor to a contact point of a first die; connecting the first metal layer of the second capacitor to a contact point of a second die; and wire bonding the second metal layer of the first capacitor to the second metal layer of the second capacitor.

In some embodiments, the first die comprises at least one transceiver, receiver, or transmitter circuit and the second die comprises at least one transceiver, receiver, or transmitter circuit.

Some embodiments may include connecting the first metal layer of the first capacitor to the contact point of the first die with flip-chip mounting and connecting the first metal layer of the second capacitor to the contact point of the second die with flip-chip mounting.

Some embodiments may include connecting the first metal layer of the first capacitor to the contact point of the first die with conductive epoxy and connecting the first metal layer of the second capacitor to the contact point of the second die with conductive epoxy.

According to the claimed invention, a capacitor comprises: a heavily doped substrate; an oxide layer deposited on the heavily doped substrate; a first metal layer deposited on top of the oxide layer; and a second metal layer deposited on a backside of the substrate.

In some embodiments, the oxide layer is at least <NUM> thick.

According to the claimed invention, a passivation layer is deposited on top of the first metal layer.

According to the claimed invention, a passivation layer is deposited on top of the first metal layer, the passivation layer is patterned and etched to expose a portion of the first metal layer and bumps may be deposited on the exposed portion of the first metal layer for flip-chip mounting.

Some embodiments may include a capacitor as described, bonded to a transmitter or a receiver chip by flip-chip bonding or conductive epoxy.

In some conventional IC devices, a primary die and a secondary die are separated by an oxide layer functioning as a capacitor. An example IC device <NUM> with this construction is depicted in <FIG>, including primary die <NUM> and secondary die <NUM>. IC device <NUM> includes two transceiver pairs 20a, 20b and 22a, 22b connected across an insulation layer <NUM>. In addition, IC device <NUM> includes capacitors <NUM> built on the primary die <NUM> and secondary die <NUM> (on-chip capacitors) along with the associated transmitter/receivers 20a, 20b, 22a, 22b.

The fabrication of IC device <NUM> provides up to <NUM> of oxide for use as the plate of capacitors <NUM>. In testing, capacitors <NUM> broke down to the intermediate node during 6kV testing. According to conventional techniques, this failure might be remedied by increasing the thickness of the oxide layer used to form the capacitors. In practice, however, the required thickness greatly increases the cost of fabrication and the complexity of the processing.

The teachings of the present disclosure, in contrast, provide methods for fabricating capacitors that may be used to simplify the fabrication processes and both reduce the cost of related IC devices and/or increase the reliability.

<FIG> is a drawing showing an example IC device <NUM> including a transmitter/receiver pair with associated capacitors according to the teachings of the present disclosure.

IC device <NUM> includes a transmitter <NUM>, a receiver <NUM>, and two attached capacitors <NUM>. The pair of attached capacitors 100a, 100b may each include a sufficiently thick oxide layer to pass a 6kV test, or the pair may be designed to pass the test when connected together.

As shown, capacitor 100a is flip-chip mounted to transmitter <NUM> and capacitor 100b is flip-chip mounted to receiver <NUM>. Flip-chip mounting may also be known as controlled collapse chip connection. Flip-chip mounting uses solder bumps <NUM> deposited on either a chip pad or an external component. In the example where solder bumps are on the external component, they are deposited on the top of the component. The component is then 'flipped' over onto the pad and a solder reflow process is used to complete the connection between the two, resulting in the configuration shown in <FIG>.

In this example, capacitor 100a and capacitor 100b are connected to one another by a wire bonding process. In contrast to flip-chip bonding, wire bonding includes mounting a chip first and then completing the electrical connections by wiring pads on the chip to the printed circuit board or other circuitry. As shown, the wire bonding essentially connects one plate of capacitor 100a to a corresponding plate of capacitor 100b.

<FIG> is a drawing showing another example IC device <NUM> incorporating the teachings of the present disclosure. IC device <NUM> includes a transceiver <NUM>, a receiver <NUM>, and two attached capacitors 100a, 100b. As shown, capacitor 100a is mounted to transmitter <NUM> and capacitor 100b is mounted to receiver <NUM> using a conductive epoxy <NUM>. In this example, capacitor 100a and capacitor 100b are connected to one another by a wire bonding process. Conductive epoxy <NUM> provides both a mechanical and an electrical connection between the respective IC component <NUM> or <NUM> and the capacitor <NUM>.

<FIG> is a drawing showing another example IC device <NUM> incorporating the teachings of the present disclosure. IC device <NUM> includes a transmitter <NUM>, a receiver <NUM>, and a single capacitor <NUM>. A first plate of capacitor <NUM> is connected to transmitter <NUM> by flip-chip bonding with solder balls <NUM>. A second plate of capacitor <NUM> is connected to receiver <NUM> by wire bonding. In an alternative configuration, capacitor <NUM> may be connected to receiver <NUM> by flip-chip bonding and to transceiver <NUM> by wire bonding.

IC device <NUM> may include only a single capacitor <NUM> in contrast to examples with two capacitors. The teachings of the present disclosure may provide capacitor <NUM> with sufficient durability and reliability to meet specifications previously requiring the use of a pair of capacitors.

<FIG> is a drawing showing another example IC device <NUM> incorporating the teachings of the present disclosure. IC device <NUM> includes a transmitter <NUM>, a receiver <NUM>, and a single capacitor <NUM>. A first plate of capacitor <NUM> is connected to transmitter <NUM> by a conductive epoxy <NUM>. A second plate of capacitor <NUM> is connected to receiver <NUM> by wire bonding. In an alternative configuration, capacitor <NUM> may be connected to receiver <NUM> by conductive epoxy <NUM> and to transceiver <NUM> by wire bonding.

<FIG> are drawings illustrating various steps that may be included in a method for manufacturing capacitor <NUM> according to the teachings of the present disclosure. As shown in <FIG>, the method may begin with depositing an oxide layer <NUM> on a heavily doped or degenerate substrate <NUM>. Degenerate substrate <NUM> may include n-doped silicon with a resistivity in the range of approximately <NUM> mOhm*cm (milliohm centimeters). The oxide layer <NUM> may include at least <NUM> of an oxide (e.g., silicon dioxide) and may be deposited by any appropriate method (e.g., LPCVD, APCVD, other CVD processes, etc.).

<FIG> is a drawing showing another stage for fabricating capacitor <NUM> according to teachings of the present disclosure. A layer of metal <NUM> is deposited on the oxide layer <NUM>. Metal layer <NUM> may be deposited by sputtering, CVD, or any appropriate fabrication process known in the art. Metal layer <NUM> may be patterned and etched as desired for the functions of capacitor <NUM>. In some embodiments of capacitor <NUM>, a layer of passivation material <NUM> may be deposited on top of metal layer <NUM>. As shown in <FIG>, passivation layer <NUM> has been patterned and etched to reveal portions of metal layer <NUM> for later connection steps.

<FIG> is a drawing showing an example capacitor <NUM> prepared for flip-chip mounting to an IC component according to teachings of the present disclosure. Capacitor <NUM> includes a second metal layer <NUM> deposited on the backside of the substrate <NUM>. In some embodiments, fabrication of capacitor <NUM> may include backgrinding the stack (grinding the other side of substrate <NUM>) before depositing the second metal layer <NUM>. In some embodiments, metal layer <NUM> and metal layer <NUM> may comprise the same metallic materials. In other embodiments, metal layer <NUM> and metal layer <NUM> may comprise various materials and/or alloys as appropriate for the desired electrical characteristics of capacitor <NUM>. Capacitor <NUM> now includes two metal plates, layer <NUM> and layer <NUM>, separated by the oxide layer <NUM> and the degenerate substrate <NUM>. Because the substrate is heavily doped, the dielectric characteristics of the oxide will dominate the performance characteristics of capacitor <NUM>.

<FIG> also shows solder balls <NUM> deposited on the exposed portions of metal layer <NUM>. Solder balls <NUM> allow implementation of flip-chip mounting for capacitor <NUM>. For example, capacitor <NUM> may be flip-chip mounted to a transceiver or a receiver as shown in <FIG>.

<FIG> is a drawing showing an example capacitor <NUM> prepared for mounting by conductive epoxy according to teachings of the present disclosure. As discussed above, capacitor <NUM> may include a degenerate substrate <NUM>, an oxide layer <NUM>, a first metal layer <NUM>, a second metal layer <NUM>, and a passivation layer <NUM>. In contrast to the embodiment shown in <FIG>, however, a different pattern has been etched in the passivation layer <NUM>. Rather than the solder balls <NUM> used for flip-chip mounting, a larger portion <NUM> of first metal layer <NUM> is exposed. A conductive epoxy such as that described above may be used to connect the portion <NUM> of first metal layer <NUM> to a pad or other connection point of an associated IC die or component. In some embodiments, a wire bonding process may be used to connect to the exposed portion <NUM> of first metal layer <NUM>.

<FIG> is a drawing showing an example capacitor <NUM> according to teachings of the present disclosure. As discussed above, capacitor <NUM> may include a degenerate substrate <NUM>, an oxide layer <NUM>, a first metal layer <NUM>, and a second metal layer <NUM>. In contrast to the embodiments shown in <FIG>, however, there is no passivation layer <NUM>. The entirety of both first metal layer <NUM> and second metal layer <NUM> is exposed. In embodiments such as that shown in <FIG>, capacitor <NUM> may be called a stand-alone capacitor.

When capacitor <NUM> is a stand-alone capacitor, either a conductive epoxy or a wire bonding process such as that described above may be used to connect the two metal layers <NUM>, <NUM> to a pad or other connection point of an associated IC die or component. In the example capacitor <NUM> shown in <FIG>, a wafer sawing process may be used to define the shape and/or size of the metal layers and, therefore, the electrical properties of capacitor <NUM>. Including such a wafer sawing process may reduce the number of processes requiring semiconductor fabrication techniques, complexity, and/or costs of manufacturing capacitor <NUM>.

<FIG> is a flowchart illustrating an example method <NUM> for manufacturing a capacitor <NUM> incorporating teachings of the present disclosure. Method <NUM> may include various alternative steps allowing for capacitor <NUM> to be mounted by flip-chip mounting, wire bonding, and/or conductive epoxy mounting.

Step <NUM> may include depositing an oxide layer on a heavily doped substrate. As described above, the heavily doped substrate may include a degenerate semiconductor. The oxide layer may include silicon dioxide or another appropriate material for forming the dielectric of a capacitor.

Step <NUM> may include depositing a first metal layer on the oxide layer. As described above, the metal layer may be deposited by sputtering, CVD, or any other appropriate process for the metal chosen. The metal layer may comprise any metal, alloy, or other material selected for the desired electrical properties of the capacitor.

Method <NUM> may include Step <NUM>. Step <NUM> includes patterning and etching the first metal layer. In embodiments comprising a stand-alone capacitor, there may be no need to pattern or etch the first metal layer. In such embodiments, method <NUM> may skip to Step <NUM> or step <NUM>.

Step <NUM> may include depositing a passivation layer on top of the first metal layer. The passivation layer may be used to restrict the connections between the first metal layer and any other component, by limiting leakage and/or the potential for short circuit connections.

Step <NUM> may include patterning and etching the passivation layer to expose a portion of the first metal layer. The exposed portion may be shaped and/or designed to accommodate flip-chip mounting, mounting with conductive epoxy, and/or any other desired connection method.

Step <NUM> may include backgrinding the wafer stack. Grinding the other side of the heavily doped substrate may prepare the substrate for Step <NUM> by improving the flatness, dimensions, and/or other characteristics of the substrate.

Step <NUM> may include depositing a second metal layer on a second side of the heavily doped substrate. The material of the second metal layer may match that chosen for the first metal layer, but may also be varied for the desired electrical performance characteristics of the capacitor.

Some embodiments of Method <NUM> may include Step <NUM>, deposit bumps on the exposed portion of the first metal layer. The bumps may comprise solder for use in flip-chip mounting methods as described above. Example methods to fabricate a stand-alone capacitor will not include Step <NUM>. In addition, example methods to fabricate a capacitor to be mounted by conductive epoxy may not include Step <NUM>.

Claim 1:
A method for manufacturing a capacitor (<NUM>; <NUM>), the method comprising:
depositing an oxide layer (<NUM>) on a first side of a heavily doped substrate (<NUM>);
depositing a first metal layer (<NUM>) on the oxide layer (<NUM>);
depositing a second metal layer (<NUM>) on a second side of the heavily doped substrate (<NUM>); and
depositing a passivation layer (<NUM>) on the first metal layer (<NUM>);
characterized by
patterning and etching the passivation layer (<NUM>) to expose a portion of the first metal layer (<NUM>) to allow flip-chip mounting or conductive epoxy mounting providing a first contact for the capacitor (<NUM>; <NUM>) and wherein a second contact for the capacitor (<NUM>; <NUM>) is provided directly through the second metal layer (<NUM>).