Patent Description:
US patent application <CIT> relates to a device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the second binary value at a second output or vice versa.

US patent application <CIT> relates to a Wave Dynamic Differential Logic (WDDL), wherein a differential logic stage is pre-charged or pre-discharged by a previous logic stage, such as, for example, a previous SDDL stage, a WDDL stage, etc. In one embodiment, a Divided Wave Dynamic Differential Logic (DWDDL) is provided wherein a WDDL circuit is conveniently implemented as dual logic trees.

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various implementations of the disclosure.

Aspects of the present disclosure are directed to functions that are used to perform an evaluation operation with a pre-charge operation. The functions can be logical components that are each used to perform different portions or rounds of a cryptographic or other such operation. The evaluation operation can refer to an operation that uses the function to generate or modify data, and the pre-charge operation can refer to an operation that involves resetting the logical components and any memory element (e.g., flip-flops or registers) of the function to a same single value (e.g., a '<NUM>').

As a cryptographic operation is performed at a device, an attacker (e.g., an unauthorized entity) may seek to compromise the security of the cryptographic operation. For example, the cryptographic operation may utilize a secret value, such as a cryptographic key, and the attacker may attempt to obtain the secret value from the device as the cryptographic operation is performed. To obtain the secret value, the attacker may perform a differential power analysis (DPA) attack (or other such side channel attack) by analyzing the power consumption of the device as the secret value is used by the cryptographic operation.

Countermeasures may be used so that the cryptographic operation is less susceptible to compromise by the attacker. For example, input data to the cryptographic operation may be masked when being utilized by the cryptographic operation. However, such masking techniques may be specific to a particular algorithm of the cryptographic operation and may require additional logical components to mask the input data. Furthermore, the masking techniques may add latency to the cryptographic operation as additional time is used to mask the input data before being used by the cryptographic operation.

Aspects of the present disclosure address the above and other deficiencies by performing an evaluation operation with a pre-charge operation at components used to perform functions of the cryptographic operation. The evaluation operation can be performed concurrently (i.e., at the same time) as the pre-charge operation. For example, the evaluation operation can be performed for a first function component while the pre-charge operation is performed for a second function component. The first function component and the second function component may be used to perform the cryptographic operation. Memory elements (e.g., registers) may be used to separate the two function components. After the evaluation operation has completed at the first function component and the output of the evaluation has been stored at a first memory element of the first function component, the pre-charge operation may then be performed at the first function component and the evaluation operation can be performed at the second function component. For example, the output of the first function component at the first memory element may be utilized by the second function component during the evaluation operation and the first function component (along with the first memory element) can be reset or pre-charged. The output of the evaluation operation at the second function component may be stored at a second memory element that had been previously pre-charged. As a result, the pre-charge operation may reduce the correlation between the power consumption of the device with the input data used by the cryptographic operation as the function component that is to perform the evaluation operation may be reset to a single value before performing the evaluation operation.

In some embodiments, the function components may be implemented based on dual rail logic. For example, a complementary input bit may be generated for each input bit of the input data to the cryptographic operation. The complementary input data and the input data may be processed or operated on by the function components so that the power consumption of the device is independent of the input data.

Advantages of the present disclosure include, but are not limited to, improved security of a device performing a cryptographic operation by reducing susceptibility of the device to a DPA attack. Furthermore, the impact of the latency of the device may be minimal as the pre-charge operation can be concurrently performed with the evaluation operation. Thus, a cycle of the cryptographic operation is not utilized to solely perform the pre-charge operation. As a result, the performance of the device may be improved as the cryptographic operation can be performed without additional latency while also reducing the susceptibility of the device to the DPA attack.

<FIG> illustrates an example architecture <NUM> of function components that are used to perform an evaluation operation with a pre-charge operation. The architecture <NUM> may include multiple function components and memory elements (e.g., registers or flip-flops) where a first function component performs an evaluation operation while a second function component performs a pre-charge operation.

As shown in <FIG>, the architecture <NUM> may include various function components that may be used to perform an operation. For example, the function components may be used together to perform a cryptographic operation or any other type of operation. In some embodiments, the cryptographic operation may be based on a block cipher that specifies a round of sub-operations that are executed or run multiple times. An example of such a cryptographic operation includes, but is not limited to, Advanced Encryption Standard (AES) operations. Further details with respect to AES operations are described in conjunction with <FIG>. The architecture <NUM> may include a first function component <NUM> and a second function component <NUM> that each performs a portion or round of the cryptographic operation. For example, the first function component <NUM> may perform a first round of the cryptographic operation and the second function component <NUM> may perform a second round of the cryptographic operation based on the results of the first round. The first function component <NUM> may then perform a third round of the cryptographic operation based on the results of the second round from the second function component <NUM>. Subsequently, the second function component <NUM> may perform a fourth round of the cryptographic operation based on the results of the third round from the first function component <NUM>. Such rounds may continue to be performed by the first function component <NUM> and the second function component <NUM> until the cryptographic operation has completed with the output <NUM>.

As shown, the first function component <NUM> and the second function component <NUM> may be separated by memory elements such as registers <NUM> and <NUM>. The register <NUM> may be used to store the output from the first function component <NUM> and the register <NUM> may be used to store the output from the second function component <NUM>. The output stored at the second function component <NUM> may subsequently be used by the first function component <NUM> if a further performance of a round to complete the cryptographic operation is necessary.

Furthermore, a masking table generation component <NUM> may be used to provide additional data that is to be used during the cryptographic operation to provide resistance to a DPA attack. The masking table generation component <NUM> may provide, but is not limited to, LMDPL (LUT-Masked Dual-rail with Pre-charge Logic) gate level masking that provides a masked value that is to be used during the performance of the cryptographic operation. Further details with respect to the LMDPL is described in conjunction with <FIG>. The register <NUM> may be used to store a mask value from the masking table generation component <NUM> to be used by the first function component <NUM> when performing an evaluation operation and the register <NUM> may be used to store another mask value from the masking table generation component <NUM> that is to be used by the second function component <NUM> when performing another evaluation operation.

As previously described, the first and second function components <NUM> and <NUM> may perform an evaluation operation and a pre-charge operation. The evaluation operation may correspond to the performance of a portion or a round of the cryptographic operation. The pre-charge operation may correspond to the reset of the respective function component and the respective memory components. For example, a pre-charge operation for the first function component <NUM> may result in the same value (e.g., a <NUM>) to be propagated and stored at each memory element and logic gate of the first function component <NUM> and register <NUM> by using the same pre-charge value (e.g., the '<NUM>') that is stored at register <NUM> and register <NUM>. Similarly, a pre-charge operation for the second function component <NUM> may result in the same value (e.g., a <NUM>) to be propagated and stored at each memory element and logic gate of the second function component <NUM> and register <NUM> by using the pre-charge value at registers <NUM> and <NUM>. In the same cycle, the same value (e.g., a <NUM>) is stored in register <NUM>. Thus, the pre-charge operation may switch any values of '<NUM>' stored at the function components or registers to a <NUM> (or vice versa).

In operation, an input <NUM> may be received. The input <NUM> may be a first input for the cryptographic operation. The first function component <NUM> may perform the evaluation operation by executing a round of the cryptographic operation with the first input. For example, the first function component <NUM> may perform the cipher-block round transformation with the input <NUM> and the mask value from the register <NUM> and store the result of the first round at the register <NUM>. While the first function component <NUM> is performing the evaluation operation corresponding to the first round, the second function component <NUM> may be pre-charged by using pre-charge values stored at the registers <NUM> and <NUM>. For example, an input may be provided to the second function component <NUM> from the registers <NUM> and <NUM> so that the values stored at the second function component <NUM> are uniform (e.g., all bits are at a value of <NUM>). Thus, the second function component <NUM> may receive pre-charge values stored in the registers <NUM> and <NUM> so that each register and logic component in the second function component <NUM> may be pre-charged, and the pre-charge value may be stored at the register <NUM>. When the first function component <NUM> has completed the evaluation operation corresponding to the first round of the cryptographic operation, the output of the first round may be stored at the register <NUM>. Subsequently, when the second function component <NUM> has completed the pre-charge operation, the second function component <NUM> can perform a next evaluation operation corresponding to the next or second round of the cryptographic operation with the output stored at the register <NUM> and the mask value stored at the register <NUM>. In response to the second function component <NUM> performing the evaluation operation with the value stored at the register <NUM>, the pre-charge operation may then be performed with the first function component <NUM> and registers <NUM> and <NUM>.

As such, the function components may perform different successive portions or rounds of a cryptographic or other such operation. The first function component may perform an evaluation operation with data while the second function component may perform a pre-charge operation. The second function component may then perform a subsequent evaluation operation with the output of the first function component in response to the first function component completing the evaluation operation. Subsequently, the first function component may perform the pre-charge operation.

<FIG> is a flow diagram of an example method <NUM> to perform evaluation operations with pre-charge operations. The method <NUM> may be performed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof In some embodiments, the method <NUM> may be performed by the architecture <NUM> of <FIG>.

As shown in <FIG>, the processing logic may receive data (block <NUM>). The data may be an input to a cryptographic operation. For example, the data may be data that is to be encrypted by an AES cryptographic operation. The processing logic may further perform an evaluation operation with the received data at a first function component (block <NUM>). For example, a first round of the cryptographic operation may be performed. In some embodiments, the first round of the cryptographic operation may be performed with the received data and a mask value that is to be used to mask the received data when being used in the first round of the cryptographic operation. The processing logic may further store the results of the evaluation operation from the first function component at a first memory element (block <NUM>). For example, an intermediate output value of the cryptographic operation that corresponds to an output of the evaluation operation may be stored at a first register or other such memory element. Furthermore, the processing logic may perform a pre-charge operation at a second function component and store the pre-charge value into a second memory element during the performance of the evaluation operation at the first function component (block <NUM>). In some embodiments, the pre-charge operation may further be performed at another memory element that is to store another mask value for an evaluation operation to be performed by the second function component. In some embodiments, the logic of the respective function components may be pre-charged by using the pre-charge values at input registers to the respective function components. The logic of the respective function component may then be reset by propagating the pre-charge values through the logic of the function component.

The processing logic may perform another evaluation operation at the second function component with results of the prior evaluation operation received from the first memory element (block <NUM>). For example, a second round of the cryptographic operation may be performed by the second function component. In some embodiments, the second round of the cryptographic operation may be performed with the results of the prior evaluation operation and another mask value that is to be used to protect the results of the prior evaluation operation when being used in the second round of the cryptographic operation. Furthermore, the processing logic may perform a pre-charge operation at the first function component and store the pre-charge value into the first memory element during the evaluation operation at the second function component (block <NUM>). For example, the pre-charge operation may be performed for the first function component after the first function component has performed the prior evaluation operation and has stored the output of the evaluation operation at the first memory element. Subsequently, the operations of the processing logic may be repeated for each additional data that is received.

<FIG> illustrates an example architecture <NUM> of cryptographic round function components that are used to perform an evaluation operation with a pre-charge operation. The architecture <NUM> may correspond to the architecture <NUM> of <FIG>. In some embodiments, the architecture <NUM> may correspond to an architecture to perform the evaluation operation and the pre-charge operation with respect to a data path.

The architecture <NUM> may correspond to AES cryptographic round functions that utilize LMDPL to provide a DPA countermeasure for the AES cryptographic round functions. In some embodiments, the AES cryptographic round functions may be used to encrypt input data. The architecture <NUM> may be implemented based on dual-rail logic. For example, the function components of the architecture <NUM> may be implemented by operating on bit values at a value of <NUM> and a <NUM> so that a true network and a complementary false network may be included in each of the function components. As shown, the function components of the AES cryptographic operation may be the AddRoundKey, ShiftRows, SubBytes, and MixColumns sub-operations. In some embodiments, the AES cryptographic operation may operate on a two-dimensional array of bytes where the ShiftRows, SubBytes, and MixColumns sub-operations may each perform a transformation of the bytes in the two-dimensional array to modify one or more of the bytes. Each round may further include an exclusive-or (XOR) operation that is performed on data to be used in the round and a round key. For example, the XOR operation <NUM> of the first round may utilize a round key <NUM> and the XOR operation <NUM> of the second round may utilize a second round key <NUM>.

The mask value generator <NUM> may be based on an LMDPL DPA countermeasure as previously described. The LMDPL countermeasure may be used to provide a mask value (e.g., a round mask value) that is based on an input mask <NUM> that is combined with a round key mask value <NUM> by an XOR operation. The mask value may be based on transformations of the bytes of the output of the XOR operation and may be repeated for each round of the AES cryptographic operation to generate a different mask value (e.g., a different mask value) to be used in each evaluation operation of the AES cryptographic operation.

In operation, the input data <NUM> may be received by a dual-rail logic converter <NUM>. The dual-rail logic converter <NUM> may convert the input data <NUM> by generating a complementary input data. The input data <NUM> and the complementary input data may then be provided to a selection unit such as the multiplexer <NUM>. A selection signal of the multiplexer <NUM> may be used to transmit the output of the dual-rail logic converter <NUM> to an XOR component <NUM> so that the output may be combined with a round key <NUM>. The first evaluation operation may then be performed by the first function component. For example, the ShiftRows sub-operation <NUM> may be performed with the output of the XOR operation <NUM> and the result may be stored at the register <NUM>. The SubBytes sub-operation <NUM> may then be performed with the output stored at the register <NUM> and a countermeasure value stored at the register <NUM> that has been generated by the mask value generator <NUM>. The MixColumns sub-operation <NUM> may then transform the output of the SubBytes sub-operation <NUM> and the result is combined with another round key <NUM> by the XOR operation <NUM>. The output of the XOR operation <NUM> may then be subjected to the ShiftRows sub-operation <NUM> and the result may be stored at the register <NUM>. During the first evaluation operation, the second function component may be pre-charged by resetting the values at the SubBytes sub-operation <NUM> and registers <NUM> and <NUM>. Subsequently, when the first evaluation operation has completed and the output of the ShiftRows sub-operation <NUM> has been stored at the register <NUM>, a subsequent evaluation operation may be performed by the second function component. For example, the SubBytes sub-operation <NUM> may be performed with the results of the first evaluation operation and a new mask value generated by the mask value generator <NUM> that is stored at the register <NUM>. The MixColumns sub-operation <NUM> may then be performed with the output of the SubBytes sub-operation <NUM> and the result may be received by the multiplexer <NUM>. Further evaluation operations may be performed for each round as necessary to complete the AES operation. As the subsequent evaluation operation is being performed, the components of the SubBytes sub-operation <NUM> and registers <NUM> and <NUM> may be pre-charged.

Thus, in a single cycle (i.e., clock cycle), the evaluation operation may be performed with the first function component while the pre-charge operation may be performed with the second function component. Subsequently, the pre-charge operation may be performed with the first function component while the evaluation operation may be performed with the second function component that had completed the pre-charge operation.

<FIG> is a flow diagram of an example method <NUM> to perform an evaluation operation and a pre-charge operation at a function component. The method <NUM> may be performed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof In some embodiments, the method <NUM> may be performed by the architecture <NUM> of <FIG> or architecture <NUM> of <FIG>.

As shown in <FIG>, the processing logic may perform an evaluation operation (block <NUM>). For example, a first function component may perform a round of a cryptographic operation. The results of the evaluation operation may be stored at a register or other such memory element of the first function component. The processing logic may further receive an indication that a subsequent evaluation operation has initiated (block <NUM>). For example, a second function component may have started the performance of a subsequent round of the cryptographic operation with the results of the prior evaluation operation generated by the first function component and that have been stored at the register. In response to receiving the indication that the subsequent evaluation operation has initiated, the processing logic may perform a pre-charge operation at the function component that performed the prior evaluation operation (block <NUM>). For example, components and registers of the first function component may be pre-charged. The processing logic may further receive an indication that the subsequent evaluation operation has completed and another evaluation operation is to be performed (block <NUM>). For example, the cryptographic operation may be implemented by the performance of additional rounds or evaluation operations and another evaluation operation may be performed when the additional rounds or evaluation operations needed to complete the cryptographic operation have not been performed by the function components. In response to receiving the indication that the subsequent evaluation operation has completed and another evaluation operation is to be performed, the processing logic may perform another evaluation operation based on the results of the subsequent evaluation operation that had completed (block <NUM>). For example, the first function component that had been pre-charged may perform another evaluation operation that corresponds to another round of the cryptographic operation.

illustrates an example architecture <NUM> of a pipeline architecture to perform an evaluation operation with a pre-charge operation. The architecture <NUM> may include multiple pipelines that each correspond to the performance of an operation such as a cryptographic operation.

As shown in <FIG>, the architecture <NUM> may include a first pipeline (e.g., components in the left portion of the architecture <NUM>) and a second pipeline (e.g., components in the right portion of the architecture <NUM>). The first pipeline may include function components and memory elements. For example, the first pipeline may include function components that perform an evaluation operation for a round of the cryptographic operation and registers that separate the function components. As shown, the first pipeline may include memory elements or registers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and may include function components to perform evaluation operations corresponding to a first round through n-number of rounds. The second pipeline may include other function components and memory elements. For example, the second pipeline may include function components that perform an evaluation operation for a round of another cryptographic operation and registers that separate the other function components. As shown, the second pipeline may include memory elements or registers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and may include function components to perform evaluation operations corresponding to a first round through N-number of rounds of another cryptographic operation. The architecture <NUM> may further include a selection unit <NUM> (e.g., a multiplexer) that provides an output <NUM> from one of the first pipeline or second pipeline based on a selection signal.

In operation, a first data may be received from the input signal <NUM>. The first data may be received by the first pipeline and may not be received by the second pipeline. Furthermore, a subsequent data from the input signal <NUM> may be received by the second pipeline and may not be received by the first pipeline. For example, the registers <NUM> and <NUM> may alternate between storing data received from the input signal <NUM> so that at a first time the register <NUM> may store data from the input signal <NUM> while the register <NUM> does not store data from the input signal <NUM>. Additionally, at a second time, the register <NUM> may store data from the input signal <NUM> while the register <NUM> does not store data from the input signal <NUM>. The evaluation operations for each of the rounds of each of the first and second pipelines may be performed based on the data received by the respective pipeline. Furthermore, the function components and registers of the first pipeline and the second pipeline may alternate between pre-charge operations and evaluation operations. For example, at a first time, the first pipeline may perform evaluation operations at its respective function components. For example, the first pipeline may receive data at registers <NUM>, <NUM>, and <NUM> and perform evaluation operations at the function components corresponding to the different rounds of the cryptographic operation. At the same time, the second pipeline may perform pre-charge operations at its respective function components. For example, the second pipeline may perform pre-charge operations at the function components corresponding to the different rounds and may also pre-charge a subset of the registers. For example, the registers <NUM>, <NUM>, and <NUM> may be pre-charged with the function components of the second pipeline. At a second time that is subsequent to the first time (e.g., a next clock cycle), the first pipeline may perform the pre-charge operations while the second pipeline may perform evaluation operations. For example, the pre-charge operations may be performed with the first pipeline at registers <NUM>, <NUM>, and <NUM> as well as at the function components corresponding to the different rounds of the cryptographic operation. While the pre-charge operations are performed with the first pipeline at registers <NUM>, <NUM>, and <NUM>, the registers <NUM> and <NUM> may receive data from the output of the evaluation operation. At the same time, the second pipeline may perform evaluation operations at its respective function components. For example, the second pipeline may perform evaluation operations at the function components corresponding to the different rounds of the function components and may also store data at registers <NUM>, <NUM>, and <NUM>. Furthermore, while the pre-charge operations are performed with the second pipeline at registers <NUM>, <NUM>, and <NUM>, the registers <NUM> and <NUM> may receive data from the output of the evaluation operation at the second pipeline.

As such, the architecture <NUM> may include two pipelines each may perform a separate cryptographic operation. The two pipelines may accept or receive input data in alternate cycles and the resulting data of the rounds of the cryptographic operation may progress through each respective pipeline based on alternating evaluation operations and pre-charge operations.

<FIG> is a flow diagram of an example method <NUM> to alternate between a pre-charge operation and an evaluation operation of a pipeline architecture. The method <NUM> may be performed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method <NUM> may be performed by the architecture <NUM> of <FIG>.

As shown in <FIG>, the processing logic may receive data at a first pipeline of a cryptographic component. The data may be data that is to be performed with a cryptographic operation. For example, the data may be encrypted by the cryptographic operation. The processing logic may further alternate between an evaluation operation and a pre-charge operation for components of the first pipeline (block <NUM>). For example, the performance of the evaluation operation at function components and the storing of data at registers and the performance of the pre-charge operation at the function components and a subset of the registers may be alternated through each cycle of the first pipeline. For example, the first pipeline may perform the evaluation operation at a first clock cycle of the cryptographic component and may perform the pre-charge operation at a second clock cycle of the cryptographic component. The processing logic may further receive additional data at a second pipeline of the cryptographic component (block <NUM>). For example, the additional data may be received after the prior data has been received by the first pipeline of the cryptographic component. In some embodiments, the additional data may be received at a next clock cycle of the cryptographic operation with respect to the first pipeline receiving the prior data. Furthermore, the processing logic may alternate between a pre-charge operation and an evaluation operation for components of the second pipeline (block <NUM>). For example, the second pipeline may perform the pre-charge operation at a first clock cycle of the cryptographic component and may perform the evaluation operation at a next second clock cycle of the cryptographic component. Furthermore, the second pipeline may perform the pre-charge operation when the evaluation operation is being performed at the first pipeline and the second pipeline may perform the evaluation operation when the pre-charge operation is being performed at the first pipeline. The processing logic may further provide an output of the cryptographic component based on the first pipeline and the second pipeline (block <NUM>). For example, after data has progressed through the different rounds of each of the first pipeline and the second pipeline (e.g., the pipelines are full), a selection unit (e.g., the multiplexer) may alternate between outputting the result of the final round of the first pipeline and the result of the final round of the second pipeline. In some embodiments, the first and second pipelines may operate in synchronization where a number of bits (e.g., <NUM> bits) may be received every two clock cycles as opposed to data being received each clock cycle by the alternating first and second pipelines. Furthermore, although two pipelines are described, any number of pipelines may be used.

<FIG> illustrates an example of a computer system <NUM> within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine may operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system <NUM> includes a processing device <NUM>, a main memory <NUM> (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory <NUM> (e.g., flash memory, static random access memory (SRAM), etc.), graphics processing unit <NUM>, video processing unit <NUM>, audio processing unit <NUM>, video display unit <NUM>, alpha-numeric input device <NUM>, cursor control device <NUM>, a signal generation device <NUM>, and a data storage device <NUM>, which communicate with each other via a bus <NUM>.

Processing device <NUM> represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device <NUM> may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device <NUM> is configured to execute instructions <NUM> for performing the operations and steps discussed herein.

The computer system <NUM> may further include a network interface device <NUM> to communicate over the network <NUM>. The computer system <NUM> also may include a video display unit <NUM> (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device <NUM> (e.g., a keyboard), a cursor control device <NUM> (e.g., a mouse), a graphics processing unit <NUM>, a signal generation device <NUM> (e.g., a speaker), video processing unit <NUM>, and audio processing unit <NUM>.

The data storage device <NUM> may include a machine-readable storage medium <NUM> (also known as a computer-readable medium) on which is stored one or more sets of instructions or software <NUM> embodying any one or more of the methodologies or functions described herein. The instructions <NUM> may also reside, completely or at least partially, within the main memory <NUM> and/or within the processing device <NUM> during execution thereof by the computer system <NUM>, the main memory <NUM> and the processing device <NUM> also constituting machine-readable storage media.

In one implementation, the instructions <NUM> include instructions to implement functionality as described herein. While the machine-readable storage medium <NUM> is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media and magnetic media.

Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as "identifying" or "determining" or "executing" or "performing" or "collecting" or "creating" or "sending" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

Claim 1:
A method comprising:
receiving an input data (<NUM>);
performing, by a processing device, a portion of a cryptographic operation with the received input data (<NUM>) at a first function component (<NUM>); and
during the performance of the cryptographic operation at the first function component (<NUM>), performing a pre-charge operation at a second function component (<NUM>) that is to perform another portion of the cryptographic operation with a result of the portion of the cryptographic operation performed at the first function component (<NUM>).