Patent Description:
<CIT> relates to processors to scale floating point numbers responsive to floating point scaling instructions. For example, a method includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or more floating point data elements, a second source including one or more corresponding floating point data elements, and a destination. A result is stored in the destination in response to the floating point scaling instruction. The result includes one or more corresponding result floating point data elements each including a corresponding floating point data element of the second source multiplied by a base of the one or more floating point data elements of the first source raised to a power of an integer representative of the corresponding floating point data element of the first source.

The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for instructions for calculating a scale of FP8 data elements, a reduced argument of FP8 data elements, or rounding of FP8 data elements.

BF16 is gaining traction due to its ability to work well in machine learning algorithms, in particular deep learning training. <FIG> illustrates different floating point representation formats. In this illustration, the formats are in little endian format, however, in some embodiments, a big endian format is used. The FP32 format <NUM> has a sign bit (S), an <NUM>-bit exponent, and a <NUM>-bit fraction (a <NUM>-bit mantissa that uses an implicit bit). The FP16 format <NUM> has a sign bit (S), a <NUM>-bit exponent, and a <NUM>-bit fraction. The BF16 format <NUM> has a sign bit (S), an <NUM>-bit exponent, and a <NUM>-bit fraction.

In contrast to the IEEE <NUM>-standardized <NUM>-bit (FP16) variant, BF16 does not compromise on range when being compared to FP32. FP32 numbers have <NUM> bits of exponent and <NUM> bits of mantissa (including the one implicit). BF16 cuts <NUM> bits from the <NUM>-bit FP32 mantissa to create a <NUM>-bit floating point datatype. In contrast FP16, roughly halves the FP32 mantissa to <NUM> explicit bits and reduces the exponent to <NUM> bits to fit the <NUM>-bit datatype envelope.

Although BF16 offers less precision than FP16, it is typically better suited to support deep learning tasks. FP16's range is not enough to accomplish deep learning training out-of-the-box due to its limited range. BF16 does not suffer from this issue and the limited precision may actually help to generalize the learned weights in the neural net training task. In other words, lower precision can be seen as offering a built-in regularization property.

In some examples, an <NUM>-bit floating point format (FP8) provides some advantages over a larger floating point format. For example, an <NUM>-bit floating point format may reduce pressure on memory and bandwidth used for machine learning (such as weights, activations, and gradient values used for training and/or inference of neural networks). As shown, the IEEE and BF16 formats have a fixed number of bits allocated to the fraction (or mantissa which is the fraction bits + <NUM> bit) and exponent fields. Additionally, in some examples, a fixed exponent bias may be provided for a FP16 or BF16 number. As eight bits allows for a small number of mantissa and exponent bits than FP16 or BF16 it may be advantageous to have some variance in FP8 formats (e.g., ensure high accuracy and convergence when training machine learning models).

In machine learning, different parameters, namely weights, gradients and activations, have different precision and range requirements to achieve high training accuracy and/or convergence. This allows for different allocations of the number of exponent and fraction (mantissa bits) depending on the parameter being represented.

An example FP8 format is shown in <NUM>. In some examples, this is called a bfloat8-bit floating point (HF8) format. As shown, this format uses <NUM> bit for a sign, <NUM> bits for the exponent, and <NUM> bits for the fraction (or <NUM> + <NUM> bits for the mantissa). An example FP8 format is shown in <NUM>. In some examples, this is called a hybrid8-bit floating point (HF8) format. As shown, this format uses <NUM> bit for a sign, <NUM> bits for the exponent, and <NUM> bits for the fraction (or <NUM> + <NUM> bits for the mantissa).

Normalized numbers, subnormal (denormal) numbers, and zeroes are supported in both FP8 formats. In some examples, infinity and not-a-number (NaN) encodings are not supported, however, in some examples one or more are. In examples where infinities are not supported, a maximum exponent value is not reserved for encoding NaN and +/infinity and just used to represent normalized floating-point numbers.

In examples where infinities and NaN are supported, the are mapped to 0x80. In some examples, for a NaN on an overflow, the value may be upconverted to IEEE754 NaN. In some examples, infinities and NaN raise exceptions for a hardware status register to delineate NaN from overflow.

In some examples, a zero is represented by an encoding with all zeroes the exponent and the fraction. Encodings with an all zero exponent and non-zero fraction represent denormal numbers. In the BF8 format, an exponent = <NUM><NUM> and mantissa = <NUM><NUM> represents numerical value of zero, while exponent = <NUM><NUM> and mantissa = <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, <NUM><NUM>, and <NUM><NUM> represent the denormal numbers. Similarly, in the HF8 format an exponent = <NUM><NUM> and mantissa = <NUM><NUM> represents numerical value of zero, while exponent = <NUM><NUM> and mantissa =<NUM><NUM>, <NUM><NUM>, and <NUM><NUM> represent the denormal numbers.

In some examples, the FP8 formats utilize a variable exponential bias (e.g., a <NUM>-bit unsigned integer value used as a bias). A bias skews the range of representable values more on the smaller numeric values at the expense of larger numerical values. In these examples, a numerical value of a normalized floating point number is (<NUM>)sign x <NUM>exponent-bias x <NUM>. mantissa and the numerical value of a denormal floating point number is (<NUM>)sign x <NUM>exponent-bias x <NUM>. In some examples, the bias is provided by one or more packed data registers (e.g., SIMD or vector) where each data element position of the one or more packed data registers is to provides a bias value for a corresponding data element position of a source and/or destination. In some examples, the bias is provided by one or more general purpose registers where each general purpose register provides a bias to be used for each data element of a particular source and/or destination. Note that in some examples, a single general purpose register is used for a plurality of sources and/or destination. In some examples, the maximum bias is <NUM> for BF8 and <NUM> for HF8.

In some examples, not-a-number (NANs) and infinities are defined similarly to other IEEE floating points format, using an all-ones exponents. However, it is also acceptable in some examples to define versions of instructions that support other formats where "negative zero" is used to denote NANs and infinities, and the all-ones exponent is used to encode normal floating point numbers.

In some examples, hardware support for FP8 supports one or more status (condition code) flags: invalid, denormal, overflow, and underflow. An arithmetic operation with a denormal operand will set the denormal exception flag, while an arithmetic operation with any NaN operand or no useful definable result will set the invalid exception flag. An arithmetic operation with a result that that overflows or underflows a destination will set the overflow and underflow exception flags respectively in some examples.

Recent work has also shown that <NUM>-bit float point formats, such as BF8 (using a <NUM>-<NUM>-<NUM> format (<NUM>-bit sign, <NUM>-bit exponent, and <NUM>-bit fraction or a <NUM>-<NUM>-<NUM> format), are a viable option for input data for mixed precision computation such as fused multiply-add (FMA) with BF8 inputs and a FP32 accumulator. To prepare higher-precision outputs to be used as the next operation's inputs, in some embodiments, those outputs need to be converted/rounded to FP8 numbers. Using <NUM>-bit floating-point format instead of single- precision in at least some matrix operations is expected to alleviate memory utilization and bandwidth issues while providing a non-trivial performance upside (e.g., on the order of 2X) even during the compute operation. Additionally, numerical accuracy studies have shown that the precision of the Deep Learning application is not compromised. However, extensive workload studies have shown, that from time to time its required to avoid classic round-to-nearest behavior during these down converts. Instead, a stochastic rounding operation is needed. Examples herein relate to conversion using a provided bias term, including variable in-place, <NUM>nd source merging and/or saturating.

Current experiments show bandwidth issues on the various cache levels and DRAM. So, as matrix compute capabilities speed up significantly (2X), the memory sub-systems capabilities only increase modestly due to reduce memory footprint. However, it has been found important to achieve convergence that FMAs accumulate into single-precision, IEEE float32. That means it may be important down-convert a result to FP8 after the operation completes.

In some examples, BF8-based operations support round to nearest even (RNE) and stochastic rounding. In some examples, HF8-based operations support round to nearest even (RNE) and stochastic rounding. In some examples, hybrid operations using both HF8 and BF8 are supported.

Detailed herein are embodiments of instructions, and their support, that operate on FP8 source data elements. In some embodiments, an execution of a single instruction causes a floating-point scale of the packed FP8 floating-point values in a first source operand by multiplying it by power of <NUM> of the FP8 values in a second source operand and storing of the floating-point scales in a destination operand. In some embodiments, an execution of a single instruction causes an extraction of a reduced argument of FP8 values in a first source operand by a number of bits specified in an operand or immediate and places the reduced arguments in a destination operand. In some embodiments, an execution of a single instruction causes a rounding of FP8 values in a source operand by a rounding mode specified in an operand or immediate and places the values in the destination operand.

In some embodiments, the single instruction is translated from a first instruction set architecture (ISA) to one or more instructions of a second ISA and the execution of the one or more instructions of the second ISA perform those calculations.

In some embodiments, one or more of the instructions are defined such as their execution is to treat denormal inputs or outputs as zeros, support any rounding mode, and/or report or suppress floating point numerical flags.

<FIG> illustrates an exemplary execution of an instruction to calculate a scale of FP8 data elements. While this illustration is in little endian format, the principles discussed herein work in big endian format. In particular, the execution of this instruction causes a calculation of floating-point scale of the packed FP8 floating-point values in the first source operand by multiplying it by power of <NUM> of the FP8 values in second source operand and storing the destination operand.

The calculate a scale of FP8 data elements instruction (shown here with an exemplary opcode mnemonic of VSCALEFNEPFP8) includes one or more fields to define the opcode for the instruction, one or more fields to reference or indicate a first and a second packed data source (e.g., a register or memory location), and/or one or more fields to reference or indicate a packed data source (e.g., a register or memory location). In some embodiments, the instruction also includes one or more fields to reference or indicate a writemask or predication register that is to store writemask or predicate values as described later.

An embodiment of a format for a calculate a scale of FP8 data elements instruction is VSCALEFNEPBF DST{k}, SRC1, SRC2. In some embodiments, VSCALEFNEPBF is the opcode mnemonic of the instruction. DST is a field for the destination operand identifier, such as packed data register or memory. SRC1 is one or more fields for the source operands identifier, such as a packed data register and/or memory. In some examples, the opcode is provided by at least field <NUM>, DST field is provided by field at least <NUM>, the first source is provided by bits VVVV of one of <NUM>, BPJ17, or <NUM>, and the second source is provided by at least <NUM>. In some examples, the opcode is provided by at least field <NUM>, DST field is provided by at least field <NUM>, the first source is provided by bits VVVV of one of <NUM>, BPJ17, or <NUM>, and the second source is a memory location provided by at least <NUM> and/or the SIB byte <NUM>. The source operands and destination operand may come in one or more sizes such as <NUM>-bit, <NUM>-bit, <NUM>-bit, etc. The {k} is used when writemasking or predication is used.

In this example, the first packed data source <NUM> includes <NUM> packed data elements each of which is in FP8 format. The first packed data source <NUM> may be a register or a memory location. The second packed data source <NUM> includes <NUM> packed data elements each of which is in FP8 format. The second packed data source <NUM> may be a register or a memory location.

The packed data sources <NUM> and <NUM> are fed into execution circuitry <NUM> to be operated on to calculate the floating-point scale. In some embodiments, the execution circuitry <NUM> the scale is calculated according to the following destination = source <NUM> * <NUM>(floor(source <NUM>) using scale/reduction circuitry <NUM>. In some embodiments, this execution of the instruction uses a round to nearest (even) rounding mode. In some embodiments, output denormals are always flushed to zero and input denormals are always treated as zero.

In some examples, FP8 values are upconverted using upconvert circuitry <NUM>. In some examples, a (variable or static) bias <NUM> is applied during the upconversion. In some examples, the upconversion is to FP16. In some examples, the upconversion is to BF16. In some examples, the upconversion is to FP32.

In some examples, the bias <NUM> is provided by one or more packed data registers (e.g., SIMD or vector) where each data element position of the one or more packed data registers is to provides a bias value for a corresponding data element position of a source and/or destination. In some examples, the bias <NUM> is provided by one or more general purpose registers where each general purpose register provides a bias to be used for each data element of a particular source and/or destination. Note that in some examples, a single general purpose register is used for a plurality of sources and/or destination.

In some examples, the execution circuitry <NUM> is configured according to control information to use one or more of the described components instead of other execution circuits <NUM>. The control information may be provided by a decoder, scheduler, etc..

The packed data destination <NUM> is written to store the resultant scale values in corresponding packed data elements as the packed data source <NUM>. In some embodiments, when the instruction calls for the use of predication or writemasking, a writemask (or predicate) register <NUM> dictates how the resultant scale values are stored and/or zeroed using the writemask circuitry <NUM>.

<FIG> illustrates an embodiment of method to process a calculate a scale of FP8 data elements instruction. For example, a processor core as shown herein), a pipeline as detailed below, etc. performs this method.

At <NUM> an instruction is fetched having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a FP8 data element of the first packed data source by multiplying the data element by a power of <NUM> value wherein a value of the exponent of the power of <NUM> value is a floor value of a data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand.

In some embodiments, the fetched instruction, of a first ISA, is translated into one or more instructions of a second, different ISA at <NUM>. The one or more instructions of the second, different ISA, when executed, provided the same result as if the fetched instruction had been executed. Note the translation may be performed by hardware, software, or a combination thereof.

The instruction (or the translated one or more instructions) is/are decoded <NUM>. This decoding may cause the generation of one or more micro-operations to be performed. Note that as this instruction.

Data values associated with the source operands of the decoded instruction are retrieved at <NUM>. For example, when a source operand is stored in memory, the data from the indicated memory location is retrieved.

At <NUM>, the decoded instruction(s) is/are executed by execution circuitry (hardware) such as that detailed herein. The execution circuitry is to perform for each data element position of the packed data source operands, a floating point scale operation of a FP8 data element of the first packed data source by multiplying the data element by a power of <NUM> value wherein a value of the exponent of the power of <NUM> value is a floor value of a data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand. In some examples, the data elements are upscaled (e.g., to BF16, FP16, FP32, etc.) prior to the operation. Note upscaling, etc. may use a variable bias.

In some embodiments, the instruction is committed or retired at <NUM>.

<FIG> illustrate exemplary embodiments of pseudocode representing the execution and format of a calculate a scale of FP8 data elements instruction. Note that EVEX. b maps to the b of prefix <NUM>(C). The comment of DAZ, FTZ, RNE, and SAE refer to the use of support for flush-to-zero (FTZ), denormals-are-zero (DAZ), suppress all exceptions (SAE), and round-to-even (RNE) rounding.

<FIG> illustrates embodiments of execution of an extract a reduced argument of FP8 data elements instruction. While this illustration is in little endian format, the principles discussed herein work in big endian format. The extract a reduced argument of FP8 data elements instruction (shown here with an exemplary opcode mnemonic of VREDUCENEPFP8) includes one or more fields to define the opcode for the instruction, one or more fields to reference or indicate a FP8 packed data source (e.g., a register or memory location), one more fields to indicate a scaling value (e.g., portions of an immediate or a scaling value stored in a register or memory location), and/or one or more fields to reference or indicate a packed data destination (e.g., a register or memory location). In some embodiments, the instruction also includes one or more fields to reference or indicate a writemask or predication register that is to store writemask or predicate values as described later.

An embodiment of a format for an extract a reduced argument of FP8 data elements instruction is VREDUCENEPFP8 DST{k}, SRC1 IMM8. In some embodiments, VREDUCENEPFP8 is the opcode mnemonic of the instruction. DST is a field for the destination operand identifier, such as packed data register or memory. SRC is one or more fields for the source operands identifier, such as a packed data register and/or memory. In some examples, the opcode is provided by at least field <NUM>, DST field is provided by field <NUM>, the source is provided by bits VVVV of one of <NUM>, BPJ17, or <NUM>, or the source is provided by at least <NUM>. In some examples, the opcode is provided by at least field <NUM>, DST field is provided by at least field <NUM>, the source is provided by bits VVVV of one of <NUM>, BPJ17, or <NUM>, or the source is a memory location provided by at least <NUM> and/or the SIB byte <NUM>. IMM8 is an immediate provided by <NUM>. The source operand and destination operand may come in one or more sizes such as <NUM>-bit, <NUM>-bit, <NUM>-bit, etc. The {k} is used when writemasking or predication is used.

In this example, the packed data source <NUM> includes <NUM> packed data elements each of which is in FP8 format. The packed data source <NUM> may be a register or a memory location.

The packed data source <NUM> and immediate ISAR05 are fed into execution circuitry <NUM> to be operated on. In particular, execution circuitry <NUM> (such as scale/reduce circuitry <NUM>) performs an extraction of a reduced argument of FP8 data elements of the packed data source ISAR01 according to a scale provided by the immediate <NUM>. In some embodiments, the execution circuitry <NUM> the scale is calculated according to the following destination = source <NUM>*.

(ROUND(<NUM>M * source <NUM>)) * <NUM>-M using scale/reduction circuitry <NUM>. The scaling value M comes from the immediate <NUM>.

In some embodiments, this execution of the instruction uses a round to nearest (even) rounding mode. In some embodiments, output denormals are always flushed to zero and input denormals are always treated as zero.

In some examples,FP8 values are upconverted using upconvert circuitry <NUM>. In some examples, a (variable or static) bias <NUM> is applied during the upconversion. In some examples, the upconversion is to FP16. In some examples, the upconversion is to BF16. In some examples, the upconversion is to FP32.

The packed data destination <NUM> is written to store the resultant reduced values in corresponding packed data elements as the packed data source <NUM>. In some embodiments, when the instruction calls for the use of predication or writemasking, a writemask (or predicate) register <NUM> dictates how the resultant FP8-formated reduced values are stored and/or zeroed using the writemask circuitry <NUM>.

<FIG> illustrates embodiments of an exemplary method performed by a processor to process an instruction to extract a reduced argument of FP8 data elements. For example, a processor core as shown herein, a pipeline as detailed below, etc. performs this method.

At <NUM> an instruction is fetched having fields for an opcode, an identification of a location of a packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operand, an extraction of a reduced argument of a FP8 data element of the packed data source <NUM> by a number of bits specified in the immediate <NUM>, and store the extracted reduced argument into a corresponding data element position of the packed data destination operand <NUM> using the scale/reduce circuitry <NUM>.

Data values associated with the source operand of the decoded instruction are retrieved at <NUM>. For example, when a source operand is stored in memory, the data from the indicated memory location is retrieved.

At <NUM>, the decoded instruction(s) is/are executed by execution circuitry (hardware) such as that detailed herein. The execution circuitry is to perform, for each data element position of the packed data source operand, an extraction of a reduced argument of a FP8 data element of the packed data source by a number of bits specified in the immediate, and store the extracted reduced argument into a corresponding data element position of the packed data destination operand. In some examples, the data elements are upscaled (e.g., to BF16, FP16, FP32, etc.) prior to the operation. Note upscaling, etc. may use a variable bias.

<FIG> illustrate exemplary embodiments of pseudocode representing the execution and format of an extract a reduced argument of FP8 data elements instruction. Note that EVEX. b maps to the b of prefix <NUM>(C). The comment of DAZ, FTZ, RNE, and SAE refer to the use of support for flush-to-zero (FTZ), denormals-are-zero (DAZ), suppress all exceptions (SAE), and round-to-even (RNE) rounding.

<FIG> illustrates embodiments of execution of a round FP8 data elements instruction according to some embodiments. While this illustration is in little endian format, the principles discussed herein work in big endian format. The round FP8 data elements instruction (shown here with an exemplary opcode mnemonic of VRNDSCALENEPFP8) includes one or more fields to define the opcode for the instruction, one or more fields to reference or indicate a FP8 packed data source (e.g., a register or memory location), one more fields to indicate a rounding mode (e.g., portions of an immediate or a scaling value stored in a register or memory location), and/or one or more fields to reference or indicate a packed data destination (e.g., a register or memory location). In some embodiments, the instruction also includes one or more fields to reference or indicate a writemask or predication register that is to store writemask or predicate values as described later.

An embodiment of a format for a round FP8 data elements instruction is VRNDSCALENEPFP8 DST{k}, SRC1 IMM. In some embodiments, VRNDSCALENEPFP8 is the opcode mnemonic of the instruction. DST is a field for the destination operand identifier, such as packed data register or memory. SRC is one or more fields for the source operands identifier, such as a packed data register and/or memory. In some examples, the opcode is provided by at least field <NUM>, DST field is provided by field <NUM>, the source is provided by bits VVVV of one of <NUM>, BPJ17, or <NUM>, or the source is provided by at least <NUM>. In some examples, the opcode is provided by at least field <NUM>, DST field is provided by at least field <NUM>, the source is provided by bits VVVV of one of <NUM>, BPJ17, or <NUM>, or the source is a memory location provided by at least <NUM> and/or the SIB byte <NUM>. IMM8 is an immediate provided by <NUM> which encodes a rounding mode. The source operand and destination operand may come in one or more sizes such as <NUM>-bit, <NUM>-bit, <NUM>-bit, etc. The {k} is used when writemasking or predication is used.

The packed data source <NUM> and immediate <NUM> are fed into execution circuitry <NUM> to be operated on. In particular, execution circuitry <NUM> (such as scale/reduce circuitry <NUM>) performs a round of FP8 data elements in the source operand <NUM> by a rounding mode specified by the immediate <NUM>. The rounding rounds the input to an integer value, plus a number of bits of fraction that are specified by the immediate (to be included in the result) to generate a per data element result and stores the results as FP8 values in the destination <NUM>. The rounding is defined in some embodiments as destination = <NUM> -M * Round to nearest even integer(<NUM>M * SRC). M is set by the immediate such as bits <NUM>:<NUM> of an <NUM>-bit immediate. In some embodiments, scale/reduce circuitry <NUM> of the execution circuitry <NUM> performs this operation.

In some embodiments, if any data element is a signaling non-a-number (SNaN) then it will be converted to a quiet not-a-number (QNaN). In some embodiments, this execution of the instruction uses a round to nearest (even) rounding mode. In some embodiments, output denormals are always flushed to zero and input denormals are always treated as zero. The sign of the result of this instruction is preserved, including the sign of zero.

The packed data destination <NUM> is written to store the resultant values in corresponding packed data elements as the packed data source <NUM>. In some embodiments, when the instruction calls for the use of predication or writemasking, a writemask (or predicate) register <NUM> dictates how the resultant values are stored and/or zeroed using the writemask circuitry <NUM>.

<FIG> illustrates embodiments of an exemplary method performed by a processor to process an instruction to round FP8 data elements according to some embodiments. For example, a processor core as shown herein, a pipeline as detailed below, etc. performs this method.

At <NUM> an instruction is fetched having fields for an opcode, an identification of a location of a packed data source operand, an indication of a rounding mode, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to, for each packed data element position of the packed data source operand, round the packed FP8 data element of that position by the indicated rounding mode and store a result of the round in a corresponding packed data element position of the packed data destination operand.

At <NUM>, the decoded instruction(s) is/are executed by execution circuitry (hardware) such as that detailed herein. The execution circuitry is to, for each packed data element position of the packed data source operand, round the packed FP8 data element of that position by the indicated rounding mode and store a result of the round in a corresponding packed data element position of the packed data destination operand. In some examples, the data elements are upscaled (e.g., to BF16, FP16, FP32, etc.) prior to the operation. Note upscaling, etc. may use a variable bias.

<FIG> illustrate exemplary embodiments of pseudo code representing the execution and format of a round FP8 data elements instruction. Note that EVEX. b maps to the b of prefix <NUM>(C). The comment of DAZ, FTZ, RNE, and SAE refer to the use of support for flush-to-zero (FTZ), denormals-are-zero (DAZ), suppress all exceptions (SAE), and round-to-even (RNE) rounding.

<FIG> illustrates embodiments of hardware to process an instruction such as the VSCALEFNEPFP8, VREDUCENEPFP8, and/or VRNDSCALENEPFP8 instructions. As illustrated, storage <NUM> stores a VSCALEFNEPFP8, VREDUCENEPFP8, and/or VRNDSCALENEPFP8 instruction <NUM> to be executed. Other instructions <NUM> may also be stored.

The instruction <NUM> is received by decode circuitry <NUM>. For example, the decode circuitry <NUM> receives this instruction from fetch logic/circuitry. The instruction includes fields for an opcode, one or more sources, and a destination. In some embodiments, the one or more sources and destination are registers, and in other embodiments one or more are memory locations. In some examples, the decode circuitry <NUM> is capable of decoding the other instructions <NUM>.

More detailed embodiments of at least one instruction format will be detailed later. The decode circuitry <NUM> decodes the instruction into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry <NUM>). The decode circuitry <NUM> also decodes instruction prefixes.

In some embodiments, register renaming, register allocation, and/or scheduling circuitry <NUM> provides functionality for one or more of: <NUM>) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), <NUM>) allocating status bits and flags to the decoded instruction, and <NUM>) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some embodiments).

Registers (register file) and/or memory <NUM> store data as operands of the instruction to be operated on by execution circuitry <NUM>. Exemplary register types include packed data registers, general purpose registers, and floating-point registers.

Execution circuitry <NUM> executes the decoded instruction. Exemplary detailed execution circuitry is shown in <FIG>, <FIG>, <FIG>, <FIG>, etc. The execution of the decoded instruction causes the execution circuitry to perform the operations detailed above.

In some embodiments, retirement/write back circuitry <NUM> architecturally commits the result <NUM> and retires the instruction.

As noted above, in some examples FP8 data elements are upscaled by upconversion circuitry and/or downscaled from FP16 or FP32 by downconversion circuitry. Detailed below are example pseudocode representing acts the conversion circuitries perform. In some examples, this pseudocode is usable to create such circuitry (other pseudocode also be used to create circuitry such as aspects of execution circuitry in some examples). In the code below, the input is a data element, an indication of the FP8 type, a bias, and an indication of NaN handling. Note that this is merely illustrative and some aspects may not be included (for example, the BF8 or HF8 may be indicated by the helper function itself). Note that use of variants of convert (e.g., CVT, UPSCALE), DOWNSCALE may be used in other places. For example, in some of the pseudocode the helper function is merely UPSCALE or DOWNSCALE and one or more of the helper functions below may be used in its place including the use of a bias. <IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>
<IMG>.

The instructions detailed above may be used in a variety of computer architectures and environments, utilize one or more instruction formats, etc. Examples of architectures, formats, etc. that support these instructions are detailed below.

Detailed below are descriptions of example computer architectures. Other system designs and configurations known in the arts for laptop, desktop, and handheld personal computers (PC)s, personal digital assistants, engineering workstations, servers, disaggregated servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand-held devices, and various other electronic devices, are also suitable. In general, a variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

<FIG> illustrates an example computing system. Multiprocessor system <NUM> is an interfaced system and includes a plurality of processors or cores including a first processor <NUM> and a second processor <NUM> coupled via an interface <NUM> such as a point-to-point (P-P) interconnect, a fabric, and/or bus. In some examples, the first processor <NUM> and the second processor <NUM> are homogeneous. In some examples, first processor <NUM> and the second processor <NUM> are heterogenous. Though the example system <NUM> is shown to have two processors, the system may have three or more processors, or may be a single processor system. In some examples, the computing system is a system on a chip (SoC).

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) circuitry <NUM> and <NUM>, respectively. Processor <NUM> also includes interface circuits <NUM> and <NUM>; similarly, second processor <NUM> includes interface circuits <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via the interface <NUM> using interface circuits <NUM>, <NUM>. IMCs <NUM> and <NUM> couple the processors <NUM>, <NUM> to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a network interface (NW I/F) <NUM> via individual interfaces <NUM>, <NUM> using interface circuits <NUM>, <NUM>, <NUM>, <NUM>. The network interface <NUM> (e.g., one or more of an interconnect, bus, and/or fabric, and in some examples is a chipset) may optionally exchange information with a coprocessor <NUM> via an interface circuit <NUM>. In some examples, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput processor, a network or communication processor, compression engine, graphics processor, general purpose graphics processing unit (GPGPU), neural-network processing unit (NPU), embedded processor, or the like.

A shared cache (not shown) may be included in either processor <NUM>, <NUM> or outside of both processors, yet connected with the processors via an interface such as P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Network interface <NUM> may be coupled to a first interface <NUM> via interface circuit <NUM>. In some examples, first interface <NUM> may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect or another I/O interconnect. In some examples, first interface <NUM> is coupled to a power control unit (PCU) <NUM>, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors <NUM>, <NUM> and/or co-processor <NUM>. PCU <NUM> provides control information to a voltage regulator (not shown) to cause the voltage regulator to generate the appropriate regulated voltage. PCU <NUM> also provides control information to control the operating voltage generated. In various examples, PCU <NUM> may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).

PCU <NUM> is illustrated as being present as logic separate from the processor <NUM> and/or processor <NUM>. In other cases, PCU <NUM> may execute on a given one or more of cores (not shown) of processor <NUM> or <NUM>. In some cases, PCU <NUM> may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCU <NUM> may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCU <NUM> may be implemented within BIOS or other system software.

Various I/O devices <NUM> may be coupled to first interface <NUM>, along with a bus bridge <NUM> which couples first interface <NUM> to a second interface <NUM>. In some examples, one or more additional processor(s) <NUM>, such as coprocessors, high throughput many integrated core (MIC) processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interface <NUM>. In some examples, second interface <NUM> may be a low pin count (LPC) interface. Various devices may be coupled to second interface <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and storage circuitry <NUM>. Storage circuitry <NUM> may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device which may include instructions/code and data <NUM> and may implement the storage 'ISAB03 in some examples. Further, an audio I/O <NUM> may be coupled to second interface <NUM>. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system <NUM> may implement a multi-drop interface or other such architecture.

Example Core Architectures, Processors, and Computer Architectures.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high-performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip (SoC) that may be included on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Example core architectures are described next, followed by descriptions of example processors and computer architectures.

<FIG> illustrates a block diagram of an example processor and/or SoC <NUM> that may have one or more cores and an integrated memory controller. The solid lined boxes illustrate a processor <NUM> with a single core <NUM>(A), system agent unit circuitry <NUM>, and a set of one or more interface controller unit(s) circuitry <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores <NUM>(A)-(N), a set of one or more integrated memory controller unit(s) circuitry <NUM> in the system agent unit circuitry <NUM>, and special purpose logic <NUM>, as well as a set of one or more interface controller units circuitry <NUM>. Note that the processor <NUM> may be one of the processors <NUM> or <NUM>, or co-processor <NUM> or <NUM> of <FIG>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores, not shown), and the cores <NUM>(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); <NUM>) a coprocessor with the cores <NUM>(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores <NUM>(A)-(N) being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

A memory hierarchy includes one or more levels of cache unit(s) circuitry <NUM>(A)-(N) within the cores <NUM>(A)-(N), a set of one or more shared cache unit(s) circuitry <NUM>, and external memory (not shown) coupled to the set of integrated memory controller unit(s) circuitry <NUM>. The set of one or more shared cache unit(s) circuitry <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples interface network circuitry <NUM> (e.g., a ring interconnect) interfaces the special purpose logic <NUM> (e.g., integrated graphics logic), the set of shared cache unit(s) circuitry <NUM>, and the system agent unit circuitry <NUM>, alternative examples use any number of well-known techniques for interfacing such units. In some examples, coherency is maintained between one or more of the shared cache unit(s) circuitry <NUM> and cores <NUM>(A)-(N). In some examples, interface controller units circuitry <NUM> couple the cores <NUM> to one or more other devices <NUM> such as one or more I/O devices, storage, one or more communication devices (e.g., wireless networking, wired networking, etc.), etc..

In some examples, one or more of the cores <NUM>(A)-(N) are capable of multi-threading. The system agent unit circuitry <NUM> includes those components coordinating and operating cores <NUM>(A)-(N). The system agent unit circuitry <NUM> may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores <NUM>(A)-(N) and/or the special purpose logic <NUM> (e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.

The cores <NUM>(A)-(N) may be homogenous in terms of instruction set architecture (ISA). Alternatively, the cores <NUM>(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores <NUM>(A)-(N) may be capable of executing an ISA, while other cores may be capable of executing only a subset of that ISA or another ISA.

Example Core Architectures - In-order and out-of-order core block diagram.

<FIG> is a block diagram illustrating both an example in-order pipeline and an example register renaming, out-of-order issue/execution pipeline according to examples. <FIG> is a block diagram illustrating both an example in-order architecture core and an example register renaming, out-of-order issue/execution architecture core to be included in a processor according to examples. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

In <FIG>, a processor pipeline <NUM> includes a fetch stage <NUM>, an optional length decoding stage <NUM>, a decode stage <NUM>, an optional allocation (Alloc) stage <NUM>, an optional renaming stage <NUM>, a schedule (also known as a dispatch or issue) stage <NUM>, an optional register read/memory read stage <NUM>, an execute stage <NUM>, a write back/memory write stage <NUM>, an optional exception handling stage <NUM>, and an optional commit stage <NUM>. One or more operations can be performed in each of these processor pipeline stages. For example, during the fetch stage <NUM>, one or more instructions are fetched from instruction memory, and during the decode stage <NUM>, the one or more fetched instructions may be decoded, addresses (e.g., load store unit (LSU) addresses) using forwarded register ports may be generated, and branch forwarding (e.g., immediate offset or a link register (LR)) may be performed. In one example, the decode stage <NUM> and the register read/memory read stage <NUM> may be combined into one pipeline stage. In one example, during the execute stage <NUM>, the decoded instructions may be executed, LSU address/data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiply and add operations may be performed, arithmetic operations with branch results may be performed, etc..

By way of example, the example register renaming, out-of-order issue/execution architecture core of <FIG> may implement the pipeline <NUM> as follows: <NUM>) the instruction fetch circuitry <NUM> performs the fetch and length decoding stages <NUM> and <NUM>; <NUM>) the decode circuitry <NUM> performs the decode stage <NUM>; <NUM>) the rename/allocator unit circuitry <NUM> performs the allocation stage <NUM> and renaming stage <NUM>; <NUM>) the scheduler(s) circuitry <NUM> performs the schedule stage <NUM>; <NUM>) the physical register file(s) circuitry <NUM> and the memory unit circuitry <NUM> perform the register read/memory read stage <NUM>; the execution cluster(s) <NUM> perform the execute stage <NUM>; <NUM>) the memory unit circuitry <NUM> and the physical register file(s) circuitry <NUM> perform the write back/memory write stage <NUM>; <NUM>) various circuitry may be involved in the exception handling stage <NUM>; and <NUM>) the retirement unit circuitry <NUM> and the physical register file(s) circuitry <NUM> perform the commit stage <NUM>.

<FIG> shows a processor core <NUM> including front-end unit circuitry <NUM> coupled to execution engine unit circuitry <NUM>, and both are coupled to memory unit circuitry <NUM>. The core <NUM> may be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type.

The front-end unit circuitry <NUM> may include branch prediction circuitry <NUM> coupled to instruction cache circuitry <NUM>, which is coupled to an instruction translation lookaside buffer (TLB) <NUM>, which is coupled to instruction fetch circuitry <NUM>, which is coupled to decode circuitry <NUM>. In one example, the instruction cache circuitry <NUM> is included in the memory unit circuitry <NUM> rather than the front-end circuitry <NUM>. The decode circuitry <NUM> (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode circuitry <NUM> may further include address generation unit (AGU, not shown) circuitry. In one example, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuitry <NUM> may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one example, the core <NUM> includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode circuitry <NUM> or otherwise within the front-end circuitry <NUM>). In one example, the decode circuitry <NUM> includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline <NUM>. The decode circuitry <NUM> may be coupled to rename/allocator unit circuitry <NUM> in the execution engine circuitry <NUM>.

The execution engine circuitry <NUM> includes the rename/allocator unit circuitry <NUM> coupled to retirement unit circuitry <NUM> and a set of one or more scheduler(s) circuitry <NUM>. The scheduler(s) circuitry <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. In some examples, the scheduler(s) circuitry <NUM> can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, address generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry <NUM> is coupled to the physical register file(s) circuitry <NUM>. Each of the physical register file(s) circuitry <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one example, the physical register file(s) circuitry <NUM> includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) circuitry <NUM> is coupled to the retirement unit circuitry <NUM> (also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry <NUM> and the physical register file(s) circuitry <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution unit(s) circuitry <NUM> and a set of one or more memory access circuitry <NUM>. The execution unit(s) circuitry <NUM> may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some examples may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other examples may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry <NUM>, physical register file(s) circuitry <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain examples create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) circuitry, and/or execution cluster - and in the case of a separate memory access pipeline, certain examples are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

In some examples, the execution engine unit circuitry <NUM> may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AMB) interface (not shown), and address phase and writeback, data phase load, store, and branches.

The set of memory access circuitry <NUM> is coupled to the memory unit circuitry <NUM>, which includes data TLB circuitry <NUM> coupled to data cache circuitry <NUM> coupled to level <NUM> (L2) cache circuitry <NUM>. In one example, the memory access circuitry <NUM> may include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to the data TLB circuitry <NUM> in the memory unit circuitry <NUM>. The instruction cache circuitry <NUM> is further coupled to the level <NUM> (L2) cache circuitry <NUM> in the memory unit circuitry <NUM>. In one example, the instruction cache <NUM> and the data cache <NUM> are combined into a single instruction and data cache (not shown) in L2 cache circuitry <NUM>, level <NUM> (L3) cache circuitry (not shown), and/or main memory. The L2 cache circuitry <NUM> is coupled to one or more other levels of cache and eventually to a main memory.

The core <NUM> may support one or more instructions sets (e.g., the x86 instruction set architecture (optionally with some extensions that have been added with newer versions); the MIPS instruction set architecture; the ARM instruction set architecture (optionally with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, the core <NUM> includes logic to support a packed data instruction set architecture extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

<FIG> illustrates examples of execution unit(s) circuitry, such as execution unit(s) circuitry <NUM> of <FIG>. As illustrated, execution unit(s) circuity <NUM> may include one or more ALU circuits <NUM>, optional vector/single instruction multiple data (SIMD) circuits <NUM>, load/store circuits <NUM>, branch/jump circuits <NUM>, and/or Floating-point unit (FPU) circuits <NUM>. ALU circuits <NUM> perform integer arithmetic and/or Boolean operations. Vector/SIMD circuits <NUM> perform vector/SIMD operations on packed data (such as SIMD/vector registers). Load/store circuits <NUM> execute load and store instructions to load data from memory into registers or store from registers to memory. Load/store circuits <NUM> may also generate addresses. Branch/jump circuits <NUM> cause a branch or jump to a memory address depending on the instruction. FPU circuits <NUM> perform floating-point arithmetic. The width of the execution unit(s) circuitry <NUM> varies depending upon the example and can range from <NUM>-bit to <NUM>,<NUM>-bit, for example. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two <NUM>-bit execution units are logically combined to form a <NUM>-bit execution unit).

<FIG> is a block diagram of a register architecture <NUM> according to some examples. As illustrated, the register architecture <NUM> includes vector/SIMD registers <NUM> that vary from <NUM>-bit to <NUM>,<NUM> bits width. In some examples, the vector/SIMD registers <NUM> are physically <NUM>-bits and, depending upon the mapping, only some of the lower bits are used. For example, in some examples, the vector/SIMD registers <NUM> are ZMM registers which are <NUM> bits: the lower <NUM> bits are used for YMM registers and the lower <NUM> bits are used for XMM registers. As such, there is an overlay of registers. In some examples, a vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length. Scalar operations are operations performed on the lowest order data element position in a ZMM/YMM/XMM register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the example.

In some examples, the register architecture <NUM> includes writemask/predicate registers <NUM>. For example, in some examples, there are <NUM> writemask/predicate registers (sometimes called k0 through k7) that are each <NUM>-bit, <NUM>-bit, <NUM>-bit, or <NUM>-bit in size. Writemask/predicate registers <NUM> may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given writemask/predicate register <NUM> corresponds to a data element position of the destination. In other examples, the writemask/predicate registers <NUM> are scalable and consists of a set number of enable bits for a given vector element (e.g., <NUM> enable bits per <NUM>-bit vector element).

The register architecture <NUM> includes a plurality of general-purpose registers <NUM>. These registers may be <NUM>-bit, <NUM>-bit, <NUM>-bit, etc. and can be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

In some examples, the register architecture <NUM> includes scalar floating-point (FP) register file <NUM> which is used for scalar floating-point operations on <NUM>/<NUM>/<NUM>-bit floating-point data using the x87 instruction set architecture extension or as MMX registers to perform operations on <NUM>-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

One or more flag registers <NUM> (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers <NUM> may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, the one or more flag registers <NUM> are called program status and control registers.

Segment registers <NUM> contain segment points for use in accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

Model specific registers or machine specific registers (MSRs) <NUM> control and report on processor performance. Most MSRs <NUM> handle system-related functions and are not accessible to an application program. For example, MSRs may provide control for one or more of: performance-monitoring counters, debug extensions, memory type range registers, thermal and power management, instruction-specific support, and/or processor feature/mode support. Machine check registers <NUM> consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors. Control register(s) <NUM> (e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM>) and the characteristics of a currently executing task. In some examples, MSRs <NUM> are a subset of control registers <NUM>.

One or more instruction pointer register(s) <NUM> store an instruction pointer value. Debug registers <NUM> control and allow for the monitoring of a processor or core's debugging operations.

Memory (mem) management registers <NUM> specify the locations of data structures used in protected mode memory management. These registers may include a global descriptor table register (GDTR), interrupt descriptor table register (IDTR), task register, and a local descriptor table register (LDTR) register.

Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, less, or different register files and registers. The register architecture <NUM> may, for example, be used in register file / memory 'ISAB08, or physical register file(s) circuitry <NUM><NUM>.

An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down through the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an example ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. In addition, though the description below is made in the context of x86 ISA, it is within the knowledge of one skilled in the art to apply the teachings of the present disclosure in another ISA.

Examples of the instruction(s) described herein may be embodied in different formats. Additionally, example systems, architectures, and pipelines are detailed below. Examples of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

<FIG> illustrates examples of an instruction format. As illustrated, an instruction may include multiple components including, but not limited to, one or more fields for: one or more prefixes <NUM>, an opcode <NUM>, addressing information <NUM> (e.g., register identifiers, memory addressing information, etc.), a displacement value <NUM>, and/or an immediate value <NUM>. Note that some instructions utilize some or all the fields of the format whereas others may only use the field for the opcode <NUM>. In some examples, the order illustrated is the order in which these fields are to be encoded, however, it should be appreciated that in other examples these fields may be encoded in a different order, combined, etc..

The prefix(es) field(s) <NUM>, when used, modifies an instruction. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered "legacy" prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the "legacy" prefixes.

The opcode field <NUM> is used to at least partially define the operation to be performed upon a decoding of the instruction. In some examples, a primary opcode encoded in the opcode field <NUM> is one, two, or three bytes in length. In other examples, a primary opcode can be a different length. An additional <NUM>-bit opcode field is sometimes encoded in another field.

The addressing information field <NUM> is used to address one or more operands of the instruction, such as a location in memory or one or more registers. <FIG> illustrates examples of the addressing information field <NUM>. In this illustration, an optional MOD R/M byte <NUM> and an optional Scale, Index, Base (SIB) byte <NUM> are shown. The MOD R/M byte <NUM> and the SIB byte <NUM> are used to encode up to two operands of an instruction, each of which is a direct register or effective memory address. Note that both of these fields are optional in that not all instructions include one or more of these fields. The MOD R/M byte <NUM> includes a MOD field <NUM>, a register (reg) field <NUM>, and R/M field <NUM>.

The content of the MOD field <NUM> distinguishes between memory access and non-memory access modes. In some examples, when the MOD field <NUM> has a binary value of <NUM> (11b), a register-direct addressing mode is utilized, and otherwise a register-indirect addressing mode is used.

The register field <NUM> may encode either the destination register operand or a source register operand or may encode an opcode extension and not be used to encode any instruction operand. The content of register field <NUM>, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some examples, the register field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing.

The R/M field <NUM> may be used to encode an instruction operand that references a memory address or may be used to encode either the destination register operand or a source register operand. Note the R/M field <NUM> may be combined with the MOD field <NUM> to dictate an addressing mode in some examples.

The SIB byte <NUM> includes a scale field <NUM>, an index field <NUM>, and a base field <NUM> to be used in the generation of an address. The scale field <NUM> indicates a scaling factor. The index field <NUM> specifies an index register to use. In some examples, the index field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing. The base field <NUM> specifies a base register to use. In some examples, the base field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing. In practice, the content of the scale field <NUM> allows for the scaling of the content of the index field <NUM> for memory address generation (e.g., for address generation that uses <NUM>scale * index + base).

Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to <NUM>scale * index + base + displacement, index*scale + displacement, r/m + displacement, instruction pointer (RIP/EIP) + displacement, register + displacement, etc. The displacement may be a <NUM>-byte, <NUM>-byte, <NUM>-byte, etc. value. In some examples, the displacement field <NUM> provides this value. Additionally, in some examples, a displacement factor usage is encoded in the MOD field of the addressing information field <NUM> that indicates a compressed displacement scheme for which a displacement value is calculated and stored in the displacement field <NUM>.

In some examples, the immediate value field <NUM> specifies an immediate value for the instruction. An immediate value may be encoded as a <NUM>-byte value, a <NUM>-byte value, a <NUM>-byte value, etc..

<FIG> illustrates examples of a first prefix <NUM>(A). In some examples, the first prefix <NUM>(A) is an example of a REX prefix. Instructions that use this prefix may specify general purpose registers, <NUM>-bit packed data registers (e.g., single instruction, multiple data (SIMD) registers or vector registers), and/or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

Instructions using the first prefix <NUM>(A) may specify up to three registers using <NUM>-bit fields depending on the format: <NUM>) using the reg field <NUM> and the R/M field <NUM> of the MOD R/M byte <NUM>; <NUM>) using the MOD R/M byte <NUM> with the SIB byte <NUM> including using the reg field <NUM> and the base field <NUM> and index field <NUM>; or <NUM>) using the register field of an opcode.

In the first prefix <NUM>(A), bit positions <NUM>:<NUM> are set as <NUM>. Bit position <NUM> (W) can be used to determine the operand size but may not solely determine operand width. As such, when W = <NUM>, the operand size is determined by a code segment descriptor (CS. D) and when W = <NUM>, the operand size is <NUM>-bit.

Note that the addition of another bit allows for <NUM> (<NUM><NUM>) registers to be addressed, whereas the MOD R/M reg field <NUM> and MOD R/M R/M field <NUM> alone can each only address <NUM> registers.

In the first prefix <NUM>(A), bit position <NUM> (R) may be an extension of the MOD R/M reg field <NUM> and may be used to modify the MOD R/M reg field <NUM> when that field encodes a general-purpose register, a <NUM>-bit packed data register (e.g., a SSE register), or a control or debug register. R is ignored when MOD R/M byte <NUM> specifies other registers or defines an extended opcode.

Bit position <NUM> (X) may modify the SIB byte index field <NUM>.

Bit position <NUM> (B) may modify the base in the MOD R/M R/M field <NUM> or the SIB byte base field <NUM>; or it may modify the opcode register field used for accessing general purpose registers (e.g., general purpose registers <NUM>).

<FIG> illustrate examples of how the R, X, and B fields of the first prefix <NUM>(A) are used. <FIG> illustrates R and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> and R/M field <NUM> of the MOD R/M byte <NUM> when the SIB byte <NUM><NUM> is not used for memory addressing. <FIG> illustrates R and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> and R/M field <NUM> of the MOD R/M byte <NUM> when the SIB byte <NUM><NUM> is not used (register-register addressing). <FIG> illustrates R, X, and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> of the MOD R/M byte <NUM> and the index field <NUM> and base field <NUM> when the SIB byte <NUM><NUM> being used for memory addressing. <FIG> illustrates B from the first prefix <NUM>(A) being used to extend the reg field <NUM> of the MOD R/M byte <NUM> when a register is encoded in the opcode <NUM>.

<FIG> illustrate examples of a second prefix <NUM>(B). In some examples, the second prefix <NUM>(B) is an example of a VEX prefix. The second prefix <NUM>(B) encoding allows instructions to have more than two operands, and allows SIMD vector registers (e.g., vector/SIMD registers <NUM>) to be longer than <NUM>-bits (e.g., <NUM>-bit and <NUM>-bit). The use of the second prefix <NUM>(B) provides for three-operand (or more) syntax. For example, previous two- operand instructions performed operations such as A = A + B, which overwrites a source operand. The use of the second prefix <NUM>(B) enables operands to perform nondestructive operations such as A = B + C.

In some examples, the second prefix <NUM>(B) comes in two forms - a two-byte form and a three-byte form. The two-byte second prefix <NUM>(B) is used mainly for <NUM>-bit, scalar, and some <NUM>-bit instructions; while the three-byte second prefix <NUM>(B) provides a compact replacement of the first prefix <NUM>(A) and <NUM>-byte opcode instructions.

<FIG> illustrates examples of a two-byte form of the second prefix <NUM>(B). In one example, a format field <NUM> (byte <NUM><NUM>) contains the value C5H. In one example, byte <NUM><NUM> includes an "R" value in bit[<NUM>]. This value is the complement of the "R" value of the first prefix <NUM>(A). Bit[<NUM>] is used to dictate the length (L) of the vector (where a value of <NUM> is a scalar or <NUM>-bit vector and a value of <NUM> is a <NUM>-bit vector). Bits[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). Bits[<NUM>:<NUM>] shown as vvvv may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

Instructions that use this prefix may use the MOD R/M R/M field <NUM> to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.

Instructions that use this prefix may use the MOD R/M reg field <NUM> to encode either the destination register operand or a source register operand, or to be treated as an opcode extension and not used to encode any instruction operand.

For instruction syntax that support four operands, vvvv, the MOD R/M R/M field <NUM> and the MOD R/M reg field <NUM> encode three of the four operands. Bits[<NUM>:<NUM>] of the immediate value field <NUM> are then used to encode the third source register operand.

<FIG> illustrates examples of a three-byte form of the second prefix <NUM>(B). In one example, a format field <NUM> (byte <NUM><NUM>) contains the value C4H. Byte <NUM><NUM> includes in bits[<NUM>:<NUM>] "R," "X," and "B" which are the complements of the same values of the first prefix <NUM>(A). Bits[<NUM>:<NUM>] of byte <NUM><NUM> (shown as mmmmm) include content to encode, as need, one or more implied leading opcode bytes. For example, <NUM> implies a 0FH leading opcode, <NUM> implies a 0F38H leading opcode, <NUM> implies a 0F3AH leading opcode, etc..

Bit[<NUM>] of byte <NUM><NUM> is used similar to W of the first prefix <NUM>(A) including helping to determine promotable operand sizes. Bit[<NUM>] is used to dictate the length (L) of the vector (where a value of <NUM> is a scalar or <NUM>-bit vector and a value of <NUM> is a <NUM>-bit vector). Bits[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). Bits[<NUM>:<NUM>], shown as vvvv, may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

For instruction syntax that support four operands, vvvv, the MOD R/M R/M field <NUM>, and the MOD R/M reg field <NUM> encode three of the four operands. Bits[<NUM>:<NUM>] of the immediate value field <NUM> are then used to encode the third source register operand.

<FIG> illustrates examples of a third prefix <NUM>(C). In some examples, the third prefix <NUM>(C) is an example of an EVEX prefix. The third prefix <NUM>(C) is a four-byte prefix.

The third prefix <NUM>(C) can encode <NUM> vector registers (e.g., <NUM>-bit, <NUM>-bit, and <NUM>-bit registers) in <NUM>-bit mode. In some examples, instructions that utilize a writemask/opmask (see discussion of registers in a previous figure, such as <FIG>) or predication utilize this prefix. Opmask register allow for conditional processing or selection control. Opmask instructions, whose source/destination operands are opmask registers and treat the content of an opmask register as a single value, are encoded using the second prefix <NUM>(B).

The third prefix <NUM>(C) may encode functionality that is specific to instruction classes (e.g., a packed instruction with "load+op" semantic can support embedded broadcast functionality, a floating-point instruction with rounding semantic can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantic can support "suppress all exceptions" functionality, etc.).

The first byte of the third prefix <NUM>(C) is a format field <NUM> that has a value, in one example, of <NUM>. Subsequent bytes are referred to as payload bytes <NUM>-<NUM> and collectively form a <NUM>-bit value of P[<NUM>:<NUM>] providing specific capability in the form of one or more fields (detailed herein).

In some examples, P[<NUM>:<NUM>] of payload byte <NUM> are identical to the low two mm bits. P[<NUM>:<NUM>] are reserved in some examples. Bit P[<NUM>] (R') allows access to the high <NUM> vector register set when combined with P[<NUM>] and the MOD R/M reg field <NUM>. P[<NUM>] can also provide access to a high <NUM> vector register when SIB-type addressing is not needed. P[<NUM>:<NUM>] consist of R, X, and B which are operand specifier modifier bits for vector register, general purpose register, memory addressing and allow access to the next set of <NUM> registers beyond the low <NUM> registers when combined with the MOD R/M register field <NUM> and MOD R/M R/M field <NUM>. P[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). P[<NUM>] in some examples is a fixed value of <NUM>. P[<NUM>:<NUM>], shown as vvvv, may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

P[<NUM>] is similar to W of the first prefix <NUM>(A) and second prefix <NUM>(B) and may serve as an opcode extension bit or operand size promotion.

P[<NUM>:<NUM>] specify the index of a register in the opmask (writemask) registers (e.g., writemask/predicate registers <NUM>). In one example, the specific value aaa = <NUM> has a special behavior implying no opmask is used for the particular instruction (this may be implemented in a variety of ways including the use of a opmask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one example, preserving the old value of each element of the destination where the corresponding mask bit has a <NUM>. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one example, an element of the destination is set to <NUM> when the corresponding mask bit has a <NUM> value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the opmask field allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While examples are described in which the opmask field's content selects one of a number of opmask registers that contains the opmask to be used (and thus the opmask field's content indirectly identifies that masking to be performed), alternative examples instead or additional allow the mask write field's content to directly specify the masking to be performed.

P[<NUM>] can be combined with P[<NUM>:<NUM>] to encode a second source vector register in a non-destructive source syntax which can access an upper <NUM> vector registers using P[<NUM>]. P[<NUM>] encodes multiple functionalities, which differs across different classes of instructions and can affect the meaning of the vector length/ rounding control specifier field (P[<NUM>:<NUM>]). P[<NUM>] indicates support for merging-writemasking (e.g., when set to <NUM>) or support for zeroing and merging-writemasking (e.g., when set to <NUM>).

Example examples of encoding of registers in instructions using the third prefix <NUM>(C) are detailed in the following tables.

Program code may be applied to input information to perform the functions described herein and generate output information. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.

The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system.

Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Examples may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as "intellectual property (IP) cores" may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that make the logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.

In some cases, an instruction converter may be used to convert an instruction from a source instruction set architecture to a target instruction set architecture.

<FIG> is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source ISA to binary instructions in a target ISA according to examples. In the illustrated example, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. <FIG> shows a program in a high-level language <NUM> may be compiled using a first ISA compiler <NUM> to generate first ISA binary code <NUM> that may be natively executed by a processor with at least one first ISA core <NUM>. The processor with at least one first ISA core <NUM> represents any processor that can perform substantially the same functions as an Intel® processor with at least one first ISA core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the first ISA or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one first ISA core, in order to achieve substantially the same result as a processor with at least one first ISA core. The first ISA compiler <NUM> represents a compiler that is operable to generate first ISA binary code <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one first ISA core <NUM>. Similarly, <FIG> shows the program in the high-level language <NUM> may be compiled using an alternative ISA compiler <NUM> to generate alternative ISA binary code <NUM> that may be natively executed by a processor without a first ISA core <NUM>. The instruction converter <NUM> is used to convert the first ISA binary code <NUM> into code that may be natively executed by the processor without a first ISA core <NUM>. This converted code is not necessarily to be the same as the alternative ISA binary code <NUM>; however, the converted code will accomplish the general operation and be made up of instructions from the alternative ISA. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have a first ISA processor or core to execute the first ISA binary code <NUM>.

References to "one example," "an example," etc., indicate that the example described may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. Further, when a particular feature, structure, or characteristic is described in connection with an example, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other examples whether or not explicitly described.

Moreover, in the various examples described above, unless specifically noted otherwise, disjunctive language such as the phrase "at least one of A, B, or C" or "A, B, and/or C" is intended to be understood to mean either A, B, or C, or any combination thereof (i.e. A and B, A and C, B and C, and A, B and C).

Claim 1:
An apparatus comprising:
decode circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a location of a first packed data source (<NUM>) operand, an identification of a location of a second packed data source (<NUM>) operand, and an identification of a packed data destination (<NUM>) operand, wherein the opcode is to indicate that execution circuitry (<NUM>) is to perform, for each data element position of the packed data source (<NUM>, <NUM>) operands, a floating point scale operation of a FP8 data element of the first packed data source (<NUM>) by multiplying the data element by a power of <NUM> value, wherein a value of the exponent of the power of <NUM> value is a floor value of a FP8 data element of the second packed data source (<NUM>), and store a result of the floating point scale operation into a corresponding data element position of the packed data destination (<NUM>) operand; and
the execution circuitry (<NUM>) to execute the decoded instruction according to the opcode,
wherein the floor value is a zero when the data element of the second packed data source (<NUM>) is a denormal and wherein the data element of the first packed data source (<NUM>) is a zero when the data element of the first packed data source (<NUM>) is a denormal.