Patent Description:
A semiconductor package structure can not only provide a semiconductor die with protection from environmental contaminants, but it can also provide an electrical connection between the semiconductor die packaged therein and a substrate, such as a printed circuit board (PCB).

Heat is generated during the operation of the semiconductor die. If the heat is not adequately removed, the increased temperatures may result in damage to the semiconductor components, and may cause thermal stress and warpage of the semiconductor package structure.

A heat dissipation device is needed to be disposed in the semiconductor package structure. A heatsink is commonly used to transfer the heat away. A thermal interface material is interposed between the semiconductor die and the heatsink to facilitate heat transfer from the semiconductor die to the heatsink. However, while existing heat dissipation devices in the semiconductor package structure generally meet requirements, they are not satisfactory in every respect, and further improvements are needed to improve the heat-dissipation efficiency.

A semiconductor package structure according to the preamble of claim <NUM> is known from <CIT>, <CIT> and <CIT>. Further relevant disclosures are <CIT> and <CIT>.

The invention provides a semiconductor package structure according to claim <NUM>. Embodiments are provided in the dependent claims.

The scope of the invention is determined by reference to the appended claims.

The present invention is described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

<FIG> is a cross-sectional view of a semiconductor package structure <NUM>. Additional features can be added to the semiconductor package structure <NUM>. Some of the features described below can be replaced or eliminated for different embodiments. To simplify the diagram, only a portion of the semiconductor package structure <NUM> is depicted in <FIG>.

As illustrated in <FIG>, a substrate <NUM> is provided. The substrate <NUM> may be a coreless/core substrate or a printed circuit board (PCB). The substrate <NUM> may be formed of polypropylene (PP), Polyimide, BT/Epoxy, Prepreg, ABF, ceramic material or other suitable material. Any desired semiconductor element may be formed in and on the substrate <NUM>. However, in order to simplify the Figures, only the flat substrate <NUM> is illustrated.

The semiconductor package structure <NUM> may include a semiconductor die <NUM> disposed over the substrate <NUM>. For the sake of simplicity, <FIG> only shows one semiconductor die <NUM>, in accordance with some embodiments. In some embodiments, multiple semiconductor dies <NUM> could be disposed over the substrate <NUM> and arranged side-by-side. In some embodiments, the semiconductor die <NUM> is an active device. For example, the semiconductor die <NUM> is a system-on-chip (SOC) die that may include a microcontroller (MCU), a microprocessor (MPU), a power management integrated circuit (PMIC), a global positioning system (GPS) device, or a radio frequency (RF) device, the like, or any combination thereof. Alternatively, the semiconductor die <NUM> may be a logic die that may include a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller, the like, or any combination thereof. In some other embodiments, one or more passive devices are also bonded onto the substrate <NUM>, such as resistors, capacitors, inductors, the like, or a combination thereof.

The semiconductor package structure <NUM> includes a molding material <NUM> surrounding the semiconductor die <NUM>. The molding material <NUM> may adjoin the sidewalls of the semiconductor die <NUM>. Although the upper surface of the semiconductor die <NUM> is exposed as illustrated, the upper surface of the semiconductor die <NUM> may also be covered by the molding material <NUM>.

In some embodiments, the molding material <NUM> includes a nonconductive material such as an epoxy, a resin, a moldable polymer, or another suitable molding material. In some embodiments, the molding material <NUM> is applied as a substantial liquid, and then is cured through a chemical reaction. In some other embodiments, the molding material <NUM> is an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid, and then is cured through a UV or thermal curing process. The molding material <NUM> may be cured with a mold (not illustrated).

As illustrated in <FIG>, the semiconductor die <NUM> and the molding material <NUM> are bonded onto the substrate <NUM> through a conductive element <NUM>, in accordance with some embodiments. In some embodiments, the conductive element <NUM> includes conductive ball structures, conductive pillar structures, or conductive paste structures that are mounted on and electrically coupled to the substrate <NUM> in the bonding process. For example, the conductive element <NUM> may be land grid array (LGA), ball grid array (BGA), the like, or a combination thereof.

As illustrated in <FIG>, the semiconductor package structure <NUM> includes a heatsink <NUM> bonded onto the semiconductor die <NUM> through a thermal interface material <NUM>. The heatsink <NUM> may be made of Cu, Al, the like, or a combination thereof. The thermal interface material <NUM> may include a polymer which is adhesive. For example, the thermal interface material <NUM> may be silicone adhesive, such as SE4450 epoxy from Dow-Corning. In other example, the thermal interface material <NUM> may also include ceramic material, such as crystalline oxide, nitride or carbide material.

However, side effects may occur when only using the thermal interface material <NUM> to connect the heatsink <NUM> and the semiconductor die <NUM>. Typically, the thermal interface material <NUM> with high viscosity has low thermal conductivity. Therefore, the thermal interface material <NUM> may be the thermal bottleneck between the semiconductor die <NUM> and the heatsink <NUM>. Therefore, the present disclosure provides another embodiment to solve the above problem.

<FIG> is a cross-sectional view of a semiconductor package structure <NUM>, in accordance with embodiments of the invention. It should be noted that the semiconductor package structure <NUM> may include the same or similar components as that of the semiconductor package structure <NUM>, which is illustrated in <FIG>, and for the sake of simplicity, those components will not be discussed in detail again. In comparison with the embodiment of <FIG> where the heatsink <NUM> and the semiconductor die <NUM> are bonded only through the thermal interface material <NUM>, the following embodiments will replace a portion of the thermal interface material <NUM> with a bonding layer to improve the heat-dissipation efficiency.

Additional features can be added to the semiconductor package structure <NUM>. Some of the features described below can be replaced or eliminated for different embodiments. To simplify the diagram, only a portion of the semiconductor package structure <NUM> is depicted in <FIG>.

As illustrated in <FIG>, a metal layer <NUM> is disposed on the semiconductor die <NUM> to provide a surface for the bonding layer to form thereon. The metal layer <NUM> may be formed on the semiconductor die <NUM> through a backside metallization (BSM) technology. In some embodiments, the metal layer <NUM> is formed by chemical vapor deposition, sputter deposition, plating, the like, or a combination thereof. The metal layer <NUM> may include gold, silver, chromium, titanium, tungsten, vanadium, nickel, the like, an alloy thereof, or a combination thereof. The metal layer <NUM> may also include Stainless Steel (SUS) material. The metal layer <NUM> may be a single layer or multiple layers.

Although the semiconductor die <NUM> is coplanar with the molding material <NUM> as illustrated, the present disclosure is not limit thereto. For example, in some embodiments, the molding material <NUM> is formed after the formation of the metal layer <NUM>, and the molding material <NUM> also surrounds the metal layer <NUM>. In these embodiments, the molding material <NUM> is coplanar with the metal layer <NUM>.

As illustrated in <FIG>, a bonding layer <NUM> is disposed on the metal layer <NUM>. The bonding layer <NUM> may include a metal or solder material. For example, the bonding layer <NUM> may be lead, tin, indium, silver, copper, the like, an alloy thereof, or a combination thereof. Since the bonding layer <NUM> has better thermal conductivity than the thermal interface material <NUM>, such as <NUM> times thermal conductivity than the thermal interface material <NUM>, the heat-dissipation efficiency can be improved by disposing the bonding layer <NUM>.

However, if only the bonding layer <NUM> is used to bond the heatsink <NUM> to the semiconductor die <NUM>, the stress may be high. In this case, the bonding layer <NUM> may fragile during the sequential process, such as surface mount technology (SMT), thereby causing yield loss. Therefore, the semiconductor package structure <NUM> according to the present disclosure includes both of the thermal interface material <NUM> and the bonding layer <NUM>, thereby improving the heat-dissipation efficiency without increasing stress, which is preferred for high-power applications. As a result, thermal performance, manufacturability and the reliability can be enhanced at the same time.

As illustrated in <FIG>, the heatsink <NUM> is connected to the molding material <NUM> through the thermal interface material <NUM>, and connected to the semiconductor die <NUM> through the metal layer <NUM> and the bonding layer <NUM>. The thermal interface material <NUM> may be disposed on the edge of the molding layer <NUM>. In particular, the sidewall of the thermal interface material <NUM> may be aligned with the sidewall of the molding layer <NUM>.

The thermal interface material <NUM> is spaced apart from the metal layer <NUM> and the bonding layer <NUM> by a first gap to prevent the issues caused by the different coefficients of thermal expansion (CTE) of the thermal interface material <NUM> and the metal layer <NUM> and the bonding layer <NUM>. As a result, the reliability of the semiconductor package structure can be improved.

In some embodiments, the thermal interface material <NUM> is thicker than the metal layer <NUM> and is thicker than the bonding layer <NUM> to provide a planar surface for bonding the heatsink <NUM> thereon. Alternatively, as described above, in some other embodiments, the molding material <NUM> is coplanar with the metal layer <NUM>. In these embodiments, the thickness of the thermal interface material <NUM> may be substantially equal to the thickness of the bonding layer <NUM> to provide a planar surface for bonding the heatsink <NUM> thereon.

<FIG> are plan views of a semiconductor package structure, in accordance with embodiments of the invention. It should be noted that <FIG> may be the plan view from the top of the semiconductor package structure <NUM>, which is illustrated in <FIG>, and some components are omitted for brevity.

As illustrated in <FIG>, which only illustrates some aspects of the invention, the thermal interface material <NUM> surrounds the bonding layer <NUM>, in accordance with embodiments. Although not illustrated, the thermal interface material <NUM> may also surround the metal layer <NUM> (referring to <FIG>) disposed below the bonding layer <NUM>. The thermal interface material <NUM> may be disposed on the edge of the molding layer <NUM>. In particular, the sidewall of the thermal interface material <NUM> may be aligned with the sidewall of the molding layer <NUM>.

As illustrated in <FIG>, the thermal interface material <NUM> partially surrounds the bonding layer <NUM>, in accordance with some embodiments. Although not illustrated, the thermal interface material <NUM> may also partially surround the metal layer <NUM> disposed below the bonding layer <NUM>. In other words, the thermal interface material <NUM> is cut off by a second gap <NUM>, in some embodiments. The second gap <NUM> may release the gas generated during the manufacturing process. Therefore, the reliability of the semiconductor package structure can be further improved.

Although only one second gap <NUM> is illustrated in <FIG>, the present disclosure is not limited thereto. For example, the thermal interface material <NUM> may be cut off by a plurality of second gaps. In particular, the thermal interface material <NUM> may include a plurality of separate sections.

In some embodiments, instead of being cut off by second gaps, the thermal interface material <NUM> has a notch (not illustrated) to release the gas. In other embodiments, the thermal interface material <NUM> is cut off by one or more second gaps <NUM> and/or has one or more notches.

<FIG> is a cross-sectional view of a semiconductor package structure <NUM>, in accordance with some other embodiments of the invention. It should be noted that the semiconductor package structure <NUM> may include the same or similar components as that of the semiconductor package structure <NUM>, which is illustrated in <FIG>, and for the sake of simplicity, those components will not be discussed in detail again. In comparison with the embodiment of <FIG> where the thermal interface material <NUM> is disposed on the edge of the molding layer <NUM>, the thermal interface material <NUM> is disposed on the periphery of the molding layer <NUM>. In particular, the sidewalls of the thermal interface material <NUM> may be inside the sidewalls of the molding layer <NUM>.

<FIG> are plan views of a semiconductor package structure, in accordance with some embodiments of the invention. It should be noted that <FIG> may be the plan view from the top of the semiconductor package structure <NUM>, which is illustrated in <FIG>, and some components are omitted for brevity.

As illustrated in <FIG>, which only illustrates some aspects of the invention, the thermal interface material <NUM> surrounds the bonding layer <NUM>, in accordance with some embodiments. Although not illustrated, the thermal interface material <NUM> may also surround the metal layer <NUM> (referring to <FIG>) disposed below the bonding layer <NUM>. The thermal interface material <NUM> may be disposed on the periphery of the molding layer <NUM>.

In some embodiments, the thermal interface material <NUM> is spaced apart from the metal layer <NUM> and the bonding layer <NUM> by a first gap to prevent the issues caused by the different coefficients of thermal expansion (CTE) of the thermal interface material <NUM> and the metal layer <NUM> and the bonding layer <NUM>. As a result, the reliability of the semiconductor package structure can be improved.

Although only one second gap <NUM> is illustrated in <FIG>, the present disclosure is not limited thereto. For example, the thermal interface material <NUM> may be cut off by a plurality of second gaps, as illustrated in <FIG>. In particular, the thermal interface material <NUM> may include a plurality of separate sections.

<FIG> is a cross-sectional view of a semiconductor package structure <NUM>, in accordance with some other embodiments of the invention. It should be noted that the semiconductor package structure <NUM> may include the same or similar components as that of the semiconductor package structure <NUM>, and for the sake of simplicity, those components will not be discussed in detail again. In comparison with the embodiment of <FIG> where the heatsink <NUM> is disposed over the substrate <NUM>, the following embodiments further provides another heatsink disposed below the substrate <NUM> to further improve the heat-dissipation efficiency.

As illustrated in <FIG>, the semiconductor package structure <NUM> includes the heatsink <NUM> and a heatsink <NUM> disposed on opposite sides of the substrate <NUM>, in accordance with some embodiments. The heatsink <NUM> may be bonded onto the substrate <NUM> through a bonding layer <NUM>. The bonding layer <NUM> may include a metal or solder material. For example, the bonding layer <NUM> may be lead, tin, indium, silver, copper, the like, an alloy thereof, or a combination thereof. Although only two heatsinks (the heatsink <NUM> and the heatsink <NUM>) are illustrated, the present disclosure may include more than two heatsinks as needed.

In an embodiment, the heatsink <NUM> is bonded before bonding the heatsink <NUM>. In this embodiment, if the temperature of bonding the heatsink <NUM> is higher than or substantially equal to the melting point of the bonding layer <NUM>, the bonding layer <NUM> will melt and cause the heatsink <NUM> to fall off during the process such as reflow. In this regard, the bonding layer <NUM> having a melting point lower than the bonding layer <NUM> can prevent this issue, in accordance with some embodiments. For example, the bonding layer <NUM> may include SnBi, SnBiAg, the like, or a combination thereof.

Similarly, the composition of the bonding layers may be adjusted based on the process sequence. For example, if the heatsink <NUM> is bonded before bonding the heatsink <NUM>, the bonding layer <NUM> used for bonding the heatsink <NUM> may have a melting point lower than the bonding layer <NUM> used for bonding the heatsink <NUM>. Therefore, the reliability of the semiconductor package structure <NUM> can be improved.

In summary, the present disclosure provides a semiconductor package structure including the bonding layer and the thermal interface material, which are used to bond the heatsink onto the substrate, so that the heat-dissipation efficiency can be improved without increasing the stress. Therefore, thermal performance, manufacturability and the reliability of the semiconductor package structure can be enhanced at the same time.

Furthermore, according to the invention, the thermal interface material and the bonding layer are spaced apart by a first gap to prevent the CTE mismatch. In addition, according to the invention, the thermal interface material cut off by one or more second gaps and/or the thermal interface material having one or more notches can release the gas generated during the manufacturing process.

Moreover, in some embodiments, the semiconductor package structure has a plurality of heatsinks on opposite sides to further improve the heat-dissipation efficiency. In the embodiment where the heatsink is bonded onto the semiconductor die after the other heatsink is bonded onto the substrate, the bonding layer for the former may have a melting point lower than the bonding layer for latter. Therefore, the risk of the heatsink falling off during the process can be reduced, thereby improving the reliability of the semiconductor package structure.

Many variations and/or modifications can be made to embodiments of the disclosure. The semiconductor package structures in accordance with some embodiments of the disclosure can be used to form a three-dimensional (3D) package, a <NUM>. 5D package, a fan-out package, or another suitable package.

Claim 1:
A semiconductor package structure (<NUM>, <NUM>, <NUM>), comprising:
a substrate (<NUM>);
a semiconductor die (<NUM>) disposed over the substrate (<NUM>);
a molding material (<NUM>) surrounding the semiconductor die (<NUM>) and adjoining the sidewalls of the semiconductor die (<NUM>);
a first bonding layer (<NUM>) disposed over the semiconductor die (<NUM>);
a metal layer (<NUM>) disposed between the first bonding layer (<NUM>) and the semiconductor die (<NUM>); and
a heatsink (<NUM>) disposed over the first bonding layer (<NUM>) and bonded onto the semiconductor die (<NUM>) through the first bonding layer (<NUM>) and the metal layer (<NUM>),
characterised by
a thermal interface material (<NUM>) disposed over the molding material (<NUM>) and at least partially surrounding the first bonding layer (<NUM>),
wherein the thermal interface material (<NUM>) connects the molding material (<NUM>) and the heatsink (<NUM>) with the heatsink (<NUM>) being bonded on the thermal interface material (<NUM>);
wherein the first bonding layer (<NUM>) has better thermal conductivity than the thermal interface material (<NUM>);
wherein the thermal interface material (<NUM>) is spaced apart from the first bonding layer (<NUM>) and the metal layer (<NUM>) by a first gap to prevent issues caused by different coefficients of thermal expansion, CTEs, of the thermal interface material (<NUM>), the metal layer (<NUM>) and the first bonding layer (<NUM>); and
wherein the thermal interface material (<NUM>) is cut off by one or more second gaps (<NUM>) configured to release gas generated during the manufacturing process and/or comprises one or more notches configured to release the gas generated during the manufacturing process.