Patent Description:
Two of the primary performance metrics for a HBT for Radio Frequency (RF) applications, are the cut-off frequencies for maximum current gain, Ft, and power gain, Fmax, respectively. As the consumer requirements continue to push higher, parasitic capacitances and resistances are becoming the most critical factors in limiting the HBT performance. In particular, the base-collector (depletion) capacitance, Ccb, is one of the most critical parasitic capacitances, because it affects both Ft and Fmax.

<FIG> illustrates a conventional HBT <NUM>, which comprises a sub-collector region <NUM>, a collector region <NUM> arranged on the sub-collector region <NUM>, a base region <NUM> arranged on the collector region <NUM>, and an emitter region <NUM> arranged on the base region <NUM>. The emitter region <NUM> is narrower than the base region <NUM>, to provide space to form base contacts <NUM> contacting the base region <NUM> next to the emitter region <NUM>. The emitter region <NUM>, and the parts of the base region <NUM> and collector region <NUM> located beneath the emitter region <NUM>, together form the active (transistor) area of the HBT <NUM>.

The parasitic Ccb is indicated in <FIG> beneath the base contacts <NUM>. It could be reduced by eliminating the part of the collector region <NUM>, which is located underneath the base contacts <NUM>, since this part of the collector region <NUM> is not part of the active transistor area. However, the challenge in controlling, and in particular reducing, the value of the parasitic Ccb for an optimized performance of the HBT <NUM> is twofold.

Firstly, scaling the width of the collector region <NUM> would limit the space for the base contacts <NUM>, thereby severely limiting the base resistance, Rbb, which would adversely affect Fmax. Secondly, selectively etching out the unwanted parts of the collector region <NUM> is not only difficult, but also limits the stability of the HBT and thus its yield, especially, in case of a Schottky HBT (SHBT), where this is not a suitable solution in a traditional process flow.

One conventional approach to reduce the parasitic Ccb in a HBT is to deliberately over-etch the collector region <NUM> in a process flow based on blanket wafers. However, this still leads to significant stability and yield issues.

Another conventional approach to reduce the parasitic Ccb in a HBT is the transferred substrate method. In this method, the HBT is fabricated on a blanket substrate up to the formation of the base contacts <NUM>. Afterwards, the HBT is transferred to a host wafer in an upside-down orientation, and is then bonded to the host wafer. Following the removal of a carrier wafer from the top, the collector region can then be patterned to reduce the parasitic Ccb. However, this is a very complex process, and thus also not the ideal solution in terms of yield.

<CIT> discloses a method for forming an HBT, wherein the method comprises bridging an extrinsic base and an intrinsic base by a selective epitaxial growth process.

<CIT> discloses an HBT and a fabrication method for the HBT. In particular, the HBT is provided with an airgap located vertically between an extrinsic base and a collector of the HBT.

In view of the above-mentioned challenges and disadvantages of the conventional approaches, embodiments of the invention aim to provide an improved method to fabricate a HBT and to provide an improved HBT. An objective is, in particular, to provide a HBT having enhanced cut-off frequencies for both maximum current gain and power gain. To this end, the aim is to fabricate a HBT with reduced parasitic base-collector capacitance. However, the stability of the HBT should thereby not be compromised. In addition, a high fabrication yield is of course another important goal.

The objective is achieved by the embodiment of the invention provided in the enclosed independent claim. Advantageous implementations of this embodiment are defined in the dependent claims.

The embodiments of the invention base on fabricating a HBT using the ART technology in ridge structures, in particular using nanoridges.

A first aspect of the invention provides a method for fabricating a HBT, the method comprising: providing a semiconductor support layer; forming an even number of at least four elongated wall structures on the support layer, wherein the wall structures are arranged side-by-side at a regular interval; forming an odd number of at least three semiconductor collector-material ridge structures on the support layer, wherein each ridge structure is formed between two adjacent wall structures; forming a semiconductor base-material layer on a determined ridge structure of the at least three ridge structures, wherein the determined ridge structure is surrounded by the other ridge structures of the at least three ridge structures; forming a semiconductor emitter-material layer on the base-material layer; extending the base-material layer epitaxially so that it coherently covers all the wall structures and all the ridge structures; and selectively removing all the other ridge structures surrounding the determined ridge structure and not removing the determined ridge structure; and filling spaces formed by removing the other ridge structures with an insulator material or air.

The determined ridge structure may be the central ridge structure, i.e. the ridge structure arranged centrally in the odd number of ridge structures arranged next to each other. The formation of the different layers and ridge structures may be implemented by growth or deposition, particularly by epitaxial growth. For example, Metalorganic Vapor Phase Epitaxy (MOVPE), Metalorganic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) may be employed.

The method of the first aspect is able to fabricate an improved HBT. In particular, since the other collector-material ridge structures, other than the determined ridge structure, are removed by the method, the parasitic base-collector (depletion) capacitance, Ccb, is significantly reduced in the final HBT. The HBT has accordingly extremely low, or possibly even zero, Ccb. Accordingly, the cut-off frequencies for both the maximum current gain, Ft, and the power gain, Fmax, are improved for the HBT.

Suitable insulator materials may improve further the stability of the HBT, without adding parasitic Ccb.

In an implementation of the method, the semiconductor collector-material and the semiconductor emitter-material comprise a first-conductivity-type III-V semiconductor material; and the base-material comprises a second-conductivity-type III-V semiconductor material.

The III-V semiconductor material allows a well-controlled formation, in particular growth, of the ridge structures. The ridge structures may be grown using the ART technology, wherein the ridge structures may be nanoridges.

In an implementation of the method, the wall structures comprise a silicon oxide; and/or the semiconductor support layer comprises a silicon-based layer.

In an implementation of the method, the forming of each ridge structure is confined in and guided by a trench formed in the support layer.

In an implementation, the method further comprises forming each ridge structure in a V-groove, wherein the V-groove is disposed in the support layer.

The support layer trench and/or V-groove are characteristic for the ART technology. Defects can be trapped in a lower part of the ridge structures, and the parts of the ridge structures above can be made more or less defect-free.

In an implementation of the method, extending the base-material layer comprises: epitaxially growing base-material on the other ridge structures than the determined ridge structure, until the base-material merges together over the wall structures and with the base-material layer formed on the determined ridge structure.

This provides a simple but efficient way to extend the base-material layer.

In an implementation of the method, removing the other ridge structures comprises: selectively etching the semiconductor collector-material using wet chemistry.

Thus, the material responsible for the parasitic Ccb can be easily but efficiently removed.

In an implementation, the method further comprises, before extending epitaxially the base-material layer: forming an etch-stop layer, in particular a not-intentionally-doped III-V semiconductor etch-stop layer, on each other ridge structure than the determined ridge structure.

In an implementation, the method further comprises, after removing the other ridge structures: removing the etch-stop layers by selectively etching using wet chemistry.

For instance, for forming the etch-stop layer, a thin InGaP re-growth under the extended base-material layer can be performed. The etch-stop layer protects the extended base-material layer from getting etched during the above-described collector-material ridge structure removal. In this way, the base-collector junction can be completely removed under the extended base-material layer, and therefore, Ccb can be reduced to zero.

In an implementation, the method further comprising, before removing the other ridge structures: forming a protective layer on the base-material layer and on the emitter-material layer of the ridge structure, respectively.

This protects the top surface of these layers from the processing that removes the ridge structures, and therefore leads to higher stability and yield.

In an implementation of the method, forming the ridge structures comprises, for each ridge structure: forming a narrower ridge portion to confine all defects on the support layer, and forming a wider defect-free ridge portion on top of the narrower ridge portion, wherein the forming of the wider ridge portion is guided by the corresponding two adjacent wall structures.

This improves the performance of the HBT, since the collector-material ridge structure that remains to from the active transistor area is of high quality. The wall structures act as a template to grow the ridge structures, and benefit the stability of the final HBT.

In an implementation of the method, epitaxially forming the ridge structures comprises, for each ridge structure: forming a sub-collector region on the support layer and forming a collector region on the sub-collector region.

A HBT fabricated according to the above-described method is clearly distinguishable from a HBT formed by another method. For instance, remainders of the collector-material ridge structures may remain in the support layer (e.g. in trenches). Further, the wall structure template that provides stability to the HBT is not present in other HBTs.

The HBT is not claimed but it is useful for understanding the present invention.

In summary, by using e.g. the ART approach to form the ridge structures, the base-material layer can be separately formed around, but outside, the active transistor area. Thus, space is provided to form base contacts to the base-material layer. The template of the wall structures provides the necessary stability to the HBT. Further, the extended base-material can be made independent of the parasitic base-collector junction, which leads to easier scaling control over the base parasitics.

The above described aspects and implementations are explained in the following description of embodiments with respect to the enclosed drawings:.

Figure (<FIG> shows a general method <NUM> according to an embodiment of the invention. The method <NUM> is suitable to fabricate a HBT <NUM>, in particular to fabricate a HBT <NUM> with very low or even zero parasitic base-collector capacitance Ccb.

The method <NUM> comprises the following steps. In a first step, a semiconductor support layer <NUM> or substrate or wafer is provided. In a second step, an even number of at least four elongated wall structures <NUM> are formed on the support layer <NUM>. That is, for example, four, six, eight, ten, or more, wall structures <NUM> are formed. The wall structures <NUM> are arranged side-by-side at a regular interval, i.e., with the same distance between each two adjacent wall structures <NUM>. The wall structures <NUM> may all extend into the same direction and may thus be arranged in parallel. In a third step, an odd number of at least three semiconductor collector-material ridge structures <NUM> is formed on the support layer <NUM>. That is, for example, three, five, seven, nine, or more ridge structures <NUM> are formed. Each ridge structure <NUM> is formed between two adjacent wall structures <NUM>, wherein these adjacent wall structures <NUM> may guide a growth of the ridge structure <NUM>.

In a fourth step, a semiconductor base-material layer <NUM> is formed on a determined ridge structure 13c of the at least three ridge structures <NUM>, or between two determined adjacent wall structures <NUM>, wherein the determined ridge structure 13c is surrounded by the other ridge structures <NUM> of the at least three ridge structures <NUM>. The determined ridge structure 13c may be a central ridge structure (e.g. in case of three ridge structure <NUM> it may be the middle ridge structure), and/or may be formed between the central adjacent pair of the wall structures <NUM> (e.g. in case of four wall structures <NUM> it may be formed between the two inner wall structures <NUM>. The forming of ridge structures <NUM> may be confined in and guided by a trench or groove, e.g. V-groove, formed in the support layer <NUM>, thus, the ridge structures <NUM> can be formed using the ART technology.

In a fifth step, a semiconductor emitter-material layer <NUM> is formed on the base-material layer <NUM>. The first to fifths steps lead to the intermediate structure shown in (a) of <FIG>.

In a sixth step, the base-material layer <NUM> is epitaxially extended, so that it coherently covers all the wall structures <NUM> and all the ridge structures <NUM>. This sixth step leads to the intermediate structure shown in (b) of <FIG>. The sixth step may be performed by epitaxially growing base-material on the ridge structures <NUM>, other than the determined ridge structure 13c, until the base-material merges together over the wall structures <NUM> and with the base-material layer <NUM> formed on the determined ridge structure 13c.

In a seventh step, the other ridge structures <NUM> surrounding the determined ridge structure 13c are selectively removed and the determined ridge structure 13c is not removed. Further, spaces <NUM> that are formed by removing the other ridge structures <NUM> are filled with an insulator material or air. This seventh step leads to the finally fabricated HBT <NUM> that is shown in (c) of <FIG>. The seventh step may be performed by selectively etching the semiconductor collector-material using wet chemistry.

The fabricated HBT <NUM> shown in (c) of <FIG> accordingly comprises the semiconductor support layer <NUM>, and the at least four elongated wall structures <NUM> arranged on the support layer <NUM>, wherein the wall structures <NUM> are arranged side-by-side at a regular interval. Further, the HBT <NUM> comprises the determined semiconductor collector-material ridge structure 13c arranged on the support layer <NUM>, wherein the determined ridge structure 13c is arranged between the two determined adjacent wall structures <NUM> of the at least four wall structures <NUM>. Further, the HBT <NUM> comprises the (extended) semiconductor base-material layer <NUM> arranged on the determined ridge structure 13c and over the wall structures <NUM>, wherein the base-material layer is supported by the wall structures <NUM>, and the semiconductor emitter-material layer <NUM> arranged above the ridge structure 13c on the base-material layer. In the spaces <NUM> formed between the wall structures <NUM> other than the two determined adjacent wall structures <NUM> (formed by removing the collector material ridge structures <NUM> other then the determined ridge structure 13c) are filled with air and/or with an insulator material.

The primary difficulty in controlling the parasitic Ccb of the base-collector region in a HBT is separating the formation (e.g. growth) and the processing of the base-material with respect to the collector-material. The parasitic collector-material needs to be removed, with good control, e.g. control over the extent of etching, without etching or otherwise negatively affecting the stability of the base-material. In, for example, a conventional HBT based on blanket epitaxial growth and processing, this is not only difficult to achieve, but, in case of an SHBT, not a viable solution at all.

However, in the embodiments of the invention, by forming the ridges structures <NUM>, for example using ART based growth of collector-material, the above-mentioned difficulty can be inherently overcome, due to the separation of each ridge structure <NUM> by a wall structure <NUM> (acting as a template barrier). As a result, a single determined ridge structure 13c can be used for the active transistor area, while the nearby ridge structures <NUM> can still be separately processed (here removed). This separation, can lead to zero parasitic Ccb, namely by removing all the collector-material from the ridge structures <NUM> surrounding the determined ridge structure 13c.

The base-material layer <NUM> around the active transistor area can be created by overgrowing the ridge structures <NUM> and wall structures <NUM> to enable a merging of the base-material across different ridge structures <NUM>. The separation between the base-material and collector-material, to ensure selective removal of only the collector-material, may be achieved by growing a (very thin) etch-stop layer <NUM>, particularly from a material known to have a high selectivity towards a solution used to etch.

In this respect, the <FIG> show more details of the method <NUM> according to an embodiment of the invention, which builds on the embodiment of the method <NUM> shown in <FIG>. That is, the method <NUM> is exemplarily shown in the <FIG> with more specific and/or additional steps and features. Same elements in <FIG> and in the <FIG> are labelled with the same reference signs and function likewise. In particular, a HBT <NUM> obtainable by a method according to an embodiment of the invention, as shown in <FIG>, can finally be obtained by using the illustrated process flow.

In <FIG>, the ridge structures <NUM> are formed on the support layer <NUM> and between the wall structures <NUM> provided also on the support layer <NUM>. In particular, they may be grown epitaxially.

Further, an active transistor area is then formed from the determined collector-material ridge structure 13c, the base-material layer <NUM> arranged on the ridge structure 13c, and the emitter-material layer <NUM> arranged on the base-material layer <NUM>. A protective cap <NUM> may further be provided on the base material layer <NUM>. The semiconductor emitter-material may comprise a first-conductivity-type III-V semiconductor material (e.g., including an n-doped InGaP emitter 15a and an n++-doped GaAs emitter cap 15b). The semiconductor base-material may comprise a second-conductivity-type III-V semiconductor material (e.g., p-doped GaAs). The semiconductor collector-material may comprise a first-conductivity-type III-V semiconductor material (e.g., including an n-doped GaAs collector region 23b and an n+-doped GaAs sub-collector region 23a). The active transistor area may be defined by etching, for example, by using a resist with/without SiO<NUM> as a hard mask. In this case, the emitter-material, the base-material and the SiO<NUM> mask may be provided on top of and over all ridge structures <NUM> and all wall structures <NUM>, respectively, and may then be etched until the semiconductor collector-material of the ridge structures <NUM> is reached. Thereby, the pillar-like structure may be formed above the determined ridge structure 13c, as shown in <FIG>. A spacer layer may further be provided to protect this area from further processing.

<FIG> shows further that an etch-stop layer <NUM> (e.g., a thin InGaP layer), may be formed, particularly grown, on the exposed collector-material surface, i.e., on the ridge structures <NUM> and wall structures <NUM>, respectively. The etch-stop layer <NUM> enables a selective etching of the collector-material.

<FIG> shows further that the base-material layer <NUM> can be epitaxially extended, namely by epitaxially growing base-material (e.g., p-doped GaAs) onto the etch-stop layer <NUM>. The base-material may specifically be grown until the base-material merges together over the ridge structures <NUM> other than the determined ridge structure 13c, and merges together with the base-material layer <NUM> that is formed on the determined ridge structure 13c. This enables good contacting to the base-material layer <NUM> arranged on the determined ridge structure 13c. The extended base-material layer <NUM> finally covers coherently all the wall structures <NUM> and all the ridge structures <NUM>. The extended base-material layer <NUM> provides space for and enables good base contacts.

<FIG> shows further that a protective layer <NUM> may be provided, or may be extended from the protective cap <NUM>, to the extended base-material layer <NUM>. For example, by using a resist. Thereafter, the underlying collector-material of the ridge structures <NUM> other than the determined ridge structure 13c can be removed, for example, by wet etching. This is then followed by removal of the etch-stop layer <NUM>, for example, again by wet etching.

Claim 1:
Method (<NUM>) for fabricating a Heterojunction Bipolar Transistor (<NUM>), the method (<NUM>) comprising:
providing a semiconductor support layer (<NUM>);
forming an even number of at least four elongated wall structures (<NUM>) on the support layer (<NUM>), wherein the wall structures (<NUM>) are arranged side-by-side at a regular interval;
forming an odd number of at least three semiconductor collector-material ridge structures (<NUM>) on the support layer (<NUM>), wherein each ridge structure (<NUM>) is formed between two adjacent wall structures (<NUM>);
forming a semiconductor base-material layer (<NUM>) on a determined ridge structure (13c) of the at least three ridge structures (<NUM>),
wherein the determined ridge structure (13c) is between two ridge structures of said at least three ridge structures (<NUM>);
forming a semiconductor emitter-material layer (<NUM>) on the base-material layer (<NUM>);
extending the base-material layer (<NUM>) epitaxially so that it coherently covers all the wall structures (<NUM>) and all the ridge structures (<NUM>);
selectively removing all said ridge structures (<NUM>) except the determined ridge structure (13c); and
filling spaces (<NUM>) formed by removing said ridge structures (<NUM>) with an insulator material or air.