Patent Description:
The present application relates to a semiconductor device structure and a method for making the same.

Dynamic random access memory (DRAM) is a kind of semiconductor memory devices widely used in multiple computer systems. With the development of semiconductor integrated circuit device technologies, the critical dimensions of the dynamic random access memory are getting ever smaller. For example, the active areas (AA) are becoming increasingly smaller, setting very high requirements for corresponding semiconductor manufacturing process. Related technologies are known from <CIT>, <CIT>, and <CIT>.

The invention is defined by the independent claim. According to the present invention, a method for manufacturing a semiconductor device structure is described.

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments. Apparently, the drawings in the following description are only some embodiments of the present application for those of ordinary skill in the art, without creative work, other drawings can be obtained from these drawings.

Reference numerals in the <FIG>. Substrate; <NUM>. First pattern; <NUM>. Second pattern; <NUM>. First trench; <NUM>. Second trench; <NUM>. First dielectric layer; <NUM>. Patterned mask layer; <NUM>. Opening pattern; <NUM>. The second dielectric layer; and <NUM>. The third dielectric layer.

As the width of an active area is very narrow, the ends of such elongated active area are usually damaged during etching with an existing etching process.

In order to better understand the purpose, technical solutions, and technical effects of the present disclosure, the present disclosure will be further explained below in conjunction with the accompanying drawings and embodiments. At the same time, it is stated that the embodiments described below are only used to explain the present disclosure, not to limit the present disclosure.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the disclosure. The terminology used in the specification of the application herein is only for the purpose of describing specific embodiments, and is not intended to limit the application. The term "and/or" as used herein includes any and all combinations of one or more related listed items.

In the case of using the "including", "having", and "including" described in this article, unless a clear qualifying term is used, such as "only", "consisting of", etc., another component or process may be added. Unless mentioned to the contrary, terms in the singular form may include the plural form, and it cannot be understood that the number is one.

In the existing semiconductor process, a one-step etching process is used to dry-etch the substrate to form shallow trenches in the substrate to isolate a number of active regions in the substrate, and then the shallow trenches are filled with an insulating material layer to form shallow trench isolation structures. When using the existing dry etching process to directly etch the substrate to form the active areas, especially as the design dimensions decrease, the ends of such active areas become more and more elongated. Because of high-energy charged particles or groups contained in the etching gas, as the charged particles or groups bombard the substrate to form shallow trenches, they cause damage or destruction to the ends of the active areas, which will have an adverse effect on the performance of the device.

Therefore, based on the above-mentioned problems, there is a need for a method for preparing a semiconductor structure to reduce the damage to the edge of the active region caused by the etching process.

As shown in <FIG>, the present disclosure provides a method for manufacturing a semiconductor structure, which includes:.

The method for preparing the semiconductor structure according to the present disclosure obtain the active areas composed of the second patterns by forming a first dielectric layer as a protective layer on the sidewalls of the first patterns in the substrate, and then segmenting the first patterns to form the second patterns. In this way, when the second patterns constituting the active areas forms from segmenting the first patterns, the sidewalls of the first patterns are always protected by the first dielectric layer, so the ends of the second patterns (which are the ends of the active areas) are not easily damaged during the segmentation process.

Referring to <FIG>, S1 includes the steps of:.

As an example, at S11, the substrate <NUM> can be, but not limited to a silicon substrate, a gallium nitride substrate, a silicon-on-insulator or a silicon carbide substrate, etc. In this embodiment, the substrate <NUM> may be a silicon substrate. A doped well region by applying an ion implantation process may be formed in the substrate <NUM>, and the doping type of the doped well region may be P-type or N-type.

As an example, at S12, the first trenches <NUM> and the first patterns <NUM> form a line array structure. Specifically, each line element of the first patterns <NUM> may be, but is not limited to, a rectangular wall-shaped structure. Herein, the plurality of the first patterns <NUM> are spaced apart, and the first trenches <NUM> are formed between adjacent first patterns <NUM>. Specifically, the plurality of the first patterns <NUM> are arranged in parallel at intervals.

As an example, please refer to <FIG>. In S12, the width d of a first pattern <NUM> along the horizontal direction of the substrate <NUM> can be set according to actual needs. It is worth noting that the width d of the first pattern <NUM> is the length, along the horizontal direction of the substrate <NUM>, of the cross section perpendicular to the extension direction of the first pattern <NUM>. The width d of the first pattern <NUM> is ≤ <NUM>, and more specifically, the width d of the first pattern <NUM> may be <NUM>, <NUM>, or <NUM>, etc. Within the width range, the technical problem described in the present disclosure is more prominent, and the technical solution described in this embodiment has better economic efficiency and beneficial technical effects. The distance L between adjacent first patterns <NUM> may be set according to actual needs. Specifically, the distance L between the adjacent first patterns <NUM> is ≤<NUM>, and more specifically, the distance L between the adjacent first patterns <NUM> may be <NUM>, <NUM>, <NUM>, <NUM> or <NUM> and so on. It should be noted that the distance between the adjacent first patterns <NUM> refers to the center-to-center distance between the adjacent two first patterns <NUM>.

As an example, in S12, a SADP (Self-Aligned Double Patterning) process or a SAQP (Self-Aligned Quadruple Patterning) process can be applied to form the line array structure including the plurality of the first patterns <NUM> and the plurality of first trenches <NUM> on the substrate <NUM>. The SADP process and the SAQP process are known to those skilled in the art and will not be repeated here.

In an example, referring to <FIG>, S2 further includes the following steps.

At S21, the first dielectric layer <NUM> is formed on the sidewalls of the first pattern <NUM> and the bottom surfaces of the first trenches <NUM>; alternatively, the first dielectric layer <NUM> is also formed on the sidewalls of the first pattern <NUM>, the bottom surfaces of the first trenches <NUM>, and the top surfaces of the first pattern <NUM>, so that when the second trenches are subsequently formed in an etching process, the first dielectric layer <NUM> can effectively protect the surfaces of the first pattern <NUM>. In this process, the thickness of the first dielectric layer <NUM> can be set according to actual needs. Specifically, the thickness of the first dielectric layer <NUM> is less than half of the width of a first trench <NUM>. In this process, after the first dielectric layer <NUM> is formed, there is a gap in the first trenches <NUM>, as shown in <FIG>. Preferably, the thickness of the first dielectric layer <NUM> is in the range of <NUM>-<NUM>. Within this range, the first dielectric layer <NUM> can not only provide sufficient protection for the first pattern <NUM>, but also leave enough space for subsequent filling of the third dielectric layer.

At S22, a third dielectric layer <NUM> is formed in the first trenches <NUM> and fills up the first trenches <NUM>. Specifically, the third dielectric layer <NUM> fills up the gaps between the first dielectric layer <NUM> in the first trenches <NUM>, as shown in <FIG>.

More specifically, S22 includes these exemplary steps.

At S221, the third dielectric material layer (not shown) is formed, which fills up the first trenches <NUM> and covers the first dielectric layer <NUM> on the top surfaces of the first pattern <NUM>. Specifically, the third dielectric material layer is deposited by a process of, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a spin coating process; and.

At S222, the third dielectric material layer which covers the top surfaces of the first patterns <NUM> is removed, and the retained third dielectric material layer in the first trenches <NUM> is as the third dielectric layer <NUM>. Specifically, the third dielectric material layer covering the first dielectric layer <NUM> on the top surfaces of the first patterns <NUM> is removed by a process such as, but not limited to, the chemical mechanical polishing process. In another embodiment, the third dielectric material layer is located on the first dielectric layer <NUM> on the top surfaces of the first patterns <NUM>. The third dielectric material layer both on the first dielectric layer <NUM> on the top surface of the first pattern <NUM> and in the first trenches <NUM> has a continuous flat upper surface.

In one example, referring to <FIG>, after forming the first dielectric layer <NUM> and before forming the third dielectric layer <NUM>, the method further includes removing the first dielectric layer <NUM> located at the bottom surfaces of the first trenches <NUM>. In this way, the first dielectric layer <NUM> is discontinuous at the bottoms of the first trenches <NUM> into separated structures, to avoid too many carriers accumulate at the bottoms of the first trenches <NUM>, thereby avoiding leakage current caused by holes or electrons accumulated near the first dielectric layer <NUM> in the transistor substrate. It is worth noting that the first dielectric layer <NUM> at the bottoms of the first trenches <NUM> can be completely removed or partially removed. In this embodiment, all the first dielectric layer <NUM> at the bottoms of the first trenches <NUM> is removed.

In another example, S2 includes the following steps of forming a first dielectric layer <NUM> in the first trenches <NUM>, which fills up the first trenches <NUM>. Specifically, a first dielectric material layer (not shown) is formed in the first trenches <NUM> and the top surfaces of the first pattern <NUM> firstly, and then the first dielectric material layer on the top surfaces of the first patterns <NUM> are removed by a process such as, but not limited to, a chemical mechanical polishing process. The first dielectric material layer remaining in the first trenches <NUM> is the first dielectric layer.

As an example, a physical vapor formation process, a chemical vapor formation process, an atomic layer formation process or a thermal oxidation process can be used to form the first dielectric layer <NUM>. The first dielectric layer <NUM> serves as a protective layer for the first patterns <NUM>. The first dielectric layer <NUM> may include, but is not limited to, a silicon dioxide (SiO<NUM>) layer, a silicon monoxide (SiO) layer, a silicon nitride (SiN) layer, or a silicon oxynitride (SiON) layer, etc. In this embodiment, the first dielectric layer <NUM> can be a silicon dioxide layer.

As an example, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process or a spin coating process may be used to form the third dielectric layer <NUM>, and the material of the third dielectric layer <NUM> is different from the material of the first dielectric layer <NUM>. In this embodiment, the third dielectric layer <NUM> may include, but is not limited to, a silicon dioxide layer. Specifically, the hardness of the first dielectric layer <NUM> is greater than the hardness of the third dielectric layer <NUM>, so that the first dielectric layer <NUM> provides good protection for the first patterns <NUM>. At the same time, under the same etching conditions, the etching rate of the third dielectric layer <NUM> is greater than the etching rate of the first dielectric layer <NUM>, so as to ensure that when the third dielectric layer <NUM> is removed, the first dielectric layer <NUM> on the upper surfaces of the first patterns <NUM> is hardly removed.

Referring to <FIG> in detail, S3 includes the following steps.

At S31, a plurality of second trenches <NUM> are formed on each of the first patterns <NUM> to divide each of the first patterns <NUM> into a plurality of second patterns <NUM>.

As an example, step S31 includes the following steps.

At S311, a mask layer is formed on the upper surface of the substrate <NUM>.

At S312, a patterning process on the mask layer is performed to obtain a patterned mask layer <NUM>. The patterned mask layer <NUM> includes a plurality of openings <NUM> penetrating through the mask layer, and the openings <NUM> define the positions and the shape of the second trenches <NUM> as shown in <FIG>. Optionally, the shape of the openings <NUM> is a circle, an ellipse or a rectangle, etc..

At S313, the first patterns <NUM> are etched based on the patterned mask <NUM> to form the plurality of second trenches <NUM> on the first patterns <NUM> to divide each of the first patterns <NUM> into the plurality of second patterns <NUM>.

At S314, the patterned mask layer <NUM> is removed, as shown in <FIG>.

As an example, in S311, the mask layer <NUM> may include one of or a combination of at least two of an amorphous carbon layer, a silicon oxynitride layer and a silicon oxide layer, but not limited thereto. Specifically, the mask layer may be formed by at least one of the processes of a physical vapor formation process, a chemical a vapor phase formation process, an atomic layer formation process and a spin coating process.

As an example, in S312, the mask layer <NUM> may be patterned by a photolithography process to obtain the pattern mask layer <NUM>. The dimension of the openings <NUM> is larger than the width of each first pattern <NUM>. Specifically, the dimension of the openings <NUM> may be the size along the width of the first patterns <NUM>, or the maximum size along a horizontal direction of the substrate. For example, the width of the first patterns <NUM> is less than or equal to <NUM>, the size of the second trenches <NUM> is less than or equal to <NUM>, the thickness of the first dielectric layer <NUM> ranges from <NUM> to <NUM>, and the size of the openings <NUM> is less than <NUM>. The opening size being larger than the width of the first patterns <NUM> is beneficial to increase the process window and improves the product yield. It should be noted that the size of the second trenches <NUM> may be the size along the width direction of the first patterns <NUM>, or the maximum size along a horizontal direction of the substrate.

As an example, in S313, a dry etching process may be used to pattern the first patterns <NUM> with the patterned mask layer <NUM>. In another example, the second trenches <NUM> segment the first patterns <NUM> only, but do not cut the first dielectric layer <NUM> which covers the sidewalls of the first patterns <NUM>. Specifically, utilizing the pattern of the openings <NUM>, the first patterns <NUM> are etched with an etching process that has an etch selection ratio of greater than <NUM> between the first patterns <NUM> and the first dielectric layer <NUM> to form the second trenches <NUM>, and second patterns <NUM> are formed between the first trenches <NUM> and the second trenches <NUM>. The first dielectric layer <NUM> on the sidewalls of the second patterns adjacent to the second trenches <NUM> is not etched. With the etching process having the high etch selection ratio, only the first patterns <NUM> are etched and segmented, and the whole first dielectric layer <NUM> is retained intact, which ensures better end shapes of the second patterns <NUM>, thereby improving the device performance.

As an example, in S314, an etching process or a chemical mechanical polishing process may be used to remove the patterned mask layer <NUM>.

By referring to <FIG>, according to one of the embodiments, the extending direction of the first patterns <NUM> is obliquely intersected with the arrangement direction of the second trenches <NUM> with the shortest adjacent distance in each of the columns. Specifically, the second trenches <NUM> on a same first pattern <NUM> are arranged at intervals, and the second trenches <NUM> on the adjacent first patterns <NUM> are arranged in a staggered way. More specifically, the second trenches <NUM> located in adjacent odd-numbered columns of the first pattern <NUM> are arranged in a staggered way with the second trenches <NUM> located in the nearby even-numbered columns of the first pattern <NUM>, the second trenches <NUM> located in the adjacent odd-numbered columns of the first pattern <NUM> are arranged in one-to-one correspondence, and the second trenches <NUM> in adjacent even-numbered columns of the first pattern <NUM> are arranged in a one-to-one correspondence. Specifically, the first patterns are the active areas of the storage device, and the above arrangement is beneficial to maximize the device storage density.

According to another embodiment, by referring to <FIG> and <FIG>, the depth H1 of the first trenches <NUM> may be greater than or equal to the depth H2 of the second trenches <NUM>. In this embodiment, the depth H1 of the first trenches <NUM> may be greater than the depth H2 of the second trenches <NUM>. As the depth H1 of the first trenches <NUM> is greater than the depth H2 of the second trenches <NUM>, the isolation effect is better, and thus the mutual influence between the adjacent active areas is avoid. Specifically, the first trenches <NUM> can be etched with the above process, and the second trenches <NUM> can be etched later, that is, different depths in H1 of the first trenches <NUM> and H2 of the second trenches <NUM> are achieved by twice etching.

According to another embodiment, in <FIG> and <FIG>, the width D1 of the first trenches <NUM> is narrower than or equal to the width D2 of the second trenches <NUM>. In this embodiment, the width D1 of the first trenches <NUM> is less than the width D2 of the second trenches <NUM>. It is worth noting that the width of the second trenches <NUM> refers to the dimension along the extending direction of the first patterns <NUM>. The maximum dimension of the second trenches <NUM> in a horizontal direction of the substrate <NUM> is less than <NUM>.

In an example, after the second pattern <NUM> is formed, S32 is further included, which includes filling a second dielectric layer <NUM> in the second trenches <NUM>, as shown in <FIG>.

As an example, the second dielectric layer <NUM> can be formed by a process of, but not limited to, a physical vapor formation process, a chemical vapor formation process, or an atomic layer formation process. The material of the second dielectric layer <NUM> is the same the material of the first dielectric layer <NUM>, or it is different from that of the first dielectric layer <NUM>. The material of the second dielectric layer <NUM> and the material of the third dielectric layer <NUM> are different. When the materials of the second dielectric layer <NUM> and the first dielectric layer <NUM> are different, the second dielectric layer <NUM> may include, but not limited to, a silicon oxide layer or a silicon nitride (SiN) layer. When the material of the second dielectric layer <NUM> is different from the material of the third dielectric layer <NUM>, the viscosity of the second dielectric layer <NUM> is lower than that of the third dielectric layer <NUM>. The first trenches <NUM> and the second trenches <NUM> are respectively filled with the third dielectric layer <NUM> and the second dielectric layer <NUM> which have different viscosities, ensuring the filling quality and the isolation performance as well.

It should be noted that, according to other embodiments, with respect to the solution in which the first dielectric layer <NUM> fills up the first trenches <NUM>, before filling the second trenches <NUM> with the second dielectric layer <NUM>, it may also include the step of removing the first dielectric layer <NUM> from the first trenches <NUM>, and in this case, while filling the second dielectric layer <NUM> into the second trenches <NUM>, the first trenches <NUM> are filled with the second dielectric layer <NUM>. With respect to the solution in which the first trenches <NUM> is filled up with the third dielectric layer <NUM>, before filling the second dielectric layer <NUM> into the second trenches <NUM>, it may also include a step of removing the third dielectric layer <NUM> from the first trenches <NUM>, and in this case, when filling the second dielectric layer <NUM> into the second trenches <NUM>, the first trenches <NUM> are filled with the second dielectric layer <NUM>.

The disclosure is simple in manufacture processes and has a broad prospect for applications in the semiconductor manufacturing field, and it effectively overcomes the shortcomings in the related art and having a high industrial application value.

The exemplary embodiments of the present disclosure also provide a semiconductor structure, not part of the present invention. The semiconductor structure may be formed by the method described in the above embodiments. Other methods may also be used.

The semiconductor structure includes: a substrate <NUM>; a number of first trenches <NUM> and a number of second trenches <NUM> both located in the substrate <NUM>; second patterns <NUM> located between the first trenches <NUM> and the second trenches <NUM>; a first dielectric layer <NUM>, covering at least the sidewalls of the second pattern <NUM> adjacent to the first trenches <NUM>; and a second dielectric layer <NUM>, filling the second trenches <NUM>.

In one of the examples, the substrate <NUM> includes, but is not limited to, a silicon substrate, a gallium nitride substrate, a silicon-on-insulator substrate or a silicon carbide substrate, etc. In this embodiment, the substrate <NUM> may be a silicon substrate. A doped well region formed with an ion implantation process may be formed in the substrate <NUM>, and the dopant type of the doped well region may be either P-type or N-type.

In one of the examples, the depth H1 of the first trenches <NUM> may be greater than or equal to the depth H2 of the second trenches <NUM>. In this embodiment, the depth H1 of the first trenches <NUM> being greater than the depth H2 of the second trenches <NUM> makes the isolation effect better, so to avoid mutual influence between adjacent active areas.

In one of the examples, the material of the second dielectric layer <NUM> is the same as the material of the first dielectric layer <NUM>, or is different from the material of the first dielectric layer <NUM>. When the materials of the second dielectric layer <NUM> and the first dielectric layer <NUM> are different, the second dielectric layer <NUM> may include, but is not limited to, a silicon oxide layer or a silicon nitride (SiN) layer.

The width of the second patterns <NUM> is less than or equal to <NUM>. It is worth noting that the width of the second patterns <NUM> is the length, along the horizontal direction of the substrate <NUM>, of the cross section perpendicular to the extension direction of the second patterns <NUM>. Specifically, the width of the second patterns <NUM> may be <NUM>, <NUM>, or <NUM>, etc. Within the width range, the technical problem described in the present disclosure is more prominent, and the technical solution described in this embodiment will be more economical and more beneficial. The distance between adjacent second patterns <NUM> can be set according to actual needs.

In another embodiment, the sidewalls of the second pattern <NUM> adjacent to the second trenches <NUM> are not covered with the first dielectric layer <NUM>.

The distance between two adjacent second pattern <NUM> is ≤ <NUM>. More specifically, the distance between the adjacent second pattern <NUM> may be <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>, etc., but in other embodiments, the distance between two adjacent second patterns <NUM> is not limited to the above-mentioned values. It should be noted that the distance between two adjacent ones of the second patterns <NUM> mentioned herein refers to the center-to-center distance between two adjacent second patterns <NUM>.

The maximum dimension of one of the second trenches <NUM> in a horizontal direction of the substrate <NUM> is less than <NUM>.

The semiconductor structure further includes a third dielectric layer <NUM>, and the third dielectric layer <NUM> fills in the first trenches <NUM>.

The material of the third dielectric layer <NUM> is different from the material of the first dielectric layer <NUM>. In this embodiment, the third dielectric layer <NUM> may include, but is not limited to, a silicon dioxide layer.

In one example, the material of the second dielectric layer <NUM> and the material of the third dielectric layer <NUM> are different. When the material of the second dielectric layer <NUM> is different from the material of the third dielectric layer <NUM>, the viscosity of the second dielectric layer <NUM> is lower than that of the third dielectric layer <NUM>. The first trench <NUM> and the second trench <NUM> are respectively filled with the third dielectric layer <NUM> and the second dielectric layer <NUM> which have different viscosities, thereby ensuring both the filling effect and the isolation performance. Specifically, the width of the first patterns <NUM> is less than or equal to <NUM>, the distance between adjacent first patterns <NUM> is less than or equal to <NUM>, the size of the second trenches <NUM> is less than or equal to <NUM>, and the thickness of the first dielectric layer <NUM> ranges from <NUM> to <NUM>. The spin coating process may be used to fill the first trenches <NUM> and the second trenches <NUM>. Since the filling difficulty of the second trenches <NUM> is higher than that of the first trenches <NUM>, the second trenches <NUM> are filled with the second dielectric layer <NUM> with a low viscosity to obtain a better filling effect, and the first trenches <NUM> can be filled with a high-viscosity third dielectric layer <NUM> to obtain a better isolation performance. It should be noted that the size of the second trenches <NUM> may be the size along the width direction of the first patterns <NUM>, or the maximum size along the horizontal direction of the substrate.

In another example, the first dielectric layer <NUM> is also present between the adjacent second patterns <NUM> and is integrated with the first dielectric layer <NUM> on the sidewalls of the second patterns <NUM>. Specifically, the second trenches <NUM> only segment the first patterns <NUM>, and the first dielectric layer <NUM> covering the sidewalls of the first patterns <NUM> is not segmented. By utilizing the openings <NUM>, an etching process with an etch selection ratio greater than <NUM> between the first patterns <NUM> and the first dielectric layer <NUM>, the first patterns <NUM> are patterned to form the second trenches <NUM>. The second patterns <NUM> are formed between the first trenches <NUM> and the second trenches <NUM> , and the first dielectric layer <NUM> on the sidewalls of the second patterns <NUM> adjacent to the second trenches <NUM> is not segmented by this etching. In the process with the high etch selection ratio, only the first patterns <NUM> are segmented and the first dielectric layer <NUM> is retained intact, so the end shape of the resultant second patterns <NUM> will be better ensured, thereby improving the device performance.

It should be understood that, although the steps disclosed in the flowcharts of the drawings are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order as indicated. Unless there is a clear description in this disclosure, no strict order for executing these steps, so these steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, instead they may be executed at different times, and the order of execution of these steps or stages is not necessarily in sequence. They may be performed in turn or alternately with other steps, or at least a part of steps or stages of said other steps.

The technical features of the above-mentioned embodiments can be combined in any ways necessary. In order to describe the disclosure concisely, not all possible combinations of the various technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in combining these technical features, all should be considered as within the scope of this specification.

Claim 1:
A method for manufacturing a semiconductor structure, comprising:
(S1) providing a substrate (<NUM>), wherein the substrate (<NUM>) comprises a plurality of first trenches (<NUM>), and first patterns (<NUM>) are formed by a single material between adjacent ones of the plurality of first trenches (<NUM>),
(S21) forming a first dielectric layer (<NUM>) on sidewalls of the first patterns (<NUM>) and bottoms of the first trenches (<NUM>);
(S22) forming a third dielectric layer (<NUM>) in the first trenches (<NUM>), wherein the third dielectric layer (<NUM>) fills up the first trenches (<NUM>), a hardness of the first dielectric layer (<NUM>) is greater than a hardness of the third dielectric layer (<NUM>);
(S31) forming a plurality of second trenches (<NUM>) in each of the first patterns (<NUM>) to divide each of the first patterns (<NUM>) into a plurality of second patterns (<NUM>) by etching part of the first patterns (<NUM>) with an etch selection ratio of greater than <NUM> between the first patterns (<NUM>) and the first dielectric layer (<NUM>) to form a plurality of active areas constituted by the plurality of second patterns (<NUM>), wherein the first dielectric layer (<NUM>) is retained intact between adjacent second patterns (<NUM>); and
(S32) filling a second dielectric layer (<NUM>) in the second trenches (<NUM>),
wherein a width of the first patterns (<NUM>) is ≤ <NUM>, a distance between the adjacent ones of the first patterns (<NUM>) is ≤ <NUM>, a maximum dimension of the second trenches (<NUM>) along a horizontal direction of the substrate (<NUM>) is less than <NUM>.