Patent Description:
Universal Serial Bus (USB) is a standard of an interface, which has been developed for enhancing the expandability of a peripheral device (USB device/function device) connected to a USB host such as a personal computer. USB is a serial interface standard which allows communications between a host device and various USB-compliant devices to be performed via a common bus line.

X defines two modes having different data transfer rates, i.e. low-speed mode (LS) of <NUM> Mbps and full-speed mode (FS) of <NUM> Mbps. The LS and FS mode may also be used in the standard termed USB <NUM>, USB <NUM>, etc..

Under USB standard, in principle, one USB host device can be connected with up to <NUM> devices via a common bus line which includes USB data lines and power supply lines. In order to decode the data transmission on the USB data lines, usually a field programmable gate array (FPGA) or a microcontroller/microprocessor may be used to complete USB clock synchronization and USB signal analysis.

There remains a need for a system with low cost for decoding the data communication under universal serial bus standard.

<CIT>, <CIT> and XP011375064 disclose USB data receiver performing NRZI decoding before bit unstuffing implemented on programmable hardware logic like ASICs or FPGAs or using state machines.

According to one aspect of the application, a device adapted to implement a state machine which defines a plurality of predetermined states and a plurality of predetermined events, for decoding USB data communicated over a universal serial bus (USB), the device comprising:.

In one or more embodiments, a clock rate of the device clock is at least <NUM> times the data transferring rate over the USB.

In one or more embodiments, a clock rate of the device clock is no more than <NUM> times of the data transferring rate over the USB.

In one or more embodiments, the device further comprises an indicator output terminal configured to output an indication signal indicative that the bus state of the USB is an end of package or not.

In one or more embodiments, the control circuity further comprises a counter unit (<NUM>) including first and second counters that are configurable to operate as a unified <NUM>-bit counter or as two separate <NUM>-bit counters.

In one or more embodiments, the control circuity further comprises a control logic circuitry connected to the counter unit to provide control signals for the counters of the counter unit, wherein the control logic circuitry is also connected to the event generator to receive event signals therefrom, and wherein the control logic circuit is configured to use the control signals to reset the counter after an event is triggered by the event generator.

In one or more embodiments, the control circuity further comprises a match register configured to load expected match value.

In one or more embodiments, the control circuity further comprises a match logic module configured to generate a match logic in response to the count values from the counter unit being equals to the match values from the match register, and wherein the one of the predetermined events is triggered only when the match logic is generated.

In one or more embodiments, the device further comprises an interrupt module connected to the event generator, wherein the interrupt module is configured to generate an interrupt signal in response to receiving a predetermined one of the event signals from the event generator.

The application as summarized above is further illustrated by the following embodiments and drawings. The drawings are for facilitating an understanding of the application and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying drawings, in which like reference numerals have been used to designate like elements, and in which:.

USB does not transmit data directly on the USB data lines. It converts the data into NRZI encoded data with Not-Return-to-Zero-Inverse (NRZI) encoding, and then the NRZI encoded data are transmitted on the USB data lines. Data capture by using a conventional low cost microcontroller may therefore be challenging. The NRZI data comprises J state and K state.

<FIG> illustrates an example of a data encoding for USB transmission, using bit-stuffing and subsequent NRZI encoding. In NRZI encoding, a "<NUM>" is represented by no change in level and a "<NUM>" is represented by a change in level. A string of "<NUM>" thus causes the NRZI data to toggle each bit time. "<NUM>"s may also be referred to as "one"s. "<NUM>"s may also be referred to as "zero"s.

A string of raw data "<NUM>"s as shown throughout most of the "Packet-Data" interval in the upper waveform, at <NUM>, may cause long periods with no transitions in the encoded data. In order to ensure adequate signal transitions, A "<NUM>" is inserted after every six consecutive "<NUM>", in the raw data, as shown by the middle waveform, at <NUM>. This process is known as "bit stuffing" and the inserted "<NUM>" is known as a "stuffed-bit". The stuffed data packet is then converted to NRZI, with each "<NUM>" causing a data transition, and each "<NUM>" causing no transition, as shown by the lower waveform, at <NUM>. One difficulty in decoding the data on the USB data lines is how to detect the stuffed-bit. In addition, in order to decode the USB data lines, it is also necessary to ensure clock synchronization.

<FIG> is a schematic block diagram of a system <NUM> for decoding the data communication under universal serial bus (USB) standard. System <NUM> may comprise a USB host <NUM>, a USB device <NUM> (also sometimes referred to as a "USB function", or "USB peripheral device"), USB data lines <NUM>, a device <NUM>, a USB transceiver <NUM>, a co-processor <NUM>, and a SPI interface <NUM>. The USB device <NUM> may be coupled to the USB host <NUM> through USB cables. The USB includes two data lines D+/D- that carry data and two lines VBUS/GND that carry power. The supply voltage on the line VBUS may be +5V. The USB device <NUM> is configured to communicate data with the USB host <NUM> over data lines <NUM>. In some embodiments, the USB device <NUM> may receive data from the USB host <NUM>. In some other embodiments, the USB device <NUM> may transmit data to the USB host <NUM> based on the request of the USB host <NUM>.

The system <NUM> uses bit stuffing and NRZI encoding system (not shown) in physical layer of the USB host <NUM> to encode the data for USB transmission. The system <NUM> may be used for LS and FS mode which may be used in the standard of USB <NUM>. x, <NUM>, <NUM> etc..

The device <NUM> may be coupled to one of the USB host <NUM> and the USB device <NUM>. In some embodiments, the device <NUM> may be on the host side and coupled to the USB host <NUM> through cables. In some embodiments, the device <NUM> may be on the function side and coupled to the USB device <NUM> through cables. In some other embodiments, the device <NUM> may be located separately from the host side and the function side and coupled to one of the USB host <NUM> and the USB device <NUM> through cables.

The device <NUM> may be a peripheral which is adapted to implement a state machine with one <NUM> bit counter. In some embodiments, the device <NUM> is adapted to implement a state machine with two <NUM> bit counters. Each of the <NUM> bit counters may be used for some parts of the state machine. The state machine defines a plurality of predetermined states and a plurality of predetermined events, for decoding USB data communicated over a universal serial bus (USB). The device <NUM> is configured to receive the data over the USB data lines <NUM> and then synchronize the data, provide decoded stuffed-bit stripped synchronized data by using the predetermined states and events.

The device <NUM> comprises pair of data input terminals <NUM>, <NUM> for receiving the USB encoded data with bit stuffing which is encoded from the raw data. Then the device <NUM> synchronizes the data and processes the synchronized data based on the predetermined events and states. The device <NUM> also comprises a clock input terminal (not shown) for receiving a system clock from a clock source. Then the device <NUM> identifies the stuffed-bits and decode synchronized data to raw data "<NUM>" and raw data "<NUM>". Some of the predetermined events comprise identifying a stuffed-bit in the synchronized data. Some of the predetermined events comprise stripping the identified stuffed-bit from synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data. A combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data, and a further of the predetermined events comprises outputting decoded stuffed-bit stripped synchronized data and toggling the output clock at the output terminals.

The USB data lines <NUM> include two data lines D+/D- that carry the encoded data. The synchronized data from each of the data lines D+ and D- have high level and low level. And there are rising edges from the low level to the high level and falling edges from the high level to the low level. The device <NUM> checks if the USB bus state is "end of package" (EOP) which means the synchronized data are not valid. If the USB bus state is not EOP, the synchronized data "<NUM>" means the state of the data on one of the data lines D+ and D- does not change, and the synchronized data "<NUM>" means the state of the data on the data lines D+ and D- changes. When the synchronized data from the D+ have one of the rising edge and the falling edge, the synchronized data from the D- have corresponding one of the falling edge and the rising edge. Then the device <NUM> may use one of the data lines D+ and D- to decode the synchronized data. The device <NUM> decodes the synchronized data "<NUM>" when the data on the data line D- and data line D+ does not have a rising edge or a falling edge. The device <NUM> decodes the synchronized data "<NUM>" when the data on the data lines D+ D- has one of the rising edge and the falling edge. The device <NUM> identifies a stuffed-bit when the synchronized data "<NUM>" is received after six synchronized data "<NUM>" received consecutively. The stuffed-bit will not be output by the device <NUM> and the output clock will not be toggled. The device <NUM> outputs the decoded stuffed-bit stripped synchronized data when the output clock is toggled.

The details of the device <NUM> will be described below in combination of <FIG>.

<FIG> shows, at block level, an embodiment of the device <NUM> adapted to implement a state machine which defines a plurality of predetermined states and a plurality of predetermined events, for decoding USB data communicated over a universal serial bus (USB). Referring to <FIG>, the device <NUM> comprises a pair of data input terminals and a clock input terminal, a clock processor <NUM>, an event generator <NUM>, a state logic circuitry <NUM>, output terminals <NUM>, interrupts module <NUM>, counter unit <NUM>, prescaler <NUM>, match register <NUM>, match logic module <NUM> and control logic circuitry <NUM>. The counter unit <NUM>, prescaler <NUM>, match register <NUM>, match logic module <NUM> and control logic circuitry <NUM> are included in a control circuity <NUM> which is coupled to the event generator <NUM> and configured to provide control information to the event generator <NUM>. Although the components of the device <NUM> are illustrated in <FIG> as being separate modules, these modules are typically integrated into one circuit.

The pair of data input terminals are used for receiving the USB data, and the clock input terminal is used for receiving a system clock. The clock processor <NUM> is coupled to the pair of data input terminals and the clock input terminal, and is configured to output synchronized data for the event generator <NUM> and a device clock (SCT clock) based on the system clock for various components of the device <NUM>. The device also outputs a prescaler clock for the prescaler <NUM>. The system clock may be generated by a clock generator. In some embodiments, the device clock and the prescaler clock are equivalent to the system clock. However, in other embodiment, one or both of the device clock and the prescaler clock may be differ from the system clock with respect to clock rate. The clock rate is also referred to as the clock frequency. For the full-speed mode (FS), the data transferring rate over the USB is typically 12Mbps. In some embodiments, the clock rate of the device clock is no more than <NUM> times of the data transferring rate over the USB. The clock rate of the device clock may be one of <NUM>, <NUM>, <NUM> and <NUM>. Then the clock rate of the system clock of device <NUM> may be 6times, 8times, 10times or <NUM> times of the data transferring rate. By this way, the device <NUM> may have enough time to decode the data package on the USB.

The prescaler <NUM> is configured to produce one or more clock signals for the counter unit <NUM> using the prescaler clock from the clock processor <NUM>. The control logic circuitry <NUM> is configured to produce control signals to control at least one counter of the counter unit <NUM>. The control signals determine when the counter is incremented, cleared and loaded. The control logic circuitry <NUM> includes an input to receive event signals generated by the event generator <NUM>. The control logic circuitry is configured to provide corresponding control signals to the counter unit <NUM> in response to different event signals, i.e., when certain events are triggered. The control logic circuit <NUM> is configured to use the control signals to reset the counters of the counter unit <NUM> after an event is triggered by the event generator <NUM>.

The counter unit <NUM> is configured to produce one or more running count values. As mentioned above, the counter unit includes one or more counters. In an embodiment, the counter unit <NUM> includes first and second counters that are configurable to operate as a unified <NUM>-bit counter or as two separate <NUM>-bit counters. In this embodiment, each counter of the counter unit <NUM> is connected to prescaler <NUM> to receive the device clock. Each counter is also connected to the control logic circuitry <NUM> to receive the control signals from the control logic circuitry <NUM>. Thus, each counter maintains a count value using the device clock from the prescaler <NUM> and using the control signals from the control logic circuitry <NUM>.

The match register <NUM> is configured to load expected match value. In some embodiments, the expected match value may be thirteen when the clock rate of the system clock of device <NUM> is <NUM> times of the data transferring rate, which means the USB data may be received at the time of the thirteenth clock cycle comes.

The match logic module <NUM> is configured to generate a match logic in response to the count values from the counter unit <NUM> being equal to the expected match values from the match register, and wherein the one of the predetermined events is triggered only when the match logic is generated. Thus, each data from the USB could be captured for every twelve counts when the clock rate of the system clock of device <NUM> is twelve times of the data transferring rate.

The event generator <NUM> is coupled to the clock processor <NUM> to receive the synchronized data and the device clock. The state logic circuitry <NUM> is coupled to an output of the event generator <NUM>. The state logic circuitry <NUM> is configured to store a present state, being a one of the predetermined states. The output terminals <NUM> are coupled to the event generator <NUM> and comprise a decoded-data output terminal and a clock output terminal. The event generator <NUM> is configured to trigger respective ones of the predetermined events, in response to respective combinations of values of the synchronized data, the device clock, the control information and the present state. Referring to <FIG>, <FIG> and <FIG>, a one of the predetermined events comprises identifying a stuffed-bit in the synchronized data. Another of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data, such as data "<NUM>" and data "<NUM>". A combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data. And a further of the predetermined events comprises outputting, at the output terminals, the decoded stuffed-bit stripped synchronized data and toggling the output clock.

In some embodiments, the output terminals <NUM> are configured to output an indication signal indicative whether the bus state of the USB is an end of package (EOP) or not.

In some embodiments, an interrupt module <NUM> is configured to generate an interrupt signal in response to receiving a predetermined one of the event signals from the event generator.

Thus, present application uses a device adapted to implement a state machine with predetermined states and events to decode the data communication on the USB bus. The device may be implemented with a low cost MCU which may reduce the cost and may be easily integrated into other embedded products such as a secure bus monitor.

Referring back to <FIG>, an apparatus <NUM> is used for decoding USB data communicated over the USB data lines. The apparatus <NUM> comprises the device <NUM> which is also shown as the device <NUM> in <FIG>. In some embodiments, the apparatus may also comprise a co-processor <NUM> and a serial peripheral interface (SPI) interface <NUM>.

The co-processor <NUM> comprises input terminals <NUM>, <NUM>, and <NUM> and at least one output <NUM> terminal. The input terminals <NUM>, <NUM> of the co-processor <NUM> are coupled to the output terminals of the device <NUM> and configured to receive the output clock (at input terminal <NUM>) and the decoded stuffed-bit stripped synchronized data (at input terminal <NUM>) from the device <NUM>. The co-processor <NUM> is configured to convert the decoded stuffed-bit stripped synchronized data and output clock into serial peripheral interface (SPI) signals. In some embodiments, In some embodiments, the device <NUM> also outputs an indication signal as shown by SCT_CS to the input <NUM> of the co-processor <NUM>. The indication signal SCT_CS is used for indicating whether the bus state of the USB is an end of package (EOP) or not. Then the co-processor <NUM> is configured to convert the indication signal to a SPI indication signal as shown as SPI_CS. The co-processor <NUM> may transmit the SPI signals to the SPI interface <NUM> by internal bus. In embodiments which are implemented on or together with an ARM Cortex M architecture, the internal bus may include AHB bus and APB bridge. In some other embodiments, the co-processor <NUM> may convert the raw data signals in other ways to meet different requirement.

The serial peripheral interface (SPI) interface <NUM> is coupled to the output terminals <NUM> of the processor. The apparatus <NUM> may be configured to output the SPI indication signal (SPI_CS), SPI data signal (SPI_MOSI) and SPI clock signal (SPI_CLK) via the SPI interface <NUM>.

In some embodiments, a USB transceiver <NUM> is coupled between the USB host <NUM> and the device <NUM> for improving the signal quality and signal integrity. The USB data lines D+ and D- carry analog data. The transceiver <NUM> is used to transfer the analog data to digital data. In some other embodiments, the device <NUM> may also receive the data from data lines directly without the transceiver <NUM> because the analog data from the data lines are similar to digital data. The USB transceiver <NUM> may be implemented using a transceiver which is well-known in the art.

A non-transitory computer-readable medium stores a program to execute processing for decoding USB data. The USB data is communicated over a universal serial bus (USB) and input to a pair of data input terminals, and a system clock is put to the clock input terminal. The processing comprises generating synchronized data and a device clock based on a system clock by a clock processor <NUM>; providing the synchronized data to an event generator <NUM>; providing control information to the event generator, wherein the control information is generated by a control circuity <NUM>; providing a present state stored by a state logic circuitry <NUM> to the event generator; providing a plurality of predetermined events to a plurality of registers of the event generator; triggering respective ones of the predetermined events is in response to respective combinations of values of the synchronized data, the device clock, the control information and the present state. A one of the predetermined events comprises identifying a stuffed-bit in the synchronized data, another of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, a combination of the predetermined events comprises decoding stuffed-bit stripped synchronized data, and a further of the predetermined events comprises outputting, at the output terminals, decoded stuffed-bit stripped synchronized data and toggling the output clock. In some embodiments, a clock rate of the device clock is no more than <NUM> times of the data transferring rate over the USB.

In some embodiments, the processing provides control information to the event generator includes at least one of selecting a rising edge of the synchronized data as an ingredient of the event, and selecting a falling edge of the synchronized data as an ingredient of the event.

In some embodiments, the processing provides control information includes generating count values at counters; loading match values to match registers; and comparing the count values from the counters with the values stored in the match registers to produce a match result.

In some embodiments, the processing generates count values includes generating two counter values that represent a unified <NUM>-bit count values or two separate <NUM>-bit count values.

In some embodiments, the processing further comprises generating an interrupt signal in response to a predetermined event signal from the event generator.

<FIG> illustrates a flow chart <NUM> of the operation of a device <NUM> adapted to implement a state machine in accordance with an embodiment of the present application. The device <NUM> receives the data on the USB data lines and processes the data by using predetermined states and events of the state machine. The device <NUM> processes the data may comprise: handling bus state; checking the data on any of the USB data lines; detecting stuffed-bit, raw data <NUM> and raw data <NUM>. The device <NUM> may output indication signals, raw data signals and clock signals. The device <NUM> may output data <NUM> when the data on the data line D- or D+ does not have rising edge or falling edge. And the device may check if the data is a stuffed-bit when the data on the data line D- or D+ has a rising edge or a falling edge, and the device outputs data <NUM> if the data is not a stuffed-bit, or the device ignores the stuffed-bit if the stuffed-bit is detected.

In some embodiments, the operation of device <NUM> decode the data with NRZI encoding may include the following steps.

S401 is a step for initializing output signals of the device <NUM>. For example, the indication signal SCT_CS is set to zero. Both of the clock signal SCT_CLOCK and the raw data signal SCT_DATA are set to one.

S402 is a step for detecting or decoding the data received on the USB data lines D+ and D-. If a data packet has been supplied to the device, the operation goes to S403.

S403 is a step for handling the bus state. If the bus state of the data signal lines is on an "SE0" state which means both of the data signal line D+ and the data signal line D- are at low level and the bus state of the USB is an end of package (EOP), then goes to S404. If the bus state is not an EOP, the operation goes to S406.

S404 is a step for processing the end of packet (EOP). After processing the EOP, goes to S405.

S405 is a step for setting the indication signal output by device <NUM> to zero. The operation returns to S402.

S406 is a step for processing data on the USB data lines. And the operation goes to S407.

S407 is a step for checking whether USB D- has rising or falling edge. If the USB D-does not have rising or falling edge, the operation goes to S408. If the USB D- has rising or falling edge, the operation goes to S410. In some embodiments, the step S407 may also be used for judging whether USB D+ has rising or falling edge.

S408 is a step for telling the data on the USB data lines is not changed and the raw data is one. The operation goes to S409.

S409 is a step for setting the raw data signal SCT_DATA to one, toggling the clock signal SCT_CLOCK and setting the indication signal SCT_CS to one.

S410 is a step for checking whether a bit stuffing is inserted or not. If six ones have been received consecutively, the next data zero will be treated as a stuffed-bit and the operation goes to S411. Otherwise, the operation goes to S412.

S411 is a step for ignoring the stuffed-bit. And the operation returns to S402.

S412 is a step for telling the data zero received as the raw data zero. The operation goes to S413.

S413 is for setting the raw data signal SCT_DATA to zero, toggling the clock signal SCT_CLOCK and setting the indication signal SCT_CS to one. And the operation returns to S402.

The device <NUM> operates in this manner, making it possible to decoding the data with NRZI encoding on the USB and detecting the stuffed-bit and realizing clock synchronization.

The device <NUM> may be adapted to implement a low state machine ("L State Machine") part and a high state machine ("H State Machine") part. Both the low state machine and the high state machine are implemented with hardware. <FIG> and <FIG> illustrate a low state machine part and <FIG> illustrates a high state machine part respectively in accordance with an embodiment of the present application. In some embodiments, the state machine may only comprise one part to decode the data and detect the stuffed-bit. It might not be split into a high state machine part and a low state machine part.

The clock source of state machine may be at <NUM> and the USB data communication may be under full speed mode with the data transferring rate over the USB of 12Mbps. The low state machine part may include first counter ("L counter") and the high state machine part may include second counter ("H counter"). The first counter may be known as using the first half bits of a <NUM>-bit counter. The higher counter may be known as using the second half bits of the <NUM>-bit counter.

Some of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data. As shown in <FIG>, event <NUM><NUM>, event1, <NUM>, event <NUM><NUM>, event <NUM><NUM>, event <NUM><NUM>, event <NUM><NUM> etc. are used to decode data "<NUM>" when the data on the data line D- has one of the rising edge and falling edge. As shown in <FIG>, event <NUM><NUM> is used to decode data "<NUM>" when no rising edge or falling edge is detected. Some of the predetermined events comprises identifying a stuffed-bit in the synchronized data, such as event <NUM><NUM> and event <NUM><NUM>.

The state logic circuitry <NUM> in <FIG> is configured to store a present state, being a one of the predetermined states. The predetermined states comprise state <NUM><NUM>, state <NUM><NUM>, state <NUM><NUM>, state <NUM><NUM>, state <NUM><NUM>, state <NUM>, <NUM>, state <NUM>, <NUM>, state <NUM><NUM>, state <NUM><NUM> as shown in <FIG>, <FIG> and <FIG>.

The event generator <NUM> in <FIG> is configured to trigger respective ones of the predetermined events, in response to respective combinations of values of the synchronized data, the device clock, the control information and the present state.

A combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data.

A further of the predetermined events comprises outputting, at the output terminals, the decoded stuffed-bit stripped synchronized data and toggling the output clock.

Some of the predetermined events comprising detecting the end of the package. As shown in <FIG>, event <NUM><NUM>, event <NUM><NUM>, event <NUM><NUM> and event <NUM><NUM> are used to detect the end of the package ("EOP").

In this way, the device <NUM> is configurated to comprise two state machine parts (L State Machine part and High State Machine part) to process the USB signal with predetermined states and events. The Low state machine part is for processing USB data streams. The high state machine part is for detecting USB EOP. In other embodiments, the "H State Machine" part may be used for processing USB data streams. And the "L State Machine" part may be used for detecting USB EOP.

<FIG> illustrates the signals captured by using a logic analyzer. Referring to <FIG>, the waveform <NUM> shows the synchronized data carried by the data line D+ and the waveform <NUM> shows the synchronized data carried by the data line D-. The line <NUM> shows the SPI indication signal (HSPI_CS) output through the SPI interface. The waveforms <NUM> and <NUM> show the clock signal (HSPI CLK) and the stuffed-bit stripped synchronized data (HSPI_MOSI) output through the SPI interface respectively. As shown in <FIG>, there is a time delay between the stuffed-bit stripped synchronized data output through the SPI interface at <NUM> and the data carried by the USB data line D+ at <NUM> and the USB data line D- at <NUM>. Take one databyte "E6" for example, when the device <NUM> of <FIG> receives a synchronized data "E6" from the data line D+ as shown at <NUM> and the data line D- as shown at <NUM>, the device <NUM> outputs the decoded stuffed-bit stripped synchronized data and toggling the output clock at the output terminals. The co-processor <NUM> received the decoded stuffed-bit stripped synchronized data, the output clock and the indication signal output from the device <NUM> and converts them to corresponding signals compliant with the SPI specification. The stuffed-bit stripped synchronized data "E6" output through the SPI interface as shown at <NUM> are captured when the clock signal (HSPI CLK) output through the SPI interface toggles. In this way, the present application may convert complex USB synchronized data into simple SPI signals.

Referring now to the use of the terms "a" and "an" and "the" and similar referents in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Furthermore, the foregoing description is for the purpose of illustration only. The use of the term "based on" and other like phrases indicating a condition for bringing about a result, both in the claims and in the written description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the application as claimed.

Claim 1:
A device adapted to implement a state machine which defines a plurality of predetermined states and a plurality of predetermined events, for decoding USB data communicated over a universal serial bus (USB), the device comprising:
a pair of data input terminals for receiving the USB data, and a clock input terminal for receiving a system clock;
a clock processor (<NUM>) coupled to the pair of data input terminals and the clock input terminal, and configured to output, based on the system clock, synchronized data and a device clock;
an event generator (<NUM>) coupled to the clock processor to receive the synchronized data and the device clock;
state logic circuitry (<NUM>) coupled to an output of the event generator;
output terminals (<NUM>), coupled to the event generator and comprising a decoded-data output terminal and a clock output terminal; and
control circuity (<NUM>) coupled to the event generator and for providing control information to the event generator;
wherein the state logic circuitry (<NUM>) is configured to store a present state, being one of the predetermined states;
wherein the event generator is configured to trigger respective ones of the predetermined events, in response to respective combinations of values of the synchronized data, the device clock, the control information and the present state;
wherein:
a one of the predetermined events comprises identifying a stuffed-bit in the synchronized data,
another of the predetermined events comprises stripping the identified stuffed-bit from the synchronized data and not toggling output clock, to provide stuff-bit stripped synchronized data,
a combination of the predetermined events comprises decoding the stuffed-bit stripped synchronized data, to provide decoded stuffed-bit stripped synchronized data,
and a further of the predetermined events comprises outputting, at the output terminals, the decoded stuffed-bit stripped synchronized data and toggling the output clock.