Patent Description:
The Super Junction (SJ) concept in Silicon uses a stack of layers, alternately doped with a p- or n-type dopant, such that the charge in one layer is compensated by the opposite-polarity charge in the next layer, to achieve a high overall charge density. This requires precise doping. Super-Junction based power MOSFETs are commercially available today.

Group III nitride semiconductors, are thought to be good candidates for next generation power devices. They have high electron-saturation velocities, high breakdown fields and wide band gaps, and can provide heterojunctions. At this time, though, it is not possible to implement the SJ concept in group III nitride semiconductors because the doping cannot be controlled with sufficient precision for those semiconductors. In fact, in general it has not been possible to successfully produce a p-type doping in a group III nitride semiconductor device.

There are numerous group-III devices, which take advantage, among other things, of the heterojunctions that can be produced in those devices. A heterojunction is an interface between two layers, or regions, of different semiconductor materials. A heterojunction between different III-nitride semiconductors, e.g. between Aluminium Gallium Nitride (AlGaN) and Gallium Nitride (GaN), can yield a thin layer of highly mobile, highly concentrated electrons thereby resulting in regions with very low resistivity. This layer is called a two-dimensional electron gas (2DEG).

Research effort has gone into developing devices containing parallel n-channels using respective 2DEGs, to reduce overall channel resistivity in the devices. See, for example, patent application <CIT>. However, further developments in devices that can reduce power consumption are highly desirable.

<CIT>, <CIT> and <CIT> disclose various transistor configurations that utilise a 2DEG or 2DHG.

The present invention provides use, as a bi-directional transistor, of a device comprising: a substrate; three semiconductor layers supported on the substrate; wherein the semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer; and a plurality of electrodes comprising: a first source, a second source, and at least one gate electrode arranged to vary the current flowing in either direction between the two sources via at least one of the 2DEG and the 2DHG.

Spontaneous polarization, which is required for the formation of the 2DEG and 2DHG, occurs to a greater or lesser extent in a number of different semiconductor materials. Suitable semiconductors include III-V semiconductors, II-VI semiconductors, and organic (polymer) semiconductors such as PVDF, poly(vinylidene fluoride). Of the III-V semiconductors, group III nitrides are particularly suitable in some embodiments. Examples of II-VI semiconductors are ZnO and MgZnO.

The semiconductor layers may all be of the same semiconductor material, or they may be of different materials.

Therefore at least one of the semiconductor layers may be a III-V semiconductor, which may be a group III nitride. In some cases all three of the semiconductor layers may be III-V semiconductors, and may be group III nitrides.

The electrical connection may be direct, or indirect for example being through one or more intermediate layers of material. Also the electrical connection may be of any type, such as ohmic contact or Schottky contact.

One of the semiconductor layers may be between the other two semiconductor layers. It may form the polarization layer. The 2DHG may be formed at an interface between the polarization layer and another of the semiconductor layers. The 2DEG may be formed at an interface between the polarization layer and the other of the semiconductor layers.

The first semiconductor layer may comprise a group III nitride, such as an undoped aluminium gallium nitride 'u-AlGaN' semiconductor layer. The second semiconductor layer may comprise a group III nitride, such as an undoped Gallium Nitride 'u-GaN' semiconductor layer. The third semiconductor layer may comprise a group III nitride, such as a u-GaN semiconductor layer.

The second semiconductor layer may be is less than half as thick as the first semiconductor layer. The third semiconductor layer may be more than ten times the thickness of the first semiconductor layer.

The present invention further provides use, as a reverse conducting transistor, or a device comprising: a substrate; three semiconductor layers supported on the substrate; wherein the semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer, and a plurality of electrodes comprising: a source electrode and a drain electrode, a gate electrode arranged to vary the current flowing between the source and drain electrodes via at least one of the 2DEG and the 2DHG, and a further electrode arranged to form a Schottky barrier diode with one of the layers to provide a reverse conducting path.

The present invention further provides use, as a bi-directional transistor, of a device comprising: a substrate; three semiconductor layers supported on the substrate; wherein the semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer, and a plurality of electrodes comprising: three electrodes comprising two source-drain pairs, each pair being connected together via one of the 2DEG and the 2DHG, and two gate electrodes each arranged to vary the current flowing between the electrodes in a respective one of the gate-source pairs.

One of the electrodes may be mounted on one of the layers and connected to the 2DEG and another of the electrodes may be mounted on another of the layers and connected to the 2DHG. An upper one of the layers may only partially cover a lower one of the layers. One of the electrodes may be mounted on a part of the lower layer not covered by the upper layer.

The respective regions of p- and n-type carriers may be induced at respective interfaces between layers, as a result of the heterojunctions when different Group-III nitride materials are formed over one another. In that case the carriers may be concentrated at the interface. Alternatively the regions may be formed through impurity doping, and may be spread through the whole or part of the semiconductor layer they are in. The regions may coextend with the respective interfaces or semiconductor layers, or they may extend over only a part of the respective interfaces or semiconductor layers.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings:.

Referring to <FIG>, a Schottky barrier diode (SBD) <NUM> according to one embodiment of the invention comprises a substrate <NUM>, on which are grown three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Three electrodes <NUM>, <NUM>, <NUM> are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

An undoped Gallium Nitride (u-GaN) layer <NUM> is provided directly onto the substrate <NUM>. An undoped Aluminium Gallium Nitride (u-AlGaN) layer <NUM> is provided over the first u-GaN layer <NUM> so that a mobile two-dimensional electron gas (2DEG) <NUM> forms at the heterointerface between the u-GaN and u-AlGaN layers <NUM>, <NUM>. A third layer <NUM>, comprising a second u-GaN layer, is positioned over the u-AlGaN layer <NUM>, so that a two dimensional hole gas (2DHG) <NUM>, which is a planar region, or layer, with majority p-type carriers, is induced at the heterointerface between the u-AlGaN and third layers <NUM>, <NUM>. The 2DEG <NUM> extends as a continuous layer, or planar region, beneath the whole of the 2DHG <NUM>, and specifically under all of the electrodes <NUM>, <NUM>, <NUM>.

The semiconductor layers are arranged such that the respective quantities of positive and negative charges in the 2DHGs and 2DEGs are approximately equal, so a high charge balance condition can be achieved to support high voltage capability. Further information on this point is provided in "<NPL>.

Two of the electrodes - an anode <NUM> and a cathode <NUM> - are provided on top of the third layer <NUM>. The third layer <NUM> is thin enough to permit the anode <NUM> and the cathode <NUM> to be electrically connected to the 2DHG <NUM> by respective current paths 125a, 130a. The anode <NUM> is formed from a metal with a work function that permits an ohmic connection to the 2DHG <NUM>, e.g. nickel or platinum. The cathode <NUM> is formed from a metal with a work function that results in a Schottky barrier connection to the 2DHG <NUM>, e.g. from an alloy of Ti and Al. Accordingly, the anode <NUM> is electrically connected to the cathode <NUM> by the 2DHG <NUM>, via a Schottky barrier junction, and so forms a 2DHG super junction (SJ) Schottky barrier diode. For ease of reference, typical metals that give Ohmic and Schottky contacts to the 2DEG and 2DHG are:.

In this diode <NUM>, the third layer <NUM> extends over most but not all of the u-AlGaN layer <NUM>, leaving an exposed upper surface 115a of the u-AlGaN layer <NUM> at one end. A further cathode <NUM> is provided on the exposed upper surface 115a, so that the cathode <NUM> is positioned between the further cathode <NUM> and the anode <NUM>. In the diode <NUM>, the two cathodes <NUM>, <NUM> can be electrically connected together. The further cathode <NUM> is formed from a metal with a work function that permits an ohmic connection to the GaN layer <NUM> and hence to the 2DEG <NUM>. For example, an alloy of titanium (Ti) and aluminium (Al) may be used for ohmic connection to the 2DEG <NUM>. The u-AlGaN layer <NUM> is thin enough to permit the further cathode <NUM> to be electrically connected to the 2DEG <NUM>. In this instance, 2DEG <NUM> acts as a field strength reducing layer, through charge balance as will be described in more detail below. The further cathode does not have to extend across all of the width of the device cross-section (perpendicular to the plane of <FIG>). A contact made somewhere along the width of the device is adequate.

In a modification to this embodiment, the two cathodes <NUM>, <NUM> are not connected together but are controlled independently.

Referring to <FIG> if a forward voltage is applied between the anode <NUM> and the cathodes <NUM>, <NUM> then, when the threshold voltage of the Schottky barrier diode is exceeded, at about 1V, the diode will start to conduct between the anode <NUM> and the first cathode <NUM> via the 2DHG <NUM>, as shown in <FIG>, and as indicated by (b) in <FIG>. If the forward voltage is increased further then the p-n junctions between the AlGaN layer <NUM> and the two GaN layers <NUM><NUM>, which act as a pn junction diode, will start to conduct between the anode <NUM> and the second cathode <NUM> via the 2DEG <NUM>. This reduces the resistance as in this state both the 2DHG and the 2DEG are conducting, as shown in <FIG> and as indicated by (c) in <FIG>, producing bipolar conduction. If a reverse voltage is applied between the two cathodes <NUM>, <NUM> and the anode <NUM>, so that the cathodes are at a positive potential relative to the anode, then the Schottky diode between the first cathode <NUM> and the top layer <NUM> will tend not to conduct. Also the positive potential at the cathode will start to deplete the 2DEG <NUM> and the polarisation in the GaN layer <NUM>, and hence also the 2DHG <NUM>,as shown in <FIG>, and as indicated by (d) in <FIG>. If the 2DEG and 2DHG are well balanced, their depletion can be almost complete so that they will cease to conduct. This means that the electric field around the electrodes do not increase rapidly with increased reverse voltage, so the device can withstand high reverse voltages, before breakdown occurs.

Referring to <FIG>, a depletion mode p-channel transistor <NUM> according to a second embodiment of the invention is made from a wafer having the structure described above with reference to the first embodiment. Corresponding wafer layers will be referred to in this embodiment by the reference numerals of the first embodiment, but increased by <NUM>. Thus, the transistor <NUM> comprises a substrate <NUM>, on which are grown three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Four electrodes <NUM>, <NUM>, <NUM>, <NUM> are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

Three of the electrodes - a drain electrode <NUM>, a gate electrode <NUM> and a source electrode <NUM> - are provided on top of the third layer <NUM>. The drain electrode <NUM> and the source electrode <NUM> are both formed from a metal with a work function that permits an ohmic connection to the 2DHG <NUM>. The third layer <NUM> is thin enough to permit the drain electrode <NUM> and the source electrode <NUM> to be electrically connected to the 2DHG <NUM> by respective ohmic current paths 225a and 235a. Accordingly, the drain electrode <NUM> is electrically connected to the source electrode <NUM> by the 2DHG <NUM> i.e. by a p-channel.

The gate electrode <NUM> is made from a metal with a small work function which achieves a Schottky-barrier junction between it and the upper GaN layer <NUM> and hence with the 2DHG <NUM>. It is positioned between the drain electrode <NUM> and source electrode <NUM>, above the p-channel formed along the 2DHG <NUM>, and is operable to affect the p-channel. Accordingly, the drain electrode <NUM>, gate electrode <NUM> and source electrode <NUM> electrodes are arranged to form a depletion mode p-channel transistor.

In this transistor <NUM>, the third layer <NUM> extends over most but not all of the u-AlGaN layer <NUM>, leaving an exposed upper surface 215a of the u-AlGaN layer <NUM> at one end. A further source electrode <NUM> is operatively provided on the exposed upper surface 215a, and is in this embodiment electrically connected to the first source electrode <NUM>, though in other embodiments it can be controlled independently. The further source electrode <NUM> is formed from a metal with a work function that permits an ohmic connection to the AlGaN layer <NUM> and hence to the 2DEG <NUM>. The further source does not have to extend across all of the width of the device cross-section (perpendicular to the plane of <FIG>). A contact made somewhere along the width of the device is adequate. The u-AlGaN layer <NUM> is thin enough to permit the further source electrode <NUM> to be electrically connected to the 2DEG <NUM> by an ohmic current path 240a. The 2DEG <NUM> extends as a continuous layer beneath the source electrode <NUM>, the gate electrode <NUM> and the drain electrode <NUM>.

Referring to <FIG>, the depletion mode p-channel transistor <NUM> operates in a similar manner to known p-channel field effect transistors (FETs).

The depletion mode p-channel transistor <NUM> is a 'normally-on' type of transistor in that it has a positive threshold voltage. Therefore when the potential at the gate with respect to the source, the gate-source voltage (Vgs), is zero the transistor <NUM> conducts when forward bias voltage Vds is applied between the source and drain i.e. when the drain is at a negative voltage with respect to the source, as shown in <FIG>, and indicated by (b) in <FIG>. Since the transistor <NUM> is a p-channel (2DHG) device, when it conducts current flows from the source electrode <NUM> to the drain electrode <NUM>. Referring to <FIG>, if the current reaches a saturation threshold, the 2DEG and 2DHG start to deplete as the voltage is further increased and the current does not increase further, until a breakdown voltage is reached.

Increasing Vgs from zero to above the threshold voltage causes a depletion region around the gate electrode <NUM> to enlarge, such that it encroaches on the channel along the 2DHG and switches the transistor off i.e. it stops the current from the source electrode <NUM> to the drain electrode <NUM>, as shown in <FIG>. With forward bias, as shown in <FIG>, charge balancing (depletion) between the 2DEG and 2DHG occurs so the source-drain voltage Vds can be increased to high levels before breakdown occurs.

When a reverse bias voltage is applied between the source and drain, the device conducts via the 2DHG when the gate is turned on, as shown in <FIG>. If the gate is turned off, the device does not conduct at low reverse bias voltages, but when a threshold voltage is reached the 2DEG starts to conduct as shown in <FIG>.

In a further embodiment two of the p-channel transistors <NUM> of this embodiment are provided, adjacent one another, on the same wafer with the respective drain electrodes <NUM> connected together forming a bidirectional transistor as an integrated device.

In the embodiment of <FIG>, the gate electrode <NUM> can extend down into the third layer <NUM> by different amounts to vary the threshold voltage at which it will turn off. In other embodiments, as described below, it can extend through the whole of the third layer <NUM> and through the 2DHG <NUM> in which case the transistor is an enhancement mode transistor. In that case the distance it extends into the second layer <NUM> can be varied to vary the threshold voltage at which it turns on.

Referring now to <FIG>, an enhancement mode p-channel transistor <NUM> according to a third embodiment of the invention is made from a wafer having the structure described above with reference to the first embodiment. Corresponding wafer layers will be referred to in this embodiment by the reference numerals of the first embodiment, but increased by <NUM>. Thus, the transistor <NUM> comprises a substrate <NUM> and three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Four electrodes <NUM>, <NUM>, <NUM>, <NUM> are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

Two of the electrodes - a drain electrode <NUM> and a source electrode <NUM> - are provided on top of the third layer <NUM>. The source electrode <NUM> and the drain electrode <NUM> are each formed from a metal with a work function that permits ohmic connection to the 2DHG <NUM>. The third layer <NUM> is thin enough to permit the drain electrode <NUM> and the source electrode <NUM> to be electrically connected to the 2DHG <NUM> by respective ohmic current paths 325a, 335a.

A gap <NUM> is etched through the third layer <NUM> and part way into the u-AlGaN layer <NUM>, to provide a second exposed surface 315b. A gate electrode <NUM> is provided in, and extends through, the gap <NUM>. The gate electrode <NUM> is a metal insulator semiconductor (MIS) gate, and so comprises a metal separated from the surface of the gap <NUM> by an insulating dielectric. The gate electrode <NUM> is positioned between the other electrodes, with the drain electrode <NUM> on one side and the source electrode <NUM> on the other side, and extends through the p-channel formed along the 2DHG <NUM>. Therefore when no gate voltage is applied, the 2DHG <NUM> is interrupted in the region around the gate <NUM> and so the device is off. In use, when a negative voltage of a magnitude above a threshold is applied to the gate electrode <NUM>, with respect to the source electrode <NUM>, a 2DHG is formed around the gate electrode <NUM>. In this condition the 2DHG is connecting the drain electrode <NUM> to the source electrode <NUM>. Accordingly, the electrodes are arranged to produce an enhancement mode p-channel (2DHG) transistor.

The third layer <NUM> extends over most but not all of the u-AlGaN layer <NUM>, leaving an exposed upper surface 315a of the u-AlGaN layer <NUM> at one end. A further source electrode <NUM> is operatively provided on the exposed upper surface 315a. The further source electrode <NUM> is formed from a metal with a work function that permits an ohmic connection to the 2DEG <NUM>. The u-AlGaN layer <NUM> is thin enough to permit the further source electrode <NUM> to be electrically connected to the 2DEG <NUM> by a current path 340a. The further source does not have to extend across all of the width of the device cross-section (perpendicular to the plane of <FIG>). A contact made somewhere along the width of the device is adequate. The 2DEG <NUM> extends as a continuous layer beneath the two source electrodes <NUM>, <NUM>, the gate electrode <NUM> and the drain electrode <NUM>.

Referring to <FIG>, the enhancement mode p-channel transistor <NUM> operates in a similar manner to other enhancement mode FETs.

The enhancement mode p-channel transistor has a negative threshold voltage and therefore is a 'normally-off' type of transistor i.e. when Vgs=<NUM> no current flows between drain and source electrodes <NUM>, <NUM>. Referring to <FIG>, when a negative Vgs of magnitude above the threshold voltage is applied, a hole gas forms around the gate electrode <NUM> thereby completing a p-channel between the source and drain electrodes <NUM>, <NUM> so that current flows from the source electrode <NUM> to the drain electrode <NUM> as shown in <FIG> when a forward bias voltage is applied between the source and drain. Further increasing the magnitude of Vgs will increase the current until a saturation point is reached. After saturation, further increasing the voltage will not increase the current, as the 2DEG and 2DHG start to deplete, as shown in <FIG>, until a breakdown voltage is reached, at which point the current then starts to increase rapidly. When Vgs is below a threshold voltage the 2DHG around the gate electrode is not present, and the gate is turned off. Therefore a forward bias voltage will not cause current to flow until it reaches a breakdown voltage. As shown in <FIG>, in this state the increasing voltage tends to cause charge balancing between the 2DEG and 2DHG by the super junction effect. This allows the voltage to reach high levels before breakdown occurs.

When a reverse bias voltage is applied, and the gate is turned on, the device conducts via the 2DHG as shown in <FIG>. If the gate is turned off, there is no current at low voltages, but when the reverse bias voltage reaches a threshold the 2DEG and 2DHG start to conduct providing a current path around the gate electrode as shown in <FIG>.

Referring to <FIG>, a complementary transistor pair <NUM> according to one embodiment of the invention is made from a wafer having the structure described above with reference to the first embodiment. Corresponding wafer layers will be referred to in this embodiment by the reference numerals of the first embodiment, but increased by <NUM>. Thus, the transistor pair <NUM> comprises a substrate <NUM> and three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Eight electrodes 425n, 430n, 435n, 440n, 425p, 430p, 435p, 440p are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

The electrodes are arranged such that one side 400n (the left-hand side as shown in <FIG>) of the transistor pair <NUM> forms an enhancement mode n-channel transistor, and the other side 400p forms a p-channel transistor. A first gap <NUM> extends through the third layer <NUM> and the u-AlGaN layer <NUM>, and separates the n-side 400n of those layers from the p-side 400p of them.

Referring first to the n-channel side 400n, the third layer <NUM> extends over some but not all of the u-AlGaN layer <NUM> on that side 400n, leaving first and second exposed upper surfaces 415a, 415b of the AlGaN layer <NUM> - one at either end of the third layer <NUM>. Two of the electrodes on the n-side 400n - a drain electrode 425n and a source electrode 435n - are provided on the exposed surfaces 415a, 415b. The drain electrode 425n and the source electrode 435n are formed from a metal with a work function that permits an ohmic connection to the 2DEG <NUM>. The u-AlGaN layer <NUM> is thin enough to permit the source electrode 435n and the drain electrode 425n to be electrically connected to the 2DEG <NUM> by respective current paths 436n, 426n. Accordingly, the drain electrode 425n can be connected to the source electrode 435n via an n-channel.

A second gap <NUM> is etched down through the first exposed surface 415a of the u-AlGaN layer <NUM>, and part way into the first u-GaN layer <NUM>, on the n-channel side 400n. This provides an exposed surface 410b in the first u-GaN layer <NUM> and an exposed side wall 415d of the u-AlGaN layer <NUM> above that exposed surface 410b.

A gate electrode 430n is provided in, and extends through, the second gap <NUM>. Thus the gate electrode 430n is positioned between the source electrode 435n and the drain electrode 425n on the n-side 400n, and extends through the 2DEG <NUM>. The gate electrode 430n is a metal insulator semiconductor (MIS) gate, and so comprises a metal separated from the exposed surfaces 410b, <NUM> in the gap <NUM> by an insulating dielectric. In use, when a positive Vgs of magnitude above a threshold is applied, an 'enhancement' region is formed in the u-GaN layer <NUM> around the gate electrode 430n. In this condition an n-channel is formed along the 2DEG <NUM> via the enhancement region, connecting the drain electrode 425n to the source electrode 435n. Accordingly, the electrodes on the n-side 400n are arranged to provide an n-channel enhancement mode transistor. As described above the depth of the gate electrode can be varied to vary the threshold voltage, or to make the transistor a depletion mode transistor.

A further source electrode 440n is provided on the third layer <NUM>. The further source electrode 440n is formed from a metal with a work function that permits ohmic connection to the 2DHG <NUM>. The third layer <NUM> is thin enough to permit the further source electrode 440n to be electrically connected to the 2DHG <NUM>. Accordingly, a SJ is formed which comprises the 2DEG and 2DHG. As such it reduces the peak electric strength between the gate and drain electrode, in a similar manner to the 2DHG transistor of <FIG>.

Referring now to the p-channel side 400p shown in <FIG>, two electrodes - a drain electrode 425p and a source electrode 435p - are provided on top of the third layer <NUM>. The drain electrode 425p and the source electrode 435p are each formed from a metal with a work function that permits ohmic connection to the 2DHG <NUM>. The third layer <NUM> is thin enough to permit the drain electrode 425p and the source electrode 435p to be electrically connected to the 2DHG <NUM> by respective current paths 426p, 436p. Accordingly, the drain electrode 425p can be electrically connected to the source electrode 435p via a p-channel along the 2DHG <NUM>.

A third gap <NUM> is etched down through the third layer <NUM> on the p-side 400p, part way into the u-AlGaN layer <NUM>. This provides a fourth exposed surface 415e on the u-AlGaN layer <NUM> and an exposed side wall 420a of the third layer <NUM> above that exposed surface 415e. A gate electrode 430p is provided in, and extends through, the third gap <NUM>. Thus gate electrode 430p is positioned between the drain electrode 425p and the source electrode 435p, and extends through the 2DHG <NUM>. Like the gate electrode 430n on the n-side 400n, the gate electrode 430p on the p-side 400p is a metal insulator semiconductor (MIS) gate. As was described with reference to the third embodiment, in use a p-channel can be formed along the 2DEG <NUM> part of which is formed around the gate electrode 430p, connecting the drain electrode 425p to the source electrode 435p. Accordingly, the electrodes on the p-side 400p are arranged to provide a p-channel enhancement mode transistor on the p-side 400p.

The third layer <NUM> extends over some but not all of the uAlGaN layer <NUM> on the p-side 400p, leaving a fifth exposed upper surface 415c of the uAlGaN layer <NUM> at the end opposite the end adjacent the first gap <NUM>. A further source electrode 440p is provided on the fifth exposed surface 415b, and is formed from a metal with a work function that permits an ohmic connection to the 2DEG <NUM>. The u-AlGaN layer <NUM> is thin enough to permit the further source electrode 440p to be electrically connected to the 2DEG <NUM>. Accordingly, as was described with reference to the embodiment of <FIG>, the further source electrode 440p connects to the 2DEG <NUM> thereby acting like a SJ comprising the 2DEG and 2DHG. As such it reduces the peak electric strength between the gate and drain electrode under certain conditions.

The respective drains 425p, 425n from the p- and n-sides 400p, 400n are connected together by a metal in the gap <NUM> to form a single mass which includes both drains. The combined drain electrodes 425n, 425p also fill a gap in the AlGaN layer <NUM> between the two devices, which ensures that there is a break in the 2DEG <NUM> between the two devices. In variants of this embodiment, however, they may be formed as physically separate electrodes that are subsequently connected together e.g. by a wire.

The respective gates 430p, 430n from the p- and n-sides 400p, 400n are connected together by a wire. However, they may be joined by metal to form as a single integrated electrode, or they may be controlled independently of each other.

In the final packaged device, the sources 440n, 435n on the n-side 400n will be electrically connected together, and the sources 440p, 435p on the p-side 400p will be electrically connected together.

The n-side 400n operates as an enhancement mode n-channel transistor, as will be appreciated from of its transfer characteristics. A enhancement mode n-channel transistor has a positive threshold voltage and therefore is a 'normally off' type of transistor i.e. when Vgs=<NUM> no current flows between the drain and source electrodes <NUM>, <NUM>. When Vgs is increased to above the threshold voltage, a 2DEG is formed around the gate electrode such that current flows from the drain electrode <NUM> to the source electrode <NUM> via the n-channel formed by the enhancement region. Further increasing Vgs will increase the drain current until a saturation point is reached.

While both of the transistors of <FIG> are enhancement mode devices, either or both of them can be modified to be depletion mode devices with suitable re-arrangement of the gate electrode.

In a modification to this embodiment, the respective gates 430p, 430n on the p- and n-sides are instead formed on the third layer <NUM> and the u-AlGaN layer <NUM>, respectively. The gates 430p, 430n are formed from a metal that permits a Schottky barrier connection to the 2DHG <NUM> and the 2DEG <NUM>, respectively, so as to form depletion mode transistors instead of enhancement mode transistors. Alternatively, the plurality of electrodes may be provided in a different arrangement on the n-channel side 400n to form some other n-channel or 2DEG device.

Referring now to <FIG>, a reverse conducting transistor (RCT) <NUM> according to one embodiment of the invention is made from a wafer having the structure described above with reference to the first embodiment. Corresponding wafer layers will be referred to in this embodiment by the reference numerals used in the first embodiment, but increased by <NUM>. Thus, the RCT <NUM> comprises a substrate <NUM> and three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Five electrodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

The third layer <NUM> extends over some but not all of the u-AlGaN layer <NUM>, leaving first and second exposed upper surfaces 515a, 515b of the u-AlGaN layer <NUM> - one at either end. A first source electrode <NUM> is provided on the first exposed upper surface 515a, and a drain electrode <NUM> is provided on the second exposed upper surface 515b. The drain electrode <NUM> and the first source electrode <NUM> are formed from a metal with a work function that permits an ohmic connection to the 2DEG <NUM>. The u-AlGaN layer <NUM> is thin enough to permit the drain electrode <NUM> and the first source electrode <NUM> to be electrically connected to the 2DEG <NUM> by respective current paths 525a, 535a.

Accordingly, the drain electrode <NUM> is electrically connected to the first source electrode <NUM> by the 2DEG <NUM>.

A gate electrode <NUM> and a second source electrode <NUM> are also provided on the first exposed upper surface 515a of the u-AlGaN layer <NUM>. The gate electrode <NUM> and the second source electrode <NUM> are each made from a metal with a large work function which achieves a Schottky-barrier junction between it and the 2DEG <NUM>.

The gate electrode <NUM> is positioned between the drain electrode <NUM> and first source electrode <NUM>, and above the n-channel formed along the 2DEG <NUM>. Therefore it is operable to affect the n-channel between the drain electrode <NUM> and first source electrode <NUM>. Accordingly, the drain electrode <NUM>, gate electrode <NUM> and first source electrode <NUM> electrodes are arranged to form a depletion mode n-channel (2DEG) transistor.

The second source electrode <NUM> is positioned between the gate electrode <NUM> and the drain electrode <NUM>, and the u-AlGaN layer <NUM> is thin enough to permit the second source electrode <NUM> to be connected to the 2DEG <NUM> by a current path 540a (the direction of which is shown for positive current, which is the opposite direction to the flow of negative charge carriers). Therefore the gate electrode <NUM> has no significant affect on the 2DEG between the second source electrode <NUM> and the drain electrode <NUM>. Accordingly the second source electrode <NUM> and drain electrode <NUM> electrodes are arranged to form a 2DEG Schottky barrier diode, the second source electrode <NUM> being the anode.

A third source electrode <NUM> is operatively provided on the third layer <NUM>, at the end adjacent the first exposed upper surface. The third source electrode <NUM> is formed from a metal with a work function that permits an ohmic connection to the 2DHG <NUM> via a current path 542a. Accordingly, a SJ is formed which comprises the 2DEG and 2DHG. As such it reduces the peak electric strength between the gate and drain electrode.

Referring to <FIG>, when Vds (i.e. the voltage applied to the drain with respect to the source) is positive, i.e. a forward bias voltage, the reverse conducting transistor <NUM> operates as a depletion mode n-channel transistor. A depletion mode n-channel transistor has a negative threshold voltage and therefore is a 'normally on' type of transistor i.e. when Vgs=<NUM> negative charge carriers (electrons) flows from the drain electrode <NUM> to the first source electrode <NUM> as shown in <FIG> (which can be considered as a positive current flowing in the opposite direction), until it reaches saturation at which point charge balancing between the 2DEG and 2DHG limits further current increase as shown in <FIG>, up until a breakdown voltage is reached. Again the arrows in <FIG>, and in <FIG>, show flow of charge carriers. Reducing Vgs from zero to a negative voltage of magnitude greater than the threshold voltage causes a depletion region around the gate electrode to expand so as to 'pinch off' the channel between the drain and first source electrodes <NUM>, <NUM>, thereby stopping the current between them. Increasing the bias voltage Vds causes depletion of the 2DEG and 2DHG by charge balancing as shown in <FIG>, so no current will flow until a very high breakdown voltage is reached.

When a reverse voltage is applied so that the potential of the drain with respect to the source, the drain-source voltage (Vds), is negative and when the gate is turned on it conducts via the 2DEG as shown in <FIG>. When the gate is turned off, the reverse conducting transistor <NUM> operates as a 2DEG SJ Schottky-barrier diode with its anode (the second source electrode <NUM>) connected to the first source electrode <NUM> and the drain electrode <NUM> functioning as its cathode, as shown in <FIG>. When the magnitude of the negative Vds exceeds the threshold voltage of the Schottky-barrier junction at the second source electrode <NUM>, current flows from the second source electrode <NUM> to the drain electrode <NUM> via the 2DEG <NUM> and the 2DHG.

In a modification to this embodiment the gate electrode can extend down through the GaN layer <NUM> into the AlGaN layer <NUM> so that the transistor is an enhancement mode transistor similar to that of <FIG>.

Referring now to <FIG>, a reverse conducting transistor (RCT) <NUM> according to a sixth embodiment of the invention is made from a wafer having the structure described above with reference to the first embodiment. Corresponding wafer layers will be referred to in this embodiment by the reference numerals used in the first embodiment, but increased by <NUM>. Thus, the RCT <NUM> comprises a substrate <NUM> and three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Five electrodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

The third layer <NUM> extends over some but not all of the u-AlGaN layer <NUM>, leaving first and second exposed upper surfaces 615a, 615b of the u-AlGaN layer <NUM> - on opposite sides of the region in which the third layer <NUM> is present, one at either end of the RCT <NUM>. A source electrode <NUM> is provided on the first exposed upper surface 615a, and a drain electrode <NUM> is provided on the second exposed upper surface 615b. The drain electrode <NUM> and the source electrode <NUM> are formed from a metal with a work function that permits an ohmic connection to the 2DEG <NUM> by respective current paths 625a, 635a. Accordingly, the drain electrode <NUM> is electrically connected to the source electrode <NUM> by the 2DEG <NUM>.

A gate electrode <NUM> is also provided on the first exposed upper surface 615a between the source electrode <NUM> and the region in which the third layer <NUM> is present. The gate electrode <NUM> is made from a metal with a large work function which achieves a Schottky-barrier junction between it and the 2DEG <NUM>. The gate electrode <NUM> is positioned between the drain electrode <NUM> and the source electrode <NUM>, above the 2DEG <NUM>. The gate electrode <NUM> is therefore operable to affect the n-channel formed along the 2DEG <NUM>, which connects the drain electrode <NUM> to the source electrode <NUM>. Accordingly, the drain electrode <NUM>, gate electrode <NUM> and source electrode <NUM> electrodes are arranged to form a depletion mode 2DEG transistor <NUM>.

A further source electrode <NUM> and a further drain electrode <NUM> are provided on the third layer <NUM>, at its ends adjacent the first and second exposed upper surfaces 615a, 615b respectively, and electrically connected to the source electrode <NUM> and the drain electrode <NUM> respectively. The further source electrode <NUM> is formed from a metal with a work function that permits an ohmic connection to the 2DHG <NUM>. The further drain electrode <NUM> is made from a metal with a small work function which produces a Schottky-barrier junction between it and the 2DHG <NUM>. The further source electrode <NUM> and the further drain electrode <NUM> are electrically connected to the 2DHG <NUM> by respective currents paths 640a, 642a. The gate electrode <NUM> is operable to affect the 2DEG <NUM> but not the 2DHG <NUM>. Accordingly, the 2DHG <NUM> connects the further source electrode <NUM> to the further drain electrode <NUM>, which form a 2DHG Schottky barrier diode in which the further source electrode <NUM> acts as the anode.

When Vds (i.e. the voltage applied to the drain with respect to the source) is positive the reverse conducting transistor <NUM> operates as a depletion mode n-channel transistor, substantially as was described above with reference to the fifth embodiment.

When Vds is negative and the gate electrode is at a potential to prevent conduction via the 2DEG the reverse conducting transistor <NUM> operates as a reverse-coupled 2DHG Schottky-barrier diode. When the magnitude of Vds exceeds the threshold voltage of the diode, current flows from the further source electrode <NUM> to the further drain electrode <NUM> via the 2DHG <NUM>, first in a unipolar mode, then in a bipolar mode when the voltage increases above a threshold, as in <FIG>. In other states, the device operates as a 2DEG d-mode transistor in the same way as the device of <FIG>.

Referring now to <FIG>, a reverse conducting transistor (RCT) <NUM> according to a seventh embodiment of the invention is made from a wafer having the structure described above with reference to the first embodiment. Corresponding wafer layers will be referred to in this embodiment by the reference numerals used in the first embodiment, but increased by <NUM>. Thus, the RCT <NUM> comprises a substrate <NUM> and three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Five electrodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

The third layer <NUM> extends over some but not all of the u-AlGaN layer <NUM>, leaving first and second exposed upper surfaces 615a, 615b of the u-AlGaN layer <NUM> - one at either end. A source electrode <NUM> is provided on the first exposed upper surface 715a, and a drain electrode <NUM> is provided on the second exposed upper surface 715b.

The source electrode <NUM> is formed from a metal with a work function that permits an ohmic connection to the 2DEG <NUM>. The drain electrode <NUM> is formed from a metal with a large work function which achieves a Schottky-barrier junction between it and the 2DEG <NUM>. The u-AlGaN layer <NUM> is thin enough to permit the drain electrode <NUM> and the source electrode <NUM> to be electrically connected to the 2DEG <NUM> by respective current paths 725a, 735a. Accordingly, the 2DEG <NUM> electrically connects the drain electrode <NUM> to the source electrode <NUM>, which form a 2DEG Schottky barrier diode in which the drain electrode <NUM> is the anode.

A further source electrode <NUM> and a further drain electrode <NUM> are provided on the third layer <NUM>, at the ends adjacent the first and second exposed upper surfaces 715a, 715b respectively. In the fully packaged RCT the two sources <NUM>, <NUM> are electrically connected together, and the two drains <NUM>, <NUM> are electrically connected together. A gate electrode <NUM> is provided on the third layer <NUM> between the further source electrode <NUM> and the further drain electrode <NUM>.

The further source electrode <NUM> and the further drain electrode <NUM> are each formed from a metal with a work function that permits an ohmic connection to the 2DHG <NUM>. The further source electrode <NUM> and the further drain electrode <NUM> are electrically connected to the 2DHG <NUM> by respective current paths 740a, 742a. Accordingly, the 2DHG <NUM> connects the further source electrode <NUM> to the further drain electrode <NUM>.

The gate electrode <NUM> is made from a metal with a small work function which achieves a Schottky-barrier junction between it and the2DHG <NUM>. The gate electrode <NUM> is positioned between the further source electrode <NUM> and the further drain electrode <NUM>, above the 2DHG <NUM>. The gate electrode <NUM> is therefore operable to affect the 2DHG <NUM>, which connects the further source electrode <NUM> to the further drain electrode <NUM>, but to have no significant affect on the 2DEG <NUM>. Accordingly, the drain electrode <NUM>, gate electrode <NUM> and source electrodes <NUM>, <NUM> are arranged to form a depletion mode 2DHG transistor <NUM>, which operates like that of <FIG>. The additional electrode <NUM> forms a SBD under reverse bias voltage.

Referring to <FIG>, parts (b), (c), (d), (e), and (f) are the same as those parts in <FIG> as the device operates as that of <FIG>. However, when Vds is positive the reverse conducting transistor <NUM> operates as a 2DEG Schottky-barrier diode. When the magnitude of Vds exceeds the threshold voltage of the diode, current flows from the drain electrode <NUM> to the source electrode <NUM> in unipolar manner via the 2DEG <NUM>, as shown at (f) in <FIG>. When a threshold voltage is reached current starts to flow via the 2DEG and 2DHG in a bipolar manner as shown at (g) in <FIG>.

Referring now to <FIG>, a reverse conducting transistor (RCT) <NUM> according to an eighth embodiment of the invention is made from a wafer having the structure described above with reference to the first embodiment. Corresponding wafer layers will be referred to in this embodiment by the reference numerals used in the first embodiment, but increased by <NUM>. Thus, the RCT <NUM> comprises a substrate <NUM> and three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Five electrodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

A drain electrode <NUM>, a gate electrode <NUM> and first and second source electrodes <NUM>, <NUM> are provided on the third layer <NUM>. The second source electrode <NUM> is provided at one end of the third layer <NUM>, and the drain electrode <NUM> is provided at the opposite end. The second source electrode <NUM> and the drain electrode <NUM> are each formed from a metal with a work function that permits an ohmic connection to the 2DHG <NUM>. The third layer <NUM> is thin enough to permit the second source electrode <NUM> and the drain electrode <NUM> to be electrically connected to the 2DHG <NUM>. Accordingly, the 2DHG <NUM> connects the second source electrode <NUM> to the drain electrode <NUM>.

The gate electrode <NUM> is provided between the drain electrode <NUM> and the second source electrode <NUM>. The gate electrode <NUM> is made from a metal with a small work function which achieves a Schottky-barrier junction between it and the 2DHG <NUM>. The gate electrode <NUM> is positioned between the second source electrode <NUM> and the drain electrode <NUM>, above the 2DHG <NUM>. The gate electrode <NUM> is therefore operable to affect the p-channel formed along the 2DHG <NUM>, which connects the second source electrode <NUM> to the drain electrode <NUM>. Accordingly, the drain electrode <NUM>, the gate electrode <NUM> and the second source electrode <NUM> are arranged to form a depletion mode p-channel transistor <NUM>.

The first source electrode <NUM> is provided between the gate electrode <NUM> and the drain electrode <NUM>. The first source electrode <NUM> is formed from a metal with a small work function which achieves a Schottky-barrier junction between it and the 2DHG <NUM>. The third layer <NUM> is thin enough to permit the first source electrode <NUM> to be electrically connected to the 2DHG <NUM>. Accordingly, the 2DHG <NUM> electrically connects the drain electrode <NUM> to the first source electrode <NUM>, which form a p-channel Schottky barrier diode in which the first source electrode <NUM> is the anode.

The third layer <NUM> extends over some but not all of the u-AlGaN layer <NUM>, leaving an exposed upper surface 815a of the u-AlGaN layer. A third source electrode <NUM> is provided on the exposed surface 815a. In the fully packaged RCT the three sources <NUM>, <NUM>, <NUM> are connected together e.g. by a wire <NUM>. The third source electrode <NUM> is formed from a metal with a work function that permits an ohmic connection to the 2DEG <NUM>. Accordingly, substantially as was described with reference to the third embodiment, , a SJ comprises the 2DEG and 2DHG. As such it reduces the peak electric strength between the gate and drain electrode.

Under most conditions this device acts like the devices of <FIG>, operating as a 2DHG d-mode transistor. However, when Vds is positive the reverse conducting transistor <NUM> operates as a p-channel Schottky-barrier diode. When the magnitude of Vds exceeds the threshold voltage of the diode, current flows from the drain electrode <NUM> to the first source electrode <NUM> via the 2DHG <NUM>.

Referring now to <FIG>, a bidirectional transistor (BT) <NUM> according to an ninth embodiment of the invention is made from a wafer having the structure described above with reference to the first embodiment. Corresponding wafer layers will be referred to in this embodiment by the reference numerals used in the first embodiment, but increased by <NUM>. Thus, the BT <NUM> comprises a substrate <NUM> and three III-nitride semiconductor layers <NUM>, <NUM>, <NUM>. Five electrodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are formed on the semiconductor layers <NUM>, <NUM>, <NUM>.

A gate electrode <NUM> and first and second source electrodes <NUM>, <NUM> are provided on top of the third layer <NUM>. Both source electrodes <NUM>, <NUM> are formed from a metal with a work function that permits an ohmic connection to the 2DHG <NUM>.

The gate electrode <NUM> is located between the two source electrodes <NUM>, <NUM> and is formed from a metal with a work function that achieves a Schottky barrier junction between it and the 2DHG <NUM>.

The third layer <NUM> extends over some but not all of the u-AlGaN layer <NUM>, leaving respective exposed surfaces 915a, 915b of the u-AlGaN layer <NUM> at either end of the BT <NUM>. First and second further gate electrodes <NUM>, <NUM> are provided on the u-AlGaN layer <NUM>, one on each of the exposed surfaces 915a, 915b. The two further gate electrodes <NUM>, <NUM> are electrically connected to the gate <NUM>.

Both further gate electrodes <NUM>, <NUM> are formed from a metal with a work function that permits an ohmic connection to the 2DEG <NUM>, and the u-AlGaN layer <NUM> is thin enough to permit them to be connected to the 2DEG <NUM> via respective current paths 925a, 935a. The 2DEG <NUM> extends in a continuous layer beneath the gate electrode <NUM> and both source electrodes <NUM>, <NUM>.

The voltage between the two source electrodes <NUM>, <NUM> can be arranged such that current flows either way between them through the 2DHG, under control of the gate voltage applied to the gate, with the more positive source electrode acting as the source and the more negative source electrode acting as the drain. As this s a D-mode device a positive voltage Vgs applied to the gate electrode <NUM> (relative to the source) turns the transistor off, whichever way the current is flowing through it. When the positive gate voltage is applied, the two further gate electrodes <NUM>, <NUM> will also be positive with respect to the source which will deplete the 2DEG and hence also the 2DHG, thereby increasing the breakdown voltage of the device.

Devices in accordance with the invention may be formed from various wafers suitable for inducing an n-channel, e.g. a 2DEG, and/or a p-channel e.g. a 2DHG. For example, one suitable wafer structure comprises four III-nitride semiconductor layers grown on a sapphire substrate. The bottom two layers are a u-GaN layer beneath an u-AlGaN (x=<NUM>) layer, at approximately <NUM> thick and approximately <NUM> thick respectively. The third layer <NUM>, <NUM>, <NUM> in the embodiments described above is replaced by two layers: a u-GaN lower layer and a p-type GaN (p-GaN) upper layer. The u-GaN lower layer is approximately <NUM> thick, and the p-GaN upper layer is approximately <NUM> thick and is doped with Magnesium (Mg) at a doping density of approximately 3e19 cm-<NUM>.

In one suitable variant of this example structure, an Indium Gallium Nitride (InGaN) layer and a Mg doped InGaN layer replace the top two layers. In another variant, an InGaN layer replaces the bottom layer. Many more suitable variants will be apparent to those skilled in the art. The fifth, sixth, seventh and eighth embodiments comprise respective reverse conducting transistors which include a depletion mode transistor and a Schottky barrier diode. Persons skilled in the art will be appreciate that, in variations of those embodiments, an enhancement mode transistor could replace the depletion mode transistor and a PN junction diode could replace the Schottky barrier diode where applicable. Such variations are considered to fall within the scope of the invention.

In the embodiments comprising a depletion mode and enhancement mode transistors, the gate electrode has been described as being formed from a metal which permits a Schottky barrier junction to a 2DHG or a 2DEG. In variations of those embodiments, the gate electrode may instead be a MIS gate. Indeed in all embodiments where a Schottky barrier gate electrode is described, a MIS electrode can be used instead.

In the embodiments, an undoped Gallium Nitride layer is provided directly onto the substrate. It will be clear to the skilled person may put a initial layer, e.g. an Aluminium Nitride buffer layer, between the undoped Gallium Nitride layer and the substrate.

Whereas the embodiments described above include group III nitrides, other materials which show spontaneous polarization and therefore can form the 2DEG and 2DHG can also be used. Suitable semiconductors include other III-V semiconductors, II-VI semiconductors, and organic (polymer) semiconductors such as PVDF, poly(vinylidene fluoride). Examples of II-VI semiconductors are ZnO and MgZnO.

In many of the embodiments described above two of the electrodes are connected together, such as the two cathode electrodes of <FIG>. It will be clear to the skilled may that in each case the electrodes do not need to be connected together and can be controlled independently, either to produce the same results, or to allow more flexibility in the way the device is controlled.

Whereas the wafer structures, and the embodiments of the invention made from it, have been described with layers in one order, it will be appreciated that the layers could be formed in a different order. For example, the layers could be formed so that a 2DHG is induced beneath a 2DEG, instead of above it.

Claim 1:
Use, as a bi-directional transistor, of a device comprising:
three semiconductor layers (<NUM>, <NUM>, <NUM>); wherein the semiconductor layers are arranged to form a 2DHG (<NUM>)
and a 2DEG (<NUM>) separated by a polarization layer, a plurality of electrodes comprising:
a first source (<NUM>), a second source (<NUM>), and at least one gate electrode (<NUM>) arranged to vary the current flowing in either direction between the two sources via at least one of the 2DEG and the 2DHG.