Patent Description:
The present disclosure is generally related to wireless communications and, more particularly, to joint encoding schemes with interleaver and tone mapper for multiple-resource unit (multi-RU) operation.

In order to achieve better efficiency in spectrum utilization as well as to achieve frequency diversity for improved link quality, multi-RU allocation for a single station (STA) has been adopted in the next-generation wireless local area network (WLAN) standard Institute of Electrical and Electronics Engineers (IEEE) <NUM>. 11be for extreme high-throughput (EHT) wireless communications. With multi-RU, the STA would be allowed to receive and/or transmit using more than one RU. There are several technical issues to be addressed in order to implement multi-RU operations such as, for example, how to encode information and how to interleave and tone map to multiple RUs. For binary convolutional codes (BCC) encoding of multi-RU operations, encoded bits would need to go through a BCC interleaver. On the other hand, for low-density parity-check (LDPC) encoding of multi-RU operations, the encoded bits would be modulated and then go through an LDPC tone mapper. However, how the BCC interleaver and LDPC tone mapper are implemented remains to be defined or otherwise designed by individual vendors.

<CIT> focuses on transmitter architecture for Resource Units, RUs, transmission with separate, independent coding, stream parsing , constellation mapping and LDPC tone mapping for each RUs, or with common, joint LDCP coding, stream parser, constellation mapper and LDPC tone mapper for two RUs. Intermediate solutions between common and individual processing of <NUM> RUs for the different modules are proposed.

<CIT> discusses the use of joint interleaving and joint LDPC tone mapper for a WLAN system with <NUM> protocol when multiple RUs are allocated for transmission. But it appears that the joint interleaving and joint LDPC tone mapping is only performed for RUs of the same size.

<CIT> discloses several method transmit data from a Base Station (BS) to a User Equipment (UE) for multicarrier HSDPA. The third method (<FIG>) uses CRC, segmentation, channel coding, rate matching, scrambling, interleaving, constellation rearrangement common to the N streams, before data are mapped to different carriers. Code blocks are segmented according to the Transport Block Size (TBS) selected by the BS according to channel measurements fed back by the UE.

<CIT> is a late document potentially relevant for Article <NUM>(<NUM>) EPC and discloses the use of multi-RUs scheduling to determine virtual RUs parameters and to configure Pre FEC padding, FEC encoding and post FEC padding for joint encoding of the multiple RUs. The virtual RUs is processed by a segment parser, constellation mapper, LDPC tone mapper. The virtual RU is made of aggregated RUs.

The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce concepts, highlights, benefits and advantages of the novel and non-obvious techniques described herein. Select implementations are further described below in the detailed description.

An objective of the present disclosure is to provide schemes, concepts, designs, techniques, methods and apparatuses pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation. A method according to the invention is defined in independent claim <NUM>.

In one aspect, a method according to claim <NUM> is disclosed.

The dependent claims define preferred embodiments of the invention.

It is noteworthy that, although description provided herein may be in the context of certain radio access technologies, networks and network topologies such as, Wi-Fi, the proposed concepts, schemes and any variation(s)/derivative(s) thereof may be implemented in, for and by other types of radio access technologies, networks and network topologies such as, for example and without limitation, Bluetooth, ZigBee, <NUM>th Generation (<NUM>)/New Radio (NR), Long-Term Evolution (LTE), LTE-Advanced, LTE-Advanced Pro, Internet-of-Things (IoT), Industrial loT (IIoT) and narrowband loT (NB-loT). Thus, the scope of the present disclosure is not limited to the examples described herein.

Implementations in accordance with the present disclosure relate to various techniques, methods, schemes and/or solutions pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in wireless communications. According to the present disclosure, a number of possible solutions may be implemented separately or jointly. That is, although these possible solutions may be described below separately, two or more of these possible solutions may be implemented in one combination or another.

Referring to <FIG>, network environment <NUM> may involve at least a STA <NUM> which is associated with, and communicating wirelessly with, an access point (AP) <NUM> in a basic service set (BSS) <NUM> in accordance with one or more IEEE <NUM> standards (e.g., IEEE <NUM>. 11ax, IEEE <NUM>. 11be and future-developed standards). STA <NUM> may be allocated by AP <NUM> multiple RUs for multi-RU operation in that STA <NUM> may receive and transmit using the allocated multiple RUs. Under various proposed schemes in accordance with the present disclosure, STA <NUM> and AP <NUM> may be configured to perform joint encoding schemes with interleaver and tone mapper for multi-RU operation in wireless communications in accordance with various proposed schemes described below.

For multi-RU operations, any of a number of approaches may be utilized, including independent encoding per RU, joint encoding across multiple RUs, and mixed encoding involving a combination of independent encoding per RU and joint encoding across multiple RUs. For joint and/or mixed encoding approaches, a new concept of "aggregate RU" (herein interchangeably referred as "virtual RU") may be utilized in pre-forward error correction (pre-FEC) padding, post-FEC padding and encoding process for multi-RU operations under various proposed schemes in accordance with the present disclosure. For instance, for BCC encoding of multiple RUs (assuming the size of virtual RU is less than or equal to <NUM>), the encoded bits would be processed by BCC interleaver(s) through which interleaving may be performed on either an individual-RU (herein interchangeably referred as "physical-RU") basis or an aggregate-RU (herein interchangeably referred as "virtual-RU") basis. Similarly, for LDPC encoding of multiple RUs, the encoded bits would be modulated and the processed by LDPC tone mapper(s) through which tone mapping may be performed on either the individual-RU (or physical-RU) basis or the aggregate-RU (or virtual-RU) basis. The term "aggregate RU" (or "virtual RU") herein refers to an aggregate or combination of two or more physical RUs (e.g., a <NUM>-tone RU and a <NUM>-tone RU with total <NUM> tones), and the term "individual RU" (or "physical RU") herein refers to an individual RU with one or more tones (e.g., as defined under IEEE <NUM>.

<FIG> illustrates an example design <NUM> in accordance with the present disclosure. Design <NUM> may be a design or configuration of electronic circuitry in STA <NUM> for multi-RU operations with processing of bit sequences on an individual-RU (or physical-RU) basis. Referring to <FIG>, design <NUM> may include a joint encoding stage and a post-joint encoding stage. The post-joint encoding stage may process multiple RUs on an individual-RU (or physical-RU) basis. The joint encoding stage may involve various functional blocks in series including, for example, a cyclic redundancy check (CRC32) function, which converts a variable-length string into a <NUM>-bit binary sequence, followed by a scrambler, followed by a pre-FEC padding block, followed by a FEC encoding block, followed by a post-FEC padding block, followed by a stream parser, followed by a segment parser, followed by an RU parser. The joint encoding stage may receive, for transmission (TX), a plurality or a string of information bits and perform joint encoding thereon to generate a plurality or a string of encoded bit sequences. The joint encoding stage may also include additional functional blocks such as a multi-RU configuration block and an aggregate-RU parameter selection block. The multi-RU configuration block may provide configuration information to the aggregate-RU parameter selection block as well as the RU parser. Based on the configuration information, the aggregate-RU parameter selection block may select a corresponding set of parameters from a plurality of possible sets of parameters and provide the selected set of parameters to the pre-FEC padding block, the FEC encoding block, the post-FEC padding block and the RU parser.

The post-joint encoding stage may include n individual-RU processing sets, with n being a positive integer greater than <NUM> and representing the number of RUs of the multiple RUs (e.g., RU<NUM> - RUn) allocated to STA <NUM>. Each individual-RU processing set may include a Rui interleaver, followed by a Rui modulator, followed by a Rui tone mapper, with <NUM> ≤ i ≤ n. The n individual-RU processing sets may process the plurality of encoded bit sequences generated by the joint encoding stage. Specifically, the n individual-RU processing sets may process the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to the n RUs allocated to STA <NUM> on an individual-RU (physical-RU) basis to generate a plurality of processed bit sequences. In particular, the RU parser may parser the plurality of encoded bit sequences to the RU<NUM> - RUn interleavers each of which, in turn, may interleave a respective encoded bit sequence from the plurality of encoded bit sequences to provide a respective interleaved bit sequence, via a respective one of the RU<NUM> - RUn modulators, to a respective one of the RU<NUM> - RUn tone mappers. Each of the RU<NUM> - RUn tone mappers may tone map the respective interleaved bit sequence to provide a respective processed bit sequence of the plurality of processed bit sequences. The processed bit sequences may then be mapped by a RU mapper and provided to an inverse fast Fourier transform (IFFT) functional block which converts one or more signals represented by the processed bit sequences from the frequency domain to the time domain for transmission by one or more antennas as radio frequency (RF) waves.

Under a proposed scheme in accordance with the present disclosure, each of the RU<NUM> - RUn interleavers may be a BCC interleaver and each of the RU<NUM> - RUn tone mappers may be an LDPC tone mapper. Under the proposed scheme, interleaver parameters as defined in the IEEE <NUM>. 11ax specification (e.g., in Table <NUM>-<NUM>) may be utilized by each of the RU<NUM> - RUn interleavers in interleaving the respective encoded bit sequence on the individual-RU (or physical-RU) basis. Similarly, tone mapper parameters as defined in the IEEE <NUM>. 11ax specification (e.g., in Table <NUM>-<NUM>) may be utilized by each of the RU<NUM> - RUn tone mappers in tone mapping the respective encoded bit sequence on the individual-RU (or physical-RU) basis.

<FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, the interleaver parameters as defined in Table <NUM>-<NUM> of the IEEE <NUM>. 11ax specification may be utilized by each of the RU<NUM> - RUn interleavers of design <NUM> in interleaving the respective encoded bit sequence on the individual-RU (or physical-RU) basis. Likewise, the tone mapper parameters as defined in Table <NUM>-<NUM> of the IEEE <NUM>. 11ax specification may be utilized by each of the RU<NUM> - RUn tone mappers of design <NUM> in tone mapping the respective encoded bit sequence on the individual-RU (or physical-RU) basis.

<FIG> illustrates an example design <NUM> in accordance with the present disclosure. Design <NUM> may be a design or configuration of electronic circuitry in STA <NUM> for multi-RU operations with processing of bit sequences on an aggregate-RU (or virtual-RU) basis.

Referring to <FIG>, design <NUM> may include a joint encoding stage and a post-joint encoding stage. The post-joint encoding stage may process multiple RUs on an aggregate-RU (or virtual-RU) basis. The joint encoding stage may involve various functional blocks in series including, for example, a CRC32 function, which converts a variable-length string into a <NUM>-bit binary sequence, followed by a scrambler, followed by a pre-FEC padding block, followed by a FEC encoding block, followed by a post-FEC padding block, followed by a stream parser, followed by a segment parser. The joint encoding stage may receive, for transmission (TX), a plurality or a string of information bits and perform joint encoding thereon to generate a plurality or a string of encoded bit sequences. The joint encoding stage may also include additional functional blocks such as a multi-RU configuration block and an aggregate-RU parameter selection block. The multi-RU configuration block may provide configuration information to the aggregate-RU parameter selection block as well as the RU parser. Based on the configuration information, the aggregate-RU parameter selection block may select a corresponding set of parameters from a plurality of possible sets of parameters and provide the selected set of parameters to the pre-FEC padding block, the FEC encoding block, the post-FEC padding block and various functional blocks of the post-joint encoding stage.

The post-joint encoding stage may include a virtual RU (vRU) interleaver, followed by a vRU modulator, followed by a vRU tone mapper, followed by a RU parser. The post-joint encoding stage may process the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to the plurality of RUs (e.g., n RUs) allocated to STA <NUM> on an aggregate-RU (virtual-RU) basis to generate a plurality of processed bit sequences. In particular, the vRU interleaver may interleave the plurality of encoded bit sequences with respect to an aggregate of the plurality of RUs to provide a plurality of interleaved bit sequences, via the vRU modulator, to the vRU tone mapper. The vRU tone mapper may tone map the plurality of interleaved bit sequences with respect to the aggregate of the plurality of RUs to provide the plurality of processed bit sequences to the RU parser. The RU parser may parse the plurality of processed bit sequences. The processed bit sequences may then be mapped by a RU mapper and provided to an IFFT functional block which converts one or more signals represented by the processed bit sequences from the frequency domain to the time domain for transmission by one or more antennas as RF waves.

According to the claimed invention, the vRU interleaver may be a BCC interleaver and the vRU tone mapper may be an LDPC tone mapper. According to the claimed invention, the vRU interleaver may interleave the plurality of encoded bit sequences on the aggregate-RU (or virtual-RU) basis by using any set of interleaver parameters among a plurality of sets of interleaver parameters shown in <FIG>. According to the claimed invention, the vRU interleaver may utilize a set of parameters corresponding to a <NUM>-tone RU and a <NUM>-tone RU for a total of <NUM> data subcarriers (e.g., Nsd = <NUM>), with a number of interleaver matrix columns being <NUM> (e.g., Ncol = <NUM>) and a number of interleaver matrix rows being a multiple of <NUM> (e.g., Nrow = <NUM> * a number of coded bits per single carrier for each spatial stream (Nbpscs)). Similarly, the vRU tone mapper may tone map the plurality of interleaved bit sequences on the aggregate-RU (or virtual-RU) basis by using any set of tone mapper parameters among a plurality of sets of tone mapper parameters shown in <FIG> and <FIG>. According to the claimed invention, the vRU tone mapper may utilize a set of parameters corresponding to a <NUM>-tone RU and a <NUM>-tone RU, with a distance between tones being <NUM> (e.g., DTM = <NUM>). Alternatively, the vRU tone mapper may utilize a set of parameters corresponding to a <NUM>-tone RU and a <NUM>-tone RU, with a distance between tones being <NUM> (e.g., DTM = <NUM>).

<FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, scenario <NUM> shows some possible sets of interleaver parameters and some possible sets of tone mapper parameters that may be utilized by the vRU interleaver and the vRU tone mapper of design <NUM>, respectively. It is noteworthy that, for smaller-size RUs (e.g., less than <NUM> tones), the RUs may be contiguous to one another in the frequency domain, while larger-size RUs may not necessarily be contiguous in the frequency domain.

<FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, scenario <NUM> shows some possible sets of interleaver parameters without dual carrier modulation (DCM), or DCM = <NUM>. <FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, scenario <NUM> shows some possible sets of interleaver parameters with DCM, or DCM = <NUM>. <FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, scenario <NUM> shows some possible sets of interleaver parameters without DCM, or DCM = <NUM>. <FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, scenario <NUM> shows some possible sets of interleaver parameters with DCM, or DCM = <NUM>. <FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, scenario <NUM> shows some possible sets of tone mapper parameters without DCM, or DCM = <NUM>. <FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, scenario <NUM> shows some possible sets of tone mapper parameters without DCM, or DCM = <NUM>. <FIG> illustrates an example scenario <NUM> in accordance with the present disclosure. Referring to <FIG>, scenario <NUM> shows some possible sets of tone mapper parameters with DCM, or DCM = <NUM>.

<FIG> illustrates an example system <NUM> having at least an example apparatus <NUM> and an example apparatus <NUM> in accordance with an implementation of the present disclosure. Each of apparatus <NUM> and apparatus <NUM> may perform various functions to implement schemes, techniques, processes and methods described herein pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in wireless communications, including the various schemes described above with respect to various proposed designs, concepts, schemes, systems and methods described above as well as processes described below. For instance, apparatus <NUM> may be implemented in STA <NUM> and apparatus <NUM> may be implemented in AP <NUM>, or vice versa.

Each of apparatus <NUM> and apparatus <NUM> may be a part of an electronic apparatus, which may be a STA or an AP, such as a portable or mobile apparatus, a wearable apparatus, a wireless communication apparatus or a computing apparatus. When implemented in a STA, each of apparatus <NUM> and apparatus <NUM> may be implemented in a smartphone, a smart watch, a personal digital assistant, a digital camera, or a computing equipment such as a tablet computer, a laptop computer or a notebook computer. Each of apparatus <NUM> and apparatus <NUM> may also be a part of a machine type apparatus, which may be an IoT apparatus such as an immobile or a stationary apparatus, a home apparatus, a wire communication apparatus or a computing apparatus. For instance, each of apparatus <NUM> and apparatus <NUM> may be implemented in a smart thermostat, a smart fridge, a smart door lock, a wireless speaker or a home control center. When implemented in or as a network apparatus, apparatus <NUM> and/or apparatus <NUM> may be implemented in a network node, such as an AP in a WLAN.

In some implementations, each of apparatus <NUM> and apparatus <NUM> may be implemented in the form of one or more integrated-circuit (IC) chips such as, for example and without limitation, one or more single-core processors, one or more multicore processors, one or more reduced-instruction set computing (RISC) processors, or one or more complex-instruction-set-computing (CISC) processors. In the various schemes described above, each of apparatus <NUM> and apparatus <NUM> may be implemented in or as a STA or an AP. Each of apparatus <NUM> and apparatus <NUM> may include at least some of those components shown in <FIG> such as a processor <NUM> and a processor <NUM>, respectively, for example. Each of apparatus <NUM> and apparatus <NUM> may further include one or more other components not pertinent to the proposed scheme of the present disclosure (e.g., internal power supply, display device and/or user interface device), and, thus, such component(s) of apparatus <NUM> and apparatus <NUM> are neither shown in <FIG> nor described below in the interest of simplicity and brevity.

In one aspect, each of processor <NUM> and processor <NUM> may be implemented in the form of one or more single-core processors, one or more multicore processors, one or more RISC processors or one or more CISC processors. That is, even though a singular term "a processor" is used herein to refer to processor <NUM> and processor <NUM>, each of processor <NUM> and processor <NUM> may include multiple processors in some implementations and a single processor in other implementations in accordance with the present disclosure. In another aspect, each of processor <NUM> and processor <NUM> may be implemented in the form of hardware (and, optionally, firmware) with electronic components including, for example and without limitation, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and/or one or more varactors that are configured and arranged to achieve specific purposes in accordance with the present disclosure. In other words, in at least some implementations, each of processor <NUM> and processor <NUM> is a special-purpose machine specifically designed, arranged and configured to perform specific tasks including those pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in wireless communications in accordance with various implementations of the present disclosure. For instance, each of processor <NUM> and processor <NUM> may be configured with hardware, electronic components and/or circuitry arranged in design <NUM> and design <NUM> (e.g., one or more encoding/processing pipelines of circuitry according to design <NUM> and one or more encoding/processing pipelines of circuitry according to design <NUM>).

In some implementations, apparatus <NUM> may also include a transceiver <NUM> coupled to processor <NUM>. Transceiver <NUM> may include a transmitter capable of wirelessly transmitting and a receiver capable of wirelessly receiving data. In some implementations, apparatus <NUM> may also include a transceiver <NUM> coupled to processor <NUM>. Transceiver <NUM> may include a transmitter capable of wirelessly transmitting and a receiver capable of wirelessly receiving data. It is noteworthy that, although transceiver <NUM> and transceiver <NUM> are illustrated as being external to and separate from processor <NUM> and processor <NUM>, respectively, in some implementations, transceiver <NUM> may be an integral part of processor <NUM> as a system on chip (SoC) and/or transceiver <NUM> may be an integral part of processor <NUM> as a SoC.

Each of apparatus <NUM> and apparatus <NUM> may be a communication entity capable of communicating with each other using various proposed schemes in accordance with the present disclosure. For illustrative purposes and without limitation, a description of capabilities of apparatus <NUM>, as STA <NUM>, and apparatus <NUM>, as AP <NUM>, is provided below. It is noteworthy that, although a detailed description of capabilities, functionalities and/or technical features of apparatus <NUM> is provided below, the same may be applied to apparatus <NUM> although a detailed description thereof is not provided solely in the interest of brevity. It is also noteworthy that, although the example implementations described below are provided in the context of WLAN, the same may be implemented in other types of networks.

Under a proposed scheme pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in accordance with the present disclosure, with apparatus <NUM> implemented in or as STA <NUM> and apparatus <NUM> implemented in or as AP <NUM> associated with a BSS (e.g., BSS <NUM>) of a wireless network such as a WLAN in network environment <NUM> in accordance with one or more of IEEE <NUM> standards, processor <NUM> of apparatus <NUM> may perform joint encoding of a plurality of information bits to generate a plurality of encoded bit sequences. Additionally, processor <NUM> may process the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to a plurality of RUs (e.g., allocated to apparatus <NUM> by apparatus <NUM> as AP <NUM>) on either or both of an aggregate-RU (or virtual-RU) basis and an individual-RU (or physical-RU) basis to generate a plurality of processed bit sequences. Moreover, processor <NUM> may transmit, via transceiver <NUM>, the plurality of processed bit sequences to apparatus <NUM> over the plurality of RUs.

According to the invention, in processing the plurality of encoded bit sequences, processor <NUM> interleaves and tone maps the encoded bit sequences on the aggregate-RU (or virtual-RU) basis by performing certain operations. For instance, processor <NUM> interleaves, by an interleaver of processor <NUM> (e.g., the vRU interleaver in design <NUM>), the plurality of encoded bit sequences with respect to an aggregate of the plurality of RUs to provide a plurality of interleaved bit sequences. Additionally, processor <NUM> tone maps, by a tone mapper of processor <NUM> (e.g., the vRU tone mapper in design <NUM>), the plurality of interleaved bit sequences with respect to the aggregate of the plurality of RUs to provide the plurality of processed bit sequences. Moreover, processor <NUM> may parse, by a parser of processor <NUM> (e.g., the RU parser in design <NUM>), the plurality of processed bit sequences.

According to the claimed invention, in interleaving the plurality of encoded bit sequences, processor <NUM> may interleave, by a BCC interleaver of processor <NUM> (e.g., the vRU interleaver in design <NUM>), the plurality of encoded bit sequences with respect to one or more sizes of RUs with corresponding one or more interleaver parameters.

According to the claimed invention, the one or more sizes of RUs may include a <NUM>-tone RU and a <NUM>-tone RU for a total of <NUM> data subcarriers (e.g., Nsd = <NUM>). In such cases, the one or more interleaver parameters may include a number of interleaver matrix columns being <NUM> (e.g., Ncol = <NUM>) and a number of interleaver matrix rows being a multiple of <NUM> (e.g., Nrow = <NUM> * a number of coded bits per single carrier for each spatial stream (Nbpscs)).

According to the claimed invention, in tone mapping the plurality of interleaved bit sequences, processor <NUM> may tone map, by an LDPC tone mapper of processor <NUM> (e.g., the vRU tone mapper in design <NUM>), the plurality of interleaved bit sequences with respect to one or more sizes of RUs with corresponding one or more tone mapper parameters.

According to the claimed invention, the one or more sizes of RUs may include a <NUM>-tone RU and a <NUM>-tone RU. In such cases, the one or more tone mapper parameters comprise a distance between tones being <NUM> (DTM = <NUM>).

In some non-claimed implementations, in processing the plurality of encoded bit sequences, processor <NUM> may interleave and tone mapping the encoded bit sequences on the individual-RU (or physical-RU) basis by performing certain operations. For instance, processor <NUM> may parse, by a parser of processor <NUM> (e.g., the RU parser in design <NUM>), the plurality of encoded bit sequences to a plurality of interleavers of processor <NUM> (e.g., the RU<NUM> - RUn interleavers in design <NUM>) each of which corresponding to a respective one of the plurality of RUs. Moreover, processor <NUM> may interleave, by each of the plurality of interleavers, a respective encoded bit sequence from the plurality of encoded bit sequences to provide a respective interleaved bit sequence to a respective one of a plurality of tone mappers of processor <NUM> (e.g., the RU<NUM> - RUn tone mappers in design <NUM>) each of which corresponding to a respective one of the plurality of RUs. Furthermore, processor <NUM> may tone map, by each of the plurality of tone mappers, the respective interleaved bit sequence to provide a respective processed bit sequence of the plurality of processed bit sequences.

In some implementations, in parsing the plurality of encoded bit sequences, processor <NUM> may parse the plurality of encoded bit sequences with respect to one or more sizes of RUs with corresponding interleaver parameters and tone mapper parameters.

In some implementations, the plurality of interleavers may include BCC interleavers. Moreover, the plurality of tone mappers may include LDPC tone mappers. In such cases, the interleaver parameters and the tone mapper parameters may include interleaver parameters and tone mapper parameters specified in IEEE <NUM>1ax specification for Wi-Fi (e.g., the parameters specified in Table <NUM>-<NUM> and Table <NUM>-<NUM> of the IEEE <NUM>. 11ax specification).

Under another proposed scheme pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in accordance with the present invention, with apparatus <NUM> implemented in or as STA <NUM> and apparatus <NUM> implemented in or as AP <NUM> associated with a BSS (e.g., BSS <NUM>) of a wireless network such as a WLAN in network environment <NUM> in accordance with one or more of IEEE <NUM> standards, processor <NUM> of apparatus <NUM> performs joint encoding of a plurality of information bits to generate a plurality of encoded bit sequences. Additionally, processor <NUM> processes the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to a plurality of RUs allocated to apparatus <NUM> (e.g., by apparatus <NUM> as AP <NUM>) on an aggregate-RU (or virtual-RU) basis to generate a plurality of processed bit sequences. For instance, processor <NUM> interleaves, by an interleaver of processor <NUM> (e.g., the vRU interleaver in design <NUM>), the plurality of encoded bit sequences with respect to an aggregate of the plurality of RUs to provide a plurality of interleaved bit sequences. Additionally, processor <NUM> tone maps, by a tone mapper of processor <NUM> (e.g., the vRU tone mapper in design <NUM>), the plurality of interleaved bit sequences with respect to the aggregate of the plurality of RUs to provide the plurality of processed bit sequences. Moreover, processor <NUM> may parse, by a parser of processor <NUM> (e.g., the RU parser in design <NUM>), the plurality of processed bit sequences. Afterwards, processor <NUM> may transmit, via transceiver <NUM>, the plurality of processed bit sequences to apparatus <NUM> over the plurality of RUs.

In some implementations, in interleaving the plurality of encoded bit sequences, processor <NUM> may interleave, by a BCC interleaver of processor <NUM>, the plurality of encoded bit sequences with respect to one or more sizes of RUs with corresponding one or more interleaver parameters.

In some implementations, the one or more sizes of RUs may include a <NUM>-tone RU and a <NUM>-tone RU for a total of <NUM> data subcarriers (e.g., Nsd = <NUM>). In such cases, the one or more interleaver parameters may include a number of interleaver matrix columns being <NUM> (e.g., Ncol = <NUM>) and a number of interleaver matrix rows being a multiple of <NUM> (e.g., Nrow = <NUM> * Nbpscs).

In some implementations, in tone mapping the plurality of interleaved bit sequences, processor <NUM> may tone map, by an LDPC tone mapper of processor <NUM>, the plurality of interleaved bit sequences with respect to one or more sizes of RUs with corresponding one or more tone mapper parameters.

In some implementations, the one or more sizes of RUs may include a <NUM>-tone RU and a <NUM>-tone RU. In such cases, the one or more tone mapper parameters may include a distance between tones being <NUM> (DTM = <NUM>).

Under yet another proposed scheme pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in accordance with the present disclosure, with apparatus <NUM> implemented in or as STA <NUM> and apparatus <NUM> implemented in or as AP <NUM> associated with a BSS (e.g., BSS <NUM>) of a wireless network such as a WLAN in network environment <NUM> in accordance with one or more of IEEE <NUM> standards, processor <NUM> of apparatus <NUM> may perform joint encoding of a plurality of information bits to generate a plurality of encoded bit sequences. Additionally, processor <NUM> may process the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to a plurality of RUs allocated to apparatus <NUM> (e.g., by apparatus <NUM> as AP <NUM>) on an individual-RU (or physical-RU) basis to generate a plurality of processed bit sequences. For instance, processor <NUM> may parse, by a parser of processor <NUM> (e.g., the RU parser in design <NUM>), the plurality of encoded bit sequences to a plurality of interleavers of processor <NUM> (e.g., the RU<NUM> - RUn interleavers in design <NUM>) each of which corresponding to a respective one of the plurality of RUs. Additionally, processor <NUM> may interleave, by each of the plurality of interleavers, a respective encoded bit sequence from the plurality of encoded bit sequences to provide a respective interleaved bit sequence to a respective one of a plurality of tone mappers of processor <NUM> (e.g., the RU<NUM> - RUn tone mappers in design <NUM>) each of which corresponding to a respective one of the plurality of RUs. Moreover, processor <NUM> may tone map, by each of the plurality of tone mappers, the respective interleaved bit sequence to provide a respective processed bit sequence of the plurality of processed bit sequences. Afterwards, processor <NUM> may transmit, via transceiver <NUM>, the plurality of processed bit sequences to apparatus <NUM> over the plurality of RUs.

In some implementations, the plurality of interleavers may include BCC interleavers. Moreover, the plurality of tone mappers may include LDPC tone mappers.

In some implementations, the interleaver parameters and the tone mapper parameters may include interleaver parameters and tone mapper parameters specified in IEEE <NUM>1ax specification for Wi-Fi (e.g., the parameters specified in Table <NUM>-<NUM> and Table <NUM>-<NUM> of the IEEE <NUM>. 11ax specification).

<FIG> illustrates an example process <NUM> in accordance with an implementation of the present disclosure. Process <NUM> may represent an aspect of implementing various proposed designs, concepts, schemes, systems and methods described above. More specifically, process <NUM> may represent an aspect of the proposed concepts and schemes pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in wireless communications in accordance with the present disclosure. Process <NUM> may include one or more operations, actions, or functions as illustrated by one or more of blocks <NUM>, <NUM> and <NUM>. Although illustrated as discrete blocks, various blocks of process <NUM> may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process <NUM> may be executed in the order shown in <FIG> or, alternatively in a different order. Furthermore, one or more of the blocks/sub-blocks of process <NUM> may be executed repeatedly or iteratively. Process <NUM> may be implemented by or in apparatus <NUM> and apparatus <NUM> as well as any variations thereof. Process <NUM> may begin at block <NUM>.

At <NUM>, process <NUM> may involve, e.g. preferably by processor <NUM> of apparatus <NUM> (e.g., implemented in or as STA), performing joint encoding of a plurality of information bits to generate a plurality of encoded bit sequences. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve, e.g. preferably by processor <NUM>, processing the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to a plurality of RUs, e.g. preferably allocated to apparatus <NUM> (e.g., by apparatus <NUM> implemented in or as AP <NUM>), on either or both of an aggregate-RU basis and an individual-RU basis to generate a plurality of processed bit sequences. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve, e.g. preferably by processor <NUM>, transmitting, e.g. preferably via transceiver <NUM>, the plurality of processed bit sequences, e.g. preferably to apparatus <NUM>, over the plurality of RUs.

In some implementations, in processing the plurality of encoded bit sequences, process <NUM> may involve, e.g. preferably by processor <NUM>, interleaving and tone mapping the encoded bit sequences on the aggregate-RU basis by performing certain operations. For instance, process <NUM> may involve, e.g. preferably by processor <NUM>, interleaving, e.g. preferably by an interleaver of processor <NUM>, the plurality of encoded bit sequences with respect to an aggregate of the plurality of RUs to provide a plurality of interleaved bit sequences. Additionally, process <NUM> may involve, e.g. preferably by processor <NUM>, tone mapping, e.g. preferably by a tone mapper of processor <NUM>, the plurality of interleaved bit sequences with respect to the aggregate of the plurality of RUs to provide the plurality of processed bit sequences. Moreover, process <NUM> may involve, e.g. preferably by processor <NUM>, parsing, e.g. preferably by a parser of processor <NUM>, the plurality of processed bit sequences.

In some implementations, in interleaving the plurality of encoded bit sequences, process <NUM> may involve, e.g. preferably by processor <NUM>, interleaving, e.g. preferably by a BCC interleaver of processor <NUM>, the plurality of encoded bit sequences with respect to one or more sizes of RUs with corresponding one or more interleaver parameters.

In some implementations, in tone mapping the plurality of interleaved bit sequences, process <NUM> may involve, e.g. preferably by processor <NUM>, tone mapping, e.g. preferably by an LDPC tone mapper of processor <NUM>, the plurality of interleaved bit sequences with respect to one or more sizes of RUs with corresponding one or more tone mapper parameters.

In some implementations, the one or more sizes of RUs may include a <NUM>-tone RU and a <NUM>-tone RU. In such cases, the one or more tone mapper parameters comprise a distance between tones being <NUM> (DTM = <NUM>).

In some implementations, in processing the plurality of encoded bit sequences, process <NUM> may involve, e.g. preferably by processor <NUM>, interleaving and tone mapping the encoded bit sequences on the individual-RU basis by performing certain operations. For instance, process <NUM> may involve, e.g. preferably by processor <NUM>, parsing, e.g. preferably by a parser of processor <NUM>, the plurality of encoded bit sequences to a plurality of interleavers, e.g. preferably of processor <NUM>, each of which corresponding to a respective one of the plurality of RUs. Moreover, process <NUM> may involve, e.g. preferably by processor <NUM>, interleaving, by each of the plurality of interleavers, a respective encoded bit sequence from the plurality of encoded bit sequences to provide a respective interleaved bit sequence to a respective one of a plurality of tone mappers, e.g. preferably of processor <NUM>, each of which corresponding to a respective one of the plurality of RUs. Furthermore, process <NUM> may involve, e.g. preferably by processor <NUM>, tone mapping, by each of the plurality of tone mappers, the respective interleaved bit sequence to provide a respective processed bit sequence of the plurality of processed bit sequences.

In some implementations, in parsing the plurality of encoded bit sequences, process <NUM> may involve, e.g. preferably by processor <NUM>, parsing the plurality of encoded bit sequences with respect to one or more sizes of RUs with corresponding interleaver parameters and tone mapper parameters.

In some implementations, the plurality of interleavers may include BCC interleavers. Moreover, the plurality of tone mappers may include LDPC tone mappers. In such cases, the interleaver parameters and the tone mapper parameters may include interleaver parameters and tone mapper parameters specified in IEEE <NUM> ax specification for Wi-Fi (e.g., the parameters specified in Table <NUM>-<NUM> and Table <NUM>-<NUM> of the IEEE <NUM>. 11ax specification).

<FIG> illustrates an example process <NUM> in accordance with an implementation of the present invention. Process <NUM> may represent an aspect of implementing various proposed designs, concepts, schemes, systems and methods described above. More specifically, process <NUM> may represent an aspect of the proposed concepts and schemes pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in wireless communications in accordance with the present invention. Process <NUM> may include one or more operations, actions, or functions as illustrated by one or more of blocks <NUM>, <NUM> and <NUM> as well as sub-blocks <NUM>, <NUM> and <NUM>. Although illustrated as discrete blocks, various blocks of process <NUM> may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process <NUM> may be executed in the order shown in <FIG> or, alternatively in a different order. Furthermore, one or more of the blocks/sub-blocks of process <NUM> may be executed repeatedly or iteratively. Process <NUM> may be implemented by or in apparatus <NUM> and apparatus <NUM> as well as any variations thereof. Solely for illustrative purposes and without limiting the scope, process <NUM> is described below in the context of apparatus <NUM> implemented in or as STA <NUM> and apparatus <NUM> implemented in or as AP <NUM> of a wireless network such as a WLAN in network environment <NUM> in accordance with one or more of IEEE <NUM> standards. Process <NUM> may begin at block <NUM>.

At <NUM>, process <NUM> involves processor <NUM> of apparatus <NUM> performing joint encoding of a plurality of information bits to generate a plurality of encoded bit sequences. Process <NUM> proceeds from <NUM> to <NUM>.

At <NUM>, process <NUM> involves processor <NUM> processing the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to a plurality of RUs allocated to apparatus <NUM> (e.g., by apparatus <NUM> as AP <NUM>) on an aggregate-RU basis to generate a plurality of processed bit sequences, as represented by <NUM>, <NUM> and <NUM>. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> transmitting, via transceiver <NUM>, the plurality of processed bit sequences to apparatus <NUM> over the plurality of RUs.

At <NUM>, process <NUM> involves processor <NUM> interleaving, by an interleaver of processor <NUM>, the plurality of encoded bit sequences with respect to an aggregate of the plurality of RUs to provide a plurality of interleaved bit sequences. Process <NUM> proceeds from <NUM> to <NUM>.

At <NUM>, process <NUM> involves processor <NUM> tone mapping, by a tone mapper of processor <NUM>, the plurality of interleaved bit sequences with respect to the aggregate of the plurality of RUs to provide the plurality of processed bit sequences. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> parsing, by a parser of processor <NUM>, the plurality of processed bit sequences.

In some implementations, in interleaving the plurality of encoded bit sequences, process <NUM> may involve processor <NUM> interleaving, by a BCC interleaver of processor <NUM>, the plurality of encoded bit sequences with respect to one or more sizes of RUs with corresponding one or more interleaver parameters.

In some implementations, in tone mapping the plurality of interleaved bit sequences, process <NUM> may involve processor <NUM> tone mapping, by an LDPC tone mapper of processor <NUM>, the plurality of interleaved bit sequences with respect to one or more sizes of RUs with corresponding one or more tone mapper parameters.

<FIG> illustrates an example process <NUM> in accordance with an implementation of the present disclosure. Process <NUM> may represent an aspect of implementing various proposed designs, concepts, schemes, systems and methods described above. More specifically, process <NUM> may represent an aspect of the proposed concepts and schemes pertaining to joint encoding schemes with interleaver and tone mapper for multi-RU operation in wireless communications in accordance with the present disclosure. Process <NUM> may include one or more operations, actions, or functions as illustrated by one or more of blocks <NUM>, <NUM> and <NUM> as well as sub-blocks <NUM>, <NUM> and <NUM>. Although illustrated as discrete blocks, various blocks of process <NUM> may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process <NUM> may be executed in the order shown in <FIG> or, alternatively in a different order. Furthermore, one or more of the blocks/sub-blocks of process <NUM> may be executed repeatedly or iteratively. Process <NUM> may be implemented by or in apparatus <NUM> and apparatus <NUM> as well as any variations thereof. Solely for illustrative purposes and without limiting the scope, process <NUM> is described below in the context of apparatus <NUM> implemented in or as STA <NUM> and apparatus <NUM> implemented in or as AP <NUM> of a wireless network such as a WLAN in network environment <NUM> in accordance with one or more of IEEE <NUM> standards. Process <NUM> may begin at block <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> of apparatus <NUM> performing joint encoding of a plurality of information bits to generate a plurality of encoded bit sequences. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> processing the plurality of encoded bit sequences by interleaving and tone mapping the encoded bit sequences with respect to a plurality of RUs allocated to apparatus <NUM> (e.g., by apparatus <NUM> as AP <NUM>) on an individual-RU basis to generate a plurality of processed bit sequences, as represented by <NUM>, <NUM> and <NUM>. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> parsing, by a parser of processor <NUM>, the plurality of encoded bit sequences to a plurality of interleavers of processor <NUM> each of which corresponding to a respective one of the plurality of RUs. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> interleaving, by each of the plurality of interleavers, a respective encoded bit sequence from the plurality of encoded bit sequences to provide a respective interleaved bit sequence to a respective one of a plurality of tone mappers of processor <NUM> each of which corresponding to a respective one of the plurality of RUs. Process <NUM> may proceed from <NUM> to <NUM>.

At <NUM>, process <NUM> may involve processor <NUM> tone mapping, by each of the plurality of tone mappers, the respective interleaved bit sequence to provide a respective processed bit sequence of the plurality of processed bit sequences.

In some implementations, in parsing the plurality of encoded bit sequences, process <NUM> may involve processor <NUM> parsing the plurality of encoded bit sequences with respect to one or more sizes of RUs with corresponding interleaver parameters and tone mapper parameters.

Claim 1:
A method, comprising:
performing joint encoding of a plurality of information bits to generate a plurality of encoded bits (<NUM>); and
processing the plurality of encoded bits by interleaving and tone mapping the encoded bits with respect to a plurality of resource units, in the following also referred to as RUs, on an aggregate-RU basis to generate a plurality of processed bits (<NUM>),
wherein the processing of the plurality of encoded bits comprises interleaving and tone mapping the encoded bits on the aggregate-RU basis (<NUM>) by:
interleaving, by an interleaver, the plurality of encoded bits with respect to an aggregate of the plurality of RUs to provide a plurality of interleaved bits (<NUM>); and
tone mapping, by a tone mapper, the plurality of interleaved bits with respect to the aggregate of the plurality of RUs to provide the plurality of processed bits (<NUM>),
characterized in that
the tone mapping of the plurality of interleaved bits comprises tone mapping, by the tone mapper, the plurality of interleaved bits with respect to at least two different sizes of RUs with corresponding one or more tone mapper parameters, wherein:
when the at least two different sizes of RUs comprise a <NUM>-tone RU and a <NUM>-tone RU, the one or more tone mapper parameters comprise a distance between tones being <NUM>, or
when the at least two different sizes of RUs comprise a <NUM>-tone RU and a <NUM>-tone RU, the one or more tone mapper parameters comprise a distance between tones being <NUM>; and/or
the interleaving of the plurality of encoded bits comprises interleaving, by the interleaver, the plurality of encoded bits with respect to at least two different sizes of RUs with corresponding one or more interleaver parameters, wherein when the at least two different sizes of RUs comprise a <NUM>-tone RU and a <NUM>-tone RU for a total of <NUM> data subcarriers, the one or more interleaver parameters comprise a number of interleaver matrix columns being <NUM> and a number of interleaver matrix rows being a multiple of <NUM>.