Patent Description:
A zero crossing point detection-type frequency calculation is known as a technique of detecting a system frequency of a power system. The zero crossing point detection-type frequency calculation can take measurement data only in intervals synchronized with the system frequency; ordinarily, a filter of a relatively long time constant of <NUM> msec or more has been provided to acquire resistance to system disturbances. Therefore, for example, rapid output tracking for a change of the system frequency such as tracking with a delay of <NUM> msec or less, etc., is difficult.

Also, a frequency calculation using PLL (Phase Locked Loop) using a DQ transformation also is known. Such a frequency calculation using PLL can be used as a good frequency detector if there is no trouble at the power system side, and the system frequency can be tracked more quickly than the zero crossing point detection-type frequency calculation. However, there are cases where the calculated frequency temporarily oscillates greatly when a phase jump occurs in the system voltage.

Therefore, in a system frequency detector, it is desirable to be able to quickly track the change of the system frequency and to be able to suppress an erroneous detection of the system frequency even when a system disturbance occurs.

Embodiments of the invention provide a system frequency detector in which the change of the system frequency can be quickly tracked and an erroneous detection of the system frequency can be suppressed even when a system disturbance occurs.

According to an embodiment of the invention, a system frequency detector is provided and includes: an orthogonal coordinate signal generator generating an orthogonal two-phase voltage signal from a three-phase voltage signal of three-phase alternating current power of a power system by converting the three-phase voltage signal into a two-phase voltage signal orthogonal to the three-phase voltage signal, converting the two-phase voltage signal into a voltage signal of a rotating coordinate system, calculating a moving average of the voltage signal of the rotating coordinate system, and performing an inverse transformation of the voltage signal of the rotating coordinate system after calculating the moving average; and a frequency calculator including an angular frequency calculator calculating an angular frequency of the power system based on the two-phase voltage signal after calculating the moving average generated by the orthogonal coordinate signal generator, and an arithmetic unit calculating a system frequency of the power system from the angular frequency by multiplying the angular frequency by <NUM>/2π, wherein the frequency calculator further includes a rate limiter that is provided in series with the arithmetic unit and limits a change of the system frequency equal to or greater than a prescribed change rate.

According to embodiments of the invention, a system frequency detector is provided in which the change of the system frequency can be quickly tracked and an erroneous detection of the system frequency can be suppressed even when a system disturbance occurs.

Embodiments will now be described with reference to the drawings.

The drawings are schematic and conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values. The dimensions and/or the proportions may be illustrated differently among drawings even in the case where the same portion is illustrated.

In the specification and drawings, components similar to those described previously or illustrated in an antecedent drawing are marked with the same reference numerals; and a detailed description is omitted as appropriate.

<FIG> is a block diagram schematically illustrating a system frequency detector according to a first embodiment.

As illustrated in <FIG>, the system frequency detector <NUM> includes an orthogonal coordinate signal generator <NUM> and a frequency calculator <NUM>. The system frequency detector <NUM> detects the system frequency of a power system of three-phase alternating current power.

For example, the system frequency detector <NUM> is used in a power conversion device in which a distributed power source such as solar power generation, wind power generation, or the like is connected to a power system, etc. However, applications of the system frequency detector <NUM> are not limited thereto. The system frequency detector <NUM> can be used in any device in which it is necessary to detect the system frequency of a power system of three-phase alternating current power.

The orthogonal coordinate signal generator <NUM> generates orthogonal two-phase voltage signals Vα' and Vβ' from three-phase voltage signals Va, Vb, and Vc of the three-phase alternating current power of the power system. For example, the three-phase voltage signals Va, Vb, and Vc are detected by a voltage detector or the like and are input to the orthogonal coordinate signal generator <NUM>. For example, the three-phase voltage signals Va, Vb, and Vc are instantaneous values of a three-phase alternating current voltage input at a prescribed sampling interval.

The orthogonal coordinate signal generator <NUM> includes a three-phase to two-phase converter <NUM>, a rotating coordinate converter <NUM>, moving average filters <NUM> and <NUM>, and an inverse converter <NUM>.

The three-phase to two-phase converter <NUM> converts the three-phase voltage signals Va, Vb, and Vc into two-phase voltage signals Vα and Vβ of an α-phase and a β-phase by performing an α-β transform (a Clarke transformation).

The two-phase voltage signals Vα and Vβ are input to the rotating coordinate converter <NUM>, and a nominal phase θn obtained by integrating a nominal angular frequency ωn of the power system is input to the rotating coordinate converter <NUM>. The rotating coordinate converter <NUM> performs a rotating coordinate transformation of the voltage signals Vα and Vβ of the orthogonal two-axis coordinates into voltage signals Vd and Vq of a coordinate system (dq coordinates) synchronized with the phase θn by a so-called dq transformation (a Park transformation). The voltage signal Vd is a voltage signal of the d-axis component of the three-phase alternating current power (the voltage signals Va, Vb, and Vc) of the power system, and the voltage signal Vq is a voltage signal of the q-axis component of the three-phase alternating current power (the voltage signals Va, Vb, and Vc) of the power system.

The moving average filter <NUM> outputs a voltage signal Vd' after the moving average calculation by calculating the moving average of the voltage signal Vd. Similarly, the moving average filter <NUM> outputs a voltage signal Vq' after the moving average calculation by calculating the moving average of the voltage signal Vq. Thus, the moving average filters <NUM> and <NUM> suppress the high frequency components of the voltage signals Vd and Vq by calculating the moving averages of the voltage signals Vd and Vq. For example, the moving average filters <NUM> and <NUM> suppress the harmonic components included in the voltage signals Vd and Vq. Thereby, for example, the undesirable effects on the detection of the system frequency due to trouble at the power system side such as voltage imbalance of the three phases, harmonics, noise, etc., can be suppressed.

By performing an inverse transformation of the voltage signal Vd' and Vq' of the rotating coordinate system into an orthogonal two-axis coordinate system, the inverse converter <NUM> converts the voltage signal Vd' and Vq' into the voltage signals Vα' and Vβ' of the orthogonal two-axis coordinates after the moving average calculation. Thereby, the orthogonal coordinate signal generator <NUM> generates the orthogonal two-phase voltage signals Vα' and Vβ' from the three-phase voltage signals Va, Vb, and Vc.

The frequency calculator <NUM> calculates a system frequency f of the power system based on the two-phase voltage signals Vα' and Vβ' generated by the orthogonal coordinate signal generator <NUM>. By using a PLL (Phase-Locked-Loop) calculation, the frequency calculator <NUM> detects a synchronous phase θαβPLL synchronized with the voltage signals Vα' and Vβ' after the two-phase conversion and calculates the system frequency f of the power system from an angular frequency ω obtained in the detection process of the synchronous phase θαβPLL.

The frequency calculator <NUM> includes an angular frequency calculator AFP. The angular frequency calculator AFP includes, for example, arithmetic units <NUM>, <NUM>, and <NUM>, multipliers <NUM> and <NUM>, a subtractor <NUM>, arithmetic units <NUM> and <NUM>, an integrator <NUM>, adders <NUM> and <NUM>, an integrator <NUM>, an arithmetic unit <NUM>, and a subtractor <NUM>.

The arithmetic unit <NUM> calculates cosθn and sinθn from the two-phase voltage signals Vα' and Vβ'. The arithmetic unit <NUM> calculates cosθn by using the formula Vα'/√(Vα'<NUM> + Vβ'<NUM>), and calculates sinθn by using the formula Vβ'/√(Vα'<NUM> + Vβ'<NUM>). The arithmetic unit <NUM> inputs the calculated cosθn to the multiplier <NUM>, and inputs the calculated sinθn to the multiplier <NUM>.

The arithmetic unit <NUM> calculates sinθαβPLL based on the detected synchronous phase θαβPLL and inputs sinθαβPLL to the multiplier <NUM>.

The arithmetic unit <NUM> calculates cosθαβPLL based on the detected synchronous phase θαβPLL and inputs cosθαβPLL to the multiplier <NUM>.

The multiplier <NUM> multiplies the input cosθn and sinθαβPLL and inputs the multiplication result to the subtractor <NUM>.

The multiplier <NUM> multiplies the input sinθn and cosθαβPLL and inputs the multiplication result to the subtractor <NUM>.

The subtractor <NUM> calculates an error phase Δθ between the phase θn of the power system and the synchronous phase θαβPLL by calculating sinθn and cosθαβPLL - cosθn and sinθαβPLL. The frequency calculator <NUM> calculates the error phase Δθ as
Δθ = θn - θαβPLL ≈ sinθn and cosθαβPLL - cosθn and sinθαβPLL.

The arithmetic unit <NUM> multiplies the error phase Δθ by a proportional gain KP and inputs the multiplication result to the adder <NUM>.

The arithmetic unit <NUM> multiplies the error phase Δθ by an integral gain KI and inputs the multiplication result to the integrator <NUM>.

The integrator <NUM> integrates the multiplication result of the error phase Δθ and the integral gain KI and inputs the integral to the adder <NUM>.

The adder <NUM> adds the multiplication result of the arithmetic unit <NUM> and the integral of the integrator <NUM>. The arithmetic units <NUM> and <NUM>, the integrator <NUM>, and the adder <NUM> calculate a command value Δω of the angular frequency for setting the error phase Δθ to zero by so-called proportional-integral control.

The command value Δω of the angular frequency calculated by the adder <NUM> is input to the adder <NUM>, and the nominal angular frequency ωn of the power system is input to the adder <NUM>. The adder <NUM> calculates the angular frequency ω of the power system by adding the command value Δω of the angular frequency and the nominal angular frequency ωn of the power system. Thus, the angular frequency calculator AFP calculates the angular frequency ω by performing the proportional-integral control based on the two-phase voltage signals Vα' and Vβ'.

The integrator <NUM> calculates a synchronous phase θ from the angular frequency ω by integrating the angular frequency ω calculated by the adder <NUM>. The integrator <NUM> inputs the calculated synchronous phase θ to the subtractor <NUM>.

The arithmetic unit <NUM> calculates a correction value by multiplying the integration result of the integrator <NUM> by a constant Kφ. The constant Kφ is determined by Kφ = (Tω - TSP)/<NUM>. TSP is the sampling interval of the voltage signals Va, Vb, and Vc. Tω is the window length of the moving average filters <NUM> and <NUM>. Tω is represented by N·TSP, where N is the averaging number of the moving average filters <NUM> and <NUM>. The arithmetic unit <NUM> inputs the calculated correction value to the subtractor <NUM>.

The subtractor <NUM> corrects the synchronous phase θ by subtracting the correction value from the synchronous phase θ. The subtractor <NUM> calculates the synchronous phase θαβPLL by the correction.

The angular frequency calculator AFP synchronizes the synchronous phase θαβPLL with the phase θn of the power system by feeding back the detected synchronous phase θαβPLL to the arithmetic units <NUM> and <NUM>. Thus, based on the angular frequency ω, the angular frequency calculator AFP detects the synchronous phase θαβPLL synchronized with the two-phase voltage signals Vα' and Vβ' after calculating the moving averages, calculates the error phase Δθ between the nominal phase θn of the power system and the synchronous phase θαβPLL, and calculates the angular frequency ω to cause the error phase Δθ to be zero. For example, the configuration of the PLL of the angular frequency calculator AFP (the frequency calculator <NUM>) of the example may be called αβEPMAFPLL (αβ Enhanced Pre-filtering Moving Average Filter PLL).

The frequency calculator <NUM> further includes an arithmetic unit <NUM> and a rate limiter <NUM>. The frequency calculator <NUM> calculates the system frequency f of the power system from the calculated angular frequency ω. The adder <NUM> inputs the calculated angular frequency ω to the integrator <NUM> and inputs the angular frequency ω to the rate limiter <NUM>.

The rate limiter <NUM> limits a change of the angular frequency ω equal to or greater than a prescribed change rate. The rate limiter <NUM> inputs, to the arithmetic unit <NUM>, the angular frequency ω that is less than the prescribed change rate or the angular frequency ω after being limited to the prescribed change rate.

The arithmetic unit <NUM> calculates the system frequency f from the angular frequency ω by multiplying the angular frequency ω by <NUM>/<NUM>π. The rate limiter <NUM> is provided in series with the arithmetic unit <NUM>. By limiting a change of the angular frequency ω equal to or greater than the prescribed change rate, the rate limiter <NUM> limits a change of the system frequency f equal to or greater than a prescribed change rate. For example, the rate limiter <NUM> suppresses a change of the system frequency f equal to or greater than <NUM>/sec. The rate limiter <NUM> suppresses an abrupt fluctuation of the system frequency f.

Thus, the frequency calculator <NUM> calculates the system frequency f of the power system from the two-phase voltage signals Vα' and Vβ'. The system frequency detector <NUM> detects the system frequency f of the power system from the three-phase voltage signals Va, Vb, and Vc.

As described above, the system frequency detector <NUM> according to the embodiment includes the rate limiter <NUM> that limits a change of the system frequency f equal to or greater than the prescribed change rate. Thereby, even when a phase jump or the like occurs in the power system, an abrupt fluctuation of the system frequency f can be suppressed, and the error of the calculation of the system frequency f can be reduced. Also, the calculation of the system frequency f is an open loop; therefore, effects on the speed of the system voltage phase tracking by PLL can be suppressed even when the rate limiter <NUM> is provided in the part calculating the system frequency f. Accordingly, the system frequency detector <NUM> can be provided in which the change of the system frequency f can be quickly tracked, and an erroneous detection of the system frequency f can be suppressed even when a system disturbance occurs.

<FIG> is a block diagram schematically illustrating a modification of the system frequency detector according to the first embodiment.

Components that are substantially the same functionally and configurationally as those of the embodiments described above are marked with the same reference numerals, and a detailed description is omitted.

In the system frequency detector 10a as illustrated in <FIG>, the rate limiter <NUM> is provided after the arithmetic unit <NUM> that multiplies <NUM>/<NUM>π. Thus, the rate limiter <NUM> may directly limit a change of the system frequency f equal to or greater than the prescribed change rate after being converted from the angular frequency ω.

Thus, the rate limiter <NUM> may be provided before the arithmetic unit <NUM> or may be provided after the arithmetic unit <NUM>. The rate limiter <NUM> may limit a change of the system frequency f equal to or greater than the prescribed change rate by limiting a change of the angular frequency ω equal to or greater than the prescribed change rate or may directly limit a change of the system frequency f equal to or greater than the prescribed change rate. The configuration of the rate limiter <NUM> may be any configuration in which the rate limiter <NUM> is provided in series with the arithmetic unit <NUM> and can limit a change of the system frequency f equal to or greater than the prescribed change rate.

<FIG> is a block diagram schematically illustrating a system frequency detector according to a second embodiment.

In the system frequency detector 10b as illustrated in <FIG>, the frequency calculator <NUM> further includes a low-pass filter <NUM>. The low-pass filter <NUM> is provided in series with the arithmetic unit <NUM>. For example, the low-pass filter <NUM> is provided between the arithmetic unit <NUM> and the rate limiter <NUM>.

The low-pass filter <NUM> suppresses the high frequency components of the angular frequency ω. The low-pass filter <NUM> attenuates frequency components of the angular frequency ω that are greater than a prescribed frequency. In other words, the low-pass filter <NUM> suppresses an abrupt fluctuation of the angular frequency ω. For example, the low-pass filter <NUM> may use a moving average filter. The low-pass filter <NUM> inputs, to the arithmetic unit <NUM>, the angular frequency ω after the high frequency components are suppressed.

The low-pass filter <NUM> is provided in series with the arithmetic unit <NUM>. The low-pass filter <NUM> suppresses the high frequency components of the system frequency f by suppressing the high frequency components of the angular frequency ω. The low-pass filter <NUM> suppresses an abrupt fluctuation of the system frequency f.

Thus, by providing the low-pass filter <NUM>, even when a phase jump or the like occurs in the power system, an abrupt fluctuation of the system frequency f can be suppressed, and the error of the calculation of the system frequency f can be reduced further.

The low-pass filter <NUM> is not limited to being between the arithmetic unit <NUM> and the rate limiter <NUM>, and may be provided before the rate limiter <NUM> or may be provided after the arithmetic unit <NUM>. The configuration of the low-pass filter <NUM> may be any configuration in which the low-pass filter <NUM> is provided in series with the arithmetic unit <NUM> and can suppress the high frequency components of the system frequency f.

<FIG> is a block diagram schematically illustrating a system frequency detector according to a third embodiment.

In the system frequency detector 10c as illustrated in <FIG>, the frequency calculator <NUM> further includes subtractors <NUM> and <NUM>. The subtractor <NUM> is connected to the input and output sides of the rate limiter <NUM>. The subtractor <NUM> subtracts the output value of the rate limiter <NUM> from the input value of the rate limiter <NUM>. In other words, the subtractor <NUM> calculates the difference between the input value and the output value of the rate limiter <NUM>. The difference between the output value of the rate limiter <NUM> and the input value of the rate limiter <NUM> is calculated by the subtractor <NUM> when the calculated value of the angular frequency ω abruptly increases, the angular frequency ω is limited by the rate limiter <NUM>, and the output value of the rate limiter <NUM> becomes less than the input value of the rate limiter <NUM>. The subtractor <NUM> inputs the calculation result of the difference to the subtractor <NUM>.

The subtractor <NUM> is provided between the arithmetic unit <NUM> and the integrator <NUM> of the angular frequency calculator AFP. The subtractor <NUM> subtracts the calculation result of the difference of the subtractor <NUM> from the multiplication result of the arithmetic unit <NUM> multiplying the error phase Δθ by the integral gain KI. In other words, when the rate limiter <NUM> limits the angular frequency ω, the subtractor <NUM> subtracts the amount limited by the rate limiter <NUM> from the calculation of the integration operation of the proportional-integral control.

Thus, in the frequency calculator <NUM> of the system frequency detector 10c, the subtractors <NUM> and <NUM> are provided and feed back the output-input difference of the rate limiter <NUM> to the calculation of the proportional-integral control of the angular frequency calculator AFP. Thereby, even when a phase jump or the like occurs in the power system, an abrupt fluctuation of the system frequency f can be more reliably suppressed, and the error of the calculation of the system frequency f can be reduced further. For example, such a control of the feedback may be called Anti reset wind up.

<FIG> is a block diagram schematically illustrating a system frequency detector according to a fourth embodiment.

In the system frequency detector 10d as illustrated in <FIG>, the frequency calculator <NUM> further includes a saturation limiter <NUM>, a switching element <NUM>, and a switching circuit <NUM>.

The saturation limiter <NUM> is provided in parallel with the rate limiter <NUM>. In the example, the rate limiter <NUM> is provided between the adder <NUM> and the low-pass filter <NUM>; similarly to the rate limiter <NUM>, the saturation limiter <NUM> also is provided between the adder <NUM> and the low-pass filter <NUM>. For example, when the rate limiter <NUM> is provided between the low-pass filter <NUM> and the arithmetic unit <NUM>, it is sufficient for the saturation limiter <NUM> also to be similarly provided between the low-pass filter <NUM> and the arithmetic unit <NUM>.

The switching element <NUM> is provided between the rate limiter <NUM> and the arithmetic unit <NUM> (the low-pass filter <NUM>) and between the saturation limiter <NUM> and the arithmetic unit <NUM> (the low-pass filter <NUM>). The switching element <NUM> selectively switches between a state in which the rate limiter <NUM> is connected in series to the arithmetic unit <NUM> and a state in which the saturation limiter <NUM> is connected in series to the arithmetic unit <NUM>.

In the state in which the switching element <NUM> connects the rate limiter <NUM> to the arithmetic unit <NUM> in series, the subtractor <NUM> is connected to the input and output sides of the rate limiter <NUM>. Accordingly, in this state, the output-input difference of the rate limiter <NUM> is fed back to the calculation of the proportional-integral control.

On the other hand, in the state in which the switching element <NUM> connects the saturation limiter <NUM> to the arithmetic unit <NUM> in series, the subtractor <NUM> is connected to the input and output sides of the saturation limiter <NUM>. Accordingly, in this state, the output-input difference of the saturation limiter <NUM> is fed back to the calculation of the proportional-integral control.

The saturation limiter <NUM> limits a change of the system frequency f equal to or greater than a prescribed value with respect to the nominal system frequency fn by limiting a change of the angular frequency ω equal to or greater than a prescribed value with respect to the nominal angular frequency ωn. The prescribed value (the prescribed absolute value) is, for example, <NUM>. For example, when the nominal system frequency fn is <NUM>, the saturation limiter <NUM> limits the change of the system frequency f to be within the range of <NUM>±<NUM>.

As described above, for example, the rate limiter <NUM> suppresses a change of the system frequency f equal to or greater than <NUM>/sec. Thus, the prescribed value (e.g., <NUM>) of the change of the system frequency f limited by the saturation limiter <NUM> is, for example, less than the frequency (e.g., <NUM>) of the change rate per unit time (<NUM> second) of the rate limiter <NUM>.

The switching circuit <NUM> selectively switches between the first state in which the rate limiter <NUM> is used and the second state in which the saturation limiter <NUM> is used. For example, the switching circuit <NUM> selectively switches between the first state and the second state by controlling the switching of the paths by the switching element <NUM>.

However, the switching between the first state and the second state is not limited thereto. For example, the first state and the second state may be switched by selectively operating the rate limiter <NUM> and the saturation limiter <NUM> by selectively supplying power to the rate limiter <NUM> and the saturation limiter <NUM>, or the first state and the second state may be switched by selectively operating the rate limiter <NUM> and the saturation limiter <NUM> by selectively transmitting control signals to the rate limiter <NUM> and the saturation limiter <NUM>. The switching element <NUM> is omissible in such cases. It is sufficient for the switching element <NUM> to be provided as necessary.

<FIG> is a block diagram schematically illustrating the switching circuit.

As illustrated in <FIG>, the switching circuit <NUM> includes a differential circuit <NUM>, an absolute value calculation circuit <NUM>, and a determination circuit <NUM>. The voltage signal Vd that is calculated by the rotating coordinate converter <NUM> is input to the switching circuit <NUM>.

The differential circuit <NUM> calculates a differential of the voltage signal Vd. In other words, the differential circuit <NUM> calculates the slope of the voltage signal Vd. The absolute value calculation circuit <NUM> calculates the absolute value of the differential of the voltage signal Vd calculated by the differential circuit <NUM>.

The determination circuit <NUM> determines whether or not the absolute value of the differential of the voltage signal Vd is equal to or greater than a prescribed value. When a phase jump occurs in the power system, the voltage signal Vd of the d-axis component of the three-phase alternating current power of the power system abruptly changes (referring to <FIG>). Therefore, when the absolute value of the differential of the voltage signal Vd is equal to or greater than the prescribed value, it can be considered that a phase jump has occurred in the power system.

The determination circuit <NUM> switches the path of the switching element <NUM>. When the absolute value of the differential of the voltage signal Vd is less than the prescribed value, the determination circuit <NUM> sets the switching element <NUM> to a state in which the output of the rate limiter <NUM> is connected to the low-pass filter <NUM>. In other words, the determination circuit <NUM> selects the first state in which the rate limiter <NUM> is used when it is determined that a phase jump has not occurred in the power system.

On the other hand, when the absolute value of the differential of the voltage signal Vd is equal to or greater than the prescribed value, the determination circuit <NUM> sets the switching element <NUM> to a state in which the output of the saturation limiter <NUM> is connected to the low-pass filter <NUM>. In other words, the determination circuit <NUM> selects the second state in which the saturation limiter <NUM> is used when it is determined that a phase jump has occurred in the power system.

Thus, the switching circuit <NUM> selects the first state when the absolute value of the differential of the voltage signal Vd of the active component is less than the prescribed value, and selects the second state when the absolute value of the differential of the voltage signal Vd of the active component is equal to or greater than the prescribed value.

When switching from the first state to the second state, for example, the determination circuit <NUM> returns the second state to the first state after a prescribed period of time has elapsed from the timing of the switching from the first state to the second state. For example, after switching from the first state to the second state, the determination circuit <NUM> may return the second state to the first state by responding to the absolute value of the differential of the voltage signal Vd returning to be less than the prescribed value.

<FIG> are graphs schematically illustrating an example of an operation of the system frequency detector.

The vertical axis of <FIG> is an example of the three-phase voltage signal Va.

The vertical axis of <FIG> is an example of the three-phase voltage signal Vb.

The vertical axis of <FIG> is an example of the three-phase voltage signal Vc.

The vertical axis of <FIG> is an example of the voltage signal Vd of the rotating coordinate system.

The vertical axis of <FIG> is an example of a reference system frequency f calculated by the arithmetic unit <NUM> from the angular frequency ω calculated by the adder <NUM> as-is without passing through the low-pass filter <NUM>, etc..

The vertical axis of <FIG> is an example of the system frequency f calculated by the configuration of the system frequency detector 10c.

The vertical axis of <FIG> is an example of the system frequency f calculated by the configuration of the system frequency detector 10d.

<FIG> illustrate an example when a phase jump of about <NUM> degrees occurs at a time T1. Also, the actual system frequency of the power system is set to <NUM> in <FIG>.

When a phase jump occurs as illustrated in <FIG>, the voltage signal Vd of the d-axis component of the three-phase alternating current power of the power system abruptly changes.

As illustrated in <FIG>, when the system frequency f is calculated without using the low-pass filter <NUM>, etc., a mismeasurement of about <NUM> occurs when the phase jump occurs.

Conversely, as illustrated in <FIG>, in the system frequency detector 10c in which the output-input difference of the rate limiter <NUM> is fed back to the calculation of the proportional-integral control, the mismeasurement can be suppressed to about <NUM> when the phase jump occurs.

Also, in the system frequency detector 10d that switches from the rate limiter <NUM> to the saturation limiter <NUM> when the occurrence of a phase jump is detected, the mismeasurement when the phase jump occurs can be suppressed further. In the system frequency detector 10d, the mismeasurement can be suppressed to about <NUM>. In other words, in the system frequency detector 10d, the mismeasurement of the system frequency f when the phase jump occurs can be suppressed to the width of the limit of the saturation limiter <NUM>.

Thereby, in the system frequency detector 10d, even when a phase jump or the like occurs in the power system, an abrupt fluctuation of the system frequency f can be more reliably suppressed, and the error of the calculation of the system frequency f can be reduced further.

<FIG> is a block diagram schematically illustrating a system frequency detector according to a fifth embodiment.

In the system frequency detector 10e as illustrated in <FIG>, the saturation limiter <NUM> of the system frequency detector 10d is replaced with a slow rate limiter <NUM>. The slow rate limiter <NUM> limits the change of the system frequency f at a lower change rate than the change rate of the rate limiter <NUM>.

In the example, the switching circuit <NUM> selectively switches between the first state in which the rate limiter <NUM> is used and the second state in which the slow rate limiter <NUM> is used. Similarly to the embodiments described above, the switching circuit <NUM> selects the first state when the absolute value of the differential of the voltage signal Vd of the active component is less than a prescribed value, and selects the second state when the absolute value of the differential of the voltage signal Vd of the active component is equal to or greater than the prescribed value.

Thus, even when switching from the rate limiter <NUM> to the slow rate limiter <NUM> when the occurrence of a phase jump is detected, similarly to when the saturation limiter <NUM> is provided, the mismeasurement when the phase jump occurs can be suppressed further compared to the configuration of the system frequency detector 10c that feeds back the output-input difference of the rate limiter <NUM> to the calculation of the proportional-integral control.

<FIG> is a block diagram schematically illustrating a system frequency detector according to a sixth embodiment.

In the system frequency detector 10f as illustrated in <FIG>, the saturation limiter <NUM> is provided in series with the rate limiter <NUM>. Also, in the system frequency detector 10f, the switching element <NUM> selectively switches between a state in which only the rate limiter <NUM> is connected in series to the arithmetic unit <NUM>, and a state in which the rate limiter <NUM>, the saturation limiter <NUM>, and the arithmetic unit <NUM> are connected in series.

In the state in which the switching element <NUM> connects only the rate limiter <NUM> to the arithmetic unit <NUM> in series, the subtractor <NUM> is connected to the input and output sides of the rate limiter <NUM>. Accordingly, in this state, the output-input difference of the rate limiter <NUM> is fed back to the calculation of the proportional-integral control.

On the other hand, in the state in which the switching element <NUM> connects the rate limiter <NUM>, the saturation limiter <NUM>, and the arithmetic unit <NUM> in series, the subtractor <NUM> is connected to the input and output sides of a series-connected unit of the rate limiter <NUM> and the saturation limiter <NUM>.

The switching circuit <NUM> selectively switches between the first state in which only the rate limiter <NUM> is used and the second state in which the series-connected unit of the rate limiter <NUM> and the saturation limiter <NUM> is used. For example, the switching circuit <NUM> selectively switches between the first state and the second state by controlling the switching of the paths by the switching element <NUM>.

However, the switching between the first state and the second state is not limited thereto. For example, the first state may be set by operating only the rate limiter <NUM>, and the second state may be set by operating the rate limiter <NUM> and the saturation limiter <NUM>. In such a case, the switching element <NUM> is omissible.

Similarly to the embodiments described above, the switching circuit <NUM> selects the first state when the absolute value of the differential of the voltage signal Vd of the active component is less than a prescribed value, and selects the second state when the absolute value of the differential of the voltage signal Vd of the active component is equal to or greater than the prescribed value.

The frequency that is limited by the saturation limiter <NUM> is set to be less than the frequency limited by the rate limiter <NUM>. Accordingly, in this state, substantially, the output of the saturation limiter <NUM> is used in the calculation of the system frequency f, and the output-input difference of the saturation limiter <NUM> is fed back to the calculation of the proportional-integral control. Therefore, effects similar to those of the system frequency detector 10d in which the saturation limiter <NUM> is provided in parallel with the rate limiter <NUM> can be obtained also in the system frequency detector 10f in which the saturation limiter <NUM> is provided in series with the rate limiter <NUM>.

Instead of the saturation limiter <NUM>, the slow rate limiter <NUM> may be provided in series with the rate limiter <NUM>. In such a case, effects similar to those of the system frequency detector 10e can be obtained.

<FIG> is a block diagram schematically illustrating a system frequency detector according to a seventh embodiment. In the system frequency detector <NUM> as illustrated in <FIG>, the saturation limiter <NUM> of the system frequency detector 10d is replaced with a sample-and-hold circuit <NUM>.

The sample-and-hold circuit <NUM> includes a sample mode in which the output signal is caused to track the input signal, and a hold mode in which the output signal is held to be substantially constant at a value of a prescribed timing.

The switching circuit <NUM> selectively switches between the first state in which the rate limiter <NUM> is used and the second state in which the sample-and-hold circuit <NUM> is used.

When the absolute value of the differential of the voltage signal Vd is less than a prescribed value and it is determined that a phase jump has not occurred in the power system, the switching circuit <NUM> (the determination circuit <NUM>) selects the first state in which the rate limiter <NUM> is used and operates the sample-and-hold circuit <NUM> in the sample mode.

When the absolute value of the differential of the voltage signal Vd is equal to or greater than the prescribed value and it is determined that a phase jump has occurred in the power system, the switching circuit <NUM> (the determination circuit <NUM>) selects the second state in which the sample-and-hold circuit <NUM> is used and switches the sample-and-hold circuit <NUM> from the sample mode to the hold mode. Thereby, the switching circuit <NUM> causes the sample-and-hold circuit <NUM> to maintain the signal (the angular frequency ω or the system frequency f) directly before the phase jump occurs in the power system.

Thus, even when switching from the rate limiter <NUM> to the sample-and-hold circuit <NUM> when the occurrence of a phase jump is detected, similarly to when the saturation limiter <NUM> is provided, the mismeasurement when the phase jump occurs can be suppressed further compared to the configuration of the system frequency detector 10c in which the output-input difference of the rate limiter <NUM> is fed back to the calculation of the proportional-integral control.

As described above, the mismeasurement of the system frequency f due to the occurrence of the phase jump can be more reliably suppressed by causing the sample-and-hold circuit <NUM> to maintain the signal directly before the phase jump occurs in the power system.

<FIG> is a block diagram schematically illustrating a system frequency detector according to an eighth embodiment. In the system frequency detector <NUM> as illustrated in <FIG>, the angular frequency calculator AFP of a frequency calculator 14a includes a rotating coordinate converter <NUM>, an integrator <NUM>, adders <NUM> and <NUM>, an arithmetic unit <NUM>, an integrator <NUM>, an arithmetic unit <NUM>, and a subtractor <NUM>.

The two-phase voltage signals Vα' and Vβ' are input to the rotating coordinate converter <NUM>, and the synchronous phase θPLL is input to the rotating coordinate converter <NUM>. The rotating coordinate converter <NUM> uses a so-called dq transformation (a Park transformation) to perform a rotating coordinate transformation of the voltage signals Vα' and Vβ' of the orthogonal two-axis coordinates into voltage signals vd and vq of a coordinate system (dq coordinates) synchronized with the synchronous phase θPLL.

The integrator <NUM> calculates the command value Δω of the angular frequency for setting the voltage signal vq of the q-axis component of the three-phase alternating current power of the power system to zero by multiplying the voltage signal vq by the integral gain KI and by integrating the multiplication result. The integrator <NUM> inputs the calculated command value Δω to the adder <NUM>.

The command value Δω of the angular frequency calculated by the integrator <NUM> is input to the adder <NUM>, and the nominal angular frequency ωn of the power system is input to the adder <NUM>. The adder <NUM> calculates the angular frequency ω of the power system by adding the command value Δω of the angular frequency and the nominal angular frequency ωn of the power system. The adder <NUM> inputs the calculated angular frequency ω to the adder <NUM>.

The arithmetic unit <NUM> multiplies the voltage signal vq by the proportional gain KP and inputs the multiplication result to the adder <NUM>.

The adder <NUM> corrects the angular frequency ω by adding the angular frequency ω calculated by the adder <NUM> and the multiplication result of the arithmetic unit <NUM>.

The integrator <NUM> calculates the synchronous phase θPLL that is synchronized with the voltage signals Vα' and Vβ' after the two-phase conversion from the angular frequency ω by integrating the angular frequency ω after being corrected by the adder <NUM>. The integrator <NUM> inputs the calculated synchronous phase θPLL to the subtractor <NUM>.

The arithmetic unit <NUM> calculates the correction value by multiplying the integration result of the integrator <NUM> by the constant Kφ. The arithmetic unit <NUM> inputs the calculated correction value to the subtractor <NUM>.

The subtractor <NUM> corrects the synchronous phase θPLL by subtracting the correction value from the synchronous phase θPLL. The subtractor <NUM> inputs the synchronous phase θPLL after the correction to the rotating coordinate converter <NUM>. As described above, the rotating coordinate converter <NUM> calculates the voltage signals vd and vq based on the synchronous phase θPLL after the correction.

Thus, the angular frequency calculator AFP of the frequency calculator 14a synchronizes the synchronous phase θPLL with the phase θn of the power system by feeding back the detected synchronous phase θPLL to the rotating coordinate converter <NUM> and by detecting the synchronous phase θPLL to cause the voltage signal vq of the q-axis component of the three-phase alternating current power of the power system to be zero. Based on the angular frequency ω, the angular frequency calculator AFP of the frequency calculator 14a generates the voltage signal vq of the q-axis component of the three-phase alternating current power of the power system and calculates the angular frequency ω to cause the voltage signal vq of the reactive component to be zero by detecting the synchronous phase θPLL synchronized with the two-phase voltage signals Vα' and Vβ' after calculating the moving averages and by performing a rotating coordinate transformation of the two-phase voltage signals Vα' and Vβ' after calculating the moving averages. For example, the configuration of the PLL of the angular frequency calculator AFP (the frequency calculator 14a) of the example may be called an EPMAFPLL (Enhanced Pre-filtering Moving Average Filter PLL).

Also, the frequency calculator 14a calculates the system frequency f of the power system from the calculated angular frequency ω. The frequency calculator 14a further includes a rate limiter <NUM> and an arithmetic unit <NUM>. The adder <NUM> inputs the calculated angular frequency ω to the integrator <NUM> and inputs the angular frequency ω to the rate limiter <NUM>.

The rate limiter <NUM> limits a change of the angular frequency ω equal to or greater than a prescribed change rate. The rate limiter <NUM> inputs, to the arithmetic unit <NUM>, the angular frequency ω that is less than the prescribed change rate or the angular frequency ω after being limited to the prescribed change rate. The arithmetic unit <NUM> calculates the system frequency f from the angular frequency ω by multiplying the angular frequency ω by <NUM>/<NUM>π. As described in the embodiments described above, the rate limiter <NUM> may be provided after the arithmetic unit <NUM>.

Thus, the configuration of the frequency calculator may be an EPMAFPLL configuration or may be an αβEPMAFPLL configuration. However, the configuration of the frequency calculator is not limited to these configurations. The configuration of the frequency calculator may be, for example, a PMAFPLL (Pre-filtering Moving Average Filter PLL) configuration in which the arithmetic unit <NUM> and the subtractor <NUM> are omitted from an EPMAFPLL configuration and the synchronous phase θPLL calculated by the integrator <NUM> is fed back to the rotating coordinate converter <NUM> as-is. Or, the configuration of the frequency calculator may be an EPMAFPLL Type-<NUM> configuration, etc., in which the integration result of the integrator <NUM> is multiplied by the constant Kφ, and the calculated correction value is fed back to the inverse converter <NUM> and the rotating coordinate converter <NUM> of the orthogonal coordinate signal generator <NUM>.

Also, an Anti reset wind up feedback control may be added to the EPMAFPLL configuration illustrated in <FIG>. In such a case, for example, it is sufficient for the integrator <NUM> to be divided into an arithmetic unit multiplying the integral gain KI by the voltage signal vq and an integrator integrating the multiplication result similarly to the example illustrated in <FIG>, etc., and for the output-input difference of the rate limiter <NUM> to be fed back to the calculation of the proportional-integral control by providing a subtractor between the arithmetic unit and the integrator.

Hereinabove, embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in the system frequency detectors <NUM> and 10a to <NUM> from known art, and such practice is within the scope of the invention as defined by the appended claims to the extent that similar effects can be obtained.

Claim 1:
A system frequency detector (<NUM>), comprising:
an orthogonal coordinate signal generator (<NUM>) generating an orthogonal two-phase voltage signal from a three-phase voltage signal of three-phase alternating current power of a power system by converting the three-phase voltage signal into a two-phase voltage signal orthogonal to the three-phase voltage signal, converting the two-phase voltage signal into a voltage signal of a rotating coordinate system, calculating a moving average of the voltage signal of the rotating coordinate system, and performing an inverse transformation of the voltage signal of the rotating coordinate system after calculating the moving average; and
a frequency calculator (<NUM>) including an angular frequency calculator (AFP) calculating an angular frequency of the power system based on the two-phase voltage signal after calculating the moving average generated by the orthogonal coordinate signal generator (<NUM>), and
an arithmetic unit (<NUM>) calculating a system frequency of the power system from the angular frequency by multiplying the angular frequency by <NUM>/<NUM>π,
the frequency calculator further including a rate limiter (<NUM>) provided in series with the arithmetic unit (<NUM>),
the rate limiter limiting a change of the system frequency equal to or greater than a prescribed change rate.