Patent Description:
Variable gain amplifiers (VGAs), for maintaining a desired level of output signals by adjusting gain, are widely used in radio frequency (RF) communication systems, in particular in transceivers receiving a signal which experiences rapid and wide variations in signal power.

In receivers such as those that may be used in various portable devices or base stations, it is often necessary to control the power of the demodulated signal for proper signal processing. Additionally, in transmitters such as those that may be used in various portable devices or base stations, it is also often useful to control the transmit power in order to avoid excessive interference from other equipment.

Reception and transmission power and gain control are typically performed by an automatic gain control (AGC) circuit using a VGA. It is generally desirable for the AGC to have high linearity and low noise, over a wide range of power levels, such that signals can be received and transmitted with little or no distortion. To achieve the desired AGC characteristics, the dB gain of the VGA should preferably be linearly changed according to a gain control signal over a wide dynamic range.

However, a VGA's performance may degrade significantly over a high dynamic range. For example, sensitivity of a VGA to low level signals may be reduced when the VGA is operating with a very high gain; on the other hand, the input signal may get lost in noise if there is insufficient gain for the VGA to amplify the input signal. Conventional VGA circuits have been found to exhibit deterioration in linearity at upper or lower ranges of gain.

Accordingly, solutions for achieving low noise, high linearity, and sufficient gain range for VGAs are desirable to provide adjustable gain in a variety of applications.

Document <CIT> relates to radio frequency (RF) receivers, and to the design and implementation of low-noise amplifiers (LNAs).

The invention discloses a hybrid VGA and a method for controlling a hybrid VGA, respectively, as provided in the appended independent claims. Preferred embodiments are set forth in the appended dependent claims.

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:.

In electronic circuit diagrams, conventional electronic components are labeled with conventional reference letters followed by a number indication the iteration of that element in the circuit. For example, R indicates a resistor, C indicates a capacitor, L indicates an inductor, Q indicates a bipolar junction transistor and M indicates a field-effect transistor. Although examples disclosed herein have been implemented using certain types of components, such as certain types of transistors, it should be understood that these are illustrative only. For example, in some embodiments, different types of transistors may be used, while in other embodiments different types of loads may be used. Each electronic component has a plurality of terminal through which it is connected to wires and other components. However, the use of the word "terminal" does not imply an implementation based on discrete components only, and any circuit described may be implemented as integrated circuit (IC).

In a radio frequency (RF) communication system, a linearly adjustable hybrid variable gain amplifier (VGA) with high dynamic range may be desirable for use in transceivers. Example methods and systems are described below for a high dynamic range hybrid VGA that may be implemented in a RF communication system to help to improve linearity, with relatively low power consumption.

<FIG> is a schematic diagram of a transceiver <NUM> in which an example hybrid variable gain amplifier, as described herein, may be implemented. In some examples, the architecture shown in <FIG> may be implemented in a portable electronic device (sometimes called a user equipment (UE)) or a base station for use in a wireless network, for example a Fifth Generation (<NUM>) wireless communication network. As illustrated in <FIG>, one VGA is used for a receiver automatic gain control (AGC) amplifier <NUM> and another VGA is used for a transmitter AGC amplifier <NUM>. The front end receiver portion of the transceiver <NUM> includes an antenna <NUM>, a duplexer <NUM>, and a low noise amplifier (LAN) and mixer circuit <NUM>. The output of the receiver AGC amplifier <NUM> is provided to a baseband analog application specific integrated circuit (ASIC) <NUM> which converts an analog signal to a digital signal. The gain of the receiver AGC amplifier <NUM> is controlled by a gain control circuit (shown as RX gain control of <FIG>), which applies a control signal (e.g., a control voltage or a digital control word) to the receiver AGC amplifier <NUM> to vary the gain of the receiver AGC amplifier <NUM>. Although <FIG> shows a baseband analog ASIC <NUM> and the AGCs <NUM>, <NUM> operating at baseband, it should be understood that the transceiver <NUM> may, in some examples, use RF VGAs and AGCs instead.

For transmitting signals, the baseband analog ASIC <NUM> receives a baseband modulated digital representation of a waveform or a modulated analog representation of a frequency modulation (FM) waveform. Then the baseband analog ASIC <NUM> converts the baseband signal's representation to analog intermediate frequency (IF) form at a constant signal level and supplies the analog IF form to the transmitter AGC amplifier <NUM>. The transmitter AGC amplifier <NUM> provides power control to the signal and supplies the powercontrolled signal to an upconverter <NUM>. The output from the upconverter <NUM> is provided to a power amplifier (PA) and driver circuitry <NUM>. The output from the PA and driver circuitry <NUM> is provided to an isolator <NUM>. The output from the isolator <NUM> is provided to the duplexer <NUM>. Finally, the duplexed signal outputted from the duplexer <NUM> is provided to the antenna <NUM> for transmission. The gain of the transmitter AGC amplifier <NUM> is controlled by a gain control circuit (shown as TX gain control of <FIG>), which applies a control signal (e.g., a control voltage or a digital control word) to the transmitter AGC amplifier <NUM> to vary the gain of the transmitter AGC amplifier <NUM>.

An important operating characteristic of a VGA is linearity, which is a measure of the variation of output signal strength in proportional to input signal strength. Generally, the dB gain of the VGA should preferably be linearly changed according to a gain control signal over a range of input signal amplitudes. A standard measure of the linearity of a VGA is referred to as a third order input intercept point (IIP3). The IIP3 of a VGA is the input power amplitude at which the output power of a fundamental input signal and the output power amplitude of a third order intermodulation product signal have equal magnitude. The greater the value of IIP3 is for a particular VGA, the greater the linearity of that VGA. Likewise, the lower the value of IIP3 for a particular VGA, the lower the linearity of that VGA. One drawback of conventional VGAs is that IIP3 varies significantly as a result of controlling gain of the VGA over a wide dynamic range. For conventional VGAs that use current steering to control gain, the IIP3 varies as the amount of current flowing across the transistor in the signal path varies, as discussed further below with respect to example conventional VGAs. Such variation in IIP3 is undesirable because the linearity of the VGA will be reduced when the gain of the circuit is adjusted to operate at certain levels, resulting in signal distortion.

An example conventional VGA <NUM> is shown in <FIG>. In this approach, the VGA <NUM> is based on a differential amplifier, and uses current steering to control gain. The differential amplifier includes a positive cell indicated by a dashed circle <NUM> coupled to a positive input <NUM>, and a negative cell indicated by a dashed circle <NUM> coupled to a negative input <NUM>. The positive cell <NUM> includes bipolar junction transistors (BJTs) Q21 and Q22, and the negative cell <NUM> includes BJTs Q23 and Q24. Each of the transistors in the VGA <NUM> has a base (B), an emitter (E) and a collector (C) terminal. In some implementations, the transistors may instead be heterojunction bipolar transistors (HBTs). The transistors Q21 and Q24 are connected to a voltage rail Vdd, which may be the highest voltage level supplied on a chip. The gain of the VGA <NUM> is controlled by varying the amount of current that flows through the transistor Q22 in the positive cell <NUM>, and the transistor Q23 in the negative cell <NUM> of the differential amplifier. The current that flows through the transistor Q21 in the positive cell is varied such that the total current in the positive cell <NUM> is substantially constant, and the current that flows through the transistor Q24 is also varied to ensure substantially constant current in the negative cell <NUM>. Control signals 205a and 205b (generally referred to as control signals <NUM>) are applied to transistors Q21 and Q22, respectively, to control the amounts of current flowing in each path of the positive cell <NUM>. Similarly, the control signals <NUM> are applied to transistors Q23 and Q24 to control the amounts of current flowing in each path of the negative cell <NUM>. Controlling the amount or percentage of current flowing through parallel paths (with the total amount of current flowing through the paths being substantially constant) may also be known as current steering. When the majority of current flows through transistors Q21 and Q24, a small portion of the current flows through transistors Q22 and Q23, and the gain of the VGA <NUM> will be at or close to its minimum. However, the output signals are significantly or completely suppressed because the transistors Q22 and Q23 are short of current. In this regard, the linearity is poor when gain is at or close to minimum.

In the VGA <NUM>, inadequate current flow through transistors Q22 and Q23 leads to decreased linearity at low gain, which is illustrated in <FIG> by an IIP3 plot versus gain of the VGA <NUM>. In particular, a decreased linearity in performance is indicated by dashed circle <NUM>. At low gains, the value of the IIP3 decreases significantly for the VGA <NUM>, indicating poor linearity for low gains, which is undesirable if the VGA <NUM> is to be used for a wide dynamic range of input signals.

Another example conventional VGA <NUM> is shown in <FIG>. The VGA <NUM> is based on a differential amplifier, and uses current steering to control gain. The differential amplifier includes a positive cell indicated by a dashed circle <NUM> and a negative cell indicated by a dashed circle <NUM>. The positive cell <NUM> includes field effect transistors (FETs) M1 and M2, and the negative cell <NUM> includes FETs M3 and M4. Each of the transistors in the VGA <NUM> has a gate (G), a source (S) and a drain (D) terminal. The source of the transistor M2 is coupled to the negative output <NUM> which is at the source of the transistor M4. Similarly, the source of the transistor M3 is coupled to the positive output <NUM> which is at the source of the transistor M1. In the positive cell <NUM>, current is steered between the path across the transistor M1 and the path across the transistor M2; similarly, in the negative cell <NUM>, current is steered between the path across the transistor M3 and the path across the transistor M4. For the VGA <NUM>, when the majority of current flows across transistors M1 and M3, and a small portion of current flows across transistors M2 and M4, the gain of the VGA <NUM> will be at or close to its maximum. However, inadequate current flow across transistors M2 and M4 may result in the transistors M2 and M4 being turned off or close to being turned off.

<FIG> is an IIP3 plot versus gain of the VGA <NUM>. As shown in <FIG>, when only a small current is flowing through transistors M2 and M4, the linearity drops significantly. Specifically, the value of the IIP3 decreases significantly when the gain of the VGA <NUM> is close to its maximum, indicated by a dashed circle <NUM>. This is undesirable if the VGA <NUM> is to be used for a wide dynamic range of input signals. Moreover, the maximum gain of the VGA <NUM> is lower due to the transistors M2 and M4 loading the outputs of the amplifier.

The conventional VGAs <NUM> and <NUM> discussed above show poor linearity when considering a wide dynamic range. Conventional approaches to address such drawbacks may include improving linearity by increasing the supply voltage or increasing the current, or reducing the gain (which would have to be compensated elsewhere). Such approaches may require any or all of greater demand on power consumption, lower battery life and greater complexity elsewhere in the system. Such approaches may not be suitable in certain applications, such as in <NUM> phased array systems, where there may be hundreds of VGAs and the total increase in either or both of power consumption and complexity may be significant.

A hybrid VGA, as disclosed herein, may help to improve linearity performance over a wide dynamic gain, and may address at least some drawbacks of the above-discussed conventional VGAs. The disclosed hybrid VGA may be used in various applications, including transceivers in portable devices or base stations in wireless communication networks. <FIG> is a schematic diagram of a hybrid VGA <NUM> in accordance with an example embodiment.

As will be discussed in greater detail below, the hybrid VGA <NUM> may be controlled to operate in a first mode of operation or a second mode of operation, depending on the desired gain. In the first mode of operation, the electrical paths illustrated in solid lines in <FIG> are enabled so that current can flow in those paths, and the electrical paths illustrated in dashed lines in <FIG> are disabled so that current flow in those paths is inhibited. In the second mode of operation, the electrical paths illustrated in solid lines in <FIG> are enabled so that current can flow in those paths, and the electrical paths illustrated in dashed lines in <FIG> are disabled so that current flow in those paths is inhibited. The first and second modes of operation have different linearity characteristics. Thus, one mode of operation may compensate for drawbacks of the other mode of operation. By controlling the hybrid VGA <NUM> to operate in a particular mode of operation, depending on the desired gain, the overall linearity of the hybrid VGA <NUM> may be improved, compared to the conventional VGAs discussed previously.

The details of the hybrid VGA <NUM> are now discussed with respect to <FIG>. The hybrid VGA <NUM> has a positive input <NUM>, a negative input <NUM>, a positive output <NUM> and a negative output <NUM>. A first portion of the hybrid VGA <NUM> is associated with the positive input <NUM>, and a second portion is associated with the negative input <NUM>. In the example shown, the first portion includes an electrical path from the positive input <NUM> to the positive output <NUM>, via the transistor Q41; this electrical path is enabled in both the first and the second modes of operation. The first portion also includes an electrical path from the positive input <NUM> to the negative output <NUM>, via the transistor Q42; this electrical path is enabled when the hybrid VGA <NUM> is operating in the first mode of operation. The first portion also includes an electrical path from the positive input <NUM> to the voltage source Vdd, via the transistor Q43; this electrical path is enabled when the hybrid VGA <NUM> is operating in the second mode of operation.

The second portion of the hybrid VGA <NUM> is similar to the first portion. In the example shown, the second portion includes an electrical path from the negative input <NUM> to the negative output <NUM>, via the transistor Q46; this electrical path is enabled in both the first and the second modes of operation. The second portion also includes an electrical path from the negative input <NUM> to the positive output <NUM>, via the transistor Q45; this electrical path is enabled when the hybrid VGA <NUM> is operating in the first mode of operation. The second portion also includes an electrical path from the negative input <NUM> to the voltage source Vdd, via the transistor Q44; this electrical path is enabled when the hybrid VGA <NUM> is operating in the second mode of operation.

The hybrid VGA <NUM> includes connections to control signals, in this example three control voltages V<NUM>, V<NUM>, V<NUM> (although fewer or greater number of control signals may be used in other implementations). The control voltage V<NUM> is used to control transistors Q41 and Q46; the control voltage V<NUM> is used to control transistors Q42 and Q45; and the control voltage V<NUM> is used to control transistors Q43 and Q44. The control voltages V<NUM>, V<NUM>, V<NUM> selectively enable electrical paths for the first mode of operation or the second mode of operation. For example, to operate the hybrid VGA <NUM> in the first mode of operation, the control voltages V<NUM>, V<NUM>, V<NUM> control operation of the transistors Q42 and Q45 so that these transistors allow at least some current to flow (e.g., at least partially turning on the transistors Q42, Q45), and at the same time control operation of the transistors Q43 and Q44 so that these transistors inhibit current flow (e.g., turning off the transistors Q43, Q44). To operate the hybrid VGA <NUM> in the second mode of operation, for example, the control voltages V<NUM>, V<NUM>, V<NUM> control operation of the transistors Q43 and Q44 so that these transistors allow at least some current to flow (e.g., at least partially turning on the transistors Q43, Q44), and at the same time control operation of the transistors Q42 and Q45 so that these transistors inhibit current flow (e.g., turning off the transistors Q42, Q45). At the same time, the control voltages V<NUM>, V<NUM>, V<NUM> are used for current steering, to control the amount or percentage of total current flowing in the different enabled electrical paths.

To help in understanding the hybrid VGA <NUM>, the hybrid VGA <NUM> may be viewed as having first and second differential amplifiers that are coupled by common transistors Q41 and Q46.

The first differential amplifier is now described with reference to <FIG>. The hybrid VGA <NUM> operates using the first differential amplifier when the electrical paths shown in solid lines are enabled and current flow is inhibited for the paths shown in dashed lines, in the first mode of operation. The first differential amplifier includes a first transistor Q41, a sixth transistor Q46 and a first plurality of transistors Q42, Q45 (indicated by dashed box <NUM>). In the first plurality of transistors, the transistor Q42 cross-connects the positive input <NUM> to the negative output <NUM> and the transistor Q45 cross-connects the negative input <NUM> to the positive output <NUM>. Such a configuration, in which the first transistor Q41 is coupled between a positive output and a positive input, the sixth transistor Q46 is coupled between a negative output and a negative input, and the first plurality of transistors Q42, Q45 cross-connects the positive/negative inputs to the negative/positive outputs, may be referred to as a cross-connected topology. Operation of the hybrid VGA <NUM> using this first differential amplifier, in the first mode of operation, provides good linearity at low gains.

The second differential amplifier is now described with reference to <FIG>. The hybrid VGA <NUM> operates using the second differential amplifier when the electrical paths shown in solid lines are enabled and current flow is inhibited for the paths shown in dashed lines, in the second mode of operation. The second differential amplifier includes the first transistor Q41, the sixth transistor Q46 and a second plurality of transistors Q43, Q44 (indicated by dashed box <NUM>). Each of the second plurality of transistors Q43, Q44 is tied to the voltage source Vdd. Such a configuration, in which the first transistor Q41 is coupled between a positive output and a positive input, the sixth transistor Q46 is coupled between a negative output and a negative input, and the second plurality of transistors Q43, Q44 is coupled between the voltage source Vdd and the positive/negative inputs, may be referred to as a tied-to-Vdd topology. Operation of the hybrid VGA <NUM> using this second differential amplifier, in the second mode of operation, provides good linearity at high gains.

As discussed above, control signals, in this example three control voltages V<NUM>, V<NUM>, V<NUM>, control operation of the transistors, to cause the hybrid VGA <NUM> to operate in the first or the second mode of operation. The first control voltage V<NUM> is for example connected to the first and sixth transistors Q41, Q46; the second control voltage V<NUM> is for example connected to the first plurality of transistors Q42, Q45; and the third control voltage V<NUM> is for example connected to the second plurality of transistors Q43, Q44. The control voltages V<NUM>, V<NUM>, V<NUM> may then be used to turn the transistors on or off as appropriate, to operate in the first mode of operation (using the first differential amplifier - see <FIG>) or the second mode of operation (using the second differential amplifier - see <FIG>), as well as for current steering, as discussed previously.

Accordingly, in the illustrated example, the control voltages V<NUM>, V<NUM>, V<NUM> enable the hybrid VGA <NUM> to operate as a current steering amplifier. In <FIG>, the hybrid VGA <NUM> is illustrated as being implemented using bipolar transistors, however the hybrid VGA <NUM> may be implemented using any type of transistors. In the case where the hybrid VGA <NUM> is implemented using BJTs or HBTs, as shown in <FIG>, the hybrid VGA <NUM> operates as a common-base amplifier, in which the input signal injects into the emitter of each transistor and flows out through the collector of each transistor. In some examples, different types of transistors may be used, and the hybrid VGA <NUM> may instead operate as a cascode amplifier or a common-emitter amplifier.

Reference is made again to <FIG>. In operation, control voltages V<NUM>, V<NUM>, V<NUM> are provided (e.g., by a control circuit or a processor) to enable the hybrid VGA <NUM> to operate in the first mode or the second mode of operation, depending on the desired performance of the hybrid VGA <NUM>.

For example, when the desired gain of the hybrid VGA <NUM> is low, the hybrid VGA <NUM> can be operated using the first mode of operation (i.e., using the first differential amplifier, having the cross-connected topology). To achieve this, the control voltage V<NUM> is set to control transistors Q43 and Q44 to inhibit current flow (e.g., turn off). The control voltages V<NUM> and V<NUM> may then be used to perform current steering by controlling operation of transistors Q41, Q42, Q45 and Q46, to amplify the input signal with the desired gain.

When the desired gain of the hybrid VGA <NUM> is high, the hybrid VGA <NUM> can be operated using the second mode of operation (i.e., using the second differential amplifier, having the tied-to-Vdd topology). To achieve this, the control voltage V<NUM> is set to control transistors Q42 and Q45 to inhibit current flow (e.g., turn off). The control voltages V<NUM> and V<NUM> may then be used to perform current steering by controlling operation of transistors Q41, Q43, Q44 and Q46, to amplify the input signal with the desired gain.

By way of non-limiting example, in one possible configuration, the positive output <NUM> is coupled to the voltage source Vdd via an inductor <NUM>, the negative output <NUM> is coupled to the voltage source Vdd via another inductor <NUM>; the positive input <NUM> is coupled to ground via an inductor <NUM>, and the negative input <NUM> is coupled to ground via another inductor <NUM>. Although inductors are shown in this example, other loads, such as capacitors and resistors, as well as combinations of any or all of capacitors, inductors and resistors, are possible. In various examples, a bias voltage or a bias current in the hybrid VGA <NUM> may be set in any suitable way.

In the example shown, the hybrid VGA <NUM> is implemented using bipolar transistors, such as BJTs or HBTs, and the control voltages V<NUM>, V<NUM>, V<NUM> are connected to the bases of the transistors to control operation of the transistors. The hybrid VGA <NUM> may be implemented using other types of transistors, and controlled using appropriate control voltages. For example, the hybrid VGA <NUM> may be implemented using FETs, such as metal-oxide semiconductor field-effect transistors (MOSFETs) or high-electron-mobility transistors (HEMTs), and the control voltages may be connected to the gates of the transistors to control operation of the transistors in the manner discussed above. In other examples, implementation may use other transistors, such as other types of FETs (including metal-semiconductor field-effect transistors (MESFETs)), other types of bipolar transistors, and others. As used herein, "transistor" generically refers to any active circuit, and is not limited to the particular implementation shown in the figures. In various examples, the transistors used in the hybrid VGA <NUM> may be of different sizes, for example according to a gain specification.

<FIG> presents an IIP3 plot versus gain of the example hybrid VGA <NUM>. As shown in <FIG>, at lower gains (e.g., in the range of about -30dB to about -10dB), the performance of the hybrid VGA <NUM> (indicated by <NUM>) shows improvement over the performance of the conventional VGA <NUM> of <FIG> (indicated by <NUM>). This is because at lower gains, the hybrid VGA <NUM> may be operated in the first mode of operation, which has good linearity at lower gains. At higher gains (e.g., in the range of about -10dB to about 10dB), the performance of the hybrid VGA <NUM> (indicated by <NUM>) shows improvement over the performance of the conventional VGA <NUM> of <FIG> (indicated by <NUM>). This is because at higher gains, the hybrid VGA <NUM> may be operated in the second mode of operation, which has good linearity at higher gains. Generally, the hybrid VGA <NUM> may be controlled to operate in either the first or the second mode of operation, in order to maintain good linearity over a wider dynamic range than is possible using the conventional VGAs <NUM>, <NUM>. Further, the example disclosed hybrid VGA <NUM> may be implemented, with no significant increase in power consumption, die area or gain penalty.

<FIG> is a schematic diagram of an example processing system <NUM>, which may be used to implement the methods and systems disclosed herein. For example, the processing system <NUM> may be used for a portable device or a base station implemented in <NUM> communication networks, and including a hybrid VGA as disclosed above. The processing system <NUM> may also be used to control operation of the hybrid VGA, as discussed further below. Other processing systems suitable for implementing examples described in the present disclosure may be used, which may include components different from those discussed below. Although <FIG> shows a single instance of each component, there may be multiple instances of each component in the processing system <NUM> and the processing system <NUM> could be implemented using either or both of parallel and distributed systems.

The processing system <NUM> may include one or more processing devices <NUM>, such as a processor, a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a dedicated logic circuitry, or combinations thereof. The processing system <NUM> may also include one or more optional input/output (I/O) interfaces <NUM>, which may enable interfacing with one or more optional input devices <NUM> or output devices <NUM>. The processing system <NUM> may include one or more network interfaces <NUM> for wired or wireless communication with a network (e.g. any or all of an intranet, the Internet, a P2P network, a WAN, a LAN, and a Radio Access Network (RAN)) or other node. The network interfaces <NUM> may include one or more interfaces to wired networks and wireless networks. Wired networks may make use of wired links (e.g., Ethernet cable). Wireless networks, where they are used, may make use of wireless connections transmitted over an antenna such as antenna <NUM>. The network interfaces <NUM> may provide wireless communication via one or more transmitters or transmit antennas and one or more receivers or receive antennas, for example. In this example, a single antenna <NUM> is shown, which may serve as both transmitter and receiver. However, in other examples there may be separate antennas for transmitting and receiving. The processing system <NUM> may also include one or more storage units <NUM>, which may include a mass storage unit such as any one or more of a solid state drive, a hard disk drive, a magnetic disk drive and an optical disk drive.

The processing system <NUM> may include one or more memories <NUM> that can include physical memory <NUM>, which may include a volatile or non-volatile memory (e.g. any one or more of a flash memory, a random access memory (RAM), and a read-only memory (ROM)). The non-transitory memories <NUM> (as well as storage <NUM>) may store instructions for execution by the processing devices <NUM>, such as to carry out methods such as those described in the present disclosure. The memories <NUM> may include other software instructions, such as for implementing an operating system (OS), and other applications/functions. In some examples, one or more data sets or modules may be provided by an external memory (e.g., an external drive in wired or wireless communication with the processing system <NUM>) or may be provided by a transitory or non-transitory computer-readable medium. Examples of non-transitory computer readable media include a RAM, a ROM, an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a CD-ROM, or other portable memory storage.

There may be a bus <NUM> providing communication among components of the processing system <NUM>. The bus <NUM> may be any suitable bus architecture including, for example, a memory bus, a peripheral bus or a video bus. Optional input devices <NUM> (e.g., a keyboard, a mouse, a microphone, a touchscreen, or a keypad) and optional output devices <NUM> (e.g., a display, a speaker or a printer) are shown as external to the processing system <NUM>, and connected to optional I/O interface <NUM>. In other examples, one or more of the input devices <NUM> and the output devices <NUM> may be included as a component of the processing system <NUM>.

The hybrid VGA may be included as a component of the processing system <NUM>, for example as a component in the signal path for transmitting and receiving signals using the antenna <NUM>. The processing system <NUM> may also be used to control operation of the hybrid VGA.

<FIG> illustrates an example of a method that may be implemented using the processing system <NUM> to control the hybrid VGA to operate in the first or the second mode of operation. In some examples, instructions that cause the processing device <NUM> to carry out the method shown in <FIG> may be stored in the storage <NUM> of the processing system <NUM>.

The method includes, optionally, at <NUM>, receiving instructions to provide a desired gain of the hybrid VGA. In some examples, the desired gain of the hybrid VGA may be set without receiving external instructions (e.g., the desired gain may be set according to an internal determination by the processing system or according an internal feedback loop of the hybrid VGA).

The hybrid VGA is controlled by setting the control voltages (e.g., V<NUM>, V<NUM>, V<NUM> in the example of <FIG>), depending on the desired gain, such that the hybrid VGA operates in the first or the second mode of operation.

At <NUM>, it is determined whether the hybrid VGA is to operate in the first mode or the second mode of operation. This may be determined using a comparison with threshold values, which may be preset or changed dynamically, for example. The threshold values may be set according to either one or both of the device specification and expected operation of the hybrid VGA (e.g., whether the hybrid VGA is designed for mostly high gain or mostly low gain). In some examples, the threshold values may be changed dynamically (e.g., in real-time response to input signals), according to one or both of different desired performance and conditions.

At <NUM>, if the desired gain is below a first threshold, then the control voltages are set to control the hybrid VGA to operate in the first mode of operation, because the first mode of operation has better linearity for lower gains.

At <NUM>, if the desired gain at or above a second threshold, the control voltages are set to control the hybrid VGA to operate in the second mode of operation, because the second mode of operation has better linearity for higher gains.

The first and second threshold values may be equal, so that there is effectively a single threshold value that the desired gain is compared against.

The first and second threshold values may be different, with the first threshold value being lower in value than the second threshold value. This may enable a hysteresis effect. When the desired gain is below the first threshold value, the first mode of operation is used; when the desired gain is above the second threshold value, the second mode of operation is used; and when the desired gain is between the first and second threshold values, the currently used mode of operation, whether first mode or second mode, is maintained. This hysteresis effect may avoid frequent switching between the two modes of operation, and may help to provide greater stability in performance.

At <NUM>, the control voltages are further set to control the hybrid VGA so as to achieve the desired gain. In the example hybrid VGA of <FIG>, the control voltages are used for current steering to control the gain that is obtained.

In the present disclosure, an example hybrid VGA is described, as well as a method and system for controlling the operation of the hybrid VGA. By adjusting the control voltages, the hybrid VGA can be controlled to operate using an appropriate mode of operation, in order to improve linearity, over both high and low gains, compared to conventional VGAs. The example disclosed hybrid VGA may be implemented with little or no negative impact to the size of the circuitry, compared to conventional VGAs.

In various examples, the hybrid VGA may have increased power handling capability at both high and low gain. The example disclosed hybrid VGA may be used in portable devices and base stations, for example in a <NUM> communication system, to boost performance with little or no battery usage penalty, because the hybrid VGA has little or no negative impact on efficiency and power consumption.

In some examples, the disclosed hybrid VGA may use only two extra transistors and require negligible increase in control circuitry (for example requiring only a few additional analog multiplexers and digital control gates), compared to a conventional amplifier. Thus, the complexity in the RF circuitry design for the hybrid VGA may be increased insignificantly. Further, the maximum possible gain may be unchanged. The disclosed hybrid VGA may provide a greater degree of freedom to design for both gain and linearity specifications. The disclosed hybrid VGA may also be implemented using digital control.

Although the present disclosure describes methods and processes with steps in a certain order, one or more steps of the methods and processes may be omitted or altered as appropriate. One or more steps may take place in an order other than that in which they are described, as appropriate.

Although the present disclosure is described, at least in part, in terms of methods, a person of ordinary skill in the art will understand that the present disclosure is also directed to the various components for performing at least some of the aspects and features of the described methods, be it by way of hardware components, software or any combination of the two. Accordingly, the technical solution of the present disclosure may be embodied in the form of a software product. A suitable software product may be stored in a pre-recorded storage device or other similar non-volatile or non-transitory computer readable medium, including DVDs, CD-POMs, USB flash disk, a removable hard disk, or other storage media, for example. The software product includes instructions tangibly stored thereon that enable a processing device (e.g., a personal computer, a server, or a network device) to execute examples of the methods disclosed herein.

Claim 1:
A hybrid variable gain amplifier, VGA, (<NUM>) comprising:
a positive input (<NUM>) and a negative input (<NUM>), a positive output (<NUM>) and a negative output (<NUM>);
a first portion of the VGA (<NUM>) that is configured to provide an electrical path for current to flow between the positive input (<NUM>) and the positive output (<NUM>) in both a first mode of operation and a second mode of operation, provide an electrical path for current to flow between the positive input (<NUM>) and the negative output (<NUM>) in the first mode of operation only, and provide an electrical path for current to flow between the positive input (<NUM>) and a voltage source (Vdd) in the second mode of operation only; and
a second portion of the VGA that is configured to provide an electrical path for current to flow between the negative input (<NUM>) and the negative output (<NUM>) in both the first mode of operation and the second mode of operation, provide an electrical path for current to flow between the negative input (<NUM>) and the positive output (<NUM>) in the first mode of operation only, and provide an electrical path for current to flow between the negative input (<NUM>) and the voltage source (Vdd) in the second mode of operation only;
each of the first and second portions of the VGA including connections to control voltages (V1, V2, V3) to selectively enable the electrical paths in the first mode of operation or the electrical paths in the second mode of operation, the control voltages (V1, V2, V3) further controlling amount of current flow in the enabled electrical paths.