Patent Description:
A semiconductor package can not only provide a semiconductor die with protection from environmental contaminants, but it can also provide an electrical connection between the semiconductor die packaged therein and a substrate, such as a printed circuit board (PCB). For instance, a semiconductor die may be enclosed in an encapsulating material, and traces are electrically connected to the semiconductor die and the substrate.

However, a problem with such a semiconductor package is that it is subject to different temperatures during the packaging process. The semiconductor package may be highly stressed due to the different coefficients of thermal expansion (CTEs) of the various substrate and semiconductor die materials. As a result, the semiconductor package may exhibit warping or cracking so that the electrical connection between the semiconductor die and the substrate may be damaged, and the reliability of the semiconductor package may be decreased.

This problem is exacerbated in the case of a relatively large package, for example a package of <NUM> × <NUM> or larger. Therefore, a novel semiconductor package structure is desirable.

A configuration of a semiconductor device in which a heat-sink is in contact with a die is known from <CIT>. However, this document discloses a buffer layer disposed over a substrate and located between a frame and a semiconductor die.

The invention refers to a semiconductor package structure according to claim <NUM>. Preferred embodiments of the invention are defined in the appended dependent claims.

The scope of the invention is determined by reference to the appended claims.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

<FIG> is a cross-sectional view of a semiconductor package structure 100a, in accordance with some examples not corresponding to the invention as defined in the claims but useful for the understanding thereof. <FIG> is a plan view of an arrangement of holes in a substrate <NUM> of the semiconductor package structure 100a shown in <FIG> is a cross-sectional view of the semiconductor package structure 100a along line I-I' of <FIG>.

Additional features can be added to the semiconductor package structure 100a. Some of the features described below can be replaced or eliminated for different embodiments. To simplify the diagram, only a portion of the semiconductor package structure 100a is depicted in <FIG> and <FIG>. In some embodiments, the semiconductor package structure 100a may include a wafer-level semiconductor package, for example, a flip-chip semiconductor package.

Referring to <FIG>, the semiconductor package structure 100a may be mounted on a base (not shown). In some embodiments, the semiconductor package structure 100a may be a system-on-chip (SOC) package structure. Moreover, the base may include a printed circuit board (PCB) and may be formed of polypropylene (PP). In some embodiments, the base may include a package substrate. The semiconductor package structure 100a is mounted on the base by a bonding process. For example, the semiconductor package structure 100a includes bump structures <NUM>. In some embodiments, the bump structures <NUM> may be conductive ball structures (such as ball grid array (BGA)), conductive pillar structures, or conductive paste structures that are mounted on and electrically coupled to the base in the bonding process.

In the example, the semiconductor package structure 100a includes a substrate <NUM>. The substrate <NUM> has a wiring structure therein. In some embodiments, the wiring structure in the substrate <NUM> is a fan-out structure, and may include one or more conductive pads <NUM>, conductive vias <NUM>, conductive layers <NUM> and conductive pillars <NUM>. In such cases, the wiring structure in the substrate <NUM> may be disposed in one or more inter-metal dielectric (IMD) layers. In some embodiments, the IMD layers may be formed of organic materials, which include a polymer base material, non-organic materials, which include silicon nitride (SiNx), silicon oxide (SiOx), grapheme, or the like. For example, the IMD layers are made of a polymer base material. It should be noted that the number and configuration of the IMD layers, the conductive pads <NUM>, the conductive vias <NUM>, the conductive layers <NUM> and the conductive pillars <NUM> shown in Figures and only some examples and are not limitations to the present invention.

Moreover, the semiconductor package structure 100a also includes a first semiconductor die 115a and a second semiconductor die 115b bonded onto the substrate <NUM> through a plurality of conductive structures <NUM>. The substrate <NUM> has a first surface 101a and a second surface 101b opposite thereto, the first surface 101a is facing the first semiconductor die 115a and the second semiconductor die 115b, and the second surface 101b is facing the above-mentioned base. The conductive structures <NUM> are disposed over the first surface 101a and below the first semiconductor die 115a and the second semiconductor die 115b, and the bump structures <NUM> are disposed over the second surface 101b of the substrate <NUM>.

In some embodiments, the first semiconductor die 115a and the second semiconductor die 115b are electrically coupled to the bump structures <NUM> through the conductive structures <NUM> and the wiring structure in the substrate <NUM>. In addition, the conductive structures <NUM> may be controlled collapse chip connection (C4) structures. It should be noted that the number of semiconductor dies integrated in the semiconductor package structure 100a is not limited to that disclosed in the embodiment.

In some embodiments, the first semiconductor die 115a and the second semiconductor die 115b are active devices. For example, the first semiconductor die 115a and the second semiconductor die 115b may be logic dies including a central processing unit (CPU), a graphics processing unit (GPU), a dynamic random access memory (DRAM) controller or any combination thereof. In some other embodiments, one or more passive devices are also bonded onto the substrate <NUM>.

The first semiconductor die 115a and the second semiconductor dies 115b are arranged side-by-side. In some embodiments, the first semiconductor die 115a and the second semiconductor dies 115b are separated by a molding material <NUM>. The molding material <NUM> surrounds the first semiconductor die 115a and the second semiconductor die 115b, and adjoins the sidewalls of the first semiconductor die 115a and the second semiconductor die 115b. In some embodiments, the molding material <NUM> includes a nonconductive material such as an epoxy, a resin, a moldable polymer, or another suitable molding material. In some embodiments, the molding material <NUM> is applied as a substantial liquid, and then is cured through a chemical reaction. In some other embodiments, the molding material <NUM> is an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid, and then is cured through a UV or thermal curing process. The molding material <NUM> may be cured with a mold (not shown).

In some embodiments, the surfaces of the first semiconductor die 115a and the second semiconductor dies 115b facing away from the first surface 101a of the substrate <NUM> are exposed by the molding material <NUM>, such that a heat dissipating device (not shown) can directly attached to the surfaces of the first semiconductor die 115a and the second semiconductor dies 115b. As a result, the heat-dissipation efficiency of the semiconductor package structure 100a can be improved, particularly for a large semiconductor package structure, such as <NUM> × <NUM>, which is preferred for high-power applications.

The semiconductor package structure 100a also includes a polymer material <NUM> disposed under the molding material <NUM>, the first semiconductor die 115a and the second semiconductor die 115b, and between the conductive structures <NUM>. The semiconductor package structure 100a further includes an underfill layer <NUM> interposed between the first surface 101a of the substrate <NUM> and the polymer material <NUM>. In some embodiments, the first semiconductor die 115a, the second semiconductor dies 115b and the molding material <NUM> are surrounded by the underfill layer <NUM>. The polymer material <NUM> and the underfill layer <NUM> are disposed to compensate for differing coefficients of thermal expansion (CTEs) between the substrate <NUM>, the conductive structures <NUM>, the first semiconductor die 115a and the second semiconductor dies 115b.

In addition, the semiconductor package structure 100a includes a frame <NUM> attached to the first surface 101a of the substrate <NUM> through an adhesive layer <NUM>. The first semiconductor die 115a and the second semiconductor die 115b are surrounded by the frame <NUM> and the adhesive layer <NUM>. In some embodiments, the frame <NUM> and the adhesive layer <NUM> are separated from the underfill layer <NUM> by a gap. The substrate <NUM> has a first edge 101E<NUM> and a second edge 101E<NUM> opposite thereto. In some embodiments, the first edge <NUM> E<NUM> and the second edge 101E<NUM> are coplanar with sidewalls of the frame 113and the adhesive layer <NUM>.

Still referring to <FIG>, the substrate <NUM> of the semiconductor package structure 100a includes a first hole 110a and a second hole 110b formed on the second surface 101b. In some embodiments, at least one of the first hole 110a and the second hole 110b penetrates through the substrate <NUM> from the first surface 101a to the second surface 101b. Although the first hole 110a and the second hole 110b shown in <FIG> penetrate through the substrate <NUM>, in some other embodiments, both the first hole 110a and the second hole 110b do not penetrate through the substrate <NUM> from the first surface 101a to the second surface 101b. In some embodiments, the first hole 110a is covered by the first semiconductor die 115a, and the second hole 110b is covered by the second semiconductor die 115b. In other words, the first hole 110a is located within the projection of the first semiconductor die 115a on the substrate <NUM>, and the second hole 110b is located within the projection of the second semiconductor die 115b on the substrate <NUM>.

Specifically, the first semiconductor die 115a and the second semiconductor die 115b have a center line C-C' between them. The first hole 110a is disposed closer to the center line C-C' than the first edge 101E<NUM> of the substrate <NUM>, and the second hole 110b is disposed closer to the center line C-C' than the second edge 101E<NUM> of the substrate <NUM>. Although there are only two holes in the substrate <NUM> shown in <FIG>, it should be noted that there is no limitation on the number of the holes formed in the substrate <NUM>.

In some embodiments, the first hole 110a and the second hole 110b are formed by a laser drilling process or another suitable process. It should be noted that the first hole 110a and the second hole 110b may be formed by the same forming process for the conductive pillars <NUM> in the wiring structure of the substrate <NUM>. Moreover, the first semiconductor die 115a and the second semiconductor die 115b are bonded to the substrate <NUM> after forming the holes in the substrate <NUM>. Therefore, the damage of the first semiconductor die 115a and the second semiconductor die 115b can be prevented.

Referring to <FIG>, which is a plan view of an arrangement of holes in a substrate <NUM> of the semiconductor package structure 100a shown in <FIG> is a cross-sectional view of the semiconductor package structure 100a along line I-I' of <FIG>. It should be noted that <FIG> is the plan view from the bottom of the semiconductor package structure 100a. In other words, <FIG> is the plan view from the second surface 101b of the substrate <NUM>, which the bump structures <NUM> are disposed on. In particular, the bump structures <NUM> are omitted for brevity.

As shown in <FIG>, the substrate <NUM> includes more than two holes. In particular, the substrate <NUM> further includes a third hole 110c and the fourth hole 110d formed on the second surface 101b. The third hole 110c is covered by the first semiconductor die 115a, and the fourth hole 110d is covered by the second semiconductor die 115b. It should be noted that the substrate <NUM> has a center 101C, and the first hole 101a, the second hole 101b, the third hole 110c, and the fourth hole 110d are disposed closer to the center 101C than the first edge 101E<NUM> and the second edge 101E<NUM> of the substrate <NUM>.

The holes formed in the substrate <NUM>, for example, the first hole 110a, the second hole 110b, the third hole 110c and the fourth hole 110d, are designed to release the stress in the substrate <NUM>, especially the stress concentrated in the region below the interface between two semiconductor dies (i.e. the first semiconductor die 115a and the second semiconductor die 115b). Since the semiconductor package structure 100a may be highly stressed due to the different coefficients of thermal expansion (CTEs) of the substrate <NUM> and the semiconductor dies, the holes formed in the substrate <NUM> can solve the warping or cracking problems caused by mismatched CTEs. As a result, the electrical connection within the semiconductor package structure 100a may not be damaged, and the reliability of the semiconductor package structure 100a may be increased.

<FIG> is a cross-sectional view of a semiconductor package structure 100b, in accordance with some other examples not corresponding to the invention as defined in the claims but useful for the understanding thereof. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to <FIG> are omitted for brevity.

As shown in <FIG>, the semiconductor package structure 100b includes a stress buffer layer <NUM> filled in the first hole 110a and the second hole 110b. The stress buffer layer <NUM> is made of a polymer material, such as a silicone resin or rubber. In some embodiments, the stress buffer layer <NUM> is made of an organic resin, such as Ajinomoto Build-up Film (ABF).

Moreover, the stress buffer layer <NUM> may be formed by a spin coating process. In some other embodiments, a material of the stress buffer layer <NUM> may be dispensed in the first hole 110a and the second hole <NUM>10b, and an excess portion of the material of the stress buffer layer <NUM> may be removed. In some embodiments, the stress buffer layer <NUM> may be formed before bonding the first semiconductor die 115a and the second semiconductor die 115b to the substrate <NUM>.

In some embodiments, the stress buffer layer <NUM> may filled up the first hole 110a and the second hole 110b, and the surfaces of the stress buffer layer <NUM> are level with the second surface 101b of the substrate <NUM>. In some other embodiments, the surfaces of the stress buffer layer <NUM> may not be level with the second surface 101b of the substrate <NUM> according to the actual manufacturing processes.

Filling the first hole 110a and the second hole 110b with the stress buffer layer <NUM> may offer advantages like preventing the impurities and dust from dropping into the first hole 110a and the second hole 110b during the process of handling the substrate <NUM>. In addition, the warping or cracking caused by mismatched coefficients of thermal expansion in the semiconductor package structure 100b can be solved by the holes (including the first hole 110a and the second hole 110b) and the stress buffer layer <NUM> formed in the substrate <NUM>. Accordingly, the electrical connection within the semiconductor package structure 100b may not be damaged, and the lifespan of the semiconductor package structure 100b may be increased.

<FIG> is a plan view showing shapes of holes in a substrate 201A of a semiconductor package structure 200a, and <FIG> is a plan view showing shapes of holes in a substrate 201B of a semiconductor package structure 200b, in accordance with some embodiments of the invention. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to <FIG> are omitted for brevity.

Referring to <FIG>, the semiconductor package structure 200a has holes A, B, C, D, E, F, G, H, I, J, K and L in the substrate 201A, and the number of holes in the substrate 201A is much more than that in the substrate <NUM> of the semiconductor package structure 100a. As shown in <FIG>, the holes A, B, C, D, E and F are covered by the first semiconductor die 115a, and the holes G, H, I, J, K and L are covered by the second semiconductor die 115b. In other words, the holes A-F are located within the projection of the first semiconductor die 115a on the substrate 201A, and the holes G-L are located within the projection of the second semiconductor die 115b on the substrate 201A.

Specifically, the holes A, B and C are arranged in a first array, the holes D, E and F are arranged in a second array, the holes G, H and I are arranged in a third array, and the holes J, K and L are arranged in a fourth array. The first array, the second array, the third array and the fourth array are parallel to the center line C-C' of the first semiconductor die 115a and the second semiconductor die 115b.

Referring to <FIG>, the substrate 201B in the semiconductor package structure 200b has holes a, b, c, d, e, f, g, h, i, j, k and l, which are arranged in the same way as the holes A-L of the substrate 201A in the semiconductor package structure 200a. The difference between the substrate 201A and the substrate 201B is that the holes a-l have circular shapes in the plan view. Compared with the holes A-L in the substrate 201A, which have rectangular shapes in the plan view, the problems of stress concentrated at the corners of the holes A-L can be prevented in the substrate 201B due to the round shapes of the holes a-l. Therefore, the probability that the cracking problem occurs in the substrate 201B of the semiconductor package structure 200b can be more decreased.

In some embodiments, stress buffer layers may be optionally formed in the holes A-L of the semiconductor package structure 200a and in the holes a-l of the semiconductor package structure 200b. It should be noted that the holes A-L are symmetrically located about the center line C-C' in the plan view of <FIG>, and the holes a-l are symmetrically located about the center line C-C' in the plan view of <FIG>. In some other embodiments, the holes A-L are symmetrically located about the center 201C of the substrate 201A in the plan view of <FIG>, and the holes a-l are symmetrically located about the center 201C' of the substrate 201B in the plan view of <FIG>.

<FIG> is a plan view showing arrangements of holes in a substrate 301A of a semiconductor package structure 300a, and <FIG> is a plan view showing arrangements of holes in a substrate 301B of a semiconductor package structure 300b, in accordance with some embodiments of the disclosure. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to <FIG> are omitted for brevity.

Referring to <FIG>, the semiconductor package structure 300a has holes A, B, C, D, E, and F in the substrate 301A. The holes A, B and C are covered by the first semiconductor die 115a, and the holes D, E and F are covered by the second semiconductor die 115b. In other words, the holes A-C are located within the projection of the first semiconductor die 115a on the substrate 301A, and the holes D-F are located within the projection of the second semiconductor die 115b on the substrate 301A.

It should be noted that the holes A-F are arranged radially around the center 301C of the substrate 301A. In some other embodiments, the holes A-F are arranged radially around a center, and the center is located between the first semiconductor die 115a and the second semiconductor die 115b.

Compared with the semiconductor substrate 200a of <FIG>, the stress in the substrate 301A of the semiconductor package structure 300a, which has holes A-F arranged radially, can be released more efficiently. In other words, in order to obtain the same stress releasing effect as in the semiconductor package structure 200a, the number of the holes in the substrate 301A of the semiconductor package structure 300a can be less than the number of the holes in the substrate 201A of the semiconductor package structure 200a. However, the substrate 201A of the semiconductor package structure 200a, which has holes A-L arranged parallel to the center line C-C', is more easily to be manufactured than the substrate 301A of the semiconductor package structure 300a, which has holes A-F arranged radially.

Referring to <FIG>, the substrate 301B in the semiconductor package structure 300b has holes a, b, c, d, e, f, g, h, i, j, k, l, m and n arranged staggered in the substrate 301B. Specifically, the holes a-g are covered by the first semiconductor die 115a and staggered disposed along the direction of the center line C-C', and the holes h-n are covered by the second semiconductor die 115b and staggered disposed along the direction of the center line C-C'.

Compared with the semiconductor package structure 200a in <FIG> and the semiconductor package structure 300a in <FIG>, the substrate 301B of the semiconductor package structure 300b can combine the above-mentioned benefits of the hole arrangements of the substrate 201A in the semiconductor package structure 200a and the substrate 301A of the semiconductor package structure 300a. Specifically, the holes a-n in the substrate 301B can be manufactured easily, and the stress in the substrate 301B can be released efficiently.

In some embodiments, stress buffer layers may optionally be formed in the holes A-F of the semiconductor package structure 300a and the holes a-n of the semiconductor package structure 300b. It should be noted that the holes A-F are symmetrically located about the center line C-C' in the plan view of <FIG>, and the holes a-n are symmetrically located about the center line C-C' in the plan view of <FIG>. In some other embodiments, the holes A-F are symmetrically located about the center 301C of the substrate 301A in the plan view of <FIG>, and the holes a-n are symmetrically located about the center 301C' of the substrate 301B in the plan view of <FIG>.

<FIG> is a plan view showing locations of holes in a substrate 401A of a semiconductor package structure 400a, and <FIG> is a plan view showing locations of holes in a substrate 401B of a semiconductor package structure 400b, in accordance with some embodiments of the disclosure. Descriptions of elements of the embodiments hereinafter that are the same as or similar to those previously described with reference to <FIG> are omitted for brevity.

Referring to <FIG>, the substrate 401A in the semiconductor package structure 400a has holes A, B, C, D, E, F, G, H, I, J, K and L arranged in the same way as the holes A-L of the substrate 201A in the semiconductor package structure 200a shown in <FIG>. The holes A-L are arranged parallel to the center line C-C' in the substrate 401A. The difference between <FIG> and <FIG> is that the holes A-L in the substrate 401A are located closer to the center 401C of the substrate 401A than the holes A-L in the substrate 201A.

Since the maximum stress is likely to be concentrated at the center 401C of the substrate 401A, the stress in the substrate 401A of the semiconductor package structure 400a, which has holes A-L located closer to the center 401C of the substrate 401A, can be released more efficiently than the semiconductor package structure 200a.

Referring to <FIG>, the substrate 401B in the semiconductor package structure 400b has holes a, b, c, d, e, f, g, h, i and j located along the peripheral edge of the substrate 401B. In other words, the holes a-j are located far from the center 401C' of the substrate 401B to reserve space in the middle of the substrate 401B for routing. Compared with the semiconductor substrate 400a of <FIG>, the semiconductor substrate 400b of <FIG> can provide a better routing capability for the substrate 401B.

In some embodiments, stress buffer layers may optionally be formed in the holes A-L of the semiconductor package structure 400a and the holes a-j of the semiconductor package structure 400b. It should be noted that the holes A-L are symmetrically located about the center line C-C' in the plan view of <FIG>, and the holes a-j are symmetrically located about the center line C-C' in the plan view of <FIG>. In some other embodiments, the holes A-L are symmetrically located about the center 401C of the substrate 401A in the plan view of <FIG>, and the holes a-j are symmetrically located about the center 401C' of the substrate 401B in the plan view of <FIG>.

<FIG> is a cross-sectional view of a semiconductor package structure 500a, in accordance with some examples not corresponding to the invention as defined in the claims but useful for the understanding thereof. It should be noted that the semiconductor package structure 500a may include the same or similar portions as that of the semiconductor package structures 100a and 100b, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure 500a includes a substrate <NUM>, a first semiconductor die 115a, a second semiconductor die 115b and a frame <NUM>. As shown in <FIG>, the semiconductor package structure 500a further includes a heat sink <NUM> and a plurality of passive components <NUM>, wherein the heat sink <NUM> is disposed on the first semiconductor die 115a and the second semiconductor die 115b, and the passive components <NUM> is disposed adjacent to one of the first semiconductor die 115a and the second semiconductor die 115b.

In the present example, the heat sink <NUM> is configured to dissipate the heat generated by the first semiconductor die 115a and the second semiconductor die 115b during operation. In some examples not corresponding to the invention as defined in the claims but useful for the understanding thereof, the heat sink <NUM> is in direct contact with the first semiconductor die 115a and the second semiconductor die 115b, such that the heat may be dissipated rapidly. In some other examples not corresponding to the invention as defined in the claims but useful for the understanding thereof, a bonding layer (not shown) is disposed between the heat sink <NUM> and the first semiconductor die 115a, the second semiconductor die 115b in order to arrange the heat sink <NUM> more stably. In addition, the bonding layer may also help for eliminating the interstice (if present) between the heat sink and the semiconductor dies 115a, 115b, such that the thermal dissipation may also be improved.

As shown in <FIG>, the upper surface of the frame <NUM> is lower than the upper surface of the semiconductor dies 115a, 115b. In other words, there is a gap between the frame <NUM> and the heat sink <NUM>. It should be appreciated that the term "upper surface" of an element disposed over the substrate <NUM> is defined as a surface that is away from the substrate <NUM>. In other words, the upper surface of the element is opposite to an surface that faces or contacts the first surface 101a of the substrate <NUM>. Generally, the upper surface is substantially perpendicular to the center line C-C'. In addition, the terms "higher" and "lower" are referred to different positions along the center line C-C'. If an element or a portion is higher than another element or portion, the element or a portion is located farther away from the first surface 101a than the another element or portion, and vice versa. As viewed in a direction that is perpendicular to the upper surface of the semiconductor dies 115a, 115b, the heat sink <NUM> overlaps with the frame <NUM> and the semiconductor dies 115a, 115b. The above arrangement of the frame <NUM> may ensure the semiconductor dies 115a, 115b to contact the heat sink <NUM>.

A plurality of passive components <NUM> are disposed on the substrate <NUM>, and located between the frame <NUM> and the semiconductor dies 115a, 115b. It is noted that the passive components <NUM> are designed according to functional purposes of the semiconductor package structure 500a, and those skilled in the art may adjust the arrangement of the passive components <NUM> as required. For the sake of simplicity, the detailed description will not be provided herein.

<FIG> is a cross-sectional view of a semiconductor package structure 500b, in accordance with some other examples not corresponding to the invention as defined in the claims but useful for the understanding thereof, and <FIG> is a top view of the semiconductor package structure 500b shown in <FIG> is illustrated along line A-A' shown in <FIG>. It should be noted that the semiconductor package structure 500b may include the same or similar portions as that of the semiconductor package structure 500a, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure 500b includes a substrate <NUM>, a frame <NUM>, semiconductor dies 115a, 115b and a heat sink <NUM>.

As shown in <FIG>, the semiconductor package structure 500b further includes a buffer layer <NUM> which is disposed on the substrate <NUM> and located between the frame <NUM> and the semiconductor dies 115a, 115b. In the present example, upper surfaces of the frame <NUM>, the buffer layer <NUM> and the semiconductor dies 115a, 115b are located on the same imaginary plane. That is, the upper surface of the frame <NUM> is substantially level with the upper surfaces of the frame <NUM> and the semiconductor dies 115a, 115b. In the present example, the passive components <NUM> may be surrounded by the buffer layer <NUM>. For example, the buffer layer <NUM> includes polymer materials, but it is not limited thereto. Thanks to the arrangement of the buffer layer <NUM>, the passive components <NUM> may be protected and the thermal dissipation may be further improved since the thermal conductivity of the buffer layer <NUM> is greater than that of air. In addition, the warpage issue of the semiconductor package structure 500a may also be reduced since the substrate <NUM> may be supported by the frame <NUM> and/or the buffer layer <NUM>.

<FIG> is a cross-sectional view of a semiconductor package structure 500c, in accordance with some embodiments of the invention. It should be noted that the semiconductor package structure 500c may include the same or similar portions as that of the semiconductor package structure 500b, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure 500c includes a substrate <NUM>, a frame <NUM>, semiconductor dies 115a, 115b, a heat sink <NUM>, and a buffer layer <NUM>. In the present embodiment, the buffer layer <NUM> is separated from the frame <NUM> and the semiconductor dies 115a, 115b, reducing the difficulty of forming the buffer layer <NUM>. In addition, there is a gap between the heat sink <NUM> and the frame <NUM>, the buffer layer <NUM>. As set forth above, the frame <NUM> and the buffer layer <NUM> may not interfere the bonging between the semiconductor dies 115a, 115b and the heat sink <NUM>.

<FIG> is a cross-sectional view of a semiconductor package structure 500d, in accordance with some other examples not corresponding to the invention as defined in the claims but useful for the understanding thereof. It should be noted that the semiconductor package structure 500c may include the same or similar portions as that of the semiconductor package structure 500b, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure 500c includes a substrate <NUM>, semiconductor dies 115a, 115b, a heat sink <NUM>, and a buffer layer <NUM>. In the present example, the frame <NUM> is omitted and replaced by the buffer layer <NUM>, such that the manufacturing process of the semiconductor package structure 500d may be simplified, reducing the required time and cost of the manufacturing process. It should be noted that the buffer layer <NUM> may provide sufficient support so as to reduce the warpage issue of the semiconductor package structure 500d. In the present example, the heat sink <NUM> is disposed directly above the semiconductor dies 115a, 115b and the buffer layer <NUM>.

<FIG> is a cross-sectional view of a semiconductor package structure 500e, in accordance with some other examples not corresponding to the invention as defined in the claims but useful for the understanding thereof. It should be noted that the semiconductor package structure 500c may include the same or similar portions as that of the semiconductor package structure 500b, and for the sake of simplicity, those portions will not be discussed in detail again. For example, the semiconductor package structure 500c includes a substrate <NUM>, a frame <NUM>, semiconductor dies 115a, 115b, a heat sink <NUM>, and a buffer layer <NUM>. In the present example, the buffer layer <NUM> covers the upper surface of the frame <NUM>. As a result, the frame <NUM> may not directly contact the heat sink <NUM> (namely, the frame <NUM> may be separated from the heat sink <NUM>), and the buffer layer <NUM> contacts the heat sink <NUM> instead. Since the flatness of the surface formed by the buffer layer <NUM> may be higher than the flatness of the surface formed by the frame <NUM>, a flatter interface between the buffer layer <NUM> and the heat sink <NUM>. Accordingly, the contact between the semiconductor dies 115a, 115b and the heat sink <NUM> may be created, enhancing the thermal dissipation of the semiconductor dies 115a, 115b.

According to the foregoing embodiments and examples, the holes formed in the substrate are designed to release the stress in the substrate, especially the stress concentrated in the region below the interface between two semiconductor dies. Since the semiconductor package structure may be highly stressed due to the different coefficients of thermal expansion (CTEs) of the substrate and the semiconductor dies, the holes formed in the substrate can solve the warping or cracking problems caused by mismatched CTEs. As a result, the electrical connection within the semiconductor package structure may not be damaged, and the reliability and the lifespan of the semiconductor package structure may be increased. In addition, in some embodiment of the present disclosure, the buffer layer formed on the substrate may help to reduce warpage of the semiconductor package structure and/or enhance the thermal dissipation of the semiconductor dies.

In the foregoing embodiments and examples, the semiconductor dies 115a and 115b may be formed in the same package, for example, the semiconductor dies 115a and 115b are disposed on a fan-out package interposer, the fan-out package interposer is a rewiring laminate structure. In addition, the semiconductor dies 115a and 115b could be disposed on a Chip-on-Wafer-on-Substrate (CoWoS) structure with a package interposer, the package interposer has multiple through silicon vias (TSVs) as interconnection between the semiconductore dies and the substrate <NUM>.

In other embodiments, the semiconductor dies 115a and 115b may be formed in different packages, for example, the semiconductor die 115a could be a flip-chip (FC) package, while the semiconductor die 115b could be a fan-out structure. The package construction may be varied to achieve different technical purposes.

Claim 1:
A semiconductor package structure, comprising:
a substrate (<NUM>);
a semiconductor die (115a, 115b) disposed over the substrate (<NUM>);
an underfill layer (<NUM>) between the semiconductor die (115a, 115b) and the substrate (<NUM>); and
a frame (<NUM>) disposed over the substrate (<NUM>), wherein the frame (<NUM>) is adjacent to the semiconductor die (115a, 115b), and an upper surface of the frame (<NUM>) is lower than an upper surface of the semiconductor die (115a, 115b);
comprising a buffer layer (<NUM>) disposed over the substrate (<NUM>), wherein the buffer layer (<NUM>) is located between the frame (<NUM>) and the semiconductor die (115a, 115b);
further comprising a heat sink (<NUM>) disposed over the semiconductor die, wherein the heat sink (<NUM>) is in contact with at least one of the semiconductor die (115a, 115b), and the buffer layer (<NUM>) and is separate from the frame (<NUM>).