Patent Description:
Conventionally, a synchronous solid-state imaging element for capturing image data (frame) in synchronization with a synchronous signal such as a vertical synchronous signal has been used in an imaging device or the like. The typical synchronous solid-state imaging element can acquire the image data only at each cycle (for example, <NUM>/<NUM> seconds) of the synchronous signal, and is thus difficult to deal with a case where higher-speed processing is required in the fields of transportation, robots, and the like. Therefore, an asynchronous solid-state imaging element provided with a detection circuit for each pixel, the detection circuit detecting that, for each pixel address, a change amount of a light amount of the pixel has exceeded a threshold as an address event in real time has been proposed (for example, see Non-Patent Document <NUM>). Such a solid-state imaging element for detecting an address event for each pixel is called dynamic vision sensor (DVS).

<CIT> describes an image processing device including a vision sensor and a processor. The vision sensor generates a plurality of events in which an intensity of light changes and generates a plurality of timestamps depending on times when the events occur. In addition, the processor may regenerate a timestamp of a pixel where an abnormal event occurs, based on temporal correlation of the events.

Document "<NPL>, describes an asynchronous event-driven-address time-stamped (EDATS) pixelated array detector, operational over correlation time spans ranging from less than <NUM>-<NUM> to greater than <NUM><NUM> seconds, was designed, fabricated, and tested. Its performance was validated for use in X-ray photon correlation spectroscopy (XPCS) experiments. The EDATS pixelated detector arrays each include a custom readout integrated circuit (ROIC), the Voxtel model VX-<NUM>, hybridized to a silicon photodiode array optimized for <NUM> eV to <NUM> eV X-ray photons. The <NUM> x <NUM>-element array is composed of each <NUM>-micrometer x <NUM>-micrometer pixel unit cell. The unit cell circuits of the VX-<NUM> ROIC include a low-noise capacitive transimpedence amplifier (CTIA) followed by a C-RC shaping amplifier. These analog front-end (AFE) circuits are used to convert the absorbed X-ray photon signal to a voltage pulse, which may trigger a user-programmable threshold comparator. The detected X-ray photon events are broadcast to token-based address arbitration circuits, at the periphery of the X-ray sensitive pixel array, which recover the address of the photon event and communicate the address to a time-to-digital converter (TDC), where the address is time stamped, with a maximum temporal jitter of <NUM> nanoseconds.

<CIT> describes an imaging apparatus including a correction section configured to amplify an addition pixel value, which is a value obtained by adding results of photoelectric conversion on a plurality of pixels, according to an amplification factor set based on a number of defective pixels included in the plurality of pixels, and output the amplified addition pixel value as a corrected addition pixel value.

<CIT> relates to a photoarray, comprising: a plurality of cells, wherein each of said cells comprises a means that is configured to generate a photocurrent being proportional to the intensity of the light impinging on the respective cell, and wherein each of said cells comprises a change detection circuit connected to the respective means for generating the photocurrent, which change detection circuit is configured to generate an output signal merely in case a change event occurs at which said intensity changes by a threshold amount since the preceding change event from the respective cell. According to the invention said means for generating said photocurrent is additionally also used to estimate the magnitude of the said photocurrent being a measure of the brightness of the light at the respective cell.

The above-described asynchronous solid-state imaging element (DVS) generates data at a much higher speed than the synchronous solid-state imaging element. However, in the above-described DVS, pixels with abnormal behavior may occur due to various factors such as dark current noise and defective elements. For example, an address event is erroneously detected even though there is no change in the incident light. When such an abnormal pixel erroneously detects an address event, various adverse effects such as a decrease in image recognition accuracy and an increase in power consumption may occur.

The present technology has been made in view of such a situation, and an object is to suppress erroneous detection of an address event in a solid-state imaging element that detects the presence or absence of an address event.

The present technology has been made to solve the above-described problem and the first aspect is a solid-state imaging element as set out in independent claim <NUM>, including a plurality of pixel circuits each configured to execute detection processing of detecting whether or not a change amount of an incident light amount exceeds a predetermined threshold and outputting a detection result, an abnormal pixel determination unit configured to determine whether or not each of the plurality of pixel circuits has an abnormality, and set a pixel circuit without the abnormality to be enabled and set a pixel circuit with the abnormality to be disabled, and a control unit configured to perform control of causing the pixel circuit set to be enabled to execute the detection processing and control of fixing the detection result of the pixel circuit set to be disabled to a specific value. This brings about an effect that the detection result of the abnormal pixel circuit is fixed.

Furthermore, in the first aspect, each of the plurality of pixel circuits may include a logarithmic response unit in which a photoelectric conversion element configured to generate a photocurrent by photoelectric conversion and a current-voltage conversion unit configured to convert the photocurrent into a voltage are arranged, a buffer configured to output the voltage, a differential circuit configured to generate a differential signal indicating a change amount of the output voltage by differential operation, a comparator configured to compare the differential signal with the threshold, and a transfer unit configured to transfer a comparison result of the comparator as the detection result, and any of the logarithmic response unit, the buffer, the differential circuit, and the comparator may include a switch that opens or closes a predetermined path according to control of the control unit. This brings about an effect that the detection result is fixed by the switch.

Furthermore, in the first aspect, the control unit may control the switch of the pixel circuit set to be disabled to be in an open state. This brings about an effect that the detection result is fixed by the switch in the open state.

The switch may be inserted between the photoelectric conversion element and the current-voltage conversion unit. This brings about an effect that the photoelectric conversion element is cut off.

Furthermore, in the first aspect, the current-voltage conversion unit may include a transistor and a switch connected in series to the photoelectric conversion element, and the switch may be inserted in at least one of a path between the photoelectric conversion element and the transistor or a path between the transistor and a power supply terminal. This brings about an effect that the current is cut off.

Furthermore, in the first aspect, the buffer may include first and second transistors connected in series, and the switch may be inserted at least one of between the first and second transistors or between a connection point of the first and second transistors and the differential circuit. This brings about an effect that an output voltage of the buffer is cut off.

Furthermore, in the first aspect, the differential circuit may include a capacitance configured to output a charge according to the change amount of the voltage to a predetermined input terminal, and an inverting circuit configured to output a signal of an inverted voltage of the input terminal as the differential signal, and the switch may be inserted between the capacitance and the input terminal. This brings about an effect that the differential signal is cut off.

Furthermore, in the first aspect, the switch may be inserted between an output node of the comparator and the transfer unit. This brings about an effect that the comparison result of the comparator is cut off.

Furthermore, in the first aspect, the control unit may control the switch of the pixel circuit set to be disabled to be in a close state. This brings about an effect that the detection result is fixed by the switch in the close state.

Furthermore, in the first aspect, the switch may be inserted between a connection point of the current-voltage conversion unit and the photoelectric conversion element and a predetermined reference terminal. This brings about an effect that an input side of the current-voltage conversion unit is short-circuited.

Furthermore, in the first aspect, the switch may be inserted between a connection point of the current-voltage conversion unit and the buffer and a predetermined reference terminal. This brings about an effect that an output side of the current-voltage conversion unit is short-circuited.

Furthermore, in the first aspect, the switch may be inserted between a connection point of the buffer and the differential circuit and a predetermined reference terminal. This brings about an effect that an output terminal of the buffer is short-circuited.

Furthermore, in the first aspect, the differential circuit may include a capacitance configured to output a charge according to the change amount of the voltage to a predetermined input terminal, and an inverting circuit configured to output a signal of an inverted voltage of the input terminal as the differential signal, and the switch may be inserted between the input terminal and an output terminal of the inverting circuit. This brings about an effect that the differential circuit is initialized.

Furthermore, in the first aspect, the differential circuit may include a capacitance configured to output a charge according to the change amount of the voltage to a predetermined input terminal, an inverting circuit configured to output a signal of an inverted voltage of the input terminal as the differential signal, and a short-circuit transistor configured to short-circuit between the input terminal and an output terminal of the inverting circuit according to an auto-zero signal from the transfer unit, the auto-zero signal instructing initialization, and the switch may be inserted between a gate of the short-circuit transistor and the transfer unit. This brings about an effect that the differential circuit is initialized.

Furthermore, in the first aspect, the switch may be inserted between an output terminal of the comparator and a predetermined terminal. This brings about an effect that the output terminal of the comparator is short-circuited.

Furthermore, in the first aspect, the abnormal pixel determination unit may determine whether or not each of the plurality of pixel circuits has an abnormality before execution of the detection processing. This brings about an effect that the presence or absence of abnormalities due to static factors is determined.

Furthermore, in the first aspect, the abnormal pixel determination unit may determine whether or not each of the plurality of pixel circuits has an abnormality during execution of the detection processing. This brings about an effect that the presence or absence of abnormalities due to dynamic factors is determined.

Furthermore, in the first aspect, the abnormal pixel determination unit may include a plurality of abnormal pixel determination circuits, the plurality of abnormal pixel determination circuits may be arranged in pixels different from one another, and the plurality of pixel circuits may be arranged in pixels different from one another. This brings about an effect that the presence or absence of an abnormality is determined by the circuit provided for each pixel.

Furthermore, in the first aspect, the above specific value may be a value indicating that the change amount does not exceed the threshold. This brings about an effect that the detection result is fixed to a value of when an address event does not occur.

Furthermore, the second aspect of the present technology is an imaging device including a plurality of pixel circuits each configured to execute detection processing of detecting whether or not a change amount of an incident light amount exceeds a predetermined threshold and outputting a detection result, an abnormal pixel determination unit configured to determine whether or not each of the plurality of pixel circuits has an abnormality, and set a pixel circuit without the abnormality to be enabled and set a pixel circuit with the abnormality to be disabled, a control unit configured to perform control of causing the pixel circuit set to be enabled to execute the detection processing and control of fixing the detection result of the pixel circuit set to be disabled to a specific value, and a signal processing unit configured to process the detection result. This brings about an effect that the detection result of the pixel circuit without an abnormality is processed, and the detection result of the pixel circuit with an abnormality is fixed.

Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. Description will be given according to the following order.

<FIG> is a block diagram illustrating a configuration example of an imaging device <NUM> according to a first embodiment of the present technology. The imaging device <NUM> includes an imaging lens <NUM>, a solid-state imaging element <NUM>, a recording unit <NUM>, and a control unit <NUM>. As the imaging device <NUM>, a camera mounted on an industrial robot, an in-vehicle camera, or the like is assumed.

The imaging lens <NUM> condenses incident light and guides the incident light to the solid-state imaging element <NUM>. The solid-state imaging element <NUM> photoelectrically converts the incident light to detect the presence or absence of an address event, and generates a detection result of the detection. Here, the address event includes an on-event and an off-event, and the detection result includes a one-bit on-event detection result and a one-bit off-event detection result. The on-event means that a change amount of an incident light amount has exceeded a predetermined upper limit threshold. Meanwhile, the off-event means that the change amount of the light amount has fallen below a predetermined lower limit threshold. The solid-state imaging element <NUM> processes the detection result of the address event and outputs data indicating a processing result to the recording unit <NUM> via a signal line <NUM>. Note that the solid-state imaging element <NUM> may detect only one of the on-event and the off-event.

The recording unit <NUM> records the data from the solid-state imaging element <NUM>. The control unit <NUM> controls the solid-state imaging element <NUM> to detect the presence or absence of an address event.

<FIG> is a diagram illustrating an example of a stacked structure of the solid-state imaging element <NUM> according to the first embodiment of the present technology. The solid-state imaging element <NUM> includes a circuit chip <NUM> and a light-receiving chip <NUM> stacked on the circuit chip <NUM>. These chips are electrically connected via a connection part such as a via. Note that Cu-Cu bonding or bump can be used for connection in addition to the via.

<FIG> is a block diagram illustrating a configuration example of the solid-state imaging element <NUM> according to the first embodiment of the present technology. The solid-state imaging element <NUM> includes a drive circuit <NUM>, an arbiter <NUM>, a pixel array unit <NUM>, a signal processing unit <NUM>, an abnormal pixel determination unit <NUM>, and a setting information holding unit <NUM>. In the pixel array unit <NUM>, a plurality of pixels <NUM> is arrayed in a two-dimensional lattice manner.

The pixel <NUM> detects the presence or absence of an address event on the basis of setting information held in the setting information holding unit <NUM>. When detecting an address event, the pixel <NUM> supplies a request for requesting transfer of a detection signal indicating a detection result to the arbiter <NUM>. Then, when receiving a response to the request, the pixel <NUM> supplies the detection signal to the signal processing unit <NUM>.

The arbiter <NUM> arbitrates requests from respective pixel blocks, and transmits a response to the pixel <NUM> on the basis of an arbitration result.

The signal processing unit <NUM> executes predetermined signal processing such as image recognition processing for the detection signal from the pixel array unit <NUM>. A mode signal MODE from the control unit <NUM> is input to the signal processing unit <NUM>. The mode signal MODE is a signal indicating one of a plurality of modes including a detection mode and an abnormality determination mode. In the detection mode, the solid-state imaging element <NUM> detects the presence or absence of an address event for each pixel. Meanwhile, in the abnormality determination mode, whether or not the pixel is abnormal is determined for each pixel.

Here, the "abnormality" means that the behavior of the pixel is different from that assumed in the design. For example, when a large number of address events occur even though there is no change in the incident light amount, the pixels blink in the image data in which the detection results of the address events are arrayed. Further, when the state in which the address event occurs continues even though there is a change in the incident light amount, the pixel becomes a white spot in the image data. Furthermore, in a case where a pixel receives a flicker light source, an address event periodically occurs regardless of the presence or absence of a change in light from an object other than the light source, and the pixel blinks. These behaviors are treated as abnormal behaviors.

Factors that cause such abnormalities can be divided into static factors and dynamic factors. As the static factors, noise such as dark current noise, product variation of an element, defective element in the pixel, and the like are assumed. As the dynamic factors, aging deterioration, irradiation with a flicker light source, and the like are assumed.

The signal processing unit <NUM> executes signal processing for the detection signal in the detection mode, and supplies processed data to the recording unit <NUM>. Meanwhile, in the abnormality determination mode, the signal processing unit <NUM> supplies the detection signal to the abnormal pixel determination unit <NUM>.

The abnormal pixel determination unit <NUM> determines, for each pixel, whether or not the pixel is abnormal. The abnormality determination in the abnormality determination mode is executed, for example, before address event detection processing, for example, at the time of shipment from a factory or at the time of repair. In the abnormality determination mode, the abnormal pixel determination unit <NUM> generates setting information setting pixels without abnormality to be enabled and pixels with abnormality to be disabled, and causes the setting information holding unit <NUM> to hold the setting information. This setting information includes one-bit enable information indicating whether or not the pixel is enabled for each pixel. For example, in a case where the number of pixels is N, N-bit setting information is held.

By the abnormal pixel determination unit <NUM> determining the presence or absence of an abnormality in advance before the address event detection processing, erroneous detection of an address event due to the static factors such as a defective element can be suppressed. Note that a method for suppressing erroneous detection of an address event due to the dynamic factors such as irradiation with a flicker light source irradiation will be described below.

The setting information holding unit <NUM> holds the setting information. The setting information holding unit <NUM> includes, for example, a memory that cannot be rewritten. A read only memory (ROM), an eFuse register, or the like is used as the non-rewritable memory. Furthermore, the setting information holding unit <NUM> supplies each enable information in the held setting information to the corresponding pixel, thereby causing the pixel set to be enabled to execute the address event detection processing, and fixes the detection signal of the pixel set to be disabled to a specific value. Note that the setting information holding unit <NUM> is an example of a control unit described in the claims.

The drive circuit <NUM> drives each of the pixels <NUM>. The arbiter <NUM> arbitrates requests from the pixel array unit <NUM> and returns a response on the basis of an arbitration result.

<FIG> is a block diagram illustrating a configuration example of the pixel <NUM> according to the first embodiment of the present technology. The pixel <NUM> is provided with a pixel circuit <NUM>, and a logarithmic response unit <NUM>, a buffer <NUM>, a differential circuit <NUM>, a comparator <NUM>, and a transfer unit <NUM> are arranged in the pixel circuit <NUM>.

The logarithmic response unit <NUM> converts a photocurrent into a pixel voltage Vp proportional to a logarithmic value of the photocurrent. The logarithmic response unit <NUM> supplies the pixel voltage Vp to the buffer <NUM>.

The buffer <NUM> outputs the pixel voltage Vp from the logarithmic response unit <NUM> to the differential circuit <NUM>. The buffer <NUM> can improve a drive force for driving a rear stage. Furthermore, the buffer <NUM> can secure isolation of noise associated with a rear-stage switching operation.

The differential circuit <NUM> obtains the change amount of the pixel voltage Vp by differential operation. The change amount of the pixel voltage Vp indicates the change amount of the light amount. The differential circuit <NUM> supplies a differential signal Vout indicating the change amount of the light amount to the comparator <NUM>.

The comparator <NUM> compares the differential signal Vout with the predetermined threshold (upper limit threshold or lower limit threshold). A comparison result COMP of the comparator <NUM> indicates the detection result of the address event. The comparator <NUM> supplies the comparison result COMP to the transfer unit <NUM>.

The transfer unit <NUM> transfers a detection signal DET and supplies an auto-zero signal XAZ to the differential circuit <NUM> for initialization after the transfer. The transfer unit <NUM> supplies a request for requesting transfer of the detection signal DET to the arbiter <NUM> when the address event is detected. Then, when receiving a response to the request, the transfer unit <NUM> supplies the comparison result COMP as the detection signal DET to the signal processing unit <NUM> and supplies the auto-zero signal XAZ to the differential circuit <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to the first embodiment of the present technology.

The logarithmic response unit <NUM> includes a photoelectric conversion element <NUM>, a switch <NUM>, and a current-voltage conversion unit <NUM>. The photoelectric conversion element <NUM> generates a photocurrent by photoelectric conversion for incident light.

The switch <NUM> opens or closes a path between the photoelectric conversion element <NUM> and the current-voltage conversion unit <NUM> according to enable information EN from the setting information holding unit <NUM>. This switch <NUM> transitions to a close state in the case of being set to be enabled by the enable information EN and transitions to an open state in the case of being set to be disabled by the enable information EN. For example, a metal-oxide-semiconductor (MOS) transistor is used as the switch <NUM>.

The current-voltage conversion unit <NUM> logarithmically converts the photocurrent into a pixel voltage Vp. The current-voltage conversion unit <NUM> includes N-type transistors <NUM> and <NUM>, a capacitance <NUM>, and a P-type transistor <NUM>. As the N-type transistor <NUM>, the P-type transistor <NUM>, and the N-type transistor <NUM>, a MOS transistor is used, for example.

A source of the N-type transistor <NUM> is connected to the switch <NUM> and a drain of the N-type transistor <NUM> is connected to the power supply terminal. The P-type transistor <NUM> and the N-type transistor <NUM> are connected in series between the power supply terminal and a reference terminal having a predetermined reference potential (ground potential or the like). Furthermore, a connection point between the P-type transistor <NUM> and the N-type transistor <NUM> is connected to a gate of the N-type transistor <NUM> and an input terminal of the buffer <NUM>. A connection point between the N-type transistor <NUM> and the photoelectric conversion element <NUM> is connected to a gate of the N-type transistor <NUM>. In this way, the N-type transistors <NUM> and <NUM> are connected in a loop manner. Note that the circuit including the N-type transistors <NUM> and <NUM> connected in a loop manner is an example of a loop circuit described in the claims.

Furthermore, a predetermined bias voltage Vblog is applied to a gate of the P-type transistor <NUM>. The capacitance <NUM> is inserted between the gate of the N-type transistor <NUM> and the gate of the N-type transistor <NUM>.

Furthermore, for example, the photoelectric conversion element <NUM> and the switch <NUM> are arranged on the light-receiving chip <NUM>, and a rear-stage circuit is arranged on the circuit chip <NUM>. Note that the circuits and elements arranged on the light-receiving chip <NUM> and the circuit chip <NUM> are not limited to this configuration.

The buffer <NUM> includes P-type transistors <NUM> and <NUM>. For example, a MOS transistor is used as the transistors.

In the buffer <NUM>, the P-type transistors <NUM> and <NUM> are connected in series between the power supply terminal and the reference potential terminal. Furthermore, a gate of the P-type transistor <NUM> is connected to the logarithmic response unit <NUM>, and a connection point of the P-type transistors <NUM> and <NUM> is connected to the differential circuit <NUM>. A predetermined bias voltage Vbsf is applied to a gate of the P-type transistor <NUM>.

The differential circuit <NUM> includes capacitances <NUM> and <NUM>, P-type transistors <NUM> and <NUM>, and an N-type transistor <NUM>. For example, MOS transistors are used as transistors in the differential circuit <NUM>.

The P-type transistor <NUM> and the N-type transistor <NUM> are connected in series between the power supply terminal and the reference potential terminal. A predetermined bias voltage Vbdiff is input to a gate of the N-type transistor <NUM>. These transistors function as an inverting circuit having the gate of the P-type transistor <NUM> as an input terminal <NUM> and the connection point of the P-type transistor <NUM> and the N-type transistor <NUM> as an output terminal <NUM>.

The capacitance <NUM> is inserted between the buffer <NUM> and the input terminal <NUM>. The capacitance <NUM> supplies to a current according to time derivative of (in other words, the change amount in) the pixel voltage Vp from the buffer <NUM> to the input terminal <NUM>. Furthermore, the capacitance <NUM> is inserted between the input terminal <NUM> and the output terminal <NUM>.

The P-type transistor <NUM> opens or closes a path between the input terminal <NUM> and the output terminal <NUM> according to the auto-zero signal XAZ from the transfer unit <NUM>. For example, when the low-level auto-zero signal XAZ is input, the P-type transistor <NUM> transitions to the on state according to the auto-zero signal XAZ and sets the differential signal Vout to the initial value.

The comparator <NUM> includes P-type transistors <NUM> and <NUM> and N-type transistors <NUM> and <NUM>. For example, a MOS transistor is used as the transistors.

In the comparator <NUM>, the P-type transistor <NUM> and the N-type transistor <NUM> are connected in series between the power supply terminal and the reference terminal, and the P-type transistor <NUM> and the N-type transistor <NUM> are also connected in series between the power supply terminal and the reference terminal. Furthermore, gates of the P-type transistors <NUM> and <NUM> are connected to the differential circuit <NUM>. An upper limit voltage Vhigh indicating an upper limit threshold is applied to a gate of the N-type transistor <NUM>, and a lower limit voltage Vlow indicating a lower limit threshold is applied to a gate of the N-type transistor <NUM>.

A connection point of the P-type transistor <NUM> and the N-type transistor <NUM> is connected to the transfer unit <NUM>, and a voltage at this connection point is output as a comparison result COMP+ with respect to the upper limit threshold. A connection point of the P-type transistor <NUM> and the N-type transistor <NUM> is also connected to the transfer unit <NUM>, and a voltage at this connection point is output as a comparison result COMP- with respect to the lower limit threshold. With such a connection, the comparator <NUM> outputs the high-level comparison result COMP+ in a case where the differential signal Vout is higher than the upper limit voltage Vhigh, and outputs the low-level comparison result COMP-in a case where the differential signal Vout is lower than the lower limit voltage Vlow. The comparison result COMP is a signal including these comparison results COMP+ and COMP-.

As described above, the switch <NUM> transitions to the close state in the case of being set to be enabled by the enable information EN. Thereby, the address event detection processing is executed. Meanwhile, the switch <NUM> transitions to the open state in the case of being set to be disabled by the enable information EN. In this state, the photoelectric conversion element <NUM> is cut off from the rear-stage circuit and the detection processing is not executed. Then, the detection signal is fixed to the specific value indicating that the address event does not occur (in other words, the change amount of the incident light amount does not exceed the threshold).

Note that the switch <NUM> is inserted between the photoelectric conversion element <NUM> and the current-voltage conversion unit <NUM>, but the insertion position of the switch <NUM> is not limited to this position. As will be described below, the switch <NUM> can be inserted into a path after the current-voltage conversion unit <NUM>.

Furthermore, the comparator <NUM> compares both the upper limit threshold and the lower limit threshold with the differential signal Vout. However, the comparator <NUM> may compare only one of the upper limit threshold and the lower limit threshold with the differential signal Vout. In this case, unnecessary transistors can be eliminated. For example, when comparing the differential signal Vout only with the upper limit threshold, only the P-type transistor <NUM> and the N-type transistor <NUM> are arranged.

Furthermore, the capacitance <NUM> is arranged in the differential circuit <NUM>, but the capacitance <NUM> can be reduced as illustrated in <FIG>.

<FIG> is a block diagram illustrating a configuration example of the signal processing unit <NUM> according to the first embodiment of the present technology. The signal processing unit <NUM> includes a selector <NUM> provided for each column and a signal processing circuit <NUM>.

The selector <NUM> switches an output destination of the detection signal DET from a corresponding column in the pixel array unit <NUM> according to the mode signal MODE. The selector <NUM> outputs the detection signal DET to the signal processing circuit <NUM> in the detection mode, and outputs the detection signal DET to the abnormal pixel determination unit <NUM> in the abnormality determination mode.

The signal processing circuit <NUM> performs predetermined signal processing for the detection signal DET and outputs processed data to the recording unit <NUM>.

<FIG> is a block diagram illustrating a configuration example of the abnormal pixel determination unit <NUM> according to the first embodiment of the present technology. The abnormal pixel determination unit <NUM> includes a detection count counting unit <NUM> and a threshold comparison unit <NUM>.

The detection count counting unit <NUM> counts the number of times an address event has been detected for each pixel in the abnormality determination mode. In the abnormality determination mode, the solid-state imaging element <NUM> detects the presence or absence of an address event for each pixel for a certain period of time in a state where the incident light amount has no change (for example, in a shaded state). The detection count counting unit <NUM> counts the number of times within this period and supplies a detection count for each pixel to the threshold comparison unit <NUM>.

The threshold comparison unit <NUM> compares the corresponding detection count with a predetermined determination threshold for each pixel. As described above, since an address event is supposed not to occur in the state where the incident light amount has no change, a pixel in which the detection count of an address event exceeds the determination threshold in this state can be determined to be abnormal. The threshold comparison unit <NUM> determines whether or not the detection count exceeds the determination threshold (that is, presence or absence of abnormality) for each pixel, and causes the setting information holding unit <NUM> to hold information indicating a determination result for each pixel as the setting information.

Note that the detection count counting unit <NUM> and the threshold comparison unit <NUM> are provided in the abnormal pixel determination unit <NUM>. However, a plurality of counters <NUM> may be arranged instead of the detection count counting unit <NUM> and the threshold comparison unit <NUM>. In this case, for example, as illustrated in <FIG>, an N-bit (N is an integer) counter <NUM> is arranged for each pixel. In the counter <NUM>, N-stage n-th digit output units <NUM> that each output the n-th (n is an integer from <NUM> to N-<NUM>) digit and N switches <NUM> are arranged. The detection signal DET+ of a corresponding pixel is input to the n-th digit output unit <NUM> of the lowest digit. <FIG> assumes a case of detecting only on-events. Furthermore, the N switches <NUM> do not output any N digits at the start of the abnormality determination mode, and output any of the N digits as the enable information EN of the pixel to the setting information holding unit <NUM> according to the control signal SW when a certain time elapses. The n-th digit becomes at a high level when a count value becomes <NUM>n in the case of a binary counter. When the switch <NUM> outputs the n-th digit, <NUM>n corresponds to the threshold.

<FIG> is a flowchart illustrating an example of the abnormality determination processing according to the first embodiment of the present technology. The abnormality determination processing is started when the mode signal MODE indicating the abnormality determination mode is input.

In the abnormality determination mode, each of the pixels <NUM> detects the presence or absence of an address event (step S901), and the abnormal pixel determination unit <NUM> counts the detection count of the address event for each pixel (step S902). Then, the solid-state imaging element <NUM> determines whether or not an elapsed time from the time when the detection of an address event is started becomes longer than a predetermined set time (step S903). In a case where the elapsed time is equal to or less than the set time (step S903: No), the solid-state imaging element <NUM> repeatedly executes step S901 and the subsequent steps.

On the other hand, in a case where the elapsed time is longer than the predetermined set time (step S903: Yes), the abnormal pixel determination unit <NUM> focuses on a certain pixel and determines whether or not the count value of the pixel exceeds the determination threshold (that is, whether or not the pixel is abnormal) (step S904). In a case where the count value exceeds the determination threshold (step S904: Yes), the abnormal pixel determination unit <NUM> sets the pixel of interest to be disable in the setting information (step S905).

On the other hand, in a case where the count value is equal to or smaller than the determination threshold (step S904: No), the abnormal pixel determination unit <NUM> sets the pixel of interest to be enable in the setting information (step S906). After step S905 or S906, the abnormal pixel determination unit <NUM> determines whether or not the determination of the presence or absence of abnormality has been completed for all the pixels (step S907). In a case where the determination for all the pixels has not been completed (step S907: No), the abnormal pixel determination unit <NUM> repeats step S904 and the subsequent steps. On the other hand, in a case where the determination for all the pixels has been completed (step S907: Yes), the abnormal pixel determination unit <NUM> holds the setting information and terminates the abnormality determination processing.

<FIG> is a flowchart illustrating an example of detection processing according to the first embodiment of the present technology. The detection processing is started when the mode signal MODE indicating the detection mode is input.

The switch <NUM> in the pixel <NUM> determines whether or not the enable information EN is enabled (step S911). In a case where the enable information EN is disabled (step S911: No), the switch <NUM> transitions to the open state and repeats step S911 and the subsequent steps.

On the other hand, in a case where the enable information EN is enabled (step S911: Yes), the switch <NUM> transitions to the close state, and the logarithmic response unit <NUM> converts the photocurrent into the pixel voltage (step S912). The differential circuit <NUM> outputs an output voltage Vout according to a change amount in brightness (step S913). The comparator <NUM> compares the output voltage Vout with an upper limit threshold and determines whether or not the change amount in brightness exceeds the upper limit threshold (step S914).

In a case where the change amount exceeds the upper limit threshold (step S914: Yes), the comparator <NUM> detects an on-event (step S915). On the other hand, in a case where the change amount is equal to or less than the upper limit threshold (step S914: No), the comparator <NUM> compares the differential signal Vout with the lower limit threshold and determines whether or not the change amount in brightness falls below the lower limit threshold (step S917).

In a case where the change amount falls below the lower limit threshold (step S917: Yes), the comparator <NUM> detects an off-event (step S918). On the other hand, in a case where the change amount is equal to or larger than the lower limit threshold (step S917: No), the pixel <NUM> repeats step S912 and the subsequent steps.

After step S915 or S918, the transfer unit <NUM> transfers the detection result (step S916) and repeatedly executes step S912 and the subsequent steps.

In a synchronous solid-state imaging element that captures an image in synchronization with a vertical synchronous signal or the like, an output of an abnormal pixel such as a blinking point or a white spot is the same amount as that of a normal pixel, and there is no particular effect on readout. However, in a DVS such as the solid-state imaging element <NUM>, when an abnormal pixel detection signal is output, the signal occupies a part of an output interface band and is output mixed with a normal pixel detection signal. Furthermore, the detection signal of an abnormal pixel (in other words, noise) increases the power consumption of the solid-state imaging element <NUM>, and the increase in noise lowers the recognition accuracy in the processing such as image recognition.

Assuming that the number of pixels is <NUM> × <NUM> pixels (that is, <NUM> megapixels) and <NUM>% of the number of pixels are abnormal pixels, the abnormal pixels are <NUM> pixels. In addition, it is assumed that the abnormal pixel blinks twice on average in one second, and one blinking causes ten address events. In this case, the band for <NUM> events per second is wasted. Furthermore, assuming that the power consumption when one address event occurs is <NUM> nanowatts (nW), the power consumption by the abnormal pixel is <NUM> milliwatts (mW). Assuming that the power consumption when one address event occurs is <NUM> nanowatts (nW), the power consumption by the abnormal pixel is <NUM> milliwatts (mW).

In contrast, the above-described solid-state imaging element <NUM> sets abnormal pixels to be disabled to suppress erroneous detection of address events, thereby reducing the power consumption and widening the band for transferring the detection signals of normal pixels.

As described above, according to the first embodiment of the present technology, since the value of the detection signal of the abnormal pixel is fixed to a specific value indicating that an address event does not occur, erroneous detection of the address event by the abnormal pixel can be suppressed.

In the above-described first embodiment, the photoelectric conversion element <NUM> and the switch <NUM> have been provided on the light-receiving chip <NUM>, but in this configuration, the circuit scale of the circuit chip <NUM> increases as the number of pixels increases. The solid-state imaging element <NUM> of a first modification of the first embodiment is different from that of the first embodiment in that a part of the circuit of the current-voltage conversion unit <NUM> and the subsequent elements is further provided on the light-receiving chip <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to the first modification of the first embodiment of the present technology. The pixel <NUM> of the first modification of the first embodiment is different from that of the first embodiment in that the N-type transistors <NUM> and <NUM> and the capacitance <NUM> are further provided on the light-receiving chip <NUM>. In the case where an N-type MOS transistor is used as the switch <NUM>, the transistors in the light-receiving chip <NUM> can be limited to the N-type transistors. Thereby, the number of steps for forming the transistors can be reduced as compared with the case where N-type transistors and P-type transistors are mixed, and the manufacturing cost of the light-receiving chip <NUM> can be reduced.

As described above, according to the first modification of the first embodiment of the present technology, the N-type transistors <NUM> and <NUM> and the capacitance <NUM> are further provided on the light-receiving chip <NUM>. Therefore, the circuit scale of the circuit chip <NUM> can be reduced.

In the above-described first embodiment, the photoelectric conversion element <NUM> and the switch <NUM> have been provided on the light-receiving chip <NUM>, but in this configuration, the circuit scale of the circuit chip <NUM> increases as the number of pixels increases. The solid-state imaging element <NUM> of a second modification of the first embodiment is different from that of the first embodiment in that a part of the circuit of the current-voltage conversion unit <NUM> and the subsequent elements is further provided on the light-receiving chip <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to the second modification of the first embodiment of the present technology. The pixel <NUM> of the second modification of the first embodiment is different from that of the first embodiment in that the current-voltage conversion unit <NUM> and the P-type transistor <NUM> in the buffer <NUM> are further provided on the light-receiving chip <NUM>.

As described above, according to the second modification of the first embodiment of the present technology, the current-voltage conversion unit <NUM> and the P-type transistor <NUM> in the buffer <NUM> are further provided on the light-receiving chip <NUM>. Therefore, the circuit scale of the circuit chip <NUM> can be reduced.

In the above-described first embodiment, the photoelectric conversion element <NUM> and the switch <NUM> have been provided on the light-receiving chip <NUM>, but in this configuration, the circuit scale of the circuit chip <NUM> increases as the number of pixels increases. The solid-state imaging element <NUM> of a third modification of the first embodiment is different from that of the first embodiment in that a part of the circuit of the current-voltage conversion unit <NUM> and the subsequent elements is further provided on the light-receiving chip <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to the third modification of the first embodiment of the present technology. The pixel <NUM> of the third modification of the first embodiment is different from that of the first embodiment in that the current-voltage conversion unit <NUM> and the buffer <NUM> are further provided on the light-receiving chip <NUM>.

As described above, according to the third modification of the first embodiment of the present technology, the current-voltage conversion unit <NUM> and the buffer <NUM> are further provided on the light-receiving chip <NUM>. Therefore, the circuit scale of the circuit chip <NUM> can be reduced.

In the above-described first embodiment, the photoelectric conversion element <NUM> and the switch <NUM> have been provided on the light-receiving chip <NUM>, but in this configuration, the circuit scale of the circuit chip <NUM> increases as the number of pixels increases. The solid-state imaging element <NUM> of a fourth modification of the first embodiment is different from that of the first embodiment in that a part of the circuit of the current-voltage conversion unit <NUM> and the subsequent elements is further provided on the light-receiving chip <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to a fourth modification of the first embodiment of the present technology. The pixel <NUM> of the fourth modification of the first embodiment is different from that of the first embodiment in that the current-voltage conversion unit <NUM> and the buffer <NUM>, and the capacitance <NUM> in the differential circuit <NUM> are further provided on the light-receiving chip <NUM>.

As described above, according to the fourth modification of the first embodiment of the present technology, the current-voltage conversion unit <NUM> and the buffer <NUM>, and the capacitance <NUM> are further provided on the light-receiving chip <NUM>. Therefore, the circuit scale of the circuit chip <NUM> can be reduced.

In the above-described first embodiment, the photoelectric conversion element <NUM> and the switch <NUM> have been provided on the light-receiving chip <NUM>, but in this configuration, the circuit scale of the circuit chip <NUM> increases as the number of pixels increases. The solid-state imaging element <NUM> of a fifth modification of the first embodiment is different from that of the first embodiment in that a part of the circuit of the current-voltage conversion unit <NUM> and the subsequent elements is further provided on the light-receiving chip <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to the fifth modification of the first embodiment of the present technology. The pixel <NUM> of the fifth modification of the first embodiment is different from that of the first embodiment in that the current-voltage conversion unit <NUM> and the buffer <NUM>, and the elements other than the N-type transistor <NUM> in the differential circuit <NUM> are further provided on the light-receiving chip <NUM>.

As described above, according to the fifth modification of the first embodiment of the present technology, the current-voltage conversion unit <NUM> and the buffer <NUM>, and a part of the differential circuit <NUM> are further provided on the light-receiving chip <NUM>. Therefore, the circuit scale of the circuit chip <NUM> can be reduced.

In the above-described first embodiment, the photoelectric conversion element <NUM> and the switch <NUM> have been provided on the light-receiving chip <NUM>, but in this configuration, the circuit scale of the circuit chip <NUM> increases as the number of pixels increases. The solid-state imaging element <NUM> of a sixth modification of the first embodiment is different from that of the first embodiment in that a part of the circuit of the current-voltage conversion unit <NUM> and the subsequent elements is further provided on the light-receiving chip <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to the sixth modification of the first embodiment of the present technology. The pixel <NUM> of the sixth modification of the first embodiment is different from that of the first embodiment in that the current-voltage conversion unit <NUM>, the buffer <NUM>, and the differential circuit <NUM> are further provided on the light-receiving chip <NUM>.

As described above, according to the third modification of the first embodiment of the present technology, the current-voltage conversion unit <NUM>, the buffer <NUM>, and the differential circuit <NUM> are further provided on the light-receiving chip <NUM>. Therefore, the circuit scale of the circuit chip <NUM> can be reduced.

In the above-described first embodiment, the photoelectric conversion element <NUM> has been cut off from the rear-stage circuit by the switch <NUM>, but there is a possibility that noise occurs in the rear-stage circuit and an address event is erroneously detected. A solid-state imaging element <NUM> according to a second embodiment is different from that of the first embodiment in that a switch is inserted into a rear-stage circuit of a photoelectric conversion element <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of a logarithmic response unit <NUM>, a buffer <NUM>, a differential circuit <NUM>, and a comparator <NUM> according to the second embodiment of the present technology. A pixel <NUM> of the second embodiment is different from that of the first embodiment in that a switch <NUM> is further provided in a current-voltage conversion unit <NUM>. Furthermore, a switch <NUM> of the second embodiment is inserted in a path between a photoelectric conversion element <NUM> and an N-type transistor <NUM> in a loop circuit. The switch <NUM> is inserted between the N-type transistor <NUM> and a power supply terminal in the loop circuit. The switch <NUM> transitions to an open state in a case of being set to be disabled by enable information EN and transitions to a close state in a case of being set to be enabled by the enable information EN. The transition to the open state of the switch <NUM> or <NUM> cuts off a current from the power supply, and can reliably suppress erroneous detection of an address event.

Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the second embodiment. Further, although both the switch <NUM> and the switch <NUM> are inserted, only one of them may be arranged. Only the switch <NUM> may be arranged, or only the switch <NUM> may be arranged.

As described above, according to the second embodiment of the present technology, since the switch <NUM> is further inserted between the N-type transistor <NUM> and the power supply terminal, the current from the power supply is further cut off and erroneous detection of the address event can be more reliably suppressed.

In the above-described second embodiment, the current has been cut off by the switches <NUM> and <NUM>, but there is a possibility that noise occurs in the rear-stage circuit of the buffer <NUM> or of the subsequent elements and an address event is erroneously detected. The solid-state imaging element <NUM> according to a first modification of the second embodiment is different from that of the second embodiment in that a switch is inserted to the circuit of the buffer <NUM> or a subsequent element.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, and the differential circuit <NUM> according to the first modification of the second embodiment of the present technology. The pixel <NUM> of the first modification of the second embodiment is different from that of the second embodiment in that switches <NUM> and <NUM> are provided instead of the switches <NUM> and <NUM>.

The switch <NUM> is inserted between P-type transistors <NUM> and <NUM> in the buffer <NUM>. Furthermore, the switch <NUM> is inserted between a connection point of the P-type transistor <NUM> and the switch <NUM> and the differential circuit <NUM>. Note that the P-type transistor <NUM> is an example of a first transistor described in the claims, and the P-type transistor <NUM> is an example of a second transistor described in the claims.

The switches <NUM> and <NUM> transition to an open state in a case of being set to be disabled by enable information EN and transition to a close state in a case of being set to be enabled by the enable information EN. The transitions to the open state of the switches <NUM> and <NUM> cut off a pixel voltage Vp from the logarithmic response unit <NUM> and can suppress erroneous detection of an address event.

Note that both the switches <NUM> and <NUM> are arranged, but only one of them can be arranged. Furthermore, each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the first modification of the second embodiment.

As described above, according to the first modification of the second embodiment of the present technology, since the switches <NUM> and <NUM> are provided in the buffer <NUM>, the pixel voltage Vp from the logarithmic response unit <NUM> in the front stage of the buffer <NUM> can be cut off. As a result, erroneous detection of an address event can be suppressed.

In the above-described second embodiment, the current has been cut off by the switches <NUM> and <NUM>, but there is a possibility that noise occurs in the rear-stage circuit of the buffer <NUM> or of the subsequent elements and an address event is erroneously detected. The solid-state imaging element <NUM> according to a second modification of the second embodiment is different from that of the second embodiment in that a switch is inserted to the circuit of the buffer <NUM> or a subsequent element.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, and the differential circuit <NUM> according to the second modification of the second embodiment of the present technology. The pixel <NUM> of the second modification of the second embodiment is different from that of the second embodiment in that a switch <NUM> is provided instead of the switches <NUM> and <NUM>.

The switch <NUM> is inserted between a capacitance <NUM> in the differential circuit <NUM> and an input terminal <NUM> of an inverting circuit. The switch <NUM> transitions to an open state in a case of being set to be disabled by enable information EN and transitions to a close state in a case of being set to be enabled by the enable information EN. The transition to the open state of the switch <NUM> cuts off a differential signal Vout and can suppress erroneous detection of an address event.

Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the second modification of the second embodiment.

As described above, according to the second modification of the second embodiment of the present technology, since the switch <NUM> is provided in the differential circuit <NUM>, the differential signal Vout can be cut off. As a result, erroneous detection of an address event can be suppressed.

In the above-described second embodiment, the current has been cut off by the switches <NUM> and <NUM>, but there is a possibility that noise occurs in the rear-stage circuit of the buffer <NUM> or of the subsequent elements and an address event is erroneously detected. The solid-state imaging element <NUM> according to a third modification of the second embodiment is different from that of the second embodiment in that a switch is inserted to the circuit of the buffer <NUM> or a subsequent element.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to the third modification of the second embodiment of the present technology. The pixel <NUM> of the third modification of the second embodiment is different from that of the second embodiment in that switches <NUM> and <NUM> are provided instead of the switches <NUM> and <NUM>.

The switch <NUM> is inserted between a connection point of a P-type transistor <NUM> and an N-type transistor <NUM> (in other words, an output node of the comparator <NUM>) and a transfer unit <NUM>. The switch <NUM> is inserted between a connection point of the P-type transistor <NUM> and an N-type transistor <NUM> (the output node of the comparator <NUM>) and the transfer unit <NUM>.

The switches <NUM> and <NUM> transition to an open state in a case of being set to be disabled by enable information EN and transition to a close state in a case of being set to be enabled by the enable information EN. The transitions to the open state of the switches <NUM> and <NUM> cut off a comparison result of the comparator <NUM> and can suppress erroneous detection of an address event.

Note that the pixel <NUM> detects both the on-event and off-event, but the pixel <NUM> can detect only one of them. In this case, the element for detection the other of them is reduced. For example, in the case of detecting only the on-event, the P-type transistor <NUM> and the N-type transistor <NUM>, and the switch <NUM> become unnecessary.

Furthermore, each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the third modification of the second embodiment.

As described above, according to the third modification of the second embodiment of the present technology, since the switches <NUM> and <NUM> are inserted on the output side of the comparator <NUM>, the comparison result of the comparator <NUM> can be cut off. As a result, erroneous detection of an address event can be suppressed.

In the above-described first embodiment, the switch <NUM> in the disabled pixel has been set to the open state, and the value of the detection signal has been fixed. However, in this configuration, when the switch <NUM> in the enabled pixel is set to the close state, the current or voltage value may slightly drop due to an on-resistance of the switch <NUM>. A solid-state imaging element <NUM> according to a third embodiment is different from that of the first embodiment in that a switch that is opened when set to be enabled is inserted.

<FIG> is a circuit diagram illustrating a configuration example of a logarithmic response unit <NUM>, a buffer <NUM>, a differential circuit <NUM>, and a comparator <NUM> according to the third embodiment of the present technology. The logarithmic response unit <NUM> of the third embodiment is provided with a switch <NUM> instead of the switch <NUM>.

The switch <NUM> is inserted between a connection point of a photoelectric conversion element <NUM> and a current-voltage conversion unit <NUM> and a reference terminal (ground terminal or the like). The switch <NUM> transitions to a close state in a case of being set to be disabled by enable information EN and transitions to an open state in a case of being set to be enabled by the enable information EN. The transition to the close state of the switch <NUM> stops a photocurrent from flowing into an input side of the current-voltage conversion unit <NUM>, and thus can suppress erroneous detection of an address event. Furthermore, since the switch <NUM> is not inserted into a path through which the photocurrent flows, the switch <NUM> does not affect current or voltage values when set to be enabled.

Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the third embodiment.

As described above, according to the third embodiment of the present technology, the switch <NUM> that is opened when enabled is inserted between the connection point of the photoelectric conversion element <NUM> and the current-voltage conversion unit <NUM>, and the reference terminal. Therefore, a decrease in current due to the enabled switch <NUM> can be suppressed.

In the above-described third embodiment, the switch <NUM> has been provided on the input side of the current-voltage conversion unit <NUM>, but there is a possibility that noise occurs in a rear-stage circuit of the current-voltage conversion unit <NUM> or of the subsequent elements and an address event is erroneously detected. The solid-state imaging element <NUM> according to a first modification of the third embodiment is different from that of the third embodiment in that a switch is inserted to the circuit of the current-voltage conversion unit <NUM> or a subsequent element.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, and the differential circuit <NUM> according to the first modification of the third embodiment of the present technology. The logarithmic response unit <NUM> of the first modification of the third embodiment is provided with a switch <NUM> instead of the switch <NUM>.

The switch <NUM> is inserted between a connection point of the current-voltage conversion unit <NUM> and the buffer <NUM> and the reference terminal. The switch <NUM> transitions to the close state in the case of being set to be disabled by the enable information EN and transitions to the open state in the case of being set to be enabled by the enable information EN. The transition to the close state of the switch <NUM> can suppress erroneous detection of an address event because a pixel voltage Vp input to the buffer <NUM> becomes a reference potential (ground potential or the like).

Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the first modification of the third embodiment.

As described above, according to the first modification of the third embodiment of the present technology, since the switch <NUM> is inserted between the connection point of the current-voltage conversion unit <NUM> and the buffer <NUM> and the reference terminal, erroneous detection due to noise generated in the current-voltage conversion unit <NUM> can be suppressed.

In the above-described third embodiment, the switch <NUM> has been provided on the input side of the current-voltage conversion unit <NUM>, but there is a possibility that noise occurs in a rear-stage circuit of the current-voltage conversion unit <NUM> or of the subsequent elements and an address event is erroneously detected. The solid-state imaging element <NUM> according to a second modification of the third embodiment is different from that of the third embodiment in that a switch is inserted to the circuit of the current-voltage conversion unit <NUM> or a subsequent element.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, and the differential circuit <NUM> according to the second modification of the third embodiment of the present technology. The pixel <NUM> of the second modification of the third embodiment is different from that of the third embodiment in that a switch <NUM> is provided instead of the switch <NUM>.

The switch <NUM> is inserted between a connection point of the buffer <NUM> and the differential circuit <NUM>, and the reference terminal. The switch <NUM> transitions to the close state in the case of being set to be disabled by the enable information EN and transitions to the open state in the case of being set to be enabled by the enable information EN. The transition to the close state of the switch <NUM> can suppress erroneous detection of an address event because the pixel voltage Vp output from the buffer <NUM> becomes the reference potential (ground potential or the like).

Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the second modification of the third embodiment.

As described above, according to the second modification of the third embodiment of the present technology, since the switch <NUM> is inserted between the connection point of the buffer <NUM> and the differential circuit <NUM> and the reference terminal, erroneous detection due to noise generated in the current-voltage conversion unit <NUM> or the buffer <NUM> can be suppressed.

In the above-described third embodiment, the switch <NUM> has been provided on the input side of the current-voltage conversion unit <NUM>, but there is a possibility that noise occurs in a rear-stage circuit of the current-voltage conversion unit <NUM> or of the subsequent elements and an address event is erroneously detected. The solid-state imaging element <NUM> according to a third modification of the third embodiment is different from that of the third embodiment in that a switch is inserted to the circuit of the current-voltage conversion unit <NUM> or a subsequent element.

<FIG> is a circuit diagram illustrating a configuration example of the logarithmic response unit <NUM>, the buffer <NUM>, and the differential circuit <NUM> according to the third modification of the third embodiment of the present technology. The pixel <NUM> of the third modification of the third embodiment is different from that of the third embodiment in that a switch <NUM> is provided instead of the switch <NUM>.

The switch <NUM> is inserted between an input terminal <NUM> and an output terminal <NUM> of an inverting circuit. The switch <NUM> transitions to the close state in the case of being set to be disabled by the enable information EN and transitions to the open state in the case of being set to be enabled by the enable information EN. The transition to the close state of the switch <NUM> can suppress erroneous detection of an address event because the differential circuit <NUM> is initialized.

Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the third modification of the third embodiment. Furthermore, as illustrated in <FIG>, an AND gate <NUM> can be arranged instead of the switch <NUM>. The AND gate <NUM> supplies a logical product of the enable information EN and an auto-zero signal XAZ to a gate of a P-type transistor <NUM>. The AND gate <NUM> is an example of a switch described in the claims, and the P-type transistor <NUM> is an example of a short-circuit transistor described in the claims.

As described above, according to the third modification of the third embodiment of the present technology, since the switch <NUM> is inserted between the input terminal <NUM> and the output terminal <NUM> of the inverting circuit, erroneous detection due to noise generated in the current-voltage conversion unit <NUM> or the buffer <NUM> can be suppressed.

In the above-described third embodiment, the switch <NUM> has been provided on the input side of the current-voltage conversion unit <NUM>, but there is a possibility that noise occurs in a rear-stage circuit of the current-voltage conversion unit <NUM> or of the subsequent elements and an address event is erroneously detected. The solid-state imaging element <NUM> according to a fourth modification of the third embodiment is different from that of the third embodiment in that a switch is inserted to the circuit of the current-voltage conversion unit <NUM> or a subsequent element.

<FIG> is a circuit diagram illustrating a configuration example of the buffer <NUM>, the differential circuit <NUM>, and the comparator <NUM> according to the fourth modification of the third embodiment of the present technology. The pixel <NUM> of the fourth modification of the third embodiment is different from that of the third embodiment in that switches <NUM> and <NUM> are provided instead of the switch <NUM>.

The switch <NUM> is inserted between an output terminal of the comparator <NUM> that outputs a comparison result COMP+ and the reference terminal. The switch <NUM> is inserted between the output terminal of the comparator <NUM> that outputs a comparison result COMP- and a power supply terminal. The switches <NUM> and <NUM> transition to the close state in the case of being set to be disabled by the enable information EN and transition to the open state in the case of being set to be enabled by the enable information EN. The transitions to the close state of the switches <NUM> and <NUM> can suppress erroneous detection of an address event because the comparison results COMP+ and COMP- are fixed to low level and high level.

Note that the pixel <NUM> detects both the on-event and off-event, but the pixel <NUM> can detect only one of them. In this case, the element for detection the other of them is reduced. For example, in the case of detecting only the on-event, an N-type transistor <NUM> and a P-type transistor <NUM>, and the switch <NUM> become unnecessary.

Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the fourth modification of the third embodiment.

As described above, according to the fourth modification of the third embodiment of the present technology, since the switches <NUM> and <NUM> are inserted between the output terminal of the comparator <NUM> and the ground terminal, erroneous detection due to noise generated in the front stage of the comparator <NUM> can be suppressed.

In the above-described first embodiment, the erroneous detection of the address event due to the static factors such as a defective element has been suppressed by the abnormal pixel determination unit <NUM> determining the presence or absence of an abnormality in advance before the address event detection processing. However, the erroneous detection of an address event may occur due to the dynamic factors such as irradiation with a flicker light source irradiation. A solid-state imaging element <NUM> according to a fourth embodiment is different from that of the first embodiment in determining presence or absence of an abnormality during detection of an address event and suppressing erroneous detection of the address event due to a dynamic factor.

<FIG> is a block diagram illustrating a configuration example of the solid-state imaging element <NUM> according to the fourth embodiment of the present technology. The solid-state imaging element <NUM> of the fourth embodiment is different from that of the first embodiment in that an abnormal pixel determination unit <NUM> and a setting information holding unit <NUM> are not provided outside a pixel array unit <NUM>. In the fourth embodiment, circuits in the abnormal pixel determination unit <NUM> and the setting information holding unit <NUM> are distributed and arranged in pixels <NUM>.

Furthermore, a mode signal MODE is not input to a signal processing unit <NUM> of the fourth embodiment. In the fourth embodiment, the presence or absence of an abnormality is determined during address event detection processing. The signal processing unit <NUM> performs signal processing for a detection signal and supplies processed data to the recording unit <NUM>.

<FIG> is a block diagram illustrating a configuration example of the pixel <NUM> according to the fourth embodiment of the present technology. The pixel <NUM> of the fourth embodiment is different from that of the first embodiment in including an abnormal pixel determination circuit <NUM> and an enable holding circuit <NUM> in addition to a pixel circuit <NUM>. Furthermore, a transfer unit <NUM> of the fourth embodiment also supplies a detection signal DET to the abnormal pixel determination circuit <NUM>.

The abnormal pixel determination circuit <NUM> determines whether or not the pixel <NUM> is abnormal. During the address event detection processing, the abnormal pixel determination circuit <NUM> counts a detection count as in the first embodiment, and determines whether or not the presence or absence of an abnormality according to whether or not a count value exceeds a threshold. The abnormal pixel determination circuit <NUM> causes the enable holding circuit <NUM> to hold one-bit enable information.

The enable holding circuit <NUM> holds the enable information. The enable holding circuit <NUM> includes, for example, a rewritable memory. A latch circuit, an SRAM, or the like is used as the rewritable memory. Furthermore, the enable holding circuit <NUM> supplies the enable information to the pixel circuit <NUM>. Note that the enable holding circuit <NUM> is an example of a control circuit described in the claims.

The abnormal pixel determination circuit <NUM> determines the presence or absence of an abnormality during the address event detection processing, so that erroneous detection of the address event due to the dynamic factors such as aging deterioration and a flicker light source can be suppressed. Note that the abnormal pixel determination circuit <NUM> can further determine the presence or absence of an abnormality before the detection processing as in the first embodiment, in addition to the determination for the presence or absence of an abnormality during the detection processing.

Note that the abnormal pixel determination circuit <NUM> and the enable holding circuit <NUM> are arranged for each pixel, but these circuits can be collectively arranged outside the pixel array unit <NUM>, as in the first embodiment.

Furthermore, each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the fourth embodiment. Furthermore, each of the second and third embodiments and the modifications thereof can be applied to the solid-state imaging element <NUM> of the fourth embodiment.

As described above, according to the fourth embodiment of the present technology, the abnormal pixel determination circuit <NUM> determines the presence or absence of an abnormality during detection of an address event. Therefore, erroneous detection of the address event due to the dynamic factors can be suppressed.

In the above-described first embodiment, the circuit in the solid-state imaging element <NUM> has determined the presence or absence of an abnormality, but the function to determine the presence or absence of an abnormality can be implemented by a computer executing a program. A solid-state imaging element <NUM> according to a fifth embodiment is different from that of the first embodiment in using a program that executes a procedure for determining the presence or absence of an abnormality.

<FIG> is a block diagram illustrating a configuration example of an imaging device <NUM> according to the fifth embodiment of the present technology. The imaging device <NUM> is different from that of the first embodiment in further including an abnormal pixel determination unit <NUM>.

The abnormal pixel determination unit <NUM> determines the presence or absence of an abnormality for each pixel. The method for determining the abnormal pixel is similar to that of the fourth embodiment for dynamically determining the presence or absence of an abnormality. Note that the abnormal pixel determination unit <NUM> can also statically determine the presence or absence of an abnormality as in the first embodiment.

Furthermore, the abnormal pixel determination unit <NUM> is implemented by a processing device such as a CPU executing a predetermined program. Therefore, it is not necessary to provide a circuit for determining the presence or absence of an abnormality in the solid-state imaging element <NUM>, and the circuit scale can be reduced accordingly.

<FIG> is a block diagram illustrating a configuration example of the solid-state imaging element <NUM> according to the fifth embodiment of the present technology. The solid-state imaging element <NUM> of the fifth embodiment is different from that of the first embodiment in that the abnormal pixel determination unit <NUM> is not provided.

A signal processing unit <NUM> of the fifth embodiment supplies a detection signal to the abnormal pixel determination unit <NUM> in an abnormality determination mode. Furthermore, setting information from the abnormal pixel determination unit <NUM> is input to a setting information holding unit <NUM>.

Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element <NUM> of the fifth embodiment. Furthermore, each of the second and third embodiments and the modifications thereof can be applied to the solid-state imaging element <NUM> of the fifth embodiment.

As described above, according to the fifth embodiment of the present technology, since the program for executing the procedure for determining the presence or absence of an abnormality is used, the circuit for determining the presence or absence of an abnormality is not necessary, and the circuit scale of the solid-state imaging element <NUM> can be reduced.

The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving bodies including an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, and the like.

<FIG> is a block diagram illustrating a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure is applicable.

A vehicle control system <NUM> includes a plurality of electronic control units connected through a communication network <NUM>. In the example illustrated in <FIG>, the vehicle control system <NUM> includes a drive system control unit <NUM>, a body system control unit <NUM>, a vehicle exterior information detection unit <NUM>, a vehicle interior information detection unit <NUM>, and an integrated control unit <NUM>. Furthermore, as functional configurations of the integrated control unit <NUM>, a microcomputer <NUM>, a sound image output unit <NUM>, and an in-vehicle network interface (I/F) <NUM> are illustrated.

The drive system control unit <NUM> controls operations of devices regarding a drive system of a vehicle according to various programs. For example, the drive system control unit <NUM> functions as a control device of a drive force generation device for generating drive force of a vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to wheels, a steering mechanism that adjusts a steering angle of a vehicle, a braking device that generates braking force of a vehicle, and the like.

The body system control unit <NUM> controls operations of various devices equipped in a vehicle body according to various programs. For example, the body system control unit <NUM> functions as a control device of a keyless entry system, a smart key system, an automatic window device, and various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a mobile device substituted for a key or signals of various switches can be input to the body system control unit <NUM>. The body system control unit <NUM> receives an input of the radio waves or the signals, and controls a door lock device, the automatic window device, the lamps, and the like of the vehicle.

The vehicle exterior information detection unit <NUM> detects information outside the vehicle that mounts the vehicle control system <NUM>. For example, an imaging unit <NUM> is connected to the vehicle exterior information detection unit <NUM>. The vehicle exterior information detection unit <NUM> causes the imaging unit <NUM> to capture an image outside the vehicle, and receives the captured image. The vehicle exterior information detection unit <NUM> may perform object detection processing or distance detection processing of persons, vehicles, obstacles, signs, letters on a road surface, or the like on the basis of the received image.

The imaging unit <NUM> is an optical sensor that receives light and outputs an electrical signal according to a light-receiving amount of the light. The imaging unit <NUM> can output the electrical signal as an image and can output the electrical signal as information of distance measurement. Furthermore, the light received by the imaging unit <NUM> may be visible light or may be non-visible light such as infrared light.

The vehicle interior information detection unit <NUM> detects information inside the vehicle. A driver state detection unit <NUM> that detects a state of a driver is connected to the vehicle interior information detection unit <NUM>, for example. The driver state detection unit <NUM> includes a camera that captures the driver, for example, and the vehicle interior information detection unit <NUM> may calculate the degree of fatigue or the degree of concentration of the driver, or may determine whether or not the driver falls asleep on the basis of the detection information input from the driver state detection unit <NUM>.

The microcomputer <NUM> calculates a control target value of the drive force generation device, the steering mechanism, or the braking device on the basis of the information outside and inside the vehicle acquired in the vehicle exterior information detection unit <NUM> or the vehicle interior information detection unit <NUM>, and can output a control command to the drive system control unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control for the purpose of realization of an advanced driver assistance system (ADAS) function including collision avoidance or shock mitigation of the vehicle, following travel based on an inter-vehicle distance, vehicle speed maintaining travel, collision warning of the vehicle, lane out warning of the vehicle, and the like.

Furthermore, the microcomputer <NUM> controls the drive force generation device, the steering mechanism, the braking device, or the like on the basis of the information of a vicinity of the vehicle acquired in the vehicle exterior information detection unit <NUM> or the vehicle interior information detection unit <NUM> to perform cooperative control for the purpose of automatic drive of autonomous travel without depending on an operation of the driver or the like.

Furthermore, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information outside the vehicle acquired in the vehicle exterior information detection unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control for the purpose of achievement of non-glare such as by controlling the head lamps according to the position of a leading vehicle or an oncoming vehicle detected in the vehicle exterior information detection unit <NUM>, and switching high beam light to low beam light.

The sound image output unit <NUM> transmits an output signal of at least one of a sound or an image to an output device that can visually and aurally notify a passenger of the vehicle or an outside of the vehicle of information. In the example in <FIG>, as the output device, an audio speaker <NUM>, a display unit <NUM>, and an instrument panel <NUM> are exemplarily illustrated. The display unit <NUM> may include, for example, at least one of an on-board display or a head-up display.

<FIG> is a diagram illustrating an example of an installation position of the imaging unit <NUM>.

In <FIG>, imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are included as the imaging unit <NUM>.

The imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are provided at positions of a front nose, side mirrors, a rear bumper, a back door, an upper portion of a windshield, and the like in an interior of a vehicle <NUM>, for example. The imaging unit <NUM> provided at the front nose and the imaging unit <NUM> provided at an upper portion of the windshield in an interior of the vehicle mainly acquire images in front of the vehicle <NUM>. The imaging units <NUM> and <NUM> provided at the side mirrors mainly acquire images on sides of the vehicle <NUM>. The imaging unit <NUM> provided at the rear bumper or the back door mainly acquires images in back of the vehicle <NUM>. The imaging unit <NUM> provided at the upper portion of the windshield in the interior of the vehicle is mainly used for detecting a leading vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that <FIG> illustrates an example of capture ranges of the imaging units <NUM> to <NUM>. An imaging range <NUM> indicates the imaging range of the imaging unit <NUM> provided at the front nose, imaging ranges <NUM> and <NUM> respectively indicate the imaging ranges of the imaging units <NUM> and <NUM> provided at the side mirrors, and an imaging range <NUM> indicates the imaging range of the imaging unit <NUM> provided at the rear bumper or the back door. For example, a bird's-eye view image of the vehicle <NUM> as viewed from above can be obtained by superimposing image data captured by the imaging units <NUM> to <NUM>.

At least one of the imaging units <NUM> to <NUM> may have a function to acquire distance information. For example, at least one of the imaging units <NUM> to <NUM> may be a stereo camera including a plurality of imaging elements or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer <NUM> obtains distances to three-dimensional objects in the imaging ranges <NUM> to <NUM> and temporal change of the distances (relative speeds to the vehicle <NUM>) on the basis of the distance information obtained from the imaging units <NUM> to <NUM>, thereby to extract particularly a three-dimensional object closest to the vehicle <NUM> on a traveling road and traveling at a predetermined speed (for example, <NUM>/h or more) in substantially the same direction as the vehicle <NUM> as a leading vehicle. Moreover, the microcomputer <NUM> can set an inter-vehicle distance to be secured from the leading vehicle in advance and perform automatic braking control (including following stop control) and automatic acceleration control (including following start control), and the like. In this way, the cooperative control for the purpose of automatic drive of autonomous travel without depending on an operation of the driver, and the like can be performed.

For example, the microcomputer <NUM> classifies three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, and other three-dimensional objects such as electric poles to be extracted, on the basis of the distance information obtained from the imaging units <NUM> to <NUM>, and can use the data for automatic avoidance of obstacles. For example, the microcomputer <NUM> discriminates obstacles around the vehicle <NUM> into obstacles visually recognizable by the driver of the vehicle <NUM> and obstacles visually unrecognizable by the driver. The microcomputer <NUM> then determines a collision risk indicating a risk of collision with each of the obstacles, and can perform drive assist for collision avoidance by outputting warning to the driver through the audio speaker <NUM> or the display unit <NUM>, and performing forced deceleration or avoidance steering through the drive system control unit <NUM>, in a case where the collision risk is a set value or more and there is a collision possibility.

At least one of the imaging units <NUM> to <NUM> may be an infrared camera that detects infrared light. For example, the microcomputer <NUM> determines whether or not a pedestrian exists in the captured images of the imaging units <NUM> to <NUM>, thereby to recognize the pedestrian. Such recognition of a pedestrian is performed by a process of extracting characteristic points in the captured images of the imaging units <NUM> to <NUM>, as the infrared camera, for example, and by a process of performing pattern matching processing for the series of characteristic points indicating a contour of an object and determining whether or not the object is a pedestrian. When the microcomputer <NUM> determines that a pedestrian exists in the captured images of the imaging units <NUM> to <NUM> and recognizes the pedestrian, the sound image output unit <NUM> causes the display unit <NUM> to superimpose and display a square contour line for emphasis on the recognized pedestrian. Furthermore, the sound image output unit <NUM> may cause the display unit <NUM> to display an icon or the like representing the pedestrian at a desired position.

An example of a vehicle control system to which the technology according to the present disclosure is applicable has been described. The technology according to the present disclosure is applicable to the imaging unit <NUM>, of the above-described configurations. Specifically, the imaging device <NUM> in <FIG> can be applied to the imaging unit <NUM>. By applying the technology according to the present disclosure to the imaging unit <NUM>, the erroneous detection of an address event can be suppressed, whereby the reliability of the system can be improved.

Claim 1:
A solid-state imaging element (<NUM>) comprising:
a plurality of pixel circuits (<NUM>) each configured to execute detection processing of detecting the presence or absence of an address event, the address event indicating that a change amount of an incident light amount exceeds a predetermined threshold, and outputting a detection result, each of the plurality of pixel circuits (<NUM>) including
a logarithmic response unit (<NUM>) in which a photoelectric conversion element (<NUM>) configured to generate a photocurrent by photoelectric conversion and a current-voltage conversion unit (<NUM>) configured to convert the photocurrent into a voltage are arranged,
a buffer (<NUM>) configured to output the voltage,
a differential circuit (<NUM>) configured to generate a differential signal indicating a change amount of the output voltage by differential operation,
a comparator (<NUM>) configured to compare the differential signal with the threshold, and
a transfer unit (<NUM>) configured to transfer a comparison result of the comparator as the detection result, wherein
any of the logarithmic response unit (<NUM>), the buffer (<NUM>), the differential circuit (<NUM>), and the comparator (<NUM>) includes a switch (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>);
an abnormal pixel determination unit (<NUM>, <NUM>) configured to determine whether or not each of the plurality of pixel circuits (<NUM>) has an abnormality, and set a pixel circuit without (<NUM>) the abnormality to be enabled and set a pixel circuit (<NUM>) with the abnormality to be disabled; and
a control unit (<NUM>) configured to perform control of causing the pixel circuit (<NUM>) set to be enabled to execute the detection processing, and, by controlling the switch (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) to open or close a predetermined path, to perform control of fixing the detection result of the pixel circuit (<NUM>) set to be disabled to a specific value, the specific value indicating that the address event does not occur.