Patent Description:
Prior art printed circuit boards (PCB) are formed using a subtractive process by etching a sheet of copper laminated to a substrate using patterned resist to form conductive metal interconnects (known as "traces") on the dielectric substrate, where each surface carrying conductors is known as a "layer". Each dielectric core has traces formed on one surface or on both surfaces, and by stacking several such dielectric cores having traces formed on one or more surfaces, and interspersed with bare dielectric layers, a multi-layer printed circuit may be formed by laminating them together under temperature and pressure. The dielectric substrate comprises an epoxy resin embedded in a fiber matrix such as glass fiber woven into a cloth. In one prior art fabrication method, copper is laminated onto the outer surfaces of a dielectric layer, the copper surfaces are patterned such as with a photoresist or photo sensitive film to create masked and unmasked regions, and then etched to form a conductive trace layer on one or both sides of the core dielectric. A stack of dielectric cores with conductive traces may then be laminated together to form a multi-layer circuit board, and any layer to layer trace interconnects made with vias, which are drilled holes plated with copper to form annular rings which provide connectivity from one layer to another.

Printed circuit boards (PCB) are typically used to provide conductive traces between various electronic components mounted on the PCB. The dimension of a trace which is parallel to the surface of the laminate is considered a trace width, and the dimension of a trace which is perpendicular to the surface of the laminate is considered a trace thickness. One type of electronic component is a through-hole device which is mounted on the PCB by having leads positioned through one or more holes in the PCB, where the PCB hole includes a conductive annular ring pad on each trace connect layer, and the component lead is soldered to the annular ring pad of the PCB hole. Through hole components have leads which tend to be difficult to align with the associated PCB mounting hole, but surface mount technology (SMT) provides a preferable mounting system, where component leads are simply placed on the surface of a PCB pad or land and soldered, which is preferred for PCB assembly because of the smaller size and higher density of SMT components and ease of mechanized assembly compared to through-hole components. Surface mount components require only surface mount pads which provide a surface soldering terminal on an outside finished PCB layer. Within a two layer or multi-layer PCB, interconnects of conductive traces from one layer to another are accomplished using through-hole vias, where a conductive trace on one trace layer leads to a hole which is typically drilled through one or more dielectric layers of the PCB and plated with copper or other conductive metal to complete the trace layer connection. A hole drilled through all dielectric layers is known as a thru-via, a hole drilled through an outer layer only (typically as part of the fabrication of the individual layer) is known as a micro-via, and a hole drilled through one or more inner layers is known as a blind via. For any of these via types, the via is patterned to include an annular ring conductor region on opposite trace layers of the PCB, with the drilled hole lined with conductive material which connects the annular ring conductors on either side of the laminate or PCB.

The thickness of pre-patterned or postpatterned copper on a printed circuit board laminate may be increased using electroplating, where the PCB or dielectric layer with traces is placed in an electrolytic bath, and a DC source is connected between a sacrificial anodic conductor electrode (such as a copper rod) to an electrode clamped or attached to an existing conductive layer of a PCB which forms the two electrodes across which a DC current may be applied. Where a pre-existing conductive copper layer is not present on a PCB to facilitate electroplating, such as the case of bare dielectric material or drilled via holes, a seed layer of copper must first be deposited. This is done using an electroless process with the assistance of a "seed" catalytic material (which enhances the deposition of a particular conductive material) which is deposited on the surface of the dielectric, and the board is then placed in an electroless bath. For a catalyst such as palladium and an electroless bath of copper, the copper ions in solution deposit over the palladium until the surface is covered sufficiently to provide uniform electrical conductivity, after which the copper deposited using the electroless process provides a conductive scaffold for the subsequent addition of material using the electroplating process. Electroplating is preferred for finishing the plating operation, as it has a faster deposition rate than the electroless plating process.

As electronic assemblies increase in complexity, it is desired to increase component densities on PCB assemblies, such as by using smaller trace widths (known as fine pitch traces) in conjunction with increasingly dense integrated circuit (IC) lead patterns. One problem of prior art surface mount PCB fabrication and assembly methods is that because the traces are formed on the surface of the dielectric, the adhesion between copper trace and underlying laminate for narrower conductor line widths (known as fine pitch traces) is reduced, causing the fine pitch traces and component pads to separate (lift) during a component replacement operation, ruining the entire circuit board assembly and expensive components on it. Another problem of fine pitch surface traces is that when fabricating a multi-layer circuit board, the individual trace layers are laminated together under pressure in an elevated temperature environment. During lamination, fine pitch traces tend to migrate laterally across the surface of the dielectric. In high speed circuit board layout and design, it is desired to maintain a fixed impedance between traces, particularly for differential pair (edge coupled) transmission lines. This lateral migration of traces during lamination causes the transmission line impedance of the finished PCB differential pair to vary over the length of the trace, which causes reflections and losses in the transmission line compared to one with fixed impedance characteristics resulting from constant spacing.

Where traces are formed using subtractive processes such as etching a copper foil surface layer to form traces, lower resistance traces can be formed using electroplating to build up the thickness of the traces on the outer surface to reduce the trace resistance, or by widening the traces on the top surface to reduce the current density in the trace. However, it becomes difficult to electroplate more than 3oz of copper because of bleeding of the copper to surrounding areas, and width increase of the traces, limiting the thickness of the copper which can be electroplated. Typically, the trace is made wider during the design of the circuit board, which consumes available real estate on the board, or the trace is replicated onto lower trace layers to form parallel traces on separate inner trace layers separated by dielectric, where the inner layers are typically formed from thinner base copper such as <NUM>/<NUM> oz copper (~<NUM> mil thick). Alternatively, traces may be formed in channels using the applicant's additive process as described in <CIT>,<CIT>, <CIT>, and <CIT>. It is similarly possible to extend the width of these additive process traces formed in a channel to reduce trace resistance, subject to the same limitation of increasing the width of the trace to support greater current density. It is desired to provide traces with lower resistance than is provided by the prior art processes, and without increasing the width of the trace.

The disclosure <CIT> refers to a printed circuit board, comprising: a laminate substrate, the laminate substrate including catalytic core material overlaid with non-catalytic material so that the laminate substrate resists metal plating except where catalytic core material is exposed; metal traces within in trace channels formed within the laminate substrate, the channels extending below the surface of the catalytic core material; catalytic material over the laminate substrate; vias through the catalytic material; and additional traces on the surface of the catalytic material, including traces within the vias.

An object of the invention is to provide a multi-layer circuit board as defined in claims <NUM>-<NUM>.

The invention is set out in appended claims. In particular, a first catalytic layer formed from either a catalytic laminate or a catalytic adhesive has catalytic particles an exclusion depth below at least one surface of the catalytic layer, the catalytic layer having channels formed into at least one surface of the catalytic layer which have a depth of at least the exclusion depth, the channels thereby exposing catalytic particles. The channels of the first catalytic layer are exposed to electroless plating of a conductive metal such as copper for a duration of time sufficient for a deposition of metal with a thickness from the bottom of the channel to a depth near the surface of the first catalytic layer. The first catalytic layer is bonded or laminated to a second catalytic layer and at least one channel is formed into the second catalytic layer which extends through the thickness of the second catalytic layer and to the deposition of metal on the first catalytic layer, after which the second catalytic layer channel is electroless plated over a depth from the metal deposition of the first catalytic layer to the surface of the second catalytic layer, thereby forming a trace which has greater depth than a single catalytic layer. Additional catalytic layers may be bonded or laminated to previous catalytic layers, the additional catalytic layers each having full depth channels formed to the underlying metal deposition of an adjacent catalytic layer, with the electroless deposition plated to form traces having a trace depth which spans each additional catalytic layer to form traces with a depth which spans the several catalytic layers, each catalytic layer providing a full depth channel.

Catalytic layers are formed as either catalytic laminates or catalytic adhesives. Catalytic laminates are formed by curing a mixture of a resin, catalytic particles, and a fiber mesh, the catalytic particles an exclusion depth below the surface of the catalytic laminate. Catalytic adhesives are formed as a mixture of resin and catalytic particles which are cured onto an underlying surface, the surface of the cured catalytic adhesive having catalytic particles an exclusion depth below the surface of the cured catalytic adhesive. In this embodiment, traces are formed having a depth of a plurality of catalytic layers, where a first catalytic layer has a channel formed, and the channel deposited with a metal using electroless plating to substantially fill the channel to a surface layer. The first catalytic layer is then bonded or laminated to one or more subsequent catalytic layers, each subsequent catalytic layer having a channel formed through the catalytic layer to the level of the first catalytic layer electroless plated metal, after which electroless copper is deposited in the channel to the surface of each subsequent layer, thereby providing traces continuous in depth over multiple catalytic layers, the resulting trace having a thickness greater than the thickness of a single catalytic layer, and spanning the depth of the multiple catalytic layers which form the trace. The lamination of a subsequent catalytic laminate to an underlying catalytic laminate layer with a formed channel may be performed with an electroless deposition after each lamination and channel forming step, or the channel may be formed through multiple catalytic laminate layers and electroless plated in a single step. In one example of the invention, the step of performing a sequential lamination of a catalytic laminate, forming a channel in the catalytic laminate after each lamination, and electroless plating each channel, are done in a repeating sequence until the desired trace depth is formed.

A process for forming traces in a catalytic layer formed from either catalytic laminate or a catalytic adhesive has at least one trace sequentially formed in a channel, the resultant trace having a thickness greater than the depth of a single catalytic layer, where the process comprises:.

<FIG> shows an example catalytic pre-preg for use in one aspect of the current invention. The catalytic pre-preg consists of a matrix of pre-impregnated fibers bound in a resin containing catalytic particles. Many different materials may be used for the fibers of prepreg, including woven glass-fiber cloth, carbon-fiber, or other fibers, and a variety of different materials may be used for the resin, including epoxy resin, polyimide resin, cyanate ester resin, PTFE (Teflon) blend resin, or other resins. One aspect of the invention is a printed circuit board laminate capable of supporting fine pitch conductive traces on the order of <NUM> mil (25u), and while the description is drawn to the formation of copper traces using catalysts for electroless copper formation, it is understood that the scope of the invention may be extended to other metals suitable for electroless plating and electro-plating. For electroless deposition of copper (Cu) channels, elemental palladium (Pd) is preferred as the catalyst, although selected periodic table transition metal elements, such as group <NUM> to <NUM> platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or other compounds of these, including other metals such as iron (Fe), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tin (Sn), or mixtures or salts of the above, any of which may be used as catalytic particles. The present candidate list is intended to be exemplar rather than comprehensive, it is known in the art that other catalysts for attracting copper ions may also be used. In one example of the invention, the catalytic particles are homogeneous catalytic particles. In another example of the invention, the catalytic particles are inorganic particles or high temperature resistant plastic particles which are coated with a few angstrom thickness of catalytic metal, thereby forming heterogeneous catalytic particles having a thin catalytic outer surface encapsulating a non-catalytic inner particle. This formulation may be desirable for larger catalytic particles, such as those on the order of 25u in longest dimension. The heterogeneous catalytic particle of this formulation can comprise an inorganic, organic, or inert filler such as silicon dioxide (SiO2), an inorganic clay such as Kaolin, or a high temperature plastic filler coated on the surface with a catalyst such as palladium adsorbed onto the surface of the filler, such as by vapor deposition or chemical deposition. Only a few atomic layers of catalyst are required for the catalytic particle to have desirable properties conducive to electroless plating.

In another example of a catalytic layer formed using a catalytic adhesive, the catalytic adhesive formulation is the same as for the catalytic laminate except that no fiber is introduced into the resin and catalytic particle mixture and the resin and catalytic particle mixture is applied to an underlying surface and cured such that catalytic particles are an exclusion depth below the surface of the cured catalytic adhesive, as was the case with the catalytic particle distribution of the catalytic laminate layer, thereby enabling electroless plating only in channels which are formed which extend below the exclusion depth for catalytic particles.

In one example of forming heterogeneous catalytic particles, a bath of fillers (organic or inorganic) is sorted by size to include particles less than 25u in size, these sorted inorganic particles are mixed into an aqueous bath in a tank, agitated, and then a palladium salt such as PdCl (or any other catalyst such as a salt of silver of other catalyst) is introduced with an acid such as HCl, and with a reducing agent such as hydrazine hydrate, the mixture thereby reducing metallic Pd which coats the inorganic particles provide a few angstroms of thickness of Pd coated on the filler, thereby creating a heterogeneous catalytic particle which has the catalytic property of a homogeneous Pd particle with a greatly reduced volume requirement of Pd compared to using homogeneous Pd metallic particles. For extremely small catalytic particles on the order of a few nm, however, homogeneous catalytic particles (such as pure Pd) may be preferred.

Example inorganic fillers include clay minerals such as hydrous aluminum phyllosilicates, which may contain variable amounts of iron, magnesium, alkali metals, alkaline earths, and other cations. This family of example inorganic fillers includes silicon dioxide, aluminum silicate, kaolinite (Al<NUM>Si<NUM>O<NUM>(OH)<NUM>), polysilicate, or other clay minerals which belong to the kaolin or china clay family. Example organic fillers include PTFE (Teflon) and other polymers with high temperature resistance.

Examples of palladium salts are: BrPd, CL<NUM>Pd, Pd(CN)<NUM>, I<NUM>Pd, Pd(NO<NUM>)<NUM>*<NUM><NUM><NUM>, Pd(NO<NUM>)<NUM>, PdSO<NUM>, Pd(NH<NUM>)4Br<NUM>, Pd(NH<NUM>)4Cl<NUM>H<NUM>O. The catalytic powder of the present invention may also contain a mixture of heterogeneous catalytic particles (for example, catalytic materials coated over inorganic filler particles), homogeneous catalytic particles (such as elemental palladium), as well as non-catalytic particles (selected from the family of inorganic fillers).

Among the catalysts, palladium is a preferred catalyst because of comparative economy, availability, and mechanical properties, but other catalysts may be used.

In one method of forming catalytic laminates, a woven glass fiber is fed through as set of rollers infuse the fabric with epoxy resin blended with catalytic particles and mixed with a volatile liquid to reduce the viscosity, thereby forming an A-stage (liquid) pre-preg.

The resin may be a polyimide resin, a blend of epoxy and cyanide ester (which provides curing at elevated temperatures), or any other suitable resin formulation with selectable viscosity during coating and thermosetting properties after cooling. Fire retardants may be added, for example to comply with a flammability standard, or to be compatible with one of the standard FR series of prepreg such as FR-<NUM> or FR-<NUM>. An additional requirement for high speed electrical circuits is dielectric constant ε (permittivity), which is often approximately <NUM> and governs the characteristic impedance of a transmission line formed on the dielectric, and loss tangent δ, which is measure of frequency-dependent energy absorption over a distance, whereby the loss tangent is a measure of how the dielectric interacts with high frequency electric fields to undesirably reduce signal amplitude by a calculable amount of dB per cm of transmission line length. The resin is blended with catalytic particles which have been sorted for size. In one example formulation, the catalytic particles include at least one of: homogeneous catalytic particles (metallic palladium), or heterogeneous catalytic particles (palladium coated over an inorganic particle or high temperature plastic), and for either formulation, the catalytic particles preferably having a maximum extent of less than 25u and with <NUM>% of the particles by count sized between 12u and 25u, or the range <NUM>-25u, or smaller. These are example catalytic particle size embodiments not intended to limit the scope of the invention. In one example embodiment, the catalytic particles (either homogeneous or heterogeneous) are in the size range 1u-25u. In another example of the invention, homogeneous catalytic particles are formed by grinding metallic palladium into particles and passing the resultant particles through a sieve with a mesh having 25u rectangular openings. In another example, the catalytic resin mixture is formed by blending homogeneous or heterogeneous catalytic particles into the pre-preg resin by a ratio of weights, such as the ratio of substantially <NUM>% catalytic particles by weight to the weight of resin. The ratio by weight of catalytic particles in the resin mixture may alternatively be in the range of <NUM>-<NUM>% of catalytic particle weight to the total weight of resin. It is understood that other blending ratios may also be used, and it may be preferable to use smaller particles. In one example of the invention, the catalytic particle density is chosen to provide a mean distance between catalytic particles on the order of 3u-5u.

In one example of the invention, to create the resin rich surface which excludes catalytic particles, the pre-preg sheets positioned near the outer surfaces (which will later have the surface removed to expose the underlying catalytic particles) are selected to have greater than <NUM>% resin, such as Glass <NUM> (<NUM>% resin), Glass <NUM>, or Glass <NUM> (<NUM>% resin), and the inner prepreg sheets (which are not subject to surface removal) are selected to have less than <NUM>% resin. Additionally, to reduce the likelihood of fiberglass being present near the surface of the catalytic pre-preg, a woven fiberglass may be used with the inner pre-preg layers and a flat unwoven fiberglass may be used in the outer resin rich pre-preg layers. The combination of resin-rich pre-preg and flat unwoven fiberglass on the outer surface layer results in an exclusion zone of. <NUM> mil (17u) to. <NUM> mil (23u) between an outer surface and the encapsulated fiberglass. Glass styles <NUM>, <NUM>, and <NUM> are preferred for use on the outer resin rich surface since the glass fiber thicknesses are smaller (<NUM>-<NUM> mil / <NUM>-35u) than the glass fiber thickness found in typical pre-preg sheets with greater than <NUM>% resin used in the central regions of the laminate, such as glass style <NUM>, which has <NUM> mil (94u) fibers. These values are given as examples, the smallest glass fibers which are commercially available are expected to continue to reduce in diameter. During processing of the catalytic laminate for use with the present invention, a temperature vs. time sequence is applied to cause the catalytic particles and fiberglass to migrate away from the outer surface of the laminate, repelled by the surface tension of the epoxy during a liquid state of the gel point temperature. After the cooling cycle, the cured C-stage pre-preg sheets are offloaded. The process which forms the cured C-stage pre-preg sheets may use single or multiple sheets of fiber fabric to vary the finished thickness, which may vary from <NUM> mil (51u) to <NUM> mil (<NUM>). A complete description of the process for forming catalytic laminates, catalytic adhesives, and resins may be found in <CIT> by the present inventors and commonly assigned, which is incorporated by reference.

<FIG> shows the resultant catalytic pre-preg <NUM> formed by the pre-preg process, where the catalytic particles <NUM> are distributed uniformly within the central region of pre-preg <NUM>, but are not present below a boundary region <NUM> below first surface <NUM>, or below boundary region <NUM> below second surface <NUM>. This boundary region <NUM> is a fundamental characteristic of the catalytic particle exclusion zone common to both catalytic laminate and catalytic adhesive catalytic layers. For the example particle distribution of particles smaller than 25u, the catalytic particle boundary is typically <NUM>-12u below the surface (on the order of half of the length of a catalytic particle), accordingly this depth or greater of surface material must be removed for the embedded catalytic particles to be available for electroless plating. The region from surface <NUM> to catalytic particles at region <NUM> and from surface <NUM> to catalytic particles at region <NUM> are referred to as catalytic particle exclusion zones in the present application. In one example of the invention, the catalytic particle exclusion zone contains an insufficient density of catalytic particles to enable electroless plating without forming a channel below the catalytic particle exclusion depth. In another example of the invention, the density of catalytic particles in the exclusion zone is less than <NUM>/<NUM> of the catalytic particle density in non-exclusion zone regions of the catalytic laminate. In another example of the invention, the exclusion zone regions are unable to form continuous conductors through electroless plating in a given duration of time, whereas the regions below the exclusion zone are able to form continuous conductors in the same interval of time.

Prior art catalytic laminates have activated surfaces that must be masked to prevent unwanted electroless plating on the activated surface of the catalytic laminate. By contrast, the catalytic laminate and catalytic adhesives of the present invention exclude catalytic particles over the thickness extent from first surface <NUM> to first boundary <NUM>, and from second surface <NUM> to second boundary <NUM>, providing the benefit that a separate mask layer preventing contact with the catalytic particles is not required for electroless plating as it is in the prior art. Accordingly, removal of surface material from either first surface <NUM> to the depth of boundary layer <NUM> or deeper, or removal of surface material from second surface <NUM> to second boundary <NUM>, results in the exposure of catalytic material which may be used for electroless plating. It is also desirable for the process which provides the resin rich surface to also exclude not only catalyst, but the fiber fabric, as removal of the surface layer in subsequent steps which results in the exposure of fibers requires additional cleaning steps, accordingly it is preferred that the surface removal be of resin only, so as to expose only the underlying catalytic particles. This is accomplished by using a combination of resin-rich outer pre-preg layers and flat unwoven fiberglass layers having smaller diameter fibers on the outside layers. An additional advantage of forming traces in channels using electroless plating is that the traces are mechanically supported on three sides, which provides greatly improved trace adhesion to the dielectric laminate.

<FIG> shows a prior art buck regulator circuit. When the switch <NUM> is closed, inductor charging current flows from the power source <NUM> through energy storage inductor <NUM> and to smoothing capacitor <NUM>, increasing the voltage in smoothing capacitor <NUM>. When switch <NUM> is open, inductor discharge current continues to flow through inductor <NUM>, through the path of diode <NUM> and capacitor <NUM>. Steady state currents I3 and I4 drawn by load <NUM> and <NUM>, respectively, are significantly lower than the peak pulsatile current I1 <NUM> through switch <NUM> or peak pulsatile current I2 <NUM> through inductor <NUM>.

<FIG> shows the current waveform plots <NUM> for I1 showing the switch opening and closing, Inductor current I2 <NUM>, and steady state currents I3 <NUM> and I4 <NUM>.

<FIG> illustrates an example of the effect on a prior art printed circuit board which is designed for pulsatile vs steady state current flows. Inductor 208A corresponds to <NUM> of <FIG> and capacitor 218A of <FIG> corresponds to <NUM> of <FIG>. The trace 237A (corresponding to thick line <NUM> of schematic of <FIG>) carries peak pulsatile currents and so must be comparatively wide to reduce I<NUM>R losses associated with I2, whereas the width of the traces 214A and 216A carrying steady state currents I3 and I4 (associated with corresponding lines <NUM> and <NUM> of <FIG>) may be significantly narrower. Further, it is typically the case that small signal traces are excluded from power supply areas during printed circuit design, to prevent coupling of unwanted transient signals from the pulsatile current flows into the small signal traces by magnetic induction or electrostatic displacement currents through cross-coupling of the traces.

For this reason, it is desired to provide traces which can grow in thickness rather than width, and which can utilize the thickness of two or more layers of a multi-layer circuit board to form the conductive traces.

The sequence of <FIG> shows example process steps for understanding the invention. <FIG> shows a cross section view of a catalytic laminate (or catalytic adhesive) <NUM> with the catalytic particle distribution plot of <FIG>, where the catalytic particles are distributed throughout the inner regions of the catalytic layer (either a catalytic laminate or catalytic adhesive), and the catalytic particles are below the surface exclusion depth <NUM> and <NUM> of the associated outer surfaces, thereby providing a density of catalytic particles from <NUM> to <NUM> which is sufficient to provide electroless deposition of conductive metal such as copper in regions which extend below the surface catalytic particle exclusion zone, and to exclude electroless deposition at native surfaces <NUM> or <NUM>.

Catalytic particles (not shown) in the region between <NUM> and <NUM> may be in the size range of 25u and smaller, in the present example they may be in the range 12u to 25u. The catalytic particles may include heterogeneous catalytic particles (organic or inorganic particles having a catalytic surface coating) or homogeneous particles (catalytic metal particles), as described previously. The exclusion boundary <NUM> is approximately 25u below the first surface <NUM>. The second surface <NUM> and second surface exclusion boundary <NUM> on the opposite surface are shown for reference, but it is understood that the process may be used on one or both sides of a candidate catalytic laminate or catalytic adhesive.

<FIG> shows the laminate of <FIG> with a channel <NUM> formed by removal of the surface layer <NUM> below exclusion zone <NUM> in a region where a trace is desired. The removal of surface material to form channels in the catalytic laminate or catalytic adhesive <NUM> may be by laser ablation, where the temperature of the catalytic pre-preg is instantly elevated until the catalytic pre-preg is vaporized, while leaving the surrounding catalytic prepreg structurally unchanged, leaving the catalytic particles exposed. It may be preferable to use a laser with a wavelength with a low reflectivity and high absorption of this optical wavelength for the pre-preg material being ablated, such as ultraviolet (UV) wavelengths. Examples of such UV lasers are the UV excimer laser or yttrium-aluminum-garnet (YAG) laser, which are also good choices because of the narrow beam extent and high available power which for forming channels of precise mechanical depth and with well-defined sidewalls. An example laser may remove material in a <NUM>-<NUM> mil (23u to 28u) diameter width with a depth governed by laser power and speed of movement across the surface. Another surface removal technique for forming channel <NUM> is plasma etching, which may be done locally or by preparing the surface with a patterned mask which excludes the plasma from the surface layers <NUM> or <NUM>, such as a dry film photoresist or other mask material which has a low plasma etch rate compared to the plasma etch rate of catalytic pre-preg. The photoresist thickness is typically chosen based on epoxy/photoresist etch selectivity (such that plasma etch to the desired depth of removal of the cured epoxy leaves sufficient photoresist at the end of the etch), or in the case of photoresist which is used as an electroplate mask, the thickness is chosen according to desired deposition thickness. Typical dry film thickness is in the range of <NUM>-<NUM> mil (<NUM>-64u). Plasmas suitable for etching the resin rich surface include mixtures of oxygen (O) and CF<NUM> plasmas, mixed with inert gasses such as nitrogen (N), or argon (Ar) may be added as carrier gasses for the reactive gases. A mask pattern may also be formed with a dry film mask, metal mask, or any other type of mask having apertures. Where a mechanical mask is used, the etch resist may be applied using any of photolithography, screen printing, stenciling, squeegee, or any method of application of etch resist. Another method for removal of the surface layer of catalytic pre-preg is mechanical grinding, such as a linear or rotational cutting tool. In this example, the catalytic pre-preg may be secured in a vacuum plate chuck, and a rotating cutter (or fixed cutter with movable vacuum plate) may travel a pattern defining the traces such as defined by x,y coordinate pairs of a Gerber format photofile. In another example of removing surface material, a water cutting tool may be used, where a water jet with abrasive particles entrained in the stream may impinge on the surface, thereby removing material below the first boundary <NUM>. Any of these methods may be used separately or in combination to remove surface material and form channel <NUM> from catalytic pre-preg <NUM>, with the channel extending below the first boundary <NUM>. Accordingly, the minimum channel depth is the depth required to expose the underlying catalytic particles, which is a characteristic of the cured pre-preg. As the catalytic material is dispersed uniformly through the cured pre-preg below the exclusion boundary <NUM>, the maximum channel depth may be limited by the depth of the woven fiber (such as fiberglass) fabric, which tends to complicate channel cleaning, as the fibers may break off and re-deposit in channels intended for electroless plating, or otherwise interfere with subsequent process steps. Typical channel depths are <NUM> mil (25u) to <NUM> mil (70u), but may extend deeper into the prepreg for reduced electrical resistance after electroless deposition. The final step after removing the surface material to form the channel <NUM> is to clean away any particles of material which were removed, which may be accomplished using ultrasound cleaning, jets of water mixed with surfactant, or any other cleaning means which does not result in surface <NUM> material surrounding the channel from being removed. Alternatively, the use of a catalytic adhesive, which may be applied to the underlying catalytic layer and cured, and contains no fabric, may be preferable for deep channels extending through a single layer, as there are no remaining fibers after ablation or channel formation to interfere with subsequent deposition steps.

<FIG> shows an electroless deposition <NUM> step, which is allowed to progress until the deposition approximately reaches the upper surface <NUM>, which allows for application of a subsequent layer of catalytic layer (which may be a catalytic laminate or catalytic adhesive) <NUM> shown in <FIG>. Catalytic layer <NUM> also has associated surface catalytic particle exclusions depth <NUM> and <NUM>, as did the catalytic layer <NUM> previously described. The use of catalytic adhesive for catalytic layer <NUM> is preferred to avoid interference between unablated or remaining fibers in the channel after the channels <NUM> are formed of <FIG>, which may interfere with the subsequent electroless copper deposition <NUM> of <FIG>. The subsequent layer of catalytic layer <NUM> may be bonded or laminated to the adjacent catalytic layer <NUM> and electroless deposition <NUM> of <FIG> using vacuum lamination or other process for layer bonding or lamination known in PCB fabrication prior art.

<FIG> shows the removal of catalytic layer <NUM> through the depth of catalytic layer <NUM> using the previously described method from the surface <NUM> of catalytic layer <NUM> through to the underlying electroless deposition <NUM> of the first layer <NUM>. The formation of the channel <NUM> may be done using any known method for removing laminate, although laser ablation is preferred.

<FIG> shows electroless plating <NUM> of the channel <NUM> from the deposition <NUM> below to the top level <NUM> of the catalytic layer <NUM>. The resulting circuit board now has a homogeneous trace with a trace thickness which is greater than the thickness of a single catalytic layer <NUM> or <NUM>. The circuit board may be used in a finished form of <FIG> in this manner after the addition of components. High current trace segments, such as trace segment <NUM> of <FIG>, may have its resistance reduced using the current method, and additional layers may be bonded or laminated to continue the process and increase the depth of the trace segment, as shown in <FIG> where catalytic layer <NUM> (where first exclusion surface <NUM> and second exclusion surface <NUM> may be present, as before).

<FIG> shows the subsequent step of forming channel <NUM> in catalytic layer <NUM> of <FIG>. <FIG> shows a final step, where electroless deposition of metal <NUM> is in electrical contact with previous electroless depositions <NUM> and <NUM>, thereby providing a method for forming a low resistance elongate conductor of selectable thickness, which can be narrower than allowed by the prior art for a given deposition metal resistivity (which translates to resistance per inch for a given trace thickness and width) of trace having a greater depth than provided in the prior art. Although boundaries are shown between trace deposition layers <NUM>, <NUM>, and <NUM> for clarity in understanding the steps of the process and resulting circuit, the electroless metal deposition is homogeneous across layers, providing a low resistance trace which spans the several dielectric layers and without the boundaries shown in the figures.

Electroless plating for <NUM> of <FIG> and <NUM> of <FIG> may be performed several different ways. One example electroless copper bath formulation uses a mixture of Rochelle salt as the complexing agent, copper sulfate as the copper metal source, formaldehyde as the reducing agent, and sodium hydroxide as a reactant. In this example, the tartrate (Rochelle salt) bath is preferred for ease of waste treatment; the Rochelle salt does not chelate as strongly as alternatives such as EDTA or quadrol. In this example, the tartrate (Rochelle salt) is the completing agent, copper sulfate is the metal source, formaldehyde is the reducing agent, and sodium hydroxide is a reactant. Other electroless plating formulations are possible, this example is given for reference. The electroless plating initially forms over the surfaces of the exposed catalytic particles and progresses until the deposition is below the native outer surfaces of the catalytic layer.

A key advantage of electroless plating of channels etched in catalytic material is that the electroless plating progresses on all three sides at once, compared to electroplating which only progresses from a bottom (initially plated) layer.

<FIG> shows a series of process steps for using catalytic layers (catalytic adhesive or catalytic laminate) to form circuit boards with trace layers having a thickness greater than a single laminate layer thickness. Apertures (if needed) are formed in step <NUM> such as for interlayer vias (not shown but well known in the prior art), followed by channels in step <NUM> such as channel <NUM> of <FIG>. Electroless plating is performed in step <NUM> corresponding to <NUM> of <FIG>, and a series of steps <NUM>, <NUM>, and <NUM> are iteratively performed as needed for each layer of laminate/channel/electroless plate to extend the thickness of the electroless deposition of step <NUM>. Step <NUM> corresponds to the bonded or laminated subsequent layers <NUM> of step 3D and layer <NUM> to <NUM> of step <NUM>. Step <NUM> corresponds to the formation of channels <NUM> of <FIG> or <NUM> of <FIG>. Step <NUM> corresponds to the electroless plating <NUM> of <FIG> or <NUM> of <FIG>. The process of adding additional layers to further extend the thickness of the traces may be performed by the path <NUM> following step <NUM> for each iteration.

The preceding description is only to provide examples of the invention for understanding the underlying mechanisms and structures used, and is not intended to limit the scope of the invention to only the particular methods or structures shown. For example, the sequences of <FIG> show a single sided construction with the trace channels formed over a plurality of catalytic layers built above a first layer <NUM>, whereas the first catalytic layer <NUM> may have surface <NUM> subsequently ablated to the level of electroless deposition <NUM> and additional layers added to surface <NUM> in the opposite direction using convention methods of multi-layer boards, or the method for extending the trace thickness described above.

The trace structures of <FIG> are shown in combination as they would normally occur on a PCB, these examples are only for illustration, and are not intended to limit the invention to these constructions. The result of using the present invention for the example given in <FIG> and <FIG> is that if trace 237A is. <NUM>" wide and <NUM> mil thick for a conventional subtractive circuit board process, and the top and underlying catalytic layers <NUM> mil thick (<NUM> mil total) were used to form the trace described in <FIG>, then trace <NUM> could be reduced from <NUM> mil to <NUM> mil width.

Claim 1:
A multi-layer circuit board comprising:
a first catalytic layer having a surface which contains an insufficient density of catalytic particles to enable electroless plating unless a channel extending an exclusion depth below the surface is reached, the first catalytic layer having a conductive trace formed by electroless deposition in a channel in the first catalytic layer, the channel extending into the first catalytic layer and below the exclusion depth for catalytic particles;
a second catalytic layer applied, bonded, or laminated to the first catalytic layer, the second catalytic layer having a channel formed through the thickness of the second catalytic layer and extending in depth to the conductive trace of the first catalytic layer;
the channel of the second catalytic layer filled with a conductive metal by electroless deposition and in contact with the electroless deposition of the first catalytic layer.