Patent Description:
Many wireless and wired communication systems employ Quadrature Amplitude Modulation (QAM) transceivers to transmit and receive data. Many QAM transceivers include a quadrature clock signal generator to provide the in-phase (I) and quadrature (Q) clock signals used for modulating or encoding transmit data and for demodulating or decoding receive data. Phase mismatch between the I and Q clock signals may introduce I/Q mismatch impairments in the transmitted and received signals, which in turn may cause signal degradation and data errors. Because I/Q phase mismatch may be related to clock frequencies, it is becoming more and more important to minimize I/Q phase mismatch as clock frequencies increase, for example, such as in multi-gigabit SERial/DESerial (SERDES) based communications.

<NPL> indicates that to support high-speed IOs, a <NUM>-to-<NUM> cross-coupled inverter-based multi-phase PLL with phase interpolators using injection locked oscillation buffers can be provided. The voltage-controlled oscillator (VCO) is made of two <NUM>-stage ting oscillators (RO), where the introduction of feedback and cross-coupled resistances enable the VCO to run at higher speeds compared to a conventional <NUM>-stage RO.

<NPL> present an energy-efficient forward-clock receiver in a <NUM> CMOS process. The receiver adopts an injection-locked ring oscillator (ILRO) to implement jitter filtering and phase de-skew. The proposed cascaded ILROs allegedly enable their receiver to maintain a constant jitter tracking bandwidth (JTB). The first-stage ILRO is used to control the JTB and filter out the high-frequency clock jitter that cannot track the data jitter. The second-stage ILRO is injected by the first one's outputs to generate precise quadrature clocks for phase shifting and de-skew.

<NPL> proposes a supply-regulated inverter-based clocking scheme. The proposed architecture uses only inverter-based circuits after an on-chip clock source. Only a single differential phase (I-Phase) clock is distributed to the local injection-locked ring oscillator (ILRO). The ILRO generates the multi-phase clocks for the phase interpolators on each channel. The phase interpolator is used to rotate the multi-phase clocks based on the transmitter or receiver frontend usage. The ILRO consists of a ring oscillator made of four identical pseudo-differential delay cells, injection locked by an input clock at frequency.

<NPL> describe a <NUM>-GHz direct-conversion transceiver using <NUM>-GHz quadrature oscillators. The transceiver has been fabricated in a standard <NUM>-nm CMOS process. It includes a receiver with a <NUM>-dB conversion gain and less than <NUM>-dB noise figure, a transmitter with a <NUM>-dB conversion gain, a <NUM>-dBm output <NUM> dB compression point, a <NUM>-dBm saturation output power and <NUM>-% power added efficiency. The <NUM>-GHz frequency synthesizer is implemented by a combination of a <NUM>-GHz PLL and a <NUM>-GHz quadrature injection-locked oscillator. Both transmitter and receiver are driven by a <NUM>-GHz PLL.

The aspects of the present invention are defined by the independent claims. Some preferred features are defined in the dependent claims.

This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Moreover, the systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.

One innovative aspect of the subject matter described in this disclosure can be used to reduce phase mismatch between in-phase (I) and quadrature (Q) clock signals by using a quadrature clock generator such as defined in independent claim <NUM>.

Another innovative aspect of the subject matter described in this disclosure can be implemented as a method for operating a quadrature clock generator such as defined in independent claim <NUM>.

The example implementations described herein are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings. Like numbers reference like elements throughout the drawings and specification.

Aspects of the present disclosure may be used to reduce or minimize I/Q mismatch and other phase errors that can degrade the signal integrity of wired and wireless communications. In some implementations, a quadrature clock generator is disclosed that utilizes two injection-locked oscillators and a single phase interpolator to generate a first set of in-phase (I) and quadrature (Q) clock signals and a second set of I and Q clock signals. The first and second sets of I and Q clock signals may be phase shifted relative to each other, and may be used to transmit and receive data. By using a single phase interpolator rather than multiple phase interpolators, aspects of the present disclosure may reduce phase mismatch compared to conventional quadrature clock generators.

In the following description, numerous specific details are set forth such as examples of specific components, circuits, and processes to provide a thorough understanding of the present disclosure. The term "coupled" as used herein means coupled directly to or coupled through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature and/or details are set forth to provide a thorough understanding of the example implementations. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the example implementations. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the present disclosure. Any of the signals provided over various buses described herein may be time-multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit elements or software blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses, and a single line or bus might represent any one or more of a myriad of physical or logical mechanisms for communication between components. The example implementations are not to be construed as limited to specific examples described herein but rather to include within their scope all implementations defined by the appended claims.

<FIG> shows a block diagram of an example programmable device <NUM> within which aspects of the present disclosure may be implemented. In some implementations, the device <NUM> may be formed on a single die. In other implementations, the device <NUM> may be distributed across a plurality of dice. In addition, or in the alternative, the device <NUM> may be implemented as a System-on-a-Chip (SoC) including a number of subsystems capable of interacting with one another. Thus, the programmable device <NUM> shown in <FIG> is an illustrative example of programmable devices within which aspects of the present disclosure may be implemented; other implementations with additional or fewer blocks or modules, in a similar or different arrangement, are possible.

The device <NUM> may include a number of subsystems such as, for example, programmable logic (PL) <NUM>, a network-on-chip (NoC) interconnect system <NUM>, dedicated circuitry <NUM>, a CCIX and PCle Module (CPM) <NUM>, connectivity fabric <NUM>, transceivers <NUM>, input/output (I/O) blocks <NUM>, and memory controllers <NUM>. In one or more implementations, the device <NUM> may include other subsystems or components not shown in <FIG>. Further, although not shown for simplicity, the device <NUM> may be coupled to a number of peripheral components (such as one or more high-performance memory devices <NUM>) and/or other devices or chips (such as another programmable device).

The PL <NUM> includes circuitry that may be programmed to perform a number of different user-defined functions or operations. In some implementations, the PL <NUM> may include an array of programmable circuit blocks or tiles each including programmable interconnect circuitry and programmable logic circuitry. The programmable circuit blocks may include (but are not limited to) configurable logic blocks (CLBs), random access memory blocks (BRAM), digital signal processing blocks (DSPs), clock managers, delay lock loops (DLLs), and/or other logic or circuits that can be programmed or configured to implement a user-specified circuit design. In addition, or in the alternative, the PL <NUM> may include a number of input/output blocks (IOBs). In one or more implementations, the PL <NUM> may be implemented as an array of programmable fabric sub-regions (FSRs) that can be distributed across the programmable fabric. In some aspects, the FSRs may be implemented as repeatable tiles within the programmable fabric.

The programmable interconnect circuitry may include a plurality of interconnect wires of varying lengths interconnected by programmable interconnect points (PIPs). The interconnect wires may be configured to provide connectivity between components within a particular programmable tile, between components within different programmable tiles, and between components of a programmable tile and other subsystems or devices. The programmable interconnect circuitry and the programmable circuit blocks may be programmed or configured by loading configuration data into configuration registers that define how the programmable elements are configured and operate to implement a corresponding user-specified circuit design. In some aspects, the programmable interconnect circuitry within each of a number of the programmable circuit blocks may form part of a programmable interconnect fabric that provides block-level and/or device-level signal routing resources for the device <NUM>.

Each CLB may include look-up tables (LUTs), flip-flops, combinational logic, and/or programmable interconnect circuitry that can be collectively programmed by the configuration data to perform various logic functions (such as addition and subtraction) on input signals of varying widths. The LUTs may be of any suitable size, and may include any suitable number of inputs and outputs. In some aspects, each CLB may include <NUM> LUTs and <NUM> flip-flops. Each of the CLBs may also include arithmetic carry logic and multiplexers that can be used to implement wider logic functions. In some implementations, the resources of the PL <NUM> may be implemented as repeatable tiles arranged in columns in the programmable device <NUM>, and may be divided into a number of regions of a fixed height and width. For the example of <FIG>, the PL <NUM> is depicted as occupying different regions of the device <NUM>. In other implementations, the PL <NUM> may be implemented as a unified region of programmable fabric.

The NoC interconnect system <NUM>, which may be fabricated as part of the device <NUM>, provides a high-speed, high-bandwidth programmable signal routing network that may selectively interconnect the various resources, subsystems, circuits, and other components of the device <NUM>. In some implementations, the NoC interconnect system <NUM> may extend in the horizontal and vertical directions across the programmable fabric (e.g., towards the edges) of the device <NUM>, as shown in <FIG>. In addition, or in the alternative, the NoC interconnect system <NUM> may extend in one or more diagonal directions across the programmable fabric. Further, although shown in the example of <FIG> as having a single columnar portion, in other implementations, the NoC interconnect system <NUM> may include a plurality of columnar portions extending vertically across the height of the programmable fabric. Thus, the particular layout, shape, size, orientation, and other physical characteristics of the example NoC interconnect system <NUM> are merely illustrative of the various implementations disclosed herein.

In some implementations, the NoC interconnect system <NUM> may employ a data packet protocol and memory-mapped addresses to route information between the various resources, subsystems, circuits, and other components of the device <NUM> as packetized data. The data packets may include source addresses, destination addresses, and protocol information that can be used by the NoC interconnect system <NUM> to route the data packets to their indicated destinations. In one or more implementations, the data packets may include Quality-of-Service (QoS) information that allows the transmission of data packets through the NoC interconnect system <NUM> to be prioritized, for example, based on assigned priorities, traffic types, and/or flow information. In such implementations, the NoC interconnect system <NUM> may include priority logic that can determine priority levels or traffic classes of received data packets, and use the determined priority levels or traffic classes when queuing the data packets for transmission.

Although not shown for simplicity, the NoC interconnect system <NUM> may also include a scheduler and arbitration logic. The scheduler may be used to schedule the transmission of data packets from a source address to a destination address using one or more physical and/or virtual channels of the NoC interconnect system <NUM>. The arbitration logic may be used to arbitrate access to the NoC interconnect system <NUM>, for example, to minimize collisions and other contention-related latencies. For implementations in which the device <NUM> is fabricated using stacked silicon interconnect (SSI) technology, the columnal portions of the NoC interconnect system <NUM> may provide signal connections between adjacent super logic regions (SLRs), for example, to allow configuration data to be routed between master and slave SLRs.

In some implementations, the NoC interconnect system <NUM> may include a plurality of nodes, ports, or other interfaces (not shown for simplicity) that provide selective connectivity between the NoC interconnect system <NUM> and the various resources, subsystems, circuits, and other components of the device <NUM>. For example, the NoC interconnect system <NUM> may allow multiple subsystems of the device <NUM> to share access to on-chip memory (OCM) resources, processing resources, and/or I/O resources. By selectively interconnecting the various resources, subsystems, circuits, and other components of the device <NUM> that can demand and use large amounts of data, the NoC interconnect system <NUM> may alleviate signal routing burdens on local interconnect resources, thereby increasing device performance and allowing for greater configuration flexibility than other programmable devices. Moreover, by providing a high-performance signal routing network having higher data transmission rates and lower error rates than device-level and block-level programmable interconnects, the NoC interconnect system <NUM> may increase the processing power and data throughput of the device <NUM> (as compared to other programmable devices).

The dedicated circuitry <NUM> may include any suitable hard-wired circuits including (but not limited to) processors, serial transceivers, digital signal processors (DSPs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), device management resources, device monitoring resources, device testing management resources, and so on. In some implementations, the dedicated circuitry <NUM> may include a processing system (PS) and a platform management controller (PMC). In some implementations, the PS may include a number of processor cores, cache memory, and unidirectional and/or bidirectional interfaces configurable to couple directly to the I/O pins of the device <NUM>. In some aspects, each processor core may include central processing units (CPU) or scalar processors that can be used for sequential data processing. The PMC may be used for booting and configuring the device <NUM> based on configuration data (such as a configuration bitstream) provided from external memory. The PMC may also be used to configure the PL <NUM> and to control various encryption, authentication, system monitoring, and debug capabilities of the device <NUM>.

The CCIX and PCle module (CPM) <NUM> may include a number of interfaces that provide connectivity between the device <NUM> and a number of peripheral components (such as external devices or chips). In some implementations, the CPM <NUM> may include a number of peripheral interconnect express (PCle) interfaces and cache coherent interconnect for accelerators (CCIX) interfaces that provide connectivity to other devices or chips via the transceivers <NUM>. In some aspects, the PCle and CCIX interfaces may be implemented as part of the transceivers <NUM>.

The programmable interconnect fabric (not shown for simplicity) may provide block-level and/or device-level signal routing resources that can selectively interconnect circuits and subsystems in nearby regions of the programmable fabric based on configuration data loaded into corresponding configuration registers. In some implementations, the programmable interconnect fabric may include a plurality of fabric sub-regions (FSRs) that can be implemented as repeatable tiles and distributed across the device <NUM>. In some aspects, the FSRs may include portions of the programmable interconnect elements associated with the various programmable logic circuits (such as CLBs, DSPs, and BRAM) of the PL <NUM>.

The transceivers <NUM> may provide signal connections with one or more other devices or chips (not shown for simplicity) connected to the device <NUM>. The transceivers <NUM> may include a number of different data serializers and deserializers (SERDES) such as, for example, gigabit serial transceivers. In some implementations, the transceivers <NUM> may be implemented as a number of repeatable tiles positioned in various locations along the right and left sides of the device <NUM>, as depicted in <FIG>. In other implementations, the transceivers <NUM> may be positioned in other suitable locations of the device <NUM>.

The I/O blocks <NUM> are coupled to the device's I/O pins (not shown for simplicity), and may provide I/O capabilities for the device <NUM>. For example, the I/O blocks <NUM> may receive data from one or more other devices, and may drive the received data to a number of destinations in the device <NUM>. The I/O blocks <NUM> may also receive data from a number of sources in the device <NUM>, and may drive the received data to one or more other devices via the device's I/O pins. In some implementations, the I/O blocks <NUM> may be implemented as repeatable tiles. The device <NUM> may include any suitable number of I/O blocks <NUM>, and therefore the example implementation depicted in <FIG> is merely illustrative.

The I/O blocks <NUM> may include any number of suitable I/O circuits or devices. In some implementations, the I/O blocks <NUM> may include extremely high-performance I/O (XPIO) circuits, high-density I/O (HDIO) circuits, and multiplexed I/O (MIO) circuits. The XPIO circuits may be optimized for high-performance communications such as providing a high-speed, low latency interface to the memory controllers <NUM>. The HDIO circuits may provide a cost-effective solution that supports lower speed and higher voltage I/O capabilities (as compared with the XPIO circuits). The MIO circuits may provide general-purpose I/O resources that can be accessed by various subsystems such as, for example, the PL <NUM>, the dedicated circuitry <NUM>, and the CPM <NUM>.

In some implementations, a first row of I/O blocks <NUM> may be implemented as repeatable tiles positioned along a bottom edge of the device <NUM>, and a second row of I/O blocks <NUM> may be implemented as repeatable tiles positioned along a top edge of the device <NUM>. In some aspects, the repeatable tiles that implement the I/O blocks <NUM> may be different from one another. For example, some I/O blocks <NUM> may implement XPIO circuits, other I/O blocks <NUM> may implement HDIO circuits, and other I/O blocks <NUM> may implement MIO circuits.

The memory controllers <NUM> may be used to control access to various memory resources provided within and/or external to the device <NUM>. The memory controllers <NUM> may include double data rate v4 (DDR4) memory controllers, double data rate v5 (DDR5) memory controllers, high bandwidth memory (HBM) controllers, and/or other suitable memory controllers. In one or more implementations, some or all of the memory controllers <NUM> may include a scheduler having transaction reordering capabilities that may improve memory access efficiency.

In some implementations, a first row of memory controllers <NUM> may be implemented as repeatable tiles positioned along the bottom edge of the device <NUM>, and a second row of memory controllers <NUM> may be implemented as repeatable tiles positioned along the top edge of the device <NUM>. In some aspects, the repeatable tiles that implement the memory controllers <NUM> may be different from one another. For example, a first number of the memory controllers <NUM> may implement DDR4 memory controllers, a second number of the memory controllers <NUM> may implement LPDDR4 memory controllers, and a third number of the memory controllers <NUM> may implement HBM controllers. The repeatable tiles that implement the I/O blocks <NUM> and memory controllers <NUM> may be alternately positioned or distributed relative to each other, for example, as depicted in the example of <FIG>. The device <NUM> may include any number of the I/O blocks <NUM> and memory controllers <NUM>, and therefore the numbers and positions of the I/O blocks <NUM> and memory controllers <NUM> depicted in <FIG> are merely illustrative.

Although not shown in <FIG> for simplicity, the device <NUM> may include a Boundary Logic Interface (BLI) that provides connectivity between the I/O blocks <NUM> and programmable interconnects provided within the PL <NUM>. In some aspects, the BLI may allow large and complex external devices (such as HBM) to appear as much smaller blocks (such as a CLB) in the programmable fabric of the device <NUM>. In some implementations, the BLI may be arranged in rows positioned at the top and bottom boundaries or edges of the programmable fabric. In this manner, the BLI may be used to route signals between columnar logic structures (such as a CLB column or a DSP column) and rows of I/O resources (such as the I/O blocks <NUM>).

<FIG> shows a simplified block diagram of a transceiver <NUM>, according to some implementations. The transceiver <NUM>, which may be one example of one or more of the transceivers <NUM> of <FIG>, is shown to include a transmit (TX) front end <NUM>, a transmit data processing block <NUM>, a quadrature clock generator <NUM>, a receive (RX) data processing block <NUM>, and a receive front end <NUM> coupled between an input terminal (IN) and an output terminal (OUT). In some implementations, the transceiver <NUM> may be a gigabit SERDES transceiver. In other implementations, the transceiver <NUM> may be of another suitable type or configuration.

The quadrature clock generator <NUM>, which is coupled to the TX data processing block <NUM> and to the RX data processing block <NUM>, includes an input terminal to receive a reference clock signal CLKREF. For the example of <FIG>, the reference clock signal CLKREF is generated by a reference clock generator <NUM>, which may be any feasible reference clock source including (but not limited to) a crystal-based oscillator, a phase-locked loop, or the like. In other implementations, the reference clock signal CLKREF may be generated by another suitable circuit or oscillator.

The quadrature clock generator <NUM> may generate a first quadrature clock signal <NUM> and a second quadrature clock signal <NUM> based on CLKREF. In some implementations, the first quadrature clock signal <NUM> may be used for transmitting data, and the second quadrature clock signal <NUM> may be used for receiving data. Although not shown in <FIG> for simplicity, the first quadrature clock signal <NUM> may include an in-phase (I) component and a quadrature (Q) component, and the second quadrature clock signal <NUM> may include an I component and a Q component. In some implementations, the I and Q components (which may also be referred to as I and Q clock signals) of the first quadrature clock signal <NUM> may be implemented as differential signals, and the I and Q components (which may also be referred to as the I and Q clock signals) of the second quadrature clock signal <NUM> may be implemented as differential signals.

In one or more implementations, the first quadrature clock signal <NUM> may be related in frequency to the second quadrature clock signal <NUM>, but may be offset in phase relative to the second quadrature clock signal <NUM>. For example, the first and second quadrature clock signals <NUM>-<NUM> may have the same frequency and offset in phase from one another by <NUM> degrees. For another example, the first and second quadrature clock signals <NUM>-<NUM> may have the same frequency and offset in phase from one another by <NUM> degrees (or some other suitable integer multiple of <NUM> degrees).

The transmit data processing block <NUM>, which is coupled between the quadrature clock generator <NUM> and the transmit front end <NUM>, may receive the first quadrature clock signal <NUM> generated by the quadrature clock generator <NUM>. The transmit data processing block <NUM> may also receive output data <NUM> to be transmitted by the transceiver <NUM>. The output data <NUM> may be provided by the PL <NUM>, the dedicated circuitry <NUM>, or any other feasible circuit, component, or subsystem of the programmable device <NUM> of <FIG>. The transmit data processing block <NUM> may use the first quadrature clock signal <NUM> to encode and/or modulate the output data <NUM> for transmission. In some implementations, the transmit data processing block <NUM> may serialize the output data <NUM> based on the first quadrature clock signal <NUM>.

The transmit front end <NUM> may process the encoded and/or modulated output data provided by the transmit data processing block <NUM>, and may provide the processed output data as transmit data <NUM> to a wired or wireless communication medium. The transmit front end <NUM> may include any number of circuits or components suitable for preparing the processed output data for transmissions as transmit data <NUM>. For example, in some aspects, the transmit front end <NUM> may include amplifiers, mixers, filters, and other components configured to increase signal integrity while minimizing noise, distortion, and timing errors.

The receive front end <NUM> may receive RX data <NUM> from one or more other devices or circuits, either via a wireless medium or a wired connection, via the input terminal IN. In some implementations, the receive front end <NUM> may include amplifiers, mixers, filters, and any other circuit or component suitable for maximizing data reception rates while minimizing data loss, noise, and distortion. The receive front end <NUM> may provide the RX data <NUM> to the receive data processing block <NUM>.

The receive data processing block <NUM>, which is also coupled to the quadrature clock generator <NUM>, may use the second quadrature clock signal <NUM> to decode and/or demodulate the RX data <NUM> to generate input data <NUM>. The input data <NUM> may be provided (or routed) to the PL <NUM>, the dedicated circuitry <NUM>, or any other feasible circuit, component, or subsystem of the programmable device <NUM> of <FIG>. In some implementations, the receive data processing block <NUM> may deserialize the RX data <NUM> based on the second quadrature clock signal <NUM>.

<FIG> shows a block diagram of an example quadrature clock generator <NUM>, according to some implementations that are not comprised in the scope of the present invention. The quadrature clock generator <NUM> may include an injection-locked oscillator (ILO) <NUM>, a first phase interpolator <NUM>, a second phase interpolator <NUM>, a quadrature-locked loop (QLL) <NUM>, and a voltage regulator <NUM>. In some aspects, the quadrature clock generator <NUM> may be one example of the quadrature clock generator <NUM> of <FIG>.

The ILO <NUM>, which includes a first input coupled to the reference clock generator <NUM>, a second input coupled to the voltage regulator <NUM>, and an output coupled to the first and second phase interpolators <NUM>-<NUM>, may be any suitable ILO that can generate a plurality of clock signals having the same frequency as the reference clock signal CLKREF yet offset in phase relative to each other. In some implementations, the ILO <NUM> may be configured as a differential oscillator, and the reference clock generator <NUM> may provide CLKREF as a differential clock signal.

The ILO <NUM> may generate a number M of clock signals CLKILO that are frequency-locked to CLKREF, where M is an integer greater than one. The clock signals CLKILO, which may also be referred to as clock phases, may be equally spaced or offset in phase from one each other, for example, such that each of the clock signals CLKILO has a unique phase that is an integer multiple of a reference phase offset. For example, in the implementation of <FIG>, the ILO <NUM> generates M = eight clock signals CLKILO that are offset in phase from each other by forty-five degrees, where a first clock signal CLK_0 has no phase offset, a second clock signal CLK_45 has a phase offset of <NUM> degrees relative to CLK_0, a third clock signal CLK_90 has a phase offset of <NUM> degrees relative to CLK_0, a fourth clock signal CLK_135 has a phase offset of <NUM> degrees relative to CLK_0, a fifth clock signal CLK_180 has a phase offset of <NUM> degrees relative to CLK_0, a sixth clock signal CLK_225 has a phase offset of <NUM> degrees relative to CLK_0, a seventh clock signal CLK_270 has a phase offset of <NUM> degrees relative to CLK_0, and an eighth clock signal CLK_315 has a phase offset of <NUM> degrees relative to CLK_0.

The first phase interpolator <NUM> and the second phase interpolator <NUM> may be implemented using complementary metal oxide silicon (CMOS) technology, current mode logic (CML), or any other feasible technology. The first phase interpolator <NUM> may use a first set of the M clock signals CLKILO provided by the ILO <NUM> to generate one or more in-phase (I) output clock signals, and the second phase interpolator <NUM> may use a second set of the M clock signals CLKILO provided by the ILO <NUM> to generate one or more quadrature (Q) output clock signals. In the example of <FIG>, the first phase interpolator <NUM> may generate a differential in-phase (I) output clock signal represented as I and I signals, where I is the logical complement of I. Similarly, the second phase interpolator <NUM> may generate a differential quadrature (Q) output clock signal represented as Q and Q signals, where Q is the logical complement of Q. In other instances, the first and second phase interpolators <NUM>-<NUM> may generate single-ended I and Q clock signals, respectively.

In some implementations, the first phase interpolator <NUM> may interpolate between a pair of adjacent clock signals of the first set (or the second set) of clock signals CLKILO to generate the in-phase output clock signals, for example, such that the I and I signals may have any desired phase. Similarly, the second phase interpolator <NUM> may interpolate between a pair of adjacent clock signals of the second set (or the first set) of clock signals CLKILO to generate the quadrature output clock signal, for example, such that the Q and Q signals may have any desired phase.

The QLL <NUM> includes a number of inputs coupled to one or more outputs of the ILO <NUM>, and includes an output coupled to a control terminal of the voltage regulator <NUM>. In some implementations, the QLL <NUM> may receive the M clock signals CLKILO (such as clock signals CLK_0, CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, and CLK_315), and may be configured to generate a control signal (CTRL) based on one or more relationships between the M clock signals CLKILO. The CTRL signal is provided to the control input of the voltage regulator <NUM>, which in turn may generate a reference voltage VREF based at least in part on the CTRL signal.

The voltage regulator <NUM> may provide the reference voltage VREF to control terminals of the ILO <NUM>, the first phase interpolator <NUM>, and the second phase interpolator <NUM>. The reference voltage VREF may be used to control, adjust, or modify one or more operating characteristics of the ILO <NUM>, the first phase interpolator <NUM>, and the second phase interpolator <NUM>.

In some implementations, the QLL <NUM> may also receive one or more signals (not shown for simplicity) provided by the receive data processing block <NUM> of <FIG>. These one or more signals may embody or indicate various characteristics of incoming RX data, and the QLL <NUM> may be configured to generate the control signal CTRL based at least in part on these one or more signals. For example, in some aspects, these one or more signals may adjust the reference voltage VREF in a manner that causes the first phase interpolator <NUM> to maintain a certain relationship between the in-phase output clock signal and the RX data, and/or that causes the second phase interpolator <NUM> to maintain a certain relationship between the quadrature output clock signal and the RX data.

Mismatches between circuit elements (such as mixers and filters) within the first and second phase interpolators <NUM>-<NUM> may cause timing mismatch between the in-phase output clock signal and the quadrature clock signal. In accordance with other aspects of the present disclosure, timing mismatch between the I and Q output clock signals may be avoided by using single phase interpolator (rather than the two phase interpolators <NUM>-<NUM> of <FIG>).

<FIG> shows a block diagram of another example quadrature clock generator <NUM>, according to some implementations. The quadrature clock generator <NUM>, which may be an example of the quadrature clock generator <NUM> of <FIG>, is shown to include a first ILO <NUM>, a second ILO <NUM>, a phase interpolator <NUM>, a number of buffers <NUM>, <NUM>, and <NUM>, a number of select circuits <NUM> and <NUM>, a quadrature-locked loop (QLL) <NUM>, a voltage regulator <NUM>, a coarse frequency tracking circuit <NUM>, and a switch <NUM>.

The first ILO <NUM>, which includes a first input coupled to receive a first reference voltage VREF1, a second input coupled to the voltage regulator <NUM>, and an output coupled to the first buffer <NUM>, may be any suitable ILO that can generate a plurality of clock signals having the same frequency as the reference clock signal CLKREF yet offset in phase relative to each other. The first reference clock signal CLKREF may be generated by the reference clock generator <NUM> (not shown in <FIG> for simplicity), or alternatively by another suitable clock generation circuit. In some implementations, the first ILO <NUM> may be configured as a differential oscillator, and the reference clock generator <NUM> may provide CLKREF1 as a differential clock signal.

The first ILO <NUM> may generate a number P of first clock signals CLKILO1 that are frequency-locked to CLKREF1, where P is an integer greater than one. The first clock signals CLKILO1, which may also be referred to as clock phases, may be equally spaced or offset in phase from one each other, for example, such that each of the first clock signals CLKILO1 has a unique phase that is an integer multiple of a reference phase offset. For example, in some implementations, the first ILO <NUM> may generate P = <NUM> first clock signals CLKILO1 that are offset in phase from each other by forty-five degrees, where a first clock signal CLK_0 has no phase offset, a second clock signal CLK_45 has a phase offset of <NUM> degrees relative to CLK_0, a third clock signal CLK_90 has a phase offset of <NUM> degrees relative to CLK_0, a fourth clock signal CLK_135 has a phase offset of <NUM> degrees relative to CLK_0, a fifth clock signal CLK_180 has a phase offset of <NUM> degrees relative to CLK_0, a sixth clock signal CLK_225 has a phase offset of <NUM> degrees relative to CLK_0, a seventh clock signal CLK_270 has a phase offset of <NUM> degrees relative to CLK_0, and an eighth clock signal CLK_315 has a phase offset of <NUM> degrees relative to CLK_0.

In some implementations, the first clock signals CLKILO1 generated by the first ILO <NUM> may be buffered by the buffer <NUM> to generate buffered first clock signals CLKILO1', which may be provided to the phase interpolator <NUM> and to the first select circuit <NUM>. In other implementations, the optional buffer <NUM> (as indicated by the dashed lines) may be omitted, and the first clock signals CLKILO1 may be provided to the phase interpolator <NUM> and to the first select circuit <NUM>. In some implementations, the optional buffer <NUM> (as indicated by the dashed lines) may buffer the buffered first clock signals CLKILO1' for the phase interpolator <NUM>. In other implementations, the optional buffer <NUM> may be omitted.

The phase interpolator <NUM> may use the first clock signals CLKILO1 provided by the first ILO <NUM> to generate a second reference clock signal CLKREF2. In the example of <FIG>, the phase interpolator <NUM> may generate the second reference clock signal CLKREF2 as a differential signal. In some implementations, the phase interpolator <NUM> may interpolate between a pair of adjacent clock signals of the plurality of first clock signals CLKILO1 to generate the second reference clock signal CLKREF2. In this manner, the phase interpolator <NUM> may generate the second reference clock signal CLKREF2 with an arbitrary phase relationship to the first clock signals CLKILO1. In addition, or in the alternative, the phase interpolator <NUM> may receive a signal <NUM> from an associated receive circuit (such as a clock data recovery circuit and/or a receive data processing block), and may use the signal <NUM> to control or adjust the interpolation.

The phase interpolator <NUM> may be implemented using complementary metal oxide silicon (CMOS) technology, current mode logic (CML), or any other feasible technology. In some implementations, the phase interpolator <NUM> may be an example of the first phase interpolator <NUM> or the second phase interpolator <NUM> of <FIG>. Thus, although not shown for simplicity, each of the number P of first clock signals CLKILO1 may be provided to corresponding inputs of the phase interpolator <NUM>, and the phase interpolator <NUM> may generate the second reference clock signal CLKREF2 based on relationships between the number P of first clock signals CLKILO1.

The first select circuit <NUM> is configured to select two (or a pair) of the first clock signals CLKILO1 to provide as I/Q output clock signals <NUM>. In some implementations, the first select circuit <NUM> may select any suitable pair of the first clock signals CLKILO1 to provide as I/Q TX output clock signals <NUM>. A transmit circuit, such as the transmit data processing block <NUM> of <FIG>, may use the I/Q output clock signals <NUM> to encode or modulate data for transmission.

The second ILO <NUM>, which includes first inputs coupled to the phase interpolator <NUM>, a second input to receive VREF from the voltage regulator <NUM>, and an output coupled to an optional buffer <NUM> (as indicated by the dashed lines), may be any suitable ILO that can generate a plurality of clock signals having the same frequency as the second reference clock signal CLKREF2 yet offset in phase relative to each other. The second ILO <NUM> may generate a number P of second clock signals CLKILO2 that are frequency-locked to CLKREF2, where P is an integer greater than one. The second clock signals CLKILO2, which may also be referred to as clock phases, may be equally spaced or offset in phase from one each other, for example, such that each of the second clock signals CLKILO2 has a unique phase that is an integer multiple of a reference phase offset.

In some implementations, the second clock signals CLKILO2 may also be equally spaced or offset in phase from one each other, for example, such that each of the second clock signals CLKILO2 has a unique phase that is an integer multiple of a reference phase offset. For example, in some implementations, the second ILO <NUM> may generate P = <NUM> second clock signals CLKILO2 that are offset in phase from each other by forty-five degrees, where a first clock signal CLK_0 has no phase offset, a second clock signal CLK_45 has a phase offset of <NUM> degrees relative to CLK_0, a third clock signal CLK_90 has a phase offset of <NUM> degrees relative to CLK_0, a fourth clock signal CLK_135 has a phase offset of <NUM> degrees relative to CLK_0, a fifth clock signal CLK_180 has a phase offset of <NUM> degrees relative to CLK_0, a sixth clock signal CLK_225 has a phase offset of <NUM> degrees relative to CLK_0, a seventh clock signal CLK_270 has a phase offset of <NUM> degrees relative to CLK_0, and an eighth clock signal CLK_315 has a phase offset of <NUM> degrees relative to CLK_0. In some aspects, the second clock signals CLKILO2 may be provided to the optional buffer <NUM> to generate a plurality of buffered second clock signals CLKILO2'.

The second select circuit <NUM> is configured to select two (or a pair) of the second clock signals CLKILO2 to provide as I/Q RX output clock signals <NUM>. In some implementations, the second select circuit <NUM> may select any suitable pair of the second clock signals CLKILO2 to provide as the I/Q RX output clock signals <NUM>. A receive circuit, such as the receive data processing block <NUM> of <FIG>, may use the I/Q RX output clock signals <NUM> to decode or demodulate data received by the transceiver <NUM>.

The QLL <NUM> includes a number of inputs coupled to one or more outputs of the second ILO <NUM> (via the optional buffer <NUM>), and includes an output coupled to a control terminal of the voltage regulator <NUM>. In some implementations, the QLL <NUM> may receive the number P of second clock signals CLKILO2 (such as clock signals CLK_0, CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, and CLK_315), and may be configured to generate a control signal (CTRL) based on one or more relationships between the second clock signals CLKILO2. The CTRL signal is provided to the control input of the voltage regulator <NUM>, which in turn may generate a reference voltage VREF based at least in part on the CTRL signal.

The voltage regulator <NUM> may provide the reference voltage VREF to control terminals of the first ILO <NUM>, the second ILO <NUM>, the phase interpolator <NUM>, and the optional buffers <NUM> and <NUM>. The reference voltage VREF may be used to control, adjust, or modify one or more operating characteristics of the first ILO <NUM>, the second ILO <NUM>, and the phase interpolator <NUM> (as well as the optional buffers <NUM> and <NUM>). In some implementations, the QLL <NUM> may control or adjust the value of the control signal (CTRL) based on the relative phases of the second clock signals CLKILO2. The voltage regulator <NUM> may adjust the value of VREF based at least in part on the control signal (CTRL), thereby allowing the QLL <NUM> to essentially control various operations of the first ILO <NUM>, the second ILO <NUM>, and the phase interpolator <NUM>. In some implementations, the voltage regulator <NUM> may also control operation of the optional buffers <NUM> and <NUM>.

The coarse frequency tracking circuit <NUM>, which may include a finite state machine (FSM) <NUM> and a digital-to-analog converter (DAC) <NUM>, may be used to control initial start-operations of at least the first ILO <NUM> and the second ILO <NUM>. In some implementations, the coarse frequency tracking circuit <NUM> may generate a control voltage VCTRL in response to detecting a start-up condition, and use the control voltage VCTRL to temporarily disable the CTRL signal generated by the QLL <NUM> during the start-up operation. More specifically, upon detecting a start-up condition, the FSM <NUM> may assert a select signal that causes the switch <NUM> to close (such as in a conductive state), and may output a digital voltage or code that causes the DAC <NUM> to drive VCTRL to a level that disables the CTRL signal via the switch <NUM>, for example, such that the voltage regulator <NUM> can control oscillation frequencies of at least the first ILO <NUM> and the second ILO <NUM> before quadrature lock is established during start-up conditions. At other times, the FSM <NUM> may deassert the SEL signal to open the switch <NUM> (such as to maintain the switch <NUM> in a non-conductive state).

In some implementations, an I/Q mismatch may exist between the I/Q TX clock signals <NUM> and/or may exist between the I/Q RX clock signals <NUM>. Mismatches between the I/Q TX clock signals <NUM> and mismatches between the I/Q RX clock signals <NUM> may be caused by the QLL <NUM> monitoring the second clock signals CLKILO2 while not monitoring the first clock signals CLKILO1.

<FIG> shows a block diagram of another example quadrature clock generator <NUM>, according to other implementations. The quadrature clock generator <NUM> is similar in many aspects to the quadrature clock generator <NUM> of <FIG>, except that the QLL <NUM> receives the buffered first clock signals CLKILO1' as input signals, for example, rather than the buffered second clock signals CLKILO2'.

<FIG> shows a block diagram of another example quadrature clock generator <NUM>, according to some implementations. The quadrature clock generator <NUM> may include a first ILO <NUM>, a second ILO <NUM>, a phase interpolator <NUM>, a first optional buffer <NUM>, a first select circuit <NUM>, a second optional buffer <NUM>, a second select circuit <NUM>, a first QLL <NUM>, a second QLL <NUM>, a first voltage regulator <NUM>, a second voltage regulator <NUM>, a coarse frequency tracking circuit <NUM>, a first switch <NUM>, and a second switch <NUM>. As discussed in more detail below, the quadrature clock generator <NUM> may use the first QLL <NUM> to control the I/Q TX clock signals <NUM> used by a transmit data processing block, and may use the second QLL <NUM> to control the I/Q RX clock signals <NUM> used by a receive data processing block.

The first ILO <NUM>, which includes first inputs coupled to receive a first reference clock signal CLKREF1, a second input to receive a first reference voltage VREF1 generated by the first voltage regulator <NUM>, and an output coupled to the first buffer <NUM>, may be any suitable ILO that can generate a plurality of clock signals having the same frequency as the first reference clock signal CLKREF1 yet offset in phase relative to each other. The first reference clock signal CLKREF1 may be generated by the reference clock generator <NUM> (not shown in <FIG> for simplicity), or alternatively by another suitable clock generation circuit. In some implementations, the first ILO <NUM> may be configured as a differential oscillator, and the reference clock generator <NUM> may provide CLKREF1 as a differential clock signal.

The first ILO <NUM> may generate a number N of first clock signals CLKILO1 that are frequency-locked to CLKREF1, where N is an integer greater than one. The first clock signals CLKILO1, which may also be referred to as clock phases, may be equally spaced or offset in phase from one each other, for example, such that each of the first clock signals CLKILO1 has a unique phase that is an integer multiple of a reference phase offset. For example, in some implementations, the first ILO <NUM> may generate N = <NUM> first clock signals CLKILO1 that are offset in phase from each other by forty-five degrees, where a first clock signal CLK_0 has no phase offset, a second clock signal CLK_45 has a phase offset of <NUM> degrees relative to CLK_0, a third clock signal CLK_90 has a phase offset of <NUM> degrees relative to CLK_0, a fourth clock signal CLK_135 has a phase offset of <NUM> degrees relative to CLK_0, a fifth clock signal CLK_180 has a phase offset of <NUM> degrees relative to CLK_0, a sixth clock signal CLK_225 has a phase offset of <NUM> degrees relative to CLK_0, a seventh clock signal CLK_270 has a phase offset of <NUM> degrees relative to CLK_0, and an eighth clock signal CLK_315 has a phase offset of <NUM> degrees relative to CLK_0.

In some implementations, the first clock signals CLKILO1 generated by the first ILO <NUM> may be buffered by the buffer <NUM> to generate buffered first clock signals CLKILO1', which may be provided to the phase interpolator <NUM>, the first select circuit <NUM>, and the first QLL <NUM>. In other implementations, the optional buffer <NUM> (as indicated by the dashed lines) may be omitted, and the first clock signals CLKILO1 may be provided to the phase interpolator <NUM>, the first select circuit <NUM>, and the first QLL <NUM>. In some implementations, the optional buffer <NUM> (as indicated by the dashed lines) may buffer the buffered first clock signals CLKILO1' for the phase interpolator <NUM>. In other implementations, the optional buffer <NUM> may be omitted.

The first QLL <NUM> includes a number of inputs coupled to one or more outputs of the first ILO <NUM> (via the optional buffer <NUM>), and includes an output coupled to a control terminal of the first voltage regulator <NUM>. In some implementations, the first QLL <NUM> may receive the number N of first clock signals CLKILO1 (such as clock signals CLK_0, CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, and CLK_315), and may be configured to generate a first control signal (CTRL1) based on one or more relationships between the first clock signals CLKILO1. The CTRL1 signal is provided to the control input of the first voltage regulator <NUM>, which in turn may generate VREF1 based at least in part on the CTRL1 signal.

The first voltage regulator <NUM> may provide VREF1 to control terminals of the first ILO <NUM> and the optional buffer <NUM>, for example, to control, adjust, or modify one or more operating characteristics of the first ILO <NUM> and the optional buffer <NUM>. In some implementations, the first QLL <NUM> may control or adjust the value of the CTRL1 signal based on the relative phases of the first clock signals CLKILO1. The first voltage regulator <NUM> may adjust the value of VREF1 based at least in part on the CTRL1 signal, thereby allowing the first QLL <NUM> to control various operations of the first ILO <NUM>.

The phase interpolator <NUM> may be implemented using complementary metal oxide silicon (CMOS) technology, current mode logic (CML), or any other feasible technology. In some implementations, the phase interpolator <NUM> may be an example of the first phase interpolator <NUM> or the second phase interpolator <NUM> of <FIG>. Thus, although not shown for simplicity, each of the number N of first clock signals CLKILO1 may be provided to corresponding inputs of the phase interpolator <NUM>, and the phase interpolator <NUM> may generate the second reference clock signal CLKREF2 based on relationships between the number N of first clock signals CLKILO1.

The first select circuit <NUM> is configured to select two (or a pair) of the first clock signals CLKILO1 to provide as I/Q TX output clock signals <NUM>. In some implementations, the first select circuit <NUM> may select any suitable pair of the first clock signals CLKILO1 to provide as the I/Q TX output clock signals <NUM>. A transmit circuit, such as the transmit data processing block <NUM> of <FIG>, may use the I/Q TX output clock signals <NUM> to encode or modulate data for transmission.

The second ILO <NUM>, which includes first inputs to receive the second reference clock signal CLKREF2 from the phase interpolator <NUM>, a second input to receive a second reference voltage VREF2 generated by the second voltage regulator <NUM>, and an output coupled to an optional buffer <NUM> (as indicated by the dashed lines), may be any suitable ILO that can generate a plurality of clock signals having the same frequency as the second reference clock signal CLKREF2 yet offset in phase relative to each other.

In some implementations, the second clock signals CLKILO2 may also be equally spaced or offset in phase from one each other, for example, such that each of the second clock signals CLKILO2 has a unique phase that is an integer multiple of a reference phase offset. For example, in some implementations, the second ILO <NUM> may generate N = <NUM> second clock signals CLKILO2 that are offset in phase from each other by forty-five degrees, where a first clock signal CLK_0 has no phase offset, a second clock signal CLK_45 has a phase offset of <NUM> degrees relative to CLK_0, a third clock signal CLK_90 has a phase offset of <NUM> degrees relative to CLK_0, a fourth clock signal CLK_135 has a phase offset of <NUM> degrees relative to CLK_0, a fifth clock signal CLK_180 has a phase offset of <NUM> degrees relative to CLK_0, a sixth clock signal CLK_225 has a phase offset of <NUM> degrees relative to CLK_0, a seventh clock signal CLK_270 has a phase offset of <NUM> degrees relative to CLK_0, and an eighth clock signal CLK_315 has a phase offset of <NUM> degrees relative to CLK_0. In some aspects, the second clock signals CLKILO2 may be provided to the optional buffer <NUM> to generate a plurality of buffered second clock signals CLKILO2'.

The second QLL <NUM> includes a number of inputs coupled to one or more outputs of the second ILO <NUM> (via the optional buffer <NUM>), and includes an output coupled to a control terminal of the second voltage regulator <NUM>. In some implementations, the second QLL <NUM> may receive the number N of second clock signals CLKILO2 (such as clock signals CLK_0, CLK_45, CLK_90, CLK_135, CLK_180, CLK_225, CLK_270, and CLK_315), and may be configured to generate a second control signal (CTRL2) based on one or more relationships between the second clock signals CLKILO2. The CTRL2 signal is provided to the control input of the second voltage regulator <NUM>, which in turn may generate and/or adjust a value of VREF2 based at least in part on the CTRL2 signal.

The second voltage regulator <NUM> may provide VREF2 to control terminals of the phase interpolator <NUM>, the second ILO <NUM>, and the optional buffer <NUM>, for example, to control, adjust, or modify one or more operating characteristics of the phase interpolator <NUM> and the second ILO <NUM>. In some implementations, the second QLL <NUM> may control or adjust the value of the CTRL2 signal based on the relative phases of the second clock signals CLKILO2. The second voltage regulator <NUM> may adjust the value of VREF2 based at least in part on the CTRL2 signal, thereby allowing the second QLL <NUM> to control various operations of the phase interpolator <NUM> and the second ILO <NUM>.

The coarse frequency tracking circuit <NUM>, which may be one implementation of the coarse frequency tracking circuit <NUM> of <FIG>, may be used to control initial start-operations of at least the first ILO <NUM> and the second ILO <NUM>. In some implementations, the coarse frequency tracking circuit <NUM> may generate a control voltage VCTRL and assert the select (SEL) signal in response to detecting a start-up condition, and use the control voltage VCTRL and the SEL signal to temporarily disable the CTRL1 signal via the first switch <NUM> and/or to temporarily disable the CTRL2 signal via the second switch <NUM>. More specifically, upon detecting the start-up condition, the coarse frequency tracking circuit <NUM> may assert the SEL signal to close or turn on switches <NUM>-<NUM>, and may drive VCTRL to a level that disables the CTRL1 signal via switch <NUM> and/or that disables the CTRL1 signal via switch <NUM>. In this manner, the coarse frequency tracking circuit <NUM> may allow the first voltage regulator <NUM> to control oscillation frequencies of the first ILO <NUM>, and may allow the second voltage regulator <NUM> to control oscillation frequencies of the second ILO <NUM> before quadrature lock is established during start-up conditions.

<FIG> shows a block diagram of another example quadrature clock generator <NUM>, according to other implementations. The quadrature clock generator <NUM> is similar in many aspects to the quadrature clock generator <NUM> of <FIG>, except that the phase interpolator <NUM> may be controlled by the first reference voltage VREF1, for example, rather than the second reference voltage VREF2.

<FIG> shows an illustrative flowchart depicting an example operation <NUM> for operating a quadrature clock generator, according to some implementations. The operation <NUM> may be used to operate any suitable quadrature clock generator including, for example, the quadrature clock generator <NUM> of <FIG>, the quadrature clock generator <NUM> of <FIG>, the quadrature clock generator <NUM> of <FIG>, and the quadrature clock generator <NUM> of <FIG>. Thus, although described below with respect to the quadrature clock generator <NUM> of <FIG>, the quadrature clock generator <NUM> of <FIG>, the quadrature clock generator <NUM> of <FIG>, and the quadrature clock generator <NUM> of <FIG>, the example operation <NUM> may be used with other suitable quadrature clock generators.

The operation <NUM> may begin with generating a plurality of first clock signals based at least in part on a first reference clock signal (<NUM>). Referring also to <FIG> and <FIG>, the first ILO <NUM> generates a plurality of first clock signals CLKILO1 based on the first reference clock signal CLKREF1. In some implementations, the first clock signals CLKILO1 may include an integer number of clock signals that may be selected for use as I and Q TX clock signals.

The operation <NUM> may proceed with selecting one of the plurality of first clock signals as a transmit quadrature clock signal (<NUM>). Referring also to <FIG> and <FIG>, the select circuit <NUM> selects any suitable one of the first clock signals CLKILO1 to provide as the I/Q TX output clock signals <NUM>. A transmit circuit, such as the transmit data processing block <NUM> of <FIG>, may use the I/Q TX output clock signals <NUM> to encode or modulate data for transmission.

The operation <NUM> may proceed with generating a second reference clock signal based at least in part on the plurality of first clock signals (<NUM>). Referring also to <FIG> and <FIG>, the phase interpolator <NUM> uses the first clock signals CLKILO1 provided by the first ILO <NUM> to generate a second reference clock signal CLKREF2. In some implementations, the phase interpolator <NUM> may interpolate between a pair of adjacent clock signals of the plurality of first clock signals CLKILO1 to generate the second reference clock signal CLKREF2. for example, so that the second reference clock signal CLKREF2 may have an arbitrary phase relative to the first clock signals CLKILO1.

The operation <NUM> may proceed with generating a plurality of second clock signals based at least in part on the second reference clock signal (<NUM>). Referring also to <FIG> and <FIG>, the second ILO <NUM> generates a plurality of second clock signals CLKILO2 based on the second reference clock signal CLKREF2. In some implementations, the second clock signals CLKILO2 may include an integer number of clock signals that may be selected for use as I and Q RX clock signals.

The operation <NUM> may proceed with selecting one of the plurality of second clock signals as a receive quadrature clock signa (<NUM>). Referring also to <FIG> and <FIG>, the second select circuit <NUM> selects any suitable pair of the second clock signals CLKILO2 to provide as the I/Q RX output clock signals <NUM>. A receive circuit, such as the receive data processing block <NUM> of <FIG>, may use the I/Q RX output clock signals <NUM> to encode or modulate data for transmission.

Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure.

The methods, sequences or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM latch, flash latch, ROM latch, EPROM latch, EEPROM latch, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An example storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.

Claim 1:
A quadrature clock generator (<NUM>), comprising:
a first injection-locked oscillator (<NUM>) configured to generate a plurality of first clock signals (CLKILO1) based at least in part on a first reference clock signal (CLKREF1);
a first select circuit (<NUM>) coupled to the first injection-locked oscillator (<NUM>) and configured to select two of the first clock signals (CLKILO1) as a transmit quadrature clock signal (<NUM>), wherein the transmit quadrature clock signal (<NUM>) is provided to a transmit circuit (<NUM>);
a phase interpolator (<NUM>) coupled to the first injection-locked oscillator (<NUM>) and configured to generate a second reference clock signal (CLKREF2) based on a selected pair of the first clock signals (CLKILO1);
a second injection-locked oscillator (<NUM>) configured to generate a plurality of second clock signals (CLKILO2) based at least in part on the second reference clock signal (CLKREF2); and
a second select circuit (<NUM>) coupled to the second injection-locked oscillator (<NUM>) and configured to select two
of the second clock signals (CLKILO2) as a receive quadrature clock signal (<NUM>), wherein the receive quadrature clock signal (<NUM>) is provided to a receive circuit (<NUM>).