Patent Description:
Conventional initialization electronics and procedures include custom, fixed logic or microprocessors. The custom logic serves only small to medium intellectual property (IP) blocks and use logic developed for that IP block without any unifying methodology to define and implement a flexible initialization procedure. There is no support for different initialization modes such as powering up, entering a low power state, or exiting a low power state.

Larger IPs or system-on-chips (SoCs) use microprocessors or microsequencers. While this approach is very flexible and reusable, microprocessors come at significant area, time, and manufacturing cost.

<CIT> discloses a method of changing operating states of a PHY interface which includes a plurality of blocks. Changing operating states of a PHY interface includes: receiving parameters indicating desired feature settings of the plurality of blocks for changing the operating state of the PHY interface; and enabling the desired feature settings in a sequence, the sequence based on dependencies between the feature settings, the dependencies being stored in a dependency table.

<CIT> discloses a processor having a number of functional units includes a hybrid reset sequence controller that includes a master reset controller configured to hierarchically control a sequence of initialization operations performed on the functional units based upon a value stored within a master control register. The processor includes a number of additional controllers, each configured to control initialization operations for a respective functional unit based upon a value stored within an additional respective control register. The master reset controller controls each of the additional reset controllers dependent on the value stored within the master control register.

<CIT> discloses a system including a finite state machine generator implemented in programmable circuitry of an integrated circuit. The finite state machine generator is parameterizable to implement different finite state machines at runtime of the integrated circuit. The system includes a processor configured to execute program code. The processor is configured to provide first parameterization data to the finite state machine generator at runtime of the integrated circuit. The first parameterization data specifies a first finite state machine and the finite state machine generator implements the first finite state machine in response to receiving the first parameterization data from the processor.

Features and advantages of the disclosure may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. Features of the present invention will become more fully apparent from the following description and appended claims or may be learned by the practice of the disclosure as set forth hereinafter.

In order to describe the manner in which the above-recited and other features of the disclosure can be obtained, a more particular description will be rendered by reference to specific implementations thereof which are illustrated in the appended drawings. For better understanding, the like elements have been designated by like reference numbers throughout the various accompanying figures. While some of the drawings may be schematic or exaggerated representations of concepts, at least some of the drawings may be drawn to scale. Understanding that the drawings depict some example implementations, the implementations will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:.

This disclosure generally relates to devices, systems, and methods for initializing electronic hardware on a circuit board. More specifically, the present disclosure relates to a reusable hardware initialization (INIT) intellectual property (IP) block that initializes hardware on a circuit board. The INIT block includes a finite state machine (FSM) that allows the INIT block to transition between receive and transmit states. The INIT block also includes an input-output (IO) modifier that allows the INIT block to receive input signals from one or more components while in the receive state and to transmit one or more initialization signals to one or more components while in the transmit state.

The FSM of the INIT block can change between a first state or first set of states and a second state or second set of states. For example, the FSM can change between a "high" state and a "low" state. The high state and low state can be associated with a transmit state and receive state, respectively. In other examples, the FSM can increment in an integer counter that progresses through a numbered sequence while also providing an alternating "odd" state and an "even" state for the INIT block. The odd state and even state can be associated with a transmit state and receive state, respectively.

A conventional INIT block receives a reset command and begins a fixed series of hardware initialization procedures. The INIT block begins the process of initializing one or more components on a circuit board by sending an initialization signal to a first component, which in turn send a second signal to another component, and so forth. The process is conventionally determined for a particular device and is set in the silicon or wires of the device to be specific to the components of the electronic device. Therefore, each conventional INIT block architecture is made specifically for that device and is not reusable for other devices. Furthermore, the sequence is a fixed sequence and if, upon running the initialization sequence, any errors occur during the sequence, debugging and testing the sequence and the components is difficult or impossible.

An INIT block according to the present disclosure may increment through a discrete set of receive and transmit states that allow the INIT block to send and receive signals from each component of the device at each point in the initialization procedure. By routing signals through the INIT block, the INIT block becomes a centralized point through which a user or other system can view and debug the sequence.

Further, the discrete cycles of the receive and transmit states allow the INIT block to be scalable. An INIT block according to the present disclosure reads a definition table to correlate a FSM state to a group of potential inputs or outputs for each FSM state, and the definition table can include bypass and qualification conditions that allow the INIT block to adapt to different modes and different devices. An INIT block architecture according to the present disclosure is usable in different devices by changing the definition table only.

<FIG> is a schematic representation of an electronic device <NUM> including a plurality of electronic components. The electronic device <NUM> includes fuses <NUM>, a phase-locked loop (PLL) <NUM>, a generic IP block <NUM>, input-output (IO) block <NUM>, device memory <NUM>, and an INIT block <NUM>.

The fuses <NUM> can communicate default values to the INIT block <NUM> to establish the circuits of the electronic device. The fuses <NUM> are commonly established first in the initialization procedure.

The PLL <NUM> provides macros and clock speeds for the electronic device <NUM>. The PLL <NUM> is a control system that generates an output signal with a phase related to the phase of an input signal. There are different types off PLL with the simplest being an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to keep the phases matched.

Locking the input and output phase also, inherently, keeps the input and output frequencies the same. Therefore, in addition to synchronizing signals, a PLL <NUM> can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. This, in turn, allows the PLL <NUM> of the electronic device <NUM> to set and synchronize the clock speed for the components of the electronic device <NUM>.

The IP block <NUM> can be any IP block <NUM> that is available for a given task. In some embodiments, the IP block <NUM> can be a device related to audio, video display, motion control, input detection, or any other processing requirement of the electronic device. The IP block <NUM> can receive clock information that is provided by the PLL <NUM> either directly or through the INIT block <NUM>. In some embodiments, the IP block <NUM> is in communication with a device memory <NUM>. The device memory <NUM> may be in data communication with the INIT block <NUM>. The INIT block <NUM> can provide an initialization signal to flash the device memory <NUM> and prepare the device memory <NUM> for use. For example, the device memory <NUM> may initially power on in a random state, and the initialization procedure can zero out or otherwise render the memory uniform for use.

In some embodiments, the INIT block <NUM> is in direct data communication, meaning there is a direct communication path without an intervening electronic component, with at least the fuses <NUM>, the PLL <NUM>, and the IP block <NUM>. The INIT block <NUM> can receive an input signal <NUM> from the IO block <NUM> while in a receive state, and the INIT block <NUM> can compare the input signal <NUM> to a definition table to set a mode of the initialization procedure. The INIT block <NUM> then changes a state of the FSM of the INIT block <NUM> and continues the initialization procedure in a transmit state.

In some embodiments, the INIT block <NUM> has a definition table stored thereon. In other embodiments, the INIT block <NUM> is in data communication with a storage device having a definition table stored thereon. The INIT block <NUM> parses the information in the definition table and performs an initialization procedure according to the definition table. In doing so, the architecture of the INIT block <NUM> is reusable, adaptable, and scalable for different applications. By changing the definition table, the functionality of the INIT block <NUM> can be modified without having to change the architecture of the INIT block <NUM> or any other components or wiring on the electronic device <NUM>.

<FIG> is an exemplary embodiment of a definition table <NUM> that is enforced by the INIT block. The definition table <NUM> includes a state type <NUM> and/or a state number <NUM> provided by the FSM of the INIT block. In some examples, the state type <NUM> is based upon the state number <NUM>. The definition table <NUM> illustrated in <FIG> is enforced by an INIT block with an incrementing integer FSM. With each change in FSM state, the FSM counter increments by one integer value. An even number in the state number <NUM> correlates to a "Wait for Input" or receive state type <NUM>. An odd number in the state number <NUM> correlates to an "Assert Output" or transmit state type <NUM>. In other examples, the FSM may toggle between two finite states, such as <NUM> and <NUM> or High and Low, that correlate to the "Wait for Input" or receive state type <NUM> and the "Assert Output" or transmit state type <NUM>.

Incrementing a state number <NUM> allows additional functionality of debugging different points in the initialization procedure, as well as bypass functionality. For example, the inputs or outputs <NUM> column of the definition table <NUM> provides instruction and/or conditions for the INIT block at each state number <NUM> of the FSM.

At state number <NUM>, the INIT block is in a Receive state and is waiting for input to be received by the IO modifier of the INIT block. In some embodiments, a state number <NUM> includes a plurality of inputs commands that the INIT block will recognize at that state number <NUM>. In some examples, the IO modifier can allow the INIT block to receive input commands from a plurality of sources. The received input is recognized as one of a power_up, enter_low_power, or exit_low_power inputs. Each of the inputs indicate that the INIT block is needed to initialize the components of the electronic device into a particular state: in the presented definition table <NUM>, these include either powering up into a high power mode, entering a low power mode, or exiting from the low power mode into the high power mode. The definition table <NUM> further includes mode columns <NUM> that identify mode of the input command and the state numbers <NUM> of the definition table <NUM> associated with that mode column <NUM>.

For example, the power_up input is received by the INIT block during state number <NUM> and the INIT block identifies the power_up input as putting the INIT block in mode0 according to the mode columns <NUM>. After receiving the input command, the FSM of the INIT block changes state and increments by <NUM> integer value to state number <NUM>.

State number <NUM> is an odd value state number <NUM>, so the INIT block enters an "Assert output" or Transmit state type <NUM>. In some embodiments, a state number <NUM> includes a plurality of initialization commands that the INIT block will transmit at that state number <NUM>. For example, the IO modifier can transmit a plurality of initialization commands and/or transmit to a plurality of components of the electronic device. When the INIT block is in mode0 after receiving the power_up input, the mode columns <NUM> of the definition table <NUM> identify two outputs in the state number <NUM>. In mode0, both the load_slot0_start, block0_bist_state and the mem_erase outputs are asserted. In mode2 (associated with exiting a low power state and entering a high power state), only the mem_erase output is asserted. In mode1, (associated with enter a low power state), no outputs are asserted at state number <NUM>.

The FSM then changes state again, by incrementing the state number <NUM> by one integer value again, and the INIT block enters state number <NUM>. The even state number <NUM> results in the INIT block entering a Receive state type <NUM> and waiting for an input command when the INIT block is in mode0.

When the INIT block, through the IO modifier, receives the lsm_block0_pass and block0_bist_done input commands (indicating a self-test has completed), the FSM changes state again, and the INIT block enters state number <NUM>. The INIT block continues through the initialization procedure according to the definition table <NUM> until encountering a state number <NUM> that includes an input bypasser or output qualifier <NUM>. For example, the state number <NUM>, in which the INIT block is in a Transmit state, requires a block1_bist_pass and block0_bist_pass to be true to assert the load_slot1_start command. Otherwise, the state number will increment again without asserting the load_slot1_start command.

Including an input bypasser or output qualifier <NUM> in the definition table <NUM> allows the INIT to perform basic checks and allows for timeout conditions to prevent the initialization procedure from failing, hanging, or initializing a component before other prerequisite components are initialized. Further, because initialization commands and inputs from the initialized components pass through the INIT block, an INIT block according to the present disclosure becomes a centralized component through which all parts of the initialization procedure can be monitored and debugged.

A flexible and customizable INIT block according to the present disclosure can be particularly beneficial in a nest system, such as a system on chip (SOC) <NUM> illustrated in <FIG>. The SOC <NUM> includes an electronic device <NUM>, which may be similar to the electronic device <NUM> described in relation to <FIG>. The SOC <NUM> also includes other devices and/or systems on the SOC <NUM>, such a first subsystem <NUM> and a second subsystem <NUM>. The electronic device <NUM> includes a first set of fuses <NUM>-<NUM>, a first PLL <NUM>-<NUM>, a first IP block <NUM>-<NUM>, an IO block <NUM>, and a first INIT block <NUM>-<NUM> according to the present disclosure. The SOC <NUM>, itself, includes a second set of fuses <NUM>-<NUM>, a second PLL <NUM>-<NUM>, a second IP block <NUM>-<NUM>, system memory <NUM>, and a second INIT block <NUM>-<NUM> according to the present disclosure. The first subsystem <NUM> of the SOC <NUM> includes at least a third IP block <NUM>-<NUM> and a third INIT block <NUM>-<NUM>, and the second subsystem <NUM> of the SOC <NUM> includes at least a fourth IP block <NUM>-<NUM> and a fourth INIT block <NUM>-<NUM>.

The different components and different subsystems of the SOC <NUM> are each in communication with one another. For example, the electronic device <NUM> on the SOC <NUM> is in data communication with second INIT block <NUM>-<NUM> of the SOC <NUM>. The second INIT block <NUM>-<NUM> can be in data communication with the other INIT blocks <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>. Because an INIT block <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> according to the present disclosure is a central hub for initialization procedures, data communication between each of the INIT blocks <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> in a SOC <NUM> or other nested system allows initialization of the entire SOC <NUM> using feedback through the other subsystems and components of the SOC <NUM>. Additionally, the bypasses and qualifiers allow the INIT blocks <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> to initialize or reinitialize only the portion of the SOC <NUM> needed during power up, state changes, or mode changes.

In some embodiments, the INIT block <NUM>-<NUM> of the SOC <NUM> is a central INIT block that is in direct data communication with one or more INIT blocks of subsystems <NUM>, <NUM>. The central INIT block enforces the order and dependencies of the components of the SOC <NUM> and subsystems during the initialization procedure.

<FIG> is a schematic representation of an INIT block <NUM>, according to the present disclosure. In order to change between Transmit and Receive states and to communicate with other components on a chip, an INIT block <NUM> has a FSM <NUM> and an IO modifier <NUM> in the INIT block <NUM>. The INIT block <NUM> can further include memory <NUM> that stores information thereon, including a definition table used to determine input or output logic for the INIT block <NUM>. In some embodiments, the INIT block <NUM> shares a die with one or more of the other electronic components.

The FSM <NUM> is any finite state device that changes between discrete states during operation. For example, a FSM <NUM> can change between any number of finite states. While the example of an FSM <NUM> described in relation to <FIG> is an integer counter with finite states of integers, other FSMs may toggle or cycle between a limited number of states. For example, the integer counter FSM described herein provides both a state number and a state type. In other embodiments, a FSM can also toggle between two finite states to provide the state type. In yet other embodiments, an INIT block <NUM> can have a first FSM that toggles between two states and provide the state type while a second FSM provides state numbers.

The IO modifier <NUM> provides communication between the INIT block <NUM> and other components. The IO modifier <NUM> receives inputs from a plurality of components and can aggregate the inputs into a single signal that can be compared to the state number and/or state type and to the definition table. The IO modifier <NUM> may be in communication with a memory <NUM> that contains the definition table.

The IO modifier <NUM> can parse the definition table and provide input logic and output logic based on the contents of the definition table. The code, therefore, can be changed by simply providing a new definition table for different applications of the INIT block architecture.

For example, the sample table below includes a relatively simple instance of a definition table that alternates between an input state and an output state:
<IMG>.

Based on the above table, the INIT block can parse the definition table to identify what input to wait for and what output to assert in each of the state numbers. The table also provides the mode and the switch type (pulse or level switch) of the associated signal.

An INIT block can parse the provided generic table and automatically generate the following sample code:
//auto generate output LEVEL logic for output state# <NUM>
logic sig_030;
logic set_sig_030;
logic reset_sig_030;
always @ (posedge hsp_clk or negedge reset_na)
if ( ~reset_na )
sig_030 <= <NUM>;
else if ( set_sig_030 )
sig_030 <= <NUM>;
else if ( reset_sig_030 )
sig_030 <= <NUM>;
assign set_sig_030 = (count_next == 'd3 & (qualifer_030 )) & (mode0
);
assign reset_sig_030 = (count =='d0) & (mode0 );
//auto generate input logic for input state# <NUM>
logic input_4;
assign input_4 = (sig_040) | mode1 ;
//auto generate output LEVEL logic for output state# <NUM>
logic sig_050;
logic set_sig_050;
logic reset_sig_050;
always @ (posedge hsp_clk or negedge reset na)
if ( ~reset_na )
sig_050 <= <NUM>;
else if ( set_sig_050 )
sig_050 <= <NUM>;
else if ( reset_sig_050 )
sig_050 <= <NUM>;
assign set_sig_050 = (count_next == 'd5 ) & (mode0 );
assign reset_sig_050 = (count =='d0) & (mode0 );
//auto generate input logic for input state# <NUM>
logic input_6;
assign input_6 = (sig_060) | mode0 ;
//auto generate output LEVEL logic for output state# <NUM>
logic sig_070;
logic set_sig_070;
logic reset_sig_070;
always @ (posedge hsp_clk or negedge reset na)
if ( ~reset_na )
sig_070 <= <NUM>;
else if ( set_sig_070 )
sig_070 <= <NUM>;
else if ( reset_sig_070 )
sig_070 <= <NUM>;
assign set_sig_070 = (count_next == 'd7 ) & (| mode1 );
assign reset_sig_070 = (count == 'd0) & ( | mode1 );
//auto generate input logic for input state# <NUM>
logic input_8;
logic sig_080_lev;
always @ (posedge hsp_clk or negedge reset na)
if ( ~reset_na )
sig_080_lev <= <NUM>;
else if ( sig_080 )
sig_080_lev <= <NUM>;
else if ( count_next == 'd0 )
sig_080_lev <= <NUM>;
assign input_8 = (sig_080_lev) | mode0 ;
//auto generate output PULSE logic for output state# <NUM>
logic sig_090;
logic set_sig_090;
logic reset_sig_090;
always @ (posedge hsp_clk or negedge reset_na)
if ( ~reset_na )
sig_090 <= <NUM>;
else if ( set_sig_090 )
sig_090 <= <NUM>;
else if ( reset_sig_090 )
sig_090 <= <NUM>;
assign set_sig_090 = (count_next == 'd9 ) & (| mode1 );
assign reset_sig_090 = (count == 'd9 ) & (| mode1 );.

The expression of this automatically generated code allows the INIT block <NUM> architecture described herein to be customized and scaled to different electronic devices, systems, subsystems, and chips by changing the definition table only. This reduces the risk of errors converting engineering intent to implementation. Further, the INIT block becomes adaptive based on the signals received from different components at different points in the initialization procedure.

Over a sideband test interface, all inputs and outputs to the INIT block <NUM> are observable. Inputs into the INIT block <NUM> can step through states or jump states to aid in debugging or repeating state numbers. For example, a component in data communication with the INIT block <NUM> may fail a BIST. An input command provided to the INIT block <NUM> in response to the failed BIST can set the state number to rerun a portion of the initialization procedure. This can attempt to reinitialize the component that failed a self test and correct the initialization procedure of that component without either rerunning the entire initialization procedure.

Furthermore, changes to other components or changes to the operational state of other components does not necessitate a change in the INIT block, and visa versa. The interfaces for the IP blocks and other components can remain the same while the INIT block can adapt to the interfaces of the other components.

<FIG> is a schematic representation of an INIT block <NUM> in direct communication with each of the components of a system. The system has fuses <NUM>, a PLL <NUM>, a first IP block <NUM>-<NUM>, and a second IP block <NUM>-<NUM>. The INIT block <NUM> can receive an input signal <NUM> that begins an initialization procedure. In some embodiments, the input signal <NUM> is received from another location on the chip, such as with a subsystem of a SOC. In other embodiments, the input signal <NUM> is received from an external source not on the chip, such as another electronic device including a communication device for remote startups, power supplies, another circuit board, or other external sources.

The INIT block <NUM> can send a first output signal <NUM>-<NUM> to a first component, such as the fuses <NUM>, to request information about the first component. The first component sends a first return signal <NUM>-<NUM> to the INIT block <NUM>, which receives the first return signal <NUM>-<NUM> with the IO modifier <NUM>. The INIT block <NUM> compares the first return signal <NUM>-<NUM> to code automatically generated from the definition table.

When the first return signal <NUM>-<NUM> is recognized, the INIT block <NUM> can send the second output signal <NUM>-<NUM> to the second component in the initialization procedure. In an example, the second component is the PLL <NUM> and the second output signal <NUM>-<NUM> can instruct the PLL to lock the clock speed. The PLL <NUM> can provide a second return signal <NUM>-<NUM> to the INIT block <NUM> that confirms or communicates the clock speed of the PLL <NUM>. Each time an output signal is asserted, or a return signal is recognized, the FSM <NUM> changes state, and INIT block <NUM> moves down the definition table.

Now that the clock speed is locked with the PLL <NUM>, the INIT block <NUM> can initialize the first IP block <NUM>-<NUM> with a third output signal <NUM>-<NUM>. After the first IP block <NUM>-<NUM> has received the third output signal <NUM>-<NUM> and initialized, a third return signal <NUM>-<NUM> informs the INIT block <NUM> that the first IP block <NUM>-<NUM> is initialized and, for example, has passed a self test.

The INIT block <NUM> can then initialize the second IP block <NUM>-<NUM> with a fourth output signal <NUM>-<NUM>. After the second IP block <NUM>-<NUM> has received the fourth output signal <NUM>-<NUM> and initialized, a fourth return signal <NUM>-<NUM> informs the INIT block <NUM> that the second IP block <NUM>-<NUM> is initialized and, for example, has passed a self test.

In another example, the INIT block <NUM> can assert the third output signal <NUM>-<NUM> to the first IP block <NUM>-<NUM> and the fourth output signal <NUM>-<NUM> to the second IP block <NUM>-<NUM> at the same time. Based upon the state of the FSM <NUM> and the definition table, the INIT block <NUM> can recognize the second return signal <NUM>-<NUM> from the PLL <NUM> and initialize the first IP block <NUM>-<NUM> and the second IP block <NUM>-<NUM> at the same time if there is no dependency on the order of the IP blocks <NUM>-<NUM>, <NUM>-<NUM> initializing. In some modes, however, only one of the IP blocks may need to be initialized or the IP blocks may need to be initialized in a particular order. By setting a mode of the initialization procedure as described in relation to <FIG>, the INIT block <NUM> can adapt to different modes and system needs.

<FIG> is a flowchart that illustrates an embodiment of a general method <NUM> of initializing hardware components using an INIT block according to the present disclosure. The method <NUM> includes receiving an input signal at an initialization block at <NUM>. The input signal may originate from a local source on the chip, or a remote source that communicates with the chip, for example through an IO block or directly with the INIT block. In at least one case, the input signal is a power_up signal from a power supply.

After receiving the input signal, the method <NUM> includes changing the state of a FSM of the initialization block at <NUM>. In some embodiments, changing the state of the FSM includes toggling the state from a first state to a second state. Changing the state of the FSM includes incrementing a counter of the FSM. In yet other embodiments, changing the state of the FSM includes incrementing a counter and toggling between a first state and a second state. For example, the FSM can increment an integer counter, while the incremented integer is a member of either an odd set or an even set of integers. In other examples, the FSM can include two FSMs, providing independent control of toggling between a first state and a second state and an incrementing counter.

The method <NUM> can optionally include determining a mode based on the input signal at <NUM>. The input signal, as described herein, can originate from a variety of sources. In some embodiments, a mode is determined based on the source of the input signal. For example, a power_up input signal and that is associated with a mode0 of the initialization procedure may originate from a different source than a enter_low_power input signal. In other embodiments, a mode is determined by the data included in the input signal. For example, an enter_low_power input signal may include data to set a particular value to high while an exit_low_power input signal may include data to set that same value to low. In other embodiments, a mode is determined by a voltage of the input signal. For example, the input signal may be a simple voltage applied to an IO block or to the INIT block, and different voltages may correlate to a mode0, mode1, mode2, etc. of the initialization procedure.

After receiving the input signal to begin the initialization procedure, the initialization procedure is executed according to a series of communication loops. The communication loop includes sending an initialization signal from the initialization block to a component on a chip at <NUM>. After sending the initialization signal, the method <NUM> further includes changing the state of the FSM again at <NUM>. As described herein, changing the state of the FSM includes incrementing a counter, and, optionally, toggling a state.

The initialization signal send to the component will initialize the component and prompt a return signal from the component to the INIT block. The method <NUM> further includes receiving the return signal from the component at the INIT block <NUM> and then changing the state of the FSM at <NUM>. The method <NUM> can repeat the sending portion at <NUM> and receiving portion at <NUM> of the method <NUM> (and associated FSM state changes at <NUM> and <NUM>) to communicate with additional components to initialize the entire chip and/or device.

<FIG> is a flowchart illustrating another embodiment of a method <NUM> of initializing hardware according to the present disclosure. The method <NUM> includes receiving an input signal at an initialization block at <NUM>. The input signal may originate from a local source on the chip, or a remote source that communicates with the chip, for example through an IO block or directly with the INIT block. In at least one case, the input signal is a power_up signal from a power supply.

After receiving the input signal, the method <NUM> includes changing the state of a FSM of the initialization block at <NUM>. In some embodiments, changing the state of the FSM includes toggling the state from a first state to a second state. Changing the state of the FSM includes incrementing a counter of the FSM. In yet other embodiments, changing the state of the FSM includes incrementing a counter and toggling between a first state and a second state. The method <NUM> can optionally include determining a mode based on the input signal at <NUM>.

A method <NUM> according to the present disclosure includes comparing the input signal to at least one input bypass and output qualifier of a definition table at <NUM>. If the input signal does not correspond to an input bypass or output qualifier of the definition table, the method <NUM> continues by sending an initialization signal from the initialization block to a component on a chip at <NUM>. After sending the initialization signal, the method <NUM> further includes changing the state of the FSM again at <NUM>. As described herein, changing the state of the FSM includes incrementing a counter, and, optionally, toggling a state.

The initialization signal sent to the component will initialize the component and prompt a return signal from the component to the INIT block. The method <NUM> further includes receiving the return signal from the component at the INIT block <NUM> and then changing the state of the FSM at <NUM>. The method <NUM> can repeat the sending portion at <NUM> and receiving portion at <NUM> of the method <NUM> (and associated FSM state changes at <NUM> and <NUM>) to communicate with additional components to initialize the entire chip and/or device.

When the input signal corresponds to an input bypass or does not correspond to an output qualifier of the definition table, the method <NUM> continues by bypassing a wait or an output and changing the state of the FSM at <NUM>. For example, when the FSM is in a Receive state, the INIT block waits for a signal before continuing the procedure. However, if the input signal and/or return signal corresponds to an input bypass, the INIT block will bypass the wait for the signal and continue the initialization procedure. In other examples, when the INIT block is in a Transmit state, the INIT block will assert an output when the input signal and/or return signal corresponds to the output qualifier.

The method <NUM> includes iterating through comparing an input signal and/or a return signal to the definition table until the initialization procedure is complete. By iterating through, the initialization procedure can initialize all of the needed components of the electronic device or chip by communicating through the INIT block. As described herein, by maintaining the initialization procedure communications routed through the INIT block, the procedure can be more easily scalable, reusable, viewable, and debuggable, providing a more robust and reliable system.

The articles "a," "an," and "the" are intended to mean that there are one or more of the elements in the preceding descriptions. Additionally, it should be understood that references to "one implementation" or "an implementation" of the present disclosure are not intended to be interpreted as excluding the existence of additional implementations that also incorporate the recited features. For example, any element described in relation to an implementation herein may be combinable with any element of any other implementation described herein. Numbers, percentages, ratios, or other values stated herein are intended to include that value, and also other values that are "about" or "approximately" the stated value, as would be appreciated by one of ordinary skill in the art encompassed by implementations of the present disclosure. A stated value should therefore be interpreted broadly enough to encompass values that are at least close enough to the stated value to perform a desired function or achieve a desired result. The stated values include at least the variation to be expected in a suitable manufacturing or production process, and may include values that are within <NUM>%, within <NUM>%, within <NUM>%, or within <NUM>% of a stated value.

Claim 1:
A method for initializing components of an electronic device (<NUM>), the method comprising:
receiving an input signal (<NUM>) at an initialization block (<NUM>);
after receiving the input signal, changing a state of a finite state machine, FSM, (<NUM>) of the initialization block;
sending an initialization signal from the initialization block (<NUM>) to a component on a chip;
after sending the initialization signal, changing the state of the FSM;
receiving a return signal from the component with the initialization block (<NUM>); and
after receiving the return signal, changing the state of the FSM;
wherein changing the state of the FSM includes incrementing a state number (<NUM>);
the method further comprising comparing the state number (<NUM>) of the FSM to a definition table (<NUM>) stored in a memory (<NUM>) of the initialization block (<NUM>), wherein the initialization block (<NUM>) parses the information in the definition table and performs an initialization procedure according to the definition table (<NUM>).