Patent Description:
A storage device may be a memory system, and may store data based on a request from a host, such as a mobile terminal such as, for example, a computer, a smartphone, a tablet, or various other types of electronic devices. The storage device may include, for example, a hard disk drive, a solid state drive, a universal flash storage (UFS) device, an embedded multimedia card (eMMC), etc..

<CIT> discloses techniques for processing metadata (MD) that may include: determining, in accordance with one or more criteria, a plurality of MD blocks that are similar and expected to have matching corresponding portions of MD in at least some of the plurality of MD blocks; forming a MD superblock including the plurality of MD blocks; filtering the MD superblock and generating a filtered MD superblock, wherein said filtering includes rearranging content of the MD superblock so that a first plurality of MD portions that are similar are grouped together in the filtered MD superblock, wherein at least some of the first plurality of MD portions that are similar are expected to match; and compressing the filtered MD superblock and generating a compressed filtered MD superblock. Filtering may include performing a bitshuffle algorithm that includes performing a bitwise transpose of a matrix of the MD blocks in the MD superblock.

<CIT> discloses a system, an apparatus, and method for dynamic allocation of sub-blocks. First, a non-volatile memory array receives a set of write commands. The non-volatile memory array comprises multiple memory dies organized into metablocks. The metablocks are configured to span two or more memory dies. A stream manager determines a workload type for the set of write commands. A block allocation manager selects a target storage block to receive the set of write commands based on the workload type. The selected target storage block is configured to receive data blocks for the workload type and the block allocation manager directs the set of write commands to the target storage block.

<CIT> discloses apparatus and methods, including enabling communication between a memory controller and multiple memory devices of a storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells, and compressing data using at least one of the device controllers prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system.

<CIT> discloses an embodiment as follows: when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

The dependent claims define preferred embodiments.

Embodiments of the inventive concept provide a storage device which supports a compression function that efficiently uses a small memory space for converting a logical address into a physical address to write or read data received from a host, and a data processing system including the storage device.

According to an embodiment of the inventive concept, a storage device includes a memory device including a plurality of memory blocks, and a memory controller. The memory controller is configured to control a memory operation performed on the memory device by dividing the plurality of memory blocks into a plurality of superblocks, write a first compressed chunk generated by compressing a first chunk including data requested by a host to be written to a first superblock selected based on a first logical address received from the host among the plurality of superblocks, and generate a location-related offset of the first compressed chunk in the first superblock.

According to an embodiment of the inventive concept, a data processing system includes a storage device including a plurality of memory blocks and configured to perform a memory operation by dividing the plurality of memory blocks into a plurality of superblocks, and a host processor. The host processor is configured to operate the storage device in a zoned namespace, recognize the storage device as a plurality of zones, each including a plurality of chunks, and provide a memory operation request to the storage device. The storage device is further configured to write a plurality of compressed chunks generated by compressing the plurality of chunks to the plurality of superblocks respectively corresponding to the plurality of zones, and manage location-related offsets of the plurality of compressed chunks in the plurality of superblocks.

According to an embodiment of the inventive concept, a storage device includes a memory device including a plurality of memory blocks, and a memory controller. The memory controller is configured to control a memory operation performed on the memory device by dividing the plurality of memory blocks into a plurality of superblocks, write a first compressed chunk generated by compressing a first chunk including first data requested by a host to be written to a first superblock selected based on a first logical address received from the host among the plurality of superblocks, and transmit first information indicating a current first available capacity of the first superblock to the host.

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:.

Embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

It will be understood that the terms "first," "second," "third," etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a "first" element in an embodiment may be described as a "second" element in another embodiment.

It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly indicates otherwise.

It will be understood that when a component such as a film, a region, a layer, etc., is referred to as being "on", "connected to", "coupled to", or "adjacent to" another component, it can be directly on, connected, coupled, or adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or one or more intervening components may also be present. It will also be understood that when a component is referred to as "covering" another component, it can be the only component covering the other component, or one or more intervening components may also be covering the other component. Other words used to describe the relationships between components should be interpreted in a like fashion.

<FIG> is a block diagram illustrating a data processing system <NUM> according to an embodiment of the inventive concept. <FIG> and <FIG> are diagrams illustrating a logical area and a physical area related to a memory operation of a storage device <NUM> according to an embodiment of the inventive concept.

Referring to <FIG>, the data processing system <NUM> may include a host <NUM> and the storage device <NUM>. The host <NUM> is a data processing device and may be any one of, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), etc. In the present specification, the host <NUM> may also be referred to as a host processor or a host device. The host <NUM> may communicate with the storage device <NUM> to write data generated while performing a data processing operation to the storage device <NUM> or to read data utilized for a processing operation from the storage device <NUM>. The host <NUM> may communicate with the storage device <NUM> by using at least one of various communication methods such as, for example, universal serial bus (USB), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), high speed interchip (HSIC), peripheral component interconnection (PCI), PCI express (PCIe), or non-volatile memory express (NVMe) communication methods. However, embodiments of the inventive concept are not limited thereto.

The storage device <NUM> may include a memory controller <NUM> and a memory device <NUM>. The memory controller <NUM> may control a memory operation and a background operation performed on the memory device <NUM>. For example, the memory operation may include a write operation (or a program operation), a read operation, and an erase operation. For example, the background operation may include at least one of a garbage collection operation, a wear leveling operation, a bad block management operation, etc..

In an embodiment, the memory device <NUM> may be implemented in various types, such as, for example, NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. Hereinafter, embodiments of the inventive concept are described with respect to an example in which the memory device <NUM> is implemented as NAND flash memory, and specific implementation examples of the NAND flash memory are described below with reference to FIGS. 12A to <NUM>.

In an embodiment, the memory controller <NUM> may include a zone management circuit <NUM> and a compression/decompression circuit <NUM>. Although it is disclosed with reference to <FIG> that the zone management circuit <NUM> and the compression/decompression circuit <NUM> are included in in the memory controller <NUM>, embodiments of the inventive concept are not limited thereto. For example, according to embodiments, the memory controller <NUM> may directly perform the operation of the zone management circuit <NUM> and the compression/decompression circuit <NUM> without inclusion of the zone management circuit <NUM> and the compression/decompression circuit <NUM>. Moreover, the zone management circuit <NUM> and the compression/decompression circuit <NUM> may be implemented as, for example, hardware logic or software logic, and may be executed by the memory controller <NUM>.

The zone management circuit <NUM> may support zoned namespace technology for the host <NUM> to divide and use a plurality of memory blocks BLKs in a zone unit. In the present specification, a namespace refers to the size of a nonvolatile memory that may be formatted as a logical area (or a logical block) at one time. Based on the zoned namespace technology, the storage device <NUM> may sequentially perform a write operation on each of a plurality of zones, in response to a request from the host <NUM>. For example, when the host <NUM> executes a first application program, because data with respect to a first application may be written to a first zone allocated to the first application, properties of the data written to the first zone may be similar. Also, logical addresses of logical pages included in one zone are consecutive, and the zone management circuit <NUM> may sequentially write data to logical pages.

Referring to <FIG>, the logical area may include first to n-th zones Z#<NUM> to Z# (where n is an integer greater than or equal to <NUM>). The host <NUM> may request a memory operation from the storage device <NUM> by recognizing the plurality of memory blocks BLKs of the memory device <NUM> as the first to n-th zones Z#<NUM> to Z#n. Each of the first to n-th zones Z#<NUM> to Z#n may include a plurality of logical pages, and each of the first to n-th zones Z#<NUM> to Z#n may have the same size as one another. Also, an application program executed by the host <NUM> may correspond to at least one zone. First to m-th chunks C#<NUM> to C#m (where m is an integer greater than or equal to <NUM>) may be virtually written to the n-th zone Z#n. The first to m-th chunks C#<NUM> to C#m may have sequential logical addresses based on an index. Accordingly, data may be sequentially written to the first to m-th chunks C#<NUM> to C#m in a direction from a low index to a high index. In the present specification, a virtual write operation is a write operation recognized by the host <NUM>, and the host <NUM> may recognize that data requested to be written to the storage device <NUM> by the host <NUM> is included in a specific chunk of a specific zone. The storage device <NUM> may actually compress the first to m-th chunks C#<NUM> to C#m and respectively write the same to the plurality of memory blocks BLKs. In the present specification, a chunk may be defined as a data set written to a preset number of logical pages or a data unit including a preset number of logical pages. Each of the first to m-th chunks C#<NUM> to C#m may have the same size as one another. The embodiment of the n-th zone Z#n may also be applied to the first to n-1th zones Z#<NUM> to Z#(n-<NUM>).

Referring to <FIG>, the physical area may include first to n-th superblocks SB#<NUM> to SB#n. Each of the first to n-th superblocks SB#<NUM> to SB#n may include a plurality of physical pages, and each of the first to n-th superblocks SB#<NUM> to SB#n may have the same size as one another. The plurality of memory blocks BLKs of the memory device <NUM> may be divided into the first to n-th superblocks SB#<NUM> to SB#n. For example, one superblock may include at least one memory block. The first to n-th superblocks SB#<NUM> to SB#n may respectively correspond to the first to n-th zones Z#<NUM> to Z#n. The zone management circuit <NUM> may manage a zone mapping table TB11 indicating mapping relationships between the first to n-th zones Z#<NUM> to Z#n, which are logical areas, and the first to n-th superblocks SB#<NUM> to SB#n, which are physical areas. For example, similar to the zone mapping table TB11, the n-th zone Z#n may be mapped to the second superblock SB#<NUM>. As the storage device <NUM> performs a memory operation, the n-th zone Z#n may be mapped to a superblock other than the second superblock SB#<NUM>, and the zone management circuit <NUM> may update the zone mapping table TB11 based on a changed mapping relationship. In some embodiments, in the storage device <NUM>, instead of the zone mapping table TB11, fixed mapping relationships between the first to n-th zones Z#<NUM> to Z#n and the first to n-th superblocks SB#<NUM> to SB#n may be defined, and in this case, the zone mapping table TB11 may be omitted.

In an embodiment, the first to m-th compressed chunks CC#<NUM> to CC#m may be written to the second superblock SB#<NUM>. The first to m-th compressed chunks CC#<NUM> to CC#m may have sequential physical addresses with respect to the index. Accordingly, the first to m-th compressed chunks CC#<NUM> to CC#m may be sequentially written from a low index to a high index. The compression/decompression circuit <NUM> may compress the first to m-th chunks C#<NUM> to C#m of the n-th zone Z#n, respectively, generate the first to m-th compressed chunks CC#<NUM> to CC# m, and write the generated first to m-th compressed chunks CC#<NUM> to CC#m to the second superblock SB#<NUM>. In an embodiment, the first to m-th compressed chunks CC#<NUM> to CC#m may be based on at least one of a plurality of compression algorithms. The sizes of the first to m-th compressed chunks CC#<NUM> to CC#m may be the same as or different from each other. For example, the size of the first compressed chunk CC#<NUM> based on a first compression algorithm may be different from that of the second compressed chunk CC#<NUM> based on a second compression algorithm. In another example, the first compressed chunk CC#<NUM> and the second compressed chunk CC#<NUM> based on the same algorithm may have the same size as each other.

In an embodiment, the first compressed chunk CC#<NUM> may include a compression header and compressed data. For example, the compression header may include at least one of a compression algorithm of the first compressed chunk CC#<NUM>, the size of the first compressed chunk CC#<NUM>, and the number of logical pages included in the first chunk (C#<NUM>, <FIG>) corresponding to the first compressed chunk CC#<NUM>. The compressed data may be compressed from the first chunk (C#<NUM>, <FIG>). In an embodiment, the compression/decompression circuit <NUM> may first read the compression header and perform a decompression operation on the compressed data based on the read compression header. The configuration example of the first compressed chunk CC#<NUM> may also be applied to the second to m-th compressed chunks CC#<NUM> to CC#m, and embodiments of the second superblock SB#<NUM> may also be applied to the first and third to n-th superblocks SB#<NUM> and SB#<NUM> to SB#n.

Referring back to <FIG>, in an embodiment, the zone management circuit <NUM> may generate location-related offsets of compressed chunks in superblocks. For example, the zone management circuit <NUM> may update a compressed chunk mapping table based on the location-related offsets of the generated compressed chunks. In another example, the zone management circuit <NUM> may transmit address information including the location-related offsets of the generated compressed chunks to the host <NUM>.

In an embodiment, the compressed chunks are generated by compressing chunks, and, unlike chunks including logical pages, may not be page-aligned and may be in a byte-aligned state. Thus, the location-related offsets of the compressed chunks may correspond to byte-aligned offsets. In an embodiment, the location-related offsets of the compressed chunks may include a start physical address of the compressed chunks in the superblocks respectively including the compressed chunks.

In an embodiment, the zone management circuit <NUM> may transmit information indicating additionally secured available capacities of superblocks to the host <NUM> by writing the compressed chunks to the superblocks. Because the host <NUM> recognizes a superblock, which is a physical area, as a zone, which is a logical area, the host <NUM> may recognize the available capacities of the superblocks as available capacities of the zones. Because the compression/decompression circuit <NUM> does not apply the same compression algorithm to the chunks at once, but selects and applies at least one of a plurality of compression algorithms, the compression algorithms of the compressed chunks may be the same or different. Accordingly, in an embodiment, because the host <NUM> does not predict the available capacities of the superblocks, the zone management circuit <NUM> may provide the same. The host <NUM> may periodically or aperiodically confirm the available capacities of the superblocks through the information, and transmit a write request to the storage device <NUM> based thereon. For example, in an embodiment, the host <NUM> may transmit a write request to the storage device <NUM> to preferentially use an available capacity of a target superblock (which is recognized by the host <NUM> as a target zone) of the current write operation. Through this, the efficiency of a zoned named space method in which data is sequentially written for each zone may be increased or maximized.

The storage device <NUM> according to an embodiment of the inventive concept may quickly access the compressed chunks respectively included in the superblocks by managing the location-related offset for each compressed chunk, and minimize or reduce a memory space utilized for conversion between the logical address and the physical address when accessing the compressed chunks.

In addition, the storage device <NUM> according to an embodiment of the inventive concept may provide the available capacities of superblocks to the host <NUM> so that the host <NUM> may be induce to make a write request, capable of increasing or maximizing the efficiency of the zoned namespace method, to the storage device <NUM>.

<FIG> is a diagram illustrating a series of operations of a data processing system according to an embodiment of the inventive concept. The embodiment described below is merely an example and may be applied in various ways based on various implementations, and the inventive concept is not limited thereto.

Referring to <FIG>, a host may store a 100th file page #<NUM> of a first file File <NUM>, a 21st file page #<NUM> of a fifth file File <NUM>, and a 99th file page #<NUM> of a first file File <NUM> while executing a certain application program and performing a data processing operation. In the present specification, a file page may be data in a page unit used or processed by the host. In the present specification, a page may refer to a memory space in a page unit included in a chunk or a compressed chunk. The host may rearrange the 100th file page #<NUM>, the 21st file page #<NUM>, and the 99th file page #<NUM> by considering a file index order and then considering a file page index order. As a result, the host may transmit the rearranged 99th file page #<NUM>, 100th file page #<NUM>, and 21st file page #<NUM>, a write request, and a logical address to a storage device. The write request in <FIG> may be referred to as a named write request, and may be a different type from that of a write request described below with reference to <FIG>.

In an embodiment, the host may request a read operation performed on the storage device based on a first file mapping table TB21. The first file mapping table TB21 may indicate mapping relationships between indexes of file pages and logical addresses to which a plurality of file pages are written. In the present specification, data written to a specific address may be interpreted as data written to a memory area indicated by the specific address. An entry of a logical address may include a zone index, a chunk index, and a page index. The page index is for identifying pages included in the corresponding chunk. For example, in the first file mapping table TB21, the 21st file page #<NUM> may have a logical address indicating that the 21st file page #<NUM> is written to a third page P#<NUM> of a k-th chunk C#k (where k is an integer greater than or equal to <NUM> or less than m) of the n-th zone Z#n, the 99th file page #<NUM> may have a logical address indicating that the 99th file page #<NUM> is written to a first page P#<NUM> of the k-th chunk C#k of the n-th zone Z#n, and the 100th file page #<NUM> may have a logical address indicating that the 100th file page #<NUM> is written to a second page #<NUM> of the k-th chunk C#k of the n-th zone Z#n.

In an embodiment, in response to a write request from the host, the storage device may sequentially write the 99th file page #<NUM>, the 100th file page #<NUM>, and the 21st file page #<NUM> to the k-th chunk C#k of the n-th zone Z#n corresponding to the logical area. The storage device may compress the k-th chunk C#k to generate a k-th compressed chunk CC#k, and write the k-th compressed chunk CC#k to the second superblock SB#<NUM> mapped to the n-th zone Z#n with reference to the zone mapping table TB11.

In an embodiment, the storage device may generate a k-th offset OS#k related to the location of the k-th compressed chunk CC#k in the second superblock SB#<NUM>, and update a compressed chunk mapping table TB31 based on the k-th offset OS#k. The storage device may use the compressed chunk mapping table TB31 to convert logical addresses into physical addresses. In an embodiment, the compressed chunk mapping table TB31 may indicate mapping relationships between indexes of superblocks, indexes of compressed chunks, and location-related offsets of the compressed chunks. For example, referring to the compressed chunk mapping table TB31, the k-th compressed chunk CC#k of the second superblock SB#<NUM> may be mapped to the k-th offset OS#k. In addition, a k-1th compressed chunk CC#(k-<NUM>) of the second superblock SB#<NUM> written before the k-th compressed chunk CC#k may be mapped a k-1th offset OS#(k-<NUM>).

In an embodiment, the k-1th offset OS#(k-<NUM>) may indicate a start physical address in the second superblock SB#<NUM> of the k-1th compressed chunk CC#(k-<NUM>), and the k-th offset OS#k may indicate a start physical address in the second superblock SB#<NUM> of the k-th compressed chunk CC#k. The storage device may find the k-1th compressed chunk CC#(k-<NUM>) and the k-th compressed chunk CC#k based on a relationship between the k-1th compressed chunk CC#(k-<NUM>) and the k-th compressed chunk CC#k, which are sequentially written in the second superblock SB#<NUM>, and the k-1th offset OS#(k-<NUM>) and the k-th offset OS#k. As described above, the storage device may find other compressed chunks in the second superblock SB#<NUM>, and may further find compressed chunks of other superblocks.

In an embodiment, the storage device may compress a received chunk in response to a write request from the host to generate a compressed chunk, write the compressed chunk to a superblock, and confirm a location-related offset of the compressed chunk to update the compressed chunk mapping table TB31. The storage device may convert a logical address received in response to a read request from the host into a physical address, based on the zone mapping table TB11 and the compressed chunk mapping table TB31. The storage device may perform the read operation using the physical address.

Various embodiments based on <FIG> are described below with reference to <FIG>.

<FIG> is a diagram illustrating an operating method of a data processing system according to an embodiment of the inventive concept. In <FIG>, the data processing system may include a host 30a and a storage device 200a.

Referring to <FIG>, in operation S100, the host 30a may transmit, to the storage device 200a, data including a write request, a logical address, and at least one file page. In an embodiment, the logical address is for designating a location where data is written, and includes a zone index, a chunk index, and a page index. In operation S110, the storage device 200a converts the logical address received from the host 30a into a first physical address. The first physical address includes an index of a superblock and an index of a compressed chunk. In operation S120, the storage device 200a compresses the chunk including data, based on a compression algorithm. In an embodiment, the storage device 200a may select a compression algorithm most suitable for compressing the corresponding chunk from among a plurality of compression algorithms, and may use the selected algorithm to compress the corresponding chunk. In operation S130, the storage device 200a may write the compressed chunk to the superblock, based on the first physical address. In an embodiment, the storage device 200a may sequentially write the corresponding compressed chunk following an area in which a compressed chunk having an index closest to and lower than the index of the corresponding compressed chunk in the superblock indicated by the first physical address is written. Referring back to <FIG>, the storage device 200a may write the k-th compression chunk CC#k next to the k-1th compressed chunk CC#(k-<NUM>) in the designated second superblock SB#<NUM>. In operation S140, the storage device 200a may update a compressed chunk mapping table based on the second physical address indicating the location of the compressed chunk in the superblock. Referring to <FIG>, the storage device 200a may reflect the k-th offset OS#k of the k-th compressed chunk CC#k in the compressed chunk mapping table TB31. In an embodiment, the second physical address may be a start physical address of the compressed chunk in the superblock as a location-related offset of the above-described compressed chunk. In operation S150, the storage device 200a may transmit, to the host 30a, a write operation success notification in response to the write request.

In operation S160, the host 30a may update the first file mapping table based on the logical address and data in operation S100 for a read request of data written to the storage device 200a. However, this is only an embodiment, and the inventive concept is not limited thereto. For example, according to embodiments, the host 30a may update the first file mapping table in advance before performing operation S100.

<FIG> is a flowchart illustrating an operating method of a data processing system according to an embodiment of the inventive concept. In <FIG>, the data processing system may include the host 30a and the storage device 200a. Hereinafter, an embodiment relating to a target zone recognized by the host 30a is mainly described.

Referring to <FIG>, in operation S200, the host 30a may transmit a first write request for the target zone to the storage device 200a. In operation S210, the storage device 200a may perform a first write operation on the target zone. According to the claimed invention, the storage device 200a performs the first write operation on a superblock mapped to the target zone. In operation S220, the storage device 200a may confirm an available capacity of the target zone. According to the claimed invention, the storage device 200a confirms the remaining memory capacity of the superblock after completing the first write operation on the superblock mapped to the target zone as the available capacity. In operation S230, the storage device 200a may transmit information indicating the available capacity of the target zone. For example, the storage device 200a may transmit, to the host 30a, information indicating the available capacity of the superblock mapped to the target zone. In operation S240, the host 30a may generate a second write request for the target zone based on the received information. For example, in an embodiment, the host 30a may generate a second write request for data to be written to the storage device 200a following the data for which the first write request is performed in operation S200 so as to preferentially use the available capacity of the target zone with reference to the information received in operation S230. In some embodiments, when the available capacity of the target zone is insufficient or there is no available capacity of the target zone, the host 30a may generate the second write request so that the corresponding data is written to a next target zone. In operation S250, the host 30a may transmit the second write request for the target zone.

<FIG> is a flowchart illustrating an operating method of a data processing system according to an embodiment of the inventive concept. In <FIG>, the data processing system may include the host 30a and the storage device 200a. Hereinafter, an embodiment in which the storage device 200a performs a read operation in response to a read request from the host 30a is described.

Referring to <FIG>, in operation S300, the host 30a may transmit the read request for requested data and a logical address to the storage device 200a. For example, the host 30a may obtain the logical address of the requested data with reference to the file mapping table TB21 of <FIG>. In an embodiment, the logical address may include a zone index, a chunk index, and page indexes. In the present specification, page indexes are for identifying pages included in a chunk, and may be referred to as indexes of pages. In operation S310, the storage device 200a may convert the logical address received from the host 30a into a physical address by using a zone mapping table and a compressed chunk table. In operation S320, the storage device may read the compressed chunk based on the physical address. For example, the storage device 200a may find a superblock mapped to the zone index of the logical address with reference to the zone mapping table, and find a compressed chunk mapped to the chunk index of the logical address in the corresponding superblock with reference to the compressed chunk mapping table. In operation S330, the storage device 200a may generate a chunk by decompressing the read compressed chunk. In operation S340, the storage device 200a may transmit, to the host 30a, data written to pages respectively corresponding to page indexes of logical addresses in the generated chunk.

<FIG> is a flowchart illustrating an operation of the storage device 200a in operation S320 of <FIG> according to an embodiment of the inventive concept. <FIG> is a table diagram illustrating operation references of the storage device 200a of <FIG> according to an embodiment of the inventive concept. Operations S321 and S322 of <FIG> may be included in operation S320 of <FIG>.

Referring to <FIG>, in operation S321, the storage device 200a may read a compression header of a compressed chunk matching a physical address. For example, in an embodiment, the storage device 200a may preferentially read the compression header to obtain information about a compression algorithm utilized for decompressing the compressed chunk. In operation S322, the storage device 200a may additionally read more pages by the number of pages set in the compressed chunk than the number of pages requested by the host 30a to be read at the time of reading the compression header. In the present specification, an operation in which the storage device 200a additionally reads more pages by the number of pages set in the compressed chunk than the number of pages requested by the host 30a to be read may be referred to as a prefetch operation. The storage device 200a may prefetch data that is expected to be read in order to reduce or minimize a memory access wait time. Because a compression algorithm, a size, etc. may be different for each compressed chunk, the number of pages set for prefetch may be set differently for each compressed chunk.

Referring to <FIG>, a table TB41 may indicate the number of pages set for prefetch for each compressed chunk index. For example, a first number of pages S1 may be set in the first compressed chunk CC#<NUM>, and a second number of pages S2 may be set in the second compressed chunk CC#<NUM>. The storage device 200a may update the table TB41 considering the compression algorithm and size of the compressed chunk.

Referring to <FIG>, a host may store a 100th file page #<NUM> of a first file File <NUM>, a 21st file page #<NUM> of a fifth file File <NUM>, and a 99th file page #<NUM> of a first file File <NUM> while executing a certain application program and performing a data processing operation. The host may rearrange the 100th file page #<NUM>, the 21st file page #<NUM>, and the 99th file page #<NUM> by considering a file index order and then considering a file page index order. The host may transmit the rearranged 99th file page #<NUM>, 100th file page #<NUM>, and 21st file page #<NUM>, a write request, and a logical address to a storage device. The write request in <FIG> may be referred to as a nameless write request or a zone append command. Unlike the logical address of <FIG> including a zone index, a chunk index, and a page index, the logical address of <FIG> may include only a zone index. That is, the host may indicate only a zone in which data including the rearranged 99th file page #<NUM>, 100th file page #<NUM>, and 21st file page #<NUM> is written.

In an embodiment, in response to the write request from the host, the storage device may use the zone mapping table TB12 to find the n-th zone Z#n matching the logical address, randomly select the k-th chunk C#k and pages P#<NUM>, P#<NUM>, and P#<NUM> included in the k-th chunk C#k from among a plurality of chunks of the n-th zone Z#n, and sequentially write the 99th file page #<NUM>, the 100th file page #<NUM>, and the 21st file page #<NUM> to the k-th chunk C#k. The storage device may compress the k-th chunk C#k to generate a k-th compressed chunk CC#k, and write the k-th compressed chunk CC#k to the second superblock SB#<NUM> mapped to the n-th zone Z#n with reference to the zone mapping table TB12.

In an embodiment, the storage device may generate the k-th offset OS#k related to the location of the k-th compressed chunk CC#k in the second superblock SB#<NUM>. The storage device may write the k-th compressed chunk CC#k to the second superblock SB#<NUM>, and then transmit, to the host, address information including the index of the n-th zone Z#n, the k-th offset OS#k, and indexes of the first to third pages P#<NUM>, P#<NUM>, and P#<NUM>. In some embodiments, the storage device may transmit, to the host, the address information including the k-th offset OS#k, and the indexes of the first to third pages P#<NUM>, P#<NUM>, and P#<NUM>, excluding the index of the n-th zone Z#n.

In an embodiment, the host may update the second file mapping table TB22 based on address information received from the storage device. The second file mapping table TB22 may indicate mapping relationships between indexes of file pages and logical addresses to which a plurality of file pages are written. An entry of a logical address may include a zone index, a location-related offset of the compressed chunk, and a page index. On the other hand, because the host has not determined that the compression/decompression operation is performed in the storage device, and the index of the compressed chunk may be the same as the index of the chunk, the host may recognize the location-related offset of the compressed chunk as the location-related offset of the chunk. For example, the host may update the second file mapping table TB22 to indicate that the 21st file page #<NUM> is written to the third page P#<NUM> of a chunk corresponding to a compressed chunk having the k-th offset OS#k of the n-th zone Z#n, the 99th file page #<NUM> is written to the first page P#<NUM> of the chunk corresponding to the compressed chunk having the k-th offset OS#k of the n-th zone Z#n, and the 100th file page #<NUM> is written to the second page #<NUM> of the chunk corresponding to the compressed chunk having the k-th offset OS#k of the n-th zone Z#n, based on the address information. The host may request a read operation with respect to the storage device based on the second file mapping table TB22.

In an embodiment, the storage device may convert the received logical address into a physical address based on the zone mapping table TB12, in response to a read request from the host. The storage device may perform the read operation using the physical address.

In an embodiment according to <FIG>, unlike <FIG>, the host side may manage location-related offsets of compressed chunks by using the second file mapping table TB22. Various embodiments based on <FIG> are described below with reference to <FIG> and <FIG>.

<FIG> is a flowchart illustrating an operating method of a data processing system according to an embodiment of the inventive concept. In <FIG>, the data processing system may include a host 30b and a storage device 200b.

Referring to <FIG>, in operation S400, the host 30b may transmit, to the storage device 200b, data including a write request, a logical address, and at least one file page. In an embodiment, the logical address may designate a location where data is written, and may include a zone index. Moreover, the storage device 200b may designate the remaining locations where data is written, and notify the host 30b of the locations where data is written. In operation S410, the storage device 200b may convert the logical address received from the host 30b into a third physical address by using a zone mapping table. In an embodiment, the third physical address may include a zone index included in the logical address and an index of a mapped superblock. In operation S420, the storage device 200b may compress the chunk including data, based on a compression algorithm. In an embodiment, the storage device 200b may select a compression algorithm most suitable for compressing the corresponding chunk from among a plurality of compression algorithms, and use the selected compression algorithm to compress the corresponding chunk. In operation S430, the storage device 200b may write the compressed chunk to the superblock, based on the third physical address.

In an embodiment, the storage device 200b may determine an index of the compressed chunk, and may determine indexes of pages in which data received in a chunk corresponding to the corresponding compressed chunk is written. The storage device 200b may sequentially write the corresponding compressed chunk following an area in which a compressed chunk having an index closest to and lower than the index of the corresponding compressed chunk in the superblock corresponding to the third physical address is written. In operation S440, the storage device 200b may generate address information including a fourth physical address indicating a location of the corresponding compressed chunk in the superblock. In an embodiment, the fourth physical address may include an offset of the corresponding compressed chunk and indexes of pages of the chunk corresponding to the compressed chunk. In some embodiments, the fourth physical address may further include an index of a zone mapped to the superblock in which the corresponding compressed chunk is written. In operation S450, the storage device 200b may transmit the address information to the host 30b. In operation S460, the host 30b may update a second file mapping table based on the address information. In an embodiment, the host 30b may reflect the address information in the second file mapping table to indicate an area in the storage device 200b to which the data in operation S400 is written.

<FIG> is a flowchart illustrating an operating method of a data processing system according to an embodiment of the inventive concept. In <FIG>, the data processing system may include a host 30b and a storage device 200b. Hereinafter, an embodiment in which the storage device 200b performs a read operation in response to a read request from the host 30b will be described.

Referring to <FIG>, in operation S500, the host 30b may transmit, to the storage device 200b, a read request for requested data and a logical address. For example, the host 30b may obtain the logical address of the requested data with reference to the file mapping table TB22 of <FIG>. In an embodiment, the logical address may include a zone index, an offset of a compressed chunk, and page indexes. The page indexes may indicate pages in which data utilized by the host 30b is written among pages included in a chunk generated by decompressing the corresponding compressed chunk. In operation S510, the storage device 200b may convert the logical address into a physical address by using a zone mapping table. In an embodiment, the storage device 200b may convert a zone index of the corresponding logical address into an index of a superblock mapped thereto with reference to the zone mapping table. In an embodiment, the physical address may include the index of the superblock and the offset of the compressed chunk. In operation S520, the storage device 200b may read the compressed chunk based on the physical address. In operation S530, the storage device 200b may decompress the read compressed chunk. In an embodiment, the storage device 200b may confirm a compression algorithm from a compression header of the compressed chunk, and decompress the compressed chunk based on the confirmed compression algorithm. In operation S540, the storage device 200b may transmit, to the host 30b, the data written to pages corresponding to the page indexes of the logical address in the chunk generated by decompressing the compressed chunk.

<FIG> and <FIG> are diagrams illustrating garbage collection operations of a storage device according to an embodiment of the inventive concept. The garbage collection operation according to an embodiment of <FIG> is described with reference to <FIG>, and the garbage collection operation according to an embodiment of <FIG> is described with reference to <FIG>.

Referring to <FIG>, the storage device may receive valid page information for each chunk (the storage device recognizes valid page information for each compressed chunk) and information about a selected victim zone from a host. For example, the victim zone corresponds to the n-th zone Z#n, and the storage device may perform garbage collection on the second superblock SB#<NUM> corresponding to the n-th zone Z#n, based on the valid page information for each chunk received from the host. For example, the storage device may decompress the k-1th compressed chunk CC#(k-<NUM>) and the k-th compressed chunk CC#k to generate the k-1th chunk C#(k-<NUM>) and the k-th chunk C#k, respectively, and write (or copy) valid pages among pages of the k-1th chunk C#(k-<NUM>) and pages of the k-th chunk C#k to a chunk buffer as a target chunk TC. The storage device may write a target compressed chunk generated by compressing the target chunk TC to the third superblock SB#<NUM> as a third compressed chunk CC#<NUM>. For example, the third superblock SB#<NUM>, to which the target chunk TC is compressed and written, may be determined by the storage device or the host. The storage device may update a compressed chunk mapping table TB33 based on a result of garbage collection. For example, the storage device may reflect a third offset OS#<NUM> of the third compressed chunk CC#<NUM> of the third superblock SB#<NUM> in the compressed chunk mapping table TB33 so as to indicate an area to which the target chunk TC including the valid pages is compressed and written. To notify the host of the result of garbage collection, the storage device may transmit garbage collection result information including a new zone index, a new chunk index, and new page indexes with respect to the target chunk TC to the host. For example, when page A included in the k-th chunk C#k is an x-th file page #x, and is written to a sixth page of the target chunk TC, the host may update a logical address of the x-th file page #x of the first file mapping table TB23 based on the garbage collection result information. For example, the host may update the first file mapping table TB23 to indicate that the x-th file page #x is written to the sixth page P#<NUM> of the third chunk C#<NUM> corresponding to the third compressed chunk CC#<NUM> in the second zone Z#<NUM> mapped to the third superblock SB#<NUM>, based on the garbage collection result information.

Referring to <FIG>, unlike in <FIG>, the storage device does not manage the compressed chunk mapping table, and may transmit the garbage collection result information to the host so that the host may manage offsets of the compressed chunks through a second file mapping table TB23'. In an embodiment, the storage device may transmit, to the host, the garbage collection result information including a new zone index, an offset of a new compressed chunk, and new page indexes with respect to the target chunk to notify the host of the result of the garbage collection. For example, when the page A included in the k-th chunk C#k is the x-th file page #x, and is written to a sixth page of the target chunk TC, the host may update the logical address with respect to the x-th file page #x of the second file mapping table TB23', based on the garbage collection result information. For example, the host may update the first file mapping table TB23' to the second zone Z#<NUM> indicating a location of the storage device to which the x-th file page #x is written, the third offset OS#<NUM> of the third compressed chunk CC#<NUM>, and the sixth page P#<NUM>, based on the garbage collection result information.

<FIG> is a flowchart illustrating a garbage collection operation method of a data processing system according to an embodiment of the inventive concept. In <FIG>, the data processing system may include a host <NUM> and a storage device <NUM>.

Referring to <FIG>, in operation S600, the host <NUM> may transmit valid page information for each compressed chunk to the storage device <NUM>. In operation S610, the storage device <NUM> may read and decompress at least one compressed chunk corresponding to a victim zone. In operation S620, the storage device <NUM> may write valid pages of at least one decompressed chunk to a chunk buffer, based on the valid page information for each compressed chunk. In operation S630, the storage device <NUM> may compress the valid pages of the chunk buffer. In operation S640, the storage device <NUM> may write the compressed chunk to a superblock corresponding to a target zone. In operation S650, the storage device <NUM> may transmit, to the host <NUM>, garbage collection result information according to operations S610 to S640. In operation S660, the host <NUM> may update a file mapping table based on the garbage collection result information.

<FIG> is a diagram illustrating a memory cell array (MCA) of the memory device <NUM> of <FIG> according to an embodiment of the inventive concept. <FIG> is a diagram illustrating a configuration of a block BLK1 among a plurality of memory blocks BLK1 to BLKz of <FIG> according to an embodiment of the inventive concept.

Referring to <FIG>, the MCA may include the plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz may have a three-dimensional structure (or a vertical structure). For example, each of the memory blocks BLK1 to BLKz may include structures extending in first to third directions. Each of the memory blocks BLK1 to BLKz may include a plurality of cell strings extending in the second direction. The plurality of cell strings may be spaced apart from each other in the first and third directions. The cell strings of one memory block are connected to a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of word lines WL, a single ground selection line or a plurality of ground selection lines GSL, and a common source line. The cell strings of the plurality of memory blocks BLK1 to BLKz may share the plurality of bit lines BL. For example, the plurality of bit lines BL may extend in the second direction and may be shared by the plurality of memory blocks BLK1 to BLKz.

Referring to <FIG>, one memory block BLKn among the plurality of memory blocks BLK1 to BLKz of <FIG> is formed in a vertical direction with respect to a substrate SUB. The common source line CSL is disposed on the substrate SUB, and gate electrodes GE and an insulation layer IL are alternately stacked on the substrate SUB. Also, a charge storage layer CS may be formed between the gate electrode GE and the insulating layer IL.

When the plurality of gate electrodes GE and the insulating layers IL that are alternately stacked are vertically patterned, a V-shaped pillar PL is formed. The pillar PL passes through the gate electrodes GE and the insulating layers IL to be connected to the substrate SUB. An outer portion O of the pillar PL may include a semiconductor material and function as a channel, and an inner portion I of the pillar PL may include an insulating material, such as, for example, silicon oxide.

The gate electrodes GE of the memory block BLKn may be respectively connected to the ground selection line GSL, a plurality of word lines WL1 to WL6, and the string selection line SSL. In addition, the pillar PL of the memory block BLKn may be connected to the plurality of bit lines BL1 to BL3.

It is to be understood that the memory block BLKn illustrated in <FIG> is merely an embodiment provided as an example, and the inventive concept is not limited thereto. For example, embodiments of the inventive concept may be applied to various implementations (including a two-dimensional memory structure) of the memory block BLKn.

<FIG> is a diagram illustrating a chip-to-chip (C2C) structure applied to a memory device <NUM> according to an embodiment of the inventive concept. The memory device <NUM> is an embodiment of the memory device <NUM> of <FIG>.

Referring to <FIG>, the memory device <NUM> may have the C2C structure. The C2C structure may mean manufacturing an upper chip including a cell area CELL on a first wafer, manufacturing a lower chip including a peripheral circuit area PERI on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by using a bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may be formed of aluminum or tungsten.

Each of the peripheral circuit area PERI and the cell area CELL of the memory device <NUM> may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit area PERI may include a first substrate <NUM>, an interlayer insulating layer <NUM>, a plurality of circuit elements 320a, 320b, and 320c formed on the first substrate <NUM>, first metal layers 330a, 330b, and 330c respectively connected to the plurality of circuit elements 320a, 320b, and 320c, and second metal layers 340a, 340b, and 340c respectively formed on the first metal layers 330a, 330b, and 330c. In an embodiment, the first metal layers 330a, 330b, and 330c may be formed of tungsten having a relatively high resistance, and the second metal layers 340a, 340b, and 340c may be formed of copper having a relatively low resistance.

In the present specification, only the first metal layers 330a, 330b, and 330c and the second metal layers 340a, 340b, and 340c are shown and described, but the inventive concept is not limited thereto. For example, according to embodiments, at least one or more metal layers may be further formed and included with the second metal layers 340a, 340b, and 340c. At least some of the one or more metal layers formed on the second metal layers 340a, 340b, and 340c may be formed of aluminum having a lower resistance than that of copper forming the second metal layers 340a, 340b, and 340c.

The interlayer insulating layer <NUM> may be disposed on the first substrate <NUM> to cover the plurality of circuit elements 320a, 320b, and 320c, the first metal layers 330a, 330b, and 330c, and the second metal layers 340a, 340b, and 340c, and may include an insulating material, such as, for example, silicon oxide, silicon nitride, etc..

Lower bonding metals 371b and 372b may be formed on the second metal layer 340b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 371b and 372b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 471b and 472b of the cell area CELL by using a bonding method. The lower bonding metals 371b and 372b and the upper bonding metals 471b and 472b may be formed of, for example, aluminum, copper, tungsten, etc..

The cell area CELL may provide at least one memory block. The cell area CELL may include a second substrate <NUM> and a common source line <NUM>. On the second substrate <NUM>, a plurality of word lines <NUM> (including word lines <NUM> to <NUM>) may be stacked in a direction (Z-axis direction) substantially perpendicular to an upper surface of the second substrate <NUM>. String selection lines and ground selection lines may be disposed on upper and lower portions of the word lines <NUM>, respectively, and the plurality of word lines <NUM> may be disposed between the string selection lines and the ground selection line.

In the bit line bonding area BLBA, the channel structure CH may extend in the direction substantially perpendicular to the upper surface of the second substrate <NUM> to pass through the word lines <NUM>, the string selection lines, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 450c and the second metal layer 460c. For example, the first metal layer 450c may be a bit line contact, and the second metal layer 460c may be a bit line. In an embodiment, the bit line 460c may extend in a first direction (Y-axis direction) substantially parallel to the upper surface of the second substrate <NUM>.

In an embodiment as shown in <FIG>, an area in which the channel structure CH and the bit line 460c are disposed may be defined as the bit line bonding area BLBA. The bit line 460c may be electrically connected to the circuit elements 320c providing the page buffer <NUM> in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 460c may be connected to the upper bonding metals 471c and 472c in the peripheral circuit area PERI, and the upper bonding metals 471c and 472c may be connected to the lower bonding metals 371c and 372c connected to the circuit elements 320c of the page buffer <NUM>.

In the word line bonding area WLBA, the word lines <NUM> may extend in a second direction (X-axis direction) substantially parallel to the upper surface of the second substrate <NUM>, and may be connected to a plurality of cell contact plugs <NUM> (including cell contact plugs <NUM> to <NUM>). The word lines <NUM> and the cell contact plugs <NUM> may be connected to each other through pads provided by at least some of the word lines <NUM> extending in different lengths in the second direction. The first metal layer 450b and the second metal layer 460b may be sequentially connected to upper portions of the cell contact plugs <NUM> connected to the word lines <NUM>. In the word line bonding area WLBA, the cell contact plugs <NUM> may be connected to the peripheral circuit area PERI through the upper bonding metals 471b and 472b of the cell area CELL and the lower bonding metals 371b and 372b of the peripheral circuit area PERI.

The cell contact plugs <NUM> may be electrically connected to the circuit elements 320b providing the row decoder <NUM> in the peripheral circuit area PERI. In an embodiment, operating voltages of the circuit elements 320b providing the row decoder <NUM> may be different from operating voltages of the circuit elements 320c providing the page buffer <NUM>. For example, the operating voltages of the circuit elements 320c providing the page buffer <NUM> may be greater than the operating voltages of the circuit elements 320b providing the row decoder <NUM>.

A common source line contact plug <NUM> may be disposed in the external pad bonding area PA. The common source line contact plug <NUM> may be formed of, for example, a metal, a metal compound, or a conductive material such as polysilicon, and may be electrically connected to the common source line <NUM>. The first metal layer 450a and the second metal layer 460a may be sequentially stacked on the common source line contact plug <NUM>. For example, an area in which the common source line contact plug <NUM>, the first metal layer 450a, and the second metal layer 460a are disposed may be defined as the external pad bonding area PA.

In an embodiment, input/output pads <NUM> and <NUM> may be disposed in the external pad bonding area PA. A lower insulating layer <NUM> covering a lower surface of the first substrate <NUM> may be formed on a lower portion of the first substrate <NUM>, and first input/output pads <NUM> may be formed on the lower insulating layer <NUM>. The first input/output pad <NUM> may be connected to at least one of the plurality of circuit elements 320a, 320b, and 320c disposed in the peripheral circuit area PERI through the first input/output contact plug <NUM>, and may be separated from the first substrate <NUM> by the lower insulating layer <NUM>. In addition, a side insulating layer may be disposed between the first input/output contact plug <NUM> and the first substrate <NUM> to electrically separate the first input/output contact plug <NUM> from the first substrate <NUM>.

An upper insulating layer <NUM> covering the upper surface of the second substrate <NUM> may be formed on the upper portion of the second substrate <NUM>, and the second input/output pads <NUM> may be disposed on the upper insulating layer <NUM>. The second input/output pad <NUM> may be connected to at least one of the plurality of circuit elements 320a, 320b, and 320c disposed in the peripheral circuit area PERI through the second input/output contact plug <NUM>.

In some embodiments, the second substrate <NUM> and the common source line <NUM> are not disposed in the area where the second input/output contact plug <NUM> is disposed. Also, in some embodiments, the second input/output pad <NUM> does not overlap the word lines <NUM> in the third direction (Z-axis direction). The second input/output contact plug <NUM> may be separated from the second substrate <NUM> in the direction substantially parallel to the upper surface of the second substrate <NUM>, may penetrate the interlayer insulating layer <NUM> of the cell area CELL, and may be connected to the second input/output pad <NUM>.

According to embodiments, the first input/output pad <NUM> and the second input/output pad <NUM> may be selectively formed. For example, the memory device <NUM> may include only the first input/output pad <NUM> disposed on the upper portion of the first substrate <NUM> or may include only the second input/output pad <NUM> disposed on the upper portion of second substrate <NUM>. Alternatively, the memory device <NUM> may include both the first input/output pad <NUM> and the second input/output pad <NUM>.

In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer may exist as a dummy pattern, or the uppermost metal layer may be empty.

In the external pad bonding area PA, the memory device <NUM> may form a lower metal pattern 373a having the same shape as that of the upper metal pattern 472a of the cell area CELL in the uppermost metal layer of the peripheral circuit area PERI in correspondence to the upper metal pattern 472a formed on the uppermost metal layer of the cell area CELL. In some embodiments, the lower metal pattern 373a formed on the uppermost metal layer of the peripheral circuit area PERI is not connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, the memory device <NUM> may form an upper metal pattern having the same shape as that of the lower metal pattern of the peripheral circuit area PERI in the upper metal layer of the cell area CELL in correspondence to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area PERI.

The lower bonding metals 371b and 372b may be formed on the second metal layer 440b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 371b and 372b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 471b and 472b of the cell area CELL by using the bonding method.

In addition, in the bit line bonding area BLBA, the memory device <NUM> may form the upper metal pattern <NUM> having the same shape as that of the metal pattern <NUM> of the peripheral circuit area PERI on the uppermost metal layer of the cell area CELL in correspondence to the lower metal pattern <NUM> formed on the uppermost metal layer of the peripheral circuit area PERI. In some embodiments, a contact is not formed on the upper metal pattern <NUM> formed on the uppermost metal layer of the cell area CELL.

<FIG> is a block diagram illustrating a solid state drive (SSD) system <NUM> according to an embodiment of the inventive concept.

Referring to <FIG>, the SSD system <NUM> may include a host <NUM> and an SSD <NUM>. The SSD <NUM> may exchange a signal SGL with the host <NUM> through a signal connector, and may receive power PWR through a power connector. The SSD <NUM> may include a memory controller <NUM>, an auxiliary power supply <NUM>, and a plurality of memory devices <NUM>, <NUM>, and <NUM>.

In an embodiment, the memory controller <NUM> may be connected to the plurality of memory devices <NUM>, <NUM>, and <NUM> through channels Ch1, Ch2, and Chn, respectively, to perform a zone management operation according to embodiments of the inventive concept. For example, the memory controller <NUM> may divide and compress data received from the host <NUM> in a chunk unit, write compressed chunks to the plurality of memory devices <NUM>, <NUM>, and <NUM>, and generate offsets of the compressed chunks. For example, the memory controller <NUM> may use a compressed chunk mapping table to directly manage the offsets of the compressed chunks. In another example, the memory controller <NUM> may provide the offsets of the compressed chunks to the host <NUM>, and the host <NUM> may directly manage the offsets of the compressed chunks.

In addition, the memory controller <NUM> may periodically or aperiodically notify the host <NUM> of available capacities of superblocks additionally secured by compressing and writing the chunks, thereby inducing an efficient write operation request of the host <NUM>. In an embodiment, the memory controller <NUM> may change an operation method of zone management for each of the memory devices <NUM>, <NUM>, and <NUM>.

<FIG> is a block diagram illustrating a memory card system <NUM> to which a memory system is applied according to embodiments of the inventive concept.

Referring to <FIG>, the memory card system <NUM> may include a host <NUM> and a memory card <NUM>. The host <NUM> may include a host controller <NUM> and a host connector <NUM>. The memory card <NUM> may include a card connector <NUM>, a memory controller <NUM>, and a memory device <NUM>.

The host <NUM> may write data to the memory card <NUM> or read data written to the memory card <NUM>. The host controller <NUM> may transmit a command CMD, a clock signal CLK and data DATA generated from a clock generator disposed in the host <NUM> to the memory card <NUM> through the host connector <NUM>. The memory card <NUM> may provide a zoned namespace interface according to embodiments of the inventive concept to the host <NUM>.

For example, the memory card <NUM> may divide and compress the data DATA received from the host <NUM> in a chunk unit, write compressed chunks to the memory device <NUM>, and generate offsets of the compressed chunks. For example, the memory controller <NUM> may use a compressed chunk mapping table to directly manage the offsets of the compressed chunks. In another example, the memory controller <NUM> may provide the offsets of the compressed chunks to the host <NUM>, and the host <NUM> may directly manage the offsets of the compressed chunks.

Also, the memory card <NUM> may periodically or aperiodically notify the host <NUM> of available capacities of superblocks additionally secured by compressing and writing the chunks, thereby inducing an efficient write operation request of the host <NUM>.

The memory controller <NUM> may store data in the memory device <NUM> in synchronization with a clock signal generated from a clock generator disposed in the memory controller <NUM> in response to a command received through the card connector <NUM>.

The memory card <NUM> may be implemented as, for example, compact flash card (CFC), microdrive, smart media card (SMC), multimedia card (MMC), security digital card (SDC), memory stick, a USB flash memory driver, etc..

As is traditional in the field of the inventive concept, embodiments are described, and illustrated in the drawings, in terms of functional blocks, units and/or modules. Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units and/or modules being implemented by microprocessors or similar, they may be programmed using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. Alternatively, each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions.

In an embodiment of the present inventive concept, a three dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term "monolithic" means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In an embodiment of the present inventive concept, the 3D memory array includes vertical NAND strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may include a charge trap layer. The following patent documents, which are hereby incorporated by reference, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array is configured as a plurality of levels, with word lines and/or bit lines shared between levels: <CIT>; <CIT>; <CIT>; <CIT>; and <CIT>.

Claim 1:
A storage device (<NUM>, <NUM>, 200a, 200b), comprising:
a memory device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprising a plurality of memory blocks (BLKs, BLK1 - BLKz); and
a memory controller (<NUM>, <NUM>, <NUM>) configured to:
control a memory operation performed on the memory device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) by dividing the plurality of memory blocks (BLKs, BLK1 - BLKz) into a plurality of physical superblocks (SB#<NUM> - SB#n) each superblock comprising a plurality a compressed chunks,
receive from a host data requested to be written and a logical address, said logical address including a zone index and a chunk index identifying a first chunk (C#1I) within the zone identified by said zone index,
convert the logical address into a first physical address, said physical address including an index of a superblock mapped to said zone index and an index of a compressed chunk within the corresponding superblock,
compress data requested to be written by the host and write said data to generate a first compressed chunk,
write said first compressed chunk (CC#<NUM>) to a first superblock (SB#<NUM>) among the plurality of superblocks (SB#<NUM> - SB#n) based on the first physical address, and
generate a location-related offset of the first compressed chunk (CC#<NUM>) in the first superblock (SB#<NUM>),
wherein the location-related offset of the first compressed chunk (CC#<NUM>) comprises a start physical address of the first compressed chunk (CC#<NUM>) in the first superblock (SB#<NUM>),
wherein the memory controller (<NUM>, <NUM>, <NUM>) is further configured to transmit, to the host (<NUM>, <NUM>, 30a, 30b), information indicating a currently available capacity of the first superblock (SB#<NUM>), after writing the first compressed chunk (CC#<NUM>) to the first superblock (SB#<NUM>).