Patent Description:
Computing systems such as cloud computing systems or data centers that are used for hosting, storing, or conveying large amounts of data typically include many high-performance computing devices interconnected to one another. A typical computing device includes a printed circuit board, an integrated circuit die mounted on the printed circuit board and a separate optical module mounted on the printed circuit board. An external optical cable is connected to the optical module to connect the integrated circuit die to the rest of the system.

Data is transferred between the integrated circuit die and the optical module using package traces formed on the printed circuit board. State of the art computing systems may have high bandwidth requirements, with communications exceeding <NUM> Gigabit per second (Gbps), <NUM> Gbps, or even <NUM> Gbps, either per lane, or aggregated. The package traces on the printed circuit board connecting the integrated circuit die to the optical module are, however, not optimized for high bandwidth density and low power. As a result, power dissipation poses a significant problem with such types of package-level interconnects (i.e., a large percentage of power in data centers, wireless applications, and other high-performance computing systems are due tc interconnect power).

It is within this context that the embodiments described herein arise. <CIT> describes a photonic integrated circuit package, including a photonic integrated circuit chip, including a lumped active optical element; an elec-trode configured to receive an electrical signal, where at least one characteristics of the lumped active optical element is changed based on the electrical signal re-ceived by the electrode; a ground electrode; and a bond contact electrically coupled to the electrode; and an interposer bonded to at least a portion of the photonic inte-grated circuit chip, the interposer including a conductive trace formed on a surface of the interposer, the conductive trace electrically coupled to a source of the electri-cal signal; a ground trace; and a conductive via bonded with the bond contact of the photonic integrated circuit chip, the conductive via electrically coupled to the conductive trace to provide the electrical signal to the electrode of the photonic in-tegrated circuit chip. <CIT> describes a semiconductor package including a first transceiver disposed on a top surface of a substrate; and a second transceiver disposed on a bottom surface of the substrate. The first and second transceivers optically com-municate with each other through optical signals that permeate the substrate. The article "<NPL>, describes a chip scale <NUM>-channel <NUM> Gb/s optical transmitter and receiver subassemblies based on wet etched silicon interposer. The article "<NPL>, describes use and fabrication of an embedded multi-die interconnect bridge. The invention is defined in independent claim <NUM> and in independent claim <NUM>.

The present embodiments relate to integrated circuits, and more particularly, to a multichip package that includes a main integrated circuit die and an electro-optical tile. The electro-optical tile may include a transceiver and an optical engine, which eliminates the conventional chip-to-module interconnect. Configured in this way, the power consumption can be greatly reduced while supporting high bandwidth interconnect density.

It will be recognized by one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

An illustrative system <NUM> of interconnected electronic devices is shown in <FIG>. The system of interconnected electronic devices may have multiple electronic devices such as device A, device B, device C, device D, and interconnection resources <NUM>. The electronic devices A-D may be any suitable type of electronic device that communicates with other electronic devices. Examples of such electronic devices include basic electronic components and circuits such as analog circuits, digital circuits, optical circuits, mixed-signal circuits, etc. Examples of such electronic devices also include complex electronic systems such as data centers, network routers, cellular base stations, or parts thereof that communicate with each other over wired or wireless networks. Interconnection resources <NUM> may include conductive lines and busses, optical interconnect infrastructure, and/or wired and wireless networks with optional intermediate switching circuitry may be used to send signals from one electronic device to another electronic device or to broadcast information from one electronic device to multiple other electronic devices. For example, a transmitter in device B may transmit serialized data signals at a given transmission rate as a data stream over a serial communication link <NUM> to a receiver in device C. Similarly, device C may use a transmitter to transmit serialized data signals as a data stream over a serial communication link <NUM> to a receiver in device B.

If desired, multiple serial communication links may be used to transmit data. For example, multiple transmitters in a transmitting device may each transmit a portion of the data as serial data streams over multiple serial communication links or "channels" to multiple receivers in a receiving device. Upon reception, receiver circuitry in the receiving device may restore the data by aggregating portions from the different channels received at the multiple receivers. The aggregated data may then be stored by memory circuit on the receiving device or processed and retransmitted to another device.

As integrated circuit fabrication technology scales towards smaller processing nodes, it becomes increasingly challenging to design an entire system on a single integrated circuit die (sometimes referred to as a system-on-chip). Designing analog and digital circuitry to support desired performance levels while minimizing leakage and power consumption can be extremely time consuming and costly.

One alternative to single-die packages is an arrangement in which multiple dies are placed within a single package. Such types of packages that contain multiple interconnected dies may sometimes be referred to as systems-in-package (SiPs), multichip modules (MCM), or multichip packages (MCP). Placing multiple chips (dies) into a single package may allow each die to be implemented using the most appropriate or optimal technology process (e.g., a core logic chip may be implemented using one technology node, whereas a memory chip may be implemented using another technology node) and may help increase the performance of die-to-die interface (e.g., driving signals from one die to another within a single package is substantially easier than driving signals from one package to another, thereby reducing power consumption of associated input-output buffers), may free up input-output pins (e.g., input-output pins associated with die-to-die connections are much smaller than pins associated with package-to-board connections), and may help simplify printed circuit board (PCB) design (i.e., the design of the PCB on which the multi-chip package is mounted during normal system operation).

<FIG> is a diagram of an illustrative multichip package <NUM> that includes multiple integrated circuit (IC) dies including at least a first IC die <NUM>-<NUM> and a second IC die <NUM>-<NUM>. The integrated circuit dies on package <NUM> may be any suitable integrated circuit such as programmable logic devices, application specific standard products (ASSPs), application specific integrated circuits (ASICs), transceiver dies, optical engine dies, memory dies, etc. Examples of programmable logic devices include programmable array logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), just to name a few.

As shown in <FIG> , package <NUM> may include interconnect paths <NUM> (e.g., conductive signal traces formed on a substrate in multichip package <NUM>) that connect die <NUM>-<NUM> to die <NUM>-<NUM>. Configured in this way, dies <NUM>-<NUM> and <NUM>-<NUM> may communicate with one another by sending control and data signals via paths <NUM>. The example of <FIG> in which multichip package <NUM> includes two integrated circuit dies is merely illustrative. In general multichip package <NUM> may include three or more dies, four or more dies, or any desired number of chips stacked laterally with respect to one another or stacked on top of one another.

In accordance with an an example not falling under the literal wording of the appended claims, <FIG> shows how multichip package <NUM> may include a main die <NUM> and an electro-optical tile <NUM>. Main die <NUM> may be any suitable integrated circuit such as application specific integrated circuits (ASICs), programmable logic devices, application specific standard products (ASSPs), or other integrated circuits that include core processing circuitry or processing/logic circuitry configured to carry out a user application/function. Electro-optical tile <NUM> may include a transceiver component <NUM> and an optical engine (OE) component <NUM>. Transceiver component <NUM> may be configured to handle electrical signals (e.g., digital and analog signals), whereas optical component <NUM> may be configured to handle primarily optical signals. As a result, transceiver <NUM> and optical engine <NUM> may be referred to collectively as an "electro-optical" tile.

An external optical cable <NUM> may have a connector <NUM> configured to mate with optical engine component <NUM>, as indicated by connection path <NUM>. Mated in this way, external optical network signals can be fed directly to and from multichip package <NUM>. By forming the optical engine component <NUM> directly on multichip package <NUM>, interconnects between main die <NUM> and component <NUM> can be optimized for low power and high bandwidth density, which can help substantially reduce power consumption in a high-performance computing system while maintaining interconnect speeds of greater than <NUM> Gbps, <NUM> Gbps, <NUM> Gbps, <NUM> Gbps, etc..

<FIG> is cross-sectional side view of an illustrative multiple package <NUM> with main die <NUM>, a transceiver die <NUM>, and optical engine dies <NUM> according to an embodiment. As shown in <FIG> , multichip package <NUM> includes a package substrate <NUM> with a top surface and a bottom surface, main die <NUM> mounted on the top surface of substrate <NUM>, transceiver die <NUM> mounted on the top surface of substrate <NUM>, and optical engine die <NUM> mounted on the top surface of substrate <NUM>. An array of solder balls <NUM> (sometimes referred to collectively as a ball grid array or BGA) is formed at the bottom surface of package substrate <NUM>.

Main die <NUM>, transceiver die <NUM>, and optical engine die <NUM> are mounted on package substrate <NUM> using solder bumps <NUM> (e.g., controlled collapse chip connection (C4) bumps) and microbumps <NUM>. It should be noted that the pitch width of solder bumps <NUM> may be greater than the pitch width of microbumps <NUM>, such that microbumps <NUM> have greater connectivity density than solder bumps <NUM>. The diameter of microbumps <NUM> are also generally smaller than the diameter of C4 bumps <NUM> (e.g., bumps <NUM> may be at least two times smaller, at least four times smaller, etc.). Solder bumps <NUM> are also smaller than BGA solder balls <NUM>.

In order to facilitate communications between two chips on multichip package <NUM>, package <NUM> may include one or more embedded multi-die interconnect bridge (EMIB) components <NUM>. An EMIB is a small silicon die that is embedded in package substrate <NUM> and that offers dedicated ultra-high-density interconnection between dies within package <NUM>. EMIBs generally include wires of minimal length, which help to significantly reduce loading and directly boost performance without consuming large amounts of power.

EMIB solutions may be advantageous over other multichip packaging schemes that use a silicon interposer, which is prone to issues such as warpage and requires a comparatively large number of microbumps and through-silicon vias (TSVs) to be formed on and within the interposer, thereby reducing overall yield and increasing manufacturing complexity and cost. The number of dies that can be integrated using an interposer is also limited to that supported by EMIB technology.

The EMIB technology described above may be used as an interface between two or more integrated circuit dies in package <NUM>. In the example of <FIG> , main die <NUM> may be coupled to and convey signals to and from transceiver die <NUM> using a first EMIB <NUM> that is embedded in package substrate <NUM>. In particular, main die <NUM> and transceiver die <NUM> interface with the first EMIB <NUM> using only microbumps <NUM>, which supplies high density interconnectivity relative to C4 bumps <NUM>. Similarly, transceiver <NUM> may be coupled to and convey signals to and from optical engine die <NUM> using a second EMIB <NUM> that is embedded in package substrate <NUM>. Transceiver die <NUM> and optical engine die <NUM> also interface with the second EMIB <NUM> using only microbumps <NUM>, which supplies high density interconnectivity compared to C4 bumps <NUM>.

The exemplary multichip package stack-up of <FIG> is merely illustrative and does not serve to limit the scope of the present embodiments. If desired, multichip package <NUM> may include more than one transceiver die <NUM> coupled to main die <NUM> via respective EMIB components. One or more additional optical engine dies are mounted on package substrate <NUM> or stacked on top of other dies (e.g., see additional optical engine die <NUM>' stacked on top of transceiver die <NUM>). As an example, multichip package <NUM> may include one main die <NUM> and four transceiver dies <NUM>, two of which are coupled to one optical engine die <NUM> and another two of which are coupled to multiple optical engine dies <NUM>.

<FIG> is a diagram illustrating the interface between the transceiver die and the optical engine die within the multichip package. As shown in <FIG> , transceiver <NUM> may include a physical-layer interface portion (oftentimes abbreviated as "PHY"), which connects the physical medium through which data is conveyed to and from transceiver die <NUM> to an associated protocol processing circuit <NUM>.

The transceiver PHY may include a physical coding sublayer (PCS) and forward error correction (FEC) block <NUM>, a serializer <NUM>, a deserializer <NUM>, a link management circuit <NUM>, and/or other high-speed serial interface circuitry suitable for transmitting and receiving data. Block <NUM> may include, among others, decoders, encoders, data alignment circuitry, and registers such as first-in-first-out (FIFO) storage elements. Serializer <NUM> may be configured to transmit serialized data off of transceiver <NUM>, whereas deserializer <NUM> may be configured to receive serialized data, deserialize the received data, and feed the deserialized data to block <NUM> for further processing. Management block <NUM> may be configured to control the operations of the transceiver PHY to ensure proper connection and data transfer.

Protocol processing circuit <NUM> may serve as a data link layer component that is used to provide address and channel access control mechanisms to support unicast, multicast, or broadcast communications services. Protocol processing circuit <NUM> that is used to support an Ethernet link is sometimes referred to as a media access controller (MAC). In general, protocol processing circuit <NUM> may be used as the interface between the transceiver PHY and the main die to support any type of network communications protocol.

Still referring to <FIG> , optical engine <NUM> may include channel driver <NUM>, optical transmitter and laser component <NUM>, optical receiver <NUM>, and transimpedance amplifier (TIA) and limiting amplifier (LA) component <NUM>. Channel driver <NUM> may be driven directly by the transceiver PHY (e.g., serializer <NUM> may directly drive channel driver <NUM> via EMIB path <NUM>). Channel driver <NUM> may then generate corresponding output signals to component <NUM> so that optical signals can be output from optical engine <NUM> to an optical cable. Optical receiver <NUM> may receive signals from the external optical cable and may feed corresponding signals to component <NUM>. Component may then feed the received signals directly to the transceiver PHY (e.g., deserializer <NUM> may receive signals directly from optical engine <NUM> via EMIB path <NUM>).

Blocks <NUM> and <NUM> are configured to process signals in the digital domain. Blocks <NUM> and <NUM> in the transceiver PHY and blocks <NUM> and <NUM> in the optical engine are configured to process signals in the analog domain. Blocks <NUM> and <NUM> are configured to process signals in the optical domain. Operated in this way, transceiver <NUM> and optical engine <NUM> are configured as an electro-optical tile that converts signals between the digital/electrical domain and the optical domain.

<FIG> is a flow chart of illustrative steps for operating a multichip package of the type shown in <FIG>. At step <NUM>, serializer <NUM> in the transceiver PHY may directly drive channel driver <NUM> in the optical engine. At step <NUM>, channel driver <NUM> may then output corresponding signals to optical transmitter <NUM>. Optical transmitter <NUM> may then output signals via an external optical cable.

At step <NUM>, transimpedance amplifier (TIA) and limiting amplifier (LA) block <NUM> may receive signals from optical receiver <NUM>. At step <NUM>, deserializer <NUM> in the transceiver PHY may directly receive signals from block <NUM> in the optical engine. Deserializer <NUM> may then feed deserialized signals to the main die via blocks <NUM> and <NUM>.

These steps are merely illustrative and are not intended to limit the present embodiments. The existing steps may be modified or omitted; some of the steps may be performed in parallel; additional steps may be added; and the order of certain steps may be reversed or altered. If desired, other ways of using the transceiver to directly drive optical engine within the same package via an EMIB or other embedded high-density interconnect component may be used. The scope of the invention is in any case defined by the appended claims.

In another suitable embodiment (see, e.g., <FIG> ), not falling under the scope of the claims, multichip package <NUM> may include main die <NUM> and another die <NUM> that includes both the transceiver and optical engine circuits. In other words, the transceiver component and the optical engine component are collectively formed on a single auxiliary die <NUM> within package <NUM>.

Claim 1:
An integrated circuit package (<NUM>), comprising:
a processing circuitry die (<NUM>);
an optical engine die (<NUM>) coupled to the processing circuitry die (<NUM>), the optical engine die (<NUM>) comprising optical engine circuits including an optical transmitter and laser component (<NUM>), and an optical receiver (<NUM>);
a transceiver die (<NUM>);
a package substrate (<NUM>) with a top surface on which the processing circuitry die (<NUM>), transceiver die (<NUM>), and optical engine die (<NUM>) are mounted using at least one of solder bumps (<NUM>) and microbumps (<NUM>);
one or more additional optical engine dies mounted on the package substrate or stacked on top of the dies (<NUM>, <NUM>); and
conductive signal traces formed on the package substrate (<NUM>), wherein
the signal traces directly interconnect the processing circuitry die (<NUM>) with the transceiver die (<NUM>), and the signal traces directly connect the transceiver die (<NUM>) with the optical engine die (<NUM>), the signal traces interfacing with the processing circuitry die (<NUM>), transceiver die (<NUM>), and optical engine die (<NUM>) using at least one of the solder bumps (<NUM>) and the microbumps (<NUM>).