Patent Description:
Direct bonding on wafer level, commonly referred to as 'wafer to wafer' bonding, involves the alignment and contacting at room temperature of two semiconductor wafers, usually silicon wafers, followed by an annealing step, during which step chemical bonds are formed between the materials on at least a portion of the contacted wafer surfaces.

Current wafer to wafer bonding practice falls in two main categories:.

For both categories, the challenge is to achieve a very flat, low roughness dielectric bonding layer which is beneficial for obtaining void-free bonds with a high bond strength. Chemical Mechanical Polishing (CMP) is applied to reduce the roughness of the dielectric layers. Surface treatments are applied such as plasma treatment and ultrasonic or other cleaning techniques. Required post-bond annealing temperatures are generally higher than <NUM> in order to reach the desired bond strength. In order to reduce the thermal budget of the bonding process, it is desirable to obtain high strength bonds at lower temperatures. This is particularly important in the field of memory devices.

For the second category, an additional problem is the diffusion of the metal into the dielectric bonding layer. This is the case for example when silicon oxide bonding is applied to bonding of hybrid wafers that comprise copper line patterns, resulting in direct Cu contact to the oxide surface of the mating wafer. During annealing, the Cu may diffuse in the oxide, resulting in leakage or shorting between interconnect nets. In order to avoid this diffusion, a dielectric bonding layer can be applied that forms a barrier against the Cu-diffusion, such as silicon nitride. However, this makes achieving a high bonding force more difficult and increases the interconnect capacitance due to the higher dielectric constant of the Si nitride versus the Si oxide.

The same problems are confronted in the 'die to wafer' bonding processes, wherein a silicon chip is bonded to a carrier wafer by direct bonding. In the latter domain, it has been known to apply Silicon Carbon Nitride (SiCN) as the dielectric bonding layer. Reference is made to <CIT>. Like silicon nitride, SiCN is a good Cu diffusion barrier. However, the cited document fails to describe the bonding process in detail and no information is given on applicable annealing temperatures. <CIT> describes SiCN as a 'bonding aid film' in a direct wafer to wafer bonding process. This process is however open to further improvement in terms of the thermal budget (the post-bonding annealing temperature is <NUM>). Use of SiCN as bonding layer is furthermore known from <CIT> and <CIT>. A CMP step reducing the roughness of the bonding layer is known from <CIT>. A CMP step reducing the roughness of the bonding layer to less than or equal to <NUM> RMS is described in <CIT> and <CIT>.

The invention is related to a method as disclosed in the appended claims. The present invention is related to a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding, wherein the substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. The dielectric layer after CMP has an roughness of less than <NUM> RMS. Then a layer of SiCN with a thickness between <NUM> and <NUM> is deposited onto the thinned dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of <NUM> tenth of a nanometre. The RMS value after CMP is less than <NUM> RMS. Then the substrates are subjected to a pre-bond annealing step. The substrates are then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to <NUM>, preferably between <NUM> and <NUM>. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

The invention is thus related to a method for bonding a first semiconductor substrate to a second semiconductor substrate as defined in the appended claims, wherein both substrates are subjected to the following steps, prior to bonding :.

According to a preferred embodiment, the annealing temperature of the post-bond annealing step is less than or equal to <NUM>, more preferably said temperature is between <NUM> and <NUM>.

According to one embodiment of the method of the invention, the substrates are blanket wafers, wherein the dielectric and SiCN layers are continuous layers.

According to another embodiment, the substrates are hybrid dielectric/metal wafers comprising a patterned surface having areas of dielectric material and areas of metal, and the pre-bond annealing step is followed by :.

According to an embodiment, the temperature during bonding is the same as the post-bond annealing temperature. The pre-bond annealing temperature may be between <NUM> and <NUM>.

In the following description, the materials silicon oxide and silicon carbon nitride are defined as follows. Silicon oxide is defined by the formula SiOx, with x between <NUM> and <NUM>. Silicon carbon nitride, hereafter referred to as SiCN, is defined by the formula SiCyNz with y between <NUM> and <NUM> and z between <NUM> and <NUM>. The term SiCN also includes layers of SiCyNz:H, wherein the 'H' represents hydrogen atoms attached to the SiCN molecules. This may be obtained as a consequence of the precursors used in the deposition method for the SiCN layers.

<FIG> illustrates the process steps of a wafer-to-wafer bonding process according to the invention, for the direct bonding of two blanket wafers, i.e. wafers covered over their entire surface with a dielectric bonding layer. As illustrated in <FIG>, the wafers may be silicon wafers comprising a silicon bulk portion <NUM> and a functional layer <NUM> which may comprise semiconductor devices together with a stack of interconnect layers, said functional layer being best known in the art as a FEOL/BEOL layer (Front-end-of-line/Back-end-of-line). The aim is to produce a bond between two such wafers. As seen in the detail of <FIG>, a microscopic but significant roughness is exhibited by the FEOL/BEOL layer <NUM>, which may be mainly due to a degree of surface topography of the layer.

A thick layer <NUM> of SiOx is then deposited onto the FEOL/BEOL layer <NUM>, see <FIG>, covering the totality of said FEOL/BEOL layer <NUM>. As illustrated in the detail of <FIG>, the SiOx layer thickness is high compared to the roughness of the FEOL/BEOL layer, e.g. at least ten times higher that said roughness (expressed as RMS value or expressed as a step height value when the roughness of the FEOL/BEOL layer <NUM> is mainly defined by the topography). In absolute terms, the SiOx layer <NUM> may have a thickness between <NUM> and <NUM> micron. The SiOx layer is then thinned by a CMP step, thereby reducing the roughness to a lower value less than or equal to <NUM> RMS (<FIG>). Instead of a SiOx layer, other dielectric layers may be used, e.g. a silicon nitride layer. Preferably, the dielectric layer <NUM> is an inorganic dielectric layer. An organic dielectric layer <NUM> is not excluded, but in that case, a curing step of the dielectric layer is required to avoid outgassing of the layer during subsequent process steps.

Then a layer <NUM> of SiCN is deposited onto the thinned SiOx layer (<FIG>). The deposition may take place by Plasma Enhanced Chemical Vapour Deposition (PECVD), resulting in an amorphous SiCN layer <NUM>. The thickness of the SiCN layer at this stage is between <NUM> and <NUM>, preferably between <NUM> and <NUM>. The wafers are then subjected to an pre-bond annealing step.

A CMP step is then performed on the SiCN layer, reducing the roughness of the layer to the order of tenths of a nanometre, such that its is equal to or less than <NUM> RMS (<FIG>). The steps illustrated in <FIG> may be performed as part of a BEOL integration scheme. In that case, the pre-bond anneal temperature is preferably compatible with such an integration scheme, and may be between <NUM> and <NUM>, preferably around <NUM>.

The wafers which have both been prepared in the above-described way, are then aligned and bonded (<FIG>) to form an assembly of the two bonded substrates. Any standard alignment technique known in the art can be used, for example based on a camera image of the wafers to be aligned or based on interferometry. Possibly a number of pre-treatments are performed on the contact surfaces, such as a plasma treatment and/or a cleaning step (e.g. megasonic cleaning). The bonding takes place in a bonding tool as known per se in the art, wherein possibly some of the pre-treatments may be performed as well.

The bond is produced by bringing the two polished SiCN surfaces in contact with each other under appropriate process conditions (see further). The extremely low surface roughness facilitates the formation of chemical bonds between the contact surfaces, thereby improving the bond strength between the wafers.

The bond strength is further improved by a post-bond annealing step performed while the wafers are in contact, at a temperature of less than or equal to <NUM>, preferably between <NUM> and <NUM>. Despite the low anneal temperature, the bond strength between the wafers is excellent.

<FIG> illustrates the method of the invention in the case of the direct bonding of hybrid dielectric/metal wafers. Each of the wafers that are to be bonded comprises metal islands <NUM> on the surface of the FEOL/BEOL layer <NUM>. These islands can represent contact pads or metal lines. The surface of the FEOL/BEOL layer <NUM> again shows a degree of roughness, as illustrated in the detail of <FIG>. In <FIG>, the same steps are performed as described in the case of the blanket wafers : deposition of a thick silicon oxide layer <NUM> and CMP on said layer, thinning the SiOx layer by CMP (to a roughness of less than or equal to <NUM> RMS), and deposition of a SiCN layer <NUM> on the thinned SiOx layer. A pre-bond annealing step is again performed at this point.

This is now followed by the production of openings <NUM> in the stack of SiOx/SiCN layers (<FIG>), said openings being formed above a number of the metal islands <NUM> of the FEOL/BEOL layer <NUM>. The formation of these openings can take place by standard lithography steps known in the art and not described in detail here. The openings are formed by removing the SiOx and SiCN throughout the complete thickness of the SiOx/SiCN stack, thereby exposing the metal <NUM> at the bottom of the openings. Then a layer <NUM> of Cu is deposited in the openings and on top of the wafer. This may be done by any suitable technique known in the art. For example, a barrier layer and a Cu seed layer is deposited (not shown), followed by the electrodeposition of Cu <NUM> inside the openings and on top of the wafer (<FIG>). A CMP step is then performed which removes the Cu from the upper surface of the wafer. The SiCN layer <NUM> acts as a stopping layer for the CMP, as it exhibits a higher resistance to CMP than copper. At the same time, the CMP step reduces the roughness of the SiCN layer to the order of tenths of a nanometre, equal to or less than <NUM> RMS. This results in the wafer as shown in <FIG>, where Cu regions <NUM> are surrounded by smooth SiCN areas <NUM>. Once again, the steps illustrated in <FIG> may be performed as part of a BEOL integration scheme. In that case, the pre-bond anneal temperature is preferably compatible with such an integration scheme, and may be between <NUM> and <NUM>, preferably around <NUM>.

The bonding process is illustrated in <FIG>. Possibly after performing pre-treatments of the type described in relation to <FIG>, corresponding metal areas are aligned and the bond is established by bringing the wafers in contact with each other under appropriate process conditions (see further). Bond formation between Cu areas preferably requires exerting a mechanical pressure that pushes the wafers together.

The bonding is followed by a post-bond anneal, at a temperature less than or equal to <NUM>, preferably between <NUM> and <NUM>, resulting again in excellent bond strength between bonded SiCN areas, despite the lower temperatures. The added advantage of using SiCN in this case is that the SiCN forms a barrier against Cu-diffusion.

The invention includes the method as described above, wherein one of the substrates is a semiconductor die instead of a wafer.

In any of the above-described embodiments, the process parameters during the bonding process, i.e. after pre-bond annealing and before post-bond annealing, may be chosen according to known bonding technology, in terms of temperature and ambient pressure in the bonding tool, as well as the pressure exerted mechanically to push the substrates against each other. Bonding may take place at room temperature or any other suitable temperature, preferably not higher than <NUM>. According to a preferred embodiment, the temperature during bonding is the same or in the same range as the post-bond anneal, so that the post-bond anneal can take place in the same tool without losing time. A preferred range for the temperature during bonding is therefore the same range of <NUM>-<NUM> identified above for the post-bond anneal. The bonding preferably takes place at a low ambient pressure, preferably not lower than 10E-7mBar, more preferably around 10E-6mBar. The mechanical force used to push the substrates together may be up to 90kN, with a preferred range between <NUM>-60kN. However in the case of the bonding between blanket wafers (as illustrated in <FIG>, no metal areas on the surface), the bond may be established without a mechanical force being exerted.

In the following, a number of preferred process parameters are described for performing the method of the invention. The values given hereafter are given purely by way of example and are not limiting the scope of the present invention.

Two wafers having FEOL/BEOL layers <NUM> are to be bonded by the method of the invention. They have a surface topology defined by a step height between <NUM> and <NUM>. The deposition of the SiOx layer <NUM> can take place by PECVD, at <NUM>, under a pressure of <NUM> Torr, using as precursors silane and oxygen-containing gases such as NO, NO<NUM> or O<NUM>.

A preferred value of the SiOx thickness is around <NUM>. The CMP on the SiOx layers includes a timed dielectric CMP step and a regular post CMP clean (megasonic cleaning), followed by treatment in <NUM> brush modules and a vapour dryer, e.g. in an integrated Desica cleaner.

The SiCN deposition takes place by PECVD, at <NUM> and <NUM> Torr. The precursor gases include a mixture of at least two types of gases :.

The pre-bond anneal takes place at <NUM> during <NUM>, in a dissociated ammonia atmosphere containing <NUM>%H<NUM>.

The CMP on the SiCN layer includes a timed dielectric CMP step and a regular post CMP clean (megasonic cleaning), followed by treatment in <NUM> brush modules and a vapour dryer, e.g. in an integrated Desica cleaner, followed by a BTA (benzotriazole) rinse step. The post bonding annealing step is performed at <NUM> during <NUM> in a dissociated ammonia atmosphere comprising <NUM>% H<NUM>.

<FIG> illustrates the bond strength (expressed as the bonding energy in J/cm<NUM>) obtained between SiCN layers produced with the above-described method, and compared to the bond strength obtained with other bonding layers, subjected to the same bonding process, including a post-bond annealing step at <NUM> during 2hours. The layers to which the invention is compared were plasma enhanced silicon oxide (PE ox) and SiN. It is clear that the bond strength between SiCN layers obtained by the method of the invention is superior to the other materials.

<FIG> shows bond strengths obtained between PE-ox layers as a function of the post-bond anneal temperature (each time annealing took place during 2hours). Even at a temperature of <NUM>, the bond strength is lower than the bond strength obtained between SiCN layers annealed at <NUM>, according to the method of the invention.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims.

Claim 1:
A method for bonding a first semiconductor substrate to a second semiconductor substrate, wherein both substrates are subjected to the following steps, prior to bonding :
• deposition of a dielectric layer (<NUM>) on the surface of the substrate,
• subjecting the dielectric layer (<NUM>) to a CMP step to reduce the roughness of said dielectric layer,
• deposition of a silicon carbon nitride layer (<NUM>) on the surface of the dielectric layer,
• subjecting the substrate to a pre-bond annealing step,
• subjecting the SiCN layer (<NUM>) to a CMP step to reduce the roughness of said SiCN layer,
wherein the bonding comprises :
• aligning the substrates,
• bringing the SiCN layers (<NUM>) of both substrates into physical contact, to form an assembly of bonded substrates,
and wherein the method further comprises the step of subjecting the assembly to a post-bond annealing step, and wherein the thickness of the SiCN layer, before subjecting the SiCN layer to a CMP step, is between <NUM> and <NUM>,
characterized in that
• the roughness of the dielectric layer (<NUM>) on both substrates, after the step of subjecting the dielectric layers to CMP, is less than or equal to <NUM>, and
• the roughness of the SiCN layer (<NUM>) on both substrates, after the step of subjecting the SiCN layers to CMP, is less than or equal to <NUM> RMS.