Patent Description:
A typical electronic apparatus, such as a processor within wireless devices, may include various cores operating within different power domains. A core may vary from a collection of transistors or circuits to an execution unit. Increasingly, the cores may enter or exit power-down modes at various times to manage power consumption. The power-down modes vary and may include a power-collapse mode, in which all power is disconnected from the cores. Other power-down modes may include gating the clocks with the cores (e.g., disabling clocking in the cores). Yet other power-down modes may include adjusting the operating voltages and frequencies of the cores. While the entering and exiting of the power-down modes may conserve power, such changes of power-down modes may lead to various drawbacks. One design challenge is to manage the entering or exiting of the power-down modes for multiple cores and mitigate the drawbacks. <CIT> discloses a method and apparatus to control current transitions in a processor.

Various aspects of apparatus and methods will now be presented in the detailed description by way of example, and not by way of limitation, with reference to the accompanying drawings, wherein:.

The detailed description set forth below in connection with the appended drawings is intended as a description of various exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. Acronyms and other descriptive terminology may be used merely for convenience and clarity and are not intended to limit the scope of the invention.

Various apparatus and methods presented throughout this disclosure may be implemented in various forms of hardware. By way of example, any of these apparatus or methods, either alone or in combination, may be implemented as an integrated circuit, or as part of an integrated circuit. The integrated circuit may be an end product, such as a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), programmable logic, or any other suitable integrated circuit. Altematively, the integrated circuit may be integrated with other chips, discrete circuit elements, and/or other components as part of either an intermediate product, such as a motherboard, or an end product. The end product can be any suitable product that includes integrated circuits, including by way of example, a cellular phone, personal digital assistant (PDA), laptop computer, a desktop computer (PC), a computer peripheral device, a multimedia device, a video device, an audio device, a global positioning system (GPS), a wireless sensor, or any other suitable device.

The word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiment" of an apparatus or method does not require that all embodiments of the invention include the described components, structure, features, functionality, processes, advantages, benefits, or modes of operation.

When a "signal" is reference, the term may include the conductor carrying the described signal. The term "connection" may include a signal line. The terms "connected," "coupled," or any variant thereof, mean any connection or coupling, either direct or indirect, between two or more elements, and can encompass the presence of one or more intermediate elements between two elements that are "connected" or "coupled" together. The coupling or connection between the elements can be physical, logical, or a combination thereof. As used herein, two elements can be considered to be "connected" or "coupled" together by the use of one or more wires, cables and/or printed electrical connections, as well as by the use of electromagnetic energy, such as electromagnetic energy having wavelengths in the radio frequency region, the microwave region and the optical (both visible and invisible) region, as several nonlimiting and non-exhaustive examples.

Any reference to an element herein using a designation such as "first," "second," and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Various aspects of an apparatus with circuits for managing the entering or exiting of power-down modes for multiple cores are provided. An example of such apparatus may be a processor for wireless communication application. In some examples, the apparatus may include a power management circuit configured to select the cores for entering or exiting power-down modes based on inrush current information. In some examples, the power management circuit is configured as a token manager receiving requests from the cores for entering or exiting power-down modes and issuing tokens to the selected cores to grant the requests.

As those skilled in the art will readily appreciate, aspects and applications of the disclosure may not be limited to the described exemplary embodiments. For example, the apparatus of present disclosure is not limited to a processor, and the power management circuit is not limited to the token manger. Accordingly, all references to a specific application are intended only to illustrate exemplary aspects of the memory with the understanding that such aspects may have a wide differential of applications.

<FIG> is a block diagram of an exemplary embodiment of a processor <NUM> configured to mange entering or exiting of power-down modes for multiple cores based on inrush current information. The processor <NUM> may be, for example, a processor for wireless communication. In some examples, an exemplary apparatus may include the processor <NUM> or a cell phone incorporating the processor <NUM>. The processor <NUM> may be a stand along processor or integrated in an end product, such as mobile phone, desktop computer, laptop computer, tablet computer, or the like.

The processor <NUM> includes cores <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>). A core may be, for example, a collection of circuits. In some examples, the cores <NUM> may be processor or execution units executing instructions. The processor <NUM> may further include additional function blocks (not shown for clarity) such as a graphic processor unit, a digital signal processors (DSP), a wireless modem, and a wireless local area network or WLAN block interfacing with the cores <NUM>.

Each of the cores <NUM> may include a power-down mode circuit <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, or <NUM>-<NUM> for each of the cores <NUM>). The power-down mode circuits <NUM> may effect the corresponding cores <NUM> to enter or to exit various power-down modes. Thus, the power-down mode circuits <NUM> may cause the corresponding cores <NUM> to power up from a power-down mode, to power down to a power-down mode, or to transition among the various power-down modes.

Examples of the power-down modes may include a power-collapse mode, in which all power is disconnected from the cores. Accordingly, the power-collapse mode may draw no current as all power is disconnected. Other power-down modes may include a clock-gating mode that disables clocking in the cores. Yet other power-down modes may include adjusting the operating voltages and frequencies of the cores. The entering and the exiting of the various power-down modes may take different amount of time. For example, entering and exiting the power-collapse mode may take more cycles than the other power-down modes.

The power-down mode circuits <NUM>, as illustrated, may effect the corresponding core <NUM> to enter into the power-collapse mode or the clock-gating mode (e.g., powering down the core <NUM>). The power-down mode circuit <NUM> may likewise effect the core <NUM> to exit the power-down modes and return to full-power operations (e.g., powering up the core <NUM>). In some examples, the power-down mode circuit <NUM> may effect the corresponding core <NUM> to transition among the power-collapse mode and the clock-gating mode.

The processor <NUM> further includes the power manager <NUM>, the inrush current information storage <NUM>, and the power-down mode priority storage <NUM>. The power manager <NUM> may be configured to select among the cores <NUM> for entering or exiting power-down modes by selectively controlling the power-down mode circuits <NUM>. In some examples, the power manager <NUM> may include a processor (such as one of the cores <NUM>) executing software instructions. The power manager <NUM> may select among the cores <NUM> based on inrush current information stored in the inrush current information storage <NUM> and/or the power-down mode priorities stored in the power-down mode priority storage <NUM>. In some examples, the stored inrush current information and/or the power-down mode priorities may be programmable (e.g., changed by software instructions).

The inrush current information storage <NUM> may be, for example, registers storing inrush current information including inrush current caused by entering or exiting the various power-down modes. The process of entering and exiting the various power-down modes may cause inrush current in the cores <NUM> to spike, even to the point of exceeding the capability of current supplies to the cores <NUM>. By utilizing the inrush current information associated with the entering and exiting of the various power-down modes, the power manager <NUM> may determine a number and an order of the cores <NUM> to be selected for entering or exiting the power-down modes efficiently without causing excessive inrush current.

The power-down mode priority storage <NUM> may be, for example, registers storing power-down mode priorities. The priorities may be, for example, based on the times to enter or to exit the power-down modes. For example, the power-collapse mode may take the longest to enter or to exit, and therefore, the power-collapse mode may have the lowest priority. In some examples, the priorities may be based on power saving of the power-down modes.

The power manager <NUM> may further receive an inrush current budget and select the cores <NUM> based on the inrush current budget. The inrush current budget may be based on the current limit of the power supply (e.g., the power management integrated circuit or PMIC). In some examples, the inrush current budget may be further based on present operations of the cores, even the cores not requesting to enter or to exit the power-down modes. For example, in the cases some of the cores are operating in high performance modes (thus consuming more power), the inrush current budget may be reduced.

<FIG> is a block diagram of an exemplary embodiment of the power manager <NUM> of <FIG> operating as a token manager. A token may be a signaling indicating a grant or allowance to enter or exit power-down modes. The power manager <NUM> includes a power manager control <NUM> configured to receive one or more requests to enter or to exit power-down modes from the cores <NUM> (core <NUM>-<NUM> to core <NUM>-<NUM>). Each of the one or more requests indicates that one of the cores wishes to enter or to exit one of the power-down modes.

The multiple cores <NUM> may send the requests to enter or to exit the power-down modes independently and in parallel. For example, the core <NUM>-<NUM> may request a power-up from a power-collapse mode. The core <NUM>-<NUM> may request a power-down from a full-power operation to a clock-gating mode. The <NUM>-<NUM> may request transitioning from the power-collapse mode to the clock-gating mode, and so forth. All the requests may be made at the same time. As described above, enacting all the requests to enter or to exit the power-down modes in the multiple cores <NUM> may cause the inrush current to spike. Accordingly, the power manager control <NUM> may be further configured to select one or more of the cores <NUM> to grant to tokens so as not to cause the inrush current to spike exceeding an inrush current threshold (e.g., the inrush current budget). Additional features of this selection process are presented with <FIG>.

The process of requesting and granting the token is described below. The power manager <NUM> (e.g., the power manager control <NUM>) communicate with the cores <NUM> via the signaling REQ <NUM> (<NUM>-<NUM> to <NUM>-<NUM> for each of the cores <NUM>) and the signaling ACK <NUM> (<NUM>-<NUM> to <NUM>-<NUM> for each of the cores <NUM>). To request permission to enter or exit power-down modes, each of the cores <NUM> may independently and in parallel request a token from the power manager <NUM> by asserting the signaling REQ <NUM>. In some examples, the signaling REQ <NUM> may be carried by multiple signals lines to indicate the desired action and the desired resulting power-down mode (e.g., indicating the desire to exit from the current power-down mode to a full-power operation, to enter a desired power-down mode, the identity of the desired power-down mode, etc.).

The power manager <NUM> (e.g., the power manager control <NUM>) receives the signaling REQ <NUM>. For example, the signaling REQ <NUM> is provided as input to logic gates or components within the power manager control <NUM>. To grant the token, the power manager <NUM> asserts the signaling ACK <NUM> (<NUM>-<NUM> to <NUM>-<NUM> for each of the cores <NUM>). In response to the assertion, the power-down mode circuits <NUM> of the selected cores <NUM> effect the requested power-down actions (e.g., to enter or to exit power-down modes). Upon a completion of the requested power-down action, the power-down mode circuit <NUM> de-asserts both the signaling REQ <NUM> (to terminate the request) and the signaling ACK <NUM> (to indicate a completion of the requested power-down action).

The power manager <NUM> further includes the token register <NUM> and the core status register <NUM> to manage the requests and the tokens. The token register <NUM> includes multiples bits (<NUM> to <NUM>), each of which corresponds to one of the cores <NUM>. The bits <NUM>-<NUM> indicate that a request for token from the corresponding cores <NUM> is active. For example, the bit <NUM> stores the value "<NUM>" to indicate that the corresponding core <NUM>-<NUM> is requesting a token (e.g., the signaling REQ <NUM>-<NUM> is asserted). The bits <NUM> and <NUM> store the value "<NUM>" to indicate that the corresponding cores <NUM>-<NUM> and <NUM>-<NUM> are not requesting a token (e.g., the signaling REQ <NUM>-<NUM> to <NUM>-<NUM> are de-asserted).

The core status register <NUM> stores the current power-modes of the cores. The core status register <NUM> includes bits <NUM>-<NUM> to <NUM>-<NUM>, each of which corresponds to one of the cores <NUM>. For example, the bit <NUM>-<NUM> stores the value C0, indicating that the core <NUM>-<NUM> is in the full-power operation state. The <NUM>-<NUM> stores the value C1, indicating that the core <NUM>-<NUM> is in the power-collapse mode. The <NUM>-<NUM> stores the value C2, indicating that the core <NUM>-<NUM> is in clock-gating mode, and so forth. Via the token register <NUM> and the core status register <NUM>, the power manager <NUM> is able to keep track the current states of token requests and status of each of the cores <NUM> (e.g., full-power operation state or one of the power-down modes).

<FIG> is a timing diagram of the operations of requesting and granting tokens. At T<NUM>, one or more of the cores <NUM> request a token to enter or to exit power-down modes by asserting (e.g., pulling high) the signaling REQ <NUM>. At T<NUM>, the power manager <NUM> (e.g., the power manager control <NUM>) issues a token to the selected core or cores <NUM> by asserting (e.g., pulling high) the signaling ACK <NUM>. In response, a power-down mode circuit <NUM> of the selected core or cores effect the requested power-down mode operation. For example, the power-down mode circuit <NUM> causes the corresponding core <NUM> to power up to the full-power operation state, to power down to one of the power-down modes from the full-power operation state, or to transition among the power-down modes (at A). At B, the requested power-down mode operation is completed. In response, the power-down mode circuit <NUM> notifies the power manager <NUM> the release of the token by de-asserting (e.g., pulling low) both the signaling REQ <NUM> and the signaling ACK <NUM>.

<FIG> is a flowchart of operations of an exemplary embodiment of the power manager control <NUM> selecting one or more cores <NUM> to grant requests. In some examples, the operations may be performed by the power manager control <NUM>. At <NUM>, one or more requests from a plurality of cores are received. In some examples, the power manager control <NUM> receives the requests by providing the signaling REQ <NUM> as input to logic gates or components within the power manager control <NUM>. In some examples, each of the one or more requests is a request to enter or to exit one of a multiple of power-down modes. Referring to <FIG>, for example, the power manager control <NUM> receives token requests from the cores <NUM> (<NUM>-<NUM> to <NUM>-<NUM>) by receiving the low state of the signaling REQ <NUM>-<NUM> and the signaling REQ <NUM>-<NUM>. The power manager control <NUM> then saves the requests in the token register <NUM> by storing "<NUM>"s in the bits <NUM> and <NUM>, indicating respectively that the core <NUM>-<NUM> and <NUM>-<NUM> are requesting to enter or to exit at least one of the power-down modes.

The power-down modes vary and may include a power-collapse mode, in which all power is disconnected from the cores. Other power-down modes may include gating the clocks with the cores (e.g., disabling clocking in the cores). Yet other power-down modes may include adjusting the operating voltages and frequencies of the cores. The requests to enter or to exit the power-down modes may include, for example, powering-up the requesting core by exiting one of the power-down modes to a full-power operation state and powering-down the requesting core by entering one of the power-down modes from a full-power operation state.

At <NUM>, a priority is assigned to each of the cores. Referring to <FIG>, the assignment is based on the power-down modes requested by the cores <NUM> and the power-down mode priorities , optionally stored within the power-down mode priority storage <NUM>. The priorities are based on the times to enter or to exit the power-down modes. For example, the power-collapse mode may take the longest to enter or to exit, and therefore, the power-collapse mode may have the lowest priority. Referring to <FIG>, for example, the power manager control <NUM> may assign priorities to the cores <NUM> based on the states of the cores stored in the core status register <NUM> and the power-down modes indicated by the signaling REQ <NUM>.

At <NUM>, additional one or more of the cores are selected. The additional one or more of the cores are in reference and in addition to the cores selected at <NUM>. The inrush current budget may be based on the current limit of the power supply (e.g., PMIC). In some examples, the inrush current budget may be further based on present operations of the cores, even the cores not requesting to enter or to exit the power-down modes. For example, in the cases some of the cores are operating in high performance modes (thus consuming more power), the inrush current budget may be reduced.

At <NUM>, one or more of the cores are selected to enter or to exit the requested power-down mode or modes. The selection is based on the priorities assigned in operation <NUM>. The selection is based on inrush current information associated with the power-down modes. The inrush currents of the highest priorities are compared with the inrush current budget to allow a maximum selection of cores without exceeding the current budge. In such fashion, the number of the selected cores may be determined.

The selection of cores <NUM> allows for granting the maximum number of requests from the highest priority cores <NUM> ( the cores <NUM> requesting to enter or to exit the power-down modes of highest priorities) within the inrush current budget. Such selection is made using the inrush current information of the highest priority cores <NUM>. The remaining inrush current budget is utilized by selecting cores <NUM> of lower priorities (e.g., requesting to enter or exit power-down modes of lower priories) requiring inrush currents within the remaining inrush current budget. In such fashion, the core or cores <NUM> requesting to enter or to exit a first power-down mode and the core or cores <NUM> requesting to enter or to exit a second, different power-down mode may be selected concurrently. In some examples, "concurrently" may stand for selecting and/or granting requests for entering or exiting different power-down modes at substantially the same time. In some examples, , "concurrently" may stand for selecting and/or granting requests for entering or exiting different power-down modes with substantial, nontrivial overlaps as understood by persons of ordinary skill in the art.

At <NUM>, the power-down mode or modes requested by the selected one or more of the cores are entered or exited. For example, referring to <FIG> and <FIG>, the power-down mode circuits <NUM> of the selected cores <NUM> (e.g., from operations <NUM> and <NUM>) may cause the selected cores <NUM> to enter the requested power-down modes or to exit the current power-down mode.

At <NUM>, priorities of unselected ones of the cores may be increased. In some example, when one of the cores selected completes the entering or exiting the power-down modes, the inrush current budget may be increase. In response, the power manager control <NUM> may return to <NUM> (via operation <NUM>) to select another core or cores to grant requests. Increasing the priorities of the unselected cores, which may be of lower priorities to start with, prevents starvation of these cores.

<FIG> is a block diagram of an exemplary embodiment of the power manager control <NUM>. The block diagram may be an exemplary embodiment of a hardware implementation of the power manager control <NUM> and may include various (e.g., hardware and/or software) components. In some examples, theses components described below may include instructions executed by one of the cores <NUM>-<NUM> - <NUM>-<NUM>.

In an exemplary embodiment, the power manager control <NUM> and the components contained therein, presented below, may include circuits, processor or processors, software executing on the processor or processors, or combinations thereof. These components may include circuits for generating the signals for the functions described infra or signal lines carrying those signals.

By way of example, a component, or any portion of a component, or any combination of components may be implemented with one or more processors.

The power manager control <NUM> includes the priority assignment component <NUM>, the core selection component <NUM>, and the request processing component <NUM>. The priority assignment component <NUM> receives the requested power-down modes (to enter or to exit from) and the requesting cores <NUM> from the request processing component <NUM>. The priority assignment component <NUM> further receives the power-down mode priorities from the programmable power-down mode priority storage <NUM>. The priority assignment component <NUM> assigns priorities to the cores based on the power-down mode priorities (which are based on the time to enter or exit the power-down modes)(e.g., operation <NUM>). In some examples, the priority assignment component <NUM> may increase the priorities of the unselected cores so as not to starve the unselected cores (e.g., operation <NUM>).

The core selection component <NUM> receives the assigned priorities of the requesting cores from the priority assignment component <NUM>. The core selection component <NUM> also receives the inrush current information and the inrush current budget. In some examples, the inrush current information may include the inrush current consumed to enter or to exit each of the power-down modes. The inrush current information may be received from the inrush current information storage <NUM> and may be programmable by software. The inrush current budget may be a limit based on the power supplied (e.g., the PMIC). The inrush current budget may further be adjusted based on the present operations of the cores <NUM>. For example, some of the cores <NUM> may be engaging the current-consuming operations such that the inrush current budget is reduced.

The core selection component <NUM> grants the maximum number of requests from the highest priority cores <NUM> (the cores <NUM> requesting to enter or to exit the power-down modes of highest priorities) within the inrush current budget. Such determination may be made using the inrush current information of the highest priority cores <NUM>. The core selection component <NUM> may further utilizes the remaining inrush current budget by selecting cores <NUM> of lower priorities (e.g., requesting to enter or exit power-down modes of lower priories) requiring inrush currents within the remaining inrush current budget. In such fashion, the core selection component <NUM> may select concurrently the core or cores <NUM> requesting to enter or to exit a first power-down mode and the core or cores <NUM> requesting to enter or to exit a second, different power-down mode. Accordingly, the core selection component <NUM> is configured to select the one or more of the cores <NUM> to grant the power-down mode requests based on an the inrush current budget. Moreover, the number of the one or more of the cores <NUM> selected is based on the inrush current budget. See, for example, operation <NUM>.

The core selection component <NUM> receives notification of a completion of one of the selected cores <NUM> from the request processing component <NUM>. In response, the core selection component <NUM> may perform the selections described above of the unselected cores <NUM> and new requesting cores <NUM>. The unselected cores <NUM> may have increased priorities from the previous selection so as not to starve those cores <NUM>.

The request processing component <NUM> interfaces with cores <NUM> via the signaling REQ <NUM> and the signaling ACK <NUM> to receive requests and to grant requests to enter or to exit power-down modes. To grant requests, the request processing component <NUM> receives the core selection from the core selection component <NUM>. Upon a completion of one of the requests, the request processing component <NUM> sends the notification to the core selection component <NUM>.

The specific order or hierarchy of blocks in the method of operation described above is provided merely as an example. Based upon design preferences, the specific order or hierarchy of blocks in the method of operation may be re-arranged, amended, and/or modified. The accompanying method claims include various limitations related to a method of operation, but the recited limitations are not meant to be limited in any way by the specific order or hierarchy unless expressly stated in the claims.

Claim 1:
A processor apparatus having a plurality of cores, the processor further comprising:
a first circuit configured to
receive one or more requests (<NUM>-<NUM>, <NUM>-<NUM>) from the plurality of cores (<NUM>), each of the one or more requests being to enter one of a plurality of power-down modes from a full-power operation, wherein each power-down mode of the plurality of power-down modes has a priority, the power-down mode having the longest entry time from a full-power operation having the lowest priority;
assign a priority to each of the plurality of cores based on the priority of the power-down mode the core has requested to enter, wherein the cores requesting to enter the power-down modes of highest priorities are highest priority cores;
compare the inrush current caused by entering the power-down mode for each request against an inrush current budget; and
grant the maximum number of requests from the highest priority cores of the plurality of cores without the sum of the inrush currents exceeding the inrush current budget, and utilising a remainder of the inrush current budget by selecting cores of lower priorities requiring inrush currents within the remaining inrush current budget; and
a second circuit (<NUM>) configured to effect entering the respective requested power-down mode in each of the cores having the respective requested power-down mode in each of the cores having the respective request granted and further configured to effect entering the respective requested power-down mode in each of the selected cores of lower priority.