Patent Description:
Various features relate to a package-on-package (PoP) device that includes a bi-directional thermal electric cooler (TEC).

<FIG> illustrates an integrated device package <NUM> that includes a first die <NUM> and a package substrate <NUM>. The package substrate <NUM> includes a dielectric layer and a plurality of interconnects <NUM>. The package substrate <NUM> is a laminated substrate. The plurality of interconnects <NUM> includes traces, pads and/or vias. The first die <NUM> is coupled to the package substrate <NUM> through the first set of solder balls <NUM>. The package substrate <NUM> is coupled to the PCB <NUM> through the second set of solder balls <NUM>. <FIG> also illustrates a heat spreader <NUM> coupled to the die <NUM>. An adhesive or thermal interface material may be used to couple the heat spreader <NUM> to the die <NUM>. As shown in <FIG>, the heat spreader <NUM> is adapted to dissipate heat away from the die <NUM> to an external environment. It is noted that heat may dissipate away from the die in various directions.

One drawback of the above configuration is that the heat spreader <NUM> is a passive heat dissipating device. Thus, there is no active control of how heat is dissipated. That is, the use of heat spreader <NUM> does not allow for a dynamic heat flow control. Second, the use of the heat spreader <NUM> is only applicable when a single die is used in the integrated device package. Today's mobile devices and/or wearable devices include many dies, and thus are more complicated configurations that require more intelligent thermal and/or heat dissipation management. Putting a heat spreader in a device that includes several dies will not provide effective thermal and/or heat dissipation management of the device.

Therefore, there is a need for a device that includes several dies and an effective thermal management of the device, while at the same time meeting the needs and/or requirements of mobile computing devices and/or wearable computing devices. In the patent document, <CIT> a semiconductor chip package is provided include a substrate having circuit patterns and substrate pads connected with the circuit patterns. At least one semiconductor chip is mounted on the substrate, and a thermoelectric cooler having a P-type material plate and an N-type material plate is mounted on the semiconductor chip.

In patent document <CIT> a package on package, POP, device is disclosed, the POP device disclosing a first package comprising: a first substrate; and a first die coupled to the first substrate; a second package coupled to the first package, the second package comprising: a second substrate; and a second die coupled to the second substrate; and a bi-directional thermal electric cooler, TEC, located between the first die and the second substrate, the bi-directional TEC adapted to dynamically dissipate heat back and forth between the first package and the second package, wherein the bi-directional thermal electric cooler, TEC, is configured to dissipate heat from the first die to the second die or from the second die to the first die based on first and second temperature readings and the comparison thereof with predefined maximum operating temperatures.

The invention is defined in the appended claims to which reference is now directed. In the description of embodiments of the invention presented herein, instances of terms such as "for example", "may", "can" etc., if used in relation to features of the independent claims, should not be taken as implying that these features do not form part of the claimed invention.

Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.

The present disclosure describes a package on package (PoP) device that includes a first package, a second package, and a bi-directional thermal electric cooler (TEC). The first package includes a first substrate and a first die coupled to the first substrate. The second package is coupled to the first package. The second package includes a second substrate and a second die coupled to the second substrate. The bi-directional TEC is located between the first die and the second substrate. The bi-directional TEC is adapted to dynamically dissipate heat back and forth between the first package and the second package. The bi-directional TEC is adapted to dissipate heat from the first die to the second die in a first time period. The bi-directional TEC is further adapted to dissipate heat from the second die to the first die in a second time period. The bi-directional TEC is adapted to dissipate heat from the first die to the second die through the second substrate.

<FIG> illustrates an example of a package on package (PoP) device <NUM> that includes a first package <NUM> (e.g., first integrated device package), a second package <NUM> (e.g., second integrated device package), and a thermal electric cooler (TEC) <NUM>.

The first package <NUM> includes a first substrate <NUM>, a first die <NUM>, and a first encapsulation layer <NUM>. The first package <NUM> may also include the TEC <NUM>. The TEC <NUM> is coupled to the first die <NUM>. An adhesive <NUM> (e.g., thermally conductive adhesive) may be used to couple the TEC <NUM> to the first die <NUM>. The adhesive <NUM> may couple a first surface (e.g., bottom surface) of the TEC <NUM> to a back side of the first die <NUM>. The TEC <NUM> is a bi-directional TEC capable of dissipating heat in a first direction (e.g., in a first time period / frame) and a second direction (e.g., in a second time period / frame), where the second direction is opposite to the first direction. More specifically, the TEC <NUM> is a bi-directional TEC that is configured and/or adapted to dynamically (e.g., in real time during operation of the PoP device <NUM>) dissipate heat back and forth between the first package <NUM> and the second package <NUM>. The TEC <NUM> is a bi-directional heat transfer means. The TEC <NUM> provides active heat dissipation (e.g., active heat transfer means). Various examples of TECs are further illustrated and described in detail below in at least <FIG>.

The first substrate <NUM> is package substrate. The first substrate <NUM> includes at least one dielectric layer <NUM>, several interconnects <NUM>, a first solder resist layer <NUM>, and a second solder resist layer <NUM>. The first solder resist layer <NUM> is on a first surface (e.g., bottom surface) of the first substrate <NUM>. The second solder resist layer <NUM> is on a second surface (e.g., top surface) of the first substrate <NUM>. The dielectric layer <NUM> may include a core layer and/or a prepeg layer. The interconnects <NUM> may include several traces, vias, and/or pads. The interconnects <NUM> may be located in the dielectric layer <NUM> and/or on a surface of the dielectric layer <NUM>.

An interconnect is an element or component of a device (e.g., integrated device, integrated device package, die) and/or a base (e.g., package substrate, printed circuit board, interposer) that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and/or an under bump metallization (UBM) layer. In some implementations, an interconnect is an electrically conductive material that is capable of providing an electrical path for a signal (e.g., data signal, ground signal, power signal). An interconnect may include more than one element / component. A set of interconnects may include one or more interconnects.

The first die <NUM> is coupled to (e.g., mounted) the first substrate <NUM> through a set of solder <NUM> (e.g., solder balls). The first die <NUM> may be a logic die (e.g., central processing unit (CPU), graphical processing unit (GPU)). The first die <NUM> may be a flip chip. The first die <NUM> may be coupled to the first substrate <NUM> differently in different implementations. For example, the first die <NUM> may be coupled to the first substrate <NUM> through pillars and/or solder. Other forms of interconnects may be used to couple the first die <NUM> to the first substrate <NUM>.

The first encapsulation layer <NUM> encapsulates at least part of the first die <NUM>. The first encapsulation layer <NUM> may include a mold and/or an epoxy fill. The first encapsulation layer <NUM> may include several solder <NUM>, <NUM>, <NUM>, and <NUM> (e.g., solder balls). The solder <NUM>, <NUM>, <NUM>, and <NUM> may be coupled to the interconnects <NUM>.

The first package <NUM> is coupled to (e.g., mounted on) a printed circuit board (PCB) <NUM> through a set of solder balls <NUM>. The set of solder balls <NUM> is coupled to the interconnects <NUM>. However, it is noted that the first package <NUM> may be coupled to the PCB <NUM> by using other means, such as a land grid array (LGA) and/or a pin grid array (PGA).

The second package <NUM> includes a second substrate <NUM>, a second die <NUM>, and a second encapsulation layer <NUM>. The second substrate <NUM> is a package substrate. The second substrate <NUM> includes at least one dielectric layer <NUM>, several interconnects <NUM>, a first solder resist layer <NUM>, and a second solder resist layer <NUM>. The first solder resist layer <NUM> is on a first surface (e.g., bottom surface) of the second substrate <NUM>. The second solder resist layer <NUM> is on a second surface (e.g., top surface) of the second substrate <NUM>. The dielectric layer <NUM> may include a core layer and/or a prepeg layer. The interconnects <NUM> may include several traces, vias, and/or pads. The interconnects <NUM> may be located in the dielectric layer <NUM> and/or on a surface of the dielectric layer <NUM>.

The second die <NUM> is coupled to (e.g., mounted) the second substrate <NUM> through a set of solder balls <NUM>. The second die <NUM> may be a logic die or a memory die. The second die <NUM> may be a flip chip. The second die <NUM> may be coupled to the second substrate <NUM> differently in different implementations. For example, the second die <NUM> may be coupled to the second substrate <NUM> through pillars and/or solder. Other forms of interconnects may be used to couple the second die <NUM> to the second substrate <NUM>. The second encapsulation layer <NUM> encapsulates at least part of the second die <NUM>. The second encapsulation layer <NUM> may include a mold and/or an epoxy fill.

The second package <NUM> is coupled (e.g., mounted) to the first package <NUM> such that the TEC <NUM> is between the first package <NUM> and the second package <NUM>. As shown in <FIG>, the TEC <NUM> is located between the first die <NUM> and the second substrate <NUM>. An adhesive <NUM> (e.g., thermally conductive adhesive) may be used to couple the TEC <NUM> to the second substrate <NUM>. The adhesive <NUM> may couple a second surface (e.g., top surface) of the TEC <NUM> to the first solder resist layer <NUM>. In some implementations, the adhesive <NUM> may couple the second surface of the TEC <NUM> to the dielectric layer <NUM>. The second package <NUM> may be coupled to the first package <NUM> so that at least part of the second die <NUM> is vertically aligned with the TEC <NUM> and/or the first die <NUM>. The second package <NUM> may be electrically coupled to the first package <NUM> through the solder <NUM>, <NUM>, <NUM> and <NUM>. The solder <NUM>, <NUM>, <NUM>, and <NUM> may be coupled to the interconnects <NUM>.

As mentioned above, the TEC <NUM> is a bi-directional TEC capable of dissipating heat in a first direction (e.g., in a first time period / frame) and a second direction (e.g., in a second time period / frame), where the second direction is opposite to the first direction.

<FIG> illustrate examples of how the TEC <NUM> may be adapted and/or configured to dissipate heat. <FIG> illustrates the TEC <NUM> adapted to dissipate heat from the first package <NUM> to the second package <NUM> during a first time period. At or during the first time period, the TEC <NUM> is adapted to dissipate heat from the first die <NUM> to the second package <NUM>. The heat that is dissipated from the first die <NUM> may pass through the TEC <NUM>, the second substrate <NUM> (which includes the dielectric layer <NUM>, the interconnects <NUM>), the solder balls <NUM>, the second die <NUM>, and/or the second encapsulation layer <NUM>. Thus, some of the heat from the first die <NUM> may heat the second die <NUM>.

<FIG> illustrates the TEC <NUM> adapted to dissipate heat from the second package <NUM> to the first package <NUM> during a second time period. At or during the second time period, the TEC <NUM> is adapted to dissipate heat from the second die <NUM> to the first package <NUM>. The heat that is dissipated from the second die <NUM> may pass through the solder balls <NUM>, the second substrate <NUM> (which includes the dielectric layer <NUM>, the interconnects <NUM>), the TEC <NUM> and/or the first die <NUM>. Thus, some of the heat from the second die <NUM> may heat the first die <NUM>.

According to the claimed invention, the TEC <NUM> is adapted to dissipate heat back and forth between the first package <NUM> and the second package <NUM> (i.e. back and forth between the first die <NUM> and the second die <NUM>) to provide optimal die performance while still operating within thermal limits of the dies. For example, if the first die <NUM> has reached its thermal operating limit (i.e. the temperature operating limit), the TEC <NUM> is adapted and/or configured to dissipate heat away from the first die <NUM> and towards the second die <NUM> (as long as the second die has not reached its thermal operating limit). Similarly, if the first die <NUM> is still within its thermal operating limit, but the second die <NUM> has reached its thermal operating limit, the TEC <NUM> is adapted and/or configured to dissipate heat away from the second die <NUM> and towards the first die <NUM>. Thus, the TEC <NUM> may be a bi-directional TEC that is configured and/or adapted to dynamically (e.g., in real time during operation of the PoP device <NUM>) dissipate heat back and forth between the first package <NUM> and the second package <NUM>. Various examples of TECs in a device (e.g., PoP device) and how the TECs may be configured, adapted, and/or controlled for thermal management are further illustrated and described in detail below in at least <FIG> and <FIG>, wherein only PoP devices fall under the claimed invention.

According to the claimed invention, a TEC (i.e. a bi-directional TEC) is located between two dies. An example of such a configuration is illustrated and described below in <FIG>.

<FIG> illustrates an example of another package on package (PoP) device <NUM> that includes a first package <NUM> (e.g., first integrated device package), the second package <NUM> (e.g., second integrated device package), and the thermal electric cooler (TEC) <NUM>. In some implementations, the PoP device <NUM> of <FIG> is similar to the PoP device <NUM>, except that different types of interconnects are used to electrically couple the second package <NUM> to the first package <NUM>.

The first package <NUM> includes the first substrate <NUM>, the first die <NUM>, and the first encapsulation layer <NUM>. The first package <NUM> may also include the TEC <NUM>. The TEC <NUM> is coupled to the first die <NUM>. The adhesive <NUM> (e.g., thermally conductive adhesive) may be used to couple the TEC <NUM> to the first die <NUM>. The adhesive <NUM> may couple a first surface (e.g., bottom surface) of the TEC <NUM> to the back side of the first die <NUM>. The TEC <NUM> is a bi-directional TEC capable of dissipating heat in a first direction (e.g., in a first time period / frame) and a second direction (e.g., in a second time period / frame), where the second direction is opposite to the first direction. In some implementations, the TEC <NUM> is a bi-directional TEC that is configured and/or adapted to dynamically (e.g., in real time during operation of the PoP device <NUM>) dissipate heat back and forth between the first package <NUM> and the second package <NUM>, as described above for <FIG>.

The first encapsulation layer <NUM> encapsulates at least part of the first die <NUM>. The first encapsulation layer <NUM> may include a mold and/or an epoxy fill. The first encapsulation layer <NUM> may include several vias <NUM>. The vias <NUM> may be through encapsulation vias (TEVs) or through mold vias (TMVs). The vias <NUM> are coupled to the interconnects <NUM>. Several interconnects <NUM> are formed in the first encapsulation layer <NUM>. The interconnects <NUM> may be redistribution interconnects. The interconnects <NUM> are coupled to the vias <NUM>. A solder <NUM> (e.g., solder ball) is coupled to the interconnects <NUM> and the second substrate <NUM>. The solder <NUM> is coupled to the interconnects <NUM> of the second substrate <NUM>.

<FIG> illustrates a profile view of an example of thermal electric cooler (TEC) <NUM>. The TEC <NUM> may be implemented in any packages and/or package on package (PoP) devices described in the present disclosure. For example, the TEC <NUM> may be the TEC <NUM> described above.

The TEC <NUM> may be a bi-directional TEC. The TEC <NUM> may be a bi-directional heat transfer means. The TEC <NUM> includes an N-doped component <NUM> (e.g., N-doped semiconductor) and a P-doped component <NUM> (e.g., P-doped semiconductor), a carrier <NUM>, an interconnect <NUM>, and an interconnect <NUM>. The carrier <NUM> may be optional. The TEC <NUM> may include several N-doped components <NUM> and several P-doped components <NUM>. The TEC <NUM> may include several interconnects <NUM> and several interconnects <NUM>. The interconnects <NUM> are located on a first side (e.g., bottom side) of the TEC <NUM>. The interconnects <NUM> are located on a second side (e.g., top side) of the TEC <NUM>.

The N-doped component <NUM> is coupled to the P-doped component <NUM> through an interconnect. For example, the interconnect <NUM> is coupled to the N-doped component <NUM>. The N-doped component <NUM> is coupled to the interconnect <NUM>. The interconnect <NUM> is coupled to the P-doped component <NUM>. The P-doped component <NUM> is coupled to another interconnect <NUM>. The above pattern may be repeated several times to form the TEC <NUM>.

In some implementations, the TEC <NUM> may be configured and/or adapted to dissipate heat in a first direction and a second direction by providing a current through the TEC <NUM>. Different polarities of the current that run through the TEC <NUM> may configure and/or adapt the TEC <NUM> differently. For example, a first current (e.g., first current with a first polarity) that flows from the interconnect <NUM>, the N-doped component <NUM>, the interconnect <NUM>, and the P-doped component <NUM> may configure the TEC <NUM> so that heat dissipates from the bottom side of the TEC <NUM> to the top side of the TEC <NUM>. In such an instance, the bottom side of the TEC <NUM> is the cool side, and the top side of the TEC <NUM> is the hot side.

When a second current (e.g., first current with a second polarity) flows from the P-doped component <NUM>, the interconnect <NUM>, the N-doped component <NUM>, and the interconnect <NUM>, the TEC <NUM> may be configured so that heat dissipates from the top side of the TEC <NUM> to the bottom side of the TEC <NUM>. In such instance, the top side of the TEC <NUM> is the cool side, and the bottom side of the TEC <NUM> is the hot side.

Thus, by changing the flow or polarity of the current (e.g., positive current, negative current) through the TEC <NUM>, the TEC <NUM> may be configured as a bi-directional TEC that can be adapted to dissipate heat back and forth between the top side and the bottom side of the TEC <NUM>.

<FIG> illustrates an angled view of a conceptual TEC <NUM>. The TEC <NUM> includes a first pad <NUM> (e.g., first terminal), a second pad <NUM> (e.g., second terminal), a dielectric layer <NUM>, and a dielectric layer <NUM>. The first pad <NUM> may be coupled to an interconnect (e.g., interconnect <NUM>) or N-doped component (e.g., N-doped component <NUM>). The second pad <NUM> may be coupled to an interconnect or P-doped component (e.g., P-doped component <NUM>). The dielectric layers <NUM> and <NUM> surround the respective pads <NUM> and <NUM> to ensure that there is no shorting when the pads <NUM> and <NUM> are coupled to interconnects (e.g., solder) of a package.

The first pad <NUM> and the second pad <NUM> may be located on different portions of the TEC <NUM>. <FIG> illustrates that the first pad <NUM> and the second pad <NUM> are a first side (e.g., top side) of the TEC <NUM>. However, in some implementations, the first pad <NUM> and/or the second pad <NUM> may be located on a second side (e.g., bottom side) of the TEC <NUM>. The TEC <NUM> may be coupled to packages (e.g., die of a package, substrate of a package) by using one or more adhesives (e.g., thermally conductive adhesives). For example, a first adhesive may be coupled on a first side or a first surface of the TEC <NUM>, and a second adhesive may be coupled on a second side or second surface of the TEC <NUM>.

In some implementations, a TEC may include several TECs. That is, a TEC may be an array of TECs that can be individually adapted and/or configured to dissipate heat in a particular direction.

<FIG> illustrates an angled view of a conceptual TEC <NUM> that includes several TECs. The TEC <NUM> is an array of TECs. As shown in <FIG>, the TEC <NUM> includes a carrier <NUM>, a first TEC <NUM>, a second TEC <NUM>, a third TEC <NUM>, a fourth TEC <NUM>, a fifth TEC <NUM>, and a sixth TEC <NUM>. The carrier <NUM> may be used to provide structural support for the individual TECs. The individual TECs (e.g., TEC <NUM>) may be similar to the TEC <NUM>. The TEC <NUM> may be implemented in any of the packages and/or PoP devices described in the present disclosure.

The TEC <NUM> may be used to provide heat dissipation for one or more dies, and/or providing localized heat dissipation for a die. For example, a die may include hot spots and/or cool spots, and in an example not falling within the scope of the claimed invention, the TEC <NUM> may be used to only dissipate heat away from specific hot spot regions on the die.

<FIG> illustrates an example of how an array of TECs may be configured and/or adapted to dissipate heat. As shown in <FIG>, the TEC <NUM> is configured so that some TECs dissipate heat in one direction, while other TECs dissipate heat in another direction. In addition, some TECs may be inactive. When a TEC is inactive, the TEC may still passively conduct (e.g., passive heat conduction) heat from a hotter side to a cooler side. In the example of <FIG>, the TEC <NUM> and the TEC <NUM> are configured and/or adapted to dissipate heat from a top side to a bottom side of the TEC <NUM>. The TEC <NUM> and the TEC <NUM> are configured and/or adapted to dissipate heat from a bottom side to a top side of the TEC <NUM>. The TEC <NUM> and the TEC <NUM> are inactive (off). The TEC <NUM> may be dynamically configured and/or adapted differently based on the temperatures (e.g., localized temperatures) of the die(s), as the die(s) are in operation. The TEC <NUM> may be coupled to one die or several dies.

A thermal electric cooler (TEC) may be adapted and/or configured by one or more controllers in a device. <FIG> illustrates an example of a configuration of how one or more thermal electric coolers (TECs) <NUM> may be controlled, configured and/or adapted to dissipate heat. The configuration includes the TECs <NUM>, a TEC controller <NUM>, a thermal controller <NUM>, and several temperature sensors <NUM>. The TECs <NUM> may be a bi-directional heat transfer means.

The temperature sensors <NUM> include at least one temperature sensor for a first die (e.g., logic die), and at least one temperature sensor for a second die (e.g., memory die). The temperature sensors <NUM> may include other sensors for other dies. The temperature sensors <NUM> may be separate from their respective dies, or they may be integrated into their respective dies. The temperature sensors <NUM> are in communication with the thermal controller <NUM>. The temperature sensors <NUM> may transmit temperature readings to the thermal controller <NUM>. Thus, the thermal controller <NUM> may receive temperature readings from the temperature sensors <NUM>.

The thermal controller <NUM> may be a separate device, unit, and/or die. The thermal controller <NUM> may be configured to control and regulate operations of a TEC and/or dies so that the dies operate within their operational temperature limits. For example, the thermal controller <NUM> may operate how and when an TEC is active (on) or inactive (off). The thermal controller <NUM> may also control the performance of a die, by putting performance limitations on the die. For example, the thermal controller <NUM> may limit the clock speed of a die in order to ensure that the die does not reach or exceed its maximum operating temperature. The thermal controller <NUM> may control, configure, and/or adapt the TECs <NUM> through the TEC controller <NUM>. However, the thermal controller <NUM> may control, configure and/or adapt the TECs <NUM> directly in some implementations. In some implementations, the TEC controller <NUM> is part of the thermal controller <NUM>. The thermal controller <NUM> may transmit signals and/or instruction to the TEC controller <NUM> so that the TEC controller <NUM> can control, adapt and/or configure the TECs <NUM>.

The TEC controller <NUM> may control, adapt and/or configured one or more TECs <NUM> by transmitting one or more currents (e.g., first current, second current) to one or more TECs <NUM>. The property of the current (e.g., polarity of the current) that is transmitted to the TEC may configure how the TEC dissipates heat. For example, a first current having a first polarity (e.g., positive current) that is transmitted to a TEC may configure the TEC to dissipate heat in a first direction (e.g., bottom to top). A second current having a second polarity (e.g., negative current) that is transmitted to a TEC may configure the TEC to dissipate heat in a second direction (e.g., top to bottom), that is opposite to the first direction. Moreover, different amperes of current may transmitted to the different TECs <NUM>. For example, first TEC may be transmitted with a first current comprising a first ampere, while a second TEC may be transmitted with a second current comprising a second ampere.

<FIG> further illustrates some of the variables that the thermal controller <NUM> may take into account to control, adapt and/or configured one or more TECs <NUM>. As shown in <FIG>, the thermal controller <NUM> may receive an input of a temperature of a first die (e.g., logic die) and compare it to the limit temperature (e.g., upper limit temperature) of the first die. The thermal controller <NUM> may further weight the difference (if any) between the temperature of the first die and the limit temperature of the first die to control, adapt and/or configured one or more TECs <NUM> associated with (e.g., coupled to) the first die.

<FIG> also illustrates the thermal controller <NUM> may receive an input of a temperature of a second die (e.g., memory die) and compare it to the limit temperature (e.g., upper limit temperature) of the second die. The thermal controller <NUM> may further weight the difference (if any) between the temperature of the second die and the limit temperature of the second die to control, adapt and/or configured one or more TECs <NUM> associated with (e.g., coupled to) the first die.

In addition to temperature and/or temperature limits, other variables include the rate at which heat is being generated by the dies, the rate at which the temperature is increasing/decreasing in the dies, the source of the power to the packages (e.g., battery, plug-in source) and/or how much are the dies being utilized (e.g., percentage utilization of dies, clock speed). These variables may be weighed differently.

The thermal controller <NUM> may take into account the above various variables separately, independently, concurrently, and/or jointly. An example of how a thermal controller <NUM> may take into account the various temperatures of the dies is illustrated and described in <FIG>.

Different implementations may provide different configurations of a device that includes at least one TEC. <FIG> illustrates an example of another configuration of how one or more thermal electric coolers (TECs) <NUM> may be controlled, configured and/or adapted to dissipate heat. The configuration of <FIG> includes the TEC <NUM>, a first die <NUM>, a TEC controller <NUM>, a thermal controller <NUM>, at least one first temperature sensor <NUM>, and at least one second temperature sensor <NUM>.

The first die <NUM> includes the thermal controller <NUM> and the first temperature sensor <NUM>. The second temperature sensor <NUM> may transmit temperature readings (e.g., temperature readings of a second die) to the first die <NUM>. More specifically, the second temperature sensor <NUM> may transmit temperature readings to the thermal controller <NUM>. Similarly, the first temperature sensor <NUM> may transmit temperature readings (e.g., temperature readings of the first die <NUM>) to the thermal controller <NUM>. Thus, the thermal controller <NUM> may receive temperature readings from the first temperature sensor <NUM> and the second temperature sensor <NUM>. The thermal controller <NUM> may be configured to control and regulate operations of a TEC and/or dies so that the dies operate within their operational temperature limits, in a similar manner as described for the thermal controller <NUM>.

The first die <NUM> and the thermal controller <NUM> may transmit signals and/or instructions to the TEC controller <NUM> so that the TEC controller <NUM> can control, adapt and/or configure the TECs <NUM>. The TEC controller <NUM> may control, adapt and/or configure the TECs <NUM> by transmitting currents, in a similar manner as described for the TEC controller <NUM>.

<FIG> also illustrates some of the variables that the first die <NUM> and/or the thermal controller <NUM> may take into account to control, adapt and/or configured one or more TECs <NUM>. The variables in <FIG> are similar to the variables described in <FIG>, except that the variables may be taken into account by the first die <NUM> and/or the thermal controller <NUM>.

<FIG> illustrates an example of another configuration of how one or more thermal electric coolers (TECs) <NUM> may be controlled, configured and/or adapted to dissipate heat. The configuration of <FIG> includes the TECs <NUM>, a first die <NUM>, a TEC controller <NUM>, the thermal controller <NUM>, at least one first temperature sensor <NUM>, and at least one second temperature sensor <NUM>. <FIG> is similar <FIG>, except that the TEC controller <NUM> is implemented in the first die <NUM>. Thus, the configuration of <FIG> operates in a similar manner the configuration of <FIG>, except that the TEC controller <NUM> operates within the first die <NUM>.

It is noted that different implementations may provide different configurations and/or designs of the above TECs, TEC controller, thermal controller, and temperature sensors.

<FIG> illustrate various examples of how a thermal electric cooler (TEC) in a package on package (PoP) device may be electrically coupled to various components or devices.

<FIG> illustrates the PoP device <NUM> of <FIG>. As shown in <FIG>, the first die <NUM> is electrically coupled to the printed circuit board (PCB) <NUM> through a first set of interconnects <NUM>. The first set of interconnects <NUM> may include a solder (from solder <NUM>), interconnects (e.g., traces, vias, pads) from interconnects <NUM>, and a solder ball (from solder balls <NUM>). The first set of interconnects <NUM> may provide an electrical path between the first die <NUM> a power source (not shown), a thermal controller (not shown), or a thermal electric cooler (TEC) controller (not shown). In some implementations, the thermal controller and/or the TEC controller may be implemented in the first die <NUM>.

<FIG> also illustrates the thermal electric cooler (TEC) <NUM> electrically coupled the PCB <NUM> through a second set of interconnects <NUM>. The second set of interconnect <NUM> may be coupled to pads (e.g., pads <NUM>, <NUM>) and/or terminals on the TEC <NUM> as described in <FIG>. The second set of interconnects <NUM> may include a through substrate via (TSV) that traverses the first die <NUM>, redistribution layers, a solder (from solder <NUM>), interconnects (e.g., traces, vias, pads) from interconnects <NUM>, and a solder ball (from solder balls <NUM>). The second set of interconnects <NUM> may provide an electrical path between the TEC <NUM> and a TEC controller (not shown).

<FIG> illustrates how the TEC <NUM> may be electrically coupled to different components and/or device in the PoP device <NUM>. As shown in <FIG>, the first die <NUM> is electrically coupled to the printed circuit board (PCB) <NUM> through a first set of interconnects <NUM>. The first set of interconnects <NUM> may include a solder (from solder <NUM>), interconnects (e.g., traces, vias, pads) from interconnects <NUM>, and a solder ball (from solder balls <NUM>). The first set of interconnects <NUM> may provide an electrical path between the first die <NUM> a power source (not shown), a thermal controller (not shown), or a thermal electric cooler (TEC) controller (not shown). In some implementations, the thermal controller and/or the TEC controller may be implemented in the first die <NUM>.

<FIG> also illustrates the thermal electric cooler (TEC) <NUM> electrically coupled the PCB <NUM> through a second set of interconnects <NUM>. The second set of interconnect <NUM> may be coupled to pads (e.g., pads <NUM>, <NUM>) and/or terminals on the TEC <NUM> as described in <FIG>. The second set of interconnects <NUM> may include interconnects from interconnect <NUM>, solder <NUM>, interconnects (e.g., traces, vias, pads) from interconnects <NUM>, and a solder ball (from solder balls <NUM>). The second set of interconnects <NUM> may provide an electrical path between the TEC <NUM> and a TEC controller (not shown). In this example, the second set of interconnects <NUM> traverses both the second package <NUM> and the first package <NUM>.

<FIG> also illustrates the thermal electric cooler (TEC) <NUM> electrically coupled the PCB <NUM> through a second set of interconnects <NUM>. The second set of interconnect <NUM> may be coupled to pads (e.g., pads <NUM>, <NUM>) and/or terminals on the TEC <NUM> as described in <FIG>. The second set of interconnects <NUM> may include interconnects from interconnect <NUM> (e.g., redistribution interconnects), a via (e.g., through mold via (TMV), through encapsulation via (TEV)) from vias <NUM>, interconnects (e.g., traces, vias, pads) from interconnects <NUM>, and a solder ball (from solder balls <NUM>). The second set of interconnects <NUM> may provide an electrical path between the TEC <NUM> and a TEC controller (not shown).

<FIG> illustrates three graphs of how the operation of a thermal electric cooler (TEC) may affect the temperatures of various dies. <FIG> illustrates a first graph <NUM>, a second graph <NUM>, and a third graph <NUM>. The first graph <NUM> is a temperature reading of a first die (e.g., during operation of the first die <NUM>) over a time period. The second graph <NUM> is a temperature reading of a second die (e.g., during operation of the second die <NUM>) over a time period. The third graph <NUM> is current reading that is transmitted to / received by the thermal electric cooler (TEC) (e.g., TEC <NUM>) over a time period.

During the time period A, both the first die and the second die are operational. As time passes, the temperatures of the first die and second die increases. Since both the first die and the second die have operating temperatures that are respectively less than their maximum temperatures (e.g., maximum operating temperatures, first maximum temperature, second maximum temperature), the TEC does not have to operational / active. Thus, no current is transmitted to the TEC or received by the TEC.

At the end of the time period A, the second die has reached its maximum operating temperature (e.g., TDIE2). However, the first die has not reached its maximum operating temperature (e.g., TDIE1) at the end of the time period A. Thus, heat can be dissipated away from the second die towards the first die. A current (e.g., first current having a first polarity) is transmitted to and received by the TEC, which causes the TEC to dissipate heat away from the second die. The first polarity may be a positive polarity.

During the time period B, after the TEC is activated and while the TEC is active, the temperature of the second die begins to decrease, while the temperature of the first die increases at a faster rate (due to the heat from the second die being transferred to the first). Since the first die is operational, the first die is generating its own heat, while at the same time, the first die is receiving heat from the second die.

At the end of the time period B, the first die has reached its maximum operating temperature, while the second die is now below its maximum operating temperature. In this instance, heat can be dissipated away from the first die and towards the second die. A current with a different polarity (e.g., opposite polarity, second polarity) is transmitted to and received by the TEC. The second polarity may be a negative polarity. The new polarity of the current causes the TEC to dissipate heat away from the first die and towards the second die.

During the time period C, while the TEC is active with a current with a new polarity, the temperature of the first die begins to decrease, while the temperature of the second begins to increase (due to heat generated from the second die and the heat that is transferred from the first die).

At the end of the time period C, the second die has reached it maximum operating temperature, while the first die is now below its maximum operating temperature. The current that is transmitted to and received by the TEC has now been changed back to another polarity (e.g., first polarity, positive polarity), which causes the TEC to again dissipate heat away from the second die.

During the time period D, the temperature of the second die begins to decrease, while the temperature of the first die increases.

Thus, by changing the current that is transmitted to and received by the TEC, the temperatures of the dies may be dynamically controlled without having to throttle the performance of the dies. However, in some implementations, the thermal management and/or control of the dies may be achieved through a combination of limiting the performance of the dies (e.g., throttling one or more dies) and the use of at least one TEC. It is noted that the different implementations may use different currents with different values and polarity to activate, configure and adapt the TEC to dissipate heat.

Having described an example of how thermal management of dies may be achieved by using at least one TEC, several methods for thermal management of dies that includes at least one TEC will now be described in the next sections. In some implementations, the thermal management of the dies may include limiting the performance of one or more dies.

<FIG> illustrates an exemplary flow diagram of a method <NUM> for thermal management of two or more dies by using at least one thermal electric cooler (TEC). The method <NUM> may be performed by a TEC controller and/or a thermal controller.

The TEC may be active (e.g., on) or inactive (off) before the method <NUM>. The method receives (at <NUM>) temperature(s) (e.g., first temperature reading, second temperature reading) of a first die and temperature(s) of a second die. The first die may be the first die <NUM>. The second die may be the second die <NUM>. The temperatures may be temperature readings from at least one first temperature sensor for the first die, and temperature readings from at least one second temperature sensor for the second die.

The method determines (at <NUM>) whether the temperature of the first die is equal or greater than a maximum threshold operating temperature of the first die. For example, if the maximum threshold operating temperature of the first die is <NUM>°F, the method determines whether the temperature of the first die is equal or greater than <NUM>°F. In instances where there are multiple temperatures (e.g., localized temperatures) for the first die, the method may make several determinations.

When the method determines (at <NUM>) that the temperature of the first die is not equal or greater than the maximum threshold operating temperature of the first die, the method proceeds to determine (at <NUM>) whether the temperature of the second die is equal or greater than a maximum threshold operating temperature of the second die. For example, if the maximum threshold operating temperature of the second die is <NUM>°F, the method determines whether the temperature of the second die is equal or greater than <NUM>°F. In instances where there are multiple temperatures (e.g., localized temperatures) for the second die, the method may make several determinations.

When the method determines (at <NUM>) that the temperature of the second die is not equal or greater than maximum threshold operating temperature of the second die, the method proceeds to instruct (at <NUM>) the TEC to be inactive (e.g., off). In some implementations, instructing the TEC to be inactive includes not transmitting a current to the TEC. If the TEC is already inactive, then there is no current being transmitted to the TEC. The method then proceeds to determine (at <NUM>) whether to continue with the thermal management of the dies.

However, referring back to <NUM>, when the method determines (at <NUM>) that the temperature of the second die is equal or greater than maximum threshold operating temperature of the second die, the method proceeds to configure (at <NUM>) and/or adapt the TEC to dissipate heat away from the second die. In such instances, the method configures and/or adapts the TEC to dissipate heat in a first direction (e.g., direction away from the second die), towards the first die. This may include sending a first current having a first polarity (e.g., positive polarity) to the TEC. The method then proceeds to determine (at <NUM>) whether to continue with the thermal management of the dies.

Referring back to <NUM>, when the method determines (at <NUM>) that the temperature of the first die is equal or greater than the maximum threshold operating temperature of the first die, the method proceeds to determine (at <NUM>) whether the temperature of the second die is equal or greater than a maximum threshold operating temperature of the second die. In instances where there are multiple temperatures (e.g., localized temperatures) for the second die, the method may make several determinations.

When the method determines (at <NUM>) that the temperature of the second die is equal or greater than maximum threshold operating temperature of the second die, the method proceeds to configure (at <NUM>) the TEC to be inactive (e.g., off). In this instance, both the first dies and the second die have temperatures that are greater than their respective maximum threshold temperatures, using the TEC would be not be productive. In such instances, throttling the performance of one or more of the dies (e.g., limiting the clock speed of the dies) may be used to reduce the temperatures of the dies. In some implementations, instructing the TEC to be inactive includes not transmitting a current to the TEC. If the TEC is already inactive, then there is no current being transmitted to the TEC. The method then proceeds to determine (at <NUM>) whether to continue with the thermal management of the dies.

However, referring back to <NUM>, when the method determines (at <NUM>) that the temperature of the second die is not equal or greater than maximum threshold operating temperature of the second die, the method proceeds to configure (at <NUM>) and/or adapt the TEC to dissipate heat away from the first die. In such instances, the method configures and/or adapts the TEC to dissipate heat in a second direction (e.g., direction away from the first die), towards the second die. This may include sending a second current having a second polarity (e.g., negative polarity) to the TEC. The method then proceeds to determine (at <NUM>) whether to continue with the thermal management of the dies.

The method determines (at <NUM>) whether to continue with the thermal management of the dies. If so, the method proceeds back to receive (at <NUM>) temperature(s) of the first die and temperature(s) of the second die.

However, when the method determines (at <NUM>) not to continue with the thermal management of the dies, the method proceeds to configure (at <NUM>) the TEC to be inactive (e.g., off). This may be achieved by discontinuing transmitting any current to the TEC.

<FIG> illustrates an exemplary flow diagram of another method <NUM> for thermal management of two or more dies by using at least one thermal electric cooler (TEC) and/or performance limitations on the dies. The method <NUM> may be performed by a TEC controller and/or a thermal controller.

The TEC may be active (e.g., on) or inactive (off) before the method <NUM>. The method receives (at <NUM>) temperature(s) (i.e. first temperature reading, second temperature reading) of a first die and temperature(s) of a second die. The first die is the first die <NUM>. The second die is the second die <NUM>. The temperatures are temperature readings from at least one first temperature sensor for the first die, and temperature readings from at least one second temperature sensor for the second die.

The method determines (at <NUM>) whether the temperature of the first die is equal or greater than a maximum threshold operating temperature of the first die, and the temperature of the second die is equal or greater than a maximum threshold operating temperature of the second die. In instances where there are multiple temperatures (e.g., localized temperatures) for the first die and/or the second die, the method may make several determinations.

When the method determines (at <NUM>) that both the temperature of the first die is equal or greater than a maximum threshold operating temperature of the first die, and the temperature of the second die is equal or greater than a maximum threshold operating temperature of the second die, the method limits (at <NUM>) the performance of the first die and/or the second die. In some implementations, limiting the performance of the dies may include throttling the die, such as limiting the maximum clock speeds of one or more dies. Different implementations, may limit the performance of the dies differently. For example, the performance of the first die may be limited more than the performance of the second die.

The method then proceeds to receive (at <NUM>) temperature(s) of a first die and temperature(s) of a second die.

However, when the method determines (at <NUM>) that the temperature of the first die is not equal or greater than a maximum threshold operating temperature of the first die, and the temperature of the second die is not equal or greater than a maximum threshold operating temperature of the second die, then method may optionally remove or reduce (at <NUM>) any limitations on the performances of the first die and/or the second die.

The method determines (at <NUM>) whether the temperature of the first die is equal or greater than a maximum threshold operating temperature of the first die, or the temperature of the second die is equal or greater than a maximum threshold operating temperature of the second die. In instances where there are multiple temperatures (e.g., localized temperatures) for the first die and/or the second die, the method may make several determinations.

When the method determines (at <NUM>) that the temperature of the first die is equal or greater than a maximum threshold operating temperature of the first die, or the temperature of the second die is equal or greater than a maximum threshold operating temperature of the second die, the method activates (at <NUM>) a thermal electric cooler (TEC). This may include sending a current to the TEC. The TEC may be activated to either dissipate heat away from the first die or away from the second die. For example, when the temperature of the first die is equal or greater than a maximum threshold operating temperature of the first die, but the temperature of the second die is not equal or greater than a maximum threshold operating temperature of the second die, the TEC is activated to dissipate heat away from the first die. When the temperature of the first die is not equal or greater than a maximum threshold operating temperature of the first die, but the temperature of the second die is equal or greater than a maximum threshold operating temperature of the second die, the TEC is activated to dissipate heat away from the second die. An example of how a TEC may be activated is illustrated and described in <FIG>. The method then proceeds to receive (at <NUM>) temperature(s) of the first die and temperature(s) of the second die.

When the method determines (at <NUM>) that the temperature of the first die is not equal or greater than a maximum threshold operating temperature of the first die, and the temperature of the second die is not equal or greater than a maximum threshold operating temperature of the second die, the method deactivates (at <NUM>) the thermal electric cooler (TEC). Deactivating the TEC may include not transmitting a current to the TEC. When the TEC is already inactive, no current is transmitted either. It is noted that in some implementations, the same current or different currents (e.g., current with different amperes) may be transmitted. In some implementations, a stronger current (e.g., current with a greater ampere) will provide greater active heat dissipation than a weaker current (e.g., current with a lower ampere). Different implementations may use different factors and/or variables to consider the strength of the current. Such factors and/or variables may include the source of the power of the package (e.g., battery power, plug-in power) and/or rate of temperature change of the dies.

The method of <NUM> may be iterated several times until thermal management of the dies ends.

In some implementations, not forming part of the claimed invention but useful for the understanding thereof, providing / fabricating a package on package (PoP) device that includes at least one bi-directional thermal electric cooler (TEC) includes several processes. <FIG> (which includes <FIG>) illustrates an exemplary sequence for providing / fabricating a PoP device that includes at least one bi-directional thermal electric cooler (TEC). In some implementations, the sequence of FIGS. 19A-19C may be used to provide / fabricate the PoP device of <FIG> and/or other PoP devices described in the present disclosure.

It should be noted that the sequence of FIGS. 19A-19C may combine one or more stages in order to simplify and/or clarify the sequence for providing / fabricating a PoP device that includes a bi-directional thermal electric cooler (TEC). In some implementations, the order of the processes may be changed or modified.

Stage <NUM>, as shown in <FIG>, illustrates a state after a substrate <NUM> is provided. The substrate <NUM> may be a package substrate. The substrate <NUM> may be fabricated or supplied by a supplier or manufacturer. The substrate <NUM> includes at least one dielectric layer <NUM>, a set of interconnects <NUM> (e.g., traces, vias, pads), a first solder resist layer <NUM> and a second solder resist layer <NUM>. The dielectric layer <NUM> may include a core layer and/or a prepeg layer.

Stage <NUM> illustrates a state after a first die <NUM> is coupled (e.g., mounted) to the substrate <NUM>. The first die <NUM> is coupled to the substrate <NUM> through a set of solder <NUM> (e.g., solder balls). Different implementations may couple the first die <NUM> to the substrate <NUM> differently. In some implementations, the first die <NUM> is coupled to the substrate <NUM> through a set of pillars and solder.

Stage <NUM> illustrates a state after an encapsulation layer <NUM> is provided (e.g., formed) on the substrate <NUM> and the first die <NUM>. The encapsulation layer <NUM> may encapsulate the entire first die <NUM> or just part of the first die <NUM>. The encapsulation layer <NUM> may be a mold and/or epoxy fill.

Stage <NUM> illustrates a state after at least one cavity <NUM> is formed in the encapsulation layer <NUM>. Different implementations may form the cavity <NUM>. In some implementations, a laser is used to form the cavity <NUM>. In some implementations, the encapsulation layer <NUM> is a photo-patternable layer, and the cavity <NUM> can be formed by using a photo-lithography process (e.g., photo-etching process) to pattern the encapsulation layer <NUM>.

Stage <NUM> illustrates a state after at least one via <NUM> and at least one interconnect <NUM> are formed in and on the encapsulation layer <NUM>. A plating process may be used to form the via <NUM> and the interconnect <NUM>. The interconnect <NUM> may include a trace and/or a pad. The interconnect <NUM> may be a redistribution interconnect. The via <NUM> and the interconnect <NUM> may each include a seed metal layer and metal layer.

Stage <NUM>, as shown in <FIG>, illustrates a state after a thermal electric cooler (TEC) <NUM> is coupled (e.g., mounted) to the first die <NUM>. In some implementations, an adhesive (e.g., thermally conductive adhesive) is used to couple the TEC <NUM> to the first die <NUM>. The TEC <NUM> is a bi-directional TEC. The TEC <NUM> includes pads and/or terminals (e.g., as described in <FIG>). The TEC <NUM> may coupled to the first die <NUM> such that the pads and/or terminals of the TEC <NUM> are coupled (e.g., electrically coupled) to interconnects on the encapsulation layer <NUM> (e.g., redistribution interconnects, interconnect from interconnects <NUM>). Stage <NUM> may illustrate a first package <NUM> that includes the substrate <NUM>, the first die <NUM>, and the encapsulation layer <NUM>. The first package <NUM> may also include the TEC <NUM>.

Stage <NUM> illustrates a state after a second package <NUM> is coupled (e.g., mounted) to the first package <NUM>, such that the TEC <NUM> is between the first package <NUM> and the second package <NUM>. The second package <NUM> includes a second substrate <NUM> (e.g., package substrate), a second die <NUM>, and a second encapsulation layer <NUM>. The second substrate <NUM> includes at least one dielectric layer <NUM> and a set of interconnects <NUM> (e.g., traces, pads, vias). A set of solder balls <NUM> may be coupled to the second substrate <NUM> and interconnects (e.g., interconnect <NUM>) from the first package <NUM>. The second die <NUM> is coupled (e.g., mounted) to the second substrate <NUM> through a set of solder <NUM> (e.g., solder balls). As shown at stage <NUM>, the TEC <NUM> is located between the first die <NUM> and the second substrate <NUM>. In some implementations, an adhesive (e.g., thermal conductive adhesive) is used to couple the second substrate <NUM> to the TEC <NUM>.

Stage <NUM> illustrates a state after a set of solder balls <NUM> is coupled to the first package <NUM>. Stage <NUM> may include a package on package (PoP) device <NUM>, which includes the first package <NUM>, the second package <NUM> and the TEC <NUM>.

<FIG> illustrates an exemplary flow diagram of a method <NUM>, not forming part of the claimed invention but useful for the understanding thereof, for providing / fabricating a package on package (PoP) device that includes at least one bi-directional thermal electric cooler (TEC). In some implementations, the method <NUM> of <FIG> may be used to provide / fabricate the PoP device of <FIG> and/or other PoP devices in the present disclosure.

It should be noted that the flow diagram of <FIG> may combine one or more step and/or processes in order to simplify and/or clarify the method for providing a PoP device that includes a bi-directional TEC. In some implementations, the order of the processes may be changed or modified.

The method provides (at <NUM>) a substrate. The substrate may be a package substrate. The substrate may be fabricated or supplied by a supplier or manufacturer. The substrate includes at least one dielectric layer, a set of interconnects (e.g., traces, vias, pads), a first solder resist layer and a second solder resist layer. The dielectric layer may include a core layer and/or a prepeg layer.

The method couples (at <NUM>) a first die to the substrate. The first die may be coupled (e.g., mounted) to the substrate through a set of solder (e.g., solder balls). Different implementations may couple the first die to the substrate differently. In some implementations, the first die is coupled to the substrate through a set of pillars and solder.

The method optionally provides (at <NUM>) an encapsulation layer on the substrate and the first die. In some implementations, providing the encapsulation layer includes forming the encapsulation layer on the substrate and the first die such that the encapsulation layer encapsulates the entire first die or just part of the first die. The encapsulation layer may be a mold and/or epoxy fill.

The method forms (at <NUM>) interconnects in and on the encapsulation layer. In some implementations, forming interconnects includes forming cavities in the encapsulation layer and forming interconnects in the cavity and/or the encapsulation layer. Different implementations may form the cavities. In some implementations, a laser is used to form the cavities. In some implementations, the encapsulation layer is a photo-patternable layer, and the cavities may be formed by using a photo-lithography process (e.g., photo-etching process) to pattern the encapsulation layer.

Forming the interconnects may include forming at least one via and at least one interconnect in and on the encapsulation layer <NUM>. A plating process may be used to form the vias and the interconnects. The interconnects may include a trace and/or a pad. The interconnects may be a redistribution interconnect. The vias and the interconnects may each include a seed metal layer and metal layer.

The method couples (at <NUM>) a thermal electric cooler (TEC) to the first die. In some implementations, an adhesive (e.g., thermally conductive adhesive) is used to couple (e.g., mount) the TEC to the first die. The TEC is a bi-directional TEC. A first package may be defined by the first substrate, the first die, the encapsulation layer. The first package may also include the TEC coupled to the first die.

The method couples (at <NUM>) a second package to the first package, such that the TEC is between the first package and the second package. The second package includes a second substrate (e.g., package substrate), a second die, and a second encapsulation layer. The second substrate includes at least one dielectric layer and a set of interconnects (e.g., traces, pads, vias). A set of solder balls may be coupled to the second substrate and interconnects from the first package. The TEC is located between the first die (of the first package) and the second substrate (of the second package). In some implementations, an adhesive (e.g., thermal conductive adhesive) is used to couple the second substrate to the TEC.

The method provides (at <NUM>) a set of solder balls to the first package. More specifically, the set of solder balls may be coupled to the first substrate of the first package.

<FIG> illustrates an example of another package on package (PoP) device <NUM> that includes a first package <NUM> (e.g., first integrated device package), a second package <NUM> (e.g., second integrated device package), a first thermal electric cooler (TEC) <NUM>, and a second TEC <NUM>. In some implementations, the first thermal electric cooler (TEC) <NUM> and the second TEC <NUM> may be configured as an assembly or an array of TECs, as described in <FIG>.

The first package <NUM> includes a first substrate <NUM>, a first die <NUM> (e.g., first logic die), a second die <NUM> (e.g., second logic die), and a first encapsulation layer <NUM>. The first substrate <NUM> includes at least one dielectric layer <NUM> and a set of interconnects <NUM>. The first package <NUM> may also include the first TEC <NUM> and the second TEC <NUM>. The first TEC <NUM> is coupled to the first die <NUM>. The second TEC <NUM> is coupled to the second die <NUM>. An adhesive (e.g., thermally conductive adhesive) may be used to couple the TECs (e.g., first TEC <NUM>) to the first dies (e.g., die <NUM>).

The second package <NUM> is coupled (e.g., mounted) to the first package <NUM>, such that the first TEC <NUM> and the second TEC <NUM> are between the first package <NUM> and the second package <NUM>. The second package <NUM> includes a second substrate <NUM>, a first die <NUM>, a second die <NUM>, a first encapsulation layer <NUM>, and a third TEC <NUM>. The second substrate <NUM> includes at least one dielectric layer <NUM> and a set of interconnects <NUM>. The first TEC <NUM> is between the first die <NUM> and the second substrate <NUM>. The second TEC <NUM> is between the second die <NUM> and the second substrate <NUM>. The third TEC <NUM> is between the first die <NUM> and the second die <NUM>.

The first TEC <NUM> is a bi-directional TEC capable of dissipating heat in a first direction (e.g., in a first time period / frame) and a second direction (e.g., in a second time period / frame), where the second direction is opposite to the first direction. Similarly, the second TEC <NUM> is a bi-directional TEC capable of dissipating heat in a first direction (e.g., in a first time period / frame) and a second direction (e.g., in a second time period / frame), where the second direction is opposite to the first direction. The third TEC <NUM> is a bi-directional TEC capable of dissipating heat in a first direction (e.g., in a first time period / frame) and a second direction (e.g., in a second time period / frame), where the second direction is opposite to the first direction.

In some implementations, the TECs <NUM> and <NUM> are bi-directional TECs that may be configured and/or adapted to dynamically (e.g., in real time during operation of the PoP device <NUM>) dissipate heat back and forth between the first package <NUM> and the second package <NUM>, as described in <FIG>.

In some implementations, the TECs <NUM> and <NUM> are bi-directional TECs that may be configured and/or adapted to dynamically (e.g., in real time during operation of the PoP device <NUM>) dissipate heat back and forth between the first die <NUM> and the second die <NUM>. That is, the TECs <NUM> and <NUM> may be configured such that heat that is dissipated away from the first die <NUM> may be dissipated towards the second die <NUM>. Thus, in some implementations, the TECs <NUM> and <NUM> may be configured so that heat dissipates from the first die <NUM>, through the first TEC <NUM>, the second substrate <NUM>, the second TEC <NUM>, and to the second die <NUM>.

In some implementations, the TECs <NUM> and <NUM> may be configured such that heat that is dissipated away from the second die <NUM> may be dissipated towards the first die <NUM>. Thus, in some implementations, the TECs <NUM> and <NUM> may be configured so that heat dissipates from the second die <NUM>, through the second TEC <NUM>, the second substrate <NUM>, the first TEC <NUM>, and to the first die <NUM>.

In some implementations, the TEC <NUM> is a bi-directional TEC that may be configured and/or adapted to dynamically (e.g., in real time during operation of the PoP device <NUM>) dissipate heat back and forth between the first die <NUM> and the second die <NUM>. That is, for example, the TEC <NUM> and <NUM> may be configured such that heat that is dissipated away from the first die <NUM> may be dissipated towards the second die <NUM>. Different implementations may configure the TECS differently to achieve a desired thermal management of the dies in the PoP device <NUM>.

<FIG> illustrates various electronic devices that may be integrated with any of the aforementioned integrated device, semiconductor device, integrated circuit, die, interposer, package or package-on-package (PoP). For example, a mobile phone device <NUM>, a laptop computer device <NUM>, and a fixed location terminal device <NUM> may include an integrated device <NUM> as described herein. The integrated device <NUM> may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, package-on-package devices described herein. The devices <NUM>, <NUM>, <NUM> illustrated in <FIG> are merely exemplary. Other electronic devices may also feature the integrated device <NUM> including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, steps, features, and/or functions illustrated in <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and/or <NUM> may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. It should also be noted that <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and/or <NUM> and its corresponding description in the present disclosure is not limited to ICs. In some implementations, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and/or <FIG> and its corresponding description may be used to manufacture, create, provide, and/or produce integrated devices. In some implementations, a device may include a die, a die package, an integrated circuit (IC), an integrated device, an integrated device package, a wafer, a semiconductor device, a package on package (PoP) device, and/or an interposer.

Claim 1:
A package on package (PoP) device comprising:
a first package (<NUM>, <NUM>, <NUM>) comprising:
a first substrate (<NUM>, <NUM>); and
a first die (<NUM>, <NUM>) coupled to the first substrate;
a second package (<NUM>, <NUM>, <NUM>) coupled to the first package, the second package comprising:
a second substrate (<NUM>, <NUM>); and
a second die (<NUM>, <NUM>) coupled to the second substrate; and
a bi-directional thermal electric cooler,TEC, (<NUM>, <NUM>, <NUM>) located between the first die and the second substrate, the bi-directional TEC adapted to dynamically dissipate heat back and forth between the first package and the second package, wherein the bi-directional thermal electric cooler, TEC, is configured to:
dissipate heat from the first die to the second die when (i) a first temperature reading of the first die, is equal or greater than a first maximum operating temperature of the first die, and (ii) a second temperature reading of the second die, is less than a second maximum operating temperature of the second die; and
dissipate heat from the second die to the first die when (i) the second temperature reading is equal or greater than the second maximum operating temperature, and (ii) the first temperature reading is less than the first maximum operating temperature.