Patent Description:
PCDs commonly include an application processor ("AP") that is comprised within a complex system termed a mobile chipset or system on a chip ("SoC"). The AP is generally the overall supervisor of the functions delivered by the SoC and, as such, is often in the role of a "master" processor directing the activities of other "slave" processors that are dedicated to delivering specific functionalities. For example, the modem processor of a SoC is usually designated as a slave processor to the AP.

On many SoCs, the modem operates according to a peripheral component interconnect express ("PCIe") protocol. The PCIe protocol not only dictates what a modem should do, but also when the modem is allowed to do it The PCIe protocol is a low-level standard for SoC components and is the protocol used by end-point components (such as a modem) to communicate over a high data rate, PCIe bus with master processors (such as an AP), as would be understood by one of ordinary skill in the art.

By contrast, an AP generally functions according to a Modem-Host Interface ("MHI") protocol that is "on top of" the PCIe standard. That is, the MHI protocol is a master protocol that dictates actions of the AP including its transitions in and out of sleep states (I. , its modes) as well as end-point sleep states. The PCIe root complex runs on the master AP and is used by the AP to manage PCIe channel links available to end-point components, packet handling between modules, etc. In this way, an end-point component such as a modem relies on the AP to tell it when it can make use of a PCIe channel link for data packet transfer ("DMA") and when it should enter a low-power consumption sleep state.

As would be understood by one of ordinary skill in the art, according to PCIe protocol, establishing a PCIe channel link between a master AP and a slave modem is triggered by action from the AP that transitions the AP into, or out of, a sleep state (such as a D3 hot state or a D3 cold state). The PCIe protocol won't allow the modem to establish a communications link with the AP unless and until the AP makes a state transition. And so, if an overflow of downlink data packets is queued for processing by a modem, and the master AP is taking no action to transition from its own MHI state, then the modem will not be allowed to establish a PCIe communications link with the AP for processing the workload. The modem stays in its own low-power state. From there, the overflow of unprocessed data packets may overwhelm the limited amount of memory available to the modem, resulting in an undesirable modem crash.

Accordingly, what is needed in the art is a method and system for addressing the scenario explained above and avoiding a modem crash. More specifically, what is needed in the art is a system and method for stabilizing an end-point modem while it awaits an AP-driven PCIe link reestablishment.

Attention is drawn to document <CIT> which relates to a method of and system for allocating a buffer. The method comprises the steps of partitioning less than the total buffer storage capacity to a plurality of queue classes, allocating the remaining buffer storage as a spare buffer, and assigning incoming packets into said queue classes based on the packet type. When a queue becomes congested, incoming packets are tagged with the assigned queue class and these additional incoming packets are sent to said spare buffer. When the congested queue class has space available, the additional incoming packets in said spare buffer are pushed into the tail of the congested queue class.

Further attention is drawn to document <CIT> which relates to a semiconductor device and a semiconductor system. A semiconductor device includes a non-volatile memory; a device interface circuit which receives an input/output (I/O) request from a host; and a device controller which executes a data access according to the I/O request on the non-volatile memory, and transmits an interrupt to the host a predetermined time before completion of the data access.

Furthermore attention is drawn to document <CIT> which relates to a packet control function (PCF) within a wireless communication network, such as a network based on the TIA/EIA/IS-<NUM> family of standards, which manages incoming data for dormant mobile terminals. In response to the PCF receiving incoming data for a dormant mobile terminal, it starts a reactivation timer, begins buffering the incoming data, and initiates reactivation of the mobile terminal. If the network reestablishes connection with the mobile terminal before expiration of the reactivation timer, the PCF transfers buffered data to the mobile terminal; otherwise, it flushes the buffered data and resets the timer. Subsequent incoming data causes this process to repeat, but the timer's expiration period limits the repeat interval. This period limits the frequency at which reactivation is attempted, thus limiting network signaling overhead. Further, the PCF limits the memory needed for buffering incoming data, by discarding data received during the expiration period in excess of a defined buffer limit.

Further embodiments of the invention are defined by the appended dependent claims. Various embodiments of methods and systems for a modem stabilization in a SoC of a portable computing device ("PCD") when waiting for an application processor ("AP") to reestablish a PCIe communications link are disclosed.

In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as "102A" or "102B", the letter character designations may differentiate two like parts or elements present in the same figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral to encompass all parts having the same reference numeral in all figures.

" Any aspect described herein as "exemplary" is not necessarily to be construed as exclusive, preferred or advantageous over other aspects.

In this description, the term "application" may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an "application" referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

As used in this description, the terms "component," "database," "module," "system," "processing component," "processing engine," "modem," "application processor" and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution and represent exemplary means for providing the functionality and performing the certain steps in the processes or process flows described in this specification. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).

In this description, the terms "central processing unit ("CPU")," "digital signal processor ("DSP")," "application processor ("AP")," "chip" and "chipset" are non-limiting examples of processing components that may reside in a PCD and are used interchangeably except when otherwise indicated. Moreover, as distinguished in this description, a CPU, DSP, AP or a chip or chipset may be comprised of one or more distinct processing components generally referred to herein as "core(s).

In this description, reference to "external memory device" and the like refers to a broader class of non-volatile (i.e., retains its data after power is removed) programmable memory and will not limit the scope of the solutions disclosed. As such, it will be understood that use of the terms envisions any programmable read-only memory or field programmable non-volatile memory suitable for a given application of a solution such as, but not limited to, embedded multimedia card ("eMMC") memory, EEPROM, flash memory, etc..

In this description, the term "portable computing device" ("PCD") is used to describe any device operating on a limited capacity power supply, such as a battery. Although battery operated PCDs have been in use for decades, technological advances in rechargeable batteries coupled with the advent of third generation ("<NUM>") and fourth generation ("<NUM>") and fifth generation ("<NUM>") wireless technology have enabled numerous PCDs with multiple capabilities. Therefore, a PCD may be a cellular telephone, a satellite telephone, a pager, a PDA, a smartphone, a navigation device, a tablet, a smartbook or reader, a media player, a combination of the aforementioned devices, a laptop computer with a wireless connection, among others.

In this description, the term "DMA engine" refers to a direct memory access component of the SoC that allows certain hardware or subsystems, such as a modem for example, to access system and/or peripheral memory independently from the central processing unit or application processor.

In this description, the term "GPIO" refers to a general purpose input/output communication or signal and/or the physical connection within a SoC designated for handling GPIO communications. A GPIO connection is a type of pin commonly available on an integrated circuit without a designated function. While most pins on a SoC have a dedicated purpose, such as sending a signal to a certain component, the function of a GPIO pin is customizable and can be controlled by software. Embodiments of the solution may leverage a GPIO connection to communicate between a slave modem and a master AP in certain scenarios.

For convenience of describing the exemplary embodiments of the solution, this description refers to "D3hot" and "D3cold" low-power states which are substates of a D3 power state, although embodiments of the solution may be applicable in scenarios that include other low power states such as, but not limited to, D1 and/or D2 low-power states. D0 is understood in the art to be an active processing state.

As one of ordinary skill in the art would recognize, processors may transition between various power states in response to workload demands, thermal energy generation/dissipation levels and power consumption goals. D3 is generally understood in the art to be the lowest-powered device low-power state. The D3 state is commonly subcategorized into two separate and distinct substates, D3hot and D3cold. A slave processor is in the D3hot substate if the slave processor is in the D3 state and the system is in the active S0 system power state. In D3hot, the processor is connected to a power source (although the processor might be configured to draw low current), and the presence of the processor on the PCIe bus can be detected. By contrast, a processor may be in the D3cold substate if the processor is in the D3 state and the system is in a low-power state (a state other than S0). In the D3cold substate, the processor might receive a trickle current, but the processor and the system are effectively turned off until a wake event occurs.

A processor can enter D3hot directly from the D0 state. The transition from D0 to D3hot is made under software control by a driver, as would be understood in the art. A modem in D3hot may be detected on the PCIe bus that it connects to. The bus must remain in the D0 state while the modem is in the D3hot substate. From D3hot, the modem can either return to D0 or enter D3cold. D3cold can be entered only from D3hot.

In D3cold, the modem may be physically connected to the PCIe bus but the presence of the modem on the bus cannot be detected (that is, until the modem is turned on again). In D3cold, either the PCIe bus that the modem connects to is in a low-power state and/or the modem is in a low-power state that doesn't allow it to respond when the PCIe bus driver tries to detect its presence.

The transition from D3hot to D3cold by a modem may occur with no driver interaction. Instead, the driver may indicate whether it is prepared for a D3cold transition before it initiates the transition from D0 to D3hot. Subsequently, a transition from D3hot to D3cold may or may not occur, depending on whether all of the conditions are right to enable the transition.

When a modem enters D3cold, the AP may cause the power source (I. , the modem PMIC) to turn off. A modem that is transitioned into D3cold transitions out only by entering D0. There is no direct transition from D3cold to D3hot. In the D3cold substate, a processor may be able to trigger a wake signal to wake a sleeping AP.

In this description, the term PCIe is a reference to peripheral component interconnect express. PCIe is a serial I/O interconnect between components on a board, such as between a master application processor ("AP") and an end-point, slave modem ("MDM"). PCIe connections are often used for memory mapping transactions and interrupts. The PCIe bus is multi-lane, with each lane having a pair of connections (one for incoming communications traffic and one for outgoing communications traffic). Notably, PCIe is also an interface standard or protocol for connecting high-speed components over a PCIe interconnect. Accordingly, use of the term "PCIe" in this description may refer to both the physical interconnect between a master AP and a slave modem and the protocol by which use of the interconnect is governed.

In this description, the term "MHI" is a reference to a Modem-Host Interface. MHI is a protocol commonly used by host processors, such as an AP, to control and communicate with modem devices over high speed peripheral buses or shared memory, such as PCIe. Even though MHI can be easily adapted to any peripheral buses, it is primarily used with PCIe based devices. MHI provides logical channels over the physical buses and allows transporting the modem protocols, such as IP data packets, modem control messages, and diagnostics over at least one of those logical channels. Also, the MHI protocol provides data acknowledgment features and manages the power state of the slave modems via one or more logical channels.

In this description, the term "root complex" references a component that connects modem and its memory subsystem to a PCIe switch fabric composed of one or more switch devices. The root complex is executed by the AP.

In certain application scenarios, a modem processor ("MDM") may be unable to exit a D3cold state, and unable to move out of M3 while waiting for D3 hot/cold state, to process incoming data packets when an application processor ("AP") is "stuck" in its own low power state. As described above, the PCIe protocol may prevent the MDM from transitioning out of D3cold unless or until the AP transitions out of its own state of inactivity. In such situations, the MDM may be in danger of crashing and adversely affecting user experience. As will become clearer from a review of the figures and the associated detailed descriptions below, novel methods may be employed to stabilize the modem and avoid such a crash without violating the MHI / PCIe protocol hierarchy.

Beginning now with <FIG>, illustrated is a functional block diagram of an exemplary, non-limiting aspect of a PCD in the form of a wireless telephone for implementing methods and systems for modem stabilization when waiting for an AP-driven PCIe link recovery. As shown, the PCD <NUM> includes an on-chip system <NUM> that includes a heterogeneous, multi-core central processing unit ("CPU") <NUM> and an analog signal processor <NUM> that are coupled together. The CPU <NUM> may comprise a zeroth core <NUM>, a first core <NUM>, and an Nth core <NUM> as understood by one of ordinary skill in the art. Further, instead of a CPU <NUM>, a digital signal processor ("DSP") may also be employed as understood by one of ordinary skill in the art. Moreover, as is understood in the art of heterogeneous multi-core processors, each of the cores <NUM>, <NUM>, <NUM> may process workloads at different maximum voltage frequencies, exhibit different quiescent supply current ("IDDq") leakage rates at given temperatures and operating states, have different latencies for transitioning from a given idle operating state to an active state, etc. The CPU <NUM> communicates with multiple operational sensors (e.g., temperature sensors <NUM>) and components distributed throughout the on-chip system <NUM> of the PCD <NUM>, such as with the modem <NUM>.

In general, the modem <NUM> may be responsible for monitoring page and/or other downlink data requests requiring action and working with the application processor ("AP") <NUM> and its DRAM 112B via a PCIe communications link to process the requests. The AP <NUM> may be a heterogeneous, multi-core processor. In some embodiments, the AP <NUM> may receive GPIO signals from the modem <NUM>.

As illustrated in <FIG>, a display controller <NUM> and a touch screen controller <NUM> are coupled to the CPU <NUM>. A touch screen display <NUM> external to the on-chip system <NUM> is coupled to the display controller <NUM> and the touch screen controller <NUM>. PCD <NUM> may further include a video decoder <NUM>, e.g., a phase-alternating line ("PAL") decoder, a sequential couleur avec memoire ("SECAM") decoder, a national television system(s) committee ("NTSC") decoder or any other type of video decoder <NUM>. The video decoder <NUM> is coupled to the multi-core central processing unit ("CPU") <NUM>. A video amplifier <NUM> is coupled to the video decoder <NUM> and the touch screen display <NUM>. A video port <NUM> is coupled to the video amplifier <NUM>. As depicted in <FIG>, a universal serial bus ("USB") controller <NUM> is coupled to the CPU <NUM>. Also, a USB port <NUM> is coupled to the USB controller <NUM>. A memory <NUM> (on-chip DRAM 112B associated with AP <NUM> and off-chip Flash and/or DRAM 112A associated with MDM <NUM>) and a subscriber identity module (SIM) card <NUM> may also be coupled to the CPU <NUM> and/or AP <NUM>. Further, as shown in <FIG>, a digital camera <NUM> may be coupled to the CPU <NUM>. In an exemplary aspect, the digital camera <NUM> is a charge-coupled device ("CCD") camera or a complementary metal-oxide semiconductor ("CMOS") camera.

As further illustrated in <FIG>, a stereo audio CODEC <NUM> may be coupled to the analog signal processor <NUM>. Moreover, an audio amplifier <NUM> may be coupled to the stereo audio CODEC <NUM>. In an exemplary aspect, a first stereo speaker <NUM> and a second stereo speaker <NUM> are coupled to the audio amplifier <NUM>. <FIG> shows that a microphone amplifier <NUM> may be also coupled to the stereo audio CODEC <NUM>. Additionally, a microphone <NUM> may be coupled to the microphone amplifier <NUM>. In a particular aspect, a frequency modulation ("FM") radio tuner <NUM> may be coupled to the stereo audio CODEC <NUM>. Also, an FM antenna <NUM> is coupled to the FM radio tuner <NUM>. Further, stereo headphones <NUM> may be coupled to the stereo audio CODEC <NUM>.

<FIG> further indicates that a radio frequency ("RF") transceiver <NUM> may be coupled to the analog signal processor <NUM>. An RF switch <NUM> may be coupled to the RF transceiver <NUM> and an RF antenna <NUM>. As shown in <FIG>, a keypad <NUM> may be coupled to the analog signal processor <NUM>. Also, a mono headset with a microphone <NUM> may be coupled to the analog signal processor <NUM>. Further, a vibrator device <NUM> may be coupled to the analog signal processor <NUM>. <FIG> also shows that a power supply <NUM>, for example a battery, is coupled to the on-chip system <NUM> via a power management integrated circuit ("PMIC") <NUM>. Multiple instances of PMIC <NUM> may be dedicated to a given component(s) of the SoC such as PMIC 180A for the modem <NUM> and PMIC 180B for the AP <NUM>. In a particular aspect, the power supply <NUM> includes a rechargeable DC battery or a DC power supply that is derived from an alternating current ("AC") to DC transformer that is connected to an AC power source.

The CPU <NUM> may also be coupled to one or more internal, on-chip temperature sensors 157A and 157B as well as one or more external, off-chip temperature sensors 157C. The on-chip temperature sensors 157A, 157B may comprise one or more proportional to absolute temperature ("PTAT") temperature sensors that are based on vertical PNP structure and are usually dedicated to complementary metal oxide semiconductor ("CMOS") very large-scale integration ("VLSI") circuits. The off-chip thermal sensors 157C may comprise one or more thermistors. The temperature sensors <NUM> may produce a voltage drop that is converted to digital signals with an analog-to-digital converter ("ADC") controller <NUM>. However, other types of temperature sensors <NUM> may be employed without departing from the scope of the invention.

The temperature sensors <NUM>, in addition to being controlled and monitored by an ADC controller <NUM>, may also be controlled and monitored by one or more modem <NUM> and/or monitor module(s). The modem <NUM> and/or monitor module(s) may comprise software which is executed by the CPU <NUM>. However, the modem <NUM> and/or monitor module(s) may also be formed from hardware and/or firmware without departing from the scope of the invention.

Returning to <FIG>, any one or more of the touch screen display <NUM>, the video port <NUM>, the USB port <NUM>, the camera <NUM>, the first stereo speaker <NUM>, the second stereo speaker <NUM>, the microphone <NUM>, the FM antenna <NUM>, the stereo headphones <NUM>, the RF switch <NUM>, the RF antenna <NUM>, the keypad <NUM>, the mono headset <NUM>, the vibrator <NUM>, thermal sensors 157C, PMIC <NUM>, Flash 112A, the power supply <NUM> and the ADC controller <NUM> are external to the on-chip system <NUM>. However, it should be understood that the modem <NUM> and AP <NUM> may also receive one or more indications or signals from one or more of these external devices by way of the analog signal processor <NUM> and the CPU <NUM> to aid in the real time management of the resources operable on the PCD <NUM>.

In a particular aspect, one or more of the method steps described herein may be implemented by executable instructions and parameters stored in the memory <NUM>. The processors <NUM>, <NUM>, <NUM>, the modem <NUM>, and the DMA engine (not shown in <FIG>), the memory controllers and associated memory <NUM>, the instructions stored therein, or a combination thereof may serve as a means for performing one or more of the method steps described herein.

<FIG> is a functional block diagram illustrating an embodiment of an on-chip system for executing methods of modem stabilization when waiting for an AP-driven PCIe link reestablishment or recovery. As can be seen in the <FIG> illustration, a modem <NUM> is in communication with a multi-core <NUM> application processor <NUM>. The AP <NUM> shown in the illustration includes four cores 271A, 271B, 271C, 271D, however, it will be understood that an AP <NUM> is not limited to any specific number of cores <NUM>. Each core may have associated with it a temperature sensor <NUM> for monitoring thermal energy generation by the respective core and for triggering MHI state changes to manage thermal energy generation, power consumption, etc..

The modem <NUM> may be in communication with flash/DRAM controller and its associated DMA engine. The controllers control and manage access to data images stored in external memory (e.g., a boot image), such as Flash/NAND memory or MDM DRAM 112A. The modem <NUM> may also include internal memory registers, as would be understood by one of ordinary skill in the art. Further, the AP <NUM> may also be in communication with a DRAM memory 112B, by and through a DRAM controller, as would be understood by one of ordinary skill in the art. The DRAM 112B may contain an executing image, as would be understood by one of ordinary skill in the art. The on-chip system <NUM> may include a clock component <NUM>.

The modem <NUM> may communicate with the AP <NUM> via a PCIe bus <NUM> and according to a PCIe protocol. Depending on embodiment, the modem <NUM> may also send and receive control signals to/from the AP <NUM> via a GPIO connection <NUM>. As would be understood by one of ordinary skill in the art, the modem <NUM> may receive data requests and, via the PCIe link <NUM>, work with the AP <NUM> and AP DRAM 112B to process the data requests. The MDM's local memory may be fairly limited in size and capacity for queuing incoming data requests. As will become better understood from subsequent figures and their related description, the SoC system <NUM> illustrated in <FIG> may be configured and operable to execute methods to stabilize the modem <NUM> when it cannot process incoming data requests due to an unavailable or delayed reestablishment of an AP-driven PCIe link.

<FIG> is a functional block diagram <NUM> demonstrating the relative level of an exemplary PCIe interface <NUM> within a protocol stack that may be utilized by the AP <NUM> and MDM <NUM> of the on-chip system <NUM> illustrated in <FIG>. As previously suggested, the AP <NUM> may load a boot image from its AP RAM 112B and transfer it to the MDM modem <NUM> which may store it in its device memory for execution. The boot image transfer between the AP <NUM> and modem <NUM> may be performed between a USB host (at the AP <NUM>) and a USB device which provide a low-level transport mechanism on which higher level software may effectuate the boot image transfer using the device's upper-layer protocols. Also shown are a controller interface (HCI) layer within the AP stack for the universal serial bus (USB) interface. The modem upper layer protocols may govern the transfer of messages and packets over logical channels.

PCIe devices with a CPU, such as modem <NUM>, that require an executable software image can store their software images onboard in either a boot ROM chip or in persistent file storage mechanism (e.g., NAND/NOR flash 112A). Both of these alternatives may be cost and time inefficient. An alternate scheme is to have the device driver on the AP <NUM> memory map the device RAM and copy the software images directly into device RAM. This approach requires application processor involvement and may result in sub-optimal AP CPU throughput.

<FIG> also depicts the relative level of a PCIe interface <NUM> within the protocol stack. As would be understood by one of ordinary skill in the art, PCIe does not provide all of the low-level support provided by USB. USB supports messages and packets transfer over serial links and end points However, one advantage of PCIe is that it can provide faster throughput than USB and is scalable as the system architecture expands. Consequently, in certain circumstances, it may be desirable to implement a PCIe interface <NUM> between the host processor <NUM> and MDM <NUM> while avoiding the USB interface.

<FIG> is a functional block diagram <NUM> illustrating a functional gap in the protocol stack of <FIG>. <FIG> illustrates a computing device, such as on-chip system <NUM>, that uses a PCIe interface <NUM> as a memory-mapped communication path between a host processor, such as AP <NUM>, and a modem <NUM>. As shown, there is a functional gap between the low-level PCIe interface <NUM> and upper layer protocols. For example, the standard PCIe interface <NUM> may fail to provide sufficient support to implement data transfer from the AP <NUM> to the modem <NUM> without significant involvement from a core of the AP <NUM>.

<FIG> is a functional block diagram <NUM> illustrating a modem-host interface ("MHI") deployed within the functional gap illustrated in <FIG>. In general, the modem-host interface provides logical channels over a memory-mapped communication path such as a PCIe link. The logical channels enable transport of upper layer cellular modem communication protocols (e.g., <NUM>, <NUM>, <NUM>, <NUM> and LTE protocols) from the modem <NUM> to the host AP <NUM>. Moreover, commands may be issued between the host AP <NUM> and the cellular-communication modem (MDM) <NUM> and a power state may also be communicated and managed via one or more of the logical channels. In addition, the modem-host interface functions to offload the task of downloading software executable images to a PCIe device, such as modem <NUM>. The modem <NUM> may accomplish software image download via a hardware-accelerated mechanism (e.g., an enhanced direct memory access (DMA) Engine <NUM>) using data buffers allocated in the RAM <NUM>. That is, a shared memory space may be used to transfer the boot image between the host AP <NUM> and MDM modem <NUM>.

A communication link (e.g., PCIe <NUM>) device driver enumerates the MDM <NUM> and allocates direct memory access data buffers in the AP RAM 212B. The location (address) of the DMA buffer list may be communicated to the modem <NUM> via memory mapped configuration registers, as would be understood by one of ordinary skill in the art. Moreover, a doorbell located in application logic of the modem <NUM> may be leveraged by the host AP <NUM> to trigger the processing of new transactions by the modem <NUM> (reference back to this particular operational scenario will be made in regards to the <FIG> illustration). Upon completion, the modem <NUM> triggers an interrupt (e.g., PCIe interrupt) towards the host AP <NUM> for further processing.

In operation, upon reset/power-up, the modem <NUM> executes its primary boot loader (PBL) from the hardware boot ROM (small read-only on-chip memory). The PBL then downloads executable code from the AP RAM 212B into the MDM RAM 212A over a memory-mapped communication path <NUM> (e.g., PCIe) via a hardware accelerated DMA mechanism using the data buffers programmed by the AP <NUM> in the configuration registers. The DMA engine <NUM> communicates read/write completion via events/interrupts back to the AP <NUM>. DMA buffer recycling may be handled by the host AP <NUM> upon receipt of the read/write completion events. Once the MDM <NUM> executable image is downloaded into the MDM RAM 212A and authenticated, the MDM boot ROM code jumps into that image and starts executing the main MDM boot program from RAM. Similarly for RAM dumps, the MDM <NUM> uploads RAM dump regions from MDM RAM 212A into the host AP RAM 212B using a similar hardware accelerated mechanism. In one exemplary implementation, the modem-host protocol (flashless boot over high-speed inter-chip HSIC) may be implemented using the proposed hardware accelerated mechanism as a transport medium. In the case where the MDM <NUM> is realized by a modem chip, the application logic may be a modem subsystem or a packet processing component.

<FIG> is an MHI power state machine diagram <NUM> identifying the state scenario <NUM> in which embodiments of the solution for modem stabilization when waiting for an AP-driven PCIe link recovery may be employed. Briefly referring back to the <FIG> description, a doorbell located in application logic of the modem <NUM> may be leveraged by the host AP <NUM> to trigger the processing of new transactions by the modem <NUM>. Upon completion, the modem <NUM> triggers a PCIe interrupt towards the host AP <NUM> for further processing. Notably, however, a problem may arise in the state scenario <NUM> when the host AP <NUM> is unavailable to change its state and provide the modem <NUM> with a PCIe link to process the new transactions. In such a scenario, the modem <NUM> may be "stuck" in a D3cold state and unable to transition back to the running state shown in <NUM> as it waits on the AP <NUM> to reestablish a PCIe link. Meanwhile, data packets associated with new transactions may continue to queue up in the limited memory associated with modem <NUM> (the modem <NUM> won't process the transactions without being triggered by the AP <NUM>, as required per the PCIe protocol). An overflow of data packets may result in an undesirable crash of modem <NUM>, thereby generating a poor user experience. Advantageously, embodiments of the solution work to address such a situation within state scenario <NUM> without violating PCIe protocol.

<FIG> is a flowchart illustrating a first method (<NUM>) not according to the invention for modem stabilization in a SoC when waiting for an AP-driven PCIe communications link reestablishment. Beginning at block <NUM>, the method <NUM> may determine that the AP <NUM> is in an MHI sleep state. The modem <NUM> may also be in a sleep state, such as a D3cold state. In such a situation, as previously described, data packets may be arriving at the modem <NUM> for processing, however, the modem <NUM> may not be available for processing unless and until the AP <NUM> transitions out of its present state and establishes (or, more likely, reestablishes) a PCIe communications link with modem <NUM>. With a PCIe communications link <NUM> established, the modem <NUM> may transition out of the D3 state and into a D0 state for processing the workloads, per the PCIe protocol.

The method <NUM> continues to decision block <NUM>. At decision block <NUM>, the method <NUM> may determine whether a downlink data packet has arrived at modem <NUM> for processing. If no downlink data packet has arrived, the "no" branch may be followed to block <NUM> and the system safely transitioned to an X0 sleep mode (system "off"). From there, the method <NUM> returns. If at decision block <NUM> it is determined, however, that a downlink data packet has arrived at the modem <NUM> for processing, the "yes" branch may be followed to subsequent decision block <NUM>.

At decision block <NUM>, the method <NUM> determines whether there is modem-associated memory capacity available for holding the data packet. If there is capacity available, the "yes" branch is followed to block <NUM> and the data packet is queued for future processing when the PCIe link <NUM> is reestablished. The method <NUM> returns and the modem <NUM> continues to wait for the AP <NUM> to establish the communications link. If, however, at decision block <NUM> it is determined that there is insufficient modem-associated memory capacity to hold the incoming data packet, the "no" branch is followed to block <NUM> and the data packet is dropped before the system is transitioned to X0 at block <NUM>. In this way, the method <NUM> avoids overflow of data into the modem-associated memory while the modem <NUM> is unavailable for processing a workload due to no available PCIe link. And, advantageously, a crash of modem <NUM> may be avoided.

<FIG> is a flowchart illustrating a second exemplary method <NUM> for modem stabilization in a SoC when waiting for an AP-driven PCIe communications link reestablishment. Beginning at block <NUM>, the method <NUM> may determine that the AP <NUM> is in an MHI sleep state. The modem <NUM> may also be in a sleep state, such as a D3cold state. In such a situation, as previously described, data packets may be arriving at the modem <NUM> for processing, however, the modem <NUM> may not be available for processing unless and until the AP <NUM> transitions out of its present state and establishes (or, more likely, reestablishes) a PCIe communications link with modem <NUM>. With a PCIe communications link <NUM> established, the modem <NUM> may transition out of the D3 state and into a D0 state for processing the workloads, per the PCIe protocol.

At decision block <NUM>, the method <NUM> determines whether there is modem-associated memory capacity available for holding the data packet. If, at decision block <NUM>, it is determined that there is insufficient modem-associated memory capacity to hold the incoming data packet, the "no" branch is followed to block <NUM> and the data packet is dropped before the system is transitioned to X0 at block <NUM>. If, at decision block <NUM>, there is capacity available, the "yes" branch is followed to decision block <NUM> and the method <NUM> determines whether a link-recovery threshold timer <NUM> has expired. If the timer has expired, the "yes" branch is followed to block <NUM> and the packet is dropped before the system is transitioned to X0 at block <NUM>, even though pending queue capacity in the modem-associated memory is available. If the timer has not expired, however, then the method <NUM> follows the "no" branch from decision block <NUM> to block <NUM>. At block <NUM>, the data packet is queued for future processing when the PCIe link <NUM> is reestablished. The method <NUM> returns and the modem <NUM> continues to wait for the AP <NUM> to establish the communications link. In this way, the method <NUM> avoids overflow of data into the modem-associated memory while the modem <NUM> is unavailable for processing a workload due to no available PCIe link. And, advantageously, a crash of modem <NUM> may be avoided.

<FIG> is a flowchart illustrating a third exemplary method <NUM> for modem stabilization in a SoC when waiting for an AP-driven PCIe communications link reestablishment. Beginning at block <NUM>, the method <NUM> may determine that the AP <NUM> is in an MHI sleep state. The modem <NUM> may also be in a sleep state, such as a D3cold state. In such a situation, as previously described, data packets may be arriving at the modem <NUM> for processing, however, the modem <NUM> may not be available for processing unless and until the AP <NUM> transitions out of its present state and establishes (or, more likely, reestablishes) a PCIe communications link with modem <NUM>. With a PCIe communications link <NUM> established, the modem <NUM> may transition out of the D3 state and into a D0 state for processing the workloads, per the PCIe protocol.

At decision block <NUM>, the method <NUM> determines whether there is modem-associated memory capacity available for holding the data packet. If, at decision block <NUM>, it is determined that there is insufficient modem-associated memory capacity to hold the incoming data packet, the "no" branch is followed to block <NUM> and a wake interrupt is driven to the AP <NUM>. Next, at decision block <NUM> it is determined whether the PCIe communications link is reestablished. If the link is not reestablished, the "no" branch is followed to decision block <NUM> and a threshold counter establishing a maximum number of wakeup attempts (WAKE# signals) to the AP <NUM> is consulted. If the wakeup threshold counter indicates that the maximum allowed number of wakeup attempts has not been reached, the "no" branch is followed from decision block <NUM> back to block <NUM> where a next WAKE# is driven to the AP <NUM>. The method <NUM> may continue to loop through blocks <NUM>, <NUM> and <NUM> in this way until either the PCIe link is recovered or the wakeup threshold is reached.

If the wakeup threshold is reached at decision block <NUM>, the "yes" branch is followed to block <NUM> and the data packet is dropped before the system is transitioned to X0 at block <NUM>. Alternatively, if the PCIe link is reestablished by the AP <NUM> in response to a WAKE# signal driven to the AP <NUM>, the "yes" branch is followed from decision block <NUM> to block <NUM> where the modem <NUM> is transitioned to a mission mode D0 for processing workloads. With the modem <NUM> in mission mode, the method <NUM> may move to block <NUM> to retrieve the data packet for processing.

Returning back to decision block <NUM>, if there is pending queue capacity available in modem-associated memory, the method <NUM> may follow the "yes" branch to decision block <NUM>. At decision block <NUM> the method <NUM> determines whether a link-recovery threshold timer <NUM> has expired. If the timer has expired, the "yes" branch is followed to block <NUM> and a WAKE# is driven to AP <NUM> - the method <NUM> proceeds from block <NUM> as previously described. If, however, the timer has not expired, the method <NUM> may follow the "no" branch from decision block <NUM> to block <NUM>. At block <NUM>, the data packet is queued for future processing when the PCIe link <NUM> is reestablished. The method <NUM> returns and the modem <NUM> continues to wait for the AP <NUM> to establish the communications link. In these ways, the method <NUM> avoids overflow of data into the modem-associated memory while the modem <NUM> is unavailable for processing a workload due to no available PCIe link. And, advantageously, a crash of modem <NUM> may be avoided.

<FIG> is a flowchart illustrating a fourth exemplary method <NUM> for modem stabilization in a SoC when waiting for an AP-driven PCIe communications link reestablishment. Beginning at block <NUM>, the method <NUM> may determine that the AP <NUM> is in an MHI sleep state. The modem <NUM> may also be in a sleep state, such as a D3cold state. In such a situation, as previously described, data packets may be arriving at the modem <NUM> for processing, however, the modem <NUM> may not be available for processing unless and until the AP <NUM> transitions out of its present state and establishes (or, more likely, reestablishes) a PCIe communications link with modem <NUM>. With a PCIe communications link <NUM> established, the modem <NUM> may transition out of the D3 state and into a D0 state for processing the workloads, per the PCIe protocol.

At decision block <NUM>, the method <NUM> determines whether there is modem-associated memory capacity available for holding the data packet. If, at decision block <NUM>, it is determined that there is insufficient modem-associated memory capacity to hold the incoming data packet, the "no" branch is followed to block <NUM> and a GPIO toggle is driven to the AP <NUM>. Next, at decision block <NUM> it is determined whether the PCIe communications link is reestablished. If the link is not reestablished, the "no" branch is followed to decision block <NUM> and a threshold counter establishing a maximum number of GPIO toggle attempts to the AP <NUM> is consulted. If the toggle threshold counter indicates that the maximum allowed number of GPIO toggle attempts has not been reached, the "no" branch is followed from decision block <NUM> back to block <NUM> where a next GPIO toggle is driven to the AP <NUM>. The method <NUM> may continue to loop through blocks <NUM>, <NUM> and <NUM> in this way until either the PCIe link is recovered or the toggle threshold is reached.

If the GPIO toggle threshold is reached at decision block <NUM>, the "yes" branch is followed to block <NUM> and the data packet is dropped before the system is transitioned to X0 at block <NUM>. Alternatively, if the PCIe link is reestablished by the AP <NUM> in response to a GPIO toggle driven to the AP <NUM>, the "yes" branch is followed from decision block <NUM> to block <NUM> where the modem <NUM> is transitioned to a mission mode D0 for processing workloads. With the modem <NUM> in mission mode, the method <NUM> may move to block <NUM> to retrieve the data packet for processing.

Returning back to decision block <NUM>, if there is pending queue capacity available in modem-associated memory, the method <NUM> may follow the "yes" branch to decision block <NUM>. At decision block <NUM> the method <NUM> determines whether a link-recovery threshold timer <NUM> has expired. If the timer has expired, the "yes" branch is followed to block <NUM> and a GPIO toggle is driven to AP <NUM> - the method <NUM> proceeds from block <NUM> as previously described. If, however, the timer has not expired, the method <NUM> may follow the "no" branch from decision block <NUM> to block <NUM>. At block <NUM>, the data packet is queued for future processing when the PCIe link <NUM> is reestablished. The method <NUM> returns and the modem <NUM> continues to wait for the AP <NUM> to establish the communications link. In these ways, the method <NUM> avoids overflow of data into the modem-associated memory while the modem <NUM> is unavailable for processing a workload due to no available PCIe link. And, advantageously, a crash of modem <NUM> may be avoided.

Certain steps in the processes or process flows described in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the invention. In some instances, certain steps may be omitted or not performed without departing from the invention. Further, words such as "thereafter", "then", "next", etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the exemplary method.

Additionally, one of ordinary skill in programming is able to write computer code or identify appropriate hardware and/or circuits to implement the disclosed invention without difficulty based on the flow charts and associated description in this specification, for example. Therefore, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary for an adequate understanding of how to make and use the invention. The inventive functionality of the claimed computer implemented processes is explained in more detail in the above description and in conjunction with the drawings, which may illustrate various process flows.

In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. By way of example, and not limitation, such computer-readable media may comprise random-access memory ("RAM"), read-only memory ("ROM"), EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.

For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line ("DSL"), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

Claim 1:
A method (<NUM>, <NUM>, <NUM>) for modem stabilization, the method comprising:
determining that an application processor, AP, is in a sleep state, wherein the AP and a modem are operable to communicate over a peripheral component interconnect express, PCIe, channel;
determining (<NUM>, <NUM>, <NUM>) that no active link is available over the PCIe channel;
monitoring a PCIe link recovery timer;
recognizing (<NUM>, <NUM>, <NUM>) that a data packet is available in a workload queue for processing by a modem; and
determining (<NUM>, <NUM>, <NUM>) an available queue capacity in a memory component associated with the modem, wherein:
if the available queue capacity is adequate to store the data packet, storing (<NUM>, <NUM>, <NUM>) the data packet in the available queue capacity for later processing, wherein the data packet is dropped from the workload queue if the PCIe link recovery timer has exceeded a predefined threshold, and wherein the data packet is stored in the available queue capacity for later processing if the PCle link recovery timer has not exceeded the predefined threshold; and
if the available queue capacity is inadequate to store the data packet, dropping (<NUM>, <NUM>, <NUM>) the data packet from the workload queue.