Patent Description:
Certain electronic systems can include a plurality of processing channels. For example, processing channels in radio systems can include transmit channels and receive channels. As electronic systems are being scaled up to include more processing channels, controlling the various processing channels can become more difficult. Some previous ways of configuring the processing channels can encounter difficulties in scaling for electronic systems that include more processing channels. Such difficulties can include increased design complexity, among other things.

Patent Publication No. <CIT> describes a programmable digital signal processor including a clustered SIMD microarchitecture configured to execute complex vector instructions. The programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Patent Publication No. <CIT> discloses a data processing unit combining a scalar processor and a heterogeneous processor which includes a vector processing array. The vector processing array includes a plurality of vector processors which are operable in a single instruction multiple data configuration. <NPL> discloses a method for modeling a generic orthogonal frequency division multiplexing wireless transceiver on the Zync system-on-chip by decomposing the standard specifications into a set of functional blocks used in multiple protocols.

The invention is defined in the appended independent claims. Dependent claims define optional further specifications of the invention.

The drawings and the associated description herein are provided to illustrate specific embodiments of the disclosure and are not intended to be limiting.

The following detailed description presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in a multitude of different ways, for example, as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals can indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims.

The disclosed technology relates to a stream processor system that includes parallel programmable processors, which can be referred to as stream processors or threads. Methods of controlling the stream processor system are also disclosed. Each of the stream processors can read, write, poll, and/or perform other suitable operations from different register sets. The stream processors can be implemented in a radio context, such as in a transceiver chip for a base station. The disclosed technology can also be applied to other applications, such as high speed converters (e.g., high speed analog-to-digital converters and/or high speed digital-to-analog converters). In the radio context, more and more radio frequency channels are being used. For example, some previous parts had <NUM> transmit (Tx) channels and <NUM> receive (Rx) channels. Some current designs are including <NUM> Tx channels and <NUM> Rx channels, and future parts may include <NUM> Tx channels and <NUM> Rx channels. The stream processing architecture described herein allows control functions, such as setting values in hardware registers to control radio operations, in such systems to be more scalable than existing solutions.

Aspects of this disclosure relate to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an advanced reduced instruction set computer machine (ARM) processor, configured to execute main processor instructions and a plurality of processing channels. Each of the processing channels can include a co-processor, such as a stream processor, configured to execute co-processor instructions. The co-processors can execute instructions having a lower latency than the main processor instructions.

Each of the co-processors can execute a set of instructions received in response to a trigger received at a respective trigger interface. The trigger interface can receive and input signal from external to the distributed processing system, such as from a baseband processor. The set of instructions can include an instruction to access a resister of a respective processing channel. The co-processors in the respective processing channels can receive another trigger from a main co-processor and/or an ARM processor and execute a different set of instructions in response to the other trigger. The co-processors can execute instructions in parallel with each other. Each of the co-processors can send an interrupt to the main processor. The interrupt can be provided via a dedicated signal line. The co-processors can be re-configurable.

The distributed processing system can be included in a radio system to configure radio channels for operation. This can involve configuring analog circuit components for processing a radio frequency signal. The processing channels can include transmit channels, receive channels, and observation receive channels. The distributed processing system can receive a high level command and write at least a hundred registers in the processing channels to be written in response to the high level command.

Although embodiments discussed herein may be described with reference to stream processors and an ARM processor, any suitable principles and advantages disclosed herein can be implemented in a distributed processing system that includes a main processor and co-processors. The main processor can execute instructions with longer latency and the co-processors can execute instructions with lower latency. For example, the main processor can be an ARM processor, such as an ARM M3 processor or an ARM M4 processor, and co-processors can execute instructions with lower latency than the instructions executed by the ARM processor. The main processor can execute more computation intensive instructions and the co-processors can execute less computation intensive instructions. The co-processors can be reconfigurable. Example co-processors include, but are not limited to, stream processors, any other suitable processors that can perform functions similar to some or all of the functionality of any of the stream processors disclosed herein, or the like. Example main processors, but are not limited to, ARM processors, any other suitable processors that can perform functions similar to some or all of the functionality of any of the ARM processors disclosed, or the like.

<FIG> is a schematic block diagram of an example stream processor system <NUM> for radio applications according to an embodiment. The stream processor system <NUM> can receive external commands and manage the timing of register transactions. A single command received by the stream processor system can trigger thousands of register writes in certain instances. Stream processors of the stream processor system <NUM> can manage real time control of registers. The stream processors of the stream processor system <NUM> can control radio events and channel enabling and/or disabling.

The stream processor system <NUM> of <FIG> includes a digital core <NUM>, receive channels 14a to 14d, transmit channels 16a to 16d, and observation channels 18a to 18b. The digital core <NUM> includes an ARM processor <NUM>, a main stream processor <NUM>, a stream trigger interface <NUM> for the main stream processor <NUM>, and memory <NUM> for the digital core <NUM>. The stream trigger interface <NUM> can be any suitable interface, such as a serial peripheral interface (SPI). The stream trigger interface <NUM> can include any suitable digital circuitry.

The stream processor system <NUM> includes <NUM> stream processors that are all communicatively coupled to the ARM processor <NUM>. The stream processor system <NUM> has a stream parallel processing arrangement. As illustrated in <FIG>, the <NUM> stream processors can include <NUM> stream processors <NUM> for receive channels 14a to 14d, <NUM> stream processors <NUM> for transmit channels 16a to 16d, <NUM> stream processors <NUM> for observation channels 18a to 18b, and <NUM> main stream processor <NUM>. The ARM processor <NUM> can be an M4 ARM processor, for example. The stream processors <NUM>, <NUM>, <NUM>, and <NUM> and the ARM processor <NUM> can be implemented on a monolithic integrated circuit. A microcontroller can include the stream processors <NUM>, <NUM>, <NUM>, and <NUM> and the ARM processor <NUM>. A transceiver integrated circuit can include the illustrated stream processor system <NUM>.

As shown in <FIG>, all of the <NUM> stream processors <NUM>, <NUM>, <NUM>, and <NUM> are connected to the ARM processor <NUM>. The stream processors <NUM>, <NUM>, <NUM>, and <NUM> can communicate with the ARM processor <NUM> without data passing through an intermediate processor. Each of the stream processors <NUM>, <NUM>, <NUM>, and <NUM> can be in communication with the ARM processor <NUM> by way of a dedicated signal line. As illustrated, each of the stream processors <NUM>, <NUM>, <NUM>, and <NUM> has a dedicated signal line to provide an interrupt to the ARM processor <NUM>. The stream processors <NUM>, <NUM>, <NUM>, and <NUM> can receive respective stream triggers from the ARM processor <NUM>. In addition, the <NUM> stream processors <NUM>, <NUM>, and <NUM> are also connected to the main stream processor <NUM>. The <NUM> stream processors <NUM>, <NUM>, and <NUM> can receive triggers from the main stream processor <NUM>.

The stream processors <NUM>, <NUM>, and <NUM> can be referred to as auxiliary stream processors or slice stream processors. Each of these stream processors is included in a processing channel, such as a transmit channel, a receive channel, or an observation channel. Each auxiliary stream processor <NUM>, <NUM>, and <NUM> can access the registers <NUM>, <NUM>, and <NUM>, respectively, in its respective processing channel. As an example, a transmit slice processor <NUM> can access registers <NUM> that include transmit slice registers, transmit analog sub map registers, digital-to-analog converter (DAC) registers, the like, or suitable any combination thereof. To access registers in another processing channel or in the digital core <NUM>, an auxiliary stream processor can trigger a corresponding stream in the main stream processor <NUM>. For instance, a trigger mechanism in an auxiliary stream processor can provide a RETURN opcode to trigger a corresponding stream in the main stream processor <NUM>. The auxiliary stream processors <NUM>, <NUM>, and <NUM> that can be controlled by the main stream processor <NUM>.

The main stream processor <NUM> can be referred to as a core stream processor. The main stream processor <NUM> can have access to all hardware registers. Each of the auxiliary stream processors <NUM>, <NUM>, and <NUM> has access to a respective group of dedicated hardware registers. Each auxiliary stream processor <NUM>, <NUM>, and <NUM> can provide an interrupt to the ARM processor <NUM>. Each auxiliary stream processor <NUM>, <NUM>, and <NUM> can provide an interrupt to the main stream processor <NUM>. Each auxiliary stream processor <NUM>, <NUM>, <NUM> has a respective stream trigger interface <NUM>, <NUM>, <NUM> configured to receive a signal from a baseband processor, which can allow external access to an auxiliary stream processor <NUM>, <NUM>, <NUM>. The stream trigger interface <NUM>, <NUM>, <NUM> for each auxiliary stream processor <NUM>, <NUM>, <NUM> can also receive a signal from the main stream processor <NUM>. The stream trigger interfaces can be any suitable interfaces, such as SPI interfaces. The stream trigger interfaces can include any suitable digital circuitry.

The stream parallel processing arrangement can be implemented in the radio context. For example, as illustrated in <FIG>, each auxiliary stream processor <NUM>, <NUM>, <NUM> can be for a radio frequency channel, such as a receive channel, a transmit channel, or an observation channel. The auxiliary stream processors can configure hardware registers for radio operation.

The receive channels 14a to 14d include digital circuitry arranged to configure analog components in a receiver of a radio. The receive channels 14a to 14d each include a stream processor <NUM>, a stream trigger interface <NUM>, registers <NUM>, radio event contacts <NUM>, and memory <NUM> for the stream processor <NUM>. The memory <NUM> can be random access memory (RAM). The memory <NUM> can store op codes and data for writing to registers <NUM>. The receive channels 14a to 14d can configure a radio for receiving radio frequency signals.

The transmit channels 16a to 16d include digital circuitry arranged to configure analog components in a transmitter of a radio. The transmit channels 16a to 16d each include a stream processor <NUM>, a stream trigger interface <NUM>, registers <NUM>, radio event contacts <NUM>, and memory <NUM> for the stream processor <NUM>. The memory <NUM> can be RAM. The memory <NUM> can store op codes and data for writing to registers <NUM>. The transmit channels 16a to 16d can configure the radio for transmitting radio frequency signals.

The observation channels 18a to 18b include digital circuitry arranged to configure analog components in observation receive paths of a radio. The observation channels 18a to 18b each include a stream processor <NUM>, a stream trigger interface <NUM>, registers <NUM>, radio event contacts <NUM>, and memory <NUM> for the stream processor <NUM>. The memory <NUM> can be RAM. The memory <NUM> can store op codes and data for writing to registers <NUM>. The observation channels 18a to 18b can configure the radio for observing radio frequency signals.

The stream processor system <NUM> of <FIG> can implement one or more of the following advantages, among others. The stream processor system <NUM> can implement increased programmability/configurability relative to other systems. For example, even after tape out, modifications can be made that allow for customer specific implementations, such as different power up sequences.

The stream processor system <NUM> can achieve increased robustness relative to other systems. For example, the stream processors <NUM>, <NUM>, <NUM>, and <NUM> typically do not crash and can allow for the radio to stay on even if the ARM processor <NUM> crashes. A baseband processor can provide an input signal to a stream processor via a respective stream trigger interface so that the baseband processor can trigger streams even when the ARM processor <NUM> is non-operational.

The stream processor system <NUM> can have improved response time and latency relative to other systems. For example, time critical tasks relating to start-up, transmit, receive, adjustments for overloaded data converters, attenuation changes, power amplifier protection, and/or the like can be performed more quickly and reliably by the stream processor system <NUM> relative to other systems. Such tasks can be implemented with a fixed and relatively low latency. The latency can be unchanged even as more channels are implemented in a radio system. With the stream processors discussed herein, latency for executing instructions can be deterministic. In some instances, all instructions executed by the stream processor system <NUM> can have a deterministic latency.

A relatively high level command can trigger relatively complex streams of control that can be managed by the stream processor system. This can enable an external system to control the stream processing system <NUM> with relatively minimal input.

The stream processing system <NUM> can efficiently handle interrupts. Interrupts can be queued such that if a second interrupt for an auxiliary stream processor <NUM>, <NUM>, or <NUM> is received while the auxiliary stream processor is handling a first interrupt, the second interrupt is not lost.

A stream processor, such as any of the stream processors of the stream processor system <NUM>, can include a program counter (PC) register and/or a data pointer (DP) register to point to locations in memory for an ARM processor. The stream processor can be activated by a writing a particular command to a register of the ARM processor. During operation, the stream processor can successively fetch program words pointed to by the PC and/or data words pointed to by the DP. These fetched words can be stored to a cache for the stream processor. The stream processor can include architectural registers (e.g., <NUM><NUM>-bit architectural registers), which can be used to provide address and/or data fields. This can save data memory when data is repeated and/or has a relatively simple pattern. A loop instruction can allow counted loops to be realized in program memory. The stream processor can execute instructions to perform one or more of the following operations: arithmetic on data stored in one or more architectural registers, wait for calibration, interrupt the ARM processor, or check register values.

A stream processor can implement various instructions. As an example, certain stream processors can implement <NUM> instructions. A first type of instructions can be hard wired on the stream processor. The first type of instructions can have dedicated contacts, such as pins, connected to dedicated circuitry arranged to execute such instructions. The first type of instructions can be received at one or more contacts of radio events contacts <NUM>, <NUM>, and/or <NUM>. Instructions with one or more dedicated contacts and/or hardware can be for relatively important and/or time sensitive instructions. For example, instructions to turn ON a receive channel, turn OFF a receive channel, turn ON a transmit channel, turn OFF a transmit channel, and the like are examples of instructions of the first type of instructions. In the example where certain stream processors are arranged to execute <NUM> instructions, about <NUM> instructions can be implemented with dedicated circuitry arranged to efficiently implement those instructions in certain instances.

The stream processor can implement a second type of instructions, which are unmapped to specific circuitry of the stream processor, using a serial peripheral interface (SPI) register and circuitry of the stream processor. The second type of instructions can be triggered via a stream trigger interface <NUM>, <NUM>, <NUM>, or <NUM>. The first type of instructions and the second type of instructions can make up most or all of the instructions that the stream processor is arranged to execute.

The auxiliary stream processors <NUM>, <NUM>, and <NUM> can each provide an event trigger to the main stream processor <NUM> via a dedicated signal line. The event triggers can provide interrupts to the main stream processor <NUM>. Any suitable number of auxiliary stream processors can be implemented in accordance with the principles and advantages discussed herein. For example, one auxiliary stream processor can be provided per channel as illustrated in <FIG>.

As shown in <FIG>, one stream processor is included in each transmit channel 16a to 16d, receive channel 14a to 14d, and observe channel 18a to 18b. In certain instances, all receive and transmit channels can be turned ON and OFF, respectively, at approximately the same time. Each slice stream processor can have unfettered access to a respective memory, such as captive random access memory (RAM). The stream processors can still function if the ARM <NUM> crashes, and the radio can still function. The main stream processor <NUM> is included in the digital core <NUM>. Separate interfaces for baseband processor (BBP) and ARM <NUM> can prevent conflicts and/or race conditions.

There can typically be more than <NUM> regular controls for a radio. The registers that store these controls should be properly configured for the radio to function as desired. The configuration of these registers can change relatively often, such as between time-division duplexing (TDD) transmit and/or receive operations.

In order to streamline the process of configuring radio registers and to implement such functionality in a manner that is transparent to external hardware, sequences that drive the stream processors can be implemented by a high level command. For example, a turn ON command, such as a radio turn ON command, can be provided to the stream processor system <NUM> to implement a startup process. Streams are also capable of implementing delays and deferred processing. Streams can be used to bring up or down a channel in power sequence operations to avoid transients on the radio frequency (RF) output and/or the power supplies. Using auxiliary stream processors to perform register writes can take advantage of the speed of an internal register bus.

In the stream processor system <NUM> shown in <FIG>, a relatively large number (e.g., hundreds or thousands) of writes to registers to control the radio can be abstracted to a relatively simple command. Events in the radio can trigger relatively complex responses from the stream processors in real time. Radio channels can be simultaneously controlled in response to inputs to the stream processor system <NUM>. Timing and sequencing of analog controls can be determined in firmware associated with the part and abstracted away from external (e.g., customer) control specifications.

The stream parallel processing arrangement can have a streamlined startup sequence. A high level command, such as a radio turn ON command, can be provided to the stream processing system <NUM>. Hundreds or thousands of register writes can be performed in response to a single high level command. A baseband processor can provide the high command to the stream processor system <NUM>. The stream processors <NUM>, <NUM>, <NUM>, and <NUM> can execute a startup process in response to the high level command. This can involve the stream processors <NUM>, <NUM>, <NUM>, and <NUM> setting radio configuration registers <NUM>, <NUM>, and/or <NUM>.

Other example high level commands include, but are not limited to, commands to change configuration of a digital pre-distortion (DPD) path, commands to update filter coefficients for a receiver and/or a transmitter, commands to update a local oscillator frequency, commands to turn ON a radio channel, commands to turn OFF a radio channel, or the like. As an example, a high level command to change configuration of the DPD path can involve triggering a transmit stream, interrupting the main stream processor <NUM>, and then interrupting the ARM processor <NUM>. As another example, a high level command to change local oscillator frequency can be provided in association with the radio changing from a transmit mode to a receive mode. A stream can be triggered in the main stream processor <NUM> that can trigger a change in local oscillator frequency.

High level commands can be executed by several instructions executed in parallel by the stream processor system <NUM>. As an example, receive filter coefficients for a plurality of receive channels and/or transmit filter coefficients for a plurality of transmit channels can be updated in parallel. The stream processor system <NUM> enabling these commands to be executed in parallel can be a significant advantage to having such commands execute in serial. As another example, two high level commands can be provided and executed in parallel with the stream processor system <NUM>. For instance, a configure DPD command and an update filter coefficients command can be received. Related streams can be executed in parallel in the stream processor system <NUM>.

The stream processor system <NUM> divides processing between the ARM processor <NUM> and the stream processors <NUM>, <NUM>, <NUM>, and <NUM>. The ARM processor <NUM> can execute instructions with longer latency (e.g., a relatively long calibration) and stream processors <NUM>, <NUM>, <NUM>, and <NUM> can execute instructions with lower latency (e.g., instructions that can respond in real time). The stream processing system <NUM> can receive input signals at different interfaces for executing instructions on the ARM processor <NUM> and the stream processors.

Stream processors <NUM>, <NUM>, <NUM>, and/or <NUM> can process timing sensitive and/or critical instructions. The stream processors <NUM>, <NUM>, <NUM>, <NUM> can process other lower latency instructions. The stream processors <NUM>, <NUM>, <NUM>, <NUM> can execute instructions in response to an input signal received at stream trigger interface. Such instructions can be executed by circuitry configured to execute a variety of instructions. The stream processors <NUM>, <NUM>, <NUM> can execute instructions in response to an input signal received at radio event contacts. Such instructions can be executed by dedicated hardware configured to execute the instructions. Each processing channel (e.g., transmit channel, receive channel, or observation channel) can be controlled by the main stream processor <NUM> and/or an auxiliary stream processor <NUM>, <NUM>, or <NUM>.

The ARM processor <NUM> can execute computationally intensive tasks and/or tasks that are not time sensitive. The ARM processor <NUM> can execute instructions for which there is significant latency for data being ready. The ARM processor <NUM> can execute instructions in response to an input signal received by a bus for the ARM processor <NUM>. The bus can be an Advanced Microcontroller Bus Architecture High-performance Bus (AHB), for example. The ARM processor <NUM> can execute instructions in response to an interrupt received from the main stream processor <NUM> or any of the slice stream processors <NUM>, <NUM>, or <NUM>. The stream processors <NUM>, <NUM>, <NUM>, and <NUM> can process radio configuration control data. The ARM processor <NUM> can process other data, such as input data. When there are multiple requests at a given time, the main stream processor <NUM> can queue the requests without arbitration.

Streams can be triggered a variety of ways in the stream processor system <NUM>. The main stream processor <NUM> can trigger a stream through a stream trigger interface <NUM>, <NUM>, <NUM>, or <NUM>. An example processes of the main stream processor <NUM> triggering a stream through a stream trigger interface will be described with reference to <FIG>.

A baseband processor (BBP) can trigger a stream through a stream trigger <NUM>, <NUM>, <NUM>, or <NUM>. An example process of a BBP triggering a stream through a stream trigger interface will be described with reference to <FIG>.

A slice stream processor can trigger a stream in the main stream processor <NUM>. Such a stream can be triggered via a dedicated signal line between the slice stream processor and the main stream processor <NUM>. An example process of a slice stream processor triggering a main stream processor will be described with reference to <FIG>.

A slice stream processor can trigger the ARM processor <NUM> via an interrupt. An example process of a slice stream processor providing an interrupt to the ARM processor will be described with reference to <FIG>.

The main stream processor <NUM> can trigger the ARM processor <NUM> via an interrupt. An example process of the main stream processor <NUM> providing an interrupt to the ARM processor will be described with reference to <FIG>.

The ARM processor <NUM> can trigger a stream in any of the stream processors <NUM>, <NUM>, or <NUM>. The ARM processor <NUM> can receive a trigger via a bus for the ARM processor <NUM> (not illustrated in <FIG>). Example processes of the ARM processor <NUM> triggering a stream will be described with reference to <FIG> and <FIG>.

A stream can be triggered through radio event contacts <NUM>, <NUM>, or <NUM>. Radio events can trigger one or more streams on slice stream processors. The radio events can be turning on a transmitter, turning on a receiver, or turning on an observation receiver, for example. A pin control interface can trigger such streams. The pin control interface can provide the stream trigger to radio event contacts <NUM>, <NUM>, or <NUM> to trigger a stream on the stream processor. An example process a radio event triggering a stream on a slice stream processors will be described with reference to <FIG>.

<FIG> is a schematic diagram of a radio system <NUM> that includes a digital signal processor <NUM> with a distributed processing system according to an embodiment. The radio system <NUM> can be implemented on an integrated circuit. The radio system <NUM> can be included in a base station. As illustrated, the radio system <NUM> includes a digital signal processor <NUM>, receivers 64a to 64d, transmitters 66a to 66d, an observation path <NUM>, and a loopback circuit <NUM> coupled between transmitters 66a to 66d and the observation path <NUM>.

The digital signal processor <NUM> can include a digital core, digital transmit channels, digital receive channels, and digital observation channels. The digital signal processor <NUM> can implement any suitable combination of features discussed with reference to <FIG>. For example, the digital signal processor <NUM> can include the stream processor system <NUM> of <FIG>.

The stream processor system <NUM> of <FIG> can efficiently set configurations for the radio system <NUM>. The registers <NUM>, <NUM>, <NUM> of the processing channels of the stream processor system <NUM> can store data to control analog components of the receivers 64a to 64d, the transmitters 66a to 66d, and observation path <NUM>, respectively. For example, the registers <NUM>, <NUM>, and <NUM> can store filter coefficients for filters 74a and 74b, 84a and 84b, and 96a and 96b, respectively. As another example, registers <NUM>, <NUM>, and <NUM> can store data to control one or more local oscillator frequencies for upconverting or downconverting signals in the radio system <NUM>. As one more example, registers <NUM>, <NUM>, and <NUM> can store data to configure (e.g., set a sampling rate of) data converters (e.g., ADCs or DACs).

The receivers 64a to 64d can receive radio frequency signals RXRFIN and provide digital signals to the receive channels of the digital signal processor <NUM>. Each of the receivers 64a to 64d can include an attenuator <NUM>, a quadrature circuit <NUM> to generate quadrature local oscillator (LO) signals, mixers 72a and 72b, filters 74a and 74b, and analog-to-digital converters (ADCs) 76a and 76b. In an in-phase path, the mixer 72a downconverts the radio frequency input signal RXRFIN, the filter 74a filters the output of the mixer 72a, and the ADC 76a converts the output signal from the filter 74a from an analog signal to a digital signal. Similarly, in a quadrature-phase path, the mixer 72b downconverts the radio frequency input signal RXRFIN, the filter 74b filters the output of the mixer 72b, and the ADC 76b converts the output signal from the filter 74b from an analog signal to a digital signal. Although the illustrated radio system <NUM> includes <NUM> receivers, any suitable number of receivers can be implemented. With the distributed processing systems discussed herein, the number of receivers in the radio system <NUM> is more scalable than other radio systems.

The transmitters 66a to 66d can receive digital signals from the digital signal processor <NUM> and provide radio frequency transmit signals TXRFOUT for transmission via an antenna. Each of the transmitters 66a to 66d can include digital-to-analog converters (DACs) 82a and 82b, filters 84a and 84b, mixers 86a and 86b, and a quadrature circuit <NUM> to generate quadrature LO signals for the mixers 86a and 86b. In an in-phase path, the DAC 82a converts a digital signal from a transmit channel of the digital signal processor <NUM> to an analog signal, the filter 84a filters the output signal from the DAC 82a, and the mixer 86a upconverts the output signal from the filter 84a to radio frequency. Similarly, in a quadrature-phase path, the DAC 82b converts a digital signal from the digital signal processor <NUM> to an analog signal, the filter 84b filters the output signal from the DAC 82b, and the mixer 86b upconverts the output signal from the filter 84b to radio frequency. Although the illustrated radio system <NUM> includes <NUM> transmitters, any suitable number of transmitters can be implemented. With the distributed processing systems discussed herein, the number of transmitters in the radio system <NUM> is more scalable than other radio systems.

The observation path <NUM> can receive a radio frequency signal from one or more transmitters 66a to 66d via the loopback circuit <NUM>. The observation path <NUM> includes attenuators 91a to 91d, mixers 92a to 92d to downconvert radio frequency signals to baseband, a multiplexer <NUM>, filters 96a to 96b, and ADCs 98a to 98b. Any suitable number of observations paths can be implemented and/or the observation channel can process signals associated with any suitable number of transmitters.

<FIG> is a timing diagram for radio control operation of the stream processor system <NUM> of <FIG>. The signals TX1_EN to TX4_EN and RX1_EN to RX4_EN can be provided to pins of respective stream trigger interfaces <NUM> and <NUM> of the stream processor system <NUM> and/or to pins of respective radio events contacts <NUM> and <NUM>. These pins can be connected to the stream processors <NUM> or <NUM> via digital circuitry. Streams in the transmit channels can be active concurrently. Streams in the receive channels can be active concurrently.

As shown in <FIG>, transmit channels and receive channels can be triggered in parallel with each other. In the example of <FIG>, <FIG> streams can be triggered in parallel. Each of these streams can be completed within a deterministic duration after the radio event trigger. The streams can be completed at approximately the same time (e.g., in the same number of cycles or within a few cycles of each other).

The stream processor system <NUM> of <FIG> can implement a variety of functionalities. Examples use cases will be described with reference to the flow diagrams of <FIG>. These examples include various masters (e.g., a baseband processor, a main stream processor, a slice stream processor, an ARM processor, or a radio event), various processors executing instructions (e.g., a slice stream processor, a main stream processor, and/or an ARM), and various trigger types (e.g., a pin control interface, a stream trigger interface, an interrupt, a bus for an ARM processor). These processes can be performed in the context of the radio system <NUM> of <FIG> using the stream processor system <NUM> of <FIG>. Accordingly, reference may be made to elements of the stream processor system <NUM>. The operations of any of the processes discussed below can be performed in any other suitable system. Moreover, the operations of any of the processes discussed below can be performed in any suitable order that is technically feasible and certain operations can be implemented in parallel as appropriate.

<FIG> is a flow diagram of a process <NUM> in which a main stream processor triggers a slice stream processor in response to a radio channel being turned ON. The process <NUM> involves a main stream processor <NUM> triggering a transmit channel stream processor <NUM> in response to a transmit channel being enabled. Similar functionalities can be implemented in other radio channels in response to a receive channel and/or an observation channel being turned ON.

During initialization of a device under test (DUT), a JESD control channel can be configured to accept transmit/receive/observation receive enables. A link can be configured and made active. At block <NUM>, a transmit enable for transmit channel <NUM> can be received. The transmit enable can correspond to the TX1_EN signal of <FIG> being asserted (e.g., transitioning from low to high in <FIG>). The transmit enable signal can be received on an embedded control channel. A baseband processor can provide the transmit enable signal to a stream trigger interface <NUM> of the digital core <NUM> of the stream processor <NUM> of <FIG>. This can cause several other operations of the process <NUM> to be performed. Thus, a high level command provided to the stream processor system <NUM> can result in a number of operations being performed in a radio system <NUM>.

In response to the transmit enable signal TX1_EN being asserted, the main stream processor <NUM> can trigger a stream in the stream processor <NUM> of a first transmit channel 16a at block <NUM>. The stream in the first transmit channel 16a can be triggered by the main stream processor <NUM> triggering the stream processor <NUM> via the stream trigger interface <NUM>.

The transmit slice stream processor <NUM> executes instructions in response to a trigger from the main stream processor <NUM>. The operations at blocks <NUM>-<NUM> can be controlled by the stream processor <NUM>. The stream processor <NUM> can cause a transmit baseband filter 84a/84b of the transmitter 66a of <FIG> to power up at block <NUM>. A baseband filter flicker noise amplifier can also be powered up. At block <NUM>, the stream processor <NUM> can power up the local oscillator generator buffers. The system can wait for a period of time, such as <NUM> cycles, at block <NUM>. Then the upconverter mixers 86a and 86b of <FIG> and local oscillator buffer can be powered up at block <NUM>. The system can wait for a period of time, such as <NUM> cycles, at block <NUM>.

More circuit components, including pre-distortion amplifier and clock buffers for interface and DAC clocks, can be powered up at block <NUM>. Transmit clocks can also be enabled at block <NUM>.

At block <NUM>, a time-division duplexing ramp can be triggered. The system can wait for a number of cycles, such as <NUM> cycles, at block <NUM>. Data can be unmasked from DRFM at block <NUM>. Then the slice processor <NUM> can provide a return at block <NUM>. This can indicate that the radio system <NUM> is configured for transmission.

<FIG> is a flow diagram of a process <NUM> of a main stream processor being triggered by a baseband processor via a stream trigger interface. This is one example of a process of a baseband processor triggering a main stream processor. The process <NUM> involves a baseband processor triggering a main stream processor in response to a state of a switch on a printed circuit board toggling.

A default mapping for an initial polarity of switches on a printed circuit board can be configured to initialize a DUT. At block <NUM>, a switch configuration on a printed circuit board changes position. For example, a particular switch can change from an ON position to an OFF position. This can cause a baseband processor of the digital signal processor <NUM> of <FIG> to trigger a stream at block <NUM>. The stream corresponds to the particular switch position toggling. The stream can be triggered by the baseband processor providing an input signal to the stream trigger interface <NUM> to initiate the stream in the main stream processor <NUM> of <FIG>.

In the stream, a current state of mapping in the DUT can be read at block <NUM>. Then a bit corresponding to the particular switch toggling can be modified at block <NUM>. A transition bit field can be written to indicate that a radio channel, such as an observation receive channel, is in transition at block <NUM>. At block <NUM>, the stream can wait for a period of time, such as about <NUM> microseconds. Then the transition bit field can be cleared at block <NUM>. An interrupt can be sent to the ARM processor <NUM> at block <NUM>. A return can be provided by a main stream processor at block <NUM>. At block <NUM>, an ARM scheduler updates its internal mapping and triggers calibration.

<FIG> is a flow diagram of a process <NUM> of a slice stream processor triggering a main stream processor. The process <NUM> involves a radio event, such as a JDESD link sharing configuration, to cause the auxiliary stream processor, such as the transmit channel stream processor <NUM>, to trigger the main stream processor <NUM>. The trigger in the process <NUM> can be considered a direct trigger.

At block <NUM>, an observation receive path <NUM> can be powered. A local oscillator mixer can be enabled in powering up the observation receive path <NUM>.

A transmit channel stream processor <NUM> can execute instructions in response to an input signal received at radio events contacts <NUM>. Various circuitry, such as a loop back mixer, transimpedance amplifier and baseband multiplexer selects, can be powered up at block <NUM>. An ADC can be powered up at block <NUM>. Then the system can wait for a period of time, such as about <NUM> microsecond, at block <NUM>. At block <NUM>, a local oscillator delay buffer can be powered up. A DAC delay circuit can be powered up at block <NUM>. Accordingly, a radio system can be ready for the observation path to observe a transmit path. The stream processor <NUM> can send a return at block <NUM>. This can trigger the main stream processor <NUM>. An event trigger signal can be sent from the stream processor <NUM> to the main stream processor <NUM> via a dedicated signal line.

The main stream processor <NUM> can execute instructions in response to an event trigger from the stream processor <NUM> in the transmit channel. At block <NUM>, a multiplexer can be re-configured to route observation receive data (instead of receive data) to digital radio frequency memory (DRFM). The observation channel data can be unmasked to DRFM at block <NUM>. Then at block <NUM> a return can be provided by the main stream processor <NUM>.

<FIG> is a flow diagram of a process <NUM> of a slice stream processor interrupting an ARM processor. The process <NUM> involves a radio channel stream processor, such as a transmit channel stream processor, sending an interrupt to an ARM processor in response to the radio channel turning on. This can re-start tracking calibrations.

At block <NUM>, a transmit path is powered up. This can set the transmit path into an initial configuration.

A transmit channel stream processor <NUM> can execute instructions and provide an interrupt to the ARM processor <NUM>. The stream processor <NUM> can power up analog circuitry of a transmitter 66a. The stream processor <NUM> can execute instructions to cause a transmit baseband filter 84a/84b to be powered up at block <NUM>. Baseband filter flicker noise amplifiers can also be powered up. Local oscillator generator buffers can be powered at block <NUM>. An upconverter 86a/86b and local oscillator buffer can be powered up at block <NUM>. The system can wait for a period of time, such as <NUM> cycles, at block <NUM>. Then additional circuitry can be powered up at block <NUM>. The additional circuitry can include a pre-distortion amplifier, clock buffers for interface and DAC clocks, and enable circuitry for transmit clocks. At block <NUM>, a TDD ramp can be triggered. The system can wait for another period of time (e.g., <NUM> cycles) at block <NUM>. Data can be unmasked from DRFM at block <NUM>.

The transmit channel stream processor <NUM> can send an interrupt to ARM processor <NUM> at block <NUM>. The interrupt can be provided via a dedicated signal line. The stream processor <NUM> can provide a return at block <NUM>. This can indicate that the stream processor <NUM> is done executing the stream. The ARM processor <NUM> can initiate data capture for transmit calibrations at block <NUM> in response to receiving the interrupt.

<FIG> is a flow diagram of a process <NUM> of a main stream processor interrupting an ARM processor. In the process <NUM>, a polarity of a switch in a front end on a printed circuit board can change state. This can pause calibration and/or abort calibration on the ARM processor of a stream processor system.

A DUT can be initialized. A default mapping for an initial polarity of switches on a printed circuit board can be configured to initialize the DUT at block <NUM>. General purpose input/output (GPIO) pins can be configured as input pins at block <NUM>.

At block <NUM>, a switch configuration on a printed circuit board changes position. For example, a particular switch can change from an ON position to an OFF position. The particular switch can be included in a radio frequency front end. An input of the particular switch can be connected to a GIPO pin. Toggling the polarity of the particular switch can also toggle a GPIO pin to the DUT at block <NUM>. The GIPO toggle can trigger a stream on the main stream processor <NUM> of <FIG>.

In the stream on the main stream processor <NUM>, a current state of mapping in the DUT can be read at block <NUM>. Then one or more bits corresponding to the particular switch toggling can be modified at block <NUM>. A transition bit field can be written to indicate that a radio channel, such as an observation receive channel, is in transition at block <NUM>. At block <NUM>, the stream can wait for a period of time, such as about <NUM> microseconds. Then the transition bit field can be cleared at block <NUM>. An interrupt can be sent from the main stream processor <NUM> to the ARM processor <NUM> at block <NUM>. A return can be provided by a main stream processor at block <NUM>. This can indicate that the main stream processor <NUM> is done executing the stream. At block <NUM>, an ARM scheduler updates its internal mapping and triggers calibration in response to receiving the interrupt.

<FIG> is a flow diagram of a process <NUM> of an initialization stream called by an ARM processor according to an embodiment. In the process <NUM>, an ARM processor triggers a main stream processor in an initialization and/or power up. The stream can be triggered using a bus for the ARM processor. The bus can be an Advanced Microcontroller Bus Architecture High-performance Bus (AHB), for example.

At block <NUM>, JESD parameters are configured. The JESD parameters can be use case specific. Mask bits can be configured for radio event triggers from a slice stream processor to a main stream processor at block <NUM>. ARM/stream processor intercommunication registers can be reset at block <NUM>. Transmit-observation receive mapping registers can be configured at block <NUM>. At block <NUM>, a return can be provided.

<FIG> is a flow diagram of a process <NUM> of an ARM processor triggering a stream in a slice stream processor according to an embodiment. In the process <NUM>, an observation receive/loopback path for transmit loopback calibration is configured. The stream can be triggered using a bus, such as an AHB, of the ARM processor.

At block <NUM>, a local oscillator mixer is enabled. This can be done as part of initial power up. It is determined whether the observation receiver is enabled at decision block <NUM>. In response to determining that the observation receiver is enabled, the process <NUM> can exit at block <NUM>. In response to determining that the observation receiver is not enabled, the process <NUM> proceeds with configuring an observation path for transmit loopback calibration.

Analog components of an observation receive path can be configured by a slice stream processor <NUM> of an observation channel 18a. A loop back mixer, transimpedance amplifier and baseband multiplexer selects can be powered up at block <NUM>. An ADC can be powered up at block <NUM>. Then the system can wait for a period of time, such as about <NUM> microsecond, at block <NUM>. At block <NUM>, a local oscillator delay buffer can be powered up. A DAC delay circuit can be powered up at block <NUM>. Digital circuitry can be powered up at block <NUM>. This can involve turning on digital clocks. Correlators for tracking based calibrations can be unpaused at block <NUM>. JESD data can be unmasked at block <NUM>. A return can be provided by the slice stream processor <NUM> at block <NUM>. This can indicate that the observation receive path is ready for transmitter loopback calibrations.

Radio events can trigger slice stream processors via a pin control interface. This can turn ON a radio channel (e.g., a transmit channel, a receive channel, or an observation channel). <FIG> is a flow diagram of a process <NUM> of powering up an observation path. The <FIG> is a flow diagram of powering up a transmit path. In these processes, slice stream processors can be triggered though the pin control interface without the ARM processor or the main stream processor triggering the slice stream processor.

<FIG> is a flow diagram of a process <NUM> of a radio event triggering a slice stream processor for powering up an observation path. At block <NUM>, an observation receive path <NUM> can be powered up. A local oscillator mixer can be enabled in powering up the observation receive path <NUM>.

The slice stream processor <NUM> can execute instructions in response to an input signals received at radio events contacts. The slice stream processor <NUM> can be triggered by an input signal received at radio event contacts <NUM> of the observation channel 18a. The slice stream processor <NUM> can configure analog components on the observation receive path. A loop back mixer, transimpedance amplifier and baseband multiplexer selects can be powered up at block <NUM>. An ADC can be powered up at block <NUM>. Then the system can wait for a period of time, such as about <NUM> microsecond, at block <NUM>. At block <NUM>, a local oscillator delay buffer can be powered up. A DAC delay circuit can be powered up at block <NUM>. Data can be unmasked to FRMs at block <NUM>. Then at block <NUM> a return can be provided by the slice stream processor <NUM>.

<FIG> is a flow diagram of a process <NUM> of a radio event triggering a slice stream processor for powering up a transmit path. The slice stream processor <NUM> can be triggered by an input signal received at radio event contacts <NUM> of the transmit channel 16a. At block <NUM>, a transmit path is powered up. This can set the transmit path into an initial configuration. A slice stream processor <NUM> can execute instructions to configure the transmit path for transmission. The slice stream processor42 can execute instructions to cause a transmit baseband filter 84a/84b to be powered up at block <NUM>. Baseband filter flicker noise amplifiers can also be powered up. Local oscillator generator buffers can be powered at block <NUM>. The system can wait for a period of time, such as <NUM> cycles, at block <NUM>. Then an upconverter 86a/86b and local oscillator buffer can be powered up at block <NUM>. The system can wait for a period of time, such as <NUM> cycles, at block <NUM>. Then additional circuitry can be powered up at block <NUM>. The additional circuitry can include a pre-distortion amplifier, clock buffers for interface and DAC clocks, and enable circuitry for transmit clocks. At block <NUM>, a TDD ramp can be triggered. The system can wait for another period of time (e.g., <NUM> cycles) at block <NUM>. Data can be unmasked from DRFM at block <NUM>.

Although embodiments may be discussed above with reference to the stream processor system <NUM> of <FIG>, other stream processor systems can implement any suitable principles and advantages discussed herein. For example, a stream processor system can include more than one ARM processor. <FIG> illustrates an example stream processor system that includes two ARM processors. As another example, a stream processor system can be implemented with an ARM processor and stream processors for processing channels and without a main stream processor. <FIG> illustrates an example stream processor system with such features. The principles and examples of the example stream processing systems of <FIG> and <FIG> can be applied to any other suitable distributed processing systems that include a main processor and co-processors.

<FIG> is a schematic block diagram of a stream processor system <NUM> according to an embodiment. The stream processor system <NUM> is like the stream processor system <NUM> of <FIG>, except that the digital core <NUM> includes an additional ARM processor <NUM> relative to the digital core <NUM> of <FIG>. The additional ARM processor <NUM> can be configured to execute instructions for particular tasks, which can be computation intensive. As an example, the ARM processor <NUM> can be configured to execute digital pre-distortion (DPD) functions. The ARM processor <NUM> can be any suitable processor, such as an ARM M3 processor or an ARM M4 processor.

<FIG> is a schematic block diagram of a stream processor system <NUM> according to another embodiment. The stream processor system <NUM> is like the stream processor system <NUM> of <FIG>, except that the digital core <NUM> does not include a main stream processor and connections among components are adjusted accordingly relative to the stream processor system <NUM>. Functions of the main stream processor of the stream processor system <NUM> can be executed by the ARM processor <NUM> in the stream processor system <NUM>. The ARM <NUM> can receive event triggers from stream processors in processing channels. The ARM <NUM> can trigger streams in the stream processors in processing channels.

Any of the principles and advantages discussed herein can be applied to other systems, devices, integrated circuits, electronic apparatus, methods, not just to the embodiments described above. The elements and operations of the various embodiments described herein can be combined to provide further embodiments. The principles and advantages of the embodiments can be used in connection with any other systems, devices, integrated circuits, apparatus, or methods that could benefit from any of the teachings herein.

Unless the context indicates otherwise, throughout the description and the claims, the words "comprise," "comprising," "include," "including," and the like are to generally be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to. " The word "coupled," as generally used herein, refers to two or more elements that may be either directly coupled to each other, or coupled by way of one or more intermediate elements. Likewise, the word "connected," as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words "herein," "above," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. Where the context permits, the word "or" in reference to a list of two or more items is intended to cover all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

Moreover, conditional language used herein, such as, among others, "can," "could," "might," "may," "e.g.," "for example," "such as" and the like, unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.

Claim 1:
A distributed processing system (<NUM>) for configuring multiple processing channels of a radio system, the distributed processing system comprising:
a main processor (<NUM>) configured to execute main processor instructions; and
a plurality of processing channels (14a-d, 16a-d), wherein each of the processing channels comprises:
registers (<NUM>, <NUM>) configured to store data;
a co-processor (<NUM>, <NUM>) configured to execute co-processor instructions and to receive a trigger from the main processor that causes the co-processor to execute a set of instructions of the co-processor instructions including at least one instruction to access at least one of the registers of the respective processing channel,
radio event contacts (<NUM>, <NUM>) and dedicated circuitry connected to the radio event contacts, wherein the dedicated circuity is configured to execute a first type of instruction received at the radio event contacts; and
a stream trigger interface (<NUM>, <NUM>) configured to receive an input signal from external to the distributed processing system and to cause the co-processor to execute a second type of instruction in response to receiving the input signal, wherein the second type of instruction is unmapped to specific circuitry,
wherein the distributed processing system is configured to divide processing between the main processor and the co-processor such that the main processor executes instructions with longer latency and the co-processor executes instructions with lower latency.