Patent Description:
Presently, the task of developing and configuring a network system is a great challenge, especially when complex network applications are part of the network system. A main reason is the lack of sufficient visibility and observability of properties of the network system (for example due to the lack of suitable logging of network information) in early design and modeling phases, but also in posterior verification and validation phases. This causes trouble to maintenance and growth of such networking systems. Therefore, the lack of said visibility keeps present along the whole life cycle of the network system.

Taking the automotive industry as an example, a current trend is that network systems become a core part of a vehicle, bringing features like modularity, scalability and configurability into the backbone of the vehicle. A growth of network systems however is not only present in automotive or transportation, but across all industries. Often, these network systems are implemented by electronic control units (ECUs) or integrated hardware. As a result, simulation of network systems for any kinds of use cases becomes an important aspect of the design and modeling phase.

In order to develop a precise dynamic model, which is able to accurately simulate a physical system (e.g. the network system in a vehicle), the simulation or model needs to have access to sufficient data (e.g. data obtained by logging network information). Typically, the lack of such data is a main barrier of implementing a dynamic model. This problem is not limited to automotive use cases and generally applies to simulation of all kinds of network systems.

A conventional solution for logging network information required for simulation and modeling is using standalone and expensive test and measurement equipment (e.g. a data logger, a digital oscilloscope, or the like) to monitor a network system under test. However, these conventional solutions involve the following drawbacks: lack of miniaturization, lack of a customizability and flexibility, lack of memory space or computation performance for real-time analysis. That is, in the prior art there is the lack of a solution for logging network information with little dimensions, high performance, and which can be flexibly integrated into other devices.

<CIT> relates to packet capture in a network.

<CIT> Aldiscloses a reliable load-balanced multi-photonic star configuration.

In view of the above-mentioned problem, embodiments of the present invention aim to improve the conventional solutions for logging network information.

The object is achieved by the invention as defined in the enclosed independent claims. Advantageous implementations of embodiments of the invention are further defined in the dependent claims.

A first aspect of the present invention provides an integrated circuit for network data processing and network data logging, wherein the integrated circuit comprises a first processor configured to process multiple network packets obtained from one or more input ports of the integrated circuit and to forward the multiple network packets towards one or more output ports of the integrated circuit, and a coprocessor separate from the first processor, configured to obtain duplicates of the multiple network packets from the first processor and/or from the integrated circuit, and to aggregate logging network information based on the duplicates of the multiple network packets, wherein the logging network information comprises information about the multiple network packets, wherein the duplicates relate to multiple input ports of the integrated circuit, and the coprocessor is configured to arrange the duplicates in a chronological and/or a serial order, to aggregate the logging network information.

This is beneficial, as a conventional network processing device (e.g. a switch, a router, or the like) is extended with embedded coprocessing capabilities, which can be used for
aggregation the logging network information exclusively. In particular, this is achieved by providing and integrated circuit with a processor for network processing, and a separate processor for logging network information. In doing so, a sufficient level of visibility of network information is obtained and core features like high performance, flexible integration into other device, and a small form factor are realized.

This is also beneficial, as compaction and miniaturization aspects are addressed by providing the solution for logging network information in a single integrated circuit.

By means of making data that flow through the network system accessible, it is possible to develop virtual models/simulations or digital twins of complex physical systems, which becomes more and more important in many real use cases in the industry. The implementation of digital twins can not only be related to any functionality or application distributed across several entities or devices interconnected through a communication network, but also can be related to the own functionality of the network itself, i.e. a network digital twin understood as the simulation model of the communication network along with its operating environment and the application traffic that it carries, modeling the features of performance of the physical networking device (e.g. a bridge, switch, or router).

According to certain embodiments, the integrated circuit may be a system on a chip (SoC).

According to certain embodiments, a duplicate of a network packet may be any information representing the network packet and its content.

According to certain embodiments, the first processor may be implemented by a first processing core. In particular, the coprocessor is implemented by a separate processing core. According to certain embodiments, a power of the coprocessor and a power of the first processor may be equal. According to certain embodiments, a power of the coprocessor may be different from a power of the first processor. For example, a power of the coprocessor is smaller or greater than a power of the first processor.

According to certain embodiments, the first processor may be a main processor, a primary processor, or a central processing unit.

According to certain embodiments, the first processor may be configured for at least one of: network data switching, network data routing, network data bridging, network data forwarding.

According to certain embodiments, the logging network information may be aggregated based on the content of each of the duplicates of network packets.

According to certain embodiments, the duplicates obtained by the coprocessor may be duplicates of network packets obtained by the first processor. In other words, the first processor can receive network packets as a part of network traffic that is received by the integrated circuit. The first processor makes duplicates of the received network packets and forwards the duplicates to the coprocessor for network data logging. Alternatively, the duplicates are made directly by the coprocessor based on single or multiple network packets received by the first processor and/or by the integrated circuit. To this end, the first processor can provide information about each network packet to the coprocessor. In any of such two cases, afterwards, conventional network switching (including forwarding, routing, or bridging) is applied to the network packets originally received by the first processor.

According to certain embodiments, the coprocessor may be a computer processor used to supplement the functions of the first processor.

According to certain embodiments, the coprocessor may be configured to implement network data logging on a hardware level.

According to certain embodiments, the logging network information may comprise information about each of the single or multiple network packets.

According to certain embodiments, the network packet and/or the duplicate may be a packet on a data link layer (e.g. OSI layer <NUM>). The network packet and/or the duplicate can alternatively be a packet of one of: a network layer (e.g. OSI layer <NUM>), a transport layer (e.g. OSI layer <NUM>), a session layer (e.g. OSI layer <NUM>), a presentation layer (e.g. OSI layer <NUM>), an application layer (e.g. OSI layer <NUM>).

According to certain embodiments, the network packet and/or the duplicate may be an ethernet frame, or a message in a controller area network (CAN) bus, or a message in local interconnect network (LIN) bus, or a message in FlexRay bus, or a message in Peripheral Component Interconnect Express (PCIe) bus.

This is beneficial, as a separate processor can be provided to the first processor. The coprocessor can exclusively use its computing power for network data logging, thereby making network data logging more effective and efficient. The coprocessor in particular ensures network data logging in real-time and on the fly. More specifically, the power of the primary processor (e.g. network switching or routing) is not affected by the coprocessor. This is further beneficial as the first processor and the coprocessor can be provided as one single unit, i.e. as one integrated circuit.

In an implementation form of the first aspect, the coprocessor is configured to exclusively implement network data logging.

This is beneficial as the processing power of one coprocessor can be exclusively used for network data logging. The coprocessor e.g. can implement network data logging function in hardware.

In a further implementation form of the first aspect, the coprocessor is configured to add a timestamp to each duplicate in the duplicates, to aggregate the logging network information.

This ensures that a network traffic scenario, which was logged by the integrated circuit, can be reconstructed, e.g. during a test or simulation, guaranteeing time-invariant features.

In a further implementation form of the first aspect, the coprocessor is configured to compress each duplicate in the duplicates, to aggregate the logging network information.

This ensures that logging network information can be stored in an efficient manner. This helps to safe storage capacity when storing the logging network information, or bandwidth when providing the logging network information to an external device by means of a network connection.

According to certain embodiments, the coprocessor may be further configured to reshape a frame format of each duplicate in the duplicates, to aggregate the logging network information. Reshaping the frame format is e.g. implemented by a predefined protocol.

In a further implementation form of the first aspect, the coprocessor is configured to encrypt each duplicate in the duplicates, to aggregate the logging network information. This ensures security of the logging network information in both internal data storage and external data transfer scenarios.

In a further implementation form of the first aspect, the coprocessor is configured to configure a header and/or a trailer of each duplicate in the duplicates, to aggregate the logging network information.

According to certain embodiments, the trailer of each duplicate in the duplicates may be used to aggregate data packet redundancy information for reliability and integrity check of the respective duplicate.

This allows for pre-processing of the duplicates of the network packets which form the logging network information. Thus, the logging network information can be post-processed more efficiently.

According to certain embodiments, the chronological and/or the serial order is obtained based on the timestamps added to the duplicates.

According to certain embodiments, the duplicates may be arranged in the chronological and/or serial order based on a timestamp in each duplicate of a packet. The timestamp may be e.g. obtained as described above. In particular, the plural of duplicate, reading "duplicates" means greater or equal to two.

This ensures that the integrated circuit can be used when information from multiple input ports has to be processed. In particular, an input port is an ingress port.

In a further implementation form of the first aspect, the integrated circuit comprises a memory, wherein the coprocessor is configured to provide the logging network information to the memory.

This is beneficial, as the integrated circuit can also provide the logging network information to a memory, if no other entity for receiving the logging network information is present.

In a further implementation form of the first aspect, the memory comprises a volatile memory for queueing and/or buffering the logging network information and/or a non-volatile memory for storing the logging network information.

This is beneficial as the integrated circuit can queue and/or buffer the logging network information, e.g. if an external device for receiving the logging network information is temporarily not available, e.g. due to an overload. This is beneficial as the integrated circuit can store the logging network information, e.g. if the logging network information is to be analyzed later, e.g. in a laboratory environment. In particular, the integrated circuit comprises the volatile memory and the non-volatile memory. This ensures that the integrated circuit can implement a queue and/or buffer as well as a storage.

In a further implementation form of the first aspect, the coprocessor is configured to provide the logging network information to an external entity.

According to certain embodiments, the coprocessor may be configured to read the logging network information from the memory to provide it to the external entity. According to certain embodiments, the coprocessor may be configured to provide the logging network information to the external entity directly after aggregating it. That is, the logging network information can be provided directly after it is obtained, on the fly and/or can be stored in the volatile and/or non-volatile memory and provided to the external entity from the volatile and/or non-volatile memory. According to certain embodiments, the logging network information may be provided to the external entity by means of one or more monitoring ports of the integrated circuit. According to certain embodiments, the logging network information may be provided to an external entity through one or more output ports of the integrated circuit.

In a further implementation form of the first aspect, the coprocessor and/or the processor is further configured to create and/or inject a new network packet to the one or more output ports, wherein the coprocessor is further configured to aggregate the logging network information also based on the new network packet.

According to certain embodiments, the new network packet and/or its format may be configurable by the user. In particular, this new data injection task performed by the coprocessor or the processor is optional/configurable by the user.

This is beneficial, as with this new network packet injection feature activated/enabled, the integrated circuit is no more a passive agent in a network but an active agent, able to modify the whole network activity with new network packets.

A second aspect of the present invention provides a method for network data processing and network data logging, wherein the method comprises the steps of processing, by a first processor of an integrated circuit, multiple network packets obtained from one or more input ports of the integrated circuit, and forwarding, by the first processor, the multiple packets towards one or more output ports of the integrated circuit, obtaining, by a coprocessor of the integrated circuit, duplicates of the multiple network packets from the first processor and/or from the integrated circuit, wherein the coprocessor is separate from the first processor, and aggregating, by the coprocessor, logging network information based on the duplicates of the multiple network packets, wherein the logging network information comprises information about the multiple network packets, wherein the duplicates relate to multiple input ports of the integrated circuit, and the method further includes arranging, by the coprocessor, the duplicates in a serial order corresponding to the input ports, to aggregate the logging network information.

In an implementation form of the second aspect, the method further includes exclusively implementing network data logging by the coprocessor.

In a further implementation form of the second aspect, the method further includes adding, by the coprocessor, a timestamp to each duplicate in the duplicates, to aggregate the logging network information.

In a further implementation form of the second aspect, the method further includes compressing, by the coprocessor, each duplicate in the duplicates, to aggregate the logging network information.

In a further implementation form of the second aspect, the method further includes encrypting, by the coprocessor, each duplicate in the duplicates, to aggregate the logging network information.

In a further implementation form of the second aspect, the method further includes configuring, by the coprocessor, a header of each duplicate in the duplicates, to aggregate the logging network information and a trailer of each duplicate in the duplicates to aggregate data packet redundancy information for reliability and integrity check of such resultant duplicate data packet with aggregated logging network information.

In a further implementation form of the second aspect, the integrated circuit comprises a memory, wherein the method further includes providing, by the coprocessor, the logging network information to the memory.

In a further implementation form of the second aspect, the memory comprises a volatile memory for queuing or buffering the logging network information and/or a non-volatile memory for storing the logging network information.

In a further implementation form of the second aspect, the method further includes providing, by the coprocessor, the logging network information to an external entity.

In a further implementation form of the second aspect, the method further includes creating and/or injecting, by the coprocessor and/or processor, a new network packet to the one or more output ports, and aggregating, by the coprocessor, the logging network information also based on the new network packet.

The second aspect and its implementation forms include the same advantages as the first aspect and its respective implementation forms.

A third aspect of the present invention provides a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the steps of the method of the second aspects or any of its implementation forms.

The third aspect and its implementation forms include the same advantages as the second aspect and its respective implementation forms.

A fifth aspect of the present invention provides a system comprising the integrated circuit according to the first aspect or any of its implementation forms, and a simulation device, wherein the integrated circuit is configured to provide the logging network information to the simulation device, and wherein the simulation device implements digital twin technology for processing the logging network information.

This ensures that with digital twin technology, a mathematical model that fully describes the dynamic behavior of a real physical system, can be applied to the logging network information.

The fifth aspect and its implementation forms include the same advantages as the first aspect and its respective implementation forms.

The above-described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which.

<FIG> shows a schematic view of an integrated circuit <NUM> according to an embodiment of the present invention. The integrated circuit <NUM> is for network data processing and network data logging, and comprises two separate processors, a first processor <NUM> and a coprocessor <NUM>. The integrated circuit <NUM> can for example be an ECU or a system on a chip (SoC). For example, the first processor <NUM> is implemented by a first processing core and the coprocessor <NUM> is implemented by a separate processing core.

The first processor <NUM> is configured to process multiple network packets <NUM> obtained from one or more input ports <NUM> of the integrated circuit <NUM> and to forward the multiple network packets <NUM> towards one or more output ports <NUM> of the integrated circuit <NUM>. The multiple network packets <NUM> are the multiple network packets <NUM> which optionally have been processed and/or amended by the first processor <NUM>. In other words, the first processor <NUM> implements conventional network processing (e.g. as done in a switch, a router, a bridge, or the like). Although there is only one input port <NUM> shown in <FIG>, there can be an arbitrary number of input ports <NUM> of the integrated circuit <NUM>. Although there is only one output port <NUM> shown in <FIG>, there can be an arbitrary number of output ports <NUM> of the integrated circuit <NUM>.

To extend the conventional network processing (which is implemented by the first processor <NUM>), the coprocessor <NUM> is separate from the first processor <NUM> and is configured to obtain duplicates <NUM> of the multiple network packets <NUM> from the first processor <NUM> and/or from the integrated circuit <NUM>.

The first processor <NUM> can either forward the selected duplicates <NUM> to the coprocessor <NUM> or the coprocessor <NUM> obtains the duplicates <NUM> by itself, e.g. running in a parallel data path of the integrated circuit <NUM> (without interfering the behavior of the first processor <NUM>).

The coprocessor <NUM> is further configured to aggregate logging network information <NUM> based on the duplicates <NUM> of the multiple network packets <NUM>, wherein the logging network information <NUM> comprises information <NUM> about the multiple network packets <NUM>. That is, by means of aggregating, information about each of the network packets <NUM> is stored in a single piece of information (i.e. the logging network information).

Both the first processor <NUM> and the coprocessor <NUM> are integrated in the same electronic chip. In other words, an on-chip data logging function is embedded into a network switching chip (or a routing chip or a bridging chip). A network switching function and a logging function are seamlessly interconnected in order to improve performance of logging network information.

Both the switching function and the logging function can be configurable by a user, that is, the user can define what kind of network packets <NUM>, <NUM> can be switched from one input port <NUM> to an output port <NUM>. For the logging function, the user can define what kind of network packets <NUM> can be captured to be logged. This can be managed by configurable parameters of the integrated circuit <NUM>.

To meet real-time constraints and performance requirements, the coprocessor <NUM> can execute the logging functionality directly in hardware (e.g. by a custom processing core synthesized in logic cells and exploiting parallelism and pipeline) instead of software (e.g. a sequence of instructions executed on a processor).

The integrated circuit <NUM> optionally can process network packets <NUM> at layer <NUM> of the OSI model or above (layer <NUM> to layer <NUM>). The network packets <NUM> can be ethernet frames being forwarded through different ports of an ethernet switch or a router, or other messages, such as in a CAN bus or a LIN bus in a vehicle.

The integrated circuit <NUM> optionally can be a standardized hardware solution, which can be used in SoC devices across many network applications fields (e.g. automotive, smart manufacturing, information technology, aerospace, military, or health equipment).

The first processor <NUM> and/or the coprocessor <NUM> optionally can implement an open and standardized software architecture for automotive ECUs, e.g. for definition of software components, libraries or application programming interfaces.

In other words, the integrated circuit <NUM> allows to aggregate logging network information <NUM> (e.g. logging reports) in order to evaluate the status and functional behavior of a network system. Moreover, by using this logging network information <NUM> as an input stimulus to a digital functional twin of the networking system, it is possible to perform verification, validation, and predictive maintenance of the network system.

Optionally, the coprocessor <NUM> is configured to exclusively implement network data logging, so as to clearly separate the network logging function from the conventional network processing in the first processor <NUM>.

<FIG> shows a schematic view of an integrated circuit <NUM> according to an embodiment of the present invention in more detail. The integrated circuit <NUM> shown in <FIG> comprises all features and functionality of the integrated circuit <NUM> of <FIG>, as well as the following optional features:
As illustrated in <FIG>, the integrated circuit <NUM> can also comprise a memory <NUM> and the coprocessor <NUM> can provide the logging network information <NUM> to the memory <NUM>. The memory <NUM> e.g. can comprise a volatile memory 201a for queueing or buffering the logging network information <NUM> and/or a non-volatile memory 201b for storing the logging network information <NUM>. The logging network information <NUM> can then be provided to an external entity from the memory <NUM>. Moreover, in general, the memory can be onchip or off-chip, and in-system or external to the system itself, for instance a hard drive memory or a pen drive pluggable to the system or integrated circuit <NUM>.

However, the logging network information <NUM> can also be sent to an external device (outside the integrated circuit <NUM>) directly, following predefined traffic shaping, scheduling and adapting rules. Thus, a transmission speed according to the demands of the receiver or to the status of the network (e.g. to reduce the transfer rate if the receiver or network is overloaded, in order to not have packets drop) can be achieved.

In any of the above cases, the external entity optionally can undo/unpack the logging network information <NUM> in order to obtain the original network packets <NUM> captured by the integrated circuit <NUM>. In this way, the logging procedure is transparent, and the external entity can synthesize a digital twin free of interference.

As it is also illustrated in <FIG> the coprocessor <NUM> and or the processor <NUM> optionally can be configured to create and/or inject a new network packet <NUM> to the one or more output ports <NUM>, and the coprocessor <NUM> can be configured to aggregate the logging network information <NUM> also based on the new network packet <NUM>.

<FIG> shows a schematic view of an operating scenario of the integrated circuit <NUM>. As it is now going to be described in view of <FIG>, the functionality of the integrated circuit <NUM> can be grouped into three blocks <NUM>, <NUM>, <NUM>.

The first block <NUM> relates to handling network packets <NUM>, <NUM> that reach the integrated circuit <NUM>, respectively their duplicates in real-time and on the fly. For example, the coprocessor <NUM> optionally can be configured to add a timestamp to each duplicate <NUM> in the duplicates <NUM>, to aggregate the logging network information <NUM>.

The second block <NUM> relates to formatting duplicates <NUM> of the packets <NUM> according to a set of rules and either storing/queueing/buffering them in memory or directly forwarding them to one or more logging ports.

For example, the coprocessor <NUM> optionally can be configured to compress each duplicate <NUM> in the duplicates <NUM>, to aggregate the logging network information <NUM>.

The compression can be configured by a user of the integrated circuit <NUM>. This includes optional reshaping of the frame format of the duplicate <NUM> according to a predefined protocol.

According to another example, the coprocessor <NUM> optionally can be configured to encrypt each duplicate <NUM> in the duplicates <NUM>, to aggregate the logging network information <NUM>. The encryption can be configured by a user of the integrated circuit <NUM>.

According to another example, the coprocessor <NUM> optionally can be configured to configure a header and/or a trailer of each duplicate <NUM> in the duplicates <NUM>, to aggregate the logging network information <NUM>. The trailer of each duplicate <NUM> in the duplicates <NUM> can be used to aggregate data packet redundancy information for reliability and integrity check of such resulting duplicates.

In particular, into the header of each duplicate <NUM>, it is put all kind of information that is relevant for interpreting the duplicate <NUM> or the corresponding network packet <NUM>. All information put into the header is configurable according to a set of system parameters that a user can configure previously in a setup process of the integrated circuit <NUM>.

According to another example, the coprocessor <NUM> optionally can be configured to apply packetization to each duplicate <NUM> in the duplicates <NUM>, to aggregate the logging network information <NUM>.

Packetization refers to information related to one or more duplicate <NUM> being formatted, shaped or stored following a pre-defined format. For instance, two frames can be grouped in one if both have the same source and destination addresses. These aspects are configurable by a user in a setup process.

The third block <NUM> relates to output data handling, e.g. to which output port <NUM> a network packet <NUM> is to be provided, or that the new packet <NUM> can be created and injected to the output ports <NUM>.

The functionality defined in blocks <NUM>, <NUM> and <NUM> is implemented on a hardware level in the integrated circuit <NUM> by the first processor <NUM> and/or the coprocessor <NUM>, resulting in a high level of performance, e.g. by exploitation of parallelism and pipelining design techniques. Allocating network data processing to the first processor <NUM> and network data logging to the coprocessor <NUM> also ensures that normal operation or the quality of service (QoS) of the integrated circuit <NUM> is not affected by aggregating the logging information <NUM>.

<FIG> shows a schematic view of the integrated circuit <NUM> according to the present invention, being realized for example as an automotive in-vehicle networking chip. As it is illustrated in <FIG>, the integrated circuit <NUM> employs a system bus / Network-On-Chip which is accessible by both the first processor <NUM> and the coprocessor <NUM>.

<FIG> shows another schematic view of an integrated circuit <NUM> according to the present invention. More specifically, <FIG> shows a multiport ethernet local area network (LAN) switch (also called "LSW") which employs the integrated circuit <NUM> and is e.g. composed of several ports and e.g. operates ethernet frames at Layer <NUM> (but optionally also any other network packets <NUM> mentioned herein).

In the integrated circuit shown in <FIG>, the coprocessor <NUM> is illustrated as a dedicated peripheral or IP (Intellectual Property) core (labelled "Data Logger and Digital Twin Core") inside the LSW. This IP core is responsible for capturing, at real-time, at least one network packet <NUM> that flows between at least one ingress port (input ports <NUM> labelled "PHY" on the left side of <FIG>) and at least one egress port (output ports <NUM> labelled "PHY" on the right side of <FIG>) of the LSW, formatting (e.g. packetization, compression, wire-speed encryption) and storing them in a storage unit (e.g. the memory <NUM>), e.g. DDR4 memory, and finally transferring them outside, e.g. through a dedicated logging port <NUM>, which e.g. follows specific traffic shaping rules which can be configured by a user.

<FIG> shows another schematic view of an integrated circuit <NUM> according to the present invention. To increase performance of the logging process (e.g. to establish a low latency data path, or data storage space optimization), optionally, the duplicates <NUM> of the network packets <NUM> can be temporarily stored and can be furthermore packetized, compressed and/or encrypted on the fly, before writing them as logging network information <NUM> to the memory <NUM>, and can be depacketized, decompressed and decrypted afterwards when reading the logging network information <NUM> back from the memory <NUM> or even later when the logging network packet <NUM> reaches an external simulation or digital twin device <NUM> as it is going to be described below in view of <FIG>.

To this end, the integrated circuit <NUM> can perform the following optional steps:.

It is important to note that all these steps are performed without affecting the normal behavior of the network data processing (i.e. the conventional operation of a switch or router).

In the following, three exemplary use cases are going to be described in which the integrated circuit <NUM> can be employed:
Data Logger function: By means of the network data logging function provided by the integrated circuit <NUM> it is possible to have visibility of network packets <NUM> that flow through the different input ports <NUM> and output ports <NUM> of the switch. That is, every electronic system equipped with the integrated circuit provides a superior level of visibility and observability of network traffic to develop network applications on top of it. The fact that the integrated circuit <NUM> is equipped with such technology allows network engineers to visualize the communication in a user-friendly environment at any time.

Digital Twin function: Developing products with switching chipsets that employ the integrated circuit <NUM> enable the possibility to virtualize the functionality of said product through a digital twin as the integrated circuit <NUM> can log network packets <NUM> that flow through its input ports <NUM> (e.g. ingress ports) and output ports <NUM> (e.g. egress ports) in real-time. The network data logging and digital twin function provide the foundation on which the virtualization and digital model of any product or function can be built (for example the simulation of networks systems, e.g. in vehicles).

Event Data Recording function: In a similar way to the mandatory presence of black boxes (i.e. flight data recorders) in airplanes, it is planned to obligate the installation of such an information recording systems also in automatic driving vehicles, e.g. for autonomous driving levels <NUM> to <NUM>, to help determine responsibility in the event of an accident. All kind of vehicles (including trucks, buses, vans, utility vehicles, boats, drones, helicopters, planes) can be equipped with an Event Data Recorder that employs the integrated circuit <NUM>.

<FIG> shows a schematic view of method <NUM> according to an embodiment of the present invention. The method <NUM> is for network data processing and network data logging and therefore comprises a first step of processing <NUM>, by a first processor <NUM> of an integrated circuit <NUM>, multiple network packets <NUM> obtained from one or more input ports <NUM> of the integrated circuit <NUM>, and forwarding, by the first processor <NUM>, the multiple packets <NUM> towards one or more output ports <NUM> of the integrated circuit <NUM>.

The method <NUM> comprises a second step of obtaining <NUM>, by a coprocessor <NUM> of the integrated circuit <NUM>, duplicates <NUM> of the multiple network packets <NUM> from the first processor <NUM> and/or from the integrated circuit <NUM>, wherein the coprocessor <NUM> is separate from the first processor <NUM>.

The method <NUM> comprises a third step of aggregating <NUM>, by the coprocessor <NUM>, logging network information <NUM> based on the duplicates <NUM> of the multiple network packets <NUM>, wherein the logging network information <NUM> comprises information <NUM> about the multiple network packets <NUM>.

<FIG> shows a schematic view of a system <NUM> according to an embodiment of the present invention. The system <NUM> is for simulation a network system, in particular by means of digital twin technology. The system <NUM> therefore comprises the integrated circuit <NUM> according as it was described in any of the above embodiments and a simulation device <NUM>. To allow for simulation of a network system, the integrated circuit <NUM> is configured to provide the logging network information <NUM> to the simulation device <NUM>. The simulation device <NUM> in tum is configured to implement digital twin technology for processing the logging network information <NUM>.

By means of the digital twin technology which processes the logging network information <NUM>, a simulation device or computer can emulate and predict the behavior of an integrated circuit <NUM> itself or of a network system in real-time. Such an implementation may also be called network digital twin. Apart from the network digital twin, an application oriented digital twin can be provided on top, based on the information transferred in the network packets <NUM> that are logged. For instance, to simulate the behavior of a battery (state-of-charge, state-of-health) in a vehicle, based on data related to temperature, voltage and current provided in the logged data frames.

Moreover, the system <NUM> can be able to undo or unpack the logging network information <NUM> in order to extract and recover the original network packets <NUM>. For instance, in case of implementing a digital twin, the digital twin makes use of the same network packets <NUM> that were processed at real-time in the integrated circuit. They are totally free of interference, and through the timestamp field attached to the header of each network packet <NUM>, they provide real-time information relating to this network packet <NUM>.

<FIG> shows a schematic view of a method according to an embodiment of the present invention. The method <NUM> comprises a first step of providing <NUM>, by the integrated circuit <NUM> as described in view of any of the above figures, logging network information <NUM> to a simulation device <NUM>.

The method <NUM> comprises a second step of implementing <NUM>, by the simulation device <NUM>, digital twin technology for processing the logging network information <NUM>.

According to certain embodiments, in order for the simulation device <NUM> and/or the digital twin to make use of the network packets <NUM>, the aggregation steps (which can be also called formatting steps) done by the coprocessor <NUM> can be reverted to obtain the network packets <NUM> from the logging network information <NUM> (e.g. by undoing the formatting, and/or by decompression, and/or by decryption, and/or by removing timestamps of the logging network information <NUM> to recover the original network packets <NUM>). Once this preprocessing step is performed to obtain the original data, then it is possible to run the simulation or the digital twin.

Claim 1:
An integrated circuit (<NUM>) for network data processing and network data logging, wherein the integrated circuit (<NUM>) comprises:
- a first processor (<NUM>) configured to process multiple network packets (<NUM>) obtained from one or more input ports (<NUM>) of the integrated circuit (<NUM>) and to forward the multiple network packets (<NUM>) towards one or more output ports (<NUM>) of the integrated circuit (<NUM>), and
- a coprocessor (<NUM>) separate from the first processor (<NUM>), configured to obtain duplicates (<NUM>) of the multiple network packets (<NUM>) from the first processor (<NUM>) and/or from the integrated circuit (<NUM>), and to aggregate logging network information (<NUM>) based on the duplicates (<NUM>) of the multiple network packets (<NUM>), wherein the logging network information (<NUM>) comprises information (<NUM>) about the multiple network packets (<NUM>),
wherein the duplicates (<NUM>) relate to multiple input ports (<NUM>) of the integrated circuit (<NUM>), and wherein the coprocessor (<NUM>) is further configured to arrange the duplicates in a chronological and/or a serial order, to aggregate the logging network information (<NUM>).