Patent Description:
RRAM is a type of memory that encodes information in the resistive state of an RRAM cell. For example, the RRAM cell may have various different physical states that it can occupy, each with a different resistance. The value stored in the RRAM cell can be read by applying a voltage to the RRAM cell and measuring a resulting current. A resistance of the RRAM cell can then be determined from the measured current. Document <CIT> illustrates a quasi-nanowire transistor made of silicon /silicon-germanium stack deposited on a SOI substrate. Document <CIT> describes a three-dimensional phase change memory device containing vertically constricted current paths and document <CIT> shows three-dimensional resistive random access memory (ReRAM) devices with vertically alternating stacks of electrically conductive layers and dielectric material layers formed on a substrate.

A method of forming a settable resistance device includes isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor layer, to selectively form divots in exposed sidewalls of the conductor layer. The stack of layers is isotropically etched to selectively form divots in exposed sidewalls of the insulator layer, thereby forming a tip at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the stack of layers to cover the tip. An electrode is formed over the dielectric layer, such that the dielectric layer is between the electrode and the tip.

A settable resistance cell includes a stack of layers that includes an insulator layer in contact with a conductor layer, each having concave sidewall surfaces that meet at an interface between the insulator layer and the conductor layer to form a tip to focus electrical field strength. A dielectric layer is formed over the stack of layers that covers the tip. An electrode is formed over the dielectric layer, such that the dielectric layer is positioned between the electrode and the tip.

A neuromorphic computing device includes an array of settable resistance cells. Each settable resistance cell includes a stack of layers that includes an insulator layer in contact with a conductor layer, each having concave sidewall surfaces that meet at an interface between the insulator layer and the conductor layer to form a tip to focus electrical field strength, a dielectric layer formed over the stack of layers that covers the tip, and an electrode formed over the dielectric layer, such that the dielectric layer is positioned between the electrode and the tip.

These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

The following description will provide details of preferred embodiments with reference to the following figures wherein:.

Resistive random access memory (RRAM) cells may be formed using a memristor element, for example formed from a hafnium oxide. During operation, a defect may be formed in the dielectric material that can be programmed to different resistive states, which may correspond to different logic states. For example, a low-resistance state may equate to a logical '<NUM>', while a high-resistance state may equate to a logical '<NUM>'. Thus, a RRAM cell may have a settable resistance. A change between these states may be triggered electrically, for example by changing the polarity of an electrical field across the memristor element. Such RRAM cells can be used for classic memory applications, as well as in neuromorphic computing applications, where a resistive memory cell may be used to perform computations in neural network models.

One way to implement a memristor element uses a hafnium oxide dielectric layer. Conductive filaments may form in hafnium oxide under an appropriate electrical field, which provide a conductive path through the dielectric layer. However, the formation of such filaments can be random, with edge effects becoming more obvious due to etching damage as the cell size scales down. To help localize the formation of such filaments, tipped structures may be formed that help to focus the electric field. The control voltage may then be reduced, and the likelihood of forming filaments is increased relative to the likelihood of forming filaments at less useful positions. Thus, filaments may form preferentially at the tipped structures. As to the voltage, RRAM cells that do not include tips to enhance field strength may operate at voltages between about 1V and about 3V, whereas RRAM cells that do include such tipped structures may operate at significantly lower voltages. In one illustrative example, RRAM cells with tipped structures may operate at about <NUM>. 5V or less.

During operation, the filament may be formed from a redox operation, within the dielectric layer. Mechanisms responsible for this include the electrochemical metallization effect (ECM) and the valence change memory effect (VCM). In ECM, the conductive path of the switching layer may be formed by metal cations of an electrochemically active electrode under an electric field. For VCM, migration of anions (e.g., oxygen vacancies) contributes to the formation of a conductive path within the oxide layer. VCM may use an oxygen scavenging layer to facilitate anionic movement between the electrodes.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an RRAM cell is shown. A stack of layers <NUM> is formed on a substrate <NUM>. The stack <NUM> may include alternating dielectric layers <NUM> and conductor layers <NUM>, with a lowest dielectric layer <NUM> being positioned below a lowest conductor layer <NUM> to prevent leakage currents between the conductor layer <NUM> and the substrate <NUM>. Although seven layers are shown in the stack <NUM> for simplicity of illustration, it should be understood that any appropriate number of layers may be used. For example, structures formed in processes designed around NAND memory may have hundreds of layers.

The substrate <NUM> may be a bulk-semiconductor substrate. In one example, the bulk-semiconductor substrate may be a silicon-containing material. Illustrative examples of silicon-containing materials suitable for the bulk-semiconductor substrate include, but are not limited to, silicon, silicon germanium, silicon germanium carbide, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide. Although not depicted in the present figures, the substrate <NUM> may also be a semiconductor on insulator (SOI) substrate.

Additionally, the substrate <NUM> may be a device layer that may include a variety of different components, including active devices such as transistors, passive electrical devices such as resistors, capacitors, or inductors, interconnects such as conductive lines, vias, and contacts, and isolation structures such as interlayer dielectrics and shallow trench isolation regions.

It is specifically contemplated that the conductor layers <NUM> may be formed from titanium nitride or other titanium-base materials, tantalum-based materials (e.g., TaN), or tungsten-based materials (e.g., WxNy), but it should be understood that any appropriate conductive material may be used instead. Other exemplary conductive materials may include, e.g., e.g., titanium, tantalum, tungsten, nickel, molybdenum, copper, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, cobalt, and alloys thereof.

It is specifically contemplated that the insulator layers <NUM> may be formed from such materials as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonide nitride (SiCN), or silicon oxide (SiOx), but it should be understood that any appropriate dielectric material may be used instead.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an RRAM cell is shown. The original layer stack <NUM> is patterned to form device stack <NUM>. The device stack <NUM> includes exposed sidewalls of the dielectric layers <NUM> and the conductor layers <NUM>.

Forming the device stack <NUM> from the layer stack <NUM> may be performed using any appropriate patterning process, such as by photolithography to form a mask <NUM>, followed by one or more anisotropic etches. For example, reactive ion etching (RIE) is a form of plasma etching in which during etching the surface to be etched is placed on a radio-frequency powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface. Other examples of anisotropic etching that can be used at this point of the present invention include ion beam etching, plasma etching or laser ablation.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an RRAM cell is shown. A selective isotropic etch, such as a wet or dry chemical etch, is performed that targets the material of the conductor layers <NUM>, leaving the dielectric layers <NUM> and the substrate <NUM> relatively undamaged. The etch creates concave divots <NUM> at the sidewalls of the conductor layers <NUM>. As used herein, the term "selective" in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an RRAM cell is shown. A selective isotropic etch, such as a wet or dry chemical etch, is performed that targets the material of the insulator layers <NUM>, leaving the conductor layers <NUM> relatively undamaged. The etch creates concave divots <NUM> at the sidewalls of the insulator layers <NUM>. It should be understood that the etches of the insulator layers <NUM> and the conductor layers may <NUM>, shown in <FIG>, may be performed in any appropriate order.

Each of these isotropic etches has a greater rate of material removal near the center of their respective layers, such that the concave divots <NUM> and <NUM> have a curved profile. At the boundaries between each pair of a dielectric layer <NUM> and a conductor layer <NUM>, these curved profiles meet and create tips <NUM>.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an RRAM cell is shown. A layer of dielectric material <NUM> is conformally deposited over the device stack <NUM>, covering the tips <NUM>, for example using a deposition process like chemical vapor deposition (CVD) or atomic layer deposition (ALD). The dielectric material <NUM> can have a thickness of about <NUM> to about <NUM> nanometers. Specific illustrative embodiments may have thicknesses that range between about <NUM> to about <NUM>. Specific illustrative embodiments may have thicknesses that range between about <NUM> to about <NUM>. In some embodiments, RRAM dielectric material <NUM> is a high-k dielectric material. In some embodiments, the dielectric material <NUM> is a transitional metal oxide. Examples of materials that can be suitable for RRAM cell dielectrics include nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, and strontium titanium oxide.

CVD is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (e.g., from about <NUM> about <NUM>). The solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. In alternative embodiments that use ALD, chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an RRAM cell is shown. A top electrode <NUM> is formed, for example by conformally depositing a conductive material over the dielectric material <NUM>. The top electrode <NUM> may include an aluminum-containing alloy (for example, TiAl, TiAlC, TaAl, or TaAlC), titanium, tantalum, a combination including at least one of the foregoing, or a stack structure of metal nitride (for example, titanium nitride, tantalum nitride, or tungsten nitride). An illustrative stack structure may include titanium nitride and TiAlC. The top electrode <NUM> may further include tungsten, molybdenum, platinum, hafnium, copper, aluminum, gold, nickel, iridium or a combination including at least one of the foregoing.

During operation, the conductive layers <NUM> act as a first electrode, and the top electrode <NUM> acts as a second electrode. A current may be passed through the electrodes, across the dielectric material <NUM>, to determine the resistance of the dielectric material.

Referring now to <FIG>, a top-down view of the RRAM cell of <FIG> is shown. This view indicates two cross-sections: Cross-section A identifies the location of the cross-sectional view shown in <FIG>, while cross-section B identifies the location of a cross-sectional view that is referred to in the discussion below to illustrate different interconnect positions.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an RRAM cell is shown. This view is shown along cross-section B of <FIG>. This view shows the top electrode <NUM> over the device stack <NUM>. A word line electrode <NUM> is formed in a via that penetrates the device stack <NUM>, making contact with the conductor layers <NUM>. An interlayer dielectric <NUM> is formed over the device stack <NUM> and between the top electrode <NUM> and the word line electrode <NUM>. In this example, the conductor layers <NUM> are all tied to a single word line electrode <NUM>.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an alternative RRAM cell is shown. This view is also shown along cross-section B of <FIG>. In this example, the device stack <NUM> is etched into a stepped stack <NUM>, with each conductor layer <NUM> being etched to a different length. This may be performed by repeated masking and etching, where each conductor layer <NUM> and the corresponding dielectric layer <NUM> is selectively etched according to a respective mask. A new mask may then be formed before etching the next layer down, to protect a larger surface on the next layer.

Multiple different wordline electrodes <NUM> are formed to contact the different conductor layers <NUM>. An interlayer dielectric <NUM> is formed around the top electrode <NUM> and the multiple wordline electrodes <NUM>. In this manner, different conductor layers <NUM> can be addressed separately.

Referring now to <FIG>, a cross-sectional view of a step in the formation of an alternative RRAM cell is shown. This view is also shown along cross-section B of <FIG>. In this example, as in the example of <FIG>, multiple wordline electrodes <NUM> may be formed. Additionally, this example shows multiple bitline electrodes <NUM>, in lieu of the single top electrode <NUM>. Any appropriate number of such bitline electrodes <NUM>, with each contacting the sidewalls of the conductor layers <NUM> by way of the dielectric material <NUM>.

Referring now to <FIG>, a method of forming an RRAM cell is shown. Block <NUM> forms a stack <NUM> of alternating dielectric layers <NUM> and conductor layers <NUM>, for example by alternating deposition processes. Block <NUM> then patterns the stack <NUM> to form device stack <NUM>, for example using a photolithographic mask <NUM> and an anisotropic etch.

Block <NUM> performs an isotropic etch that is selective to the conductor layers <NUM>, forming divots <NUM> at the sidewalls of the conductor layers <NUM>. Block <NUM> performs an isotropic etch that is selective to the dielectric layers <NUM>, forming divots <NUM> at the sidewalls of the dielectric layers <NUM>. Blocks <NUM> and <NUM> can be performed in any order, for example with the etch of the dielectric layers <NUM> being performed before the etch of the conductor layers <NUM>.

Block <NUM> forms the dielectric layer <NUM> over the device stack <NUM>, for example using a conformal deposition process to deposit a high-k dielectric material over the tips <NUM> that were formed by the formation of the divots <NUM> and <NUM>. Top electrode(s) <NUM> may be formed over the device stack <NUM>, providing an electrical connection to the conductor layers <NUM> through the dielectric layer <NUM>. Block <NUM> may form wordline electrode(s) <NUM> to provide direct electrical contact to one or more conductor layers <NUM> by forming a via through the device stack <NUM> and forming a conductive material therein.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.

It will also be understood that when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present.

The present embodiments may include a design for an integrated circuit chip, which may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe<NUM>-x where x is less than or equal to <NUM>, etc. In addition, other elements may be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

Reference in the specification to "one embodiment" or "an embodiment" of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment", as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following "/", "and/or", and "at least one of", for example, in the cases of "A/B", "A and/or B" and "at least one of A and B", is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of "A, B, and/or C" and "at least one of A, B, and C", such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated <NUM> degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

In some embodiments, RRAM cells may be used for neuromorphic computing in a neural network. An artificial neural network (ANN) is an information processing system that is inspired by biological nervous systems, such as the brain. One element of ANNs is the structure of the information processing system, which includes a large number of highly interconnected processing elements (called "neurons") working in parallel to solve specific problems. ANNs are furthermore trained using a set of training data, with learning that involves adjustments to weights that exist between the neurons. An ANN is configured for a specific application, such as pattern recognition or data classification, through such a learning process.

Referring now to <FIG>, a generalized diagram of a neural network is shown. Although a specific structure of an ANN is shown, having three layers and a set number of fully connected neurons, it should be understood that this is intended solely for the purpose of illustration. In practice, the present embodiments may take any appropriate form, including any number of layers and any pattern or patterns of connections therebetween.

ANNs demonstrate an ability to derive meaning from complicated or imprecise data and can be used to extract patterns and detect trends that are too complex to be detected by humans or other computer-based systems. The structure of a neural network is known generally to have input neurons <NUM> that provide information to one or more "hidden" neurons <NUM>. Connections <NUM> between the input neurons <NUM> and hidden neurons <NUM> are weighted, and these weighted inputs are then processed by the hidden neurons <NUM> according to some function in the hidden neurons <NUM>. These weights <NUM> may be implemented using the settable resistance devices described above.

There can be any number of layers of hidden neurons <NUM>, and as well as neurons that perform different functions. There exist different neural network structures as well, such as a convolutional neural network, a maxout network, etc., which may vary according to the structure and function of the hidden layers, as well as the pattern of weights between the layers. The individual layers may perform particular functions, and may include convolutional layers, pooling layers, fully connected layers, softmax layers, or any other appropriate type of neural network layer. Finally, a set of output neurons <NUM> accepts and processes weighted input from the last set of hidden neurons <NUM>.

This represents a "feed-forward" computation, where information propagates from input neurons <NUM> to the output neurons <NUM>. Upon completion of a feed-forward computation, the output is compared to a desired output available from training data. The error relative to the training data is then processed in "backpropagation" computation, where the hidden neurons <NUM> and input neurons <NUM> receive information regarding the error propagating backward from the output neurons <NUM>. Once the backward error propagation has been completed, weight updates are performed, with the weighted connections <NUM> being updated to account for the received error. It should be noted that the three modes of operation, feed forward, back propagation, and weight update, do not overlap with one another. This represents just one variety of ANN computation, and that any appropriate form of computation may be used instead.

To train an ANN, training data can be divided into a training set and a testing set. The training data includes pairs of an input and a known output. During training, the inputs of the training set are fed into the ANN using feed-forward propagation. After each input, the output of the ANN is compared to the respective known output. Discrepancies between the output of the ANN and the known output that is associated with that particular input are used to generate an error value, which may be backpropagated through the ANN, after which the weight values of the ANN may be updated. This process continues until the pairs in the training set are exhausted.

After the training has been completed, the ANN may be tested against the testing set, to ensure that the training has not resulted in overfitting. If the ANN can generalize to new inputs, beyond those which it was already trained on, then it is ready for use. If the ANN does not accurately reproduce the known outputs of the testing set, then additional training data may be needed, or hyperparameters of the ANN may need to be adjusted.

ANNs may be implemented in hardware. For example, each weight <NUM> may be characterized as a weight value that is stored as a resistive value of a resistive processing unit (RPUs), generating a predictable current output when an input voltage is applied in accordance with a settable resistance.

Referring now to <FIG>, a hardware architecture <NUM> for an ANN is shown. It should be understood that the present architecture is purely exemplary, and that other architectures or types of neural network can be used instead. The hardware embodiment described herein is included with the intent of illustrating general principles of neural network computation at a high level of generality and should not be construed as limiting in any way.

Furthermore, the layers of neurons described below and the weights connecting them are described in a general manner and can be replaced by any type of neural network layers with any appropriate degree or type of interconnectivity. For example, layers can include convolutional layers, pooling layers, fully connected layers, softmax layers, or any other appropriate type of neural network layer. Furthermore, layers can be added or removed as needed, and the weights described herein can be replaced with more complicated forms of interconnection.

During feed-forward operation, input neurons <NUM> each provide an input voltage in parallel to a respective row of weights <NUM>. As noted above, the weights <NUM> can be implemented in hardware, for example using the settable resistance cells described above. In the hardware embodiment described herein, the weights <NUM> each have a settable resistance value, such that a current output flows from the weight <NUM> to a respective hidden neuron <NUM>. The current output by the weight <NUM> therefore represents a weighted input to the hidden neuron <NUM>.

Following the hardware embodiment, the current output by a given weight <NUM> is determined as <MAT>, where V is the input voltage from the input neuron <NUM> and r is the set resistance of the weight <NUM>. The currents from each of the weights <NUM> add column-wise and flow to a hidden neuron <NUM>.

A set of reference weights <NUM> have a fixed resistance and combine their outputs into a reference current that is provided to each of the hidden neurons <NUM>. Because conductance values can only be positive numbers, some reference conductance is needed to encode both positive and negative values in the matrix. The currents produced by the weights <NUM> are continuously valued and positive, and therefore the reference weights <NUM> are used to provide a reference current, above which currents are considered to have positive values and below which currents are considered to have negative values. As an alternative to using the reference weights <NUM>, another embodiment can use separate arrays of weights <NUM> to capture negative values.

The hidden neurons <NUM> use the currents from the array of weights <NUM> and the reference weights <NUM> to perform some calculation. This calculation may be, for example, any appropriate activation function, and may be implemented in hardware using appropriate circuitry, or in software.

The hidden neurons <NUM> then output a voltage of their own, based on the activation function, to another array of weights <NUM>. This array performs its weighting calculations in the same way, with a column of weights <NUM> receiving a voltage from their respective hidden neuron <NUM> to produce a weighted current output that adds row-wise and is provided to the output neuron <NUM>.

It should be understood that any number of these stages can be implemented, by interposing additional layers of arrays and hidden neurons <NUM>. It should also be noted that some neurons can be constant neurons <NUM>, which provide a constant output to the array. The constant neurons <NUM> can be present among the input neurons <NUM> and/or hidden neurons <NUM> and are only used during feed-forward operation.

During back propagation, the output neurons <NUM> provide a voltage back across the array of weights <NUM>. The output layer compares the generated network response to training data and computes an error. The error is applied to the array as a voltage pulse, where the height and/or duration of the pulse is modulated proportional to the error value. In this example, a row of weights <NUM> receives a voltage from a respective output neuron <NUM> in parallel and converts that voltage into a current which adds column-wise to provide an input to hidden neurons <NUM>. The hidden neurons <NUM> combine the weighted feedback signal with a derivative of its feed-forward calculation and stores an error value before outputting a feedback signal voltage to its respective column of weights <NUM>. This back propagation travels through the entire network <NUM> until all hidden neurons <NUM> and the input neurons <NUM> have stored an error value.

The weight update process will depend on how the weights <NUM> are implemented. For settable resistances that include phase change materials, the input neurons <NUM> and hidden neurons <NUM> may apply a first weight update voltage forward and the output neurons <NUM> and hidden neurons <NUM> may apply a second weight update voltage backward through the network <NUM>. The combinations of these voltages may create a state change within each weight <NUM>, causing the weight <NUM> to take on a new resistance value, for example by raising a temperature of the weight <NUM> above a threshold and thus changing its resistance. In this manner the weights <NUM> can be trained to adapt the neural network <NUM> to errors in its processing.

Claim 1:
A method of forming a settable resistance device, comprising:
isotropically etching a stack of layers (<NUM>), the stack of layers (<NUM>) having an insulator layer (<NUM>) in contact with a conductor layer (<NUM>), to selectively form divots in exposed sidewalls of the conductor layer (<NUM>);
isotropically etching the stack of layers (<NUM>) to selectively form divots (<NUM>, <NUM>) in exposed sidewalls of the insulator layer (<NUM>), thereby forming a tip (<NUM>) at an interface between the insulator layer (<NUM>) and the conductor layer (<NUM>);
forming a dielectric layer (<NUM>) over the stack of layers (<NUM>) to cover the tip (<NUM>); and
forming an electrode (<NUM>) over the dielectric layer (<NUM>), such that the dielectric layer (<NUM>) is between the electrode (<NUM>) and the tip (<NUM>).