Patent Description:
The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof.

With the development of semiconductor technologies, the memory, especially a dynamic random access memory (DRAM) is widely used in various electronic devices due to its high storage density and fast reading and writing speed.

The DRAM usually includes a plurality of memory cells. Each memory cell includes a transistor and a capacitor. A gate of the transistor is electrically connected to a word line (WL) of the DRAM. The on and off of the transistor is controlled by the voltage on the WL. One of a source and a drain of the transistor is electrically connected to a bit line (BL), and the other is electrically connected to the capacitor. Data information is stored or outputted by the BL.

To reduce the size of the memory and increase its storage density, the capacitor is usually placed horizontally, which facilitates manufacturing a capacitor with a larger slenderness ratio. Correspondingly, the transistor is also placed horizontally, and the transistor is led out to a BL plug through the BL to be electrically connected to a peripheral circuit. However, the contact resistance between the BL and the BL plug affects the speed of signal propagation, resulting in lower overall performance of the semiconductor structure. Related technology is known from <CIT>, <CIT> and <CIT>.

In view of the above problem, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, to improve the performance of the semiconductor structure. The invention is defined by the independent claim.

The dependent claims set out particular embodiments of the invention.

In the related art, the transistor and capacitor are placed horizontally. To connect the transistor to the peripheral circuit, a stepped BL is usually formed at one end of the transistor, and then a BL plug in contact with it is formed on the stepped BL. The BL and the peripheral circuit are electrically connected through the BL plug. The extension direction of the BL is usually perpendicular to that of the BL plug, and a contact area between the BL and the BL plug is limited, resulting in a high contact resistance between them, and reducing the speed of signal propagation, thus decreasing the performance of the semiconductor structure. In addition, in the stepped BLs, the BL is of a horizontal structure, and an insulating material fills a space between adjacent BLs. Therefore, in a normal process, it is difficult to dope the entire BL. As a result, the BL resistance is relatively large, the signal propagation speed is decreased, and the overall performance of the transistor is affected, thus decreasing the performance of the semiconductor structure.

In view of this, the embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The BL includes a first core layer and a first conductive layer covering the first core layer. The BL plug is in contact with the first conductive layer. The material of the first conductive layer is adjusted, to reduce the contact resistance between the BL plug and first conductive layer and improve the speed of signal propagation, thereby improving the performance of the semiconductor structure. The materials of the first conductive layer and the first core layer are adjusted, to realize ohmic contact between them, thereby reducing the resistance of the BL. In addition, a contact area between the first conductive layer and the first core layer is relatively large, which is beneficial to reducing the contact resistance between them, thereby reducing the resistance of the BL. When the first core layer is formed, a structure filling a space between the first core layers is removed through an etching process, to make the first core layer suspended. Moreover, vapor doping is performed on the first core layer, thereby doping the entire first core layer. It is beneficial to reducing the conductive resistance of the first core layer, thereby further reducing the resistance of the BL.

To make the objectives, features and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure are described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely some rather than all of the embodiments of the present disclosure.

A first aspect of the embodiments of the present disclosure provides a semiconductor structure. The semiconductor structure may be a memory device or a non-memory device. The memory device may include, for example, a DRAM, a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magneto-resistive random access memory (MRAM). The non-memory device may be a logic device, such as, a micro-processor unit (MPU), a digital signal processor (DSP), or a micro-controller unit (MCU), or a similar device. In the embodiments of the present disclosure, description is made by the DRAM as an example.

With reference to <FIG>, the semiconductor structure includes a substrate <NUM>, a WL <NUM>, a BL <NUM>, and a BL plug <NUM>. The substrate <NUM> is configured for supporting and may be made of a semiconductor such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide (SiC), silicon germanium (SiGe), germanium on insulator (GOI), silicon on insulator (SOI), or another material known to those skilled in the art.

A first stacked structure is disposed on the substrate <NUM>. The first stacked structure includes a memory cell array, which is configured to store data. The WL <NUM> extends along the first direction and is disposed in the first stacked structure. The WL <NUM> is electrically connected to the memory cell array and is configured to control the opening or closing of the memory cell array. The BL <NUM> extends along the second direction, is electrically connected to the memory cell array, and is configured to write data information into the memory cell array or read data information in the memory cell array. The BL plug <NUM> is in contact with the BL <NUM>, such that they are electrically connected, thereby electrically connecting the BL <NUM> to the peripheral circuit.

Specifically, with reference to <FIG>, the memory cell array includes a plurality of transistors <NUM>, and the plurality of transistors <NUM> are arranged at intervals along the first direction and the second direction, and each transistor extends along a third direction. The third direction is perpendicular to both of the first direction and the second direction.

In some possible embodiments, as shown in <FIG>, the plurality of transistors <NUM> may be arranged in an array. The plurality of transistors <NUM> are arranged at intervals not only along the first direction, but also along the second direction. The first direction and the second direction cross each other. The second direction is parallel to the substrate <NUM>. The third direction is also parallel to the substrate <NUM>. The third direction is perpendicular to the first direction and to the second direction.

Any two of the first direction, the second direction, and the third direction are perpendicular to each other, that is, the first direction is also perpendicular to the second direction. For example, the first direction is the direction Z shown in <FIG>, the second direction is the direction X shown in <FIG>, and the third direction is the direction Y shown in <FIG>. In this manner, the plurality of transistors <NUM> can be arranged more compact, and the arrangement quantity of the transistors <NUM> can be maximized, thereby improving storage density of the memory cell array.

In some possible embodiments, with reference to <FIG> and <FIG>, the transistor <NUM> includes a source, a drain, a channel <NUM>, a dielectric layer <NUM>, and a gate. The source or drain is electrically connected to the BL <NUM>. For example, the drain is electrically connected to the BL <NUM>. The channel <NUM> is disposed between the source and the drain, and the source, the channel <NUM>, and the drain are arranged sequentially along the third direction. The gate surrounds the channel <NUM> and is electrically connected to the WL <NUM>. A dielectric layer <NUM> is disposed between the gate and the channel <NUM>.

The material of the source and the drain may be metal or semiconductor, such as molybdenum (Mo) or polysilicon. The material of the channel <NUM> may be indium gallium zinc oxide (IGZO), SiGe, SiC, or the like. The material of the gate may be metal or its alloy, such as titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), and the like. The dielectric layer <NUM> may be made of an insulating material, such as silicon oxide (SiO<NUM>), silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO<NUM>), hafnium silicon oxide (HfSiO<NUM>), lanthanum oxide (LaO), zirconium oxide (ZrO<NUM>), zirconium oxide silicon (ZrSiO<NUM>), tantalum oxide (Ta<NUM>O<NUM>), titanium oxide (TiO<NUM>), barium strontium titanium oxide (BaSrTiO<NUM>), barium titanium oxide (BaTiO<NUM>), strontium titanium oxide (SrTiO<NUM>), lithium oxide (Li<NUM>O), alumina (Al<NUM>O<NUM>), lead scandium tantalum oxide (PbScTaO), lead zinc niobate (PbZnNbO<NUM>), or a combination thereof.

In some possible implementations, the plurality of WLs <NUM> are provided, extend along the first direction (the direction Z in <FIG>), and are arranged at intervals along the second direction (the direction X in <FIG>), to ensure that adjacent WLs <NUM> are electrically isolated, and prevent the WLs <NUM> from interfering each other. Each WL <NUM> surrounds the plurality of channels <NUM> in a same column along the first direction. Each BL <NUM> connects a plurality of drains located in the same row along the second direction. In such a manner, the arrangement of the WLs <NUM> and the BLs <NUM> can be optimized, and they occupy a smaller space, to increase the arrangement quantity of the transistors <NUM>, thereby improving the storage density of the semiconductor structure.

In this case, the WL <NUM> is used as the gate of the transistor <NUM> to enable the transistor <NUM> to be a vertical gate-all-around (GAA) transistor <NUM>. Because the feature size of the vertical GAA transistor is small, when they are disposed in a substrate with a same area, the integration of the semiconductor structure can be improved. At the same time, the channel control ability of the gate and the short channel effect can be also improved.

In some possible embodiments, with reference to <FIG> and <FIG>, the memory cell array further includes a plurality of capacitors <NUM>. The plurality of capacitors <NUM> are electrically connected to the plurality of transistors <NUM> in a one-to-one correspondence. The plurality of capacitors <NUM> extend along the third direction and are arranged at intervals, such that the capacitors <NUM> are placed horizontally on the substrate <NUM>, and the capacitor <NUM> is unlikely to collapse, and has a larger slenderness ratio, thereby improving the storage capacity of the semiconductor structure. One of the source and drain of the transistor <NUM> is connected to the BL <NUM>, and the other is connected to the capacitor <NUM>. For example, the source of the transistor <NUM> is electrically connected to the BL <NUM>, and the drain of the transistor <NUM> is electrically connected to the capacitor <NUM>.

In some possible embodiments, with reference to <FIG> and <FIG>, the first stacked structure further includes: a plurality of support layers <NUM>, where the support layer <NUM> is disposed between two adjacent rows of transistors <NUM> along the first direction; and an isolation layer <NUM>, where the isolation layer <NUM> fills the remaining space of the first stacked structure. The remaining space refers to a space between adjacent transistors <NUM>, between adjacent capacitors <NUM>, and between the transistor <NUM> and the capacitor <NUM> without the support layer <NUM>. The support layer <NUM> is disposed, to support the transistor <NUM>, to prevent it from collapsing, and facilitate the stacking of the transistors <NUM> in the first direction. The isolation layer <NUM> is disposed to electrically isolate the transistors <NUM> and the capacitors <NUM> in the memory cell array and prevent the transistors <NUM> and the capacitors <NUM> in the memory cell array from interfering with each other.

In some possible embodiments, a plurality of support layers <NUM> are arranged at intervals along the third direction, fill spaces between adjacent transistors <NUM> and are integrated. Specifically, the support layer <NUM> is disposed on the substrate <NUM> and is penetrated by the transistor <NUM>, that is, the support layer <NUM> is substantially in the shape of a mesh with a plurality of mesh holes arranged at intervals. Each transistor <NUM> passes through one mesh hole of the support layer <NUM> and fills the mesh hole. In this way, it facilitates manufacturing the support layer <NUM>, and the support layer can prevent the transistor <NUM> from collapsing. The material of the support layer <NUM> may be a material that is relatively tough, and is unlikely to collapse or not easy to etch, for example, SiON or SiN, to improve the stability of the first stacked structure.

In some possible embodiments, with reference to <FIG>, in the embodiments of the present disclosure, the plurality of BLs <NUM> are provided, extend along the second direction (the direction X in <FIG>), and are stacked along the first direction (the direction Z in <FIG>) and arranged at intervals, to electrically isolate adjacent BLs <NUM>.

The BL <NUM> is disposed beside the first stacked structure. For example, with reference to <FIG>, the BL <NUM> is disposed on the left side of the first stacked structure, to be electrically connected to the transistor <NUM> in the first stacked structure. Specifically, the BL <NUM> and the capacitor <NUM> are respectively located at opposite sides of the transistor <NUM> along the third direction (the direction Y shown in <FIG>). The end of the BL <NUM> is in contact with the source or the drain of the transistor <NUM>, such that the BL <NUM> is electrically connected to the transistor <NUM>.

Certainly, the position of the BL <NUM> is not limited in the embodiment of the present disclosure. For example, the BL <NUM> may further be disposed at any one of the two opposite sides of the first stacked structure along the second direction. Specifically, the BL <NUM> may also be disposed on the upper side or the lower side of the first stacked structure as shown in <FIG>. It should be noted that when the BL <NUM> is disposed on the upper side or the lower side of the first stacked structure, the BL <NUM> extends into the first stacked structure, to be electrically connected to the source or drain of the transistor <NUM> in the first stacked structure. For example, the BL <NUM> surrounds the source or drain of the transistor <NUM>.

With reference to <FIG>, one end of each of the plurality of BLs <NUM> away from the memory cell array forms a step. Specifically, along the direction away from the substrate <NUM>, the lengths of the plurality of BLs <NUM> are successively reduced, such that one end of each of the plurality of BLs <NUM> away from the memory cell array forms a step. In this way, in every two adjacent BLs <NUM>, a partial region of the BL <NUM> close to the substrate <NUM> is exposed, and is not blocked by the BL <NUM> away from the substrate <NUM>, such that a BL plug <NUM> is formed in the exposed partial region of the BL <NUM>, thereby electrically connecting the BL <NUM> to the peripheral circuit. As shown in <FIG>, the left side of each BL <NUM> is exposed, such that the BL plug <NUM> is formed at the left side of each BL <NUM>.

Specifically, each BL <NUM> includes a first core layer <NUM> and a first conductive layer <NUM> covering the first core layer <NUM>. As shown in <FIG>, the first conductive layer <NUM> covers a surface of the first core layer <NUM> opposite to the first direction and a side surface of the first core layer <NUM>, that is, the first conductive layer <NUM> covers the exposed surface of the first core layer <NUM>. The material of the first core layer <NUM> may be a semiconductor, such as silicon. The material of the first conductive layer <NUM> may be metal, a metal alloy, or a metal-semiconductor compound, such as titanium, nickel, cobalt, molybdenum, aluminum, metal silicide, and the like.

In this way, the materials of the first core layer <NUM> and the first conductive layer <NUM> are adjusted, to adjust and adapt their work functions, and realize the ohmic contact between the first core layer <NUM> and the first conductive layer <NUM>, such that the contact resistance is relatively small, thereby reducing the resistance of the BL <NUM>. In this case, the relatively large contact area between the first core layer <NUM> and the first conductive layer <NUM> can also reduce the contact resistance between the first core layer <NUM> and the first conductive layer <NUM>, to further decrease the resistance of the BL <NUM>.

At least one of the plurality of first core layers <NUM> is a N-type semiconductor or a P-type semiconductor. In other words, the N-type or P-type doping is performed on at least one of the first core layers <NUM>. In this way, the work function of the first core layer <NUM> can be adjusted by adjusting the doping concentration of the first core layer <NUM>, such that, on the one hand, the conductive resistance and the resistance of the first core layer <NUM> can be reduced, and on the other hand, the contact resistance between the first core layer <NUM> and the first conductive layer <NUM> can be reduced.

Further, each first core layer <NUM> is an N-type semiconductor or a P-type semiconductor, such that the contact resistance between each first core layer <NUM> and its corresponding first conductive layer <NUM> is reduced, thereby improving the performance of the semiconductor structure. For example, the N-type semiconductor is formed by doping elements such as phosphorus, arsenic, and antimony into the first core layer <NUM>, and the P-type semiconductor is formed by doping elements such as boron, aluminum, and indium into the first core layer <NUM>. Furthermore, the entire first core layer <NUM> can be doped through a vapor doping process, thereby reducing the resistance of the first core layer <NUM>, and a contact resistance between the first core layer <NUM> and the first conductive layer <NUM>.

With reference to <FIG>, in the embodiment of the present disclosure, a plurality of BL plugs <NUM> are provided, extend along the first direction, and are arranged at intervals along the third direction, such that the BL plugs <NUM> are isolated from each other, to prevent the BLs <NUM> from interfering with each other. The plurality of BL plugs <NUM> are staggered along the second direction. As shown in <FIG>, a connecting line of the plurality of BL plugs <NUM> and the second direction form an angle. In this way, the distance between adjacent BL plugs <NUM> is relatively large, and the mutual interference is small. Lengths of the plurality of BL plugs <NUM> change in a stepwise manner. In this way, the surfaces of the BL plugs <NUM> away from the substrate <NUM> are flush with each other. It facilitates making the connecting line thereon, to connect the peripheral circuit.

The plurality of BL plugs <NUM> are electrically connected to the plurality of BLs <NUM> in a one-to-one correspondence. Each BL plug <NUM> is in corresponding contact with the first conductive layer <NUM> of one BL <NUM>. The material of the first conductive layer <NUM> is adjusted, to reduce the contact resistance between the BL plug <NUM> and first conductive layer <NUM>, thereby reducing the contact resistance between the BL plug <NUM> and the BL <NUM>.

In some possible embodiments, the BL plug <NUM> includes a first conductive part, and a second conductive part disposed on the first conductive part. Orthographic projection of the second conductive part on the substrate <NUM> covers orthographic projection of the first conductive part on the substrate <NUM>.

Specifically, as shown in <FIG>, the second conductive part is located at a side of the first conductive part away from the substrate <NUM>. The lower surface of the second conductive part is in contact with the upper surface of the first conductive part, and the lower surface of the first conductive part is in contact with the upper surface of the first conductive layer <NUM>. The orthographic projection of the second conductive part on the substrate <NUM> covers orthographic projection of the first conductive part on the substrate <NUM>. It ensures that the first conductive part is electrically connected to the second conductive part. In the embodiment in which the lengths of the plurality of BL plugs <NUM> change in a stepwise manner, in a possible implementation, the lengths of the plurality of first conductive parts change in a stepwise manner, and the lengths of the plurality of second conductive parts are the same, such that the surfaces of the first conductive parts away from the substrate <NUM> are flush with each other. It is beneficial to manufacturing the first conductive part and the second conductive part.

In the embodiment in which the BL plug <NUM> includes the first conductive part and the second conductive part disposed on the first conductive part, the first conductive part includes a second core layer <NUM> and a first metal layer <NUM> covering the second core layer <NUM>. The first metal layer <NUM> covers the side surface of the second core layer <NUM> and the surface of the second core layer <NUM> facing the substrate <NUM>, such that the first metal layer <NUM> is in contact with the first conductive layer <NUM>, and the first metal layer <NUM> is in contact with the second conductive part, thereby electrically connecting the first metal layer <NUM> to the first conductive layer <NUM>, and electrically connecting the first metal layer <NUM> to the second conductive part.

The first metal layer <NUM> and the first conductive layer <NUM> are made of a same material. In this way, the first metal layer <NUM> is in contact with the first conductive layer <NUM>, or the two layers are integrated. There is no contact surface between the first metal layer <NUM> and the first conductive layer <NUM>, thereby reducing the contact resistance between the BL <NUM> and the BL plug <NUM>, and improving the performance of the semiconductor structure.

The second conductive part includes a third core layer <NUM> and a second metal layer <NUM> covering the third core layer <NUM>. The second metal layer <NUM> covers the side surface of the third core layer <NUM> and the surface of the third core layer <NUM> facing the substrate <NUM>, such that the second metal layer <NUM> is in contact with the first metal layer <NUM>, thereby electrically connecting the second metal layer <NUM> to the first metal layer <NUM>. The second core layer <NUM> and the third core layer <NUM> may be made of an insulating material. In this way, on the basis of ensuring the electrical properties of the first conductive part and the second conductive part, the thicknesses of the first metal layer <NUM> and the second metal layer <NUM> are reduced, to save the costs. Alternatively, the second core layer <NUM> and the third core layer <NUM> may further be made of a conductive material, to further reduce the resistance of the BL plug <NUM>. The second core layer <NUM> and the first metal layer <NUM> may be made of a same material or not, and/or the third core layer <NUM> and the second metal layer <NUM> may be made of a same material or not. It may be understood that when the second core layer <NUM> and the first metal layer <NUM> are made of a same material, the second core layer <NUM> and the first metal layer <NUM> are integrated. When the third core layer <NUM> and the second metal layer <NUM> are made of a same material, the third core layer <NUM> and the second metal layer <NUM> are integrated.

With reference to <FIG>, in some possible embodiments, the semiconductor structure further includes: a first insulating layer <NUM> filling a space between two adjacent ones of the BLs <NUM>, a first protective layer <NUM> covering the BLs <NUM> and the first insulating layer <NUM>, and a second insulating layer <NUM> filling a space between two adjacent ones of the BL plugs <NUM> and covering the first stacked structure, where a plurality of WL plugs <NUM> are arranged at intervals in the second insulating layer <NUM>, and the plurality of WL plugs <NUM> are electrically connected to the plurality of WLs <NUM> in a one-to-one correspondence.

Specifically, the first insulating layer <NUM> may further fill a space between adjacent BLs <NUM>, that is, the BL <NUM> and the first insulating layer <NUM> are stacked sequentially and alternately along the first direction. The first insulating layer <NUM> can not only isolate the BLs <NUM>, but also support the BLs <NUM>, to improve the stability of the BL <NUM>. Specifically, the first protective layer <NUM> covers the BL <NUM> and the first insulating layer <NUM>, to prevent the surface of the first conductive layer <NUM> of the BL <NUM> away from the substrate <NUM> from being exposed, and isolate and protect the first conductive layer <NUM>. The first protective layer <NUM> is formed in a stepped shape and may be made of SiN or SiON. The second insulating layer <NUM> fills a space between two adjacent BL plugs <NUM>, and covers the first stacked structure, to further ensure the insulating performance between the BL plugs <NUM>. The second insulating layer <NUM> is made of SiO<NUM>.

As shown in <FIG>, a plurality of WL plugs <NUM> are arranged at intervals in the second insulating layer <NUM>, and the plurality of WL plugs <NUM> extend along the first direction, and are electrically connected to the plurality of WLs <NUM> in a one-to-one correspondence, to connect the WL <NUM> to the peripheral circuit. It should be noted that the WL plug is not shown in <FIG>, which is a schematic structural diagram.

In conclusion, in the semiconductor structure provided by the embodiments of the present disclosure, the BL <NUM> includes a first core layer <NUM> and a first conductive layer <NUM> covering the first core layer <NUM>. The BL plug <NUM> is in contact with the first conductive layer <NUM>. The materials of the BL plug <NUM> and the first conductive layer <NUM> are adjusted, to reduce the contact resistance between the BL plug <NUM> and first conductive layer <NUM>, thereby reducing the contact resistance between the BL plug <NUM> and the BL <NUM>, and to improve the speed of signal propagation, thereby improving the performance of the semiconductor structure. The materials of the first conductive layer <NUM> and the first core layer <NUM> are adjusted, to realize ohmic contact between the first conductive layer <NUM> and the first core layer <NUM>, thereby reducing the resistance of the BL <NUM>. In addition, a contact area between the first conductive layer <NUM> and the first core layer <NUM> is relatively large, which is beneficial to reducing the contact resistance between them, thereby reducing the resistance of the BL <NUM>.

A second aspect of the embodiments of the present disclosure provides a manufacturing method of a semiconductor structure. With reference to <FIG>, the manufacturing method includes the following steps:
Step S10: Form a first stacked structure on a substrate, where the first stacked structure includes a memory cell array.

The substrate <NUM> is configured for supporting. The substrate <NUM> may be made of a semiconductor, such as, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, SiC, SiGe, GOI, or SOI. A first stacked structure is disposed on the substrate <NUM>. The first stacked structure includes a memory cell array, which is configured to store data. Specifically, with reference to <FIG>, the memory cell array includes a plurality of transistors <NUM>, and the plurality of transistors <NUM> are arranged at intervals along the first direction and the second direction, and each transistor extends along a third direction. The third direction is perpendicular to both of the first direction and the second direction.

The material of the source and the drain may be metal or semiconductor, such as Mo or polysilicon. The material of the channel <NUM> may be IGZO, SiGe, SiC, or the like. The material of the gate may be metal or its alloy, such as Ti, TiN, W, Al, and the like. The material of the dielectric layer <NUM> may be an insulating material, such as SiO<NUM>, SiN, SiON, HfO<NUM>, HfSiO<NUM>, LaO, ZrO<NUM>, ZrSiO<NUM>, Ta<NUM>O<NUM>, TiO<NUM>, BaSrTiO<NUM>, BaTiO<NUM>, SrTiO<NUM>, Li<NUM>O, Al<NUM>O<NUM>, PbScTaO, PbZnNbO<NUM>, or a combination thereof.

The memory cell array further includes a plurality of capacitors <NUM>. The plurality of capacitors <NUM> are electrically connected to the plurality of transistors <NUM> in a one-to-one correspondence. The plurality of capacitors <NUM> extend along the third direction and are arranged at intervals, such that the capacitors <NUM> are placed horizontally on the substrate <NUM>, and the capacitor <NUM> is unlikely to collapse, and has a larger slenderness ratio, thereby improving the storage capacity of the semiconductor structure. One of the source and drain of the transistor <NUM> is connected to the BL <NUM>, and the other is connected to the capacitor <NUM>. For example, the source of the transistor <NUM> is electrically connected to the BL <NUM>, and the drain of the transistor <NUM> is electrically connected to the capacitor <NUM>.

Step S20: Form, on the substrate, a plurality of WLs arranged at intervals and extending along a first direction, where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array.

In some possible implementations, the plurality of WLs <NUM> are provided, extend along the first direction (the direction Z in <FIG>), and are arranged at intervals along the second direction (the direction X in <FIG>), to ensure that adjacent WLs <NUM> are electrically isolated, and prevent the WLs <NUM> from interfering each other. Each WL <NUM> surrounds a plurality of channels <NUM> located in a same column along the first direction. In such a manner, the arrangement of the WLs <NUM> can be optimized, and they occupy a smaller space, to increase the arrangement quantity of the transistors <NUM>, thereby improving the storage density of the semiconductor structure. In this case, the WL <NUM> is used as the gate of the transistor <NUM> to enable the transistor <NUM> to be a vertical GAA transistor <NUM>. Because the feature size of the vertical GAA transistor is small, when they are disposed in a substrate <NUM> with a same area, the integration of the semiconductor structure can be improved. At the same time, the channel <NUM> control ability of the gate and the short channel <NUM> effect can be also improved.

In some possible embodiments, after the plurality of WLs <NUM> arranged at intervals and extending along the first direction are formed on the substrate <NUM>, the method further includes: forming a plurality of support layers <NUM> and an isolation layer <NUM>, where the support layer <NUM> is disposed between two adjacent rows of transistors <NUM> along the first direction; and the isolation layer <NUM> fills the remaining space of the first stacked structure. The support layer <NUM> is disposed, to support the transistor <NUM>, to prevent it from collapsing, and facilitate the stacking of the transistors <NUM> in the first direction. The isolation layer <NUM> is disposed to electrically isolate the transistors <NUM> and the capacitors <NUM> in the memory cell array and prevent the transistors <NUM> and the capacitors <NUM> in the memory cell array from interfering with each other.

In some possible embodiments, a plurality of support layers <NUM> are arranged at intervals along the third direction, fill spaces between transistors <NUM> and are integrated. For example, the support layer <NUM> is disposed on the substrate <NUM>, and is penetrated through by the transistor <NUM>. In this way, it facilitates manufacturing the support layer <NUM>, and the support layer can prevent the transistor <NUM> from collapsing. The material of the support layer <NUM> may be a material that is relatively tough, and is unlikely to collapse or not easy to etch, for example, SiON or SiN, to improve the stability of the first stacked structure.

Step S30: Form, on the substrate, a plurality of BLs arranged at intervals and extending along a second direction, where the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each of the plurality of BLs away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer.

With reference to <FIG>, the plurality of BLs <NUM> are provided, extend along the second direction (the direction X in <FIG>), and are stacked along the first direction (the direction Z in <FIG>) and arranged at intervals, to electrically isolate adjacent BLs <NUM>.

With reference to <FIG>, one end of each of the plurality of BLs <NUM> away from the memory cell array forms a step. Specifically, along the direction away from the substrate <NUM>, the lengths of the plurality of BLs <NUM> are successively reduced, such that one end of each of the plurality of BLs <NUM> away from the memory cell array forms a step. In this way, in every two adjacent BLs <NUM>, a partial region of the BL <NUM> close to the substrate <NUM> is exposed, and is not blocked by the BL <NUM> away from the substrate <NUM>, such that a BL plug <NUM> is subsequently formed in the exposed partial region of the BL <NUM>, thereby electrically connecting the BL <NUM> to the peripheral circuit.

Each BL <NUM> includes a first core layer <NUM> and a first conductive layer <NUM> covering the first core layer <NUM>. As shown in <FIG>, the first conductive layer <NUM> covers a surface of the first core layer <NUM> opposite to the first direction and a side surface of the first core layer <NUM>, that is, the first conductive layer <NUM> covers the exposed surface of the first core layer <NUM>. The material of the first core layer <NUM> may be a semiconductor, such as silicon. The material of the first conductive layer <NUM> may be metal, a metal alloy, or a metal-semiconductor compound, such as titanium, nickel, cobalt, molybdenum, aluminum, metal silicide, and the like. The materials of the first core layer <NUM> and the first conductive layer <NUM> are adjusted, to adjust and adapt their work functions, and realize the ohmic contact between the first core layer <NUM> and the first conductive layer <NUM>, such that the contact resistance is relatively small. In this case, the relatively large contact area between the first core layer <NUM> and the first conductive layer <NUM> can also reduce the contact resistance between the first core layer <NUM> and the first conductive layer <NUM>.

At least one of the plurality of first core layers <NUM> is a N-type semiconductor or a P-type semiconductor. In other words, the N-type or P-type doping is performed on at least one of the first core layers <NUM>. In this way, the work function of the first core layer <NUM> can be adjusted by adjusting the doping concentration of the first core layer <NUM>, such that, on the one hand, the conductive resistance of the first core layer <NUM> can be reduced, and on the other hand, the contact resistance between the first core layer <NUM> and the first conductive layer <NUM> can be reduced.

In some possible implementations, with reference to <FIG>, the step of forming, on the substrate <NUM>, the plurality of BLs <NUM> arranged at intervals and extending along the second direction, where the BL <NUM> is disposed beside the first stacked structure, and is electrically connected to the memory cell array includes the following steps:
Step S31: Form a second stacked structure on the substrate, where the second stacked structure is located beside the first stacked structure; and the second stacked structure includes a sacrificial layer and an active layer that are disposed sequentially and alternately.

With reference to <FIG>, the second stacked structure <NUM> includes a plurality of sacrificial layers <NUM> and a plurality of active layers <NUM>. The plurality of sacrificial layers <NUM> and the plurality of active layers <NUM> are stacked alternately along the first direction. Along the first direction, the active layer <NUM> is disposed between two adjacent sacrificial layers <NUM>, or the sacrificial layer <NUM> is disposed between two adjacent active layers <NUM>, such that the sacrificial layers <NUM> and the active layers <NUM> are disposed sequentially and alternately. In this arrangement, two adjacent active layers <NUM> can be isolated by the sacrificial layer <NUM>, to electrically isolate the active layers <NUM> along the first direction.

As shown in <FIG>, in some possible embodiments, the innermost layer in the second stacked structure <NUM> close to the substrate <NUM> is the sacrificial layer <NUM>. In this way, the active layers <NUM> can all subsequently form the first core layers <NUM>, increasing the quantity of the first core layers <NUM>. The outermost layer in the second stacked structure <NUM> away from the substrate <NUM> is also the sacrificial layer <NUM>. In this way, the sacrificial layer <NUM> can protect the active layer <NUM> from being oxidized.

In some possible implementations, the sacrificial layer <NUM> and the active layer <NUM> may be formed through a deposition process, such as a chemical vapor deposition (CVD), a physical vapor deposition (PVD), an atomic layer deposition (ALD), or the like. In some other possible implementations, the sacrificial layer <NUM> and the active layer <NUM> may further be formed through an epitaxy (EPI) process. The material of the active layer <NUM> includes silicon, and the material of the sacrificial layer <NUM> includes SiGe.

Step S32: Remove a part of the sacrificial layer and a part of the active layer that are away from the first stacked structure, and take the remaining active layer as a step, to form the first core layer.

In some possible embodiments, with reference to <FIG>, a first mask layer <NUM> is formed on the second stacked structure <NUM>. The size of the first mask layer <NUM> is gradually confined to etch the sacrificial layer <NUM> and the active layer <NUM>, such that the active layers <NUM> form steps.

Specifically, with reference to <FIG>, the first mask layer <NUM> is formed on the first stacked structure and the second stacked structure <NUM>. The first mask layer <NUM> formed on the second stacked structure <NUM> is provided with a required pattern, to expose a part of the second stacked structure <NUM>. With reference to <FIG>, the first mask layer <NUM> is used as a mask layer, to etch through the topmost sacrificial layer <NUM> and active layer <NUM> to the penultimate second sacrificial layer <NUM> and active layer <NUM>. In other words, the bottommost sacrificial layer <NUM> and active layer <NUM> are each still of an integral structure, and the bottommost sacrificial layer and the penultimate second sacrificial layer <NUM> each form a first core layer <NUM>. With reference to <FIG>, a part of the first mask layer <NUM> away from the first stacked structure is removed, to confine the first mask layer. With reference to <FIG>, the confined first mask layer <NUM> is used as a mask, to etch through the topmost sacrificial layer <NUM> and active layer <NUM> to the penultimate third sacrificial layer <NUM> and the active layer <NUM>, to make the penultimate third active layer <NUM> form a first core layer <NUM>. With reference to <FIG>, the confining of the first mask layer <NUM> and the etching on the corresponding sacrificial layer <NUM> and active layer <NUM> are repeated, until the topmost active layer <NUM> forms a first core layer <NUM>. At last, the remaining first mask layer <NUM> is removed.

Specifically, in some other possible implementations, the first mask layer <NUM> is formed on the first stacked structure and the second stacked structure <NUM>, and the first mask layer <NUM> formed on the second stacked structure <NUM> has a required pattern, to expose a part of the second stacked structure <NUM>. Alternatively, the first mask layer <NUM> is used as a mask, to etch the topmost sacrificial layer <NUM> and active layer <NUM>. A part of the first mask layer <NUM> away from the first stacked structure is removed, to confine the first mask layer <NUM>. The confined first mask layer <NUM> is used as a mask to etch through the topmost sacrificial layer <NUM> and active layer <NUM> to the second topmost sacrificial layer <NUM> and active layer <NUM>. The processes of confining the first mask layer <NUM> and etching the sacrificial layers <NUM> and the active layers <NUM> are repeated, until the topmost sacrificial layer <NUM> and active layer <NUM> are etched through to the bottommost sacrificial layer <NUM> and active layer <NUM>. In this case, the all active layers <NUM> form the first core layers <NUM>. At last, the remaining first mask layer <NUM> is removed. In the foregoing manufacturing process, the sacrificial layers <NUM> and the active layers <NUM> are etched by a same thickness, which is beneficial to forming the steps.

In some possible embodiments, the step of forming the first mask layer <NUM> on the second stacked structure <NUM> includes: forming a second protective layer <NUM> on the first stacked structure and the second stacked structure <NUM>, and forming the first mask layer <NUM> on the second protective layer <NUM>. The material of the second protective layer <NUM> is relatively tough. When the second stacked structure <NUM> is etched, the pattern on the first mask layer <NUM> is first transferred to the second protective layer <NUM>. The patterned second protective layer <NUM> in the subsequent etching process can ensure the accuracy of transferred pattern. Then, the second stacked structure <NUM> is etched by the patterned second protective layer <NUM>, to improve the consistency between the pattern formed in the second stacked structure <NUM> and the pattern in the first mask layer <NUM>, thereby improving the precision of the semiconductor structure.

Step S33: Remove the remaining sacrificial layer.

With reference to <FIG> and <FIG>, the remaining sacrificial layer <NUM> is removed through a dry-etching or wet-etching process, to make each first core layer <NUM> suspended, such that the exposed surface area of the first core layer <NUM> is increased. It is beneficial to doping the entire first core layer <NUM> subsequently, and reducing the conductive resistance of the first core layer <NUM>, thereby decreasing the resistance of the BL <NUM>.

Step S34: Form the first conductive layer covering the first core layer.

With reference to <FIG>, a first conductive layer <NUM> is formed, through an atomic-layer deposition process, on two opposite surfaces of the first core layer <NUM> along the first direction and on the surface of the first core layer <NUM> away from the first stacked structure. The first conductive layer <NUM> covers the first core layer <NUM>. The material of the first core layer <NUM> may be a semiconductor, such as silicon. The material of the first conductive layer <NUM> may be metal, a metal alloy, or a metal-semiconductor compound, such as titanium, nickel, cobalt, molybdenum, aluminum, metal silicide, and the like. The materials of the first core layer <NUM> and the first conductive layer <NUM> are adjusted, to adjust and adapt their work functions, and realize the ohmic contact between the first core layer <NUM> and the first conductive layer <NUM>, such that the contact resistance is relatively small. In this case, the relatively large contact area between the first core layer <NUM> and the first conductive layer <NUM> can also reduce the contact resistance between the first core layer <NUM> and the first conductive layer <NUM>.

In some possible embodiments, with reference to <FIG>, before the first conductive layer <NUM> covering the first core layer <NUM> is formed, the method further includes: performing N-type or P-type doping on the first core layer <NUM> through a vapor doping process, to reduce a resistance of the first core layer <NUM>.

Specifically, at least one of the plurality of first core layers <NUM> is a N-type semiconductor or a P-type semiconductor. In this way, the work function of the first core layer <NUM> can be adjusted by adjusting the doping concentration of the first core layer <NUM>, such that, on the one hand, the conductive resistance of the first core layer <NUM> can be reduced, and on the other hand, the contact resistance between the first core layer <NUM> and the first conductive layer <NUM> can be reduced. Each first core layer <NUM> is an N-type semiconductor or a P-type semiconductor, such that the contact resistance between each first core layer <NUM> and its corresponding first conductive layer <NUM> is reduced, thereby improving the performance of the semiconductor structure. For example, the N-type semiconductor is formed by doping elements such as phosphorus, arsenic, and antimony into the first core layer <NUM>, and the P-type semiconductor is formed by doping elements such as boron, aluminum, and indium into the first core layer <NUM>. Furthermore, the entire first core layer <NUM> can be doped with phosphorus elements through a vapor doping process, thereby reducing the resistance of the first core layer <NUM>, and a contact resistance between the first core layer <NUM> and the first conductive layer <NUM>.

In some possible implementations, the material of the active layer <NUM> includes silicon. The N-type or P-type doping is performed on the first core layer <NUM> through a vapor doping process, to reduce the resistance of the first core layer <NUM>. In some embodiments, when first core layer <NUM> is doped with phosphorus elements, the method includes: under a vapor condition of phosphorus oxychloride (POCl<NUM>), doping phosphorus atoms into the first core layer <NUM> by a thermal diffusion process, and forming a phospho-silicate glass (PSG) on a surface of the first core layer <NUM>; and removing the PSG through etching, to expose the doped first core layer <NUM>. Because the two opposite surfaces of the first core layer <NUM> along the first direction are exposed, the two surfaces of the first core layer <NUM> can be doped simultaneously through the vapor doping, such that the first core layer <NUM> is completely doped, to improve the doping efficiency and uniformity. The thermal diffusion process is performed at <NUM> to <NUM>. Then, the PSG is formed on the surface of the first core layer <NUM>. In this case, the PSG is removed by hydrofluoric acid.

Step S40: Form a plurality of BL plugs arranged at intervals and extending along the first direction, where each of the BL plugs is in corresponding contact with the first conductive layer of one of the BLs.

With reference to <FIG>, a plurality of BL plugs <NUM> are provided, extend along the first direction, and are arranged at intervals along the third direction, such that the BL plugs <NUM> are isolated from each other, to prevent the BLs <NUM> from interfering with each other. The plurality of BL plugs <NUM> are staggered along the second direction. As shown in <FIG>, a connecting line of the plurality of BL plugs <NUM> and the second direction form an angle. In this way, the distance between adjacent BL plugs <NUM> is relatively large, and the mutual interference is small. Lengths of the plurality of BL plugs <NUM> change in a stepwise manner. In this way, the surfaces of the BL plugs <NUM> away from the substrate <NUM> are flush with each other. It facilitates making the connecting line thereon, to connect the peripheral circuit.

The second conductive part includes a third core layer <NUM> and a second metal layer <NUM> covering the third core layer <NUM>. The second metal layer <NUM> covers the side surface of the third core layer <NUM> and the surface of the third core layer <NUM> facing the substrate <NUM>, such that the second metal layer <NUM> is in contact with the first metal layer <NUM>, thereby electrically connecting the second metal layer <NUM> to the first metal layer <NUM>. The second core layer <NUM> and the third core layer <NUM> may be made of an insulating material. In this way, on the basis of ensuring the electrical properties of the first conductive part and the second conductive part, the thicknesses of the first metal layer <NUM> and the second metal layer <NUM> are reduced, to save the costs.

In some possible embodiments, after the plurality of BL plugs <NUM> arranged at intervals and extending along the first direction are formed, where each of the BL plugs <NUM> is in corresponding contact with the first conductive layer <NUM> of one of the BLs <NUM> (step S40), the method further includes:
forming a first insulating layer <NUM> filling a space between the BLs <NUM>, and forming a first protective layer <NUM> covering the BLs <NUM> and the first insulating layer <NUM>; and forming a second insulating layer <NUM> filling a space between the BL plugs <NUM> and covering the first stacked structure, where a plurality of WL plugs <NUM> are arranged at intervals in the second insulating layer <NUM>, and each of the WL plugs <NUM> is electrically connected to a WL <NUM>.

Specifically, with reference to <FIG>, the first insulating layer <NUM> may further fill a space between adjacent BLs <NUM>, that is, the BL <NUM> and the first insulating layer <NUM> are stacked sequentially and alternately along the first direction. The first insulating layer <NUM> can not only isolate the BLs <NUM>, but also support the BLs <NUM>, to improve the stability of the BL <NUM>. Specifically, the first protective layer <NUM> covers the BL <NUM> and the first insulating layer <NUM>, to prevent the surface of the first conductive layer <NUM> of the BL <NUM> away from the substrate <NUM> from being exposed, and isolate and protect the first conductive layer <NUM>. The first protective layer <NUM> is formed in a stepped shape and may be made of SiN or SiON. The second insulating layer <NUM> fills a space between two adjacent BL plugs <NUM>, and covers the first stacked structure, to further ensure the insulating performance between the BL plugs <NUM>. The second insulating layer <NUM> is made of SiO2. The plurality of WL plugs <NUM> are arranged at intervals in the second insulating layer <NUM>, extend along the first direction, and are electrically connected to the plurality of WLs <NUM> in a one-to-one correspondence, to connect the WL <NUM> to the peripheral circuit.

In conclusion, in the manufacturing method of a semiconductor structure provided by the embodiments of the present disclosure, the BL <NUM> is formed, and includes the first core layer <NUM> and the first conductive layer <NUM> covering the first core layer <NUM>. In addition, the BL plug <NUM> in contact with the first conductive layer <NUM> is formed. The materials of the BL plug <NUM> and the first conductive layer <NUM> are adjusted, to reduce the contact resistance between the BL plug <NUM> and first conductive layer <NUM>, and improve the speed of signal propagation, thereby improving the performance of the semiconductor structure, and reducing the contact resistance between the BL plug <NUM> and the BL <NUM>. The materials of the first conductive layer <NUM> and the first core layer <NUM> are adjusted, to realize ohmic contact between the first conductive layer <NUM> and the first core layer <NUM>, thereby reducing the resistance of the BL <NUM>. In addition, a contact area between the first conductive layer <NUM> and the first core layer <NUM> is relatively large, which is beneficial to reducing the contact resistance between them, thereby reducing the resistance of the BL <NUM>. Vapor doping is subsequently performed on the first core layer <NUM>, thereby doping the entire first core layer <NUM>, and reducing the conductive resistance of the first core layer <NUM>, to further reduce the resistance of the BL <NUM>.

The embodiments or implementations of this specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments. The same or similar parts between the embodiments may refer to each other. In the descriptions of this specification, a description with reference to the term "one implementation", "some implementations", "an exemplary implementation", "an example", "a specific example", "some examples", or the like means that a specific feature, structure, material, or characteristic described in combination with the implementation(s) or example(s) is included in at least one implementation or example of the present disclosure. In this specification, the schematic expression of the above terms does not necessarily refer to the same implementation or example. Moreover, the described specific feature, structure, material or characteristic may be combined in an appropriate manner in any one or more implementations or examples.

Claim 1:
A manufacturing method of a semiconductor structure of 1T1C DRAM, comprising:
forming a first stacked structure on a substrate (<NUM>), wherein the first stacked structure comprises a memory cell array (S10);
forming, on the substrate (<NUM>), a plurality of word lines, WLs, (<NUM>) arranged at intervals and extending along a first direction (Z), wherein the WLs (<NUM>) are disposed in the first stacked structure and are electrically connected to the memory cell array (S20);
forming, on the substrate (<NUM>), a plurality of bit lines, BLs, (<NUM>) arranged at intervals and extending along a second direction (X), wherein the BLs (<NUM>) are disposed beside the first stacked structure, and
are electrically connected to the memory cell array; and one end of each of the plurality of BLs (<NUM>) away from the memory cell array forms a step, and the BLs (<NUM>) comprise a first core layer (<NUM>) and a first conductive layer (<NUM>) covering the first core layer (<NUM>) (S30); and
forming a plurality of BL plugs (<NUM>) arranged at intervals and extending along the first direction (Z), wherein each of the BL plugs (<NUM>) is in corresponding contact with the first conductive layer (<NUM>) of one of the BLs (<NUM>) (S40);
wherein the forming, on the substrate (<NUM>), a plurality of BLs (<NUM>) arranged at intervals and extending along a second direction (X), wherein the BLs (<NUM>) are disposed beside the first stacked structure, and are electrically connected to the memory cell array (S30) comprises:
forming a second stacked structure (<NUM>) on the substrate (<NUM>), wherein the second stacked structure (<NUM>) is located beside the first stacked structure; and the second stacked structure (<NUM>) comprises a sacrificial layer (<NUM>) and an active layer (<NUM>) that are disposed alternately;
removing a part of the sacrificial layer (<NUM>) and a part of the active layer (<NUM>) that are away from the first stacked structure, and taking the remaining active layer (<NUM>) as a step in the first direction (Z), to form the first core layer (<NUM>);
removing the remaining sacrificial layer (<NUM>); and
forming the first conductive layer (<NUM>) covering the first core layer (<NUM>).