Patent Description:
Numerous embodiments are disclosed of output mechanisms for reading or verifying a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.

<CIT> discloses that numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.

<CIT> discloses that configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.

<CIT> discloses adaptive interconnect architectures.

<FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>. The non-volatile memory arrays operate as an analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs.

Each non-volatile memory cells used in the analog neuromorphic memory system must be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

Because the outputs of one VMM often will need to be applied to another VMM, it is desirable in VMM systems to be able to convert an output of a VMM into bits and to apply input bits to another VMM. A challenge then emerges as to how to best implement the bit coding mechanism for the VMM system.

What is needed are improved input and output blocks for a VMM for performing programming, verifying, and reading.

The invention is defined by the features of independent claims.

Digital non-volatile memories are well known. For example, <CIT> ("the '<NUM> patent"), discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal <NUM>, which causes electrons on the floating gate <NUM> to tunnel through the intermediate insulation from the floating gate <NUM> to the word line terminal <NUM> via Fowler-Nordheim (FN) tunneling.

Memory cell <NUM> is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electron current will flow from the drain region <NUM> towards the source region <NUM>. The electrons will accelerate and become heated when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

Table No. <NUM> depicts typical voltage and current ranges that can be applied to the terminals of memory cell <NUM> for performing read, erase, and program operations:.

Other split gate memory cell configurations, which are other types of flash memory cells, are known. For example, <FIG> depicts a four-gate memory cell <NUM> comprising source region <NUM>, drain region <NUM>, floating gate <NUM> over a first portion of channel region <NUM>, a select gate <NUM> (typically coupled to a word line, WL) over a second portion of the channel region <NUM>, a control gate <NUM> over the floating gate <NUM>, and an erase gate <NUM> over the source region <NUM>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate. The erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line during a program operation to compensate for a lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except that floating gate <NUM> extends over the entire channel region <NUM>, and control gate <NUM> (which here will be coupled to a word line) extends over floating gate <NUM>, separated by an insulating layer (not shown). The erase is done by FN tunneling of electrons from FG to substrate, programming is by channel hot electron (CHE) injection at region between the channel <NUM> and the drain region <NUM>, by the electrons flowing from the source region <NUM> towards to drain region <NUM> and read operation which is similar to that for memory cell <NUM> with a higher control gate voltage.

The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation.

S0 is the input layer, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the feature maps of layer C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of layer C1, until all the features maps of layer C1 have been calculated.

The purpose of the pooling function P1 is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage. The synapses CB2 going from layer S1 to layer C2 scan maps in layer S1 with 4x4 filters, with a filter shift of <NUM> pixel.

<FIG> is a block diagram of an array that can be used for that purpose. Vector-by-matrix multiplication (VMM) array <NUM> includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in <FIG>) between one layer and the next layer. Specifically, VMM array <NUM> includes an array of non-volatile memory cells <NUM>, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the respective inputs for the non-volatile memory cell array <NUM>. Input to VMM array <NUM> can be from the erase gate and wordline gate decoder <NUM> or from the control gate decoder <NUM>. Source line decoder <NUM> in this example also decodes the output of the non-volatile memory cell array <NUM>. Alternatively, bit line decoder <NUM> can decode the output of the non-volatile memory cell array <NUM>.

Non-volatile memory cell array <NUM> serves two purposes. Second, the non-volatile memory cell array <NUM> effectively multiplies the inputs by the weights stored in the non-volatile memory cell array <NUM> and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, the non-volatile memory cell array <NUM> negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of non-volatile memory cell array <NUM> is supplied to a differential summer (such as a summing op-amp or a summing current mirror) <NUM>, which sums up the outputs of the non-volatile memory cell array <NUM> to create a single value for that convolution. The differential summer <NUM> is arranged to perform summation of positive weight and negative weight.

The summed-up output values of differential summer <NUM> are then supplied to an activation function circuit <NUM>, which rectifies the output. The activation function circuit <NUM> may provide sigmoid, tanh, or ReLU functions. The rectified output values of activation function circuit <NUM> become an element of a feature map as the next layer (e.g. C1 in <FIG>), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, non-volatile memory cell array <NUM> constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summing op-amp <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

The input to VMM array <NUM> in <FIG> (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

<FIG> is a block diagram depicting the usage of numerous layers of VMM arrays <NUM>, here labeled as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in <FIG>, the input, denoted Inputx, is converted from digital to analog by a digital-to-analog converter <NUM> and provided to input VMM array 32a. The input D/A conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs Inputx to appropriate analog levels for the matrix multiplier of input VMM array 32a. The input conversion could also be done by an analog to analog (A/A) converter to convert an external analog input to a mapped analog input to the input VMM array 32a.

The output generated by input VMM array 32a is provided as an input to the next VMM array (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM array (hidden level <NUM>) 32c, and so on. The various layers of VMM array <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical non-volatile memory array, or multiple VMM arrays could utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays could utilize overlapping portions of the same physical non-volatile memory array. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG> and is utilized as the synapses and parts of neurons between an input layer and the next layer.

As described herein for neural networks, the non-volatile memory cells of VMM array <NUM>, i.e. the memory cells <NUM> of VMM array <NUM>, are preferably configured to operate in a sub-threshold region.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion (sub threshold region): <MAT> where <MAT> where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor = <NUM> + (Cdep/Cox) with Cdep = capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox* (n-<NUM>) * Vt<NUM> where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current into an input voltage: <MAT> where, wp is w of a reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier VMM array with the current input, the output current is: <MAT> namely <MAT> <MAT>.

Where Vth0 is threshold voltage with zero substrate bias, φF is a surface potential, and gamma is a body effect parameter.

Alternatively, the flash memory cells of VMM arrays described herein can be configured to operate in the linear region: <MAT> <MAT> meaning weight W in the linear region is proportional to (Vgs-Vth).

For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in the linear region can be used to linearly convert an input/output current into an input/output voltage.

Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region: <MAT> Wα (Vgs-Vth)<NUM>, meaning weight W is proportional to (Vgs-Vth)<NUM>.

Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.

Other embodiments for VMM array <NUM> of <FIG> are described in <CIT>. As described in that application. a sourceline or a bitline can be used as the neuron output (current summation output).

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG> and is utilized as the synapses between an input layer and the next layer.

Table No. <NUM> depicts operating voltages and currents for VMM array <NUM>.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG> and is utilized as the synapses and parts of neurons between an input layer and the next layer.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG> and is utilized as the synapses and parts of neurons between an input layer and the next layer.

VMM array <NUM> implements uni-directional tuning for non-volatile memory cells in memory array <NUM>. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell is erased and the sequence of partial programming operations starts over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

Table No. <NUM> depicts operating voltages and currents for VMM array <NUM>.

<FIG> depicts VMM array <NUM>. VMM array <NUM> implements uni-directional or bi-directional tuning for a page of non-volatile memory cells. Here, exemplary page <NUM> comprises two words, each in a different row. A word includes a plurality of memory cells, e.g. <NUM>-<NUM>. A special word may include just one cell or a few cells. Pairs of adjacent rows share a source line, such as SL0 or SL1. All cells in page <NUM> share a common erase gate line that is controlled by erase gate enable transistor <NUM>, which controls the provision of a voltage to the erase gate terminals EGW of all cells in exemplary page set <NUM>. Here, all cells in page <NUM> can be erased at the same time. Thereafter, cells in page <NUM> can be uni-directionally or bi-directionally tuned through program (cellwise, meaning each cell in a word can be tuned at a time; wordwise, meaning all cells in a word can be tuned at the same times) and erase (wordwise, meaning all cells in a word can be tuned at same time) operations and some cells in page <NUM> can be uni-directionally tuned through program operation. The program operations can include the precision programming techniques described below with reference to <FIG>. If too much electron charge is placed on a floating gate (which would cause an incorrect current value to be stored in the cell, i.e. a current value lower than the intended current value), the cell must be erased and the sequence of partial programming operations must start over.

<FIG> depicts VMM array <NUM>. VMM array <NUM> implements uni-directional or bi-directional tuning for a word of non-volatile memory cells. Here, exemplary word <NUM> comprises a plurality of cells in a row. All cells in word <NUM> share a common erase gate line that is controlled by erase gate enable transistor <NUM>, which controls the provision of a voltage to the erase gate terminals of all cells in word <NUM>. Here, all cells in word <NUM> can be erased at the same time. Thereafter, cells in word <NUM> can be uni-directionally or bi-directionally tuned through program (cellwise, meaning each cell in a word can be tuned at a time; wordwise, meaning all cells in a word can be tuned at the same times) and erase (wordwise, meaning all cells in a word can be tuned at same time)operations. The program operations can include the precision programming techniques described below. If too much electron charge is placed on a floating gate (such that an incorrect current value is stored in the cell, i.e. a current value lower than the intended current value), the cell must be erased and the sequence of partial programming operations must start over.

<FIG> depicts VMM array <NUM>. VMM array <NUM> implements uni-directional or bi-directional tuning for a word of non-volatile memory cells. Here, exemplary word <NUM> comprises two half words of cells. Each half word belongs to a row that shares an erase gate. All cells in word <NUM> share a common erase gate line connected to erase gate terminal EGW. Unlike in VMM array <NUM> and <NUM>, there is no erase gate enable transistor. Here, all cells in word <NUM> can be erased at the same time. Thereafter, cells in word <NUM> can be uni-directionally or bi-directionally tuned through program (cellwise, meaning each cell in a word can be tuned at a time; wordwise, meaning all cells in a word can be tuned at the same times) and erase (wordwise, meaning all cells in a word can be tuned at same time) operations. The program operations can include the precision programming techniques described below. If too much electron charge is placed on a floating gate (such that an incorrect current value is stored in the cell, i.e. a current value lower than the intended current value), the cell must be erased and the sequence of partial programming operations must start over.

The prior art includes a concept known as long short-term memory (LSTM). LSTM units often are used in neural networks. LSTM allows a neural network to remember information over predetermined arbitrary time intervals and to use that information in subsequent operations. A conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval that the information is remembered in the LSTM. VMMs are particularly useful in LSTM units.

<FIG> depicts an exemplary LSTM <NUM>. LSTM <NUM> in this example comprises cells <NUM>, <NUM>, <NUM>, and <NUM>. Cell <NUM> receives input vector x<NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM> from cell <NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM>. Additional cells can be used, and an LSTM with four cells is merely an example.

<FIG> depicts an exemplary implementation of an LSTM cell <NUM>, which can be used for cells <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>. LSTM cell <NUM> receives input vector x(t), cell state vector c(t-<NUM>) from a preceding cell, and output vector h(t-<NUM>) from a preceding cell, and generates cell state vector c(t) and output vector h(t).

LSTM cell <NUM> comprises sigmoid function devices <NUM>, <NUM>, and <NUM>, each of which applies a number between <NUM> and <NUM> to control how much of each component in the input vector is allowed through to the output vector. LSTM cell <NUM> also comprises tanh devices <NUM> and <NUM> to apply a hyperbolic tangent function to an input vector, multiplier devices <NUM>, <NUM>, and <NUM> to multiply two vectors together, and addition device <NUM> to add two vectors together. Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

<FIG> depicts an LSTM cell <NUM>, which is an example of an implementation of LSTM cell <NUM>. For the reader's convenience, the same numbering from LSTM cell <NUM> is used in LSTM cell <NUM>. Sigmoid function devices <NUM>, <NUM>, and <NUM> and tanh device <NUM> each comprise multiple VMM arrays <NUM> and activation circuit blocks <NUM>. Thus, it can be seen that VMM arrays are particular useful in LSTM cells used in certain neural network systems.

An alternative to LSTM cell <NUM> (and another example of an implementation of LSTM cell <NUM>) is shown in <FIG>. In <FIG>, sigmoid function devices <NUM>, <NUM>, and <NUM> and tanh device <NUM> share the same physical hardware (VMM arrays <NUM> and activation function block <NUM>) in a time-multiplexed fashion. LSTM cell <NUM> also comprises multiplier device <NUM> to multiply two vectors together, addition device <NUM> to add two vectors together, tanh device <NUM> (which comprises activation circuit block <NUM>), register <NUM> to store the value i(t) when i(t) is output from sigmoid function block <NUM>, register <NUM> to store the value f(t) * c(t-<NUM>) when that value is output from multiplier device <NUM> through multiplexor <NUM>, register <NUM> to store the value i(t) * u(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and register <NUM> to store the value o(t) * c~(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and multiplexor <NUM>.

Whereas LSTM cell <NUM> contains multiple sets of VMM arrays <NUM> and respective activation function blocks <NUM>, LSTM cell <NUM> contains only one set of VMM arrays <NUM> and activation function block <NUM>, which are used to represent multiple layers in the embodiment of LSTM cell <NUM>. LSTM cell <NUM> will require less space than LSTM <NUM>, as LSTM cell <NUM> will require <NUM>/<NUM> as much space for VMMs and activation function blocks compared to LSTM cell <NUM>.

It can be further appreciated that LSTM units will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The embodiments described below therefore attempt to minimize the circuitry required outside of the VMM arrays themselves.

An analog VMM implementation can be utilized for a GRU (gated recurrent unit) system. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than an LSTM cell.

<FIG> depicts an exemplary GRU <NUM>. GRU <NUM> in this example comprises cells <NUM>, <NUM>, <NUM>, and <NUM>. Cell <NUM> receives input vector x<NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector h<NUM> from cell <NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM> and the output vector (hidden state) h<NUM> from cell <NUM> and generates output vector h<NUM>. Cell <NUM> receives input vector x<NUM> and the output vector (hidden state) h<NUM> from cell <NUM> and generates output vector h<NUM>. Additional cells can be used, and an GRU with four cells is merely an example.

<FIG> depicts an exemplary implementation of a GRU cell <NUM>, which can be used for cells <NUM>, <NUM>, <NUM>, and <NUM> of <FIG>. GRU cell <NUM> receives input vector x(t) and output vector h(t-<NUM>) from a preceding GRU cell and generates output vector h(t). GRU cell <NUM> comprises sigmoid function devices <NUM> and <NUM>, each of which applies a number between <NUM> and <NUM> to components from output vector h(t-<NUM>) and input vector x(t). GRU cell <NUM> also comprises a tanh device <NUM> to apply a hyperbolic tangent function to an input vector, a plurality of multiplier devices <NUM>, <NUM>, and <NUM> to multiply two vectors together, an addition device <NUM> to add two vectors together, and a complementary device <NUM> to subtract an input from <NUM> to generate an output.

<FIG> depicts a GRU cell <NUM>, which is an example of an implementation of GRU cell <NUM>. For the reader's convenience, the same numbering from GRU cell <NUM> is used in GRU cell <NUM>. As can be seen in <FIG>, sigmoid function devices <NUM> and <NUM>, and tanh device <NUM> each comprise multiple VMM arrays <NUM> and activation function blocks <NUM>. Thus, it can be seen that VMM arrays are of particular use in GRU cells used in certain neural network systems.

An alternative to GRU cell <NUM> (and another example of an implementation of GRU cell <NUM>) is shown in <FIG>. In <FIG>, GRU cell <NUM> utilizes VMM arrays <NUM> and activation function block <NUM>, which when configured as a sigmoid function applies a number between <NUM> and <NUM> to control how much of each component in the input vector is allowed through to the output vector. In <FIG>, sigmoid function devices <NUM> and <NUM> and tanh device <NUM> share the same physical hardware (VMM arrays <NUM> and activation function block <NUM>) in a time-multiplexed fashion. GRU cell <NUM> also comprises multiplier device <NUM> to multiply two vectors together, addition device <NUM> to add two vectors together, complementary device <NUM> to subtract an input from <NUM> to generate an output, multiplexor <NUM>, register <NUM> to hold the value h(t-<NUM>) * r(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, register <NUM> to hold the value h(t-<NUM>) *z(t) when that value is output from multiplier device <NUM> through multiplexor <NUM>, and register <NUM> to hold the value h^(t) * (<NUM>-z(t)) when that value is output from multiplier device <NUM> through multiplexor <NUM>.

Whereas GRU cell <NUM> contains multiple sets of VMM arrays <NUM> and activation function blocks <NUM>, GRU cell <NUM> contains only one set of VMM arrays <NUM> and activation function block <NUM>, which are used to represent multiple layers in the embodiment of GRU cell <NUM>. GRU cell <NUM> will require less space than GRU cell <NUM>, as GRU cell <NUM> will require <NUM>/<NUM> as much space for VMMs and activation function blocks compared to GRU cell <NUM>.

It can be further appreciated that GRU systems will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The embodiments described below therefore attempt to minimize the circuitry required outside of the VMM arrays themselves.

The input to the VMM arrays can be an analog level, a binary level, a pulse, a time modulated pulse, or digital bits (in this case a DAC is needed to convert digital bits to appropriate input analog level) and the output can be an analog level, a binary level, a timing pulse, pulses, or digital bits (in this case an output ADC is needed to convert output analog level into digital bits).

For each memory cell in a VMM array, each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of <NUM> cells). In the differential cell case, two memory cells are needed to implement a weight W as a differential weight (W = W+ - W-). In the two blend memory cells, two memory cells are needed to implement a weight W as an average of two cells.

<FIG> depicts a block diagram of VMM system <NUM>. VMM system <NUM> comprises VMM array <NUM>, row decoders <NUM>, high voltage decoders <NUM>, column decoders <NUM>, bit line drivers <NUM>, input circuit <NUM>, output circuit <NUM>, control logic <NUM>, and bias generator <NUM>. VMM system <NUM> further comprises high voltage generation block <NUM>, which comprises charge pump <NUM>, charge pump regulator <NUM>, and high voltage level generator <NUM>. VMM system <NUM> further comprises (program/erase, or aka weight tuning) algorithm controller <NUM>, analog circuitry <NUM>, control engine <NUM> (that may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, etc.), and test control logic <NUM>. The systems and methods described below can be implemented in VMM system <NUM>.

The input circuit <NUM> may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter ), PAC (pulse to analog level converter), or any other type of converters. The input circuit <NUM> may implement normalization, linear or non-linear up/down scaling functions, or arithmetic functions. The input circuit <NUM> may implement a temperature compensation function for input levels. The input circuit <NUM> may implement an activation function such as ReLU or sigmoid. The output circuit <NUM> may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters. The output circuit <NUM> may implement an activation function such as ReLU or sigmoids. The output circuit <NUM> may implement statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit <NUM> may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.

<FIG> depicts programming method <NUM>. First, the method starts (step <NUM>), which typically occurs in response to a program command being received. Next, a mass program operation programs all cells to a '<NUM>' state (step <NUM>). Then a soft erase operation erases all cells to an intermediate level (achieved by weak erasing, i.e., a less than complete erasing) such that each cell draws current of approximately <NUM>-<NUM>µA during a read operation (step <NUM>). This is in contrast to a deeply erased level where each cell draws current of approximately ~ <NUM>-<NUM>µA during a read operation. Then, a hard program is performed on all unselected cells or zero weight cells (i.e. cells with weight = <NUM> or insignificant weight, i.e. weight within an insignificant threshold value) to a very deep programmed state to add electrons to the floating gates of the cells and to remove all positive charge (step <NUM>) to ensure that those cells are really "off," meaning that those cells will draw a negligible amount of current during a read operation.

A coarse programming method is then performed on selected cells (step <NUM>), followed by a precision programming method on the selected cells (step <NUM>) to program the precise value desired for each selected cell. Here, a selected cell is a cell that is identified as the subject of programming method <NUM> and is selected by asserting the appropriate word line and bit line or by some other mechanism.

<FIG> depicts another programming method <NUM>, which is similar to programming method <NUM>. However, instead of a program operation to program all cells to a '<NUM>' state as in step <NUM> of <FIG>, after the method start (step <NUM>), an erase operation is used to erase all cells to a '<NUM>' state (step <NUM>). Then a soft program operation (step <NUM>) is used to program all cells to an intermediate level (achieved by soft programming, i.e., a less than complete programming) such that each cell would draw current of approximately <NUM>-5uA during a read operation. Afterward, hard programming of unselected cells (step <NUM>) and coarse and precision programming method follow (steps <NUM> - <NUM>) as described above in relation to <FIG>. A variation of the embodiment of <FIG> removes the soft programing method (step <NUM>) altogether.

<FIG> depicts a first embodiment of coarse programming method <NUM>, which is search and execute method <NUM>. First, a lookup table search, or a predetermined function is performed, to determine a coarse target current value (ICT) for each of the selected cells based on the value that is intended to be stored in that selected cell (step <NUM>). The selected cell can be programmed to store one of N possible values (e.g., <NUM>, <NUM>, <NUM>, without limitation). Each of the N values corresponds to a different desired current value (ID) that is to be drawn by the selected cell during a read operation. In one embodiment, a look-up table or function (for example a function derived from curve fitting to data or based on the physics of memory behavior, where the function operates on variables such as the final target value and the existing value and calculates the expected or desired target for next operation) contains M possible current values to use as the coarse target current value ICT for the selected cell during search and execute method <NUM>, where M is an integer less than N. For example, if N is <NUM>, then M might be <NUM>, meaning that there are <NUM> possible values that the selected cell can store, and one of <NUM> coarse target current values ICT will be selected as the coarse target current value ICT for search and execute method <NUM>. That is, search and execute method <NUM> is arranged to quickly program the selected cell to the coarse target current value (ICT) that is somewhat close to the desired current value ID, and then the precision programming method <NUM> is more precisely programs the selected cell to be extremely close to the desired current value ID.

Examples of cell values, desired current values, and coarse target current values are depicted in Tables <NUM> and <NUM> for the simple example of N=<NUM> and M=<NUM>:.

The offset values ICTOFFSETx are used to prevent overshooting the desired current value during coarse programming.

Once the coarse target current value ICT is selected, the selected cell is programmed by applying a voltage v<NUM> to the appropriate terminal of selected cell based on the cell architecture type of the selected cell (e.g., memory cells <NUM>, <NUM>, <NUM>, or <NUM>) (step <NUM>). If the selected cell is of type memory cell <NUM> in <FIG>, then the voltage v<NUM> is applied to control gate terminal <NUM>, and v<NUM> might be <NUM>-7V depending on coarse target current value ICT. The value of v<NUM> optionally can be determined from a voltage look up table that stores v<NUM> vs. coarse target current value ICT.

Next, the selected cell is programmed by applying the voltage vi = vi-<NUM>+vincrement, where i starts at <NUM> and increments each time this step is repeated (step <NUM>), and where vincrement is a small voltage that causes a degree of programming that is appropriate for the granularity of change desired. Thus, the first time step <NUM> is performed, i=<NUM>, and v<NUM> will be v<NUM> + vincrement. Then a verify operation is performed (step <NUM>), wherein a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is measured. If Icell is less than or equal to ICT (a first threshold value), then search and execute method <NUM> is complete and precision programming method <NUM> can begin. If Icell is not less than or equal to ICT, then step <NUM> is repeated, and i is incremented.

Thus, at the point when coarse programming method <NUM> ends and precision programming method <NUM> begins, the voltage vi will be the last voltage used to program the selected cell, and the selected cell stores a value associated with the coarse target current value ICT. Precision programming method <NUM> programs the selected cell to the point where during a read operation it draws desired current value ID (plus or minus an acceptable amount of deviation, such as <NUM> pA or less), which is the desired current value ID that is associated with the value that is intended to be stored in the selected cell.

<FIG> depicts examples of different voltage progressions that can be applied to the control gate of a selected memory cell during precision program method <NUM>.

In a first embodiment, increasing voltages are progressively applied to the control gate to further program the selected memory cell. The starting point is vi, which is the last voltage applied during coarse programming method <NUM>. An increment of vp1 is added to v<NUM> and the voltage v<NUM> + vp1 is then used to program the selected cell (indicated by the second pulse from the left in progression <NUM>). vp1 is an increment that is smaller than vincrement (the voltage increment used during coarse programming method <NUM>). After each programming voltage is applied, a verify step (similar to step <NUM>) is performed, where a determination is made if Icell is less than or equal to IPT1 (which is the first precision target current value and here is a second threshold value), where IPT1 = ID + IPT1OFFSET, where IPT1OFFSET is an offset valued added to prevent program overshoot. If it is not less than or equal to IPT1, then another increment vp1 is added to the previously-applied programming voltage, and the process is repeated. At the point where Icell is less than or equal to IPT1, then this portion of the programming sequence stops. Optionally, if IPT1 is equal to ID, or almost equal to ID with sufficient precision (meaning an acceptable amount of deviation), then the selected memory cell has been successfully programmed.

If IPT1 is not equal to ID, or almost equal to ID with sufficient precision, then further programming of a smaller granularity occurs. Here, progression <NUM> is now used. The starting point for progression <NUM> is the last voltage used for programming under progression <NUM>. An increment of Vp2 (which is smaller than vp1) is added to that programming voltage, and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, a verify step (similar to step <NUM>) is performed, where a determination is made if Icell is less than or equal to IPT2 (which is the second precision target current value and here is a third threshold value), where IPT2 = ID + IPT2OFFSET, and where IPT2OFFSET is an offset value added to prevent program overshoot. If Icell is not less than or equal to IPT2 , then another increment Vp2 is added to the previously-applied programming voltage, and the process is repeated. At the point where Icell is less than or equal to IPT2, then this portion of the programming sequence stops. Here, it is assumed that IPT2 is equal to ID or close enough to ID that the programming can stop, since the target value has been achieved with sufficient precision. One of ordinary skill in the art can appreciate that additional progressions can be applied with smaller and smaller programming increments used if IPT2 is not equal to ID or close enough to ID that the programming can stop. For example, in <FIG>, three progressions (<NUM>, <NUM>, and <NUM>) are applied instead of just two.

A second embodiment is shown in progression <NUM>. Here, instead of increasing the programming voltage applied during the programming of the selected memory cell, the same programming voltage is applied for durations of increasing period. Instead of adding an incremental voltage such as vp1 in progression <NUM> and vp2 in progression <NUM>, an additional increment of time tp1 is added to the programming pulse such that each applied pulse is longer than the previously-applied pulse by tp1. In the example shown, the first pulse has a duration tp0, and the second pulse has a duration tp0 + tp1. After each programming pulse is applied, the same verify step is performed as described previously for progression <NUM>. Optionally, additional progressions can be applied where the additional increment of time added to the programming pulse is of a smaller duration than the previous progression used. Although only one temporal progression is shown, one of ordinary skill in the art will appreciate that any number of different temporal progressions can be applied.

Additional detail will now be provided for two additional embodiments of coarse programming method <NUM>.

<FIG> depicts a second embodiment of coarse programming method <NUM> (shown in <FIG> and <FIG>), which is adaptive calibration method <NUM>. The method starts (step <NUM>). The selected cell is programmed at a default start programming voltage value v<NUM> (step <NUM>). Unlike in search and execute method <NUM>, here programming voltage value v<NUM> is not derived from a lookup table, or from a function, and instead is a relatively small initial value. The control gate voltage (Vcg) of the cell is measured at a first current value IR1 (e.g., 100na) and at a second current value IR2 (e.g., 10na), and a slope is determined based on those measurements (e.g., 360mV/decade of current) and stored (step <NUM>).

A new programming voltage, vi, is determined. The first time this step is performed, i=<NUM>, and v<NUM> is determined based on the stored slope and a current target value, such as coarse target current value ICT, and an offset value using a sub-threshold equation, such as the following: <MAT> vincrement is proportional to slope of Vcg vs. log [Ids/wa*Io] with <MAT> Here, Vcg is the control gate voltage, wa is w of a memory cell, Ids is the current target plus offset value.

If the stored slope value is relatively steep, then a relatively small current offset value can be used. If the stored slope value is relatively flat, then a relatively high current offset value can be used. Thus, determining the slope information allows for a current offset value to be selected that is customized for the particular cell in question. This ultimately makes the programming process shorter. When this step is repeated, i is incremented, and vi = vi-<NUM> + vincrement. The cell is then programmed using vi. vincrement can be determined from a lookup table storing values of vincrement. vs. current target value, such as coarse target current value ICT.

Next, a verify operation occurs, wherein a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is compared with coarse target current value ICT (step <NUM>). If Icell is less than or equal to coarse target current value ICT, where ICT is set = ID + ICTOFFSET, where ICTOFFSET is an offset value added to prevent program overshoot, then adaptive calibration method <NUM> is complete and precision programming method <NUM> can begin. If Icell is not less than or equal to ICT, then steps <NUM>-<NUM> are repeated, and i is incremented.

<FIG> depicts a second embodiment of coarse programming method <NUM>, which is adaptive calibration method <NUM>. The method starts (step <NUM>). The cell is programmed at a default start value v<NUM> (step <NUM>). v<NUM> is derived from a lookup table created from silicon characterization, where the table value further provides an offset value ICTOFFSET so as not to overshoot the programmed target.

In step <NUM> an I-V slope parameter is created which is used in determining the next programming voltage. A first control gate read voltage, VCGR1, is applied to the selected cell, and the resulting cell current, IR<NUM>, is measured. Then a second control gate read voltage, VCGR2, is applied to the selected cell, and the resulting cell current, IR<NUM>, is measured. A slope is determined based on those measurements and stored, for example as according to the equation in sub threshold region (cell operating in sub threshold): <MAT> (step <NUM>). Examples of values for VCGR1 and VCGR2 are <NUM>. 5V and <NUM>. 3V, respectively.

Determining the slope allows for a vincrement value to be selected that is customized for each of the selected cells. This makes the programming process shorter.

When step <NUM> is performed, i is incremented, and a new programming voltage, vi, is determined based on the stored slope value and the coarse target current value ICT and an offset value using an equation such as the following: <MAT> where <MAT> where alpha is a pre-determined constant < <NUM> (programming offset value) to prevent overshoot, e.g., <NUM>.

The cell is then programmed using programming voltage vi (step <NUM>). Here, vi can be applied to the source line terminal, control gate terminal, or erase gate terminal of the selected cell, depending on the programming scheme used.

Next, a verify operation occurs, wherein a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is compared with the coarse target current value ICT (step <NUM>). If Icell is less than or equal to coarse target current value ICT , where coarse target threshold value ICT is set = ID + ICTOFFSET, where ICTOFFSET is an offset value added to prevent program overshoot, then the process proceeds to the step <NUM>. If not, then the process returns to step <NUM> and i is incremented.

In step <NUM>, Icell is compared against a threshold value, ICT2, that is smaller than coarse target current value ICT, in order to determine if an overshoot has occurred. That is, although the steps <NUM> - <NUM> ensure that Icell is below coarse target current value ICT, Icell may be too far below coarse target current value ICT, i.e. an overshoot has occurred and Icell may represent a stored value that corresponds to the wrong value. If Icell is not less than or equal to ICT2, then no overshoot has occurred, and adaptive calibration method <NUM> has completed, as which point the process progresses to precision programming method <NUM> with starting value vi and cell programmed to, or near to, coarse target threshold value ICT. If Icell is less than or equal to ICT2, then an overshoot has occurred and the selected cells are then erased (step <NUM>), and the programming process starts over at step <NUM>, this time with a smaller Vincrement to avoid overshooting again. Optionally, if step <NUM> is performed more than a predetermined number of times, the selected cell can be deemed a bad cell that should not be used.

The precision program method <NUM> consists of multiple verify and program cycles, in which the program voltage is incremented by a constant fine voltage with a fixed pulse width or in which the program voltage is fixed and the program pulse width is varied or constant for next pulses, as described above in relation to <FIG>.

Optionally, the step (<NUM>) of determining if the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the coarse target current value, ICT, can be performed by applying a fixed bias to a terminal of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate digital output bits, and comparing the digital output bits to digital bits representing the first threshold current value, ICT.

Optionally, the step of determining if the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the coarse target current value, ICT, can be performed by applying an input to a terminal of the non-volatile memory cell, modulating the current drawn by the non-volatile memory cell with an input pulse to generate a modulated output, digitizing the modulated output to generate digital output bits, and comparing the digital output bits to digital bits representing the first threshold current, ICT. <FIG> depicts an example circuit implementation for performing a portion of adaptive calibration method <NUM>. During step <NUM>, current source <NUM> is used to apply the exemplary current values IR1 and IR2 to the selected cell (here, memory cell <NUM>), and the voltage (CGR1 for IR1 and CGR2 for IR2) at the control gate of memory cell <NUM> is then measured. As indicate above, the slope is (VCGR1 - VCGR2) / (LOG(IR<NUM>) - LOG(IR<NUM>)).

<FIG> depicts another embodiment of coarse programming method <NUM>, which is absolute calibration method <NUM>. The method starts (step <NUM>). The cell is programmed at a default starting value v<NUM> (step <NUM>). The control gate voltage of the cell (VCGRx) is measured at a current value Itarget (i.e. the final desired value of cell current) and stored (step <NUM>). A programming voltage, v<NUM>, is determined based on the stored control gate voltage and the current value Itarget plus an offset value, Ioffset+Itarget (step <NUM>). For example, the new programming voltage, v<NUM>, can be calculated as follows: v<NUM>= v<NUM> + (VCGBIAS - stored VCGR), where VCGBIAS is the default read control gate voltage at a maximum target current (which in one embodiment is ~ <NUM>. 5V) and stored VCGR is the measured read control gate voltage of step <NUM>.

The cell is then programmed using programming voltage vi. When i=<NUM>, the voltage v<NUM> from step <NUM> is used. When i>=<NUM>, the voltage vi = vi-<NUM> + Vincrement is used. vincrement can be determined from a lookup table storing values of vincrement. vs. current value Itarget. Next, a verify operation occurs, wherein a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is compared with coarse target current value ICT (step <NUM>). If Icell is less than or equal to coarse target current value ICT, then absolute calibration method <NUM> is complete and precision programming method <NUM> can begin. If Icell is not less than or equal to coarse target current value ICT, then steps <NUM>-<NUM> are repeated, and i is incremented.

<FIG> depicts circuit <NUM> for implementing step <NUM> of absolute calibration method <NUM>. A voltage source (not shown) generates VCGR, which begins at an initial voltage and ramps upward. Here, n+<NUM> different current sources <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n) generate different currents IO0, IO1, IO2,. IOn of increasing magnitude. Each current source <NUM> is connected to a respective inverter <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n) and memory cell <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. As VCGR ramps upward, each memory cell <NUM> draws increasing amounts of current, and the input voltage to each inverter <NUM> decreases. Because IO0 < IO1 < IO2 <. < IOn, the output of inverter <NUM>-<NUM> will switch from low to high first as VCGR increases. The output of inverter <NUM>-<NUM> will switch from low to high next, then the output of inverter <NUM>-<NUM>, and so on, until the output of inverter <NUM>-n switches from low to high. Each inverter <NUM> controls a respective switch <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n), such that when the output of inverter <NUM> is low, switch <NUM> is closed, and when the output of inverter <NUM> is high, switch <NUM> is open. When inverter <NUM> switches from low to high, VCGR, which was sampled when switch <NUM> is low, is held by the respective capacitor <NUM> (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>,. , <NUM>-n). Thus, each respective switch <NUM> and capacitor <NUM> form a sample-and-hold circuit. The values of IO0, IO1, IO2,. , IOn are used as possible values of Itarget and the respective sampled voltage is used as the associated value VCGRx in absolute calibration method <NUM> of <FIG>. Graph <NUM> shows VCGR ramping upward over time, and the outputs of inverters <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-n switching from low to high at various times.

<FIG> depicts example progression <NUM> for programming a selected cell during adaptive calibration method <NUM> or absolute calibration method <NUM>. In one embodiment, the voltage vcgp is applied to the control gates of a selected row of memory cells. The number of selected memory cells in the selected row is for example = <NUM> cells. Hence, up to <NUM> memory cells in a selected row can be programmed in parallel. Each memory cell is enabled to couple to a programming current Iprog by a bitline enable signal. If the bitline enable signal is inactive (meaning a positive voltage being applied to selected bitline), the memory cell is inhibited (not being programmed). As shown in <FIG>, bitline enabling signal En_blx (where x varies between <NUM> and n, where n is the number of bit lines) is enabled at different time with a vcgp voltage level desired for that bitline (hence for selected memory on said bitline). In another embodiment, the voltage applied to the control gate of the selected cell can be controlled using enable signals on the bitline. Each bitline enable signal causes a desired voltage (such as vi described in <FIG>) corresponding to that bitline to be applied as vcgp. The bitline enable signal may also control the programming current flowing into the bitline. In this example, each subsequent control gate voltage vcgp is higher than the previous voltage. Alternatively, each subsequent control gate voltage can be lower or higher than the previous voltage. Each subsequent increment in vcgp can either be equal or not equal to the previous increment.

<FIG> depicts example progression <NUM> for programming a selected cell during adaptive calibration method <NUM> or absolute calibration method <NUM>. In one embodiment, a bitline enable signal (e.g. EN_bin, EN_bl1, EN_bl5)_enables the selected bitline (that is, the bitline that is coupled to the selected memory cell) to be programmed with corresponding Vcgp voltage level. In another embodiment, the voltage applied to the increment ramping control gate of the selected cell can be controlled using bitline enable signals. Each bitline enable signal causes a desired voltage (such as vi described in <FIG>) corresponding to that bitline to be applied to the control gate voltage. In this example, each subsequent increment is equal to the previous increment.

<FIG> depicts a system for implementing the input and output method for reading or verifying with a VMM array. The input function circuit <NUM> receives digital bit values and converts those digital values into an analog signal that is then used to apply a voltage to the control gate of a selected cell in array <NUM> that is selected by control gate decoder <NUM>, word line decoder <NUM>, and a bit line (not shown) In the embodiments described below, an input is applied to the selected memory cell, which then generates an output current that represents a multiplication operation of the received input and the stored weight, W, in the selected cell. Output neuron circuit block <NUM> performs an output action for each column (neuron) of cells in VMM array <NUM>. The output circuit block <NUM> can be implemented using an integrating analog-to-digital converter (ADC), a successive approximation (SAR) ADC, or a Sigma-Delta ADC.

In one embodiment, the digital values provided to input function circuit <NUM> comprise four bits (DIN3, DIN2, DIN1, and DINO), meaning that the input can be one of <NUM> different values. Each of the <NUM> different combinations of bit values corresponds to different numbers of input pulses to be applied to the control gate of the selected cell, which will then generate an output current representing the multiplication of the input value and the stored weight, W, in that cell. A greater number of pulses will cause a greater output value (current) of the cell. An example of input bit values, DIN[<NUM>:<NUM>] and the corresponding number of pulses applied to the control gate is shown in Table No. <NUM>:.

In the above example, there are a maximum of <NUM> pulses for <NUM> bit digital values for reading out the cell value. Each pulse is equal to one unit cell value (current). For example, if Icell unit = 1nA, then for DIN[<NUM>-<NUM>] = <NUM>, Icell = <NUM>*1nA = 1nA,; and for DIN[<NUM>-<NUM>] = <NUM>, Icell = <NUM>*1nA = 15nA.

In another embodiment, the digital bit input uses digital bit position summation to read out the cell value as shown in Table <NUM>. Here, only <NUM> pulses are needed to evaluate the <NUM> bit digital value. For example, a first pulse is used to evaluate DIN0, a second pulse is used to evaluate DIN1, a third pulse is used to evaluate DIN2, and a fourth pulse is used to evaluate DIN3. Then, the results from the four pulses are summed according to bit position. The digital bit summation equation realized is the following: Output =<NUM>^<NUM>*DIN0 + <NUM>^<NUM>*DIN1 + <NUM>^<NUM>*DIN2 + <NUM>^<NUM>*DIN3)*Icell unit.

For example, if Icell unit = 1nA, then for DIN[<NUM>-<NUM>] = <NUM>, Icell total = <NUM>+<NUM>+<NUM>+<NUM>*1nA = 1nA; and for DIN[<NUM>-<NUM>] = <NUM>, Icell total = <NUM>*1nA + <NUM>*1nA + <NUM>*1nA + <NUM>*1nA =15nA.

<FIG> depicts an example of charge summer <NUM> that can be used to sum the output of a VMM during a verify or read operation to obtain a single analog value that represents the output, and that can optionally be then converted into digital bit values. Charge summer <NUM> comprises current source <NUM> and an array of sample-and-hold circuits comprising switches <NUM> and sample-and-hold (S/H) capacitors <NUM>. As shown for an example of a <NUM>-bit digital value, there are <NUM>/H circuits to hold the value from <NUM> evaluation pulses, where the values are summed up at the end of the process. S/H capacitors <NUM> are selected with ratios that are associated with the <NUM>^n*DINn bit position for that S/H capacitor; for example C_DIN3 = x8 Cu DIN3 (where Cu is a unit capacitor), C_DIN2 = x4 Cu for bit DIN2, C_DIN1 = x2 Cu for bit DIN1, DINO = x1 Cu for bit DIN9. The current source <NUM> is also ratioed accordingly.

<FIG> depicts current summer <NUM> that can be used to sum the output of a VMM during a verify or read operation. Current summer <NUM> comprises current source <NUM> (which is Icell, the output of the VMM array), transistor <NUM>, switch <NUM>, node <NUM>, and transistor <NUM>. In this example, current summer <NUM> outputs four digital values on node <NUM> in a serial fashion, DINO, DIN1, DIN2, and DIN3. Four evaluation pulses are input to the VMM array in sequence. During the first pulse, for time period t_DINO, the switch <NUM> corresponding to DINO is closed and the other switches <NUM> are open. During the second pulse, for time period t_DIN1, the switch <NUM> corresponding to DIN1 is closed and the other switches are open. During the third pulse, the switch <NUM> corresponding to DIN2 is closed for time period t_DIN2, and the other switches are open. During the fourth pulse, the switch <NUM> corresponding to DIN3 is closed, for time period t_DIN3, and the other switches are open. At the end of the process, the values are summed up to generate a digital output, where a weighting process is applied to the DIN values based on the relative bit position of DIN. For example, DOUT can equal <NUM>* I_DIN3 + <NUM> * I_DIN2, + <NUM>* I_DIN1 + <NUM>*I_DIN0.

<FIG> depicts output block <NUM> (which is an embodiment of output block <NUM> in <FIG>). Output block <NUM> receives an output current from a VMM array (such as array <NUM> in <FIG>), here shown as ICELL <NUM>. Output block <NUM> comprises D/A converter <NUM>, shifter <NUM>, adder <NUM>, and output register <NUM>.

Here, it is assumed that the input to the input block (such as input block <NUM> in <FIG>) of VMM is DIN[n:<NUM>], where n is an input bit binary index number and there are i bits total, where i can range from <NUM> to n+<NUM>. For example, if i= <NUM>, then the input will be four input bits, DIN3, DIN2, DIN1, and DIN0. Each input bit, DINx , is applied to the input block <NUM> of VMM <NUM> one at a time.

Input block <NUM> converts DINx into an input signal (using one of the embodiments described herein or other known techniques) that is applied to a terminal of the selected cell in array <NUM> (where the selected cell is selected by word line decoder <NUM> and a selected bit line, not shown). In one embodiment, the input signal is a single pulse of variable duration, as shown in Table <NUM> for an exemplary <NUM>-bit input. The input signal (row input to VMM array) of the pulse TPULSE has a width proportional to the decimal value (<NUM> to <NUM>) of the datain DIN [<NUM>:<NUM>].

In another embodiment, the input signal is an analog bias voltage, as shown in Table 14A for an exemplary <NUM>-bit input. The input signal may have <NUM> voltage levels, for example, linearly spaced for cells operating in a linear region. Alternately, the input signal may be logarithmically spaced (meaning a voltage value is proportional to the log of the cell current) for cells operating in a sub-threshold region, for example VCGINk = VCGIN(k-<NUM>) - (<NUM>/n*Vt)* LN <NUM> for binary current values, VCGIN is the voltage on the corresponding CG terminal.

A <NUM>-bit input DIN [<NUM>:<NUM>] for a particular row will cause one voltage level out of <NUM> levels (e.g., VCGIN0,. , or VCGIN15) to be selected and applied to the row of the VMM array. In one embodiment, this operation operates on all four input data bits at the same time, meaning that the four input data bits will be converted into one of <NUM> possible voltage levels and applied to a row. In an alternative embodiment, the data input bits are applied one at a time in a sequential manner (input bitwise-operation), and the result for each data input is then added (summed) together in an analog domain (<FIG>, <FIG>) or in the digital domain (<FIG>, <FIG>). Each data input bit can be weighted based on its bit position. For example a "<NUM>" in the least significant bit location might cause the voltage VCGIN1 to be applied as an input to a row of the VMM array while a "<NUM>" in the most significant bit location might cause the voltage VCGIN8 to be applied as an input to a row of the VMM array, such as by using output block <NUM> in <FIG>.

In another embodiment, the input signal to the input block of the array is an exemplary <NUM>-bit input shown in Table 14B for input bit-wise operation (e.g., operation is done for DIN0, then DIN1, then DIN2, then DIN3 input) with a constant analog bias voltage for cells operating in linear or sub-threshold or any regions.

The binary weighted result per input bit DIN is summed together in the analog domain, such as by using a current summer such as the one shown in <FIG>, or in the digital domain, such as by using the embodiments of <FIG> or <FIG> depicts digital summer <NUM>, which the same as digital summer <NUM> in <FIG> except that specific weights have been assigned to each output stream generated in response to an input bit.

In another embodiment, the input signal to the input block of the array is an exemplary <NUM>-bit input as shown in Table 14C for input multibit-wise operation (e.g., DIN3 and DIN2 together, and DIN1 and DIN0 together) with examples of four analog bias levels. In one embodiment four analog levels are linearly spaced for cells operating in linear region, e.g., 0V,. 5V,<NUM> V to ensure linear equal scaling for the output cell currents. In another embodiment the levels are log spaced for cells operating in sub-threshold to ensure linearly scaling for the output cell currents, meaning for example the voltage value is proportional to a log of the current for cells operating in sub threshold region, for example VCGINk = VCGIN(k-<NUM>) - (<NUM>/n*Vt)* LN <NUM> for binary current values.

The binary weighted result per multibit DIN [<NUM>:<NUM>] and DIN [<NUM>:<NUM>] are summed together in the analog domain (like current summer in <FIG>) or in the digital domain (<FIG>, <FIG>).

In another embodiment, the input signal is a hybrid signal comprising an analog bias voltage component added with a pulse component (analog bias supply modulated pulse), as shown in Table <NUM> for an exemplary <NUM>-bit input with analog bias supply and pulses. The pulses may be modulated by length (TPULSE) or by number of pulses within a predetermined time period (PULSES):.

In the above table, a value of "<NUM>. 5X" means a pulse with a width equal to <NUM> times the width of a 1X pulse, or <NUM>1X pulses plus a pulse with half the width of a 1X pulse.

The input data is partitioned into multiple input data-in sets, with each data-in set being assigned to a particular voltage bias level For example for an <NUM>-bit input DIN [<NUM>:<NUM>], a first row supply VCGIN1 is applied for input bits in the set DIN [<NUM>:<NUM>], and a second row supply VCGIN2, different than VCGIN1, is applied for input bits in the set DIN [<NUM>:<NUM>]. In this exemplary embodiment of a two binary input set partition, the analog bias supply VCGIN2 (for the second data-in set DIN [<NUM>:<NUM>]) produces a cell current that is 2x the cell current that is produced by the analog bias supply VCGIN1 (for the first data-in set DIN [<NUM>:<NUM>]). For example, the ratio of VCGIN2/VCGIN1 can be 2x for cells operating in linear region. Because a different VCGIN voltage is applied for each data-in set, the same number of pulses with the same periods can be applied for a member of data-in set DIN[<NUM>:<NUM>] and a member of data-in set DIN[<NUM>:<NUM>], as the difference in VCGIN will differentiate the two members.

In a variation of this embodiment, two partitions can be used for each input data-in set, where each partition corresponds to a different analog bias voltage, meaning that four different voltages VCGIN1, VCGIN2, VCGIN3, and VCGIN4 are used. This can further reduce the number/period of pulses needed. That is, four different data-in values can use the same number/period of pulses, as the difference in VCGIN will differentiate the four different values.

With reference again to <FIG>, output block <NUM> receives the output current, ICELL, from VMM in response to the input DINx. D/A converter <NUM> converts ICELL into digital form, DOUT [m:<NUM>], that represents the digital value of the output generated in response to DINn, where each DOUT_n is a set of one or more output bits.

Shifter <NUM>, adder <NUM>, and register <NUM> operate to apply a different weight to each output, DOUT[m:<NUM>]_n, that is generated in response to each input bit, DINn. In a simple example where n=<NUM>, shifter <NUM>, adder <NUM>, and register <NUM> perform the following actions:.

In the case the DIN [n:<NUM>] inputs are combined with an analog voltage level to represent for the binary weight of each data input, only adding is needed, without shifting for such a hybrid input bitwise-operation. Output register <NUM> stores and outputs the result of (<NUM>) as DOUT.

<FIG> depicts digital summer <NUM>, which receives a plurality of digital values, sums them together, and generates an output DOUT representing the sum of the inputs. Digital summer <NUM> can be used during a verify or read operation. <FIG> depicts an example of a <NUM>-bit digital value comprising bits DOUT0, DOUT1, DOUT2, and DOUT3. Each bit is generated from an evaluation input pulse. Each bit can be weighted based on its bit position, where a weight, t_DINn, of <NUM>^n is applied to bit DINn. For example, DOUT3 can be multiplied by <NUM>^<NUM> (=<NUM>), DOUT2 can be multiplied by <NUM>^<NUM> (=<NUM>), DOUT1 can be multiplied by <NUM>^<NUM> (=<NUM>), and DOUT0 can be multiplied by <NUM>^<NUM> (=<NUM>).

<FIG> shows an integrating dual-slope ADC <NUM> applied to an output neuron to convert the array cell current into digital output bits DOUTx. An integrator consisting of integrating op-amp <NUM> and integrating capacitor <NUM> integrates a cell current ICELL versus a reference current IREF. As shown in <FIG>, during a fixed time t1 (integration time) , the cell current is up integrated (VOUT rises), and then a reference current is applied and down integrated for a time t2 (VOUT falls, de-integration time). The current Icell is = t2/t1* IREF. For example, for t1, for a <NUM> bit digital bits resolution, <NUM> cycles are used, and the cycle number for t2 varies from <NUM> to <NUM> cycles depending on the Icell value. Digital counter <NUM>, enabled by the signal EC, is used to generate digital output bits DOUTx during the t2 period.

<FIG> shows integrating single slope ADC <NUM> applied to an output neuron to convert the array cell current into digital output bits. An integrator consisting of integrating op-amp <NUM>, integrating capacitor <NUM>, switch S3, and comparator <NUM> integrates a array cell current ICELL <NUM> and generates an output signal EC.

As shown in <FIG>, graph <NUM> shows that during a time t1, a cell current ICELL1 is up integrated (VOUT rises until it reaches VREF2, which corresponds to a change in value of EC in <FIG>), and during time t2, another cell current ICELL2 is up integrated. The cell current ICELL = Cint*VREF2/t, where t is the time that elapses before EC changes value. Pulse counter <NUM>, enabled by the signal EC, is used to count the number of pulses during integration time t, and the number of pulses represents the digital output value DOUTx.

In the example shown, the digital output for t1 will be less than the digital output for t2 since the count for t1 will be less than the count for t2, which also means that the cell current ICELL1 during time period t1 was larger than the cell current ICELL2 during time period t2. An initial calibration is done to calibrate the integrating capacitor <NUM> value with a reference current Iref and a fixed time Tref, Cint = Tref*Iref/VREF2.

<FIG> shows integrating dual slope ADC <NUM> comprising ICELL <NUM>, comparator <NUM>, switch S1, switch S2, switch S3, capacitor <NUM>, and reference current source <NUM>. Integrating dual slope ADC <NUM> receives output neuron current (ICELL <NUM>) and generates output EC. The integrating dual slope ADC <NUM> does not utilize an integrating op-amp. The cell current or the reference current is integrated directly on the capacitor <NUM>. A pulse counter <NUM>, enabled by the signal EC, is used to count pulses during integration time, where the integration time ends when EC changes value. The output of the pulse counter is a digital output DOUTx representing ICELL. The current ICELL is = t2/t1* IREF.

<FIG> shows integrating single slope ADC <NUM> comprising ICELL <NUM>, comparator <NUM>, switch S2, switch S3, and capacitor <NUM>. Integrating single sloped ADC <NUM> receives output neuron current (ICELL <NUM>) and generates output EC. The integrating single slope ADC <NUM> does not utilize an integrating op-amp. The cell current is integrated directly on the capacitor <NUM>. A pulse counter <NUM>, enabled by the signal EC, is used to count digital output pulses during integration time, where the integration time ends when EC changes value. The output of the pulse counter is a digital output DOUTx representing ICELL. The cell current ICELL = Cint*VREF2/t.

<FIG> shows a SAR (Successive Approximation Register) ADC <NUM> applied to an output neuron to convert a cell (array) current into digital output bits. Cell current can be dropped across a resistor to convert into a VCELL. Alternatively, the cell current can be used to charge up a S/H capacitor to convert into a VCELL. A binary search is used to compute the bit starting from MSB bit (most significant bit). Basing on the digital bits from SAR <NUM>, DAC <NUM> is used to set an appropriate analog reference voltage to comparator <NUM>. The output of the comparator <NUM> is fed back to SAR <NUM> to choose the next analog level. As shown in <FIG>, for the example of <NUM>-bit digital output bits, there are <NUM> evaluation periods: a first pulse to evaluate DOUT3 by setting an analog level half-way, then a second pulse to evaluate DOUT2 by setting an analog level half-way of the top-half or half-way of the bottom-half. DOUT3 and DOUT4 similarly divide the ranges in half. Another embodiment can use SAR CDAC (charge re-distribution CDAC) to convert a neuron current into digital output bits.

<FIG> shows sigma delta ADC <NUM> applied to an output neuron to convert a cell current into digital output bits. An integrator consisting of op-amp <NUM> and capacitor <NUM> integrates the summation of current from a selected cell current and a reference current resulting from <NUM>-bit current DAC <NUM>. A comparator <NUM> compares the integrated output voltage versus a reference voltage. The clocked DFF <NUM> provides digital output streams depending on the output of the comparator <NUM>. The digital output stream typically goes to a digital filter before outputting digital output bits.

<FIG> depicts output block <NUM>. Output block <NUM> comprises current-to-voltage converter <NUM> and analog-to-digital converter <NUM>. Output block <NUM> receives output current from the VMM array, here shown as Ineu, where the output current represents the output value from the VMM array for the read or verify operation being performed. Current-to-voltage converter <NUM> converts the output current Ineu into a voltage signal, here shown as VOUT, such that the voltage VOUT represents the output current Ineu from the VMM. A/D converter <NUM> converts voltage VOUT into digital form and outputs a digital output, here shown as DOUT.

In one implementation of output block <NUM>, current-to-voltage converter <NUM> receives a sequence of currents from one or more selected non-volatile memory cells in the array in response to a sequence of inputs and converts the sequence of currents into a sequence of voltages. A/D converter then converts a sequence of voltages received from current-to-voltage converter <NUM> into a plurality of output bits, wherein the plurality of output bits is generated based upon a weighted sum of the sequence of voltages.

<FIG> depicts a loss-less (no I*Rmux drop) current-to-voltage converter <NUM>, which is an embodiment of current-to-voltage converter <NUM> in <FIG>. Current-to-voltage converter <NUM> comprises operational amplifier <NUM>; resistors <NUM>, <NUM>, <NUM>, and <NUM>; and switches <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. A loss-less variable resistor unit consists of a resistor and two switches (mux), e.g., resistor <NUM> and switches <NUM> and <NUM>, where one switch carries current (switch <NUM>) and one switch does not carry current (switch <NUM>), and the output is taken from the switch that does not carry current.

Current-to-voltage converter <NUM> receives current Ineu and outputs voltage VOUT. Notably, VOUT can be measured without suffering a voltage drop, due to muxing (I*R drop of the switches) in output voltage VOUT, meaning that the output voltage is sampled outside of the feedback loop or the current loop. For example, when switches <NUM> and <NUM> are closed (on) and the other switches are open (off), VOUT is equal to VREF + (R4602 + R4603 + R4604 + R4605)*(Ineu). As another example, when switches <NUM> and <NUM> are closed (on) and the other switches are open (off), VOUT is VREF + (R4602*Ineu). After the current Ineu is converted to a voltage VOUT, the voltage VOUT can be sampled and held by opening all switches. The voltage VOUT in this case references to reference level VREF.

<FIG> depicts current-to-voltage converter <NUM>, which is an embodiment of current-to-voltage converter <NUM> in <FIG>. Current-to-voltage converter <NUM> comprises comparator <NUM>; switches <NUM>, <NUM>, <NUM> and <NUM>; S/H (sample and hold) capacitor <NUM>; and variable resistor <NUM>. Current-to-voltage converter <NUM> receives current Ineu and outputs S/H voltage VOUT. Loss-less variable resistor <NUM> is similar to resistor <NUM> in <FIG>. During the current to voltage conversion, the current Ineu flows through the resistor <NUM> to generate an output voltage = R4704*Ineu, the S1 (<NUM>), S2 (<NUM>) and S3 (<NUM>) are closed (on) and S4 (<NUM>) is open-ed (off), the output VOUT is = R4704*Ineu since S3 does not carry current. During the hold period, S4 is closed (on) and S1, S2 and S3 are open-ed (off), the VOUT is held on the capacitor <NUM>. Notably, VOUT can be measured without suffering a voltage drop because VOUT is measured (enabled) outside of the switches that carry current.

<FIG> depicts current-to-voltage converter <NUM>, which is an embodiment of current-to-voltage converter <NUM> in <FIG>. Current-to-voltage converter <NUM> comprises operational amplifier <NUM>; switches <NUM> and <NUM>; S/H capacitor <NUM>; and variable resistor <NUM>. Current-to-voltage converter <NUM> receives current Ineu and outputs voltage VOUT. Notably, VOUT can be measured without voltage drop due to VOUT is measured (enabled) outside of the switches (muxes) that carry current. During the current to voltage conversion, the current Ineu flows through the resistor <NUM> to generate an output voltage = R4804*Ineu, the S1 (<NUM>) and S2 (<NUM>) are closed (on), the output VOUT is = R4804*Ineu since S2 does not carry current. During the hold period, S1 and S2 are open-ed (off), the VOUT is held on the capacitor <NUM> The S/H voltage VOUT in this case references to ground level.

Alternatively, the current-to-voltage converter <NUM> and <NUM> does not contain variable resistor <NUM> or <NUM>, in which case Ineu charges up S/H capacitor <NUM> or <NUM> by a variable signal pulse enabling switch <NUM> or <NUM> controlled by a pre-determined trimmable timing pulse value, where the timing pulse value is selected based on the Ineu dynamic current range. In this case the S/H capacitor can be a variable capacitor with trimmable capacitance values.

<FIG> depicts current-to-voltage converter <NUM>, which is an embodiment of current-to-voltage converter <NUM> in <FIG>. Current-to-voltage converter <NUM> comprises switches <NUM> and <NUM>; variable resistor <NUM>; and capacitor <NUM>. Current-to-voltage converter <NUM> receives current Ineu and outputs voltage VOUT. During the current to voltage conversion, the current Ineu flows through the variable resistor <NUM> to generate an output voltage = R4903*Ineu, the S1 (<NUM>) closed (on), the output VOUT is = R4804*Ineu. During the hold period, S1 open-ed (off), the VOUT is held on the capacitor <NUM>, and the switches (muxes) inside the variable resistor <NUM> (for example S1a/S2a/S3a/S4a in the variable resistor <NUM> in <FIG>) are also opened (off). Notably, VOUT can be measured without suffering voltage drop due to VOUT is measured (enabled ) outside of the switches (muxes) that carry current.

<FIG> depicts variable resistor <NUM> as used in <NUM>. Variable resistor <NUM> comprises switches S1a, S2a, S3a, S4a, S1b, S2b, S3b, and S4b.

<FIG> depicts current-to-voltage converter <NUM>, which is an embodiment of current-to-voltage converter <NUM> in <FIG>. Current-to-voltage converter <NUM> comprises operational amplifier (op amp) <NUM>; level shifter <NUM> (gate of transistor <NUM> = drain of transistor <NUM> - Voffset); NMOS transistor <NUM>, PMOS transistors <NUM> and <NUM>; switches <NUM> and <NUM>; variable resistor <NUM> (which may be implemented as described above in relation to <FIG>); capacitor <NUM>; and voltage source VH. Current-to-voltage converter <NUM> receives current Ineu and outputs voltage VOUT. Notably, VOUT can be measured similarly (as in <FIG>) without suffering voltage drop. The S/H voltage VOUT in this case references to ground level. The op amp <NUM> and transistor <NUM> forces a fixed bias voltage VREF <NUM> on the bitline of the array during read operation. The PMOS transistor <NUM> and <NUM> serves as a variable ratio current mirror to mirror the array output current (Ineu) into the variable resistor <NUM> and S/H capacitor <NUM>. Alternatively current-to-voltage converter <NUM> does not contain variable resistor <NUM>, in which case the mirrored Ineu charges up S/H capacitor <NUM> by a variable signal pulse enabling switch <NUM> controlled by a pre-determined trimmable timing pulse value, where the timing pulse value is selected based on the Ineu dynamic current range. In this case the S/H capacitor can be a variable capacitor with trimmable capacitance values.

<FIG> depicts current-to-voltage converter <NUM>, which is an embodiment of current-to-voltage converter <NUM> in <FIG>. Current-to-voltage converter <NUM> comprises operational amplifier <NUM>; NMOS transistor <NUM>, variable resistor <NUM> (which may be implemented as described above in relation to <FIG>); switches <NUM> and <NUM>; capacitor <NUM>; and voltage source VH. Current-to-voltage converter <NUM> receives current Ineu and outputs voltage VOUT. Notably, VOUT can be measured without suffering voltage drop similarly as in <FIG> The S/H voltage VOUT in this case references to a high power supply VH. The op amp <NUM> and transistor <NUM> serves to force a fixed bias VREF <NUM> on the bitline during read operation. Alternatively, the current-to-voltage converter <NUM> does not contain variable resistor <NUM>, in which case Ineu discharges S/H capacitor <NUM> through a variable signal pulse enabling switch <NUM> controlled by a pre-determined trimmable pulse timing value, where the timing value is selected based on the Ineu dynamic current range. In this case the S/H capacitor can be a variable capacitor with trimmable capacitance values.

<FIG> depicts hybrid serial analog-to-digital converter <NUM> which utilizes the loss-less current to voltage converter <NUM> described above in relation to <FIG>. It consists of current to voltage converter <NUM>, comparator <NUM>, current sources <NUM> and <NUM>, and switches S1 and S2. Current to voltage converter <NUM> may instead be implemented using any of the current to voltage converters described above in <FIG>, <FIG>,<FIG>, <FIG>, and <FIG>. Current to voltage converter <NUM> comprises operational amplifier <NUM>, switch <NUM>, variable resistor <NUM> and sample and hold capacitor <NUM>.

<FIG> shows a timing diagram <NUM> of an operation of the hybrid serial ADC converter <NUM> in which during time period t1, the current ICELL <NUM> is converted into voltage VOUT by closing switch <NUM> (S2) while maintaining switch <NUM> (S1) open and then held by the capacitor <NUM> by opening switch <NUM> (S2). During the period t2 IREF <NUM> is enabled by closing switch <NUM> (S1) to begin the de-integration period, meaning the counting period, during which time, denoted as t2, clock pulses (not shown) are counted by pulse counter <NUM>, as long a EC is high, which is translated into the digital bits DOUT, i.e. the number of counts. The digital counter and clock and control logic to convert the comparator output EC into digital bits is not shown.

<FIG> shows another a timing diagram <NUM> of an operation of the hybrid serial ADC converter <NUM>, in which t1 period is same as that of the <FIG>. During time period t2, voltage VOUT is translated into digital bits DOUT by ramping the reference voltage VREF2 from a reference level such as VREF1 to its maximum level. During the time period t2, a digital counter (not shown) counts pluses, and the output of the digital counter is the output DOUT. The time period t2 ends when VREF2 exceeds VOUT, which will result in the value of EC changing in <FIG>.

Claim 1:
A system (<NUM>) comprising:
a vector-by-matrix multiplication array (<NUM>) in an artificial neural network, the array comprising a plurality of non-volatile memory cells;
an input block (<NUM>) to receive a digital input comprising n+<NUM> bits (DIN[n:<NUM>]), to apply the digital input to the array one bit at a time by converting the bit into an analog input signal and applying the analog input signal to a row of non-volatile memory cells in the array, wherein a "<NUM>" for the bit is converted into an analog input signal with a voltage whose magnitude depends on the bit location of the bit in the digital input; and
an output block (<NUM>, <NUM>) to receive an output current from the array in response to each analog input signal applied to the array and to combine the output currents to form an output (DOUT[m:<NUM>]), the output block comprising:
an analog-to-digital converter (<NUM>) to generate a digital value (DOUT_n) in response to each analog input signal applied to the array; and
an adder (<NUM>) to add the digital values from the analog-to-digital converter to generate the output (DOUT[m:<NUM>]);
a register (<NUM>) to store the output (DOUT[m:<NUM>]).