Patent Description:
The double data rate fifth-generation synchronous dynamic random-access memory (DDR5 SDRAM) is a high-bandwidth computer memory.

DDR5 generally includes two types of refresh commands: an all-bank refresh command and a same-bank refresh command. The same-bank refresh command only refreshes one bank at a time. The all-bank refresh command refreshes all-banks at a time. Thus, the counting methods for specific refresh times are also different.

The existing refresh method suitable for one type of refresh command cannot satisfy the refresh method of DDR5. Therefore, determination of a unified counting circuit suitable for DDR5 has become an existing urgent problem to be solved.

A patent application <CIT> and a patent application <CIT> provide teachings related to the technical field of the application.

According to a first aspect of the present disclosure, a refresh address counting circuit as set forth in claim <NUM> is provided.

In some embodiments of the present disclosure, the all-bank refresh mask submodule is further configured to generate the non-mask sub-signal in the normal refresh mode upon reception of the all-bank refresh command when the lowest bit of the current refresh address is an even number.

In some embodiments of the present disclosure, the all-bank refresh mask submodule is further configured to turn off the mask sub-signal and generate the non-mask sub-signal when a system reset signal is generated or a cycle refresh command in the next refresh cycle is received.

In some embodiments of the present disclosure, the all-bank refresh mask submodule includes a first NOR gate, a first NAND gate, a first latch, and a first NOT gate, where a first input terminal of the first NOR gate is configured to receive the system reset signal and a second input terminal of the first NOR gate is configured to receive the cycle refresh command, and an output terminal of the first NOR gate is connected to a reset terminal of the first latch; an input terminal of the first NAND gate is configured to receive a normal refresh mode command, a lowest bit odd signal of the current refresh address, and the all-bank refresh command, and an output terminal of the first NAND gate is connected to a set terminal of the first latch; and an output terminal of the first latch is connected to an input terminal of the first NOT gate, and an output terminal of the first NOT gate is configured to output the mask signal.

In some embodiments of the present disclosure, the same-bank refresh mask submodule includes a bank refresh counter, a reset signal generator, and a mask signal generator, where the bank refresh counter is configured to obtain the refresh state of each of banks and generate a refresh cycle signal after each bank has been refreshed once, the mask signal generator is configured to generate the mask sub-signal or the non-mask sub-signal based on the refresh state of each bank, and the reset signal generator is configured to generate, based on the all-bank refresh command, a self-refresh command, a system reset signal and the refresh cycle signal, a reset signal for resetting the bank refresh counter to generate the non-mask sub-signal.

In some embodiments of the present disclosure, the bank refresh counter includes multiple exclusive-OR (XOR) gates, multiple first AND gates, multiple counters, and a second AND gate, where each of the multiple XOR gates is configured to receive a preset bank address and a refresh bank address, an output terminal of each of the multiple XOR gates is connected to a first input terminal of a respective one of the multiple first AND gates, each of the multiple first AND gates has a second input terminal configured to receive the same-bank refresh command, and an output terminal connected to a set terminal of one of the multiple counters, each of the multiple counters has a reset terminal configured to receive the reset signal and an output terminal connected to a respective inverter configured to output the refresh state; each XOR gate corresponds to a respective first AND gate, a respective counter, and a respective inverter; and an input terminal of the second AND gate is connected to output terminals of the multiple inverters, and an output terminal of the second AND gate is configured to output the refresh cycle signal.

In some embodiments of the present disclosure, the mask signal generator includes a second NOT gate, a second NAND gate, and a second latch, where a first input terminal of the second NAND gate is configured to receive the refresh cycle signal through the second NOT gate, a second input terminal of the second NAND gate is configured to receive the same-bank refresh command, and an output terminal of the second NAND gate is connected to a reset terminal of the second latch; and a set terminal of the second latch is configured to receive the reset signal, and an output terminal of the second latch outputs the mask signal.

In some embodiments of the present disclosure, the reset signal generator includes: a NOR gate, wherein an input terminal of the NOR gate is configured to receive the all-bank refresh command, the self-refresh command, the system reset signal, and the refresh cycle signal, and an output terminal of the NOR gate outputs the reset signal.

In some embodiments of the present disclosure, the self-oscillating mask module further includes an OR gate, where the all-bank refresh mask submodule and the same-bank refresh mask submodule are connected in parallel, and a first input terminal of the OR gate is connected to an output terminal of the all-bank refresh mask submodule and a second input terminal of the OR gate is connected to an output terminal of the same-bank refresh mask submodule, and an output terminal of the OR gate is connected to the refresh address counting module.

In some embodiments of the present disclosure, the circuit further includes a third AND gate, where a first input terminal of the third AND gate is connected to an output terminal of the self-oscillating mask module and a second input terminal of the third AND gate is connected to an output terminal of the self-oscillating clock generation module, and an output terminal of the third AND gate is connected to an input terminal of the refresh address counting module.

In some embodiments of the present disclosure, the self-oscillating clock generation module includes an edge generation unit and a delay unit, where the edge generation unit is configured to acquire each of the at least one bank activation signal in the refresh cycle, and extract falling edge information of the bank activation signal; and the delay unit is configured to adjust timing of the falling edge information.

In some embodiments of the present disclosure, the edge generation unit includes two NAND gates, two NOT gates, and a first delayer, where a first input terminal of a first one of the two NAND gates is configured to receive a refresh cycle signal and a second input terminal of the first one of the two NAND gates is configured to receive the bank activation signal, and a first input terminal of a second one of the two NAND gates is connected to an output terminal of the first one of the two NAND gate; an input terminal of a first one of the two NOT gates is connected to the output terminal of the first one of the two NAND gates, an output terminal of the first of the two NOT gates is connected to a second input terminal of the second one of the two NAND gates, and the first delayer is provided between the output terminal of the first one of the two NOT gates and the second input terminal of the second one of the two NAND gates; and an output terminal of the second one of the two NAND gates is connected to an input terminal of the second one of the two NOT gates, and an output terminal of the second one of the two NOT gates is configured to output the falling edge information of the bank activation signal. The delay unit includes a second delayer, where an input terminal of the second delayer is connected to the output terminal of the second one of the two NOT gates, and an output terminal of the second delayer is configured to output the self-oscillating clock signal.

According to the second aspect of the present disclosure, a refresh address counting method is provided, which is used for the above refresh address counting circuit, the method includes operations as set forth in claim <NUM>.

According to the third aspect of the present disclosure, a refresh address read-write circuit as set forth in claim <NUM> is provided.

In some embodiments of the present disclosure, the latch module includes a multiplexer and a latch, where a first input terminal of the multiplexer is configured to receive a self-oscillating refresh address and a second input terminal of the multiplexer is configured to receive activation address from the refresh address counting circuit, a control terminal of the multiplexer is configured to receive a refresh cycle signal, an output terminal of the multiplexer is connected to an input terminal of the latch, and an output terminal of the latch is connected to the decoding module.

According to the fourth aspect of the present disclosure, an electronic device as set forth in claim <NUM> is provided.

Exemplary embodiments will be more comprehensively described with reference to the drawings. However, the exemplary embodiments may be implemented in a variety of forms, and should not be understood to be limited to the examples set forth herein. Rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and so that the concept of the exemplary embodiments is comprehensively communicated to those who are skilled in the art. The features, structures, or characteristics described may be incorporated in one or more embodiments by using any suitable means. In the following description, numerous specific details are presented to provide a sufficient understanding of the embodiments of the present disclosure. However, a person skilled in the art will be aware that the technical solutions of the present disclosure may be implemented by omitted one or more of the specific details, or by using other methods, components, devices, steps, and the like. In other situations, known technical solutions are not shown or described in detail so as not to detract the main points and obscure various aspects of the present disclosure.

Furthermore, the drawings are merely schematic representations of the present disclosure and are not necessarily drawn to scale. The same reference marks in the drawings denote the same or similar parts, and therefore repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily have to correspond to physically or logically separate entities. These functional entities may be implemented as software, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and/or processor devices and/or microcontroller devices.

The flowchart shown in the drawings is for illustrative purposes only and does not necessarily include all steps. For example, some steps may also be separated, while some steps may be combined or partially combined, and thus the actual execution order may vary according to actual situations. In addition, all of the terms "first", "second", and "third" below are for purposes of distinction only and should not be used as limitations on the content of the present disclosure.

DDR4 is the abbreviation for the fourth-generation DDR SDRAM. DDR5 is the abbreviation for the fifth-generation DDR SDRAM. DDR SDRAM is an abbreviation for double data rate SDRAM, while SDRAM is an abbreviation for synchronous dynamic random access memory, and a synchronization object is a system clock frequency. Thus, in combination, DDR4 is a fourth-generation double data rate synchronous dynamic random-access memory, and DDR5 is a fifth-generation double data rate synchronous dynamic random-access memory. From DDR4 to DDR5, a refresh instruction changes from a single refresh command to an all-bank refresh command REFab and a same-bank refresh command REFsb.

For DDR5, multiple refresh modes (REF Modes) are typically included, including a normal refresh mode (Normal <NUM>×), a double-rate normal refresh mode (Normal <NUM>×), a double fine-grained refresh mode (FGR <NUM>×), etc..

With reference to <FIG>, for an all-bank refresh command REFab, in the normal refresh mode (Normal <NUM>×), when the REFab command is processed in a DRAM, a self-oscillating refresh address is generated, and meanwhile a global refresh counter performs global refresh counting. While the self-oscillating refresh address is being generated, the parity (REF Count) of the current self-oscillating refresh address is monitored. In <FIG>, Odd represents an odd number, and Even represents an even number.

As shown in <FIG>, when the refresh mode (REF Mode) switches from FGR <NUM>× to Normal <NUM>×, if the current count of REF Count is an even number Even, then the global refresh counter continues to count in an even number counting manner, i.e., a +<NUM> manner, so that the REF Count is still recorded as an even number Even at the end of Normal <NUM>×.

With reference to <FIG>, when the refresh mode (REF Mode) switches from FGR <NUM>× to Normal <NUM>×, if the current count of REF Count is an odd number Odd, then in the Normal <NUM>× refresh mode, when the REFab command is received for the first time, REF Count is first added by <NUM> so as to obtain an even number Even, and then counting is performed as normal in the +<NUM> manner to ensure that the recorded REF Count is still an even number Even at the terminal of the Normal <NUM>× refresh mode.

It should be noted that one refresh interval is present between two adjacent REFab commands in <FIG> and <FIG>.

With reference to <FIG>, for a same-bank refresh command REFsb, each REFsb command only correspondingly refreshes one bank. Therefore, before all banks are refreshed, the global refresh counter does not increment for consecutively issued REFsb commands. The global refresh counter does not increment until all banks have been refreshed. To count the number of banks per refresh, an internal bank counter is also added in <FIG> to count each bank refreshed under the REFsb command.

Since the refresh command of DDR5 and the refresh command of DDR4 are different, and a different counting manner is used in a refresh mode switching process in DDR5, the counting manner applicable to DDR4 thus cannot meet the requirements of DDR5.

In view of this, an exemplary embodiment of the present disclosure provides a refresh address counting circuit, and the refresh address counting circuit is mainly used in DDR5. With reference to <FIG>, a refresh address counting circuit <NUM> may include a self-oscillating clock generation module <NUM>, a self-oscillating mask module <NUM>, and a refresh address counting module <NUM>.

The self-oscillating clock generation module <NUM> may be configured to generate, upon acquiring a refresh signal, a self-oscillating clock signal based on at least one bank activation signal in each of refresh cycles. With reference to <FIG> and <FIG>, the self-oscillating clock generation module <NUM> is mainly configured to generate a self-oscillating clock signal OSC_CLK_Pre. As long as a bank activation signal BANK_ACT is currently present, the self-oscillating clock signal OSC_CLK_Pre will be generated regardless of whether a current refresh instruction is an all-bank refresh command REFab or a same-bank refresh command REFsb. In addition, one bank activation signal BANK_ACT corresponds to one self-oscillating clock signal OSC_CLK_Pre.

The self-oscillating mask module <NUM> may be configured to generate a self-oscillating mask signal under a preset refresh command. In an exemplary embodiment of the present disclosure, the preset refresh command may be the above same-bank refresh command REFsb, the all-bank refresh command REFab, and may also be a self-refresh command SREF. For example, in one refresh cycle, the self-oscillating mask signal OSC_MASK generated by the self-oscillating mask module <NUM> may be used to mask the self-oscillating clock signal OSC_CLK_Pre.

In an actual application, all banks are refreshed under an all-bank refresh command REFab or a self-refresh command SREF, which is equivalent to one refresh cycle, and therefore, as shown in <FIG>, the self-oscillating mask signal OSC_MASK does not mask the self-oscillating clock signal OSC_CLK_Pre under one all-bank refresh command REFab or self-refresh command SREF. In this case, the generated self-oscillating mask signal OSC_MASK is a non-mask sub-signal. This means that the non-mask sub-signal is used to not mask the self-oscillating clock signal OSC_CLK_Pre under the all-bank refresh command REFab or the self-refresh command SREF.

However, multiple same-bank refresh commands REFsb are typically generated in one refresh cycle. Therefore, as shown in <FIG>, in one refresh cycle, the self-oscillating clock signal OSC_CLK_Pre generated based on the multiple bank activation signals BANK_ACT is masked by the self-oscillating mask signal OSC_MASK, and a masked target self-oscillating clock signal OSC_CLK is generated only once in one refresh cycle. In this case, the generated self-oscillating mask signal OSC_MASK is a mask sub-signal, and the mask sub-signal is used to mask the self-oscillating clock signal OSC_CLK_Pre under the same-bank refresh command REFsb.

In an exemplary embodiment of the present disclosure, the above self-oscillating clock signal OSC_CLK_Pre and self-oscillating mask signal OSC_MASK are both steady and sustained oscillations that are self-generated without any externally applied excitation signals. Therefore, self-oscillation is added to the names of the self-oscillating clock signal OSC_CLK_Pre and the self-oscillating mask signal OSC_MASK as an indication.

In the refresh address counting circuit provided in an exemplary embodiment of the present disclosure, the refresh address counting module <NUM> may be configured to count refresh addresses based on the self-oscillating clock signal OSC_CLK_Pre and the self-oscillating mask signal OSC_MASK and to output a self-oscillating refresh address OSC_RA. That is, the refresh address counting module <NUM> counts the refresh addresses based on a result of masking of the self-oscillating clock signal OSC_CLK_Pre performed by the self-oscillating mask signal OSC_MASK.

In an exemplary embodiment of the present disclosure, in addition to the self-oscillating clock signal OSC_CLK_Pre being masked by means of the self-oscillating mask signal OSC_MASK in one refresh cycle so as to count refresh addresses as described above, there are also the situations that are shown in <FIG> and <FIG>, that is, in a refresh mode switching process, the self-oscillating clock signal OSC_CLK_Pre is masked based on a parity state of a current refresh address.

Specifically, in the exemplary embodiment of the present disclosure, with reference to <FIG>, the self-oscillating mask module <NUM> includes an all-bank refresh mask submodule <NUM> and a same-bank refresh mask submodule <NUM>. The all-bank refresh mask submodule <NUM> may be configured to generate a mask sub-signal in a normal refresh mode Normal <NUM>× upon reception of an all-bank refresh command REFab when the lowest bit REF Count of a current refresh address is an odd number Odd. The mask sub-signal masks the self-oscillating clock signal OSC_CLK_Pre so that all-bank address alignment work is first performed in the first cycle. Then, an even address is newly generated, so that the refresh address generated at the end of refreshing is still an even address.

Once a mask sub-signal is generated, if the mask sub-signal needs to be turned off, then the all-bank refresh mask submodule <NUM> may be used to turn off the mask sub-signal and to generate a non-mask sub-signal when a system reset signal RST is generated or when a cycle refresh command REF2 is received in the next refresh cycle, so that after the refresh address is masked in a first refresh cycle, the mask is released in a second refresh cycle, so as to ensure that the final refresh address is an even address.

In addition, the all-bank refresh mask submodule <NUM> may be further configured to generate the non-mask sub-signal in the normal refresh mode Normal <NUM>× upon reception of the all-bank refresh command REFab when the lowest bit of the current refresh address is an even number Even, so as to maintain the normal counting of refresh addresses, so that the refresh address generated after refreshing has ended is still an even address.

On the basis of the above functional description, provided in an exemplary embodiment of the present disclosure is a circuit structure of the all-bank refresh mask submodule <NUM>. With reference to <FIG>, the all-bank refresh mask submodule <NUM> includes a first NOR gate <NUM>, a first NAND gate <NUM>, a first latch <NUM>, and a first NOT gate <NUM>. An input terminal of the first NOR gate <NUM> is configured to receive the system reset signal RST and the cycle refresh command REF2, so as to output a high level when the system reset signal RST and the cycle refresh command REF2 are both low levels. An output terminal of the first NOR gate <NUM> is connected to a reset terminal of the first latch <NUM>. The first latch <NUM> includes two NAND gates. When input at the reset terminal of the first latch is a high level, an output terminal of the first latch <NUM> depends on a signal input at a set terminal of the first latch.

An input terminal of the first NAND gate <NUM> is configured to receive a normal refresh mode Normal <NUM>× command, the lowest bit odd signal REF Count of the current refresh address, and the all-bank refresh command REFab, and an output terminal of the first NAND gate <NUM> is connected to the set terminal of the first latch <NUM>. When three input signals of the first NAND gate are all high level, that is, when the all-bank refresh command is received in the normal refresh mode and the lowest bit of the current refresh address is an odd signal, the first NAND gate <NUM> outputs a low level.

Under the action of the low level output by the first NAND gate <NUM> and the high level output by the first NOR gate <NUM>, the output terminal of the first latch <NUM> outputs a low level. However, if at least one of the system reset signal RST and the cycle refresh command REF2 is a high level, the output terminal of the first latch <NUM> outputs a high level.

In addition, since the output terminal of the first latch <NUM> is connected to an input terminal of the first NOT gate <NUM>, the output terminal of the first NOT gate <NUM> outputs the self-oscillating mask signal OSC_MASK. When the first latch <NUM> outputs a low level, the self-oscillating mask signal OSC_MASK is a high level, i.e., the self-oscillating mask signal OSC_MASK is a mask sub-signal in this case, which is equivalent to the all-bank refresh mask submodule <NUM> outputting a mask sub-signal when an all-bank refresh command is received in the normal refresh mode and the lowest bit of a current refresh address is an odd signal. When the first latch <NUM> outputs a high level, the self-oscillating mask signal OSC_MASK is a low level, i.e., the self-oscillating mask signal OSC_MASK is a non-mask sub-signal in this case, which is equivalent to the mask sub-signal being turned off and the non-mask sub-signal being generated when the system reset signal RST is generated or the cycle refresh command REF2 is received.

It should be noted that the above all-bank refresh mask submodule <NUM> is provided when the high level is valid, and in situations in which the low level is valid, a corresponding inverter is provided. No further details will be described herein.

In an exemplary embodiment of the present disclosure, the same-bank refresh mask submodule <NUM> may be configured to generate the mask sub-signal upon reception of a same-bank refresh command REFsb before all the banks are refreshed. Therefore, in one refresh cycle, even if a same-bank refresh command is received, the self-oscillating clock signal OSC_CLK_Pre is still masked by means of the self-oscillating mask signal OSC_MASK, so as to achieve the purpose of counting refresh addresses only after all the banks are refreshed.

With reference to <FIG>, in an exemplary embodiment of the present disclosure, the same-bank refresh mask submodule <NUM> includes a bank refresh counter <NUM>, a reset signal generator <NUM>, and a self-oscillating mask signal generator <NUM>.

The bank refresh counter <NUM> may be configured to obtain a refresh state of each of the banks, and generate a refresh cycle signal after each bank has been refreshed once. The self-oscillating mask signal generator <NUM> may be configured to generate the mask sub-signal or the non-mask sub-signal based on the refresh state of each bank. The reset signal generator <NUM> may be configured to generate a reset signal based on the all-bank refresh command, the self-refresh command, the system reset signal, and the refresh cycle signal. The reset signal resets the bank refresh counter to generate the non-mask sub-signal.

A circuit structure of the bank refresh counter <NUM>, the reset signal generator <NUM>, and the self-oscillating mask signal generator <NUM> are described below by using an example in which the high level is valid.

In an exemplary embodiment of the present disclosure, with reference to <FIG>, the bank refresh counter <NUM> includes multiple XOR gates <NUM>, multiple first AND gates <NUM>, multiple counters <NUM>, and a second AND gate <NUM>. Each of the multiple XOR gates <NUM> is configured to receive a preset bank address BA1, BA2, BA3, or BA4 (<FIG> shows four banks) and a refresh bank address REF_BA. An output terminal of each XOR gate <NUM> is connected to a first input terminal of a respective one of the multiple first AND gates <NUM>. Each of the multiple first AND gates <NUM> has a second input terminal configured to receive the same-bank refresh command REF_SB and an output terminal configured to receive a set terminal of one of the multiple counters <NUM>. Each of the multiple counters <NUM> has a reset terminal configured to receive a reset signal RSTB. The reset signal RSTB is determined by the reset signal generator <NUM>.

An output terminal of each of the multiple counters <NUM> is provided with an inverter <NUM>. Each of the multiple inverters <NUM> outputs the refresh state. Each XOR gate <NUM> corresponds to a respective first AND gate <NUM>, a respective counter <NUM>, and a respective inverter <NUM>. A group of the XOR gates <NUM>, first AND gates <NUM>, counters <NUM>, and inverters <NUM> output the refresh state of one bank and outputs, for example, a high level when the bank is refreshed. When four banks are all refreshed, each of the four inverters <NUM> outputs a high level. At this case, this means that each bank is refreshed once.

After the refresh state of each bank is determined, the refresh state can be received by the second AND gate <NUM>. Specifically, an input terminal of the second AND gate <NUM> is connected to output terminals of the multiple inverters <NUM>, and an output terminal of the second AND gate <NUM> is configured to output a refresh cycle signal REF_1CYCLE. When each of the multiple inverters <NUM> outputs a high level, the refresh cycle signal REF_1CYCLE output by the second AND gate <NUM> is a high level.

In an exemplary embodiment of the present disclosure, with reference to <FIG>, the self-oscillating mask signal generator <NUM> includes a second NOT gate <NUM>, a second NAND gate <NUM>, and a second latch <NUM>. A first input terminal of the second NAND gate <NUM> is configured to receive the refresh cycle signal REF_1CYCLE through the second NOT gate <NUM>. A second input terminal of the second NAND gate <NUM> is configured to receive the same-bank refresh command REFsb. An output terminal of the second NAND gate <NUM> is connected to a reset terminal of the second latch <NUM>. A set terminal of the second latch <NUM> is configured to receive the reset signal RSTB. An output terminal of the second latch <NUM> is configured to output the self-oscillating mask signal OSC_MASK.

By means of the self-oscillating mask signal generator <NUM>, when the refresh cycle signal REF_1CYCLE is a low level, it is indicated that one refresh cycle is not completed, and at this time, under the action of the same-bank refresh command REFsb, the output self-oscillating mask signal OSC_MASK is a high level, that is, a mask sub-signal is output. When the refresh cycle signal REF_1CYCLE is a high level, it is indicated that one refresh cycle is completed, and at this time, under the action of the same-bank refresh command REFsb, the output self-oscillating mask signal OSC_MASK is a low level, that is, a non-mask sub-signal is output.

In an exemplary embodiment of the present disclosure, with reference to <FIG>, the reset signal generator <NUM> includes an NOR gate <NUM>. An input terminal of the NOR gate <NUM> is configured to receive the all-bank refresh command REFab, the self-refresh command SREF, the system reset signal RST, and the refresh cycle signal REF_1CYCLE, and an output terminal of the NOR gate <NUM> is configured to output the reset signal RSTB. That is, when any one among the all-bank refresh command REFab, the self-refresh command SREF, the system reset signal RST, and the refresh cycle signal REF_1CYCLE is enabled, the reset signal RSTB is triggered. The triggered reset signal RSTB converts the mask sub-signal generated by the self-oscillating mask signal generator <NUM> into a non-mask sub-signal.

It can be seen on the basis of the above description that the all-bank refresh mask submodule <NUM> is configured to generate a mask sub-signal under an all-bank refresh command, and the same-bank refresh mask submodule <NUM> is configured to generate a mask sub-signal under a same-bank refresh command. The all-bank refresh mask submodule <NUM> and the same-bank refresh mask submodule <NUM> relate to different commands. Therefore, in the exemplary embodiment of the present disclosure, the all-bank refresh mask submodule <NUM> and the same-bank refresh mask submodule <NUM> are connected in parallel.

In addition, with reference to <FIG>, the self-oscillating mask module <NUM> further includes an OR gate <NUM>. An input terminal of the OR gate <NUM> is connected to an output terminal of the all-bank refresh mask submodule <NUM> and an output terminal of the same-bank refresh mask submodule <NUM>, and an output terminal of the OR gate <NUM> is connected to the refresh address counting module <NUM>. When either one among the all-bank refresh mask submodule <NUM> and the same-bank refresh mask submodule <NUM> outputs a mask sub-signal, a counting result of the refresh address counting module <NUM> will be affected.

In addition, in the exemplary embodiment of the present invention, when the self-oscillating mask signal OSC_MASK output by the self-oscillating mask module <NUM> masks the self-oscillating clock signal OSC_CLK_Pre output by the self-oscillating clock generation module <NUM>, a third AND gate <NUM> in <FIG> is further required. An input terminal of the third AND gate <NUM> is connected to an output terminal of the self-oscillating mask module <NUM> and an output terminal of the self-oscillating clock generation module <NUM>, and an output terminal of the third AND gate <NUM> is connected to an input terminal of the refresh address counting module <NUM>. The third AND gate <NUM> is configured to mask the self-oscillating clock signal OSC_CLK_Pre when the self-oscillating mask signal OSC_MASK is a low level and to not mask the self-oscillating clock signal OSC_CLK_Pre when the self-oscillating mask signal OSC_MASK is a high level.

Assuming that enabling is performed at a high level, an inverter needs to be further provided so as to invert the self-oscillating mask signal OSC_MASK output by the self-oscillating mask module <NUM>, as shown in <FIG>.

In an actual application, the refresh address counting module <NUM> may include multiple counting units. Each of the counting units is configured to perform counting based on the self-oscillating clock signal OSC_CLK_Pre that is output by the third AND gate <NUM> and that is not masked. The counting unit may include devices such as counters, etc., which will not be specifically defined by the exemplary embodiment of the present disclosure.

In the exemplary embodiment of the present disclosure, with reference to <FIG>, the self-oscillating clock generation module <NUM> may include an edge generation unit <NUM> and a delay unit <NUM>. The edge generation unit <NUM> is configured to acquire each of the at least one bank activation signal in the refresh cycle, and extract falling edge information of the bank activation signal. The delay unit <NUM> is configured to adjust timing of the falling edge information. Falling edge information eventually output by the self-oscillating clock generation module <NUM> is the self-oscillating clock signal OSC_CLK_Pre.

In an exemplary embodiment of the present disclosure, the edge generation unit <NUM> may include two NAND gates, two NOT gates, and a first delayer. An input terminal of a first one of the two NAND gates is configured to receive the refresh cycle signal and the bank activation signal. An input terminal of a second one of the two NAND gates is connected to an output terminal of the first one of the two NAND gates. An input terminal of a first one of the two NOT gates is connected to the output terminal of the first one of the two NAND gates. An output terminal of the first one of the two NOT gates is connected to the input terminal of the second one of the two NAND gates. The first delayer is further provided between the output terminal of the first one of the two NOT gates and the input terminal of the second one of the two NAND gates. An output terminal of the second one of the two NAND gates is connected to an input terminal of the second one of the two NOT gates. An output terminal of the second one of the two NOT gates is configured to output the falling edge information of the bank activation signal. The delay unit <NUM> may include a second delayer. An input terminal of the second delayer is connected to the output terminal of the second one of the two NOT gates, and an output terminal of the second delayer is configured to output the self-oscillating clock signal OSC_CLK_Pre. Herein, the structure of the edge generation unit <NUM> and the delay unit <NUM> is only exemplary, and a different structural form may be configured according to actual requirements, which is not specially defined by the exemplary embodiment of the present disclosure.

In conclusion, the refresh address counting circuit provided in the exemplary embodiment of the present disclosure generates a self-oscillating mask signal by the self-oscillating mask module, which can mask the self-oscillating clock signal generated by the bank activation signal according to an actual situation, and can eventually perform the refresh address counting based on the masked self-oscillating clock signal, so as to meet different requirements for different refresh commands in DDR5. In addition, the refresh address counting circuit can also enable refresh address counting to be performed in a refresh mode switching process. Functional requirements for different refresh modes and refresh instructions in DDR5 can be met by means of a single circuit structure, thereby improving the compatibility of the counting circuit.

Also provided in an exemplary embodiment of the present disclosure is a refresh address counting method. With reference to <FIG>, the refresh address counting method may specifically include the following operations S152, S154 and S156.

In operation S152, self-oscillating clock signal is generated by a self-oscillating clock generation module based on at least one bank activation signal in each of refresh cycles, upon acquiring a refresh signal;.

In operation S154, a self-oscillating mask signal is generated by a self-oscillating mask module under a preset refresh command; and.

In operation S156, refresh addresses are counted by a refresh address counting module based on the self-oscillating clock signal and the self-oscillating mask signal, and a self-oscillating refresh address is output.

Specific details of the operations in the above refresh address counting method have been described in detail in the corresponding refresh address counting circuit, and thus will not be described herein again.

Also provided in an exemplary embodiment of the present disclosure is a refresh address read-write circuit. With reference to <FIG>. The refresh address read-write circuit includes a latch module <NUM>, a decoding module <NUM>, a reading module <NUM>, and the above refresh address counting circuit <NUM>. An output terminal of the refresh address counting circuit <NUM> is connected to an input terminal of the latch module <NUM>. An output terminal of the latch module <NUM> is connected to an input terminal of the decoding module <NUM>. An output terminal of the decoding module <NUM> is connected to the reading module <NUM>. After being latched by the latch module <NUM>, a self-oscillating refresh address output by the refresh address counting circuit can be decoded by the decoding module <NUM>, and read by the reading module <NUM>. For the decoding module <NUM> and the reading module <NUM>, reference may be made to the existing conventional circuit structures, and the specific structures of the decoding module <NUM> and the reading module <NUM> are not specially defined herein.

In an exemplary embodiment of the present disclosure, the latch module <NUM> includes a multiplexer <NUM> and a latch <NUM>. An input terminal of the multiplexer <NUM> is configured to receive a self-oscillating refresh address OSC_RA and activation address ACT_RA from the refresh address counting circuit <NUM>, and a control terminal of the multiplexer <NUM> is configured to receive a refresh cycle signal REF_1 CYCLE. An output terminal of the multiplexer <NUM> is connected to an input terminal of the latch <NUM>, and an output terminal of the latch <NUM> is connected to the decoding module <NUM>. The multiplexer <NUM> is configured to, under the control of the refresh cycle signal REF_1CYCLE, select and output the activation address ACT_RA before one cycle of refreshing is completed, and to select and output the self-oscillating refresh address OSC_RA after one cycle of refreshing is completed. The address selected and output by the multiplexer <NUM> is latched by the latch <NUM>.

In addition, the specific structural form of the refresh address counting circuit <NUM> has been described in detail in the above embodiment, and thus will not be further described herein.

Also provided in an exemplary embodiment of the present disclosure is an electronic device. The electronic device may include multiple banks and a bank control unit. The bank control unit is provided with the above refresh address counting circuit. The specific structural details of the refresh address counting circuit have been described in detail in the above embodiment, and thus will not be further described herein.

The above embodiment may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by using a software program, the above embodiment may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer commands. When a computer program command is loaded and executed on a computer, the processes or functions according to the embodiments of the present disclosure are generated in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer command may be stored in a computer readable storage medium, or transmitted from a computer readable storage medium to another computer readable storage medium. The computer readable storage medium may be any available medium that a computer can access, or may be a data storage device that includes one or more servers, data centers, and the like, that can be integrated with media. The available media may be magnetic media (e.g., a floppy disk, a hard disk, or a magnetic tape), optical media (e.g., a DVD), semiconductor media (e.g., a solid state disk (SSD)) or the like. In the embodiments of the present disclosure, the computer may include the foregoing devices.

Although the present disclosure is described herein with reference to various embodiments, during implementation of the present disclosure that is set forth, a person skilled in the art may understand and implement other variations of the embodiments of the present disclosure by examining the drawings, the description, and the appended claims. In the claims, the term "comprising" does not exclude other components or steps, and "a" or "an" does not exclude plural scenarios. A single processor or other unit may implement several functions recited in the claims. Certain measures are set forth in dependent claims which are different from each other, but this does not mean that these measures cannot be combined to achieve good effects.

Claim 1:
A refresh address counting circuit for a DRAM, comprising:
a self-oscillating clock generation module (<NUM>), configured to generate a self-oscillating clock signal based on at least one bank activation signal in each of refresh cycles, upon acquiring a refresh signal;
a self-oscillating mask module (<NUM>) configured to generate a mask signal under a preset refresh command; and
a refresh address counting module (<NUM>) configured to count refresh addresses based on the self-oscillating clock signal and the mask signal and to output a self-oscillating refresh address;
characterized in that the preset refresh command comprises a same-bank refresh command, an all-bank refresh command, or a self-refresh command,
wherein the mask signal comprises: a mask sub-signal for masking the self-oscillating clock signal, and a non-mask sub-signal for not masking the self-oscillating clock signal, and
wherein the self-oscillating mask module (<NUM>) comprises an all-bank refresh mask submodule (<NUM>) and a same-bank refresh mask submodule (<NUM>), and wherein
the all-bank refresh mask submodule (<NUM>) is configured to: in response to reception of the all-bank refresh command in a normal refresh mode, generate the mask sub-signal in a normal refresh mode when a lowest bit of a current refresh address is an odd number; and
the same-bank refresh mask submodule (<NUM>) is configured to: in response to reception of the same-bank refresh command, generate the mask sub-signal before all banks are refreshed.