Patent Description:
A HEMT is a field-effect transistor that incorporates a junction between two materials with different band gaps as the channel, rather than a doped region (as is generally the case for a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)). HEMTs have exceptional carrier mobility and provide enhanced switching speed as compared to MOSFETs.

Typical current sensing circuits for solid-state switches may utilize a current sensing resistor or current sensors in a current path for the Field Effect Transistor (FET), with amplifier circuits measuring a differential voltage across the current sensing resistor in order to detect overcurrent conditions at the FET. However, as applications move towards more compact system solutions with increased use of power converters, fault time constraints are becoming shorter. With the limited overcurrent capability of HEMT devices, it is desirable to ensure safe operation of the HEMT device and limit the fault energy in the application by implementing fast fault detection and fault termination, thereby necessitating the use of high-bandwidth current sensing solutions. However, high-bandwidth current sensing solutions increase the cost associated with protection circuits for HEMTs, which is undesirable. <CIT> relates to an IGBT short-circuit overcurrent detecting circuit.

Thus, it is desirable to detect current faults for circuits that utilize HEMTs without resorting to the use of high-bandwidth current sensing solutions, which can increase the cost of the protection circuits.

The invetion is set out in the appended set of claims. In one aspect, an overcurrent fault detector as defined in claim <NUM> is disclosed.

In another aspect, a method of detecting an overcurrent as defined in claim <NUM> is disclosed.

As used herein, the terms "processor" and "computer," and related terms, e.g., "processing device," "computing device," and "controller" are not limited to just those integrated circuits referred to in the art as a computer, but broadly refers to a microcontroller, a microcomputer, an analog computer, a programmable logic controller (PLC), an application specific integrated circuit (ASIC), and other programmable circuits, and these terms are used interchangeably herein. In the embodiments described herein, "memory" may include, but is not limited to, a computer-readable medium, such as a random-access memory (RAM), a computer-readable non-volatile medium, such as a flash memory. Alternatively, a floppy disk, a compact disc - read only memory (CD-ROM), a magneto-optical disk (MOD), and/or a digital versatile disc (DVD) may also be used. Also, in the embodiments described herein, additional input channels may be, but are not limited to, computer peripherals associated with an operator interface such as a touchscreen, a mouse, and a keyboard. Alternatively, other computer peripherals may also be used that may include, for example, but not be limited to, a scanner. Furthermore, in the example embodiment, additional output channels may include, but not be limited to, an operator interface monitor or heads-up display. Some embodiments involve the use of one or more electronic or computing devices. Such devices typically include a processor, processing device, or controller, such as a general purpose central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, a reduced instruction set computer (RISC) processor, an ASIC, a programmable logic controller (PLC), a field programmable gate array (FPGA), a digital signal processing (DSP) device, and/or any other circuit or processing device capable of executing the functions described herein. The methods described herein may be encoded as executable instructions embodied in a computer readable medium, including, without limitation, a storage device and/or a memory device. Such instructions, when executed by a processing device, cause the processing device to perform at least a portion of the methods described herein. The above examples are exemplary only, and thus are not intended to limit in any way the definition and/or meaning of the term processor and processing device.

<FIG> is a block diagram of an overcurrent fault detector <NUM> using a High Electron Mobility Transistor (HEMT) <NUM> operated by a gate driver <NUM> in an example embodiment. In this embodiment, the fault detector <NUM> includes a control circuit <NUM> and a band-pass filter <NUM>. The control circuit <NUM> includes any component, system, or device that implements the functions described herein for the control circuit <NUM>. In this regard, the control circuit <NUM> may include additional logic devices and analog circuits not specifically shown or described herein.

The band-pass filter <NUM> includes any component, system, or device that filters signals. In this embodiment, the band-pass filter <NUM> receives, as an input, gate-to-source voltage (VGS) signals <NUM> representative of a voltage differential between a gate <NUM> of the HEMT <NUM> and a source <NUM> of the HEMT <NUM>, and filters the VGS signals <NUM> to generate band-limited VGS signals <NUM> (e.g., band-limited VGS signals <NUM> are a band-limited version of the VGS signals <NUM>) as an output. In some embodiments, the bandwidth of the band-pass filter <NUM> includes a center frequency from about <NUM> Megahertz (MHz) to about <NUM> and a pass-band frequency from about <NUM> to about <NUM> around the center frequency.

The band-limited VGS signals <NUM> are provided to the control circuit <NUM> for analysis. During an overcurrent fault condition, such as when a current <NUM> supplied to a load <NUM> from a supply <NUM> has a high enough value to cause an overcurrent condition at the HEMT <NUM>, the VGS signals <NUM> from the gate <NUM> of the HEMT <NUM> exhibit a characteristic oscillation. Generally, the characteristic oscillation may have a frequency from about one hundred MHz to about two hundred MHz. The control circuit <NUM> measures a value of this characteristic oscillation generated from the HEMT <NUM> during the overcurrent fault condition, determines if the value exceeds a threshold value, and generates a fault signal <NUM> when the value exceeds the threshold value. The fault signal <NUM> disables the gate driver <NUM> and terminates the overcurrent fault regardless of the logical state of a gate command signal <NUM> applied to the gate driver <NUM>.

In this embodiment, the overcurrent fault detection occurs without current sensors in the current path between the supply <NUM> and the load <NUM> and/or without or other types of inductive current sensing circuits that may be used to determine the current <NUM>, which facilitates the detection of the overcurrent fault conditions without resorting to the use of high-bandwidth current sense circuits, thereby providing a technical benefit in the art.

In this embodiment, the gate driver <NUM> selectively turns the HEMT <NUM> on or off based on the gate command signal <NUM> in order to selectively couple a supply path <NUM> between the supply <NUM> and the load <NUM> and provide the current <NUM> to the load <NUM>. In one embodiment, the HEMT <NUM> is one device of a plurality of devices that operate as part of a solid-state circuit breaker (SSCB) <NUM> between the supply <NUM> and the load <NUM>, and the gate command signal <NUM> may be generated by a controller <NUM> of the SSCB <NUM>. In this embodiment, the supply <NUM> is electrically coupled to the SSCB <NUM> at a line input connector <NUM>, and the load <NUM> is electrically coupled to the SSCB <NUM> at a line output connector <NUM>. Thus, in one embodiment, the supply <NUM> provides Alternating Current (AC) electrical power to the load <NUM>, and the supply path <NUM> is a line conductor. In another embodiment, the supply <NUM> provides Direct Current (DC) electrical power to the load <NUM>, and the supply path <NUM> is a DC power conductor.

In this embodiment, the supply <NUM> and the load <NUM> are electrically coupled via a return path <NUM> for the current <NUM>. The return path <NUM> includes a neutral conductor in embodiments where the supply <NUM> provides AC electrical power to the load <NUM> and a ground conductor in embodiments where the supply <NUM> provides DC electrical power to the load <NUM>. In <FIG>, the current <NUM> is depicted having a particular direction, but the principles described herein for the fault detector <NUM> apply equally to when the current <NUM> is reversed. The current <NUM> is an AC current or a DC current in different embodiments.

In this embodiment, the supply <NUM> is coupled to a drain <NUM> of the HEMT <NUM>, and the load <NUM> is coupled to the source <NUM> of the HEMT <NUM> for purposes of discussion. In this configuration, the drain <NUM> and the source <NUM> selectively form a conduction path between the line input connector <NUM> and the line output connector <NUM>. The HEMT <NUM> depicted in <FIG> may have other configurations in other embodiments. In this embodiment, the HEMT <NUM> is a normally-off device, although the HEMT <NUM> is a normally-on device in other embodiments. In embodiments where the HEMT <NUM> is a normally-off device, the HEMT <NUM> may include an enhancement mode HEMT, a Gate Injection Transistor, or have a "cascode" configuration whereby the HEMT <NUM> is packaged with a normally-off MOSFET to convert a normally-on HEMT to a normally-off HEMT.

HEMTs operate based on the presence of a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) within the device, which forms based on two semiconductors in the HEMT <NUM> that have different band gaps. The presence of the 2DEG or the 2DHG forms a conduction channel <NUM> in the HEMT <NUM> that is bidirectional in this embodiment and facilitates a current flow between the drain <NUM> and the source <NUM> of the HEMT <NUM> (e.g., the conduction channel <NUM> facilitates the current <NUM> flowing between the supply <NUM> and the load <NUM>). The use of two semiconductor materials in the HEMT <NUM> that have different band gaps is referred to as a heterojunction. In some embodiments, the heterojunction for the HEMT <NUM> is formed from gallium nitride (GaN) and aluminum gallium arsenide AlGaAs, although GaN may be combined with other semiconductor materials in other embodiments. Generally, the heterojunction for the HEMT <NUM> may be formed from any two semiconductor materials that have different band gaps. In some embodiments, HEMT <NUM> is a GaN Gate Injection Transistor (GIT) HEMT.

During normal operation, the gate driver <NUM> receives the gate command signal <NUM> (e.g., from the controller <NUM>), and the gate driver <NUM> applies a drive signal <NUM> to the gate <NUM> of the HEMT <NUM> based on the gate command signal <NUM>. For example, if the gate command signal <NUM> directs the gate driver <NUM> to turn the HEMT <NUM> on, then the gate driver <NUM>, in the configuration for the HEMT <NUM> depicted in <FIG>, generates the drive signal <NUM> to bias the gate <NUM> with respect to the source <NUM> above a turn-on voltage for the HEMT <NUM>, which forms the conduction channel <NUM> and electrically couples the supply <NUM> with the load <NUM>. In embodiments where the HEMT <NUM> is a Gate Injection Transistor (GIT) HEMT, then the gate driver <NUM> additionally provides a current to the gate <NUM> of the HEMT <NUM> to maintain the conduction channel <NUM>.

In continuing with the example, if the gate command signal <NUM> directs the gate driver <NUM> to turn the HEMT <NUM> off, then the gate driver <NUM>, in the configuration for the HEMT <NUM> depicted in <FIG>, generates the drive signal <NUM> to bias the gate <NUM> with respect to the source <NUM> below the turn-on voltage for the HEMT <NUM> (and/or terminates the current provided to the gate <NUM> when the HEMT <NUM> is a GIT HEMT), which terminates the conduction channel <NUM> and electrically decouples the supply <NUM> from the load <NUM>, thereby disconnecting the input line connector <NUM> from the line output connector <NUM>.

In an overcurrent fault condition, the magnitude of the current <NUM> can quickly increase due to shorts at the load side of <FIG> (e.g., shorts between the supply path <NUM> and the return path <NUM> at the load <NUM>) or other conditions, which are quickly detected by the fault detector <NUM> by sensing a characteristic oscillation at the gate <NUM> of the HEMT <NUM> and terminating the fault condition using the fault signal <NUM> applied to the gate driver <NUM>. This will be discussed in more detail below.

In <FIG>, the overcurrent fault detection is a sensor-less design, as the characteristic oscillation present at the gate <NUM> of the HEMT <NUM> during overcurrent fault conditions is detectable without the use of additional current sensors or inductive circuits for measuring the current <NUM>. In this embodiment, the fault detector <NUM> operates to detect and terminate the overcurrent fault condition within a few microseconds, thereby mitigating the overcurrent fault condition quickly. This type of response time is difficult to achieve in typical current sense circuits without resorting to the use of high-bandwidth devices, which would increase the cost associated with detecting and mitigating the overcurrent fault conditions.

<FIG> is a block diagram of the fault detector <NUM> in another example embodiment. In this embodiment, the control circuit <NUM> includes a series of devices that form an overcurrent fault detection and control path for the control circuit <NUM>. The overcurrent fault detection and control path receives the band-limited VGS signals <NUM> from the band-pass filter <NUM> and generates the fault signal <NUM> when appropriate. In this embodiment, the overcurrent fault detection and control path for the control circuit <NUM> include a rectifier <NUM>, an integrator <NUM>, a comparator <NUM>, and a latch <NUM>. The rectifier <NUM> includes any component, system, or device that receives the band-limited VGS signals <NUM> from the output of the band-pass filter <NUM> and generates DC signals <NUM> at its output for the integrator <NUM>. Generally, the output of the band-pass filter <NUM> is an AC signal (e.g., a bidirectional signal) and the rectifier <NUM> converts the bidirectional signal from the band-pass filter <NUM> to unidirectional signals. The integrator <NUM> includes any component, system, or device that receives the DC signals <NUM> from the output of the rectifier <NUM> and integrates the DC signals <NUM> over a time frame to generate an integrated output signal <NUM>. For example, the DC signals <NUM> may include a half-wave rectified output from the band-pass filter <NUM> with a zero-volt DC offset, and the integrator <NUM> performs an integration process over the time frame to generate the integrated output signal <NUM>. In some embodiments, the time frame is controlled or reset by a reset signal <NUM> that is selectively applied to the control circuit <NUM> (e.g., via the controller <NUM>). The time frame may also be referred to as an integration time in some embodiments.

In this embodiment, the comparator <NUM> of the control circuit <NUM> includes any component, system, or device that receives the integrated output signal <NUM> from the integrator <NUM> and generates a logic signal <NUM> based the difference between the integrated output signal <NUM> and a reference voltage <NUM>. For example, if the integrated output signal <NUM> is greater than the reference voltage <NUM>, then the comparator <NUM>, in one embodiment, generates the logic signal <NUM> to have a logic high value. In continuing with the example, in this embodiment, if the integrated output signal <NUM> has a magnitude that is less than the reference voltage <NUM>, then the comparator <NUM> generates the logic signal <NUM> to have a logic low value.

The logic signal <NUM> is applied to the latch <NUM> in this embodiment. The latch <NUM> of the control circuit <NUM> includes any component, system, or device that receives the logic signal <NUM> from the comparator <NUM> and generates the fault signal <NUM> based on the logic signal <NUM>. In this embodiment, the fault signal <NUM> continues to be asserted by the latch <NUM> until the reset signal <NUM> is received by the control circuit <NUM> (e.g., from the controller <NUM>). This allows the controller <NUM> or another device to perform a fault recovery process before clearing the latch <NUM> with the reset signal <NUM>, which clears an asserted state of the fault signal <NUM>.

<FIG> is a flow chart of a method <NUM> of detecting an overcurrent fault condition using a HEMT operated by a gate driver in an example embodiment, and <FIG> depicts additional details of the method <NUM> in an example embodiment. The method <NUM> will be discussed with respect to the fault detector <NUM> depicted in <FIG> and <FIG>, but the method <NUM> may apply to other systems not specifically shown or described herein. The steps of the method <NUM> are not all inclusive, and the method <NUM> may include other steps different from those shown or described herein. Further, the steps of the method <NUM> may be performed in a different order.

Consider that SSCB <NUM> (see <FIG>) is installed at a premise location, that the SSCB <NUM> is operating as a solid-state circuit breaker between the supply <NUM> and the load <NUM>, and that the supply <NUM> is currently providing a non-zero current <NUM> for the load <NUM>. The load <NUM> may be, for example, a household appliance. The gate <NUM> of the HEMT <NUM> generates VGS signals <NUM>, which are received by the band-pass filter <NUM> of the fault detector <NUM> (see <NUM>). Generally, the VGS signals <NUM> from the HEMT <NUM> will have an AC signal component of about zero when no overcurrent fault condition is present and will have a characteristic oscillation (e.g., between about <NUM> and <NUM>, depending on the device characteristics of the HEMT <NUM>) when an overcurrent fault condition is present.

The VGS signals <NUM> received by the fault detector <NUM> from the HEMT <NUM> are band-limited to suppress signals outside of the characteristic oscillation frequency of the HEMT <NUM>, and the band-limited VGS signals <NUM> from the output of the band-pass filter <NUM> are applied to the control circuit <NUM> for analysis (see <NUM>). The control circuit <NUM> measures a value of the band-limited VGS signals <NUM> (see <NUM>) and determines if the value is greater than a threshold value (see <NUM>). In some cases, the value is less than the threshold value, and processing returns to block <NUM>. For example, the value is less than the threshold value when the characteristic AC signal at the gate <NUM> of the HEMT <NUM> is not present, which indicates that no overcurrent fault condition is present.

In some cases, the values of the band-limited VGS signals <NUM> measured by the control circuit <NUM> are greater than the threshold value. For example, during an overcurrent fault at the load <NUM>, the magnitude of the current <NUM> quickly reaches a high level, which may cause the junction temperature in the HEMT <NUM> to quickly rise and exceed its thermal design specification due to the magnitude of the current <NUM> flowing through the conduction channel <NUM> of the HEMT <NUM>. The differential voltage across the gate <NUM> and the source <NUM> begins oscillating at a characteristic frequency (e.g., a frequency from about <NUM> to about <NUM>) in response to the thermal overload, which is reflected in the VGS signals <NUM> at the gate <NUM> and applied to the band-pass filter <NUM>. In this overcurrent fault condition, the value measured by the control circuit <NUM> is greater than the threshold value, and the control circuit <NUM> generates the fault signal <NUM> to disable the gate driver <NUM> at the HEMT <NUM> (see <NUM>). The fault signal <NUM> overrides the gate command signal <NUM> for the gate driver <NUM>, and the gate driver <NUM> turns off the HEMT <NUM> and terminates the overcurrent fault condition.

Referring to <FIG> and <FIG>, when the HEMT <NUM> is operating normally, the gate driver <NUM> receives the gate command signal <NUM> (e.g., from the controller <NUM>) and applies the drive signal <NUM> to the gate <NUM> of the HEMT <NUM> to turn the HEMT <NUM> on, and the current <NUM> flows between the supply <NUM> and the load <NUM> through the conduction channel <NUM> of the HEMT <NUM>. The band-pass filter <NUM> of the fault detector <NUM> receives the VGS signals <NUM> from the gate <NUM> of the HEMT (see <NUM>, previously described).

If the current <NUM> rises quickly due to a overcurrent fault condition, the VGS signals <NUM> from the gate <NUM> begin to oscillate at a characteristic frequency (e.g., an AC signal having a frequency of about <NUM> +/- about <NUM>), which is band-limited by the band-pass filter <NUM> (see <NUM> of <FIG>, previously described). The band-limited VGS signals <NUM> are applied to the rectifier <NUM> of the control circuit <NUM>. The rectifier <NUM>, upon receiving the band-limited VGS signals <NUM> at its input from the band-pass filter <NUM>, generates the DC signals <NUM> at its output (see <NUM> of <FIG>). The DC signals <NUM> may include, for example, a half-wave rectified output of the band-limited VGS signals <NUM>, having a DC offset about zero. The integrator <NUM> integrates the DC signals <NUM> (see <NUM>) and applies its integrated output signal <NUM> to the comparator <NUM>. The comparator <NUM> performs a comparison of the integrated output signal <NUM> with the threshold value represented by the reference voltage <NUM> and generates the logic signal <NUM> for the latch <NUM> based on the comparison. If for example, the integrated output signal <NUM> is greater than the reference voltage <NUM>, then the logic signal <NUM> generated by the comparator <NUM> causes the latch <NUM> to generate and latch the fault signal <NUM> (see <NUM>), which is applied to the gate driver <NUM>. The fault signal <NUM> overrides the gate command signal <NUM> at the gate driver <NUM>, causing the gate driver <NUM> to turn off the HEMT <NUM> and terminate the overcurrent fault condition. The fault signal <NUM> is latched by the latch <NUM> and continues to assert the fault signal <NUM> until the reset signal <NUM> is applied to the latch <NUM> (e.g. by the controller <NUM>, see <NUM>), which resets the integration time frame for the integrator <NUM> and clears the latch <NUM>. Clearing the latch <NUM> terminates the fault signal <NUM> (see <NUM>), allowing the control circuit <NUM> to perform another analysis based on the VGS signals <NUM> from the gate <NUM> of the HEMT <NUM> to determine if the overcurrent fault condition is still present.

<FIG> is a circuit diagram of an overcurrent fault detector <NUM> for an SSCB <NUM> in an example embodiment, and <FIG> is a timing diagram <NUM> for signals at the SSCB <NUM> in an example embodiment. In <FIG>, a region <NUM> of the timing diagram <NUM> is expanded for clarity. Referring to <FIG>, the SSCB <NUM> in this embodiment includes a line input connector <NUM> that couples to a line conductor for an AC power supply and a line output connector <NUM> that couples to a line conductor for an AC load. For example, the SSCB <NUM> may be located in an electrical panel at a premise location, with the line input connector <NUM> for the SSCB <NUM> electrically coupled to an electrical utility line supply (L) in the electrical panel and the line output connector <NUM> for the SSCB <NUM> electrically coupled to a line conductor for an appliance at the premise location. The neutral return is not shown in <FIG>.

In this embodiment, the SSCB <NUM> includes one or more HEMTs <NUM> that selectively couple the line input connector <NUM> to the line output connector <NUM> based on a gate drive signal <NUM> generated by a gate driver <NUM>. The gate drive signal <NUM> is generated by the gate driver <NUM> based on a VGS command signal <NUM>, which is an interlocked signal generated by a logic gate <NUM>. When a command signal <NUM> has a high logic level and a fault signal <NUM> from the detector <NUM> has a low logic level, then the VGS command signal <NUM> and the command signal <NUM> have the same logic level (e.g., the command signal <NUM> controls the on/off state of the HEMT <NUM> and the VGS command signal <NUM> logically corresponds to the command signal <NUM>). However, when the fault signal <NUM> has a high logic level (e.g., in response to an overcurrent fault condition at the HEMT <NUM>), then the VGS command signal <NUM> has a low logic level regardless of the logic level of the command signal <NUM>, which commands the gate driver <NUM> to turn off the HEMT <NUM>.

In this embodiment, the gate drive signal <NUM> generated by the gate driver <NUM> is applied to a gate <NUM> of the HEMT <NUM>, which allows a drain current <NUM> to flow between a drain <NUM> of the HEMT <NUM> and a source <NUM> of the HEMT <NUM>. A drain-to-source voltage (VDS) <NUM> is a voltage between the drain <NUM> and the source <NUM> of the HEMT <NUM>.

In this embodiment, the fault detector <NUM> includes a digital isolator <NUM>, which electrically isolates the fault detector <NUM> from circuits in the SSCB <NUM>. During operation of the fault detector <NUM>, the differential voltage between the gate <NUM> and the source <NUM> of the HEMT <NUM>, referred to as VGS signals <NUM>, is applied to a signal and control path that includes a band-pass filter <NUM>, a rectifier <NUM>, an integrator <NUM>, a comparator <NUM>, and a latch <NUM>, each of which may operate the same or similarly to the band-pass filter <NUM>, the rectifier <NUM>, the integrator <NUM>, the comparator <NUM>, and the latch <NUM>, respectively, as previously described for <FIG>. In this embodiment, the output of the comparator <NUM> generates an interrupt signal <NUM> that is applied to an AND gate <NUM>, and the AND gate forwards the interrupt signal <NUM> to the latch <NUM> as long as the VGS command signal <NUM> applied to the gate driver <NUM> has a high logic value (e.g., the AND gate forms an interlock for the interrupt signal <NUM> in this embodiment). The latch <NUM> in this embodiment latches the fault signal <NUM> logic level high when the VGS command signal <NUM> is high and the interrupt signal <NUM> generated by the comparator <NUM> is also logic level high. The output of the comparator <NUM> is logic level high in <FIG> when the output value of the integrator <NUM> applied to the comparator <NUM> is greater than the reference voltage <NUM> (e.g., a threshold value) applied to the comparator <NUM>. In this embodiment, a reset signal <NUM> (e.g., applied by a controller <NUM>) resets the integration time window for the integrator <NUM>, and also clears the latch <NUM>. Clearing the latch <NUM> resets the fault signal <NUM> logic level low.

With reference to <FIG> and <FIG>, consider that a line conductor downstream of the SSCB <NUM> is shorted to neutral, that the reset signal <NUM> is logic low, and that the fault signal <NUM> is also logic low. When the command signal <NUM> is set logic high at time(t<NUM>) <NUM>, the VGS command signal <NUM> also goes logic high, because the fault signal <NUM> is currently logic low. The gate driver <NUM> turns on the HEMT <NUM> in response to the VGS command signal <NUM> being logic high. The drain current <NUM> through the HEMT <NUM> rises to a high value due to the short, generating an overcurrent condition at the HEMT <NUM>. The VDS <NUM> of the HEMT <NUM> has a low value at this point in time.

At time(t<NUM>) <NUM>, the HEMT <NUM> has reached its overcurrent duration limit (e.g., based on the junction temperature at the HEMT <NUM>) and the HEMT <NUM> saturates. In this embodiment, the VDS starts to rise, which is a characteristic of some types of HEMT devices during overcurrent conditions. At time(t<NUM>) <NUM>, the drain current <NUM> begins to fall and the voltage at the gate <NUM> of the HEMT <NUM> starts to oscillate, generating an AC component for the VGS signal <NUM> at a characteristic frequency (e.g., the VGS signal <NUM> oscillates at a frequency from about <NUM> to about <NUM>), which is band-limited by the band-pass filter <NUM>, and is rectified by the rectifier <NUM>. The integrator <NUM> integrates the output of the rectifier <NUM>, and the result is compared to the reference voltage <NUM> at the comparator <NUM>. In this example, the VGS signal <NUM> is oscillating as depicted in <FIG>, and therefore, the integrator <NUM> outputs a value that is greater than the reference voltage <NUM> at the comparator <NUM>. The result is that the comparator <NUM> sets the interrupt signal <NUM> logically high at time(t<NUM>) <NUM>, which is passed by the AND gate <NUM> to the latch <NUM> (e.g., the reset signal <NUM> is low during analysis). The latch <NUM> generates and latches the fault signal <NUM> high based on the high logic level of the interrupt signal <NUM>, which is applied to the logic gate <NUM> that controls whether the command signal <NUM> is applied to the gate driver <NUM>. The high logic level of the fault signal <NUM> at the logic gate <NUM> overrides the command signal <NUM>, and the VGS command signal <NUM> goes low, commanding the gate driver <NUM> to turn off the HEMT <NUM> at time(t<NUM>) <NUM> and terminate the overcurrent fault condition. The fault signal <NUM> may also be applied to the controller <NUM>, which may terminate the command signal <NUM> in response to the overcurrent fault and perform a post-fault recovery process. The post-fault recovery process may include generating the reset signal <NUM> to reset the integration time window for the integrator <NUM> and reset the latch <NUM>. Resetting the latch <NUM> clears the fault signal <NUM> and enables the controller <NUM> to re-enable normal operation for sensing overcurrent fault conditions at the HEMT <NUM>.

Claim 1:
An overcurrent fault detector (<NUM>, <NUM>) using a High Electron Mobility Transistor, HEMT, (<NUM>, <NUM>) operated by a gate driver (<NUM>, <NUM>), the overcurrent fault detector (<NUM>, <NUM>) comprising:
a band-pass filter (<NUM>, <NUM>) configured to:
receive gate-to-source voltage (VGS) signals (<NUM>, <NUM>) of the HEMT (<NUM>, <NUM>), wherein the HEMT generates an oscillation in the VGS signals at a characteristic frequency in response to a thermal overload at HEMT during an overcurrent fault condition; and
filter the VGS signals (<NUM>, <NUM>) to generate a band-limited version (<NUM>) of the VGS signals (<NUM>, <NUM>) that suppresses signals outside of the characteristic frequency; and
a control circuit (<NUM>) configured to:
measure a value of the band-limited version (<NUM>) of the VGS signals (<NUM>, <NUM>);
determine if the value is greater than a threshold value (<NUM>); and
generate a fault signal (<NUM>, <NUM>) that disables the gate driver (<NUM>, <NUM>) and terminates the overcurrent fault condition in response to determining that the value is greater than the threshold value (<NUM>).