Patent Description:
Ways to improve efficiency of power/energy conversion systems are continually being sought. For example, switch-mode power supply (SMPS) applications. The SMPS topology is gaining wider acceptance because of its high efficiency, small size and light weight. However, as the size of an SMPS is decreased, heat dissipation/removal therefrom becomes more problematic. Even though the typical efficiency of an SMPS may be <NUM> percent, there still remains <NUM> percent of the energy used by the SMPS becoming wasted heat. In addition, the high efficiency of the SMPS is optimized for only a single load condition. However, in real world applications power utilization loads vary over a wide range, and so do the associated SMPS efficiencies at those loads. Therefore, any further improvements in SMPS efficiency will result in even smaller and more cost effective solutions in addition to more energy savings. The size, weight and power savings have significant value. In addition, it is desirable to determine the health of an SMPS system, adjust operating parameters for maximum efficiency, and be able to predict a potential system failure.

<CIT> discloses a control system optimization via independent parameter adjustment. <CIT> discloses a semiconductor device including a digital control circuit configured to supply two semiconductor switching elements connected in series in a switching power supply circuit with a pulse signal.

<CIT> discloses a power converter device with a digital controller and a method to optimize the efficiency of its operation by means of minimizing the PWM duty cycle of a primary side switching device. This is done by observing said primary side duty cycle which is established by output feedback control and manipulating switching signals of secondary side synchronous rectifier switches, which in turn influence the efficiency of the energy conversion and thus indirectly the duty cycle of the primary side switch representing said efficiency (column <NUM>, line <NUM> - column <NUM>, line <NUM>; <FIG>).

Therefore a need exists for a power/energy conversion switch-mode power supply (SMPS) that is capable of improved efficiencies in a smaller, simpler system solution. This and other objects can be achieved by an SMPS and method of operating such as defined in the independent claims. Further enhancements are characterized in the dependent claims.

According to one aspect of the invention, a switch-mode power supply (SMPS) is provided, comprising: at least one power switch coupled to a voltage source; a power inductor coupled to the at least one power switch; a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage output of the SMPS; at least one driver coupled to the at least one power switch; a pulse width modulation (PWM) generator having at least one output coupled to and controlling the at least one driver, the at least one output of the PWM generator providing at least one PWM signal comprising a plurality of pulses; and a digital processor having a memory, the digital processor is coupled to and provides operating parameters to the PWM generator during operation thereof.

The switch-mode power supply according to the present aspect is characterized by:.

In an embodiment, averaging the PWM control signal and periodically taking samples of the averaged PWM control signal is conducted in determining relative efficiency of the SMPS system and best practices in maintaining the maximum efficiency thereof over all load conditions. Also by knowing the PWM control signal averages during operation thereof, a baseline can be established so that the health and potential system failures may be determined and monitored.

According to a further embodiment, the highest relative efficiency is when the analog signal representative of the relative efficiency is at a lowest value. According to a further embodiment, the ramp signal may represent current values of the power inductor. According to a further embodiment, the ramp signal may represent a generated voltage ramp. According to a further embodiment, the digital processor may use the stored digital efficiency values to adjust the operating parameters of the PWM generator to provide the PWM signal resulting in optimum relative efficiency of the SMPS. According to a further embodiment, the operating parameters of the PWM generator can be selected from any one or more of the group consisting of on and off percents of the at least one power switch, drive current from the at least one driver to the at least one power switch, and PWM pulse rate per second (frequency). According to a further embodiment, the at least one power switch can be at least one power transistor. According to a further embodiment, the at least one power transistor can be at least one power metal oxide semiconductor (MOS) field effect transistor (FET). According to a further embodiment, the PWM averaging filter can be coupled to the at least one driver for receiving the PWM signal. According to a further embodiment, the PWM averaging filter can be an analog low-pass filter. According to a further embodiment, the analog low-pass filter can be a resistor-capacitor low-pass filter. According to a further embodiment, the SMPS may further comprise a communications interface coupled to the digital processor. According to a further embodiment, the digital processor and memory can be a microcontroller.

According to another aspect of the invention, a method for optimizing efficiency of a switch-mode power supply (SMPS), comprises the steps of:.

According to an embodiment of the method, the operating parameters of the PWM generator can be selected from any one or more of the group consisting of percent on of the pulses of the PWM signal, drive current to a power switch, and PWM pulse rate per second (frequency).

According to yet another embodiment, the step of determining comprises determining an average of on pulses of a first PWM signal from a PWM generator with a first PWM averaging filter; wherein the step of driving comprises driving a first power switch of a SMPS with the first PWM signal, and driving a second power switch of the SMPS with a second PWM signal; and the step of adjusting comprises adjusting operating parameters of the PWM generator to minimize the average of the on pulses of the first PWM signal and thereby increase efficiency of a SMPS.

According to a further embodiment of the method, the operating parameters of the PWM generator can be selected from any one or more of the group consisting of percent on times of the pulses of the PWM signal, drive current to the first power switch, drive current to the second power switch, off times between on times of the first and second power switches, and PWM pulse rate per second (frequency). According to a further embodiment of the method, the method may further comprise the steps of: determining an average of on pulses of the second PWM signal from the PWM generator with a second PWM averaging filter; and adjusting operating parameters of the PWM generator to minimize the average of the on pulses of the second PWM signal and thereby increase efficiency of the SMPS.

According to yet another embodiment, a method for optimizing operation of a switch-mode power supply (SMPS), may comprise the steps of: providing at least one power switch coupled to a voltage source; providing a power inductor coupled to the at least one power switch; providing a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage from the SMPS; and providing a SMPS controller, wherein operating the SMPS controller comprises the steps of: driving the at least one power switch with an associated at least one driver, controlling the at least one driver with a pulse width modulation (PWM) signal from a PWM generator, comparing the regulated voltage from the SMPS to a reference voltage with a voltage comparison circuit, generating a voltage error signal representative of a difference between the regulated voltage and the reference voltage with the voltage comparison circuit, coupling the voltage error signal to the PWM generator, determining an average of on pulses of the PWM signal with a PWM averaging filter; and adjusting operating parameters of the PWM generator to minimize the average of the on pulses of the PWM signal and thereby increase efficiency of the SMPS.

According to a further embodiment of the method, the operating parameters of the PWM generator are selected from any one or more of the group consisting of percent on of the pulses of the PWM signal, drive current to the at least one power switch, and PWM pulse rate per second (frequency).

According to yet another embodiment, a method for optimizing operation of a switch-mode power supply (SMPS) may comprise the steps of: providing a first power switch coupled to a voltage source; providing a second power switch coupled between the first power switch and a voltage source return; providing a power inductor coupled to the first and second power switches; providing a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage from the SMPS; and providing a SMPS controller, wherein operating the SMPS controller comprises the steps of: driving the first power switch with a first driver, driving the second power switch with a second driver, controlling the first and second drivers with first and second pulse width modulation (PWM) signals, respectively, from a PWM generator, comparing the regulated voltage from the SMPS to a reference voltage with a voltage comparison circuit, generating a voltage error signal representative of a difference between the regulated voltage and the reference voltage with the voltage comparison circuit, coupling the voltage error signal to the PWM generator, determining an average of on pulses of the first PWM signal with a first PWM averaging filter; and adjusting operating parameters of the PWM generator to minimize the average of the on pulses of the first PWM signal and thereby increase efficiency of the SMPS.

According to a further embodiment of the method, the operating parameters of the PWM generator can be selected from any one or more of the group consisting of percent on times of the pulses of the first and second PWM signals, drive currents to the first and second power switches, off times between on times of the first and second power switches, and PWM pulse rate per second (frequency). According to a further embodiment of the method, the method may further comprise the steps of: determining an average of on pulses of the second PWM signal from the PWM generator with a second PWM averaging filter; and adjusting operating parameters of the PWM generator to minimize the average of the on pulses of the second PWM signal and thereby increase efficiency of the SMPS.

A more complete understanding of the present disclosure thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:.

While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.

A pulse width modulation (PWM) power conversion system has improved efficiency over a wide operating input voltage and load range. Being able to measure relative efficiency of an analog PWM system allows enhanced control while maintaining the benefits of analog control. An analog low pass filter produces an average value of the PWM pulse train, then this analog average value is converted into digital values with an analog-to-digital converter and stored so that relative efficiencies of the PWM power conversion system may be compared for various combinations of operating parameters.

According to the teachings of this disclosure, a low pass, e.g., resistor-capacitor (RC), filter may be used to average the PWM control signal used in a SMPS system. An analog-to-digital converter (ADC) may convert the analog output of the low pass filter to digital values that may be stored in a digital format. PWM system parameters can be adjusted (e.g., fine tuned) while the digitally stored relative efficiency values are checked for each parameter change, and/or combinations thereof. Efficiency reference points may be set so as to be able to identify SMPS system component potential malfunction and reliability issues. It is contemplated and within the scope of this disclosure that any power/energy conversion systems utilizing PWM control would benefit from averaging the PWM control signal for determining system efficiencies during operation thereof and any changes in operating parameters thereto.

According to a specific example embodiment of this disclosure, a switch-mode power supply (SMPS) comprises: at least one power switch coupled to a voltage source; a power inductor coupled to the at least one power switch; a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage output of the SMPS; at least one driver coupled to the at least one power switch; a pulse width modulation (PWM) generator having at least one output coupled to and controlling the at least one driver, the at least one output of the PWM generator providing at least one PWM signal comprising a plurality of pulses; a digital processor having a memory, the digital processor is coupled to and provides operating parameters to the PWM generator during operation thereof; a voltage comparison circuit for comparing the regulated output voltage to a reference voltage, wherein the voltage comparison circuit has an error signal output representative of a difference between the regulated output voltage and the reference voltage; a comparator having a first input coupled to the error signal output from the voltage comparison circuit, a second input coupled to a ramp signal, and an output coupled to an input of the PWM generator; an PWM averaging filter, wherein the PWM averaging filter receives the PWM signal and produces an analog signal representative of a relative efficiency thereof; and an analog-to-digital converter (ADC) having an analog input coupled to the analog signal representative of the relative efficiency of the PWM signal, and a digital output coupled to the digital processor having a memory; wherein the digital processor optimizes operation of the SMPS by adjusting operating parameters of the PWM generator to provide the at least one PWM signal that produces a highest relative efficiency of the SMPS.

According to another specific example embodiment of this disclosure, a switch-mode power supply (SMPS) comprises: a first power switch coupled to a voltage source; a second power switch coupled to a voltage source return; a power inductor coupled to the first and second power switches; a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage output of the SMPS; a first driver coupled to the first power switch; a second driver coupled to the second power switch; a pulse width modulation (PWM) generator having first and second outputs coupled to and controlling the first and second drivers, respectively, the first and second outputs of the PWM generator providing first and second PWM signals, each comprising a plurality of pulses; a digital processor having a memory, the digital processor is coupled to and provides operating parameters to the PWM generator during operation thereof; a voltage comparison circuit for comparing the regulated output voltage to a reference voltage, wherein the voltage comparison circuit has an error signal output representative of a difference between the regulated output voltage and the reference voltage; a comparator having a first input coupled to the error signal output from the voltage comparison circuit, a second input coupled to a ramp signal, and an output coupled to an input of the PWM generator; a first PWM averaging filter, the first PWM averaging filter receives the first PWM signal and produces a first analog signal representative of a relative efficiency thereof; and an analog-to-digital converter (ADC) having an analog input coupled to the first analog signal representative of the relative efficiency of the first PWM signal, and a digital output coupled to the digital processor having a memory; wherein the digital processor optimizes operation of the SMPS by adjusting operating parameters of the PWM generator to provide the first and second PWM signals that produce a highest relative efficiency of the SMPS.

According to yet another specific example embodiment of this disclosure, a method for optimizing efficiency of a switch-mode power supply (SMPS), said method comprising the steps of: determining an average of on pulses of a PWM signal with a PWM averaging filter; and adjusting operating parameters of a PWM generator to minimize the average of the on pulses of the PWM signal and thereby increase efficiency of the SMPS. Wherein the operating parameters of the PWM generator are selected from any one or more of the group consisting of percent on of the pulses of the PWM signal, drive current to a power switch, and PWM pulse rate per second (frequency).

Referring now to the drawing, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

In a general sense, a power converter can be defined as a device which converts one form of energy into another on a continuous basis. Any storage or loss of energy within such a power system while it is performing its conversion function is usually identical to the process of energy translation. There are many types of devices which can provide such a function with varying degrees of cost, reliability, complexity, and efficiency.

The mechanisms for power conversion can take many basic forms, such as those which are mechanical, electrical, or chemical processing in nature. The focus herein will be on power converters which perform energy translation electrically and in a dynamic fashion, employing a restricted set of components which include inductors, capacitors, transformers, switches and resistors. How these circuit components are connected is determined by the desired power translation. Resistors introduce undesirable power loss. Since high efficiency is usually an overriding requirement in most applications, resistive circuit elements should be avoided or minimized in a main power control path. Only on rare occasions and for very specific reasons are power consuming resistances introduced into the main power control path. In auxiliary circuits, such as sequence, monitor, and control electronics of total system, high value resistors are commonplace, since their loss contributions are usually insignificant.

Referring to <FIG>, depicted is a schematic block diagram of a basic voltage regulator system. A power system <NUM>, e.g., a basic switch-mode power converter where an input of an uncontrolled source of voltage (or current, or power) is applied to the input of the power system <NUM> with the expectation that the voltage (or current, or power) at the output will be very well controlled. The basis of controlling the output is to compare it to some form of reference, and any deviation between the output and the reference becomes an error. In a feedback-controlled system, negative feedback is used to reduce this error to an acceptable value, as close to zero as is required by the system. It is desirable, typically, to reduce the error quickly, but inherent with feedback control is the trade-off between system response and system stability. The more responsive the feedback network is, the greater becomes the risk of instability.

At this point, it should be mentioned that there is another method of control - feed forward. With feed forward control, a control signal is developed directly in response to an input variation or perturbation. Feed forward is less accurate than feedback since output sensing is not involved, however, there is no delay waiting for an output error signal to be developed, and feed forward control cannot cause instability. It should be clear that feed forward control typically is not adequate as the only control method for a voltage regulator, but it is often used together with feedback to improve a regulator's response to dynamic input variations.

Referring to <FIG>, depicted is a more detailed schematic block diagram of the voltage regulator system shown in <FIG>. The power system <NUM> has been separated into two blocks: the power circuit <NUM> and the control circuit <NUM>. The power circuit <NUM> handles the power system load current and is typically large, robust, and subject to wide temperature fluctuations. Its switching functions are by definition, large-signal phenomenon, normally simulated in most stability analyses as just a two-state switch with a duty cycle. The output filter (not shown) is also considered as a part of the power circuit <NUM>, but can be considered as a linear block. The control circuit <NUM> will normally be made up of a gain block, an error amplifier, and a pulse-width modulator, used to define the duty cycle for the power switches. According to the teachings of this disclosure, the control circuit <NUM> is optimized to respond to disturbances in the power system <NUM> while maintaining a desired output voltage, VOUT.

Referring to <FIG>, depicted is a schematic diagram of the circuits shown in <FIG> implemented as a switch-mode power supply (SMPS), according to a specific example embodiment of this disclosure. The power circuit <NUM> of the SMPS may receive power from a power source <NUM>, e.g., battery, and may comprise a power inductor <NUM>, high and low switches <NUM> and <NUM>, respectively, e.g., power field effect transistors; a load capacitor <NUM> for smoothing alternating current (AC) ripple from the desired direct current (DC) output, and a boot voltage capacitor <NUM>. The power circuit <NUM> is connected to and is controlled by the control circuit <NUM> as shown in <FIG> and more fully described hereinafter.

The SMPS shown in <FIG> may be for example, but not limited to, a voltage mode or current mode analog pulse width modulated (PWM) voltage conversion system. An outer voltage loop is regulated using an amplifier <NUM> and a comparator <NUM>. An output D of the PWM generator and drivers <NUM> is adjusted by comparing the output of the amplifier <NUM> with the inductor <NUM> ramp current or a generated ramp voltage depending upon the control method chosen. In either case, the value of the PWM output (D) is a relative measure of the SMPS system efficiency. The higher the PWM output (D) average is the lower the efficiency (i.e., the PWM output (D) on time increases and the off time decreases), and the lower the PWM output (D) is the higher the efficiency (i.e., the PWM output (D) on time decreases and the off time increases). This is reflected in and is advantageous for the switching frequency of the SMPS converter to be lowered in frequency, i.e., less switch transitions per second, whereby the inductor <NUM> maintains a desired current charge with less power transistor switching losses.

For example, if the SMPS converter is stepping down a +<NUM> VDC input to a +<NUM> VDC output when the value at the output D is <NUM>% at a switching frequency of <NUM>, compared to the output D of <NUM>% at a switching frequency of <NUM>, the SMPS system efficiency has improved. The PWM output D (HDR) may be averaged using an analog low pass filter, e.g., resistor-capacitor filter, then measured and stored, e.g., with an analog-to-digital converter (ADC) and a digital memory. The stored average efficiency values may then be compared with a digital processor, e.g., microcontroller, capable of determining relative system efficiencies for different combinations of operating parameters. Other system level adjustments that may be beneficial and advantageous may be, for example but are not limited to, delay time between the on times of the upper and lower switches <NUM> and <NUM>, and drive strength to the gates thereof (not as much current drive is required when the current through the switches <NUM> and <NUM> is lower, all though the switches <NUM> and <NUM>, e.g., power FETs, are either off or saturated on. It is contemplated and within the scope of this disclosure that the PWM output /D (LDR) may also be averaged using an analog low pass filter, e.g., resistor-capacitor filter, then measured and stored, e.g., with the analog-to-digital converter (ADC) and the digital memory. Having on times as percentages of both PWM outputs D (HDR) and /D (LDR) will further enable operational profiling for efficiency, optimal "dead time," etc. Thus, digital techniques may be used to enhance an analog control system in a simple and cost effective manner. Full digital loop control for determining relative efficiency would require a larger digital circuit size and power drawn, slower transient response and higher quiescent current.

Referring to <FIG>, depicted is a more detailed schematic block diagram of the control circuit shown in <FIG>, according to the specific example embodiment of this disclosure. The control circuit <NUM> is connected to the power circuit <NUM> shown in <FIG> and comprises a digital processor with memory <NUM>, e.g., microcontroller; high and low switch drivers having deadband logic represented by function block <NUM>, bias generator, current and voltage reference circuits <NUM>; under and over voltage detectors <NUM>, a PWM generator <NUM>, an over current detector <NUM>, a voltage comparison circuit <NUM>, a power inductor current measurement circuit <NUM>, an PWM output control averaging circuit(s) <NUM>, an analog-to-digital converter (ADC) <NUM> and, optionally, a communications interface <NUM>.

The high and low switch drivers of the function block <NUM> are coupled to and control when the high and low switches <NUM> and <NUM> turn on and off. In addition the deadband logic of the function block <NUM> prevents the high and low switches <NUM> and <NUM> from ever being on at the same time, preferably, there is a deadband where both of the high and low switches <NUM> and <NUM> are off. The PWM generator <NUM> controls when and for how long the power inductor <NUM> is coupled to and is being charged from the power source <NUM>.

The boot voltage capacitor <NUM> supplies power to the bias generator, current and voltage reference circuits <NUM> which in turn supply precision current and voltage reference values that are used by the current and voltage circuits <NUM>, <NUM> and <NUM>. The voltage comparison circuit <NUM> measures the output voltage and compares it to a reference voltage, VREF, from the voltage reference circuit <NUM>. An error signal from the voltage comparison circuit <NUM>, representing the difference between a desired voltage value and the actual output voltage value, is applied to an error input of the PWM generator <NUM>, wherein the PWM generator <NUM> adjusts its pulse waveform output to minimize that difference (closed loop feedback, see <FIG>). The over current detector <NUM> monitors the current to the power inductor <NUM>, and the under and over voltage detectors <NUM> monitor the input voltage to the SMPS for undesirable e.g., abnormal, conditions, e.g., inductor current exceeds allowable design limits, input voltage is above or below a design operating input voltage range. The power inductor current measurement circuit <NUM> measures SMPS power inductor current. It is contemplated and within the scope of this disclosure that any method and/or circuit for measuring current through the power inductor <NUM> may be used, and one having ordinary skill in the design of SMPS systems and having the benefit of this disclosure would understand how to implement such a current measurement circuit. Various inductor current measurement circuits are more fully described in commonly owned <CIT>, and is incorporated by reference herein for all purposes.

The averaging filter(s) <NUM> continuously supplies an average value of the PWM control signal to an input of the ADC <NUM>. The ADC <NUM> converts the average value of the PWM control signal(s) to digital values that are periodically sampled by and stored in the memory of the digital processor <NUM>. From these stored averages, a determination can be made, e.g., with an optimization program running in the digital processor with memory <NUM>, for the most efficient combination(s) of operating parameters to run the SMPS system at any input voltage of load, e.g., frequency on and off times of the control signals, HDR and/or LDR, including dead times between HDR and LDR control signals.

Claim 1:
A switch-mode power supply (SMPS), comprising:
at least one power switch (<NUM>; <NUM>) coupled to a voltage source;
a power inductor (<NUM>) coupled to the at least one power switch (<NUM>; <NUM>);
a filter capacitor (<NUM>) coupled to a load side of the power inductor (<NUM>) that provides a regulated voltage output (VOUT) of the SMPS;
at least one driver (<NUM>) coupled to the at least one power switch (<NUM>; <NUM>);
a pulse width modulation (PWM) generator (<NUM>; <NUM>) having at least one output coupled to and controlling the at least one driver (<NUM>), the at least one output of the PWM generator (<NUM>; <NUM>) providing at least one PWM signal comprising a plurality of pulses;
a digital processor (<NUM>) having a memory, the digital processor (<NUM>) is coupled to and provides operating parameters to the PWM generator (<NUM>; <NUM>) during operation thereof;
characterized by
a voltage comparison circuit (<NUM>) for comparing the regulated output voltage (VOUT) to a reference voltage (VREF), wherein the voltage comparison circuit (<NUM>) has an error signal output representative of a difference between the regulated output voltage (VOUT) and the reference voltage (VREF);
a comparator (<NUM>) having a first input coupled to the error signal output from the voltage comparison circuit (<NUM>), a second input coupled to a ramp signal (ISENSE; VRAMP), and an output coupled to an input of the PWM generator (<NUM>; <NUM>);
a PWM averaging filter (<NUM>; <NUM>), wherein the PWM averaging filter (<NUM>; <NUM>) receives the PWM signal and produces an analog signal representative of a relative efficiency thereof; and
an analog-to-digital converter (ADC) (<NUM>) having an analog input coupled to the PWM averaging filter (<NUM>; <NUM>) for receiving the analog signal representative of the relative efficiency of the PWM signal, and a digital output coupled to the digital processor (<NUM>) having the memory;
wherein the digital processor (<NUM>) is designated for storing in the memory digital efficiency values from the digital output of the analog-to-digital converter (ADC) (<NUM>) and wherein the digital processor (<NUM>) optimizes operation of the SMPS by adjusting operating parameters of the PWM generator (<NUM>; <NUM>) by using the stored digital efficiency values to provide the at least one PWM signal that produces a highest relative efficiency of the SMPS.