Patent Description:
Thus, there is a need for integration of SiC wafer splitting and SiC production processes in an efficient and cost sensitive manner.

Of course, the present invention is not limited to the above features and advantages. Indeed, those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

According to the present invention, a method of splitting a semiconductor is disclosed in claim <NUM>.

The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.

Notably, modifications and other embodiments of the disclosed invention(s) will come to mind to one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.

The embodiments described herein are directed to a semiconductor wafer splitting process that reduces manufacturing costs associated with producing semiconductor devices. While emphasis is placed on SiC wafers and SiC devices produced using SiC wafers, the embodiments described herein are not intended to be limited to SiC wafers and may be used with other semiconductor wafer technologies such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), sapphire, etc. Device structures are produced in a base (thick) semiconductor wafer and the base wafer is subsequently split into a thinner device wafer, which includes the device structures, and a thinner reclaimed wafer. The reclaimed wafer may be processed and further devices produced within the reclaimed wafer.

The wafer splitting technique described herein includes at least two main steps: (i) forming a separation region within a semiconductor wafer and which has at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer splits into two separate pieces.

In some embodiments, forming the separation region includes forming microscopic cracks that are at least partially disconnected from one another within the separation region. The microscopic cracks connect to one another in response to the external force applied to the semiconductor wafer, forming the at least one crack which propagates along the separation region and which splits the semiconductor wafer into two separate pieces. Material waste/loss may be reduced by first creating the microcracks and subsequently connecting the microcracks, as opposed to creating connected cracks in a single step/process.

The external force applied to the semiconductor wafer may involve ultrasonic vibrations or application of a polymer layer, for example. Splitting a semiconductor wafer using just ultrasonic vibrations or a polymer layer without first creating a separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region may result in uncontrolled splitting and/or unwanted surface structures such as Wallner lines, river lines, etc., owing to the effect of sound reflections during the splitting which occurs as the at least one crack progresses.

Described next are various embodiments of the semiconductor wafer splitting process.

<FIG> illustrate cross-sectional views of a semiconductor wafer <NUM> during different stages of the splitting process, according to an embodiment. As explained above, the semiconductor wafer <NUM> may be any type of wafer used to produce semiconductor devices. For example, the semiconductor wafer may be a SiC wafer such as <NUM>-SiC and may have a thickness (T _wafer) which may vary depending on wafer diameter. Typically, <NUM> inch whereby <NUM> inch = <NUM>, and <NUM> inch SiC wafers have a thickness of <NUM> (microns) with an accuracy of, e.g., at most ± <NUM> or at most ±<NUM>. For larger SiC wafer diameters, the thickness may be higher. The wafer splitting process described herein may also be used with other SiC polytypes and/or other semiconductor materials, as explained above (e.g., Si, GaAs, GaN, sapphire, etc.), with corresponding adaptations of the process parameters.

<FIG> shows the semiconductor wafer <NUM> after one or more epitaxial layers <NUM> are formed on the semiconductor wafer <NUM>, device structures <NUM> are formed in the one or more epitaxial layers <NUM>, a metallization layer and/or a passivation layer <NUM> (e.g., at least one passivation layer) is formed over the device structures <NUM>, and a carrier <NUM> is attached to the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM>. Layer <NUM> is shown in the cross-sectional as a continuous layer, but instead may be discontinuous. For example, in the case of a passivation layer, layer <NUM> may be present only above the device structures <NUM>. In the case of a metallization layer, layer <NUM> may be patterned. The carrier <NUM> protects the device structures <NUM> from damage and mechanically stabilizes the semiconductor wafer <NUM> during and/or after the splitting process.

Doping regions <NUM>, <NUM>, <NUM> of the device structures <NUM> are produced by implantation with subsequent annealing steps or by doping during the epitaxial process. For example, a first deposited epitaxial layer <NUM> may be an n-doped drain or emitter layer with a thickness ranging, e.g., between <NUM> and <NUM> for power MOSFET (metal-oxide-semiconductor field effect transistors) or power diode devices, or a p-doped emitter layer for IGBT (insulated gate bipolar transistor) devices. A second epitaxially deposited layer (not shown) may be deposited as a buffer layer for preventing punch-through of the space charge layer towards the emitter / drain layer <NUM>. The thickness of the buffer layer is typically <NUM> to <NUM> or <NUM> to <NUM>. A n-type drift zone layer <NUM> may then be deposited by an epitaxial technique. The thickness of the drift zone layer <NUM> depends on the target breakdown voltage (for <NUM> V devices typically in the range between <NUM> and <NUM> and for <NUM>. kV devices between <NUM> and <NUM>). The doping level of the drift zone layer <NUM> also may be adjusted according to the desired breakdown voltage (for <NUM> V devices typically about <NUM>-<NUM> and for <NUM> kV devices a few times <NUM>-<NUM>). Front side device structures <NUM>, such as p-body and source regions for power MOSFETs or IGBTs or p-emitter for power diodes, may be formed by masked ion implantation with subsequent annealing steps. For switchable devices, a gate structure is also realized in the form of planar or trench-based gates.

After device formation, the semiconductor wafer <NUM> has a front side with the device structures <NUM> and a front side metallization layer and/or passivation layers <NUM>. The device structures <NUM> may be structures of a semiconductor device, for example a MEMS (microelectromechanical systems) and/or a MOEMS (micro-opto-electro-mechanical system) device, a diode such as an MPS (merged-pin-Schottky) diode, Schottky diode, MOS-gated diode, etc. or a transistor device such as a MOSFET, JFET (junction FET), IGBT, fin-FET, thyristor, etc. or a combination thereof. If the device structures <NUM> include a Schottky contact, the front side metallization layer <NUM> may include a Schottky contact metal. In addition, or as an alternative in the case of no Schottky contact, the front side metallization layer <NUM> may include an Ohmic contact metal.

<FIG> shows the semiconductor wafer <NUM> after forming a separation region <NUM> within the semiconductor wafer <NUM>. The separation region <NUM> has at least one altered physical property which increases thermo-mechanical stress within the separation region <NUM> relative to the remainder of the semiconductor wafer <NUM>. The carrier <NUM> which protects the device structures <NUM> from damage and mechanically stabilizes the semiconductor wafer <NUM> during and/or after the splitting process is attached to the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> before or after forming the separation region <NUM>. The carrier <NUM> may be a single piece of material or a carrier system that includes multiple layers and/or complex structures.

The shape of the carrier <NUM> may be similar or even identical to the shape of the semiconductor wafer <NUM>. The semiconductor wafer <NUM> may have a flat cut into one or more sides for indicating the crystallographic planes of the wafer <NUM>, whereas the carrier <NUM> may not have such flats. The carrier <NUM> may have a larger diameter than the semiconductor wafer <NUM>, e.g., at least <NUM>% larger. The diameter of the carrier <NUM> may be, e.g., at most <NUM> times or at most <NUM> times or at most <NUM> times the diameter of the semiconductor wafer <NUM>. Either a mechanically stabilizing part of the carrier <NUM> and/or an optional fixing layer of the carrier <NUM> may fully cover the front side of the semiconductor wafer <NUM>, e.g., as shown in <FIG>. Alternatively, either the mechanically stabilizing part and/or an optional fixing layer of the carrier <NUM> divide the front (active) side of the semiconductor wafer <NUM> into sections along the surface of the wafer <NUM> as shown in <FIG>. According to this embodiment, either the mechanically stabilizing part and/or an optional fixing layer of the carrier <NUM> may have the shape of a ring, a grid, and/or may only be present in peripheral regions of the semiconductor wafer <NUM>, e.g., an intersected ring at the outer / peripheral part of the wafer <NUM>. In each case, the topography of the device structures <NUM> may be embedded in the carrier <NUM>, e.g., by a potting material and/or an adhesive layer and/or a non-adhesive layer <NUM> between the carrier <NUM> and the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> and the front side metallization <NUM>.

The carrier <NUM> may be either temporarily (reversibly) or permanently attached to the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM>. In the case of temporary attachment, the carrier <NUM> may include an adhesive tape having thermal or UV release, an adhesive (organic or inorganic composition) layer in combination with a rigid support such as a transparent substrate, non-transparent substrate, polymer film, etc., a fixed or mobile electrostatic chuck, a fixed or mobile vacuum chuck, a mobile vacuum carrier, etc. In the case of permanent attachment, the carrier <NUM> may include hot embossed glass, e.g., in the form of a grid, a ring, etc., a glass grid and/or ring attached via solder glass, a glass grid and/or ring attached via a laser welding process, etc., a substrate such as a semiconductor, metal, insulator (e.g. glass) substrate joint to the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> via one or more diffusion soldering layers, a substrate joined to the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> via aerobic and or anaerobic adhesives or other binding components, etc..

The separation region <NUM> allows for splitting of the semiconductor wafer <NUM> at a defined position. Otherwise, the splitting would take place at a random position that may be influenced by crystal damages, etc. Furthermore, without the defined separation region <NUM>, reproducible manufacturing would be more difficult since only some of device wafers and/or reclaimed wafers could be used. The well-defined separation region <NUM> significantly reduces material losses (also referred to as kerf loss) during wafer splitting. A thickness (t_sep) of the separation region <NUM> may define the kerf loss. For example, losses may originate from the vertical extent of the microscopic cracks and additional losses due to chemical, mechanical, electrochemical and/or plasma material removal.

The position of the separation region <NUM> may be chosen such that, after defining the device structures <NUM>, the distance 'd1' to the front side of the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> is sufficiently high to allow for mechanical handling of the thinner device wafer which results from the splitting process, and such that the distance d1 to the front side is sufficiently low and therefore the distance 'd2' to the backside is sufficiently high so that the reclaimed wafer which results from the splitting process may still be processed. In one embodiment, the separation region <NUM> is close to the interface between the wafer <NUM> and the first deposited epitaxial layer <NUM> (substrate/drain layer for power MOSFETs or substrate/emitter layer for diodes). Typically, the distance between the separation region <NUM> and the interface between the wafer <NUM> and the first deposited epitaxial layer <NUM> is less than <NUM> or even less than <NUM> or even less than <NUM>.

In general, thermo-mechanical stress may be increased within the separation region <NUM> compared to the remainder of the semiconductor wafer <NUM>, thus simplifying splitting of the semiconductor wafer <NUM> into a device wafer and a reclaimed wafer, e.g., by applying mechanical force and/or thermal stress to the wafer <NUM>. The thermo-mechanical stress generated within the separation region <NUM> may be sufficient to bring about the wafer splitting, without necessarily requiring application of an external force. For example, laser radiation may be applied to the separation region <NUM> such that the separation region <NUM> has increased thermo-mechanical stress relative to the remainder of the semiconductor wafer <NUM> and at least one crack propagates along the separation region <NUM>, thereby enabling wafer splitting without the use of an external force. However, an external force will still be applied to lift off one of the split wafer pieces and/or to aid in the wafer splitting.

The separation region <NUM> is formed by damaging the material of the semiconductor wafer <NUM> at a targeted position. For example, in the case of SiC as the wafer material, the SiC material may be damaged. In some cases, SiC may be at least partially decomposed, for instance, into Si and C. This may be done, e.g., by creating a plasma in the SiC material at the targeted position within the semiconductor wafer <NUM>. At least some of the atoms in the plasma may reform to carbon clusters and silicon material, e.g., in the form of amorphous carbon and/or amorphous silicon. In addition or as an alternative, at least some of the atoms may re-crystallize, semi-crystallize and/or re-organize, for example to at least one polytype of SiC (e.g., <NUM>-SiC, <NUM>-SiC, or 3C-SiC) or amorphous SiC where both Si and C phases are amorphous. In some examples, the separation region <NUM> may comprise at least one of crystalline portions of at least one polytype of SiC or silicon or carbon (e.g., in the form of microcrystalline), amorphous portions of SiC or silicon or carbon, and/or cavities.

A plasma is created in the material at the targeted position within the semiconductor wafer <NUM> by focusing laser radiation at the targeted position within the semiconductor wafer <NUM>. The semiconductor wafer <NUM> is irradiated through the backside opposite the device structures <NUM>, and focused to a well-defined region within the wafer <NUM> to ignite a plasma within the wafer <NUM> and which decomposes the laser irradiated semiconductor material into its constituent components. For example, in the case of SiC, laser irradiated SiC decomposes as follows: SiC → Si + C. The interaction with the laser radiation may result in a different material phase, e.g., as described above, and/or in microscopic cracks within the semiconductor wafer <NUM>. Irradiating the semiconductor wafer <NUM> with laser radiation through the front side is preferably be done before producing the device structures <NUM> or at least before producing the front side metallization <NUM>, since the laser radiation might damage the device structures <NUM> and since the metallization <NUM> is not transparent for laser radiation.

If the separation region <NUM> has already been pre-defined, e.g., by implantation as explained above briefly and as explained below in more detail, the laser radiation that is applied to the separation region <NUM> may be in a resonant regime where single-photon processes (e.g., single-photon absorption) dominate, i.e., a probability of multi-photon processes is small (e.g. at least ten times smaller than the probability of a single-photon process). In the resonant regime, the band gap of the material within the separation region <NUM> may be, e.g., in the range of the photon energy of the laser radiation (e.g. with a detuning of at most ±<NUM>% or at most ±<NUM>% or at most ±<NUM>% or at most ±<NUM>% of the band gap, depending on the laser energy). The laser radiation may be absorbed in the separation region <NUM> and may lead to further damage of the separation region <NUM> (e.g. decomposition of SiC in the case of a SiC wafer <NUM>), such that no or only a small mechanical force and/or thermal stress is needed to split the semiconductor wafer <NUM> at the separation region <NUM>.

The separation region <NUM> may be defined, or in the case of a pre-defined layer previously formed, e.g., by ion implantation, further defined, by focusing laser radiation to a well-defined region such as a region with at most the targeted thickness, e.g. at most <NUM>% of the targeted thickness, of the separation region <NUM> within the semiconductor wafer <NUM>. In this case, the laser radiation may be in an off-resonant regime such that a probability of single-photon processes in the separation region <NUM> is small and mostly multi-photon processes (in particular, multi-photon absorption) may have to be accounted for. For example, the off-resonant regime may be achieved if the band gap of the separation region <NUM> is larger than (e.g., at least twice of or at least ten times of) the photon energy of the laser radiation. In the case of a multi-photon process, damage creation may be further supported by a pre-defined layer (e.g., formed by ion implantation) that increases absorption within the region where the focal point of the laser radiation is positioned.

The laser radiation may be pulsed laser radiation. The parameters of the laser radiation such as pulse duration, repetition rate, pulse energy, intensity, wavelength, pulse shape, polarization, etc. are interconnected and may be optimized according to a specific application or requirement. For example, the laser radiation may have a pulse duration of <NUM> fs to <NUM> ns (e.g. <NUM> ps to <NUM> ns), a repetition rate of <NUM> to <NUM>, a pulse energy of 100nJ to 50µJ, and a peak wavelength of <NUM> to <NUM> (e.g., <NUM> to <NUM>).

The laser radiation may be applied along laser lines (also referred to as scribe lines) that run essentially parallel to one another. For each laser line, a laser beam is scanned along the line. The speed of the laser scanning may be so fast that neighboring single laser shots can be distinguished, e.g. do not overlap. Here, a single laser shot may correspond to the damage created by a single pulse of laser radiation as shown in <FIG>.

In <FIG>, which shows a small section of the separation region <NUM>, the dashed ovals labelled 'A' correspond to locations of individual / single laser shots. At each single laser shot location 'A', material of the separation region <NUM> is decomposed and microscopic cracks appear that extend along a crystal plane of the material of the wafer as indicated by the additional microscopic cracks labelled 'B' and 'C'. The microscopic cracks 'A', 'B', 'C' formed within the separation region <NUM> are at least partially disconnected from one another. The microscopic crack labelled 'C' is produced by tensions between other microscopic cracks 'A' and not directly formed by a laser shot. For <NUM>-SiC, the growth direction of the semiconductor wafer <NUM>, which corresponds to the vertical direction along which the wafer <NUM> has a thickness T _wafer, may be slightly tilted to the main crystal axis, typically by <NUM>° (also referred to as off-axis angle). Therefore, the crystal planes are tilted.

If the separation region <NUM> were to have only a single large crack, which would be planar but tilted, the separation region <NUM> would be tilted by <NUM>° with respect to the lateral directions (i.e., the directions perpendicular to the vertical direction). Along the entire diameter of the semiconductor wafer <NUM> this would result in tremendous losses. Accordingly, for SiC, the splitting process may be useful for <NUM>-SiC if the separation plane is not planar but has a zigzag shape / saw-tooth shape. The microscopic cracks 'A', 'B', 'C' are subsequently connected to enable splitting of the semiconductor wafer <NUM>, as described in more detail further below.

In addition or alternatively to damaging the semiconductor wafer <NUM> by laser radiation to form the separation region <NUM>, the material of the semiconductor wafer <NUM> may be damaged at the targeted position by implanting ions into the semiconductor wafer <NUM> at a depth corresponding to the targeted position within the wafer <NUM> to produce and/or pre-define the separation region <NUM>. The ions may result directly in higher absorption, e.g., due to higher absorption rate in the separation region <NUM> where the majority of implanted ions reside. In the case of SiC as the material of the semiconductor wafer <NUM>, the ions may lead to conversion of the crystal structure of the SiC wafer into a different material, for example into a different polytype (e.g., from <NUM>-SiC to 3C-SiC) and/or into a different crystallinity and/or into amorphous SiC and/or into silicon and carbon (amorphous or crystalline), such that the absorption coefficient at the wavelength of the laser radiation is increased in the separation region <NUM>. The ions may also result in decomposition of the material of the semiconductor wafer <NUM> in the separation region <NUM>.

In one embodiment, the ions may be selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions, and helium ions. For example, atoms such as nitrogen and/or phosphorus atoms may be implanted into the separation region <NUM>, with an implantation dose resulting in an amorphous layer and/or or cavities being created. In addition or alternatively, helium ions or protons may be implanted to create a local damaged layer within the separation region <NUM>. Light ions such as helium and hydrogen penetrate more deeply in the semiconductor wafer <NUM> as compared to heavier ions for the same energy, increasing the depth of the separation region <NUM> if desired. Light ions like helium and hydrogen may create vacancy clusters and damaged layers preferentially in the end-of-range of the implantation so that the splitting process can be facilitated in this region. Phosphorous and/or nitrogen are suitable for realizing highly damaged layers in SiC. In the case of phosphorous and/or nitrogen, the implantation dose may be chosen such that an amorphous layer and/or cavities are created in the separation region <NUM>. Optionally, channelling may be exploited during implantation which results in a lower surface damage of the surface into which the implantation is performed. The ions may be implanted before the one or more epitaxial layers <NUM> are formed. For example, the ions may be implanted through the surface of the semiconductor wafer <NUM> onto which the one or more epitaxial layers <NUM> are to be formed.

After ion implantation, the device structures <NUM> may be produced. After or before producing the device structures <NUM>, laser radiation as described above may be irradiated through the semiconductor wafer <NUM>, with the focal point being roughly positioned at the implantation layer. The ions and/or the semiconductor material that has been converted by the ions will have an increased absorption compared to the rest of the wafer <NUM>, thus improving the decomposition of, e.g., SiC into Si and C by an enhanced local heating of the wafer <NUM>. For example, a combination of a multi-photon and single-photon processes may take place within the pre-defined ion implantation layer in order to increase the thermo-mechanical stress within the separation region <NUM> relative to the remainder of the semiconductor wafer <NUM>.

The separation region <NUM> may be formed before or after for the device structures <NUM> are formed. In some embodiments, a part of the separation region <NUM> may be formed before the device structures <NUM> are formed, e.g. even before epitaxial growth, and another part of the separation region <NUM> may be formed after the device structures <NUM> are formed.

In one embodiment, the separation region <NUM> is formed by both laser irradiation and ion implantation of the semiconductor wafer <NUM>. Particularly, the material of the semiconductor wafer <NUM> may be damaged at the targeted position within the semiconductor wafer <NUM> by implanting ions into the semiconductor wafer <NUM> at a depth corresponding to the targeted position within the wafer <NUM>. After the ions are implanted, laser radiation is then focussed at the targeted position within the semiconductor wafer <NUM>. According to this embodiment, the implanted ions increase an absorption coefficient in the separation region <NUM> at a wavelength of the laser radiation which further increases the thermo-mechanical stress within the separation region <NUM> relative to the remainder of the semiconductor wafer <NUM>.

After formation of the separation region <NUM>, an external force is applied to the semiconductor wafer <NUM> such that at least one large crack propagates along the separation region <NUM> and the semiconductor wafer <NUM> splits into two separate pieces. The force equilibrium of surface energy, bonding forces and external pressure are shifted in favor of the external force such that internal binding forces still present within the semiconductor wafer <NUM> are overcome at the separation region <NUM>, thus resulting in crack propagation. Alternatively, the laser radiation propagates enough cracks along the separation region <NUM> such that application of an external force is not necessarily required to split the semiconductor wafer <NUM>. However, an external force will still be applied to aid the lift-off process of the split wafer pieces and/or the wafer splitting.

The separation region <NUM> has at least one altered physical property which increases thermo-mechanical stress within the separation region <NUM> relative to the remainder of the semiconductor wafer <NUM>, as explained above. For example, laser radiation and/or ion implantation may be used to alter at least one physical property of the separation region <NUM>. Laser radiation may form microscopic cracks 'A', 'B', 'C' in the separation region <NUM> whereas implanted ions may increase the absorption coefficient in the separation region <NUM> at a wavelength of the laser radiation. The localized increase in thermo-mechanical stress restricts crack propagation to the separation region <NUM> in a controlled and reproducible manner. The localized increase in thermo-mechanical stress may be sufficient to propagate enough cracks along the separation region <NUM> such that application of an external force is not necessarily required to split the semiconductor wafer <NUM>. However, an external force is used to aid in splitting the semiconductor wafer <NUM>.

In one embodiment, the external force applied to the semiconductor wafer <NUM> for splitting the wafer <NUM> along the separation region <NUM> includes applying ultrasonic vibrations (sound waves) to the semiconductor wafer <NUM>. The ultrasonic vibrations may have a frequency in the kHz regime, e.g., at least <NUM> and at most <NUM> (e.g., <NUM>-<NUM>, e.g. <NUM>-<NUM>). The semiconductor wafer <NUM> may be placed in a container filled with a fluid such as pure water, deionized water, solvents in general, dimethylformamide, isopropyl alcohol, methanol, and/or ethanol when applying the ultrasonic vibrations. For example, a device similar to an ultrasonic cleaning apparatus may be used to apply the ultrasonic waves to the semiconductor wafer <NUM>.

<FIG> illustrate another embodiment of applying the external force to the semiconductor wafer <NUM> for splitting the wafer <NUM> along the separation region <NUM>. According to this embodiment, a polymer <NUM> is applied to the semiconductor wafer <NUM> and/or the carrier <NUM> as shown in <FIG>. The polymer <NUM> has a CTE (coefficient of thermal expansion) different from a CTE of the semiconductor wafer <NUM>. The polymer <NUM> and semiconductor wafer <NUM> are the then subjected to a temperature process during which the polymer <NUM> imparts mechanical stress to the semiconductor wafer <NUM> as indicated by the dashed arrows in <FIG>. The mechanical stress causes at least one large crack <NUM> to propagate along the separation region <NUM> such that the semiconductor wafer splits <NUM> into two separate pieces <NUM>, <NUM> as shown in <FIG>. One piece <NUM> retains the device structures <NUM>. The other piece <NUM> is available for subsequent device processing.

In the case of the separation region <NUM> including microscopic cracks 'A', 'B', 'C' as explained above in connection with <FIG>, the mechanical stress imparted to the semiconductor wafer <NUM> causes the microscopic cracks 'A', 'B', 'C' to connect to one another to form the large crack <NUM> which splits the wafer <NUM>. That is, the individual microscopic cracks 'A', 'B', 'C' shift with respect to one another in response to the external force. The separation region <NUM> may thus not be viewed as a single layer within the semiconductor wafer <NUM>, but rather a combination of several microscopic cracks 'A', 'B', 'C' that are only combined during the splitting. In the case of SiC as the material of the semiconductor wafer <NUM>, combining the microscopic cracks 'A', 'B', 'C' results in both separate pieces <NUM>, <NUM> having a separation surface <NUM>, <NUM> with a saw-tooth pattern. The resulting device piece <NUM> and the reclaimed piece <NUM> thus do not have a smooth planar surface in the case of SiC. In one embodiment, after the semiconductor wafer <NUM> is split into the two separate pieces <NUM>, <NUM>, each separation surface <NUM>, <NUM> which results from the large crack <NUM> propagating along the separation region <NUM> is smoothed. Residual decomposed material may be present at the separation surface <NUM>, <NUM> of each piece <NUM>, <NUM> split from the wafer <NUM>, and may be removed by a cleaning process.

The polymer <NUM> may be attached to the semiconductor wafer <NUM> with the carrier <NUM> already attached to the wafer <NUM>. The polymer <NUM> may be attached at the backside <NUM> of the semiconductor wafer <NUM> that faces away from the front side and the carrier <NUM>. The polymer <NUM> instead may be attached to an outer side <NUM> of the carrier <NUM> which faces away from the semiconductor wafer <NUM>. In this case, the carrier <NUM> is located between the polymer <NUM> and the semiconductor wafer <NUM>. According to another embodiment, the polymer <NUM> may be attached to both the backside <NUM> of the semiconductor wafer <NUM> and the outer side <NUM> of the carrier <NUM>. For example, if a glass grid or a glass ring is used as the carrier <NUM>, the polymer <NUM> may be applied at the backside <NUM> of the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> and additionally at the outer side <NUM> of the carrier <NUM>. In general, a further layer (e.g., a bonding layer, such as an adhesive, and/or a layer that simplifies later removal of the polymer <NUM>) may be applied between the polymer <NUM> and the side at which the polymer <NUM> is applied.

The polymer <NUM> may be selected based not only CTE, but also by taking into account multiple parameters. The CTE of the polymer <NUM> should be different from the CTE of the semiconductor wafer <NUM>. For example, the CTE of the polymer <NUM> is preferably larger than the CTE of the semiconductor wafer <NUM>. In addition to the CTE difference, the linear course of the CTE in the polymer <NUM> over a wide temperature range may be advantageous for successful separation.

Furthermore, the polymer <NUM> should have sufficiently high thermal conductivity. In one embodiment, one or more fillers such as ZnO and/or carbon black are added to the polymer <NUM> before the temperature process. The filler(s) increase the thermal conductivity of the polymer <NUM> and reduce a slope of a storage modulus of the polymer <NUM>, extending the linear course of the CTE in the polymer <NUM> over a smaller temperature range. By adding ZnO and/or carbon black to the polymer <NUM>, percolation chains that form can significantly increase thermal conductivity in the polymer <NUM>. If a filler material is used, the polymer material may be chosen such that the filler material is easily homogeneously distributed throughout the polymer <NUM>.

For sufficiently large coefficients of heat transfer to the semiconductor wafer <NUM>, adding one or more fillers such as ZnO and/or carbon black to the polymer reduces by more than half the time needed to achieve a temperature differential that generates sufficient mechanical stress for splitting the semiconductor wafer <NUM> along the separation region <NUM>. At the same time, the rise in modulus of elasticity is distributed over a greater temperature range since it is already apparent at higher temperatures by comparison with an unfilled polymer. As a result, there is less wafer breakage in the manufacturing process and a higher split efficiency is provided. One example for the polymer <NUM> is PDMS (polydimethylsiloxane), usually with at least one filler. PDMS may generate high adhesion to a surface. Attaching may thus require some preprocessing or conditioning to allow for damage-free polymer removal. For example, a foil may be positioned between the polymer and the surface to which the polymer is attached.

Attaching the polymer <NUM> is typically performed at higher temperatures (e.g., above room temperature but below <NUM>). A binding process may be applied to allow for a firm bond throughout the entire temperature process. For example, before applying the polymer <NUM>, the application surface of the polymer <NUM> and/or semiconductor wafer <NUM> and/or carrier <NUM> may undergo chemical and/or physical surface treatment (for example, with a plasma) to allow for firm bonding. An indirect temporary cold plasma activation process may be used to ensure subsequent easy removal of the polymer <NUM>. This has the advantage that ambivalent characteristics of the structure-property relationships are achievable here and that no significant thermal diffusion processes are to be expected at the low temperatures that occur. Diffusion may, e.g., be problematic in the case of metallic impurities, such as impurities originating from metallic layers of the device structures <NUM>. The polymer binding is sufficient for execution of the splitting operation, but sufficiently weak for complete removal of the polymer <NUM> in subsequent steps.

Another additional or alternative approach is to apply a binding (sacrificial) layer between the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> (and/or, if applicable, carrier <NUM>) and the polymer <NUM>. The binding layer may be chosen such that adhesion to the polymer <NUM> can be reduced, e.g., with chemicals or with thermal treatment.

The polymer <NUM> may not be produced directly on the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> and/or directly on the carrier <NUM>. Rather, the polymer <NUM> may be pre-produced and subsequently attached to the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> and/or carrier <NUM>. In other embodiments, the polymer <NUM> is produced directly on the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> and/or carrier <NUM>, e.g., via spraying or coating.

After attaching the polymer <NUM> to the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM> and/or carrier <NUM>, the temperature process is carried out. In one embodiment, the temperature process is selected such that the polymer <NUM> undergoes a partial glass transition and a partial crystallization during the temperature process. This may include a first phase during which the polymer <NUM> and the semiconductor wafer <NUM> undergo a temperature gradient from a starting temperature down to room temperature, the starting temperature being <NUM> or less but above room temperature, and a second phase during which the polymer <NUM> and the semiconductor wafer <NUM> are further cooled down to a lower temperature. For example, the lower temperature may correspond to ±<NUM> of a boiling temperature of a cooling liquid (e.g., liquid nitrogen) used for cooling. The lower temperature may be, for example, -<NUM>, in particular for the entire wafer <NUM>. In some examples, the lower temperature may be below a glass transition temperature (Tg) of the polymer <NUM>, depending on the cooling conditions (e.g., the cooling liquid.

<FIG> illustrate the storage modulus (modulus of elasticity) in MPa over temperature in °C for the same polymer <NUM> without fillers (<FIG>) and with one or more fillers (<FIG>). During the second phase of the temperature process, the polymer <NUM> may undergo a partial glass transition and a partial crystallization process as shown in <FIG>. The definition of glass transition Tg is not standardized. There are several methods to determine Tg which is not a constant material property but rather depends on the method used to define Tg and also on parameters used during this method. For example, if using the DMA (dynamic mechanical analyzing) method, which measures the viscoelastic moduli, the dynamic glass transition temperature must be stated and also what parameters are used for the measurement (e.g., frequency of the external load, ramping speed, ramping direction, measurement accuracy, etc.).

In <FIG>, the glass transition temperature Tg is found at the turning point (at least for some methods of defining Tg). In <FIG>, the crystallization starts at higher temperatures (slower slope between T1 and T2) than the glass transition (higher slope below T2) where T3 is below T2 and T2 is below T1. A turning point, and thus Tg, can no longer be clearly determined as compared to the same polymer in <FIG> but without fillers.

By adding one or more fillers to the polymer <NUM>, the degrees of freedom in the used polymer crystallize earlier than those of a polymer without fillers. At a temperature above the glass transition, the polymer molecules are flexible and can adopt different conformations, e.g., through bond rotation around flexible Si-O-Si siloxane single bonds ([R3Si-O-SiR3]n). With an increasing temperature reduction, there is a restriction of the existing degrees of freedom and thus a reduction in the mobility of the elastomer molecules, since the necessary activation energy for binding rotation is achieved statistically less often. The frequency of site changes of the polymer molecules decreases with decreasing temperature. Due to the additionally occurring intermolecular interactions between the filler particles and the polymer molecules, the dynamics of the rearrangement of the polymer molecules is reduced as the group vibrations or cooperative movements of the surrounding chains and molecules are reduced due to the lower free volume. At very high filler contents (e.g. > <NUM> w%), particle-particle interactions should be accounted for.

The storage modulus (modulus of elasticity) of the polymer <NUM> has an increase for higher temperatures for the polymer <NUM> in <FIG> which has one or more fillers, compared to the polymer in <FIG> with no fillers. Consequently, the slope of the storage modulus increase is lower. The increase in force during the splitting process is proportional to the storage modulus. Therefore, a lower slope translates into a lower increase in force and thus a smoother force increase, resulting in a smoother crack propagation. Tensions within the semiconductor wafer <NUM> may be relieved with less wafer breakage outside the separation region <NUM> by adding one or more fillers to the polymer <NUM>. In contrast, for a higher increase in force, inhomogeneities have a higher impact on the splitting process. The polymer crystallization may lead to lower overall force, but this could be, e.g., compensated for by increasing the thickness of the polymer <NUM>. The temperature gradient and temperature process are preferably chosen such that local temperature differences within the semiconductor wafer <NUM> are reduced. Excessive local temperature differences can lead to excessive increases in stress and to unwanted fractures within the semiconductor wafer <NUM>.

The semiconductor wafer <NUM> may have a bevelled edge <NUM>, e.g., as shown in <FIG>. The bevelled edge <NUM> has chamfered outer faces as shown in <FIG>. The shape of the bevelled edge <NUM> may lead to problems when preparing the separation region <NUM> the position of which is indicated by a dashed line in <FIG>. For example, the change in thickness in the bevelled edge <NUM> may lead to a change in propagation length for a laser beam. Therefore, the focus point of the laser beam changes at the wafer bevel. As a result, the separation region <NUM> may not continue to the outer rim /edge face <NUM> of the semiconductor wafer <NUM>. A change in thickness and/or position at the outer rim / edge face <NUM> of the semiconductor wafer <NUM> may also hinder implantation of ions to define or pre-define the separation region <NUM>.

To allow for access to the separation region <NUM> from the outer rim / edge face <NUM> and thus to facilitate or at least simplify the splitting process, the shape of the bevel may be modified as shown in <FIG>. According to these embodiments, the bevelled edge <NUM> of the semiconductor wafer <NUM> is thinned to a depth T_thin at or below the separation region <NUM> the position of which is indicated by a dashed line in <FIG>. Depending on the type of thinning employed, the thinned area may have a square (<FIG>) or rounded (<FIG>) corner. The bevelled edge <NUM> of the semiconductor wafer <NUM> may be thinned by mechanical removal such as by grinding, cutting, by laser ablation, by electro (chemical) discharge machining, by etching, etc..

<FIG> shows another embodiment according to which a slot <NUM> is formed in the bevelled edge <NUM> of the semiconductor wafer <NUM> and which laterally extends to the separation region <NUM> the position of which is indicated by a dashed line in <FIG>. The slot <NUM> may be formed as an alternative or in addition to the thinning shown in <FIG>. In each case, the bevelled edge <NUM> of the semiconductor wafer <NUM> may be processed before or after producing the separation region <NUM>.

During the wafer splitting process, pressure may be applied to the semiconductor wafer <NUM>. For example, a piston may apply pressure to the semiconductor wafer <NUM> with the one or more epitaxial layers <NUM>. The piston may be pushed in the direction of the wafer <NUM> with pressurized air, or only the weight force of the piston may be applied to the wafer <NUM>. Such a process is better controlled than dipping (e.g., fully or gradually) the wafer <NUM> with the polymer <NUM> into cryogenic fluids (e.g. nitrogen), particularly for spatial resolution of the cooling process.

After the splitting of the semiconductor wafer <NUM>, the piece <NUM> which retains the device structures <NUM> may be thinner than the other piece126. For example, the piece <NUM> which retains the device structures <NUM> may have a thickness of at most <NUM> (e.g., at most <NUM> or at most <NUM>) and at least the required thickness of the drift zone as described above (or at least <NUM> more than the required thickness) and the other piece <NUM> may have a thickness of at least <NUM> (e.g., at least <NUM>).

To allow for re-using the polymer <NUM> and to avoid breakage of the split wafer pieces <NUM>, <NUM>, polymer removal may be employed. For example, the polymer <NUM> may be removed by mechanical means both on the device side separation surface <NUM> (if applicable) and on the reclaimed side separation surface <NUM> without chemical etching (in general, without chemicals), without plasma etching or other gas phase sputtering processes. The polymer <NUM> may thus be removed rapidly and in an environmentally friendly and residue-free manner, owing to the attachment processes described herein.

After the wafer splitting, the separation surfaces <NUM>, <NUM> of the split wafer pieces <NUM>, <NUM> on which piece <NUM>, <NUM> is being processed. For the backside of the piece <NUM> with the device structures <NUM>, a damage removal, e.g., by mechanical grinding and/or chemical mechanical polish and/or etching may be performed. The final roughness of the separation surface <NUM> after damage removal may have a root-mean-square (rms) value below <NUM> or even below <NUM>. Further processing may then follow. In the case of the piece <NUM> without the device structures <NUM>, the separation surface <NUM> may need processing to be ready for subsequent epitaxial growth. In this case, the rms value of the separation surface <NUM> may be below <NUM> or even below <NUM>. The thickness of the piece <NUM> without the device structures <NUM> may be adapted to the original thickness of the wafer <NUM>, e.g., by means of deposition techniques such as CVD-epitaxial techniques, so that the same procedure as described above can be repeated several times for the thickened pieces <NUM>.

The embodiments previously described herein involve splitting a new wafer from a base semiconductor wafer. Alternatively, the splitting techniques described herein may be applied to splitting semiconductor wafers from a semiconductor boule. A semiconductor boule is a single crystal ingot produced by a synthetic means such as the Bridgman technique, the Czochralski process, etc. The splitting techniques described herein may be applied to splitting semiconductor wafers from a semiconductor boule by forming a separation region within a semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule. For example, thermo-mechanical stress may be increased within the separation region by focusing laser radiation at a targeted position within the semiconductor boule. An external force is then applied to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule. In one embodiment, an external force is applied to the semiconductor boule by applying a polymer to the semiconductor boule, the polymer having a CTE different from a CTE of the semiconductor boule. The polymer and the semiconductor boule are subjected to a temperature process during which the polymer imparts mechanical stress to the semiconductor boule. Also as previously described herein, the thermo-mechanical stress generated within the separation region of the semiconductor boule may be sufficient to bring about wafer splitting, without necessarily requiring application of an external force. In either case, the process may be applied multiple times to yield a plurality of wafers from a single semiconductor boule.

Terms such as "first", "second", and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

Claim 1:
A method of splitting a semiconductor wafer, the semiconductor wafer having a front side and a backside, the method comprising:
forming one or more epitaxial layers (<NUM>) on the front side of the semiconductor wafer (<NUM>);
forming a plurality of device structures (<NUM>) in the one or more epitaxial layers (<NUM>);
forming a metallization layer and/or a passivation layer (<NUM>) over the plurality of device structures (<NUM>);
attaching a carrier (<NUM>) to the semiconductor wafer (<NUM>) with the one or more epitaxial layers (<NUM>), the carrier (<NUM>) protecting the plurality of device structures (<NUM>) and mechanically stabilizing the semiconductor wafer (<NUM>);
forming a separation region (<NUM>) within the semiconductor wafer (<NUM>), the separation region (<NUM>) having at least one altered physical property which increases thermo-mechanical stress within the separation region (<NUM>) relative to the remainder of the semiconductor wafer (<NUM>), wherein forming the separation region (<NUM>) comprises damaging a material of the semiconductor wafer (<NUM>) at a targeted position within the semiconductor wafer (<NUM>), wherein damaging the material of the semiconductor wafer (<NUM>) comprises creating a plasma in the material at the targeted position, wherein creating the plasma comprises focusing laser radiation at the targeted position through the backside of the semiconductor wafer (<NUM>) opposite the device structures (<NUM>); and
applying an external force to the semiconductor wafer (<NUM>) such that at least one crack propagates along the separation region (<NUM>) and the semiconductor wafer (<NUM>) splits into two separate pieces (<NUM>, <NUM>), one of the pieces (<NUM>) retaining the plurality of device structures (<NUM>).