Patent Description:
Semiconductor device assemblies, such as assemblies including power semiconductor devices, such as power transistors (e.g., insulated-gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field effect transistors (MOSFETs), etc.) can be implemented using multiple semiconductor die, one or more substrates (e.g., direct-bonded metal substrates) and electrical interconnections, such as bond wires, conductive spacers and conductive clips, as well as a molding compound (e.g., an epoxy molding compound) that is used as an encapsulant to protect other components of an associated device assembly. Such power transistor devices can be used in a number of applications, including automotive and/or industrial applications.

For instance, such power transistor devices can be used to implement electrical inverters used in electrical vehicles (EVs) and/or hybrid electrical vehicles (HEVs). Current implementations of semiconductor device assemblies including such power transistors (e.g., in combination with a fast recovery diode (FRD)) have certain drawbacks, however. For instance, current implementations may only allow for cooling of the assembly (e.g., by attaching a thermal dissipation appliance) on a single side of the assembly. This can cause and/or exacerbate stresses between components within such an assembly, such as tensile stress and strain energy on the included semiconductor die, which can damage (e.g., crack) those semiconductor die. As power requirements and associated operating temperatures for such devices increase, incidents of such damage will also increase. A signal distribution assembly according to the preamble of claim <NUM> and a semiconductor device module according to the preamble of claim <NUM> are disclosed by <CIT>. Further signal distribution assemblies and semiconductor device modules are disclosed by <CIT>, <CIT> and <CIT>.

In some aspects, the techniques described herein relate to a semiconductor device module including: a substrate including: a first ceramic layer; and a first metal layer disposed on a first surface of the substrate; and a first semiconductor die, a first side of the first semiconductor die being coupled to the first metal layer; a second semiconductor die, a first side of the second semiconductor die being coupled to the first metal layer; and a signal distribution assembly including a second metal layer, the second metal layer having: a first side, the first side being planar; and a second side opposite the first side, the second side being non-planar and including: a base portion; a first post extending from the base portion, the first post being coupled with a second side of the first semiconductor die opposite the first side of the first semiconductor die; and a second post extending from the base portion, the second post being coupled with a second side of the second semiconductor die opposite the first side of the second semiconductor die, the signal distribution assembly electrically coupling the first semiconductor die with the second semiconductor die.

In some aspects, the techniques described herein relate to a semiconductor device module, further including a second ceramic layer coupled with the first side of the second metal layer.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein the second ceramic layer is a thermally conductive ceramic layer that is coupled with the first side of the second metal layer via a thermally conductive epoxy adhesive.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein: the signal distribution assembly is pre-molded and includes a molding compound disposed on the second side of the second metal layer; a surface of the first post that is coupled with the first semiconductor die is exposed through the molding compound; and a surface of the second post that is coupled with the second semiconductor die is exposed through the molding compound.

In some aspects, the techniques described herein relate to a semiconductor device module, further including: an insulator layer, a first surface of the insulator layer being coupled with the first side of the second metal layer; and a third metal layer coupled with a second surface of the insulator layer opposite the first surface of the insulator layer.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein the insulator layer electrically insulative and thermally conductive.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein: the second metal layer has an overall thickness of less than <NUM> millimeter (mm); and the first post and the second post have a same height of less than <NUM>.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein the same height is less than <NUM>.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein: the base portion is a first base portion; the first base portion, the first post and the second post are included in a first portion of the second metal layer; and the second metal layer further includes a second portion having: a second base portion; and a third post extending from the second base portion, the third post being coupled with the second side of the first semiconductor die.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein: the first semiconductor die is one of an insulated-gate bipolar transistor (IGBT) or a metal-oxide-silicon field-effect transistor (MOSFET); the second semiconductor die is a fast-recovery diode (FRD); and the first post being coupled with one of an emitter terminal of the IGBT, or with a source terminal of the MOSFET; the second post being coupled with a cathode of the FRD; and the third post being coupled with a gate terminal of the IGBT, or with a gate terminal of the MOSFET.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein the first portion of the second metal layer further includes a fourth post extending from the first base portion, the fourth post being coupled with a signal terminal of a leadframe of the semiconductor device module, the signal terminal being an emitter signal terminal, or a source signal terminal.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein the first portion of the second metal layer includes a fourth post extending from the first base portion, the fourth post being coupled with a thermal sense signal pin of a leadframe of the semiconductor device module.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein the second portion of the second metal layer includes a fourth post extending from the second base portion, the fourth post being coupled with a gate signal pin of a leadframe of the semiconductor device module.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein: the signal distribution assembly is pre-molded and includes a molding compound disposed on the second side of the second metal layer; a surface of the first post that is coupled with the first semiconductor die is exposed through the molding compound; a surface of the second post that is coupled with the second semiconductor die is exposed through the molding compound; and a surface of the third post that is coupled with the gate terminal of the IGBT, or with the gate terminal of the MOSFET is exposed through the molding compound.

In some aspects, the techniques described herein relate to a semiconductor device module, wherein: the first base portion of the second metal layer is coupled with a signal terminal of a leadframe of the semiconductor device module, the signal terminal being an emitter signal terminal, or a source signal terminal; the first base portion of the second metal layer is further coupled with a thermal sense signal pin of the leadframe; and the second base portion of the second metal layer is coupled with a gate signal pin of the leadframe.

In some aspects, the techniques described herein relate to a signal distribution assembly configured to conduct signals in a semiconductor device module, the signal distribution assembly including: a metal layer, the metal layer having: a first side, the first side being planar; and a second side opposite the first side, the second side being non-planar and including: a base portion; a first post extending from the base portion; and a second post extending from the base portion; and a molding compound disposed on the second side of the metal layer, an upper surface of the first post and an upper surface of the second post being exposed through the molding compound; and a thermally conductive ceramic layer coupled with the first side of the metal layer, the thermally conductive ceramic layer being coupled with the first side of the metal layer via a thermally conductive epoxy adhesive.

In some aspects, the techniques described herein relate to a signal distribution assembly, wherein: the base portion is a first base portion; the first base portion, the first post and the second post are included in a first portion of the metal layer; and the metal layer further includes a second portion having: a second base portion; and a third post extending from the second base portion, an upper surface of the third post being coupled being exposed through the molding compound.

In some aspects, the techniques described herein relate to a signal distribution assembly, wherein: the first portion of the metal layer further includes: a fourth post extending from the first base portion, an upper surface of the fourth post being exposed through the molding compound; and a fifth post extending from the first base portion, an upper surface of the fourth post being exposed through the molding compound; and the second portion of the metal layer further includes a sixth post extending from the second base portion, an upper surface of the sixth post being exposed through the molding compound.

In some aspects, the techniques described herein relate to a signal distribution assembly configured to conduct signals in a semiconductor device module, the signal distribution assembly including: a first metal layer, the first metal layer having: a first side, the first side being planar; and a second side opposite the first side, the second side being non-planar and including: a base portion; a first post extending from the base portion; and a second post extending from the base portion; and a thermally conductive insulator layer, a first surface of the thermally conductive insulator layer being coupled with the first side of the first metal layer; and a second metal layer coupled with a second surface of the thermally conductive insulator layer opposite the first surface of the thermally conductive insulator layer.

In some aspects, the techniques described herein relate to a signal distribution assembly, wherein: the base portion is a first base portion; the first base portion, the first post and the second post are included in a first portion of the first metal layer; and the first metal layer further includes a second portion having: a second base portion; and a third post extending from the second base portion.

In the drawings, which are not necessarily drawn to scale, like reference symbols may indicate like and/or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols shown in one drawing may not be repeated for the same, and/or similar elements in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings, but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of an element are illustrated.

This disclosure relates to implementations of semiconductor device assemblies including signal distribution assemblies (e.g., electrical interconnection appliances, or structures) that can improve thermal performance and reduce mechanical stresses in such assemblies, e.g., power transistor assemblies. For instance, in some implementations, a power transistor assembly can include a pre-molded electrical interconnect structure, or signal distribution assembly, where contact surfaces (of conductive posts for contacting semiconductor die and/or portions of a leadframe) are exposed through a molding compound that is used to pre-mold the structure. The pre-molded structure can then be coupled with a thermally conductive ceramic layer (e.g., using a thermally conductive adhesive, such as an epoxy). Such implementations can be referred to as substrate bonded ceramic (SBC) assemblies.

In some implementations, a signal distribution assembly with a metal-insulator-metal (MIM) stacked structure can be used, which can be referred to as MIM assemblies. As compared with SBC assemblies, MIM assemblies can exclude a molding compound, e.g., may not be pre-molded. Such signal distribution structures (e.g., SBC structures and/or MIM structures), as shown in the semiconductor device assemblies described herein, can improve thermal performance (reduce thermal resistance) by allowing for dual-sided cooling, which increases (e.g., can approximately double) heat spreading area as compared to current device assemblies with single-sided cooling. The implementations described herein can also achieve shorter thermal (and electrical) conduction paths (e.g., by, in part, eliminating use of conductive spacers), which also improves thermal performance (e.g., reduces thermal resistance), as well as improved mechanical performance, e.g., reduced mechanical stresses on the semiconductor die stress, as well as improved solder joint reliability due to mechanical flexibility of the disclosed SBC structures and MIM structures. As compared to current implementations of a power transistor assemblies for use in, e.g., electrical vehicle (EV) and/or hybrid-electric vehicle (HEV) electrical inverter applications, the approaches described herein can reduce thermal resistance (e.g., junction-to-case and/or junction-to-sink thermal resistance) by <NUM>% to <NUM>%. Further the approaches described herein, as compared to current approaches, can reduce die tensile stress by <NUM>-<NUM>%, which can reduce occurrence of die cracking, and also can improve die top solder joint reliability by <NUM>-<NUM>%, e.g., as a result of reducing die top strain density.

<FIG> is a diagram schematically illustrating a side view of a signal distribution assembly <NUM>. The example of <FIG> can be referred to as a SBC structure, such as described above. As shown in <FIG>, the signal distribution assembly <NUM> includes a pre-molded signal distribution assembly <NUM>, a ceramic layer <NUM> and an adhesive <NUM>. The pre-molded signal distribution assembly <NUM> can include a metal layer <NUM> and a molding compound <NUM> that is used to pre-mold the metal layer <NUM>. The metal layer <NUM> is shown in <FIG> for purposes of illustration (and context). In some implementations the metal layer <NUM> may not be visible in the view shown in <FIG>, as being obscured by the molding compound <NUM>.

In this example, the molding compound <NUM> can provide mechanical stability to the metal layer <NUM> (which can be less than <NUM> millimeter thick), while still allowing sufficient mechanical flexibility to reduce the occurrence of stresses within an associated semiconductor device assembly including the signal distribution assembly <NUM>. The ceramic layer <NUM> can be a thermally conductive, and electrically insulative layer, such as aluminum oxide (Al<NUM>O<NUM>), aluminum nitride (AlN), silicon nitride Si<NUM>N<NUM>, or a resin, such as polyimide, as some examples. The adhesive <NUM> can be used to couple the ceramic layer <NUM> to the pre-molded signal distribution assembly <NUM>. In some examples, the adhesive <NUM> can be a thermally conductive and electrically conductive epoxy, such as a silver-filled epoxy, as one example. In other implementations, the adhesive <NUM> can be a thermally conductive, but electrically insulative adhesive material, e.g., a thermal interface material.

<FIG> is a diagram illustrating a plan view (e.g., bottom-side plan view) of a signal distribution portion (e.g., the metal layer <NUM>) of the assembly <NUM> of <FIG>. As shown in <FIG>, the metal layer <NUM>, in this example, includes a base portion <NUM>, a post <NUM>, a post <NUM>, a post <NUM> and a post <NUM>, where each of the posts <NUM>-<NUM> extends away (e.g., out of the page) from the base portion <NUM>, such as is further illustrated in, at least, <FIG>.

As can be seen from a comparison of <FIG>, the portion of the metal layer <NUM> shown in <FIG> (e.g., exposed through the molding compound <NUM>) corresponds with the post <NUM>. In some implementations, the metal layer <NUM> can be formed from a metal sheet, where etching or other process can be performed on the metal sheet to form the base portion <NUM> and the posts <NUM>-<NUM>. In some implementations, the metal layer <NUM> can be formed using one or more deposition processes, and/or sputtering processes. In some implementations, the metal layer <NUM> can be formed from copper, aluminum-copper, copper-molybdenum, and/or one or more other electrically conductive materials. In this example, the metal layer <NUM> is monolithic. In other words, the base portion <NUM> and the posts <NUM>-<NUM> are included a unitary structure, which can eliminate the use of electrically conductive spacers and, as a result, reduce the reliability issues associated with such spacers.

<FIG> is a diagram illustrating a side view of the metal layer <NUM> of <FIG>. In this example, the metal layer <NUM> is viewed along the direction V1 shown in <FIG>. In the view shown in <FIG>, the post <NUM>, the post <NUM> and the post <NUM> are shown as extending away from the base portion <NUM>. As also shown in <FIG>, the metal layer <NUM> has a first side S1 and a second side S2. In this example, the side S <NUM> is planar, which facilitates coupling the pre-molded signal distribution assembly <NUM> with the ceramic layer <NUM> (e.g., using the adhesive <NUM>) to produce the signal distribution assembly <NUM>. Further in this example, the side S2 is non-planar, with the posts <NUM>-<NUM> extending away from the base portion <NUM>.

<FIG> is a diagram illustrating a plan-view the metal layer <NUM> of <FIG> after pre-molding with the molding compound <NUM> and attaching the ceramic layer <NUM> to form the pre-molded signal distribution assembly <NUM> of <FIG>. In an example implementation, the metal layer <NUM> can be placed (and/or formed) in a molding jig, and then a transfer molding process (or other molding encapsulation process) can be performed to apply the molding compound <NUM> to the side S2 of the metal layer <NUM>. As shown in <FIG>, after this molding process, respective upper surfaces of the posts <NUM>-<NUM> are exposed through the molding compound <NUM>, e.g., using film assisted molding technology. In some implementations, these upper surfaces can be exposed by controlling a volume of the molding compound <NUM> applied to the side S2 of the metal layer <NUM>, such that the upper surfaces of the posts are not encapsulated in the molding compound <NUM>. In other implementations, a grinding process can be performed to expose the upper surfaces of the posts <NUM>-<NUM> through the molding compound <NUM> after the molding process.

In an example implementation, the signal distribution assembly <NUM> can be included in a power transistor device assembly including a power transistor, such as an insulated-gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET), and a fast-recovery diode (FRD). Depending on the particular implementation, the power transistor and/or the FRD can be implemented in silicon, silicon carbide, gallium nitride, gallium arsenide, or any appropriate semiconductor material. In some implementations, the exposed surfaces of the post <NUM> and the post <NUM> can be coupled with the power transistor, e.g. with a collector terminal of an IGBT or a source terminal of a MOSFET. Further, an exposed surface of the post <NUM> can be coupled with a cathode terminal of the FRD, such that the metal layer <NUM> electrically couples the power transistor (emitter or source) with the FRD (cathode). Still further, the post <NUM> can be coupled with a signal blade (signal terminal, signal lead, etc.) of a leadframe included in the corresponding power transistor assembly. Such an example is illustrated in <FIG>.

In some implementations, the arrangement of posts on the base portion <NUM>, as well as shape and dimensions of the base portion <NUM>, can vary. As an example, in some implementations, a single post (e.g., larger post) can replace the posts <NUM> and <NUM>.

<FIG> is a diagram illustrating a plan view (e.g., bottom-side plan view) of another signal distribution portion (e.g., a metal layer 112a) of an SBC structure. As shown in <FIG>, the metal layer 112a, similar to the metal layer <NUM> of <FIG>, includes (e.g. monolithically) a base portion <NUM>, a post <NUM>, a post <NUM>, a post <NUM>, a post <NUM>, and a post <NUM>, where each of the posts <NUM>-<NUM> extends away (e.g., out of the page) from the base portion <NUM>, similar to the posts <NUM>-<NUM> of the metal layer <NUM>. The metal layer 112a also includes a base portion <NUM>, a post <NUM> and a post <NUM>, which are physically separate, and electrically isolated from the base portion <NUM>, and the posts <NUM>-<NUM>, and can also be monolithic. That is, as shown in <FIG>, the base portion <NUM> and the posts <NUM>-<NUM> are included in a first portion of the metal layer 112a, while the base portion <NUM> and the posts <NUM>-<NUM> are included in a second portion of the metal layer 112a.

<FIG> is a diagram illustrating the metal layer 112a of <FIG> after pre-molding with a molding compound 114a and attachment of a ceramic layer (such as the ceramic layer <NUM>) to form the signal distribution assembly <NUM> (e.g., an SBC structure) similar to the signal distribution assembly <NUM> of <FIG>. In an example implementation, the metal layer 112a can be placed (and/or formed) in a molding jig, and then a transfer molding process (or other molding encapsulation process) can be performed to apply the molding compound 114a to a side of the metal layer <NUM> including the posts <NUM>-<NUM> and the posts <NUM>-<NUM> (e.g., covering the visible parts of the base portion <NUM> and base portion <NUM>, e.g., using film assisted molding. As shown in <FIG>, after this molding process, respective upper surfaces of the posts <NUM>-<NUM> and the posts <NUM>-<NUM> are exposed through the molding compound 114a. In some implementations, these upper surfaces can be exposed by controlling a volume of the molding compound 114a applied, such that the upper surfaces are not encapsulated in the molding compound 114a. In other implementations, a grinding process can be performed to expose the upper surfaces of the posts <NUM>-<NUM> and the posts <NUM>-<NUM> through the molding compound 114a after the molding process.

In an example implementation, the signal distribution assembly 100a can be included in a power transistor device assembly including a power transistor, such as an IGBT or a MOSFET, and a FRD. Depending on the particular implementation, the power transistor and/or the diode can be implemented in silicon, silicon carbide, gallium nitride, gallium arsenide, or any appropriate semiconductor material. In an example implementation, the exposed surfaces of the post <NUM> and the post <NUM> can be coupled with the power transistor, e.g. with a collector terminal of an IGBT or a source terminal of a MOSFET. Further, the post <NUM> can be coupled with a cathode terminal of the FRD, and the metal layer 112a can electrically couple the power transistor (emitter or source) with the FRD (cathode). Still further, the post <NUM> can be coupled with a signal blade (signal terminal, signal lead, etc.) of a leadframe included in the corresponding power transistor assembly, and the post <NUM> can be coupled with a thermal sense signal pin of the leadframe. Also, the post <NUM> can be coupled with a gate terminal of the corresponding power transistor semiconductor die, and the post <NUM> can be coupled with a gate signal pin of the leadframe. Such an example is illustrated in <FIG>.

In some implementations, the arrangement of respective posts on the base portion <NUM> and the base portion <NUM>, as well as respective shapes and dimensions of the base portion <NUM> and the base portion <NUM>, can vary. As an example, in some implementations, the base portion <NUM> may be a straight metal trace, can include additional corners, or bends to route a gate signal from the corresponding signal pin of an associated leadframe to a gate pad on the semiconductor die including an associated power transistor, as is appropriate for the particular implementation.

<FIG> is a diagram schematically illustrating a side view of a signal distribution assembly <NUM>. The example of <FIG> can be referred to as a MIM structure, such as described above. As shown in <FIG>, the signal distribution assembly <NUM> includes a metal layer <NUM>, a metal layer <NUM> and an insulator layer <NUM>. In some implementations, the metal layer <NUM> and the metal layer <NUM> can be coupled to respective sides of the insulator layer <NUM> using active metal brazing (AMB), sintering, plating, etc. As compared with pre-molded signal distribution assembly <NUM> and the metal layer <NUM>, the metal layer <NUM> exclude pre-molding. In this example, structural support for the <NUM> (and the metal layer <NUM>) is provided by the insulator layer <NUM>, while still allowing sufficient mechanical flexibility to reduce the occurrence of stresses within an associated semiconductor device assembly including the signal distribution assembly <NUM>. The insulator layer <NUM> can be a thermally conductive, and electrically insulative layer, such as tetraethyl orthosilicate (TEOS). can be a thermally conductive, and electrically insulative layer, such as aluminum oxide (Al<NUM>O<NUM>), aluminum nitride (AlN), silicon nitride Si<NUM>N<NUM>, silicon dioxide (SiO<NUM>), a resin, such as polyimide, or an epoxy, as some examples.

In this example, <FIG>, with further reference to <FIG>, is a diagram illustrating a side view of the signal distribution assembly <NUM> viewed along the direction V2 shown in <FIG>. In the view shown in <FIG>, the post <NUM> and the post <NUM> are shown as extending away from the base portion <NUM>. As also shown in <FIG>, the metal layer <NUM> has a first side S3 and a second side S3. In this example, the side S3 is planar, which can facilitate coupling the metal layer <NUM> with the insulator layer <NUM>. Further in this example, the side S4 of the metal layer <NUM> is non-planar, with, as shown in <FIG>, post <NUM> and post <NUM> extending away from the base portion <NUM>, e.g., out of the paper in <FIG>.

<FIG> is a diagram illustrating a plan view (e.g., bottom-side plan view) of the signal distribution assembly <NUM> of <FIG>. As shown in <FIG>, the side S4 of the metal layer <NUM>, in this example, includes the base portion <NUM>, and the posts <NUM>-<NUM>, where each of the posts <NUM>-<NUM> extends away (e.g., out of the page) from the base portion <NUM>.

In some implementations, the metal layer <NUM> can be formed from a metal sheet, where etching or other process can be performed on the metal sheet to form the base portion <NUM> and the posts <NUM>-<NUM>. In some implementations, the metal layer <NUM> can be formed using one or more deposition processes, and/or sputtering processes. In some implementations, the metal layer <NUM> can be formed from copper, aluminum-copper, copper-molybdenum, and/or one or more other electrically conductive materials. In this example, the metal layer <NUM> is monolithic. In other words, the base portion <NUM> and the posts <NUM>-<NUM> are included a unitary structure, which can eliminate the use of electrically conductive spacers and, as a result, reduce the reliability issues associated with such spacers.

In an example implementation, the signal distribution assembly <NUM> can be included in a power transistor device assembly including a power transistor, such as an insulated-gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET), and a fast-recovery diode (FRD). Depending on the particular implementation, the power transistor and/or the FRD can be implemented in silicon, silicon carbide, gallium nitride, gallium arsenide, or any appropriate semiconductor material. In some implementations, respective upper surfaces of the post <NUM> and the post <NUM> (e.g., the surfaces shown in <FIG>) can be coupled with the power transistor, e.g. with a collector terminal of an IGBT or a source terminal of a MOSFET. Further, an upper surface of the post <NUM> (e.g., the surface shown in <FIG>) can be coupled with a cathode terminal of the FRD, such that the metal layer <NUM> electrically couples the power transistor (emitter or source) with the FRD (cathode). Still further, the base portion <NUM> can be coupled, e.g., near an edge <NUM>, with a signal blade (signal terminal, signal lead, etc.) of a leadframe included in the corresponding power transistor assembly. Such an example is similar to the implementation of <FIG>.

In some implementations, the arrangement of posts on the base portion <NUM>, as well as shape and dimensions of the base portion <NUM>, can vary. As an example, in some implementations, a single post (e.g., larger post) can replace the posts <NUM> and <NUM> and/or the size and shape of the base layer <NUM> can be changed.

<FIG> is a diagram illustrating a plan view (e.g., bottom-side plan view) of another signal distribution assembly 200a. As shown in <FIG>, a metal layer 210a, (which is similar to, and could be implemented in place of the metal layer <NUM> of <FIG>), includes a base portion <NUM>, a post <NUM>, a post <NUM>, and a post <NUM>, where each of the posts <NUM>-<NUM> extends away (e.g., out of the page) from the base portion <NUM>. The metal layer 210a also includes a base portion <NUM>, and a post <NUM>, which are physically separate, and electrically isolated from the base portion <NUM>, and the posts <NUM>-<NUM>. That is, as shown in <FIG>, the base portion <NUM> and the posts <NUM>-<NUM> are included in a first portion of the metal layer <NUM>, while the base portion <NUM> and the post <NUM> are included in a second portion of the metal layer 210a.

In an example implementation, the signal distribution assembly 200a can be included in a power transistor device assembly including a power transistor, such as an insulated-gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET), and a fast-recovery diode (FRD). Depending on the particular implementation, the power transistor and/or the FRD can be implemented in silicon, silicon carbide, gallium nitride, gallium arsenide, or any appropriate semiconductor material. In some implementations, respective upper surfaces of the post <NUM> and the post <NUM> (e.g., the surfaces shown in <FIG>) can be coupled with the power transistor, e.g. with a collector terminal of an IGBT or a source terminal of a MOSFET. Further, an upper surface of the post <NUM> (e.g., the surface shown in <FIG>) can be coupled with a cathode terminal of the FRD, such that the metal layer 210a electrically couples the power transistor (emitter or source) with the FRD (cathode). Still further, the base portion <NUM> can be coupled, e.g., near an edge <NUM>, with a signal blade (signal terminal, signal lead, etc.) of a leadframe included in the corresponding power transistor assembly, and also coupled, e.g., near and edge <NUM>, with a thermal sense signal pin of the leadframe. Also, the post <NUM> can be coupled with a gate terminal of the corresponding power transistor semiconductor die, and the base portion <NUM>, e.g., near and edge <NUM>, can be coupled with a gate signal pin of the leadframe. Such an example is similar to the implementation illustrated in <FIG>.

In some implementations, the arrangement of respective posts on the base portion <NUM> and the base portion <NUM>, as well as respective shapes and dimensions of the base portion <NUM> and the base portion <NUM>, can vary. As an example, in some implementations, the base portion <NUM> may not be a straight metal trace, but rather may include corners, or bends to route a gate signal from the corresponding signal pin of an associated leadframe to a gate pad on the semiconductor die including an associated power transistor.

<FIG> is a flow diagram illustrating a portion of a method for a producing a semiconductor device module <NUM> including the signal distribution assembly <NUM> of <FIG>. A similar flow can be used to produce a semiconductor device module using the signal distribution assembly <NUM> of <FIG> in place of the signal distribution assembly <NUM>. For purposes of brevity, that flow (e.g., for the signal distribution assembly <NUM>) is not shown here.

In this example, referring first to the left portion of <FIG>, the semiconductor device module <NUM> can include a substrate <NUM>, which can be a DBM substrate. The substrate <NUM> can include a top metal layer <NUM>, which can be a copper layer, or other metal layer. As shown in <FIG>, a semiconductor die <NUM> and a semiconductor die <NUM> can be coupled with the top metal layer <NUM> of the substrate <NUM>, e.g., via a soldering reflow process, a sintering process, or other appropriate process. A blade signal terminal <NUM> (of a leadframe) can also be coupled with the top metal layer <NUM> using the same process operations (solder, sinter, etc.) used to attach the semiconductor die <NUM> and the semiconductor die <NUM> to the top metal layer <NUM>.

In this example, the semiconductor die <NUM> can include a power transistor, such as an IGBT or a MOSFET, and the semiconductor die <NUM> can include a FRD. In this example, the top metal layer <NUM> of the substrate <NUM>, as well as the blade signal terminal <NUM>, are electrically coupled with a collector terminal (for an IGBT included in the semiconductor die <NUM>) or a drain terminal (for a MOSFET included in the semiconductor die <NUM>), as well as anode for the FRD included in the semiconductor die <NUM>. That is, the top metal layer <NUM> electrically couples both the power transistor (collector or drain) and the FRD (anode) with the blade signal terminal <NUM>.

As further shown in <FIG>, a solder print or dispense operation can be performed to form a solder portion <NUM>, a solder portion <NUM>, and a solder portion <NUM>, which respectively correspond with the posts <NUM>-<NUM> of the signal distribution assembly <NUM>. That is, the signal distribution assembly <NUM> can be flipped and placed on the solder portions <NUM>-<NUM>, such that the posts <NUM>-<NUM> align with their respective solder portions. Further, the post <NUM> of the signal distribution assembly <NUM> can align with a corresponding solder portion (not shown in <FIG>) that is disposed on a blade terminal <NUM> (of the leadframe). A solder reflow process can then be performed to couple the signal distribution assembly <NUM> to the semiconductor die <NUM>, the semiconductor die <NUM> and the blade terminal <NUM> (via the respective posts of the signal distribution assembly <NUM>).

As also shown in <FIG>, the leadframe of the semiconductor device module <NUM> can also include a signal pin <NUM> (e.g., a gate signal pin) and a signal pin <NUM> (e.g., a thermal sense signal pin), which can be coupled with the semiconductor die <NUM>, respectively, via a wire bond 370a and a wire bond 372a.

<FIG> is a flow diagram illustrating a portion of a method for a producing a semiconductor device module <NUM> including the signal distribution assembly 100a of <FIG>. A similar flow can be used to produce a semiconductor device module using the signal distribution assembly 200a of <FIG> in place of the signal distribution assembly 100a. For purposes of brevity, that flow (e.g., for the signal distribution assembly 200a) is not shown here.

As further shown in <FIG>, a solder print or dispense operation can be performed to form a solder portion <NUM>, a solder portion <NUM>, a solder portion <NUM>, and a solder portion <NUM>, which respectively correspond with the posts <NUM>, <NUM>, <NUM> and <NUM> of the signal distribution assembly 100a. That is, the signal distribution assembly 100a can be flipped and placed on the solder portions <NUM>, <NUM>, <NUM> and <NUM>, such that the posts <NUM>, <NUM>, <NUM> and <NUM> align with their respective solder portions. Further, the post <NUM> of the signal distribution assembly 100a can align with a corresponding solder portion (not shown in <FIG>) that is disposed on a blade terminal <NUM>. Still further, the posts <NUM> and <NUM> of the signal distribution assembly 100a can align with respective solder portions (not shown in <FIG>) that are disposed on a signal pin <NUM> (e.g., a thermal sense signal pin) and a signal pin <NUM> (e.g., a gate signal pin) of the leadframe. A solder reflow process can then be performed to couple the signal distribution assembly 100a to the semiconductor die <NUM>, the semiconductor die <NUM>, the blade terminal <NUM>, the signal pin <NUM> and the signal pin <NUM> (via the respective posts of the signal distribution assembly 100a). In this implementation, as compared to the implementation of <FIG>, the wire bond 370a and the wire bond 372a are replaced by signal routing implemented in the signal distribution assembly 100a.

<FIG> is a side view (e.g., a cross-sectional view) of a semiconductor device module <NUM> including a signal distribution assembly (an SBC structure), such the signal distribution assembly <NUM> of <FIG>. That is, for purposes of illustration, the semiconductor device module <NUM> is described as including the signal distribution assembly <NUM>, though could include other signal distribution assembly implementations. In this example, the semiconductor device module <NUM> includes a substrate <NUM> (e.g., a DBM substrate), the signal distribution assembly <NUM>, a semiconductor die <NUM> (e.g., including a power transistor) and a semiconductor die <NUM> (e.g., including a FRD). A dashed line 500a in <FIG> defines an inset 500a, for which a magnified view is shown in <FIG>. That is the inset 500a includes the arrangement of elements for the semiconductor device module <NUM> corresponding with the semiconductor die <NUM> (where the stack associated with the semiconductor die <NUM> would be the same or similar).

Referring to <FIG>, illustrating the magnified view of the inset 500a shown in <FIG>, the substrate <NUM> includes a metal layer <NUM> (e.g., top metal layer) a ceramic layer <NUM>, and a metal layer <NUM> (e.g., bottom metal layer), which can be used for bottom-side cooling of the semiconductor device module <NUM>. As also shown in <FIG>, and as described above, the signal distribution assembly <NUM> includes the metal layer <NUM>, the molding compound <NUM>, the ceramic layer <NUM> (which can be used for top-side cooling of the semiconductor device module <NUM>), and the adhesive <NUM>. In example of the inset 500a, the base portion <NUM> and the post <NUM> of the metal layer <NUM> are illustrated. As shown in <FIG>, the semiconductor die <NUM> is coupled with the metal layer <NUM> of the substrate <NUM> using a layer <NUM>, which can be a solder layer or a sinter layer. Further as shown in <FIG>, the post <NUM> is coupled with the semiconductor die <NUM> using a layer <NUM>, which can be a solder layer or sinter layer.

In a specific, non-limiting example, the elements of the semiconductor device module <NUM> shown in <FIG> can have thicknesses, along the line T1, as specified below. Of course, in other implementations, other thicknesses can be used, and the following discussion is provided by way of example and for purposes of illustration. For clarity, the example thickness (along the line T1) for each of the elements shown in <FIG> are listed, generally, from the top of the semiconductor device module <NUM> to the bottom of the semiconductor device module <NUM>.

In this example, for the signal distribution assembly <NUM>, the ceramic layer <NUM> can have a thickness of approximately <NUM>, the adhesive <NUM> can have a thickness of approximately <NUM>, and the metal layer <NUM> can have an overall thickness of approximately <NUM>, e.g., less than <NUM>. For the metal layer <NUM>, the base portion <NUM> can have a thickness of approximately <NUM> and the post <NUM> can have a thickness (height from the base portion <NUM>) of approximately <NUM>, e.g., both less than <NUM>. It is noted that the other posts of the metal layer <NUM> can have a same height. Further in this example, the molding compound <NUM> of the signal distribution assembly <NUM> can have a thickness of approximately <NUM> (or about a same thickness, or a slightly smaller thickness that the height of the post <NUM>), so that the post <NUM> is exposed through the <NUM>.

Still further in this example, the layer <NUM> can have a thickness of approximately <NUM>, the semiconductor die <NUM> can have a thickness of approximately <NUM>, and the layer <NUM> can have a thickness of approximately <NUM>. For the substrate <NUM> in this example, the metal layer <NUM> can have a thickness of approximately <NUM>, the ceramic layer <NUM> can have a thickness of approximately <NUM>, and the metal layer <NUM> can have a thickness of approximately <NUM>.

<FIG> is a side view (e.g., a cross-sectional view) of a semiconductor device module <NUM> including a signal distribution assembly (a MIM structure), such the signal distribution assembly <NUM> of <FIG>. that is, for purposes of illustration, the semiconductor device module <NUM> is described as including the signal distribution assembly <NUM>, though could include other signal distribution assembly implementations. In this example, the semiconductor device module <NUM> includes a substrate <NUM> (e.g., a DBM substrate), the signal distribution assembly <NUM>, a semiconductor die <NUM> (e.g., including a power transistor) and a semiconductor die <NUM> (e.g., including a FRD). A dashed line 600a in <FIG> defines an inset 600a, for which a magnified view is shown in <FIG>. That is the inset 600a includes the arrangement of elements for the semiconductor device module <NUM> corresponding with the semiconductor die <NUM> (where the stack associated with the semiconductor die <NUM> would be the same or similar).

Referring to <FIG>, illustrating the magnified view of the inset 600a shown in <FIG>, the substrate <NUM> includes a metal layer <NUM> (e.g., top metal layer) a ceramic layer <NUM>, and a metal layer <NUM> (e.g., bottom metal layer), which can be used for bottom-side cooling of the semiconductor device module <NUM>. As also shown in <FIG>, and as described above, the signal distribution assembly <NUM> includes the metal layer <NUM>, the insulator layer <NUM>, and the metal layer <NUM> (which can be used for top-side cooling of the semiconductor device module <NUM>). In example of the inset 600a, the base portion <NUM> and the post <NUM> of the metal layer <NUM> are illustrated. As shown in <FIG>, the semiconductor die <NUM> is coupled with the metal layer <NUM> of the substrate <NUM> using a layer <NUM>, which can be a solder layer or a sinter layer. Further as shown in <FIG>, the post <NUM> is coupled with the semiconductor die <NUM> using a layer <NUM>, which can be a solder layer or sinter layer.

In a specific, non-limiting example, the elements of the semiconductor device module <NUM> shown in <FIG> can have thicknesses, along the line T2, as specified below. Of course, in other implementations, other thicknesses can be used, and the following discussion is provided by way of example and for purposes of illustration. For clarity, the example thickness (along the line T2) for each of the elements shown in <FIG> are listed, generally, from the top of the semiconductor device module <NUM> to the bottom of the semiconductor device module <NUM>.

In this example, for the signal distribution assembly <NUM>, the metal layer <NUM> can have a thickness of approximately <NUM>, and the insulator layer <NUM> can have a thickness of approximately <NUM>. Further, the metal layer <NUM> can have an overall thickness of approximately <NUM>, e.g., less than <NUM>. For the metal layer <NUM>, the base portion <NUM> can have a thickness of approximately <NUM> and the post <NUM> can have a thickness (height from the base portion <NUM>) of approximately <NUM>. It is noted that the other posts of the metal layer <NUM> can have a same height.

<FIG> is a flowchart illustrating a method <NUM> for producing a semiconductor device module including a signal distribution assembly, such as the assemblies of <FIG> or <FIG>. In the method <NUM>, block <NUM> includes preparing or providing a signal distribution assembly, such as an SBC structure or a MIM structure, as those described herein with respect to <FIG>. At block <NUM>, the method <NUM> includes coupling a power transistor (e.g., a collector terminal of an IGBT or a drain terminal of a MOSFET), a FRD (e.g., an anode terminal) and one or more leadframe portions to a substrate, such as on a metal layer of a DBM substrate as in the examples of <FIG> and <FIG>. At block <NUM>, if signal distribution assembly excludes gate and/or thermal sense signal routing and/or associated conductive posts, the method <NUM> includes forming respective wire bond(s) to provide electrical connections from respective signal terminals (signal pins, etc.) of the leadframe to a gate terminal and/or a thermal sense terminal (e.g., on a surface of the power transistor semiconductor die). At block <NUM>, the method <NUM> includes coupling the signal distribution assembly of block <NUM> to the semiconductor die and to one or more respective portions of the leadframe. In some implementations, the operation at block <NUM> can be done with a first solder and the operation at block <NUM> can be done with a second solder, where the second solder has a lower melting point than the first solder, e.g., to prevent unwanted reflow of solder used at block <NUM>. In some implementations, the operations at blocks <NUM> and <NUM> can include sintering operations, such as silver sintering. At block <NUM>, the method <NUM> includes encapsulating the produced semiconductor device assembly in a molding compound, where a surface of the signal distribution structure is exposed through a first surface of the molding compound and a surface of the substrate of block <NUM> is exposed through a second surface of the molding compound.

It will be understood that, in the foregoing description, when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

Claim 1:
A signal distribution assembly (<NUM>) configured to conduct signals in a semiconductor device module, the signal distribution assembly (<NUM>) comprising:
a first metal layer (<NUM>), the first metal layer (<NUM>) having:
a first side, the first side being planar; and
a second side opposite the first side, the second side being non-planar and including:
a base portion (<NUM>);
a first post (<NUM>) extending from the base portion (<NUM>); and
a second post (<NUM>) extending from the base portion (<NUM>); and
a thermally conductive insulator layer (<NUM>), a first surface of the thermally conductive insulator layer (<NUM>) being coupled with the first side of the first metal layer (<NUM>); and
a second metal layer (<NUM>) coupled with a second surface of the thermally conductive insulator layer (<NUM>) opposite the first surface of the thermally conductive insulator layer (<NUM>),
characterized in that
the signal distribution assembly (<NUM>) is pre-molded and comprises a molding compound disposed on the second side of the first metal layer (<NUM>), an upper surface of the first post (<NUM>) and an upper surface of the second post (<NUM>) being exposed through the molding compound.