Patent Description:
Even though nanopore-based sequencing sensor chips have been successful in some applications, improvements are still desirable. For example, there is a need for improved nanopore well structures and methods.

Embodiments are directed to nanopore cells that include a well having a working electrode at a bottom of the well. The well may be formed within a dielectric layer, where the sidewalls of the well may be formed of the dielectric or other materials coating the walls of the dielectric layer. Various embodiments may use different materials having different hydrophobicity and hydrophilicity to provide desired properties of the cell. In operation, the nanopore cell may have a membrane formed over the well, where the nanopore can be inserted into the membrane. A shape of the well can impact the properties and ability to form the membrane, which can further impact the ease of performing measurements with the nanopore cell. Various techniques can be used for providing a desired shape and other properties (e.g., of materials forming the well).

According to the embodiments, a nanopore cell includes a substrate, a conductive layer disposed overlying a top portion of the substrate, and a first dielectric layer overlying the conductive layer. The first dielectric layer has an opening exposing a portion of the conductive layer. An electrode layer maybe disposed in the opening of the first dielectric layer. The electrode layer has an overhang portion extending over the first dielectric layer. Further, a second dielectric layer is disposed on the first dielectric layer, and a cavity is formed in the second dielectric layer. The cavity exposes a portion of the electrode layer. Further, the cavity includes an undercut portion of the second dielectric layer above the overhang portion of the electrode. The nanopore device includes a well formed by the cavity. The well has a bottom base formed by a top surface of the electrode layer and well sidewalls formed by the second dielectric layer.

According to an embodiment, a shape of the well can include aspects of a corner between a top surface of the dielectric layer and the well sidewall. The corner can be characterized by a radius of curvature r, and an angle between the top surface of the dielectric layer and the well sidewall is characterized by an angle θ. The values for the curvature r and angle θ can be selected to provide desired properties of the well, thereby providing desired properties of the nanopore cell.

Some embodiments may include a nanopore cell that includes a substrate, a conductive layer disposed in a top portion of the substrate, a porous titanium nitride (TiN) electrode layer disposed on the conductive layer, a first dielectric layer disposed on the porous TiN electrode layer, and a polyimide layer disposed on the first dielectric layer. A cavity is formed in the polyimide layer and the first dielectric layer, and the cavity exposes a portion of the porous TiN electrode layer. A well is formed by the cavity on the exposed portion of the porous TiN electrode layer, and the well has a bottom base formed by a top surface of the porous TiN electrode layer and well sidewalls of the stacked polyimide layer over the first dielectric layer.

Some embodiments may include a nanopore cell. The nanopore cell includes a substrate, a conductive layer disposed in a top portion of the substrate, a porous titanium nitride (TiN) electrode layer disposed on the conductive layer, a polyimide layer disposed on the porous titanium nitride (TiN) electrode layer. The nanopore cell also includes a cavity in the polyimide layer, and the cavity exposes a portion of the TiN electrode layer. Further, a well is formed by the cavity on the exposed portion of the TiN electrode layer. The well has a bottom base of the TiN electrode layer and well sidewalls of the polyimide layer. Further, the polyimide sidewalls have a reentrant profile.

Some embodiments may include a nanopore cell includes a substrate, a conductive layer disposed in a top portion of the substrate, an electrode layer disposed on the conductive layer, a dielectric layer disposed on the electrode layer. A cavity in the dielectric layer, and the cavity exposes a portion of the electrode layer. A well is formed by the cavity on the exposed portion of the electrode layer, and the well has the exposed portion of the electrode layer as a bottom base and sidewalls extending from a top opening to the bottom base forming a reentrant profile. Further, the bottom base is wider than the top opening.

Thus, the present invention provides a nanopore cell, comprising a substrate; a conductive layer disposed overlying a top portion of the substrate; a first dielectric layer overlying the conductive layer, the first dielectric layer having an opening exposing a portion of the conductive layer; an electrode layer disposed in the opening of the first dielectric layer, the electrode layer having an overhang portion extending over the first dielectric layer; a second dielectric layer disposed on the first dielectric layer; a cavity in the second dielectric layer, the cavity exposing at least a portion of the electrode layer, the cavity including an undercut portion of the second dielectric layer above the overhang portion of the electrode; and a well formed by the cavity, the well having a bottom base formed by a top surface of the electrode layer and well sidewalls formed by the second dielectric layer. The electrode layer may comprise porous TiN (titanium nitride). The second dielectric layer comprises polyimide or an organic material. The first dielectric layer may comprise an oxide layer. The overhang portion may have a length in a range of <NUM> to <NUM>. The undercut portion may have a length in a range of <NUM> to <NUM>. The well may have a width in a range of <NUM> to <NUM> and a depth in a range of <NUM> to <NUM>.

The present invention also provides a nanopore cell, comprising a substrate; a conductive layer disposed in a top portion of the substrate; an electrode layer disposed on the conductive layer; a dielectric layer disposed on the electrode layer; a cavity in the dielectric layer, the cavity exposing a portion of the electrode layer; and a well formed in the cavity, the well having a well sidewall formed by the dielectric layer and a well bottom on the exposed portion of the electrode layer; wherein a corner between a top surface of the dielectric layer and the well sidewall is characterized by a radius of curvature r, and an angle between the top surface of the dielectric layer and the well sidewall is characterized by an angle θ. The well sidewall may have a reentrant profile, which may be concave. The angle θ may be less than <NUM>° or even less than <NUM>°. The angle θ may also be substantially <NUM>°. and the radius of curvature r may then be less than <NUM>. The angle θ may also be greater than <NUM>°. The well bottom amy be hydrophilic and the well sidewall may be hydrophobic. Also, a lower portion of the well sidewall may be hydrophilic, and an upper portion of the well sidewall may be hydrophobic. Also, the well bottom may be hydrophilic, the well sidewall may be hydrophilic, and the top surface of the dielectric layer may be hydrophobic. The well sidewall may have a reentrant profile, wherein the well bottom is hydrophilic and the well sidewall is hydrophobic. The electrode layer may extend to cover a lower portion of the well sidewalls.

The present invention further provides a nanopore cell, comprising a substrate; a conductive layer disposed in a top portion of the substrate; an electrode layer disposed on the conductive layer; a dielectric layer disposed on the electrode layer; a cavity in the dielectric layer, the cavity exposing a portion of the electrode layer; and a well formed by the cavity on the exposed portion of the electrode layer, the well having the exposed portion of the electrode layer as a bottom base and sidewalls extending from a top opening to the bottom base forming a reentrant profile, wherein the bottom base is wider than the top opening. The electrode layer may comprise a porous electrode layer, which may be a porous TiN electrode layer. The dielectric layer may comprise a polyimide layer, and/or a hydrophobic surface.

The angle between the top surface of the well and the well sidewalls may be characterized by an angle θ less than <NUM>°, or even less than <NUM>°. The corner between a top surface of the well and the well sidewall may be characterized by a radius of curvature r less than <NUM>, or even less than <NUM>.

A "nanopore" refers to a pore, channel or passage formed or otherwise provided in a membrane. A membrane can be an organic membrane, such as a lipid bilayer, or a synthetic membrane, such as a membrane formed of a polymeric material. The nanopore can be disposed adjacent or in proximity to a sensing circuit or an electrode coupled to a sensing circuit, such as, for example, a complementary metal oxide semiconductor (CMOS) or field effect transistor (FET) circuit. In some examples, a nanopore has a characteristic width or diameter on the order of <NUM> nanometers (nm) to about <NUM>. Some nanopores are proteins.

A "well" in a nanopore device refers to a structure formed by insulating walls and a working electrode into which an electrolyte may be contained. A "well profile" refers to a structural description of the well and can include measures of an angle and a sharpness of a well edge. A "cell" of a nanopore device can include at various stages of operation: a well, a nanopore (e.g., in a membrane across the well), and a working electrode, as well as other circuitry, e.g., data acquisition circuitry.

A "dielectric material" refers to an electrical insulator that can be polarized by an applied electric field. When a dielectric is placed in an electric field, electric charges do not flow through the material as they do in a conductor, but only slightly shift from their average equilibrium positions causing dielectric polarization. A "conductive layer" refers to a layer of material that allows the flow of an electrical current in one or more directions. A metal wire is a common electrical conductor.

A "porous material" refers to a material that contains pores or voids at a surface of the material. A "spongy material" refers to a material having an open, porous structure.

In a nanopore device, a membrane can be formed over a well in a dielectric layer. For example, the membrane can include a lipid monolayer formed on top of the dielectric layer. As the membrane reaches the opening of well, the lipid monolayer can transition to a lipid bilayer that spans across the opening of the well. The shape of the well and the materials that form the well can perform important roles in the formation of the membrane and the insertion of the nanopore in the membrane. Further, the interaction between the materials forming the well can also affect the operation of the nanopore device.

The description below includes an overview of a structure and operation of nanopore cells. The impact of the shape of the well and the materials that form the well are also discussed. The problems caused by the interaction between a porous dielectric material and a porous working electrode are also described, along with proposed solutions.

This section includes an introduction to the operation of a nanopore cell, cell structure and usage, and circuitry for measuring signal. The capacitive effects at a working electrode (referred to as a double layer capacitance) are explained, and an example process of constructing a porous working electrode for improving the measurement is described.

<FIG> illustrates an embodiment of a cell <NUM> in an array of cells that form a nanopore-based sequencing chip. A membrane <NUM> is formed over the surface of the cell. In some embodiments, membrane <NUM> is a lipid bilayer. The bulk electrolyte <NUM> containing protein nanopore transmembrane molecular complexes (PNTMC) and the analyte of interest (e.g., a single polymer molecule, such as DNA) can be placed directly onto the surface of the cell. A single PNTMC <NUM> can be inserted into membrane <NUM> by electroporation. The individual membranes in the array are neither chemically nor electrically connected to each other. Thus, each cell in the array is an independent sequencing machine, producing data unique to the single polymer molecule associated with the PNTMC. PNTMC <NUM> can modulate the ionic current through the otherwise impermeable bilayer.

Analog measurement circuitry <NUM> is connected to a working electrode <NUM> (e.g., made of metal) covered by a volume of electrolyte <NUM> inside a well formed in an oxide layer <NUM>. The volume of electrolyte <NUM> is isolated from the bulk electrolyte <NUM> by the ion-impermeable membrane <NUM>. PNTMC <NUM> crosses membrane <NUM> and provides the only path for ionic current to flow from the bulk liquid to working electrode <NUM>. The cell also includes a counter electrode (CE) <NUM>. The cell also includes a reference electrode <NUM>, which can act as an electrochemical potential sensor.

<FIG> illustrates an embodiment of a cell <NUM> performing nucleotide sequencing with the nanopore-based sequencing by a synthesis (Nano-SBS) technique. In the Nano-SBS technique, a template <NUM> to be sequenced and a primer are introduced to cell <NUM>. To this template-primer complex, four differently tagged nucleotides <NUM>, A, T, G, and C are added to the bulk aqueous phase. As the correctly tagged nucleotide is complexed with the polymerase <NUM>, the tail of the tag is positioned in the barrel of nanopore <NUM>. The tag held in the barrel of nanopore <NUM> generates a unique ionic blockade signal <NUM>, thereby electronically identifying the added base due to the tags' distinct chemical structures.

<FIG> illustrates an embodiment of electrochemical cell <NUM> of a nanopore-based sequencing chip that includes a working electrode (e.g., TiN, which has a high electrochemical capacitance). Cell <NUM> includes a conductive or metal layer <NUM>. Metal layer <NUM> connects cell <NUM> to the remaining portions of the nanopore-based sequencing chip. In some embodiments, metal layer <NUM> is the top metal of the CMOS chip (e.g., metal <NUM> layer M6 of the underlying circuitry). Cell <NUM> further includes a working electrode <NUM> and a dielectric layer <NUM> above metal layer <NUM>. In some embodiments, working electrode <NUM> can be circular or octagonal in shape, and dielectric layer <NUM> forms the walls surrounding working electrode <NUM>. Cell <NUM> further includes a dielectric layer <NUM> above working electrode <NUM> and dielectric layer <NUM>. Dielectric layer <NUM> forms the insulating walls surrounding a well <NUM>.

In some embodiments, dielectric layer <NUM> and dielectric layer <NUM> together form a single piece of dielectric. Dielectric layer <NUM> is the portion that is disposed horizontally adjacent to working electrode <NUM>, and dielectric layer <NUM> is the portion that is disposed above and covering a portion of the working electrode. In some embodiments, dielectric layer <NUM> and dielectric layer <NUM> are separate pieces of dielectric and they may be formed separately. Well <NUM> has an opening above an uncovered portion of the working electrode. In some embodiments, the opening above the uncovered portion of the working electrode can be circular or octagonal in shape.

Inside well <NUM>, a volume of salt solution/electrolyte <NUM> is disposed above working electrode <NUM>. Salt solution <NUM> may include one of the following: lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KCl), lithium glutamate, sodium glutamate, potassium glutamate, lithium acetate, sodium acetate, potassium acetate, calcium chloride (CaClz), strontium chloride (SrClz), manganese chloride (MnClz), and magnesium chloride (MgClz). In some embodiments, salt solution <NUM> has a thickness of about three microns (µm). The thickness of salt solution <NUM> may range from <NUM>-<NUM> microns.

The dielectric material used to form dielectric layers <NUM> and <NUM> includes glass, oxide, silicon mononitride (SiN), and the like. The top surface of dielectric layer <NUM> may be silanized. Silanization forms a hydrophobic layer <NUM> above the top surface of dielectric layer <NUM>. In some embodiments, hydrophobic layer <NUM> has a thickness of about <NUM> nanometers (nm). Alternatively, dielectric material that is hydrophobic such as hafnium oxide may be used to form dielectric layer <NUM>.

As shown in <FIG>, a membrane is formed on top of dielectric layer <NUM> and spans across well <NUM>. For example, the membrane includes a lipid monolayer <NUM> formed on top of hydrophobic layer <NUM> and as the membrane reaches the opening of well <NUM>, the lipid monolayer transitions to a lipid bilayer <NUM> that spans across the opening of the well. Hydrophobic layer <NUM> facilitates the formation of lipid monolayer <NUM> above dielectric layer <NUM> and the transition from a lipid monolayer to a lipid bilayer. A bulk electrolyte <NUM> containing protein nanopore transmembrane molecular complexes (PNTMC) and the analyte of interest is placed directly above the well. A single PNTMC/nanopore <NUM> is inserted into lipid bilayer <NUM> by electroporation. Nanopore <NUM> crosses lipid bilayer <NUM> and provides the only path for ionic flow from bulk electrolyte <NUM> to working electrode <NUM>. Bulk electrolyte <NUM> may further include one of the following: lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KCl), lithium glutamate, sodium glutamate, potassium glutamate, lithium acetate, sodium acetate, potassium acetate, calcium chloride (CaCb), strontium chloride (SrCb), manganese chloride (MnCb), and magnesium chloride (MgCb).

Cell <NUM> includes a counter electrode (CE) <NUM>. Cell <NUM> also includes a reference electrode <NUM>, which acts as an electrochemical potential sensor. In some embodiments, counter electrode <NUM> can be shared between a plurality of cells, and is therefore also referred to as a common electrode. The common electrode can be configured to apply a common potential to the bulk liquid in contact with the nanopores in the measurements cells. The common potential and the common electrode are common to all of the measurement cells.

Working electrode <NUM> is a titanium nitride (TiN) working electrode with increased electrochemical capacitance. The electrochemical capacitance associated with working electrode <NUM> may be increased by maximizing the specific surface area of the electrode. The specific surface area of working electrode <NUM> is the total surface area of the electrode per unit of mass (e. , m<NUM>/kg) or per unit of volume (e. , m<NUM>/m<NUM>, m<NUM>/m<NUM>, or m-<NUM> or per unit of base area (e. , m<NUM>/m<NUM>). As the surface area increases, the electrochemical capacitance of the working electrode increases, and a greater amount of ions can be displaced with the same applied potential before the capacitor becomes charged. The surface area of working electrode <NUM> may be increased by making the TiN electrode "spongy" or porous. The TiN sponge soaks up electrolyte and creates a large effective surface area in contact with the electrolyte.

The ratio of the capacitance associated with the membrane Cmembrane and the capacitance associated with the working electrode Celectrochemical may be adjusted to achieve optimal overall system performance. Increased system performance may be achieved by reducing Cmembrane while maximizing Celectrochemical. Cmembrane can be adjusted to create the required RC time constant without the need for additional on-chip capacitance, thereby allowing a significant reduction in cell size and chip size.

In cell <NUM>, the base surface area of the opening of well <NUM> (which is the same as the base surface area of lipid bilayer <NUM>) and the base surface area of working electrode <NUM> are determined by the dimensions of dielectric layer <NUM> and dielectric layer <NUM>, respectively. The base surface area of working electrode <NUM> is greater than or equal to the base surface area of the opening of well <NUM>. Therefore, the two base surface areas may be optimized independently to provide the desired ratio between Cmembrane and Celectrochemical. As shown in <FIG>, a portion of working electrode <NUM> is covered by dielectric <NUM> and therefore the covered portion does not have direct contact with salt solution/electrolyte <NUM>. By using a spongy and porous TiN working electrode, the electrolyte can diffuse through the spaces between the columnar TiN structures and vertically down the uncovered portion of the working electrode and then horizontally to the covered portion of working electrode <NUM> that is underneath dielectric layer <NUM>. As a result, the effective surface area of TiN that is in contact with the electrolyte is maximized and Celectrochemical is maximized.

<FIG> illustrates an embodiment of a circuitry <NUM> in a cell of a nanopore-based sequencing chip, wherein the voltage or current applied across the nanopore can be configured to vary over a time period during which the nanopore is in a particular detectable state. In <FIG>, instead of showing a nanopore inserted in a membrane and the liquid surrounding the nanopore, an electrical model <NUM> represents the electrical properties of the nanopore and the membrane, and an electrical model <NUM> represents the electrical properties of the working electrode are shown.

Electrical model <NUM> includes a capacitor <NUM> that models a capacitance associated with the membrane (Cmembrane) and a resistor <NUM> that models a resistance associated with the nanopore in different states (e. , the openchannel state or the states corresponding to having different types of tags or molecules inside the nanopore). Electrical model <NUM> includes a capacitor <NUM> that models a capacitance associated with the working electrode. The capacitance associated with the working electrode is also referred to as an electrochemical capacitance (Celectrochemical). The electrochemical capacitance Celectrochemical associated with the working electrode includes a double-layer capacitance and may further include a pseudo capacitance.

<FIG> also includes a switch <NUM> coupled to a voltage <NUM>, which can be switched on and off for the purpose of measuring resistance <NUM>. In some embodiments, voltage <NUM> is applied to electrical model <NUM> representing the nanopore. After capacitor <NUM> is fully charged (which may not be very long as it is desirable for the membrane to have a low capacitance), the switch <NUM> can be opened, and current can flow from one side of capacitor <NUM> to the other side via resistor <NUM> (i.e., the nanopore that includes the molecule being detected). Different values for resistor <NUM> will cause different current to flow, and thus different voltage decays. Capacitor <NUM> can be sufficiently large to not impact the circuit significantly.

After a specified amount of time, a voltage can be measured at an ADC (Analog-to-Digital Converter) <NUM>. This can measure the time constant in the circuit represented by RCmembrane, as the voltage changes after the specified amount of time will correlate to the resistance of the pore (and thus the molecule inside of it). Embodiments can also measure an amount of time to reach a specific voltage, e.g., by using a comparator, as is described in <CIT>.

It is desirable for the working electrode to have a high capacitance, thereby reducing its impedance effect on the circuit, which can cause voltage levels to move slightly as a result of charge build up after multiple measurements that involve switch <NUM> opening and closing.

<FIG> illustrates a double layer that is formed at an interface between a conductive electrode and an adjacent liquid electrolyte. An electrical model for the double layer is shown as electrical model <NUM> in <FIG> that models a capacitance associated with the working electrode. In the example shown, the electrode surface is negatively charged, resulting in the accumulation of positively charged species in the electrolyte. In another example, the polarity of all charges may be opposite to the example shown. The charge in the electrode is balanced by reorientation of dipoles and accumulation of ions of opposite charge in the electrolyte near the interface. The accumulation of charges on either side of the interface between electrode and electrolyte, separated by a small distance due to the finite size of charged species and solvent molecules in the electrolyte, acts like a dielectric in a conventional capacitor. The term "double layer" refers to the ensemble of electronic and ionic charge distribution in the vicinity of the interface between the electrode and electrolyte.

<FIG> illustrates a pseudocapacitance effect that can be formed, simultaneously with the formation of a double-layer as in <FIG>, at an interface between a conductive electrode and an adjacent liquid electrolyte. <FIG> shows a double-layer with the addition of pseudo capacitance from charge transfer resulting in adsorption, intercalation, or reduction-oxidation reactions limited by available surface area (represented by solid circles).

<FIG> illustrates an example of a process for constructing an electrochemical cell of a nanopore-based sequencing chip that includes a TiN working electrode with increased electrochemical capacitance. The increased electrochemical capacitance can also be achieved with other electrodes having a porous structure and increased surface area.

At step A, a layer of dielectric <NUM> (e. , SiO<NUM>) is disposed on top of a conductive layer <NUM>. The conductive layer can be part of circuitries that deliver the signals from the cell to the rest of the chip. For example, the circuitries deliver signals from the cell to an integrating capacitor, and conductive layer <NUM> can be a metal six (M6) layer of the underlying circuitry. In some embodiments, the layer of dielectric <NUM> has a thickness of about <NUM>.

At step B, the layer of dielectric <NUM> is etched to create a hole <NUM>. The hole <NUM> provides a space for forming the spongy and porous TiN electrode.

At step C, a spongy and porous TiN layer <NUM> is deposited to fill the hole <NUM> created at step B. The spongy and porous TiN layer <NUM> is grown and deposited in a manner to create rough, sparsely-spaced TiN columnar structures or columns of TiN crystals that provide a high specific surface area that can come in contact with an electrolyte. The layer of spongy and porous TiN layer <NUM> can be deposited using different deposition techniques, including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) sputtering deposition, and the like. For example, layer <NUM> may be deposited by chemical vapor deposition using TiCl<NUM> in combination with nitrogen containing precursors (e. , NH<NUM> or N<NUM>). Layer <NUM> may also be deposited by chemical vapor deposition using TiCl<NUM> in combination with titanium and nitrogen containing precursors (e. , tetrakis-(dimethylamido) titanium (TDMAT) or tetrakis-(diethylamido) titanium TDEAT). Layer <NUM> may also be deposited by PVD sputtering deposition. For example, titanium can be reactively sputtered in an N<NUM> environment or directly sputtered from a Ti target or directly sputtered from a TiN target. The conditions of each of the deposition methods may be tuned in such a way to deposit sparsely-spaced TiN columnar structures or columns of TiN crystals. For example, when layer <NUM> is deposited by DC (direct current) reactive magnetron sputtering from a titanium (Ti) target, the deposition system can be tuned to use a low temperature, low substrate bias voltage (the DC voltage between the silicon substrate and the Ti target), and high pressure (e. , <NUM> mT) such that the TiN can be deposited more slowly and more gently to form columns of TiN crystals. In some examples the depth of the deposited layer <NUM> is about <NUM> times the depth of hole <NUM>. The depth of the deposited layer <NUM> is between <NUM> angstroms to <NUM> microns thick. The diameter or width of the deposited layer <NUM> is between <NUM> to <NUM> microns.

With continued reference to <FIG>, at step D, the excess TiN layer is removed. For example, the excess TiN layer may be removed using chemical mechanical polishing (CMP) techniques. The remaining TiN deposited in the hole <NUM> forms a spongy and porous Ti working electrode <NUM>. After working electrode <NUM> is formed, a layer of dielectric <NUM> (e. , SiO<NUM>) is deposited on top of the dielectric <NUM> and working electrode <NUM>. In some examples, the depth of dielectric <NUM> is between <NUM> to <NUM> microns.

At step E, the layer of dielectric <NUM> is etched to create a well <NUM> exposing only a portion of the upper base surface area of the working electrode. For example, the well may be etched by reactive-ion etching (RIE). Because the base surface area of the opening of the well is independent from the base surface area of the working electrode, Cmembrane and Celectrochemical in the cell may be fine-tuned to obtain the desired Cmembrane and Celectrochemical ratio. In some examples, the diameter (d1) of well <NUM> is between <NUM> to <NUM> microns.

An electrochemical cell of a nanopore-based sequencing chip having a spongy TiN working electrode has many advantages. Depending on the thickness of the TiN electrode (e. , <NUM> angstroms to <NUM> microns thick), the specific surface area of the spongy TiN working electrode and its electrochemical capacitance (e. , <NUM> picofarads to <NUM> picofarads per square micron of base area) have a <NUM>-<NUM> times improvement over that of a flat TiN working electrode with substantially identical dimensions (e. , substantially identical thickness and base surface area). Since the spongy TiN working electrode allows electrolyte to diffuse through easily, the diameter/width of the spongy TiN working electrode may extend beyond the diameter/width of the well, such that the base surface area of the well and the working electrode can be optimized independently to provide the desired ratio between Cmembrane and Celectrochemical or improved system performance. Other advantages of using TiN include its low cost and ease of patterning and etching compared to other electrode materials, such as platinum.

<FIG> is a micrograph illustrating a cross-section view of a spongy and porous TiN layer <NUM> deposited above a metal layer <NUM>. As shown in <FIG>, the spongy and porous TiN layer <NUM> includes grass-like columnar structures <NUM>. These structures can increase the surface area for the electrode, and thus the capacitance, which helps to reduce the effect of capacitance <NUM> from <FIG>. <FIG> is another micrograph illustrating another cross-section view of a spongy and porous TiN layer <NUM> with TiN columnar structures <NUM> that are grown from the surface of the hole <NUM> at Step B of <FIG>.

More details of the nanopore cells described above can be found in <CIT>.

<FIG> are simplified cross-sectional views of various shapes of wells that can be used in a nanopore cell according to various embodiments of the invention. A nanopore cell has a well that has a well sidewall formed within a dielectric layer and a working electrode at the bottom of the well. The shape of the well can affect the formation of the nanopore device and its performance. <FIG> illustrates that the shape of the well can be described by a corner between a top surface of the dielectric layer and the well sidewall and the slope of the sidewall. <FIG> illustrate wells with angles at well edge equal to or greater than <NUM>°, and <FIG> illustrate wells with angles at well edge less than <NUM>° (reentrant profile). The well sidewall can be straight, slanted, or curved. The shape of the well may be affected by the material forming the well and the process condition. Possible effect of well shape on the well performance is also discussed.

<FIG> illustrates a well <NUM> overlying an electrode <NUM>. Well <NUM> is surrounded by a dielectric material layer <NUM>. Dielectric material layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. The angle formed at the well edge between sidewall surface <NUM> and top surface <NUM> can be characterized as angle θ. The corner formed at the intersection of sidewall surface <NUM> and top surface <NUM> can be described by a radius of curvature r. In <FIG>, the angle θ is substantially <NUM>°, and the corner at the well edge is rounded with a relatively small radius of curvature r.

The well profile (e.g., as defined by the angle and the sharpness of the well edge) can affect how fast the metastable bilayer structure forms and how robust it is. For electrical measurement, it is desirable to have a low capacitance of the bilayer (smaller time constant for voltage changes, thereby providing faster acquisition time) and a high double layer capacitance at the working electrode (decreases effect of double layer on the circuit by reducing impedance of the working electrode). The bilayer capacitance can be made smaller by reducing the size of the aperture or opening of the well, or making the bilayer membrane thicker. The double layer capacitance can be made larger by increasing the surface area of the working electrode. Further, the TiN electrode described above has a spongy and porous top surface that can increase the effective capacitance. Alternatively, a smaller bilayer capacitance and larger double layer capacitance can be achieved with a reentrant well profile, in which the well has a wider bottom base than the top opening.

The shape of the well can be influenced by the material and process used in forming the well. For example, a well can be formed in a layer of polyimide, which is a polymer of an imide monomers. A monomer is a functional group consisting of two acyl groups bound to nitrogen. Polyimide materials are known for thermal stability, good chemical resistance, excellent mechanical properties, and they are widely used in the electronics industry. A well formed by reactive ion etching (RIE) of polyimide tends to have a more vertical profile and sharp corners. In contrast, a well formed by photolithographic patterning of a polyimide layer tends to have more rounded corners and more sloped sidewalls. If a well is formed in an oxide layer, a wet etching process can undercut the oxide, leading to a wider bottom of the well. In addition, other materials can also be used to form a well with different profiles. For example, SU-<NUM>, which is an epoxy material, or CYTOP, which is a fluoropolymer, can also be used to form wells.

<FIG> illustrates a well <NUM> overlying electrode <NUM>. Well <NUM> is surrounded by a dielectric material layer <NUM>. Dielectric material layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. The angle formed at the well edge between sidewall surface <NUM> and top surface <NUM> can be characterized as an angle θ of <NUM>°. The corner formed at the intersection of sidewall surface <NUM> and top surface <NUM> can be described by a radius of curvature r. For example, the radius of curvature r can be as small as <NUM>Å. The well structure in <FIG> can be formed by, for example, RIE etching of a dielectric layer. The sharp corners can facilitate the formation of the bilayer membrane.

<FIG> illustrates a well <NUM> overlying electrode <NUM>. Well <NUM> is surrounded by a dielectric material layer <NUM>. Dielectric material layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. The angle formed at the well edge between sidewall surface <NUM> and top surface <NUM> can be characterized as angle θ of greater by <NUM>°. The corner formed at the intersection of sidewall surface <NUM> and top surface <NUM> can be described by a radius of curvature r of, e. , <NUM> -<NUM>. In <FIG>, well <NUM> has a wide rounded edge profile with a large angle θ and a large radius of curvature r. The well structure in <FIG> can be formed by photolithography patterning of a polyimide layer.

<FIG> illustrates a well <NUM> overlying electrode <NUM>. Well <NUM> is surrounded by a dielectric material layer <NUM>. Dielectric material layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. In <FIG>, well <NUM> has a reentrant well edge profile, and the angle formed at the well edge between sidewall surface <NUM> and top surface <NUM> can be characterized as angle θ of less than <NUM>°. The corner formed at the intersection of sidewall surface <NUM> and top surface <NUM> can be described by a small radius of curvature r. The sharp corners can facilitate the formation of the bilayer membrane. Further, the reentrant well profile can also provide a larger bottom area than the top aperture area. The well structure in <FIG> also provides a smaller bilayer membrane capacitance at the top aperture and a larger double layer capacitance at the working electrode. A method for forming the well structure of <FIG> is described in a section below.

<FIG> illustrates a well <NUM> overlying electrode <NUM>. Well <NUM> is surrounded by a dielectric material layer <NUM>. Dielectric material layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. The angle formed at the well edge between sidewall surface <NUM> and top surface <NUM> can be characterized as angle θ. In <FIG>, well <NUM> has a reentrant well edge profile with an even smaller angle θ than the profile shown in <FIG>. The well sidewall has a concave profile forming a sharp angle θ with the top surface of the dielectric material. The corner formed at the intersection of sidewall surface <NUM> and top surface <NUM> can be described by a very small radius of curvature r. The sharp corners can facilitate the formation of the bilayer membrane. Similar to <FIG>, the reentrant profile of <FIG> also provides a smaller bilayer membrane capacitance at the top aperture and a larger double layer capacitance at the working electrode. This structure can be made by using a preexisting mandrel or by using a combination of RIE and wet etch.

The surface properties of various parts of the well can affect the formation of the nanopore device and its performance. For example, it is desirable to have a working electrode that is wettable by aqueous solvents to facilitate the formation of the double layer. The wettability of a solid surface is determined by its surface energy and is often characterized by a water contact angle. Generally, if the water contact angle is less than <NUM>°, the solid surface is considered hydrophilic, and if the water contact angle is greater than <NUM>°, the solid surface is considered hydrophobic. Therefore, it is desirable that the working electrode is hydrophilic, which can be characterized by a water contact angle of less than <NUM>°. In some cases, a surface can be considered hydrophilic if the water contact angle is less than <NUM>°. In other cases, a surface can be considered hydrophilic if the water contact angle is less than <NUM>°. It is desirable for the working electrode to be hydrophilic as this will increase the capacitance of the working electrode, thereby reducing its impedance effect on the circuit, which can cause voltage levels to move slightly as a result of charge build up after multiple measurements that involve switch <NUM> opening and closing.

The lipid that forms the membrane is in an organic solvent, and it is lipophilic. Lipophilic substances tend to dissolve in other lipophilic substances, while hydrophilic substances tend to dissolve in water and other hydrophilic substances.

The process of forming the bilayer over the aperture of the cell involves feeding reagents through the flow cell to set up the membrane. Factors that can influence the bilayer formation include the surface energy of all of the surfaces that are in contact with the liquid, the height of the flow cell, the flow rate of the liquids, and the viscosities of the fluids, etc. For example, it is desirable to have a hydrophobic surface around the aperture to wet with the organic solvent and lipid mixture that spans across the aperture.

The hydrophobicity of the well surface can be determined by the material and surface treatment used in the well construction. For example, the well can be formed in an oxide, and a silane treatment can change the oxide from hydrophilic to hydrophobic. Alternatively, the well can be formed in a polyimide layer, which is hydrophobic. The well can also be formed in CYTOP, which is a hydrophobic amorphous fluoropolymer. The sidewall surface and top surface of the well can have different arrangement of hydrophobicity.

<FIG> are simplified cross-sectional views of various wells that have different surface properties. In <FIG>, a typical cell with vertical sidewalls and approximately <NUM>° corners is used to illustrate the surface properties. However, the analysis of well surface properties can also be applied to other well profiles. For example, <FIG> illustrates a reentrant well having similar surface properties as the well in <FIG>.

<FIG> illustrates a well <NUM> overlying an electrode <NUM>. Well <NUM> is surrounded by a dielectric layer <NUM>. Dielectric layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. In <FIG>, the top surface of electrode <NUM> is hydrophilic, as illustrated with hatched marks. The well sidewall surface <NUM> and top surface <NUM> are hydrophobic, as illustrated by solid black lines. In this structure, the well can be made with a hydrophobic dielectric material (e.g., polyimide) over a hydrophilic electrode, for example, a TiN electrode. Alternatively, a well can be formed in an oxide layer, and then a silane treatment can be used to convert the oxide surface to become hydrophobic. As described above, the hydrophilic working electrode facilitates the wetting of the solvents in the well for forming contact with the solvents, and the hydrophobic top well surface is desirable for the formation of the bilayer membrane. As explained above in connection with <FIG>, a membrane can be formed on top of dielectric layer <NUM> and span across well <NUM>. For example, the membrane can include a lipid monolayer formed on top of hydrophobic top surface <NUM>. As the membrane reaches the opening of well <NUM>, the lipid monolayer can transition to a lipid bilayer that spans across the opening of the well. Having a hydrophobic surface (e.g., from a layer or a coating/film over a layer) can facilitate the formation of a lipid monolayer and the transition from a lipid monolayer to a lipid bilayer.

<FIG> illustrates a well <NUM> overlying an electrode <NUM>. Well <NUM> is surrounded by a dielectric material layer <NUM>. Dielectric material layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. In <FIG>, the top surface of electrode <NUM> is hydrophilic, as illustrated with hatched marks. An upper portion of the well sidewall surface <NUM> and the well top surface <NUM> are hydrophobic, as illustrated by solid black lines. However, a lower portion of the well sidewall surface <NUM> is hydrophilic, as illustrated with hatched marks. Similar to the well structure in <FIG>, in <FIG>, the hydrophilic working electrode facilitates the wetting of the solvents in the well, and the hydrophobic top well surface is desirable for the formation of the bilayer membrane. This structure can be formed by using a hydrophilic liner in the well. It can also be created by using a film stack with a hydrophilic material closest to the electrode and a hydrophobic material on top. This could allow better wetting of the well (especially very small wells) and electrode.

<FIG> illustrates a well <NUM> overlying an electrode <NUM>. Well <NUM> is surrounded by a dielectric material layer <NUM>. Dielectric material layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. In <FIG>, the top surface of electrode <NUM> is hydrophilic, as illustrated with hatched marks. The well top surface <NUM> is hydrophobic, as illustrated by solid black lines. However, the well sidewall surface <NUM> is hydrophilic, as illustrated with hatched marks. A method for forming the well structure of <FIG> can include depositing a layer of a hydrophilic dielectric material, coating the dielectric layer with a hydrophobic top surface layer, and then forming a well by an etching process. Similar to the well structure in <FIG>, the hydrophilic working electrode facilitates the wetting of the solvents in the well, and the hydrophobic top well surface is desirable for the formation of the bilayer membrane.

<FIG> illustrates a reentrant well having similar surface properties as the well in <FIG> illustrates a reentrant well <NUM> overlying an electrode <NUM>. Well <NUM> is surrounded by a dielectric material layer <NUM>. Dielectric material layer <NUM> has a sidewall surface <NUM> and a top surface <NUM>. In <FIG>, the top surface of electrode <NUM> is hydrophilic, as illustrated with hatched marks. The well sidewall surface <NUM> and top surface <NUM> are hydrophobic, as illustrated by solid black lines.

In this structure, the well can be made with a hydrophilic dielectric material such as polyimide over a hydrophilic electrode, such as a TiN electrode. An example method for forming a reentrant well using polyimide is described in a section below. Alternatively, a well can be formed in an oxide layer, and then a silane treatment can be used to convert the oxide surface to become hydrophobic. As described above, the hydrophilic working electrode facilitates the wetting of the solvents in the well, and the hydrophobic top well surface is desirable for the formation of the bilayer membrane. Further, the reentrant profile of <FIG> also provides a smaller bilayer membrane capacitance at the top aperture and a larger double layer capacitance at the working electrode.

As described above, a nanopore well can be defined by a spongy and porous working electrode and a hydrophobic dielectric layer. Using a spongy and porous material for the working electrode (e.g., TiN) can provide increased surface area and higher double layer capacitance for the nanopore cells. However, if the hydrophobic dielectric layer (e. , the polyimide layer or other hydrophobic layer) is formed directly on the porous electrode, residues of the hydrophobic dielectric material can be embedded in the gaps or cavities in the porous electrode, e.g., within the columnar structures of a TiN electrode. The organic residues can make the electrode surface less wettable and prevent fluid from contacting the surface of the electrode. As a result, the effective surface area can be reduced, causing a significant drop in the double layer capacitance at the electrolyte-electrode interface. To alleviate this problem,, a thin buffer or sacrificial dielectric layer, such as an SiO<NUM> layer, can be formed on the electrode to protect the surface of the electrode prior to subsequent processing, such as the deposition of the polyimide layer. After the well is formed, the thin sacrificial dielectric layer can be removed from the top surface of the electrode. The thin buffer or sacrificial dielectric layer serves to protect the porous electrode layer from the hydrophobic layer during the well formation process.

<FIG> illustrate a process for constructing an electrochemical cell of a nanopore-based sequencing chip that includes a buffer for protecting a porous working electrode. After the formation of the working electrode, a buffer layer is formed on the working electrode, and then a hydrophobic dielectric layer is formed on the buffer layer. After the hydrophobic dielectric layer is etched to form the cavity of the well, the buffer layer is removed to expose the working electrode. During this process, the hydrophobic dielectric material does not form direct contact with the working electrode at the bottom of the well. The buffer layer can prevent organic residues from being embedded in the porous working electrode.

<FIG> shows a structure with a substrate having a conductive layer <NUM> disposed in a top portion of the substrate and a dielectric layer <NUM> surrounding conductive layer <NUM>, which can connect to a circuit, e.g., in a semiconductor layer. A porous electrode layer <NUM> is formed on the conductive layer in an opening of the first dielectric layer <NUM>. The structure in <FIG> is similar to the structure shown in Step D in <FIG>, and can be formed using the method described above in connection to <FIG>.

Conductive layer <NUM> can be part of circuitries that deliver the signals from the cell to the rest of the chip. In some cases, conductive layer <NUM> can be the top metal layer of the circuitry, for example, the sixth metal layer labeled as M6 in <FIG>. However, conductive layer <NUM> is not limited to being the sixth metal layer of the underlying circuitry. Conductive layer <NUM> can be, for example, an aluminum layer. As shown in <FIG>, conductive layer <NUM> is enclosed in a layer of dielectric <NUM> (e. , SiO<NUM>). Dielectric layer <NUM> can include a dielectric layer formed on top of conductive layer <NUM>, which is already surrounded by a dielectric layer. In some examples, the layer of dielectric <NUM> has a thickness of about <NUM>.

Next, the layer of dielectric <NUM> is etched to create a hole, and a spongy and porous layer (e.g., TiN) is deposited to fill the hole. The spongy and porous layer can be grown in a manner to create rough, sparsely-spaced columnar structures or columns of crystals that provide a high specific surface area that can come in contact with an electrolyte. An example of the formation process for TiN is described above in connection with <FIG>. In some examples, the depth of the deposited layer <NUM> is about <NUM> times the depth of the hole. The depth of the deposited layer can be between <NUM> angstroms to <NUM> microns thick. The diameter or width of the deposited electrode layer can be between <NUM> to <NUM> microns. The excess electrode layer can be removed using chemical mechanical polishing (CMP) techniques. The remaining TiN deposited in the hole can form a spongy and porous working electrode (WE) <NUM>. In some cases, a titanium (Ti) adhesive layer can be formed between metal conductive layer <NUM> and working electrode layer <NUM>.

In <FIG>, a layer of dielectric <NUM> (e. , SiO<NUM>) is deposited on top of the working electrode <NUM> and the dielectric layer <NUM>. Dielectric layer <NUM> is used as a buffer layer or sacrificial layer to protect the TiN electrode so it retains wettability and the increased double layer capacitance. This layer can be easily chemically removed without damaging the electrode and well materials. For example, this layer can be nonporous. Examples of a protective cap oxide are silicon oxide, titanium oxide, hafnium oxide, zirconium oxide. This material can be hydrophobic or hydrophilic. Dielectric layer <NUM> can be a low temperature silicon oxide having a thickness of about <NUM>Å. The low temperature silicon oxide can be formed using a chemical vapor deposition (CVD) process at a temperature of, for example, <NUM>° to <NUM>°. Depending on the device requirement, the thickness of the SiO<NUM> layer <NUM> can be between, for example, <NUM>Å to <NUM>Å. Suitable dielectric materials for use in embodiments of the present invention (e. , dielectric layer <NUM>) include, without limitation, oxides, nitrides (e.g., silicon mononitride or SiN), silicon oxide, silicon oxynitride, metal oxides, metal nitrides, metal silicates, transition-metal oxides, transition-metal nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium oxide, zirconium silicate, zirconium aluminate, hafnium oxide, titanium oxide, or combinations thereof. Those of ordinary skill in the art will appreciate other dielectric materials that are suitable for use in the present invention.

In <FIG>, a layer of dielectric layer <NUM> (e. , polyimide) is deposited on top of the dielectric layer <NUM>. For example, the polyimide layer can be formed by a spin-on process, which can be followed by a bake or curing process. The thickness of polyimide layer <NUM> is selected according to the desired depth of the nanopore.

In <FIG>, the layer of dielectric <NUM> is etched to create a cavity <NUM> exposing a portion of the upper surface of dielectric layer <NUM>. As described above in connection with <FIG>, the polyimide layer can be patterned by reactive-ion etching (RIE) or by direct photolithographic patterning. For example, the depth of cavity <NUM> can be between <NUM> to <NUM> microns. In this process, dielectric layer <NUM> prevents polyimide layer <NUM> from directly contacting electrode layer <NUM>. In some examples, the thickness of dielectric layer <NUM> can be between <NUM> to <NUM> microns.

In <FIG>, the layer of dielectric <NUM> is removed from cavity <NUM> to expose a portion of the upper base surface area of the working electrode <NUM> to form a well. For example, dielectric layer <NUM> may be etched by a wet etching process using hydrofluoric acid (HF). Preferably, the etching process used to remove dielectric layer <NUM> has proper selectivity such that it does not damage dielectric layer <NUM> forming the sidewalls of the well and the top surface of the porous electrode that forms the bottom of the well. Further, the etching process does not leave etching residues or renders the top surface of the electrode to become hydrophobic, which may reduce the effective surface area of the electrode. In some embodiments, the diameter of cavity <NUM> can be between <NUM> to <NUM> microns.

In <FIG>, undercut regions <NUM> can be formed if a prolonged etching process is used to remove dielectric layer <NUM>.

<FIG> illustrates a nanopore cell <NUM> that includes a conductive layer <NUM> disposed in a top portion of a substrate, and a porous titanium nitride (TiN) electrode layer <NUM> disposed on the conductive layer. As described above, the nanopore cell can be formed on top of a substrate, for example, a CMOS substrate, that includes circuitry for controlling the operation of the nanopore cell. Conductive layer <NUM> can be a top metal layer of the underlying circuitry. For simplicity, the substrate is not shown in <FIG>. A first dielectric layer <NUM>, e. , a silicon oxide layer, is disposed on the TiN electrode layer, and a polyimide layer <NUM> is disposed on the first dielectric layer. A cavity or well <NUM> is formed in the polyimide layer and the first dielectric layer <NUM>, the cavity exposing a portion of the TiN electrode layer. A well is formed by the cavity on the exposed portion of the TiN electrode layer. It can be seen in <FIG> that the well <NUM> has a bottom base formed by the TiN electrode layer, and the well sidewall is formed by a polyimide layer over the first dielectric layer <NUM>.

<FIG> are SEM (scanning electron microscope) images illustrating an example of a nanopore device formed by the method of <FIG>. A well <NUM> is formed in a cavity of a polyimide layer <NUM>. As shown in <FIG>, well <NUM> is filled with a coating material for SEM sample preparation. At the bottom of well <NUM> is the top surface of TiN electrode <NUM>. The sidewalls of well <NUM> are formed by a polyimide layer over a dielectric layer <NUM>, such as a silicon oxide layer. At the bottom of well <NUM>, the silicon oxide sacrificial layer is removed to expose the porous top surface of the TiN electrode for contact with the electrolyte in well <NUM>.

The examples described above are related to methods for protecting porous electrode material in order to preserve its high electric double-layer capacitance. The porous electrode material, if not protected, is susceptible to oxidation and polymer insertion which will result in a drastic reduction in double-layer capacitance. For example, an oxide film or other dielectric film can be deposited on the electrode surface as a protection layer, which will be removed when the chip is ready for usage.

In alternative examples, a metallic film, as opposed to an oxide film, can be used as the protective layer. Metallic films such as a titanium film can be deposited at low temperatures in a non-oxidizing, vacuum chamber to reduce exposure to an oxidizing ambient, which can reduce double-layer capacitance of porous electrode material. In addition, metal films such as titanium can be directly deposited in-situ following porous electrode material deposition in the same chamber without breaking vacuum. The metallic film is sacrificial and will be removed prior to chip when the chip is ready for usage.

<FIG> illustrate a process for constructing an electrochemical cell of a nanopore-based sequencing chip that includes a sacrificial metal layer for protecting a porous working electrode during cell manufacturing. In one example, after the formation of the porous working electrode, a sacrificial metal layer is formed on the working electrode, and then a hydrophobic dielectric layer is formed on the sacrificial metal layer. After the hydrophobic dielectric layer is etched to form the cavity of the well, the sacrificial metal layer is removed to expose the working electrode. During this process, the hydrophobic dielectric material does not form direct contact with the working electrode at the bottom of the well. The sacrificial metal layer can prevent organic residues from being embedded in the porous working electrode. In the example illustrated in <FIG>, a titanium layer is used as the sacrificial metal layer. However, it is understood that other suitable metal or metal alloy layer can also be used.

<FIG> shows a device structure with a substrate <NUM> having a conductive layer <NUM> disposed in a top portion of the substrate and a dielectric layer <NUM> surrounding conductive layer <NUM>, which can be connected to a circuit, e.g., in a semiconductor layer in the substrate. For example, conductive layer <NUM> can be part of circuitries that deliver the signals from the cell to the rest of the chip. In some cases, conductive layer <NUM> can be the top metal layer of the circuitry, for example, the sixth metal layer labeled as M6 in <FIG>. However, conductive layer <NUM> is not limited to being the sixth metal layer of the underlying circuitry. Conductive layer <NUM> can be, for example, an aluminum layer. As shown in <FIG>, conductive layer <NUM> is surrounded in a layer of dielectric <NUM> (e. , SiO<NUM>). For example, the layer of dielectric <NUM> has a thickness of about <NUM>. As shown in <FIG>, the layer of dielectric <NUM> is etched to create an opening to expose a top surface of conductive layer <NUM>.

In <FIG>, a porous electrode layer <NUM> is formed on the conductive layer <NUM> in the opening of the first dielectric layer <NUM> and on the first dielectric layer <NUM>. In some examples, the porous electrode <NUM> can be a porous TiN layer formed using a process similar to the process described in connection to Step C of <FIG>. The spongy and porous layer can be grown in a manner to create rough, sparsely-spaced columnar structures or columns of crystals that provide a high specific surface area that can come in contact with an electrolyte. The TiN deposited in the hole can form a spongy and porous working electrode (WE). In some cases, a titanium (Ti) adhesive layer can be formed between metal conductive layer <NUM> and working electrode layer <NUM>.

In <FIG>, a sacrificial metal layer or cap layer <NUM> is deposited on top of the porous electrode layer <NUM>. In this example, the cap layer is a titanium (Ti) layer. The Ti layer <NUM> can be deposited using different deposition techniques, including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) sputtering deposition, and the like. For example, Ti layer <NUM> may be deposited by chemical vapor deposition using a precursor TiCl<NUM>. Ti Layer <NUM> may also be deposited by chemical vapor deposition using TiCl<NUM> in combination with titanium containing precursors (e. , tetrakis-(dimethylamido) titanium (TDMAT) or tetrakis-(diethylamido) titanium TDEAT). Ti layer <NUM> may also be deposited by PVD sputtering deposition. For example, titanium can be reactively sputtered in an inert environment or directly sputtered from a Ti target. In some examples, the porous TiN electrode layer <NUM> and the Ti layer <NUM> can be deposited in-situ in the same process chamber without breaking vacuum. In some examples, the thickness of the deposited Ti layer <NUM> can be between <NUM> angstroms to <NUM> microns thick. In one example, the TiN layer <NUM> is approximately <NUM> thick and the Ti cap layer <NUM> is approximately <NUM> thick.

In <FIG>, the sacrificial metal layer Ti <NUM> and the porous TiN electrode layer <NUM> are patterned to form a patterned stacked layer <NUM> covering the opening in the first dielectric layer. The stacked layer <NUM> includes a portion of the porous TiN electrode layer <NUM> and a portion of the sacrificial TiN layer <NUM>. The patterning of the sacrificial metal layer and the porous TiN electrode layer can be carried out using known lithography patterning process and etching process, such as a reactive ion etching (RIE) process.

In <FIG>, a dielectric layer <NUM> is deposited on top of the Ti/TiN stacked layer <NUM>. Dielectric layer <NUM> is used to form the walls of the nanopore cell. In this example, dielectric layer <NUM> is a polyimide layer. For example, the polyimide layer can be formed by a spin-on process, which can be followed by a bake or curing process. The thickness of polyimide layer <NUM> is selected according to the desired depth of the nanopore cell.

In <FIG>, a portion of the polyimide layer <NUM> is etched to create a cavity <NUM> to exposing a portion of the upper surface of Ti layer <NUM>. As described above in connection with <FIG>, the polyimide layer can be patterned by reactive-ion etching (RIE) or by direct photolithographic patterning. In some examples, the diameter of cavity <NUM> can be between <NUM> to <NUM> microns. In this process, Ti layer <NUM> prevents polyimide layer <NUM> from directly contacting porous electrode layer <NUM>.

In <FIG>, the Ti layer <NUM> is removed from cavity <NUM> to expose a portion of the top surface area of porous TiN layer <NUM> to form the lower base of the well. For example, the sacrificial Ti layer <NUM> may be etched by a wet etching process using hydrofluoric acid (HF). Preferably, the etching process used to remove metal layer <NUM> has proper selectivity such that it does not damage polyimide layer <NUM> forming the sidewalls of the well and the top surface of the porous electrode that forms the bottom of the well. Further, the etching process should not leave etching residues or renders the top surface of the electrode to become hydrophobic, which may reduce the effective surface area of the electrode. After the removal of Ti layer <NUM>, porous TiN layer <NUM> will function as the working electrode (WE) of the well.

<FIG> are SEM (scanning electron microscope) images illustrating an example of a device structure depicted in <FIG>. The device structure includes approximately <NUM> of titanium cap layer deposited on approximately <NUM> of porous TiN electrode layer. <FIG> is a top view of a surface of the deposited titanium layer. <FIG> is a cross-sectional view of a portion of the titanium cap layer deposited on the porous TiN electrode layer. It can be seen that the Ti layer only caps the surface of the porous TiN layer, and does not fill the gaps of the porous structures.

<FIG> is a diagram illustrating the double layer capacitance of a device structure having a sacrificial metal layer according to the method illustrated in <FIG>. The method includes approximately <NUM> of titanium sacrificial layer deposited on approximately <NUM> of porous TiN to protect the porous TiN electrode from the ambient and the polyimide layer. In <FIG>, data point <NUM> shows that the double-layer capacitance (Cdl) of the porous TiN electrode before the Ti cap deposition was about <NUM> uF/cm^<NUM>. Data point <NUM> shows that, after the Ti cap layer deposition, the double-layer capacitance dropped to about <NUM> uF/cm^<NUM>, signifying that the porous material had been sealed by the titanium layer. The substrate was then annealed at an elevated temperature in atmosphere to simulate environmental oxidation / contamination conditions. Data point <NUM> shows that the double-layer capacitance substantially remain unchanged after the anneal process. The Ti cap layer was then removed with a hydrofluoric acid-based chemical. Data point <NUM> shows the double-layer capacitance after the removal of the Ti cap. It can be seen that the double-layer capacitance of the porous electrode not only fully recovered its capacitance value, but also appeared to increase slightly. The increase in the double-layer capacitance may be due to the reducing effect or the oxygen gettering effect of the Ti protective layer. Alternatively, the increase in the double-layer capacitance may be due to prolonged exposure to the hydrofluoric acid-based chemical during the removal of the Ti cap layer. The data points in <FIG> demonstrate that the sacrificial Ti cap layer is effective in protecting the porous TiN electrode.

In some variations of the process described above in <FIG>, the Ti cap layer can be deposited in situ with the porous TiN electrode layer to protect the porous TiN electrode layer from exposure to the ambient. Alternatively, the Ti cap layer and the porous TiN electrode layer can be formed separately. Further, the Ti cap can be deposited after the porous TiN electrode is already deposited and patterned. For example, a process of forming the porous TiN electrode using a polishing (CMP) process is described in <FIG> and referenced in <FIG> and <FIG>. Starting with a planarized porous TiN electrode as shown in <FIG> or <FIG>, a Ti cap layer can be deposited and then patterned before the deposition of the polyimide layer for forming the well.

In the above description, a titanium layer is used as an example of the sacrificial metallic cap layer. However, other metallic layers can also be used as the cap layer. The metal cap layer is used as a buffer layer or sacrificial layer to protect the porous TiN electrode so it retains wettability and high double layer capacitance. Therefore, it is desirable that the sacrificial protective layer be nonporous and can be removed without damaging the electrode and well materials. Examples of the protective metal cap material can include titanium, aluminum, tungsten, etc. The removal of the metal cap layer can be achieved using a wet chemical process including hydrofluoric acid, nitric acid, or combination of chemicals. The removal of the metal cap layer can also be achieved using reactive ion etch with reactive fluorine and oxygen species, etc. It is desirable that the etch process has adequate etch selectivity with respect to the porous TiN layer and the polyimide layer. Moreover, the process described in <FIG>, which does not include a polishing planarization step, can also be used with a dielectric sacrificial layer, such as a oxide layer.

As described above, a nanopore well having sharp corners with a reentrant profile and a hydrophobic top surface of the well can provide advantages in bilayer formation and improve cell performance, such as bilayer lifetime and stability. Therefore, a method for forming a reentrant well structure using a hydrophobic material is desirable. For example, the hydrophobic material can be a polyimide or a negative photolithographic material like SU-<NUM>. A method is described below using polyimide as an example. In some examples, a reentrant well structure is formed using a sacrificial dielectric structure that has a mandrel structure. The mandrel structure can be formed before a polyimide layer is formed around the sacrificial structure. The sacrificial structure has a wider bottom region than a top region. As a result, after the sacrificial structure is removed, the remaining polyimide layer has a cavity with a narrow opening and a wider base, forming a reentrant well. As an additional advantage, the dielectric sacrificial structure serves to protect the underlying electrode during the formation of the polyimide layer.

<FIG> illustrate a process for constructing an electrochemical cell of a nanopore-based sequencing chip that includes a reentrant well profile.

<FIG> shows a structure with a substrate having a conductive layer <NUM> disposed in a top portion of the substrate and a dielectric layer <NUM> surrounding conductive layer <NUM>. A porous electrode layer <NUM> is formed on the conductive layer in an opening of the first dielectric layer <NUM>. The structure in <FIG> is similar to the structure shown in <FIG>, and can be formed using the method described above in connection to <FIG>.

In <FIG>, conductive layer <NUM> can be part of circuitries that deliver the signals from the cell to the rest of the chip. In some cases, conductive layer <NUM> can be the top metal layer of the circuitry, for example, the sixth metal layer labeled as M6 in <FIG>. However, conductive layer <NUM> is not limited to being the sixth metal layer of the underlying circuitry. Conductive layer <NUM> can be, for example, an aluminum layer. As shown in <FIG>, conductive layer <NUM> is enclosed in a layer of dielectric <NUM> (e. , Si0<NUM>). Dielectric layer <NUM> can include a dielectric layer formed on top of conductive layer <NUM>, which is already surrounded by a dielectric layer. For example, the layer of dielectric <NUM> may have a thickness of about <NUM>.

Next, the layer of dielectric <NUM> is etched to create a hole, and an electrode layer (e. , a spongy and porous TiN layer) is deposited to fill the hole. The spongy and porous layer is grown in a manner to create rough, sparsely-spaced TiN columnar structures or columns of TiN crystals that provide a high specific surface area that can come in contact with an electrolyte. An example of the TiN formation process is described above in connection with <FIG>. In some variations, the depth of the deposited layer <NUM> is about <NUM> times the depth of hole. The depth of the deposited electrode layer can be between <NUM> angstroms to <NUM> microns thick. The diameter or width of the deposited electrode layer can be between <NUM> to <NUM> microns. The excess electrode layer is removed using chemical mechanical polishing (CMP) techniques. The remaining electrode material deposited in the hole forms a spongy and porous electrode working electrode (WE) layer <NUM>. In some cases, an adhesive layer can be formed between metal layer and working electrode layer <NUM>. For example, for the TiN electrode layer, a titanium (Ti) adhesive layer can be formed between metal layer <NUM> and TiN working electrode layer <NUM>.

In <FIG>, a layer of dielectric <NUM> (e. , SiO<NUM>) is deposited on top of the dielectric layer <NUM> and working electrode <NUM>. The thickness of dielectric <NUM> can be approximately <NUM> microns. In some cases, the thickness of dielectric layer <NUM> can be, for example, between <NUM> to <NUM> microns.

In <FIG>, a layer of photoresist is deposited on top of the dielectric <NUM>. The photoresist <NUM> is then patterned to form an etch mask <NUM>. In <FIG>, dielectric layer <NUM> is etched using etch mask <NUM> to form a sacrificial or mandrel structure <NUM> shown in <FIG>. In some examples, sacrificial or mandrel structure <NUM> can have a circular or octagonal shape, and the diameter of sacrificial or mandrel structure <NUM> can be between <NUM> to <NUM> microns. Different etch conditions can be used to change the angle of the remaining sacrificial or mandrel structure <NUM>. For example, the mandrel structure is smaller at the top and wider at the bottom.

In <FIG>, the layer of dielectric <NUM> (e. , polyimide) is formed around sacrificial structure <NUM>. The sacrificial or mandrel structure remains on the working electrode layer <NUM> during the formation of the polyimide layer to protect the electrode layer from directly contacting the polyimide layer. The polyimide layer <NUM> can be formed by a spin-on process to a thickness just below the thickness of sacrificial structure <NUM> to expose a top portion of sacrificial structure <NUM>. In some cases, the spun-on polyimide layer <NUM> may be thicker than sacrificial structure <NUM>, and the polyimide layer <NUM> can be etched back to expose a top portion of sacrificial structure <NUM>. The polyimide layer is then baked (partially or fully), which causes it to shrink in volume.

In <FIG>, sacrificial structure <NUM> is removed by an etch process. For example, sacrificial structure <NUM> made of silicon oxide can be etched away using a hydrofluoric acid (HF) wet etch process. The condition for the wet etch for removing the SiO2 structure <NUM> is selected such that it does not damage the surface of the polyimide and does not have detrimental effects on the TiN working electrode surface. It can be seen that a well <NUM> is formed in the cavity in the polyimide layer <NUM>. The well has reentrant sidewalls; the top edges of well <NUM> have sharp angles <NUM>.

<FIG> illustrates a nanopore cell <NUM> that includes a conductive layer <NUM> disposed in a top portion of a substrate, a titanium nitride (TiN) electrode layer <NUM> disposed on the conductive layer. As described above, the nanopore cell can be formed on top of a substrate, for example, a CMOS substrate, that includes circuitry for controlling the operation of the nanopore cell. Conductive layer <NUM> can be a top metal layer of the underlying circuitry. For simplicity, the substrate is not shown in <FIG>. A polyimide layer <NUM> is disposed on the TiN electrode layer <NUM>. A cavity or well <NUM> is formed in the polyimide layer to expose a portion of the TiN electrode layer. A well having a reentrant profile is formed by the cavity on the exposed portion of the TiN electrode layer. It can be seen in <FIG> that the well <NUM> has a wider bottom base formed by the TiN electrode layer and a narrower top opening with sharp corners <NUM>.

A nanopore well having sharp edges with a reentrant profile and hydrophobic top surface of the well may provide advantages in bilayer formation and improve cell performance. For example, the base surface area of the working electrode is greater than the base surface area of the opening of well. Therefore, the nanopore bilayer capacitance Cmembrane is smaller than the double layer capacitance Celectrochemical. The method described above for forming the well structure in <FIG> also provides the additional advantage that the dielectric sacrificial structure serves to protect the underlying TiN electrode during the formation of the polyimide layer.

In the methods described above, e.g., <FIG>, <FIG>, <FIG>, and <FIG>, a polishing method may be used. For example, in <FIG>, between Step C and Step D, a polishing method (e.g., CMP) may be used to remove the excess working electrode (TiN) material to form the working electrode <NUM> having a top surface that is substantially coplanar to the top surface of adjacent dielectric layers. In arrangements
described below, the working electrode is formed without using a polishing method. This method can provide more working electrode surface area and better process control.

<FIG> illustrate a process for constructing an electrochemical cell of a nanopore-based sequencing chip without using a polishing method. The process also includes a sacrificial layer for protecting a porous working electrode during cell manufacturing. In one example, after the formation of the porous working electrode, a sacrificial layer is formed on the working electrode. The sacrificial layer and the working electrode can be patterned using a lithographic process instead of a polishing process. Next, a hydrophobic dielectric layer is formed on the sacrificial layer. After the hydrophobic dielectric layer is etched to form the cavity of the well, the sacrificial layer is removed to expose the working electrode. During this process, the hydrophobic dielectric material does not form direct contact with the working electrode at the bottom of the well. The sacrificial layer can prevent organic residues from being embedded in the porous working electrode. In the example illustrated in <FIG>, a silicon oxide layer is used as the sacrificial metal layer. However, it is understood that other suitable dielectric materials, including silicon nitride, or combinations of dielectric materials, can also be used. Further, metals, such as those described above in connection with <FIG>, or metal alloy layers can also be used.

<FIG> shows a device structure with a substrate <NUM> having a conductive layer <NUM> disposed in a top portion of the substrate and a dielectric layer <NUM> surrounding conductive layer <NUM>, which can be connected to a circuit, e.g., in a semiconductor layer in the substrate. For example, conductive layer <NUM> can be part of circuitries that deliver the signals from the cell to the rest of the chip. In some cases, conductive layer <NUM> can be the top metal layer of the circuitry, for example, the sixth metal layer labeled as M6 in <FIG>. However, conductive layer <NUM> is not limited to being the sixth metal layer of the underlying circuitry. Conductive layer <NUM> can be, for example, an aluminum layer. As shown in <FIG>, conductive layer <NUM> is surrounded in a layer of dielectric <NUM> (e. , SiO<NUM>). In some alternatives, the layer of dielectric <NUM> has a thickness of about <NUM>. As shown in <FIG>, the layer of dielectric <NUM> is etched to create an opening to expose a top surface of conductive layer <NUM>.

In <FIG>, a porous electrode layer <NUM> is formed on the conductive layer <NUM> in the opening of the first dielectric layer <NUM> and on the first dielectric layer <NUM>. In some examples, the porous electrode <NUM> can be a porous TiN layer formed using a process similar to the process described in connection to Step C of <FIG>. The spongy and porous layer can be grown in a manner to create rough, sparsely-spaced columnar structures or columns of crystals that provide a high specific surface area that can come in contact with an electrolyte. The TiN deposited in the hole can form a spongy and porous working electrode (WE). In some cases, a titanium (Ti) adhesive layer, also referred to as a seed layer, can be formed between metal conductive layer <NUM> and working electrode layer <NUM>.

In <FIG>, a sacrificial layer, also referred to as a cap layer, <NUM> is deposited on top of the porous electrode layer <NUM>. Cap layer <NUM> is used as a buffer layer or sacrificial layer to protect the TiN electrode so it retains wettability and the increased double layer capacitance. This layer can be easily chemically removed without damaging the electrode and well materials. As an example, the cap layer can be an oxide layer. Examples of a protective cap oxide are silicon oxide (SiO2), titanium oxide, hafnium oxide, zirconium oxide, etc. This material can be hydrophobic or hydrophilic. Dielectric layer <NUM> can be a low temperature silicon oxide having a thickness of about <NUM>Å. The low temperature silicon oxide can be formed using a chemical vapor deposition (CVD) process at a temperature of, for example, <NUM>° to <NUM>°. Depending on the device requirement, the thickness of the SiO<NUM> layer <NUM> can be between, for example, <NUM>Å to <NUM>Å. Suitable dielectric materials for use in embodiments of the present invention (e. , dielectric layer <NUM>) include, without limitation, oxides, nitrides (e.g., silicon mononitride or SiN), silicon oxide, silicon oxynitride, metal oxides, metal nitrides, metal silicates, transition-metal oxides, transition-metal nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium oxide, zirconium silicate, zirconium aluminate, hafnium oxide, titanium oxide, or combinations thereof. Those of ordinary skill in the art will appreciate other dielectric materials that are suitable for use in the present invention.

In <FIG>, a photoresist layer <NUM> is formed on the sacrificial layer <NUM> and the porous TiN electrode layer <NUM> and then patterned using a known lithography patterning process. The patterned photoresist layer <NUM> is used as an etch mask in <FIG>.

In <FIG>, using the patterned photoresist layer <NUM> of <FIG> as a mask, the sacrificial layer <NUM> and the porous TiN electrode layer <NUM> are etched to form a patterned stacked layer <NUM> covering the opening in the first dielectric layer. The stacked layer <NUM> includes a portion of the porous TiN electrode layer <NUM> and a portion of the sacrificial layer <NUM>. The stacked layer <NUM> extends from the opening in the dielectric layer <NUM> to cover a portion of the dielectric layer <NUM>, forming an overhang region <NUM> in the TiN electrode layer <NUM>. The etch can be carried out using a known process, such as a reactive ion etching (RIE) process. After the etching, the photoresist mask is removed.

In <FIG>, a portion of the polyimide layer <NUM> is etched to create a cavity <NUM> to expose a portion of the upper surface of Ti layer <NUM>. As described above in connection with <FIG>, the polyimide layer can be patterned by reactive-ion etching (RIE) or by direct photolithographic patterning. In some embodiments, the diameter of cavity <NUM> can be between <NUM> to <NUM> microns. In this process, the cap layer, or sacrificial layer, <NUM> can prevent polyimide layer <NUM> from directly contacting porous electrode layer <NUM>.

In <FIG>, the cap layer <NUM> is removed from cavity <NUM> to expose a portion of the top surface area of porous TiN layer <NUM> to form the lower base of the well. For example, the sacrificial layer <NUM> may be etched by a wet etching process using hydrofluoric acid (HF). Preferably, the etching process used to remove sacrificial layer <NUM> has proper selectivity such that it does not damage polyimide layer <NUM> forming the sidewalls of the well and the top surface of the porous electrode that forms the bottom of the well. Further, the etching process should not leave etching residues or renders the top surface of the electrode to become hydrophobic, which may reduce the effective surface area of the electrode. After the removal of Ti layer <NUM>, porous TiN layer <NUM> will function as the working electrode (WE) of the well.

<FIG> illustrates a nanopore cell <NUM> that includes a substrate <NUM>, a conductive layer <NUM> disposed in a top portion of the substrate <NUM>, and a first dielectric layer <NUM> overlying the conductive layer <NUM>. The first dielectric layer has an opening exposing a portion of the conductive layer, as shown in <FIG>. An electrode layer <NUM> is disposed in the opening of the first dielectric layer <NUM>. The electrode layer has an overhang portion <NUM> extending over the first dielectric layer <NUM> to overlap a portion of the first dielectric layer <NUM>. A second dielectric layer <NUM> is disposed on the first dielectric layer <NUM>. A cavity <NUM> in the second dielectric layer <NUM> exposes a portion of the electrode layer <NUM>. The cavity including an undercut portion <NUM> of the second dielectric layer <NUM> above the overhang portion <NUM> of the electrode. Nanopore cell <NUM> includes a well formed by the cavity <NUM>, which has a bottom base <NUM> formed by a top surface of the electrode layer <NUM> and well sidewalls <NUM> formed by the second dielectric layer <NUM>.

In the example of <FIG>, the electrode layer <NUM> includes porous TiN (titanium nitride), the first dielectric layer <NUM> includes an oxide layer, and the second dielectric layer <NUM> includes polyimide. Other suitable material can also be used, as described above in connection to <FIG>, <FIG>, <FIG>, and <FIG>. For example, the second dielectric layer <NUM> can include an organic material.

In some embodiments of the nanopore cell of <FIG>, the overhang portion can have a length in a range of <NUM> to <NUM>, the undercut portion can have a length in a range of <NUM> to <NUM>, the well can have a width in a range of <NUM> to <NUM> and a depth in a range of <NUM> to <NUM>.

Nanopore device <NUM> can provide many advantages. For example, the exposed surface area of the electrode <NUM> can be increased as a result of the overhang portion <NUM> of the electrode <NUM> and the undercut portion <NUM> under the second dielectric layer <NUM>, thereby increasing the double layer capacitance Celectrochemical. Further, the surface of the vertical portion of the electrode can also contribute to the overall surface area of the electrode. As a result, the base surface dimension of the working electrode can be greater than the base surface area of the well opening. Therefore, the nanopore double layer capacitance Celectrochemical can be larger than the bilayer capacitance Cmembrane, which can improve cell performance, as described above. Moreover, the overhang portion <NUM> of the electrode <NUM> overlaps the edges of the first dielectric layer <NUM>, which can provide process margin and improve process control.

It is possible to increase the porosity of the porous electrode, thereby increasing the effective area for increased double layer capacitance. In some of the examples described above, a protective thin film is deposited on the porous electrode to shield it from the organic film, such as polyimide, which forms the well boundaries. The protective film, or sacrificial film, can be removed with a chemistry (mixture) containing high concentration of hydrofluoric acid (HF). The protective film removal chemistry can be extended to increase the electrode double-layer capacitance by etching the electrode and making it more porous in the process. However, high concentration HF can be non-selective towards the underlying device's passivation dielectrics, and, therefore, poses risks of short circuits if applied over extended periods of time. An improved surface treatment method is described below.

<FIG> are cross-sectional views of representative nanopore device structures that are suitable for the surface treatment. <FIG> illustrates a nanopore device <NUM> similar to devices depicted in <FIG>, or <FIG>, where polishing may or may not be used to form the working electrode. <FIG> illustrates a nanopore device <NUM> similar to devices depicted in <FIG> or <FIG>, where a polishing method may or may not be used to form the working electrode. In <FIG>, the components are identified with the same reference numerals as the corresponding components in <FIG>. In <FIG>, the components are identified with the same reference numerals as the corresponding components in <FIG>. In both <FIG>, the arrows <NUM> correspond to the application of the chemistry in the new surface treatment.

In some nanopore devices, a sacrificial layer, or protective layer, such as an oxide layer, can be formed over the electrode layer during device formation. The sacrificial layer can be removed by a wet etch process, for example, using a buffered oxide etch (BOE) etch. With this chemical, a longer etch time can be chosen to increase Titanium Nitride (TiN) electrode double-layer capacitance (Cdbl). The prolonged etch can result in undercut regions such as <NUM> in <FIG> and <NUM> in <FIG>. However, with the certain cladding structure in the nanopore device, excessive BOE etch can cause damage, such as etching into underlying passivation oxide and/or electrode seed layer.

A chemistry including a mixture of oxidizing nitric acid (HNO<NUM>) and HF diluted in DI water can increase double-layer capacitance. For example, equal portions of oxidizing nitric acid (HNO<NUM>) and HF can be used. This treatment can increase double-layer capacitance by increasing the electrode porosity. HNO<NUM> can oxidize the metallic electrode, and HF can dissolve the metal oxide. This enhanced reaction allows for a more diluted concentration of HF, which in turn can suppress oxide etch rates. As an example, a nitric acid (HNO<NUM>) and HF mixture, diluted in DI Water to <NUM>:<NUM>:<NUM> concentration (<NUM>% HF), has been found to increase TiN working electrode double layer capacitance, Cdl, by increasing TiN porosity, but with high etch selectivity to oxide. In other examples, HF concentrations of <NUM>% to <NUM>% can be used.

<FIG> is a flowchart illustrating a method of surface treatment for increasing porosity of a porous electrode in a nanopore device. At step <NUM>, a nanopore cell with a porous electrode is provided. Step <NUM> is expanded further in <FIG>. At step <NUM>, the electrode is exposed with a nitric acid and HF mixture to increase porosity. As described above, nitric acid (HNO<NUM>) and HF can be diluted in DI water in various proportions can be used in the surface treatment.

<FIG> is a flowchart illustrating a method for forming a nanopore device with a porous electrode. Method <NUM> in <FIG> can be used to form the nanopore device in step <NUM> of <FIG> described above. Method <NUM> includes the methods of forming nanopore devices described above in connection with <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, and the accompanying texts, which illustrate methods for forming various nanopore devices. Method <NUM> can be briefly summarized as follows.

Method <NUM> includes, at Step <NUM>, forming a conductive layer overlying a substrate. At Step <NUM>, a first dielectric is formed over the conductive layer. An opening in the dielectric layer exposing a portion of the conductive layer. More detail is provided in the description in connection with <FIG>, Steps A and B, <FIG>, and <FIG>.

At Step <NUM>, a porous electrode layer is formed over the first dielectric layer and the opening. More detail is provided in the description in connection with <FIG>, Step C. This can include several variations. For example, <FIG> illustrates forming a dielectric sacrificial layer over the porous electrode. <FIG> illustrates forming a metallic sacrificial layer over the porous electrode, <FIG> illustrates forming a trapezoidal-shaped sacrificial layer over the porous electrode for forming a reentrant well. <FIG> illustrates a process forming a sacrificial layer over the electrode layer using a non-polishing method.

At Step <NUM>, a second dielectric layer is formed over the porous electrode layer. More detail is provided in the description in connection with <FIG>, Step D, <FIG>, <FIG>, <FIG>, and <FIG>.

At Step <NUM>, a cavity is formed in the second dielectric layer to form a well, with the porous electrode layer forming the bottom of the well. More detail is provided in the description in connection with <FIG>, Step E, <FIG>, <FIG>, <FIG>, and <FIG>.

<FIG> provides SEM (scanning electron microscope) images illustrating the results of surface treatment for increasing the double layer capacitance of a nanopore device. Three nanopore devices, A, B, and C (such as device <NUM> shown in <FIG>, device <NUM> shown in in <FIG>, or device <NUM> shown in <FIG>) were treated with the same amount of BOE (buffered oxide etch) for <NUM> minutes to remove the protective oxide film. The three deviceswere then treated with additional HNO<NUM>/HF chemistry for different lengths of time. Device A received no additional HNO<NUM>/HF treatment, device B received an additional five minutes of HNO<NUM>/HF treatment, and device C received an additional <NUM> minutes of HNO<NUM>/HF treatment.

The top row of SEM images in <FIG> contains top-down SEM images of the electrodes for device A, B, and C. It can be seen from magnified views of the top down SEM images that the porosity of the electrode increases with the increased time of the HNO<NUM>/HF surface treatment. The increased electrode porosity is also confirmed from double layer capacitance measurements described in more detail below in connection with <FIG>. The center row of SEM images in <FIG> contains cross-section SEM images of the electrodes. The circles in the center row of SEM images show that no change to the residual protective oxide is observed from the cross-section images, highlighting the high etch selectivity this treatment has on oxide. The high etch selectivity allows longer treatment, which increases porosity. The bottom row of SEM images in <FIG> contains magnified cross-section SEM images of the electrodes showing more details of the porous working electrode.

In some cases, prolonged treatment in the HNO<NUM>/HF mixture may attack the titanium (Ti) layer, which is used as the seed material for the TiN working electrode. However, this issue can be mitigated by choosing a seed material with high resistance to HF, such as tungsten (W) or chromium (Cr).

<FIG> is a diagram illustrating an increase in the double layer capacitance with additional surface treatment time. Two nanopore devices, such as device <NUM> shown in <FIG>, were used in this experiment. Both devices had an initial wet etch process of <NUM> minutes in <NUM>:<NUM>:<NUM> BOE to remove protective oxide (cap layer). In <FIG>, the circles illustrate the double layer capacitance Cdbl for the first device, which had an initial double layer capacitance of about <NUM> pF/cell about. After an additional <NUM>-minute treatment in <NUM>:<NUM>:<NUM> BOE, the double layer capacitance for the first device increased to about <NUM> pF/cell. After a <NUM>-minute additional treatment in <NUM>:<NUM>:<NUM> BOE, the double layer capacitance increased to about <NUM> pF/cell.

In <FIG>, the crosses illustrate the double layer capacitance Cdbl for the second device, which had an initial double layer capacitance of about <NUM> pF/cell after the removal of protective oxide (cap layer) using a wet etch process of <NUM> minutes in <NUM>:<NUM>:<NUM> BOE. After an additional <NUM>-minute treatment in <NUM>:<NUM>:<NUM> HNO<NUM>/HF, the double layer capacitance increased to about <NUM> pF/cell. Further, after a <NUM>-minute additional treatment in <NUM>:<NUM>:<NUM> HNO<NUM>/HF, the double layer capacitance increases to about <NUM> pF/cell. The variation in the initial double layer capacitances of the two devices are due to device variations.

As described above, continued treatment in <NUM>:<NUM>:<NUM> BOE poses the risk of over-etching the underlying dielectric layer (field oxide) in the device. However, treatment in <NUM>:<NUM>:<NUM> HNO<NUM>/HF is shown to effectively increase the double-layer capacitance of the porous electrode without causing excessive oxide loss in the underlying structures.

In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range, is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

As used herein and in the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a method" includes a plurality of such methods.

Claim 1:
A nanopore cell (<NUM>), comprising:
a substrate (<NUM>);
a conductive layer (<NUM>) disposed overlying a top portion of the substrate (<NUM>);
a first dielectric layer (<NUM>) overlying the conductive layer (<NUM>), the first dielectric laye (<NUM>) having an opening exposing a portion of the conductive layer (<NUM>),
an electrode layer (<NUM>) disposed in the opening of the first dielectric layer (<NUM>), the electrode layer (<NUM>) having an overhang portion (<NUM>) extending over the first dielectric layer (<NUM>),
a second dielectric layer (<NUM>) disposed on the first dielectric layer (<NUM>),
a cavity (<NUM>) in the second dielectric layer (<NUM>), the cavity (<NUM>) exposing at least a portion of the electrode layer (<NUM>), the cavity (<NUM>) including an undercut portion (<NUM>) of the second dielectric layer (<NUM>) above the overhang portion (<NUM>) of the electrode (<NUM>), and
a well formed by the cavity (<NUM>), the well having a bottom base (<NUM>) formed by a top surface of the electrode layer (<NUM>) and well sidewalls (<NUM>) formed by the second dielectric layer (<NUM>).