Patent Description:
The present invention relates generally to programmable logic devices and, more particularly, to power-on-reset signal generators for such devices.

Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.

PLDs may be used to control and/or be integrated with large array of different types of user devices, and both the PLDs and other circuitry and/or circuit elements of the user device can be subjected to a relatively wide range of different supply voltages (e.g., VCC, generally between <NUM>. 2v and <NUM>. 3v, +/- <NUM>%). Such supply voltages are typically stable during operation of the user device/PLD, but supply voltages can vary (e.g., ramp, or be set initially to one power on value and then ramp to an operational value) during a typical power on sequence for the user device and/or the PLD. Moreover, PLDs and/or other logic devices fabricated using advanced integrated circuit processes (e.g., <NUM> fully depleted silicon-on-insulator - FDSOI - processes) may be implemented with I/O transistors (e.g., relatively thick gate transistors) and/or other circuit elements that can only tolerate up to approximately <NUM>. 8v +/- <NUM>% (e.g., source/drain Vds, gate/source Vgs, gate/drain Vgd voltages) and guarantee an operational lifespan of at least <NUM> years without incurring reliability issues.

A prior art adaptive power-on-reset circuit can be seen in <CIT>.

However, there is a need in the art for systems and methods to provide supply voltage protections for PLDs, particularly during power on of a PLD and/or a user device controlled by and/or integrated with the PLD.

The present disclosure provides systems and methods for providing adaptive power on reset (POR) signal generation to protect a programmable logic device (PLD) and/or other circuit elements for use in or with various user devices for computing applications and architectures, as described herein. For example, semiconductor circuits are often located in systems or other devices that are turned on and off. While to a person, turning power on in (or providing power to) a device or system with semiconductor circuits in it can be seen as an instantaneous event, that is not strictly true within the timeframes and power domains of the system or device containing the semiconductor circuits. When a system or device is turned on, power may not be instantaneously available to every component in the device or may not be available at a desired level or stability for each and every component to operate. Devices and systems may hold semiconductor chips or components in a reset state until an appropriate power supply is available. A POR signal may be used to indicate availability of an appropriate power supply voltage for a particular chip or group of chips in a device or system. A given POR signal may be generated by a particular chip for itself, for example, or may be generated for use by a number of chips, as described herein.

In various embodiments described herein, it is desirable to allow a chip, or certain portions of a chip, or a system, to turn on as quickly as possible. However, allowing a chip or other circuitry to turn on before it has a suitable power source risks causing malfunction or damage to that circuitry and/or the chip. Moreover, particularly with respect to a PLD or other circuit element meant to be integrated with a variety of different user devices and/or according to a variety of different applications, such chip may be provided multiple supply voltages, and in various embodiments, adaptive POR signal generators described herein provide for targeting relatively fast turn-on of certain portions of a chip (or of a subset of circuitry in a chip, device or system). Such aspects include situations where it is desirable to speed up system configuration, bring up I/O functionality, and/or begin configuration of a device, or to begin to initiate control functionality. For some applications (such as where certain parts of a chip may turn on before others (e.g., such as I/O circuitry before a core logic portion), allowing POR release too early can cause a current inrush while other supplies are ramping, which can damage and/or otherwise reduce the lifetime of circuitry.

Providing a relatively simple fixed delay (such as based one worst case expected voltage ramp) from initially detecting application of a voltage to an integrated circuit before generating a POR signal does not permit adaptability to fast ramping and/or variable ramping power supplies. An integrated circuit that has a voltage rail or power supplied from a fast ramping supply could potentially turn on sooner if provided a POR signal that could adaptively support both slow and fast-ramping power supplies. However, it is not necessarily desired to design a user device or chip to always require a fast-ramping power supply because such power supplies may be more expensive, require more strict design rules, and/or may have other relatively complex design constraints. Therefore, it is desirable to employ an adaptive POR signal generator, according to embodiments described herein, that can adapt to a variety of power supply slew rates/ramp rates when generating a POR signal. Integrated circuits including an adaptive POR signal generator are therefore significantly more flexible than conventional circuit elements with respect to common system design constraints, including both overall system cost and performance.

In one embodiment, an integrated circuit can turn on certain input/output (I/O) circuits sooner with an adaptive POR signal generator, as described herein, which can generally increase overall system performance, security (e.g., by ensuring security measures are functioning before elements of the system are compromisable in-situ), and reliability (e.g., by helping to ensure circuits aren't damaged or otherwise degraded over time by power on events). Such integrated/semiconductor circuits according to the present disclosure can be any one or combination of Application Specific Integrated Circuits (ASICs), System on Chip (SOCs), PLDs (including Field Programmable Gate Arrays (FPGAs)). In various embodiments, an adaptive POR signal generator as described herein may be configured to generate a POR signal for a part of an integrated circuit (e.g., one or more power or voltage domains on one chip), an entire integrated circuit located on one substrate, or multiple integrated circuits across multiple substrates that could be located in the same package, such as with Through Silicon Via (TSV) technology, side-by-side packages connected via interconnect, or other such technologies, or multiple integrated circuits in different chips. Multiple functional elements in an SOC could receive a POR signal generated according to the present disclosure, as described herein.

For example, PLDs can be integrated into and/or configured to control a wide array of different user devices, each with varying supply voltage requirements, generally selected to be one or more of <NUM>. 5v, and <NUM>. To increase flexibility of a particular PLD, each user device or PLD may be implemented with an adaptive POR signal generator configured to prevent the PLD, elements of the PLD, and/or other elements of the user device from operating before the supply voltage reaches a minimum compatible operating voltage, including during power on states, where the various supply voltages provided to the PLD and/or other elements of the user device ramp to their operating levels.

In general, an adaptive POR signal generator may be implemented by a logic device/controller configured to measure a ramp rate of a supply voltage prior to the supply voltage reaching its nominal operating voltage and generate a POR signal roughly coincident with the supply voltage reaching its nominal operating voltage based, at least in part, on the measured ramp rate and/or ramp rate characteristics. In particular embodiments, an adaptive POR signal generator may include a counter or other timing device, for example, and the logic device may be configured to use the counter to measure a ramp time between at least first and second ramp voltages of the supply voltage and generate the POR signal based, at least in part, on that ramp time measurement, where the first and second ramp voltages of the supply voltage are selected to be lower than the nominal operating voltage.

As described herein, a POR signal generator may be coupled to and/or integrated with a PLD, which may itself include various circuit elements and/or a user design configured to facilitate operation of the POR signal generator and/or a coupled user device. In accordance with embodiments set forth herein, techniques are provided to manage implementation of user designs in PLDs. In various embodiments, a user design may be converted into and/or represented by a set of PLD components (e.g., configured for logic, arithmetic, or other hardware functions) and their associated interconnections available in a PLD. For example, a PLD may include a number of programmable logic blocks (PLBs), each PLB including a number of logic cells, and configurable routing resources that may be used to interconnect the PLBs and/or logic cells. In some embodiments, each PLB may be implemented with between <NUM> and <NUM> or between <NUM> and <NUM> logic cells.

In general, a PLD (e.g., an FPGA) fabric includes one or more routing structures and an array of similarly arranged logic cells arranged within programmable function blocks (e.g., PFBs and/or PLBs). The purpose of the routing structures is to programmably connect the ports of the logic cells/PLBs to one another in such combinations as necessary to achieve an intended functionality. A remote PLD may include various additional "hard" engines or modules configured to provide a range of remote management functionality that may be linked to operation of the PLD fabric to provide configurable computing functionality and/or architectures. Routing flexibility and configurable function embedding may be used when synthesizing, mapping, placing, and/or routing a user design into a number of PLD components. As a result of various user design optimization processes, a user design can be implemented relatively efficiently, thereby freeing up configurable PLD components that would otherwise be occupied by additional operations and routing resources. In some embodiments, an optimized user design may be represented by a netlist that identifies various types of components provided by the PLD and their associated signals. In embodiments that produce a netlist of the converted user design, the optimization process may be performed on such a netlist. Once optimized, such configuration may be loaded into a PLD and the PLD may boot and execute the configuration, which may include the use of various I/O buses to communicate with a user device, as described herein.

Referring now to the drawings, <FIG> illustrates a block diagram of a PLD <NUM> in accordance with an embodiment of the disclosure. PLD <NUM> (e.g., a field programmable gate array (FPGA)), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other type of programmable device) generally includes input/output (I/O) blocks <NUM> and logic blocks <NUM> (e.g., also referred to as programmable logic blocks (PLBs), programmable functional units (PFUs), or programmable logic cells (PLCs)). More generally, the individual elements of PLD <NUM> may be referred to as a PLD fabric.

I/O blocks <NUM> provide I/O functionality (e.g., to support one or more I/O and/or memory interface standards) for PLD <NUM>, while programmable logic blocks <NUM> provide logic functionality (e.g., LUT-based logic or logic gate array-based logic) for PLD <NUM>. Additional I/O functionality may be provided by serializer/deserializer (SERDES) blocks <NUM> and physical coding sublayer (PCS) blocks <NUM>. PLD <NUM> may also include hard intellectual property core (IP) blocks <NUM> to provide additional functionality (e.g., substantially predetermined functionality provided in hardware which may be configured with less programming than logic blocks <NUM>).

PLD <NUM> may also include blocks of memory <NUM> (e.g., blocks of EEPROM, block SRAM, and/or flash memory), clock-related circuitry <NUM> (e.g., clock sources, PLL circuits, and/or DLL circuits), and/or various routing resources <NUM> (e.g., interconnect and appropriate switching logic to provide paths for routing signals throughout PLD <NUM>, such as for clock signals, data signals, or others) as appropriate. In general, the various elements of PLD <NUM> may be used to perform their intended functions for desired applications, as would be understood by one skilled in the art.

For example, certain I/O blocks <NUM> may be used for programming memory <NUM> or transferring information (e.g., various types of user data and/or control signals) to/from PLD <NUM>. Other I/O blocks <NUM> include a first programming port (which may represent a central processing unit (CPU) port, a peripheral data port, an SPI interface, and/or a sysCONFIG programming port) and/or a second programming port such as a joint test action group (JTAG) port (e.g., by employing standards such as Institute of Electrical and Electronics Engineers (IEEE) <NUM> or <NUM> standards). In various embodiments, I/O blocks <NUM> may be included to receive configuration data and commands (e.g., over one or more connections <NUM>) to configure PLD <NUM> for its intended use and to support serial or parallel device configuration and information transfer with SERDES blocks <NUM>, PCS blocks <NUM>, hard IP blocks <NUM>, and/or logic blocks <NUM> as appropriate.

It should be understood that the number and placement of the various elements are not limiting and may depend upon the desired application. For example, various elements may not be required for a desired application or design specification (e.g., for the type of programmable device selected). Furthermore, it should be understood that the elements are illustrated in block form for clarity and that various elements would typically be distributed throughout PLD <NUM>, such as in and between logic blocks <NUM>, hard IP blocks <NUM>, and routing resources (e.g., routing resources <NUM> of <FIG>) to perform their conventional functions (e.g., storing configuration data that configures PLD <NUM> or providing interconnect structure within PLD <NUM>). It should also be understood that the various embodiments disclosed herein are not limited to programmable logic devices, such as PLD <NUM>, and may be applied to various other types of programmable devices, as would be understood by one skilled in the art.

An external system <NUM> may be used to create a desired user configuration or design of PLD <NUM> and generate corresponding configuration data to program (e.g., configure) PLD <NUM>. For example, system <NUM> may provide such configuration data to one or more I/O blocks <NUM>, SERDES blocks <NUM>, and/or other portions of PLD <NUM>. As a result, programmable logic blocks <NUM>, various routing resources, and any other appropriate components of PLD <NUM> may be configured to operate in accordance with user-specified applications.

In the illustrated embodiment, system <NUM> is implemented as a computer system. In this regard, system <NUM> includes, for example, one or more processors <NUM> which may be configured to execute instructions, such as software instructions, provided in one or more memories <NUM> and/or stored in non-transitory form in one or more non-transitory machine-readable mediums <NUM> (e.g., which may be internal or external to system <NUM>). For example, in some embodiments, system <NUM> may run PLD configuration software, such as Lattice Diamond System Planner software available from Lattice Semiconductor Corporation to permit a user to create a desired configuration and generate corresponding configuration data to program PLD <NUM>.

System <NUM> also includes, for example, a user interface <NUM> (e.g., a screen or display) to display information to a user, and one or more user input devices <NUM> (e.g., a keyboard, mouse, trackball, touchscreen, and/or other device) to receive user commands or design entry to prepare a desired configuration of PLD <NUM>.

<FIG> illustrates a block diagram of a logic block <NUM> of PLD <NUM> in accordance with an embodiment of the disclosure. As discussed, PLD <NUM> includes a plurality of logic blocks <NUM> including various components to provide logic and arithmetic functionality. In the example embodiment shown in <FIG>, logic block <NUM> includes a plurality of logic cells <NUM>, which may be interconnected internally within logic block <NUM> and/or externally using routing resources <NUM>. For example, each logic cell <NUM> may include various components such as: a lookup table (LUT) <NUM>, a mode logic circuit <NUM>, a register <NUM> (e.g., a flip-flop or latch), and various programmable multiplexers (e.g., programmable multiplexers <NUM> and <NUM>) for selecting desired signal paths for logic cell <NUM> and/or between logic cells <NUM>. In this example, LUT <NUM> accepts four inputs 220A-220D, which makes it a four-input LUT (which may be abbreviated as "<NUM>-LUT" or "LUT4") that can be programmed by configuration data for PLD <NUM> to implement any appropriate logic operation having four inputs or less. Mode Logic <NUM> may include various logic elements and/or additional inputs, such as input 220E, to support the functionality of various modes, as described herein. LUT <NUM> in other examples may be of any other suitable size having any other suitable number of inputs for a particular implementation of a PLD. In some embodiments, different size LUTs may be provided for different logic blocks <NUM> and/or different logic cells <NUM>.

An output signal <NUM> from LUT <NUM> and/or mode logic <NUM> may in some embodiments be passed through register <NUM> to provide an output signal <NUM> of logic cell <NUM>. In various embodiments, an output signal <NUM> from LUT <NUM> and/or mode logic <NUM> may be passed to output <NUM> directly, as shown. Depending on the configuration of multiplexers <NUM>-<NUM> and/or mode logic <NUM>, output signal <NUM> may be temporarily stored (e.g., latched) in latch <NUM> according to control signals <NUM>. In some embodiments, configuration data for PLD <NUM> may configure output <NUM> and/or <NUM> of logic cell <NUM> to be provided as one or more inputs of another logic cell <NUM> (e.g., in another logic block or the same logic block) in a staged or cascaded arrangement (e.g., comprising multiple levels) to configure logic operations that cannot be implemented in a single logic cell <NUM> (e.g., logic operations that have too many inputs to be implemented by a single LUT <NUM>). Moreover, logic cells <NUM> may be implemented with multiple outputs and/or interconnections to facilitate selectable modes of operation, as described herein.

Mode logic circuit <NUM> may be utilized for some configurations of PLD <NUM> to efficiently implement arithmetic operations such as adders, subtractors, comparators, counters, or other operations, to efficiently form some extended logic operations (e.g., higher order LUTs, working on multiple bit data), to efficiently implement a relatively small RAM, and/or to allow for selection between logic, arithmetic, extended logic, and/or other selectable modes of operation. In this regard, mode logic circuits <NUM>, across multiple logic cells <NUM>, may be chained together to pass carry-in signals <NUM> and carry-out signals <NUM>, and/or other signals (e.g., output signals <NUM>) between adjacent logic cells <NUM>, as described herein. In the example of <FIG>, carry-in signal <NUM> may be passed directly to mode logic circuit <NUM>, for example, or may be passed to mode logic circuit <NUM> by configuring one or more programmable multiplexers, as described herein. In some embodiments, mode logic circuits <NUM> may be chained across multiple logic blocks <NUM>.

Logic cell <NUM> illustrated in <FIG> is merely an example, and logic cells <NUM> according to different embodiments may include different combinations and arrangements of PLD components. Also, although <FIG> illustrates logic block <NUM> having eight logic cells <NUM>, logic block <NUM> according to other embodiments may include fewer logic cells <NUM> or more logic cells <NUM>. Each of the logic cells <NUM> of logic block <NUM> may be used to implement a portion of a user design implemented by PLD <NUM>. In this regard, PLD <NUM> may include many logic blocks <NUM>, each of which may include logic cells <NUM> and/or other components which are used to collectively implement the user design.

As further described herein, portions of a user design may be adjusted to occupy fewer logic cells <NUM>, fewer logic blocks <NUM>, and/or with less burden on routing resources <NUM> when PLD <NUM> is configured to implement the user design. Such adjustments according to various embodiments may identify certain logic, arithmetic, and/or extended logic operations, to be implemented in an arrangement occupying multiple embodiments of logic cells <NUM> and/or logic blocks <NUM>. As further described herein, an optimization process may route various signal connections associated with the arithmetic/logic operations described herein, such that a logic, ripple arithmetic, or extended logic operation may be implemented into one or more logic cells <NUM> and/or logic blocks <NUM> to be associated with the preceding arithmetic/logic operations.

<FIG> illustrates a design process <NUM> for a PLD in accordance with an embodiment of the disclosure. For example, the process of <FIG> may be performed by system <NUM> running Lattice Diamond software to configure PLD <NUM>. In some embodiments, the various files and information referenced in <FIG> may be stored, for example, in one or more databases and/or other data structures in memory <NUM>, machine readable medium <NUM>, and/or otherwise. In various embodiments, such files and/or information may be encrypted or otherwise secured when stored and/or conveyed to PLD <NUM> and/or other devices or systems.

In operation <NUM>, system <NUM> receives a user design that specifies the desired functionality of PLD <NUM>. For example, the user may interact with system <NUM> (e.g., through user input device <NUM> and hardware description language (HDL) code representing the design) to identify various features of the user design (e.g., high level logic operations, hardware configurations, and/or other features). In some embodiments, the user design may be provided in a register transfer level (RTL) description (e.g., a gate level description). System <NUM> may perform one or more rule checks to confirm that the user design describes a valid configuration of PLD <NUM>. For example, system <NUM> may reject invalid configurations and/or request the user to provide new design information as appropriate.

In operation <NUM>, system <NUM> synthesizes the design to create a netlist (e.g., a synthesized RTL description) identifying an abstract logic implementation of the user design as a plurality of logic components (e.g., also referred to as netlist components), which may include both programmable components and hard IP components of PLD <NUM>. In some embodiments, the netlist may be stored in Electronic Design Interchange Format (EDIF) in a Native Generic Database (NGD) file.

In some embodiments, synthesizing the design into a netlist in operation <NUM> may involve converting (e.g., translating) the high-level description of logic operations, hardware configurations, and/or other features in the user design into a set of PLD components (e.g., logic blocks <NUM>, logic cells <NUM>, and other components of PLD <NUM> configured for logic, arithmetic, or other hardware functions to implement the user design) and their associated interconnections or signals. Depending on embodiments, the converted user design may be represented as a netlist.

In some embodiments, synthesizing the design into a netlist in operation <NUM> may further involve performing an optimization process on the user design (e.g., the user design converted/translated into a set of PLD components and their associated interconnections or signals) to reduce propagation delays, consumption of PLD resources and routing resources, and/or otherwise optimize the performance of the PLD when configured to implement the user design. Depending on embodiments, the optimization process may be performed on a netlist representing the converted/translated user design. Depending on embodiments, the optimization process may represent the optimized user design in a netlist (e.g., to produce an optimized netlist).

In some embodiments, the optimization process may include optimizing certain instances of a logic function operation, a ripple arithmetic operation, and/or an extended logic function operation which, when a PLD is configured to implement the user design, would occupy a plurality of configurable PLD components (e.g., logic cells <NUM>, logic blocks <NUM>, and/or routing resources <NUM>). For example, the optimization process may include detecting multiple mode or configurable logic cells implementing logic function operations, ripple arithmetic operations, extended logic function operations, and/or corresponding routing resources in the user design, interchanging operational modes of logic cells implementing the various operations to reduce the number of PLD components and/or routing resources used to implement the operations and/or to reduce the propagation delay associated with the operations, and/or reprogramming corresponding LUTs and/or mode logic to account for the interchanged operational modes.

In another example, the optimization process may include detecting extended logic function operations and/or corresponding routing resources in the user design, implementing the extended logic operations into multiple mode or convertible logic cells with single physical logic cell outputs, routing or coupling the logic cell outputs of a first set of logic cells to the inputs of a second set of logic cells to reduce the number of PLD components used to implement the extended logic operations and/or routing resources and/or to reduce the propagation delay associated with the extended logic operations, and/or programming corresponding LUTs and/or mode logic to implement the extended logic function operations with at least the first and second sets of logic cells.

In another example, the optimization process may include detecting multiple mode or configurable logic cells implementing logic function operations, ripple arithmetic operations, extended logic function operations, and/or corresponding routing resources in the user design, interchanging operational modes of logic cells implementing the various operations to provide a programmable register along a signal path within the PLD to reduce propagation delay associated with the signal path, and reprogramming corresponding LUTs, mode logic, and/or other logic cell control bits/registers to account for the interchanged operational modes and/or to program the programmable register to store or latch a signal on the signal path.

In operation <NUM>, system <NUM> performs a mapping process that identifies components of PLD <NUM> that may be used to implement the user design. In this regard, system <NUM> may map the optimized netlist (e.g., stored in operation <NUM> as a result of the optimization process) to various types of components provided by PLD <NUM> (e.g., logic blocks <NUM>, logic cells <NUM>, embedded hardware, and/or other portions of PLD <NUM>) and their associated signals (e.g., in a logical fashion, but without yet specifying placement or routing). In some embodiments, the mapping may be performed on one or more previously-stored NGD files, with the mapping results stored as a physical design file (e.g., also referred to as an NCD file). In some embodiments, the mapping process may be performed as part of the synthesis process in operation <NUM> to produce a netlist that is mapped to PLD components.

In operation <NUM>, system <NUM> performs a placement process to assign the mapped netlist components to particular physical components residing at specific physical locations of the PLD <NUM> (e.g., assigned to particular logic cells <NUM>, logic blocks <NUM>, routing resources <NUM>, and/or other physical components of PLD <NUM>), and thus determine a layout for the PLD <NUM>. In some embodiments, the placement may be performed on one or more previously-stored NCD files, with the placement results stored as another physical design file.

In operation <NUM>, system <NUM> performs a routing process to route connections (e.g., using routing resources <NUM>) among the components of PLD <NUM> based on the placement layout determined in operation <NUM> to realize the physical interconnections among the placed components. In some embodiments, the routing may be performed on one or more previously-stored NCD files, with the routing results stored as another physical design file.

In various embodiments, routing the connections in operation <NUM> may further involve performing an optimization process on the user design to reduce propagation delays, consumption of PLD resources and/or routing resources, and/or otherwise optimize the performance of the PLD when configured to implement the user design. The optimization process may in some embodiments be performed on a physical design file representing the converted/translated user design, and the optimization process may represent the optimized user design in the physical design file (e.g., to produce an optimized physical design file).

Changes in the routing may be propagated back to prior operations, such as synthesis, mapping, and/or placement, to further optimize various aspects of the user design.

Thus, following operation <NUM>, one or more physical design files may be provided which specify the user design after it has been synthesized (e.g., converted and optimized), mapped, placed, and routed (e.g., further optimized) for PLD <NUM> (e.g., by combining the results of the corresponding previous operations). In operation <NUM>, system <NUM> generates configuration data for the synthesized, mapped, placed, and routed user design. In various embodiments, such configuration data may be encrypted, signed, and/or otherwise protected as part of such generation process, as described more fully herein. In operation <NUM>, system <NUM> configures PLD <NUM> with the configuration data by, for example, loading a configuration data bitstream (e.g., a "configuration" or "configuration image") into PLD <NUM> over connection <NUM>. Such configuration may be provided in an encrypted, signed, or unsecured/unauthenticated form, for example, and PLD <NUM> may be configured to treat secured and unsecured configurations differently, as described herein.

<FIG> illustrates a block diagram of a user device <NUM> including a PLD <NUM> and one or more adaptive power on reset (POR) signal generators <NUM> in accordance with an embodiment of the disclosure. In various embodiments, user device <NUM> may include power supply <NUM>, adaptive POR signal generator <NUM>, and one or more electronic components facilitating operation of user device <NUM>, such as PLD <NUM>, communication module <NUM>, and other user device modules <NUM> configured to facilitate remote management of PLD <NUM>, for example, or to facilitate a particular user device application, as described herein. In various embodiments, user device <NUM> may be implemented as a smart phone, a laptop computer, a tablet computer, a desktop computer, a smart environmental sensor, a home automation device (e.g., sensor and/or actuator), a network management device, a smart display or television, an automobile user interface, and/or other user device, as described herein. More generally, user device <NUM> may be implemented as an embedded device or any other computing or electronic device integrable with one or more of PLD <NUM>.

As shown in <FIG>, power supply <NUM> may be configured to provide one or more supply voltages (e.g., one or more VCCs, VAUXs) to various components of user device <NUM> over power buses <NUM>. For example, power supply <NUM> may be implemented as a battery or battery bank, for example, with integrated charging and monitoring electronics. In other embodiments, power supply <NUM> may be configured to receive grid or other external power and include various power conditioning, regulating, and/or conversion components configured to provide the appropriate operating voltage for each component of user device <NUM> using one or more of power buses <NUM>. Power buses <NUM> may be include one or more conductive wires and/or traces configured to convey such supply voltages to the various components, as shown, and may in some embodiments include signaling traces configured to transmit and receive logic signals/data facilitating operation of power supply <NUM>, user device <NUM>, and/or the various elements of user device <NUM>. In some embodiments, power buses <NUM> may be configured to provide the same supply voltages to one or more adaptive POR generators <NUM>, as shown.

In various embodiments, adaptive POR signal generator <NUM> may be configured to receive one or more supply voltages from power supply <NUM> over a power bus <NUM> and generate a POR signal configured to release a restart state of one or more components of user device <NUM> approximately when a corresponding supply voltage reaches a minimum compatible operating voltage for the one or more components. As shown in <FIG>, in some embodiments, such POR signal may be conveyed to each component via POR signal buses <NUM>, and each device may include circuitry configured to maintain a reset or power safe state of the component until a POR signal is received over POR signal bus <NUM>. For example, a POR signal may be a logic signal that transitions (e.g., from high to low, from low to high, from low to high to low, etc.) to release such restart state, and the corresponding component receiving such signal may be configured to latch or store such restart release state until user device <NUM> and/or power supply <NUM> are power cycled, for example, or adaptive POR signal generator <NUM> generates a forced reset signal (e.g., a separate logic signal transition also conveyed over POR signal buses <NUM>) configured to force corresponding components back into a reset state, as described herein.

In some embodiments, each component may include its own optional adaptive POR signal generator <NUM>, for example, so as to increase the design flexibility of the individual component with respect to power supply performance characteristics, operating voltages, and corresponding ramp times. More generally, user device <NUM> may include any combination of adaptive POR signal generators <NUM> configured to protect operation of user device <NUM> and elements of user device <NUM>, for example, and, at the same time maintain relatively high system performance by minimizing the delay between power on of power supply <NUM> and operation of user device <NUM> and/or individual elements of user device <NUM> (e.g., minimize boot time under variable conditions).

As shown in <FIG>, PLD <NUM> may be implemented by elements similar to those described with respect to PLD <NUM> in <FIG>, and/or with additional configurable and/or hard IP elements configured to facilitate operation of PLD <NUM> in a particular computing application and/or architecture, as described herein. In particular, PLD <NUM> may include a PLD fabric <NUM> linked by various buses to a non-volatile memory (NVM) <NUM>, a programmable I/O <NUM>, and/or other integrated circuit (IC) modules <NUM>, all implemented on a monolithic IC, as shown. In general, PLD fabric <NUM> may be implemented by any of the various elements described with respect to PLD <NUM> and may be configured using a design process similar to design process <NUM> described in relation to <FIG> to generate and program PLD fabric <NUM> according to a desired configuration. In some embodiments, PLD <NUM> may include one or more adaptive POR signal generators <NUM> (e.g., as one or more hard IP components integrated with PLD <NUM>).

NVM <NUM> may be implemented as a hard IP resource configured to provide securable and/or non-volatile storage of data used to facilitate operation of PLD <NUM>. NVM <NUM> may include multiple differentiated sectors, such as one or more configuration image sectors, a device key sector (e.g., an AES key sector and a separate public key/key pair sector), a user flash memory (UFM) sector, and/or other defined storage sectors. Configuration image sectors may each store a configuration for PLD fabric <NUM>, for example, so as to allow them to be selected (e.g., based on version or date) and used to program PLD fabric <NUM>. A trim sector may be used to store manufacturer trim, device identifier, device category identifier, and/or other data specific to a particular PLD <NUM>, for example, such as a modifiable customer-specific ordering part number and/or a generated customer ID number. Device key sectors may be used to store encryption/decryption keys, public/private keys, and/or other security keys specific to a particular PLD <NUM>. UFM sectors may be used to store user data generally accessible by PLD fabric <NUM>, such as configurations or application-specific security keys, certificates, and/or other secure(d) user data. Any one or more individual elements, portions, or sectors of NVM <NUM> may be implemented as configurable memory, for example, or one-time programmable (OTP) memory, as described herein.

Programmable I/O <NUM> may be implemented as at least partially configurable resources and/or hard IP resources configured to provide or support a communications link between PLD fabric <NUM> and an external controller, memory, and/or other device, such as communication module <NUM>, for example, across bus <NUM> (e.g., a bus configured to link portions of PLD fabric <NUM> to programmable I/O <NUM> and/or NVM <NUM>) and according to one or more external bus interfaces, protocols, and/or bus supply voltages (e.g., external bus interface <NUM>). Programmable I/O <NUM> may also be configured to support communications between PLD fabric <NUM> and/or NVM <NUM> across bus <NUM> and/or external bus interface <NUM> with communication module <NUM>, for example, in addition or as an alternative to external system130/machine readable medium <NUM>, as described herein.

In some embodiments, bus <NUM> and/or programmable I/O <NUM> may be integrated with PLD fabric <NUM>. More generally, one or more elements of PLD <NUM> shown as separate in <FIG> may be integrated with and/or within each other. Other IC modules <NUM> may be implemented as hard and/or configurable IP resources configured to facilitate operation of PLD <NUM>. For example, other IC modules <NUM> may include a security engine implemented as a hard IP resource configured to provide various security functions for use by PLD fabric <NUM> and/or user device <NUM>, a configuration engine implemented as a hard IP resource configured to manage the configurations of and/or communications amongst the various elements of PLD <NUM>, including to manage or control configurations of elements of PLD <NUM>, boot of PLD fabric <NUM>, and flow control throughout PLD <NUM>, one or more additional external access busses implemented according to one or more of a JTAG, I2C, SPI, and/or other external access bus or protocol, for example, configured to provide access to and/or from communication module <NUM> and/or other user device modules <NUM>.

Communication module <NUM> may be implemented as a network communications IC configured to form communications links to a remote external device used to manage operation of PLD <NUM>. For example, in some embodiments, communication module <NUM> may be implemented as a wireless communication module configured to support a wired and/or wireless communications link (e.g., formed according to WiFi, Bluetooth, Zigbee, Zwave, near-field communication (NFC), cellular, Ethernet, and/or other open and/or proprietary wired and/or wireless communication protocols) to a communications network, as described herein. In such embodiments, communication module <NUM> may be configured to manage various security features of such wired and/or wireless communications link (e.g., establishing communications link credentials, employing communications link credentials to establish a communications link, negotiating encryption keys for encrypted communications tunnels established over such communications link, such as transport layer security (TLS)), for example, and/or may be configured to be controlled by PLD <NUM> and/or other user device module <NUM> to manage such security features.

Other user device modules <NUM> may include various computing, sensor, and/or actuator elements configured to implement a particular user device application, for example, such as a remote sensor application, a remote controller application, and/or a remote computing application, as described herein. Other user device modules <NUM> may also include various other communication buses, power storage and delivery elements, user interfaces (e.g., buttons, keyboard, mouse, track pad, and/or displays/touch screen displays) to support such user device applications. In one embodiment, other user device modules <NUM> includes an electrical characteristic sensor configured to detect and/or measure an electrical state of a transducer element (e.g., also an element of other user device modules <NUM>) that is used to measure an environmental condition associated with user device <NUM>. In another embodiment, other user device modules <NUM> includes various electronic devices typically found within a smart phone, a laptop computer, a tablet computer, and/or a desktop computer.

<FIG> illustrates a block diagram of adaptive POR signal generator <NUM> in accordance with an embodiment of the disclosure. Operation of adaptive POR signal generator <NUM> in <FIG> will be described with respect to an example supply voltage (or a voltage derived from a supply voltage) that is nominally about <NUM>. 9v when fully ramped. However, embodiments are adaptable to any supply voltage, and any particular values are merely examples from which those of ordinary skill in the art can understand how to apply aspects of the disclosure to other implementations. An example supply voltage can be referred to as VCC. In general operation, the supply voltage (e.g., a VCC) that is ramping is sampled (e.g., referred to herein also as a ramp voltage when sampled during ramp, according to various different sampling techniques) as it increases from a relatively low first threshold ramp voltage (e.g., Vl ~ <NUM>. 38v) to a relatively high second threshold ramp voltage (e.g., Vh ~ <NUM>. 58v) in order to characterize a ramp time required to ramp through the monitored supply voltage range.

In general, both the first threshold ramp voltage Vl and the second threshold ramp voltage Vh should be less than the desired fully ramped supply voltage (e.g., the minimum compatible operating voltage for the corresponding component). The first threshold voltage level Vl can be selected to be high enough to avoid an early turn on period of power supply <NUM> in which there may be transients or other undesirable and/or unreliable power supply behavior. In various embodiments, the ramp time can be characterized by counting transitions of an embedded oscillator/clock source with a known frequency Fon. A time for each transition, or a count based on a number of such transitions, can be determined based on the known clock frequency Fon. In some implementations, an assumption of monotonic ramping of the supply voltage may be made or required in order to characterize both the ramp time and any delay needed to properly generate a resulting POR signal, as described herein.

In embodiments including a counter as the timing device, in order to appropriately delay generation of a POR signal, the value of the counter when VCC has ramped to Vh can be used as the basis for determining when the POR signal should be generated. In some embodiments, if the count was started at zero to represent the ramp time of ramping between Vl and Vh, then the POR signal delay to release reset (e.g., to generate the POR signal) may be calculated based on how far Vh is away from a desired fully-ramped operating voltage, for example, or a value at which the circuit or portion thereof can operate). For instance, if the operating voltage value for supply voltage VCC is desired/expected to be <NUM>. 98v, then the POR signal should be generated (reset released) when VCC is about <NUM>. Assuming a linear ramp rate for supply voltage VCC, if Vl=<NUM>. 38v and Vh=<NUM>. 58v (meaning a change in voltage level of about <NUM>. 2v), then the voltage change between Vh and the final value of VCC is about <NUM> volts or twice the voltage difference between the two threshold ramp voltages Vl and Vh. Therefore, under such conditions, the POR signal delay between reaching Vh and POR signal generation should be about twice the ramp time between VCC reaching Vl and then reaching Vh.

In one embodiment, the value of the counter when VCC reaches Vh (e.g., a ramp time count, at a given counter frequency, Fon) may be used to implement the POR signal delay (e.g., in this numerical example, by doubling the count value or halving the Fon frequency), for example, and may be used to determine precisely when to generate the POR signal. For instance, in some embodiments, the POR signal can be generated by counting down from the counter value (e.g., the determined ramp time count) at a frequency of Fon/<NUM> based on the above-described voltages and a linear ramp assumption. More generally, other values for Vl and Vh can be selected, and/or Fon can be selected based on a number of bits to be allocated or available for the counter. Also, the POR signal delay to POR signal generation may be adjusted by modifying the countdown frequency or modifying the count value. Countdown frequency can be modified by changing a resistance value for the counter and/or clock source/oscillator, which may be done (e.g., at manufacture) by selecting from among several resistances, by changing a metal layer, or other appropriate means (e.g., laser trimming), or by implementing a variable resistor or other programmable circuit element (e.g., which may be adjusted programmatically during operation of adaptive POR signal generator <NUM>). In various embodiments, a POR signal delay can be modified to account for process and temperature variations, for example, which may be monitored and provided to adaptive POR signal generator <NUM> over power supply buses <NUM> and/or POR signal buses <NUM>. A margin of safety or other POR signal delay adjustment can be modified on an ongoing basis based on observed or possible non-linearities in ramp rates of VCC, for example, and the POR signal delay may be determined based on any linear or nonlinear ramp rate profile produced by and/or expected from power supply <NUM>, for example, and/or measured by adaptive POR signal generator <NUM>, as described herein.

In some embodiments, adaptive POR signal generator <NUM> may be implemented to be simple and robust. The example implementation architecture presented in <FIG> illustrates aspects of the disclosure that provide POR signal generation (reset release) with adaptive timing based on voltage ramp rate in a relatively simple, compact, reliable, and low power embodiment. For example, the embodiment of adaptive POR signal generator <NUM> depicted in <FIG> may be used with any or multiple supply voltages - internally and/or externally sourced or generated, and an amount of POR signal delay may be ramping rate dependent. With the example voltage values disclosed above, and a fast ramping (<NUM>/v), POR signal delay in this example would be near <NUM> (microseconds), while with slow ramping (<NUM>/v), POR signal delay would be around <NUM>. The POR signal delay can be varied by varying oscillator frequency. An amount of POR signal delay supported can be varied by changing the number of available bits of the counter. The available oscillator frequencies can be varied by modifying resistance (metal option) or bondout option, for example. Output of the POR signal on POR signal bus <NUM> can be further processed (for example, OR-ed and/or AND'ed with one or more other signals) as required for the particular application of the POR signal being generated. A number of bits in the counter can be selected based on the maximum necessary or desired or expected POR signal delay to be supported. In one example, a <NUM>-bit counter is sufficient to support a maximum POR signal delay required for a minimum allowable ramp rate (e.g., where ramp rates lower than the minimum allowable ramp rate tend to indicate a malfunctioning power supply <NUM>). A timeout feature can be included, where if the ramping supply/ramp voltage does not reach the second threshold ramp voltage Vh within a required time period (which can be indicated by the counter rolling over and generating an overflow logic signal), then a system/power supply/chip/POR signal generator restart signal can be generated to attempt a system/power supply/chip/POR signal generator restart, generate an alert, and/or power down. In various embodiments, a monotonic voltage ramp in the monitored power supply voltage is assumed, but in alternative embodiments, relatively noisy DC supply voltages and/or AC supply voltages may be accommodated by including appropriate filtering and/or monitoring circuitry (e.g., AC voltage peak monitoring circuitry) within adaptive POR signal generator <NUM>.

<FIG> depicts circuitry of adaptive POR signal generator <NUM> that can be formed in a semiconductor as an integrated circuit or part of one. Such integrated circuit can be one integrated circuit of a number of separate and/or interconnected circuits formed on such semiconductor. In the embodiment depicted in <FIG>, in general operation, a reference voltage <NUM> is produced by a reference voltage generator <NUM>, which may then be supplied to ramp traversal detector <NUM>. Ramp traversal detector <NUM> may then generate a ramp traversal signal <NUM> and provide it to controller <NUM>, which may be configured to determine an appropriate POR signal delay with which to generate a POR signal on POR signal bus <NUM>.

Controller <NUM> may be may be implemented as any appropriate logic device (e.g., processing device, microcontroller, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), memory storage device, memory reader, or other device or combinations of devices) that may be adapted to execute, store, and/or receive appropriate instructions, such as software instructions implementing a control loop for controlling various operations of adaptive POR signal generator <NUM>, for example. Such software instructions may also implement methods for querying devices for operational parameters, selecting operational parameters for devices, or performing any of the various operations described herein (e.g., operations performed by logic devices of various devices of adaptive POR signal generator <NUM>). In addition, controller <NUM> may be implemented with a machine-readable medium for storing non-transitory instructions for loading into and execution by controller <NUM>. In these and other embodiments, controller <NUM> may be implemented with other components where appropriate, such as volatile memory, non-volatile memory, one or more interfaces, and/or various analog and/or digital components for interfacing with devices of adaptive POR signal generator <NUM> and/or user device <NUM>.

As shown in <FIG>, reference voltage generator <NUM> may be implemented by a current mirror <NUM> that can be enabled/turned on by bandgap transistor structure <NUM> and a linear resistor array <NUM> configured to provide a selected reference voltage based on the current output of current mirror <NUM>. In some embodiments, current mirror <NUM> may be coupled to and/or powered by any available supply voltage, such as VCC and/or VAUX, for example, at inputs <NUM> and <NUM>, and bandgap transistor structure <NUM> may be gated by a bandgap signal at input <NUM> (e.g., conveyed via power bus <NUM> and/or POR signal bus <NUM>), which may be configured to indicate that a supply voltage generated by power supply <NUM> (e.g., and provided to inputs <NUM> and/or <NUM>) is available to power current mirror <NUM> and generate a stable and reliable reference voltage <NUM>.

In some embodiments, reference voltage generator <NUM> is turned on by a voltage signal produced from another circuit, such as a bandgap, or even another POR generation circuit. Such voltage signal can indicate that the supply voltage at inputs <NUM> and/or <NUM> (e.g., VCC) has reached a certain minimum voltage, such as <NUM>, <NUM> or <NUM> volts. Current mirror <NUM> thereafter produces a stable and reliable reference voltage <NUM> via linear resistor array <NUM>. In various embodiments, reference voltage generator <NUM> may be implemented using other circuit elements and/or circuit arrangements. In general, reference voltage generator <NUM> may be any combination of circuit elements configured to generate a relatively stable and reliable reference voltage <NUM> prior to the monitored supply voltage (e.g., provided at monitored supply voltage input <NUM> of ramp voltage selector <NUM>) ramping to its nominal operating voltage, for example, where reference voltage <NUM> may be lower than the nominal operating voltage of the supply voltage monitored by adaptive POR signal generator <NUM>. In some embodiments, reference voltage generator <NUM> may be implemented by hard and/or soft IP resources integrated with PLD <NUM>.

As shown in <FIG>, reference voltage <NUM> may be supplied to ramp traversal detector <NUM>, which may in some embodiments be implemented as a comparator. Ramp traversal detector <NUM> may be coupled to ramp voltage selector <NUM> and configured to generate a ramp traversal signal <NUM> when ramp voltage <NUM> provided by ramp voltage selector <NUM> traverses reference voltage <NUM> (e.g., when ramp voltage <NUM> becomes equal to and/or greater than reference voltage <NUM> - which can be within a specified temporal/voltage tolerance or other approximation). In various embodiments, ramp traversal detector <NUM> may include programmable linear resistor array/voltage divider <NUM>, which may include resistors <NUM>, <NUM>, and <NUM> and resistor bypass switch <NUM> configured to generate ramp voltage <NUM> from supply voltage input <NUM> (e.g. the monitored supply voltage VCC) based on a switch state of resistor bypass switch <NUM>. For example, resistor bypass switch <NUM> may be configured to selectively short out resistor <NUM> and thereby change the range of voltages generated by ramp voltage selector and output as ramp voltage <NUM>. As shown, programmable linear resistor array/voltage divider <NUM> is coupled to VCC at input <NUM>, which as described, is ramping. Therefore, ramp voltage <NUM> is also increasing with increasing VCC.

In some embodiments, resistors R1/<NUM>, R2/<NUM>, R3/<NUM> may be chosen so that ramp voltage <NUM> is equal to reference voltage <NUM> when supply voltage VCC is about <NUM>. 38V and again when VCC is about <NUM>. 58v (e.g., when resistor bypass switch <NUM> is closed). In particular, ramp voltage <NUM> may be determined as (R2+R3)/(R1+R2+R3) when resistor bypass switch <NUM> is open and as (R2/(R1+R2)) when resistor bypass switch <NUM> is closed. Reasonable values for one or more of R1-R3 can be chosen, and then the resulting equations solved for both instances. Note that reference voltage <NUM> does not need to, and typically would not, equal <NUM> or <NUM>.

In various embodiments, adaptive POR signal generator <NUM> may include circuity (e.g., POR enabler <NUM>) configured to enable and disable operation of adaptive POR signal generator <NUM> when it is not needed, such as to save power. For example, signal input <NUM> (e.g., pmu_done) can indicate that a circuit receiving a POR signal from adaptive POR signal generator <NUM> has successfully turned on, and thus operation of adaptive POR signal generator <NUM> is no longer needed, while signal input <NUM> (e.g., bg_ready) can indicate that reference voltage <NUM> is ready to be (or is being) supplied to ramp traversal detector <NUM>, such that adaptive POR signal generator <NUM> may be used to generate a POR signal. For example, signal input <NUM> may be coupled to the same bandgap signal at input <NUM>. In some embodiments, counter <NUM> should be held in reset (e.g., via reset signal <NUM> generated by POR enabler <NUM>) if pmu_done is logically true, regardless of bg_ready, and counter <NUM> should come out of reset only if bg_ready is logically true while pmu_done is logically false. In various embodiments, POR enabler <NUM> may be configured to implement such logic to facilitate operation, enabling, and disabling of adaptive POR signal generator <NUM> and/or individual elements of adaptive POR signal generator <NUM>, as shown.

In response to ramp traversal detector <NUM> indicating to controller <NUM> via ramp traversal signal <NUM> that supply voltage VCC at input <NUM> has reached <NUM>. 38V, controller <NUM> initiates the output of oscillator <NUM> to counter <NUM> via various clock control signals, including clock enable signal <NUM>. Controller <NUM> also can adjust a frequency of oscillator <NUM> via clock control signals (e.g., slow enable signal <NUM>), as described herein. Controller <NUM> also can cause counter <NUM> to count either up or down via various counter control signals (e.g., up/down signal <NUM>), and in this example, upon ramp voltage selector <NUM> indicating supply voltage VCC at input <NUM> is at <NUM>. 38V, counter <NUM> starts to count up at a frequency of the clock signal <NUM> output by oscillator <NUM> to counter <NUM>. Upon ramp traversal detector <NUM> indicating to controller <NUM> that supply voltage VCC at input <NUM> has reached <NUM>. 58V, controller <NUM> disables oscillator <NUM> from providing clock signal <NUM> to counter <NUM> (e.g., via clock enable signal <NUM>). Note that the oscillator may still be active, but simply not outputting clock signal <NUM>. Counter <NUM> thus stops incrementing.

Aspects of the disclosure provide for delaying release of the POR signal by an amount dependent on how quickly supply voltage VCC ramped between the two ramp threshold voltages, referred to herein as the ramp time. In certain aspects, the POR signal delay is also determined based on how far Vh is from an expected final value of and/or nominal operating voltage for VCC. In the example presented with Vl=<NUM> and Vh=<NUM> (a difference of <NUM>. 2v) and a final VCC value of <NUM>, there is about <NUM>. 4v left for VCC to increase, and so the time to release should be about twice an amount of time that was required to ramp from Vl=<NUM> to Vh=<NUM>.

While a variety of implementations to provide the POR signal delay can be provided, in this example, the POR signal delay is implemented and/or adjusted by decreasing the oscillator frequency to about one half of the value that was used to count up. Then, controller <NUM> directs counter <NUM> to count down instead of up, at the now-reduced frequency. The current count from counter <NUM> can be provided to controller <NUM>, which may be configured to detect when the count value has reached zero and responsively generate a POR signal on POR signal bus <NUM> that can be used as a POR signal or to generate a further logic gated POR signal (i.e., to release reset or to come out of reset). For example, POR signal on POR signal bus <NUM> could be used directly to release reset, or it can be consumed by another circuit that may further gate or use the POR signal on POR signal bus <NUM> before a POR release.

In some implementations, counter <NUM> also has a capability to indicate overflow (e.g., via overflow signal <NUM>), meaning that ramp traversal detector <NUM> ultimately did not trigger controller <NUM> that ramp voltage <NUM> reached a value indicating VCC reached Vh. Controller <NUM> can use this overflow signal to take an action, which can depend on the intended usage of the POR signal. Such action can include causing the entire chip or portion of an integrated circuit to reset and try again, or a POR signal can be released anyway. In various embodiments, POR signal bus <NUM> may be used to convey a POR signal and/or other communicative logic signals between controller <NUM> and any other circuit elements services by adaptive POR signal generator <NUM>. Other implementations may include a counter <NUM> that itself can trigger another signal on a value of significance such as zero, and no exact division these functions implemented by controller <NUM> and counter <NUM> is implied or required.

In general, Vl and Vh can be adjusted and a corresponding change in delay or oscillator frequency can be provided. Additionally, an amount of bits in counter <NUM> can be provided based on an expected range and desired resolution of oscillator <NUM>. For example, oscillator <NUM> can operate at a value such as <NUM>, or more. Then, each transition of the clock from oscillator <NUM> represents <NUM>. A maximum number of bits can be determined by a maximum permissible POR signal delay. For example, with <NUM> bits, counter can count <NUM>^<NUM> transitions of clock signal <NUM>, or about <NUM> of total time (for the ramp up). More or fewer bits can be allocated, allowing more granularity and/or more range. Also, in general, oscillator <NUM>, counter <NUM>, POR enabler <NUM>, controller <NUM>, and/or other elements of adaptive POR signal generator <NUM> may be implemented by hard or soft IP resources of PLD <NUM>, for example.

In alternative or supplemental embodiments, adaptive POR signal generator <NUM> may be implemented by controller <NUM> and various circuit elements configured to sample a supply voltage provided by power supply <NUM> prior to the supply voltage reaching its nominal operating voltage, where controller <NUM> is configured to determine an appropriate POR signal delay and generate a POR signal according to the POR signal delay that roughly coincides with the supply voltage reaching it nominal operating voltage. In the embodiment shown in <FIG>, controller <NUM> uses two samples of the supply voltage (e.g., as selected by ramp voltage selector <NUM>) taken at different times and voltage levels to determine the appropriate POR signal delay. In alternative embodiments, controller <NUM> and ramp voltage selector <NUM> may be configured to sample the supply voltage at more than two different times, for example, or just once. For example, power supply <NUM> may be adapted to provide a supply voltage according to a characteristic ramp profile and controller <NUM> may be configured to use a single sample to determine where the supply voltage is on the ramp profile and then use the ramp profile to extrapolate an appropriate POR signal delay based on the single sample (e.g., ramp voltage <NUM> traversing a single threshold ramp voltage). Alternatively, where power supply <NUM> provides a supply voltage with a non-linear and multi-variable varying/unreliable ramp profile, or where more than two supply voltage samples are beneficial to determine a reliable POR signal delay, controller <NUM> may be configured to determine or characterize the non-linear ramp profile based on the more than two supply voltage samples and then determine the POR signal delay based on the supply voltage samples and the characterized non-linear ramp profile.

While the embodiment of adaptive POR signal generator <NUM> shown in <FIG> includes various elements, other embodiments of adaptive POR signal generator <NUM> may omit reference voltage generator <NUM> and replace ramp voltage selector <NUM> and ramp traversal detector <NUM> with other analog or digital circuitry configured to sample the supply voltage and provide the samples and/or timing of the samples to controller <NUM>. In addition, oscillator <NUM> and counter <NUM> may be omitted and/or replace with timing and/or clock circuitry configured to enable operation of controller <NUM> and adaptive POR signal generator <NUM>. More generally, any of the individual elements of adaptive POR signal generator <NUM> shown in <FIG> may be integrated together and/or their functionality implemented with different circuit elements and arrangements of circuit elements. Particular benefits of the embodiment shown in <FIG> are that oscillator <NUM> and counter <NUM> may be used for both ramp time characterization and POR signal delay implementation with minimal interconnects between controller <NUM>, oscillator <NUM>, and counter <NUM>. Also, reference voltage <NUM> is allowed to remain stable throughout the ramp characterization and POR signal generation, while ramp voltage <NUM> ramps, thereby ensuring repeatable and precise sampling of the supply voltage provided to input <NUM> throughout the ramp process.

<FIG> illustrates an adaptive POR signal generation process <NUM> in accordance with an embodiment of the disclosure. In some embodiments, the operations of <FIG> may be implemented as software instructions executed by one or more logic devices associated with corresponding electronic devices, modules, and/or structures depicted in <FIG>. More generally, the operations of <FIG> may be implemented with any combination of software instructions and/or electronic hardware (e.g., inductors, capacitors, amplifiers, actuators, or other analog and/or digital components). It should be appreciated that any step, sub-step, sub-process, or block of process <NUM> may be performed in an order or arrangement different from the embodiments illustrated by <FIG>. For example, in other embodiments, one or more blocks may be omitted from process <NUM>, and other blocks may be included. Furthermore, block inputs, block outputs, various sensor signals, sensor information, calibration parameters, and/or other operational parameters may be stored to one or more memories prior to moving to a following portion of process <NUM>. Although process <NUM> is described with reference to systems, devices, and elements of <FIG>, process <NUM> may be performed by other systems, devices, and elements, and including a different selection of electronic systems, devices, elements, assemblies, and/or arrangements. At the initiation of process <NUM>, various system parameters may be populated by prior execution of a process similar to process <NUM>, for example, or may be initialized to zero and/or one or more values corresponding to typical, stored, and/or learned values derived from past operation of process <NUM>, as described herein.

In block <NUM>, a logic device detects a first supply voltage ramp traversal. For example, controller <NUM> may be configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage selected via resistor bypass switch <NUM> of ramp voltage selector <NUM>. For example, ramp voltage selector <NUM> may be configured to generate ramp voltage <NUM> according to the first threshold ramp voltage or the second threshold ramp voltage based on the monitored supply voltage at input <NUM> and how the supply voltage is modified by the switch state of resistor bypass switch <NUM> and linear resistor array/resistor divider <NUM>. In some embodiments, controller <NUM> may be configured to detect such traversal by monitoring a ramp traversal signal generated by ramp traversal detector <NUM>, for example, and initiating an incrementing count within counter <NUM> upon detecting a logic signal transition in the ramp traversal signal. Controller <NUM> may be configured to initiate the incrementing count by generating counter control signals to control counter <NUM> to count incrementally and generating clock control signals to enable oscillator <NUM> and control oscillator <NUM> to provide clock signal <NUM> to counter <NUM>.

In general, ramp traversal detector <NUM> may be configured to receive ramp voltage <NUM> from ramp voltage selector <NUM> and provide ramp traversal signal <NUM> to controller <NUM>, and counter <NUM> may be configured to receive counter control signals from controller <NUM> (e.g., via up/down signal <NUM>, POR reset signal <NUM>) and count incrementally and/or decrementally based, at least in part, on the counter control signals provided by controller <NUM>. Oscillator <NUM> may be configured to receive clock control signals from controller <NUM> and provide clock signal <NUM> to counter <NUM> based, at least in part, on the clock control signals <NUM>, <NUM> provided by controller <NUM>. Controller <NUM> may be configured to detect the first supply voltage ramp traversal by detecting a first logic signal transition corresponding to the first supply voltage ramp traversal in ramp traversal signal <NUM> generated by ramp traversal detector <NUM> and initiating an incrementing count by counter <NUM>.

In various embodiments, controller <NUM> may be configured to select the first threshold ramp voltage prior to detecting the first supply voltage ramp traversal by polling a state of bypass switch <NUM> of ramp voltage selector <NUM> and/or opening resistor bypass switch <NUM>. Such selection may occur upon initialization of controller <NUM>, for example, or at any time prior to detecting the first supply voltage ramp traversal. More generally, controller <NUM> may be configured to configure ramp voltage selector <NUM> according to the first threshold ramp voltage prior to detecting the first supply voltage ramp traversal by polling the switch state of resistor bypass switch <NUM> and/or opening resistor bypass switch <NUM>. Ramp traversal detector <NUM> may be configured to generate the ramp traversal signal by determining ramp voltage <NUM> generated by ramp voltage selector <NUM> is greater than or equal to reference voltage <NUM> generated by reference voltage generator <NUM>, where reference voltage <NUM> is lower than the nominal operating voltage associated with power supply <NUM> and/or the supply voltage, and by generating the first logic signal transition in ramp traversal signal <NUM>.

In block <NUM>, a logic device detects a second supply voltage ramp traversal. For example, controller <NUM> may be configured to detect a second supply voltage ramp traversal across a second threshold ramp voltage selected via resistor bypass switch <NUM> ramp voltage selector <NUM>. In some embodiments, controller <NUM> may be configured to detect such traversal by monitoring a ramp traversal signal generated by ramp traversal detector <NUM>, for example, and halting the incrementing count within counter <NUM> (e.g., initialized in block <NUM>) upon detecting a logic signal transition in the ramp traversal signal. In various embodiments, controller <NUM> may be configured to select the second threshold ramp voltage subsequent to detecting the first supply voltage ramp traversal by closing resistor bypass switch <NUM> of ramp voltage selector <NUM>. Such selection may occur at any time prior to detecting the second supply voltage ramp traversal. More generally, controller <NUM> may be configured to configure ramp voltage selector <NUM> according to the second threshold ramp voltage after the detecting the first supply voltage ramp traversal and/or prior to the detecting the second supply voltage ramp traversal by closing resistor bypass switch <NUM>.

In various embodiments, controller <NUM> may be configured to initiate the decrementing count by generating counter control signals to control the counter to count decrementally starting at the ramp time count and by generating clock control signals to enable oscillator <NUM> and control oscillator <NUM> to provide a modified clock signal <NUM> to counter <NUM>, where the modified clock signal <NUM> comprises a frequency based, at least in part, on the ramp time and the nominal operating voltage level. For example, such frequency may be selected to set the duration of time needed to count down to zero equal to a desired POR signal delay derived from the ramp time and the nominal operating voltage level for the supply voltage. Controller <NUM> may be configured to detect the second supply voltage ramp traversal by detecting a second logic signal transition corresponding to the second supply voltage ramp traversal in ramp traversal signal <NUM> generated by ramp traversal detector <NUM> and halting the incrementing count by counter <NUM> initiated in block <NUM>.

In block <NUM>, a logic generates a POR signal based, at least in part, on a ramp time associated with the first and second supply voltage ramp traversals. For example, controller <NUM> may be configured to generate a POR signal based, at least in part, on such ramp time and a nominal operating voltage of power supply <NUM>, as described herein. In some embodiments, controller <NUM> may be configured to determine a POR signal delay based, at least in part, on the ramp time and the nominal operating voltage and to generate the POR signal after the detected second supply voltage ramp traversal and delayed relative to the detected second supply voltage ramp traversal according to the POR signal delay.

In some embodiments, controller <NUM> may be configured to determine such POR signal delay based, at least in part, on a linear supply voltage ramp rate corresponding to the ramp time between the first and second supply voltage ramp traversals and a voltage difference between the first and second threshold ramp voltages. In such embodiments, the POR signal delay may be determined by linear extrapolation based on the linear supply voltage ramp rate and a voltage difference between the nominal operating voltage and the second threshold ramp voltage, as described herein. In other embodiments, controller <NUM> may be configured to determine the POR signal delay based, at least in part, on a non-linear ramp profile associated with power supply <NUM> and/or the supply voltage, for example, in addition to the ramp time and the first and second threshold ramp voltages. In such embodiments, the POR signal delay may be determined by non-linear extrapolation based on such non-linear ramp profile. In various embodiments, controller <NUM> may be configured to adjust such POR signal delay based on a temperature of any element of user device <NUM>, based on one or more prior stored POR signal delays, a safety margin delay buffer, and/or other POR signal delay adjustments, as described herein.

In embodiments where adaptive POR signal generator <NUM> is implemented with counter <NUM> and oscillator <NUM> as shown in <FIG>, controller <NUM> may be configured to generate the POR signal by initiating a decrementing count by counter <NUM> starting at the ramp time count identified in block <NUM> and generating the POR signal as the decrementing count reaches zero (e.g., as conveyed to controller <NUM> via count signal <NUM>). More generally, controller <NUM> may be configured to generate the POR signal by determining a POR signal delay based, at least in part, on the ramp time and the nominal operating voltage level and generating the POR signal after the detected second supply voltage ramp traversal and delayed relative to the detected second supply voltage ramp traversal according to the POR signal delay, as described herein. In various embodiments, controller <NUM> may be configured to determine the POR signal delay by linear extrapolation based, at least in part, on the linear supply voltage ramp rate and a voltage difference between the nominal operating voltage and the second threshold ramp voltage, for example, or by non-linear extrapolation based, at least in part, on a non-linear ramp profile associated with the power supply and/or the supply voltage.

Thus, by employing the systems and methods described herein, embodiments of the present disclosure are able to provide flexible and reliable protection for a PLD and/or other components of a user device during all possible power ramping levels and sequences.

Additional embodiments may include an article of manufacture comprising an integrated circuit that is coupled to receive a POR signal and a power supply that has a nominal operating voltage (an expected operating voltage, within a bounded variation under normal conditions); an adaptive POR signal generator comprising logic to detect that the power supply has become active and to measure a ramp time for the supply voltage of the power supply (or a ramp voltage derived from the supply voltage) to ramp from a low first threshold ramp voltage to a higher second threshold ramp voltage, where both the low first threshold ramp voltage and the higher second threshold ramp voltage are less than the nominal operating voltage, and the logic is configured to generate a POR signal for receipt by the integrated circuit after a POR signal delay that is based on the ramp time. In some embodiments, the POR signal delay may be based on a difference between the higher second threshold ramp voltage and the nominal operating voltage of the power supply.

Additional embodiments may also include a method comprising comparing, by a voltage comparator, a ramp voltage derived from a ramping supply voltage to detect when the ramp voltage reaches a lower first threshold ramp voltage and a higher second threshold ramp voltage, both of which are less than a nominal operating voltage of the power supply; using a ramp time between the ramp voltage reaching the lower first threshold ramp voltage and reaching the higher second threshold ramp voltage to condition generation of a POR signal provided to circuitry that is coupled to receive the supply voltage.

Additional embodiments may also include integrated circuit, comprising a counter that counts transitions in a signal; an oscillator coupled to output a clock signal to the counter; a voltage comparator coupled to a power supply to compare a reference voltage with a ramp voltage related to an instantaneous supply voltage of the power supply at first and second points in time to detect when the supply voltage (or a ramp voltage derived from the supply voltage) has reached a low first threshold ramp voltage and a higher second threshold ramp voltage; control logic coupled to the voltage comparator and to the counter, the control logic configured to receive an indicator from the voltage comparator when the supply or ramp voltage reaches the low first threshold ramp voltage, responsively to output a signal to the counter, causing the counter to begin counting, and when the supply or ramp voltage reaches the higher second threshold ramp voltage, responsively to output a signal to the counter, causing the counter to stop counting; and to use a resulting value of the counter to delay release of a POR signal an amount of time expected to elapse between the supply or ramp voltage reaching the higher second threshold ramp voltage and the supply voltage reaching a nominal operating voltage.

Additional embodiments may also include an integrated circuit that performs a method comprising estimating a slew or ramp rate of a supply voltage that is ramping from an initial voltage to a nominal operating voltage, the estimating performed before the supply voltage has reached the nominal operating voltage; generating a POR signal after elapse of a period of time determined based on the estimated ramp rate and a remaining amount of voltage increase required to reach the nominal operating voltage. Additional embodiments may also include a method performed by an integrated circuit comprising estimating a ramp rate of a power source voltage that is ramping from an initial voltage to a nominal operating voltage, the estimating performed before the supply voltage has reached the nominal operating voltage; providing a POR signal after elapse of a period of time determined based on the estimated ramp rate and a remaining amount of voltage increase required to reach the nominal operating voltage.

Where applicable, various embodiments provided by the present disclosure can be implemented using hardware, software, or combinations of hardware and software. Also, where applicable, the various hardware components and/or software components set forth herein can be combined into composite components comprising software, hardware, and/or both. In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice-versa.

Software in accordance with the present disclosure, such as non-transitory instructions, program code, and/or data, can be stored on one or more non-transitory machine-readable mediums. It is also contemplated that software identified herein can be implemented using one or more general purpose or specific purpose computers and/or computer systems, networked and/or otherwise. Where applicable, the ordering of various steps described herein can be changed, combined into composite steps, and/or separated into sub-steps to provide features described herein.

Claim 1:
An adaptive power on reset (POR) signal generator, comprising:
a ramp voltage selector (<NUM>) configured to monitor a supply voltage provided by a power supply (<NUM>) and generate a ramp voltage (<NUM>) based, at least in part, on the monitored supply voltage; and
a logic device configured to:
detect a first supply voltage ramp traversal (<NUM>) across a first threshold ramp voltage based, at least in part, on the ramp voltage provided by the ramp voltage selector;
detect a second supply voltage ramp traversal (<NUM>) across a second threshold ramp voltage, wherein the second threshold ramp voltage is higher than the first threshold ramp voltage and the first and second threshold ramp voltages are lower than a nominal operating voltage associated with the power supply and/or the supply voltage;
determine a time at which to generate a POR signal (<NUM>) based, at least in part, on an amount of time between the first supply voltage ramp traversal and the second supply voltage ramp traversal; and
generate the POR signal (<NUM>) based on the determined time.