Patent Description:
Conventional clocking techniques drive a clock distribution network with a square-wave shaped clock signal. Resonant clocking techniques can drive the same clock distribution network with less energy than conventional clocking techniques. In addition, resonant clocking techniques can result in less jitter than may be experienced with conventional clocking techniques. However, conventional resonant clocking techniques drive a clock distribution network with a sinusoidally shaped clock signal. As a result, resonant clocking techniques can have a poorer slew rate than conventional clocking techniques.

<CIT> discloses a method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system. <CIT> discloses an electronic circuit uses a resonance technique to reduce power consumption. The circuit contains function circuitry that performs electronic functions. Certain elements of the function circuitry change state at a circuit frequency in response to one or more input signals, typically clock signals, that change state at the circuit frequency. A resonant system which oscillates at the circuit frequency is operated close to a resonant frequency so that the resonant system is largely in resonance. Oscillations of the resonance system typically include frequency components attributable to the fundamental resonance frequency and at least one other resonance frequency of the system. The resonant system is coupled to the function circuitry in order to help the indicated elements in changing state by overcoming parasitic capacitances and/or inductances associated with the function circuitry. <CIT> discloses a band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a second clock signal based on the first clock signal. A band-pass filter may be configured to receive the second clock signal and to provide a third clock signal to one or more load circuits. The band-pass filter includes a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap. The filtering resonant network is configurable to resonate with a parasitic capacitance associated with the one or more load circuits. A portion of the band-pass filter is integrated with the clock tree circuit.

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

The invention is as set out in independent claim <NUM>. Preferable features of the invention are defined in the appended dependent claims.

Conventional techniques for resonant clocking can have a poorer slew rate than conventional clocking techniques. Embodiments relate generally to apparatus and systems that employ resonant clocking techniques that provide slew rates that are better than conventional techniques for resonant clocking and which may be comparable to conventional clocking techniques. Disclosed herein are embodiments for power efficient resonant clocking having slew-rate improvements that make them useful for applications, such as but not limited to, wireline/optical I/O, e.g., to drive samplers and data serializers in receivers (RX) and transmitters (TX), wireless single-antenna or multi-antenna systems to drive mixers in the TX and RX path, and other communication and data processing systems.

In various embodiments, an apparatus includes a driver circuit to generate a clock signal at an output. When the output is coupled with a coupled-resonator network and a clock distribution network, the generated clock signal comprises both a first component comprising a first frequency at a first phase, and a second component comprising a second frequency at a second phase. The second frequency is a harmonic of the first frequency. In addition, the apparatus includes the coupled-resonator network to receive the clock signal at a node. In response to receiving the clock signal when the coupled-resonator network is coupled with the output of the driver circuit and the clock distribution network at the node, the coupled-resonator network is configured to simultaneously resonate at both the first frequency and first phase of the first component of the clock signal, and the second frequency and second phase of the second component of the clock signal. The coupled-resonator network comprises a first inductor to be magnetically coupled with a second inductor. The first inductor is also to be electrically coupled with the second inductor via a first capacitor.

In some embodiments, the second frequency of the clock signal is a third harmonic of the first frequency. In some embodiments, the second frequency of the clock signal is an odd-integer multiple of the first frequency. By adding an in-phase third harmonic (or other odd-integer multiple of the first frequency) to a conventional resonant clock signal, slew rate may be improved in comparison to conventional techniques for resonant clocking.

In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on.

The term "device" may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.

The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value. For example, unless otherwise specified in the explicit context of their use, the terms "substantially equal," "about equal" and "approximately equal" mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/-<NUM>% of a predetermined target value.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For example, the terms "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material "over" a second material in the context of a figure provided herein may also be "under" the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term "between" may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material "between" two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

The terms "functional block," "functional unit," or "component" herein generally refer to any circuitry that performs a particular function. A "functional block" or "component" may be a unit of logic, circuit, cell, or chip layout that is reusable. A functional block is sometimes colloquially referred to as an IP (intellectual property) block. A few examples of functional blocks or components include processor cores, memories, caches, floating point processors, memory controllers, bus controllers, graphics processors, transceivers, network interface controllers, and display controllers. One or more portions of a larger functional block can themselves be designated as functional blocks. For example, an instruction execution unit and cache controller can be functional units or components of a processor functional unit. It should be appreciated that the foregoing examples are a non-exhaustive list of functional blocks.

Wherever possible, in this description, the same names and reference numbers are used in the drawings and the description to refer to the same or like parts, components, blocks, signals, and operations. In this regard it should be appreciated that components and signals shown in or described with respect to a particular figure may be shown in or described with respect to other figures of this description. When a part, component, block, signal, or operation having a specific name or reference number is shown or described in a figure other than the particular figure in which it was first referenced, the part, component, block, signal, or operation can operate or function in any manner similar to that described in the particular figure. However, it should be appreciated that these elements with the same reference numbers (or names), when referred to with respect to a figure other than the particular figure in which it was first referenced, are not limited to the manner of operation or function as shown in or described with respect the particular figure.

Embodiments provide a number of advantages. Various embodiments are directed to resonant clocking techniques, which have the advantage of using less energy than conventional clocking techniques. In addition, embodiments advantageously have lower jitter and lower jitter transfer as compared with conventional clocking techniques. Moreover, various embodiments also have the advantage of providing better slew rates than conventional resonant clocking techniques.

A further advantage of the disclosed embodiments is that they are capable of achieving wide pole splitting in a resonator network using techniques that can be fabricated using presently known fabrication processes. This wide pole splitting is achieved with a combination of inductors that are magnetically coupled in a moderate amount and electrically coupled through one or more coupling capacitors. The dual magnetic and electrical coupling provides an advantage with respect to a resonator network with wide pole splitting based only on magnetic coupling, because the inductors required for wide pole splitting in a resonator without electrical coupling require high magnetic coupling, which would likely not be manufacturable using known techniques.

Resonant clocking is a technique in which energy stored in one or more inductors resonate with energy stored in the parasitic capacitance of the clock distribution network. Compared with conventional clocking techniques, resonant clocking can improve energy efficiency because the clock driver only needs to supply enough power to replenish the energy lost to the parasitic resistance of the clock distribution network. Resonance does not occur at all frequencies in a clock distribution network; resonance only occurs at the fundamental and in-phase harmonics of the clock frequency.

Conventional clocking techniques employ a clock driver that generates a clock signal having a square wave shape. The conventional square-wave clock signal includes a fundamental frequency component along with various harmonic components. In contrast, resonant clocking techniques employ a clock driver that generates a clock signal having a sinusoidal shape. The sinusoidally-shaped clock signal used in conventional resonant clocking techniques only includes the fundamental frequency without any harmonic components.

The rise time of a signal is the time for the signal to rise from a lower threshold and cross an upper threshold. For example, the lower threshold may be <NUM>% above a minimum amplitude and the higher threshold may be <NUM>% of a maximum amplitude. A related metric is the slew rate of a signal, which is the rate of change of the waveform. The slew rate is the slope of the waveform at any point or region. A conventional square-wave clock signal achieves a faster rise time and higher slew rate than the sinusoidally-shaped clock signal because of the harmonic components included in the square-wave clock signal.

<FIG> illustrates periodic signals in accordance with some embodiments. Each graph is a plot of amplitude y versus time t. <FIG> is a plot of a sinusoidal signal <NUM>, having a frequency f and phase Φ1. <FIG> is a plot of a sinusoidal signal <NUM>, having a frequency <NUM> x f and phase Φ2. Signal <NUM> is the third harmonic of signal <NUM>. <FIG> is a plot of a periodic signal <NUM>, having a frequency f and phase Φ3. Signal <NUM> is the sum of signals <NUM> and <NUM>. It can be seen from <FIG>, that a signal that is the sum of a fundamental frequency and its third harmonic, e.g., signal <NUM>, has faster rise time and higher slew rate than a signal comprised of only the fundamental frequency, e.g., signal <NUM>. It can also be seen that signal <NUM> includes ripple. A signal with ripple can serve as a clock signal provided the ripple is not too large. It can also be seen that phase Φ1 equals phase Φ2. In order to generate signal <NUM> that can be used to drive a clock distribution network, phases Φ1 and Φ2 need to be equal, or at least need to be substantially or approximately equal. In some embodiments, phases Φ1 and Φ2 are not required to be equal, provided they agree within a particular range, e.g., <NUM>%, <NUM>%.

<FIG> illustrates a resonant clocking apparatus <NUM> in accordance with some embodiments. A clock source <NUM> generates a first periodic signal <NUM>, which may be a conventional clock signal having the form of a square wave. The clock source <NUM> may be any of a wide variety of clock drivers known in the art. The clock source <NUM> may be fabricated on-chip, or it may be situated externally to an integrated circuit (IC).

A driver circuit <NUM> receives the first periodic signal <NUM> via an electrical conductor <NUM>. The driver circuit <NUM> generates a second periodic signal <NUM> based on the first periodic signal at an output <NUM>. In embodiments, second periodic signal <NUM> is a clock signal. The driver circuit <NUM> may be any of a wide variety of clock drivers known in the art. In some embodiments, driver circuit <NUM> is an inverter, as shown in the figure. In some embodiments, driver circuit <NUM> is a buffer, or other suitable circuitry. In various embodiments, a property of driver circuit <NUM> is that it generates a sinusoidal signal having fundamental frequency component and a harmonic component, e.g., second periodic signal <NUM>, based on a square wave signal, e.g., first periodic signal <NUM>, received on an input. In various embodiments, driver circuit <NUM> generates the second periodic signal <NUM> at a first power level.

The second periodic signal or clock signal <NUM> comprises two components: a first component, e.g., signal <NUM>, at a first frequency and first phase, and a second component, e.g., signal <NUM>, at a second frequency and second phase. In various embodiments, the second frequency is a harmonic of the first frequency. In various embodiments, the second frequency is an odd-integer multiple of the fundamental frequency. In an embodiment, the second frequency is the third harmonic of the fundamental frequency. In other embodiments, the second frequency may be the fifth, seventh, or ninth harmonic of the fundamental frequency.

It is not essential that the second phase of the second frequency of a clock signal generated by a clock driver according to the principles described herein be exactly in phase with the first phase of a first or fundamental frequency. In various embodiments, the second phase is substantially equal to the first phase. For example, the second phase of the second frequency may be in a range comprised of <NUM>% or less of the first phase of the first or fundamental frequency of a clock signal.

A coupled-resonator network <NUM> is coupled to the driver circuit <NUM> via a first node <NUM>, according to various embodiments. Coupled-resonator network <NUM> comprises first node <NUM> (VPRIMARY PORT) and a second node <NUM> (VSECONDARY PORT). In addition, coupled-resonator network <NUM> comprises a first inductor L<NUM>, a second inductor L<NUM>, a first capacitor CC <NUM> and a second capacitor C<NUM> <NUM>. The network <NUM> may be referred to as a "coupled-resonator" network because, in operation, second inductor L<NUM> is simultaneously both: magnetically coupled with first inductor L<NUM>, and electrically coupled with first inductor L<NUM> via first capacitor CC <NUM>. First capacitor CC <NUM> is coupled to first inductor L<NUM> via first node <NUM> and coupled to second inductor L<NUM> via second node <NUM>. Second capacitor C<NUM> <NUM> is coupled to second inductor L<NUM> via second node <NUM> and to ground VSS. Second inductor L<NUM> is also coupled to ground VSS. First inductor L<NUM> is coupled to direct current voltage VDC. The amount of magnetic coupling between first inductor L<NUM> and second inductor L<NUM> is given by the coefficient of coupling k. The amount of electrical coupling between first inductor L<NUM> and second inductor L<NUM> is given by the capacitive value of first capacitor CC <NUM>. Component values are selected so that, in operation, coupled-resonator network <NUM>, in response to receiving the clock signal <NUM> when coupled with the output of driver circuit <NUM> and clock distribution network <NUM> at the first node <NUM>, simultaneously resonates at both the first frequency and first phase of the first component and the second frequency and second phase of the second component of the second periodic or clock signal <NUM>.

In embodiments, the coupled-resonator network or resonator circuit <NUM> provides a fine-grained, small- range phase correction capability through tuning the value of first capacitor CC <NUM>. In some embodiments, a phase correction range of approximately <NUM> degrees is provided. Accordingly, the coupled-resonator network or resonator circuit <NUM> attenuates or mitigates a difference between a first phase of the first component and a second phase of the second component, and the degree of attenuation is adjustable. In addition, it should be appreciated that coupled-resonator network or resonator circuit <NUM> reduces input duty cycle error by approximately two fold. The residual duty cycle error can be corrected by tuning VDC.

It is not essential that a coupled-resonator network according to the principles described herein resonate at exactly the first frequency and first phase of a clock signal. In various embodiments, a coupled-resonator network resonates at substantially the first frequency and first phase. For example, a coupled-resonator network may resonate at frequency in a range comprised of <NUM>% or less of the first frequency of the clock signal. In addition, a coupled-resonator network may resonate at a phase in a range comprised of <NUM>% or less of the first phase of the first frequency of the clock signal.

It is not essential that a coupled-resonator network according to the principles described herein resonate exactly at the second frequency and second phase of a clock signal. In various embodiments, a coupled-resonator network resonates at substantially the second frequency and second phase. For example, a coupled-resonator network may resonate at frequency in a range comprised of <NUM>% or less of the second frequency of the clock signal. In addition, a coupled-resonator network may resonate at a phase in a range comprised of <NUM>% or less of the second phase of the second frequency of the clock signal.

In operation, driver circuit <NUM> and coupled-resonator network <NUM> cooperate to provide clock signal at first node <NUM>, each providing part of the total energy of the clock signal <NUM>. At the first node <NUM> (VPRIMARY PORT), the first component of the second periodic signal <NUM> is in phase with the second component of the second periodic signal <NUM>. It should be appreciated that the signal at second node <NUM> (VSECONDARY PORT) has one component at a third frequency and third phase, and another component at a fourth frequency and fourth phase. However, although the third frequency is substantially equal to the first frequency, and the fourth frequency is substantially equal to the second frequency, the fourth phase is approximately <NUM> degrees out of phase with the third phase. Hence, the component at the fourth frequency will create distortion rather than improve the slew rate of the resonant clock signal at first node <NUM>. Therefore, the signal at second node <NUM> cannot be used to provide a resonant clock signal with improved slew rate. In some embodiments, the clock frequency may be <NUM>. However, embodiments are not limited to <NUM> and various embodiments contemplate other frequencies.

In various embodiments, coupled-resonator network <NUM> is coupled to a clock distribution network <NUM> at first node <NUM>. Clock distribution network <NUM> comprises one or more devices (<NUM>, <NUM>, <NUM>, <NUM>), e.g., latches, flip-flops, etc., and an electrical conductor <NUM>. The electrical conductor <NUM> is coupled with the first node <NUM> and various devices that are to receive the clock signal. In operation, clock distribution network <NUM> receives the clock signal <NUM> via first node <NUM>. The parasitic capacitance of clock distribution network <NUM> is referred to in this description as CL. In subsequent figures of this description, clock distribution network <NUM> may be represented by only the circuit symbol for equivalent capacitance CL in order to simplify the figures. It should be understood that the circuit symbol for equivalent capacitance CL represents clock distribution network <NUM>.

In various embodiments, the quantity of energy in clock signal <NUM> is an amount required to provide a sufficient clock signal to all devices in clock distribution network <NUM>. A first portion of the required energy is provided by driver circuit <NUM>. A second portion of the required energy is provided by coupled-resonator network <NUM>. In various embodiments, the second portion of energy is greater than the first portion of energy in second periodic or clock signal <NUM>. In various embodiments, the first portion of energy provided by driver circuit <NUM> is less than the amount of energy required to provide a sufficient clock signal to all devices in clock distribution network <NUM>. Accordingly, an advantage of resonant clocking apparatus <NUM> is that it uses less energy than a conventional clock driver would use to drive clock distribution network <NUM>. Driver circuit <NUM> only needs to supply enough power to replenish the energy lost to the parasitic resistance of the clock distribution network <NUM>.

As noted above, driver circuit <NUM> generates a clock signal <NUM> comprised of two components: a first component, e.g., signal <NUM>, and a second component, e.g., signal <NUM>. First and second components may each have a distinct amplitude. In various embodiments, the first component has a first amplitude, denoted A1, and the second component has a second amplitude, denoted A2. In various embodiments, the first amplitude is greater than the second amplitude. As will be discussed below, the first amplitude may be in a range that is three to ten times greater than the second amplitude.

While driver circuit <NUM> generates a clock signal comprised of two components: a first component that may be a fundamental frequency and a second component that may be a harmonic of the fundamental frequency, in other embodiments, a driver circuit may generate a second periodic signal comprised of more than two components. For example, a driver circuit may generate a second periodic signal comprised three components: a first component at a fundamental frequency, a second component at a third harmonic of the fundamental frequency, and a third component at a fifth harmonic of the fundamental frequency. In embodiments in which a driver circuit generates a second periodic signal comprised of more than two components, a coupled-resonator network is provided that resonates at each of the more than two component frequencies.

<FIG> illustrates a clocking apparatus <NUM> having resonant and non-resonant modes of operation in accordance with some embodiments. Clocking apparatus <NUM> is capable of operating in a first mode in which it provides a resonant clock signal at a first clock frequency and a second mode in which it provides a non-resonant clock signal at a second clock frequency. In some embodiments, the first clock frequency may be <NUM> and the second clock frequency may be <NUM>. Clocking apparatus <NUM> includes a mechanism for adjusting the resonance frequency of the coupled-resonator. Clocking apparatus <NUM> also includes a mechanism for fine-grain tuning of the phase of the second periodic signal over a particular range. In some embodiments, the phase can be adjusted over correction range of about <NUM>°.

The clocking apparatus <NUM> includes several components that may be the same as or similar to those of resonant clocking apparatus <NUM> in some embodiments. Clock source <NUM> generates a first periodic signal <NUM>, which may be a conventional clock signal having the form of a square wave. Driver circuit <NUM> receives the first periodic signal <NUM> via an electrical conductor <NUM> and generates a second periodic or clock signal <NUM> based on the first periodic signal at output <NUM>. In some embodiments, the first periodic signal <NUM> and the second periodic signal <NUM> may be the same as described above with reference to resonant clocking apparatus <NUM>. The clocking apparatus <NUM> generates a clock signal for clock distribution network <NUM>, represented in <FIG> by reference CL. In some embodiments, the clock distribution network <NUM> may be the same as described above with reference to resonant clocking apparatus <NUM>.

Clocking apparatus <NUM> differs from clocking apparatus <NUM> in that it includes a second driver circuit <NUM> and switching circuitry (S1, S2, and S3). Clocking apparatus <NUM> includes a switch S1 for selectively coupling an input of second driver circuit <NUM> to clock source <NUM>, and a switch S2 for selectively coupling an output <NUM> of second driver circuit <NUM> to a first node <NUM> of a coupled-resonator network <NUM>.

Coupled-resonator network <NUM> comprises first inductor L1, second inductor L2, a first capacitor CC <NUM>, and a second capacitor C<NUM> <NUM>. In some embodiments, L1 and L2 may be the same as described above with reference to resonant clocking apparatus <NUM>. Clocking apparatus <NUM> also differs from clocking apparatus <NUM> in that the capacitive values of one or both of first capacitor CC <NUM> and second capacitor C<NUM> <NUM> are variable. In various embodiments, first capacitor CC <NUM> may comprise two or more discrete capacitors and switching circuitry that can be controlled to connect the two or more discrete capacitors in parallel or series (or in a combined parallel and series arrangement) to provide two more discrete capacitive values for first capacitor CC <NUM>. As one example, first capacitor CC <NUM> may have capacitive values switchable between <NUM>, <NUM>, <NUM>, and <NUM> times a reference capacitive value. Similarly, in various embodiments, second capacitor C<NUM> <NUM> may comprise two or more discrete capacitors and switching circuitry that can be controlled to connect the two or more discrete capacitors in parallel or series (or in a combined parallel and series arrangement) to provide two more discrete capacitive values for second capacitor C<NUM> <NUM>. As an example, second capacitor C<NUM> <NUM> may have capacitive values switchable between <NUM>, <NUM>, <NUM>, and <NUM> times a reference capacitive value.

In coupled-resonator network <NUM>, L<NUM> is simultaneously both magnetically coupled with first inductor L<NUM>, and electrically coupled with first inductor L<NUM> via first capacitor CC <NUM>. First capacitor CC <NUM> is coupled to first inductor L<NUM> via first node <NUM> and coupled to second inductor L<NUM> via second node <NUM>. Second capacitor C<NUM> <NUM> is coupled to second inductor L<NUM> via second node <NUM>. Second inductor L<NUM> is also coupled to ground VSS. First inductor L<NUM> is coupled to direct current voltage VDC. Coupled-resonator network <NUM> differs from coupled-resonator network <NUM> in that it includes a switch S3 connected between first inductor L1 and VDC. In addition, in various embodiments, VDC is provided at a variable value that may be varied in response to a control signal.

Clocking apparatus <NUM> can be operated in the first mode in which it provides a resonant clock signal at a first clock frequency. In the first mode, switches S1 and S2 are open, and S3 is closed. In operation, driver circuit <NUM> receives the first periodic signal <NUM> via an electrical conductor <NUM>, and, when output <NUM> is coupled with the coupled-resonator network <NUM> and clock distribution network CL, driver circuit <NUM> generates a second periodic or clock signal <NUM>. In a manner similar to coupled-resonator network <NUM>, coupled-resonator network <NUM>, in response to receiving the clock signal <NUM> when coupled with the output <NUM> of driver circuit <NUM> and clock distribution network CL at the first node <NUM>, simultaneously resonates at both the first frequency and first phase of the first component and the second frequency and second phase of the second component of the second periodic or clock signal <NUM>.

Clocking apparatus <NUM> can be operated in the second mode in which it provides a non-resonant clock signal at a second clock frequency. In the second mode, switches S1 and S2 are closed, and S3 is open. In operation, driver circuit <NUM> receives the first periodic signal <NUM> and generates a clock signal (not shown). Driver circuit <NUM> generates a clock signal in the form of a square wave (similar to signal <NUM>) at a first power level. In addition, driver circuit <NUM> receives the first periodic signal <NUM> and generates periodic signal <NUM>. In various embodiments, periodic signal <NUM> is a square wave signal. Driver circuit <NUM> generates periodic signal <NUM> at a second power level. In various embodiments, the second power level is higher than the first power level. Driver circuit <NUM> sources and sinks more current than driver circuit <NUM>. Accordingly, in non-resonant mode, driver circuit <NUM> advantageously increases the power in the clock signal provided to the clock distribution network as compared with the amount of power that would be provided by driver circuit <NUM> alone. Driver circuit <NUM> also improves the slew rate that driver circuit <NUM> alone provides. Coupled-resonator network <NUM> does not contribute in a significant way to the clock signal provided at the first node <NUM>. The clock signal provided at the first node <NUM> is provided at a power level that is at or above the amount of power required to provide a sufficient clock signal to all devices in clock distribution network <NUM>.

<FIG> illustrates a resonant clocking apparatus having driver circuitry comprising two driver circuits in accordance with some embodiments. Specifically, resonant clocking apparatus <NUM> comprises driver circuitry the includes a first driver circuit <NUM>, a second driver circuit <NUM>, and an output <NUM>. Several components that may be the same as or similar to those of resonant clocking apparatus <NUM> are included in resonant clocking apparatus <NUM> in some embodiments. Clock source <NUM> generates a first periodic signal <NUM>, which may be a conventional clock signal having the form of a square wave. Coupled-resonator network <NUM> comprises first inductor L1, second inductor L2, a first capacitor CC <NUM>, and a second capacitor C<NUM> <NUM>. Coupled-resonator network <NUM> comprises first node <NUM> (VPRIMARY PORT) and second node <NUM> (VSECONDARY PORT). In some embodiments, first inductor L1, second inductor L2, first capacitor CC <NUM>, and second capacitor C<NUM> <NUM> may be coupled in the same way as described above with reference to coupled-resonator network <NUM>. Resonant clocking apparatus <NUM> generates a clock signal <NUM> at output <NUM> for clock distribution network <NUM>, represented in <FIG> by reference CL. In some embodiments, the clock distribution network <NUM> may be the same as described above with reference to resonant clocking apparatus <NUM>.

First driver circuit <NUM> and second driver circuit <NUM> each receive first periodic signal <NUM> via an electrical conductor <NUM>. First driver circuit <NUM> generates a fundamental periodic signal that is a fundamental or first harmonic of a frequency and which is based on first periodic signal <NUM>. Second driver circuit <NUM> generates a harmonic periodic signal that is an odd-integer harmonic of the fundamental frequency and which is based on first periodic signal <NUM>. In some embodiments, second driver circuit <NUM> generates a harmonic periodic signal that is a third harmonic of the fundamental frequency. In various embodiments, first driver circuit <NUM> and second driver circuit <NUM> together generate the clock signal <NUM>. The second periodic or clock signal <NUM> comprises two components: a first frequency at a first phase, and a second frequency at a second phase. Coupled-resonator network <NUM>, in response to receiving the clock signal <NUM> when coupled with the output of the driver circuits <NUM> and <NUM>, and clock distribution network at the first node <NUM>, simultaneously resonates at both the first frequency and first phase of the first component and the second frequency and second phase of the second component of the clock signal <NUM>.

In various embodiments, first driver circuit <NUM> generates the first component of clock signal <NUM>, which may be a fundamental periodic signal at a first power level. Second driver circuit <NUM> generates the second component of the clock signal <NUM>, which may be a harmonic periodic signal, e.g., a signal at an odd-integer harmonic of the first component, at a second power level. In various embodiments, the first power level is higher than the second power level. In operation, coupled-resonator network <NUM> receives the clock signal <NUM> via first node <NUM>.

While resonant clocking apparatus <NUM> includes two driver circuits <NUM>, <NUM>, in other embodiments, a clocking apparatus can have three or more driver circuits. As one example, a clocking apparatus may include a first driver circuit that generates a periodic signal at fundamental frequency, a second driver circuit that generates a periodic signal at a third harmonic of the fundamental frequency, and third driver circuit that generates a periodic signal at a fifth harmonic of the fundamental frequency. In embodiments in which clocking apparatus has three or more driver circuits, coupled-resonator network <NUM> is configured to resonate at each frequency.

<FIG> illustrates a resonant clocking apparatus having a coupled-resonator network configured to resonate at a plurality of harmonic frequencies in accordance with various embodiments. Driver circuitry comprises driver circuits <NUM>, <NUM>, and <NUM>. Driver circuit <NUM> generates a first sinusoidal signal at a first frequency and first phase, which can be a fundamental frequency with respect to harmonic frequencies. Driver circuit <NUM> generates a second sinusoidal signal at a second frequency and second phase. In an embodiment, the second frequency is the third harmonic of the first frequency, and the second phase is substantially equal to the first phase. Driver circuit <NUM> generates a third sinusoidal signal at a third frequency and third phase. In an embodiment, the third frequency is the fifth harmonic of the first frequency, and the third phase is substantially equal to the first phase. The first, second, and third sinusoidal signals are superimposed at driver circuitry output node <NUM> to provide a clock signal <NUM>.

Accordingly, the clock signal <NUM> comprises three components: a first component, i.e., a first frequency at a first phase; a second component, i.e., a second frequency at second phase; and a third component, i.e., a third frequency at third phase. In other embodiments, one or more additional driver circuits may be provided to generate a clock signal comprised of more than three components, where each harmonic component is an odd-integer multiple of the fundamental frequency. It should be appreciated that each of the components of clock signal <NUM> has an amplitude and the amplitude of the harmonic components is less than the amplitude of the fundamental frequency.

According to various embodiments, a coupled-resonator network <NUM> is coupled to the output of the driver circuitry <NUM> via a first node <NUM>. The coupled-resonator network <NUM> comprises a first inductor L<NUM>, a second inductor L<NUM>, and a third inductor L<NUM>. When the coupled-resonator network <NUM> is operating, first inductor L<NUM> and second inductor L<NUM> are magnetically coupled and amount of magnetic coupling is given by the coefficient of coupling k<NUM>. In addition, when coupled-resonator network <NUM> is operating, first inductor L<NUM> and third inductor L<NUM> are magnetically coupled and amount of magnetic coupling is given by the coefficient of coupling k<NUM>.

In various embodiments, the coupled-resonator network <NUM> also includes a first coupling capacitor CC1 <NUM> that, in operation, electrically couples first inductor L<NUM> with second inductor L<NUM>. In addition, the coupled-resonator network <NUM> includes a second coupling capacitor CC2 <NUM> that, in operation, electrically couples first inductor L<NUM> with third inductor L<NUM>. Accordingly, when coupled-resonator network <NUM> is operating, first inductor L<NUM> and second inductor L<NUM> are simultaneously both magnetically and electrically coupled, and first inductor L<NUM> and third inductor L<NUM> are simultaneously both magnetically and electrically coupled.

Coupled-resonator network <NUM> comprises first node <NUM> and second node <NUM>. A first terminal of first inductor L<NUM> is coupled with first node <NUM>. A first terminal of second inductor L<NUM> is coupled with second node <NUM>. First coupling capacitor CC1 <NUM> is connected between first node <NUM> and second node <NUM> to electrically couple the first inductor L<NUM> and second inductor L<NUM>.

Coupled-resonator network <NUM> comprises third node <NUM>. As noted, a first terminal of first inductor L<NUM> is coupled with first node <NUM>. A first terminal of third inductor L<NUM> is coupled with third node <NUM>. Second coupling capacitor CC2 <NUM> is connected between first node <NUM> and third node <NUM> to electrically couple the first inductor L<NUM> and third inductor L<NUM>.

Coupled-resonator network <NUM> also comprises second capacitor C<NUM> <NUM>, third capacitor C<NUM> <NUM>, node <NUM>, node <NUM>, ground VSS, and direct current voltage VDC. Second capacitor C<NUM> <NUM> is coupled to second inductor L<NUM> via second node <NUM> and to ground VSS via node <NUM>. Third capacitor C<NUM> <NUM> is coupled to third inductor L<NUM> via third node <NUM> and to ground VSS via node <NUM>. Second inductor L<NUM> is also coupled to ground VSS. First inductor L<NUM> is coupled to direct current voltage VDC.

Clock distribution network <NUM> is coupled with driver circuits <NUM>, <NUM>, and <NUM> at output <NUM> and coupled-resonator network <NUM> at first node <NUM>. Component values are selected so that, in operation, coupled-resonator network <NUM>, in response to receiving the clock signal <NUM> when coupled with the output of the driver circuitry and clock distribution network <NUM> at the first node <NUM>, simultaneously resonates at the first frequency and first phase of the first component, the second frequency and second phase of the second component, and the third frequency and third phase of the third component of the clock signal <NUM>.

<FIG> illustrates a clocking apparatus <NUM> for a differential clock signal that provides resonant and non-resonant modes of operation, in accordance with various embodiments.

Clocking apparatus <NUM> comprises a differential clock source <NUM> that generates a double-ended clock signal, driver circuits 208a, 208b, 316a, and 316b for receiving the clock signals, and a coupled-resonator network <NUM>. A clock distribution network <NUM> is coupled to coupled-resonator network <NUM> at first node <NUM>, and phase-offset first node <NUM>, where differential clock signals are provided. Clock distribution network <NUM> is represented in <FIG> with the circuit symbols CL corresponding with its equivalent capacitance.

Clocking apparatus <NUM> comprises switching circuitry (switches S1, S2, S3, S4, S5, and S6) that is controlled to switch between resonant and non-resonant modes of operation. For resonant mode of operation, switches S1, S2, S3, and S4 are opened, and switches S5 and S6 are closed. For non-resonant mode of operation, switches S1, S2, S3, and S4 are closed, and switches S5 and S6 are opened. In resonant mode, driver circuits 316a, 316b are decoupled from clocking apparatus <NUM>. In non-resonant mode, driver circuits 316a, 316b are coupled to clocking apparatus <NUM>, and coupled-resonator network <NUM> does not contribute in a significant way to the clock signals provided at first nodes <NUM>, <NUM>. Resonant mode is described first.

Clock source <NUM> generates two signals: first periodic signal <NUM> and a phase-offset first periodic signal <NUM>. The first periodic signal <NUM> may be the same signal as described above with respect to <FIG>, i.e., a conventional clock signal having the form of a square wave. Phase-offset first periodic signal <NUM> is the same as first periodic signal <NUM> except that it is <NUM> degrees out of phase with signal <NUM>. Accordingly, first periodic signal <NUM> and phase-offset first periodic signal <NUM> may both be conventional double-ended clock signals having the form of a square wave that are <NUM> degrees out of phase with each other. The clock source <NUM> may be any of a wide variety of clock drivers known in the art. The clock source <NUM> may be fabricated on-chip, or it may be situated externally to an IC.

Coupled-resonator network <NUM> is coupled to driver circuit 208a via a first node <NUM>, and to driver circuit 208b via phase-offset first node <NUM>, according to various embodiments. Driver circuit 208a receives first periodic signal <NUM> via an electrical conductor 608p. Driver circuit 208a generates a second periodic or clock signal <NUM> based on the first periodic signal. Driver circuit 208a generates the clock signal at an output 207a. Driver circuit 208b receives phase-offset first periodic signal <NUM> via an electrical conductor 608n. Driver circuit 208b generates a phase-offset second periodic signal <NUM>, which may be a complementary clock signal, based on the first periodic signal. Driver circuit 208b generates the complementary clock signal at an output 207b. Second periodic (or clock) signal <NUM> is provided at first node <NUM>. Phase-offset second periodic (or complementary clock) signal <NUM> is provided at phase-offset first node <NUM>.

Coupled-resonator network <NUM> comprises first node <NUM> and phase-offset first node <NUM>, both of which are primary port nodes (VPRIMARY PORT). In addition, coupled-resonator network <NUM> comprises second node <NUM> and phase-offset second node <NUM>, both of which are secondary port nodes (VSECONDARY PORT). Coupled-resonator network <NUM> also comprises first and second coupling capacitors CC <NUM>, <NUM>, and second capacitors C<NUM> <NUM>, <NUM>.

It should be appreciated that the phrase "resonator circuit" may be used in this specification and, in the claims, to refer to a "coupled-resonator network," e.g., networks <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

In various embodiments, the coupled-resonator network or resonator circuit described herein provide a fine-grained, small- range phase correction capability through tuning the value of capacitors that electrically couple inductors, e.g., CC <NUM>, CC <NUM>, CC <NUM>, CC1 <NUM>, CC2 <NUM>, CC <NUM>, and CC <NUM>. In some embodiments, a phase correction range of approximately <NUM> degrees is provided. Accordingly, the coupled-resonator network or resonator circuit <NUM> attenuates or mitigates a difference between a first phase of the first component and a second phase of the second component, and the degree of attenuation is adjustable. In addition, it should be appreciated that coupled-resonator network or resonator circuit reduces input duty cycle error by approximately two fold. The residual duty cycle error can be corrected by tuning VDC.

Coupled-resonator network <NUM> comprises first inductors L1a, L1b and second inductors L2a, L2b( structure <NUM>). <FIG> is a plan view of first inductors L1a, L1b and second inductors L2a, L2b constructed according to various embodiments. In an embodiment, first and second inductors are electrical conductors constructed in one layer of an IC. In another embodiment, first and second inductors are electrical conductors constructed in two layers of an IC. First inductors L1a, L1b and second inductors L2a, L2b may be fabricated using known lithographic techniques. The arrangement of first inductors L1a, L1b and second inductors L2a, L2b, is not limited to the arrangement shown in <FIG>: any suitable arrangement may be used. Reference numbers <NUM>, <NUM>, <NUM>, and <NUM> indicate respective terminals of first inductors L1a, L1b, and are the same as those shown in <FIG>. Reference numbers <NUM> and <NUM> indicate respective terminals of second inductors L2a, L2b, and are the same as those shown in <FIG>.

In resonant mode operation, second inductor L2a is simultaneously both: magnetically coupled with first inductor L1a, and electrically coupled with first inductor L1a via first capacitor CC <NUM>. Similarly, second inductor L2b is simultaneously both: magnetically coupled with first inductor L1b, and electrically coupled with first inductor L1b via second coupling capacitor CC <NUM>. This dual coupling may be equivalently stated as: second inductor L<NUM> (i.e., L2a and L2b,) is both: magnetically coupled with first inductor L<NUM> (i.e., L1a and L1b), and electrically coupled with first inductor L<NUM> via first coupling capacitor CC (<NUM> and <NUM>).

First coupling capacitor CC <NUM> is coupled to first inductor L1a via first node <NUM> and coupled to second inductor L2a via second node <NUM>. Second capacitor C<NUM> <NUM> is coupled to second inductor L2a via second node <NUM> and to second capacitor C<NUM> <NUM> at connection <NUM>. Second coupling capacitor CC <NUM> is coupled to first inductor L1b via first node <NUM> and coupled to second inductor L2b via second node <NUM>. Second capacitor C<NUM> <NUM> is coupled to second inductor L2b via second node <NUM> and to second capacitor C<NUM> <NUM> at connection <NUM>. Second inductor L2a is coupled to second inductor L2b via node <NUM>.

First inductor L<NUM> (i.e., L1a and L1b) is coupled to direct current voltage VDC when clocking apparatus <NUM> is operated in resonant modes of operation. In various embodiments, VDC is provided at a variable value that may be varied in response to a control signal. Switches S5 and S6 respectively connect L1a and L1b to VDC when closed.

The amount of magnetic coupling between first inductor L<NUM> (i.e., L1a and L1b) and second inductor L<NUM> (i.e., L2a and L2b,) is given by the coefficient of coupling k. The amount of electrical coupling between first inductor L<NUM> and second inductor L<NUM> is given by the capacitive values of first and second coupling capacitors CC <NUM><NUM>. Component values are selected so that, in operation, coupled-resonator network <NUM>, when connected to the driver circuits 208a, 208b and clock distribution network <NUM>, simultaneously resonate at the first frequency of the first component and the second frequency of the second component of the clock signals <NUM>, <NUM>.

In resonant mode operation, coupled-resonator network <NUM> receives clock signal <NUM> at first node <NUM>, and receives complimentary clock signal <NUM> at phase-offset first node <NUM>. As noted above, the second periodic or clock signal <NUM> comprises two components: a first component, e.g., signal <NUM> at a first frequency and first phase, and a second component, e.g., signal <NUM> at a second frequency and second phase. The complimentary clock signal <NUM> includes these two components <NUM>° out of phase. In various embodiments, the second frequency is a harmonic of the first frequency. In various embodiments, the second frequency is an odd-integer multiple of the fundamental frequency. In an embodiment, the second frequency is the third harmonic of the fundamental frequency. In various embodiments, the first phase is substantially equal to the second phase.

In resonant operating mode, driver circuits 208a, 208b and coupled-resonator network <NUM> cooperate to provide a differential clock signal at first nodes <NUM>, <NUM>. The clock signal at first node <NUM> is comprised of the first component and an in-phase portion of the second component of the second periodic signal <NUM>. The clock signal <NUM> at first node <NUM> is comprised of a phase-offset portion of the first component, where the phase-offset portion of first component is <NUM>° out of phase, which is in-phase with a phase-offset portion of the second component, where the phase-offset second component is also <NUM>° out of phase.

It should be appreciated that the differential signal at second nodes <NUM>, <NUM> (VSECONDARY PORT) has one component at third frequency and third phase, and another component at fourth frequency and fourth phase. However, although third frequency is substantially equal to the first frequency and fourth frequency is substantially equal to the second frequency, the fourth phase is approximately <NUM> degrees out of phase with the third phase, and hence, the component at the fourth frequency will create distortion rather than improving the slew rate of the resonant clock signal. Therefore, the signal at second nodes <NUM>, <NUM> cannot be used to provide a resonant clock signal with improved slew rate.

Examples of approximate component values for coupled-resonator network <NUM> are: CL = <NUM> fF, L<NUM> = <NUM> pH, L<NUM> = <NUM> pH, k = <NUM>, C<NUM> = <NUM> fF to <NUM> fF, and CC = <NUM> fF to 225fF. The resonant mode frequencies of the coupled-resonator networks described herein can be tuned through CC and the secondary side capacitor (C<NUM>) to enable operation across a frequency range.

As noted above, second periodic (or clock) signal <NUM> is comprised of two or more components, e.g., a first component, e.g., signal <NUM>, and a second component, e.g., signal <NUM>. Second periodic signal (or complimentary clock) <NUM> also comprises of similar two or more components that are <NUM>°out of phase with the components of second periodic signal <NUM>. Each component of signal <NUM> and signal <NUM> has a distinct amplitude. Amplitudes of the first components may be denoted A1 and amplitudes of the second components may be denoted A2. A parameter r may be defined as a ratio of A2/A1. As one example, r = <NUM>/<NUM> indicates that the amplitude of second component <NUM>/<NUM> of the amplitude of the first component of the second periodic signal <NUM>.

A simulation of an embodiment of clocking apparatus <NUM> indicated an improvement in slew rate as compared with conventional resonant clocking. Depending on the value of r, the slew rate was seen to be <NUM>-<NUM> times better than conventional resonant clocking. However, the amount of ripple present in the time-domain waveform increases with increasing values of r. The simulation indicated that an acceptable amount of ripple (less than <NUM>%) was achievable when A1 and A2 were selected to provide a r value in a range between <NUM> and <NUM>. Accordingly, driver circuit may be selected or designed to provide amplitudes A1 and A2 such that the amount of ripple in the clock signal is acceptable. In various embodiments, the first amplitudes A1 are greater than the second amplitudes A2. In various embodiments, driver circuits disclosed herein have a property that the first and second amplitudes produce an r value ranging between <NUM> and <NUM>. In various embodiments, the first amplitude may be in a range that is three to ten times greater than the second amplitude. It should be appreciated that the amplitudes of the fundamental and harmonic components are not limited to particular values or ranges of r. The values and r range are design choices that will vary depending on the particular implementation. Moreover, in some embodiments, ripple may be managed into an acceptable range by the addition of one or more additional harmonic components are different multiples of the fundamental frequency.

In resonant mode operation, second inductor L<NUM> (i.e., L2a and L2b,) is simultaneously both: magnetically coupled with first inductor L<NUM> (i.e., L1a and L1b), and electrically coupled with first inductor L<NUM> via first and second coupling capacitors CC (<NUM> and <NUM>). This coupling mechanism results in pole splitting, where one pole can be placed at the <NUM>st harmonic (f<NUM>) and the other at the <NUM>rd harmonic (f<NUM>) of the clock frequency. This pole splitting is illustrated by equations (<NUM>), (<NUM>), and (<NUM>), which are for L<NUM> (L1a and L1b) = L<NUM> (L2a and L2b,) = L, and CC (<NUM> and <NUM>) = C<NUM> (<NUM> and <NUM>) = C. <MAT> <MAT> where: <MAT>.

While it is theoretically possible to obtain wide pole splitting using only inductive coupling, this approach requires high coupling factors, e.g., k = <NUM>. The high coupling factors required may not be realizable on chip or may be difficult to achieve using most presently known fabrication processes. This is because two inductors need to be closely spaced to achieve high coupling. Inductors are made from thick metal with low resistance in a typical fabrication process. If both inductors are drawn side-by-side using the same metal layer, there is a limit as to how closely they can be spaced without violating DRC fabrication rules. Positioning the two inductors too close in an attempt to achieve a high coupling factor may cause an electrical short.

In contrast, the disclosed embodiments are capable of achieving wide pole splitting with moderate inductive coupling (e.g., k = <NUM>), which can be fabricated using presently known fabrication processes. Coupled resonators, according to various embodiments, utilize a moderate inductive coupling along with an additional electrical coupling mechanism through coupling capacitors (CC) from the primary to the secondary coil. This combination of magnetic and electric coupling results in wide pole splitting and gain equalization between the two pole frequencies. Moreover, moderate inductive coupling makes coupled-resonators realizable on chip while consuming area similar to only a single inductor footprint.

In non-resonant mode, switches S1, S2, S3, and S4 are controlled so that driver circuits 316a, 316b are respectively coupled to first nodes <NUM>, <NUM>. In addition, switches S5 and S6 are controlled so that coupled-resonator network <NUM> does not contribute in a significant way to the clock signals provided at first nodes <NUM>, <NUM>.

In non-resonant mode operation, driver circuit 208a receives the first periodic signal <NUM> and generates a clock signal (not shown). Driver circuit 208a generates a clock signal in the form of a square wave (similar to signal <NUM>) at a first power level. In addition, driver circuit 316a receives the first periodic signal <NUM> and generates periodic signal <NUM>. In various embodiments, periodic signal <NUM> is a square wave signal. Driver circuit 316a generates periodic signal at a second power level. In various embodiments, the second power level is higher than the first power level. Driver circuit 316a sources and sinks more current than driver circuit 208a.

In addition, in non-resonant mode operation, driver circuit 208b receives the first periodic signal <NUM> and generates a clock signal (not shown). Driver circuit 208b generates a clock signal in the form of a square wave (similar to signal <NUM>) at a third power level. In addition, driver circuit 316b receives the first periodic signal <NUM> and generates periodic signal <NUM>. In various embodiments, periodic signal <NUM> is a square wave signal. Driver circuit 316b generates periodic signal at a fourth power level. In various embodiments, the fourth power level is higher than the third power level. Driver circuit 316b sources and sinks more current than driver circuit 208b.

The clock signal provided at the first node <NUM> is comprised of the clock signal output from driver 208a and periodic signal <NUM>. The clock signal provided at the first node <NUM> is comprised of the complementary clock signal output from driver 208b and periodic signal <NUM>. The differential clock signals provided at the first nodes <NUM>, <NUM> are provided at power levels that is at or above the amount of power required to provide a sufficient clock signal to all devices in clock distribution network <NUM>.

In non-resonant mode, driver circuits 316a, 316b advantageously increase the power in the clock signal provided to the clock distribution network as compared with the amount of power that would be provided by driver circuits 208a, 208b alone. Driver circuits 316a, 316b also improve the slew rate that driver circuits 208a, 208b alone provide. Coupled-resonator network <NUM> does not contribute in a significant way to the clock signal provided at the first nodes <NUM>, <NUM>. The clock signals provided at the first nodes <NUM>, <NUM> are provided at power levels that are at or above the amount of power required to provide a sufficient clock signal to all devices in clock distribution network <NUM>.

<FIG> illustrates a smart device or a computer system or an SoC (System-on-Chip) having a resonant clocking apparatus or a clocking apparatus having a resonant mode in accordance with various embodiments. It is pointed out that those elements of <FIG> having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, device <NUM> represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an Internet-of-Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in device <NUM>.

In an example, the device <NUM> comprises a SoC (System-on-Chip) <NUM>. An example boundary of the SOC <NUM> is illustrated using dotted lines in <FIG>, with some example components being illustrated to be included within SOC <NUM> - however, SOC <NUM> may include any appropriate components of device <NUM>.

In some embodiments, device <NUM> includes processor <NUM>. Processor <NUM> can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, processing cores, or other processing means. The processing operations performed by processor <NUM> include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, operations related to connecting computing device <NUM> to another device, and/or the like. The processing operations may also include operations related to audio I/O and/or display I/O.

In some embodiments, processor <NUM> includes multiple processing cores (also referred to as cores) 808a, 808b, 808c. Although merely three cores 808a, 808b, 808c are illustrated in <FIG>, the processor <NUM> may include any other appropriate number of processing cores, e.g., tens, or even hundreds of processing cores. Processor cores 808a, 808b, 808c may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches, buses or interconnections, graphics and/or memory controllers, or other components.

In some embodiments, processor <NUM> includes cache <NUM>. In an example, sections of cache <NUM> may be dedicated to individual cores <NUM> (e.g., a first section of cache <NUM> dedicated to core 808a, a second section of cache <NUM> dedicated to core 808b, and so on). In an example, one or more sections of cache <NUM> may be shared among two or more of cores <NUM>. Cache <NUM> may be split in different levels, e.g., level <NUM> (L1) cache, level <NUM> (L2) cache, level <NUM> (L3) cache, etc..

In some embodiments, a given processor core (e.g., core 808a) may include a fetch unit to fetch instructions (including instructions with conditional branches) for execution by the core 808a. The instructions may be fetched from any storage devices such as the memory <NUM>. Processor core 808a may also include a decode unit to decode the fetched instruction. For example, the decode unit may decode the fetched instruction into a plurality of micro-operations. Processor core 808a may include a schedule unit to perform various operations associated with storing decoded instructions. For example, the schedule unit may hold data from the decode unit until the instructions are ready for dispatch, e.g., until all source values of a decoded instruction become available. In one embodiment, the schedule unit may schedule and/or issue (or dispatch) decoded instructions to an execution unit for execution.

The execution unit may execute the dispatched instructions after they are decoded (e.g., by the decode unit) and dispatched (e.g., by the schedule unit). In an embodiment, the execution unit may include more than one execution unit (such as an imaging computational unit, a graphics computational unit, a general-purpose computational unit, etc.). The execution unit may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more an arithmetic logic units (ALUs). In an embodiment, a co-processor (not shown) may perform various arithmetic operations in conjunction with the execution unit.

Further, an execution unit may execute instructions out-of-order. Hence, processor core 808a (for example) may be an out-of-order processor core in one embodiment. Processor core 808a may also include a retirement unit. The retirement unit may retire executed instructions after they are committed. In an embodiment, retirement of the executed instructions may result in processor state being committed from the execution of the instructions, physical registers used by the instructions being de-allocated, etc. The processor core 808a may also include a bus unit to enable communication between components of the processor core 808a and other components via one or more buses. Processor core 808a may also include one or more registers to store data accessed by various components of the core 808a (such as values related to assigned app priorities and/or sub-system states (modes) association.

In some embodiments, device <NUM> comprises connectivity circuitries <NUM>. For example, connectivity circuitries <NUM> includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and/or software components (e.g., drivers, protocol stacks), e.g., to enable device <NUM> to communicate with external devices. Device <NUM> may be separate from the external devices, such as other computing devices, wireless access points or base stations, etc..

In an example, connectivity circuitries <NUM> may include multiple different types of connectivity. To generalize, the connectivity circuitries <NUM> may include cellular connectivity circuitries, wireless connectivity circuitries, etc. Cellular connectivity circuitries of connectivity circuitries <NUM> refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS) system or variations or derivatives, 3GPP Long-Term Evolution (LTE) system or variations or derivatives, 3GPP LTE-Advanced (LTE-A) system or variations or derivatives, Fifth Generation (<NUM>) wireless system or variations or derivatives, <NUM> mobile networks system or variations or derivatives, <NUM> New Radio (NR) system or variations or derivatives, or other cellular service standards. Wireless connectivity circuitries (or wireless interface) of the connectivity circuitries <NUM> refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), and/or other wireless communication. In an example, connectivity circuitries <NUM> may include a network interface, such as a wired or wireless interface, e.g., so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In some embodiments, device <NUM> comprises control hub <NUM>, which represents hardware devices and/or software components related to interaction with one or more I/O devices. For example, processor <NUM> may communicate with one or more of display <NUM>, one or more peripheral devices <NUM>, storage devices <NUM>, one or more other external devices <NUM>, etc., via control hub <NUM>. Control hub <NUM> may be a chipset, a Platform Control Hub (PCH), and/or the like.

For example, control hub <NUM> illustrates one or more connection points for additional devices that connect to device <NUM>, e.g., through which a user might interact with the system. For example, devices (e.g., devices <NUM>) that can be attached to device <NUM> include microphone devices, speaker or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, control hub <NUM> can interact with audio devices, display <NUM>, etc. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of device <NUM>. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display <NUM> includes a touch screen, display <NUM> also acts as an input device, which can be at least partially managed by control hub <NUM>. There can also be additional buttons or switches on computing device <NUM> to provide I/O functions managed by control hub <NUM>. In one embodiment, control hub <NUM> manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in device <NUM>. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In some embodiments, control hub <NUM> may couple to various devices using any appropriate communication protocol, e.g., PCle (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc..

In some embodiments, display <NUM> represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with device <NUM>. Display <NUM> may include a display interface, a display screen, and/or hardware device used to provide a display to a user. In some embodiments, display <NUM> includes a touch screen (or touch pad) device that provides both output and input to a user. In an example, display <NUM> may communicate directly with the processor <NUM>. Display <NUM> can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment display <NUM> can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In some embodiments and although not illustrated in the figure, in addition to (or instead of) processor <NUM>, device <NUM> may include Graphics Processing Unit (GPU) comprising one or more graphics processing cores, which may control one or more aspects of displaying contents on display <NUM>.

Control hub <NUM> (or platform controller hub) may include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections, e.g., to peripheral devices <NUM>.

It will be understood that device <NUM> could both be a peripheral device to other computing devices, as well as have peripheral devices connected to it. Device <NUM> may have a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device <NUM>. Additionally, a docking connector can allow device <NUM> to connect to certain peripherals that allow computing device <NUM> to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, device <NUM> can make peripheral connections via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

In some embodiments, connectivity circuitries <NUM> may be coupled to control hub <NUM>, e.g., in addition to, or instead of, being coupled directly to the processor <NUM>. In some embodiments, display <NUM> may be coupled to control hub <NUM>, e.g., in addition to, or instead of, being coupled directly to processor <NUM>.

In some embodiments, device <NUM> comprises memory <NUM> coupled to processor <NUM> via memory interface <NUM>. Memory <NUM> includes memory devices for storing information in device <NUM>. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory device <NUM> can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment, memory <NUM> can operate as system memory for device <NUM>, to store data and instructions for use when the one or more processors <NUM> executes an application or process. Memory <NUM> can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of device <NUM>.

Elements of various embodiments and examples are also provided as a machine-readable medium (e.g., memory <NUM>) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory <NUM>) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

In some embodiments, device <NUM> comprises temperature measurement circuitries <NUM>, e.g., for measuring temperature of various components of device <NUM>. In an example, temperature measurement circuitries <NUM> may be embedded, or coupled or attached to various components, whose temperature are to be measured and monitored. For example, temperature measurement circuitries <NUM> may measure temperature of (or within) one or more of cores 808a, 808b, 808c, voltage regulator <NUM>, memory <NUM>, a mother-board of SOC <NUM>, and/or any appropriate component of device <NUM>.

In some embodiments, device <NUM> comprises power measurement circuitries <NUM>, e.g., for measuring power consumed by one or more components of the device <NUM>. In an example, in addition to, or instead of, measuring power, the power measurement circuitries <NUM> may measure voltage and/or current. In an example, the power measurement circuitries <NUM> may be embedded, or coupled or attached to various components, whose power, voltage, and/or current consumption are to be measured and monitored. For example, power measurement circuitries <NUM> may measure power, current and/or voltage supplied by one or more voltage regulators <NUM>, power supplied to SOC <NUM>, power supplied to device <NUM>, power consumed by processor <NUM> (or any other component) of device <NUM>, etc..

In some embodiments, device <NUM> comprises one or more voltage regulator circuitries, generally referred to as voltage regulator (VR) <NUM>. VR <NUM> generates signals at appropriate voltage levels, which may be supplied to operate any appropriate components of the device <NUM>. Merely as an example, VR <NUM> is illustrated to be supplying signals to processor <NUM> of device <NUM>. In some embodiments, VR <NUM> receives one or more Voltage Identification (VID) signals, and generates the voltage signal at an appropriate level, based on the VID signals. Various type of VRs may be utilized for the VR <NUM>. For example, VR <NUM> may include a "buck" VR, "boost" VR, a combination of buck and boost VRs, low dropout (LDO) regulators, switching DC-DC regulators, etc. Buck VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is smaller than unity. Boost VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is larger than unity. In some embodiments, each processor core has its own VR which is controlled by PCU 810a/b and/or PMIC <NUM>. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital, analog, or a combination of digital or analog LDOs.

In some embodiments, device <NUM> comprises one or more clock generator circuitries, generally referred to as clock generator <NUM>. Clock generator <NUM> generates clock signals at appropriate frequency levels, which may be supplied to any appropriate components of device <NUM>. Merely as an example, clock generator <NUM> is illustrated to be supplying clock signals to processor <NUM> of device <NUM>. In some embodiments, clock generator <NUM> receives one or more Frequency Identification (FID) signals, and generates the clock signals at an appropriate frequency, based on the FID signals.

In some embodiments, device <NUM> comprises battery <NUM> supplying power to various components of device <NUM>. Merely as an example, battery <NUM> is illustrated to be supplying power to processor <NUM>. Although not illustrated in the figures, device <NUM> may comprise a charging circuitry, e.g., to recharge the battery, based on Alternating Current (AC) power supply received from an AC adapter.

In some embodiments, device <NUM> comprises Power Control Unit (PCU) <NUM> (also referred to as Power Management Unit (PMU), Power Controller, etc.). In an example, some sections of PCU <NUM> may be implemented by one or more processing cores <NUM>, and these sections of PCU <NUM> are symbolically illustrated using a dotted box and labelled PCU 810a. In an example, some other sections of PCU <NUM> may be implemented outside the processing cores <NUM>, and these sections of PCU <NUM> are symbolically illustrated using a dotted box and labelled as PCU 810b. PCU <NUM> may implement various power management operations for device <NUM>. PCU <NUM> may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device <NUM>.

In some embodiments, device <NUM> comprises Power Management Integrated Circuit (PMIC) <NUM>, e.g., to implement various power management operations for device <NUM>. In some embodiments, PMIC <NUM> is a Reconfigurable Power Management ICs (RPMICs) and/or an IMVP (Intel® Mobile Voltage Positioning). In an example, the PMIC is within an IC chip separate from processor <NUM>. The PMIC <NUM> may implement various power management operations for device <NUM>. PMIC <NUM> may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device <NUM>.

In an example, device <NUM> comprises one or both PCU <NUM> or PMIC <NUM>. In an example, any one of PCU <NUM> or PMIC <NUM> may be absent in device <NUM>, and hence, these components are illustrated using dotted lines.

Various power management operations of device <NUM> may be performed by PCU <NUM>, by PMIC <NUM>, or by a combination of PCU <NUM> and PMIC <NUM>. For example, PCU <NUM> and/or PMIC <NUM> may select a power state (e.g., P-state) for various components of device <NUM>. For example, PCU <NUM> and/or PMIC <NUM> may select a power state (e.g., in accordance with the ACPI (Advanced Configuration and Power Interface) specification) for various components of device <NUM>. Merely as an example, PCU <NUM> and/or PMIC <NUM> may cause various components of the device <NUM> to transition to a sleep state, to an active state, to an appropriate C state (e.g., C0 state, or another appropriate C state, in accordance with the ACPI specification), etc. In an example, PCU <NUM> and/or PMIC <NUM> may control a voltage output by VR <NUM> and/or a frequency of a clock signal output by the clock generator, e.g., by outputting the VID signal and/or the FID signal, respectively. In an example, PCU <NUM> and/or PMIC <NUM> may control battery power usage, charging of battery <NUM>, and features related to power saving operation.

The clock generator <NUM> can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor <NUM> has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU <NUM> and/or PMIC <NUM> performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, PCU <NUM> and/or PMIC <NUM> determines the operating condition of each core of a processor, and opportunistically adjusts frequency and/or power supply voltage of that core without the core clocking source (e.g., PLL of that core) losing lock when the PCU <NUM> and/or PMIC <NUM> determines that the core is operating below a target performance level. For example, if a core is drawing current from a power supply rail less than a total current allocated for that core or processor <NUM>, then PCU <NUM> and/or PMIC <NUM> can temporarily increase the power draw for that core or processor <NUM> (e.g., by increasing clock frequency and/or power supply voltage level) so that the core or processor <NUM> can perform at a higher performance level. As such, voltage and/or frequency can be increased temporality for processor <NUM> without violating product reliability.

In an example, PCU <NUM> and/or PMIC <NUM> may perform power management operations, e.g., based at least in part on receiving measurements from power measurement circuitries <NUM>, temperature measurement circuitries <NUM>, charge level of battery <NUM>, and/or any other appropriate information that may be used for power management. To that end, PMIC <NUM> is communicatively coupled to one or more sensors to sense/detect various values/variations in one or more factors having an effect on power/thermal behavior of the system/platform. Examples of the one or more factors include electrical current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be provided in physical proximity (and/or thermal contact/coupling) with one or more components or logic/IP blocks of a computing system. Additionally, sensor(s) may be directly coupled to PCU <NUM> and/or PMIC <NUM> in at least one embodiment to allow PCU <NUM> and/or PMIC <NUM> to manage processor core energy at least in part based on value(s) detected by one or more of the sensors.

Also illustrated is an example software stack of device <NUM> (although not all elements of the software stack are illustrated). Merely as an example, processors <NUM> may execute application programs <NUM>, Operating System <NUM>, one or more Power Management (PM) specific application programs (e.g., generically referred to as PM applications <NUM>), and/or the like. PM applications <NUM> may also be executed by the PCU <NUM> and/or PMIC <NUM>. OS <NUM> may also include one or more PM applications 856a, 856b, 856c. The OS <NUM> may also include various drivers 854a, 854b, 854c, etc., some of which may be specific for power management purposes. In some embodiments, device <NUM> may further comprise a Basic Input/Output System (BIOS) <NUM>. BIOS <NUM> may communicate with OS <NUM> (e.g., via one or more drivers <NUM>), communicate with processors <NUM>, etc..

For example, one or more of PM applications <NUM>, <NUM>, drivers <NUM>, BIOS <NUM>, etc. may be used to implement power management specific tasks, e.g., to control voltage and/or frequency of various components of device <NUM>, to control wake-up state, sleep state, and/or any other appropriate power state of various components of device <NUM>, control battery power usage, charging of the battery <NUM>, features related to power saving operation, etc..

As described above, device <NUM> comprises one or more clock generator circuitries, generally referred to as clock generator <NUM>. Resonant clocking apparatus <NUM>, clocking apparatus <NUM>, resonant clocking apparatus <NUM>, resonant clocking apparatus <NUM>, and clocking apparatus <NUM> are specific examples of these one or more clock generator circuitries generally referred to as clock generator <NUM>. In various embodiments, device <NUM> comprises one or more instances of a resonant clocking apparatus or a clocking apparatus having a resonant mode according to the principles described herein. An instance of a resonant clocking apparatus is used to drive a clock signal to a local clock distribution network in various embodiments. In some embodiments, clocking apparatus <NUM> and clocking apparatus <NUM> are used to drive a clock signal to a local clock distribution network at two different frequencies. In some embodiments, resonant clocking apparatus <NUM>, clocking apparatus <NUM>, resonant clocking apparatus <NUM>, and resonant clocking apparatus <NUM> are used to drive a single-ended clock signal to a local clock distribution network. In some embodiments, clocking apparatus <NUM>, is used to drive a differential clock signal to a local clock distribution network.

Driver circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> comprise one or more instances of a circuit or circuitry. Coupled-resonator networks <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> comprise one or more instances of a circuit or circuitry. As used herein, the terms "circuit" and "circuitry" comprise various electronic and electrical devices ("hardware"). Examples of hardware include analog circuits and analog circuit components (e.g., resistors, capacitors, inductors, diodes, and transistors). Other examples of hardware include digital circuits and digital circuit components, such as logic devices implementing Boolean functions. Examples of digital circuits include programmable logic devices (PLD), field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), processors, processor cores, microprocessors, microcontrollers, digital signal processors (DSP), and graphics processors. In yet another example, hardware includes a circuit that may be synthesized using a hardware description language (HDL) and which implements a state machine or other logic circuit. It should be understood that when hardware executes instructions stored in a memory device, the term hardware includes the stored instructions. Additional examples of hardware include volatile and non-volatile memory devices, such as registers, read-only memory (ROM), random access memory (RAM), and flash memory. Circuits and circuitry can include two or more instances of circuitry. Circuits and circuitry may comprise a combination of hardware elements that cooperate to provide one or more functions. A particular instance of a circuits and circuitry may be referred to with a descriptive or non-descriptive label. For example, instances of circuits and circuitry that perform various functions may be referred to as receiver circuitry, processor circuitry, first circuit, or second circuit. Each of two or more instances of a circuit and circuitry can be comprised of distinct components. In addition, two or more instances of a circuit or circuitry can share one or more common components or resources.

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description.

Claim 1:
An apparatus (<NUM>) comprising:
a driver circuit (<NUM>) to generate a clock signal at an output (<NUM>), wherein the clock signal comprises both a first component comprising a first frequency, and a second component comprising a second frequency, wherein the second frequency is a harmonic of the first frequency; and
a resonator circuit (<NUM>) coupled to the output (<NUM>) via a node (<NUM>), the resonator circuit (<NUM>) to receive the clock signal at the node (<NUM>) while the resonator circuit (<NUM>) and the driver circuit (<NUM>) are to be coupled to a clock distribution network (<NUM>) via the node (<NUM>), wherein, based on an impedance of the clock distribution network (<NUM>), the resonator circuit (<NUM>) is to attenuate a difference between a first phase of the first component, and a second phase of the second component, wherein the resonator circuit (<NUM>) comprises a first inductor, a second inductor to be magnetically coupled with the first inductor, and a first capacitor (<NUM>) which is coupled between the first inductor and the second inductor, wherein the first capacitor (<NUM>) is coupled to the first inductor via the node (<NUM>) and coupled to the second inductor via a second node (<NUM>), and a second capacitor (<NUM>) is coupled to the second inductor via the second node (<NUM>).