Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. <CIT> discloses a NAND memory and a preparation method therefor. The NAND memory comprises a silicon substrate, a plurality of peripheral devices, a plurality of NAND strings formed above the peripheral devices, a monocrystal silicon layer formed above the multiple NAND strings, and one or more first interconnection layers formed between the multiple peripheral devices separately, mutual influence to the processing process of the two devices in manufacturing can be avoided, so that the problem of limitation to the post layer manufacturing by the temperature of the former layer in the prior art can be solved, thereby obtaining high peripheral device performance; and in addition, the array devices are overlaid on the peripheral devices, so that high device density is realized.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

3D memory devices and methods for forming the same according to the invention are presented in independent claims <NUM> and <NUM>.

Embodiments of the invention are presented in the dependent claims.

In one example, a 3D memory device includes a substrate, a memory stack on the silicon substrate including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer comprising single crystalline silicon above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel A bottom surface of the semiconductor plug is above a top surface of the memory stack, and a top surface of the semiconductor plug is flush with a top surface of the semiconductor layer.

In another example, which is not part of the invention, a 3D memory device includes a first memory deck including a first plurality of interleaved conductive layers and dielectric layers, an etch stop layer on the first memory deck, a second memory deck including a second plurality of interleaved conductive layers and dielectric layers on the etch stop layer, a channel structure extending vertically through the first and second memory decks and the etch stop layer, and a semiconductor plug above a top surface of the second memory deck and in contact with the channel structure.

In still another example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a front side of a first substrate. A channel hole is formed through the dielectric stack. A memory film and a semiconductor channel are formed along a sidewall and on a bottom surface of the channel hole. A memory stack including interleaved conductive layers and dielectric layers is formed by replacing the sacrificial layers in the dielectric stack with the conductive layers. The first substrate is attached to a second substrate. The front side of the first substrate is toward the second substrate. The first substrate is thinned from a backside of the first substrate to remove parts of the memory film and semiconductor channel on the bottom surface of the channel hole. A semiconductor plug is formed in the thinned first substrate to contact the semiconductor channel. A bottom surface of the semiconductor plug is formed above a top surface of the memory stack, and a top surface of the semiconductor plug is flush with a top surface of the semiconductor layer.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used.

It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

Based on the particular technology node, the term "about" can indicate a value of a given quantity that varies within, for example, <NUM>-<NUM>% of the value (e.g., ± <NUM>%, ±<NUM>%, or ±<NUM>% of the value).

In some 3D memory devices, such as 3D NAND memory devices, a semiconductor plug is typically formed at one end of a NAND memory string, which acts as the channel of a transistor to control the source of the NAND memory string. In fabricating 3D NAND memory devices with advanced technologies, such as having <NUM> or more levels, a dual-deck architecture is usually used, which requires removal of a sacrificial layer that temporarily fills the lower channel hole in the lower deck above the semiconductor plug and filling of both lower and upper channel holes together at once with memory film and semiconductor channel (known as "single channel formation" (SCF)).

For example, <FIG> illustrates a cross-section of an exemplary 3D memory device <NUM> at a fabrication stage for forming a NAND memory string <NUM> extending vertically through a dual-deck dielectric stack <NUM> (including a lower dielectric deck 104A and an upper dielectric deck 104B) above a substrate <NUM>. Each of lower and upper dielectric decks 104A and 104B includes a plurality of pairs each including a sacrificial layer <NUM> and a dielectric layer <NUM> (referred to herein as "dielectric layer pairs"). Once all the fabrication processes are finished, dielectric stack <NUM> is replaced with a memory stack by a gate replacement process, which replaces each sacrificial layer <NUM> with a conductive layer. NAND memory string <NUM> includes a lower channel structure 112A and an upper channel structure 112B formed through lower dielectric deck 104A and upper dielectric deck 104B, respectively. NAND memory string <NUM> also includes a semiconductor plug <NUM> at its lower end and a channel plug <NUM> at its upper end. As shown in <FIG>, semiconductor plug <NUM> extends into part of substrate <NUM>, i.e., below the top surface of substrate <NUM>.

Lower channel structure 112A and upper channel structure 112B (collectively referred to as "channel structure" <NUM>) includes a memory film <NUM> and a semiconductor channel <NUM> along its sidewall and on its bottom surface. In order to contact semiconductor channel <NUM> to semiconductor plug <NUM> underneath memory film <NUM>, a "SONO punch" process needs to be performed to etch through a blocking layer <NUM>, a storage layer <NUM>, and a tunneling layer <NUM> forming memory film <NUM> and a channel sacrificial layer (not shown) on the bottom surface of lower channel structure 112A. Since the SONO punch process uses high-energy etchant plasma, there is a narrow process margin (e.g., less than <NUM>) for upper channel structure 112B and lower channel structure 112A to overlay at their joint location to avoid sidewall damages at the joint location and/or under-etch on the bottom surface.

Further, to form semiconductor plug <NUM> and accommodate the SONO punch process, the channel sacrificial layer needs to be first deposited over memory film <NUM>, then etched back to form a recess for channel plug <NUM>, and eventually replaced by semiconductor channel <NUM>, which increases process complexity and cost. The use of the channel sacrificial layer also reduces the yield because of the void formation and wafer bow and warpage issues caused by filling the channel sacrificial layer. In some situations, the removal of the channel sacrificial layer may also cause damages to semiconductor plug <NUM> underneath and/or leave residuals in the channel hole, which can directly lead to cell function failure.

Various embodiments in accordance with the present disclosure provide a backside substrate thinning process, which can replace the conventional SONO punch process, for forming a semiconductor plug in 3D memory devices. The process can release more margin for upper channel hole overlay, thereby easing the challenges of photolithograph alignment and etching processes in making the upper channel hole. The elimination of the SONO punch process and channel sacrificial layer can reduce the cell malfunction risk caused by bottom under-etch, sidewall and semiconductor plug damages, channel hole residuals, etc. Further, in some embodiments, an etch stop layer is formed between upper and lower dielectric decks to reduce the risk of damaging the dielectric layer pairs in the lower dielectric deck caused by the shift of upper channel hole overlay.

<FIG> illustrates a cross-section of an exemplary 3D memory device <NUM>, according to some embodiments of the present disclosure. 3D memory device <NUM> comprises a silicon substrate. The silicon substrate can be single crystalline silicon, silicon germanium (SiGe), silicon on insulator, or any other silicon substrates. In examples not part of the invention, the substrate can be gallium arsenide (GaAs), germanium (Ge), germanium on insulator (GOI), glass, quartz, or any other suitable materials. In some embodiments, substrate <NUM> is a carrier substrate. As described below in detail, the carrier substrate can be attached to the front side of a thinned memory array device chip <NUM> at a joining interface <NUM> using any suitable joining processes, such as bonding, adhesion, fusion, etc. It is understood that in some embodiments, the carrier substrate is removed from 3D memory device <NUM> after the formation of thinned memory array device chip <NUM>. As shown in <FIG>, thinned memory array device chip <NUM> includes a memory stack <NUM> (including a first memory deck 204A, an etch stop layer <NUM> on first memory deck <NUM>, and a second memory deck 204B on etch stop layer <NUM>) and a semiconductor layer <NUM> (e.g., a thinned substrate) above memory stack <NUM>. Semiconductor layer <NUM> can be formed by thinning a substrate using grinding, chemical mechanical polishing (CMP), and/or etching processes. In some embodiments, joining interface <NUM> is vertically between substrate <NUM> and memory stack <NUM>. An insulation layer <NUM>, such as a dielectric layer, is disposed vertically between memory stack <NUM> and semiconductor layer <NUM>, according to some embodiments.

It is noted that x and y axes are included in <FIG> to further illustrate the spatial relationship of the components in 3D memory device <NUM>. Substrate <NUM> of 3D memory device <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a 3D memory device (e.g., 3D memory device <NUM>) is determined relative to the substrate of the 3D memory device (e.g., substrate <NUM>) in the y-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the 3D memory device in the y-direction. The same notion for describing spatial relationship is applied throughout the present disclosure.

In some embodiments, 3D memory device <NUM> is a NAND Flash memory device in which memory cells are provided in the form of array of NAND memory strings <NUM> extending vertically above substrate <NUM>. The memory array device can include NAND memory strings <NUM> that extend through a plurality of pairs each including a conductive layer <NUM> and a dielectric layer <NUM> (referred to herein as "conductor/dielectric layer pairs"). The stacked conductive/dielectric layer pairs are also referred to herein as memory stack <NUM>. The number of the conductive/dielectric layer pairs in memory stack <NUM> (e.g., <NUM>, <NUM>, <NUM>, or <NUM>) determines the number of memory cells in 3D memory device <NUM>. Memory stack <NUM> includes a plurality of interleaved conductive layers <NUM> and dielectric layers <NUM>. Conductive layers <NUM> and dielectric layers <NUM> in memory stack <NUM> alternate in the vertical direction. Conductive layers <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

In some embodiments, memory stack <NUM> has a dual-deck architecture, which includes first memory deck 204A and second memory deck 204B. The numbers of conductive/dielectric layer pairs in each of first and second memory decks 204A and 204B can be the same or different. Memory stack <NUM> can further include etch stop layer <NUM> disposed vertically between first memory deck 204A and second memory deck 204B. Etch stop layer <NUM> can include a metal, such as W, Co, Cu, Al, or any combination thereof. In one example, etch stop layer <NUM> is a tungsten layer. Etch stop layer <NUM> can also include a semiconductor, such as polysilicon, amorphous silicon, silicides, or any combination thereof. Etch stop layer <NUM> can include any other suitable materials that are different from the materials forming dielectric layers <NUM> (e.g., silicon oxide) and another type of dielectric layers (e.g., silicon nitride) replaced by conductive layers <NUM>. The thickness of etch stop layer <NUM> can be between about <NUM> and about <NUM>, such as between <NUM> and <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). The thickness of etch stop layer <NUM> can be sufficiently thick to resist the etching in forming the channel hole through first memory deck 204A and also protect structures of second memory deck 204B from damages due to shift of channel hole overlay as described below in detail.

As shown in <FIG>, NAND memory string <NUM> includes a channel structure <NUM> extending vertically through memory stack <NUM>. Channel structure <NUM> can include a channel hole having two openings overlaid one over another. Each opening is formed through one of first and second memory decks 204A and 204B, according to some embodiments. A shift of overlay can occur when the two openings are not precisely aligned, as shown in <FIG>. The channel hole can be filled with semiconductor material(s) (e.g., as a semiconductor channel <NUM>) and dielectric material(s) (e.g., as a memory film <NUM>). In some embodiments, semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film <NUM> is a composite layer including a tunneling layer <NUM>, a storage layer <NUM> (also known as a "charge trap layer"), and a blocking layer <NUM>. The remaining space of channel structure <NUM> can be partially or fully filled with a capping layer <NUM> including dielectric materials, such as silicon oxide. Memory film <NUM> is disposed along the sidewall of channel structure <NUM>, and semiconductor channel <NUM> is disposed over memory film <NUM>, according to some embodiments. Channel structure <NUM> can have a cylinder shape (e.g., a pillar shape). Capping layer <NUM>, semiconductor channel <NUM>, tunneling layer <NUM>, storage layer <NUM>, and blocking layer <NUM> are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. Tunneling layer <NUM> can include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer <NUM> can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Blocking layer <NUM> can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, memory film <NUM> can include a composite layer of silicon oxide/silicon oxynitride (or silicon oxide)/silicon oxide ("ONO"), and semiconductor film can include a polysilicon layer ("S"), so that channel structure <NUM> can include a so-called "SONO" structure.

In some embodiments, conductive layer <NUM> in memory stack <NUM> functions as a gate conductor of memory cells in NAND memory string <NUM>. Conductive layer <NUM> can include multiple control gates of multiple NAND memory cells and can extend laterally as a word line ending at the edge of memory stack <NUM> (e.g., in a staircase structure of memory stack <NUM>). In some embodiments, memory cell transistors in NAND memory string <NUM> include gate conductors (i.e., parts of conductive layers <NUM> that abut channel structure <NUM>) made from tungsten, adhesion layers (not shown) including titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN), gate dielectric layers (not shown) made from high-k dielectric materials, and channel structure <NUM>.

In some embodiments, channel structure <NUM> of NAND memory string <NUM> further includes a channel plug <NUM> in the lower portion (e.g., at the lower end) of NAND memory string <NUM>. Channel plug <NUM> can be in contact with the lower portion of semiconductor channel <NUM>. As used herein, the "upper end" of a component (e.g., NAND memory string <NUM>) is the end farther away from substrate <NUM> in the y-direction, and the "lower end" of the component (e.g., NAND memory string <NUM>) is the end closer to substrate <NUM> in the y-direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>. Channel plug <NUM> can include semiconductor materials (e.g., polysilicon) or conductive materials (e.g., metals). In some embodiments, channel plug <NUM> includes a recess filled with Ti/TiN or Ta/TaN as an adhesion layer and tungsten as a conductor layer. In some embodiments, channel plug <NUM> functions as the drain of NAND memory string <NUM>.

In some embodiments, NAND memory string <NUM> further includes a semiconductor plug <NUM> in the upper portion (e.g., at the upper end) of NAND memory string <NUM>. Semiconductor plug <NUM> can function as a channel controlled by a source select gate of NAND memory string <NUM>. Different from <FIG> in which part of semiconductor plug <NUM> extends from substrate <NUM> into dielectric stack <NUM>, as shown in <FIG>, the entirety of semiconductor plug <NUM> can be in semiconductor layer <NUM> and above the top surface of memory stack <NUM>. The bottom surface of semiconductor plug <NUM> is above the top surface of memory stack <NUM>, and the top surface of semiconductor plug <NUM> is flush with the top surface of semiconductor layer <NUM>. The thickness of semiconductor plug <NUM> can be equal to or less than the thickness of semiconductor layer <NUM>.

As shown in <FIG>, due to the SONO punch process for forming semiconductor plug <NUM>, memory film <NUM> extends laterally along the bottom surface of lower channel structure 112A (i.e., the surface in contact with semiconductor plug <NUM>), and semiconductor channel <NUM> extends through part of memory film <NUM> on the bottom surface of lower channel structure 112A and further into semiconductor plug <NUM> to make contact. By replacing the SONO punch process with a backside substrate thinning process for forming semiconductor plug <NUM>, as shown in <FIG>, memory film <NUM> does not extend laterally along the top surface and the bottom surface of channel structure <NUM>, and the upper end of semiconductor channel <NUM> is in contact with the bottom surface of semiconductor plug <NUM> to make contact. In some embodiments, semiconductor plug <NUM> is above and in contact with the upper end of channel structure <NUM> (and memory film <NUM> and semiconductor channel <NUM> thereof).

In some embodiments, semiconductor plug <NUM> is an epitaxially-grown silicon plug, which can be formed by a selective epitaxial growth (SEG) process, and thereby also known as a "SEG plug. " Semiconductor plug <NUM> can include a semiconductor material, such as silicon, which is epitaxially grown from semiconductor layer <NUM>. It is understood that in some embodiments, semiconductor layer <NUM> is a thinned silicon substrate on which memory stack <NUM> and channel structure <NUM> were formed, and semiconductor plug <NUM> includes single crystalline silicon, the same material of semiconductor layer <NUM>. In other words, semiconductor plug <NUM> can include an epitaxially-grown semiconductor layer that is made of the same material as that of semiconductor layer <NUM>. In some embodiments, semiconductor plug <NUM> can be doped with p-type or n-type dopants at a doping concentration higher than that of semiconductor layer <NUM>. In some embodiments, semiconductor plug <NUM> is a deposited polysilicon plug or a silicide plug. Semiconductor plug <NUM> can include a recess in semiconductor layer <NUM> filled with polysilicon or filled with silicide by a self-aligned silicide (salicide) process, such as copper silicide, cobalt silicide, nickel silicide, titanium silicide, and tungsten silicide.

3D memory device <NUM> can be part of a non-monolithic 3D memory device, in which components (e.g., the peripheral device and memory array device) can be formed separately on different substrates and then bonded, for example, in a face-to-face manner. In some embodiments, 3D memory device <NUM> includes a peripheral device chip <NUM> having a peripheral device and a substrate. The peripheral device can include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>. For example, the peripheral device can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). In some embodiments, the peripheral device is formed on the substrate of peripheral device chip <NUM> using complementary metal-oxide-semiconductor (CMOS) technology (also known as a "CMOS chip").

As shown in <FIG>, peripheral device chip <NUM> (and the peripheral device and substrate thereof) can be disposed above semiconductor layer <NUM> of thinned memory array device chip <NUM>, for example, joined by the hybrid bonding process. Substrate <NUM> can thereby act as the device substrate of 3D memory device <NUM>. It is understood that although not shown in <FIG>, in some embodiments, substrate <NUM> is a carrier substrate, which is later removed from the final product of 3D memory device <NUM>. Peripheral device chip <NUM> can thereby be disposed below thinned memory array device chip <NUM>, for example, joined by a hybrid bonding process. The substrate of peripheral device chip <NUM> can thus act as the device substrate of 3D memory device <NUM>.

Although not shown in <FIG>, it is understood that 3D memory device <NUM> can further include an interconnect layer for middle-end-of-line (MEOL) interconnects and/or back-end-of-line (BEOL) interconnects. The interconnect layer can include interconnects, such as lateral interconnect lines and vertical via contacts in one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers"). The interconnect layer can further include contact pads and redistribution layers for pad-out. In some embodiments, the interconnect layer transfers electrical signals between 3D memory device <NUM> and external circuits and is electrically connected to the memory array devices and/or peripheral devices by local interconnects. The interconnect layer can be disposed in any suitable position in 3D memory device <NUM>, such as vertically between substrate <NUM> and thinned memory array device chip <NUM>, vertically between thinned memory array device chip <NUM> and peripheral device chip <NUM>, and/or above peripheral device chip <NUM>.

<FIG> illustrates a cross-section of an exemplary 3D memory device <NUM>, according to some embodiments of the present disclosure. Similar to 3D memory device <NUM> described above in <FIG>, <FIG> memory device <NUM> includes semiconductor plug <NUM> formed in semiconductor layer <NUM> using a backside substrate thinning process, instead of the SONO punch process. Different from 3D memory device <NUM> described above in <FIG> in which peripheral device chip <NUM> is disposed above thinned memory array device chip <NUM>, in <FIG>, peripheral device chip <NUM> is disposed below thinned memory array device chip <NUM> in 3D memory device <NUM>. It is understood that the details of counterpart structures (e.g., materials, fabrication process, functions, etc.) in both 3D memory devices <NUM> and <NUM> may not be repeated below.

Peripheral device chip <NUM> can include substrate <NUM> and peripheral device <NUM> formed on and/or in substrate <NUM>. Substrate <NUM> is not a carrier substrate in this example and cannot be removed from the final product of 3D memory device <NUM>. Rather, substrate <NUM> is the device substrate of 3D memory device <NUM> as well as the device substrate of peripheral device chip <NUM>, according to some embodiments. Peripheral device <NUM> can include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>. For example, peripheral device <NUM> can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors). Peripheral device <NUM> is disposed vertically between substrate <NUM> and memory stack <NUM>, according to some embodiments.

In some embodiments, peripheral device chip <NUM> (including peripheral device <NUM> and substrate <NUM> thereof) is bonded to thinned memory array device chip <NUM> in a face-to-face manner at joining interface <NUM>. Joining interface <NUM> can be a bonding interface at which peripheral device chip <NUM> and thinned memory array device chip <NUM> are bonded using hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. Joining interface <NUM> is vertically between substrate <NUM> and memory stack <NUM>.

Although not shown in <FIG>, it is understood that 3D memory device <NUM> can further include an interconnect layer for MEOL interconnects and/or BEOL interconnects. The interconnect layer can include interconnects, such as lateral interconnect lines and vertical via contacts in one or more ILD layers. The interconnect layer can further include contact pads and redistribution layers for pad-out. In some embodiments, the interconnect layer transfers electrical signals between 3D memory device <NUM> and external circuits and is electrically connected to the memory array devices and/or peripheral devices by local interconnects. The interconnect layer can be disposed in any suitable position in 3D memory device <NUM>, such as vertically between peripheral device <NUM> and thinned memory array device chip <NUM>, and/or above semiconductor layer <NUM> of thinned memory array device chip <NUM>.

<FIG> illustrate an exemplary fabrication process for forming a 3D memory device having a semiconductor plug using backside substrate thinning, according to some embodiments of the present disclosure. <FIG> illustrate a flowchart of an exemplary method <NUM> for forming a 3D memory device having a semiconductor plug using backside substrate thinning, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in <FIG> and <FIG> include 3D memory devices <NUM> and <NUM> depicted in <FIG>. <FIG> and 4A-4B will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a first dielectric deck is formed on a substrate. The substrate is a silicon substrate. The first dielectric deck includes a first plurality of interleaved sacrificial layers and dielectric layers. Referring to <FIG>, a first dielectric deck 304A including a plurality pairs of a first dielectric layer <NUM> and a second dielectric layer (known as a "sacrificial layer") <NUM> (together referred to herein as "dielectric layer pairs") is formed on the front side of a silicon substrate <NUM>. In some embodiments, an insulation layer <NUM> is formed between first dielectric deck 304A and silicon substrate <NUM> by depositing dielectric materials, such as silicon oxide, or thermal oxidation, on silicon substrate <NUM> prior to the formation of first dielectric deck 304A. First dielectric deck 304A includes interleaved sacrificial layers <NUM> and dielectric layers <NUM>.

Dielectric layers <NUM> and sacrificial layers <NUM> are alternatively deposited on silicon substrate <NUM> to form first dielectric deck 304A. In some embodiments, each dielectric layer <NUM> includes a layer of silicon oxide, and each sacrificial layer <NUM> includes a layer of silicon nitride. First dielectric deck 304A can be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first opening extending vertically through the first dielectric deck is formed. In some embodiments, to form the first opening, a gouging is formed through part of the first substrate. In some embodiments, a sacrificial layer is formed to fill in the first opening.

As illustrated in <FIG>, a first channel hole 310A is an opening formed extending vertically through first dielectric deck 304A. A plurality of openings are formed through first dielectric deck 304A, such that each opening becomes the location for forming an individual NAND memory string in the later process. In some embodiments, fabrication processes for forming first channel hole 310A include wet etching and/or dry etching, such as deep-ion reactive etching (DRIE). In some embodiments, first channel hole 310A extends further into the top portion of silicon substrate <NUM> to form a gouging <NUM> of first channel hole 310A. The etching process through first dielectric deck 304A may not stop at the top surface of silicon substrate <NUM> and may continue to etch part of silicon substrate <NUM>. In some embodiments, a separate etching process is used to etch part of silicon substrate <NUM> to form gouging <NUM> after etching through first dielectric deck 304A. As described below in detail, the depth of gouging <NUM> of first channel hole 310A is greater than gouging of any other structure through silicon substrate <NUM>, such as the slit openings and contact openings, to ensure that the later backside substrate thinning process would not damage other structures.

As illustrated in <FIG>, a sacrificial layer <NUM> is deposited using one or more thin film deposition processes, such as PVD, CVD, ALD, electroplating, electroless plating, or any combinations thereof, to partially or fully fill first channel hole 310A (including gouging <NUM>, shown in <FIG>). Sacrificial layer <NUM> can include any suitable materials that can be removed in a later process, such as polysilicon, carbon, photoresist, etc. In some embodiments, sacrificial layer <NUM> is planarized using a CMP process to make its top surface flush with the top surface of first dielectric deck 304A.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an etch stop layer is formed on the first dielectric deck to cover the first dielectric deck. In some embodiments, the etch stop layer covers the sacrificial layer in the first opening as well. As illustrated in <FIG>, an etch stop layer <NUM> is formed on first dielectric deck 304A and sacrificial layer <NUM> to completely cover first dielectric deck 304A and sacrificial layer <NUM>. In some embodiments, the thickness of etch stop layer <NUM> is between about <NUM> and about <NUM>, such as between <NUM> and <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). Etch stop layer <NUM> can be formed by depositing a metal, such as tungsten, or a semiconductor, such as polysilicon, using one or more thin film deposition processes, such as PVD, CVD, ALD, or any combinations thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second dielectric deck is formed on the etch stop layer. Similar to the first dielectric deck, the second dielectric deck can include a second plurality of interleaved sacrificial layers and dielectric layers. Referring to <FIG>, a second dielectric deck 304B including a plurality of dielectric layer pairs is formed on etch stop layer <NUM> above first dielectric deck 304A. Second dielectric deck 304B can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second opening extending vertically through the second dielectric deck is formed until being stopped by the etch stop layer. As illustrated in <FIG>, a second channel hole 310B is another opening formed extending vertically through second dielectric deck 304B until being stopped by etch stop layer <NUM>. Second channel hole 310B can be aligned with first channel hole 310A (shown in <FIG>) so as to overlay with at least part of first channel hole 310A, such that first and second channel holes 310A and 310B can be connected once sacrificial layer <NUM> is removed. In some embodiments, fabrication processes for forming second channel hole 310B include wet etching and/or dry etching, such as DRIE. Because etch stop layer <NUM> can protect structures of first dielectric deck 304A from damages due to the etching of second channel hole 310B, the misalignment margin (i.e., the shift of overlay) can be increased by the fabrication process disclosed herein, compared with the conventional fabrication process for forming dual-deck 3D memory devices (e.g., 3D memory device <NUM> in <FIG>).

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which part of the etch stop layer is removed, such that the first and second openings are connected to form a channel hole. In some embodiments, the sacrificial layer filling the first opening is exposed and removed after the removal of the part of etch stop layer. As illustrated in <FIG>, part of etch stop layer <NUM> in which first and second openings 310A and 310B are overlaid is removed, for example, using dry etching and/or wet etching processes. Additional part of etch stop layer <NUM> may be etched back (not shown) due to isotropic etching, for example, by wet etching. Once the part of etch stop layer <NUM> is removed, sacrificial layer <NUM> (shown in <FIG>) can be exposed from second channel hole 310B. As illustrated in <FIG>, sacrificial layer <NUM> is removed in first dielectric deck 304A by wet etching and/or dry etching processes. After the removal of sacrificial layer <NUM>, first channel hole 310A becomes open again and connected with second channel hole 310B to form a channel hole <NUM>, as shown in <FIG>, which extends vertically through first and second dielectric decks 304A and 304B and etch stop layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a memory film and a semiconductor channel are formed along a sidewall and on a bottom surface of the channel hole. In some embodiments, the memory film is first formed along the sidewall and on the bottom surface of the channel hole, and a semiconductor channel is formed over the memory film. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer are subsequently deposited along the sidewall and on the bottom surface of the channel hole in this order to form the memory film and semiconductor channel. In some embodiments, a capping layer is deposited to fill the remaining space of the channel hole after the formation of the semiconductor channel.

As illustrated in <FIG>, a memory film <NUM> (including a blocking layer <NUM>, a storage layer <NUM>, and a tunneling layer <NUM>) and a semiconductor channel <NUM> are formed along the sidewall and bottom surface of channel hole <NUM>. In some embodiments, memory film <NUM> is first deposited along the sidewall and bottom surface of channel hole <NUM>, and semiconductor channel <NUM> is then deposited over memory film <NUM>. Blocking layer <NUM>, storage layer <NUM>, and tunneling layer <NUM> can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form memory film <NUM>. Semiconductor channel <NUM> can then be formed by depositing polysilicon or any other suitable semiconductor materials on tunneling layer <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As shown in <FIG>, memory film <NUM> and semiconductor channel <NUM> can cover both the bottom surface and the sidewall of channel hole <NUM>. In some embodiments, a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a polysilicon layer (an "SONO" structure) are subsequently deposited to form memory film <NUM> and semiconductor channel <NUM>. Different from some 3D memory devices (e.g., 3D memory device <NUM> in <FIG>) using a channel sacrificial layer, which is later removed after the SONO punch process and before the deposition of a semiconductor channel, semiconductor channel <NUM> deposited over memory film <NUM> remains through all the later fabrication processes and in the resulting 3D memory device. In other words, a channel sacrificial layer is no long needed in the fabrication process disclosed herein.

As illustrated in <FIG>, a capping layer <NUM>, such as a silicon oxide layer, is formed in channel hole <NUM> (shown in <FIG>) to fully or partially fill the remaining space of channel hole <NUM> using one or more thin film deposition processes, such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. In some embodiments, parts of memory film <NUM>, semiconductor channel <NUM>, and capping layer <NUM> that are on the top surface of second dielectric deck 304B are removed and planarized by CMP, wet etching, and/or dry etching.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a channel plug is formed in the upper portion of the channel hole to contact the semiconductor channel. As illustrated in <FIG>, a channel plug <NUM> is formed in the upper portion of channel hole <NUM> (shown in <FIG>). A recess can then be formed in the upper portion of channel hole <NUM> by wet etching and/or drying etching parts of memory film <NUM>, semiconductor channel <NUM>, and capping layer <NUM> in the upper portion of channel hole <NUM>. Channel plug <NUM> can then be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. A channel structure <NUM> is thereby formed.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a memory stack including interleaved conductive layers and dielectric layers is formed by replacing the sacrificial layers in the dielectric stack with the conductive layers. In some embodiments, to form the memory stack, a slit opening is formed through the dielectric stack. The gouging of the slit opening can be formed through part of the first substrate. In some embodiments, the depth of the gouging of the channel hole is greater than the depth of the gouging of the slit opening.

As illustrated in <FIG>. a slit opening (e.g., a gate line slit) is formed through dielectric stack <NUM> (including first and second dielectric decks 304A and 304B and etch stop layer <NUM> shown in <FIG>) using wet etching and/or dry etching process, such as DRIE. In some embodiments, a separate etching process is used to extend the slit opening into part of silicon substrate <NUM> to form a gouging <NUM> of the slit opening. The depth of gouging <NUM> of channel hole <NUM> can be greater than gouging <NUM> of the slit opening. In other words, the lower end of gouging <NUM> is farther away from the backside of silicon substrate <NUM> than the lower end of gouging <NUM>. As a result, when thinning silicon substrate <NUM> from its backside in the later process, structure in gouging <NUM> of the slit opening would not be damaged when the thinning stopped at the lower end of gouging <NUM>. Similarly, the depths of gougings of other openings (e.g., contact holes) through the front side of silicon substrate <NUM> are smaller than the depth of gouging <NUM> of channel hole <NUM>.

As illustrated in <FIG>, a dual-deck memory stack <NUM> including interleaved conductive layers <NUM> and dielectric layer <NUM> is formed by a gate replacement process. Sacrificial layers <NUM> in dielectric stack <NUM> (shown in <FIG>) can be etched away using wet etching and/or drying etching processes. The replacement of sacrificial layers <NUM> with conductive layers <NUM> can be performed by wet etching and/or drying etching of sacrificial layers <NUM> selective to dielectric layers <NUM> and filling the resulting lateral recesses with conductive layers <NUM>. In some embodiments, wet etchants are applied through the slit opening to remove sacrificial layers <NUM>, leaving lateral recesses between dielectric layers <NUM>. The lateral recesses can be filled with conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, polysilicon, silicides, or any combination thereof. Conductive layers <NUM> can be filled by one or more thin film deposition processes, such as CVD, ALD, PVD, any other suitable process, or any combination thereof. The conductive materials can be deposited into the lateral recesses through the slit opening.

As illustrated in <FIG>, a slit structure <NUM> (e.g., a gate line slit, "GLS") extending vertically through memory stack <NUM> and part of silicon substrate <NUM> is formed. Slit structure <NUM> can include a doped region <NUM> at its lower end in silicon substrate <NUM>, a spacer <NUM> along its sidewall, and a slit contact <NUM> electrically insulated from conductive layers <NUM> by spacer <NUM>. In some embodiments, doped region <NUM> is formed by ion implantation and/or thermal diffusion to dope part of silicon substrate <NUM> surrounding gouging <NUM> of the slit opening. In some embodiments, spacer <NUM> and slit contact <NUM> are formed by subsequently depositing dielectric materials (e.g., silicon oxide) and conductive materials (e.g., tungsten) in the slit opening by one or more thin film deposition processes, such as CVD, ALD, PVD, any other suitable process, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate is attached to a second substrate. The front side of the first substrate is toward the second substrate. In some embodiments, a peripheral device is formed on the second substrate prior to the attachment. In some embodiments, the second substrate is a carrier substrate without any device formed thereon.

As illustrated in <FIG>, once all the front side processes are finished on silicon substrate <NUM>, i.e., all the devices and structures on the front side of silicon substrate <NUM> have been formed, the structures and devices (e.g., memory stack <NUM> and channel structure <NUM>) formed on the front side of silicon substrate <NUM> are attached to a substrate <NUM> at a joining interface <NUM> using any suitable joining processes. That is, the front side of silicon substrate <NUM> is toward substrate <NUM> when silicon substrate <NUM> is attached to substrate <NUM>, according to some embodiments. In some embodiments, substrate <NUM> is a carrier substrate without any devices or structures formed thereon. The front side of silicon substrate <NUM> can be attached to the carrier substrate (e.g., a bare silicon wafer) using thermal bonding, adhesion, fusion, any other suitable process, or any combination thereof.

In some embodiments, a peripheral device (not shown), such as transistors, is formed on or in substrate <NUM> prior to the attachment by a plurality of processes including, but not limited to, photolithography, dry etching, wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. Substrate <NUM> with the peripheral device can be bonded with silicon substrate <NUM> using hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. The metal-metal bonding can be formed between bonding contacts at joining interface <NUM>, and the dielectric-dielectric bonding can be formed between the dielectric materials at the remaining areas at joining interface <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate is thinned from the backside to remove parts of the memory film and semiconductor channel on the bottom surface of the channel hole. As illustrated in <FIG>, the resulting structure including attached silicon substrate <NUM> and substrate <NUM> is flipped upside down, such that the backside of silicon substrate <NUM> can face up for the backside thinning process and substrate <NUM> can support the resulting structure during the thinning process. Silicon substrate <NUM> can be thinned from its backside (now facing up) using grinding, CMP, etching, any other suitable process, or any combination thereof to reduce its thickness. The rate and/or time of the thinning process can be controlled, such that parts of memory film <NUM> and semiconductor channel <NUM> on the bottom surface of channel hole <NUM> of channel structure <NUM> are removed after the thinning process. It is noted that because memory stack <NUM> is flipped upside down, the bottom surface of channel structure <NUM> becomes the top surface in <FIG> and later figures. Nevertheless, this is the surface opposite to the surface on which channel plug <NUM> is formed and is the surface on which memory film <NUM> and semiconductor channel <NUM> extend laterally. Once the thinning process is completed, memory film <NUM> and semiconductor channel <NUM> do not have any parts that extend laterally on the bottom surface or top surface of channel structure <NUM>. A semiconductor layer <NUM> is thereby formed as the thinned silicon substrate <NUM> after the backside substrate thinning process.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which parts of the memory film and semiconductor channel in the thinned first substrate are removed using wet etching and/or dry etching processes to form a recess. As illustrated in <FIG>, a recess <NUM> is formed in semiconductor layer <NUM> by removing parts of memory film <NUM>, semiconductor channel <NUM>, and capping layer <NUM> in semiconductor layer <NUM>. In some embodiments, part of semiconductor layer <NUM> surrounding memory film <NUM> is removed as well. The etching rate and/or time can be controlled to control the depth of recess <NUM>. In some embodiments, the bottom surface of recess <NUM> and the upper ends of memory film <NUM> and semiconductor channel <NUM> are above the top surface of memory stack <NUM>, as shown in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a semiconductor plug is formed in the recess of the thinned first substrate to contact the semiconductor channel. The semiconductor plug can be epitaxially grown from the thinned first substrate. In some embodiments, the semiconductor is formed by depositing the semiconductor plug in the recess.

As illustrated in <FIG>, in some embodiments, a semiconductor plug <NUM> is formed by filling recess <NUM> (shown in <FIG>) with single crystalline silicon epitaxially grown from semiconductor layer <NUM> (thinned silicon substrate <NUM>) from its side surfaces. The fabrication processes for forming epitaxially semiconductor plug <NUM> can include, but not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combinations thereof. In some embodiments, semiconductor plug <NUM> is doped with n-type or n-type dopants to a doping concentration greater than semiconductor layer <NUM> using ion implantation and/or thermal diffusion.

In some embodiments, semiconductor plug <NUM> is formed by depositing a layer of semiconductor into recess <NUM>, such as a polysilicon layer, using one or more thin film deposition processes, such as CVD, ALD, PVD, any other suitable process, or any combination thereof. In some embodiments, semiconductor plug <NUM> is formed by a salicide process, i.e., deposition a layer of metal into recess <NUM> and silicidation of the silicon in semiconductor layer <NUM> and the deposited metal layer by a thermal treatment (e.g., annealing, sintering, or any other suitable process). In some embodiments, both a silicon layer and a metal layer are deposited into recess <NUM> to form a silicide plug in recess by a silicidation process. Once semiconductor plug <NUM> is formed in recess <NUM>, it can contact channel structure <NUM> including semiconductor channel <NUM>. In some embodiments in which the bottom surface of recess <NUM> is above the top surface of memory stack <NUM>, the bottom surface of semiconductor plug <NUM> filling recess <NUM> is above the top surface of memory stack <NUM> as well.

Once the semiconductor plug is formed in the thinned first substrate, additional structures can be formed above the thinned first substrate. In some embodiments, a peripheral device and/or an interconnect layer formed on a separate substrate is bonded with the structure shown in <FIG> in a face-to-face manner to form a non-monolithic 3D memory device in which the peripheral device is disposed above the memory array device. In some embodiments, substrate <NUM> is a carrier substrate that can be removed and replaced with another substrate having a peripheral device and/or an interconnect layer to form a non-monolithic 3D memory device in which the peripheral device is disposed below the memory array device. In some embodiments, substrate <NUM> is the substrate of a peripheral device, so that the structure shown in <FIG> is a non-monolithic 3D memory device in which the peripheral device is disposed below the memory array device.

According to one aspect of the present disclosure, a 3D memory device includes a silicon substrate, a memory stack on the silicon substrate including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer comprising single crystalline silicon above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.

In some embodiments, the memory film does not extend along a top surface and a bottom surface of the channel structure.

The semiconductor plug is an epitaxially-grown silicon plug. The semiconductor plug can be also a deposited polysilicon plug or a silicide plug.

The 3D memory device further includes a substrate above which the memory stack is disposed, and a j oining interface vertically between the substrate and the memory stack. In some embodiments, the 3D memory device further includes a peripheral device above the semiconductor layer. In some embodiments, the 3D memory device further includes a peripheral device vertically between the substrate and the memory stack.

According to another aspect of the present disclosure, , not being part of the invention, a 3D memory device includes a first memory deck including a first plurality of interleaved conductive layers and dielectric layers, an etch stop layer on the first memory deck, a second memory deck including a second plurality of interleaved conductive layers and dielectric layers on the etch stop layer, a channel structure extending vertically through the first and second memory decks and the etch stop layer, and a semiconductor plug above a top surface of the second memory deck and in contact with the channel structure.

In some embodiments, the etch stop layer includes a metal or a semiconductor.

The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug and the semiconductor plug.

In some embodiments, an upper end of the semiconductor channel is in contact with a bottom surface of the semiconductor plug.

In some embodiments, the semiconductor plug is an epitaxially-grown silicon plug. In some embodiments, the semiconductor plug is a deposited polysilicon plug or a silicide plug.

The 3D memory device includes a substrate above which the first memory deck is disposed; and a joining interface vertically between the substrate and the first memory deck. In some embodiments, the 3D memory device includes a peripheral device above the semiconductor plug. In some embodiments, the 3D memory device includes a peripheral device vertically between the substrate and the first memory deck.

According to still another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a front side of a first substrate. A channel hole is formed through the dielectric stack. A memory film and a semiconductor channel are formed along a sidewall and on a bottom surface of the channel hole. A memory stack including interleaved conductive layers and dielectric layers is formed by replacing the sacrificial layers in the dielectric stack with the conductive layers. The first substrate is attached to a second substrate. The front side of the first substrate is toward the second substrate. The first substrate is thinned from a backside of the first substrate to remove parts of the memory film and semiconductor channel on the bottom surface of the channel hole. A semiconductor plug is formed in the thinned first substrate to contact the semiconductor channel.

In some embodiments, prior to attaching, a channel plug is formed in an upper portion of the channel hole to contact the semiconductor channel.

In some embodiments, to form the semiconductor plug, parts of the memory film and semiconductor channel in the thinned first substrate are removed to form a recess. The semiconductor plug can be deposited in the recess or epitaxially grown in the recess from the thinned first substrate.

In some embodiments, to form the dielectric stack, a first dielectric deck including a first plurality of interleaved sacrificial layers and dielectric layers are formed on the frontside of the first substrate, an etch stop layer is formed on the first dielectric deck to cover the first dielectric deck, and a second dielectric deck including a second plurality of interleaved sacrificial layers and dielectric layers is formed on the etch stop layer.

In some embodiments, to form the channel hole, a first opening extending vertically through the first dielectric deck is formed, a second opening extending vertically through the second dielectric deck is formed until being stopped by the etch stop layer, and part of the etch stop layer is removed, such that the first and second openings are connected to form the channel hole.

In some embodiments, to form the channel hole, a gouging of the channel hole is formed through part of the first substrate. In some embodiments, a slit opening is formed through the dielectric stack, and a gouging of the slit opening is formed through part of the first substrate. A depth of the gouging of the channel hole is greater than a depth of the gouging of the slit opening.

In some embodiments, prior to attaching, a peripheral device is formed on the second substrate. In some embodiments, after forming the semiconductor plug, a peripheral device is formed above the thinned first substrate.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional, 3D, memory device ( <NUM>), comprising:
a silicon substrate (<NUM>);
a memory stack (<NUM>) on the silicon substrate comprising interleaved conductive layers (<NUM>) and dielectric layers (<NUM>);
a channel structure ( <NUM>) extending vertically through the memory stack (<NUM>) and comprising:
a channel plug (<NUM>) in a lower portion of the channel structure ( <NUM>);
a memory film (<NUM>) along a sidewall of the channel structure ( <NUM>); and
a semiconductor channel (<NUM>) over the memory film ( <NUM>) and in contact with the channel plug (<NUM>); and
a semiconductor layer (<NUM>) comprising single crystalline silicon above the memory stack (<NUM>) and comprising a semiconductor plug (<NUM>) above and in contact with the semiconductor channel (<NUM>),
wherein a bottom surface of the semiconductor plug (<NUM>) is above a top surface of the memory stack (<NUM>), and a top surface of the semiconductor plug (<NUM>) is flush with a top surface of the semiconductor layer (<NUM>).