Patent Description:
Some CMOS integrated circuits may be made in a partially depleted silicon on insulator (SOI) process. Certain applications such as electronics for satellites, upper rocket stages, space probes, spaceships, and other applications with radiation-hardened requirements impose special demands such as single event upset (SEU) mitigation, or mitigating electronic state upsets by single radiation-induced events, that are not met by circuit architecture for ordinary consumer electronics. SEU in space is caused by energetic particles traversing circuit nodes and depositing charge sufficient to disrupt operation.

Reference may be made to <CIT> which relates to a transistor device with resistive coupling, specifically a CMOS memory cell comprising a PMOS transistor, an NMOS transistor and a gated resistor. Reference may be made to <CIT> which relates to an FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one example, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. The FET is fabricated by forming an oxide mask (e.g., by etching a window in the gate oxide over the device active area); enhancement implanting the substrate through the window (e.g., n-substrate and n-implant for a p-channel FET); enlarging the window width a predetermined distance by etching; and depletion implanting the substrate through the window (p-implant for n-substrate) to a concentration below that of the enhancement implant. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels. This effectively provides an enhancement FET which is in parallel with a depletion FET. The effective channel width of the depletion FET equals the combined width of the two narrow depletion regions and is approximately equal to the difference in width of the two etch-defined windows. The method is applicable to both silicon and metal gate technology, to n-channel and p-channel, and to various combinations of enhancement and/or depletion devices. Reference may be made to <CIT> which relates to a semiconductor device and method of producing semiconductor device. Reference may be made to <CIT> which relates to a logic circuit using a transistor as a load element. Reference may be made to <CIT> which relates to a semiconductor device is characterized in that a part of a channel region between a source region and a drain region facing each other is a depletion type channel region, and the rest is an enhancement type channel region.

Space applications typically call for random access memory (RAM) with high performance and low power requirements, as well as protection against radiation effects. Radiation can cause many undesirable effects in circuit operation. For example, radiation can change the conductance of MOS transistors by changing the threshold voltage (Vt). In space, heavy particles from a single cosmic ray are capable of depositing relatively large amounts of deposited charge on a circuit node. There is a direct relationship between the radiation induced upset rate requirements and the performance requirement of radiation hardened static random access memory (SRAM). Radiation can also generate significant levels of transient voltage and current disturbances on internal nodes, including power and ground.

These internal disturbances can slow circuit performance or even upset circuit operation, e.g., changing the state of a memory cell. For a given node within a memory cell, there exists an amount of deposited charge which the driving transistor and the nodal capacitance cannot absorb without failing to maintain the node in the desired state. Therefore, the radiation induced charge can result in a change in the stored data state. Some specialized circuit architecture technologies have used designs such as back-to-back reverse-biased Schottky resistors as compact high value resistors with an active delay element (ADE) in SRAM cells.

The present invention is defined by the appended claims to which reference should now be made.

This disclosure is directed to methods for fabricating SRAM cells with resistors formed along the sidewall edges of transistors (e.g., ADE transistors) by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation. The implantation is done prior to removal of a Shallow Trench Isolation (STI) barrier such as nitride, enabling the implantation to be self-aligned to the sidewall edge of the silicon island. The height of the silicon islands may determine the width of the implantation. The length of the implantation may be controlled by the gate dimension which may be the most highly controlled dimension in a CMOS process. The depth of the implantation may be controlled by implant variables which may also be highly controlled in a CMOS process. A self-aligned transistor sidewall edge resistor of this disclosure may thus be precisely formed with very compact size, very high resistance (e.g., approximately <NUM>,<NUM> to over a million ohms), and nominal read-write margin. A self-aligned transistor sidewall edge resistor of this disclosure may thus enable a small circuit architecture with reduction or prevention of SEU suitable for specialized applications such as space-based assets, and across a large temperature range and with low supply voltage.

Various examples are described below directed to techniques, methods, systems, and devices for fabricating SRAM cells with resistors formed along the sidewall edges of transistors (e.g., ADE transistors) by self-aligned, angled implantation. A self-aligned SRAM cell sidewall edge resistor ("self-aligned edge resistor") as described herein may minimize effects of turning the transistor off on the resistor value, while enabling the resistance to increase proportionally to source-to-drain bias. In addition, the gate to source/drain capacitance may be reduced by a factor of two or more relative to typical SRAM cells using Schottky elements, since the extra capacitance associated with the gate next to the Schottky elements is eliminated. The dimensions of the self-aligned edge resistor may be controlled by the thickness of the starting top silicon layer on the SOI substrate and the gate masking step, which may be the most highly controlled dimensions in an SOI CMOS process, resulting in the ability to control the resistor value to a high degree of precision relative to previous techniques. The improvement in both control and temperature stability enabled by the self-aligned edge resistor may be sufficient to avoid a requirement to turn on the transistor during the read/write cycle, as is typical in previous techniques, thus further minimizing circuit design complexity.

A self-aligned edge resistor as described herein may be compatible with the minimum-sized transistor available in the technology, and may be compatible with either a p-channel or n-channel transistor, permitting optimization for SRAM cell size. For example, a p-channel option (a p-type edge implant in an n-type well) for implementing a self-aligned edge resistor may maximize usable resistance for a given doping level due to approximately three times lower mobility and may balance n-well and p-well area to maximize density.

The high degree of control for the dimensions of the self-aligned edge resistor may be an advantage over other planar resistor solutions, and the use of an SOI silicon process may provide improved control and temperature effects over polysilicon processes. A self-aligned edge resistor may increase resistance with source-to-drain bias which may enable excellent resistor characteristics even when the transistor part is turned off. A self-aligned edge resistor may also scale down with successively smaller technology generations, and may directly enable smaller SRAM area using smaller values of active power. A self-aligned edge resistor may also enable advantageous implementations in any application requiring a compact resistor with high-precision, high resistance value, including in analog circuits.

<FIG> shows a lateral cross-section view of a CMOS device 10A including a self-aligned edge resistor <NUM> in mid-fabrication in a Shallow Trench Isolation (STI) partially depleted silicon on insulator (SOI) process, in one example. CMOS device 10A may be in a fabrication state as shown in <FIG> after initial process functions performed on an STI stack that includes a bulk silicon substrate <NUM>, a buried oxide layer <NUM> or other type of buried insulator layer (e.g., a buried oxide layer of silicon dioxide) disposed on top of the bulk silicon substrate <NUM>, a silicon device layer <NUM> disposed on top of the buried oxide layer <NUM>, a pad oxide layer <NUM> disposed on top of the silicon device layer <NUM>, an STI nitride barrier layer <NUM> disposed on top of the pad oxide layer <NUM>, and a top oxide layer <NUM> disposed on top of the STI nitride barrier layer <NUM>.

As shown in <FIG>, the layers <NUM>-<NUM> of CMOS device 10A have been modified in CMOS STI process steps of patterning, etching, and initial doping, to eliminate portions of silicon device layer <NUM>, pad oxide layer <NUM>, STI nitride barrier layer <NUM>, and top oxide layer <NUM> to create two silicon islands with first and second semiconductor wells, an n-type well <NUM> ("n-well <NUM>") and a p-type well <NUM> ("p-well <NUM>") topped with STI nitride barrier blocks <NUM>, <NUM> respectively. The patterning and etching steps may include placement of a patterned photoresist mask over CMOS device 10A; etching via sputter, plasma, reactive-ion, or other etching technique; and stripping of the photoresist. N-well <NUM> may be doped with an n-type dopant (e.g., phosphorus) that donates electrons to surrounding silicon, and p-well <NUM> may be doped with a p-type dopant (e.g., boron) that donates electron holes to (i.e., that accepts electrons from) surrounding silicon. P-well <NUM> thus has opposite doping as N-well <NUM>. CMOS device 10A as shown in <FIG> may provide electrical isolation between n-well <NUM> and p-well <NUM>.

In CMOS device 10A as shown in <FIG>, a p-type dopant <NUM> (e.g., boron) is also implanted via a self-aligned, angled implantation into a compact internal sidewall edge area of n-well <NUM>, resulting in a self-aligned edge resistor <NUM> along the compact internal sidewall edge area of n-well <NUM>. The p-type dopant <NUM> of self-aligned edge resistor <NUM> inverts the doping of n-well <NUM> within the volume of self-aligned edge resistor <NUM>. The implantation of p-type dopant <NUM> is self-aligned and angled around the implantation shadow of STI nitride barrier block <NUM>. P-type dopant <NUM> may be implanted past and around the bulk of STI nitride barrier block <NUM> or other barrier, which prevents implantation of p-type dopant into the central body of n-well <NUM>. Self-aligned edge resistor <NUM> is thus self-aligned along a compact, precisely controlled volume of the sidewall edge of n-well <NUM>.

In other examples, any type of barrier layer may be used in place of STI nitride barrier layer <NUM> or STI nitride barrier block <NUM>, and dopant ions may be implanted into the sidewall edge area of n-well <NUM> past the barrier shadow of the barrier layer. Depending on the dopant implant technique, the p-type dopant <NUM> may also be incidentally implanted in the sidewall edge of p-well <NUM>, though in this case, the p-type dopant will superimpose on the same p-type doping type as p-well <NUM> and not create an edge resistor in p-well <NUM>.

<FIG> shows a lateral cross-section view of a CMOS device 10B, corresponding to CMOS device 10A shown in <FIG> after additional process steps to deposit or otherwise form a Shallow Trench Isolation (STI) oxide layer <NUM> or other type of STI insulator layer, to planarize (chemically mechanically polish) STI oxide layer <NUM>, to remove STI nitride barrier layer <NUM> (including STI nitride barrier blocks <NUM>, <NUM>), and to form a device gate layer <NUM>, in one example. CMOS device 10B may thus include a transistor gate in device gate layer <NUM> over n-well <NUM> and p-well <NUM> with a self-aligned edge resistor <NUM> in the n-well <NUM>. Device gate layer <NUM> may be formed by being deposited or thermally grown, in various examples. Self-aligned edge resistor <NUM> may thus connect a source and a drain (not shown in <FIG>) self-aligned to device gate layer <NUM>, in which the source and drain may also be n-type, as further described below. Self-aligned edge resistor <NUM> with p-type doping may thus enable the resistance between the source and drain to increase proportionally to source-to-drain bias.

Buried oxide layer <NUM> and STI oxide layer <NUM> may thus electrically insulate and isolate n-well <NUM> and p-well <NUM> from each other and from other CMOS devices (not shown in <FIG>) formed in the device layer <NUM>, such as other similar n-well and p-well pairs. In other examples, a CMOS device may be formed with an n-type self-aligned edge resistor along a silicon island sidewall edge in p-well <NUM>. The process step of removing STI nitride barrier layer <NUM> (or other barrier layer) may include using a hot phosphoric strip, for example.

In some examples, p-type dopant <NUM> may be deposited via an ion implantation process. In various examples, "implanting" may include any process for embedding, integrating, or depositing p-type dopant <NUM> into n-well <NUM>. In some examples, p-type dopant <NUM> may be deposited into the sidewall edge of n-well <NUM> to form self-aligned edge resistor <NUM> in multiple implant steps with repositioning of a wafer hosting CMOS device 10A/10B (collectively "CMOS device <NUM>") between each implant step. For example, p-type dopant <NUM> may be divided into four equally divided portions to be implanted in four steps, and the wafer may be rotated <NUM> degrees between each implant step, a process known as quad mode implantation. Although this disclosure presents an STI SOI process to create a self-aligned edge resistor, a self-aligned edge resistor may be created using other types of isolation schemes or patterning and etching steps in other example processes.

Thus, the height of the silicon islands formed by n-well <NUM> and p-well <NUM> may determine the width of the implantation of p-type dopant <NUM> in forming self-aligned edge resistor <NUM>. The length of the implantation of p-type dopant <NUM> to form self-aligned edge resistor <NUM> may be controlled by the gate dimension which may be the most highly controlled dimension in a CMOS process. The depth of the implantation of p-type dopant <NUM> to form self-aligned edge resistor <NUM> may be controlled by implant variables which may also be highly controlled in a CMOS process. Self-aligned edge resistor <NUM> may thus be precisely formed with very compact size, very high resistance (e.g., approximately <NUM>,<NUM> to over a million ohms), and nominal read-write margin. Self-aligned edge resistor <NUM> may thus enable a small circuit architecture with reduction or prevention of SEU suitable for specialized applications such as space-based assets, and across a large temperature range and with low supply voltage.

<FIG> shows lateral cross-section views of section views of various examples of CMOS devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> ("CMOS devices <NUM>-<NUM>") with respective self-aligned edge resistors 20A, 20B, 20C, 20D, 20E, 20F (collectively, "self-aligned edge resistors <NUM>") implanted with different implant characteristics, in accordance with example two-dimensional simulations. CMOS devices <NUM>-<NUM> also have respective n-wells 36A, 36B, 36C, 36D, 36E, 36F (collectively, "n-wells <NUM>") separated from respective self-aligned edge resistors 20A, 20B, 20C, 20D, 20E, 20F by respective inversion boundaries 21A, 21B, 21C, 21D, 21E, 21F. <FIG> shows sections of each of CMOS devices <NUM>-<NUM> with n-well <NUM> and self-aligned edge resistor <NUM> isolated by buried oxide layer <NUM> and STI oxide layer <NUM>, and with gate layer <NUM> disposed above. Each of the six section views in <FIG> is a cross-sectional view of half of a gate, with a perspective in a direction between the source and the drain. In each case, self-aligned edge resistor <NUM> may be considered separate from the surrounding n-well <NUM> along a metallurgical junction where the n-type doping concentration of n-well <NUM> and the p-type doping concentration of self-aligned edge resistor <NUM> are balanced.

<FIG> further shows how the different implant variables, in particular, implantation energies and doses in the examples of <FIG>, may determine the size, form, and doping concentration of the self-aligned edge resistors <NUM> in process simulations. In particular, CMOS device <NUM> shows a self-aligned edge resistor 20B with a higher implantation energy than self-aligned edge resistor 20A of CMOS device <NUM>, and CMOS device <NUM> shows a self-aligned edge resistor 20C with a higher implantation energy than self-aligned edge resistor 20B of CMOS device <NUM>. In the particular examples shown, CMOS devices <NUM>-<NUM> show implantation energies of <NUM>, <NUM>, and <NUM> kilo-electronvolts (keV), respectively. In other examples, the energy of implantation may be <NUM> keV or lower, or <NUM> keV or higher, depending on specific characteristics of a particular CMOS device, to enable sufficient current to flow through self-aligned edge resistor 20B for it to function as a transistor sidewall edge resistor.

The resistance of self-aligned edge resistor 20B may thus form a conductive path between the source and the drain through a gate formed by CMOS device <NUM>. The resistance of self-aligned edge resistor 20B may be sufficient to enable a current of a selected value to flow through the resistor when a gate bias of the gate is turned on, and a current of a lower value to flow through the resistor when the gate bias of the gate is turned off. The dopant may be implanted at a selected implantation dosage and a selected energy of implantation to provide the resistance sufficient to enable the current to flow through the resistor in this way.

CMOS devices <NUM>-<NUM> show the same implantation energies as CMOS devices <NUM>-<NUM>, respectively, but with a higher implantation dosage. In particular, CMOS devices <NUM>-<NUM> are all shown with an implantation dosage of <NUM>×<NUM><NUM> ions per square centimeter, while CMOS devices <NUM>-<NUM> are all shown with an implantation dosage of <NUM>×<NUM><NUM> ions per square centimeter. In other examples, the selected implantation dosage may be <NUM>×<NUM><NUM> ions per square centimeter or lower, or <NUM>×<NUM><NUM> ions per square centimeter or higher, depending on the characteristics of the specific CMOS device to enable sufficient current to flow through self-aligned edge resistor 20B. The resistance value of self-aligned edge resistor <NUM> may be determined by the characteristics of the implant, such that the higher the implant dose, the lower the resistance.

<FIG> shows an angled longitudinal/azimuthal cross-section view and cross-sectional views of another example CMOS device, labeled 111A in an angled longitudinal/azimuthal cross-section view (perpendicular to the views of <FIG>), and 111B in a lateral (as in <FIG>) cross-section view, respectively (collectively, "CMOS device <NUM>"), with a self-aligned edge resistor <NUM> in an example three-dimensional simulation. View 111B is a lateral cross-section along vertical reference line 112A in view 111A. View 111A shows a lateral distribution of self-aligned edge resistor <NUM> relative to n-well <NUM>, in one example. Self-aligned edge resistor <NUM> forms a p-type channel with a width of <NUM> micrometers (microns) in this example (and may have a larger or smaller width in other examples). Views 111A and 111B both indicate doping concentrations with dashed lines in approximately half-order of magnitude boundaries, such as from - <NUM> * <NUM><NUM> at right to + <NUM> * <NUM><NUM> at left in view 111B. CMOS device <NUM> in longitudinal/azimuthal view 111A shows a cross-section of an n-well <NUM> proximate an edge thereof and proximate the junction with self-aligned edge resistor <NUM>. CMOS device in perspective view 111A also shows STI oxide layer <NUM>, and source and drain implants <NUM> and <NUM>, respectively, on the top of the CMOS device, on either side of gate layer <NUM>; and bulk silicon substrate <NUM>.

View 111B of CMOS device <NUM> shows lateral distribution of self-aligned edge resistor <NUM> relative to n-well <NUM> in silicon device layer <NUM>, with gate layer <NUM> disposed above silicon device layer <NUM>. View 111B also shows depletion region boundaries <NUM> and <NUM> within self-aligned edge resistor <NUM> and n-well <NUM>, respectively, on either side of the inversion boundary <NUM> that defines the boundary between p-type self-aligned edge resistor <NUM> and n-well <NUM>. Depletion region boundaries <NUM> and <NUM> as shown in view 111B are the edges of a depletion region between the n-type material in n-well <NUM> and the p-type material in self-aligned edge resistor <NUM> when a drain voltage Vd of drain implant <NUM> and source voltage Vs of source implant <NUM> are applied at -<NUM> volts, and body voltage Vbody and gate voltage Vgate are zero. The major part of the resistance of self-aligned edge resistor <NUM> in this example is due to the core part of self-aligned edge resistor <NUM> to the right of depletion region boundary <NUM> as shown in view 111B, which has a significantly higher ratio of p-type to n-type doping than within the depletion region portion of self-aligned edge resistor <NUM> between depletion region boundary <NUM> and inversion boundary <NUM>.

<FIG> shows a graph of source to drain conductivity characteristics of self-aligned edge resistor <NUM> of <FIG> in a drain voltage sweep followed by a source voltage sweep, via drain implant <NUM> and source implant <NUM> on opposing sides of the transistor gate as shown in the angled longitudinal/azimuthal cross-section view 111A in <FIG>, in one example. The left y axis in <FIG> shows current from zero to <NUM> microamps, the lower x axis shows the source voltage from -<NUM> to <NUM> volts going from left to right, and the upper x axis shows the drain voltage from -<NUM> to <NUM> volts going from right to left. Arc <NUM> shows a drain voltage sweep as drain voltage goes from <NUM> to -<NUM> and current rises from <NUM> to <NUM> microamps, and arc <NUM> shows a subsequent source voltage sweep as source voltage goes from <NUM> to -<NUM> and current drops back from <NUM> microamps to <NUM>, while body voltage and gate voltage are <NUM>.

The graph of <FIG> shows that self-aligned edge resistor <NUM> remains conductive under all conditions, and that the source-drain voltage induces a sufficient depletion region to enable conduction through self-aligned edge resistor <NUM>. As CMOS device <NUM> is turned on and off, it can be driven into effective deep depletion equivalent to having a body tie bias on the device. CMOS device <NUM> is prevented from being turned off if a gate bias voltage or a body bias voltage appears. The effective resistance of self-aligned edge resistor <NUM> may vary proportionally to the source-to-drain bias voltage, and may be approximately in the range of <NUM>,<NUM> to ten million ohms. The effective resistance of self-aligned edge resistor <NUM> when drain-to-source bias voltage is near <NUM> may vary from about <NUM>,<NUM> to <NUM>,<NUM> ohms as a function of body bias, in this example. <NUM>,<NUM> ohms may occur in a worst case transient resistance in this example when the transistor is turned off and the body goes into deep depletion. In another example, the drain and source voltage may go to -<NUM> volts instead of -<NUM>, and the worst case transient resistance effects may be smaller.

<FIG> shows graphs <NUM>, <NUM>, <NUM>, <NUM> of examples of current flowing through self-aligned edge resistor <NUM> as a function of drain voltage Vdrain in on and off gate bias conditions in three different example CMOS devices, in accordance with experimental results of measurements in example physical implementations of CMOS devices. Graphs <NUM> and <NUM> show current over voltage, in logarithmic and direct scales, respectively, in each of the three CMOS devices with a doping implantation density of <NUM>×<NUM><NUM> ions per square centimeter, and graphs <NUM> and <NUM> show current over voltage, also in logarithmic and direct scales, respectively, in each of the three CMOS devices with a doping implantation density of <NUM>×<NUM><NUM> ions per square centimeter. Graphs <NUM>-<NUM> all show current in microamps through self-aligned edge resistor <NUM> along the y axis, and applied drain voltage in volts along the x axis. Graphs <NUM> and <NUM> are in a logarithmic scale, while graphs <NUM> and <NUM> show a detailed section of interest of graphs <NUM> and <NUM>, respectively, in a linear scale.

The three different CMOS devices are a high voltage (HV), low voltage (LV), and super low voltage (SLV) versions, and the drain voltage Vdrain in each case rises from <NUM> to <NUM> volts. The HV version CMOS device may have a <NUM> volt transistor, the LV version CMOS device may have a <NUM> volt transistor, and the SLV version CMOS device may have a <NUM> volt transistor, in these examples.

In each example, self-aligned edge resistor <NUM> has a p-type channel with a width of <NUM> microns, as in the example of <FIG> and <FIG> as described above. The current through self-aligned edge resistor <NUM> varies as voltage over resistance of self-aligned edge resistor <NUM>, where resistance varies proportionally to drain voltage, and is a function of the halo implantation dose of n-well <NUM> and the edge implantation dose of self-aligned edge resistor <NUM>, as shown in <FIG>. Self-aligned edge resistor <NUM> may achieve a resistance in the range of approximately <NUM>,<NUM> to one million ohms, in these examples. Self-aligned edge resistor <NUM> may have a p-type doping implantation level tuned to a specified resistance with respect to the voltage of the particular version of the CMOS device, with a relatively low doping level and relatively high resistance for the SLV version, a higher doping level and lower resistance for the LV version, and a still higher doping level and still lower resistance for the HV version. The implantation level of self-aligned edge resistor <NUM> may thus be adjusted relative to the voltage of the CMOS device version to target a specified resistance over the applicable voltage range. While this example is discussed in terms of forming self-aligned edge resistor <NUM> with a p-type dopant implanted into the sidewall edge of an n-type well, other examples may be implemented with a self-aligned edge resistor formed of an n-type doping implantation into an edge of a p-type well.

In graphs <NUM>-<NUM>, the higher values of current occur in the drain voltage Vdrain on condition, when the drain voltage in the CMOS device is applied or turned on. In this condition, the current shorts out self-aligned edge resistor <NUM>. When the drain voltage is turned off, the resistance remains, and at a high value. Self-aligned edge resistor <NUM> thus enables voltage still to be applied to the body of the CMOS device when the drain voltage of the CMOS device is turned off. Self-aligned edge resistor <NUM> may thus also prevent floating body effects in the CMOS device and mitigate the risk of an SEU in an SRAM cell that includes the CMOS device.

<FIG> depicts a flowchart for an example process <NUM> for forming a CMOS device with a self-aligned edge resistor, in accordance with illustrative aspects of this disclosure. In this example, process <NUM> includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type (e.g., implanting a p-type dopant <NUM> such as boron into a sidewall edge of n-type doped semiconductor well <NUM> covered by the barrier of STI nitride barrier block <NUM> of STI nitride barrier layer <NUM> to form self-aligned edge resistor <NUM>, wherein n-well <NUM> is disposed on the insulator of buried oxide layer <NUM>, and wherein p-type dopant <NUM> is of opposite doping type to n-type well <NUM>, as described above) (<NUM>). Process <NUM> further includes forming a second insulator adjacent to the resistor (e.g., depositing an STI oxide layer <NUM> over CMOS device <NUM>, including adjacent to self-aligned edge resistor <NUM>) (<NUM>). Process <NUM> further includes removing the barrier (e.g., removing STI nitride barrier block <NUM>) (<NUM>). Process <NUM> further includes forming a gate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor (e.g., depositing or thermally growing gate layer <NUM> on CMOS device <NUM> including n-well <NUM>) (<NUM>).

Claim 1:
A method (<NUM>) comprising:
implanting (<NUM>, <NUM>) a dopant (<NUM>) into a doped semiconductor well (<NUM>) covered by a barrier (<NUM>, <NUM>, <NUM>, <NUM>), wherein the doped semiconductor well is disposed on a buried first insulator (<NUM>) and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a first semiconductor well disposed on a first insulator, the first semiconductor well having a first doping type, and forming a resistor (<NUM>) on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type;
forming (<NUM>) a second insulator (<NUM>) adjacent to the first semiconductor well and to the resistor;
removing (<NUM>) the barrier;
forming (<NUM>) a gate layer (<NUM>) disposed on the second insulator and over the doped semiconductor well, thereby forming a gate (<NUM>) disposed over the first semiconductor well and the resistor; and
forming a source and a drain such that they are on opposing sides of the gate layer,
wherein:
the resistor is disposed on an edge of the doped semiconductor well, adjacent to the second insulator;
the resistor forms a conductive path between the source and the drain; and
the dopant is implanted into only one edge of the doped semiconductor well by a self-aligned angled implantation, thereby forming the resistor as a self-aligned transistor sidewall edge resistor (<NUM>) on only one edge of the doped semiconductor well.