Patent Description:
The front-end of an ultrasound system is that part of the system which communicates with an ultrasound probe, controlling the transmission of ultrasound from the probe transducer and receiving and initially processing the returning echo signals from the transducer. The front-end circuitry also controls related processing such as TGC amplification of the echo signals, digitization and at least some portion of the beamforming process. It is desirable that most of this circuitry be fabricated in integrated circuit (IC) form to reduce system size and weight and desirably cost. But today's ultrasound system use probes with multi-element array transducers to steer and focus beams electronically, eliminating mechanical parts in the probe. A conventional 1D (one dimensional) array size is <NUM> elements, although probes with <NUM> and <NUM> elements are in use, and 2D probes for 3D imaging have many thousands of transducer elements. For 2D array probes, microbeamformers are a necessity to enable use of an efficiently sized cable, although the front-end circuitry is still generally used for probe control and final beamformation.

It is also desirable for the front-end circuitry to provide a full range of capabilities, able to operate probes requiring pulse transmission and those using shaped waveform transmission, as well as those with multiline capability. It is further desirable that digitization be done prior to beamformation so that a digital beamformer can be used for all imaging applications. These requirements impose challenges for the number and layout of integrated circuit components, as they result in an increasing pin count for the integrated circuit components. These requirements would be lessened for probes with a fewer number of elements and those that use multiplexing, but multiplexing generally reduces performance and so the need to efficiently operate a <NUM>-element array probe is minimally a desired requirement.

In "<NPL>), it is disclosed a novel US system based on high-level commercial integrated circuits which is characterized by its high programmability and wide access to raw data.

Technical publication "<NPL>), discusses how low-voltage semiconductor integrated circuit technologies make it possible to manufacture ultrasound transceivers chips with high-gain and low-noise performance.

In "<NPL>), it is described a noninvasive ultrasonic thickness measurement device that determines the gingiva thickness by using A-mode ultrasonic method.

Finally, "<NPL>), relates to a compact and cost-effective method for generating simultaneous arbitrary waveforms needed for medical ultrasound array probes over several channels using an FPGA.

It is an object of the present invention to provide an integrated circuit front-end for an ultrasound system which provides premium performance for a <NUM>-element array transducer probe with IC packages having a reduced pin count for efficient configuration, packaging and p. board layout, and with consideration of the various types of fabrication required for ICs of different voltages and capabilities.

This object is solved by the ultrasound system for multi-mode imaging of Claim <NUM>.

In accordance with the principles of the present invention, front-end circuitry for an ultrasound system is described which comprises a beamformer FPGA integrated circuit, transmit ICs with both pulse transmitters and linear waveform transmitters, transmit control and receiver ICs, and analog-to-digital converter (ADC) ICs. Only the transmit ICs require high voltages, and the transmit/receive switches are integrated in the transmit ICs, isolating the receiver ICs from high voltages. The transmitters can be trimmed to adjust the pulse slew rates, enabling the transmission of pulses with low harmonic frequency content and thus better harmonic images. Waveform data for both the linear and pulser transmitters is stored in the transmit control and receiver ICs, saving pins on the FPGA, which is the conventional source of this data. The ADCs couple digital echo data to the FPGA for beamforming over serial bus lines, saving additional FPGA pins over a conventional parallel data arrangement. The inclusion of both pulser and linear waveform transmit capabilities in the transmit ICs enables the use of both types of transmitters in the formation of a multi-mode image, such as use of the pulsers for Doppler beams and linear transmitters for B mode beams in the formation of a colorflow image.

Referring first to <FIG>, the ICs of an ultrasound system front-end constructed in accordance with the principles of the present invention are shown in block diagram form. A beamformer FPGA (field programmable gate array) <NUM> communicates with the system backend, receiving commands for a transmit-receive imaging sequence for a probe with an array transducer and sending back digitally beamformed echo data for image formation in the backend. The FPGA <NUM> is configured to perform digital beamforming of received echo signals as is known in the art. Beamforming comprises receiving echo signals received by elements of a transducer array and respectively delaying the echoes to bring them into time and phase coherency, then summing them. In essence, echoes received by different elements of the array transducer from a common point in an image field are combined to produce a coherent beamformed echo signal. Analog beamformers use delay lines to delay echo signals for combining, but a digital beamformer can use a variety of delay techniques, including the relative times of sampling (digitization) of echo signals, the time to clock a sequence of digital echo signal samples through a shift register or the write-to-read time of echoes stored in a random access memory. These techniques are described in <CIT>. ), for instance. Representative digital beamformers which may be implemented in FPGA <NUM> are shown in <CIT>. ) and <CIT>. ), for example.

The echo signals which are beamformed by the FPGA <NUM> are produced by ADCs <NUM> and stored in DRAM memory. The FPGA then extracts the data from memory as needed and beamforms the data into digital coherent echo signals, which are then communicated to the ultrasound system backend for further processing and image formation. The DRAM memory may comprise separate memory ICs which are electrically coupled to the FPGA <NUM>. Preferably, the DRAM memory is integral to the same IC package as the FPGA. Such an integrated IC devices can be fabricated as an electronic package in which multiple integrated circuits are packaged on a unifying substrate, facilitating their use as a single component which includes the functionality and capability of multiple integrated circuit devices in a much smaller volume. Another packaging approach is to vertically stack the FPGA chip and the memory chip(s) on a p. board, which minimizes the packaging size (i.e., the length and width) and the footprint occupied by the chips on the circuit board. This approach, while achieving the objective of board size reduction, will not achieve one of the objects of the present invention, which is to reduce the number of pins required for the IC package, as external package pins will still be needed for the data bus, clock signal, and control lines (e.g., address lines) between the FPGA and memory ICs. A preferred implementation of the present invention is to package both the FPGA device and DRAM chips in the same IC package so that the connections between them can be made internal to the package, reducing and freeing up external pins on the FPGA package for other uses, such as connections to other ICs of the front-end.

In response to the commands for a particular transmit-receive imaging sequence, the FPGA communicates transmit and receive control data (TxRx Control Data) to transmit control and receiver ICs <NUM>. In a preferred implementation for a <NUM>-element transducer array, each transmit control and receiver IC <NUM> receives control data for operation of thirty-two elements of the transducer array. Thus, four transmit control and receiver ICs <NUM> are required for operation of a <NUM>-element array. Each transmit control and receiver IC <NUM> responds by producing the transmit data for thirty-two elements of the array. Each IC <NUM> also comprises thirty-two receive signal paths including preamplifiers and TCG control for the same thirty-two elements. The transmit control and receiver ICs produce both pulse control signals and linear waveform signals for each transducer element. The transmit control and receiver ICs output a linear waveform signal for a linear transmitter and transmit control data for a pulser for each transducer element which is coupled to linear and pulser transmitter ICs <NUM>. Also coupled to the linear and pulser transmitter ICs are control signals to control transmitter parameters such as transmitter gain and enable signals. Signal lines are also connected between the transmit control and receiver ICs <NUM> and the linear and pulser transmitter ICs <NUM> to couple received echo signals back to the TGC controlled preamplifiers of the receive signal path in the ICs <NUM>.

In a preferred implementation each linear and pulser transmitter IC <NUM> comprises a pulser and linear transmitter and a transmit/receive (T/R) switch for two transducer elements <NUM>. Thus, sixtyfour linear and pulser transmitter ICs <NUM> are needed for a <NUM>-element transducer array. During the receive portion of a transmit-receive cycle the T/R switches are closed to couple received signals back to the receive signal paths of the transmit control and receiver ICs. During the transmit portion of a transmit-receive cycle the T/R switches are opened to isolate the receive signal path from transmit high voltages. Thus, high voltages are needed only for the linear and pulser transmitter ICs <NUM>, and the transmit control and receiver ICs are entirely low voltage ICs as they are completely isolated from the high voltages of transmission and have no high voltage requirement.

Echo signals received from the linear and pulser transmitter ICs <NUM> are amplified with TGC gain control by preamplifiers in the receive signal paths of the transmit control and receiver ICs <NUM> and coupled to ADC ICs <NUM>. In a preferred implementation for a <NUM>-element transducer array, each ADC IC <NUM> comprises eight ADCs for the echo signals received from eight elements of the array. Thus, each transmit control and receiver IC <NUM> is coupled to four ADC ICs <NUM>. The digitized echo signals of eight transducer elements are coupled back to the FPGA <NUM> from each ADC IC <NUM> by time multiplexing over a serial receive data line (Serial Rx Data), where the digitized echo signal data is stored in the DRAM memory for use by the FPGA in beamformation. By use of serial data lines instead of parallel data lines, the number of pins required on the FPGA IC is reduced, and by time multiplexing the digitized echo signals of eight ADCs onto the same serial data line for each ADC IC, the number of pins required on the FPGA is further reduced; only sixteen serial data lines are required for the preferred implementation for a <NUM>-element array. In the preferred implementation each serial data line is implemented as a differential pair of conductors operating in accordance with the JESD204B serial data bus format.

<FIG> illustrates the circuitry of a linear and pulser transmitter IC <NUM> in schematic detail. Since each IC <NUM> in the preferred implementation operates two transducer elements <NUM>, the circuitry of <FIG> is replicated twice in an IC for two transducer elements. The boundaries of the IC package are delineated by dashed lines, with the small boxes on the dashed lines indicating external connection pins of the IC package. Digital data Dig. In defines the characteristics of high voltage drive pulses produced by a pulser <NUM> for pulse transmission by a transducer element <NUM>, and is applied with timing appropriate for the steering and focusing of the transmit beam to which signals from a particular element contribute. In data is interpreted by pulse logic <NUM> to control the pulser <NUM> for production of a two-level pulse (e.g., zero and one), a three-level pulse, or a seven-level pulse. In data comprises one bit (zero or one) for a two-level pulse, two bits for a three-level pulse, and three bits for a seven-level pulse. The pulser <NUM> is powered by high voltages +HVP and -HVP applied to pins of the IC <NUM> (not shown). An analog waveform DAC In is coupled to a pin of the IC <NUM> for transmission of a linear waveform such as a shaped sine wave to drive transducer element <NUM>, again with timing appropriate for the transmit beam to which the particular element contributes. The low voltage DAC In waveform is amplified by an amplifier <NUM> with selectable gain and produces a waveform which is further amplified by a high power linear transmitter <NUM> which drives the transducer element. The linear transmitter <NUM> is powered by high voltages +HVL and - HVL applied to pins of the IC <NUM> (not shown). The outputs of both the pulser <NUM> and the linear transmitter <NUM> are coupled to the same output pin of the IC <NUM>, to which the transducer element <NUM> is connected. Transmit control data (Tx Control Data) received prior to a transmission period by transmit control logic <NUM> determines which transmitter is to be used, the pulser <NUM> or the linear transmitter <NUM>, by generation of enable signals Pen and Len for each transmitter. The pulser enable signal Pen is coupled to the pulse logic <NUM> and the linear transmitter enable signal Len is coupled to the amplifier <NUM>. A gain control signal generated by the transmit control logic is also applied to the amplifier <NUM> for gain determination.

A T/R switch <NUM> is also integrated on IC <NUM> for each transducer element <NUM>. The preferred T/R switch contains one single pole, single throw switch TR<NUM> in series with the receive signal path from transducer element <NUM> and another single pole, single throw switch TR<NUM> shunting the signal path to ground. The switches are operated in complementary fashion by the TR control signal generated by the transmit control logic <NUM>. During transmission, when either the high voltage pulser or the linear transmitter is driving the transducer element <NUM>, the TR<NUM> switch is open and the TR<NUM> switch is closed to isolate the receive signal path of the transmit control and receiver IC <NUM> from high voltages. During echo reception, when the transmitters are disabled and echo signals are received by the transducer element <NUM>, the TR<NUM> switch is closed and the TR<NUM> switch is open to couple the received echo signals to the receive signal path by way of output line RcvOut.

The pulser <NUM> in a preferred implementation is commonly used for harmonic signal operation, in which harmonic frequency signals developed in the body either by tissue or contrast agents are stimulated by pulse transmission and received by the transducer array for imaging or other diagnosis. In order for the harmonic signals received by the transducer array to be as clean as possible, it is desirable that the transmitted pulses themselves contain as little high frequency content as possible, which would otherwise result in reception of signals in the harmonic frequency band which originate from the ultrasound system and not the body. To reduce harmonic frequency generation by the ultrasound system it is desirable for the transmitted pulses to be as symmetric as possible in their rise and fall times, their slew rates from one pulse level to another. Semiconductor processing, while precise for most applications, can nonetheless result in current and/or impedance differences between positive drive and negative drive MOSFETs <NUM>, <NUM> of the complementary drive pulser configuration. If the positive drive transistor <NUM> is more conductive for a given drive signal than the negative drive transistor <NUM>, for instance, transmit pulses will have a faster rise time (greater slew rate) at rising edges than the rate of decline at falling edges, for instance. The same effect can occur with falling edges. In accordance with a further aspect of the present invention, the drive transistors of the pulser <NUM> can be controllably trimmed to equalize the rise and fall characteristics of transmitted pulses. One way to do this is indicated at <NUM>, which is to controllably change the size of a drive transistor. As indicated in the drawing, the drive transistors can be fabricated with parallel switchable channel paths between the source and drain electrodes of a MOSFET, and also for the gate electrode. As additional parallel semiconductor paths are switched in, the conductivity of the transistor is increased as the effective size of the transistor increases. When the size of the positive drive transistor <NUM> is increased, for instance, the rise time toward the positive voltage rail is increased, and when the size is reduced the rise time is slowed down. The sizes of the drive transistors can be controllably adjusted during manufacture or testing of the ultrasound system and test pulses applied and measured until symmetrically balanced pulses with minimal harmonic frequency content are produced. The slew rate characteristics could also be adjusted in the field, if desired. For instance, the electrical load of the transducer element seen by the pulser can also affect the rise and fall characteristics of applied drive pulses. A newly developed probe may have a transducer array which requires different trimming of the pulser transistors to achieve the best harmonic performance. When the new probe is connected to the system for a scanning procedure, data in the probe EPROM can be read by the FPGA and coupled to the linear and pulser transmitter IC <NUM> to reset the trimming of the pulser transistors for better harmonic performance by the new probe.

Another way to trim the pulser transistors for balanced slew rate performance is by controllable adjustment of the first stage transistors used to drive the high voltage MOSFETs. A complementary pair of power transistors such as MOSFETS <NUM> and <NUM> in <FIG> are generally driven by a pair of low power drive transistors coupled to their gate electrodes, which are generally operated as a balanced pair. In accordance with the present invention, such drive transistors have bias currents which can be trimmed using switchable parallel resistors <NUM> coupled to the transistor voltage supply as shown in <FIG>. By adding more resistors in parallel between the supply voltage and an electrode of a drive transistor, the transistor operation is altered so that it will become more conductive, or more conductive earlier in response to a drive signal. Thus, by biasing the positive supply drive transistor for earlier or greater conductivity, the rise time of the positive power transistor <NUM> is increased corresponding, increasing the slew rate of a positive-going transmit pulse. By trimming the bias supplies of one or both of the drive transistors for the power transistors <NUM>, <NUM> in this manner, the performance of the pulser can be adjusted to exhibit substantially identical rise times for both positive-going and negative-going pulses and pulse edges.

<FIG> is a block diagram and schematic drawing of the circuitry of one of the transmit control and receiver ICs <NUM> of <FIG>. Each IC <NUM> of <FIG> contains the components illustrated in <FIG> for thirty-two transducer elements, and so the circuitry of <FIG> is replicated thirty-two times in each IC for a <NUM>-element array transducer. The transmit circuitry shown at the top of the drawing comprises a transmit data memory which is an n-byte digital memory <NUM> containing data sequences for a plurality of different pulser pulse sequences and linear transmit waveforms. Transmit and receive control logic <NUM> receives control data (TxRx Control Data, <FIG>) from the FPGA <NUM> which defines the transmit pulses and waveforms and the TGC control characteristic for the transmit components and receive signal path of the front-end circuitry. In response to this information an address register <NUM> addresses the memory locations for the n bytes of the appropriate transmit pulse or waveform stored in the memory <NUM>. The sequence of pulse or waveform data is read out of memory <NUM> and applied to pulser logic <NUM> and to digital-to-analog converter (DAC) <NUM>. The pulser logic <NUM> responds to this data by outputting a sequence of digital data bytes of the appropriate bit length for the desired pulser waveform, which is applied to the pulser input of a linear and pulser transmitter IC <NUM> (Dig. This data sequence, generally of a length of hundreds of bytes, depending on the clock frequency and desired transmit pulse resolution, causes the pulser to transmit the desired pulse shape and duration. When data for a linear waveform is read out of the memory <NUM>, the sequence of data bytes is converted into a linearly varying analog waveform by the DAC <NUM>, which is applied to the linear transmitter (DAC In). The transmit and receive control logic <NUM> also outputs control data for control of the other parameters of a transmit pulse or waveform (Tx Control Data) including the enable bits for control of pulser or linear transmitter operation and bits for control of the T/R switch <NUM>.

The receive signal path for echo signals received by a transducer element <NUM> and coupled by a T/R switch <NUM> is shown at the bottom of <FIG>. The echo signals (RcvOut) are applied to a first preamplifier <NUM> with a gain controlling TGC<NUM> resistor which is switched into circuit by a switch <NUM> at a time determined by the control data received by the transmit and receive control logic <NUM>. The output of preamplifier <NUM> is coupled to a second gain stage <NUM>, which includes a second switchable feedback resistor TGC<NUM> for a second stage of TGC control. The TGC<NUM> resistor is switched into circuit by a switch <NUM>, also controlled by a signal generated by the transmit and receive control logic <NUM>. This is followed by a third preamplifier <NUM>. The amplified echo signals at the output of preamplifier <NUM> are coupled to an ADC IC <NUM> for digitization in the form of a complementary pair, RcvOut P produced by a further inverting preamplifier <NUM>, and RcvOut N produced by preamplifier <NUM>. After digitization by an ADC of one of IC chips <NUM>, the digitized echo data is coupled to the FPGA <NUM> for beamformation by means of a serial data bus (Serial Rx Data). It is seen that the components and signals of the transmit control and receiver ICs <NUM> are all low voltage components and signals, enabling these ICs to be fabricated using an efficient low voltage CMOS process.

A method for operating the front-end IC circuitry of the previous drawings for an ultrasound transmit-receive scanning sequence is illustrated in <FIG>. At the outset in step <NUM>, information defining the scanning sequence is sent from the backend of the ultrasound system to the FPGA <NUM>. In step <NUM> the FPGA <NUM> sends transmit and receive control data to the transmit control and receiver ICs <NUM>. The ICs <NUM> in turn send transmit control data to the linear and pulser transmitter ICs <NUM> in step <NUM>, and also condition the receive signal path for the desired TGC operation in step <NUM>. The transmit waveforms are produced in the transmit control and receiver ICs <NUM> and applied to the enabled pulser or linear transmitter of a linear and pulser transmitter IC, causing the transmission of the desired pulse or linear waveform by the transducer elements in step <NUM>, and the resultant reception of echo signals. The echo signals are coupled through T/R switches <NUM> to the receive signal paths of the transmit control and receiver ICs <NUM>, where TGC amplification is applied. The amplified echo signals are then applied to the ADC ICs, which convert them to digital signal samples in step <NUM>. The digital echo signal samples are then sent to the FPGA <NUM> in step <NUM> over the serial data lines for beamformation in the FPGA.

The scanning sequence of <FIG> can be further defined to produce a multi-mode image, such as a colorflow image, using both pulsers and linear transmitters to acquire the different modes of echo signals as shown in <FIG>. For acquisition of echo signals for a colorflow image, operation begins with the communication of the desired colorflow scanning sequence from the backend of the ultrasound system to FPGA <NUM> in step <NUM>. In step <NUM> control data for transmission and reception of Doppler beams for Doppler (motion) echo data and B mode beams for B mode (structural) echo data is sent to the transmit control and receiver ICs <NUM> (TxRx Control Data). In step <NUM> transmit control data for the pulsers and linear amplifiers is sent to the linear and pulser transmitter ICs <NUM> (Tx Control Data). The receive control data is used to control the TGC characteristic applied to received echoes in the receive signal path of the transmit control and receiver ICs. In step <NUM>, digital data from the n-byte memories <NUM> is processed by the pulser logic of ICs <NUM> and coupled to the inputs of the pulsers <NUM> in the ICs <NUM> for transmission of a pulsed Doppler beam by the array elements <NUM>. The echoes received in response to a Doppler beam are coupled from the transducer elements by way of the T/R switches <NUM> of ICs <NUM> to the TGC preamplifiers of the receive signal paths of ICs <NUM>. The amplified echo signals (RcvOut P,N) are coupled to the ADC ICs <NUM> where they are converted to digital signal samples in step <NUM>. The digital Doppler echo signal samples are sent (Serial Rx Data) to the FPGA DRAM memory for temporary storage in step <NUM> in preparation for beamforming by the FPGA into coherent echo signals received along each Doppler scanline.

For B mode scanlines a sequence of digital waveform bytes is coupled to DACs <NUM> from the n-byte memories, which produce linearly varying waveforms for B mode transmission. The waveforms (DAC In) are applied at appropriate times to the inputs of the amplifiers <NUM> for the linear transmitters <NUM> of ICs <NUM>, which drive the elements of the transducer array to transmit a B mode waveform beam in step <NUM>. In response to the B mode beam, echoes are returned from structural (e.g., tissue) matter of the subject and received by the transducer elements <NUM>. The received B mode echo signals are coupled by way of T/R switches <NUM> to the receive signal paths of the ICs <NUM> with the same or different TGC gain characteristic as was used for the Doppler echo signals. The amplified B mode echoes are coupled to the ADC ICs <NUM> (RcvOut P,N) where they are converted to digital B mode echo signal samples in step <NUM> and forwarded to the DRAM memory of FPGA <NUM> (Serial Rx Data) for temporary storage and beamformation.

Since it is desired to acquire the Doppler and B mode echo signals for a given scanline at essentially the same moment in time, the transmission of Doppler pulses and B mode waveforms and resultant echo reception is generally alternated across the array. Since Doppler processing requires an ensemble of echo signals acquired over time from each point in the image field, the number of Doppler pulses exceeds the number of B mode pulses, with multiple Doppler beams being transmitted at different times along each scanline direction. The timing and degree of Doppler and B mode interleave, indicated by the arrows on the right side of <FIG>, is determined as is known in the art in consideration of the range of tissue motion or blood flow velocities to be detected (I. e, Nyquist sampling rule,) with Doppler echoes of an ensemble being acquired over greater time intervals for measurement of lower velocities. The number of Doppler transmissions used to acquire a Doppler ensemble is dependent on considerations such as the desired accuracy of the flow and motion information.

An ultrasound system which utilizes the front-end ICs described above for the production of ultrasound images, including colorflow images, is shown in block diagram form in <FIG>. A probe <NUM> having, in this example, a transducer array <NUM> of <NUM> elements is coupled to the IC front end shown in <FIG>, in particular the transducer element pins of the linear and pulser transmitter ICs <NUM>. The beamformer of the FPGA produces scanlines of coherent echo signals in response to pulse and waveform beams transmitted across the image field. In some implementations a second system beamformer <NUM> may be used to perform some of or specialized beamforming, such as the completion of beamformation from partial beamformed sums produced by the FPGA beamformer. However, in most instances the FPGA beamformer will be sufficient for all beamforming, even for those requiring complex computations such as multiline beamforming. This is particularly the case when functions commonly performed in an FPGA such as the storage of pulse and waveform characteristics and their processing is offloaded to other components, as it is in the exemplary front-end configuration of <FIG>. In the implementation of <FIG> the pulse and waveform data is stored in the n-byte memories <NUM> of the transmit control and receiver ICs, where they not only eliminate this functionality from the FPGA but also bring it closer to the transmitter ICs where it is used. Since an FPGA can be, as its name states, field programmable, firmware can be used to reconfigure the logic elements in the FPGA into a single <NUM> channel beamformer for some imaging procedures, or into 2x, 4x, 8x, or even higher order multiline beamformers for the production of multiple receive beams in response to a single transmit event in other imaging procedures. Furthermore, the use of the FPGA configuration described above has demonstrated that a premium performance ultrasound system front-end with the foregoing capabilities can be realized with the use of only a single FPGA IC as illustrated in <FIG>.

The digital coherent echo signals resulting from beamformation are processed by a signal processor <NUM>, which performs functions such as decimation, filtering, spatial or frequency compounding and quadrature detection for Doppler processing. The processed signals are applied to a B mode processor <NUM>, where the B mode echo signals are amplitude detected and further processed for B mode image formation. The processed signals are also applied to a Doppler processor where ensembles of Doppler echo signals are processed to estimate the Doppler shift (frequency) of flow or motion at points in the image field. For a colorflow image the Doppler frequencies are used to look up color values in a color data table so that the Doppler-measured motion can be displayed in corresponding colors. The Doppler and B mode scanlines are coupled to an image processor <NUM>, where they are combined by scan conversion into overlays for an image of the desired display format, e.g., sector, linear or 3D. The resultant B mode, colorflow, color Doppler, or other multi-mode image is displayed on an image display <NUM>.

User control of the ultrasound system is effected through a user control <NUM>. Signals resulting from user interaction with the user control are coupled to a system controller <NUM> which coordinates the overall control of the ultrasound system, such as commanding the front-end circuitry to acquire B mode and Doppler echo signals for a desired imaging scan sequence definition, and controlling the B mode processor, the Doppler processor, and the image processor of the backend to process and combine these echo signals into a displayed colorflow or other image.

It should be noted that the various embodiments described above and illustrated by the exemplary ultrasound system of <FIG> may be implemented in hardware, software or a combination thereof. The various embodiments and/or components of an ultrasound system, for example, the modules, or components and controllers therein, also may be implemented as part of one or more computers or microprocessors. The computer or processor may include a computing device, an input device, a display unit and an interface, for example, for accessing the Internet. The computer or processor may include a microprocessor. The microprocessor may be connected to a communication bus, for example, to access a PACS system. The computer or processor may also include a memory. The memory devices described above may include Random Access Memory (RAM) and Read Only Memory (ROM). The computer or processor further may include a storage device, which may be a hard disk drive or a removable storage drive such as a floppy disk drive, optical disk drive, solid-state thumb drive, and the like. The storage device may also be other similar means for loading computer programs or other instructions into the computer or processor.

As used herein, the term "computer" or "module" or "processor" may include any processor-based or microprocessor-based system including systems using microcontrollers, reduced instruction set computers (RISC), ASICs, logic circuits, and any other circuit or processor capable of executing the functions described herein. The above examples are exemplary only, and are thus not intended to limit in any way the definition and/or meaning of these terms.

The computer or processor executes a set of instructions that are stored in one or more storage elements, in order to process input data. The storage elements may also store data or other information as desired or needed. The storage element may be in the form of an information source or a physical memory element within a processing machine.

Claim 1:
An ultrasound system for multi-mode imaging, the system comprising:
a probe (<NUM>) comprising an array of transducer elements (<NUM>);
a high voltage transmitter integrated circuit (<NUM>) comprising a pulser (<NUM>) adapted to produce high voltage drive pulses for pulse transmission and a linear transmitter (<NUM>) adapted to produce linear waveforms for linear transmission, the pulser (<NUM>) and the linear transmitter (<NUM>) coupled via a same output pin of the integrated circuit (<NUM>) to a common transducer element (<NUM>) of the array of transducer elements, the pulser (<NUM>) being adapted to generate transmit pulses from the common transducer element during a first imaging mode and the linear transmitter (<NUM>) being adapted to transmit a linear waveform from the common transducer element during a second imaging mode;
a beamformer (<NUM>) coupled to the array and adapted to beamform echo signals from the array; and
an image processor (<NUM>) that is coupled to receive beamformed echo signals from the beamformer (<NUM>) and adapted to produce a multi-mode image combining image data from the first imaging mode and the second imaging mode.