Patent Description:
Applications executing within a computing environment provide many operations used by numerous types of technologies, including but not limited to, engineering, manufacturing, medical technologies, automotive technologies, computer processing, etc. These applications, written in a programming language, such as COBOL, often perform complex calculations in performing the operations. The calculations include, for instance, power and/or exponentiation functions, which often require conversion of data from one format (e.g., binary coded decimal) to another format (e.g., hexadecimal floating point), and vice versa.

In order for an application to perform the conversion from one format to another format, various steps are executed. For instance, to convert from binary coded decimal to hexadecimal floating point, an application includes steps to convert a binary coded decimal number to an integer number, then the integer number is converted to hexadecimal floating point. Further, to convert back to binary coded decimal, the hexadecimal floating point number is converted to an integer number, and then the integer number is converted to binary coded decimal. Moreover, each of those steps may include sub-steps. This is time-consuming, impacting performance of the computing environment, and affecting availability of computer resources. <CIT> discloses a processor executing a convert instruction.

Shortcomings of the prior art are overcome, and additional advantages are provided through the provision of a computer program product for facilitating processing within a computing environment. The computer program product includes one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method. The method includes executing an instruction to perform converting and scaling operations. The executing the instruction includes converting an input value from one format to provide a converted result in another format, scaling the converted result into a scaled result, and placing a result obtained from the scaled result in a selected location.

By using a single instruction to perform the converting and scaling operations, performance is improved, and utilization of resources is reduced. By using a single architected instruction to perform the converting and scaling operations, certain tasks may be performed, such as the converting and scaling operations, much more efficiently than using a software paradigm. The converting and scaling operations are performed much faster, reducing execution time, and improving processor and/or overall system performance.

In one example, the one format is a hexadecimal floating point format, and the other format is a decimal format. As an example, the decimal format is a binary coded decimal format.

In one example, the scaling includes determining a scale factor and using the scale factor in scaling the converted result to provide the scaled result. The determining the scale factor includes, for instance, obtaining a scale value using an operand of the instruction and using the scale value to determine the scale factor. The using the scale factor includes multiplying the converted result by the scale factor to obtain the scaled result.

The scaling isolates, for instance, certain digits of a number to indicate a selected location in the number to truncate or round, as examples.

In one example, the scaled result is rounded to provide a rounded result. The rounding includes obtaining a rounding mode using a field of the instruction and rounding the scaled result to the rounded result based on the rounding mode.

In one example, the placing includes selecting a portion of the rounded result as the result and placing the result in the selected location.

In one example, a sign of the result is determined, and the sign of the result is placed in the selected location. The selected location is, for instance, a register specified using a field of the instruction.

In another aspect, a computer program product for facilitating processing within a computing environment is provided. The computer program product includes one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method The method includes executing an instruction to perform scaling and converting operations. The executing the instruction includes scaling an input value in one format to provide a scaled result, converting the scaled result from the one format to provide a converted result in another format, and placing a result obtained from the converted result in a selected location.

By using a single instruction to perform the scaling and converting operations, performance is improved, and utilization of resources is reduced. By using a single architected instruction to perform the scaling and converting operations, certain tasks may be performed, such as the scaling and converting operations, much more efficiently than using a software paradigm. The scaling and converting operations are performed much faster, reducing execution time, and improving processor and/or overall system performance.

In one example, the executing the instruction further includes rounding a version of the converted result to provide a rounded result, and wherein the result is obtained using the rounded result.

By using a single instruction to perform the scaling, converting and rounding operations, performance is improved, and utilization of resources is reduced. By using a single architected instruction to perform the scaling, converting and rounding operations, certain tasks may be performed, such as the scaling, converting and rounding operations, much more efficiently than using a software paradigm. The scaling, converting and rounding operations are performed much faster, reducing execution time, and improving processor and/or overall system performance.

As an example, the selected location is a register specified using a field of the instruction, and the placing the result in the selected location includes determining a format for the result and placing the result in the register based on the format.

Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Further, services relating to one or more aspects are also described and may be claimed herein.

Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and objects, features, and advantages of one or more aspects are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:.

In accordance with an aspect of the present invention, a capability is provided to facilitate processing within a computing environment. As one example, a single instruction (e.g., a single architected hardware machine instruction at the hardware/software interface) is provided to perform scale and convert operations. The instruction, referred to herein as a Decimal Scale and Convert to Hexadecimal Floating Point instruction, is part of a general-purpose processor instruction set architecture (ISA), which is dispatched by a program on a processor, such as a general-purpose processor. (In another example, the instruction may be part of a special-purpose processor, such as a co-processor configured for certain functions.

As part of execution of the single instruction (e.g., the Decimal Scale and Convert to Hexadecimal Floating Point instruction), various operations are performed including scaling the input data using a scale factor to provide scaled data and converting the scaled data from one format (e.g., binary coded decimal) to another format (e.g., hexadecimal floating point). Each of these operations is performed as part of executing the single instruction, improving system performance, and reducing use of system resources.

In accordance with another aspect of the present invention, a single instruction (e.g., a single architected hardware machine instruction at the hardware/software interface) is provided to perform convert and then scale operations. The instruction, referred to herein as a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction, is part of a general-purpose processor instruction set architecture (ISA), which is dispatched by a program on a processor, such as a general-purpose processor. (In another example, the instruction may be part of a special-purpose processor, such as a co-processor configured for certain functions.

As part of execution of the single instruction (e.g., the Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction), various operations are performed including converting the input data from one format (e.g., hexadecimal floating point) to another format (e.g., binary coded decimal), and scaling the converted data. Each of these operations is performed as part of executing the single instruction, improving system performance, and reducing use of system resources.

In one example, as indicated, the conversion is from binary coded decimal to hexadecimal floating point or from hexadecimal floating point to binary coded decimal. Binary coded decimal is a binary encoding of a decimal number, in which each decimal digit is represented by a fixed number of bits (e.g., <NUM> or <NUM> bits). Hexadecimal floating point is a format for encoding floating point numbers. In one example, a hexadecimal floating point number includes a sign bit, a characteristic (e.g., <NUM> bits) and a fraction (e.g., <NUM>, <NUM> or <NUM> digits). The characteristic represents a signed exponent and is obtained by adding, e.g., <NUM> to the exponent value. The range of the characteristic is <NUM> to <NUM>, which corresponds to an exponent range of, e.g., -<NUM> to +<NUM>. The magnitude of a hexadecimal floating point number is the product of its fraction and the number <NUM> raised to the power of the exponent that is represented by its characteristic. The number is positive or negative depending on whether the sign bit is, e.g., zero or one, respectively.

A hexadecimal floating point number may be represented in a number of different formats, including a short format (e.g., <NUM>-bit), a long format (e.g., <NUM>-bit) and an extended format (e.g., <NUM>-bit). In each format, the first bit (e.g., the first leftmost bit, bit <NUM>) is the sign bit; the next selected number of bits (e.g., seven bits) are the characteristic, and in the short and long formats, the remaining bits are the fraction, which include, e.g., six or fourteen hexadecimal digits, respectively. In the extended format, the fraction is, e.g., a <NUM>-digit fraction, and the extended hexadecimal floating point number consists of two long format numbers that are called the high-order and the low-order parts. The high-order part is any long hexadecimal floating point number. The fraction of the high-order part contains, e.g., the leftmost <NUM> hexadecimal digits of the <NUM>-digit fraction, and the fraction of the low-order part contains, e.g., the rightmost <NUM> hexadecimal digits of the <NUM>-digit fraction. The characteristic and sign of the high-order part are the characteristic and sign of the extended hexadecimal floating point number, and the sign and characteristic of the low-order part of an extended operand are ignored.

One embodiment of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to <FIG>. As an example, the computing environment is based on the z/Architecture® hardware architecture, offered by International Business Machines Corporation, Armonk, New York. One embodiment of the z/Architecture hardware architecture is described in a publication entitled, "<NPL>. The z/Architecture hardware architecture, however, is only one example architecture; other architectures and/or other types of computing environments of International Business Machines Corporation and/or of other entities may include and/or use one or more aspects of the present invention. z/Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

Referring to <FIG>, a computing environment <NUM> includes, for instance, a computer system <NUM> shown, e.g., in the form of a general-purpose computing device. Computer system <NUM> may include, but is not limited to, one or more processors or processing units <NUM> (e.g., central processing units (CPUs)), a memory <NUM> (a. , system memory, main memory, main storage, central storage or storage, as examples), and one or more input/output (I/O) interfaces <NUM>, coupled to one another via one or more buses and/or other connections <NUM>.

Bus <NUM> represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include the Industry Standard Architecture (ISA), the Micro Channel Architecture (MCA), the Enhanced ISA (EISA), the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI).

Memory <NUM> may include, for instance, a cache <NUM>, such as a shared cache, which may be coupled to local caches <NUM> of processors <NUM>. Further, memory <NUM> may include one or more programs or applications <NUM> and at least one operating system <NUM>. An example operating system includes a z/OS® operating system, offered by International Business Machines Corporation, Armonk, New York. z/OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems offered by International Business Machines Corporation and/or other entities may also be used. Memory <NUM> may also include one or more computer readable program instructions <NUM>, which may be configured to carry out functions of embodiments of aspects of the invention.

Computer system <NUM> may communicate via, e.g., I/O interfaces <NUM> with one or more external devices <NUM>, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices <NUM>, etc. A data storage device <NUM> may store one or more programs <NUM>, one or more computer readable program instructions <NUM>, and/or data, etc. The computer readable program instructions may be configured to carry out functions of embodiments of aspects of the invention.

Computer system <NUM> may also communicate via, e.g., I/O interfaces <NUM> with network interface <NUM>, which enables computer system <NUM> to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet), providing communication with other computing devices or systems.

Computer system <NUM> may include and/or be coupled to removable/non-removable, volatile/non-volatile computer system storage media. For example, it may include and/or be coupled to a non-removable, non-volatile magnetic media (typically called a "hard drive"), a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and/or an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM or other optical media. It should be understood that other hardware and/or software components could be used in conjunction with computer system <NUM>. Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc..

Computer system <NUM> may be operational with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and/or configurations that may be suitable for use with computer system <NUM> include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

In one example, a processor (e.g., processor <NUM>) includes a plurality of functional components used to execute instructions. As depicted in <FIG>, these functional components include, for instance, an instruction fetch component <NUM> to fetch instructions to be executed; an instruction decode unit <NUM> to decode the fetched instructions and to obtain operands of the decoded instructions; one or more instruction execute components <NUM> to execute the decoded instructions; a memory access component <NUM> to access memory for instruction execution, if necessary; and a write back component <NUM> to provide the results of the executed instructions. One or more of the components may access and/or use one or more registers <NUM> in instruction processing. Further, one or more of the components may, in accordance with one or more aspects of the present invention, include at least a portion of or have access to one or more other components used in performing scaling and/or converting operations of, e.g., a Decimal Scale and Convert to Hexadecimal Floating Point instruction and/or a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction (or other processing that may use one or more aspects of the present invention), as described herein. The one or more other components include, for instance, a scale/convert component (or one or more other components) <NUM>.

In accordance with an aspect of the present invention, an instruction, referred to herein as a Decimal Scale and Convert to Hexadecimal Floating Point instruction, is provided to perform, as part of executing the one instruction, at least, scaling and converting operations to convert a number from one format (e.g., decimal, such as signed packed decimal) to another format (e.g., hexadecimal floating point).

One embodiment of a Decimal Scale and Convert to Hexadecimal Floating Point instruction used to perform scale and convert operations is described with reference to <FIG>. The instruction is executed, in one example, using a general-purpose processor (e.g., processor <NUM>). In the description herein, specific locations, specific fields and/or specific sizes of the fields are indicated (e.g., specific bytes and/or bits). However, other locations, fields and/or sizes may be provided. Further, although the setting of a bit to a particular value, e.g., one or zero, may be specified, this is only an example. The bit may be set to a different value, such as the opposite value or to another value, in other examples. Many variations are possible.

In one example, the Decimal Scale and Convert to Hexadecimal Floating Point instruction has a VRR-b format that denotes a vector register and register operation with an extended operation code (opcode). The Decimal Scale and Convert to Hexadecimal Floating Point instruction is, for instance, part of a vector facility, which provides, for instance, fixed sized vectors ranging from one to sixteen elements. Each vector includes data which is operated on by vector instructions defined in the facility. In one embodiment, if a vector is made up of multiple elements, then each element is processed in parallel with the other elements. Instruction completion does not occur, in one example, until processing of all the elements is complete. In other embodiments, the elements are processed partially in parallel and/or sequentially.

In one embodiment, there are <NUM> vector registers and other types of registers can map to a quadrant of the vector registers. For instance, a register file, which is an array of processor registers in a central processing unit (e.g., processor <NUM>), may include <NUM> vector registers and each register is <NUM> bits in length. Sixteen floating point registers, which are <NUM> bits in length, can overlay the vector registers. Thus, as an example, when floating point register <NUM> is modified, then vector register <NUM> is also modified. Other mappings for other types of registers are also possible.

Vector data appears in storage, for instance, in the same left-to-right sequence as other data formats. Bits of a data format that are numbered <NUM>-<NUM> constitute the byte in the leftmost (lowest-numbered) byte location in storage, bits <NUM>-<NUM> form the byte in the next sequential location, and so on. In a further example, the vector data may appear in storage in another sequence, such as right-to-left.

As shown in <FIG>, in one example, a Decimal Scale and Convert to Hexadecimal Floating Point instruction <NUM> has a plurality of fields, and a field may have a subscript number associated therewith. The subscript number associated with a field of the instruction denotes the operand to which the field applies. For instance, the subscript number <NUM> associated with vector register Vi denotes that the register specified using Vi includes the first operand, and so forth. A register operand is one register in length, which is, for instance, <NUM> bits.

In one embodiment, Decimal Scale and Convert to Hexadecimal Floating Point instruction <NUM> includes operation code (opcode) fields 202a, 202b (e.g., bits <NUM>-<NUM> and <NUM>-<NUM>) indicating scale and convert operations, in which the input data is, e.g., a decimal number (e.g., a signed packed decimal number, such as a binary coded decimal number having, e.g., <NUM> digits and a sign) and the output is, e.g., a hexadecimal floating point value; a first vector register (V<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>) used to designate a first vector register; a second vector register (V<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>) used to designate a second vector register; a third vector register (V<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>) used to designate a third vector register; a first mask (M<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>); a second mask (M<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>); and a register extension bit (RXB) field <NUM> (e.g., bits <NUM>-<NUM>), each of which is described below. In one embodiment, the fields are separate and independent from one another; however, in other embodiments, more than one field may be combined. Further information regarding these fields is described below.

In one embodiment, vector register (V<NUM>) field <NUM> is used to indicate a vector register that is to store the first operand. The first operand is a result obtained from scaling and converting a decimal value to a hexadecimal floating point value. The second operand is contained in the vector register specified using vector register (V<NUM>) field <NUM> and is, for instance, a signed packed decimal number (e.g., a binary coded decimal having, e.g., <NUM> digits plus a sign) that is scaled using an unsigned integer included in the third operand, which is contained in the vector register specified using vector register (V<NUM>) field <NUM>.

In one example, each of vector register fields <NUM>, <NUM>, <NUM> is used with RXB field <NUM> to designate the vector register. For instance, RXB field <NUM> includes the most significant bit for a vector register designated operand. Bits for register designations not specified by the instruction are to be reserved and set to zero. The most significant bit is concatenated, for instance, to the left of the four-bit register designation of the vector register field to create a five-bit vector register designation.

In one example, the RXB field includes four bits (e.g., bits <NUM>-<NUM>), and the bits are defined, as follows:.

Each bit is set to zero or one by, for instance, the assembler depending on the register number. For instance, for registers <NUM>-<NUM>, the bit is set to <NUM>; for registers <NUM>-<NUM>, the bit is set to <NUM>, etc..

In one embodiment, each RXB bit is an extension bit for a particular location in an instruction that includes one or more vector registers. For instance, bit <NUM> of RXB is an extension bit for location <NUM>-<NUM>, which is assigned to, e.g., Vi, and so forth. In particular, for vector registers, the register containing the operand is specified using, for instance, a four-bit field of the register field with the addition of its corresponding register extension bit (RXB) as the most significant bit. For instance, if the four bit field is <NUM> and the extension bit is <NUM>, then the five bit field <NUM> indicates register number <NUM>. In a further embodiment, the RXB field includes additional bits, and more than one bit is used as an extension for each vector or location.

In one example, the size of the first operand is selected by a floating point format control specified, for instance, in M<NUM> field <NUM>. The M<NUM> field specifies the hexadecimal floating point format for operand one. If a reserved value of the M<NUM> field is specified, a specification exception is recognized. Example values for the M<NUM> field include, for instance:.

Although particular values and formats are provided as examples, additional, fewer and/or other values and/or formats may be used.

In one example, a rounding mode is specified using M<NUM> field <NUM>. The scaled and converted result is rounded by the rounding technique, as specified by a rounding mode control in the M<NUM> field, which is, for instance, in bit <NUM> of the four-bit M<NUM> field. When the control (e.g., bit) is, e.g., zero, a normalized result obtained from the converted result is truncated to form the result. When the control is, e.g., one, the normalized result is rounded to nearest with ties away from zero. A normalized result includes, for instance, the <NUM>, <NUM> or <NUM> most significant hexadecimal digits of the scaled and converted result for extended, long and short format, respectively, which includes, in one example, one guard digit on the right. (The guard digit may increase the precision of the final result because it participates in certain operations including, for instance, addition, subtraction, comparison, and the left shift that occurs during normalization. ) A one is added to the leftmost bit of the guard digit of the normalized result, any carry is propagated to the left, and the guard digit is dropped to produce the result fraction.

In execution of one embodiment of the Decimal Scale and Convert to Hexadecimal Floating Point instruction, the second operand is scaled using an unsigned integer in a selected location (e.g., byte element seven) of the third operand and converted to a hexadecimal floating point number. The second operand is multiplied by a scale factor which is equal to, for instance, <NUM> to the power of byte element seven of the third operand. The scaled result is converted to, e.g., a hexadecimal floating point value. The size of the first operand is selected by the floating point format control in the M<NUM> field. The scaled and converted result (e.g., a normalized converted result) is rounded using the rounding technique specified in the M<NUM> field. The result obtained from rounding the normalized converted result, based on the rounding mode control specified in M<NUM>, is placed in the entire vector register specified by the first operand, for all formats, placing the result in, e.g., the zero-indexed element in the vector and placing, e.g., zeros in any other elements.

The sign of the result is equal to the sign code of the second operand except when the second operand is zero, and then the result is forced to be a positive true zero. A true zero is a hexadecimal floating point number with a zero characteristic and a zero fraction.

In one example, the digits and sign of the second operand are checked for validity. If the validity check fails, a general operand data exception is recognized.

Further details of one embodiment of processing based on execution of a Decimal Scale and Convert to Hexadecimal Floating Point instruction, in accordance with one or more aspects of the present invention, are described with reference to <FIG>. In one example, a processor, such as a general processor <NUM>, is used to execute the instruction. As an example, hardware of the processor is used to execute the instruction. The hardware may be within the processor or coupled thereto for purposes of receiving the instruction from the processor, which, e.g., obtains, decodes and sets-up the instruction to execute on the hardware. Other variations are possible.

Referring to <FIG>, initially, an instruction, such as a Decimal Scale and Convert to Hexadecimal Floating Point instruction, is obtained (e.g., fetched, received, provided, etc.) (<NUM>), and executed (<NUM>). The executing includes, for instance, obtaining the second and third operands of the instruction (<NUM>). The second operand is, for instance, a signed packed decimal number obtained from a location (e.g., a vector register) specified by the instruction (e.g., using V<NUM> field <NUM>), and the third operand includes, for instance, an unsigned integer obtained from a location (e.g., a vector register) specified by the instruction (e.g., using V<NUM> field <NUM>). In one example, the unsigned integer is located in byte element seven of the third operand.

The second operand (e.g., the signed packed decimal number obtained using V<NUM>) is scaled using the unsigned integer in, e.g., byte element seven of the third operand (obtained using, e.g., V<NUM>) to obtain a scaled result (<NUM>).

The scaled result, which is in one format (e.g., decimal, such as signed packed decimal - a. , binary coded decimal), is converted to a converted result in another format (<NUM>). For instance, the scaled decimal number is converted to a hexadecimal floating point number. A result obtained from the converted result, as described herein, is placed in the first operand location (e.g., a register specified using V<NUM>) (<NUM>). Further details regarding the scaling, converting and placing are described with reference to <FIG>.

Referring initially to <FIG>, one embodiment of performing the scaling of the second operand (<NUM> of <FIG>) is described. In one example, a value, referred to as a scale value, of a selected portion (e.g., byte element seven) of the third operand (stored in a vector register designated using V<NUM>) is obtained (<NUM>). A determination is made as to whether the value is valid (<NUM>). For instance, a determination is made as to whether the value has a predetermined relationship with a preselected value, e.g., is the value less than a preselected value, such as <NUM>, as an example? If the value is invalid, the processing ends, e.g., with an error. However, if the value is valid, processing continues with using the value to determine a scale factor. For instance, the scale factor is equal to <NUM> to the power of the value (<NUM>). The second operand is multiplied by the scale factor to obtain a scaled result (<NUM>). In one example, since the second operand is a signed packed decimal number, the scaling by a power of <NUM> is equivalent to shifting the digits left. The scaling facilitates conversion of the signed packed decimal number to a hexadecimal floating point number by, e.g., isolating certain digits of a number to indicate a selected location in the number to truncate or round, as examples.

The scaled result, which is in one format (e.g., a decimal format), is then converted to a converted result, which is in another format (e.g., a hexadecimal floating point format) (<NUM> of <FIG>). The conversion may be performed using a number of techniques. In one example, to convert a decimal number to a hexadecimal number:.

The decimal number is divided by <NUM> into a quotient and a remainder;.

The remainder times <NUM> is a digit of the hexadecimal number, starting with the rightmost digit;.

The quotient is divided by <NUM> to provide another quotient and remainder; and.

The process repeats starting at the remainder times <NUM> until the quotient is <NUM>.

Although the above technique may be used to convert a decimal number to a hexadecimal number, other techniques may also be used. In one example, hardware logic is used to facilitate the conversion, improving the speed at which the processing may be performed.

One example of hardware logic used to perform the converting is described with reference to <FIG>. Referring to <FIG>, in one example, a binary coded decimal number <NUM> is input to the logic. Initially, up to <NUM> digits of the binary coded decimal number are selected <NUM>, starting at the leftmost digits of the binary coded decimal number. The selected digits are input to a counter tree <NUM>, which uses a redundant format of the digits and an equation to multiply each digit. In one example, the multiplying is performed by shifting the number, in which each power of <NUM> multiply is a shift of the number.

One example of an equation used by the counter tree is as follows, in which (X' + Y') is initially set to <NUM> and represents a value resulting from a previous loop in the counter tree, and A, B, C, D are digits of the binary coded decimal (BCD) number.

The processing loops in the counter tree until all of the digits of the BCD number have been processed. Output of counter tree <NUM> is input to a <NUM>:<NUM> adder <NUM>, which provides an intermediate converted result (e.g., intermediate hexadecimal floating point number) in a non-redundant format. The output of adder <NUM> is input to hex normalize, update exponent logic <NUM>, which is used to normalize the output of the adder and update the exponent to provide a hexadecimal floating point number. For instance, the normalization shifts to the left any leading zero digits which are to the right of the radix point to remove those digits and decreases the exponent by one for each shift.

One particular example of the above processing for an <NUM> digit BCD number is described herein. In the following example, since the actual values of X and Y are implementation specific (e.g., X and Y may be different values but still have the same sum), Z is used which is independent of the implementation. Thus, Z = X + Y; Z' = X' + Y'; and Z' is initialized to <NUM>. Further, in this example, BCD = <NUM>, and therefore, initially, A = <NUM>; B = <NUM>; C = <NUM>; D = <NUM>.

Next, A = <NUM>; B = <NUM>; C = <NUM>; D = <NUM>.

The hexadecimal floating point number (also referred to herein as the converted result) is used in obtaining a result, which is placed in the first operand location, such as a register specified using Vi (<NUM> of <FIG>), as described with reference to <FIG>. In one embodiment, a selected rounding mode is determined (<NUM>). For instance, the rounding mode indicator specified in M<NUM> is obtained and used to determine the rounding mode. The converted result (e.g., a version of the converted result) is then rounded based on the specified rounding mode to obtain a result (<NUM>). For instance, when the control (e.g., bit) is, e.g., zero, a normalized result obtained from the converted result is truncated to form the result. When the control is, e.g., one, the normalized result is rounded to nearest with ties away from zero. A normalized result includes, for instance, the <NUM>, <NUM> or <NUM> most significant hexadecimal digits of the scaled and converted result for extended, long and short format, respectively, which includes, in one example, one guard digit on the right. A one is added to the leftmost bit of the guard digit of the normalized result, any carry is propagated to the left, and the guard digit is dropped to produce the result fraction.

A sign of the result is also determined, in one example (<NUM>). For instance, the sign of the result is equal to the sign code of the second operand except when the second operand is zero, and then the result is forced to be a positive true zero. A true zero is a hexadecimal floating point number with a zero characteristic and a zero fraction.

Further, in one example, a format of the first operand is determined (<NUM>). For instance, a value stored in the M<NUM> field is obtained to determine the selected format. The result (e.g., the scaled, converted, normalized and rounded hexadecimal floating point result) and the sign are placed in the selected location (e.g., register specified using V<NUM>) based on the selected format (<NUM>). For instance, the result and sign are placed in the entire vector register specified by the first operand, for each of the formats, placing the result starting in, e.g., the zero-indexed element in the vector and placing, e.g., zeros in any other elements.

Although various fields and registers of the Decimal Scale and Convert to Hexadecimal Floating Point instruction are described, one or more aspects of the present invention may use other, additional and/or fewer fields and/or registers, and/or other sizes of fields and/or registers, etc. Many variations are possible. For instance, implied registers may be used instead of explicitly specified registers and/or fields of the instruction and/or explicitly specified registers and/or fields may be used instead of implied registers and/or fields. Other variations are also possible.

As described herein, in one aspect, a single instruction (e.g., a single architected machine instruction at the hardware/software interface, e.g., a Decimal Scale and Convert to Hexadecimal Floating Point instruction) is provided to perform a scaling of a decimal number to provide a scaled decimal number and converting the scaled decimal number to a hexadecimal floating point number. Further, in one embodiment, this single instruction is also able to round the converted result (e.g., a version of the converted result, such as a normalized converted result) based on a selected rounding mode and/or is able to format the result based on a selected format of a plurality of possible formats. This instruction is, for instance, a hardware instruction defined in an instruction set architecture (ISA) that directly converts a value in one format, e.g., a decimal number, to a value in another format, e.g., a hexadecimal floating point number. The conversion is direct from, e.g., a decimal number to a hexadecimal floating point number, rather than from, e.g., decimal to integer and integer to hexadecimal floating point. Processing is faster and more efficient than a program performing, for instance, a binary coded decimal multiply or shift, converting binary coded decimal to integer, and converting integer to hexadecimal floating point. The complexity of a program related to performing scale and convert operations is reduced. Further, performance of the operations, and thus, the processor, is improved. The hardware instruction execution reduces execution times and improves performance.

By using a single instruction to perform, e.g., the scaling and converting (and, optionally, rounding; and/or other operations), rather than multiple instructions, performance is improved by not requiring multiple passes through the hardware/software interface. Further, by performing the processing as part of one instruction, the processing remains in the processing unit performing the operations (e.g., a floating point processing unit), not requiring prior to completing the processing, updating of the registers of a register file of the processor (i.e., an array of processor registers used to store data between memory and the functional units, e.g., a floating point processing unit). This improves execution time and reduces use of processor resources.

In a further aspect, a hexadecimal floating point value is converted to a decimal value (e.g., a binary coded decimal value). To provide the conversion, in one example, a single architected machine instruction, referred to herein as a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction, is used. This single instruction performs, as part of executing the one instruction, at least, converting a value from one format (e.g., hexadecimal floating point) to a converted result in another format (e.g., decimal, such as binary coded decimal), and scaling the converted result to provide a scaled result (e.g., a scaled decimal value).

One embodiment of a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction used to perform, at least, convert and scale operations is described with reference to <FIG>. The instruction is executed, in one example, using a general-purpose processor (e.g., processor <NUM>). In the description herein, specific locations, specific fields and/or specific sizes of the fields are indicated (e.g., specific bytes and/or bits). However, other locations, fields and/or sizes may be provided. Further, although the setting of a bit to a particular value, e.g., one or zero, may be specified, this is only an example. The bit may be set to a different value, such as the opposite value or to another value, in other examples. Many variations are possible.

In one example, the Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction has a VRR-j format that denotes a vector register and register operation with an extended operation code (opcode). The instruction is, for instance, part of the vector facility, as described herein.

As shown in <FIG>, in one example, a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction <NUM> has a plurality of fields, and a field may have a subscript number associated therewith. The subscript number associated with a field of the instruction denotes the operand to which the field applies. For instance, the subscript number <NUM> associated with vector register Vi denotes that the register specified using Vi includes the first operand, and so forth. A register operand is one register in length, which is, for instance, <NUM> bits.

In one embodiment, Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction <NUM> includes operation code (opcode) fields 702a, 702b (e.g., bits <NUM>-<NUM> and <NUM>-<NUM>) indicating convert and scale operations in which the input data is, e.g., a hexadecimal floating point number and the output is, e.g., a decimal (e.g., binary coded decimal) number; a first vector register (V<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>) used to designate a first vector register; a second vector register (V<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>) used to designate a second vector register; a third vector register (V<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>) used to designate a third vector register; a mask (M<NUM>) field <NUM> (e.g., bits <NUM>-<NUM>); and a register extension bit (RXB) field <NUM> (e.g., bits <NUM>-<NUM>), each of which is described below. In one embodiment, the fields are separate and independent from one another; however, in other embodiments, more than one field may be combined. Further information regarding these fields is described below.

In one embodiment, vector register (V<NUM>) field <NUM> is used to indicate a vector register that is to store the first operand. The first operand is a result of converting a hexadecimal floating point value to a decimal value, scaling the decimal value to provide a scaled result, and using the scaled result to obtain the result. The second operand is contained in the vector register specified using vector register (V<NUM>) field <NUM> and is, for instance, an extended precision hexadecimal floating point number. The extended precision hexadecimal floating point number is converted to a binary coded decimal number that is scaled using an unsigned integer included in the third operand, which is contained in the vector register specified using vector register (V<NUM>) field <NUM>. In one example, each of vector register fields <NUM>, <NUM>, <NUM> is used with RXB field <NUM> to designate the vector register, as described herein.

In one example, a rounding mode is specified using M<NUM> field <NUM>. The converted and scaled result is rounded by the rounding technique, as specified by a rounding mode modifier in the M<NUM> field, which is, for instance, in bit <NUM> of the four-bit M<NUM> field. When the control (e.g., bit) is, e.g., zero, the scaled result is truncated to form the result. When the bit is, e.g., one, the scaled result is rounded to nearest with ties away from zero.

In execution of one embodiment of the Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction, the second operand (e.g., an extended precision hexadecimal floating point number) is converted to a converted result (e.g., a binary coded decimal number), and the converted result is scaled to provide a scaled result, which is, for instance, rounded to obtain a result (e.g., a decimal integer).

Further details of one embodiment of processing based on execution of a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction, in accordance with one or more aspects of the present invention, are described with reference to <FIG>. In one example, a processor, such as a general processor <NUM>, is used to execute the instruction. As an example, hardware of the processor is used to execute the instruction. The hardware may be within the processor or coupled thereto for purposes of receiving the instruction from the processor, which, e.g., obtains, decodes and sets-up the instruction to execute on the hardware. Other variations are possible.

Referring to <FIG>, initially, an instruction, such as a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction, is obtained (e.g., fetched, received, provided, etc.) <NUM> and executed <NUM>. The executing includes, for instance, obtaining the second and third operands of the instruction <NUM>. The second operand is, for instance, an extended precision hexadecimal floating point number obtained from a location (e.g., a vector register) specified by the instruction (e.g., using V<NUM> field <NUM>), and the third operand includes, for instance, an unsigned integer obtained from a location (e.g., a vector register) specified by the instruction (e.g., using V<NUM> field <NUM>). In one example, the unsigned integer is located in byte element seven of the third operand.

The second operand, which is in one format (e.g., the extended precision hexadecimal floating point number obtained using V<NUM>), is converted to another format (e.g., a binary coded decimal number), which is referred to herein as a converted result <NUM>. The converted result is scaled using the unsigned integer in, e.g., byte element seven of the third operand (obtained using, e.g., V<NUM>) to obtain a scaled result <NUM>. The scaled result is rounded, based on the rounding mode specified in M<NUM> field <NUM>, to obtain a rounded result (e.g., a decimal integer) <NUM>. A result, obtained from the rounded result, is placed at the first operand location (e.g., in the vector register specified using V<NUM>) <NUM>. Further details regarding the converting, scaling and placing are described below.

As indicated, the second operand, which is in one format (e.g., the extended precision hexadecimal floating point number obtained using V<NUM>), is converted to another format (e.g., a binary coded decimal number), which is referred to as a converted result (<NUM> of <FIG>). The conversion may be performed using a number of techniques. In one example, the conversion includes converting a hexadecimal number to a decimal number. To perform such a conversion, in one example, the decimal equivalent of each digit of the hexadecimal number is multiplied by <NUM> raised to a power, in which the power starts at <NUM> for the rightmost hexadecimal digit and increases by one for each next digit. For instance, to convert hex ABC to decimal, C=<NUM> is multiplied by <NUM>° (<NUM> x <NUM> = <NUM>); B=<NUM> is multiplied by <NUM><NUM> (<NUM> x <NUM> = <NUM>); and A=<NUM> is multiplied by <NUM><NUM> (<NUM> x <NUM> = <NUM>). Then, the results of each multiplication are added together, such as <NUM> + <NUM> + <NUM> = <NUM>. Thus, hexadecimal ABC is equal to <NUM> in decimal.

Further, if there is a fractional part, then the fractional part is converted to decimal, as follows, in one example: The decimal equivalent of each digit of the fractional hexadecimal number is multiplied by <NUM> raised to a negative power, in which the power starts at -<NUM> for the leftmost hexadecimal digit after the period and increased by one for each next digit. For instance, to convert hex. DEF to decimal, D=<NUM> is multiplied by <NUM>-<NUM> (<NUM> x <NUM> = <NUM>); E=<NUM> is multiplied by <NUM>-<NUM> (<NUM> x <NUM> = <NUM>); and F=<NUM> is multiplied by <NUM>-<NUM> (<NUM> x <NUM> = <NUM>). Then, the results of each multiplication are added together, such as <NUM> + <NUM> + <NUM> = <NUM>. Thus, hexadecimal. DEF is equal to <NUM> in decimal.

The integer value (e.g., <NUM>) is combined, in one example, with the fractional value (<NUM>) to provide a result of <NUM>, which is the decimal equivalent of xABC.

Although the above technique may be used to convert a hexadecimal number to a decimal number, other techniques may also be used. In one example, hardware logic is used to facilitate the conversion, improving the speed at which the processing may be performed.

One example of hardware logic used to perform the converting is described with reference to <FIG>. To facilitate understanding of the hardware logic, a particular example is shown. However, this is only one example and not meant to be limiting in any way.

Referring to <FIG>, in one example, a hexadecimal floating point number (HFP) <NUM> is input to the logic. As a particular example, the input hexadecimal floating point number is ABC. Initially, the hexadecimal floating point number is split <NUM> into a hexadecimal floating point fraction part <NUM> (e.g., DEF) and a hexadecimal floating point integer part (e.g., ABC) <NUM>. The fractional part <NUM> and a selected value (e.g., decimal <NUM><NUM> = x5F5E100) are input to a counter tree <NUM>. The counter tree multiplies x5F5E100 by a redundant format of the fractional digits of the fractional part to provide a result. The output of counter tree <NUM> is input to a <NUM>:<NUM> adder <NUM> to provide a non-redundant product having an integer portion and a fractional portion. For instance, the output of adder <NUM> is 530CFA0F00, which is input to split logic <NUM>, which splits the value into an integer portion 530CFA0 and a fractional portion F00 and the process repeats.

An integer portion <NUM> (e.g., ABC) with a shift amount of five (e.g., 00000ABC) is input to a hexadecimal to decimal conversion logic <NUM>. In one example, two hexadecimal digits per cycle are converted to binary coded decimal starting with the most significant digit, in which it takes four loops to convert eight hexadecimal digits. For instance, for the integer portion, S=<NUM>; H(i, i+<NUM>) =>A; prior accumulated sum goes through eight binary coded decimal doublers (2x) to multiply by, e.g., <NUM>. Then, the converted hex is summed to old sum * <NUM> (S' = S * <NUM> + A; i = i+<NUM>). It takes four loops to convert eight hexadecimal digits.

As shown, the output of hexadecimal to decimal conversion logic <NUM> is input to adder <NUM> (e.g., a <NUM>:<NUM> adder), as well as up to eight decimal digits from a previous loop <NUM>. The output of adder <NUM>, after a second loop, for the particular example given, is <NUM>. The final output of the adder is input to a final shift round logic <NUM>. In one example, there are a scaling by <NUM><NUM> and a round function. Therefore, ABC. DEF in hexadecimal is converted to a binary coded decimal number of <NUM>. (<NUM> scale by <NUM><NUM> and rounded = <NUM>.

To summarize, for a six digit hexadecimal number, such as ABC. DEF and a shift amount of <NUM>, the logic performs, as follows:.

In one example, when multiply by <NUM><NUM>, the original radix point is to be retained, so multiply by <NUM>-<NUM> to offset the multiply by <NUM><NUM>. <NUM> and scale by <NUM><NUM> and round = <NUM>.

In one example, after converting the hexadecimal number to a binary coded decimal number, the converted result is scaled (<NUM> of <FIG>). For instance, as described with reference to <FIG>, a value, referred to as a scale value, of a selected portion (e.g., byte element seven) of the third operand (stored in a vector register designated using V<NUM>) is obtained (<NUM>). A determination is made as to whether the value is valid (<NUM>). For instance, a determination is made as to whether the value has a predetermined relationship with a preselected value, e.g., is the value less than a preselected value, such as <NUM>, as an example? If the value is invalid, the processing ends, e.g., with an error. However, if the value is valid, processing continues with using the value to determine a scale factor. For instance, the scale factor is equal to <NUM> to the power of the value (<NUM>). The second operand is multiplied by the scale factor to obtain a scaled result (<NUM>). In one example, the scaling by a power of <NUM> is equivalent to a shift operation. The scaling facilitates conversion of the extended precision hexadecimal floating point number by, e.g., allowing more digits to be converted if the result is fractional.

In one example, the converted and scaled value is rounded to obtain a rounded result (<NUM> of <FIG>). For instance, the scaled result is rounded by the rounding technique, as specified by a rounding mode modifier in the M<NUM> field, which is, for instance, in bit <NUM> of the four-bit M<NUM> field <NUM>. When the control (e.g., bit) is, e.g., zero, the scaled result is truncated to form the result. When the control is, e.g., one, the scaled result is rounded to nearest with ties away from zero. A result is obtained from the rounded result. For instance, a selected portion of the rounded result is selected as the result (e.g., a decimal number, such as a <NUM>-digit signed packed decimal number), which is placed in the first operand location (<NUM> of <FIG>).

Further details regarding one embodiment of the placing are described with reference to <FIG>. In one embodiment, a portion of the rounded result (e.g., rightmost <NUM> digits of the decimal integer, ignoring any overflow) is selected as the decimal integer result (<NUM>). Further, in one example, a sign of the result is determined (<NUM>). For instance, the sign of the result is equal to the sign of the second operand even when the second operand is negative zero. The result and the sign are placed in the first operand location (<NUM>).

Although various fields and registers of the Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction are described, one or more aspects of the present invention may use other, additional and/or fewer fields and/or registers, and/or other sizes of fields and/or registers, etc. Many variations are possible. For instance, implied registers may be used instead of explicitly specified registers and/or fields of the instruction and/or explicitly specified registers and/or fields may be used instead of implied registers and/or fields. Other variations are also possible.

As described herein, in one aspect, a single instruction (e.g., a single architected machine instruction at the hardware/software interface, e.g., a Vector Convert Hexadecimal Floating Point to Scaled Decimal instruction) is provided to perform converting of a hexadecimal floating point number to a decimal number and scaling the decimal number to provide a scaled decimal number. Further, in one embodiment, this single instruction is also able to round the converted and scaled result based on a selected rounding mode. This instruction is, for instance, a hardware instruction defined in an instruction set architecture (ISA) that directly converts a value in one format, e.g., a hexadecimal floating point number, to a value in another format, e.g., a decimal number. The conversion is direct from, e.g., a hexadecimal floating point number, to a decimal number, rather than from, e.g., hexadecimal floating point number to integer and integer to decimal, as performed by programs. Thus, processing is faster and more efficient, and the complexity of a program related to performing convert and scale operations is reduced. Further, performance of the operations, and thus, the processor, is improved. The hardware instruction execution reduces execution times and improves performance.

By using a single instruction to perform, e.g., the converting and scaling operations (and, optionally, rounding), rather than multiple instructions, performance is improved by not requiring multiple passes through the hardware/software interface. Further, by performing the processing as part of one instruction, the processing remains in the processing unit performing the operations (e.g., a floating point processing unit), not requiring prior to completing the processing, updating of the registers of a register file of the processor (i.e., an array of processor registers used to store data between memory and the functional units, e.g., a floating point processing unit). This improves execution time and reduces use of processor resources.

One or more aspects of the present invention are inextricably tied to computer technology and facilitate processing within a computer, improving performance thereof. The use of a single architected machine instruction to, at least, perform a scale of a decimal number (e.g., a binary coded decimal number) to obtain a scaled decimal number, to convert the scaled decimal number to a hexadecimal floating point number, and optionally, to perform rounding improves performance within the computing environment by reducing complexity, reducing use of resources and increasing processing speed. Further, the use of a single architected machine instruction to convert a hexadecimal floating point number to a decimal number (e.g., a binary coded decimal number) and to scale the decimal number to obtain a scaled decimal number (and, in one embodiment, round the result and/or perform other operations) improves performance within the computing environment by reducing complexity, reducing use of resources and increasing processing speed. The data and/or instruction(s) may be used in many technical fields, such as in computer processing, medical processing, engineering, automotive technologies, manufacturing, etc. By providing optimizations in converting the data, these technical fields are improved by reducing execution time.

Further details of embodiments of facilitating processing within a computing environment, as it relates to one or more aspects of the present invention, are described with reference to <FIG>.

Referring to <FIG>, in one embodiment, an instruction is executed to perform converting and scaling operations (<NUM>). The executing the instruction includes converting an input value from one format to provide a converted result in another format (<NUM>), scaling the converted value to provide a scaled result (<NUM>), and placing a result obtained from the scaled result in a selected location (<NUM>).

In one example, the one format is a hexadecimal floating point format, and the other format is a decimal format (<NUM>). As an example, the decimal format is a binary coded decimal format (<NUM>).

In one example, the scaling includes determining a scale factor (<NUM>) and using the scale factor in scaling the converted result to provide the scaled result (<NUM>). The determining the scale factor includes, for instance, obtaining a scale value using an operand of the instruction (<NUM>) and using the scale value to determine the scale factor (<NUM>). The using the scale factor includes multiplying the converted result by the scale factor to obtain the scaled result (<NUM>).

In one example, referring to <FIG>, the executing further includes rounding the scaled result to provide a rounded result (<NUM>). The rounding includes, for instance, obtaining a rounding mode using a field of the instruction (<NUM>) and rounding the scaled result to the rounded result based on the rounding mode (<NUM>).

By using a single instruction to perform, at least, the converting, scaling and rounding operations, performance is improved, and utilization of resources is reduced. By using a single architected instruction to perform the converting, scaling and rounding operations, certain tasks may be performed, such as the converting, scaling and rounding operations, much more efficiently than using a software paradigm. The converting, scaling and rounding operations are performed much faster, reducing execution time, and improving processor and/or overall system performance.

In one example, the placing includes selecting a portion of the rounded result as the result (<NUM>) and placing the result in the selected location (<NUM>). In one example, a sign of the result is determined (<NUM>), and the sign of the result is placed in the selected location (<NUM>). The selected location includes, for instance, a register specified using a field of the instruction (<NUM>).

In another aspect, referring to <FIG>, in one embodiment, an instruction is executed to perform scaling and converting operations (<NUM>). The executing the instruction includes, for instance, scaling an input value in one format to provide a scaled result (<NUM>), converting the scaled result from the one format to provide a converted result in another format (<NUM>), and placing a result obtained from the converted result in a selected location (<NUM>).

By using a single instruction to perform, at least, the scaling and converting operations, performance is improved, and utilization of resources is reduced. By using a single architected instruction to perform the scaling and converting operations, certain tasks may be performed, such as the scaling and converting operations, much more efficiently than using a software paradigm. The scaling and converting operations are performed much faster, reducing execution time, and improving processor and/or overall system performance.

In one example, the executing the instruction further includes rounding a version of the converted result to provide a rounded result (<NUM>), and the result is obtained using the rounded result (<NUM>).

By using a single instruction to perform, at least, the scaling, converting and rounding operations, performance is improved, and utilization of resources is reduced. By using a single architected instruction to perform the scaling, converting and rounding operations, certain tasks may be performed, such as the scaling, converting and rounding operations, much more efficiently than using a software paradigm. The scaling, converting and rounding operations are performed much faster, reducing execution time, and improving processor and/or overall system performance.

As an example, the selected location is a register specified using a field of the instruction (<NUM>), and the placing the result in the selected location includes determining a format for the result (<NUM>) and placing the result in the register based on the format (<NUM>).

Other variations and embodiments are possible.

Aspects of the present invention may be used by many types of computing environments. Another example of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to <FIG>. As an example, the computing environment of <FIG> is based on the z/Architecture® hardware architecture offered by International Business Machines Corporation, Armonk, New York. The z/Architecture hardware architecture, however, is only one example architecture. Again, the computing environment may be based on other architectures, including, but not limited to, the Intel® x86 architectures, other architectures of International Business Machines Corporation, and/or architectures of other companies. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

In one example, a computing environment <NUM> includes a central electronics complex (CEC) <NUM>. Central electronics complex <NUM> includes a plurality of components, such as, for instance, a memory <NUM> (a. , system memory, main memory, main storage, central storage, storage) coupled to one or more processors (a. , central processing units (CPUs)) <NUM> and to an input/output (I/O) subsystem <NUM>.

I/O subsystem <NUM> can be a part of the central electronics complex or separate therefrom. It directs the flow of information between main storage <NUM> and input/output control units <NUM> and input/output (I/O) devices <NUM> coupled to the central electronics complex.

Many types of I/O devices may be used. One particular type is a data storage device <NUM>. Data storage device <NUM> can store one or more programs <NUM>, one or more computer readable program instructions <NUM>, and/or data, etc. The computer readable program instructions can be configured to carry out functions of embodiments of aspects of the invention.

Central electronics complex <NUM> can include and/or be coupled to removable/non-removable, volatile/non-volatile computer system storage media. For example, it can include and/or be coupled to a non-removable, non-volatile magnetic media (typically called a "hard drive"), a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and/or an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM or other optical media. It should be understood that other hardware and/or software components could be used in conjunction with central electronics complex <NUM>. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc..

Further, central electronics complex <NUM> can be operational with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and/or configurations that may be suitable for use with central electronics complex <NUM> include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

Central electronics complex <NUM> provides in one or more embodiments logical partitioning and/or virtualization support. In one embodiment, as shown in <FIG>, memory <NUM> includes, for example, one or more logical partitions <NUM>, a hypervisor <NUM> that manages the logical partitions, and processor firmware <NUM>. One example of hypervisor <NUM> is the Processor Resource/System Manager (PR/SM™), offered by International Business Machines Corporation, Armonk, New York. As used herein, firmware includes, e.g., the microcode of the processor. It includes, for instance, the hardware-level instructions and/or data structures used in implementation of higher level machine code. In one embodiment, it includes, for instance, proprietary code that is typically delivered as microcode that includes trusted software or microcode specific to the underlying hardware and controls operating system access to the system hardware. PRISM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

Each logical partition <NUM> is capable of functioning as a separate system. That is, each logical partition can be independently reset, run a guest operating system <NUM> such as the z/OS® operating system, offered by International Business Machines Corporation, Armonk, New York, or other control code <NUM>, such as coupling facility control code (CFCC), and operate with different programs <NUM>. An operating system or application program running in a logical partition appears to have access to a full and complete system, but in reality, only a portion of it is available. Although the z/OS operating system is offered as an example, other operating systems offered by International Business Machines Corporation and/or other companies may be used in accordance with one or more aspects of the present invention.

Memory <NUM> is coupled to CPUs <NUM> (<FIG>), which are physical processor resources that can be allocated to the logical partitions. For instance, a logical partition <NUM> includes one or more logical processors, each of which represents all or a share of a physical processor resource <NUM> that can be dynamically allocated to the logical partition.

In yet a further embodiment, the central electronics complex provides virtual machine support (either with or without logical partitioning support). As shown in <FIG>, memory <NUM> of central electronics complex <NUM> includes, for example, one or more virtual machines <NUM>, a virtual machine manager, such as a hypervisor <NUM>, that manages the virtual machines, and processor firmware <NUM>. One example of hypervisor <NUM> is the z/VM® hypervisor, offered by International Business Machines Corporation, Armonk, New York. The hypervisor is sometimes referred to as a host z/VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

The virtual machine support of the central electronics complex provides the ability to operate large numbers of virtual machines <NUM>, each capable of operating with different programs <NUM> and running a guest operating system <NUM>, such as the Linux® operating system. Each virtual machine <NUM> is capable of functioning as a separate system. That is, each virtual machine can be independently reset, run a guest operating system, and operate with different programs. An operating system or application program running in a virtual machine appears to have access to a full and complete system, but in reality, only a portion of it is available. Although z/VM and Linux are offered as examples, other virtual machine managers and/or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux® is used pursuant to a sublicense from the Linux Foundation, the exclusive licensee of Linus Torvalds, owner of the mark on a worldwide basis.

Another embodiment of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to <FIG>. In this example, a computing environment <NUM> includes, for instance, a native central processing unit (CPU) <NUM>, a memory <NUM>, and one or more input/output devices and/or interfaces <NUM> coupled to one another via, for example, one or more buses <NUM> and/or other connections. As examples, computing environment <NUM> may include a PowerPC® processor offered by International Business Machines Corporation, Armonk, New York; an HP Superdome with Intel® Itanium® II processors offered by Hewlett Packard Co. , Palo Alto, California; and/or other machines based on architectures offered by International Business Machines Corporation, Hewlett Packard, Intel Corporation, Oracle, and/or others. PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

Native central processing unit <NUM> includes one or more native registers <NUM>, such as one or more general purpose registers and/or one or more special purpose registers used during processing within the environment. These registers include information that represents the state of the environment at any particular point in time.

Moreover, native central processing unit <NUM> executes instructions and code that are stored in memory <NUM>. In one particular example, the central processing unit executes emulator code <NUM> stored in memory <NUM>. This code enables the computing environment configured in one architecture to emulate another architecture. For instance, emulator code <NUM> allows machines based on architectures other than the z/Architecture hardware architecture, such as PowerPC processors, HP Superdome servers or others, to emulate the z/Architecture hardware architecture and to execute software and instructions developed based on the z/Architecture hardware architecture.

Further details relating to emulator code <NUM> are described with reference to <FIG>. Guest instructions <NUM> stored in memory <NUM> comprise software instructions (e.g., correlating to machine instructions) that were developed to be executed in an architecture other than that of native CPU <NUM>. For example, guest instructions <NUM> may have been designed to execute on a processor based on the z/Architecture hardware architecture, but instead, are being emulated on native CPU <NUM>, which may be, for example, an Intel Itanium II processor. In one example, emulator code <NUM> includes an instruction fetching routine <NUM> to obtain one or more guest instructions <NUM> from memory <NUM>, and to optionally provide local buffering for the instructions obtained. It also includes an instruction translation routine <NUM> to determine the type of guest instruction that has been obtained and to translate the guest instruction into one or more corresponding native instructions <NUM>. This translation includes, for instance, identifying the function to be performed by the guest instruction and choosing the native instruction(s) to perform that function.

Further, emulator code <NUM> includes an emulation control routine <NUM> to cause the native instructions to be executed. Emulation control routine <NUM> may cause native CPU <NUM> to execute a routine of native instructions that emulate one or more previously obtained guest instructions and, at the conclusion of such execution, return control to the instruction fetch routine to emulate the obtaining of the next guest instruction or a group of guest instructions. Execution of the native instructions <NUM> may include loading data into a register from memory <NUM>; storing data back to memory from a register; or performing some type of arithmetic or logic operation, as determined by the translation routine.

Each routine is, for instance, implemented in software, which is stored in memory and executed by native central processing unit <NUM>. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software or some combination thereof. The registers of the emulated processor may be emulated using registers <NUM> of the native CPU or by using locations in memory <NUM>. In embodiments, guest instructions <NUM>, native instructions <NUM> and emulator code <NUM> may reside in the same memory or may be disbursed among different memory devices.

Example instructions that may be emulated are the Decimal Scale and Convert To Hexadecimal Floating Point instruction and the Vector Convert Hexadecimal Floating Point To Scaled Decimal instruction described herein, in accordance with one or more aspects of the present invention.

The computing environments described above are only examples of computing environments that can be used. Other environments, including but not limited to, non-partitioned environments, partitioned environments, cloud environments and/or emulated environments, may be used; embodiments are not limited to any one environment. Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are only examples.

Each computing environment is capable of being configured to include one or more aspects of the present invention.

One or more aspects may relate to cloud computing.

Measured service: cloud systems automatically control and optimize resource use by leveraging a metering capability at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency for both the provider and consumer of the utilized service.

Infrastructure as a Service (IaaS): the capability provided to the consumer is to provision processing, storage, networks, and other fundamental computing resources where the consumer is able to deploy and run arbitrary software, which can include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure but has control over operating systems, storage, deployed applications, and possibly limited control of select networking components (e.g., host firewalls).

Deployment Models are as follows:
Private cloud: the cloud infrastructure is operated solely for an organization. It may be managed by the organization or a third party and may exist on-premises or off-premises.

Workloads layer <NUM> provides examples of functionality for which the cloud computing environment may be utilized. Examples of workloads and functions which may be provided from this layer include: mapping and navigation <NUM>; software development and lifecycle management <NUM>; virtual classroom education delivery <NUM>; data analytics processing <NUM>; transaction processing <NUM>; and scale and convert and/or convert and scale (and round processing) <NUM>.

Aspects of the present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration.

In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider who offers management of customer environments. For instance, the service provider can create, maintain, support, etc. computer code and/or a computer infrastructure that performs one or more aspects for one or more customers. In return, the service provider may receive payment from the customer under a subscription and/or fee agreement, as examples. Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.

In one aspect, an application may be deployed for performing one or more embodiments. As one example, the deploying of an application comprises providing computer infrastructure operable to perform one or more embodiments.

As a further aspect, a computing infrastructure may be deployed comprising integrating computer readable code into a computing system, in which the code in combination with the computing system is capable of performing one or more embodiments.

As yet a further aspect, a process for integrating computing infrastructure comprising integrating computer readable code into a computer system may be provided. The computer system comprises a computer readable medium, in which the computer medium comprises one or more embodiments. The code in combination with the computer system is capable of performing one or more embodiments.

Although various embodiments are described above, these are only examples. For instance, computing environments of other architectures can be used to incorporate and/or use one or more aspects. Further, different instructions or operations may be used. Additionally, different types of registers and/or different register may be used. Many variations are possible.

Various aspects are described herein. It should be noted that, unless otherwise inconsistent, each aspect or feature described herein, and variants thereof, may be combinable with any other aspect or feature.

Further, other types of computing environments can benefit and be used. As an example, a data processing system suitable for storing and/or executing program code is usable that includes at least two processors coupled directly or indirectly to memory elements through a system bus. The memory elements include, for instance, local memory employed during actual execution of the program code, bulk storage, and cache memory which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

Input/Output or I/O devices (including, but not limited to, keyboards, displays, pointing devices, DASD, tape, CDs, DVDs, thumb drives and other memory media, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.

It will be further understood that the terms "comprises" and/or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Claim 1:
A computer program product for facilitating processing within a computing environment, the computer program product comprising:
one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method comprising:
executing a convert instruction (<NUM>, <NUM>) to perform converting and scaling operations, the convert instruction (<NUM>, <NUM>) being part of an instruction set architecture, the executing the convert instruction (<NUM>, <NUM>) comprising:
scaling a value to provide a scaled result, wherein the scaling includes, as part of executing the convert instruction (<NUM>, <NUM>):
obtaining (<NUM>), using a field of the convert instruction (<NUM>, <NUM>), a scale value;
determining whether the scale value is valid (<NUM>), wherein the determining is based on a preselected value;
using the scale value to determine (<NUM>) a scale factor different from the scale value, based on determining that the scale value is valid; and
using the scale factor in scaling the value to provide the scaled result (<NUM>), wherein the value is an input value of the convert instruction (<NUM>, <NUM>) or a converted result (<NUM>) obtained from converting, as part of executing the convert instruction (<NUM>, <NUM>), the input value from one format to another format;
converting (<NUM>) the scaled result to provide a converted scaled result, based on the value being the input value; and
placing (<NUM>, <NUM>) a result obtained from the executing the convert instruction (<NUM>, <NUM>) in a selected location.