Patent Description:
As CMOS transistor geometries get smaller and smaller, safe operating voltages on the internal transistors get lower. Therefore, inputs and outputs of the devices must use larger geometry transistors in the I/O circuits to protect the device from excessive voltages to prevent damage to the internal logic of the device. Current injection on an analog input pin has additional concerns. Injection current can cause a degradation in the accuracy of the analog-to-digital converter (ADC). In addition, current injection on an analog input may cause errors in adjacent analog channels. The expected injection currents are typically specified in the recommended operating conditions of a device data sheet and are generally in the range of <NUM> to <NUM> mA.

An analog mux is commonly used to provide the multiple input into a single ADC input. It is desirable for the analog mux to be able to handle the injected current when disabled. In addition, it is desirable for the analog mux to generate as low as possible leakage current and noise coupling as highly accurate ADCs are commonly required in processing systems, such as microcontrollers and microprocessors embodied in systems on a chip.

<CIT> discloses a switch means designed as an integrated circuit which possesses two series-connected FETs (Q1P, Q2P; Q1N, Q2N) whose common switching point (N5, N6) is clamped via a clamp FET (Q3N, Q3P) to a reference potential. The conductivity type of the clamp FET (Q3N, Q3P) is opposite the conductivity type of the two series-connected FETs (Q1P, Q2P; Q1N, Q2N). In the case of an n-channel clamp FET (Q3N), the latter is connected to negative potential. In the case of a p-channel clamp FET (Q3P), it is connected to positive potential.

Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements.

Embodiments of analog multiplexers (anamux) disclosed herein function with low leakage and low noise coupling. Both positive and negative current injection are handled by using contesting well biasing even in branches of the anamux that are disabled. The contesting well biasing can be applied to harden both N-type and P-type devices from the effects of current injection. The contesting well biasing provides extra capability to discharge injected current in N-type devices and source the injected circuit in P-type devices while keeping the N-type and P-type hardening devices size relatively small.

<FIG> illustrates a simplified block diagram of an embodiment of input circuit <NUM> that includes anamux <NUM> coupled to an analog to digital converter (ADC) <NUM>. Anamux <NUM> can includes one or more input branches <NUM>, <NUM>, <NUM>, shown as IN0, IN1,. Each input branch <NUM>-<NUM> can be enabled one at a time by an indexed enable signal, en(i), independently from the other input branches. When a particular input branch <NUM>-<NUM> is enabled, the output from the enabled branch <NUM>-<NUM> is provided as input to ADC <NUM>.

ADC <NUM> is an integrated circuit that converts analog signals to digital signals. The digital signals can then be used by a digital processing system (not shown) that performs various processing functions in devices such as cellular phones, laptop computers, desktop computers, tablet computers, gaming systems, industrial control systems for robotics, temperature control, electric grid control, hydroelectrical control, automotive processors for advanced driver assistance systems, infotainment, connectivity, powertrain, braking, car body, driver controls, aircraft, appliances, and many other applications where embedded and non-embedded processing devices may be used.

ADC <NUM> can be implemented in various architectures such as successive approximation, sigma-delta, or pipeline, among others, and may be selected based on type of application or use, speed, accuracy, linearity, resolution, power supply voltage, and/or other parameters and performance factors.

<FIG> illustrates a simplified block diagram of an embodiment of a first branch <NUM> of anamux <NUM> in <FIG> that includes P-type transistors <NUM>, <NUM> and N-type transistors <NUM>, <NUM> that behave as transmission gates between input pad <NUM> and output pad <NUM>. Anamux branch <NUM> further includes protection circuits <NUM>, <NUM> that are used when anamux branch <NUM> is not enabled to either dissipate positive injection current or source negative injection current, thereby preventing the injection current from affecting operation of ADC <NUM> (<FIG>). When anamux branch <NUM> is enabled, protection circuits <NUM>, <NUM> do not operate, and input from anamux branch <NUM> is conducted from input pad <NUM> to outpad <NUM>.

P-type transistor <NUM> includes a first current electrode coupled to input pad <NUM>, a second current electrode coupled to a net that includes nodes A and B and to a first current electrode of P-type transistor <NUM>. A second current electrode of P-type transistor <NUM> is coupled to output pad <NUM>. Control gates of P-type transistors <NUM>, <NUM> are coupled to one another and to a complement of an enable signal shown as ENb(<NUM>) for anamux branch <NUM>. Other anamux branches <NUM>, <NUM> will be coupled to their own respective complement of the enable signal.

N-type transistor <NUM> includes a first current electrode coupled to input pad <NUM>, a second current electrode coupled to a net that includes nodes C and D, and a first current electrode of N-type transistor <NUM>. A second current electrode of N-type transistor <NUM> is coupled to output pad <NUM>. Control gates of N-type transistors <NUM>, <NUM> are coupled to one another and to enable signal shown as EN(<NUM>) for anamux branch <NUM>. Other anamux branches <NUM>, <NUM> will be coupled to their own respective enable signal.

Protection circuit <NUM> includes N-type transistor <NUM> including a first current electrode coupled to node A, a second current electrode coupled to ground <NUM>, and a control electrode coupled to the complement of the enable signal. P-type transistor <NUM> and N-type transistor <NUM> form transmission gate <NUM>. P-type transistor <NUM> includes a first current electrode coupled to a first current electrode of N-type transistor <NUM> and a second current electrode coupled to a second current electrode of N-type transistor <NUM>. The control electrode of P-type transistor <NUM> is coupled to the enable signal EN(<NUM>) and the control electrode of N-type transistor <NUM> is coupled to the complement of the enable signal ENb(<NUM>). The first current electrodes of P-type transistor <NUM> and N-type transistor <NUM> are further coupled to a body of N-type transistor <NUM>. The second current electrodes of P-type transistor <NUM> and N-type transistor <NUM> are further coupled to nodes A and B, the second current electrode of P-type transistor <NUM> and the first current electrode of P-type transistor <NUM>.

N-type transistor <NUM> includes a first current electrode coupled to the body electrode of N-type transistor <NUM> and the first current electrodes of P-type transistor <NUM> and N-type transistor <NUM>. N-type transistor <NUM> further includes a second current electrode coupled to ground <NUM> and a control electrode coupled to a supply voltage VDDA.

Protection circuit <NUM> includes P-type transistor <NUM> including a first current electrode coupled to node D, a second current electrode coupled to supply voltage VDDA, and a control electrode coupled to the enable signal EN(<NUM>). P-type transistor <NUM> and N-type transistor <NUM> form transmission gate <NUM>. P-type transistor <NUM> includes a first current electrode coupled to a first current electrode of N-type transistor <NUM> and a second current electrode coupled to a second current electrode of N-type transistor <NUM>. The control electrode of P-type transistor <NUM> is coupled to the enable signal EN(<NUM>) and the control electrode of N-type transistor <NUM> is coupled to the complement of the enable signal ENb(<NUM>). The first current electrodes of P-type transistor <NUM> and N-type transistor <NUM> are further coupled to a body electrode of P-type transistor <NUM>. The second current electrodes of P-type transistor <NUM> and N-type transistor <NUM> are further coupled to nodes C and D, the second current electrode of N-type transistor <NUM>, and the first current electrode of N-type transistor <NUM>.

P-type transistor <NUM> includes a first current electrode coupled to the body electrode of P-type transistor <NUM> and the first current electrodes of P-type transistor <NUM> and N-type transistor <NUM>. P-type transistor <NUM> further includes a second current electrode coupled to supply voltage VDDA <NUM> and a control electrode coupled to ground.

N-type transistor <NUM> and P-type transistor <NUM> may be referred to as "hardening transistors" that are used to dissipate or source current injection. During operation of anamux <NUM> (<FIG>), when anamux branch <NUM> is enabled (EN(<NUM>) is asserted and ENb(<NUM>) is deasserted), transmission gates <NUM>, <NUM> are off. The body electrode of N-type transistor <NUM> is tied to ground <NUM> by N-type transistor <NUM>. The body electrode of P-type transistor <NUM> is tied to VDDA by P-type transistor <NUM> being in conductive mode. Both N-type transistor <NUM> and P-type transistor <NUM> will be off. There is no current injection from anamux branch <NUM> in normal ADC conversion when anamux branch <NUM> is enabled. Transmission gates <NUM>, <NUM> and transistors <NUM>, <NUM>, allow the size of transistors <NUM>, <NUM> to be smaller than would otherwise be needed to remove injection current when anamux branch <NUM> is not enabled. The smaller transistors <NUM>, <NUM> produce lower leakage current, which improves the accuracy ADC <NUM>.

In the current injection mode, anamux branch <NUM> is not enabled (EN(<NUM>) is deasserted and ENb(<NUM>) is asserted) and transmission gates <NUM>, <NUM> are on. The body electrode of hardening N-type transistor <NUM> is still tied to ground by the N-type transistor <NUM>, and is also connected to node A, which is pulled to ground by N-type transistor <NUM>. The body electrode of hardening P-type transistor <NUM> is still tied to supply voltage VDDA by P-type transistor <NUM> and is also coupled to node D, which is pulled to VDDA by P-type transistor <NUM>.

During the positive current injection, the input voltage is diode voltage (for example, <NUM>-<NUM>. 8V) above the supply voltage VDDA. The injected current will be discharged to ground through P-type transistor <NUM> and N-type transistor <NUM>. Due to the small size of N-type transistor <NUM>, node A will be charged to above ground, as a result the threshold voltage of N-type transistor <NUM> will be reduced due to the body bias effect from transmission gate <NUM>, and N-type transistor <NUM> is able to handle more channel current. However, the size of N-type transistor <NUM> may not be able to handle the injected current. Even with threshold voltage shift, node A will rise further, and once node A is above the diode voltage, a body-source diode of N-type transistor <NUM> starts conducting and is able to discharge the rest of the injected current.

Once the injected current dissipates, the body of the N-type transistor <NUM> will be pulled back to ground by the always on N-type transistor <NUM>. Accordingly, the 'contesting well biasing' structure is able to handle the injected current. Additionally, the leakage is low due to the small size of N-type transistors <NUM>, <NUM> and transmission gate <NUM>.

During negative current injection, the input voltage can be diode voltage (<NUM>-<NUM>. 8V) below ground <NUM>. The injected negative current can be sourced from supply voltage VDDA through N-type transistor <NUM> and P-type transistor <NUM>. Due to the small size of P-type transistor <NUM>, node D will be discharged to below supply voltage VDDA. As a result, the threshold voltage of P-type transistor <NUM> will be reduced due to the body bias effect, and P-type transistor <NUM> is able to handle more channel current. The size of P-type transistor <NUM> may not be able to handle the full amount of current injected even with threshold voltage shift. To overcome this possibility, node D will fall further once the diode voltage of node D falls below supply voltage VDDA. At this point, the source-body diode of P-type transistor <NUM> will start to conduct and source the rest of injected current. Once the injected current dissipates, the body of the P-type transistor <NUM> will be pulled back to supply voltage VDDA by the always-on P-type transistor <NUM>. Hence the 'contesting well biasing' structure is able to handle the full amount of negative injected current. Additionally, leakage current is low due to the small size of transistors <NUM>, <NUM> and <NUM> in protection circuit <NUM>.

<FIG> illustrates a block diagram of an embodiment of a processing system in which the analog multiplexer (anamux) <NUM> and analog to digital converter (ADC) <NUM> of <FIG> can be utilized. While processing system <NUM> is provided as an example of the use of anamux <NUM> and ADC <NUM>, anamux <NUM> and ADC <NUM> may be used in processing systems with other architectures and for other purposes.

Processing system <NUM> can include hypervisor <NUM>, and master device <NUM> with two or more processors allocated to virtual machines <NUM>, <NUM>, <NUM>, <NUM>. Each virtual machine <NUM>-<NUM> can include all or at least a portion of one or more processor in processor elements <NUM>, memory devices <NUM> to store bootup and application software <NUM> and input/output circuitry <NUM>. Other components may be included in processing system <NUM>.

Remote peripherals <NUM> are coupled to interconnect <NUM>. Each peripheral device may be assigned to a domain identifier as a member of a peripheral device subgroup <NUM>-<NUM>, according to the domain in virtual machines <NUM>-<NUM> with which remote peripheral devices <NUM> are associated. Domain assignments for components in virtual machines <NUM>-<NUM> and remote peripheral devices <NUM> can be stored in memory <NUM> in one or more files for domain configuration information (not shown).

Parameters that can be communicated between master device <NUM> and remote peripherals <NUM> can include domain identifiers, peripheral addresses, and access attributes such as secure/nonsecure and privileged/nonprivileged attributes, requests for data or other information, responses to requests, among others. Interconnect <NUM> also routes requests and responses between virtual machines <NUM>-<NUM> and remote peripherals <NUM>.

Hypervisor <NUM> can create one or more virtual machines <NUM>-<NUM> in processing system <NUM>. Virtual machines <NUM>-<NUM> are private execution environments run by hypervisor <NUM> and are referred to as domains, each of which can run a different operating system simultaneously on processing system <NUM>. Hypervisor <NUM> can be implemented in hardware or in software that runs directly on hardware resources such as processor elements <NUM>, memory <NUM>, and input/output (I/O) interface circuitry <NUM>. One of virtual machines <NUM>-<NUM> may be a control domain that runs a full instance of an operating system and the other domains may run a full instance of an operating system that may be different from the operating system running on the control domain or the other guest domains. Hypervisor <NUM> partitions, shares, manages, and monitors the hardware resources and acts as an interface between the hardware resources and the domains. As such, hypervisor <NUM> performs the low-level operations required to provide a virtualized platform. The control domain can perform all other tasks. For example, the control domain can determine which guest domains are created, which resources each guest domain can access, and how much memory is allocated to each guest domain. An example of a commercially available product that can be used for hypervisor <NUM> is the COQOS Hypervisor by OpenSynergy, Inc. in San Diego, California, USA. Other suitable hypervisor products can be used, however.

Hypervisor <NUM> can include a scheduler that schedules domains onto processor elements <NUM>. Each domain, including the control domain, includes one or more virtual processors that it owns and does not share with other domains. Hypervisor <NUM> may be integrated with a bootloader or work in conjunction with the bootloader to help create the virtual machines <NUM>-<NUM> during boot. The system firmware (not shown) can start the bootloader using a first processor element. The bootloader can load the domain configuration information, kernel images and device trees from a boot partition in memory <NUM> for virtual machines <NUM>-<NUM>.

Once hypervisor <NUM> configures the virtual machines <NUM>-<NUM>, hypervisor <NUM> can then switch to a hypervisor mode, initialize hypervisor registers, and hand control over to a guest kernel. On the control core, hypervisor <NUM> can then do the same for the guest that will run on the control core (i.e., initialize the data structures for the guest, switch to the hypervisor mode, initialize hypervisor registers, and hand off control to the guest kernel). After bootup, the distinction between a primary core and a secondary core may be ignored and hypervisor <NUM> may treat the two cores equally.

Master device <NUM> may be implemented using a system on a chip (SoC) that includes multiple processing cores, referred to as a multi-core processor. For example. , master device <NUM> can be implemented using a system-on-a-chip with an ARM architecture or any other architecture. In other embodiments, master device <NUM> may include a multi-core processor that is not a system-on-a-chip to provide the same or a similar environment. For example, a multi-core processor may be a general computing multi-core processor on a motherboard supporting multiple processing cores. In further embodiments, master device <NUM> may be implemented using a plurality of networked processing cores. In one embodiment, master device <NUM> may be implemented using a cloud computing architecture or other distributed computing architecture.

Processor elements <NUM> are virtualized elements that can each include one or more processing cores to perform calculations and general processing tasks, run application software <NUM>, manage I/O interfaces <NUM>, run operating systems, etc. Note that a single processing core can be shared among virtual machines <NUM>-<NUM>, and each virtual machine <NUM>-<NUM> can use more than one processing core.

Domains associated with virtual machines <NUM>-<NUM> can be configured for various purposes. For example, in an automobile, domain <NUM> may be used for a powertrain controller for remote peripherals that can include an engine, transmission, brakes, battery management system, steering, airbags, and suspension. Domain <NUM> may be used for a body controller for remote peripherals that can include HVAC, mirrors, interior lighting, doors, sears, steering wheel, sunroof, and windshield wipers. Domain <NUM> may be used for a cockpit controller for remote peripherals that can include touch displays and voice recognition amplifiers. Domain <NUM> may be used for a connectivity controller for remote peripherals that can include vehicle-to-everything, broadcast radio, cellular, WiFi, Bluetooth, near field communication, and smart car access components. Other domains and functionality can be implemented in processing system <NUM> for other purposes, with automotive domains being just one example.

In various embodiments, any number and/or type of domains may be supported (e.g., two domains, three domains, five domains, eight domains,. sixteen domains, etc.) in addition to or in place of the four domains enumerated herein. In selected embodiments, two or more different operating system environments are provided (e.g., one for each of the domains). Each of the operating system environments may be dedicated to different cores (or multiple cores) of a multi-core system-on-a-chip (SoC). Any number and/or type of operating environments may be provided, and may be used for devices and equipment other than automobiles.

Memory devices <NUM> can include one or more random access memory (RAM) devices, such as double data rate (DDR) RAM module, quad serial peripheral interface (QUADSPI) memory, system on-chip RAM modules, graphics on-chip RAM module, boot read only memory (ROM) module, and other suitable memory devices.

Application software <NUM> can be stored in memory <NUM> that is internal to an SoC, or in a memory device external to master device <NUM> and loaded into internal memory devices <NUM> during startup. Various types of application software <NUM> can be used, depending on the functions to be provided by processing system <NUM>. Using the automotive example described above, application software <NUM> can include various controllers for remote peripheral devices <NUM>, such as the powertrain domain controller, body domain controller, cockpit domain controller and connectivity domain controller. Other types of application software <NUM> can be used in addition to or instead of application software <NUM> related to automotive domains.

Input/output (I/O) circuitry <NUM> provides a connection between virtual machines <NUM>-<NUM> and remote peripheral devices <NUM>. I/O pins (not shown) are driven by pad drivers that provide for logic level translation, protection against potentially damaging static charges, and amplification of the internal signals to provide sufficient current drive to be useful outside master device <NUM>. I/O circuitry <NUM> typically includes pads or pins connected to respective input pullup devices, electrostatic discharge protection, input buffers, level shifters, output drivers, and output pulldown devices. anamux <NUM> and ADC <NUM> can be included in I/O circuitry <NUM> to receive analog data from remote peripherals <NUM> and convert the analog data to digital data that may then be processed by processor elements <NUM> and stored in memory <NUM>. Other components can be included in I/O circuitry <NUM>.

I/O circuitry <NUM> can be coupled to interconnect <NUM> either directly or through a network interface card (not shown). The connection between I/O circuitry <NUM>, interconnect <NUM>, and domain access control <NUM> can be wired or wireless. Any suitable interconnect technology can be used. For wired networks, an example of a suitable interconnect technology is Ethernet that allows multiple virtual machines <NUM>-<NUM> to communicate with remote peripheral devices <NUM> and may be implemented using Ethernet cables plugged into an Ethernet switch, router, hub, network bridge, etc. Messages sent to and from interconnect <NUM> can adhere to a protocol suitable for the interconnect technology being used. When using Ethernet, for example, a stream of data can be divided into frames or packets, also referred to as messages, that each include source and destination addresses, a payload, and error checking so damaged frames can be discarded and replacements retransmitted.

One or more remote peripheral devices <NUM> may send data to or receive data from portable media devices, data storage devices, servers, mobile phones, radios for AM, FM and digital or satellite broadcast, etc. which are connected through connector hardware such as a one or more USB connectors, firewire connectors, lightning connectors, wireless communications connections for data transfer using infrared communication, Bluetooth communication, ZigBee communication, Wi-Fi communication, communication over a local area network and/or wireless local area network, etc..

For automotive applications, for example, one or more remote peripheral devices <NUM> may be connected to one or more Local Interconnect Networks (LIN) and/or Controller Area Networks (CAN) to allow communication between vehicle components. Vehicle sensors may be included in remote peripheral devices <NUM> such as one or more of gyroscopes, accelerometers, three dimensional accelerometers, inclinometers, thermometers, etc. Other remote peripheral devices <NUM> may be used, in addition to, or instead of, the remote peripherals devices <NUM> described herein.

By now it should be appreciated that for processing systems and integrated circuitry that use multiple I/O inputs multiplexed into a single ADC channel, anamux <NUM> can be used to support the mux function with smaller devices and lower leakage current than previously possible. For example, if an ADC channel specifies a +/-3mA current injection, the MOS transistors may be turned on/conduct earlier than ESD bipolar devices at sub +/-3mA current injection, due to the lower threshold voltage of I/O circuits. In previous system, the hardening transistors in the anamux had to be large to discharge the injected current. The MOS drivers in the I/O cell could also help discharge over <NUM>% of injection current, but the analog input pad for devices being developed may not include MOS output drivers. Hence the injected current is ideally fully discharged by anamux <NUM>. Yet there are limitations on how large the size of hardening devices in the anamux can be increased without reducing the accuracy required by ADC <NUM>. Embodiments of anamux <NUM> with protection circuits <NUM>, <NUM> provide a novel contesting well biasing configuration to discharge the injected current without increasing leakage current.

In some embodiments, an analog multiplexer (MUX) can comprise a plurality of branch circuits, each branch circuit configured to receive a corresponding input signal and provide a corresponding output signal. A multiplexer (MUX) output can be coupled to the plurality of branch circuits, wherein the MUX output is configured to provide the corresponding output signal provided by a selected branch circuit of the plurality of branch circuits as a MUX output signal, each branch circuit of the plurality of branch circuits comprising a first transistor of a first conductivity type having a first current electrode configured to receive the corresponding input signal for the branch circuit, a second current electrode coupled to a circuit node, and a control electrode; a second transistor of the first conductivity type having a first current electrode coupled to the circuit node, a second current electrode configured to provide the corresponding output signal, and a control electrode; a third transistor of a second conductivity type, opposite the first conductivity type, having a first current electrode coupled to the circuit node, a second current electrode coupled to a first voltage supply terminal, and a control electrode, wherein the branch circuit is configured to turn on the third transistor and turn off the first and second transistors when the branch circuit is not selected, and the branch circuit is configured to turn off the third transistor and turn on the first and second transistors when the branch circuit is selected; and a switch circuit coupled between a body electrode of the third transistor and the circuit node, wherein the switch circuit is configured to be conductive when the branch circuit is not selected and non-conductive when the branch circuit is selected.

In other aspects, the analog MUX can further comprise a fourth transistor of the second conductivity type having a first current electrode coupled to the body electrode of the third transistor, a control electrode coupled to a second voltage supply terminal different from the first voltage supply terminal, and a second current electrode coupled to the first voltage supply terminal.

In another aspect, in each branch circuit of the plurality of branch circuits: control electrodes of the first, second, and third transistors can each be coupled to receive an enable signal which is asserted when the branch circuit is selected, and negated when the branch circuit is not selected.

In another aspect, the first conductivity type is N-type, and the first voltage supply terminal provides a first supply voltage that is greater than a second supply voltage provided by the second voltage supply terminal.

In another aspect, the enable signal can be implemented as an active high signal such that it is asserted to a logic level high when the branch circuit is selected and negated to a logic level low when the branch circuit is not selected.

In another aspect, the first conductivity type is P-type, and the first voltage supply terminal provides a first supply voltage that is less than a second supply voltage provided by the second voltage supply terminal.

In another aspect, the enable signal is implemented as an active low signal such that it is asserted to a logic level low when the branch circuit is selected and negated to a logic level high when the branch circuit is not selected.

In another aspect, the switch circuit can comprise a fourth transistor of a third conductivity type having a first current electrode coupled to the body electrode of the third transistor, a second electrode coupled to the circuit node, and a control electrode coupled to receive the enable signal; and a fifth transistor of a fourth conductivity type, opposite the third conductivity type, having a first current electrode coupled to the body electrode of the third transistor, a second electrode coupled to the circuit node, and a control electrode to receive an inverse of the enable signal.

In another aspect, the corresponding input signals, the corresponding output signals, and the MUX output signal can be analog signals.

In another aspect, each branch circuit of the plurality of branch circuits can further comprise: a fourth transistor of the second conductivity type having a first current electrode coupled to receive the corresponding input signal for the branch circuit, a second current electrode coupled to a second circuit node, and a control electrode; and a fifth transistor of the second conductivity type having a first current electrode coupled to the second circuit node, a second current electrode coupled to provide the corresponding output signal, and a control electrode; a sixth transistor of the first conductivity type having a first current electrode coupled to the second circuit node, a second current electrode coupled to the second voltage supply terminal, and a control electrode. The branch circuit can be configured to turn on the sixth transistor and turn off the fourth and fifth transistors when the branch circuit is not selected, and the branch circuit is configured to turn off the sixth transistor and turn on the fourth and fifth transistors when the branch circuit is selected, and a second switch circuit coupled between a body electrode of the sixth transistor and the second circuit node, wherein the second switch circuit is configured to be conductive when the branch circuit is not selected and non-conductive when the branch circuit is selected.

In another aspect, the analog MUX of claim <NUM> can further comprise a seventh transistor of the first conductivity type having a first current electrode coupled to the body electrode of the sixth transistor, a control electrode coupled to the first voltage supply terminal, and a second current electrode coupled to the second voltage supply terminal.

In another aspect, in each branch circuit of the plurality of branch circuits: control electrodes of the first, second, and third transistors can each be coupled to receive an enable signal which is asserted when the branch circuit is selected, and negated when the branch circuit is not selected; and control electrodes of the fourth, fifth, and sixth transistors are each coupled to receive an inverse of the enable signal.

In other embodiments, a processing system can comprise a processing element; a memory device coupled to the processing element; an input/output (I/O) circuit coupled to the processing element, the I/O circuit including an analog multiplexer, the analog multiplexer including: a plurality of branch circuits, each branch circuit configured to receive a corresponding input signal and provide a corresponding output signal; and a multiplexer output coupled to the plurality of branch circuits. The MUX output can be configured to provide the corresponding output signal provided by a selected branch circuit of the plurality of branch circuits as a MUX output signal, each branch circuit of the plurality of branch circuits can comprise: a first transistor of a first conductivity type having a first current electrode configured to receive the corresponding input signal for the branch circuit, a second current electrode coupled to a circuit node, and a control electrode, a second transistor of the first conductivity type having a first current electrode coupled to the circuit node, a second current electrode configured to provide the corresponding output signal, and a control electrode, a third transistor of a second conductivity type, opposite the first conductivity type, having a first current electrode coupled to the circuit node, a second current electrode coupled to a first voltage supply terminal, and a control electrode. The control electrodes of the first, second, and third transistors can each be coupled to receive an enable signal which is asserted when the branch circuit is selected, and negated when the branch circuit is not selected. The analog multiplexer can further include a fourth transistor of the second conductivity type having a first current electrode coupled to the body electrode of the third transistor, a control electrode coupled to a second voltage supply terminal different from the first voltage supply terminal, and a second current electrode coupled to the first voltage supply terminal, and a switch circuit coupled between a body electrode of the third transistor and the circuit node, wherein the switch circuit is configured to be conductive when the enable signal is negated and non-conductive when the enable signal is asserted.

In other aspects, the switch circuit can comprise a fifth transistor of a third conductivity type having a first current electrode coupled to the body electrode of the third transistor, a second electrode coupled to the circuit node, and a control electrode coupled to receive the enable signal; and a sixth transistor of the fourth conductivity type, opposite the third conductivity type, having a first current electrode coupled to the body electrode of the third transistor, a second electrode coupled to the circuit node, and a control electrode to receive an inverse of the enable signal.

In further embodiments, an integrated circuit device can comprise an analog multiplexer including plurality of branch circuits, each branch circuit can be configured to receive a corresponding input signal and provide a corresponding output signal; and a multiplexer (MUX) output coupled to the plurality of branch circuits. The MUX output can be configured to provide the corresponding output signal provided by a selected branch circuit of the plurality of branch circuits as a MUX output signal, each branch circuit of the plurality of branch circuits can comprise a pair of n-type transistors connected in series between the corresponding input and the corresponding output of the branch circuit, via a first circuit node, wherein control electrodes of each of the pair of n-type transistors can be coupled to receive an enable signal which is asserted when the branch circuit is selected and negated when the branch circuit is not selected. A first p-type transistor can be coupled between the first circuit node and a first voltage supply terminal, wherein a control electrode of the first p-type transistor is coupled to receive the enable signal. A first switch circuit can be coupled between the first circuit node and a body electrode of the first p-type transistor, wherein the switch circuit is configured to be conductive when the enable signal is negated and non-conductive when the enable signal is asserted. A pair of p-type transistors can be connected in series between the corresponding input and the corresponding output of the branch circuit, via a second circuit node, wherein control electrodes of each of the pair of p-type transistors are coupled to receive an inverse of the enable signa. A first n-type transistor can be coupled between the second circuit node and a second voltage supply terminal, wherein a control electrode of the first n-type transistor is coupled to receive the inverse of the enable signal. A second switch circuit can be coupled between the second circuit node and a body electrode of the first n-type transistor, wherein the switch circuit is configured to be conductive when the enable signal is negated and non-conductive when the enable signal is asserted.

In other aspects, the integrated circuit device can further comprise a second p-type transistor coupled between the body electrode of the first p-type transistor and the first voltage supply terminal and having a control electrode coupled to a second voltage supply terminal, wherein the first voltage supply terminal is configured to provide a first supply voltage and the second voltage supply terminal is configured to provide a second supply voltage that is less than the first supply voltage; and a second n-type transistor coupled between the body electrode of the first n-type transistor and the second voltage supply terminal and having a control electrode coupled to the first voltage supply terminal.

In another aspect, the first switch circuit can comprise a third p-type transistor coupled between the first circuit node and the body electrode of the first p-type transistor and having a control electrode coupled to receive the enable signal; and a third n-type transistor coupled in parallel with the second p-type transistor between the first circuit node and the body electrode of the first p-type transistor, and having a control electrode coupled to receive the inverse of the enable signal.

In another aspect, the second switch circuit can comprise a fourth p-type transistor coupled between the second circuit node and the body electrode of the first n-type transistor and having a control electrode coupled to receive the enable signal; and a fourth n-type transistor coupled in parallel with the third p-type transistor between the second circuit node and the body electrode of the first n-type transistor, and having a control electrode coupled to receive the inverse of the enable signal.

In another aspect, the enable signal is implemented as an active high signal such that it is asserted to a logic level high when the branch circuit is selected and negated to a logic level low when the branch circuit is not selected.

In another aspect, the MUX output signal is provided to an analog to digital converter (ADC).

A multi-branch analog multiplexer (anamux) includes protection circuitry to help dissipate both positive and negative injected current without increasing the size of hardening transistors in each branch, thereby avoiding increased leakage current and enabling an analog to digital converter to operate with the required accuracy. The protection circuitry is tied to the body of the hardening transistor to lower the threshold voltage of the hardening device, thereby enabling the hardening device to handle more of the injected current.

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. Also, plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.

Although specific conductivity types or polarity of potentials have been described in the examples, it will be appreciated that conductivity types and polarities of potentials maybe reversed.

Any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

Claim 1:
An analog multiplexer, MUX (<NUM>), comprising:
a plurality of branch circuits (<NUM>, <NUM>, <NUM>), each branch circuit configured to receive a corresponding input signal and provide a corresponding output signal; and
a multiplexer, MUX, output coupled to the plurality of branch circuits (<NUM>, <NUM>, <NUM>), wherein the MUX output is configured to provide the corresponding output signal provided by a selected branch circuit of the plurality of branch circuits as a MUX output signal, each branch circuit of the plurality of branch circuits (<NUM>, <NUM>, <NUM>) comprising:
a first transistor (<NUM>) of a first conductivity type having a first current electrode configured to receive the corresponding input signal for the branch circuit, a second current electrode coupled to a circuit node, and a control electrode,
a second transistor (<NUM>) of the first conductivity type having a first current electrode coupled to the circuit node, a second current electrode configured to provide the corresponding output signal, and a control electrode,
a third transistor (<NUM>) of a second conductivity type, opposite the first conductivity type, having a first current electrode coupled to the circuit node, a second current electrode coupled to a first voltage supply terminal (<NUM>), and a control electrode, wherein the branch circuit is configured to turn on the third transistor (<NUM>) and turn off the first (<NUM>) and second (<NUM>) transistors when the branch circuit is not selected, and the branch circuit is configured to turn off the third transistor (<NUM>) and turn on the first (<NUM>) and second (<NUM>) transistors when the branch circuit is selected,
a switch circuit (<NUM>) coupled between a body electrode of the third transistor (<NUM>) and the circuit node, wherein the switch circuit (<NUM>) is configured to be conductive when the branch circuit is not selected and non-conductive when the branch circuit is selected, a fourth transistor (<NUM>) of the second conductivity type having a first current electrode coupled to the body electrode of the third transistor (<NUM>), a control electrode coupled to a second voltage supply terminal (<NUM>) different from the first voltage supply terminal (<NUM>), and a second current electrode coupled to the first voltage supply terminal (<NUM>).