Patent Description:
An organic light-emitting diode (OLED) display panel includes an array substrate. An array substrate includes a substrate, and a plurality of pixel regions disposed over the substrate and arranged in an array. Each pixel region includes an OLED, and a pixel circuit for controlling the OLED such that the OLED emits light.

In a pixel region, the pixel circuit may include a switching transistor and a driving transistor coupled to a control integrated circuit (IC). To turn on the OLED in the pixel region to emit light, the control IC can input turn-on voltages to the switching transistor and the driving transistor, thereby turning on the switching transistor and the driving transistor. Further, the control IC can input a driving voltage to a source electrode of the driving transistor, and the driving transistor can input a driving current to the OLED according to the driving voltage. As a result, the OLED emits light under an influence of the driving current. The driving current of a driving transistor is related to the threshold voltage of the driving transistor. Thus, when two driving transistors have different threshold voltages, the two driving transistors may provide different driving currents under the same driving voltage.

<CIT> discloses a device having a first transistor and a second transistor wherein a channel length direction of the first transistor extends along a first direction and a channel length direction of the second transistor extends along a second direction intersecting the first direction, and the second transistor is formed on a same substrate as the first transistor. A first channel region and a second channel region are formed in semiconductor layers which are simultaneously formed and a mobility of the semiconductor film has an anisotropy in the first and second directions. With this structure, transistors having different mobilities can be obtained while using the semiconductor films formed on the same substrate and from a same material.

<CIT> discloses a method for fabricating organic electroluminescent devices. The method comprises providing a substrate divided into first and second regions, forming an amorphous silicon layer on the substrate, forming a protection film on the amorphous silicon layer within the second region, performing an excimer laser annealing process on the amorphous silicon layer for converting it to a polysilicon layer, removing the protection film, patterning the polysilicon layer, thus a first patterned polysilicon layer in the first region and a second patterned polysilicon layer in the second region are formed. A resultant organic electroluminescent device is obtained. Specifically, the grain size of the first patterned polysilicon layer is large than that of the second patterned polysilicon layer.

It is an object of the present invention to provide a method for fabricating an array substrate.

The object is achieved by the features of the independent claim <NUM>.

<FIG> illustrates a schematic view of an exemplary array substrate <NUM>. As shown in <FIG>, the array substrate <NUM> includes a pixel circuit and an organic light-emitting diode (OLED) <NUM> (one electrode of the OLED <NUM> is shown in <FIG>). The pixel circuit includes a driving transistor and a switching transistor.

The driving transistor includes a first active medium A1, and the switching transistor includes a second active medium A2. Both the first active medium A1 and the second active medium A2 may be polysilicon. The grain size of the first active medium Al may be smaller than the grain size of the second active medium A2, where the grain size of the first active medium Al refers to the size of the grains in the first active medium, and the grain size of the second active medium A2 refers to the size of the grains in the second active medium.

In the array substrate, both the first active medium in the driving transistor and the second active medium in the switching transistor may be polysilicon. In addition, the first active medium may have a smaller grain size than the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor is smaller than the standard size. Further, a smaller grain size in the driving transistors can result in a less significant non-uniformity of the threshold voltages in the driving transistors caused by the non-uniform grain sizes. As a result, the driving currents inputted to OLEDs from driving transistors of the OLED display panel may tend to be the same. Accordingly, the brightness of the light emitted from each pixel region may tend to be the same, and the display performance of the OLED display panel can be improved.

The polysilicon may be low temperature polysilicon.

<FIG> illustrates schematic views showing two exemplary grain sizes. As shown in <FIG>, the grain size of polysilicon <NUM> is larger and hence less uniform, and the grain size of polysilicon <NUM> is smaller and hence more uniform.

As shown in <FIG>, the driving transistor further includes a first gate electrode B1, first source/drain electrodes C1 (i.e. a first source electrode and a first drain electrode), and a first gate insulating block D1. The switching transistor includes a second gate electrode B2, second source/drain electrodes C2 (i.e. a second source electrode and a second drain electrode), and a second gate insulating block D2. In addition, the first gate insulating block D1 has a greater thickness than the second gate insulating block D2. A thicker gate insulating block in a transistor can result in a larger subthreshold swing (SS) coefficient of the transistor. In various application scenarios, in order to effectively control the gray scale, the driving transistor may need to have a greater SS coefficient than the switching transistor. Thus, the thickness of the first gate insulating block D1 in the driving transistor may be set to be greater than the thickness of the second gate insulating block D2 in the switching transistor. For example, as shown in <FIG>, a thickness H1 of the gate insulating block D1 below the first gate electrode B1 is greater than a thickness H2 of the gate insulating block D2 below the second gate electrode B2.

As shown in <FIG>, the array substrate <NUM> further includes an interlayer insulating layer <NUM>. The first source/drain electrodes C1 are coupled to the first active medium A1 through via holes in the interlayer insulating layer <NUM>. The second source/drain electrodes C2 are coupled to the second active medium A2 through via holes in the interlayer insulating layer <NUM>. A flat layer <NUM> is formed over the first source/drain electrodes C1 and the second source/drain electrodes C2. The OLED <NUM> is formed over the flat layer <NUM>. The OLED <NUM> is coupled to the pixel circuit through a via hole in the flat layer <NUM>.

Further, the array substrate <NUM> includes a substrate <NUM> and a buffer layer <NUM> disposed over the substrate <NUM>. The pixel circuit is disposed over the substrate <NUM> over which the buffer layer <NUM> has been disposed. That is, prior to fabricating the pixel circuit, the buffer layer <NUM> may be formed over the substrate <NUM> to reduce the influence of impurities, which may be present on the surface of the substrate <NUM>, on the pixel circuit. The OLED <NUM> may be disposed directly on the substrate <NUM>. Alternatively, the OLED <NUM> may be disposed over the buffer layer <NUM> which is above the substrate <NUM>.

The driving current IOLED outputted from the driving transistor to the light-emitting diode may satisfy the formula: IOLED = γ * (Vgs - Vth)<NUM>, where Vgs is a voltage difference between the gate electrode and the source electrode of the driving transistor, Vth is a threshold voltage of the driving transistor, and γ is a coefficient determined by characteristic dimensions and process parameters of the driving transistor. That is, the driving current outputted from the driving transistor may be related to the threshold voltage Vth of the driving transistor, and the driving currents outputted from two driving transistors to OLEDs may be different if the threshold voltages of the two driving transistors are different. The uniformity of threshold voltage of multiple polysilicon transistors may be positively correlated with the uniformity of the grain size of the active medium (polysilicon) in the polysilicon transistors, i.e., a more uniform grain size in the active medium across the multiple polysilicon transistors may result in a more uniform threshold voltage across the multiple polysilicon transistors. Further, the magnitude of the grain size of the polycrystalline silicon may be negatively correlated with the uniformity of the grain size of the polycrystalline silicon. In addition, the magnitude of the grain size of the polycrystalline silicon may also be positively correlated with the magnitude of the on-state current of a transistor. The switching transistor may need to have a relatively large on-state current, and hence may need a relatively large grain size in the active medium.

In a pixel circuit of the conventional technologies, a grain size of an active medium in a switching transistor may be approximately equal to a grain size of an active medium in a driving transistor. The relatively large grain size of the active medium can allow the switching transistor to have a relatively large on-state current, but also may cause the grain size of the active medium in the driving transistor to be relatively non-uniform. Accordingly, the non-uniformity of the grain size of the active medium in the driving transistor may cause a relatively large non-uniformity in threshold voltage.

If the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. In addition, when the grain size is smaller, the grain size may be more uniform. Accordingly, non-uniformity of the threshold voltage of the driving transistors caused by the non-uniformity of the grain size may be less significant. Further, the driving current provided by the driving transistor under a driving voltage may be related to the threshold voltage of the driving transistor. When the threshold voltages of two driving transistors are similar, the driving currents provided by the two driving transistors under the same driving voltages may be similar. Consequently, in the display panel, the driving currents provided by the driving transistors to OLEDs may tend to be the same.

The grain size of the second active medium in the switching transistor consistent with the disclosure may be approximately equal to a grain size of an active medium in a switching transistor in the conventional technologies. Alternatively, the grain size of the second active medium in the switching transistor consistent with the disclosure may not be equal to the grain size of the active medium in the switching transistor in the conventional technologies. The grain size of the second active medium in the switching transistor consistent with the disclosure is not restricted, and may be selected according to various application scenarios. Further, the grain size of the second active medium in the switching transistor does not have to be equal to the grain size of the first active medium. Thus, a second active medium having a relatively large grain size may be selected as needed, thereby ensuring a relatively large on-state current in the switching transistor.

In an array substrate, the first active medium in the driving transistor and the second active medium in the switching transistor may both be polysilicon, and the grain size of the first active medium may be smaller than the grain size of the second active medium. That is, when the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size in the driving transistors is smaller, non-uniformity of threshold voltages in the driving transistors caused by non-uniform grain sizes may be smaller. As a result, in the OLED display panel, driving currents provided by the driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, and the display performance of the OLED display panel may be improved.

The present disclosure provides a driving transistor. The driving transistor may be a driving transistor as shown in <FIG>. As shown in <FIG>, the driving transistor includes the first active medium A1 which can include polysilicon. In addition, the first active medium A1 may have a smaller grain size than the second active medium A2 in the switching transistor formed by polysilicon.

As shown in <FIG>, the driving transistor further includes the first gate electrode B1, the first source/drain electrodes C1 (i.e., the first source electrode and the first drain electrode), and the first gate insulating block D1. The first gate insulating block D1 may have a greater thickness than the second gate insulating block D2 in the switching transistor.

In the driving transistor, the first active medium of the driving transistor may include polysilicon, similar to the second active medium of the switching transistor. Further, the grain size of the first active medium may be smaller than the grain size of the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size is smaller, non-uniformity of the threshold voltages in driving transistors caused by non-uniform grain size may be smaller. As a result, in an OLED display panel including the driving transistors consistent with the disclosure, driving currents provided by the driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, and the display performance of the OLED display panel may be improved.

The present disclosure provides a display panel. <FIG> illustrates a schematic view of an exemplary display panel <NUM>. As shown in <FIG>, the display panel <NUM> includes an array substrate <NUM>. The array substrate <NUM> can be any array substrate, such as the array substrate <NUM> shown in <FIG>. The display panel <NUM> may form a display device, alone or together with one or more other appropriate structures. The display device including the display panel may be an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any suitable product or component having a display function.

In the array substrate of the display panel, the first active medium in the driving transistor and the second active medium in the switching transistor may both be polysilicon. Further, the first active medium may have a smaller grain size than the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size is smaller, non-uniformity of threshold voltages in the driving transistors caused by non-uniform grain size may be smaller. As a result, in the OLED display panel, driving currents provided by driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, thereby improving the display performance of the OLED display panel.

<FIG> illustrates a flow chart of a fabrication method <NUM> for an array substrate according to the present invention. The fabrication method <NUM> for the array substrate will be described with reference to <FIG>.

At <NUM>, a pixel circuit is fabricated.

At <NUM>, an OLED is fabricated. The OLED is coupled to the pixel circuit.

The pixel circuit includes a driving transistor and a switching transistor. The driving transistor includes a first active medium, and the switching transistor includes a second active medium. The first active medium and the second active medium both are polysilicon. The first active medium has a smaller grain size than the second active medium.

In an array substrate fabricated by the fabrication method for an array substrate consistent with the invention, the first active medium in the driving transistor and the second active medium in the switching transistor both are polysilicon, and the first active medium has a smaller grain size than the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor is smaller than the standard size. Further, since the grain size is smaller, non-uniformity of threshold voltages in the driving transistors caused by non-uniform grain sizes is smaller. As a result, in the OLED display panel including the array substrate, driving currents provided by the driving transistors to OLEDs tends to be the same. Accordingly, the brightness of the light emitted from different pixel regions tends to be the same, and the display performance of the OLED display panel can be improved.

<FIG> illustrates a flow chart of another exemplary fabrication method <NUM> for an exemplary array substrate according to various disclosed embodiments of the present invention.

With reference to <FIG>, the exemplary fabrication method <NUM> for the exemplary array substrate will be described in detail.

At <NUM>, a buffer layer is formed over the substrate.

In some embodiments, before the buffer layer is formed, the substrate can be cleaned to minimize impurities on the substrate as much as possible. After the cleaning, a buffer layer <NUM> as shown in <FIG> is formed over the substrate <NUM>. The buffer layer <NUM> is cleaner, containing less impurities. Thus, when a pixel circuit is fabricated over the buffer layer <NUM>, the impurities on the buffer layer may have less influence on the pixel circuit.

Referring again to <FIG>, at <NUM>, an amorphous silicon layer is formed over the substrate over which the buffer layer has been formed.

As shown in <FIG>, after the buffer layer <NUM> is formed over the substrate <NUM>, the pixel circuit can be further fabricated over the buffer layer. For example, an amorphous silicon layer <NUM> is formed over the substrate <NUM> over which the buffer layer <NUM> has been formed. In some embodiments, the amorphous silicon layer <NUM> may have a thickness of approximately <NUM> angstroms.

In some embodiments, the amorphous silicon layer <NUM> may be deposited over the substrate <NUM> by coating, magnetron sputtering, thermal evaporation, plasma enhanced chemical vapor deposition (PECVD), or another appropriate method.

Referring again to <FIG>, at <NUM>, a gate insulating layer is formed over the substrate over which the amorphous silicon layer has been formed.

As shown in <FIG>, after the amorphous silicon layer <NUM> is formed over the substrate <NUM>, a gate insulating layer <NUM> is formed over the substrate <NUM> over which the amorphous silicon layer <NUM> has been formed.

Referring again to <FIG>, at <NUM>, a preset pattern is formed over the substrate over which the gate insulating layer has been formed.

As shown in <FIG>, after the buffer layer <NUM>, the amorphous silicon layer <NUM>, and the gate insulating layer <NUM> are formed over the substrate <NUM>, a preset pattern <NUM> is formed over the substrate <NUM> over which the gate insulating layer has been formed. In addition, an orthogonal projection region of the preset pattern <NUM> on the substrate <NUM> is a preset region X. Because the thickness of the preset pattern <NUM> is non-zero, the absorbance of the preset pattern <NUM> of a laser can be greater than zero.

In some embodiments, the material of the preset pattern <NUM> may include amorphous silicon, the preset pattern <NUM> can be an amorphous silicon pattern, and a thickness of the amorphous silicon pattern can range from approximately <NUM> angstroms to approximately <NUM> angstroms.

When forming the amorphous silicon pattern <NUM>, first, an amorphous silicon material layer can be deposited over the substrate <NUM> by coating, magnetron sputtering, thermal evaporation, PECVD, or another appropriate method and, then, the amorphous silicon material layer can be processed by a patterning process to obtain the amorphous silicon pattern <NUM>. The patterning process may include: photoresist coating, exposure, development, etching, and photoresist peeling. For example, the processing of the amorphous silicon material layer by the patterning process may include: coating a layer of photoresist over the amorphous silicon material layer; exposing the photoresist using a mask to form at least one fully exposed region and at least one non-exposed region; subsequently processing using a development process, such that the photoresist of the at least one fully exposed region is removed and the photoresist of the at least one non-exposed region is retained; etching away the portion of the amorphous silicon material layer corresponding to the at least one fully exposed region; and peeling off the photoresist of the at least one non-exposed region to obtain an amorphous silicon pattern after completing the etching.

Referring again to <FIG>, at <NUM>, the substrate over which the preset pattern has been formed is annealed by laser annealing, such that the amorphous silicon layer can turn into a polysilicon layer.

In some embodiments, as shown in <FIG>, after the preset pattern <NUM> is formed, the substrate <NUM> over which the preset pattern <NUM> has been formed can be annealed by laser annealing, such that the amorphous silicon layer <NUM> formed at <NUM> can turn into a polysilicon layer <NUM> under the influence of laser. In some embodiments, the laser annealing can include excimer laser annealing (ELA).

As shown in <FIG>, the polysilicon layer <NUM> includes a first region Y1 and a second region Y2. An orthogonal projection region of the first region Y1 on the substrate <NUM> may be the preset region X, and an orthogonal projection region of the second region Y2 on the substrate <NUM> may be located outside the preset area X. When performing laser annealing, the preset pattern <NUM> may cover the first region Y1. Thus, the preset pattern <NUM> may be capable of absorbing a portion of the laser that will irradiate the first region Y1. As a result, the first region Y1 may absorb less laser energy, while the second region Y2 may absorb more laser energy. An amorphous silicon region absorbing less laser energy may turn into a polysilicon region having a smaller grain size. Thus, after laser annealing at <NUM>, the first region Y1 may have a smaller grain size than the second region Y2. In various application scenarios, the amount of laser energy absorbed by the first region Y1 may be changed by adjusting the thickness of the preset pattern and thereby changing the extent of laser absorption of the preset pattern. Accordingly, the grain size of the first region Y1 may be changed.

The first active medium in the driving transistor and the second active medium in the switching transistor which need to be formed later can both be located in the polysilicon layer. And an orthogonal projection of the first active medium on the substrate can be located in the preset region, and an orthogonal projection of the second active medium on the substrate can be located outside the preset region.

Referring again to <FIG>, at <NUM>, the preset pattern is removed.

As shown in <FIG>, after the polysilicon layer <NUM> is formed, the preset pattern <NUM> is removed.

According to the invention, a preset etching solution that can etch both the preset pattern <NUM> and the gate insulating layer <NUM> is used to remove the preset pattern <NUM>. That is, the preset etching solution can react chemically with the preset pattern <NUM> and the gate insulating layer <NUM>. When removing the preset pattern <NUM>, the preset etching solution is applied to the substrate <NUM> after laser annealing. As a result, the preset pattern <NUM> is completely removed and, the region in the gate insulating layer <NUM> not covered by the preset pattern <NUM> in <FIG> is thinned to obtain the structure shown in <FIG>.

That is, after the preset pattern <NUM> is removed, as shown in <FIG>, the gate insulating layer <NUM> includes a third region Y3 and a fourth region Y4. An orthogonal projection region of the third region Y3 on the substrate <NUM> may be the preset region X, and an orthogonal projection region of the fourth region Y4 on the substrate may be located outside the preset area X. The thickness H1 of the third region Y3 may be greater than the thickness H2 of the fourth region Y4.

Referring again to <FIG>, at <NUM>, after the preset pattern is removed, the substrate is processed to form a driving transistor and a switching transistor.

The processing at <NUM> will be described in detail with reference to <FIG>.

At <NUM>, after the preset pattern is removed, the substrate is processed by patterning to obtain a polysilicon pattern and a gate insulating pattern.

Referring to <FIG> and <FIG>, at <NUM>, after the preset pattern <NUM> is removed, the substrate is processed by patterning, such that a portion of the polysilicon layer <NUM> is removed to form the polysilicon pattern <NUM>, and a portion of the gate insulating layer <NUM> is removed to form a gate insulating pattern <NUM>.

In some embodiments, as shown in <FIG>, the polysilicon pattern <NUM> includes the first active medium A1 and the second active medium A2. The gate insulating pattern <NUM> includes the first gate insulating block D1 stacked over the first active medium A1, and the second gate insulating block D2 stacked over the second active medium A2.

Referring again to <FIG>, at <NUM>, a gate electrode pattern is formed over the substrate over which the gate insulating pattern has been formed.

As shown in <FIG>, a gate electrode pattern <NUM> is formed over the substrate <NUM> over which the gate insulating pattern <NUM> has been formed. The gate electrode pattern <NUM> includes the first gate electrode B1 stacked over the first gate insulating block D1, and the second gate electrode B2 stacked over the second gate insulating block D2.

To form the gate electrode pattern <NUM>, a gate electrode material layer may be deposited over the substrate <NUM> by coating, magnetron sputtering, thermal evaporation, PECVD, or another appropriate method and then the gate electrode material layer may be processed by a patterning process to obtain the gate electrode pattern <NUM>. The patterning process may include: photoresist coating, exposure, development, etching, and photoresist peeling. For example, the processing of the gate electrode material layer using the patterning process may include: coating a layer of photoresist over the gate electrode material layer; exposing the photoresist using a mask to form at least one fully exposed region and at least one non-exposed region; subsequently processing using a development process, such that the photoresist of the at least one fully exposed region is removed, and the photoresist of the at least one non-exposed region is retained; etching the region of the gate electrode material layer corresponding to the at least one fully exposed region; and peeling off the photoresist of the at least one non-exposed region to obtain the gate electrode pattern <NUM> after completing the etching.

Referring again to <FIG>, at <NUM>, the polysilicon pattern is doped.

As shown in <FIG>, the first active medium A1 and the second active medium A2 in the polysilicon pattern <NUM> are doped. In some embodiments, an orthogonal projection region of an un-doped region a11 in the first active medium A1 on the substrate <NUM> can be overlapped with an orthogonal projection region of the first gate electrode B1 on the substrate <NUM>; and doped regions a12 in the first active medium A1 may be regions other than the un-doped region a11. An orthogonal projection region of an un-doped region a21 in the second active medium A2 on the substrate <NUM> may be overlapped with an orthogonal projection region of the second gate electrode B2 on the substrate <NUM>; and doped regions a22 in the second active medium A2 may be regions other than the un-doped region a21.

Referring again to <FIG>, at <NUM>, an interlayer insulating layer is formed over the substrate over which the gate electrode pattern has been formed.

As shown in <FIG>, an interlayer insulating layer <NUM> is formed over the substrate <NUM> over which the gate electrode pattern <NUM> has been formed.

Referring again to <FIG>, at <NUM>, a source/drain electrode pattern is formed over the substrate over which the interlayer insulating layer has been formed.

As shown in <FIG>, a source/drain electrode pattern <NUM> is formed over the substrate over which the interlayer insulating layer has been formed. The source/drain electrode pattern <NUM> includes first source/drain electrodes C1, i.e., a first source electrode and a first drain electrode, and second source/drain electrodes C2, i.e., a second source electrode and a second drain electrode. The first source/drain electrodes C1 are coupled to the first active medium A1 through via holes in the interlayer insulating layer <NUM>, and the second source/drain electrodes C2 are coupled to the second active medium A2 through via holes in the interlayer insulating layer <NUM>. In some embodiments, as shown in <FIG>, the doped regions a12 in the first active medium Al are coupled to the first source/drain electrodes C1, and the doped regions a22 in the second active medium A2 are coupled to the second source/drain electrode C2.

After the source/drain electrode pattern is formed, a driving transistor and a switching transistor of the pixel circuit are obtained. The driving transistor includes the first gate electrode B1, the first source/drain electrodes C1, and the first active medium A1. The switching transistor includes the second gate electrode B1, the second source/drain electrode C1, and the second active medium A2. The first active medium A1 and the second active medium A2 may both be polysilicon. The grain size of the first active medium A1 may be smaller than the grain size of the second active medium A2.

As discussed above, the driving current IOLED outputted from the driving transistor to the light-emitting diode may satisfy the formula: IOLED = γ * (Vgs - Vth)<NUM>, where Vgs is a voltage difference between the gate electrode and the source electrode of the driving transistor, Vth is a threshold voltage of the driving transistor, and γ is a coefficient determined by characteristic dimensions and process parameters of the driving transistor. That is, the driving current outputted from the driving transistor may be related to the threshold voltage Vth of the driving transistor, and the driving currents outputted from two driving transistors to OLEDs may be different if the threshold voltages of the two driving transistors are different. The uniformity of threshold voltage of multiple polysilicon transistors may be positively correlated with the uniformity of the grain size of the active medium (polysilicon) in the polysilicon transistors, i.e., a more uniform grain size in the active medium across the multiple polysilicon transistors may result in a more uniform threshold voltage across the multiple polysilicon transistors. Further, the magnitude of the grain size of the polycrystalline silicon may be negatively correlated with the uniformity of the grain size of the polycrystalline silicon. In addition, the magnitude of the grain size of the polycrystalline silicon may also be positively correlated with the magnitude of the on-state current of a transistor. The switching transistor may need to have a relatively large on-state current, and hence may need a relatively large grain size in the active medium.

In some embodiments, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. In addition, when the grain size is smaller, the grain size may be more uniform. Accordingly, non-uniformity of the threshold voltage of the driving transistors caused by the non-uniformity of the grain size may be less significant. Further, the driving current provided by the driving transistor under a driving voltage may be related to the threshold voltage of the driving transistor. When the threshold voltages of two driving transistors are similar, the driving currents provided by the two driving transistors under the same driving voltages may be similar. Consequently, in the display panel, the driving currents provided by the driving transistors to OLEDs may tend to be the same.

In some embodiments, the grain size of the second active medium in the switching transistor consistent with the disclosure may be approximately equal to a grain size of an active medium in a switching transistor in the conventional technologies. In some other embodiments, the grain size of the second active medium in the switching transistor consistent with the disclosure may not be equal to the grain size of the active medium in the switching transistor in the conventional technologies. In embodiments of the present disclosure, the grain size of the second active medium in the switching transistor consistent with the disclosure is not restricted, and may be selected according to various application scenarios. According to the invention, the grain size of the second active medium in the switching transistor is larger than the grain size of the first active medium. Thus, a second active medium having a relatively large grain size may be selected as needed, thereby ensuring a relatively large on-state current in the switching transistor.

The first gate insulating block may has a greater thickness than the second gate insulating block. A transistor having a thicker gate insulating block may have a larger subthreshold swing (SS) coefficient. In various application scenarios, in order to effectively control the gray scale, the driving transistor may need to have a greater SS coefficient than the switching transistor. Thus, in some embodiments, the thickness of the first gate insulating block of the driving transistor may be greater than the thickness of the second gate insulating block of the switching transistor. For example, the thickness of the gate insulating block below the first gate electrode may be greater than the thickness of the gate insulating block below the second gate electrode.

Referring again to <FIG>, at <NUM>, an organic light-emitting diode is fabricated, and the organic light-emitting diode is coupled to the pixel circuit.

In some embodiments, as shown in <FIG>, the flat layer <NUM> is formed over the substrate <NUM> over which the sour/drain electrode pattern <NUM> has been formed, and the OLED <NUM> is formed over the substrate <NUM> over which the flat layer <NUM> has been formed (one electrode of the OLED <NUM> is shown in <FIG>). The OLED <NUM> is coupled to the pixel circuit through the via hole in the flat layer <NUM>.

In an array substrate fabricated by the fabrication method for an array substrate consistent with the disclosure, the first active medium in the driving transistor and the second active medium in the switching transistor are both be polysilicon, and the first active medium has a smaller grain size than the second active medium. That is, if the grain size of the second active medium of the switching transistor is regarded as a standard size, the grain size of the first active medium of the driving transistor may be smaller than the standard size. Further, since the grain size is smaller, non-uniformity of threshold voltages in the driving transistors caused by non-uniform grain sizes may be smaller. As a result, in the OLED display panel including the array substrate, driving currents provided by the driving transistors to OLEDs may tend to be the same. Accordingly, the brightness of the light emitted from different pixel regions may tend to be the same, and the display performance of the OLED display panel may be improved.

The present invention provides a method for fabricating an array substrate. The array substrate includes pixel circuits and organic light-emitting diodes (OLED). A pixel circuit includes: a driving transistor having a first active medium, and a switching transistor having a second active medium. The first active medium and the second active medium both are polysilicon. In addition, the first active medium has a smaller grain size than the second active medium. The present disclosure is directed to improving display performance of the OLED display panel.

The Example numbers of the disclosed embodiments of the present disclosure are merely for the illustration and description purposes, and do not represent the merits of the disclosed embodiments.

The foregoing description of the embodiments of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to persons skilled in this art. The embodiments are chosen and described in order to explain the principles of the technology, with various modifications suitable to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claim 1:
A method for fabricating an array substrate, comprising:
fabricating a pixel circuit, the pixel circuit including:
a driving transistor including a first active medium (A1) made of polysilicon, the first active medium (A1) having a first grain size; and
a switching transistor including a second active medium (A2) made of polysilicon, the second active medium (A2) having a second grain size larger than the first grain size; and
fabricating an organic light-emitting diode (<NUM>) coupled to the pixel circuit,
wherein fabricating the pixel circuit includes:
forming an amorphous silicon layer (<NUM>) over a substrate (<NUM>);
forming a gate insulating layer (<NUM>) over the amorphous silicon layer (<NUM>);
forming a preset pattern (<NUM>), an orthogonal projection of the preset pattern (<NUM>) on the substrate (<NUM>) overlapping an orthogonal projection of the first active medium (A1) on the substrate (<NUM>) and not overlapping with an orthogonal projection of the second active medium (A2) on the substrate (<NUM>);
performing laser annealing to turn the amorphous silicon layer (<NUM>) into a polysilicon layer; and
forming the driving transistor and the switching transistor based on the polysilicon layer and the gate insulating layer (<NUM>),
characterized in that
the preset pattern (<NUM>) is formed over the gate insulating layer (<NUM>),
the preset pattern (<NUM>) is removed after performing laser annealing to turn the amorphous silicon layer (<NUM>) into the polysilicon layer and before forming the driving transistor and the switching transistor based on the polysilicon layer and the gate insulating layer (<NUM>), and
removing the preset pattern (<NUM>) includes applying a preset etching solution capable of etching the preset pattern (<NUM>) and the gate insulating layer (<NUM>) to remove the preset pattern (<NUM>) and reduce a thickness of a region of the gate insulating layer (<NUM>) not covered by the preset pattern (<NUM>).