Patent Description:
A ball grid array (BGA) is a type of package for integrated circuits having a large number of interconnects. A BGA package includes a number of electrical contacts on a bottom side for providing electrical connections between the integrated circuit and a printed circuit board (PCB) on which the BGA package is mounted. The contacts take the form of solder balls, or "contact balls", on copper pads on the bottom side of the BGA package. The contact balls supply voltage and power to the integrated circuit, and provide paths for electrical signals traveling to and from the integrated circuit. Usable area on a top side of the BGA package is limited by multiple factors such as: the circuit components, area for under fill epoxy, for a lid or structure ring attachment, and for adhesive bleed out. Real estate on a bottom side of the BGA package is limited by the typically dense array of contact balls. Traditionally, the PCB on which the BGA package is mounted includes capacitors to smooth ripple in the power supply voltages.

Document <CIT> refers to a method for reducing electrical noise inside a ball grid array package for installing capacitors between a plurality of power pads and ground pads on a top side of a substrate of the ball grid array package coats solder paste on the plurality of power pads and ground pads, coats adhesive glue beneath the plurality of capacitors, that fixes the plurality of capacitors on the power pads and ground pads with the adhesive glue and solder paste, and solidifies the adhesive glue in a reflow soldering stove. <CIT>, <CIT>, <CIT> and <CIT> disclose similar arrangements of solder balls and capacitors for an integrated circuit package.

In the figures, elements with the same or similar reference numerals have the same or similar function or steps, unless otherwise indicated.

In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one having ordinary skill in the art that the implementations of the present disclosure can be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail so as not to obscure the disclosure.

The system disclosed herein relates to integrated circuit packaging. More specifically, systems disclosed herein provide packaging solutions for integrated circuits with added capacitance on a 'bottom' side of the package to support high frequency and high current operating conditions.

Modern large integrated circuit devices, such as application-specific integrated circuits (ASICs) and general-purpose processors, may operate at high frequency, high power specifications, thereby necessitating extra capacitive resources coupled to the circuitry to avoid inductive effects that can reduce power supply voltages when current to the integrated circuit increases sharply, such as when a computationally intensive process begins. The resulting voltage drop may reduce the speed of the circuit, increase interference, and increase error rates. Bypass capacitors are used to reduce this voltage ripple on the power supply connections to the integrated circuits. The capacitors are more effective the closer they are in the circuit to the load; that is, the integrated circuit. Ball grid array (BGA) packages, which are commonly used for integrated circuits with many interconnects and large power requirements, have limited real estate in which to place capacitors. Previous approaches to placing the capacitors closer to the integrated circuit in a BGA package have involved removing contact balls on a bottom side of the BGA package. However, removing contact balls from the BGA package has a negative effect on overall circuit performance because of the increased current throughput in the fewer contact balls remaining in the BGA. Beyond a fundamental limit for current throughput, irreversible effects in the contact balls put the long-term reliability of the packaged circuit at risk. Even continuous high current throughput within the specifications of the contact balls may damage the contact balls, if extended beyond a period of time. Moreover, future integrated circuit designs are expected to operate at increased power, requiring more current for chip operation. Accordingly, the problem of increasing capacitance resources of integrated circuit packages will likely worsen in the future.

Implementations as disclosed herein combine a capacitor pad and a BGA pad into a single unit so that package capacitors can be placed on the bottom side of the circuit package without removing contact balls. This allows the package designer to add capacitance close to the load-e.g., the integrated circuit -without jeopardizing the long-term reliability of contact balls. In some implementations, the BGA pad and the capacitor pad are combined with the capacitors bridging adjacent contact balls. In a two terminal capacitor, one terminal is connected to power (e.g., a drain voltage, VDD) and the other is connected to ground (e.g., a sink source voltage, VSS). Adjacent BGA pads can be designed likewise as power and ground with combined pad structures so the capacitor can be placed between pads without removing contact balls from the BGA.

BGA designs typically follow standard spacing rules, for example, a <NUM> or <NUM> pitch. Different size standard capacitors can be used with these different BGA pitches. Also, custom BGA pitches are possible to align with a variety of capacitor sizes.

<FIG> illustrates a bottom side of an integrated circuit package <NUM>, according to some implementations. In some implementations, the integrated circuit package <NUM> may include an integrated circuit component, such as an ASIC, configured to perform a specific application in a system that is part of an electronic appliance (e.g., a GPS-based application in a mobile device). A BGA <NUM> formed on a first side <NUM> of a silicon substrate <NUM> includes multiple contact balls <NUM> arranged in a pattern. Some of the contact balls <NUM> are electrically coupled to a first voltage input <NUM> of an integrated circuit component <NUM>, and some of the contact balls <NUM> are electrically coupled to a second voltage input <NUM> of the integrated circuit component <NUM>. The integrated circuit component <NUM> is disposed on a second side <NUM> of the silicon substrate <NUM>, opposite to the first side. Some of the contact balls <NUM> couple input/output signals to the integrated circuit package. Without limiting the present disclosure, the pattern of the ball grid array <NUM> may be square, rectangular, diagonal, rhomboidal, or any other lattice configuration. In some implementations, the pattern of the BGA <NUM> may be asymmetrical, or have a limited symmetry. More generally, a measure of the size of the BGA <NUM> may be a pitch <NUM>, which in the case of a square lattice may be defined as a lateral side of the unit cell in the lattice.

In some implementations, the integrated circuit package <NUM> includes a capacitor <NUM> having a first terminal coupled with a first contact ball <NUM>-<NUM> that is electrically coupled with the first voltage input <NUM> and a second terminal coupled with a second, neighboring contact ball <NUM>-<NUM> that is electrically coupled with the second voltage input <NUM>. In some implementations, the first contact ball <NUM>-<NUM> and the second contact ball <NUM>-<NUM> may be nearest neighbors in the BGA <NUM>. In some implementations, the first contact ball <NUM>-<NUM> and the second contact ball <NUM>-<NUM> may be adjacent to one another in the ball grid array along a diagonal direction.

In some implementations the first voltage input <NUM> is coupled to a drain voltage (VDD) in a complementary, metal-oxide-semiconductor (CMOS) device of the integrated circuit component <NUM>, and the second voltage input <NUM> is coupled to a sink voltage (VSS) in a CMOS device of the integrated circuit component <NUM>.

<FIG> illustrates a plan view of contact pads for a capacitor on a bottom side <NUM> of an integrated circuit package <NUM> including a capacitor <NUM> between adjacent contact balls 210a and 210b (hereinafter, collectively referred to as "the contact balls <NUM>"), according to some implementations. The contact balls <NUM> are electrically coupled to circuit components on the opposite side of the ASIC package <NUM> via contact pads <NUM>. The contact balls 210a and 210b may be diagonally adjacent to one another in a square BGA <NUM> (e.g., the contact balls 210a and 210b are neighbors along a diagonal direction), thereby allowing for the length of the capacitor <NUM> to fit in the BGA <NUM> without removing the contact balls <NUM>. This allows the package designer to adjust the capacitor <NUM> to add a desired capacitance to the ASIC package <NUM> without jeopardizing the long term reliability of the contact balls <NUM>. In this disclosure, the BGA pads <NUM> and the capacitor pad are combined into the merged pads 220a and 220b, so the capacitor <NUM> can be placed between the contact balls 210a and 210b. In a typical two terminal capacitor, one terminal (e.g., the terminal 201a) may be electrically coupled to power (e.g., a drain voltage VDD) and the other (e.g., the terminal 201b) may be electrically coupled to ground (e.g., a sink voltage VSS, ground, or a "bulk" voltage). The terminal 211a and the terminal 211b will be collectively referred to, hereinafter, as "the terminals <NUM>. " Adjacent merged pads 220a and 220b are designed as power and ground contact pads enabling the placement of capacitor <NUM> between the BGA pads <NUM> without depopulating the contact balls <NUM>. A capacitor body <NUM> provides the bulk capacitance to the capacitor <NUM>. In some implementations, the capacitor body <NUM> includes multiple conductive (e.g., metallic) fingers in contact with the capacitor terminals and interspaced by a dielectric material.

In some implementations, the capacitor <NUM> is placed in the BGA <NUM> by considering a gap distance <NUM> and <NUM> between the capacitor terminals <NUM> and the contact balls <NUM>. Given the symmetry of the BGA <NUM>, the gap distance <NUM> may be larger than the gap distance <NUM>, and both may be larger than a minimum value, to avoid arcing; that is, electric breakdown between the capacitor terminals <NUM> that have different voltages from the contact balls <NUM>. In some implementations, it is expected that gap <NUM> is smaller than the gap <NUM>, as the terminal 211b is in fact electrically coupled to the contact ball 210b via the merged pad 220b. In some implementations, the gap distance <NUM> may be about <NUM> and the gap distance <NUM> may be about <NUM>, or more. In some implementations, a minimum gap for <NUM> may be zero mm because the BGA ball and the capacitor terminal can be electrically coupled.

<FIG> illustrates another plan view of the bottom side <NUM> the integrated circuit package <NUM> shown in <FIG> with the capacitor <NUM> removed. <FIG> shows underlying details of the contact pads <NUM> on the bottom side <NUM> of the integrated circuit package <NUM>, according to some implementations. The contact pads <NUM> may include the BGA pads and also the merged pads 220a and 220b, including contact regions 230a and 230b for the terminals of the capacitor, e.g., terminals <NUM> in capacitor <NUM>, (hereinafter, collectively referred to as "the contact regions <NUM>"). A contact region is a portion of the bottom side of the integrated circuit package <NUM> where the insulator layer is removed to allow for contact with a capacitor terminal. The contact regions <NUM> may have a rectangular shape with a width <NUM> and a length <NUM>. The merged pads <NUM> may include a tab having a width <NUM>. The tabs of the merged pads 220a and 220b may be separated by a gap <NUM>, forming a total length <NUM> for the capacitor <NUM>. A gap <NUM> is formed between a contact ball <NUM> electrically insulated from the capacitor <NUM>.

Without limitation, the BGA <NUM> may follow different spacing rules. For example, a pitch <NUM> between adjacent contact balls may be <NUM>, or less (e.g., <NUM>, or even less). In such configurations, the capacitors <NUM> may include different standard sizes (e.g., the length <NUM>). Some implementations include a custom the BGA pitch <NUM> enabling a variety of the capacitor lengths <NUM>, as desired.

<FIG> illustrates a cross-section view of the integrated circuit package <NUM> including the capacitor <NUM> between adjacent contact balls 210a and 210b, according to some implementations. The contact balls <NUM> and the capacitor <NUM> are disposed on the bottom side <NUM> of the silicon substrate <NUM>. The silicon substrate has a top side <NUM> opposite to the bottom side <NUM>. The contact balls are separated by a pitch <NUM>. The integrated circuit components <NUM> may be disposed on the front side <NUM> of the silicon substrate <NUM>. Other dimensions in integrated circuit package <NUM> include a width <NUM> of the contact region for contact balls <NUM>, a width <NUM> of the contact region for the terminals <NUM> of the capacitor <NUM>, and a spacing <NUM> between the contact regions for a capacitor terminal and a closest contact ball, filled with an insulating layer <NUM>. In some implementations, the pitch <NUM> can be between <NUM> and <NUM>. In some implementations, a width <NUM> can be between <NUM> and <NUM>. In some implementations, the width <NUM> can be between <NUM> and <NUM>. In some implementations, a height <NUM> can be between <NUM> and <NUM>. In some implementations, a width <NUM> can be between <NUM> and <NUM>. In some implementations, a height <NUM> can be between <NUM> and <NUM>. In some implementations, a gap <NUM> can be between <NUM> (i.e., connected) and <NUM>.

The capacitor body <NUM> includes alternating layers of conductor and dielectric material within an electrically insulating package. The capacitor <NUM> is mounted over the bottom side <NUM> of the integrated circuit package <NUM>, in some cases over the insulating layer <NUM>, such as a solder mask. The capacitor <NUM> has two terminals 211a and 211b, which are soldered to merged pads 220a and 220b, which also provide an electrical connection to the contact balls <NUM>. A height <NUM> of the capacitor <NUM> with respect to the bottom side <NUM> is lower than a profile <NUM> of the contact balls <NUM>. The terminals <NUM> are in electrical contact with the contact balls <NUM> through the merged pads 220a and 220b formed over a silicon substrate <NUM> and under the insulating layer <NUM> on the bottom side <NUM> of the ASIC package <NUM>, in some implementations the silicon substrate includes the circuit component.

<FIG> include partial views of the bottom side of the integrated circuit packages 30A, 30B, 30C and 30D (hereinafter, collectively referred to as "the integrated circuit packages <NUM>"), respectively, including different arrangements for capacitors, consistent with implementations disclosed herein. The integrated circuit packages <NUM> include the contact pads <NUM>, which also include the merged pads 320a for first capacitor terminals and first contact balls carrying a first voltage, and the merged pads 320b for second capacitor terminals and second contact balls carrying a second voltage (contact balls and capacitors are not shown in the figures, for clarity).

<FIG> illustrates a partial view of the bottom side of the integrated circuit package 30A including the contact pads <NUM> for multiple capacitors in a first pattern, according to some implementations. The first pattern includes capacitors coupled across contact balls that are diagonal neighbors. In some implementations the BGA <NUM> is a square lattice with contact balls coupled to positive and negative voltage inputs alternatively, by column.

<FIG> illustrates a partial view of the bottom side of the integrated circuit package 30B including the contact pads <NUM> for multiple capacitors a second pattern, according to the invention. The second pattern includes capacitors coupled across contact balls that are diagonal neighbors. In some implementations the BGA <NUM> is a square or rhomboidal lattice and the contact pads 320a and 320b are coupled to positive and negative voltage inputs alternatively, by row.

<FIG> illustrates a partial view of the bottom side of the integrated circuit package 30C including the contact pads <NUM> for multiple capacitors in a bridged pattern, according to the invention. The bridged pattern includes capacitors coupled across contact balls that are diagonal neighbors. In some implementations the BGA <NUM> is a square or rhomboidal lattice with contact pads coupled to positive and negative voltage inputs alternatively, by row. Additionally, the bridged pattern includes positive bridges 330a and negative bridges 330b (hereinafter, collectively referred to as "the bridges <NUM>"). The bridges <NUM> electrically couple more than one contact pad <NUM> to a given capacitor terminal, which can allow a single capacitor to provide capacitance to more than one contact ball. In many cases, however, the bridges <NUM> may be redundant because the VDD pads will be connected to each other within the package, as will the VSS pads.

<FIG> illustrates a partial view of the bottom side of an integrated circuit package 30D including multiple capacitors in a second bridged pattern, according to some implementations. The second bridged pattern includes capacitors bridging contact balls that are diagonal neighbors. In some implementations the BGA <NUM> is a square or rhomboidal lattice with contact pads that can be coupled to positive, negative, and/or ground voltage inputs alternatively, by row. Additionally, the bridged pattern includes the positive bridges 330a and the negative bridges 330b (hereinafter, collectively referred to as "the bridges <NUM>") coupling the capacitor terminals in parallel. Accordingly, implementations consistent with the integrated circuit package 30D may include an increased capacitance.

<FIG> illustrates a cross-sectional view of a system <NUM> including an integrated circuit package 40A and a memory circuit 40B, mounted on a printed circuit board (PCB) <NUM>, according to some implementations. The system <NUM> includes a memory circuit package 40B storing data and/or instructions and an integrated circuit package 40A including an integrated circuit <NUM> configured to execute the instructions or process the data stored in the memory circuit package 40B. The integrated circuit package 40A includes a ball grid array <NUM>-<NUM> formed on a bottom side <NUM> of a silicon substrate <NUM> in the integrated circuit package 40A. In some implementations, the ball grid array <NUM>-<NUM> includes multiple contact balls <NUM> arranged in a pattern (e.g., ball grid arrays <NUM> and <NUM>). Each of a subset of the contact balls <NUM> is electrically coupled to a first voltage input or a second voltage input of the integrated circuit <NUM> on a top side <NUM> opposite to the bottom side <NUM>. The integrated circuit package 40A also includes a capacitor <NUM> having a first terminal coupled with a first contact ball that is electrically coupled with the first voltage input and a second terminal coupled with a second contact ball that is electrically coupled with the second voltage input.

In some implementations, the system <NUM> is an electronic appliance (e.g., a personal computer, a laptop, a mobile computer, smartphone, palm computer, or the like). In some implementations, the memory circuit package 40B is also packaged with a ball grid array <NUM>-<NUM> on the bottom side <NUM>, with memory blocks <NUM> on the top side <NUM> of silicon substrate <NUM>. The ball grid array <NUM>-<NUM> may include a capacitor <NUM>, as disclosed herein. Memory circuit package 40B may include a random access memory (RAM), such as a dynamic RAM (DRAM), or a synchronous RAM (SRAM), accessible by integrated circuit <NUM> in integrated circuit package 40A.

In some implementations, system <NUM> may also include a positive power terminal <NUM> and a negative power terminal <NUM> mounted on the printed circuit board <NUM>. For example, in some implementations positive power terminal <NUM> may provide the VDD voltage to a CMOS circuit (e.g., to memory blocks <NUM> or to integrated circuit <NUM>). Likewise, in some implementations the negative power terminal <NUM> may provide the VSS voltage to the CMOS circuit. Moreover, in some implementations the positive power terminal <NUM> and the negative power terminal <NUM> may be directly coupled to the contact balls <NUM>, which in turn provide voltage to the capacitors <NUM>, to the integrated circuit <NUM>, and to the memory blocks <NUM>. Further, in some embodiments the system <NUM> includes a board capacitor <NUM> mounted on the printed circuit board <NUM>. The board capacitor <NUM> may provide a capacitive relief to the system <NUM> for low frequency signals (e.g., <NUM> or less). In some implementations, board capacitor <NUM> may have a first terminal directly coupled to the positive power terminal <NUM> and a second terminal directly coupled to the negative power terminal <NUM>.

As used herein, the phrase "at least one of" preceding a series of items, with the terms "and" or "or" to separate any of the items, modifies the list as a whole, rather than each member of the list (i.e., each item). To the extent that the term "include," "have," or the like is used in the description or the claims, such term is intended to be inclusive in a manner similar to the term "comprise" as "comprise" is interpreted when employed as a transitional word in a claim.

A reference to an element in the singular is not intended to mean "one and only one" unless specifically stated, but rather "one or more. " The term "some" refers to one or more. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the above description.

Claim 1:
An integrated circuit package (<NUM>), comprising:
a substrate (<NUM>) having a first side (<NUM>) and a second side (<NUM>) opposite the first side;
an integrated circuit component (<NUM>) coupled to the second side of the substrate;
a ball grid array (<NUM>) formed on the first side of the substrate, the ball grid array comprising multiple contact balls (<NUM>) arranged in a pattern, wherein each of a first subset of the contact balls is electrically coupled to a first voltage input (<NUM>) of an integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input (<NUM>) of the integrated circuit component;
multiple capacitors (<NUM>) mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls; characterised by
a plurality of bridges (<NUM>) electrically coupling a third contact ball with at least one of the first contact ball or the second contact ball thereby forming a bridged pattern, wherein the bridged pattern further comprises positive bridges (330a) and negative bridges (330b).