Patent Description:
In recent years, with the miniaturization of semiconductor devices, signal delay due to wiring has attracted attention as a factor reducing an operation speed of a semiconductor device. Specifically, since a sectional area of the wiring decreases due to the miniaturization of the semiconductor device, and a wiring resistance increases, delay in proportion to a product between the wiring resistance and wiring capacity (also referred to as RC delay) increases.

In order to reduce such signal delay due to wiring, causing an interlayer film between wirings to have a lower dielectric constant has been considered. However, an interlayer film material that realizes a sufficiently low dielectric constant has not been found yet.

Thus, further reducing the dielectric constant between wirings by removing the material between the wirings and providing a hollow layer (also referred to as an air gap) with a specific dielectric constant <NUM> between the wirings has been considered.

For example, Patent Literature <NUM> listed below discloses providing a structure that does not damage wirings when insulating layers between wirings are removed to form an air gap structure.

Moreover, patent application <CIT> describes a semiconductor device with a wiring layer which forms insulator layers, whose wet etching resistance is higher than another insulating in the upper and lower layers.

From patent application <CIT>, it is known that properties of a hard mask liner can be used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack.

From patent <CIT>, multi-level semiconductor devices are known which are formed with reduced parasitic capacitance.

Patent application <CIT> describes an image sensor employing deep trench spacing isolation.

Patent application <CIT> describes interconnections of an integrated electronic circuit.

However, since a thin film with low mechanical strength protrudes into a space in which the air gap is formed according to the technology disclosed in Patent Literature <NUM>, there is a probability that the protruding thin film may collapse. Also, since mechanical strength of an entire semiconductor device is degraded due to the air gap in a case in which intervals between the wirings are wide according to the technology disclosed in Patent Literature <NUM>, there is a probability that reliability of the semiconductor device will be degraded.

Thus, the present disclosure proposes a novel and improved semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device capable of reducing wiring capacity by using gaps and maintaining mechanical strength and reliability.

According to a first aspect the invention provides a semiconductor device in accordance with claim <NUM>. According to a second aspect the invention provides an image pickup device in accordance with claim <NUM>. According to a third aspect the invention provides a method for manufacturing a semiconductor device in accordance with claim <NUM>. Further aspects are set forth in the dependent claims, the description and the drawings.

According to the present disclosure, there is provided a semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.

In addition, according to the present disclosure, there is provided an image pickup device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.

In addition, according to the present disclosure, there is provided a method for manufacturing a semiconductor device, including: a step of forming a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a step of forming a through-hole such that the through-hole penetrates through at least one or more insulating layers from one surface of the multilayered wiring layer; a step of forming a protective side wall inside the through-hole; and a step of forming a gap by etching at least one or more insulating layers immediately below the through-hole.

According to the present disclosure, it is possible to form gaps in insulating layers that are the second and following layers from a surface of the multilayered wiring layer that forms a semiconductor device. According to this, since it is possible to provide a hollow with a specific dielectric constant <NUM> between wirings while the mechanical strength of the semiconductor device is maintained, it is possible to reduce wiring capacity of the semiconductor device.

According to the present disclosure, it is possible to reduce wiring capacity by the gaps and to maintain mechanical strength and reliability of the semiconductor device.

Note that description will be given in the following order.

First, a sectional structure of a semiconductor device according to a first embodiment of the present disclosure will be described with reference to <FIG> is a sectional view of a semiconductor device <NUM> according to the embodiment taken in a laminating direction. Note that <FIG> illustrates a part of the sectional surface of the semiconductor device <NUM> according to the embodiment and it is needless to say that the semiconductor device <NUM> also extends in an in-plane direction in a range which is not illustrated in the drawing.

As illustrated in <FIG>, the semiconductor device <NUM> includes a substrate <NUM> and a multilayered wiring layer in which first to fifth insulating layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and first to fifth diffusion preventing layers <NUM>, <NUM>, <NUM><NUM>, and <NUM> are alternately laminated. In addition, the substrate <NUM> is provided with a semiconductor element (not illustrated), and the second to fifth insulating layers <NUM>, <NUM>, <NUM>, and <NUM> are provided with first to fourth wiring layers <NUM>, <NUM>, <NUM>, and <NUM>, respectively. Note that the semiconductor element is caused to have continuity with the first wiring layer <NUM> via a contact plug <NUM>, and the first to fourth wiring layers <NUM>, <NUM>, <NUM>, and <NUM> are caused to have continuity with each other via first to third through-vias <NUM>, <NUM>, and <NUM>.

In the following description, the first to fifth insulating layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> will also be referred to collectively as insulating layers <NUM> while the first to fifth diffusion preventing layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> will also be referred to collectively as diffusion preventing layers <NUM>. Also, the first to fourth wiring layers <NUM>, <NUM>, <NUM>, and <NUM> will also be referred to collectively as wiring layers <NUM> while the first to third through-vias <NUM>, <NUM>, and <NUM> will also be referred to collectively as through-vias <NUM>.

That is, the semiconductor device <NUM> includes the multilayered wiring layer in which the insulating layers <NUM> including the wiring layers <NUM> and the through-vias <NUM> and the diffusion preventing layers <NUM> are alternately laminated.

Note that, although <FIG> illustrates that the semiconductor device <NUM> has a configuration of a five-layer structure in which the first to fifth insulating layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and the first to fifth diffusion preventing layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are alternately laminated, the technology according to the present disclosure is not limited to such an illustrative example. For example, the semiconductor device <NUM> may include a multilayered wiring layer including three or four layers or may include a multilayered wiring layer including six or more layers.

The insulating layers <NUM> are main layer formation materials that electrically insulate the wiring layers <NUM> from each other and form the semiconductor device <NUM>. The insulating layers <NUM> include an insulating material that can be etched relatively easily (specifically, that can be etched more easily than the diffusion preventing layers <NUM>, which will be described layer) and may include an insulating material such as SiOx, for example.

The diffusion preventing layers <NUM> are provided to sandwich the respective insulating layers <NUM>, suppress surface diffusion of metal atoms that form the wiring layers <NUM>, and serve as stoppers when members in the upper layers are worked. Specifically, the diffusion preventing layers <NUM> include an insulating material with higher etching resistance (for example, etching resistance with respective to fluorine compounds) than the insulating layers <NUM> and may include an insulating material such as SiNx, SiCN, SiON, or SiC, for example.

The wiring layers <NUM> deliver currents or voltages between the respective elements provided in the semiconductor device <NUM>. The wiring layers <NUM> include a conductive metal material and may include copper (Cu), tungsten (W), aluminum (Al), or an alloy containing these metals, for example. Also, barrier metal layers may be formed using a metal with a high barrier property on the surfaces of the wiring layers <NUM>, although these are not illustrated in the drawing. The barrier metal layer can include a metal such as tantalum (Ta), titanium (Ti), ruthenium (Ru), cobalt (Co), or manganese (Mn) or nitrides or oxides of these metals, for example.

The through-vias <NUM> electrically connect the wiring layers <NUM> provided in different insulating layers <NUM>. Specifically, the first through-via <NUM> connects the first wiring layer <NUM> to the second wiring layer <NUM>, the second through-via <NUM> connects the second wiring layer <NUM> to the third wiring layer <NUM>, and the third through-via <NUM> connects the third wiring layer <NUM> to the fourth wiring layer <NUM>. The through-vias <NUM> include a conductive metal material similarly to the wiring layers <NUM> and may include copper (Cu), tungsten (W), aluminum (Al), or an alloy containing these materials, for example. Also, barrier metal layers may be formed on the surfaces of the through-vias <NUM> similarly to the wiring layers <NUM>.

The substrate <NUM> is a substrate including various semiconductors and may be a substrate including polycrystalline, monocrystalline, or amorphous silicon (Si). Also, the substrate <NUM> is provided with a semiconductor element that realizes functions of the semiconductor device <NUM>. As the semiconductor element provided on the substrate <NUM>, a logic circuit or the like including a memory element, a color sensor, or a transistor, for example, can be exemplified.

The contact plug <NUM> electrically connects an electrode or a wiring of the semiconductor element or the like provided on the substrate <NUM> to the first wiring layer <NUM>. The contact plug <NUM> may include a metal material that is similar to that of the through-vias <NUM> and may include copper (Cu), tungsten (W), aluminum (Al), or an alloy containing these metals, for example.

In addition, the semiconductor device <NUM> is provided with a through-hole <NUM> that penetrates the fifth diffusion preventing layer <NUM>, the fifth insulating layer <NUM>, and the fourth diffusion preventing layer <NUM> and has an inside covered with a protective side wall <NUM>, as illustrated in <FIG>. The through-hole <NUM> causes a gap <NUM> provided at the third insulating layer <NUM> and the fourth insulating layer <NUM> to communicate with an external space.

Note that a sealing layer that blocks an opening of the through-hole <NUM> may be provided on the fifth diffusion preventing layer <NUM> although this is not illustrated in <FIG>. The sealing layer includes an arbitrary insulating material such as SiOx, SiNx, SiCN, SiON, or SiC, for example and prevents moisture and the like from entering the through-hole <NUM> and the gap <NUM>.

The through-hole <NUM> is provided to penetrate through the insulating layer <NUM> provided on any one surface of the semiconductor device <NUM> and the diffusion preventing layers <NUM> that sandwich the insulating layer <NUM>. Specifically, the through-hole <NUM> is provided to penetrate through the fifth insulating layer <NUM>, and the fourth diffusion preventing layer <NUM> and the fifth diffusion preventing layer <NUM> that sandwich the fifth insulating layer <NUM> therebetween. The shape of the opening of the through-hole <NUM> may be a substantially quadrangular shape with a side of at least <NUM> to <NUM> or may be a substantially circular shape with a diameter of <NUM> to <NUM>, for example.

The protective side wall <NUM> is provided inside the through-hole <NUM> to protect a side surface of the fifth insulating layer <NUM> exposed due to the through-hole <NUM>. The protective side wall <NUM> includes an insulating material with higher etching resistance (for example, etching resistance with respect to fluorine compounds) than that of the insulating layers <NUM>, for example, and may include an insulating material such as SiNx, SiCN, SiON, SiOC, or SiC, for example.

The protective side wall <NUM> functions to protect the fifth insulating layer <NUM> such that the fifth insulating layer <NUM> is not etched when the gap <NUM> is formed. Specifically, the gap <NUM> is formed by introducing an etching solution via the through-hole <NUM> and performing wet-etching on the third insulating layer <NUM> and the fourth insulating layer <NUM>. At this time, the protective side wall <NUM> prevents the fifth insulating layer <NUM> from being wet-etched by the etching solution. Therefore, it is possible to form the gap <NUM> in the insulating layer <NUM> provided inside the second and following layers in the multilayered wiring layer in the semiconductor device <NUM> by using the through-hole <NUM> with the inside covered with the protective side wall <NUM>. Note that the protective side wall <NUM> may be a thin film of <NUM> to <NUM>, for example.

The gap <NUM> is provided in the second and following insulating layers <NUM> in the multilayered wiring layer (that is, the inside of the multilayered wiring layer) in the semiconductor device <NUM>, and spaces in the wiring layers <NUM> are formed as hollows with a specific dielectric constant of <NUM>. In this manner, the gap <NUM> can reduce wiring capacity in the wiring layers <NUM>. Specifically, the gap <NUM> is provided at the third insulating layer <NUM> and the fourth insulating layer <NUM> and can reduce the wiring capacity by forming the space between the third wiring layer <NUM> and the second wiring layer <NUM> as a hollow.

Note that the gap <NUM> is not provided in the insulating layer <NUM> on the surface of the multilayered wiring layer in the semiconductor device <NUM>. Specifically, the gap <NUM> is not provided in the first insulating layer <NUM> and the fifth insulating layer <NUM> on the surface of the multilayered wiring layer. In this manner, it is possible to maintain overall mechanical strength although the gap <NUM> is formed in the semiconductor device <NUM>.

The gap <NUM> can be formed by introducing an etching solution via the through-hole <NUM> and performing etching on the third insulating layer <NUM> and the fourth insulating layer <NUM> by using a wet etching method.

At this time, a region in which the gap <NUM> is formed is restricted to a region surrounded by the diffusion preventing layers <NUM> in the laminating direction of the multilayered wiring layer. This is because it is difficult for etching to advance through the diffusion preventing layers <NUM> due to higher etching resistance thereof than that of the insulating layers <NUM>. Therefore, in a case in which sufficient etching is performed, the gap <NUM> causes the second diffusion preventing layer <NUM> and the fourth diffusion preventing layer <NUM> that are present above and below the third insulating layer <NUM> and the fourth insulating layer <NUM> to be exposed.

In addition, the region in which the gap <NUM> is formed is controlled by a length of time during which etching is performed in the in-plane direction of the multilayered wiring layer. That is, the gap <NUM> is formed in a region that extends isotropically from a portion immediately below the through-hole <NUM> into which the etching solution has been introduced while the broadness of the region is controlled by an etching time.

Note that the through-vias <NUM> or the wiring layers <NUM> are not etched under conditions under which the insulating layers <NUM> are etched. Therefore, in a case in which the through-vias <NUM> or the wiring layers <NUM> are present in the region in which the gap <NUM> is formed, the through-vias <NUM> or the wiring layers <NUM> directly remain inside the gap <NUM>. Also, in a case in which the insulating layers <NUM> are spatially sectioned by the through-vias <NUM> or the wiring layers <NUM>, the etching solution does not enter a space on the opposite side sectioned by the through-vias <NUM> or the wiring layers <NUM>. In this case, the region in which the gap <NUM> is formed is restricted by the through-vias <NUM> or the wiring layers <NUM>.

In a case in which the gap <NUM> is provided in a plurality of insulating layers <NUM>, a part of the diffusion preventing layers <NUM> between the plurality of insulating layers <NUM> is removed in advance to form an opening. Specifically, the gap <NUM> is provided in the third insulating layer <NUM> and the fourth insulating layer <NUM>, and a part of the third diffusion preventing layer <NUM> in the vicinity of the through-hole <NUM> is removed in advance to form an opening. In this manner, since the etching solution can be diffused from the fourth insulating layer <NUM> to the third insulating layer <NUM> when the etching for forming the gap <NUM> is performed, it is possible to form the gap <NUM> over a plurality of layers, namely the third insulating layer <NUM> and the fourth insulating layer <NUM>.

In addition, an opening is formed at this time in the diffusion preventing layers <NUM> such that a region that protrudes to the gap <NUM> and is not formed above the wiring layer <NUM> is not formed. In this manner, it is possible to prevent the diffusion preventing layers <NUM> protruding to the gap <NUM> from collapsing after the gap <NUM> is formed.

Note that, although <FIG> illustrates a case in which only one through-hole <NUM> is formed, the technology according to the present disclosure is not limited to the aforementioned illustrative example. For example, a plurality of through-holes <NUM> may be formed. In such a case, the plurality of through-holes <NUM> may form the same gap <NUM> or each may form a separate gap <NUM>.

In addition, the protective layer <NUM> may be formed on the surface exposed by the gap <NUM> as illustrated in <FIG> is a sectional view illustrating a configuration in which the protective layer <NUM> is formed on the inner surface of the gap <NUM> in the semiconductor device <NUM> illustrated in <FIG>.

As illustrated in <FIG>, the protective layer <NUM> may be formed on each of the surfaces of the insulating layers <NUM>, the diffusion preventing layers <NUM>, the wiring layers <NUM>, and the through-vias <NUM> exposed by the gap <NUM>.

The protective layer <NUM> includes an arbitrary insulating material, for example, and may include an insulating material such as SiOx, SiNx, SiCN, SiON, SiOC, or SiC, for example. Also, the film thickness of the protective layer <NUM> may be <NUM> to <NUM>, for example. The protective layer <NUM> can improve reliability of the wirings by preventing electromigration and time dependant dielectric breakdown (TDDB) in the wiring layers <NUM> and the through-vias <NUM>. Such a protective layer <NUM> can be formed by introducing a raw material gas into the gap <NUM> via the through-hole <NUM> and performing an atomic layer deposition (ALD) method, for example.

According to the semiconductor device <NUM> described above, it is possible to form a hollow between the wiring layers <NUM> by the gap <NUM> and thereby to reduce the wiring capacity. Therefore, it is possible to realize a high operation speed and low power consumption by suppressing delay in the wirings according to the semiconductor device <NUM>.

In addition, since the gap <NUM> is not provided in the insulating layers <NUM> (that is, the first insulating layer <NUM> and the fifth insulating layer <NUM>) provided on the surface of the multilayered wiring layer in the semiconductor device <NUM>, it is possible to maintain mechanical strength of the entire semiconductor device <NUM>. Further since the diffusion preventing layers <NUM> that protrude into the gap <NUM> are not generated in the semiconductor device <NUM>, it is possible to prevent the diffusion preventing layers <NUM> with low mechanical strength from collapsing.

Next, an example of planar arrangement of the respective configurations in the semiconductor device <NUM> according to the embodiment will be described with reference to <FIG> is a planar diagram illustrating the semiconductor device <NUM> according to the embodiment in a plan view in the laminating direction.

Note that only the planar arrangement of the second to fourth wiring layers <NUM>, <NUM>, and <NUM>, the through-hole <NUM>, and an opening <NUM> formed in the third diffusion preventing layer <NUM> are illustrated and illustration of the other configurations is omitted. Also, the planar arrangement illustrated in <FIG> is just an example, and the planar arrangement of the respective configurations in the semiconductor device <NUM> according to the embodiment is not limited thereto.

Since the second to fourth wiring layers <NUM>, <NUM>, and <NUM> are formed in mutually different insulating layers <NUM> as illustrated in <FIG>, partial regions thereof are formed in a mutually overlapped manner. Also, the first through-via <NUM> and the second through-via <NUM>, for example, may be formed in the partial regions at which the second to fourth wiring layers <NUM>, <NUM>, and <NUM> mutually overlapping with each other.

The through-hole <NUM> is formed in a region in which the through-hole <NUM> does not overlap with the third wiring layer <NUM> and the fourth wiring layer <NUM> so as not to interfere with the third wiring layer <NUM> and the fourth wiring layer <NUM>. The shape of the opening of the through-hole <NUM> may be a substantially quadrangular shape with a side of at least <NUM> to <NUM>, for example. Also, one through-hole <NUM> may be provided for one gap <NUM>, or a plurality of through-holes <NUM> may be provided for one gap <NUM>. Further, the through-hole <NUM> may be provided in a region for which it is desired to reduce wiring capacity.

The gap <NUM> is formed in a region in which the second to fourth wiring layers <NUM>, <NUM>, and <NUM> are not formed though not illustrated in the drawing.

The opening <NUM> formed in the third diffusion preventing layer <NUM> is formed in a region that avoids the region in which the second wiring layer <NUM> is formed. This is for preventing the second wiring layer <NUM> from collapsing by forming the opening <NUM> since the third diffusion preventing layer <NUM> is formed on the second wiring layer <NUM>. In addition, the opening <NUM> may be formed in a region including a region in which the through-hole <NUM> is formed or may be formed in a region not including the region in which the through-hole <NUM> is formed. Note that the shape of the opening <NUM> formed in the third diffusion preventing layer <NUM> may be an arbitrary polygonal shape with a side of <NUM> to <NUM>.

Next, a method for manufacturing the semiconductor device <NUM> according to the embodiment will be described with reference to <FIG> are sectional views illustrating steps of the method for manufacturing the semiconductor device <NUM> according to the embodiment.

First, the first insulating layer <NUM>, the first diffusion preventing layer <NUM>, the second insulating layer <NUM>, the second diffusion preventing layer <NUM>, the third insulating layer <NUM>, and the third diffusion preventing layer <NUM> are sequentially laminated on the substrate <NUM> provided with the semiconductor element and the like by a CVD method as illustrated in <FIG>. In addition, the contact plug <NUM>, the first wiring layer <NUM>, the second wiring layer <NUM>, and the first through-via <NUM> are formed in each of the insulating layers <NUM>.

Specifically, the first insulating layer <NUM> is formed on the substrate <NUM> including silicon (Si) or the like, first. Next, the first wiring layer <NUM> can be formed by using a damascene method in which the first diffusion preventing layer <NUM> and the second insulating layer <NUM> are formed on the first insulating layer <NUM>, the first diffusion preventing layer <NUM> and the second insulating layer <NUM> in a predetermined region are then removed by etching, and the etched portion is buried again with copper (Cu) or the like. In addition, the second wiring layer <NUM> and the first through-via <NUM> can be formed by a similar method.

Note that the first to third insulating layers <NUM>, <NUM>, and <NUM> may include SiOx or the like that can be easily etched with a hydrofluoric acid, and the first to third diffusion preventing layers <NUM>, <NUM>, and <NUM> may include SiC or the like with high etching resistance with respect to the hydrofluoric acid.

Next, a part of the third diffusion preventing layer <NUM> is removed by using a photolithography method as illustrated in <FIG>. At this time, the region from which the third diffusion preventing layer <NUM> has been removed functions as an opening for introducing the etching solution into the second insulating layer <NUM> in a step of etching the second insulating layer <NUM> and the third insulating layer <NUM> in a later stage.

Next, the fourth insulating layer <NUM>, the fourth diffusion preventing layer <NUM>, the fifth insulating layer <NUM>, and the fifth diffusion preventing layer <NUM> are sequentially laminated on the third diffusion preventing layer <NUM> by a CVD method as illustrated in <FIG>. Also, the third wiring layer <NUM>, the fourth wiring layer <NUM>, the second through-via <NUM>, and the third through-via <NUM> are formed on each of the insulating layers <NUM>.

Specifically, it is possible to form the third wiring layer <NUM> by using the damascene method in which the fourth insulating layer <NUM> is formed on the third diffusion preventing layer <NUM>, the fourth insulating layer <NUM> in a predetermined region is then removed by etching, and the etched portion is buried with copper (Cu) or the like. In addition, it is possible to form the fourth wiring layer <NUM>, the second through-via <NUM>, and the third through-via <NUM> by a similar method. Note that the fourth and fifth insulating layers <NUM> and <NUM> may include SiOx or the like that can be easily etched with a hydrofluoric acid, and the fourth and fifth diffusion preventing layers <NUM> and <NUM> may include SiC or the like with high etching resistance with respect to the hydrofluoric acid.

Next, the through-hole <NUM> is formed by forming a barrier layer <NUM> on the fifth diffusion preventing layer <NUM> and removing the fifth insulating layer <NUM>, the fourth diffusion preventing layer <NUM>, and the fifth diffusion preventing layer <NUM> in a partial region by using etching or the like as illustrated in <FIG>. The barrier layer <NUM> functions to protect the fifth diffusion preventing layer <NUM> and may include SiO<NUM> of about <NUM>, for example. Also, the region in which the through-hole <NUM> is formed is a region in which the third wiring layer <NUM> and the fourth wiring layer <NUM> are not formed, for example, and the shape of the opening of the through hole <NUM> may be a square shape of <NUM> to <NUM>. Note that a plurality of through-holes <NUM> may be provided.

Next, a protective film <NUM> is formed on the barrier layer <NUM> and inside the through-hole <NUM> by using an ALD method as illustrated in <FIG>. The protective film <NUM> may be formed to have a film thickness of <NUM> to <NUM> with SiC or the like with high etching resistance with respect to a hydrofluoric acid, for example. Here, since the protective film <NUM> is formed by using the ALD method, the protective film <NUM> is uniformly (conformally) formed on the barrier layer <NUM> and inside the through-hole <NUM>.

Next, the protective film <NUM> is removed while the protective side wall <NUM> is made to remain inside the through-hole <NUM> by etching back the entire surface of the protective film <NUM>, thereby causing the barrier layer <NUM> and the fourth insulating layer <NUM> to be exposed as illustrated in <FIG>. Such etching back of the entire surface can be realized by performing etching with significantly high perpendicular anisotropy. At this time, it is possible to prevent the fifth diffusion preventing layer <NUM> from being damaged by the etching back of the entire surface since the barrier layer <NUM> is provided on the fifth diffusion preventing layer <NUM>.

Next, the gap <NUM> is formed by introducing a diluted hydrofluoric acid into the second insulating layer <NUM> and the third insulating layer <NUM> via the through-hole <NUM> and performing wet-etching thereon as illustrated in <FIG>. Note that the barrier layer <NUM> is removed by the wet etching using the diluted hydrofluoric acid at this time.

At this time, the etching hardly advances through the protective side wall <NUM> and the second to fourth diffusion preventing layers <NUM>, <NUM>, and <NUM> since the protective side wall <NUM> and the second to fourth diffusion preventing layers <NUM>, <NUM>, and <NUM> include SiC or the like with high etching resistance with respect to the hydrofluoric acid. Also, etching hardly advances through the second wring layer <NUM>, the third wiring layer <NUM>, the first through-via <NUM>, and the second through-via <NUM> since the second wiring layer <NUM>, the third wiring layer <NUM>, the first through-via <NUM>, and the second through-via <NUM> include a metal material such as copper (Cu) and have high etching resistance with respect to the hydrofluoric acid. Therefore, the region in which the gap <NUM> is formed is controlled depending on a region sandwiched between the second diffusion preventing layer <NUM> and the fourth diffusion preventing layer <NUM> in the laminating direction of the semiconductor device <NUM> and is controlled depending on a time during which the wet etching is performed in the in-plane direction of the semiconductor device <NUM>.

In this manner, it is possible to etch only the second insulating layer <NUM> and the third insulating layer <NUM> by the wet etching using the diluted hydrofluoric acid and to thereby form the gap <NUM>. Note that the third diffusion preventing layer <NUM> is formed in a region with an end corresponding to a region in which the second wiring layer <NUM> is formed and does not protrude to the gap <NUM>, it is possible to prevent the third diffusion preventing layer <NUM> from collapsing.

It is possible to manufacture the semiconductor device <NUM> according to the embodiment through the aforementioned process. Note that a sealing layer that includes an insulating material and blocks the opening of the through-hole <NUM> may be provided on the fifth diffusion preventing layer <NUM> in order to prevent moisture and the like from entering the gap <NUM>.

In the aforementioned manufacturing method, the hydrofluoric acid is used for the etching, SiOx is used as a material that can be easily etched with respect to the hydrofluoric acid for the insulating layers <NUM>, and SiC is used as a material with high etching resistance with respect to the hydrofluoric acid for the diffusion preventing layers <NUM>. However, the technology according to the present disclosure is not limited to the aforementioned illustrative example. An arbitrary combination may be employed as a combination of materials used for the insulating layers <NUM> and the diffusion preventing layers <NUM> as long as it is possible to secure a sufficient etching selection ratio. Also, it is possible to appropriately select the etching solution used for the etching in accordance with the insulating layers <NUM> and the diffusion preventing layers <NUM>.

Here, modification examples of the semiconductor device <NUM> according to the embodiment will be described with reference to <FIG>. <FIG> is a sectional view illustrating a semiconductor device 1A according to a first modification example of the embodiment taken along the laminating direction, <FIG> is a sectional view illustrating a semiconductor device 1B according to a second modification example of the embodiment taken along the laminating direction, and <FIG> is a sectional view illustrating a semiconductor device 1C according to a third modification example of the embodiment taken along the laminating direction. Note that it is needless to say that <FIG> illustrate parts of the sectional surfaces of the semiconductor devices and the semiconductor devices also extend in the in-plane direction in ranges that are not illustrated in the drawings.

First, the semiconductor device 1A according to the first modification example of the embodiment will be described with reference to <FIG>.

As illustrated in <FIG>, the semiconductor device 1A includes a multilayered wiring layer in which six insulating layers <NUM> and six diffusion preventing layers <NUM> are alternately laminated and is different from the semiconductor device <NUM> as illustrated in <FIG> in that a gap 530A is formed in the fifth insulating layer <NUM>. Here, a sixth insulating layer <NUM> may include a material similar to that of the first to fifth insulating layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, and the sixth diffusion preventing layer <NUM> may include a material similar to that of the first to fifth diffusion preventing layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. In addition, since the other configurations are as described above with reference to <FIG>, the description thereof will be omitted here.

As illustrated in the semiconductor device 1A according to the first modification example, a gap 530A may be formed only in one insulating layer <NUM> (that is, the fifth insulating layer <NUM>). At this time, since no opening is formed in the fourth diffusion preventing layer <NUM> provided below the fifth insulating layer <NUM> by etching, the etching solution does not enter the fourth insulating layer <NUM>, and the gap 530A is not formed in the fourth insulating layer <NUM>. In the semiconductor device 1A according to the first modification example, a space in which the gap 530A is formed is reduced, it is possible to improve mechanical strength of the entire semiconductor device 1A.

In addition, the semiconductor device 1A according to the first modification example may include a multilayered wiring layer in which six insulating layers <NUM> and six diffusion preventing layers <NUM> are alternately laminated or may include a multilayered wiring layer in which seven or more insulating layers <NUM> and seven or more diffusion preventing layers <NUM> are alternately laminated. In the technology according to the present technology, the number of layers laminated in the multilayered wiring layer that forms the semiconductor device <NUM> may be at least three or more in order to form the gap <NUM> inside the multilayered wiring layer, and an upper limit thereof is not particularly limited.

Next, a semiconductor device 1B according to a second modification example of the embodiment will be described with reference to <FIG>.

As illustrated in <FIG> the semiconductor device 1B is different from the semiconductor device <NUM> as illustrated in <FIG> in that a through-hole 510B is formed to penetrate through the fourth and fifth insulating layers <NUM> and <NUM> and the third to fifth diffusion preventing layers <NUM>, <NUM>, and <NUM>. Therefore, the gap <NUM> is formed in the second insulating layer <NUM> and the third insulating layer <NUM> in the semiconductor device 1B. Note that since the respective configurations in the semiconductor device 1B are as described above with reference to <FIG>, description thereof will be omitted here.

As illustrated in the semiconductor device 1B according to the second modification example, the through-hole 501B may be provided to penetrate through the plurality of insulating layers <NUM> (that is, the fourth insulating layer <NUM> and the fifth insulating layer <NUM>). At this time, since the opening is formed in the second diffusion preventing layer <NUM> and the etching solution for forming the gap <NUM> enters the second insulating layer <NUM> from the third insulating layer <NUM>, the gap <NUM> is formed in the second insulating layer <NUM> and the third insulating layer <NUM>. Since the gap <NUM> is formed in the third and following layers from the surface of the multilayered wiring layer in the semiconductor device 1B according to the second modification example, it is possible to improve mechanical strength of the entire semiconductor device 1B.

In addition, the through-hole 510B may be provided to further penetrate through three or more insulating layers <NUM> in the semiconductor device 1B according to the second modification example. However, since it becomes more difficult to form the through-hole 510B as an aspect ratio increases, the number of the insulating layers <NUM> through which the through-hole 510B penetrates may be four or less, for example.

Next, a semiconductor device 1C according to a third modification example of the embodiment will be described with reference to <FIG>.

As illustrated in <FIG>, the semiconductor device 1C is different from the semiconductor device <NUM> illustrated in <FIG> in that a gap 530C is formed in the second to fourth insulating layers <NUM>, <NUM>, and <NUM>. Note that since the respective configurations in the semiconductor device 1C are as described above with reference to <FIG>, description thereof will be omitted here.

As illustrated in the semiconductor device 1B according to the second modification example, the gap 530C may be further formed over the three or more insulating layers <NUM> other than the insulating layers <NUM> on the surface of the multilayered wiring layer (that is, the first insulating layer <NUM> and the fifth insulating layer <NUM>) that forms the semiconductor device 1C. At this time, since an opening is formed in the second diffusion preventing layer <NUM> and the third diffusion preventing layer <NUM> by etching, the etching solution enters the second insulating layer <NUM> and the third insulating layer <NUM>, and the gap 530C is formed from the second insulating layer <NUM> to the fourth insulating layer <NUM>. In the semiconductor device 1C according to the third modification example, it is possible to form the gap 530C in more insulating layers <NUM>, to thereby further suppress signal delay, and to further reduce power consumption by further reducing wiring capacity between the wirings.

In addition, the gap 530C may be further provided in a plurality of insulating layers <NUM> in the semiconductor device 1C according to the third modification example. However, since a probability that mechanical strength of the entire semiconductor device 1C is degraded increases as a space in which the gap 530C is formed increases, the number of the insulating layers <NUM> in which the gap 530C is formed may be <NUM> or less, for example.

Next, a sectional structure of a semiconductor device according to a second embodiment of the present disclosure will be described with reference to <FIG> is a sectional view of a semiconductor device <NUM> according to the embodiment taken in a laminating direction. Note that <FIG> illustrates a part of the sectional surface of the semiconductor device <NUM> and it is needless to say that the semiconductor device <NUM> also extends in an in-plane direction in a range which is not illustrated in the drawing.

As illustrated in <FIG>, the multilayered wiring layer in which the insulating layers <NUM> and the diffusion preventing layers <NUM> are alternately laminated is sandwiched between a pair of substrates <NUM> and <NUM> in the semiconductor device <NUM>, and the through-hole <NUM> is provided to penetrate through the substrate <NUM> and the first insulating layer <NUM>. Note that the semiconductor device <NUM> illustrated in <FIG> is obtained by vertically inverting the semiconductor device <NUM> illustrated in <FIG>.

Here, a sixth insulating layer <NUM> and a seventh insulating layer <NUM> may include a material similar to that of the first to fifth insulating layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, and the sixth diffusion preventing layer <NUM> may include a material similar to that of the first to fifth diffusion preventing layers <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. In addition, since the other configurations are as described above with reference to <FIG>, the description thereof will be omitted here.

In the semiconductor device <NUM> according to the embodiment, it is possible to improve mechanical strength of the entire semiconductor device <NUM> by sandwiching the multilayered wiring layer in which the insulating layers <NUM> and the diffusion preventing layers <NUM> are alternately laminated between the pair of substrates <NUM> and <NUM>.

A substrate of any material can be used as the substrate <NUM> as long as it is possible to bond the substrate <NUM> to the multilayered wiring layer in which the insulating layers <NUM> and the diffusion preventing layers <NUM> are alternately laminated. The substrate <NUM> may be a substrate including glass such as quartz, resin such as polyimide or polyester, or a semiconductor of silicone (Si) or the like, for example.

In addition, the thickness of the substrate <NUM> with the semiconductor element (not illustrated) formed thereon may be reduced by using chemical mechanical polishing (CMP) or the like. In a case in which the semiconductor element provided on the substrate <NUM> is a color sensor, such a semiconductor device <NUM> can be used as an image pickup device of a rear surface irradiation type, for example.

As illustrated in the semiconductor device <NUM> according to the embodiment, the through-hole <NUM> may be provided in the insulating layer <NUM> on any of the surfaces of the multilayered wiring layer in which the insulating layers <NUM> and the diffusion preventing layers <NUM> are alternately laminated. That is, the through-hole <NUM> may be provided in the first insulating layer <NUM> or may be provided in the seventh insulating layer <NUM>. It is also possible to form the gap <NUM> inside the multilayered wiring layer via the through-hole <NUM> similarly to the first embodiment in the semiconductor device <NUM> in such a case.

First, the first insulating layer <NUM>, the first diffusion preventing layer <NUM>, the second insulating layer <NUM>, and the second diffusion preventing layer <NUM> are sequentially laminated on the substrate <NUM> with the semiconductor element and the like provided thereon by the CVD method as illustrated in <FIG>. Also, the contact plug <NUM> is formed on the first insulating layer <NUM>, and the first wiring layer <NUM> is formed on the second insulating layer <NUM>.

Specifically, the first insulating layer <NUM> is formed on the substrate <NUM> including silicon (Si) or the like, first. Next, the first wiring layer <NUM> can be formed by using a damascene method in which the first diffusion preventing layer <NUM> and the second insulating layer <NUM> are formed on the first insulating layer <NUM>, the first diffusion preventing layer <NUM> and the second insulating layer <NUM> in a predetermined region are then removed by etching, and the etched portion is buried again with copper (Cu) or the like.

Note that the first and second insulating layers <NUM> and <NUM> may include SiOx or the like that can be easily etched with a hydrofluoric acid, and the first and second diffusion preventing layers <NUM> and <NUM> may include SiC or the like with high etching resistance with respect to the hydrofluoric acid.

Next, a part of the second diffusion preventing layer <NUM> is removed by using a photolithography method as illustrated in <FIG>. At this time, the region from which the second diffusion preventing layer <NUM> has been removed functions as an opening for introducing the etching solution into the third insulating layer <NUM> in a step of etching the second insulating layer <NUM> and the third insulating layer <NUM> in a later stage.

Next, the third insulating layer <NUM>, the third diffusion preventing layer <NUM>, the fourth insulating layer <NUM>, the fourth diffusion preventing layer <NUM>, the fifth insulating layer <NUM>, and the fifth diffusion preventing layer <NUM> are sequentially laminated on the second diffusion preventing layer <NUM> by a CVD method as illustrated in <FIG>. Also, the second wiring layer <NUM>, the third wiring layer <NUM>, the fourth wiring layer <NUM>, the first through-via <NUM>, the second through-via <NUM>, and the third through-via <NUM> are formed on each of the insulating layers <NUM>.

Specifically, it is possible to form the second wiring layer <NUM> by using the damascene method in which the third insulating layer <NUM> is formed on the second diffusion preventing layer <NUM>, the third insulating layer <NUM> in a predetermined region is then removed by etching, and the etched portion is buried with copper (Cu) or the like. In addition, it is possible to form the third wiring layer <NUM>, the fourth wiring layer <NUM>, the first through-via <NUM>, the second through-via <NUM>, and the third through-via <NUM> by a similar method. Note that the third to fifth insulating layers <NUM>, <NUM>, and <NUM> may include SiOx or the like that can be easily etched with a hydrofluoric acid, and the third to fifth diffusion preventing layers <NUM>, <NUM>, and <NUM> may include SiC or the like with high etching resistance with respect to the hydrofluoric acid.

Next, the sixth insulating layer <NUM>, the sixth diffusion preventing layer <NUM>, and the seventh insulating layer <NUM> are laminated on the fifth diffusion preventing layer <NUM> by the CVD method, and the substrate <NUM> is then bonded to the surface of the seventh insulating layer <NUM> as illustrated in <FIG>. In addition, the thickness of the substrate <NUM> may be reduced by CMP or the like after the substrate <NUM> is bonded to the multilayered wiring layer.

The sixth and seventh insulating layers <NUM> and <NUM> may include SiOx or the like that can be easily etched with a hydrofluoric acid, and the sixth diffusion preventing layer <NUM> may include SiC or the like with high etching resistance with respect to the hydrofluoric acid. Also, the substrate <NUM> may be a silicon (Si) substrate.

Next, the through-hole <NUM> may be formed by removing the first insulating layer <NUM>, the first diffusion preventing layer <NUM>, and the substrate <NUM> in a partial region by using etching or the like as illustrated in <FIG>. In addition, the protective film <NUM> is formed on the substrate <NUM> and inside the through-hole <NUM>. The shape of the opening of the through-hole <NUM> may be a square shape with a side of <NUM> to <NUM>, and a plurality of through-holes <NUM> may be provided. The protective film <NUM> may be formed to have a film thickness of <NUM> to <NUM> by using SiC or the like with high etching resistance with respect to the hydrofluoric acid, for example. Here, since the protective film <NUM> is formed by using the ALD method, the protective film <NUM> is uniformly (conformally) formed on the substrate <NUM> and inside the through-hole <NUM>.

Next, the substrate <NUM> and the second insulating layer <NUM> are exposed by removing the protective film <NUM> while causing the protective side wall <NUM> to remain inside the through-hole <NUM> by etching back the entire surface of the protective film <NUM> as illustrated in <FIG>. Such etching back of the entire surface can be realized by performing etching with high perpendicular anisotropy, for example.

Next, the gap <NUM> is formed by introducing a diluted hydrofluoric acid into the second insulating layer <NUM> and the third insulating layer <NUM> via the through-hole <NUM> and performing wet watching as illustrated in <FIG>.

At this time, the etching hardly advances through the protective side wall <NUM> and the first to third diffusion preventing layers <NUM>, <NUM>, and <NUM> since the protective side wall <NUM> and the first to third diffusion preventing layers <NUM>, <NUM>, and <NUM> include SiC or the like with high etching resistance with respect to the hydrofluoric acid. Also, etching hardly advances through the first wiring layer <NUM>, the second wring layer <NUM>, and the first through-via <NUM> since the first wiring layer <NUM>, the second wiring layer <NUM>, and the first through-via <NUM> include a metal material such as copper (Cu) and have high etching resistance with respect to the hydrofluoric acid. Therefore, the region in which the gap <NUM> is formed is controlled depending on a region sandwiched between the first diffusion preventing layer <NUM> and the third diffusion preventing layer <NUM> in the laminating direction of the semiconductor device <NUM> and is controlled depending on a time during which the wet etching is performed in the in-plane direction of the semiconductor device <NUM>.

It is possible to manufacture the semiconductor device <NUM> according to the embodiment through the aforementioned process. Note that a sealing layer that includes an insulating material and blocks the opening of the through-hole <NUM> may be provided on the substrate <NUM> in order to prevent moisture and the like from entering the gap <NUM>.

In the method for manufacturing the semiconductor device <NUM> according to the embodiment, the gap <NUM> is formed inside the semiconductor device <NUM> after the thickness of the substrate <NUM> is reduced by the CMP. According to this, it is possible to suppress occurrence of cracking or the like in the CMP process since the gap <NUM> is formed in the semiconductor device <NUM> after the CMP process in which mechanical stress is applied.

As described above, it is possible to provide a hollow between the wiring layers <NUM> by the gap <NUM> provided inside and to thereby reduce wiring capacity according to the semiconductor device of the embodiment of the present disclosure. In this manner, it is possible to suppress delay in the wirings and to thereby realizing a high operation speed and lower power consumption according to the semiconductor device.

In addition, since the gap <NUM> is not provided in the insulating layers <NUM> provided on the surface of the multilayered wiring layer in the semiconductor device, it is possible to maintain mechanical strength of the entire semiconductor device. Further since the diffusion preventing layers <NUM> that protrude into the gap <NUM> are not generated in the semiconductor device, it is possible to prevent the diffusion preventing layers <NUM> with low mechanical strength from collapsing.

According to the semiconductor device of the embodiment of the present disclosure, it is possible to use the semiconductor device in a memory device, a logic circuit, or an image pickup device, for example, by changing semiconductor elements to be mounted thereon. In particular, it is possible to use the semiconductor device <NUM> according to the second embodiment of the present disclosure as an image pickup device of a rear surface irradiation type by mounting a color sensor as a semiconductor element.

Claim 1:
A semiconductor device comprising:
a multilayered wiring layer in which insulating layers (<NUM>) and diffusion preventing layers (<NUM>) are alternately laminated and a wiring layer (<NUM>) is provided inside an insulating layer (<NUM>, <NUM>, <NUM>, <NUM>);
a through-hole (<NUM>) that is provided to penetrate through at least one or more insulating layers (<NUM>) from one surface of the multilayered wiring layer and has an inside covered with a protective side wall layer (<NUM>); and
a gap (<NUM>) that is provided in at least one or more insulating layers (<NUM>) immediately below the through-hole (<NUM>), wherein at least a part of the wiring layer (<NUM>) is provided inside the gap (<NUM>).