Patent Description:
High-speed silicon photonic devices, such as, for example, optical modulators and photodiodes, include both optical and electronic elements. Many of the optical elements are formed in a silicon device layer on top of a buried oxide, BOX, or other insulating layer. The electrical conductivity of this silicon layer (e.g., the silicon slab that remains in areas surrounding the silicon device structures) can negatively impact the RF performance of the devices due to increased RF losses and additional parasitic elements. While this issue can in some cases be addressed by removing the silicon slab underneath RF metal pads and lines, fabrication considerations and optical device configurations preclude this solution in many instances. For example, in some devices, optical waveguides or other optical structures formed in the silicon layer take up real estate in the vicinity of metal pads and lines, significantly limiting the area from which silicon can be removed. Further, even in device-free regions, silicon removal across substantial areas may not be possible because of its tendency to undermine the structural integrity of the substrate. Accordingly, alternatives to simply removing silicon under metal lines and pads are desirable.

<CIT> discloses that in photonic integrated circuits implemented in silicon-on-insulator substrates, non-conductive channels formed in the silicon device layer and/or the silicon handle of the substrate in regions underneath radio-frequency transmission lines of photonic devices can provide breaks in parasitic conductive layers of the substrate, thereby reducing radio-frequency substrate losses.

<CIT> discloses an integrated circuit inductor structure that includes a shielding pattern that induces a plurality of small eddy currents to shield the magnetic energy generated by the inductor from the substrate of the IC. The IC inductor structure is formed on a Silicon on Insulator (SOI) substrate where the substrate of the SOI has high resistivity. The shielding pattern forms a checkerboard pattern that includes a plurality of conducting regions completely isolated from each other by oxide material. The inductor has a high quality factor and a high self-resonance frequency due to the effective shielding of electromagnetic energy from the substrate of the IC while not reducing the effective inductance of the inductor.

<CIT> discloses a silicon-on-insulator radio frequency device and a silicon on-insulator substrate are provided. In the silicon-on-insulator radio frequency device, a pit is formed on a surface of a high resistivity silicon plate which is close to a buried oxide layer. The pit may be filled with an insulating material, thereby increasing an equivalent surface resistance of the high resistivity silicon plate; or no insulating material is filled into the pit, that is, the pit remains a vacuum state or is only filled with air, which can increase the equivalent surface resistance of the high resistivity silicon plate as well. In such, an eddy current generated on a surface of the high resistivity silicon plate under the action of a radio frequency signal may be reduced. As a result, loss of the radio frequency signal is reduced and the linearity of the radio frequency signal is improved.

Described herein are approaches to reducing RF losses associated with integrated RF devices by increasing the average electrical resistivity (i.e., reducing the average conductivity) of the device layer at least in the vicinity of the metallization structures of the devices (such as metal lines and pads), and in some cases across the entire device layer except in areas defining semiconductor device structures. In comparative examples, increased resistivity is achieved by ion implantation of, e.g., hydrogen (H), helium (He), boron (B), lithium (Li), carbon (C), or other suitable materials. As claimed, the device layer is patterned to form disconnected islands separated by non-conductive (e.g., dielectric-filled) channels that serve to interrupt eddy currents induced in the device layer. These islands may decrease in size and increase in density towards the edges of the metallization structures, where eddy currents tend to be strongest.

In the following, RF loss reduction is described, for specificity, with respect to photonic devices implemented in silicon-on-insulator, SOI, substrates. As will be appreciated by those of ordinary skill in the art, however, the disclosed RF loss reduction approaches are not limited to photonic devices, but are equally applicable to any RF devices implemented in a semiconductor-on-insulator substrate, including RF electronic devices and sensors. Further, although the integrated devices are commonly implemented on SOI substrates, semiconductor materials other than silicon (e.g., germanium, indium phosphide, gallium arsenide, etc.) may also be used for the device layer and device structures (such as waveguides) formed therein.

<FIG> illustrates, in a schematic cross-sectional view, an example RF photonic structure <NUM> in accordance with various embodiments. The structure <NUM> includes optical and electronic device components formed on an SOI substrate that includes a handle layer <NUM> (made e.g., of silicon, diamond, or another suitable material) and, separated from the handle layer <NUM> by a buried oxide (BOX) or other dielectric layer (herein also generically "insulating layer") <NUM>, a silicon device layer <NUM>. A silicon waveguide and/or other silicon device structure <NUM> may be formed in the silicon device layer <NUM>. As shown, the silicon device structure <NUM> may result from a partial etch of the silicon device layer <NUM> that leaves a silicon slab <NUM> of smaller thickness than the original the device layer at least in the vicinity of the metallization structures of the devices (such as metal lines and pads), and in some cases across the entire device layer except in areas defining semiconductor device structures. In comparative examples, increased resistivity is achieved by ion implantation of, e.g., hydrogen (H), helium (He), boron (B), lithium (Li), carbon (C), or other suitable materials. As claimed, the device layer is patterned to form disconnected islands separated by non-conductive (e.g., dielectric-filled) channels that serve to interrupt eddy currents induced in the device layer. These islands may decrease in size and increase in density towards the edges of the metallization structures, where eddy currents tend to be strongest.

<FIG> illustrates, in a schematic cross-sectional view, an example RF photonic structure <NUM> in accordance with various embodiments. The structure <NUM> includes optical and electronic device components formed on an SOI substrate that includes a handle layer <NUM> (made e.g., of silicon, diamond, or another suitable material) and, separated from the handle layer <NUM> by a buried oxide (BOX) or other dielectric layer (herein also generically "insulating layer") <NUM>, a silicon device layer <NUM>. A silicon waveguide and/or other silicon device structure <NUM> may be formed in the silicon device layer <NUM>. As shown, the silicon device structure <NUM> may result from silicon device layer <NUM> across portions of the substrate. Alternatively, the contours of the silicon device structure <NUM> may be defined by channels etched into the silicon device layer <NUM> down to the insulating layer <NUM>. The RF photonic structure <NUM> may also include, alternatively or additionally to any silicon device structure(s) <NUM> in the silicon device layer, other semiconductor device structures (not shown), e.g., made of III-V or other compound semiconductor materials, disposed above the silicon device layer <NUM>. For instance, many laser diodes, photodiodes, optical amplifiers, and optical modulators include active device layers, or p-i-n layered structures, made of III-V material. The silicon device layer <NUM>, along with any semiconductor device structures formed in or on the silicon device layer <NUM>, may be covered in a top cladding layer <NUM>, of, e.g., an oxide or other dielectric. To enable application or read-out of an RF signal, the RF photonic structure <NUM> includes one or more metallization structures <NUM> embedded in (or alternatively disposed on) the top cladding layer <NUM>. As shown, the metallization structures <NUM> may include metal layers <NUM> at multiple levels above the silicon device layer <NUM>, connected by vertical metal vias <NUM>.

<FIG> provides a schematic top view of an example RF photonic structure <NUM> in accordance with various embodiments (such as, e.g., the structure <NUM> of <FIG>), further illustrating various types of metallization structures (e.g., <NUM>). As shown, the metallization structures may include, as one type, device metallization <NUM>, that is, metal disposed directly on one or more semiconductor device structures of the RF photonic device. Another type of metallization structure is a transmission line, which includes a pair of electrodes <NUM> connected to the two terminals of an RF voltage source. The electrodes <NUM> may run, for at least a portion of their length, along a semiconductor device formed in or on the silicon device layer, e.g., as shown, along both sides of a waveguide <NUM>. Further, the RF photonic structure <NUM> generally includes metal bonding pads <NUM> for bonding wire leads to the photonic chip, as well as general metal lines or traces <NUM> that can make electrical connections between metallization structures within a device, or run across the chip to form interconnects between multiple devices or between a device and the bonding pads (e.g., as shown, between the transmission line electrodes <NUM> and the bonding pads <NUM>).

<FIG> shows, as an example of an RF photonic structure with device metallization, a p-i-n diode structure <NUM>, as can be used in RF photonic devices such as laser diodes, photodiodes, or electro-absorption modulators. As shown in a cross-sectional view, the p-i-n diode may take the form of a layered structure with a narrower mesa <NUM> including the intrinsic and p-type layers <NUM>, <NUM> stacked on top of a wider strip of n-type material <NUM>. To establish electrical connections with the p-type and n-type layers <NUM>, <NUM> of the diode, a p-side metal contact via <NUM> may be disposed across the top p-type layer <NUM>, and n-side metal layers <NUM> may be disposed on the n-type layer <NUM> to both sides of the mesa <NUM>, with vertical contact vias <NUM>, in turn, extending from the n-side metal layers <NUM>. The contact vias <NUM>, <NUM> may extend to the top of the top cladding layer, where they may connect, directly or via metal lines, to metal bonding pads (not shown) constituting the electrical terminals of the photonic chip.

<FIG> and <FIG> show, as an example of an RF photonic structure including a transmission line, a waveguide-based Mach-Zehnder modulator <NUM>. As <FIG> shows in a top view, the Mach-Zehnder modulator <NUM> includes an incoming waveguide <NUM> that bifurcates into two interferometric waveguide arms <NUM>, <NUM>, which are then recombined into an outgoing waveguide <NUM>. Electrodes <NUM>, <NUM> of opposite polarity are disposed to both sides of the interferometric waveguide arms <NUM>, <NUM>, and are each connected to one of the interferometric waveguide arms <NUM>, <NUM> via contact traces <NUM>. An RF signal applied between these electrodes <NUM>, <NUM> can be used to electrooptically modulate the relative optical phase between light propagating along the two waveguide arms <NUM>, <NUM>, thereby modulating the optical signal amplitude in the outgoing waveguide <NUM>. As shown in cross-sectional view in <FIG>, each interferometer arm <NUM>, <NUM> may be implemented as a composite waveguide including a silicon rib waveguide <NUM> formed in the silicon device layer <NUM> and, disposed above the rib waveguide <NUM>, a III-V waveguide <NUM>. The contact traces <NUM> may connect to device metallization <NUM> on the III-V waveguides <NUM>.

In RF photonic devices, the desired electrooptic modulation of the optical properties of the semiconductor device structures, such as the refractive index of a waveguide or the absorption edge of an intrinsic diode layer, is generally accompanied by undesirable, parasitic electrical currents, including eddy currents induced in the silicon device layer by the varying magnetic field of the RF signal. These parasitic currents give rise to energy losses, which reduce the device performance, e.g., by lowering the modulation amplitude of an optical modulator, the signal strength of a photodiode, etc. In accordance with various embodiments, RF losses are reduced, and the RF performance of the device is accordingly increased, by modifying the silicon device layer to reduce its conductivity and, thus, the parasitic currents.

<FIG> is a schematic cross-sectional view of an example RF photonic structure <NUM>, otherwise as depicted in <FIG>, in which the silicon (or other semiconductor) device layer <NUM> is patterned with current-interrupting insulating channels <NUM> (depicted as vertical lines, only a few being labeled), in accordance with various embodiments. These channels <NUM> may be etched into the silicon device layer <NUM> and have a width, depending on process details, in the range between <NUM> and <NUM>, e.g., about <NUM>. The channels <NUM> may be filled with a dielectric material, e.g., as a result of the deposition of the top cladding layer <NUM> on top of the patterned silicon device layer <NUM>. As shown in top views in <FIG>, the channels are oriented in multiple directions (in a plane of the silicon device layer <NUM>) so as to intersect with or meet one another and, as a result, form a two-dimensional grid or network of channels that leaves disconnected regions of silicon, herein "silicon islands" or, more broadly, "semiconductor islands" in between the channels. In some embodiments, the silicon islands have dimensions in the range between about <NUM> and about <NUM>, or in the narrower range between about <NUM> and about <NUM>. By "cutting up" the silicon device layer <NUM> in this manner, eddy currents across the silicon device layer <NUM> are interrupted, and large-scale current loops are, thus, avoided. With reference again to <FIG>, the channels <NUM> preferably extend throughout the silicon device layer <NUM> all the way down to the insulating (e.g., BOX) layer <NUM>, such that the silicon islands are electrically isolated from one another, eliminating current flow between islands and confining eddy currents to the much smaller region within each island. However, even partially etched channels will tend to reduce overall eddy current flows across the silicon device layer <NUM>.

<FIG> is a schematic top view of an example RF photonic structure <NUM> in accordance with one embodiment, illustrating a rectangular grid channel pattern in the silicon device layer relative to the locations of the metallization structures <NUM>, <NUM>, <NUM>, <NUM> and waveguide <NUM> of <FIG>. In this example, the silicon device layer includes two sets of parallel, straight channels <NUM>, <NUM> (only a few channels of each set being labeled), the two sets intersecting one another to form a quadrilateral grid. More specifically, in the example shown, the channels <NUM> of one set are oriented parallel to the waveguide <NUM>, and the channels <NUM> of the other set are oriented perpendicular to the waveguide <NUM>, such that the channels <NUM>, <NUM> form a rectangular grid with rectangular silicon islands <NUM> (only a few being labeled). The channels <NUM>, <NUM> need not intersect at right angles, however, and may instead define parallelogram-shaped silicon islands. Further, a third set of parallel channels may intersect the first and second sets at their intersection points to form a triangular grid. Additional configurations of grid lines may occur to those of ordinary skill in the art.

As shown in <FIG>, the grid formed by the intersecting channels <NUM>, <NUM> need not be uniform, but spacings between channels may vary, resulting in silicon islands <NUM> of varying size across the silicon device layer. The channels <NUM>, <NUM> may be particularly densely spaced, and form the smallest silicon islands <NUM>, in regions directly below the metallization structures <NUM>, <NUM>, <NUM>, <NUM>, or the immediately surrounding regions. Towards greater distances from the metallization structures <NUM>, <NUM>, <NUM>, <NUM>, the spacings between adjacent channels <NUM>, <NUM> may increase, or channels may even disappear altogether, as generally indicated for the regions <NUM> away from bonding pads, transmission lines, and device metallization. This decreasing channel density with increasing distance from the metallization structures reflects that the induced eddy currents are, at greater distances, lower in magnitude in the first place. Further, even near metallization structures, channels may be omitted from regions of the silicon device layer that define silicon device structures or include other (e.g., III-V) semiconductor device structures disposed above the silicon, to avoid interfering with the device function. For example, <FIG> shows a strip <NUM> surrounding the waveguide <NUM> in which the silicon slab remains free of channels.

<FIG> is a schematic top view of an example RF photonic structure <NUM> in accordance with one embodiment, illustrating a triangulation channel patterning in the silicon device layer relative to the locations of the metallization structures <NUM>, <NUM>, <NUM>, <NUM> and waveguide <NUM> of <FIG>. In this example, the channels <NUM> form short segments at various orientations, meeting in groups of three or more channels at the vertices of a channel network that triangulates the arear of the silicon device layer. Similarly to the RF photonic structure <NUM> with a rectangular grid channel pattern, the channel density may be higher, and the silicon islands correspondingly smaller, in the vicinity of the metallization structures. In some embodiment, the islands may be smallest in regions underneath the edges of a metallization structure, as most clearly shown in <FIG> for the metal bonding pads <NUM> and associated contact traces <NUM>. The waveguide <NUM> is, just as in <FIG>, flanked on both sides by a strip of non-patterned, channel-free silicon.

The two channel patterns depicted in <FIG> are, of course, merely examples, and other channel configurations that dissect the silicon device layer into a plurality of disconnected silicon islands will occur to those of ordinary skill in the art. In general, the silicon islands are located, or concentrated in number and density, in regions where the RF currents are strongest and where the insulating channels, therefore, achieve the greatest performance improvements. These regions generally include the portions of the silicon device layer underneath and/or (laterally) surrounding, in whole or in part, the metallization structures, and especially the regions along edges of the metallization structures. It may not always be possible to fully surround a metallization structure because of nearby semiconductor device components. For example, a silicon waveguide in the region between the electrodes of a transmission line may preclude patterning the area underneath or between the inner edges of the electrodes, but, in this case, patterning underneath and around the outer edges of the electrodes can still effect a significant reduction in RF losses.

Patterning of the silicon device layer with electrically insulating channels that define disconnected silicon islands, as shown in <FIG>, can interrupt the free flow of RF-induced eddy currents and, as such, reduce the average electrical conductivity of the silicon device layer. Beneficially, this conductivity reduction (or resistivity increase) is achieved by removal of only a small fraction (e.g., less than <NUM>% in some embodiments) of the silicon material in the silicon device layer, maintaining much of the structural support provided by this layer. Limiting material removal to a small fraction can also serve, in some cases, to satisfy layer density balance requirements imposed by the fabrication process.

A comparative approach to increasing the electrical resistivity of the silicon device layer (in regions underneath and/or fully or partially surrounding the metallization structures) is by ion implantation. In this process, ions of a suitable material, such as, e.g., H, He, B, Li, or C are accelerated towards and into the SOI substrate (generally prior to any patterning of the silicon device layer), with ion implantation parameters chosen to cause a reduction of the conductivity of the silicon device layer. In general, ion implantation can lead to crystalline defects in the silicon lattice that are electrically active, and can increase the resistivity of the silicon layer. In some examples, a resistivity increase by two to three orders of magnitude is achieved. Ion implantation parameters that can be adjusted to achieve the desired resistivity increase include, in addition to the type of ions, the ion energy (as they are impending on the substrate), the ion dosage, and various annealing parameters (e.g., annealing duration, temperature, temperature slope, and ambient gas). Suitable combinations of ion implantation parameters are known to those of ordinary skill in the art. To provide just one example, hydrogen ion implantation may use <NUM> KeV H+ ions at a dose between <NUM><NUM> and <NUM>·<NUM><NUM> ions per cm<NUM>, and the H+ implantation may be followed by thermal annealing in two stages: rapid thermal annealing (e.g., over a period of about one minute, with a steep temperature slope of about <NUM>/s and a plateau of about <NUM>), and thereafter conventional thermal annealing (e.g., for a duration in a range between several minutes and two hours, at a temperature of about <NUM>). When ion implantation is used to increase the resistivity of the silicon layer, the layer areas that have functional roles (e.g., include semiconductor device structures) are generally masked prior to implantation.

<FIG> is a flow chart of a method <NUM> of manufacturing RF photonic structures that, in comparative approaches, incorporates steps for increasing the resistivity of the silicon device layer at least near metallization structures. The method <NUM> begins with providing, at step <NUM>, a (plain) SOI substrate (or, more generally, semiconductor-on-insulator substrate). In comparative examples, the electrical resistivity of the silicon (or other semiconductor) device layer is increased by ion implantation. In this case, a masking layer is first deposited on the silicon device layer and patterned to mask at least areas of the device layer where sensitive structures, such as semiconductor device structures, will be placed (<NUM>). The exposed areas of the silicon device, including, in particular, regions where the metallization structures will be located, are then treated by ion implantation to increase resistivity (<NUM>). The silicon device layer is then photolithographically patterned and etched (herein collectively "patterned"), in one or more steps, to form silicon device structures and/or insulating channels that dissect regions outside the device structure(s) and near locations where metallization structures are to be placed into a plurality of disconnected silicon islands (<NUM>). (In the case of a substrate with resistivity-increasing ions implanted in the silicon device layer, creating the insulating channels is optional. ) Depending on the particular structure and etch depths of the silicon device structure(s), these structures (or portions thereof) and the insulating channels may be created simultaneously or in separate steps. For example, a ridge waveguide, whose sidewalls extend all the way down to the insulating layer of the substrate, can be defined and etched in the same step as the insulating channels. A rib waveguide, which extends from an underling slab of silicon, on the other hand, may be created by a partial etch of the silicon device layer before the remaining silicon slab is photolithographically patterned and fully etched to form the insulating channels.

Following patterning of the silicon device layer, additional semiconductor device structures may be created on top of the silicon device layer (<NUM>). For instance, in some embodiments, a layer of another semiconductor material (e.g., silicon nitride) is deposited and patterned to form additional device structures (e.g., silicon nitride waveguides). In other embodiments, compound semiconductor (e.g., III-V) die are bonded to the silicon device layer and then patterned, e.g., to form mesa structures. In some embodiments, surfaces of some of the semiconductor device structures are metallized, e.g., to form electrical contact layers (<NUM>). A top dielectric cladding may then be disposed over the substrate and semiconductor device structures (<NUM>). Metallization structures may be created in and on the top dielectric cladding by photolithographically patterning and etching the cladding to form via holes, which are thereafter filled with metal to form vertical metal vias (<NUM>), and/or by depositing and patterning metal layers to create horizontal metal structures (<NUM>). Deposition and patterning of dielectric and metal layers may be repeated alternatingly to form metallization structures at multiple levels (including, e.g., metal bonding pads at the top), with metal vias vertically connecting the different levels. The method <NUM> ends with a completed RF photonic structure (at <NUM>) within a PIC, ready for integration and packaging with electronic circuit chips.

Thus, from one perspective, there has now been discusses how, in radio-frequency (RF) devices integrated on semiconductor-on-insulator (e.g., silicon-based) substrates, RF losses are expected to be reduced by increasing the resistivity of the semiconductor device layer in the vicinity of (e.g., underneath and/or in whole or in part surrounding) the metallization structures of the RF device, such as, e.g., transmission lines, contacts, or bonding pads. Increased resistivity is expected to be achieved, by patterning the device layer to create disconnected semiconductor islands.

Claim 1:
A radio-frequency, RF, structure comprising:
a substrate comprising a semiconductor device layer disposed on an insulating layer;
formed in or on the semiconductor device layer, a semiconductor device structure of an integrated RF device; and
disposed in or on a cladding layer above the semiconductor device layer and the semiconductor device structure, at least one metallization structure to carry an RF signal to or from the integrated RF device,
wherein the semiconductor device layer is patterned to form a plurality of insulating channels which are oriented in multiple directions so as to intersect with or meet one another and thereby form disconnected semiconductor islands in between the channels, the disconnected semiconductor islands extending at least over a region that at least partially surrounds the at least one metallization structure.