Patent Description:
With the development of semiconductor integration technology, a system on chip (SOC) has emerged in which blocks that respectively perform functions that are conventionally implemented using separate independent chips is integrated into one chip. A system on a chip may be used in a variety of electronic devices. A system on a chip may include a processor and peripheral blocks connected to the processor. A system on a chip may include a bus that connects the processor and the peripheral blocks to each other.

At least one of the peripheral blocks included in the system-on-chip may perform serial communication with other peripheral blocks included in the system-on-chip or a chip or a semiconductor device outside the system-on-chip. The block performing the serial communication may be referred to as a serial communication interface. The serial communication interface may perform the serial communication with the other peripheral blocks or the chip outside the system-on-chip while complying with a pre-agreed serial communication standard.

For example, as shown in <FIG>, in a semiconductor device as the system-on-chip, a processor <NUM> is connected to an input/output data converter <NUM> and a GPIO (general-purpose input/output) input/output unit <NUM> via a bus <NUM>. The input/output data converter <NUM> is connected to a plurality of pads <NUM> via a first input/output line <NUM>, and the GPIO input/output unit <NUM> is connected to the plurality of pads <NUM> via a second input/output line <NUM>. Specifically, the input/output data converter <NUM> may be connected to a multiplexer MUX via the first input/output line <NUM> to input or output data via the plurality of pads <NUM>, and may input or output the data from or to a pad <NUM> selected by the multiplexer MUX. Furthermore, the GPIO input/output unit <NUM> may be connected to the multiplexer MUX via the second input/output line <NUM> to input or output data via the plurality of pads <NUM>, and may input or output the data from or to a pad <NUM> selected by the multiplexer MUX.

That is, the conventional semiconductor device requires each input/output line and the multiplexer MUX to control the data input from or output to the pad from the plurality of peripheral blocks. Thus, line complexity may be increased, and an area of the semiconductor device may be increased.

<CIT> discloses a semiconductor integrated circuit including a central processing unit, a hardware function block that outputs a plurality of hardware signals to be transmitted to an external device independently of the central processing unit, a virtual general purpose input/output (GPIO) finite state machine that transforms the plurality of hardware signals to a virtual GPIO payload, and an I3C communication block that transmits the virtual GPIO payload to the external device through a serial data line and a serial clock line. <CIT> discloses a method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

A technical purpose of the present disclosure is to provide a semiconductor device capable of reducing internal line pattern complexity of the semiconductor device and reducing an area of the semiconductor device.

A semiconductor device includes a processor that processes input data received via a bus and transmits the process input data as output data via the bus; an input/output data converter that receives the output data via the bus, converts the output data into transmit preGPIO data, and transmits the transmit preGPIO data to the bus; and a GPIO input/output unit that receives the transmit preGPIO data via the bus, converts the transmit preGPIO data into transmit GPIO data, and outputs the transmit GPIO data to at least one GPIO pad, wherein the input/output data converter is configured to convert the output data into transmit protocol data corresponding to a communication protocol of the output data, and convert the transmit protocol data into the transmit preGPIO data.

The semiconductor device of the present disclosure converts a communication protocol into data in a specific form and transmits the data in the specific form via the bus. Thus, the complexity of the internal line pattern may be reduced.

Furthermore, in the semiconductor device of the present disclosure, a multiplexer (MUX) that controls input/output of data may be omitted. Thus, the area of the semiconductor device may be minimized.

In the following optional features are provided, which might be combined with the general concept as mentioned independently or in combination.

In one or more embodiments, the transmit protocol data may include at least one protocol data transmitted in parallel via at least one line.

In one or more embodiments, wherein the input/output data converter may be configured to convert the at least one protocol data into serial data based on a timing to convert the transmit protocol data into the transmit preGPIO data.

In one or more embodiments, the transmit preGPIO data may be composed of a number of bits corresponding to a number of GPIO pads.

In one or more embodiments, the input/output data converter may be configured to: receive data about a data transmit bit corresponding to a GPIO pad allocated to communication of the output data; and convert the transmit protocol data to the transmit preGPIO data including serial data in the data transmit bit of the transmit preGPIO data, wherein the transmit protocol data is converted to the serial data based on a timing.

In one or more embodiments, the GPIO input/output unit may be configured to convert the transmit preGPIO data into the transmit GPIO data by applying a transmit mask to the transmit preGPIO data to extract only a bit corresponding to the GPIO pad allocated to communication of the transmit preGPIO data.

In one or more embodiments, the GPIO input/output unit may be configured to convert receive GPIO data received from at least one GPIO pad into receive preGPIO data and transmit the receive preGPIO data to the input/output data converter via the bus.

In one or more embodiments, the input/output data converter may be configured to convert the receive preGPIO data into input data and transmit the input data via the bus.

In one or more embodiments, the input/output data converter may be configured to convert the receive preGPIO data into parallel data based on a timing to convert the receive preGPIO data into receive protocol data including the at least one protocol data.

In one or more embodiments, the receive protocol data may include the at least one protocol data transmitted in parallel via at least one line.

In one or more embodiments, the GPIO input/output unit may be configured to convert the receive GPIO data into the transmit preGPIO data by applying a receive mask to the receive GPIO data to extract only a bit corresponding to the GPIO pad allocated to communication of the receive GPIO data.

In another aspect of the present disclosure a communication method in a semiconductor device is provided, the method comprising: receiving, by an input/output data converter, output data via a bus; converting, by the input/output data converter, the output data into transmit protocol data; converting, by the input/output data converter, the transmit protocol data into transmit preGPIO data; and converting, by a GPIO input/output unit, the transmit preGPIO data into transmit GPIO data; and transmitting, by the GPIO input/output unit, the transmit GPIO data to a GPIO pad via the bus.

In one or more embodiments, the transmit protocol data may include at least one protocol data transmitted in parallel.

In one or more embodiments, converting the transmit protocol data into the transmit preGPIO data may include converting, by the input/output data converter, the at least one protocol data into serial data based on a timing to convert the transmit protocol data into the transmit preGPIO data.

In one or more embodiments, converting the transmit protocol data into the transmit preGPIO data may include receiving, by the input/output data converter, data about a data transmit bit corresponding to a GPIO pad allocated to communication of the output data; and converting, by the input/output data converter, the transmit protocol data to the transmit preGPIO data including serial data in the data transmit bit of the transmit preGPIO data, wherein the transmit protocol data is converted to the serial data based on a timing.

In one or more embodiments, converting, by the GPIO input/output unit, the transmit preGPIO data into the transmit GPIO data may include converting, by the GPIO input/output unit, the transmit preGPIO data into the transmit GPIO data by applying a transmit mask to the transmit preGPIO data to extract only a bit corresponding to the GPIO pad allocated to communication of the transmit preGPIO data.

In one or more embodiments, the method may further comprise: receiving, by the GIPO input/output unit, receive GPIO data from a GPIO pad via the bus; converting, by the GIPO input/output unit, the receive GPIO data into receive preGPIO data; converting, by the input/output data converter, the receive preGPIO data into receive protocol data; converting, by the input/output data converter, the receive protocol data into input data; and transmitting, by the input/output data converter, the input data via the bus.

In one or more embodiments, the receive protocol data may include at least one protocol data transmitted in parallel via at least one line.

In one or more embodiments, converting, by the input/output data converter, the receive preGPIO data into the receive protocol data may include converting, by the input/output data converter, the receive preGPIO data into parallel data based on a timing to convert the receive preGPIO data into receive protocol data including the at least one protocol data.

In one or more embodiments, converting, by the GPIO input/output unit, the receive GPIO data to the receive preGPIO data may include converting, by the GPIO input/output unit, the receive GPIO data into the transmit preGPIO data by applying a receive mask to the receive GPIO data to extract only a bit corresponding to the GPIO pad allocated to communication of the receive GPIO data.

The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the present disclosure and together with the description serve to describe the principle of the present disclosure. In the drawings:.

Advantages and features of the present disclosure, and a method of achieving the advantages and features will become apparent with reference to embodiments described later in detail together with the accompanying drawings.

For simplicity and clarity of illustration, elements in the drawings are not necessarily drawn to scale. The same reference numbers in different drawings represent the same or similar elements, and as such perform similar functionality.

A shape, a size, a ratio, an angle, a number, etc. disclosed in the drawings for describing embodiments of the present disclosure are illustrative.

As used herein, the singular constitutes "a" and "an" are intended to include the plural constitutes as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprise", "comprising", "include", and "including" when used in this specification, specify the presence of the stated features, integers, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and/or portions thereof. As used herein, the term "and/or" includes any and all combinations of one or more of associated listed items. Expression such as "at least one of" when preceding a list of elements may modify the entire list of elements and may not modify the individual elements of the list. In interpretation of numerical values, an error or tolerance therein may occur even when there is no explicit description thereof.

It will be understood that when an element or layer is referred to as being "connected to", or "connected to" another element or layer, it may be directly on, connected to, or connected to the other element or layer, or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

In descriptions of temporal relationships, for example, temporal precedent relationships between two events such as "after", "subsequent to", "before", etc., another event may occur therebetween unless "directly after", "directly subsequent" or "directly before" is not indicated.

When a certain embodiment may be implemented differently, a function or an operation specified in a specific block may occur in a different order from an order specified in a flowchart. For example, two blocks in succession may be actually performed substantially concurrently, or the two blocks may be performed in a reverse order depending on a function or operation involved.

Thus, a first element, component, region, layer or section described under could be termed a second element, component, region, layer or section, without departing from the scope of the present disclosure.

The features of the various embodiments of the present disclosure may be partially or entirely combined with each other, and may be technically associated with each other or operate with each other. The embodiments may be implemented independently of each other and may be implemented together in an association relationship.

In interpreting a numerical value, the value is interpreted as including an error range unless there is no separate explicit description thereof.

Hereinafter, a semiconductor device of an embodiment of the present disclosure will be described in detail with reference to <FIG>.

<FIG> is a block diagram of a semiconductor device of an embodiment of the present disclosure. <FIG> is a block diagram of an input/output data converter of an embodiment of the present disclosure, and <FIG> is a diagram showing a structure of data received by a GPIO data converter from a processor of an embodiment of the present disclosure. <FIG> is an example block diagram of an input/output data converter of an embodiment of the present disclosure. <FIG> is a diagram showing a signal transmitted from an input/output data converter to a GPIO input/output unit of an embodiment of the present disclosure. <FIG> is a diagram showing a signal input from a GPIO input/output unit to an input/output data converter of an embodiment of the present disclosure. <FIG> is a block diagram of a bus communication data converter of an embodiment of the present disclosure. <FIG> is a diagram showing a signal transmitted from a bus communication data converter to a GPIO input/output unit of an embodiment of the present disclosure. <FIG> is a diagram showing a signal received by a bus communication data converter from a GPIO input/output unit of an embodiment of the present disclosure. <FIG> is a block diagram of a GPIO input/output unit of an embodiment of the present disclosure. <FIG> is a diagram illustrating a process of converting transmit preGPIO data into transmit GPIO data in a GPIO input/output unit of an embodiment of the present disclosure. <FIG> is a diagram illustrating a process of converting receive preGPIO data into receive GPIO data in a GPIO input/output unit of an embodiment of the present disclosure.

Referring to <FIG>, a semiconductor device of an embodiment of the present disclosure includes a processor <NUM>, an input/output data converter <NUM>, a GPIO input/output unit <NUM>, a bus <NUM>, a GPIO input/output line <NUM>, and at least one pad <NUM>.

The processor <NUM> may process input data RX_data received from the input/output data converter <NUM> and transmit the processed data as output data TX_data. For example, the processor <NUM> may be a timing controller or a display driving integrated circuit for providing image data to a display device, a memory controller for controlling memory devices, or a central processing unit (CPU) that operates based on software in a memory. However, the present disclosure is not limited thereto, and as described above, the processor <NUM> may be a component that processes the input data and outputs processed data.

As shown in <FIG>, the input/output data converter <NUM> converts output data TX_data received from the processor <NUM> via the bus <NUM> into transmit preGPIO data TX_preGPIO_data and outputs the transmit preGPIO data TX_preGPIO_data to the GPIO input/output unit <NUM> via the bus <NUM>, and converts receive preGPIO data RX_preGPIO_data received from the GPIO input/output unit <NUM> into input data RX_data and outputs the input data RX_data to the processor <NUM> via the bus <NUM>. In this regard, the output data TX_data received from the processor <NUM> includes first to third output data TX_data1 to TX_data3, as shown in <FIG>. The first output data TX_data1 indicates information about the communication protocol of the output data TX_data, and may have different values depending on the communication protocol of the output data TX_data. The second output data TX_data2 indicates information about a GPIO pad from which the data is output among the GPIO pads <NUM>. Furthermore, the third output data TX_data3 includes the data processed by the processor <NUM> as described above. For example, the output data TX_data may include the first output data TX_data1 having a value of "<NUM>(<NUM>)" meaning a SPI protocol, the second output data TX_data2 having a value of "<NUM><NUM><NUM>" indicating using middle <NUM> GPIO pads among <NUM> GPIO pads, and the third output data TX_data3 as the data processed by the processor <NUM> having a value of "<NUM><NUM>(0x5A)". Although not shown, like the output data TX_data, the input data RX_data may include first input data RX_data1 as information about a communication protocol, second input data RX_data2 as information about a GPIO pad to which the data is input among the GPIO pads <NUM>, and third input data RX_data3 as the data input to the GPIO pad.

As shown in <FIG>, the input/output data converter <NUM> may include a serial/parallel converter <NUM>, a communication protocol controller <NUM>, and a Pre-GPIO data converter <NUM>.

The serial/parallel converter <NUM> may convert the output data TX_data received from the processor <NUM> via the bus <NUM> and the input data RX_data received from the communication protocol controller <NUM> via the bus <NUM> into serial or parallel data. For example, the serial/parallel converter <NUM> may convert the output data TX_data received in parallel from the processor <NUM> into serial data or may convert the input data RX_data received in serial from the communication protocol controller <NUM> into parallel data. However, the present disclosure is not limited thereto, and the serial/parallel converter <NUM> may convert the output data TX_data received in serial from the processor <NUM> into parallel data, or may convert the input data RX_data received in parallel from the communication protocol controller <NUM> into serial data.

The communication protocol controller <NUM> converts the output data TX_data having been converted into the serial or parallel data into transmit protocol data TX_prtc_data corresponding to a corresponding communication protocol and transmits the transmit protocol data TX_prtc_data to the Pre-GPIO data converter <NUM>. In this regard, the transmit protocol data TX_prtc_data may include at least one protocol data according to the protocol of the output data TX_data. Specifically, the transmit protocol data TX_prtc_data includes at least one protocol data according to the communication protocol corresponding to the first output data TX_data1 of the output data TX_data. For example, when the protocol of the output data TX_data is a SPI (Serial Peripheral Interface) communication protocol, the communication protocol controller <NUM> may convert the received output data TX_data to the transmit protocol data TX_prtc_data according to the SPI communication protocol, as shown in <FIG>. In this regard, the transmit protocol data TX_prtc_data may include SPI clock data SPI_CLK, SPI chip select data SPI_CS, and SPI transmit data SPI_TXD as protocol data. Although described based on the SPI protocol, the present disclosure is not limited thereto. As described above, the transmit protocol data TX_prtc_data may include at least one protocol data according to the communication protocol of the output data TX_data. For example, the communication protocol controller <NUM> may convert the output data TX_data to data based on the serial communication protocol such as I2C (Inter-Integrated Circuit) communication protocol and UART (Universal Asynchronous Receiver/Transmitter) communication protocol other than the SPI communication protocol. The communication protocol controller <NUM> may convert the output data TX_data to data based on a communication protocol other than the aforementioned communication protocol.

The communication protocol controller <NUM> converts receive protocol data RX_prtc_data received from the Pre-GPIO data converter <NUM> into the input data RX_data and transmits the input data RX_data to the serial/parallel converter <NUM>. Specifically, the communication protocol controller <NUM> extracts receive preGPIO data RX_preGPIO_data and converts the extracted data into the receive protocol data RX_prct_data based on a timing at which the data is transmitted. That is, the communication protocol controller <NUM> extracts the receive preGPIO data RX_preGPIO_data, and converts the extracted data into parallel data based on the timing at which the data is transmitted to convert the same into the receive protocol data RX_prct_data.

In this regard, the receive protocol data TX_prtc_data may include at least one protocol data according to the corresponding communication protocol. For example, when the protocol of the receive protocol data RX_prtc_data received from the Pre-GPIO data converter <NUM> is the SPI (Serial Peripheral Interface) communication protocol, the communication protocol controller <NUM> may receive the receive protocol data RX_prtc_data including the SPI receive data SPI_RXD as the protocol data, and may convert the receive protocol data RX_prtc_data into the input data RX_data, and may transmit the input data RX_data to the serial/parallel converter <NUM>, as shown in <FIG>. Although described based on the SPI protocol, the present disclosure is not limited thereto. As described above, the receive protocol data RX_prtc_data may include data transmitted via at least one line according to the corresponding communication protocol. For example, the communication protocol controller <NUM> may convert the receive protocol data RX_prtc_data based on the serial communication protocols such as the I2C (Inter-Integrated Circuit) communication protocol and the UART (Universal Asynchronous Receiver/Transmitter) communication protocol other than the SPI communication protocol into the input data RX_data. The receive protocol data RX_prtc_data may be data of a communication protocol other than the aforementioned communication protocol.

Furthermore, the communication protocol controller <NUM> may receive transmission speed data, and data about a size of one-time transmitted or received data from the processor <NUM>, and may set a speed at which the transmit protocol data TX_prtc_data is transmitted, and the receive protocol data RX_prct_data is received, and the size of one-time transmitted or received data. For example, the communication protocol controller <NUM> may set the transmission speed to <NUM> ns, and may set the size of one-time transmitted data to <NUM> bits.

The pre-GPIO data converter <NUM> converts transmit protocol data TX_prct_data received from communication protocol controller <NUM> into transmit preGPIO data TX_preGPIO_data and transmits the transmit preGPIO data TX_preGPIO_data to the GPIO input/output unit <NUM> via the bus <NUM>. The pre-GPIO data converter <NUM> converts receive preGPIO data RX_preGPIOdata received from the GPIO output unit <NUM> into receive protocol data RX_prct_data and transmits the receive protocol data RX_prct_data to the communication protocol controller <NUM> via the bus <NUM>. To this end, the Pre-GPIO data converter <NUM> includes a transmit data converter <NUM>, a receive data converter <NUM>, and a transmit/receive controller <NUM>.

As shown in <FIG>, the transmit data converter <NUM> converts the transmit protocol data TX_prct_data received from the communication protocol controller <NUM> into the transmit preGPIO data TX_preGPIO_data and transmits the transmit preGPIO data TX_preGPIO_data to the transmit/receive controller <NUM>. Specifically, the transmit data converter <NUM> extracts the transmit protocol data TX_prct_data based on a timing at which the data is transmitted, and converts the extracted data into the transmit preGPIO data TX_preGPIO_data. That is, the transmit data converter <NUM> converts the transmit protocol data TX_prct_data transmitted in parallel into serial data based on the timing at which the data is transmitted to convert the same into the transmit preGPIO data TX_preGPIO_data. For example, when the communication protocol of the transmit protocol data TX_prtc_data is the SPI communication protocol, the transmit data converter <NUM> receives the transmit protocol data TX_prtc_data including the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD from the communication protocol controller <NUM>. As shown in <FIG>, the transmit data converter <NUM> may divide the received transmit protocol data TX_prct_data including the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD based on the timing at which the data is transmitted to convert the received transmit protocol data TX_prct_data into the transmit preGPIO data TX_preGPIO_data. That is, the transmit data converter <NUM> converts the transmit protocol data TX_prct_data transmitted in parallel into the serial data based on the timing at which the data is transmitted to convert the same into the transmit preGPIO data TX_preGPIO_data. Accordingly, the transmit data converter <NUM> may convert the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD to the transmit preGPIO data TX_preGPIO_data including "<NUM>", "<NUM>" and "<NUM>" as respective values of the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD transmitted at a first timing, and may convert the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD to the transmit preGPIO data TX_preGPIO_data including "<NUM>", "<NUM>" and "<NUM>" as respective values of the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD transmitted at a second timing.

According to an embodiment of the present disclosure, the transmit preGPIO data TX_preGPIO_data is composed of the number of bits corresponding to the number of GPIO pads. Specifically, the transmit data converter <NUM> may receive transmit bit data as data about data transmit bits corresponding to the GPIO pads <NUM> allocated to communication of the output data TX_data, from the processor <NUM>. Accordingly, for example, a fifth GPIO pad, a sixth GPIO pad, and a seventh GPIO pad of the GPIO pads <NUM> may be allocated to the output data TX_data transmission. Thus, the transmit data converter <NUM> may receive, from the processor <NUM>, the data indicating that the fifth bit, the sixth bit, and the seventh bit are allocated to the communication of the output data TX_data as the data indicating the data transmit bits corresponding to the allocated GPIO pads. As shown in <FIG>, the transmit preGPIO data TX_preGPIO_data composed of <NUM> bits corresponding to the <NUM> GPIO pads includes the SPI clock data SPI_CLK, the SPI chip select data SPI_CS and the SPI transmit data SPI_TXD output at the same timing in the 5th, 6th and 7th bits, respectively.

To this end, although not shown, the transmit data converter <NUM> may include a transmit register that receives the transmit protocol data TX_prtc_data, and a transmit bit select setting unit for generating the transmit preGPIO data TX_preGPIO_data in which the transmit protocol data TX_prtc_data is included in the corresponding bit, using the transmit bit data.

As shown in <FIG>, the receive data converter <NUM> converts the receive preGPIO data RX_preGPIO_data received from the transmit/receive controller <NUM> into the receive protocol data RX_prct_data and transmits the receive protocol data RX_prct_data to the input/output data converter <NUM>. For example, when the communication protocol of the receive protocol data RX_prtc_data is the SPI communication protocol, the receive data converter <NUM> sequentially receives the receive preGPIO data RX_preGPIO_data, and converts the receive preGPIO data RX_preGPIO_data into the receive protocol data RX_prct_data including the SPI receive data SPI_RXD and transmits the receive protocol data RX_prct_data to the input/output data converter <NUM>, as shown in <FIG>.

According to an embodiment of the present disclosure, the receive preGPIO data RX_preGPIO_data is composed of the number of bits corresponding to the number of the GPIO pads. Specifically, the transmit data converter <NUM> may receive data about data receive bits corresponding to the GPIO pads <NUM> to which the receive protocol data RX_prct_data is output, from the processor <NUM>. Accordingly, for example, the eighth pad of the GPIO pad <NUM> from the processor <NUM> is allocated to the reception of the input data RX data, and the receive data converter <NUM> receives data indicating that the eighth bit is allocated to the reception of the input data RX_data as the data about the data receive bit corresponding to the allocated GPIO pad from the processor <NUM>. As shown in <FIG>, the receive data converter <NUM> may extract the 8th bit of the receive preGPIO data RX preGPIO data composed of <NUM> bits corresponding to the <NUM> GPIO pads to convert the same into the receive protocol data RX prct data.

To this end, although not shown, the receive data converter <NUM> may include a receive register that receives the receive preGPIO data RX preGPIO data received from the transmit/receive controller <NUM>, and a receive bit select setting unit for extracting the data of the corresponding bit from the receive preGPIO data RX preGPIO data using the receive bit data received from the processor <NUM> to generate the protocol data RX prct data.

The transmit/receive controller <NUM> transmits the converted transmit preGPIO data TX preGPIO data from the transmit data converter <NUM> along with an address ADDR of the GPIO pad to which the transmit preGPIO data TX preGPIO data is to be output to the GPIO input/output unit <NUM> via the bus <NUM>. The transmit/receive controller <NUM> transmits the receive preGPIO data RX preGPIO data received from the GPIO input/output unit <NUM> to the receive data converter <NUM>. To this end, although not shown, the transmit/receive controller <NUM> may include an address setting unit for setting an address to which the transmit preGPIO data TX preGPIO data or the receive preGPIO data RX preGPIO data is to be transmitted, and a timing controller for controlling transmission or reception of the data in response to a timing of the communication protocol.

The input/output data converter <NUM> converts the transmit protocol data TX prtc data into the transmit preGPIO data TX preGPIO data and transmits the transmit preGPIO data TX preGPIO data to the GPIO input/output unit <NUM> via the bus <NUM>. The input/output data converter <NUM> converts the receive preGPIO data RX preGPIO data input from the GPIO input/output unit <NUM> via the bus <NUM> into the receive protocol data RX prtc data. Thus, the line patterns for outputting the transmit protocol data TX prtc data and the receive protocol data RX prtc data via the GPIO pads <NUM> may be omitted to reduce the complexity of the internal line pattern and minimize the area of the semiconductor device.

The GPIO input/output unit <NUM> converts the transmit preGPIO data TX preGPIO data into the transmit CPIO data TX CPIO data and transmits the transmit CPIO data TX CPIO data to at least one GPIO pad <NUM>. Furthermore, the GPIO input/output unit <NUM> converts the receive GPIO data RX GPIO data to the receive preGPIO data RX preGPIO data and transmits the receive preGPIO data RX GPIO data to the input/output data converter <NUM>. Specifically, the GPIO input/output unit <NUM> may convert the transmit preGPIO data TX preGPIO data received from the input/output data converter <NUM> to the transmit GPIO data TX GPIO data by applying a transmit mask TX MASK to the transmit preGPIO data TX preGPIO data so that only the GPIO pad <NUM> allocated to the communication of the corresponding data is controlled. Then, the GPIO input/output unit <NUM> transmits the transmit GPIO data TX_GPIO_data to at least one GPIO pad <NUM>. To this end, the GPIO input/output unit <NUM> includes a GPIO data converter <NUM>, a GPIO output unit <NUM>, and a GPIO input unit <NUM>.

The GPIO data converter <NUM> converts the transmit preGPIO data TX_preGPIO_data into the transmit GPIO data TX_GPIO_data. Specifically, the GPIO data converter <NUM> converts the transmit preGPIO data TX_preGPIO_data received from the input/output data converter <NUM> to the transmit GPIO data TX_GPIO_data by applying the transmit mask TX_MASK to the transmit preGPIO data TX_preGPIO_data to extract only the data bits corresponding to the GPIO pad <NUM> allocated to the communication of the corresponding data from the transmit preGPIO data TX_preGPIO_data received from the input/output data converter <NUM>. For example, as shown in <FIG>, the GPIO data converter <NUM> may apply, to the transmit preGPIO data TX_preGPIO_data, the transmit mask TX_MASK in which each of the fifth bit, the sixth bit, and the seventh bit has a value of "<NUM>", and the other bits have a value of "<NUM>" such that only to the fifth bit, the sixth bit, and the seventh bit as data bits corresponding to the GPIO pad <NUM> allocated to the communication of the corresponding data are extracted from the transmit preGPIO data TX_preGPIO_data. Thus, the transmit preGPIO data TX_preGPIO_data may be converted to the transmit GPIO data TX_GPIO_data including values of the fifth bit, the sixth bit, and the seventh bit of each transmit preGPIO data TX_preGPIO_data.

Furthermore, the GPIO data converter <NUM> converts the receive GPIO data RX_GPIO _data received from at least one GPIO pad <NUM> to the receive preGPIO data RX_preGPIOdata by applying a receive mask RX_MASK to the receive GPIO data RX_GPIO_data to extract only the data bits corresponding to the GPIO pad <NUM> allocated to the communication of the corresponding data therefrom. For example, as shown in <FIG>, the GPIO data converter <NUM> may apply, to the receive GPIO data RX_GPIO_data, the receive mask RX_MASK in which the eighth bit has the value of "<NUM>" and the other bits have a value of "<NUM>" such that only the eighth bit as the data bit corresponding to the GPIO pad <NUM> allocated to the communication of the corresponding data is extracted therefrom. Thus, the receive GPIO data RX_GPIO_data may be converted to the receive preGPIO data RX_preGPIO_data including the value of the 8th bit of each receive GPIO data RX_GPIO_data to receive GPIO data RX_GPIO_data.

The GPIO output unit <NUM> outputs the transmit GPIO data TX_GPIO_data transmitted from the GPIO data converter <NUM> via the GPIO input/output line <NUM> and at least one GPIO pad <NUM>.

The GPIO input unit <NUM> receives the receive GPIO data RX_GPIO_data received via the at least one GPIO pad <NUM> via the GPIO input/output line <NUM> and the at least one GPIO pad <NUM>.

Hereinafter, with reference to <FIG>, an internal communication method in a semiconductor device of an embodiment of the present disclosure will be described in detail.

<FIG> is a flow chart of a data transmit method in a semiconductor device of an embodiment of the present disclosure. <FIG> is a diagram illustrating data resulting from conversion according to a data transmit method in a semiconductor device of an embodiment of the present disclosure. <FIG> is a flowchart of a data reception method in a semiconductor device of an embodiment of the present disclosure. <FIG> is a diagram illustrating data resulting from conversion according to a data reception method in a semiconductor device of an embodiment of the present disclosure.

Referring to <FIG> and <FIG>, a data transmit method in a semiconductor device of an embodiment of the present disclosure is described in detail.

First, although not shown, the input/output data converter <NUM> may convert the output data TX_data received from the processor <NUM> into serial or parallel data.

Then, the input/output data converter <NUM> converts the output data TX_data received from the processor <NUM> into the transmit protocol data TX_prtc_data corresponding to the communication protocol of the output data TX_data in s1001. For example, when the protocol of the output data TX_data is the SPI (Serial Peripheral Interface) communication protocol, the input/output data converter <NUM> converts the output data TX_data into the transmit protocol data TX_prtc_data including the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD according to the SPI communication protocol as shown in <FIG>. In this regard, the output data TX_data includes the first to third output data TX_data1 to TX_data3, as shown in <FIG>. The first output data TX_data1 indicates information about the communication protocol of the output data TX_data, and may have different values depending on the communication protocol of the output data TX_data. The second output data TX_data2 indicates information about a GPIO pad from which the data is output among the GPIO pads <NUM>. Furthermore, the third output data TX_data3 includes the data processed by the processor <NUM> as described above. For example, the output data TX_data may include the first output data TX_data1 having a value of "<NUM>(<NUM>)" indicating the SPI protocol, the second output data TX_data2 having a value of "<NUM><NUM><NUM>" indicating using middle <NUM> GPIO pads among <NUM> GPIO pads, and the third output data TX_data3 as the data processed by the processor <NUM> having a value of "<NUM><NUM>(0x5A)". Although not shown, like the output data TX_data, the input data RX_data may include first input data RX_data1 as information about a communication protocol, second input data RX_data2 as information about a GPIO pad to which the data is input among the GPIO pads <NUM>, and third input data RX_data3 as the data input to the GPIO pad. Although described based on the SPI protocol, the present disclosure is not limited thereto. The input/output data converter <NUM> converts the output data TX_data the transmit protocol data TX_prtc_data based on other communication protocols.

Then, the input/output data converter <NUM> converts the transmit protocol data TX_prct_data into the transmit preGPIO data TX_preGPIO_data in s1002. Specifically, the input/output data converter <NUM> converts the transmit protocol data TX_prct_data into the transmit preGPIO data TX_preGPIO_data by dividing the transmit protocol data TX_prct_data based on the timing at which the data is transmitted. That is, the transmit data converter <NUM> converts the transmit protocol data TX_prct_data transmitted in parallel into serial data based on the timing at which the data is transmitted to convert the same into the transmit preGPIO data TX_preGPIO_data. For example, when the communication protocol of the transmit protocol data TX_prtc_data is the SPI communication protocol, the input/output data converter <NUM> may extract the transmit protocol data TX_prct_data including the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD based on the timing at which the data is transmitted to convert the transmit protocol data TX_prct_data into the transmit preGPIO data TX_preGPIO_data. That is, the transmit data converter <NUM> converts the transmit protocol data TX_prct_data transmitted in parallel into serial data based on the timing at which the data is transmitted to convert the transmit protocol data TX_prct_data into the transmit preGPIO data TX_preGPIO_data. Accordingly, the transmit data converter <NUM> may convert the transmit protocol data TX_prct_data to the transmit preGPIO data TX_preGPIO_data including "<NUM>", "<NUM>" and "<NUM>" as respective values of the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD transmitted at a first timing, and may convert the transmit protocol data TX_prct_data to the transmit preGPIO data TX_preGPIO_data including "<NUM>", "<NUM>" and "<NUM>" as respective values of the SPI clock data SPI_CLK, the SPI chip select data SPI_CS, and the SPI transmit data SPI_TXD transmitted at a second timing. According to an embodiment of the present disclosure, the transmit preGPIO data TX_preGPIO_data is composed of the number of bits corresponding to GPIO pads. Specifically, the transmit data converter <NUM> may receive transmit bit data as data about data transmit bits corresponding to the GPIO pads <NUM> allocated to communication of the output data TX_data, from the processor <NUM>. Accordingly, for example, a fifth GPIO pad, a sixth GPIO pad, and a seventh GPIO pad of the GPIO pads <NUM> may be allocated to the output data TX_data transmission. Thus, the transmit data converter <NUM> may receive, from the processor <NUM>, the data indicating that the fifth bit, the sixth bit, and the seventh bit are allocated to the communication of the output data TX_data as the data indicating the data transmit bits corresponding to the allocated GPIO pads. As shown in <FIG>, the transmit preGPIO data TX_preGPIO_data composed of <NUM> bits corresponding to the <NUM> GPIO pads includes the SPI clock data SPI_CLK, the SPI chip select data SPI_CS and the SPI transmit data SPI_TXD output at the same timing in the 5th, 6th and 7th bits, respectively.

Then, the input/output data converter <NUM> transmits the converted transmit preGPIO data TX_preGPIO_data to the GPIO input/output unit <NUM> via the bus <NUM> in s1003. According to an embodiment of the present disclosure, the transmit preGPIO data TX_preGPIO_data is transmitted from the input/output data converter <NUM> to the GPIO input/output unit <NUM> via the bus <NUM> rather than a separate line pattern, such that the complexity of the internal line pattern may be reduced.

Then, the GPIO input/output unit <NUM> converts the transmit preGPIO data TX_preGPIO_data into the transmit GPIO data TX_GPIO_data in s1004. Specifically, the GPIO input/output unit <NUM> may convert the transmit preGPIO data TX_preGPIO_data received from the input/output data converter <NUM> to the transmit GPIO data TX_GPIO_data by applying the transmit mask TX_MASK to the transmit preGPIO data TX_preGPIO_data so that only the GPIO pad <NUM> allocated to the communication of the corresponding data is controlled. For example, as shown in <FIG>, the GPIO input/output unit <NUM> may apply, to the transmit preGPIO data TX_preGPIO_data, the transmit mask TX_MASK in which each of the fifth bit, the sixth bit, and the seventh bit has a value of "<NUM>", and the other bits have a value of "<NUM>" such that only to the fifth bit, the sixth bit, and the seventh bit as data bits corresponding to the GPIO pad <NUM> allocated to the communication of the corresponding data are extracted from the transmit preGPIO data TX_preGPIO_data. Thus, the transmit preGPIO data TX_preGPIO_data may be converted to the transmit GPIO data TX_GPIO_data including values of the fifth bit, the sixth bit, and the seventh bit of each transmit preGPIO data TX_preGPIO_data.

A data reception method in a semiconductor device of an embodiment of the present disclosure is described in detail with reference to <FIG> and <FIG>.

First, the GPIO input/output unit <NUM> converts the receive GPIO data RX_GPIO_data to the receive preGPIO data RX_preGPIO_data in s1201. Specifically, the GPIO input/output unit <NUM> converts the receive GPIO data RX_GPIO_data received from at least one GPIO pad <NUM> to the receive preGPIO data RX_preGPIO_data by applying the receive mask RX_MASK to the receive GPIO data RX_GPIO_data to extract only the data bits corresponding to the GPIO pad <NUM> allocated to the communication of the corresponding data therefrom. For example, as shown in <FIG>, the GPIO input/output unit <NUM> may apply, to the receive GPIO data RX_GPIO_data, the receive mask RX_MASK in which the eighth bit has the value of "<NUM>" and the other bits have a value of "<NUM>" such that only the eighth bit as the data bit corresponding to the GPIO pad <NUM> allocated to the communication of the corresponding data is extracted therefrom. Thus, the receive GPIO data RX_GPIO_data may be converted to the receive preGPIO data RX_preGPIO_data including the value of the 8th bit of each receive GPIO data RX_GPIO_data to receive GPIO data RX_GPIO_data.

Thereafter, the GPIO input/output unit <NUM> transmits the converted receive preGPIO data RX_preGPIO_data to the input/output data converter <NUM> via the bus <NUM> in s1202. According to an embodiment of the present disclosure, the receive preGPIO data RX_preGPIO_data is transmitted from the GPIO input/output unit <NUM> to the input/output data converter <NUM> via the bus rather than a separate line pattern, such that the complexity of the internal line pattern may be reduced.

Then, the input/output data converter <NUM> converts the receive preGPIO data RX_preGPIO_data into the receive protocol data RX_prct_data in s1203. Specifically, the input/output data converter <NUM> extracts the receive preGPIO data RX_preGPIO_data based on the timing at which the data is transmitted to convert the receive preGPIO data RX_preGPIO_data into the receive protocol data RX_prct_data. That is, the transmit data converter <NUM> converts the transmit protocol data TX_prct_data transmitted in parallel into the serial data based on the timing at which the data is transmitted to convert the transmit protocol data TX_prct_data into the transmit preGPIO data TX_preGPIO_data. Accordingly, the receive protocol data RX_prct_data may include data transmitted via at least one line according to the corresponding communication protocol. For example, when the protocol of the receive protocol data RX_prtc_data is the SPI (Serial Peripheral Interface) communication protocol, the input/output data converter <NUM> converts the receive preGPIO data RX_preGPIO_data into the receive protocol data RX_prtc_data including the SPI receive data SPI_RXD as shown in <FIG>. According to an embodiment of the present disclosure, the receive preGPIO data RX_preGPIO_data is composed of the number of bits corresponding to the number of GPIO pads. Specifically, the transmit data converter <NUM> may receive the data about the data receive bit corresponding to the GPIO pads <NUM> to which the receive protocol data RX_prct_data is output from the processor <NUM> and may convert the receive preGPIO data RX_preGPIO_data into the receive protocol data RX_prtc_data using the data about the data receive bit. For example, the receive data converter <NUM> receives the data indicating that the eighth bit is allocated to communication of the input data RX_data as the data about the data receive bit corresponding to the allocated GPIO pad. Thus, as shown in <FIG>, the receive data converter <NUM> may extract the 8th bit of the receive preGPIO data RX_preGPIO_data composed of <NUM> bits corresponding to the <NUM> GPIO pads to convert the same into the receive protocol data RX_prct_data.

Thereafter, the input/output data converter <NUM> converts the receive protocol data RX_prct_data into the input data RX_data in s1204. For example, when the protocol of the receive protocol data RX_prtc_data is the SPI (Serial Peripheral Interface) communication protocol, the input/output data converter <NUM> receives the receive protocol data RX_prtc_data including the SPI receive data SPI_RXD, and converts the receive protocol data RX_prtc _data into the input data RX_data including the first input data RX_data1, the second input data RX_data2, and the third input data RX_data3 as shown in <FIG>. That is, as shown in <FIG>, the receive protocol data RX_prct_data including the SPI receive data SPI_RXD having a value of "<NUM>(0x83)" may be converted to the input data RX_data including the first input data RX_data1 having a value of "<NUM><NUM>" indicating the SPI protocol, the second input data RX_data2 having a value of "<NUM><NUM><NUM>" indicating using the middle <NUM> GPIO pads among <NUM> GPIO pads, and the third input data TX_data3 having a value of "<NUM>(0x83)" as the receive protocol data RX_prct_data.

Then, although not shown, the input/output data converter <NUM> may convert the input data RX data into serial or parallel data and transmit the converted data to the processor <NUM>.

Claim 1:
A semiconductor device comprising:
a processor (<NUM>);
an input/output data converter (<NUM>) configured to receive output data (TX_data) via a bus (<NUM>), convert the output data (TX_data) into transmit preGPIO data (TX_preGPIO_data), and transmit the transmit preGPIO data (TX_preGPIO_data) to the bus (<NUM>),
wherein the output data (TX_data) includes first output data (TX_data1) indicating information about a communication protocol of the output data (TX_data), second output data (TX_data2) indicating information about at least one GPIO pad among a plurality of GPIO pads (<NUM>) from which the data is to be output, and third output data (TX_data3) including data processed by the processor (<NUM>); and
a GPIO input/output unit (<NUM>) configured to receive the transmit preGPIO data (TX_preGPIO_data) via the bus (<NUM>), convert the transmit preGPIO data (TX_preGPIO_data) into transmit GPIO data (TX_GPIO_data), and output the transmit GPIO data (TX_GPIO_data) to the at least one GPIO pad,
wherein the input/output data converter (<NUM>) is configured to convert the output data (TX_data) into transmit protocol data (TX_prtc_data) corresponding to the communication protocol of the first output data (TX_data1) included in the output data (TX_data), and convert the transmit protocol data (TX_prtc_data) into the transmit preGPIO data (TX_preGPIO_data).