Patent Description:
Several serial transmission protocols, particularly transmission protocols for high data rates, do not have a dedicated clock signal so that a clock data recovery (CDR) based on the data signal is required.

In the state of the art, clock data recovery is done by means of a phase-locked loop (PLL) based clock data recovery. Typically, analog components are used in order to avoid major delays in the feedbacks done by the PLL based clock recovery which might have an impact on the function and stability of the respective system used for clock data recovery. For instance, such a clock data recovery is described in <CIT>.

In addition, digital solutions for clock data recovery are known in the state of the art.

For instance, phase interpolation techniques are used wherein the phase or rather the phase position of the clock signal is corrected in a feedback-controlled manner. The phase information of the data signal as well as the one of the clock signal are compared and used for controlling a phase interpolation. Thus, the respective information gathered is used for reconstructing the clock signal. The phase interpolation techniques ensure to track frequency shifts, for instance frequency shifts that occur in spread spectrum clocking (SSC) modulations. However, the technique is critical with regard to latency due to the feedback.

Another concept is based on sampling the data signal with a high sampling rate in an uncontrolled manner, also called blind oversampling. Edges in the data signal are detected which are used for determining the sampling times for generating the clock signal and recovering the respective data. Hence, no feedback is necessary. However, larger frequency shifts are critical that may occur due to spread-spectrum clocking modulations.

<CIT> describes an adaptive regeneration system for reconstructing a signal received. The adaptive regeneration system comprises a clock recovery circuit that receives the multi-level signal to be reconstructed as well as several phase-delayed clock signals, wherein the several phase-delayed clock signals are compared with the multi-level signal to be reconstructed in order to identify the one of the several phase-delayed clock signals that best matches the multi-level signal.

Accordingly, there is a need for a possibility enabling clock data recovery for n-ary serial signals, e.g. PAM-n signals, at high data rates with a large area of application.

Embodiments of the present disclosure inter alia provide a method for recovering a clock signal from a data signal according to appended claim <NUM>.

Moreover, embodiments of the present disclosure provide a clock recovery module for recovering a clock signal from a data signal, according to appended claim <NUM>.

In addition, embodiments of the present disclosure provide a computer program for recovering a clock signal from a data signal according to appended claim <NUM>.

The underlying idea is to provide a clock data recovery for n-ary signals, e.g. PAM-n, wherein a feed-forward structure is used instead of a feedback structure being critical with regard to latency issues such as a phase-locked loop. In addition, data signals with jitter, frequency shifts or larger frequency variations can be processed appropriately, for instance spread spectrum clocking (SSC) modulated signals. Moreover, data rates higher than 10Gbps at system clock rates of <NUM> can be achieved. Thus, a highly parallel implementation is obtained.

A bit comprises a <NUM>-ary symbol having the states '<NUM>' or '<NUM>'. For n-ary signals, e.g. PAM4, the bit means an n-ary symbol, e.g. a <NUM>-ary bit.

The edge timings correspond to the temporal edge positions in the data signal, namely the positions of data signal threshold transitions or level transitions.

The transformation of the edge timings for obtaining the reference bit period relates to a modulo transformation allowing a statistical evaluation of the edge timings within a bit period. Put it another way, the edge timings are transformed in one bit period interval for further evaluation by applying the respective modulo transformation.

The bit period used may be set, particularly pre-set initially.

The time offset for the reference bit period is chosen from a number of time offset values wherein the time offset chosen corresponds to a base value for the clock signal. The respective time offset is chosen by applying a criterion which shall be fulfilled, for instance an argument of minimum, also called arg min.

Once the time offset used as the base value has been chosen, the reference clock signal can be determined. For instance, the time offset chosen is used to determine the last edge timing within the system clock by taking the bit period into account so as to determine the reference clock signal.

In addition, the number of edges within the system clock can be determined. Put it another way, the number of bit periods is verified that are present in the system clock.

The different modules of the clock recovery module may relate to software modules.

Generally, the clock data recovery is based on edge timings of the data signal which are accumulated and processed in an appropriate manner wherein the respective edges were indirectly defined previously, in particular via thresholds applied on the data signal.

The clock signal may be recovered by an interpolation on the reference clock signal and the number of bits. The reference clock signal as well as the number of bit periods are used for recovering the clock signal by performing an interpolation on the respective data. Particularly, the clock signal recovery is done by an interpolation in case that the data signal has a data rate which is substantially equal or higher than the system clock rate.

Hence, the clock module may be a clock interpolation module.

According to an aspect, another clock signal is estimated based on the edge timings. The other clock signal is particularly used for clock recovery with low bandwidth. The other clock signal may be estimated via a post-processing unit that is connected with the clock module so as to obtain the already determined clock signal. The post-processing unit may provide a feedback signal to the accumulation and compensation calculation module, the offset selection module and/or the front clock generation module. The other clock signal may correspond to clock signal timings estimated based on the bit period as well as the edge timings wherein the bit period is also estimated by applying a criterion to be fulfilled.

For estimating the other clock signal, the already determined clock signal may be used.

Moreover, a bit period may be estimated. The bit period may be estimated based on the edge timings, in particular via the post-processing unit. In addition, the bit period may be estimated by a bit period calculation module. The bit period estimated may also be fed back to the accumulation and compensation calculation module, the offset selection module and/or the front clock generation module. The bit period may be estimated by applying a criterion to be fulfilled.

Accordingly, a post-processing unit may be provided that is configured to estimate the bit period and/or the other clock signal based on the edge timings.

According to another aspect, not part of the invention, for data rates being lower than the respective system clock, several system clocks are summarized to a virtual system clock, wherein the virtual system clock is de-virtualized afterwards. Hence, a virtualization and normalization module may be provided that is configured to summarize several system clocks to a virtual system clock and to normalize the edge timings within the virtual system clock. Further, a de-normalization and de-virtualization module may be provided that is configured to reverse the result of the virtualization and normalization module. Particularly, the edge timings in the virtual system clock are normalized, wherein the normalized edge timings are de-virtualized after the clock signal is recovered.

The data signal comprising several valid edge timings in a system clock wherein the several edge timings define their relative position within the system clock. For data rates being lower than the system clock, <NUM>µVSP system clocks can be summarized to the virtual system clock for being processed appropriately. Moreover, the edge timings may be normalized so that they correspond to their position within the virtual system clock.

After the processing, in particular the clock data recovery, the virtualization and normalization is reversed in the de-normalization and de-virtualization module so that the signal clock timings obtained relate to clock signals instead of the virtual ones.

Another aspect provides that the value of the time offset determined is corrected to obtain a corrected time offset, and wherein the corrected time offset is the sum of the time offset determined and averaged deviations from the time offset determined. The time offset determined is corrected by adding the respective averaged deviations from the time offset determined which were previously used for determining the time offset. The averaged deviations from the time offset determined correspond to the sum of the respective deviations divided by the number of deviations summed up. The respective deviations were obtained when choosing the time offset by comparing the different time offset values available.

In addition, a bit period calculation module may be provided that is configured to feed back an estimated bit period to the accumulation and compensation calculation module, the offset selection module and/or the front clock generation module. The optional bit period calculation module provides a feedback to the respective modules ensuring that data spread spectrum clocking (SSC) modulated signals can be handled that have larger frequency shifts with slow change. Due to the slow change, the feedback used is not latency critical. The estimation of the bit period may be done by means of an infinite impulse response filter (IIR filter).

In case of no feedback by the bit period calculation module, the nominal bit period is used which was set.

According to another aspect, a transition density calculation module is provided that is configured to determine a mean value of the clock signals and edge timings. The transition density calculation module can be used for determining and applying thresholds with regard to the mean value of the clock signals and edge timings wherein a respective indication may be set or rather output to inform the user. In other words, an allowable range for the mean value of the clock signals and edge timings may be set by the transition density calculation module wherein a respective indication, labeling or rather marker is output depending on a violation of the allowable range or not. The violation may correspond to an exceeding or rather a falling below the respective threshold(s).

Furthermore, the number of accumulated edge timings can be chosen. The clock data recovery can be set appropriately by choosing the number of accumulated edge timings as well as the update rate of the bit period estimation.

Generally, the clock recovery module may be configured to perform the method for recovering a clock signal from a data signal mentioned above. Hence, the clock recovery module may also be configured to run the computer program described above.

Since the different modules of the clock recovery module may relate to software modules, the overall clock recovery module may be established by a processor that may run the computer program.

In <FIG> a clock recovery module <NUM> is shown that has an input <NUM> via which a data signal to be processed is received.

In the shown embodiment, the clock recovery module <NUM> has an optional virtualization and normalization module <NUM> that is connected with the input <NUM> so that the data signal received or rather respective information of the data signal is forwarded to the virtualization and normalization module <NUM>.

In fact, the above mentioned data or rather information is received by the clock recovery module <NUM> anyway so as to start recovering the clock signal from the data signal.

The clock recovery module <NUM> further comprises an accumulation and compensation calculation module <NUM> that is connected with the virtualization and normalization module <NUM>.

The accumulation and compensation calculation module <NUM> is inter alia configured to accumulate the edge timings of the data signal that are forwarded to the accumulation and compensation calculation module <NUM>.

Further, the accumulation and compensation calculation module <NUM> is configured to transform the edge timings accumulated into one reference bit period that is used for further processing as will be described later with respect to <FIG> when the overall method for recovering the clock signal from the data signal by using the clock recovery module <NUM> is described.

The clock recovery module <NUM> also comprises an offset selection module <NUM> that is connected with the accumulation and compensation calculation module <NUM> so as to receive at least the reference bit period determined previously.

The offset selection module <NUM> is configured to determine a time offset for the reference bit period.

In addition, the clock recovery module <NUM> comprises a front clock generation module <NUM> that is connected with the offset selection module <NUM> so as to receive at least the time offset determined previously.

The front clock generation module <NUM> is configured to determine a reference clock signal based on the time offset received.

Further, the front clock generation module <NUM> is configured to determine the number of bits within a system clock of the clock recovery module <NUM>.

The system clock may relate to the virtual system clock provided that the optional virtualization and normalization module <NUM> is provided.

The clock recovery module <NUM> further comprises a clock module <NUM> that is connected with the front clock generation module <NUM>.

The clock module <NUM> is configured to receive the number of bits determined by the front clock generation module <NUM> as well as the reference clock signal determined by the front clock generation module <NUM>. Thus, the number of bits determined as well as the reference clock signal are forwarded to the clock module <NUM>.

The clock module <NUM> may be a clock interpolation module.

Moreover, the clock recovery module <NUM> may have an optional de-normalization and de-virtualization module <NUM> that is connected with the clock module <NUM>. In fact, the de-normalization and de-virtualization module <NUM> is configured to reverse the result of the virtualization and normalization module <NUM>. Accordingly, the optional de-normalization and de-virtualization module <NUM> is provided in case that the optional virtualization and normalization module <NUM> is provided.

In addition, the clock recovery module <NUM> may have an optional transition density calculation module <NUM> that is connected with the clock module <NUM> as well as the virtual and normalization module <NUM> being optional as discussed above.

The transition density calculation module <NUM> is configured to determine a mean value of the clock signals and edge timings.

Furthermore the clock recovery module <NUM> may optionally comprise a bit period calculation module <NUM> that is connected with the clock module <NUM>. The bit period calculation module <NUM> is configured to feed back an estimated bit period to the accumulation and compensation calculation module <NUM>, the offset selection module <NUM> and/or the front clock generation module <NUM>.

Thus, the accumulation and compensation calculation module <NUM>, the offset selection module <NUM> and/or the front clock generation module <NUM> may use the bit period estimated instead of the set one.

Hereinafter, reference is made to <FIG> for describing the method for recovering the clock signal from the data signal by using the clock recovery module <NUM> shown in <FIG>, which is generally called clock data recovery (CDR).

In a general first step S1, thresholds for distinguishing the status of the binary data signal are defined, namely <NUM> and <NUM> of the data signal. Based on these thresholds, edge timings of the data signal are calculated, for instance the timings of exceeding or rather reaching the threshold(s) set. The respective edge timings are forwarded to the clock recovery module <NUM> via its input <NUM> as an input signal.

The clock signal timings, which define the clock signal, are recovered based on the edge timings of the data signal by using the clock recovery module <NUM> shown in <FIG> as will be discussed hereinafter in more detail.

In a second step S2, the virtualization and normalization module <NUM> receives via the input <NUM> the signal for resetting the clock data recovery (RESTART_IN), the number of valid edge timings NData,V[k] (N_DATA_V_IN) in system clock k of the clock recovery module <NUM> as well as the respective edge timings TData[k, l] with parallelism PData (DATA_IN) wherein l = <NUM>,. , PData - <NUM> in samples.

The number of valid edge timings NData,V[k] as well as the respective edge timings TData[k, l] are calculated based on the thresholds set in step S1.

In fact, the edge timings TData[k, l] define the positions of the edges within the system clock with a sub-sample resolution.

The virtualization and normalization module <NUM> may generally summarize several system clocks to a virtual system clock, particularly <NUM>µVSP system clocks in case of data rates being lower than the system clock rate.

The edge timings are further normalized so that their respective positions correspond to the positions within the virtual system clock. The normalization can be done as follows: <MAT> , wherein TVSP[k] defines the offset of the current system clock, namely the k-th one, in the virtual system clock in samples.

The virtualization and normalization module <NUM> outputs the signal for resetting the clock data recovery (RESTART), the normalized edge timings T̃Data[k, l] (DATA_OUT), the number of edge timings NData,V[k] (N_DATA_V_OUT), an indicator, marker or rather label for indicating the end of the virtual system clock (VSP_FULL) and an ending time of the current system clock (SP_TIME_END).

In the shown embodiment, the edge timings are forwarded after being normalized.

The respective data output is forwarded to the accumulation and compensation calculation module <NUM> as shown in <FIG>.

Provided that no virtualization and normalization module <NUM> is provided, the edge timings TData[k, l] would be forwarded to the accumulation and compensation calculation module <NUM> directly.

In a third step S3, the accumulation and compensation calculation module <NUM> receives the data output wherein NData,Acc edges are accumulated and their respective values TAcc[k, l] are updated continuously, namely the positions of the edges within the (virtual) system clock or the positions of the edges within a bit period within the (virtual) system clock. In fact, the (virtual) system clock may comprise several bit periods. Put it another way, NData,Acc edges are kept for further processing. The respective number may be set or rather pre-defined.

The accumulated edges NData,Acc provide the basis for calculating the clock signal and, therefore, the number is of high importance with regard to the performance and resource consumption of the clock data recovery.

The accumulation and compensation calculation module <NUM> accumulates the last NData,Acc edges received, which means that the respective number of edges NData,Acc are kept.

Further, the accumulation and compensation calculation module <NUM> compensates the values of the edges in order to transform them into one reference bit period within the current (virtual) system clock by applying a modulo transformation.

New (non-negative) edge timings from the current system clock k are calculated by using the (standardized) bit period T̃b[k] as follows: <MAT>.

If there is also a change to a new virtual system clock at the transition from system clock k - <NUM> to system clock k, the existing accumulated edge timings TAcc[k, l] are additionally updated with the number of samples per system clock NSmp as follows: <MAT>.

The modulo transformation to one bit period interval allows a statistical evaluation of the edge timings within a single bit period as shown in <FIG>.

The accumulated edge timings TAcc[k, l] (DATA_ACC) as well as their number (CNT_DATA) are output by the accumulation and compensation calculation module <NUM> so that the following offset selection module <NUM> is enabled to process the respective data.

Besides the accumulated edge timings TAcc[k, l] (DATA_ACC) and their number (CNT_DATA), the accumulation and compensation calculation module <NUM> also outputs the signal for resetting the clock data recovery (RESTART), the indicator for indicating the end of the virtual system clock (VSP_FULL) as well as the ending time of the current system clock (SP_TIME_END) as shown in <FIG>.

In a fourth step S4, the offset selection module <NUM> receives and processes the output data of the accumulation and compensation calculation module <NUM>.

The offset selection module <NUM> is configured to determine a time offset as the base value for the clock signal. In fact, the offset selection module <NUM> can access a number of different time offset values for evaluating purposes, namely NOff time offset values.

For each of these time offset values, the bit period interval is shifted appropriately. The edge timings TAcc[k, l] within the respective bit period interval are updated as follows: <MAT> <MAT>.

Thus, the time offset to be applied is chosen from a number of different time offsets by evaluating the difference of the accumulated edge timings TAcc[k, l] with respect to the center of the bit period interval <MAT> as shown hereinafter: <MAT>.

This can also be calculated as follows: <MAT> <MAT>.

Then, the sum of the absolute values of these differences is created wherein the time offset value resulting yielding the lowest value is chosen according to: <MAT> , wherein <NUM> ≤ NData,x ≤ NData,Acc and x ∈ {Start,End}.

At the beginning NData,x = <NUM>, wherein NData,x = NData,Start once NData,Start have been accumulated. As soon as NData,End edge timings have been accumulated and a defined number of system clock cycles NCyc,Sw has expired, NData,x = NData,End applies.

When changing to NData,x = NData,End, the lock state of the CDR LockCDR changes from <NUM> to <NUM>. As soon as the lock state of the bit period estimate LockTb also changes from <NUM> to <NUM> at the input, the change LockCDR changes from <NUM> to <NUM> and thus the lock state is reached.

Either the offset value TOff,s[k][k] can be used for further processing or the offset value determined can be corrected by adding the mean value of the differences. This allows a more accurate offset value to be obtained for the clock signal. The mean value of the differences may be added as follows to the offset value determined: <MAT>.

The offset selection module <NUM> outputs at least the time offset determined TOff,s[k][k] or rather the corrected time offset ŤOff[k] (DATA_OFFSET) as well as the lock status of the clock data recovery (LOCK_CDR) as shown in <FIG>.

Besides the time offset determined TOff,s[k][k] or rather the corrected time offset ŤOff[k] (DATA_OFFSET) as well as the lock status of the clock data recovery (LOCK_CDR), the offset selection module <NUM> also outputs the signal for resetting the clock data recovery (RESTART), the indicator for indicating the end of the virtual system clock (VSP_FULL) and the ending time of the current system clock (SP_TIME_END).

In a fifth step S5, the front clock generation module <NUM> receives the respective data and processes the data to determine the number of edges NClk,V[k] within the (virtual) system clock as well as the value of the last edge timing T̃Clk,last[k] within the (virtual) system clock. The last edge timing T̃Clk,last[k] is assigned to the reference clock signal used for determining the clock signal.

The last edge timing T̃Clk,last[k] within the (virtual) system clock is calculated based on the basis value TBase[k] = ŤOff[k] + ΔClk and the standardized bit period T̃b[k]. In fact, ΔClk corresponds to the offset of the clock signal with respect to the mean edge transition. Typically, ΔClk = T̃<NUM>/<NUM> with the (standardized) nominal bit period T̃<NUM>.

The respective calculation is also illustrated in <FIG>. It becomes obvious that the last edge timing T̃Clk,last[k] within the (virtual) system clock corresponds to the reference clock signal. In fact, the last edge timing T̃Clk,last[k] is assigned to the last bit within the (virtual) system clock.

The distance between two clock timings must be > T̃b[k]/<NUM> and ≤ <NUM> T̃b[k]/<NUM>. Accordingly, the first bit within the (virtual) system clock must be cancelled, remains or is added so as to obtain consistence between the previous (virtual) system clock and the current one.

Thus, the number of edges or rather edge timings NClk,V[k] in the actual system clock can be obtained.

The front clock generation module <NUM> outputs inter alia the last edge timing T̃Clk,last[k] (CLK_VSP) within the current (virtual) system clock as well as the edge timing T̃Clk,last[k - <NUM>µVSP] (CLK_VSP_PRV) of the previous (virtual) system clock as well as the number of edges NClk,V[k] (N_CLK_V) as shown in <FIG>.

Besides this data, the front clock generation module <NUM> also outputs the signal for resetting the clock data recovery (RESTART), the indicator for indicating the end of the virtual system clock (VSP_FULL), the ending time of the current system clock (SP_TIME_END) as well as the lock status of the clock data recovery (LOCK_CDR).

In a sixth step S6, the clock module <NUM> receives and processes the data appropriately.

Hence, the reference clock signals, namely the one assigned to the last edge timings, are used to determine the clock signal by interpolation provided that more than one clock signal is present in the system clock. The reference clock signal of the current system clock k as well as the one of the previous system clock k - <NUM> are used and interpolated in a linear manner for generating the interposing clock signals: <MAT>.

The respective clock signals T̃Clk[k, l] (CLK_VSP_INT) and their number (N_CLK_V_OUT) are output.

Provided that a normalization and virtualization module <NUM> was used as shown in the embodiment of <FIG>, the respecting virtualization and normalization is reversed by the subsequent de-normalization and de-virtualization module <NUM> in a seventh step S7.

Hence, the de-normalization and de-virtualization provides clock signals that relate to the (non-virtual) system clock (CLK_SIG_OUT) which are output by the de-normalization and de-virtualization module <NUM> and obtained as follows: <MAT>.

Furthermore, the unlock-status of the clock data recovery (UNLOCK_CDR) is output.

As shown in <FIG>, the number of valid clock signals NClk,V[k] (N_CLK_V_OUT), the signal for resetting the clock data recovery (RESTART_OUT) and the lock-status of the clock data recovery (UNLOCK_CDR) are output.

In an eighth step S8, the transition density calculation module <NUM> determines the mean number of the clock signals and edges. The calculation is done by means of an infinite impulse response filter (IIR filter) of first order as shown hereinafter: <MAT> , wherein x ∈ {Data,Clock}, L = <NUM>,. ,<NUM>, and wherein Nx [k] corresponds to the number of clock signals or rather edges (N_CLK_AVG_VSP or rather N_DATA_AVG_VSP) within the current system clock.

Hence, the current system clock may comprise several bit periods, clock signals assigned to the bit periods or rather clock edges.

Furthermore, threshold(s) may be set to define a range of accepted values for the mean number of cycle signals or rather. In case of exceeding or rather falling below the threshold(s), an indication by means of TDHigh or rather TDLow is output (TD_HIGH or rather TD_LOW). Hence, breaching or rather violating the range of accepted values is indicated. The breaching or rather violating may be assigned to an exceeding or rather falling below the respective threshold(s).

In a ninth step S9, the optional bit period calculation module <NUM> may estimate a bit period that is fed back to the accumulation and compensation calculation module <NUM>, the offset selection module <NUM> and/or the front clock generation module <NUM> as shown in <FIG>. If no feedback occurs, the nominal (pre-set) bit period is used.

The feedback generally ensures the support of spread spectrum clocking (SSC) modulated signals where larger frequency shifts occur with slow changes. Due to the slow change of the bit period, the feedback is not latency critical.

The estimation of the bit period is done by an infinite impulse response filter (IIR filter) of first order wherein the distance ΔClk[k] between two clock signals is used for all NCyc,BPU system clocks for updating purposes: <MAT>.

The coefficients a and b are determined by the constant number of clock signals covered by the distance ΔClk[k] as well as the (desired) setting of the filter, in particular its speed.

Besides the feedback of the estimated bit period T̂b[k] (TB_TEST), the lock state of the bit period estimation LockTb (LOCK_TB_EST) is also forwarded to the accumulation and compensation calculation module <NUM>. The status is only <NUM> in case of LockCDR ≥ <NUM> and a defined number of clock signals NClk,Tb has occurred after the last change from <NUM> to <NUM>.

Once the clock signals have been recovered from the data signal based on the edge timings as described above, the data signal is sampled with the respective clock signals in a tenth step S10.

As the steps S7 to S9 are optional ones, the sampling may take place after the sixth step S6 once the clock signals were determined by the clock module <NUM>.

In <FIG>, another embodiment is shown that comprises a post-processing unit <NUM> instead of the bit period calculation module <NUM>. The post-processing unit <NUM> is interconnected between the clock module <NUM> and the de-normalization and de-virtualization module <NUM>.

The number of accumulated edge timings TAcc[k, l] is limited yielding a high adaption speed of the clock data recovery with respect to the data signal which corresponds to a high bandwidth of a phase-locked loop (PLL). In general, this is advantageous for successful data recovery.

However, in case of a low bandwidth being desired, a post-processing is necessary.

The post-processing is based on an estimation of (standardized) clock signal timings T̃Clk as well as a (standardized) bit period T̃b of N (standardized) edge timings T̃Data [k], k = <NUM>,. , N - <NUM>.

The estimation is separated in two optimization problems.

In fact, a criterion is provided for the bit period and another criterion is provided for the (other) clock signal. For estimating the clock signal timing, the minimum of the following criterion has to be determined: <MAT> , wherein n[k] corresponds to the bit position of the k-th edge related to the clock signal. Thus, the clock signal timing T̃Clk is yield in dependency of the bit period T̃b as follows: <MAT>.

For estimating the bit period T̃b, the minimum of the following criterion (for even N) is to be determined: <MAT>.

Inserting T̃b as defined above in <MAT> yields the clock signal timing T̃Clk.

No complex calculations are required with the exception of some multiplications. The sums can be continuously updated according to the "first in, first out" (FIFO) principle by subtracting a delayed signal.

The reference position for the data edges and the clock signals must be reinitialized at regular intervals to avoid an overflow. A corresponding correction must be made for the data output from the FIFO memories until reinitialized data is output.

The respective principle is outlined in <FIG> for a sum in the following form <MAT>.

As shown in <FIG>, the R block performs the reinitialization at the input and the S block the correction of the data from the FIFO memory.

Claim 1:
A method for recovering a clock signal from a data signal by using a clock recovery module (<NUM>), with the following steps:
- Accumulating edge timings of the data signal,
- Transforming the edge timings accumulated into one bit period interval by applying a modulo transformation, thereby obtaining a reference bit period,
- Determining a time offset for the reference bit period, wherein the time offset is chosen from a number of different time offsets by evaluating the difference of the accumulated edge timings with respect to a center of the bit period interval,
- Determining a reference clock signal based on the time offset,
- Determining the number of bits within a system clock of the clock recovery module (<NUM>), and
- Recovering the clock signal based on the reference clock signal and the number of bits.