Patent Description:
The present invention relates generally to programmable logic devices and, more particularly, to fast boot techniques for such devices.

Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources, including by way of non-limiting example programmable logic gates, look-up tables (LUTs), embedded hardware, interconnections, and/or other types of resources, available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs. The generated configuration data is loaded into configuration memory of the PLDs to implement the programmable logic gates, LUTs, embedded hardware, interconnections, and/or other types of configurable resources. The loading of the configuration data may take a considerable amount of time. Therefore, improved techniques for the loading of configuration data and PLD operation are desired.

<CIT> describes systems and techniques for configuration of a system on a programmable chip (SOPC). By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space. <CIT> discloses a FPGA, which is provided with a plurality of logic circuits and memories. By transmitting logic circuit information to the memories of the logic circuits which are not operating, and switching to the logic circuits which are operating when the transmission is completed, the FPGA is capable of operating such that there is no operational transmission period. <CIT> discloses a method and an apparatus, which is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.

It should be appreciated that like.

reference numerals are used to identify like elements illustrated in one or more of the figures.

The present invention provides a method as recited in claim <NUM>, an apparatus as recited in claim <NUM>, a computer implemented data processing as recited in claim <NUM>. Advantageous embodiments are recited in the dependent claims.

Various techniques are provided to facilitate fast boot for PLDs. In some aspects, a PLD may be implemented with fast boot capability to allow at least a portion of an input/output (I/O) fabric of the PLD to provide I/O functionality. Fast boot may also be referred to as fast wake up, fast activation, early boot, early wake up, early activation, or variant thereof. In some cases, alternatively or in addition, a portion of a logic fabric and/or other components of the PLD may be designated for fast boot. To this end, some functionality (e.g., I/O and/or logic functionality) of the PLD may be designated for fast boot.

In an aspect, to facilitate fast boot, configuration data associated with a portion of the I/O fabric designated for fast boot may be loaded into configuration memory cells associated with the portion of the I/O fabric. Once the configuration memory cells have been configured (e.g., programmed, loaded with configuration data), a wakeup signal may be provided to wake up (e.g., also referred to as activate) I/O functionality associated with the portion of the I/O fabric. In waking up the I/O functionality, the I/O functionality transitions from a configuration mode to a fast boot operation mode.

After the portion of the I/O fabric has been activated, remaining configuration memory cells of the PLD, which may include the logic fabric and any remaining portion of the I/O fabric, may be configured with corresponding configuration data and activated. Once all of the configuration data is loaded into the PLD, the PLD can wake up and provide functionality. In waking up the remaining functionality of the PLD, the functionality transitions to a full system operation mode (e.g., also referred to as normal operation mode). In an aspect, the I/O functionality designated for fast boot may transition from the fast boot operation mode to the full system operation mode, whereas the remaining.

functionality (e.g., functionality not designated for fast boot) may transition from the configuration mode to the full system operation mode. Alternatively or in addition to designating at least some I/O functionality for fast boot, logic functionality and/or other components of the PLD may be designated for fast boot.

The configuration data may be provided as a configuration bitstream. Configuration time for configuring (e.g., loading configuration data into) a PLD may be based on a configuration method, bitstream source, link speed of a bitstream (e.g., including the configuration bitstream) to be written into the PLD, and/or other factors. Prior to configuring the PLD using the configuration bitstream, the I/O fabric and logic fabric of the PLD may be in an unknown state or tri-stated state (e.g., aside from any hardcoded components of the PLD which are generally in a defined state at power on).

In providing fast boot of the I/O functionality, the PLD may provide predictable I/O behavior (e.g., I/O functionality) soon after powering up a device, without waiting for the entire PLD to be configured and activated prior to providing such I/O behavior. Such a device may include the PLD and/or may be controlled by the PLD. An example of a device may be a fan or a light emitting diode (LED). In this regard, the I/O functionality that is activated may drive proper polarity (e.g., on or off, <NUM> or <NUM>) with desired driver characteristics (e.g., I/O type, drive strength, pull up/down feature, etc.) to devices controlled by the PLD.

In some user-specified applications, a delay associated with providing the I/O behavior may adversely affect user and/or consumer experience and/or otherwise be undesirable. For example, LEDs controlled by the PLD may have undefined behavior (e.g., due to the undefined I/O functionality), which may be experienced as flickering or generally any misbehavior of the LEDs prior to the functionality being activated (e.g., placed in a defined state). By providing fast boot to allow early wake up of the I/O behavior of the PLD associated with the LEDs, the LEDs may receive appropriate control signals to define behavior of the LEDs. In these user-specified applications, other functionality of the PLD may be considered to be less critical, less time-sensitive, and/or less apparent and thus may be activated at a later time. As an example, in a case that the entire PLD is configured and activated in tens or hundreds of milliseconds, the portions of the PLD designated for fast boot may be configured and activated in the microseconds range (e.g., <NUM> - <NUM>,<NUM>). Time associated with configuration and activation for fast boot operation may be based at least in part on the amount of I/O and/or logic functionality designated for fast boot.

In some aspects, such I/O functionality provided by the PLD may be referred to as static state control, and fast boot of such I/O functionality may be referred to as fast boot static state control. Static state control may provide control to component coupled to the PLD that is generally independent of the PLD's logic fabric. In some cases, fast boot may be applied to a portion of the logic fabric of the PLD that controls I/O functionality. In these cases, the fast boot may facilitate static state control (e.g., I/O fabric-based control independent of logic fabric) and/or logic fabric controlled I/O.

In an aspect, security may be enabled for at least a portion of the configuration data. To enable security, one or more authentication certificates may be generated. In some cases, one or more authentication certificates may be provided for configuration data associated with fabric (e.g., I/O and/or logic functionality) designated for fast boot, and/or one or more authentication certificates may be provided for configuration data not designated for fast boot. Authentication may be performed based on the authentication certificate(s) before or after corresponding configuration data has been loaded into the PLD. For example, when a portion of the I/O fabric is designated for fast boot, a portion of the configuration data may be loaded into configuration memory cells associated with the portion of the I/O fabric. An authentication may be performed based on an authentication certificate(s) associated with the portion of the configuration data. If the authentication is successful, functionality associated with the portion of the I/O fabric can be activated and remaining configuration data loaded into the PLD. If the authentication is not successful, the configuration and activation of the PLD may be aborted.

In various aspects, portions of I/O and/or logic functionality of the PLD may be configured and activated to provide a stable, controlled state, prior to configuring and activating other functionality. In some cases, at least some I/O functionality may be designated for fast boot to effectuate a low I/O wakeup time of the PLD with respect to such I/O functionality. In some aspects, once the remainder of the PLD is configured and activated, seamless (e.g., glitchless) transition from a fast boot operation mode to a full system operation mode may be provided.

Referring now to the figures, <FIG> illustrates a block diagram of a PLD <NUM> in accordance with an embodiment of the disclosure. The PLD <NUM> (e.g., an FPGA, a CPLD, an FPSC, or other type of programmable device) generally includes I/O blocks <NUM> and programmable logic blocks (PLBs) <NUM>. In some cases, the PLD <NUM> may generally be any type of programmable device (e.g., programmable integrated circuit) with distributed configuration, which may involve loading configuration data through pins, shifting to appropriate locations in associated fabric, and configuring configuration memory cells. The PLBs may also be referred to as logic blocks, programmable functional units (PFUs), or programmable logic cells (PLCs). In an aspect, the PLBs <NUM> may collectively form an integrated circuit (IC) core or logic core of the PLD <NUM>. The I/O blocks <NUM> provide I/O functionality (e.g., to support one or more I/O and/or memory interface standards) for the PLD <NUM>, while the PLBs <NUM> provide logic functionality (e.g., LUT-based logic) for the PLD <NUM>. Additional I/O functionality may be provided by serializer/deserializer (SERDES) blocks <NUM> and physical coding sublayer (PCS) blocks <NUM>. The PLD <NUM> may also include hard intellectual property core (IP) blocks <NUM> to provide additional functionality (e.g., substantially predetermined functionality provided in hardware which may be configured with less programming than the PLBs <NUM>).

The PLD <NUM> may include blocks of memory <NUM> (e.g., blocks of erasable programmable read-only memory (EEPROM), block static RAM (SRAM), and/or flash memory), clock-related circuitry <NUM> (e.g., clock sources, phase-locked loop (PLL) circuits, and/or delay-locked loop (DLL) circuits), and/or various routing resources <NUM> (e.g., interconnect and appropriate switching circuits to provide paths for routing signals throughout the PLD <NUM>, such as for clock signals, data signals, control signals, wakeup signals, or others) as appropriate. The PLD <NUM> may include configuration and activation logic to receive configuration data, configure various programmable elements of the PLD <NUM>, and activate functionality associated with these programmable elements. In general, the various elements of the PLD <NUM> may be used to perform their intended functions for desired applications, as would be understood by one skilled in the art.

For example, certain of the I/O blocks <NUM> may be used for programming the memory <NUM> or transferring information (e.g., various types of user data and/or control signals) to/from the PLD <NUM>. Other of the I/O blocks <NUM> include a first programming port (which may represent a central processing unit (CPU) port, a peripheral data port, a serial peripheral interface (SPI) interface, and/or a sysCONFIG programming port) and/or a second programming port such as a joint test action group (JTAG) port (e.g., by employing standards such as Institute of Electrical and Electronics Engineers (IEEE) <NUM> or <NUM> standards). In various embodiments, the I/O blocks <NUM> may be included to receive configuration data and commands (e.g., over one or more connections) to configure the PLD <NUM> for its intended use and to support serial or parallel device configuration and information transfer with the SERDES blocks <NUM>, PCS blocks <NUM>, hard IP blocks <NUM>, and/or PLBs <NUM> as appropriate.

It should be understood that the number and placement of the various elements are not limiting and may depend upon the desired application. For example, various elements may not be required for a desired application or design specification (e.g., for the type of programmable device selected).

Furthermore, it should be understood that the elements are illustrated in block form for clarity and that various elements would typically be distributed throughout the PLD <NUM>, such as in and between the PLBs <NUM>, hard IP blocks <NUM>, and routing resources <NUM> to perform their conventional functions (e.g., storing configuration data that configures the PLD <NUM> or providing interconnect structure within the PLD <NUM>). For example, the routing resources <NUM> may be used for internal connections within each PLB <NUM> and/or between different PLBs <NUM>. It should also be understood that the various embodiments disclosed herein are not limited to programmable logic devices, such as the PLD <NUM>, and may be applied to various other types of programmable devices, as would be understood by one skilled in the art.

An external system <NUM> may be used to create a desired user configuration or design of the PLD <NUM> and generate corresponding configuration data to program (e.g., configure) the PLD <NUM>. For example, to configure the PLD <NUM>, the system <NUM> may provide such configuration data to one or more of the I/O blocks <NUM>, PLBs <NUM>, SERDES blocks <NUM>, and/or other portions of the PLD <NUM>. In this regard, the external system <NUM> may include a link <NUM> that connects to a programming port (e.g., SPI, JTAG) of the PLD <NUM> to facilitate transfer of the configuration data from the external system <NUM> to the PLD <NUM>. As a result, the I/O blocks <NUM>, PLBs <NUM>, various of the routing resources <NUM>, and any other appropriate components of the PLD <NUM> may be configured to operate in accordance with user-specified applications. In some cases, the I/O blocks <NUM> or portion thereof may be designated for fast boot. In some cases, the PLBs <NUM> or portion thereof may be designated for fast boot.

In the illustrated embodiment, the system <NUM> is implemented as a computer system. In this regard, the system <NUM> includes, for example, one or more processors <NUM> that may be configured to execute instructions, such as software instructions, provided in one or more memories <NUM> and/or stored in non-transitory form in one or more non-transitory machine readable media <NUM> (e.g., which may be internal or external to the system <NUM>). For example, in some embodiments, the system <NUM> may run PLD configuration software, such as Lattice Diamond System Planner software available from Lattice Semiconductor Corporation to permit a user to create a desired configuration and generate corresponding configuration data to program the PLD <NUM>.

In some embodiments, the memory <NUM> of the PLD <NUM> may include non-volatile memory (e.g., flash memory) utilized to store the configuration data generated and provided to the memory <NUM> by the external system <NUM>. During configuration of the PLD <NUM>, the non-volatile memory may provide the configuration data via configuration paths and associated data lines to configure the various portions (e.g., I/O blocks <NUM>, PLBs <NUM>, SERDES blocks <NUM>, routing resources <NUM>, and/or other portions) of the PLD <NUM>. In some cases, the configuration data may be stored in non-volatile memory external to the PLD <NUM> (e.g., on an external hard drive such as the memories <NUM> in the system <NUM>). During configuration, the configuration data may be provided (e.g., loaded) from the external non-volatile memory into the PLD <NUM> to configure the PLD <NUM>.

The system <NUM> also includes, for example, a user interface <NUM> (e.g., a screen or display) to display information to a user, and one or more user input devices <NUM> (e.g., a keyboard, mouse, trackball, touchscreen, and/or other device) to receive user commands or design entry to prepare a desired configuration of the PLD <NUM>.

<FIG> illustrates a block diagram of a PLD <NUM> with I/O fabric and logic fabric and an associated processing circuit <NUM> in accordance with an embodiment of the disclosure. The I/O fabric of the PLD <NUM> may be provided by I/O portions <NUM>, <NUM>, <NUM>, and <NUM>. The logic fabric of the PLD <NUM> may be provided by a logic core <NUM> (e.g., also referred to as an IC core). The I/O portions <NUM>, <NUM>, <NUM>, and/or <NUM> may include logic, resources (e.g., routing resources), configuration memory usable for storing configuration data, and/or generally any components, that are associated with facilitating providing of the I/O fabric's functionality. Similarly, the logic core <NUM> may include logic, resources (e.g., routing resources), configuration memory usable for storing configuration data, and/or generally any components, that are associated with facilitating providing of the logic fabric's functionality.

In an embodiment, the PLD <NUM> may be, may include, or may be a part of the PLD <NUM>. In an aspect, the I/O fabric of the PLD <NUM> may include the I/O blocks <NUM>, SERDES blocks <NUM>, PCS blocks <NUM>, and associated circuitry (e.g., routing resources <NUM>, clock-related circuitry <NUM>, and/or connections thereto, etc.). In an aspect, the logic fabric may include the PLBs <NUM>, hard IP blocks <NUM>, and associated circuitry.

The configuration memory of the PLD <NUM> may include an array of configuration memory cells usable to store configuration data (e.g., each configuration memory cell may store one bit). The array of configuration memory cells may be arranged in rows and columns. In an aspect, the I/O portions <NUM>, <NUM>, <NUM>, and/or <NUM> and the logic core <NUM> may include configuration memory cells (e.g., arranged in rows and columns) and form a portion of the array. The configuration memory cells may be volatile memory cells (e.g., RAM cells, such as SRAM cells). In some cases, the configuration memory cells may be referred to as configuration RAM (CRAM) cells. Although the present disclosure generally refers to various operations performed on rows and/or columns, rows may be used as columns and columns may be used as rows as appropriate. In an aspect, configuration memory cells associated with I/O and logic may be referred to as I/O block configuration memory cells and logic block configuration memory cells.

To configure (e.g., program) the PLD <NUM> (e.g., the I/O fabric and the logic fabric), the configuration data can be provided as a configuration bitstream that is loaded serially or in parallel into the configuration memory cells. In some cases, shifting may be performed serially, such as using JTAG or SPlx1 mode. Alternatively or in addition, in some cases, shifting may be in parallel, then followed by internally shifting parallel/serial, such as using SPIx4 mode or parallel x8 mode for example. The processing circuit <NUM> of the PLD <NUM> may include an address logic circuit <NUM> to assert an address (e.g., column address) of the PLD <NUM> and a data write circuit <NUM> to load corresponding configuration data into one or more configuration memory cells associated with the asserted address. For example, the address logic circuit <NUM> may be utilized to selectively assert columns of the array using respective address lines (not shown) to allow configuration data to be loaded into the configuration memory cells using the data write circuit <NUM>.

In <FIG>, the address logic circuit <NUM> may be, or may be utilized to control (e.g., using control signals), an address shifter to effectuate a column-by-column address shift (e.g., represented by address shift <NUM>) across columns of the PLD <NUM>. The data write circuit <NUM> may be, or may be utilized to control (e.g., using control signals), a data shifter to receive a portion of the configuration data corresponding to an asserted column and load the portion of the configuration data into corresponding configuration memory cells (e.g., represented by data shift <NUM>) of the PLD <NUM>. In this regard, the configuration data may be loaded into the PLD <NUM> one column at a time by pushing data to be written into a data shifter controlled by the data write circuit <NUM>, asserting a column address using the address logic circuit <NUM> to allow data to be written into configuration memory cells associated with the asserted column address, and loading the data into these configuration memory cells. Such pushing of configuration data, asserting of column address, and loading of configuration data may be performed for each subsequent column of the PLD <NUM> until the columns of the configuration memory have been loaded with their corresponding configuration data.

In some cases, the configuration data may include configuration memory frames, with the configuration data being written frame-by-frame into the configuration memory. For example, each configuration memory frame may include configuration data for one column of the PLD <NUM>, with each configuration memory frame being shifted into a corresponding column of the configuration memory.

The processing circuit <NUM> of the PLD <NUM> may include a wakeup circuit <NUM> to wake up (e.g., activate) functionality of the I/O fabric and logic fabric after the configuration data have been loaded into the configuration memory cells associated with (e.g., utilized to implement) the I/O fabric and logic fabric. In an aspect, wakeup may refer to transitioning the PLD <NUM> from a configuration mode, in which configuration data is being loaded into the PLD <NUM>, to a functional mode (e.g., also referred to as operational mode), in which the PLD <NUM> provides I/O and logic functionality. In this regard, after wakeup of the PLD <NUM> is complete, the PLD <NUM> is configured to operate using its I/O and logic fabric to provide I/O and logic functionality in accordance with user-specified applications. Such I/O and logic functionality may be effectuated through use of associated logic, resources (e.g., routing resources), stored configuration data, and/or other associated components. In some cases, a portion of the I/O fabric may provide static state control whereas another portion of the I/O fabric may be driven by (e.g., controlled by) the logic fabric.

In an embodiment, the processing circuit <NUM> may be, may include, or may be part of configuration and activation logic circuitry to receive configuration data, configure configuration memory cells of the PLD <NUM>, and activate functionality of the I/O fabric and/or logic fabric associated with the configuration memory cells. In some cases, at least a portion of such circuitry is hardcoded in the PLD <NUM>. For example, the address logic circuit <NUM>, data write circuit <NUM>, and wakeup circuit <NUM> may be hardcoded in the PLD <NUM>.

In one or more embodiments, configuration data can be loaded into a portion of a PLD and wakeup of these configured portions of the PLD may be performed to facilitate fast boot of some functionality of the PLD. In this regard, configured portions (e.g., also referred to as programmed portions) of the PLD may refer to portions of the array of configuration memory cells of the PLD into which a corresponding portion of configuration data has been loaded. Fast boot may allow designated functionality to be provided by configured portions of the PLD while other portions of the PLD are still being configured (e.g., configuration data is being loaded into these non-configured portions). In some aspects, the functionality designated for fast boot may include designated I/O functionality and, in some cases, designated core logic functionality to be provided by the PLD faster than in a case that the PLD waits for an entirety of the PLD to be configured before waking up any portion of the PLD.

In some aspects, a manufacturer of the PLD may define portion(s) (e.g., physical locations) of the PLD designated for fast boot. The portions of the PLD designated for fast boot may correspond to a subset of the array of configuration memory cells of the PLD. As such, the configuration memory cells in the subset may be loaded with configuration data prior to configuration memory cells not part of the subset to allow early configuration and wakeup of functionality associated with the subset. In some cases, the manufacturer may indicate (e.g., on a datasheet) which portions of the PLD are designated for fast boot. A user (e.g., a designer) may generate a user design in accordance with these designations from the manufacturer to leverage fast boot capability. For example, for a given user-specified application, a user may identify I/O and/or logic functionality considered by the user to be the most time sensitive and/or critical functionality to cause generation of a layout with such functionality provided in the portions of the PLD designated for fast boot (e.g., to be configured and activated prior to other portions of the PLD).

In implementing fast boot, portions of the PLD, such as portions of the I/O fabric and, in some cases, the logic fabric, may be configured into a known state and activated faster than in a case that the entire PLD is configured prior to wakeup. In some cases, the portions of the PLD designated for fast boot may be configured into a known state once a few frames of the configuration bitstream is loaded into the PLD and an associated wakeup performed to activate associated functionality. For example, the portions of the I/O fabric that are activated due to the fast boot may drive to a proper polarity and with desired driver characteristics (e.g., I/O type, drive strength, pull up/down feature, etc.), such as to effectuate control of a component (e.g., fan, LED) by the PLD.

<FIG> illustrates block diagrams of a PLD <NUM> with I/O portions <NUM> and <NUM> designated for fast boot at various stages of configuration and wakeup in accordance with an embodiment of the invention. The PLD <NUM> also includes I/O portions <NUM> and <NUM> and logic core <NUM> that are not designated for fast boot. In an embodiment, the PLD <NUM> may be the same as the PLD <NUM> except with the I/O portions <NUM> and <NUM> designated for fast boot. In some cases, the I/O portions <NUM> and <NUM> may be designated for fast boot by a manufacturer of the PLD <NUM>. To leverage the fast boot capability, the user may associate I/O functionality with the I/O portions <NUM> and/or <NUM> based on criteria (e.g., time sensitivity and/or importance of functionality) and associate other I/O functionality (e.g., less time-sensitive and/or less critical) with the I/O portions <NUM> and/or <NUM>.

The processing circuit <NUM> effectuates the fast boot by providing (e.g., using the address logic circuit <NUM> and data write circuit <NUM>) configuration data to configuration memory cells of the I/O portions <NUM> and <NUM> and, upon configuring the I/O portions <NUM> and <NUM>, activating, using the wakeup circuit <NUM>, the portion of the I/O fabric associated with the I/O portions <NUM> and <NUM>. Upon waking up the portion of the I/O fabric, the portion of the I/O fabric may provide its associated I/O functionality. After functionality associated with the I/O portions <NUM> and <NUM> are activated, the processing circuit <NUM> may configure and activate the other portions <NUM>, <NUM>, and <NUM> of the PLD <NUM>.

As an example, to configure the PLD <NUM>, the addresses associated with the I/O portion <NUM> may be asserted one at a time (e.g., starting with a leftmost column) and a configuration memory frame loaded into the asserted column until all columns of the I/O portion <NUM> are configured. In some cases, column addresses may be asserted such that contiguous columns are asserted from one iteration to the next iteration. The addresses associated with the I/O portion <NUM> may be asserted one at a time and a configuration memory frame loaded into the asserted column until all columns of the I/O portion <NUM> are configured. In some cases, configuration time associated with configuration of the I/O portions <NUM> and <NUM> may be facilitated (e.g., made more time efficient) through writing of the configuration bitstream frame-by-frame. For example, a first set of frames of the configuration bitstream (e.g., frames earlier in the bitstream) may be loaded into the I/O portion <NUM> and a last set of frames of the bitstream (e.g., frames toward an end of the bitstream) may be loaded into the I/O portion <NUM>.

As shown in <FIG>, once the I/O portions <NUM> and <NUM> are configured, the wakeup circuit <NUM> may generate and provide a wakeup signal to wake up the portions of the I/O fabric associated with the I/O portions <NUM> and <NUM> such that the portions of the I/O fabric may provide their functionality. In waking up the portions of the I/O fabric, the portions of the I/O fabric transition from a configuration mode to a fast boot operation mode such that the portions of the I/O fabric perform I/O functionality (e.g., as defined by the user). In this regard, such I/O functionality may be referred to as fast boot static state control. Configuration data associated with such I/O functionality are stored in the configuration memory cells of the I/O portions <NUM> and <NUM>.

As an example, the I/O functionality may include causing an LED controlled by the I/O fabric of the PLD <NUM> to turn on. In this example, by designating such I/O functionality for fast boot, the I/O functionality for controlling the LED by the PLD <NUM> may be defined earlier than in a case that the I/O functionality is provided after the entire PLD <NUM> is configured, thus reducing any flickering or misbehavior of the LED prior to the I/O functionality being placed in a defined state to control the LED.

To configure a remaining portion of the PLD <NUM>, the processing circuit <NUM> may use the address logic circuit <NUM> and data write circuit <NUM> to load configuration data into configuration memory cells of the I/O portions <NUM> and <NUM> and logic core <NUM>. In some cases, the I/O functionality associated with the I/O portions <NUM> and <NUM> may be in the process of being wakened up while configuration data is starting to be loaded into the remaining configuration memory of the remaining portions <NUM>, <NUM>, and <NUM> of the PLD <NUM>. In other cases, the I/O functionality is finished waking up prior to configuration data starting to be loaded into the remaining configuration memory of the PLD <NUM>.

In some embodiments, the I/O portions <NUM> and <NUM> and logic core <NUM> may be configured in any order and/or using any orientation (e.g., row-by-row, column-by-column, or any other manner). As an example, in configuring the logic core <NUM>, the address logic circuit <NUM> and data write circuit <NUM> may be configured as appropriate to assert rows or columns and load in associated configuration data based on the number of rows or columns of configuration memory cells in the logic core <NUM>. In some cases, in <FIG>, shifting column-by-column may be more efficient (e.g., faster, uses fewer address shifting, etc.) due to sharing the address and data shift units (e.g., <NUM>, <NUM>) utilized when configuring the I/O portions <NUM> and <NUM> designated for fast boot.

In some cases, configuration of the I/O portions <NUM> and <NUM> may be segmented. For example, in <FIG>, some columns of the I/O portion <NUM> overlap with columns of the I/O portions <NUM> and <NUM>, and similarly some columns of the I/O portion <NUM> overlap with columns of the I/O portions <NUM> and <NUM>. The processing circuit <NUM> may use the address logic circuit <NUM> and data write circuit <NUM> to load the configuration data column-by-column into the I/O portions <NUM> and <NUM>. In one example, the address shift <NUM> and data shift <NUM> may be used such that a column of the I/O portions <NUM> and <NUM> is asserted and associated configuration data loaded into configuration memory cells of the I/O portions <NUM> and <NUM> (e.g., and not the configuration memory cells of the I/O portions <NUM> and <NUM>) for the asserted column. In another example, the address shift <NUM> and data shift <NUM> may be used to assert each column of the I/O portion <NUM> and load associated configuration data into the I/O portion <NUM>, and then the address shift <NUM> and data shift <NUM> may be used to assert each column of the I/O portion <NUM> and load associated configuration data into the I/O portion <NUM>. In other cases, the address logic circuit <NUM> and data write circuit <NUM> may rotate their orientation such that the address logic circuit <NUM> asserts the I/O portions <NUM> and <NUM> row-by-row and the data write circuit <NUM> loads configuration data for the asserted row.

Other manners by which to configure the remaining portions <NUM>, <NUM>, and <NUM> may be utilized and may be selected based on criteria, such as speed considerations, complexity (e.g., number of operations), etc. Different portions of the PLD <NUM> may be configured using data and address shifts in different orientations (e.g., rotations) and/or with segmented data shift.

As shown in <FIG>, after the configuration data is loaded into the configuration memory cells of the remaining portions <NUM>, <NUM>, and <NUM> of the PLD <NUM>, the wakeup circuit <NUM> generates and provides a wakeup signal for the PLD <NUM> that allows wake up of I/O and logic functionality of the PLD <NUM>. In this regard, the portion of the I/O fabric associated with fast boot may transition from the fast boot operation mode to a system operation mode associated with the PLD <NUM>. The logic fabric and the remaining portion of the I/O fabric may transition from the configuration mode to the full system operation mode of the PLD <NUM>. In some cases, the portion of the I/O fabric associated with fast boot may have different functionality at the time of fast boot relative to the time at which the entire PLD <NUM> is configured. For example, a portion of the I/O fabric may provide static state control in the fast boot operation mode and then transition to logic-controlled I/O in the full system operation mode. In this regard, such portion of the I/O fabric may provide I/O functionality based on signals provided to the I/O fabric from the logic fabric.

Although examples are given above with regard to loading configuration data into the I/O portions <NUM> and <NUM> for fast boot configuration and activation and the remaining portions <NUM>, <NUM>, and <NUM> for normal configuration and activation, the configuration data may be loaded into the I/O portions <NUM> and <NUM> in any manner such that the I/O portions <NUM> and <NUM> are configured and subsequently the configuration data may be loaded into the remaining portions <NUM>, <NUM>, and <NUM> in any manner such that the remaining portions <NUM>, <NUM>, and <NUM> are configured. For example, the configuration data need not be loaded one column or row at a time into these portions <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. In addition, although <FIG> show the address shift <NUM> and the data shift <NUM>, multiple address shifts and multiple data shifts may be operated (e.g., serially or in parallel, synchronously or independently) to configure the I/O portions <NUM> and <NUM> for fast boot and/or the remaining portions <NUM>, <NUM>, and <NUM> afterwards.

<FIG> illustrates a block diagram of a PLD <NUM> with the I/O portions <NUM>, <NUM>, <NUM>, and <NUM> designated for fast boot in accordance with an embodiment of the present disclosure. The description of <FIG> generally applies to <FIG>, with examples of differences and other description provided herein. In an embodiment, the PLD <NUM> may generally be the same as the PLD <NUM> except with the I/O portions <NUM>, <NUM>, <NUM>, and <NUM> designated for fast boot.

To configure the PLD <NUM> for fast boot operation, various address shifts and data shifts (represented by <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) may be utilized to configure the I/O portions <NUM>, <NUM>, <NUM>, and <NUM>. Upon configuring the I/O portions <NUM>, <NUM>, <NUM>, and <NUM>, the I/O fabric of the PLD <NUM> may be activated to provide I/O functionality of the PLD <NUM>, thus transitioning the I/O fabric of the PLD <NUM> from a configuration mode to a fast boot operation mode. In conjunction with or after activating the I/O functionality, an address shift and a data shift (represented by <NUM> and <NUM>) may be utilized to configure the logic core <NUM>. The logic functionality associated with the logic fabric of the PLD <NUM> may be activated to transition from the configuration mode to a full system operation mode of the PLD <NUM>. The I/O functionality may transition from the fast boot operation mode to the full system operation mode.

The various address shifts and data shifts may be, or may be controlled by, the address logic circuit <NUM> and data write circuit <NUM>. Control signals from the address logic circuit <NUM> and data write circuit <NUM> are not shown in <FIG> for purposes of clarity. In <FIG>, the various address shifts and data shifts are perpendicular to each other. Different combinations of orientations may be utilized for the address shifts and data shifts. As one example, the shift <NUM> may be an address shift (e.g., column address shift) and shift <NUM> may be a data shift (e.g., shifting in data one column at a time). As another example, the shift <NUM> may be an address shift (e.g., row address shift) and shift <NUM> may be a data shift (e.g., shifting in data one row at a time).

In some cases, one or multiple address shifters and data shifters may be utilized for configuring the I/O portions <NUM>, <NUM>, <NUM>, and <NUM> and logic core <NUM>. As an example, when the I/O portions <NUM> and <NUM> are configured column-by-column, the shifts <NUM> and <NUM> may be implemented by a single column address shift and the shifts <NUM> and <NUM> may be a single data shifter for loading in configuration data of an asserted column. As another example, when the I/O portions <NUM> and <NUM> are configured column-by-column, the shifts <NUM> and <NUM> may be implemented by two (or more) column address shifters and the shifts <NUM> and <NUM> may be a two (or more) data shifters for loading in configuration data of two (or more) simultaneously asserted columns. In this latter example, the shifts <NUM> and <NUM> may operate independently of each other (e.g., the shifts <NUM> and <NUM> may be asserting different columns). Fewer, more, and/or different shifts other than those shown in <FIG> may be utilized.

<FIG> illustrates a block diagram of a PLD <NUM> with the I/O portions <NUM> and <NUM> and logic core portions <NUM> and <NUM> designated for fast boot in accordance with an embodiment of the present disclosure. The description of <FIG> generally applies to <FIG>, with examples of differences and other description provided herein. In an embodiment, the PLD <NUM> may generally be the same as the PLD <NUM> except with the I/O portions <NUM> and <NUM> and logic core portions <NUM> and <NUM> designated for fast boot.

The logic core <NUM> may include logic core portions <NUM>, <NUM>, and <NUM>. To configure the PLD <NUM> for fast boot, an address shift (e.g., <NUM>) and a data shift (e.g., <NUM>) may be utilized to configure the I/O portions <NUM> and <NUM> and logic core portions <NUM> and <NUM>. In one example, the address shift may begin configuration by asserting a left-most column of the I/O portion <NUM> and moving rightwards to a right-most column of the logic core portion <NUM>, and then begin configuration of the I/O portion <NUM> and logic core portion <NUM>.

Upon configuring the portions <NUM>, <NUM>, <NUM>, and <NUM>, the associated portion of the I/O fabric and logic fabric of the PLD <NUM> may be activated to provide associated I/O and logic functionality of the PLD <NUM>, thus transitioning the portion of the I/O fabric and logic fabric from a configuration mode to a fast boot operation mode. In this case, the portion of the I/O fabric may provide static state control and/or logic controlled I/O. In conjunction with or after waking up the portion of the I/O and logic functionality, one or more address shifts and/or data shifts may be utilized to load configuration data into configuration memory cells of the logic core portion <NUM> and I/O portions <NUM> and <NUM> to configure the portions <NUM>, <NUM>, and <NUM>. The I/O and logic functionality of the PLD <NUM> may be activated to transition to the full system operation mode of the PLD <NUM>. Other manners (e.g., orders, orientations) by which to configure the I/O portions <NUM>, <NUM>, <NUM>, and <NUM> and logic core portions <NUM>, <NUM>, and <NUM> may be utilized.

<FIG> illustrates a block diagram of a PLD <NUM> with the I/O portions <NUM>, <NUM>, <NUM>, and <NUM> and logic core portions <NUM>, <NUM>, <NUM>, and <NUM> designated for fast boot in accordance with an embodiment of the present disclosure. The description of <FIG> generally applies to <FIG>, with examples of differences and other description provided herein. In an embodiment, the PLD <NUM> may generally be the same as the PLD <NUM> except with the I/O portions <NUM>, <NUM>, <NUM>, and <NUM>, and logic core portions <NUM>, <NUM>, <NUM>, and <NUM> designated for fast boot.

To configure the PLD <NUM> for fast boot operation, various address shifts and data shifts (represented by <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>) may be utilized to configure the I/O portions <NUM>, <NUM>, <NUM>, and <NUM> and the logic portions <NUM> and <NUM>. In conjunction with or after waking up the portion of the I/O and logic functionality associated with the portions <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, shifts <NUM> and <NUM> may be utilized to configure a logic core portion <NUM>. The I/O and logic functionality of the PLD <NUM> may then be activated to transition to the full system operation mode of the PLD <NUM>.

Although <FIG> and <FIG> show examples of a PLD with I/O portions and/or logic portions being designated for fast boot, in some cases different I/O and logic portions may be defined in the PLD. For example, the I/O portion <NUM> may include a first portion designated for fast boot and a second portion not designated for fast boot. As indicated previously, more, fewer, and/or different address shifts and/or data shifts may be utilized to configure the PLD. In addition, although the foregoing describes the configuration memory cells of the I/O portions and/or logic core portions in terms of rows and columns with configuration memory cells designated for fast boot being provided by contiguous rows/columns, in some cases the configuration memory cells designated for fast boot may be distributed in other manners and need not be in contiguous columns/rows.

<FIG> illustrates a block diagram of an I/O control circuit <NUM> for activating and providing I/O functionality in accordance with an embodiment of the disclosure. The I/O control circuit <NUM> of <FIG> is primarily described with reference to the PLD <NUM> of <FIG> in which the I/O portions <NUM> and <NUM> are designated for fast boot, although the I/O control circuit <NUM> may also be utilized with other designations of I/O and/or control functionality such as those in <FIG>. For discussion purposes, the I/O control circuit <NUM> is associated with a portion of an I/O fabric of the PLD <NUM> designated for fast boot.

The I/O control circuit <NUM> includes an I/O pad <NUM> coupled to a logic fabric <NUM> via an output path or an input path. In an aspect, the logic fabric <NUM> may be provided by the logic core <NUM>. In some cases, a portion of the I/O control circuit <NUM> may be hardcoded in to the PLD <NUM>, such as logic of an I/O boot control logic circuit <NUM>, output driver <NUM>, and/or input logic circuit <NUM>.

With reference to the PLD <NUM>, once the I/O portions <NUM> and <NUM> are configured (e.g., loaded with configuration data), the I/O boot control logic circuit <NUM> may receive a wakeup signal (e.g., from the wakeup circuit <NUM>) and generate control signals in response to the wakeup signal to wake up of the I/O functionality associated with the I/O portions <NUM> and <NUM>. The control signals may be utilized as selector signals to control operation of multiplexers <NUM> and <NUM>. In this regard, the multiplexer <NUM> is coupled to four input lines: tri-state direct data (DD) line, flip-flop line, tri-state double data rate (DDR) line, and constant value line. The multiplexer <NUM> is coupled to three input lines: output DD line, output flip-flop line, and output DDR line. In some cases, the DD line and DDR line for the multiplexers <NUM> and <NUM> allow logic-driven I/O functionality. In <FIG>, the control signals of the I/O boot control logic circuit <NUM> may be selector signals to select one of the four input lines of the multiplexer <NUM> and one of the three input lines of the multiplexer <NUM>.

In some aspects, to facilitate fast boot operation, the I/O boot control logic circuit <NUM> may generate control signals to cause selection of the flip-flop lines of the multiplexers <NUM> and <NUM> or the constant value line of the multiplexer <NUM>. Values (e.g., <NUM> or <NUM>) stored in flip-flops <NUM> and <NUM> are provided on the flip-flop lines. In some cases, the flip-flops <NUM> and/or <NUM> may store a bit (e.g., <NUM> or <NUM> value) of the configuration bitstream. In other cases, the flip-flops <NUM> and/or <NUM> may store a bit (e.g., <NUM> or <NUM>) that is hardcoded into memory of the PLD <NUM>. In an aspect, when a portion of the logic fabric designated for fast boot operation (e.g., PLD <NUM> and <NUM>) is configured, the I/O boot control logic circuit <NUM> may generate control signals to cause selection of the flip-flop lines, constant value line (e.g., for the multiplexer <NUM>), DDR line, or DD line, such as based on logic provided by the portion of the logic fabric to allow logic-driven I/O functionality.

An output of the multiplexer <NUM> (e.g., the value stored in the flip-flop <NUM>) may enable an output driver <NUM> to drive a value onto the I/O pad <NUM> or disable (e.g., put in tri-state) the output driver <NUM>. When the output driver <NUM> is enabled for driving, the output driver <NUM> drives a value provided by an output of the multiplexer <NUM> (e.g., the value stored in the flip-flop <NUM>) to the output driver <NUM> onto the I/O pad <NUM>. For example, when the flip-flop <NUM> stores a <NUM>, the output driver <NUM> may be enabled and the value (e.g., <NUM> or <NUM>) stored in the flip-flop <NUM> is provided to the output driver <NUM> and driven (e.g., to logic low or logic high) onto the I/O pad <NUM> by the output driver <NUM>. When the flip-flop <NUM> stores a <NUM>, the output driver <NUM> may be disabled and any value received by the output driver <NUM> from the flip-flop <NUM> is not driven onto the I/O pad <NUM> by the output driver <NUM>. In an aspect, when the output driver <NUM> is disabled, the output driver <NUM> may be referred to as being in tri-state or high-impedance mode.

As an example, the I/O pad <NUM> may be coupled to a component (e.g., a fan, an LED) controlled by the I/O fabric of the PLD <NUM>. When a value of <NUM> (e.g., converted to a logic low) is driven onto the I/O pad <NUM>, the component may be off (e.g., turned off if the component is turned on or remain off if the component is already off). When a value of <NUM> (e.g., converted to a logic high) is driven onto the I/O pad <NUM>, the component may be on (e.g., turned on if the component is turned off or remain on if the component is already on).

On the input side, the I/O pad <NUM> may receive signals from an external component connected to the PLD <NUM>. An input buffer <NUM> may receive the signals from the external component via the I/O pad <NUM> and provide the signals to the input logic circuit <NUM>. The input logic circuit <NUM> may process the received signals and provide the processed signals to the logic fabric <NUM> to perform associated logic. In some cases, such as when logic functionality is not designated for fast boot, the input path is generally not used during fast boot operation since logic functionality provided by the PLD <NUM> has not been activated. In other cases, such as when a portion of the logic functionality is designated for fast boot, the input path may be utilized to receive signals from an external component and provide to the logic fabric <NUM> for processing.

Once the entirely of the PLD <NUM> is configured, the wakeup circuit <NUM> may provide a wakeup signal to transition the I/O and logic fabric to the full system operation mode. In transitioning from the fast boot operation mode to the full system operation mode, the I/O boot control logic circuit <NUM> may generate control signals to cause the multiplexers <NUM> and/or <NUM> to select from one of their respective input lines in accordance with a user-specified application, as shown in Table <NUM>. In this regard, the I/O boot control logic circuit <NUM> may, but need not, select the flip-flop input lines.

In one case, the I/O functionality effectuated through use of the I/O pad <NUM> and other components of the I/O logic control circuit <NUM> may remain unchanged between the fast boot operation mode and the full system operation mode. In this case, for example, the I/O boot control logic circuit <NUM> may generate control signals to cause the multiplexers <NUM> and <NUM> to select the flip-flops lines during the fast boot operation mode and the full system operation mode. Such I/O functionality may provide static state control in both the fast boot and full system operation modes.

In another case, the I/O functionality effectuated through use of the I/O pad <NUM> may differ between the fast boot operation mode and the full system operation mode. In this case, the I/O boot control logic circuit <NUM> may generate control signals to cause the multiplexers <NUM> and/or <NUM> to transition from selecting the flip-flop line to one of the other input lines, such as one of the DD, flip-flop, DDR, or constant value line. In an embodiment, to facilitate transition (e.g., seamless transition, glitchless transition) from the fast boot operation mode to the full system operation mode, DD or DDR values provided by the logic fabric <NUM> on the corresponding input lines of the multiplexers <NUM> and/or <NUM> may be reset to the same values as those stored in the flip-flops <NUM> and <NUM>. After reset, the logic fabric <NUM> may provide onto the DD or DDR lines values according to a user-specified application, where such values on the DD or DDR lines may be different from the values stored in the flip-flops <NUM> and <NUM>. For example, such logic-controlled I/O may be effectuated after a predetermined (e.g., threshold) amount of time after transitioning into the full system operation mode has elapsed to facilitate the transition.

Although <FIG> is described with respect to I/O designated for fast boot, in some cases the I/O control circuit <NUM> may be utilized with I/O not designated for fast boot. In such cases, the I/O boot control logic circuit <NUM> does not receive or does not respond to a wakeup signal associated with fast boot. The I/O boot control logic circuit <NUM> may generate control signals to control the multiplexers <NUM> and <NUM> (and thus control the output and input sides) in response to a wakeup signal received after the entire PLD has been configured.

<FIG> illustrates a flow diagram of an example design process <NUM> for a PLD in accordance with an embodiment of the invention. Note that one or more operations may be combined, omitted, and/or performed in a different order as desired. For example, the process of <FIG> may be performed by the external system <NUM> running Lattice Diamond software to configure the PLD.

At block <NUM>, the external system <NUM> receives a design that specifies a desired functionality of a PLD (e.g., <NUM>). For example, a user may interact with the external system <NUM> (e.g., through user input device <NUM> and hardware description language (HDL) code representing the design) to identify various features of the design (e.g., high level logic operations, hardware configurations, and/or other features. For example, the HDL representation may utilize register-transfer-level (RTL)-based design. In the user design, the user may set an attribute to designate for fast boot portions of the I/O fabric, portions of the logic fabric, and/or other components.

At block <NUM>, the external system <NUM> synthesizes the design into a set of netlist components that may be used to implement the design. For example, the external system <NUM> may provide a netlist that identifies various types of components by the PLD and their associated signals. The external system <NUM> may perform one or more rule checks to confirm that the design describes a valid configuration of the PLD. For example, the external system <NUM> may reject invalid configurations and/or request the user to provide new design information as appropriate.

At block <NUM>, the external system <NUM> performs a mapping process in which sets of the netlist components are grouped (e.g., packed) together. In some cases, the sets of the netlist components may include sets associated with I/O functionality and sets associated with logic functionality.

At block <NUM>, the external system <NUM> performs a placement process to assign the grouped netlist components associated with I/O functionality to particular physical components residing at specific physical locations of the PLD. For example, with reference to <FIG>, the placement process may place grouped netlist components associated with fast boot I/O functionality in physical locations (e.g., banks) of the PLD <NUM> designated for fast boot of I/O functionality, such as the physical locations of the I/O portions <NUM> and <NUM>. The placement process may place grouped netlist components not associated with fast boot I/O functionality in other physical locations, such as in the I/O portions <NUM> and <NUM>.

At block <NUM>, the external system <NUM> performs a placement process to assign the grouped netlist components associated with logic functionality to particular physical components residing at specific physical locations of the PLD (e.g., assigned to particular logic blocks and/or particular physical components within logic blocks). For example, the placement process may place grouped netlist components associated with fast boot logic functionality (if any) in physical locations (e.g., banks) of the PLD designated for fast boot of logic functionality.

Although the blocks <NUM> and <NUM> are provided as separate blocks in <FIG>, the blocks <NUM> and <NUM> may be performed separately or together. For example, I/O placement may occur together with logic placement. In another example, the placement of any fast boot functionality (e.g., fast boot I/O and/or logic functionality) may be performed prior to placement of any remaining I/O and/or logic functionality.

At block <NUM>, the external system <NUM> routes connections among the assigned physical components (e.g., using routing resources) to realize physical interconnections. By performing the blocks <NUM>, <NUM>, and <NUM>, the external system <NUM> determines a layout (associated with the received design) that includes positions of PLD components to be configured and activated to provide functionality (e.g., I/O and logic functionality) and associated routing.

At block <NUM>, the external system <NUM> generates configuration data for the determined layout (e.g., placed-and-routed design). For example, with reference to <FIG>, the configuration data may include I/O configuration data for the I/O portions <NUM> and <NUM> associated with fast boot I/O, I/O configuration data for the I/O portions <NUM> and <NUM>, and logic configuration data for the logic core <NUM>.

At block <NUM>, the external system <NUM> enables security for the configuration data. In an aspect, the external system <NUM> may generate one or more authentication certificates to allow authentication to be performed on configuration data after being loaded into configuration memory cells. In some cases, one or more authentication certificates may be generated for fast boot functionality and another one or more authentication certificates may be generated for the remaining functionality. In cases without authentication, block <NUM> is not performed.

In some aspects, the security may be based on keyed-hash message authentication code (HMAC) (e.g., generally faster), elliptic curve digital signature algorithm (EDCSA) (e.g., asymmetric keys), and/or others. In some cases, a certificate creator has a private key and a device holds a public key. Each authentication certificate may be or may include a bitstream digest generated based on the configuration bitstream or portion thereof. As an example, the bitstream digest may be generated by operating a secure hash algorithm (SHA) engine, such as a SHA-<NUM> engine, on the configuration bitstream or portion thereof.

In one case, one or more authentication certificates may be generated in connection with the fast boot functionality and one or more authentication certificates may be generated in connection with the remaining functionality.

At block <NUM>, the external system <NUM> provides the generated configuration data to facilitate configuration and wake up of the PLD. In an aspect, the configuration data may be provided as a configuration bitstream onto bitlines to be written in corresponding configuration memory cells (e.g., configuration SRAM cells). When configuring the PLD, the configuration data may be stored in non-volatile memory (e.g., flash memory) and then loaded from the non-volatile into voltage memory of the PLD. The non-volatile memory may be in the PLD and/or external to the PLD (e.g., external hard drive, external flash drive). An example of configuring and waking up the PLD is provided with respect to <FIG>.

<FIG> illustrates a flow diagram of an example process <NUM> for facilitating fast boot functionality of a PLD in accordance with an embodiment of the invention. For explanatory purposes, the example process <NUM> is described herein with reference to the PLD <NUM> of <FIG>, although the example process <NUM> may be utilized with other PLDs. Note that one or more operations may be combined, omitted, and/or performed in a different order as desired.

At block <NUM>, the processing circuit <NUM> receives configuration data associated with the PLD <NUM>. The configuration data may be generated by the external system <NUM>. In an aspect, the processing circuit <NUM> may obtain the configuration data from non-volatile memory of the PLD <NUM> (e.g., loaded into the non-volatile memory by the external system <NUM>) that is in the PLD <NUM> and/or external to the PLD <NUM>. The processing circuit <NUM> may receive the configuration data as part of a bitstream. In some cases, a preamble may be provided immediately before the configuration bitstream or as part of an initial sequence of bits of the configuration bitstream. The preamble may be a predetermined sequence of bits utilized as an indication of a beginning of the configuration data for the PLD <NUM>. When security is enabled, authentication certificates may be provided along with or as part of the configuration data.

At block <NUM>, the processing circuit <NUM> programs the subset of the configuration memory cells of the PLD <NUM> associated with fast boot functionality. The processing circuit <NUM> may cause the address logic circuit <NUM> to assert addresses associated with fast boot functionality and the data write circuit <NUM> to load in associated configuration data, prior to asserting addresses and loading configuration data associated with the remaining functionality (e.g., non-fast boot functionality) of the PLD <NUM>. For example, in <FIG>, following the preamble, the configuration data may include configuration data frames for the I/O portions <NUM> and <NUM>. As another example, in <FIG>, following the preamble, the configuration data may include configuration data frames for the I/O portion <NUM>, logic core portion <NUM>, logic core portion <NUM>, and I/O portion <NUM>. In some cases, the order and/or shifting orientation (e.g., row-by-row or column-by-column) in which the configuration data frames are loaded into the various portions (e.g., <NUM>, <NUM>) may be based on speed considerations, complexity (e.g., number of data shifting and/or address shifting operations), and/or other considerations.

At block <NUM>, the processing circuit <NUM> performs authentication of the configuration data stored in the subset of memory cells based on the corresponding authentication certificate(s). In an aspect, the authentication may be performed prior to block <NUM> (e.g., prior to storing the configuration data in the subset of the memory cells). For example, the authentication may be performed by running the incoming bitstream through an authentication engine, and then writing the configuration data to the subset of the memory cells. In some cases, read back and authentication (e.g., re-authentication) may be performed, although such processes may add latency. In this regard, any technique by which the configuration data that is stored or to be stored in the subset of memory cells may be determined to be intact may be utilized to authenticate the configuration data. At block <NUM>, the processing circuit <NUM> determines whether authentication is successful. In cases that security is not enabled for the configuration data, blocks <NUM> and <NUM> are not performed.

If the authentication is not successful, the process <NUM> proceeds to block <NUM>. At block <NUM>, the processing circuit <NUM> aborts the configuration and wake up of the PLD <NUM>.

In some cases, an indication may be provided (e.g., displayed) to the user to indicate that the configuration and wake up of the PLD <NUM> have been aborted.

If the authentication is successful, the process <NUM> proceeds to block <NUM>. The processing circuit <NUM> provides a wakeup signal to activate fast boot functionality. The wakeup signal may be generated by the wakeup circuit <NUM> of the processing circuit <NUM>. When the fast boot functionality is activated, the PLD <NUM> may provide the fast boot I/O functionality, thus transitioning the associated I/O fabric of the PLD <NUM> from a configuration mode to a fast boot operation mode. In other PLDs, such as the PLD <NUM> of <FIG>, when the fast boot functionality is activated, the PLD <NUM> may provide the fast boot I/O and logic functionality.

At block <NUM>, the processing circuit <NUM> programs remaining configuration memory cells of the PLD <NUM>. These remaining configuration cells are those not associated with fast boot functionality. As shown in <FIG>, these remaining configuration memory cells may be those in the I/O portions <NUM> and <NUM> and logic core <NUM>.

At block <NUM>, the processing circuit <NUM> performs authentication of the configuration data stored in these remaining memory cells based on the corresponding authentication certificate(s). In an aspect, the authentication may be performed prior to block <NUM> (e.g., prior to storing the configuration data in the remaining memory cells). More generally, in some cases, authentication procedures as described above with reference to block <NUM> may also apply to block <NUM>. At block <NUM>, the processing circuit <NUM> determines whether authentication is successful. In cases that security is not enabled for the configuration data, block <NUM> and <NUM> are not performed.

If the authentication is not successful, the process <NUM> proceeds to block <NUM>. At block <NUM>, the processing circuit <NUM> aborts the configuration and wake up of the PLD <NUM>. If the authentication is successful, the process <NUM> proceeds to block <NUM>. The processing circuit <NUM> provides a wakeup signal to activate functionality of the PLD <NUM>. The fast boot I/O functionality may transition from the fast boot operation mode to a full system operation mode. The logic functionality and remaining I/O functionality may transition from the configuration mode to the full system operation mode. The logic functionality and remaining I/O functionality may transition from the configuration mode to the full system operation mode.

Where applicable, various embodiments provided by the present disclosure can be implemented using hardware, software, or combinations of hardware and software. Also where applicable, the various hardware components and/or software components set forth herein can be combined into composite components comprising software, hardware, and/or both. Where applicable, the various hardware components and/or software components set forth herein can be separated into sub-components comprising software, hardware, or both. In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice-versa.

Software in accordance with the present disclosure, such as program code and/or data, can be stored on one or more non-transitory machine readable mediums. It is also contemplated that software identified herein can be implemented using one or more general purpose or specific purpose computers and/or computer systems, networked and/or otherwise. Where applicable, the ordering of various steps described herein can be changed, combined into composite steps, and/or separated into sub-steps to provide features described herein.

Claim 1:
A method comprising:
receiving (<NUM>) configuration data associated with a programmable logic device (PLD) (<NUM>), wherein the PLD comprises an array of configuration memory cells comprising a plurality of logic block memory cells associated with a logic fabric (<NUM>) of the PLD and a plurality of input/output (I/O) block memory cells associated with an I/O fabric (<NUM>, <NUM>, <NUM>, <NUM>) of the PLD;
programming (<NUM>) a first subset of the I/O block memory cells with a first portion of the configuration data;
providing (<NUM>) a first wakeup signal to wake up functionality associated with a first portion (<NUM>, <NUM>) of the I/O fabric associated with the first subset of the I/O block memory cells;
in response to the first wakeup signal, transitioning the first portion of the I/O fabric from a configuration mode to a fast boot operation mode;
programming (<NUM>) remaining configuration memory cells of the array with a second portion of the configuration data, wherein the remaining configuration memory cells comprise a second subset of any remaining portion of the I/O block memory cells and at least a subset of the logic block memory cells;
operating the first portion of the I/O fabric while the programming the remaining configuration memory cells is performed;
providing (<NUM>) a second wakeup signal to wake up functionality associated with a second portion (<NUM>, <NUM>) of the I/O fabric associated with the second subset of the I/O block memory cells and at least a portion of the logic fabric associated with the subset of the logic block memory cells; and
in response to the second wakeup signal, transitioning the first portion of the I/O fabric from the fast boot operation mode to a system operation mode and transitioning the second portion of the I/O fabric and the portion of the logic fabric from the configuration mode to the system operation mode.