Patent Description:
Piezoelectric materials have been used in transducers to reversibly transfer strain to thin films of other materials, including semiconductors, for the purpose of tuning the electrical, optical, and electrooptical properties of those materials. In such transducers, the magnitude of strain induced in the thin film is proportional to the electric field applied across the piezoelectric material. Devices that have been fabricated based on this design include those in which piezoelectric actuation is used to tune the optical emission spectra and the electroacoustic properties of semiconductor films. However, conventional piezoelectric transducers require a bonding agent between the piezoelectric substrate and the semiconductor in order to bond the two materials together. These bonding agents have included polymer adhesives (e.g., parylene gluing), metal layers (e.g., eutectic bonding), and glass.

Unfortunately, intermediate bonding layers between a semiconductor film and a piezoelectric substrate can affect strain transfer between the piezoelectric substrate and the semiconductor film and attenuate the acoustic amplitude of a piezoelectric transducer. Moreover, bonding agents may be incompatible with biological environments, limiting the applications in which piezoelectric transducers with bonding layers can be used.

Scientific article "<NPL>) discloses the development of high performance surface acoustic wave devices by using graphene as a virtually massless interdigital transducer to mitigate mass-loading effects. Scientific article "<NPL>) discloses the development of an electromechanical device that can apply biaxial compressive strain to trilayer MoS<NUM> supported by a piezoelectric substrate and covered by a transparent graphene electrode. Scientific article "<NPL>) discloses a method to produce free-standing graphene sheets from epitaxial graphene on silicon carbide (SiC) substrate. Scientific article "<NPL>) discloses the investigation of two electrochemical polishing techniques to improve silicon carbide substrate surfaces prior to epitaxial growth. The techniques were compared with a mechanical polishing procedure involving various grades of diamond paste. "<NPL>) discloses an investigation of the structure of and electrical transport across the interface of a Si/Ge bilayer formed by direct, low-temperature hydrophobic bonding of a <NUM> thick monocrystalline Si(<NUM>) membrane to a bulk Ge(<NUM>) wafer.

Piezoelectric transducers composed of semiconductor - piezoelectric composite structures and methods for fabricating the transducers are provided.

One embodiment of a piezoelectric transducer includes: a piezoelectric substrate having a membrane-bonding surface with a surface roughness of no greater than <NUM> RMS; a semiconductor membrane having a thickness of no greater than <NUM> bonded directly to the membrane-bonding surface, such that the surface of the semiconductor membrane and the piezoelectric substate are in direct physical contact with one another at an interface, and no other material is applied or inserted between the surface of the semiconductor membrane and the piezoelectric substrate at the interface to create a bond, wherein the semiconductor membrane is a silicon membrane, a germanium membrane, a group III-V semiconductor membrane, or a group II-VI semiconductor membrane; and a set of electrodes in electrical communication with the piezoelectric substrate and configured to apply an electric signal to the piezoelectric substrate.

One embodiment of a method of forming a piezoelectric transducer includes the steps of: forming a semiconductor membrane having a thickness of no greater than <NUM>, wherein the semiconductor membrane is a silicon membrane, a germanium membrane, a group III-V semiconductor membrane, or a group II-VI semiconductor membrane; polishing a membrane-bonding surface of a piezoelectric substrate to a surface roughness of no greater than <NUM> RMS; and directly bonding the semiconductor membrane to the membrane-bonding surface of the piezoelectric substrate, such that the surface of the semiconductor membrane and the piezoelectric substate are in direct physical contact with one another at an interface, and no other material is applied or inserted between the surface of the semiconductor membrane and the piezoelectric substrate at the interface to create a bond.

Other principal features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.

Illustrative embodiments of the invention will hereafter be described with reference to the accompanying drawings, wherein like numerals denote like elements.

Semiconductor - piezoelectric composite structures constructed from thin semiconductor membranes bonded to piezoelectric substrates are provided. Methods for fabricating the structures are also provided. The semiconductor membranes can be actuated piezoelectrically by applying an electric signal to the substrate. This actuation of the semiconductor membrane can be used to provide a transducer that modulates various properties of the semiconductor membranes, making them useful in a variety of devices. Examples of devices into which the composite semiconductor - piezoelectric devices can be incorporated include chemical, including biochemical, sensors, optoelectronics, and strain-responsive electronics.

Aspects of the invention described herein are based, at least in part, on the inventors' discovery that the use of a piezoelectric substrate having an ultra-smooth surface enables the bonding of a semiconductor membrane directly to the surface of a piezoelectric substrate without the use of any bonding agents. The directly bonded membrane adheres strongly to the piezoelectric substrate and the bonding can provide a flat (i.e., unwrinkled) membrane that well suited for microelectronic device integration.

The semiconductor membrane can be formed and microelectronic devices can be patterned on the semiconductor membrane prior to bonding the semiconductor membrane to the piezoelectric substrate. This offers the benefit of combining two pre-fabricated and well-defined device materials and eliminates the need to modify the semiconductor membrane and/or the piezoelectric substrate after the two layers have been integrated.

The semiconductor membranes are thin films of a semiconductor material. The use of a thin semiconductor membrane allows for the piezoelectric actuation of membrane properties, including optoelectronic (e.g., photoluminescence and electroluminescence) and/or electroacoustical properties. The semiconductor membranes have thicknesses of <NUM> or less. This includes semiconductor membranes having a thickness of <NUM> or less, semiconductor membranes having a thickness of <NUM> or less, and semiconductor membranes having a thickness of <NUM> or less. By way of illustration, some of the semiconductor membranes have thicknesses in the range from <NUM> to <NUM>. The semiconductor membranes can be single-crystalline, polycrystalline, or amorphous. The use of single-crystalline semiconductor membranes is advantageous because the membranes can have standard microelectronic devices patterned on the semiconductor element prior to bonding to a piezoelectric substrate, and because the membranes are very conformal, which allows them to bond better than their bulk counterparts.

The semiconductor membranes can be obtained by releasing a thin film of semiconductor material from a support substrate or a substrate structure on which the semiconductor film was originally grown. For example, a silicon membrane can be obtained by releasing the silicon device layer from a silicon-on-insulator substrate, as illustrated in panels (a) - (c) of <FIG>. The process begins with silicon-on-insulator (SOI) wafer that includes a handle substrate <NUM>, a buried oxide (BOX) layer <NUM>, and a thin single-crystalline silicon device layer <NUM>. In the embodiment of the process shown in <FIG>, panels (a) through (c), a layer of photoresist (PR) <NUM> is applied to the top surface of silicon device layer <NUM> using, for example, spin-coating. Silicon device layer <NUM> is then released from handle substrate <NUM> by submerging silicon device layer <NUM> in a solution comprising an etchant that is selective for silicon oxide, such as hydrofluoric acid (HF), to selectively etch away BOX layer <NUM> (<FIG>, panel (b)). Optionally, silicon device layer <NUM> can be thinned using, for example, a chemical or mechanical polish prior to the application of photoresist <NUM> and/or release from sacrificial oxide layer <NUM>.

Photoresist layer <NUM> serves as a buoyancy aid and protective layer during membrane release (<FIG>, panel (b)). Thus, the photoresist is desirably selected such that it renders the released semiconductor/photoresist bilayer buoyant in the etchant solution. The use of a buoyancy aid may be advantageous for very thin semiconductor membranes (e.g., membranes having thicknesses of about <NUM> or less) because it helps to prevent the released membranes from settling back onto handle substrate <NUM> after release. However, the use of photoresist layer <NUM> is not necessary, particularly for thicker membranes. If photoresist layer <NUM> is used, it can be removed from semiconductor membrane <NUM> after release using a suitable PR stripper (<FIG>, panel (c)). Other suitable resists include electron-beam (E-beam) resists, such as novolak-based resists, including S1813 available from Dow (Shipley), and acrylate-styrene co-polymer resists, such as ZEP520, a copolymer of α-chloromethacrylate and α-methylstyrene, available from Zeon Chemicals.

Semiconductors other than silicon can be used as the semiconductor membrane. These include germanium (Ge). Other suitable semiconductors include Group III-V semiconductors and Group II-VI semiconductors. The Group III-V and Group II-VI semiconductors include binary, ternary, and higher compound semiconductors. Examples of Group III-V semiconductors include GaAs, AlGaAs, InGaAs, AlAs, InAlAs, InP, GaInP, GaP, GaN, InGaN, InAlN, and AlGaN. Examples of Group II-VI semiconductors include oxides, such as ZnO. Thin films of these other semiconductors can be released from their growth substrates by selectively etching away the substrate or an intervening sacrificial layer, such as a buried oxide, in a manner analogous to that described above for silicon.

Microelectronic devices can be formed on the semiconductor membrane before or after it is released from its substrate and prior to or after bonding the membrane to the piezoelectric substrate. The microelectronic devices can be formed using, for example, lithography, etching, or printing. Microelectronic devices will generally include active and passive electrical components that make up a circuit, including electrical contacts, transmission lines, capacitors, transistors, and the like. The specific components and their location on the membrane will depend on the particular application for which the devices are designed.

In some embodiments of the semiconductor membrane - piezoelectric substrate structures, the piezoelectric substrate defines an aperture and the semiconductor membrane is bonded to the piezoelectric substrate around the perimeter of the aperture, such that a portion of the semiconductor membrane is suspended over the aperture. In embodiments of the structures that include an aperture in the piezoelectric substrate, the components of the microelectronic devices may be positioned such that they are located over the portion of the semiconductor membrane that is suspended over the aperture in the piezoelectric substrate, and/or they may be positioned such that they are located over the piezoelectric material substrate around the aperture.

Once semiconductor membrane <NUM> is released, it can be transferred onto a piezoelectric substrate <NUM> and then bonded to the surface of that substrate, as illustrated in panels (d) and (e) of <FIG>. The transfer can be a wet transfer, whereby semiconductor membrane <NUM> is lifted out of solution by piezoelectric substrate <NUM>, or a dry transfer, whereby semiconductor membrane <NUM> is removed from the etching solution and then transferred onto piezoelectric substrate <NUM> using a stamp. In the particular embodiment shown here, the piezoelectric substrate defines an aperture <NUM> through its thickness. However, for many device applications, no aperture is needed. The "H" on panels (d) and (e) represents electronic components integrated on the suspended portion of semiconductor membrane <NUM>.

The piezoelectric substrate can be a bulk material, such as a wafer. Piezoelectric materials that can be used include lead zirconium titanate (PZT), which may be undoped or doped with La, Mn, or Nb, lithium niobate, lead magnesium niobate-lead titanate (PMN-PT), lead zinc niobite-lead titanate (PZN-PT), KxNa<NUM>-xNbO<NUM> (KNN), BaxSr<NUM>-xTiO<NUM> (BST), Ba(TixZr<NUM>-x)O<NUM>-(BayCa -y)TiO<NUM> (BCTZ), or NaxBiyTiO<NUM>-BaTiO<NUM> (NBT-BT), LiNbO<NUM>, gallium phosphate, quartz, and tourmaline.

In order to facilitate direct bonding between the semiconductor membrane and the surface of the piezoelectric substrate, the surface of the piezoelectric substrate should have a low surface roughness. Therefore, prior to transferring the semiconductor membrane to the piezoelectric substrate, the membrane-bonding surface <NUM> of piezoelectric substrate <NUM> can be polished to reduce its RMS roughness in order to enable high-quality, direct bonding between the membrane and the substrate. The piezoelectric substrates can be polished using mechanical polishing with readily available polishing media suitable for ceramics. The surface should be polished to an RMS roughness of <NUM> or less, including <NUM> or less, and <NUM> or less. RMS surface roughness, as measured by atomic force microscopy.

As used herein, the phrases "direct bonding" or "bonded directly to" mean that the surface of semiconductor membrane and the surface of the piezoelectric substrate are in direct physical contact with one another at an interface and that no other material is applied or inserted between them at that interface in order to create a bond between the semiconductor membrane and the piezoelectric substrate. Thus, the methods described herein are distinguishable from methods in which a semiconductor is bonded to a substrate using bonding agents, where the term "bonding agent" refers to a material, such as a chemical adhesive or a deliberate chemical surface functionalization, that is disposed between the semiconductor membrane and the piezoelectric substrate that strengthens the bonding of the semiconductor membrane to the piezoelectric substrate. Such bonding agents include polymer-based adhesives, such as parylene and epoxy resins, and intervening layers of glass or metals, including metal thermo compression layers and/or metal eutectics, such as gold eutectics or gold-tin eutectics. It should be noted, however, that electrical components, such as electrodes and/or electrical interconnects can be located between the semiconductor membrane and the piezoelectric substrate, provided that there still exists direct bonding of the semiconductor membrane to a bonding surface of the piezoelectric membrane around such electrical components. And, while in some embodiments of the structures, one or more electrical components are located between the semiconductor membrane and the piezoelectric substrate, in other embodiments there are no electrical components disposed between the membrane and the substrate.

The bonding of the transferred semiconductor membrane to the membrane-bonding surface of the piezoelectric substrate can be carried out by annealing in an ambient environment. Annealing is not, however, necessary. The membrane may simply be allowed to dry without annealing. If annealing is used, illustrative annealing conditions include temperatures up to <NUM> (e.g., <NUM> to <NUM>) for up to <NUM> (e.g., <NUM> to <NUM>) to eliminate water. As a result of the bonding process, semiconductor membrane <NUM> covers aperture <NUM> and is directly bonded to surface <NUM> around the perimeter of aperture <NUM>. In the embodiment shown in <FIG>, aperture <NUM> is a round hole (shown bisected in the cross-sectional view of <FIG>). However, the perimeter of the aperture need not be round; it can have a variety of regular or irregular shapes, including oval, square, rectangular, and the like, and the aperture need not extend through the entire thickness of the piezoelectric substrate. Moreover, as previously noted, the aperture need not be present.

The semiconductor - piezoelectric composite structures made according to the methods described herein use the piezoelectric effect to convert electrical energy into a mechanical displacement. This enables a number of piezoelectrically actuated devices, including chemical sensors, optoelectronics, strain-responsive electronics, and electroacoustic devices.

A set of two or more electrodes can be used to apply an electric signal to the piezoelectric substrate to elicit a piezoelectric response. For example, an external stress can be applied to the semiconductor membrane by applying a voltage V between a first electrode and a second electrode, both of which are in electrical communication with the piezoelectric substrate. In some embodiments of the structures, one or more of the electrodes forms and antenna. The electrodes can be placed, for example, on opposing sides or surfaces of the piezoelectric substrate or on the same surface of the piezoelectric substrate. The electrodes can be in direct contact with the piezoelectric substrate or can make contact with the piezoelectric substrate through one or more electrically conducting layers. The application of a voltage across the piezoelectric substrate using an external electric signal source in electrical communication with the electrodes creates a distortion of the piezoelectric material that actuates strain in the semiconductor membrane. This strain actuation can be harnessed for a variety of device applications. For example, a DC signal applied to the piezoelectric substrate can be used to induce an expansion and contraction of the piezoelectric substrate, thereby imparting strain to the adherent semiconductor membrane.

The controlled and reversible application of strain to the semiconductor membrane is useful in controlling the efficiency and/or wavelength of light emission from photoluminescent or electroluminescent semiconductor membranes, such as Group III-V membranes (e.g., InGaAs), Ge membranes, and dichalcogenide membranes which undergo a strain-induced direct bandgap transition with strain. The piezoelectric device could also be used in radiofrequency nanoelectromechanical (RF-NEMS) devices, where piezoelectric activity is used for active antenna applications.

Additional device applications are enabled by forming one or more apertures in the piezoelectric substrate and bonding the semiconductor membrane to the surface of the piezoelectric substrate around the perimeter of the one or more apertures, such that a portion of the membrane is suspended over the one or more apertures. For example, a semiconductor membrane bonded to a piezoelectric substrate and suspended over an aperture in the piezoelectric substrate can be acoustically coupled to the substrate, such that surface wave induced in the piezoelectric substrate by the application of an electric signal to the substrate are conducted to the semiconductor membrane. Devices of this type have applications as eardrum transducers, as described in <CIT>.

In another application, one or more through-holes are defined in the semiconductor membrane, such that the semiconductor membrane - piezoelectric substrate structure can be used as a micro- or nano-valve. By applying an electric signal to the piezoelectric substrate, the substrate aperture can be reversible expanded and contracted, resulting in the opening and closing of the one or more holes in the semiconductor membrane.

Another application for a structure in which the piezoelectric substrate defines an aperture and the semiconductor membrane includes one or more through-holes is in nanopore DNA sequencing. In nanopore DNA sequencing the membrane defines one or more through-holes sized to allow a single DNA molecule to pass. As a DNA molecule traverses the through-hole, different bases generate different electric current densities across the hole. In this manner, the through-hole acts as an antenna. A second antenna can be positioned to electrically couple to the nanopore antenna. The sequence of the DNA can be determined by measuring the resulting current fluctuations. The magnitude of electric current density across a through-hole depends on the diameter of the hole and the composition of the DNA that occupies the hole. Using the semiconductor membrane - piezoelectric substrate structures described herein, the through-hole diameter can be modulated by applying an electric signal to the piezoelectric substrate that induces a strain in the membrane. More details regarding the operation and microelectronic components and circuitry of nanopore DNA sequencers can be found in <CIT>.

This example illustrates the fabrication of composite semiconductor membrane-piezoelectric substrate structures that include a single-crystalline semiconductor (silicon) nanomembrane bonded to a machined and polished bulk PZT substrate having a circular opening defined therein. Although these are the specific materials used in this example, the process described here can be used with other semiconductors and piezoelectric materials.

To prepare the substrates, the membrane-bonding surfaces of bulk PZT wafers were polished to an RMS roughness of approximately <NUM>. The polishing was achieved by mounting the PZT wafer to a lapping plate with Crystal Bond, and polishing with varying sized suspended alumina media (down to <NUM>) on a Logitec PM5 manual polisher. Holes from <NUM>-<NUM> were mechanically drilled using <NUM> - <NUM> drill bits.

The silicon nanomembranes were obtained by releasing the device layers from silicon-on-insulator (SOI) substrates. The process generally started with <NUM> device layer thickness SOI that was thinned to the desired thickness (<NUM>, <NUM>, and <NUM>) using cycles of wet thermal oxidation in a Tystar oxidation furnace and sacrificial oxide stripping in hydrofluoric acid (HF). The SOI substrate was patterned to define the size of the membrane with standard photolithography, using <NUM> (Shipley) photoresist (PR). The photoresist was applied by spin coating according to the manufacturer's instructions. Silicon membranes having thickness of <NUM>, <NUM>, and <NUM> were released from SOI substrates by selectively etching the buried oxide layer (which is an intermediate layer between the membrane and handle wafer) in <NUM>% HF. For the membranes thinner than <NUM>, the PR layer was left intact on the surface of the device layer prior to its release. This PR layer serves as a buoyancy aid for thin membranes and enables easier handling. After membrane release in HF and a subsequent distilled deionized (DI) water rinse, the PR coating was removed using N-N dimethylacetamide, which minimized damage to the membranes during the subsequent water transfer to the polished PZT substrates. The water transfer method employed a wire loop, which was used to "fish" the membranes out of the DI water by forming a thin film of water containing the membrane within the loop. This water film-membrane was then transferred to the PZT substrate by contacting the loop to the substrate, causing the water containing the membrane to transfer to the substrate. Generally, the substrate/membrane was heated on a hotplate at up to <NUM> for <NUM> to evaporate the water; although this step is not required, it shortens the time for water evaporation.

The procedure described above produced samples having relatively flat silicon membranes over the circular holes (apertures) in the PZT substrates and good bonding between the silicon nanomembranes and the PZT around the perimeters of the holes. Notably, the method of bonding the silicon membranes to the PZT does not require deleterious high-temperature processing and intermediate layers. Therefore, the integrity of the membranes and any devices that have been patterned on the membranes can be maintained, and the need to re-pole the PZT can be circumvented, as no thermal treatment is required.

<FIG> shows that polishing the PZT substrates resulted in significantly flatter membranes bonded around the hole, resulting in flatter suspended membranes over the hole and significantly better bonding of the two materials. The rings visible in some of the images are from gold electrodes patterned on the PZT prior to transfer. The images in the right panel (non-polished PZT) demonstrate rippling in the bonded membrane (<NUM>) and no bonding at all (<NUM>). <FIG> further demonstrates that this general method works for membranes of various thickness.

The word "illustrative" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Further, for the purposes of this disclosure and unless otherwise specified, "a" or "an" means "one or more.

Claim 1:
A piezoelectric transducer comprising:
a piezoelectric substrate (<NUM>) having a membrane-bonding surface (<NUM>) with a surface roughness of no greater than <NUM> RMS;
a semiconductor membrane (<NUM>) having a thickness of no greater than <NUM> bonded directly to the membrane-bonding surface, such that the surface of the semiconductor membrane and the piezoelectric substate are in direct physical contact with one another at an interface, and no other material is applied or inserted between the surface of the semiconductor membrane and the piezoelectric substrate at the interface to create a bond, wherein the semiconductor membrane is a silicon membrane, a germanium membrane, a group III-V semiconductor membrane, or a group II-VI semiconductor membrane; and
a set of electrodes in electrical communication with the piezoelectric substrate and configured to apply an electric signal to the piezoelectric substrate.