Patent Description:
This document pertains generally, but not by way of limitation, to integrated circuits and, and particularly, but not by way of limitation, to digital modulation techniques for use within a single integrated circuit or between multiple integrated circuits.

Isolated analog-to-digital converters (ADCs) are used in a number of applications, for example, where sensors, motors, or other components operate at a different voltage level than related information processing.

<CIT> discloses a circuit package for providing isolation between a controller on a first side of a switched power supply and a second side of the switched power supply. An isolation link provides voltage isolation between the first and second sides and includes on the first sides circuitry for transmitting a driver signal received from the controller and circuitry for receiving a voltage feedback signal responsive to a sensed output voltage on the second side. The second side includes circuitry for receiving the driver signal and also circuitry for transmitting the voltage feedback signal.

<CIT> discloses an isolation system, in which analog to digital converters are provided on a first side of an isolation barrier. Outputs from the ADCs may be merged into a common data stream and communicated across the isolation barrier by a single isolation device.

<CIT> discloses a power measurement, circuit breaker or integrated protection system including isolated analog-to-digital modulators for measuring current using current sensors.

Various examples described herein are directed to an isolated analog-to-digital converter (ADC) circuit. The invention is set out in the appended claim set.

An isolated ADC circuit, as described herein, comprises at least a hot side and a cold side. The hot side and cold side are galvanically isolated from one another and may operate at different voltages and/or be referenced to different grounds. For example, an isolated ADC circuit may have a hot side with an ADC that is powered at a voltage (e.g., <NUM> volts) that is referenced to the line voltage of a power transmission or delivery line (e.g., 120V RMS 230V RMS, 440V RMS or a DC Voltage such as +/-270V or 48V or 1000V). In this way, the ADC at the hot side may directly measure the current in a shunt that is series with the delivery or transmission line. The example isolated ADC circuit also has a cold side that is referenced to a different ground (e.g., the neutral line, earth, a floating voltage, etc.). The supply voltage for the cold side electronics may be at a lower voltage for digital processing (e.g., <NUM>. 2V, etc.) and/or a high voltage for actuation or display or communications (e.g. 12V, 5V or <NUM>.

Isolation between the hot and cold sides is provided by an isolator. Any suitable isolator may be used. Example isolators that may be use isolation mechanisms such as a transformer or other inductive isolator, a capacitive isolator, an optical isolator, etc. The isolator may include transmit and receive circuitry either side of the isolation mechanism that will be able to withstand constant and surge voltages without breaking down. In some examples, the isolation technology may be optimized to some degree to reject EMC and other transient events, but because of stray coupling mechanisms and imbalances it is possible for surges and/or electrical fast transient events to corrupt the data being sent across the isolators. In some examples, it is desirable for systems that use isolators, such as isolated ADC circuits, to be tolerant to this type of corruption.

In some examples, inductive isolator mechanisms may be selected to transmit power from the cold side to the hot side. This can be beneficial to power the function on the hot side even if the efficiency of the power transmitted is low. In systems optimized to use isolated power, power consumption on the hot side effectively 'costs' more than on the cold side due to this inefficiency and so it is often desirable to minimize it.

The hot and cold sides, in some examples are implemented on separate semiconductor dies (e.g., silicon dies). A hot side die and a cold side die may be packaged in a common integrated circuit package or implemented in separate integrated circuit packages. The isolator may be positioned on the hot side die, on the cold side die, on a separate, additional die or combinations thereof. In some examples, when the hot side die and cold side die are included in a common integrated circuit package. For example, the dies may be on separate lead frame sections or separate sections of a planar substrate or a stacked-die design could be used, where the hot side and cold side dies are stacked upon one another with a suitable isolation component between.

Communicating digital data between isolated sides of an isolated ADC circuit can present a considerable challenge. In some examples, an ADC on the hot side of an isolated ADC circuit itself generates a single-bit stream of digital signal that is unframed, for example from a single bit second order sigma-delta ADC. The single-bit digital signal is transmitted across the isolator to the cold side. There, the single-bit digital signal can be framed using a filter or other suitable filter to generate a multi-bit digital value that can be resampled at an appropriate rate. In this way, the single-bit digital signal is transmitted without a corresponding clock or synchronization signal but a higher resolution lower frequency value be recovered.

According to the invention as claimed, an ADC on the hot side generates a multi-bit digital signal (e.g., a <NUM>-bit digital signal) as output. A multi-bit ADC may provide benefits over a single-bit ADC such as, for example, higher resolution, better power efficiency or higher data rate, etc. For example, a multi-bit ADC may achieve higher SNR with a lower oversampling rate and may improve the power efficiency of the isolated ADC circuit For example a second order sigma-delta converter with <NUM>-bit quantizer may be used on the hot side to create a multi-bit digital signal with a word size of <NUM>-bits. If the multi-bit digital signal is filtered and decimated on the hot side to create the desired lower data-rate higher resolution value, then to determine the phase of this decimation a synchronization signal would need to be sent across the barrier from the cold side to the hot side.

A requirement to synchronize the phase of decimation is often needed in electrical measurement systems to guarantee the relative phasing between sampling the different current and voltage channels to determine correctly active and reactive power. Sending a signal across the isolation in the opposite direction to the data often incurs additional cost and complexity. For example, it may require an additional channel of isolation with associated high voltage passive and transmit and receive circuitry. In addition, if during operation there is an electromagnetic interference (EMI) event that causes corruption of this synchronization signal, the effect on the signal integrity could be large, as it may take several periods to recover. Another approach which would keep the filtering and decimation on the cold side would be to use multiple channels of isolation for transmitting the multi-bit digital signal from the hot side to the cold side. This, however, would increase cost, size and power. Another approach would be to frame the multi-bit digital signal with start and stop sequences and send it over a single channel. However, this would require a higher clock speed for the extra start-stop sequences. If there was corruption from an EMI event it could potentially corrupt one of the more significant bits increasing the error.

The previous examples were for oversampling converters, and although these run at a relatively high sampling rate, the latency to get a higher resolution value out of the signal chain is often determined by the filtering and decimation. In many applications low latency is desirable. Consider an energy measurement example including circuit breakers and protective relays. Here, latency may affect the speed at which faults can be detected and remedied.

When a multi-bit ADC is used on the hot side, it may be challenging to send the resulting multi-bit data across the isolator, for example, while maintaining resilience and flexibility in terms of synchronization. The ADC output signal generated by a multi-bit ADC is framed. That is, the ADC output signal includes discrete digital words with each digital word including multiple bits (e.g., <NUM> bits, <NUM> bits, <NUM> bits, etc.). Transmitting the ADC output signal across the isolator involves sending the ADC output signal itself as well as communicating a clock or other synchronization signal that allows a receiving component on the cold side to recreate the digital words of the multi-bit signal. This increases the complexity of the isolator and, in some examples, leads to the inclusion of multiple isolators between the hot and cold sides of the circuit. Sending the synchronization signal at the data rate of the ADC can also decrease efficiency.

Some examples utilize a framing scheme to organize the multi-bit digital signal output by the ADC for transmission across a single channel isolator for transfer to a cold side. A framing scheme, however, may introduce additional overhead. For example, in ADC designs that oversample the analog input, such as delta-sigma ADCs, the ADC data may be at the higher ADC data rate, which may not be power efficient.

Further, when data is transmitted across an isolator, framed and/or synchronized arrangements can be vulnerable to interference or other sources of noise. Isolators, in some examples, are susceptible to noise caused by Electromagnetic interference (EMI) and/or other factors. A multi-bit signal transmitted across an isolator may be more vulnerable to noise at the isolator. For example, a single bit flip in a multi-bit digital signal can change the value of a digital word by as much as <NUM>%. Further, in a framing scheme, corruption of just a few bits can lead to several frames lost data.

A multi-bit ADC on the hot side of an isolated ADC circuit may include a digital modulator on the hot side. The digital modulator converts the ADC output signal generated by the ADC to a single-bit stream that may be unframed. The single-bit stream includes a series of logic <NUM>'s and <NUM>'s where the value of the single-bit stream is given by proportion of <NUM>'s and <NUM>'s. The single-bit stream is transmitted across the isolator to the cold side of the isolated ADC circuit. A filter on the cold side combines the received single-bit stream to generate a reconstructed ADC output signal. In this way, the ADC output signal generated by the multi-bit ADC is transmitted across the isolator, for example, without the need to also transmit a clock signal or other synchronization information.

The reconstructed ADC output signal may be at a higher resolution than the ADC output signal. In some examples, the reconstructed ADC output signal is decimated to the desired output frequency and synchronized to be at the desired phase needed at the output of the isolated ADC circuit. Also as each bit in the single-bit bitstream from the digital modulator has equal weighting and because of the high data rate, any corruption of a single bit only has minimal impact on the subsequent SNR and does not affect the resynchronization. In this way the above system may benefit from the superior ADC characteristics of SNR or power efficiency or bandwidth of a multi-bit ADC while benefiting from the efficiency and resilience and synchronization flexibility of a single-bit converter with minimal additional latency.

In some examples, it is desirable to communicate other information from the hot side to the cold side of an isolated ADC circuit. For example, the ADC may generate status and/or control information that is desirable to process on the cold side or transmit to other components from the cold side. Various examples herein also describe systems and methods for modulating additional data onto a signal transmitted across the isolator. For example, a digital data signal may be amplitude modulated onto a carrier signal to generate a modulated data signal. A carrier frequency of the carrier signal is higher than and, in some examples, much higher than the frequency of the ADC output signal transmitted across the isolator. For example, the carrier frequency may be at about the <NUM>th harmonic of the frequency of the ADC output signal, well beyond the frequency of interest and in the frequency range that will normally be filtered out. The modulated data signal is embedded (e.g., additively) to the ADC output signal and transmitted across the isolator.

<FIG> is a diagram showing one example of an isolated ADC circuit <NUM>. The isolated ADC circuit <NUM> includes a hot side <NUM> and a cold side <NUM> separated by an isolator <NUM>. The hot side <NUM> and cold side <NUM> are galvanically isolated from one another. In some examples, the hot side <NUM> and cold side <NUM> are implemented on separate dies. For example, the hot side <NUM> may be implemented on a first die and the cold side <NUM> may be implemented on a second die. The first and second dies may be included in a common integrated circuit package, for example, according to a stacked die structure. In other examples, the first and second dies are included in separate integrated circuit packages.

The hot side <NUM> includes an ADC <NUM> and a digital modulator <NUM>. The ADC <NUM> may be of any suitable type. In some examples, the ADC <NUM> includes a multi-bit second order sigma-delta ADC. Also, in some examples, the ADC <NUM> includes a multi-bit Successive Approximation Register (SAR) ADC, or any other suitable multi-bit ADC. The ADC <NUM> converts an analog signal <NUM> to a multi-bit ADC output signal <NUM>. The analog signal <NUM> may originate from any suitable source. In some examples, the hot side <NUM> also includes one or more sensors <NUM>. The sensor <NUM>, for example, may sense current, voltage, temperature, or another suitable value on the first side of the circuit. In some examples, the sensor <NUM> measures current or voltage at a power transmission line or other high-voltage application.

The ADC output signal <NUM> is provided to the digital modulator <NUM> on the hot side <NUM>. In some examples, the ADC output signal <NUM> is filtered before being provided to the digital modulator. A low-pass filter may be used to remove part of the high frequency spectrum of the ADC to remove high frequency artifacts of the ADC conversion process. The digital modulator <NUM> converts that ADC output signal <NUM> to a single-bit stream <NUM>. This removes framing data. For example, the ADC output signal <NUM> comprises discrete digital words. On the other hand, the single-bit stream <NUM> includes a stream of logic <NUM>'s and <NUM>'s where the value is conveyed by the proportion of the time that the stream <NUM> has a particular logic value. In some examples, converting the ADC output signal <NUM> to a single-bit stream <NUM> includes modifying the data rate. For example, the single-bit stream <NUM> may have a data rate higher than a data rate of the ADC output signal. In some examples, a data rate increase at the digital modulator <NUM> is proportional to the number of bits in the ADC output signal <NUM>. For example, if the ADC output signal <NUM> includes <NUM>-bit words, the data rate of the single-bit stream <NUM> may be four time higher than a data rate of the ADC output signal <NUM>. In some examples the modulator may reduce the net data rate if the ADC <NUM> is sampling at a higher rate than is needed for the frequencies of interest, for example to improve the anti-aliasing of the system.

The digital modulator <NUM> may be of any suitable type. In some examples, the digital modulator <NUM> includes a sigma-delta modulator. In some examples, such as examples where the ADC is a sigma-delta ADC, the ADC <NUM> itself may include a n analog modulator. The digital modulator <NUM> may therefore be in addition to the analog modulator, if any, that is part of the ADC <NUM>. The digital modulator <NUM> acts on the ADC output signal <NUM> generated by the ADC <NUM>.

The single-bit stream <NUM> is transmitted across the isolator <NUM> to the cold side <NUM>. The isolator <NUM> may be or include any suitable type of isolator device such as, for example, one or more transformers or other inductive isolator devices, one or more capacitors or other capacitive isolator devices, one or more optical isolators, etc. At the cold side <NUM>, the single-bit stream <NUM> is provided to a filter <NUM>. At the cold side <NUM> (e.g., after being transmitted across the isolator <NUM>, the single-bit stream <NUM> may be referenced to a ground of the cold side <NUM>.

The filter <NUM> average the single-bit stream <NUM> to generate a reconstructed ADC output signal <NUM>. The reconstructed ADC output signal <NUM> is a reconstruction on the cold side <NUM> of the original multi-bit signal <NUM> generated by the ADC <NUM>. The reconstructed ADC output signal <NUM> may have words of any suitable length (e.g., in bits). In some examples, the reconstructed ADC output signal <NUM> has words of the same length as the words of the ADC output signal <NUM>. In other examples, the word length of the reconstructed ADC output signal <NUM> may be different than that of the ADC output signal <NUM>. The data rate of the reconstructed ADC output signal <NUM> may be lower than the data rate of the single-bit stream <NUM>, for example, by a factor related to the word length of the reconstructed ADC output signal <NUM> and the order and frequency of operation of the digital modulators.

The filter <NUM>, for example, may comprise one or more digital filters, one or more digital integrators, etc. For example, the filter <NUM> may include a digital sinc filter, a progressive cascaded integrator-comb (CIC) filter, or any other suitable filter. The filter <NUM> may also receive a synchronization signal <NUM>. For example, the synchronization signal <NUM> may be a clock signal used by one or more digital filters implemented by the filter <NUM>. In some examples, the synchronization signal <NUM> is generated by another component, such as the interface or processing circuit <NUM> circuit, and provided to the filter <NUM>. The reconstructed ADC output signal <NUM> and synchronization signal <NUM> are provided to and by an interface/processing circuit <NUM>. The interface/processing circuit <NUM> may process the reconstructed ADC output signal <NUM> and/or transmit it to a remote circuit or device for processing. For example, when the reconstructed ADC output signal <NUM> represents a sensor output, the interface/processing circuit <NUM> (or other remote circuit or device) may process the reconstructed ADC output signal <NUM> to calculate frequency components, calculate averages, combine with other data, be scaled, detect errors, record values, etc..

Although one filter <NUM> is shown in <FIG>, some examples may include multiple filters on the cold side <NUM>. For example, a first filter may have a relatively low latency and a relatively low precision. The second filter may have a relatively higher latency and relatively higher precision. The high-latency, high-precision filter may be used, for example, for data recordation. The low-latency, low precision filter may be used, for example, to quickly detect error conditions.

<FIG> is a diagram showing another example of an isolated ADC circuit <NUM> including multiple hot sides 102A, 102B 102C. The hot sides 102A, 102B, 102C may be implemented on separate dies from the cold side <NUM> and, in some examples, separate dies from each other. Each hot side 102A, 102B, 102C comprises an optional sensor 126A, 126B, 126C, ADC 108A, 108B, 108C, and digital modulator 110A, 110B, 110C. In the isolated ADC circuit <NUM>, the respective hot sides 102A, 102B, 102C operate similar to the hot side <NUM> to generate respective single-bit streams 120A, 120B, 120C that are provided across isolators 106A, 106B, 106C to the cold side <NUM>. For example, the ADCs 108A, 108B, 108C receive respective analog signals 117A, 117B, 117C. Analog signals 117A, 117B, 117C may be received from optional sensors 126A, 126B, 126C. The ADCs <NUM> convert the analog signals 117A, 117B, 117C to respective ADC output signals 118A, 118B, 118C that are provided to respective modulators 110A, 110B, 110C. Modulators 110A, 110B, 110C convert the respective ADC output signals 118A, 118B, 118C to respective single-bit streams 120A, 120B, 120C that are transmitted across respective isolators 106A, 106B, 106C to the cold side <NUM>.

The cold side <NUM> includes respective filters 114A, 114B, 114C that convert the respective multi-bit signals 120A, 120B, 120N to respective reconstructed ADC output signals 124A, 124B, 124C using synchronization signals 127A, 127B, 127C. Three synchronization signals 127A, 127B, 127C are shown in <FIG>. In some examples, this allows for the insertion of different phase delay between the different channels, for example to cancel phase errors in the sensor analog part on each channel. Also, in some examples, two or more of the quantizers 114A, 114B, 114C operate using the same synchronization signal.

An arrangement such as the example of <FIG> with three hot sides 102A, 102B, 102C may be used, in some examples, for implementations that monitor a device or transmission line using or transporting a three-phase signal. In a multiphase system there may be more than one hot side for each cold side. In the example of <FIG>, there are three hot sides 102A, 102B, 102C to one common cold-side <NUM> at the neutral (e.g., one hot side at each of the <NUM> phases). Also, although three hot sides 102A, 102B, 102C are shown, arrangements with any suitable number of hot sides may be used in some examples.

<FIG> is a diagram showing one example of an isolated ADC circuit <NUM> that is configured to transmit a modulated data signal embedded with the ADC output across the isolator <NUM>. Similar to the isolated ADC circuits <NUM>, <NUM>, the isolated ADC circuit <NUM> includes a hot side <NUM> and a cold side <NUM> separated by an isolator <NUM>.

In the example of <FIG>, the hot side <NUM> includes an ADC <NUM> that converts an analog signal <NUM> to an ADC output signal <NUM>. The ADC output signal <NUM> is multi-bit, similar to the ADC output signals <NUM>, 118A, 118B, 118C. The hot side <NUM> also includes a digital data signal <NUM>. The digital data signal <NUM> includes digital data generated on the hot side <NUM> that is to be transmitted to the cold side <NUM>. For example, the digital data signal <NUM> may include register values from the optional sensor <NUM>, control data generated by the ADC <NUM>, or any other suitable data.

The digital data signal is modulated onto a carrier signal <NUM> at modulator <NUM> to generate a modulated data signal <NUM>. The carrier signal <NUM> has a carrier frequency that may be higher than a threshold harmonic of the data rate of the ADC output signal <NUM>. For example, the band of interest of the ADC maybe up to the <NUM>th harmonic and the carrier frequency may be higher than the <NUM>th harmonic of the data rate of the ADC output <NUM>. In this way, adding the modulated data signal <NUM> is out-of-band relative to the ADC output <NUM>. Accordingly, adding the modulated data signal <NUM> to the ADC output signal <NUM> may result in a small reduction in the signal-to-noise (SNR) ratio in-band.

The modulated data signal <NUM> is additively embedded on the ADC output <NUM> at adder <NUM>, resulting in an embedded ADC output signal <NUM>. The embedded ADC output signal <NUM> is transmitted across the isolator <NUM> to the cold side The isolated ADC circuit <NUM> converts a ADC output signal from the ADC <NUM> to a single-bit stream prior to transmission across the isolator <NUM>, as shown in <FIG> and <FIG>. In other examples, not according to the invention as claimed, the embedded ADC output signal <NUM> is a multi-bit signal and synchronization data is transmitted with the embedded ADC output signal <NUM> and/or reconstructed on the cold side <NUM>.

On the cold side, the embedded ADC output signal <NUM> is received by an interface/processing circuit <NUM> that may process and/or transmit the embedded ADC output signal <NUM> to another device for processing. In some examples, the interface/processing circuit <NUM>, or other suitable component, applies low-pass filtering to the embedded ADC output signal <NUM> to remove the embedded modulated data signal <NUM> prior to processing or transfer to another device for processing.

The embedded ADC output signal <NUM> is also provided to a bandpass filter <NUM>. The bandpass filter <NUM> may have a passband centered on the carrier frequency of the carrier signal <NUM>. A filtered signal <NUM> may include frequency content from the embedded ADC output signal <NUM> including the modulated data signal <NUM>. A data detection circuit <NUM> may demodulate the filtered signal <NUM> to generate a reconstructed data signal <NUM>. The reconstructed data signal <NUM>, in some examples, is provided to the interface/processing circuit <NUM>. In some examples, the data detection circuit <NUM> utilizes a peak detect mechanism, an angle tracking mechanism or a combination of both approaches.

<FIG> is a diagram showing one example of an isolated ADC circuit <NUM> for embedding a data signal and transmitting a single-bit data stream over an isolator <NUM>. For example, the isolated ADC circuit <NUM> includes features of both the isolated ADC circuit <NUM> of <FIG> and the isolated ADC circuit <NUM> of <FIG>. The isolated ADC circuit <NUM> includes a hot side <NUM> and a cold side <NUM> separated by an isolator <NUM>. The hot side <NUM>, cold side <NUM>, and isolator <NUM> may be implemented, for example, as described herein with respect to other hot sides, cold sides, and isolators.

The hot side <NUM> includes an ADC <NUM>. The ADC <NUM> is a multi-bit ADC that converts an analog signal to a multi-bit ADC output signal. The ADC <NUM>, in some examples, includes a multi-bit, <NUM>nd order sigma-delta ADC, a SAR ADC, or other suitable ADC. In the example of <FIG>, the ADC output signal generated by the ADC <NUM> includes words with a <NUM>-bit word length. The ADC output signal may include, for example, quantizer data from the flash converter in the modulator, data (e.g., <NUM>-bit data) from an analog sigma delta converter, etc..

The example isolated ADC circuit <NUM> of <FIG> includes optional components <NUM>, <NUM> for decimating the ADC output signal on the hot side <NUM>. Decimating on the hot side <NUM> (e.g., before data is transferred to the cold side <NUM>) is desirable in some uses, but not in others. For example, decimating on the hot side <NUM>, may introduce additional latencies into the circuit <NUM> that make the hot side decimation unsuitable for some applications. In other examples, the ADC output signal is transferred from the hot side <NUM> to the cold side <NUM> without having first been decimated. In the example of <FIG>, decimation is performed by a CIC filter <NUM>, which may act as a decimator. The CIC filter <NUM> receives the ADC output signal and generates a decimated ADC output signal, which may be multi-bit. Decimating the ADC output signal, in some examples, reduces its data rate and may also, in some examples, increases its word length. In the example of <FIG>, the CIC filter <NUM> reduces the data rate of the ADC output by half, but also doubles the word length from <NUM>-bits to <NUM>-bits.

As described, decimation of the ADC output signal may be desirable in some implementations but not in others. For example, use of limited or no decimation may decrease latency, which may be important for some applications. Accordingly, in the example of <FIG>, both the ADC output signal and the decimated ADC output signal are provided to a multiplexer <NUM>. A decimation bypass input is provided to the multiplexer <NUM>. At its output, the multiplexer <NUM> provides the ADC output signal or the decimated ADC output signal depending on the state of the decimation bypass signal. An optional multiplier <NUM> multiplies the output of the multiplexer <NUM> by a gain given by α. This can be to equalize the data depending on the path it took, or to maximize the dynamic going into the digital modulator <NUM>.

The example isolated ADC circuit <NUM> of <FIG> also includes components for embedding a digital data signal for transmission across the isolator. The embedding may be done by modulating the digital data signal to a high frequency carrier having a carrier frequency greater than a threshold harmonic of the data rate of the ADC output (e.g., the <NUM>th harmonic). In some examples, the digital data signal may be very slowly varying, may not have high frequency components. Accordingly, the digital data signal may be safely modulated on the carrier frequency, which is at a higher frequency. If the digital data signal is chattering, it may be filtered prior to modulation. Pre-modulation filtering may require additional area on the hot die and may also reduce latency performance, but this may be acceptable for some cases.

In the example of <FIG>, the digital data signal originates from the ADC <NUM> and may include, for example, control data from the ADC <NUM> such as, for example, the state of a control register of the ADC <NUM>, etc. In the example of <FIG>, the digital data signal has a <NUM>-bit word length. The digital data signal is modulated onto a carrier signal at a modulator <NUM>. The carrier signal may have a carrier signal frequency that is higher than the data rate of the ADC output signal, and in some examples, much higher. For example, the carrier signal may have a carrier signal frequency that is at or above a threshold harmonic of the data rate of the ADC output such as, for example, above the <NUM>th harmonic. In some examples, the carrier is selected to permit multiple harmonics of the carrier tone to be used to send more bits with varying dynamic range of control code. The carrier signal may be low energy. For example, the energy of the carrier signal may be <NUM> dB or more lower than the energy of the ADC output signal. In some examples, the energy of the carrier signal is lower than the energy of the ADC output signal by <NUM> dB or more, <NUM> dB or more, etc..

A sine wave look-up table (LUT) <NUM> is used, in this example, to produce the carrier signal. The LUT <NUM>, in some examples, is accessed at the decimation rate of the CIC filter <NUM>, which may be <NUM>. In this example, the carrier signal has an <NUM>-bit word length. The modulated data signal generated by the combination of the <NUM>-bit digital data signal and the <NUM>-bit carrier signal has a <NUM>-bit word length. The bandwidth of the modulated data signal, in this example, is <NUM>.

The modulated data signal is additively combined with the output of the amplifier <NUM> at adder <NUM>. Embedding of the control data in an additive manner, as described herein, may cause a small to negligible degradation the signal-to-noise ratio (SNR) in-band, but may also cause a slight loss in dynamic range of the ADC data. For example, the modulated data signal may have a suitably small bandwidth (<NUM> in this example), and be positioned above the threshold harmonic to reduce its contribution to the SNR. Also, in some examples, the embedding of the control may be strategically placed, as described herein, such that suitable (e.g., maximum) code swing is achieved with clean detection under noisy scenarios.

The output of the adder <NUM> is provided to the digital modulator <NUM>. In the example of <FIG>, the digital modulator <NUM> includes a sigma-delta modulator. In various examples, the digital modulator <NUM> includes an all-digital cascade of integrator feedback (CIFF) dual data rate (DDR) modulator. Also, in some examples, the digital modulator <NUM> comprises a topology cascade of integrators with dual resonator feedback. In some examples, the arrangement may be a fifth-order arrangement, as described herein. Also, in some examples, the digital modulator provides higher-order noise shaping as described herein.

The output of the digital modulator <NUM> is the single-bit stream, which is transmitted across the isolator <NUM> to the cold side. The single-bit stream, as described herein, may not use a framing synchronization scheme with its attendant disadvantages.

On the cold side <NUM>, the single-bit stream is provided to a filter <NUM>. In the example of <FIG>, the filter <NUM> includes a progressive CIC filter. The filter <NUM> converts the single-bit stream to a reconstructed multi-bit signal that represents the output of the ADC <NUM>. An amplifier <NUM> may be applied to the reconstructed multi-bit signal. The gain of the amplifier (<NUM>/α) may be the inverse of the gain of the amplifier <NUM>. The reconstructed multi-bit signal, in the example of <FIG>, is provided to a front end digital signal processor (DSP) <NUM> for processing. In some examples, a communication interface may be included in addition to or instead of the front-end DSP <NUM> to transmit the reconstructed multi-bit digital signal to another component for processing.

The single-bit stream is also provided to a band pass filter <NUM> and data detection circuit <NUM> to extract the digital data signal embedded on the hot side <NUM>. The band pass filter <NUM> is centered on the carrier frequency and may have a passband that is equivalent to the bandwidth of the modulated data signal generated by the hot-side modulator <NUM>. In this example, the pass band of the band pass filter <NUM> may be about <NUM>. An output of the bandpass filter <NUM> is passed to the data detection circuit <NUM>, which may detect the original digital data signal by extracting the digital data signal from the combination of the carrier signal and the digital data signal.

In various examples, electrostatic discharge (ESD) and/or interference of high frequency components cause errors that can translate into bit errors. These errors can be of periodic nature or random nature with multiple bits being corrupted. Various examples described herein have acceptable loss in SNR for when the errors occur with no frequency deviation of the fundamental. On the control side the occurrence of errors should not cause significant (or any) corruption of the digital data signal embedded on the ADC output. For example, in some examples, the detection circuitry clean retrieves the digital data signal without loss in latency. When the errors go away, the SNR numbers may come back to normal. In some examples, the one-bit scheme described herein has no framing and, therefore, a corruption may never lead to a loss of multiple frames of data.

In some examples, embedding the digital data signal as described may raise the noise floor temporarily. This mechanism may make the receiver side cleanly detect the digital data signal without having to make decisions about the framing synchronization. Since the scheme employed is amplitude modulation the digital data signal can be recovered by either a peak detect mechanism or angle tracking mechanism or a combination of both.

<FIG> is a diagram showing one example of a digital modulator <NUM> that may be used to implement any of the digital modulators described herein. The example digital modulator circuit <NUM> is a sigma-delta modulator with cascaded integrator feedback. For example, the sigma-delta modulator may be implemented utilizing CIFF technology.

An input to the digital modulator <NUM>, given by u(n), is a multi-bit digital signal. In the diagram of <FIG>, the internal math of the digital modulator <NUM> is represented with digital 'analog' variables with appropriate bit width for the required mathematical precision in the form of an appropriate number system, for example floating point or scaled integer, signed or unsigned. The output of the digital modulator <NUM>, given by v(n), is the single-bit stream described herein. The digital modulator <NUM> is a fifth-order modulator including five integrator stages 502A, 502B, 502C, 502D, 502E. The respective integrator stages 502A, 502B, 502C, 502D, 502E sum to the input u(n) and an analog variable version of the output v(n). Effective digital-to-analog converters (DACs) a1, a2, a3, a4, a5 convert the output v(n) to a digital analog variable for the respective integrator stages 502A, 502B, 502C, 502D, 502E. The sum at each stage 502A, 502B, 502C, 502D, 502E is fed into the following integrator, denoted as (<NUM>/z-<NUM>), in the Z-domain transfer function and a stage-specific scaling factor c1, c2, c3, c4, c5 is applied. Integrator stages 502B and 502D add a feedback from the next integrator stages 502C and 502E, respectively. An optional dither stage <NUM> may be used to whiten the noise floor. The output of the integrator stages 502A, 502B, 502C, 502D, 502E and optional dither stage <NUM> is provided to a comparator <NUM> which generates the single-bit stream output v(n).

The digital modulator <NUM> may be optimized using iterative techniques to reduce integrator width. The resonator portions of the modulator may provide better performance with tradeoff of higher digital area. In some examples, optional resonators are used to create nulls in the noise band, which may result in better SNR parametric numbers.

<FIG> is a diagram showing one example of an integrator stage <NUM> including saturation logic. The integrator stage <NUM>, for example, may be used to implement one or more of the integrator stages 502A, 502B, 502C, 502D, 502E of <FIG>. The integrator stage <NUM> may be suitable for use in digital modulators that implement a CIFF scheme, as described herein.

In the integrator stage <NUM>, a previous integrator output is summed with an output of a DAC <NUM> at summer <NUM>. The modulator output v(n) controls the DAC <NUM>. If the modulator output v(n) is high, the DAC <NUM> returns -ai. If the modulator output v(n) is low, the DAC <NUM> returns ai. A clipping stage <NUM> is configured to change the integrator stage output if the output of the summer <NUM> clips. To optimize the bit widths of the integrators, some examples may include analyzing the registered value of the output of the summer <NUM> to see how close it is to clip whether the signal overflow. Clipping points may be calculated and set as pre-set thresholds to avoid this condition from happening. In some examples, the clipping preset thresholds are built using hardwired logic. The block shown as T is a part selector as, in some examples, the entire bit-width does not need to be compared and comparing a section will suffice. When the summing signal is out-of-bounds with respect to the thresholds the integrator is held in saturation. This may have the effect of order reduction as no integration of the feedback is taking place. In some examples, truncation or rounding as shown in <FIG> is performed at the third integrator stage 502C, fourth integrator stage 502D, and fifth integrator stage 502E and not at the first two integrator stages 502A, 502B.

As described herein, the digital modulator increases the data rate of the single-bit stream relative to the data rate of the multi-bit signal input, for example, by oversampling at an over sampling rate (OSR). In some examples, the OSR of the modulator may be increased, for example, with signal transfer between hot side and cold side at a dual data rate (DDR). In some examples, such as when the ADC is a SAR ADC, a first clock, such as a <NUM> clock, may be input to the hot side. Using standard cells, a second, higher-frequency clock, a <NUM> clock is created and used to clock the hot side digital modulator. The OSR may be <NUM> for an example case where the first clock is at <NUM> and the second clock is at <NUM>. In some examples, such as some examples where a SAR ADC is used, 16x oversampling or better may yield no SNR degradation. The data may be transmitted using <NUM>-bit lanes, which, in some examples, each have a bandwidth of <NUM> Mb/sec. On the receiver side, which is the cold side, the <NUM>-bit lanes may be recovered back to <NUM> bits at <NUM>.

State elements may be employed to implement the dual data rate. For example, <FIG> is a diagram showing an example circuit <NUM> including elements for increasing the OSR of the digital modulator. In <FIG>, the single-bit stream output by the digital modulator is provided to two flip-flops <NUM>, <NUM>. The flip-flop <NUM> receives a clock signal (clk) used by the ADC. The flip-flop <NUM> receives a complement of the clock signal. The outputs of the flip-flops <NUM>, <NUM> are provided to a multiplexer <NUM>. The output of the multiplexer is the over-sampled single-bit stream. The output of the multiplexer <NUM> is, alternatively, output of the flip-flop <NUM> or the output of the flip-flop <NUM>, switching on transitions of the clock signal.

<FIG> is a timing diagram <NUM> showing one example diagram of a clock signal <NUM> and a data signal <NUM> showing increased OSR using the arrangement of <FIG>. As shown, the data signal <NUM> is sampled on both the rising and the falling edges of the clock signal <NUM>. The multiplexer <NUM> may be used to select between clocking on the positive edge of the clock signal, the negative edge of the clock signal, or both.

The example isolated ADC circuit of <FIG> was analyzed for interference, which can cause glitches in digital data line or clock. Glitches may result in bursty interference errors. The analysis was performed by varying the burst size from <NUM> to <NUM>. <FIG> is a plot <NUM> showing bit errors versus signal to noise ratio for a single burst, with bit errors indicated on a logarithmic scale. <FIG> is a plot <NUM> showing bit errors versus signal to noise ratio for a single burst on a linear scale. <FIG> is a plot <NUM> showing bit errors versus signal to noise ratio for a dual burst on a linear scale. The plots <NUM>, <NUM>, <NUM> were generated by simulating the isolated ADC circuit <NUM> of <FIG> utilizing Matlab by MathWorks, Inc. The plots of <FIG>, <FIG>, and <FIG> indicate that SNR performance of the digital modulator may stay better than <NUM> dB for a <NUM> test of <NUM> bursts, or about <NUM> burst events. In the case of dual burst errors, the SNR degradation happened quickly. However, the frequency component of the line signal had little to no amplitude or frequency degradation, where degradation is shown by a decrease in signal to noise ratio.

Errors may also be due to corruption (e.g., from a bit being flipped). The example isolated ADC circuit of <FIG> was analyzed for flipping of bits from <NUM> to <NUM>. <FIG> is a plot <NUM> showing bit errors versus signal SNR for a single bit flip error. <FIG> is a plot <NUM> showing bit errors versus signal SNR for two bit flip errors. The plots <NUM> and <NUM> were also generated utilizing a simulation in Matlab, by MathWorks, Inc. , of the isolated ADC circuit <NUM> of <FIG>.

In the analysis, the interval of flip was kept at <NUM> (e.g., one bit was flipped at the given interval of <NUM>). This implies <NUM> corruption on a <NUM> DDR stream. It is interesting to note that in the case of data errors this analysis shows almost no variance to the SNR degradation and more bit errors provide a constant degradation. The analyzed example may be tolerable to about <NUM> bit error, after which the degradation seems rapid until about <NUM> bit errors. Following that degradation appears to be constant. It is interesting to note the fundamental frequency component is never lost and can easily be recovered by the CIC/SINC filter. The system is robust in that the line frequency component has no amplitude and frequency degradation or error and bit errors contribute to higher noise floors.

Corruption or bit flip errors may occur with varying repeatability. The example isolated ADC circuit of <FIG> was also analyzed for flip errors with repeatability set to different bit intervals. <FIG> is a chart <NUM> showing plots of bit errors versus SNR for bit errors with repeatability set to <NUM>,<NUM>; <NUM>,<NUM>; and <NUM>,<NUM> bit intervals. In all analyzed cases there was no frequency deviation or amplitude deviation. Noise Distortion was observed to go down as the interval of the flip error increase. The plot <NUM> also shows results of a simulation of the isolated ADC circuit <NUM> of <FIG> made utilizing Matlab, by MathWorks, Inc. As illustrated in <FIG>, the example isolated ADC circuit of <FIG> was analyzed for flip, insertion, and lost bit errors. <FIG> is a plot <NUM> showing flip and insertion corruptions at <NUM> spikes per burst up to <NUM> spikes per burst. A curve <NUM> shows flip corruptions and a curve <NUM> shows insertion corruptions. For example, the <NUM> EFT specification indicates that analysis should be done for <NUM> spikes per burst. The plot <NUM> also shows results of a simulation of the isolated ADC circuit <NUM> of <FIG> utilizing Matlab by MathWorks, Inc.

<FIG> is a diagram showing another example of an isolated ADC circuit <NUM>. The isolated ADC circuit <NUM> may be similar to the isolated ADC circuit <NUM> of <FIG>. The isolated ADC circuit <NUM> utilizes multiple carriers to send redundant digital data signals. This may combat narrowband interference, for example, at the isolator. In the isolated ADC circuit <NUM>, the digital data signal is modulated onto three different carrier signals at three different carrier frequencies. The three carrier frequencies may be at integer multiples of the bandwidth, in this example, <NUM>. Three modulators 454A, 454B, 454C modulate the digital data signal onto the three respective carrier frequencies to generate three respective modulated digital data signals, which are additively embedded to the ADC output at adder <NUM> as described herein.

In the case of EFT events, there may be narrow band corruption at a single carrier frequency. Sending identical digital data over multiple carriers is redundant. This redundancy may be exploited in the receiving control decision circuitry. For example, the single-bit stream at the cold side <NUM> may be provided to three band pass filters 464A, 464B, 464C having a pass band of about the signal bandwidth and centered at the respective carrier frequencies. Peak detection circuits 470A, 470B, 470C extract the digital signal from the respective carrier signals and provide outputs to a control decision circuit <NUM>. The control decision circuit <NUM> may take peak signals from the three different peak detectors 470A, 470B, 470C and perform a decision, for example, based on two out of the three paths conforming to codes in bounded regions. In the case of narrowband interference, the isolated ADC circuit <NUM> may allow for corruption in a <NUM> bandwidth centered on any one of the three carriers. One of the tradeoff s of this scheme is reduced dynamic range for the digital data signal bits. Assuming we start with an information budget for the ADC output and the digital data signal, it may not be advantageous to trade off dynamic range of the ADC output for robust embedded digital data. Instead, in some examples, it may be better to reduce the dynamic range for control and spread it over three carriers for robustness during narrow band interference. If a scheme is so desired where ADC output range is traded for excess embedded digital data signal robustness by putting the control on multiple carrier the isolated ADC circuit <NUM> of <FIG>.

In some examples, clocking on the hot side <NUM> may include various clocks derived from a base clock, which may be at <NUM>. In some examples, the progressive CIC filter <NUM> operates off a <NUM> clock. On the cold side <NUM>, the decimation of the signal path may continue with further SINC decimation (e.g., up to <NUM>) followed by optional Biquad decimation (e.g., up to <NUM>). In some examples, these functions are performed by the frontend DSP <NUM>. TABLE <NUM> below shows example clock rates for different components of the arrangements described herein.

In some examples, the digital data signal is embedded with multiples on a single carrier, for example, as shown and described with respect to <FIG> and <FIG> above. In these examples, peak detection is used after band pass filtering to demodulate the digital data signal from the carrier signal. In these examples, the bandpass filter may recover the modulated data signal quickly, but the peak detector may be slower to converge, increasing the latency of the embedded digital data.

In other examples, a different carrier may be used for each bit to implement a fast path recovery process. <FIG> is a diagram showing another example of an isolated ADC circuit <NUM> implementing a fast path recovery scheme. In the example of <FIG>, the digital data signal has a <NUM>-bit word length. Seven modulators 454A, 454B, 454N are used to modulate each bit of the word onto a distinct carrier signal. This generates seven modulated data signals that are additively embedded to the ADC output at adder <NUM>. The carrier frequencies of the carrier signals may be integer multiples of the bandwidth, in this example, <NUM>. In the example of <FIG>, the digital data signal is put on <NUM> and six harmonics thereof.

On the cold side <NUM>, a distinct bandpass filter 464A, 464B, 464N is provided for each of the modulated data signals. Because only a single bit is modulated on each modulated data signal, the individual bits of the digital data signal words can be recovered at a data detection circuit <NUM>. The data detection circuit <NUM> may detect the individual bits modulated onto the respective carrier frequencies utilizing a binary detect algorithm. Accordingly, the digital data signal can be reconstructed quickly without the need to wait for a peak detection circuit to converge. For example, the data detection circuit <NUM> may include a digital filter that provides a moving average of the bit rate. On the other hand, a peak detector may need to recover a wide word value and average over time. The digital data signal recovery of the arrangement of <FIG> may be robust, although the tradeoff is higher digital area for the additional modulators and band pass filters.

<FIG> is a diagram showing another example isolated ADC circuit <NUM> implementing a fast path recovery scheme and a slow path recovery scheme. At the hot side <NUM>, the digital data signal has a <NUM>-bit word length. Words of the digital data signal are split. A <NUM>-bit nibble is modulated onto a first carrier signal at modulator 454A. The additional bits of each word are individually modulated onto additional carrier signals at additional modulators 454B, 454N (e.g., one bit per carrier signal). The result may be a <NUM>-bit modulated data signal resulting from the modulator 454A and <NUM>-bit modulated data signals resulting from the other modulators 454B, 454N. (The nine bits including one bit from the digital data signal and the <NUM>-bits from the carrier. ) The carrier frequencies of the carrier signals may be integer multiples of the bandwidth, in this example, <NUM>. In the example of <FIG>, the digital data signal is at <NUM> and six harmonics thereof. Also, the word length of the digital data signal may vary as well as the combinations of nibbles and bits modulated onto individual signals.

On the cold side <NUM>, each modulated data signal may have a corresponding band pass filter 464A, 464B, 464N. A peak detection circuit <NUM> demodulates the multiple bits modulated onto the first carrier signal. The remaining bits are decoded by a data detection circuit <NUM>. The binary detection circuit <NUM> may decode bits by making a binary decision if the band pass filtered signal has sufficient signal strength. In this example, the peak detection circuit <NUM> may converge more slowly than the data detection circuit <NUM>, meaning that the latency for <NUM>-bit nibble modulated onto the first carrier signal is higher than the latency of the remaining bits modulated onto distinct carrier signals. For example, the portion of the digital data signal modulated onto the first carrier signal, and detected using the peak detection circuit, may be data, such as status bits, that are expected to vary slowly.

<FIG> include respective plots <NUM>, <NUM>, <NUM> showing fast Fourier transforms (FFTs) of data transmitted in the isolated ADC circuit <NUM> of <FIG> with fast and slow control at lower carrier and fast control at integer multiples of fast carrier over DDR. The plot <NUM> of <FIG> shows compliance at <NUM> spikes per burst. The plot <NUM> of <FIG> shows compliance at <NUM> spikes per burst. The plot <NUM> of <FIG> shows compliance at <NUM> spikes per burst. For example, the noise floor of the system rises as the number of spikes per burst increases.

<FIG> is a diagram showing another example isolated ADC circuit <NUM>. The isolated ADC circuit <NUM> also partitions the digital data signal on the hot side into fast and slow processing lanes with multiple carrier signals, similar to the isolated ADC circuit <NUM>. The isolated ADC circuit <NUM> is configured to send the embedded digital data signal in a format including a preamble and packets. For example, in a packet mode configuration, a preamble signifies the start of packet. This preamble is a detect of <NUM> that is the presence of a carrier. Subsequent tones are part of the digital data that can be packetized. The packet construction can be accomplished by using available dynamic range of the carrier tone and also using the next dynamic range of the next tone. Since the noise power of the modulator rises with frequency the information per carrier will go down as the integer multiple rises. In the case above using six carrier tones a total of <NUM> + <NUM> + <NUM> + <NUM> + <NUM> + <NUM> = <NUM> bits can be sent. If the recovery is done at <NUM> with <NUM> samples of convergence time it implies that <NUM>*<NUM>/<NUM> = <NUM> Kbits per second can be sent using this scheme. This method operates at low efficiency of entropy as for an oversampled system of clock frequency <NUM> with Nyquist frequency being <NUM>. The usable spectral band above the <NUM>th harmonic being <NUM> to <NUM> being <NUM> the amount of control information that can be sent is roughly <NUM> Kbps/<NUM> Kbps implies an efficient of approximately <NUM>%. Higher efficiencies may be achievable by coding of packets using advanced spatial and temporal techniques are employed.

After the signal crosses over the isolation interface it may be input into the CIC filter and in parallel input into the band pass filters 464A, 464B, 464N. The band pass filter 464A, 464B, 464N may be a biquad operating at <NUM>. Once the signal is filtered through the bandpass filters 464A, 464B, 464N it may be converted to absolute value and input into the peak detector. The peak detector operates at <NUM>. The input code may be seven bits and can take values from <NUM> to <NUM>. The biquad filter may keep fraction precision up to <NUM> bits. The resulting number format may be unsigned U7.

<FIG> is a plot <NUM> showing code convergence versus the number of samples using peak detection, as described herein. Noise of up to eight fractional bits may be tolerated on the codes. The peak detector is shown to converge at about <NUM> samples at <NUM>. It is possible to make the peak detector more aggressive with prediction of the peak before convergence and this has to be explored further. The total delay for the slow path will be the convergence time of the peak detector plus the latency of the band pass filter. In the case of the fast path there is no peak detection necessary for a binary decision.

In some examples, the reliability of the propagation of the embedded digital signal from the hot side to the cold side is significant. Several experiments were done where bursty noise was introduced to bring the performance down from <NUM> dB to <NUM> dB by varying the number of spikes per burst. It is noted for the degradation in SNR in the signal fundamental the control code is very reliably decoded provided at least <NUM> fractional bits are employed. In some examples, this architecture recommends having <NUM> as the likelihood of a misdetection will be <NUM> in several million. Analyzing the fractional numbers there appears to be a scaling bias between <NUM> and <NUM>. The bias scales from code <NUM> to code <NUM> and the distance between codes is approximately <NUM>. Comparing Code <NUM> and Code <NUM> it is observed the difference is <NUM> and this is less than <NUM> and is due to the inherent noise in the system. If the bias is reduced then the probability of misdetection would rise closer to the end code <NUM>. If the bias is increased the control code <NUM> when on bits are on could be misdetected to a <NUM>. In the bias selected there is some margin on changing of about + or - <NUM>%.

<FIG> is a diagram showing one example of a LUT-based sinusoid generator <NUM>. For example, the sinusoid generator <NUM> may be used to generate digital carrier signals described for use with the various isolated ADC circuits described herein. The sinusoid generator <NUM> comprises a LUT <NUM>, at LUT address generator <NUM>, and an output waveform generator <NUM>. The sinusoid generator <NUM> may be operable at 1x, 2x, and 4x rates. The sinusoid generator <NUM> may be designed with fixed coefficients using a LUT <NUM> approach. The angle may be <NUM>*π*<NUM>/<NUM>. In some examples, the LUT table has <NUM> points. An odd number of entries may not be ideal, as it makes the optimization using quarter wave a little bit trickier. Using this approach there may be distortion as the LUT <NUM> repeats over a period rather than computing next cycle values. The LUT <NUM> may be optimized to a width of <NUM> bits which includes the sign bit. There is minimum error deviance however the guard band <NUM> between codes is further reduced due to both phase error and finite bit width truncation. The scale factor α on the cold side may be changed slightly to compensate for this error. The area can be optimized using only <NUM> entries rather than <NUM> using quarter wave symmetry. The multiplier on the hot side is 10x7. TABLE <NUM> below gives the recovered codes using <NUM> bit sine wave entries.

TABLE <NUM> shows that a control code of the digital data signal is recovered less accurately as the number of spikes per burst increases and as the code itself is lower.

Geometric terms, such as "parallel", "perpendicular", "round", or "square", are not intended to require absolute mathematical precision, unless the context indicates otherwise. Instead, such geometric terms allow for variations due to manufacturing or equivalent functions. For example, if an element is described as "round" or "generally round," a component that is not precisely circular (e.g., one that is slightly oblong or is a many-sided polygon) is still encompassed by this description.

The term "circuit" can include a dedicated hardware circuit, a general-purpose microprocessor, digital signal processor, or other processor circuit, and may be structurally configured from a general purpose circuit to a specialized circuit such as using firmware or software.

Any one or more of the techniques (e.g., methodologies) discussed herein may be performed on a machine. In various embodiments, the machine may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine may operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine may act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine.

Examples, as described herein, may include, or may operate by, logic or a number of components, or mechanisms. Circuit sets are a collection of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuit set membership may be flexible over time and underlying hardware variability. Circuit sets include members that may, alone or in combination, perform specified operations when operating. In an example, hardware of the circuit set may be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuit set may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a computer readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to encode instructions of the specific operation. In connecting the physical components, the underlying electrical properties of a hardware constituent are changed, for example, from an insulator to a conductor or vice versa. The instructions can enable embedded hardware (e.g., the execution units or a loading mechanism) to create members of the circuit set in hardware via the variable connections to carry out portions of the specific operation when in operation. Accordingly, the computer readable medium is communicatively coupled to the other components of the circuit set member when the device is operating. In an example, any of the physical components may be used in more than one member of more than one circuit set. For example, under operation, execution units may be used in a first circuit of a first circuit set at one point in time and reused by a second circuit in the first circuit set, or by a third circuit in a second circuit set at a different time.

Particular implementations of the systems and methods described herein may involve use of a machine (e.g., computer system) that may include a hardware processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory and a static memory, some or all of which may communicate with each other via an interlink (e.g., bus). The machine may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, the display unit, input device and UI navigation device may be a touch screen display. The machine may additionally include a storage device (e.g., drive unit), a signal generation device (e.g., a speaker), a network interface device, and one or more sensors, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

The storage device may include a machine readable medium on which is stored one or more sets of data structures or instructions (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions may also reside, completely or at least partially, within the main memory, within static memory, or within the hardware processor during execution thereof by the machine. In an example, one or any combination of the hardware processor, the main memory, the static memory, or the storage device may constitute machine readable media.

While the machine readable medium can include a single medium, the term "machine readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions.

The term "machine readable medium" may include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine and that cause the machine to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine readable medium examples may include solid-state memories, and optical and magnetic media. In an example, a massed machine readable medium comprises a machine readable medium with a plurality of particles having invariant (e.g., rest) mass. Accordingly, massed machine-readable media are not transitory propagating signals. Specific examples of massed machine readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

The instructions may further be transmitted or received over a communications network using a transmission medium via the network interface device utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) <NUM> family of standards known as Wi-Fi®, IEEE <NUM> family of standards known as WiMax®), IEEE <NUM>. <NUM> family of standards, peer-to-peer (P2P) networks, among others. In an example, the network interface device may include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communications network. In an example, the network interface device may include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.

Claim 1:
An analog-to-digital conversion method for an isolated analog-to-digital converter circuit (<NUM>) comprising a hot side (<NUM>) and a cold side (<NUM>) separated from the hot side by a first isolator (<NUM>), comprising:
converting a first analog input signal (<NUM>) to a first side multi-bit digital signal (<NUM>) using a first analog-to-digital converter (<NUM>) on the hot side, wherein the first side multi-bit digital signal comprises discrete digital words;
modulating the first side multi-bit digital signal to generate a first single-bit stream (<NUM>) using a first digital modulator (<NUM>) in the hot side, wherein each bit in the first single-bit stream has an equal weighting and a value represented by the first single-bit stream is given by the proportion of <NUM> and <NUM>;
transmitting the first single-bit stream from the hot side to the cold side across the first isolator; and
filtering the first single-bit stream from the first isolator to generate a first reconstructed multi-bit digital signal (<NUM>) using a first filter (<NUM>) on the cold side.