Patent Description:
Today's consumer electronics market frequently demands complex functions requiring very intricate circuitry. Scaling to smaller and smaller fundamental building blocks, e.g. transistors, has enabled the incorporation of even more intricate circuitry on a single die with each progressive generation. Semiconductor packages are used to protect an integrated circuit (IC) chip or die, and provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support larger circuit density.

For example, a trend in semiconductor packages is to move optical interconnects into the package to interface directly with a logic chip for increased data transfer speeds transmitting using light. An optical interconnect may include a photonic die connected to a processor or memory connected to external components through an optical fiber array and corresponding optical connectors or ferrules. One problem is that optical interconnect packages need less than sub-um alignment accuracy to align the optical fibers to the on-chip photonics waveguide. Arrays of the optical fibers need to be assembled simultaneously to achieve high volume assembly, which makes meeting the alignment accuracy requirement a significant challenge for yield. <CIT> relates to a device for passively aligning at least one substrate-carried optical fiber with at least one optical device. <CIT> relates to articles and methods for securing or aligning objects on substrates. <CIT> relates to a method for releasably connecting two groups of optical fibers, and a plug-in connector for carrying out said method.

The extent of the protection conferred is determined by the claims.

Silicon groove architectures and manufacturing processes for passive alignment in photonics modules are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

There is increased need for techniques to integrate fiber connectors with a flip chip package. One or more embodiments described herein are directed to silicon groove architectures and manufacturing processes for passive alignment in photonics die.

To provide context, <FIG> illustrates an example of a silicon groove structure for integrating an optical interconnect or a fiber connector in an optical interconnect semiconductor package. <FIG> illustrates a top view of the optical interconnect package <NUM>, which includes a logic die <NUM> mounted to a polymer substrate <NUM>. The optical interconnect may comprise a photonics die <NUM> mounted on the polymer substrate <NUM> and connected to the logic die <NUM> through the polymer substrate <NUM> and connected to external components through an optical fiber array <NUM> and a corresponding optical connector <NUM> also called a ferrule. The optical interconnect packages <NUM> need less than <NUM> alignment accuracy to align the optical fibers comprising the fiber array <NUM> to the photonics die <NUM>.

<FIG> illustrates a front, close-up view of an edge of photonics die <NUM> showing that existing solutions use a V-groove array <NUM> to guide and align the fiber array <NUM> into the photonics die <NUM>. The V-groove array <NUM> is fabricated by wet non-isotropic etching of silicon comprising a body of the photonics die <NUM>. <FIG> shows that after formation of the V-groove array <NUM>, respective optical fibers in the fiber array <NUM> are inserted into corresponding V-grooves 112A. Typically, each of the optical fibers 108A is <NUM> in diameter. Sidewalls of the V-grooves are etched at certain degree angle. After the optical fibers 108A are inserted, a compressor plate then presses on top of the optical fibers 108A to push the fiber down in the groove so that the center of the optical fiber 108A is aligned with the top surface of the photonics die <NUM>.

Because the non-isotropic etching process for the V-grooves uses the <<NUM>> crystal plane of the silicon as an etch stop, non-isotropic etching cannot be used if the photonics die <NUM> requires multiple optical fibers 108A to be aligned in different directions. The V-grooves are also high stress points that may result in cracking of the photonics die <NUM> after die thinning, and use of a thicker photonics die may limit any use of through-silicon vias (TSV) in the photonics die. Finally, use of wet non-isotropic etching may impose limitations if it is performed after for the photonics die is thinned.

In accordance with the disclosed embodiments, improved groove alignment architectures and manufacturing processes for passive alignment of optical fibers in a photonics die are described. Embodiments disclose groove alignment structures. An etch stop material and a substrate is over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of each of the optical fibers extend above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.

Embodiments disclose novel-shaped groove alignment structures defined by <NUM>-step lithographic etching of silicon and corresponding polymer structures to guide the optical fibers into the grooves for lithographic-based XY alignment accuracy. Such an approach enables the use of thin photonics die and die thickness control accuracy to achieve Z alignment. Use of thin photonics die also enable use of TSV through the photonics die.

<FIG> illustrates an example of a groove alignment structure for integrating an optical interconnect or a fiber connector in an optical interconnect semiconductor package. <FIG> illustrates a top view of the optical interconnect package <NUM>. The optical interconnect package <NUM> includes a logic die <NUM> mounted to a substrate <NUM> (e.g., a polymer substrate) and a photonics die <NUM> mounted on the substrate <NUM> to transmit and receive optical I/O. For example, the photonic die <NUM> may provide a Terabit/s optical physical layer to support high-bandwidth, low-latency connectivity. The photonics die <NUM> may refer to a single die, or may be included in a photonic multi-chip-package with laser and electronic control chips. The photonics die <NUM> may be mounted to the substrate <NUM> through micro-bumps or other contacts and may be connected to the logic die <NUM> through interconnects within the substrate <NUM>. In one embodiment, the photonics die <NUM> may have a body comprising a silicon substrate and the photonics die <NUM> may have a thickness of approximately <NUM>.

In one embodiment, the photonic die <NUM> may be connected to external components (not shown) through a first optical interconnect comprising optical fiber array 208A and optical connector 210A along one side of the photonics die <NUM>, and a second optical interconnect comprising optical fiber array 208B and optical connector 210B along another side of the photonics die <NUM>. Optical fiber arrays 208A and 208B run in two different directions on the photonics die <NUM>. Accordingly, a V-groove array is not suitable to guide and align both of the optical fiber arrays 208A and 208B due to limitations in non-isotropic etching of the surface of the photonics die <NUM>. Optical fiber arrays 208A and 208B are collectively referred to herein as optical fiber array <NUM>, and optical connectors 210A and 210B are collectively referred to herein as optical connectors <NUM>.

According to the disclosed embodiments, the optical interconnect package <NUM> includes two groove alignment structures 212A and 212B on the photonics die <NUM> that allow for the optical fiber arrays 208A and 208B to run in different directions on the photonics die <NUM> and still meet the less than <NUM> alignment accuracy to align the optical fibers.

<FIG> illustrates a front, close-up view of an edge of photonics die <NUM> showing one embodiment of a first groove alignment structure 212A to guide and align the optical fiber array 208A into the photonics die <NUM>. The cross-section view shows that the first groove alignment structure 212A comprises an etch stop material <NUM>, a substrate <NUM> over the etch stop material <NUM>, and a set of grooves <NUM> along a first direction in a top surface of the substrate <NUM>. The second groove alignment structure 212B comprises a second set of grooves (not shown) along a second direction in a top surface of the substrate <NUM>.

An adhesive material <NUM> is in a bottom of the set of grooves <NUM>. Optical fibers <NUM> comprising the optical fiber array 208A are in the set of grooves <NUM> over the adhesive material <NUM>, and a portion of each of the optical fibers <NUM> extends or rises above the substrate <NUM>. A set of polymer guides <NUM> run along a first direction on a top surface of the substrate <NUM> interleaved with the set of grooves <NUM>. The set of polymer guides <NUM> function as passive alignment structures to help guide the optical fibers <NUM> into the set of grooves <NUM>.

<FIG> is a top view of the first groove alignment structure 212A without the optical fibers <NUM> and shows that the set of grooves <NUM> interleaved with the set of polymer guides <NUM> are substantially parallel (+/- <NUM> degrees) on the substrate <NUM>. As shown in <FIG>, directions of the optical fiber arrays 208A and 208B are substantially orthogonal to one another on the photonics die <NUM>, as are the first and second groove alignment structures 212A and 212B.

Due to the methods of fabrication, different groove alignment structures are possible. For example, referring again to <FIG>, the first groove alignment structure 212A has a cross-section that is U-shaped. The groove cross-section shape is determined by sidewalls of the groove, the etch stop material <NUM>, and any silicon material remaining in the groove after etching.

<FIG> illustrate front, close-up views of an edge of photonics die showing embodiments for a second groove alignment structure 212B and a third groove alignment structure 212C, respectively. In the second embodiment shown in <FIG>, the second groove alignment structure 212B has a cross-section that is square-shaped. In a third embodiment shown in Figure 3C, the third groove alignment structure 212C has a cross-section that has an under etch-shape.

In the first, second and third embodiments, the optical fibers <NUM> may have a diameter of approximately <NUM>-<NUM>, and a pitch of approximately <NUM>-<NUM>. In one embodiment, the substrate <NUM> may have a thickness of approximately one-half of a diameter of the optical fibers <NUM>. The set of grooves <NUM> may each have a width of approximately equal to the diameter of the optical fibers <NUM>.

The disclosed embodiments thus disclose novel-shaped groove alignment structures defined by <NUM>-step lithographic etching of silicon and corresponding polymer guides <NUM> to guide the optical fibers <NUM> into the grooves <NUM> for lithographic-based XY alignment accuracy. Grooves at any silicon plain angle can be supported and the polymer guides help with crude alignment of fibers into the grooves. Such an approach enables the use of thin photonics die and die thickness control (~<NUM> accuracy) to achieve Z alignment. Use of thin photonics die also enable use of TSV through the photonics die due to the thinness (e.g., ~<NUM>). Although in one embodiment all the following process steps utilize dry etching to allow more versatility, in another embodiment, an isotropic wet etch may also be used.

<FIG> are cross-section diagrams illustrating an exemplary process flow for fabricating a groove alignment structure according to the first embodiment. <FIG> shows that the process may begin by applying an etch stop material <NUM> to a backside of a substrate <NUM> comprising the photonics die. In one embodiment, the substrate comprises silicon (Si), but may comprise other materials including, but are not limited to: silicon germanium (SiGe), silicon-on-insulator (SOI), and group III-V semiconductors.

In an embodiment, etch stop material <NUM> may comprise a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. Alternatively, other etch stop layers known in the art may be used depending upon the particular implementation. In certain embodiments, the thickness of the etch stop material <NUM> may range from approximately <NUM> to <NUM>. The etch stop layers may be formed by CVD, PVD, or by other deposition methods. In embodiments, the etch stop material <NUM> may be spun-on the surface of the substrate using standard techniques.

<FIG> shows that on an opposite or a front side of the substrate <NUM> a first etch process is performed to form openings <NUM> that define accurate locations and widths of a plurality of grooves along a first direction in the substrate <NUM>. The first lithography and etch process defines X and Z alignment for the optical fiber array with sub-micron accuracy. Bridge thickness control defines Z alignment within <NUM>. Once inserted into the grooves, the optical fibers move within a plane (Y) of the substrate <NUM> (see <FIG>).

In embodiments, the etching process may be performed by a dry etch (e.g., a reactive-ion etch) or a laser etching process. Laser etching, if used, may also allow groove creation after the photonic die is attached to a package, which reduces the risk of the photonics die cracking. Any type of dry etching process that etches directionally or anisotropically may be used. Optionally, a wet etch may be used in place of a dry etch. The etching process is performed after an etch mask is formed using known photolithographic methods. In certain embodiments, the etch mask may be a hard mask of silicon dioxide or silicon nitride; and in other embodiments the etch-mask is made from known photoresist materials.

<FIG> also shows that polymer guides <NUM> are deposited in-between the openings <NUM> and run in the same direction as the openings <NUM>. As described above, the polymer guides <NUM> help with crude alignment of the optical fibers on the photonics die.

<FIG> shows that after the polymer guides <NUM> are formed, a second etch process is performed on the openings <NUM> to remove Si down to the etch stop material <NUM> to form the grooves <NUM>. As shown, the second etch process is performed on the openings such that the sidewalls and bottom form a U-shape <NUM> at the bottom of the grooves <NUM>. In embodiments, the second etching process may be performed by a dry etch (e.g., a reactive-ion etch) or a laser etching process.

<FIG> shows that after the second etch process, an adhesive material <NUM> is inserted or dispensed into the bottom of each of the grooves <NUM> and an optical fiber <NUM> of the optical fiber array is inserted into respective ones of the grooves <NUM> over the adhesive material <NUM>. Approximately one-half of each of the optical fibers <NUM> extends arises above a surface of the substrate <NUM>. The resultant groove alignment structure 212A is now ready to be covered by a polymer lid (not shown).

<FIG> are cross-section diagrams illustrating an exemplary process flow for fabricating a groove alignment structure according to the second embodiment. <FIG> shows that the process may begin by applying an etch stop material 220B to a backside of a substrate 222B comprising the photonics die.

<FIG> shows that on an opposite or a front side of the substrate 222B, an etch process is performed to remove silicon material down to the etch stop material 220B to form the grooves 224B in specific locations and with specific widths along a first direction in the substrate 222B. As shown, the etch process creates grooves 224B that are substantially square shaped as defined by near vertical sidewalls and the bottom etch stop material 220B. In embodiments, the etching process may be performed by a dry etch, such as a Bosch high-aspect ratio plasma etching process in which cyclic isotropic etching is performed.

<FIG> also shows that polymer guides 230B are deposited in-between the grooves 224B and run in the same direction as the openings <NUM>. As described above, the polymer guides 230B help with crude alignment of the optical fibers on the photonics die.

<FIG> shows that after the etch process, an adhesive material 226B is inserted into the bottom of each of the grooves 224B and an optical fiber 228B is inserted into each of the grooves 224B over the adhesive material 226B. Approximately one-half of each of the optical fibers 228B extends above a surface of the substrate 222B. The resultant groove alignment structure 212B is now ready to be covered by a polymer lid (not shown).

<FIG> are cross-section diagrams illustrating an exemplary process flow for fabricating a groove alignment structure according to the third embodiment in which a combination of isotropic and anisotropic etch are used. <FIG> shows that the process may begin by applying an etch mask <NUM> to a front side of the substrate 222C and applying an etch stop material 220C to a backside of a substrate 222C comprising the photonics die. The etch mask <NUM> is formed using known photolithographic methods. In certain embodiments, the etch mask <NUM> may be a hard mask of silicon dioxide or silicon nitride; and in other embodiments the etch-mask is a made from known photoresist materials. Openings in the etch mask <NUM> define the locations of a plurality of grooves to be formed along a first direction in the substrate 222C, and widths of the openings will define eventual widths of the plurality of grooves after the etching processes.

In one embodiment, the substrate comprises silicon (Si), but may comprise other materials including, but are not limited to: silicon germanium (SiGe), silicon-on-insulator (SOI), and group III-V semiconductors. In an embodiment, etch stop material 220C may comprise a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. Alternatively, other etch stop layers known in the art may be used depending upon the particular implementation. In certain embodiments, the thickness of the etch stop material 220C may range from approximately <NUM> to <NUM>. The etch stop layers maybe formed by CVD, PVD, or by other deposition methods. In embodiments, the etch stop material 220C may be spun-on the surface of the substrate using standard techniques.

<FIG> shows that a first lithography etch process is performed to form openings <NUM> to define accurate locations and widths of the plurality of grooves 224C. The first lithography and etch process defines X and Z alignment for the optical fibers 228C with sub-micron accuracy. Bridge thickness control defines Z alignment within <NUM>. In embodiments, an isotropic etching process may be performed by a dry etch (e.g., a reactive-ion etch) or a laser etching process. Laser etching, if use may also allow groove creation after the photonic die is attached to a package, which reduces the risk of the photonics die cracking. Any type of dry etching process that etches directionally or anisotropically may be used. Optionally, a wet etch may be used in place of a dry etch.

<FIG> also shows that polymer guides 230C are deposited over the etch mask <NUM> in-between the openings <NUM> and run in the same direction as the openings <NUM>. As described above, the polymer guides 230C help with crude alignment of the optical fibers on the photonics die.

<FIG> shows that after the polymer guides 230C are formed, a second etch process is performed on the openings <NUM> to remove the silicon substrate material down to the etch stop material 220C to form the grooves 224C. In embodiments, the second etching process comprises a wet isotropic etch. As shown, the second etch process etches sidewalls of the grooves 224C beneath the etch mask <NUM> such that the sidewalls form an under etch-shape <NUM>, where the widest part of the grooves 224C is wider than the corresponding opening <NUM> in the substrate 222C.

<FIG> shows that after the second etch process, an adhesive material 226C is inserted or dispensed into the bottom of each of the grooves 224C and an optical fiber 228C is inserted into each of the grooves 224C over the adhesive material 226C such that approximately one-half of each of the optical fibers 228C extends above a surface of the substrate 222C. The resultant groove alignment structure 212A is now ready to be covered by a polymer lid (not shown).

The third embodiment utilizes a combination of a dry etch and a wet etch to form a groove alignment structure having under etch-shaped grooves. The wider openings of the grooves 224C ensures that the optical fibers 228C can be inserted into the grooves 224C without any potential interferences from sidewall surface non-uniformities. In addition, the wider openings of the grooves 224C can accommodate excess adhesive 226C as well.

<FIG> illustrates a block diagram of an electronic system <NUM>. The electronic system <NUM> can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system <NUM> may include a microprocessor <NUM> (having a processor <NUM> and control unit <NUM>), a memory device <NUM>, and an input/output device <NUM> (it is to be appreciated that the electronic system <NUM> may have a plurality of processors, control units, memory device units and/or input/output devices). The electronic system <NUM> may have a set of instructions that define operations which are to be performed on data by the processor <NUM>, as well as, other transactions between the processor <NUM>, the memory device <NUM>, and the input/output device <NUM>. The control unit <NUM> coordinates the operations of the processor <NUM>, the memory device <NUM> and the input/output device <NUM> by cycling through a set of operations that cause instructions to be retrieved from the memory device <NUM> and executed. The memory device <NUM> can include a non-volatile memory cell as described in the present description. The memory device <NUM> may be embedded in the microprocessor <NUM>, as depicted in <FIG>. The processor <NUM>, or another component of electronic system <NUM>, may include one or more groove alignment structures, such as those described herein.

<FIG> is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more groove alignment structures as are disclosed herein.

Referring to <FIG>, an IC device assembly <NUM> includes components having one or more integrated circuit structures described herein. The IC device assembly <NUM> includes a number of components disposed on a circuit board <NUM> (which may be, e.g., a motherboard). The IC device assembly <NUM> includes components disposed on a first face <NUM> of the circuit board <NUM> and an opposing second face <NUM> of the circuit board <NUM>. Generally, components may be disposed on one or both faces <NUM> and <NUM>. In particular, any suitable ones of the components of the IC device assembly <NUM> may include a number of groove alignment structures, such as disclosed herein.

The circuit board <NUM> may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board <NUM>. Alternatively, the circuit board <NUM> may be a non-PCB substrate.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-interposer structure <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may electrically and mechanically couple the package-on-interposer structure <NUM> to the circuit board <NUM>, and may include solder balls (as shown in <FIG>), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure <NUM> may include an IC package <NUM> coupled to an interposer <NUM> by coupling components <NUM>. The coupling components <NUM> may take any suitable form for the application, such as the forms discussed above with reference to the coupling components <NUM>. Although a single IC package <NUM> is shown in <FIG>, multiple IC packages may be coupled to the interposer <NUM>. It is to be appreciated that additional interposers may be coupled to the interposer <NUM>. The interposer <NUM> may provide an intervening substrate used to bridge the circuit board <NUM> and the IC package <NUM>. The IC package <NUM> may be or include, for example, a die, or any other suitable component. Generally, the interposer <NUM> may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer <NUM> may couple the IC package <NUM> (e.g., a die) to a ball grid array (BGA) of the coupling components <NUM> for coupling to the circuit board <NUM>. In the assembly illustrated in <FIG>, the IC package <NUM> and the circuit board <NUM> are attached to opposing sides of the interposer <NUM>. Alternatively, the IC package <NUM> and the circuit board <NUM> may be attached to a same side of the interposer <NUM>. In some configurations, three or more components may be interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer <NUM>. The package-on-interposer structure <NUM> may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly <NUM> may include an IC package <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may take the form of any of the components discussed above with reference to the coupling components <NUM>, and the IC package <NUM> may take the form of any of the packages discussed above with reference to the IC package <NUM>.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-package structure <NUM> coupled to the second face <NUM> of the circuit board <NUM> by coupling components <NUM>. The package-on-package structure <NUM> may include an IC package <NUM> and an IC package <NUM> coupled together by coupling components <NUM> such that the IC package <NUM> is disposed between the circuit board <NUM> and the IC package <NUM>. The coupling components <NUM> and <NUM> may take the form of any of the coupling components <NUM> discussed above, and the IC packages <NUM> and <NUM> may take the form of any of the IC packages <NUM> discussed above. The package-on-package structure <NUM> may be configured in accordance with any of the package-on-package structures known in the art.

<FIG> illustrates a computing device <NUM>. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The term does not imply that the associated devices do not contain any wires, although it is not ruled out that they might not.

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more groove alignment structures, in accordance with implementations of embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more groove alignment structures, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes one or more groove alignment structures, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

Silicon groove architectures and manufacturing processes have been described for passive alignment in a photonics die.

Claim 1:
A groove alignment structure (212A, 212B, 212C), comprising:
an etch stop material (<NUM>, 220B, 220C);
a substrate (<NUM>, 222B, 222C) over the etch stop material (<NUM>, 220B, 220C);
a set of grooves (<NUM>, 224B, 224C) along a first direction in a top surface of the substrate (<NUM>, 222B, 222C);
adhesive material (<NUM>, 226B, 226C) in a bottom of the set of grooves (<NUM>, 224B, 224C);
optical fibers (<NUM>, 228B, 228C) in the set of grooves (<NUM>, 224B, 224C) over the adhesive material (<NUM>, 226B, 226C) and a portion of the optical fibers (<NUM>, 228B, 228C) extending above the substrate (<NUM>, 222B, 222C); and
a set of polymer guides (<NUM>, 230B, 230C) along the first direction on the top surface of the substrate (<NUM>, 222B, 222C) interleaved with the set of grooves (<NUM>, 224B, 224C), the set of polymer guides (<NUM>, 230B, 230C) for guiding the optical fibers (<NUM>, 228B, 228C) into the set of grooves (<NUM>, 224B, 224C).