Patent Description:
It is the object of the present invention to provide an enhanced method for controlling an electric motor.

A method for motor stator resistance calculation is disclosed. The method estimates an output voltage using a Direct Current (DC) bus voltage and a duty ratio for a motor drive at a first switching frequency and at least one second switching frequency. The method measures an output current at the first switching frequency and the at least one second switching frequency. The method calculates a first stator resistance for the first switching frequency and at least one second stator resistance for the at least one second switching frequency. The method estimates a stator resistance at a DC condition based on the first stator resistance and the at least one second stator resistance. The method sets a dynamic compensation based a stator resistance error between the first switching frequency and the at least one second switching frequency.

An apparatus for motor stator resistance calculation is also disclosed. The apparatus includes a processor and a memory. The processor estimates an output voltage using a DC bus voltage and a duty ratio for a motor drive at a first switching frequency and at least one second switching frequency. The processor measures an output current at the first switching frequency and the at least one second switching frequency. The processor calculates a first stator resistance for the first switching frequency and at least one second stator resistance for the at least one second switching frequency. The processor estimates a stator resistance at a DC condition based on the first stator resistance and the at least one second stator resistance. The processor sets a dynamic compensation based on a stator resistance error between the first switching frequency and the at least one second switching frequency.

A computer program product for motor stator resistance calculation is also disclosed. The computer program product includes non-transitory computer readable storage medium having program code embodied therein, the program code readable/executable by a processor. The processor estimates an output voltage using a DC bus voltage and a duty ratio for a motor drive at a first switching frequency and at least one second switching frequency. The processor measures an output current at the first switching frequency and the at least one second switching frequency. The processor calculates a first stator resistance for the first switching frequency and at least one second stator resistance for the at least one second switching frequency. The processor estimates a stator resistance at a DC condition based on the first stator resistance and the at least one second stator resistance. The processor sets a dynamic compensation based on a stator resistance error between the first switching frequency and the at least one second switching frequency.

In order that the advantages of the embodiments of the invention will be readily understood, a more particular description of the embodiments briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.

The terms "including," "comprising," "having," and variations thereof mean "including but not limited to" unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise. The term "and/or" indicates embodiments of one or more of the listed elements, with "A and/or B" indicating embodiments of element A alone, element B alone, or elements A and B taken together.

Furthermore, the described features, advantages, and characteristics of the embodiments may be combined in any suitable manner. One skilled in the relevant art will recognize that the embodiments may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments.

These features and advantages of the embodiments will become more fully apparent from the following description and appended claims or may be learned by the practice of embodiments as set forth hereinafter. As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method, and/or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," "module," or "system. " Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having program code embodied thereon.

Many of the functional units described in this specification have been labeled as modules, in order to emphasize their implementation independence more particularly. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components.

Modules may also be implemented in software for execution by various types of processors. An identified module of program code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.

Indeed, a module of program code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within modules and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network. Where a module or portions of a module are implemented in software, the program code may be stored and/or propagated on in one or more computer readable medium(s).

The computer readable medium may be a tangible computer readable storage medium storing the program code. The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, holographic, micromechanical, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.

More specific examples of the computer readable storage medium may include but are not limited to a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), an optical storage device, a magnetic storage device, a holographic storage medium, a micromechanical storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, and/or store program code for use by and/or in connection with an instruction execution system, apparatus, or device.

The computer readable medium may also be a computer readable signal medium. A computer readable signal medium may include a propagated data signal with program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electrical, electro-magnetic, magnetic, optical, or any suitable combination thereof A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport program code for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable signal medium may be transmitted using any appropriate medium, including but not limited to wireline, optical fiber, Radio Frequency (RF), or the like, or any suitable combination of the foregoing.

In one embodiment, the computer readable medium may comprise a combination of one or more computer readable storage mediums and one or more computer readable signal mediums. For example, program code may be both propagated as an electro-magnetic signal through a fiber optic cable for execution by a processor and stored on RAM storage device for execution by the processor.

Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Python, Ruby, R, Java, Java Script, Smalltalk, C++, C sharp, Lisp, Clojure, PHP or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer program product may be shared, simultaneously serving multiple customers in a flexible, automated fashion.

The computer program product may be integrated into a client, server and network environment by providing for the computer program product to coexist with applications, operating systems and network operating systems software and then installing the computer program product on the clients and servers in the environment where the computer program product will function. In one embodiment software is identified on the clients and servers including the network operating system where the computer program product will be deployed that are required by the computer program product or that work in conjunction with the computer program product. This includes the network operating system that is software that enhances a basic operating system by adding networking features.

The embodiments may transmit data between electronic devices. The embodiments may further convert the data from a first format to a second format, including converting the data from a non-standard format to a standard format and/or converting the data from the standard format to a non-standard format. The embodiments may modify, update, and/or process the data. The embodiments may store the received, converted, modified, updated, and/or processed data. The embodiments may provide remote access to the data including the updated data. The embodiments may make the data and/or updated data available in real time. The embodiments may generate and transmit a message based on the data and/or updated data in real time.

Aspects of the embodiments are described below with reference to schematic flowchart diagrams and/or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the invention. It will be understood that each block of the schematic flowchart diagrams and/or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams and/or schematic block diagrams, can be implemented by program code. The program code may be provided to a processor of a general purpose computer, special purpose computer, sequencer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the schematic flowchart diagrams and/or schematic block diagrams block or blocks.

The program code may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the schematic flowchart diagrams and/or schematic block diagrams block or blocks.

The program code may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the program code which executed on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The schematic flowchart diagrams and/or schematic block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of apparatuses, systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the schematic flowchart diagrams and/or schematic block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions of the program code for implementing the specified logical function(s).

It will also be noted that each block of the block diagrams and/or flowchart diagrams, and combinations of blocks in the block diagrams and/or flowchart diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and program code.

<FIG> is a schematic diagram of motor system <NUM>. The system <NUM> includes a motor <NUM> and a motor drive <NUM>. The motor <NUM> may be a salient motor <NUM>. The motor <NUM> may be controlled by the motor drive <NUM>.

In the depicted embodiment, the motor <NUM> includes a salient rotor <NUM> and a plurality of coils 103a-c. The motor drive <NUM> may direct electric currents with an output voltage <NUM> through the coils 103a-c to generate a motor flux that drives the rotor <NUM>.

The motor drive <NUM> may control the motor <NUM> to generate torque at a specified angular velocity. The motor drive <NUM> may be required to control the motor <NUM> within a range of torques and/or angular velocities for a variety of loads. In the depicted embodiment, the motor drive <NUM> includes a rectifier and/or converter <NUM>, referred to hereafter as a rectifier <NUM>, an inverter <NUM>, a bus capacitor <NUM>, and a controller <NUM>. The converter <NUM> supplies Direct Current (DC) bus voltage <NUM> and a neutral <NUM> to the inverter <NUM>. A capacitor <NUM> may filter the DC bus voltage <NUM>. The controller <NUM> may include a processor as shown in <FIG>. The controller <NUM> may produce the gate signals <NUM> to control the output voltage <NUM> supplied by the inverter <NUM>, and therefore control the motor <NUM>. The system <NUM> may include an encoder <NUM> that generates a position signal <NUM>. The position signal <NUM> may be used accurately control the motor <NUM>. In a certain embodiment, at least a portion of the motor drive <NUM> comprises one or more of hardware and executable code, the executable code stored on one or more computer readable storage media.

The motor system <NUM> does not include voltage sensing circuits to determine an output voltage <NUM>. As a result, the output voltage <NUM> is estimated. In the past, the output voltage <NUM> could not be accurately predicted because of nonlinear characteristics of the inverter <NUM>. Because of output voltage estimation inaccuracies, the torque accuracy of the motor system <NUM> was diminished, particularly at low speeds. The embodiments estimate a stator resistance at a DC condition and calculate the output voltage <NUM> using the stator resistance at the DC condition to improve the torque accuracy of the motor <NUM> as will be described hereafter.

<FIG> is a schematic diagram of the inverter <NUM>. The inverter <NUM> includes a plurality of gates <NUM> and diodes <NUM>. The gates <NUM> may be insulated-gate bipolar transistors (IGBT). The gate signals <NUM> turn the gates <NUM> on and off to generate the output voltages 115a-c for the plurality of coils 103a-c. The output voltages <NUM> have output currents <NUM> with an output current direction <NUM>. The output current <NUM> and output current direction <NUM> may be measured. Each gate <NUM> may have a collector to emitter voltage drop VCE <NUM>. In addition, each diode <NUM> may have diode voltage drop <NUM>.

<FIG> is a graph of an inverter turn off waveform. The graph shows a collector to emitter voltage drop <NUM> when a gate <NUM> is turned off by a gate signal <NUM>. The gate voltage <NUM>, gate current <NUM>, and switching loss <NUM> are also shown. The output voltage <NUM> is difficult to predict because the collector to emitter voltage drop <NUM> is not linear and is heavily dependent on inverter parasitics, motor cable type, motor cable length, and motor winding construction. The embodiments estimate a stator resistance measured at the DC condition and set a dynamic compensation based on the stator resistance. As a result, the nonlinear properties of the inverter <NUM> are compensated for as will be described hereafter.

<FIG> is a graph of an inverter turn on waveform. The graph shows a collector to emitter voltage drop <NUM> when a gate <NUM> is turned on by a gate signal <NUM>. The gate voltage <NUM>, gate current <NUM>, and switching loss <NUM> are also shown. The output voltage <NUM> is difficult to predict because the collector to emitter voltage drop <NUM> is not linear and is heavily dependent on inverter parasitics, motor cable type, motor cable length, and motor winding construction.

The embodiments estimate the output voltage <NUM> using the DC bus voltage <NUM> and a duty cycle for the motor drive <NUM> at least two switching frequencies. The embodiments further calculate at least two stator resistances for the switching frequencies and estimate a stator resistance measured at a DC condition based on the switching frequencies. The embodiments employ the stator resistance to set a dynamic compensation. The dynamic compensation may mitigate poor errors of stator resistance accuracy caused by the nonlinear properties of the inverter <NUM> as will be described hereafter. In one embodiment, the dynamic compensation mitigates the gate voltage drop Vce <NUM> and/or diode voltage drop Vf <NUM>.

<FIG> is a graph of compensated control signals. For clarity, differences are not to scale. A gate signal <NUM> and a gate signal transition <NUM> are shown. The gate signal <NUM> has a pulse width <NUM>. In addition, switch ON delays <NUM> and switch OFF delays <NUM> further modify the gate voltage drops <NUM> relative to the gate signal <NUM>. As a result, gate signal <NUM>-A1 is not aligned with the gate signal <NUM>. The embodiments determine the dynamic compensations <NUM> to mitigate the nonlinear properties of the inverter <NUM>.

<FIG> is a schematic block diagram of motor data <NUM>. The motor data <NUM> may be used to set the dynamic compensation <NUM> and/or estimate the output voltage <NUM>. The motor data <NUM> may be organized as a data structure in a memory. In the depicted embodiment, the motor data <NUM> includes a stator resistance <NUM> at a DC condition, the dynamic compensation <NUM>, and an estimated output voltage <NUM>. In one embodiment, the motor data <NUM> includes a time of the change <NUM>. The time of change <NUM> may record a time when the output current direction <NUM> changes after a gate signal transition <NUM> for a gate signal <NUM>.

In addition, the motor data <NUM> includes a plurality of frequency records <NUM>. Each frequency record <NUM> may include a duty ratio <NUM> for the motor drive <NUM>, a DC bus voltage <NUM>, a switching frequency <NUM> of the motor drive <NUM>, an output voltage <NUM>, a stator resistance <NUM>, and the output current <NUM>.

The stator resistance <NUM> measured at the DC condition may be estimated using the frequency records <NUM> as will be described hereafter. The estimated output voltage <NUM> may be estimated from the DC bus voltage <NUM> and a duty ratio <NUM> for the motor drive <NUM> at least two switching frequencies <NUM>. The switching frequency <NUM> may be a frequency of Pulse Width Modulation (PWM) switching by the inverter <NUM>. In one embodiment, each frequency record <NUM> is used to estimate the estimated output voltage <NUM>.

Each duty ratio <NUM> in the frequency record <NUM> may record the duty ratio <NUM> for the motor drive <NUM> at the corresponding switching frequency <NUM>. Each DC bus voltage <NUM> may record the DC bus voltage <NUM> for the motor drive <NUM> at the corresponding switching frequency <NUM>. Each switching frequency <NUM> in the frequency record <NUM> records the switching frequency <NUM> of the motor drive <NUM>. Each output voltage <NUM> in the frequency record <NUM> may record the output voltage <NUM> for the corresponding switching frequency <NUM>. Each stator resistance <NUM> in the frequency record <NUM> may be calculated based on the corresponding duty ratio <NUM>, DC bus voltage <NUM>, and/or output voltage <NUM>.

<FIG> is a graph of estimating the stator resistance <NUM> at a DC condition. In the depicted embodiment, a plurality of stator resistances <NUM> corresponding to a plurality of switching frequencies <NUM> are shown. In one embodiment, the stator resistance <NUM> at a DC condition is estimated as a linear regression of at least two of the stator resistances <NUM>. The stator resistance <NUM> may also be estimated using curve fitting and/or an equation.

<FIG> is a schematic block diagram of the controller <NUM>. In the depicted embodiment, the controller <NUM> includes a processor <NUM>, a memory <NUM>, and communication hardware <NUM>. The memory <NUM> may store code and data such as the motor data <NUM>. The processor <NUM> may execute the code and process the data. The communication hardware <NUM> may communicate with other devices.

<FIG> is a schematic flow chart diagram of a motor control method <NUM>. The method <NUM> may set the dynamic compensation <NUM>. In addition, the method <NUM> may dynamically calculate the output voltage <NUM> based on the stator resistance <NUM> and control the motor <NUM> using the calculated output voltage <NUM>. The method <NUM> may be performed by the processor <NUM>.

The method <NUM> starts, and in one embodiment, the processor <NUM> estimates <NUM> an output voltage <NUM> using the DC bus voltage VDC <NUM> and the duty ratio DR <NUM> for the motor drive <NUM> at a first switching frequency <NUM>-<NUM> and at least one second switching frequency <NUM>-<NUM>. Each output voltage Vo <NUM> may be estimated <NUM> using Equation <NUM>.

In one embodiment, the DC bus voltage <NUM>, the duty ratio <NUM>, the switching frequency <NUM>, and the output voltage <NUM> are recorded in a frequency record <NUM> for each switching frequency <NUM>.

In addition, the processor <NUM> may measure <NUM> the output current <NUM> at the first switching frequency <NUM>-<NUM> and the at least one second switching frequency <NUM>-<NUM>.

The processor <NUM> may further calculate <NUM> a first stator resistance <NUM>-<NUM> for the first switching frequency <NUM>-<NUM> and at least one second stator resistance <NUM>-<NUM> for the at least one second switching frequency <NUM>-<NUM>. In one embodiment, the processor <NUM> calculates <NUM> at least two stator resistances <NUM>. The stator resistances RS <NUM> may be calculated using Equation <NUM>, where IO is the output current <NUM>.

The processor <NUM> may estimate <NUM> the stator resistance <NUM> at a DC condition. In one embodiment, the stator resistance RS <NUM> at the DC condition is estimated using a linear regression based on the first stator resistance <NUM>-<NUM> and the at least one second stator resistance <NUM>-<NUM> such as is illustrated in <FIG>. In addition, the stator resistance RS <NUM> at the DC condition may be estimated using curve fitting based on the first stator resistance <NUM>-<NUM> and the at least one second stator resistance <NUM>-<NUM>. In a certain embodiment, the stator resistance RS <NUM> at the DC condition is estimated using Equation <NUM>, where R<NUM> is the first stator resistance <NUM>-<NUM>, R<NUM> is a second stator resistance <NUM>-<NUM>, F<NUM> is the first switching frequency <NUM>-<NUM>, and F<NUM> is the second switching frequency <NUM>-<NUM>.

The processor <NUM> may set <NUM> the dynamic compensation <NUM> based on a stator resistance error between the first switching frequency and the at least one second switching frequency.

In one embodiment, the dynamic compensation Td <NUM> is set <NUM> using Equation <NUM>, wherein TS is the dynamic transition equivalent time during the gate signal transition <NUM>, TON is the switch ON delay <NUM>, and TOFF is the switch OFF delay <NUM>.

In one embodiment, the dynamic compensation <NUM> modifies gate signals <NUM> for the inverter <NUM>. In one embodiment, the dynamic compensation <NUM> compensates for nonlinearities in the collector to emitter voltage drop <NUM> and/or the diode voltage drop <NUM>.

The processor <NUM> may dynamically calculate <NUM> the output voltage <NUM> based on the stator resistance <NUM> at the DC condition. The output voltage <NUM> may be dynamically calculated <NUM> during operation of the motor <NUM>. In one embodiment, the output voltage Vo <NUM> is calculated for Equation <NUM>, wherein RS is the stator resistance <NUM> at the DC condition and IO is the output current <NUM>.

The processor <NUM> may further dynamically control <NUM> the motor <NUM> using the calculated output voltage <NUM>. Controlling <NUM> the motor <NUM> using the calculated output voltage <NUM> and/or dynamic compensation <NUM> may significantly improve torque accuracy for the motor <NUM>.

The output voltage <NUM> is difficult to predict because the collector to emitter voltage drop <NUM> is not linear and is heavily dependent on inverter parasitics. Because the output voltage <NUM> cannot be accurately predicted, the torque accuracy of the motor system <NUM> may be diminished, particularly at low speeds. In the past, voltage sensing circuits have been used to measure the output voltage <NUM>. However, voltage sensing circuits increase the cost of the motor system <NUM>.

Claim 1:
A motor control method (<NUM>) the method comprising:
estimating (<NUM>) an output voltage (<NUM>) of an inverter (<NUM>) of a motor drive using a Direct Current, DC, bus voltage (<NUM>) and a duty ratio (<NUM>) for the motor drive at a first switching frequency (<NUM>-<NUM>) and at least one second switching frequency (<NUM>-<NUM>);
measuring (<NUM>) an output current (<NUM>) of the inverter at the first switching frequency and the at least one second switching frequency;
calculating (<NUM>) a first stator resistance (<NUM>-<NUM>) for the first switching frequency and at least one second stator resistance (<NUM>-<NUM>) for the at least one second switching frequency based on the estimated output voltage and the measured output current at the respective switching frequency;
estimating (<NUM>) a stator resistance (<NUM>) at a DC condition based on the first stator resistance and the at least one second stator resistance;
setting (<NUM>) a dynamic compensation based on a stator resistance error between the first switching frequency and the at least one second switching frequency.