Patent Description:
The group III nitride semiconductor devices using the group III nitride semiconductors, especially GaN (gallium nitride) or AlGaN (aluminum gallium nitride), have high dielectric breakdown voltages due to the wide bandgap of the materials. In addition, with the group III nitride semiconductor devices, a hetero structure such as AlGaN/GaN can be easily formed.

With the AlGaN/GaN hetero structure, due to the difference between piezoelectric polarization generated by the difference in lattice constants between the materials and the spontaneous polarization of AlGaN and GaN, a channel consisting of high-concentration electrons (hereinafter referred to as a "two-dimensional electron gas layer") on the GaN layer side of the AlGaN/GaN interface. The group III nitride semiconductor devices using the channels of the above-described two-dimensional electron gas layer have a relatively high electron saturation velocity, relatively high insulation resistance, and relatively high thermal conductivity, and thus are applied to high-frequency power devices.

In order to enhance the characteristics of the above-described group III nitride semiconductor devices, the parasitic resistance components such as the contact (hereinafter referred to as an ohmic contact) between the ohmic electrode and the two-dimensional electron gas layer in the group III nitride semiconductor device and the resistance of the channel may be reduced as much as possible.

<FIG> is a cross-sectional view illustrating a configuration in proximity to an ohmic electrode in a group III nitride semiconductor device described in Patent Literature (PTL) <NUM>. As illustrated in <FIG>, according to PTL <NUM>, buffer layer <NUM>, GaN layer 1103A, AIN layer <NUM>, and AlGaN layer 1104A are formed in order above substrate <NUM>, and two-dimensional electron gas layer <NUM> resulting from the hetero structure of AIN layer <NUM> and GaN layer 1103A is provided on a GaN layer 1103A side. Ohmic electrode <NUM> is formed on recess <NUM> where portions of AlGaN layer 1104A, AIN layer <NUM>, and GaN layer 1103A have been removed. It is described that the angle of recess <NUM> intersecting the hetero interface between AIN layer <NUM> and GaN layer 1103A to the surface of substrate <NUM> on the acute angle side is greater than <NUM> degrees and less than or equal to <NUM> degrees. According to the above-described configuration, with the semiconductor device described in PTL <NUM>, two-dimensional electron gas layer <NUM> and ohmic electrode <NUM> can be in contact with each other and the contact area can be increased, and thus it is possible to reduce the resistance of the ohmic contact.

[PTL <NUM>] <CIT>
<CIT> discloses a nitride semiconductor device in which contact resistance between an ohmic electrode and an ohmic recess portion is reduced. The recess portion is formed by dry etching followed by wet etching using a KOH solution.

According to the method described in PTL <NUM> above, the contact area between two-dimensional electron gas layer <NUM> and ohmic electrode <NUM> is increased by reducing the angle of recess <NUM> intersecting the hetero interface between AIN layer <NUM> and GaN layer 1103A to the surface of the substrate <NUM> on the acute angle side. However, the contact area is still insufficient. In addition, AIN layer <NUM> is capable of improving the electron mobility and sheet carrier concentration of two-dimensional electron gas layer <NUM>, and thus is indispensable for enhancing the performance of the group III nitride semiconductor device. However, due to the large bandgap, there is a problem that contact from AlGaN layer 1104A that is an upper layer becomes significantly high resistance resulting from AIN layer <NUM> being a barrier.

Furthermore, since recess <NUM> is formed by dry etching, high resistance layer <NUM> including a crystal defect is formed on the surface of AlGaN layer 1104A, AIN layer <NUM>, and GaN layer 1103A exposed by recess <NUM>. For that reason, two-dimensional electron gas layer <NUM> and ohmic electrode <NUM> are not in direct contact with each other, and are distant from each other by the width of high resistance layer <NUM>. As a result, the resistance of the ohmic contact is increased.

As described above, with the conventional techniques, there is a problem that it is not possible to sufficiently reduce the resistance of the ohmic contact.

The present disclosure has been conceived in view of the above-described problems, and has an object to provide a semiconductor device capable of reducing the resistance of the ohmic contact.

According to the invention there is provided a semiconductor device according to claim <NUM>.

According to the invention there is further provided a method of manufacturing a semiconductor device according to claim <NUM>.

Particular embodiments are defined by the dependent claims.

A semiconductor device capable of reducing ohmic resistance is provided.

The inventors have conducted a series of diligent investigation and experiments in order to provide a semiconductor device capable of reducing the resistance of an ohmic contact. As a result, the inventors have arrived at the following semiconductor device, etc..

A semiconductor device according to one aspect of the present disclosure includes: a substrate; a channel layer disposed above the substrate, the channel layer being a group III nitride not containing Al; a barrier layer disposed above the channel layer, the barrier layer being a group III nitride containing Al; a gate electrode joined to the barrier layer; a recess defined by removing at least a portion of the barrier layer from a surface of a laminated semiconductor including the channel layer and the barrier layer; and an ohmic electrode disposed in the recess, the ohmic electrode being in ohmic contact with a two-dimensional electron gas layer generated in the channel layer. In the semiconductor device, an Al composition ratio distribution of the barrier layer in a first direction perpendicular to a surface of the substrate has a maximum point at a first position, the semiconductor device includes, in the first direction: a first inclined surface of the barrier layer, the first inclined surface including the first position and being in contact with the ohmic electrode; and a second inclined surface of the barrier layer, the second inclined surface intersecting the first inclined surface at a first intersection line on a lower side of the first inclined surface and being in contact with the ohmic electrode, an angle of the second inclined surface to the surface of the substrate is smaller than an angle of the first inclined surface to the surface of the substrate, and a second position that is a position of the first intersection line in the first direction is lower than the first position.

According to the above-described semiconductor device, it is possible to make the barrier layer on the second inclined surface significantly thin. Therefore, the ohmic electrode and the two-dimensional electron gas layer can be in ohmic contact with each other via the second inclined surface, and thus it is possible to increase the contact area. In addition, it is possible to increase the contact area by reducing the angle of the second inclined surface to the surface of the substrate. In addition, since the second inclined surface is formed by wet etching, the high resistance layer formed by dry etching is at least partially removed. As a result, at the second inclined surface where the contacting area is increased, the distance between the two-dimensional electron gas layer and the ohmic electrode is short and there is no resistance component, and thus it is possible to reduce the resistance of an ohmic contact.

In addition, a distance between the first position and the second position may be greater than <NUM> and less than or equal to <NUM>.

According to the above-described configuration, the distance between the first position and the second position is made small, and thus the angle of the second inclined surface to the surface of the substrate is made small. As a result, the area of the second inclined surface can further be increased, and thus it is possible to further reduce the resistance of the ohmic contact.

In addition, in a plan view of the substrate, in a plan view of the substrate: the first intersection line may include three or more recess portions each being recessed toward a first inclined surface side in a second direction in which the first inclined surface and the second inclined surface are arranged; and the three or more recess portions may be irregularly arranged in a third direction that is an extending direction of the first intersection line.

According to the above-described configuration, the area of the second inclined surface can further be increased, and thus it is possible to further reduce the resistance of the ohmic contact.

A semiconductor device according to one aspect of the present disclosure includes: a substrate; a channel layer disposed above the substrate, the channel layer being a group III nitride not containing Al; a barrier layer disposed above the channel layer, the barrier layer being a group III nitride containing Al; a gate electrode joined to the barrier layer; a recess defined by removing at least a portion of the barrier layer from a surface of a laminated semiconductor including the channel layer and the barrier layer; and an ohmic electrode disposed in the recess, the ohmic electrode being in ohmic contact with a two-dimensional electron gas layer generated in the channel layer. In the semiconductor device, an Al composition ratio distribution of the barrier layer in a first direction perpendicular to a surface of the substrate has a maximum point at a first position, the semiconductor device includes, in the first direction: a first inclined surface of the barrier layer, the first inclined surface including the first position and being in contact with the ohmic electrode; and a second inclined surface of the barrier layer, the second inclined surface intersecting the first inclined surface at a first intersection line on a lower side of the first inclined surface and being in contact with the ohmic electrode, and in a plan view of the substrate: the first intersection line includes three or more recess portions each being recessed toward a first inclined surface side in a second direction in which the first inclined surface and the second inclined surface are arranged; and the three or more recess portions are irregularly arranged in a third direction that is an extending direction of the first intersection line.

With the above-described semiconductor device, it is possible to increase the area of the second inclined surface, by forming the recess portion. As a result, it is possible to reduce the resistance of the ohmic contact. In addition, since the second inclined surface is formed by wet etching, the high resistance layer formed by dry etching is at least partially removed. As a result, it is possible to reduce the resistance of the ohmic contact, as well as reducing the distance between the two-dimensional electron gas layer and the ohmic electrode.

In addition, in each of the three or more recess portions, an angle of the second inclined surface to the surface of the substrate may be less than <NUM> degrees.

According to the above-described configuration, the area of the second inclined surface in the recess portion can further be increased, and thus it is possible to further reduce the resistance of the ohmic contact.

In addition, in each of the three or more recess portions, the first intersection line may include a curve.

According to the above-described configuration, since the first intersection line includes a curve in the recess portion, it is possible to alleviate electric field concentration in the end portion of the ohmic electrode in the recess portion.

In addition, each of the three or more recess portions may have a depth greater than or equal to <NUM> and less than or equal to <NUM> in the second direction.

In addition, the barrier layer may include an AIN layer, and the first position may be located within a range defined by a thickness of the AIN layer in the first direction.

In addition, an Al composition ratio of the barrier layer at the first position may be greater than or equal to <NUM>%.

In addition, in the first direction, a distance between the first position and a bottom position of the barrier layer may be less than or equal to <NUM>% of a thickness of the barrier layer.

In addition, a third inclined surface of the channel layer, the third inclined surface intersecting the second inclined surface at a second intersection line on a lower side of the second inclined surface, and being in contact with the ohmic electrode may be included. In the semiconductor device, the angle of the second inclined surface to the surface of the substrate may be smaller than an angle of the third inclined surface to the surface of the substrate.

In addition, a third inclined surface of the channel layer, the third inclined surface intersecting the second inclined surface at a second intersection line on a lower side of the second inclined surface, and being in contact with the ohmic electrode may be included. In the semiconductor device, an angle of the third inclined surface to the surface of the substrate may be smaller than the angle of the first inclined surface to the surface of the substrate.

According to the above-described configuration, since the second inclined surface is formed by wet etching, the angle of the second inclined surface to the surface of the substrate is made small. As a result, the area of the second inclined surface can further be increased, and thus it is possible to further reduce the resistance of the ohmic contact.

In addition, the angle of the first inclined surface to the surface of the substrate may be less than <NUM> degrees.

According to the above-described configuration, it is possible to implant metal atoms to the second inclined surface when an ohmic electrode is deposited by sputtering. As a result, it is possible to further reduce the resistance of the ohmic contact.

In addition, the second inclined surface may be a semi-polar plane of a semiconductor crystal configuring the barrier layer.

According to the above-described configuration, the second inclined surface is a semi-polar plane of the semiconductor crystal configuring the barrier layer, which facilitates formation of nitrogen holes by heat treatment when forming the ohmic electrode, and making it n-type. As a result, it is possible to further reduce the resistance of the ohmic contact.

In addition, the angle of the second inclined surface to the surface of the substrate may be less than or equal to <NUM> degrees.

In addition, in the first direction, a distance between the first position and a bottom position of the recess may be greater than or equal to <NUM> and less than or equal to <NUM>.

According to the above-described configuration, the distance between the first position and the bottom surface of the recess is made relatively small, and thus it is possible to reduce the time period of dry etching when forming the recess. It is thus possible to reduce the amount of formation of the high resistance layer that is formed on the side surface of the recess, thereby enabling an increase in the resistance value to be inhibited. As a result, it is possible to further reduce the resistance of the ohmic contact.

In addition, a <<NUM>> direction of a semiconductor crystal configuring the channel layer may be the first direction.

According to the above-described configuration, the sheet carrier concentration of the two-dimensional electron gas layer can be increased, and thus it is possible to further reduce the resistance of the ohmic contact.

According to the invention, an extending direction of the gate electrode in a plan view of the substrate is a <<NUM>-<NUM>> direction of a semiconductor crystal configuring the channel layer.

According to the above-described configuration, it is possible to enhance the temperature characteristics of Vth.

A manufacturing method of a semiconductor device according to one aspect of the present disclosure includes in particular: forming a channel layer above a substrate, the channel layer being a group III nitride not containing Al; forming a barrier layer above the channel layer, the barrier layer being a group III nitride containing Al; performing dry etching to define a recess by removing at least a portion of the barrier layer from a surface of a laminated semiconductor including the channel layer and the barrier layer; performing wet etching using an alkaline chemical solution after the performing of the dry etching, the alkaline chemical solution having a pH value of <NUM> to <NUM> and a temperature of greater than or equal to <NUM> degrees Celsius; forming an ohmic electrode to fill the recess after the performing of the wet etching; and performing a heat treatment on the ohmic electrode.

According to the above-described manufacturing method of the semiconductor device, the second position that is the position of the first intersection line is lower than the first position that is the maximum point of the Al composition ratio distribution in the first direction, and thus it is possible to make the barrier layer on the second inclined surface significantly thin. Therefore, the ohmic electrode and the two-dimensional electron gas layer can be in ohmic contact with each other via the second inclined surface, and thus it is possible to increase the contact area. In addition, since the second inclined surface is formed by wet etching, the high resistance layer formed by dry etching is at least partially removed. As a result, at the second inclined surface where the contacting area is increased, the distance between the two-dimensional electron gas layer and the ohmic electrode is short and there is no resistance component, and thus it is possible to reduce the resistance of the ohmic contact.

In addition, in a plan view of the substrate, the first intersection line is capable of including a recess portion on the first inclined surface side in the second direction in which the first inclined surface and the second inclined surface are arranged. In the case where three or more recess portions are included, the three or more recess portions are irregularly arranged in the third direction that is an extending direction of the first intersection line. As a result, the area of the second inclined surface can further be increased, and thus it is possible to further reduce the resistance of the ohmic contact.

A manufacturing method of a semiconductor device according to one aspect of the present disclosure includes in particular:
forming a channel layer above a substrate, the channel layer being a group III nitride; forming a barrier layer above the channel layer, the barrier layer being the group III nitride and having a band gap larger than a band gap of the channel layer; forming an insulating layer above the barrier layer; forming a mask above the insulating layer, the mask being provided with an opening; forming a side etch by removing, using the mask, (i) an entirety of the insulating layer in a region exposed by the opening and (ii) a portion of the insulating layer to cause a side surface of the insulating layer to be recessed inwardly relative to a side surface of the mask; removing at least a portion of the barrier layer and the channel layer to define a recess, by dry etching using the mask; removing the mask; forming an ohmic electrode to cover the recess and a portion of the insulating layer; and performing a heat treatment on the ohmic electrode.

Hereinafter, a semiconductor device according to an aspect of the present disclosure will be described with reference to the drawings. It should be noted that each of the exemplary embodiments described below shows a specific example of the present disclosure. The numerical values, shapes, elements, the arrangement and connection of the elements, steps (processes), and the processing order of the steps, for instance, described in the following embodiment are mere examples, and thus are not intended to limit the scope of the present disclosure. The drawings are schematic diagrams and do not necessarily give strict illustration. Throughout the drawings, the same numeral is given to substantially the same element, and redundant description is omitted or simplified.

First, a semiconductor device according to an embodiment will be described with reference to <FIG>, <FIG>, and <FIG>.

<FIG> is a cross-sectional view illustrating a configuration of semiconductor device <NUM> according to the embodiment. <FIG> is an enlarged cross-sectional view illustrating a configuration of semiconductor device <NUM> in proximity to an ohmic electrode. <FIG> illustrates plan views and cross-sectional views of semiconductor device <NUM> after dry etch processing, after wet etch processing, and after formation of the ohmic electrode.

In the present embodiment, the case where semiconductor device <NUM> is a heterojunction field effect transistor (HFET) will be described.

As illustrated in <FIG>, semiconductor device <NUM> includes substrate <NUM>, buffer layer <NUM>, channel layer <NUM>, barrier layer <NUM>, two-dimensional electron gas layer <NUM>, recess <NUM>, gate electrode <NUM>, source electrode <NUM>, and drain electrode 108D. Here, when there is no need to distinguish between source electrode <NUM> and drain electrode 108D in the description, source electrode <NUM> and drain electrode 108D are also referred to as ohmic electrode <NUM>.

Substrate <NUM> is, for example, a substrate including Si. Substrate <NUM> is not limited to a substrate including Si, but may also be a substrate including sapphire, SiC, GaN, AIN, or the like.

Buffer layer <NUM> is formed above substrate <NUM>. Buffer layer <NUM> is, for example, a group III nitride semiconductor layer having a thickness of <NUM> and including a plurality of laminated structures each including AIN and AlGaN. Buffer layer <NUM> may alternatively include a single layer or multiple layers of group III nitride semiconductors such as GaN, AlGaN, AIN, InGaN, AlInGaN, etc..

Channel layer <NUM> is formed above substrate <NUM>. According to the present embodiment, channel layer <NUM> is formed above buffer layer <NUM> in the +c-plane direction (<<NUM>> direction), for example. Channel layer <NUM> is a group III nitride semiconductor layer in which Al is not included, and includes GaN having a thickness of <NUM>, for example.

It should be noted that channel layer <NUM> may include a group III nitride semiconductor of not only GaN but also InGaN or the like, as long as channel layer <NUM> is a group III nitride semiconductor layer in which Al is not included. In addition, channel layer <NUM> may contain an n-type impurity.

Barrier layer <NUM> is formed above channel layer <NUM>. According to the present embodiment, barrier layer <NUM> is formed above channel layer <NUM> in the +c-plane direction (<<NUM>> direction), for example. Barrier layer <NUM> is a group III nitride semiconductor layer in which Al is included. The Al composition ratio distribution of barrier layer <NUM> in the first direction perpendicular to substrate <NUM> has a maximum point at first position <NUM>.

According to the present embodiment, two-dimensional electron gas that is highly concentrated is generated on the channel layer <NUM> side of the hetero interface between barrier layer <NUM> and channel layer <NUM> laminated in the +c-plane direction (<<NUM>> direction), and a channel of two-dimensional electron gas layer <NUM> is formed.

It should be noted that a cap layer that includes GaN and has a thickness of approximately <NUM> to <NUM>, for example, may be provided above barrier layer <NUM> as a cap layer.

Recess <NUM> is formed so as to remove the entirety of barrier layer <NUM> and a portion of channel layer <NUM> from the surface of the laminated semiconductor including channel layer <NUM> and barrier layer <NUM>. In addition, recess <NUM> is formed such that the distance between first position <NUM> and the bottom position of recess <NUM> is <NUM>.

It should be noted that recess <NUM> need only be formed so as to remove at least a portion of barrier layer <NUM> from the surface of the laminated semiconductor including channel layer <NUM> and barrier layer <NUM>, and do not necessarily need to be limited to the example in which recess <NUM> is formed so as to remove the entirety of barrier layer <NUM> and a portion of channel layer <NUM>.

Gate electrode <NUM> is formed above barrier layer <NUM>. Gate electrode <NUM> is in contact with barrier layer <NUM>. More specifically, gate electrode <NUM> is Schottky bonded to barrier layer <NUM>. Gate electrode <NUM> has, for example, a multilayer film structure including a Ni film and an Au film laminated in sequence.

It should be noted that gate electrode <NUM> may be a single layer structure, or a multilayer film structure including Ti, TiN, Ta, TaN, Pt, Pd, Al, W, WN, WSi, Cu, etc. which are laminated in order. In addition, gate electrode <NUM> and barrier layer <NUM> need not necessarily be limited to the example in which gate electrode <NUM> is Schottky bonded to barrier layer <NUM>, and may be in contact with each other by a PN junction, or gate electrode <NUM> and barrier layer <NUM> may form a metal-insulator-semiconductor (MIS) structure, a metal-oxide-semiconductor (MOS) structure, etc., for example.

Ohmic electrode <NUM> is formed above substrate <NUM>. Ohmic electrode <NUM> is, for example, a multilayer electrode film that has a laminated structure including a Ti film and an Al film laminated in order.

It should be noted that ohmic electrode <NUM> is not limited to the combination of Ti and Al, but may be a single layer electrode film including a single metal such as Ti, Au, Ta, Al, Mo, Hf, Zr, Au, Cu, etc., or a multilayer electrode film including a combination of two or more of these metals.

Ohmic electrode <NUM> is disposed in recess <NUM> and electrically connected to two-dimensional electron gas layer <NUM>. More specifically, barrier layer <NUM> and channel layer <NUM> of a side surface of recess <NUM> react with ohmic electrode <NUM> as a result of heat treatment to form nitrogen holes and become n-type. In addition, the face of recess <NUM> at which barrier layer <NUM> and channel layer <NUM> are exposed is a semi-polar plane, which makes it easier to form nitrogen holes and to become n-type. In this manner, ohmic electrode <NUM> is in ohmic contact with two-dimensional electron gas layer <NUM>. Here, the semi-polar plane refers to a plane other than a plane in which atoms are regularly arranged in a GaN crystal.

Next, with reference to <FIG>, the configuration of semiconductor device <NUM> in proximity to ohmic electrode <NUM> will be described in more detail.

As illustrated in <FIG>, barrier layer <NUM> is a group III nitride semiconductor layer that includes, for example, Al diffusion layer <NUM> having a thickness of <NUM>, AIN layer <NUM> having a thickness of <NUM>, Al diffusion layer <NUM> having a thickness of <NUM>, and AlGaN layer 104A having a thickness of <NUM> and an Al composition ratio of <NUM>%, which are laminated in stated order. Al diffusion layer <NUM> is formed on the channel layer <NUM> side and the AlGaN layer 104A side as a result of diffusion of Al from AIN layer <NUM> due to the heat generated when AIN layer <NUM> and barrier layer <NUM> are deposited.

It should be noted that, although the case where there is AIN layer <NUM> which is a spacer layer in barrier layer <NUM> has been described in the present embodiment, there may be no AIN layer <NUM>. It should be noted that AlGaN layer 104A may contain In, and barrier layer <NUM> may contain an n-type impurity.

In addition, recess <NUM> includes first inclined surface <NUM> having a maximum point of the Al composition ratio distribution at first position <NUM> in contact with ohmic electrode <NUM>, second inclined surface <NUM> below first inclined surface <NUM>, and third inclined surface <NUM>. More specifically, as illustrated in column (b) of <FIG>, in the first direction, recess <NUM> includes: first inclined surface <NUM>; second inclined surface <NUM> intersecting first inclined surface <NUM> at second position <NUM> in a cross-sectional view and first intersection line <NUM> in a plan view; and third inclined surface <NUM> intersecting second inclined surface <NUM> at third position <NUM> in the cross-sectional view and second intersection line <NUM> in the plan view. Third inclined surface <NUM> intersects the bottom surface of recess <NUM> at fourth position <NUM> which is an edge portion of the bottom surface of recess <NUM> in the cross-sectional view, and at third intersection line <NUM> in the plan view. In addition, the angle of second inclined surface <NUM> to the surface of substrate <NUM> is smaller than the angle of first inclined surface <NUM> to the surface of substrate <NUM>, and second position <NUM> is lower than first position <NUM>.

In the present embodiment, the distance from first position <NUM> to second position <NUM> is, for example, <NUM>.

It should be noted that the distance from first position <NUM> to second position <NUM> may be greater than <NUM> and less than or equal to <NUM>. As described above, it is possible to increase a contact area between ohmic electrode <NUM> and two-dimensional electron gas layer <NUM>, by reducing the distance from first position <NUM> to second position <NUM>.

In addition, the angle of second inclined surface <NUM> to the surface of substrate <NUM> is smaller than the angle of third inclined surface <NUM> to the surface of substrate <NUM>. In addition, the angle of third inclined surface <NUM> to the surface of substrate <NUM> is smaller than the angle of first inclined surface <NUM> to the surface of substrate <NUM>. According to the present embodiment, the angles of first inclined surface <NUM>, second inclined surface <NUM>, and third inclined surface <NUM> to the surface of substrate <NUM> are arranged such that, for example, the angle of first inclined surface <NUM> is <NUM> degrees, the angle of second inclined surface <NUM> is <NUM> degrees, and the angle of third inclined surface <NUM> is <NUM> degrees.

It should be noted that the angle of second inclined surface <NUM> to the surface of substrate <NUM> may be less than or equal to <NUM> degrees. As described above, it is possible to increase the contact area between ohmic electrode <NUM> and two-dimensional electron gas layer <NUM>, by reducing the angle of second inclined surface <NUM> to the surface of substrate <NUM>.

As illustrated in column (b) of <FIG>, first intersection line <NUM> includes recess portions <NUM> on the first inclined surface <NUM> side in the second direction in which first inclined surface <NUM> and second inclined surface <NUM> are arranged. Recess portions <NUM> are irregularly arranged in the third direction that is an extending direction of first intersection line <NUM>. Second position 115A in recess portions <NUM> is recessed toward the first inclined surface <NUM> side compared to second position <NUM> in other than recess portions <NUM>, thereby increasing the area of second inclined surface <NUM>. As a result, it is possible to further reduce the resistance of the ohmic contact.

It should be noted that, in recess portions <NUM>, the angle of second inclined surface <NUM> to the surface of substrate <NUM> may be less than <NUM> degrees. As described above, it is possible to increase the contact area between ohmic electrode <NUM> and two-dimensional electron gas layer <NUM>, by setting the angle of second inclined surface <NUM> to the surface of substrate <NUM> to less than <NUM> degrees.

In addition, recess portions <NUM> may each include a curved portion in a plan view. In this case, it is possible to alleviate the electric field that concentrates at an edge of the ohmic electrode, by including a curved portion in each of recess portions <NUM>. As a result, it is possible to inhibit destruction of the device.

The depth of recess portions <NUM> in the second direction may be <NUM> to <NUM>. The width of each of recess portions <NUM> may be <NUM> to <NUM> in the third direction. In addition, recess portions <NUM> that are arranged may be spaced apart from each other with an interval of <NUM> to <NUM> in the third direction, with a pitch of <NUM> to <NUM>.

As a result of semiconductor device <NUM> having the above-described configuration, second position <NUM> is lower than first position <NUM>, and thus it is possible to make barrier layer <NUM> on second inclined surface <NUM> significantly thin, compared to the conventional technique of PTL <NUM>. Therefore, ohmic electrode <NUM> and two-dimensional electron gas layer <NUM> can be in ohmic contact with each other via second inclined surface <NUM>, and thus it is possible to increase the contact area.

<FIG> is an enlarged plan view illustrating a configuration of semiconductor device <NUM> in proximity to a gate electrode.

As illustrated in <FIG>, the extending direction of gate electrode <NUM> in a plan view of substrate <NUM> is in a <<NUM>-<NUM>> direction of orientation <NUM> of a semiconductor crystal configuring channel layer <NUM>. Since semiconductor device <NUM> has such a configuration as described above, it is possible to improve the temperature characteristics of Vth.

The following describes a manufacturing method of semiconductor device <NUM> according to the present embodiment with reference to <FIG>, and <FIG>.

<FIG> each illustrate a cross-sectional view and an enlarged cross-sectional view indicating a configuration of semiconductor device <NUM> during a manufacturing process. In <FIG>, the diagram on the left side is a cross-sectional view illustrating the overall configuration of semiconductor device <NUM>, and the diagram on the right side is an enlarged cross-sectional view illustrating the configuration in proximity to ohmic electrode <NUM>.

First, as illustrated in <FIG>, buffer layer <NUM> having a thickness of <NUM> and including a laminated structure of AIN and AlGaN, channel layer <NUM> having a thickness of <NUM> and including i-type GaN, AIN layer <NUM> having a thickness of <NUM>, and i-type AlGaN layer 104A having a thickness of <NUM> and an Al composition ratio of <NUM>% are epitaxially grown in the +c-plane direction (<<NUM>> direction) sequentially above substrate <NUM> including Si, using a metalorganic chemical vapor deposition (MOCVD). At this time, Al diffusion layer <NUM> is formed on the channel layer <NUM> side and the AlGaN layer 104A side as a result of diffusion of Al from AlN layer <NUM> due to the heat generated when AIN layer <NUM> and AlGaN layer 104A are deposited. In this manner, barrier layer <NUM> which includes Al diffusion layer <NUM>, AIN layer <NUM>, and AlGaN layer 104A, and has a maximum point of the Al composition ratio distribution at first position <NUM>. The lower surface of Al diffusion layer <NUM> on the substrate <NUM> side becomes the hetero-interface.

Two-dimensional electron gas that is highly concentrated is generated on the channel layer <NUM> side of the hetero interface between barrier layer <NUM> and channel layer <NUM>, and a channel of two-dimensional electron gas layer <NUM> is formed.

Next, as illustrated in <FIG>, insulating layer <NUM> including SiN and having a thickness of <NUM> is deposited on barrier layer <NUM> using a plasma chemical vapor deposition (CVD) method, and then resist <NUM> is applied to the region where recess <NUM> is to be formed, followed by patterning of resist <NUM> using a lithography method. Next, an opening is formed in insulating layer <NUM>, using a wet etching method, such that barrier layer <NUM> is exposed. In addition, using the wet etching method, a side etch is provided in insulating layer <NUM> to form an opening, by causing the side surface of insulating layer <NUM> to be recessed inwardly relative to the side surface of resist <NUM> and positioned under resist <NUM>. It should be noted that, although the wet etching method is used according to the present embodiment, a chemical dry etching method may be used to define an opening in insulating layer <NUM>. In addition, insulating layer <NUM> may be SiO<NUM>, SiON, or SiCN.

Next, as illustrated in <FIG>, barrier layer <NUM> and channel layer <NUM> are partially removed by performing etching processing with Cl<NUM> gas, using an inductively coupled plasma (ICP) dry etching device with resist <NUM> as a mask. In this manner, fourth position <NUM> is formed at the edge portion of the bottom surface of the recess. In a plan view, fourth position <NUM> corresponds to third intersection line <NUM> as illustrated in column (a) of <FIG>. At this time, crystal defects are generated on the surface of barrier layer <NUM> and channel layer <NUM> exposed by the dry etch processing, and high resistance layer <NUM> is formed. In the first direction, the distance between first position <NUM> and the bottom position of recess <NUM> is <NUM> according to the present embodiment. In this way, it is possible to inhibit an increase in resistance of high resistance layer <NUM> by reducing the dry etching time during the formation of recess <NUM>. In addition, in the first direction, the distance between first position <NUM> and the bottom position of recess <NUM> may be greater than or equal to <NUM> and less than or equal to <NUM>. The side surface of insulating layer <NUM> is caused to be recessed inwardly relative to the side surface of resist <NUM> during the wet etching, and thus is positioned under resist <NUM>. As a result, the side surface of insulating layer <NUM> is protected by resist <NUM>. For that reason, the top and side surfaces of insulating layer <NUM> are not subject to loss due to dry etching. Therefore, during the heat treatment to form an ohmic contact, it is possible to reduce the interdiffusion between ohmic electrode <NUM> and insulating layer <NUM>.

It should be noted that, although recess <NUM> was formed using resist <NUM> as a mask in the present embodiment, recess <NUM> may be formed using insulating layer <NUM> as a mask after removing resist <NUM>.

As a specific example of the dry etch processing, for example, plasma processing by the ICP dry etching device is described according to the present embodiment. However, plasma processing by a capacitively coupled plasma (CCP) or an electron cyclotron resonance (ECR) dry etching device may be used.

The etching processing using the ICP dry etching device is performed, for example, by introducing CL<NUM> gas at a gas flow rate of <NUM> sccm to <NUM> sccm, using Cl<NUM> as a gas feedstock. At this time, in addition to Cl<NUM> gas, SiH<NUM> as a material containing silicon (Si) and/or SiCl<NUM>, BCl<NUM>, or CCl as a material containing chlorine may be added. In addition, Ar (Argon) or He (Helium) that are inert gas may be introduced to dilute Cl<NUM> gas. The setting conditions for the etching processing are, for example, <NUM> Pa to <NUM> Pa for the pressure of an etching process atmosphere, <NUM> W to <NUM> W for the power applied to an upper electrode by the <NUM> power supply, <NUM> W to <NUM> W for the power applied to a lower electrode by the <NUM> power supply, and <NUM> degrees Celsius to <NUM> degrees Celsius for the temperature of the substrate.

Next, as illustrated in <FIG>, resist <NUM> is removed using a resist removal solution, the polymer is removed using a polymer cleaning solution, and then channel layer <NUM> and barrier layer <NUM> exposed to the side surface of recess <NUM> are subjected to wet etching using an alkaline chemical solution with a pH value of <NUM> to <NUM> and a temperature of greater than or equal to <NUM> degrees Celsius, only in a side-surface direction with barrier layer <NUM> being in high selectivity relative to channel layer <NUM>. In this manner, in cross-sectional view, first inclined surface <NUM> including first position <NUM> and second inclined surface <NUM> are formed in barrier layer <NUM>, and third inclined surface <NUM> is formed in channel layer <NUM>. As a result, as illustrated in column (b) of <FIG>, in cross-sectional view, second position <NUM> at which first inclined surface <NUM> formed intersects second inclined surface <NUM> formed and third position <NUM> at which second inclined surface <NUM> formed intersects third inclined surface <NUM> formed are formed. Second position <NUM> and third position <NUM> in the cross-sectional view correspond to first intersection line <NUM> and second intersection line <NUM>, respectively, in the plan view. At this time, second position <NUM> is located below first position <NUM>. The angles of first inclined surface <NUM>, second inclined surface <NUM>, and third inclined surface <NUM> with respect to the surface of substrate <NUM> are formed such that the angle of first inclined surface <NUM> is <NUM> degrees, the angle of second inclined surface <NUM> is <NUM> degrees, and the angle of third inclined surface <NUM> is <NUM> degrees, for example.

In addition, since the wet etch processing removes at least a portion of barrier layer <NUM> to form first inclined surface <NUM> and second inclined surface <NUM>, high resistance layer <NUM> on first inclined surface <NUM> and second inclined surface <NUM> is at least partially removed. Since at least a portion of the surface of barrier layer <NUM> where gate electrode <NUM> is formed is covered by insulating layer <NUM>, it is possible to inhibit an increase of crystal defects caused by an alkaline chemical solution in barrier layer <NUM> under gate electrode <NUM>.

In addition, as illustrated in column (a) of <FIG>, dislocations <NUM> are present in barrier layer <NUM>. As illustrated in column (b) of <FIG>, during the wet etch processing, barrier layer <NUM> is etched with dislocations <NUM> as starting points, and a plurality of recess portions <NUM> each including a curve are irregularly formed in barrier layer <NUM>. The angle of first inclined surface <NUM> to the surface of substrate <NUM> in recess portions <NUM> is less than <NUM> degrees, and the depth of recess portions <NUM> in the second direction is <NUM> to <NUM>. It should be noted that the width of recess portions <NUM> may be <NUM> to <NUM> in the third direction. In addition, there may be three or more recess portions <NUM> that are arranged so as to be spaced apart from each other with an interval of <NUM> to <NUM> in the third direction, with a pitch of <NUM> to <NUM>.

Here, the reason why first inclined surface <NUM>, second inclined surface <NUM>, and third inclined surface <NUM> are formed by etching barrier layer <NUM> only in the side-surface direction with barrier layer <NUM> being in high selectivity relative to channel layer <NUM>, using an alkaline chemical solution will be described. The etching of AlGaN using an alkaline chemical solution involves crystal orientation dependency and is difficult to etch from the top surface, but can be done from the side surface.

More specifically, in etching of AlGaN using an alkaline chemical solution, since AlGaN has a hexagonal dense structure, the polar plane includes Group III Al or Ga, and thus the etching rate significantly slows down. Meanwhile, the side surface is a semi-polar plane, and thus can be etched at a certain rate.

Next, when the alkaline chemical solution has a pH value of <NUM> to <NUM> and a temperature of greater than or equal to <NUM> degrees Celsius, GaN that contains no Al is not etched, and thus the etching rate gradually increases as the Al content of AlGaN increases.

Accordingly, it is possible to etch only the side surface of barrier layer <NUM> that contains Al without etching channel layer <NUM> that contains no Al, and AIN layer <NUM> that includes first position <NUM> that is a maximum point in the Al composition ratio distribution in barrier layer <NUM> is etched the most.

As a result, first inclined surface <NUM>, second inclined surface <NUM>, and third inclined surface <NUM> are formed with high precision. In addition, since Al diffusion layer <NUM> on the substrate side is at least partially etched, second position <NUM> is located below first position <NUM>.

The following describes the relationship between the angles of first inclined surface <NUM>, second inclined surface <NUM>, and third inclined surface <NUM> to the surface of substrate <NUM>. First, the angle of second inclined surface <NUM> to the surface of substrate <NUM> is smaller than the angle of first inclined surface <NUM> to the surface of substrate <NUM>. The angle of second inclined surface <NUM> to the surface of the substrate is smaller than the angle of third inclined surface <NUM> to the surface of substrate <NUM>. The angle of third inclined surface <NUM> to the surface of substrate <NUM> is smaller than the angle of first inclined surface <NUM> to the surface of substrate <NUM>. In addition, the angle of first inclined surface <NUM> to the surface of substrate <NUM> is less than <NUM> degrees. In addition, it is better that the angle of second inclined surface <NUM> to the surface of the substrate is smaller than or equal to <NUM> degrees. According to the above-described configuration, it is possible to increase the contact area between ohmic electrode <NUM> and two-dimensional electron gas layer <NUM>, thereby enabling further reduction in the resistance of the ohmic contact.

It should be noted that, after forming recess <NUM>, barrier layer <NUM> and channel layer <NUM> on the surface of recess <NUM> may be made n-type by plasma processing including SiCl<NUM> gas. In addition, after forming recess <NUM>, a portion of barrier layer <NUM> and a portion of channel layer <NUM> may be made n-type by ion implantation device in a predetermined region.

As a specific example of an alkaline chemical solution, for example, etching processing using ammonium-hydrogen peroxide mixture (APM) is explained according to the present embodiment. However, etching processing using tetramethyl ammonium hydroxide (TMAH), kalium hydroxide (KOH), etc. may be performed. The setting of the etching processing using the APM includes, for example, the ratio of HN<NUM>OH:H<NUM>O<NUM>:H<NUM>O = <NUM>:<NUM>:<NUM>, and the temperature of the chemical solution is <NUM> degrees Celsius. Here, the pH value of the alkaline chemical solution may be <NUM> to <NUM>, and the temperature of the chemical solution may be greater than or equal to <NUM> degrees Celsius. According to the above-described configuration, it is possible to etch barrier layer <NUM> only on the side surface with barrier layer <NUM> being in high selectivity relative to channel layer <NUM>.

Next, as illustrated in <FIG>, after pre-cleaning with hydrochloric acid, a Ti film and an Al film are sequentially deposited by the sputtering method, and then the lithography method and the dry etching method are applied in sequence for patterning the laminated film of the Ti film and the Al film, thereby forming ohmic electrode <NUM> that has a predetermined shape on recess <NUM>.

It should be noted that ohmic electrode <NUM> that has a predetermined shape may be formed by using a lift-off method to sequentially deposit the Ti film and the Al film with a vapor-deposition technique instead of the sputtering method. In addition, ohmic electrode <NUM> is not limited to a combination of Ti and Al, but may be a single layer electrode film including a single metal such as Ti, Au, Ta, Al, Mo, Hf, Zr, Au, or Cu, or a multilayer electrode film including a combination of two or more of these metals.

Here, since the angle of first inclined surface <NUM> to the surface of substrate <NUM> is less than <NUM> degrees, it is possible to implant metal atoms to second inclined surface <NUM> when ohmic electrode <NUM> is deposited by sputtering. As a result, it is possible to further reduce the resistance of the ohmic contact. In addition, when ohmic electrode <NUM> is deposited by sputtering, it is possible to deposit it with good coverage. As a result, it is possible to stably reduce the resistance of the ohmic contact.

Next, an ohmic contact between ohmic electrode <NUM> and two-dimensional electron gas layer <NUM> is formed by performing a heat treatment at <NUM> degrees Celsius for one minute under a nitrogen atmosphere. Here, second inclined surface <NUM> is a semi-polar plane of the semiconductor crystal that constitutes barrier layer <NUM>, which makes it easier to form nitrogen holes and to make it n-type.

It should be noted that, although the temperature of the heat treatment is <NUM> degrees Celsius according to the present embodiment, the temperature of the heat treatment may be less than or equal to <NUM> degrees Celsius, or greater than or equal to <NUM> degrees Celsius and less than <NUM> degrees Celsius.

Next, as illustrated in <FIG>, gate electrode <NUM> is formed above barrier layer <NUM> by patterning the laminated films of the Ni film and the Au film by applying the lithography method and the dry etching method in sequence after sequentially depositing the Ni film and the Au film by the sputtering method. It should be noted that gate electrode <NUM> that has a predetermined shape may be formed by using the lift-off method to sequentially deposit the Ni film and the Au film with a vapor-deposition technique instead of the sputtering method. In addition, the extending direction of gate electrode <NUM> in a plan view of substrate <NUM> is in a <<NUM>-<NUM>> direction of a semiconductor crystal configuring channel layer <NUM>.

By going through the series of processes as described above, manufacturing of semiconductor device <NUM> that has the configuration illustrated in <FIG> is completed.

In semiconductor device <NUM> formed as described above, second position <NUM> is lower than first position <NUM> at which the Al composition ratio distribution has a maximum point, and thus it is possible to make barrier layer <NUM> on second inclined surface <NUM> quite thin. Therefore, ohmic electrode <NUM> and two-dimensional electron gas layer <NUM> can be in ohmic contact with each other via second inclined surface <NUM>, and thus it is possible to increase the contact area. In addition, since second inclined surface <NUM> is formed by wet etching, high resistance layer <NUM> formed by dry etching is at least partially removed. According to the above-described configuration, in second inclined surface <NUM> with a large contact area, the distance between two-dimensional electron gas layer <NUM> and ohmic electrode <NUM> is short and there is no resistance component, and thus it is possible to further reduce the resistance of the ohmic contact.

In regard to semiconductor device <NUM> manufactured using the manufacturing method according to the present embodiment, <FIG> illustrates a cross-sectional transmission electron microscope (TEM) photograph showing the cross-section in proximity to the ohmic electrode in the configuration example illustrated in <FIG>. As illustrated in <FIG>, second position <NUM> is lower than first position <NUM> at which the Al composition ratio distribution has a maximum point, and the angles of first inclined surface <NUM>, second inclined surface <NUM>, and third inclined surface <NUM> to the surface of substrate <NUM> are <NUM> degrees, <NUM> degrees, and <NUM> degrees, respectively.

Next, in regard to semiconductor device <NUM> manufactured using the manufacturing method according to the present embodiment, <FIG> illustrates a scanning Electron microscope (SEM) photograph showing the plane of the recess portion after the wet etch processing in the configuration example illustrated in column (b) of <FIG>. As illustrated in <FIG>, it can be seen that a plurality of recess portions <NUM> each including a curve are irregularly provided in barrier layer <NUM>.

Although the semiconductor device according to the present disclosure has been described based on the exemplary embodiment thus far, the present disclosure is not limited to the embodiment described above.

For example, aside from the above, forms obtained by various modifications to the exemplary embodiment that can be conceived by a person of skill in the art as well as forms realized by arbitrarily combining structural components and functions in the exemplary embodiment which are within the scope of the essence of the present disclosure are included in the present disclosure.

Claim 1:
A semiconductor device (<NUM>) comprising:
a substrate (<NUM>);
a channel layer (<NUM>) disposed above the substrate (<NUM>), the channel layer (<NUM>) being a group III nitride not containing Al;
a barrier layer (<NUM>) disposed above the channel layer (<NUM>), the barrier layer (<NUM>) being a group III nitride containing Al;
a gate electrode (<NUM>) joined to the barrier layer (<NUM>);
a recess (<NUM>) obtainable by removing at least a portion of the barrier layer (<NUM>) from a surface of a laminated semiconductor including the channel layer (<NUM>) and the barrier layer (<NUM>);
an ohmic electrode (<NUM>) disposed in the recess (<NUM>), the ohmic electrode (<NUM>) being in ohmic contact with a two-dimensional electron gas layer (<NUM>) generated in the channel layer (<NUM>), and
in a first direction perpendicular to a surface of the substrate (<NUM>), a first inclined surface (<NUM>) of the barrier layer (<NUM>), the first inclined surface (<NUM>) including a first position (<NUM>) and being in contact with the ohmic electrode (<NUM>);
characterized in that
an Al composition ratio distribution of the barrier layer (<NUM>) in the first direction has a maximum point at the first position (<NUM>),
the semiconductor device (<NUM>) comprises, in the first direction:
a second inclined surface (<NUM>) of the barrier layer (<NUM>), the second inclined surface (<NUM>) intersecting the first inclined surface (<NUM>) at a first intersection line (<NUM>) on a lower side of the first inclined surface (<NUM>) and being in contact with the ohmic electrode (<NUM>),
an angle of the second inclined surface (<NUM>) to the surface of the substrate (<NUM>) is smaller than an angle of the first inclined surface (<NUM>) to the surface of the substrate (<NUM>),
a second position (<NUM>) that is a position of the first intersection line (<NUM>) in the first direction is lower than the first position (<NUM>) and
an extending direction of the gate electrode (<NUM>) along its longest dimension in a plan view of the substrate (<NUM>) is a <<NUM>-<NUM>> direction of a semiconductor crystal configuring the channel layer (<NUM>).