Patent Description:
The present application relates generally to switched electrical devices. More particularly, the present application is directed to circuit interrupting devices, such as ground fault circuit interrupter (GFCI) devices, that switch to a "tripped" or unlatched state from a "reset" or latched state when one or more conditions are detected. Such devices consistent with embodiments of the application disclosed herein are more reliable than previously known GFCI devices.

To be commercially sold in the United States a GFCI device must conform to standards established by the Underwriter's Laboratory (UL) in conjunction with industry-leading manufacturers as well as other industry members, such as various safety groups. One UL standard covering GFCI devices is UL-<NUM> (http://ulstandards. com/standard/?id=<NUM>), entitled "Standard for Safety - Ground Fault Circuit Interrupters. " UL-<NUM> applies to Class A, single-phase and three-phase GFCIs intended for protection of personnel and includes minimum requirements for the function, constructions, performance, and markings of such GFCI devices. UL-<NUM> requires, among other things, specific fault current levels and response timing requirements at which the GFCI device should trip. Typically, GFCIs are required to trip when a ground fault having a level of approximately four-milliamps (mA) to approximately six mA is detected. Additionally, when a high resistance ground fault is applied to the device, UL-<NUM> requires that the device should trip and prevent current from being delivered to the load in accordance with the equation, T=(<NUM>/I)<NUM>, where T refers to time and is expressed in seconds (s) and I refers to electrical current and is expressed in mA. Thus, for example, in the case of a 5mA fault, the device must detect the fault and trip in <NUM> or less.

Typically, GFCI devices include a TEST button, which when pressed, actuates a simulated ground fault outside the sense core from the load hot to the line neutral conductors. If the device is functioning properly, the simulated fault is detected and the device will trip (i.e., a mechanical interrupter is actuated to open the current path connecting the line side of the device to the load side of the device). Studies performed by industry safety groups have indicated that most users do not regularly test their GFCI device (i.e., by manually pressing the TEST button). As a result, unsafe conditions may occur. Therefore, many GFCI devices are now operable to perform self-tests and auto-monitor themselves without the need for human intervention. Such self-tests and auto-monitoring operations must not interfere with the primary function of the device (i.e., supply power and trip when an actual fault is encountered). Typically, such self-tests are operated with the assumption the GFCI device is receiving an AC input having a constant <NUM> frequency. However, when the frequency of the AC input (e.g., AC input from a power generator, invertor applications, and the like) is not constant, such self-tests may be unreliable and may also result in unnecessary trips of the GFCI device. Furthermore, the AC input may include noise, which further causes unreliability in the self-tests and unnecessary trips of the GFCI device.

<CIT>discloses a wiring device having the pre-characterizing features of claims <NUM> and <NUM>.

Thus, to cure the deficiencies of known GFCI devices, in accordance with a first aspect of the present invention a wiring device is provided having the characterizing features of claim <NUM>. Optional preferred features are defined in claims <NUM> to <NUM>.

In accordance with a second aspect of the present invention there is provided a method of performing a self-test of a wiring device having the characterizing features of claim <NUM>. Optional, preferred features are defined in claims <NUM> to <NUM>.

Other aspects of the application will become apparent by consideration of the detailed description and accompanying drawings.

Before any embodiments of the application are explained in detail, it is to be understood that the application is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the following drawings. The application is capable of other embodiments and of being practiced or of being carried out in various ways.

<FIG> illustrates a perspective view of a GFCI device, or GFCI receptacle, <NUM> according to some embodiments of the application. The GFCI receptacle <NUM> includes a front cover <NUM> having a duplex outlet face <NUM> with a phase opening <NUM>, a neutral opening <NUM>, and a ground opening <NUM>. The face <NUM> further has opening <NUM>, accommodating a RESET button <NUM>, an adjacent opening <NUM>, accommodating a TEST button <NUM>, and six respective circular openings <NUM>-<NUM>. In some embodiments, openings <NUM> and <NUM> accommodate two respective indicators, such as but not limited to, various colored light-emitting diodes (LEDs). In some embodiments, openings <NUM> and <NUM> accommodate respective bright LEDs used, for example, as a nightlight. In some embodiments, opening <NUM> accommodates a photoconductive photocell used, for example, to control the nightlight LEDs. In some embodiments, opening <NUM> provides access to a set screw for adjusting a photocell device or a buzzer (e.g., buzzer <NUM> described in more detail below) in accordance with this, as well as other, embodiments.

The GFCI receptacle <NUM> further includes a rear cover <NUM> secured to the front cover <NUM> by eight fasteners <NUM> (four fasteners <NUM> are shown in <FIG>, while the other four fasteners <NUM> are obstructed from view). In some embodiments, the fasteners <NUM> include a barbed post <NUM> on the front cover <NUM> and a corresponding resilient hoop <NUM> on the rear cover <NUM>, similar to that which is described in detail in <CIT>, the entire contents of which are incorporated herein by reference for all that is taught. A ground yoke/bridge assembly <NUM> includes standard mounting ears <NUM> protruding from the ends of the GFCI receptacle <NUM>.

<FIG> illustrates a perspective view of the GFCI receptacle <NUM> with the front cover <NUM> removed to expose manifold <NUM>. Manifold <NUM> provides support for a printed circuit board <NUM> and the yoke/bridge assembly <NUM>. According to one embodiment, manifold <NUM> includes four dovetail interconnects <NUM> that mate with corresponding cavities <NUM> along an upper edge of the rear cover <NUM>. One dovetail-cavity pair is provided on each of the four sides of manifold <NUM> and rear cover <NUM>, respectively.

<FIG> is a side elevation view of a core assembly <NUM> according to some embodiments. Core assembly <NUM> includes a circuit board <NUM> that supports most of the working components of the GFCI receptacle <NUM>, including the circuit shown in <FIG>, which are referred to collectively herein as <FIG>, as well as a sense transformer <NUM> (illustrated in <FIG>) and a grounded neutral transformer <NUM> (illustrated in <FIG>). Line contact arms <NUM>, <NUM> pass through transformers <NUM>, <NUM> with an insulating separator <NUM> there between. Line contact arms <NUM>, <NUM> are cantilevered, their respective distal ends carrying phase and neutral line contacts <NUM>, <NUM>. Load contact arms <NUM>, <NUM> are also cantilevered with their respective distal ends carrying phase and neutral load contacts <NUM>, <NUM>. The resiliency of the cantilevered contact arms biases the line contacts <NUM>, <NUM> and load contacts <NUM>, <NUM> away from each other. Load contact arms <NUM>, <NUM> rest on a movable contact carriage <NUM>, made of insulating (preferably thermoplastic) material.

<FIG>) is an electrical schematic of a circuit <NUM> of the GFCI receptacle <NUM> in accordance with some embodiments of the application. The GFCI circuit <NUM> includes a phase line terminal <NUM> and a neutral line terminal <NUM> for electrical connection to a power source (not shown). The phase line terminal <NUM> and the neutral line terminal <NUM> are configured to receive an input voltage from the power source. In some embodiments, the input voltage is approximately 120V having a frequency of approximately <NUM>. In other embodiments, the input voltage is within a range of approximately 60V to approximately 180V having a frequency of approximately <NUM> to approximately <NUM>. By way of example, the phase line terminal <NUM> and the neutral line terminal <NUM> may correspond to input terminals of the GFCI receptacle <NUM>.

The phase line terminal <NUM> and the neutral line terminal <NUM> are respectively connected to phase line conductor <NUM> and neutral line conductor <NUM>. Phase line conductor <NUM> and neutral line conductor <NUM> each pass through sense transformer <NUM> and grounded neutral transformer <NUM>. Phase line conductor <NUM> and neutral line conductor <NUM> are further releasably connected to face and load conductors <NUM>, <NUM>. For example, the phase line conductor <NUM> and neutral line conductor <NUM> may be releasably connected to face and load conductors <NUM>, <NUM> via line contacts <NUM>, <NUM>, load contacts <NUM>, <NUM>, and face contacts, discussed above with respect to <FIG>. GFCI circuit <NUM> may also include optional phase and load neutral terminals, which electrically connect to a downstream load (not shown), such as one or more additional receptacle devices.

The GFCI circuit <NUM> includes a detection, or fault detection, circuit <NUM> and a self-test, or testing, circuit <NUM>. The detection circuit <NUM> includes, among other things, the sense transformer <NUM>, the ground neutral transformer <NUM>, a detection controller <NUM>, and an interrupting device <NUM> (e.g., a solenoid <NUM> and a solenoid switch <NUM>). The detection controller <NUM> is configured to detect one or more fault conditions, and place the GFCI receptacle <NUM> in the tripped state when the one or more fault conditions are detected. In some embodiments, the detection controller <NUM> is a well-known integrated circuit device, such as but not limited to, a <NUM> device. In some embodiments, the detection controller <NUM> is an RV <NUM> device made by Fairchild Semiconductor Corporation.

The detection controller <NUM> receives electrical signals from various other components of the GFCI circuit <NUM>, including the sense transformer <NUM> and the ground neutral transformer <NUM>, and detects one or more fault conditions, such as a real fault, a simulated fault or self-test ground fault, and a real or simulated grounded neutral fault. In operation, when there is a current imbalance in line conductors <NUM>, <NUM> a net current flows through transformers <NUM>, <NUM>, causing a magnetic flux to be created about at least the sense transformer <NUM>. The magnetic flux results in electrical current being induced on conductor <NUM>. Conductor <NUM> is wound around sense transformer <NUM>, with respective ends of conductor <NUM> being connected to V-REF and INPUT pins of the detection controller <NUM>. The induced current on conductor <NUM> causes a voltage difference between the V-REF and INPUT pins. When the voltage difference exceeds a predetermined threshold, the detection controller <NUM> outputs a control signal. For example, the detection controller <NUM> outputs a control signal from the SCR_OUT pin.

The current imbalance on line conductors <NUM>, <NUM> results from either a real ground fault, a simulated ground fault, or a self-test ground fault. A simulated ground fault is generated when test switch <NUM> closes, which occurs when TEST button <NUM> (<FIG>) is pressed. As described in further detail below, a self-test ground fault occurs when the self-test circuit <NUM> initiates a self-test sequence.

According to the present embodiments, when test switch <NUM> closes, at least some of the current flowing in line conductors <NUM>, <NUM> and face and load conductors <NUM>, <NUM> is diverted around sense transformer <NUM>, through resistor R1, and back to neutral line conductor <NUM>. By diverting the current in such a manner, an imbalance is created in the current flowing through the phase line conductor <NUM> and the current flowing through the neutral line conductor <NUM>. As stated above, such a current imbalance causes a magnetic flux to be created about sense transformer <NUM>, as well as a voltage difference present at the V-REF and INPUT pins that exceeds the predetermined threshold. In response, the detection controller <NUM> outputs the control signal from the SCR_OUT pin.

The control signal output from the SCR_OUT pin may be used to control the solenoid switch, or switch, <NUM>. In some embodiment, the solenoid switch <NUM> is a silicon controlled rectifier (SCR) switch having a gate, an anode, and a cathode. In such an embodiment, the control signal is received at the gate of the switch <NUM>. When the control signal is received at the gate of the solenoid switch <NUM>, the solenoid switch <NUM> is activated and current is allowed to flow between the anode and the cathode of the solenoid switch <NUM>. When the solenoid switch <NUM> is activated, current flows from phase line conductor <NUM> through the solenoid <NUM>. When current flows through solenoid <NUM>, a magnetic field is generated that moves an armature within solenoid <NUM>. When the solenoid armature moves, it unlatches a contact carriage (e.g., movable contact carriage <NUM> of <FIG>) and the carriage drops under a natural bias of line conductors <NUM>, <NUM> away from the face and load conductors <NUM>, <NUM>. The GFCI receptacle <NUM> is now in the tripped condition, as a result of the successful manually simulated ground fault. When in the tripped condition, the GFCI receptacle <NUM> will not deliver power to a load until it is reset.

Manual testing via the reset operation may also be performed on the GFCI receptacle <NUM> by pressing the RESET button <NUM> (<FIG>). Pressing the RESET button <NUM> closes reset switch <NUM>. By closing reset switch <NUM>, a voltage supply output pin VS of the detection controller <NUM> is electrically connected to the solenoid switch <NUM>. Thus the solenoid switch <NUM> receives a voltage from the VS pin, the solenoid switch <NUM> activates in a similar fashion as when receiving the control signal from the SCR_OUT pin. Likewise, similar to the simulated ground fault discussed above, when solenoid switch <NUM> is activated, solenoid <NUM> is activated.

However, when reset switch <NUM> closes, the GFCI receptacle <NUM> is most likely already in the tripped condition (i.e., the contacts of the line, face, and load contacts are electrically isolated from each other). Therefore, the RESET button <NUM> is pressed to "re-latch" the contact carriage and bring the line, face, and load contacts back into electrical contact after the GFCI receptacle <NUM> has been tripped.

The self-test circuit <NUM> is configured to perform self-test and auto-monitoring sequences of the GFCI receptacle <NUM>. The self-test circuit <NUM> includes, among other things, a self-test controller <NUM>, a self-test switch <NUM>, an opto-isolator <NUM>, and an indicator <NUM>.

As explained in greater detail below, the self-test controller <NUM> is programmed to implement one or more self-test and auto-monitoring routines, including but not limited to, frequency detection, a ground fault detection self-test, and a solenoid self-test. In some embodiments, the self-test controller <NUM> is a well-known integrated circuit device, such as but not limited to, a Microchip microcontroller such as, but not limited to, a PIC12F675.

As discussed in more detail below, the self-test controller <NUM> is operable to perform a ground fault detection self-test and a solenoid self-test of the GFCI receptacle <NUM>. In some embodiments, before the ground fault detection self-test or the solenoid self-test is performed, the self-test controller <NUM> measures a frequency of the input voltage received by the GFCI receptacle <NUM>. The frequency is measured by counting the number of positive zero crossings of the input voltage over a predetermined time-period (e.g., a two second time period). In order to determine the number of positive zero crossings over the predetermined time-period, the self-test controller <NUM> monitors node <NUM> via the GP2/INT pin. The self-test controller <NUM> then divides the number of positive zero crossings by the predetermined time-period (e.g., two) to calculate the frequency.

In some embodiments, if the frequency is outside of a predetermined range (e.g., approximately <NUM> to approximately <NUM>), the self-test controller <NUM> will hold, and will not perform the ground fault detection self-test and/or the solenoid self-test until the measured frequency is within the predetermined range. In other embodiments, if the frequency is outside of the predetermined range, the self-test controller <NUM> post-pones the ground fault detection self-test and/or the solenoid self-test until the frequency is within the predetermined range. In some embodiments, if the frequency is determined to be approximately zero Hz, the frequency is remeasured, for example but not limited to, two-seconds later. Re-measurements will occur until the frequency is not equal to zero Hz, or if the frequency is measured to be zero Hz a predetermined amount of additional times in a row. In some embodiments, if the frequency is measured to be equal to zero Hz eight consecutive times, the GFCI receptacle <NUM> end-of-life (EOL) will be determined.

In some embodiments, the self-test controller <NUM> performs a filtering operation when determining the frequency. The filtering operation is performed to block out noise of the input voltage. In some embodiments, a low-pass filtering operation is performed. In some embodiments, the frequency is sampled at a predetermined rate (e.g., every <NUM>).

The self-test controller <NUM> is operable to perform a ground fault detection self-test. In some embodiments, the ground fault detection self-test is performed within a predetermined time of the GFCI receptacle <NUM> receiving power (e.g., approximately five seconds). The ground fault detection self-test is performed to confirm that the GFCI receptacle <NUM>, and more specifically the detection circuit <NUM> of the GFCI circuit <NUM>, correctly detects the one or more fault conditions. The ground fault detection self-test is performed at predetermined time intervals (e.g., once every minute). If the ground fault detection self-test is failed, a retest is performed, for example but not limited to, two-seconds later. Retests will occur until the ground fault detection self-test is passed or seven additional failures have occurred. If eight consecutive fails occur, the GFCI receptacle <NUM> EOL is determined. In other embodiments, EOL may be determined if more or less than eight consecutive fails occur. Yet, in other embodiments, EOL may be determined if more or less than eight non-consecutive fails occur.

In some embodiments, to perform the ground fault detection self-test, the self-test controller <NUM> initially measures a frequency of the input voltage as described above. After calculating the frequency of the input voltage, the self-test controller <NUM> outputs a ground fault signal at a predetermined period (e.g., <NUM>/<NUM>th) of the frequency of the input voltage after the input voltage has crossed the positive zero (i.e., during the negative half-cycle of the input voltage). In other embodiments, the self-test controller <NUM> may output the ground fault signal at any period of the frequency of the input voltage. The ground fault signal is output from the GP0 pin to the self-test switch <NUM>. In some embodiments, the self-test switch <NUM> is a transistor, such as but not limited to a BJT semiconductor. In some embodiments, the ground fault signal is output for a predetermined duration (e.g., approximately eight-milliseconds) or until a predetermined voltage (e.g., approximately 190mV) is measured at node <NUM> via the GP1 pin of the self-test controller <NUM>.

Upon receiving the ground fault signal, the self-test switch <NUM> is activated. When the self-test switch <NUM> is activated, current is allowed to flow, through a rectifier <NUM>, on conductor <NUM>. As illustrated, current flowing on conductor <NUM> will flow through sense transformer <NUM>. Similar to the manually simulated ground fault discussed above, in normal operation, the current flowing through sense transformer <NUM> will cause a magnetic flux to be created about the sense transformer <NUM>. The magnetic flux results in electrical current being induced on conductor <NUM>. The induced current on conductor <NUM> causes a voltage difference between the V-REF and INPUT pins. When the voltage difference exceeds a predetermined threshold, the detection controller <NUM> outputs the control signal from the SCR_OUT pin. The control signal may then be detected at node <NUM> via pin GP1 of the self-test controller <NUM>. Once the control signal exceed the predetermined voltage (e.g., 190mV), the ground fault signal is deactivated and it is determined by the self-test controller <NUM> that the GFCI receptacle <NUM> has passed the ground fault detection self-test. If the control signal does not exceed the predetermined voltage (e.g., approximately 190mV) within the predetermined duration (e.g., approximately eight-milliseconds) discussed above, the self-test controller <NUM> determines that the GFCI receptacle <NUM> has failed, and the GFCI receptacle <NUM> will be retested in a similar fashion as discussed above.

The self-test controller <NUM> is further operable to perform a solenoid self-test. In some embodiments, the solenoid self-test is performed within a predetermined time of the GFCI receptacle <NUM> receiving power (e.g., approximately five seconds). The solenoid self-test confirms that the GFCI receptacle <NUM>, and more specifically the solenoid <NUM>, is operating correctly. The solenoid self-test may also be performed at a predetermined period (e.g., once every minute). In some embodiments, the solenoid self-test is performed at a predetermined time period (e.g., approximately thirty-seconds) after the ground fault self-test is performed. In such an embodiment, the ground fault self-test or the solenoid self-test occurs every thirty-seconds. Similar to the ground fault self-test, if the solenoid self-test is failed, a retest is performed, for example but not limited to, two-seconds later. Retests will occur until the solenoid self-test is passed or seven additional failures have occurred. If eight consecutive fails occur, the GFCI receptacle <NUM> EOL will be determined. In other embodiments, EOL may be determined if more or less than eight consecutive fails occur. Yet, in other embodiments, EOL may be determined if more or less than eight non-consecutive fails occur.

To perform the solenoid self-test, the self-test controller <NUM> initially measures the frequency of the input voltage as described above. After calculating the frequency of the input voltage, the self-test controller <NUM> outputs a solenoid test signal at a second predetermined period (e.g., <NUM>/<NUM>th) of the frequency of the input voltage after the input voltage has crossed the positive zero (i.e., during the negative half-cycle of the input voltage). However, in some embodiments, the solenoid self-test may be performed at the same predetermined period as the ground fault detection self-test.

The solenoid test signal is output from the GP1 pin and is received by the solenoid switch <NUM> (e.g., at the gate of the solenoid switch <NUM>). The solenoid test signal activates the solenoid switch <NUM>, thus allowing current to flow through the solenoid <NUM>. Current flowing through the solenoid <NUM> may then be detected at node <NUM> via the GP2/INT pin of the self-test controller <NUM>. If current is detected, the solenoid self-test has been passed and output of the solenoid test signal is stopped. If current is not detected, the solenoid self-test has failed. In such an embodiment, the GFCI receptacle <NUM> will not be tripped during the solenoid self-test because the solenoid self-test is performed during the negative half-cycle of the input voltage.

The self-test controller <NUM> is further operable to determine when the GFCI receptacle <NUM> is in a tripped condition and activate indicator <NUM> (e.g., a light-emitting diode (LED) located in opening <NUM> or <NUM> of <FIG>) when in the tripped condition. In operation, the self-test controller <NUM> monitors activation of the opto-isolator <NUM> via the GP4 pin. The opto-isolator <NUM> is in an active state when current is present on conductors <NUM>, <NUM>. When the opto-isolator <NUM> is active, the self-test controller <NUM> deactivates the indicator <NUM>. When current is not present on conductors <NUM>, <NUM>, the GFCI receptacle <NUM> is in the tripped condition and the opto-isolator <NUM> is in an inactive state. When the opto-isolator <NUM> is in the inactive state, the self-test controller <NUM> will activate the indicator <NUM> by outputting an activation signal at pin GP5. In some embodiments, the activation signal is output at a predetermined rate (e.g., a rate of <NUM>). In such an embodiment, the predetermined rate is fast enough that the indicator <NUM> appears to be in a constant on-state to the user, while also conserving power.

The self-test controller <NUM> may further includes a buzzer circuit <NUM>. In such an embodiment, the buzzer circuit <NUM> is configured to output a signal (e.g., an auditory signal) when the GFCI receptacle <NUM> is in a tripped condition. The buzzer circuit <NUM> includes, among other things, a buzzer <NUM> and a buzzer switch <NUM>. The buzzer <NUM> is electrically connected to, and configured to receive power from, the phase line terminal <NUM>. The buzzer <NUM> is further connected to ground through the buzzer switch <NUM>. In operation, when the indicator <NUM> is activated (i.e., the activation signal is output from pin GP5), the buzzer switch <NUM> is also activated, thus allowing power to the buzzer and activating the buzzer <NUM>. Similar to the indicator <NUM>, in some embodiments, when activated, the buzzer <NUM>, is switched on and off at a predetermined rate (e.g., a rate of <NUM>). In such an embodiment, the predetermined rate is fast enough that the buzzer <NUM> appears to be in a constant on-state to the user, while also conserving power. In some embodiments, the indicator <NUM> and buzzer <NUM> are disabled when the input voltage crosses a predetermined threshold (for example, a predetermined threshold of approximately 155VAC to approximately 160VAC). In some embodiments the indicator <NUM> and buzzer <NUM> are disabled when the input voltage is above approximately 160VAC and enabled when the input voltage is below approximately 155VAC.

In some embodiments, the buzzer circuit <NUM> further includes rectifier diode XD1; resistors XR2, XR3, and XR4; zener diodes XZ1 and XZ2; and capacitor XC2. In such an embodiment, the rectifier diode XD1 provides a half-wave rectification to the buzzer <NUM>, while the resistors XR2, XR3, and XR4 limit current to the buzzer <NUM>. Additionally, in such an embodiment, Zener diodes XZ1 and XZ2 provide a voltage drop to set the buzzer voltage and capacitor XC2 filters the buzzer voltage.

The self-test controller <NUM> is further operable to deny power to the load and face. In some embodiments, power is denied when EOL is determined. In operation, when EOL is determined, the self-test controller <NUM> outputs an EOL signal from the GP1 pin to the solenoid switch <NUM>. The value of resistor R5 (i.e., the resistor connected between the GP1 pin and the solenoid switch <NUM>) is selectively chosen to ensure that the voltage received by the solenoid switch <NUM> does not reach an "ON" threshold voltage and activate the solenoid switch <NUM>. Thus, the solenoid switch <NUM> is permanently maintained in the OFF position (e.g., deactivated) and the GFCI receptacle <NUM> is not allowed to be reset out of the tripped condition. Such an operation inhibits any further resets (via the RESET button <NUM>) from triggering the solenoid switch <NUM> and thus latching the contacts closed when in the GFCI receptacle <NUM> is in the tripped condition. In some embodiments, when EOL is determined, the indicator <NUM> and the buzzer <NUM> are switched on and off at a second predetermined rate (e.g., <NUM>). In some embodiments, the second predetermined rate causes the user to experience the indicator <NUM> as flashing and the buzzer <NUM> as pulsing on and off.

<FIG> is a flow chart illustrating a method, or operation, <NUM> of the GFCI receptacle <NUM> in accordance with some embodiments of the application. The GFCI receptacle <NUM> initially receives input voltage through the phase line terminal <NUM> and neutral line terminal <NUM> (Block <NUM>). The GFCI receptacle <NUM> determines an input frequency of the input voltage (Block <NUM>). The GFCI receptacle <NUM> determines if the input frequency is within a predetermined frequency range (Block <NUM>). If the input frequency is not within the predetermined frequency range, the GFCI receptacle <NUM> determines if the input frequency is equal to zero (Block <NUM>). If the input frequency is equal to zero, the method <NUM> proceeds directly to Block <NUM>. If the input frequency is not equal to zero, the GFCI receptacle <NUM> waits a predetermined time period (e.g., two-seconds) (Block <NUM>) and then proceeds to Block <NUM> to once again determine the input frequency.

If the input frequency is determined to be within the predetermined frequency, the method <NUM> continues to Block <NUM>. At Block <NUM>, the GFCI receptacle <NUM> determines if there has not been a previous test, or if the previous test performed was the solenoid self-test. If there has not been a previous test, or if the previous test performed was the solenoid self-test, the GFCI receptacle <NUM> will perform the ground fault detection self-test (Block <NUM>). If there was a previous test and it was not the solenoid self-test, the previous test was therefore the ground fault detection self-test, and the GFCI receptacle <NUM> will next perform the solenoid self-test (Block <NUM>). The GFCI receptacle <NUM> then determines if the previous test performed has passed (Block <NUM>). If the previously-performed self-test has passed, a fail count is cleared (Block <NUM>) and the method <NUM> reverts back to Block <NUM>. If the previously-performed self-test did not pass, the fail count is incremented (Block <NUM>). The GFCI receptacle <NUM> next determines if the fail count has surpassed a fail count limit (e.g., seven) (Block <NUM>). If the fail count has surpassed the fail count limit, EOL is determined (Block <NUM>). If the fail count has not surpassed the fail count limit, the GFCI receptacle <NUM> waits a predetermined amount of time (e.g., two-seconds) (Block <NUM>). The method <NUM> then returns to Block <NUM>.

<FIG> is a flow chart illustrating a method <NUM> of the ground fault detection self-test in accordance with some embodiments of the application. The ground fault signal is output from by the self-test controller <NUM> (Block <NUM>). The self-test controller <NUM> determines if a control signal output by the detection controller <NUM> is detected within a predetermined time period after outputting the ground fault signal (Block <NUM>). If the control signal is detected within the predetermined time period, the test is passed (Block <NUM>) and the operation proceeds to Block <NUM> of method <NUM>. If the control signal is not detected, the test is failed (Block <NUM>) and the operation proceeds to Block <NUM> of method <NUM>.

<FIG> is a flow chart illustrating a method <NUM> of the solenoid self-test in accordance with some embodiments of the application. The solenoid test signal is output from by the self-test controller <NUM> (Block <NUM>). The self-test controller <NUM> determines if a solenoid current is detected (Block <NUM>). If the solenoid current is detected, the test is passed (Block <NUM>) and the operation proceeds to Block <NUM> of method <NUM>. If the solenoid current is not detected, the test is failed (Block <NUM>) and the operation proceeds to Block <NUM> of method <NUM>.

Claim 1:
A wiring device comprising:
an interrupting device (<NUM>) electrically connecting one or more line terminals (<NUM>) to one or more load terminals (<NUM>) when the interrupting device (<NUM>) is in a reset condition and disconnecting the line terminals from the load terminals when the interrupting device is in a tripped condition;
a fault detection circuit (<NUM>) configured to detect a fault condition and generate a fault detection signal in response to detecting the fault condition, the fault detection signal being provided to the interrupting device (<NUM>) to place the interrupting device (<NUM>) in the tripped condition; and comprising
a testing circuit (<NUM>) configured to,
determine a frequency of an input voltage at the one or more line terminals (<NUM>),
characterized in that the testing circuit (<NUM>) is further configured to determine whether the frequency of the input voltage is within a predetermined range, and
when the frequency is within the predetermined range, perform a first test of the interrupting device (<NUM>) at a first period of the frequency, and a second test of the fault detection circuit (<NUM>) at a second period of the frequency.