Patent Description:
A datacenter typically houses tens or hundreds of servers for load sharing and redundancy. Such large-scale server networks consume large amounts of electric power which makes electric power distribution a complex and error-prone task. Any manner of monitoring the power delivery and protecting integrity of the servers and the electric infrastructure of the datacenter is desirable.

Notably, the recent development of liquid cooling technologies to provide cooling to electric equipment has brought additional problematics. For example, a failure of the electric connectivity of the equipment may lead to electric current flowing in the cooling liquid, thereby causing electrolysis thereof. This may put the entire equipment at risk in case of presence of shortcut currents.

Solutions for safe distribution of electric power from a power source to an electronic device with reduced electric current is thus desirable.

<CIT> and <CIT> disclose known systems and methods for providing power to electronic devices.

Embodiments and examples of the present technology have been developed based on developers' appreciation of shortcomings associated with the prior art.

In a first broad aspect of the present technology, there is provided a method for providing electric power to an electronic device. The method includes receiving, from a power source and at a monitoring circuit electrically connected to the electronic device, electric power at a corresponding voltage, the electric power being received at a corresponding power input of the monitoring circuit, receiving, at a standby power input of the monitoring circuit, a first standby electric power at a first standby voltage, directing, by the monitoring circuit, the electric power to the electronic device through a corresponding fuse state indicator of the monitoring circuit, the fuse state indicator selectively connecting a corresponding power input to the electronic device and relying on the first standby electric power to operate, the fuse state indicator being configured to generate a fuse state signal indicative of a state thereof that can be selectively an alive state or a failure state, combining, by a logic combiner of the monitoring circuit, the fuse state signal with a signal indicative of a presence of the electric power at the power input of the monitoring circuit to form a main state signal that can be selectively an alive state or a failure state and, in response to the main state signal being in a failure state, disconnecting the electronic device from the power source.

Broadly speaking, the monitoring circuit relies on the standby electric power which enables fuse state indicators to operate and monitor a state of fuses once the electronic device is powered. The monitoring circuit may thus enable segregation between circumstances where no electric power is provided to the electronic device, and circumstances where one or more of the fuses are blown.

In some non-limiting implementations, the logic combiner is a first logic combiner, the electric power is a plurality of electric powers, each electric power being received at a corresponding power input of the monitoring circuit. Directing the electric power to the electronic device through a corresponding fuse state indicator of the monitoring circuit includes directing, by the monitoring circuit, the plurality of electric powers to the electronic device through a plurality of corresponding fuse state indicators of the monitoring circuit, each fuse state indicator selectively connecting a corresponding one of the plurality of power inputs to the electronic device and relying on the first standby electric power to operate, each fuse assembly being configured to generate a corresponding fuse state signal. The method further includes, prior to combining the fuse state signal with the electric power, combining, by a second logic combiner of the monitoring circuit, the status signals of the plurality of fuse state indicators to form a combined fuse state signal, the first logic combiner being configured to combine the combined fuse state signal with the plurality of electric powers to obtain the main state signal.

In some non-limiting implementations, the first logic combiner has a first characteristic time during which a main state of the electronic device is set to an alive state upon establishment of the electric connection between the power source and the electronic device, and the second logic combiner has a second characteristic time during which the status of each fuse state indicator is set to an alive state upon establishment of the electric connection between the power source and the electronic device, the second characteristic time being greater than the first characteristic time.

In some non-limiting implementations, the second characteristic time is between <NUM> and <NUM> times greater than the first characteristic time.

In some non-limiting implementations, the electronic device is a server of a datacenter, and the power source is electrically connected a power distribution unit for transmitting the electric power to the monitoring circuit.

In some non-limiting implementations, the first standby voltage is 12Vsb.

In some non-limiting implementations, the method further includes, subsequent to receiving the first standby electric power, converting, by a converting module of the monitoring circuit, the first standby electric power into a second standby electric power.

In some non-limiting implementations, the second standby voltage is <NUM>.

In some non-limiting implementations, the latch is a D-type latch.

In some non-limiting implementations, the method further includes, in response to the main state signal being in a failure state, operating a latch to maintain a failure state of the main state signal.

In a second broad aspect of the present technology, there is provided a system for providing electric power to an electronic device. The system includes a power input configured to receive an electric power at a corresponding voltage from a power source, a standby power input configured to receive a first standby electric power at a first standby voltage from the power source, a fuse state indicator configured to receive a corresponding electric power from a corresponding power input and output the electric power to the electronic device, the fuse state indicator relying on the first standby electric power to operate, the fuse state indicator being configured to generate a fuse state signal indicative of a state thereof that can be selectively an alive state or a failure state, a logic combiner configured to combine the fuse state signal with a signal indicative of a presence of the electric power at the power input, the logic combiner being configured to generate a main state signal that can be selectively an alive state or a failure state; and a controller. The controller causes, in response to the main state signal being in a failure state, a disconnection of the electronic device from the power source.

In some non-limiting implementations, the controller further causes, in response to the main state signal being in a failure state, a latch to be operated to maintain a failure state of the main state signal.

In some non-limiting implementations, the logic combiner is a first logic combiner. The system further includes a plurality of power inputs, each power input being configured to receive a corresponding electric power at a correspond voltage from the power source, a plurality of fuse state indicator, each fuse state indicator being configured to receive the corresponding electric power from a corresponding one of the power inputs and output the electric power to the electronic device, a second logic combiner configured to combine the status signals of the plurality of fuse state indicators to form a combined fuse state signal, the first logic combiner being configured to combine the combined fuse state signal with the plurality of electric powers to obtain the main state signal.

In some non-limiting implementations, the system further includes a converting module to convert, subsequent to receiving the first standby electric power, the first standby electric power into a second standby electric power.

In some non-limiting implementations, the system is mounted on a support board of the electronic device.

In some non-limiting implementations, the electronic device is a server of a datacenter, and the power source is electrically connected a power distribution unit for transmitting the electric powers to the monitoring circuit.

In the context of the present specification, a "server" is a computer program that is running on appropriate hardware and is capable of receiving requests (e.g., from client devices) over a network, and carrying out those requests, or causing those requests to be carried out. The hardware may be one physical computer or one physical computer system, but neither is required to be the case with respect to the present technology. In the present context, the use of the expression a "server" is not intended to mean that every task (e.g., received instructions or requests) or any particular task will have been received, carried out, or caused to be carried out, by the same server (i.e., the same software and/or hardware); it is intended to mean that any number of software elements or hardware devices may be involved in receiving/sending, carrying out or causing to be carried out any task or request, or the consequences of any task or request; and all of this software and hardware may be one server or multiple servers, both of which are included within the expression "at least one server".

In the context of the present specification, the expression "information" includes information of any nature or kind whatsoever capable of being stored in a database. Thus information includes, but is not limited to audiovisual works (images, movies, sound records, presentations etc.), data (location data, numerical data, etc.), text (opinions, comments, questions, messages, etc.), documents, spreadsheets, lists of words, etc..

In the context of the present specification, the expression "component" is meant to include software (appropriate to a particular hardware context) that is both necessary and sufficient to achieve the specific function(s) being referenced.

In the context of the present specification, the expression "computer usable information storage medium" is intended to include media of any nature and kind whatsoever, including RAM, ROM, disks (CD-ROMs, DVDs, floppy disks, hard drivers, etc.), USB keys, solid state-drives, tape drives, etc..

In the context of the present specification, unless expressly provided otherwise, an "indication" of an information element may be the information element itself or a pointer, reference, link, or other indirect mechanism enabling the recipient of the indication to locate a network, memory, database, or other computer-readable medium location from which the information element may be retrieved. For example, an indication of a document could include the document itself (i.e. its contents), or it could be a unique document descriptor identifying a data object with respect to a particular object storage device, or some other means of directing the recipient of the indication to a network location, memory address, database table, or other location where the data object may be accessed. As one skilled in the art would recognize, the degree of precision required in such an indication depends on the extent of any prior understanding about the interpretation to be given to information being exchanged as between the sender and the recipient of the indication. For example, if it is understood prior to a communication between a sender and a recipient that an indication of an information element will take the form of a database key for an entry in a particular table of a predetermined database containing the information element, then the sending of the database key is all that is required to effectively convey the information element to the recipient, even though the information element itself was not transmitted as between the sender and the recipient of the indication.

In the context of the present specification, the words "first", "second", "third", etc. have been used as adjectives only for the purpose of allowing for distinction between the nouns that they modify from one another, and not for the purpose of describing any particular relationship between those nouns. Thus, for example, it should be understood that, the use of the terms "first server" and "third server" is not intended to imply any particular order, type, chronology, hierarchy or ranking (for example) of/between the server, nor is their use (by itself) intended imply that any "second server" must necessarily exist in any given situation. Further, as is discussed herein in other contexts, reference to a "first" element and a "second" element does not preclude the two elements from being the same actual real-world element. Thus, for example, in some instances, a "first" server and a "second" server may be the same software and/or hardware, in other cases they may be different software and/or hardware.

Embodiments and examples of the present technology each have at least one of the above-mentioned objects and/or aspects, but do not necessarily have all of them. It should be understood that some aspects of the present technology that have resulted from attempting to attain the above-mentioned object may not satisfy this object and/or may satisfy other objects not specifically recited herein.

Moreover, all statements herein reciting principles, aspects, and implementations of the present technology, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof, whether they are currently known or developed in the future. Thus, for example, it will be appreciated by those skilled in the art that any block diagrams herein represents conceptual views of illustrative circuitry embodying the principles of the present technology. Similarly, it will be appreciated that any flowcharts, flow diagrams, state transition diagrams, pseudo-code, and the like represent various processes that may be substantially represented in non-transitory computer-readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

The functions of the various elements shown in the figures, including any functional block labeled as a "processor" or "processing unit", may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. In some examples of the present technology, the processor may be a general-purpose processor, such as a central processing unit (CPU) or a processor dedicated to a specific purpose, such as a digital signal processor (DSP). Moreover, explicit use of the term a "processor" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read-only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage.

Moreover, it should be understood that module may include for example, but without being limitative, computer program logic, computer program instructions, software, stack, firmware, hardware circuitry or a combination thereof which provides the required capabilities.

Additional and/or alternative features, aspects and advantages of embodiments and examples of the present technology will become apparent from the following description, the accompanying drawings and the appended claims.

It should also be noted that, unless otherwise explicitly specified herein, the drawings are not to scale.

The examples and conditional language recited herein are principally intended to aid the reader in understanding the principles of the present technology and not to limit its scope to such specifically recited examples and conditions. It will be appreciated that those skilled in the art may devise various arrangements that, although not explicitly described or shown herein, nonetheless embody the principles of the present technology.

<FIG> is a schematic diagram of a monitoring circuit <NUM> for distributing electric power from a power source <NUM> to an electronic device <NUM>. The power source <NUM> may be a power distribution unit (PDU) that provides one or more electric powers at different voltages. For example, the power source <NUM> may provide a first electric power at 12V, a second electric power at 5V, a third electric power at <NUM>. 3V and a fourth electric at 12V standby, or "12Vsb".

In this implementation, the electronic device <NUM> is a server <NUM> of a datacenter. The load may be any other type of electronic device in alternative implementations of the present technology. The server <NUM> may be implemented as a conventional computer server. In an example of an embodiment of the present technology, the server <NUM> may be implemented as a Dell™ PowerEdge™ Server running the Microsoft™ Windows Server™ operating system. Needless to say, the server <NUM> may be implemented in any other suitable hardware, software, and/or firmware, or a combination thereof. The server <NUM> may be provided with air cooling equipment, water cooling equipment or any other suitable cooling equipment that provides cooling to the electronic components of the server <NUM>.

The monitoring circuit <NUM> includes a plurality of power inputs <NUM><NUM>, <NUM><NUM> (two of them being depicted on <FIG>) and directs the electric power to electronic components <NUM><NUM>, <NUM><NUM> of the server <NUM>. To do so, the monitoring circuit includes a local controller <NUM> and a plurality of fuse state indicators <NUM><NUM>, <NUM><NUM> communicably connected therewith. In some embodiments, the monitoring circuit <NUM> includes eight (<NUM>) power inputs and eight (<NUM>) corresponding fuse state indicators. Only two of each are depicted for simplicity of <FIG>. It should be noted that two or more power inputs <NUM> may receive a same electric power (e.g. 12V) from the power source <NUM>. Some of the fuse state indicators may not be electrically connected to electric components of the server <NUM> and be used to assess if the power source provides the required electric powers.

Broadly speaking, each fuse state indicator <NUM> includes a fuse whose state can be either an "alive" state or a "failure" state. The state of the fuse of each fuse state indicators <NUM> is actively monitored by the local controller which may, in response to a fuse being in a failure state, disconnect the server <NUM> from the power source <NUM> to prevent any additional damages from occurring to the server <NUM> and/or the power source <NUM> and other equipment electrically connected therewith. In the event of a short circuit on another server electrically connected to the power source <NUM>, it may be important that the power source <NUM> is not overloaded and can continue to supply power to the other servers (i.e. to avoid propagation of the failure).

In opposition to some other technologies relying on fuses, the monitoring circuit <NUM> may actively detect which fuse is in a failure state. Said other technologies usually measure a voltage at an output of a fuse to detect a state thereof. However, there still may be confusion about, in case where no voltage is measured at the output of the fuse, whether the fuse is in a failure state, or if there is no electric power flowing there through. In both cases, this may generate an infinite reaction loop that inhibits the flow of electric current to the load to be powered through the fuse.

The monitoring circuit further receives, from the power source <NUM>, a standby electric power at a standby power input <NUM>sb. As will be described in greater details herein after, the standby electric power is used to enable to local controller <NUM> to monitor the fuse state indicators <NUM><NUM>, <NUM><NUM>. In this implementation, the standby electric power is 12Vsb but this aspect is not limitative.

<FIG> is an electric diagram of a fuse state indicator <NUM>i of the monitoring circuit <NUM> of <FIG> in accordance with non-limiting implementations of the present technology. The fuse state indicator <NUM>i includes a fuse <NUM>i electrically connected to a metal-oxide-semiconductor field-effect transistor (MOSFET) <NUM>i used as an electric switching device.

More specifically, the MOSFET <NUM>i is electrically connected to the fuse <NUM>i at input <NUM> and a 3V3sb inlet at input <NUM>. In this implementation, the monitoring circuit includes a voltage converter to convert a voltage of the standby electric power of 12Vsb into a <NUM>. 3Vsb standby electric power. This aspect is not limitative, other voltage values may be used for the standby electric powers used by the monitoring circuit <NUM>.

In use, the MOSFET <NUM>i generate an output signal <NUM>i indicative of a state of the fuse <NUM>i, or "status signal" <NUM>i. More specifically, the status signal <NUM>i is 3V3sb in case where the fuse <NUM>i is blown or at a pre-determined value based on the electric power received at the power input <NUM>i corresponding to the fuse state indicator <NUM>i. As such, the MOSFET <NUM>i rely on the standby electric power to provide the status signal <NUM>i indicative of the state of the fuse <NUM>i.

<FIG> is an electric diagram of the logic combiner <NUM> of the monitoring circuit <NUM> in accordance with non-limiting implementations of the present technology. The logic combiner <NUM> receives status signals from each of the fuse states indicators and includes an NAND gate <NUM> for combining output signals thereof. In use, the gate <NUM> is electrically connected to the Ground (GND) and to a <NUM>. 3Vsb inlet to operate. The gate <NUM> thus generates a signal <NUM> from the status signals.

In some implementations, the logic combiner <NUM> further includes a resistor-capacitor circuit (RC circuit) <NUM> including a resistor R27 and a capacitor C17, and another AND gate <NUM> receiving the signal <NUM> through the RC circuit <NUM> and a <NUM>. 3Vsb inlet. In use, the gate <NUM> generates a combined fuse state signal <NUM> denoted Fuses. As will be described in greater details herein after, the RC circuit <NUM> may disable or delay a generation of the combined fuse state signal <NUM> during a loading time of the capacitor C17 upon establishment of the electric connection between the power source <NUM> and the server <NUM>.

<FIG> is an electric diagram of a logical gate of the logic combiner <NUM> in accordance with non-limiting implementations of the present technology. In these implementations, the logic combiner <NUM> includes a NAND gate <NUM> that receives the combined fuse state signal <NUM> and a status signal of a fuse state indicator that indicates the presence of a 12V electric power at a power input of the monitoring circuit <NUM>. The voltage value (i.e. 12V) of the electric power is not limitative. One of the functions of the gate <NUM> is to check that all the fuses <NUM> are not blown and a presence of the 12V electric power that may be used to power some of the electronic components <NUM> of the server <NUM>. In other words, the status signal "12V img" is a status signal generated by one of the fuse state indicators. In some implementations, the status signal "12V img" is 12V in cases where the fuse of said fuse state indicator is not blown, and <NUM>. 3V in cases where the fuse is blown. The gate <NUM> thus generates an adjusted combined fuse state signal <NUM>.

<FIG> is an electric diagram of the logic combiner <NUM> of the monitoring circuit <NUM> in accordance with non-limiting implementations of the present technology. The logic combiner <NUM> includes a latch <NUM>. In this implementation, the latch <NUM> is a D-latch that receives the adjusted combined fuse state signal <NUM> from the gate <NUM> as a Clock Pulse (CP) input (see input <NUM>), and the status signal "12V img" as a Data (D) input. Therefore, the output signal of the gate <NUM> is used to trigger a latching of the status signal "12V img" into the latch. The logic combiner <NUM> also includes a RC circuit <NUM> combined with an AND gate <NUM> to generate a Read Enable (RD) input for the latch <NUM>. Therefore, the RC circuit <NUM> and the gate <NUM> are used to generate control signal that enables or disables the reading of data into the latch <NUM>. The latch <NUM> also receives a <NUM>. 3Vsb signal as a Set-Disable" input that serves as a control signal to set or rest the latch <NUM>.

Broadly speaking, the logic combiner <NUM> combines the adjusted combined fuse state signal <NUM> with a signal indicative of a presence of the electric power at the power input of the monitoring circuit to form a main state signal <NUM> "srvOk" that can be selectively an alive state (i.e. high state) or a failure state (i.e. low state). Referring back to <FIG>, the monitoring circuit <NUM> further includes a switching mechanism <NUM> that can disconnect the server <NUM> from the power source <NUM> in case of the srvOk signal being in the failure state (i.e. detection of a failure of one of the fuse <NUM>). For example, the switching mechanism <NUM> may include a plurality of switches that can be actuated in parallel to disconnect the server <NUM> from the power source <NUM>.

In some implementations, the srvOK signal must be high for the monitoring circuit <NUM> to distribute electric power from the power source to the server <NUM>. In the event of a fault, (e.g. an open fuse <NUM>), the srvOK signal must switch to the low state. However, when the server <NUM> is electrically connected to the monitoring circuit <NUM> and the power source <NUM>, as the monitoring circuit <NUM> is not powered, the srvOK signal can only be in the low state, which may cause issues (e.g. blocking reception of the power supply from the power source <NUM>) during insertion of the server <NUM>.

The latch <NUM> is used to force the srvOK signal in the high state for a short time denoted T<NUM> using the RC circuit <NUM> at the RD input thereof, so that the inserted server <NUM> can receive electric power and start up. Therefore, when the server <NUM> is inserted, the monitoring circuit <NUM> is supplied with the 12Vsb standby electric power which enables the fuse state indicators <NUM> to operate and monitor a state of the fuses <NUM>.

In this embodiment, the detection of the state of the fuses <NUM> is delayed by a time T2 with T2>T1 to ensure that in the event of an insertion failure at the server <NUM>, said detection is correctly executed and is not altered by the state of the latch <NUM>. It can be said that the latch <NUM> acts as a memory and stores the detection state to indicate failure of a fuse <NUM>.

<FIG> shows temporal charts of voltages of signals processed by the monitoring circuit <NUM> in accordance with non-limiting implementations of the present technology.

Chart <NUM> shows a temporal evolution of the <NUM>. 3Vsb used to operate the components of the monitoring circuit <NUM> such as the logic combiners <NUM>, <NUM>. In the illustrative example of <FIG>, the monitoring circuit <NUM> is electrically connected to the power source <NUM> at t=t<NUM>. The power source <NUM> thus provides the standby electric power 12Vsb at t=t<NUM> such that the <NUM>. 3Vsb signal rises at that time.

Chart <NUM> shows a temporal evolution of the voltage at inlet <NUM> of the gate <NUM> of the logic combiner <NUM> (i.e. an output of the RC circuit <NUM>). A characteristic time of the RC circuit <NUM> is noted τ<NUM>. In this illustrative example, τ<NUM> is about <NUM>. It can be said that the RC circuit <NUM> thus delays an establishment of the output of the gate <NUM>. As a result, the "Fuses" signal is delayed and rises at t=t<NUM> as shown on chart <NUM>, which in turn causes the srvOk signal to rise at t=t<NUM>.

In response to the electrical connection of the monitoring circuit <NUM> to the power source <NUM> at t=t<NUM>, the inlet <NUM> of the gate <NUM> of the logic combiner <NUM> receives a signal. Chart <NUM> shows a temporal evolution of said signal. A characteristic time of the RC circuit <NUM> is noted τ<NUM>. In this illustrative example, τ<NUM> is about <NUM>. It can be said that the RC circuit <NUM> thus delays an establishment of the output of the gate <NUM>.

In this example, a failure of one of the fuses <NUM> occurs at t=t<NUM>, as shown on chart <NUM> when the "Fuses" signal is down to zero, which in turn causes the srvOk signal to fall to zero at t=t<NUM>. In response, the monitoring circuit <NUM> actuates the switching mechanism <NUM> to disconnect the server <NUM> from the power source <NUM>. As shown on chart <NUM>, the voltage at the power inputs <NUM> of the monitoring circuit <NUM> is thus zero at t=t<NUM> shortly after t<NUM>.

Chart <NUM> shows a temporal evolution of the voltage of the Clock Pulse (CP) input of the latch <NUM>, showing a clock rising edge at t=t<NUM> to store the detection state to indicate that the srvOk in is the failure state.

<FIG> is a flow diagram of a method <NUM> for providing electric power to an electronic device such as the server <NUM> according to some examples of the present technology. In one or more aspects, the method <NUM> or one or more steps thereof may be performed by a processor or a computer system, in the present example by the local controller <NUM>. The method <NUM> or one or more steps thereof may be embodied in computer-executable instructions that are stored in a computer-readable medium, such as a non-transitory mass storage device, loaded into memory and executed by a CPU. Some steps or portions of steps in the flow diagram may be omitted or changed in order.

The method <NUM> starts with receiving, at operation <NUM>, from a power source and at a monitoring circuit electrically connected to the electronic device, electric power at a corresponding voltage, the electric power being received at a corresponding power input of the monitoring circuit. For example and without limitations, the electronic device may be a server of a datacenter and the power source may be electrically connected a power distribution unit for transmitting the electric power to the monitoring circuit.

The method <NUM> continues with receiving, at operation <NUM>, at a standby power input of the monitoring circuit, a first standby electric power at a first standby voltage. The first standby voltage may be for example 12Vsb.

The method <NUM> continues with directing, at operation <NUM>, by the monitoring circuit, the electric power to the electronic device through a corresponding fuse state indicator of the monitoring circuit. In use, the fuse state indicator selectively connects a corresponding power input to the electronic device and relies on the first standby electric power to operate. The fuse state indicator generates a fuse state signal indicative of a state thereof that can be selectively an alive state or a failure state.

In some implementations, the method <NUM> may further include converting, subsequent to receiving the first standby electric power, by the monitoring circuit, the first standby electric power into a second standby electric power. For example, the fuse state indicator may rely on a <NUM>. 3Vsb generated from a voltage conversion of the 12Vsb.

The method <NUM> continues with combining, at operation <NUM>, by a logic combiner of the monitoring circuit such as the logic combiner <NUM>, the fuse state signal with a signal indicative of a presence of the electric power at the power input of the monitoring circuit to form a main state signal that can be selectively an alive state or a failure state.

In some implementations, the logic combiner is a first logic combiner, the electric power is a plurality of electric powers and each electric power being received at a corresponding power input of the monitoring circuit. The monitoring circuit may direct the plurality of electric powers to the electronic device through a plurality of corresponding fuse state indicators of the monitoring circuit, each fuse state indicator selectively connecting a corresponding one of the plurality of power inputs to the electronic device and relying on the first standby electric power to operate, each fuse assembly being configured to generate a corresponding fuse state signal.

In these implementations, the method <NUM> further includes combining, by a second logic combiner of the monitoring circuit such as the logic combiner <NUM>, the status signals of the plurality of fuse state indicators to form a combined fuse state signal, the first logic combiner being configured to combine the combined fuse state signal with the plurality of electric powers to obtain the main state signal.

In these implementations, the first logic combiner has a first characteristic time during which a main state of the electronic device is set to an alive state upon establishment of the electric connection between the power source and the electronic device. The second logic combiner has a second characteristic time during which the status of each fuse state indicator is set to an alive state upon establishment of the electric connection between the power source and the electronic device, the second characteristic time being greater than the first characteristic time. For example, the second characteristic time may be between <NUM> and <NUM> times greater than the first characteristic time.

The method <NUM> continues with assessing, at operation <NUM>, whether the main state signal is in a failure state. In response to the main state signal being in a failure state, the method <NUM> includes operating, at sub-operation <NUM>, a latch to maintain a failure state of the main state signal, and disconnecting, at sub-operation <NUM>, the electronic device from the power source. For example, the latch may be a D-type latch. Other types of latch such as S-R latch, JK latch or any other suitable latch are contemplated alternative implementations.

While the above-described implementations have been described and shown with reference to particular steps performed in a particular order, it will be understood that these steps may be combined, sub-divided, or re-ordered without departing from the teachings of the present technology. At least some of the steps may be executed in parallel or in series. Accordingly, the order and grouping of the steps is not a limitation of the present technology.

As an example, <FIG> is a schematic block diagram of the local controller <NUM> of the monitoring circuit <NUM> according to an example of the present technology. The local controller <NUM> includes a processor or a plurality of cooperating processors (represented as a processor <NUM> for simplicity), a memory device or a plurality of memory devices (represented as a memory device <NUM> for simplicity), and an input/output interface <NUM> allowing the local controller <NUM> to communicate with other components of the monitoring circuit <NUM> and/or other components in communication with the monitoring circuit <NUM> such as the fuse state indicators <NUM>, the power source <NUM> and the server <NUM>. The processor <NUM> is operatively connected to the memory device <NUM> and to the input/output interface <NUM>. The memory device <NUM> includes a storage for storing parameters <NUM>. The memory device <NUM> may comprise a non-transitory computer-readable medium for storing code instructions <NUM> that are executable by the processor <NUM> to allow the local controller <NUM> to perform the various tasks allocated to the local controller <NUM> in the method <NUM>.

The local controller <NUM> is operatively connected, via the input/output interface <NUM>, to the fuse state indicators <NUM>, the power source <NUM> and the server <NUM>. The local controller <NUM> executes the code instructions <NUM> stored in the memory device <NUM> to implement the various above-described functions that may be present in a particular example. <FIG> as illustrated represents a non-limiting example in which the local controller <NUM> orchestrates operations of the monitoring circuit <NUM>. This particular example is not meant to limit the present disclosure and is provided for illustration purposes.

It should be noted that, in this implementation, the local controller <NUM> may be implemented directly on the server <NUM>.

It is to be understood that the operations and functionality of the described monitoring circuit <NUM>, its constituent components, and associated processes may be achieved by any one or more of hardware-based, software-based, and firmware-based elements. Such operational alternatives do not, in any way, limit the scope of the present disclosure.

It should be expressly understood that not all technical effects mentioned herein need to be enjoyed in each and every example of the present technology.

Claim 1:
A method (<NUM>) for providing electric power to an electronic device (<NUM>), the method comprising:
receiving, from a power source and at a monitoring circuit (<NUM>) electrically connected to the electronic device (<NUM>), electric power at a corresponding voltage, the electric power being received at a corresponding power input of the monitoring circuit (<NUM>);
receiving, at a standby power input (<NUM>sb) of the monitoring circuit (<NUM>), a first standby electric power at a first standby voltage;
directing, by the monitoring circuit (<NUM>), the electric power to the electronic device (<NUM>) through a corresponding fuse state indicator (<NUM>) of the monitoring circuit (<NUM>), the fuse state indicator (<NUM>) selectively connecting a corresponding power input to the electronic device (<NUM>) and relying on the first standby electric power to operate, the fuse state indicator (<NUM>) being configured to generate a fuse state signal indicative of a state thereof that can be selectively an alive state or a failure state;
combining, by a logic combiner (<NUM>) of the monitoring circuit (<NUM>), the fuse state signal with a signal indicative of a presence of the electric power at the power input of the monitoring circuit (<NUM>) to form a main state signal that can be selectively an alive state or a failure state; and
in response to the main state signal being in a failure state:
disconnecting the electronic device (<NUM>) from the power source (<NUM>).