Patent Description:
One factor to consider for power consumption by electronic devices is the power consumed by the integrated circuit (IC) devices of an electronic device. In general, power consumption by IC devices increases with an increase in a clock frequency that controls the IC devices. In some instances, a relatively high clock frequency may be desirable for one or more IC devices to achieve an elevated performance level. However, if the clock frequency remains high when the elevated performance level is not needed, power may be wasted. Consequently, controlling a clock frequency while balancing power efficiency with performance can therefore be challenging.

This background description is provided to generally present the context of the disclosure. Unless otherwise indicated herein, material described in this section is neither expressly nor impliedly admitted to be prior art to the present disclosure or the appended claims. <CIT>proposes systems, methods, and apparatus that can reduce power consumption of memory controllers in response to memory command backlog in various situations. A data storage device includes a plurality of sets of non-volatile memory (NVM) devices, a central controller, and a plurality of channel controllers. Each channel controller is coupled to a distinct set of the plurality of sets of NVM devices. Each channel controller includes a command queue configured to store pending memory commands and provide backlog information. The central controller is configured to receive the backlog information of the command queues of the plurality of channel controllers, and adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level. <CIT> proposes systems and methods for storing data in a multi-level cell (MLC) flash memory. One such data storage system has a data path with cascaded data access performance, including multiple storage portions having different data access speeds. A cascaded data path enables flash memory data access that has a more graceful degradation instead of an abrupt decrease in performance during operation.

Techniques and apparatuses are described that use transaction queue occupancy to alter a clock frequency that controls access to a memory of an electronic device. Techniques include detecting that a transaction queue threshold has been violated, initiating a counter to measure a time duration, determining that the transaction queue threshold continues to be violated for the time duration, and altering the clock frequency controlling access to the memory in response to the extended violation.

According to the present invention, there is provided a method as set out in claim <NUM>.

Also disclosed herein is a method not according to the claims, which is performed by a memory controller. The method includes computing, for a second clock frequency that is lower than a first clock frequency presently controlling a rate of accessing a memory, a quantity of clock cycles consumed to perform a transaction with the memory. The computed quantity of clock cycles consumed to perform the transaction with the memory may, in some instances, correspond to a simulated occupied portion of a length of a transaction queue for accessing the memory. The method also includes determining, based on the computed quantity of clock cycles, that the simulated, occupied portion of the length of the transaction queue will fall below transaction queue threshold for a time duration and, in response, decreasing the rate of accessing the memory to the second clock frequency.

The details of one or more implementations are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the description, the drawings, and the claims. This summary is provided to introduce subject matter that is further described in the Detailed Description. Accordingly, a reader should not consider the summary to describe essential features nor threshold the scope of the claimed subject matter.

Apparatuses and techniques enabling alteration of a clock frequency controlling access to a memory based on transaction queue occupancy are described with reference to the following drawings. The same numbers are used throughout the drawings to reference like features and components:.

Techniques and apparatuses are described that use transaction queue occupancy to alter a clock frequency that controls access to a memory of an electronic device. Techniques include detecting that a transaction queue threshold has been violated, initiating a counter to measure a time duration, determining that the transaction queue threshold continues to be violated for the time duration, and altering the clock frequency that controls access to the memory of the electronic device in response to the extended violation.

Manufacturers often consider anticipated levels of power consumption when designing electronic devices. Motivations for lowering power consumption include reducing cost-of-use and minimizing environmental impact. Furthermore, electronic devices that are portable are powered by batteries, which have a limited ability to provide energy before needing to be recharged. Thus, a portable electronic device can be used for longer periods before needing to be recharged by reducing power consumption. A lower rate of power consumption can also enable the use of a smaller battery to decrease the size of a portable electronic device.

A major power consumer of an electronic device is often the integrated circuit (IC) devices. In general, power consumption by IC devices can escalate with an increase in a clock frequency controlling the IC devices (e.g., a clock frequency that is typically measured in megahertz (MHz) or gigahertz (GHz)). A relatively high clock frequency may be desirable for the IC devices to achieve elevated performance levels. However, if the clock frequency of the IC devices remains high when the elevated performance level is not needed, power may be wasted.

A memory controller may be used to control a clock frequency and a rate of memory transactions, or accesses, between a processor IC device and a memory IC device. Heuristics within the memory controller often rely upon counting approaches that tally a total number of accesses, such as writes to the memory IC device or reads from the memory IC device. If the total number of accesses violates a predefined upper-threshold, the memory controller may increase a clock frequency of the memory IC device. If the total number of memory accesses violates a predefined lower-threshold, the memory controller may decrease the clock frequency of the memory IC device.

Heuristics that rely upon such counting approaches, however, are often flawed. As an example, in some instances accesses to the memory by the processor may be clustered within a relatively small time-window. This presents a conflict wherein the heuristics indicate that the predefined upper-threshold is not violated but where, in actuality, an increase in the clock frequency of the memory IC device is advisable to maintain performance. To compensate for this flaw, heuristics using counting approaches may artificially lower the predefined upper-threshold so that the memory controller triggers the increase in the clock frequency sooner.

With such a compensation approach, however, a new flaw may be introduced. For example, in other instances where accesses to the memory by the processor may be evenly distributed across a relatively large time-window, the artificially-lowered upper-threshold may cause the memory controller to trigger an increase to the clock frequency that is, in actuality, unneeded. In these other example instances the unneeded clock frequency may waste power.

The drawbacks of heuristics that use counting approaches to control clock frequencies of memory IC devices in an electronic device compound themselves as a complexity of a memory architecture of the electronic device increases. For example, the electronic device may use a memory architecture that relies upon a main memory IC device and multiple levels of cache memory IC devices, each of which may include a respective memory controller to control respective clock frequencies. These drawbacks may be overcome, however, by employing heuristics that use factors including transaction queue occupancy to determine thresholds for increasing and/or decreasing frequency as described herein.

Example implementations in various levels of detail are discussed below with reference to the associated figures. The example implementations include (i) a method that alters clock frequency based on a transaction queue threshold being violated for a time duration, (ii) another method that decreases a clock frequency based on a simulated, occupied portion of a length of a transaction queue falling below a transaction queue threshold for a time duration, and (iii) another method that includes a first memory controller determining that a transaction queue threshold is violated for a time duration and transmitting a message to a second memory controller that directs the second memory controller to change a rate of accessing the second memory. The discussion below first describes an example operating environment, followed by example heuristic details, followed by example methods, and ends with related example aspects.

<FIG> illustrates an example environment <NUM> including integrated circuitry in which altering a clock frequency controlling access to a memory based on transaction queue occupancy can be implemented. As shown, the environment <NUM> includes an electronic device <NUM>. Although illustrated as a smartphone, the electronic device <NUM> can be a computer, a tablet, a laptop, a server, a wearable device, an Internet of Things (IoT) device, an entertainment device, a security device, and so on.

The electronic device <NUM> includes integrated circuitry <NUM>. The integrated circuitry <NUM> includes multiple different portions or cores. These include at least one processor <NUM>, a first level of a cache memory (e.g., L1 cache memory <NUM>), a second level of a cache memory (e.g., L2 cache memory <NUM>), a third level of a cache memory (e.g., L3 cache memory <NUM>), and a main memory <NUM>. In general, the different memories (e.g., the L1 cache memory <NUM>, the L2 cache memory <NUM>, the L3 cache memory <NUM>, and the main memory <NUM>) can operate in one or more memory states using different respective clock frequencies.

The different memories may be of different types and/or combinations. For example, the L1 cache memory <NUM>, the L2 cache memory <NUM>, and the L3 cache memory <NUM> may each be a type of memory corresponding to a static random-access memory (SRAM) that is "on-chip" (e.g., shares a same IC die with the processor <NUM>). The main memory <NUM> may, in contrast, be a type of memory corresponding to a dynamic random-access memory (DRAM) that is "off-chip" (e.g., on a different IC die than the processor <NUM>). Alternatively, the different memories may all share a same IC die with the processor <NUM> (e.g., share a system-on-chip (SoC) IC die with the processor <NUM>), be of one or more other types of memory (e.g., Flash memory), and so on.

In an example implementation, one or more of the different memories may include a controller. For instance, the main memory <NUM> may include a main memory controller <NUM>, and the L3 cache memory <NUM> may include an L3 cache memory controller <NUM>. In some instances, the main memory controller <NUM> and the L3 cache memory controller <NUM> may each include logic circuitry that alters a flow of data going to and from the respective memories For example, the logic circuitry may control clock frequencies that control accessing of the respective memories. Furthermore, the main memory controller <NUM> may be communicatively coupled to the L3 cache memory controller <NUM>.

In some instances, the processor <NUM> may attempt to access data with the different memories (e.g., read data from or write data to the memories to perform a transaction) in a hierarchal fashion. For instance, while executing a program or a set of instructions, the processor <NUM> may attempt to access target data (corresponding to an allocated physical address or location in the main memory <NUM>) with the L1 cache memory <NUM> first. If the data associated with the specific physical address or location is not accommodated by the L1 cache memory <NUM> (e.g., there is a miss in the first cache), the system can make a second attempt to access the target data, but with the L2 cache memory <NUM>. If the data associated with the allocated physical address or location is not accommodated by the L2 cache memory <NUM>, (e.g., a miss in the second cache), the system can make a third attempt to access the target data, but with the L3 cache memory <NUM>. If the data associated with the allocated physical address or location is not accommodated by the L3 cache memory <NUM> (e.g., a miss in the third cache), the system may then access the target data from the main memory <NUM> (e.g., access the target data using the allocated physical address or location in the main memory <NUM>).

Data transactions between the processor <NUM> and the L1 cache memory <NUM>, the L2 cache memory <NUM>, the L3 cache memory <NUM>, and the main memory <NUM> may occur at a rate controlled by a clock frequency (e.g., a clock frequency in MHz or GHz). The clock frequency for data transactions between the processor <NUM> and the memories may vary with each memory.

<FIG> illustrates example details <NUM> of a cache memory transaction queue and a main memory transaction queue in accordance with one or more aspects. As shown in <FIG>, the L3 cache memory <NUM> includes an L3 cache memory transaction queue <NUM> (e.g., Cache_Q) having a length <NUM> (e.g., a length corresponding to a quantity of "L+<NUM>" entries available in the L3 cache memory transaction queue <NUM>). In some instances, the L3 cache memory transaction queue <NUM> may be an outgoing transaction queue, from which the processor <NUM> may read data.

The main memory <NUM> includes a main memory transaction queue <NUM> (e.g., Main_Q) having another length <NUM> (e.g., a length corresponding to a quantity of "N+<NUM>" available entries in the main memory transaction queue <NUM>). In some instances, the main memory transaction queue <NUM> may be an incoming transaction queue, to which the processor <NUM> may write data.

Memory transactions between the processor <NUM> and the L3 cache memory <NUM> (e.g., memory reads and/or writes corresponding to entries in the L3 cache memory transaction queue <NUM>) can be serviced at a rate that is responsive to, or corresponds to, an L3 cache memory clock frequency <NUM>. Memory transactions between the processor <NUM> and the main memory <NUM> (e.g., memory reads and/or writes corresponding to entries in the main memory transaction queue <NUM>) can be serviced at a rate that is responsive to, or corresponds to, a main memory clock frequency <NUM>.

In general, and due to differences in lengths of transaction queues and/or differences in clock frequencies, a transaction between the processor <NUM> and respective memories may be completed at different rates. For example, if the length <NUM> is relatively shorter than the length <NUM>, and if the L3 cache memory clock frequency <NUM> is relatively higher than the main memory clock frequency <NUM>, the processor <NUM> may complete a memory transaction with the L3 cache memory <NUM> more quickly than it can complete a different transaction with the main memory <NUM>.

In some instances, and as will be described in greater detail below, the L3 cache memory controller <NUM> and/or the main memory controller <NUM> may use heuristics to control the L3 cache memory clock frequency <NUM> and/or the main memory clock frequency <NUM>. Such heuristics may use an occupied portion <NUM> of the length <NUM> of the L3 cache memory transaction queue <NUM> and/or an occupied portion <NUM> of the length <NUM> of the main memory transaction queue <NUM>.

<FIG> illustrates example transaction request profiles <NUM> in accordance with one or more aspects. In some instances, the transaction request profiles <NUM> may be associated with the processor <NUM> of <FIG> and <FIG> performing transactions with the main memory <NUM> of <FIG> and <FIG> using aspects depicted in <FIG> and <FIG>.

The first example transaction request profile <NUM> illustrates an instance of a relatively low and uniform distribution of memory transaction requests across a predetermined duration of time. As illustrated, the transaction request profile <NUM> indicates that the processor <NUM> requests a quantity of "X" transactions with the main memory <NUM> over the predetermined duration of time that spans between t<NUM> and t<NUM> (e.g., count = X).

Due to the even distribution, no memory transactions between the processor <NUM> and the main memory <NUM> are missed (e.g., the main memory clock frequency <NUM> is such that the main memory <NUM> can support memory transactions at a rate that is compatible with requests from the processor <NUM>). Using heuristics founded on a count-based threshold (e.g., a count threshold of X), the main memory controller <NUM> would determine not to increase the main memory clock frequency <NUM> for the first example transaction request profile <NUM>.

The second example transaction request profile <NUM> illustrates an instance of a non-uniform distribution of memory transaction requests across the same predetermined duration of time. Even though the processor <NUM> requests the same quantity of transactions with the main memory <NUM> over the same predetermined period of time (e.g., count = X), the transaction request profile <NUM> includes a "burst" during which a number of transaction requests is relatively high.

If the main memory clock frequency <NUM> is relatively low, the main memory <NUM> may "stall" (e.g., not be able to fulfill requested transactions with the processor <NUM>) during the burst. Using heuristics founded on a count-based threshold (e.g., a count threshold of X), however, the main memory controller <NUM> would still determine not to increase the main memory clock frequency <NUM> for the second example transaction request profile <NUM>.

In some instances, and to circumvent stalls that may occur during the burst condition, the heuristics in the main memory controller <NUM> may use a lower count threshold (e.g., count threshold < X). However, this may unnecessarily increase the main memory clock frequency <NUM> during steady-state conditions and therefore waste power.

The third example transaction request profile <NUM> illustrates an instance of a relatively high and uniform distribution of memory transaction requests across the same predetermined duration of time. As illustrated, the transaction request profile <NUM> indicates that the processor <NUM> requests a quantity of "Y" transactions with the main memory <NUM> over the predetermined duration of time that spans between t<NUM> and t<NUM> (e.g., count =Y). Using heuristics founded on a count-based threshold (e.g., a count threshold of Y), the main memory controller <NUM> would determine to increase the main memory clock frequency <NUM>. The increase in the main memory clock frequency <NUM>, however, would not manifest until after the predetermined duration of time has transpired. Furthermore, the main memory <NUM> may stall before the predetermined duration of time expires.

In general, improved heuristics that use one or more thresholds based on memory transaction queue occupancy (e.g., an occupied portion of a length of the memory transaction queue) may alleviate drawbacks associated with heuristics that use count-based thresholds. The improved heuristics may proactively increase a clock frequency controlling access to a memory before the occurrence of instances where the memory may stall or may proactively reduce the clock frequency controlling the access to the memory ahead of instances where power may be wasted to further promote power efficiency.

<FIG> illustrates a flowchart <NUM> illustrating example heuristics for altering a clock frequency controlling access to a memory using transaction queue occupancy in accordance with one or more aspects. For simplicity, the below description of the flowchart <NUM> will be in the context of the main memory controller <NUM> of <FIG> and <FIG> controlling the main memory clock frequency <NUM> of the main memory <NUM>. Nonetheless, the described principles are applicable to other memory types and/or levels, such as a cache memory that operates responsive to a cache memory clock frequency and a corresponding cache memory controller.

In some instances, the heuristics of the flowchart <NUM> may be initiated during a power-up condition of an electronic device (e.g., the electronic device <NUM> of <FIG>). In other instances, heuristics of the flowchart <NUM> may be initiated in response to a command entered by a user of the electronic device <NUM> (e.g., the user may, through a selectable menu, change a mode or a setting of the electronic device to operate in a particular memory clock frequency mode using specific parameters or categories indicative of memory performance and/or power efficiency).

At decision <NUM>, a determination of a state of a transaction queue is made relative to a transaction queue threshold. The transaction queue threshold corresponds to an occupied portion of a length of a transaction queue. Using the main memory transaction queue <NUM> and the main memory controller <NUM> as an example, the main memory controller <NUM> may compute the occupied portion <NUM> of the length <NUM>. If the computation indicates that a transaction queue threshold is not violated (e.g., the occupied portion <NUM> of the length <NUM> is not greater than <NUM>%), the main memory controller <NUM> may, at process <NUM>, reset (e.g., zero-out) a timer. In some instances, the timer may be realized as circuitry that is included as part of the main memory controller <NUM> and that is capable of tracking a time duration using the main memory clock frequency <NUM>.

The main memory controller <NUM> may, at operation <NUM>, continue to monitor the main memory transaction queue <NUM>. At decision <NUM>, the main memory controller <NUM> determines that the occupied portion <NUM> of the length <NUM> exceeds the transaction queue threshold (e.g., the occupied portion <NUM> is greater than <NUM>% of the length <NUM>). Upon determining that the transaction queue threshold is exceeded, the main memory controller <NUM> may, at operation <NUM>, initiate the timer to monitor for a duration of time as indicated at decision <NUM>.

The main memory controller <NUM> determines, through iterative monitoring of the occupied portion <NUM> of the length <NUM> and comparison of the occupied portion <NUM> to the transaction queue threshold (at decision <NUM>) over time, at decision <NUM> that the transaction queue threshold is violated for a duration of time (e.g., as illustrated, the transaction queue threshold of <NUM>% is exceeded for more than <NUM> milliseconds (ms)). In response, the main memory controller <NUM> may at operation <NUM> increase the main memory clock frequency <NUM> to increase a rate at which the processor <NUM> can access the main memory <NUM> (e.g., by increasing a rate at which the main memory <NUM> processes memory transaction requests).

Although the heuristics of the flowchart <NUM> described above apply to a transaction queue threshold that provides an upper-threshold (e.g., a threshold that is violated if exceeded), variations of the heuristics may apply to a transaction queue threshold that provides a lower-threshold (e.g., one that is violated if a monitored value drops below the threshold). For instance, the main memory controller <NUM> may determine that the occupied portion <NUM> of the length <NUM> falls below another threshold of <NUM>% for another time duration and, in response, decrease the main memory clock frequency <NUM> to decrease the rate of accessing of the main memory <NUM>.

Heuristics illustrated by the flowchart <NUM> may also be modified to include simulations. The simulations can be used to "predict" if a lower frequency is sufficient for a current memory transaction rate. For example, using the main memory clock frequency <NUM>, the main memory controller <NUM> may compute a quantity of clock cycles consumed to perform a memory transaction. The main memory controller <NUM> may determine that the simulated occupied portion <NUM> of the length <NUM> of the main memory transaction queue <NUM> will or would fall below a threshold based on the computed quantity of clock cycles. Responsive to this determination that is based on the simulation using a computed quantity of clock cycles at a given clock frequency, the main memory controller <NUM> may decrease the main memory clock frequency <NUM>. Such simulations may, in some instances, use multiple iterations to decrease the main memory clock frequency <NUM> in stages using different thresholds.

In some instances, heuristics illustrated by the flowchart <NUM> may be performed by a combination of memory controllers. For example, the main memory controller <NUM> and the L3 cache memory controller <NUM> may be communicatively coupled, allowing operations and decisions of the flowchart <NUM> to be divided or shared between the main memory controller <NUM> and the L3 cache memory controller <NUM>. The main memory controller <NUM> or the L3 cache memory controller <NUM> may, for instance, control the other's clock frequency through an exchange of messages, instructions, and so on.

In general, parameters that influence the heuristics of the flowchart <NUM> may be variable. For example, the transaction queue threshold, whether an upper-threshold or a lower-threshold, may be <NUM>%, <NUM>%, <NUM>% and so on. As another example, the duration of time may be <NUM>, <NUM>, <NUM>, and so on. In some instances, a user may vary or input such parameters into the electronic device <NUM> through a selectable menu, which may use qualitative terms (e.g., "memory power saving mode" or "memory high-performance mode") to represent different threshold values. In other instances, a manufacturer of the electronic device <NUM> may load the parameters into the electronic device <NUM>. In yet other instances, the electronic device <NUM> may include power monitoring circuitry and logic that varies the parameters based on a charge-level (e.g., stored power) available to the electronic device.

<FIG> illustrates an example method <NUM> in accordance with one or more aspects. In some instances, the method <NUM> may be performed by a memory controller using elements of <FIG>, <FIG>, and <FIG>.

At operation <NUM>, the memory controller (e.g., the main memory controller <NUM>) detects that a transaction queue threshold is violated. The transaction queue threshold corresponds to the occupied portion <NUM> of the length <NUM> of the main memory transaction queue <NUM>. In some instances, the violation may correspond to exceeding an upper-threshold, while in other instances the violation may correspond to falling below a lower-threshold.

At operation <NUM>, and in response to determining that the transaction queue threshold is violated, the memory controller initiates a counter based on a clock frequency to measure a time duration (e.g., for a given or known clock frequency, a counter may count a number of cycles and, from the counted number of cycles, compute a corresponding time duration). The clock frequency corresponds to the main memory clock frequency <NUM> that controls a rate at which the main memory <NUM> can process memory requests issued by the processor <NUM>.

At operation <NUM>, the memory controller determines that the transaction queue threshold continues to be violated for the time duration. At <NUM>, and in response to the determination that the transaction queue threshold continues to be violated for the time duration, the memory controller alters the clock frequency.

In an instance where the transaction queue threshold is an upper-threshold and violating the transaction queue threshold for the time duration includes exceeding the transaction queue threshold for the time duration, altering the clock frequency may include increasing the clock frequency to increase the rate at which the processor can access the memory. In an instance where the transaction queue threshold is a lower-threshold and violating the transaction queue threshold for the time duration includes being below the transaction queue threshold for the time duration, altering the clock frequency may include decreasing the clock frequency to decrease the rate of operation of the memory to reduce power use.

Although the method <NUM> is described in the context of the main memory controller <NUM> altering the main memory clock frequency <NUM>, the method <NUM> includes many variations. For instance, the method <NUM> may be performed by another memory controller, such as the L3 cache memory controller <NUM>. In such an instance, the transaction queue threshold may correspond to the occupied portion <NUM> of the length <NUM> of the L3 cache memory transaction queue <NUM>, the clock frequency may correspond to L3 cache memory clock frequency <NUM>, and the memory may correspond to the L3 cache memory <NUM>. The method <NUM> may also encompass other memories (e.g., the L1 cache memory <NUM>, the L2 cache memory <NUM>, and so on). Furthermore, and in some instances, portions of the method <NUM> may be performed by the processor <NUM>.

<FIG> illustrates another example method <NUM> not according to the claims. In some instances, the method <NUM> may be performed by a memory controller using elements of <FIG>, <FIG>, and <FIG>.

At operation <NUM>, the memory controller (e.g., the main memory controller <NUM>) may compute, for a second clock frequency that is lower than a first clock frequency presently controlling a rate of accessing a memory (e.g., the main memory <NUM>), a quantity of clock cycles that transpire to perform a memory transaction (e.g., a read or a write entry from the main memory transaction queue <NUM>). The computed quantity of clock cycles per memory transaction may be used to simulate a changing size of an occupied portion of a length of a transaction queue for accessing the memory (e.g., simulate how the occupied portion <NUM> of the length <NUM> of the main memory transaction queue <NUM> would change over time if the main memory <NUM> were processing memory transactions at the slower second clock frequency).

At operation <NUM>, the memory controller may determine that the simulated occupied portion of the length (e.g., the portion <NUM> of the length <NUM> as simulated) falls below a transaction queue threshold for a time duration. At operation <NUM>, the memory controller may then decrease the rate of accessing the memory from the first clock frequency to the second clock frequency.

In some instances, determining that the simulated occupied portion of the length falls below the transaction queue threshold may include subtracting an offset (e.g., an offset that functions as a guard-band or a bias) from the transaction queue threshold. Also, in some instances, the memory controller may identify a value for the second clock frequency through iterative computations using multiple other clock frequencies that are lower than the first clock frequency. In such instances, and before identifying the second clock frequency, the memory controller may determine that multiple, other clock frequencies have simulated portions of the length of the transaction queue that are greater than or equal to the transaction queue threshold for the time duration.

Although the method <NUM> is described in the context of the main memory controller <NUM> altering the main memory clock frequency <NUM>, the method <NUM> includes many variations. For instance, the method <NUM> may be performed by another memory controller, such as the L3 cache memory controller <NUM>. In such an instance, the transaction queue threshold may correspond to the occupied portion <NUM> of the length <NUM> of the L3 cache memory transaction queue <NUM> (e.g., the portion <NUM> as simulated), the clock frequency may correspond to the L3 cache memory clock frequency <NUM>, and the memory may correspond to the L3 cache memory <NUM>. The method <NUM> may also encompass other memories (e.g., the L1 cache memory <NUM>, the L2 cache memory <NUM>, and so on). Furthermore, and in some instances, portions of the method <NUM> may be performed by the processor <NUM>.

<FIG> illustrates another example method <NUM> in accordance with one or more aspects. In some instances, the method <NUM> may be performed by memory controllers of an electronic device, such as the main memory controller <NUM> and the L3 cache memory controller <NUM> of the electronic device <NUM> of <FIG>, using elements of <FIG>, <FIG>, and <FIG>.

At operation <NUM>, a first memory controller (e.g., the main memory controller <NUM>) may determine that a transaction queue threshold is violated for a time duration. In such an instance, the transaction queue threshold may correspond to an occupied portion of a length of a memory transaction queue (e.g., the occupied portion <NUM> of the length <NUM> of the L3 cache memory transaction queue <NUM>).

In response, at operation <NUM>, the first memory controller may transmit a message to a second memory controller (e.g., the L3 cache memory controller <NUM>). The message may include an instruction that directs (e.g., causes) the second memory controller to alter a clock frequency to change a rate of accessing a second memory (e.g., the L3 cache memory <NUM>).

Although described in the context of operations between the main memory controller <NUM> and the L3 cache memory controller <NUM>, the method <NUM> includes many variations. As a first example variation, the method <NUM> may include operations performed by the L3 cache memory controller <NUM> and another cache memory controller (e.g., a controller of the L1 cache memory <NUM> or the L2 cache memory <NUM>). As a second example variation, the L3 cache memory controller <NUM> may use input from the main memory controller <NUM> as an additional input for controlling a rate of accessing the L3 cache memory <NUM> (e.g., whether the L3 cache memory controller <NUM> controls the L3 cache memory clock frequency <NUM> based on the occupied portion <NUM> of the length <NUM> of the L3 cache memory transaction queue <NUM> or whether the L3 cache memory controller <NUM> controls the L3 cache memory clock frequency <NUM> using another technique). As a third example variation, portions of the method <NUM> may be performed by the processor <NUM>.

The preceding discussion describes methods relating to using transaction queue occupancy to alter a clock frequency that controls access to a memory of an electronic device. Aspects of these methods may be implemented in hardware (e.g., fixed logic circuitry), firmware, software, or any combination thereof. As an example, one or more operations described in methods <NUM>, <NUM>, or <NUM> may be performed by a computing system having one or more processors and a computer-readable medium (CRM). In such an instance, the CRM may encompass fixed or hard-coded circuitry, finite-state machines, programmed logic, and so forth that perform the one or more operations.

Furthermore, these techniques may be realized using one or more of the entities or components shown in <FIG>, <FIG>, and <FIG>, which may be further divided, combined, and so on. Thus, these figures illustrate some of the many possible systems or apparatuses capable of employing the described techniques. The entities and components of these figures generally represent software, firmware, hardware, whole or portions of devices or networks, or a combination thereof.

Claim 1:
A method (<NUM>) performed by a memory controller (<NUM>, <NUM>), the method comprising:
detecting (<NUM>) that a transaction queue threshold is violated, the transaction queue threshold corresponding to an occupied portion (<NUM>, <NUM>) of a length (<NUM>, <NUM>) of a transaction queue (<NUM>, <NUM>) for accessing a memory (<NUM>, <NUM>);
in response to the detecting, initiating (<NUM>) a counter to measure a time duration, the counter based on a clock frequency (<NUM>, <NUM>) controlling a rate of accessing the memory (<NUM>, <NUM>);
determining (<NUM>) that the transaction queue threshold continues to be violated for the time duration; and
in response (<NUM>) to the determining, altering the clock frequency (<NUM>, <NUM>).