Patent Description:
Hereinafter, a "Q" prefix in a word or phrase is indicative of a reference of that word or phrase in a quantum computing context unless expressly distinguished where used.

Molecules and subatomic particles follow the laws of quantum mechanics, a branch of physics that explores how the physical world works at the most fundamental levels. At this level, particles behave in strange ways, taking on more than one state at the same time, and interacting with other particles that are very far away. Quantum computing harnesses these quantum phenomena to process information.

The computers we use today are known as classical computers (also referred to herein as "conventional" computers or conventional nodes, or "CN"). A conventional computer uses a conventional processor fabricated using semiconductor materials and technology, a semiconductor memory, and a magnetic or solid-state storage device, in what is known as a Von Neumann architecture. Particularly, the processors in conventional computers are binary processors, i.e., operating on binary data represented by strings comprising <NUM> and <NUM>.

A quantum processor (q-processor) uses the odd nature of entangled qubit devices (compactly referred to herein as "qubit," plural "qubits") to perform computational tasks. In the particular realms where quantum mechanics operates, particles of matter can exist in multiple states-such as an "on" state, an "off" state, or both "on" and "off" states simultaneously. Where binary computing using semiconductor processors is limited to using just the on and off states (equivalent to <NUM> and <NUM> in binary code), a quantum processor harnesses these quantum states of matter to output signals that are usable in data computing.

Conventional computers encode information in bits. Each bit can take the value of <NUM> or <NUM>. These <NUM> and <NUM> are physically implemented by on/off switches that ultimately drive computer functions. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both a <NUM> and a <NUM> at the same time. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one (whether it is a <NUM> or a <NUM> or both) can depend on the state of another, and that there is more information that can be ascertained about the two qubits when they are entangled than when they are treated individually.

Using these two principles, qubits operate as more sophisticated processors of information, enabling quantum computers to function in ways that allow them to solve difficult problems that are intractable using conventional computers. IBM has successfully constructed and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines corporation in the United States and in other countries.

A superconducting qubit includes a Josephson junction. A Josephson junction is formed by separating two thin-film superconducting metal layers by a non-superconducting material (or by a geometric constriction of superconducting material). When the metal in the superconducting layers is caused to become superconducting - e.g. by reducing the temperature of the metal to a specified cryogenic temperature - pairs of electrons can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In a qubit, the Josephson junction - which functions as a dissipationless nonlinear inductor - is electrically coupled in parallel with one or more capacitive devices forming a nonlinear microwave oscillator. The oscillator has a resonance/transition frequency determined by the value of the inductance and the capacitance in the qubit circuit. Any reference to the term "qubit" is a reference to a superconducting qubit circuitry that employs a Josephson junction, unless expressly distinguished where used.

In a superconducting state, the material firstly offers no resistance to the passage of electrical current. When resistance falls to zero, a current can circulate inside the material without any dissipation of energy. Secondly, the material exhibits Meissner effect, i.e., provided they are sufficiently weak, external magnetic fields do not penetrate the superconductor, but remain at its surface. When one or both of these properties are no longer exhibited by the material, the material is said to be no longer superconducting.

A critical temperature of a superconducting material is a temperature at which the material begins to exhibit characteristics of superconductivity. Superconducting materials exhibit very low or zero resistivity to the flow of current. A critical field is the highest magnetic field, for a given temperature, under which a material remains superconducting.

Superconductors are generally classified into one of two types. Type I superconductors exhibit a single transition at the critical field. Type I superconductors transition from a non-superconducting state to a superconducting state when the critical field is reached. Type II superconductors include two critical fields and two transitions. At or below the lower critical field, type II superconductors exhibit a superconducting state. Above the upper critical field, type II superconductors exhibit no properties of superconductivity. Between the upper critical field and the lower critical field, type II superconductors exhibit a mixed state. In a mixed state, type II superconductors exhibit an incomplete Meissner effect, i.e., penetration of external magnetic fields in quantized packets at specific locations through the superconductor material.

The Meissner effect results from the generation of persistent currents at the surface of the superconductor material. Persistent currents are perpetual electric currents which do not require an external power source. The persistent currents generate an opposing magnetic field to cancel the external magnetic field throughout the bulk of the superconductor material. In a superconducting state, persistent currents do not decay with time due to the zero resistance property.

The information processed by qubits is carried or transmitted in the form of microwave signals/photons in the range of microwave frequencies. The microwave signals are captured, processed, and analyzed to decipher the quantum information encoded therein. A readout circuit is a circuit coupled with the qubit to capture, read, and measure the quantum state of the qubit. An output of the readout circuit is information usable by a q-processor to perform computations.

A superconducting qubit has two computational states -|<NUM>> and |<NUM>>. These two states may be two energy states of atoms, for example, the ground (|g>) and first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of the nuclear or electronic spins, two positions of a crystalline defect, and two states of a quantum dot. Since the system is of a quantum nature, any (normalized) linear combination of the two computational states is allowed and valid.

For quantum computing using qubits to be reliable, quantum circuits, e.g., the qubits themselves, the readout circuitry associated with the qubits, and other parts of the quantum processor, must not alter the energy states of the qubit, such as by injecting or dissipating energy, in any significant manner or influence the relative phase between the |<NUM>> and |<NUM>> states of the qubit. This operational constraint on any circuit that operates with quantum information necessitates special considerations in fabricating semiconductor and superconducting structures that are used in such circuits.

The presently available quantum circuits are formed using materials that become superconducting at cryogenically low temperatures, e.g., below <NUM>. The external circuits that connect to a quantum circuit usually operate at room temperature (approximately <NUM>-<NUM>) or higher. The connections between an external circuit and a q-circuit, e.g., an input line to the q-circuit or an output line from the q-circuit, or both, must therefore be thermally isolated from the external circuit's environment.

To provide this thermal isolation, the lines connecting to a q-circuit pass through a series of one or more dilution fridge stages (compactly referred to herein as "stage", plural "stages"). A dilution fridge is a heat-exchange device which causes a reduction in a temperature of a component as compared to the temperature at which the component is introduced into the dilution fridge, maintains the component at a designated reduced temperature, or both. For example, a dilution fridge stage may reduce the temperature of an input line to a q-circuit and another dilution fridge stage down the line in a series of dilution fridge stages may house the q-circuit.

A signal on a line passing through a stage can contain noise. This noise can be in the microwave frequency spectrum. For the reasons described herein, microwave frequency noise is undesirable when the line and signals relate to quantum computing using q-circuits.

Flip chip assembly is a method of interconnecting an electronic device with external circuitry by metallic solder bumps deposited onto pads of the electronic device. Pads on the electronic device are aligned with matching pads on the external circuitry.

Patent application<CIT> describes a qubit bonding scheme wherein a qubit chip is positioned on the surface of a substrate. International application <CIT> describes details of known bump connections.

The invention recognizes certain disadvantages with the presently available methods for quantum device assembly. For example, in the presently available methods, solder paste is deposited onto contact pads and the entire circuit assembly is then heated to create a molten state for the solder paste. Heating of the circuit assembly can be damaging to the Josephson Junction and degrade the performance of the circuit. As example, in the presently available methods, the metal deposits tend to oxidize, affecting the mechanical and electrical properties of the connection. De-oxidation of the metal deposits can be damaging to qubits. For example, chemicals and methods to remove surface oxides can be damaging and even completely destroy the Josephson Junction. Additionally, the presently available methods do not effectively create good electrical connections due to warpage of the substrate during the manufacturing process.

The invention recognizes that solder used to form electrical connections can deform during quantum device assembly and cooling. Plastic deformation is a non-reversible change of shape of a material under applied forces. Plastic deformation, called creep, depends on the time and temperature under which the solder is exposed to a stress during assembly. The invention recognizes that a direct relationship exists between the temperature of solder material and the amount of deformation. That is, the higher the temperature of the solder material, the more the solder deforms under an applied stress.

The invention further recognizes that deformation of the solder during quantum device assembly affects the desired electrical connections, that solder creep changes the gap height between pads on a flip chip, that solder creep changes the distance between the qubit and the ground and signals on the interposer, and that performance degradation occurs due to solder creep between signals, grounds, and qubits on any substrates, such as the qubit chip, interposer, or organic package. The gap height is designed to create a desired capacitance. Fluctuations in the gap height due to solder creep affects the capacitance values and the performance of the electrical connection.

An embodiment of the invention is a quantum device as defined by claim <NUM>.

The first set of protrusions may be of at least one member selected from a set comprising Gold and Platinum. The second set of protrusions may be of at least one member selected from a set comprising Gold and Platinum.

The set of bumps may be of at least one member selected from a set comprising Indium, Tin, Lead, and Bismuth. The first set of protrusions may have a conical shape. The second set of protrusions may have a pyramid shape.

The set of bumps may comprise a material exhibiting superconductivity in a cryogenic temperature range. A plurality of the first set of protrusions may be configured to cold weld to one of the set of bumps.

In an embodiment of the invention, a method as defined by claim <NUM> is provided.

Examples as well as embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, wherein:.

The examples and embodiments of the invention described here generally address and solve the above-described needs in quantum device assembly.

An operation described herein as occurring with respect to a frequency of frequencies should be interpreted as occurring with respect to a signal of that frequency or frequencies. All references to a "signal" are references to a microwave signal unless expressly distinguished where used.

An embodiment of the invention provides a configuration of a quantum device that can be used in a quantum computing device. Another embodiment of the invention provides a fabrication method for the quantum device, such that the method can be implemented as a software application. The application implementing a fabrication method can be configured to operate in conjunction with an existing fabrication system - such as a lithography system, or a circuit assembly system.

For the clarity of the description, and without implying any limitation thereto, embodiments of the invention are described using some example configurations. From this disclosure, those of ordinary skill in the art will be able to conceive many alterations, adaptations, and modifications of a described configuration for achieving a described purpose, and the same are contemplated within the scope of the invention as defined by the claims.

Furthermore, simplified diagrams of the example device components are used in the figures. In an actual fabrication or circuit, additional structures or component that are not shown or described herein, or structures or components different from those shown but for a similar function as described herein may be present without departing the scope of the invention as defined by the claims.

Furthermore, embodiments of the invention are described with respect to specific actual or hypothetical components only as examples. The steps described can be adapted for fabricating a circuit using a variety of components that can be purposed or repurposed to provide a described function, and such adaptations are contemplated within the scope of the invention provided that they are within the definition of the independent claims.

Embodiments of the invention are described with respect to certain types of materials, electrical properties, steps, numerosity, frequencies, circuits, components, and applications only as examples. Any specific manifestations of these and other similar artifacts are not intended to be limiting to the invention. Any suitable manifestation of these and other similar artifacts can be selected within the scope of the invention as defined by the claims.

The examples in this disclosure are used only for the clarity of the description and are not limiting to the invention. Any advantages listed herein are only examples and are not intended to be limiting to the invention. Additional or different advantages may be realized. Furthermore, a particular embodiment of the invention may have some, all, or none of the advantages listed above.

<FIG>, is a diagram of a data processing environment <NUM> in which embodiments of the invention may be implemented. <FIG> is only an example and is not intended to assert or imply any limitation with regard to the environments in which different embodiments of the invention may be implemented. A particular implementation may make many modifications to the depicted environments based on the following description.

Data processing environment <NUM> is a network of computers in which the illustrative embodiments may be implemented. Data processing environment <NUM> includes network <NUM>. Network <NUM> is the medium used to provide communications links between various devices and computers connected together within data processing environment <NUM>. Network <NUM> may include connections, such as wire, wireless communication links, or fiber optic cables.

Clients or servers are only example roles of certain data processing systems connected to network <NUM> and are not intended to exclude other configurations or roles for these data processing systems. Server <NUM> and server <NUM> couple to network <NUM> along with storage unit <NUM>. Software applications may execute on any computer in data processing environment <NUM>. Clients <NUM>, <NUM>, and <NUM> are also coupled to network <NUM>. A data processing system, such as server <NUM> or <NUM>, or client <NUM>, <NUM>, or <NUM> may contain data and may have software applications or software tools executing thereon.

Device <NUM> is an example of a mobile computing device. For example, device <NUM> can take the form of a smartphone, a tablet computer, a laptop computer, client <NUM> in a stationary or a portable form, a wearable computing device, or any other suitable device. Any software application described as executing in another data processing system in <FIG> can be configured to execute in device <NUM> in a similar manner. Any data or information stored or produced in another data processing system in <FIG> can be configured to be stored or produced in device <NUM> in a similar manner.

Application <NUM> implements an embodiment of the invention described herein. Fabrication system <NUM> is any suitable system for fabricating a quantum device. Application <NUM> provides instructions to system <NUM> for flip chip assembly of quantum devices in a manner described herein.

The hardware in <FIG> may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash memory, equivalent non-volatile memory, or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in <FIG>. In addition, the processes of embodiments of the invention may be applied to a multiprocessor data processing system.

<FIG>, is a block diagram of an example configuration <NUM>. Application <NUM> interacts with fabrication system <NUM> to produce or manipulate configuration <NUM> as described herein.

Configuration <NUM> comprises substrate <NUM>. Substrate <NUM> comprises a recess 202A disposed therethrough. Substrate <NUM> comprises a material with a predetermined thermal conductivity (above a threshold) in the cryogenic temperature range, about <NUM> to <NUM>. Substrate <NUM> is formed using a material that exhibits a Residual Resistance Ratio (RRR) of at least <NUM>, and a thermal conductivity of greater than a <NUM> W/(cm*K) at <NUM> Kelvin, threshold level of thermal conductivity. RRR is the ratio of the resistivity of a material at room temperature and at <NUM>. Because <NUM> cannot be reached in practice, an approximation at <NUM> is used. For example, substrate <NUM> may be an organic substrate or a ceramic substrate for operations in the cryogenic temperature range. This example of substrate material is not intended to be limiting. From this disclosure those of ordinary skill in the art will be able to conceive of many other materials suitable for forming the substrate and the same are contemplated within the scope of the invention according to the claims.

In an embodiment of the invention, the fabrication system <NUM>, creates a set of protrusions <NUM> on a surface of the substrate <NUM>. For example, an embodiment of the invention can cause the fabrication system to deposit material <NUM>, thus forming the set of protrusions <NUM>. In an embodiment of the invention, fabrication system <NUM> comprises a wire bonder to deposit material <NUM> and form protrusion <NUM>. For example, the wire bonder can form a first half of a ball bond before pulling upwards to deposit the remainder of the protrusion.

In an embodiment of the invention, protrusion <NUM> is a column. In another embodiment of the invention, protrusion <NUM> is a cone or a pyramid. For example, protrusion <NUM> can have an approximately triangular, cylindrical, circular, or rectangular cross-section.

In an embodiment of the invention, protrusion <NUM> comprises a material <NUM> with a predetermined ductility (above a threshold) at a room temperature range, <NUM> to <NUM>. In an embodiment of the invention, protrusion <NUM> is formed using a material that exhibits an elongation at break of at least twenty percent at a room temperature range, threshold level of ductility. Elongation at break is the ratio between increased length and initial length after fracture of a material in a tension test. For example, protrusion <NUM> may be formed using gold, platinum, or a gold-coated superconducting material. In an embodiment, protrusion <NUM> is formed using a material resistant to oxidation, chemical degradation of a surface of the material caused by oxygen. These examples of substrate materials, deposition devices, protrusion shapes, and protrusion materials are not intended to be limiting. From this disclosure those of ordinary skill in the art will be able to conceive of many other shapes, materials, and deposition devices suitable for forming the substrate and protrusions and the same are contemplated within the scope of the invention.

<FIG> is a block diagram of an example configuration <NUM>. Application <NUM> interacts with fabrication system <NUM> to produce or manipulate configuration <NUM> as described herein.

Configuration <NUM> comprises substrate <NUM>, interposer <NUM>, and qubit chip <NUM>. Substrate <NUM> is an example of substrate <NUM> in <FIG>. An embodiment of the invention causes the fabrication system <NUM> to deposit material on the interposer <NUM>, thus forming a set of bumps <NUM>. For example, an embodiment of the invention can cause the fabrication system <NUM> to solder the set of bumps <NUM> on the interposer <NUM>. As another example, the set of bumps <NUM> can be formed by electroplating, evaporating, ball mounting, paste printing, jetting, or injection molded soldering (IMS).

In an embodiment of the invention, the set of bumps <NUM> comprises a material with a predetermined ductility (above a threshold) at a room temperature range. In an embodiment of the invention, the set of bumps <NUM> is formed using a material that exhibits an elongation at break of at least twenty percent at a room temperature range. For example, the set of bumps <NUM> is formed using at least one of Indium, Tin, Lead, Bismuth, and any combination thereof.

In an embodiment of the invention the fabrication system couples a qubit chip <NUM> to interposer <NUM>. In an embodiment of the invention, fabrication system <NUM> cold welds a set of pads of the qubit chip <NUM> with a subset of the set of solder bumps <NUM> on the interposer <NUM>. In an embodiment of the invention, fabrication system <NUM> cold welds a second subset of the set of solder bumps <NUM> with a set of protrusions <NUM> formed on the substrate <NUM>. Protrusion <NUM> is similar to protrusion <NUM> in <FIG>.

In an embodiment of the invention, each protrusion <NUM> couples to a corresponding solder bump <NUM>. For example, each protrusion <NUM> can pierce the corresponding solder bump <NUM>. Piercing the corresponding solder bump <NUM> enables contact between an outer surface of the protrusion <NUM> and an unoxidized, inner surface of the solder bump <NUM>. In another embodiment, multiple protrusions <NUM> couple to a single solder bump <NUM>. In an embodiment of the invention the fabrication system performs cold welding of the second subset of solder bumps <NUM> with the set of protrusions <NUM>. Cold welding is a welding process in which coupling takes place without heating at the interface of the two parts to be welded. In cold welding, no liquid or molten phase is present. After coupling, the qubit chip <NUM> is disposed in a recess 302A of the substrate. These examples of deposition methods and solder bump material are not intended to be limiting. From this disclosure, those of ordinary skill in the art will be able to conceive of many other materials and methods suitable for forming the set of bumps and the same are contemplated within the scope of the invention according to the claims.

Configuration <NUM> comprises qubit chip <NUM>. Qubit chip <NUM> comprises a material with a predetermined thermal conductivity (above a threshold) in the cryogenic temperature range. In an embodiment of the invention, qubit chip <NUM> is formed using a material that exhibits a RRR of at least <NUM>, and a thermal conductivity of greater than a <NUM> W/(cm*K) at <NUM> Kelvin, threshold level of thermal conductivity. For example, qubit chip <NUM> may be formed using sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, or diamond for operations in the cryogenic temperature range.

In an embodiment of the invention fabrication system <NUM> creates a set of protrusions <NUM> on a surface of the qubit chip <NUM> by fabrication system depositing material <NUM> in the same manner as material <NUM> is deposited to form protrusions <NUM>. Protrusion <NUM> may be a column and may have a triangular, cylindrical, or rectangular cross-section.

In an embodiment of the invention, protrusion <NUM> comprises a material <NUM> similar to material <NUM> of protrusions <NUM>. These examples of protrusion material, qubit chip material, protrusion shapes, and deposition methods are not intended to be limiting. From this disclosure those of ordinary skill in the art will be able to conceive of many other materials and methods suitable for forming the substrate, qubit chip, and protrusions and the same are contemplated within the scope of the invention according to the claims.

<FIG> is a block diagram of a configuraion <NUM> according to the invention. Application <NUM> interacts with fabrication system <NUM> to produce or manipulate configuration <NUM> as described herein.

Configuration <NUM> comprises substrate <NUM>, interposer <NUM>, and qubit chip <NUM>. Substrate <NUM> is an example of substrate <NUM> in <FIG>. In an embodiment of the invention the fabrication system <NUM> deposits material on the interposer <NUM>, thus forming a set of bumps <NUM> in similar fashion to the formation of bumps <NUM> on interposer <NUM>.

In an embodiment of the invention, the set of bumps <NUM> comprises a similar material to that of bumps <NUM>.

In an embodiment of the invention the fabrication system <NUM> couples a qubit chip <NUM> to interposer <NUM>. In an embodiment of the invention, fabrication system <NUM> cold welds a set of protrusions <NUM> of the qubit chip <NUM> with a subset of the set of solder bumps <NUM> on the interposer <NUM>. In an embodiment of the invention, each protrusion <NUM> couples to a corresponding solder bump <NUM>. For example, each protrusion <NUM> can pierce the corresponding solder bump <NUM>. In an embodimen the fabrication system performs cold welding the first subset of solder bumps <NUM> with the set of protrusions <NUM>. Cold welding is a welding process in which the interface of the two parts to be welded is at a room temperature range. In cold welding, the interface is in a solid state.

In an embodiment of the invention the fabrication system <NUM> couples interposer <NUM> to substrate <NUM>. In an embodiment of the invention, fabrication system <NUM> cold welds a second subset of the set of solder bumps <NUM> with a set of protrusions <NUM> formed on the substrate <NUM>. In an embodiment of the invention, each protrusion <NUM> couples to a corresponding solder bump <NUM>. For example, each protrusion <NUM> can pierce the corresponding solder bump <NUM>. In an embodiment of the invention the fabrication system <NUM> performs cold welding the second subset of solder bumps <NUM> with the set of protrusions <NUM>. Protrusion <NUM> is similar to protrusion <NUM> in <FIG>. After coupling the substrate <NUM> and interposer <NUM>, the qubit chip <NUM> is disposed in a recess 502A of the substrate. These examples of deposition methods and solder bump materials are not intended to be limiting. From this disclosure, those of ordinary skill in the art will be able to conceive of many other materials and deposition methods suitable for forming the set of bumps and the same are contemplated within the scope of the invention according to the claims.

Configuration <NUM> comprises substrate <NUM>, and qubit chip <NUM>. Substrate <NUM> is an example of substrate <NUM> in <FIG>. Qubit chip <NUM> is an example of qubit chip <NUM> in <FIG>. In an embodiment of the invention fabrication system <NUM> deposits material on the substrate <NUM>, thus forming a set of bumps <NUM>. For example, in an embodiment of the invention fabrication system <NUM> can solder the set of bumps <NUM> on substrate <NUM>. As another example, the set of bumps <NUM> can be formed by electroplating, evaporating, ball mounting, paste printing, jetting, or injection molded soldering (IMS).

In an embodiment of the invention the fabrication system <NUM> couples qubit chip <NUM> to substrate <NUM>. In an embodiment of the invention, fabrication system <NUM> cold welds a set of protrusions <NUM> of qubit chip <NUM> with the set of solder bumps <NUM> on substrate <NUM>. In an embodiment of the invention, each protrusion <NUM> couples to a corresponding solder bump <NUM>. For example, each protrusion <NUM> can pierce the corresponding solder bump <NUM>. In an embodiment of the invention the fabrication system <NUM> to perform cold welding the set of solder bumps <NUM> with the set of protrusions <NUM>. These examples of deposition methods and solder bump materials are not intended to be limiting. From this disclosure, those of ordinary skill in the art will be able to conceive of many other materials and deposition methods suitable for forming the set of bumps and the same are contemplated within the scope of the invention according to the claims.

<FIG>, is a block diagram of an example configuration <NUM>. Configuration <NUM> is an example of the cold-welded connection between protrusion <NUM> and bump <NUM>; protrusion <NUM> and bump <NUM>; protrusion <NUM> and bump <NUM>; or bump <NUM> and <NUM> in <FIG>, <FIG>, and <FIG>, respectively. Configuration <NUM> comprises first substrate <NUM>, first pad <NUM>, protrusion <NUM>, bump <NUM>, second pad <NUM>, and second substrate <NUM>.

Substrate <NUM> may be formed from the same material as substrate <NUM>.

Substrate <NUM> comprises a material with a predetermined thermal conductivity (above a threshold) in the cryogenic temperature range. In an embodiment of the invention, substrate <NUM> is formed using a similar material to that of qubit chip <NUM>.

In an embodiment of the invention, first pad <NUM> and second pad <NUM> is formed using at least one of titanium, palladium, gold, silver, copper, or platinum for operations in the cryogenic temperature range. In an embodiment of the invention, first pad <NUM> and second pad <NUM> are deposited as under bump metallurgy (UBM) by using sputtering, evaporation, or plating method.

Protrusion <NUM> is an example of protrusion <NUM> in <FIG>. Bump <NUM> is an example of bump <NUM> in <FIG>. An embodiment of the invention causes the fabrication system <NUM> to couple first substrate <NUM> to second substrate <NUM>. In an embodiment of the invention, fabrication system <NUM> cold welds the protrusion <NUM> of the first substrate <NUM> with a solder bump <NUM> on the second substrate <NUM>. For example, protrusion <NUM> can pierce the corresponding solder bump <NUM>. An embodiment of the invention causes the fabrication system <NUM> to cold weld the solder bump <NUM> with the protrusion <NUM>.

In an embodiment of the invention, the bump <NUM> is formed using a similar material to that used to form bump <NUM>.

In an embodiment of the invention, the bump <NUM> is formed using a material that exhibits superconductivity in the cryogenic temperature range. In an embodiment of the invention, bump <NUM> contacts first pad <NUM> and second pad <NUM>. In an embodiment of the invention, bump <NUM> provides a superconducting path between first pad <NUM> and second pad <NUM> in the cryogenic temperature range. These examples of substrate materials, bump materials, deposition methods, and pad materials are not intended to be limiting. From this disclosure those of ordinary skill in the art will be able to conceive of many other materials and deposition methods suitable for forming the components of the device and the same are contemplated within the scope of the invention.

<FIG> is a block diagram of an example configuration. Configuration <NUM> is an example of the cold-welded connection between protrusion <NUM> and bump <NUM>; protrusion <NUM> and bump <NUM>; protrusion <NUM> and bump <NUM>; or bump <NUM> and protrusion <NUM> in <FIG>, <FIG>, and <FIG>, respectively. Configuration <NUM> comprises first substrate <NUM>, first pad <NUM>, protrusion <NUM>, bump <NUM>, second pad <NUM>, and second substrate <NUM>.

Substrate <NUM> is similar to substrate <NUM>.

In an embodiment of the invention, first pad <NUM> and second pad <NUM> are similar to pads <NUM> and <NUM>. These examples are not intended to be limiting. From this disclosure those of ordinary skill in the art will be able to conceive of many other materials suitable for forming the first layer and the same are contemplated within the scope of the invention.

Protrusion <NUM> is an example of protrusion <NUM> in <FIG>. Bump <NUM> is an example of bump <NUM> in <FIG>. An embodiment of the invention causes the fabrication system to couple first substrate <NUM> to second substrate <NUM>. In an embodiment of the invention, fabrication system <NUM> cold welds the protrusion <NUM> of the first substrate <NUM> with a solder bump <NUM> on the second substrate <NUM>. For example, protrusion <NUM> can pierce the corresponding solder bump <NUM>. An embodiment of the invention causes the fabrication system to cold weld the solder bump <NUM> with the protrusion <NUM>.

In an embodiment of the invention, the bump <NUM> is similar to bump <NUM>.

In an embodiment of the invention, a capacitance of the electrical connection is determined by a distance between the pads <NUM> and <NUM>. For example, the capacitance is inversely proportional to a distance, or gap height, between the pads <NUM> and <NUM>. In an embodiment of the invention, protrusion <NUM> has a height corresponding to a desired capacitance of the electrical connection. In an embodiment of the invention, the gap height is a function of the height of the protrusion <NUM> and the compression force during cold welding. For example, the gap height can have an inverse relationship with the amount of the compression force during cold welding. As another example, the gap height can have a direct relationship with the height of the protrusion <NUM>. These examples of substrate materials, bump materials, deposition methods, and pad materials are not intended to be limiting. From this disclosure those of ordinary skill in the art will be able to conceive of many other materials and deposition methods suitable for forming the components of the device and the same are contemplated within the scope of the invention. In an embodiment of the invention, a height of corresponding protrusions differs between a set of protrusions formed on a surface. For example, a height of protrusions can differ to accommodate warpage of a substrate.

With respect to <FIG>, this figure depicts a flowchart of a quantum device assembly process. Process <NUM> can be implemented in application <NUM>, to cold weld an electrical connection as described with respect to <FIG>.

The application causes a fabrication system to deposit a first set of stud bumps (protrusions) on a qubit chip (block <NUM>); deposit a second set of stud bumps (protrusions) on a substrate (block <NUM>); and, deposit a set of bumps on an interposer (block <NUM>), Such as a set of solder bumps. The application causes a fabrication system to form an electrical connection between the qubit chip and an interposer (block <NUM>), such as to cold weld an electrical connection between the stud bump on the qubit chip and a solder bump on the interposer. The application causes a fabrication system to form an electrical connection between the interposer and the substrate (block <NUM>), such as to cold weld an electrical connection between the stud bump on the substrate and a solder bump on the interposer. The application causes a fabrication system to form an electrical connection between the qubit chip and the substrate (block <NUM>), such as to cold weld an electrical connection between the stud bump on the qubit chip and a solder bump on the substrate. The application ends process <NUM> thereafter. These examples of process steps and order of process steps are not intended to be limiting. From this disclosure those of ordinary skill in the art will be able to conceive of many other steps and order of process steps suitable for quantum device assembly and the same are contemplated within the scope of the invention as defined by the claims.

Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer "A" over layer "B" include situations in which one or more intermediate layers (e.g., layer "C") is between layer "A" and layer "B" as long as the relevant characteristics and functionalities of layer "A" and layer "B" are not substantially changed by the intermediate layer(s).

Additionally, the term "illustrative" is used herein to mean "serving as an example, instance or illustration. " Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms "a plurality" are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term "connection" can include an indirect "connection" and a direct "connection,".

References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic.

Claim 1:
A quantum device comprising:
a first set of protrusions (<NUM>) formed on a substrate (<NUM>);
a second set of protrusions (<NUM>) formed on a qubit chip (<NUM>), the qubit chip being disposed in a recess (502A) of the substrate; and
a set of bumps (<NUM>) formed on an interposer (<NUM>), the set of bumps formed of a material having above a threshold ductility at a room temperature range;
a first set of cold-welded couplings between a first subset of the set of bumps and the first set of protrusions, the first set of cold-welded couplings providing a first predetermined gap height between the interposer and the substrate; and,
a second set of set of cold-welded couplings between a second subset of the set of bumps and the second set of protrusions, the second set of cold welded couplings providing a second predetermined gap height between the interposer and the qubit chip, the second predetermined gap height being less than the first predetermined gap height.