Patent Description:
Computing devices abound in modern society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences.

Most such mobile communication devices have a suite of circuits coupled to one another by a bus to serve as a radio front end. The MIPI® Alliance has promulgated a standard to make devices associated with such radio front ends compatible. This standard is descriptively named the Radio Frequency Front End Control Interface (RFFE). The standard was initially released in July <NUM> as v. Subsequently, RFFE has been updated to accommodate <NUM> communication requirements. In particular, RFFE <NUM> has introduced the concept of a Timed-Trigger that permits reduction in control latency. The Timed-Trigger may require use of an active clock signal for extended periods of time as counters used to track triggers are decremented (or incremented) based on a clock signal.

<CIT> discloses a device for activating trigger data having a serial bus interface and a processing circuit coupled to the serial bus interface. The processing circuit is configured to receive a plurality of trigger data via a serial bus, receive a plurality of activation data via the serial bus, detect an activation scheme for activating a respective trigger data of the plurality of trigger data based on activation data corresponding to the respective trigger data, and activate the respective trigger data according to the detected activation scheme. If activated, each one of the plurality of trigger data respectively enables a corresponding operation to be performed at the device. Each one of the plurality of activation data respectively correspond to each one of the plurality of trigger data.

<CIT> discloses systems, methods, and apparatus for data communication. A method performed by a device operating as a bus master may include transmitting a first pulse on a first wire of a multi-wire interface, transmitting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, and initiating a low-latency mode of communication immediately after termination of the first pulse. The second pulse may be shorter in duration than the first pulse.

<CIT> discloses systems, methods, and apparatus for improving bus latency. A data communication apparatus has an interface circuit adapted to couple the apparatus to a first serial bus, a clock source configured to provide a clock signal and a trigger handler. The interface circuit may be configured to receive trigger configuration information in a first transaction conducted over a serial bus, and receive a trigger actuation command from a bus master coupled to the serial bus. The trigger handler may be configured to delay a trigger actuation signal for a delay duration defined by the trigger configuration information, and provide the trigger actuation signal after the delay duration has expired. The trigger actuation signal may be generated in response to the trigger actuation command.

Aspects disclosed in the detailed description include systems and methods for variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus. In particular, instead of having a master clock change a counter at a slave device on a one-to-one clock tick-to-counter change, exemplary aspects of the present disclosure contemplate allowing a bus ownership master (BOM) to select a stride size wherein each clock tick causes the counter to change by the size of the stride. Clock ticks are then sent less frequently over the clock line of the RFFE bus. In this fashion, fewer clock ticks are required to change the counter to a trigger event. By reducing a number of clock ticks required to reach the trigger event, dynamic power consumption may be reduced, thereby extending battery life for a mobile terminal that includes the RFFE bus.

Aspects disclosed in the detailed description include systems and methods for variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus. In particular, instead of having a master clock change a counter at a slave device on a one-to-one clock tick to counter change, exemplary aspects of the present disclosure contemplate allowing a bus ownership master (BOM) to select a stride size wherein each clock tick causes the counter to change by the size of the stride. Clock ticks are then sent less frequently over the clock line of the RFFE bus. In this fashion, fewer clock ticks are required to change the counter to the trigger event. By reducing a number of clock ticks required to reach a trigger event, dynamic power consumption may be reduced, thereby extending battery life for a mobile terminal that includes the RFFE bus.

To understand the context of the present disclosure, an overview of a computing device that includes an RFFE system including an RFFE bus is provided in <FIG>, with more detailed descriptions of slaves on the RFFE bus described in <FIG>. A description of an RFFE system that may use the variable stride clock signal of the present disclosure begins below with reference to <FIG>.

In this regard, <FIG> is a system-level block diagram of an exemplary computing device and in particular a mobile terminal <NUM> such as a smart phone, mobile computing device, tablet, or the like. The mobile terminal <NUM> includes an application processor <NUM> (sometimes referred to as a host) that communicates with a mass storage element <NUM> through a universal flash storage (UFS) bus <NUM>. The application processor <NUM> may further be connected to a display <NUM> through a display serial interface (DSI) bus <NUM> and a camera <NUM> through a camera serial interface (CSI) bus <NUM>. Various audio elements such as a microphone <NUM>, a speaker <NUM>, and an audio codec <NUM> may be coupled to the application processor <NUM> through a serial low-power interchip multimedia bus (SLIMbus) <NUM>. Additionally, the audio elements may communicate with each other through a SOUNDWIRE bus <NUM>. A modem <NUM> may also be coupled to the SLIMbus <NUM> and/or the SOUNDWIRE bus <NUM>. The modem <NUM> may further be connected to the application processor <NUM> through a peripheral component interconnect (PCI) or PCI express (PCIe) bus <NUM> and/or a system power management interface (SPMI) bus <NUM>.

With continued reference to <FIG>, the SPMI bus <NUM> may also be coupled to a wireless local area network (LAN or WLAN) integrated circuit (IC) (LAN IC or WLAN IC) <NUM>, a power management integrated circuit (PMIC) <NUM>, a companion IC (sometimes referred to as a bridge chip) <NUM>, and a radio frequency IC (RFIC) <NUM>. It should be appreciated that separate PCI buses <NUM> and <NUM> may also couple the application processor <NUM> to the companion IC <NUM> and the WLAN IC <NUM>. The application processor <NUM> may further be connected to sensors <NUM> through a sensor bus <NUM>. The modem <NUM> and the RFIC <NUM> may communicate using a bus <NUM>.

With continued reference to <FIG>, the RFIC <NUM> may couple to one or more RFFE elements, such as an antenna tuner <NUM>, a switch <NUM>, and a power amplifier <NUM> through an RFFE bus <NUM>. Additionally, the RFIC <NUM> may couple to an envelope tracking power supply (ETPS) <NUM> through a bus <NUM>, and the ETPS <NUM> may communicate with the power amplifier <NUM>. Collectively, the RFFE elements, including the RFIC <NUM>, may be considered an RFFE system <NUM>. It should be appreciated that the RFFE bus <NUM> is a two-wire bus and may be formed from a clock line and a data line (not illustrated).

It should be appreciated that typically the RFIC <NUM> is considered the master or host of the RFFE system <NUM> and particularly the master of the RFFE bus <NUM>. In contrast, the antenna tuner <NUM>, the switch <NUM>, and the power amplifier <NUM> are typically considered to be slaves for the RFFE system <NUM> and the RFFE bus <NUM>. The most recent version of the RFFE standard was released in May <NUM>.

A generic RFFE slave <NUM>, sometimes referred to as a slave circuit, is illustrated in <FIG>. In particular, the RFFE slave <NUM> includes a bus interface (sometimes referred to as I/F) <NUM> that is configured to couple to the RFFE bus <NUM> or other comparable two-wire bus. The bus interface <NUM> is controlled by a control circuit <NUM>, which may also control one or more active elements <NUM> (only one shown). The control circuit <NUM> may sometimes be referred to as a slave control circuit.

By way of example, the RFFE slave <NUM> may be the power amplifier <NUM>, and the active elements <NUM> may be individual low noise amplifiers (LNAs) for different frequency bands. The active elements <NUM> may need to be triggered at certain times depending on which frequencies are being used to effectuate wireless communications (e.g., to or from a remote base station). In view of this need to activate or trigger the active elements <NUM>, they are also referred to as triggered elements. The RFFE <NUM> standard introduces the concept of immediate triggers, which cause the triggered element to act immediately on receipt of the trigger command, and timed-triggers, which trigger triggered elements at specific subsequent times. It should further be appreciated that while the term "triggered elements" is used, an actual active element <NUM> is a circuit within an IC or chip that is the RFFE slave <NUM>. While exemplary aspects of the RFFE slave <NUM> may include new circuit structures within the control circuit <NUM>, the actual active elements <NUM> are generally conventional and well understood.

Individual counters and registers are generally provided for each active element <NUM> to track timed-trigger events. To assist in understanding this conventional system, <FIG> illustrates a slave <NUM> coupled to an RFFE bus <NUM>. The RFFE bus <NUM> is further coupled to a host or master (not shown) and includes a clock line <NUM> and a data line <NUM>. The clock line <NUM> carries a clock signal SCLK thereon, and the data line <NUM> carries a data signal SDATA thereon. The slave <NUM> is coupled to the RFFE bus <NUM> through a serial I/F <NUM>. The slave <NUM> further includes a triggered element <NUM>, which for the sake of example, may be an LNA. The triggered element <NUM> needs to be triggered at a precise time to amplify a signal that is being manipulated (e.g., transmitted or received) by an RFFE system (not shown). The host (still not shown) sends instructions and a timing value in the SDATA signal over the data line <NUM>. The instructions are loaded into a shadow register <NUM>, and the timing value is loaded into an N-bit down-counter <NUM>. The SCLK signal causes the N-bit down-counter <NUM> to decrement down from the timing value loaded therein from the SDATA signal at a one-to-one ratio of clock ticks-to-changes in the N-bit down-counter <NUM>. An N-bit <NUM>-detector <NUM> detects when the N-bit down-counter <NUM> has been decremented down to zero (<NUM>) and, when <NUM> is reached, causes the contents of the shadow register <NUM> to be loaded into the triggered element <NUM>. Equivalently, the N-bit down-counter <NUM> may be replaced with an up-counter that counts to a predefined threshold before loading the contents of the shadow register <NUM> to the triggered element <NUM>.

Similarly, <FIG> illustrates a slave <NUM> that has multiple triggered elements <NUM>(<NUM>)-<NUM>(K). For each of the multiple triggered elements <NUM>(<NUM>)-<NUM>(K), there is a corresponding N-bit down-counter <NUM>(<NUM>)-<NUM>(K), an N-bit <NUM>-detector <NUM>(<NUM>)-<NUM>(K), and a shadow register <NUM>(<NUM>)-<NUM>(K). Again, the contents of the shadow registers <NUM>(<NUM>)-<NUM>(K) are loaded from data in the SDATA signal (not shown in <FIG>) as are values for the N-bit down-counters <NUM>(<NUM>)-<NUM>(K). Each N-bit down-counter <NUM>(<NUM>)-<NUM>(K) is decremented by the SCLK signal. When a zero is detected by the corresponding one of the N-bit <NUM>-detectors <NUM>(<NUM>)-<NUM>(K), the contents of the corresponding shadow register <NUM>(<NUM>)-<NUM>(K) are loaded into the respective triggered element <NUM>(<NUM>)-<NUM>(K). Again, the triggered elements <NUM>(<NUM>)-<NUM>(K) may be, for example, LNAs, each operating at different frequencies which are turned on to certain amplifications at different times.

More generally <FIG> illustrates an RFFE system <NUM> with circuitry that allows a master <NUM> (sometimes referred to as master circuit) to set a stride length and communicate properties or variables of the stride to a slave <NUM>(<NUM>)-<NUM>(N) that causes the slave <NUM>(<NUM>)-<NUM>(N) to change counters therein by the stride length. The master <NUM> may include a control circuit <NUM> that is coupled to an always on subsystem (AOSS) <NUM> that is part of a bus interface <NUM>, which is more specifically an RFFE bus interface and sometimes referred to as a master bus interface. The control circuit <NUM> may include a clock, be coupled to a clock, or control a clock (not shown). Such a clock may be referred to as a clock circuit or clock source. The AOSS <NUM> may include a halt generator circuit <NUM>, a plurality of counters <NUM>, and multiplexers <NUM>(clk) and <NUM>(data). The bus interface <NUM> is configured to be coupled to an RFFE bus <NUM> formed from a clock line (SCLK) <NUM> and a data line (SDATA) <NUM>. The multiplexers <NUM>(clk) and <NUM>(data) are coupled to the clock line <NUM> and the data line <NUM>, respectively.

With continued reference to <FIG>, a given slave <NUM> such as slave <NUM>(<NUM>) has a slave bus interface <NUM> configured to be coupled to the RFFE bus <NUM>. The slave <NUM> may further have a halt detect circuit <NUM>, counters <NUM>, and timed-trigger registers <NUM>. Additionally, the slave <NUM> may include a control circuit <NUM>.

In use, the master <NUM> acts as a bus ownership master (BOM) that controls the RFFE bus <NUM>. Commands are sent to a given slave <NUM> to cause the slave <NUM> to operate in a particular fashion (e.g., change frequency at a particular time, change power levels, or the like). Because some of the slaves <NUM>(<NUM>)-<NUM>(N) may have limited (or no) counters <NUM> for use for timed-triggers, the master <NUM> may track triggers using the counters <NUM>. When a counter <NUM> expires by reaching zero (if a count-down counter) or by reaching a threshold (if a count-up counter), the master <NUM> may need to send an immediate trigger command to a slave <NUM>(<NUM>)-<NUM>(N) while an active process is ongoing.

In a conventional RFFE system, the SCLK signal on the clock line <NUM> of the RFFE bus <NUM> has a one-to-one correspondence of clock tick-to-change in counters <NUM>. When the counter is set at a large value, this means that a large number of clock ticks are sent over the clock line <NUM>. By way of example, <FIG>, shows a clock signal <NUM> having fourteen (<NUM>) clock ticks <NUM>. While fourteen clock ticks <NUM> are illustrated, it should be appreciated that sometimes the counters are set at values of one hundred (<NUM>) or more. Each time the clock signal <NUM> has a clock tick <NUM>, power is consumed by the line drivers. The invention allows fewer clock ticks to be sent while still changing the counters <NUM> at the slaves <NUM>(<NUM>)-<NUM>(N) by a programmed stride length so as to cause the counters <NUM> to reach the trigger count at the appropriate time. For example, if a stride length of two (<NUM>) is selected, a clock signal <NUM> is generated with a clock tick <NUM> every other normal clock cycle resulting in a <NUM>% power savings. Likewise, if a stride length of three (<NUM>) is selected, a clock signal <NUM> is generated with a clock tick <NUM> every third normal clock resulting in a <NUM>% power savings. Signals <NUM>, <NUM>, and <NUM> are also illustrated showing stride lengths of four, five and six (<NUM>,<NUM>, and <NUM>), respectively, with the clock ticks spread out accordingly.

The master <NUM> may communicate the stride length and other stride variables in a datagram sent to the slaves <NUM>(<NUM>)-<NUM>(N) at set up, or when the master <NUM> assumes BOM after a BOM change command. Note further that the stride may not be uniform, but may be dynamically adjusted by the master <NUM> sending another datagram to the slaves <NUM>(<NUM>)-<NUM>(N) or by more extensive programming at set up. Additional variables may be, but are not necessarily limited to: the stride size, changes to stride size based on values loaded into a corresponding counter, an indication of whether the stride is a positive or negative value (to change a count-up versus a count-down timer), whether the change to the counter occurs at the positive edge of the clock tick, the negative edge of the clock tick, or both, and a definition of stride zones.

As used herein, a stride size is an integer value that dictates by what value a counter is changed. A stride size of one (<NUM>) corresponds to the conventional one-to-one clock tick-to-counter change arrangement of a conventional RFFE system. But, for example, a stride size of six (<NUM>) means that a counter changes its value (up or down) by six (<NUM>) each time a clock tick is received.

A simple example using three counters <NUM>(<NUM>)-<NUM>(<NUM>) in a slave <NUM> is provided in <FIG>. For the sake of simplicity, it is assumed that each of the counters <NUM>(<NUM>)-<NUM>(<NUM>) has a stride size of eight (<NUM>). A first counter <NUM>(<NUM>) has a count of ten (<NUM>); a second counter <NUM>(<NUM>) has a count of twenty-four (<NUM>); and a third counter <NUM>(<NUM>) has a count of forty (<NUM>). In a conventional system, it would require forty (<NUM>) clock ticks for the third counter <NUM>(<NUM>) to count down from forty (<NUM>) to zero (<NUM>) and trigger the triggered element. However, because the present disclosure allows for dynamic stride size programming, that value may be reduced to five (<NUM>) clock ticks, while all three counters trigger the triggered element at the appropriate time. Specifically, at a first clock tick <NUM>(<NUM>), all the counters <NUM>(<NUM>)-<NUM>(<NUM>) decrement by eight (<NUM>) (i.e., the stride size) (i.e., counters are at <NUM>, <NUM>, and <NUM>, respectively). While the stride size is eight (<NUM>), the BOM master <NUM> has counters <NUM> concurrently tracking the count to the trigger event and "knows" that first counter <NUM>(<NUM>) is supposed to trigger in two (<NUM>) normal ticks, not eight (<NUM>). Accordingly, the master <NUM> sends the next clock tick <NUM>(<NUM>) at a trigger time, that is, in this example, a time two (<NUM>) clock cycles after the first clock tick <NUM>(<NUM>) corresponding to when the triggered element is to be triggered. On receipt of the clock tick <NUM>(<NUM>), all the counters <NUM>(<NUM>)-<NUM>(<NUM>) decrement by eight (<NUM>) (even though only two clock cycles have occurred). The BOM master <NUM> does not send out a clock tick at time <NUM> corresponding to eight (<NUM>) clock cycles after the first clock tick <NUM>(<NUM>) because the counters have already decremented for that time. The next clock tick <NUM>(<NUM>) occurs fourteen (<NUM>) clock cycles after clock tick <NUM>(<NUM>) and sixteen (<NUM>) clock cycles after the first clock tick <NUM>(<NUM>). Counter <NUM>(<NUM>) is inactive at this point, but counters <NUM>(<NUM>), <NUM>(<NUM>) decrement by the stride size eight (<NUM>), resulting in the counter <NUM>(<NUM>) being at zero (<NUM>) and triggering the triggered element, while counter <NUM>(<NUM>) is now at sixteen (<NUM>). Clock tick <NUM>(<NUM>) occurs eight (<NUM>) clock cycles later. Counter <NUM>(<NUM>) is now inactive, but counter <NUM>(<NUM>) decrements by the stride size eight (<NUM>) to eight (<NUM>). Finally, at clock tick <NUM>(<NUM>), thirty-two (<NUM>) clock cycles after the first clock tick <NUM>(<NUM>), counter <NUM>(<NUM>) decrements to zero (<NUM>) and triggers the triggered element.

The simple example of <FIG> is readily extrapolated to more counters and/or counters having different values than those described. Likewise, if other counters do not have count values that are integer multiples of the stride size, the BOM master <NUM> may likewise adjust when a clock tick is sent as it did for clock tick <NUM>(<NUM>) so that the counters reach the trigger threshold at the appropriate time.

Thus, after the clock tick <NUM>(<NUM>), the counters <NUM>(<NUM>)-<NUM>(<NUM>) are at zero (<NUM>) (since negative six is not an option), eight (<NUM>-<NUM>), and <NUM> (<NUM>-<NUM>), respectively. The counter <NUM>(<NUM>), having reached zero (<NUM>), triggers the triggered element.

In general, it should be appreciated that the stride size may be selected with an intention that the stride size corresponds to the largest common divisor shared between values loaded into the counters while still achieving desired power savings. This selection avoids the need to have clock ticks sent out of position as was done with the clock tick <NUM>(<NUM>). Selection of such a stride size may be done, for example, when multiple counters are loaded with count values using a single datagram that further includes the stride size and any other stride parameters. Note further, that the counters do not necessarily need to have the same stride size. However, different stride sizes may require that the value loaded into the counter be adjusted. This may be appropriate where the values loaded into the counters do not have a reasonable largest common divisor to be used as a stride size.

Note also that if multiple counters have count values that trigger inside a single stride, the master <NUM> may signal through a datagram to the slaves <NUM>(<NUM>)-<NUM>(N) that the stride size has been changed back to one (<NUM>) (i.e., the conventional stride) to handle such situations.

There may also be stride zones defined where so long as all count values on all counters are over a certain value, the stride is relatively large, but once the count value on one or more counters gets below a threshold, the stride changes to a shorter stride to accommodate the different count values. For example, if all count values are over fifty (<NUM>), then a stride size of ten (<NUM>) may be appropriate, but once a count is less than fifty (<NUM>), a stride of five (<NUM>) or three (<NUM>) may be more appropriate.

As noted above, the datagram that sets the stride may also set whether the stride is positive or negative depending on whether the counters are count-up or count-down counters. Likewise, the datagram that sets the stride may indicate an edge count instruction (e.g., whether the counters decrement/increment based on a rising edge or falling edge of the clock tick).

The stride length may also change when a new datagram is generated and sent during a stride operation. This situation is illustrated in <FIG>, where a signal flow <NUM> is shown. The signal flow <NUM> starts in a stride mode <NUM> where a clock tick is sent less frequently than once a clock cycle as described above. When the master <NUM> has a datagram <NUM> to send to a slave <NUM>, an initial message 704A may be sent which instructs the slaves <NUM>(<NUM>)-<NUM>(N) to switch back to a standard <NUM>-<NUM> stride, the datagram <NUM> is sent, and then a follow-on message 704B is sent instructing the slaves <NUM>(<NUM>)-<NUM>(N) to return to a larger stride size mode <NUM>. While messages 704A and 704B are specifically contemplated, it is possible that the mere presence of an active signal on the data line of the RFFE bus indicates the stride switch to the slaves <NUM>(<NUM>)-<NUM>(N) or there may be other ways to indicate the change without departing from the present disclosure.

<FIG> provides a flowchart of a process <NUM> associated with the dynamic stride length of the present disclosure. In this regard, the process <NUM> begins at set up or a BOM transfer when the master <NUM> provides stride parameters to the slaves <NUM>(<NUM>)-<NUM>(N) (block <NUM>). Subsequently, the master <NUM> loads a counter at a slave <NUM> with a count value using a datagram (block <NUM>). The master <NUM> sends clock ticks according to the stride length (block <NUM>). For example, each clock tick may represent a stride size of eight (<NUM>) (although other values may be chosen). The slave(s) <NUM>(<NUM>)-<NUM>(N) change counters by the stride length (block <NUM>) for every clock tick received. When the counter threshold is reached or passed, the slave activates the triggered element (block <NUM>). As noted above, use of the stride may be varied if additional datagrams are sent by the master or a counter at a slave is below a certain value.

The RFFE bus having dynamic stride size according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

Claim 1:
A master integrated circuit, IC (<NUM>) comprising:
a master two-wire bus interface coupled to a two-wire bus (<NUM>);
a clock source operative to produce a clock signal having a clock cycle, the clock source producing a clock tick once per clock cycle; and
a master control circuit (<NUM>) configured to:
set and send to a remote slave IC a stride length comprising a plurality of clock cycles; and
send only one clock tick from the clock source through the master two-wire bus interface per stride length to cause a remote counter (<NUM>) of the remote slave IC (<NUM>) to change by the plurality of clock cycles on receipt of the only one clock tick.