Patent Description:
As the use of digital data becomes wide spread, the electronic devices that use digital data, such as wireless communication devices, require larger and more effective memory systems to store and access the digital data. In addition, the number of these memory systems is increasing in system on chip designs along with increases in the clock frequency driving these memory systems. By increasing the clock frequency, memory systems are becoming a bottleneck for Power, Performance, and Area (PPA) of the chip. For such memory systems, clock latency is beneficial to meet the Setup Time on the inputs of the memory. However, clock latency has a negative impact on timing on the memory output paths. Improved timing at memory inputs and outputs can be translated into reduced power, improved system performance, or reduced system area. In other words, clock latency can improve PPA on the input side of memory, while it decreases PPA on the output side. Therefore, desired clocking system for memory system can be defined as (<NUM>) when writing to memory, higher clock latency is desirable and (<NUM>) when reading from memory, lower clock latency is desirable. However, current circuit design as well as place and route methods can only provide a constant clock latency, independent of read or write operation. This leads to a sub-optimal design depending on timing criticality on the input or output side. In other words, current designs only achieve one of the above situations for the clock latency.

Accordingly, there is a need for systems, apparatus, and methods that overcome the deficiencies of conventional approaches including the methods, system and apparatus provided hereby.

<CIT> relates to a circuit and a method for controlling precharge in a semiconductor memory apparatus. <CIT> relates to a structure for reducing power consumption of a DRAM operating as a pseudo-SRAM. <CIT> relates to pseudo SRAM and operation control methods.

The following presents a simplified summary relating to one or more aspects and/or examples associated with the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or examples, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or examples or to delineate the scope associated with any particular aspect and/or example. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects and/or examples relating to the apparatus and methods disclosed herein in a simplified form to precede the detailed description presented below.

Aspects of the present invention are provided in the independent claims. Preferred embodiments are provided in the dependent claims.

Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

A more complete appreciation of aspects of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings which are presented solely for illustration and not limitation of the disclosure, and in which:.

In accordance with common practice, the features depicted by the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Further, like reference numerals denote like features throughout the specification and figures.

The exemplary methods, apparatus, and systems disclosed herein address the industry needs, as well as other previously unidentified needs, and mitigate shortcomings of the conventional methods, apparatus, and systems. For example, a clock delay circuit according to some examples of the disclosure may provide higher clock latency (i.e. delay) during a write cycle and provide lower clock latency during a read cycle. This can be used to improve power, performance, and area on the input side without any negative impact on power, performance, and area on the output side. The clock delay circuit may use a polarity of a write enable signal to determine an operation (i.e. read or write) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line (e.g. a polarity of the write enable signal). This may improve the write operation frequency by <NUM>% in multi-GHz designs, for example. In addition, examples discussed herein may increase the maximum frequency of the products that are limited by memory clock, balance the data setup time for the farthest memory with respect to closest memory, and improve power and area factors by reducing data-path buffer size.

<FIG> illustrates an exemplary memory circuit in accordance with some examples of the disclosure. As shown in <FIG>, a memory circuit <NUM> may include a system clock <NUM> (i.e. CLK) coupled to a first clock delay circuit <NUM> (i.e. D1), a second delay clock circuit <NUM> (i.e. D2), and a third delay clock circuit <NUM> (i.e. D3). The first clock delay circuit <NUM> may be coupled to a first sequential logic circuit <NUM> (e.g. a flip flop circuit, S1) that is coupled to a first combination logic circuit <NUM> (C1),which in turn, is coupled to a memory <NUM> (e.g. a cache memory or a main memory array). The second clock delay circuit <NUM> may be coupled to the memory <NUM>. The third delay clock circuit <NUM> may be coupled to a second sequential logic circuit <NUM> (i.e. S2) along with a second combination logic circuit <NUM> (i.e. C2) that is coupled to the memory <NUM>. The second sequential logic circuit <NUM> may be coupled through additional logic circuits (not shown) to the first sequential logic circuit <NUM>.

Memory circuit <NUM> may be viewed as a closed loop between memory <NUM>, the second sequential logic circuit, and the first sequential logic circuit <NUM> where the system clock <NUM> controls synchronous operation between the memory <NUM>, the second sequential logic circuit, and the first sequential logic circuit <NUM>. In order to achieve correct functionality of the memory circuit <NUM> at a given clock frequency, two sets of timing requirements need to be checked during static timing analysis. These include (a) a setup/hold time on the input side of the memory <NUM> and (b) a setup/hold time on the second sequential logic circuit <NUM> after the memory <NUM>. The maximum clock frequency depends on the setup checks:.

<FIG> illustrates a memory circuit and a clock delay circuit in accordance with some examples of the disclosure. As shown in <FIG>, a memory circuit <NUM> includes a clock delay circuit <NUM> (e.g. second clock delay circuit <NUM>) and a memory <NUM> (e.g. memory <NUM>). The clock delay circuit <NUM> is coupled to a system clock signal <NUM> (e.g. a system clock line) and a write enable signal <NUM> (e.g. a write enable line). The clock delay circuit <NUM> includes a low skew circuit <NUM> and a high skew circuit <NUM> coupled between the system clock signal <NUM> and a logic element <NUM> (e.g. a MUX gate). The logic element <NUM> is coupled to the write enable signal <NUM> and configured to allow the logic element <NUM> to select between the low skew circuit <NUM> and the high skew circuit <NUM> to output a memory clock signal <NUM> based on the polarity of the write enable signal <NUM>. For example, if the write enable signal <NUM> has a positive polarity or has a voltage level corresponding to a logical <NUM>, then the memory circuit <NUM> is in a write mode. Conversely, if the write enable signal <NUM> has a negative polarity or has a voltage level corresponding to a logical <NUM>, then the memory circuit <NUM> is in a read mode. The low skew clock circuit <NUM> may be configured to provide a low skew memory clock signal 280R (See <FIG>) during a read operation and the high skew clock circuit <NUM> may be configured to provide a high skew memory clock signal 280W (See <FIG>) during a write operation. The memory <NUM> may include a data input <NUM> and a data output <NUM>. The low skew memory clock signal 280R may be used during a read operation to initiate reading data from the memory <NUM> on the data output <NUM> and the high skew memory clock signal 280W may be used during a write operation to initiate writing data into memory <NUM> from the data input <NUM>. The clock delay circuit <NUM> is a gating and delay circuit, which can delay a clock based on a desired operation or gate the clock when none of the operations happen.

<FIG> illustrates a timing diagram of clock skew in accordance with some examples of the disclosure. As shown in <FIG>, a timing diagram <NUM> illustrates the system clock signal <NUM>, the low skew memory clock signal 280R with a read skew <NUM>, the high skew memory clock signal 280W with a write skew <NUM>, the data output <NUM>, and the data input <NUM> for a read operation (i.e. read skew <NUM>) and a write operation (i.e. write skew <NUM>). As can be seen, the read skew <NUM> is smaller (or lower) than the write skew <NUM> that allows the memory clock signal <NUM> to have a higher delay during a write operation and a lower delay during a read operation.

<FIG> illustrates a clock delay circuit in accordance with some examples of the disclosure. As shown in <FIG>, a clock delay circuit <NUM> (e.g. second delay clock circuit <NUM>) includes a latch circuit <NUM> (e.g. an ND latch) with a clock input <NUM> (i.e. clk) coupled to the system clock signal <NUM>, a latch input <NUM> (i.e. 'd') coupled to the write enable signal <NUM>, and a latch output <NUM> (i.e. `nq'). The clock delay circuit <NUM> includes a first AND logic gate <NUM> coupled to the system clock signal <NUM> and the latch output <NUM> and configured to output the low skew memory clock signal 280R when the write enable signal is a negative polarity or a logical <NUM>. The clock delay circuit <NUM> includes a second AND logic gate <NUM> coupled to the system clock signal <NUM> and the latch output <NUM> after a first inverter <NUM> in series with a second inverter <NUM> and a third inverter <NUM>, and configured to output the high skew memory clock signal 280W when the write enable signal is a positive polarity or a logical <NUM>. The clock delay circuit <NUM> includes an OR logic gate <NUM> coupled to the low skew memory clock signal 280R and the high skew memory clock signal 280W that outputs the memory clock signal <NUM> to a memory (not shown) based on the polarity or logical value of the write enable signal <NUM> to enable the memory clock signal <NUM> to equal the high skew memory clock signal 280W when the write enable signal is a positive polarity or a logical <NUM> (e.g. during a write operation) and the low skew memory clock signal 280R when the write enable signal is a negative polarity or a logical <NUM> (e.g. during a read operation). While three inverters are shown, it should be understood that more or less inverters may be used depending on the timing requirements. The number of inverters is configurable according to an adjustable third clock delay. In addition, the clock delay circuit <NUM> can be implemented as clock gating cell with configurable clock shaping for memory depending on a read or a write operation.

<FIG> illustrates another clock delay circuit in accordance with some examples of the disclosure. As shown in <FIG>, a clock delay circuit <NUM> (e.g. second clock delay circuit <NUM>) includes a clock enable signal <NUM> coupled to a first AND logic gate <NUM> and a second AND logic gate <NUM> as an input, and a write enable signal <NUM> coupled to the first AND logic gate <NUM> through a first inverter <NUM> and directly to the second AND logic gate <NUM> as an input. The clock delay circuit <NUM> includes a system clock signal <NUM> coupled as an input to a first clock gating cell <NUM> and a second clock gating cell <NUM>. The first clock gating cell <NUM> includes a clock enable input <NUM> (e.g. CLK_EN) coupled to the first AND logic gate <NUM> and be configured to generate a low skew memory clock signal 280R. The first clock gating cell <NUM> is configured to provide a first delay or first latency to the low skew memory clock signal 280R. The second clock gating cell <NUM> includes a clock enable input <NUM> (e.g. CLK_EN) coupled to the second AND logic gate <NUM> and be configured to generate a high skew memory clock signal 280W. The second clock gating cell <NUM> may be configured to provide a second delay or second latency to the high skew memory clock signal 280W. The clock delay circuit <NUM> includes an OR logic gate <NUM> configured to directly input the low skew memory clock signal 280R and input the high skew memory clock signal 280W after a first inverter <NUM>, a second inverter <NUM>, and a third inverter <NUM>, and configured to output a memory clock signal <NUM> to a memory (not shown) based on the polarity or logical value of the write enable signal <NUM> to enable the memory clock signal <NUM> to equal the high skew memory clock signal 280W when the write enable signal is a positive polarity or a logical <NUM> (e.g. during a write operation) and the low skew memory clock signal 280R when the write enable signal is a negative polarity or a logical <NUM> (e.g. during a read operation). The clock enable <NUM> may be used to control application of the system clock signal <NUM> to a memory operation or disable the clock delay circuit <NUM>. The write enable signal <NUM> may be used as the enable for the two clock gating cells <NUM> and <NUM>. Each clock gating cell <NUM> and <NUM> may generate a separate clock for each of the read/write operation of memory. The generated clocks may be skewed according to the desired timing requirement.

<FIG> illustrates still another clock delay circuit in accordance with some examples of the disclosure. As shown in <FIG>, a clock delay circuit <NUM> (e.g. second clock delay circuit <NUM>) may include a first latch circuit <NUM> (e.g. an ND latch) with a clock input <NUM> (i.e. clk) coupled to the system clock signal <NUM>, a latch input <NUM> (i.e. 'd') coupled to the write enable signal <NUM>, and a first latch output <NUM> (i.e. 'q'). The clock delay circuit <NUM> may also include a second latch circuit <NUM> (e.g. an ND latch) with the clock input <NUM> (i.e. clk) coupled to the system clock signal <NUM>, a latch input <NUM> (i.e. 'd') coupled to a first inverter <NUM> and then coupled to the write enable signal <NUM>, and a second latch output <NUM> (i.e. 'q'). The clock delay circuit <NUM> may also include a first NAND logic gate <NUM> coupled to the system clock signal <NUM> through a inverter or buffer <NUM> and a inverter or buffer <NUM> and the first latch output <NUM> and configured to output the high skew memory clock signal 280W when the write enable signal is a positive polarity or a logical <NUM>. The clock delay circuit <NUM> may also include a second NAND logic gate <NUM> coupled to the system clock signal <NUM> and the second latch output <NUM>, and configured to output the low skew memory clock signal 280R when the write enable signal is a negative polarity or a logical <NUM>. The clock delay circuit <NUM> may also include a third NAND logic gate <NUM> coupled to the low skew memory clock signal 280R and the high skew memory clock signal 280W that outputs the memory clock signal <NUM> to a memory (not shown) based on the polarity or logical value of the write enable signal <NUM> to enable the memory clock signal <NUM> to equal the high skew memory clock signal 280W when the write enable signal is a positive polarity or a logical <NUM> (e.g. during a write operation) and the low skew memory clock signal 280R when the write enable signal is a negative polarity or a logical <NUM> (e.g. during a read operation).

<FIG> illustrates various electronic devices that may be integrated with any of the aforementioned memory circuits (e.g. memory circuit <NUM> or <NUM>) or clock delay circuits (e.g. clock delay circuit <NUM>, <NUM>, or <NUM>), such as an integrated device, semiconductor device, integrated circuit, or die in accordance with some examples of the disclosure. For example, a mobile phone device <NUM>, a laptop computer device <NUM>, and a fixed location terminal device <NUM> may include an integrated device <NUM> as described herein. The integrated device <NUM> may be, for example, any of the integrated circuits, dies, or integrated devices described herein. The devices <NUM>, <NUM>, <NUM> illustrated in <FIG> are merely exemplary. Other electronic devices may also feature the integrated device <NUM> including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, processes, features, and/or functions illustrated in <FIG> may be rearranged and/or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be noted that <FIG> and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations, <FIG> and its corresponding description may be used to manufacture, create, provide, and/or produce integrated devices. In some implementations, a device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package on package (PoP) device, and/or an interposer.

In this description, certain terminology is used to describe certain features. The term "mobile device" can describe, and is not limited to, a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an automotive device in an automotive vehicle, and/or other types of portable electronic devices typically carried by a person and/or having communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). Further, the terms "user equipment" (UE), "mobile terminal," "mobile device," and "wireless device," can be interchangeable.

The wireless communication between electronic devices can be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE) or other protocols that may be used in a wireless communications network or a data communications network.

" Any details described herein as "exemplary" is not to be construed as advantageous over other examples. Likewise, the term "examples" does not mean that all examples include the discussed feature, advantage or mode of operation. Furthermore, a particular feature and/or structure can be combined with one or more other features and/or structures. Moreover, at least a portion of the apparatus described hereby can be configured to perform at least a portion of a method described hereby.

The terminology used herein is for the purpose of describing particular examples and is not intended to be limiting of examples of the disclosure. It will be further understood that the terms "comprises", "comprising," "includes," and/or "including," when used herein, specify the presence of stated features, integers, actions, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, actions, operations, elements, components, and/or groups thereof.

It should be noted that the terms "connected," "coupled," or any variant thereof, mean any connection or coupling, either direct or indirect, between elements, and can encompass a presence of an intermediate element between two elements that are "connected" or "coupled" together via the intermediate element.

Any reference herein to an element using a designation such as "first," "second," and so forth does not limit the quantity and/or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and/or instances of an element. Also, unless stated otherwise, a set of elements can comprise one or more elements.

Nothing stated or illustrated depicted in this application is intended to dedicate any component, action, feature, benefit, advantage, or equivalent to the public, regardless of whether the component, action, feature, benefit, advantage, or the equivalent is recited in the claims.

In the detailed description above it can be seen that different features are grouped together in examples. This manner of disclosure should not be understood as an intention that the claimed examples have more features than are explicitly mentioned in the respective claim. Rather, the situation is such that inventive content may reside in fewer than all features of an individual example disclosed. Therefore, the following claims should hereby be deemed to be incorporated in the description, wherein each claim by itself can stand as a separate example. Although each claim by itself can stand as a separate example, it should be noted that-although a dependent claim can refer in the claims to a specific combination with one or a plurality of claims-other examples can also encompass or include a combination of said dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein, unless it is explicitly expressed that a specific combination is not intended. Furthermore, it is also intended that features of a claim can be included in any other independent claim, even if said claim is not directly dependent on the independent claim.

It should furthermore be noted that methods disclosed in the description or in the claims can be implemented by a device comprising means for performing the respective actions of this method.

Furthermore, in some examples, an individual action can be subdivided into a plurality of sub-actions or contain a plurality of sub-actions. Such sub-actions can be contained in the disclosure of the individual action and be part of the disclosure of the individual action.

Claim 1:
A memory circuit (<NUM>) comprising:
a first clock signal (<NUM>);
a write enable signal (<NUM>), wherein the write enable signal has a polarity;
a low skew circuit (<NUM>) coupled to the first clock signal, the low skew circuit, configured to output a second clock signal (280R) different from the first clock signal, the second clock signal comprising a first clock skew (<NUM>);
a high skew circuit (<NUM>) coupled to the first clock signal, the high skew circuit, configured to output a third clock signal (280W) different from the second clock signal, the third clock signal comprising a second clock skew (<NUM>) larger than the first clock skew;
a selection circuit (<NUM>) coupled to the low skew circuit, the high skew circuit, and the write enable signal, the selection circuit configured to output the second clock signal when the write enable signal has a first polarity or output the third clock signal when the write enable signal has a second polarity different from the first polarity; and
a memory (<NUM>) coupled to the selection circuit.