Patent Description:
The document <CIT> (also published as <CIT>) discloses the production of transistors, particularly JoFETs, including source and drain made of a material capable of having superconducting properties. In this document, the superconducting regions are produced by the deposition of a metal material above a semiconductor material, and then a thermal annealing forming regions comprising a compound of the metal material and the semiconductor material.

<CIT> discusses the use of dummy gates in semiconductor manufacturing.

<CIT> shows an earlier generation superconducting transistor with a contiguous superconducting source-drain channel structure with a gate positioned over this structure.

It could be advantageous to use superconducting materials having a high critical temperature (Tc) because with such materials, a larger BCS (Bardeen-Cooper-Schrieffer) energy gap can be obtained, leading to a higher supercurrent, for a given temperature. However, the process disclosed in the document <CIT> is not adapted for several superconducting material having a high Tc, like V<NUM>Si.

Therefore, there is a need to propose a new method for producing superconducting transistors, advantageously Josephson Field-Effect Transistors, which can be used for a large number of superconducting materials, especially for high-Tc superconducting materials.

It is thus proposed a method for producing a superconducting transistor comprising at least the steps of:.

This method thus proposes a gate-last process which enables to obtain a gate that is self-aligned with the superconducting electrodes.

Another advantage is that this method is compatible with many High-Tc superconducting material like metal silicide.

A further advantage is that the superconducting electrodes are produced against the first part of the semiconducting layer which forms the weak link between the superconducting electrodes, making it possible to obtain a Josephson effect between the superconducting electrodes.

Advantageously, the method may be such that:.

Thanks to these cavities, which can be filled by a dielectric material before the etching of the dummy gate, the superconducting material of the superconducting electrodes is not damaged during the removal of the dummy gate.

According to a first embodiment, the method may further comprise, before the production of the superconducting electrodes, a partial etching of second parts of the semiconducting layer contiguous to the first part of the semiconducting layer such that a part of the side edges of the first part of the semiconducting layer is exposed,
and the first superconducting material layer may then be deposited such that the second parts of the first superconducting material layer are arranged against the part of the side edges of the first part of the semiconducting layer.

According to a variant of the first embodiment:.

The configuration according to this second embodiment is advantageous because the first parts of the superconducting electrodes made as proposed in this embodiment enable to obtain a better interface with the semiconducting layer toward Andreev Reflection, and the second parts of the superconducting electrodes can be produced with a high-Tc superconducting material.

The method may further comprise, between the production of the superconducting electrodes and the production of the lateral spacers, a conformal deposition of a dielectric layer on the first superconducting material layer, the lateral spacers being produced against parts of the dielectric layer.

In an advantageous configuration, the dielectric layer may also be deposited such that the cavities are filled by the dielectric layer.

The method may further comprise, after the production of the gate, a step of producing electrical contacts on the gate and on the superconducting electrodes, the electrical contacts comprising advantageously at least a second superconducting material (which may be similar or not to the first superconducting material).

The method may further comprise, between the production of the lateral spacers and the removal of the dummy gate, an etching of parts of the first superconducting material layer arranged outside an active zone of the superconducting transistor.

Throughout the document, the term "on" is used irrespective of the spatial direction of the component to which the term refers. For example, in the characteristic "on at least a first surface of a component", this first surface is not necessarily directed upwards, but may be a surface facing in any other direction. Furthermore, the arrangement of a first component on a second component is to be understood as possibly being the arrangement of the first component directly against the second component, without any intermediate component between the first and second components, or as possibly being the arrangement of the first component on the second component with one or more intermediate components arranged between the first and second components. Furthermore, the arrangement of a first component on a second component does not necessarily imply that the first component is directed upwards and the second component is directed downwards.

The present invention will be better understood on reading the description of examples of embodiments given purely by way of illustration and by no means limitatively with reference to the annexed drawings wherein:.

Identical, similar or equivalent parts of the various figures described hereunder bear the same numerical references so as to facilitate the transition from one figure to another.

The different parts shown in the figures are not necessarily presented in a uniform scale, in order to make the figures more legible.

The various possibilities (variants and embodiments) should be understood as not being exclusive of each other and may be combined with each other.

A method for producing a superconducting transistor <NUM> according to a first embodiment is described below in relation with <FIG>. In these figures, the production of only one transistor <NUM> is shown. However, the method is implemented to produce simultaneously several superconducting transistors on the same substrate.

In the example shown and disclosed in relation with <FIG>, the superconducting transistor <NUM> corresponds to a Josephson field-effect transistor.

As shown in <FIG>, a substrate <NUM> is provided. In the example shown in <FIG>, the substrate <NUM> is a semiconductor-on-insulator substrate, advantageously a Silicon-On-Insulator (SOI) substrate, comprising a bulk layer <NUM>, a dielectric layer <NUM> and a semiconducting layer <NUM> forming a superficial layer of the substrate <NUM>. The bulk layer <NUM> may comprise silicon. The dielectric layer <NUM>, arranged between the bulk layer <NUM> and the semiconducting layer <NUM>, may correspond to a BOX, or buried-oxide, comprising SiO<NUM>. The semiconducting layer <NUM> may comprise silicon. Other materials may be used for the layers <NUM>, <NUM> and <NUM>.

For example, the thickness of the bulk layer <NUM> may be equal to several hundreds of microns, the thickness of the dielectric layer <NUM> may be between <NUM> and <NUM>, and the thickness of the semiconducting layer <NUM> may be between <NUM> and <NUM>, or thicker than <NUM>, and advantageously equal to <NUM>.

Insulation trenches <NUM> are produced in the substrate <NUM> in order to delimit the active zone in which the transistor <NUM> is intended to be produced. In the example here described, the trenches correspond to STI (Shallow Trench Isolation) trenches and are produced through the semiconducting layer <NUM>, the dielectric layer <NUM> and a part of the thickness of the bulk layer <NUM>.

A stack of layers intended to be used for the production of a dummy gate is then deposited on the substrate <NUM>, i.e. on the semiconducting layer <NUM> and on the top of the insulation trenches <NUM>. This stack includes a first layer <NUM> comprising a dielectric material, e.g. SiO<NUM>, and a second layer <NUM> comprising polycrystalline silicon or silicide for example. The thickness of the first layer <NUM> may be between <NUM> and <NUM>, and the thickness of the second layer <NUM> may be between <NUM> and <NUM>, and advantageously between <NUM> and <NUM>. The materials of the layers <NUM>, <NUM> are chosen such that they can be etched selectively one to the other. As explained below, the materials of the layers <NUM>, <NUM> are also chosen such that they can be selectively etched against the materials which will surround the dummy gate.

A hard mask layer <NUM> is then deposited on the second layer <NUM>. In the example here described, the hard mask layer <NUM> comprises a nitride insulator, e.g. SiNx.

The hard mask layer <NUM>, and then the layers <NUM> and <NUM>, are etched according to the desired pattern (in a plane parallel to (X,Y) plane) of the dummy gate. The obtained dummy gate, referenced <NUM>, is shown in <FIG>, and comprises a first portion <NUM> corresponding to a remaining portion of the first layer <NUM>, and a second portion <NUM> corresponding to a remaining portion of the second layer <NUM>. The hard mask used to etch the layers <NUM> and <NUM> is referenced <NUM>. The dummy gate <NUM> is located on a first part <NUM> of the semiconducting layer <NUM>. Second parts of the semiconducting layer <NUM> which are contiguous to the first part <NUM> (and thus which are not covered by the dummy gate <NUM>) are referenced <NUM>. In <FIG>, the first part <NUM> and the second parts <NUM> of the semiconducting layer <NUM> are symbolically delimited one to the other by dotted lines.

The second parts <NUM> of the semiconducting layer <NUM> are then partially etched, i.e. only a part of the thickness (dimension parallel to Z axis) of the material of the second parts <NUM> is etched. This etching may correspond to a dry etching carried out using plasma, or to oxidation / oxide removal steps. After this partial etching, a part of side edges <NUM> of the first part <NUM> of the semiconducting layer <NUM> are exposed, as shown in <FIG>. This partial etching of the second parts <NUM> of the semiconducting layer <NUM> creates locations <NUM> on the remaining portions of the second parts <NUM> of the semiconducting layer <NUM> and wherein superconducting electrodes of the transistor <NUM> are intended to be produced. The part of the thickness of the second parts <NUM> of the semiconducting layer <NUM> which is etched is chosen such that it corresponds to the thickness of the superconducting electrodes which will be produced, and may be between <NUM> % and <NUM> % of the initial thickness of the semiconducting layer <NUM>.

An etching, e.g. an isotropic wet etching using HF solution, of side edges of the first portion <NUM> of the dummy gate <NUM> is then carried out, creating cavities <NUM> between the second portion <NUM> of the dummy gate <NUM> and the first part <NUM> of the semiconducting layer <NUM>. The depth of each of the cavities <NUM> (dimension parallel to the X axis shown in <FIG>), which corresponds to the lateral encroachment etched in the material of the first portion <NUM> on each side of the dummy gate <NUM>, may be between <NUM> and <NUM>. As shown in <FIG>, this etching also etches top of the dielectric material of the insulation trenches <NUM>. The hard mask <NUM> is then removed.

Superconducting electrodes of the transistor <NUM> are then produced such that the side edges <NUM> of the first part <NUM> of the semiconducting layer <NUM> are arranged against parts of the superconducting electrodes. In the first embodiment, the superconducting electrodes are produced by a deposition of a layer <NUM> comprising a first superconducting material, at least in locations <NUM> of the electrodes and against side edges <NUM> of the second portion <NUM> of the dummy gate <NUM>. In the example shown in <FIG>, the first superconducting material layer <NUM> is also deposited on top of the dummy gate <NUM>. The parts of the first superconducting material layer <NUM> deposited against side edges <NUM> of the second portion <NUM> of the dummy gate <NUM> are named first parts <NUM> of the first superconducting material layer <NUM>. Second parts <NUM> of the first superconducting material layer <NUM> located in the superconducting electrode locations <NUM> correspond to the superconducting electrodes of the transistor <NUM> in this first embodiment.

The first superconducting material of the layer <NUM> may correspond to at least one of the following metal silicides: CoSi<NUM>, V<NUM>Si, PtSi, Nb<NUM>Si. In this case, an anneal is then carried out to convert the deposited metal films to superconducting silicide films. It may also correspond to TiN or any other superconducting material which can be deposited as previously described. If the first superconducting material of the layer <NUM> is TiN, no subsequent anneal is needed. The thickness of the first superconducting material layer <NUM> may be between <NUM> and <NUM>, and advantageously between <NUM> and <NUM>.

Advantageously, the deposition of the first superconducting material layer <NUM> is carried out such that this layer <NUM> is not deposited in the cavities <NUM>, i.e. such that the layer <NUM> is not deposited on the first part <NUM> of the semiconducting layer <NUM>. Thus, the deposition of the layer <NUM> carried out is not a conformal deposition. For example, the first superconducting material layer <NUM> may be deposited by carrying out a physical deposition, e.g. PVD (Physical Vapor Deposition), or low-conformality CVD (Chemical Vapor Deposition).

A conformal deposition of a dielectric layer <NUM> is then carried out on the first superconducting material layer <NUM>. The dielectric layer <NUM> may correspond to an oxide layer, e.g. comprising at least one of the following materials: SiOX, HfOX, AlOX, etc., deposited by means of ALD (Atomic Layer Deposition) for example, or PE-CVD (Plasma Enhanced Chemical Vapor Deposition). In the example here described, the layer <NUM> comprises SiO<NUM>. The thickness of the dielectric layer <NUM> and the type of deposition implemented are chosen such that the dielectric layer <NUM> forms a continuous layer arranged on the second parts <NUM> of the first semiconducting material layer <NUM> and filling the cavities <NUM>.

Lateral spacers <NUM> are then produced next to the first parts <NUM> of the layer <NUM>, here against the parts of the dielectric layer <NUM> which are arranged against these first parts <NUM>, and on the second parts <NUM> of the first superconducting material layer <NUM>. The lateral spacers <NUM> may be obtained by the deposition of a dielectric material layer, e.g. a nitride layer such as a SiN layer, and a partial etching of this layer such that remaining parts of this layer correspond to the lateral spacers <NUM>. The deposition of the nitride material layer may correspond to an ALD (Atomic Layer Deposition) or a CVD, and the thickness of the deposited nitride layer (dimension according to X axis shown in <FIG>) may be between <NUM> and <NUM>.

A resist mask <NUM> covering an active zone of the transistor <NUM>, i.e. covering parts of the dielectric layer <NUM> arranged against the dummy gate <NUM> and on the second parts <NUM> of the layer <NUM>, is then produced (see <FIG>).

As shown in <FIG>, an etching of the parts of the dielectric layer <NUM> and of the first superconducting material layer <NUM> arranged next to the locations of the electrodes <NUM>, outside the active zone of the transistor <NUM>, is then carried out. The type of this etching is adapted to the materials to be etched, and may correspond to a dry etching (e.g. plasma etching) and/or a wet etching.

The resist mask <NUM> and the parts of the dielectric layer <NUM> which are not protected by the lateral spacers <NUM> are then removed by etching (see <FIG>). After this etching, the second parts <NUM> of the first superconducting material layer <NUM>, i.e. the superconducting electrodes, are exposed. The part of the dielectric layer <NUM> arranged on top of the dummy gate <NUM> is then removed.

A nitride layer <NUM> is then deposited such that it covers all the elements produced on the substrate <NUM>, and a thick oxide layer <NUM> is then deposited on the nitride layer <NUM>. The total thickness of the layers <NUM>+<NUM> is larger than the sum of the thicknesses of the dummy gate <NUM> and the dielectric layer <NUM>. A planarization, e.g. CMP (Chemical-Mechanical Polishing), is then carried out with stop on top of the dummy gate <NUM>, i.e. on the second portion <NUM> of the dummy gate <NUM>. The structure obtained at this stage of the method is shown in <FIG>.

As a variant, it is possible to deposit the oxide layer <NUM> only, without the nitride layer <NUM>.

As shown in <FIG>, the second portion <NUM> of the dummy gate <NUM> is then removed by etching selectively the second portion <NUM> of the dummy gate <NUM> in view of the other exposed materials (the first superconducting material of the first parts <NUM> of the layer <NUM>, the oxide layer <NUM>, the dielectric layer <NUM>, the first portion <NUM> of the dummy gate <NUM>). As an example, this etching may correspond to a wet etching carried out with a TMAH (Tetramethylammonium hydroxide) solution.

As shown in <FIG>, the removal of the dummy gate <NUM> is finished by removing the first portion <NUM> of the dummy gate <NUM>, e.g. with a wet etching carried out with an HF (hydrofluoric acid) solution. This etching also removes the parts of the dielectric layer <NUM> contiguous to the first portion <NUM> of the dummy gate <NUM> and covered by the first parts <NUM> of the first superconducting material layer <NUM>. Then these first parts <NUM> are removed, e.g. by lift-off. Thanks to the dielectric material of the dielectric layer <NUM> deposited in the cavities <NUM>, the removal of the first parts <NUM> of the first superconducting material layer does not damage the second parts <NUM> of the first superconducting material layer <NUM>. A surface cleaning, e.g. with a HNO<NUM> solution or a H<NUM>SO<NUM> + H<NUM>O<NUM> solution, is then carried out.

The removal of the dummy gate <NUM> and of the first parts <NUM> of the first superconducting material layer <NUM> forms a gate location <NUM> arranged between the lateral spacers <NUM> (and between remaining parts of the dielectric layer <NUM> in the example here described) and above the first part <NUM> of the semiconducting layer <NUM>, and also above parts of the superconducting electrodes (corresponding to the second parts <NUM> of the first superconducting material layer <NUM>) contiguous to the first part <NUM> of the semiconducting layer <NUM>.

As a variant, it is possible to completely etch the dielectric layer <NUM> and the first portion <NUM> of the dummy gate <NUM>. The first parts <NUM> of the layer <NUM> are thus removed by lift-off.

A gate is then produced in the gate location <NUM> (see <FIG>). The gate is made, in this example, by a conformal deposition of a dielectric layer and a deposition of a conductive material which, together, fill the gate location <NUM>. The parts of these layers deposited outside the gate location <NUM> are then removed by CMP. The remaining parts of these layers correspond to a gate dielectric <NUM> and a gate conductor <NUM> forming together the gate of the transistor <NUM>. The gate dielectric <NUM> may comprise e.g. a high-K material or SiO<NUM>, and the gate conductor <NUM> may comprise at least one metal, doped polycrystalline semiconductor or advantageously a second superconducting material (which may correspond or not to the first superconducting material).

A PMD (Pre-Metal Dielectric) layer <NUM> is then deposited. This PMD layer may comprise the same dielectric material as the oxide layer <NUM>. Contact holes <NUM> are then etched through the PMD layer <NUM> to expose the top of the gate conductor <NUM>, and also through the oxide layer <NUM> to expose the top of the superconducting electrodes formed by the second parts <NUM> of the first superconducting material layer <NUM> (see <FIG>).

Electrical contacts <NUM> are then produced by deposition of at least one conductive material in the contact holes <NUM> (see <FIG>). Advantageously, the electrical contacts <NUM> comprise a third superconducting material which may be similar or not to the first superconducting material of the layer <NUM> and/or to the second superconducting material of the gate conductor <NUM>. However, it is possible to make electrical contacts <NUM> with other types of conductive materials: doped polycrystalline silicon, doped SiGe, TiN, TaN, metal silicide, W, TiW, Al, Cu, etc..

In the first embodiment previously described, the semiconducting layer <NUM> is etched only through a part of its total thickness such that second parts <NUM> are kept next to the first part <NUM> arranged below the dummy gate <NUM>. In a variant, the second parts <NUM> of the semiconducting layer <NUM> which are not covered by the dummy gate <NUM> may be completely etched. In this case, the first superconducting material layer <NUM>/<NUM> is deposited directly on parts of the dielectric layer <NUM> exposed after the etching of the second parts <NUM> of the semiconducting layer <NUM> and the second parts <NUM> of the first superconducting material layer <NUM> are arranged against the side edges <NUM> of the first part <NUM> of the semiconducting layer <NUM>. The transistor <NUM> thus obtained is shown in <FIG>. In this variant, it is also possible, as previously described for the first embodiment, to completely etch the dielectric layer <NUM> and the first portion <NUM> of the dummy gate <NUM> before producing the gate.

A method for producing a transistor <NUM> according to a second embodiment is described below in relation to <FIG>. In these figures, the production of one transistor <NUM> is shown. However, this method is implemented to produce simultaneously several transistors on the same substrate.

Similarly to the first embodiment, the substrate <NUM> is provided. The insulation trenches <NUM> are produced in the substrate <NUM> and the stack of layers intended to be used for the production of the dummy gate <NUM> is then deposited. The hard mask layer is then deposited. The hard mask layer and the dummy gate stack layers are then etched according to the desired pattern of the dummy gate <NUM>.

Contrary to the first embodiment wherein the second parts <NUM> of the semiconducting layer <NUM> are partially or completely etched, the method according to the second embodiment does not include an etching of these second parts <NUM>. In this second embodiment, the production of the superconducting electrodes comprises doping and annealing of the second parts <NUM> of the semiconducting layer <NUM>. In the example here described, the doping of the second parts <NUM> correspond to a boron implantation, symbolically shown by arrows <NUM> in <FIG>. The annealing which is carried out after the doping activates the implanted dopants and may correspond to a laser annealing. These steps create, in the second parts <NUM> of the semiconducting layer <NUM>, first parts (referenced <NUM> in <FIG>) of the superconducting electrodes against the side edges <NUM> of the first part <NUM> of the semiconducting layer <NUM>, these first parts <NUM> being arranged in the superconducting electrode locations <NUM>.

As previously described for the first embodiment, an etching of side edges of the first portion <NUM> of the dummy gate <NUM> is then carried out, creating the cavities <NUM> between the second portion <NUM> of the dummy gate <NUM> and the first part <NUM> of the semiconducting layer <NUM>. The hard mask <NUM> is then removed.

The second parts of the superconducting electrodes of the transistor <NUM> are then produced by depositing the first superconducting material layer <NUM> on the first parts <NUM> of the superconducting electrodes (i.e. on the superconducting electrodes locations <NUM>) and against the side edges <NUM> of the second portion <NUM> of the dummy gate <NUM> (see <FIG>). In the example shown in <FIG>, the first superconducting material layer <NUM> is also deposited on top of the dummy gate <NUM>. The second parts <NUM> of the first superconducting material layer <NUM> located above the first parts <NUM> of the superconducting electrodes form the second parts of the superconducting electrodes of the transistor <NUM>. Similarly to the first embodiment, the deposition of the first superconducting material layer <NUM> is carried out such that this first superconducting material layer <NUM> is not deposited in the cavities <NUM>, i.e. such that the layer <NUM> is not deposited on the first part <NUM> of the semiconducting layer <NUM>. In this second embodiment, because the superconducting electrodes also comprise the first parts <NUM>, the first superconducting material of the layer <NUM> may be Ta or TaN, or one of the superconducting material previously described in relation with the first embodiment.

The steps of the method according to the second embodiment which are then carried out are similar to those previously described for the first embodiment, i.e.:.

The transistor <NUM> obtained at the end of the method according to the second embodiment is shown in <FIG>.

The different options and variants previously disclosed in relation with the first embodiment can be applied to the second embodiment. Especially, it is possible to form the gate location <NUM> by completely etching the dielectric layer <NUM> and the first portion <NUM> of the dummy gate <NUM>. The first parts <NUM> of the layer <NUM> are thus removed by lift-off.

In the previously described embodiments, the substrate <NUM> corresponds to a SOI substrate. Alternatively, the substrate <NUM> may correspond to a semiconductor bulk substrate, e.g. a silicon bulk substrate.

In the previously described embodiments, the first part <NUM> of the dummy gate <NUM> is etched and the cavities <NUM> are filled with the material of the dielectric layer <NUM>. As a variant, it is possible to not etch the first part <NUM> of the dummy gate <NUM>. In this case, the first and second parts <NUM>, <NUM> of the first superconducting material layer <NUM> are not separated by the cavities <NUM>. In this case, during the production of the gate location <NUM>, the etching of the first parts <NUM> of the first superconducting material layer <NUM> has to be carefully implemented to cause as little damage as possible to the second parts <NUM> of the first superconducting material layer <NUM>.

In another variant, when the first part <NUM> of the dummy gate <NUM> is not etched, it is possible to not deposit the dielectric layer <NUM> and to make the lateral spacers <NUM> directly against the parts <NUM> of superconducting material.

Claim 1:
Method for producing a superconducting transistor (<NUM>), comprising at least the steps of:
- producing a dummy gate (<NUM>) on a first part (<NUM>) of a semiconducting layer (<NUM>);
- producing superconducting electrodes (<NUM>, <NUM>) such that the first part (<NUM>) of the semiconducting layer (<NUM>) comprises side edges (<NUM>) arranged against parts of the superconducting electrodes (<NUM>, <NUM>), the step of producing superconducting electrodes (<NUM>, <NUM>) comprising at least a deposition of a first superconducting material layer (<NUM>) having first parts (<NUM>) arranged against side edges (<NUM>) of the dummy gate (<NUM>) and second parts (<NUM>) forming the superconducting electrodes (<NUM>, <NUM>) or being parts of the superconducting electrodes (<NUM>, <NUM>);
- producing lateral spacers (<NUM>) next to the first parts (<NUM>) of the first superconducting material layer (<NUM>) and on the second parts (<NUM>) of the first superconducting material layer (<NUM>);
- removing the dummy gate (<NUM>) and the first parts (<NUM>) of the first superconducting material layer (<NUM>), creating a gate location (<NUM>) arranged between the lateral spacers (<NUM>) and above the first part (<NUM>) of the semiconducting layer (<NUM>) and above said parts of the superconducting electrodes (<NUM>, <NUM>);
- producing a gate (<NUM>, <NUM>) in the gate location (<NUM>).