Patent Description:
To facilitate communication between two devices, a connection port may be usually disposed in each device, and the connection ports of the two devices are connected by using a connection component, to implement connection between the two devices. The connection component may be a connection cable. The connection component may be a component for implementing a connection between a television and a set top box, a component for implementing a connection between a computer and a display, or the like.

With continuous development of electronic technologies, a data signal between devices has an increasingly high transmission rate. If the data signal between the devices has a relatively high transmission rate, when the devices are connected by using a connection port, relatively strong surge is generated in a circuit. The generated surge may cause damage to an interface chip in the device. In the prior art, to reduce damage caused by the surge to the interface chip, a transient voltage suppressor (Transient Voltage Suppressor, TVS for short) is usually disposed in the device, to protect the interface chip by using the TVS transistor. Currently, to improve a protection capability of the TVS transistor for the interface chip, power of the TVS transistor is usually increased. When the power of the TVS transistor is relatively high, a relatively high parasitic capacitance is generated in the TVS transistor. The parasitic capacitance affects quality of the data signal transmitted between the devices, resulting in relatively poor quality of the data signal transmitted between the devices. <CIT> relates an electrostatic protection circuit, which includes : output interface, electrostatic protection module and IO chip, two signal lines of IO chip are connected with the electrostatic protection module through the difference wire pair respectively, electrostatic protection module ground connection, the IO chip pass through the connector cable with the output interface is connected. <CIT> relates to a high speed and high frequency signal port surge protection circuit. The circuit comprises a surge discharge circuit, a decoupling circuit, and a voltage limiting circuit. The decoupling circuit is serially connected with the voltage limiting circuit to form a series circuit. The series circuit is connected in parallel with the surge discharge circuit. The surge discharge circuit is used to discharge surge energy. The decoupling circuit is used to control the voltage across two ends of the voltage limiting circuit in the surge generation process. Another example of prior art can be found in <CIT>.

Embodiments of the present invention provide an interface protection circuit, so as to improve a protection capability for an interface chip while ensuring quality of a data signal transmitted between devices.

The present application discloses an interface protection circuit, comprising a capacitor (<NUM>) and a transient voltage suppressor, TVS, transistor (<NUM>), wherein a first end of the capacitor (<NUM>) is connected to a connection port of a protected device (<NUM>, <NUM>), and a second end of the capacitor (<NUM>) is connected to a first end of the TVS transistor (<NUM>) and an interface chip of the protected device; and a second end of the TVS transistor (<NUM>) is grounded, wherein the TVS transistor is connected in parallel with the interface chip, and wherein a clamping voltage of the TVS transistor (<NUM>) is greater than a maximum voltage of a data signal transmitted on the connection port.

<FIG> is a schematic diagram of an application scenario of an interface protection circuit according to the present invention. Referring to <FIG>, the interface protection circuit includes a first device <NUM>, a second device <NUM>, and a connection component <NUM>. A first interface chip, a first interface protection circuit, and a connection port A are disposed in the first device <NUM>. A second interface chip, a second interface protection circuit, and a connection port D are disposed in the second device <NUM>. A connection port B and a connection port C are disposed in the connection component <NUM>. Optionally, the first device <NUM> may be a computer, and correspondingly, the second device <NUM> may be a display. Optionally, the first device <NUM> may be a television, and correspondingly, the second device <NUM> may be a set top box. Certainly, the connection component <NUM> and the first device <NUM> or the second device <NUM> may be an integrated device. When the connection component <NUM> and the first device <NUM> are an integrated device, the connection component <NUM> and the first device <NUM> may be removable disks. Optionally, the connection component <NUM> may be a connection cable, or the like.

The first device <NUM> can be connected to the second device <NUM> by using the connection component <NUM>. When the first device <NUM> needs to be connected to the second device <NUM>, the connection port A of the first device <NUM> may be connected to the connection port B of the connection component <NUM>, and the connection port D of the second device <NUM> may be connected to the connection port C of the connection component <NUM>.

After the first device <NUM> is connected to the second device <NUM> by using the connection component <NUM>, communication between the first device <NUM> and the second device <NUM> may be implemented by using the first interface chip, the first interface protection circuit, the connection component <NUM>, the second interface protection circuit, and the second interface chip. When the first device <NUM> sends data to the second device <NUM>, the second interface chip may be protected by using the second interface protection circuit. When the second device <NUM> sends data to the first device <NUM>, the first interface chip may be protected by using the first interface protection circuit.

It should be further noted that interface protection circuits in all devices have similar structures. Using a structure of an interface protection circuit in any device as an example, the following describes in detail the interface protection circuit shown in this application based on specific embodiments. The following specific embodiments may be mutually combined, and same or similar concepts or processes may not be repeatedly described in some embodiments.

<FIG> is schematic structural diagram <NUM> of an interface protection circuit according to the present invention. The interface protection circuit is disposed in a protected device. Referring to <FIG>, the circuit may include a capacitor <NUM> and a TVS transistor <NUM>. A first end of the capacitor <NUM> is connected to a connection port of the protected device. A second end of the capacitor <NUM> is connected to a first end of the TVS transistor <NUM> and an interface chip of the protected device. A second end of the TVS transistor <NUM> is grounded.

Optionally, the TVS transistor <NUM> in this application may be a unidirectional TVS transistor or a bidirectional TVS transistor. It should be noted that the TVS transistor <NUM> shown in <FIG> is a unidirectional TVS transistor. When the TVS transistor <NUM> is the unidirectional TVS transistor, a negative electrode of the TVS transistor <NUM> is connected to the connection port. Alternatively, when the TVS transistor <NUM> is the bidirectional TVS transistor, either electrode of the TVS transistor <NUM> may be connected to the connection port.

Optionally, a capacitance value of the capacitor <NUM> is related to a frequency of a data signal transmitted on the connection port. A higher frequency of the data signal may indicate a smaller capacitance value of the capacitor <NUM>. Optionally, the capacitance value of the capacitor <NUM> may be between <NUM> nanofarad and <NUM> microfarad. In this way, the capacitor may not only effectively filter out a direct current portion in surge, but also ensure relatively small impact on the data signal transmitted on the connection port. Optionally, there may be an inverse relationship between the capacitance value of the capacitor <NUM> and the frequency of the data signal transmitted on the connection port. Optionally, the data signal transmitted on the connection port may be sent by the connection port to the interface chip, or may be sent by the interface chip to the connection port.

In this application, a clamping voltage of the TVS transistor <NUM> is greater than a maximum voltage of the data signal transmitted on the connection port. When voltages at both ends of the TVS transistor <NUM> are greater than the clamping voltage, an impedance of the TVS transistor <NUM> instantly becomes lower, so that the TVS transistor <NUM> is conductive. When voltages at both ends of the TVS transistor <NUM> are less than the clamping voltage, an impedance of the TVS transistor <NUM> instantly becomes higher, and consequently the TVS transistor <NUM> is non-conductive.

The following describes in detail a working process of the interface protection circuit shown in the embodiment in <FIG>.

In an actual application process, relatively strong surge may be generated in the protected device in a plurality of scenarios, for example, in a scenario in which the protected device is connected to another device, or in a scenario in which a data signal starts to be transmitted between a protected circuit and another device. When relatively strong surge is generated in the protected device, the surge first passes through the capacitor <NUM>, and the capacitor <NUM> can filter out a direct current portion in the surge, to reduce energy of the surge. After the capacitor <NUM> filters out the direct current portion in the surge, the surge still has relatively strong energy. Consequently, voltages generated because of the surge at both ends of the TVS transistor are greater than the clamping voltage of the TVS transistor <NUM>. Therefore, the impedance of the TVS transistor <NUM> instantly becomes extremely low, so that the TVS transistor <NUM> is conductive. The TVS transistor <NUM> is connected in parallel to the interface chip, and the impedance of the TVS transistor <NUM> is extremely low. Therefore, the surge does not flow to the interface chip, but flows to the TVS transistor <NUM>. After the surge flows to the TVS transistor, the surge passes through the TVS transistor <NUM> and then is grounded, so that most of the energy of the surge is grounded. In this case, the TVS transistor <NUM> clamps the voltages at both ends of the TVS transistor <NUM> to a relatively low voltage. The interface chip is connected in parallel to the TVS transistor <NUM>. Therefore, voltages at both ends of the interface chip are equal to the voltages at both ends of the TVS transistor.

In a stable working process of the protected circuit, the surge in the protected device disappears. Because the data signal transmitted on the connection port has a relatively high frequency, for example, the frequency of the data signal is usually greater than <NUM>, most of energy of the data signal is an alternating component. When the alternating component passes through the capacitor <NUM>, the capacitor <NUM> does not filter the alternating component, so that a relatively entire data signal can pass through the capacitor <NUM>. The maximum voltage of the data signal is less than the clamping voltage of the TVS transistor <NUM>. Therefore, the impedance of the TVS transistor instantly becomes higher. Consequently, the TVS transistor is in a non-conductive state.

According to the interface protection circuit provided in this embodiment of the present invention, the capacitor and the TVS transistor are disposed in the interface protection circuit, and the capacitor is located between the connection port and the TVS transistor. In the foregoing process, a protection capability for the interface chip can be improved without increasing power of the interface protection circuit, so that the protection capability for the interface chip is improved while quality of a data signal transmitted between devices is ensured. Further, the capacitor can reduce the energy of the surge, so that the energy of the surge flowing to the TVS transistor is reduced, and the TVS transistor can be further protected, thereby improving reliability of the interface protection circuit.

Based on the embodiment shown in <FIG>, optionally, a resistor may be further disposed in the interface protection circuit, and the resistor is connected in series to the capacitor and the interface chip. In this way, voltage division may be performed on the resistor and the interface chip, to reduce impact of the surge on the interface chip, and further improve a protection effect of the interface protection circuit on the interface chip.

In an actual application process, when the resistor is disposed at a different location in the interface protection circuit, the protection effect of the interface protection circuit on the interface chip is different. The following describes in detail an interface protection circuit including a resistor with reference to embodiments shown in <FIG>.

<FIG> is schematic structural diagram <NUM> of an interface protection circuit according to the present invention. Based on the embodiment shown in <FIG>, refer to <FIG>. The interface protection circuit further includes a resistor <NUM>. The resistor <NUM> is disposed between the first end of the TVS transistor <NUM> and the interface chip.

In an actual application process, when a resistance value of the resistor <NUM> is excessively small, a protection effect of the resistor on the interface chip is not obvious. When the resistance value of the resistor <NUM> is excessively large, the resistor <NUM> causes relatively strong interference to the data signal transmitted on the connection port. Optionally, the resistance value of the resistor <NUM> is usually between a first resistance value and a second resistance value. The first resistance value is greater than the second resistance value. Optionally, the first resistance value is greater than <NUM> ohm, and the second resistance value is less than <NUM> ohms. Optionally, the resistance value of the resistor <NUM> may be <NUM> ohms.

When relatively strong surge is generated in a protected circuit, the capacitor <NUM> first filters out a direct current portion in the surge, to reduce energy of the surge. The surge passing through the capacitor <NUM> passes through the conductive TVS transistor <NUM> and then is grounded, so that the TVS transistor <NUM> clamps the voltages at both ends of the TVS transistor <NUM> to a low voltage. The interface chip is connected in series to the resistor <NUM>. Therefore, a sum of voltages at both ends of the interface chip and voltages at both ends of the resistor <NUM> is equal to the voltages at both ends of the TVS transistor <NUM>. Voltage division may be performed on the resistor <NUM> and the interface chip. Therefore, a surge voltage at both ends of the interface chip may be reduced, to further reduce impact of the surge on the interface chip.

In a process in which the connection port stably sends a data signal to the interface chip, for a process in which the capacitor <NUM> and the TVS transistor <NUM> process data information, refer to the embodiment shown in <FIG>. After the data signal passes through the capacitor <NUM>, because the TVS transistor is non-conductive, the data signal passing through the capacitor <NUM> flows to the interface chip after passing through the resistor <NUM>. The resistance value of the resistor is less than the second resistance value. Therefore, the resistor has relatively small impact on the data signal.

In the embodiment shown in <FIG>, the resistor <NUM> is disposed between the TVS transistor <NUM> and the interface chip. In this way, when relatively strong surge is generated because of the data signal sent by the connection port, voltage division may be performed on the resistor <NUM> and the interface chip, to reduce surge voltages at both ends of the interface chip, and further reduce impact of the surge on the interface chip. In a stable working process of the protected circuit, the resistance value of the resistor is less than the second resistance value. Therefore, the resistor has relatively small impact on the data signal.

<FIG> is schematic structural diagram <NUM> of an interface protection circuit according to the present invention. Based on the embodiment shown in <FIG>, refer to <FIG>. The interface protection circuit further includes a resistor <NUM>. The resistor <NUM> is disposed between the connection port and the first end of the capacitor <NUM>.

It should be noted that a characteristic of the resistor shown in the embodiment in <FIG> is similar to a characteristic of the resistor shown in the embodiment in <FIG>.

When relatively strong surge is generated in a protected device, the surge passes through the resistor <NUM>, the capacitor <NUM>, and the TVS transistor <NUM>, and then is grounded (for a specific reason, refer to the embodiment shown in <FIG>). Before the surge flows to the TVS transistor <NUM>, the surge first passes through the resistor <NUM>, to reduce energy of the surge flowing to the capacitor <NUM>. The capacitor <NUM> filters out a direct current portion in the surge, to further reduce the energy of the surge flowing to the TVS transistor <NUM>. In the foregoing process, a protection capability for the interface chip can be improved without increasing power of the TVS transistor, so that the protection capability for the interface chip is improved while quality of a data signal transmitted between devices is ensured. In this way, the TVS transistor can be better protected by using both the resistor <NUM> and the capacitor <NUM>, to further improve reliability of a protection circuit.

In a stable working process of a protected circuit, for a process in which the capacitor <NUM> and the TVS transistor <NUM> process data information, refer to the embodiment shown in <FIG>. Specifically, after passing through the resistor <NUM>, the data signal transmitted on the connection port flows to the interface chip. A resistance value of the resistor is less than a second resistance value. Therefore, the resistor has relatively small impact on the data signal.

In the embodiment shown in <FIG>, the resistor <NUM> is disposed between the connection port and the first end of the capacitor <NUM>. In this way, when relatively strong surge is generated in the protected device, the resistor <NUM> and the capacitor <NUM> may reduce energy of the surge flowing to the TVS transistor <NUM>, thereby improving a protection effect on the TVS transistor, and further improving reliability of the protection circuit. In a stable working process of the protected circuit, the resistance value of the resistor is less than the second resistance value. Therefore, the resistor has relatively small impact on the data signal.

<FIG> is schematic structural diagram <NUM> of an interface protection circuit according to the present invention. Based on the embodiment shown in <FIG>, refer to <FIG>. The interface protection circuit further includes a resistor <NUM>. The resistor <NUM> is disposed between the second end of the capacitor and the first end of the TVS transistor.

It should be further noted that, for a working process and an achieved beneficial effect of the interface protection circuit shown in the embodiment in <FIG>, refer to the embodiment shown in <FIG>.

Based on any one of the foregoing embodiments, optionally, to further improve a protection effect of the interface protection circuit on the interface chip, two TVS transistors may be disposed in the interface protection circuit. The interface protection circuit shown in the embodiment in <FIG> is used as an example. Another TVS transistor may be disposed between the resistor <NUM> and the interface chip. For details, refer to an embodiment shown in <FIG>.

<FIG> is schematic structural diagram <NUM> of an interface protection circuit according to the present invention. Based on the embodiment shown in <FIG>, referring to <FIG>, the interface protection circuit further includes a TVS transistor <NUM>. One end of the TVS transistor <NUM> is disposed between the resistor <NUM> and the interface chip, and the other end of the TVS transistor <NUM> is grounded.

Optionally, a characteristic of the TVS transistor <NUM> may be the same as a characteristic of the TVS transistor <NUM>.

The TVS transistor <NUM> may further reduce surge voltages at both ends of the interface chip, so that an effect of protection for the interface chip can be improved. Further, when one TVS transistor is faulty, the interface chip may be protected by using the other TVS transistor, thereby improving reliability of the protection for the interface chip.

Certainly, in an actual application process, a location of the TVS transistor in the interface protection circuit and a quantity of TVS transistors in the interface protection circuit may be further set based on an actual requirement. This is not specifically limited in this embodiment of the present invention.

<FIG> is a schematic structural diagram of a device interface according to the present invention. Referring to <FIG>, the device interface includes an interface chip <NUM> and an interface protection circuit <NUM> according to any one of the embodiments in <FIG>.

Claim 1:
An interface protection circuit, comprising a capacitor (<NUM>) and a transient voltage suppressor, TVS, transistor (<NUM>), wherein
a first end of the capacitor (<NUM>) is connected to a connection port of a protected device (<NUM>, <NUM>), and a second end of the capacitor (<NUM>) is connected to a first end of the TVS transistor (<NUM>) and an interface chip of the protected device; and
a second end of the TVS transistor (<NUM>) is grounded,
and characterised in that
the TVS transistor is connected in parallel with the interface chip, and
wherein a clamping voltage of the TVS transistor (<NUM>) is greater than a maximum voltage of a data signal transmitted on the connection port.