Patent Description:
In legacy analog imagers, particularly infrared imagers, photocurrent from a detector diode is integrated by a well capacitor coupled to the detector diode, and then once per video frame, the voltage or charge of each well capacitor is transferred to a downstream analog-to-digital converter (ADC), where the voltage is converted to a binary value. Pixel sizes continue to shrink and the ratio of well capacitor to pixel area shrinks disproportionately more. Simultaneously, there is a demand by consumers for increased Signal-to-Noise Ratio (SNR) which can be realized by increasing effective well capacitance.

In-pixel ADC imagers are used to address this problem associated with decreasing pixel size. In particular, in-pixel ADC imaging improves photo-charge capacity for infrared imaging and other applications as the size of pixels continues to decrease. A good in-pixel ADC design can store nearly all of the available photo-charge from a detector diode and thus improve SNR to near theoretical limits. A common method of integration for in-pixel ADC circuits uses a quantizing analog front end circuit which accumulates charge over a relatively small capacitor, trips a threshold and is then reset. This pattern is repeated as more photo-current integrates.

An example of an in-pixel ADC circuit <NUM> is illustrated in <FIG>. Charge from a photodiode <NUM> is accumulated over an integration capacitor <NUM>. As charge is accumulated across the integration capacitor <NUM> it is compared to a threshold voltage (Vref) by a comparator <NUM>. When the voltage across the integration capacitor <NUM> (referred to as Vint herein) exceeds Vref the circuit <NUM> is reset via a reset switch <NUM> that receives a control signal Reset from the comparator <NUM>. During a reset, a voltage equal to the difference between Vref and Vreset is subtracted from the integration capacitor <NUM>. Vreset can be referred to as a base voltage herein.

Control of the flow of current from the photodiode <NUM> is controlled by an injection transistor <NUM>. The gate of the injection transistor <NUM> is coupled to a bias voltage Vbias. The level of this voltage can be selected by the skilled artisan and is used, in part, to keep the photodiode <NUM> in reverse bias where the voltage at node <NUM> is lower than the diode supply voltage Vdiode. If the voltage at node <NUM> exceeds Vbias, current created in the photodiode <NUM> is allowed to pass through the injection transistor <NUM> for accumulation by the integration capacitor <NUM>.

Each reset event is accumulated (counted) with a counter circuit <NUM>. In some instances the counter circuit <NUM> is a digital circuit.

After the integration time expires, the "count" accumulated on the counter circuit <NUM> can be read out. Also, any residual charge accumulated on the integration capacitor <NUM> can be read out by, for example, a single slope ADC or any other type of ADC. Such operations are known in the prior art.

The example in-pixel ADC circuit <NUM> illustrated in <FIG> is an asynchronous circuit. In asynchronous in-pixel ADCs, the comparator reset event occurs as soon as the voltage on the integration capacitor <NUM> crosses the comparator threshold.

For further background,<NPL> describes an active-quenching circuit and a linear counting circuit used for a silicon single photon avalanche diode (SPAD). The proposed quenching circuit is fast and compact. The linear counting circuit can achieve <NUM> bit large count range with a small capacitor, which can effectively reduce the area of pixel.

<NPL> describes a compact analog readout circuit for photon counting. It describes a test chip, including a <NUM> × <NUM> counter array, that has been manufactured in a standard <NUM>-µm CMOS technology. The circuit delivers an output voltage proportional to the input pulse count, with a programmable voltage step. The counting resolution can be set to <NUM> or <NUM> bits with a readout noise of <NUM> and <NUM> electrons, respectively, and an output nonuniformity of <NUM>% across the array. Due to the compactness and the lower counter power consumption with regard to the former designs, the proposed circuit can be exploited for signal processing in high-spatial resolution single-photon-avalanche-diode-based image sensors.

<CIT> describes an image sensor containing an array of pixels, where a pixel signal corresponding to the state of a photosensitive element is read-out of each pixel and compared with a threshold. If the pixel signal exceeds the first threshold, the state of the photosensitive element is reset and an analog-count voltage that corresponds to the pixel is incremented.

The invention is defined by the appended independent claim <NUM> and preferred embodiments are defined by the appended dependent claims.

In a circuit according to an embodiment, the accumulating capacitor can be connected between the output and a reset voltage.

In a circuit according to an embodiment, the circuit further includes a frame reset switch connected in parallel with the accumulating capacitor.

In a circuit according the invention, the injection switch has gate that is connected to a counter bias voltage Vcb.

In a circuit according to an embodiment, the control switch is a P-channel MOSFET that has a gate, a drain and a source.

In a circuit according to the prior embodiment, the gate of the P-channel MOSFET is connected to the first inverter output.

In a circuit according to the prior embodiment, the drain of the P-channel MOSFET is connected to source voltage and the source of the P-channel MOSFET is connected to the floating node.

In a circuit according to the prior embodiment, the injection switch is a P-channel MOSFET.

Also disclosed is a digital pixel. The digital pixel includes: a photocurrent source; an injection transistor connected to the photocurrent source; an integration capacitor connected between the injection transistor and a reset voltage; and a comparator having inputs connected to the injection transistor and to a reference voltage. The comparator has an output on which it provides an output RESET signal that has either a high or low value based on a relationship between the reference voltage and a voltage on the integration capacitor. The digital pixel can include a an analog counter according to the invention that is connected to the output of the comparator.

In any prior digital pixel, the pixel can include a reset switch connected in parallel with the integrating capacitor, the reset switch being controlled by the time delayed signal (RP).

In any prior digital pixel, a gate of the reset switch is connected to the second inverter output.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.

The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the terms "coupled", "connected" and variations thereof, describe having a conductive path between two elements. The use of such terms herein provides written description for both direct and indirect couplings/connections. In the claims, such terms shall include both direct and indirect connections/couplings unless the claim specifically states that connection is direct. A direct connection/coupling is a connection/coupling between the elements with no intervening elements/connections between them.

Disclosed herein is an analog counter that can used, for example, as the counter <NUM> in <FIG>. The analog counter transfers a fixed amount of charge to an accumulating capacitor each time the output of the comparator <NUM> goes high. In particular, analog "counting" is achieved by pulsing a current source to inject charge onto an accumulating capacitor. Any residual charge not transferred is removed into a capacitor so that it will not cause counter non-uniformity.

Herein, the output signal from the comparator shall be referred to as "RESET". In one embodiment, the amount of charge stored on the accumulating transistor is incremented by the fixed amount (analog or "count" voltage step) by enabling a control/enable switch allowing current to flow through an injection transistor for as long as the switch is enabled.

In some instances, as will be understood from the following discussion, the analog counter disclosed herein can have increased performance/accuracy for the analog voltage step by removing charge from a floating node between the control/enable switch and the biased transistor. In some instances, the analog circuit disclosed herein may provide a simple manner to eliminating leakage onto the accumulating capacitor.

In general, the analog counter disclosed herein utilizes a delayed version the reset pulse (RESET) and its complement RESET* to control current flow into the accumulating transistor. In particular, both a recycle pulse (RP) and its complement (RP*) are created from RESET with RP being delayed relative to RP*. RP* is used to control the control/enable switch. RP is provided to the floating node connected to the biased transistor. The connection is through a capacitor in one embodiment that can be referred to as a feedback capacitor herein. The feedback capacitor can be used to remove excess charge from the floating node so each "count" accumulates the same amount of charge/voltage on the accumulating capacitor. As will be understood based on the teachings herein, by controlling the system with RP being time delayed relative to its complement enables the use of the feedback capacitor to remove excess charge and require less devices. In some embodiment, due the time delay, the falling edge of the recycle pulse (RP) occurs after the RP* rises. This means that the falling edge of RP occurs after the control switch is turned off and the feedback capacitor is large enough to remove all of the floating charge ensuring the current source is turned off.

<FIG> shows waveform diagrams illustrating the various voltage or signal values during operation of the circuit in <FIG>. As can be seen during, each time Vint meets or exceeds Vref, an output pulse is generated on RESET. The output pulse is generated at the output of the comparator <NUM>. This pulse can be called a comparator reset or recycle pulse herein. That pulse has a height h and width w. Depending on the type of comparator <NUM> used, h and w can be variable. Herein disclosed is an analog counter that may operate independent of the pulse height h. The height of the pulse can also be referred to as Vpd herein and represents the change in potential provided at the input to the analog counters discussed herein when the comparator <NUM> generates RESET pulses.

<FIG> shows an example of a digital pixel <NUM> that includes an analog counter <NUM> according to one embodiment. Operation of the circuit outside of the analog counter <NUM> is as above and will not be discussed further. It shall be understood that other types of in-pixel devices can be used with the analog counter <NUM> disclosed herein as long as it generates a RESET pulse. The same is true for all later disclosed embodiments.

The counter <NUM> includes an input <NUM> and an output <NUM>. In operation, the input <NUM> receives RESET pulses from the comparator <NUM>. Each time RESET is received, a fixed amount of charge is caused to be stored in an accumulating capacitor <NUM>. At the end of a frame or other time period, the amount of charge stored on the accumulating capacitor <NUM> can be read out via the output <NUM>. The amount of charge that is read out is, thus, proportional to the number of RESET pulses received during the frame.

The counter <NUM> includes a control/enable switch <NUM> and an injection switch <NUM> that are connected such that they are between a current source (Vsource) and the accumulating capacitor <NUM> and control current flow from Vsource to the accumulating capacitor <NUM>. As illustrated in <FIG>, both the control switch <NUM> and the injection switch <NUM> is implemented as a P-type switche but the skilled artisan will realize that other types of switches can be utilized as long at the correct gate input voltages are provided. The switches can be FET, MOSFETs or the like and can be either N-type or P-type.

In the example of <FIG>, first and second inverters <NUM>, <NUM> are provided. The first and second inverters <NUM>, <NUM> are serially connected to one another. The first inverter <NUM> has an input connected to the input <NUM> and an output connected to the input of the second inverter <NUM>. A node <NUM> is shown between the output of the first inverter <NUM> and the input of the second inverter <NUM>. The signal at node <NUM> is a slightly time delayed and inverted version of RESET and is denoted at RP* in <FIG>. The signal at the output of the second inverter <NUM> is a delayed and inverted version of RP* and is denoted as RP. The skilled artisan will realize that RP will be a slightly time delayed version of RESET but may have a different amplitude therefrom depending on the nature of the comparator <NUM> and the first and second inverters <NUM>, <NUM>. In contrast to <FIG>, the control signal provided to reset switch <NUM> is RP rather than RESET. This ensures that the comparator <NUM> does not change state prematurely (e.g., before RP falls as will be described below). The amplitude of RP and RP* is typically larger or equal to Vsource.

In the example in <FIG>, the drain of the control switch <NUM> is connected to Vsource and the source of the control switch <NUM> is connected to the injection switch <NUM>. A floating node <NUM> is defined between the drain of the control switch <NUM> and the source of the injection switch <NUM>. A feedback capacitor <NUM> is connected between the output of second inverter <NUM> and the floating node <NUM>. The gate of the control switch <NUM> is connected to RP*. When RESET goes high, RP* goes low. In such a case, current can pass from the source to the drain because to voltage between the gate and source (Vgs) is negative. When RP* is low, the transistor <NUM> will drive the node <NUM> to Vsource. As long as Vsource is slightly larger than a counter bias voltage Vcb applied to the gate of the injection switch <NUM>, the injection switch <NUM> will conduct and the charge can be accumulated on the accumulating capacitor <NUM>.

In more detail, the source of injection switch <NUM> is connected to the floating node <NUM>, the gate of the injection switch <NUM> is connected to Vcb and the drain is connected to the accumulating capacitor <NUM>. The accumulating capacitor <NUM> is coupled between the output <NUM> and Vreset. A frame reset switch <NUM> is connected in parallel with the accumulating capacitor <NUM> and works in a manner similar to the reset switch <NUM> to lower the charge thereon down to the reset level Vreset.

When RESET goes low again, RP* will go high and the control switch <NUM> will stop passing charge. Shortly thereafter, RP will go low and charge will stop accumulating on the accumulating capacitor <NUM>. Thus, the width of RP*/RP will control the amount of charge accumulated on the accumulating capacitor <NUM>. That is, the width RP*/RP will control the analog voltage step due to RESET going high. This is due to the capacitance on the floating node <NUM> which is created by the combined total of drain capacitance of the control switch <NUM>, the source capacitance of the injection swtich <NUM> and any other parasitic capacitances incurred during fabrication. After RP goes low, some residual charge may remain at the floating node <NUM>. This residual charge will leak with an exponential decay as a function of time between recycles so that it does not adversely affect the voltage step by non-uniformly influencing the analog counter voltage as described earlier. As connected in <FIG>, the counter <NUM> can discharge this voltage into the switch <NUM>.

It shall be understood that the above described analog counters can be implemented as the counter <NUM> in <FIG>. As such, in one embodiment, the teachings herein can be utilized to form a digital pixel. Such a pixel can include a photocurrent source <NUM>, an injection transistor <NUM> connected to the photocurrent source and an integration capacitor <NUM> that is connected to a reset (Vreset) voltage. The comparator <NUM> has inputs operatively connected to the injection transistor <NUM> and to a reference voltage (Vref). The comparator <NUM> has an output on which, as discussed above, an output RESET signal is provided that has either a high or low value based on a relationship between the reference voltage and a voltage on the integration capacitor <NUM>. In one instance, RESET is high when reference voltage is exceeded by the voltage on the integration capacitor <NUM>. The output of the comparator <NUM> is connected the input of any of the analog counters discussed herein.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claim 1:
An analog counter circuit (<NUM>) for use with a digital pixel (<NUM>), the analog counter circuit (<NUM>) comprising:
an input (<NUM>) for receiving reset pulses (RESET) from the digital pixel (<NUM>);
an output (<NUM>);
a first inverter (<NUM>) connected to the input (<NUM>) that produces on a first inverter output (<NUM>) a time delayed inverted signal (RP*) from an input signal received at the input (<NUM>);
a second inverter (<NUM>) connected to the first inverter output (<NUM>) that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to the time delayed inverted signal (RP*);
a control switch (<NUM>) connected between a source voltage and a floating node (<NUM>), wherein the control switch (<NUM>) is controlled by the time delayed inverted signal on the first inverter output (<NUM>) such that when the time delayed inverted signal (RP*) goes low, the control switch (<NUM>) will drive the floating node (<NUM>) to the source voltage (Vsource);
a feedback capacitor (<NUM>) connected between the second inverter output and the floating node (<NUM>);
an accumulating capacitor (<NUM>) that accumulates at least some of a charge that passes through the control switch (<NUM>); and
an injection transistor (<NUM>) with a gate connected to a bias voltage (Vcb), a source connected to the floating node (<NUM>) and a drain connected to the output (<NUM>) and the accumulating capacitor (<NUM>) such that the injection transistor (<NUM>) will conduct when the floating node (<NUM>) is driven to the source voltage (Vsource) and a charge can be accumulated on the accumulating capacitor (<NUM>); wherein the amount of charge stored on the accumulating capacitor (<NUM>) is proportional to the number of RESET pulses received at the input (<NUM>).