Patent Description:
Cloud security providers (CSPs) use cryptographic isolation for the customer workloads running on their platform. Various cryptographic isolation methods have been implemented to meet these requirements for the cloud providers, such as Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV). Memory integrity operates by associating a cryptographic message authentication code (MAC) with each data line in memory. The MAC is generated when data is written to memory and verified when the data is read from memory. If data was modified, either when resident in memory, the MAC will not match and result in the modification attack being detected (a security exception can then be signaled to notify software of the attack). Traditional integrity approaches can suffer from significant performance overheads as the MAC associated with each data line must be loaded on each access and verified/updated depending on the type of memory access. This additional access results in storage, performance, and bandwidth overheads.

<CIT> discloses a system, which may use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED may be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC, in response to identifying the error.

<CIT> relates to memory organisation for security and reliability. This document discloses a method and apparatus for retrieving data from a memory in which data, an associated message authentication code (MAC) and an associated error correction code (ECC) are stored in a memory such that the data, MAC and ECC can be retrieved together in a single read transaction and written in a single write transaction. Additional read transactions may be used to retrieve counters values that enable the retrieved MAC to be compared with a computed MAC. Still further, node value values of an integrity tree may also be retrieved to enable hash values of the integrity tree to be verified. The MAC and ECC may be stored in a metadata region of a memory module, for example.

Advantageous embodiments are described by the dependent claims.

Features and advantages of various embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals designate like parts, and in which:.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.

The systems and methods disclosed herein provide a memory integrity architecture that features full error correction capabilities and high-strength memory integrity without introducing the performance overheads of traditional memory integrity approaches. The systems and methods disclosed herein use extended Reed-Solomon codes to provide error correction code (ECC) that includes error detection data and error correction data. The use of Reed-Solomon codes advantageously permits splitting the ECC into two tiers (hereinafter, "Tier I" and "Tier II"). Tier I data, including at least the error detection data and message authentication code (MAC) data, is stored in memory circuitry at the same location as the associated data line, such that at least the error detection data and MAC data are read during each read operation on the data line. The Tier I data may, at times, also include other data such as security-related metadata, and some or all of the error correction data. Tier II data includes error correction data and is stored in a separate or sequestered location in the memory circuitry. The Tier II error correction data is accessed when the memory controller circuitry detects an error in the data line. Thus, Tier I stores performance sensitive metadata (e.g., the error detection and correction tier of ECC, MAC) and Tier II uses sequestered memory to store the metadata associated with a data line that is off the performance critical path (e.g., the error correction tier of ECC). System performance is enhanced by obviating the need to read the MAC data and both the error detection data and error correction data during each read operation - instead, the MAC data and the error detection data are read during each read operation and only when a data error occurs is the full error correction data read.

A data storage system is provided. The system may include: memory circuitry; controller circuitry to, for each of a plurality of lines of data stored in memory circuitry: generate metadata that includes: data representative of a cryptographic message authentication code associated with the respective line of data; and data representative of an error code associated with the respective line of data, the error correction code including at least error detection data associated with the respective line of data and error correction data associated with the respective line of data; and apportion the metadata into a Tier I portion stored in a first location in the memory circuitry proximate the respective line of data in the memory circuitry and a Tier II portion stored in a second location in the memory circuitry remote from the respective line of data; wherein the Tier I portion includes at least the error detection data portion and the message authentication code portion associated with the respective line of data; and wherein the Tier II portion includes at least a portion of the error correction data portion associated with the respective line of data.

A data storage method is provided. The method may include: generating, by controller circuitry, metadata for each respective one of a plurality of lines of data stored in memory circuitry the metadata including: data representative of a cryptographic message authentication code (MAC) associated with the respective line of data; and data representative of an error correction code (ECC) associated with the respective line of data, the error correction code including at least error detection data associated with the respective line of data and error correction data associated with the respective line of data; and apportioning, by the controller circuitry, the metadata into a Tier I portion stored in a first memory location in the memory circuitry proximate the respective line of data and a Tier II portion stored in a second location in the memory circuitry remote from the respective line of data; wherein the Tier I portion includes at least the error detection data portion and the message authentication code portion of the metadata associated with the respective line of data; and wherein the Tier II portion includes at least a portion of the error correction data portion of the metadata associated with the respective line of data.

A non-transitory storage device that includes instructions is provided. The instructions, when executed by controller circuitry, cause the controller circuitry to: generate metadata for each respective one of a plurality of lines of data stored in memory circuitry the metadata including: data representative of a cryptographic message authentication code (MAC) associated with the respective line of data; and data representative of an error correction code (ECC) associated with the respective line of data, the error correction code including at least error detection data associated with the respective line of data and error correction data associated with the respective line of data; and apportion the metadata into a Tier I portion stored in a first memory location in the memory circuitry proximate the respective line of data and a Tier II portion stored in a second location in the memory circuitry remote from the respective line of data; wherein the Tier I portion includes at least the error detection data portion and the message authentication code portion of the metadata associated with the respective line of data; and wherein the Tier II portion includes at least a portion of the error correction data portion of the metadata associated with the respective line of data.

A data storage system is provided. The system may include: means for generating metadata for each respective one of a plurality of lines of data stored in memory circuitry the metadata including: data representative of a cryptographic message authentication code (MAC) associated with the respective line of data; and data representative of an error correction code (ECC) associated with the respective line of data, the error correction code including at least error detection data associated with the respective line of data and error correction data associated with the respective line of data; and means for apportioning the metadata into a Tier I portion stored in a first memory location in the memory circuitry proximate the respective line of data and a Tier II portion stored in a second location in the memory circuitry remote from the respective line of data; wherein the Tier I portion includes at least the error detection data portion and the message authentication code portion of the metadata associated with the respective line of data; and wherein the Tier II portion includes at least a portion of the error correction data portion of the metadata associated with the respective line of data.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed embodiments. However, one skilled in the relevant art will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with data storage and retrieval have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the embodiments. Although the following disclosure is directed to specific embodiments utilizing electromagnetic memory such as random access memory (RAM); dual data rate RAM (DDR-RAM); static RAM (SRAM); and dynamic RAM (DRAM), those of ordinary skill in the computer arts will readily appreciate the applicability of the systems and methods disclosed herein to other data storage structures such as: magneto-resistive RAM (MRAM); spin transfer torque MRAM (STT-MRAM); resistive RAM (ReRAM); quantum storage devices; molecular storage devices; and similar.

Unless the context requires otherwise, throughout the specification and claims which follow, the word "comprise" and variations thereof, such as, "comprises" and "comprising" are to be construed in an open, inclusive sense that is as "including, but not limited to.

The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.

The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

<FIG> is a block diagram of an illustrative system <NUM> that includes controller circuitry <NUM> and memory circuitry <NUM> that includes: Tier I memory circuitry <NUM> to store data lines 132A-132n and associated Tier I metadata 134A-134n; and Tier II memory circuitry <NUM> to store Tier II metadata 142A-142n associated with respective ones of the data lines 132A-132n, in accordance with at least one embodiment described herein. As depicted in <FIG>, the system <NUM> also includes processor circuitry <NUM> to execute one or more applications that perform memory operations such as memory read and memory write operations.

As depicted in <FIG>, the Tier I metadata 134A-134n includes message authentication code (MAC) data 136A-136n, each associated with a respective one of the data lines 132A-132n. The Tier I metadata 134A-134n also includes at least a first portion of the error correction code (ECC) 138A<NUM>-138n<NUM>, each associated with a respective one of the data lines 132A-132n. In some embodiments, the first portion of the ECC 138A<NUM>-138n<NUM> includes the error detection data portion of the respective ECC 138A-138n. In other embodiments, the first portion of the ECC 138A<NUM>-138n<NUM> includes the error detection data portion of the respective ECC 138A-138n and at least a portion of the error correction data portion of the respective ECC 138A-138n. Also as depicted in <FIG>, the Tier II metadata 142A-142n includes a second portion of the error correction code (ECC) 138A<NUM>-138n<NUM>, each associated with a corresponding one of the data lines 132A-132n.

In embodiments, in response to execution of an instruction by the processor circuitry <NUM> that includes a memory write operation, the controller circuitry <NUM> may encrypt the data line 132A and generate message authentication code (MAC) data 136A that is associated with the data line 132A. The controller circuitry <NUM> may also generate an error correction code (ECC) 138A, such as a Reed-Solomon ECC, that includes error detection data and error correction data, both associated with data line 132A. The controller circuitry <NUM> stores the data line 132A and the Tier I metadata 134A, including at least the MAC data 136A and the first portion of the ECC data 138A<NUM> in the Tier I memory circuitry <NUM>. The controller circuitry <NUM> stores the Tier II metadata 142A, including the second portion of the ECC data 138A<NUM> in a sequestered Tier II memory circuitry <NUM> that is remote from the Tier I memory circuitry <NUM>.

In embodiments, in response to execution of an instruction by the processor circuitry <NUM> that includes a memory read operation, the controller circuitry <NUM> may retrieve the data line 132A and the Tier I metadata 134A, including the MAC data 136A and the first portion of the ECC data 138A<NUM>, associated with the data line 132A. The controller circuitry <NUM> uses the error detection data included in the first portion of the ECC data 138A<NUM> to detect if errors exist in the retrieved data 132A. If no errors are detected, the controller circuitry <NUM> decrypts and verifies the retrieved data 132A using the MAC data 136A included in the Tier I metadata 134A. Once verified by the controller circuitry <NUM>, the verified data line 132A is then passed to the processor circuitry <NUM>. If the retrieved data 132A cannot be verified by the controller circuitry <NUM> using the MAC data 136A, the controller circuitry <NUM> returns null data and the processor circuitry <NUM> throws an exception. If the controller circuitry <NUM> detects an error in the retrieved data line 132A, the controller circuitry <NUM> retrieves, from the Tier II memory circuitry <NUM>, the Tier II metadata 142A. The controller circuitry <NUM> uses the error correction data included in the second portion of the ECC data 138A2 to correct the data line 132A prior to decrypting and verifying the retrieved data 132A using the MAC data 136A included in the Tier I metadata 134A.

In embodiments, each of the data lines 132A-132n may include one or more lines in cache memory circuitry operably coupled to the processor circuitry <NUM>. For example, each of the data lines 132A-132n may include one or more level <NUM> (L1) cache lines; one or more level <NUM> (L2) cache lines; one or more last level cache (LLC) lines; or combinations thereof. Each of the data lines 132A-132n may include any number of bytes. In embodiments, each of the data lines 132A-132n may have the same or different number of bytes. For example, each of data lines 132A-132n may include: <NUM> bytes; <NUM> bytes; <NUM> bytes; or <NUM> bytes.

The Tier I metadata 134A-134n includes the MAC data 136A-136n and the first portion of the ECC data 138A<NUM>-138n<NUM>. In addition, in some embodiments, the Tier I metadata 134A-134n may include other data such as security data that includes but is not limited to: tag and state data, directory/poison data, and similar security related data. In some embodiments, the Tier I metadata 134A-134n may include only the first portion of the ECC data 138A<NUM>-138n<NUM>. In other embodiments, the Tier I metadata 134A-134n may include the first portion of the ECC data 138A<NUM>-138n<NUM> and at least some of the bits included in the second portion of the ECC data 138A<NUM>-138n<NUM>. In yet other embodiments, the Tier I metadata 134A-134n may include the first portion of the ECC data 138A<NUM>-138n<NUM> and the second portion of the ECC data 138A<NUM>-138n<NUM>. The Tier I metadata 134A-134n may include any number of bits. For example, the Tier I metadata 134A-134n may include: <NUM> bits; <NUM> bits; <NUM> bits; or <NUM> bits. The MAC data 136A-136n included in the Tier I metadata 134A-134n may include any number of bits. For example, the MAC data 136A-136n may include: <NUM> bits or less; <NUM> bits or less; <NUM> bits or less; or <NUM> bits or less. The first portion of the ECC data 138A<NUM>-138n<NUM> includes error detection data. In some embodiments, the first portion of the ECC data 138A<NUM>-138n<NUM> includes error detection data and at least a portion of the error correction data. The first portion of the ECC data 138A<NUM>-138n<NUM> may include any number of bits. For example, the first portion of the ECC data 138A<NUM>-138n<NUM> may include: <NUM> bits, <NUM> bits, <NUM> bits, or <NUM> bits.

In other embodiments, the Tier I metadata 134A-134n may include the first portion of the ECC data 138A<NUM>-138n<NUM> and at least some of the bits included in the second portion of the ECC data 138A<NUM>-138n<NUM>. In such embodiments, the Tier I metadata 134A-134n may include any number of bits from the second portion of the ECC data 138A<NUM>-138n<NUM>. For example, the Tier I metadata 134A-134n may include: <NUM> bits, <NUM> bits, or <NUM> bits of the second portion of the ECC data 138A<NUM>-138n<NUM>.

In yet other embodiments, the Tier I metadata 134A-134n may include the first portion of the ECC data 138A<NUM>-138n<NUM> and the second portion of the ECC data 138A<NUM>-138n<NUM>. In such embodiments, the Tier I metadata 134A-134n may include a total of: <NUM> bits, <NUM> bits, or <NUM> bits of ECC data included in the first portion of the ECC data 138A<NUM>-138n<NUM> and the second portion of the ECC data 138A<NUM>-138n<NUM>.

The Tier II metadata 142A-142n includes all or a portion of the second portion of the ECC data 138A<NUM>-138n<NUM>. In embodiments, the second portion of the ECC data 138A<NUM>-138n<NUM> may include error correction data that includes any number of bits. For example, the Tier II metadata 142A-142n may include: <NUM> bits, <NUM> bits, <NUM> bits, <NUM> bits, <NUM> bits, or <NUM> bits of error correction data included in the second portion of the ECC data 138A<NUM>-138n<NUM>.

The controller circuitry <NUM> includes any number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor device, and/or logic elements capable of performing memory access, error detection, error correction, and verification operations on data communicated to or from the memory circuitry <NUM>. In at least some embodiments, the controller circuitry <NUM> may include memory controller circuitry. In at least some embodiments, the processor circuitry <NUM> may provide all or a portion of the controller circuitry <NUM>.

The memory circuitry <NUM> includes any number and/or combination of currently available and/or future developed electronic components, optical components, semiconductor device, and/or logic elements capable of storing information and/or data. The memory circuitry <NUM> may include volatile memory, non-volatile memory, or any combination thereof. The memory circuitry <NUM> may be communicatively coupled to processor circuitry <NUM> that includes one or more processor core circuits, each processor core circuit capable of contemporaneous execution of one or more threads. In embodiments, the memory circuitry <NUM> may include cache memory circuitry communicatively coupled to the processor circuitry. In embodiments, the memory circuitry <NUM> may include level <NUM> (L1) cache memory circuitry, level <NUM> (L2) cache memory circuitry, last level cache (LLC) circuitry, or any combination thereof. In other embodiments, all or a portion of the cache memory circuitry <NUM> may include cache circuitry shared between a plurality of processor core circuits included in the processor circuitry <NUM>.

The processor circuitry <NUM> may include a general-purpose processor, such as a Core® i3, i5, i7, <NUM> Duo and Quad, Xeon®, Itanium®, Atom®, or Quark® microprocessor, available from Intel® (Intel Corporation, SANTA CLARA, CA), Alternatively, the processor circuitry <NUM> may include one or more processors from another manufacturer or supplier, such as Advanced Micro Devices (AMD®, Inc. ), ARM Holdings® Ltd, MLPS®, etc. The processor circuitry <NUM> may include a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The processor circuitry <NUM> may be implemented as a single semiconductor package or as a combination of stacked or otherwise interconnected semiconductor packages and/or dies. The processor circuitry <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

<FIG> is an illustrative metadata configuration 200A using a 10x4 DDR5 memory module, in accordance with at least one embodiment described herein. <FIG> is another illustrative metadata configuration 200B using a 9x4 DDR5 memory module, in accordance with at least one embodiment described herein. <FIG> is yet another illustrative metadata configuration 200C using a 5x8 DDR5 memory module, in accordance with at least one embodiment described herein. Those of skill in the relevant arts will readily appreciate that <FIG>, and <FIG> represent illustrative embodiments, and the general principles behind the systems and methods disclosed herein may be readily applied to other memory module configurations with similar impact on system performance as described herein.

As depicted in <FIG>, the 10x4 DDR5 memory module 200A includes <NUM> storage devices, with <NUM> storage devices 202A-<NUM> dedicated to the storage of data and <NUM> storage devices 204A and 204B dedicated to the storage of ECC data <NUM>. Each data storage device <NUM> and each ECC storage device <NUM> provides <NUM> bytes of data in each cycle with a <NUM> byte cache line requiring a total of <NUM> cycles to be read out of the 10x4 DDR5 memory module 200A.

Turning next to <FIG>, the 9x4 DDR5 memory module 200B includes <NUM> storage devices, with <NUM> storage devices 202A-<NUM> dedicated to the storage of data and <NUM> storage device 204A dedicated to the storage of ECC data <NUM>. Each data storage device <NUM> and each ECC storage device <NUM> provides <NUM> bytes of data in each cycle with a <NUM> byte cache line again requiring a total of <NUM> cycles to be read out of the 9x4 DDR5 memory module 200B.

Turning next to <FIG>, the 5x8 DDR5 memory module 200C includes <NUM> storage devices, with <NUM> storage devices 206A-206D dedicated to the storage of data and <NUM> storage device 208A dedicated to the storage of ECC data <NUM>. Each data storage device <NUM> and each ECC storage device <NUM> provides <NUM> bytes of data in each cycle with a <NUM> byte cache line requiring a total of <NUM> cycles to be read out of the 5x8 DDR5 memory module 200C.

<FIG> is a table <NUM> providing a comparison of various metadata configurations <NUM>, <NUM>, <NUM>, and <NUM>, in accordance with at least one embodiment described herein. As depicted in <FIG>, a base metadata configuration <NUM> in which all of the metadata, including a <NUM> bits of error detection + correction data, <NUM> bits of error correction data, <NUM> bits of MAC data and <NUM> bits of security (or other) data fit within the <NUM> bits allowable in the Tier I memory circuitry <NUM>. In configuration <NUM>, the MAC data is limited to <NUM> bits and the security data is limited to <NUM> bits to fit within the <NUM> bit constraint of the Tier I memory circuitry <NUM>.

Configuration <NUM> provides a first metadata configuration in which the ECC data <NUM> is split into a first portion of ECC data <NUM><NUM> stored or otherwise retained in the Tier I memory circuitry <NUM> and a second portion of ECC data <NUM><NUM> stored or otherwise retained in the Tier II memory circuitry <NUM>. As depicted in configuration <NUM>, the Tier I memory circuitry <NUM> stores or otherwise retains the first portion of the ECC data <NUM><NUM> (<NUM> bits of error detection + partial error correction data), and a portion of the second portion of the ECC data <NUM><NUM> (<NUM> bits of partial error correction data). The sequestered Tier II memory circuitry <NUM> stores or otherwise retains the remaining portion of the second portion of the ECC data <NUM><NUM> (<NUM> bits of remaining error correction data). The Tier I memory circuitry <NUM> is read on every memory read operation, thereby permitting error detection capabilities. The controller circuitry <NUM> accesses the second portion of the ECC data <NUM><NUM> (<NUM> bits of remaining error correction data) in sequestered Tier II memory circuitry <NUM> only upon detecting an error. Tier I memory circuitry allocated to the storage of MAC data <NUM> has increased to <NUM> bits, providing an additional <NUM> bits of MAC data storage. Metadata configuration <NUM> beneficially provides increased capability for storage of other data - as depicted in configuration <NUM>, up to <NUM> bits of other data. An example of such data includes but is not limited to tag bits used to support multi-level memory circuitry (e.g., three-dimensional cross point memory circuitry "3DXP" memory circuitry as provided by Intel® Corp. , SANTA CLARA, CA).

Configuration <NUM> provides a second metadata configuration in which Tier I memory circuitry <NUM> contains the first portion of ECC data <NUM><NUM> (error detection + partial correction data) and Tier II memory circuitry <NUM> contains the second portion of ECC data <NUM><NUM> (remaining error correction data). As depicted in configuration <NUM>, the Tier I memory circuitry <NUM> stores the first portion of the ECC data <NUM><NUM> (<NUM> bits of error detection + partial correction data), <NUM> bits of MAC data, and <NUM> bits of other data (multi-level memory tag and state, Directory/Poison and other security related metadata). The sequestered Tier II memory circuitry <NUM> stores the second portion of the ECC data <NUM><NUM> (<NUM> bits of remaining error correction). The Tier I memory circuitry <NUM>, including the first portion of the ECC data <NUM><NUM>, containing the error detection data, is read on every memory read operation, thereby permitting error detection capabilities. The controller circuitry <NUM> accesses the second portion of the ECC data <NUM><NUM> (<NUM> bits of remaining error correction data) in sequestered Tier II memory circuitry <NUM> only upon detecting an error. Tier I memory circuitry allocated to the storage of MAC data <NUM> has increased to <NUM> bits, providing an additional <NUM> bits of MAC data storage over the base configuration <NUM>. Similar to metadata configuration <NUM>, metadata configuration <NUM> beneficially provides increased capability for storage of other data, up to <NUM> bits of other data.

Configuration <NUM> provides a third metadata configuration in which Tier I memory circuitry <NUM> contains the first portion of ECC data <NUM><NUM> (error detection + partial correction data) and Tier II memory circuitry <NUM> contains the second portion of ECC data <NUM><NUM> (remaining error correction data). As depicted in configuration <NUM>, the Tier I memory circuitry <NUM> stores the first portion of the ECC data <NUM><NUM> (<NUM> bits of error detection + partial correction data), <NUM> bits of MAC data, and <NUM> bits of other data (multi-level memory tag and state and other security related metadata). The sequestered Tier II memory circuitry <NUM> stores the second portion of the ECC data <NUM><NUM> (<NUM> bits of remaining error correction). The Tier I memory circuitry <NUM>, including the first portion of the ECC data <NUM><NUM>, containing the error detection data, is read on every memory read operation, thereby permitting error detection capabilities. The controller circuitry <NUM> accesses the second portion of the ECC data <NUM><NUM> (<NUM> bits of remaining error correction data) in sequestered Tier II memory circuitry <NUM> only upon detecting an error. Tier I memory circuitry allocated to the storage of MAC data <NUM> has increased to <NUM> bits, providing enhanced security by providing an additional <NUM> bits of memory circuitry to store MAC data <NUM> over the base metadata configuration <NUM>.

<FIG> is a flow diagram of an illustrative method <NUM> that depicts a read operation using the first portion of the ECC data <NUM><NUM> stored in Tier I memory circuitry <NUM> and read with the data line <NUM> and the first portion of the ECC data <NUM><NUM> stored in sequestered Tier II memory circuitry <NUM> and read only upon detection of an error by the controller circuitry <NUM>, in accordance with at least one embodiment described herein. As depicted in <FIG>, the controller circuitry <NUM> may include multi-key circuitry <NUM>, encryption/decryption circuitry <NUM>, verification circuitry <NUM>, and metadata fetch and caching circuitry <NUM>.

Upon receipt of a read request operation <NUM> generated by an application executed by the processor circuitry <NUM>, the controller circuitry <NUM> forwards the read request to memory controller circuitry <NUM>. The encrypted data line <NUM> and the associated Tier I metadata <NUM>, including the MAC data <NUM>, first portion of the ECC data <NUM><NUM>, and other data such as multi-level memory tag and state data, is returned <NUM> to the controller circuitry <NUM>. The controller circuitry <NUM> first determines whether errors exist in the encrypted data line <NUM> using the error detection data included in the first portion of the ECC data <NUM><NUM>. Responsive to the controller circuitry <NUM> not detecting errors in the encrypted data line <NUM>, the data line <NUM> may be simultaneously or sequentially decrypted by the encryption/decryption circuitry <NUM> and verified using the MAC data <NUM> by the verification circuitry <NUM>. If the controller circuitry <NUM> detects errors in the encrypted data line <NUM>, the controller circuitry <NUM> fetches <NUM> the second portion of the ECC data <NUM><NUM> from the sequestered Tier II memory circuitry <NUM> and, using the error correction data retrieved from the Tier II memory circuitry <NUM> and/or the Tier I memory circuitry, repairs the encrypted data line <NUM>. Responsive to a successful verification of the data line <NUM> by the verification circuitry <NUM>, the decrypted data line <NUM> is returned <NUM> to the processor circuitry <NUM>.

<FIG> and the following discussion provide a brief, general description of the components forming an illustrative processor-based device <NUM> capable of implementing a scalable memory integrity and enhanced RAS system using sequestered memory such as depicted and described in detail in <FIG> (above), in accordance with at least one embodiment described herein. The processor-based device <NUM> includes processor circuitry <NUM>. The processor circuitry <NUM> executes one or more applications. During execution, the applications may cause the processor circuitry <NUM> to perform one or more memory operations, such as a memory write operation or a memory read operation. As depicted in <FIG>, in some embodiments, the processor circuitry <NUM> may include memory circuitry <NUM>, for example as processor cache circuitry. In embodiments, the processor memory circuitry <NUM> may include some or all of the Tier I memory circuitry <NUM>. As depicted in <FIG>, in embodiments, system memory circuitry <NUM> may include some or all of the sequestered Tier II memory circuitry <NUM>. Although not depicted in <FIG>, in other embodiments, the processor memory circuitry <NUM> may provide all or a portion of the Tier II memory circuitry <NUM>. For example, processor memory circuitry <NUM>, such as L1 cache memory circuitry may be used to provide all or a portion of the Tier I memory circuitry <NUM> and LLC cache memory circuitry may be used to provide all or a portion of the Tier II memory circuitry <NUM>. Those skilled in the relevant art will appreciate that the illustrated embodiments as well as other embodiments can be practiced with other circuit-based device configurations, including portable electronic or handheld electronic devices, for instance smartphones, portable computers, wearable computers, microprocessor-based or programmable consumer electronics, personal computers ("PCs"), network PCs, minicomputers, mainframe computers, and the like. The embodiments can be practiced in distributed computing environments where tasks or modules are performed by remote processing devices, which are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

The processor circuitry <NUM> and/or the controller circuitry <NUM> may include any number of circuits, some or all of which may include programmable and/or configurable combinations of electronic components, semiconductor devices, and/or logic elements that are disposed partially or wholly in a PC, server, or other computing system capable of executing machine-readable instructions. The processor-based device <NUM> may include processor circuitry <NUM>, and may, at times, include a bus or similar communications link <NUM> that communicatively couples and facilitates the exchange of information and/or data between various system components including a system memory <NUM> and the processor circuitry <NUM>. The processor-based device <NUM> may be referred to in the singular herein, but this is not intended to limit the embodiments to a single device and/or system, since in certain embodiments, there will be more than one processor-based device <NUM> that incorporates, includes, or contains any number of communicably coupled, collocated, or remote networked circuits or devices.

The processor circuitry <NUM> may include any number, type, or combination of devices. At times, the processor circuitry <NUM> may be implemented in whole or in part in the form of semiconductor devices such as diodes, transistors, inductors, capacitors, and resistors. Such an implementation may include, but is not limited to any current or future developed single- or multi-core processor or microprocessor, such as: on or more systems on a chip (SOCs); central processing units (CPUs); digital signal processors (DSPs); graphics processing units (GPUs); application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and the like. Unless described otherwise, the construction and operation of the various blocks shown in <FIG> are of conventional design. As a result, such blocks need not be described in further detail herein, as they will be understood by those skilled in the relevant art. The communications link <NUM> that interconnects at least some of the components of the processor-based device <NUM> may employ any known serial or parallel bus structures or architectures.

The system memory <NUM> may include read-only memory ("ROM") circuitry <NUM> and random access memory ("RAM") circuitry <NUM>. A portion of the ROM circuitry <NUM> may be used to store or otherwise retain a basic input/output system ("BIOS") <NUM>. The BIOS <NUM> provides basic functionality to the processor-based device <NUM>, for example by causing the processor circuitry <NUM> to load an operating system <NUM>, one or more machine-readable instruction sets <NUM>, and/or data <NUM> from the RAM circuitry <NUM>. In embodiments, at least some of the one or more machine-readable instruction sets cause the controller circuitry <NUM> to selectively provide the memory integrity performance enhancement system as described herein.

The processor-based device <NUM> may include one or more communicably coupled, non-transitory, data storage devices <NUM>. Although depicted in <FIG> as disposed internal to the processor-based device <NUM>, in various embodiments, the one or more data storage devices <NUM> may be disposed local to and/or remote from the processor-based device <NUM>. The one or more data storage devices <NUM> may include any current or future developed storage appliances, networks, and/or devices. Non-limiting examples of such data storage devices <NUM> may include, but are not limited to, any current or future developed non-transitory storage appliances or devices, such as one or more magnetic storage devices, one or more optical storage devices, one or more solid-state electromagnetic storage devices, one or more electro-resistive storage devices, one or more molecular storage devices, one or more quantum storage devices, or various combinations thereof. In some implementations, the one or more data storage devices <NUM> may include one or more removable storage devices, such as one or more flash drives, flash memories, flash storage units, or similar appliances or devices capable of communicable coupling to and decoupling from the processor-based device <NUM>.

The one or more storage devices <NUM> may include interfaces or controllers (not shown in <FIG>) communicatively coupling the respective storage device <NUM> or system to the communications link <NUM>. The one or more storage devices <NUM> may contain machine-readable instruction sets, data structures, program modules, data stores, databases, logical structures, and/or other data useful to the processor circuitry <NUM> and/or the controller circuitry <NUM>. In some instances, one or more external storage devices <NUM> may be communicably coupled to the processor circuitry <NUM>, for example via communications link <NUM> or via one or more wired communications interfaces (e.g., Universal Serial Bus or USB); one or more wireless communications interfaces (e.g., Bluetooth®, Near Field Communication or NFC); one or more wired network interfaces (e.g., IEEE <NUM> or Ethernet); and/or one or more wireless network interfaces (e.g., IEEE <NUM> or WiFi®).

Machine-readable instruction sets <NUM> and data <NUM> may be stored in whole or in part in the system memory <NUM>. Such instruction sets <NUM> may be transferred, in whole or in part, from one or more internal data storage devices and/or one or more external storage devices <NUM>. The instruction sets <NUM> may be loaded, stored, or otherwise retained in system memory <NUM>, in whole or in part, during execution by the processor circuitry <NUM>. The machine-readable instruction sets <NUM> may include machine-readable and/or processor-readable code, instructions, or similar logic capable of providing the memory integrity performance enhancement functions and capabilities described herein.

For example, the one or more machine-readable instruction sets <NUM> may cause the controller circuitry <NUM> to, in response to a write operation received from the processor circuitry <NUM>, encrypt and generate message authentication code (MAC) data <NUM> associated with the data line <NUM> to be written to the memory circuitry <NUM>. The instruction sets <NUM> may further cause the controller circuitry to generate error correction code data <NUM> associated with the encrypted data line <NUM>. The instruction sets <NUM> may further cause the controller circuitry <NUM> to write Tier I metadata <NUM>, including the MAC data <NUM> and a first portion of ECC data <NUM><NUM> (error detection data + (optionally) partial error correction data) to the Tier I memory circuitry <NUM>. The instruction sets <NUM> may further cause the controller circuitry <NUM> to write Tier II metadata <NUM>, including a second portion of ECC data <NUM><NUM> (full or partial error correction data) to the Tier II memory circuitry <NUM>.

The one or more machine-readable instruction sets <NUM> may cause the controller circuitry <NUM> to, in response to a read operation received from the processor circuitry <NUM>, to retrieve the Tier I metadata <NUM>, including the MAC data <NUM> and a first portion of ECC data <NUM><NUM> (error detection data + (optionally) partial error correction data) from the Tier I memory circuitry <NUM>. The instruction sets <NUM> may further cause the controller circuitry <NUM> to detect the presence of errors in the encrypted data line <NUM> using the error detection data included in the first portion of ECC data <NUM><NUM>. Responsive to detecting an error in the encrypted data line <NUM>, the instruction sets <NUM> may further cause the controller circuitry <NUM> to fetch the second portion of ECC data <NUM><NUM> from the sequestered Tier II memory circuitry <NUM> and correct the errors in the encrypted data line <NUM> using the error correction data included in the first portion of ECC data <NUM><NUM> and the second portion of ECC data <NUM><NUM>. Responsive to detecting no errors in the encrypted data line <NUM> or after repairing the errors present in the encrypted data line <NUM>, the instruction sets <NUM> may cause the controller circuitry <NUM> to simultaneously or sequentially decrypt the encrypted data line <NUM> and verify the data included in the data line <NUM> using the MAC data <NUM> included in the first portion of ECC data <NUM><NUM>. Responsive to a successful verification of the data line <NUM>, the instruction sets <NUM> may cause the controller circuitry <NUM> to forward the data line <NUM> to the processor circuitry <NUM>. Responsive to an unsuccessful verification of the data line <NUM>, the instruction sets <NUM> may cause the controller circuitry <NUM> to generate an exception and/or return a null value to the processor circuitry <NUM>.

Processor-based device users may provide, enter, or otherwise supply commands (e.g., acknowledgements, selections, confirmations, and similar) as well as information and/or data (e.g., subject identification information, color parameters) to the processor-based device <NUM> using one or more communicatively coupled physical input devices <NUM> such as one or more text entry devices <NUM> (e.g., keyboard), one or more pointing devices <NUM> (e.g., mouse, trackball, touchscreen), and/or one or more audio input devices <NUM>. Some or all of the physical input devices <NUM> may include a wired or a wireless communicable coupling to the processor-based device <NUM>.

Processor-based device users may receive output from the processor-based device <NUM> via one or more physical output devices <NUM>. In at least some implementations, the one or more physical output devices <NUM> may include but are not limited to one or more: video output or display devices <NUM>; tactile output devices <NUM>; audio output devices <NUM>, or combinations thereof. Some or all of the physical input devices <NUM> and some or all of the physical output devices <NUM> may be communicatively coupled to the processor-based device <NUM> via one or more wired or wireless interfaces.

For convenience, a network interface <NUM>, the processor circuitry <NUM>, the controller circuitry <NUM>, the system memory <NUM>, the physical input devices <NUM> and the physical output devices <NUM> are illustrated as communicatively coupled to each other via the communications link <NUM>, thereby providing connectivity between the above-described components. In alternative embodiments, the above-described components may be communicatively coupled in a different manner than illustrated in <FIG>. For example, one or more of the above-described components may be directly coupled to other components, or may be coupled to each other, via one or more intermediary components (not shown). In some embodiments, all or a portion of the communications link <NUM> may be omitted and the components are coupled directly to each other using suitable wired or wireless connections.

<FIG> is a high-level logic flow diagram of an illustrative memory integrity performance enhancement method <NUM>, in accordance with at least one embodiment described herein. The method <NUM> commences at <NUM>.

At <NUM>, the controller circuitry <NUM> receives a memory access request from the processor circuitry <NUM>. In at least some embodiments, the memory access request may be generated by one or more applications executed by the processor circuitry <NUM>.

At <NUM>, the controller circuitry <NUM> determines whether the received memory access request includes a read request. Responsive to a determination by the controller circuitry <NUM> that the received memory access request IS NOT a read request, the method <NUM> continues at <NUM> Responsive to a determination by the controller circuitry <NUM> that the received memory access request IS a read request, the method <NUM> continues at <NUM>.

At <NUM>, responsive to a determination by the controller circuitry <NUM> that the received memory access request IS NOT a read request, the controller circuitry <NUM> encrypts the received data line <NUM> and generates MAC data <NUM> for the encrypted data line <NUM>.

At <NUM>, the controller circuitry <NUM> generates error correction code (ECC) data <NUM> for the encrypted data line <NUM>. In embodiments, the ECC data <NUM> includes error detection data (e.g., <NUM> bit error detection data) and error correction data (e.g., <NUM> bit error correction data).

At <NUM>, the controller circuitry <NUM> writes the encrypted data line <NUM>, and Tier I metadata <NUM> including the MAC data <NUM> and the first portion of the ECC data <NUM><NUM> to the Tier I memory circuitry <NUM>. In embodiments, the first portion of the ECC data <NUM><NUM> may include error detection data and, optionally, partial error correction data.

At <NUM>, the controller circuitry <NUM> writes Tier II metadata <NUM> including all or a portion of the second portion of the ECC data <NUM><NUM> to the Tier II memory circuitry <NUM>. In embodiments, the second portion of the ECC data <NUM><NUM> may include some or all of the error correction data. The method <NUM> then concludes at <NUM>.

At <NUM>, responsive to a determination by the controller circuitry <NUM> that the received memory access request IS a read request, the controller circuitry <NUM>, communicates the read request to the memory circuitry <NUM>. The read request retrieves the encrypted data line <NUM> and the Tier I metadata <NUM> (including the MAC data <NUM> and the first portion of the ECC data <NUM><NUM> along with any other data such as multi-level tag and state data) from the Tier I memory circuitry <NUM>.

At <NUM>, using the error detection data included in the first portion of the ECC data <NUM><NUM>, the controller circuitry <NUM> determines whether errors exist in the retrieved, encrypted data line <NUM>.

At <NUM>, if the controller circuitry <NUM> detects errors in the encrypted data line <NUM>, the method <NUM> continues at <NUM>. If the controller circuitry <NUM> fails to detect errors in the encrypted data line, the method <NUM> continues at <NUM>.

At <NUM>, responsive to a determination by the controller circuitry <NUM> that the encrypted data line <NUM> contains errors, the controller circuitry <NUM> fetches the Tier II metadata <NUM>, including the second portion of the ECC data <NUM><NUM> (including the remaining portion of the error correction data) from the Tier II memory circuitry <NUM>.

At <NUM>, the controller circuitry <NUM> corrects the encrypted data line <NUM> using the error correction data included in the first portion of the ECC code <NUM><NUM> and/or the second portion of the ECC code <NUM><NUM>.

At <NUM>, the controller circuitry <NUM> simultaneously or sequentially decrypts the encrypted data line <NUM> and, using the MAC data <NUM> included in the Tier I metadata <NUM> and retrieved from the Tier I memory circuitry <NUM>, verifies the data line <NUM>.

At <NUM>, the controller circuitry <NUM> determines whether the verification of the data line <NUM> has failed or succeeded. Responsive to a successful verification of the data line <NUM> by the controller circuitry <NUM>, the method <NUM> continues at <NUM>. Responsive to an unsuccessful verification of the data line <NUM> by the controller circuitry <NUM>, the method <NUM> continues at <NUM>.

At <NUM>, responsive to an unsuccessful verification of the data line <NUM> at <NUM>, the controller circuitry <NUM> signals an exception and may return a null value to the processor circuitry. The method <NUM> then concludes at <NUM>.

At <NUM>, responsive to a successful verification of the data line <NUM> at <NUM>, the controller circuitry <NUM> communicates the decrypted data line <NUM> to the processor circuitry <NUM>. The method <NUM> then concludes at <NUM>.

While <FIG> illustrates various operations according to one or more embodiments, it is to be understood that not all of the operations depicted in <FIG> are necessary for other embodiments. Indeed, it is fully contemplated herein that in other embodiments of the present disclosure, the operations depicted in <FIG>, and/or other operations described herein, may be combined in a manner not specifically shown in any of the drawings, but still fully consistent with the present disclosure. Thus, claims directed to features and/or operations that are not exactly shown in one drawing are deemed within the scope and content of the present disclosure.

As used in this application and in the claims, a list of items joined by the term "and/or" can mean any combination of the listed items. For example, the phrase "A, B and/or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. As used in this application and in the claims, a list of items joined by the term "at least one of" can mean any combination of the listed terms. For example, the phrases "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

As used in any embodiment herein, the terms "system" or "module" may refer to, for example, software, firmware and/or circuitry configured to perform any of the aforementioned operations. Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on non-transitory computer readable storage mediums. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices. "Circuitry", as used in any embodiment herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry or future computing paradigms including, for example, massive parallelism, analog or quantum computing, hardware embodiments of accelerators such as neural net processors and non-silicon implementations of the above. The circuitry may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smartphones, etc..

Any of the operations described herein may be implemented in a system that includes one or more mediums (e.g., non-transitory storage mediums) having stored therein, individually or in combination, instructions that when executed by one or more processors perform the methods. Here, the processor may include, for example, a server CPU, a mobile device CPU, and/or other programmable circuitry. Also, it is intended that operations described herein may be distributed across a plurality of physical devices, such as processing structures at more than one different physical location. The storage medium may include any type of tangible medium, for example, any type of disk including hard disks, floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, Solid State Disks (SSDs), embedded multimedia cards (eMMCs), secure digital input/output (SDIO) cards, magnetic or optical cards, or any type of media suitable for storing electronic instructions. Other embodiments may be implemented as software executed by a programmable control device.

Thus, the present disclosure is directed to systems and methods for providing a scalable memory integrity and enhanced RAS using sequestered memory. A write request causes controller circuitry to write an encrypted data line and Tier I metadata including MAC data and a first portion of ECC data (error detection) to Tier I memory circuitry and a second portion of ECC data (error correction) to sequestered Tier II memory circuitry. A read request causes the controller circuitry to read the encrypted data line and the Tier I metadata from the Tier I memory circuitry. Using the first portion of the ECC data included in the Tier I metadata the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data. If an error in the data line is detected by the controller circuitry, the second portion of the ECC data is fetched from the Tier II memory circuitry and the error corrected.

Claim 1:
A data storage method, comprising:
generating, by controller circuitry (<NUM>, <NUM>), metadata (<NUM>, 134A-134n, <NUM>, 142A-142n) for each respective one of a plurality of lines of data (<NUM>, 132A-132n, <NUM>) stored in memory circuitry (<NUM>, <NUM>, <NUM>, <NUM>), the metadata (<NUM>, 134A-134n, <NUM>, 142A-142n) including:
data representative of a cryptographic message authentication code, MAC, associated with the respective line of data (<NUM>, 132A-132n, <NUM>); and
data representative of an error correction code, ECC (138A-n), associated with the respective line of data (<NUM>, 132A-132n, <NUM>), the error correction code (138A-n) including at least an error detection data portion associated with the respective line of data (<NUM>, 132A-132n, <NUM>) and an error correction data portion associated with the respective line of data (<NUM>, 132A-132n, <NUM>); and
apportioning, by the controller circuitry (<NUM>, <NUM>), the metadata (<NUM>, 134A-134n, <NUM>, 142A-142n) into a First Tier metadata portion stored in a first memory circuitry portion proximate the respective line of data (<NUM>, 132A-132n, <NUM>) and a Second Tier metadata portion stored in a sequestered, second memory circuitry portion remote from the respective line of data (<NUM>, 132A-132n, <NUM>);
wherein the First Tier metadata portion includes at least the error detection data portion and the message authentication code of the metadata (<NUM>, 134A-134n, <NUM>, 142A-142n) associated with the respective line of data (<NUM>, 132A-132n, <NUM>); and
wherein the Second Tier metadata portion includes at least a portion of the error correction data portion of the metadata (<NUM>, 134A-134n, <NUM>, 142A-142n) associated with the respective line of data (<NUM>, 132A-132n, <NUM>).