Patent Description:
Semiconductor manufactures developed vertical device technologies, such as three dimensional (3D) NAND flash memory technology, and the like to achieve higher data storage density without requiring smaller memory cells. In some examples, a 3D NAND memory device includes a core region and a staircase region. The core region includes a stack of alternating gate layers and insulating layers. The stack of alternating gate layers and insulating layers is used to form memory cells that are stacked vertically. The staircase region includes the respective gate layers in the stair-step form to facilitate forming contacts to the respective gate layers. The contacts are used to connect driving circuitry to the respective gate layers for controlling the stacked memory cells. <CIT> discloses a memory device with two dies, wherein the first die comprises a three-dimensional array of storage cells and the second die includes CMOS Cells which, wherein the two dies are bounded together. <CIT> discloses a method of fabricating a semiconductor device with alternately stacking a plurality of dielectric layers and conductive layers on a substrate, wherein photoresist patterns are arranged on the stack structure.

<CIT>, see in particular figure 17A, shows a strap-type contact to the channel structures in a 3D NAND memory.

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of layers. The stack of layers includes a common source layer, gate layers and insulating layers disposed on a substrate. The gate layers and insulating layers are stacked alternatingly. Then, the semiconductor device includes an array of channel structures formed in an array region. The channel structure extends through the stack of layers and forms a stack of transistors in a series configuration. The channel structure includes a channel layer that is in contact with the common source layer. The common source layer extends over the array region and a staircase region. The semiconductor device includes a contact structure disposed in the staircase region. The contact structure forms a conductive connection with the common source layer.

In some embodiments, the common source layer includes a metal silicon compound layer and a silicon layer. The metal silicon compound layer includes at least one of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt).

According to an aspect of the disclosure, the semiconductor device includes a gate line cut structure with a bottom conductive layer in conductive connection with the common source layer. In some embodiments, the gate line cut structure includes an upper insulating portion that is above the bottom conductive layer. In an embodiment, the bottom conductive layer comprises a metal silicon compound layer.

In an embodiment, the array region is a first array region in a block, and the contact structure is disposed in the staircase region that is located between the first array region and a second array region in the block.

In another embodiment, the contact structure is a first contact structure, and the staircase region is a first staircase region located on a first side of the array region. The semiconductor device further includes a second contact structure disposed in a second staircase region that is located at a second side of the array region that is opposite to the first side of the array region. The common source layer extends over the second staircase region, and the second contact structure is conductively connected with the common source layer.

In some embodiments, the substrate is a first substrate having a face side and a back side, the channel structures are formed on the face side of the substrate. The semiconductor device further includes a second substrate having a face side and a back side. Transistors can be formed on the face side of the second substrate. The second substrate has bonding structures on the face side to be aligned and bonded with corresponding bonding structures on the face side of the first substrate. In some examples, the semiconductor device has contact pads disposed on the back side of the first substrate. In some other examples, the semiconductor device has contact pads disposed on the back side of the second substrate.

Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming a stack of layers on a substrate. The stack of layers includes a source sacrificial layer, a conductive layer, gate sacrificial layers and insulating layers. Further, the method includes forming a staircase into the stack of layers in a staircase region that is adjacent to an array region, and forming channel structures in the array region, a channel structure including a channel layer surrounded by one or more insulating layers and extending into the stack of layers. Then, the method includes replacing the source sacrificial layer with a source layer in conductive connection with the channel layer, and replacing the gate sacrificial layers with gate layers. The source layer and the conductive layer form a common source. The method further includes forming a first contact structure in the staircase region structure, the first contact structure forming a conductive connection with the common source.

In some embodiments, the method includes etching a gate line cut trench into the stack of layer with the conductive layer being an etch stop layer. Further, the method includes replacing, through the gate line cut trench, the source sacrificial layer with the source layer, forming a silicide layer with the source layer at a bottom of the gate line cut trench and filling the gate line cut trench with insulating material.

In some embodiments, the method includes etching a contact hole corresponding to the first contact structure, with the conductive layer being an etch stop layer.

In some examples, the method includes forming the first contact structure based on a mask including a first pattern for the first contact structure and a second pattern for forming a second contact structure to a gate layer. Further, the method includes forming a second contact structure at a border of an erase block away from array regions of the erase block. In an example, the method includes connecting the first contact structure with other contact structures to the common source using metal wires that are routed away from the array region.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Aspects of the disclosure provide an array common source (ACS) technology for a vertical memory device and an ACS contact technology for connecting ACS to peripheral circuitry. Specifically, in some embodiments, a high conductive layer, such as a metal layer, a metal compound layer, a metal silicide layer and the like, is formed in connection with sources of vertical memory cell strings. The vertical memory cell strings are formed as arrays in a core region and the high conductive layer extends in the core region and forms an array common source (ACS) with relatively high current conductivity. The high conductive layer further extends into a connection region. The connection region includes a staircase structure that is used to form connections to gates of the vertical memory cell strings. A contact structure to the high conductive layer can be formed in the connection region. The contact structure can be used to interconnect the ACS with other circuitry, such as peripheral circuitry for the vertical memory device.

According to an aspect of the disclosure, the ACS and ACS contact technologies disclosed in the present disclosure can achieve various benefits over a related example. For example, the related example forms ACS structures for vertical memory cell strings in gate line cut structures, and uses conductive wires above the core region to interconnect contacts of the ACS structures for current distribution. In the related example, the area beneath the conductive wires (that interconnect the contacts of the ACS structures) in the core region is not desirable for operations of vertical memory cell strings. The present disclosure uses the high conductive layer to form ACS and distribute current, and uses contact structures in the connection region to connect the ACS to peripheral circuitry, thus area in the core region can be efficiently used for forming vertical memory cell strings. Then, for the same amount of memory bytes, the present disclosure can achieve smaller core region compared to the related example. Other benefits will be described further in the description.

<FIG> shows a cross-sectional view of a semiconductor device <NUM> according to some embodiments of the disclosure. The semiconductor device <NUM> includes a substrate <NUM>, and circuits formed on the thereupon. For simplicity, the main surface of the substrate <NUM> is referred to as an X-Y plane, and the direction perpendicular to the main surface is referred to as Z direction.

The semiconductor device <NUM> refers to any suitable device, for example, memory circuits, a semiconductor chip (or die) with memory circuits formed on the semiconductor chip, a semiconductor wafer with multiple semiconductor dies formed on the semiconductor wafer, a stack of semiconductor chips, a semiconductor package that includes one or more semiconductor chips assembled on a package substrate, and the like. The substrate <NUM> can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate. The substrate <NUM> may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate <NUM> may be a bulk wafer or an epitaxial layer. In the <FIG> example, a well <NUM> is formed on the substrate <NUM>, the well <NUM> can be N-type doped polysilicon or P-type doped polysilicon. For example, in the example that P-type well is used, the P-type well is the body portion for memory cell strings, and can provide holes during erase operation using body erase mechanism. During read operation, an array common source (will be described in detail) can drive electrons to channels during the read operation. In another example that N-type well is used, a gate induced drain leakage (GIDL) erase mechanism can be used in the erase operation. Specifically, a high field is applied on a P-N junction, and generates holes due to band-to-band tunneling.

In various embodiments, the semiconductor device <NUM> includes three dimensional (3D) NAND memory circuitry formed on the substrate <NUM>. The semiconductor device <NUM> can include other suitable circuitry (not shown), such as logic circuitry, power circuitry, and the like that is formed on the substrate <NUM>, or other suitable substrate, and is suitably coupled with the 3D NAND memory circuitry. Generally, the 3D NAND memory circuitry includes memory cell arrays and peripheral circuitry (e.g., address decoder, driving circuits, sense amplifier and the like). A memory cell array is formed in a core region <NUM> as an array of vertical memory cell strings. The peripheral circuitry is formed in a peripheral region (not shown). Besides the core region <NUM> and the peripheral region, the semiconductor device <NUM> includes a staircase region <NUM> (also referred to as a connection region in some examples) to facilitate making connections to, for example, gates of the memory cells in the vertical memory cell strings. The gates of the memory cells in the vertical memory cell strings correspond to word lines for the NAND memory architecture.

In the example of <FIG>, vertical memory cell strings <NUM> are shown as representation of an array of vertical memory cell strings formed in the core region <NUM>. The vertical memory cell strings <NUM> are formed in a stack of layers <NUM>. The stack of layers <NUM> includes gate layers <NUM> and insulating layers <NUM> that are stacked alternatingly. The gate layers <NUM> and the insulating layers <NUM> are configured to form transistors that are stacked vertically. In some examples, the stack of transistors includes memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors and the like. In some examples, the stack of transistors can include one or more dummy select transistors. The gate layers <NUM> correspond to gates of the transistors. The gate layers <NUM> are made of gate stack materials, such as high dielectric constant (high-k) gate insulator layers, metal gate (MG) electrode, and the like. The insulating layers <NUM> are made of insulating material(s), such as silicon nitride, silicon dioxide, and the like.

According to some aspects of the disclosure, the vertical memory cell strings are formed of channel structures <NUM> that extend vertically (Z direction) into the stack of layers <NUM>. The channel structures <NUM> can be disposed separate from each other in the X-Y plane. In some embodiments, the channel structures <NUM> are disposed in the form of arrays between gate line cut structures <NUM> (also referred to as gate line slit structures in some examples). The gate line cut structures <NUM> are used to facilitate replacement of sacrificial layers with the gate layers <NUM> in a gate-last process. The arrays of the channel structures <NUM> can have any suitable array shape, such as a matrix array shape along the X direction and the Y direction, a zig-zag array shape along the X or Y direction, a beehive (e.g., hexagonal) array shape, and the like. In some embodiments, each of the channel structures has a circular shape in the X-Y plane, and a pillar shape in the X-Z plane and Y-Z plane. In some embodiments, the quantity and arrangement of the channel structures between gate line cut structures is not limited.

As shown in the <FIG> example, a vertical memory cell string <NUM> is formed of a channel structure <NUM>. In some embodiments, the channel structure <NUM> has a pillar shape that extends in the Z direction that is perpendicular to the direction of the main surface of the substrate <NUM>. In an embodiment, the channel structure <NUM> is formed by materials in the circular shape in the X-Y plane, and extends in the Z direction. For example, the channel structure <NUM> includes function layers, such as a blocking insulating layer <NUM> (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride) <NUM>, a tunneling insulating layer <NUM> (e.g., silicon oxide), a semiconductor layer <NUM>, and an insulating layer <NUM> that have the circular shape in the X-Y plane, and extend in the Z direction. In an example, the blocking insulating layer <NUM> (e.g., silicon oxide) is formed on the sidewall of a hole (into the stack of layers <NUM>) for the channel structure <NUM>, and then the charge storage layer (e.g., silicon nitride) <NUM>, the tunneling insulating layer <NUM>, the semiconductor layer <NUM>, and the insulating layer <NUM> are sequentially stacked from the sidewall. The semiconductor layer <NUM> can be any suitable semiconductor material, such as polysilicon or monocrystalline silicon, and the semiconductor material may be un-doped or may include a p-type or n-type dopant. In some examples, the semiconductor material is intrinsic silicon material that is un-doped. However due to defects, intrinsic silicon material can have a carrier density in the order of <NUM><NUM> cm-<NUM> in some examples. The insulating layer <NUM> is formed of an insulating material, such as silicon oxide and/or silicon nitride, and/or may be formed as an air gap.

According to some aspects of the disclosure, the channel structure <NUM> and the stack of layers <NUM> together form the memory cell string <NUM>. For example, the semiconductor layer <NUM> corresponds to the channel portions for transistors in the memory cell string <NUM>, and the gate layers <NUM> corresponds to the gates of the transistors in the memory cells string <NUM>. Generally, a transistor has a gate that controls a channel, and has a drain and a source at each side of the channel. For simplicity, in the <FIG> example, the upper side of the channel for transistors in <FIG> is referred to as the drain, and the bottom side of the channel for transistors in <FIG> is referred to as the source. It is noted that the drain and the source can be switched under certain driving configurations. In the <FIG> example, the semiconductor layer <NUM> corresponds to connected channels of the transistors. For a specific transistor, the drain of the specific transistor is connected with a source of an upper transistor above the specific transistor, and the source of the specific transistor is connected with a drain of a lower transistor below the specific transistor. Thus, the transistors in the memory cell string <NUM> are connected in series.

According to some aspects of the disclosure, the bottom portion of the semiconductor layer <NUM> in the hole corresponds to a source of the vertical memory cell string <NUM>, and a common source layer <NUM> is formed in conductive connection with the source of the vertical memory cell string <NUM>. The common source layer <NUM> can includes one or more layers. In the <FIG> example, and according to the invention, the common source layer <NUM> includes a high conductive layer <NUM> and a source layer <NUM>. According to the invention, the source layer <NUM> is silicon material, such as intrinsic polysilicon, doped polysilicon (such as N-type doped silicon, P-type doped silicon) and the like.

Similarly, the common source layer <NUM> is in conductive connection with sources of other vertical memory cell strings, and thus forms an array common source, and can be referred to as a source connection layer in some examples. In some examples, when the vertical memory cell strings <NUM> are configured to be erased by block, the common source layer <NUM> can extend and cover the core regions of a block and staircase regions for the block. In some examples, for different blocks that are erased separately, the common source layer <NUM> may be suitably insulated for the different blocks.

The high conductive layer <NUM> is configured to have a relatively large current conductivity and an extensive coverage in the X-Y plane, thus the common source layer <NUM> can have relatively small resistance and provide relatively efficient current distribution. According to the invention, the high conductive layer <NUM> comprises at least one of a metal, metal compound, metal silicide and the like. In some embodiments, the high conductive layer <NUM> is formed of a metal silicide that includes metal and silicon (e.g., has a form of MxSiy), the metal can be any suitable metal, such as titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), and the like.

According to the invention, the bottom portion of the gate line cut structure <NUM> also includes a high conductive layer <NUM>, such as a metal silicide layer that is conductively connected with the high conductive layer <NUM>. According to the invention, the bottom high conductive layer <NUM> comprises different materials from the high conductive layer <NUM>. The high conductive layer <NUM> is formed in different process steps from the high conductive layer <NUM>. It is noted that, in the <FIG> example, and according to the invention, the upper portion of the gate line cut structure <NUM> are filled with insulating material, such as silicon oxide, and the like. Thus, the gate line cut structure <NUM> is not used for ACS contact in the <FIG> example, and according to the invention.

In a related example, ACS contact structures are formed in the gate line cut structures and have various issues, such as word line to ACS leakage, a relatively large word line to ACS capacitance, stress during process due to the ACS contact in the gate line cut structures and the like. The present disclosure provides techniques to dispose the ACS contact away from the array region, for example, in the staircase region, around block border or die border, and the like, thus the issues, such as word line to ACS leakage, a relatively large word line to ACS capacitance, stress during process due to the ACS contact in the gate line cut structures and the like can be resolved. For example, the present disclosure can achieve word line to ACS leakage free, no word line to ACS capacitance, and no ACS contact related stress to the array region in some embodiments.

According to an aspect of the disclosure, the common source layer <NUM> covers extensively in the X-Y plane, and contacts (also referred to as ACS contact in some examples) to the common source layer <NUM> can be formed in any suitable locations, such as the staircase region, array borders, die borders, and the like. In some embodiments, the contacts to the common source layer <NUM> can be formed at the same time with other contacts (e.g., word line contacts, bit line contacts and the like) using a same mask, and the high conductive layer <NUM> can be used as an etch stop layer for the contacts to the common source layer <NUM>. It is noted that in the related example that forms ACS contact in the gate line cut structures, a separate mask (different from a general contact mask) is used with additional process steps to form the ACS contact. Thus, the ACS and ACS contact technologies in the present disclosure have a reduced number of masks.

According to some aspects of the disclosure, due to the use of the high conductive layer <NUM>, the contacts (also referred to as ACS contact) to the common source layer <NUM> can be disposed with flexibility, and the ACS and ACS contact technologies in the present disclosure can be used with other vertical memory device technologies. In some examples, the ACS and ACS contact technologies disclosed in the present disclosure can be used with various staircase implementations, such as center staircase implementation, side staircase implementation and the like. In some examples, the ACS and ACS contact technologies disclosed in the present disclosure can be used with various pad-out implementations, such as array die side pad-out implementation, CMOS die side contact pad implementation, and the like.

In the <FIG> example, an ACS contact structure <NUM> is configured to connect the common source layer <NUM> to a driving circuitry (not shown) for source terminals of the vertical memory cell strings. The driving circuitry can provide suitable driving voltages and powers to the ACS (e.g., common source layer <NUM>) during operation.

In the <FIG> example, the ACS contact structure <NUM> includes a contact structure <NUM>, a via structure <NUM>, and a metal wire <NUM>. The contact structure <NUM>, the via structure <NUM> and the metal wire <NUM> are conductively coupled together. In some embodiments, the ACS contact structure <NUM> has similar configuration as the other connection structures, such as word line connection structures <NUM>. For example, as shown in <FIG>, a word line connection structure <NUM> includes a contact structure <NUM>, a via structure <NUM>, and metal wire <NUM> that are conductively coupled together. In some examples, the contact structure <NUM> can be formed with the contact structure <NUM> using a same mask, same process steps, and same materials; the via structure <NUM> can be formed with the via structure <NUM> using a same mask, same process steps, and same materials; and the metal wire <NUM> and the metal wire <NUM> can be formed using a same mask, same process steps, and same materials.

<FIG> show some top views for a semiconductor device, such as the semiconductor device <NUM> according to some embodiments of the disclosure. It is noted that, for ease of illustration, <FIG> show a portion of the layers in the semiconductor device, and omit other layers.

<FIG> shows a top view <NUM> for a semiconductor device, such as the semiconductor device <NUM>, according to some embodiments of the disclosure. The top view <NUM> includes patterns that correspond to top views of some components of the semiconductor device in the X-Y plane. In an example, <FIG> is a cross-sectional view of the semiconductor device along A-A' line shown in <FIG>.

In the <FIG> example, the top view <NUM> includes patterns <NUM> for gate line cut structures, such as the gate line cut structure <NUM> in <FIG>. The patterns <NUM> have narrow rectangular shapes and are disposed parallel to the X direction. The top view <NUM> can include a core region <NUM> (also referred to as array region in some examples) and staircase regions <NUM> (also referred to as connection regions in some examples) that are disposed at two opposite sides of the core region <NUM> in the X direction.

The top view <NUM> includes patterns <NUM> in the core region <NUM> for channel structures, such as the channel structures <NUM> in <FIG>. The top view <NUM> also includes patterns <NUM>(D) in the staircase regions <NUM> for dummy channel structures.

According to some aspects of the disclosure, a common source layer <NUM> extensively covers the core region <NUM> and the staircase region <NUM>, and has a high conductive layer (not shown), thus contacts to the common source layer <NUM> can be disposed with flexibility. In an example, contacts can be disposed in the staircase regions <NUM> as shown by <NUM>. In another example, contacts can be disposed at a border of the block, such as shown by <NUM> (B) of the top view <NUM>.

<FIG> shows a top view <NUM> for a semiconductor device, such as the semiconductor device <NUM>, according to some embodiments of the disclosure. The top view <NUM> includes patterns that correspond to top view of some components of the semiconductor device in the X-Y plane. In an example, <FIG> is a cross-sectional view of the semiconductor device along B-B' line shown in <FIG>.

In the <FIG> example, the top view <NUM> includes patterns <NUM> for gate line cut structures, such as the gate line cut structure <NUM> in <FIG>. The patterns <NUM> have narrow rectangular shapes and are disposed parallel to the X direction. The top view <NUM> can include two core regions <NUM> (also referred to as array regions in some examples) and a staircase region <NUM> (also referred to as connection region in some examples) that is disposed between the core regions <NUM>.

The top view <NUM> includes patterns <NUM> in the core regions <NUM> for channel structures, such as the channel structures <NUM> in <FIG>. The top view <NUM> also includes patterns <NUM>(D) in the staircase region <NUM> for dummy channel structures.

According to some aspects of the disclosure, the common source layer <NUM> extensively covers the core regions <NUM> and the staircase region <NUM> and includes a high conductive layer, thus contacts to the common source layer <NUM> can be disposed with flexibility. In an example, contacts can be disposed in the staircase region <NUM> as shown by <NUM>. In another example, contacts can be disposed at a border of the block, such as shown by <NUM> (B) of the top view <NUM>.

<FIG> shows a top view <NUM> for a semiconductor device, such as the semiconductor device <NUM>, according to some embodiments of the disclosure. In some examples, the top view <NUM> is top view of a die, and includes patterns that correspond to top views of some components, such as the common source layer <NUM> (ACS), the contact structures <NUM>, via structures <NUM> to the contact structures, metal wires <NUM> for interconnecting the via structures <NUM> in the X-Y plane.

In the <FIG> example, the top view <NUM> shows two rectangular regions <NUM> (L and R) for the common source layer, such as the common source layer <NUM>. Further, the top view shows two core regions <NUM> respectively in the two rectangular regions <NUM> (L and R). A staircase region <NUM> is disposed between the two core regions <NUM> (L and R). The rectangular regions <NUM> (L and R) expend and cover a large portion of the die, such as the core regions <NUM> (L and R) and the staircase region <NUM> and the like, and due to a use of a high conducive layer in the common source layer <NUM>, thus the common source layer can provide relatively high conductivity for current distribution. It is noted that, the high conductive layer can include holes (not shown) corresponding to bottoms of channel structures (and/or dummy channel structures).

The top view <NUM> also includes patterns <NUM> (L and R) corresponding to contact structures, such as the contact structure <NUM> in <FIG> and the like, that are in conductive connection with the array common source, such as the common source layer <NUM>. It is noted that while rectangular shape of the patterns <NUM> (L and R) is used to illustrate the contact structures, the contact structures can have other suitable shape, such as circular shape, oval shape, and the like. It is noted that, in some embodiments, the semiconductor device also includes via patterns that may have the similar but smaller top view patterns as the patterns <NUM>. The via patterns correspond to via structures, such as the via structure <NUM> in <FIG>. The via structures can be used to conductively connect the contact structures <NUM> with metal wires.

In the <FIG> example, the patterns <NUM> (L and R) are disposed in the staircase region <NUM> and around the borders of the rectangular regions <NUM> (L and R). For example, patterns <NUM>(L) are disposed around the borders of the left rectangular region <NUM>(L), and patterns <NUM>(R) are disposed around the borders of the right rectangular region <NUM>(R). Further, the top view <NUM> includes pattern <NUM> that corresponds to metal wires, such as metal wire <NUM> and the like, that are used to connect the contact structures <NUM>.

In an example that the two core regions belong to the same block (e.g., erase block with memory cells to be erased at the same time), the metal wires <NUM> as shown by patterns <NUM> connect the contact structures <NUM> as shown by patterns <NUM> (L and R), for example, via the via structures. It is note that, when the two core regions belong to different blocks, the metal wires <NUM> as shown by patterns <NUM> can be suitably configured to separately connect the contact structures <NUM>(L) together, and then the contact structures <NUM>(R) together.

Further, in <FIG> example, the top view <NUM> also shows patterns <NUM> corresponding to contact pads for the semiconductor device. In some embodiments, the semiconductor device includes an array die and a complementary metal-oxide-semiconductor (CMOS) die that are bonded together. The array die includes vertical memory cell strings, and the CMOS die includes peripheral circuitry for the vertical memory cell strings. In some embodiments, the array die provides the contact pads for the bonded dies. The contact pads can be used to connect the semiconductor device (array die and the CMOS die) to other circuitry.

It is noted that the patterns <NUM> are for illustrations, the number of the contact pads, the sizes of the contact pads, the distances between the contact pads and the like can be adjusted for example, based on design requirements, supply voltage requirements, contact resistance requirements for the contact pads.

<FIG> shows a top view <NUM> for a semiconductor device, such as the semiconductor device <NUM>, according to some embodiments of the disclosure. In some examples, the top view <NUM> is top view of a die, and includes patterns that correspond to top views of some components, such as the common source layer <NUM> (ACS), the contact structures <NUM>, via structures to the contact structures, metal wires for interconnecting the via structures in the X-Y plane.

In the <FIG> example, the top view <NUM> shows a rectangular region <NUM> corresponding to the array common source, such as the common source layer <NUM>. Further, the top view <NUM> shows a core region <NUM> and two staircase regions <NUM> respectively disposed at two sides of the core region <NUM>. The pattern <NUM> covers a large portion of the die, such as the core region <NUM> and the staircase regions <NUM> and the like. Due to the use of a high conductive layer in the common source layer <NUM>, the common source layer <NUM> can provide relatively high conductivity for current distribution. It is noted that the high conductive layer can include holes (not shown) corresponding to bottoms of channel structures (and/or dummy channel structures).

The top view <NUM> also includes patterns <NUM> corresponding to contact structures, such as the contact structure <NUM> in <FIG> and the like, that are in conductive connection with the common source layer <NUM>. It is noted that while rectangular shape of the patterns <NUM> is used to illustrate the contact structures, the contact structures can have other suitable shape, such as circular shape, oval shape, and the like. It is noted that, in some embodiments, the semiconductor device also includes via patterns that may have the similar but smaller top view patterns as the patterns <NUM>. The via patterns correspond to via structures, such as the via structure <NUM> in <FIG>. The via structures can be used to conductively connect the contact structures <NUM> with metal wires.

In the <FIG> example, the patterns <NUM> are disposed in the staircase region <NUM> and around the border of the pattern <NUM>. Further, the top view <NUM> includes pattern <NUM> that corresponds to metal wires, such as metal wire <NUM> and the like, that are used to connect the contact structures <NUM>.

It is noted that in the examples shown in <FIG>, the contact structures to the common source layer can be connected using metal wires that are routed way from the array region, thus the array region can be efficiently used for vertical memory cell strings of data storage.

<FIG> shows a cross-sectional view of a semiconductor device <NUM> having an array die and a CMOS die bonded together according to some embodiments of the disclosure.

The array die includes components that are configured similarly as corresponding components of the semiconductor device <NUM> shown in <FIG>. For example, a substrate <NUM> is similarly configured as the substrate <NUM>; a core region <NUM> that is similarly configured as the core region <NUM>; a staircase region <NUM> is similarly configured as the staircase region <NUM>; vertical memory cell strings <NUM> are similarly configured as the vertical memory cell strings <NUM>; a stack of layers <NUM> is similarly configured as the stack of layers <NUM>; channel structures <NUM> are similarly configured as the channel structures <NUM>; gate line cut structures <NUM> are similarly configured as the gate line cut structures <NUM>; a common source layer <NUM> is similarly configured as the common source layer <NUM>; ACS contact structures <NUM> are similarly configured as the ACS contact structures <NUM>; word line connection structures <NUM> are similarly configured as the word line connection structures <NUM>. The description of these components has been provided above and will be omitted here for clarity purposes.

In the <FIG> example, the array die and the CMOS die are disposed face-to-face (circuitry side is face, and the substrate side is back) and bonded together. Generally, the periphery circuitry on the CMOS die interfaces the semiconductor device <NUM> with external circuitry. For example, the periphery circuitry receives instructions from the external circuitry, provides control signals on the array die, receives data from the array die, and outputs data to the external circuitry.

In the <FIG> example, the CMOS die and the array die respectively include bonding structures that can be aligned with each other. For example the CMOS die includes bonding structures I1-I7 and the array die includes corresponding bonding structures <NUM>-<NUM>. The array die and the CMOS die can be suitably aligned, thus the bonding structures I1-I7 are respectively aligned with the bonding structures <NUM>-<NUM>. When the array die and the CMOS die are bonded together, the bonding structures I1-I7 are respectively bonded and electrically coupled with the bonding structures <NUM>-<NUM>.

Further, in the <FIG> example, pad-out structures P1-P3 for the semiconductor device <NUM> are formed on the back side of the array die and the pad-out structures P1-P3 are electrically connected to the bonding structures <NUM>-<NUM>, for example by punch through via structures T1-T3 as shown in <FIG>.

Further, in the <FIG> example, pad-out structures P1-P2 for the semiconductor device <NUM> are formed on the back side of the CMOS die. In the <FIG> example, the input/output signals do not need to route through the array die, thus the signal paths for the input/output signals of the semiconductor device <NUM> can be shorter than the signals paths in <FIG>.

<FIG> shows a flow chat outlining a process example for fabricating a semiconductor device, such as the semiconductor device <NUM> and according to some embodiments of the disclosure. <FIG> show cross-sectional views of a semiconductor device, such as the semiconductor device <NUM>, the semiconductor device <NUM>, during fabrication. It is noted that the cross-sectional views are labeled in the context of the semiconductor device <NUM> and the semiconductor device <NUM> as an example, the cross-sectional views can be suitably labeled in the context of other suitable semiconductor device, such as the semiconductor device <NUM> and the like.

At S810, a stack of initial layers is formed on a substrate. The stack of initial layers includes a source sacrificial layer, a high conductive layer, insulating layers and gate sacrificial layers.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the source sacrificial layer, and the high conductive layer are formed on the substrate <NUM>.

In the <FIG> example, a polysilicon well <NUM> is formed on the substrate <NUM> and then a source sacrificial layer <NUM> and a high conductive layer <NUM> are sequentially deposited. In some examples, the source sacrificial layer <NUM> is a stack of suitable sacrificial layers. In an example, the source sacrificial layer <NUM> includes, for example, a silicon oxide layer, a silicon nitride layer, a polysilicon layer, a silicon nitride layer and a silicon oxide layer from bottom up. The polysilicon layer is sandwiched between two silicon nitride layers and then two silicon oxide layers.

In some examples, the high conductive layer <NUM> is formed by a titanium layer that is later brought in contact with polysilicon layer (e.g., source layer) to form titanium silicide under a relatively high temperature (e.g., above <NUM>° C).

Referring back to <FIG>, at S820, a staircase is formed in a staircase region that is adjacent to an array region.

At S830, channel structures are formed in the array region.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the channel structures are formed.

In the <FIG> example, an initial stack of layer <NUM>(I) is deposited on the high conductive layer <NUM>. The initial stack of layers <NUM>(I) includes sacrificial gate layers <NUM>(I) and insulating layers <NUM> that are stacked alternatingly. Several regions are defined on the substrate, such as the core region <NUM>, the stair region <NUM> and a border region <NUM>.

In the <FIG> example, steps <NUM> are formed in the staircase region. Any suitable process can be used to form the steps. In some examples, an etch-trim process is used. In an example, a mask layer is formed that covers the array region <NUM> and a portion of the staircase region <NUM> adjacent to the array region <NUM>. The mask layer can include a photoresist or carbon-based polymer material, and can be formed using a patterning process such as lithography. In some embodiments, the mask layer can also include a hard mask, such as silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, or polycrystalline silicon. The hard mask can be patterned using etching process such as reactive-ion-etching (RIE) using O2 or CF4 chemistry.

In some embodiments, the steps <NUM> can be formed by applying a repetitive etch-trim process using the mask layer. The etch-trim process includes an etching process and a trimming process. During the etching process, a portion of the initial stack with exposed surface can be removed. In an example, the etch depth equals to a layer pair that is the thickness of a sacrificial gate layer and an insulating layer. In an example, the etching process for the insulating layer can have a high selectivity over the sacrificial layer, and/or vice versa.

In some embodiments, the etching of the stack is performed by an anisotropic etching such as a reactive ion etch (RIE) or other dry etch processes. In some embodiments, the insulating layer is silicon oxide. In this example, the etching of silicon oxide can include RIE using fluorine based gases such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, or C3F6 and/or any other suitable gases. In some embodiments, the silicon oxide layer can be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed-etch approach can be used. In some embodiments, the sacrificial layer is silicon nitride. In this example, the etching of silicon nitride can include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and/or combinations thereof. The methods and etchants to remove a single layer stack should not be limited by the embodiments of the present disclosure.

The trimming process includes applying a suitable etching process (e.g., an isotropic dry etch or a wet etch) on the mask layer such that the mask layer can be pulled back (e.g., shrink inwardly) laterally in the x-y plane from edges. In some embodiments, the trimming process can include dry etching, such as RIE using O2, Ar, N2, etc..

After trimming the mask layer, one portion of the topmost level of the initial stack is exposed and the other potion of the topmost level of the initial stack remains covered by the mask layer. The next cycle of etch-trim process resumes with the etching process.

Further, channel structures <NUM> are formed in the array region <NUM>. In some embodiments, after the steps <NUM> are formed in the staircase region <NUM>, suitable planarization process is performed to obtain a relatively flat surface. Then, photo lithography technology is used to define patterns of channel holes and dummy channel holes (not shown) in photoresist and/or hard mask layers, and etch technology is used to transfer the patterns into the stack of initial layers <NUM>(I), the high conductive layer <NUM>, the source sacrificial layer <NUM> and into the polysilicon well <NUM>. Thus, channel holes can be formed in the core region <NUM> and the staircase region <NUM> (channels holes in the staircase region are not shown).

Then, channel structures <NUM> are formed in the channel holes. In some embodiments, dummy channel structures can be formed with the channel structures, thus the dummy channel structures are formed of the same materials as the channel structures. In an example, the blocking insulating layer is formed on the sidewall of channel holes and the dummy channel holes. Then, a charge storage layer, a tunneling insulating layer, a semiconductor layer, and an insulating layer are sequentially stacked from the sidewall.

Referring back to <FIG>, at S840, gate line cut trenches are formed. In some embodiments, the gate line cut trenches are etched to a source sacrificial layer. In some embodiments, the high conductive layer <NUM> is used as an etch stop layer for the etch process to form the gate line cut trenches.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after a gate line cut trench <NUM> is formed.

Referring back to <FIG>, at S850, the source sacrificial layer is replaced with a source layer using through the gate line cut trench.

In an example, a spacer structure is formed on the sidewall of the gate line cut structures that can protect the gate sacrificial layers during the replacement of the source sacrificial layer.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after spacer layers <NUM> are deposited on the sidewall of the gate line cut trench <NUM>. In some examples, the spacer layers <NUM> include a nitride layer, an oxide layer and another nitride layer.

Then, in an example, a spacer etch process is performed to remove excess spacer materials at the bottom of the gate line cut trench <NUM>. The spacer etch process can also remove the spacer material at the upper surface of the semiconductor device <NUM>.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the spacer etch process. The spacer materials at the bottom of the gate line cut trench <NUM> are removed as shown by <NUM>, and the spacer layers <NUM> remain on the sidewall of the gate line cut trench <NUM>. It is noted that the spacer materials at the upper surface of the semiconductor device <NUM> are also removed by the spacer etch process. In some example, the spacer etch process is an anisotropic etching process.

Further, the source sacrificial layers are removed through the gate line cut trenches. The removal of the source sacrificial layers forms an opening.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the removal of the source sacrificial layers. As shown, an opening <NUM> is formed in the place of the source sacrificial layers and the bottom potion of the channel structure <NUM> is exposed to the opening <NUM>.

In some embodiments, the channel structure <NUM> includes the blocking insulating layer, the charge storage layer, the tunneling insulating layer that have oxide-nitride-oxide (ONO) structure surrounding the semiconductor layer. Then, subsequently, an ONO removal process is performed to expose the bottom portion of the semiconductor layer in the channel structure <NUM> to the opening <NUM>.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the ONO removal process. As shown by <NUM>, the blocking insulating layer, the charge storage layer, the tunneling insulating layer at the bottom the of channel structure <NUM> have been removed, and thus the bottom portion of the semiconductor layer in the channel structure <NUM> is exposed to the opening <NUM>. It is noted that a portion of the spacer may be removed during the ONO removal process.

Subsequently, polysilicon is deposited in the opening <NUM> via the gate line cut trench <NUM>. In some embodiments, a sidewall selective epitaxial growth is performed to grow epitaxial layer and fill the opening <NUM> with source material <NUM>, such as doped or un-doped silicon, doped or un-doped polysilicon, doped or un-doped amorphous silicon and the like.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the polysilicon deposition in some embodiments. The source material <NUM> is then in contact with the semiconductor layer (for forming channel of the memory cells and select transistors) at the bottom of the channel structure <NUM>. The source material <NUM> is in conductive connection (in direct contact) with the high conductive layer <NUM>. In an example, the high conductive layer <NUM> includes titanium that is in contact with the silicon and can form titanium silicide. The high conductive layer <NUM> and the source material <NUM> then form common source layer <NUM>.

Referring back to <FIG>, at S860, the sacrificial gate layers are replaced with gate layers through the gate line cut trench. In some embodiments, using the gate line cut trench <NUM>, the gate sacrificial layers <NUM>(I) can be replaced by the gate layers <NUM>. In an example, etchants to the gate sacrificial layers are applied via the gate line cut trenches to remove the gate sacrificial layers. In an example, the gate sacrificial layers are made of silicon nitride, and the hot sulfuric acid (H<NUM>SO<NUM>) is applied via the gate line cut trenches to remove the gate sacrificial layers.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the gate sacrificial layers <NUM>(I) are removed. The removal of the gate sacrificial layers <NUM>(I) leave openings <NUM>(O).

Further, via the gate line cut trenches, gate stacks <NUM> to the transistors in the array region are formed. In an example, a gate stack <NUM> is formed of a high-k dielectric layer, a glue layer and a metal layer. The high-k dielectric layer can include any suitable material that provide the relatively large dielectric constant, such as hafnium oxide (HfO<NUM>), hafnium silicon oxide (HfSiO<NUM>), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al<NUM>O<NUM>), lanthanum oxide (La<NUM>O<NUM>), tantalum oxide (Ta<NUM>O<NUM>), yttrium oxide (Y<NUM>O<NUM>), zirconium oxide (ZrO<NUM>), strontium titanate oxide (SrTiO<NUM>), zirconium silicon oxide (ZrSiO<NUM>), hafnium zirconium oxide (HfZrO<NUM>), and the like. The glue layer can include refractory metals, such as titanium (Ti), tantalum (Ta) and their nitrides, such as TiN, TaN, W2N, TiSiN, TaSiN, and the like. The metal layer includes a metal having high conductivity, such as tungsten (W), copper (Cu) and the like.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> when the gate stacks <NUM> are filled into the openings.

It is noted that the deposition process of the gate stack <NUM> may deposit excess material, such as the high-k dielectric layer, the glue layer (e.g., TiN) and the metal layer (e.g.. tungsten) on the upper surface of the semiconductor device <NUM> and the bottom of the gate line cut trench <NUM>. In the <FIG> example, the glue layer (e.g., TiN) and the metal layer (e.g., tungsten) on the upper surface of the semiconductor device <NUM> and the bottom of the gate line cut trench <NUM> are removed for example by anisotropic etch process. The high-K dielectric layer on the upper surface of the semiconductor device <NUM> and the bottom of the gate line cut trench <NUM> can be further removed, for example, using an anisotropic etch process.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the high-K dielectric layer on the upper surface of the semiconductor device <NUM> and the bottom of the gate line cut trench <NUM> is removed.

Referring back to <FIG>, at S870, the gate line cut trench is filled. In some embodiments, the gate line cut trench is filled with a bottom conductive layer and an upper insulating portion to form the gate line cut structure. The bottom conductive layer is in conductive connection with the high conductive layer <NUM>.

In an example, after the high-K dielectric layer on the bottom of the gate line cut trench <NUM> is removed, the source layer <NUM> is exposed. Then, a metal layer, such as titanium, can be deposited.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the deposition of the metal layer (e.g., titanium). The titanium is deposited on the bottom of the gate line cut trench <NUM> and the upper surface of the semiconductor device <NUM>. The titanium deposited on the upper surface of the semiconductor device <NUM> can be selectively removed.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the removal of the excess titanium on the upper surface of the semiconductor device <NUM>. In an example, the titanium deposited on the bottom surface of gate line cut trench <NUM> can react with the polysilicon of the source layer <NUM> to form titanium silicide <NUM>. The titanium silicide <NUM> is in conductive connection with the high conductive layer <NUM> in some examples.

Further, insulating material, such as silicon oxide can be deposited to fill the gate line cut trench <NUM>.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the gate line cut trench <NUM> is filled with insulating material, as shown by <NUM>.

Referring back to <FIG>, at S880, contact structures to the common source layer are formed in staircase region. In some embodiments, the contact structures to the common source layer are formed with the contact structures to other portions of the vertical memory cell strings, such as the contact structures to the gate layers, and the like. In some examples, a same mask that includes patterns for the contact structures to the common source layer <NUM>, and patterns for other contacts structures, such as the contact structures to the gate layers, and the like. The mask is used to form contact holes for the contact structures. Etch process can be used to form the contact holes. The high conductive layer <NUM> can be used as an etch stop layer for forming the contact holes to the common source layer <NUM>.

At S890, the fabrication process continues to, for example, back end of line (BEOL) processes. The back end of line processes are used to form various connection structures, such via structures, metal wires, punch through via structure, and the like.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> after the BEOL processes according to some embodiments of the disclosure. Various connection structures are formed on the semiconductor device <NUM>, such as the contact structure <NUM> to the common source layer <NUM>, the contact structures <NUM> to the gate layers, the via structures <NUM> and <NUM>, the wires <NUM> and <NUM>, bonding structures B, punch through via structures T, and the like. In some examples, a semiconductor die with memory array formed on a substrate of the semiconductor die is referred to as an array die.

In some embodiments, the semiconductor device <NUM> is the array die that can be coupled with a CMOS die. Additional processes, such as a bonding process, a thinning process, a contact pad process, and the like can be used to electrically couple the array die and the CMOS die.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> with the array die (e.g., semiconductor device <NUM>) bonded with a CMOS die. In an example, the array die and the CMOS die are disposed face to face with corresponding bonding structures aligned, then the bonded together.

In some examples, the contact pads are from the back side of the array die.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> according to some embodiments of the disclosure. The back side of the array wafer is thinned for example using chemical mechanical polishing process.

<FIG> shows a cross-sectional view of the semiconductor device <NUM> with contact pads P1-P3 formed on the back side of the array die.

It is noted that <FIG> show process examples to form contact pads on the back side of the array die, similar processes can be used to form contact pads on the back side of the CMOS die.

Claim 1:
A semiconductor device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
a stack of layers (<NUM>, <NUM>, <NUM>) comprising a common source layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), gate layers (<NUM>) and insulating layers (<NUM>) disposed on a substrate (<NUM>, <NUM>, <NUM>), the gate layers (<NUM>) and insulating layers <NUM>) being stacked alternatingly;
an array of channel structures (<NUM>, <NUM>, <NUM>) formed in an array region (<NUM>), each channel structure (<NUM>, <NUM>, <NUM>) extending through the stack of layers (<NUM>, <NUM>, <NUM>) forming a stack of transistors in a series configuration, each the channel structure (<NUM>, <NUM>, <NUM>) comprising a channel layer that is conductively connected with the common source layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), the common source layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) extending over the array region and a staircase region (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>);
a contact structure (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) disposed in the staircase region (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), the contact structure (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) forming a conductive connection with the common source layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), wherein the common source layer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprises a source layer (<NUM>) and a high conductive layer (<NUM>), wherein the high conductive layer (<NUM>) is disposed between the source layer (<NUM>) and the bottom most insulating layer (<NUM>), wherein the high conductive layer (<NUM>) comprises at least one of metal, metal compound or metal silicide, wherein the source layer (<NUM>) comprises a silicon layer;
a gate line cut structure (<NUM>, <NUM>, <NUM>) with a bottom high conductive layer (<NUM>) in conductive connection and in direct contact with the high conductive layer (<NUM>), wherein the bottom high conductive layer (<NUM>) comprises a different material than the high conductive layer (<NUM>), wherein the gate line cut structure (<NUM>, <NUM>, <NUM>) comprises an upper insulating portion that is above the bottom high conductive layer (<NUM>); and
vertical memory cell strings (<NUM>, <NUM>) formed as arrays in the respective channel structures (<NUM>, <NUM>, <NUM>) in the array region (<NUM>) (<NUM>), wherein the high conductive layer extends in the array region (<NUM>) and forms an array common source, ACS.