Patent Description:
An image sensor capturing an image and converting the image into an electrical signal has been used in consumer electronic devices such as a digital camera, a mobile phone camera and a portable camcorder, and also in cameras mounted on automobiles, security devices, and robots. Since there has been demand for miniaturization and high resolution of such an image sensor, various studies have been conducted to meet the demand therefor.

The document <CIT> represents such study.

Some example embodiments of the present inventive concepts provide an image sensor in which dark current properties may be addressed and which may have improved optical property efficiency and improved sensitivity. The image sensor according to the invention is defined by the claims. The method of manufacturing the said image sensor hereinafter is not part of the invention.

According to some example embodiments of the present inventive concepts, an image sensor may include a first chip structure including a first substrate and first circuit devices on the first substrate; and a second chip structure on the first chip structure. The second chip structure may include a second substrate having a first surface facing the first chip structure and a second surface opposing the first surface; second circuit devices on the first surface of the second substrate; anti-reflective layers on the second surface of the second substrate; color filters on the anti-reflective layers; microlenses on the color filters; an isolation structure in the second substrate; and photoelectric conversion device regions spaced apart from each other by the isolation structure in the second substrate. The isolation structure may have first regions adjacent to side surfaces of the photoelectric conversion device regions and second regions adjacent to each corner of the photoelectric conversion device regions. The isolation structure may include first isolation layers surrounding the photoelectric conversion device regions, respectively, second isolation layers surrounding the first isolation layers, first gap-fill patterns filling at least a portion of a space between the second isolation layers in the first regions, and second gap-fill patterns filling at least a portion of a space between the second isolation layers in the second regions, in a plan view, and wherein the second gap-fill patterns directly contact with the first gap-fill patterns, in the plan view.

The above and other aspects, features, and advantages of the present inventive concepts will be more clearly understood from the following detailed description, taken in combination with the accompanying drawings, in which:.

Hereinafter, some example embodiments of the present inventive concepts will be described as follows with reference to the accompanying drawings.

It will be understood that elements and/or properties thereof (e.g., structures, surfaces, directions, or the like), which may be referred to as being "perpendicular," "parallel," "coplanar," or the like with regard to other elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) may be "perpendicular," "parallel," "coplanar," or the like or may be "substantially perpendicular," "substantially parallel," "substantially coplanar," respectively, with regard to the other elements and/or properties thereof.

Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are "substantially perpendicular" with regard to other elements and/or properties thereof will be understood to be "perpendicular" with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from "perpendicular," or the like with regard to the other elements and/or properties thereof that is equal to or less than <NUM>% (e.g., a. tolerance of ±<NUM>%).

Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are "substantially parallel" with regard to other elements and/or properties thereof will be understood to be "parallel" with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from "parallel," or the like with regard to the other elements and/or properties thereof that is equal to or less than <NUM>% (e.g., a. tolerance of ±<NUM>%).

Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are "substantially coplanar" with regard to other elements and/or properties thereof will be understood to be "coplanar" with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from "coplanar," or the like with regard to the other elements and/or properties thereof that is equal to or less than <NUM>% (e.g., a. tolerance of ±<NUM>%).

It will be understood that elements and/or properties thereof may be recited herein as being "the same" or "equal" as other elements, and it will be further understood that elements and/or properties thereof recited herein as being "identical" to, "the same" as, or "equal" to other elements may be "identical" to, "the same" as, or "equal" to or "substantially identical" to, "substantially the same" as or "substantially equal" to the other elements and/or properties thereof. Elements and/or properties thereof that are "substantially identical" to, "substantially the same" as or "substantially equal" to other elements and/or properties thereof will be understood to include elements and/or properties thereof that are identical to, the same as, or equal to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances. Elements and/or properties thereof that are identical or substantially identical to and/or the same or substantially the same as other elements and/or properties thereof may be structurally the same or substantially the same, functionally the same or substantially the same, and/or compositionally the same or substantially the same.

It will be understood that elements and/or properties thereof described herein as being "substantially" the same and/or identical encompasses elements and/or properties thereof that have a relative difference in magnitude that is equal to or less than <NUM>%. Further, regardless of whether elements and/or properties thereof are modified as "substantially," it will be understood that these elements and/or properties thereof should be construed as including a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated elements and/or properties thereof.

While the term "same," "equal" or "identical" may be used in description of some example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±<NUM>%).

When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical value. Moreover, when the words "about" and "substantially" are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as "about" or "substantially," it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as increments of <NUM>%.

As described herein, when an operation is described to be performed "by" performing additional operations, it will be understood that the operation may be performed "based on" the additional operations, which may include performing said additional operations alone or in combination with other further additional operations.

Elements that are described herein to be in "contact" with one or more other elements or with each other may be interchangeably referred to as being in "direct contact" with the one or more other elements or with each other. Elements that are described herein to be spaced apart from each other may be interchangeably referred to as being "isolated from direct contact with each other.

<FIG> is a diagram illustrating an image sensor, an enlarged diagram illustrating a portion of an image sensor, according to some example embodiments.

<FIG> is an enlarged diagram illustrating a region of an image sensor including an isolation structure, illustrating region "A" of the image sensor in <FIG>, according to some example embodiments.

<FIG> and <FIG> are cross-sectional diagrams illustrating an image sensor according to some example embodiments. <FIG> is a cross-sectional diagram illustrating an image sensor taken along line I-I' in <FIG>. <FIG> is a cross-sectional diagram illustrating an image sensor taken along line II-II' in <FIG>.

<FIG> is an enlarged diagram illustrating a region of an image sensor including an isolation structure according to some example embodiments. <FIG> illustrates region "B1" in <FIG> and region "B2" in <FIG>.

Referring to <FIG>, an image sensor <NUM> in some example embodiments may include a first chip structure <NUM> and a second chip structure <NUM>. The second chip structure <NUM> may be disposed on the first chip structure <NUM>. The first chip structure <NUM> may be configured as a logic chip, and the second chip structure <NUM> may be configured as an image sensor chip including a plurality of pixel regions PX. In some example embodiments, the first chip structure <NUM> may be configured as a stack chip structure including a logic chip and a memory chip.

The first chip structure <NUM> may include a first substrate <NUM>, a first device isolation layer <NUM> defining an active region on the first substrate <NUM>, a first circuit device <NUM> on the first substrate <NUM>, and a first wiring structure <NUM> and a first insulating layer <NUM> on the first circuit device <NUM>.

The first substrate <NUM> may include a semiconductor material, such as, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first circuit device <NUM> may include a device such as a transistor including a gate <NUM> and a source/drain <NUM>. The first insulating layer <NUM> may cover the first circuit device <NUM> and the first wiring structure <NUM> on the first substrate <NUM>, and may include a plurality of insulating layers. For example, the first insulating layer <NUM> may be configured as multiple layers including at least two of a silicon oxide layer, a low dielectric layer, or a silicon nitride layer.

The second chip structure <NUM> may include a second substrate <NUM> having a first surface 201S1 and a second surface 201S2 opposing each other, a second device isolation layer <NUM> disposed on the first surface 201S1 of the second substrate <NUM> and defining an active region, a second circuit device <NUM>, a second wiring structure <NUM>, and a second insulating layer <NUM> disposed between the first surface 201S1 of the second substrate <NUM> and the first chip structure <NUM>, photoelectric conversion device regions PD in the second substrate <NUM>, an isolation structure IS penetrating the second substrate <NUM> and surrounding the photoelectric conversion device regions PD, an insulating structure <NUM> disposed on the second surface 201S2 of the second substrate <NUM>, color filters <NUM> on the insulating structure <NUM>, and microlenses <NUM> on the color filters <NUM>.

The second substrate <NUM> may include a semiconductor material, such as, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the second substrate <NUM> may be configured as a single crystal silicon substrate.

The second device isolation layer <NUM> may be formed by, for example, a shallow trench isolation (STI) process. The second device isolation layer <NUM> may partially extend from the first surface 201S1 of the second substrate <NUM> into the second substrate <NUM>. The second device isolation layer <NUM> may be formed of an insulating material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

The second circuit device <NUM> may include a transfer gate TG, a floating diffusion region FD, and circuit transistors <NUM>. The circuit transistor <NUM> may include a gate <NUM> and a source/drain <NUM>. The transfer gate TG may transfer electric charges from an adjacent photoelectric conversion device region PD to an adjacent floating diffusion region FD. The circuit transistor <NUM> may be configured as at least one of a source follower transistor, a reset transistor, or a select transistor. The transfer gate TG may be configured as a vertical transfer gate including a portion extending from the first surface 201S1 of the second substrate <NUM> into the second substrate <NUM>.

The second wiring structure <NUM> may include multiple wirings disposed in layers on different levels and vias electrically connecting the multiple wirings and electrically connecting the multiple wirings to the second circuit device <NUM>.

The second insulating layer <NUM> may cover the second circuit device <NUM> and the second wiring structure <NUM> below the first surface 201S1 of the second substrate <NUM>, and may include a plurality of insulating layers. For example, the second insulating layer <NUM> may be formed as multiple layers including at least two of a silicon oxide layer, a low dielectric layer, or a silicon nitride layer. The second insulating layer <NUM> may be in contact with and bonded to the first insulating layer <NUM>.

The photoelectric conversion device regions PD may be formed in the second substrate <NUM> and may be spaced apart from each other by the isolation structure IS. The pixel regions PX may be defined as regions including the photoelectric conversion device regions PD. For example, each of the pixel regions PX may include a photoelectric conversion device region PD. The photoelectric conversion device region PD may generate and accumulate electric charges corresponding to incident light. For example, the photoelectric conversion device region PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or any combination thereof.

The isolation structure IS may be disposed to surround the pixel regions PX including each of the photoelectric conversion device regions PD. The isolation structure IS may be disposed in the isolation trench DT penetrating through the second substrate <NUM>. The isolation structure IS may be formed in a direction from the first surface <NUM> <NUM> of the second substrate <NUM> to the second surface 201S2 opposing the first surface 201S1. For example, at least a portion of the isolation structure IS may penetrate the second substrate <NUM>. In another example, the isolation structure IS may be disposed to partially penetrate the second substrate <NUM> rather than completely penetrating the second substrate <NUM>. The isolation structure IS may be connected to a portion of the second device isolation layer <NUM>. For example, the isolation structure IS may penetrate the second device isolation layer <NUM>.

As illustrated in <FIG> and <FIG>, the isolation structure IS may include first regions LR adjacent to side surfaces S of the photoelectric conversion device regions PD and second regions CR adjacent to each corner C of the photoelectric conversion device regions PD. The second regions CR may be intersecting regions of a grid pattern of the isolation structure IS in a plan view, and may include, for example, regions in which patterns extending in the X-direction intersect with patterns extending in the Y-direction.

In a plan view, the isolation structure IS may include first isolation layers <NUM> and second isolation layers <NUM> surrounding the photoelectric conversion device regions PD, respectively. The first isolation layers <NUM> may surround the photoelectric conversion device regions PD, respectively, and the second isolation layers <NUM> may surround the first isolation layers <NUM>, respectively. The first isolation layers <NUM> and the second isolation layers <NUM> may extend from the first regions LR to the second regions CR, and may include a rounded portion surrounding each corner of the photoelectric conversion device regions PD in the second regions CR.

The isolation structure IS may further include first gap-fill patterns <NUM> filling at least a portion of a space between the second isolation layers <NUM> in the first regions LR and second gap-fill patterns <NUM> filling at least a portion of a space between the second isolation layers <NUM> in the second regions CR. The second gap-fill patterns <NUM> directly contact the first gap-fill patterns <NUM>. The second gap-fill patterns <NUM> may be disposed adjacent to each corner of the plurality of photoelectric conversion device regions PD, and may be spaced apart from each other by the first gap-fill patterns <NUM>. The first gap-fill patterns <NUM> may be disposed between adjacent photoelectric conversion device regions PD in a first direction (X-direction or Y-direction) in a plan view, and the second gap-fill patterns <NUM> may be disposed between the photoelectric conversion device regions PD adjacent to each other in a second direction (W1 direction or W2 direction) oblique to the first direction and parallel to the second surface 201S2 of the second substrate <NUM> in a plan view. The first gap-fill patterns <NUM> may have a first minimum width W1 in the first direction (X-direction or Y-direction), the second gap-fill patterns <NUM> may have a second minimum width W2 in the second direction (W1 direction or W2 direction), and the first minimum width W1 may be smaller than the second minimum width W2. For example, the second minimum width W2 may be about <NUM> times to about <NUM> times, or about <NUM> times to about <NUM> times the first minimum width W1. The first gap-fill pattern <NUM> may include a first portion having a first minimum width W1 and a second portion having a width W1e greater than the first minimum width W1, and the second gap-fill pattern <NUM> may include a first portion having a second minimum width W2 and a width W2e greater than the second minimum width W2.

The second gap-fill patterns <NUM> may have a cross shape in a plan view. Side surfaces of the second gap-fill patterns <NUM> in contact with the first gap-fill patterns <NUM> may be curved surfaces, curved toward the first gap-fill patterns <NUM>. Surfaces of a first element that are herein described to be curved "toward" another element may be "convex" surfaces of the first element. The second gap-fill patterns <NUM> may include a concave region CS facing a portion of each corner C of the photoelectric conversion device region PD in a plan view. The concave region CS may be in contact with the second isolation layer <NUM>.

The isolation structure IS may include liner layers <NUM> disposed between the first isolation layers <NUM> and the second isolation layers <NUM> and a capping layer <NUM> covering first gap-fill patterns <NUM> and second gap-fill patterns <NUM> between the first isolation layers <NUM>. The liner layers <NUM> may surround the first isolation layers <NUM> in a plan view, respectively. The liner layers <NUM> may be formed of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first isolation layers <NUM> may extend longer toward the first surface 201S1 of the second substrate <NUM> than the second isolation layers <NUM> and the liner layers <NUM>, and may be in contact with the capping layer <NUM>. The capping layer <NUM> may be formed of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

For example, the second gap-fill patterns <NUM> may include a material different from a material of the first gap-fill patterns <NUM>, and may include the same material as a material of the second isolation layers <NUM>. For example, the first isolation layers <NUM> may include a material different from a material of the second isolation layers <NUM>. The liner layers <NUM> may include a material different from a material of the first isolation layers <NUM> and the second isolation layers <NUM>. The first isolation layer <NUM> may be formed of an insulating material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The second isolation layer <NUM> may include a semiconductor material, such as, for example, polysilicon doped with n-type or p-type impurities or undoped polysilicon. The first gap-fill pattern <NUM> may be formed of an insulating material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The second gap-fill pattern <NUM> may include a semiconductor material, such as, for example, polysilicon doped with n-type or p-type impurities or undoped polysilicon. N-type impurities may include at least one of phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb), and p-type impurities may include at least one of boron (B), indium (In), or gallium (Ga).

Differently from the above example, each of the first and second isolation layers <NUM> and <NUM> and the first and second gap-fill patterns <NUM> and <NUM> forming the isolation structure IS may include a conductive material, such as, for example, at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium (Ti), tungsten (W), aluminum (Al), or copper (Cu).

Each of the first isolation layer <NUM>, the second isolation layer <NUM>, the liner layer <NUM>, the first gap-fill pattern <NUM>, and the second gap-fill pattern <NUM> may be exaggerated in the diagrams to indicate the structure of the isolation structure IS of the image sensor <NUM>, and each component may have a thickness relatively reduced as compared to the illustrated example. The second isolation layer <NUM> may have a thickness greater than that of the first isolation layer <NUM>, but some example embodiments thereof are not limited thereto, and thicknesses of the components included in the isolation structure IS may be the same or different.

In some example embodiments, a negative voltage may be applied to the second gap-fill pattern <NUM>. A negative voltage may be applied to the second isolation layer <NUM> in contact with the second gap-fill pattern <NUM> through the second gap-fill pattern <NUM>. Positive charges generated by the photoelectric conversion device region PD may be removed through the second isolation layer <NUM> surrounding the photoelectric conversion device region PD, thereby potentially reducing the dark current that may be generated in the image sensor <NUM> and which may otherwise degrade quality of images generated based on electrical signals generated by the image sensor <NUM>. Accordingly, dark current properties of the image sensor may improve (e.g., the image sensor <NUM> may be configured to have reduced dark current therein, thereby the image sensor <NUM> may have improved image generating performance due to the reduction of dark current) based on the second gap-fill pattern <NUM> being in contact with the second isolation layer <NUM>.

For example, the second gap-fill pattern <NUM> includes a polysilicon layer, and the polysilicon layer is used as a material layer gap-filling the entire internal space of the isolation trench DT between the second isolation layers <NUM>, a portion of incident light may be absorbed by the polysilicon layer instead of the photoelectric conversion device region PD, such that optical property efficiency may degrade. In some example embodiments, a first gap-fill pattern <NUM> may be formed as a gap-fill material layer in the first regions LR, and a second gap-fill pattern <NUM> may be formed as a gap-fill material layer in the second regions CR. The second gap-fill pattern <NUM> may be locally disposed to be adjacent to a corner of the photoelectric conversion device region PD (e.g., based on the second gap-fill pattern <NUM> filling at least a portion of a space between the second isolation layers in the second region CR where the second region CR is adjacent to a corner of the photoelectric conversion device region PD), such that absorption of a portion of incident light by the polysilicon layer may be reduced, and thus optical property efficiency of the image sensor <NUM> may be improved such that performance of the image sensor <NUM> may be improved due to reduction of such absorption, based on the second gap-fill pattern <NUM> being adjacent to the corner of the photoelectric conversion device region PD.

That is, since the second gap-fill pattern <NUM> in the second region CR is in contact with the second isolation layer <NUM>, an electrical connection path through which a negative voltage may be applied to the second isolation layer <NUM> may be provided, such that dark current properties of the image sensor may be addressed, and by locally or intermittently disposing the second gap-fill pattern <NUM> in the second region CR, the optical property efficiency and sensitivity of the image sensor may improve.

The insulating structure <NUM> may cover the second substrate <NUM> and the isolation structure IS. The insulating structure <NUM> may include an anti-reflective layer configured to allow incident light to travel to the photoelectric conversion device regions PD with high transmittance by adjusting a refractive index. The insulating structure <NUM> may include a plurality of insulating layers stacked in sequence. For example, the insulating structure <NUM> may include a first layer <NUM>, a second layer <NUM>, a third layer <NUM>, and a fourth layer <NUM> stacked in sequence. The first to fourth layers <NUM>, <NUM>, <NUM>, and <NUM> may include at least one of aluminum oxide, hafnium oxide, silicon oxynitride, silicon oxide, or silicon nitride.

The color filters <NUM> may allow light of a specific wavelength to transmit and to reach the photoelectric conversion device regions PD. For example, the color filters <NUM> may be formed of a material in which a pigment including a metal or a metal oxide is mixed with a resin. The color filters <NUM> may include a green filter, a red filter, and a blue filter. In example embodiments, the color filters <NUM> may not be provided, and the image sensor <NUM> may include an organic photoelectric conversion film provided together with the color filters <NUM> or replacing the color filters <NUM>.

The microlenses <NUM> may overlap each of the photoelectric conversion device regions PD in the vertical direction (Z). The microlenses <NUM> may be convex in a direction away from the second substrate <NUM> to condense incident light. The microlenses <NUM> may condense incident light into the photoelectric conversion device regions PD. The microlenses <NUM> may be formed of a transparent photoresist material or a transparent thermosetting resin material. For example, the microlenses <NUM> may be formed of a TMR-based vertical (manufactured by Tokyo Ohka Kogo, Co. ) or an MFR-based resin (manufactured by Japan Synthetic Rubber Corporation), but some example embodiments thereof are not limited thereto.

<FIG> is a plan diagram illustrating an image sensor according to some example embodiments.

<FIG> and <FIG> are cross-sectional diagrams illustrating an image sensor according to some example embodiments. <FIG> illustrates a cross-sectional diagram illustrating the image sensor in <FIG> taken along line III-III', and <FIG> illustrates a cross-sectional diagram illustrating the image sensor in <FIG> taken along line IV-IV'.

Referring to <FIG>, in the second chip structure <NUM> of an image sensor 1000A in some example embodiments, the isolation structure IS may not include the liner layers <NUM>. The second isolation layer <NUM> may surround the first isolation layer <NUM> and may be in direct contact with the first isolation layer <NUM>. Each of the first gap-fill patterns <NUM> and the second gap-fill patterns <NUM> may include a portion in contact with the first isolation layer <NUM>.

<FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are enlarged diagrams illustrating a region of an image sensor including an isolation structure according to some example embodiments. <FIG> are enlarged diagrams illustrating regions corresponding to regions "B1" and "B2" in <FIG>, respectively.

Referring to <FIG>, in an image sensor 1000B, with reference to the first surface 201S1 of the second substrate <NUM>, the lower surface of the first gap-fill pattern <NUM> and the lower surface of the second gap-fill pattern <NUM> may be disposed lower than in some example embodiments, including the example embodiments shown in <FIG>. For example, the lower surface of the first gap-fill pattern <NUM> and the lower surface of the second gap-fill pattern <NUM> may be disposed on a level lower than the level in some example embodiments, including the example embodiments shown in <FIG>. For example, the lower surface of the first gap-fill pattern <NUM> and the lower surface of the second gap-fill pattern <NUM> may be disposed on the same level as a level of the upper surface of the second device isolation layer <NUM> in the second substrate <NUM>. However, some example embodiments thereof are not limited thereto, and the lower surface of the first gap-fill pattern <NUM> and the lower surface of the second gap-fill pattern <NUM> may be disposed on a level higher than a level of the upper surface of the second device isolation layer <NUM> in the second substrate <NUM>. Alternatively, the lower surface of the first gap-fill pattern <NUM> may be disposed on a level different from a level of the lower surface of the second gap-fill pattern <NUM>.

Referring to <FIG>, in an image sensor 1000C, with reference to the first surface 201S1 of the second substrate <NUM>, each of the lower surface of the first gap-fill pattern <NUM> and the lower surface of the second gap-fill pattern <NUM> may have a concave lower surface. The shape of the lower surface of the first gap-fill pattern <NUM> may be formed in the process of etching the first gap-fill pattern <NUM>, and the shape of the lower surface of the second gap-fill pattern <NUM> may be formed in the process of etching the second gap-fill pattern <NUM>, and each shape may be varied in example embodiments.

Referring to <FIG>, in an image sensor 1000D, each of the lower surface of the first gap-fill pattern <NUM> and the lower surface of the second gap-fill pattern <NUM> may have a concave lower surface, and a lower surface of the second gap-fill pattern <NUM> may provide a relatively deep recess with respect to the first surface 201S1 of the second substrate <NUM>. The recess may extend to a region between internal side surfaces of the second isolation layers <NUM> facing each other, and an upper end thereof may be disposed on a level lower than or on the same level as a level of an upper surface of the second gap-fill pattern <NUM>.

Referring to <FIG>, the image sensor 1000E may not include the second device isolation layer <NUM> through which the isolation structure IS penetrates. The isolation structure IS may work as an isolation layer defining an active region between the second circuit devices <NUM>.

Referring to <FIG>, in an image sensor 1000F, a portion 262a of the second gap-fill pattern <NUM> of the isolation structure IS may extend in a direction from the capping layer <NUM> toward an upper end of the first gap-fill pattern <NUM> in the first gap-fill pattern <NUM> in the first regions LR. In the first regions LR, when the first gap-fill material layer <NUM>' (<FIG>) does not completely fill the isolation trench DT such that a seam is formed therein, a recess having a predetermined depth may be formed in the first gap-fill pattern <NUM> in the process (<FIG>) of etching the first gap-fill material layer <NUM>'. A portion 262a of the second gap-fill pattern <NUM> may be formed by filling the recess with the second gap-fill material layer <NUM>' when the second gap-fill material layer <NUM>' (<FIG>) is formed. The portion 262a of the second gap-fill pattern <NUM> in the first regions LR may not be in contact with the second isolation layer <NUM> and may have a shape of which a width decreases toward the second surface <NUM> S2 of the second substrate <NUM>. For example, the portion 262a of the second gap-fill pattern <NUM> may have a pointy shape toward the second surface 201S2 of the second substrate <NUM>.

Referring to <FIG>, in an image sensor <NUM>, similarly to the image sensor in <FIG>, a portion 262a' of the second gap-fill pattern <NUM> of the isolation structure IS may extend in a direction from the capping layer <NUM> toward an upper end of the first gap-fill pattern <NUM> in the first gap-fill pattern <NUM> in the first regions LR, and the portion 262a' of the second gap-fill pattern <NUM> may be in contact with the second isolation layer <NUM>. In some example embodiments, including the example embodiments shown in <FIG>, the etching of the first gap-fill material layer <NUM>' may be performed more excessively in the first regions LR than in some example embodiments, including the example embodiments shown in <FIG>.

Referring to <FIG>, the image sensor <NUM> may include a second chip structure <NUM> including pixel regions PX configured in a Q-cell pattern, and for example, the four photoelectric conversion device regions PD adjacent to each other may share a single microlens <NUM>, and the connection region PD_C connecting the four photoelectric conversion device regions PD adjacent to each other may be disposed in a central region of the four photoelectric conversion device regions PD. Accordingly, a dynamic range of the image sensor 1000F may be improved or optimized. By intermittently disposing the second gap-fill pattern <NUM> in each region adjacent to corners of the four photoelectric conversion device regions PD, optical property efficiency and sensitivity of the image sensor may improve.

<FIG> is a flowchart illustrating processes of a method of manufacturing an image sensor according to some example embodiments.

<FIG> is a diagram illustrating a substrate on which an isolation trench is formed in relation to a method of manufacturing an image sensor according to some example embodiments.

<FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are diagrams illustrating processes of a method of manufacturing an image sensor according to some example embodiments. <FIG> illustrate cross-sectional regions of the substrate taken long lines V-V' and VI-VI' in <FIG>.

<FIG>, <FIG>, <FIG>, and <FIG> are diagrams illustrating processes of a method of manufacturing an image sensor according to some example embodiments.

Referring to <FIG>, <FIG>, and <FIG>, an isolation trench DT having line regions LR and cross regions CR may be formed by etching the second substrate <NUM> (S10), and a first isolation layer <NUM>, a liner layer <NUM>, and a second isolation layer <NUM> may be formed in the isolation trench DT (S20).

A second substrate <NUM> may be prepared, a mask pattern MK may be formed on the first surface 201S1 of the second substrate <NUM>, an etching process may be performed on the second substrate <NUM> using the mask pattern MK, a shallow isolation trench ST may be formed, and a device isolation layer <NUM>' may be formed in the shallow isolation trench ST. The device isolation layer <NUM>' may completely fill the shallow isolation trench ST and may cover the mask pattern MK. The upper surface of the device isolation layer <NUM>' may be formed on a level higher than a level of the first surface 201S1 of the second substrate <NUM>.

Thereafter, a mask (not illustrated) may be formed on the device isolation layer <NUM>', and the isolation trench DT may be formed by anisotropically etching the device isolation layer <NUM>' and the second substrate <NUM>. As illustrated in <FIG>, the isolation trench DT may be formed in the form of a grid pattern. For example, the isolation trench DT may include first line patterns extending in the X-direction and second lines extending in the Y-direction. The isolation trench DT may include line regions LR having a line shape in a plan view and cross regions CR including regions in which the first and second line patterns intersect with each other. By the isolation trench DT, as illustrated in <FIG>, semiconductor patterns 201P arranged in a matrix form in the X- and Y-directions on the second substrate <NUM> and spaced apart from each other by the isolation trench DT may be formed. The first distance d1 between the side surfaces S of the semiconductor patterns 201P in the line regions LR may be less than a second distance d2 between the corners C of the semiconductor patterns 201P in the cross regions CR.

Thereafter, a first isolation layer <NUM> conformally covering an internal side surface and a bottom surface of the isolation trench DT may be formed in the isolation trench DT, a liner layer <NUM> may be formed on the first isolation layer <NUM> in the isolation trench DT, and the second isolation layer <NUM> may be formed on the liner layer <NUM> in the isolation trench DT. In example embodiments, the forming the liner layer <NUM> may not be performed, and in this case, the second isolation layer <NUM> may be formed on the first isolation layer <NUM>. The second isolation layer <NUM> may be formed on the isolation trench DT and may be recessed to a level lower than a level of the lower surface of the shallow isolation trench ST by an etching process. The upper side surface of the second isolation layer <NUM> may be inclined toward an internal wall of the isolation trench DT, but some example embodiments thereof are not limited thereto.

Referring to <FIG> and <FIG>, the first gap-fill material layer <NUM>' filling the isolation trench DT in the line regions LR and partially filling the isolation trench DT in the cross regions CR' may be formed (S30).

The first gap-fill material layer <NUM>' may completely fill the isolation trench DT in the line regions LR and may extend to the isolation trench DT. Since the space between the semiconductor patterns 201P is wider in the cross regions CR than in the line regions LR, the first gap-fill material layer <NUM>' may partially fill the isolation trench DT in the cross regions CR. For example, the first gap-fill material layer <NUM>' may not completely gap-fill the isolation trench DT in the cross regions CR. The first gap-fill material layer <NUM>' may conformally cover the second isolation layer <NUM> and the liner layer <NUM> in the cross regions CR.

Referring to <FIG> and <FIG>, the first gap-fill patterns <NUM> may be formed in the line regions LR by etching the first gap-fill material layer <NUM>', and the second isolation layer <NUM> may be exposed in the cross regions CR (S40).

The first gap-fill material layer <NUM>' may be partially removed from an upper portion in the line regions LR such that an upper end thereof may be formed on a lower level than a level of the first surface 201S1 of the second substrate <NUM>, such as, for example, a level lower than a level of a lower end of the shallow isolation trench ST. The first gap-fill material layer <NUM>' may be etched and may be formed as first gap-fill patterns <NUM> in the line regions LR. A portion of the first gap-fill material layer <NUM>' covering the second isolation layer <NUM> may be removed in the cross regions CR and the second isolation layer <NUM> may be exposed.

Referring to <FIG> and <FIG>, a second gap-fill material layer <NUM>' filling the isolation trench DT in the cross regions CR may be formed (S50).

The second gap-fill material layer <NUM>' may be formed to be in contact with the second isolation layer <NUM> in the cross regions CR and to at least partially fill the isolation trench DT. The second gap-fill material layer <NUM>' may be deposited on the first surface 201S1 of the second substrate <NUM>, and may partially cover the first gap-fill pattern <NUM> in the line regions LR.

Referring to <FIG> and <FIG>, second gap-fill patterns <NUM> may be in the cross regions CR by etching the second gap-fill material layer <NUM>' (S60).

The second gap-fill material layer <NUM>' may be partially removed from an upper portion in the cross regions CR such that an upper end thereof may be disposed on a level lower than the first surface 201S1 of the second substrate <NUM>, that is, for example, on a level lower than a level of a lower end of the shallow isolation trench ST. The second gap-fill material layer <NUM>' may be etched and may be formed as second gap-fill patterns <NUM> in the cross regions CR. The second gap-fill patterns <NUM> may be spaced apart from each other by the first gap-fill patterns <NUM> disposed in the line regions LR and may be locally disposed only in the cross regions CR. The upper ends of the second gap-fill patterns <NUM> may be formed on substantially the same level as a level of the lower end of the shallow isolation trench ST. As the second gap-fill patterns <NUM> are formed, a portion of the second gap-fill material layer <NUM>' covering a portion of the first gap-fill pattern <NUM> in the line regions LR may also be removed.

Referring to <FIG> and <FIG>, the liner layer <NUM> may be partially removed (S70).

The liner layer <NUM> exposed on the first gap-fill patterns <NUM> and the second gap-fill patterns <NUM> may be selectively removed with respect to the first gap-fill patterns <NUM> and the second gap-fill patterns <NUM>. By removing the liner layer <NUM>, the first isolation layer <NUM> on the second substrate <NUM> may be exposed. When the liner layer <NUM> is not formed in process S20, this process may not be performed.

Referring to <FIG> and <FIG>, a capping layer <NUM> may be formed on the first gap-fill patterns <NUM> and the second gap-fill patterns <NUM> (S80).

A capping layer <NUM> covering the first gap-fill patterns <NUM> and the second gap-fill patterns <NUM> and in contact with an internal surface of the first isolation layers <NUM> may be formed. The capping layer <NUM> may fill an upper region of the isolation trench DT. The capping layer <NUM> may be formed by depositing an insulating layer on the second substrate <NUM> and performing a planarization process. When the planarization process is performed, a portion of the device isolation layer <NUM>' on the first surface 201S1 of the second substrate <NUM> may be removed such that the second device isolation layer <NUM> filling the shallow isolation trench ST may be formed. In an example, the mask pattern MK may be removed after the planarization process is performed, thereby reducing or preventing damages to the first surface <NUM> of the second substrate <NUM>.

Thereafter, referring to <FIG> and <FIG>, photoelectric conversion device regions PD may be formed by doping the semiconductor patterns 201P with impurities, and a transfer gate TG, a second circuit device <NUM> including a floating diffusion region FD and circuit transistors <NUM>, a second wiring structure <NUM>, and a second insulating layer <NUM> may be formed on the first surface <NUM> of the second substrate <NUM>. Specifically, the forming the second circuit device <NUM> may include forming the transfer gate TG and the gate <NUM> on the active region defined by the second device isolation layer <NUM>, and forming a floating diffusion region FD and a source/drain <NUM> by doping the active region with impurities. A plurality of layers forming the second insulating layer <NUM> may be formed on the first surface 201S1 of the second substrate <NUM> and the second wiring structure <NUM> may be formed in the second insulating layer <NUM>.

Referring to <FIG> and <FIG>, a first chip structure <NUM> including a first substrate <NUM>, a first device isolation layer <NUM>, a first circuit device <NUM>, a first wiring structure <NUM>, and a first insulating layer <NUM> may be prepared, and the substrate structure in <FIG> and <FIG> may be turned upside down and may be bonded to the first chip structure <NUM>. The first insulating layer <NUM> and the second insulating layer <NUM> may be in direct contact with and bonded to each other.

A vertical thickness of the second substrate <NUM> may be reduced by removing a portion of the second substrate <NUM>. The second substrate <NUM> may include grinding or polishing the second surface 201S2' opposing the first surface 201S1, and anisotropic and isotropic etching the second surface <NUM> S2'. Accordingly, each of the first isolation layer <NUM>, the second isolation layer <NUM>, the liner layer <NUM>, the first gap-fill pattern <NUM>, and the second gap-fill pattern <NUM> may be partially removed and the surfaces thereof may be removed. Accordingly, the isolation structure IS penetrating through the second substrate <NUM> may be formed.

Referring back to <FIG> and <FIG>, an insulating structure <NUM>, color filters <NUM>, and microlenses <NUM> may be formed on the second surface 201S2 of the second substrate <NUM>, thereby forming the second chip structure <NUM>. Accordingly, the image sensor <NUM> including the first chip structure <NUM> and the second chip structure <NUM> on the first chip structure <NUM> may be manufactured.

<FIG> is a flowchart illustrating processes of a method of manufacturing an image sensor according to some example embodiments. <FIG> is a flowchart illustrating another example of a method of etching the first gap-fill material layer <NUM>' to expose the second isolation layer <NUM> in the cross regions CR.

<FIG>, <FIG>, and <FIG> are diagrams illustrating processes of a method of manufacturing an image sensor according to some example embodiments. <FIG> illustrate cross-sectional regions of the substrate in <FIG> taken along line V-V' and VI-VI'.

Referring to <FIG>, exposing the second isolation layer <NUM> in the cross regions CR (S40) may include forming a photoresist pattern PR covering the first gap-fill material layer <NUM>' in the line regions LR and exposing the first gap-fill material layer <NUM>' in the cross regions CR (S41), etching the first gap-fill material layer <NUM>' in the cross regions CR using the photoresist pattern PR as an etch mask (S42), and removing the photoresist pattern PR (S43).

Referring to <FIG>, a photoresist may be formed on the first gap-fill material layer <NUM>', and a photolithography process may be performed such that the photoresist may be opened to expose the first gap-fill material layer <NUM>' in the cross regions CR, thereby forming the photoresist pattern PR.

Thereafter, referring to <FIG>, an etching process may be performed such that the first gap-fill material layer <NUM>' may be removed from the cross regions CR through the open region of the photoresist pattern PR. The first gap-fill material layer <NUM>' may not remain in the isolation trench DT in the cross regions CR. Accordingly, the second isolation layer <NUM> may be exposed.

Thereafter, referring to <FIG>, the photoresist pattern PR may be removed by performing a stripping process and an ashing process. The other processes of the manufacturing the image sensor may be the same as the processes described with reference to <FIG>.

According to at least some of the aforementioned example embodiments, by disposing the first gap-fill patterns in the line regions of the isolation trench and disposing the second gap-fill patterns in the cross regions of the isolation trench, an image sensor having improved optical property efficiency and improved sensitivity and a method of manufacturing the same may be provided.

Claim 1:
An image sensor (<NUM>; 1000A; 1000B; 1000C; 1000D; 1000E; 1000F; <NUM>; <NUM>), comprising:
a first chip structure (<NUM>) including a first substrate (<NUM>) and first circuit devices (<NUM>) on the first substrate (<NUM>); and
a second chip structure (<NUM>) on the first chip structure (<NUM>),
wherein the second chip structure (<NUM>) includes
a second substrate (<NUM>) having a first surface (201S1) facing the first chip structure (<NUM>) and a second surface (201S2) opposing the first surface (201S1),
second circuit devices (<NUM>) on the first surface (201S1) of the second substrate (<NUM>),
anti-reflective layers on the second surface (201S2) of the second substrate (<NUM>),
color filters (<NUM>) on the anti-reflective layers,
microlenses (<NUM>) on the color filters (<NUM>),
an isolation structure (IS) in the second substrate (<NUM>), and
photoelectric conversion device regions (PD) spaced apart from each other by the isolation structure (IS) in the second substrate (<NUM>),
wherein the isolation structure (IS) has first regions (LR) adjacent to side surfaces of the photoelectric conversion device regions (PD) and second regions (CR) adjacent to each corner of the photoelectric conversion device regions (PD),
wherein the isolation structure (IS) includes
first isolation layers (<NUM>) surrounding the photoelectric conversion device regions (PD), respectively,
second isolation layers (<NUM>) surrounding the first isolation layers (<NUM>),
first gap-fill patterns (<NUM>) filling at least a portion of a space between the second isolation layers (<NUM>) in the first regions (LR), and
second gap-fill patterns (<NUM>) filling at least a portion of a space between the second isolation layers (<NUM>) in the second regions (CR), in a plan view, and
wherein the second gap-fill patterns (<NUM>) directly contact the first gap-fill patterns (<NUM>), in the plan view.