Patent Description:
As a means for cooling a sensor element, such as a solid-state imaging element, a hermetically sealed package incorporating a Peltier element is known (see, for example, Patent Literature <NUM>).

Document <CIT> discloses the solid state image sensor comprising a chip in a package. A image sensor is formed in the chip. The package has a package main body, a light receiving glass plate fixed to the package main body, and a buffer member arranged between the package main body and light receiving glass plate. The buffer member is fixed to the light receiving glass plate and to the package main body. The thermal expansion coefficient of the buffer member is substantially equal to that of the light receiving glass plate, so that the light receiving plate is fixed to the package main body even though the temperature of the imaging device changes.

Document <CIT> discloses an optical semiconductor element package including a housing, electric signal input and output wiring boards, and external leads. The housing has a metal frame and a metal bottom plate, for storing optical semiconductor elements. The electric signal input and output wiring boards are arranged in the housing at positions so that the optical semiconductor elements are not existent right above and right below the boards. The external leads are drawn to the outside through the side wall of the metal frame. The wiring boards are connected to the external leads and to the optical semiconductor elements by bonding wires. The input and output of an electric signal between the outside and the optical semiconductor elements are carried out through the bonding wires, the wiring boards and the external leads. Document <CIT> discloses an optical sensor apparatus including a package having a window; a sensor chip having an array of light receiving devices and a pixel electrode connected to the light receiving device, the sensor chip having an incidence surface that faces the window of the package; and a read-out circuit disposed under the sensor chip, the read-out circuit having a read-out electrode electrically connected to the pixel electrode of the sensor chip. The sensor chip and the read-out circuit are housed in the package. In plan view from the sensor chip, the read-out circuit is overlapped with the sensor chip, and the read-out circuit has no portion extending off the sensor chip.

The present disclosure proposes a sensor device capable of improving detection sensitivity.

The problem is solved by the teachings of the independent claim.

According to the present disclosure, there is provided a sensor device. The sensor device includes a Peltier element, a sensor element thermally connected to a cooling surface of the Peltier element, and a window member that faces a light receiving surface of the sensor element and is made of borosilicate glass.

Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. Note that the same portions are denoted by the same reference signs in each of the following embodiments, and a repetitive description thereof will be omitted.

As a means for cooling a sensor element, such as a solid-state imaging element, a hermetically sealed package incorporating a Peltier element is known. In the hermetically sealed package, sapphire glass is used as a window member that allows detected light to be transmitted through the inside.

In the above technology, however, the sapphire glass has a wavelength region where the absorptivity increases, so that incident light is absorbed by the sapphire glass. Thus, there is a problem that detection sensitivity is lowered.

Therefore, it is expected to achieve a technology capable of overcoming the above-described problem and improving the detection sensitivity of a sensor device.

First, a configuration of a sensor element <NUM> according to an embodiment will be described with reference to <FIG>. <FIG> is a diagram illustrating a schematic configuration of the sensor element <NUM> according to the embodiment of the present disclosure.

The sensor element <NUM> in <FIG> includes: a pixel array region <NUM> in which pixels <NUM> are two-dimensionally arranged in a matrix on a semiconductor substrate <NUM> using, for example, single crystal silicon (Si) as a semiconductor; and a peripheral circuit region <NUM> (see <FIG>) in the periphery thereof. The peripheral circuit region <NUM> includes a vertical drive circuit <NUM>, column signal processing circuits <NUM>, a horizontal drive circuit <NUM>, an output circuit <NUM>, a control circuit <NUM>, and the like.

The pixel <NUM> includes: a photoelectric conversion unit made of a semiconductor thin film; and a plurality of pixel transistors. The plurality of pixel transistors include, for example, three MOS transistors of a reset transistor, an amplification transistor, and a selection transistor.

The control circuit <NUM> receives an input clock and data giving an instruction on an operation mode and the like, and outputs data such as internal information of the sensor element <NUM>. That is, the control circuit <NUM> generates a clock signal and a control signal serving as references of operations of the vertical drive circuit <NUM>, the column signal processing circuit <NUM>, the horizontal drive circuit <NUM>, and the like based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock.

Then, the control circuit <NUM> outputs the generated clock signal and control signal to the vertical drive circuit <NUM>, the column signal processing circuit <NUM>, the horizontal drive circuit <NUM>, and the like.

The vertical drive circuit <NUM> includes, for example, a shift register, selects a predetermined pixel driving wiring <NUM>, supplies a pulse for driving the pixel <NUM> to the selected pixel driving wiring <NUM>, and drives the pixels <NUM> in units of rows.

That is, the vertical drive circuit <NUM> selectively scans the pixels <NUM> in the pixel array region <NUM> sequentially in the vertical direction in units of rows. Then, the vertical drive circuit <NUM> supplies a pixel signal based on a signal charge generated according to the amount of received light in the photoelectric conversion unit of each of the pixels <NUM> to the column signal processing circuit <NUM> through a vertical signal line <NUM>.

The column signal processing circuit <NUM> is arranged for each column of the pixels <NUM>, and performs signal processing such as noise removal on signals output from the pixels <NUM> of one row for each column. For example, the column signal processing circuit <NUM> performs signal processing such as correlated double sampling (CDS) and AD conversion to remove fixed pattern noise unique to each pixel.

The horizontal drive circuit <NUM> includes, for example, a shift register, and sequentially outputs horizontal scanning pulses to sequentially select each of the column signal processing circuits <NUM> such that a pixel signal is output from each of the column signal processing circuits <NUM> to a horizontal signal line <NUM>.

The output circuit <NUM> performs signal processing on the signals sequentially supplied from the column signal processing circuits <NUM>, respectively, through the horizontal signal line <NUM>, and outputs the processed signals. For example, the output circuit <NUM> may perform only buffering, or may perform black level adjustment, column variation correction, various types of digital signal processing, and the like. A input/output terminal <NUM> exchanges signals with the outside.

The sensor element <NUM> configured as described above is a CMOS image sensor called a column AD system in which the column signal processing circuit <NUM> that performs CDS processing and AD conversion processing is arranged for each column.

<FIG> is a diagram illustrating a pixel circuit of each pixel of the sensor element <NUM> according to the embodiment of the present disclosure. Each of the pixels <NUM> includes a photoelectric conversion unit <NUM>, a capacitive element <NUM>, a reset transistor <NUM>, an amplification transistor <NUM>, and a selection transistor <NUM>.

The photoelectric conversion unit <NUM> is made of a semiconductor thin film using a compound semiconductor, such as InGaAs, and generates a charge (signal charge) corresponding to the amount of received light. A predetermined bias voltage Va is applied to the photoelectric conversion unit <NUM>.

The capacitive element <NUM> accumulates the charge generated in the photoelectric conversion unit <NUM>. The capacitive element <NUM> can include at least one of, for example, a pn junction capacitor, a MOS capacitor, or a wiring capacitor.

When being turned on by a reset signal RST, the reset transistor <NUM> resets a potential of the capacitive element <NUM> as the charge accumulated in the capacitive element <NUM> is discharged to a source (ground).

The amplification transistor <NUM> outputs a pixel signal according to the accumulated potential of the capacitive element <NUM>. That is, the amplification transistor <NUM> constitutes a source follower circuit with a load MOS (not illustrated) as a constant current source connected via the vertical signal line <NUM>.

As a result, a pixel signal indicating a level corresponding to the charge accumulated in the capacitive element <NUM> is output from the amplification transistor <NUM> to the column signal processing circuit <NUM> (see <FIG>) via the selection transistor <NUM>.

The selection transistor <NUM> is turned on when the pixel <NUM> is selected by a selection signal SEL, and outputs the pixel signal of the pixel <NUM> to the column signal processing circuit <NUM> via the vertical signal line <NUM>. Each of signal lines through which a transfer signal TRX, the selection signal SEL, and the reset signal RST are transmitted corresponds to the pixel driving wiring <NUM> in <FIG>.

<FIG> is a cross-sectional view illustrating a structure of the pixel <NUM> according to the embodiment of the present disclosure. Although details will be described later, the pixels <NUM> in the pixel array region <NUM> are divided into ordinary pixels 102A and charge emitting pixels 102B depending on a difference in control of the reset transistor <NUM> in <FIG>.

Meanwhile, pixel structures of the ordinary pixel 102A and the charge emitting pixel 102B are basically the same, and thus, simply the pixel <NUM> may be described hereinafter. Note that the charge emitting pixels 102B are arranged on the outermost side of the pixel array region <NUM> (see <FIG>).

A readout circuit of the capacitive element <NUM>, the reset transistor <NUM>, the amplification transistor <NUM>, and the selection transistor <NUM> of each of the pixels <NUM> described in <FIG> is formed for each of the pixels <NUM> on the semiconductor substrate <NUM> made of a single crystal material such as single crystal silicon.

Note that <FIG> does not illustrate reference signs of the capacitive element <NUM>, the reset transistor <NUM>, the amplification transistor <NUM>, and the selection transistor <NUM> formed on the semiconductor substrate <NUM>.

On the upper side, which is the light incident side, of the semiconductor substrate <NUM>, an N-type semiconductor thin film <NUM> to be the photoelectric conversion unit <NUM> is formed on the entire surface of the pixel array region <NUM>. The N-type semiconductor thin film <NUM> is made of InGaP, InAlP, InGaAs, InAlAs, or a compound semiconductor having a chalcopyrite structure.

The compound semiconductor having the chalcopyrite structure is a material capable of obtaining a high light absorption coefficient and high sensitivity over a wide wavelength range, and is preferably used as the N-type semiconductor thin film <NUM> for photoelectric conversion.

Such a compound semiconductor having the chalcopyrite structure is configured using elements around group IV elements such as Cu, Al, Ga, In, S, and Se, and examples thereof include CuGaInS mixed crystals, CuAlGaInS mixed crystals, and CuAlGaInSSe mixed crystals, and the like.

In addition, as a material of the N-type semiconductor thin film <NUM>, amorphous silicon, germanium (Ge), a quantum dot photoelectric conversion film, an organic photoelectric conversion film, and the like can also be used in addition to the compound semiconductor described above. Note that it is assumed that a compound semiconductor of InGaAs is used as the N-type semiconductor thin film <NUM> in the present disclosure.

On the lower side, which is the semiconductor substrate <NUM> side, of the N-type semiconductor thin film <NUM>, a high-concentration P-type layer <NUM> constituting a pixel electrode is formed for each of the pixels <NUM>. Further, an N-type layer <NUM> as a pixel separation region, which isolates the respective pixels <NUM>, is formed using a compound semiconductor such as InP, for example, between the high-concentration P-type layers <NUM> formed respectively for the pixels <NUM>. The N-type layer <NUM> has not only the function as the pixel separation region but also as a role of preventing a dark current.

Meanwhile, an N-type layer <NUM> having a higher concentration than the N-type semiconductor thin film <NUM> is also formed on the upper side, which the light incident side, of the N-type semiconductor thin film <NUM> using the compound semiconductor such as InP used for the pixel separation region.

This high-concentration N-type layer <NUM> functions as a barrier layer that prevents reverse flow of a charge generated in the N-type semiconductor thin film <NUM>. As a material of the high-concentration N-type layer <NUM>, for example, a compound semiconductor such as InP, InGaAs, and InAlAs can be used.

An antireflection film <NUM> is formed on the high-concentration N-type layer <NUM> as the barrier layer. As a material of the antireflection film <NUM>, for example, silicon nitride (SiN), hafnium oxide (HfO<NUM>), aluminum oxide (Al<NUM>O<NUM>), zirconium oxide (ZrO<NUM>), tantalum oxide (Ta<NUM>O<NUM>), titanium oxide (TiO<NUM>), or the like can be used.

Either the high-concentration N-type layer <NUM> or the antireflection film <NUM> also functions as an upper electrode on the upper side among electrodes vertically sandwiching the N-type semiconductor thin film <NUM>, and a predetermined voltage Va is applied to the high-concentration N-type layer <NUM> or the antireflection film <NUM> as the upper electrode.

A color filter <NUM> and an on-chip lens <NUM> are further formed on the antireflection film <NUM>. The color filter <NUM> is a filter that transmits light (wavelength light) of any of red (R), green (G), and blue (B), and is arranged in a so-called Bayer array in the pixel array region <NUM>, for example.

A passivation layer <NUM> and an insulating layer <NUM> are formed on the lower side of the high-concentration P-type layer <NUM> constituting the pixel electrode and the N-type layer <NUM> as the pixel separation region. Further, connection electrodes 153A and 153B and a bump electrode <NUM> are formed so as to penetrate the passivation layer <NUM> and the insulating layer <NUM>.

The connection electrodes 153A and 153B and the bump electrode <NUM> electrically connect the high-concentration P-type layer <NUM> constituting the pixel electrode and the capacitive element <NUM> accumulating the charge.

The ordinary pixel 102A and the charge emitting pixel 102B are configured as described above, and have the same pixel structure. However, a method of controlling the reset transistor <NUM> is different between the ordinary pixel 102A and the charge emitting pixel 102B.

In the ordinary pixel 102A, the reset transistor <NUM> is turned on/off based on the reset signal RST according to a charge generation period (light reception period) by the photoelectric conversion unit <NUM>, a reset period of the potential of the capacitive element <NUM> before the start of light reception, and the like. On the other hand, the reset transistor <NUM> is always controlled to be turned on in the charge emitting pixel 102B.

As a result, the charge generated in the photoelectric conversion unit <NUM> is discharged to the ground, and a constant voltage Va is always applied to the charge emitting pixel 102B.

<FIG> is a plan view of the pixel array region <NUM> illustrating a pixel arrangement of the charge emitting pixel 102B. The pixel array region <NUM> is arranged inside the peripheral circuit region <NUM> in which the vertical drive circuit <NUM>, the column signal processing circuit <NUM>, and the like are formed. The outermost one row and one column of the pixel array region <NUM> are set as charge emission regions <NUM> in which the charge emitting pixels 102B are arranged.

Note that the charge emission region <NUM> may include a plurality of rows and a plurality of columns including at least the outermost one row and one column of the pixel array region <NUM> having a rectangular shape.

In the pixels <NUM> located in the outermost column and row on each side of the rectangular pixel array region <NUM>, a dark current is likely to be generated by the influence from a processed portion interface (processed portion end surface) of the photoelectric conversion unit <NUM> that is the compound semiconductor as illustrated in <FIG>.

In particular, in a case where the readout circuit formed on the semiconductor substrate <NUM> is a circuit of a source follower type, a potential difference of a pixel decreases as the charge is accumulated, and thus, a dark current component affects the adjacent pixel one after another due to blooming.

Therefore, in the embodiment, the pixels <NUM> located in the outermost column and row on each side of the rectangular pixel array region <NUM> are set as the charge emitting pixels 102B controlled such that the reset transistor <NUM> is always turned on.

As a result, gush-out of the charge from the end surface of the processed portion (processed portion interface) of the N-type semiconductor thin film <NUM>, which is the photoelectric conversion unit <NUM>, is concentrated on and discharged to the charge emitting pixel 102B. As a result, it is possible to prevent the charge from flowing into the ordinary pixels 102A on the inner side in the charge emission region <NUM>.

As described above, it is possible to suppress image quality deterioration due to the gush-out of the charge from the processed portion interface of the N-type semiconductor thin film <NUM> according to the embodiment.

<FIG> is a view illustrating a schematic cross-sectional configuration of the sensor element <NUM> according to the embodiment of the present disclosure. The sensor element <NUM> is applied to, for example, an infrared sensor using a compound semiconductor material such as a III-V group semiconductor.

The sensor element <NUM> has a photoelectric conversion function with respect to light having a wavelength in a visible region (for example, <NUM> or more and less than <NUM>) to a short infrared region (for example, <NUM> or more and less than <NUM>), for example. The sensor element <NUM> is provided with, for example, a plurality of light receiving unit regions (the pixels <NUM>) arranged two-dimensionally. <FIG> illustrates a cross-sectional configuration of a portion corresponding to the three pixels <NUM>.

The sensor element <NUM> has a stacked structure of an element substrate <NUM> and a circuit board <NUM>. One surface of the element substrate <NUM> is a light incident surface (light incident surface S1), and a surface (the other surface) opposite to the light incident surface S1 is a junction surface (junction surface S2) with the circuit board <NUM>.

The element substrate <NUM> includes a wiring layer 180W including a first electrode <NUM>, a semiconductor layer <NUM>, a second electrode <NUM>, and a passivation film <NUM> in this order from a position closer to the circuit board <NUM>.

The semiconductor layer <NUM> has a surface facing the wiring layer 180W and an end surface (side surface) which are covered with an insulating film <NUM>. The circuit board <NUM> includes a wiring layer 192W in contact with the junction surface S2 of the element substrate <NUM>, and a support substrate <NUM> facing the element substrate <NUM> with the wiring layer 192W interposed therebetween.

An element region R1, which is an effective pixel region, is provided in a central portion of the element substrate <NUM>, and the semiconductor layer <NUM> is arranged in the element region R1. In other words, a region where the semiconductor layer <NUM> is provided is the element region R1.

A peripheral region R2 surrounding the element region R1 is provided outside the element region R1. In the peripheral region R2 of the element substrate <NUM>, a buried layer <NUM> is provided together with the insulating film <NUM>. In the sensor element <NUM>, light is incident on the semiconductor layer <NUM> from the light incident surface S1 of the element substrate <NUM> via the passivation film <NUM>, the second electrode <NUM>, and a second contact layer <NUM>.

A signal charge photoelectrically converted by the semiconductor layer <NUM> moves through the wiring layer 180W and is read out by the circuit board <NUM>. Hereinafter, a configuration of each portion will be described.

The wiring layer 180W is provided over the element region R1 and the peripheral region R2, and has the junction surface S2 with the circuit board <NUM>. In the sensor element <NUM>, the junction surface S2 of the element substrate <NUM> is provided in the element region R1 and the peripheral region R2. For example, the junction surface S2 in the element region R1 and the junction surface S2 in the peripheral region R2 constitute the same plane.

In the sensor element <NUM>, the junction surface S2 of the peripheral region R2 is formed by providing the buried layer <NUM> as will be described later.

The wiring layer 180W includes, for example, the first electrode <NUM> and contact electrodes 189EA and 189EB in interlayer insulating films 189A and 189B. For example, the interlayer insulating film 189B is arranged on the circuit board <NUM> side, the interlayer insulating film 189A is arranged on a first contact layer <NUM> side, and these interlayer insulating films 189A and 189B are stacked.

The interlayer insulating films 189A and 189B are made of, for example, an inorganic insulating material. Examples of the inorganic insulating material include silicon nitride, aluminum oxide, silicon oxide (SiO<NUM>), and hafnium oxide, and the like. The interlayer insulating films 189A and 189B may be made of the same inorganic insulating material.

The first electrode <NUM> is an electrode (anode) supplied with a voltage for reading out a signal charge (a hole or an electron, hereinafter, the description will be given assuming the signal charge as the hole for convenience) generated in a photoelectric conversion layer <NUM>, and is provided in the element region R1 for each of the pixels <NUM>.

The first electrode <NUM> provided in the wiring layer 180W is in contact with the semiconductor layer <NUM> (more specifically, the first contact layer <NUM> to be described later) through the interlayer insulating film 189A and a connection hole of the insulating film <NUM>. The adjacent first electrodes <NUM> are electrically separated by the interlayer insulating film 189B.

The first electrode <NUM> is made of, for example, any single substance of titanium, tungsten, titanium nitride (TiN), platinum, and gold, germanium, palladium, zinc, nickel, and aluminum, or an alloy containing at least one kind of them.

The first electrode <NUM> may be a single film made of such a constituent material or a stacked film obtained by combining two or more kinds. For example, the first electrode <NUM> is made of a stacked film of titanium and tungsten.

The contact electrode 189EA is configured to electrically connect the first electrode <NUM> and the circuit board <NUM>, and is provided for each of the pixels <NUM> in the element region R1. The adjacent contact electrodes 189EA are electrically separated by the interlayer insulating film 189B.

The contact electrode 189EB electrically connects the second electrode <NUM> and a wiring (wiring 192CB to be described later) of the circuit board <NUM>, and is arranged in the peripheral region R2. The contact electrode 189EB is formed in the same process as the contact electrode 189EA, for example. The contact electrodes 189EA and 189EB are configured using, for example, copper (Cu) pads and are exposed to the junction surface S2.

The semiconductor layer <NUM> includes, for example, the first contact layer <NUM>, the photoelectric conversion layer <NUM>, and the second contact layer <NUM> from a position closer to the wiring layer 180W. The first contact layer <NUM>, the photoelectric conversion layer <NUM>, and the second contact layer <NUM> have the same planar shape, and end surfaces thereof are arranged at the same position in a plan view.

The first contact layer <NUM> is provided in common to all the pixels <NUM>, for example, and is arranged between the insulating film <NUM> and the photoelectric conversion layer <NUM>. The first contact layer <NUM> is configured to electrically separate the adjacent pixels <NUM>, and the first contact layer <NUM> is provided with, for example, a plurality of diffusion regions 182A.

When the first contact layer <NUM> is formed using a compound semiconductor material having a band gap larger than a band gap of a compound semiconductor material forming the photoelectric conversion layer <NUM>, a dark current can also be suppressed. The first contact layer <NUM> can be made of, for example, N-type InP.

The diffusion regions 182A provided on the first contact layer <NUM> are arranged apart from each other. The diffusion region 182A is arranged for each of the pixels <NUM>, and the first electrodes <NUM> are connected to the diffusion regions 182A, respectively.

The diffusion region 182A is configured to read out the signal charge generated in the photoelectric conversion layer <NUM> for each of the pixels <NUM>, and contains, for example, a p-type impurity. Examples of the p-type impurity include Zn and the like.

In this manner, a pn junction interface is formed between the diffusion region 182A and the first contact layer <NUM> other than the diffusion region 182A so that the adjacent pixels <NUM> are electrically separated. The diffusion region 182A is provided, for example, in the thickness direction of the first contact layer <NUM>, and is also provided in a part of the photoelectric conversion layer <NUM> in the thickness direction.

The photoelectric conversion layer <NUM> between the first electrode <NUM> and the second electrode <NUM>, more specifically, between the first contact layer <NUM> and the second contact layer <NUM> is provided in common to all the pixels <NUM>, for example.

The photoelectric conversion layer <NUM> absorbs light having a predetermined wavelength to generate the signal charge, and is made of, for example, a compound semiconductor material such as an i-type group III-V semiconductor. Examples of the compound semiconductor material forming the photoelectric conversion layer <NUM> include InGaAs, InAsSb, InAs, InSb, HgCdTe, and the like.

In addition, the photoelectric conversion layer <NUM> may be made of Ge. The photoelectric conversion layer <NUM> enables photoelectric conversion of light having wavelengths from the visible region to the short infrared region.

The second contact layer <NUM> is provided in common to all the pixels <NUM>, for example. The second contact layer <NUM> is provided between the photoelectric conversion layer <NUM> and the second electrode <NUM>, and is in contact with the both.

The second contact layer <NUM> is a region where a charge discharged from the second electrode <NUM> moves, and is made of, for example, a compound semiconductor containing an n-type impurity. The second contact layer <NUM> can be made of, for example, N-type InP.

The second electrode <NUM> is provided on the second contact layer <NUM> (light incident side) in contact with the second contact layer <NUM>, for example, as an electrode common to the respective pixels <NUM>. The second electrode <NUM> is configured to discharge a charge that is not used as a signal charge among charges generated in the photoelectric conversion layer <NUM> (cathode).

For example, when a hole is read out from the first electrode <NUM> as the signal charge, for example, an electron can be discharged through the second electrode <NUM>. The second electrode <NUM> is made of a conductive film capable of transmitting incident light such as an infrared ray. The second electrode <NUM> can be made of, for example, indium tin oxide (ITO), ITiO (In<NUM>O<NUM>-TiO<NUM>), or the like.

The passivation film <NUM> covers the second electrode <NUM> from the light incident surface S1 side. The passivation film <NUM> may have an antireflection function. The passivation film <NUM> can be made of, for example, silicon nitride, aluminum oxide, silicon oxide, tantalum oxide, or the like.

The insulating film <NUM> is provided between the first contact layer <NUM> and the wiring layer 180W, and covers the end surface of the first contact layer <NUM>, the end surface of the photoelectric conversion layer <NUM>, the end surface of the second contact layer <NUM>, and an end surface of the second electrode <NUM>. In addition, the insulating film <NUM> is in contact with the passivation film <NUM> in the peripheral region R2.

The insulating film <NUM> includes, for example, an oxide such as silicon oxide (SiOx) and aluminum oxide. The insulating film <NUM> may be formed using a stacked structure including a plurality of films.

The insulating film <NUM> may be made of, for example, a silicon (Si)-based insulating material such as silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), silicon nitride, and silicon carbide (SiC).

The buried layer <NUM> is configured to fill a step between a temporary substrate (not illustrated) and the semiconductor layer <NUM> in a manufacturing process of the sensor element <NUM>. Since the buried layer <NUM> is formed in the present embodiment, the occurrence of a defect in the manufacturing process caused by the step between the semiconductor layer <NUM> and the temporary substrate is suppressed although details will be described later.

The buried layer <NUM> in the peripheral region R2 is provided between the wiring layer 180W and the passivation film <NUM>, and has the thickness equal to or larger than the thickness of the semiconductor layer <NUM>, for example. Here, the buried layer <NUM> surrounds the semiconductor layer <NUM>, and thus, the region (peripheral region R2) around the semiconductor layer <NUM> is formed.

As a result, the junction surface S2 with the circuit board <NUM> can be provided in the peripheral region R2. The thickness of the buried layer <NUM> may be reduced as long as the junction surface S2 is formed in the peripheral region R2, but it is preferable that the buried layer <NUM> cover the semiconductor layer <NUM> in the thickness direction such that the entire end surface of the semiconductor layer <NUM> is covered with the buried layer <NUM>.

The buried layer <NUM> covers the entire end surface of the semiconductor layer <NUM> with the insulating film <NUM> interposed therebetween, thereby effectively suppressing entry of moisture into the semiconductor layer <NUM>.

A surface of the buried layer <NUM> on the junction surface S2 side is planarized, and the wiring layer 180W is provided on the planarized surface of the buried layer <NUM> in the peripheral region R2. The buried layer <NUM> can be made of, for example, an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, carbon-containing silicon oxide, and silicon carbide.

The buried layer <NUM> is provided with through electrodes 188V. The through electrode 188V is configured to connect the second electrode <NUM> and the wiring (wiring 192CB described later) of the circuit board <NUM>, and is partially provided on the passivation film <NUM>.

One of the through electrodes 188V penetrates the passivation film <NUM> from above the passivation film <NUM> and is connected to the second electrode <NUM>. The other of the through electrodes 188V penetrates the passivation film <NUM>, the insulating film <NUM>, the buried layer <NUM>, and the interlayer insulating film 189A from above the passivation film <NUM> and is connected to the contact electrode 189EB.

The support substrate <NUM> of the circuit board <NUM> is configured to support the wiring layer 192W, and is made of, for example, silicon (Si). The wiring layer 192W includes, for example, contact electrodes 192EA and 192EB, a pixel circuit 192CA, a wiring 192CB, and a pad electrode 192P in an interlayer insulating film 192A.

The interlayer insulating film 192A is made of, for example, an inorganic insulating material. Examples of the inorganic insulating material include silicon nitride, aluminum oxide, silicon oxide, and hafnium oxide, and the like.

The contact electrode 192EA is configured to electrically connect the first electrode <NUM> and the pixel circuit 192CA, and is in contact with the contact electrode 189EA at the junction surface S2 of the element substrate <NUM>. The adjacent contact electrodes 192EA are electrically separated by the interlayer insulating film 192A.

The contact electrode 192EB is configured to electrically connect the second electrode <NUM> and the wiring 192CB of the circuit board <NUM>, and is in contact with the contact electrode 189EB at the junction surface S2 of the element substrate <NUM>. The contact electrode 192EB is formed in the same process as the contact electrode 192EA, for example.

The through electrode 188V may be connected to the wiring 192CB without providing the contact electrodes 189EB and 192EB. The contact electrodes 192EA and 192EB are made of, for example, copper pads, and are exposed to a surface of the circuit board <NUM> facing the element substrate <NUM>.

That is, a Cu-Cu junction, for example, is formed between the contact electrode 189EA and the contact electrode 192EA, and between the contact electrode 189EB and the contact electrode 192EB.

The pixel circuit 192CA is provided for each of the pixels <NUM>, and is connected to the contact electrode 192EA. The pixel circuit 192CA constitutes an ROIC. The wiring 192CB connected to the contact electrode 192EB is connected to, for example, a predetermined potential.

In this manner, one (for example, a hole) of the charge generated in the photoelectric conversion layer <NUM> is read out from the first electrode <NUM> to the pixel circuit 192CA via the contact electrodes 189EA and 192EA.

In addition, the other (for example, an electron) of the charge generated in the photoelectric conversion layer <NUM> is discharged from the second electrode <NUM> to a predetermined potential via the through electrode 188V and the contact electrodes 189EB and 192EB.

The pad electrode 192P is configured for electrical connection with the outside. The sensor element <NUM> is provided with a hole H that penetrates the element substrate <NUM> and reaches the pad electrode 192P, and the electrical connection with the outside is achieved through the hole H. The connection is achieved, for example, by a method such as wire bond or bump.

Next, a configuration of a sensor device <NUM> according to the embodiment will be described. <FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to the embodiment of the present disclosure, and <FIG> is a bottom view illustrating the configuration example of the sensor device <NUM> according to the embodiment of the present disclosure.

The sensor device <NUM> according to the embodiment is a sensor device that has a package structure whose inside is hermetically sealed, and receives light transmitted through a window member <NUM> by the sensor element <NUM> inside. Note that, in the following description, a side on which the window member <NUM> is provided in the sensor device <NUM> is defined as an upper side for convenience to indicate the up-down direction.

As illustrated in <FIG>, the sensor device <NUM> according to the embodiment includes the sensor element <NUM>, a Peltier element <NUM>, a relay substrate <NUM>, a package substrate <NUM>, a plurality of pin terminals <NUM>, the window member <NUM>, and a support member <NUM>. The plurality of pin terminals <NUM> correspond to an example of an external terminal.

The sensor element <NUM> has an effective pixel region <NUM> on a light receiving surface 10a which is a major surface (an upper surface in the drawing). The plurality of pixels <NUM> (see <FIG>) converting received light into electrical signals are formed in the effective pixel region <NUM>.

The sensor element <NUM> according to the embodiment is, for example, a short wave infrared (SWIR) image sensor such as an InGaAs image sensor. That is, the sensor element <NUM> according to the embodiment has the pixel that convers light having a short wave infrared region (for example, light having a wavelength of <NUM> to <NUM>) into the electrical signal.

The Peltier element <NUM> includes a cooling substrate <NUM>, a columnar portion <NUM>, and a heat dissipation substrate <NUM>, and the cooling substrate <NUM>, the columnar portion <NUM>, and the heat dissipation substrate <NUM> are stacked in this order from above.

<FIG> is a top view illustrating a configuration example of the cooling substrate <NUM> of the Peltier element <NUM> according to the embodiment of the present disclosure. As illustrated in <FIG>, a metal layer ML1, which is formed using a copper thin film or the like and has a predetermined pattern, is formed on a surface (lower surface in <FIG>) of the cooling substrate <NUM> facing the columnar portion <NUM>. Note that <FIG> illustrates an arrangement of the metal layer ML1 in a top view in order to facilitate understanding.

<FIG> is a top view illustrating a configuration example of the heat dissipation substrate <NUM> of the Peltier element <NUM> according to the embodiment of the present disclosure. As illustrated in <FIG>, a metal layer ML2, which is formed using a copper thin film or the like and has a predetermined pattern, is formed on a surface (upper surface in <FIG>) of the heat dissipation substrate <NUM> facing the columnar portion <NUM>. In addition, a pair of electrodes <NUM> is provided at a predetermined site of the metal layer ML2 in the heat dissipation substrate <NUM>.

Then, the columnar portion <NUM> is sandwiched between the cooling substrate <NUM> illustrated in <FIG> and the heat dissipation substrate <NUM> illustrated in <FIG>, thereby forming the Peltier element <NUM> as illustrated in <FIG> is a top view illustrating a configuration example of the Peltier element <NUM> according to the embodiment of the present disclosure.

As illustrated in <FIG>, the metal layer ML1 of the cooling substrate <NUM> and the metal layer ML2 of the heat dissipation substrate <NUM> are aligned, and the columnar portion <NUM> is arranged at a site where both the metal layer ML1 and the metal layer ML2 are arranged.

As a result, a unicursal electric circuit, formed of the metal layer ML1, the metal layer ML2, and the columnar portion <NUM>, is formed between one electrode <NUM> and the other electrode <NUM> inside the Peltier element <NUM>.

In addition, the columnar portion <NUM> includes a P-type thermoelectric semiconductor having a columnar shape and an N-type thermoelectric semiconductor having a columnar shape. Each of the P-type thermoelectric semiconductor and the N-type thermoelectric semiconductor has one end connected to the metal layer ML1 and the other end connected to the metal layer ML2. Then, the P-type thermoelectric semiconductor and the N-type thermoelectric semiconductor of the columnar portion <NUM> are alternately connected in series through the metal layer ML1 and the metal layer ML2.

As a result, when a DC current flows from the N-type thermoelectric semiconductor side in the Peltier element <NUM>, the cooling substrate <NUM> absorbs heat from a cooling surface 21a (see <FIG>) to be cooled, and the heat dissipation substrate <NUM> dissipates the heat absorbed by the cooling substrate <NUM> from a heat dissipation surface 23a (see <FIG>).

The cooling surface 21a is a surface of the cooling substrate <NUM> on the opposite side of a surface to which the columnar portion <NUM> is joined (that is, the surface on which the metal layer ML1 is arranged). The heat dissipation surface 23a is a surface of the heat dissipation substrate <NUM> on the opposite side of a surface to which the columnar portion <NUM> is joined (that is, the surface on which the metal layer ML2 is arranged).

The description returns to <FIG>. The relay substrate <NUM> is arranged between the cooling surface 21a of the Peltier element <NUM> and the sensor element <NUM>. For example, the sensor element <NUM> is joined to a front surface <NUM> of the relay substrate <NUM> via an adhesive (not illustrated) or the like, and the cooling surface 21a of the Peltier element <NUM> is joined to a back surface <NUM> of the relay substrate <NUM> via an adhesive (not illustrated) or the like.

As a result, the sensor element <NUM> is thermally connected to the cooling surface 21a of the Peltier element <NUM> via the relay substrate <NUM>.

In addition, the relay substrate <NUM> has a wiring layer (not illustrated) on the surface or inside, and relays the electrical connection between the sensor element <NUM> and the package substrate <NUM> by the wiring layer.

For example, the wiring layer of the relay substrate <NUM> and the sensor element <NUM> are electrically connected by a bonding wire <NUM>. In addition, the wiring layer of the relay substrate <NUM> and a bonding pad (not illustrated) provided in stepped portion 41b of the package substrate <NUM> are electrically connected by a bonding wire <NUM>. As a result, the relay substrate <NUM> can relay the electrical connection between the sensor element <NUM> and the package substrate <NUM>.

The relay substrate <NUM> is, for example, an interposer substrate made of ceramic. Note that the relay substrate <NUM> is not limited to the substrate made of ceramic, and may be a printed board made of resin or the like.

The package substrate <NUM> is made of a ceramic having a high thermal conductivity, such as alumina (Al<NUM>O<NUM>), aluminum nitride (AlN), and silicon nitride (Si<NUM>N<NUM>), and accommodates the sensor element <NUM>, the Peltier element <NUM>, and the relay substrate <NUM>.

The package substrate <NUM> is a multilayer substrate made of ceramic such as alumina, and is, for example, a pin grid array (PGA) substrate. As illustrated in <FIG>, the package substrate <NUM> has a first surface (for example, an upper surface <NUM>) and a second surface (for example, a bottom surface <NUM>) located on the opposite side of the first surface.

In the package substrate <NUM>, a plurality of wirings are provided in multiple layers in the inside located between the upper surface <NUM> and the bottom surface <NUM>. These wirings are connected to a plurality of terminals (for example, the pin terminals <NUM>) provided on the bottom surface <NUM> of the package substrate <NUM>.

For example, the package substrate <NUM> has a substantially rectangular parallelepiped shape, and a recess <NUM> is formed on the upper surface <NUM>. Then, the Peltier element <NUM>, the relay substrate <NUM>, and the sensor element <NUM> are stacked on a bottom surface 41a of the recess <NUM> in this order from below.

In addition, the recess <NUM> is provided with the stepped portion 41b at a location higher than the bottom surface 41a. Then, the bonding pad provided at the stepped portion 41b and the corresponding wiring layer of the relay substrate <NUM> are electrically connected by the bonding wire <NUM>.

Further, the bonding pad provided at the stepped portion 41b is electrically connected to the pin terminal <NUM> provided on the bottom surface <NUM> of the package substrate <NUM> via the wiring layer (not illustrated) formed on the surface of or inside the package substrate <NUM>. That is, the package substrate <NUM> has a function as a relay substrate that relays electrical connection between the relay substrate <NUM> and the pin terminal <NUM>.

Since the bonding pad is formed at the stepped portion 41b in this manner, the distance between the bonding pad and the relay substrate <NUM> can be shortened. As a result, the length of the bonding wire <NUM> can be shortened, so that the wiring resistance between the package substrate <NUM> and the relay substrate <NUM> can be reduced.

Therefore, electrical properties of the sensor device <NUM> can be improved according to the embodiment.

Each of the bottom surface <NUM> and a plurality of side surfaces <NUM> of the package substrate <NUM> is substantially flat. As illustrated in <FIG>, the plurality of pin terminals <NUM> are arranged side by side in a matrix on the bottom surface <NUM> of the package substrate <NUM>, and a bottom heat dissipation area 43a that is flat is provided in a region where the plurality of pin terminals <NUM> are not arranged.

In addition, side heat dissipation areas 44a, which are flat, are provided respectively on the plurality of side surfaces <NUM> of the package substrate <NUM> as illustrated in <FIG>.

The pin terminal <NUM> is made of a conductive material (for example, metal) and has a substantially cylindrical shape. Then, one end of the pin terminal <NUM> is electrically and mechanically connected to the wiring layer exposed from the bottom surface <NUM> of the package substrate <NUM>, and the pin terminal <NUM> extends downward from the bottom surface <NUM>.

In the embodiment, when the plurality of pin terminals <NUM> are electrically connected to an external device (not illustrated), power, a control signal, and the like are input from the external device to the sensor device <NUM>, and an electrical signal from the sensor element <NUM> is output to the external device.

Note that power supply is performed from the external device to the electrode <NUM> of the Peltier element <NUM> through a terminal <NUM> provided on the bottom surface 41a of the recess <NUM> in the package substrate <NUM> and a bonding wire <NUM> connected to the terminal <NUM>.

The window member <NUM> is provided to face the light receiving surface 10a (that is, the effective pixel region <NUM>) of the sensor element <NUM>, and is made of borosilicate glass which is a translucent material. In the sensor device <NUM> according to the embodiment, the light transmitted through the window member <NUM> is received by the effective pixel region <NUM> of the sensor element <NUM>.

The support member <NUM> is arranged between the sensor element <NUM> and the window member <NUM>, and supports the window member <NUM>. The support member <NUM> has an opening <NUM> and a frame <NUM>. The opening <NUM> is formed to face the light receiving surface 10a (that is, the effective pixel region <NUM>) of the sensor element <NUM>, and allows incident light to pass therethrough. The frame <NUM> has a frame shape, is arranged so as to surround the opening <NUM>, and supports the window member <NUM>.

Then, the window member <NUM> is attached to the support member <NUM> so as to cover the opening <NUM>, thereby being supported by the support member <NUM>. The window member <NUM> and the support member <NUM> are joined to each other without a gap using low-melting-point glass or the like.

In addition, the support member <NUM> is joined to the upper surface <NUM> of the package substrate <NUM> so as to cover the recess <NUM> of the package substrate <NUM>. The support member <NUM> and the package substrate <NUM> are joined without a gap using an existing method.

Since the window member <NUM> and the support member <NUM> are joined without a gap, and the support member <NUM> and the package substrate <NUM> are joined without a gap in this manner, the inside of the recess <NUM> of the package substrate <NUM> can be hermetically sealed in the sensor device <NUM>.

Note that, in a case of hermetically sealing the inside of the recess <NUM> of the package substrate <NUM>, it is preferable to perform the hermetical sealing such that the inside of the recess <NUM> is in a low-humidity state. In addition, the support member <NUM> is made of a metal material or a ceramic material.

In the sensor device <NUM> according to the embodiment described above, detection sensitivity of the sensor device <NUM> can be improved by forming the window member <NUM> using the borosilicate glass.

<FIG> is a view illustrating wavelength dependency of transmittance of window members <NUM> according to Example and Reference Example. <FIG> illustrates a transmittance of the window member <NUM> made of borosilicate glass as Example, and illustrates a transmittance of the window member <NUM> made of sapphire glass as Reference Example.

As illustrated in <FIG>, in the window member <NUM> of Reference Example, there is a region where the transmittance decreases in a visible region and a short wave infrared region (for example, the wavelength of <NUM> to <NUM>). On the other hand, in the window member <NUM> of Example, the transmittance shows a stable high value in the entire visible region and short wave infrared region.

Since the window member <NUM> is made of the borosilicate glass whose transmittance shows a stable high value in the entire visible region and short wave infrared region in this manner, it is possible to increase the amount of received light in the sensor element <NUM> in the entire visible region and short wave infrared region.

Therefore, the detection sensitivity of the sensor device <NUM> can be improved according to the embodiment.

In addition, the window member <NUM> is made of borosilicate glass that is crystal-isotropic in the embodiment, so that it is possible to suppress optical properties (for example, transmittance) from being affected by an axial direction of crystal. Therefore, it is possible to achieve the sensor device <NUM> with a small variation in the optical properties according to the embodiment.

In addition, in the embodiment, the window member <NUM> is made of borosilicate glass having a small thermal expansion coefficient and high toughness, so that thermal shock properties of the sensor device <NUM> can be improved.

In addition, in the embodiment, the window member <NUM> is made of borosilicate glass which is relatively easily processed, so that processing cost of the sensor device <NUM> can be reduced.

In addition, in the embodiment, the support member <NUM> that includes the opening <NUM> and the frame <NUM> and supports the window member <NUM> is provided in the sensor device <NUM>. As a result, as compared with a case where the window member <NUM> is directly joined to the upper surface <NUM> of the package substrate <NUM>, the area of the window member <NUM> that is relatively easily broken can be reduced, and thus, it is possible to suppress a defect of the sensor device <NUM> due to a breakage of the window member <NUM>.

Therefore, reliability of the sensor device <NUM> can be improved according to the embodiment.

In addition, in the embodiment, the frame <NUM> may be arranged outside the effective pixel region <NUM> in a plan view, and the area of the opening <NUM> may be larger than the area of the effective pixel region <NUM>. For example, in the embodiment, an opening angle of the opening <NUM> with respect to the effective pixel region <NUM> is preferably <NUM>° or more.

As a result, light from a detection target of the sensor device <NUM> can be guided to the effective pixel region <NUM> without being blocked by the support member <NUM>. Therefore, the detection target can be stably detected according to the embodiment.

In addition, in the embodiment, the window member <NUM> is arranged to cover the opening <NUM>. That is, in the embodiment, the area of the window member <NUM> is preferably larger than the area of the opening <NUM>. As a result, a margin portion between the window member <NUM> and the support member <NUM> can be increased, so that it is possible to suppress generation of a gap between the window member <NUM> and the support member <NUM>.

Therefore, according to the embodiment, it is possible to stably perform the hermetical sealing of the inside of the recess <NUM> of the package substrate <NUM>. Note that the window member <NUM> according to the embodiment is not limited to the case of being arranged so as to cover the opening <NUM>, but the window member <NUM> having a size substantially equal to that of the opening <NUM> may be arranged to be fitted into the opening <NUM>.

In addition, the sensor element <NUM> is thermally connected to the cooling surface 21a of the Peltier element <NUM> in the embodiment. Thus, the sensor element <NUM> can be stably operated even in the case of using the sensor element <NUM> that generates high heat during the operation such as the SWIR image sensor.

In addition, in the embodiment, the cooling surface 21a of the Peltier element <NUM> is preferably larger than the surface opposite to the light receiving surface 10a of the sensor element <NUM> as illustrated in <FIG>. That is, the cooling surface 21a of the Peltier element <NUM> is preferably larger than the sensor element <NUM> in a plan view.

As a result, the entire sensor element <NUM> can be uniformly cooled by the Peltier element <NUM>, so that the sensor element <NUM> can be more stably operated.

Note that the example of <FIG> illustrates the case where the cooling surface 21a of the Peltier element <NUM> is larger than the sensor element <NUM> in a plan view. However, the cooling surface 21a of the Peltier element <NUM> may have a size substantially equal to that of the sensor element <NUM>, or the cooling surface 21a of the Peltier element <NUM> may be smaller than the sensor element <NUM> as illustrated in <FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to a first modification of the embodiment of the present disclosure.

As illustrated in <FIG>, in a plan view, the recess <NUM> can be made small by making the cooling surface 21a of the Peltier element <NUM> smaller than the sensor element <NUM>, so that the sensor device <NUM> can be downsized.

In addition, in the embodiment, it is preferable that the bottom surface 41a of the recess <NUM> in the package substrate <NUM> be thermally connected to the heat dissipation surface 23a of the Peltier element <NUM> in the package substrate <NUM> accommodating the sensor element <NUM> and the Peltier element <NUM>.

As a result, the heat generated in the sensor element <NUM> can be efficiently dissipated to the outside via the Peltier element <NUM> and the package substrate <NUM> in the sensor device <NUM> that hermetically seals the Peltier element <NUM> and the sensor element <NUM>.

In addition, the Peltier element <NUM> and the sensor element <NUM> are hermetically sealed in the low-humidity state in the embodiment, so that it is possible to suppress dew condensation from occurring on the cooling surface 21a when the cooling surface 21a of the Peltier element <NUM> is cooled.

In addition, the package substrate <NUM> is made of ceramic in the embodiment, so that the sensor element <NUM> of the sensor device <NUM> can have multiple pixels. The reason for this will be described hereinafter.

<FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to a second modification of the embodiment of the present disclosure, and illustrates the sensor device <NUM> including a package substrate <NUM> made of metal. As illustrated in <FIG>, the sensor element <NUM>, the Peltier element <NUM>, and the relay substrate <NUM> are accommodated in a recess <NUM> of the package substrate <NUM> made of metal in the sensor device <NUM> of the second modification.

In addition, a plurality of pin terminals <NUM> each having a columnar shape are provided on a bottom surface 91a of the recess <NUM>. Note that an insulating seal member <NUM> is provided between the pin terminals <NUM> and the package substrate <NUM> in order to ensure insulation between the pin terminals <NUM>.

In addition, one end of the pin terminal <NUM> protrudes downward from a bottom surface <NUM> of the package substrate <NUM>, and the other end of the pin terminal <NUM> is electrically connected to the relay substrate <NUM> by the bonding wire <NUM> in the recess <NUM>.

Here, in the example of <FIG>, the package substrate <NUM> is made of a conductive metal material, and thus, it is necessary to ensure the insulation of each of the pin terminals <NUM> with the seal member <NUM>. That is, in the example of <FIG>, a space for providing the seal member <NUM> is required, and thus, it is difficult to shorten the distance between the adjacent pin terminals <NUM>, so that it is difficult to arrange the plurality of pin terminals <NUM> on the package substrate <NUM> at a high density.

On the other hand, in the example of <FIG>, the package substrate <NUM> is made of insulating ceramic, so that it is unnecessary to separately provide a member for securing the insulating property. Therefore, in the example of <FIG>, the distance between the adjacent pin terminals <NUM> can be shortened since the package substrate <NUM> is made of ceramic.

Further, the wiring layer can be three-dimensionally provided inside the package substrate <NUM> in the package substrate <NUM> made of ceramic, and thus, wiring can be individually performed on all the pin terminals <NUM> even when a large number of the pin terminals <NUM> are arranged on the bottom surface <NUM>.

That is, signals output from all the pixels can be sent to the corresponding pin terminals <NUM> even when the sensor element <NUM> has multiple pixels in the embodiment. Therefore, the pixels of the sensor element <NUM> of the sensor device <NUM> can be increased according to the embodiment.

Note that even when the package substrate <NUM> of the sensor device <NUM> is made of metal as illustrated in <FIG>, the detection sensitivity of the sensor device <NUM> can be improved by making the window member <NUM> using borosilicate glass.

In addition, the plurality of pin terminals <NUM> and the Peltier element <NUM> are preferably provided at different positions in a plan view in the embodiment as illustrated in <FIG>. As a result, a heat dissipation device (not illustrated) can be directly attached to a position (that is, immediately below the Peltier element <NUM>) corresponding to the Peltier element <NUM> on the bottom surface <NUM>.

That is, the heat transferred from the heat dissipation surface 23a of the Peltier element <NUM> to the bottom surface <NUM> of the package substrate <NUM> can be dissipated by the heat dissipation device without being hindered by the pin terminal <NUM> in the embodiment. Therefore, the heat dissipation of the sensor device <NUM> can be improved according to the embodiment.

In addition, a bottom heat dissipation area 43a that is wider and flatter than the Peltier element <NUM> is preferably provided at a position corresponding to the Peltier element <NUM> on the bottom surface <NUM> of the package substrate <NUM> in the embodiment as illustrated in <FIG>.

As a result, the heat dissipation device having a larger area than the Peltier element <NUM> can be provided in the bottom heat dissipation area 43a, so that the heat dissipation of the sensor device <NUM> can be further improved.

In addition, the plurality of pin terminals <NUM> may be provided along two sides of the bottom surface <NUM>, which face each other, in the embodiment as illustrated in <FIG>. As a result, the heat dissipation device can be arranged so as to protrude from the package substrate <NUM>, so that the heat dissipation of the sensor device <NUM> can be further improved.

Note that the bottom heat dissipation area 43a is not limited to the case of being wider than the Peltier element <NUM>, and may have a size substantially equal to that of the Peltier element <NUM> as illustrated in <FIG> is a bottom view illustrating a configuration example of the sensor device <NUM> according to a third modification of the embodiment of the present disclosure.

As illustrated in <FIG>, even if the bottom heat dissipation area 43a has a size substantially equal to that of the Peltier element <NUM>, the bottom heat dissipation area 43a is arranged so as to overlap the Peltier element <NUM>, so that the heat from the Peltier element <NUM> can be dissipated without any trouble by the heat dissipation device.

In addition, the plurality of pin terminals <NUM> may also be provided so as to surround the Peltier element <NUM> in a plan view in the embodiment as illustrated in <FIG>. As a result, the multiple pin terminals <NUM> can be provided on the package substrate <NUM>, so that the heat dissipation device can be arranged to protrude from the package substrate <NUM>. Therefore, the pixels of the sensor element <NUM> of the sensor device <NUM> can be further increased according to the example of <FIG>.

In addition, a side heat dissipation area 44a that is flat may be provided on a side surface <NUM> of the package substrate <NUM> in the embodiment as illustrated in <FIG>. As a result, the heat dissipation device (not illustrated) can be provided in the side heat dissipation area 44a, so that the heat dissipation of the sensor device <NUM> can be further improved.

Note that the example in which the bottom heat dissipation area 43a and the side heat dissipation area 44a, which are flat, are provided on the bottom surface <NUM> and the side surface <NUM> of the package substrate <NUM> has been described in the embodiment, but the bottom heat dissipation area 43a and the side heat dissipation area 44a are not limited to the case of being flat.

For example, when irregularities are provided in the bottom heat dissipation area 43a and the side heat dissipation area 44a, it is possible to increase the surface area of the bottom heat dissipation area 43a and the side heat dissipation area 44a, so that it is possible to improve the heat dissipation of the sensor device <NUM> without separately providing the heat dissipation device.

In addition, the relay substrate <NUM> that relays the electrical connection between the package substrate <NUM> and the sensor element <NUM> is preferably provided in the embodiment. As a result, the thickness of the wiring between the package substrate <NUM> and the sensor element <NUM> can be made thicker than the bonding wires <NUM> and <NUM>, so that the wiring resistance between the package substrate <NUM> and the sensor element <NUM> can be reduced.

Therefore, electrical properties of the sensor device <NUM> can be improved according to the embodiment. In addition, it is possible to make the sensor device <NUM> multifunctional by mounting various mounting components (for example, a capacitor, a resistor, and the like) on the relay substrate <NUM> in the embodiment.

In addition, the sensor element <NUM> is preferably an SWIR image sensor in the embodiment. As a result, sensing that utilizes light having a longer wavelength than visible light can be performed by the sensor device <NUM>.

Note that the sensor element <NUM> according to the embodiment is not limited to the SWIR image sensor. For example, the sensor element <NUM> according to the embodiment may be a complementary metal oxide semiconductor (CMOS) image sensor, a charge coupled device (CCD) image sensor, or the like having pixels each of which converts light in a visible region into an electrical signal.

Next, a case where the sensor element according to the embodiment is a CMOS image sensor having pixels each of which converts light in a visible region into an electrical signal will be described with reference to <FIG>.

<FIG> are views illustrating a substrate configuration of a sensor element 10A of another example according to the embodiment of the present disclosure. The sensor element 10A (see <FIG>) is a semiconductor package in which a stacked substrate <NUM> formed by stacking a lower substrate <NUM> and an upper substrate <NUM> is packaged.

The upper substrate <NUM> has a color filter (not illustrated) of red (R), green (G), or blue (B) and an on-chip lens (not illustrated) formed on an upper surface thereof. In addition, the upper substrate <NUM> is connected in a cavity-less structure via a glass protection substrate (not illustrated) configured to protect the on-chip lens and a glass seal resin (not illustrated).

For example, a pixel region <NUM> in which pixel units that perform photoelectric conversion are two-dimensionally arrayed, and a control circuit <NUM> that controls the pixel units are formed on the upper substrate <NUM> as illustrated in <FIG>. In addition, a logic circuit <NUM> such as a signal processing circuit that processes a pixel signal output from the pixel unit is formed on the lower substrate <NUM>.

Alternatively, only the pixel region <NUM> may be formed on the upper substrate <NUM>, and the control circuit <NUM> and the logic circuit <NUM> may be formed on the lower substrate <NUM> as illustrated in <FIG>.

As described above, the logic circuit <NUM> or both the control circuit <NUM> and the logic circuit <NUM> are formed and stacked on the lower substrate <NUM> different from the upper substrate <NUM> of the pixel region <NUM> in the present disclosure. As a result, a size of the sensor element 10A can be reduced as compared with a case where the pixel region <NUM>, the control circuit <NUM>, and the logic circuit <NUM> are arranged in the planar direction on one semiconductor substrate.

Hereinafter, the upper substrate <NUM> on which at least the pixel region <NUM> is formed will be referred to as a pixel sensor substrate, and the lower substrate <NUM> on which at least the logic circuit <NUM> is formed will be referred to as a logic substrate.

<FIG> is a diagram illustrating a circuit configuration example of the stacked substrate <NUM> of the sensor element 10A of the another example according to the embodiment of the present disclosure. The stacked substrate <NUM> includes a pixel array unit <NUM> in which pixels <NUM> are arrayed in a two-dimensional array, a vertical drive circuit <NUM>, column signal processing circuits <NUM>, a horizontal drive circuit <NUM>, an output circuit <NUM>, a control circuit <NUM>, an input/output terminal <NUM>, and the like.

The pixel <NUM> includes a photodiode as a photoelectric conversion element and a plurality of pixel transistors. A circuit configuration example of the pixel <NUM> will be described later with reference to <FIG>.

In addition, the pixel <NUM> can also have a shared pixel structure. Such a pixel sharing structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion (floating diffusion region), and each shared one of other pixel transistors. That is, in the shared pixels, photodiodes and transfer transistors constituting a plurality of unit pixels are configured to share each one of other pixel transistor.

The control circuit <NUM> receives an input clock and data giving an instruction on an operation mode and the like, and outputs data such as internal information of the stacked substrate <NUM>. That is, the control circuit <NUM> generates a clock signal and a control signal serving as references of operations of the vertical drive circuit <NUM>, the column signal processing circuit <NUM>, the horizontal drive circuit <NUM>, and the like based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock.

That is, the vertical drive circuit <NUM> selectively scans the pixels <NUM> in the pixel array unit <NUM> sequentially in the vertical direction in units of rows. Then, the vertical drive circuit <NUM> supplies a pixel signal based on a signal charge generated according to the amount of received light in the photoelectric conversion unit of each of the pixels <NUM> to the column signal processing circuit <NUM> through a vertical signal line <NUM>.

The column signal processing circuit <NUM> is arranged for each column of the pixels <NUM>, and performs signal processing such as noise removal on signals output from the pixels <NUM> of one row for each pixel column. For example, the column signal processing circuit <NUM> performs signal processing such as CDS and AD conversion to remove fixed pattern noise unique to each pixel.

The output circuit <NUM> performs signal processing on the signals sequentially supplied from the column signal processing circuits <NUM>, respectively, through the horizontal signal line <NUM>, and outputs the processed signals. For example, the output circuit <NUM> may perform only buffering, or may perform black level adjustment, column variation correction, various types of digital signal processing, and the like. The input/output terminal <NUM> exchanges signals with the outside.

The stacked substrate <NUM> configured as described above is a CMOS image sensor called a column AD system in which the column signal processing circuit <NUM> that performs CDS processing and AD conversion processing is arranged for each pixel column.

<FIG> is a diagram illustrating an equivalent circuit of the pixel <NUM> of the sensor element 10A of the another example according to the embodiment of the present disclosure. The pixel <NUM> illustrated in <FIG> illustrates a configuration that implements an electronic global shutter function.

The pixel <NUM> includes a photodiode <NUM>, a first transfer transistor <NUM>, a memory unit <NUM>, a second transfer transistor <NUM>, an FD <NUM>, a reset transistor <NUM>, an amplification transistor <NUM>, a selection transistor <NUM>, and a discharge transistor <NUM>. Note that the photodiode <NUM> is an example of the photoelectric conversion element, and the FD <NUM> is the floating diffusion region.

The photodiode <NUM> is a photoelectric conversion unit that generates and accumulates a charge (signal charge) corresponding to the amount of received light. The photodiode <NUM> has an anode terminal being grounded, and a cathode terminal being connected to the memory unit <NUM> via the first transfer transistor <NUM>. In addition, the cathode terminal of the photodiode <NUM> is also connected to the discharge transistor <NUM> configured to discharge an unnecessary charge.

When turned on by the transfer signal TRX, the first transfer transistor <NUM> reads out a charge generated by the photodiode <NUM> and transfers the charge to the memory unit <NUM>. The memory unit <NUM> is a charge holding unit that temporarily holds a charge until the charge is transferred to the FD <NUM>.

When turned on by a transfer signal TRG, the second transfer transistor <NUM> reads out the charge held in the memory unit <NUM> and transfers the charge to the FD <NUM>.

The FD <NUM> is a charge holding unit that holds the charge read out from the memory unit <NUM> in order to read out the charge as a signal. When turned on by the reset signal RST, the reset transistor <NUM> resets a potential of the FD <NUM> as the charge accumulated in the FD <NUM> is discharged to a constant voltage source VDD.

The amplification transistor <NUM> outputs a pixel signal corresponding to the potential of the FD <NUM>. That is, the amplification transistor <NUM> forms a source follower circuit with a load MOS <NUM> as a constant current source.

Then, a pixel signal indicating a level corresponding to the charge accumulated in the FD <NUM> is output from the amplification transistor <NUM> to the column signal processing circuit <NUM> (see <FIG>) via the selection transistor <NUM>. The load MOS <NUM> is arranged, for example, in the column signal processing circuit <NUM>.

The selection transistor <NUM> is turned on when the pixel <NUM> is selected by a selection signal SEL, and outputs the pixel signal of the pixel <NUM> to the column signal processing circuit <NUM> via the vertical signal line <NUM>.

When turned on by a discharge signal OFG, the discharge transistor <NUM> discharges the unnecessary charge accumulated in the photodiode <NUM> to the constant voltage source VDD. The transfer signals TRX and TRG, the reset signal RST, the discharge signal OFG, and the selection signal SEL are supplied from the vertical drive circuit <NUM> via the pixel driving wiring <NUM>.

Next, an operation of the pixel <NUM> will be briefly described. First, before exposure is started, the discharge transistor <NUM> is turned on by supplying the discharge signal OFG at a high level to the discharge transistor <NUM>, a charge accumulated in the photodiode <NUM> is discharged to the constant voltage source VDD, and the photodiodes <NUM> of all the pixels are reset.

After the photodiodes <NUM> are reset, when the discharge transistor <NUM> is turned off by the discharge signal OFG at a low level, the exposure is started in all the pixels of the pixel array unit <NUM>.

When a predetermined exposure time has elapsed, the first transfer transistor <NUM> is turned on by the transfer signal TRX in all the pixels of the pixel array unit <NUM>, and the charge accumulated in the photodiode <NUM> is transferred to the memory unit <NUM>.

After the first transfer transistor <NUM> is turned off, the charges held in the memory units <NUM> of the respective pixels <NUM> are sequentially read out to the column signal processing circuits <NUM> in units of rows. In the read-out operation, the second transfer transistor <NUM> of the pixel <NUM> of the read row is turned on by the transfer signal TRG, and the charge held in the memory unit <NUM> is transferred to the FD <NUM>.

Then, when the selection transistor <NUM> is turned on by the selection signal SEL, a signal indicating a level corresponding to the charge accumulated in the FD <NUM> is output from the amplification transistor <NUM> to the column signal processing circuit <NUM> via the selection transistor <NUM>.

As described above, in the example of <FIG>, it is possible to perform the operation (imaging) of a global shutter system in which the exposure time is set to be the same for all the pixels of the pixel array unit <NUM>, the charges are temporarily held in the memory units <NUM> after the end of the exposure, and the charges are sequentially read out from the memory units <NUM> in units of rows.

Note that the circuit configuration of the pixel <NUM> is not limited to the configuration illustrated in <FIG>, and for example, a circuit configuration that does not include the memory unit <NUM> and performs an operation by a so-called rolling shutter system can also be adopted.

Next, other modifications according to the embodiment will be described with reference to <FIG>. <FIG> is a plan view of a pixel array region <NUM> illustrating a pixel arrangement of a charge emitting pixel according to a fourth modification.

In the fourth modification, an optical black (OPB) region that detects a black level serving as a reference is formed as a part of the pixel array region <NUM>. A pixel structure of the fourth modification is a pixel structure in a case where the OPB region is formed as a part of the pixel array region <NUM>.

In the case where a OPB region <NUM> is formed as a part of the pixel array region <NUM>, the OPB region <NUM> includes a plurality of columns and a plurality of rows that are on the outermost side of each side of the pixel array region <NUM> having a rectangular shape as illustrated in <FIG>. Then, the innermost one row and one column in the OPB region <NUM> are set as the charge emission region <NUM>.

A region inside the OPB region <NUM> of the pixel array region <NUM> is an effective pixel region in which the ordinary pixel 102A (see <FIG>) that outputs a pixel signal corresponding to the amount of received light is arranged.

<FIG> is a cross-sectional view illustrating a structure of the pixel <NUM> according to the fourth modification of the embodiment of the present disclosure. As illustrated in <FIG>, OPB pixels 102C (102Ca and 102Cb) are arranged in the OPB region <NUM>.

The OPB pixel 102C has a light shielding film <NUM> formed on the upper side of the N-type semiconductor thin film <NUM> as the photoelectric conversion unit <NUM>, instead of the color filter <NUM> and the on-chip lens <NUM>. The light shielding film <NUM> is made of, for example, a metal material such as tungsten, aluminum, and gold.

In the OPB region <NUM>, for example, three OPB pixels 102C forming three rows or three columns are arranged side by side. Then, the innermost OPB pixel 102C (close to the center of the pixel array region <NUM>) among them is the OPB pixel 102Cb for charge emission that is controlled such that the reset transistor <NUM> is always turned on similarly to the above-described embodiment.

On the other hand, the two OPB pixels 102C on the outer side in the OPB region <NUM> in which the three OPB pixels 102C forming three rows or three columns are arranged side by side are OPB pixels 102Ca for black level read-out that is subjected to black level read-out control. Other configurations in the fourth modification are similar to those of the above-described embodiment.

For example, when the pixel array region <NUM> of the sensor element <NUM> is irradiated with high-illuminance light, blooming sometimes occurs in the ordinary pixel 102A most adjacent to the OPB region <NUM>. Then, in this case, there is a possibility that the adjacent OPB pixel 102C, that is, the OPB pixel 102C on the innermost side in the OPB region <NUM> is affected.

In addition, there is a possibility that light incident on the ordinary pixel 102A most adjacent to the OPB region <NUM> leaks into the adjacent OPB pixel 102C so that blooming occurs in the adjacent OPB pixel 102C.

Therefore, in the fourth modification, the OPB pixel 102C on the innermost side in the OPB region <NUM> is set as the OPB pixel 102Cb for charge emission that is controlled such that the reset transistor <NUM> is always turned on.

As a result, the occurrence of blooming can be prevented by the OPB pixel 102Cb for charge emission, and the charge can be prevented from flowing into the adjacent OPB pixel 102Ca for black level read-out. Therefore, it is possible to suppress image quality deterioration caused by the occurrence of blooming according to the fourth modification.

In addition, the example in which the external terminal of the sensor device <NUM> is the pin terminal <NUM> has been described in the above-described embodiment, but the external terminal of the sensor device <NUM> is not limited to the pin terminal <NUM>. <FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to a fifth modification of the embodiment of the present disclosure.

As illustrated in <FIG>, the sensor device <NUM> of the fifth modification is different from that of the embodiment in that a connector <NUM> is provided as the external terminal instead of the pin terminal <NUM>. The connector <NUM> is provided at a position different from a position (that is, immediately below the Peltier element <NUM>) corresponding to the Peltier element <NUM> on the bottom surface <NUM>, and is electrically connected to a wiring layer exposed from the bottom surface <NUM> of the package substrate <NUM>.

In the fifth modification, when the connector <NUM> is electrically connected to an external device (not illustrated), power, a control signal, and the like are input from the external device to the sensor device <NUM>, and an electrical signal from the sensor element <NUM> is output to the external device.

In the fifth modification, the external terminal is configured using the connector <NUM>, so that the sensor device <NUM> can be easily attached to the external device (not illustrated). Note that, in the present disclosure, the external terminal of the sensor device <NUM> is not limited to the pin terminal <NUM> and the connector <NUM>, and various external terminals can be adopted.

<FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to a sixth modification of the embodiment of the present disclosure. As illustrated in <FIG>, in the sensor device <NUM> of the sixth modification, a heat dissipation member <NUM> made of metal is provided on at least a part of a surface (the bottom surface 41a in the present disclosure) of the package substrate <NUM> facing the heat dissipation surface 23a of the Peltier element <NUM>.

That is, the heat dissipation member <NUM> is exposed to the bottom surface 41a in the sensor device <NUM> of the sixth modification. Note that an adhesive or the like may be interposed between the heat dissipation surface 23a of the Peltier element <NUM> and the bottom surface 41a in the sensor device <NUM> of the sixth modification.

The heat dissipation member <NUM> is made of, for example, metal having a high thermal conductivity such as copper, aluminum, and tungsten. That is, in the package substrate <NUM> of the sixth modification, at least a part of a heat transfer path from the heat dissipation surface 23a of the Peltier element <NUM> to the bottom heat dissipation area 43a is made of metal having a higher thermal conductivity than ceramic.

As a result, the heat transfer efficiency from the heat dissipation surface 23a of the Peltier element <NUM> to the bottom heat dissipation area 43a can be improved. Therefore, the heat dissipation of the sensor device <NUM> can be improved according to the sixth modification.

In addition, the heat dissipation member <NUM> preferably penetrates between the surface (bottom surface 41a) facing the heat dissipation surface 23a of the Peltier element <NUM> and the bottom surface <NUM> in the package substrate <NUM> in the sixth modification. As a result, the heat resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be reduced, so that the heat dissipation of the sensor device <NUM> can be further improved.

In addition, the heat dissipation member <NUM> is preferably provided on the entire surface of the package substrate <NUM> facing the heat dissipation surface 23a of the Peltier element <NUM> in the sixth modification as illustrated in <FIG>. As a result, the heat resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be further reduced, so that the heat dissipation of the sensor device <NUM> can be further improved.

Note that the heat dissipation member <NUM> is not limited to the case of being provided on the entire surface of the package substrate <NUM> facing the heat dissipation surface 23a of the Peltier element <NUM>. <FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to a seventh modification of the embodiment of the present disclosure.

As illustrated in <FIG>, the package substrate <NUM> may be provided with a plurality of via-shaped heat dissipation members <NUM> penetrating between the surface (bottom surface 41a) facing the heat dissipation surface 23a of the Peltier element <NUM> and the bottom surface <NUM>. Even in this example of <FIG>, the heat resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be reduced, so that the heat dissipation of the sensor device <NUM> can be further improved.

Note that the example in which the heat dissipation member <NUM> is made of the metal material has been described in the sixth modification and the seventh modification, but the heat dissipation member <NUM> is not necessarily limited to the metal material, and may be a material having a higher thermal conductivity than the ceramic forming the package substrate <NUM>. For example, a ceramic material having a high thermal conductivity may be used as the heat dissipation member <NUM>.

In addition, the example in which the heat dissipation member <NUM> is provided so as to be exposed to the surface of the package substrate <NUM> facing the heat dissipation surface 23a of the Peltier element <NUM> has been described in the sixth modification and the seventh modification, but the heat dissipation member <NUM> is not necessarily exposed to such a surface.

For example, the heat dissipation member <NUM> may be arranged so as to be buried immediately below the Peltier element <NUM> in the package substrate <NUM>. That is, the heat dissipation member <NUM> may be arranged so as to overlap the Peltier element <NUM> in a plan view. As a result, the heat resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be reduced, so that the heat dissipation of the sensor device <NUM> can be further improved.

In addition, the heat dissipation member <NUM> may be arranged at a location other the portion than immediately below the Peltier element <NUM>.

<FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to an eighth modification of the embodiment of the present disclosure. As illustrated in <FIG>, the sensor device <NUM> of the eighth modification is different from that of the embodiment in terms of a configuration of the Peltier element <NUM>.

Specifically, the package substrate <NUM> is configured integrally with the heat dissipation substrate <NUM> of the Peltier element <NUM> in the eighth modification. That is, in the eighth modification, the metal layer ML2 illustrated in <FIG> is provided not on the heat dissipation substrate <NUM> but on the bottom surface 41a of the recess <NUM> in the package substrate <NUM>, and the columnar portion <NUM> and the cooling substrate <NUM> are stacked on the metal layer ML2 of the bottom surface 41a to constitute the Peltier element <NUM>.

Since the package substrate <NUM> is configured integrally with the heat dissipation substrate <NUM> of the Peltier element <NUM> in this manner, it is possible to reduce the heat resistance at an interface between the heat dissipation substrate <NUM> and the package substrate <NUM>. In addition, the heat dissipation substrate <NUM> can be omitted in the eighth modification, so that a heat transfer path from the sensor element <NUM> to the bottom heat dissipation area 43a can be shortened.

Therefore, the heat dissipation of the sensor device <NUM> can be improved according to the eighth modification.

<FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to a ninth modification of the embodiment of the present disclosure. As illustrated in <FIG>, the sensor device <NUM> of the ninth modification is different from those of the embodiment and the eighth modification in terms of a configuration of the Peltier element <NUM>.

Specifically, the relay substrate <NUM> is configured integrally with the cooling substrate <NUM> of the Peltier element <NUM> in the ninth modification. That is, in the ninth modification, the metal layer ML1 illustrated in <FIG> is provided not on the cooling substrate <NUM> but on the back surface <NUM> of the relay substrate <NUM>, and the relay substrate <NUM> is further stacked on the stacked heat dissipation substrate <NUM> and columnar portion <NUM> to constitute the Peltier element <NUM>.

Since the relay substrate <NUM> is configured integrally with the cooling substrate <NUM> of the Peltier element <NUM> in this manner, it is possible to reduce the thermal resistance at an interface between the relay substrate <NUM> and the cooling substrate <NUM>. In addition, the cooling substrate <NUM> can be omitted in the ninth modification, so that a heat transfer path from the sensor element <NUM> to the bottom heat dissipation area 43a can be shortened.

Therefore, the heat dissipation of the sensor device <NUM> can be improved according to the ninth modification.

<FIG> is a cross-sectional view illustrating a configuration example of the sensor device <NUM> according to a tenth modification of the embodiment of the present disclosure. As illustrated in <FIG>, the sensor device <NUM> of the tenth modification is different from that of the embodiment in that the relay substrate <NUM> is not provided.

That is, the sensor element <NUM> is directly joined to the cooling surface 21a of the Peltier element <NUM> in the tenth modification. In addition, the electrical connection between the sensor element <NUM> and the package substrate <NUM> is achieved directly by the bonding wire <NUM>.

Since the relay substrate <NUM> can be omitted in the tenth modification, a heat transfer path from the sensor element <NUM> to the bottom heat dissipation area 43a can be shortened. Therefore, the heat dissipation of the sensor device <NUM> can be improved according to the tenth modification.

In addition, the recess <NUM> can be made small by omitting the relay substrate <NUM> in the tenth modification, so that the sensor device <NUM> can be downsized.

The sensor device <NUM> according to the embodiment includes the Peltier element <NUM>, the sensor element <NUM> (10A) thermally connected to the cooling surface 21a of the Peltier element <NUM>, and the window member <NUM> that faces the light receiving surface 10a of the sensor element <NUM> (10A) and is made of borosilicate glass.

As a result, the detection sensitivity of the sensor device <NUM> can be improved.

In addition, the effective pixel region <NUM>, which receives incident light from the window member <NUM>, is arranged on the light receiving surface 10a of the sensor element <NUM> (10A) in the sensor device <NUM> according to the embodiment.

In addition, the sensor device <NUM> according to the embodiment further includes the support member <NUM> arranged between the sensor element <NUM> (10A) and the window member <NUM>. In addition, the support member <NUM> includes the opening <NUM> that allows passage of the incident light, and the frame <NUM> that supports the window member <NUM>.

As a result, the reliability of the sensor device <NUM> can be improved.

In addition, the frame <NUM> is arranged outside the effective pixel region <NUM> in a plan view in the sensor device <NUM> according to the embodiment.

As a result, a detection target can be stably detected.

In addition, the area of the opening <NUM> is larger than the area of the effective pixel region <NUM> in the sensor device <NUM> according to the embodiment.

In addition, the window member <NUM> is arranged to cover the opening <NUM> in the sensor device <NUM> according to the embodiment.

As a result, it is possible to stably perform the hermetical sealing of the inside of the recess <NUM> of the package substrate <NUM>.

In addition, the cooling surface 21a of the Peltier element <NUM> is larger than the surface of the sensor element <NUM> (10A) opposite to the light receiving surface 10a in the sensor device <NUM> according to the embodiment.

As a result, the entire sensor element <NUM> (10A) can be uniformly cooled by the Peltier element <NUM>, so that the sensor element <NUM> (10A) can be more stably operated.

In addition, the sensor device <NUM> according to the embodiment further includes the package substrate <NUM> that is thermally connected to the heat dissipation surface 23a of the Peltier element <NUM> and accommodates the Peltier element <NUM> and the sensor element <NUM> (10A).

As a result, the heat generated in the sensor element <NUM> (10A) can be efficiently dissipated to the outside via the Peltier element <NUM> and the package substrate <NUM> in the sensor device <NUM> that hermetically seals the Peltier element <NUM> and the sensor element <NUM> (10A).

In addition, the sensor device <NUM> according to the embodiment further includes the relay substrate <NUM> that is arranged between the cooling surface 21a of the Peltier element <NUM> and the sensor element <NUM> (10A), and relays the electrical connection between the package substrate <NUM> and the sensor element <NUM> (10A).

Thus, electrical characteristics of the sensor device <NUM> can be improved.

In addition, the sensor element <NUM> is the SWIR image sensor in the sensor device <NUM> according to the embodiment.

As a result, sensing that utilizes light having a longer wavelength than visible light can be performed by the sensor device <NUM>.

Although the above description is given regarding the embodiments of the present disclosure, the technical scope of the present disclosure is not limited to the above-described embodiments as they are within the appended claims.

Claim 1:
A sensor device comprising:
a Peltier element (<NUM>);
a sensor element (<NUM>, 10A) thermally connected to a cooling surface of the Peltier element;
a window member (<NUM>) that faces a light receiving surface of the sensor element and is made of borosilicate glass;
a package substrate (<NUM>) that is thermally connected to a heat dissipation surface of the Peltier element (<NUM>), and accommodates the Peltier element and the sensor element; and
a support member (<NUM>) that is joined with the window member (<NUM>) and the package substrate (<NUM>) without a gap respectively and is made of metal or ceramic,
wherein
an effective pixel region (<NUM>) that receives incident light from the window member (<NUM>) is arranged on the light receiving surface of the sensor element (<NUM>, 10A),
the support member (<NUM>) is arranged between the sensor element (<NUM>, 10A) and the window member (<NUM>),
the support member (<NUM>) has an opening (<NUM>) that allows passage of the incident light and a frame (<NUM>) that supports the window member (<NUM>), and
the window member (<NUM>) is disposed above and overlaps a portion of the frame (<NUM>).