Patent Description:
Many applications require a relatively low average supply current provided by a battery, but periodically require a high peak current. These applications are often duty-cycled, with a relatively long inactive period (e.g., sleep, stand-by or off time). Typically, a battery can easily sustain the average current for a long period of time, but the battery life, or capacity, is degraded significantly when peak currents are required to be supplied.

Traditional solutions to the problem of battery degradation due to pulsed loads include adding a large capacitor in parallel with the battery. However, this large capacitor is costly, can have mechanical reliability issues due to its size, and also can contribute significantly to leakage current thus further reducing the effective battery life. In addition, use of a lower leakage capacitor in parallel with the battery further increases the cost beyond that incurred with a standard capacitor having higher leakage current.

<CIT> discloses an energy storage (ES) circuit including a plurality of terminals configured to connect to a pulse load having an input voltage and drawing a low current during a first interval and a high current during a second interval, and connect to a power supply having a source voltage and delivering a source current, an energy storage capacitor connected to the plurality of terminals, and a bidirectional direct current (DC) to DC converter configured to recharge, during at least a portion of the first interval, the energy storage capacitor using a plurality of charge drawn from the source current, and reduce a drop in the input voltage during the second interval by delivering a difference between the source current and the high current to the pulse load using the plurality of charge stored in the energy storage capacitor.

<CIT> discloses a power converter system for managing power between a power supply and a load, the system including: a first buck-boost circuit connected to the power supply; and a capacitor provided between the buck-boost circuit and the load to buffer power supply for the load. The system may include a second buck-boost circuit between the capacitor and the load. In another embodiment, a power converter system includes: a boost circuit connected to the power supply; a buck circuit connected to the load; and a capacitor provided between the boost circuit and the buck circuit to manage the supply of power to the load.

<CIT> discloses a system which includes a first battery module including a number of rechargeable cells. A first battery module current limiter is configured to monitor a current flowing to or from the plurality of rechargeable cells of the first battery module. The battery module current limiter is further configured to selectively limit the current flowing to a non-zero current that is less than a predetermined current threshold, wherein the selectively limiting is based on whether the monitored current is approaching the predetermined current threshold.

<CIT> discloses a power supply for powering a load, the load being in the form of a flash drive circuit for a digital camera. The power supply includes a supercapacitive device, in the form of a super capacitor, for powering is the circuit. A regulator unit, in the form of an inductive regulator charges the supercapacitor. The power supply includes a boost converter for charging the super capacitor from the battery and a bypass FET in parallel with the inductor of the boost converter. The bypass FET is activated if the battery voltage is greater than or equal to the required voltage.

Embodiments described herein provide for power management of battery-based systems for applications having duty-cycled high peak supply currents. Specifically, current drawn from a battery (e.g., a coin cell battery), is limited to prevent premature degradation of the battery current capacity, while peak loads are supplied from a buffer capacitor. The buffer capacitor includes undesirable limitations with regards to leakage, size and the like, which are minimized with a current limiting circuit while optimizing battery capacity.

<FIG> show the discharge characteristics of a typical Lithium coin cell battery under a continuous and pulsed current load. In <FIG>, a Closed Circuit Voltage (CCV) <NUM> is maintained relatively close to the initial <NUM>. 0V voltage over a significant range of battery capacity (expressed in mA-hours). Specifically, the CCV <NUM> represents a continuous or background current of <NUM>. 19mA at <NUM>. 9V, <NUM> degrees Celsius through <NUM> ohms. A relatively low pulsed current results in a CCV <NUM>, also over the significant range of battery capacity. Specifically, the CCV <NUM> represents a pulsed current of <NUM>. 8mA at <NUM>. 7V, <NUM> degrees Celsius through <NUM> ohms, with a <NUM> second pulse applied <NUM> times per day. An internal resistance <NUM> is also maintained at a relatively low value over the significant range of battery capacity.

In <FIG>, a Closed Circuit Voltage (CCV) <NUM> drops significantly from the initial <NUM>. 0V voltage due to premature battery degradation resulting from the application of a high peak current pulse load. Specifically, the CCV <NUM> represents a continuous or background current close to <NUM> mA at <NUM> degrees Celsius. A relatively high pulsed current results in a CCV <NUM>, with a significant reduction in CCV due to the battery degradation. Specifically, the CCV <NUM> represents a pulsed current of 23mA at <NUM>. 7V, <NUM> degrees Celsius through <NUM> ohms, with a <NUM> millisecond pulse applied every <NUM> milliseconds. An internal resistance <NUM> increases earlier than the internal resistance <NUM> of <FIG> due to the premature battery degradation.

<FIG> shows a power management system for applications having duty-cycled high peak supply currents, in accordance with an example embodiment <NUM> of the present disclosure. Examples of duty-cycled high peak supply current systems include without limitation, an Ultra Wideband (UWB) ranging system, an automotive keyless remote Frequency Operated Button (FOB), Internet of Things devices and applications powered by batteries with minimal capacity. The embodiment <NUM> includes a battery <NUM>, supplying a battery voltage <NUM> referenced to a ground <NUM>. A current limiter <NUM> charges a buffer capacitor <NUM> to the buffer voltage <NUM>. In one embodiment, the buffer capacitor <NUM> supplies a load <NUM>, such as a circuit block having an occasional or periodic requirement for high peak supply currents. In another embodiment, the load <NUM> is both supplied by the buffer capacitor <NUM> and the current limiter <NUM>.

The current limiter <NUM> ensures that the current flowing from the battery <NUM> is maintained substantially at or below a maximum current limit. In one embodiment, the buffer capacitor <NUM> supplies the peak or pulsed current to the load <NUM> that exceeds the battery <NUM> current limited by the current limiter <NUM>. The buffer capacitor <NUM> is dimensioned such that it can deliver the supply current during the time window that the connected load <NUM> is activated, while the voltage at the buffer capacitor <NUM> will not drop below a certain minimum level that is required for proper operation of the connected load <NUM>.

In one embodiment, a voltage regulator <NUM> regulates the buffer voltage <NUM> to a regulated voltage <NUM>. Preferably, the voltage regulator is a resonant or switched regulator based on inductive or capacitive elements, rather than a linear regulator thus minimizing further current drain on the buffer capacitor. In one embodiment, the voltage regulator <NUM> is a boost regulator to allow a bigger voltage drop (e.g., voltage droop) on the buffer capacitor, thereby allowing for a smaller buffer capacitor <NUM> to be used.

The embodiment <NUM> includes control circuits <NUM>, powered by a supply <NUM> and providing a control signal <NUM> to control the current limiter <NUM>. In one embodiment, the supply <NUM> is supplied from the battery <NUM> to guarantee functionality of the control circuits <NUM> with a discharged buffer capacitor <NUM>. In example embodiments, the charging current output by the current limiter <NUM>, the final charge voltage of the buffer voltage <NUM> or regulated voltage <NUM>, and the general timing of functions of the current limiter <NUM> is programmable as a function of various sensor inputs (e.g., battery <NUM> temperature, and/or state-of-charge), to optimize design trade-offs between minimum application costs, maximum battery life, minimum charging or recharging time of the buffer capacitor <NUM> and recovery time of the battery <NUM>. Specifically, in the example embodiment <NUM>, the control circuits <NUM> include a temperature sensor <NUM> to sense a temperature of the battery <NUM>, a current sensor input <NUM> indicating a current delivered by the battery <NUM>, the battery voltage <NUM> and buffer voltage <NUM> input to the control circuit <NUM> to measure voltage drop across the current limiter <NUM>, and a reset and control signal <NUM> for additional external control of the control circuits <NUM>.

In one embodiment of the power management system of <FIG>, the current limit of the current limiter <NUM> is programmable. A programmable current limiter <NUM> is useful for optimizing the power management system for different applications having different battery types or sizes or different peak-current capabilities. Furthermore, the programmable current limiter <NUM> allows for setting the maximum battery <NUM> current as a function of temperature.

In one embodiment of the power management system of <FIG>, the current limiter <NUM> is programmable to an off (or open) state having low leakage between the battery <NUM> and the buffer capacitor <NUM>. During a sleep-mode of the load <NUM>, a programmable off state prevents draining the battery <NUM> due to leakage current of the load and/or buffer capacitor <NUM>. In one embodiment, a leakier, and therefore cheaper buffer capacitor <NUM>, is used by switching the current limiter <NUM> to an off state when the load <NUM> is in a sleep-mode. Consequently, the buffer capacitor <NUM> discharges during the off state of the current limiter <NUM> and thus requires recharging before the load <NUM> is reactivated. In this mode, the battery voltage <NUM> will exceed the buffer voltage <NUM>.

In another embodiment, a low-current load is supplied directly from the battery <NUM> without discharging the buffer capacitor <NUM>, and thus the battery voltage <NUM> is less than the buffer voltage <NUM>. For example, in a Key FOB application, a low-current Low Frequency (LF) and Ultra High Frequency (UHF) integrated circuit (IC) is directly supplied by the battery <NUM>, while a high-current UWB IC is supplied by the buffer capacitor <NUM>. The LF and UHF IC will cause the battery voltage <NUM> to drop because of an output impedance of the battery <NUM>, thus causing a reversal of voltage polarity across the current limiter <NUM>.

In all embodiments of the power management system of <FIG>, the current limiter <NUM> includes a low-power bypass mode. Once the buffer capacitor <NUM> is charged while the load <NUM> is in sleep-mode, the current limiter <NUM> need only supply sufficient current to compensate for leakage of the buffer capacitor <NUM> and any leaky circuits connected thereto. The leakage current associated with the buffer capacitor <NUM> and connected circuits is typically much less than a current limit of the current limiter <NUM> (e.g., 10mA for a typical lithium coin cell battery). In all embodiments, the bias circuits that are required by the current limiter <NUM> for accurate current limiting are disabled, and the current limiter <NUM> is placed in a conductive bypass state. In one embodiment, the series impedance of this conductive bypass state is not critical, as long as sufficient current is supplied to the buffer capacitor <NUM> to minimize voltage drop of the buffer voltage <NUM>. In another embodiment, where the bypass state is also used as a test path under test conditions, with higher peak currents, it is desirable that the bypass state have a lower impedance. The low-power bypass mode is advantageous when the buffer capacitor <NUM> needs to remain charged during the sleep mode of the load <NUM> and to minimize draining the battery <NUM> due to bias currents required in the current limiter <NUM>. In all embodiments, after the load <NUM> enters the sleep mode, when the buffer capacitor is sufficiently charged, the current limiter <NUM> is latched into the bypass mode, and subsequently unlatched prior to reactivating the load <NUM>.

In one embodiment of the power management system of <FIG>, the current limiter <NUM> includes a voltage limiter mode. This mode is useful for maintaining a charge on the buffer capacitor <NUM> with reduced buffer capacitor <NUM> leakage, while the load <NUM> is in the sleep mode. In one embodiment, the voltage limiter mode includes monitoring the buffer voltage <NUM> and charging the buffer capacitor <NUM> to at least a threshold voltage. In one embodiment, the threshold voltage is programmable. Once the buffer voltage <NUM> reaches the threshold voltage, the current limiter <NUM> operates as a voltage limiter by only compensating for the leakage current of the load <NUM> and the buffer capacitor <NUM>. Leakage typically increases with applied voltage, hence the voltage limiter mode will reduce the leakage current of the buffer capacitor <NUM> and load <NUM>, thereby optimizing the effective battery life of the battery <NUM>. In one embodiment, the leakage current reduction exceeds the extra current consumed by the implementation of the voltage limiter mode. Accordingly, the voltage limiter mode is only enabled when the battery voltage <NUM> exceeds a certain threshold and/or temperature. The voltage limiter mode enables usage of cheaper capacitors with higher corresponding leakage.

In one embodiment of the power management system of <FIG>, the current limiter <NUM> includes a buck mode and a boost mode. In one embodiment, the boost mode charges the buffer capacitor <NUM> to a buffer voltage <NUM> exceeding the battery voltage <NUM>. By increasing the buffer voltage <NUM> beyond what is required for the load <NUM>, additional voltage-droop of the buffer voltage <NUM> is permitted when the load <NUM> is activated, thus permitting a smaller buffer capacitor <NUM> size. In one embodiment, the boosted buffer voltage <NUM> is reduced with the voltage regulator <NUM> of <FIG> (e.g., operating as a buck regulator). In another embodiment, the current limiter buck mode charges the buffer capacitor <NUM> when the buffer voltage <NUM> is less than the battery voltage <NUM>. Accordingly, the current limiter power efficiency and output current is maximized. Both the buck mode and the boost mode are beneficial when the buffer capacitor <NUM> is allowed to float by putting the current limiter <NUM> in the off mode, while the load <NUM> is in the sleep mode. The buffer capacitor <NUM> is subsequently recharged prior to the load <NUM> becoming active. In one embodiment, the buck mode and boost mode are implemented in the current limiter <NUM> with a resonant or switched mode converter. In one embodiment, the buck mode and boost mode use the same shared capacitors and/or inductors. In one embodiment, where excessive Radio Frequency Interference (RFI) issues are present, the buck or boost converter is disabled during the active state of the load <NUM>, thus necessitating a larger buffer capacitor <NUM>.

<FIG> shows an example embodiment <NUM> of the current limiter <NUM> of <FIG>. A current mirror is formed with P-type Field Effect Transistors (PFETs) <NUM> and <NUM> with source terminals connected to the battery voltage <NUM> and drain terminals connected between the buffer voltage <NUM> and node <NUM> respectively. A first amplifier <NUM> compares the buffer voltage <NUM> to the node <NUM> to drive a gate of a PFET <NUM> connected between the node <NUM> and a controllable current source <NUM>. The first amplifier <NUM> forces a same voltage between the drains of the PFETs <NUM> and <NUM>, resulting in a well-matched drain current through PFETs <NUM> and <NUM>. A second amplifier <NUM> compares a node <NUM>, joining a drain of the PFET <NUM> to the controllable current source <NUM>, with a reference voltage <NUM> to provide a gate voltage <NUM>. The gate voltage <NUM> forces the drain current of the PFETs <NUM> and <NUM> to be equal to a current sunk by the controllable current source <NUM>.

In another embodiment, the current sunk by the controllable current source <NUM> is reduced (for a given current limit), by increasing the gain or a channel width of the PFET <NUM> relative to a channel width relative to the PFET <NUM>. In one embodiment, the current limiter <NUM> is programmed by changing a sunk current of the controllable current source <NUM>. In another embodiment, the current limiter <NUM> is programmed by changing the relative gain or channel widths of the PFETs <NUM> and <NUM> through mask options, fuse links and the like. In one embodiment of current limiter <NUM> implementing the programmable off state, the gate voltage <NUM> is forced to the battery voltage <NUM> when the battery voltage <NUM> exceeds the buffer voltage <NUM>, or is forced to the buffer voltage <NUM> when the battery voltage <NUM> is less than the buffer voltage <NUM>. In one embodiment of current limiter <NUM> implementing the low-power bypass mode, the gate voltage <NUM> is forced to ground, thereby connecting the battery <NUM> and the buffer capacitor <NUM> through a low impedance. In another embodiment, an additional switch is added between the battery <NUM> and the buffer capacitor <NUM> to bypass the current limiter <NUM>, when the current limiter <NUM> is disabled. Disabling the bias circuits in the current limiter <NUM> minimizes power consumption. For example, bias circuits in the embodiment <NUM> include at least the controllable current source <NUM> and internal bias circuits (not shown) in the first amplifier <NUM> and the second amplifier <NUM>. In one embodiment, a decision to activate the bypass mode is made by monitoring a voltage difference between the battery voltage <NUM> and the buffer voltage <NUM>. In another embodiment, a decision to activate the bypass mode is made by monitoring the saturation of the controllable current source <NUM> as indicated by the gate voltage <NUM> being close to ground <NUM>. Accordingly, this indicates that the PFET <NUM> is out of saturation and that the buffer capacitor <NUM> is charged. Subsequently, the current limiter <NUM> is latched into the bypass state and bias circuits of the current limiter <NUM> are disabled.

<FIG> shows an example embodiment <NUM> of the controllable current source <NUM> of <FIG>. The embodiment controls a current sunk from the node <NUM> to the ground <NUM>. In the embodiment <NUM>, the node <NUM> is monitored with respect to the ground <NUM> for selecting a combination of the switches <NUM>, <NUM> and <NUM> to approximate a desired current source value. Activation of the switches <NUM> and <NUM> connect respective resistors <NUM> and <NUM> in parallel to each other and between the node <NUM> and the ground <NUM>.

The off-mode is realized by disabling all of the switches <NUM>, <NUM> and <NUM>. A low power mode is realized by closing one or more of the switches <NUM>, <NUM> and <NUM> and further disabling all monitoring circuits. It should be appreciated that other embodiments of the controllable current source <NUM> have a different number of switches from what is depicted in the example embodiment <NUM> of <FIG>.

<FIG> shows an example embodiment <NUM> of a power management system for applications having duty-cycled high peak supply currents, including a boost-mode converter <NUM> in series with the current limiter <NUM>. In one example embodiment, the boost-mode converter <NUM> is implemented with a charge pump. In another example embodiment, the boost-mode converter <NUM> is implemented with a capacitive voltage doubler. The boost-mode converter <NUM> is controlled by an oscillator <NUM> through an oscillator output <NUM>. A control circuit <NUM> controls the oscillator with control signal <NUM>. The control circuit <NUM> controls the current limiter <NUM> with a control signal <NUM> and a bypass switch <NUM> across the boost-mode converter <NUM> with a control signal <NUM>. A voltage drop monitor <NUM> measures a voltage drop between the battery voltage <NUM> and a node <NUM>, thereby measuring a voltage drop across the current limiter <NUM>. A voltage monitor <NUM> measures the buffer voltage <NUM> and provides a measured voltage signal <NUM> to the control circuit <NUM>. The voltage drop monitor <NUM> provides a voltage drop signal <NUM> to the control circuit <NUM>. A voltage drop monitor <NUM> measures a voltage difference between the battery voltage <NUM> and the buffer voltage <NUM> and provides a voltage difference signal <NUM> to the control circuit <NUM>.

When the buffer voltage <NUM> is less than the battery voltage <NUM>, as sensed by the voltage drop monitor <NUM>, then only the current limiter <NUM> is used, and the boost-mode converter <NUM> is bypassed by closing the switch <NUM> and disabled. When the voltage difference between the buffer voltage <NUM> and the battery voltage <NUM> is small or the input current to the current limiter <NUM> is half of a programmed current limit of the current limiter <NUM>, then the boost-mode converter <NUM> is enabled and the bypass switch <NUM> opened. In another embodiment, the voltage drop across the current limiter <NUM>, as measured by the voltage drop monitor <NUM>, is used to control the effective switching frequency of the boost-mode converter <NUM> to optimize converter efficiency. In one embodiment, when the buffer voltage <NUM> reaches a programmed voltage threshold, as sensed by the voltage monitor <NUM>, the boost-mode converter <NUM> is disabled or paused.

<FIG> with continued reference to <FIG> shows a charging characteristic of the buffer capacitor <NUM> during a charge phase <NUM>, with subsequent loading of the buffer capacitor <NUM> by the load <NUM> during an active phase <NUM> of the load <NUM> and a recharging phase <NUM> of the buffer capacitor <NUM>. In <FIG>, the buffer capacitor <NUM> starts with no charge and ramps to a voltage <NUM> of <NUM>. 8V while the current limiter <NUM> acts as a current source during a period <NUM>. In one embodiment, at the voltage <NUM>, the input current to the current limiter <NUM> is <NUM>% of a current limit of the current limiter <NUM>. During a period <NUM>, the boost mode converter <NUM> is enabled until the maximum voltage <NUM> of <NUM>. 6V is reached.

When the load is activated during the active phase <NUM>, the buffer voltage <NUM> drops during the period <NUM> down to the voltage <NUM> as it supplies current to the load <NUM>. The amount of reduction in the buffer voltage <NUM> depends in part on the load current and size of the buffer capacitor <NUM>. When the buffer voltage <NUM> drops below the voltage <NUM>, corresponding to the input current to the current limiter <NUM> being <NUM>% of the current limit of the current limiter <NUM>, the boost mode converter <NUM> is disabled again. Consequently, the continued reduction in buffer voltage <NUM> occurs at a slow rate during the period <NUM>. In one embodiment, the current limit is programmed to ensure that the buffer voltage <NUM> does not drop below the voltage <NUM> of <NUM>. 5V, required for proper operation of the load <NUM>. After the load <NUM> reenters the sleep-mode the buffer capacitor <NUM> is recharged during periods <NUM> and <NUM>, with the same operation performed during periods <NUM> and <NUM>. In one embodiment, the boost mode converter <NUM> is disabled during the <NUM> period to reduce RFI issues when the load <NUM> is active.

<FIG> shows an example embodiment <NUM> of a power management system for applications having duty-cycled high peak supply currents, including a reconfigurable boost and buck mode converter <NUM> for charging the buffer capacitor <NUM> and supplying the load <NUM>. A buck converter is used for charging the buffer capacitor <NUM> when the buffer voltage <NUM> is less than the battery voltage <NUM>, and a boost converter is used for charging the buffer capacitor <NUM> when the buffer voltage <NUM> is above the battery voltage <NUM>. A buck converter is used to supply a load <NUM> with a voltage that is lower than the buffer voltage <NUM>, and a boost converter is used to supply the load <NUM> with a voltage higher than the buffer voltage <NUM>, wherein the buck converter and the boost converter share an inductor <NUM>. For example, in the embodiment <NUM>, the boost and buck mode converter <NUM> supplies power to a UWB transceiver <NUM> over a path <NUM>. In the embodiment <NUM>, the boost mode is used for charging the buffer capacitor <NUM> above the battery voltage <NUM>, hence permitting more voltage droop and/or a smaller buffer capacitor <NUM>. Subsequently, the buck mode receives the boosted buffer voltage <NUM> as an input, and provides a voltage to the UWB transceiver <NUM>, which is bucked down from the buffer voltage <NUM>. This buck-charge operation provides for better efficiency and higher charging current to the load <NUM>. In another embodiment, the converter <NUM> bucks the battery voltage <NUM> down to a lower buffer voltage <NUM>, then the converter <NUM> receives and boosts the buffer voltage <NUM> up to a higher load voltage to supply the load <NUM>.

With reference to <FIG> and <FIG>, in another embodiment, during the charge phase <NUM> the converter <NUM> bucks the buffer voltage <NUM> up to the voltage <NUM> (also corresponding to the battery voltage <NUM>) during the period <NUM> and boosts the buffer voltage <NUM> up to the voltage <NUM> during the period <NUM>. During the active or discharge phase <NUM>, the converter <NUM> bucks the buffer voltage <NUM> down to the voltage <NUM> (also corresponding to the battery voltage <NUM>) during the period <NUM> and boosts the buffer voltage <NUM> during the period <NUM>.

<FIG> with reference to <FIG> shows a method <NUM> for power management for applications having duty-cycled high peak supply currents. At <NUM>, a buffer capacitor <NUM> is charged with a current from a battery <NUM>, limited by a current limiter <NUM>. At <NUM>, a load <NUM> is supplied with a pulsed current from the buffer capacitor <NUM>. At <NUM>, the current limiter <NUM> is controlled with sensor inputs <NUM>, <NUM>, <NUM> and <NUM> to limit a degradation of the battery <NUM> including at least one of a capacity and a lifetime of the battery <NUM>.

<FIG> with reference to <FIG> shows a method <NUM> for power management for applications having duty-cycled high peak supply currents. At <NUM>, a current is supplied from a supply source (e.g., a battery <NUM>), which will be damaged when it has to deliver high peak currents. At <NUM>, the current from the supply source is limited with a current limiter <NUM>. At <NUM>, an activated load <NUM> is supplied with a current from the current limiter <NUM> and a peak current from the buffer capacitor <NUM>, wherein the buffer capacitor <NUM> is charged by the current limiter <NUM>. At <NUM>, the current limiter <NUM> is controlled with sensor inputs <NUM>, <NUM>, <NUM> and <NUM> to limit the current from being a high peak current, thereby limiting degradation of the supply source.

As will be appreciated, embodiments as disclosed include at least the following. In one embodiment, a method for power management for applications having duty-cycled high peak supply currents comprises charging a buffer capacitor with a first current supplied by a battery, wherein the first current is limited by a current limiter. A load is supplied with a second current supplied by the buffer capacitor, wherein the second current comprises a pulsed current. The current limiter is controlled with at least one of a plurality of sensor inputs to limit a capacity degradation of the battery. The current limiter must be latched into a conductive bypass mode and a bias circuit of the current limiter is disabled, in response to the load entering a sleep mode and the buffer capacitor being charged above a threshold voltage, wherein the threshold voltage is greater than a minimum voltage.

Alternative embodiments of the method for power management for applications having duty-cycled high peak supply currents further include one of the following features, or any combination thereof. A current limit of the current limiter is determined by a temperature of the battery. The buffer capacitor is disconnected from the load in response to the load entering a sleep mode, and recharging the buffer capacitor prior to reconnected the buffer capacitor to the load in response to the load exiting the sleep mode. The buffer capacitor is charged to a buffer voltage being less than a battery voltage of the battery, by reducing a voltage output of the current limiter with a buck converter, thereby maximizing one or more of an output current of the current limiter and a power efficiency of the current limiter. The buffer capacitor is charged to a buffer voltage being greater than a battery voltage of the battery, by increasing a voltage output of the current limiter with a boost converter, thereby increasing a permissible voltage droop of the buffer capacitor. The buffer capacitor is charged to at least a threshold voltage in response to the load entering a sleep mode, wherein the threshold voltage is programmed to reduce a leakage of the buffer capacitor as a function of temperature, and the current limiter operates as a voltage limiter when a voltage of the buffer capacitor exceeds the threshold voltage. The buffer capacitor is charged to a buffer voltage being higher than a battery voltage, by boosting a voltage output of the current limiter with a boost converter, and reducing the buffer voltage with a buck converter to supply a load voltage to the load, wherein the buck converter and the boost converter share an inductor. An output voltage of the current limiter is doubled with a voltage doubler in response to the first current being less than half of a limit current of the current limiter. A switching frequency of the voltage doubler is controlled with a voltage drop across the current limiter.

In another embodiment, an apparatus comprises a battery configured to supply a first current, wherein the first current is at or below a threshold current. A buffer capacitor is configured for one or more of being charged by the first current and supplying a second current to a load, wherein the second current comprises a pulsed current. A current limiter is interposed between the battery and the buffer capacitor, wherein the current limiter limits the first current and the buffer capacitor supplies a pulsed load current to the load. A plurality of sensors is configured to control the current limiter. The current limiter must comprise a conductive bypass mode configured to connect the battery to the buffer capacitor through a low impedance path in response to the load entering a sleep mode and the buffer capacitor being charged above a threshold voltage.

Alternative embodiments of the apparatus further include one of the following features, or any combination thereof. The plurality of sensors comprises a temperature sensor configured to determine a current limit of the current limiter based on a temperature of the battery. A switch is configured to disconnect the buffer capacitor from the load in response to the load entering a sleep mode, and the current limiter is configured to recharge the buffer capacitor prior to reconnecting the buffer capacitor to the load with the switch in response to the load exiting the sleep mode. A buck converter is interposed between the current limiter and the buffer capacitor, wherein the buck converter is configured to charge the buffer capacitor when the buffer voltage is lower than the battery voltage, thereby maximizing one or more of an output current of the current limiter and a power efficiency of the current limiter. A boost converter is interposed between the current limiter and the buffer capacitor, wherein the boost converter is configured to charge the buffer capacitor to a buffer voltage being greater than a battery voltage of the battery, thereby increasing a permissible voltage droop of the buffer capacitor. A voltage doubler is interposed between the current limiter and the buffer capacitor, wherein the voltage doubler is configured to double an output voltage of the current limiter in response to the first current being less than half of a limit current of the current limiter.

Also disclosed is a method for power management for applications having duty-cycled high peak supply currents comprises supply a current with a supply source, wherein one or more of a lifetime and a current capacity of the supply source is degraded in response to the current being a high peak current. The current of the supply source is limited with a current limiter. The current limiter is controlled with at least one of a plurality of sensor inputs to limit the current from being the high peak current.

The disclosure of the method for power management for applications having duty-cycled high peak supply currents extends to one of the following features, or any combination thereof. The current limiter is latched into a conductive bypass mode and a bias circuit of the current limiter is disabled, in response to the load entering a sleep mode and the buffer capacitor being charged above a threshold voltage, wherein the threshold voltage is greater than a minimum voltage. An output voltage of the current limiter is doubled with a voltage doubler in response to the continuous current being less than half of a limit current of the current limiter.

Claim 1:
A method for power management for applications having duty-cycled high peak supply currents comprising:
charging (<NUM>) a buffer capacitor with a first current supplied by a battery, wherein the first current is limited by a current limiter;
supplying (<NUM>) a load with a second current supplied by the buffer capacitor, wherein the second current comprises a pulsed current; and
controlling (<NUM>)the current limiter with at least one of a plurality of sensor inputs to limit a capacity degradation of the battery;
wherein the current limiter is latched into a conductive bypass mode and a bias circuit of the current limiter is disabled, in response to the load entering a sleep mode and the buffer capacitor being charged above a threshold voltage, wherein the threshold voltage is greater than a minimum voltage.