Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

<CIT> discloses a stack of two material layers which are arranges between two overlying material layers, wherein between such overlying material layers an temporary material layer is arranged which can be removed after forming a memory opening and a memory stack structure.

<CIT> discloses 3D memory devices and its manufacturing method.

<CIT> discloses a three-dimensional memory device containing CMOS devices over memory stack structures.

<CIT> discloses a three-dimensional semiconductor memory device including stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions.

Embodiments of 3D memory devices and methods for forming the same are disclosed herein.

One aspect relates to a 3D memory device according to claim <NUM>.

Another aspect relates to a method for forming a 3D memory device according to claim <NUM>.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

In some 3D memory devices, such as 3D NAND memory devices, a slit structure is used for various functions including separating the memory array into multiple blocks, providing access for the etchant and chemical precursor during a gate replacement process, and providing an electrical connection to the source of the memory array. <FIG> illustrates a cross-section of a 3D memory device <NUM>. As illustrated in <FIG>, <FIG> memory device <NUM> includes a memory stack <NUM> above a substrate <NUM>. 3D memory device <NUM> also includes an array of channel structures <NUM> and a slit structure <NUM> each extending vertically through memory stack <NUM>. Each channel structure <NUM> functions as a NAND memory string, and slit structure <NUM> functions as an electrical connection to the source of the NAND memory string, for example, an array common source (ACS) of an array of channel structures <NUM>.

3D memory device <NUM> further includes an interconnect structure for channel structure <NUM> and slit structure <NUM> above memory stack <NUM>, which includes a local contact layer <NUM> on memory stack <NUM>, and an interconnect layer <NUM> on local contact layer <NUM>. It is noted that x-, y-, and z- axes are included in <FIG> to illustrate the spatial relationships of the components in 3D memory device <NUM>. Substrate <NUM> includes two lateral surfaces extending laterally in the x-y plane: a front surface on the front side of the wafer, and a back surface on the backside opposite to the front side of the wafer. The x- and y-directions are two orthogonal directions in the wafer plane: x-direction is the word line direction, and the y-direction is the bit line direction. The z-axis is perpendicular to both the x- and y- axes. As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device <NUM>) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM>) in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

Local contact layer <NUM> includes local contacts (also known as "C1") that are in contact with a structure in memory stack <NUM> directly, including a channel local contact <NUM> in contact with channel structure <NUM> and a slit local contact <NUM> in contact with slit structure <NUM>. In some embodiments, 3D memory device <NUM> includes additional local contacts, such as staircase local contacts <NUM> each in contact with a respective one of the word lines in a staircase structure <NUM> at the edge of memory stack <NUM> as well as peripheral local contacts <NUM> in contact with substrate <NUM> outside of memory stack <NUM>. Interconnect layer <NUM> includes contacts (also known as "V0") that are in contact with local contact layer <NUM>, such as channel contacts <NUM> in contact with channel local contacts <NUM>, respectively, a slit contact <NUM> in contact with slit local contact <NUM>, staircase contacts <NUM> in contact with staircase local contacts <NUM>, respectively, and peripheral contacts <NUM> in contact with peripheral local contacts <NUM>, respectively.

In 3D memory device <NUM>, channel local contacts <NUM> and slit local contact <NUM> have different depths, different critical dimensions, and land on different materials (e.g., channel local contact <NUM> lands on a polysilicon plug of channel structure <NUM>, while slit local contact <NUM> lands on a tungsten source contact of slit structure <NUM>), which makes the fabrication of local contact layer <NUM> more challenging. Moreover, as the upper ends of different types of local contacts (e.g., channel local contact <NUM>, slit local contact <NUM>, staircase local contact <NUM>, and peripheral local contact <NUM>) are not flush with one another (i.e., not aligned in the z-direction), different types of contacts in interconnect layer <NUM> (e.g., channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM>) have different depths, which further increases the complexity of fabricating the interconnect structure.

Various embodiments in accordance with the present disclosure provide 3D memory devices with improved interconnect structures. By removing the slit local contacts and merging the metal deposition steps of slit source contacts and various types of local contacts, e.g., channel local contacts, staircase local contacts, and/or peripheral local contacts, the process cycle time and fabrication cost can be reduced, with increased yield. Moreover, as the upper ends of the slit source contacts and various types of local contacts can be flush with one another, different types of V0 contacts in the interconnect structure can have the same depth and land on the same type of material, making the fabrication process less challenging as well.

<FIG> illustrates a cross-section of an exemplary 3D memory device <NUM> with an interconnect structure, according to some embodiments of the present disclosure. 3D memory device <NUM> includes a substrate <NUM>, which can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. In some embodiments, substrate <NUM> is a thinned substrate (e.g., a semiconductor layer), which was thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof.

3D memory device <NUM> can be part of a monolithic 3D memory device. The term "monolithic" means that the components (e.g., the peripheral device and memory array device) of the 3D memory device are formed on a single substrate. For monolithic 3D memory devices, the fabrication encounters additional restrictions due to the convolution of the peripheral device processing and the memory array device processing. For example, the fabrication of the memory array device (e.g., NAND memory strings) is constrained by the thermal budget associated with the peripheral devices that have been formed or to be formed on the same substrate.

Alternatively, 3D memory device <NUM> can be part of a non-monolithic 3D memory device, in which components (e.g., the peripheral device and memory array device) can be formed separately on different substrates and then bonded, for example, in a face-to-face manner. In some embodiments, the memory array device substrate (e.g., substrate <NUM>) remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral device (e.g., including any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>, such as page buffers, decoders, and latches; not shown) is flipped and faces down toward the memory array device (e.g., NAND memory strings) for hybrid bonding. It is understood that in some embodiments, the memory array device substrate (e.g., substrate <NUM>) is flipped and faces down toward the peripheral device (not shown) for hybrid bonding, so that in the bonded non-monolithic 3D memory device, the memory array device is above the peripheral device. The memory array device substrate (e.g., substrate <NUM>) can be a thinned substrate (which is not the substrate of the bonded non-monolithic 3D memory device), and the back-end-of-line (BEOL) interconnects of the non-monolithic 3D memory device can be formed on the backside of the thinned memory array device substrate.

In some embodiments, 3D memory device <NUM> is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings each extending vertically above substrate <NUM>. The memory array device can include an array of channel structures <NUM> functioning as the array of NAND memory strings. As shown in <FIG>, channel structure <NUM> extends vertically through a plurality of pairs each including a conductive layer <NUM> and a dielectric layer <NUM>. The interleaved conductive layers <NUM> and dielectric layers <NUM> are part of a memory stack <NUM>. The number of the pairs of conductive layers <NUM> and dielectric layers <NUM> in memory stack <NUM> (e.g., <NUM>, <NUM>, <NUM>, or <NUM>) determines the number of memory cells in 3D memory device <NUM>. It is understood that in some embodiments, memory stack <NUM> may have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of conductive layers <NUM> and dielectric layers <NUM> in each memory deck can be the same or different.

Memory stack <NUM> includes a plurality of interleaved conductive layers <NUM> and dielectric layers <NUM>. Conductive layers <NUM> and dielectric layers <NUM> in memory stack <NUM> alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack <NUM>, each conductive layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two conductive layers <NUM> on both sides. Conductive layers <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer <NUM> can be a gate electrode (gate line) surrounding channel structure <NUM> and can extend laterally as a word line. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. It is understood that a silicon oxide film, such as an in-situ steam generation (ISSG) silicon oxide, may be formed between substrate <NUM> (e.g., a silicon substrate) and memory stack <NUM>, according to some embodiments.

As shown in <FIG>, channel structure <NUM> can include a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel <NUM>) and a composite dielectric layer (e.g., as a memory film <NUM>). In some embodiments, semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single-crystal silicon. In some embodiments, memory film <NUM> is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of channel structure <NUM> can be partially or fully filled with a capping layer including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure <NUM> can have a cylinder shape (e.g., a pillar shape). The capping layer, semiconductor channel <NUM>, the tunneling layer, storage layer, and blocking layer of memory film <NUM> are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, memory film <NUM> can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, channel structure <NUM> further includes a semiconductor plug <NUM> in the bottom portion (e.g., at the lower end) of channel structure <NUM>. As used herein, the "upper end" of a component (e.g., channel structure <NUM>) is the end farther away from substrate <NUM> in the y-direction, and the "lower end" of the component (e.g., channel structure <NUM>) is the end closer to substrate <NUM> in the y-direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>. Semiconductor plug <NUM> can include a semiconductor material, such as silicon, which is epitaxially grown from substrate <NUM> in any suitable directions. It is understood that in some embodiments, semiconductor plug <NUM> includes single-crystal silicon, the same material of substrate <NUM>. In other words, semiconductor plug <NUM> can include an epitaxially-grown semiconductor layer that is the same material as substrate <NUM>. Semiconductor plug <NUM> can be below and in contact with the lower end of semiconductor channel <NUM>. Semiconductor plug <NUM> can function as a channel controlled by a source select gate of the NAND memory string.

In some embodiments, channel structure <NUM> further includes a channel plug <NUM> in the top portion (e.g., at the upper end) of channel structure <NUM>. Channel plug <NUM> can be above and in contact with the upper end of semiconductor channel <NUM>. Channel plug <NUM> can include semiconductor materials (e.g., polysilicon). By covering the upper end of channel structure <NUM> during the fabrication of 3D memory device <NUM>, channel plug <NUM> can function as an etch stop layer to prevent etching of dielectrics filled in channel structure <NUM>, such as silicon oxide and silicon nitride. In some embodiments, channel plug <NUM> can function as the drain of the NAND memory string.

As shown in <FIG>, <FIG> memory device <NUM> also includes a local contact layer <NUM> on memory stack <NUM> as part of the interconnect structure. In some embodiments, local contact layer <NUM> is formed on top of the upper end of channel structure <NUM> (i.e., channel plug <NUM>). Local contact layer <NUM> can include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and via contacts. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnects in local contact layer <NUM> are referred to herein as "local contacts" (also known as "C1"), which are in contact with a structure in memory stack <NUM> directly. In some embodiments, local contact layer <NUM> includes a channel local contact <NUM> above and in contact with the upper end of channel structure <NUM> (e.g., channel plug <NUM>).

Local contact layer <NUM> can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the local contacts (e.g., channel local contact <NUM>) can form. In some embodiments, local contact layer <NUM> includes channel local contact <NUM> in one or more local dielectric layers. Channel local contact <NUM> in local contact layer <NUM> can include conductive materials including, but not limited to, Cu, Al, W, Co, silicides, or any combination thereof. In one example, channel local contact <NUM> is made of tungsten. The ILD layers in local contact layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

As shown in <FIG>, <FIG> memory device <NUM> further includes a slit structure <NUM> extending vertically through local contact layer <NUM> and interleaved conductive layers <NUM> and dielectric layers <NUM> of memory stack <NUM>. Slit structure <NUM> can also extend laterally (e.g., in the bit line direction/y-direction in <FIG>) to separate memory stack <NUM> into multiple blocks. Slit structure <NUM> can include a slit opening that provides access for the chemical precursor to form conductive layers <NUM>. In some embodiments, slit structure <NUM> also includes a doped region (not shown) at its lower end in substrate <NUM> to reduce the resistance of the electrical connection with the ACS.

In some embodiments, slit structure <NUM> further includes a source contact <NUM> for electrically connecting the ACS of the NAND memory strings to the interconnect structures, such as source lines (not shown). In some embodiments, source contact <NUM> includes a wall-shaped contact. As shown in <FIG>, source contact <NUM> includes a lower source contact portion <NUM>-<NUM> in the bottom portion of slit structure <NUM> (e.g., in contact with the doped region) and an upper source contact portion <NUM>-<NUM> in the top portion of slit structure <NUM>. In some embodiments, upper source contact portion <NUM>-<NUM> is above and in contact with lower source contact portion <NUM>-<NUM> and has a different material of lower source contact portion <NUM>-<NUM>. Lower source contact portion <NUM>-<NUM> can include a conductive material, such as doped polysilicon, to reduce the contact resistance with the doped region. Upper source contact portion <NUM>-<NUM> can include conductive materials, such as a metal including, but not limited to, W, Co, Cu, Al, or any combination thereof. In one example, upper source contact portion <NUM>-<NUM> may include tungsten. As described below in detail, as the conductive materials of channel local contacts <NUM> and upper source contact portion <NUM>-<NUM> of slit structure <NUM> can be deposited in the same process, upper source contact portion <NUM>-<NUM> and channel local contacts <NUM> include the same conductive material, such as the same metal. In one example, the metal may include tungsten.

To electrically insulate source contact <NUM> of slit structure <NUM> from conductive layers <NUM> of memory stack <NUM>, slit structure <NUM> further includes a spacer <NUM> disposed along the sidewall of the slit opening and in etch-back recesses abutting the sidewall of the slit opening. That is, spacer <NUM> is formed laterally between source contact <NUM> and conductive layers <NUM> of memory stack <NUM>. Spacer <NUM> can include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in <FIG>, on at least one edge in the lateral direction (the x-direction and/or y-direction), memory stack <NUM> includes a staircase structure <NUM>. In staircase structure <NUM>, corresponding edges of conductor/dielectric layer pairs along the vertical direction (the z-direction in <FIG>) can be staggered laterally for word line fan-out. Each "level" of staircase structure <NUM> can include one or more conductor/dielectric layer pairs, each including a pair of conductive layer <NUM> (extending laterally in the x-direction as the word lines) and dielectric layer <NUM>. In some embodiments, the top layer in each level of staircase structure <NUM> is one of conductive layers <NUM> for interconnection in the vertical directions (e.g., word line fan-out). In some embodiments, every two adjacent levels of staircase structure <NUM> are offset by a nominally same distance in the vertical direction and a nominally same distance in the lateral direction. Each offset thus can form a "landing area" for interconnection with the word lines of 3D memory device <NUM> in the vertical direction.

In some embodiments, 3D memory device <NUM> further includes staircase local contacts <NUM> (also known as "word line local contacts") each above and in contact with a respective one of conductive layers (word line) <NUM> at staircase structure <NUM> of memory stack <NUM>. Each staircase local contact <NUM> can extend vertically through the ILD layers in local contact layer <NUM> and further through the ILD layer covering staircase structure <NUM> to reach to a respective conductive layer (word line) <NUM> on the edge of memory stack <NUM>. Staircase local contacts <NUM> can include conductive materials, such as a metal including, but not limited to, W, Co, Cu, Al, or any combination thereof. In one example, staircase local contact <NUM> may include tungsten.

In some embodiments, 3D memory device <NUM> further includes peripheral local contacts <NUM> each extending vertically to substrate <NUM> outside of memory stack <NUM>. Each peripheral local contact <NUM> can have a depth greater than the depth of memory stack <NUM> to extend vertically from local contact layer <NUM> to substrate <NUM> in a peripheral region that is outside of memory stack <NUM>. In some embodiments, peripheral local contact <NUM> is above and in contact with a peripheral circuit (not shown) or a doped region (a P-well or N-well, not shown) in substrate <NUM> for transferring electrical signals to and/or from the peripheral circuit or the doped region. In some embodiments, the peripheral circuits include any suitable digital, analog, and/or mixed-signal peripheral circuits used for facilitating the operation of 3D memory device <NUM>. For example, the peripheral circuits can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of the circuits (e.g., transistors, diodes, resistors, or capacitors, etc.). Peripheral local contacts <NUM> can include conductive materials, such as a metal including, but not limited to, W, Co, Cu, Al, or any combination thereof. In one example, peripheral local contact <NUM> may include tungsten.

3D memory device <NUM> further includes a barrier structure <NUM> including interleaved first dielectric layers and second dielectric layers having different dielectric materials. For example, the dielectric materials of first and second dielectric layers may be silicon oxide and silicon nitride, respectively. In some embodiments, the first and second dielectric layers of barrier structure <NUM> are the same as those forming a dielectric stack that eventually becomes memory stack <NUM> after the gate replacement process as described below in detail. In some embodiments, one or more of peripheral local contacts <NUM> extend through barrier structure <NUM>. That is, barrier structure <NUM> surrounds peripheral local contact <NUM> as a barrier that separates peripheral local contact <NUM> from other nearby structures. In some embodiments, peripheral local contact <NUM> includes a via contact, as opposed to a wall-shaped contact. It is understood that although peripheral local contacts <NUM> (with or without barrier structure <NUM> surrounded) locate in the peripheral region outside of memory stack <NUM> as shown in <FIG>, in some embodiments, one or more peripheral local contacts <NUM> (with or without barrier structure <NUM> surrounded) may be formed within memory stack <NUM>, also known as "through array contacts" (TACs).

Different from 3D memory device <NUM> in <FIG>, which includes slit local contact <NUM> in local contact layer <NUM> above and in contact with slit structure <NUM>, 3D memory device <NUM> in <FIG> does not include a slit local contact in local contact layer <NUM>. Instead, slit structure <NUM> (and upper source contact portion <NUM>-<NUM> therein) can extend vertically further through local contact layer <NUM>. By replacing the slit local contact with a continues, wall-type contact (e.g., source contact <NUM>), the overlay control for the local contacts in local contact layer <NUM> can be simplified, and the resistance of the interconnect structure can be reduced. Moreover, the upper end of slit structure <NUM> (and upper source contact portion <NUM>-<NUM> therein) can be flush with the upper end of each of the local contacts including channel local contact <NUM>, staircase local contact <NUM>, and peripheral local contact <NUM>, e.g., in the same plane after the same planarization process as described below in detail. That is, the upper ends of channel local contact <NUM>, slit structure <NUM>, staircase local contact <NUM>, and peripheral local contact <NUM> are flush with one another, according to some embodiments. In some embodiments, upper source contact portion <NUM>-<NUM>, channel local contact <NUM>, staircase local contact <NUM>, and peripheral local contact <NUM> include the same conductive material, e.g., deposited by the same deposition process as described below in detail. For example, upper source contact portion <NUM>-<NUM>, channel local contact <NUM>, staircase local contact <NUM>, and peripheral local contact <NUM> include the same metal, such as tungsten. The design of the local contacts of 3D memory device <NUM> in <FIG> can thus simplify the fabrication process and reduce the cost and process cycle.

As shown in <FIG>, <FIG> memory device <NUM> also includes an interconnect layer <NUM> on local contact layer <NUM> as part of the interconnect structure. Interconnect layer <NUM> can include a plurality of via contacts (also known as "V0"), such as channel contacts <NUM> each above and in contact with the upper end of a respective one of channel local contacts <NUM> and a slit contact <NUM> above and in contact with the upper end of slit structure <NUM> (e.g., upper source contact portion <NUM>-<NUM> therein). In some embodiments, interconnect layer <NUM> further includes staircase contacts <NUM> (also known as "word line contacts") each above and in contact with the upper end of a respective one of staircase local contact <NUM>, and peripheral contacts <NUM> each above and in contact with the upper end of a respective one of peripheral local contact <NUM>. Interconnect layer <NUM> can further include one or more ILD layers in which channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM> can form. That is, interconnect layer <NUM> can include channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM> in one or more first dielectric layers. Channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM> in interconnect layer <NUM> can include conductive materials including, but not limited to, Cu, Al, W, Co, silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

Different from 3D memory device <NUM> in <FIG> in which the contacts in interconnect layer <NUM> have different depths, the various types of contacts (e.g., channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM>) in interconnect layer <NUM> of 3D memory device <NUM> in <FIG> have the same depth. In some embodiments, the upper ends of channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM> are flush with one another, and the lower ends of channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM> are flush with one another as well. As a result, the fabrication process for forming interconnect layer <NUM> can be less challenging. As described below in detail, the same deposition and planarization processes can be used to form the various types of contacts (e.g., channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM>) in interconnect layer <NUM>. Thus, channel contact <NUM>, slit contact <NUM>, staircase contact <NUM>, and peripheral contact <NUM> can have the same conductive materials, such as tungsten.

It is to be understood that the number of interconnect layers in 3D memory device <NUM> is not limited by the example in <FIG>. Additional interconnect layer(s) can be formed to provide desired interconnect structures of 3D memory device <NUM>. Nevertheless, local contact layer <NUM> and interconnect layer <NUM> form interconnect structures for transferring electrical signals from and/or to channel structure <NUM>, slit structure <NUM>, conductive layers (word lines) <NUM>, and peripheral circuits/doped regions (not shown) in substrate <NUM>.

<FIG> illustrate a fabrication process for forming an exemplary 3D memory device with an interconnect structure, according to some embodiments of the present disclosure. <FIG> illustrates a flowchart of a method <NUM> for forming an exemplary 3D memory device with an interconnect structure, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in <FIG> and <FIG> include 3D memory device <NUM> depicted in <FIG>. <FIG> and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a dielectric stack including interleaved sacrificial layers and dielectric layers above a substrate. The substrate can be a silicon substrate. Referring to <FIG>, a dielectric stack <NUM> including a plurality pairs of a sacrificial layer <NUM> and a dielectric layer <NUM> (dielectric/sacrificial layer pairs) is formed above a silicon substrate <NUM>. Dielectric stack <NUM> includes interleaved sacrificial layers <NUM> and dielectric layers <NUM>, according to some embodiments. Dielectric layers <NUM> and sacrificial layers <NUM> can be alternatingly deposited on silicon substrate <NUM> to form dielectric stack <NUM>. In some embodiments, each dielectric layer <NUM> includes a layer of silicon oxide, and each sacrificial layer <NUM> includes a layer of silicon nitride. That is, a plurality of silicon nitride layers and a plurality of silicon oxide layers can be alternatingly deposited above silicon substrate <NUM> to form dielectric stack <NUM>. In some embodiments, a barrier structure <NUM> including interleaved first dielectric layers and second dielectric layers is formed outside of dielectric stack <NUM> above silicon substrate <NUM>. First and second dielectric layers of barrier structure <NUM> can include the same materials as sacrificial layers <NUM> and dielectric layers <NUM> of dielectric stack <NUM>, respectively. Dielectric stack <NUM> and barrier structure <NUM> can be formed together by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

As illustrated in <FIG>, a staircase structure <NUM> can be formed on the edge of dielectric stack <NUM>. Staircase structure <NUM> can be formed by performing a plurality of so-called "trim-etch" cycles for the dielectric/sacrificial layer pairs of dielectric stack <NUM> toward silicon substrate <NUM>. Due to the repeated trim-etch cycles for the dielectric/sacrificial layer pairs of dielectric stack <NUM>, dielectric stack <NUM> can have a tilted edge and a top dielectric/sacrificial layer pair shorter than the bottom one, as shown in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a channel structure extending vertically through the dielectric stack is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack is formed, a memory film and a semiconductor channel are subsequently formed over a sidewall of the channel hole, and a channel plug is formed above and in contact with the semiconductor channel.

As illustrated in <FIG>, a channel hole is an opening extending vertically through dielectric stack <NUM>. In some embodiments, a plurality of openings are formed through dielectric stack <NUM> such that each opening becomes the location for growing an individual channel structure <NUM> in the later process. In some embodiments, fabrication processes for forming the channel hole of channel structure <NUM> include wet etching and/or dry etching, such as deep-ion reactive etching (DRIE). In some embodiments, the channel hole of channel structure <NUM> extends further through the top portion of silicon substrate <NUM>. The etching process through dielectric stack <NUM> may not stop at the top surface of silicon substrate <NUM> and may continue to etch part of silicon substrate <NUM>. As illustrated in <FIG>, a semiconductor plug <NUM> can be formed by filling the bottom portion of the channel hole with single-crystal silicon epitaxially grown from silicon substrate <NUM> in any suitable directions (e.g., from the bottom surface and/or side surface). The fabrication processes for epitaxially growing semiconductor plug <NUM> can include, but not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combinations thereof.

As illustrated in <FIG>, a memory film <NUM> (including a blocking layer, a storage layer, and a tunneling layer) and a semiconductor channel <NUM> are formed along the sidewall of the channel hole of channel structure <NUM> and above semiconductor plug <NUM>. In some embodiments, memory film <NUM> is first deposited along the sidewall of the channel hole and above semiconductor plug <NUM>, and semiconductor channel <NUM> is then deposited over memory film <NUM>. The blocking layer, storage layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form memory film <NUM>. Semiconductor channel <NUM> can then be formed by depositing polysilicon on the tunneling layer using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. Semiconductor channel <NUM> can be in contact with semiconductor plug <NUM> using, for example, a SONO punch process. In some embodiments, semiconductor channel <NUM> is deposited in the channel hole without completely filling the channel hole. In some embodiments, a capping layer, such as a silicon oxide layer, is formed in the channel hole to fully or partially fill the remaining space of the channel hole using one or more thin film deposition processes, such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

As illustrated in <FIG>, a channel plug <NUM> is formed in the top portion of the channel hole of channel structure <NUM>. In some embodiments, parts of memory film <NUM>, semiconductor channel <NUM>, and the capping layer that are on the top surface of dielectric stack <NUM> are removed and planarized by CMP, wet etching and/or dry etching. A recess then can be formed in the top portion of the channel hole by wet etching and/or drying etching parts of semiconductor channel <NUM> and the capping layer in the top portion of the channel hole. Channel plug <NUM> then can be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Channel structure <NUM> is thereby formed through dielectric stack <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a local dielectric layer is formed on the dielectric stack. The local dielectric layer is part of the interconnect structure of the final 3D memory device to be formed. As illustrated in <FIG>, a local dielectric layer <NUM> is formed on dielectric stack <NUM>. Local dielectric layer <NUM> can be formed by depositing dielectric materials, such as silicon oxide and/or silicon nitride, using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, on top of the top surface of dielectric stack <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a slit opening extending vertically through the local dielectric layer and the dielectric stack is formed. As illustrated in <FIG>, a slit opening <NUM> is formed using wet etching and/or dry etching, such as DRIE. In some embodiments, the etching process etches slit opening <NUM> through local dielectric layer <NUM> and interleaved sacrificial layers <NUM> and dielectric layers <NUM> (e.g., silicon nitride layers and silicon oxide layers) of dielectric stack <NUM> to reach silicon substrate <NUM>. Slit opening <NUM> can be patterned by an etching mask (e.g., photoresist) using photolithography, such that slit opening <NUM> is to be formed at the place where a slit structure is to be formed.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers (i.e., the so-called "gate replacement" process). As illustrated in <FIG>, sacrificial layers <NUM> (shown in <FIG>) are replaced with conductive layers <NUM>, and a memory stack <NUM> including interleaved conductive layers <NUM> and dielectric layers <NUM> is thereby formed. It is understood that the gate replacement process may not affect barrier structure <NUM>, which still includes the interleaved first and second dielectric layers afterward and in the final 3D memory device.

In some embodiments, lateral recesses (not shown) are first formed by removing sacrificial layers <NUM> through slit opening <NUM>. In some embodiments, sacrificial layers <NUM> are removed by applying etching solutions through slit opening <NUM>, such that sacrificial layers <NUM> are removed, creating the lateral recesses interleaved between dielectric layers <NUM>. The etching solutions can include any suitable etchants that etch sacrificial layers <NUM> selective to dielectric layers <NUM>. As illustrated in <FIG>, conductive layers <NUM> are deposited into the lateral recesses through slit opening <NUM>. In some embodiments, gate dielectric layers are deposited into the lateral recesses prior to conductive layers <NUM>, such that conductive layers <NUM> are deposited on the gate dielectric layers. Conductive layers <NUM>, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first source contact portion is formed in the slit opening. In some embodiments, to form the first source contact portion, a spacer is formed over a sidewall of the slit opening, a conductive layer is deposited over the spacer in the slit opening, and the conductive layer is etched back in the slit opening. The conductive layer can include polysilicon.

As illustrated in <FIG>, a spacer <NUM> can be formed over the sidewall of slit opening <NUM>. In some embodiments, a doped region (not shown) can be first formed using ion implantation and/or thermal diffusion to dope P-type or N-type dopants into part of silicon substrate <NUM> exposed through slit opening <NUM>. In some embodiments, etch-back recesses are formed in each conductive layer <NUM> abutting the sidewall of slit opening <NUM>. The etch-back recesses can be etched-back using wet etching and/or dry etching processes through slit opening <NUM>. Spacer <NUM> including one or more dielectric layers, such as silicon oxide and silicon nitride, is deposited into the etch-back recesses and along the sidewall of slit opening <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, according to some embodiments. As illustrated in <FIG>, a lower source contact portion <NUM>-<NUM> is formed in the bottom portion of silt opening <NUM>. In some embodiments, a conductive layer including, for example, doped polysilicon, is deposited over spacer <NUM> in slit opening <NUM>. In some embodiments, an etch-back process is performed to remove part of the conductive layer in the top portion of slit opening <NUM>, leaving lower source contact portion <NUM>-<NUM> in the bottom portion of slit opening <NUM>. For example, polysilicon may be etched back using wet etching and/or dry etching.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a channel local contact opening through the local dielectric layer to expose the channel structure, a staircase local contact opening through the local dielectric layer to expose one of the conductive layers at a staircase structure on an edge of the memory stack, and a peripheral local contact opening extending vertically to the substrate outside of the memory stack, are simultaneously formed. In some embodiments, a hard mask is formed to cover the slit opening prior to the simultaneous formation of the channel local contact opening, staircase local contact opening, and peripheral local contact opening.

As illustrated in <FIG>, a hard mask <NUM> is formed on local dielectric layer <NUM> and in slit opening <NUM> (shown in <FIG>) to cover slit opening <NUM>. Hard mask <NUM> can be patterned using photolithography, followed by dry etching and/or wet etching processes, to create openings for forming channel local contact openings <NUM>, staircase local contact openings <NUM>, and peripheral local contact openings <NUM>. One or more cycles of drying etching and/or wet etching, such as DRIE, can be performed, through the openings in hard mask <NUM> to etch channel local contact openings <NUM>, staircase local contact openings <NUM>, and peripheral local contact openings <NUM> simultaneously in the same etching process. In some embodiments, local dielectric layer <NUM> is etched through to form channel local contact openings <NUM>, stopping at channel plugs <NUM> of channel structures <NUM> to expose channel structures <NUM>, respectively. In some embodiments, local dielectric layer <NUM> is etched through to form staircase local contact openings <NUM>, stopping at conductive layers <NUM> (shown in <FIG>) at staircase structure <NUM> on the edge of memory stack <NUM> to expose conductive layers <NUM>, respectively. In some embodiments, local dielectric layer <NUM> and the ILD layers outside of memory stack <NUM> are etched through to form peripheral local contact openings <NUM>, stopping at silicon substrate <NUM>. In some embodiments, the interleaved first and second dielectric layers in barrier structure <NUM> are etched through as well to form peripheral local contact opening <NUM> extending vertically through barrier structure <NUM> to silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a channel local contact in the channel local contact opening, a second source contact portion above the first source contact portion in the slit opening, a staircase local contact in the staircase local contact opening, and a peripheral local contact in the peripheral local contact opening are simultaneously formed. In some embodiments, to simultaneously channel local contact, the second source contact portion, the staircase local contact, and the peripheral local contact, a conductive layer is simultaneously deposited in the channel local contact opening, the slit opening, the staircase local contact opening, and the peripheral local contact opening, and the deposited conductive layer is planarized, such that upper ends of the channel local contact, the second source contact portion, the staircase local contact, and the peripheral local contact are flush with one another. The conductive layer can include tungsten.

As illustrated in <FIG>, hard mask <NUM> (shown in <FIG>) is removed, and channel local contacts <NUM>, upper source contact portion <NUM>-<NUM>, staircase local contacts <NUM>, and peripheral local contacts <NUM> are simultaneously formed. In some embodiments, a conductive layer including, for example, tungsten, is deposited by the same deposition process into channel local contact opening <NUM> (shown in <FIG>), the remaining space of slit opening <NUM> (shown in <FIG> once hard mask <NUM> is removed), staircase local contact openings <NUM> (shown in <FIG>), and peripheral local contact openings <NUM> (shown in <FIG>) to simultaneously form channel local contacts <NUM>, upper source contact portion <NUM>-<NUM>, staircase local contacts <NUM>, and peripheral local contacts <NUM>. The deposition process can include thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A planarization process, such as CMP, can be performed to remove the excess conductive layer and planarize the deposited conductive layer. The upper ends of channel local contacts <NUM>, upper source contact portion <NUM>-<NUM>, staircase local contacts <NUM>, and peripheral local contacts <NUM> are thus flush with one another, according to some embodiments. A slit structure <NUM> including source contact <NUM> (including lower source contact portion <NUM>-<NUM> and upper source contact portion <NUM>-<NUM>) and spacer <NUM> is thereby formed as well.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an interconnect layer is formed on the local dielectric layer. The interconnect layer includes a channel contact above and in contact with the channel local contact, a slit contact above and in contact with the second source contact portion, a staircase contact above and in contact with the staircase local contact; and a peripheral contact above and in contact with the peripheral local contact. In some embodiments, to form the interconnect layer, another dielectric layer is formed on the local dielectric layer. In some embodiments, to form the interconnect layer, a channel contact opening through the another dielectric layer to expose the channel local contact, a slit contact opening through the another dielectric layer to expose the second source contact portion, a staircase contact opening through the another dielectric layer to expose the staircase local contact, and a peripheral contact opening through the another dielectric layer to expose the peripheral local contact are simultaneously formed. In some embodiments, to form the interconnect layer, a channel local contact in the channel local contact opening, a second source contact portion above the first source contact portion in the slit opening, and a staircase local contact in the staircase local contact opening are simultaneously formed.

As illustrated in <FIG>, a dielectric layer <NUM> is formed on local dielectric layer <NUM>. Dielectric layer <NUM> can be formed by depositing dielectric materials, such as silicon oxide and/or silicon nitride, using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, on top of the top surface of local dielectric layer <NUM>. A slit contact opening, channel contact openings, staircase contact openings, and peripheral contact openings are simultaneously formed through dielectric layer <NUM> using the same etching process. In some embodiments, the etching process etches the channel contact openings through dielectric layer <NUM> stopping at the upper ends of channel local contacts <NUM> to expose the upper end of channel local contact <NUM>, respectively. In some embodiments, the same etching process etches also etches the slit contact opening through dielectric layer <NUM> stopping at the upper end of slit structure <NUM> to expose the upper end of slit structure <NUM>. In some embodiments, the same etching process also etches the staircase contact openings through dielectric layer <NUM> stopping at the upper ends of staircase local contacts <NUM> to expose the upper end of staircase local contacts <NUM>, respectively. In some embodiments, the same etching process also etches the peripheral contact openings through dielectric layer <NUM> stopping at the upper ends of peripheral local contacts <NUM> to expose the upper end of staircase local contacts <NUM>, respectively. The etching process can include one or more cycles of wet etching and/or dry etching. The channel contact openings, staircase contact openings, peripheral contact openings, and slit contact opening can be patterned by an etching mask (e.g., photoresist) using photolithography, such that the channel contact openings, staircase contact openings, peripheral contact openings, and slit contact opening are aligned with channel local contacts <NUM>, staircase local contacts <NUM>, peripheral local contacts <NUM>, and upper source contact portion <NUM>-<NUM> of slit structure <NUM>, respectively.

As illustrated in <FIG>, a conductive layer including, for example, tungsten, is deposited by the same deposition process into the channel contact opening, slit contact opening, staircase contact openings, and peripheral contact openings to simultaneously form channel contacts <NUM>, slit contact <NUM>, staircase contacts <NUM>, and peripheral contacts <NUM>. An interconnect layer including channel contacts <NUM>, slit contact <NUM>, staircase contacts <NUM>, and peripheral contacts <NUM> is thereby formed. A planarization process, such as CMP, can be performed to remove the excess conductive layer and planarize the deposited conductive layer. The upper ends of channel contacts <NUM>, slit contact <NUM>, staircase contacts <NUM>, and peripheral contacts <NUM> are thus flush with one another, according to some embodiments.

According to one aspect of the present disclosure, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.

The 3D memory device further includes channel contact above and in contact with the upper end of the channel local contact, a slit contact above and in contact with the upper end of the slit structure, and a staircase contact above and in contact with the upper end of the staircase local contact. Upper ends of the channel contact, the slit contact, and the staircase contact are flush with one another.

In some embodiments, the channel contact, the slit contact, and the staircase contact have a same depth and include a same conductive material.

The slit structure includes a source contact including a first source contact portion and a second source contact portion above the first source contact portion and has a different material of the first source contact portion, and a spacer laterally between the source contact of the slit structure and the conductive layers of the memory stack.

In some embodiments, the second source contact portion, the channel local contact, and the staircase local contact include a same conductive material.

In some embodiments, the first source contact portion includes polysilicon, and the second source contact portion, the channel local contact, and the staircase local contact include a same metal. The metal can include tungsten.

In some embodiments, the channel structure includes a semiconductor channel and a memory film. In some embodiments, the channel structure further includes a channel plug in a top portion of the channel structure and in contact with the channel local contact.

The 3D memory device further includes a peripheral local contact extending vertically to the substrate outside of the memory stack. An upper end of the peripheral local contact is flush with the upper ends of the channel local contact, the slit structure, and the staircase local contact.

According to another aspect of the present disclosure, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a peripheral local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The peripheral local contact extends vertically to the substrate outside of the memory stack. Upper ends of the channel local contact, the slit structure, and the peripheral local contact are flush with one another.

In some embodiments, the 3D memory device further includes channel contact above and in contact with the upper end of the channel local contact, a slit contact above and in contact with the upper end of the slit structure, and a peripheral contact above and in contact with the upper end of the peripheral local contact. Upper ends of the channel contact, the slit contact, and the peripheral contact are flush with one another, according to some embodiments.

In some embodiments, the channel contact, the slit contact, and the peripheral contact have a same depth and include a same conductive material.

In some embodiments, the slit structure includes a source contact including a first source contact portion and a second source contact portion above the first source contact portion and has a different material of the first source contact portion, and a spacer laterally between the source contact of the slit structure and the conductive layers of the memory stack.

In some embodiments, the second source contact portion, the channel local contact, and the peripheral local contact include a same conductive material.

In some embodiments, the first source contact portion includes polysilicon, and the second source contact portion, the channel local contact, and the peripheral local contact include a same metal. The metal can include tungsten.

In some embodiments, the 3D memory device further includes a staircase local contact above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. An upper end of the staircase local contact is flush with the upper ends of the channel local contact, the slit structure, and the peripheral local contact, according to some embodiments.

In some embodiments, the 3D memory device further includes a barrier structure comprising interleaved first dielectric layers and second dielectric layers. The peripheral local contact extends vertically through the barrier structure, according to some embodiments.

In some embodiments, the peripheral local contact is a vertical interconnect access (via) contact.

According to still another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers is formed above a substrate. A local dielectric layer is formed on the dielectric stack. A slit opening extending vertically through the local dielectric layer and the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first source contact portion is formed in the slit opening. A channel local contact opening through the local dielectric layer to expose the channel structure, and a staircase local contact opening through the local dielectric layer to expose one of the conductive layers at a staircase structure on an edge of the memory stack are simultaneously formed. A channel local contact in the channel local contact opening, a second source contact portion above the first source contact portion in the slit opening, and a staircase local contact in the staircase local contact opening are simultaneously formed.

In some embodiments, to simultaneously form the channel local contact opening and the staircase local contact opening, (i) the channel local contact opening, (ii) the staircase local contact opening, and (iii) a peripheral local contact opening extending vertically to the substrate outside of the memory stack are simultaneously formed. In some embodiments, to simultaneously form the channel local contact, the second source contact portion, and the staircase local contact further comprises, (i) the channel local contact, (ii) the second source contact portion, (iii) the staircase local contact, and (iv) a peripheral local contact in the peripheral local contact opening are simultaneously formed.

In some embodiments, an interconnect layer is formed on the local dielectric layer. The interconnect layer can include (i) a channel contact above and in contact with the channel local contact, (ii) a slit contact above and in contact with the second source contact portion, (ii) a staircase contact above and in contact with the staircase local contact; and (iv) a peripheral contact above and in contact with the peripheral local contact.

In some embodiments, to form the interconnect layer, (i) a channel contact opening through the another dielectric layer to expose the channel local contact, (ii) a slit contact opening through the another dielectric layer to expose the second source contact portion, (iii) a staircase contact opening through the another dielectric layer to expose the staircase local contact, and (iv) a peripheral contact opening through the another dielectric layer to expose the peripheral local contact are simultaneously formed, a conductive layer is simultaneously deposited into the channel contact opening, the slit contact opening, the staircase contact opening, and the peripheral contact opening, and the deposited conductive layer is planarized, such upper ends of the channel contact, the slit contact, the staircase contact, and the peripheral contact are flush with one another.

In some embodiments, to simultaneously form the channel local contact, the second source contact portion, and the staircase local contact, a conductive layer is simultaneously deposited in the channel local contact opening, the slit opening, the staircase local contact opening, and the peripheral local contact opening, and the deposited conductive layer is planarized, such that upper ends of the channel local contact, the second source contact portion, the staircase local contact, and the peripheral local contact are flush with one another. In some embodiments, the conductive layer includes tungsten.

In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack is etched, a memory film and a semiconductor channel are subsequently formed over a sidewall of the channel hole, and a channel plug is formed above and in contact with the semiconductor channel.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A three-dimensional (3D) memory device ( <NUM>), comprising:
a substrate (<NUM>, <NUM>);
a memory stack ( <NUM>, <NUM>) comprising interleaved conductive layers (<NUM>, <NUM>) and dielectric layers (<NUM>, <NUM>, <NUM>) above the substrate (<NUM>, <NUM>);
a channel structure (<NUM>, <NUM>) extending vertically through the memory stack ( <NUM>, <NUM>);
a channel local contact ( <NUM>, <NUM>) above and in contact with the channel structure ( <NUM>, <NUM>);
a slit structure (<NUM>, <NUM>) extending vertically through the memory stack ( <NUM>, <NUM>); and
a peripheral local contact extending vertically to the substrate (<NUM>, <NUM>) outside of the memory stack (<NUM>, <NUM>),
wherein upper ends of the channel local contact (<NUM>, <NUM>), the slit structure ( <NUM>, <NUM>), and the peripheral local contact are flush with one another,
the memory device further comprising:
a channel contact (<NUM>) above and in contact with the upper end of the channel local contact (<NUM>);
a slit contact (<NUM>) above and in contact with the upper end of the slit structure (<NUM>); and
a peripheral contact (<NUM>) above and in contact with the upper end of the peripheral local contact (<NUM>),
wherein upper ends of the channel contact (<NUM>), the slit contact (<NUM>), and the peripheral contact (<NUM>) are flush with one another;
wherein the slit structure comprises:
a source contact (<NUM>) comprising a first source contact portion (<NUM>-<NUM>) and a second source contact portion (<NUM>-<NUM>) above the first source contact portion, the second source contact portion has a different material than the first source contact portion; and a spacer (<NUM>) laterally between the source contact of the slit structure and the conductive layers of the memory stack;
the memory device (<NUM>) further comprising a staircase local contact (<NUM>, <NUM>) above and in contact with one of the conductive layers (<NUM>, <NUM>) at a staircase structure (<NUM>) on an edge of the memory stack (<NUM>, <NUM>), wherein an upper end of the staircase local contact (<NUM>, <NUM>) is flush with the upper ends of the channel local contact (<NUM>, <NUM>), the slit structure (<NUM>, <NUM>), and the peripheral local contact,
wherein the memory device (<NUM>) further comprises a barrier structure (<NUM>, <NUM>) which comprises interleaved first dielectric layers and second dielectric layers, wherein the peripheral local contact (<NUM>, <NUM>) extends vertically through the barrier structure (<NUM>, <NUM>).