Patent Description:
Local Area Networks (LANs) and Metropolitan Area Networks (MANs) may use the Institute of Electrical and Electronics Engineers (IEEE) <NUM> (Ethernet) protocol and frame format for data communication. The Ethernet protocol uses a common media access control (MAC) sublayer of a data link layer in the Open Systems Interconnection model (OSI model). The OSI model is a conceptual model that partitions a communication system into abstraction layers. The MAC sublayer is responsible for transferring data to and from a Physical Layer and encapsulates frames received from upper layers (for example, frames received from a network layer in the OSI reference model) into frames appropriate for the transmission medium. Speed specific Media Independent Interfaces (MIIs) provide an interface to the physical layer that encodes frames for transmission and decodes received frames with the modulation specified for the speed of operation, transmission medium and supported link length.

A data center can include a plurality of servers, with each server including one or more Network Interface Controllers (NICs). During system power-on, NICs in a server are initialized and configured by a Power-On-Reset (POR) mechanism. After configuration of an Ethernet PHY in the NIC is complete, an Ethernet link is established by exchanging messages with link partners according to the Ethernet protocol.

<NPL>, discusses how the External Bus Interface (EBI) is used to connect external peripherals and memory for access through the data memory space. Specifically, when the EBI is enabled, data address space outside the internal SRAM becomes available using dedicated EBI pins. The EBI can interface external SRAM, SDRAM, and peripherals, such as LCD displays and other memory mapped devices.

Advantageous features of the invention are recited in the accompanying dependent claims.

Features of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, in which like numerals depict like parts, and in which:.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined as set forth in the accompanying claims.

An Ethernet link is established prior to initialization of the Basic Input/Output System (BIOS), Unified Extensible Firmware Interface (UEFI), or boot loaders, and loading of operating system device drivers to initialize the Ethernet controller for post-boot operation. The time period between establishing the Ethernet link and completion of the initialization of an Ethernet controller for post-boot operation allows the Ethernet link to be used to insert a malicious program in the system or to access data stored in the system.

A user-defined time period can be selected to delay configuring the Ethernet link after a power on reset to allow sufficient time for completion of the initialization of the Ethernet controller for post-boot operation.

<FIG> is a block diagram of a system <NUM> that includes a network interface controller <NUM> to delay enabling an Ethernet link after a power on reset to allow sufficient time for completion of the configuration of the network interface controller <NUM> for post-boot operation. The network interface controller <NUM> includes host interface circuitry <NUM>, a processor <NUM>, a non-volatile memory controller <NUM>, media access control (MAC) layer circuitry <NUM>, physical (PHY) layer circuitry <NUM>, memory <NUM> and a clock controller <NUM>.

Ethernet ports include the media access control layer circuitry <NUM> and physical (PHY) layer circuitry <NUM>. The processor <NUM> performs tasks in response to a power on reset that include tasks to initialize the media access control layer circuitry <NUM> and physical (PHY) layer circuitry <NUM> for Ethernet ports.

Non-volatile memory <NUM> includes a Serial Peripheral Interface (SPI) to communicate with the non-volatile memory controller <NUM> in the Network Interface Controller <NUM>. The non-volatile memory <NUM> stores firmware <NUM>, device configuration parameters <NUM> and identifiers, for example, Media Access Control (MAC) layer addresses.

The memory <NUM> is a volatile memory to store the firmware <NUM>, the device configuration parameters <NUM> and identifiers that are also stored in non-volatile memory <NUM>.

The Media Access Control layer circuitry <NUM> includes a plurality of full duplex Ethernet layer ports. In an embodiment there can be four full duplex Ethernet layer ports. The Media Access Control layer circuitry <NUM> uses the Ethernet protocol.

The physical (PHY) layer circuitry <NUM> (PHY circuitry) provides the plurality of Ethernet ports with integrated PHY interfaces to connect directly to a medium or to external PHYs. In an embodiment with four full duplex Ethernet MAC ports, the physical PHY circuitry <NUM> supports eight physical high speed SerDes lanes, two per Ethernet layer port.

The external clock source <NUM> outputs an electric signal with a constant frequency (CLK_SRC). The external clock source <NUM> can be a crystal oscillator.

The clock controller <NUM> receives CLK_SRC from the external clock source <NUM> and uses CLK_SRC to generate other clocks with different frequencies for use by the processor <NUM>, the MAC layer circuitry <NUM> (MAC circuitry) and the PHY layer circuitry114 in the network interface controller <NUM>.

The host interface circuitry <NUM> is communicatively coupled over bus <NUM> to a host interface. In an embodiment, the host interface circuitry <NUM> may include a Peripheral Component Interconnect Express (PCIe) adapter that is communicatively coupled over bus <NUM> using the Peripheral Component Interconnect Express (PCIe) protocol to a host. The PCIe standards are available at www.

Power source <NUM> provides power to the components of system <NUM>. More specifically, power source <NUM> typically interfaces to one or multiple power supplies <NUM> in system <NUM> to provide power to the components of system <NUM>. In one example, power supply <NUM> includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source <NUM>. In one example, power source <NUM> includes a DC power source, such as an external AC to DC converter. In one example, power source <NUM> or power supply <NUM> includes wireless charging hardware to charge via proximity to a charging field. In one example, power supply <NUM> can include an internal battery or fuel cell source.

The system <NUM> is held in a reset state while the state of a power on reset signal indicates that the power source <NUM> is below the normal operation voltage.

<FIG> is an embodiment of a dynamic port enable register <NUM> used to delay configuring an Ethernet port for a delay time after a power on reset.

In the embodiment shown, the dynamic port enable register <NUM> has <NUM>-bits, with one of the <NUM>-bits reserved (unused). One bit (bit <NUM> in the embodiment shown in <FIG>) is used to select enabling delay of the enabling of the Ethernet port. The default when bit <NUM> is set to logic '<NUM>', is not to enable delay of the enabling of the Ethernet port. If bit <NUM> is set to logic '<NUM>', delay of the enabling of the Ethernet port is selected.

Four bits (bits <NUM>:<NUM> in the embodiment shown in <FIG>) of the dynamic port enable register <NUM> are used to select the ports to enable delay of the enabling of the respective Ethernet port. Each of the respective four bits are assigned to one of four communications ports (port <NUM>, port <NUM>, port <NUM>, port <NUM>). For example, if bits <NUM>:<NUM> are '0001b', one of the ports, for example, port <NUM> is selected and if bits <NUM>:<NUM> are '0101b', two of the ports, for example, port <NUM> and port <NUM> are selected.

Ten bits (bits <NUM>:<NUM> in the embodiment shown in <FIG>) of the dynamic port enable register <NUM> are used to select a time to delay (delay time) configuring of the selected communication port(s). In one embodiment, the maximum delay time is <NUM> seconds when bits <NUM>:<NUM> are '1111111111b' and the minimum delay time is <NUM> second when bits <NUM>:<NUM> are '0000000001b'. The time to delay can be selected to adapt to different systems with variable configurations. In other embodiments, the minimum delay time can be another unit of time, for example <NUM> microsecond, <NUM> millisecond or a packet transmission time.

One dynamic port enable register <NUM> is used in an embodiment in which one or more of the ports have the same delay time. In an embodiment in which the ports have different delay times, a dynamic port enable register <NUM> is assigned per port to store the delay time for the port.

The user-defined time period selected to delay configuration of an Ethernet link to allow sufficient time for completion of the initialization of the Ethernet controller for post-boot operation can be part of a security suite that may include encryption, cryptographic operation, authentication and resource partitioning.

The user-defined time period selected to delay configuration of an Ethernet link can be applied to other types of MACs and PHYs.

<FIG> is a flowgraph illustrating a method performed in system <NUM> to delay configuring an Ethernet port in a NIC <NUM> after a power on reset to allow sufficient time for completion of the configuration of the NIC <NUM> for post-boot operation.

At block <NUM>, upon detecting power has been applied to the system <NUM>, a link enable delay timer is selected to delay enabling of the Ethernet link. The link enable delay timer uses an internal clock generated by the clock controller <NUM> after an internal Phase-locked loop (PLL) locks during power on reset. The link enable delay timer can be a hardware timer in clock controller <NUM> or a software timer in firmware <NUM>.

At block <NUM>, upon detecting from the state of the power on reset signal that the power source <NUM> is no longer below normal operation range, the device configuration parameters <NUM> and firmware <NUM> are loaded from the non-volatile memory <NUM>, segment by segment, by the non-volatile memory controller <NUM> into memory <NUM> for use by the processor <NUM>.

The dynamic port enable register <NUM> in memory <NUM> is read by the processor <NUM>. If the state of the bit in the dynamic port enable register <NUM> to select enabling delay of configuration of the Ethernet ports is "enable" (for example, bit <NUM> in the embodiment shown in <FIG> is set to logic '<NUM>'), processing continues with block <NUM>. If not, processing continues with block <NUM>.

At block <NUM>, the port numbers are read from the dynamic port enable register <NUM>. In an embodiment with four Ethernet ports, one to four ports can be selected through the use of four bits, with each of the respective bits assigned to one of the four Ethernet ports. The Ethernet link for the selected port(s) will not be established until the required delay time is reached. Processing continues with block <NUM>.

At block <NUM>, the delay time to be used for the selected port(s) is read from the dynamic port enable register <NUM>.

At block <NUM>, the link enable delay timer is preset with the delay time and is enabled (started). Processing continues with block <NUM>.

At block <NUM>, the processor <NUM> and host interface circuitry <NUM> are initialized. Processing continues with block <NUM>.

At block <NUM>, the link enable delay timer is read. If the delay time has expired (is complete), processing continues with block <NUM>. If not, the link enable delay timer is periodically checked until the delay time has expired and both the media access control layer circuitry <NUM> and the PHY layer circuitry <NUM> for the Ethernet port are not enabled. The PHY layer circuitry <NUM> does not advertise PHY capabilities on the Ethernet link while it is disabled. The media access control layer circuitry <NUM> does not send or receive packets while it is disabled.

At block <NUM>, the media access control layer circuitry <NUM> and PHY layer circuitry <NUM> are initialized and configured to configure the Ethernet port and establish an Ethernet link.

<FIG> is a block diagram of an embodiment of a server <NUM> in a cloud computing system that includes the network interface controller <NUM> to delay configuring the Ethernet link after a power on reset to allow sufficient time for completion of the configuration of the NIC <NUM> for post-boot operation.

Server <NUM> includes a system on chip (SOC or SoC) <NUM> which combines processor, graphics, memory, and Input/Output (I/O) control logic into one SoC package. The I/O adapters <NUM> may include a Peripheral Component Interconnect Express (PCIe) adapter that is communicatively coupled over bus <NUM> to the NIC102.

The SoC <NUM> includes at least one Central Processing Unit (CPU) module <NUM>, a memory controller <NUM>, and a Graphics Processor Unit (GPU) module <NUM>. In other embodiments, the memory controller <NUM> may be external to the SoC <NUM>. The CPU module <NUM> includes at least one processor core <NUM> and a level <NUM> (L2) cache <NUM>.

Although not shown, the processor core <NUM> may internally include one or more instruction/data caches (L1 cache), execution units, prefetch buffers, instruction queues, branch address calculation units, instruction decoders, floating point units, retirement units, etc. The CPU module <NUM> may correspond to a single core or a multi-core general purpose processor, such as those provided by Intel® Corporation, according to one embodiment. In an embodiment the SoC <NUM> may be a standalone CPU such as an Intel® Xeon® Scalable Processor (SP), an Intel® Xeon® data center (D) SoC, or a smart NIC accelerator card format.

The memory controller <NUM> may be coupled to a persistent memory module <NUM> having at least one persistent memory integrated circuit and a volatile memory module <NUM> having at least one volatile memory integrated circuit via a memory bus <NUM>.

A non-volatile memory (NVM) device is a memory whose state is determinate even if power is interrupted to the device. In one embodiment, the NVM device can comprise a block addressable memory device, such as NAND technologies, or more specifically, multi-threshold level NAND flash memory (for example, Single-Level Cell ("SLC"), Multi-Level Cell ("MLC"), Tri-Level Cell ("TLC"), Quad-Level Cell ("QLC"), Penta-Level Cell (PLC) or some other NAND). A NVM device can also include a byte-addressable, write-in-place three dimensional Crosspoint memory device, or other byte addressable write-in-place NVM devices (also referred to as persistent memory), such as single or multi-level Phase Change Memory (PCM) or phase change memory with a switch (PCMS), NVM devices that use chalcogenide phase change material (for example, chalcogenide glass), resistive memory including metal oxide base, oxygen vacancy base and Conductive Bridge Random Access Memory (CB-RAM), nanowire memory, ferroelectric random access memory (FeRAM, FRAM), magneto resistive random access memory (MRAM) that incorporates memristor technology, spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory.

Volatile memory is memory whose state (and therefore the data stored in it) is indeterminate if power is interrupted to the device. Dynamic volatile memory requires refreshing the data stored in the device to maintain state. One example of dynamic volatile memory incudes DRAM (Dynamic Random Access Memory), or some variant such as Synchronous DRAM (SDRAM). A memory subsystem as described herein may be compatible with a number of memory technologies, such as DDR3 (Double Data Rate version <NUM>, original release by JEDEC (Joint Electronic Device Engineering Council) on June <NUM>, <NUM>). DDR4 (DDR version <NUM>, originally published in September <NUM> by JEDEC), DDR5 (DDR version <NUM>, originally published in July <NUM>), LPDDR3 (Low Power DDR version <NUM>, JESD209-3B, August <NUM> by JEDEC), LPDDR4 (LPDDR version <NUM>, JESD209-<NUM>, originally published by JEDEC in August <NUM>), LPDDR5 (LPDDR version <NUM>, JESD209-5A, originally published by JEDEC in January <NUM>), WIO2 (Wide Input/Output version <NUM>, JESD229-<NUM> originally published by JEDEC in August <NUM>), HBM (High Bandwidth Memory, JESD235, originally published by JEDEC in October <NUM>), HBM2 (HBM version <NUM>, JESD235C, originally published by JEDEC in January <NUM>), or HBM3 (HBM version <NUM> currently in discussion by JEDEC), or others or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications. The JEDEC standards are available at www.

The Graphics Processor Unit (GPU) module <NUM> may include one or more GPU cores and a GPU cache which may store graphics related data for the GPU core. The GPU core may internally include one or more execution units and one or more instruction and data caches. Additionally, the Graphics Processor Unit (GPU) module <NUM> may contain other graphics logic units that are not shown in <FIG>, such as one or more vertex processing units, rasterization units, media processing units, and codecs.

Within the I/O subsystem <NUM>, one or more I/O adapter(s) <NUM> are present to translate a host communication protocol utilized within the processor core(s) <NUM> to a protocol compatible with particular I/O devices. Some of the protocols that I/O adapter(s) <NUM> may be utilized for translation include Peripheral Component Interconnect (PCI)-Express (PCIe); Universal Serial Bus (USB); Serial Advanced Technology Attachment (SATA) and Institute of Electrical and Electronics Engineers (IEEE) <NUM> "Firewire".

The I/O adapter(s) <NUM> may communicate with external I/O devices <NUM> which may include, for example, user interface device(s) including a display and/or a touch-screen display <NUM>, printer, keypad, keyboard, communication logic, wired and/or wireless, storage device(s) including hard disk drives ("HDD"), solid-state drives ("SSD"), removable storage media, Digital Video Disk (DVD) drive, Compact Disk (CD) drive, Redundant Array of Independent Disks (RAID), tape drive or other storage device. The storage devices may be communicatively and/or physically coupled together through one or more buses using one or more of a variety of protocols including, but not limited to, SAS (Serial Attached SCSI (Small Computer System Interface)), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express) over PCIe (Peripheral Component Interconnect Express), and SATA (Serial ATA (Advanced Technology Attachment)).

Additionally, there may be one or more wireless protocol I/O adapters. Examples of wireless protocols, among others, are used in personal area networks, such as IEEE <NUM> and Bluetooth, <NUM>; wireless local area networks, such as IEEE <NUM>-based wireless protocols; and cellular protocols.

Flow diagrams as illustrated herein provide examples of sequences of various process actions. The flow diagrams can indicate operations to be executed by a software or firmware routine, as well as physical operations. In one embodiment, a flow diagram can illustrate the state of a finite state machine (FSM), which can be implemented in hardware and/or software. Although shown in a particular sequence or order, unless otherwise specified, the order of the actions can be modified. Thus, the illustrated embodiments should be understood only as an example, and the process can be performed in a different order, and some actions can be performed in parallel. Additionally, one or more actions can be omitted in various embodiments; thus, not all actions are required in every embodiment. Other process flows are possible.

To the extent various operations or functions are described herein, they can be described or defined as software code, instructions, configuration, and/or data. The content can be directly executable ("object" or "executable" form), source code, or difference code ("delta" or "patch" code). The software content of the embodiments described herein can be provided via an article of manufacture with the content stored thereon, or via a method of operating a communication interface to send data via the communication interface. A non-transitory machine-readable storage medium can cause a machine to perform the functions or operations described, and includes any mechanism that stores information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any of a hardwired, wireless, optical, etc., medium to communicate to another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and/or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface.

Various components described herein can be a means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. The components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., application specific hardware such as Intel® QuickAssist Technology, application specific integrated circuits (ASICs), digital signal processors (DSPs), programmable acceleration such as field-programmable gate arrays (FPGAs), etc.), embedded controllers, hardwired circuitry, etc..

Besides what is described herein, various modifications can be made to the disclosed embodiments and implementations of the invention without departing from their scope.

Claim 1:
A network interface controller (<NUM>) comprising:
at least one Ethernet port configured to provide an Ethernet link, and is arranged to include:
a physical, PHY, layer circuitry (<NUM>); and
a Media Access Controller (<NUM>), the Media Access Controller configured to be associated with the PHY layer circuitry; and
one or more non-transitory machine-readable storage media (<NUM>) comprising a plurality of instructions stored thereon that, which when executed, cause the network interface controller to:
in response to detecting a power on reset signal, initialize a timer with a delay time for the at least one Ethernet port to delay configuration of the PHY layer circuitry and the Media Access Controller for a duration corresponding to the delay time after detecting the power on reset signal to thereby delay establishment of the Ethernet link, wherein the PHY layer circuitry and the Media Access Controller are disabled during the delay time; and
in response to expiration of the delay time, configure the PHY layer circuitry and the Media Access Controller to enable the at least one Ethernet port for establishing the Ethernet link.