Patent Description:
Known back-illuminated semiconductor photodetectors that include a semiconductor substrate including a first main surface and a second main surface opposing each other (see Patent Literatures <NUM> and <NUM>, for example). In a back-illuminated semiconductor photodetector described in Patent Literature <NUM>, a semiconductor substrate includes a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type. The semiconductor substrate includes the plurality of second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions constitutes a pn junction with the first semiconductor region. The first main surface is a light incident surface of the semiconductor substrate. The plurality of second semiconductor regions include a textured surface.

An object of one aspect of the present invention is to provide a back-illuminated semiconductor photodetector that further improves spectral sensitivity characteristics in a long wavelength range. For example, the long wavelength range includes a near infrared wavelength range.

A back-illuminated semiconductor photodetector according to one aspect of the present invention includes a semiconductor substrate including a first main surface and a second main surface opposing each other. The first main surface is a light incident surface of the semiconductor substrate. The semiconductor substrate includes a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions of a second conductivity type. The plurality of second semiconductor regions are provided in a side of the second main surface, and constitute pn junctions with the first semiconductor region. Each of the plurality of second semiconductor regions includes a first region including a textured surface, and a second region including no textured surface. A thickness of the first region at a deepest position of recesses of the textured surface is smaller than a distance between a surface of the second region and the deepest position in a thickness direction of the semiconductor substrate.

In the back-illuminated semiconductor photodetector according to the one aspect, the first region of the second semiconductor region includes the textured surface. Light in a long wavelength range has a small absorption coefficient as compared with light in a short wavelength range. Therefore, light in a long wavelength range that is incident on the semiconductor substrate from the first main surface travels in the semiconductor substrate and reaches the textured surface. The light having reached the textured surface is reflected or diffused at the textured surface, and further travels in the semiconductor substrate. The light in the long wavelength range travels a long distance within the semiconductor substrate, and thus is absorbed by the semiconductor substrate. Consequently, the one aspect improves spectral sensitivity characteristics in the long wavelength range.

Carriers generated due to absorption of light by the semiconductor substrate may be recombined in the second semiconductor region. Carriers recombined in the second semiconductor region do not contribute to detection sensitivity. Therefore, the spectral sensitivity characteristics may deteriorate.

Recombination of carriers in the second semiconductor region tends to occur in a configuration where a thickness of the second semiconductor region is large as compared with in a configuration where the thickness of the second semiconductor region is small. That is, recombination of carriers in the second semiconductor region tends to occur in a configuration where a distance between a surface of the second semiconductor region and the pn junction is long as compared with in a configuration where the distance between the surface of the second semiconductor region and the pn junction is short.

In the one aspect, a thickness of the first region at a deepest position of recesses of the textured surface is smaller than a distance between a surface of the second region and the deepest position in a thickness direction of the semiconductor substrate.

In the one aspect, a distance between the textured surface and the pn junction is smaller than that distance in a configuration where the thickness of the first region at the deepest position of the recesses of the textured surface is equal to or larger than the distance between the surface of the second region and the deepest position in the thickness direction of the semiconductor substrate. Therefore, recombination of carriers generated by light incident on the semiconductor substrate decreases in the second semiconductor region. Consequently, the one aspect further improves the spectral sensitivity characteristics in the long wavelength range.

In the one aspect, a thickness of the second region in the thickness direction of the semiconductor substrate may be larger than a thickness of the first region in the thickness direction of the semiconductor substrate.

In a case where stress acts on the semiconductor substrate, carriers that are not attributable to incidence of light may be generated. Carriers that are not attributable to incidence of light produce dark currents. Stress tends to act on the second region as compared with on the first region. Therefore, carriers that are not attributable to incidence of light tend to be generated in the second region as compared with in the first region. In the configuration where the thickness of the second region is larger than the thickness of the first region, recombination of carriers that are not attributable to incidence of light tends to occur in the second region as compared with in a configuration where the thickness of the second region is equal to or smaller than the thickness of the first region. Therefore, this configuration reduces generation of dark currents.

The one aspect may include an electrode disposed on the second region and in contact with the second region.

In this configuration, the electrode is in contact with the second region that has a larger thickness than the thickness of the first region in the thickness direction of the semiconductor substrate. In a case where the electrode and the semiconductor substrate are in contact with each other, a material forming the electrode and a material forming the semiconductor substrate are alloyed with each other, so that an alloy spike may be produced in the semiconductor substrate. The alloy spike having reached the pn junction increases leakage currents. In the configuration where the thickness of the second region is larger than the thickness of the first region, the alloy spike tends not to reach the pn junction as compared with in a configuration where the thickness of the second region is equal to or smaller than the thickness of the first region. Therefore, this configuration reduces an increase in leakage currents.

In the one aspect, the textured surface of the first region may be located toward the first main surface in comparison to the surface of the second region in the thickness direction of the semiconductor substrate.

In this case, stress tends not to act on the first region. Therefore, generation of carriers that are not attributable to incidence of light is reduced in the first region. Consequently, this configuration reduces generation of dark currents. According to the present configuration, the distance between the textured surface and the pn junction can be further reduced when the textured surface is formed in the second semiconductor region, for example. Therefore, the present configuration can further improve the spectral sensitivity characteristics in the long wavelength range.

In the one aspect, an edge region of the textured surface of the first region may be continuous with the surface of the second region, and may be inclined to the thickness direction of the semiconductor substrate.

In a case where the textured surface of the first region is located toward the first main surface in comparison to the surface of the second region in the thickness direction of the semiconductor substrate, stress tends to act on the second region further. In the configuration where the edge region of the textured surface of the first region is inclined to the thickness direction of the semiconductor substrate, stress acting on the second region tends to be dispersed as compared with in a configuration where the edge region of the textured surface of the first region is parallel to the thickness direction of the semiconductor substrate. Therefore, even in a case where stress acts on the second region, concentration of the stress on the second region decreases. This configuration reduces generation of carriers that are not attributable to incidence of light. Consequently, this configuration reduces generation of dark currents.

One aspect of the present invention provides a back-illuminated semiconductor photodetector that further improves spectral sensitivity characteristics in a long wavelength range.

Embodiments of the present invention will be hereinafter described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same functions, and redundant descriptions thereabout are omitted.

A configuration of a back-illuminated semiconductor photodetector <NUM> according to the present embodiment will be described with reference to <FIG>. <FIG> is a plan view of the back-illuminated semiconductor photodetector according to the present embodiment. <FIG> is a view illustrating a cross-sectional configuration of the back-illuminated semiconductor photodetector according to the present embodiment. <FIG> is a plan view illustrating a configuration of the back-illuminated semiconductor photodetector according to the present embodiment. Each of <FIG> and <FIG> is an SEM image of a textured surface observed. <FIG> is a view illustrating a cross-sectional configuration of one pixel. In <FIG>, hatching for indicating a cross section is omitted.

As illustrated in <FIG> and <FIG>, the semiconductor photodetector <NUM> includes a semiconductor substrate <NUM>. The semiconductor substrate <NUM> is a substrate made of silicon (Si). The semiconductor substrate <NUM> includes a main surface 11a and a main surface 11b opposing each other. The main surface 11a is a light incident surface of the semiconductor substrate <NUM>. The main surface 11a is a back surface, and the main surface 11b is a front surface. For example, the semiconductor substrate <NUM> has a polygonal shape in a plan view. In the present embodiment, the semiconductor substrate <NUM> has a rectangular shape in the plan view. For example, the semiconductor substrate <NUM> has a thickness of <NUM>. For example, a thickness direction of the semiconductor substrate <NUM> is a direction parallel to a Z axis. In the present embodiment, the thickness direction of the semiconductor substrate <NUM> coincides with a direction in which the main surface 11a and the main surface 11b oppose each other. The thickness direction of the semiconductor substrate <NUM> coincides with a direction orthogonal to the semiconductor substrate <NUM>, a direction orthogonal to the main surface 11a, and a direction orthogonal to the main surface 11b.

The semiconductor substrate <NUM> includes a semiconductor region <NUM> of a first conductivity type, a plurality of semiconductor regions <NUM> of a second conductivity type, and a semiconductor region <NUM> of the first conductivity type. The semiconductor substrate <NUM> includes the plurality of semiconductor regions <NUM> in a side of the main surface 11b. The semiconductor substrate <NUM> includes the plurality of semiconductor regions <NUM> provided in the side of the main surface 11b. The semiconductor substrate <NUM> includes the semiconductor region <NUM> in a side of the main surface 11a. The semiconductor substrate <NUM> includes the semiconductor region <NUM> provided in the side of the main surface 11a. The semiconductor region <NUM> functions as an accumulation layer. For example, the first conductivity type is n-type. For example, the second conductivity type is p-type. In a case of the semiconductor substrate <NUM> made of Si, p-type impurities include Group <NUM> elements, for example, and n-type impurities include Group <NUM> elements, for example. For example, the p-type impurities are boron (B). For example, the n-type impurities are nitrogen (N), phosphorus (P), or arsenic (As). The first conductivity type may be p-type, and the second conductivity type may be n-type.

The semiconductor region <NUM> has low impurity concentration. The semiconductor regions <NUM> and <NUM> have high impurity concentration. The semiconductor regions <NUM> and <NUM> have higher impurity concentration than that of the semiconductor region <NUM>. For example, the impurity concentration of the semiconductor region <NUM> is <NUM>×<NUM><NUM> cm-<NUM>. For example, the impurity concentration of the semiconductor region <NUM> is <NUM> × <NUM><NUM> cm-<NUM>. For example, the impurity concentration of the semiconductor region <NUM> is <NUM>×<NUM><NUM> cm-<NUM>. For example, the semiconductor region <NUM> has a maximum thickness of <NUM>. For example, the semiconductor region <NUM> has a thickness of <NUM>.

The plurality of semiconductor regions <NUM> are two-dimensionally distributed when viewed in a direction orthogonal to the semiconductor substrate <NUM>. In the present embodiment, the plurality of semiconductor regions <NUM> are distributed in a first direction and a second direction orthogonal to each other. The plurality of semiconductor regions <NUM> are distributed in M rows by N columns. Each of M and N is an integer of <NUM> or more. For example, the first direction is a direction parallel to an X axis. For example, the second direction is a direction parallel to a Y axis. For example, each of the semiconductor region <NUM> has a polygonal shape when viewed in the direction orthogonal to the semiconductor substrate <NUM>. In the present embodiment, each of the semiconductor regions <NUM> has a rectangular shape. Each of the semiconductor regions <NUM> may have a circular shape when viewed in the direction orthogonal to the semiconductor substrate <NUM>. In the present embodiment, the one semiconductor region <NUM> constitutes one pixel. The semiconductor photodetector <NUM> includes a plurality of pixels two-dimensionally distributed. The semiconductor region <NUM> and each of the semiconductor regions <NUM> constitute a pn junction. The pn junction is formed at a boundary between the semiconductor region <NUM> and each of the semiconductor regions <NUM>. In each pixel, a region including the semiconductor region <NUM> and the pn junction corresponds to a photosensitive region. The rectangular shape includes a shape with chamfered corners, and a shape with rounded corners.

The semiconductor substrate <NUM> includes a semiconductor region <NUM> of the first conductivity type. The semiconductor substrate <NUM> includes the semiconductor region <NUM> in the side of the main surface 11b. The semiconductor substrate <NUM> includes the semiconductor region <NUM> provided in the side of the main surface 11b. The semiconductor region <NUM> has a frame shape when viewed in the direction orthogonal to the main surface 11b. The semiconductor region <NUM> is provided along an edge of the main surface 11b in such a manner as to surround the region where the plurality of semiconductor regions <NUM> are distributed when viewed in the direction orthogonal to the main surface 11b. The semiconductor region <NUM> functions as a channel stop layer to stop a depletion layer before reaching a side surface of the semiconductor substrate <NUM>.

Each of the semiconductor regions <NUM> includes a region <NUM> including a textured surface TS, and a region <NUM> not including the textured surface TS. The textured surface TS is a surface that includes fine protrusions and recesses as illustrated in <FIG> and <FIG>. The region <NUM> is a region where fine protrusions and recesses are formed on the surface. The entire surface of the region <NUM> includes fine protrusions and recesses. The entire surface of the region <NUM> includes the textured surface TS. For example, the textured surface TS is formed with wet etching. The textured surface TS may be formed with dry etching or laser irradiation. The region that includes a surface constituted by the textured surface TS corresponds to a textured region. The textured surface TS illustrated in <FIG> is formed with wet etching. The textured surface TS illustrated in <FIG> is formed with dry etching. In <FIG>, the region corresponding to the textured surface TS is hatched to help easy understanding of the region constituted by the textured surface TS.

The protrusions and recesses of the textured surface TS are irregularly formed. The irregularity of the protrusions and recesses of the textured surface TS refers to at least either a state where intervals of tops of the protrusions and recesses irregularly change, or a state where height differences of the protrusions and recesses irregularly change. In the present embodiment, the intervals of the tops of the protrusions and recesses irregularly change, and also the height differences of the protrusions and recesses irregularly change. For example, an interval of the tops of the protrusions and recesses of the textured surface TS ranges from <NUM> to <NUM>. For example, a height difference of the protrusions and recesses of the textured surface TS ranges from <NUM> to <NUM>. The protrusions and recesses of the textured surface TS may be regularly formed.

As illustrated in <FIG>, the region <NUM> is located inside the region <NUM> when viewed in the direction orthogonal to the semiconductor substrate <NUM>. In the present embodiment, an entire edge of the region <NUM> is surrounded by the region <NUM> when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The region <NUM> includes a flat surface. The region <NUM> includes two regions 19a and 19b that are continuous with each other. The region 19a is located along the edge of the semiconductor region <NUM>. The region 19b is located at one corner of the semiconductor region <NUM>. The surface of the region 19a and the surface of the region 19b are located in the same plane. The region <NUM> has a shape produced by cutting out a rectangular portion from one corner of the rectangular shape when viewed in the direction orthogonal to the semiconductor substrate <NUM>. As illustrated in <FIG>, the region <NUM> and the region 19b are adjacent to each other in a direction crossing the first direction and the second direction when viewed in the direction orthogonal to the semiconductor substrate <NUM>.

As illustrated in <FIG>, a thickness TH1 of the region <NUM> at a deepest position of the recesses of the textured surface TS is smaller than a distance D1 between the surface of the region <NUM> (region 19b) and the deepest position in the thickness direction of the semiconductor substrate <NUM>. For example, the deepest position is a deepest position of a deepest recess in all of the recesses. The deepest position may be a deepest position of any one of all of the recesses. The deepest position may be an average position of the deepest positions of all of the recesses.

Impurity concentration of the semiconductor region <NUM> changes with a depth from the front surface as illustrated in <FIG>, for example. That is, the impurity concentration of the semiconductor region <NUM> changes with a distance from the main surface 11b in the thickness direction of the semiconductor substrate <NUM>, for example. <FIG> is a chart illustrating a distribution of the impurity concentration. The impurity concentration distribution illustrated in <FIG> is a distribution in a case where impurities are thermally diffused due to a following process. The semiconductor region <NUM> is formed, and subsequently the textured surface TS is formed. Thereafter, impurities are thermally diffused due to a high temperature heat treatment. This process will be described below as a manufacturing process of the semiconductor photodetector <NUM> according to the present embodiment.

The impurity concentration of the semiconductor region <NUM> is kept high up to a position of a predetermined depth, and gradually decreases from the position of the predetermined depth toward the main surface 11a. The semiconductor region <NUM> includes a region R1 that is located closer to the main surface 11b, and a region R2 that is located toward the main surface 11a in comparison to the region R1 is, on the basis of the distribution of the impurity concentration. The region R1 and the region R2 are continuous with each other. The region R1 is a high impurity concentration region. The region R2 is a transition region where the impurity concentration gradually decreases from the impurity concentration of the region R1. In the present embodiment, the predetermined depth is approximately <NUM>, for example.

In the present embodiment, the deepest position of the recesses of the textured surface TS is located near a boundary between the region R1 and the region R2. That is, the deepest position is located near a region where the impurity concentration of the semiconductor region <NUM> begins to decrease. In the region <NUM>, an occupancy of the region R2 is higher than an occupancy of the region R1. The region <NUM> may be constituted by only the region R2.

For example, a thickness of the semiconductor region <NUM> (regions <NUM> and <NUM>) is defined by a distance between the front surface and a depth at which the impurity concentration of the semiconductor region <NUM> becomes equal to the impurity concentration of the semiconductor region <NUM>. This distance also corresponds to the distance of the semiconductor substrate <NUM> in the thickness direction. In this case, the thickness TH1 is defined by a distance between the deepest position of the recesses of the textured surface TS and the depth at which the impurity concentration of the semiconductor region <NUM> becomes equal to the impurity concentration of the semiconductor region <NUM>. For example, the deepest position of the recesses is a deepest position of the deepest recess of all of the recesses. In this case, the thickness TH1 indicates a minimum value of the thickness of the region <NUM>. For example, the deepest position of the recesses may be a deepest position of the shallowest recess of all of the recesses. In this case, the thickness TH1 indicates a maximum value of the thickness of the region <NUM>. For example, the deepest position of the recesses may be an average position of the deepest positions of all the recesses. In this case, the thickness TH1 indicates an average value of the thickness of the region <NUM>. For example, the thickness TH1 ranges from <NUM> to <NUM>.

For example, the thickness of the semiconductor region <NUM> (regions <NUM> and <NUM>) may be defined by a distance between the front surface and a position where the region R2 ends in the thickness direction of the semiconductor substrate <NUM>. As can be seen from <FIG>, the position where the region R2 ends is a position where the decrease of the impurity concentration ends. In this case, the thickness TH1 is defined by a distance between the deepest position of the recesses of the textured surface TS and the position where the region R2 ends.

The distance D1 is a depth of the recesses of the textured surface TS. In a case where the deepest position is the deepest position of the deepest recess, the distance D1 is a maximum value of the depths of the recesses of the textured surface TS. In a case where the deepest position is the deepest position of the shallowest recess, the distance D1 is a minimum value of the depths of the recesses of the textured surface TS. In a case where the deepest position is the average position of the deepest positions of all the recesses, the distance D1 is an average depth of the recesses of the textured surface TS. For example, the distance D1 ranges from <NUM> to <NUM>.

A thickness TH2 of the region <NUM> (region 19b) in the thickness direction of the semiconductor substrate <NUM> is larger than a thickness TH3 of the region <NUM> in the thickness direction of the semiconductor substrate <NUM>. For example, the thickness TH2 is <NUM>. In the present embodiment, the thickness TH2 is also a maximum thickness of the semiconductor region <NUM>.

The thickness TH3 of the region <NUM> changes in correspondence with the protrusions and recesses of the textured surface TS. For example, the thickness TH3 is a thickness at the deepest position of the recesses of the textured surface TS. In this case, the thickness TH3 is equal to the thickness TH1. For example, the thickness TH3 may be the thickness at a top of the textured surface TS. For example, the top where the thickness TH3 is defined is a highest top of all the tops. The highest top is a top located closest to the main surface 11b in the thickness direction of the semiconductor substrate <NUM>. In this case, the thickness TH3 indicates a maximum thickness of the region <NUM>. For example, the top where the thickness TH3 is defined may be a lowest top of all the tops. The lowest top is a top located closest to the main surface 11a in the thickness direction of the semiconductor substrate <NUM>. For example, the thickness TH3 may be a distance between an average height position of the protrusions and recesses of the textured surface TS and the position where the region R2 ends. For example, the thickness TH3 ranges from <NUM> to <NUM>.

The textured surface TS is located toward the main surface 11a in comparison to the surface of the region <NUM> (regions 19a and 19b) in the thickness direction of the semiconductor substrate <NUM>. That is, the textured surface TS is located toward the main surface 11a in comparison to a virtual plane VP including the surface of the region <NUM> (regions 19a and 19b). The main surface 11b is recessed in the region <NUM>. A step is formed by the textured surface TS and the surface of the region <NUM>. An edge region TSa of the textured surface TS of the region <NUM> is continuous with the surface of the region <NUM> (regions 19a, 19b), and is inclined to the thickness direction of the semiconductor substrate <NUM>. In the present embodiment, the edge region TSa is inclined such that the thickness of the region <NUM> in the edge region TSa gradually increases from the region <NUM> toward the region <NUM>.

The semiconductor photodetector <NUM> includes a plurality of insulating films <NUM>, <NUM>, and <NUM>, a plurality of pad electrodes <NUM>, a plurality of UBMs (under-bump metals) <NUM>, and a plurality of bump electrodes <NUM>. In the present embodiment, the semiconductor photodetector <NUM> includes the one pad electrode <NUM>, the one UBM <NUM>, and the one bump electrode <NUM> for each of the semiconductor regions <NUM>. The semiconductor photodetector <NUM> includes an electrode (not illustrated) electrically connected to the semiconductor region <NUM>. The electrode electrically connected to the semiconductor region <NUM> is disposed on the side of the main surface 11b.

The insulating film <NUM> is disposed on the main surface 11a of the semiconductor substrate <NUM>. The insulating film <NUM> is formed on the main surface 11a. For example, the insulating film <NUM> is an oxide film. In the present embodiment, the insulating film <NUM> is made of silicon oxide (SiO<NUM>). For example, the insulating film <NUM> is a silicon thermal oxide film. The insulating film <NUM> may be made of silicon nitride (SiN). In this case, the insulating film <NUM> is formed with plasma CVD (Plasma-enhanced Chemical Vapor Deposition), for example. The insulating film <NUM> functions as an antireflective film. For example, the insulating film <NUM> has a thickness of <NUM>.

The insulating film <NUM> is disposed on the main surface 11b of the semiconductor substrate <NUM>. The insulating film <NUM> is formed on the main surface 11b. For example, the insulating film <NUM> is an oxide film. In the present embodiment, the insulating film <NUM> is made of silicon oxide. For example, the insulating film <NUM> is a silicon thermal oxide film. The insulating film <NUM> covers the surfaces of the respective semiconductor regions <NUM>. The insulating film <NUM> directly covers the entire textured surfaces TS. The insulating film <NUM> is in contact with the main surface 11b (textured surfaces TS). The insulating film <NUM> may be made of silicon nitride. In this case, the insulating film <NUM> is formed with low CVD (Low-pressure Chemical Vapor Deposition). The insulating film <NUM> may be made of aluminum oxide (Al<NUM>O<NUM>). In this case, the insulating film <NUM> is formed with ALD (Atomic Layer Deposition). For example, the insulating film <NUM> has a thickness of <NUM>.

The insulating film <NUM> is disposed on the main surface 11b of the semiconductor substrate <NUM>. The insulating film <NUM> is formed on the insulating film <NUM>. The insulating film <NUM> is in contact with the insulating film <NUM>. For example, the insulating film <NUM> is a nitride film. In the present embodiment, the insulating film <NUM> is made of silicon nitride. The insulating film <NUM> is located between the semiconductor substrate <NUM> and the insulating film <NUM>. The insulating film <NUM> is indirectly disposed on the semiconductor substrate <NUM>. The insulating film <NUM> indirectly covers the surfaces of the respective semiconductor regions <NUM>. The insulating film <NUM> directly covers a region included in the insulating film <NUM> and corresponding to the regions <NUM>. The insulating film <NUM> indirectly covers the entire textured surfaces TS. The insulating film <NUM> may be made of silicon oxide. In this case, the insulating film <NUM> is formed with plasma CVD, for example. The insulating film <NUM> functions as a passivation film. For example, the insulating film <NUM> has a thickness ranging from <NUM> to <NUM>.

The pad electrode <NUM> is disposed on the region <NUM>. In the present embodiment, the pad electrode <NUM> is disposed on the region 19b. The pad electrode <NUM> is formed on the region 19b and the insulating film <NUM>. The pad electrode <NUM> is connected to the region 19b via a contact hole H1 formed in the insulating film <NUM>. The pad electrode <NUM> is in contact with the region <NUM> and the insulating film <NUM>. The pad electrode <NUM> is directly disposed on the region 19b. The pad electrode <NUM> is in contact with the insulating film <NUM>. The insulating film <NUM> covers peripheral edges of the pad electrodes <NUM>. The pad electrode <NUM> is made of a conductive material. For example, the pad electrode <NUM> is made of aluminum (Al). In this case, the pad electrode <NUM> is formed with sputtering or vapor deposition.

As illustrated in <FIG>, the pad electrode <NUM> includes two electrode regions 31a and 31b. In the present embodiment, the pad electrode <NUM> is constituted by the two electrode regions 31a and 31b. The electrode region 31a is disposed on the region <NUM>. In the present embodiment, the electrode region 31a is disposed on the region 19b. The electrode region 31a is in contact with the region 19b. The electrode region 31a is directly disposed on the region 19b. The electrode region 31b is disposed on at least a part of a region included in the insulating film <NUM> and corresponding to the region <NUM>. The electrode region 31b is disposed on the region <NUM> such that the insulating film <NUM> is located between the region <NUM> and the electrode region 31b. The electrode region 31b is continuous with the electrode region 31a. The pad electrode <NUM> overlaps with an entire boundary between the region <NUM> and the region 19b when viewed in the direction orthogonal to the semiconductor substrate <NUM>. In the present embodiment, the electrode region 31b overlaps with the edge region TSa that is continuous with the region 19b when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The electrode region 31b is indirectly disposed on the edge region TSa. <FIG> does not illustrate the insulating films <NUM> and <NUM>.

The UBM <NUM> is disposed on the region <NUM>. In the present embodiment, the UBM <NUM> is disposed on the region 19b. The UBM <NUM> is formed on the region 19b and the insulating film <NUM>. The UBM <NUM> is connected to the pad electrode <NUM> via a contact hole H2 formed in the insulating film <NUM>. The UBM <NUM> is in contact with the pad electrode <NUM>. The UBM <NUM> is in contact with the insulating film <NUM>. The UBM <NUM> is made of a material having excellent electrical and physical connection with the bump electrodes <NUM>. For example, the UBM <NUM> is a laminated body constituted by a layer made of titanium (Ti) and a layer made of platinum (Pt). For example, the UBM <NUM> is formed with multilayer vapor deposition.

The bump electrode <NUM> is disposed on the region <NUM>. In the present embodiment, the bump electrode <NUM> is disposed on the region 19b. The bump electrode <NUM> is formed on the UBM <NUM>. The bump electrode <NUM> is in contact with the UBM <NUM>. The UBM <NUM> is located between the pad electrode <NUM> and the bump electrode <NUM>. The bump electrode <NUM> is indirectly disposed on the region <NUM>. The bump electrode <NUM> is indirectly disposed on the pad electrode <NUM>. The bump electrode <NUM> is electrically connected to the region 19b (semiconductor region <NUM>) via the UBM <NUM> and the pad electrode <NUM>. The bump electrode <NUM> is made of a solder material. For example, the bump electrode <NUM> is made of indium (In). For example, the bump electrode <NUM> is formed with vapor deposition.

In the semiconductor photodetector <NUM>, the semiconductor region <NUM> is completely depleted due to applying a bias voltage. That is, a depletion layer extending from the semiconductor region <NUM> reaches the semiconductor region <NUM>. The semiconductor region <NUM> need not be completely depleted.

Next, an example of a manufacturing process of the semiconductor photodetector <NUM> will be described with reference to <FIG>. Each of <FIG> is a schematic diagram illustrating an example of the manufacturing process of the back-illuminated semiconductor photodetector according to the present embodiment. In <FIG>, hatching for indicating a cross section is omitted.

As illustrated in <FIG>, the n-type semiconductor substrate <NUM> is provided. An oxide film <NUM> is formed on the main surface 11a, while an oxide film <NUM> is formed on main surface 11b. For example, the oxide films <NUM> and <NUM> are formed due to heating the semiconductor substrate <NUM> in an oxygen atmosphere. In a state illustrated in <FIG>, the semiconductor substrate <NUM> is constituted by the semiconductor region <NUM>, and does not include the semiconductor regions <NUM> and the semiconductor region <NUM>.

As illustrated in <FIG>, the plurality of semiconductor regions <NUM> and the semiconductor region <NUM> are formed on the semiconductor substrate <NUM>. By employing this process, the semiconductor substrate <NUM> including the semiconductor region <NUM>, the plurality of semiconductor regions <NUM>, and the semiconductor region <NUM> is provided.

The semiconductor regions <NUM> are formed in a following manner. Openings 53a are formed in the oxide film <NUM> due to patterning the oxide film <NUM>. The openings 53a have a rectangular shape. P-type impurities are doped to the semiconductor substrate <NUM> from the main surface 11b via the opening 53a of the oxide film <NUM>. The doped p-type impurities diffuse into the semiconductor substrate <NUM> due to a high temperature heat treatment. The semiconductor regions <NUM> are constituted by the high-concentration p-type impurities diffused from the main surface 11b. An oxide film <NUM> is formed on the semiconductor region <NUM> due to the above high temperature heat treatment (see <FIG>).

The semiconductor region <NUM> is formed in a following manner. N-type impurities are doped to the semiconductor substrate <NUM> from the main surface 11a. The doped n-type impurities diffuse into the semiconductor substrate <NUM> due to the above high temperature heat treatment. The semiconductor region <NUM> is constituted by the high-concentration n-type impurities diffused from the main surface 11a.

As illustrated in <FIG>, the contact holes H1 are formed in the oxide film <NUM> due to patterning the oxide film <NUM>. After the contact holes H1 are formed, a silicon nitride film <NUM> is formed on the oxide films <NUM> and <NUM>. The silicon nitride film <NUM> is formed with low pressure CVD, for example.

As illustrated in <FIG>, the silicon nitride film <NUM> formed on the oxide film <NUM>, and the oxide film <NUM> are patterned, and the opening <NUM> is formed in the semiconductor region <NUM> at a position corresponding to the region <NUM>. The opening <NUM> is formed with dry etching, for example.

As illustrated in <FIG>, the textured surface TS is formed in a region included in the semiconductor region <NUM> and exposed through the opening <NUM>. For example, the textured surface TS is formed with wet etching as described above. In <FIG> and subsequent figures, a cross-hatched region indicates a region where the textured surface TS is formed.

As illustrated in <FIG>, an oxide film <NUM> is formed in the region included in the semiconductor region <NUM> and exposed through the opening <NUM>. The oxide film <NUM> is formed on the textured surface TS. For example, the oxide film <NUM> is formed due to heating the semiconductor substrate <NUM> in an oxygen atmosphere. The oxide films <NUM> and <NUM> constitute the insulating film <NUM>.

As illustrated in <FIG>, the silicon nitride film <NUM> is removed from the upper side of the oxide film <NUM> and the insulating film <NUM> (oxide films <NUM> and <NUM>). The semiconductor region <NUM> is exposed through the contact hole H1 due to removing the silicon nitride film <NUM>. Thereafter, the pad electrode <NUM> is formed on the region included in the semiconductor region <NUM> and exposed through the contact hole H1. The pad electrode <NUM> is also formed to be located on a region included in the insulating film <NUM> and located around the contact hole H1. The oxide film <NUM> constitutes the insulating film <NUM>.

After the insulating film <NUM> is formed on the insulating film <NUM>, the contact holes H2 are formed in the insulating film <NUM> due to patterning the insulating film <NUM> as illustrated in <FIG>. A part of the pad electrode <NUM> is exposed due to forming the contact hole H2.

As illustrated in <FIG>, the UBM <NUM> is formed on a region included in the pad electrode <NUM> and exposed through the contact hole H2. The UBM <NUM> is also formed to be located on a region included in the insulating film <NUM> and located around the contact hole H2. That is, the UBM <NUM> is also formed to be indirectly disposed on the region <NUM>. Thereafter, the bump electrode <NUM> is formed on the UBM <NUM>. The semiconductor photodetector <NUM> is obtained with these processes.

Next, a configuration of an electronic component device ED including the semiconductor photodetector <NUM> will be described with reference to <FIG> is a view illustrating a cross-sectional configuration of an electronic component device that includes the back-illuminated semiconductor photodetector according to the present embodiment.

The electronic component device ED includes the semiconductor photodetector <NUM>, an electronic component EC on which the semiconductor photodetector <NUM> is mounted, and a resin layer RL. For example, the electronic component EC includes a wiring board or an ASIC (Application Specific Integrated Circuit).

The electronic component EC includes a plurality of pad electrodes <NUM>, a plurality of UBMs <NUM>, and a plurality of bump electrodes <NUM>. The plurality of pad electrodes <NUM>, the plurality of UBMs <NUM>, and the plurality of bump electrodes <NUM> are disposed at positions corresponding to the plurality of bump electrodes <NUM> included in the semiconductor photodetector <NUM>. The semiconductor photodetector <NUM> is mounted on the electronic component EC due to joining the bump electrodes <NUM> and the bump electrodes <NUM> associated with each other. The electrode electrically connected to the semiconductor region <NUM> is also joined to a bump electrode (not illustrated) of the electronic component EC.

The resin layer RL is disposed between the semiconductor photodetector <NUM> and the electronic component EC. The resin layer RL functions as an underfill layer. The resin layer RL is produced due to curing a resin material filled in a space formed between the semiconductor photodetector <NUM> and the electronic component EC. For example, the resin layer RL contains epoxy resin, urethane resin, silicone resin, or acrylic resin.

As described above, in the semiconductor photodetector <NUM>, the region <NUM> of the semiconductor region <NUM> includes the textured surface TS. Light in a long wavelength range has a small absorption coefficient as compared with light in a short wavelength range. Therefore, light in a long wavelength range that is incident on the semiconductor substrate <NUM> from the main surface 11a travels in the semiconductor substrate <NUM> and reaches the textured surface TS. The light having reached the textured surface TS is reflected or diffused at the textured surface TS, and further travels in the semiconductor substrate <NUM>. The light in the long wavelength range travels a long distance within the semiconductor substrate <NUM>, and thus is absorbed by the semiconductor substrate <NUM>. Consequently, the semiconductor photodetector <NUM> improves spectral sensitivity characteristics in the long wavelength range.

Carriers generated due to absorption of light by the semiconductor substrate <NUM> may be recombined in the semiconductor regions <NUM>. Carriers recombined in the semiconductor regions <NUM> do not contribute to detection sensitivity. Therefore, the spectral sensitivity characteristics may deteriorate. In a configuration where the semiconductor region <NUM> has a large thickness, recombination of carriers in the semiconductor regions <NUM> tends to occur as compared with in a configuration where the semiconductor region <NUM> has a small thickness. That is, in a configuration where a distance between the surface of the semiconductor region <NUM> and the pn junction is long, recombination of carriers in the semiconductor regions <NUM> tends to occur as compared with in a configuration where the distance between the surface of the semiconductor region <NUM> and the pn junction is short.

In the semiconductor photodetector <NUM>, the thickness TH1 is smaller than the distance D1. In the semiconductor photodetector <NUM>, the distance between the textured surface TS and the pn junction is short as compared with in a configuration where the thickness TH1 is equal to or larger than the distance D1. Therefore, recombination of carriers generated by light incident on the semiconductor substrate <NUM> decreases in the semiconductor regions <NUM>. Consequently, the semiconductor photodetector <NUM> further improves the spectral sensitivity characteristics in the long wavelength range.

In the manufacturing process described above, the plurality of semiconductor regions <NUM> are formed in a plurality of planned regions before the textured regions (textured surfaces TS) are formed on the main surface 11b. In the process where the textured region is formed after forming the plurality of semiconductor regions <NUM>, it is necessary to reliably prevent the textured region from reaching the pn junction. It is considered that increasing a thickness of each of the semiconductor regions <NUM> reliably prevents the textured region from reaching the pn junction. However, in a configuration including the semiconductor regions <NUM> each having a large thickness, improvement of the spectral sensitivity characteristics may be inhibited.

The manufacturing process of the semiconductor photodetector <NUM> includes the process of forming the textured regions after the plurality of semiconductor regions <NUM> are formed. However, in the semiconductor photodetector <NUM>, the thickness TH1 is smaller than the distance D1. Therefore, improvement of the spectral sensitivity characteristics of the semiconductor photodetector <NUM> tends not to be inhibited.

In a case where stress acts on the semiconductor substrate <NUM>, carriers that are not attributable to incidence of light may be generated. Carriers that are not attributable to incidence of light produce dark currents. Stress tends to act on the region <NUM> as compared with on the region <NUM>, and therefore carriers that are not attributable to incidence of light tends to be generated in the region <NUM>.

In the semiconductor photodetector <NUM>, the thickness TH2 is larger than the thickness TH3. In the semiconductor photodetector <NUM>, therefore, recombination of carriers that are not attributable to incidence of light tends to be caused in the region <NUM> as compared with a configuration where the thickness TH2 is equal to or smaller than the thickness TH3. Consequently, the semiconductor photodetector <NUM> reduces generation of the dark currents.

In the semiconductor photodetector <NUM>, the pad electrode <NUM> is in contact with the region <NUM> (region 19b). In a case where the pad electrodes <NUM> and the semiconductor substrate <NUM> are in contact with each other, a material (Al) forming the pad electrodes <NUM> and a material (Si) forming the semiconductor substrate <NUM> are alloyed with each other, so that an alloy spike may be produced in the semiconductor substrate <NUM>. The alloy spike having reached the pn junction increases leakage currents.

In the semiconductor photodetector <NUM>, the thickness TH2 is larger than the thickness TH3. Therefore, in the semiconductor photodetector <NUM>, the alloy spike tends not to reach the pn junction as compared with in a configuration where the thickness TH2 is equal to or smaller than the thickness TH3. The semiconductor photodetector <NUM> reduces an increase in leakage currents.

In the semiconductor photodetector <NUM>, the textured surface TS is located toward the main surface 11a in comparison to the surface of the region <NUM> in the thickness direction of the semiconductor substrate <NUM>. That is, the textured surface TS is located toward the main surface 11a in comparison to the virtual plane VP. In this case, stress tends not to act on the region <NUM>. Therefore, generation of carriers that are not attributable to incidence of light is reduced in the region <NUM>. Consequently, the semiconductor photodetector <NUM> reduces generation of the dark currents.

In the semiconductor photodetector <NUM>, the distance between the textured surface TS and the pn junction further decreases in a case where the textured surface TS is formed in the semiconductor region <NUM> as in the manufacturing process described above. Therefore, the semiconductor photodetector <NUM> further improves the spectral sensitivity characteristics in the long wavelength range.

The semiconductor photodetector <NUM> is mounted on the electronic component EC via the bump electrode <NUM>. Therefore, stress acts on the region <NUM> (region 19b) when the semiconductor photodetector <NUM> is mounted on the electronic component EC. Since the textured surface TS is located toward the main surface 11a in comparison to the virtual plane VP, stress tends not to act on the region <NUM> even in a case where the semiconductor photodetector <NUM> is mounted on the electronic component EC. Therefore, generation of carriers that are not attributable to incidence of light is reduced in the region <NUM>. The semiconductor photodetector <NUM> further reduces generation of the dark currents.

If the bump electrode <NUM> (or the bump electrode <NUM>) is crushed at the time when the semiconductor photodetector <NUM> is mounted on the electronic component EC, the crushed bump electrode <NUM> (or the bump electrode <NUM>) may physically interfere with a portion of the semiconductor photodetector <NUM> other than the bump electrode <NUM>. For example, the portion other than the bump electrode <NUM> includes a wiring conductor or the textured surface TS. In a case where the bump electrode <NUM> (or the bump electrode <NUM>) physically interferes with the wiring conductor, the bump electrode <NUM> (or the bump electrode <NUM>) and the wiring conductor may be short-circuited. In a case where the bump electrode <NUM> (or the bump electrode <NUM>) physically interferes with the textured surface TS, the textured surface TS may be physically damaged, so that the spectral sensitivity characteristics in the long wavelength range may be adversely affected.

In the semiconductor photodetector <NUM>, the textured surface TS is located toward the main surface 11a in comparison to the virtual plane VP. The step is formed by the textured surface TS and the surface of the region <NUM>. Therefore, the crushed bump electrode <NUM> (or the bump electrode <NUM>) tends not to interfere with the portion of the semiconductor photodetector <NUM> other than the bump electrode <NUM> when the semiconductor photodetector <NUM> is mounted on the electronic component EC. The semiconductor photodetector <NUM> achieves reduction of generation of a short circuit between the bump electrodes <NUM> (or the bump electrodes <NUM>) and the wiring conductor, and reduction of adverse effects on the spectral sensitivity characteristics in the long wavelength range.

A device that forms the bump electrodes <NUM> may physically interfere with the textured surface TS when forming the bump electrodes <NUM>. In a case where the device that forms the bump electrodes <NUM> physically interferes with the textured surface TS, the textured surface TS may be physically damaged, so that the spectral sensitivity characteristics in the long wavelength range may be adversely affected.

In the semiconductor photodetector <NUM>, the textured surface TS is located toward the main surface 11a in comparison to the virtual plane VP. Therefore, the device that forms the bump electrodes <NUM> tends not to physically interfere with the textured surface TS. The semiconductor photodetector <NUM> reduces adverse effects on the spectral sensitivity characteristics in the long wavelength range when forming the bump electrodes <NUM>.

In the semiconductor photodetector <NUM>, the edge region TSa of the textured surface TS is continuous with the surface of the region <NUM> (regions 19a, 19b), and is inclined to the thickness direction of the semiconductor substrate <NUM>. In a case where the textured surface TS is located toward the main surface 11a in comparison to the virtual plane VP, stress tends to act on the region <NUM> further.

In the semiconductor photodetector <NUM>, the stress acting on the region <NUM> tends to be dispersed as compared with in a configuration where the edge region TSa is parallel to the thickness direction of the semiconductor substrate. Therefore, even in a case where stress acts on the region <NUM>, concentration of the stress on the region <NUM> decreases. The semiconductor photodetector <NUM> reduces generation of carriers that are not attributable to incidence of light. Consequently, the semiconductor photodetector <NUM> further reduces generation of the dark currents.

In the semiconductor photodetector <NUM>, the region <NUM> (regions 19a, 19b) does not include the textured surface TS. In the semiconductor photodetector <NUM>, the pad electrode <NUM> is easily formed on the region <NUM> (region 19b) as compared with in a configuration where the region <NUM> includes the textured surface TS.

Light having reached the surface of the textured surface TS is reflected or scattered by the textured surface TS as described above. The light reflected or scattered by the textured surface TS travels in various directions crossing the thickness direction of the semiconductor substrate <NUM> as compared with light reflected at a flat surface. Therefore, the light reflected or diffused at the textured surface TS may travel toward adjacent pixels and cause crosstalk between the pixels. Crosstalk causes noise.

In the semiconductor photodetector <NUM>, the textured surface TS is provided for each of the semiconductor regions <NUM>. The textured surface TS is not provided in regions of the main surface 11b other than the semiconductor regions <NUM>. The configuration where the textured surface TS is provided for each of the semiconductor regions <NUM> regulates generation of crosstalk as compared with a configuration where the textured surface TS is provided throughout the main surface 11b. Therefore, the semiconductor photodetector <NUM> reduces generation of crosstalk.

In the semiconductor photodetector <NUM>, the pad electrode <NUM> includes the electrode region 31a and the electrode region 31b. The electrode region 31a is disposed on the region <NUM> (region 19b). The electrode region 31b is disposed on the region <NUM> such that the insulating film <NUM> is located between the electrode region 31b and the region <NUM>. The electrode region 31a is continuous with the electrode region 31b. That is, the pad electrode <NUM> is disposed to extend over the region 19b and the region <NUM>. In this configuration, an area of the pad electrodes <NUM> is large as compared with in a configuration where the pad electrode <NUM> is disposed only on the region 19b. The UBM <NUM> and the bump electrode <NUM> are disposed on the pad electrode <NUM> having a large area. Therefore, the semiconductor photodetector <NUM> improves reliability and stability of an electrical connection between the semiconductor region <NUM> (region <NUM>) and the bump electrode <NUM>.

A configuration of the textured surface TS (region <NUM>) having a large area improves the spectral sensitivity characteristics in the long wavelength range as compared with a configuration of the textured surface TS (region <NUM>) having a small area. Therefore, to improve the spectral sensitivity characteristics in the long wavelength range, the region <NUM> having a largest possible area and the region <NUM> (region 19b) having a smallest possible area are required.

The pad electrode <NUM> contacts the region 19b via the contact hole H1. The contact hole H1 is formed in a region included in the insulating film <NUM> and located above the region 19b to easily form the contact hole H1. The contact hole H1 is easily formed in the insulating film <NUM> because the surface of the region 19b is flat. In a case where the pad electrode <NUM> is formed at a position shifted from the contact hole H1, the region 19b is exposed through the contact hole H1. In this case, breakdown voltage characteristics and reliability may deteriorate. Therefore, the area of the pad electrode <NUM> is set in consideration of accuracy of the formation position of the contact hole H1 and accuracy of the formation position of the pad electrode <NUM>. Consequently, the area of the pad electrode <NUM> inevitably increases.

In a configuration where the pad electrode <NUM> does not include the electrode region 31b, the pad electrodes <NUM> and the regions <NUM> do not overlap with each other when viewed in the direction orthogonal to the main surface 11b. In this configuration, an area of the region 19b needs to increase so as to secure the area of the pad electrode <NUM>, and the area of the region <NUM> is required to decrease. Therefore, the configuration where the pad electrode <NUM> does not include the electrode region 31b tends not to improve the spectral sensitivity characteristics in the long wavelength range.

In the semiconductor photodetector <NUM>, the pad electrode <NUM> includes the electrode region 31b. That is, at least a part of the pad electrodes <NUM> and a part of the regions <NUM> overlap with each other when viewed in the direction orthogonal to the main surface 11b. Therefore, even in a case where the areas of the pad electrodes <NUM> are secured, the semiconductor photodetector <NUM> improves the spectral sensitivity characteristics in the long wavelength range.

In the semiconductor photodetector <NUM>, the insulating film <NUM> covers the peripheral edges of the pad electrodes <NUM>. Therefore, the insulating film <NUM> reduces separation of the pad electrodes <NUM>. The insulating film <NUM> reduces entrance of a material component of the bump electrodes <NUM> from an interface between the pad electrodes <NUM> and the insulating film <NUM>. The insulating film <NUM> reduces generation of leakage currents and short circuit.

In the semiconductor photodetector <NUM>, the insulating film <NUM> covers a region included in the insulating film <NUM> and corresponding to the regions <NUM>. A laminated film constituted by the insulating film <NUM> and the insulating film <NUM> covers the entire textured surface TS. The laminated film (insulating films <NUM>, <NUM>) can constitute a highly reflective film in a case where thicknesses of the insulating film <NUM> and the insulating film <NUM> is set to desired values. In a configuration where a highly reflective film is constituted by the laminated film (insulating films <NUM>, <NUM>), the spectral sensitivity characteristics in the long wavelength range further improve.

The insulating film <NUM> is the oxide film, and the insulating film <NUM> is the nitride film. Therefore, the laminated film (insulating films <NUM>, <NUM>) can easily constitute the highly reflective film.

In a case where the insulating film <NUM> is the silicon thermal oxide film, the protrusions and recesses of the textured surface TS are smoothed due to the heat treatment in the process of forming the insulating film <NUM>. In a case where the protrusions and recesses of the textured surface TS are smoothed, a process of forming metal wiring including the pad electrodes <NUM> is easily performed.

Next, a configuration of the semiconductor photodetector <NUM> according to a first modification of the above embodiment will be described with reference to <FIG> and <FIG>. <FIG> is a view illustrating a cross-sectional configuration of a back-illuminated semiconductor photodetector according to the first modification. <FIG> is a plan view illustrating the configuration of the back-illuminated semiconductor photodetector according to the first modification. <FIG> does not illustrate the insulating films <NUM> and <NUM>. In <FIG>, a region corresponding to the textured surface TS is hatched to help easy understanding of a region constituted by the textured surface TS. The first modification is substantially similar or identical to the embodiment described above. However, the first modification is different from the above embodiment in the configuration of the semiconductor substrate <NUM>. Differences between the above embodiment and the first modification will be hereinafter chiefly described.

The semiconductor substrate <NUM> includes a semiconductor region <NUM> of the first conductivity type. The semiconductor substrate <NUM> includes the semiconductor region <NUM> in a side of the main surface 11b. The semiconductor substrate <NUM> includes the semiconductor region <NUM> provided in the side of the main surface 11b. The semiconductor region <NUM> has high impurity concentration. For example, the semiconductor region <NUM> has impurity concentration of <NUM>×<NUM><NUM> cm-<NUM>. For example, the semiconductor region <NUM> has a thickness of <NUM>. The semiconductor region <NUM> has a grid shape when viewed in the direction orthogonal to the main surface 11b. The semiconductor region <NUM> is located between the semiconductor regions <NUM> adjacent to each other in the first direction and between the semiconductor regions <NUM> adjacent to each other in the second direction when viewed in the direction orthogonal to the main surface 11b. The semiconductor region <NUM> is continuous with the semiconductor region <NUM>. The semiconductor region <NUM> functions as a channel stop layer, and reduces a spread of a depletion layer between pixels. The semiconductor region <NUM> may be divided into a plurality of regions when viewed in the direction orthogonal to the main surface 11b.

The semiconductor photodetector <NUM> includes a plurality of pad electrodes <NUM>, a plurality of UBMs (under-bump metals) <NUM>, and a plurality of bump electrodes <NUM>.

The respective pad electrodes <NUM> are disposed on the semiconductor region <NUM>. The respective pad electrodes <NUM> are disposed at predetermined intervals when viewed in the direction orthogonal to the main surface 11b. The pad electrode <NUM> is formed on the insulating film <NUM>. The pad electrode <NUM> is connected to the semiconductor region <NUM> via a contact hole formed in the insulating film <NUM>. The pad electrode <NUM> is in contact with the semiconductor region <NUM> and the insulating film <NUM>. The pad electrode <NUM> is directly disposed on the semiconductor region <NUM>. The pad electrode <NUM> is in contact with the insulating film <NUM>. The insulating film <NUM> covers peripheral edge of the pad electrode <NUM>. The pad electrode <NUM> is made of a conductive material. The pad electrode <NUM> is made of aluminum, for example. In this case, the pad electrode <NUM> is formed with sputtering or vapor deposition.

The UBM <NUM> is disposed on the semiconductor region <NUM>. The UBM <NUM> is formed on the semiconductor region <NUM> and the insulating film <NUM>. The UBM <NUM> is connected to the pad electrode <NUM> via a contact hole formed in the insulating film <NUM>. The UBM <NUM> is in contact with the pad electrode <NUM>. The UBM <NUM> is in contact with the insulating film <NUM>. The UBM <NUM> is made of a material having excellent electrical and physical connection with the bump electrode <NUM>. For example, the UBM <NUM> is constituted by a laminated body constituted by a layer made of titanium and a layer made of platinum. For example, the UBM <NUM> is formed with multilayer vapor deposition.

The bump electrode <NUM> is disposed on the semiconductor region <NUM>. The bump electrode <NUM> is formed on the UBM <NUM>. The bump electrode <NUM> is in contact with the UBM <NUM>. The UBM <NUM> is located between the pad electrode <NUM> and the bump electrode <NUM>. The bump electrode <NUM> is indirectly disposed on the semiconductor region <NUM>. The bump electrode <NUM> is indirectly disposed on the pad electrode <NUM>. The bump electrode <NUM> is electrically connected to the semiconductor region <NUM> via the UBM <NUM> and the pad electrode <NUM>. The bump electrode <NUM> is made of a solder material. For example, the bump electrode <NUM> is made of indium. For example, the bump electrode <NUM> is formed with vapor deposition.

Next, a configuration of the electronic component device ED including the semiconductor photodetector <NUM> according to the first modification will be described with reference to <FIG> is a view illustrating a cross-sectional configuration of the electronic component device that includes the back-illuminated semiconductor photodetector according to the first modification.

The electronic component device ED includes the semiconductor photodetector <NUM> according to the first modification, and the electronic component EC. The electronic component EC includes a plurality of pad electrodes <NUM>, a plurality of UBMs <NUM>, and a plurality of bump electrodes <NUM>. The plurality of pad electrodes <NUM>, the plurality of UBMs <NUM>, and the plurality of bump electrodes <NUM> are disposed at positions corresponding to the plurality of bump electrodes <NUM> and <NUM> included in the semiconductor photodetector <NUM>. The semiconductor photodetector <NUM> is mounted on the electronic component EC due to joining the bump electrodes <NUM> and <NUM> and the bump electrodes <NUM> associated with each other.

Next, a configuration of the semiconductor photodetector <NUM> according to a second modification of the above embodiment will be described with reference to <FIG> and <FIG>. <FIG> is a view illustrating a cross-sectional configuration of a back-illuminated semiconductor photodetector according to the second modification. <FIG> is a plan view illustrating the configuration of the back-illuminated semiconductor photodetector according to the second modification. <FIG> does not illustrate the insulating films <NUM> and <NUM>. In <FIG>, a region corresponding to the textured surface TS is hatched to help easy understanding of a region constituted by the textured surface TS. The second modification is substantially similar or identical to the embodiment described above. However, the second modification is different from the above embodiment in the configuration of the semiconductor substrate <NUM>. Differences between the above embodiment and the second modification will be hereinafter chiefly described.

A trench TR is formed in the semiconductor substrate <NUM> to separate the respective pixels from each other. The trench TR is opened in the main surface 11b. The trench TR is formed to divide the semiconductor region <NUM> when viewed in the direction orthogonal to the main surface 11b. The trench TR has a grid shape in such a manner as to pass between the semiconductor regions <NUM> adjacent to each other in the first direction, and between the semiconductor regions <NUM> adjacent to each other in the second direction when viewed in the direction orthogonal to the main surface 11b. For example, the opening of trench TR has a width of <NUM>. The trench TR has a depth larger than the thickness TH2. For example, the trench TR has a depth of <NUM>. For example, the trench TR is formed with reactive ion etching (RIE). The trench TR may be formed discontinuously when viewed in the direction orthogonal to main surface 11b. In this case, for example, a plurality of trenches extending in the first direction when viewed in the direction orthogonal to the main surface 11b, and a plurality of trenches extending in the second direction when viewed in the direction orthogonal to the main surface 11b are formed in the semiconductor substrate <NUM>.

The insulating film <NUM> is formed on an inner surface (specifically, side surface and bottom surface) of the trench TR. The insulating film <NUM> reaches the inside of the trench TR from the upper side of the main surface 11b. The insulating film <NUM> is formed on the insulating film <NUM> formed on the inner surface of the trench TR. The insulating film <NUM> extends from the upper side of the insulating film <NUM> located on the main surface 11b into the trench TR. A buried layer may be disposed in the trench TR. The buried layer is made of metal, for example. In this case, the buried layer (metal layer) is formed with CVD or electrolytic plating, for example.

The trench TR prevents light reflected or diffused at the textured surface TS from traveling toward an adjacent pixel. Therefore, the semiconductor photodetector <NUM> according to the second modification further reduces generation of crosstalk. The trench TR also prevents carriers from moving between adjacent pixels.

The semiconductor photodetector <NUM> according to the second modification may be mounted on the electronic component EC as illustrated in <FIG>. In this case, the electronic component device ED includes the semiconductor photodetector <NUM> according to the second modification, and the electronic component EC.

Next, a configuration of the semiconductor photodetector <NUM> according to a third modification of the above embodiment will be described with reference to <FIG> and <FIG>. <FIG> is a view illustrating a cross-sectional configuration of a back-illuminated semiconductor photodetector according to the third modification. <FIG> is a plan view illustrating a configuration of the back-illuminated semiconductor photodetector according to the third modification. <FIG> does not illustrate the insulating films <NUM> and <NUM>. In <FIG>, a region corresponding to the textured surface TS is hatched to help easy understanding of a region constituted by the textured surface TS. The third modification is substantially similar or identical to the embodiment described above. However, the third modification is different from the above embodiment in the configuration of the pad electrodes <NUM>. Differences between the above embodiment and the third modification will be hereinafter chiefly described.

The pad electrode <NUM> is disposed to cover the entire semiconductor region <NUM> when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The electrode region 31b is indirectly disposed on an entire region included in the insulating film <NUM> and corresponding to the region <NUM>. The electrode region 31b overlaps with the entire edge region TSa that is continuous with the region <NUM> (regions 19a, 19b) when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The pad electrode <NUM> overlaps with an entire boundary between the region <NUM> and the region <NUM> when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The pad electrode <NUM> is indirectly disposed on the entire semiconductor region <NUM>.

In a case where the pad electrodes <NUM> are made of Al, the pad electrodes <NUM> may absorb light having reached the pad electrodes <NUM> (for example, near infrared light). Absorption of light by the pad electrodes <NUM> deteriorates the spectral sensitivity characteristic in the long wavelength range.

In the semiconductor photodetector <NUM>, the insulating films <NUM> and <NUM> disposed on the textured surface TS reflect or diffuse the light having reached the insulating films <NUM> and <NUM>. Therefore, light transmitted through the insulating films <NUM> and <NUM> decreases. Consequently, the semiconductor photodetector <NUM> reduces deterioration of the spectral sensitivity characteristics in the long wavelength range.

Next, a configuration of the semiconductor photodetector <NUM> according to fourth and fifth modifications of the above embodiment will be described with reference to <FIG> and <FIG>. <FIG> is a plan view illustrating the configuration of a back-illuminated semiconductor photodetector according to the fourth modification. <FIG> is a plan view illustrating the configuration of a back-illuminated semiconductor photodetector according to the fifth modification. <FIG> and <FIG> do not illustrate the insulating films <NUM> and <NUM>. In <FIG> and <FIG>, a region corresponding to the textured surface TS is hatched to help easy understanding of a region constituted by the textured surface TS. The fourth and fifth modifications are substantially similar or identical to the embodiment described above. However, the fourth modification is different from the above embodiment in the configuration of the semiconductor regions <NUM>, and the fifth modification is different from the above embodiment in the configuration of the semiconductor regions <NUM> and the pad electrodes <NUM>. Differences between the above embodiment and the fourth and fifth modifications will be hereinafter chiefly described.

As illustrated in <FIG>, the region 19b is located at a center of the semiconductor region <NUM> when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The region 19b is separated from the region 19a. The region <NUM> (textured surface TS) is located between the region 19a and the region 19b when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The electrode region 31b overlaps with the entire edge region TSa that is continuous with the region 19b when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The pad electrode <NUM> overlaps with an entire boundary between the region <NUM> and the region 19b when viewed in the direction orthogonal to the semiconductor substrate <NUM>.

Similarly to the fourth modification, the region 19b is located at the center of the semiconductor region <NUM> when viewed in the direction orthogonal to the semiconductor substrate <NUM> as illustrated in <FIG>. Similarly to the third modification, the pad electrode <NUM> is disposed to cover the entire semiconductor region <NUM> when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The electrode region 31b overlaps with the entire edge region TSa that is continuous with the region 19a, and the entire edge region TSa that is continuous with the region 19b when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The pad electrode <NUM> overlaps with an entire boundary between the regions <NUM> and 19a, and an entire boundary between the regions <NUM> and 19b when viewed in the direction orthogonal to the semiconductor substrate <NUM>.

In the configuration where the region 19b is located at the center of the semiconductor region <NUM>, a carrier moving distance is short, and a time from incidence of light to output of a signal is short as compared with in a configuration where the region 19b is located at one corner of the semiconductor region <NUM>. Therefore, the semiconductor photodetector <NUM> increases a response speed in each of the fourth and fifth modifications.

Next, a configuration of a semiconductor photodetector according to a sixth modification of the above embodiment will be described with reference to <FIG> is a plan view illustrating a configuration of a back-illuminated semiconductor photodetector according to the sixth modification. <FIG> does not illustrate the insulating films <NUM> and <NUM>. In <FIG>, a region corresponding to the textured surface TS is hatched to help easy understanding of a region constituted by the textured surface TS. The sixth modification is substantially similar or identical to the embodiment described above. However, the sixth modification is different from the above embodiment in the configuration of the semiconductor regions <NUM> and the pad electrodes <NUM>. Differences between the above embodiment and the sixth modification will be hereinafter chiefly described.

The region <NUM> and the region 19b are adjacent to each other in the first direction when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The region <NUM> and the regions 19a and 19b has a rectangular shape when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The region 19b is located outside the region 19a. One side constituting an edge of the region 19a is in contact with one side constituting an edge of the region 19b. An area of the region 19b is smaller than an area of the region 19a when viewed in the direction orthogonal to the semiconductor substrate <NUM>. The pad electrode <NUM> is not located on the region <NUM> (textured surface TS). That is, the pad electrode <NUM> does not include the electrode region 31b. The pad electrode <NUM> does not overlap with the textured surface TS when viewed in the direction orthogonal to the semiconductor substrate <NUM>. In the sixth modification, the semiconductor substrate <NUM> includes the semiconductor region <NUM>. However, the semiconductor substrate <NUM> is not required to include the semiconductor region <NUM>. The region <NUM> and the region 19b may be adjacent to each other in the second direction when viewed in the direction orthogonal to the semiconductor substrate <NUM>.

Next, a configuration of the semiconductor photodetector <NUM> according to a seventh modification of the above embodiment will be described with reference to <FIG> and <FIG>. <FIG> is a view illustrating a cross-sectional configuration of a back-illuminated semiconductor photodetector according to the seventh modification. <FIG> is a view illustrating a cross-sectional configuration of one pixel. In <FIG>, hatching for indicating a cross section is omitted. The seventh modification is substantially similar or identical to the embodiment described above. However, the seventh modification is different from the above embodiment in the configuration of the semiconductor regions <NUM>. Differences between the above embodiment and the seventh modification will be hereinafter chiefly described.

The region <NUM> of the semiconductor region <NUM> is formed along the textured surface TS. A boundary interface between the region <NUM> and the semiconductor region <NUM> includes protrusions and recesses corresponding to the protrusions and recesses of the textured surface TS. For example, the boundary interface between the region <NUM> and the semiconductor region <NUM> includes protrusions and recesses that are more gradual than the protrusions and recesses of the textured surface TS. The region <NUM> of the semiconductor region <NUM> is formed along the main surface 11b. The thickness TH2 of the region <NUM> in the thickness direction of the semiconductor substrate <NUM> is equal to the thickness TH3 of the region <NUM> in the thickness direction of the semiconductor substrate <NUM>. As described above, the region <NUM> is formed along the textured surface TS. Therefore, the thickness TH3 tends not to change in correspondence with the protrusions and recesses of the textured surface TS. In the seventh modification, the thickness TH3 is approximately constant, for example. The thickness TH1 of the region <NUM> at the deepest position of the recesses of the textured surface TS is equal to each of the thickness TH2 and the thickness TH3. For example, the thickness TH1, the thickness TH2, and the thickness TH3 are <NUM>.

The semiconductor substrate <NUM> may include the semiconductor region <NUM> similarly to the first modification. The trench TR may be formed in the semiconductor substrate <NUM> similarly to the second modification. The pad electrodes <NUM> may be disposed to cover the entire semiconductor region <NUM> similarly to the third modification. The region 19b may be located at the center of the semiconductor region <NUM> when viewed in the direction orthogonal to the semiconductor substrate <NUM>, similarly to the fourth and fifth modifications. The region <NUM> and the region 19b may be adjacent to each other in the first direction or the second direction when viewed in the direction orthogonal to the semiconductor substrate <NUM>, similarly to the r sixth modification.

Next, an example of a manufacturing process of the semiconductor photodetector <NUM> according to the seventh modification will be described with reference to <FIG> and <FIG>. Each of <FIG> and <FIG> is a schematic diagram illustrating an example of the manufacturing process of the back-illuminated semiconductor photodetector according to the seventh modification. In <FIG> and <FIG>, hatching for indicating a cross section is omitted. Differences between the above embodiment and the seventh modification in the manufacturing process will be hereinafter chiefly described.

The semiconductor substrate <NUM> that includes the oxide film <NUM> on the main surface 11a and the oxide film <NUM> on the main surface 11b is provided (see <FIG>). That is, the semiconductor substrate <NUM> including the semiconductor region <NUM> is provided. The semiconductor substrate <NUM> includes a plurality of planned regions PR where the plurality of semiconductor regions <NUM> are going to be formed, in a side of the main surface 11b. In <FIG> and <FIG>, only one planned region PR is illustrated.

As illustrated in <FIG>, the plurality of semiconductor regions <NUM><NUM> and the semiconductor region <NUM> are formed on the semiconductor substrate <NUM>. Each of the semiconductor region <NUM><NUM> is formed in a corresponding planned region PR of the plurality of planned regions PR. The semiconductor regions <NUM><NUM> are formed with the same process as the process of forming the semiconductor regions <NUM> in the above embodiment. The semiconductor region <NUM><NUM> is constituted by high-concentration p-type impurities diffused from the main surface 11b. The semiconductor region <NUM> is formed with the same process as the process of forming the semiconductor region <NUM> in the above embodiment.

As illustrated in <FIG>, the contact hole H1, the silicon nitride film <NUM>, and the opening <NUM> are formed with the same processes as the corresponding forming processes of the above embodiment.

As illustrated in <FIG>, the textured surface TS is formed in a region included in the semiconductor region <NUM><NUM> and exposed through the opening <NUM> with the same processes as the corresponding forming processes of the above embodiment. That is, a plurality of textured regions are formed on surfaces included in the plurality of planned regions PR described above in the main surface 11b. The textured region is a region that includes a surface constituting the textured surface TS. The region included in the semiconductor region <NUM><NUM> and exposed from the opening <NUM> is removed due to forming the textured surface TS. The region included in the semiconductor region <NUM><NUM> and exposed from the opening <NUM> need not be completely removed, but a part of the region exposed through the opening <NUM> may be left. In <FIG> and subsequent figures, a cross-hatched region is a region where the textured surface TS is formed.

As illustrated in <FIG>, a plurality of semiconductor regions <NUM><NUM> are formed on the semiconductor substrate <NUM>. The semiconductor region <NUM><NUM> is formed along the textured surface TS. That is, the semiconductor regions <NUM><NUM> is formed along a surface shape of the textured region. Each of the semiconductor regions <NUM><NUM> is formed in the corresponding planned region PR of the plurality of planned regions PR. The semiconductor regions <NUM><NUM> are formed with the same process as the process of forming the semiconductor regions <NUM> in the above embodiment. The semiconductor regions <NUM><NUM> are constituted by high-concentration p-type impurities diffused from the main surface 11b. The p-type impurities also diffuse in the direction orthogonal to the thickness direction of the semiconductor substrate <NUM>. Therefore, the semiconductor region <NUM><NUM> is formed continuously with the semiconductor region <NUM><NUM>. The semiconductor region <NUM><NUM> and the semiconductor region <NUM><NUM> are integrated to constitute the semiconductor region <NUM>. The semiconductor region <NUM><NUM> constitutes the region <NUM>. The semiconductor region <NUM><NUM> constitutes the region <NUM>. That is, the plurality of semiconductor regions <NUM> are formed in the semiconductor substrate <NUM> with this process. The oxide film <NUM> is formed on the textured surface TS due to a high temperature heat treatment for forming the semiconductor regions <NUM><NUM> (see <FIG>). The oxide films <NUM> and <NUM> constitute the insulating film <NUM>.

As illustrated in <FIG>, the silicon nitride film <NUM> is removed from the oxide film <NUM> and the insulating film <NUM> (oxide films <NUM>, <NUM>). The semiconductor region <NUM> (semiconductor region <NUM><NUM>) is exposed through the contact holes H1 due to removing the silicon nitride film <NUM>. Thereafter, as illustrated in <FIG>, the pad electrode <NUM>, the insulating film <NUM>, the UBM <NUM>, and the bump electrode <NUM> are formed with the same processes as the corresponding forming processes of the above embodiment. The semiconductor photodetector <NUM> according to the seventh modification is obtained with these processes. The oxide film <NUM> constitutes the insulating film <NUM>.

For example, impurity concentration of the semiconductor regions <NUM><NUM> changes with a depth from the front surfaces as illustrated in <FIG>. That is, the impurity concentration of the semiconductor regions <NUM><NUM> changes with a distance from the textured surfaces TS in the thickness direction of the semiconductor substrate <NUM>, for example. <FIG> is a chart illustrating a distribution of the impurity concentration. <FIG> illustrates the textured surface TS and an interface between the semiconductor region <NUM><NUM> and the semiconductor region <NUM> flat, for convenience of illustration. Actually, however, the textured surface TS and the interface between the semiconductor region <NUM><NUM> and the semiconductor region <NUM> exhibit fine protrusions and recesses as described above.

The impurity concentration of the semiconductor regions <NUM><NUM> is also kept high up to a position of a predetermined depth, and gradually decreases from the position of the predetermined depth toward the main surface 11a. The semiconductor region <NUM><NUM> includes the region R1 and the region R2 on the basis of a distribution of impurity concentration. That is, in the seventh modification, the region <NUM> includes the region R1 and the region R2. In the semiconductor region <NUM><NUM> (region <NUM>), an occupancy of the region R2 is higher than an occupancy of the region R1. In the seventh modification, a deepest position of the recesses of the textured surface TS is separated from a region where the impurity concentration of the semiconductor regions <NUM> begins to decrease by a thickness of the region R1. In the seventh modification, the predetermined depth is approximately <NUM>, for example.

In the manufacturing process of the seventh modification, the plurality of semiconductor regions <NUM> (the plurality of semiconductor regions <NUM><NUM>) are formed in the plurality of planned regions PR after the textured region is formed on the main surface 11b. In a process where the textured regions (textured surfaces TS) are formed after forming the plurality of semiconductor regions <NUM>, the thickness of each of the semiconductor regions <NUM> inevitably increases to reliably prevent the texture regions from reaching the pn junctions. Therefore, in the process of forming the plurality of semiconductor regions <NUM> after forming the textured regions, each thickness of the semiconductor regions <NUM> can be reduced as compared with in the process of forming the textured regions after forming the plurality of semiconductor regions <NUM>. Consequently, the semiconductor photodetector <NUM> according to the seventh modification can further improve the spectral sensitivity characteristics in the long wavelength range.

In the manufacturing process of the seventh modification, the semiconductor region <NUM><NUM> (region <NUM>) is formed along the surface shape of the textured region. In this case, the thickness of the semiconductor region <NUM><NUM> (region <NUM>) can be further reduced. Therefore, the semiconductor photodetector <NUM> can further improve the spectral sensitivity characteristics in the long wavelength range with reliability.

In the manufacturing process of the seventh modification, the semiconductor regions <NUM><NUM> (regions <NUM>) are formed due to adding p-type impurities into the planned region PR. In this case, the semiconductor regions <NUM><NUM> are easily formed due to using an existing method.

Although the embodiment and the modifications of the present invention have been described, the present invention is not necessarily limited to the embodiment and the modifications described above, but may be modified in various ways without departing from the spirit of the present invention.

The textured surface TS is not required to be located toward the main surface 11a in comparison to the surface of the region <NUM> in the thickness direction of the semiconductor substrate <NUM>. That is, the textured surface TS is not required to be located toward the main surface 11a in comparison to the virtual plane VP. For example, the top of the textured surface TS may be located at the same position as the virtual plane VP. In a case where the textured surface TS is located toward the main surface 11a in comparison to the virtual plane VP, the semiconductor photodetector <NUM> reduces generation of the dark currents as described above.

The edge region TSa is not required to be continuous with the surface of the region <NUM>. For example, the edge region TSa may be separated from the step formed by the regions <NUM> and <NUM>. For example, a region not including the textured surface TS may be located between the edge region TSa and the step formed by the regions <NUM> and <NUM>. In this case, for example, the entire edge region TSa may be surrounded by the region not including the textured surface TS when viewed in the direction orthogonal to the semiconductor substrate <NUM>. For example, the region <NUM> may include a region not including the textured surface TS.

The edge region TSa may be approximately parallel to the thickness direction of the semiconductor substrate. In a case where the edge region TSa is inclined to the thickness direction of the semiconductor substrate <NUM>, the semiconductor photodetector <NUM> further decreases generation of the dark currents as described above.

The bump electrodes <NUM> may be directly disposed on the pad electrode <NUM>. In this case, the semiconductor photodetector <NUM> does not include the UBMs <NUM>.

Claim 1:
A back-illuminated semiconductor photodetector (<NUM>) comprising:
a semiconductor substrate (<NUM>) including a first main surface and a second main surface opposing each other, wherein
the semiconductor substrate includes a first semiconductor region (<NUM>) of a first conductivity type, and a plurality of second semiconductor regions (<NUM>) of a second conductivity type, the second semiconductor regions provided in a side of the second main surface and constituting pn junctions with the first semiconductor region,
each of the plurality of second semiconductor regions includes a first region including a textured surface(TS), and a second region, the thickness of the first region at the deepest position of recesses of the textured surface is smaller than the distance between the surface of the second region and the deepest position in a thickness direction of the semiconductor substrate,
the textured surface of the first region is located toward the first main surface in comparison to the surface of the second region in the thickness direction of the semiconductor substrate, and
the first main surface is a light incident surface of the semiconductor substrate.