Patent Description:
In the manufacturing of electronic components, the implementation of a circuit on a semiconductor wafer is referred to as a Front-End Process (FE), and the assembly of a wafer such that it can be actually used in a product is referred to as a Back-End Process (BE). A packaging process is included in the Back-End process.

Four key technologies of the semiconductor industry that enable the rapid development of electronic products in recent years include semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has been developed in various forms such as line width of a nanometer unit, which is smaller than a micrometer unit, <NUM> million or more cells, high-speed operation, and much heat dissipation, but technology of packaging it completely is not supported yet. Thus, the electrical performance of semiconductors may be determined by the packaging technology and the resulting electrical connection rather than the performance of the semiconductor itself.

Ceramic or resin is used as the material of a packaging substrate. In the case of a ceramic substrate such as Si substrate, it is not easy to mount a high-performance and high-frequency semiconductor element thereon due to a high resistance or high dielectric constant. In the case of a resin substrate, it is possible to mount a high-performance and high-frequency semiconductor element thereon, but there is a distinct limitation to the reduction of pitches of wirings.

Recently, research is being conducted to apply silicon or glass to a high-end packaging substrate. By forming a through-via on a silicon or glass substrate and applying a conductive material into the through-via, it is possible to shorten a length of conductive lines between an element and a motherboard, and have excellent electric characteristics.

As related art documents, there are, for example, <CIT>, <CIT>, and Korean Patent No. <NUM>-.

Further, <CIT> discloses an interposer capable of preventing breaking of a wiring pattern with an IC chip loaded on a package substrate. Stress due to a difference in thermal expansion coefficient between a multilayer printed wiring board having a large thermal expansion and the IC chip having a small thermal expansion can be absorbed by locating the interposer between the package substrate and the IC chip, wherein an insulation substrate whose Young's modulus is <NUM> to <NUM> Gpa is used as the insulation substrate constituting the interposer, and stress is absorbed within the interposer.

The objective of the present invention is to provide a packaging glass substrate for a semiconductor, a packaging substrate for a semiconductor, a semiconductor apparatus, and the like, which can be used to manufacture a more integrated semiconductor apparatus by applying a glass substrate of which stress is controlled and a semiconductor apparatus packaging substrate including the same, and the like.

To achieve the above objectives, a packaging glass substrate for a semiconductor according claim <NUM>, a packaging substrate for a semiconductor according to claim <NUM>, and a semiconductor apparatus according to claim <NUM> are provided.

According to a first aspect of the invention, a packaging glass substrate for a semiconductor includes a glass substrate with a first surface and a second surface facing each other; and a plurality of core via arranged in a grid pattern penetrating through the glass substrate in a thickness direction.

A plain line is a straight line parallel to a via line and linking places where the core via is not formed.

A via line is a straight line linking nearest places where the core via is formed.

A stress difference value P is a value according to the below Equation (<NUM>).

A stress difference value P of a packaging glass substrate for semiconductor is <NUM> MPa or less.

The core via may be disposed in the number of <NUM> to <NUM>, based on a unit area (<NUM> x <NUM>) of the glass substrate.

A stress difference ratio K is a value according to the below Equation (<NUM>).

A glass substrate for packaging according to one embodiment may have a stress difference ratio K of <NUM> or less.

The target line may be a plain line, and a stress difference ratio (K) of the glass substrate for semiconductor packaging may be <NUM> or less.

The target line may be a via line, and a stress difference ratio (K) of the glass substrate for semiconductor packaging may be <NUM> or less.

The core via may be disposed in the number of <NUM> to <NUM>, based on a unit area of <NUM> x <NUM> of the glass substrate.

According to a second aspect of the invention, a packaging substrate for a semiconductor includes a packaging glass substrate for a semiconductor in accordance with the first aspect of the invention, and further includes a core layer disposed on a surface of the core via, and a core seed layer to become as a seed for forming an electrically conductive layer, or a core distribution layer which is an electrically conductive layer.

According to a second aspect of the invention, a semiconductor apparatus includes a semiconductor element unit including one or more semiconductor elements; a packaging substrate for semiconductor electrically connected to the semiconductor element unit; and a motherboard electrically connected to the packaging substrate, configured for transmitting electrical signals of the semiconductor element and external, and connecting each other, wherein the packaging substrate is a packaging substrate according to the second aspect of the invention.

A glass substrate for semiconductor packaging, a substrate for semiconductor packaging, and a semiconductor apparatus of the invention can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible.

Additionally, since the glass substrate applied as a core of substrate is an insulator itself, there is a lower possibility of generating parasitic element compared to a conventional silicon core, and thus it is possible to simplify the treatment process for insulating layer and it is also applicable to a high-speed circuit.

In addition, unlike a silicon being manufactured in the form of a round wafer shape, the glass substrate is manufactured in the form of a large panel, and thus mass production is relatively easy and economic efficiency can be further improved.

Since the embodiment applies a glass substrate of which stress is controlled, it may have excellent mechanical properties despite formation of core vias.

Hereinafter, examples will be described in detail with reference to the accompanying drawings so that they can be easily practiced by those skilled in the art to which the embodiment pertains. However, the embodiment may be embodied in many different forms and is not to be construed as being limited to the embodiments set forth herein. Like reference numerals designate like elements throughout the specification.

Throughout the present specification, the phrase "combination(s) thereof" included in a Markush-type expression denotes one or more mixtures or combinations selected from the group consisting of components stated in the Markush-type expression, that is, denotes that one or more components selected from the group consisting of the components are included.

Throughout the present specification, terms such as "first," "second," "A," or "B" are used to distinguish the same terms from each other. The singular forms "a," "an," and "the" include the plural form unless the context clearly dictates otherwise.

Throughout the present specification, the term "X-based" may mean that a compound includes a compound corresponding to X, or a derivative of X.

Throughout the present specification, "B being disposed on A" means that B is disposed in direct contact with A or disposed over A with another layer or structure interposed therebetween and thus should not be interpreted as being limited to B being disposed in direct contact with A.

Throughout the present specification, "B being connected to A" means that B is connected to A directly or through another element therebetween, and thus should not be interpreted as being limited to B being directly connected to A, unless otherwise noted.

Throughout the present specification, a singular form is contextually interpreted as including a plural form as well as a singular form unless specially stated otherwise.

The inventors have recognized that, in the process of developing a semiconductor apparatus capable of exhibiting high performance with a more integrated and thinner thickness, not only the apparatus itself but also the packaging process is an important factor for improving its performance. Also, inventors have confirmed that, by applying a glass core in a single layer and controlling the shape of a through-via, an electrically conductive layer formed thereon, etc., it is possible to make a packaging substrate thinner and to improve the electrical properties of the semiconductor apparatus, unlike a conventional interposer and organic substrate in which two or more layers of cores are applied on a motherboard as a packaging substrate.

When a through-hole-shaped core via is formed on a thin glass substrate, partial concentration of stress is easy to occur during the machining process, and this may induce degradation of mechanical properties. It becomes one of the main causes of decreasing workability during a complicated process of manufacturing a packaging substrate. In the embodiment, a substrate for packaging applied with a glass substrate of which such concentration of stress is controlled is provided.

<FIG> is a conceptual view for illustrating a top view (a) of a glass substrate having a core via applied in embodiments of the present invention and a cross section of the core via, and <FIG> are conceptual views for illustrating a method of measuring stress in the present invention, wherein (a) shows a route for measuring stress of a via line, and (b) shows a route for measuring stress of a plain line. <FIG> is a conceptual view for illustrating a cross section of a semiconductor apparatus according to one embodiment of the present invention, <FIG> is a conceptual view for illustrating a cross section of a packaging substrate according to another embodiment of the present invention, and <FIG> and <FIG> are detailed conceptual views for illustrating some of cross sections of a packaging substrate according to example embodiments of the present invention, respectively (a circle indicates a view obtained through observation from the top or the bottom). Hereinafter, with reference to <FIG> and <FIG>, a substrate for a semiconductor packaging will be described in detail, and with reference to <FIG>, a packaging substrate, and a semiconductor apparatus will be described in detail.

To achieve the above objectives, a substrate for semiconductor packaging <NUM> includes a glass substrate <NUM>, a core via <NUM>, and a core layer <NUM>.

A glass substrate <NUM> has a first surface <NUM> and a second surface <NUM> facing each other.

A core seed layer <NUM> or a core distribution pattern <NUM> is disposed at a core layer <NUM>.

A core seed layer <NUM> is disposed on a surface of the core via and to become as a seed for forming an electrically conductive layer.

A core distribution pattern is an electrically conductive layer disposed on a surface of the core via.

As the glass substrate <NUM>, a glass substrate applied to semiconductor is preferable. For example, a borosilicate glass substrate, a non-alkali glass substrate, or the like may be applicable, but the present invention is not limited thereto.

The glass substrate <NUM> may have a thickness of <NUM>,<NUM> or less. The glass substrate <NUM> may have a thickness of <NUM> to <NUM>,<NUM>, or <NUM> to <NUM>. The glass substrate <NUM> may have a thickness of <NUM> to <NUM>.

Forming a thinner packaging substrate is advantageous in that electrical signal transmission can be made more efficient. However, the glass substrate also should serve as a supporting body which supports semiconductor elements disposed thereon, so it is preferable to have the above thickness.

The thickness of the glass substrate refers to the thickness of the glass substrate itself except for the thickness of the electrically conductive layer on the glass substrate.

The core vias <NUM> may be formed by removing a predetermined region of the glass substrate <NUM>, and in particular, it may be formed by etching a glass plate physically and/or chemically.

Formation of the core via <NUM> may be applied with a method of forming a defect (flaw) on the surface of the glass substrate by means of a laser and the like and then etching chemically, laser etching, etc., but the present invention is not limited thereto.

A stress of the glass substrate <NUM> may be measured at a plain line or a via line.

A plain line is a line linking places where the core via <NUM> is not formed on a first surface <NUM>. A via line is a line linking places where the core via <NUM> is formed on a first surface <NUM>.

A stress difference value P is represented by the below Equation (<NUM>).

The glass substrate <NUM> may have a stress difference value P of <NUM> MPa or less.

In the Equation (<NUM>), the Vp is a difference between the maximum value and the minimum value of stress measured at a via line, and the Np is a difference between the maximum value and the minimum value of stress measured at a plain line.

The P value may be <NUM> MPa or less, <NUM> MPa or less or <NUM> MPa or less. Also, the P value may be <NUM> MPa or more, or <NUM> MPa or more.

When a glass substrate with the above stress difference value P is applied as a substrate for semiconductor packaging, it is possible to manufacture a packaging substrate having more stable mechanical properties.

The Vp value of the glass substrate may be <NUM> MPa or less. The Vp value of the glass substrate may be or <NUM> MPa or less, and the Vp value may be <NUM> MPa or less. The Vp value of the glass substrate may be <NUM> MPa or less. The Vp value of the glass substrate may be <NUM> MPa or more. The Vp value of the glass substrate may be <NUM> MPa or more.

When a glass substrate with difference Vp in these ranges between the maximum value and the minimum value of stress measured at a via line, is applied as a substrate for semiconductor packaging, it is possible to manufacture a packaging substrate having more stable mechanical properties.

The Np value of the glass substrate may be <NUM> MPa or less. The Np value of the glass substrate may be <NUM> MPa or less, or <NUM> MPa or less. The Np value of the glass substrate may be <NUM> MPa or more. The Np value of the glass substrate may be <NUM> MPa or more.

When a glass substrate whose difference Np in these ranges between the maximum value and the minimum value of stress measured at a plain line, is applied as a substrate for semiconductor packaging, it is possible to manufacture a packaging substrate having more stable mechanical properties.

A stress difference ratio K is represented by the below Equation (<NUM>).

A target line is the one selected from a plain line which is a line linking places where a core via is not formed, or a via line which is a line linking places where a core via is formed.

The glass substrate may have a stress difference ratio K of <NUM> or less.

In the Equation (<NUM>), the K is a stress difference ratio measured at the same plane of the same glass substrate, the Lp is a difference between the maximum value and the minimum value of stress measured at the target line, and the La is an average value of stress measured at the target line.

The K value of the glass substrate may be <NUM> or less, <NUM> or less, or <NUM> or less. When a glass substrate with the above K value is applied as a substrate for semiconductor packaging, it is possible to manufacture a packaging substrate having more stable mechanical properties.

A stress difference ratio measured at a plain line is represented as Kn.

The stress difference ratio Kn at a plain line may be <NUM> or less. The stress difference ratio Kn at a plain line may be <NUM> or less. The stress difference ratio Kn at a plain line may be more than <NUM>. The stress difference ratio Kn at a plain line may be more than <NUM>.

A stress difference ratio measured at a via line is represented as Kv.

The stress difference ratio Kv at a via line may be <NUM> or less. The stress difference ratio Kv of a via line may be <NUM> or less. The stress difference ratio Kv of a via line may be <NUM> or less, or <NUM> or less. The stress difference ratio Kv of a via line may be <NUM> or more. The stress difference ratio Kv at a via line may be <NUM> or more, or <NUM>.

When a glass substrate with these Kn and Kv value is applied as a substrate for semiconductor packaging, it is possible to manufacture a packaging substrate having more stable mechanical properties.

The stress is analyzed by applying a birefringence 2D evaluation device. In detail, the birefringence 2D dispersion evaluation device may be WPA-<NUM> device of NPM (NIPPON PULSE KOREA CO.

For example, when data are read on a glass substrate along to a stress measuring route shown in <FIG> by a probe, measured values such as a birefringence value are inputted by the device, and stress in a measuring route is presented by pressure unit (ex. MPa) through a predetermined calculation process.

In this time, stress can be measured by inputting a light elastic coefficient and the thickness of a measuring target, and <NUM> is applied as the light elastic value in the examples.

The core via <NUM> may be disposed in the number of <NUM> to <NUM>, or <NUM> to <NUM>, or <NUM> to <NUM>, based on a unit area (<NUM> x <NUM>) of the glass substrate <NUM>. When satisfying these pitch conditions, it is more advantageous to form an electrically conductive layer, etc., and is possible to improve the performance of packaging substrate.

The core via <NUM> may be disposed at the glass substrate <NUM> in a pitch of <NUM> or less, may be disposed in a pitch of <NUM> to <NUM>, may be disposed in a pitch of <NUM> to <NUM>. In this case, it is advantageous to form an electrically conductive layer, etc., while maintaining the mechanical properties of the glass substrate above certain level.

A core via <NUM> may include a first opening part <NUM> in contact with the first surface; a second opening part <NUM> in contact with the second surface; and a minimum inner diameter part <NUM> having the smallest inner diameter in the entire core via connecting the first opening part and the second opening part.

A diameter CV1 of the first opening part and a diameter CV2 of the second opening part may be substantially different. A diameter CV1 of the first opening part and a diameter CV2 of the second opening part may be substantially same.

The core via <NUM> may have one place of smaller inner diameter than the other places, in the inner diameter surfaces connecting the first opening part and the second opening part, and it is referred to as a minimum inner diameter.

The minimum inner diameter part may be disposed at the first opening part or the second opening part. In this case, the core via may be a cylindrical type or a (truncated) triangular pyramid type core via. In this case, a diameter CV3 of the minimum inner diameter part corresponds to the diameter of smaller one between the first opening part and the second opening part.

The minimum inner diameter part may be disposed between the first opening part and the second opening part. In this case, the core via may be a barrel type core via. In this case, the diameter CV3 of the minimum inner diameter part may be smaller than the larger one between the diameter of the first opening part and the diameter of the second opening part.

The diameter of the first opening part and the diameter of the second opening part may be comparatively constant at the overall glass substrate <NUM>, respectively. Also, the inner diameter of the narrowest part in the core via (Minimum inner diameter) may be comparatively constant at the overall glass substrate <NUM>.

The minimum inner diameter may have an average diameter of <NUM> to <NUM>.

In the Equation (<NUM>), D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the minimum inner diameter, D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the minimum inner diameter, and D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the minimum inner diameter.

The minimum inner diameter may be the one satisfying the condition of the below Equation (<NUM>-<NUM>).

In the Equation (<NUM>-<NUM>), D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the minimum inner diameter, D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the minimum inner diameter, and D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the minimum inner diameter.

The target opening part corresponding to the larger one between the diameter of the first opening part and the diameter of the second opening part, may have an average diameter of <NUM> to <NUM>.

The target opening part corresponding to the larger one between the diameter of the first opening part and the diameter of the second opening part, may satisfy the condition of the below Equation (<NUM>).

In the Equation (<NUM>), D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the target opening part, D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the target opening part, and D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the target opening part.

The target opening part corresponding to the larger one between a diameter of the first opening part and a diameter of the second opening part, may have an average diameter of <NUM> to <NUM>.

The target opening part corresponding to the larger one between the diameter of the first opening part and the diameter of the second opening part, may satisfy the condition of the below Equation (<NUM>-<NUM>).

In the Equation (<NUM>-<NUM>), D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the target opening part, D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the target opening part, and D<NUM> is a value corresponding to <NUM>% from the diameter distribution of the target opening part.

The target opening part of the core via, corresponding to the larger one between a diameter of the first opening part which is a diameter at an opening part in contact with the first surface, and a diameter of the second opening part which is a diameter at an opening part in contact with the second surface, may have an average diameter of larger value than D<NUM>, which is a value corresponding to <NUM>% from the diameter distribution of the target opening part.

The diameter distribution described above, is evaluated based on a diameter which is observed by microscope in the cross-section, after dividing prepared samples into <NUM> compartments (<NUM> x <NUM>), and processing of cutting the samples of <NUM> areas (top left, bottom left, center, top right, bottom right), and measured.

When the entire length G21 of the core via is <NUM> %, the point at which the minimum inner diameter part is located may be the point G23 of <NUM> % to <NUM> % based on the first opening part, and may be the point of <NUM> % to <NUM> %. When the minimum inner diameter part is at the position described above, based on the entire length of core via, the design of electrically conductive layer of packaging substrate and the process of forming electrically conductive layer may be easier.

The angle Ca1 of the inner diameter surface connecting the inner diameter of the minimum inner diameter part and the first opening part, and the angle Ca2 of the inner diameter surface connecting the inner diameter part of the minimum inner diameter part and the second opening part, may have a ratio of <NUM>: <NUM> to <NUM>. In this case, since the angle difference between the inner diameter surface of the core via starting from the first opening and the inner diameter surface of the core via starting from the second opening is insignificant, the subsequent plating process, etc. may proceed more smoothly.

The angle is evaluated as an angle with an imaginary reference line perpendicular to the first surface or the second surface, and evaluated as an absolute value regardless of the direction (hereinafter the same).

The larger angle between the angle Ca1 of the inner diameter surface connecting the inner diameter of the minimum inner diameter part and the first opening part, and the angle Ca2 of the inner diameter surface connecting the inner diameter of the minimum inner diameter part and the second opening part, may be degree of <NUM> or less, may be degree of <NUM> to <NUM>, and may be degree of <NUM> to <NUM>. In the case of having such an angle, the efficiency of subsequent processes such as plating can be further improved.

The thickness of the electrically conductive layer measured at a larger one between the diameter CV1 of the first opening part and the diameter CV2 of the second opening part, may be same as or thicker than the thickness of an electrically conductive layer formed on the part CV3 having the minimum inner diameter among the core vias.

A semiconductor apparatus <NUM> and a packaging substrate <NUM> will be described in further detail.

A semiconductor apparatus <NUM> in one embodiment includes a semiconductor element unit <NUM> where one or more semiconductor elements <NUM>, <NUM>, and <NUM> are disposed; a packaging substrate <NUM> electrically connected to the semiconductor elements; and a motherboard <NUM> electrically connected to the packaging substrate, transmitting electrical signals of the semiconductor element and external, and connecting each other.

The packaging substrate <NUM> according to another embodiment includes a core layer <NUM> and an upper layer <NUM>.

The core layer <NUM> includes a substrate for semiconductor packaging <NUM> described in the above.

The semiconductor element unit <NUM> refers to elements mounted on a semiconductor apparatus and is mounted on the packaging substrate <NUM> by connecting electrode and the like. In detail, for example, a computation element such as CPU and GPU (a first element <NUM> and a second element <NUM>), a memory element such as a memory chip (a third element <NUM>), and the like may be applied as the semiconductor element unit <NUM>, but any semiconductor element mounted on a semiconductor apparatus is applicable without limitations.

A motherboard such as a printed circuit board and a printed wiring board may be applied as the motherboard <NUM>.

The packaging substrate <NUM> includes a core layer <NUM> and an upper layer <NUM> disposed on one surface of the core layer.

The packaging substrate <NUM> may further include a lower layer <NUM> disposed under the core layer, optionally.

The core layer <NUM> includes a glass substrate <NUM>; a plurality of core via <NUM> penetrating through the glass substrate in a thickness direction; and a core distribution layer <NUM> disposed on a surface of the glass substrate or a surface of the core via, and where an electrically conductive layer, at least a part of which electrically connect electrically conductive layers on the first surface and the second surface through the core via, is disposed.

The glass substrate <NUM> has a first surface <NUM> and a second surface <NUM> facing each other, and these two surfaces are generally parallel from each other thereby having a constant thickness in the glass substrate overall.

A core via <NUM> penetrating through the first surface and the second surface is disposed at the glass substrate <NUM>.

Conventionally, a silicon substrate and an organic substrate were applied in a form of stacked, as the packaging substrate of the semiconductor apparatus. In case of a silicon substrate, when it is applied to a high-speed circuit, a parasitic element effect may occur due to the semiconductor property thereof, and it has a disadvantage of relatively large power loss. Also, in case of an organic substrate, it requires a larger area to form a more complicated distribution pattern, but this does not correspond to the miniaturization trend of electronic apparatus. In order to form a complicated distribution pattern within a predetermined size, it is necessary to make patterns finer substantially, but there has been a practical limit to the miniaturization of the patterns due to a material property of the organic substrate.

In the embodiment, the glass substrate <NUM> is applied as a supporting body for the core layer <NUM> to solve these problems. Also, by applying the glass substrate and the core via <NUM> formed to penetrate the glass substrate, it is possible to provide a packaging substrate <NUM> having a shortened electrical flow length, a smaller size, a faster response, and a lower loss property.

The core distribution layer <NUM> includes a core distribution pattern <NUM> and a core insulating layer <NUM>.

A core distribution pattern <NUM> is an electrically conductive layer which electrically connect the first surface and the second surface of the glass substrate through a through-via.

A core insulating layer <NUM> surrounds the core distribution pattern <NUM>.

The core layer <NUM> has an electrically conductive layer formed therein through a core via, and thus serves as an electrical passage crossing the glass substrate <NUM>, and may connect upper and lower parts of the glass substrate with a relatively short distance to have faster electrical signal transmission and lower loss property.

The core distribution pattern <NUM> is a pattern that electrically connect the first surface <NUM> and the second surface <NUM> of the glass substrate through the core via <NUM>.

The core distribution pattern <NUM> includes a first surface distribution pattern 241a, a second surface distribution pattern 241c, and a core via distribution pattern 241b.

A first surface distribution pattern 241a is an electrically conductive layer disposed on at least a part of the first surface <NUM>. A second surface distribution pattern 241c is an electrically conductive layer disposed on at least a part of the second surface <NUM>. A core via distribution pattern 241b is an electrically conductive layer electrically connecting the first surface distribution pattern and the second surface distribution pattern to each other through the core via <NUM>.

As the electrically conductive layer, for example, a copper plating layer may be applicable, but the present invention is not limited thereto.

The glass substrate <NUM> serves as an intermediate role and an intermediary role for connecting a semiconductor element <NUM> and a motherboard <NUM> to the upper and lower parts, respectively. The core via <NUM> serves as a passage for transmitting electrical signals thereof, thereby facilitating seamless signal transmission.

A thickness of an electrically conductive layer measured at larger one between the diameter of the first opening part, and the diameter of the second opening part may be equal to or thicker than a thickness of an electrically conductive layer formed on a part having the minimum inner diameter within the core via.

The core distribution layer <NUM> is an electrically conductive layer formed on the glass substrate and may satisfy that a cross-cut adhesion test value according to ASTM D3359 is 4B or greater.

For example, the core distribution layer <NUM> may have the cross-cut adhesion test value of 5B or greater. Also, an electrically conductive layer that is the core distribution layer <NUM>, may have an adhesive strength of <NUM> N/cm or more and a bonding strength of <NUM> N/cm or more with the glass substrate <NUM>. When such a degree of bonding strength is satisfied, the bonding strength between the substrate and the electrically conductive layer is sufficient for applying as a packaging substrate.

An upper layer <NUM> is disposed on the first surface <NUM>.

The upper layer <NUM> may comprise an upper distribution layer <NUM> and an upper surface connecting layer <NUM> disposed on the upper distribution layer. The uppermost surface of the upper layer <NUM> may be protected by a cover layer <NUM> having an opening part formed thereon, which is capable of being in direct contact with a connecting electrode of the semiconductor element unit.

The upper distribution layer <NUM> includes an upper insulating layer <NUM> disposed on the first surface; and an upper distribution pattern <NUM> that has a predetermined pattern and is an electrically conductive layer at least a part of which is electrically connected to the core distribution layer <NUM>, and built in the upper insulting layer.

Anything applied as an insulating layer to a semiconductor element or a packaging substrate is applicable to the upper insulating layer <NUM>, for example, an epoxy-based resin comprising a filler may be applied, but the present invention is not limited thereto.

The insulating layer may be formed by a method of forming and hardening a coating layer, or by a method of laminating an insulating film which is filmizated in a state of non-hardened or semi-hardened to a core layer and hardening it. In this time, when a method of pressure sensitive lamination and the like is applied, the insulator is embedded even in the space inside a core via, and thus efficient process proceeding can be made. Also, even though plural-layered insulating layers are applied with being stacked, substantial distinction between the layers may be difficult, so that a plurality of insulating layer are collectively referred to as an upper insulating layer. Also, the core insulating layer <NUM> and the upper insulating layer <NUM> may be applied with the same insulating material, and in this case, the boundary therebetween may not be substantially distinguished.

The upper distribution pattern <NUM> refers to an electrically conductive layer disposed in the upper insulating layer <NUM> in a predetermined form. For example, the upper distribution pattern <NUM> may be formed by a method of a build-up layer method. In detail, the upper distribution pattern <NUM> where electrically conductive layer is vertically or horizontally formed in a desired pattern may be formed by repeating a process of: forming an insulating layer; removing an unnecessary part of the insulating layer and then forming an electrically conductive layer through a method of copper plating and the like; removing an unnecessary part of the electrically conductive layer and then forming an insulating layer on this electrically conductive layer again; and removing an unnecessary part again and then forming an electrically conductive layer through a method of plating and the like.

Since the upper distribution pattern <NUM> is disposed between the core layer <NUM> and the semiconductor element unit <NUM>, it is formed to at least partially includes a fine pattern so that the transmission of electrical signals with the semiconductor element unit <NUM> may proceed smoothly and a desired complicated pattern may be sufficiently accommodated. In this case, the fine pattern may have a width and an interval of about less than <NUM>, about <NUM> or less, about <NUM> or less, about <NUM> or less, or about <NUM> to about <NUM>, respectively (Hereinafter, the description of the fine pattern is the same).

In order to form the upper distribution pattern <NUM> to include a fine pattern, at least two or more methods are applied in the present invention.

One of them, is to apply a glass-applied glass substrate <NUM>, as a material for packaging substrate. The glass substrate <NUM> can have a considerably flat surface property with a surface roughness (Ra) of <NUM> angstroms or less, thereby minimizing the influence of surface morphology of a supporting substrate on formation of the fine pattern.

The other one, is based on the property of the insulating layer. In case of the insulating layer, a filler component is often applied in addition to resin, and inorganic particles such as silica particles may be applicable as the filler. When the inorganic particles are applied to the insulating layer as the filler, the size of the inorganic particles can affect whether to form the fine pattern, and therefore, the insulating layer in the embodiment applies particle fillers with an average diameter of about <NUM> or less, and in detail, including particle fillers with an average diameter of about <NUM> to about <NUM>. Such a characteristic can minimize the influence of the insulating layer itself on the formation of an electrically conductive layer with a width of several micrometer-unit, while maintaining necessary properties for the insulating layer at a certain level or more, and can also help to form a fine pattern with good adhesion onto the surface, due to the fine surface morphology.

The upper surface connecting layer <NUM> includes an upper surface connecting pattern <NUM> and an upper surface connecting electrode <NUM>.

An upper surface connecting pattern <NUM> is at least a part of which is electrically connected to the upper distribution pattern <NUM>, and is disposed in the upper insulating layer <NUM>. An upper surface connecting electrode <NUM> electrically connect the semiconductor element unit <NUM> and the upper surface connecting pattern <NUM>.

The upper surface connecting pattern <NUM> may be disposed on one surface of the upper insulating layer <NUM> or may be embedded with at least a part of which is being exposed on the upper insulating layer. For example, when the upper surface connecting pattern is disposed on one side of the upper insulating layer, the upper insulating layer may be formed by a method of plating and the like. Also, when the upper surface connecting pattern is embedded with at least a part of which is being exposed on the upper insulating layer, it may be the one which is formed by forming a copper plating layer and the like, and then a part of an insulating layer or electrically conductive layer is removed by a method of surface polishing, surface etching and the like.

The upper surface connecting pattern <NUM> may at least partially include a fine pattern like the above-described upper distribution pattern <NUM>. The upper surface connecting pattern <NUM> including the fine pattern like this may enable a larger number of elements to be electrically connected to one another even in a narrow area, facilitate electrical signal connection between elements or with the external, and more integrated packaging is possible.

The upper surface connecting electrode <NUM> may be connected to the semiconductor element unit <NUM> directly through a terminal and the like, or via an element connecting unit <NUM> such as a solder ball.

The packaging substrate <NUM> is also connected to the motherboard <NUM>. The motherboard <NUM> may be directly connected to the second surface distribution pattern 241c, which is a core distribution layer disposed on at least a part of the second surface <NUM> of the core layer <NUM>, through a motherboard terminal or may be electrically connected via a board connecting unit such as a solder ball. Also, the second surface distribution pattern 241c may be connected to the motherboard <NUM> via the lower layer <NUM> disposed under the core layer <NUM>.

The lower layer <NUM> includes a lower distribution layer <NUM> and a lower surface connecting layer <NUM>.

The lower distribution layer <NUM> includes a lower insulating layer 291b; and a lower distribution pattern 291a.

A lower insulating layer 291b is an insulating layer at least a part of which is in contact with the second surface <NUM>. A lower distribution pattern 291a is being embedded in the lower insulating layer and having a predetermined pattern, and at least a part of which is electrically connected to the core distribution layer.

The lower surface connecting layer <NUM> may further include a lower surface connecting electrode 292a and/or a lower surface connecting pattern 292b. The lower surface connecting electrode 292a is electrically connected to the lower surface connecting pattern. The lower surface connecting pattern 292b is at least a part of which is electrically connected to the lower distribution pattern, and at least a part of which is exposed to one surface of the lower insulating layer.

The lower surface connecting pattern 292b may be formed as a non-fine pattern wider than the fine pattern, unlike the upper surface connecting pattern <NUM>. In this case, more efficient transmitting of electrical signals at a part connected to the motherboard <NUM> is possible.

Not applying a substantially additional different substrate other than the glass substrate <NUM> to the packaging substrate <NUM> disposed between the semiconductor element unit <NUM> and the motherboard <NUM>, is one feature of the present invention.

Conventionally, an interposer and an organic substrate were applied with being stacked between connection of the element and the motherboard. It is considered that such a multi-stage form has been applied in at least two reasons. One reason is that there is a scale problem in directly bonding the fine pattern of the element to the motherboard, and the other reason is that problem of wiring damage may occur due to a difference in thermal expansion coefficient during the bonding process or during the driving process of the semiconductor apparatus. The embodiment has solved these problems by applying the glass substrate with a thermal expansion coefficient similar to that of the semiconductor element, and by forming a fine pattern with a fine scale enough to mount the elements on the first surface of the glass substrate and its upper layer.

The semiconductor apparatus <NUM> having a considerably thin packaging substrate <NUM> may make the overall thickness of the semiconductor apparatus thinner, and it is also possible to dispose a desired electrical connecting pattern even in a narrower area by applying the fine pattern.

In detail, the packaging substrate may have a thickness of about <NUM> or less, about <NUM> or less, or about <NUM>. Also, the packaging substrate <NUM> may have a thickness of about <NUM> or more, or about <NUM> or more. Due to the above-described characteristics, the packaging substrate can stably connect the element and the motherboard electrically and structurally even with a relatively thin thickness, thereby contributing to miniaturization and thinning of the semiconductor apparatus.

A manufacturing method of the packaging substrate will be described below.

The manufacturing method of the packaging substrate comprises a preparation step of forming a defect at predetermined positions of a first surface and a second surface of a glass substrate; an etching step of preparing a glass substrate with a core via formed thereon by applying an etchant to the glass substrate where the defect is formed; a core layer forming step of plating the surface of the glass substrate with the core via formed thereon, to form a core distribution layer which is an electrically conductive layer, and thereby forming a core layer; and an upper layer forming step of forming an upper distribution layer, which is an electrically conductive layer surrounded by an insulting layer on one side of the core layer, and thereby manufacturing the packaging substrate described above.

The type of defect is formed by considering a type of via to be formed. Due to such a defect, a core via is formed at in an etching step, and outstanding workability may be achieved, compared to working separately by drill to form a via in an organic substrate.

The core layer forming step may comprise a pretreatment process of preparing a pretreated glass substrate by forming an organic-inorganic composite primer layer containing a nanoparticle with amine-group on a surface of the glass substrate where the core via is formed; and a plating process of plating a metal layer on the glass substrate which is pretreated.

For the formation of the primer layer, different kinds of metals such as titanium, chromium, and nickel may be sputtered with copper, etc., or alone, and in this case, adhesiveness of glass-metal may be improved by surface morphology of glass, an anchor effect which is an interaction between metal particles, and the like, and it may serve as a seed in a subsequent plating process and the like.

An insulating layer forming step may be further comprised between the core layer forming step and the upper layer forming step.

The insulating layer forming step may be a step of positioning an insulating film on the core layer and performing pressure sensitive lamination to form a core insulating layer.

A manufacturing method of packaging substrate will be described in more detail.

Chemical etching may be proceeded by placing a glass substrate where a groove is formed, in a bath containing hydrofluoric acid and/or nitric acid, and applying ultrasonic treatment, etc. In this case, the hydrofluoric acid concentration may be <NUM> or more, and may be <NUM> or more. The hydrofluoric acid concentration may be <NUM> or less, and may be <NUM> or less. The nitric acid concentration may be <NUM> or more, and may be <NUM> or more. The nitric acid concentration may be <NUM> or less. The ultrasonic treatment may be performed at a frequency of <NUM> to <NUM>, and may be performed at a frequency of <NUM> to <NUM>.

When applied under these conditions, it is possible to prepare a glass substrate with improved workability while reducing residual stress on the glass substrate where the via is formed.

<NUM>-<NUM>) Core Layer Forming Step: An electrically conductive layer 21d is formed on the glass substrate. As for the electrically conductive layer, a metal layer typically containing copper metal may be applied, but not limited thereto.

A surface of the glass (including a surface of a glass substrate and a surface of a core via) and a surface of the copper metal have different properties, so the adhesion strength is rather poor. In the embodiment, the adhesion strength between the glass surface and the metal is improved by two methods, a dry method and a wet method.

The dry method is a method applying sputtering, that is, a method of forming a seed layer 21c inside the core via and on the glass surface through metal sputtering. For the formation of the seed layer, different kinds of metals such as titanium, chromium, and nickel may be sputtered with copper, etc., and in this case, it is considered that the adhesiveness of glass-metal is improved by surface morphology of glass, an anchor effect which is an interaction between metal particles, and the like.

The wet method is a method applying primer treatment, that is, a method of forming a primer layer 21c by performing pre-treatment with a compound having a functional group such as amine. After pre-treatment by using a silane coupling agent depending on the degree of intended adhesion strength, primer treatment may be done with a compound or particles having an amine functional group. As mentioned above, a supporting body substrate of the embodiment needs to be of high performance enough to form a fine pattern, and it should be maintained after the primer treatment. Therefore, when such a primer includes a nanoparticle, it is desirable to apply a nanoparticle with an average diameter of <NUM> or less, for example, a nanoparticle is desirable to be applied to a particle with amine functional group. The primer layer may be formed by applying an adhesive strength improving agent manufactured in CZ series by MEC Inc, for example.

In the seed layer/primer layer 21c, an electrically conductive layer may selectively form a metal layer in the state of removing a part where the formation of an electrically conductive layer is unnecessary, or not removing.

Also, in the seed layer/primer layer 21c, a part where the formation of an electrically conductive layer is necessary, or a part where the formation of an electrically conductive layer is unnecessary, may be selectively processed to be an activated state or an inactivated state for metal plating. The processing to be an activated state or an inactivated state may be performed, for example, by using light irradiation treatment such as laser light of a certain wavelength, etc., chemical treatment, and the like. A copper plating method, etc. applied for manufacturing a semiconductor element may be applied to form the metal layer, but not limited thereto.

During the metal plating, a thickness of an electrically conductive layer formed, may be controlled by regulating several variables such as the concentration of plating solution, plating time, and type of additive to be applied.

When a part of the core distribution layer is unnecessary, it can be removed, and an etching layer 21e of a core distribution layer may be formed by performing metal plating to form an electrically conductive layer as a predetermined pattern, after the seed layer is partially removed or processed to be inactivated.

<NUM>-<NUM>) Insulating Layer Forming Step: An insulating layer forming step in which an empty space of a core via is filled with an insulating layer after the core distribution layer, which is an electrically conductive layer, is formed, may be performed. In this case, the one manufactured in a film type may be applied to the applied insulating layer, and for example, a method such as pressure sensitive laminating the film-type insulating layer may be applied. When proceeding the pressure sensitive laminating like this, the insulating layer may be sufficiently subsided to the empty space inside the core via to form a core insulating layer without void formation.

<NUM>) Upper Layer Forming Step: It is a step for forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on a core layer. The upper distribution layer may be formed by a method of coating a resin composition forming an insulating layer 23a, or laminating an insulating film. For simplicity, applying a method of laminating an insulating film is desirable. The laminating of the insulating film may be proceeded by a process of laminating and then hardening, and in this case, if a method of the pressure sensitive lamination is applied, the insulating resin may be sufficiently subsided even into a layer where an electrically conductive layer is not formed inside the core via. The upper insulating layer is also in direct contact with a glass substrate at least in part thereof, and thus the one with a sufficient adhesive force is applied. Specifically, it is desirable that the glass substrate and the upper insulating layer have characteristics that satisfy an adhesion strength test value of 4B or more according to ASTM D3359.

The upper distribution pattern may be formed by repeating a process of forming the insulating layer 23a, forming an electrically conductive layer 23c to have a predetermined pattern, and forming an etching layer 23d of the electrically conductive layer by etching the unnecessary part, and in the case of an electrically conductive layer formed to neighbor with having an insulating layer placed therebetween, it may be formed by a method of performing a plating process after forming a blind via 23b in the insulating layer. For formation of the blind via, a dry etching method such as laser etching and plasma etching, and a wet etching method using a masking layer and an etching solution may be applied.

<NUM>) Upper Surface Connecting Layer and Cover Layer Forming Step: Upper surface connecting pattern and upper surface connecting electrode may be performed by a process similar to forming the upper distribution layer. Specifically, it may be formed by a method such as forming an etching layer 23f of an insulating layer 23e on the insulating layer 23e, and then forming an electrically conductive layer <NUM> again thereon, and then forming an etching layer <NUM> of the electrically conductive layer, but a method of selectively forming only an electrically conductive layer without applying a method of etching, may be also applied. A cover layer may be formed to have an opening part (not shown) at a position corresponding to the upper surface connecting electrode such that the upper surface connecting electrode to be exposed and directly connected to an element connection unit, a terminal of an element, or the like.

<NUM>) Lower Surface Connecting Layer and Cover Layer Forming Step: A lower distribution layer and/or a lower connecting layer, and optionally a cover layer (not shown) may be formed in a manner similar to the the upper surface connecting layer and the cover layer forming step, described above.

Hereinafter, the present invention will be described in more detail through specific examples. The following examples are only examples to help the understanding of the present invention, and the scope of the present invention is not limited thereto.

Also, the core via were formed to have a first opening part in contact with the first surface; a second opening part in contact with the second surface; and a minimum inner diameter part, which is the area whose diameter is the narrowest in the entire core via connecting the first opening part and the second opening part.

A substrate was manufactured in the same manner as in Example <NUM>, except that the condition of the ultrasonic output was changed to <NUM> %.

A substrate was manufactured in the same manner as in Example <NUM>, except that an etching was performed by placing the glass substrate in an etching bath filled with <NUM> hydrofluoric acid (HF), <NUM> nitric acid (HNO3) and deionized water, and then etching at <NUM>, <NUM> % output.

A substrate was manufactured in the same manner as in Example <NUM>, except that the condition of the ultrasonic output during etching was changed to <NUM> %.

The stress was analyzed by applying a birefringence 2D evaluation device. In detail, WPA-<NUM> device of NPM(NIPPON PULSE KOREA CO. , LTD) was applied to the birefringence 2D dispersion evaluation device.

An average diameter of the opening part was <NUM>, an average diameter of the minimum inner diameter part was <NUM>, and the stress of plain line and via line of four glass substrate samples with an average thickness of about <NUM> was measured while changing the positions <NUM> times or more, respectively. About the number of <NUM> or <NUM> core vias per unit area (<NUM><NUM>) were formed on the glass substrate.

Specifically, when data was read on a glass substrate along the stress measurement path shown in <FIG> with a probe, a measured value such as a birefringence value was input to the device, and the stress in the measurement path was presented in pressure units (e.g., MPa) through a predetermined calculation process. The photo-elastic coefficient value of <NUM> was applied, and the thickness was applied as <NUM>.

The measured results are shown as average in the below Tables <NUM> and <NUM>, respectively, and the Vp, Np, and P values, etc. evaluated by using them are also shown in Table <NUM> or Table <NUM> below, respectively.

<NUM>-<NUM>) Core Layer Forming Step: An electrically conductive layer 21d was formed on a glass substrate. As the electrically conductive layer, a metal layer containing copper metal was applied. A sputtering layer containing titanium was formed and copper plating was performed.

<NUM>-<NUM>) Insulation Layer Forming step: After forming the core distribution layer, which is an electrically conductive layer, an insulating layer forming step of filling the empty space with an insulating layer was performed. At this time, the one manufactured in the form of a film was applied to the applied insulating layer, and a method of pressure sensitive lamination of the insulating layer in the form of a film was applied.

<NUM>) Upper Layer Forming Step: A step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer was performed. A method of laminating an insulating film as the upper insulating layer was performed, and a process of lamination and hardening of the insulating was performed. The one at least a part of which is in direct contact with the glass substrate, and thus has a sufficient adhesive force, was also applied to the upper insulating layer. Specifically, the one having properties that satisfy an adhesion test value of 4B or more according to ASTM D3359, were applied to the glass substrate and the upper insulating layer.

The upper distribution pattern was formed by repeating the process of forming the insulating layer 23a, forming an electrically conductive layer 23c in a predetermined pattern, and etching unnecessary parts to form an etching layer 23d of an electrically conductive layer. In the case of an electrically conductive layer formed adjacent to each other with an insulating layer disposed therebetween, it was formed by a method of forming a blind via 23b in the insulating layer and then performing a plating process. For the formation of the blind via, a dry etching method such as laser etching and plasma etching, and a wet etching method using a masking layer and an etchant were applied to manufacture a packaging substrate.

All samples applied to manufacture were formed into packaging substrates without damage.

Referring to Tables <NUM> and <NUM>, it was confirmed that the glass substrate having the above-mentioned degree of residual stress in the plain line and the via line, respectively, had sufficient processability as a packaging substrate. The smaller the difference in stress, the more stable work is possible in the subsequent process, however, in the case of degree confirmed above, all have an adequate processability. In the case of samples that the formation of crack and the etching in strong acid without applying ultrasonic waves were performed, although the data were not clearly presented above, but damage occurred during sputtering or the formation of the insulating layer, so it was confirmed that it is necessary to apply the ultrasonic waves together during the etching process.

Claim 1:
A packaging glass substrate for a semiconductor comprising:
a glass substrate (<NUM>, 21a) with a first surface (<NUM>) and a second surface (<NUM>) facing each other;
a plurality of core via (<NUM>) arranged in a grid pattern and penetrating through the glass substrate (<NUM>, 21a) in a thickness direction;
characterized by:
a plain line is a straight line parallel to a via line and linking places where the core via (<NUM>) is not formed,
a via line is a straight line linking nearest places where the core via (<NUM>) is formed,
a stress difference value P is a value according to the below Equation <NUM>,
and the stress difference value P is <NUM> MPa or more and <NUM> MPa or less; <MAT>
wherein in the Equation <NUM>:
P is a stress difference value measured at the same glass substrate (<NUM>, 21a),
Vp is a difference between the maximum value and the minimum value of stress measured at a via line,
Np is a difference between the maximum value and the minimum value of stress measured at a plain line,
wherein the stress values are analysed by birefringence 2D dispersion evaluation.