Patent Description:
Power factor correction (PFC) controllers for alternating current (AC) to direct current (DC) converters detect peak voltages on an AC rectified line and adjust the charging time of an output power stage to compensate for AC line voltage changes. The goal of PFC is to match the power consumption measured by an AC supply with the power actually consumed by a DC load. PFC controllers use the detected peaks to shape the current supplied to the DC load, so the DC load appears substantially real (e.g., substantially resistive) to the AC supply.

The document <CIT> discloses an amplitude detector comprising a first peak holding means for generating a first peak voltage signal for holding a peak voltage of a detected signal, a differential signal generating means for generating a differential signal between the first peak voltage signal and the detected signal and a second peak holding means for generating an amplitude detect signal holding a peak voltage of the differential signal.

In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. Connecting lines or connectors shown in the various figures presented are intended to represent example functional relationships and/or physical or logical couplings between the various elements.

Adjustment of the charging time of the power stage of an AC-to-DC power converter to compensate for line voltage changes is referred to as line voltage feed forward of PFC. The effectiveness of line voltage feed forward strongly depends on the accuracy of peak detection for the line voltage. Example digital solutions perform peak detection by digitizing an input line voltage. Once the input line voltage is digitally captured, digital comparators and memory registers can be used to determine the feed forward signal. Prior digital solutions are complex, relying on high-resolution analog-to-digital converters (ADCs), low-resolution non-linear ADCs, high-fidelity sampling techniques/circuits, precision comparators, digital decoders, etc. that have significant area, accuracy, complexity, etc. requirements. Additional prior solutions use complex filters to convert an input line voltage to a ramp signal that controls a pulse width modulator (PWM).

Disclosed herein are cost-efficient, simple line voltage peak detection methods, apparatus, systems and circuits that overcome at least the deficiencies and complexities of digital and filter-based solutions. The disclosed line voltage peak detection methods, apparatus, systems and circuits are able to track positive line transients (e.g., as they occur), and sense and track negative line transients within three-quarters of a wave cycle. A three-quarters wave cycle refers the portion of an AC signal falling between a zero crossing and the peak following the next zero crossing. Disclosed examples track positive line transients by generally, closely, immediately, instantaneously, substantially, effectively, essentially, etc. tracking the shape and characteristics of positive line transients, ignoring incidental processing time, incidental signal propagation time, etc. The disclosed methods, apparatus, systems and circuits realize precise, fast and responsive line voltage feed forward for AC-to-DC converters that compensate for positive line voltage transients, reduce (e.g., minimize) the impact of negative line voltage transients, and/or compensate for asymmetric peaks that may occur during full wave cycles. Positive line voltage transients may result in damage in the power stage and/or circuits connected to the regulated output. While negative line voltage transients may result in a longer undershoot of the regulated output, they are generally more acceptable as they are not associated with damage.

Reference will now be made in detail to non-limiting examples, some of which are illustrated in the accompanying drawings.

<FIG> is a diagram of an example power converter <NUM> having an example AC-to-DC power conversion circuit <NUM>. The example AC-to-DC power conversion circuit <NUM> includes an example AC-to-DC converter circuit <NUM>, and an example PFC circuit <NUM>. The example PFC circuit <NUM> has an input terminal 106A and an output terminal 106B. The input terminal 106A of the PFC circuit <NUM> is connected to (e.g., coupled to directly and/or indirectly) an output terminal 108A of an example rectifier <NUM> of the AC-to-DC converter circuit <NUM>. The output terminal 106B of the PFC circuit <NUM> is connected to a terminal 110A of a load <NUM> to which the AC-to-DC power conversion circuit is supplying DC power. Another terminal 110B of the load <NUM> is connected to ground.

The example rectifier <NUM> of <FIG> converts an AC input line voltage VIN_LINE <NUM> across input terminals 112A and 112B of the AC-to-DC power conversion circuit <NUM> to a rectified input line voltage VIN <NUM> (e.g., a rectified AC input line voltage) across the output terminal 108A of the rectifier <NUM> and a ground terminal <NUM>. The PFC circuit <NUM> forms an output voltage VOUT <NUM> across a capacitor <NUM> from the rectified input line voltage VIN <NUM>.

To improve the quality of the output voltage VOUT <NUM> generated by the AC-to-DC power conversion circuit <NUM>, the example power converter <NUM> of <FIG> includes an example PFC controller <NUM>. The example PFC controller <NUM> controls the example PFC circuit <NUM> to increase the power factor of the power converter <NUM>. The power factor of an AC electrical power system refers to the ratio of the real power (e.g., defined as the average value of the electrical power input in the system over one line cycle) to the apparent power (e.g., defined as the product of input voltage RMS value and the input current RMS value to the power system), and is a dimensionless number in the closed interval of <NUM> to <NUM>. In an electric power system, a load with a low power factor draws more current than a load with a high power factor for a given amount of useful power transferred.

The example PFC controller <NUM> of <FIG> turns a switch <NUM> of the PFC circuit <NUM> off and on with a varying duty cycle to form an AC input current <NUM> that is sinusoidal and in phase with the AC input voltage VIN_LINE <NUM>. When the AC input current <NUM> is sinusoidal and in phase with the AC input voltage VIN_LINE <NUM>, the load <NUM> appears to a source of the AC input voltage VIN_LINE (e.g., a power company) as a purely real load and, thus, power can be provided to the load <NUM> with a high power factor. In some examples, the example PFC controller <NUM> is implemented using one or more analog circuits.

In operation, the PFC controller <NUM> cycles the PFC circuit <NUM> between two states. The first state occurs when the PFC controller <NUM> closes the switch <NUM> (e.g., turns on a field effect transistor (FET)). In this state, an example inductor <NUM> is energized via the rectifier <NUM>, thereby an inductor current <NUM> flowing through the inductor <NUM> increases. At the same time, a diode <NUM> becomes reverse biased (because its anode terminal 132A is connected to the ground), thereby energy is provided to the load <NUM> by the capacitor <NUM>. In a second state, the PFC controller <NUM> opens the switch <NUM> (e.g., turns off the FET). In this state, the inductor <NUM> de-energizes and the inductor current <NUM> decreases as the inductor <NUM> supplies energy to the load <NUM> and for recharging the capacitor <NUM>.

The example PFC controller <NUM> of <FIG> controls the cycling of the PFC circuit <NUM> between the above-described two states. Cycling back and forth between the states is done rapidly (e.g., at a high frequency such as tens or hundreds of kilohertz (kHz)) and in a manner that controls the power factor of the power converter <NUM> by maintaining an output voltage VOUT <NUM> that is constant and controls an average of the inductor current <NUM>, and subsequently an average of the AC input current <NUM>.

Because the inductor current <NUM> is increasing in the first state and decreasing in the second state, the duty cycle at which the PFC controller <NUM> opens and closes the switch <NUM> determines the amount of time the inductor current <NUM> flowing through the inductor <NUM> is increasing, versus the amount of time the inductor current <NUM> flowing through the inductor <NUM> is decreasing. By varying the duty cycle at which the switch <NUM> operates, the PFC controller <NUM> can control an average of the inductor current <NUM>. By controlling an average of the inductor current <NUM> to track the expected current consumed by the load <NUM>, the power factor and total harmonic distortion (THD) can be significantly improved. For an ideal system, the inductor current <NUM> is a rectified sine wave, the AC input current <NUM> is a sine wave, and the inductor current <NUM> and the AC input current <NUM> are phased to match each other and VIN_LINE. The purpose of the PFC is to make the shape and magnitude of the load not impact the phasing of the AC input current124 and the inductor current <NUM>. A DC load for example has no "phase".

To detect and track peaks and sense negative transients of a peak detector input voltage PDIN (e.g., a waveform, a signal, etc.) on a line <NUM>, the example PFC controller <NUM> of <FIG> includes a peak detector <NUM>. As described in more detail below in connection with <FIG>, the example peak detector <NUM> generates an output voltage VPK_OUT on a line <NUM> that immediately tracks peaks of the peak detector input voltage PDIN on the line <NUM>, and tracks reduction of magnitude of peak detector input voltage PDIN on the line <NUM> within a time interval corresponding to a half wave cycle plus a quarter of a line cycle of the AC input line voltage VIN_LINE <NUM>.

To generate a control signal on the line <NUM> for the switch <NUM>, the example PFC controller <NUM> of <FIG> includes an example switch on_off controller <NUM> that generates the control signal on the line <NUM> based on peaks detected by the peak detector <NUM>. The example switch on_off controller <NUM> generates the control signal on the line <NUM> to have a pulse width PW, which can be expressed mathematically as <MAT> where:.

The time from one pulse to the next pulse (switching period) can vary according to how the PFC controller <NUM> works. In some examples, a fixed switching period based on a controller's internal oscillator (e.g., a controller that implements a continuous conduction Mode (CCM)). Switching period can change cycle-by-cycle if different control strategies are used. For example, in a transition mode (TrM), the switch <NUM> is turned on when inductor currents decay to zero. In some examples, an error amplifier (e.g., internal to the PFC controller <NUM>) compares a voltage proportional to the output voltage VOUT on the load <NUM>, with a reference (e.g., internal to the PFC controller <NUM>) and increases COMP if the voltage proportional to VOUT on the line is below the reference, and decreases COMP if the voltage proportional to VOUT on the line is above the reference. In some examples, COMP is changed slowly enough that it can be considered constant over a line cycle.

While an example manner of implementing the power converter <NUM> is illustrated in <FIG>, one or more of the elements, processes and/or devices illustrated in <FIG> may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way. Further still, the example power converter <NUM> of <FIG> may include one or more elements, processes and/or devices in addition to, or instead of, those illustrated in <FIG>, and/or may include more than one of any or all of the illustrated elements, processes and devices. As used herein, the phrase "in communication," including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.

<FIG> is a diagram of an example peak detector <NUM> (e.g., peak detector circuit) that may be used to implement the example peak detector <NUM> of <FIG>. To track the peak detector input voltage PDIN on the line <NUM>, the example peak detector <NUM> includes example peak detector circuits <NUM> and <NUM>. The example peak detector circuits <NUM> and <NUM> of <FIG> are analog peak-hold circuits that are connected in a pipeline, serial, etc. configuration. An output terminal 202A of the peak detector circuit <NUM> is connected to an input terminal 204A of the peak detector circuit <NUM>.

The first peak detector circuit <NUM> of <FIG> includes an example analog peak-hold circuit that continuously tracks the highest peak of the peak detector input voltage PDIN on the line <NUM> for the current half wave cycle as an example voltage VPK_TRACK on a line <NUM>. The example peak detector circuit <NUM> includes an example operational amplifier <NUM> having a first input terminal 208A connected the peak detector input voltage PDIN on the line <NUM>, and having an output terminal 208B connected to a terminal 210A of an example diode <NUM>. Another terminal 210B of the diode <NUM> is connected to a second input terminal 208C of the operational amplifier <NUM>, is connected to a terminal 212A of an example capacitor CTRACK <NUM>, and is connected to the output terminal 202A of the peak detector circuit <NUM>. Another terminal 212B of the capacitor CTRACK <NUM> is connected to ground. A terminal 214A of a switch <NUM> is connected to the terminal 210B of the diode <NUM>, and a second terminal 214B of the switch <NUM> is connected to ground.

The example peak detector circuit <NUM> tracks and holds the highest peak of the peak detector input voltage PDIN on the line <NUM> as the voltage VPK_TRACK on the line <NUM>. The peak is held until an example reset signal RESET_TRACK on a line <NUM>, which is connected to a control terminal 214C of the switch <NUM>, closes the example switch <NUM>, thereby discharging the example capacitor CTRACK <NUM> and resetting the output voltage VPK_TRACK on the line <NUM> to, for example, a small or minimal value (e.g., zero). In tracking operation, the peak detector input voltage PDIN on the line <NUM> charges the capacitor CTRACK <NUM>, and the example diode <NUM> prevents the capacitor CTRACK <NUM> from discharging. If the peak detector input voltage PDIN on the line <NUM> increases further, the capacitor CTRACK <NUM> is further charged to the higher voltage. If the peak detector input voltage PDIN on the line <NUM> decreases below the previous peak value, the voltage on the capacitor CTRACK <NUM> stays at the previous peak value.

The second peak detector circuit <NUM> of <FIG> is another example analog peak-hold circuit that continuously tracks the greater, larger, etc. of: (a) the peak VPK_TRACK on the line <NUM> of the current half wave voltage as tracked by the first peak detector circuit <NUM>), and (b) the peak of the previous half wave cycle held as a voltage VPK on a line <NUM> by the second peak detector circuit <NUM>. The example peak detector circuit <NUM> includes an example operational amplifier <NUM> having a first input terminal 220A connected the input terminal 204A of the peak detector circuit <NUM>, and having an output terminal 220B connected to a terminal 222A of an example diode <NUM>. Another terminal 222B of the diode <NUM> is connected to a second input terminal 220C of the operational amplifier <NUM>, is connected to a terminal 224A of an example capacitor COUT <NUM>, and is connected to an output terminal 204B of the peak detector circuit <NUM>. Another terminal 224B of the capacitor COUT <NUM> is connected to ground. A first terminal 226A of a switch <NUM> is connected to the terminal 222B of the diode <NUM>, and a second terminal 226B of the switch <NUM> is connected to the terminal 222A of the diode <NUM>.

At half wave line cycle transitions, a reset signal RESET_VPK on the line <NUM>, which is connected to the terminal 226C of the switch <NUM>, causes the example switch <NUM> to close, thereby bypassing the example diode <NUM> to allow the voltage VPK_TRACK on the line <NUM> (even if lower than the voltage VPK on the line <NUM>) to be buffered and held as the voltage VPK on the line <NUM>. That is the output voltage VPK on the line <NUM> of the peak detector circuit <NUM> is set to the output voltage VPK_TRACK on the line <NUM> of the peak detector circuit <NUM>. The reset signal RESET_VPK on the line <NUM> for the second peak detector circuit <NUM> occurs prior to the reset signal RESET_TRACK on the line <NUM> for the first peak detector circuit <NUM>. Thereby, the peak voltage VPK_TRACK on the line <NUM> for the current half wave cycle is transferred from the first peak detector circuit <NUM> to the second peak detector circuit <NUM> as the voltage VPK on the line <NUM> prior to the voltage VPK_TRACK on the line <NUM> being reset at the first peak detector circuit <NUM>. To generate control signals for the peak detector circuits <NUM> and <NUM>, the example peak detector <NUM> includes an example control signal generator circuit <NUM>. The example control signal generator circuit <NUM> generates the reset signal RESET_TRACK <NUM> and the reset signal RESET_VPK on the line <NUM>.

To determine whether to start resets of the peak detector circuits <NUM> and <NUM>, the example control signal generator circuit <NUM> of <FIG> includes an example comparator <NUM> that compares the peak detector input voltage PDIN on the line <NUM> on a first input 234A of the comparator <NUM> to a threshold LINE_RESET_THRESHOLD on a line <NUM> at a second input 234B of the comparator <NUM>. Near the end of each half wave cycle, the peak detector input voltage PDIN on the line <NUM> will nominally satisfy the threshold LINE_RESET_THRESHOLD on the line <NUM> by falling below the threshold LINE _RESET_THRESHOLD on the line <NUM>, thereby causing a logic rising edge on an output LOW_LINE_DETECT on a line <NUM> by the comparator <NUM>.

The value of LINE RESET _THRESHOLD on the line <NUM> is selected to detect a zero crossing. Additionally, and/or alternatively, the value of LINE _RESET_THRESHOLD on the line <NUM> could be proportional to (e.g., be ten percent of) the most recent output voltage VPK_OUT on the line <NUM> as generated by, for example, a voltage divider <NUM>. Use of a proportional threshold LINE _RESET_THRESHOLD on the line <NUM> will result in the peak detector <NUM> updating at a consistent time proportional to the peak of the peak detector input voltage PDIN on the line <NUM> during steady state, leading to more predictable behavior.

To determine when to start resets of the peak detector circuits <NUM> and <NUM>, the example control signal generator circuit <NUM> of <FIG> includes an example OR gate <NUM>, an example timer <NUM>, and an example blanking circuit <NUM>. The OR gate <NUM> computes a logic OR of the output LOW_LINE_DETECT on the line <NUM> by the comparator <NUM> and an output <NUM> of the timer <NUM>. An output <NUM> of the OR gate <NUM> is a logic HIGH when either the output LOW_LINE_DETECT on the line <NUM> is a logic HIGH or the output <NUM> of the timer <NUM> is a logic HIGH signifying the timer <NUM> expired. In some examples, the maximum line period for public mains is <NUM> milliseconds (ms), and the timer <NUM> counts a time period that is larger than the maximum line half period. Accordingly, in the illustrated example, the timer <NUM> ensures the peak detector circuits <NUM> and <NUM> are reset at least every twelve milliseconds (<NUM>). In some applications, input AC voltage can have a different period (e.g., in airplanes where the period is generally <NUM>) so in this case we can select shorter time for the timer <NUM> (e.g., <NUM>).

During a blanking interval (e.g., a logic LOW portion of an output on the line <NUM> of the blanking circuit <NUM>), the peak detector circuits <NUM> and <NUM> are prevented from being reset. A logic LOW on the output on the line <NUM> prevents an output <NUM> of a logic AND gate <NUM> from transitioning from a logic LOW to a logic HIGH. The blanking interval prevents resets of the peak detector circuits <NUM> and <NUM> from occurring too close together. At the end of a blanking interval and if either the LOW_LINE_DETECT on the line <NUM> is logic HIGH or the timer <NUM> has expired, a logic rising edge occurs on the output <NUM> of the logic AND gate <NUM>. The logic rising edge on the output of the logic AND gate <NUM> resets the timer <NUM>.

To create the reset signal RESET_TRACK on the line <NUM> and the reset signal RESET _VPK on the line <NUM>, the example control signal generator circuit <NUM> includes a first example pulse generator <NUM> (e.g., a rising edge monostable pulser), and a second pulse generator <NUM> (e.g., a falling edge monostable pulser). When a rising edge occurs on the output <NUM> of the logic AND gate <NUM>, the pulse generator <NUM> sets the reset signal RESET_VPK on the line <NUM> to high, thereby closing switch <NUM> for a time duration of TIME2, which sets the voltage VPK on the line <NUM> equal to the voltage VPK_TRACK on the line <NUM>. When a logic falling edge occurs on the reset signal RESET _VPK on the line <NUM>, the second pulse generator <NUM> sets the reset signal RESET_TRACK on the line <NUM> to high, thereby closing the switch <NUM> for a time duration of TIME1, which resets the voltage on the line VPK_TRACK <NUM> to zero.

A flowchart representative of example hardware logic, hardware implemented state machine, and/or any combination thereof for implementing the control signal generator circuit <NUM> of <FIG> is shown in <FIG>. Although the example hardware logic, hardware implemented state machines is described with reference to the flowchart illustrated in <FIG>, many other methods of implementing the example control signal generator circuit <NUM> may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally, and/or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.), a processor.

The example hardware implemented state machine of <FIG> begins with waiting for the peak detector input voltage PDIN on the line <NUM> to satisfy a threshold (e.g., to fall below the threshold LINE _RESET_THRESHOLD on the line <NUM>) causing a rising edge on the output LOW_LINE_DETECT on the line <NUM> (block <NUM>), or the timer <NUM> (e.g., a <NUM> timer) to expire (block <NUM>). If the first of these two events (e.g., as determined by the OR gate <NUM>) occurs during a blanking interval (e.g., as determined by the blanking circuit <NUM>) (block <NUM>), it is ignored, waiting for the other event.

If the first of the two events occurs outside a blanking interval (e.g., <NUM>), a refresh sequence of the peak detectors <NUM> and <NUM> is carried out. The example pulse generator <NUM> (e.g., a rising edge monostable pulser) sets the reset signal RESET_VPK on the line <NUM> to high, thereby closing switch <NUM> (block <NUM>) for a time duration of TIME2 (e.g., <NUM>) (block <NUM>), which sets the voltage VPK on the line <NUM> equal to the voltage VPK_TRACK on the line <NUM> (block <NUM>). When the switch <NUM> is closed, a next blanking time is started (block <NUM>) and the timer <NUM> (e.g., a <NUM> timer) is reset (block <NUM>). Another pulse generator <NUM> (e.g., a falling edge monostable pulser triggered by the reset of the pulse generator <NUM>) sets the signal RESET_TRACK on the line <NUM> to high, thereby closing the switch <NUM> (block <NUM>) for a time duration of TIME1 (e.g., <NUM>) (block <NUM>), which resets the voltage VPK_TRACK on the line <NUM> to zero. After TIME1 elapses (block <NUM>), the signal RESET_TRACK on the line <NUM> is reset, thereby opening the switch <NUM> (block <NUM>). Opening the switch <NUM> completes the refresh sequence.

TIME1 is selected to be long enough and switch <NUM> has to be strong enough to allow VPK_TRACK on the line <NUM> to be discharged to a minimum value (e.g., <NUM>). TIME2 is selected to be long enough and the output of switch <NUM> has to be strong enough to set the voltage VPK on the line <NUM> to the voltage VPK_TRACK on the line <NUM> (e.g., <NUM>).

The duration of the blanking interval (e.g., <NUM>) is selected to be long enough to prevent multiple resets, multiple settings, multiple updates, etc. of the peak detector circuits <NUM> and <NUM> during a half wave cycle to space apart instances of resets, settings, updates, etc..

In case a zero crossing is not detected, the timer <NUM> ensures at least one update of the peak detector circuits <NUM> and <NUM> occurs during each half wave cycle. When a zero crossing is detected, the timer <NUM> avoids triggering a second refresh sequence.

An example operation of the peak detector <NUM> will be described with reference to the example graph of <FIG>. The illustrated example of <FIG> will be described with reference to five half wave cycles <NUM>, <NUM>, <NUM>, <NUM> and <NUM> of the peak detector input voltage PDIN on the line <NUM>. In the example half wave cycle <NUM>, the voltage VPK_TRACK on the line <NUM> and the voltage VPK_OUT on the line <NUM> track the peak detector input voltage PDIN on the line <NUM>. When the peak detector input voltage PDIN on the line <NUM> falls below the threshold LINE_RESET_THRESHOLD (see circle <NUM>), the voltage VPK_TRACK on the line <NUM> is transferred to the voltage VPK_OUT on the line <NUM> during a first interval <NUM> of length TIME1 for use in the half wave cycle <NUM>, and the voltage VPK_TRACK on the line <NUM> is reset to zero during a second interval <NUM> of length TIME2.

In the half wave cycle <NUM>, the peak detector input voltage PDIN on the line <NUM> has a larger peak than the previous half wave cycles <NUM> and <NUM>. Both the voltage VPK_TRACK on the line <NUM> and the voltage VPK_OUT on the line <NUM> instantaneously track the peak detector input voltage PDIN on the line <NUM>, thus preventing any circuit damage to the power converter <NUM>.

As shown in the half wave cycle <NUM>, the voltage VPK_TRACK on the line <NUM> is held over for the half wave cycle <NUM> even though the peak detector input voltage PDIN on the line <NUM> is not as large in half wave cycle <NUM>. This helps prevent any circuit damage to the power converter <NUM> in case the peak detector input voltage PDIN on the line <NUM> has any further positive transients.

The example peak detectors disclosed herein may be used in other applications where knowing or estimating the peak of a waveform according to teachings of this disclosure is beneficial. For example, detecting the envelope of AM modulated waveforms, inverter applications such as solar and wind power generation where line voltage or peak (RMS) monitoring is performed.

<FIG> illustrates an example AGC circuit <NUM> having an example peak detector <NUM>, such as that disclosed in connection with <FIG>. The example peak detector <NUM> of <FIG> tracks peaks of a received signal on a line <NUM> and outputs the peaks as the example voltage VPK_OUT on the line <NUM> of <FIG>. An example comparator <NUM> compares the voltage VPK_OUT on the line <NUM> with a target VPEAK_TARGET on a line <NUM>. Outputs of the comparator <NUM> on a line <NUM> are used to control the gain of a receive amplifier <NUM>.

<FIG> is a graph showing an example application of the automatic gain control circuit <NUM> of <FIG> to an RF signal. In the example of <FIG>, a received RF signal <NUM> has a peak amplitude <NUM> that increased at a time <NUM>. As described above, the peak detector <NUM> immediately tracks the increase in the peak amplitude <NUM> of the received signal <NUM>. In response to the increase in the peak amplitude <NUM> of the received signal <NUM>, the gain <NUM> of the receive amplifier <NUM> is lowered, thereby adjusting the gain controlled signal <NUM> to be generally even. In some examples, a zero-crossing is used rather than ten percent of peak for RF applications.

While an example peak detector topology including an operational amplifier <NUM>, <NUM>, a diode <NUM>, <NUM>, and a capacitor <NUM>, <NUM> is shown in <FIG>, other peak detector topologies may be used. <FIG> illustrates another example peak detector topology that may be used to implement the first peak detector circuit <NUM> and/or the second peak detector circuit <NUM>. Additionally, and/or alternatively, the first peak detector circuit <NUM> and/or the second peak detector circuit <NUM> may implement different peak detector topologies.

The example peak detector topology of <FIG> varies a gate voltage of an open drain PMOS device <NUM> based on the output of an operational amplifier <NUM>. When an input voltage <NUM> is greater than an output voltage <NUM>, the operation amplifier <NUM> turns on the open drain PMOS device, thereby charging a capacitor <NUM>. When the input voltage <NUM> is less than the output voltage <NUM>, the operational amplifier <NUM> turns off the open drain PMOS device, thereby maintaining the output voltage <NUM> across the capacitor <NUM>.

From the foregoing, it will be appreciated that example methods, apparatus and circuits have been disclosed that perform peak detection for power factor correction. The disclosed methods, apparatus and circuits improve the efficiency of power correction by eliminating analog-to-digital conversion, discrete comparators, complex switch network, complex switch control. Disclosed examples in stark contrast require only two half-wave peak-and-hold detectors and simple control logic.

Example peak detection methods, apparatus, systems and circuits are disclosed herein.

Claim 1:
A peak detector (<NUM>), comprising:
a first peak-hold circuit (<NUM>) having a first input terminal (<NUM>) and a second output terminal (202A)
a second peak-hold circuit (<NUM>) having a third input terminal (204A) coupled to the second output terminal, and a fourth output terminal (204B), characterised by: the second peak-hold circuit (<NUM>) including:
a first operational amplifier (<NUM>) having a fifth terminal (220A), a sixth terminal (220C) and a seventh terminal (220B), the fifth terminal coupled to the third input terminal;
a first diode (<NUM>) having an eighth terminal (222A) and a ninth terminal (222B), the eighth terminal coupled to the seventh terminal, and the ninth terminal coupled to the fourth output terminal;
a first switch (<NUM>) having a tenth terminal (226B), an eleventh terminal (226A) and a twelfth terminal (226C), the tenth terminal coupled to the seventh terminal and the eighth terminal, the eleventh terminal coupled to the ninth terminal and the fourth output terminal, and the twelfth terminal coupled to a first reset signal; and
a first capacitor (<NUM>) having a thirteenth terminal (224A) and a fourteenth terminal, the thirteenth terminal coupled to the fourth output terminal, the sixth terminal, the ninth terminal and the eleventh terminal, and the fourteenth terminal coupled to ground.