Patent Description:
Phase-change memory (PCM) technology such as multi-stack cross-point PCM is a promising alternative to other non-volatile memory (NVM) technology. There exists a continuous drive to increase electro-thermal isolation of phase-change memory elements in order to optimize PCM operation including, for example, programming current and shape of a threshold voltage (VT) to current (I) characteristic, VT-I. An example of background art may be found in US patent application <CIT>.

Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.

The term "coupled" may refer to a direct connection, an indirect connection, or an indirect communication.

As used herein, the term "module" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, state machine, and/or other suitable components that provide the described functionality.

<FIG> schematically illustrates a top view of an example die <NUM> in wafer form <NUM> and in singulated form <NUM>, in accordance with some embodiments. In some embodiments, the die <NUM> may be one of a plurality of dies (e.g., dies <NUM>, 102a, 102b) of a wafer <NUM> composed of semiconductor material such as, for example, silicon or other suitable material. The plurality of dies may be formed on a surface of the wafer <NUM>. Each of the dies may be a repeating unit of a semiconductor product that includes a phase-change memory (PCM) device as described herein. For example, the die <NUM> may include circuitry <NUM> of a PCM device in accordance with some embodiments. According to various embodiments, the circuitry <NUM> includes one or more PCM elements (e.g., cells), which may be configured in an array. The PCM elements may include, for example, a phase-change material such as a chalcogenide glass that can be switched between crystalline and amorphous states with the application of heat produced by an electric current. The state (e.g., crystalline/amorphous) of the phase-change material may correspond with a logical value (e.g., <NUM> or <NUM>) of the PCM elements. The circuitry <NUM> may be part of a PCM and switch (PCMS) device in some embodiments. That is, the PCM elements may include a switch such as, for example, an ovonic threshold switch (OTS) configured for use in selection/programming operations of the PCM elements.

The circuitry <NUM> further includes one or more bit-lines and one or more word-lines coupled to the PCM elements. The bit-lines and word-lines may be configured such that each of the PCM elements is disposed at an intersection of each individual bit-line and word-line, in some embodiments. A voltage or bias can be applied to a target PCM element of the PCM elements using the word-lines and the bit-lines to select the target cell for a read or write operation. Bit-line drivers may be coupled to the bit-lines and word-line drivers may be coupled to the word-lines to facilitate decoding/selection of the PCM elements. Capacitors and resistors may be coupled to the bit-lines and the word-lines. The circuitry <NUM> may include other suitable devices and configurations in some embodiments. For example, the circuitry <NUM> may include one or more modules that are configured to perform read, program, verify and/or analysis operations.

In some embodiments, the circuitry <NUM> may be formed using PCM fabrication techniques and/or other suitable semiconductor fabrication techniques. It is noted that the circuitry <NUM> is only schematically depicted in <FIG> and may represent a wide variety of suitable logic or memory in the form of circuitry including, for example, one or more state machines including circuitry and/or instructions in storage (e.g., firmware or software) configured to perform actions such as read, program, verify and/or analysis operations.

After a fabrication process of the semiconductor product is complete, the wafer <NUM> may undergo a singulation process in which each of the dies (e.g., dies <NUM>, 102a, 102b) is separated from one another to provide discrete "chips" of the semiconductor product. The wafer <NUM> may be any of a variety of sizes. In some embodiments, the wafer <NUM> has a diameter ranging from about <NUM> to about <NUM>. The wafer <NUM> may include other sizes and/or other shapes in other embodiments. According to various embodiments, the circuitry <NUM> may be disposed on a semiconductor substrate in wafer form <NUM> or singulated form <NUM>. In some embodiments, the die <NUM> may include logic or memory, or combinations thereof.

<FIG> schematically illustrates a cross-section side view of an integrated circuit (IC) assembly <NUM>, in accordance with some embodiments. In some embodiments, the IC assembly <NUM> may include one or more dies (hereinafter "die <NUM>") electrically and/or physically coupled with a package substrate <NUM>. The die <NUM> may include circuitry (e.g., circuitry <NUM> of <FIG>) such as a PCM device as described herein. In some embodiments, the package substrate <NUM> may be coupled with a circuit board <NUM>, as can be seen.

The die <NUM> may represent a discrete product made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching and the like used in connection with forming PCM devices. In some embodiments, the die <NUM> may be, include, or be a part of a processor, memory, system-on-chip (SoC) or ASIC in some embodiments. In some embodiments, an electrically insulative material such as, for example, molding compound or underfill material (not shown) may encapsulate at least a portion of the die <NUM> and/or die-level interconnect structures <NUM>.

The die <NUM> can be attached to the package substrate <NUM> according to a wide variety of suitable configurations including, for example, being directly coupled with the package substrate <NUM> in a flip-chip configuration, as depicted. In the flip-chip configuration, an active side, S1, of the die <NUM> including active circuitry is attached to a surface of the package substrate <NUM> using die-level interconnect structures <NUM> such as bumps, pillars, or other suitable structures that may also electrically couple the die <NUM> with the package substrate <NUM>. The active side <NUM> of the die <NUM> may include circuitry such as, for example, PCM elements. An inactive side, S2, may be disposed opposite to the active side S1, as can be seen. In other embodiments, the die <NUM> may be disposed on another die that is coupled with the package substrate <NUM> in any of a variety of suitable stacked die configurations. For example, a processor die may be coupled with the package substrate <NUM> in a flip-chip configuration and the die <NUM> may be mounted on the processor die in a flip-chip configuration and electrically coupled with the package substrate using through-silicon vias (TSVs) formed through the processor die. In still other embodiments, the die <NUM> may be embedded in the package substrate <NUM> or coupled with a die that is embedded in the package substrate <NUM>. Other dies may be coupled with the package substrate <NUM> in a side-by-side configuration with the die <NUM> in other embodiments.

In some embodiments, the die-level interconnect structures <NUM> may be configured to route electrical signals between the die <NUM> and the package substrate <NUM>. The electrical signals may include, for example, input/output (I/O) signals and/or power/ground signals that are used in connection with operation of the die. The die-level interconnect structures <NUM> may be coupled with corresponding die contacts disposed on the active side S1 of the die <NUM> and corresponding package contacts disposed on the package substrate <NUM>. The die contacts and/or package contacts may include, for example, pads, vias, trenches, traces and/or other suitable contact structures.

In some embodiments, the package substrate <NUM> is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The package substrate <NUM> may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.

The package substrate <NUM> may include electrical routing features configured to route electrical signals to or from the die <NUM>. The electrical routing features may include, for example, package contacts (e.g., pads <NUM>) disposed on one or more surfaces of the package substrate <NUM> and/or internal routing features (not shown) such as, for example, trenches, vias or other interconnect structures to route electrical signals through the package substrate <NUM>.

The circuit board <NUM> may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, the circuit board <NUM> may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant <NUM> (FR-<NUM>), FR-<NUM>, cotton paper and epoxy materials such as CEM-<NUM> or CEM-<NUM>, or woven glass materials that are laminated together using an epoxy resin prepreg material. Interconnect structures (not shown) such as traces, trenches, vias may be formed through the electrically insulating layers to route the electrical signals of the die <NUM> through the circuit board <NUM>. The circuit board <NUM> may be composed of other suitable materials in other embodiments. In some embodiments, the circuit board <NUM> is a motherboard (e.g., motherboard <NUM> of <FIG>).

Package-level interconnects such as, for example, solder balls <NUM> may be coupled to pads <NUM> on the package substrate <NUM> and/or on the circuit board <NUM> to form corresponding solder joints that are configured to further route the electrical signals between the package substrate <NUM> and the circuit board <NUM>. The pads <NUM> may be composed of any suitable electrically conductive material such as metal including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. The package-level interconnect may include other structures and/or configurations including, for example, land-grid array (LGA) structures and the like.

The IC assembly <NUM> may include a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire-bonding configurations, interposers, multi-chip package configurations including system-in-package (SiP) and/or package-on-package (PoP) configurations. Other suitable techniques to route electrical signals between the die <NUM> and other components of the IC assembly <NUM> may be used in some embodiments. <FIG><FIG>schematically illustrate cross-section side views of a phase-change memory (PCM) device during various stages of fabrication, in accordance with some embodiments. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG> depict a cross-section side of the PCM device <NUM> from a same, first perspective and <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG> depict a cross-section side of the PCM device <NUM> from a same, second perspective that is perpendicular to the first perspective. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> schematically illustrate a top view of the phase-change memory (PCM) device <NUM> during various stages of fabrication, in accordance with some embodiments. <FIG> represent the PCM device <NUM> during a same stage of fabrication, <FIG> represent the PCM device <NUM> during a same stage of fabrication, <FIG> represent the PCM device <NUM> during a same stage of fabrication, and so forth. The indicators P'-P", BL'-BL" and WL'-WL" are provided to facilitate understanding of the relative orientation between the different perspectives (e.g., <FIG>). For example, <FIG> may represent a cross-section along WL'-WL", <FIG> may represent a cross-section along BL'-BL", and <FIG> may represent a cross-section along P'-P".

Referring to <FIG>, a PCM device <NUM> is depicted subsequent to depositing an electrically conductive material such as word-line metal <NUM> on a substrate <NUM> to form a word-line layer and depositing materials to form a stack of layers on the word-line metal <NUM>. One or more intervening layers and/or structures (hereinafter "circuitry <NUM>") may be disposed between the substrate <NUM> and the word-line metal <NUM>. For example, the circuitry <NUM> may include complementary metal-oxide-semiconductor (CMOS) devices and/or metallization that are formed on the substrate <NUM> between the word-line metal <NUM> and the substrate <NUM>. The substrate <NUM> may be a semiconductor substrate such as, for example, silicon in some embodiments. The substrate <NUM> is not shown in the remainder of the figures to avoid obscuring other aspects. The word-line metal <NUM> may include, for example, tungsten. Other suitable materials for the substrate <NUM> and the word-line metal <NUM> may be used in other embodiments.

The stack of layers may include a bottom electrode layer <NUM> disposed on the word-line metal <NUM>, select device (SD) layer <NUM> disposed on the bottom electrode layer <NUM>, middle electrode layer <NUM> disposed on the SD layer <NUM>, phase-change material (PM) layer <NUM> disposed on the middle electrode layer <NUM>, and a first top electrode layer (TE1) <NUM> disposed on the PM layer <NUM>, as can be seen. Each layer of the stack of layers may be deposited according to any suitable technique.

According to various embodiments, the bottom electrode layer <NUM> may be composed of one or more conductive and/or semiconductive materials such as, for example, carbon (C), carbon nitride (CxNy); n-doped polysilicon and p-doped polysilicon; metals including, Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicides nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; and conductive metal oxides including RuO<NUM>. The SD layer <NUM> may include a P-N diode, a MIEC (Mixed Ionic Electronic Conduction) device or an OTS (Ovonic Threshold Switch) based on chalcogenide alloys with composition including any one of the chalcogenide alloy systems described for the storage element (e.g., the PM layer <NUM>) and, in addition, may further include an element that can suppress crystallization. The middle electrode layer <NUM> may be composed of one or more conductive and/or semiconductive materials such as, for example, carbon (C), carbon nitride (CxNy); n-doped polysilicon and p-doped polysilicon; metals including, Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicides nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; and conductive metal oxides including RuO<NUM>. The PM layer <NUM> may be composed of a phase-change material such as a chalcogenide glass that can be switched between crystalline and amorphous states with the application of heat produced by an electric current such as an alloy including at least two of the elements among Germanium, Antimony, Tellurium, Silicon, Indium, Selenium, Sulphur, Nitrogen and Carbon. The first top electrode layer <NUM> may be composed of an electrically conductive material such as a metal or semi-metal (e.g., semiconductive material) having a resistivity ranging from <NUM> milli-Ohm·centimeter (mOhm·cm) to <NUM> mOhm·cm such as, for example, carbon (C), carbon nitride (CxNy); n-doped polysilicon and p-doped polysilicon; metals including, Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicides nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; and conductive metal oxides including RuO<NUM> The layers <NUM>, <NUM>, <NUM>, <NUM> and <NUM> may be composed of other suitable materials having other suitable properties in other embodiments.

In some embodiments, the first top electrode layer <NUM> may have a thickness ranging from <NUM> nanometers (nm) to <NUM>. In one embodiment, the first top electrode layer <NUM> may have a thickness of about <NUM> or less. In flows that only form the first top electrode layer <NUM>, it may be difficult to increase the first top electrode layer <NUM> greater than <NUM> owing to the height of the partial stack to be etched at word-line definition, coupled with mechanical weakness of the phase-change material and a desire to reliably separate adjacent word-lines. The first top electrode layer <NUM> may have other suitable thicknesses in other embodiments.

Referring to <FIG>, the PCM device <NUM> is depicted subsequent to word-line definition. The word-line definition may be accomplished, for example, by using a patterning process such as lithography and/or etch processes to selectively remove portions of the stack of layers to provide lines <NUM> of the stack of layers on the underlying circuitry <NUM> with trenches <NUM> between the lines <NUM>, as can be seen. The trenches <NUM> may separate PCM elements from one another. In <FIG>, the word-line metal <NUM> is patterned such that the word-line extends in a direction in and out of the page. In <FIG>, the word-line metal <NUM> is disposed beneath the first top electrode layer <NUM> and extends in a direction from left to right across the page.

Referring to <FIG>, the PCM device <NUM> is depicted subsequent to depositing dielectric material to fill a region between the lines <NUM>. For example, in the depicted embodiment, a dielectric liner <NUM> may be conformally deposited on surfaces of the stack of layers (e.g., on the lines <NUM>), on the word-line metal <NUM> and on the circuitry <NUM>, as can be seen. A dielectric fill material <NUM> may be deposited to fill the region between the lines <NUM> using any suitable technique. In some embodiments, the dielectric liner <NUM> may be composed of silicon nitride (Si<NUM>N<NUM> or in general SixNy, where x and y represent any suitable relative quantity) and the dielectric fill material <NUM> may be composed of silicon oxide (SiO<NUM>). The dielectric liner <NUM> and the dielectric fill material <NUM> may be composed of other suitable materials in other embodiments.

Referring to <FIG>, the PCM device <NUM> is depicted subsequent to recessing the dielectric material (e.g., dielectric fill material <NUM> and dielectric liner <NUM>) to expose the first top electrode layer <NUM>. In some embodiments, a planarizing process such as, for example, chemical-mechanical polish (CMP) may be used to recess the dielectric material. Other suitable techniques to recess the dielectric material may be used in other embodiments.

Referring to <FIG>, the PCM device <NUM> is depicted subsequent to depositing a second top electrode (TE2) layer <NUM> on the first top electrode layer <NUM> and depositing a bit-line metal <NUM> on the second top electrode layer <NUM> to form a bit-line layer. In some embodiments, the second top electrode layer <NUM> may be deposited on portions of the dielectric liner <NUM> and the dielectric fill material <NUM>, as can be seen in <FIG>. According to various embodiments, the second top electrode layer <NUM> may be deposited using, for example, physical vapor deposition (PVD) or chemical vapor deposition, among other suitable techniques. The second top electrode layer <NUM> may be composed of an electrically conductive material such as a metal or semi-metal having a resistivity ranging from <NUM> mili-Ohm·centimeter (mOhm·cm) to <NUM> mOhm·cm. In some embodiments, the second top electrode layer <NUM> may include one or more conductive and semiconductive materials such as, for example, carbon (C), carbon nitride (CxNy); n-doped polysilicon and p-doped polysilicon; metals including, Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicides, tungsten silicides, nickel silicides, cobalt silicides and titanium silicides; conductive metal silicides nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; and conductive metal oxides including RuO<NUM>. The second top electrode layer <NUM> may be suitably integrated (e.g., etched, cleaned and sealed) into the fabrication process flow and may demonstrate good adhesion with the first top electrode layer <NUM> and/or the bit-line metal <NUM>. In some embodiments, the second top electrode layer <NUM> may have a same chemical composition as the first top electrode layer <NUM>. In other embodiments, the second top electrode layer <NUM> may have a different chemical composition than the first top electrode layer <NUM>. The second top electrode layer <NUM> may be composed of other suitable materials and/or may have other suitable properties in other embodiments.

In some embodiments, the second top electrode layer <NUM> may have a thickness ranging from <NUM> nanometers (nm) to <NUM>. In one embodiment, the second top electrode layer <NUM> may have a thickness of about <NUM>. The second top electrode layer <NUM> may be composed of other suitable materials, may be deposited by other suitable techniques and/or may have other suitable thicknesses in other embodiments. The bit-line metal <NUM> may be composed of any suitable metal including, for example, tungsten and may be deposited using any suitable technique.

Referring to <FIG>, the PCM device <NUM> is depicted subsequent to bit-line definition. Bit-line definition is accomplished using patterning processes such as, for example, lithography and/or etch processes to selectively remove portions of the bit-line metal <NUM>, the second top electrode <NUM>, and the stack of layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> to provide individual PCM elements <NUM> of an array of PCM elements on the underlying circuitry <NUM>, as can be seen. In <FIG>, the bit-line metal <NUM> extends in a direction in and out of the page. In <FIG>, the bit-line metal <NUM> is patterned such that the bit-line extends in a direction from left to right across the page, perpendicular to the word-lines.

In some embodiments, the second top electrode layer <NUM> is disposed on and in direct contact with the first top electrode layer <NUM>, as can be seen. The bit-line metal <NUM> is disposed on and in direct contact with the second top electrode layer <NUM>. In some embodiments, individual PCM elements <NUM> including the stack of layers (e.g., PM layer <NUM>) may be separated by electrically insulative pillars <NUM>. In the depicted embodiment, the electrically insulative pillars <NUM> include the dielectric materials <NUM>, <NUM>. As can be seen in <FIG>, material of the second top electrode layer <NUM> is disposed between the bit-line metal <NUM> and the electrically insulative pillars <NUM>. For example, in the vertical direction (e.g., a direction parallel with a height of the individual PCM elements <NUM>), material of the second top electrode layer <NUM> is disposed directly between the electrically insulative pillars <NUM> and the bit-line metal <NUM>. Material of the first top electrode layer <NUM> may be disposed directly between (e.g., in a horizontal direction perpendicular to the vertical direction) adjacent pillars of the electrically insulative pillars <NUM>, as can be seen. The material of the first top electrode layer <NUM> may not be disposed directly between the electrically insulative pillars <NUM> and the bit-line metal <NUM> in some embodiments.

Forming the second top electrode layer <NUM> on the first top electrode layer <NUM> may increase a comprehensive thickness (e.g., beyond ~<NUM>) of the top electrode of the individual PCM elements <NUM>. Techniques and configurations described herein may overcome challenges associated with increasing the top electrode thickness beyond <NUM> due to the height of the partial stack to be etched at word-line definition together with mechanical weakness of the phase-change material itself and an ability to reliably separate adjacent word-lines. Previously, these challenges may have constrained optimization of the phase material operation in terms of programming current and/or shape of the VT-I characteristic. The presently described fabrication techniques and PCM configurations may provide a thicker top electrode to overcome such constraints to allow further optimization of operation. For example, a height of the partial stack to be etched at word-line definition may not be increased. In this manner, mechanical stability of the stack may not be compromised, which may avoid shorts during word-line definition. In some embodiments, a total thickness of the top electrode (e.g., thickness of TE1+TE2) may be more than doubled compared with a flow that only forms TE1. For example, in some embodiments, the total thickness of TE1+TE2 may be about <NUM>-<NUM>. In some embodiments, the second top electrode layer <NUM> provides a reliable, continuous etch stop during bit-line definition (e.g., etching of the bit-line metal <NUM>), which may allow use of a thicker bit-line metal <NUM>, which may reduce bit-line resistance for better current delivery in the whole array.

Referring to <FIG>, the PCM device <NUM> is depicted subsequent to bit-line sealing and filling. As can be seen in <FIG>, a dielectric liner <NUM> may be conformally deposited on the individual PCM elements <NUM> and on the word-line metal <NUM>. A dielectric fill material <NUM> may be deposited on the dielectric liner <NUM> to fill a region between the individual PCM elements <NUM>. In some embodiments, the dielectric liner <NUM> and dielectric fill material <NUM> may comport with embodiment described in connection with the dielectric liner <NUM> and the dielectric fill material <NUM>, respectively. In other embodiments, the dielectric liner <NUM> and dielectric fill material <NUM> may be composed of suitable dielectric materials other than materials used for the dielectric liner <NUM> and the dielectric fill material <NUM>.

<FIG>schematically illustrate cross-section side views of a phase-change memory (PCM) device <NUM> during fabrication, in accordance with some embodiments. For example, <FIG> may represent a same stage of fabrication as <FIG>, that is, subsequent to bit-line sealing and filling, but for a different region of the PCM device <NUM>. <FIG> and <FIG> may schematically represent cross-sections of a final product such as, for example, a memory device that is ready to be sold to a customer, according to various embodiments.

The PCM device <NUM> may represent a decoding region. The decoding region may share a same plane as the individual PCM elements <NUM> of <FIG>. For example, the PCM device <NUM> includes a bit-line metal <NUM> disposed on a second top electrode layer <NUM>. The bit-line metal <NUM> and the second top electrode layer <NUM> of <FIG> may be on a same plane as the bit-line metal <NUM> and the second top electrode layer <NUM> of <FIG>. The individual PCM elements <NUM> of <FIG> may be in or out of the page relative to the PCM device <NUM> depicted in <FIG>.

The PCM device <NUM> includes a bit-line via <NUM> and a word-line via <NUM>, coupled as can be seen. The bit-line via <NUM> and the word-line via <NUM> each represent one of a plurality of vias formed in a decoding region that are in a same plane as the individual PCM elements <NUM> of <FIG>. In some embodiments, the second top electrode layer <NUM> is disposed directly between the bit-line metal <NUM> and the bit-line via <NUM>, as can be seen. In some embodiments, the second top electrode layer <NUM> may be disposed on the dielectric fill material <NUM>, as can be seen. The dielectric fill material <NUM> may represent multiple layers of dielectric material in some embodiments.

Barrier liners <NUM> and <NUM> may be formed to encapsulate electrically conductive material of the respective bit-line via <NUM> and word-line via <NUM>. In some embodiments, the word-line via <NUM> and the bit-line via <NUM> may each be composed of tungsten (W) and the barrier liners <NUM>, <NUM> may be composed of titanium nitride (TiN) or tantalum nitride (TaN). The word-line via <NUM>, bit-line via <NUM> and the barrier liners <NUM>, <NUM> may be composed of other suitable materials in other embodiments.

Formation of the second top electrode layer <NUM> as described herein results in the second top electrode layer <NUM> being present between the bit-line metal <NUM> and underlying vias (e.g., bit-line via <NUM> and word-line via <NUM>). A thickness of the second top electrode layer <NUM> may be tuned to create adjustable ballast between decoders and cells on the bit-line side. In a case where the thickness and/or resistivity of the second top electrode layer <NUM> creates a series resistance that is too high, a loose mask may be introduced in order to remove the second top electrode layer <NUM> from the decoding region, possibly by over-etching of the vias at the end of bit-line metal etching. If full symmetry of carbon morphology is desired for symmetric cell operation, thickness of the bottom electrode may be adjusted (e.g., by over-etching during bit-line definition). In some embodiments resistivity of the second top electrode layer <NUM> may be less than <NUM> mOhm·cm and have a thickness less than or equal to about <NUM> to reduce impact of increasing resistance in the bit-line path. For example, for a via area equal to ~<NUM>×<NUM><NUM>, a second top electrode layer <NUM> having resistivity and thickness as described may add resistance in the bit-line path that is lower than <NUM> kilo-Ohm (KOhm).

<FIG> is a flow diagram of a method <NUM> of fabricating a PCM device (e.g., PCM device <NUM> of <FIG>), in accordance with some embodiments. The method <NUM> may comport with embodiments described in connection with <FIG> and vice versa.

At <NUM>, the method <NUM> may include providing a substrate (e.g., substrate <NUM> of <FIG>). The substrate may include, for example, a semiconductor substrate such as a silicon wafer or die.

At <NUM>, the method <NUM> may include forming a plurality of phase-change memory (PCM) elements on the substrate, wherein individual PCM elements (e.g., individual PCM elements <NUM> of <FIG>) of the plurality of PCM elements include a phase-change material layer (e.g., PM layer <NUM> of <FIG>), a first top electrode layer (e.g., first top electrode layer <NUM> of <FIG>) disposed on the phase-change layer and in direct contact with the phase-change layer, and a second top electrode layer (e.g., second top electrode layer <NUM> of <FIG>) disposed on the first top electrode layer and in direct contact with the first top electrode layer.

According to various embodiments, forming the plurality of PCM elements on the substrate may include forming a stack of layers. For example, the stack of layers may be formed by depositing a word-line layer (e.g., word-line metal <NUM> of <FIG>) on the substrate, depositing a bottom electrode layer (e.g., bottom electrode layer <NUM> of <FIG>) on the word-line layer, depositing a select device layer (e.g., select device layer <NUM> of <FIG>) on the bottom electrode layer, depositing a middle electrode layer (e.g., middle electrode layer <NUM> of <FIG>) on the select device layer, depositing a phase-change material layer (e.g., phase-change material layer <NUM> of <FIG>) on the middle electrode layer, and depositing a first top electrode layer (e.g., first top electrode layer <NUM> of <FIG>) on the phase-change material layer.

The stack of layers may be patterned to provide the individual PCM elements. Patterning may include, for example, lithography and/or etch processes. For example, word-line definition as described in connection with <FIG> may be performed and/or bit-line definition as described in connection with <FIG> may be performed to provide the individual PCM elements.

In some embodiments, dielectric material may be deposited to fill a region between the individual PCM elements. For example, a dielectric liner (e.g., dielectric liner <NUM>) may be conformally deposited on the stack of layers of the individual PCM elements and a dielectric fill material (e.g., dielectric fill material <NUM>) may be deposited to fill a remaining region between the individual PCM elements.

In some embodiments, techniques described in connection with <FIG> may be performed to deposit dielectric material. The dielectric material may be recessed to expose the first top electrode layer using, for example, techniques described in connection with <FIG>. In some embodiments, the second top electrode layer may be deposited on the first top electrode layer using, for example, techniques described in connection with <FIG>. A bit-line layer may be deposited on the second top electrode layer using, for example, techniques described in connection with <FIG>.

Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.

Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired. <FIG> schematically illustrates an example system (e.g., a computing device <NUM>) that includes a PCM device (e.g., PCM device <NUM> of <FIG>) in accordance with various embodiments described herein. The computing device <NUM> may house a board such as motherboard <NUM>. The motherboard <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> may be physically and electrically coupled to the motherboard <NUM>. In some implementations, the at least one communication chip <NUM> may also be physically and electrically coupled to the motherboard <NUM>. In further implementations, the communication chip <NUM> may be part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the motherboard <NUM>. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., PCM <NUM> or ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

According to various embodiments, the PCM <NUM> may comport with embodiments described herein. For example, the PCM <NUM> may include a PCM device (e.g., PCM device <NUM> of <FIG>) as described herein.

The communication chip <NUM> may enable wireless communications for the transfer of data to and from the computing device <NUM>. The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication chip <NUM> may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip <NUM> may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication chip <NUM> may operate in accordance with other wireless protocols in other embodiments.

For instance, a first communication chip <NUM> may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip <NUM> may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

In various implementations, the computing device <NUM> may be a mobile computing device, a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

According to various embodiments, the present disclosure describes an apparatus. Example <NUM> of an apparatus may include a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include: a phase-change material layer; a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer; and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Example <NUM> may include the apparatus of Example <NUM>, wherein the individual PCM elements of the plurality of PCM elements further include a bit-line disposed on the second electrode layer and in direct contact with the second electrode layer. Example <NUM> may include the apparatus of Example <NUM>, wherein the individual PCM elements of the plurality of PCM elements are separated by electrically insulative pillars and material of the second electrode layer is disposed between the bit-line and the electrically insulative pillars. Example <NUM> may include the apparatus of Example <NUM>, wherein material of the first electrode layer is disposed between adjacent pillars of the electrically insulative pillars. Example <NUM> may include the apparatus of any of Examples <NUM>-<NUM>, wherein the individual PCM elements of the plurality of PCM elements further include: a word-line; a select device layer; a third electrode layer disposed between the select device layer and the phase-change material layer; and a fourth electrode layer disposed between the word-line and the select device layer. Example <NUM> may include the apparatus of any of Examples <NUM>-<NUM>, further comprising a plurality of vias disposed in a decoding region that is in a same plane as the individual PCM elements, wherein the second electrode layer is disposed between the bit-line and a via of the plurality of vias. Example <NUM> may include the apparatus of any of Examples <NUM>-<NUM>, wherein the first electrode layer and the second electrode layer have a different chemical composition and the first electrode layer and the second electrode layer have a resistivity from <NUM> milli-Ohm·centimeter (mOhm·cm) to <NUM> mOhm·cm. Example <NUM> includes the apparatus of any of Examples <NUM>-<NUM>, wherein the second electrode layer is configured to serve as an etch stop layer for bit-line definition.

According to various embodiments, the present disclosure describes a method. Example <NUM> of a method may include providing a substrate and forming a plurality of phase-change memory (PCM) elements on the substrate, wherein individual PCM elements of the plurality of PCM elements include: a phase-change material layer; a first top electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer; and a second top electrode layer disposed on the first top electrode layer and in direct contact with the first top electrode layer. Example <NUM> may include the method of Example <NUM>, wherein forming the plurality of PCM elements comprises forming a stack of layers by: depositing a word-line layer on the substrate; depositing a bottom electrode layer on the word-line layer; depositing a select device layer on the bottom electrode layer; depositing a middle electrode layer on the select device layer; depositing the phase-change material layer on the middle electrode layer; and depositing the first top electrode layer on the phase-change material layer; and patterning the stack of layers to provide the individual PCM elements. Example <NUM> may include the method of Example <NUM>, further comprising depositing dielectric material to fill a region between the individual PCM elements. Example <NUM> may include the method of Example <NUM>, wherein depositing the dielectric material comprises conformally depositing a dielectric liner on the individual PCM elements and depositing a dielectric material on the dielectric liner to fill the region between the individual PCM elements. Example <NUM> may include the method of Example <NUM>, further comprising recessing the dielectric material to expose the first top electrode layer. Example <NUM> may include the method of Example <NUM>, further comprising depositing the second top electrode layer on the first top electrode layer. Example <NUM> may include the method of Example <NUM>, further comprising depositing a bit-line layer on the second top electrode layer. Example <NUM> may include the method of Example <NUM>, wherein material of the second top electrode layer is disposed between the bit-line layer and the dielectric material.

According to various embodiments, the present disclosure describes a system. Example <NUM> of a system may include a circuit board and a die coupled with the circuit board, the die comprising a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include: a phase-change material layer; a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer; and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Example <NUM> may include the system of Example <NUM>, wherein the individual PCM elements of the plurality of PCM elements further include a bit-line disposed on the second electrode layer and in direct contact with the second electrode layer. Example <NUM> may include the system of Example <NUM>, wherein the individual PCM elements of the plurality of PCM elements are separated by electrically insulative pillars and material of the second electrode layer is disposed between the bit-line and the electrically insulative pillars. Example <NUM> may include the system of any of Examples <NUM>-<NUM>, wherein the system is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.

Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and" may be "and/or"). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

Claim 1:
An apparatus (<NUM>) comprising:
a plurality of vias disposed in a plane; and a plurality of phase-change memory, PCM, elements (<NUM>), wherein individual PCM elements of the plurality of PCM elements include:
a phase-change material layer (<NUM>);
a first electrode layer (<NUM>) disposed on the phase-change material layer and in direct contact with the phase-change material layer;
a second electrode layer (<NUM>) disposed on the first electrode layer (<NUM>) and in direct contact with the first electrode layer; and
a bit-line (<NUM>) disposed on the second electrode layer and in direct contact with the second electrode layer, wherein the second electrode layer is further disposed between the bit-line and a via of the plurality of vias,
characterized in that,
the second electrode layer is configured to serve as an etch stop layer for bit-line definition.