Patent Description:
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device and each interconnect becomes increasingly significant.

<CIT> relates to an arrangement in which a metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

Document <CIT> relates to methods of forming contact structures for semiconductor devices and the resulting devices.

Document <CIT> relates to a memory cell having improved mechanical stability.

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

Aspects and embodiments of the present invention are set out in the appended claims.

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

For purposes of illustrating self-aligned vias integrated in the BEOL, described herein, it might be useful to first understand phenomena that may come into play during IC fabrication. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

ICs commonly include electrically conductive microelectronic structures, which are known in the art as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. In this context, the term "metallization stack" may be used to describe a stacked series of electrically insulated metallic interconnecting wires that are used to connect together various devices of an IC, where adjacent layers of the stack are linked together through the use of electrical contacts and vias.

Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer, which may be referred to as a via location opening. Next, an opening for the via may be etched in the dielectric layer by using the location opening in the photoresist layer as an etch mask. This opening in the dielectric layer is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

In the past, the sizes and the spacing of vias have progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of ICs (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of the size of the vias is the critical dimension of the via opening. One measure of the spacing of the vias is the via pitch. Via pitch represents the center-to-center distance between the closest adjacent vias.

When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves, especially when the pitches are around <NUM> nanometers (nm) or less and/or when the critical dimensions of the via openings are around <NUM> or less. One such challenge is that the overlay between the vias and the underlying electrically conductive structures (e.g., gate and trench contacts) generally need to be controlled to high tolerances on the order of a quarter of the via pitch. Edge placement error margin is a measure of how much misalignment between a via and the underlying electrically conductive structure on which the via was supposed to land may be tolerated.

Misalignment between a via and underlying electrically conductive structures to which the via is supposed to make a contact to is one of the main contributors to BEOL resistance-capacitance (RC) delays and needs to be minimized. In particular, it would be desirable to maximize the area overlap between the bottom of a via and the top of an underlying bottom metal line, as well as to maximize the area overlap between the top of the via and the bottom of a top metal line above the via. As used herein, the term "bottom metal line" refers to any electrically conductive structure that is provided below the via (i.e., so that the bottom metal line is between the via and a support structure over which the devices and interconnects are built) and to which the via is supposed to make an electrical contact to. Similarly, as used herein, the term "top metal line" refers to any electrically conductive structure that is provided above the via (i.e., so that the via is between the support structure and the top metal line) and to which the via is supposed to make an electrical contact to. In various embodiments, such bottom and top metal lines may include electrically conductive structures other than lines/trenches (e.g., the bottom metal line may be a gate contact), and/or may be formed, or include, electrically conductive materials other than metals.

Disclosed herein are methods for manufacturing an IC structure, e.g., for manufacturing a metallization stack portion of an IC structure, with one or more self-aligned vias integrated in the BEOL provided over a support structure (e.g., a substrate, a wafer, or a chip), and related semiconductor devices. The methods may employ direct metal etch for scaling the BEOL pitches of the metallization layers. In one aspect, an example method results in fabrication of a via that is self-aligned to, both, a metal line above it (i.e., the top metal line) and a metal line below it (i.e., the bottom metal line). Methods described herein may provide improvements in terms of one or more of reducing the misalignment between vias and electrically conductive structures connected thereto, reducing the RC delays, and increasing reliability in the final IC structures.

IC structures as described herein, in particular metallization stacks with self-aligned vias integrated in the BEOL as described herein, may be used for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Further, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g., <FIG>, such a collection may be referred to herein without the letters, e.g., as "<FIG>.

In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so "ideal" when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.

The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. The terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, if used, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide. In another example, a term "interconnect" is used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the "interconnect" may refer to both trench contacts (also sometimes referred to as "lines") and vias. In general, a term "trench contact" is used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such trench contacts are typically stacked into several levels, or several layers of metallization stacks. On the other hand, the term "via" is used to describe an electrically conductive element that interconnects two or more trench contacts of different levels. To that end, vias are provided substantially perpendicularly to the plane of an IC chip. A via may interconnect two trench contacts in adjacent levels or two trench contacts in not adjacent levels. A term "metallization stack" refers to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value based on the context of a particular value as described herein or as known in the art.

<FIG> is a flow diagram of an example method <NUM> for providing self-aligned vias integrated in the BEOL, in accordance with some embodiments.

Although the operations of the method <NUM> are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple self-aligned vias integrated in the BEOL as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more self-aligned vias integrated in the BEOL as described herein will be included.

In addition, the example manufacturing method <NUM> may include other operations not specifically shown in <FIG>, such as various cleaning or planarization operations as known in the art. For example, in some embodiments, the support structure <NUM>, as well as layers of various other materials subsequently deposited thereon, may be cleaned prior to, after, or during any of the processes of the method <NUM> described herein, e.g., to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g., a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the arrangements/devices described herein may be planarized prior to, after, or during any of the processes of the method <NUM> described herein, e.g., to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

Various operations of the method <NUM> may be illustrated with reference to the example embodiments shown in <FIG>, illustrating cross-sectional side and top-down views for various stages in the manufacture of an example IC structure <NUM> (e.g., the IC structure 200A shown in <FIG>, 200B shown in <FIG>, and so on until 200Y shown in <FIG>) according to the fabrication method <NUM>, in accordance with some embodiments. In particular, the top illustration of each of <FIG> shows a cross-section side view of the IC structure <NUM> (i.e., the cross-section taken along the x-z plane of the reference coordinate system x-y-z shown in <FIG>, e.g., the cross-section taken along a plane shown in <FIG> with a dashed line AA), while the bottom illustration shows a top-down view of the IC structure <NUM> (i.e., the view of the x-y plane of the reference coordinate system).

A number of elements referred to in the description of <FIG> with reference numerals are illustrated in these figures with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of each drawing page containing <FIG>. For example, the legend illustrates that <FIG> use different patterns to show a support structure <NUM>, a dielectric <NUM>, a first electrically conductive material <NUM>, etc. Furthermore, although a certain number of a given element may be illustrated in some of <FIG> (e.g., one bottom metal line, one top metal line, and one self-aligned via in between), this is simply for ease of illustration, and more, or less, than that number may be included in an IC structure according to various embodiments of the present disclosure. Still further, various IC structure views shown in <FIG> are intended to show relative arrangements of various elements therein, and that various IC structures, or portions thereof, may include other elements or components that are not illustrated (e.g., transistor portions, various components that may be in electrical contact with any of the bottom metal line, the top metal line, and the self-aligned via in between, etc.).

Turning to <FIG>, the method <NUM> may begin with a process <NUM> that includes providing, over a support structure, a stack of a bottom dielectric material, a first electrically conductive material, a top dielectric material, and a sacrificial material. An IC structure 200A, depicted in <FIG>, illustrates an example result of the process <NUM>. As shown in <FIG>, the IC structure 200A may include a support structure <NUM>, with a stack <NUM> provided thereon. The stack <NUM> may include a bottom dielectric material <NUM>, a first electrically conductive material <NUM>, a top dielectric material <NUM>, and a sacrificial material <NUM>.

In general, implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which an IC may be built falls within the scope of the present disclosure. In various embodiments, the support structure <NUM> may include any such substrate, possibly with some layers and/or devices already formed thereon, not specifically shown in the present figures, providing a suitable surface for forming the self-aligned vias integrated in the BEOL thereon.

Each of the layers of the bottom dielectric material <NUM> and the top dielectric material <NUM> may be formed in the process <NUM> using any suitable deposition technique such as, but not limited to, spin-coating, dip-coating, atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g., evaporative deposition, magnetron sputtering, or e-beam deposition), or chemical vapor deposition (CVD). In various embodiments, the bottom dielectric material <NUM> and the top dielectric material <NUM> may include one or more materials typically used as an interlayer dielectric (ILD). For example, the bottom dielectric material <NUM> and the top dielectric material <NUM> may be formed using dielectric materials known for their applicability in ICs, such as low-k dielectric materials. Examples of dielectric materials that may be used as any of the bottom dielectric material <NUM> and the top dielectric material <NUM> may include, but are not limited to, silicon dioxide (SiO<NUM>), carbon-doped oxide (CDO), silicon nitride, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. In some embodiments, any of the bottom dielectric material <NUM> and the top dielectric material <NUM> may include organic polymers such as polyimide, polynorbornenes, benzocyclobutene, perfluorocyclobutane, or polytetrafluoroethylene (PTFE). Still other examples of low-k dielectric materials that may be used as any of the bottom dielectric material <NUM> and the top dielectric material <NUM> include silicon-based polymeric dielectrics such as hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ).

A layer of the first electrically conductive material <NUM> may be formed in the process <NUM> using a deposition technique such as, but not limited to, ALD, CVD, plasma enhanced CVD (PECVD), PVD, or electroplating. In general, various electrically conductive materials described herein, e.g., the first electrically conductive material <NUM> deposited as a part of the stack <NUM> in the process <NUM>, may include one or more of any suitable electrically conductive materials (conductors). Such materials may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, various electrically conductive materials described herein may include one or more metals or metal alloys, with metals such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, various electrically conductive materials described herein may include one or more electrically conductive alloys, oxides (e.g., conductive metal oxides), carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide, tungsten, tungsten carbide), or nitrides (e.g. hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, and aluminum nitride) of one or more metals.

The sacrificial material <NUM>, deposited as a part of the stack <NUM>, may include any material that has sufficient etch selectivity with respect to the top dielectric material <NUM>. As known in the art, two materials are said to have "sufficient etch selectivity" when etchants used to etch one material do not substantially etch the other, enabling selective etching of one material but not the other. In some embodiments, the sacrificial material <NUM> may be a sacrificial dielectric material, e.g. any of the dielectric materials described above for use as the bottom dielectric material <NUM> or the top dielectric material <NUM>, as long as different dielectric materials with sufficient etch selectivity are used for the top dielectric material <NUM> and the sacrificial material <NUM>. For example, in some embodiments, the top dielectric material <NUM> may include a dielectric material including, or being, one or more of a silicon oxide (i.e. a compound comprising silicon and oxygen, e.g. SiO2) and a hafnium oxide (i.e. a compound comprising hafnium and oxygen e.g. HfO2), while the sacrificial material <NUM> may include a dielectric or conductive material having sufficient etch selectivity with respect to the material of the top dielectric material <NUM> and being selected as one or more of a titanium nitride (i.e. a compound comprising titanium and nitrogen, e.g. TiN), a silicon oxide, a hafnium oxide, a silicon nitride (i.e. a compound comprising silicon and nitrogen, e.g. SiN), a silicon oxynitride (i.e. a compound comprising silicon, oxygen, and nitrogen, e.g. SiON), an aluminum oxide (i.e. a compound comprising aluminum and oxygen, e.g. Al2O3), an aluminum hafnium oxide (i.e. a compound comprising aluminum, hafnium, and oxygen, e.g. AlHfO), a carbon-doped oxide (i.e. a compound comprising carbon and oxygen), organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. Besides appropriate etching characteristics, some other considerations in selecting a suitable material for forming the layer of the sacrificial material <NUM> may include e.g. possibilities of smooth film formation, and low shrinkage and outgassing.

The method <NUM> may then continue with a process <NUM> that includes patterning the sacrificial material provided in the process <NUM> to form an opening to define a shape and a location of the future bottom metal line. An IC structure 200B, depicted in <FIG>, illustrates an example result of the process <NUM>. As shown in <FIG>, the IC structure 200B includes an opening <NUM> in the sacrificial material <NUM>. The opening <NUM> may have any suitable dimensions for the future bottom metal line. For example, in some embodiments, the length of the opening <NUM> (e.g., a dimension measured along the x-axis of the example coordinate system shown in <FIG>) may be between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers. On the other hand, in some embodiments, the width of the opening <NUM> (e.g., a dimension measured along the y-axis of the example coordinate system shown in <FIG>) may be between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers.

In various embodiments, any suitable patterning techniques may be used in the process <NUM>, such as, but not limited to, photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a suitable etching technique, e.g., a dry etch, such as e.g., radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE. In some embodiments, the etch performed in the process <NUM> may include an anisotropic etch (i.e., etching uniformly in a vertical direction without substantially etching in other directions), using etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (CI) based chemistries. Typically, a dry etch results in anisotropic etching, whereas a wet etch results in isotropic etching (i.e., etching in substantially all directions). In some embodiments, during the etch of the process <NUM>, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and <NUM> degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface. The etch selectivity of the top dielectric material <NUM> with respect to the sacrificial material <NUM> comes into play in the process <NUM> in that etchants used to etch portions of the sacrificial material <NUM> to form the opening <NUM> do not substantially etch the top dielectric material <NUM>. As a result, the etch of the process <NUM> substantially stops once the surface <NUM> of the top dielectric material <NUM> is exposed within the opening <NUM>.

The method <NUM> may then continue with a process <NUM> that includes patterning the top dielectric material <NUM> through the opening <NUM> formed in the process <NUM> to form an opening for the future via (i.e., to form an opening that defines a shape and a location of the future via). <FIG> illustrate various intermediate results of performing the process <NUM> for the embodiment when a lithographic process is used to form the via opening.

In such an embodiment, first, a photoresist layer may be provided over the structure formed in the process <NUM>. A result of this is illustrated with an IC structure 200C, depicted in <FIG>, showing a photoresist material <NUM> provided over the IC structure 200B. The dashed contour labeled with a reference numeral <NUM>, shown in the top-down view of <FIG> and in some of the subsequent drawings, indicates the outline of the opening <NUM> under the topmost layer shown in the drawing, in this case - under the photoresist material <NUM>.

Next, a patterned mask may be provided over the photoresist layer. A result of this is illustrated with an IC structure 200D, depicted in <FIG>, showing a mask material <NUM> provided over the photoresist material <NUM>, where the mask material <NUM> is patterned to form an opening <NUM> that exposes a portion of the photoresist material <NUM> underneath. The dot-dashed lines shown in <FIG> and in some of the subsequent drawings are provided to illustrate alignment between various materials and elements. In particular, <FIG> illustrates that the opening <NUM> may not necessarily perfectly align with the bottom metal line opening <NUM>, e.g., the opening <NUM> may extend by distances <NUM> and <NUM> with respect to the width of the bottom metal line opening <NUM>. For example, in various embodiments, any one of the distances <NUM> and <NUM> may be between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers. Thus, in some embodiments, the width of the opening <NUM> (e.g., a dimension measured along the y-axis of the example coordinate system shown in <FIG>) may be between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers, and may be greater than the width of the opening <NUM>. In some embodiments, the dimension of the opening <NUM> measured along the x-axis of the example coordinate system shown in <FIG> may be substantially the same as the dimension of the opening <NUM> measured along the y-axis.

Next, the process <NUM> may proceed with exposing the photoresist material <NUM> to patterned actinic radiation through the patterned opening <NUM> in the mask <NUM>, then the exposed portion of the photoresist material <NUM> may be developed in order to form an opening in the photoresist material <NUM>, which may be referred to as a via location opening in the photoresist material <NUM>. A result of this is illustrated with an IC structure 200E, depicted in <FIG>, showing that the photoresist material <NUM> exposed by the opening <NUM> in the mask <NUM> is removed to form a via location opening <NUM> in the photoresist material <NUM>. This opening <NUM> in the top dielectric material <NUM> may be referred to as a "via location opening. " Because the patterning of the photoresist material <NUM> in the process <NUM> is defined by the opening <NUM> in the mask material <NUM>, the dimensions of the via location opening <NUM> in the photoresist material <NUM> are substantially the same as those of the opening <NUM>, described above. However, once a portion of the photoresist material <NUM> defined by the mask opening <NUM> is removed, what is exposed at the bottom of the via location opening <NUM> are the edges <NUM> and <NUM> of the sacrificial material <NUM> and the top dielectric material <NUM> in between. The edges <NUM> and <NUM> are portions of the sacrificial material <NUM> which become exposed as a result of removing the portion of the photoresist material <NUM> defined by the mask opening <NUM>, whereas the top dielectric material <NUM> in between the edges <NUM> and <NUM> is the defined by forming the opening <NUM> for the bottom metal line. Thus, in the IC structure 2E, the edges <NUM> and <NUM> extend, in the y-direction, beyond the top dielectric material <NUM> in between by distances <NUM> and <NUM>, respectively, which were described above. The edges <NUM> and <NUM> may be referred to as self-aligned edges because they will be used to align the y-axis dimension of the opening in the top dielectric material <NUM> to that of the opening <NUM> in the next step of the process <NUM>, shown in <FIG>.

Next in the process <NUM>, the via location opening <NUM> in the photoresist material <NUM> may be used as an etch mask for forming an opening in the top dielectric material <NUM>. To that end, the top dielectric material <NUM> may be etched through the via location opening <NUM> in the photoresist material <NUM>. A result of this is illustrated with an IC structure 200F, depicted in <FIG>, showing that a portion of the top dielectric material <NUM> exposed by the via location opening <NUM> is removed, forming an opening <NUM> in the layer of the top dielectric material <NUM>. This opening <NUM> in the top dielectric material <NUM> may be referred to as a via opening. The etch selectivity of the top dielectric material <NUM> and the sacrificial material <NUM> comes into play here again in that, when an etch is performed through the via location opening <NUM>, the portion of the top dielectric material <NUM> exposed by the via location opening <NUM> is removed without substantially etching the edges <NUM> and <NUM> of the sacrificial material <NUM>, which were also exposed by the via location opening <NUM>. As a result, the opening <NUM> is aligned in the y-axis direction with the opening <NUM> for the future bottom metal line (despite the fact that the mask opening <NUM> was not so aligned). Any suitable anisotropic etch process, e.g., a dry etch, may be used in the process <NUM> to etch the top dielectric material <NUM> through the via location opening <NUM>. In some embodiments, during the etch of the top dielectric material <NUM> in the process <NUM>, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and <NUM> degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface.

The process <NUM> may conclude with removing the photoresist material and the patterned mask. A result of this is illustrated with an IC structure <NUM>, depicted in <FIG>, showing that the photoresist material <NUM> and the mask material <NUM> are removed, leaving the opening <NUM> in the top dielectric material <NUM>.

It should be noted that while the descriptions of the process <NUM> refer to photolithographic patterning to form the via opening <NUM> using the self-aligned edges <NUM> and <NUM>, in other embodiments of the process <NUM> other patterning techniques may be used instead or in addition to the photolithographic patterning. Some examples of such other patterning techniques include e-beam lithography, nanoimprint, direct self-assembly (DSA) patterning, or any other technique suitable for forming the via opening <NUM> through the self-aligned edges <NUM> and <NUM>.

The method <NUM> may then continue with a process <NUM> that includes filling the opening for the bottom metal line (formed in the process <NUM>) and the via opening (formed in the process <NUM>) with an etch block material and then polishing back the excess etch block material to expose the sacrificial material. <FIG> illustrate various intermediate results of performing the process <NUM>. In particular, first, a layer of an etch block material may be deposited over the IC structure formed in the process <NUM>. A result of this is illustrated with an IC structure <NUM>, depicted in <FIG>, showing an etch block material <NUM> provided over the IC structure <NUM>. The top-down view of <FIG> also illustrates an outline of the opening <NUM> and an outline of the via opening <NUM> under the etch block material <NUM>. The etch block material <NUM> may be deposited using any suitable deposition technique such as, but not limited to, spin-coating, dip-coating, ALD, PVD, or CVD. The etch block material <NUM> may include any suitable dielectric or conductive material, e.g., any of the materials described above (e.g., silicon nitride) that are etch selective with respect to the sacrificial material <NUM>. For example, the sacrificial material <NUM> may include titanium nitride while the etch block material <NUM> may include silicon nitride. Then, the excess amount of the etch block material <NUM> may be removed (a process typically referred to as "planarization") to expose the upper surfaces of the sacrificial material <NUM> defining the opening <NUM> (which opening is now filled with the etch block material <NUM>). A result of this is illustrated with an IC structure 200I, depicted in <FIG>, showing that the etch block material <NUM> is polished back to expose the upper surfaces <NUM> of the sacrificial material <NUM> around the opening <NUM> filled with the etch block material <NUM>. The top-down view of <FIG> also illustrates an outline of the via opening <NUM> under the etch block material <NUM> within the opening <NUM>. In various embodiments, planarization of the process <NUM> may be performed using either wet or dry planarization processes. In one embodiment, planarization of the process <NUM> may be performed using CMP to remove the overburden of the etch block material <NUM> and planarize the surface of the IC structure <NUM> to expose the upper surfaces <NUM> of the sacrificial material <NUM>. In other embodiments, planarization of the process <NUM> may be performed using timed anisotropic etch.

The method <NUM> may then continue with a process <NUM> that includes performing selective etches to remove the sacrificial material around the opening filled with the etch block material (result of the process <NUM>), the top dielectric material (provided in the process <NUM>), and the first electrically conductive material <NUM> (provided in the process <NUM>), using the etch block material <NUM> as the etch block for these etches. <FIG> illustrate various intermediate results of performing the process <NUM>. In particular, first, the sacrificial material <NUM> around the opening <NUM> filled with the etch block material <NUM> is removed. A result of this is illustrated with an IC structure 200J, depicted in <FIG>, showing that now a structure <NUM>, of the etch block material <NUM> shaped to fill the opening <NUM> and the opening <NUM> is remaining in the IC structure 200J. The etch selectivity of the etch block material <NUM> with respect to the sacrificial material <NUM> comes into play during this etch of the process <NUM> in that etchants used to etch the exposed portions of the sacrificial material <NUM> do not substantially etch the etch block material <NUM>. To that end, either a wet etch or a dry etch may be performed to substantially fully remove the sacrificial material <NUM> selective to other surrounding materials. Next, portions of the top dielectric material <NUM> exposed by the structure <NUM> are etched. A result of this is illustrated with an IC structure <NUM>, depicted in <FIG>. The etch selectivity of the etch block material <NUM> with respect to the top dielectric material <NUM> comes into play during this etch of the process <NUM> in that etchants used to etch the exposed portions of the top dielectric material <NUM> do not substantially etch the etch block material <NUM>. Finally, portions of the first electrically conductive material <NUM> exposed by the structure <NUM> and the removal of the portions of the top dielectric material <NUM> are etched. A result of this is illustrated with an IC structure <NUM>, depicted in <FIG>. The etch selectivity of the etch block material <NUM> with respect to the first electrically conductive material <NUM> comes into play during this etch of the process <NUM> in that etchants used to etch the exposed portions of the first electrically conductive material <NUM> do not substantially etch the etch block material <NUM>. The remaining portion of the first electrically conductive material <NUM> forms a bottom metal line <NUM> of the BEOL metallization stack. As can be seen in <FIG>, the bottom metal line <NUM> is a portion of the first electrically conductive material <NUM> that was shaped according to the shape of the opening <NUM> that was formed in the process <NUM>, i.e., the bottom metal like <NUM> is the first electrically conductive material <NUM> under the upper portion <NUM> of the structure <NUM>. In some embodiments, etching used to remove portions of the top dielectric material <NUM> and portions of the first electrically conductive material <NUM> in the process <NUM> may be a dry etch (i.e., anisotropic) in order to avoid or at least minimize the undercutting of the upper portion <NUM> of the structure <NUM> of the etch block material <NUM>.

Next, the method <NUM> may then continue with a process <NUM> that includes removing the etch block material from the via opening <NUM> to prepare for filling the via opening with an electrically conductive material. <FIG> illustrate various intermediate results of performing the process <NUM>. In particular, first, the upper portion <NUM> of the structure <NUM> of the etch block material <NUM> is removed. A result of this is illustrated with an IC structure <NUM>, depicted in <FIG>, showing that a portion of the etch block material <NUM> is removed to expose the upper surfaces <NUM> of the top dielectric material <NUM> and to expose the etch block material <NUM> within the opening <NUM>. In some embodiments, a planarization technique such as CMP may be used for this purpose. In other embodiments, a timed anisotropic etch may be used. Next, a dielectric material <NUM> may be provided over the IC structure <NUM>. A result of this is illustrated with an IC structure 200N, depicted in <FIG>, showing a dielectric material <NUM>. The dielectric material <NUM> may be deposited using any suitable deposition technique such as, but not limited to, spin-coating, dip-coating, ALD, PVD, or CVD. The dielectric material <NUM> may include any suitable dielectric material, e.g., any of the dielectric materials described above (e.g., silicon oxide). Subsequently, excess of the dielectric material <NUM> may be removed. A result of this is illustrated with an IC structure 200O, depicted in <FIG>, showing that a portion of the dielectric material <NUM> is removed to expose the upper surfaces <NUM> of the top dielectric material <NUM> and to expose the etch block material <NUM> within the opening <NUM>. In some embodiments, a planarization technique such as CMP may be used for this purpose. Finally, the etch block material <NUM> may be removed from the opening <NUM>. A result of this is illustrated with an IC structure 200P, depicted in <FIG>. During this etch, the etch selectivity of the etch block material <NUM> with respect to the top dielectric material <NUM> comes into play again in that etchants used to etch the etch block material <NUM> do not substantially etch the top dielectric material <NUM>.

The method <NUM> may then continue with a process <NUM> that includes providing a second electrically conductive material of a target thickness. <FIG> illustrate various intermediate results of performing the process <NUM>.

In particular, first, a second electrically conductive material is deposited. A result of this is illustrated with an IC structure 200Q, depicted in <FIG>, showing that a second electrically conductive material <NUM> is deposited over the IC structure 200P. The second electrically conductive material <NUM> may include any of the electrically conductive materials described with reference to the first electrically conductive material <NUM>. In some embodiments, the first electrically conductive material <NUM> and the second electrically conductive material <NUM> may have the same material composition. In other embodiments, their material composition may be different. Irrespective of whether the material composition of the first electrically conductive material <NUM> and the second electrically conductive material <NUM> is the same or different, because they are deposited at different processes, there may be a grain boundary present at their interface, e.g., along a line <NUM>, shown in <FIG>. Such a grain boundary may be detectable using imaging by a suitable characterization equipment, such as TEM.

Next, some of the second electrically conductive material <NUM> may be removed so that a thickness of the second electrically conductive material <NUM> as measured from the bottom of the via opening <NUM> is at a target value. A result of this is illustrated with an IC structure 200R, depicted in <FIG>, showing that the second electrically conductive material <NUM> measured from the bottom of the via opening <NUM> has a thickness <NUM> (e.g., a dimension measured along the z-axis of the example coordinate system shown in <FIG>). The thickness <NUM> should be such as to be sufficient to form a via and a top metal line from the portion of the second electrically conductive material <NUM> in and above the via opening <NUM>.

The method <NUM> may then continue with a process <NUM> that includes providing a hardmask material and performing patterning to provide a patterned mask that defines the target shape and location for the top metal line. <FIG> illustrate various intermediate results of performing the process <NUM> for the embodiment when a lithographic process is used to form the patterned mask. In such an embodiment, first, a layer of a hardmask material is provided over the IC structure that was formed in the process <NUM>. A result of this is illustrated with an IC structure <NUM>, depicted in <FIG>, showing a hardmask material <NUM> provided over the second electrically conductive material <NUM> of the IC structure 200R. The hardmask material <NUM> may include any of the materials typically used for this purpose in semiconductor manufacturing, such as silicon nitride, and may be deposited using any suitable technique such as ALD, CVD, or PVD. Next, a lithographic patterning process may be performed to provide, over the hardmask material <NUM>, a patterned mask that defines the target shape and location for the top metal line. A result of this is illustrated with an IC structure 200T, depicted in <FIG>, showing an organic material <NUM> (e.g., a spin-on-glass (SOG) or amorphous carbon, or any other organic material that may be used as a part of a lithographic stack) provided over the IC structure <NUM>, then the mask material <NUM> provided over the organic material <NUM>, and then photolithographic patterning defining a patterned mask <NUM> of the mask material <NUM>. These photolithography steps may be performed similar to the patterning described with reference to the process <NUM> (illustrated in <FIG> and <FIG>), although the exact material composition of the organic material <NUM> and the mask material <NUM> used in the process <NUM> may be different. In particular, <FIG> illustrates that the patterned mask <NUM> may not necessarily perfectly align with the opening <NUM>. In particular, the patterned mask <NUM> may be narrower than the opening <NUM> by distances <NUM> and <NUM> (with respect to the width of the opening <NUM>), as shown in <FIG>. For example, in various embodiments, any one of the distances <NUM> and <NUM> may be between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers. Thus, in some embodiments, the width of the patterned mask <NUM> (e.g., a dimension measured along the x-axis of the example coordinate system shown in <FIG>) may be between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers, and may be smaller than the width of the opening <NUM>.

The method <NUM> may then continue with a process <NUM> that includes performing selective etches to remove the hardmask material not covered by the patterned mask formed in the process <NUM>, this forming a patterned hardmask, and then remove the second electrically conductive material not covered by the patterned hardmask, without etching the top dielectric material and without over-etching (i.e., without etching into the first electrically conductive material). <FIG> illustrate various intermediate results of performing the process <NUM>.

In particular, first, the hardmask material <NUM> not protected by the patterned mask <NUM> is removed, and then the patterned mask <NUM> and the organic material <NUM> is removed. A result of this is illustrated with an IC structure 200U, depicted in <FIG>, showing that now a structure <NUM>, of the hardmask material <NUM>, shaped in substantially the same shape as the patterned mask <NUM>.

Next, the etching of the second electrically conductive material <NUM> is performed, using the hardmask material <NUM> of the structure <NUM> as an etch block. A timed anisotropic etch may be used for this purpose, e.g., a dry etch using etchants suitable for gradually removing the second electrically conductive material <NUM>. At first, all of the second electrically conductive material <NUM> not protected by the structure <NUM> is removed. A result of this is illustrated with an IC structure 200V, depicted in <FIG>, showing that, at a certain point in time of the timed etch of the process <NUM>, the second electrically conductive material <NUM> under the structure <NUM> remains (a portion of the second electrically conductive material <NUM> with a thickness <NUM>, labeled in <FIG>), as well as the second electrically conductive material <NUM> that is at and below the upper surface of the top dielectric material <NUM> (a portion of the second electrically conductive material <NUM> with a thickness <NUM>, labeled in <FIG>). The portion of the second electrically conductive material <NUM> with the thickness <NUM> is removed because it's not protected by the structure <NUM>, and none of the portion of the second electrically conductive material <NUM> with the thickness <NUM> is removed because the etch has not proceeded that far yet. As the etch continues, some of the second electrically conductive material <NUM> of the portion <NUM> will be removed, namely, the portions not protected by the structure <NUM>. A result of this is illustrated with an IC structure 200W, depicted in <FIG>, showing that, at the end of the timed etch of the process <NUM>, a portion of the second electrically conductive material <NUM> in the via opening <NUM>, that is not protected by the structure <NUM> is also etched. The top dielectric material <NUM> is not substantially etched at that point because the top dielectric material <NUM> is etch-selective with respect to the second electrically conductive material <NUM>. After the timed etch of the process <NUM>, the portion <NUM> of the second electrically conductive material <NUM> forms a top metal line <NUM>, shaped in the x-y plane according to the structure <NUM>. The remaining portion of the second electrically conductive material <NUM> forms a via <NUM> that has a bottom end interfacing the bottom metal line <NUM> of the BEOL metallization stack and has a top end being continuous with the top metal line <NUM>.

The method <NUM> may end with a process <NUM> that includes removing the patterned hardmask structure, and then providing a cover dielectric, while exposing the upper surface of the top metal line. <FIG> illustrate various intermediate results of performing the process <NUM>. First, the structure <NUM> of the hardmask material <NUM> is removed. A result of this is illustrated with an IC structure 200X, depicted in <FIG>. Next, a dielectric material, referred to herein as a "cover dielectric" <NUM> is deposited over the IC structure 200X. A result of this is illustrated with an IC structure 200Y, depicted in <FIG>. Then, excess of the cover dielectric <NUM> may be removed so that a surface of the top metal line <NUM> is exposed. A result of this is illustrated with an IC structure 200Z, depicted in <FIG>.

The fabrication method <NUM> leaves several characteristic features in the IC structure 200Z that are indicative of the method <NUM> being used. One such feature is that the material composition of the top metal line <NUM> and the via <NUM> is substantially the same, which is a result of both of the top metal line <NUM> and the via <NUM> being formed from the second electrically conductive material <NUM> deposited in the process <NUM>. A sum of the thickness of the top metal line <NUM> and the thickness of the via <NUM> is equal to the thickness <NUM> of the second electrically conductive material <NUM> (<FIG>). Another characteristic feature indicative of the use of the method <NUM> is that while there is likely to be a detectable metal grain boundary at the interface between the via <NUM> and the bottom metal line <NUM> (as illustrated in <FIG>), there will not be a metal grain boundary at the interface between the via <NUM> and the top metal line <NUM> because those are formed of the same material, deposited in a single process. Yet another characteristic feature is that the via <NUM> will have two portions with different widths (shown as portions <NUM>-<NUM> and <NUM>-<NUM> in <FIG>, where portion <NUM>-<NUM> is shown with a brick pattern): namely, the first portion <NUM>-<NUM> of the via <NUM> may be the portion that is between the bottom metal line <NUM> and the second portion <NUM>-<NUM>, and the second portion <NUM>-<NUM> may be a portion of the via <NUM> that is between the first portion <NUM>-<NUM> and the top metal line <NUM>. In some embodiments, the width of the second portion <NUM>-<NUM> (i.e., the dimension measured along the x-axis) may be smaller than the width of the first portion <NUM>-<NUM> by between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers. In some embodiments, a height of the first portion <NUM>-<NUM> (e.g., a dimension measured along the z-axis of the example coordinate system shown in <FIG>) may be between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers. In some embodiments, a height of the via <NUM> (e.g., a dimension measured along the z-axis of the example coordinate system shown in <FIG>, in particular - the dimension <NUM>) may be between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers.

Yet another feature indicative of the use of the method <NUM> is that a width of the top metal line <NUM> (e.g., a dimension measured along the x-axis of the example coordinate system shown in <FIG>) is substantially equal to the width of the second portion <NUM>-<NUM> of the via <NUM>. Furthermore, the first portion <NUM>-<NUM> of the via <NUM> is substantially aligned with the bottom metal line <NUM> (i.e., in a cross-sectional side view, a line perpendicular to the support structure <NUM> and going through the center of the first portion <NUM>-<NUM> of the via <NUM> may substantially coincide with a line perpendicular to the support structure <NUM> and going through the center of the bottom metal line <NUM>). On the other hand, the second portion <NUM>-<NUM> of the via <NUM> may be substantially aligned with the top metal line <NUM> (i.e., in a cross-sectional side view, a line perpendicular to the support structure <NUM> and going through the center of the second portion <NUM>-<NUM> of the via <NUM> may substantially coincide with a line perpendicular to the support structure <NUM> and going through the center of the top metal line <NUM>).

The method <NUM> allows forming the via <NUM> as a self-aligned via, integrated in the BEOL of a metallization stack. The via <NUM> provides electrical connectivity between the bottom metal line <NUM> and the top metal line <NUM> and, advantageously, is self-aligned to both of these metal lines.

It should be noted that the descriptions of the method <NUM>, provided above, are also applicable to embodiments where the bottom metal line <NUM> is formed as a top metal line for another set of a self-aligned via and bottom and top metal lines. In such embodiments, the processes <NUM>-<NUM>, described above, would not be included in the method <NUM>, or, rather, the processes <NUM>-<NUM> would be replaced with the processes <NUM>-<NUM>, described above except that the "top metal line" of those processes would now become the bottom metal line <NUM>. The method would then proceed with another iteration of the processes <NUM>-<NUM> to implement the self-aligned via <NUM> and the top metal line <NUM>, as described herein.

Furthermore, in still further embodiments, the bottom metal line <NUM> may be formed using processes other than the processes <NUM>-<NUM>, described above, all of which embodiments also being within the scope of the present disclosure. In such embodiments, the processes <NUM>-<NUM>, described above, would not be included in the method <NUM>, or, rather, the processes <NUM>-<NUM> would be replaced with other processes for providing a metal line as the bottom metal line <NUM>. The method would then proceed with the processes <NUM>-<NUM> to implement the self-aligned via <NUM> and the top metal line <NUM>, as described herein.

The IC structures with self-aligned vias integrated in the BEOL, disclosed herein, may be included in any suitable electronic device. <FIG> illustrate various examples of apparatuses that may include one or more of the IC structures disclosed herein.

<FIG> are top views of a wafer and dies that include one or more IC structures with self-aligned vias integrated in the BEOL in accordance with any of the embodiments disclosed herein. The wafer <NUM> may be composed of semiconductor material and may include one or more dies <NUM> having IC structures formed on a surface of the wafer <NUM>. Each of the dies <NUM> may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., the IC 200J as shown in <FIG>, or any further embodiments of such an IC). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more IC structures with self-aligned vias integrated in the BEOL as described herein, included in a particular electronic component, e.g. in a transistor or in a memory device), the wafer <NUM> may undergo a singulation process in which each of the dies <NUM> is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include a metallization stack as disclosed herein may take the form of the wafer <NUM> (e.g., not singulated) or the form of the die <NUM> (e.g., singulated). The die <NUM> may include one or more transistors (e.g., one or more of the transistors <NUM> of <FIG>, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components (e.g., one or more of the via contacts formed by the via contact patterning method as discussed herein, which may take the form of any of the metallization stacks described herein). In some embodiments, the wafer <NUM> or the die <NUM> may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die <NUM>. For example, a memory array formed by multiple memory devices may be formed on a same die <NUM> as a processing device (e.g., the processing device <NUM> of <FIG>) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

<FIG> is a cross-sectional side view of an IC device <NUM> that may include one or more IC structures with self-aligned vias integrated in the BEOL in accordance with any of the embodiments disclosed herein. The IC device <NUM> may be formed on a substrate <NUM> (e.g., the wafer <NUM> of <FIG>) and may be included in a die (e.g., the die <NUM> of <FIG>). The substrate <NUM> may be any substrate as described herein. The substrate <NUM> may be part of a singulated die (e.g., the dies <NUM> of <FIG>) or a wafer (e.g., the wafer <NUM> of <FIG>).

The IC device <NUM> may include one or more device layers <NUM> disposed on the substrate <NUM>. The device layer <NUM> may include features of one or more transistors <NUM> (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate <NUM>. The device layer <NUM> may include, for example, one or more source and/or drain (S/D) regions <NUM>, a gate <NUM> to control current flow in the transistors <NUM> between the S/D regions <NUM>, and one or more S/D contacts <NUM> to route electrical signals to/from the S/D regions <NUM>. The transistors <NUM> may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors <NUM> are not limited to the type and configuration depicted in <FIG> and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

Each transistor <NUM> may include a gate <NUM> formed of at least two layers, a gate electrode layer and a gate dielectric layer.

The gate electrode layer may be formed on the gate interconnect support layer and may include at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor, respectively. In some implementations, the gate electrode layer may include a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer or/and an adhesion layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about <NUM> electron Volts (eV) and about <NUM> eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, tungsten, tungsten carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV.

In some embodiments, when viewed as a cross-section of the transistor <NUM> along the source-channel-drain direction, the gate electrode may be formed as a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be implemented as a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may be implemented as one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may consist of a V-shaped structure (e.g., when a fin of a FinFET transistor does not have a "flat" upper surface, but instead has a rounded peak).

Generally, the gate dielectric layer of a transistor <NUM> may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of the transistor <NUM> may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

Although not specifically shown in <FIG>, gate contacts to the gate <NUM> may be made as described above with reference to the gate <NUM> and gate via contacts formed by the via contact patterning method described herein.

The S/D regions <NUM> may be formed within the substrate <NUM> adjacent to the gate <NUM> of each transistor <NUM>, using any suitable processes known in the art. For example, the S/D regions <NUM> may be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate <NUM> to form the S/D regions <NUM>. An annealing process that activates the dopants and causes them to diffuse farther into the substrate <NUM> may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the S/D regions <NUM>. In some implementations, the S/D regions <NUM> may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions <NUM> may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions <NUM>. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the substrate <NUM> in which the material for the S/D regions <NUM> is deposited.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors <NUM> of the device layer <NUM> through one or more interconnect layers disposed on the device layer <NUM> (illustrated in <FIG> as interconnect layers <NUM>-<NUM>). For example, electrically conductive features of the device layer <NUM> (e.g., the gate <NUM> and the S/D contacts <NUM>) may be electrically coupled with the interconnect structures <NUM> of the interconnect layers <NUM>-<NUM>. The one or more interconnect layers <NUM>-<NUM> may form an ILD stack <NUM> of the IC device <NUM>. In general, embodiments of the present disclosure may be used for any interconnect layer.

The interconnect structures <NUM> may be arranged within the interconnect layers <NUM>-<NUM> to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures <NUM> depicted in <FIG>). Although a particular number of interconnect layers <NUM>-<NUM> is depicted in <FIG>, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures <NUM> may include trench contact structures 1228a (sometimes referred to as "lines") and/or via structures 1228b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal. The trench contact structures 1228a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate <NUM> upon which the device layer <NUM> is formed. For example, the trench contact structures 1228a may route electrical signals in a direction in and out of the page from the perspective of <FIG>. The via structures 1228b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate <NUM> upon which the device layer <NUM> is formed. In some embodiments, the via structures 1228b may electrically couple trench contact structures 1228a of different interconnect layers <NUM>-<NUM> together.

The interconnect layers <NUM>-<NUM> may include a dielectric material <NUM> disposed between the interconnect structures <NUM>, as shown in <FIG>. The dielectric material <NUM> may take the form of any of the embodiments of the dielectric material provided between the interconnects of the IC structures disclosed herein, for example any of the embodiments discussed herein with reference to the dielectric materials <NUM> or <NUM>, described herein.

In some embodiments, the dielectric material <NUM> disposed between the interconnect structures <NUM> in different ones of the interconnect layers <NUM>-<NUM> may have different compositions. In other embodiments, the composition of the dielectric material <NUM> between different interconnect layers <NUM>-<NUM> may be the same.

A first interconnect layer <NUM> (referred to as Metal <NUM> or "M1") may be formed directly on the device layer <NUM>. In some embodiments, the first interconnect layer <NUM> may include trench contact structures 1228a and/or via structures 1228b, as shown. The trench contact structures 1228a of the first interconnect layer <NUM> may be coupled with contacts (e.g., the S/D contacts <NUM>) of the device layer <NUM>. In some embodiments, the via structures 1228b may be implemented as the self-aligned via integrated in the BEOL, e.g., as the via <NUM> formed using the method <NUM>, described above. In such embodiments, the trench contact structures 1228a may be implemented as the top metal line described herein, e.g., as the top metal line <NUM> formed using the method <NUM>, described above.

A second interconnect layer <NUM> (referred to as Metal <NUM> or "M2") may be formed directly on the first interconnect layer <NUM>. In some embodiments, the second interconnect layer <NUM> may include via structures 1228b to couple the trench contact structures 1228a of the second interconnect layer <NUM> with the trench contact structures 1228a of the first interconnect layer <NUM>. Although the trench contact structures 1228a and the via structures 1228b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer <NUM>) for the sake of clarity, the trench contact structures 1228a and the via structures 1228b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

A third interconnect layer <NUM> (referred to as Metal <NUM> or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer <NUM> according to similar techniques and configurations described in connection with the second interconnect layer <NUM> or the first interconnect layer <NUM>. As shown in <FIG>, the third interconnect layer <NUM> may include one or more trench structures 1226a and one or more via structures 1226b. In some embodiments, the via structures 1226b may be implemented as the self-aligned via integrated in the BEOL, e.g., as the via <NUM> formed using the method <NUM>, described above. In such embodiments, the trench contact structures 1226a may be implemented as the top metal line described herein, e.g., as the top metal line <NUM> formed using the method <NUM>, described above. Furthermore, in such embodiments, the trench contact structures 1228a may be implemented as the bottom metal line described herein, e.g., as the bottom metal line <NUM> formed using the method <NUM>, described above.

The IC device <NUM> may include a solder resist material <NUM> (e.g., polyimide or similar material) and one or more bond pads <NUM> formed on the interconnect layers <NUM>-<NUM>. The bond pads <NUM> may be electrically coupled with the interconnect structures <NUM> and configured to route the electrical signals of the transistor(s) <NUM> to other external devices. For example, solder bonds may be formed on the one or more bond pads <NUM> to mechanically and/or electrically couple a chip including the IC device <NUM> with another component (e.g., a circuit board). The IC device <NUM> may have other alternative configurations to route the electrical signals from the interconnect layers <NUM>-<NUM> than depicted in other embodiments. For example, the bond pads <NUM> may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

<FIG> is a cross-sectional side view of an IC device assembly <NUM> that may include components having or being associated with (e.g. being electrically connected by means of) one or more IC structures with self-aligned vias integrated in the BEOL in accordance with any of the embodiments disclosed herein. The IC device assembly <NUM> includes a number of components disposed on a circuit board <NUM> (which may be, e.g., a motherboard). The IC device assembly <NUM> includes components disposed on a first face <NUM> of the circuit board <NUM> and an opposing second face <NUM> of the circuit board <NUM>; generally, components may be disposed on one or both faces <NUM> and <NUM>. In particular, any suitable ones of the components of the IC device assembly <NUM> may include any of the metallization stacks <NUM> disclosed herein.

In some embodiments, the circuit board <NUM> may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board <NUM>. In other embodiments, the circuit board <NUM> may be a non-PCB substrate.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-interposer structure <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may electrically and mechanically couple the package-on-interposer structure <NUM> to the circuit board <NUM>, and may include solder balls (as shown in <FIG>), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure <NUM> may include an IC package <NUM> coupled to an interposer <NUM> by coupling components <NUM>. The coupling components <NUM> may take any suitable form for the application, such as the forms discussed above with reference to the coupling components <NUM>. Although a single IC package <NUM> is shown in <FIG>, multiple IC packages may be coupled to the interposer <NUM>; indeed, additional interposers may be coupled to the interposer <NUM>. The interposer <NUM> may provide an intervening substrate used to bridge the circuit board <NUM> and the IC package <NUM>. The IC package <NUM> may be or include, for example, a die (the die <NUM> of <FIG>), an IC device (e.g., the IC device <NUM> of <FIG>), or any other suitable component. Generally, the interposer <NUM> may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer <NUM> may couple the IC package <NUM> (e.g., a die) to a ball grid array (BGA) of the coupling components <NUM> for coupling to the circuit board <NUM>. In the embodiment illustrated in <FIG>, the IC package <NUM> and the circuit board <NUM> are attached to opposing sides of the interposer <NUM>; in other embodiments, the IC package <NUM> and the circuit board <NUM> may be attached to a same side of the interposer <NUM>. In some embodiments, three or more components may be interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer <NUM>. The package-on-interposer structure <NUM> may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly <NUM> may include an IC package <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may take the form of any of the embodiments discussed above with reference to the coupling components <NUM>, and the IC package <NUM> may take the form of any of the embodiments discussed above with reference to the IC package <NUM>.

The IC device assembly <NUM> illustrated in <FIG> includes a package-on-package structure <NUM> coupled to the second face <NUM> of the circuit board <NUM> by coupling components <NUM>. The package-on-package structure <NUM> may include an IC package <NUM> and an IC package <NUM> coupled together by coupling components <NUM> such that the IC package <NUM> is disposed between the circuit board <NUM> and the IC package <NUM>. The coupling components <NUM> and <NUM> may take the form of any of the embodiments of the coupling components <NUM> discussed above, and the IC packages <NUM> and <NUM> may take the form of any of the embodiments of the IC package <NUM> discussed above. The package-on-package structure <NUM> may be configured in accordance with any of the package-on-package structures known in the art.

<FIG> is a block diagram of an example computing device <NUM> that may include one or more components including one or more IC structures with self-aligned vias integrated in the BEOL in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device <NUM> may include a die (e.g., the die <NUM> of <FIG>) having one or more IC structures with self-aligned vias integrated in the BEOL as described herein. Any one or more of the components of the computing device <NUM> may include, or be included in, an IC device <NUM> (<FIG>). Any one or more of the components of the computing device <NUM> may include, or be included in, an IC device assembly <NUM> (<FIG>).

A number of components are illustrated in <FIG> as included in the computing device <NUM>, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device <NUM> may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the computing device <NUM> may not include one or more of the components illustrated in <FIG>, but the computing device <NUM> may include interface circuitry for coupling to the one or more components. For example, the computing device <NUM> may not include a display device <NUM>, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device <NUM> may be coupled. In another set of examples, the computing device <NUM> may not include an audio input device <NUM> or an audio output device <NUM>, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device <NUM> or audio output device <NUM> may be coupled.

The computing device <NUM> may include a processing device <NUM> (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device <NUM> may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device <NUM> may include a memory <NUM>, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory <NUM> may include memory that shares a die with the processing device <NUM>. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the computing device <NUM> may include a communication chip <NUM> (e.g., one or more communication chips). For example, the communication chip <NUM> may be configured for managing wireless communications for the transfer of data to and from the computing device <NUM>. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium.

The communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication chip <NUM> may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip <NUM> may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication chip <NUM> may operate in accordance with other wireless protocols in other embodiments. The computing device <NUM> may include an antenna <NUM> to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip <NUM> may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip <NUM> may include multiple communication chips. For instance, a first communication chip <NUM> may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip <NUM> may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip <NUM> may be dedicated to wireless communications, and a second communication chip <NUM> may be dedicated to wired communications.

The computing device <NUM> may include battery/power circuitry <NUM>. The battery/power circuitry <NUM> may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device <NUM> to an energy source separate from the computing device <NUM> (e.g., AC line power).

The computing device <NUM> may include a display device <NUM> (or corresponding interface circuitry, as discussed above). The display device <NUM> may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device <NUM> may include an audio output device <NUM> (or corresponding interface circuitry, as discussed above). The audio output device <NUM> may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device <NUM> may include an audio input device <NUM> (or corresponding interface circuitry, as discussed above). The audio input device <NUM> may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device <NUM> may include a global positioning system (GPS) device <NUM> (or corresponding interface circuitry, as discussed above). The GPS device <NUM> may be in communication with a satellite-based system and may receive a location of the computing device <NUM>, as known in the art.

The computing device <NUM> may include an other output device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other output device <NUM> may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device <NUM> may include an other input device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other input device <NUM> may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The computing device <NUM> may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device <NUM> may be any other electronic device that processes data.

The following examples are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

Example <NUM> provides am IC structure that includes a support structure (e.g., a substrate); a first electrically conductive structure (e.g., a bottom metal line), provided over the support structure; a via, provided over the first electrically conductive structure; and a second electrically conductive structure (e.g., a top metal line), provided over the via, where the via is configured to provide electrical connectivity between the first electrically conductive structure and the second electrically conductive structure, the via has a first portion and a second portion, the first portion is a portion of the via that is between the first electrically conductive structure and the second portion, the second portion is a portion of the via that is between the first portion and the second electrically conductive structure, and, in a cross-sectional side view, a width of the second portion (e.g., a dimension measured along the x-axis of the example coordinate system shown in <FIG>) is smaller than a width of the first portion.

Example <NUM> provides the IC structure according to example <NUM>, where the width of the second portion is smaller than the width of the first portion by between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers.

Example <NUM> provides the IC structure according to examples <NUM> or <NUM>, where a height of the first portion (e.g., a dimension measured along the z-axis of the example coordinate system shown in <FIG>) is between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers.

Example <NUM> provides the IC structure according to any one of the preceding examples, where a height of the via (e.g., a dimension measured along the z-axis of the example coordinate system shown in <FIG>) is between about <NUM> and <NUM> nanometers, including all values and ranges therein, e.g., between about <NUM> and <NUM> nanometers, or between about <NUM> and <NUM> nanometers.

Example <NUM> provides the IC structure according to any one of the preceding examples, where a width of the first electrically conductive structure (e.g., a dimension measured along the y-axis of the example coordinate system shown in <FIG>) is substantially equal to the width of the first portion of the via.

Example <NUM> provides the IC structure according to any one of the preceding examples, where a width of the second electrically conductive structure (e.g., a dimension measured along the x-axis of the example coordinate system shown in <FIG>) is substantially equal to the width of the second portion of the via.

Example <NUM> provides the IC structure according to any one of the preceding examples, where the first portion of the via is substantially aligned with the first electrically conductive structure (i.e., in a cross-sectional side view, a line perpendicular to the support structure and going through the center of the first portion of the via substantially coincides with a line perpendicular to the support structure and going through the center of the first electrically conductive structure).

Example <NUM> provides the IC structure according to any one of the preceding examples, where the second portion of the via is substantially aligned with the second electrically conductive structure (i.e., in a cross-sectional side view, a line perpendicular to the support structure and going through the center of the second portion of the via substantially coincides with a line perpendicular to the support structure and going through the center of the second electrically conductive structure).

Example <NUM> provides the IC structure according to any one of the preceding examples, where the first portion of the via is in contact with the first electrically conductive structure.

Example <NUM> provides the IC structure according to any one of the preceding examples, where the second portion of the via is in contact with the second electrically conductive structure.

Example <NUM> provides the IC structure according to any one of the preceding examples, where a material composition of the via is substantially the same as a material composition of the second electrically conductive structure.

Example <NUM> provides the IC structure according to any one of the preceding examples, where a material composition of the via is different from a material composition of the first electrically conductive structure.

Example <NUM> provides the IC structure according to any one of the preceding examples, where at least the via and the second electrically conductive structure are in a back end of line (BEOL) portion of the IC structure, and the IC structure further includes a plurality of semiconductor devices in a front end of line (FEOL) portion of the IC structure, where the FEOL portion is between the support structure and the BEOL.

Example <NUM> provides an IC package that includes an IC die having a first metal line, a via, and a second metal line stacked over one another over the IC die, where each of the first metal line and the second metal line extend in a direction parallel to the IC die, the via extends in a direction perpendicular to the IC die and has a first portion electrically connected to the first metal line and a second portion electrically connected to the first metal line, and a width of the second portion is smaller than a width of the first portion. The IC package also includes a further IC component, coupled to the IC die.

Example <NUM> provides the IC package according to example <NUM>, where the further component is one of a package substrate, a flexible substrate, or an interposer.

Example <NUM> provides the IC package according to examples <NUM> or <NUM>, where the further component is coupled to the IC die via one or more first level interconnects.

Example <NUM> provides the IC package according to example <NUM>, where the one or more first level interconnects include one or more solder bumps, solder posts, or bond wires.

Example <NUM> provides a method of forming an IC structure. The method includes providing a first electrically conductive structure (e.g., a bottom metal line) over a support structure (e.g., a substrate); providing a via over the first electrically conductive structure; and providing a second electrically conductive structure (e.g., a top metal line) over the via, where the via has a first portion and a second portion, the first portion is a portion of the via that is between the first electrically conductive structure and the second portion, the second portion is a portion of the via that is between the first portion and the second electrically conductive structure, and, in a cross-sectional side view, a width of the second portion (e.g., a dimension measured along the x-axis of the example coordinate system shown in <FIG>) is smaller than a width of the first portion.

Example <NUM> provides the method according to example <NUM>, where providing the first electrically conductive structure includes: providing a stack of a bottom dielectric material, a first electrically conductive material, a top dielectric material and a sacrificial material; patterning the sacrificial material to form an opening that defines a shape and a location of the first electrically conductive structure; patterning the top dielectric material through the opening that defines the shape and the location of the first electrically conductive structure to form an opening that defines a shape and a location of the via; filling the opening that defines the shape and the location of the first electrically conductive structure and the opening that defines the shape and the location of the via with an etch block material; and sequentially performing selective etches to remove portions of each of the sacrificial material, the top dielectric material, and the first electrically conductive material using the etch block material as an etch block.

Example <NUM> provides the method according to example <NUM>, where patterning the top dielectric material through the opening that defines the shape and the location of the first electrically conductive structure to form the opening that defines the shape and the location of the via includes: performing lithographic patterning to define an opening in a mask material that is provided over the opening that defines the shape and the location of the first electrically conductive structure, where the opening in the mask material overlaps with the opening that defines the shape and the location of the first electrically conductive structure, and performing selective etch through the opening in the mask material to remove a portion of the top dielectric material exposed by the opening in the mask material without substantially removing a portion of the sacrificial material exposed by the opening in the mask material.

Example <NUM> provides a computing device that includes a circuit board; and an IC die coupled to the circuit board, where the IC die includes one or more of: one or more IC structures according to any one of the preceding examples (e.g., each IC structure may be an IC structure according to any one of examples <NUM>-<NUM> and/or may be formed according to a method of any one of examples <NUM>-<NUM>), one or more of IC packages according to any one of the preceding examples (e.g., each IC package may be an IC package according to any one of examples <NUM>-<NUM>).

Example <NUM> provides the computing device according to example <NUM>, where the computing device is a wearable computing device (e.g., a smart watch) or handheld computing device (e.g., a mobile phone).

Example <NUM> provides the computing device according to examples <NUM> or <NUM>, where the computing device is a server processor.

Example <NUM> provides the computing device according to examples <NUM> or <NUM>, where the computing device is a motherboard.

Claim 1:
An integrated circuit, IC, structure, comprising:
a support structure (<NUM>);
a first electrically conductive structure (<NUM>) over the support structure (<NUM>);
a via (<NUM>) over the first electrically conductive structure (<NUM>), the via formed of an electrically conductive material;
a second electrically conductive structure (<NUM>) over the via (<NUM>), and
a cover dielectric over the IC structure, a height (<NUM>) of the cover dielectric over the first electrically conductive structure (<NUM>) being equal to a sum of the heights of the second electrically conductive structure (<NUM>) and the via (<NUM>), where:
the via (<NUM>) has a first portion (<NUM>-<NUM>) and a second portion (<NUM>-<NUM>), the first portion (<NUM>-<NUM>) is between the first electrically conductive structure (<NUM>) and the second portion (<NUM>-<NUM>), the second portion (<NUM>-<NUM>) is between the first portion (<NUM>-<NUM>) and the second electrically conductive structure (<NUM>), and a width of the second portion (<NUM>-<NUM>) is smaller than a width of the first portion (<NUM>-<NUM>),
the via (<NUM>) to provide electrical connectivity between the first electrically conductive structure (<NUM>) and the second electrically conductive structure (<NUM>).