Patent Description:
Microelectronic elements often comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a semiconductor wafer. A wafer can be formed to include multiple integrated chips or dies on a surface of the wafer and/or partly embedded within the wafer. Dies that are separated from a wafer are commonly provided as individual, prepackaged units. In some package designs, the die is mounted to a substrate or a chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board (PCB). For example, many dies are provided in packages suitable for surface mounting.

Packaged semiconductor dies can also be provided in "stacked" arrangements, wherein one package is provided, for example, on a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements can allow a number of different dies or devices to be mounted within a single footprint on a circuit board and can further facilitate high-speed operation by providing a short interconnection between the packages. Often, this interconnect distance can be only slightly larger than the thickness of the die itself. For interconnection to be achieved within a stack of die packages, interconnection structures for mechanical and electrical connection may be provided on both sides (e.g., faces) of each die package (except for the topmost package).

Additionally, dies or wafers may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This can include stacking a layer of one or more dies, devices, and/or wafers on a larger base die, device, wafer, substrate, or the like, stacking multiple dies or wafers in a vertical or horizontal arrangement, and various combinations of both.

Dies or wafers may be bonded in a stacked arrangement using various bonding techniques, including direct dielectric bonding, non-adhesive techniques, such as ZiBond® or a hybrid bonding technique, such as DBI®, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc. ), an Xperi company. The bonding includes a spontaneous process that takes place at ambient conditions when two prepared surfaces are brought together (see for example, <CIT> and <CIT>, which are incorporated herein in their entirety).

Respective mating surfaces of the bonded dies or wafers often include embedded conductive interconnect structures (which may be metal), or the like. In some examples, the bonding surfaces are arranged and aligned so that the conductive interconnect structures from the respective surfaces are joined during the bonding. The joined interconnect structures form continuous conductive interconnects (for signals, power, etc.) between the stacked dies or wafers.

There can be a variety of challenges to implementing stacked die and wafer arrangements. When bonding stacked dies using a direct bonding or hybrid bonding technique, it is usually desirable that the surfaces of the dies to be bonded be extremely flat, smooth, and clean. For instance, in general, the surfaces should have a very low variance in surface topology (i.e., nanometer scale variance), so that the surfaces can be closely mated to form a lasting bond.

Double-sided dies can be formed and prepared for stacking and bonding, where both sides of the dies will be bonded to other substrates or dies, such as with multiple die-to-die or die-to-wafer applications. Preparing both sides of the die includes finishing both surfaces to meet dielectric roughness specifications and metallic layer (e.g., copper, etc.) recess specifications. For instance, conductive interconnect structures at the bonding surfaces may be slightly recessed, just below the insulating material of the bonding surface. The amount of recess below the bonding surface may be determined by a dimensional tolerance, specification, or physical limitation of the device or application. The hybrid surface may be prepared for bonding with another die, wafer, or other substrate using a chemical mechanical polishing (CMP) process, or the like.

In general, when direct bonding surfaces containing a combination of a dielectric layer and one or more metal features (e.g., embedded conductive interconnect structures) are bonded together, the dielectric surfaces bond first at lower temperatures and the metal of the features expands afterwards, as the metal is heated during annealing. The expansion of the metal can cause the metal from both bonding surfaces to join into a unified conductive structure (metal-to-metal bond). While both the substrate and the metal are heated during annealing, the coefficient of thermal expansion (CTE) of the metal relative to the CTE of the substrate generally dictates that the metal expands much more than the substrate at a particular temperature (e.g., ~300C). For instance, the CTE of copper is <NUM>, while the CTE of fused silica is <NUM>, and the CTE of silicon is <NUM>.

In some cases, the greater expansion of the metal relative to the substrate can be problematic for direct bonding stacked dies or wafers. If a metal pad is positioned over a through-silicon via (TSV), the expansion of the TSV metal can contribute to the expansion of the pad metal. In some cases, the combined metal expansion can cause localized delamination of the bonding surfaces, as the expanding metal rises above the bonding surface. For instance, the expanded metal can separate the bonded dielectric surfaces of the stacked dies. <CIT> discloses a semiconductor device including: a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad. <CIT> discloses a semiconductor device including: a first laminated body and a second laminated body, wherein the first laminated body includes sequentially a first element, a first wiring layer, and a first connection layer that includes a first junction electrode, on a main surface of a first substrate, wherein the second laminated body includes sequentially a second element, a second wiring layer, and a second connection layer that includes a second junction electrode, on a main surface of a semiconductor substrate, and wherein the first laminated body and the second laminated body are bonded by directly bonding the first junction electrode and the second junction electrode with the two junction electrodes facing each other. In particular <CIT> discloses a microelectronic assembly having a plurality of metal contact pads and at least one through substrate via, TSV, the microelectronic assembly comprising: a first TSV provided within a first substrate having a first bonding surface, the first TSV extending into the first substrate in a direction normal to the first bonding surface, wherein the first bonding surface has a surface variance less than or equal to a maximum surface variance for direct bonding; and a first metal contact pad and a second metal contact pad in the first bonding surface, the first metal contact pad extending partially into the first substrate below the first bonding surface, the first metal contact pad electrically coupled and aligned with the first TSV in the direction from the first bonding surface through the first substrate, the second metal contact pad extending partially into the first substrate below the first bonding surface, the first metal contact pad having a larger surface area than a surface area of the second metal contact pad, wherein no TSV is disposed under the second metal contact pad in the direction normal to the first bonding surface. <CIT> discloses methods for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC), wherein a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion, wherein a column of pixels of the sensor may share a bond bad connected by a shared inter-metal line, the bond pads may be of different sizes and configured in different rows to be disjoint from each other and additional dummy pads may be added to increase the bonding between the sensor and the ASIC.

In particular <CIT> discloses a microelectronic assembly having a plurality of metal contact pads and at least one through substrate via, TSV, the microelectronic assembly comprising: a first TSV provided within a first substrate having a first bonding surface, the first TSV extending into the first substrate in a direction normal to the first bonding surface, wherein the first bonding surface has a surface variance less than or equal to a maximum surface variance for direct bonding; and a first metal contact pad and a second metal contact pad in the first bonding surface, the first metal contact pad extending partially into the first substrate below the first bonding surface, the first metal contact pad electrically coupled and aligned with the first TSV in the direction from the first bonding surface through the first substrate, the second metal contact pad extending partially into the first substrate below the first bonding surface, the first metal contact pad having a larger surface area than a surface area of the second metal contact pad, wherein no TSV is disposed under the second metal contact pad in the direction normal to the first bonding surface.

According to aspects of the present disclosure, there are provided a method and a microelectronic assembly according to the appended claims.

For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components. Various implementations of devices and/or systems, as described herein, may include fewer components and remain within the scope of the disclosure. Alternatively, other implementations of devices and/or systems may include additional components, or various combinations of the described components, and remain within the scope of the disclosure.

The examples and embodiments of <FIG> and <FIG> are in accordance with the claimed invention.

The examples and embodiments of <FIG>, <FIG>, <FIG> and <FIG> by themselves are not encompassed by the claimed invention but useful for the understanding thereof.

Representative techniques and devices are disclosed, including process steps for preparing various microelectronic devices for bonding, such as for direct bonding without adhesive. In various embodiments, techniques may be employed to mitigate the potential for delamination due to metal expansion, particularly when a TSV or a bond pad over a TSV is presented at the bonding surface of one or both devices to be bonded. According to the claimed invention, a metal pad having a larger diameter or surface area (e.g., oversized for the application) is used when a contact pad is positioned over a TSV. The contact pad, including the size (e.g., surface area, diameter, etc.) of the contact pad, or the amount of oversize of the contact pad is selected based on the material of the pad, its thickness, and anticipated recess during processing.

When using surface preparation processes such as CMP to prepare the bonding surface of the substrate, the metal pads on the bonding surface can become recessed relative to the dielectric, due to the softer material of the pads relative to the material of the dielectric. A larger diameter metal pad becomes recessed to a greater degree (i.e. a deeper recess) than a smaller diameter pad. In places where a contact pad is positioned over a TSV, the deeper recess can compensate for a combined metal expansion of the pad and the TSV, allowing more room for expansion of the metal, which can reduce or eliminate delamination that could occur otherwise when the metal expands.

According to the claimed invention the process includes embedding a first through silicon via (TSV) into a first substrate having a first bonding surface, where the first TSV is normal to the first bonding surface (i.e., vertical within a horizontally oriented substrate with a like horizontally oriented bonding surface. The process includes estimating an amount that a material of the first TSV will expand when heated to a preselected temperature, based on a volume of the material of the first TSV and a coefficient of thermal expansion (CTE) of the material of the first TSV. The process includes forming a first metal contact pad at the first bonding surface and coupled to the first TSV, based on the estimate or based on a volume of the material of the first TSV and a coefficient of thermal expansion (CTE) of the material of the first TSV.

The first metal contact pad is disposed at the first bonding surface (and is disposed directly over the first TSV), and extends partially into the first substrate below the first bonding surface, electrically coupling the first metal contact pad to the first TSV. The process includes planarizing the first bonding surface to have a predetermined maximum surface variance for direct bonding, and the first metal contact pad to have a predetermined recess relative to the first bonding surface, based on the volume of the material of the first TSV and the coefficient of thermal expansion (CTE) of the material of the first TSV.

According to the claimed invention, selecting or forming the contact pad comprises selecting a diameter or a surface area of the first metal contact pad. For instance, a first metal contact pad may be selected or formed to have an oversized diameter, an oversized surface area, or the like, than typical for a like application. The process includes determining a desired recess for the first metal contact pad relative to the first bonding surface, to allow for expansion of the material of the first TSV and the material of the first metal contact pad, based on the predicting, and selecting the first metal contact pad to have a perimeter shape likely to result in the desired recess when the first metal contact pad is planarized. This includes forecasting an amount of recess that is likely to occur in a surface of the first metal contact pad as a result of the planarizing. The process according to the claimed invention includes forming the desired recess in a surface of the first metal contact pad (prior to bonding), based on the determining.

The process includes reducing or eliminating delamination of bonded microelectronic components by selecting the first metal contact pad. In an alternate implementation, the process includes recessing or eroding material of the first bonding surface directly around the first metal contact pad to allow for expansion of the material of the first TSV and the material of the first metal contact pad, based on the volume of the material of the first TSV and the coefficient of thermal expansion (CTE) of the material of the first TSV.

Additionally, the back side of the first substrate may also be processed for bonding. One or more insulating layers of preselected materials may be deposited on the back side of the first substrate to provide stress relief when the back side of the first substrate is to be direct bonded.

Further, the first TSV, as well as other TSVs within the first substrate may be used to direct or transfer heat within the first substrate and/or away from the first substrate. In some implementations, the thermal transfer TSVs may extend partially or fully through a thickness of the first substrate and may include a thermally conductive barrier layer. In such examples, barrier layers normally used around the TSVs that tend to be thermally insulating may be replaced with thermally conductive layers instead. In various implementations, some TSVs may be used for signal transfer and thermal transfer.

According to the claimed invention, a microelectronic assembly comprises a first substrate including a first bonding surface with a planarized topography having a first predetermined maximum surface variance. A first through silicon via (TSV) is embedded into the first substrate and a first metal contact pad is disposed at the first bonding surface and is electrically coupled to the first TSV. The first contact pad is disposed over the first TSV. The first metal contact pad is selected or formed based on an estimate of an amount that a material of the first TSV will expand when heated to a preselected temperature and/or based on a volume of the material of the first TSV and a coefficient of thermal expansion (CTE) of the material of the first TSV. A predetermined recess is disposed in a surface of the first metal contact pad, having a volume equal to or greater than an amount of expansion of the material of the first TSV and an amount of expansion of a material of the first metal contact pad when heated to the preselected temperature.

In an implementation, the first metal contact pad is positioned over the first TSV and the first metal contact pad has an oversized diameter or an oversized surface area than a pad typically used for a like application.

Various implementations and arrangements are discussed with reference to electrical and electronics components and varied carriers. While specific components (i.e., dies, wafers, integrated circuit (IC) chip dies, substrates, etc.) are mentioned, this is not intended to be limiting, and is for ease of discussion and illustrative convenience. The techniques and devices discussed with reference to a wafer, die, substrate, or the like, are applicable to any type or number of electrical components, circuits (e.g., integrated circuits (IC), mixed circuits, ASICS, memory devices, processors, etc.), groups of components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), and the like, that may be coupled to interface with each other, with external circuits, systems, carriers, and the like. Each of these different components, circuits, groups, packages, structures, and the like, can be generically referred to as a "microelectronic component. " For simplicity, unless otherwise specified, components being bonded to another component will be referred to herein as a "die.

Referring to <FIG> (showing a cross-sectional profile view) and FIG. IB (showing a top view), patterned metal and oxide layers are frequently provided on a die, wafer, or other substrate (hereinafter "die <NUM>") as a hybrid bonding, or DBI®, surface layer. A representative device die <NUM>, which does not fall within the scope of the claimed invention, may be formed using various techniques, to include a base substrate <NUM> and one or more insulating or dielectric layers <NUM>. The base substrate <NUM> may be comprised of silicon, germanium, glass, quartz, a dielectric surface, direct or indirect gap semiconductor materials or layers or another suitable material. The insulating layer <NUM> is deposited or formed over the substrate <NUM>, and may be comprised of an inorganic dielectric material layer such as oxide, nitride, oxynitride, oxycarbide, carbides, carbonitrides, diamond, diamond like materials, glasses, ceramics, glass-ceramics, and the like.

A bonding surface <NUM> of the device wafer <NUM> can include conductive features <NUM>, such as traces, pads, and interconnect structures, for example, embedded into the insulating layer <NUM> and arranged so that the conductive features <NUM> from respective bonding surfaces <NUM> of opposing devices can be mated and joined during bonding, if desired. The joined conductive features <NUM> can form continuous conductive interconnects (for signals, power, etc.) between stacked devices.

Damascene processes (or the like) may be used to form the embedded conductive features <NUM> in the insulating layer <NUM>. The conductive features <NUM> may be comprised of metals (e.g., copper, etc.) or other conductive materials, or combinations of materials, and include structures, traces, pads, patterns, and so forth. In some examples, a barrier layer may be deposited in the cavities for the conductive features <NUM> prior to depositing the material of the conductive features <NUM>, such that the barrier layer is disposed between the conductive features <NUM> and the insulating layer <NUM>. The barrier layer may be comprised of tantalum, for example, or another conductive material, to prevent or reduce diffusion of the material of the conductive features <NUM> into the insulating layer <NUM>. After the conductive features <NUM> are formed, the exposed surface of the device wafer <NUM>, including the insulating layer <NUM> and the conductive features <NUM> can be planarized (e.g., via CMP) to form a flat bonding surface <NUM>.

Forming the bonding surface <NUM> includes finishing the surface <NUM> to meet dielectric roughness specifications and metallic layer (e.g., copper, etc.) recess specifications, to prepare the surface <NUM> for direct bonding. In other words, the bonding surface <NUM> is formed to be as flat and smooth as possible, with very minimal surface topology variance. Various conventional processes, such as chemical mechanical polishing (CMP), dry or wet etching, and so forth, may be used to achieve the low surface roughness. This process provides the flat, smooth surface <NUM> that results in a reliable bond.

In the case of double-sided dies <NUM>, a patterned metal and insulating layer <NUM> with prepared bonding surfaces <NUM> may be provided on both sides of the die <NUM>. The insulating layer <NUM> is typically highly planar (usually to nm-level roughness) with the metal layer (e.g., embedded conductive features) at or recessed just below the bonding surface <NUM>. The amount of recess below the surface <NUM> of the insulating layer <NUM> is typically determined by a dimensional tolerance, specification, or physical limitation. The bonding surfaces <NUM> are often prepared for direct bonding with another die, wafer, or other substrate using a chemical-mechanical polishing (CMP) step and/or other preparation steps.

Some embedded conductive features or interconnect structures may comprise metal pads <NUM> or conductive traces <NUM> that extend partially into the dielectric substrate <NUM> below the prepared surface <NUM>. For instance, some patterned metal (e.g., copper) features <NUM> or <NUM> may be about <NUM> - <NUM> microns thick. The metal of these features <NUM> or <NUM> may expand as the metal is heated during annealing. Other conductive interconnect structures may comprise metal (e.g., copper) through silicon vias (TSVs) <NUM> or the like, that extend normal to the bonding surface <NUM>, partly or fully through the substrate <NUM> and include a larger quantity of metal. For instance, a TSV <NUM> may extend about <NUM> microns, depending on the thickness of the substrate <NUM>. The metal of the TSV <NUM> may also expand when heated. Pads <NUM> and/or traces <NUM> may or may not be electrically coupled to TSVs <NUM>, as shown in <FIG>.

Referring to <FIG>, dies <NUM> may be direct bonded, for instance, without adhesive to other dies <NUM> with metal pads <NUM>, traces <NUM>, and/or TSVs <NUM>. If a metal pad <NUM> is positioned over a TSV <NUM> (electrically coupled to the TSV <NUM>), the expansion of the TSV <NUM> metal can contribute to the expansion of the pad <NUM> metal. In some cases, the combined metal expansion can cause localized delamination <NUM> of the bonding surfaces at the location of the TSV <NUM> (or TSV <NUM>/pad <NUM> combination), as the expanding metal rises above the bonding surface <NUM>. For instance, the expanded metal can separate the bonded dielectric surfaces <NUM> of the stacked dies <NUM>.

Referring to <FIG>, in accordance with the claimed invention, techniques are employed to mitigate the potential for delamination due to metal expansion. According to the claimed invention, a metal pad <NUM> having a larger diameter or surface area (i.e. oversized for the application) is used in place of a contact pad <NUM> when positioned over a TSV <NUM>. The pad <NUM> has a larger diameter than other contact pads <NUM> at the surface <NUM> of the die <NUM>, so that the pad <NUM> will have a deeper recess for a given CMP process than the other contact pads <NUM> that are not positioned over a TSV <NUM>. Similar to the contact pads <NUM>, the contact pad <NUM> is embedded in the dielectric layer <NUM>, extending partially into the dielectric layer <NUM> below the bonding surface <NUM>, and electrically coupled to the TSV <NUM>. The amount of oversize of the metal pad <NUM> is selected based on the material of the pad <NUM>, its thickness, and anticipated recess during CMP processing.

As shown in <FIG> (showing a cross-sectional profile view) and <FIG> (showing a top view), pads <NUM> disposed over TSVs <NUM> are larger (in area, diameter, etc.), by a preselected amount, than other pads <NUM> disposed elsewhere at the bonding surface <NUM> of the die <NUM>, not disposed over TSVs <NUM>. According to the claimed invention, the pads <NUM> are selected or formed by estimating an amount that the material of the TSV <NUM> will expand when heated to a preselected temperature (~<NUM>°), based on a volume of the material of the TSV <NUM> and a coefficient of thermal expansion (CTE) of the material of the TSV <NUM>, and predicting an amount that the material of the contact pad <NUM> will expand when heated to the preselected temperature, based on a volume of the material of the contact pad <NUM> and a CTE of the material of the contact pad.

The contact pad <NUM> is planarized along with the bonding surface <NUM> of the dielectric layer <NUM>, including recessing the contact pad <NUM> to have a predetermined recess depth (or amount) relative to the bonding surface <NUM> based on estimating and predicting the expansion of the TSV <NUM> material and the contact pad <NUM> material at the preselected temperature.

Referring to <FIG>, after preparation of the bonding surface <NUM> (e.g., by CMP) the dies <NUM> may be direct bonded, for instance, without adhesive to other dies <NUM> with metal pads <NUM> and/or <NUM>, traces <NUM>, and/or TSVs <NUM>. When a metal pad <NUM> is positioned over a TSV <NUM>, and is recessed a predetermined or predictable amount, the recess provides room for material expansion without delamination. The TSV <NUM> material and the pad <NUM> material expand during heated annealing. The mating contact pads <NUM> (or <NUM> and <NUM> in some examples) of opposite dies <NUM> bond to form a single conductive interconnect. However, the combined metal expansion does not cause delamination of the bonding surfaces since the expanding metal does not exceed the volume formed by the recess(es) in the contact pads <NUM> (or <NUM> and <NUM> in some examples). For instance, if the volume of the recess(es) is sufficient, the expanded metal does not separate the bonded dielectric surfaces <NUM> of the stacked dies <NUM>, as shown in <FIG>.

Referring to <FIG>, details of contact pads <NUM> and <NUM> over TSVs <NUM> are illustrated in order to facilitate the understanding of the claimed invention. A portion of a die <NUM> is shown, first with a contact pad <NUM> over a TSV <NUM> (<FIG>) and then with a contact pad <NUM> over a TSV <NUM> (<FIG>). When using surface preparation processes such as CMP to prepare the bonding surface <NUM> of the die <NUM>, the metal pads <NUM> or <NUM> on the bonding surface <NUM> can tend to become recessed relative to the dielectric <NUM>, due to the softness of the contact pads <NUM> or <NUM> (which may comprise copper, for instance) relative to the dielectric <NUM> (which may comprise an oxide, for example).

In various embodiments, a contact pad <NUM> with a larger diameter or surface area A2 than a contact pad <NUM> with a smaller diameter or surface area A1 (shown at <FIG>, where A2 > A1) may become recessed to a greater degree "d2" (e.g., a deeper recess) than the recess "d1" of the smaller diameter pad <NUM> during a similar CMP process. The deeper recess "d2" can compensate for the combined metal expansion of the pad <NUM> and the TSV <NUM>, allowing more room for expansion of the metal, and can reduce or eliminate delamination. In accordance with the claimed invention, the contact pad <NUM> is intentionally recessed to the desired depth "d2" and the contact pad <NUM> is selected due to the predictable recess "d2" that results from surface <NUM> preparation by CMP (or other processing), based on the size (diameter and/or surface area), material composition, etc. of the pad <NUM>.

In various embodiments, the amount of recessing (e.g., d1, d2, etc.) of a metal pad <NUM> or <NUM> may be predictable, based on the surface preparation technique used (e.g., the chemical combination used, the speed of the polishing equipment, etc.), the materials of the dielectric layer <NUM> and the metal pads <NUM> and <NUM>, the spacing or density of the metal pads <NUM> and <NUM>, and the size (e.g., area or diameter) of the metal pads <NUM> and <NUM>. In the embodiments, the area or diameter of the metal pads <NUM> and <NUM> are selected (e.g., for a particular metal thickness) to avoid delamination of bonded dies <NUM> based on the recess prediction and the expected metal expansion of the TSV <NUM> and metal pad <NUM> or <NUM> combination. According to the claimed invention, larger sized pads <NUM> are used over TSVs <NUM> and smaller sized pads <NUM> may be used over dielectric <NUM> (to avoid excessive recessing of these pads <NUM>). This technique results in reduced or eliminated delamination, as well as dependable mechanical coupling of the dielectric <NUM> and metal structures (<NUM>, <NUM>, <NUM>, and/or <NUM>) on the bonding surfaces <NUM> and reliable electrical continuity of the bonded metal structures (<NUM>, <NUM>, <NUM>, and/or <NUM>).

In one embodiment, a metal pad <NUM>, <NUM> may be selectively etched (via acid etching, plasma oxidation, etc.) to provide a desired recess depth (to accommodate a predicted metal expansion). In another embodiment, a pad <NUM>, <NUM> or a corresponding TSV <NUM> may be selected, formed, or processed to have an uneven top surface as an expansion buffer. For example, referring to <FIG>, the top surface of the pad <NUM> (or TSV <NUM> in some cases) may be formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat to allow room for material expansion.

As shown at <FIG>, the top or bonding surface of the contact pads <NUM> are selected, formed, or processed to have an uneven surface. As shown at B, after material expansion due to heated annealing, the pads <NUM> make contact and are bonded. However, with an adequate space for expansion provided by the uneven top surfaces of the pads <NUM>, the material does not exceed the space provided, and so delamination of the bonded dies <NUM> does not occur.

Additionally or alternately, as shown in <FIG>, the dielectric <NUM> around the metal pad <NUM> or <NUM> can be formed or shaped to allow room for the metal of the pad <NUM> or <NUM> (and TSV <NUM>) to expand. In one example, a CMP process can be used to shape the surface <NUM> of the dielectric <NUM> around the metal pad <NUM>, or in other examples other processes can be used, so that the dielectric <NUM> around the pad <NUM> includes a recess <NUM> or other gap that provides room for metal expansion.

In an embodiment, the dielectric <NUM> can be recessed (e.g., with CMP) while the bonding surface <NUM> is being prepared. In the embodiment, the metal pad <NUM> or <NUM> and the dielectric <NUM> may be recessed concurrently (but at different rates). For instance, the process may form erosion <NUM> in the dielectric <NUM> around the edges of the metal pad <NUM> or <NUM> while recessing the metal pad <NUM> or <NUM>.

In various embodiments, the pad <NUM> or <NUM> and/or the TSV <NUM> are comprised of copper, a copper alloy, or the like. In a further embodiment, the materials of the pad <NUM> or <NUM> and/or the TSV <NUM> may be varied to control metal expansion and potential resulting delamination. For instance, in some embodiments, the pad <NUM> or <NUM> and/or the TSV <NUM> may be comprised of different conductive materials, perhaps with lower CTEs. In some embodiments the TSV <NUM> may be comprised of a different conductive material (with a lower CTE) than the contact pad <NUM> or <NUM>. For example, the TSV <NUM> may be comprised of tungsten, an alloy, or the like.

In other embodiments the volume of material of the TSV <NUM> may be varied to control metal expansion and the potential for resulting delamination. For instance, in some embodiments, a TSV <NUM> with a preselected material volume (e.g., less volume of material) may be used to control delamination, when this is allowable within the design specifications. The preselection of volume of the TSV <NUM> may be based on predicted material expansion (of the TSV <NUM> and a contact pad <NUM> or <NUM>, when applicable).

Alternately, the top surface of the TSV <NUM> can be arranged to be exposed at the bonding surface <NUM> and used as a contact pad. These arrangements can avoid combining the expansion of the metal pad <NUM> or <NUM> with that of the TSV <NUM>, and so minimizing or eliminating delamination. In a further embodiment, the TSV <NUM> can be formed so that the TSV <NUM> extends partially (rather than fully) through the thickness of the substrate <NUM>, terminating below the bonding surface <NUM>. According to the claimed invention, a gap or recess is provided in the bonding surface <NUM> over the TSV <NUM> to allow room for the metal of the TSV <NUM> to expand, without causing delamination. For instance, the gap can be formed by etching the dialectic layer <NUM>. The gap may or may not expose the TSV <NUM>. The gap can be tuned, for example, to the volume of the TSV <NUM>, using a prediction of the expansion of the TSV <NUM>, based on the volume of the particular metal of the TSV <NUM>.

<FIG> illustrate examples of backside die <NUM> processing, according to various embodiments. In some implementations, where dies <NUM> are stacked and direct bonded without adhesive, the backside <NUM> of the die <NUM> may receive different preparation than the topside bonding surface <NUM>, when the backside <NUM> is prepared for direct bonding. Instead of forming the dielectric layer <NUM> on the backside <NUM> of the die <NUM>, the backside <NUM> may be prepared differently to reduce process steps, reduce manufacturing costs, or for other reasons.

In one implementation, the backside <NUM> is prepared so that the backend of the TSV <NUM> is exposed, to be used as a contact surface for bonding to a conductive pad, interconnect, or other conductive bonding surface. The preparation may include thinning and selectively etching the base substrate <NUM> to expose the TSV <NUM> with the liner/barrier layer <NUM> intact, depositing one or more layers of insulating materials and planarizing (via CMP, for example) the backside <NUM> to reveal the TSV <NUM>. In some cases, however, the expansion of the material of the TSV <NUM> during heated annealing can cause the insulating material and/or the substrate <NUM> to deform and rise above the planarized surface.

In an embodiment, as shown in <FIG>, one or more layers of material may be deposited on the backside <NUM> to cover up the raised area so the new surface can be re-planarized for good dielectric-to-dielectric bonding. Another important function of the multi-layer structure is to balance the stress between the front and back side of the die <NUM> to minimize die warpage prior to bonding. A balanced die <NUM> is easier to bond and less prone to bonding voids. The added layers of material can be planarized and otherwise prepared as a bonding surface on the backside <NUM> of the die <NUM>.

As shown at <FIG>, the TSV <NUM> is disposed within the die <NUM>, transverse to the bonding surface <NUM> of the die <NUM>. The TSV <NUM> may extend beyond the surface of the base substrate <NUM> after selective etching of the base substrate <NUM>. A diffusion barrier and oxide liner <NUM> surrounds the TSV <NUM> to prevent diffusion of the metal of the TSV <NUM> (e.g., copper) into the material of the base substrate <NUM> (e.g., silicon). In an embodiment, as shown at <FIG>, another diffusion barrier <NUM> is deposited on the surface of the backside of the die <NUM>. In an example, the diffusion barrier <NUM> comprises a dielectric, such as a nitride or the like.

In various embodiments, one or more inorganic dielectric layers which may have different residue stress characteristics are then deposited onto the backside <NUM> of the die <NUM> to enable proper reveal of the TSV <NUM> and to balance stress on the device side (front side) of the die <NUM> to minimize die warpage after singulation. For example, a first layer <NUM>, comprising a first low temperature dielectric, such as an oxide, may be deposited over the backside <NUM>, including the diffusion layer <NUM>.

In some embodiments, a second layer <NUM>, comprising a second low temperature dielectric, such as a second oxide, may be deposited over the backside <NUM>, including the first layer <NUM>. The second oxide layer <NUM> may have a similar or a different residue stress characteristic than the first layer <NUM> (for example, the first layer <NUM> may be compressive and the second layer <NUM> may be tensile, or vice versa, or both layers <NUM> and <NUM> may be compressive or tensile with similar or different values). In various implementations, the first layer <NUM> and the second <NUM> layer are comprised of similar or the same materials (in varying thicknesses). In other implementations, the first layer <NUM> and the second <NUM> layer are comprised of different materials. In alternate implementations, additional dielectric layers may also be deposited over the first <NUM> and second <NUM> layers.

As shown at <FIG>, the backside <NUM> is planarized (via CMP, for example), including the one or more stress layers <NUM> and <NUM> to form a flat, smooth bonding surface for direct bonding. Part of the second layer <NUM> may be left on the backside <NUM> to aid with mitigating damage, such as the oxide ring effect. Additionally, the remaining portion of the second layer <NUM> can assist with warpage control, based on a residue stress characteristic of the second layer <NUM>.

In another embodiment, as shown in <FIG>, a contact pad <NUM> may be coupled to the TSV <NUM> on the backside <NUM> of the die <NUM>. As shown at <FIG>, after deposition of the first dielectric layer (low temperature oxide stress layer <NUM>, for example), which also comprises the bonding layer in some implementations, the TSV <NUM> is fully exposed and planarized by a process such as CMP. A second dielectric layer <NUM> (which may comprise an oxide) may be deposited over the first layer <NUM> and planarized. No barrier or adhesion layer is needed between the two oxide layers (<NUM> and <NUM>). After planarization, the backside <NUM> is patterned and opened (e.g., etched, etc.) for deposition of a conductive pad. As shown in <FIG>, the opening <NUM> in the oxide layers <NUM> and <NUM> may have a larger diameter than that of the TSV <NUM>.

In an embodiment, the opening <NUM> for the contact pad <NUM> extends through the second layer <NUM> and partially (<NUM>-<NUM>) into the first layer <NUM>. A barrier/adhesion layer <NUM> (comprising titanium/titanium nitride, tantalum/tantalum nitride, etc.) may be deposited into the opening <NUM> (and may cover the entire surface of the opening <NUM>), as shown at <FIG>. A copper (or the like) deposition/plating (e.g., damascene process) fills the opening <NUM>, which is planarized (via CMP, for example) to remove excess copper and to set the resulting contact pad <NUM> recess to a specified depth. The backside <NUM> surface is prepared for bonding at this point.

In an alternate embodiment, a dual damascene process may be used to form the contact pad <NUM>, as shown in <FIG>. In the embodiment, after depositing the second dielectric layer <NUM> (which may comprise an oxide) onto the first layer <NUM> (with no barrier or adhesion layer), the resulting backside <NUM> surface is patterned twice to form a unique opening <NUM> for the contact pad <NUM> in a dual damascene process. At first a small opening, with a diameter smaller than the diameter of the TSV <NUM> is etched partially through the layer <NUM>, then a large opening (larger diameter than the diameter of the TSV <NUM>) over the small opening is patterned and etched, resulting in a smaller opening extending to the TSV <NUM> and a larger opening partially through layer <NUM>. For instance, in some cases, design rules dictate the presence of a via layer.

A thickness of the second dielectric layer <NUM> (top layer) and a thickness of the contact pad <NUM> may be adjusted to minimize thin die warpage, and to achieve a desired anneal temperature.

<FIG> show example stacking arrangements of the dies <NUM> formed with regard to <FIG> (and like structures) with front side <NUM> and backside <NUM> interconnectivity. For example, at <FIG>, an example "front-to-back" die <NUM> stack arrangement is shown. This bonds a front side bonding surface <NUM> of a first die <NUM> to a backside <NUM> bonding surface of a second die <NUM>, including a contact pad <NUM> or <NUM> of the first die <NUM> to a contact pad <NUM> of the second die <NUM>. In an example, as discussed above, the contact pad <NUM> of the second die <NUM> penetrates into the second dielectric layer <NUM> and the first dielectric layer <NUM> of the second die <NUM>, below the bonding interface <NUM>.

At <FIG>, an example "back-to-back" die <NUM> stack arrangement is shown. This bonds a backside <NUM> bonding surface of a first die <NUM> to a backside <NUM> bonding surface of a second die <NUM>, including a contact pad <NUM> of the first die <NUM> to a contact pad <NUM> of the second die <NUM>. In an example, as discussed above, the contact pads <NUM> of the first and second dies <NUM> penetrate into the second dielectric layer <NUM> and the first dielectric layer <NUM> of the first and second dies <NUM>, below the bonding interface <NUM>.

At <FIG>, an example "front-to-front" die <NUM> stack arrangement is shown. This bonds a front side bonding surface <NUM> of a first die <NUM> to a front side bonding surface <NUM> of a second die <NUM> at the bonding interface <NUM>, including a contact pad <NUM> or <NUM> of the first die <NUM> to a contact pad <NUM> or <NUM> of the second die <NUM>. In the example shown, the contact pads <NUM> or <NUM> are electrically coupled to the TSVs <NUM> of the respective dies <NUM>.

In various examples, not falling within the scope of the claimed invention, as illustrated at <FIG>, one or more of the TSVs <NUM> of a set of stacked dies <NUM> may be used to conduct heat in addition to or instead of electrical signals. For example, in some cases, it may not be practical or possible to attach a heat sink (or other heat transfer device) to a die <NUM> of a set of stacked dies <NUM> to alleviate heat generated by the die <NUM>. In such cases, other techniques may be looked-for to transfer heat as desired.

In the examples, as shown at <FIG>, various configurations of TSVs <NUM>, including TSVs that extend partially or fully through a die <NUM>, may be employed to conduct heat away from the dies <NUM> (or away from a heat-generating portion of the dies <NUM>). The TSVs <NUM> of one die <NUM> may be used in conjunction with TSVs <NUM>, contact pads <NUM> and <NUM>, traces <NUM>, and the like, of the second die <NUM> to complete heat transfer from one die <NUM> to the other die <NUM>, and so forth. The TSVs <NUM> of the first die <NUM> can be direct bonded (e.g., DBI) to the TSVs <NUM>, contact pads <NUM> and <NUM>, traces <NUM>, and the like of the second die <NUM> for high performance thermal conductivity.

In an implementation, some of the TSVs <NUM>, contact pads <NUM> and <NUM>, traces <NUM>, and the like are electrically floating or "dummy" structures, which can be used for thermal transfer. These structures may conduct heat away from a high power die <NUM> to another die <NUM> or substrate as desired. Dummy contact pads <NUM> or <NUM> may be coupled to via last or via mid thermal TSVs <NUM> for thermal conduction.

In the embodiments, diffusion barrier/oxide liner layers <NUM>, which surround the TSVs <NUM> and can be thermally restrictive or thermal barriers may be replaced by diffusion barrier/oxide liners of a different material having some thermal conductivity (such as metal or alloy barriers, or the like).

<FIG> illustrates a representative process <NUM> for preparing various microelectronic components (such as dies <NUM>, for example) for bonding, such as for direct bonding without adhesive, while reducing or eliminating the potential for delamination due to metal expansion of embedded structures at the bonding surface. For instance, through-silicon vias (TSVs) at the bonding surface may cause delamination, particularly when coupled to contact pads, as the material of the TSVs and the contact pads expands during heated annealing. The process refers to <FIG>.

The order in which the process is described is not intended to be construed as limiting, and any number of the described process blocks in the process can be combined in any order to implement the process, or alternate processes.

In an implementation, a die, wafer, or other substrate (a "substrate") is formed using various techniques to include a base substrate and one or more dielectric layers. In the implementation, at block <NUM>, the process <NUM> includes embedding a first through silicon via (TSV) (such as TSV <NUM>, for example) into a first substrate (such as die <NUM>, for example) having a first bonding surface (such as bonding surface <NUM>, for example), the first TSV normal to the first bonding surface.

In the implementation, at block <NUM>, the process includes forming a first metal contact pad (such as contact pad <NUM>, for example) at the first bonding surface and electrically coupled to the first TSV, based on a volume of the material of the first TSV and a coefficient of thermal expansion (CTE) of the material of the first TSV. In an embodiment, the first metal contact pad extends partially into the first substrate below the first bonding surface.

At block <NUM>, the process includes planarizing the first bonding surface to have a predetermined maximum surface variance for direct bonding and the first metal contact pad to have a predetermined recess relative to the first bonding surface based on the volume of the material of the first TSV and the coefficient of thermal expansion (CTE) of the material of the first TSV. In an implementation, the process includes predicting an amount that a material of the first metal contact pad will expand when heated to a preselected temperature, based on a volume of the material of the first metal contact pad and a CTE of the material of the first metal contact pad, and determining a size of the first metal contact pad based on the estimating combined with the predicting. In one implementation, the process includes selecting a diameter or a surface area of the first metal contact pad.

In an implementation, the process includes electrically coupling the first metal contact pad to the first TSV.

In an implementation, the process includes determining a desired recess for the first metal contact pad relative to the first bonding surface, to allow for expansion of the material of the first TSV and the material of the first metal contact pad, based on the estimating and the predicting; and selecting the first metal contact pad to have a perimeter shape likely to result in the desired recess when the first metal contact pad is planarized.

In another implementation, the process includes determining a desired recess for the first metal contact pad relative to the first bonding surface, to allow for expansion of the material of the first TSV and the material of the first metal contact pad based on the predicting; and forming the desired recess in a surface of the first metal contact pad.

In another implementation, the process includes selecting the first metal contact pad to have an oversized diameter or an oversized surface area than typical for a like application.

In a further implementation, the process includes forecasting an amount of recess that is likely to occur in a surface of the first metal contact pad as a result of the planarizing.

In another implementation, the process includes recessing or eroding material of the first bonding surface directly around the first metal contact pad to allow for expansion of the material of the first TSV and a material of the first metal contact pad, based on the estimating.

In an implementation, the process includes forming a recess in the first bonding surface over the first TSV to allow for expansion of the material of the first TSV. In another implementation, the process includes tuning a volume of the recess in the first bonding surface based on the estimating.

Claim 1:
A method (<NUM>) of forming a microelectronic assembly having a plurality of metal contact pads (<NUM>; <NUM>, <NUM>) and at least one through substrate via, TSV (<NUM>), the method comprising:
providing (<NUM>) a first TSV (<NUM>) in a first substrate (<NUM>) having a first bonding surface (<NUM>), the first TSV normal to the first bonding surface;
forming (<NUM>) a first metal contact pad (<NUM>, <NUM>) in the first bonding surface, the first metal contact pad electrically coupled to the first TSV, the first metal contact pad extending partially into the first substrate below the first bonding surface and aligned with the first TSV in the direction from the first bonding surface through the first substrate;
forming a second metal contact pad (<NUM>) in the first bonding surface, wherein no TSV is disposed under the second metal contact pad in the direction from the first bonding surface through the first substrate, the first metal contact pad having a larger surface area than a surface area of the second metal contact pad; and
planarizing (<NUM>) the first bonding surface to have a surface variance less than or equal to a maximum surface variance for direct bonding;
wherein the larger surface area of the first metal contact pad and the surface area of the second metal pad are dimensioned to cause, during the planarization, a first recess of the first metal contact pad relative to the first bonding surface and a second recess of the second metal contact pad relative to the first bonding surface, the first recess being greater than the second recess by a predetermined amount suitable for compensating, during direct bonding, for thermal expansion of the first TSV, the first metal contact pad and the second metal contact pad relative to the first bonding surface.