Patent Description:
The document <CIT> discloses a system arranged for carrying out time stamping comprising a Serializer/Deserializer (SerDes).

Further embodiments are depicted in the dependent claims.

In one aspect, embodiments of the inventive concepts disclosed herein are directed to a system. The system includes a field-programmable gate array (FPGA). The FPGA includes an input pad configured to receive a signal, an input serializer, and an x-bit wide shift register. The input serializer includes x serializer shift registers, wherein x is an integer greater than or equal to <NUM>. The input serializer is configured to receive the signal, wherein the signal passes through each serializer shift register in series. The input serializer is configured to output parallel data at the output of each serializer shift register indicative of the signal. Each serializer shift register shifts data at the time period of a serializer clock of the input serializer. The input serializer takes x time periods to complete output of the parallel data. The FPGA further comprises an x-bit wide shift register communicatively coupled to the input serializer. The x-bit wide shift register is configured to receive the parallel data from the input serializer. The x-bit wide shift register is sampled at a shift register clock to provide a value with each bit shift of the value corresponding to one of the x time periods for the parallel data. A speed of the shift register clock is less than a speed of the serializer clock. The x-bit wide shift register has a shift register latency value indicative of an amount of time for the signal to travel from the input pad through the x-bit wide shift register. The FPGA is configured to: determine a time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value; and determine a time when the signal arrived at the input pad based at least on the shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.

In a further aspect, embodiments of the inventive concepts disclosed herein are directed to a method. The method includes receiving a signal by an input pad of a field-programmable gate array (FPGA). The method further includes receiving the signal by an input serializer of the FPGA, the input serializer comprising x serializer shift registers, wherein x is an integer greater than or equal to <NUM>, wherein the signal passes through each serializer shift register in series. The method further includes outputting, by the input serializer, parallel data indicative of the signal, wherein each serializer shift register shifts data at the time period of a serializer clock of the input serializer, wherein the input serializer takes x time periods to complete output of the parallel data. The method further includes receiving, by an x-bit wide shift register of the FPGA, the parallel data from the input serializer, the x-bit wide shift register communicatively coupled to the input serializer, wherein the x-bit wide shift register is sampled at a shift register clock to provide a value with each bit shift of the value corresponding to one of the x time periods for the parallel data, wherein a speed of the shift register clock is less than a speed of the serializer clock, wherein the x-bit wide shift register has a shift register latency value indicative of an amount of time for the signal to travel from the input pad through the x-bit wide shift register. The method further includes determining, by the FPGA, a time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value. The method further includes determining, by the FPGA, a time when the signal arrived at the input pad based at least on the shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.

The appearances of the phrase "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, and embodiments of the inventive concepts disclosed may include one or more of the features expressly described or inherently present herein.

Broadly, embodiments of the inventive concepts disclosed herein are directed to a method and a system including an FPGA configured to determine a time when a signal arrived at an input pad of the FPGA. As moving towards smaller independent systems becomes more prevalent, maintaining timing between two systems may be important for signal characterization and location. Maintaining precision timing may also provide accurate time stamping for post processing and analysis.

Inputs and outputs (IO) on FPGAs may be capable of sampling at close to <NUM> billion samples per second on modern FPGAs utilizing input double data rate (DDR) registers and input serialization and deserialization registers. FPGAs may contain shift registers just behind IO pins to allow for sampling of general purpose IO into the gigahertz (GHz) ranges. In some embodiments, by going to a x4 or x8 serialization input a design can sample an input pad (e.g., an input pin or input ball) at sample rates exceeding <NUM> billion samples per second. In some embodiments, by using IO resources that can be in the gigabit per second sample rates, it may be possible to time an input signal edge with accuracies within <NUM> ns. Some embodiments, may include any suitable FPGA, such as a Xilinx Ultrascale FPGA or an Intel FPGA. Some embodiments may utilize input deserializers in parallel to provide high speed data interfaces between FPGAs or external peripherals such as DDR4 synchronous dynamic random access memory (SDRAM). Such IO resources can be utilized on a single input pin to provide a precise time of arrival of the signal at the pin.

Referring now to <FIG>, an exemplary embodiment of a system <NUM> according to the inventive concepts disclosed herein is depicted. The system <NUM> may be implemented as any suitable system, such as a multiple vehicle system (e.g., at least one aircraft, at least one watercraft, at least one submersible craft, at least one automobile, and/or at least one train), a multiple FPGA system, and/or a multiple computing device system. For example, as shown in <FIG>, the system <NUM> may include a system <NUM> and a system <NUM>.

In some embodiments, the system <NUM> may be at least one computing device and/or a vehicle including at least one computing device. For example, the system <NUM> may include two FPGAs <NUM>-<NUM>, <NUM>-<NUM>, though the system <NUM> may include any suitable number of FPGAs.

The first FPGA <NUM>-<NUM> may be configured to receive a first data stream. The second FPGA <NUM>-<NUM> may be configured to receive a second data stream. The third FPGA <NUM>-<NUM> may be configured to receive a third data stream. The fourth FPGA <NUM>-<NUM> may be configured to receive a fourth data stream. Each of the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> may also be configured to receive a signal (e.g., a trigger signal or a GPS strobe). Each of the FPGAs <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> may be configured to determine a time when the signal arrived at the input pad <NUM> of the particular FPGA. For example, each FPGA <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> may be configured for: timestamping data with the time when the signal arrived at the input pad <NUM>; utilizing the time when the signal arrived at the input pad <NUM> to perform data alignment; and/or utilizing the time when the signal arrived at the input pad <NUM> to perform clock synchronization operations. Some embodiments may be configured to maintain precise time synchronization across multiple FPGAs or systems. Some embodiments may be configured to increase accuracy in timestamping of collected data for post processing multiple systems. Some embodiments may allow for precision triggering to be better aligned to the trigger. Some embodiments may allow for data alignment across multiple inputs (e.g., of a single chip, of multiple chips, or of multiple systems).

Referring now to <FIG>, each FPGA <NUM> may include at least one input pad <NUM> (e.g., an input pin or an input ball), at least one input register <NUM>, at least two DDR registers <NUM>, at least one input serializer <NUM>, and/or at least one x-bit wide shift register (e.g., input deserializer <NUM>).

The input pad <NUM> may be configured to connect to a circuit card assembly (e.g., a printed circuit board (PCB)) and to receive a signal (e.g., a trigger signal or a GPS strobe).

The input register <NUM> may be located in the FPGA <NUM> directly behind the input pad <NUM>. In some embodiments, the input register may have a maximum sample rate of approximately <NUM> megahertz (MHz), though any suitable sample rate may be used.

The DDR registers <NUM> may be a set of two registers sampling on opposite edges of a sample clock to improve data rates to twice the sample clock of the input register. For example, the DDR registers <NUM> may have a sample rate of approximately <NUM>, though any suitable sample rate may be used.

The input serializer <NUM> may include a clock multiplier <NUM> and a plurality of shift registers <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> that may be able to sample at rates many times the sample clock rate of the input register <NUM>. For example, the input serializer <NUM> may be configured to sample at approximately <NUM>, though any suitable sample rate may be used. The input serializer <NUM> may include x serializer shift registers <NUM>, wherein x is an integer greater than or equal to <NUM>. For example, x may be <NUM> or <NUM>, though any suitable number greater than <NUM> may be used. The input serializer <NUM> may be configured to receive the signal, wherein the signal may pass through each serializer shift register <NUM> in series. The input serializer <NUM> may be configured to output parallel data (e.g., an x-bit serial data word) indicative of the signal. Each serializer shift register <NUM> may have a time period of a serializer clock of the input serializer <NUM>, wherein the input serializer <NUM> may take x time periods to complete output of the parallel data.

The x-bit wide shift register (e.g., input deserializer <NUM>) may be coupled to the input serializer <NUM>. The x-bit wide shift register may be configured to receive the parallel data (e.g., an x-bit serial data word) from the input serializer <NUM>. The x-bit wide shift register may be sampled at a shift register clock to provide a value with each bit shift of the value corresponding to one of the x time periods for the parallel data. A speed of the shift register clock may be less than a speed of the serializer clock. The x-bit wide shift register may have a shift register latency value indicative of an amount of time for the signal to travel from the input pad <NUM> through the x-bit wide shift register.

The FPGA <NUM> may be configured to: determine a time corresponding to in which of the x time periods the signal arrived at the input serializer <NUM> based at least on the value; and determine a time when the signal arrived at the input pad <NUM> by subtracting from the current time a sum of the shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer <NUM> based on the value. For example, the FPGA <NUM> may be further configured to determine the time corresponding to in which of the x time periods the signal arrived at the input serializer <NUM> based at least on a position of a first non-zero in the value in the case of an active high input, or position of a first zero in the case of an active low input. In some embodiments, the determined time when the signal arrived at the input pad <NUM> may be accurate to within the time period of the serializer clock of the input serializer <NUM>. Some embodiments may include a second FPGA <NUM>, wherein the second FPGA <NUM> may be configured to receive the signal and determine a time when the signal arrived at the second FPGA input pad <NUM>, wherein the FPGA <NUM> and the second FPGA <NUM> may be configured to be synchronized by utilizing the time when the signal arrived at the input pad <NUM> and the time when the signal arrived at the second FPGA input pad <NUM>. Some embodiments may include a first computing device including the FPGA <NUM> and second computing device including a second FPGA <NUM>, wherein the second FPGA <NUM> may be configured to receive the signal and determine a time when the signal arrived at the second FPGA input pad <NUM>, wherein the FPGA <NUM> and the second FPGA <NUM> may be configured to be synchronized by utilizing the time when the signal arrived at the input pad <NUM> and the time when the signal arrived at the second FPGA input pad <NUM>.

Referring now to <FIG>, an exemplary graph illustrating a function of the input deserializer <NUM> of an exemplary embodiment according to the inventive concepts disclosed herein is depicted. The input pad <NUM> may be sampled using a high-speed clock. For example, the high-speed sample clock may be set to <NUM> giving a <NUM> ns clock period, though any suitable clock may be used. For example, the deserialized output may be provided at a clock rate of <NUM>/<NUM> the input sample clock with an <NUM>-bit wide serial data word at <NUM>, though any suitable x-bit wide serial data word may be used at a clock rate of <NUM>/x of the input sample clock. For example, dealing with data at the lower clock rate may greatly ease any difficulties in meeting timing constraints on the system. While this is typically used to receive high speed data, the serial data word can also provide a precise time of arrival of the input signal at the input pad <NUM>. The timing diagram includes latency through the deserializer <NUM> processing. In this example, the delay is assumed to be <NUM> ns or one <NUM> clock. As the input is sampled at the <NUM> clock, bits may be driven high in the case of an active high input or driven low in the case of an active low input based on when the input is first seen. Depending on which bits are active in the deserialized word it can be determined when in the <NUM> clock period the input arrived. Combined with the latency of the deserializer <NUM> this can be used to give a time of arrival that is accurate to within a nanosecond of the signal's arrival.

Referring now to <FIG>, an exemplary timing diagram of an exemplary embodiment according to the inventive concepts disclosed herein is depicted. The input signal arrival time on the high-speed input clock can be inferred from the deserialized output. For example, with the <NUM>:<NUM> deserialization there may be <NUM> possible clock phases that the input signal could have arrived on.

Referring now to <FIG>, an exemplary table of an exemplary embodiment according to the inventive concepts disclosed herein is depicted. For example, assuming an active high input that is going to be active for more than <NUM> ns, the possible shift register (e.g., deserializer <NUM>) output values are listed in the table. The value to be used may be the first non-zero shift register value since all of the bits can go to steady state of logic one on the following clock. For shorter duration inputs, the values may differ but the position of the first logic <NUM> in the deserialized output may provide the time of arrival for the input signal. Values for shorter pulses are indicated as well with X signifying a value that is not required for the calculations.

Since the IO deserializers <NUM> can operate at frequencies greater than <NUM> for the sample clock the accuracy can be improved to less than <NUM> ns simply by increasing the clock speed to the maximum allowed by the particular FPGA <NUM>.

If even more accuracy is required, a delayed second clock input can be provided. The delay can be through board traces or phase shifts on the internal FPGA clocking resources. Benefits of adding additional IO may be limited since it is likely that the rise time of the signal results in ambiguities that exceed the accuracy that might be achieved with multiple IO pins.

By utilizing these IO resources in FPGAs <NUM>, two or more independent systems may be synchronized to a single source input signal with sub-nanosecond accuracies. Combined with system knowledge of the synchronization signal routing and GPS location information, other delays can also be included in the timestamping to maintain precision inter-system timing.

Referring now to <FIG>, an exemplary embodiment of a method <NUM> according to the inventive concepts disclosed herein may include one or more of the following steps. Additionally, for example, some embodiments may include performing one more instances of the method <NUM> iteratively, concurrently, and/or sequentially. Additionally, for example, at least some of the steps of the method <NUM> may be performed in parallel and/or concurrently. Additionally, in some embodiments, at least some of the steps of the method <NUM> may be performed non-sequentially.

A step <NUM> may include receiving a signal by an input pad of a field-programmable gate array (FPGA).

A step <NUM> may include receiving the signal by an input serializer of the FPGA, the input serializer comprising x serializer shift registers, wherein x is an integer greater than or equal to <NUM>, wherein the signal passes through each serializer shift register in series.

A step <NUM> may include outputting, by the input serializer, parallel data indicative of the signal, wherein each serializer shift register has a time period of a serializer clock of the input serializer, wherein the input serializer takes x time periods to complete output of the parallel data.

A step <NUM> may include receiving, by an x-bit wide shift register of the FPGA, the parallel data from the input serializer, the x-bit wide shift register communicatively coupled to the input serializer, wherein the x-bit wide shift register is sampled at a shift register clock to provide a value with each bit shift of the value corresponding to one of the x time periods for the parallel data, wherein a speed of the shift register clock is less than a speed of the serializer clock, wherein the x-bit wide shift register has a shift register latency value indicative of an amount of time for the signal to travel from the input pad through the x-bit wide shift register.

A step <NUM> may include determining, by the FPGA, a time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.

A step <NUM> may include determining, by the FPGA, a time when the signal arrived at the input pad based at least on the shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.

As will be appreciated from the above, embodiments of the inventive concepts disclosed herein may be directed to a method and a system including an FPGA configured to determine a time when a signal arrived at an input pad of the FPGA.

As used throughout and as would be appreciated by those skilled in the art, "at least one non-transitory computer-readable medium" may refer to as at least one non-transitory computer-readable medium (e.g., e.g., at least one computer-readable medium implemented as hardware; e.g., at least one non-transitory processor-readable medium, at least one memory (e.g., at least one nonvolatile memory, at least one volatile memory, or a combination thereof; e.g., at least one random-access memory, at least one flash memory, at least one read-only memory (ROM) (e.g., at least one electrically erasable programmable read-only memory (EEPROM)), at least one on-processor memory (e.g., at least one on-processor cache, at least one on-processor buffer, at least one on-processor flash memory, at least one on-processor EEPROM, or a combination thereof), or a combination thereof), at least one storage device (e.g., at least one hard-disk drive, at least one tape drive, at least one solid-state drive, at least one flash drive, at least one readable and/or writable disk of at least one optical drive configured to read from and/or write to the at least one readable and/or writable disk, or a combination thereof), or a combination thereof).

Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods, operations, and/or functionality can be rearranged while remaining within the scope of the invention which is defined by the appended claims.

Claim 1:
A system, comprising:
a field-programmable gate array, FPGA, (<NUM>) comprising:
an input pad (<NUM>) configured to receive a signal;
an input serializer (<NUM>) comprising x serializer shift registers, wherein x is an integer greater than or equal to <NUM>, wherein the input serializer is configured to receive the signal, wherein the signal passes through each serializer shift register in series, wherein the input serializer is configured to output an x-bit serial data word formed by the parallel data at the output of each serializer shift register indicative of the signal, wherein each serializer shift register shifts data at the time period of a serializer clock, wherein the input serializer takes x time periods to complete output of the x-bit serial data word; and
an x-bit wide shift register (<NUM>) communicatively coupled to the input serializer, wherein the x-bit wide shift register is an input deserializer (<NUM>), wherein the x-bit wide shift register is configured to receive the x-bit serial data word from the input serializer, wherein the x-bit wide shift register is sampled at a shift register clock to provide a value with each bit shift of the value corresponding to one of the x time periods for the x-bit serial data word, wherein a speed of the shift register clock is less than a speed of the serializer clock, wherein the x-bit wide shift register has a shift register latency value indicative of an amount of time for the signal to travel from the input pad through the x-bit wide shift register;
wherein the FPGA is configured to: determine a time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value; and determine a time when the signal arrived at the input pad based at least on the shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.