Patent Description:
Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground accurately. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation. <CIT> discloses that memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down column is disposed between the two adjacent blocks. Each source pull down column has a plurality of flash memory cells. A source of each flash memory cell in the source pull down column is coupled to sources of the flash memory cells of the plurality memory columns in a same row as the flash memory cell in the source pull down column to pull down a source of a selected flash memory cell to <NUM> V. <CIT> discloses a flash memory device including two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates.

The present invetion is set out in the appended claims.

Artificial neural networks mimic biological neural networks (e.g., the central nervous systems of animals, in particular, the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown.

<FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes the artificial neural network adaptive to inputs and capable of learning. Typically, artificial neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical artificial neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>, published as <CIT>. The non-volatile memory arrays operate as an analog neuromorphic memory. The term neuromorphic, as used herein, means circuitry that implement models of neural systems. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells arranged in this manner can be referred to as a vector by matrix multiplication (VMM) array.

Examples of different non-volatile memory cells that can be used in VMMs will now be discussed.

Various types of known non-volatile memory cells can be used in the VMM arrays. For example, <CIT> ("the '<NUM> patent") discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline terminal <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electron current will flow from the drain region <NUM> towards the source region <NUM> (source line terminal). The electrons will accelerate and become energized (heated) when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

"Read <NUM>" is a read mode in which the cell current is output on the bit line. "Read <NUM>" is a read mode in which the cell current is output on the source line terminal.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> with the addition of control gate (CG) terminal <NUM>. Control gate terminal <NUM> is biased at a high voltage, e.g., 10V, in programming, low or negative in erase, e.g., 0v/-8V, low or mid range in read, e.g., 0v/<NUM>. Other terminals are biased similarly to that of <FIG>.

<FIG> shows memory cell <NUM>, which is similar to memory cell <NUM> of <FIG> except that memory cell <NUM> does not contain an erase gate EG terminal. An erase is performed by biasing the substrate <NUM> to a high voltage and biasing the control gate CG terminal <NUM> to a low or negative voltage. Alternatively, an erase is performed by biasing word line terminal <NUM> to a positive voltage and biasing control gate terminal <NUM> to a negative voltage. Programming and reading is similar to that of <FIG>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate terminal. The erase operation (whereby erasing occurs through use of the erase gate terminal) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line terminal during a program operation to compensate for a lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except that floating gate <NUM> extends over the entire channel region <NUM>, and control gate terminal <NUM> (which here will be coupled to a word line) extends over floating gate <NUM>, separated by an insulating layer (not shown). Programming is performed using hot electron injection from channel <NUM> to floating gate <NUM> in the channel region next to the drain region <NUM>, and erasing is performed using by Fowler-Nordheim electron tunneling from floating gate <NUM> to substrate <NUM>. The read operations operate in a similar manner to that described previously for memory cell <NUM>.

"Read <NUM>" is a read mode in which the cell current is output on the bit line. "Read <NUM>" is a read mode in which the cell current is output on the source line terminal. Optionally, in arrays comprising rows and columns of memory cells <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>, source lines can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, source line terminals can be shared by adjacent rows of memory cells.

<FIG> depicts twin split-gate memory cell <NUM>. Memory cell <NUM> comprises floating gate (FG) <NUM> disposed over and insulated from the substrate <NUM>, a control gate <NUM> (CG) disposed over and insulated from the floating gate <NUM>, an erase gate <NUM> (EG) disposed adjacent to and insulated from the floating and control gates <NUM>/<NUM> and disposed over and insulated from the substrate <NUM>, where the erase gate <NUM> is created with a T shape such that a top corner of the control gate CG <NUM> faces the inside corner of the T shaped erase gate to improve erase efficiency, and a drain region <NUM> (DR) in the substrate adjacent the floating gate <NUM> (with a bit line contact <NUM> (BL) connected to the drain diffusion regions <NUM> (DR)). The memory cells are formed as pairs of memory cells (A on the left and B on the right), sharing a common erase gate <NUM>. This cell design differs from that the memory cells discussed above with reference to <FIG> at least in that it lacks a source region under the erase gate EG <NUM>, lacks a select gate (also referred to as a word line), and lacks a channel region for each memory cell <NUM>. Instead, a single continuous channel region <NUM> extends under both memory cells <NUM> (i.e. extends from the drain region <NUM> of one memory cell <NUM> to the drain region <NUM> of the other memory cell <NUM>). To read or program one memory cell <NUM>, the control gate <NUM> of the other memory cell <NUM> is raised to a sufficient voltage to turn on the underlying channel region portion via voltage coupling to the floating gate <NUM> there between (e.g. to read or program cell A, the voltage on FGB is raised via voltage coupling from CGB to turn on the channel region portion under FGB). Erasing is performed using Fowler Nordheim electron tunneling from floating gate <NUM> to erase gate <NUM>. Programming is performed using hot electron injection from channel region <NUM> to floating gate <NUM>, this is indicated as PROGRAM <NUM> in Table <NUM> below. Alternatively, programming is performed using Fowler Nordheim electron tunneling from erase gate <NUM> to floating gate <NUM>, this is indicated as PROGRAM <NUM> in Table <NUM>. Alternatively, programming is performed using Fowler Nordheim electron tunneling from channel <NUM> to floating gate <NUM>, in this case the condition is similar to PROGRAM <NUM> except the substrate <NUM> is biased at a low voltage or negative voltage while erase gate <NUM> is biased at a low positive voltage.

Table No. <NUM> depicts typical voltage ranges that can be applied to the terminals of memory cell <NUM> for performing read, erase, and program operations. Cell A (FG,CGA,BLA) is selected for read, program, and erase operation.

The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation. The methods and means described herein may apply to volatile memory technologies used for neural network such as SRAM, DRAM, and other volatile synapse cells, without limitation.

S0 is the input layer, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, where these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the layers of feature map C1. The 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

<FIG> is a block diagram of a system that can be used for that purpose. VMM system <NUM> includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in <FIG>) between one layer and the next layer. Specifically, VMM system <NUM> comprises VMM array <NUM> comprising non-volatile memory cells arranged in rows and columns, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the respective inputs for the non-volatile memory cell array <NUM>. Input to VMM array <NUM> can be from the erase gate and wordline gate decoder <NUM> or from the control gate decoder <NUM>. Source line decoder <NUM> in this example also decodes the output of VMM array <NUM>. Alternatively, bit line decoder <NUM> can decode the output of VMM array <NUM>.

VMM array <NUM> serves two purposes. First, it stores the weights that will be used by the VMM system <NUM>. Second, VMM array <NUM> effectively multiplies the inputs by the weights stored in VMM array <NUM> and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, VMM array <NUM> negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.

The output of VMM array <NUM> is supplied to a differential summer (such as a summing op-amp or a summing current mirror) <NUM>, which sums up the outputs of VMM array <NUM> to create a single value for that convolution. The differential summer <NUM> is arranged to perform summation of both positive weight and negative weight inputs to output the single value.

The summed up output values of differential summer <NUM> are then supplied to an activation function circuit <NUM>, which rectifies the output. The activation function circuit <NUM> may provide sigmoid, tanh, ReLU functions, or any other non-linear function. The rectified output values of activation function circuit <NUM> become an element of a feature map of the next layer (e.g. C1 in <FIG>) and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array <NUM> constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summer <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

The input to VMM system <NUM> in <FIG> (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, digital pulses (in which case a pulses-to-analog converter PAC may be needed to convert pulses to the appropriate input analog level) or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level (e.g., current, voltage, or charge), binary level, digital pulses, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).

The output generated by input VMM system 32a is provided as an input to the next VMM system (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level <NUM>) 32c, and so on. The various layers of VMM system <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical system comprising a respective non-volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time multiplexed for various portion of its array or neurons. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

The non-volatile reference memory cells and the non-volatile memory cells described herein are biased in weak inversion: <MAT> where w = e (- Vth)/nVt
where Ids is the drain to source current; Vg is gate voltage on the memory cell; Vth is threshold voltage of the memory cell; Vt is thermal voltage = k*T/q with k being the Boltzmann constant, T the temperature in Kelvin, and q the electronic charge; n is a slope factor = <NUM> + (Cdep/Cox) with Cdep = capacitance of the depletion layer, and Cox capacitance of the gate oxide layer; Io is the memory cell current at gate voltage equal to threshold voltage, Io is proportional to (Wt/L)*u*Cox* (n-<NUM>) * Vt<NUM> where u is carrier mobility and Wt and L are width and length, respectively, of the memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT> Here, wp is w of a reference or peripheral memory cell.

For an I-to-V log converter using a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert input current Ids, into an input voltage, Vg: <MAT>.

Here, wp is w of a reference or peripheral memory cell.

For a memory array used as a vector matrix multiplier VMM array, the output current is: <MAT> namely <MAT> <MAT> <MAT> Here, wa = w of each memory cell in the memory array. Vthp is effective threshold voltage of the peripheral memory cell and Vtha is effective threshold voltage of the main (data) memory cell. Note that threshold voltage of a transistor is a function of substrate body bias voltage and the substrate body bias can be modulated for various compensation such as over temperature or by modulating the cell current <MAT>.

Vth0 is threshold voltage with zero substrate bias, φF is surface potential, gamma is body effect parameter.

Alternatively, the non-volatile memory cells of VMM arrays described herein can be configured to operate in the linear region: <MAT> <MAT> meaning weight W in the linear region is proportional to (Vgs-Vth).

Alternatively, the memory cells of VMM arrays described herein can be configured to operate in the saturation region: <MAT> Wα (Vgs-Vth)<NUM>, meaning weight W is proportional to (Vgs-Vth)<NUM>.

Alternatively, the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.

VMM array <NUM> implements uni-directional tuning for non-volatile memory cells in memory array <NUM>. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

<FIG> depicts neuron VMM array <NUM>, which is particularly suited for memory cells <NUM> as shown in <FIG> and is utilized as the synapses and parts of neurons between an input layer and the next layer.

The input to the VMM arrays can be an analog level, a binary level, timing pulses, or digital bits and the output can be an analog level, a binary level, timing pulses, or digital bits (in this case an output ADC is needed to convert output analog level current or voltage into digital bits).

For each memory cell in a VMM array, each weight w can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of <NUM> or more cells). In the differential cell case, two memory cells are needed to implement a weight w as a differential weight (w = w+ - w-). In the two blend memory cells, two memory cells are needed to implement a weight w as an average of two cells.

One drawback of prior art arrays of non-volatile memory cells is that a relatively significant amount of time is needed to pull source lines to ground to perform a read or erase operation.

What is needed is an improved VMM system containing a source line pulldown mechanism that is able to pull a source line down to ground more expeditiously than in prior art systems.

Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation. Other embodiments contain implementations for negative and positive inputs with negative and positive weights.

In one embodiment, a non-volatile memory system comprises: an array of non-volatile memory cells arranged in rows and columns; a plurality of bit lines, each of the plurality of bit lines coupled to a column of non-volatile memory cells; and a plurality of pulldown bit lines, each of the plurality of pulldown bit lines coupled to a row of non-volatile memory cells.

In another embodiment, a non-volatile memory system comprises: an array of non-volatile memory cells arranged in rows and columns; a plurality of bit lines, each of the plurality of bit lines coupled to a column of non-volatile memory cells; and a plurality of pulldown bit lines, each of the plurality of pulldown bit lines coupled to a column of non-volatile memory cells; wherein during a read or verify operation of a selected cell, current flows through one of the plurality of bit lines into the selected cell, into multiple rows of pulldown cells and into two or more of the plurality of pulldown bit lines.

In another embodiment, a non-volatile memory system comprises: an array of non-volatile memory cells arranged in rows and columns; a plurality of bit lines, each of the plurality of bit lines coupled to a column of non-volatile memory cells; and a plurality of pulldown bit lines, each of the plurality of pulldown bit lines coupled to a column of non-volatile memory cells; wherein during a read or verify operation of a selected cell, current flows through one of the plurality of bit lines into the selected cell, into a pulldown cell adjacent to the selected cell and into one of the plurality of pulldown bit lines.

In another embodiment, a non-volatile memory system comprises: an array of non-volatile memory cells arranged in rows and columns; a plurality of bit lines, each of the plurality of bit lines coupled to a column of non-volatile memory cells; and a plurality of pulldown cells, each of the plurality of pulldown cells coupled to a source line of non-volatile memory cells.

In another embodiment, a non-volatile memory system comprises: an array of non-volatile memory cells arranged in rows and columns; a plurality of bit lines, each of the plurality of bit lines coupled to a column of non-volatile memory cells; a plurality of rows, each of the plurality of row lines coupled to a row of non-volatile memory cells; and a row receiving a negative value input.

<FIG> depicts a block diagram of VMM system <NUM>. VMM system <NUM> comprises VMM array <NUM>, row decoders <NUM>, high voltage decoders <NUM>, column decoders <NUM>, bit line drivers <NUM>, input circuit <NUM>, output circuit <NUM>, control logic <NUM>, and bias generator <NUM>. VMM system <NUM> further comprises high voltage generation block <NUM>, which comprises charge pump <NUM>, charge pump regulator <NUM>, and high voltage level generator <NUM>. VMM system <NUM> further comprises algorithm controller <NUM>, analog circuitry <NUM>, control logic <NUM>, and test control logic <NUM>. The systems and methods described below can be implemented in VMM system <NUM>.

The input circuit <NUM> may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter), AAC (analog to analog converter, such as current to voltage converter), PAC (pulse to analog level converter), or any other type of converters. The input circuit <NUM> may implement normalization, scaling functions, or arithmetic functions. The input circuit <NUM> may implement temperature compensation function for input. The input circuit <NUM> may implement activation function such as ReLU or sigmoid. The output circuit <NUM> may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as current to voltage converter), APC (analog to pulse(s) converter), or any other type of converters. The output circuit <NUM> may implement activation function such as ReLU or sigmoids. The output circuit <NUM> may implement statistic normalization, regularization, up/down scaling functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit <NUM> may implement temperature compensation function for neuron outputs or array outputs (such as bitline output) such as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.

<FIG> depicts prior art VMM system <NUM>. VMM system <NUM> comprises exemplary cells <NUM> and <NUM>, exemplary bit line switch <NUM> (which connects bit lines to sensing circuitry), exemplary dummy bit line switch <NUM> (which couples to a low level such as ground level in read ), exemplary dummy cells <NUM> and <NUM> (source line pulldown cells). Bit line switch <NUM> is coupled to a column of cells, including cells <NUM> and <NUM>, that are used to store data in VMM system <NUM>. Dummy bit line switch <NUM> is coupled to a column (bitline) of cells that are dummy cells are not used to store data in VMM system <NUM>. This dummy bitline (also known as a source line pulldown bitline) is used as source line pulldown in read, meaning it is used to pull the source line SL (e.g. SL0 and SL1) to a low level, such as a ground level, through the memory cells in the dummy bitline. Dummy bit line switch <NUM> is on the same end of the array as bit line switch <NUM>.

One drawback of VMM system <NUM> is that the input impedance for each cell varies due to the length of the electrical path through the relevant bit line switch, the cell itself, and the relevant dummy bit line switch. For example, <FIG> shows the electrical path through bit line switch <NUM>, cell <NUM>, source line SL0, dummy cell <NUM>, and dummy bit line switch <NUM>. Similarly, <FIG> shows the electrical path through bit line switch <NUM>, vertical metal bitline <NUM>, cell <NUM>, source line SL1, dummy cell <NUM>, vertical metal bitline <NUM>, and dummy bit line switch <NUM>. As can be seen, the path in <FIG> through cell <NUM> traverses a significantly larger length of bit line and dummy bit line than the path in <FIG> through cell <NUM>, and thus the path through cell <NUM> is associated with a higher capacitance and higher resistance than the path through cell <NUM>. This results in cell <NUM> having a greater parasitic impedance in the bit line or source line than cell <NUM>. This variability is a drawback, for instance, because it results in a variance in the precision of the cell output as applied to read or verify (for program/erase tuning cycles) cells depending on their location within the array.

<FIG> depicts improved VMM system <NUM> not falling under the scope of the claims. VMM system <NUM> comprises exemplary cells <NUM> and <NUM>, exemplary bit line switch <NUM> (which connects the bit lines to sensing circuitry), exemplary dummy cells <NUM> and <NUM> (which each is a pulldown cell), and exemplary dummy bit line switch <NUM> (which couples to a low level such as ground level in read). Dummy bit line switch connects to a dummy bit line that connects to dummy cells <NUM>, <NUM> used as pulldown cells). As can be seen, exemplary dummy bit line switch <NUM> and the other dummy bit line switches are located on the opposite end of the array from bit line switch <NUM> and the other bit line switches. Four columns of cells and associated dummy cells are shown, with the bit line switches labelled respectively 1903a, 1903b, 1903c, 1903d and the respective dummy bit line switches labelled 1904a, 1904b, 1904c and 1904d.

The benefit of this design can be seen in <FIG> depicts the electrical path through bit line switch <NUM>, cell <NUM>, source line SL0, dummy cell <NUM> (source line pulldown cell), vertical metal bit line <NUM>, and dummy bit line switch <NUM> (which couples to a low level such as ground level in read). <FIG> depicts the electrical path through bit line switch <NUM>, vertical metal line <NUM>, cell <NUM>, source line SL1, dummy cell <NUM> (source line pulldown cell), and dummy bit line switch <NUM>. The paths are substantially the same (cells, interconnect lengths), which is true for all cells in VMM system <NUM>. As a result, the bit line impedance plus source line impedance of each cell is substantially the same, which means that the variance in the amount of parasitic voltage drop in a read or verify operation of the various cells in the array is relatively same.

<FIG> depicts VMM system <NUM> not falling under the scope of the claims with global source line pulldown bitline. VMM system <NUM> is similar to VMM system <NUM>, except that: the dummy bit lines 2005a-2005n and 2007a-2007n are connected together (to act as global source line pulldown lines to pull memory cell source lines to ground level during read or verify), the dummy bit line switches, such as dummy bit line switch <NUM> and <NUM>, are connected or coupled to a common ground, denoted ARYGND; and the source lines are coupled together to source line switch <NUM>, which selectively pulls the source lines to ground. These changes further decrease the variance in (array) parasitic impedance among cells during read or verify operations.

<FIG> depicts VMM system <NUM> not falling under the scope of the claims. VMM system <NUM> comprises bit line switch <NUM>, dummy bit line (aka pulldown bit line) switch <NUM>, dummy bit line switch <NUM>, bit line switch <NUM>, data cell <NUM> (herein, a "data cell" is a memory cell used to store a weight value for a neural network), dummy cell (aka pulldown cell) <NUM>, dummy cell <NUM>, and data cell <NUM>. Note that the dummy cells <NUM> and <NUM> are adjacent to each together. This allows vertical metal lines BLpdx of the two dummycells <NUM> and <NUM> to be connected together (line <NUM>) to reduce parasitic resistance due to the resulting wider metal line. During a read or verify (for program/erase tuning cycles) operation of data cell <NUM>, current will flow through bit line switch <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM>, into the source line terminals of dummy cells <NUM> and <NUM>, though vertical dummy bit line <NUM>, and through dummy bit line switches <NUM> and <NUM>. During a read or verify (for program/erase tuning cycles) operation of data cell <NUM>, current will flow through bit line switch <NUM> into the bit line terminal of data cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM>, into the source line terminals of dummy cells <NUM> and <NUM>, through vertical dummy bit line <NUM>, and through dummy bit line switches <NUM> and <NUM>. This pattern of columns repeats throughout the array, where every four columns contains two columns of data cells and two adjacent array columns used for pulldown operations located between the two columns of data cells. In another embodiment, the diffusion of the two pulldown cells of the two adjacent columns can be merged together into one bigger diffusion to increase the pulldown capability. In another embodiment, the diffusion of the pulldown cell can be made to be bigger than that of the data cell diffusion to increase the pulldown capability. In another embodiment, each pulldown cell has a bias condition different than a bias condition of a selected data cell.

In one embodiment, the pulldown cell has the same physical structure as a regular data memory cell. In another embodiment, the pulldown cell has a different physical structure than a regular data memory cell, for example, the pulldown cell can be a modified version of a regular data memory cell such as by modifying one or more physical dimensions (width, length, without limitation) or electrical parameters (layer thickness, implant, without limitation). In another embodiment, the pulldown cell is a regular transistor (without a floating gate) such as an I/O or high voltage transistor.

<FIG> depicts VMM system <NUM> according to the invention. VMM system <NUM> comprises bit line <NUM>, pulldown bit line <NUM>, data cells <NUM> and <NUM>, pulldown cells <NUM> and <NUM>, and source lines <NUM>, <NUM>. During a read or verify operation of cell <NUM>, current will flow through bit line switch <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM> and into the source line terminals of pulldown cell <NUM> and through pulldown bit line BLpd <NUM> which is connected (such as through a contact) to the drain of pulldown cell <NUM>. This design is repeated for every column, with the net result that the row containing pulldown cell <NUM> is a row of pulldown cells.

During a read or verify (for program/erase tuning cycles) operation of cell <NUM>, current will flow through bit line switch <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM> and into the source line terminal of pulldown cell <NUM> and through pulldown bit line BLpd <NUM> which is connected (such as through a contact) to the drain of pulldown cell <NUM>. This design is repeated for every column, with the net result that the row containing pulldown cell <NUM> is a row of pulldown cells. As shown in <FIG>, there are four rows, the two middle adjacent rows are used for pulldown cells, the top and bottom rows are data cells.

Table No. <NUM> depicts operating voltages for VMM system <NUM>. The columns in the table indicate the voltages placed on bit lines for selected cells, pulldown bit lines, word lines WL for selected cells, control gates for selected cells, word lines WLS for selected pulldown cells, control gates CGS for selected pulldown cells, erase gates EG for all cells, and source lines SL for all cells. Note that the voltage bias for CGS and WLS in read are higher than that of the regular WL and CG biases to enhance the drive capability of the pulldown cells. The voltage biased for WLS and CGS can be negative during programming to reduce disturb.

<FIG> depicts VMM system <NUM> according to the invention. VMM system <NUM> comprises bit line <NUM>, pulldown bit line <NUM>, data cells <NUM> and <NUM>, and pulldown cells <NUM> and <NUM>. During a read or verify (for program/erase tuning cycles) operation of cell <NUM>, current will flow through bit line <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into the source line terminal of pulldown cell <NUM> (connected to source line SL0) and through pulldown bit line <NUM> which is connected to the drain terminal of pulldown cell <NUM>. This design is repeated for every column, with the net result that the row containing pulldown cell <NUM>, in a first mode, is a row of pulldown cells. During a read or verify (for program/erase tuning cycles) operation of data cell <NUM>, current will flow through bit line <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM> (connected to source line SL1), where it then flows into source line terminal of pulldown cell <NUM> and through pulldown bit line <NUM> which is connected to the drain terminal of pulldown cell <NUM>. This design is repeated for every column, with the net result that the row containing pulldown cell <NUM>, in a second mode, is a row of pulldown cells. As shown in <FIG>, there are four rows, the alternative odd (or even) rows are used for pulldown cells, the alternative even (or odd) rows are data cells.

Notably, during the second mode, cells <NUM> and <NUM> are active in read or verify and cells <NUM> and <NUM> are used for the pulldown process, with the roles of bit lines <NUM> and <NUM> being reversed compared to the first mode. In other words, the role of each row of cells can change between the first mode and the second mode, and the role of each bit line can change between the first mode and the second mode.

Table No. <NUM> depicts operating voltages for VMM system <NUM>. The columns in the table indicate the voltages placed on bit lines for selected data cells, bit lines BLOA, BLOB for selected pulldown cells, word lines WL for selected data cells, control gates CG for selected data cells, word lines WLS for selected pulldown cells, control gates CGS for selected pulldown cells, erase gates EG for all cells, and source lines SL for all cells.

<FIG> depicts VMM system <NUM> according to the invention. VMM system <NUM> comprises bit line <NUM>, pulldown bit line <NUM>, (data) cell <NUM>, source lines <NUM>, and pulldown cells <NUM>, <NUM>, and <NUM>. During a read or verify operation of cell <NUM>, current will flow through bit line <NUM> into the bit line terminal of cell <NUM> and out to the source line terminal of cell <NUM>, where it then flows into source line <NUM>, and where it then flows into the source line terminal of pulldown cells <NUM>, <NUM>, and <NUM>, from which is flows through pulldown bit line <NUM>. This design is repeated for every column, with the net result that the rows containing pulldown cells <NUM>, <NUM>, and <NUM> each are rows of pulldown cells. This maximizes the pulldown applied to the source line terminal of cell <NUM>, as current is drawn through three cells into pulldown bit line <NUM>. Note that the source lines of the four rows are connected together by vertical lines <NUM>.

Table No. <NUM> depicts operating voltages for VMM system <NUM>. The columns in the table indicate the voltages placed on bit lines BL for selected cells, pulldown bit lines BPpd, word lines WL for selected cells, control gates CG for selected cells, erase gates EG for selected cells, word lines WLS for selected pulldown cells, control gates CGS for selected pulldown cells, erase gates EGS for selected pulldown cells, and source lines SL for all cells.

<FIG> depicts an exemplary layout <NUM> for VMM system <NUM> of <FIG>. The light squares indicate metal contacts (metal to diffusion contacts) that contacts memory cell diffusions (drain region of memory cells) to metal bit lines such as bit line <NUM> (such as contacting drain diffusion of memory cell <NUM> to the bit line <NUM>) and metal pulldown bit lines such as pulldown bit line <NUM> (such as contacting drain diffusion of memory cell <NUM> to the pulldown bit line <NUM>).

<FIG> depicts an alternative layout <NUM> for a VMM system similar to the VMM system <NUM> of <FIG>, with the difference that verticalpulldown bit line <NUM> is extremely wide and traverses and connects to two columns of pulldown cells. Meaning there is one vertical pulldown line for every two bit lines for data memory cells. That is, the area for pulldown bit line <NUM> is wider than the area for bit line <NUM> of <FIG>. Layout <NUM> further shows data cell <NUM> and pulldown cell <NUM>, and source line <NUM>. In another embodiment, the diffusion of the two pulldown cells (left and right) can be merged together into one bigger diffusion area.

<FIG> depicts VMM system <NUM> not falling under the scope of the claims. To implement negative and positive weights of a neural network, half of the bit lines are designated as w+ lines (bit lines connecting to memory cells implementing positive weights), and the other half of the bit lines are designated as w- lines (bit lines connecting to memory cells implementing negative weights) and are interspersed among the w+ lines in an alternating fashion. The application of the negative operation is done at the output of the w- bit line (neuron output) by a summation circuit, such as summation circuits <NUM> and <NUM>. The output of a w+ line and the output of a w- line are combined together to give effectively w = w+ - w- for each pair of (w+, w-) cells for all pairs of (w+, w-) lines. The dummy bitlines or pulldown bitlines used respectively to avoid coupling between the floating gates of adjacent cells (FG-FG coupling) and/or reduce IR voltage drop in the source line in read are not shown in the figure. The input (such as to CG or WL) to the system <NUM> can has a positive value or a negative value. For the case where the input has a negative value, since actual input to the array is positive (such as an voltage level on CG or WL), the array output (bitline output) is made negative before output to realize the equivalent function of the negative value input.

Alternatively, with reference to <FIG>, positive weights can be implemented in a first array <NUM> and negative weights can implemented in a second array <NUM>, separate from the first array, and the resulting weights are appropriately combined together by summation circuits <NUM>. Similarly, the dummy bitlines (not shown) or pulldown bitlines (not shown) are used to respectively avoid FG-FG coupling and/or reduce IR voltage drop in the source line in read.

Alternatively, <FIG> depicts VMM system <NUM> to implement negative and positive weights of a neural network with positive or negative input. First array <NUM> implements positive value inputs with negative and positive weights in alternating columns, and second array <NUM> implements negative value inputs with negative and positive weights in respective alternating columns. The output of the second array is made negative before being added to the output of the first array by the summer <NUM>.

Table 10A shows an exemplary arrangement of a physical array arrangement of a (w+, w-) pair of bit lines BLO/<NUM> and BL2/<NUM>, where <NUM> rows are coupled to pulldown bit lines BLPWDNs. Pairs of bit lines (BLO,BL1; BL2,BL3) are used to implement (w+, w-) lines. Between the (w+, w-) line pair, there is a pulldown bit line (BLPWDN). This is used to prevent coupling (e.g., FG-FG coupling) from adjacent (w+, w-) lines into the current (w+, w-) lines. Basically, the pulldown bit line (BLPWDN) serves as physical barrier between pair of (w+, w-) lines.

Additional details regarding the FG-FG coupling phenomena, as well as mechanisms for counteracting that phenomena, are found in <CIT>, filed on February <NUM>, <NUM> by the same assignee, and titled "Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network.

Table 10B shows different exemplary weight combinations. '<NUM>' means that the cell is used and has a real output value, whereas '<NUM>' means the cell is not used and has no significant output value.

In another embodiment, dummy bit lines instead of pulldown bit lines can be used.

In another embodiment, dummy rows can also be used as physical barriers to avoid coupling between rows.

Table 11A shows another array embodiment of a physical arrangement of (w+, w-) of bitline pairs BL0/<NUM> and BL2/<NUM> with redundant lines BLO1,BL23 and pulldown bit lines BLPWDN. BLO1 is used for weight re-mapping (meaning re-distributing the weights among cells) for pair BL0/<NUM> and BL23 is used for weight re-mapping for pair BL2/<NUM>.

Table 11B shows a case of distributed weight that needs no re-mapping, basically there is no adjacent '<NUM>' between BL1 and BL3, which adjacent "<NUM>" causes adjacent bit line coupling. Table 11C shows a case of distributed weight that needs re-mapping, due to adjacent '<NUM>' between BL1 and BL2, which causes adjacent bit line coupling. This re-mapping is shown in Table 11D, resulting in no '<NUM>' value between any adjacent bit lines. Furthermore, by remapping, the '<NUM>' real value weight among the bit lines, the total current along the bit line is now reduced leading to more precise value in the bit line (output neuron). In this case, additional columns (bitline) are needed (BLO1, BL23) to act as redundant columns. Tables 11E and 11F depict another embodiments of remapping noisy cells (or defective cells) into the redundant (spare) columns such as BL01, BL23 in Table 10E or BLOB and BL1B in Table 11F. A summer is used to sum up the bit line outputs with mapping appropriately.

Table <NUM> shows an embodiment of array physical arrangement that is suitable for <FIG>. Since each array has either positive weight or negative weight, a dummy bitline acting as pulldown bitline and physical barrier to avoid FG-FG coupling is needed for each bit line.

In another embodiment, a tuning bit line is used as an adjacent bit line to a target bitline to tune the target bit line to final target by virtue of FG-FG capacitive coupling. In this case a pulldown bitline (BLPWDN) is inserted on the side of the target bit line that does not border the tuning bitline.

In another embodiment, noisy or defective cells are designated (after identifying them as noisy or defective by sensing circuitry) as non-used cells, meaning they are to be (deeply) programed to not contribute any value to the neuron output.

In another embodiment, fast cells are identified and a more precise programming algorithm is applied to these cells, such as a programming sequence using smaller or no voltage increment pulses or using a floating gate coupling algorithm.

<FIG> depicts an optional redundant array <NUM> not falling under the scope of the claims that can be included in any of the VMM arrays discussed thus far. Redundant array <NUM> can be used as redundancy to replace defective columns if any of the columns attached to bit line switches are deemed defective. The redundant array can have its own redundant neuron outputs (e.g., bit lines) and ADC circuits for redundancy purpose. In the case where the redundancy is needed, the output of redundant ADC is used to replace the output of the ADC of the bad bit line. Redundant array <NUM> can also be used for weight mapping such as described in Tables 11D, 11E, and 11F for power distribution across bit lines.

<FIG> depicts VMM system <NUM> not falling under the scope of the claims, which comprises array <NUM>, array <NUM>, column multiplexors <NUM>, top local bit lines LBL 2905a-d, bottom local bit lines LBL 2905e-h, global bit lines GBL <NUM> and <NUM>, and pulldown bit line switches <NUM>. The column multiplexors <NUM> are respectively used to select top local bit line <NUM> of the array <NUM> or bottom local bit line <NUM> of the array <NUM> into the global bit line <NUM>, <NUM>, respectively. In one embodiment, the (metal) global bit line <NUM> has the same number of lines as the number of the local bit lines, e.g. <NUM> or <NUM>. In another embodiment, the global bit line <NUM> has only one (metal) line per N number of local bit lines, such as one global bit line per <NUM> or <NUM> local bit lines. The column multiplexors <NUM> further includes multiplexing (muxing) the adjacent global bit line (such as GBL <NUM>) into the current global bit line (such as GBL <NUM>) to effectively increase the width of the current global bit line. This reduces the voltage drop across the global bit line.

<FIG> depicts VMM system <NUM> not falling under the scope of the claims. VMM system <NUM> comprises array <NUM>, (shift registers) SRs <NUM>, digital-to-analog converters <NUM> (which receives the input from the SRs <NUM> and output an equivalent (analog or pseudo-analog) level or info), summer circuits <NUM>, analog-to-digital converters (ADC) <NUM>, bit line switches (not shown), dummy bit lines (not shown), and dummy bit line switches (not shown). As shown, ADCs <NUM> can be combined together to create a single ADC with greater precision (i.e., greater number of bits).

Summer circuits <NUM> can include the circuits that are shown in <FIG>. It may include circuits for normalization, scaling, arithmetic operations, activation, or statistical rounding, without limitation.

<FIG> depicts current-to-voltage summer circuit <NUM> adjustable by a variable resistor, which comprises current sources <NUM>-<NUM>,. , <NUM>-n drawing current Ineu1,. , Ineun, respectively (which are the currents received from bit line(s) of a VMM array), of which only Ineu1 and Ineu2 are shown, operational amplifier op-amp <NUM>, variable holding capacitor <NUM>, variable resistor <NUM> and switch <NUM>. Operational amplifier <NUM> outputs a voltage, Vneuout = R3103 * (Ineu1 + Ineu2), which is proportional to the current Ineux (which is the current from a column in a VMM array). The variable holding capacitor <NUM> is used to hold the output voltage when switch <NUM> is open. This held output voltage is used, for example, to be converted into digital bits by an ADC circuit. The variability of the capacitor <NUM>, resistor <NUM> is done such as by a trim circuit (trimming the value of the capacitor or resistor) to adjust the dynamic range of the op-amp <NUM> output depending on the for example the input current range of the neuron current <NUM>.

<FIG> depicts current-to-voltage summer circuit <NUM> adjustable by a variable capacitor (basically an integrator), which comprises current source <NUM>-<NUM>,. , <NUM>-n drawing current Ineu1,. Ineun, respectively (which are the currents received from bit line(s) of a VMM array), operational amplifier <NUM>, variable capacitor <NUM>, and switch <NUM>. Operational amplifier <NUM> outputs a voltage, Vneuout = Ineu*integration time/C3203, which is proportional to the current Ineu(s).

<FIG> depicts voltage summer <NUM> adjustable by variable capacitors (i.e., a switched capacitor (SC) circuit), which comprises switches <NUM> and <NUM>, variable capacitors <NUM> and <NUM>, operational amplifier <NUM>, variable capacitor <NUM>, and switch <NUM>. When switch <NUM> is closed, input VinO is provided to operational amplifier <NUM>. When switch <NUM> is closed, input Vin1 is provided to operational amplifier <NUM>. Preferably, switches <NUM> and <NUM> are not closed at the same time. Operational amplifier <NUM> generates an output Vout, that is an amplified version of the input (either VinO and/or Vin1, depending on which switch is closed among switches <NUM> and <NUM>). That is Vout = Cin/Cout * (Vin), Cin is C3303 or C3304, Cout is C3306. For example, Vout = Cin/Cout * ∑ (Vinx), where Cin = C3303 orC3304. In one embodiment, VinO is a w+ voltage and Vin1 is a w- voltage, and voltage summer <NUM> adds them together to generate output voltage Vout.

<FIG> depicts voltage summer <NUM>, which comprises switches <NUM>, <NUM>, <NUM>, and <NUM>, variable input capacitor <NUM>, operational amplifier <NUM>, variable feedback capacitor <NUM>, and switch <NUM>. In one embodiment, VinO is a w+ voltage and Vin1 is a w-voltage, and voltage summer <NUM> adds them together to generate output voltage Vout.

For Input = VinO: when switch <NUM> and <NUM> are closed, input VinO is provided to top terminal of the capacitor <NUM>. Then switch <NUM> is open and switch <NUM> is closed to transfer the charge from the capacitor <NUM> into the feedback capacitor <NUM>. Basically, then the output VOUT = (C3358/C3356) * VinO (for case of with VREF =<NUM> as example).

For Input = Vin1: when switch <NUM> and <NUM> are closed, both terminals of the capacitor <NUM> are discharged to VREF. Then switch <NUM> is open and switch <NUM> is closed, charging the bottom terminal of the capacitor <NUM> to Vin1, which in turn charges up the feedback capacitor <NUM> to VOUT = -(C3358/C3356) * Vin1 (for case of VREF=<NUM>).

Hence, if Vin1 input is enabled after VinO input is enabled, VOUT = (C3358/C3356) * (Vin <NUM> - Vin1), for case of VREF=<NUM> as example. This is used for example to realize w = w+ - w-.

Methods of input and output operation which apply to the VMM arrays discussed above can be in digital or analog form. Methods include:.

<FIG> depict output circuits that can be used for summer circuits <NUM> and analog-to-digital converters <NUM> in <FIG>.

<FIG> depicts output circuit <NUM>, which comprises analog-to-digital converter <NUM>, which receives neuron output <NUM> and outputs output digital bits <NUM>.

<FIG> depicts output circuit <NUM>, which comprises neuron output circuit <NUM> and analog-to-digital converter <NUM>, which together receive neuron output <NUM> and generate outputs <NUM>.

<FIG> depicts output circuit <NUM>, which comprises neuron output circuit <NUM> and converter <NUM>, which together receive neuron output <NUM> and generate outputs <NUM>.

Neuron output circuit <NUM> or <NUM> can, for example, perform summing, scaling, normalization, or arithmetic operations, without limitation. Converter <NUM>, for example, can perform ADC (Analog-to-Digital Converter), PDC (Pulse-to-Digital Converter), AAC (Analog-to-Analog Converter), or APC (Analog-to-Pulse Converter) operation, without limitation.

<FIG> depicts neuron output circuit <NUM>, which comprises adjustable (scaling) current source <NUM> and adjustable (scaling) current source <NUM>, which together generate output iOUT, which is the neuron output. This circuit can perform summation of positive weight and negative weights, i.e., w = w+ - w-, i.e. Iw+ and Iw-, and up or down scaling of the output neuron current at the same time.

<FIG> depicts configurable neuron serial analog-to-digital converter <NUM>. It includes integrator <NUM> which integrates the neuron output current into the integrating capacitor <NUM>. One embodiment is that the digital output (count output) <NUM> is produced by clocking the ramping VRAMP <NUM> until the comparator <NUM> switches polarity or another embodiment is by ramping down node VC <NUM> by the ramp current <NUM> until the VOUT <NUM> reaches the value of VREF <NUM>, at which point the comparator <NUM> output EC <NUM> signal disables the counter <NUM>. The (n-bit) ADC is configurable to have lower number of bit precision <n -bits or higher number of bit precision > n -bits depending on target application. The configurability may be done by configuring the capacitor <NUM>, the current <NUM>, or ramping rate of the VRAMP <NUM>, or the clocking rate of clock <NUM>, without limitation. In another embodiment the ADC circuits of a VMM array are configured to have lower precision < n-bits and the ADC circuits of another VMM array is configured to have high precision > n-bits. Further this ADC circuit of one neuron circuit can be configured to combine with the next ADC of the next neuron circuit to produce higher n-bit ADC precision such as by combining the integrating capacitor <NUM> of two ADC circuits.

<FIG> depicts configurable neuron SAR (successive approximation register) analog-to-digital converter <NUM>. This circuit is a successive approximation converter based on charge redistribution using binary capacitors. It includes a binary CDAC (DAC basing on capacitors) <NUM>, op-amp/comparator <NUM>, SAR logic <NUM>. As shown GndV <NUM> is a low voltage reference level, for example ground level.

<FIG> depicts a configurable neuron combo SAR analog-to-digital converter <NUM>. This circuit combines two ADCs from two neuron circuits into one to achieve higher precision n-bit, for example for a <NUM>-bit ADC for one neuron circuit, this circuit can achieve > <NUM>-bit precision such as <NUM>-bit ADC precision by combining two <NUM>-bit ADCs. The combo SAR ADC circuit topology is equivalent to a split cap (bridge capacitor (cap) or attention cap) SAR ADC circuit, for example a <NUM>-bit 4C-4C SAR ADC results by combining two adjacent <NUM>-bit 4C SAR ADC circuits. A bridge circuit <NUM> is needed to accomplish this, the capacitance of capacitor of this circuit is = (total number of CDAC cap unit / total number of CDAC cap unit -<NUM>).

<FIG> depicts a configurable neuron, pipelined SAR CDAC ADC circuit <NUM> that can be used to combine with a next SAR ADC to increase the number of bits in a pipelined fashion. Residue voltage <NUM> is generated by capacitor <NUM> Cf to provide as input to next stage of pipelined ADC (e.g. to provide gain of <NUM> (ratio of Cf to C of all caps in DAC <NUM>) as input to next SAR CDAC ADC).

Additional implementation details regarding configurable output neuron (such as configurable neuron ADC) circuits can be found in <CIT> by the same assignee, and titled "Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in a Deep Learning Artificial Neural Network.

Claim 1:
A non-volatile memory system (<NUM>, <NUM>, <NUM>), comprising:
an array of non-volatile memory cells (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) arranged in rows and columns, one of the rows comprising pull down cells (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), each non-volatile memory cell comprising a bit line terminal and a source line terminal;
a plurality of bit lines (2201a, 2201b, 2201n, 2301a, 2301b, 2301n, <NUM>), each of the plurality of bit lines coupled to bit line terminals of a column of non-volatile memory cells in the array; and
a plurality of pulldown bit lines (2202a, 2202b, 2202n, 2302a, 2302b, 2302n, <NUM>) coupled to the bit line terminals of the row of pull down cells;
wherein the non-volatile memory system is configured such that during a read, verify, or erase operation of a selected non-volatile memory cell in the array, current flows: (i) through one of the plurality of bit lines into the bit line terminal of the selected non-volatile memory cell, (ii) out of the source line terminal of the selected non-volatile memory cell into a source line, (iii) into source line terminals of the pull down cells, and (iv) through bit line terminals of the pull down cells into the plurality of pulldown bit lines.