Patent Description:
In three-dimensional (3D) chip stacks, two or more semiconductor chips may be stacked on top of each other. Adjacent chips in the stack may be electrically coupled to one another via an interface. The physical design of the interface may be predetermined or fixed according to a given standard. For example, geometric dimensions of the interface, such as length, width, pad pitch, etc., may be prescribed by the standard. For example with increasing scaling in semiconductor technology, chip sizes may come close to or become even smaller than the prescribed geometric dimensions of the interface. For example, a chip may have a length that is smaller than a length of the interface as prescribed by the standard. In this case, it may be desirable to modify the chip to fit to the partly larger interface. <CIT> describes a semiconductor device having a plurality of mold-sealed semiconductor chips connected to a flip chip-mounted semiconductor chip by rewiring and an insulating layer. <CIT> describes a stack chip package using RDL and TSV to make a device thin by forming a plurality of memory chips which are laminated in the upper corner of a lower chip and reducing the thickness of the device.

A semiconductor device is provided as set out in claim <NUM>.

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects of this disclosure in which the invention may be practiced. These aspects of this disclosure are described in sufficient detail to enable those skilled in the art to practice the invention. Other aspects of this disclosure may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects of this disclosure are not necessarily mutually exclusive, as some aspects of this disclosure can be combined with one or more other aspects of this disclosure to form new aspects.

The word "over", used herein to describe forming a feature, e.g. a layer "over" a side or surface, may be used to mean that the feature, e.g. the layer, may be disposed or formed "directly on", e.g. in direct contact with, the implied side or surface. The word "over", used herein to describe forming a feature, e.g. a layer "over" a side or surface, may be used to mean that the feature, e.g. the layer, may be disposed or formed "indirectly on" the implied side or surface with one or more additional layers being arranged between the implied side or surface and the formed layer.

The terms "coupled" and/or "electrically coupled" and/or "connected" and/or "electrically connected", used herein to describe a feature being connected to at least one other implied feature, are not meant to mean that the feature and the at least one other implied feature must be directly coupled or connected together; intervening features may be provided between the feature and at least one other implied feature.

The terms "at least one" and "one or more" may be understood to include any integer number greater than or equal to one, i.e. "one", "two", three", "four", etc..

The term "a plurality of" may be understood to include any integer number greater than or equal to two, i.e. "two", "three", "four", "five", etc..

The term "standardized" as used herein may, for example, be understood as meaning "according to a standard" or "defined by a standard", for example according to or defined by a standard developed by a standardization committee, body or organization such as JEDEC (Joint Electron Device Engineering Council) or others.

In one or more aspects, the present disclosure relates to three-dimensional (3D) chip stacks such as, for example, stacks of logic and memory chips. The following description will mainly refer to logic/memory chip stacks as an example, however the present disclosure is not limited to this case and may be applied to stacking of any two or more chips in general. For example, the stacking of logic chips on logic chips; the stacking of logic chips with RF chips, analog/mixed signal chips or power chips; the stacking of chips with sensors, with micro electro mechanical systems (MEMS) or CMOS image sensors, and any other combination of 3D stacks.

Memory chips or a stack of memory chips may, for example, include or consist of dynamic random access memory (DRAM) memory chips with a 'Wide I/O (Input/Output)' interface (JEDEC standard). As will be readily understood, the present disclosure may not be limited to this particular case.

One important aspect of 3D logic/memory chip stacks with 'wide I/O' interface is the fact that the size of the logic/memory interface is fixed to <NUM> × <NUM> according to the JEDEC standard.

However, especially in mobile applications many logic chips (especially in future technology nodes beyond <NUM>) may have a chip size that may come close to or even smaller as compared to the length (<NUM>) of the 'wide I/O' standard. Therefore a cost effective solution may be needed to modify a small logic chip to fit to the partly larger 'wide I/O' interface stacked on top.

As shown in <FIG> in a cross-sectional view <NUM>, a 3D logic memory stack for e.g. mobile applications may include a logic chip <NUM> (e.g. CPU, etc.) with TSVs (through-silicon vias) <NUM> connected by a 'wide I/O interface' <NUM> to a single memory chip or a stack of memory chips <NUM>. Typically, this 3D logic/memory chip stack may be connected to a (multi-layer) ball grid array (BGA) laminate package by flip-chip connections, as shown in <FIG>. In the 3D logic memory stack shown in <FIG>, the size of the logic chip <NUM> is larger than the extension of the 'wide I/O' interface <NUM> (e.g. here with µ-bumps and TSVs).

<FIG> shows in a plan view <NUM> the standardized JEDEC 'wide I/O' logic-memory interface (LMI) <NUM> on a typical 'wide I/O' DRAM memory <NUM>. The 'wide I/O' interface <NUM> may include a high density contact grid <NUM> including a plurality of electrically conductive contacts.

Details of the 'wide I/O' interface of a typical DRAM memory, such as memory <NUM>, as defined by the JEDEC standard, include, for example:.

That is, the 'wide I/O' interface according to the JEDEC standard may have a length of <NUM> and a width of <NUM>.

If, for example, the respective size of the logic chip <NUM> in <FIG> was smaller than the length of the 'wide I/O' interface <NUM>, the interface <NUM> would no longer fit onto the logic chip <NUM>. A conventional approach to address the aforementioned issue may be to increase the chip size (here length of chip) until it is long/large enough to fit to the 'wide I/O' interface standard, as is shown in <FIG>.

<FIG> shows in a plan view <NUM> that the chip size of a small logic chip may be extended (on silicon) until it fits to the size of the 'wide I/O' interface <NUM>, wherein reference sign <NUM> denotes the logic chip having the original chip size and reference sign <NUM>' denotes the logic chip with extended chip size. As may be seen, the logic chip <NUM> having the original chip size has a length <NUM> that is shorter than a length <NUM> of the interface <NUM>, whereas the logic chip <NUM>' with extended chip size has a length <NUM> that is longer than the length <NUM> of the interface <NUM>.

The conventional approach to extend the chip size, as shown in <FIG>, may be extremely expensive, because it requires an additional 'dummy' chip area (that is, chip area which is not needed for active or passive circuitry) which may need to be manufactured in an expensive silicon wafer technology (e.g. beyond <NUM> node).

In one or more aspects, the present disclosure provides a relatively cheap (cost effective) way to increase the size (area) of the logic chip, or in general, of any first chip that shall be coupled to a second chip via an interface that is partly larger than the chip size of the first chip. For example, semiconductor devices in accordance with one or more aspects described herein may apply a relatively cheap (cost effective) fan-out WLP (wafer level package) or eWLB (embedded wafer level package ball grid array) approach to gain enough space for the interface or for the placement of one or more electrically conductive contacts (e.g. pads) connecting to the interface (e.g. logic-memory interface, e.g. 'wide I/O' interface).

An extension layer including or composed of a relatively cheap chip encapsulation material (e.g. a plastic material such as a molding material, or the like) is used to increase the chip size or area, and a redistribution layer (RDL) disposed over the extension layer is used to reroute one or more interface connections disposed outside (e.g. at least partially outside, e.g. fully outside) a boundary of the chip (in other words, outside the original chip area) to one or more electrically conductive contacts of the chip inside the boundary of the chip (inside the original chip area). The RDL may be a single level RDL or a multi-level RDL (i.e. an RDL having two or more levels or layers). A multi-level RDL may, for example, be used in cases where a relatively large number of interface interconnections lie outside the boundary of the chip (outside the original chip area).

According to one or more aspects, the present disclosure proposes for chips (e.g. logic chips) that are smaller than the extension of a standardized chip-to-chip interface (e.g. standardized logic-memory interface, e.g. 'wide I/O' memory interface according to JEDEC standard) to make use of a fan-out WLP (eWLB) chip extension with a single-level or multi-level RDL to provide the connection to the larger interface (e.g. memory interface). This approach may be significantly more cost effective (cheaper) than the conventional approach to increase the area of the chip, e.g. increase the silicon area of a highly advanced logic chip.

The eWLB RDL is able to reroute one or more interface connections (e.g. 'wide I/O' connections) to appropriate areas of the small chip, where the placement of a through-via (e.g. through-silicon via (TSV)) or an array of through-vias (e.g. TSVs) is possible.

The fan-out eWLB RDL may be disposed over one side (e.g. back side) of the chip only or, alternatively, may be disposed over both sides of the chip (i.e. over the back side and over the front side of the chip (e.g. logic chip)).

As an alternative to the through-via (e.g. TSV) connections on the chip (e.g. logic chip), all or a part of the connections may be provided by through-vias (e.g. through mold vias (TMVs)) extending through the extension layer (e.g. mold compound) in the fan-out area of the eWLB package. These through-vias (e.g. TMVs) in combination with the RDL levels are able to connect the interface contacts (e.g. 'wide I/O' pads) with the front side (active circuit area) of the small chip (e.g. logic chip) and to an interposer (e.g. laminate interposer) (if necessary even bypassing the small chip (e.g. logic chip)).

<FIG> is a plan view <NUM> of an example of a semiconductor device in accordance with one or more aspects described herein.

The semiconductor device includes a first semiconductor chip <NUM>. According to the example shown, the first semiconductor chip <NUM> may be a (small) logic chip, similar to logic chip <NUM> in <FIG>. However, the first semiconductor chip <NUM> may be another type of chip different from a logic chip, and may be any type of chip in general.

The first semiconductor chip <NUM> is to be electrically coupled to a second semiconductor chip <NUM> via a standardized chip-to-chip interface <NUM>. According to the example shown, the second semiconductor chip <NUM> may be a memory chip (e.g. a DRAM chip). Accordingly, the chip-to-chip interface <NUM> may be a logic-memory interface, e.g. a 'wide I/O' logic-memory interface, similar to interface <NUM> shown in <FIG>. However, the second semiconductor chip <NUM> may be another type of chip different from a memory chip, and may be any type of chip in general, and the interface <NUM> may be another type of interface, e.g. a different type of logic-memory interface, or a type of interface different from a logic-memory interface, and may, for example, be any type of interface having a predefined or fixed size (prescribed by some standard), which is at least partly larger than the size (area) of the first semiconductor chip <NUM>.

As shown in <FIG>, the first semiconductor chip <NUM> has a length <NUM> that is smaller than a length <NUM> of the standardized chip-to-chip interface <NUM>. For example, in case that the chip-to-chip interface <NUM> is a 'wide I/O' logic-memory interface, the length <NUM> of the first semiconductor chip <NUM> may be smaller than <NUM>. For other types of interfaces having different dimensions, the length <NUM> may be smaller than some value different from <NUM>, as will be readily understood.

Thus, as may be seen from <FIG>, a part of the chip-to-chip interface <NUM> extends laterally beyond a boundary 401a of the first semiconductor chip <NUM>. In other words, the interface <NUM> does not fully fit onto the area of the first semiconductor chip <NUM> of the semiconductor device. In particular, the interface <NUM> is longer than the chip <NUM>.

As shown, the semiconductor device further includes an extension layer <NUM> extending laterally from the boundary 401a of the first semiconductor chip <NUM>. As shown in <FIG>, the extension layer <NUM> may extend from all lateral sides of the first semiconductor chip <NUM> (in the example shown, from all four lateral sides of the chip <NUM>). That is, the extension layer <NUM> may laterally enclose the first semiconductor chip <NUM>. However, it may also be possible that the extension layer <NUM> extends only from some of the lateral sides, e.g. from one, two, or three of the four lateral sides of the first semiconductor chip <NUM>, for example from two opposite lateral sides as shown in a plan view <NUM> in <FIG> illustrating another example of a semiconductor device, or from one lateral side as shown in a plan view <NUM> in <FIG> illustrating another example of a semiconductor device.

In general, the extension layer <NUM> may be formed such that the combined area of the first semiconductor chip <NUM> and the extension layer <NUM> may be large enough to fit the size or area of the standardized chip-to-chip interface <NUM>, for example the size or area of a 'wide I/O' logic-memory interface. For example, according to the examples shown in <FIG> the extension layer <NUM> is formed such that a combined length <NUM> of the first semiconductor chip <NUM> and the extension layer <NUM> is larger than the length of the interface <NUM>.

The extension layer <NUM> may include or may be composed of a material (or materials) different from the first semiconductor chip <NUM>, for example an insulating material, for example a chip encapsulant material, e.g. a plastic material, e.g. a molding material (mold compound). For example, the molding material (mold compound) may be a composite material consisting of a resin (e.g. epoxy resin) and a filler material (e.g. fused silica).

The extension layer <NUM> may serve as a fan-out extension (fan-out region) of the first semiconductor chip <NUM> to accommodate one or more electrically conductive contacts (e.g. pads) to be coupled to one or more electrically conductive contacts (e.g. pads) of the interface <NUM> that lie outside the chip <NUM>'s boundary 401a. In other words, electrically conductive contacts of the interface <NUM> that would no longer fit onto the semiconductor chip <NUM> because of the first semiconductor chip <NUM>'s small size may now be coupled to electrically conductive contacts disposed over the extension layer <NUM>, and a redistribution layer (not shown in <FIG>, see e.g. <FIG>) used to provide electrical coupling of those contacts with the first semiconductor chip <NUM>.

In accordance with one or more aspects, a fan-out WLP (eWLB) package may be provided, which may have a single level or, if needed, a multi-level redistribution layer (RDL) with electrically conductive contacts (e.g. contact pads) in the top RDL metallization level. By this approach it becomes possible to place all necessary contacts (e.g. pads) to a standardized chip-to-chip interface (e.g. logic-memory interface, e.g. 'wide I/O' interface (of the memory chip or chip stack)) in the RDL of the chip (e.g. logic chip) either over the fan-out region or over the original chip area. On the original chip (e.g. logic chip) the non-fitting electrically conductive contacts (e.g. non-fitting 'wide I/O' pads) may be shifted or rearranged elsewhere and may be connected by the single- or multi-level RDL wiring, as described herein below with reference to <FIG>.

<FIG> is a plan view <NUM> of an example of a semiconductor device, including a redistribution layer <NUM> configured to reroute interface connections, e.g. electrically conductive contacts, <NUM> of the standardized chip-to-chip interface <NUM>, disposed outside the boundary 401a of the first semiconductor chip <NUM> to electrically conductive contacts (e.g. pads) 411a (of the first semiconductor chip <NUM>) inside the boundary 401a of the first semiconductor chip <NUM>. For example, by means of the redistribution layer <NUM> logic-memory interface connections (e.g. 'wide I/O' interface connections) on a memory chip <NUM> (or memory chip stack), e.g. a 'wide I/O' DRAM chip, not fitting on a logic chip <NUM> may be rerouted to electrically conductive contacts (e.g. pads) 411a rearranged or shifted on the logic chip <NUM>. The redistribution layer <NUM> is disposed over at least one side of the extension layer <NUM> and the first semiconductor chip <NUM>. The redistribution layer <NUM> may include or may be composed of an electrically conductive material, for example, a metal or metal alloy such as copper, aluminum, or an alloy containing copper and/or aluminum. The redistribution layer <NUM> may include one or more electrically conductive contacts (e.g. pads) to be coupled to respective electrical contacts of the chip-to-chip interface <NUM>, and may include one or more conductive traces connecting the electrically conductive contacts (e.g. pads) of the redistribution layer <NUM> to the electrically conductive contacts (e.g. pads) of the first semiconductor chip <NUM>.

Illustratively, as shown in <FIG>, not all of the electrically conductive contacts of the standardized chip-to-chip interface <NUM> fit on the original size or area of the first semiconductor chip <NUM> as, in this example, the first semiconductor chip <NUM> is shorter than the interface <NUM>. One or more electrically conductive contacts 410a of the interface <NUM> lying completely outside the boundary 401a of the first semiconductor chip <NUM> may be rerouted to one or more electrically conductive contacts 411a lying inside the boundary 401a by means of the redistribution layer <NUM>. It may also be possible to reroute one or more electrically conductive contacts 410b of the interface <NUM> that lie inside the chip boundary 401a but close to the chip boundary 401a (for example, contacts 410b having a lateral distance of less than or equal to about <NUM>, e.g. less than or equal to about <NUM>, from the chip boundary 401a) to one or more electrically conductive contacts 411a of the first semiconductor chip <NUM> that are disposed well inside the chip boundary 401a (e.g. contacts 411a having a lateral distance of greater than about <NUM>, e.g. greater than about <NUM>, from the chip boundary 401a), as shown. On the other hand, electrically conductive contacts (e.g. pads) 410c of the interface <NUM> that lie well within the boundary 401a of the first semiconductor chip <NUM> may or may not be rerouted and may be coupled to corresponding electrically conductive contacts (e.g. pads) 411b (not shown in <FIG>, see e.g. <FIG>) of the first semiconductor chip <NUM>.

<FIG> is a cross-sectional view <NUM> of a semiconductor device, which may be configured as a three-dimensional (3D) logic-memory stack.

The semiconductor device includes the first semiconductor chip <NUM>, which may be configured as a logic chip (e.g. central processing unit (CPU), graphics processing unit (GPU), application processor (AP), base band modem, micro controller, or the like), and the second semiconductor chip <NUM>, which may be configured as a memory chip, e.g. as a DRAM chip, and coupled to the first semiconductor chip <NUM> via the standardized chip-to-chip interface <NUM>, which may be a logic-memory interface (e.g. a 'wide I/O logic-memory interface). The second semiconductor chip <NUM> may be part of a chip stack <NUM>, e.g. a memory chip stack, e.g. a 'wide I/O' memory stack, e.g. a DRAM stack, including at least one additional semiconductor chip (e.g. memory chip, e.g. DRAM chip) stacked on top of the second semiconductor chip <NUM>. In the example shown in <FIG>, three additional semiconductor chips <NUM>', <NUM>", and <NUM>‴ are stacked on top of the second semiconductor chip <NUM>, resulting in a total of four chips, however the number of chips in the stack <NUM> may be different from four, e.g. two, three, five, six, seven, etc. Alternatively, only the second semiconductor chip <NUM> may be disposed over the first semiconductor chip <NUM>.

The logic-memory interface (e.g. 'wide I/O' interface) <NUM> may extend over the original logic chip size. In other words, the interface <NUM> extends beyond the (lateral) boundary 401a of the first semiconductor chip <NUM>, as shown. An extension layer <NUM> (e.g. fan-out eWLB extension) may extend laterally from the boundary 401a of the small logic chip <NUM> to increase the chip area of the logic chip <NUM>. A part of the extension layer <NUM> may be disposed between the first semiconductor chip <NUM> and the second semiconductor chip <NUM>, for example over a first side 401b of the logic chip <NUM> facing the second semiconductor chip <NUM>. The first side 401b may be a back side of the first semiconductor chip <NUM>. That is, the first semiconductor chip <NUM> may be arranged as in a typical flip chip arrangement with a second side 401c (front side or active side) of the first semiconductor chip <NUM> facing down (facing away from the interface <NUM> in this case), e.g. towards a ball grid array as shown in <FIG>.

A single-level redistribution layer (RDL) <NUM> may be disposed over the extension layer <NUM> for rerouting interface connections (e.g. 'wide I/O' connections), e.g. electrically conductive contacts (e.g. pads), <NUM> (see <FIG>) of the interface <NUM> lying outside the boundary 401a of the logic chip <NUM> to chip areas out of the drawing plane of <FIG>, e.g. to rearranged or shifted electrically conductive contacts <NUM> of the first semiconductor chip <NUM> (see <FIG>). Alternatively to a single-level RDL, a multi-level RDL may be used.

The redistribution layer <NUM>, or one or more electrically conductive contacts (e.g. pads) 409a of the redistribution layer <NUM>, may be coupled to corresponding electrically conductive contacts (e.g. pads) 411a, 411b of the first semiconductor chip <NUM> by means of one or more through-vias <NUM> (e.g. through-encapsulant vias, e.g. through-mold vias (TMVs)) in the extension layer <NUM>. The electrically conductive contact(s) 411a, 411b of the first semiconductor chip <NUM> coupled to the redistribution layer <NUM> (or to the electrically conductive contact(s) 409a of the redistribution layer <NUM>) may be disposed over the first side 401b (e.g. back side) of the first semiconductor chip <NUM> facing the second semiconductor chip <NUM>, as shown. The first semiconductor chip <NUM> may include one or more through-vias <NUM> (e.g. through-silicon vias (TSVs)) coupled to the electrically conductive contact(s) 411a, 411b disposed over the first side 401b and extending to the second side 401c (e.g. front side) of the first semiconductor chip <NUM> opposite the first side 401b.

The chips of the chip stack <NUM>, e.g. 'wide I/O' memory stack, (except for the topmost chip), i.e. the second semiconductor chip <NUM> and the additional semiconductor chips <NUM>' and <NUM>'', may also include one more through-vias <NUM> (e.g. through-silicon vias (TSVs)) extending in each case from a front side to a back side of the respective chip <NUM>, <NUM>', <NUM>'' to allow for electrical coupling between the individual chips of the chip stack <NUM> and thus to the first semiconductor chip <NUM> via the interface <NUM>.

The through-vias <NUM> through the first semiconductor chip <NUM> and the through-vias <NUM> through the chip stack <NUM> (e.g. 'wide I/O' memory stack) as well may be located underneath (or above) the respective electrically conductive contacts (e.g. pads) of the interface <NUM> (e.g. the 'wide I/O' logic/memory interface with <NUM> × <NUM> pad pitch), as shown in <FIG>.

However, the through-vias <NUM> may be located elsewhere and the connection between the electrically conductive contacts (e.g. pads) of the interface <NUM> (e.g. 'wide I/O' interface pads) and the respective through-vias <NUM> may be provided by a rerouting in the single- or multi-level RDL <NUM> of the fan-out eWLB package and/or by a back side metallization of the first semiconductor chip <NUM>. By using the rerouting capability of the RDL layers and/or the back side metallization it may be possible to put the through-vias <NUM> or through-via arrays on any arbitrary and user-defined location on the chips. In addition, by this approach much smaller through-vias (i.e. with smaller diameter) and/or smaller through-via pitches (independent of the interface pad pitch (e.g. 'wide I/O' pad pitch)) may be achieved (for example by using through-via diameters of less than <NUM> and/or through-via pitches of less than <NUM>). By this approach a significant amount of precious chip area may be saved.

As in a typical flip chip arrangement, the first semiconductor chip <NUM> (e.g. the second side, e.g. front side, 401c of the chip <NUM>) may be coupled to a (e.g. multi-level) ball grid array (BGA) package, including for example, an interposer <NUM> (e.g. a laminate interposer having one or more metallization or interconnect levels) connected to one or more electrically conductive contacts (e.g. pads) on the second side (e.g. front side) 401c of the first semiconductor chip <NUM> by means of one or more electrical connectors <NUM> (e.g. solder bumps (as shown), or metal (e.g. Cu) pillars), and a printed circuit board (PCB) <NUM> connected to the interposer <NUM> by means of one or more electrical connectors <NUM> (e.g. solder bumps, as shown).

Alternatively to the flip chip arrangement where the front side (or active side) of the first semiconductor chip <NUM> faces the ball grid array (BGA), the semiconductor chip <NUM> may also be arranged such that its front side (or active side) faces away from the BGA and towards the second semiconductor chip <NUM> or chip stack <NUM>.

In another example, a double-sided eWLB extension with single or multi-level RDL on both sides may be used. This means that an eWLB RDL may be used on the back side of the first semiconductor chip (e.g. logic chip) connecting to the standardized interface <NUM>, e.g. logic-memory interface, e.g. 'wide I/O memory interface' (as shown in <FIG>), and additionally on the chip front side to connect to an interposer <NUM>, e.g. BGA laminate, as shown in <FIG> and <FIG>.

<FIG> and <FIG>, respectively, show a cross-sectional view <NUM> and a plan view <NUM> of a semiconductor device including a redistribution layer <NUM> for rerouting interface connections (e.g. electrically conductive contacts, e.g. pads) of the standardized chip-to-chip interface <NUM>, wherein a first portion <NUM>' of the redistribution layer <NUM> is disposed over the first side (e.g. back side) 401b and a second portion <NUM>'' of the redistribution layer <NUM> is disposed over the second side (e.g. front side) 401c of the first semiconductor chip <NUM>. The extension layer <NUM> (e.g. eWLB chip extension) may laterally extend from the boundary 401a of the first semiconductor chip <NUM>, e.g. from all lateral sides of the first semiconductor chip <NUM>, as shown in <FIG>, alternatively from only some (e.g. one, two, or three) lateral sides of the first semiconductor chip <NUM>. A part of the extension layer <NUM> may be disposed over the first side 401b of the first semiconductor chip <NUM> (facing the chip-to-chip interface <NUM>), and a further part of the extension layer <NUM> may be disposed over the second side 401c of the first semiconductor chip <NUM>. The extension layer <NUM> may thus at least partially, e.g. fully, enclose the first semiconductor chip <NUM>.

As in the example of <FIG>, the semiconductor device may be configured as a three-dimensional (3D) logic-memory stack, wherein the first semiconductor chip <NUM> may be a logic chip and may be coupled (via the chip-to-chip interface <NUM>, e.g. logic-memory interface, e.g. 'wide I/O' interface) to a memory chip stack <NUM> (e.g. DRAM stack) including the second semiconductor chip <NUM> and one or more additional semiconductor chips <NUM>', <NUM>", <NUM>‴ which may be configured as memory chips (e.g. DRAM chips). Reference signs that are the same as in <FIG> may denote the same elements as there and will not described in detail again here for sake of brevity. Reference is made to the description above.

One or more electrically conductive contacts (e.g. pads) <NUM> of the standardized interface <NUM> may be rerouted via the redistribution layer <NUM>. The contacts <NUM> may include one or more contacts 410a lying at least partially outside, e.g. fully outside, the boundary 401a of the first semiconductor chip <NUM>, and may possibly also include one or more contacts 410b that lie inside the chip boundary 401a but close to the chip boundary 401a, as described above.

One or more through-vias 412c (e.g. through-encapsulant vias, e.g. through-mold vias (TMVs)) may be provided in the extension layer <NUM> to electrically couple the rerouted contacts <NUM> (e.g. contacts 410a and/or 410b) to one or more electrically conductive contacts (e.g. pads) of the first semiconductor chip <NUM> disposed over the second side (e.g. front side) 401c. To this end, the respective through-via(s) 412c may be coupled to the first portion <NUM>' of the redistribution layer <NUM> disposed over the first side 401b of the first semiconductor chip <NUM> and to the second portion <NUM>'' of the redistribution layer <NUM> disposed over the second side 401c of the first semiconductor chip <NUM>, and the second portion <NUM>'' of the redistribution layer <NUM> may further be coupled to the one or more electrically conductive contacts (e.g. pads) of the first semiconductor chip <NUM> disposed over the second side 401c of the first semiconductor chip <NUM>, for example by means of one or more through-vias 412b (e.g. through-encapsulant vias, e.g. through-mold vias (TMVs)) disposed in the part of the extension layer <NUM> that is disposed over the second side 401c of the first semiconductor chip <NUM>, i.e. between the first semiconductor chip <NUM> and the second portion <NUM>'' of the redistribution layer <NUM>. The second portion <NUM>'' of the redistribution layer <NUM> (or at least a part of the second portion <NUM>'' of the redistribution layer <NUM>) may further be coupled to the interposer <NUM>, e.g. via one or more electrical connectors <NUM> such as solder bumps (as shown) or metal pillars (e.g. Cu pillars), to provide electrical coupling of the semiconductor device to external devices.

It also be possible, that one or more of the through-vias 412c leading through the extension layer <NUM> are coupled to a part of the second portion <NUM>'' of the redistribution layer <NUM> that may be coupled to the interposer <NUM> but not to the first semiconductor chip <NUM>. For example, in the example shown <FIG>, the through-via 412c on the right-hand side of the figure is coupled to a part of the second portion <NUM>'' of the redistribution layer <NUM> that is coupled to the interposer <NUM> but not to the first semiconductor chip <NUM>, whereas the through-via 412c on the left-hand side of the figure is coupled to a part of the second portion <NUM>'' of the redistribution layer <NUM> that is coupled (by means of a through via <NUM>) to the first semiconductor chip <NUM>. Illustratively, it may be possible to lead one or more of the interface connections around the first semiconductor chip <NUM> (in other words, bypass the first semiconductor chip <NUM>) and couple them directly to the interposer <NUM> or ball grid array without making electrical contact to the first semiconductor chip <NUM>.

One or more electrically conductive contacts (e.g. pads) 410c of the interface <NUM> that lie well inside the chip boundary 401a (e.g. having a distance of greater than or equal to about <NUM>, e.g. greater than or equal to about <NUM>, from the chip boundary 401a) may be coupled to one or more electrically conductive contacts 411b of the first semiconductor chip <NUM> that are disposed over the first side (e.g. back side) 401b of the first semiconductor chip <NUM>, e.g. by means of one or more through-vias (e.g. TMVs) 412a disposed in the part of the extension layer <NUM> that is disposed over the first side (e.g. back side) 401b of the first semiconductor chip <NUM>.

Illustratively, <FIG> and <FIG> show an example of a semiconductor device wherein a standardized chip-to-chip interface <NUM> (e.g. logic-memory interface, e.g. 'wide I/O' interface) extends over the original chip size of a first semiconductor chip (e.g. logic chip) <NUM>, an extension layer <NUM> (e.g. fan-out eWLB extension) of the first semiconductor chip (e.g. (small) logic chip) <NUM> having a single-level RDL <NUM> on both sides (i.e. on a chip back side 401b connecting to the interface (e.g. 'wide I/O' interface) <NUM> and on a chip front side (e.g. over back-end-of-line (BEOL) layers) connects to an interposer (e.g. laminate interposer) <NUM> and to the first semiconductor chip (e.g. logic chip) <NUM>, and through-vias (e.g. through-mold vias (TMVs)) 412c couple electrically conductive contacts of the interface <NUM> (e.g. 'wide I/O' interface pads) via the redistribution layer <NUM> (e.g. eWLB RDL) (on back side 401b and front side 401c) with the active side (e.g. on-chip interconnect BEOL) of the chip (see left through-via 412c in <FIG>) or directly with the interposer (e.g. laminate interposer) <NUM> bypassing the first semiconductor chip (e.g. logic chip) <NUM> (see right through-via 412c in <FIG>).

The examples described herein above in connection with the figures mainly discuss the case that only one lateral dimension (e.g. the length) of the first semiconductor chip is smaller than the respective dimension of the standardized chip-to-chip interface. However, as will be readily understood, one or more aspects described herein may equally apply to the case where more than one lateral dimension of the first semiconductor chip (e.g. length and width) is smaller than the respective dimension of the standardized chip-to-chip interface. For example, if both a length and a width of the first semiconductor chip are smaller than a respective length and width of the standardized interface the extension layer (e.g. eWLB fan-out region) may be configured to increase the original chip area such that the interface fits onto the chip having the extension.

Claim 1:
A semiconductor device, comprising:
a first semiconductor chip (<NUM>);
a second semiconductor chip (<NUM>), wherein the first semiconductor chip (<NUM>) has at least one contact to be electrically coupled to the second semiconductor chip (<NUM>) having an interface (<NUM>) with standardized geometric dimensions, and wherein the second semiconductor chip (<NUM>) is electrically coupled to the first semiconductor chip (<NUM>) via the interface (<NUM>);
an extension layer (<NUM>) extending laterally from a boundary (401a) of the first semiconductor chip (<NUM>), wherein a combined lateral dimension of the first semiconductor chip (<NUM>) and the extension layer (<NUM>) along the at least one direction is greater than or equal to the lateral dimension of the interface (<NUM>) along the at least one direction; and
a redistribution layer (<NUM>) disposed over at least one side of the extension layer (<NUM>) and the first semiconductor chip (<NUM>), wherein the redistribution layer (<NUM>) is configured to electrically couple at least one contact of the first semiconductor chip (<NUM>) to at least one contact of the interface (<NUM>), characterized in that:
at least a part of the interface (<NUM>) extends laterally beyond the boundary (401a) of the first semiconductor chip (<NUM>); and
a lateral dimension (<NUM>) of the first semiconductor chip (<NUM>) along at least one direction is smaller than a lateral dimension (<NUM>) of the interface (<NUM>) along the at least one direction.