Patent Description:
Devices for determining the distance to objects are known. One currently used method is called "Time of Flight" (ToF). This method comprises sending a light signal towards the object and measuring the time taken by the signal to travel to the object and back. The calculation of the time taken by the signal for this travel may be obtained by measuring the phase shift between the signal coming out of the light source and the signal reflected from the object and detected by a light sensor. Knowing this phase shift and the speed of light enables the determination of the distance to the object.

Single photon avalanche diodes (SPAD) may be used as a detector of reflected light. In general an array of SPADs are provided as a sensor in order to detect a reflected light pulse. A photon may generate a carrier in the SPAD through the photo electric effect. The photo generated carrier may trigger an avalanche current in one or more of the SPADs in an SPAD array. The avalanche current may signal an event, namely that a photon of light has been detected.

<FIG> illustrates the general principle of a "Time of Flight" method.

In <FIG>, a generator <NUM> (shown as box PULSE in <FIG>) provides a periodic electric signal (for example, square-shaped). This signal powers a light source <NUM>. An example of a light source <NUM> may be a light-emitting diode, or any known lighting device, for example, a laser diode. The signal coming out of light source <NUM> is transmitted towards an object <NUM> and is reflected by this object. The reflected light signal is detected by a light sensor (shown as box CAPT in <FIG>) <NUM>. The signal on sensor <NUM>, is thus phase-shifted from the signal provided by the generator for an ideal system by a time period proportional to twice the distance to object <NUM> (in practice there is also electrical to optical delay time from the light source). Calculation block <NUM> (shown as box DIFF in <FIG>) receives the signals generated by generator <NUM> and by sensor <NUM> and calculates the phase shift between these signals to obtain the distance to object <NUM>. SPADs have the advantage of picosecond time resolution so are ideal for the detector of a compact time of flight pixel.

<FIG> are timing diagrams illustrating the operation of a circuit such as that in <FIG>. <FIG> illustrates a transmitted periodic signal "PULSE" capable of being provided by the generator <NUM> of <FIG>. <FIG> illustrates the signal CAPT received by a photo-diode based sensor <NUM>. Due to interactions with the outside and to the components forming sensor <NUM>, the signal received by this sensor has, in this example, variations in the form of capacitor charges and discharges. The signal on sensor <NUM> is phase-shifted from the signal coming out of generator <NUM> by a delay D.

The sensor <NUM> may integrate one or several photo detection elements enabling the detection of the signal received after reflection from the object <NUM>. Such elements may be rapid charge transfer photodiodes. Single-photon avalanche diodes, or "SPADs", also called Geiger mode avalanche photodiodes, may also be used. These devices have a reverse biased p-n junction in which a photo-generated carrier can trigger an avalanche current due to an impact ionization mechanism. SPADs may be designed to operate with a reverse bias voltage well above the breakdown voltage.

SPADs may be operated as follows. At an initial time, the diode is biased to a voltage greater than its breakdown voltage. The reception of a photon in the diode junction area starts a current avalanche in the diode, which creates an electric voltage pulse on the anode. The diode is then biased back to the voltage greater than the breakdown voltage, so that the SPAD reacts again to the reception of a photon. SPADs can currently be used in cycles having reactivation periods shorter than <NUM> ns. Thereby, SPADs can be used at high frequency to detect objects at relatively short distances from the measurement device, for example, distances ranging from a few centimetres to a few tens of centimetres. In different embodiments, different ranges may be supported.

Digital counter devices intended for histogram comparison, associated with SPAD sensors, are known. However, such devices are relatively complex to implement and require a significant amount of silicon to implement and thus reduce the potential density of pixels in the silicon sensor. Thus typically the SPAD sensor is a 'few pixels' sensor which has a poor lateral (X-Y dimension) resolution but fine distance (Z dimension) resolution.

The use of high density pixel (or 'many pixel') sensors comprising photodiodes which can transfer charge on several nodes according to the phase of the signal transmitted by the reference generator is also known. These sensors however typically have a slow response time and thus are produce a poor quality distance resolution but has a good quality lateral resolution.

There further is a need for apparatus and methods for sensors which produce both fine quality lateral and distance resolution which overcomes the disadvantages of known devices.

<CIT> discloses that a camera includes a proximity detector capable of detecting a gesture such as movement of a user's hand, finger or thumb. The detection is used to control camera functions such as image capture, focusing, exposure level control and mode selection.

<CIT> discloses an arrangement for measuring the distance to an object, comprising: a photonic source for illuminating said object using a continuous modulated photonic wave, a solid-state image sensor, comprising an array of avalanche photodiodes and a plurality of circuits for processing signals output by said avalanche photodiodes to yield data depending on the photonic wave reflected by said object onto said photodiodes.

Some embodiments will now be described by way of example only and with reference to the accompanying Figures in which:.

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.

Reference is now made to <FIG> which shows a block diagram of a few-pixel many-bin histogram generating time-of-flight range detector arrangement. <FIG> represents a conventional arrangement. To measure the time of flight at a resolution below a clock period, a flash time to digital converter (TDC) is typically used. This typically comprises a multiple-phase timing generator and front end sampling elements. There are two input TDC channels, one input for reception of SPAD pulses (i.e. pulses generated by a SPAD on detection of a photon) and the other input for illumination device pulses (i.e. pulses generated by the system coincident with emission of an illumination pulse). The TDC converts the time difference between a received SPAD event and the multiple clock phase timing generator.

The system shown in <FIG> comprises a timing generator <NUM>. The timing generator generates a timing signal which may be used to control a light source (and furthermore be used as a reference clock signal). The timing generator <NUM> may be configured to generate suitable timing pulses.

The system may furthermore comprise a light source <NUM>. The light source <NUM> may comprise any suitable fast light source, for example a vertical cavity surface emitting laser (VCSEL), a light emitting diode (LED), etc. The light source <NUM> may receive signals from the timing generator and be configured to generate light based on the signals. For example the light source <NUM> may be configured to receive timing signal pulses from the timing generator <NUM> and generate pulses of light which are emitted externally (and in some embodiments internally via an internal parasitic path not shown directly to a reference SPAD array <NUM>).

The system may further comprise a detector. In the example shown in <FIG>, the detector may comprise a first or reference SPAD array <NUM> and a second or return SPAD array <NUM>. The return SPAD array <NUM> may configured to detect light reflected back from the object <NUM> whereas the reference SPAD array <NUM> may be configured to detect light passed via the internal parasitic path only. The output of the SPAD arrays (the reference SPAD array <NUM> and the return SPAD array <NUM>) may be coupled to front end electronics (FE electronics) <NUM>.

An example of the SPAD array <NUM> architecture is further shown in <FIG>. In this example the SPAD array <NUM> comprises an array of pixels, of which one pixel <NUM> is shown in further detail.

Each pixel <NUM> may as shown in <FIG> comprise a single photon avalanche diode with quench and reset components <NUM>. The output of the pixel single photon avalanche diode <NUM> may be passed to a pulse shaper.

The system comprises a pulse shaper <NUM> per pixel, which receives the input SPAD pulse from each pixel and performs pulse shaping on the signal. The pulse shaper may be configured to shorten the pulse length and reduce the effect of pileup distortion in the OR tree network, for a given SPAD count rate. The pulse output from the SPAD array may be greater than 10ns in length. The longer the period or length of pulses entering the input of an OR tree (used in the histogram generator), the more likely it is for two or more SPAD outputs to be high together. One SPAD array output being high has the same effect at the output as two or more SPAD array outputs being high. In both cases the output of the OR tree sits high. Accordingly, timing information can be lost as output pulses increase in length. This effect is sometimes referred to as pile up distortion. The pulse shaping circuitry is used to overcome this. The output of the pulse shaper may be passed to the OR tree.

Although not shown in detail the reference SPAD array <NUM> may be similarly arranged.

As shown in <FIG> each pixel is configured to output to the OR tree <NUM>, which receives the output from each pixel pulse shaper <NUM> and logical 'OR's the inputs to generate a pulse output. The output of the OR tree <NUM> and therefore the return SPAD array <NUM> may be passed to the Front End (FE) time-to-distance (TDC) electronics <NUM>.

The FE TDC electronics <NUM> may be configured to receive signals from the timing generator <NUM>, the reference SPAD array <NUM> and the return SPAD array <NUM> and pass these signals to a histogram generator <NUM>.

The system in some embodiments comprises a histogram generator <NUM>. The histogram generator <NUM> measures the time of flight of the illumination pulse over the return journey from light source <NUM> to object <NUM> and back to the return SPAD array <NUM>. The histogram generator <NUM> in this type of arrangement may comprise clocked counters which output a large number of bins each of which comprise the number of detected events for a clocked period.

Reference is now made to <FIG> which shows a flow chart illustrating the method steps associated with the function of a conventional SPAD arrangement such as the one shown in <FIG>.

At step <NUM>, a plurality of events are determined and a time at which each event occurred is recorded.

At step <NUM>, a histogram may be generated from the event information. Typically, the histogram may be generated during the detection period and based on all the time and event information for the detection period. Typically, the histogram is generated by the histogram generator. An illustrative example of such a histogram is shown in <FIG>.

Thus for example <FIG> shows an example histogram where the Y-axis <NUM> shows the number of events for each histogram bin <NUM>. <FIG>, for example, shows at time t<NUM> a first peak <NUM> corresponding to a first detected event, at time t<NUM> a second peak <NUM> corresponding to a second detected event, and at a time t<NUM> a third peak <NUM> corresponding to a third detected event. In this example the first peak <NUM> may correspond to the internal parasitic path event detection, the second peak <NUM> the external object detection and the third peak a further distant reflected object detection.

At step <NUM>, the time of the first peak <NUM> t<NUM>, the second peak <NUM> t<NUM> and the third peak <NUM> t<NUM> may be used to determine a time taken for light to travel to and from the respective remote objects.

A drawback of the architecture described above with reference to <FIG> and <FIG> is that the histogram generator circuitry configured to output multiple bin histograms requires a large amount of implementation physical space. As a histogram is required for each of the arrays (or pixels) the number of detector pixels (or arrays) which may be implemented on a suitable silicon device is therefore limited. Hence most practical implementations are typically only able to output a few pixels. Thus, although such devices are able to provide fine resolution in the Z dimension (in other words the plane perpendicular to the sensor), they offer coarse resolution in the X-Y plane (the plane parallel to the sensor).

Reference is now made to <FIG> which shows a further example detector architecture 'many-pixel few-bin' conventional implementation. The example shows where the complexity of the circuitry is reduced to enable an increase in the density of pixels. In this example the sensor comprises a photodiode <NUM>. The photodiode <NUM> may be reversely biased close to a breakdown voltage. Once the photodiode is triggered by few photons, a current may be generated. The photodiode <NUM> is connected to a pass circuit comprising several transistors, 515a, 515b, 515c and 515d, configured in a pass transistor configuration. Each transistor is clocked by at least one clock which is passed to a delay line and the taps from which are used to activate each transistor such that one terminal is connected to the photodiode and the other is connected to a charge collection region or 'bin' 520a, 520b, 520c and 520d respectively. The advantage of this example detector is that the reduction in complexity is such that the amount of silicon required per pixel is low and therefore a higher resolution can be achieved. However, the use of pass gate logic is disadvantageous because it introduces an inherent delay to the system which significantly limits the maximum frequency of the transmitted illumination. This results in a slow system which cannot take full advantage of the speed offered by the SPAD diodes and is more limited by any differences between pass-gate transistor to pass-gate transistor. Hence the example implementation although suitable for producing a fine resolution in the X-Y dimension (due to the number of pixels), they offer limited resolution in the Z plane and furthermore limited resolution in the time domain.

There are certain applications for which a high degree of accuracy in distance measurements, without any loss of accuracy in the X-Y plane domain, is required. An example of these applications include gesture recognition. An example representation of a gesture recognition device is schematically shown in <FIG> shows for example an electronic device <NUM> with display, suitable for implementing a '3D mouse' application where the user's hand or other object is monitored and used to provide an input for the device. For example in such an application the device may be configured to detect objects (for example a finger of a hand) located over the device and the motion of the object (shown as the finger moving from the right to the left to attempt a 'swipe' gesture) is detected and used to control the device. In such applications not only is it not necessary to contact the device to enable the user input but the distance from the device (Z-distance) may itself be detected and any change in the Z-distance be used to determine a suitable input to the device. For example a single point zoom effect input may be determined based on the 'input' object distance from the device where the closer the object to the device the higher the zoom magnification and vice versa.

In other words the recognition of some gestures requires knowledge of not only x-y co-ordinates (as per optical mouse techniques), but also an array of z coordinates. Examples of this are diagonal gestures where there is motion or displacement of the object being detected in the x-y co-ordinates and the z distance. Other examples are circular gestures such as looping with a hand, turning a hand over or more complex gestures such as detecting a turning dial gesture. In all of these the change in z distance is to be detected.

Thus in order to be able to produce effective 3D gesture recognition an object detection sensor is required to have both a fine spatial resolution (X-Y axes) <NUM> that is high enough for gesture recognition in two-dimensions, whilst also being able to accurately resolve in the Z axis <NUM>. For example the device is required to distinguish between a motion of the 'target' object (within a height range <NUM>) and a different object detected at a different height. In other words being able to be quick enough both to provide a high enough frame rate and to obtain the required precision in the Z axis. Furthermore by providing a device with a good Z axis resolution three dimension gesture detection can be implemented accurately.

By way of example, an optical mouse typically uses a 20x20 two-dimensional array of detectors operated at approximately 1000fps to detect movement direction and speed.

With respect to <FIG> an example arrangement for both the few-pixel many-bin detector described above and the many-pixel few-bin detector according to some embodiments are shown. The left hand side of <FIG> shows the few-pixel many-bin detector. As can be seen, conventional architectures <NUM> use an array of SPADs which are divided into sub-arrays of SPADs. In this example the array of SPADs is divided into four sub-arrays 710a, 710b, 710c, 710d to achieve the required resolution. Each sub-array of SPADs 710a, 710b, 710c, 710d is associated with its own histogram logic 720a, 720b, 720c, 720d. As discussed previously this is not a practical solution as the silicon area required for this histogram logic is relatively large, thus the resulting circuits would require large areas of silicon and would be inefficient, expensive and difficult to make with a high yield.

By contrast the right hand side of <FIG> shows an example of the proposed solution according to the invention. In this system the SPAD array <NUM> is divided into macro pixels <NUM> which comprise smaller sub-arrays of SPADs. In the example system <NUM> each macro pixel 740a, 740b, 740c, 740d, 740e is depicted by a bold square. The macro pixels are further shown on the right hand of <FIG> wherein each macro pixel comprises a sub-array <NUM> of SPADs and associated sub-array of SPADs TDC component <NUM>, which may comprise an OR tree, pulse shaper and 'few-bin' histogram generator. In some embodiments the example TDC component <NUM> and the 'few-bin' histogram generator is physically located on the integrated circuit adjacent the SPAD sub-array <NUM>. In some embodiments the 'few-bin' histogram generator <NUM> is physically located adjacent to the SPAD sub-array <NUM> in the X or Y plane of the device (in other words within the same silicon layers as the SPAD detectors) or in the Z plane (in other words in different silicon layers as the SPAD detectors).

Reference is now made to <FIG> which shows a block diagram of a time-of-flight range determining device in accordance with some embodiments of the invention.

The ToF range determining device comprises a timing generator <NUM>'. The timing generator <NUM>' is configured to control the timing of a light source <NUM>' and furthermore in some embodiments to generate a known waveform for controlling the light source <NUM>'. The following examples are described where the timing generator <NUM>' is configured to generate a sine wave at a determined frequency f. In some other embodiments the known waveform may be any arbitrary waveform, for example a pulse wave, triangle wave, square wave, saw tooth wave or other.

The ToF range determining device comprises a light source <NUM>'. The light source <NUM>' may comprise any suitable fast switching light source, for example a vertical cavity surface emitting laser (VCSEL), a light emitting diode (LED), etc. The light source <NUM>' for example may be configured to emit light which is amplitude modulated at a sine wave at the frequency f and time controlled by the timing generator <NUM>'. The light is then reflected back from an object <NUM>'.

The ToF range determining device further comprises a first or reference SPAD array <NUM>' and a second or return SPAD array <NUM>'. The return SPAD array <NUM>' may configured to detect light reflected back from the object <NUM>' whereas the reference SPAD array <NUM>' may be configured to detect light passed via the internal parasitic path only. The output of the SPAD arrays (the reference SPAD array <NUM>' and the return SPAD array <NUM>') may be coupled to histogram processor <NUM>.

An example of the SPAD array <NUM>' architecture and an example configuration of a macro pixel <NUM> is further shown in <FIG>. In this example the SPAD array <NUM>' comprises an array of macro pixels <NUM>. Each macro pixel <NUM> is shown comprising a NxN SPAD pixel arrangement of which one pixel <NUM>' is shown in further detail and which outputs to the OR Tree <NUM>'.

Each pixel arrangement <NUM>' as shown in <FIG> may comprise a single photon avalanche diode with quench and reset components <NUM>'. The output of the pixel single photon avalanche diode <NUM>' (with quench and reset components) may be passed to a pulse shaper <NUM>'. Each pixel arrangement <NUM>' may further comprise a pulse shaper <NUM>', which receives the SPAD pulse from each pixel and performs pulse shaping on the signal. The pulse shaper may, as described previously, be configured to shorten the pulse length and reduce the effect of pileup distortion in the OR tree network, for a given SPAD count rate. The output of the pulse shaper <NUM>' may be passed to the OR tree <NUM>'.

The SPAD pixel arrangement <NUM>' is configured to receive the reflected sine wave from the object <NUM>' and generate detected event signal pulses.

The macro pixel <NUM> may further comprise an OR tree <NUM>', which is configured to receive the output from each pixel pulse shaper <NUM>' for the macro pixel <NUM> and logical 'OR' the inputs to generate a pulse output. The output of the OR tree <NUM>' and therefore the detected reflected sine wave may be passed to the Front End (FE) time-to-distance (TDC) electronics <NUM>.

The macro pixel <NUM> may further comprise FE TDC electronics <NUM> configured to receive signals from the timing generator <NUM> and the OR tree <NUM> and pass these signals to a 'few-bin' histogram generator <NUM>.

The macro pixel <NUM> may further comprise a 'few-bin' histogram generator <NUM>, configured to receive the output of the FE TDC electronics <NUM> and output a histogram. The histogram generator <NUM> is configured to generate a histogram comprising a small number of bins. For example, by way of non-limiting examples, the histogram generator <NUM> described hereafter is configured to generate <NUM> bins or <NUM> bins. However it is understood that in some embodiments more than <NUM> bins may be generated. These histogram bin values may be passed to a histogram processor <NUM>.

Although not shown in detail the reference SPAD array <NUM>' may be similarly arranged.

The ToF range determining device further comprises a histogram processor <NUM>. The histogram processor <NUM> may be configured to receive the output of the histogram generator <NUM> from each macro pixel <NUM> of the Return SPAD array <NUM>' and the output of the Reference SPAD array <NUM>'. The histogram processor <NUM> may be configured to regenerate from the determined 'few-bin' histogram data a reconstructed sinewave. This reconstructed sinewave may then be compared with the sine waveform from the timing generator <NUM>' and a phase difference between the two waveforms may be determined. From this phase difference (between the timing generator <NUM>' sine wave and the reconstructed sinewave an estimate of the range may be determined.

In some embodiments the timing generator <NUM>' may be configured to generate further (and different) frequency waveforms. For example in some embodiments the timing generator <NUM>' may be configured to generate a sine wave of frequency f-δf and a sine wave of frequency f+δf and from these be able to calculate two further range determinations. From these further range determinations and the knowledge of the frequencies an unambiguous range (which does not have any potential wrap-round error) may then be output.

Reference is now made to <FIG> which shows a more detailed view of a building block for components of the histogram generator <NUM> (or a histogram generator cell <NUM>') as shown in <FIG>. As discussed with reference to <FIG>, the histogram generator <NUM> is configured to receive the combination of SPAD pixels which are shaped, logical OR'ed and then timed based on the timing generator clock signals. Each generator cell <NUM>' is configured to generate a bin output for the histogram generator <NUM>. Thus a three bin histogram generator may comprise three histogram cells <NUM>', a four bin histogram generator may comprise four histogram cells <NUM>' and so on.

The histogram generator <NUM> thus comprises an input <NUM> receiving the processed SPAD pixel signals. The input <NUM> is passed to a delay cell <NUM> and to a clock sampling flop cell <NUM>.

The histogram generator <NUM> may comprise a delay module <NUM>. The delay module <NUM> may be configured to receive the input <NUM> and delay the input signal sufficiently such that a delayed version of the input signal may be used to 'clock' a gated edge detector cell <NUM>.

Each histogram generator cell <NUM>' comprises a clock sampling flop cell <NUM>. The clock sampling flop cell <NUM> is configured to sample the clock signal using as a clock as the input <NUM> (from the pulse shaper or OR tree). The clock sampling flop cell <NUM> is shown in <FIG> as comprising a single D-latch <NUM> (D-flop) which has a data input coupled to one of the phase clock input signals Cx and a clock input coupled to the input <NUM>. The phase clock input signal may be one of three (or four or more) depending on the number of bins generated by the histogram generator. Each neighbouring phase clock is configured to overlap the previous and next phase clock. Thus for example in a four bin histogram generator there are four phase clocks C<NUM>, C<NUM>, C<NUM>, C<NUM>, each of which overlaps the previous clock by <NUM>/<NUM> of a cycle and thus C<NUM> is substantially the inverse of C<NUM> and C<NUM> is substantially the inverse of C<NUM>. The output of the D-latch <NUM> is output to a gated edge detector cell <NUM>. Thus an output from the cell is generated where on the rising edge of an SPAD event pulse the phase clock signal is positive.

The histogram generator cell further comprises a gated edge detector (or transition detector) cell <NUM>. The gated edge detector cell <NUM> may comprise an inverter <NUM> which receives the output of the clock sampling flop cell <NUM> and outputs the inverted clock sampling flop cell signal <NUM> to an AND gate for a previous clock phase gated edge detector cell. The gated edge detector cell <NUM> further comprises an AND gate <NUM> which is configured to receive the next clock phase gated edge detector cell invertor signal <NUM>, the current phase clock sampling flop cell signal <NUM>, and the delay module output signal as a clock input signal <NUM>. The AND gate <NUM> may generate an output <NUM> which is passed to a phase rotator multiplexer <NUM>. In this way, the gated edge detector cell outputs a high state only when a SPAD event is detected between overlapping phase clock signals and therefore is defined only by positive edge triggering. An advantage of this type of edge detection is that only one type of logic is used to define the time periods, namely either PMOS or NMOS gate, making the definition of the time periods more consistent.

The histogram generator cell <NUM>' further comprises a phase rotator multiplexer cell <NUM>. The phase rotator multiplexer cell <NUM> comprises a network <NUM> which receives the output of the current phase clock gated edge detector cell <NUM> and the output of every other phase clock gated edge detector cell and a multiplexer <NUM> which is configured to receive as inputs the network <NUM> (and therefore the current phase clock gated edge detector cell <NUM> and every other phase clock gated edge detector cell) and a selector input <NUM>. The selector input <NUM> thus selects one of the current phase clock gated edge detector cell or other phase clock gated edge detector cell signals to be output by the multiplexer <NUM> to a phase bin ripple counter <NUM>.

The histogram generator cell <NUM>' further comprises a phase bin (Bin X) ripple counter <NUM>. The ripple counter <NUM> is shown receiving as an input the output from the multiplexer <NUM> and is configured to count the events detected.

With respect to <FIG> and <FIG> examples of the three and a four bin histogram generators are shown comprising the histogram generator cell <NUM>' as shown in <FIG>.

<FIG> shows a three bin histogram generator <NUM> which comprises three phases (or rows) of the histogram generator cell <NUM>' such as shown in <FIG>. The histogram generator <NUM> may thus comprise an input <NUM>. The input <NUM> may be passed to a delay cell <NUM> and to a <NUM> phase clock sampling flop <NUM>'.

The three bin histogram generator <NUM>' may comprise a delay module <NUM>. The delay module <NUM> may be configured to receive the input <NUM> signal and delay the signal sufficiently such that a delayed version of the input signal may be used to 'clock' a three phase gated edge detector <NUM>'.

The three bin histogram generator <NUM> further comprises three clock sampling flop cells to form a three phase clock sampling flop <NUM>'. The phase clock input signals are three overlapping phase clocks C<NUM>, C<NUM>, C<NUM>. The output of the three phase clock sampling flop <NUM>' is output to a three phase clock edge detector cell <NUM>'.

The three bin histogram generator <NUM> further comprises three clock gated edge detector (or transition detector) cells to form a three phase clock gated edge detector <NUM>'. The three phase clock gated edge detector <NUM>' may output to the three phase multiplexer <NUM>'.

The three bin histogram generator <NUM> further comprises three rotation multiplexer cells to form a three phase clock rotation multiplexer <NUM>'. The three phase rotation multiplexer <NUM>' is configured to output one of the three clock gated edge detector cell outputs to one of the three bin ripple counters <NUM><NUM>', <NUM><NUM>', <NUM><NUM>'. The three bin histogram generator <NUM> further shows a phase rotator/selector <NUM>' configured to control the switching of the multiplexing.

The histogram generator cell further comprises three bin ripple counters <NUM><NUM>', <NUM><NUM>', <NUM><NUM>' configured to count the events detected for each of the clock phases.

<FIG> shows a four bin histogram generator <NUM> which comprises four phases (or rows) of the histogram generator cell such as shown in <FIG>. The histogram generator <NUM> may thus comprise an input <NUM>. The input <NUM> may be passed to a delay cell <NUM> and to a four phase clock sampling flop <NUM>".

The four bin histogram generator <NUM> may comprise a delay module <NUM>. The delay module <NUM> may be configured to receive the input <NUM> signal and delay this sufficiently such that a delayed version of the input signal may be used to 'clock' or activate a four phase gated edge detector <NUM>'.

The four bin histogram generator <NUM> further comprises four clock sampling flop cells to form a four phase clock sampling flop <NUM>". The phase clock input signals are four overlapping phase clocks C<NUM>, C<NUM>, C<NUM>, C<NUM>. The output of the four phase clock sampling flop <NUM>" is output to a four phase clock edge detector cell <NUM>". This for example is shown in <FIG> where an example four overlapping phase clocks C<NUM>, C<NUM>, C<NUM>, C<NUM> are shown being used as data inputs for the four phase clock sampling flop <NUM>".

The four bin histogram generator <NUM> further comprises four clock gated edge detector (or transition detector) cells to form a four phase clock gated edge detector <NUM>". The four phase clock gated edge detector <NUM>" may output to the four phase multiplexer <NUM>".

The four bin histogram generator <NUM> further comprises four phase rotation multiplexer cells to form a four phase rotation multiplexer <NUM>". The four phase rotation multiplexer <NUM>" is configured to output one of the four clock gated edge detector cell outputs to one of the four bin ripple counters <NUM><NUM>", <NUM><NUM>", <NUM><NUM>", <NUM><NUM>". The four bin histogram generator <NUM>" further shows a phase rotator/selector <NUM>" configured to control the switching of the multiplexing. The concept behind the four phase rotation multiplexer <NUM>" is shown in further detail in <FIG>.

The first part A of <FIG> shows a first phase rotation setting whereby the phase rotator/selector <NUM>" is configured to couple the output of the first edge detector cell (defined by the period between C1 rising and C2 rising) to the first ripple counter, the second edge detector cell (defined by the period between C2 rising and C3 rising) to the second ripple counter, the third edge detector cell (defined by the period between C3 rising and C4 rising) to the third ripple counter and the fourth edge detector cell (defined by the period between C4 rising and C1 rising) to the fourth ripple counter. However as shown in <FIG> part A not all of the periods are the same and thus for example the second phase, the phase marked <NUM>, is shown to be slightly bigger than the other phases. This may cause errors as the probability of detecting an event is greater during the second phase. The solution to any phase clock inconsistency is to found in the application of the phase rotator multiplexer <NUM>. The phase rotator multiplexer <NUM> and shown in <FIG> with respect to the four phase rotator multiplexer is to repeat the histogram generation starting with a different clock phase and as such when all of the clock phases have been rotated for a whole cycle then any inconsistency is averaged out.

Thus for example <FIG> part B shows a second phase rotation setting wherein the phase rotator/selector <NUM>" is configured to 'start' the light source cycle starting at the second phase and thus couple the output of the first edge detector cell (defined by the period between C1 rising and C2 rising) to the fourth ripple counter, the second edge detector cell (defined by the period between C2 rising and C3 rising) to the first ripple counter, the third edge detector cell (defined by the period between C3 rising and C4 rising) to the second ripple counter and the fourth edge detector cell (defined by the period between C4 rising and C1 rising) to the third ripple counter.

A further rotation to a third phase rotation setting is shown in <FIG> part C wherein the phase rotator/selector <NUM>" is configured to 'start' the light source cycle starting at the third phase and thus couple the output of the first edge detector cell (defined by the period between C1 rising and C2 rising) to the third ripple counter, the second edge detector cell (defined by the period between C2 rising and C3 rising) to the fourth ripple counter, the third edge detector cell (defined by the period between C3 rising and C4 rising) to the first ripple counter and the fourth edge detector cell (defined by the period between C4 rising and C1 rising) to the second ripple counter.

The final rotation, the fourth phase rotation setting, is shown in <FIG> part D. The phase rotator/selector <NUM>" is configured to 'start' the light source cycle starting at the fourth phase and thus couple the output of the first edge detector cell (defined by the period between C1 rising and C2 rising) to the second ripple counter, the second edge detector cell (defined by the period between C2 rising and C3 rising) to the third ripple counter, the third edge detector cell (defined by the period between C3 rising and C4 rising) to the second ripple counter and the fourth edge detector cell (defined by the period between C4 rising and C1 rising) to the first ripple counter.

Turning to <FIG> a schematic illustration of an example embodiment of the delay module <NUM> is shown. The pulse shaper circuit <NUM> is shown to have an input from the SPAD array and an output <NUM> that feeds into the delay module <NUM>, as discussed with reference to <FIG> above. The delay module <NUM> effectively comprises two delay elements, <NUM> and <NUM>, which introduce time delays, TD2 and TD3 respectively. The pulse shaper <NUM> is also annotated with "TD1". As will be discussed below, with reference to the timing diagram of <FIG>, TD1 indicates the length of the pulse created by the pulse shaper circuit.

The significance of these time periods TD1, TD2, and TD3 are shown in the timing diagram of <FIG>, which illustrates the operation of the delay module <NUM>. The signal output <NUM> of the pulse shaper is shown in the uppermost diagram. The signal is shown to have a length in time of TD<NUM>. It is noted that the change in state (from low to high) for the output signal <NUM> of the pulse shaper is not instantaneous. Rather, as illustrated there is a finite rise time between t<NUM> and t<NUM>.

The "sample flops" diagram directly below the pulse diagram indicates the activation of a sampling module <NUM>. It is noted that, as can be seen in the sample flop diagram, the sampling elements also do not change state instantaneously. However, the time required for the change of state of a sampling flop (t<NUM>-t<NUM>) is smaller than the time required for the change in state of the output signal <NUM>, (t<NUM>-t<NUM>).

There is an implemented time delay TD2 introduced by the first delay element <NUM> of the delay module <NUM>, which represents the time required for a pulse <NUM> to be 'reach' the edge detector module <NUM> (or in other words for a pulse to pass through the clock sampling flops and therefore the difference in time between an initial sampling time <NUM> and the logic settling time <NUM>).

A further implemented time delay TD3 is defined from the time <NUM> from which the gated edge detector is 'enabled' to enable any pulse to settle within the gated edge detector <NUM> and thus any pulse generated by the pulse shaper is able to be clocked out of the gate edge detector to the phase rotation multiplexer <NUM> within the time safety margin <NUM> defined from the end of the delay TD3 and the PS pulse time.

<FIG> show various example implementations of the arrangements of four bin histogram generators which may differ from the implementations such as described in <FIG>, <FIG> and <FIG>.

With respect to the example implementation in <FIG> a first alternative example four bin histogram generator 180A is shown.

The histogram generator 180A may thus comprise an input 900A. The input 900A may be passed to a delay cell 905A and to a clock sampling flop 910A.

The histogram generator 180A may comprise a delay module 905A. The delay module 905A may be configured to receive the output of the shaper circuit <NUM> and delay these inputs sufficiently such that a delayed version of the input may be used to 'clock' the output of the phase rotator multiplexers 950A. Thus the delay module 905A is configured to generate a delay which enables the detected events to pass through the clock sampling flops 910A, the edge detector decoder 920A and the phase rotator multiplexers 950A. The delay module 905A is shown in <FIG> comprising an inverter 1305A configured to receive the input 900A. As such the delay module 905A uses the dead time of the SPAD or the OR tree as the delay time as the falling edge of the SPAD event or the OR tree network output may be used as the rising edge to clock the clock gating stage 1301A and therefore increment the counters.

In the example shown in <FIG> the clock sampling flops 910A are configured to sample the four phase clock signals using the input 900A from the pulse shaper. The clock sampling flops 910A are shown as four D-latches 915Aa, 915Ab, 915Ac and 915Ad which has a data input coupled to one of the phase clock input signals C<NUM>, C<NUM>, C<NUM>, C<NUM> and a clock input coupled to the input 900A. The output of each D-latch 915Aa, 915Ab, 915Ac and 915Ad is output to the edge detector 920A. Thus an output from the cell is generated where on the rising edge of an SPAD event pulse the phase clock signal is positive.

The histogram generator 180A further comprises an edge detector (or transition detector) 920A. The edge detector 920A may be configured to identify or determine whether the event was detected between which pair of positive or rising phase clock edges. A difference between the edge detector 920A as shown in <FIG> and the edge detector <NUM> shown in <FIG> is that the edge detector 920A does not receive an output from the gating delay cell 905A. Based on the determination of between which pair of positive or rising phase clock edges the event was detected the edge detector 920A is configured to output on one of the four edge interval outputs to a phase rotator multiplexer 950A.

The histogram generator 180A further comprises a phase rotation multiplexer 950A. The phase rotation multiplexer 950A may be similar to the phase rotation multiplexers described above in that it comprises a network which receives the outputs from the edge detector 920A. The multiplexer 950A may further comprise multiplexers configured to receive signals from the network and a selector input and thus selects one of the edge detector outputs to be output by the multiplexer to a clock gating stage 1301A.

The histogram generator 180A further comprises a clock gating stage 1301A which comprises a series of D-latches 1300Aa, 1300Ab, 1300Ac, 1300Ad each of which receives, as a data input, an output from the phase rotation multiplexer 950A and, as a clock input, the output from the delay module 905A and outputs the clock gated phase rotated samples to phase bin ripple counters 955Aa, 955Ab, 955Ac, 955Ad.

The histogram generator 180A further comprises phase bin ripple counters 955Aa, 955Ab, 955Ac, 955Ad. The ripple counters 955Aa, 955Ab, 955Ac, 955Ad are shown receiving, as an input, the outputs from the clock gating stage 1301A and is configured to count the events detected for each bin.

With respect to the example implementation in <FIG> a further alternative example four bin histogram generator 180B is shown. The main difference between the histogram generator 180B as shown in <FIG> and the histogram generator 180A shown in <FIG> is that the functionality of the clock gating stage functionality is implemented within the ripple counters 955B.

The histogram generator 180B may thus comprise an input 900A. The input 900A may be passed to a delay cell 905A and to a clock sampling flop 910A.

The histogram generator may comprise a delay module 905A which may be implemented as an inverter 1305A and function as described previously.

The histogram generator may further comprise clock sampling flops 910A configured to sample the four phase clock signals using the input 900A from the pulse shaper. As described above the output of each D-latch 915Aa, 915Ab, 915Ac and 915Ad is output to the edge detector 920A. Thus an output from the cell is generated where on the rising edge of an SPAD event pulse the phase clock signal is positive.

The histogram generator 180B further comprises an edge detector (or transition detector) 920A which performs the same functionality as the edge detector of <FIG> as described above.

The histogram generator 180A further comprises a phase rotation multiplexer 950A which performs the same functionality as phase rotation multiplexer 950A of <FIG> as described above. However rather than selecting one of the edge detector outputs to be output by the multiplexer to a clock gating stage 1301A the output is passed to a ripple counter 955Ba, 955Bb, 955Bc, 955Bd.

The histogram generator 180B further comprises phase bin ripple counters 955Ba, 955Bb, 955Bc, 955Bd. The ripple counters 955Ba, 955Bb, 955Bc, 955Bd are shown receiving, as a clock input the output from the delay stage 905A and as an increment enable input the outputs from the phase rotation multiplexer 950A and is configured to count the events detected for each bin. Each bin ripple counter 955Ba, 955Bb, 955Bc, 955Bd comprises a flop <NUM> which is the first bit of the ripple counter and which receives as the clock input the counter 'incr' input (the output of the phase rotator multiplexer 950A) and as a data input the output of a multiplexer <NUM>. Furthermore the bin ripple counter comprises a multiplexer <NUM> which receives as a first input the positive output from the flop <NUM>, a second input the output of the multiplexer <NUM> and a selection input of 'increment enable' signal from the output of the delay 905A. The output of the flop <NUM> may furthermore be passed to the further bits of the ripple counter module. Combined with the multiplexer <NUM>, this example shows an implementation of a ripple counter that can be enabled or disabled by changing the select input "increment enable" on the multiplexer <NUM>. The output of the rotation multiplexer 950A connects to the clock input of the flop <NUM> (marked 'incr').

With respect to the example implementation in <FIG> a further alternative four bin histogram generator 180C is shown. The main difference between the histogram generator 180C as shown in <FIG> and the histogram generators 180A, 180B shown in <FIG> and <FIG> is that the edge detector 920A, 920B is a gated edge detector 920C and thus the functionality of the clock gating stage functionality is implemented within the edge detector. Furthermore <FIG> shows an alternative delay cell 905C which comprises a pair of delay elements <NUM> and <NUM> and an inverter <NUM> to generate the delay time implicitly using the delay time of the SPAD pulse (if no pulse shaper is used) or the pulse shaper pulse. The delay time is produced from using the negative edge of a pulse coming through the OR tree. The pulse shapers connected as inputs to the OR tree provide this delay "for free", the inverter is used to convert the negative edge to a positive edge. The output of the delay cell 905C furthermore is passed to the gated edge detector 920C as the clock input.

The histogram generator 180C furthermore comprises a flop 1400C which is configured to receive the input 900A from the SPAD pixels as a clock input and has a data input which is set high and thus outputs a high value when an event is output from the SPAD. The positive output from the flop 1400C is sent as the input for the clock sampling flops 910A and to the delay cell 905C. The flop 1400C furthermore comprises a reset input which receives the output from the delay cell 905C and as such each detected event creates a pulse with a width defined by the delay cell time delay. In other words the flop 1400C and the <NUM> delay cells function as the pulse shaper or "pulse extender". The flop latches high, then the delay cells are activated which reset the flop providing a guaranteed high time of the pulse (to latch the clock sampling flops) and a guaranteed low time (to reset the flop 1400C).

The histogram generator 180C may further comprise clock sampling flops 910A configured to sample the four phase clock signals using the output from the flop 1400C. As described above the output of each D-latch 915Aa, 915Ab, 915Ac and 915Ad is output to a gated edge detector 920C. Thus an output from the cell is generated where on the rising edge of an SPAD event pulse, the phase clock signal is positive and the preceding phase clock signal is negative.

The histogram generator 180C further comprises a gated edge detector (or transition detector) 920C which performs the same functionality as the edge detector 920A of <FIG> as described above but is gated by the output of the delay cell 905C. In other words the gated edge detector 920C is similar to the gated edge detector described in <FIG>.

The histogram generator 180C further comprises a phase rotation multiplexer 950A which performs the same functionality as phase rotation multiplexer 950A of <FIG> and <FIG> as described above. However rather than selecting one of the gated edge detector outputs to be output by the multiplexer to a clock gating stage the output is passed to a ripple counter 955Aa, 955Ab, 955Ac, 955Ad.

The histogram generator 180C further comprises phase bin ripple counters 955Aa, 955Ab, 955Ac, 955Ad. The ripple counters 955Aa, 955Ab, 955Ac, 955Ad are shown receiving the outputs from the phase rotation multiplexer 950A and are configured to count the events detected for each bin.

<FIG> shows a further alternative example of a four bin histogram generator 180D. The main difference between the histogram generator 180D as shown in <FIG> and the histogram generator 180C shown in <FIG> is that the resettable flop 1400C is not implemented in this example. Thus <FIG> shows the alternative delay cell 905C which comprises a pair of delay elements <NUM> and <NUM> and an inverter <NUM> to generate the delay time. The output of the delay cell 905C furthermore is passed to the gated edge detector 920C as the clock input.

The histogram generator 180D furthermore is configured to receive the input 900A from the pulse shaper and which is sent as the input for the clock sampling flops 910A and to the delay cell 905C.

The histogram generator 180D may further comprise clock sampling flops 910A configured to sample the four phase clock signals using the input signal 900A. As described above the output of each D-latch is output to a gated edge detector 920C. Thus an output from the cell is generated where on the rising edge of an SPAD event pulse, the phase clock signal is positive and the preceding phase clock signal is negative.

The histogram generator 180D further comprises a gated edge detector (or transition detector) 920C which performs the same functionality as the edge detector 920A of <FIG> as described above but is gated by the output of the delay cell 905C. In other words the gated edge detector 920C is similar to the gated edge detector described in <FIG>.

The histogram generator 180D further comprises a phase rotation multiplexer 950A which performs the same functionality as phase rotation multiplexer 950A of <FIG> and <FIG> as described above. However rather than selecting one of the gated edge detector outputs to be output by the multiplexer to a clock gating stage the output is passed to a ripple counter 955Aa, 955Ab, 955Ac, 955Ad.

The histogram generator 180D further comprises phase bin ripple counters 955Aa, 955Ab, 955Ac, 955Ad. The ripple counters 955Aa, 955Ab, 955Ac, 955Ad are shown receiving the outputs from the phase rotation multiplexer 950A and are configured to count the events detected for each bin.

With respect to <FIG> an example of a histogram processor <NUM> is shown in further detail. In some embodiments the histogram processor <NUM> comprises a signal or waveform regenerator <NUM>, which receives the bin count values and maps the values to an expected waveform. For example in some embodiments where the timing generator <NUM>' is configured to generate a sine wave to modulate the light source <NUM>' then the signal regenerator <NUM> is configured to receive the three (or four or other number) bin values and map these to a sine wave. This regenerated waveform may then be passed to a phase comparator/range determiner <NUM>.

The histogram processor <NUM> may further comprise a phase comparator/range determiner <NUM> which receives the regenerated waveform and compares the regenerated waveform against the original waveform to determine a phase difference and from this comparison determine the time and range distance.

With respect to <FIG> an example <NUM> and <NUM> bin calculation is shown. The <NUM> bin example has bin values A, B, C, and D and the range value, Time of flight intensity <NUM>, and Baseline <NUM> may be determined by <MAT> <MAT> <MAT>.

The <NUM> bin example has bin values A, B, and C and the range value, Time of flight intensity <NUM>, and Baseline <NUM> may be determined by <MAT> <MAT> <MAT> <MAT>.

However the phase comparator/range determination may be performed using any suitable method such as look up tables.

Using a single waveform frequency may, in some circumstances, provide an ambiguous range result because of range overlap. This for example occurs because more than one range value may be mapped to a phase difference value. To overcome this ambiguous range value in some embodiments the timing generator may perform a range determination for more than one frequency waveform.

<FIG> for example shows an example wherein a first frequency integration (histogram determination) <NUM> is performed for a first frequency, then a second frequency integration (histogram determination) <NUM> is performed for a second frequency and finally in the cycle a third frequency integration (histogram determination) <NUM> is performed for a third frequency. The cycle may then be repeated as shown in <FIG> by a further first frequency integration <NUM> following the third frequency integration <NUM>.

Following the end of the first frequency integration <NUM>, the histogram values may be read out to memory and the pixel counters (ripple counters) reset. Furthermore the histogram values used to calculate the phase of the first frequency histogram values (in other words the phase difference for the first frequency) <NUM>. Following the end of the second frequency integration <NUM>, the histogram values may also be read out to memory and the pixel counters (ripple counters) reset. Furthermore the histogram values used to calculate the phase of the second frequency histogram values (in other words the phase difference for the second frequency) <NUM>. Following the end of the third frequency integration <NUM>, the histogram values may also be read out to memory and the pixel counters (ripple counters) reset. Furthermore the histogram values used to calculate the phase of the third frequency histogram values (in other words the phase difference for the third frequency) <NUM>.

Having determined phase values for all three frequencies these may then be used to determine an unambiguous range value <NUM>.

<FIG> furthermore shows a three frequency example where within each frequency a phase rotation operation is visible. For example a first frequency integration (histogram determination) <NUM> is performed for a first frequency, but within the first frequency integration is a first phase <NUM><NUM>, a second phase <NUM><NUM>, a third phase <NUM><NUM>, and a fourth phase <NUM><NUM>, then a second frequency integration (histogram determination) <NUM> is performed for a second frequency, but within the second frequency integration is a first phase, a second phase, a third phase, and a fourth phase, and finally in the cycle a third frequency integration (histogram determination) <NUM> is performed for a third frequency but within the third frequency integration is a first phase, a second phase, a third phase, and a fourth phase. The cycle may then be repeated as shown in <FIG> by a further first frequency integration <NUM> following the third frequency integration <NUM>.

Following the end of the first frequency integration <NUM>, the histogram values may be read out to memory and the pixel counters (ripple counters) reset. Furthermore the histogram values may be used to calculate the phase of the first frequency histogram values (in other words the phase difference for the first frequency) <NUM>. Following the end of the second frequency integration <NUM>, the histogram values may also be read out to memory and the pixel counters (ripple counters) reset. Furthermore the histogram values may be used to calculate the phase of the second frequency histogram values (in other words the phase difference for the second frequency) <NUM>. Following the end of the third frequency integration <NUM>, the histogram values may also be read out to memory and the pixel counters (ripple counters) reset. Furthermore the histogram values may be used to calculate the phase of the third frequency histogram values (in other words the phase difference for the third frequency) <NUM>.

Turning to <FIG>, a flowchart summarising the process implemented within the range detector in accordance with some of the previously described embodiments is shown. The flowchart does not completely correspond to the claimed invention.

At step <NUM>, the SPAD array generates detection pulses which are based on the object range and the waveform.

At step <NUM>, the Front end electronics gather the detection pulses and pass them to a pulse shaper.

At step <NUM>, the pulse shaper performs pulse shaping and passes the pulses to the few bin histogram generator to generate the histogram bins.

At step <NUM>, the histogram generator generates the few histogram bins.

At step <NUM>, the histogram processor reconstructs a waveform and determines the phase (difference) of the reconstructed waveform.

At step <NUM>, the histogram processor then furthermore determines a range based on the phase (difference).

Some embodiments may use other sensors, instead of SPADs.

It should be appreciated that the above described arrangements may be implemented at least partially by an integrated circuit, a chip set, one or more dies packaged together or in different packages, discrete circuitry or any combination of these options.

Claim 1:
A method for determining a distance from an apparatus to at least one object comprising:
generating (<NUM>) a first signal;
generating light modulated by the first signal from the apparatus;
detecting (<NUM>) light reflected by the at least one object using a Time-of-flight detector array, by determining (<NUM>, <NUM>, <NUM>) by each array element of the Time-of-flight detector array an output signal generated from a series of photon counts over a number of consecutive non-overlapping time periods, wherein the determining (<NUM>, <NUM>, <NUM>), by each array element, comprises:
sampling a determined number of overlapping clock signals using a photon detection output from the array element, wherein the sampling generates a determined number of sampling outputs;
generating a determined number of non-overlapping time periods count increment detections based on consecutive sampling outputs;
phase rotating the first signal and phase rotating the determined number of non-overlapping time periods count increment detections, in parallel, to generate a phase rotated determined number of non-overlapping time periods count increment detections; wherein the determined numbers are equal; and
incrementing the series of photon counts from the phase rotated determined number of non-overlapping time periods count increment detections to generate the output signal;
the method further comprising:
comparing (<NUM>) the output signals to the first signal to determine at least one signal phase difference; and
determining (<NUM>) a distance from the apparatus to the at least one object based on the at least one signal phase difference.