Patent Description:
Modern radar systems routinely need to be tested and calibrated under controlled conditions. One type of radar test system, known as a radar return simulator or a target generator, generates simulated return signals that a radar might receive in the field and applies the simulated signals to the radar in order to test the radar's performance. Conventional radar return simulators are typically very hardware intensive. In order to simulate a single radar return, a conventional radar return simulator requires radio frequency (RF) hardware to generate or receive a radar transmit waveform, mix the transmit signal with an appropriate Doppler frequency, and add an appropriate delay. When simulating multiple radar return, each return is typically generated separately, so each added return needs additional RF hardware. As a result, a conventional radar return simulator can become very large and expensive when multiple returns need to be simulated.

<NPL>, discusses coherent radar scene stimulators for use in the development and testing cycles of an embedded radar system. They provide a means of injecting controlled, high fidelity scenes into a radar under test. This capability allows for robust software testing, evaluation of bus and processor usage in realistic scenarios, validation of radar system requirements, and operator training platforms. By designing a scene stimulator to interface transparently with a radar signal processor, the radar may be evaluated with no test constraints. Coupled with a means to extract data from a radar signal processor, radar-in-the-loop type automated performance testing is possible such as verifying probability of detection/false alarm or image quality metrics.

This disclosure provides a real-time closed-loop digital radar simulator.

In a first aspect, a method comprising: receiving radar parameters from a unit under test, UUT; generating multiple tasks based on the radar parameters; sending the tasks and the radar parameters to multiple graphics processing units, GPUs; generating, using the GPUs, a simulated radar return for the UUT based on the tasks, the radar parameters, and a three-dimensional model of a scene, the simulated radar return comprising digital signals; controlling a timing of output of the simulated radar return to the UUT using multiple field programmable gate array, FPGA, carriers, the FPGA carriers associated with different ones of the GPUs; converting the digital signals into analog signals using multiple digital-to-analog converters, DACs; and transmitting the analog signals to the UUT.

In a second aspect, an apparatus comprising: multiple graphics processing units, GPUs; at least one processing device configured to: receive radar parameters from a unit under test, UUT; generate multiple tasks based on the radar parameters; and send the tasks and the radar parameters to the GPUs, wherein the GPUs are configured to generate a simulated radar return for the UUT based on the tasks, the radar parameters, and a three-dimensional model of a scene, the simulated radar return comprising digital signals; multiple field programmable gate array, FPGA, carriers configured to control a timing of output of the simulated radar return to the UUT, the FPGA carriers associated with different ones of the GPUs; and multiple digital-to-analog converters, DACs, configured to convert the digital signals into analog signals and transmit the analog signals to the UUT.

In a third aspect, a system comprising: a unit under test, UUT, the UUT comprising at least a portion of a radar system; multiple graphics processing units, GPUs; at least one processing device configured to; receive radar parameters from the UUT; generate multiple tasks based on the radar parameters; and send the tasks and the radar parameters to the GPUs, wherein the GPUs are configured to generate a simulated radar return for the UUT based on the tasks, the radar parameters, and a three-dimensional model of a scene, the simulated radar return comprising digital signals; multiple field programmable gate array, FPGA, carriers configured to control a timing of output of the simulated radar return to the UUT, the FPGA carriers associated with different ones of the GPUs; and multiple digital-to-analog converters, DACs, configured to convert the digital signals into analog signals and transmit the analog signals to the UUT.

<FIG>, described below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any type of suitably arranged device or system.

For simplicity and clarity, some features and components are not explicitly shown in every figure, including those illustrated in connection with other figures. It will be understood that all features illustrated in the figures may be employed in any of the embodiments described. Omission of a feature or component from a particular figure is for purposes of simplicity and clarity, and is not meant to imply that the feature or component cannot be employed in the embodiments described in connection with that figure. It will be understood that embodiments of this disclosure may include any one, more than one, or all of the features described here. Also, embodiments of this disclosure may additionally or alternatively include other features not listed here.

As noted above, modem radar systems routinely need to be tested and calibrated under controlled conditions, and one type of radar test system is known as a radar return simulator. Often times, a conventional radar return simulator receives an analog signal from a unit under test (UUT), which typically includes at least part of a radar, and manipulates the signal in the analog domain in order to present a simulated representation of a scene back to the UUT. For example, the manipulated signal can be fed back to a receiver of the UUT in order to simulate the received signals. Many conventional radar return simulators, such as computer in the loop (CIL) radar simulators, use specialized analog equipment to synthesize radar scatter returns. Unfortunately, the expense and complexity of designing, building, calibrating, and maintaining the specialized analog equipment is often prohibitive. The equipment and cost per scatterer is very linear, which limits the number of scatterers that can be practically generated (often to no more than approximately ten scatterers). In addition, many of these systems do not feature enough fidelity to accurately test modem radar systems. Previous attempts at replacing analog electronics with real-time digital-based simulations have been hampered by processing time and data throughput latencies or still rely on analog methods to control characteristics like delays, phases, and Doppler frequencies.

This disclosure provides various techniques for supporting real-time closed-loop digital radar simulations. As described in more detail below, the disclosed embodiments are capable of digitally synthesizing radar returns for radar simulations without the need for complicated or numerous analog components. Using the disclosed embodiments, the cost, size, and complexity of closed-loop radar system testing can be reduced substantially, while performance can be greatly improved (such as by a factor of one hundred or more) at the same time. Note that while the disclosed embodiments may be described below in conjunction with a radar system used in defense-related applications, other applications are within the scope of this disclosure.

<FIG> illustrates an example system <NUM> for performing a real-time closed-loop digital radar simulation according to this disclosure. As shown in <FIG>, the system <NUM> includes a unit under test (UUT) <NUM>, a radar timing interface field programmable gate array (FPGA) <NUM>, multiple processing devices 104a-104b, multiple digital-to-analog converters (DACs) 106a-<NUM>, multiple FPGA carriers 108a-108b, and multiple graphics processing units (GPUs) 110a-110f.

The system <NUM> generally operates here to calculate radar returns in a timeframe that is short enough so that a digitally-synthesized closed-loop simulation can be performed in real-time. The number of generated radar returns that may be produced by the system <NUM> in <FIG> may be limited only by the number and performance of the GPUs 110a-110f and how much time is given by the system requirements. Thus, the system <NUM> is scalable for testing of simple to highly-complex radar scenes. The calculations and functions performed within the system <NUM> are distributed across the components of the system <NUM> according to the capabilities of each component so as to optimize the performance of the system <NUM> as a whole. For example, as discussed in greater detail below, the processing devices 104a-104b can be used to perform non-timing critical calculations, the GPUs 110a-110f can be used to perform timing and precision critical math, and the FPGA carriers 108a-108b can be used to perform calculations and functions best suited to streaming data.

The UUT <NUM> represents a radar system or a device that includes a radar system (such as a missile system) that is undergoing testing using the system <NUM>. In some embodiments, the UUT <NUM> may represent a ground-based radar system that is installed in a fixed position on land or on a ground vehicle. In other embodiments, the UUT <NUM> may represent a radar system disposed in or on an aircraft, spacecraft, or other flight vehicle (such as a missile or drone). In the specific example shown in <FIG>, the UUT <NUM> represents an eight-channel radar system, although this is merely for illustration only. Other numbers of channels are possible (such as a six-channel radar system) and within the scope of this disclosure.

The radar timing interface FPGA <NUM> is configured to be coupled to the UUT <NUM>, such as via one or more cables or other suitable physical or wireless interface. The radar timing interface FPGA <NUM> generally operates to collect radar parameters from the UUT <NUM>, such as radar waveform information and timing information. The radar parameters are used by the system <NUM> to understand the type and timing of radar signals that are to be tested, which allows the system <NUM> to then generate suitable radar return information. After receiving the radar parameters from the UUT <NUM>, the radar timing interface FPGA <NUM> provides the radar parameters to the processing devices 104a-104b and also generates a trigger enabling the system <NUM> to provide radar returns to the UUT <NUM> with precise timing.

Each processing device 104a-104b generally operates to receive the radar parameters from the UUT <NUM> and process the radar parameters. Based on the radar parameters, the processing devices 104a-104b generate tasks associated with the creation of the radar parameters. Once the tasks are generated, the processing devices 104a-104b send the tasks and the radar parameters to the GPUs 110a-110f for processing. Each processing device 104a-104b represents any suitable structure configured to receive and process radar parameters and generate tasks. Example types of processing devices 104a-104b include microprocessors, microcontrollers, digital signal processors (DSPs), application specific integrated circuits (ASICs), or discrete circuitry. In some embodiments, the processing devices 104a-104b represent commercial-off-the-shelf (COTS) central processing units (CPUs), such as CPUs from INTEL or other manufacturer.

In some embodiments, the processing devices 104a-104b can operate according to instructions stored in a memory <NUM>. The memory <NUM> can also store data associated with radar parameters and radar return information. The memory <NUM> represents any structure(s) capable of storing and facilitating retrieval of information (such as data, program code, and/or other suitable information on a temporary or permanent basis). The memory <NUM> may represent a random access memory or any other suitable volatile or non-volatile storage device(s). While the system <NUM> is depicted with two processing devices 104a-104b and one memory <NUM> in <FIG>, this is merely one example implementation. Other embodiments may include other numbers of processing devices and/or other numbers of memories.

Based on the tasks received from the processing devices 104a-104b, the GPUs 110a-110f use the radar parameters and a three-dimensional, six degrees of freedom (6DoF) physics model of a scene in order to simulate one or more radar returns for the UUT <NUM>. In some embodiments, the physics model can include UUT <NUM> kinematic movements and responses to physics model stimuli. Each GPU 110a-110f generally operates to generate digitally-synthesized signals associated with the simulated radar return, including suitable Doppler frequencies, phases, and signal delays. The simulated radar return shows what the UUT <NUM> might "see" based on the radar parameters collected by the radar timing interface FPGA <NUM>. The simulated radar return can include simple or highly-complex scenes, including one or more extended targets, clutter, one or more electronic attack (EA) effects, and the like.

In this particular example, the system <NUM> includes six GPUs 110a-110f arranged in groups that operate in parallel and that are associated with different FPGA carriers 108a-108b. In this example, the GPUs 110a-110c are associated with the FPGA carrier 108a, and the GPUs 110d-110f are associated with the FPGA carrier 108b. Each FPGA carrier 108a-108b corresponds to a different set of radar channels 122a-<NUM> of the UUT <NUM>, and the GPUs 110a-110c or 110d-110f corresponding to each FPGA carrier 108a or 108b operate in parallel in order to generate the simulated radar return information associated with one set of radar channels 122a-122d or 122e-<NUM>. The radar return information includes coherent radar waveform information across the radar channels 122a-<NUM>. In some embodiments, the GPUs 110a-110f have suitable processing power to generate the radar return information in less than one millisecond for real-time operation.

Each GPU 110a-110f represents any suitable structure configured to generate simulated radar return information. In some embodiments, the GPUs 110a-110f are COTS GPU cards. Also, in some embodiments, the GPUs 110a-110f can operate according to instructions stored in the memory <NUM>. Also, in other embodiments, the GPUs 110a-110f can be substituted with FPGAs or ASICs. While the system <NUM> is depicted with six GPUs 110a-110f, this is merely one example implementation. Other embodiments may include other numbers of GPUs. In general, more GPUs allow for greater radar scene complexity or less computation time.

The FPGA carriers 108a-108b receive the simulated radar return information from the GPUs 110a-110f. Using a clock/trigger signal from a clock synchronizer <NUM>, the FPGA carriers 108a-108b operate to control the timing of when the radar return information is output to the UUT <NUM>. Each FPGA carrier 108a or 108b operates as a carrier for a corresponding group of DACs 106a-106d or 106e-<NUM>. In the embodiment shown in <FIG>, each FPGA carrier 108a-108b supports four DACs 106a-<NUM>. While the system <NUM> is depicted with two FPGA carriers 108a-108b each supporting four DACs 106a-<NUM>, this is merely one example implementation. Other embodiments may include other numbers of FPGA carriers, which support other numbers of DACs.

Using the timing control from the FPGA carriers 108a-108b, the DACs 106a-<NUM> operate to convert the digitally-synthesized signals associated with the simulated radar return to analog signals that the UUT <NUM> can actually receive and process. Each DAC 106a-<NUM> is associated with a corresponding channel of the UUT <NUM>. That is, each DAC 106a-<NUM> generates an analog signal to be transmitted over one of the radar channels 122a-<NUM>. Each DAC 106a-<NUM> represents any suitable structure configured to convert digital signals into analog signals. In some embodiments, each DAC 106a-<NUM> includes a giga-sample DAC, although other suitable DACs are possible and within the scope of this disclosure.

In some embodiments, the DACs 106a-<NUM> generate the analog signals at an intermediate frequency (IF) for injection into a UUT interface <NUM> of the UUT <NUM>. As known in the art, IF is often utilized in radar systems when going from digital-to-analog in accordance with the superheterodyne principle. In the system <NUM>, instead of the DACs 106a-<NUM> converting digital signals into analog signals at a radio frequency (RF) - only to have a receiver at the UUT <NUM> convert the analog signals back to intermediate frequency - the DACs 106a-<NUM> can generate each analog signal at the IF. If necessary, any RF up-conversion, down-conversion, and propagation steps can be simulated by the GPUs 110a-110f. Of course, generating analog signals at IF is merely one example implementation. In general, the system <NUM> is frequencyindependent and can simulate radar return signals or other types of signals at any suitable frequency or frequencies.

Also, in some embodiments, the system <NUM> may include at least one optional analog conditioner <NUM>. The analog conditioner <NUM> receives analog signals carried over the radar channels 122a-<NUM> and conditions each analog signal (such as by attenuation or amplification) to better accommodate the specifications of the UUT <NUM>. For example, in some tests, the UUT <NUM> can exhibit limited dynamic range. In such cases, if the analog signals from the DACs 106a-<NUM> are too strong, the analog conditioner <NUM> can attenuate the signals. The analog conditioner <NUM> can also be used to attenuate or amplify the simulated radar returns so that they represent the power levels encountered in a real radar environment.

The UUT interface <NUM> receives the analog signals generated by the DACs 106a-<NUM> and carried over the radar channels 122a-<NUM>. Once the analog signals are received by the UUT interface <NUM>, the UUT <NUM> can process the analog signals, interpret the simulated radar return information contained in the signals, and make any operational adjustments as needed. Operational changes by the UUT <NUM> may then be fed back to the radar timing interface FPGA <NUM> in a real-time closed-loop manner. In some embodiments, the UUT interface <NUM> is the same interface that a radar antenna would connect to when the UUT <NUM> operates in a real-world environment (not during testing). Also, in some embodiments, the UUT interface <NUM> can include one or more RF cables.

The clock synchronizer <NUM> operates to ensure that the UUT <NUM>, the DACs 106a-<NUM>, and the analog conditioner <NUM> have synchronized clocks or use the same clock source. This enables the DACs 106a-<NUM> to output the analog signals to the UUT <NUM> at precisely the right time. In one aspect of operation, the clock synchronizer <NUM> can receive timing information from the UUT <NUM>, process the timing information to generate a clock or trigger signal, and provide the clock or trigger signal to the DACs 106a-<NUM> and the analog conditioner <NUM>. In some embodiments, the system <NUM> can perform timing and synchronization of the signals via a waveform timing alignment technique. One example of this type of technique is described in the Applicant's co-pending patent application (Attorney Docket No. <NUM>-<NUM>-US-NP (RAYN01-<NUM>)). Using this technique, the system <NUM> can achieve waveform time control and alignment of less than or equal to the DAC's sampling period divided by two. The system <NUM> can achieve phase control and alignment at the accuracy of the DAC's phase control word for the analog signals transmitted across the radar channels 122a-<NUM>.

For convenience, the radar timing interface FPGA <NUM>, processing devices 104a-104b, DACs 106a-<NUM>, FPGA carriers 108a-108b, GPUs 110a-110f, and memory <NUM> can be disposed together in one housing <NUM>. In some embodiments, the housing <NUM> includes a small COTS rack or chassis. This is in contrast to some conventional analog systems, which can include enough components to occupy four or more full size (six-foot) racks. Note, however, that the radar timing interface FPGA <NUM>, processing devices 104a-104b, DACs 106a-<NUM>, FPGA carriers 108a-108b, GPUs 110a-110f, and memory <NUM> can be housed in any other suitable manner.

Using the components shown in <FIG>, the system <NUM> enables full testing coverage of tactical hardware, firmware, and software of the UUT <NUM>. The system <NUM> provides much greater testing flexibility over conventional analog systems. Radar and kinematic scenarios can be easily updated in the system <NUM> via simple software or data updates. For example, the system <NUM> can be readily updated to add, change, or remove radar return signals associated with one or more scatterers, weather objects, clutter, EA effects, and the like (no hardware changes may be needed). Calibration of the system <NUM> is simplified and can be performed in minutes. In contrast, in a conventional analog system, a new scene might require new racks of hardware to simulate and require weeks to calibrate.

The system <NUM> is fully scalable both in the frequencies used and in the number of radar channels supported. Components (such as processing devices 104a-104b, DACs 106a-<NUM>, FPGA carriers 108a-108b, GPUs 110a-110f, analog conditioners <NUM>, radar channels 122a-<NUM>, and the like) can be added, combined, or removed to scale the system <NUM> as needed. In some embodiments, the system <NUM> can support direct digital injection into the UUT <NUM>. That is, some embodiments of the system <NUM> can operate without any DACs 106a-<NUM> and maintain the radar return signals in an all-digital format. Such digital signals can be injected directly into the signal processing system of the UUT <NUM>. In some embodiments, the system <NUM> can support RF projection, where each DAC channel drives an antenna on an array wall within an anechoic chamber. The DAC channels can be optionally conditioned with frequency up/down conversion, signal gain, or attenuation to meet the requirements of the RF projection embodiments.

Although <FIG> illustrates one example of a system <NUM> for performing a real-time closed-loop digital radar simulation, various changes may be made to <FIG>. For example, the system <NUM> may include any suitable numbers of processing devices, DACs, FPGA carriers, and GPUs. In general, the makeup and arrangement of the system <NUM> are for illustration only. Components may be added, omitted, combined, rearranged, or placed in any other configuration according to particular needs.

<FIG>, and <FIG> illustrate examples of benefits that can be realized using real-time closed-loop digital radar simulation according to this disclosure. In particular,.

<FIG> depict a comparison between an image <NUM> of a radar scene generated using a conventional radar simulation technique and an image <NUM> of the same radar scene generated using the system <NUM> of <FIG>. The images <NUM>, <NUM> generally represent what a radar system might "see" during actual operation.

As shown in <FIG>, the image <NUM> was generated using a conventional radar simulation technique. The image <NUM> includes a target object <NUM> that represents a target and a background object <NUM> that may represent clutter, an interference signal, or the like. In contrast, the image <NUM> in <FIG> was generated using the system <NUM> as described above. The image <NUM> also includes a target object <NUM> representing the target and a background object <NUM> representing clutter, an interference signal, or the like.

As shown in the image <NUM>, the target object <NUM> is represented as a single point scatterer with an ideal signature in the range and Doppler dimensions. However, in the image <NUM>, the target object <NUM> is represented by hundreds of point scatterers, resulting in a more realistic radar signature in the range and Doppler dimensions. Similarly, in the image <NUM>, the background object <NUM> is generated with a noise source with a fixed position and orientation in range and Doppler. However, in the image <NUM>, the background object <NUM> is represented by a collection of scatterers in 3D space and therefore exhibits a realistic orientation in range and Doppler that changes with scene geometry. The image <NUM> is a much more accurate representation of what a radar system under test would actually receive or generate.

In <FIG>, the image <NUM> shows a clear example of the precise control of individual reflection points available using the system <NUM>. As shown in <FIG>, the word "CHIP" is spelled with thirty-one reflection points <NUM> in the range and Doppler dimensions. Using conventional radar return generators, it would be nearly impossible to scale the necessary physical analog hardware in size to generate thirty-one individual targets. In contrast, the system <NUM> is easily capable of generating thirty-one reflection points <NUM>, since the targets are generated digitally. As discussed above, the system <NUM> can provide a representation of many more scattering centers or reflection points, as well as much higher fidelity of the position of each scattering center. In some embodiments, the system <NUM> improves fidelity by fifty to one hundred times or more.

Although <FIG> illustrate examples of benefits that can be realized using real-time closed-loop digital radar simulation, various changes may be made to <FIG>. For example, <FIG> are merely meant to illustrate some examples of the type of benefits that may be obtained using real-time closed-loop digital radar simulation. Images of radar scenes vary widely, and other results may be obtained depending on the radar scene and the implementation.

<FIG> illustrates an example method <NUM> for performing a real-time closed-loop digital radar simulation according to this disclosure. For ease of explanation, the method <NUM> is described as being performed using the system <NUM> of <FIG>. However, the method <NUM> may be used with any other suitable device or system.

As shown in <FIG>, radar parameters are received from a UUT at step <NUM>. This may include, for example, the radar timing interface FPGA <NUM> receiving radar parameters from the UUT <NUM>. Multiple tasks are generated using at least one processing device at step <NUM>. This may include, for example, at least one of the processing devices 104a-104b receiving the radar parameters, generating multiple tasks, and sending the tasks to at least one of the GPUs 110a-110f. The tasks are associated with the generation of a simulated radar return.

A simulated radar return for the UUT is generated using at least GPU at step <NUM>. This may include, for example, at least one of the GPUs 110a-110f generating a simulated radar return for the UUT <NUM>. The simulated radar return includes digital signals. In some embodiments, the simulated radar return can include return signals associated with one or more scatterers, one or more weather objects, clutter, one or more EA effects, or a combination of these. For pulsed radar embodiments, a scene of one or more simulated radar returns can be calculated for each pulse's receive window, accurately simulating pulse to pulse scene kinematic changes during a coherent processing interval. A timing of the output of the simulated radar return to the UUT is controlled using at least one FPGA carrier at step <NUM>. This may include, for example, at least one of the FPGA carriers 108a-108b controlling the timing of the output of the simulated radar return to the UUT <NUM>.

The digital signals are converted into analog signals using multiple DACs at step <NUM>. This may include, for example, at least some of the DACs 106a-<NUM> receiving the digital signals from the GPUs 110a-110f and converting the digital signals into analog signals. The analog signals are optionally conditioned using at least one analog conditioner at step <NUM>. This may include, for example, the analog conditioner <NUM> attenuating or amplifying the analog signals. The analog signals can be conditioned according to one or more specifications of the UUT <NUM> and/or to represent the power levels encountered in a real radar environment.

The analog signals (or their conditioned versions) are transmitted to the UUT at step <NUM>. This may include, for example, at least some of the DACs 106a-<NUM> transmitting the analog signals to the UUT <NUM> over at least some of the radar channels 122a-<NUM>. In some embodiments, the analog signals are transmitted to the UUT over multiple radar channels 122a-<NUM>, where each channel corresponds to one of the DACs 106a-<NUM>.

The analog signals are received at the UUT at step <NUM>, and the UUT can process the signals to interpret the simulated radar return and make any operational adjustments as needed. This may include, for example, the UUT <NUM> receiving the analog signals, processing the signals, interpreting the simulated radar return, and making any desired operational adjustments. The adjusted UUT can then generate second radar return information, at which point the method <NUM> can return to step <NUM> where the second radar parameters are received from the UUT. This allows operational changes by the UUT <NUM> to be fed back to the radar timing interface FPGA <NUM> in a real-time closed-loop manner.

Although <FIG> illustrates one example of a method <NUM> for performing a real-time closed-loop digital radar simulation, various changes may be made to <FIG>. For example, while shown as a series of steps, various steps shown in <FIG> may overlap, occur in parallel, occur in a different order, or occur multiple times. Also, some steps may be combined or removed and additional steps may be added according to particular needs.

Claim 1:
A method (<NUM>) comprising:
receiving (<NUM>) radar parameters from a unit under test, UUT (<NUM>);
generating (<NUM>) multiple tasks based on the radar parameters;
sending the tasks and the radar parameters to multiple graphics processing units, GPUs (110a-110f);
generating (<NUM>), using the GPUs, a simulated radar return for the UUT based on the tasks, the radar parameters, and a three-dimensional model of a scene, the simulated radar return comprising digital signals;
controlling (<NUM>) a timing of output of the simulated radar return to the UUT using multiple field programmable gate array, FPGA, carriers (108a, 108b), the FPGA carriers associated with different ones of the GPUs;
converting (<NUM>) the digital signals into analog signals using multiple digital-to-analog converters, DACs (106a-<NUM>); and
transmitting (<NUM>) the analog signals to the UUT.