Patent Description:
Integrated circuits, which are used as an interface to the 'outside world', are often subject to heavy system level electrostatic discharge requirements. Examples are the IEC (International Electrotechnical Commission) <NUM>-<NUM>-<NUM> ('system level stress') or the IEC <NUM>-<NUM>-<NUM> ('surge stress') standards. IEC <NUM>-<NUM>-<NUM>, in particular, is the International Electrotechnical Commission's immunity standard on Electrostatic Discharge. The publication is one of the basic EMC (electromagnetic compatibility) standards of the IEC <NUM>-<NUM> series. The European equivalent of the standard is referred to as EN <NUM>-<NUM>-<NUM>. IEC <NUM>-<NUM>-<NUM> is the International Electrotechnical Commission's international standard on surge immunity. That is, power lines may be hit by surges from power switches and from lightning, and the standard defines test set-up and procedures, and classification levels.

In addition to heavy system level electrostatic discharge applications, such electrostatic discharge requirements can also apply to powered IC chips (e.g., the IC chip should be able to sink the electrostatic discharge stress when powered up). Together with these types of electrostatic discharge requirements, some IC chips may have a high DC voltage tolerance specification. For example, a Type-C USB connector (also referred to as a "Type-C connector") may be tolerant to voltages exceeding, for example, 20V DC. Note that the acronym "USB" as utilized herein refers to "Universal Serial Bus" and is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply between personal computers and their peripheral devices.

An IC chip may include a switch functionality, typically implemented provided by a switch MOS (Metal-Oxide-Semiconductor) device with the drain on one data terminal, and the source on the other data terminal. An example is the CC (Configuration Channel) line in USB applications. The 'outside world' facing terminals in such chips often connect to the drain of an HV (High Voltage) MOS device, and the source to a terminal with low to minimal electrostatic discharge risk.

Since there is a possibility that the switch is in a conducting state when the electrostatic discharge stress occurs (e.g., due to the power-up requirement), the electrostatic discharge current can pass the switch and reach the source side. Fast electrostatic discharge transients may lead to gate lifting as well (even when the switch is non-conducting) and charge the source node. This situation can be risky, because the circuitry at the source side of the switch can include low voltage circuitry, which is vulnerable to failure at a high voltage.

A pull-down circuit can be added at the source side to ameliorate these risks. If comparators are used, however, the configuration may be too slow to pull down the source node. Dedicated electrostatic discharge protection circuitry can be used in electronic devices on the source side of a switch as well (these can react fast) for additional electrostatic discharge protection. The electrostatic discharge protection circuitry, however, can take up a great deal of area. This additional circuitry on the source side may also result in additional capacitance on the data line and can compromise bandwidth performance.

United States patent publication number <CIT> discloses a substrate-triggering of ESD-protection devices, in which ESD protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A P-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-Pin ESD test, power and ground floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the flower floating around the pass.

Embodiments of a method, a circuit and a system are disclosed. In an embodiment, a discharge protection circuit is disclosed. The discharge protection circuit includes a switch having a capacitive coupling between a gate and a drain of the switch, wherein the capacitive coupling facilitates a capacitively coupled current. The discharge protection circuit further includes a gate network including at least the gate of the switch, a gate control element and a resistor connected to the gate and the gate control element. In addition, the discharge protection circuit includes an electrostatic discharge rail that connects to a diode that is coupled to the gate and the resistor, wherein the capacitive coupling facilitates sinking of at least a part of an electrostatic discharge current via the gate network.

In an embodiment of the discharge protection circuit, the gate network can include an AC-triggered electrostatic discharge protection element that sinks the capacitively coupled current.

In an embodiment of the discharge protection circuit, the gate network can include a DC-triggered electrostatic discharge protection element that sinks the capacitively coupled current.

In an embodiment, the discharge protection circuit can further include an indirect clamping of a source side of the switch.

In an embodiment, the switch of the discharge protection circuit can include an MOS device.

In an embodiment, the electrostatic discharge rail of the discharge protection circuit can include a shared rail that is shareable by at least one other circuit.

In an embodiment, the capacitive coupling of the discharge protection circuit can include one or more capacitors.

A method of operating a discharge protection circuit is also disclosed. The method involves producing a capacitively coupled current utilizing a capacitive coupling of a switch configured with the capacitive coupling between a gate and a drain of the switch, and sinking at least a part of an electrostatic discharge current via a gate network comprising at least the gate of the switch, a gate control element and a resistor connected to the gate and the gate control element, wherein the electrostatic discharge current is facilitated by an electrostatic discharge rail that connects to a diode coupled to the gate and the resistor.

In an embodiment of the method, the gate network can include an AC-triggered electrostatic discharge protection element that sinks the capacitively coupled current.

In an embodiment of the method, the gate network can include a DC-triggered electrostatic discharge protection element that sinks the capacitively coupled current.

In an embodiment of the method, an indirect clamping of a source side of the switch can be utilized.

In an embodiment of the method, the switch can include an MOS device.

In an embodiment of the method, the electrostatic discharge rail can include a shared rail that is shareable by at least one other circuit.

In an embodiment of the method, the capacitive coupling can include one or more capacitors.

A discharge protection system is also disclosed. The discharge protection system includes a circuit comprising a switch that includes at least one transistor, wherein the switch comprises a capacitive coupling between a gate and a drain of the at least one transistor, wherein the capacitive coupling facilitates a capacitively coupled current. The discharge protection system also includes a gate network comprising at least the gate of the at least one transistor, a gate control element and a resistor connected to the gate and the gate control element. The discharge protection system further includes an electrostatic discharge rail that connects to at least one diode coupled to the gate and the resistor, wherein the capacitive coupling facilitates sinking of at least a part of an electrostatic discharge current via the gate network.

In an embodiment of the discharge protection system, the gate network includes an electrostatic discharge protection element that sinks the capacitively coupled current.

In an embodiment of the discharge protection system, an indirect clamping of a source side of the at least one transistor can include an MOS device.

In an embodiment of the discharge protection system, the MOS device can include at least one of an HV (High Voltage) MOS device and an LV (Low Voltage) MOS device.

In an embodiment of the discharge protection system, the MOS device can include a plurality of MOS devices in a back-to-back arrangement that includes two or more MOS devices.

In an embodiment of the discharge protection system, the electrostatic discharge rail can include a shared rail that is shareable by one or more other circuits and the capacitive coupling can include one or more capacitors.

Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, and is merely representative of various embodiments.

The embodiments may be implemented in other specific forms. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description.

Thus, discussions of the features and advantages, and similar language, throughout this specification may or may not refer to the same embodiment.

Several aspects are presented with reference to various systems, methods and devices. These systems, methods and devices are described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, operations, processes, algorithms, engines, applications, etc. (which can be individually or collectively referred to as "elements").

The disclosed solution provides an ESD (electrostatic discharge) protection architecture for switches that may be subject to system level stresses and fast transients (e.g., for high speed, power, and protection switches). As will be discussed in greater detail herein, a capacitive coupling (e.g., one or more capacitors) can be located between the gate and drain of a switch so as to sink a part of the electrostatic discharge current via a gate network ("gate net") that includes elements such as a gate control circuit, a gate control resistor, the gate of the switch (e.g., a transistor gate) along with other features such as a gate load. Note that as utilized herein, the acronym "ESD" and the phases "electrostatic discharge" and "Electrostatic Discharge" can be utilized interchangeably with one another to refer to the same feature.

The disclosed embodiments are particularly effective for fast electrostatic discharge events, such as, for example, IEC <NUM>-<NUM>-<NUM>, because the coupling to the gate net is then the strongest. The gate net can include the use of AC (Alternating Current) -triggered or DC (Direct Current) -triggered electrostatic discharge protection elements to sink the capacitively coupled current, which results from the use of the aforementioned capacitor(s). The electrostatic discharge protection features may not interfere with the functional operation of the gate net. As will be discussed in greater detail herein, one important benefit of this approach is that the disclosed electrostatic discharge architecture can include an indirect clamping of the source side of the switch (since the source voltage may not rise above the clamping voltage of the gate minus a threshold voltage, Vth). Another benefit of this approach is that the disclosed embodiments may not load the data line (i.e., the drain/source side of the switch), and therefore may not compromise the (high) bandwidth performance of the switch.

<FIG> depict a group of schematic diagrams, which illustrate different circuit configurations with dedicated electrostatic discharge diodes and rail clamps. Depending on the particular electrostatic discharge strategy employed, the rail clamps can be shared. In addition, diode-connector resistors can be used to pre-charge the rail clamp. Note that in <FIG>, identical or similar parts or elements are generally indicated by identical reference numerals.

<FIG> depicts a schematic diagram of an HV (high speed) switch circuit <NUM> with gate control facilitated by a gate control circuit <NUM>. The HV switch circuit <NUM> includes an input pin <NUM> that connects to a transistor <NUM> (e.g., NMOS transistor) that in turn connects to an output pin <NUM> and the gate control circuit <NUM>. Note that as utilized herein, the term "switch circuit" may also be referred to simply as a "switch". That is, the terms "switch circuit" and "switch" may be utilized interchangeably to refer to the same general feature or element.

<FIG> depicts a schematic diagram of a VCONN switch circuit <NUM> with gate control facilitated by the gate control circuit <NUM>. The VCONN switch circuit <NUM> includes an input pin <NUM> and an output pin <NUM> that are coupled to the transistor <NUM>. The gate control circuit <NUM> can also be coupled to the transistor <NUM> in the configuration of switch circuit <NUM>. Note that the input pin <NUM> can be referred to as a "CC1/CC2" input pin or simply a CC1/CC2 pin, and the output pin <NUM> can be referred to as a "VCONN" output pin or simply a VCONN pin.

As utilized herein, "CC1/CC2" or simply "CC1" and "CC2" can refer to a "CC" (Configuration Channel) line of a USB Type-C connector subsystem. CC1 and CC2 are thus particular types of pins typically utilized in the context of a USB Type-C solution. CC1/CC2 provides a configuration channel capable of facilitating, for example, the detection of USB ports (e.g., a source to a sink), resolve cable orientation and twist connections to establish USB data bus routing, establishing data roles between two or more attached ports, discovering and configuring, for example, USB type-C current modes or USB power delivery, configuring VCONN, and discovering and configuring optional alternative and accessory modes.

<FIG> depicts a schematic diagram of a JTAG (Joint Test Action Group) switch circuit <NUM> with gate control facilitated by the gate control circuit <NUM>. The JTAG switch circuit <NUM> includes a JTAG input pin <NUM> and a CC1/CC2 output pin <NUM> coupled to the transistor <NUM>. The gate control circuit <NUM> is coupled to the transistor <NUM>. Note that the JTAG as utilized herein refers to "Joint Test Action Group (named after the Joint Test Action Group, which codified it) is an industry standard for verifying designs and testing printed circuit boards after manufacture.

<FIG> depicts a schematic diagram of a circuit <NUM> having a detection/termination and FRS (Fast Role Swap) configuration. The circuit <NUM> includes a CC1/CC2 input pin <NUM> coupled to a transistor <NUM> and a transistor <NUM>. Each transistor <NUM> and transistor <NUM> can include a respective gate coupled to a fixed voltage (V FIX). The transistor <NUM> can be further connected to a resistor <NUM> that in turn connects electronically to a transistor <NUM> and an amplifier <NUM>. The transistor <NUM> further connects to ground <NUM>.

Note that as utilized herein, the term FRS refers to the "Fast Role Swap" feature, which is defined in the USB Power Delivery specification (USB PD) to support the USB's goal of a flexible, low-voltage dc power-distribution system by allowing for a seamless power transfer and continued system operation following an unexpected loss of power. The "detection/termination" aspect of circuit <NUM> may involve the detection and termination of, for example, USB ports, while the FRS aspect of circuit <NUM> can support the "Fast Role Swap" feature, as discussed above.

The transistor <NUM> can also be electronically coupled to a sub-circuit <NUM> that can include a current-source <NUM> that connects to a switch <NUM> that in turn can connect to a resistor <NUM> coupled to a switch <NUM> connect to ground <NUM>. In the circuit <NUM> shown in <FIG>, the transistors <NUM>, <NUM>, and <NUM> can be implemented as, for example, NMOS transistors or other types of MOS devices.

The sub-circuit <NUM> can optionally include an operational amplifier <NUM> and buffers <NUM> and <NUM>. Although not shown as tied directly to either the current source <NUM> or <NUM> in the sub-circuit <NUM> or any other specific circuit elements, it should be appreciated that the operational amplifier <NUM> and the buffers <NUM> and <NUM> can be electronically incorporated into the sub-circuit <NUM> as may be needed and are shown as "separate" from the other elements for this reason.

<FIG> depicts a schematic diagram of a circuit <NUM> that includes a switch with two pins <NUM> and <NUM>, diodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and respective first and second electrostatic discharge rails <NUM> and <NUM>. The diodes <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> can function as electrostatic discharge diodes. The output of the diode <NUM> connects to the first electrostatic discharge rail <NUM> and to a first rail clamp <NUM>. The input of the diode <NUM> is coupled to a voltage source <NUM>. The output of the diode <NUM> can be coupled to the electrostatic discharge rail <NUM> and the output of the diode <NUM> can be coupled to the second electrostatic discharge rail <NUM>. The output of the diode <NUM> can be coupled to the second rail clamp <NUM>, the second electrostatic discharge rail <NUM> and the output of the diode <NUM>. The input to the diode <NUM> can be coupled to a voltage source <NUM>.

The output of the diode <NUM> can connect to the input of the diode <NUM>, the pin <NUM>, and a transistor <NUM>. Similarly, the output of diode <NUM> can connect to the transistor <NUM>, the input to diode <NUM>, and the pin <NUM>. In addition, the input to the diode <NUM>, the input to the diode <NUM>, and the first rail clamp <NUM> and the second rail clamp <NUM> can further connect to ground <NUM>.

<FIG> thus depict a summary of different circuit that may require at least some form of electrostatic discharge protection. In general, in the connector side of the illustrated transistor (e.g., such as transistor <NUM> shown in <FIG>, transistors <NUM>, <NUM> and <NUM> shown in <FIG>, and transistor <NUM> shown in <FIG>), which constitute the drain of a high voltage NMOS, there will be negative electrostatic discharge protection to ground, and positive electrostatic discharge protection with respect to the first rail clamp <NUM> or the second rail clamp <NUM> (e.g., which in some configurations can each be implemented in the context of a dedicated or shared ESD rail).

The source side of an EDNMOS (Enhancement and Depletion NMOS) transistor, for example, can include another pin (e.g. such as in the high speed HV switch circuit <NUM>, the JTAG switch circuit <NUM> or the VCONN switch circuit <NUM>). Note that "EDNMOS" refers to a type of MOS device having enhancement and depletion modes. In this case, the drain can be connected to the pin and can be protected by electrostatic discharge diodes depending on the requirements (e.g., negative and positive ESD). Some low voltage tolerant circuitries (e.g., such as USB Type-C RX/TX, CC Detection/Termination, etc.) may include configurations in which the drain is connected to another circuit. Thus, the gate of the switch and the gate control circuit can be protected. This means that a fast clamping mechanism may be used. The drain of the switch and whatever is connected to it may also use protection.

Pins that may need extra protection can include, for example, CC1 and CC2 pins such as the CC1/CC2 pin <NUM> shown in <FIG>, the CC1/CC2 pin <NUM> illustrated in <FIG>, and the CC1/CC2 pin <NUM> depicted in <FIG>. In some cases, a VCONN switch, CC Detection/termination components, BMC (bi-phase marked coding) and PHY (Physical layer) elements, FRS elements, and JTAG switches can be directly connected to these pins. In some configurations of the circuit <NUM>, circuit elements can be protected using, for example, a source follower EDNMOS transistor to ensure that higher signals are clamped to ~Vgate-Vth (i.e., gate voltage to threshold voltage).

SBU, DS+/- (High speed pins) may also require extra protection in some instances. In these cases, EDNMOS devices, for example, can be utilized as high-speed switches to tolerate the higher voltage. Although in this situation the drain is generally safe, the source and gate may use additional protection.

In general, to provide consistent conditions across a variety of different circuits, a high voltage NMOS (e.g., EDNMOS) can be used as a protection element, either in the form of a switch (e.g., such VCONN, JTAG, SBU and data switches) or in the form of a source follower that clamps the drain voltage to gate voltage minus Vth (i.e., threshold voltage). Because different voltage levels and electrostatic discharge requirements may be needed for different pins, consistent solutions may be required for a variety of circuit architectures. Such solutions, which are discussed in greater detail herein, can lower the complexity and risks associated with electrostatic discharge protection devices.

<FIG> depicts a schematic diagram of a Type-C connector <NUM> with pins. A fast transient can occur on any Type-C connector signal. Some of the pins "may" be used for different functionalities. For example, Vbus (i.e., bus voltage) may be used for a power delivery purpose in a sink mode or a source mode. CC <NUM> and CC2 can be used as termination/detection pins and VCONN can be used for power delivery (e.g., a power delivery pin). Note that "CC" refers to a Type-C connector pin and "CC1" refers a first Type-C connector pin and "CC2" refers to a second Type-C connector pin.

<FIG> shows the functionality of some of the connected blocks to Type-C connector pins, which can be protected according to the disclosed ESD protection approach. Each simple block shows the pin/pins used for the desired functionality.

For example, block <NUM> indicates a high-speed data path (e.g., TX for USB, or for DP Alt Mode). Block <NUM> represents a USB <NUM> interface, and block <NUM> indicates a high-speed data path (e.g., RX for USB, or TX for DP Alt Mode). Note that "TX" refers to "transmit" and "RX" refers to "receive". Block <NUM> represents a ground cable, and block <NUM> indicates cable bus power. Block <NUM> represents a secondary bus and block <NUM> indicates plug configuration detection capabilities VCONN, cable power and CC adapted for use in USB-PD (USB Power Delivery) communication. The example connector pins architecture <NUM> shown in <FIG> demonstrates that pins such as CC1/CC2 and SBU (Side Band Use), DS (Digital Signal) +/<NUM> (High Speed Pins) can require extra electrostatic discharge protection.

In general, to ensure that all conditions are similar, a high voltage element such as, for example, a high voltage NMOS (EDNMOS), can be used as the protection mechanism in the next stage. This protection feature can be provided either in the form of a switch (e.g.,VCONN, JTAG, SBU and data switches) or in form of a source follower that clamps the drain voltage to the transistor gate voltage minus Vth (e.g., threshold voltage). Because there are different voltage levels and electrostatic discharge requirements for different pins, a solution for different circuitries is desired. This solution, which is disclosed herein, can lower the complexity of the electrostatic discharge protection circuit and can also be easily implemented.

<FIG> depict schematic diagrams illustrating a switch circuit <NUM> and a switch circuit <NUM> having respective circuit configurations that include a clamped diode with shared or dedicated electrostatic discharge rails (e.g., for the cases shown in <FIG>). Note that in <FIG>, similar or identical parts or elements are indicated by identical reference numerals. The circuit <NUM> shown in <FIG> represents a first example of a discharge protection system and the circuit <NUM> shown in <FIG> represents a second example of a discharge protection system. Circuit <NUM> provides a circuit configuration that is a variation to the circuit <NUM>.

In the circuit <NUM> shown in <FIG>, an input pin <NUM> is coupled to a transistor <NUM> (e.g. an NMOS transistor), which in turn can be coupled to an output pin <NUM>. The transistor <NUM> can be further connected to the input of a diode <NUM> (DG) whose output engages an electrostatic discharge rail <NUM>. A resistor <NUM> (Rgc) is also connected to the transistor <NUM> and the input to the diode <NUM>. The resistor <NUM> can function as a gate control resistor. A gate control circuit <NUM> can be also coupled to the resistor <NUM>. A ground terminal <NUM> is also shown with respect to circuit <NUM> (and also circuit <NUM> in <FIG>).

In circuit <NUM> shown in <FIG>, an additional diode <NUM> (DD) can be provided whose input is coupled to the transistor <NUM> and to a circuit <NUM> (CKT). The output of the diode <NUM> connects to the output of the diode <NUM> and the electrostatic discharge rail <NUM>. The diode <NUM> can function as a gate diode with respect to the gate of transistor <NUM>.

<FIG> demonstrate that an ESD protection is connected to the gate net of the switch. This ESD protection can be an AC or DC ESD protection. The resistor <NUM> can be placed between the gate control circuit <NUM> and the gate net (where the ESD protection is placed) as shown in <FIG>. The resistor <NUM> can be added in series from the gate of the transistor <NUM> to the gate control circuit <NUM> (Rcg) to limt the current that goes to the gate control circuit <NUM>. This can increase Vg (safe) and decrease the size of the clamp device. The diode <NUM> connected to the (pre-biased) electrostatic discharge rail <NUM> can also be used as shown in <FIG> for AC electrostatic discharge protection (e.g., rail clamps).

The electrostatic discharge protection on the gate net can be selected such that under a fast system level electrostatic discharge event, such as found in the IEC immunity standard <NUM>-<NUM>-<NUM> on electrostatic discharge, the gate net can be clamped to a voltage where the source node circuitry can survive the electrostatic discharge event. If an instantiation using a pre-biased electrostatic discharge rail is applied, the diode <NUM> between the source net and the pre-biased electrostatic discharge rail <NUM> can be used as shown in <FIG>.

Additionally, the electrostatic discharge protection on the data line (the drain/source side of the transistor <NUM>) can potentially be reduced in size, which facilitates improvements in the bandwidth performance of the overall circuit. Simulations with ESD transients can be used to tune the ESD protections on the data line. In addition, the drain (and source) of the transistor <NUM> can be connected to the electrostatic discharge rail <NUM> using a diode (DD) such as the diode <NUM> shown in <FIG>. The diode <NUM> can be added to clamp the voltage on the drain of the transistor <NUM>. The diode <NUM> generally operates as a drain diode (i.e., with respect to the drain of the transistor <NUM>), among other functions.

The gate can also be connected to the electrostatic discharge rail <NUM> using the diode <NUM>. The diode <NUM> can be added to the circuit <NUM> to clamp the voltage on the gate. The electrostatic discharge rail <NUM> can be shared for the diode <NUM> (e.g., a gate diode) and the diode <NUM> (e.g., a drain diode) as shown in <FIG>. The rail clamp can be dedicated or shared, which means that the electrostatic discharge rail <NUM> can also be dedicated or shared, depending on the requirements of the particular system application or layout limitations. In addition, the sizes of the diodes <NUM> and <NUM> and the resistor <NUM> may vary and can be optimized, depending on the use case. Additionally, whether or not the electrostatic discharge rail <NUM> is dedicated or shared depends on the practical limitations of the layout.

<FIG> depicts a schematic diagram of a circuit <NUM> based on a transistor model with major parasitic components shown. The circuit <NUM> can be modeled to include a capacitor <NUM> (Cds) in parallel with a resistor <NUM> (Rds). The capacitor <NUM> and the resistor <NUM> can connect to a voltage input <NUM> (VD) and the input to an impedance element (Zin) <NUM> at VS. A capacitor <NUM> (Cdg) functions as a drain to gate capacitor (i.e., with respect to the drain and gate of transistor <NUM>) and a capacitor <NUM> (Cgs) functions as a gate to source capacitor (i.e., with respect to the gate and source of transistor <NUM>). Capacitors <NUM> and <NUM> can also connect to a resistor <NUM> (Rgc) and a gate load <NUM>.

The resistor <NUM>, which functions as a gate control resistor, can also be connected to a gate control circuit <NUM>. Note that "Cdg" can refer to a drain to gate capacitor, "Cgs" can refer to a gate to source capacitor, and "Cds" can refer to a drain to source capacitor. "Rgc" refers to a gate control resistor and "Rds" can refer to a drain to source resistor.

When the transistor <NUM> is large (such as shown in <FIG>), the parasitic is also large. A "very simple" model can ignore the transistor <NUM> and deals with parasitic features in a "FAST Surge" event. Two cases are possible - when the switch is "OFF" and when the switch is "ON". That is, when the switch is "OFF" (e.g., for a high speed switch case or for a surge event during power up), the resistor <NUM> (Rds) is large. The switch is "ON" for high-speed cases, wherein, Rds~few ohm, and for common source protection circuits, wherein Rds~few <NUM> of ohm.

The model shown in <FIG> thus employs parasitic capacitance between the gate and drain of the transistor <NUM> (the same is true for the transistor <NUM> shown in <FIG>), and offers strong electrostatic discharge performance for fast transient signals because of the direct capacitive coupling facilitated by, for example, the capacitor <NUM>.

<FIG> depict schematic diagrams of respective delta and star models <NUM> and <NUM> and associated conversion equations <NUM> and <NUM>, along with a simplified transistor model <NUM> with proper loading. Considering voltages V<NUM>=VG, V<NUM>=VS, V<NUM>=VD, a transistor is a "Delta impedance model" and can change to a "Star Impedance" Model.

<FIG> illustrate simplified models that consider a variety of impedances. The model shown in <FIG> demonstrates how any ΔV (i.e., change in voltage) at the drain can be transferred to the gate and source of, for example, the transistor <NUM> shown in <FIG> and can harm the transistor if not clamped properly. Note that in these models, the parameter "V" can refer to voltage, the parameter "Z" cam refer to impedance, and the parameter "I" can refer to current. The resistor <NUM> (Rgc) shown in <FIG> is the added resistor (i.e., the gate control resistor) discussed earlier. Considering: <MAT>.

Voltages at Nodes VD, Vs, VG can be calculated as follow: <MAT> <MAT> Where: <MAT> <MAT>.

This means that when, for example, the Rgc increases, Ic decreases. This is a feature that can be used to protect a gate control circuit, such as, for example, the gate control circuit <NUM> shown in <FIG> and the gate control circuit <NUM> shown in <FIG>. The equations above also indicate that the larger the resistance of Rcg, the better. In other words, a high impedance path is generally better. Although in some cases, this may not be the case, because the voltage at the gate of the transistor will be increased for a high impedance case.

If a "low impedance" path is present when Vg>Vg, the "safe" feature is desired. A similar argument is valid for VD - that is, if a low impedance path is present when VD>VD, a "safe" feature is also desired. Note that if a maximum voltage limitation is "on" and between nodes during electrostatic discharge and surge events, the impedances can be used to calculate how much voltage will fall over each node and if the voltage will remain in a safe range. If the impedance is too high, a protection feature should be added.

Note that the term "maximum voltage" can refer to the voltage at which an electrical or electronic device, circuit, component, or element can retain its properties during its lifetime and in the recommended environment and usage parameters. This may be lower than the maximum allowable voltage, for example, in testing. The term "maximum voltage" may also refer to the absolute maximum rated voltage that can be applied to an electrical or electronic device, circuit, component, or element, beyond which damage (latent or otherwise) may occur.

<FIG> depicts a schematic diagram of a circuit <NUM> having a switch configuration with electrostatic discharge protection including a gate diode. The circuit <NUM> can include a gate control element <NUM> that is coupled to resistor <NUM>, which in turn connects to a diode <NUM> and the gate of a transistor such as MOS device <NUM>. The circuit <NUM> can be implemented in a discharge protection circuit.

The diode <NUM> can further connect to a resistor <NUM> and an ESD protection element, which may be a DC or AC triggered ESD protection component or sub-circuit. The diode <NUM> can thus connect to a DC or AC triggered ESD protection element <NUM> and to the output of an optional source diode <NUM>, which may in turn can connect to a low voltage pin <NUM>, the source of the MOS device <NUM> and to an electrostatic discharge element <NUM> (i.e., which offers the ESD solution described herein). The resistor <NUM> can also connect to a pre-bias element <NUM>.

Thus, in the configuration shown in <FIG>, the diode <NUM> can be implemented from the gate net to a pre-biased net (i.e., from the gate control element <NUM> and resistor <NUM> to the resistor <NUM> and the pre-bias element <NUM>).

The drain of the MOS device <NUM> can be connected to a high voltage pin <NUM> and also to another electrostatic discharge protection element <NUM>. The electrostatic discharge protection element <NUM>, the electrostatic discharge protection element <NUM>, and the DC or AC triggered electrostatic discharge protection element <NUM> can be further connected to ground <NUM>.

<FIG> depicts a schematic diagram of a circuit <NUM> having a switch configuration with electrostatic discharge protection that does not include a gate diode. The circuit <NUM> can be implemented in a discharge protection circuit. Note that in <FIG>, <FIG>, identical or similar components or elements are generally indicated by identical reference numerals. Circuit <NUM> shown <FIG> is a modified version of the circuit <NUM> shown in <FIG>. In circuit <NUM>, the diode <NUM> that was included in circuit <NUM> has now been removed with respect to the gate control element <NUM>, meaning that the electrostatic discharge protection element can be directly connected to the gate net.

<FIG> depicts a schematic diagram of a circuit <NUM> having a back-to-back switch arrangement with electrostatic discharge protection at the gate net and including the diode <NUM> (which can function as a gate diode). In circuit <NUM>, the diode <NUM> can connect from the gate net to the pre-biased net (similar to the arrangement shown in <FIG>). The circuit <NUM> shown in <FIG> is a modified version of the previously illustrated circuits <NUM> and <NUM>.

In the configuration shown in <FIG>, circuit <NUM> includes a group of transistors including the MOS device <NUM> and another MOS device <NUM>, which are connected to one another via their respective gates. The circuit <NUM> can be implemented in a discharge protection circuit. In addition, the gates of the MOS device <NUM> and the MOS device <NUM> can connect to the diode <NUM>. The source of the MOS device <NUM> can connect to the low voltage pin <NUM> and the drain of the MOS device <NUM> can connect to the high voltage pin <NUM>. Note that in some embodiments, the MOS device <NUM> shown in <FIG> can be implemented as an HV (High Voltage) MOS device. The MOS device <NUM> can be an HV or LV (Low Voltage) MOS device. In the configuration shown in <FIG>, the MOS device is shown as an LV device (but may be provided as an HV device in other configurations).

<FIG> depicts a schematic diagram of a circuit <NUM> having a back-to-back switch configuration (i.e., a back-to-back arrangement) with electrostatic discharge protection at the gate net that does not include a gate diode. That is, circuit <NUM> does not include the diode <NUM> that is utilized in circuit <NUM>. In circuit <NUM>, the resistor <NUM> can connect to the optional source diode <NUM> and the triggered electrostatic discharge protection element <NUM>, which can be configured as an AC-triggered electrostatic discharge protection element or a DC-triggered electrostatic discharge protection element. <FIG> thus illustrate the situation in which the switch can be configured from two MOS devices <NUM> and <NUM> in a back-to-back arrangement. This type of configuration can be implemented in the context of, for example, a USB switch (e.g., CC1/CC2). The circuit <NUM> can be implemented in a discharge protection circuit.

Thus, <FIG> illustrate a switch circuit configuration (respectively, with and without a diode for electrostatic discharge protection at the gate net), and <FIG> depict a double switch circuit configuration (a back-to-back arrangement or configuration, respectively with and without the gate diode, to facilitate electrostatic discharge protection at the gate net). <FIG> and <FIG>depict alternative embodiments of the configurations shown in <FIG>.

<FIG> depicts a process flow diagram of a method <NUM> of operating a discharge protection circuit. As shown at block <NUM>, the process can be initiated. Then, as indicated at block <NUM>, a step or operation can be implemented to produce a capacitively coupled current utilizing a capacitive coupling of a switch configured with the capacitive coupling between a gate and a drain of the switch. Next, as depicted at block <NUM>, a step or operation can be implemented to sink at least a part (or all) of an electrostatic discharge current via a gate network of the discharge protection circuit. As discussed previously, such a gate network can include at least the gate of the switch, a gate control element and a resistor connected to the gate and the gate control element. Thereafter, as illustrated at block <NUM>, the electrostatic discharge current is facilitated by an electrostatic discharge rail in the discharge protection circuit that connects to a diode coupled to the aforementioned gate and resistor. The discharge protection circuit may be the same as or similar to the discharge protection circuits discussed previously herein, and may be implemented in the context of a discharge protection system.

Based on the foregoing, it can be appreciated that the disclosed approach can employ a capacitive coupling (e.g., such as, the capacitors <NUM>, <NUM>, and <NUM> shown in <FIG>) that sinks a part of (or all of) the electrostatic discharge current via the disclosed gate net. This approach is particularly effective for fast electrostatic discharge events, such as specified by IEC <NUM>-<NUM>-<NUM>, since the coupling to the gate net is then the strongest. The disclosed gate network features an AC-triggered or DC-triggered electrostatic discharge protection element (e.g., the DC or AC triggered electrostatic discharge protection element <NUM>) that sinks the capacitively coupled current. Such an electrostatic discharge protection feature may not interfere with the gate network's functional operations.

An important benefit of the disclosed embodiments is the indirect clamping of the source side of the switch (since the source may not rise above the clamping voltage of the gate net minus the threshold voltage, Vth). Another benefit is that this approach may not load the data line, and therefore may not compromise a potentially high bandwidth performance of the switch.

The disclosed approach provides a solution that can protect circuits connected to, for example, a Type-C connector (e.g., "CC" pin). This approach can also be utilized to protect a circuit supply from surge damage. A combination of diode, resistor and a dedicated or shared rail clamped (which is AC and DC triggered) can facilitate the goal of electrostatic discharge protection in a manner that can limit the voltage rise at the source of the switch and can also allow for a smaller electrostatic discharge protection on the actual drain and source net of the switch, which in turn can facilitate a more aggressive bandwidth performance (e.g., less capacitance on the data line).

The disclosed approach can also avoid overvoltage at the gate net (e.g., when a DC protection is used), which can improve the overall robustness of the IC chip in which the circuit is deployed and reduces the risks of electrical overstress (EOS). Additionally, the disclosed solution can use the (parasitic) capacitances of the (HV) MOS switch device and is therefore relatively area efficient (i.e., certainly, in comparison with the additional area that may be needed for electrostatic discharge protection at the source side of the switch, if the disclosed approach is not applied).

The disclosed approach can also handle very fast electrostatic discharge transients, because of the direct capacitive coupling to the gate net. This also reduces the chances for electrical overstress (EOS). Additionally, the disclosed approach can clamp surge voltages at internal nodes of an IC chip and can also protect circuits facing pins with potentially high voltage slow surge. The disclosed approach additionally can reduce the need for an expensive external TVS (Transient Voltage Suppressor) or remove the need for an external TVS. The disclosed embodiments can be fully integrated and take up very little area.

Although the operations of the method(s) and elements of the circuit(s) and system(s) herein are shown and described in a particular order or configuration, the order of the operations and elements of the method, circuit and system may be altered so that certain operations or elements may be performed in an inverse or different order or arrangement or so that certain operations may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations or elements may be implemented in an intermittent and/or alternating manner.

Alternatively, embodiments of the invention and elements thereof may be implemented in hardware or in an implementation containing hardware and software elements. In embodiments that utilize software, the software may include but is not limited to firmware, resident software, microcode, etc..

Claim 1:
A discharge protection circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
a switch (SW) having a capacitive coupling between a gate and a drain of the switch, such that, in use, a capacitively coupled current flows between the gate and the drain;
a gate network comprising at least the gate of the switch, a gate control element (<NUM>) and a resistor (<NUM>) connected between the gate and the gate control element;
an electrostatic discharge, ESD, rail (<NUM>, <NUM>);
wherein the ESD rail is coupled to the gate either directly or via a diode (<NUM>), such that, in use, at least a part of an electrostatic discharge current is sunk via the capacitive coupling and the gate network;
wherein the ESD rail is coupled to a ground (<NUM>) via an ESD protection element (<NUM>).