Patent Description:
Currently, devices such as notebooks, mobile phones, and tablets have become common devices in people's daily life and working. These devices all need to be charged when battery power is about to be used up, to supplement power. Therefore, people need to carry charging cables and chargers of various devices, which brings many inconveniences.

Although a terminal such as a mobile phone or a tablet may be charged through a universal serial bus (universal serial bus, USB) interface of a notebook, currently, the notebook does not support a fast charging protocol used by a device such as the mobile phone or the tablet, and therefore, a charging speed is very low, and power cannot be quickly supplemented to the mobile phone, the tablet, or the like.

In the prior art, <CIT> relates to an electronic device and a charging control method; <CIT> relates to a charging system and a charging method for a mobile terminal; and <CIT> relates to a terminal and a charging method between terminals.

To resolve the foregoing technical problem, this application provides an electronic device, a device identification method, and a charging system. In the electronic device, a charging protocol chip is added to provide a fast charging function externally, and an external interface of the electronic device is electrically connected to only one of a processor and the charging protocol chip at a same time, so that when an external device is identified, the charging protocol chip and the processor do not interfere with each other. Therefore, the electronic device can implement fast charging externally without affecting identification of a USB <NUM> device.

According to a first aspect, this application provides an electronic device. The electronic device includes a processor, a controller, a charging protocol chip, an external interface, and a switch circuit. The processor, the charging protocol chip, and the external interface each include a data pin unit. The data pin unit of the processor, the data pin unit of the charging protocol chip, the data pin unit of the external interface, and the controller are separately electrically connected to the switch circuit. The controller is configured to control the switch circuit, so that the data pin unit of the external interface is connected to one of the data pin unit of the processor and the data pin unit of the charging protocol chip and is disconnected from the other of the data pin unit of the processor and the data pin unit of the charging protocol chip. The data pin unit may include one data pin, or may include a plurality of data pins. A first protocol identification channel may be formed between the data pin unit of the external interface and the data pin unit of the processor, and the first protocol identification channel is, for example, a USB <NUM> protocol identification channel. A second protocol identification channel may be formed between the data pin unit of the external interface and the data pin unit of the charging protocol chip, and the second protocol identification channel is, for example, an SCP/FCP protocol identification channel. The controller controls the switch circuit, so that when one of the first protocol identification channel and the second protocol identification channel is conducted, the other is disconnected. The first protocol includes a USB <NUM> protocol, and a second protocol includes an SCP/FCP fast charging protocol.

According to the electronic device in the first aspect, the charging protocol chip is added, so that a fast charging function can be provided to an external device. In addition, when the external device is electrically connected to the external interface, because only one of the processor and the charging protocol chip is electrically connected to the external interface, when identifying the external device or interacting with the external device, the charging protocol chip and the processor do not interfere with each other. Therefore, the electronic device can implement fast charging on the external device without affecting identification of a USB <NUM> device.

According to the first aspect or any implementation of the first aspect, the external interface is configured to electrically connect to an external device. The processor is configured to perform first protocol identification on the external device when the external interface is electrically connected to the external device and the data pin unit of the processor is connected to the pin unit of the external interface. The charging protocol chip is configured to perform second protocol identification on the external device when the external interface is electrically connected to the external device and the data pin unit of the charging protocol chip is connected to the pin unit of the external interface. The processor and the charging protocol chip are separately electrically connected to the controller, and are configured to send, to the controller, an indication indicating that the protocol identification succeeds or fails. The controller is configured to: after receiving an indication that is sent by the processor and that indicates that the first protocol identification succeeds, continue to control the switch circuit, so that the data pin unit of the external interface is connected to the data pin unit of the processor and is disconnected from the data pin unit of the charging protocol chip; and control the switch circuit after receiving an indication that is sent by the processor and that indicates that the first protocol identification fails, so that the data pin unit of the external interface is disconnected from the data pin unit of the processor and is connected to the data pin unit of the charging protocol chip. The controller is configured to: after receiving an indication that is sent by the charging protocol chip and that indicates that the second protocol identification succeeds, continue to control the switch circuit, so that the data pin unit of the external interface is connected to the data pin unit of the charging protocol chip and is disconnected from the data pin unit of the processor; and control the switch circuit after receiving an indication that is sent by the charging protocol chip and that indicates that the second protocol identification fails, so that the data pin unit of the external interface is disconnected from the data pin unit of the charging protocol chip and is connected to the data pin unit of the processor. In this way, the controller may control the switch circuit based on an indication indicating that the processor or the charging protocol chip succeeds or fails in the identification. When the processor or the charging protocol chip succeeds in the identification, the switch circuit is controlled to continue to conduct a corresponding protocol identification channel; and when the identification fails, the switch circuit is controlled to switch to another protocol identification channel, so that the electronic device can implement fast charging on the external device without affecting identification of a USB <NUM> device.

According to the first aspect or any implementation of the first aspect, the controller controls the switch circuit, so that the data pin unit of the external interface is connected to the data pin unit of the charging protocol chip and is disconnected from the data pin unit of the processor; and after receiving the indication that is sent by the charging protocol chip and that indicates that the second protocol identification fails, the controller controls the switch circuit, so that the data pin unit of the external interface is disconnected from the data pin unit of the charging protocol chip and is connected to the data pin unit of the processor. The controller controls the switch circuit to first connect the external interface and the charging protocol chip by default, to first perform the second protocol (for example, a charging protocol) identification on the external device. Then, after the second protocol identification fails, the first protocol identification is performed on the external device. In this way, because the second protocol identification is first performed on the external device, when a second protocol has a duration requirement for an identification process, the following case may be avoided: protocol identification fails or an error occurs in protocol identification because identification duration exceeds duration specified for the second protocol identification.

According to the first aspect or any implementation of the first aspect, the electronic device further includes a voltage conversion circuit and a battery, and the external interface further includes a power-supply pin. The battery is electrically connected to the power-supply pin of the external interface by using the voltage conversion circuit. The charging protocol chip is connected to the voltage conversion circuit, and is configured to send an enable signal to the voltage conversion circuit after the charging protocol chip succeeds in the protocol identification, so that the voltage conversion circuit provides a specified voltage to the power-supply pin of the external interface. In this way, the electronic device may provide a required charging voltage based on a requirement of a to-be-charged device, to implement fast charging on the external device.

According to the first aspect or any implementation of the first aspect, the controller is further configured to: after receiving the indication that is sent by the charging protocol chip and that indicates that the second protocol identification succeeds, obtain power information of the battery, and send, to the charging protocol chip based on the power information of the battery, an indication indicating to enable fast charging or not to enable fast charging. In this way, it may be determined, based on battery power of the electronic device, whether to perform fast charging on the external device, to avoid that fast charging cannot be performed or use of the electronic device is affected due to low power.

According to the first aspect or any implementation of the first aspect, when power of the battery is greater than a specified threshold, the controller sends an indication indicating to enable fast charging to the charging protocol chip; and when the power of the battery is less than or equal to the specified threshold, the controller sends an indication indicating not to enable fast charging to the charging protocol chip. In this way, it may be determined, based on battery power of the electronic device, whether to perform fast charging on the external device, to avoid that fast charging cannot be performed or use of the electronic device is affected due to low power.

According to the first aspect or any implementation of the first aspect, when the external device is a device supporting a first protocol, and after the external device is removed from the external interface, the processor is further configured to send, to the controller after the external device is removed, an indication indicating that the external device is removed; and the controller controls the switch circuit based on the indication indicating that the external device is removed, so that the data pin unit of the external interface is disconnected from the data pin unit of the processor and is connected to the data pin unit of the charging protocol chip. In this way, after the external device is removed, the controller controls the switch circuit to first connect the external interface and the charging protocol chip by default, to first perform the second protocol (for example, a charging protocol) identification on the external device, so that when a second protocol has a duration requirement for an identification process, the following case may be avoided: protocol identification fails or an error occurs in protocol identification because identification duration exceeds duration specified for the second protocol identification.

According to the first aspect or any implementation of the first aspect, the switch circuit includes a switch chip, and the data pin unit of the processor, the data pin unit of the charging protocol chip, the data pin unit of the external interface, and the controller are separately electrically connected to the switch chip. In this way, an electrical connection between the data pin units of the external interface, the processor, and the charging protocol chip can be controlled by using one switch chip, to ensure that the processor and the charging protocol chip do not interfere with each other in a process of identifying an external device.

According to the first aspect or any implementation of the first aspect, the switch circuit includes a first switch unit and a second switch unit. The data pin unit of the processor, the data pin unit of the external interface, and the controller are separately electrically connected to the first switch unit, and the controller is configured to control the first switch unit, so that the data pin unit of the external interface is connected to or disconnected from the data pin unit of the processor. The data pin unit of the charging protocol chip, the data pin unit of the external interface, and the controller are separately electrically connected to the second switch unit, and the controller is configured to control the second switch unit, so that the data pin unit of the external interface is connected to or disconnected from the data pin unit of the charging protocol chip. In this way, the first switch unit and the second switch unit are respectively used to control an electrical connection between the processor and the external interface and an electrical connection between the charging protocol chip and the external interface, to ensure that the processor and the charging protocol chip do not interfere with each other in a process of identifying an external device.

According to the first aspect or any implementation of the first aspect, the first switch unit and the second switch unit each include a switch chip. The first switch unit and the second switch unit each can implement a switch chip, and a proper chip may be selected based on a requirement to control the electrical connection between the external interface and each of the processor and the charging protocol chip.

According to the first aspect or any implementation of the first aspect, the data pin unit includes a first data pin and a second data pin. The switch circuit includes a first switch unit to a fourth switch unit. The first data pin of the processor, the first data pin of the external interface, and the controller are separately electrically connected to the first switch unit, and the controller is configured to control the first switch unit, so that the first data pin of the external interface is connected to or disconnected from the first data pin of the processor. The second data pin of the processor, the second data pin of the external interface, and the controller are separately electrically connected to the second switch unit, and the controller is configured to control the second switch unit, so that the second data pin of the external interface is connected to or disconnected from the second data pin of the processor. The first data pin of the charging protocol chip, the first data pin of the external interface, and the controller are separately electrically connected to the third switch unit, and the controller is configured to control the third switch unit, so that the first data pin of the external interface is connected to or disconnected from the first data pin of the charging protocol chip. The second data pin of the charging protocol chip, the second data pin of the external interface, and the controller are separately electrically connected to the fourth switch unit, and the controller is configured to control the fourth switch unit, so that the second data pin of the external interface is connected to or disconnected from the second data pin of the charging protocol chip. In this way, when the data pin unit includes two data pins, the electrical connection between the processor and the external interface and the electrical connection between the charging protocol chip and the external interface may be separately controlled by using four switch units, to ensure that the processor and the charging protocol chip do not interfere with each other in a process of identifying an external device.

According to the first aspect or any implementation of the first aspect, the first switch unit to the fourth switch unit each include a switch chip or a MOS transistor. In this way, a proper switch chip or MOS transistor may be selected based on a requirement to control the electrical connection between the external interface and each of the processor and the charging protocol chip.

According to the first aspect or any implementation of the first aspect, the first switch unit includes a PMOS transistor, the second switch unit includes a PMOS transistor, the third switch unit includes an NMOS transistor, and the fourth switch unit includes an NMOS transistor. In this way, the first switch unit and the second switch unit have a same type of transistor, the third switch unit and the fourth switch unit have a same type of transistor, and the first switch unit is opposite to the second switch unit. Therefore, the four switch units can be controlled by using one switch signal or a same switch signal. For example, a same high-level signal can be used to turn on the third and fourth switch units and turn off the first and second switch units, and a same low-level signal can be used to turn off the third and fourth switch units and turn on the first and second switch units, so that a control process is simplified.

According to the invention, the first protocol includes a USB <NUM> protocol, and a second protocol includes an SCP/FCP fast charging protocol. In this way, the electronic device can implement SCP/FCP fast charging on an external device without affecting identification of a USB <NUM> device.

According to the first aspect or any implementation of the first aspect, the data pin unit includes a DP pin or a DM pin. In this way, when protocol communication is performed by using the DP pin and the DM pin, the electronic device can implement fast charging on an external device without affecting identification of a USB <NUM> device.

According to a second aspect, this application provides a device identification method, applied to the electronic device in the first aspect. The device identification method includes:
The controller controls the switch circuit, so that the data pin unit of the external interface is connected to one of the data pin unit of the processor and the data pin unit of the charging protocol chip and is disconnected from the other of the data pin unit of the processor and the data pin unit of the charging protocol chip.

One of the processor and the charging protocol chip identifies a type of an external device connected to the external interface, where the type of the external device includes, for example, an external device supporting a first protocol and an external device supporting a second protocol. For example, the external device includes a USB <NUM> device and a to-be-charged terminal.

After one of the processor and the charging protocol chip fails in the identification, the controller controls the switch circuit, so that the data pin unit of the external interface is disconnected from one of the data pin unit of the processor and the data pin unit of the charging protocol chip and is connected to the other of the data pin unit of the processor and the data pin unit of the charging protocol chip.

The other of the processor and the charging protocol chip identifies the type of the external device connected to the external interface. The charging protocol chip uses an SCP/FCP charging protocol identification. The processor uses a USB <NUM> protocol identification.

According to the device identification method in the second aspect, when the external device is electrically connected to the external interface, because only one of the processor and the charging protocol chip is electrically connected to the external interface, when identifying the external device or interacting with the external device, the charging protocol chip and the processor do not interfere with each other. Therefore, the electronic device can implement fast charging on the external device without affecting identification of a USB <NUM> device.

According to the second aspect or any implementation of the second aspect, the controller controls the switch circuit, so that the data pin unit of the external interface is connected to the data pin unit of the charging protocol chip and is disconnected from the data pin unit of the processor. The charging protocol chip identifies the type of the external device. After the charging protocol chip fails in the identification, the controller controls the switch circuit, so that the data pin unit of the external interface is disconnected from one of data pin units of the charging protocol chip and is connected to the data pin unit of the processor. The processor identifies the type of the external device. In this way, because second protocol identification is first performed on the external device, when a second protocol has a duration requirement for an identification process, the following case may be avoided: protocol identification fails or an error occurs in protocol identification because identification duration exceeds duration specified for the second protocol identification.

According to the second aspect or any implementation of the second aspect, when the external device connected to the external interface is of a type corresponding to the processor, the device identification method further includes: After the external device is removed, the processor sends, to the controller, an indication indicating that the external device is removed; and after receiving the indication indicating that the external device is removed, the controller controls the switch circuit, so that the data pin unit of the external interface is connected to the data pin unit of the charging protocol chip and is disconnected from the data pin unit of the processor. In this way, after the external device is removed, the controller controls the switch circuit to first connect the external interface and the charging protocol chip by default, to first perform the second protocol (for example, a charging protocol) identification on the external device, so that when a second protocol has a duration requirement for an identification process, the following case may be avoided: protocol identification fails or an error occurs in protocol identification because identification duration exceeds duration specified for the second protocol identification.

According to a third aspect, this application provides a charging system, including the electronic device in the first aspect and a terminal. The terminal includes a charging interface and a battery. The charging interface is electrically connected to the external interface. The electronic device charges the battery in the terminal through the external interface and the charging interface. In this way, the terminal may be quickly charged by using the electronic device, thereby improving charging convenience.

According to a fourth aspect, this application provides a chip. The chip includes a processing circuit and a transceiver pin. The transceiver pin and the processing circuit communicate with each other through an internal connection channel. The processing circuit performs the method in the second aspect or any possible implementation of the second aspect, to control a receive pin to receive a signal, and to control a transmit pin to send a signal.

Clearly, the described embodiments are some rather than all of the embodiments of this application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of this application without creative efforts shall fall within the protection scope of this application.

In this specification, the term "and/or" is merely used to describe an association relationship between associated objects, and indicates that three relationships may exist. For example, "A and/or B" may indicate the following three cases: Only A exists, both A and B exist, and only B exists.

The terms "first", "second", and the like in the specification and claims of the embodiments of this application are used to distinguish between different objects, and are not used to describe a specific sequence of the objects. For example, a first target object, a second target object, and the like are used to distinguish between different target objects, but are not used to describe a specific sequence of the target objects.

In the embodiments of this application, words such as "an example" or "for example" are used to represent giving an example, an illustration, or a description. Any embodiment or design solution described as "an example" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Exactly, use of the words such as "an example" or "for example" is intended to present a related concept in a specific manner.

In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more. For example, "a plurality of processing units" means two or more processing units, and "a plurality of systems" means two or more systems.

<FIG> is an example schematic diagram of an application scenario. Referring to <FIG>, for example, an electronic device <NUM> may be a device such as a notebook computer, and an external interface such as a Type-C universal serial bus (universal serial bus, USB) interface is configured on the electronic device <NUM>. The electronic device <NUM> may be connected to an external device <NUM> through the external interface. Referring to (<NUM>) in <FIG>, for example, the external device <NUM> may be a to-be-charged terminal such as a mobile phone or a tablet. Referring to (<NUM>) in <FIG>, for example, the external device <NUM> may alternatively be a USB <NUM> device such as a USB flash drive or a removable hard disk. The USB <NUM> device is a storage device or an electronic device that supports a USB <NUM> protocol. In the application scenario shown in <FIG>, the electronic device <NUM> may quickly charge a to-be-charged terminal <NUM> such as a mobile phone or a tablet through the external interface, or may communicate with or exchange data with an electronic device, such as a USB flash drive or a removable hard disk, that is used as a hard disk, or another type of USB <NUM> device <NUM>, to implement functions such as communication and data reading or storage.

In the application scenario shown in <FIG>, the electronic device <NUM> may provide a fast charging function for the to-be-charged terminal <NUM> such as a mobile phone or a tablet. In this application, fast charging means performing charging in a charging mode with charging power greater than <NUM> W, for example, the charging power may be <NUM> W, <NUM> W, <NUM> W, <NUM> W, or <NUM> W. In an implementation, the electronic device <NUM> supports a super charge protocol/fast charge protocol (Super Charge Protocol, SCP)/Fast Charger Protocol, FCP). Through the external interface, the electronic device <NUM> may perform fast charging on the to-be-charged terminal <NUM> that supports the SCP/FCP protocol.

<FIG> is an example schematic diagram of a structure of the electronic device <NUM> applied to the application scenario shown in <FIG>. Referring to <FIG>, the electronic device <NUM> includes a processor <NUM>, a controller <NUM>, a charging protocol chip <NUM>, an external interface <NUM>, a voltage conversion circuit <NUM>, and a battery <NUM>. The external interface <NUM> may be, for example, a type-C USB interface. In the electronic device <NUM> shown in <FIG>, the processor <NUM> includes a first data pin <NUM> (for example, DP or D+) and a second data pin (for example, DM or D-). The charging protocol chip <NUM> includes a first data pin <NUM> (for example, DP or D+) and a second data pin <NUM> (for example, DM or D-). The external interface <NUM> includes a first data pin <NUM> (for example, DP or D+) and a second data pin <NUM> (for example, DM or D-). In an aspect, the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM> are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the processor <NUM> to form a first protocol identification channel. The first protocol identification channel is a USB <NUM> device protocol identification channel. In another aspect, the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM> are alternatively respectively connected to the first data pin <NUM> and the second data pin <NUM> of the charging protocol chip <NUM> to form a second protocol identification channel. The second protocol identification channel is a fast charging protocol identification channel.

Based on the USB <NUM> protocol, the first data pin <NUM> and the second data pin <NUM> of the processor <NUM> are separately grounded by using, for example, a pull-down resistor R of <NUM> ohms. Based on the SCP/FCP protocol, the first data pin <NUM> and the second data pin <NUM> of the charging protocol chip <NUM> are separately grounded by using, for example, a pull-down resistor R of <NUM> ohms. After the external device <NUM> accesses the external interface <NUM>, in both the USB <NUM> protocol and the SCP/FCP protocol of the electronic device <NUM>, device identification is performed by using a configured level of a pull-down resistor in the electronic device <NUM>.

Specifically, for example, the processor <NUM> detects levels of the first data pin <NUM> and the second data pin <NUM> of the processor <NUM> to determine whether a device that accesses the external interface <NUM> is a USB <NUM> device. The charging protocol chip <NUM> detects levels of the first data pin <NUM> and the second data pin <NUM> of the charging protocol chip <NUM> to determine whether a device that accesses the external interface <NUM> is a terminal device that supports the SCP/FCP protocol.

<FIG> is an example schematic diagram of a principle of identifying a USB <NUM> device. Referring to (<NUM>) in <FIG>, data pins DP and DM of the processor <NUM> are separately grounded by using a pull-down resistor. Referring to (<NUM>) in <FIG>, a USB high-speed/full-speed device includes a USB <NUM> protocol chip and data pins DP and DM, and the DP pin is connected to a power supply Vcc by using a pull-up resistor. Referring to (<NUM>) in <FIG>, a USB low-speed device includes a USB <NUM> protocol chip and data pins DP and DM, and the DM pin is connected to a power supply Vcc by using a pull-up resistor. A resistance value of the pull-up resistor is, for example, <NUM> KΩ.

When the electronic device <NUM> is not connected to the external device <NUM>, pull-down resistors connected to the DP pin and the DM pin make voltages of the two data lines to be relative to the ground (refer to (<NUM>) in <FIG>). After a full-speed/high-speed device is connected to the electronic device <NUM>, the pull-down resistor connected to the data pin DP of the processor <NUM> and a pull-up resistor connected to a data pin DP of the external device <NUM> constitute a voltage divider. Because a resistance value of the pull-down resistor is <NUM> KΩ and a resistance value of the pull-up resistor is <NUM> KΩ, a direct-current high-level voltage whose value is (Vcc*<NUM>/(<NUM>+<NUM>)) appears on the data pin DP of the processor <NUM>. When the processor <NUM> detects that the voltage of the DP pin approaches a high level and the DM pin remains grounded, it can be determined that a full-speed/high-speed USB <NUM> device is accessed. Correspondingly, when the processor <NUM> detects that a voltage of the DM pin approaches a high level and the DP pin remains grounded, it can be determined that a low-speed USB <NUM> device is accessed.

It should be understood that the foregoing USB <NUM> device identification process/method is merely an example. In the embodiments of this application, identification may be performed in another manner based on the foregoing principle or a similar principle.

In an SCP protocol detection process, whether a charging interface is a dedicated charging interface (a DCP interface) is first detected through BC1. The following describes an example of an SCP protocol detection principle with reference to <FIG>.

<FIG> are example schematic diagrams of SCP protocol identification principles. The charging protocol BC1. <NUM> (Battery Charging Specification <NUM>) defines three interface types:
Standard downstream port (SDP, Standard Downstream Port): This type of interface supports a USB protocol. In a case of suspending, a maximum current is <NUM> mA; and in a case of a connected but non-suspended apparatus, a maximum current is <NUM> mA. DP and DM pins of the interface each have a resistor of <NUM> connected to the GND.

Dedicated charging port (DCP, Dedicated Charging Port): This type of port does not support any data transmission, but can provide a current greater than <NUM> A. This type of interface supports a wall charger and an in-vehicle charger that have a high charging capability, which do not need to be enumerated.

Charging downstream port (CDP, Charging Downstream Port): This type of interface supports both high-current charging (up to <NUM> A) and data transmission fully compatible with USB <NUM>. DP and DM pins of the interface each have a <NUM> kΩ pull-down resistor necessary for communication, and also have an internal circuit for switching in a charger detection phase. The internal circuit allows a device to distinguish the CDP from other types of ports.

<FIG> shows a working mode (a dashed-line area in <FIG>) used when data detection is performed after a USB interface of a terminal PD (portable device, for example, a to-be-charged terminal <NUM>) is connected to an external interface. For example, a data detection process is as follows: After VBUS is valid, the terminal PD enables a current source IDP_SRC of a DP pin and a pull-down resistor of a DM pin. Then, the terminal PD detects the DP pin, where detection duration lasts TDCD_DBNC (Data contact detect debounce min=<NUM>), and further disables the current source IDP_SRC of the DP pin and the pull-down resistor of the DM pin. In this process, if the terminal PD is not connected to an external interface (for example, the external interface <NUM> of the electronic device <NUM>), the DP pin of the terminal PD remains at a high level. A minimum value of the current source IDP_SRC (<NUM> uA) is required to be capable of ensuring that the DP pin remains at a level VLGC_HI (for example, <NUM>~<NUM> V) in a worst leakage current case (RDAT_LKG and VDAT_LKG). When the terminal is connected to an SDP interface, the DP pin is pulled down by a pull-down electron RDP_DWN of the SDP interface. A maximum value of the current source IDP_SRC (<NUM> uA) is required to be capable of ensuring that the DP pin remains at VLGC_LOW (Logic Low <NUM>~<NUM> V) in a worst leakage current case (RDAT_LKG, VDAT_LKG, and RDP_DWN). Therefore, after VBUS is valid, the current source IDP_SRC of the DP pin and the pull-down resistor of the DM pin are enabled, and a level of the DP pin can be detected to determine whether the external interface connected to the terminal PD supports a data protocol.

<FIG> shows a working mode (a dashed-line area in <FIG>) used when main detection is performed after a USB interface of a terminal PD is connected to a DCP interface. For example, a main detection process is as follows: The terminal device PD enables a voltage source VDP_SRC (for example, <NUM>~<NUM> v) of a DP pin and a current source IDM_SINK (for example, <NUM>~<NUM>µA) of a DM pin. The DP pin and the DM pin are short-circuited through a short-circuit resistor RDCP_DAT (Dedicated Charging Port resistance across D+/- max=<NUM>Ω) in the DCP interface. The terminal PD detects whether a voltage of the DM reaches VDP_SRC. The terminal PD compares the voltage of the DM with VDAT_REF (for example, <NUM>~<NUM> v) in a voltage comparator of the DM pin. If the voltage of the DM pin is greater than VDAT_REF, it can be determined that the terminal PD is connected to a charging interface, and then secondary detection is performed to determine whether the terminal PD is connected to a DCP interface or a CDP interface.

<FIG> shows a working mode (a dashed-line area in <FIG>) used when secondary detection is performed after a USB interface of a terminal PD is connected to a DCP interface. For example, a secondary detection process is as follows: The terminal PD enables a voltage source VDM_SRC on a DM pin, enables a current source IDP_SINK, and then compares a voltage of a DP pin and a voltage of VDAT_REF. Because the DP pin and the DM pin are short-circuited through a short-circuit resistor RDCP_DAT in the DCP interface, a voltage of the voltage source VDM_SRC makes VDAT_REF<DP<VDM_SRC. Therefore, when the terminal PD detects that VDAT_REF<the voltage of the DP pin, it can be determined that the terminal is connected to the DCP interface.

In conclusion, it can be learned that in a process of USB <NUM> device protocol identification and SCP protocol identification, both a level of the first data pin and a level of the second data pin of the external interface <NUM> change. In the electronic device shown in <FIG>, the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM> are directly connected to the first data pin and the second data pin of each of the processor <NUM> and the charging protocol chip <NUM> (that is, both the first protocol identification channel and the second protocol identification channel are in a conductive state), and a same pull-down resistor is used. As a result, a pull-down resistor of one party affects protocol identification of the other party. For example, if an external device that accesses the external interface <NUM> is a to-be-charged terminal <NUM> such as a mobile phone, the processor <NUM> may also detect a change in levels of the first data pin and the second data pin of the processor. As a result, the external device is identified as a USB <NUM> device, or identification fails due to interference caused to charging protocol identification of the external device. Consequently, the electronic device <NUM> cannot correctly identify a USB <NUM> device, and cannot quickly charge a to-be-charged terminal such as a mobile phone.

Based on this, the embodiments of this application provide an electronic device, a device identification method, and a charging system. The charging system includes the electronic device and a terminal, and the electronic device can charge the terminal. A charging protocol chip is added to the electronic device to provide a fast charging function for the terminal, and a switch circuit is added to control conduction and disconnection of a USB <NUM> device protocol identification channel and a fast charging protocol identification channel, so that only one of the USB <NUM> device protocol identification channel and the fast charging protocol identification channel is conducted at a same time, to avoid mutual interference between the two protocol identification channels. In this way, an external interface can perform an SCP fast charging function without affecting identification of a USB <NUM> device. The electronic device may be a device configured with an external interface, for example, a notebook computer, an all-in-one computer, or a desktop computer. The terminal may be a to-be-charged terminal such as a mobile phone, a notebook computer, a tablet computer, a personal digital assistant (personal digital assistant, PDA for short), an in-vehicle computer, a television, an intelligent wearable device (for example, a smartwatch), a media player, or a smart home device. A specific form of the terminal is not specifically limited in the embodiments of this application. For ease of description, an example in which the electronic device is a notebook computer, and the terminal is a mobile phone is used for description in all the embodiments of this application.

The problem mentioned above exists when any chip that performs charging protocol communication by using a first data pin and a second data pin implements USB <NUM> support and fast charging support at a same external interface.

It should be further understood that all the foregoing examples are described by using an example in which an external interface is a type-C USB interface and using a DP pin and a DM pin of the type-C USB interface as an example. However, this constitutes no limitation on this application, provided that any interface that implements a data communication function and a protocol identification function by using a pin in the interface falls within the protection scope of the embodiments of this application. The following also uses the type-C USB interface as an example for description.

<FIG> is an example schematic diagram of a structure of an electronic device according to an embodiment of this application. Referring to <FIG>, the electronic device <NUM> includes a processor <NUM>, a controller <NUM>, a charging protocol chip <NUM>, an external interface <NUM>, a voltage conversion circuit <NUM>, a battery <NUM>, and a switch circuit <NUM>.

It should be understood that, the electronic device <NUM> may further include one or more of modules such as a power management module, an antenna, a wireless communication module, a mouse, an indicator, a keyboard, a camera, a display, an audio module, a speaker, a sound box interface, and a microphone, or may further include another module. This is not specifically limited herein.

The processor <NUM> may include one or more processing units. For example, the processor <NUM> may include an application processor, a modem processor, a graphics processing unit GPU, an ISP, a memory, a video codec, a DSP, a baseband processor, and/or an NPU. Different processing units may be independent components or may be integrated into one or more processors.

A memory may be further disposed in the processor <NUM>, and is configured to store instructions and data. In some embodiments, the memory in the processor <NUM> is a cache. The memory may store instructions or data just used or cyclically used by the processor <NUM>. If the processor <NUM> needs to use the instructions or the data again, the processor <NUM> may directly invoke the instructions or the data from the memory. This avoids repeated access and reduces waiting time of the processor <NUM>, thereby improving system efficiency. The interface may include an inter-integrated circuit I2C interface, an inter-integrated circuit sound I2S interface, an eSPI interface, a PCM interface, a UART interface, an MIPI, a GPIO interface, a USB interface, and/or the like.

In this embodiment of this application, the processor <NUM> includes a first data pin <NUM> and a second data pin <NUM>. The processor <NUM> is connected to the external interface <NUM> by using the first data pin <NUM> and the second data pin <NUM>, to exchange data with or communicate with an external device. For example, based on a USB <NUM> protocol, the first data pin <NUM> and the second data pin <NUM> of the processor <NUM> are separately grounded by using, for example, a pull-down resistor R of <NUM> ohms.

The controller <NUM> is, for example, an embedded controller EC, and is configured to implement functions such as keyboard control, a touchpad, power management, and fan control. The controller <NUM> may include independently running software, which is stored in a non-volatile medium of the controller <NUM>. In some embodiments, the controller <NUM> may include one or more interfaces. The interface may include a general-purpose input/output (GPIO) interface, an eSPI (Enhanced Serial Peripheral, enhanced serial peripheral) interface, an inter-integrated circuit I2C interface, and the like. The controller <NUM> may be connected to and communicate with the processor <NUM> through, for example, the eSPI interface and an eSPI bus. The controller <NUM> may be further connected to the switch circuit <NUM> through, for example, the GPIO interface, to output a control signal to the switch circuit <NUM> to control the switch circuit <NUM>. The controller <NUM> may be further connected to the charging protocol chip <NUM> through, for example, the inter-integrated circuit I2C interface, to communicate with the charging protocol chip <NUM>.

The charging protocol chip <NUM> is, for example, a fast charging protocol chip that supports an SCP protocol, and is configured to perform fast charging protocol identification and charging communication. The charging protocol chip <NUM> includes a first data pin <NUM> and a second data pin <NUM>. The charging protocol chip <NUM> is connected to the external interface <NUM> by using the first data pin <NUM> and the second data pin <NUM>, to quickly charge an external device. For example, based on an SCP/FCP protocol, the first data pin <NUM> and the second data pin <NUM> of the charging protocol chip <NUM> are separately grounded by using, for example, a pull-down resistor R of <NUM> ohms.

The charging protocol chip <NUM> may include one or more interfaces. The interface may include an inter-integrated circuit I2C interface and the like. The charging protocol chip <NUM> is connected to the controller <NUM> through, for example, the I2C interface and an I2C bus. The charging protocol chip <NUM> may send, to the controller <NUM>, an indication or a signal that indicates that fast charging protocol identification succeeds or fails. The charging protocol chip <NUM> is further connected to the voltage conversion circuit <NUM>, and is configured to send an enable signal to the voltage conversion circuit <NUM> after fast charging protocol identification succeeds, so that the voltage conversion circuit <NUM> outputs, to an external port, a charging voltage required by a terminal.

The external interface <NUM> may be, for example, a type-C USB interface. The external interface <NUM> includes a first data pin <NUM> and a second data pin <NUM>. For example, the external interface <NUM> further includes a power-supply pin VBUS and a communication pin. In an aspect, the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM> are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the processor <NUM> to form a first protocol identification channel (that is, a USB <NUM> device protocol identification channel). In another aspect, the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM> are alternatively respectively connected to the first data pin <NUM> and the second data pin <NUM> of the charging protocol chip <NUM> to form a second protocol identification channel (that is, a fast charging protocol identification channel).

The battery <NUM> supplies power to the external interface <NUM> by using the voltage conversion circuit <NUM>, to supply power to or charge an external device. The battery <NUM> further supplies power to the processor <NUM>, the controller <NUM>, the charging protocol chip <NUM>, and the like.

The switch circuit <NUM> is disposed between the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM> and the first data pin and the second data pin of each of the processor <NUM> and the charging protocol chip <NUM>, and is connected to the controller <NUM>. Under control of the controller <NUM>, the switch circuit <NUM> enables only one of the first protocol identification channel and the second protocol identification channel to be conducted at a same time, to avoid mutual interference between the two protocol identification channels. In this embodiment of this application, under control of the controller <NUM>, the switch circuit <NUM> considers by default that the second protocol identification channel is conducted, and after fast charging protocol identification fails, disconnects the second protocol identification channel, and conducts the first protocol identification channel. Subsequently, USB <NUM> device identification is performed. In this way, under action of the switch circuit <NUM> and the controller <NUM>, after an external device accesses the external interface <NUM>, the electronic device <NUM> may first perform charging protocol identification and then perform USB <NUM> device identification. This not only enables the external interface <NUM> to support both a USB <NUM> device and a fast charging function, but also avoids interference between identification of a USB <NUM> device and identification of a to-be-charged terminal, thereby improving accuracy and a speed of identifying an external device. In other words, when the electronic device <NUM> is used, a terminal that supports the SCP protocol or the like can be quickly charged through the external interface without affecting identification of a USB <NUM> device.

The following describes in detail a process/method for identifying an external device by the electronic device <NUM>.

<FIG> is an example schematic diagram of a connection between an electronic device and a to-be-charged terminal according to an embodiment of this application. Referring to <FIG>, the external interface <NUM> includes a first data pin <NUM> (for example, DP), a second data pin <NUM> (for example, DM), a first communication pin <NUM> (for example, CC1), a second communication pin <NUM> (for example, CC2), and a power-supply pin <NUM> (for example, a VBUS pin). A switch circuit used to make the first data pin <NUM> and the second data pin <NUM> short-circuited is disposed in the charging protocol chip <NUM>. The first communication pin <NUM> and the second communication pin <NUM> are connected to a power supply VCC (for example, <NUM> V) by using a pull-up resistor. A to-be-charged terminal <NUM> includes a charging protocol chip <NUM>, a battery <NUM>, and a charging interface <NUM>. The charging interface <NUM> includes a first data pin <NUM> (for example, DP), a second data pin <NUM> (for example, DM), a first communication pin <NUM> (for example, CC1), a second communication pin <NUM> (for example, CC2), and a power-supply pin <NUM> (for example, a VBUS pin). The first communication pin <NUM> and the second communication pin <NUM> are grounded by using a pull-down resistor.

The controller <NUM> controls the switch circuit <NUM> to enable, by default, a second protocol channel between the charging protocol chip <NUM> and the first data pin <NUM> (for example, the DP) and the second data pin <NUM>. After the to-be-charged terminal <NUM> accesses the electronic device <NUM>, that is, after the charging interface <NUM> of the to-be-charged terminal <NUM> is connected to the external interface <NUM> of the electronic device <NUM>, the power-supply pin <NUM> of the electronic device <NUM> is connected to the power-supply pin <NUM> of the to-be-charged terminal <NUM> to form a power-supply channel or a charging channel. The electronic device <NUM> may supply power to the to-be-charged terminal <NUM> through the channel. The first data pin <NUM> and the second data pin <NUM> of the electronic device <NUM> are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the to-be-charged terminal <NUM> to form a protocol channel. The electronic device <NUM> performs protocol communication with the to-be-charged terminal <NUM> through protocol channel. The first communication pin <NUM> and the second communication pin <NUM> of the electronic device <NUM> are respectively connected to the first communication pin <NUM> and the second communication pin <NUM> of the to-be-charged terminal <NUM> to form a handshake channel. The electronic device <NUM> completes a handshake with the to-be-charged terminal <NUM> through the handshake protocol channel.

For example, in this embodiment of this application, the charging protocol chip <NUM> and the charging protocol chip <NUM> use an SCP protocol. After the to-be-charged terminal <NUM> accesses the electronic device <NUM>, the electronic device <NUM> completes a handshake with the to-be-charged terminal <NUM> (that is, the charging protocol chip <NUM> completes a handshake with the charging protocol chip <NUM>) through the handshake channel, and then provides the power-supply pin/power-supply channel with, for example, a Vbus voltage of <NUM> V. A process of a handshake between the electronic device <NUM> and the to-be-charged terminal <NUM> may be completed by using various proper handshake protocols. For example, a pull-up resistor is connected to each of the first communication pin <NUM> and the second communication pin <NUM> of the electronic device <NUM>, and a pull-down resistor is connected to each of the first communication pin <NUM> and the second communication pin <NUM> of the to-be-charged terminal <NUM>. Before the electronic device <NUM> is connected to the to-be-charged terminal <NUM>, the power-supply pin <NUM> of the electronic device <NUM> has no voltage output. After the electronic device <NUM> is connected to the to-be-charged terminal <NUM>, the first communication pin <NUM> and the second communication pin <NUM> of the electronic device <NUM> are respectively connected to the first communication pin <NUM> and the second communication pin <NUM> of the to-be-charged terminal <NUM> to form a voltage divider. The charging protocol chip <NUM> detects levels of the first communication pin <NUM> and the second communication pin <NUM> to detect the pull-down resistors of the first communication pin <NUM> and the second communication pin <NUM> of the to-be-charged terminal <NUM>, to determine whether the to-be-charged terminal <NUM> is connected to the external interface <NUM>. Then, the electronic device <NUM> turns off a switch (not shown in <FIG>) of the power-supply pin <NUM>, and outputs a Vbus power supply of, such as <NUM> V, to the to-be-charged terminal <NUM>.

After the electronic device <NUM> completes a handshake with the to-be-charged terminal <NUM> through the handshake channel, the charging protocol chip <NUM> turns off the switch circuit used to make the first data pin <NUM> and the second data pin <NUM> short-circuited, so that the first data pin <NUM> and the second data pin <NUM> are short-circuited. The to-be-charged terminal <NUM> identifies, based on a BC1. <NUM> protocol (Battery Charging v1. <NUM>), whether the electronic device <NUM> is a DCP (Dedicated Charging Port, dedicated charging port) device (an SCP fast charging protocol needs to first identify, by using the BC1. <NUM> protocol, whether the electronic device <NUM> is a DCP device).

For example, an identification process is as follows: After being powered on the power-supply pin <NUM>, the to-be-charged terminal <NUM> first performs data connection detection. For a data connection detection process, refer to the foregoing description provided with reference to <FIG>. If no detection data protocol is supported within specified duration (for example, <NUM>~<NUM>), the to-be-charged terminal <NUM> performs DCP detection.

For a DCP detection process, refer to the foregoing description provided with reference to <FIG> and <FIG>. For example, the detection process may be as follows: First, the charging protocol chip <NUM> enables a voltage source VDP_SRC (for example, <NUM>~<NUM> v, which is not shown in <FIG>, and for a setting manner, refer to <FIG> and <FIG>) of the first data pin <NUM> and a current source IDM_SINK (for example, <NUM>~<NUM>µA, which is not shown in <FIG>, and for a setting manner, refer to <FIG> and <FIG>) of the second data pin <NUM>. The first data pin <NUM> and the second data pin <NUM> are short-circuited by using a short-circuit resistor in the charging protocol chip <NUM>, and the charging protocol chip <NUM> detects whether a voltage of the second data pin <NUM> reaches VDP_SRC. The charging protocol chip <NUM> compares the voltage of the second data pin <NUM> with VDAT_REF (for example, <NUM>~<NUM> v) in a voltage comparator (not shown in <FIG>, and for a setting manner, refer to <FIG> and <FIG>) of the second data pin <NUM>. If the voltage of the second data pin <NUM> is greater than VDAT_REF, it can be determined that the to-be-charged terminal <NUM> is connected to a charging interface, and then secondary detection is performed to determine whether the to-be-charged terminal <NUM> is connected to a DCP interface or a CDP interface.

Then, the charging protocol chip <NUM> enables a voltage source VDM_SRC on the second data pin <NUM> (not shown in <FIG>, and for a setting manner, refer to <FIG> and <FIG>), enables a current source IDP_SINK (not shown in <FIG>, and for a setting manner, refer to <FIG> and a figure), and then compares a voltage of the first data pin <NUM> with a voltage of VDAT_REF. Because the first data pin <NUM> and the second data pin <NUM> are short-circuited by using the short-circuit resistor in the charging protocol chip <NUM>, a voltage of the voltage source VDM_SRC makes VDAT_REF<DP<VDM_SRC. Therefore, when the charging protocol chip <NUM> detects that VDAT_REF<the voltage of the DP pin, it can be determined that the to-be-charged terminal <NUM> is connected to the DCP interface.

In addition, the charging protocol chip <NUM> continuously detects a related signal level, disconnects a short circuit between the first data pin <NUM> and the second data pin <NUM> after specific time, and determines, based on a specified condition, whether to enter a fast charging mode (for example, SCP fast charging). If the charging protocol chip <NUM> determines to enter the fast charging mode, the charging protocol chip <NUM> communicates with the charging protocol chip <NUM> to adjust a voltage, to determine a charging voltage and current that are required by the to-be-charged terminal <NUM>.

It should be understood that a handshake circuit, a data detection circuit, and a DCP detection circuit that are used in the foregoing identification process are merely examples. This embodiment of this application is not limited thereto, provided that a corresponding detection requirement of the BC1. <NUM> protocol and/or a corresponding detection requirement of the SCP protocol can be implemented.

<FIG> is an example schematic diagram of a connection between an electronic device and a USB <NUM> device according to an embodiment of this application. Referring to <FIG>, the external interface <NUM> includes a first data pin <NUM>, a second data pin <NUM>, and a power-supply pin <NUM>. A USB <NUM> device <NUM> includes a USB <NUM> protocol chip <NUM>, a storage unit <NUM>, and a USB interface <NUM>. The USB interface <NUM> includes a first data pin <NUM>, a second data pin <NUM>, and a power-supply pin <NUM>. Based on a USB <NUM> protocol, the first data pin 261P or the second data pin <NUM> of the USB <NUM> device <NUM> is connected to, for example, a pull-up resistor of <NUM> ohms, based on different levels of transmission rates. For a process of identifying the USB <NUM> device <NUM>, refer to the foregoing description provided with reference to <FIG>.

After the USB <NUM> device <NUM> accesses the electronic device <NUM>, that is, after the USB interface <NUM> of the USB <NUM> device <NUM> is connected to the external interface <NUM> of the electronic device <NUM>, charging protocol detection is first performed, as shown in the foregoing content. If the charging protocol detection fails, the controller <NUM> controls the switch circuit <NUM> to enable a protocol channel between the processor <NUM> and the first data pin <NUM> and the second data pin <NUM>. As a Host (host device), the processor <NUM> can identify the USB <NUM> device and a speed type of the USB <NUM> device through a change in levels of the first data pin <NUM> and the second data pin <NUM> as long as detecting a pull-up resistor of the USB <NUM> device. This identification process has no insertion time limitation.

It should be noted that when an external device is a USB <NUM> device, because the electronic device <NUM> first performs fast charging protocol detection, identification of the USB <NUM> device is delayed. However, it is difficult for a user to perceive the delay, and therefore user experience is not degraded.

It should be understood that types of the external interface <NUM>, the charging interface <NUM>, and the USB interface <NUM> are not limited in this embodiment of this application, and may include, for example, a Type C USB interface, a TypeA USB interface, and the like.

The following describes locations that are of the pins when the external interface <NUM>, the charging interface <NUM>, and the USB interface <NUM> are Type C USB interfaces. The following example constitutes no limitation on this application.

Referring to <FIG>, when the external interface <NUM> is a Type C USB interface, the external interface <NUM> includes a side A and a side B. The side A includes a VBUS1 pin (a pin A4) and a VBUS2 pin (a pin A9). The side B includes a VBUS2 pin (a pin B9) and a VBUS1 pin (a pin B4). The VBUS1 pin (the pin A4) on the side A is electrically connected to the VBUS1 pin (the pin B4) on the side B, and the VBUS2 pin (the pin A9) on the side A is electrically connected to the VBUS2 pin (the pin B9) on the side B. The VBUS1 pin (the pin A4) on the side A and the VBUS1 pin (the pin B4) on the side B are first power-supply pins and can be used as the power-supply pins <NUM>, <NUM>, and <NUM>. The VBUS2 pin (the pin A9) on the side A and the VBUS1 pin (the pin B4) on the side B are second power electrical pins and can be used as the power-supply pins <NUM>, <NUM>, and <NUM>. In this embodiment of this application, for the USB <NUM> protocol or the SCP protocol, DP pins (a pin A6 on the side A and a pin B6 on the side B) are the first data pins <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, and DM pins (a pin A7 on the side A and a pin B7 on the side B) are the second data pins <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. A CC1 pin (a pin A5 on the side A) is the first communication pins <NUM> and <NUM>, and a CC2 pin (a pin B5 on the side B) is the second communication pins <NUM> and <NUM>. The external interface <NUM> shown in <FIG> can implement flexible forward/reverse insertion of a power-supply cable. Regardless of an insertion direction, an external device <NUM> can be connected, and a power-supply channel, a protocol channel/data channel, and a handshake channel can be accurately matched without additional setting of a forward/reverse insertion software/hardware detection mechanism for assistance.

It should be understood that the external interface in <FIG> is merely an example. In another embodiment of this application, the external interface <NUM> may be another type of interface, for example, a type A USB interface, or a Type C USB interface that includes pins fewer than those shown in <FIG>, such as a Type C USB interface that does not include pins TX1+, TX1-, RX2+, RX2-, and the like in <FIG>.

The following describes in detail a structure and a working principle of the switch circuit of the electronic device <NUM>.

<FIG> is an example schematic diagram of a switch circuit of an electronic device according to an embodiment of this application. Referring to <FIG>, the switch circuit <NUM> includes four switch components <NUM>. For example, the switch component <NUM> includes a first switch transistor <NUM>, a second switch transistor <NUM>, a third switch transistor <NUM>, and a fourth switch transistor <NUM>. The first switch transistor <NUM>, the second switch transistor <NUM>, the third switch transistor <NUM>, and the fourth switch transistor <NUM> each include a first terminal, a second terminal, and a control terminal. The controller <NUM> includes a general-purpose input/output (GPIO) interface, and the general-purpose input/output (GPIO) interface of the controller <NUM> includes a first control pin, a second control pin, a third control pin, and a fourth control pin. The first terminal of the first switch transistor <NUM> is connected to the first data pin <NUM> of the external interface <NUM>, the second terminal is connected to the first data pin <NUM> of the processor <NUM>, and the control terminal is connected to the first control pin of the general-purpose input/output (GPIO) interface of the controller <NUM>. The first terminal of the first switch transistor <NUM> is connected to the second data pin <NUM> of the external interface <NUM>, the second terminal is connected to the second data pin <NUM> of the processor <NUM>, and the control terminal is connected to the second control pin of the general-purpose input/output (GPIO) interface of the controller <NUM>. The first terminal of the third switch transistor <NUM> is connected to the first data pin <NUM> of the external interface <NUM>, the second terminal is connected to the first data pin <NUM> of the charging protocol chip <NUM>, and the control terminal is connected to the third control pin of the general-purpose input/output (GPIO) interface of the controller <NUM>. The first terminal of the fourth switch transistor <NUM> is connected to the second data pin <NUM> of the USB interface <NUM>, the second terminal is connected to the second data pin <NUM> of the charging protocol chip <NUM>, and the control terminal is connected to the fourth control pin of the general-purpose input/output (GPIO) interface of the controller <NUM>. The controller <NUM> outputs a level signal or a control signal to the control terminals of the first switch transistor <NUM>, the second switch transistor <NUM>, the third switch transistor <NUM>, and the fourth switch transistor <NUM> by using the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, to control on or off of the first switch transistor <NUM>, the second switch transistor <NUM>, the third switch transistor <NUM>, and the fourth switch transistor <NUM>.

When no external device accesses the external interface <NUM>, under action of the level signal or the control signal output by the controller <NUM>, the third switch transistor <NUM> and the fourth switch transistor <NUM> are turned on, and the first switch transistor <NUM> and the second switch transistor <NUM> are turned off, so that the second protocol identification channel is conducted and the first protocol identification channel is disconnected. After an external device accesses the external interface <NUM>, the charging protocol chip <NUM> communicates with the external device through the second protocol identification channel to perform charging protocol identification, to determine whether the external device supports a corresponding charging protocol (for example, the SCP protocol). For details, refer to the foregoing content. If the charging protocol identification succeeds, the charging protocol chip <NUM> sends, to the controller <NUM>, an indication indicating that the charging protocol identification succeeds. The controller <NUM> determines, based on a current status of the battery <NUM>, for example, remaining power and a current output voltage, whether to enable fast charging to charge the external device. For example, when the remaining power of the battery is greater than a specified threshold (for example, <NUM>%), the controller <NUM> determines to enable fast charging. After the controller <NUM> determines to enable fast charging to charge the external device, the charging protocol chip <NUM> sends an enable signal to the voltage conversion circuit <NUM>, and the voltage conversion circuit <NUM> performs fast charging on the external device through the external interface <NUM> based on a charging voltage and current that are determined by the charging protocol chip <NUM>.

If the charging protocol identification fails, the charging protocol chip <NUM> sends, to the controller <NUM>, an indication indicating that the charging protocol identification fails. The controller <NUM> changes, based on the indication, level signals or control signals output by the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, so that the third switch transistor <NUM> and the fourth switch transistor <NUM> are turned off, and the first switch transistor <NUM> and the second switch transistor <NUM> are turned on. Therefore, the second protocol identification channel is disconnected, and the first protocol identification channel is conducted. Then, the processor <NUM> communicates with the external device through the first protocol identification channel to perform USB <NUM> protocol identification, to determine whether the external device is a USB <NUM> device (for a USB <NUM> identification process, refer to the foregoing description). After it is determined that the external device is a USB <NUM> device, a subsequent operation such as data reading or storage is performed based on a device type. For example, when the USB <NUM> device is a high-speed storage device, high-speed data reading or storage is performed with the USB <NUM> device. When the USB <NUM> device is a low-speed storage device, low-speed data reading or storage is performed with the USB <NUM> device. After the external device is removed from the external interface <NUM>, the processor <NUM> sends, to the controller <NUM> through, for example, an eSPI bus, an indication indicating that the USB <NUM> device is removed. Then, the controller <NUM> changes the level signals or the control signals output by the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, so that the third switch transistor <NUM> and the fourth switch transistor <NUM> are turned on, and the first switch transistor <NUM> and the second switch transistor <NUM> are turned off. Therefore, the second protocol identification channel is conducted, and the first protocol identification channel is disconnected, to wait for access of a next external device and repeat the foregoing identification process.

For example, the first switch transistor <NUM> and the second switch transistor <NUM> may be PMOS transistors, and the third switch transistor <NUM> and the fourth switch transistor <NUM> may be NMOS transistors. The controller <NUM> is configured to pull up levels (that is, high levels are output) of the four pins of the GIPO that are connected to the control terminals of the switch transistors by default, so that the first switch transistor <NUM> and the second switch transistor <NUM> are turned off, and the third switch transistor <NUM> and the fourth switch transistor <NUM> are turned on. Therefore, the first protocol identification channel is disconnected, and the second protocol identification channel is conducted. After the charging protocol identification fails, the controller <NUM> pulls down the levels (that is, low levels are output) of the first control pin, the second control pin, the third control pin, and the fourth control pin of the GIPO interface, so that the first switch transistor <NUM> and the second switch transistor <NUM> are turned on, and the third switch transistor <NUM> and the fourth switch transistor <NUM> are turned off. Therefore, the first protocol identification channel is conducted, and the second protocol identification channel is disconnected. After the external device is removed, the controller <NUM> pulls up again the levels (that is, high levels are output) of the first control pin, the second control pin, the third control pin, and the fourth control pin of the GIPO interface, so that the second protocol identification channel is conducted by default, and the first protocol identification channel is disconnected by default.

It should be understood that, although in the embodiment shown in <FIG>, the GPIO interface of the controller <NUM> controls the first switch transistor to the fourth switch transistor by using four control pins, in another embodiment, only one control pin may be used to control the first switch transistor to the fourth switch transistor, or two control pins may be used to control the first switch transistor to the fourth switch transistor.

When one control pin is used, the control terminals of the first switch transistor to the fourth switch transistor all are connected to the control pin, and a level output by the control pin is used to turn on the first switch transistor and the second switch transistor and turn off the third switch transistor and the fourth switch transistor, or turn on the third switch transistor and the fourth switch transistor and turn off the first switch transistor and the second switch transistor. In this case, the first switch transistor and the second switch transistor are of a same type, the third switch transistor and the fourth switch transistor are of a same type, and the first switch transistor and the third switch transistor are opposite in type. For example, the example first switch transistor <NUM> and second switch transistor <NUM> may be PMOS transistors, and the third switch transistor <NUM> and the fourth switch transistor <NUM> may be NMOS transistors. Alternatively, the first switch transistor <NUM> and the second switch transistor <NUM> may be NMOS transistors, and the third switch transistor <NUM> and the fourth switch transistor <NUM> may be PMOS transistors. In this way, only one control pin needs to be used to control the four switch transistors, so that a quantity of occupied pins of the GPIO interface of the controller is decreased, and a control signal is relatively simple.

When two control pins are used, the control terminals of the first switch transistor and the second switch transistor are connected to the first control pin, the control terminals of the third switch transistor and the fourth switch transistor are connected to the second control pin, and levels output by the first control pin and the second control pin are used to turn on the first switch transistor and the second switch transistor and turn off the third switch transistor and the fourth switch transistor, or turn on the third switch transistor and the fourth switch transistor and turn off the first switch transistor and the second switch transistor. In this case, it is only required that the first switch transistor and the second switch transistor are of a same type, and the third switch transistor and the fourth switch transistor are of a same type, and the first switch transistor and the third switch transistor do not need to be opposite in type. For example, the first switch transistor <NUM> and the second switch transistor <NUM> may be PMOS transistors, and the third switch transistor <NUM> and the fourth switch transistor <NUM> may be PMOS transistors. Alternatively, the first switch transistor <NUM> and the second switch transistor <NUM> may be NMOS transistors, and the third switch transistor <NUM> and the fourth switch transistor <NUM> may be NMOS transistors. Alternatively, the first switch transistor <NUM> and the second switch transistor <NUM> may be PMOS transistors, and the third switch transistor <NUM> and the fourth switch transistor <NUM> may be NMOS transistors. Alternatively, the first switch transistor <NUM> and the second switch transistor <NUM> may be NMOS transistors, and the third switch transistor <NUM> and the fourth switch transistor <NUM> may be PMOS transistors. In this case, the foregoing control effect can be implemented simply by adjusting, based on a type of the switch transistor, the level output by the control pin of the controller.

It should be further understood that, when four control pins are used, as shown in <FIG>, types of the first switch transistor to the fourth switch transistor all may be P-types or N-types, and do not need to be the same.

<FIG> is an example schematic diagram of another switch circuit of an electronic device according to an embodiment of this application. Referring to <FIG>, unlike <FIG>, in the electronic device shown in <FIG>, the switch circuit <NUM> includes four switch components <NUM>. For example, the switch component <NUM> includes a first switch chip <NUM>, a second switch chip <NUM>, a third switch chip <NUM>, and a fourth switch chip <NUM>. The first switch chip <NUM>, the second switch chip <NUM>, the third switch chip <NUM>, and the fourth switch chip <NUM> each include a first terminal, a second terminal, and a control terminal. The first terminal of the first switch chip <NUM> is connected to the first data pin <NUM> of the external interface <NUM>, the second terminal is connected to the first data pin <NUM> of the processor <NUM>, and the control terminal is connected to the first control pin of the general-purpose input/output (GPIO) interface of the controller <NUM>. The first terminal of the second switch chip <NUM> is connected to the second data pin <NUM> of the external interface <NUM>, the second terminal is connected to the second data pin <NUM> of the processor <NUM>, and the control terminal is connected to the second control pin of the general-purpose input/output (GPIO) interface of the controller <NUM>. The first terminal of the third switch chip <NUM> is connected to the first data pin <NUM> of the external interface <NUM>, the second terminal is connected to the first data pin <NUM> of the charging protocol chip <NUM>, and the control terminal is connected to the third control pin of the general-purpose input/output (GPIO) interface of the controller <NUM>. The first terminal of the fourth switch chip <NUM> is connected to the second data pin <NUM> of the external interface <NUM>, the second terminal is connected to the second data pin <NUM> of the charging protocol chip <NUM>, and the control terminal is connected to the fourth control pin of the general-purpose input/output (GPIO) interface of the controller <NUM>. The controller <NUM> outputs a level signal or a control signal to the control terminals of the first switch chip <NUM>, the second switch chip <NUM>, the third switch chip <NUM>, and the fourth switch chip <NUM> by using the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, to control on and off of the first switch chip <NUM>, the second switch chip <NUM>, the third switch chip <NUM>, and the fourth switch chip <NUM>.

A working principle of the switch circuit of the electronic device shown in <FIG> is similar to a working principle of the switch circuit of the electronic device shown in <FIG>.

<FIG> is an example schematic diagram of still another switch circuit of an electronic device according to an embodiment of this application. Referring to <FIG>, unlike <FIG>, in the electronic device shown in <FIG>, the switch circuit <NUM> includes two switch components <NUM>. For example, the switch component <NUM> includes a first switch chip <NUM> and a second switch chip <NUM>. Both the first switch chip <NUM> and the second switch chip <NUM> include two input terminals, two output terminals, and one control terminal. The two input terminals of the first switch chip <NUM> are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM>, and the two output terminals are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the processor <NUM>, to form the first protocol identification channel. The two input terminals of the second switch chip <NUM> are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM>, and the two output terminals are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the charging protocol chip <NUM>, to form the second protocol identification channel. The control terminals of each of the first switch chip <NUM> and the second switch chip <NUM> are respectively connected to the first control pin and the second control pin of the GPIO interface of the controller <NUM>. The controller <NUM> applies a control signal to the control terminals of the first switch chip <NUM> and the second switch chip <NUM> to control on and off of the first switch chip <NUM> and the second switch chip <NUM>, so as to control conduction or disconnection of the first protocol identification channel and the second protocol identification channel.

<FIG> is an example schematic diagram of still another switching circuit of an electronic device according to an embodiment of this application. Referring to <FIG>, unlike <FIG>, in the electronic device shown in <FIG>, the switch circuit <NUM> includes one switch chip <NUM>. The switch chip includes four input terminals, four output terminals, and two/four control terminals (two control terminals are shown in <FIG> as examples). The two input terminals of the switch chip <NUM> are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM>, and the two output terminals are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the processor <NUM>, to form the first protocol identification channel. The other two input terminals of the switch chip <NUM> are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the external interface <NUM>, and the other two output terminals are respectively connected to the first data pin <NUM> and the second data pin <NUM> of the charging protocol chip <NUM>, to form the second protocol identification channel. The two/four control terminals of the switch chip <NUM> are respectively connected to two/four control pins of the GPIO interface of the controller <NUM>. The controller <NUM> applies a control signal to the control terminal of the switch chip <NUM> to control conduction or disconnection of the first protocol identification channel and the second protocol identification channel.

In conclusion, it can be learned that, in the electronic device provided in the embodiments of this application, the controller <NUM> and the switch circuit <NUM> are configured, so that the second protocol identification channel (that is, a charging protocol identification channel) is conducted by default. After an external device accesses the external interface <NUM>, charging protocol identification is first performed. After the charging protocol identification fails, the controller <NUM> and the switch circuit <NUM> are used to disconnect the second protocol identification channel and conduct the first protocol identification channel, to perform USB <NUM> device identification. In addition, after a USB <NUM> device is removed from the USB interface <NUM>, the controller <NUM> and the switch circuit <NUM> are used to conduct the second protocol identification channel by default again, to wait for access of a next external device. When the electronic device provided in the embodiments of this application is used, a terminal that supports the SCP protocol or the like can be quickly charged through the external interface without affecting identification of a USB <NUM> device.

An embodiment of this application further provides a device identification method. For example, the device identification method may be applied to the electronic device in the embodiments, and has a same beneficial effect. For detailed content that is not described in detail in this embodiment, refer to the foregoing embodiments of the electronic device. The following describes the device identification method with reference to the electronic devices shown in <FIG>, <FIG>, and <FIG>.

As shown in <FIG>, the device identification method may be implemented by using the following steps.

S1501: A controller controls a switch circuit to conduct a second protocol identification channel by default, and disconnect a first protocol identification channel by default.

For example, the controller <NUM> is configured to pull up levels (that is, high levels are output) of the first control pin, the second control pin, the third control pin, and the fourth control pin of the GIPO by default, so that the first switch transistor <NUM> (PMOS) and the second switch transistor <NUM> (PMOS) are turned off, and the third switch transistor <NUM> (NMOS) and the fourth switch transistor <NUM> (NMOS) are turned on. Therefore, the first protocol identification channel is disconnected, and the second protocol identification channel is conducted.

S1502: A charging protocol chip communicates with an external device to perform charging protocol detection, and feeds back a detection result to the controller.

For example, the charging protocol chip <NUM> completes a handshake with the to-be-charged terminal <NUM> through a handshake channel, and then provides a power-supply pin/power-supply channel with, for example, a Vbus voltage of <NUM> V. Then, after the to-be-charged terminal <NUM> identifies, based on a BC1. <NUM> protocol (Battery Charging v1. <NUM>), that the electronic device <NUM> is a DCP (Dedicated Charging Port, dedicated charging port) device, the charging protocol chip <NUM> performs charging protocol detection, and feeds back a detection result to the controller <NUM>. For example, the charging protocol chip <NUM> sends, to the controller <NUM> through an I2C bus, an indication indicating that the charging protocol detection succeeds or fails.

After the charging protocol chip <NUM> succeeds in the charging protocol detection, proceed to step S1503; or after the charging protocol chip <NUM> fails in the charging protocol detection, proceed to step S1505.

S1503: The controller determines, based on battery power, whether to enable fast charging.

For example, the controller <NUM> determines, based on current power of the battery <NUM>, whether to enable fast charging. For example, when the current power of the battery <NUM> is greater than a specified threshold, the controller <NUM> determines to enable fast charging.

After the controller <NUM> determines to enable fast charging, proceed to step S1504; or after the controller <NUM> determines not to enable fast charging, proceed to step S1505.

S1504: The charging protocol chip communicates charging information with a terminal, and sends an enable signal to a voltage conversion circuit after communicating the charging information, to enable fast charging.

For example, the charging protocol chip <NUM> of the terminal determines a required charging voltage and current based on a current circuit of the battery <NUM>, and then sends the charging voltage and current to the charging protocol chip <NUM>. The charging protocol chip <NUM> sends an enable signal to the voltage conversion circuit <NUM>, and the voltage conversion circuit <NUM> quickly charges the external device through the USB interface <NUM> based on the charging voltage and current that are determined by the charging protocol chip <NUM>.

S1505: The controller controls the switch circuit to disconnect the second protocol channel and conduct the first protocol identification channel.

For example, the charging protocol chip <NUM> sends, to the controller <NUM>, an indication indicating that the charging protocol identification fails or indicating not to enable fast charging. The controller <NUM> changes, based on the indication, level signals or control signals output by the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, so that the third switch transistor <NUM> and the fourth switch transistor <NUM> are turned off, and the first switch transistor <NUM> and the second switch transistor <NUM> are turned on. Therefore, the second protocol identification channel is disconnected, and the first protocol identification channel is conducted. Then, the processor <NUM> communicates with the external device through the first protocol identification channel to perform USB <NUM> protocol identification, to determine whether the external device is a USB <NUM> device. After it is determined that the external device is a USB <NUM> device, a subsequent operation such as data reading or storage is performed based on a device type.

S1506: A processor notifies the controller that the USB <NUM> device is removed.

For example, after the external device is removed from the external interface <NUM>, the processor <NUM> sends, to the controller <NUM> through, for example, an eSPI bus, an indication indicating that the USB <NUM> device is removed.

Then, go back to step S1501. The controller <NUM> changes the level signals or the control signals output by the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, so that the third switch transistor <NUM> and the fourth switch transistor <NUM> are turned on, and the first switch transistor <NUM> and the second switch transistor <NUM> are turned off. Therefore, the second protocol identification channel is conducted, and the first protocol identification channel is disconnected.

It should be noted that, the foregoing example merely shows a procedure of the device identification method, but constitutes no limitation on this application. For example, the device identification method may not include step S1503, or steps S1502 and S1504 may be combined into one step.

It may be understood that to implement the foregoing functions, the electronic device includes corresponding hardware and/or software modules for performing the functions. The algorithm steps in the examples described with reference to the embodiments disclosed in this specification can be implemented in this application in a form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or by driving hardware by using computer software depends on particular applications and design constraints of the technical solutions. Persons skilled in the art may use different methods to implement the described functions with reference to embodiments for each particular application, but it should not be considered that the implementation goes beyond the scope of this application.

In an example, <FIG> is a schematic block diagram of an apparatus <NUM> according to an embodiment of this application. The apparatus <NUM> may include a processor <NUM> and a transceiver/transceiver pin <NUM>, and optionally, further includes a memory <NUM>.

Components in the apparatus <NUM> are coupled together through a bus <NUM>. In addition to a data bus, the bus <NUM> further includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are referred to as the bus <NUM> in the figure.

Optionally, the memory <NUM> may be configured to store the instructions in the foregoing method embodiments. The processor <NUM> may be configured to: execute the instructions in the memory <NUM>, control a receive pin to receive a signal, and control a transmit pin to send a signal.

The apparatus <NUM> may be the electronic device or a chip in the electronic device in the foregoing method embodiments.

All related content of the steps in the foregoing method embodiments may be cited to function descriptions of corresponding functional modules.

Claim 1:
An electronic device (<NUM>), comprising a processor (<NUM>), a controller (<NUM>), a charging protocol chip (<NUM>), an external interface (<NUM>), and a switch circuit (<NUM>), wherein
the processor (<NUM>), the charging protocol chip (<NUM>), and the external interface (<NUM>) each comprise a data pin unit (<NUM>, <NUM>; <NUM>, <NUM>; <NUM>, <NUM>);
the data pin unit (<NUM>, <NUM>) of the processor (<NUM>), the data pin unit (<NUM>, <NUM>) of the charging protocol chip (<NUM>), the data pin unit (<NUM>, <NUM>) of the external interface (<NUM>), and the controller (<NUM>) are separately electrically connected to the switch circuit (<NUM>); and
the controller (<NUM>) is configured to control the switch circuit (<NUM>), so that the data pin unit (<NUM>, <NUM>) of the external interface (<NUM>) is connected to the data pin unit (<NUM>, <NUM>) of the charging protocol chip (<NUM>) and is disconnected from the data pin unit (<NUM>, <NUM>) of the processor (<NUM>);
the charging protocol chip (<NUM>) is configured to perform second protocol identification on an external device when the external interface (<NUM>) is connected to the external device;
the controller (<NUM>) is configured to: after receiving the indication that is sent by the charging protocol chip (<NUM>) and that indicates that the second protocol identification fails, so that the data pin unit (<NUM>, <NUM>) of the external interface (<NUM>) is disconnected from the data pin unit (<NUM>, <NUM>) of the charging protocol chip (<NUM>) and is connected to the data pin unit (<NUM>, <NUM>) of the processor (<NUM>);
the processor (<NUM>) is configured to perform first protocol identification on the external device when the external interface (<NUM>) is connected to the external device and the data pin unit (<NUM>, <NUM>) of the processor (<NUM>) is connected to the pin unit (<NUM>, <NUM>) of the external interface (<NUM>),
wherein the first protocol comprises a USB <NUM> protocol, and a second protocol comprises an SCP/FCP fast charging protocol.