Patent Description:
The following documents are disclosures in the general field of the invention: <CIT>), <CIT>), <CIT>), and <NPL>.

The invention provides a data processing system in accordance with claim <NUM> and a method in accordance with claim <NUM>. Additional features of the invention are defined in the dependent claims.

<FIG> illustrate systems and methods for efficient data caching in a cache hierarchy having three or more cache levels. In accordance with some embodiments, the control logic of the various caches of the cache hierarchy operate together to implement a hybrid lower-level cache inclusion policy that ensures that cachelines cached at a highest-level cache have at least one copy elsewhere in the cache hierarchy while also providing for reduced inter-cache messaging and evictions than conventional caching policies. As described in greater detail herein, this caching policy, referred to herein as a "hybrid lower-level cache inclusion policy", implements at least the following three guidelines. First, a cacheline present in the first-level cache (e.g., a Level <NUM>, or L1, cache) is required to be in at least one of a second-level cache (e.g., a Level <NUM>, or L2, cache) or a third-level cache (e.g., a Level <NUM>, or L3, cache). Second, a cacheline evicted from the second-level cache does not require eviction of the same cacheline from the first-level cache. Third, eviction of a cacheline from the third-level cache requires eviction of the cacheline from the first-level cache if the cacheline is not also present in the second-level cache. This can be advantageous in that if the system is already searching in the second level cache and the third level cache to access to a cacheline, the caching policy described above results in the system being guaranteed to know if the sought-after cacheline is in the first level cache as well. Note that reference to a cacheline being "present" in a cache, as found herein, is reference to a copy being both stored at the cache and having a valid status at that cache. Thus, a copy of a cacheline that is marked "invalid" or some similar status at a cache is not considered to be "present" at that cache.

<FIG> illustrates a processing system <NUM> using a hybrid lower-level cache inclusion policy in accordance with at least some embodiments. The processing system <NUM> includes a compute complex <NUM>, a cache hierarchy <NUM>, a memory controller (MC) <NUM>, and a southbridge <NUM>. The compute complex <NUM> includes one or more processor cores, such as four processor cores <NUM>, <NUM>, <NUM>, <NUM>. The processor cores include, for example, central processing unit (CPU) cores, graphics processing unit (GPU) cores, digital signal processor (DSP) cores, or a combination thereof. It will be appreciated that the number of processor cores of the compute complex <NUM> may be fewer or more than four.

The memory controller <NUM> operates as the interface between the cache hierarchy <NUM> and a system memory <NUM>. Thus, data to be cached in the cache hierarchy <NUM> typically is manipulated as blocks of data referred to as "cachelines", and which are addressed or otherwise located in a memory hierarchy using a physical address of system memory <NUM>. Cachelines are accessed from the system memory <NUM> by the memory controller <NUM> in response to memory requests from the cache hierarchy <NUM>, and the cachelines are installed, or cached, in one or more caches of the cache hierarchy <NUM>. Likewise, when a cacheline containing modified data is evicted from the cache hierarchy <NUM>, and thus needs to be updated in the system memory <NUM>, the memory controller <NUM> manages this write-back process. The southbridge <NUM> operates as the interface between the cache hierarchy <NUM>, the memory controller <NUM>, and one or more peripherals <NUM> of the processing system <NUM> (e.g., network interfaces, keyboards, mice, displays, and other input/output devices).

The cache hierarchy <NUM> includes three or more levels of caches, including a first level (L1), a second level (L2), and a third level (L3) of caches. Although the example embodiment of <FIG> includes only three levels, in other embodiments the cache hierarchy <NUM> includes four or more caching levels. Each caching level includes one or more caches at that level. For system <NUM>, the compute complex <NUM> implements small private caches for each processing core at L1, implemented as L1 caches <NUM>, <NUM>, <NUM>, <NUM>, each associated with a corresponding one of processor cores <NUM>-<NUM>. Further, for L2, the compute complex <NUM> implements larger private caches for each processor core, implemented as L2 caches <NUM>, <NUM>, <NUM>, <NUM> corresponding to processor cores <NUM>-<NUM>, respectively. Each of the L2 caches <NUM>-<NUM> is private to its corresponding processor core, but the cache hierarchy <NUM> operates to maintain coherency between the L2 caches <NUM>-<NUM>. The L2 caches <NUM>-<NUM> can be direct mapped or an n-way set associative cache in some embodiments. In other embodiments, two or more L1 caches may share a single L2 cache. For the L3 caching level, the cache hierarchy <NUM> implements an L3 cache <NUM> that is shared by the processor cores of the compute complex <NUM>, and thus shared by at least the L2 caches <NUM>-<NUM>. In other embodiments, the L3 caching level may include more than one L3 cache shared by the L2 caches <NUM>-<NUM> in various combinations.

The caches of the cache hierarchy <NUM> are used to cache data for access and manipulation by the processor cores <NUM>-<NUM>. Typically, caches at lower levels (e.g., L1) tend to have lower storage capacity and lower access latencies, while caches at higher levels (e.g., L3) tend to have higher storage capacity and higher access latencies. Accordingly, cachelines of data are transferred among the caches of different cache levels so as to better optimize the utilization of the cache data in view of the caches' storage capacities and access latencies through cacheline eviction processes and cacheline installation processes managed by cache hierarchy control logic <NUM> of the cache hierarchy <NUM>. Although depicted using a single block external to the various caches of the cache hierarchy <NUM> for ease of illustration in <FIG>, it will be appreciated that in a typical implementation individual components of the cache hierarchy control logic <NUM> are implemented at each cache as cache control logic for that cache, and thus the cache hierarchy control logic <NUM> represents the aggregate of the individual cache control logic components implemented at each cache of the cache hierarchy <NUM>. In some embodiments, the logic components of the cache hierarchy control logic <NUM> are implemented as hard-coded logic on one or more integrated circuit (IC) chips implementing the processing system <NUM>. In other embodiments, some or all of the logic components of the cache hierarchy control logic <NUM> are implemented as programmable logic, as configurable logic (e.g., fuse-configurable logic), one or more processors executing a program of instructions, or a combination thereof.

In operation, the cache hierarchy control logic <NUM> installs and evicts (that is, removes) cachelines of data fetched from the system memory <NUM> in accordance with one or more caching policies defined for the cache hierarchy control logic <NUM> via hard-coded logic, programmable elements (e.g., fuses), register sets, or a combination thereof. One of these caching policies includes a caching policy <NUM> for selective eviction of cachelines depending on their presence status in other caching levels, referred to herein as the "hybrid lower-level cache inclusion policy <NUM>". The guidelines for hybrid lower-level cache inclusion policy <NUM> are be briefly summarized as follows: (<NUM>) any cacheline present in a first-level cache (e.g., one of the L1 caches <NUM>-<NUM>) must also be present in at least one of a second-level cache (e.g., one of L2 caches <NUM>-<NUM>) or a third-level cache (e.g., L3 cache <NUM>); (<NUM>) when a cacheline is evicted from a second-level cache, eviction of the cacheline from the first-level cache is not required (that is, if the cacheline is present in the L1 cache, the cacheline will be maintained in the L1 cache even after eviction of the cacheline from the L2 cache); and (<NUM>) when a cacheline is evicted from a third-level cache and that cacheline is not present in a second-level cache at the time of eviction, then the cacheline is also evicted from the first-level cache. This particular caching policy improves performance as the first-level cachelines are not required to be evicted when a second-level cache evicts them. While an inclusive third-level (L3) policy could also achieve this, it would be at the cost of decreased capacity in the third-level cache due to the duplicated cachelines.

<FIG> illustrates an example implementation of the cache hierarchy control logic <NUM> and the caches from the cache hierarchy <NUM> in more detail in accordance with some embodiments. As noted above, each of the cache levels has one or more caches within that level. However, for ease of illustration, only a single cache from each cache level is shown in <FIG>, namely as L1 cache <NUM>, L2 cache <NUM>, and L3 cache <NUM>. It will be understood that the other caches of the cache hierarchy <NUM> would be similarly configured in the manner described below.

The L1 cache <NUM> includes a tag array <NUM>, a data array <NUM>, and L1 control logic <NUM>. The data array <NUM> includes a plurality of data entries <NUM>, or lines, each of which is configured to store a corresponding set of data (that is, "a cacheline") from the system memory <NUM>. The tag array <NUM> likewise includes a plurality of tag entries <NUM>, each of which is associated with a corresponding data entry <NUM> of the data array <NUM> and which is configured to store various information regarding a cacheline stored in the corresponding entry <NUM>, such as the address (or portion thereof) associated with the cacheline in address field <NUM> and one or more status bits stored in status field <NUM>. The L2 cache <NUM> and the L3 cache <NUM> are similarly configured. As such, the L2 cache <NUM> includes a tag array <NUM>, a data array <NUM>, and L2 control logic <NUM>, and the L3 cache <NUM> includes a tag array <NUM>, a data array <NUM>, and L3 control logic <NUM>. The data arrays <NUM>, <NUM> include a plurality of data entries <NUM>, <NUM>, respectively, for storing cachelines of data, and the tag arrays <NUM>, <NUM> include a plurality of tag entries <NUM>, <NUM> corresponding to the data entries <NUM>, <NUM>, respectively. As with the tag entries <NUM>, the tag entries <NUM> have an address field <NUM> for storing an address of a corresponding cacheline, status field <NUM> for storing status bits for the corresponding cacheline, and the like. Likewise, the tag entries <NUM> have an address field <NUM> and a status field <NUM> for the corresponding cachelines stored in the data entries <NUM>.

The L1 control logic <NUM>, the L2 control logic <NUM>, and L3 control logic <NUM> together constitute at least part of the cache hierarchy control logic <NUM>, which as noted above, operates to implement one or more caching policies for the cache hierarchy, including the caching policy <NUM> (<FIG>). To this end, each of the control logic <NUM>, <NUM>, <NUM> includes coherency logic <NUM>, <NUM>, <NUM>, respectively, to implement corresponding aspects of the hybrid lower-level cache inclusion policy <NUM>, as described in greater detail below with reference to <FIG>. To facilitate this operation, in some embodiments one or more of the caches <NUM>, <NUM>, <NUM> stores presence information that identifies whether each cacheline stored in the cache is also stored in one or more of the other caches of the cache hierarchy <NUM>. This presence information, in one embodiment, is stored in, or in association with, the tag array of the cache. To illustrate, the tag entries <NUM> of the tag array <NUM> of the L1 cache <NUM> each includes a presence (or location "LOC") field <NUM> that stores co-presence information for the cacheline with respect to the cacheline's storage in other caches.

To illustrate, in one embodiment the presence field <NUM> is configured as a single bit field <NUM> that indicates whether the corresponding cacheline is found in either an L2 cache or an L3 cache. Thus, if the single bit field <NUM> is set to <NUM>, this indicates that the cacheline in the corresponding data entry <NUM> of the L1 cache <NUM> is present in an L2 cache, whereas the single bit field <NUM> being set to <NUM> indicates that the cacheline is found in an L3 cache. In other embodiments, the presence field <NUM> is configured as a two-bit field <NUM> that indicates whether the corresponding cacheline is found in either an L2 cache or an L3 cache, and also identifies the particular cache level storing the copy of the cacheline. To illustrate, a value of <NUM> indicates a copy of the cacheline is present in an L2 cache but not present in an L3 cache, a value of <NUM> indicates a copy of the cacheline is not present in an L2 cache but present in an L3 cache, and a value of <NUM> indicates both an L2 cache and an L3 cache store a copy of the cacheline. In yet other embodiments, the presence field <NUM> is implemented as a multiple-bit field <NUM> that identifies both the lower cache level(s) at which a copy of the cacheline may be found, as well as the particular cache way(s) at each lower cache level storing the cacheline.

The L3 cache <NUM>, in some embodiments, is similarly configured with the tag entries <NUM> of the tag array <NUM> having a presence field <NUM> used to indicate whether the cacheline in the corresponding data entry <NUM> is present in the higher cache levels. As with the presence field <NUM>, in some embodiments the presence field <NUM> is configured as a single bit field <NUM> that simply identifies whether a copy of the cacheline is found in an L1 cache or an L2 cache but does not identify which of the two higher cache levels or the particular cache(s) storing the cacheline. In other embodiments, the presence field <NUM> is configured as a two-bit field <NUM> that identifies whether a copy of the cacheline is found in the higher cache levels, as well as identifying the higher cache level(s) containing a copy of the cacheline. In yet other embodiments, the presence field <NUM> is implemented as a multi-bit field <NUM> that not only identifies which higher cache level(s) store a copy of the cacheline, but the particular cache(s) as well. The L2 cache <NUM> likewise may be configured with a presence field <NUM> in the tag entries <NUM> or elsewhere in the L2 cache <NUM> configured as one of a single bit field <NUM>, a two-bit field <NUM>, or a multiple-bit field <NUM> for identifying the presence of corresponding cachelines in one or both of the L1 cache level and the L3 cache level.

The presence information represented by the presence fields <NUM>, <NUM>, <NUM> is used by the respective coherency logic <NUM>, <NUM>, <NUM> to collectively implement the hybrid lower-level cache inclusion policy <NUM> responsive to installation of a cacheline to a particular cache or responsive to eviction of a cacheline from a cache. To this end, the coherency logic <NUM>, <NUM>, <NUM> utilize a messaging interconnect <NUM> to communicate installation messages and eviction messages among the various caches in order to install a copy of a cacheline in a targeted cache or to evict a copy of a cacheline from a targeted cache in accordance with the caching guidelines specified by the caching policy <NUM>. <FIG> illustrate example methods of operation for the coherency logic <NUM>, <NUM>, and <NUM>, respectively.

<FIG> illustrates a method <NUM> for implementing a corresponding aspect of the caching policy <NUM> at an L1 cache, such as L1 cache <NUM>, in accordance with some embodiments. The method <NUM> initiates at block <NUM> with the fetching of a cacheline of data from the system memory <NUM> and installation of the cacheline in the cache hierarchy <NUM>. The cacheline is fetched as a demand fetch responsive to initial execution of an instruction referencing data contained in the cacheline, or the cacheline is fetched from system memory <NUM> as part of a speculative prefetch operation. Typically, a cacheline fetched from system memory <NUM> is first installed in a lower-level cache, such as in the L2 cache <NUM> or the L3 cache <NUM>. At some point, either as the initial fetch of the cacheline from system memory <NUM> or subsequently as part of a request for data stored in the cacheline by a processor core, a copy of the cacheline is installed in an L1 cache (e.g., L1 cache <NUM>) at block <NUM>.

As part of the initial cacheline installation and as part of the installation of the cacheline into the L1 cache, at block <NUM> the caches of the cache hierarchy <NUM> update their respective presence information fields to reflect the presence of the cacheline in one or more caches of the cache hierarchy <NUM>. In one embodiment, location status updates are performed responsive to coherency messages transmitted between the coherence logic of the various caches via the messaging interconnect <NUM>. To illustrate, installation of the cacheline in the L1 cache <NUM> triggers the coherency logic <NUM> of the L1 control logic <NUM> to broadcast a coherency message for that cacheline to the other caches of the cache hierarchy <NUM> so as to inform the cache hierarchy <NUM> of installation of the cacheline at the L1 cache <NUM>. In response to receiving this coherency message, the coherency logic <NUM> of the L2 control logic <NUM> accesses the tag entry <NUM> for that cacheline (if stored at the L2 cache <NUM>) and updates the presence field <NUM> to reflect that a copy of the cacheline is stored at the L1 cache level and if so configured, the particular L1 cache now storing the cacheline. The coherency logic <NUM> updates the corresponding presence field <NUM> in a similar manner upon receipt of the coherency message at the L3 cache <NUM>.

Recall that one of the aspects or guidelines of the hybrid lower-level cache inclusion policy <NUM> is that if a cacheline is stored in an L1 cache, a copy of that cacheline must also be stored in at least one of an L2 cache or an L3 cache. Accordingly, at block <NUM> the coherency logic (e.g., coherency logic <NUM>) of the L1 cache storing the cacheline checks the presence field <NUM> for that cacheline to determine whether the cacheline is present in a cache at the L2 or L3 caching level. If so, then the method <NUM> terminates at block <NUM> until the next cacheline is installed in the cache hierarchy <NUM>. Otherwise, if the cacheline is not present in an L2 cache or an L3 cache, at block <NUM> the coherency logic of the L1 cache triggers installation of a copy of the cacheline at a lower-level cache by sending an installation message to a lower-level cache accessible by the L1 cache to instruct that lower-level cache to install a copy of the cacheline. Generally, the next lower-level would be used, and thus, for example, the L1 cache <NUM> would instruct the L2 cache <NUM> to install a copy of the cacheline at block <NUM>. As a result of the installation of the copy of the cacheline, at block <NUM> the lower-level cache receiving and storing the copy of the cacheline broadcasts a coherency message to the other caches so that the other caches update their local presence information stores accordingly.

<FIG> illustrates a method <NUM> for implementing a corresponding aspect of the hybrid lower-level cache inclusion policy <NUM> at an L2 cache, such as L2 cache <NUM>, in accordance with some embodiments. The method <NUM> initiates at block <NUM> with the eviction of a cacheline from the L2 cache. The eviction of the cacheline typically is triggered in response to the data array <NUM> of the L2 cache being over-subscribed. In a conventional caching policy, eviction of a cacheline from an L2 cache would require eviction of that same cacheline from all L1 caches associated with the L2 cache. However, as explained above, one guideline of the hybrid lower-level cache inclusion policy <NUM> is that cacheline evictions from the L2 caching level do not require eviction of the same cachelines from the L1 caching level as a consequence. Accordingly, as represented by block <NUM>, the cacheline evicted from the L2 cache at block <NUM> is maintained in the L1 cache in accordance with the hybrid lower-level cache inclusion policy <NUM>. Further, as a result of the cacheline eviction at the L2 cache, the L2 cache broadcasts a coherency message to the other caches at block <NUM> to reflect eviction of the cacheline so that the other caches update their local presence information stores accordingly.

<FIG> illustrates a method <NUM> for implementing a corresponding aspect of the hybrid lower-level cache inclusion policy <NUM> at an L3 cache, such as L3 cache <NUM>, in accordance with some embodiments. The method <NUM> initiates at block <NUM> with the L3 cache determining that a cacheline is to be evicted. Accordingly, the L3 control logic (e.g., L3 control logic <NUM>) marks the cacheline as invalid in the status field of the tag entry corresponding to the cacheline and transmits a coherency message to the other caches of the cache hierarchy <NUM> indicating that the L3 cache has evicted the cacheline. In some implementations, eviction of a cacheline from an L3 cache results in the cacheline, if modified, being provided to the system memory <NUM> so as to overwrite the original data. Further, at block <NUM> the other caches of the cache hierarchy <NUM> update their local location stores in response to the coherency message being transmitted by the L3 cache.

As explained above, one aspect or guideline of the hybrid lower-level cache inclusion policy <NUM> is that eviction of a cacheline from the L3 cache level requires eviction of the cacheline from the L1 cache level as a result unless that cacheline is also present in an L2 cache. This guideline permits the cache hierarchy <NUM> to determine on any subsequent accesses to the cacheline that the cacheline is not in the L1 cache strictly by looking in the L2 and L3 caches and without requiring a search of the L1 cache, and thus saving power and improving performance. Accordingly, at block <NUM>, the cache hierarchy <NUM> determines whether the cacheline evicted from the L3 cache is present in an L2 cache. In some implementations, this is determined by the coherency logic <NUM> of the L3 control logic <NUM> of the L3 cache that evicted the cacheline using the presence field <NUM> of the corresponding tag entry <NUM> in the L3 cache. In other embodiments, the presence of the evicted cacheline in an L2 cache is collectively determined by the coherency logic <NUM> of the L2 control logic <NUM> of the one or more L2 caches of the cache hierarchy using the presence fields <NUM> of the corresponding tag entries <NUM> of the L2 caches. In yet other embodiments, the presence of the evicted cacheline in an L2 cache is collectively determined by the coherency logic <NUM> of the L1 control logic <NUM> of the one or more L1 caches of the cache hierarchy <NUM>.

If the cacheline is identified to be present in an L2 cache, at block <NUM> the cacheline is maintained in the L2 cache and the current iteration of method <NUM> terminates. Otherwise, if no copy of the evicted cacheline is found in the L2 cache level, at block <NUM> the cache hierarchy <NUM> evicts the cacheline from the L1 cache level as well. If presence of the evicted cacheline at the L2 cache level was performed by the L1 cache at block <NUM>, then at block <NUM> the coherency logic <NUM> of the L1 caches trigger the eviction of the cacheline from their respective data arrays <NUM>. Otherwise, if presence of the evicted cacheline at the L2 cache level was performed at the L2 cache level or the L3 cache level, then a cache at that lower cache level sends an eviction message to the one or more L1 caches of the cache hierarchy <NUM> via the messaging interconnect <NUM>, in response to which the L1 caches evict the identified cacheline. Further, at block <NUM>, the caches of the cache hierarchy <NUM> update their local presence information stores in response to the eviction message transmitted in response to the eviction of the copy of the cacheline from the one or more L1 caches so as to reflect that the cacheline is no longer present in the L1 cache level.

In accordance with one aspect, a data processing system includes one or more processor cores and a cache hierarchy. The cache heirarchy has a first-level cache, a second-level cache, and a third-level cache, and cache hierarchy control logic configured to implement a caching policy in which each cacheline cached in the first-level cache has a copy of the cacheline cached in at least one of the second-level cache and the third-level cache. In some embodiments, the caching policy further provides that an eviction of a cacheline from the second-level cache does not trigger an eviction of a copy of that cacheline from the first-level cache. In some embodiments, the caching policy further provides that an eviction of a cacheline from the third-level cache triggers the cache hierarchy control logic to evict a copy of that cacheline from the first-level cache when the cacheline is not present in the second-level cache. The caching policy further can provide that an eviction of a cacheline from the third-level cache triggers the cache hierarchy control logic to: evict a copy of that cacheline from the first-level cache when a copy of that cacheline is not present in the second-level cache; and maintain the copy of that cacheline in the first-level cache when a copy of that cacheline is present in the second-level cache.

In some embodiments, the third-level cache has access to a first set of presence fields to store first presence information identifying which cachelines in the third-level cache are also stored in either of the first-level cache or the second-level cache. In some embodiments, the first presence information indifies only whether a corresponding cacheline is in one of the first-level cache or the second-level cache. In other embodiments, he first presence information identifies whether a corresponding cacheline is in the first-level cache and whether the corresponding cacheline is in the second-level cache. In some embodiments, the cache hierarchy comprises multiple first-level caches and multiple second-level caches, and the first presence information identifies in which first-level cache of the multiple first-level caches or in which second-level cache of the multiple second-level caches a corresponding cacheline is stored. The first set of presence fields can be part of a tag array of the third-level cache. In some embodiments, the first-level cache has access to a second set of presence fields to store second presence information identifying which cachelines in the first-level cache are also stored in either of the second-level cache or the third-level cache. In some embodmients, the second presence information identifies only whether a corresponding cacheline is in one of the second-level cache or the third-level cache. In other embodiments, the second presence information identifies whether a corresponding cacheline is in the second-level cache and whether the corresponding cacheline is in the third-level cache. The cache hierarchy can include multiple second-level caches and the second presence information can identify in which second-level cache of the multiple second-level caches a corresponding cacheline is stored.

In accordance with another aspect, a method includes fetching a cacheline from memory, storing, by cache hierarchy control logic of a cache hierarchy, the cacheline in a first-level cache of the cache hierarchy, storing, by the cache hierarchy control logic, the cacheline in a second-level cache responsive to a caching policy in which every cacheline in the first-level cache is also stored in at least one of the second-level cache or a third-level cache of the cache hierarchy, and evicting, by the cache hierarchy control logic, the cacheline from the second-level cache while maintaining the cacheline in the first-level cache. In some embodiments, storing, by the cache hierarchy control logic, the cacheline in the second-level cache includes determining, by the cache hierarchy control logic, that neither the first-level cache nor the second-level cache presently stores the cacheline based on presence information stored at the first-level cache, the presence information identifying, for each cacheline stored in the first-level cache, whether that cacheline is also stored in at least one of the second-level cache or the third-level cache. In some embodiments, the presence information identifies whether the cacheline is stored at the second-level cache or stored at the third-level cache. In other embodiments, the cache hierarchy comprises multiple second-level caches and the presence information identifies a particular second-level cache of the multiple second-level caches that stores the cacheline.

In some embodiments, evicting the cacheline from the second-level cache comprises one of: storing the cacheline in the third-level cache; or updating the memory with a modified value of the cacheline. The method therefore further can include evicting, by the cache hierarchy control logic, the cacheline from the third-level cache, determining, by the cache hierarchy control logic, whether the cacheline is present in the second-level cache; and evicting, by the cache hierarchy control logic in accordance with the caching policy, the cacheline from the first-level cache responsive to the eviction of the cacheline from the third-level cache and responsive to determining the cacheline is not present in the second-level cache. In some embodiments, determining whether the cacheline is present in the second-level cache is based on presence information stored at the third-level cache, the presence information indicating whether, for each cacheline stored in the third-level cache, the cacheline is also present in the second-level cache. In other embodiments, the cache hierarchy comprises multiple second-level caches, and the presence information identifies a particular second-level cache of the multiple second-level caches that stores the cacheline.

In accordance with another aspect, a method includes fetching cachelines from memory, caching the cachelines in a cache hierarchy in accordance with a caching policy, the cache hierarchy having a first-level cache, a second-level cache, and a third-level cache, and wherein the caching policy provides that any cacheline cached in the first-level cache also is stored in at least one of the second-level cache or the third-level cache, that an eviction of a cacheline from the second-level cache does not require eviction of that cacheline from the first-level cache, and that eviction of a cacheline from the third-level cache also evicts that cacheline from the first-level cache unless that cacheline is also cached in the second-level cache. In some embodiments, the cache hierarchy control logic implements the caching policy using presence information stored at one or more of the first-level cache, the second-level cache, or the third-level cache, the presence information at a cache of a given cache level indicating whether a cacheline stored at a cache of the given cache level is stored at one or more other cache levels of the cache.

In some embodiments, the apparatus and techniques described above are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the system <NUM> described above with reference to <FIG>. Electronic design automation (EDA) and computer aided design (CAD) software tools may be used in the design and fabrication of these IC devices. These design tools typically are represented as one or more software programs. The one or more software programs include code executable by a computer system to manipulate the computer system to operate on code representative of circuitry of one or more IC devices so as to perform at least a portion of a process to design or adapt a manufacturing system to fabricate the circuitry. This code can include instructions, data, or a combination of instructions and data. The software instructions representing a design tool or fabrication tool typically are stored in a computer readable storage medium accessible to the computing system. Likewise, the code representative of one or more phases of the design or fabrication of an IC device may be stored in and accessed from the same computer readable storage medium or a different computer readable storage medium.

A computer readable storage medium may include any non-transitory storage medium, or combination of non-transitory storage media, accessible by a computer system during use to provide instructions and/or data to the computer system.

The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer readable storage medium.

Claim 1:
A data processing system, comprising:
one or more processor cores (<NUM>); and
a cache hierarchy comprising:
a first-level cache (<NUM>);
a second-level cache (<NUM>);
a third-level cache (<NUM>); and
cache hierarchy control logic (<NUM>) configured to implement a caching policy in which each cacheline cached in the first-level cache has a copy of the cacheline cached in at least one of the second-level cache and the third-level cache and in which an eviction of a cacheline from the third-level cache triggers the cache hierarchy control logic to evict a copy of that cacheline from the first-level cache based on the copy of the cacheline not being present in the second-level cache.