Patent Description:
Organic Light Emitting Diode (OLED) display devices and Quantum dots Light-emitting Diode (QLED) display devices are self-luminous display devices, and these self-luminous display devices include pixel electrodes which are used as an anode, a common electrode which is a cathode, and a light emitting layer provided between the pixel electrodes and the common electrode. The light emitting layer is capable of emitting light when an appropriate voltage is applied between the anode and the cathode.

<CIT> discloses an organic light-emitting display device including a first electrode disposed on a substrate, a plurality of insulating layers which are sequentially disposed on the first electrode, and on which a contact hole for exposing a part of a surface of the first electrode is formed; and an organic light-emitting diode which includes a pixel electrode disposed on the plurality of insulating layers, a second electrode facing the pixel electrode and contacting the first electrode through the contact hole, and an organic emissive layer disposed between the pixel electrode and the second electrode.

<CIT> discloses an OLED device. A switching thin-film transistor configured to be an oxide semiconductor thin-film transistor is disposed in a first pixel. A second pixel is adjacent to the first pixel in the direction in which data lines are extended. A switching thin-film transistor configured to be an LTPS (low temperature poly-silicon) thin-film transistor is disposed in the second pixel. The switching thin-film transistor of the first pixel and the switching thin-film transistor of the second pixel are connected to the same gate line.

An array substrate is defined according to claim <NUM>.

In the claimed embodiment the portion facing towards the third electrode plate of at least one of the first electrode plate and the second electrode is bent toward a direction of the third electrode plate.

In some embodiments, the at least three electrode plates parallel to each other further include a fourth electrode plate, the fourth electrode plate is electrically connected to the first electrode plate and is disposed between the first electrode plate and the third electrode plate, and the fourth electrode plate has a portion facing towards the third electrode plate.

In the claimed embodiment each pixel unit includes in turn an active layer, a gate insulation layer, a gate electrode of a first thin film transistor (TFT), an interlayer insulation layer, a source electrode and a drain electrode of the first TFT which are disposed in a same layer, a passivation layer, and a pixel electrode on a base substrate;
the drain electrode of the first TFT is electrically connected to the pixel electrode through a first via hole penetrating the passivation layer; the active layer is integrated with the first electrode plate; and the pixel electrode is integrated with the second electrode plate.

In the claimed embodiment the third electrode plate and the drain electrode of the first TFT are disposed in a same layer.

In some embodiments, in the array substrate, the third electrode plate is electrically connected to the gate electrode of the first TFT through a second via hole penetrating the interlayer insulation layer.

In some embodiments, the array substrate further includes a second TFT, a data line, and a gate line, wherein a source electrode of the second TFT is connected to the data line, a gate electrode of the second TFT is connected to the gate line, and the source electrode of the second TFT, a drain electrode of the second TFT, the source electrode of the first TFT, and the drain electrode of the first TFT are disposed in a same layer, the gate electrode of the second TFT and the gate electrode of the first TFT are disposed in a same layer; wherein the drain electrode of the second TFT is electrically connected to the gate electrode of the first TFT through a third via hole penetrating the interlayer insulation layer.

In some embodiments, the at least three electrode plates parallel to each other further include a fourth electrode plate which is electrically connected to the first electrode plate and has a portion facing towards the third electrode plate, the fourth electrode plate and the gate electrode of the first TFT are disposed in a same layer.

In some embodiments, the fourth electrode plate is electrically connected to the first electrode plate through a fourth via hole penetrating the gate insulation layer.

In some embodiments, a planarization layer is provided between the passivation layer and the pixel electrode, a recess is provided in a portion of the planarization layer facing towards the third electrode plate, the second electrode plate is deposited on the planarization layer and forms a bending part at the recess; and/or
a protrusion is provided at a portion of the base substrate facing towards the third electrode plate, the first electrode plate is deposited on the substrate, and the first electrode plate forms a bending part at the protrusion.

In some embodiments, the array substrate further includes an anode, a cathode, and a light emitting layer provided between the anode and the cathode, wherein the pixel electrode is the anode, the light emitting layer is disposed at a side of each pixel unit, and the light emitting layer is an organic light emitting layer or a quantum dot light emitting layer.

A display panel is claimed according to the features of claim <NUM>.

A display device is claimed according to the features of claim <NUM>.

<FIG> is a structural diagram of a driving circuit of a pixel unit in an OLED display. As shown in <FIG>, the driving circuit includes a thin film transistor (TFT) T1 provided for driving the OLED, a thin film transistor T2 provided for controlling switch of the OLED, and a storage capacitor C.

A gate electrode of the thin film transistor T2 (also referred to as the switch TFT) is connected to a gate line G1, a source electrode of the thin film transistor T2 is connected to a data line D1, and a drain electrode of the thin film transistor T2 is connected to a gate electrode of the thin film transistor T1 (also referred to as the driving TFT). A source electrode of the thin film transistor T1 is connected to a power source line Vdd, and a drain electrode of the thin film transistor T1 is connected to a pixel electrode (the anode of the organic light emitting diode (OLED) OL1). A first electrode C1 of the storage capacitor C is connected to the drain electrode of the thin film transistor T2 and the gate electrode of the thin film transistor T1, a second electrode C2 of the storage capacitor C is connected to the drain electrode of the thin film transistor T1 and the anode electrode of OL1.

In the driving circuit of the OLED display shown in <FIG>, the larger the capacitance value of the storage capacitor C is, the greater by the influence of the leakage current of the thin film transistor T1 on the display image of the OLED display, and the more stable the image quality of the display image is. Therefore, increasing the capacitance value of the storage capacitor C becomes a method for improving the stability of the display image.

In order to increase the capacitance value of the storage capacitor C, it is usually necessary to increase the facing area of the two electrodes of the storage capacitor. However, under the condition that the display area (the area of the display region of the display panel) is limited, the capacitance value cannot be increased significantly through this method.

Some embodiments of the present disclosure provide an array substrate. The array substrate includes a plurality of pixel units, wherein each pixel unit has a storage capacitor provided thereon. The storage capacitor includes at least three electrode plates parallel to each other, the at least three electrode plates parallel to each other include a first electrode plate, a second electrode plate and a third electrode plate, wherein the first electrode plate is electrically connected to the second electrode plate, the third electrode plate is disposed between the first electrode plate and the second electrode plate, the first electrode plate has a portion facing towards the third electrode plate, and the second electrode plate has a portion facing towards the third electrode plate.

In the array substrate provided by the above embodiment, the storage capacitor of each pixel unit includes at least three electrode plates parallel to each other, the third electrode plate provided between the first electrode plate and the second electrode plate faces towards the first electrode plate and the second electrode plate, respectively, and thus forming the storage capacitor. Compared with the related art, the distance between the electrode plates is reduced, and the overall capacitance value of the storage capacitor is increased by increasing the number of electrode plates of the storage capacitor without increasing the area occupied by the storage capacitor.

<FIG> is a schematic plan view of a structure of an array substrate provided by some embodiments. <FIG> is a sectional view of the array substrate taken along a line AA' in <FIG> provided by some embodiments. Referring to <FIG> and <FIG>, the array substrate includes a plurality of pixel units <NUM>, each pixel unit <NUM> includes a first TFT <NUM>, a second TFT <NUM>, a pixel electrode <NUM> and a storage capacitor.

The array substrate applied in the OLED display is described in the following. As shown in <FIG>, in the array substrate of the OLED display, the pixel electrode <NUM> is the anode of the OLED.

In some embodiments, referring to <FIG> and <FIG>, and in conjunction with <FIG>, the array substrate further includes gate lines <NUM>, data lines <NUM> and power source lines (Vdd) <NUM>. A gate electrode of the second TFT <NUM> is connected to the gate line <NUM>, a source electrode of the second TFT <NUM> is connected to the data line <NUM>, and a drain electrode of the second TFT <NUM> is connected to the gate electrode of the first TFT <NUM>. A source electrode of the first TFT <NUM> is connected to Vdd <NUM>, and a drain electrode of the first TFT <NUM> is connected to the pixel electrode (i.e., the anode of the OLED) <NUM>.

Referring to <FIG>, each pixel unit <NUM> including the above components in the array substrate is provided on a base substrate <NUM>. Taking a partial cross section of the array substrate taken along the line AA' as an example, each pixel unit <NUM> includes an active layer <NUM>, a gate insulation layer <NUM>, the gate electrode <NUM> of the first TFT <NUM>, an interlayer insulation layer <NUM>, the source electrode <NUM> of the first TFT <NUM> (which is provided in a same layer as that of the drain electrode <NUM> of the first TFT <NUM>), a passivation layer <NUM> and a pixel electrode <NUM> provided on the base substrate <NUM> in sequence.

In some embodiments, the base substrate <NUM> is a glass substrate.

In some embodiments, each pixel unit <NUM> further includes a storage capacitor. Referring to <FIG> and <FIG>, the storage capacitor includes a first electrode plate <NUM>, a second electrode plate <NUM> and a third electrode plate <NUM>. The first electrode plate <NUM> is electrically connected to the second electrode plate <NUM>, the third electrode plate <NUM> is disposed between the first electrode plate <NUM> and the second electrode plate <NUM>, and the first electrode plate <NUM> and the second electrode plate <NUM> each have a portion facing towards the third electrode plate <NUM>.

Compared with a storage capacitor having two electrode plates, the array substrate provided in the embodiment shown in <FIG> and <FIG> has an increased number of electrode plates and a reduced distance between the electrode plates, and thereby the overall capacitance value of the storage capacitor is increased without increasing the area occupied by the storage capacitor.

In some embodiments, referring to <FIG>, the active layer <NUM> is integrated with the first electrode plate <NUM>, and the pixel electrode <NUM> is integrated with the second electrode plate <NUM>.

In some embodiments, the drain electrode <NUM> of the first TFT <NUM> is connected to the pixel electrode <NUM> through a first via hole <NUM> penetrating the passivation layer <NUM>, and also connected to the active layer <NUM>. Based on such structure, the first electrode plate <NUM> is connected to the drain electrode <NUM> of the first TFT <NUM>, and the second electrode plate <NUM> is also connected to the drain electrode <NUM> of the first TFT <NUM>, and thereby the first electrode plate <NUM> is electrically connected to the second electrode plate <NUM>. The third electrode plate <NUM> is disposed between the first electrode plate <NUM> and the second electrode plate <NUM>, and faces towards the first electrode plate <NUM> and the second electrode plate <NUM>, respectively. Thus, a capacitor formed by the third electrode plate <NUM> and the first electrode plate <NUM> and a capacitor formed by the third electrode plate <NUM> and the second electrode plate <NUM> form two capacitors in parallel. The capacitance value of the two parallel capacitors is larger than a capacitance value of a storage capacitor formed by only two electrode plates.

In some embodiments, as shown in <FIG>, the third electrode plate <NUM> and the drain electrode <NUM> of the first TFT <NUM> are provided in a same layer.

In some embodiments, referring to <FIG> and <FIG>, in a pixel unit <NUM>, the source electrode <NUM> of the second TFT <NUM>, the drain electrode <NUM> of the second TFT <NUM>, the source electrode <NUM> of the first TFT <NUM> and the drain electrode <NUM> of the first TFT <NUM> are provided in a same layer, and the gate electrode <NUM> of the second TFT <NUM> and the gate electrode <NUM> of the first TFT <NUM> are provided in a same layer.

In some embodiments, as shown in <FIG> and <FIG>, if the storage capacitor includes the first electrode plate <NUM>, the second electrode plate <NUM> and the third electrode plate <NUM>, the third electrode plate <NUM> is electrically connected to the gate electrode <NUM> of the first TFT <NUM> through a second via hole <NUM> penetrating the interlayer insulation layer <NUM>, and the drain electrode <NUM> of the second TFT <NUM> is electrically connected to the gate electrode <NUM> of the first TFT <NUM> through a third via hole <NUM> penetrating the interlayer insulation layer <NUM>.

Referring to <FIG>, <FIG> and <FIG>, the third electrode plate <NUM> is connected to the gate electrode <NUM> of the first TFT <NUM>, forming one electrode plate C1 of the storage capacitor; meanwhile, the first electrode plate <NUM> and the second electrode plate <NUM> electrically connected with each other are connected to the pixel electrode <NUM>, forming the other electrode plate C2 of the storage capacitor. Thus, the capacitor including three electrode plates is connected to other components in the pixel unit.

In some embodiments, the first electrode plate of the storage capacitor is integrated with the active layer; thus, during the manufacturing of the array substrate, after the active layer is prepared using a semiconductor, a part of the active layer is ionized to complete the preparation of the first electrode plate. The second electrode of the storage capacitor is integrated with the pixel electrode; thus, by preparing the pixel electrode, the second electrode plate is also prepared.

In some embodiments, since the third electrode plate and the drain electrode of the first TFT are provided in the same layer, the third electrode plate is also prepared by manufacturing the drain electrode of the first TFT.

Therefore, in the above embodiments, the manufacturing process of the three electrode plates of the storage capacitor is simple and convenient, and does not increase complicated manufacturing processes.

In some embodiments, as shown in <FIG>, the pixel electrode <NUM> is provided on a planarization layer <NUM>, and the first via hole <NUM> also penetrates the planarization layer <NUM>.

In some embodiments, the gate electrode of the first TFT <NUM>, the source electrode of the first TFT <NUM>, the drain electrode of the first TFT <NUM>, the gate electrode of the second TFT <NUM>, the source electrode of the second TFT <NUM>, the drain electrode of the second TFT <NUM> are made of one or at least two of the metal materials Cu, Al, Mo, Ti, Cr and W.

In some embodiments, the gate electrode of the first TFT <NUM>, the source electrode of the first TFT <NUM>, the drain electrode of the first TFT <NUM>, the gate electrode of the second TFT <NUM>, the source electrode of the second TFT <NUM>, the drain electrode of the second TFT <NUM> each have a single-layer structure.

In some embodiments, the gate electrode of the first TFT <NUM>, the source electrode of the first TFT <NUM>, the drain electrode of the first TFT <NUM>, the gate electrode of the second TFT <NUM>, the source electrode of the second TFT <NUM>, the drain electrode of the second TFT <NUM> each have a multilayer structure including at least two layers.

In some embodiments, the gate insulation layer <NUM> is made of silicon nitride or silicon oxide.

In some embodiments, the gate insulation layer <NUM> has a single-layer structure.

In some embodiments, the gate insulation layer <NUM> has a multilayer structure including at least two layers. For example, the gate electrode insulation layer includes a silicon oxide layer and a silicon nitride layer.

In some embodiments, the passivation layer <NUM> is made of silicon nitride or silicon oxide.

In some embodiments, the passivation layer <NUM> has a single-layer structure.

In some embodiments, the passivation layer <NUM> has a multilayer structure including at least two layers. For example, the passivation layer <NUM> includes a silicon oxide layer and a silicon nitride layer.

In some embodiments, as shown in <FIG>, an anode of the OLED, a cathode <NUM>, and a light emitting layer <NUM> between the anode and the cathode <NUM> are provided on the array substrate in the OLED display. According to the above descriptions, the anode of the OLED is the above pixel electrode <NUM>.

In some embodiments, referring to <FIG>, a light emitting layer <NUM> is provided at a side of each pixel unit on the array substrate of the OLED display panel, and the light emitting layer <NUM> is an organic light emitting layer.

In some embodiments, the anode of the OLED is made of indium tin oxide (ITO).

In some embodiments, the anode of the OLED has an ITO/Ag/ITO structure made of ITO and Ag.

In some embodiments, the cathode of the OLED is made of Al or Ag.

In some embodiments, the storage capacitor includes the first electrode plate <NUM>, the second electrode plate <NUM> and the third electrode plate <NUM>, a portion of at least one of the first electrode plate <NUM> and the second electrode plate <NUM> facing towards the third electrode plate is bent toward the third electrode plate <NUM>.

Since the portion of at least one of the first electrode plate <NUM> and the second electrode plate <NUM> facing towards the third electrode plate is bent toward the third electrode plate <NUM>, the distance between the third electrode plate and the bent electrode plate is reduced, and the capacitance value of the storage capacitor is increased.

<FIG> is a sectional view of the array substrate taken along the line AA' in <FIG> provided by other embodiments. Similar to the structure shown in <FIG>, in the structure of the array substrate shown in <FIG>, each pixel unit <NUM> includes the active layer <NUM>, the gate insulation layer <NUM>, the gate electrode <NUM> of the first TFT <NUM>, the interlayer insulation layer <NUM>, the source electrode <NUM> of the first TFT <NUM> (which is provided in a same layer as that of the drain electrode <NUM> of the first TFT <NUM>), the passivation layer <NUM> and a pixel electrode <NUM> provided on the base substrate <NUM> in sequence. Each pixel unit <NUM> further includes the storage capacitor. Referring to <FIG> and <FIG>, the storage capacitor includes the first electrode plate <NUM>, the second electrode plate <NUM> and the third electrode plate <NUM>. The first electrode plate <NUM> is electrically connected to the second electrode plate <NUM>, the third electrode plate <NUM> is disposed between the first electrode plate <NUM> and the second electrode plate <NUM>, and the first electrode plate <NUM> and the second electrode plate <NUM> each have a portion facing towards the third electrode plate <NUM>.

The array substrate shown in <FIG> is the same as the implemented structure of the array substrate shown in <FIG>. The active layer <NUM> is integrated with the first electrode plate <NUM>, the pixel electrode <NUM> is integrated with the second electrode plate <NUM>, and the third electrode plate <NUM> is provided in a same layer as that of the drain electrode <NUM> of the first TFT <NUM>.

On the basis of the above structure, as shown in <FIG>, a planarization layer <NUM> is further provided between the passivation layer <NUM> and the pixel electrode <NUM>. A recess <NUM> is provided in a portion of the planarization layer <NUM> facing towards the third electrode plate <NUM>, the second electrode plate <NUM> is deposited on the planarization layer <NUM>, and the second electrode plate <NUM> forms a bending part at the recess <NUM>.

Compared with the structure of the array substrate shown in <FIG>, the structure of the array substrate in <FIG> reduces the distance between the portions of the second and the third electrode plates <NUM> and <NUM> facing towards the third electrode plate <NUM>, increasing the capacitance value of the storage capacitor.

In some embodiments, a protrusion is provided at a portion of the base substrate <NUM> facing towards the third electrode plate <NUM>, causing the first electrode plate <NUM> to form a bending part at the protrusion when the first electrode plate is deposited on the substrate. Thus, compared with the structure of the array substrate shown in <FIG>, such structure reduces the distance between the portions of the second and the third electrode plates <NUM> and <NUM> facing towards the third electrode plate <NUM>, increasing the capacitance value of the storage capacitor.

In the structure of the array substrate shown in <FIG>, the connection manners for the first TFT <NUM>, the second TFT <NUM>, the pixel electrode <NUM>, the first electrode plate <NUM>, the second electrode plate <NUM>, and the third electrode plate <NUM> are the same as those of the above components in the array substrate shown in <FIG>.

The array substrate provided by the above embodiment is described by taking a storage capacitor including three electrode plates as an example.

In some embodiments, the number of the electrode plates included in the storage capacitor is greater than <NUM>.

In some embodiments, in addition to the first, the second and the third electrode plates <NUM>, <NUM> and <NUM> included in the storage capacitor in the above embodiment, the storage capacitor further includes a fourth electrode plate which is electrically connected to the first electrode plate <NUM>, and is disposed between the first electrode plate <NUM> and the third electrode plate <NUM>. The fourth electrode plate has a portion facing towards the third electrode plate <NUM>.

In the above embodiment, by further providing the fourth electrode plate electrically connected to the first electrode plate <NUM> between the first electrode plate <NUM> and the third electrode plate <NUM>, the distance between two opposite electrode plates is reduced, increasing the capacitance value of the storage capacitor.

In some embodiments, on the basis of the structure of the array substrate of the above embodiment, the storage capacitor further includes a fifth electrode plate which is disposed between the second electrode plate <NUM> and the third electrode plate <NUM>, and is electrically connected to the second electrode plate <NUM>, reducing the distance between the two opposite electrode plates, and increasing the capacitance value of the storage capacitor.

In some embodiments, referring to <FIG> and <FIG>, the structure of the array substrate shown therein is the same as those in the above embodiments. The array substrate includes a plurality of pixel units <NUM>, and each pixel unit <NUM> includes a first TFT <NUM>, a second TFT <NUM>, a pixel electrode <NUM> and a storage capacitor.

The array substrate further includes gate lines <NUM>, data lines <NUM> and power source lines (Vdd) <NUM>. A gate electrode of the second TFT <NUM> is connected to the gate line <NUM>, a source electrode of the second TFT <NUM> is connected to the data line <NUM>, and a drain electrode of the second TFT <NUM> is connected to the gate electrode of the first TFT <NUM>. A source electrode of the first TFT <NUM> is connected to Vdd <NUM>, and a drain electrode of the first TFT <NUM> is connected to the pixel electrode <NUM>.

Referring to <FIG>, each pixel unit <NUM> including the above components in the array substrate is provided on a base substrate <NUM>. Taking a partial cross section of the array substrate taken along the line DD' as an example, each pixel unit <NUM> includes in sequence an active layer <NUM>, a gate insulation layer <NUM>, the gate electrode <NUM> of the first TFT <NUM>, an interlayer insulation layer <NUM>, the source electrode <NUM> of the first TFT <NUM> (the drain electrode <NUM> of the first TFT <NUM> is provided in a same layer as that of the source electrode <NUM> of the first TFT <NUM>), a passivation layer <NUM> and a pixel electrode <NUM> provided on the base substrate 1on the base substrate <NUM>.

Referring to <FIG>, each pixel unit <NUM> further includes a storage capacitor. Referring to <FIG> and <FIG>, the storage capacitor includes a first electrode plate <NUM>, a second electrode plate <NUM>, a third electrode plate <NUM> and a fourth electrode plate <NUM>. The first electrode plate <NUM>, the second electrode plate <NUM>, and the fourth electrode plate <NUM> are electrically connected to each other. The third electrode plate <NUM> is disposed between the fourth electrode plate <NUM> and the second electrode plate <NUM>, and the first electrode plate <NUM>, the second electrode plate <NUM> and the fourth electrode plate <NUM> each have a portion facing towards the third electrode plate <NUM>.

In some embodiments, the active layer <NUM> is integrated with the first electrode plate <NUM>, the pixel electrode <NUM> is integrated with the second electrode plate <NUM>, the third electrode plate <NUM> is provided in a same layer as that of the drain electrode <NUM> of the first TFT <NUM>, and the fourth electrode plate <NUM> is provided in a same layer as that of the gate electrode <NUM> of the first TFT <NUM>.

In some embodiments, as shown in <FIG>, a planarization layer <NUM> is further provided between the passivation layer <NUM> and the pixel electrode <NUM>. A recess <NUM> is provided in a portion of the planarization layer <NUM> facing towards the third electrode plate <NUM>, the second electrode plate <NUM> is deposited on the planarization layer <NUM>, and the second electrode plate <NUM> forms a bending part at the recess <NUM>.

In some embodiments, referring to <FIG> and <FIG>, the drain electrode <NUM> of the first TFT <NUM> is connected to the pixel electrode <NUM> through a first via hole <NUM> penetrating the passivation layer <NUM>. The drain electrode <NUM> of the first TFT <NUM> is also connected to the active layer <NUM>. The first electrode plate <NUM> is electrically connected to the second electrode plate <NUM>. Furthermore, the fourth electrode plate is electrically connected to the first electrode plate <NUM> through a fourth via hole <NUM> penetrating the gate insulation layer <NUM>. The first electrode plate <NUM>, the second electrode plate <NUM> and the fourth electrode plate <NUM> are electrically connected to each other.

In some embodiments, in a pixel unit <NUM>, the source electrode <NUM> of the second TFT <NUM>, the drain electrode <NUM> of the second TFT <NUM>, the source electrode <NUM> of the first TFT <NUM> and the drain electrode <NUM> of the first TFT <NUM> are provided in a same layer. The gate electrode <NUM> of the second TFT <NUM> and the gate electrode <NUM> of the first TFT <NUM> are provided in a same layer. The third electrode plate <NUM> is electrically connected to the gate electrode <NUM> of the first TFT <NUM> through a second via hole <NUM> penetrating the interlayer insulation layer <NUM>, and the drain electrode <NUM> of the second TFT <NUM> is electrically connected to the gate electrode <NUM> of the first TFT <NUM> through a third via hole <NUM> penetrating the interlayer insulation layer <NUM>.

In the structure of the above array substrate, as shown in <FIG>, <FIG> and <FIG>, the third electrode plate <NUM> is connected to the gate electrode <NUM> of the first TFT <NUM>, forming one electrode plate C1 of the storage capacitor; meanwhile, the first, the second and the third electrode plates <NUM>, <NUM> and <NUM> electrically connected with each other are connected to the pixel electrode <NUM>, forming the other electrode plate C2 of the storage capacitor. Thus, the capacitor including four electrode plates is connected to other components in the pixel unit.

In the embodiment shown in <FIG> and <FIG>, by bending the portion of the second electrode plate <NUM> facing towards the third electrode plate <NUM> to a direction of the third electrode plate, and providing the fourth electrode plate between the third electrode plate <NUM> and the first electrode plate <NUM>, the distance between the multiple electrode plates is reduced and the capacitance value of the storage capacitor is increased, compared with the array substrates in the embodiments shown in <FIG>.

The above embodiments are described by taking an array substrate in the OLED display panel.

In some embodiments, the array substrates in the above OLED display panel are applicable to a QLED display panel.

In some embodiments, the array substrate in the QLED includes an anode, a cathode, and a light emitting layer located between the anode and the cathode. When the array substrate in the OLED display panel is applied to the QLED display panel, the light emitting layer is provided at a side of each pixel unit, the light emitting layer is a quantum dot light emitting layer, and the pixel electrode is the anode.

Some embodiments provide a display panel which includes the array substrate in any of the above embodiments.

Some embodiments provide a display device which includes the above display panel.

Claim 1:
An array substrate comprising a plurality of pixel units, wherein each pixel unit comprises a storage capacitor comprising at least three electrode plates parallel to each other, the at least three electrode plates parallel to each other comprise at least a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate is electrically connected to the second electrode plate, the third electrode plate is disposed between the first electrode plate and the second electrode plate, and the first electrode plate and the second electrode plate each have a portion facing towards the third electrode plate;
wherein the portion facing towards the third electrode plate of at least one of the first electrode plate and the second electrode is bent toward a direction of the third electrode plate;
wherein each pixel unit comprises in turn an active layer, a gate insulation layer, a gate electrode of a first thin film transistor (TFT), an interlayer insulation layer, a source electrode and a drain electrode of the first TFT which are disposed in a same layer, a passivation layer, and a pixel electrode on a base substrate;
the drain electrode of the first TFT is electrically connected to the pixel electrode through a first via hole penetrating the passivation layer; the active layer is integrated with the first electrode plate; and the pixel electrode is integrated with the second electrode plate;
wherein the third electrode plate and the drain electrode of the first TFT are disposed in a same layer.