Patent Description:
As is known, semiconductor materials, which have a Wide Band Gap (WBG), in particular, which have an energy value Eg of the band gap being greater than <NUM> eV, low on-state resistance (RON), a high value of thermal conductivity, high operating frequency and high saturation velocity of charge carriers, are particularly suitable for producing electronic components for power applications, such as MOSFET, JFET, HEMT (High Electron Mobility Transistors) and MISHEMT (Metal-Insulator-Semiconductor High Electron-Mobility Transistors).

A material having similar characteristics, and designed to be used for manufacturing electronic components, is silicon carbide (SiC) in its different polytypes (for example, 3C-SiC, <NUM>-SiC, <NUM>-SiC).

Another example of material which is advantageously exploited for this purpose is gallium nitride (GaN). For example, high-mobility field-effect transistors are known based on the formation of layers of two-dimensional electron gas (2DEG) with high mobility at a heterojunction, that is at the interface between semiconductor materials having different band gap. For example, HEMT transistors are known based on the heterojunction between a layer of aluminum gallium nitride (AlGaN) and a layer of gallium nitride (GaN).

In power transistors made of SiC or GaN, using high-permittivity dielectrics is advantageous to form insulating gate structures. In fact, these materials allow both the electric field inside the insulating gate structures and the on-state resistance RON of the devices to be reduced and, in addition, also entail benefits for the threshold voltage.

The publication "<NPL>, discloses a wide band gap transistor, comprising: a semiconductor structure, including at least one wide band gap semiconductor layer of gallium nitride (GaN); an insulating gate structure; a gate electrode, separated from the semiconductor structure by the insulating gate structure; wherein the insulating gate structure contains a mixture of aluminum, hafnium and oxygen; and wherein in the HAOM insulating gate structure film, the Al<NUM>O<NUM> layers remain amorphous, while the HfO<NUM> layers have fully crystallized.

A problem of high-permittivity materials currently used is linked to the tendency to deteriorate when exposed to high temperatures. In particular, at temperatures commonly reached in some steps of the manufacturing of wide band gap devices, pure high-permittivity materials tend to crystallize and the phase change may lead to an increase in the leakage currents of the devices. For example, the formation of ohmic contacts typically requires high-temperature annealing steps and may cause the crystallization of the high-permittivity dielectrics. Consequently, the process flow has to be organized so as to perform the steps that require high temperatures before forming the insulating gate structures. However, this process sequence may require additional steps otherwise unnecessary which entail an increase in production costs. For example, an additional photolithography needs to be performed to define the ohmic contacts separately from the insulating gate structure.

On the other hand, materials such as silicon oxide tolerate even very high temperatures without degrading, but do not have sufficient permittivity to achieve the high performances often required.

The aim of the present invention is to provide a wide band gap transistor and a process for manufacturing a wide band gap transistor which allow the limitations described to be overcome or at least mitigated.

According to the present invention a wide band gap transistor and a process for manufacturing a wide band gap transistor are provided as defined in claims <NUM> and <NUM> respectively.

For a better understanding of the invention, some embodiments thereof will now be described, purely by way of non-limiting example and with reference to the attached drawings, wherein:.

The invention relates to the manufacture of insulating gate structures in particular in wide band gap transistors. Referring to <FIG>, in general, a wide band gap transistor <NUM> comprises a semiconductor structure <NUM>, wherein at least one layer is of a wide band gap semiconductor material, such as gallium nitride (GaN) or silicon carbide (SiC), a source electrode <NUM>, a drain electrode <NUM> and a gate electrode <NUM>, separated from the semiconductor structure <NUM> by an insulating gate structure <NUM>. More precisely, the semiconductor structure <NUM> may include, in case of a GaN HEMT device, an aluminum gallium nitride (AlGaN) and GaN heterostructure - AlGaN/GaN heterostructure - or, in case of a SiC MOSFET, a SiC substrate with a high doping level (e.g. <NUM><NUM> atoms/cm<NUM> or greater) and a SiC epitaxial layer with a lower doping level (e.g. <NUM><NUM>-<NUM><NUM> atoms/cm<NUM>).

The insulating gate structure <NUM>, illustrated in greater detail in <FIG>, contains a mixture of aluminum, hafnium and oxygen. More precisely, the insulating gate structure <NUM> is obtained by the conformal deposition in alternated succession of a plurality of aluminum oxide layers 8a and a plurality of hafnium oxide layers 8b having nanometer thickness to form a gate stack <NUM>' (<FIG>), followed by an annealing step (<FIG>). The aluminum oxide layers 8a and the hafnium oxide layers 8b may for example have a thickness comprised between <NUM> and <NUM>, are amorphous and are obtained by Atomic Layer Deposition (ALD). The number of layers 8a, 8b is determined so that an overall thickness of the insulating gate structure <NUM> has a desired value, for example comprised between <NUM> and <NUM>. In a non-limiting embodiment, all the aluminum oxide layers 8a and the hafnium oxide layers 8b have equal thickness.

During the annealing step, aluminum oxide and hafnium oxide diffuse at the interfaces between the layers 8a, 8b and mix. Therefore, the mixture of aluminum, hafnium and oxygen is present at least at the interfaces. According to the initial thickness of the aluminum oxide layers 8a and the hafnium oxide layers 8b, the duration and the temperature of the annealing step, in the final insulating gate structure <NUM>, the starting layered structure may be partially preserved (<FIG>) or, alternatively, may be lost (<FIG>). The annealing step may be carried out by heating the gate stack <NUM>' to an annealing temperature comprised between <NUM> and <NUM>, preferably between <NUM> and <NUM>, for example <NUM>. The annealing duration may be comprised between <NUM> and <NUM>. The annealing temperature and the annealing duration are however selected so as to avoid crystallization of the insulating gate structure <NUM>, owing to the diffusion and mixing of aluminum oxide and hafnium oxide. The permittivity and crystallization temperature of the insulating gate structure <NUM> are intermediate between the permittivity and the temperature of the aluminum oxide and those of the hafnium oxide. The insulating gate structure <NUM> has therefore satisfactory permittivity values and, at the same time, is capable of withstanding without structure alterations the thermal stresses that occur during the manufacturing steps of the power devices, for example for the formation of ohmic contacts. Since gate structures do not need to be protected from exposure to high temperatures, the process flow may be optimized so as to avoid unnecessary steps, for example by reducing the number of photolithographs.

<FIG> shows a HEMT device <NUM> provided with an insulating gate structure obtained as described. The HEMT device <NUM> includes: a substrate <NUM>, for example of silicon, or silicon carbide (SiC) or aluminum oxide (Al<NUM>O<NUM>); a channel layer <NUM>, of intrinsic gallium nitride (GaN), extending on the substrate <NUM>; a barrier layer <NUM>, of intrinsic aluminum gallium nitride (AlGaN) or, more generally, of compounds based on ternary or quaternary alloys of gallium nitride, such as AlxGa<NUM>-xN, AlInGaN, InxGa<NUM>-xN, AlxIn<NUM>-xAl, extending on the channel layer <NUM>; an insulating gate structure <NUM>, extending on a face 16a of the barrier layer <NUM> opposite to the channel layer <NUM>; a gate electrode <NUM> extending on the insulating gate structure <NUM> between a source electrode <NUM> and a drain electrode <NUM>.

The channel layer <NUM> and the barrier layer <NUM> form a heterostructure <NUM> with a heterojunction 13a at the interface to each other. The heterostructure <NUM> extends, therefore, between a bottom side of the channel layer <NUM>, which is part of the interface with the underlying substrate <NUM>, and a top side 16a of the barrier layer <NUM>.

The substrate <NUM>, the channel layer <NUM> and the barrier layer <NUM> are hereinafter referred to, as a whole, as semiconductor structure <NUM>. An active region 13a, defined in the semiconductor structure <NUM>, accommodates, in use, the conductive channel of the HEMT device <NUM>. In the embodiment of <FIG>, the gate electrode <NUM> extends on the insulating gate structure <NUM> in a zone corresponding to the active region 13a.

The insulating gate structure <NUM>, provided as already illustrated with reference to <FIG>, contains a mixture of aluminum, hafnium and oxygen. More precisely, the insulating gate structure <NUM> is obtained by the conformal deposition in alternated succession of a plurality of aluminum oxide layers 17a and a plurality of hafnium oxide layers 17b having nanometer or sub-nanometer thickness, followed by an annealing step. The aluminum oxide layers 17a and the hafnium oxide layers 17b are amorphous.

According to further embodiments not shown, the semiconductor body <NUM> and well as the active region 13a accommodated therein, may comprise, according to the design preferences, a single layer or multiple layers of GaN, or GaN alloys, suitably doped or of an intrinsic type.

In the embodiment of <FIG>, the source <NUM> and drain regions <NUM>, of conductive material, for example metal, extend exclusively through the insulating gate layer <NUM>, until they reach the surface 16a of the barrier layer <NUM>, without going deep into the barrier layer <NUM>.

According to embodiments not shown, the source regions <NUM> and the drain regions <NUM> extend for a part of the thickness of the barrier layer <NUM>, terminating inside the barrier layer <NUM>.

According to further embodiments not shown, the source regions <NUM> and the drain regions <NUM> extend in depth into the semiconductor body <NUM>, completely through the barrier layer <NUM>, terminating at the interface between the barrier layer <NUM> and the channel layer <NUM>.

According to further embodiments not shown, the source regions <NUM> and the drain regions <NUM> further extend partially through the channel layer <NUM> and terminate into the channel layer <NUM>.

An example of a manufacturing process of the HEMT device <NUM> will be described below with reference to <FIG>.

Initially, <FIG>, a semiconductor wafer <NUM> comprises the substrate <NUM>, for example of silicon or silicon carbide (SiC) or aluminum oxide (Al<NUM>O<NUM>). The channel layer <NUM>, of gallium nitride (GaN), and the barrier layer <NUM>, of aluminum gallium nitride (AlGaN), are formed on the substrate <NUM>, extending on the channel layer <NUM>. The barrier layer <NUM> and the channel layer <NUM> form, as previously mentioned, the heterostructure <NUM> and the heterojunction 13a.

A gate stack <NUM>' is then formed, as described with reference to <FIG>. In particular, the gate stack <NUM>' is obtained by the conformal deposition in alternated succession of a plurality of aluminum oxide layers 17a (Al<NUM>O<NUM>) and a plurality of hafnium oxide layers 17b (HfO<NUM>) having nanometer thickness, until they reach a desired overall thickness. The aluminum oxide layers 17a and the hafnium oxide layers 17b are amorphous and are formed by Atomic Layer Deposition (ALD), which ensures structure conformality and extremely accurate thickness control.

Subsequently (<FIG>), a first sacrificial layer <NUM>, for example of resist, is formed on the gate stack <NUM>' and defined by a first photolithographic process. The first sacrificial layer <NUM> has openings <NUM> for the formation of the source electrode <NUM> and of the drain electrode <NUM>. The first sacrificial layer <NUM> is used as a mask to selectively etch the gate stack <NUM>' through the openings <NUM>.

Referring to <FIG>, following the deposition of a metal layer or multilayer and the lift-off of the first sacrificial layer <NUM>, the source electrode <NUM> and the drain electrode <NUM> are formed in positions corresponding to respective openings <NUM>.

An annealing step is then performed at a temperature comprised for example between <NUM> and <NUM>, preferably between <NUM> and <NUM>, for the formation of ohmic contacts. At the same time, the aluminum oxide layers 17a and the hafnium oxide layers 17b that are adjacent diffuse into each other at the respective interfaces and the insulating gate structure <NUM> is formed from the residual portions of the gate stack <NUM>', as shown in <FIG>. The number and thicknesses of the aluminum oxide layers 17a and the hafnium oxide layers 17b, the annealing temperature and the annealing duration are selected according to the design preferences so that the insulating gate structure <NUM> maintains (as in the example of <FIG>) or does not maintain traces (as in the example of <FIG>) of the starting layers 17a, 17b and crystallization is avoided.

A second sacrificial layer <NUM> (<FIG>) is then formed on the insulating gate structure <NUM>, on the source electrode <NUM> and on the drain electrode <NUM> and defined by a second photolithographic process. The second sacrificial layer <NUM> has an opening <NUM> for the formation of the gate electrode <NUM>.

Following the deposition of a metal layer or multilayer and the lift-off by plasm or wet etching of the second sacrificial layer <NUM>, the gate electrode <NUM> is formed in a position corresponding to the opening <NUM>. Optionally, a further annealing step may be performed after the deposition of the metal layer or multilayer, for example at <NUM>.

After conventional and not illustrated final processing steps and the dicing of the semiconductor wafer <NUM>, the HEMT device <NUM> of <FIG> is obtained.

The diffusion of the aluminum oxide layers 17a and the hafnium oxide layers 17b during annealing allows a high permittivity value, typically intermediate between the permittivity values of the single intrinsic Al<NUM>O<NUM> and HfO<NUM> layers, to be maintained, while avoiding crystallization of the material during subsequent high temperature processing steps. In particular, the resistance to high temperatures advantageously allows the gate stack <NUM>' to be formed before forming the source and drain electrodes with the respective ohmic contacts without the material being degraded. In this manner a single photolithographic process and a single annealing step may be used to both define the insulating gate structure <NUM> and to form the source and drain electrodes with the respective ohmic contacts.

According to a different embodiment, <FIG>, the gate region, here indicated by <NUM>, may be of a recess type and insulating gate structure <NUM> is not planar. In this case, the barrier layer <NUM> is selectively plasma etched to open a trench <NUM> before forming the insulating multilayer <NUM>', which is conformally deposited by ALD (<FIG>).

Referring to <FIG>, a vertical MOSFET <NUM> comprises a semiconductor structure <NUM> of silicon carbide (SiC), has a drain electrode 100a on a rear side 102a of the semiconductor structure <NUM> and source electrodes 100b and a gate electrode 100c on a front side 102b of the semiconductor structure <NUM>. The semiconductor structure <NUM> in turn comprises a substrate <NUM> (one face whereof defines the rear side 100a) and an epitaxial layer <NUM> (one face whereof defines the front side 102b of the semiconductor structure <NUM>) both having conductivities of a first type, for example of N-type. However, the N-type substrate <NUM> of SiC has a first doping level that is higher (e.g. <NUM><NUM> atoms/cm<NUM> or greater), while the epitaxial layer <NUM> has a second doping level that is lower (e.g. <NUM><NUM>-<NUM><NUM> atoms/cm<NUM>).

Body wells <NUM>, having conductivity of a second type, here P-type, are formed inside the epitaxial layer <NUM> and accommodate respective source regions <NUM>, with conductivity of the first type, in particular N+, and contact regions <NUM>, with conductivity of the second type, in particular P+, and contiguous to respective source regions <NUM>. The epitaxial layer <NUM> defines a Current Spread Layer (CSL) wherein the body wells <NUM> are embedded.

The body wells <NUM> are separated from each other by a distance normally less than <NUM>, for example <NUM>. The body wells <NUM> and the portion of the epitaxial layer <NUM> comprised therebetween form a parasitic JFET region.

An insulating gate structure <NUM> extends on the front side 102a of the semiconductor structure <NUM> on the epitaxial layer <NUM> (or on the enhancement layer <NUM>, if any) between the source regions <NUM> and is surmounted by the gate electrode 100b. The insulating gate structure <NUM>, provided as already illustrated with reference to <FIG>, contains a mixture of aluminum, hafnium and oxygen. More precisely, the insulating gate structure <NUM> is obtained by the conformal deposition in alternated succession of a plurality of aluminum oxide layers and a plurality of hafnium oxide layers having nanometer or sub-nanometer thickness, followed by an annealing step.

An example of a manufacturing process of the MOSFET <NUM> will be described below with reference to <FIG>.

Initially, <FIG>, a semiconductor wafer <NUM> comprises the substrate <NUM>, whereon the epitaxial layer <NUM> is grown to form the semiconductor structure <NUM>. The body wells <NUM>, the source regions <NUM> and the contact regions <NUM> are then formed by subsequent ion implantations of different doping species. After the implantations, an activation annealing step is carried out at a high temperature, for example above <NUM>.

Then (<FIG>), a gate stack <NUM>' is formed, as described with reference to <FIG>. In particular, the gate stack <NUM>' is obtained by the conformal deposition in alternated succession of a plurality of aluminum oxide layers 110a and a plurality of hafnium oxide layers 110b having nanometer thickness, until they reach an overall desired thickness. The aluminum oxide layers 110a and the hafnium oxide layers 17b are formed by Atomic Layer Deposition (ALD).

As shown in <FIG>, a first sacrificial layer <NUM> of resist is formed on the gate stack <NUM>' and defined by a first photolithographic process. The first sacrificial layer <NUM> has openings <NUM> for the formation of the source electrodes 100b and is used as a mask to selectively etch the gate stack <NUM>'.

Referring to <FIG>, following the deposition of a metal layer or multilayer on the front side 102b of the semiconductor structure <NUM> and the lift-off of the first sacrificial layer <NUM>, the source electrodes 100b are formed in positions corresponding to respective openings <NUM>. Simultaneously or subsequently to the deposition on the front side 102b, a metal layer or multilayer is also deposited on the rear side 102a of the semiconductor structure 102e to form the drain electrode 100a. Before depositing the drain electrode 100a, the substrate <NUM> may be mechanically thinned (grinded) and possibly be subject to laser annealing.

Once the drain electrode 100a and the source electrodes 100b have been formed, an annealing step is carried out, for example at an annealing temperature of <NUM> for the formation of silicides. In this step, wherein the gate stack <NUM>' is heated to the annealing temperature, the aluminum oxide and hafnium oxide of the layers 110a, 110b of the gate stack <NUM>' diffuse at the interfaces and mix. Thus, at least at the interfaces, the mixture of aluminum, hafnium and oxygen is present. According to the initial thickness of the aluminum oxide layers <NUM> and the hafnium oxide layers 8b, the duration and the temperature of the annealing step, in the final insulating gate structure <NUM>, the starting layered structure may be partially preserved (as in the example of <FIG>) or, alternatively, may be lost (as in the example of <FIG>).

After annealing (<FIG>), a metal layer or multilayer <NUM>, of a material different from the material used for the source electrodes 100b, is deposited on the insulating gate structure <NUM> and on the source electrodes 100b, then a second sacrificial layer <NUM> of resist is formed on part of the metal layer or multilayer <NUM> and is defined by a second photolithographic process. The second sacrificial layer <NUM> has openings <NUM> for the formation of the gate electrodes 100c. The second sacrificial layer <NUM> is used as a mask to selectively etch the metal layer or multilayer <NUM> through the openings <NUM>, for example by plasma etching. The gate electrode 100c is thus obtained.

After conventional and not illustrated final processing steps and the dicing of the semiconductor wafer <NUM>, the MOSFET <NUM> of <FIG> is obtained.

The insulating gate structure <NUM> and the manufacturing process described allow high-permittivity dielectrics to be used as gate insulators in SiC MOSFETs instead of silicon oxide, for example, with a double advantage. On the one hand, in fact, the high permittivity allows the highest electric field values to be localized within the epitaxial layer <NUM>. It is thus possible to optimize both the thickness of the same epitaxial layer <NUM> and the on-state resistance RON. On the other hand, the process flow is simplified because the nitric oxide post-oxidation annealing steps at high temperature (<NUM> - <NUM>) are eliminated.

Claim 1:
A wide band gap transistor comprising:
a semiconductor structure (<NUM>; <NUM>; <NUM>), including at least one wide band gap semiconductor layer (<NUM>, <NUM>; <NUM>, <NUM>) of gallium nitride (GaN) or silicon carbide (SiC);
an insulating gate structure (<NUM>; <NUM>; <NUM>);
a gate electrode (<NUM>; <NUM>; 100c), separated from the semiconductor structure (<NUM>; <NUM>; <NUM>) by the insulating gate structure (<NUM>; <NUM>; <NUM>);
wherein the insulating gate structure (<NUM>; <NUM>; <NUM>) contains a mixture of aluminum, hafnium and oxygen;
and wherein the insulating gate structure (<NUM>; <NUM>; <NUM>) is completely amorphous.