Patent Description:
Various devices using integrated circuits (ICs) may include sections that require different power levels, for example about <NUM> V for low volage sections and <NUM> V for higher voltage sections. For example, a health monitoring device may be configured to include a higher voltage <NUM> V battery source (i.e., two AA or AAA batteries) and a lower voltage <NUM> V battery source As result, when a lower voltage battery (<NUM> V in this example) is used, the DC-DC converter will act as boost converter and generate the higher voltage (<NUM> V in this example). Further, when a higher voltage battery (<NUM> V in this example) is used, the DC-DC converter will act as buck converter and generate the lower voltage (<NUM> V in this example).

<CIT> describes a busk controller having integrated boost control and driver. <CIT> describes an auto-selecting holding current circuit. <CIT> describes an asynchronous arbiter using multiple arbiter elements to enhance speed. <CIT> describes a near-zero quiescent current circuit for selecting a maximum supply voltage. <CIT> system and method for configuring direct current converter. <CIT> describes a method of choosing a functioning mode of an integrated circuit device and relative device.

A summary of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope of the invention. Detailed descriptions of an exemplary embodiment adequate to allow those of ordinary skill in the art to make and use the inventive concepts will follow in later sections.

In a first aspect, according to claim <NUM>, there is provided a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the first power source line; and a second AND gate with a first input and a second input connected to the inverse output of the first latch, wherein the first input is configured to receive a second power on reset signal based upon the second power source line, wherein the mode of the circuit is indicated by the outputs of the first latch and the second latch. The mode detector further including an OR gate with inputs connected to the output of the first latch and the output of the second latch configured to produce a system power on reset signal.

Some embodiments include a maximum voltage selector connected to the first power source line and the second power source line configured to produce an output voltage that is the maximum of a voltage the first power source line and a voltage the second power source line at an output, wherein the output voltage powers the mode detector.

In some embodiments, the maximum volage selector includes: a first transistor with source connected to a first power source line, a gate connected to the second power source line, a drain connected to the output of the maximum voltage selector, and a back gate of the first transistor is connected to the drain of the first transistor; a second transistor with source connected to a second power source line, a gate connected to the first power source line, a drain connected to the output of the maximum voltage selector, and a back gate of the second transistor is connected to the drain of the second transistor.

Some embodiments include a first power on reset circuit connected to the first power source line, configured to produce the first power on reset signal; and a second power on reset circuit connected to the second power source line, configured to produce the second power on reset signal.

Some embodiments include: : a first switch connected to the first power source line, wherein the first switch is controlled by the inverse output of the first latch; a first power on reset circuit connected to the first switch configured to produce the first power on reset signal; a second switch connected to the second power source line, wherein the second switch is controlled by the inverse output of the second latch; and a second power on reset circuit connected to the second switch configured to produce the second power on reset signal.

In some embodiments, the first latch is a flip-flop, and the second latch is a flip-flop.

Some embodiments of the mode detector are included in an integrated circuit further including: a circuit, wherein the circuit is configured to operate using either a first power source or a second power source.

In some embodiments, the circuit is one of a DCDC converter, a low dropout regulator, an analog to digital converter, a current source, and a bandgap reference voltage generator.

To facilitate understanding, identical reference numerals have been used to designate elements having substantially the same or similar structure and/or substantially the same or similar function.

The description and drawings illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Additionally, the term, "or," as used herein, refers to a non-exclusive or (i.e., and/or), unless otherwise indicated (e.g., "or else" or "or in the alternative").

<FIG> illustrates a DCDC converter for use on an integrated circuit (IC). The DCDC converter is set up so that either a low battery voltage Vbat_LV or a high battery voltage Vbat_HV may be applied to power the IC. The IC is further configured to automatically detect the voltage source applied by the batteries, as the user is able to use either type of battery to power the IC. This automatic detection of the available battery voltage will be accomplished in a way that reduces the drain on the battery sources.

The IC <NUM> includes a DCDC converter <NUM>, a mode detector <NUM>, a high voltage power on reset (FOR HV <NUM>), and a low voltage power on resent (FOR LV) <NUM>. The DCDC converter <NUM> includes both a boost converter and a buck converter. The boost converter may take a lower voltage and boost to a higher voltage, and the buck converter may take a higher voltage and drop it to a lower voltage. The DCDC converter has an Lx pin that is connected to an inductor and this Lx pin receives the switching signal. The VSS_DCDC pin provides a ground to the DCDC converter <NUM>. The POR HV <NUM> detects the presence of a voltage on the Vbat_HV line, and when such a voltage is detected, the mode detector <NUM> will set the DCDC converter <NUM> to buck operation mode to produce the voltage Vbat_LV on the low voltage line. The POR HV <NUM> detects the presence of a voltage on the Vbat_HV line, and when such a voltage is detected, the mode detector <NUM> will set the DCDC converter <NUM> to buck operation mode to produce the voltage Vbat_TV on the low voltage line.

Once the mode detector <NUM> detects the presence of one of the battery voltages, the mode of the mode detector <NUM> will not change if the voltages on Vbat_LV or Vbat_HV change after the mode was determined. For example, if the Vbat_LV is detected, the DCDC converter <NUM> will produce Vbat_HV which may cause the POR HV to detect that voltage and provide an input to the mode detector that Vbat_HV is present. The mode detector <NUM> is designed to avoid this as will be described below.

In order to reduce the current draw of the PORs, POR switches <NUM> and <NUM> are controlled by the mode detector <NUM>. When the mode detector <NUM> determines the presence of the Vbat_LV or Vbat_HV, the mode detector <NUM> will cause the POR switches <NUM> and <NUM> to open so that the POR HV <NUM> and POR LV <NUM> cannot now signal the presence of the battery voltage Vbat_HV or Vbat_LV which will reduce power consumption.

Also a low power bypass switch (LPBS) <NUM> may be used when the DCDC converter <NUM> is off or in some low power mode to provide a voltage on a both of the battery lines that will then result in an equal supply. In this situation the IC is in a very low power mode and consumes only a few microamps.

Further, the mode detector <NUM> will assert the determined mode information in all power modes until the battery is disconnected. Also, there should be no static current consumption and minimum leakage to maximize the lifetime of the battery. In some applications, the <NUM> V battery is a silver-oxide button cell with very low capacity and high internal resistance. In such an application, the leakage of the mode detector <NUM> should remain below <NUM> nA.

<FIG> is a block diagram of the mode detector and the power source for the mode detector. The mode detector system includes the following key features: the use of two POR blocks (one each for Vbat_LV and Vbat_HV); a latch with two RS flipflops to avoid using a clock; a power supply for the latch; and the generation of a POR signal POR_INT for the rest of the system.

A maximum voltage selector <NUM> supplies power to the mode detector <NUM> before a POR. The maximum voltage selector <NUM> receives both battery voltages Vbat_LV and Vbat_HV. The maximum voltage selector <NUM> includes two transistors <NUM> and <NUM>. The first transistor <NUM> has a source connected to Vbat_HV, a gate connected to Vbat_TV, and a drain connected to the output of the maximum voltage selector. The second transistor <NUM> has a source connected to Vbat_TV, a gate connected to Vbat_HV, and a drain connected to the output of the maximum voltage selector. Further, the back gate of each transistor is connected to the source or output of the transistor. If one supply line is at least one Vt higher than the other, the corresponding PMOS will start to conduct. The result is the higher of the two input voltages is output to power the mode detector. <FIG> shows a plot of Vbat_RV and Vbat_HV input into the maximum voltage selector over time. Vbat_RV is constant at <NUM> V over time. The Vbat_HV increases from <NUM> V to <NUM> V linearly over time, then stays at <NUM> V for a period of time, then drops back to <NUM> V linearly. <FIG> illustrates the output of the maximum voltage detector when the input voltages are as found in <FIG>. As can be seen the output of the maximum voltage selector is <NUM> V until the value of Vbat_HV approaches <NUM> V at which time the output voltage drops about <NUM> V before then recovering and increasing to <NUM> V. Accordingly, in this example, the difference between Vbat_RV and Vbat_HV should be greater than <NUM> V for the circuit to operate properly.

Once one of the PORs <NUM>, <NUM> has detected sufficient battery voltage and the mode has been detected, the supply for the mode detector <NUM> is taken over by internal switches (not shown) and connected to either Vbat_LV or Vbat_HV.

The PORs <NUM>, <NUM> are circuits where the output voltage is kept low until a certain threshold value is reached. For example, in the example herein, a threshold voltage of <NUM> V may be used for POR_LV, and a threshold voltage of <NUM> may be used for POR_HV. Accordingly, once one of the batteries are attached to produce either Vbat_HV or Vbat_LV, the associated POR will produce an output voltage that is supplied to the mode detector <NUM>.

The mode detector <NUM> includes two AND gates <NUM>, <NUM>, two flip-flops (or latches) <NUM>, <NUM>, an OR gate <NUM>, and switches <NUM>, <NUM>. The two flip-flops <NUM>, <NUM> form a latch which is reset at power up before either of the PORs <NUM>, <NUM> is released. This defines the state of the flip-flops <NUM>, <NUM> before anything in the system is active. As a result, no clock is needed in the system to reset the flip-flops which saves current. The flip-flops receive an input from AND gates <NUM>, <NUM> which is then held until the flip-flops <NUM>, <NUM> are reset. Each of the flip-flops <NUM>, <NUM> produce an output value based upon the value held by the flip-flop as well as an inverse of that output.

A first AND gate <NUM> receives as inputs the output of the POR HV <NUM> and the inverse output of the second flip-flop <NUM>. A second AND gate receives as input the output of the POR LV <NUM> and the inverse output of the first flip-flop <NUM>. This means that the output of the AND gates <NUM>, <NUM> will only be <NUM> when its respective POR is triggered and the opposite flip-flop is holding a <NUM> value, i.e., the opposite flip-flop is outputting a <NUM> at its inverse output. As a result, only one of the flip-flops <NUM>, <NUM> can hold a value of <NUM> at any given time. For example, if the POR HV detects a Vbat_HV voltage and asserts an output of <NUM>. As the flip-flop <NUM> was reset to holding a <NUM> at startup, it asserts a <NUM> at the inverse output. Accordingly, the AND gate <NUM> outputs a <NUM>, which is held in the flip-flop <NUM>. So the output of flip-flop <NUM> is now <NUM> and the inverse output is <NUM>. As the inverse output of flip-flop <NUM> is input into the second AND gate <NUM>, no matter what the POR LV outputs to the second AND gate <NUM>, the output of the second AND gate <NUM> will always be <NUM> until the flip-flop <NUM> is reset. So even if Vbat_LV is asserted and the POR LV <NUM> detects this and outputs a <NUM>, the second flip-flop will still hold a <NUM>. This arrangement means that whichever battery voltage is first available, the mode detector <NUM> will detect that voltage and cause the detected battery voltage to be asserted at an output Vbat_int until the system is reset.

A first output switch <NUM> is controlled by the output of the first flip-flop <NUM>, and first output switch <NUM> is closed when the output of the first flip-flop <NUM> is <NUM>. When the first output switch <NUM> is closed, it connects Vbat_LV to the output Vbat_int. Also, a second output switch <NUM> is controlled by the output of the second flip-flop <NUM>, and second output switch <NUM> is closed when the output of the second flip-flop <NUM> is <NUM>. When the second output switch <NUM> is closed, it connects Vbat_HV to the output Vbat_int. Further, the outputs of the first flip-flop <NUM> and the second flip-flop <NUM> are ORed by OR gate <NUM> to produce a POR_INT signal, which is a system power on reset signal provided to other parts of the system on the IC. Accordingly, when either POR HV <NUM> or POR LV <NUM> detects a battery voltage, the system POR_INT signal is generated.

The mode detector also may provide the outputs of the two flip-flops <NUM>, <NUM> to the DCDC converter <NUM> to indicate the mode indication. For example, the output of the first flip-flop <NUM> may indicate a buck mode, and the output of the second flip-flop <NUM> may indicate the boost mode. In another embodiment, the outputs of the two flip-flops <NUM>, <NUM> may be combined to provide a <NUM> bit indication of which mode the should be used.

As the mode detector operates without clock, current consumption is reduced. The flipflops act as a memory element to preserve at least <NUM> states: undefined; boost mode; and buck mode. This requires <NUM> bits to define at least <NUM> states. The two flip-flops store the information. Both flipflops are reset at power up, before either of the PORs can be active, so the output is then "<NUM>" at power up.

The PORs provide a signal to the mode detector when a battery is connected. The current consumption of the PORs is a few µA, which is not a problem for regular AA batteries or rechargeable batteries. But for a small silver-oxide battery, it results a significant reduction of useful life of the battery. These batteries may only be designed for <NUM>µA. In order to remove the drain on the batteries cause by the PORs, each POR is switched off after one of the PORs detects a battery voltage. This is accomplished using POR switches <NUM>, <NUM>. A first POR switch <NUM> is connected between Vbat_HV and the POR HV <NUM> and is controlled by the inverted output of the first flip-flop <NUM>. At start up, this POR switch <NUM> will be closed because the first flip-flop <NUM> holds a <NUM>, so the inverted output is <NUM>. Likewise, a second POR switch <NUM> is connected between Vbat_LV and the POR LV <NUM> and is controlled by the inverted output of the second flip-flop <NUM>. At start up this POR switch <NUM> will be closed because the second flip-flop <NUM> holds a <NUM>, so the inverted output is <NUM>. Accordingly, once one of the PORs detects the presence of a battery, that POR will be disconnected from that battery once the mode detector detects <NUM> the mode. As a result, that battery will not have the POR drawing current from it after detection.

While <FIG> illustrates the mode detector <NUM> as including the AND gates <NUM>, <NUM>, flipflops <NUM>, <NUM>, output switches <NUM>, <NUM>, and OR gate <NUM>, the mode detector <NUM> may also include the maximum voltage selector <NUM>, the POR HV <NUM>, POR LV <NUM>, and/or POR switches <NUM>, <NUM> in any combination.

While the mode converter is described as being used with a DCDC converter, it may be used with other types of circuits that may receive and operate off of two different level power sources such as different types of batteries. The mode converted described herein may also be used with for example, an analog to digital converter (ADC), current source, a low dropout regulator (LDO), or a bandgap reference voltage generator. The ADC, may for example, measure the battery voltage, no matter to which terminal the battery is connected and the mode detector will identify when a batter has been connected. In another example, a bias current generator may need to be always connected to the battery, so the mode detector may indicate which battery line has a batter attached and the bias current generator connects to that line. In another example, an IC may have a number of blocks depending on the mode detector state including a low power LDO and a bandgap reference voltage generator. The IC may have two supply switches that are controlled by the mode detector: one connects to Vbat_HV if a battery is detected on Vbat_HV. The other switch does the same for Vbat_TV. The result is that these blocks are always connected to a battery, so that a battery may be connected to either Vbat_LV or Vbat_HV.

Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the first power source line; and a second AND gate with a first input and a second input connected to the inverse output of the first latch, wherein the first input is configured to receive a second power on reset signal based upon the second power source line, wherein the mode of the circuit is indicated by the outputs of the first latch and the second latch.

Claim 1:
A mode detector (<NUM>) configured to be attached to a power source and to determine a mode of a circuit based upon the attached power source, comprising:
a first latch (<NUM>) configured to hold a first input value and output the first held value and an inverse of the first held value;
a second latch (<NUM>) configured to hold a second input value and output the second held value and an inverse of the second held value;
a first output switch (<NUM>) connected between a first power source line (Vbat_hv) and a power source output (Vbat_int) of the mode detector, wherein the first output switch (<NUM>) is configured to be controlled by the output of the first latch (<NUM>);
a second output switch (<NUM>) connected between a second power source line (vbat_lv) and the power source output (Vbat_int) of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch;
a first AND gate (<NUM>) with a first input and a second input which is connected to the inverse output of the second latch (<NUM>) , wherein the first input is configured to receive a first power on reset signal based upon the first power source line; and
a second AND gate (<NUM>) with a first input and a second input which is connected to the inverse output of the first latch (<NUM>), wherein the second input is configured to receive a second power on reset signal based upon the second power source line (Vbat_lv),
wherein the mode of the circuit is indicated by the outputs of the first latch (<NUM>) and the second latch (<NUM>) ; and wherein the mode detector further comprises an OR gate (<NUM>) with inputs connected to the output of the first latch and the output of the second latch configured to produce a system power on reset signal (POR_INT).