Patent Description:
The present writing is directed to the field of semiconductors, and in particular, to transistors comprising diamond. The technology presented herein, is applicable to devices and systems that utilize gate structures to control the source-to-channel barrier in diamond electronics and otherwise.

The following references are of interest to understand this presentation.

Diamond-based electronics have been attractive for decades due to the intrinsic characteristics of diamond materials. With a breakdown field of at least <NUM> MV/cm, an electron and hole mobility greater than <NUM><NUM>/V/s, and a thermal conductivity greater than 20W/cm/K, diamond transistors will continue to significantly improve the power performance of solid state radio frequency (RF) electronics, benefiting electronic systems such as, for example, phased- array radar systems, electric automobiles, and the electric power grid. Simplified thermal management and size, weight, and power (SWAP) improvements enabled by diamond technology can potentially facilitate the application of diamond electronics to high-power, solid-state, RF systems and mobile platforms such as satellites/drones.

Despite its notable properties, in terms of its development in the electronics industry, diamond has not been able to compete with other wide-band gap materials in the past due to several limitations. One limitation includes material availability, as the average size of diamond samples is typically small. However, advancements in microwave plasma chemical vapor deposition (CVD) growth technology have resulted in the availability of larger diamond samples. A second limitation includes the lack of suitable dopants for diamond, though P-type dopants such as boron are readily available. However, since boron has a relatively high activation energy of <NUM> eV, boron is particularly unsuitable for certain applications. N-type doping in diamond has been researched for decades without many significant improvements. Without overcoming these challenges, diamond electronics may never become a mainstream technology.

In consideration of these limitations and leveraging the notable properties of diamond, the technology herein presented comprises in one embodiment, a lateral, fin-based, static induction transistor (SIT) comprising diamond. SITs were introduced decades ago and they are currently used in silicon carbide (SiC) technologies. Almost all of these technologies use vertical structures with large device areas. Unfortunately, the parasitic capacitance between the gate and drain, limits the device operation in high frequency regimes. Using a lateral SIT, such as a lateral punch-through transistor, can simplify the engineering of parasitic components for highfrequency operations. However, ensuring that the device channel is properly isolated from the substrate is a big challenge when the channel comprises wide-band gap materials. Most lateral SITs have been engineered using silicon technology, where good device channel isolations are possible through a P-N junction or through silicon-on-insulator (SOI) technology. The lack of channel isolations at high voltages in lateral devices was of consideration in developing the present technology, and it is thought that by introducing a fin-based channel with an additional buffer layer to isolate the device from a semi conductive substrate, that problem may be resolved or lessened to a notable extent.

<CIT> discloses a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.

<CIT> discloses a junctionless accumulation-mode (JAM) semiconductive device isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

The technology now presented is comprised of transistors using multi-gate structures operating in the space charge limited regime. The use of a multi-gate structure increases a current leakage path distance, thereby increasing the breakdown voltage of a transistor without sacrificing its current conduction capability.

The term "fin" as here used defines a channel with a thin cross-sectional area relative to a corresponding cross-sectional area of a source and/or drain of the transistor. The fin can extend along a current path distance between the source and drain of the transistor. The thin cross-sectional area of the fin can remain generally constant along the current path distance, or it can vary within a range of thin cross-sectional areas along the current path distance. The fin can be a nanowire fin.

In this writing, a P-type semiconductor is a semiconductor having holes as the majority charge carriers. A P-type semiconductor can be an extrinsic or intrinsic semiconductor, and if extrinsic, the P-type semiconductor is doped with a P-type dopant. A P-type dopant is a dopant that, when added to a semiconductor, increases the positive charge carrier (e.g. hole) concentrations therein.

In this writing, an N-type semiconductor is a semiconductor having electrons as the majority charge carriers. An N-type semiconductor can be an extrinsic or intrinsic semiconductor, and if extrinsic, the N-type semiconductor is doped with an N-type dopant. An N-type dopant is a dopant that, when added to a semiconductor, increases the negative charge carrier (e.g. electron) concentrations therein.

In this writing, a multigate device, multiple gate device, or multiple gate field-effect transistor can be a Fin Field-effect transistor (FinFet) that incorporates more than one gate into a single device. The multiple gates can be controlled by a single, integral gate structure, wherein the multiple gate surfaces act electrically as a single gate, or by independent, distinct gate structures. (This information is to be considered noting that a planar double-gate transistor is one in which the drain, source and channel are sandwiched between two independently fabricated gate/gate-oxide stacks. A FlexFet is a planar, independently double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET (junction gate field-effect transistor) bottom gate that are self-aligned in a gate trench, both as described in reference [<NUM>] above.

In this writing, the description "intrinsic" refers to a semiconductor that is not doped. For example, "intrinsic diamond" refers to undoped diamond.

In this writing, a "pinch off" voltage refers to a gate bias voltage threshold at which the transistor turns off. A current "pinch off" refers to the act of a current shutting off at the "pinch off" voltage.

In this writing a "short-gated channel" refers to a short channel length such as between a source and a drain. The gate to drain separation can be adjusted for different materials and the use and non use of buffer layers.

In this writing, a "breakdown voltage" can refer to the voltage difference between the drain and the source at which the device begins to leak current through the drain or source when the gate voltage is such that the channel is "off'.

In this writing a good ohmic contact is an ohmic contact with a low ohmic contact resistance. A low ohmic contact resistance is an ohmic contact resistance that is less than <NUM>Ω*mm.

In an aspect, increasing drift region conduction is of interest. Increasing drift region conduction can comprise: reducing the drift region length of the semi conductive channel (i.e. the gate-to-drain separation distance) and increasing a thickness of the drift region channel. The dimensions of the drift region (i.e. length, width, and/or thickness) can determine the breakdown voltage of the device.

In a further aspect, reducing the substrate punch-through effect is of interest. Reducing the substrate punch-through effect can comprise: incorporating a semi conductive buffer layer between the source/drain regions and a substrate on which the transistor is placed and increasing the size and/or thickness of the buffer layer.

In a further aspect, the large parasitic capacitance inherent in vertical SITs is of interest and addressed to be reduced or overcome. By incorporating a lateral structure, the gate-to-source and gate-to-drain parasitic capacitance can be engineered with greater freedom, thereby enabling a higher frequency of operation and a higher power performance. In existing lateral SITs, there is a lack of efficient methods to turn the conductive channel "off" at high voltages, leading to a lower breakdown voltage and lower powers of operation. Using a multiple gate structure, the conduction channel can be regulated by wrapping a gate around the sides of the channel. This multiple gate design enables a material agnostic SIT, which is ideal for use in material systems comprising diamond, since diamond systems often lack good hetero junctions and homo junc. tions to control leakages therein.

In a further aspect, leveraging a multiple gate structure configured to decouple the current paths for conduction and leakage is of interest. This effectively increases the device breakdown voltage without reducing the channel conduction, resulting in a higher power performance. The incorporation of a fin structure introduces a larger cross section area for space-charge limited transport in the drift region thereby reducing the drift region resistance. This arrangement can enable a high conduction channel.

To better understand the technology and methodology herein presented, reference is made to the following description taken in conjunction with the accompanying drawings in which like reference numerals represent like parts. The drawings are not drawn to scale.

The present technology involves a lateral, multiple-gate, transistor operating within a space charge limited system. The technology uses a multiple gate structure to control the source-to-channel barrier in order to control the injection of charge carriers into the channel for current transport in the space charge limited system. The use of a multiple-gate structure seems to increase the leakage path thereby increasing the breakdown voltage without sacrificing the current conduction capability of the transistor. As will be seen, the present technology may be used with single gate structures as well.

Turning to <FIG>, prior art background information is provided. As described in references [<NUM>] and [<NUM>] above, the term FinFET refers generally to a non-planar, double-gate transistor built on a substrate of the type seen in <FIG> with the fin extending between the source and the drain. The term 'FinFET' can refer to multiple-gate as well as single gate structures. The FinFET is a variation on traditional MOSFETs (metal-oxide field effect transistor) distinguished by the presence of a thin silicon 'fin' inversion channel on top of a substrate, allowing the gate to make (at least) two points of contact: the left and right sides of the fin. The length of the fin (measured in the direction from the source to the drain) determines the effective channel length of the device. A wrap-around gate structure provides better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects.

The use of multigate transistors is one strategy being developed to create ever smaller microprocessors and memory cells and is referred to often as extending Moore's law. Silicon digital circuits have continually advanced the computing front by following Moore's Law in reducing energy consumption and increasing computing power by relentlessly scaling the transistor.

The thinking underlying the present technology is that a different approach is needed at least for RF and power electronics to increase power performance as higher breakdown fields are needed to increase power density. Ohmic gate dielectric engineering is tested in the technology now presented.

Device concepts such as FinFETs, junctionless FETs, and unipolar nanowire FETs developed in the silicon industry to create a fin or nanowire-type structure with the gate wrapping around the channel provide much better channel control especially for short-channel devices required for RF operation. Fin-like geometry was recently reported in H (hydrogen)-terminated diamond FET but the demonstrated device requires H-termination and does not use fins as active device channels. Instead the fin-based geometry was used purely to increase the conductive surface area and thereby increase device current. In the present technology, active fin channels made in diamond are fully utilized without H-termination, enabling the leveraging of thicker diamond films with much better quality and the maintenance of channel control for unipolar transport at the sub-micron scale. Fin geometry offers an additional degree of freedom to increase the current density by reducing the fin channel pitch and increasing the fin height enabling a high, power-density device for RF and power electronics. The device discussed now operates with hole accumulation metal-oxide semiconductor (MOS) structures built on fins to maintain effective control of the channel conduction.

Succinctly stated, the technology now presented offers fin geometry with space charge limited current transport. For at least diamond, this seems to be a very advantageous combination.

Turning to <FIG>, a perspective view of an embodiment of a lateral fin SIT is shown. <FIG> presents the source <NUM>, the drain <NUM>, the channel (including fin and drift region)<NUM>, the gate structure <NUM>, the dielectric layer <NUM>, the buffer layer <NUM>, and the substrate <NUM> of the lateral fin SIT. Axes x, y, and z are labeled for the reader's reference. Given these axes, the term "length" refers to a distance measured along the x-axis exemplified in <FIG>. Similarly, the terms "width" and "thickness" refer to distances measured along the y-axis and the z-axis, respectively.

Channel <NUM> and buffer layer <NUM> can comprise lightly doped regions of P-type diamond to enable control of the channel conductivity. Source <NUM> and drain <NUM> can comprise heavily doped regions of P-type diamond to reduce the ohmic contact resistance introduced by ohmic contacts (not shown) coupled to source <NUM> and drain <NUM>. (Contact resistance is a measure of the ease with which current can flow across a metal-semiconductor interface. ) This ohmic contact resistance can be reduced to less than <NUM>Ω mm with sufficiently high P-type dopant concentrations in the source <NUM> and drain <NUM> regions. Source <NUM> and drain <NUM> can comprise heavily doped regions of P-type diamond to enable a high power and a high frequency operation.

Heavily doped P-type diamond can comprise diamond doped with a P-type dopant (e.g. boron) concentration greater than or equal to <NUM><NUM> cm-<NUM> Lightly doped P-type diamond can comprise diamond doped with a P-type dopant (e.g. boron) concentration ranging between <NUM><NUM> cm-<NUM> and <NUM><NUM> cm-<NUM> The unit of "cm-<NUM>" refers to a number of atoms (of e.g. boron) per cubic centimeter.

As seen in <FIG>, source <NUM>, drain <NUM>, channel <NUM>, buffer layer <NUM>, dielectric layer <NUM>, and gate structure <NUM> are disposed atop substrate <NUM>. Substrate <NUM> preferably comprises N-type diamond and/or intrinsic diamond to reduce substrate current leakage therethrough. N-type diamond can comprise diamond doped with an N-type dopant (e.g. phosphorus, nitrogen). Substrate <NUM> can be doped at any suitable N-type dopant concentration.

Next, <FIG> presents a cross sectional view of the transistor along line 1C-1C of <FIG>, with source <NUM>, drain <NUM>, channel <NUM>, dielectric layer <NUM>, and gate structure <NUM> disposed atop substrate <NUM>. <FIG> does not label channel <NUM> though it should be understood that channel <NUM> comprises gated channel <NUM> and drift region <NUM> which are shown in <FIG>. Typical Finfets do not have drift regions. Drift regions are useful for wide-band gap materials and silicon. The width of the drift region is independent of the channel width.

Turning now to <FIG>, the device geometry and relevant dimensions are identified by suitable legends. <FIG> is a variation of the cross section shown in <FIG>. Dielectric layer <NUM> is shown to cover a larger surface area of source <NUM> than what is shown in <FIG>, though the amount of dielectric layer <NUM> covering source <NUM> is not critical. Gated channel <NUM> is a fin-like structure formed of the lightly doped P-type diamond region discussed above. (Gate structure <NUM> can be either a multiple gate structure or a single gate structure formed on at least one, two, or three faces of gated channel <NUM> (the top and two opposing sides of gated channel <NUM>. The gate structure should be formed on the gated channel in whatever manner is needed to facilitate pinching off the current in that channel if desired. ) The source <NUM>, and drain <NUM> regions are preferably comprised of heavily doped P type diamond (shown as P+ in <FIG>) to reduce the ohmic contact resistance. The gated channel <NUM> is separated from the drain <NUM> by a gap distance Lgd.

The length Lg of gated channel <NUM> is defined as the channel length underneath the gate structure <NUM>. Heavily doped source <NUM> and drain <NUM> regions are separated from the substrate <NUM> by buffer layer <NUM>. This buffer layer <NUM> provides additional voltage blockage when the device is "off' and therefore increases the breakdown voltage of the device. For certain applications not requiring a high breakdown voltage, the buffer layer <NUM> may be omitted. The buffer layer <NUM> may vary in thickness, being thicker under the drain <NUM> than the source <NUM>, as just one example. There is an interrelationship between the buffer layer <NUM> and the channel length. Generally, for greater performance (greater speed), a short channel length is desired. But as the channel length gets shorter and shorter, the electric field between the drain and the source increases. If the channel is extremely short, there will be current leakage. The buffer layer is then needed to prevent this current leakage. If the channel length were greater, performance (speed) would be reduced but also reduced would be leakage and the need for a buffer layer or a buffer layer of notable thickness. Hence, the buffer layer enables the tuning of the device without changing the channel length. A high speed device is anything at or above the gigahertz range.

A conventional semiconductor device requires reasonable dopant densities to operate at its ohmic conductive regions. However, the most common P-type dopant in diamond is boron which has a relatively high activation energy of <NUM>. 36eV, resulting in high resistance / low conduction even at reasonably high doping levels. To increase conduction, a much higher dopant density is necessary though this can reduce the charge carrier mobility and reduce the breakdown voltage of the device.

To achieve a higher power transistor device with both <NUM>) a high device "on" current and <NUM>) a high device "off" breakdown voltage, the design and operation of the device can be adjusted. Instead of relying on its ohmic transport behavior at low electric fields, space charge limited transport can be used and perhaps exploited. When the device gate <NUM> is biased with a sufficiently high electric field, its conduction is determined by the source of the charge carriers, making the transistor carrier injection limited. If a sufficient amount of charge carriers are able to overcome the source <NUM>/channel <NUM> barrier, the conduction of channel <NUM> is eventually limited by the space charge flowing through the drift region <NUM>. In this circumstance, the transistor is described by the space charge limited current (SCLC) regime model. The transistor device, here disclosed, can operate in the space charge limited regime in at least one embodiment.

As appreciated, <FIG> defines the lengths and voltage differences across the transistor. This figure becomes important when interpreting the formulas that follow. From this figure, the reader can see the gate dielectric <NUM> and drift region <NUM>, Lg and Lgd, which are respectively the gated channel <NUM> length and the gate-to-drain separation distance (i.e. the length of the drift region <NUM>). Also presented are voltage differences Vdi and Vds. The voltage difference Vdi is measured across gated channel <NUM>. The voltage difference Vds is measured across gated channel <NUM> and drift region <NUM>. Gated channel <NUM> length Lg is measured along an axis running from the source <NUM> to the drain region <NUM> of the transistor.

Looking now at <FIG>, these figures also illustrate a variation of the cross sectional view shown in <FIG>, and are marked with legends showing the device is "on" (<FIG>) and the device is "off" (<FIG> illustrates the concentration of holes <NUM> and the direction of current (by the arrow pointing toward the drain <NUM>) when the device is "on", and <FIG> illustrates the depletion region <NUM> and the current leakage through the substrate shown by the arrowed line <NUM> going from the source <NUM> toward the area under the drain <NUM> when the device is "off'. That leakage can be stemmed as indicated by the X in <FIG> across the arrow <NUM>, through the use of buffer layer <NUM>. While in these figures gate structure <NUM> overlaps the source <NUM>, such overlap is not required. This is especially so for high frequency RF devices. In these devices, an overlap should be eliminated and replaced with a small gap as depicted in <FIG>, later discussed.

When the transistor is under a negative gate bias voltage relative to a grounded source <NUM>, the gated channel <NUM> is populated with positive charge carriers or holes. With a negative gate bias voltage relative to a grounded source <NUM>, the diamond valence band of gated channel <NUM> is lifted so that the holes form an accumulation layer originating from the source <NUM>, extending through the fin channel <NUM> best seen in <FIG> which are described in the following paragraphs.

For devices with short-gated channels <NUM>, the device current density is essentially determined by the hole concentration and the hole saturation velocity. The total channel current can be determined by modeling two sections of the transistor, the gated channel <NUM> and the drift region <NUM>, as being coupled in series. The gated channel region <NUM> can be modeled as a normal accumulated MOSFET, as shown below: <MAT>.

The drift region <NUM> can be modeled as space charge limited transport: <MAT>.

Some variables in equations Eqn. (<NUM>) and Eqn. (<NUM>) were earlier presented, however, for clarity now, in equations Eqn. (<NUM>) and Eqn. (<NUM>), Vdi is the voltage difference across the gated channel <NUM>. Vds is the voltage difference across gated channel <NUM> and the drift region <NUM>, respectively; tdrift is the drift region <NUM> thickness, Lg and Lgd are the gated channel <NUM> length and the gate-to-drain separation distance (i.e. the length of the drift region <NUM>), respectively; εs is the dielectric permittivity of the channel (e.g. of diamond); νs is the saturation velocity of the charge carriers (e.g. holes) in for example, diamond; µh is the effective channel mobility under the gate structure <NUM>, and Vt is a threshold voltage of the device. The drift region transport is modeled in bulk. Hence, bulk mobility can be used for µh, though bulk mobility is typically higher than the effective channel mobility. As long as the drift region <NUM> can support enough conduction, the series resistance introduced by the drift region <NUM> is much smaller than the resistance introduced by the gated channel region <NUM>. The device conduction is therefore, determined by the conduction of the gated channel region <NUM> under the model detailed by Eqn.

If the gate structure <NUM> voltage is positively biased, a channel depletion region is induced. At increased gate voltages, the channel depletion region can be widened such that gated channel <NUM> is pinched off. Under this circumstance, the transistor device is "off" and its breakdown voltage can be mainly determined by the gate-to-drain separation distance Lgd, which can also be the length of the drift region <NUM>. The breakdown field in diamond is expected to be <NUM>0MV/cm. Hence, with Lgd on the order of <NUM>, it is possible for the transistor to support a breakdown voltage of <NUM>00V. This high breakdown field allows for the use of a much shorter Lgd, which is critical to support a sufficient conduction through the drift region <NUM> of the transistor. The width of the depletion region is determined by the composition of the gate structure <NUM> (e.g. type of metal and/or conductive material), the gate dielectric layer <NUM>, and the boron doping concentration of channel <NUM> through the following equation: <MAT> where Vg is the gate <NUM> bias voltage, Vfb is the flat-band voltage determined by the composition of the gate <NUM> (metal) and diamond work function, q is the single electron charge, Na is the acceptor concentration in channel <NUM>, εs is the dielectric constant of diamond, Cox is the oxide capacitance, and Wdep is the width of the depletion region. The second term on the right hand side of Eqn. (<NUM>) represents the potential drop across the depletion region and the third term on the right hand side of Eqn. (<NUM>) represents the potential drop across the gate dielectric layer. Typically, increasing the dopant concentration of channel <NUM> increases the gate <NUM> bias voltage required to generate the same depletion region width. To pinch off the gated channel <NUM> at a zero gate bias voltage, the depletion region width needs to be larger than half the width of the semi conductive fin channel <NUM>. With an aluminum gate structure <NUM> and a boron dopant concentration of <NUM>×<NUM><NUM>cm-<NUM> in diamond, the flat-band voltage, Vfb, is calculated to be -<NUM>. 4V using <NUM>. 3eV and <NUM>. 08eV electron affinity for diamond and aluminum, respectively. Using a <NUM> layer of silicon dioxide (SiO<NUM>) as the gate dielectric <NUM>, the depletion region width is calculated to be about <NUM> at a zero gate bias voltage. Hence, the device may be designed with <NUM>-wide fins to ensure a current pinch-off at a zero gate bias voltage in at least one embodiment, though the width of fin channel <NUM> can be less than <NUM> in other embodiments.

Turning now to <FIG> and as a brief review of the structure of these figures, <FIG> is a schematic drawing of a diamond FinFET showing the source <NUM>, drain <NUM>, gated channel <NUM>, and fin channel <NUM>. Gate <NUM> and dielectric layer <NUM> are omitted from this view to focus on the fin channel <NUM>. Heavily doped P-type diamond (P+) is used in the source <NUM> and drain <NUM>, while lightly doped P-type diamond is used in the fin channel <NUM>. Gated channel <NUM> can be defined as the portion of channel <NUM> underneath gate structure <NUM>. In the case that the gate overlaps with source <NUM> and drain <NUM>, channel <NUM> is gated channel <NUM>. In the case that gated channel <NUM> is a purely fin-like structure, gated channel <NUM> is fin channel <NUM>. However, gated channel <NUM> should at least comprise fin channel <NUM> so that the portion of channel <NUM> underneath the gate comprises fin <NUM>. As such, lead lines originating from gated channel <NUM> and fin <NUM> in <FIG> are labeled as "<NUM>, <NUM>", indicating that gated channel <NUM> is fin channel <NUM>. A fin-like structure or channel can include a nanowire structure. For example, gated channel <NUM>/fin channel <NUM> can have a rounded and/or circular cross section wherein gated channel <NUM>/fin channel <NUM> has a diameter smaller than <NUM>. Gate structure <NUM> sufficiently wraps around the nanowire structure of gated channel <NUM>/fin channel <NUM> to ensure a current pinch off at positive gate voltages.

<FIG> is a cross sectional view of the fin channel <NUM> of the device which is in this figure, shown with the gate dielectric <NUM> and the gate <NUM> wrapping around the fin channel <NUM> on its top and two opposing sides. In a preferred embodiment, the aspect ratio of fin <NUM> is at least <NUM>:<NUM> (height: width).

In <FIG>, the hole concentration is shown when the device is turned "on" by a negative gate bias. <FIG> is a cross sectional view of <FIG> along the cross sectional line 2D-2D shown in <FIG>.

In <FIG>, the hole concentration of the device is again is shown with <FIG> being a perspective view as <FIG> is and <FIG> being a cross sectional view of <FIG> along lines 2F-2F.

In <FIG>, the device is off with zero gate bias, indicating a completely pinched-off channel.

Going into more detail with respect to <FIG>, a diamond FinFET is shown. In <FIG> two heavily boron-doped diamond layers (P+) as source <NUM> and drain <NUM> sitting atop a lightly boron doped diamond layer (P-) as buffer layer <NUM> are seen. A narrow fin structure <NUM> is created between the source <NUM> and drain <NUM> regions as a conduction channel. The gate <NUM> and gate dielectric <NUM> are not shown in this figure as earlier mentioned. The device is built upon a semi-insulating diamond substrate <NUM>, which is used to reduce current leakage. With negative gate bias, the diamond valence band is lifted relative to the grounded source so that the holes form an accumulation layer originating from the source <NUM>, extending through the fin channel <NUM>, to drain <NUM>. Consequently, the device is turned "on". The device current density is essentially determined by the hole concentration and the hole saturation velocity for short-channel devices. Positive gate bias, on the other hand, will induce depletion regions in the channel. Returning to Eqn. (<NUM>) above, the depletion region's width is determined by the gate metal, the gate dielectric, and the boron doping concentration of the channel through equation Eqn.

A three-dimensional technology computer-aided design (TCAD) simulation using the software suite Sentaurus™ was executed for a representative device as shown in <FIG>, with <NUM><NUM> cm-<NUM> and <NUM>×<NUM><NUM> cm-<NUM> boron dopant concentrations in P+(heavily doped P-type) and P-(lightly doped P-type) regions, respectively.

In <FIG>, the device channel <NUM> width was set to be <NUM> with the gate <NUM> structure being composed of aluminum (Al) and the gate dielectric <NUM> comprising <NUM> silicon dioxide (SiO<NUM>). <FIG> illustrates the simulated hole concentration in three dimensions, with the source <NUM>, drain <NUM>, and gate <NUM> biased at the voltages 0V, -16V, and -10V, respectively. As earlier noted, <FIG> and <FIG> are cross sectional views taken along lines 2D-2D of <FIG> and <FIG> of <FIG>, respectively. Under a negative gate bias voltage, the fin channel <NUM> is populated with holes as shown in <FIG>; hence the device is turned "on", as can be seen by the lightly shaded regions of fin channel <NUM>. A gradient of increasing hole concentrations extends from substrate <NUM> and upward through each of the buffer layers <NUM> underneath the drain <NUM> and source <NUM>, with fin channel <NUM> and source/drain region <NUM> and <NUM> having the highest concentration of holes (><NUM>×<NUM><NUM>cm-<NUM>) and regions of buffer layer <NUM> adjacent substrate <NUM> having a low concentration of holes (< <NUM> ×<NUM><NUM>cm-<NUM>). Substrate <NUM>, being either N-type diamond or intrinsic diamond, has a hole concentration of zero. The amount of charge accumulated is determined by the gate bias voltage and the gate-to-channel capacitance. Similarly, <FIG> and <FIG> illustrate the distribution of holes under a 0V gate bias voltage and a -16V drain bias voltage. The fin channel <NUM> is completely depleted as expected, from a calculation using a simple one-dimensional electrostatic model, as can be seen by the dark shaded regions of fin channel <NUM>, wherein fin channel <NUM> and substrate <NUM> have a low hole concentration of about < <NUM> ×<NUM><NUM> cm-<NUM>. It is noted that there is a depletion region extending into the drain region <NUM>. This is because the negative drain bias voltage relative to the zero gate bias voltage pulls holes away from the drain/channel region even though the drain is doped at a high concentration of <NUM><NUM> cm-<NUM>, the drain region still being non-degenerated.

As can be appreciated from the foregoing, one feature of the present technology is that the transistor incorporates a fin structure configured to enable the device to operate with both a high breakdown voltage and a high "on" current. In order to support a high "on" current, the drift region <NUM> needs to be sufficiently conductive. To increase the drift region <NUM> conduction, one technique comprises reducing the drift region length, Lgd. In equation Eqn. (<NUM>) above, the drift region <NUM> current is inversely proportional to Lgd<NUM>, the square of the distance between the gate <NUM> and the drain <NUM>. However, the minimum gate-to-drain distance, Lgd, is limited by the desired device breakdown voltage as reducing Lgd also reduces the device's breakdown voltage.

Another method to increase the drift region conduction comprises increasing a thickness of the drift region to include more bulk space, at the expense of limiting the gate-to-channel control. For example, in a traditional top gate only device (i.e. a device having a top gate such as a planar MOSFET), the conduction channel will be incapable of being pinched off when the drift region thickness is sufficiently large. The drift region thickness is measured along an axis perpendicular to the substrate, and running from the bottom of the drain <NUM> to an uppermost surface of the drift region. Incorporating a fin structure facilitates the wrapping of the gate structure <NUM> around the channel, wherein, in addition to the top gate, the side gates (those gates which cover the side faces of the fin/channel) can pinch off the gated channel <NUM> when the width of the channel <NUM> and fin <NUM> is sufficiently small, thin, or fin-like. This essentially decouples (or reduces the coupling of) the drift region <NUM> thickness from the gate-to-channel control, offering the freedom to increase the drift region <NUM> conduction by increasing the thickness of the drift region <NUM> without sacrificing the gate-to-channel control.

A similar description can be made for the drift region width. That is, the method of increasing the drift region conduction can comprise increasing the drift region width. Incorporating a fin structure still has the benefit of decoupling (or reducing the coupling of) the drift region <NUM> width from the gate-to-channel control since gate structure <NUM> can pinch off gated channel <NUM> when the width of channel <NUM> and fin <NUM> is sufficiently small, thin, or fin-like. In a preferred embodiment, the width of drift region <NUM> is larger than the width of the channel <NUM> and/or fin <NUM>.

A second feature of the transistor having a fin structure with a buffer layer <NUM>, as shown, includes the capability of blocking or reducing substrate punch-through effects. If the device length is sufficiently short, the source <NUM> and drain <NUM> regions can leak current through the substrate when the device is "off," as shown with the white arrow <NUM> in <FIG>. The "X" positioned over the white arrow <NUM>, as noted above, indicates that the current leaked through the substrate is blocked or reduced upon the incorporation of buffer layer <NUM>. The P-N junction formed between source/drain (<NUM>,<NUM>) and substrate <NUM> can still be punched through under a high voltage operation of the drain <NUM>. To mitigate these effects and as earlier noted, a buffer layer <NUM> can be incorporated into the transistor device to separate each of the source <NUM> and drain <NUM> regions from the substrate <NUM>. This optional buffer layer <NUM> essentially increases the leakage path between the source/drain (<NUM>, <NUM>) and through the substrate <NUM>. Hence, increasing a thickness of the buffer layer <NUM> increases the leakage path between the source <NUM> / drain <NUM> and the substrate, thereby increasing the significance, or weight, of the gate-to-drain separation, Lgd, in determining the breakdown voltage of the device. The gate-to-drain separation, Lgd, can therefore determine the device breakdown voltage when the buffer layer <NUM> is sufficiently thick.

If the gated channel <NUM> length is sufficiently long, and/or the dopant concentration in the drift region <NUM> is sufficiently high, the drain voltage has a minor or negligible effect on the source/channel barrier and the device conduction can be modeled as two resistors in series, wherein the gated channel <NUM> is coupled in series to the drift region <NUM>. Based on this model, the transistor device drain current, IDS, is simulated as shown in <FIG> for a device having a gated channel <NUM> length of <NUM> and a drift region <NUM> length of <NUM>. Here, VDS is the voltage difference between drain and source, and Vg is the voltage difference between the gate and source. The height of the fin in gated channel <NUM> is <NUM>. The total current is adjusted by an area filling factor of four to reflect the current density in a fin array. The short channel effect in the gated channel <NUM> region is also considered in the simulated model. A positively sloped load line is illustrated in <FIG> to indicate the potential device operation with maximum current and breakdown voltage. The simulation in <FIG> considers the simple one-dimensional model, though a more detailed two-dimensional simulation using Technology Computer Aided Design (TCAD) software can be implemented. For a short channel device wherein the total device length is sufficiently short, the effect of the drain <NUM> bias voltage on the source/channel barrier height can be significant.

In practice, the device behavior can deviate from the simulation shown in <FIG> and can be closer to the behavior of a SIT device, the three-dimensional simulation of which is shown in <FIG> illustrates a graphical representation of a three dimensional simulation of an operation of the device, with drain currents plotted against drain bias voltages, for gate voltages ranging from -10V to +6V with incremental steps of 2V. Gate and drain voltages are measured with respect to a grounded source. Curves <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> correspond to gate bias voltages +6V, +4V, +2V, 0V, -2V, -4V, -6V, -8V, and -10V, respectively, indicating that the magnitude of the drain current decreases as the gate bias voltage increases.

To illustrate the behavior of the device, a prototype device featuring a 2x3 finger FinFET with titanium (Ti) / platinum (Pt) / gold (Au) multiple layer ohmic contacts to the P+ regions was fabricated and its electronic properties were measured. Though platinum and gold layers were used to form the ohmic contacts, the titanium layer is the most essential layer of the above three layers since titanium carbide can form upon deposition and annealing of titanium on the P+ regions. However, an ohmic contact made of only platinum is contemplated. Any metal that can be used to form a carbide upon its deposition and following thermal annealing on diamond, such as for example, tungsten (W), can be used as an ohmic contact. Ohmic contacts to the P+ regions (the source and drain regions) should be made of the same material. For this, we refer the reader to <FIG> which are scanning electron microscope (SEM) images of a transistor according to the technology described herein, with the source <NUM>, drain <NUM>, and gate <NUM> regions labeled with "S", "D", and "G", respectively. Here, the source <NUM> and drain <NUM> each comprise a metal contact coupled to a heavily doped P-type region of the prototype. The width of the fin channel <NUM> was designed to be <NUM> and the height of the fin channel, which is determined by the thickness of the P- layer, was designed to be <NUM>, resulting in an aspect ratio of about <NUM>:<NUM> for the height and width of the fin channel. Here, the terms "height" and "width" refer to distances measured along the z-axis and y-axis of <FIG>, respectively. The fin <NUM> channel is connected to the lightly doped P- region underneath the heavily doped P+ ohmic layer. The length of the P- channel was designed to be about <NUM> for this prototype. However, due to the sidewall slope of the channel resulting from the process of dry etching, the channel length is reduced significantly at the bottom of the fin <NUM> after etching through the <NUM> P-type film. A <NUM> atomic layer deposition of silicon dioxide (SiO<NUM>) was used to form the gate dielectric and aluminum was used to form the gate structure <NUM>.

<FIG> illustrates a graphical representation of the drain current as a function of the drain bias voltage at different gate bias voltages for the prototype diamond transistor illustrated in <FIG>. Drain and gate voltages are measured with respect to a grounded source. Curves <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> correspond to gate <NUM> bias voltages +2V, 0V, -2V, -4V, -6V, -8V, -10V, -12V, -14V, and -16V, respectively. The DC transfer characteristics of the device in <FIG> was measured for the left source, drain, and gate; the right source terminal was floated and not electrically coupled for measurement. The prototype includes a gate-to-drain overlap and the breakdown voltage is limited by the properties of the gate dielectric. The amount of overlap present in the prototype depends upon the processing technique utilized. As expected at a zero or positive gate bias voltage (i.e., 0V or 2V), the gated channel <NUM> is completely pinched off; hence, no channel current is observed in <FIG> at these voltages. With the increase of a negative gate bias voltage, the channel becomes increasingly conductive, as shown in <FIG>. At a small negative drain bias voltage, the channel current is linearly proportional to the drain bias voltage, though it becomes saturated at a more negative drain bias voltage. The maximum drain current observed was <NUM>. 22µA, resulting in an on/off current ratio larger than <NUM>:<NUM>. The gate leakage is shown in <FIG>. Curves <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> correspond to gate <NUM> bias voltages -16V, -14V, -12V, -10V, -8V, -6V, -4V, -2V, 0V, and +2V, respectively. Gate and drain voltages are again measured with respect to a grounded source. Only about a -<NUM>-nA gate current leakage was observed at large gate-to-drain potential differences. The maximum current of each fin channel was about <NUM> nA, which translates into a current density of <NUM>. 7mA/mm, assuming a fin channel width of <NUM>. Note that the current density here is calculated by dividing the maximum current by the width of the fin channel instead of its cross-sectional area. These transfer characteristics clearly demonstrate the concept of diamond FinFET. The breakdown voltage of the current device is larger in magnitude than that of the applied maximum gate voltage, |-15V|. Since the gate and drain overlap, the maximum breakdown voltage is essentially determined by the gate dielectric thickness and dielectric breakdown field. A dielectric thickness of <NUM> would support a breakdown voltage of 45V, assuming a breakdown field of <NUM>-MV!cm. To increase the breakdown voltage of the device, the gate-to-drain distance, Lgd, can be optimized to increase and/or maximize the power performance of the device at a desired frequency.

Turning to <FIG>, a graphical representation is shown plotting the square root of the drain current <MAT>, against the gate voltage for the extraction of the gate threshold voltage, wherein the gate voltages are measured with respect to a grounded source. In <FIG>, the drain current is taken at the saturation region. The exploration indicates a threshold voltage exists at -<NUM> V. In <FIG>, capacitance is plotted against the gate voltage at different frequencies for a MOS capacitor fabricated on the same chip. Curves <NUM>, <NUM>, <NUM>, and <NUM> correspond to frequencies <NUM>, <NUM>, <NUM>, and <NUM>, respectively. In <FIG>, a graphical representation is shown plotting the maximum accumulation capacitance against the frequency to illustrate the frequency dependence of the maximum accumulation capacitance. The dotted line is the calculated capacitance based upon a model with a serial resistor.

The device threshold voltage can be determined by the linear extrapolation method in the saturation region to avoid the impact of series resistance. As shown in <FIG>, the gate threshold voltage was measured to be about -<NUM>. 74V, which is close to the flat-band voltage calculated by band alignment. This is consistent with capacitance vs. gate voltage (CV) measurements on MOS capacitors fabricated on the same chip, as shown in <FIG>. The diamond substrate was grounded, hence at large negative gate biases, holes formed an accumulation layer, showing maximum capacitances. However, the measurement of maximum capacitance in the accumulation regime for different frequencies ranging from <NUM> to <NUM>, as shown in <FIG>, clearly indicates the impact of series resistance: with increased measuring frequency, maximum accumulation capacitance decreases. Even at a frequency of <NUM> as shown in <FIG> maximum capacitance only reaches <NUM> pF for a <NUM>-µm<NUM> MOS capacitor, which is about half of the theoretical value (<NUM> pF) based upon the SiO<NUM> thickness. Only at very low frequencies could the theoretical value be reached due to much less impact of the series resistance. This is consistent with other frequency-dependent studies for diamond MOS capacitors. Taking the series resistance into account, the maximum accumulation capacitance at various frequencies can be calculated as shown in <FIG>. The model and measured data show good agreement of the general trend of frequency dependency. The disagreement might originate from the interface charge on non-ideal diamond/dielectric interface. The ohmic contacts in the device are formed on diamond nominally doped with boron at a concentration of <NUM><NUM> cm-<NUM>. Although the doping in contact regions is much higher than that in the channel, it is still a much less than typical <NUM>-<NUM>×<NUM><NUM> cm-<NUM> doping concentration needed for a metal-to-insulator transition in diamond. Due to incomplete ionization, only less than <NUM>% of boron is activated at room temperature, leading to much larger contact resistance. This explains the frequency dependency in MOS CV measurement. To further understand this and explore the device's capability, a similar diamond FinFET was measured at a higher temperature. <FIG> show the measured IV (current voltage) at room temperature and <NUM> respectively. They were drawn in the same scale. In <FIG>, the inset is the room temperature data redrawn in a different scale to show the transfer characteristics.

Turning again to <FIG>, the drain current is plotted against the gate bias voltage for a device held at room temperature. Curves <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> correspond to gate bias voltages 2V, 0V, -2V, -4V, -6V, -8V, -10V, -12V, -14V, and - 16V. At room temperature, the maximum drain current is about <NUM> nA for a -16V bias voltage on the gate and drain. By operating the device at an elevated temperature of <NUM>, the current is increased by a factor of <NUM>, to about <NUM>µA with the same bias voltage, as shown in <FIG>. Curves <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> correspond to gate bias voltages 2V, 0V, -2V, -4V, -6V, -8V, -10V, -12V, -14V, and -16V. For a <NUM><NUM>cm-<NUM> boron doping concentration, the boron activation efficiency was calculated to be <NUM>×<NUM>-<NUM> at room temperature. At <NUM>, the boron activation efficiency increased to about <NUM>×<NUM>-<NUM>. This is consistent with the conduction current increase as shown in <FIG> indicating the limitation of ohmic contact in current devices. Through a transmission line measurement (TLM), the ohmic contact resistances at room temperature and <NUM> were extracted to be <NUM>Ω·mm and 47Ω·mm, respectively. This is also consistent with the observed current increase in the transistor measurement. In conclusion, a diamond FinFET with more than <NUM> on/off ratio was demonstrated. The threshold voltage and MOS capacitance measurements show a hole accumulation in the device. The <NUM> mA/mm maximum current density was observed at <NUM>. The relatively low current density was mainly limited by a high ohmic contact resistance due to the incomplete ionization of boron. A high ohmic contact resistance can be defined as an ohmic contact resistance above <NUM>Ω·mm. The observation of a higher conductivity at elevated temperatures indicates the potential of diamond FinFETs for high-temperature environments. A high temperature environment can be defined as an environment with a temperature greater than or equal to <NUM>. Or it can be defined as any temperature above room temperature as that temperature is understood by those skilled in the art. It is reasonable to expect that the contact resistance can be improved significantly by increasing the boron dopant concentration because higher boron doping levels in diamond has been demonstrated to improve the ohmic contact resistance for superconducting applications. For practical applications in power or radio frequency (RF) electronics, diamond transistors need to provide at least 1A/mm current density to be competitive. The cutoff frequency of a diamond FinFET also needs to reach <NUM> to be useful for RF applications at the Ka frequency band (the Ka band is a portion of the microwave part of the electromagnetic spectrum defined as frequencies in the range <NUM>-<NUM> gigahertz (GHz) i.e. wavelengths from slightly over one centimeter down to <NUM> millimeters).

There are challenges to improving the device performance through ohmic, gate dielectric engineering. However, this new diamond transistor device design, leveraging the existing technologies, represents a paradigm shift for future diamond research ranging from digital to RF electronics.

The remaining figures present the transistor above discussed in a more simplified review and may be helpful to the reader in better understanding the foregoing presentation.

Turning to Figures 2AA through 2BB, there is seen a variation of the cross sectional shown in <FIG>, Again, present are source <NUM>, drain <NUM>, semi conductive channel <NUM>, substrate <NUM>, and gate structure <NUM>. These are all evident in Figure 2AA.

Figure 2BB is identical to Figure 2AA except that it identifies gated channel <NUM>, buffer layer <NUM>, and drift region <NUM>. Semi conductive channel <NUM>, which is shown in <FIG>, comprises gated channel <NUM> and drift region <NUM> shown in Figure 2BB. Figure 2BB introduces the optional buffer layer <NUM>. Buffer layer <NUM> can reduce current leakage through the substrate when the device is, for example, turned "off". In a preferred embodiment, buffer layer <NUM>, gated channel <NUM>, and drift region <NUM> are made of lightly doped P-type diamond. In a preferred embodiment, buffer layer <NUM>, gated channel <NUM>, and drift region <NUM> are integrally made of lightly doped P-type diamond.

As seen in a number of the drawings, source <NUM> and drain <NUM> regions are supported by substrate <NUM>. In some embodiments, source <NUM> and drain <NUM> regions can be separated from substrate <NUM> by a buffer layer <NUM>. Buffer layer <NUM> provides additional voltage blocking when the transistor is "off". Buffer layer <NUM> can be removed in certain embodiments, thereby allowing direct contact of the substrate <NUM> to the source <NUM> and drain <NUM> regions. In some embodiments, the thickness of buffer layer <NUM> between source <NUM> and substrate <NUM> is different than the thickness of buffer layer <NUM> between the drain <NUM> and substrate <NUM>. In other embodiments, the thickness of buffer layer <NUM> between source <NUM> and substrate <NUM> is the same as the thickness of buffer layer <NUM> between drain <NUM> and substrate <NUM>. Increasing the thickness of buffer layer <NUM> essentially increases the current leakage path distance between source <NUM> and drain <NUM>, and through the substrate, thereby reducing the current leaked through substrate <NUM> when for example, the transistor is turned off.

Gate structure <NUM> is separated from gated channel <NUM> by a dielectric layer <NUM>, as seen in Figures 2AA-2CC. Dielectric layer <NUM> can also be used to insulate gate structure <NUM> from source <NUM>. Gate structure <NUM> can comprise or be composed of metal, alloys, or any suitable conductive material. A portion of channel <NUM> underneath a surface of the gate structure <NUM> is seen to define gated channel <NUM>. As can be seen in Figure 2BB, drift region <NUM> does not have a surface covered by gate structure <NUM>.

Turning now to <FIG> (which is a cross sectional view taken along line 3A-3A of <FIG>), source <NUM> and drain <NUM> are shown associated with gated channel <NUM>, which lies within channel <NUM> as shown in Figures 2AA-2BB. From Figures 2AA and 2BB, <FIG> also includes dielectric layer <NUM> which electrically insulates gate structure <NUM> from gated channel <NUM>.

In <FIG>, which is a variation of <FIG>, gate structure <NUM> no longer overlaps source <NUM> but is spaced therefrom to form a gap with channel <NUM> revealed. Channel <NUM> can be formed integrally with buffer layer <NUM>, gated channel <NUM>, and drift region <NUM> shown in Figures 2AA-2DD, and can be made of lightly doped P-type diamond. Channel <NUM> identified in Figure 2AA can comprise channel <NUM>, though this is not illustrated.

In <FIG> and <FIG>, which respectively mirror <FIG> and <FIG>, rather than one gated channel <NUM>, there is shown more than one gated channel. Three gated channels <NUM> have been chosen for illustration purposes only. In addition, the gate structure <NUM> wrapped around the three gated channels <NUM> can comprise several electrically independent gate structures, wherein each electrically independent gate structure wraps around a respective gated channel, though this is not illustrated. The benefit of using more than one gated channel <NUM> is that the current flowing through the transistor can be increased. The benefit of wrapping each gated channel <NUM> with its own gate structure is that, essentially, a parallel combination of single gated channel <NUM> devices is facilitated.

Returning to <FIG>, single gated channel <NUM> is coupled or defined between source <NUM> and drift region <NUM>, wherein gate structure <NUM> overlaps source <NUM>. One benefit of the gate structure <NUM> overlapping source <NUM> is that the device can operate with a higher maximum current and a reduced device breakdown voltage. Gate structure <NUM> overlapping source <NUM> is optional. In high frequency devices, this overlap can be nonexistent, such that channel <NUM> separates the gate structure <NUM> and the source region <NUM>. This is shown in <FIG> and <FIG>. If gate structure <NUM> does not overlap source <NUM>, the device operates with a lower maximum current and an increased breakdown voltage. In <FIG>, gate structure <NUM> does not overlap with source region <NUM>, and a single gated channel <NUM> is coupled (defined) between drift region <NUM> and channel <NUM> within channel <NUM>.

In <FIG>, a plurality of gated channels <NUM> is coupled between source <NUM> and drift region <NUM>, wherein the gate structure <NUM> overlaps with source region <NUM>.

In <FIG>, gate structure <NUM> does not overlap source region <NUM>, and the plurality of gated channels <NUM> is coupled/defined between drift region <NUM> and channel <NUM> within channel <NUM>. Gated channel <NUM> can be separated from the drain region <NUM> by a drift region <NUM>, which is situated within channel <NUM>,.

Turning to <FIG>, a cross sectional view of the transistor, along line 4A-4A of <FIG> shares the same reference numerals as found in <FIG> and further includes reference numerals <NUM> and <NUM> which are respectively, a semi conductive fin and a dielectric layer. The semi conductive fin <NUM> having a rectangular cross section is formed in a region of the gated channel <NUM> shown in <FIG>, the fin <NUM> electrically coupling source <NUM> and drain <NUM> regions of the transistor. Gate structure <NUM> can be formed on one, two, or three faces of fin <NUM>. The one, two, or three faces of fin <NUM> can comprise the top, side, and/or bottom surfaces of fin <NUM>. Therefore, gate structure <NUM> can be regarded as a multiple gate structure <NUM>. Gate structure <NUM> is electrically insulated from fin <NUM> by dielectric layer <NUM>. More than one gated channel <NUM> is seen in <FIG> which is otherwise the same as <FIG>. Gate structure <NUM> covers one, two, or three faces of each fin <NUM> in <FIG>. From these Figures, it is seen that gate structure <NUM> covers or surrounds an outermost surface of gated channel(s) <NUM>, wrapping around the top and side faces of gated channel(s) <NUM>.

<FIG> illustrates an embodiment of the transistor having one gated channel <NUM>, wherein the gated channel <NUM> comprises one semi conductive fin <NUM>. Alternatively, the gated channel <NUM> can comprise a plurality of gated channels <NUM><NUM> as seen in <FIG>, wherein each gated channel <NUM> comprises a semi conductive fin <NUM> all of which are covered or partially surrounded by gate structure <NUM>. In some embodiments, gated channel <NUM> is the semi conductive fin <NUM>, though in other embodiments, gated channel <NUM> comprises the semi conductive fin <NUM> so that fin <NUM> extends along a majority of the length of gated channel <NUM>. In all embodiments, dielectric layer <NUM> insulates gate structure <NUM> from gated channel <NUM> and fin <NUM>.

Methodology and fabrication methods for manufacturing a diamond Fin-SIT device can comprise a variety of different methods, as shown in <FIG>. Steps in the fabrication of the transistor comprise: forming good ohmic contacts to the source <NUM> and drain <NUM> regions by forming heavily doped P+ diamond regions on a semi conductive channel <NUM> to create the source <NUM> and drain <NUM> regions of the transistor with regrown P+ diamond; dry etching and/or using electron beam lithography on lightly doped P- regions of channel <NUM> to form a fin channel <NUM>. Regrown P+ diamond is P+ diamond whose growth occurred after the fabrication of the device began. Source <NUM> and drain <NUM> regions can be patterned by positioning a mask <NUM> comprising, for example, silicon dioxide (SiO2) or metal, on a surface of the lightly doped P- diamond region. The patterned sample can be loaded into a diamond growth apparatus, such as, for example, a microwave plasma CVD growth apparatus configured for diamond growth with high boron doping as shown in <FIG>. The mask can be removed by either wet or dry etching until the source <NUM> and drain <NUM> regions contain the desired amount of heavily doped P+ diamond, as shown in <FIG>. The contacts to the P- channel regions of channel <NUM> can be significantly reduced by incorporating the heavily doped P+ diamond layers in the source <NUM> and/or drain <NUM>. Following the ohmic regrowth of the source <NUM> and drain <NUM>, the gate dielectric <NUM> can be deposited onto the gated channel <NUM> by atomic layer deposition or other methods as shown in <FIG>. The deposition can be conformal such that some or all of the surfaces/faces of the fin <NUM> are covered by dielectric layer <NUM>. A final step can comprise forming a gate <NUM> on the top and side faces of dielectric layer <NUM> formed on the faces of channel <NUM>, as partially shown in <FIG>. To conformably wrap gate <NUM> around the sidewalls of the fin <NUM>, aluminum can be sputtered with a photoresist in front of the desired regions of the transistor (e.g. regions not intended to be covered by aluminum such as: source <NUM>, drain <NUM>, and regions of dielectric layer <NUM>) to ensure a proper lift-off of the aluminum in the desired regions. The metal or conductive contacts <NUM> to the P+ layers can be fabricated to make ideal ohmic contacts. The illustrated process described here features a metal-oxide semiconductor (MOS) styled gated channel, though other channel types can be fabricated using these methods such as, for example, a Schottky gated channel. The fabrication steps described herein can be performed in any suitable order.

ln a Schottky gated channel when using diamond, the gate must be in the channel and cannot overlap the source. With a MOS gated structure, the gate can overlap the source.

As a variation in composition, it is noted that there is symmetry present between P-type and N-type dopants such that source <NUM> and drain <NUM> regions can comprise heavily doped N-type diamond instead of comprising heavily doped P-type diamond. Additionally, channel <NUM> and buffer layer <NUM> can comprise lightly doped N-type diamond instead of comprising lightly doped P-type diamond. Substrate <NUM> can comprise intrinsic diamond or P-type diamond instead of comprising N-type diamond, and if substrate105 is doped, substrate <NUM> can be doped at any suitable P-type dopant concentration. In this circumstance, the device is turned "on" at positive gate voltages and the drain current increases as the gate voltage increases. The current through the drift region can still be modeled according to equation (<NUM>).

As another variation not forming part of the claimed invention, though the transistor is described as comprising doped and undoped diamond, which is a wide-band gap material, the transistor can instead comprise other doped and undoped wide-band gap materials in general. For example, the transistor can comprise doped and undoped silicon carbide instead of doped and undoped diamond. In one embodiment, source <NUM> and drain <NUM> regions can comprise heavily doped P-type silicon carbide. Channel <NUM> and buffer layer <NUM> can comprise lightly doped P-type silicon carbide. Substrate <NUM> can comprise intrinsic silicon carbide or N-type silicon carbide. Here, an N-type dopant can be nitrogen and a P-type dopant can be aluminum.

Further, since there is a symmetry between N-type and P-type dopants in silicon carbide, an example not forming part of the claimed invention can include the source <NUM> and drain <NUM> regions comprising heavily doped N-type silicon carbide. Channel <NUM> and buffer layer <NUM> can comprise lightly doped N-type silicon carbide. Substrate <NUM> can comprise intrinsic silicon carbide or P-type silicon carbide. An N-type dopant can be nitrogen and a P-type dopant can be aluminum.

A Schottky gated channel is a gated channel that is in direct electrical contact with a metal gate. For an embodiment that includes a Schottky gated channel instead of a MOS styled gated channel, the transistor does not comprise dielectric layer <NUM>, and gate structure <NUM> is in contact with gated channel <NUM>. At positive gate voltages, holes are repelled from the gate-channel interface and the gated channel <NUM> can be pinched off. At sufficiently large negative gate voltages, holes are attracted to the gate-channel interface and current can leak through gate structure <NUM> since the Schottky barrier at the gate-channel interface does not prevent holes from flowing into the gate structure. As a result, the transistor having a Schottky gated channel is limited to operating at relatively small negative gate voltages which imposes a constraint on the channel conduction and therefore also on the performance of the transistor.

In a sample created by the inventors, a <NUM> × <NUM> undoped diamond substrate was used with an epitaxially grown P+/P- bilayer on top of the diamond substrate. The P+ layer was patterned and dry etched to define the ohmic area and also to expose the channel area. Titanium/Platinum/Gold (Ti/Pt/Au) was evaporated to form a good ohmic contact after <NUM> degrees centigrade annealing. E-beam lithography and O2 plasma dry etching were used subsequently to form <NUM> wide and <NUM> micro meter tall fins. A silicon dioxide (SiO<NUM>) gate dielectric was deposited by atomic layer deposition at <NUM> degrees centigrade. To conformably wrap the gate around the sidewalls of the fins, aluminum (Al) metal was sputtered with a photoresist in place. The metal was then lifted off. Only <NUM> of Al was used to ensure successful liftoff by sputtering. Finally, the ohmic contact pads were open with wet etching.

Modulation by the gate validates the concept of a fin-based diamond electronic device.

Claim 1:
A transistor comprising:
a source region(<NUM>), a drain region (<NUM>) and a semi conductive substrate (<NUM>), the source and drain regions being disposed on the semi conductive substrate;
a semi conductive channel (<NUM>) formed between the source (<NUM>) and drain (<NUM>) regions, a portion of the semi conductive channel (<NUM>) comprising a fin (<NUM>);
a gate structure (<NUM>) covering a surface of the fin (<NUM>), the semi conductive channel (<NUM>) further comprising a drift region (<NUM>) coupled between the fin (<NUM>) and the drain region (<NUM>), wherein:
the source (<NUM>) and drain (<NUM>) regions comprise diamond doped at a first amount; and the semi conductive channel (<NUM>) comprises diamond doped at a second amount, wherein the first amount is larger than the second amount;
wherein the diamond doped at a first amount is doped with a P-type dopant and the diamond doped at the second amount is doped with a P-type dopant; or
wherein the diamond doped at the first amount is doped with an N-type dopant and the diamond doped at the second amount is doped with an N-type dopant.