Patent Description:
In an organic light-emitting display apparatus, thin-film transistors (TFTs) may be located in each (sub) pixel to control the luminance of each (sub) pixel. Such TFTs control the luminance of the sub (pixel) according to a received data signal.

However, luminance realized in a (sub) pixel of a general display apparatus may be different from that depending on a received data signal. Accordingly, an image displayed on the general display apparatus may have deteriorated quality.

<CIT> discloses an electro-optical device which comprises, above a substrate, pixel electrodes, thin film transistors connected to the pixel electrodes, an upper light shielding film for covering the upper side of the channel regions of the thin film transistors, and a lower light shielding film for covering the lower side of the channel regions of the thin film transistors. Each of the upper light shielding film and the lower light shielding film has projecting portions for defining corner cuts in an opening region of each pixel, in the intersection regions where data lines and scanning lines intersect each other. Both projecting portions are connected to each other through contact holes. The channel region of the thin film transistors are disposed in the intersection regions.

<CIT> discloses an electro-optical device which includes scanning lines and data lines intersecting with each other, wherein pixel circuits are provided corresponding to the intersection thereof, and shield wires. The pixel circuit includes a light emitting element, one transistor which controls a current flowing to the light emitting element, and the other transistor of which conduction state is controlled according to a scanning signal which is supplied to the scanning line, wherein the other transistor selectively connects a data line to the gate electrode of the one transistor. The shield wires are provided between the data line and the one transistor when seen in the plan view.

<CIT> discloses an organic light emitting diode (OLED) display which includes: a substrate; a scan line formed on the substrate and that transfers a scan signal; a data line and a driving voltage line that intersect the scan line and that transfer a data signal and a driving voltage, respectively; a switching thin film transistor (TFT) connected to the scan line and the data line; a driving TFT connected to the switching TFT and the driving voltage line; an OLED connected to the driving TFT; a storage capacitor connected between the driving voltage line and a driving gate electrode of the driving TFT; and a boosting capacitor connected to the storage capacitor, wherein the storage capacitor has at least one capacitor opening.

<CIT> discloses an organic light emitting diode display which includes a substrate; a scan line on the substrate for transferring a scan signal; an initialization voltage line on the substrate for transferring an initialization voltage; a data line crossing the scan line and for transferring a data signal; a driving voltage line crossing the scan line and for transferring a driving voltage; a switching thin film transistor coupled to the scan line and the data line; a driving thin film transistor coupled to a switching drain electrode of the switching thin film transistor; an organic light emitting diode (OLED) electrically coupled to a driving drain electrode of the driving thin film transistor; a light emission control thin film transistor between the driving drain electrode and the OLED; and a bypass thin film transistor between the initialization voltage line and a light emission control drain electrode of the light emission control thin film transistor; wherein the bypass thin film transistor transfers a portion of a driving current transferred by the driving thin film transistor according to a bypass control signal transferred by a bypass control line.

<CIT> discloses an organic light emitting diode display device which includes an internal compensation structure for threshold voltage variations in driving transistors. A shield electrode may be formed using the same metal layer as that of scan lines or data lines, thereby providing an organic light-emitting diode display device in which the effect of coupling between the gate electrode of driving thin-film transistors and the data lines is minimized.

<CIT> discloses an organic electroluminescence device which includes an organic electro luminescence light emitting element; and a driving circuit for driving the organic electro luminescence light emitting element, wherein the driving circuit includes (A) an element driving transistor, (B) a video-signal write transistor, and (C) a capacitor having a pair of particular and other electrodes, with regard to the element driving transistor, (A-<NUM>) a source/drain area provided on a particular side of the element driving transistor to serve as a particular source/drain area of the element driving transistor is connected to a current supply section, and (A-<NUM>) a source/drain area provided on the other side of the element driving transistor to serve as another source/drain area of the element driving transistor is connected to the anode electrode of the organic electro luminescence light emitting element and the particular electrode of the capacitor, forming a second node.

One or more embodiments of the present invention include a display apparatus for preventing quality deterioration of a displayed image. According to the invention there is provided a display apparatus according to claim <NUM>.

According to the invention, a display apparatus comprises a first thin-film transistor (T3) comprising a gate electrode and a first semiconductor comprising a first source area and a first drain area;a storage capacitor (Cst) comprising a first storage capacitor plate and a second storage capacitor plate, the second capacitor plate overlapping the first storage capacitor plate and being above the first storage capacitor plate, wherein the first storage capacitor plate is electrically coupled to the first drain area;a driving thin-film transistor (T1) comprising a driving gate electrode formed as an integral part of the first storage capacitor plate and a driving semiconductor comprising a driving drain area coupled to the first source area and a driving source area;a data signal line over the second storage capacitor plate;a first shield layer (SD1) in a layer between the data signal line and the first semiconductor, wherein the gate electrode of the first thin-film transistor (T3) comprises a first gate electrode and a second gate electrode, wherein the second storage capacitor plate comprises the first shield layer (SD1), and the first shield layer (SD1) overlaps a part of the first semiconductor between the first gate electrode and the second gate electrode of the first thin-film transistor; anda second shield layer (SD3) in a layer between the data signal line and the driving gate electrode, wherein the second shield layer (SD3) is integrally formed with the second storage capacitor plate as a portion of said second storage capacitor plate not overlapping with the first capacitor plate, and the second shield layer (SD3) extends from the edge of the first storage capacitor plate in a direction towards the data signal line.

Aspects and features of one or more embodiments of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of the embodiments and the accompanying drawings. Rather, these embodiments are provided so that this disclosure will be more thorough and will more fully convey the concepts of the present embodiments to one of ordinary skill in the art, and the present invention will only be defined by the appended claims.

Hereinafter, one or more embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. Those components that are the same or are in correspondence are rendered the same reference numeral regardless of the figure number, and redundant explanations are omitted.

It will be understood that when a layer, region, or component is referred to as being "formed on," another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present. Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

In the following examples, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.

<FIG> is an equivalent circuit diagram of a (sub) pixel of an organic light-emitting display apparatus, according to some embodiments of the present invention.

As shown in <FIG>, the (sub) pixel of the organic light-emitting display apparatus according to an embodiment includes a plurality of signal lines, a plurality of thin-film transistors (TFTs) coupled to the plurality of signal lines, a storage capacitor Cst, and an organic light-emitting device OLED. Here, the plurality of signal lines may be shared by a plurality of (sub) pixels.

The plurality of TFTs include a driving TFT T1, a switching TFT T2, a compensating TFT T3, an initialization TFT T4, an operation control TFT T5, and an emission control TFT T6.

The plurality of signal lines include a scan line <NUM> transmitting a scan signal Sn, a previous scan line <NUM> transmitting a previous scan signal Sn-<NUM> to the initialization TFT T4, an emission control line <NUM> transmitting an emission control signal En to the operation control TFT T5 and the emission control TFT T6, a data line <NUM> crossing the scan line <NUM> and transmitting a data signal Dm, a driving voltage line <NUM> transmitting a driving voltage ELVDD and disposed almost in parallel to the data line <NUM>, and an initialization voltage line <NUM> transmitting an initialization voltage Vint for initializing the driving TFT T1.

A gate electrode G1 of the driving TFT T1 is coupled to a first storage capacitor plate Cst1 of the storage capacitor Cst, a source electrode S1 of the driving TFT T1 is coupled to the driving voltage line <NUM> through the operation control TFT T5, and a drain electrode D1 of the driving TFT T1 is electrically coupled to a pixel electrode of the organic light-emitting device OLED through the emission control TFT T6. According to a switching operation of the switching TFT T2, the driving TFT T1 receives the data signal Dm and supplies a driving current IOLED to the organic light-emitting device OLED.

A gate electrode G2 of the switching TFT T2 is coupled to the scan line <NUM>, a source electrode S2 of the switching TFT T2 is coupled to the data line <NUM>, and a drain electrode D2 of the switching TFT T2 is coupled to the source electrode S1 of the driving TFT T1 and coupled to the driving voltage line <NUM> through the operation control TFT T5. Such a switching TFT T2 is turned on according to the scan signal Sn received through the scan line <NUM>, and performs a switching operation by transmitting the data signal Dm from the data line <NUM> to the source electrode S1 of the driving TFT T1.

A gate electrode G3 of the compensation TFT T3 is coupled to the scan line <NUM>, a source electrode S3 of the compensating TFT T3 is coupled to the drain electrode D1 of the driving TFT T1 while being coupled to the pixel electrode of the organic light-emitting device OLED through the emission control TFT T6, and a drain electrode D3 of the compensating TFT T3 is coupled to the first storage capacitor plate Cst1 of the storage capacitor Cst, a drain electrode D4 of the initialization TFT T4, and the gate electrode G1 of the driving TFT T1. Such a compensating TFT T3 is turned on according to the scan signal Sn received through the scan line <NUM>, and diode-connects the driving TFT T1 by electrically coupling the gate electrode G1 and the drain electrode D1 of the driving TFT T1.

A gate electrode G4 of the initialization TFT T4 is coupled to the previous scan line <NUM>, a source electrode S4 of the initialization TFT T4 is coupled to the initialization voltage line <NUM>, and the drain electrode D4 of the initialization TFT T4 is coupled to the first storage capacitor plate Cst1 of the storage capacitor Cst, the drain electrode D3 of the compensating TFT T3, and the gate electrode G1 of the driving TFT T1. The initialization TFT T4 is turned on according to the previous scan signal Sn-<NUM> received through the previous scan line <NUM>, and performs an initialization operation by initializing a voltage of the gate electrode G1 of the driving TFT T1 by transmitting the initialization voltage Vint to the gate electrode G1 of the driving TFT T1.

A gate electrode G5 of the operation control TFT T5 is coupled to the emission control line <NUM>, a source electrode S5 of the operation control TFT T5 is coupled to the driving voltage line <NUM>, and a drain electrode D5 of the operation control TFT T5 is coupled to the source electrode S1 of the driving TFT T1 and the drain electrode D2 of the switching TFT T2.

A gate electrode G6 of the emission control TFT T6 is coupled to the emission control line <NUM>, a source electrode S6 of the emission control TFT T6 is coupled to the drain electrode D1 of the driving TFT T1 and the source electrode S3 of the compensating TFT T3, and a drain electrode D6 of the emission control TFT T6 is electrically coupled to the pixel electrode of the organic light-emitting device OLED. The operation control TFT T5 and an emission control TFT T6 are concurrently (e.g., simultaneously) turned on according to the emission control signal En received through the emission control line <NUM>, and transmit the driving voltage ELVDD to the organic light-emitting device OLED such that the driving current IOLED flows through the organic light-emitting device OLED.

A second storage capacitor plate Cst2 of the storage capacitor Cst is coupled to the driving voltage line <NUM>, and a counter electrode of the organic light-emitting device OLED is coupled to a common voltage ELVSS. Accordingly, the organic light-emitting device OLED emits light by receiving the driving current IOLED from the driving TFT T1, thereby displaying an image.

Detailed operations of a pixel in such an organic light-emitting display apparatus will now be briefly described.

First, the previous scan signal Sn-<NUM> in a low level is supplied through the previous can line <NUM> during an initialization period. Then, the initialization TFT T4 is turned on in response to the previous scan signal Sn-<NUM> in the low level, and thus the initialization voltage Vint is transmitted to the gate electrode G1 of the driving TFT T1 from the initialization voltage line <NUM> through the initialization TFT T4, and the driving TFT T1 is initialized by the initialization voltage Vint.

Then, the scan signal Sn in a low level is supplied through the scan line <NUM> during a data programming period. Accordingly, the switching TFT T1 and the compensating TFT T3 are turned on in response to the scan signal Sn in the low level. Thus, the driving TFT T1 is diode-coupled by the turned on compensating TFT T3 and is biased in a forward direction. Then, a compensating voltage (Dm+Vth, wherein Vth has a negative value) obtained by subtracting a threshold voltage Vth of the driving TFT T1 from the data signal Dm supplied from the data line <NUM> is applied to the gate electrode G1. Next, the driving voltage ELVDD and the compensating voltage are applied to two ends of the storage capacitor Cst, and thus a charge corresponding to a voltage difference between the two ends is stored in the storage capacitor Cst.

Then, the emission control signal En supplied from the emission control line <NUM> during an emission period is changed from a high level to a low level. Accordingly, the operation control TFT T5 and the emission control TFT T6 are turned on according to the emission control signal En in the low level during the emission period. Then, the driving current IOLED determined based on a voltage difference between a voltage of the gate electrode G1 of the driving TFT T1 and the driving voltage ELVDD is generated, and the driving current IOLED is supplied to the organic light-emitting device OLED through the emission control TFT T6. A gate-source voltage VGS of the driving TFT T1 maintains '(Dm+Vth)-ELVDD' by the storage capacitor Cst during the emission period, and because the driving current IOLED is proportional to '(Dm-ELVDD)<NUM>' (i.e., a square of a value obtained by subtracting the threshold voltage Vth from the gate-source voltage VGS, according to a current-voltage relationship of the driving TFT T1), the driving current IOLED may be determined regardless of the threshold voltage Vth of the driving TFT T1.

A more detailed structure of the (sub) pixel of the organic light-emitting display apparatus of <FIG> will now be described with reference to <FIG>.

<FIG> is a schematic diagram showing locations of the plurality of TFTs and the capacitor in the (sub) pixel of <FIG>, according to an embodiment of the present invention. <FIG> are schematic diagrams showing components of the plurality of TFTs and the capacitor of <FIG> by each layer. In other words, each of <FIG> illustrates an arrangement of a wire or a semiconductor layer disposed in the same layer, and an insulating layer may be located between layers shown in <FIG>. For example, a first insulating layer <NUM> of <FIG> may be located between the layer of <FIG> and the layer of <FIG>, a second insulating layer <NUM> of <FIG> may be located between the layer of <FIG> and the layer of <FIG>, and an interlayer insulating layer <NUM> of <FIG> may be located between the layer of <FIG> and the layer of <FIG>. Here, contact holes etc. may be formed on such insulating layers so that the layers of <FIG> are electrically coupled to each other.

The (sub) pixel of the organic light-emitting display apparatus, according to the current embodiment, includes the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, and the initialization voltage line <NUM>, which respectively apply the scan signal Sn, the previous scan signal Sn-<NUM>, the emission control signal En, and the initialization voltage Vint and are formed along a row direction. Also, the (sub) pixel of the organic light-emitting display apparatus, according to the current embodiment, may include the data line <NUM> and the driving voltage line <NUM>, which cross the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, and the initialization voltage line <NUM>, and respectively apply the data signal Dm and the driving voltage ELVDD to the (sub) pixel.

Also, the (sub) pixel may include the driving TFT T1, the switching TFT T2, the compensating TFT T3, the initialization TFT T4, the operation control TFT T5, the emission control TFT T6, the storage capacitor Cst, and an organic light-emitting device.

The driving TFT T1, the switching TFT T2, the compensating TFT T3, the initialization TFT T4, the operation control TFT T5, and the emission control TFT T6 are formed on a semiconductor layer as shown in <FIG>, wherein the semiconductor layer may have a shape curving or contouring in any shape. The semiconductor layer may include a driving semiconductor layer 131a corresponding to the driving TFT T1, a switching semiconductor layer 131b corresponding to the switching TFT T2, a compensating semiconductor layer 131c1, 131c2, and 131c3 corresponding to the compensating TFT T3, initialization semiconductor layer 131d1, 131d2, and 131d3 corresponding to the initialization TFT T4, an operation control semiconductor layer 131e corresponding to the operation control TFT T5, and an emission control semiconductor layer 131f corresponding to the emission control TFT T6. In other words, the driving semiconductor layer 131a, the switching semiconductor layer 131b, the compensating semiconductor layer 131c1, 131c2, and 131c3, the initialization semiconductor layer 131d1 through 131d3, the operation control semiconductor layer 131e, and the emission control semiconductor layer 131f may be understood to constitute partial regions of the semiconductor layer of <FIG>.

The semiconductor layer may include polysilicon. Also, the semiconductor layer may include, for example, a channel region that is not doped with an impurity, and source and drain regions that are formed as impurities are doped on two sides of the channel region. Here, the impurities may vary according to a type of a TFT, and may be N-type impurities or P-type impurities. Also, the source or drain region may be interpreted as a source or drain electrode of a TFT. In other words, for example, a driving source electrode 176a may correspond to a driving drain region doped with an impurity near the driving semiconductor layer 131a of the semiconductor layer of <FIG>, and a driving drain electrode 177a may correspond to a driving drain region doped with an impurity near the driving semiconductor layer 131a of the semiconductor layer of <FIG>. Also, a region of the semiconductor layer of <FIG> between TFTs may be doped with an impurity to operate as a wire electrically coupling the TFTs.

Meanwhile, the storage capacitor Cst may be formed. The storage capacitor Cst may include a first storage capacitor plate 125a and a second storage capacitor plate <NUM>, wherein the second insulating layer <NUM> is located therebetween. Here, the first storage capacitor plate 125a may also operate as a driving gate electrode of the driving TFT T1. In other words, the driving gate electrode and the first storage capacitor plate 125a may be integrally formed. Hereinafter, for convenience, the same reference numeral as the first storage capacitor plate 125a may be used for the driving gate electrode.

The first storage capacitor plate 125a may have a rectangular shape isolated from an adjacent (sub) pixel as shown in <FIG>. Such a first storage capacitor plate 125a may be formed in the same layer and of the same material as the scan line <NUM>, the previous scan line <NUM>, and the emission control line <NUM> as shown in <FIG>.

For reference, a switching gate electrode 125b and a compensating gate electrode 125c1 and 125c2 may be a part of the scan line <NUM> crossing the semiconductor layer or a part protruding from the scan line <NUM>, an initialization gate electrode 125d1 and 125d2 may be parts of the previous scan line <NUM> crossing the semiconductor layer or parts protruding from the previous scan line <NUM>, and an operation control gate electrode 125e and an emission control gate electrode 125f may be parts of the emission control line <NUM> crossing the semiconductor layer or parts protruding from the emission control line <NUM>.

The second storage capacitor plates <NUM> of adjacent (sub) pixels may be coupled to each other, and as shown in <FIG>, may be formed in the same layer and of the same material as the initialization voltage line <NUM>. A storage opening <NUM> may be formed on the second storage capacitor plate <NUM> and may enable the first storage capacitor plate 125a and a compensating drain electrode 177c of the compensating TFT T3 to be electrically coupled to each other through a connecting unit <NUM> described in more detail later. The second storage capacitor plate <NUM> may be coupled to the driving voltage line <NUM> through a contact hole <NUM> formed on the interlayer insulating layer <NUM>.

The driving TFT T1 includes the driving semiconductor layer 131a, the driving gate electrode 125a, the driving source electrode 176a, and the driving drain electrode 177a. As described above, the driving gate electrode 125a may also operate as the first storage capacitor plate 125a. The driving source electrode 176a is an external region (in -x direction in <FIG>) of the driving gate electrode 125a, and the driving drain electrode 177a is an external region (in +x direction in <FIG>) of the driving gate electrode 125a and is arranged opposite to the driving source electrode 176a based on the driving gate electrode 125a.

The switching TFT T2 includes the switching semiconductor layer 131b, the switching gate electrode 125b, a switching source electrode 176b, and a switching drain electrode 177b. The switching source electrode 176b may be electrically coupled to the data line <NUM> through a contact hole <NUM> formed through the first insulating layer <NUM>, the second insulating layer <NUM>, and the interlayer insulating layer <NUM>. Here, if required, a part near the contact hole <NUM> of the data line <NUM> may be understood to be the source electrode S2 of the switching TFT T2. The switching drain electrode 177b corresponds to a switching drain region doped with an impurity near the switching semiconductor layer 131b.

The compensating TFT T3 includes the compensating semiconductor layer 131c1, 131c2, and 131c3, the compensating gate electrode 125c1 and 125c2, a compensating source electrode 176c, and the compensating drain electrode 177c. The compensating source electrode 176c corresponds to a compensating source region doped with an impurity near the compensating semiconductor layer, and the compensating drain electrode 177c corresponds to a compensating drain region doped with an impurity near the compensating semiconductor layer. The compensating gate electrode 125c1 and 125c2 is a dual gate electrode including a first gate electrode 125c1 and a second gate electrode 125c2, and may prevent or reduce generation of a leakage current. The compensating drain electrode 177c of the compensating TFT T3 may be coupled to the first storage capacitor plate 125a through the connecting unit <NUM>. The compensating semiconductor layer may include a part or component 131c1 corresponding to the first gate electrode 125c1, a part or component 131c3 corresponding to the second gate electrode 125c2, and a part or component 131c2 between the parts 131c1 and 131c3.

As shown in <FIG>, the connecting unit <NUM> may be formed of the same material and in the same layer as the data line <NUM>. One end of the connecting unit <NUM> is coupled to the compensating drain electrode 177c and an initialization drain electrode 177d through a contact hole <NUM> formed through the first insulating layer <NUM>, the second insulating layer <NUM>, and the interlayer insulating layer <NUM>, and the other end of the connecting unit <NUM> is coupled to the first storage capacitor plate 125a through a contact hole <NUM> formed through the second insulating layer <NUM> and the interlayer insulating layer <NUM>. Here, the other end of the connecting unit <NUM> is coupled to the first storage capacitor plate 125a through the storage opening <NUM> formed on the second storage capacitor plate <NUM>.

The initialization TFT T4 includes an initialization semiconductor layer 131d1, 131d2, and 131d3, an initialization gate electrode 125d1 and 125d2, an initialization source electrode 176d, and the initialization drain electrode 177d. The initialization drain electrode 177d corresponds to an initialization drain region doped with an impurity near the initialization semiconductor layer 131d1, 131d2, and 131d3.

The initialization source electrode 176d is coupled to the initialization voltage line <NUM> through an initialization connecting line <NUM>. One end of the initialization connecting line <NUM> may be coupled to the initialization voltage line <NUM> through a contact hole <NUM> formed through the second insulating layer <NUM> and the interlayer insulating layer <NUM>, and the other end of the initialization connecting line <NUM> may be coupled to the initialization source electrode 176d through a contact hole <NUM> formed through the first insulating layer <NUM>, the second insulating layer <NUM>, and the interlayer insulating layer <NUM>.

The operation control TFT T5 includes the operation control semiconductor layer 131e, the operation control gate electrode 125e, an operation control source electrode 176e, and an operation control drain electrode 177e. The operation control source electrode 176e may be electrically coupled to the driving voltage line <NUM> through a contact hole <NUM> formed through the first insulating layer <NUM>, the second insulating layer <NUM>, and the interlayer insulating layer <NUM>. Here, if required, a part near the contact hole <NUM> of the driving voltage line <NUM> may be understood to be the source electrode S5 of the operation control TFT T5. The operation control drain electrode 177e corresponds to an operation control drain region doped with an impurity near the operation control semiconductor layer 131e.

The emission control TFT T6 includes the emission control semiconductor layer 131f, the emission control gate electrode 125f, an emission control source electrode 176f, and an emission control drain electrode 177f. The emission control source electrode 176f corresponds to an emission control source region doped with an impurity near the emission control semiconductor layer 131f. As shown in <FIG>, the emission control drain electrode 177f may be understood to be a part formed on the interlayer insulating layer <NUM> together with the data line <NUM> or the driving voltage line <NUM>. The emission control drain electrode 177f may be coupled to a lower semiconductor layer through a contact hole <NUM> formed through the first insulating layer <NUM>, the second insulating layer <NUM>, and the interlayer insulating layer <NUM>. Alternatively, it may be understood that a part of the lower semiconductor layer is a emission control drain electrode, and the reference numeral 177f denote an intermediate connection layer for coupling the emission control drain electrode and the pixel electrode of the organic light-emitting device OLED.

One end of the driving semiconductor layer 131a of the driving TFT T1 is coupled to the switching semiconductor layer 131b and the compensating semiconductor layer, and the other end of the driving semiconductor layer 131a is coupled to the operation control semiconductor layer 131e and the emission control semiconductor layer 131f. Accordingly, the driving source electrode 176a is coupled to the switching drain electrode 177b and the operation control drain electrode 177e, and the driving drain electrode 177a is coupled to the compensating source electrode 176c and the emission control source electrode 176f.

Meanwhile, the switching TFT T2 is used as a switching device for selecting a (sub) pixel to emit light. The switching gate electrode 125b is coupled to the scan line <NUM>, the switching source electrode 176b is coupled to the data line <NUM>, and the switching drain electrode 177b is coupled to the driving TFT T1 and the operation control TFT T5.

Also, as shown in <FIG>, the emission control drain electrode 177f of the emission control TFT T6 is coupled to the pixel electrode of the organic light-emitting device OLED through a contact hole <NUM> formed on a passivation film or planarization film covering the data line <NUM> or the driving voltage line <NUM> formed in the same layer.

<FIG> is a cross-sectional view taken along the line VII-VII of <FIG>. As shown in <FIG>, various components described above may be arranged on a substrate <NUM>. The substrate <NUM> may be formed of any one of various suitable substrate materials, such as glass, a metal, and plastic. A buffer layer <NUM> may be disposed on the substrate <NUM> as occasion demands. The buffer layer <NUM> may flatten a surface of the substrate <NUM> or prevent impurities from penetrating into a semiconductor layer on the substrate <NUM>. Such a buffer layer <NUM> may be a single layer or multilayer structure formed of silicon oxide, silicon nitride, or silicon oxynitride.

The driving semiconductor layer 131a, the switching semiconductor layer 131b, and the compensating semiconductor layer described above with reference to <FIG> may be arranged on the buffer layer <NUM>. The first insulating layer <NUM> formed of silicon nitride, silicon oxide, or silicon oxynitride may be arranged on the driving semiconductor layer 131a, the switching semiconductor layer 131b, and the compensating semiconductor layer.

Wires including the driving gate electrode 125a, the scan line <NUM> including the switching gate electrode 125b and the compensating gate electrode 125c1 and 125c2, the previous scan line <NUM> including the initialization gate electrode 125d1 and 125d2, the emission control line <NUM> including the operation control gate electrode 125e and the emission control gate electrode 125f, which have been described above with reference to <FIG>, may be arranged on the first insulating layer <NUM>. The driving gate electrode 125a, the scan line <NUM>, the previous scan line <NUM>, and the emission control line <NUM> may be collectively referred to as a first gate wire.

The second insulating layer <NUM> may cover the first gate wire. The second insulating layer <NUM> may be formed of silicon nitride, silicon oxide, or silicon oxynitride. The second storage capacitor plate <NUM> and the initialization voltage line <NUM> described above with reference to <FIG> may be arranged on the second insulating layer <NUM>. The second storage capacitor plate <NUM> and the initialization voltage line <NUM> may be collectively referred to as a second gate wire.

The interlayer insulating layer <NUM> is disposed on the second gate wire. The interlayer insulating layer <NUM> may be formed of silicon nitride, silicon oxide, or silicon oxynitride.

The data line <NUM>, the driving voltage line <NUM>, the connecting unit <NUM>, the initialization connecting line <NUM>, and the emission control drain electrode 177f, which have been described above with reference to <FIG>, may be arranged on the interlayer insulating layer <NUM>. The data line <NUM>, the driving voltage line <NUM>, the connecting unit <NUM>, the initialization connecting line <NUM>, and the emission control drain electrode 177f may be collectively referred to as a data wire. As described above, the data line <NUM>, the driving voltage line <NUM>, the connecting unit <NUM>, the initialization connecting line <NUM>, and the emission control drain electrode 177f may be electrically coupled to a lower semiconductor layer or an electrode through the contact holes <NUM> through <NUM> formed on at least a part of the first insulating layer <NUM>, the second insulating layer <NUM>, and the interlayer insulating layer <NUM>.

A passivation film or planarization film is disposed on the data wire, and a pixel electrode of an organic light-emitting device may be arranged on the passivation film or planarization film. The pixel electrode may be coupled to the emission control drain electrode 177f through the contact hole <NUM> formed on the passivation film or planarization film.

Meanwhile, as shown in <FIG>, <FIG>, and <FIG>, the second storage capacitor plate <NUM> may include a first shield layer SD1 at one side. As shown in <FIG> and <FIG>, the first shield layer SD1 may be a part protruding from the second storage capacitor plate <NUM>. The first shield layer SD1 is to be understood as a part of the second storage capacitor plate <NUM>, which extends between the data line <NUM> and at least a part between the first gate electrode 125c1 and the second gate electrode 125c2 of the compensating TFT T3.

For reference, <FIG> is a diagram of one (sub) pixel, and a (sub) pixel having the same or similar structure may be disposed top, bottom, left, and right of the (sub) pixel. In <FIG>, a (sub) pixel P1 corresponds to the (sub) pixel of <FIG>, and a part of a (sub) pixel P2 disposed next to the (sub) pixel P1 in the +x direction of <FIG> are illustrated. The (sub) pixel P2 may also include the data line <NUM>, and accordingly, the first shield layer SD1 of the (sub) pixel P1 may be understood to be a part of the second storage capacitor plate <NUM>, which extends between the data line <NUM> of the (sub) pixel P2 and at least a part between the first and second gate electrodes 125c1 and 125c2 of the compensating TFT T3.

If the first shield layer SD1 does not exist, the components between the first and second gate electrodes 125c1 and 125c2 of the compensating TFT T3, for example, the part 131c2 of the compensating semiconductor layer, may be affected by the data line <NUM>.

The data line <NUM> transmits a data signal to the (sub) pixel P2 disposed near the (sub) pixel P1 in the +x direction, and also transmits a data signal to a plurality of (sub) pixels disposed near the (sub) pixel P2 in +y and -y directions. Here, a data signal being transmitted may vary according to luminance to be realized in the plurality of (sub) pixels disposed near the (sub) pixel P2 in the +y and -y directions, and accordingly, the data line <NUM> near the part 131c2 of the compensating semiconductor layer of the (sub) pixel P1 may transmit different electric signals according to time while the (sub) pixel P1 emits light.

If the first shield layer SD1 does not exist, parasitic capacitance may occur between the data line <NUM> of the (sub) pixel P2 and the part 131c2 of the compensating TFT T3 of the (sub) pixel P1, and accordingly, the electric potential of the part 131c2 of the compensating TFT T3 of the (sub) pixel P1 may be affected by different electric signals transmitted by the data line <NUM> of the (sub) pixel P2 according to time while the (sub) pixel P1 emits light. Because the compensating TFT T3 is electrically coupled to the driving TFT T1, if the electric potential of the part 131c2 of the compensating TFT T3 of the (sub) pixel P1 is affected by the different electric signals transmitted by the data line <NUM> of the (sub) pixel P2, the luminance of the organic light-emitting device OLED determined by the driving TFT T1 may become different from an initial intension, and thus quality of an image displayed by the organic light-emitting display apparatus may deteriorate.

However, according to the organic light-emitting display apparatus of some embodiments, because the first shield layer SD1 is disposed between the data line <NUM> of the (sub) pixel P2 and the part 131c2 of the compensating TFT T3 of the (sub) pixel P1, the part 131c2 of the compensating TFT T3 of the (sub) pixel P1 may not be affected or may be less affected by the data line <NUM> of the (sub) pixel P2, and thus the organic light-emitting display apparatus may be able to display an image having a more accurate luminance and a relatively higher quality. For example, if the first shield layer SD1 is a part of the second storage capacitor plate <NUM>, the second storage capacitor plate <NUM> is connected to the driving voltage line <NUM> always having uniform electric potential, through the contact hole <NUM>, and thus the first shield layer SD1 may also always have a uniform electric potential. Accordingly, an effect of an adjacent electric signal on the part 131c2 of the compensating TFT T3 may be reduced.

Alternatively, the first shield layer SD1 may extend below the data line <NUM> of the (sub) pixel P2 as shown in <FIG> that is a cross-sectional view of an organic light-emitting display apparatus according to some embodiments of the present invention. Accordingly, the part 131c2 of the compensating TFT T3 may be further shielded. Here, the part 131c2 of the compensating TFT T3 may also be further shielded by extending the first shield layer SD1 above at least a part of the part 131c2 between the first and second gate electrodes 125c1 and 125c2 of the compensating TFT T3.

<FIG> is a cross-sectional view taken along the line IX-IX of <FIG>. As shown in <FIG>, <FIG>, and <FIG>, the initialization voltage line <NUM> may include a third shield layer SD2.

As shown in <FIG> and <FIG>, the third shield layer SD2 may be a part of the initialization voltage line <NUM>, which extends along an x-axis. The third shield layer SD2 may be understood to be a part of the initialization voltage line <NUM>, which extends between the data line <NUM> and at least a part between first gate electrode 125d1 and a second gate electrode 125d2 of the initialization gate electrode 125d1 and 125d2 of the initialization TFT T4.

In <FIG> and <FIG>, the initialization voltage line <NUM> extends above the part between the first and second gate electrodes 125d1 and 125d2 of the initialization TFT T4, but an embodiment is not limited thereto. If the initialization voltage line <NUM> has another location or another shape, for example, is moved in a +y direction, a -y direction, or another direction, or is curved, the initialization voltage line <NUM> may have a protrusion and the protrusion may extend between the data line <NUM> and at least a part between the first and second gate electrodes 125d1 and 125d2 of the initialization TFT T4 to operate as the third shield layer SD2. In other words, in <FIG> and <FIG>, the initialization voltage line <NUM> may extend along an x-axis direction while passing between the data line <NUM> and at least the part between the first and second gate electrodes 125d1 and 125d2 of the initialization TFT T4, such that a location of the initialization voltage line <NUM> is specified without having to include the protrusion.

If the third shield layer SD2 does not exist, the components between the first and second gate electrodes 125d1 and 125d2 of the initialization TFT T4, for example, a part 131d2 of the initialization semiconductor layer 131d1,131d2, and 131d3 may be affected by the data line <NUM>.

The data line <NUM> transmits a data signal to the (sub) pixel of <FIG>, and also transmits a data signal to a plurality of (sub) pixels disposed near the (sub) pixel of <FIG> in +y and -y directions. Here, a data signal being transmitted may vary according to luminance to be realized by the plurality of (sub) pixels disposed near the (sub) pixel of <FIG> in the +y and -y directions, and accordingly, the data line <NUM> near the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 of the (sub) pixel of <FIG> transmits different electric signals according to time while the (sub) pixel of <FIG> emits light.

If the third shield layer SD2 does not exist, parasitic capacitance may occur between the data line <NUM> and the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 of the initialization TFT T4, and thus electric potential of the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 of the initialization TFT T4 may be affected by the different electric signals transmitted by the data line <NUM>, according to time while the (sub) pixel of <FIG> emits light. Because the initialization TFT T4 is electrically coupled to the driving TFT T1, if the electric potential of the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 of the initialization TFT <NUM> is affected by the different electric signals transmitted by the data line <NUM>, the luminance of the organic light-emitting device OLED determined by the driving TFT T1 may become different from an initial intention, and thus quality of an image displayed by the organic light-emitting display apparatus may deteriorate.

However, according to the organic light-emitting display apparatus of some embodiments, because the third shield layer SD2 is arranged between the data line <NUM> and the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 of the initialization TFT T4, the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 of the initialization TFT T4 may not be affected or may be less affected by the data line <NUM>, and thus the organic light-emitting display apparatus may be able to display an image having a more accurate luminance and a relatively higher quality. For example, if the third shield layer SD2 is a part of the initialization voltage line <NUM>, the third shield layer SD2 may always have a uniform electric potential by the initialization voltage line <NUM> that always has uniform electric potential. Accordingly, an effect of an adjacent electric signal on the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 of the initialization TFT T4 may be reduced.

Here, if a layout of various wires or a semiconductor layer differs from that shown in <FIG>, the third shield layer SD2 may be a part extending at least above the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 between the first and second gate electrodes 125d1 and 125d2 of the initialization TFT T4, or a part extending below the data line <NUM>.

<FIG> is a cross-sectional view taken along the line X-X of <FIG>. As shown in <FIG>, <FIG>, and <FIG>, the second storage capacitor plate <NUM> may include a third shield layer SD3.

As shown in <FIG> and <FIG>, the second shield layer SD3 may be a part of the second storage capacitor plate <NUM>. The second shield layer SD3 may be understood to be a part of the second storage capacitor plate <NUM>, which extends between the data line <NUM> and the driving gate electrode 125a of the driving TFT T1. For example, the second storage capacitor plate <NUM> may have a (virtual) end in the -x direction, which approximately match an end of the first storage capacitor plate 125a in the -x direction below the second storage capacitor plate <NUM>, and the third shield layer SD3 may exist between the data line <NUM> and the driving gate electrode 125a of the driving TFT T1 in the -x direction from the (virtual) end, wherein the second shield layer SD3 may be understood to be integrally formed with the second storage capacitor plate <NUM>.

Alternatively, unlike shown in <FIG> and <FIG>, the second storage capacitor plate <NUM> may not extend in the -x direction where the data line <NUM> is located due to nonexistence of the second shield layer SD3, and the end of the second storage capacitor plate <NUM> in the -x direction may approximately match the end of the first storage capacitor plate 125a in the -x direction. In this case, the driving gate electrode 125a of the driving TFT T1 is affected by the data line <NUM>.

The data line <NUM> transmits a data signal to the (sub) pixel of <FIG>, and also transmits a data signal to the plurality of (sub) pixels disposed in the +y and -y directions of the (sub) pixel. Here, the data signal being transmitted may vary according to the luminance to be realized by the plurality of (sub) pixels disposed in the +y and -y directions of the (sub) pixel of <FIG>, and accordingly, the data line <NUM> near the part 131d2 of the initialization semiconductor layer 131d1, 131d2, and 131d3 of the (sub) pixel of <FIG> may transmit different electric signals according to time while the (sub) pixel of <FIG> emits light.

If the second shield layer SD3 does not exist and thus the second storage capacitor plate <NUM> does not extend in the -x direction where the data line <NUM> is disposed and the end of the second storage capacitor plate <NUM> in the -x direction approximately matches the end of the first storage capacitor plate 125a in the -x direction, parasitic capacitance exists between the data line <NUM> and the driving gate electrode 125a of the driving TFT T1, and accordingly, electric potential of the driving gate electrode 125a of the driving TFT T1 is affected by the different electric signals transmitted by the data line <NUM> according to time while the (sub) pixel of <FIG> emits light. As a result, the luminance of the organic light-emitting device OLED determined by the driving TFT T1 may become different from an initial intension, and thus quality of an image displayed by the organic light-emitting display apparatus may deteriorate.

However, according to the organic light-emitting display apparatus of the current embodiment, because the second shield layer SD3 exists between the data line <NUM> and the driving gate electrode 125a of the driving TFT T1, the driving gate electrode 125a of the driving TFT T1 may not be affected or may be less affected by the data line <NUM>, and thus the organic light-emitting display apparatus may be able to display an image having a more accurate luminance and a relatively higher quality. For example, if the second shield layer SD3 is a part of the second storage capacitor plate <NUM>, the second storage capacitor plate <NUM> is coupled to the driving voltage line <NUM> always having uniform electric potential, through the contact hole <NUM>, and thus the second shield layer SD3 may also always have a uniform electric potential. Accordingly, an effect of an adjacent electric signal on the driving gate electrode 125a of the driving TFT T1 may be reduced.

Of course, the second shield layer SD3 may not only be disposed between the data line <NUM> and the driving gate electrode 125a, and may also extend below the data line <NUM> as shown in <FIG>. Accordingly, the driving gate electrode 125a of the driving TFT T1 may be further shielded.

Hereinabove, the organic light-emitting display apparatus may include the first shield layer SD1, the third shield layer SD2, and the second shield layer SD3, but alternatively, the organic light-emitting display apparatus may include only some of the first through third shield layers. In other words, the organic light-emitting display apparatus may include at least any one of the first through third shield layers. According to the invention, it comprises at least the first shield layer SD1 and the second shield layer SD3.

In the above embodiments, the compensating TFT T3 and the initialization TFT T4 include a dual gate electrode.

Meanwhile, all of the first through third shield layers are included in the second gate wire as shown in <FIG> and <FIG>, but an embodiment is not limited thereto. In other words, the first through third shield layers may be a part of the second storage capacitor plate <NUM> or a part of the initialization voltage line <NUM>.

<FIG> is a schematic diagram showing locations of a plurality of TFTs and a capacitor in a (sub) pixel of an organic light-emitting display apparatus, according to another embodiment of the present invention, and <FIG> is a cross-sectional view taken along the line XII-XII of <FIG>. Differences between the organic light-emitting display apparatuses of <FIG> and <FIG> are shapes of the previous scan lines <NUM>, the initialization voltage lines <NUM>, and the initialization TFTs T4.

Referring to <FIG> and <FIG>, the initialization voltage line may be arranged in the same layer as the second storage capacitor plate <NUM>, or in the same layer as a pixel electrode. The initialization voltage line may be coupled to the initialization source electrode 176d of the initialization TFT T4 through the contact hole <NUM>. As described above with reference to <FIG>, the initialization drain electrode 177d of the initialization TFT T4 is electrically coupled to the compensating drain electrode 177c of the compensating TFT T3 and the driving gate electrode 125a of the driving TFT T1.

The previous scan line <NUM> that may be arranged in the same layer as the driving gate electrode 125a, the scan line <NUM>, and the emission control line <NUM> may include two protrusions corresponding to a location of the initialization TFT T4. Here, the two protrusions may be the first and second gate electrodes 125d1 and 125d2 of the initialization TFT T4. At least a part of the second gate electrode 125d2 may be the third shield layer SD2.

A dual gate electrode may have two parts overlapping a semiconductor layer. For example, referring to <FIG>, the second gate electrode 125d2 of the initialization TFT T4 may be a part of the previous scan line <NUM> extending along an x-axis without having to protrude from the previous scan line <NUM>, and a part 125d2' of the first gate electrode 125d1 in the -x direction, which crosses a semiconductor layer near the initialization source electrode 176d, may operate as a second gate electrode. However, in this case, a part between a part of the semiconductor layer corresponding to the part 125d2' and a part of the semiconductor layer corresponding to the first gate electrode 125d1 is arranged adjacent to the data line <NUM> and is not shielded, and thus may be affected by the data line <NUM>.

However, according to the organic light-emitting display apparatus of the some embodiments, the previous scan line <NUM> includes the two protrusions, wherein one of the protrusions operates as the first gate electrode 125d1 and the other one of the protrusions protrudes form the part 125d2' of the previous can line <NUM> and operates as the second gate electrode 125d2. Here, the second gate electrode 125d2 shields the part between the part of the semiconductor layer corresponding to the part 125d2' and the part of the semiconductor layer corresponding to the first gate electrode 125d1 from the data line <NUM>, and thus an unintended effect on the initialization TFT T4 from the data line <NUM> may be effectively blocked or reduced.

According to the initialization TFT T4 having such a structure, the initialization TFT T4 includes the first and second gate electrodes 125d1 and 125d2, and at least any one of the first and second gate electrodes 125d1 and 125d2 is partially disposed between the data line <NUM> and the semiconductor layer 131d2 that is a part between the first and second gate electrodes 125d1 and 125d2 of the initialization TFT T4. In <FIG> and <FIG>, the second gate electrode 125d2 is at least partially disposed between the data line <NUM> and the semiconductor layer 131d2 that is the part between the first and second gate electrodes 125d1 and 125d2 of the initialization TFT T4, and thus the semiconductor layer 131d2 is shielded from the data line <NUM>. In other words, the second gate electrode 125d2 is shown to be the third shield layer SD2. Here, the second gate electrode 125d2 may not only be arranged between the data line <NUM> and the semiconductor layer 131d2 as shown in <FIG> and <FIG>, but may also extend below the data line <NUM> in the -x direction. In <FIG>, the data line <NUM> is arranged above the second gate electrode 125d2, but if the data line <NUM> is arranged below the semiconductor layer 131d2 and the second gate electrode 125d2 is arranged between the data line <NUM> and the semiconductor layer 131d2, the second gate electrode 125d2 may extend above the data line <NUM>.

As such, the third shield layer SD2 may be formed as the second gate wire as described above with reference to <FIG>, <FIG>, and <FIG>, but may alternatively be formed as the first gate wire as described with reference to <FIG> and <FIG>. If the first or second shield layer SD1 or SD3 is included as well as the third shield layer SD2, the first or second shield layer SD1 or SD3 may be formed as the first gate wire. In this case, in an example not falling within the scope of the claims, the first or second shield layer SD1 or SD3 may not be electrically coupled to the second storage capacitor plate <NUM>, but may have an island shape and electrically float.

Hereinabove, it is described that the parts of the driving TFT T1, the compensating TFT T3, and the initialization TFT T4 are shielded from the data line <NUM>, but an embodiment is not limited thereto. In other words, if a TFT of a (sub) pixel of an organic light-emitting display apparatus is near the data line <NUM>, a shield layer may be disposed between the data line <NUM> and at least a part of the TFT such that the organic light-emitting display apparatus displays an image having high quality. The shield layer may be arranged at least one of between the data line <NUM> and a source electrode of the TFT, between the data line <NUM> and a drain electrode of the TFT, and between the data line <NUM> and a gate electrode of the TFT.

Meanwhile, hereinabove, it is described that a shield layer is arranged between a data line and a part of a TFT, but an embodiment is not limited thereto. For example, an organic light-emitting display apparatus may include a TFT that includes a source electrode, a drain electrode, and a gate electrode, a control signal line that is arranged in a layer different from the source electrode, the drain electrode, and the gate electrode and transmits a control signal, and a shield layer that is arranged between the control signal line and at least a part of the TFT. Here, the control signal line may be at least any one of the plurality of signal lines described above. In other words, the control signal line may be the scan line <NUM>, the previous scan line <NUM>, the emission control line <NUM>, the data line <NUM>, the driving voltage line <NUM>, or the initialization voltage line <NUM>. The shield layer may shield the at least the part of the TFT from the control signal line so as to block or reduce an effect of a control signal transmitted from the control signal line on the TFT.

An embodiment of the present is not limited to an organic light-emitting display apparatus. An image having high quality may be displayed as long as a display apparatus including a TFT and a data line in a (sub) pixel has a shield layer in the same or similar manner described above.

As described above, according to one or more embodiments of the present invention, a display apparatus capable of preventing quality deterioration of a displayed image may be realized.

Claim 1:
A display apparatus comprising:
a first thin-film transistor (T3) comprising a gate electrode and a first semiconductor comprising a first source area and a first drain area;
a storage capacitor (Cst) comprising a first storage capacitor plate and a second storage capacitor plate, the second capacitor plate overlapping the first storage capacitor plate and being above the first storage capacitor plate, wherein the first storage capacitor plate is electrically coupled to the first drain area;
a driving thin-film transistor (T1) comprising a driving gate electrode formed as an integral part of the first storage capacitor plate and a driving semiconductor comprising a driving drain area coupled to the first source area and a driving source area;
a data signal line over the second storage capacitor plate;
a first shield layer (SD1) in a layer between the data signal line and the first semiconductor, wherein the gate electrode of the first thin-film transistor (T3) comprises a first gate electrode and a second gate electrode, wherein the second storage capacitor plate comprises the first shield layer (SD1), and the first shield layer (SD1) overlaps a part of the first semiconductor between the first gate electrode and the second gate electrode of the first thin-film transistor; and
a second shield layer (SD3) in a layer between the data signal line and the driving gate electrode, wherein the second shield layer (SD3) is integrally formed with the second storage capacitor plate as a portion of said second storage capacitor plate not overlapping with the first capacitor plate, and the second shield layer (SD3) extends from the edge of the first storage capacitor plate in a direction towards the data signal line.