Patent Description:
Modem processing devices employ disk encryption to protect data at rest. However, data in memory is in plaintext and vulnerable to attacks. Attackers can use a variety of techniques including software and hardware-based bus scanning, memory scanning, hardware probing etc. to retrieve data from memory. This data from memory could include sensitive data for example, privacy-sensitive data, IP-sensitive data, and also keys used for file encryption or communication. The exposure of data is further exacerbated with the current trend of moving data and enterprise workloads into the cloud utilizing virtualization-based hosting services provided by cloud service providers.

<CIT> pertains to the field of security in information processing systems. For example, in order to maintain a secure processing environment across power cycles, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to evict a root version array page entry from a secure cache. The execution unit is to execute the instruction. Execution of the instruction includes generating a blob to contain information to maintain a secure processing environment across a power cycle and storing the blob in a non-volatile memory.

<CIT> relates to security of a public cloud by enabling a consumer of public cloud services to ensure that the consumer's processes executing in the cloud and the consumer's private data are secured from access and modification by others, including the public cloud services provider. For example, a method for ensuring a secure cloud environment is provided, where public cloud services providers can remove their code from the Trusted Computing Base (TCB) of their cloud services consumers. The method for ensuring a secure cloud environment keeps the Virtual Machine Monitor (VMM), devices, firmware and the physical adversary (where a bad administrator/technician attempts to directly access the cloud host hardware) outside of a consumer's Virtual Machine (VM) TCB. Only the consumer that owns this secure VM can modify the VM or access contents of the VM (as determined by the consumer).

The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

Systems and methods for supporting memory paging in virtualized systems using trust domains are provided. A current trend in computing is the placement of data and enterprise workloads (e.g., tasks to be performed by one or more applications) in the cloud by utilizing hosting services provided by cloud service providers (CSPs). As a result of the hosting of the data and enterprise workloads in the cloud, customers (also referred to as tenants herein) of the CSPs are requesting better security and isolation solutions for their workloads. In particular, customers are seeking out solutions that enable the operation of CSP-provided software outside of a Trusted Computing Base (TCB) of the tenant's software. The TCB of a system refers to a set of hardware, firmware, and/or software components that have an ability to influence the trust for the overall operation of the system.

A trust domain (TD) architecture implemented as an instruction set architecture (ISA) extensions (referred to herein as TD extensions (TDX)) provide confidentiality (and integrity) for customer software executing in an untrusted CSP infrastructure. The TD architecture, which can be a System-on-Chip (SoC) capability, provides isolation between workloads (e.g., execution of applications) of the CSP tenants. Components of the TD architecture can include, but not limited to, memory encryption via a MK-Total Memory Encryption (MK-TME) engine, a resource management capability referred to herein as the trust domain resource manager (TDRM) (e.g., a TDRM may be a software extension of the Virtual Machine Monitor (VMM)), and execution state and memory isolation capabilities in the processor provided via a CPU-managed Memory Ownership Table (MOT) and via CPU access-controlled TD control structures. The TD architecture provides an ability of the processor to deploy TDs that leverage the MK-TME engine, the MOT, and the access-controlled TD control structures for secure operation of TD workloads.

Using the TD architecture, the CSP tenant's software can be executed in a trust domain TD. A TD (also referred to as a tenant TD) refers to a cryptographically protected execution environment that support a CSP tenant's workload. For example, the TD can comprise an operating system (OS) along with applications running on top of the OS, or a virtual machine (VM) running on top of a virtual machine manager (VMM) along with other applications. Each TD operates independently of other TDs in the system and uses logical processor(s), memory, and I/O assigned by the TDRM on the platform. For example, the TDRM in the TD architecture acts as a host for the TDs and has full control of the cores and other platform hardware. A TDRM assigns software in a TD with logical processor(s). The TDRM, however, cannot access a TD's execution state on the assigned logical processor(s). Similarly, a TDRM assigns physical memory and I/O resources to the TDs, but is not privy to access the memory state of a TD due to the use of separate encryption keys enforced by the CPUs per TD, and other integrity and replay controls on memory.

Each TD is cryptographically isolated in memory using at least one exclusive (e.g., TD specific) encryption key of the MK-TME engine for encrypting the memory (holding code and/or data) associated with the trust domain. The processor may utilize the MK-TME engine to encrypt (and decrypt) memory used during execution of the TD workloads. With the MK-TME engine, any memory accesses by software executing within the TD on the processor can be encrypted in memory. For example, the MK-TME engine may be used by the TD architecture to implement one or more keys per each TD/tenant (in which each TD is running a tenant's workload) to achieve a cryptographic isolation between different tenant workloads.

The MK-TME engine may enforce that any memory pages of a particular TD should to be encrypted using a TD-specific encryption key. The TD may further choose specific TD memory pages to be plain text or encrypted using a combination of keys (e.g., ephemeral keys that are generated for each execution of the TD) that are unknown to the TDRM, and a binding ("tweak") operation. The binding operation binds the TD memory pages to a particular TD by using a host physical address (HPA) of the page as a parameter to an encryption algorithm (e.g., a type of AES-XTS Encryption Algorithm with <NUM> bit encryption key and <NUM> bit tweak key), which is utilized to encrypt the TD memory page. Thus, if the TD memory page is moved to another location (e.g., in memory or external storage), the page cannot be decrypted correctly even if the TD-specific encryption key is used.

There are, however, several issues that can occur due to the binding of memory pages to specific TDs. For example, memory paging may be used by a host system in a virtualized environment to ensure that the hosted applications (which in this case are implemented as TDs) do not crash due to a lack of memory. With memory paging, the host system software (e.g., VMM/TDRM) may reclaim TD memory pages allocated to a given TD. This may be accomplished by storing contents of the TD memory pages to a disk (e.g., an external hard disk). The freed memory pages can then be allocated to another TD that is in need of extra memory. When the first TD request access to the contents of the reclaimed memory pages, the host system software takes the memory pages from disk and copies them back to any location in memory associated with the first TD. When the first TD tries the decrypt the memory page, it is unable to do so due to a possible new location of the memory pages in memory. This is because the location in which the memory pages are placed back is not fixed. As such, the TD cannot decrypt the memory page correctly if it is in a different physical location in memory. As a result, a tenant application of first TD that uses those TD memory pages may produce unexpected results or even crash, which can adversely affect the service provided by the CSPs to their tenants.

Embodiments of the disclosure address the above-mentioned and other deficiencies by providing transportable pages that can support full memory paging between different TDs in the TD architecture without losing any of its security properties (e.g., tamper resistant/detection and confidentiality on a per TD basis). In one embodiment, the TD architecture may implement instructions that allow the VMM/TDRM to create a transportable page for a target TD memory page bound to a specific TD. This target TD memory page may be associated with memory that is to be freed from the TD. For example, the VMM/TDRM may use the instructions during a memory paging operation to extract or otherwise evict a TD memory page from one TD in order to insert the page into another TD or to move that page to a different physical location in memory.

During a memory paging operation, the VMM/TDRM may use the instructions to first evict the TD memory page from the TD. This eviction unbinds the TD memory page from the TD. To unbind the TD memory page from the TD, the instructions may read the target TD memory page on behalf of the TD. For example, the instruction may instruct the TD to read the target TD memory page which in turn decrypts the page within the TD. The decryption of the TD memory page uses the HPA address of the page and the ephemeral keys of the TD. The VMM/TDRM may issue the instructions for the TD to read a TD memory page in order to extract contents of a TD-assigned volatile memory page from a source memory address to a destination address of the transportable page. This transportable page allows the VMM/TDRM to page out a TD memory page to use for another TD. When the target TD memory page is selected for eviction, the VMM/TDRM then marks the TD memory page (e.g., in a paging table) as unavailable for the TD.

Once the binding of the TD memory page to the TD is removed, the VMM/TDRM can use the instructions to encrypt the extracted content on the transportable page by using the TD-specific encryption key. The transportable page with some metadata is then transported to a different location in memory, or off to a disk or other types of storage devices. For example, the metadata may include integrity value (e.g., cryptographic hash value based on the page contents) that is also stored by the VMM/TDRM in VMM-managed memory. For example, the integrity value can be generated using cryptographic hash algorithm, such as HMAC-SHA256. This integrity value is used to verify that the transportable page has not been tampered with on the storage device. For example, when the transportable page is brought back to be inserted in memory, the VMM/TDRM executes instructions to remove the encryption of the page based on the TD specific encryption key. The instruction then validates the transportable page by comparing the integrity value derived from the transportable page with the integrity value in the VMM-managed memory.

If the integrity value in the VMM-managed memory does not match the integrity value of the transportable page, this indicates that the integrity validation has failed. As a result, the instructions may return an alert notification to the VMM/TDRM of a memory mapping failure associated with the TD. If the integrity value of the transportable page is a match with the integrity value in the VMM-managed memory, this indicates that the transportable page has not been modified. On a successful integrity validation of the transportable page, the VMM/TDRM inserts the page at a specific HPA in memory. The VMM/TDRM then instructs the processor to encrypt the transportable page by using the ephemeral key associated with the TD and the specific HPA location of the page. For example, the VMM/TDRM executes an instruction that passes as a parameter the new location of the transportable page. In some embodiments, this may be a new memory location that is different from where the TD memory page was when it was paged out of TD assigned memory. This encryption binds the transportable page back to the TD at the new memory location. As a result, the binding allows the TD to access the content of the transportable page because the instruction causes the TD to bind the transportable page to TD at the new HPA in memory.

<FIG> is a block diagram of a processing system <NUM> to support memory paging in virtualized systems using trust domains according to one embodiment. In some embodiments, processing system <NUM> includes a virtualization server <NUM> that supports a number of client devices 101A-101C. The virtualization server <NUM> includes at least one processor <NUM> (also referred to as a processing device) that executes a trust domain resource manager (TDRM) <NUM>. In some embodiments, the TDRM <NUM> may be included as part virtual machine monitor (VMM) functionality. A VMM (also referred to as hypervisor) may refer to software, firmware, or hardware to create, run, and manage guest applications, such as a virtual machine (VM). In one embodiment, the TDRM <NUM> may include a VMM that may instantiate one or more trust domains (TDs) 190A-190C (e.g., a software environment to execute a tenant (e.g., customer) workload) accessible by the client devices 101A-101C via a network interface <NUM>. The client devices 101A-101C may include, but is not limited to, a desktop computer, a tablet computer, a laptop computer, a netbook, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device.

In one embodiment, processor <NUM> implements a TD architecture and ISA extensions (TDX) for the TD architecture. The TD architecture provides isolation between TD workloads 190A-190C and from CSP software (e.g., TDRM <NUM> and/or a CSP VMM (e.g., root VMM <NUM>)) executing on the processor <NUM>). Components of the TD architecture can include <NUM>) memory encryption via an MK-TME engine <NUM>, <NUM>) a resource management capability referred to herein as the TDRM <NUM>, and <NUM>) execution state and memory isolation capabilities in the processor <NUM> provided via a MOT <NUM> and via access-controlled TD control structures (i.e., TDCS <NUM> and TDTCS <NUM>). The TDX architecture provides an ability of the processor <NUM> to deploy TDs 190A-190C that leverage the MK-TME engine <NUM>, the MOT <NUM>, and the access-controlled TD control structures (i.e., TDCS <NUM> and TDTCS <NUM>) for secure operation of TDs 190A-190C.

As shown, the processor <NUM> may include several components that include, but not limited to, one or more cores <NUM> (also referred to as processing cores <NUM>), range registers <NUM> and a memory controller <NUM>. The processor <NUM> may be used in a processing system <NUM> that is representative of processing systems based on the PENTIUM III™, PENTIUM <NUM>™, Xeon™, Itanium, XScale™ and/or StrongARM™ microprocessing devices available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessing devices, engineering workstations, set-top boxes and the like) may also be used. In one embodiment, sample system <NUM> executes a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used. Thus, embodiments of the disclosure are not limited to any specific combination of hardware circuitry and software.

In an illustrative example, processing core <NUM> may have a micro-architecture including processor logic and circuits. Processor cores <NUM> with different micro-architectures may share at least a portion of a common instruction set. For example, similar register architectures may be implemented in different ways in different micro-architectures using various techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a register alias table (RAT), a reorder buffer (ROB) and a retirement register file). The processor core(s) <NUM> may execute instructions for the processor <NUM>. The instructions may include, but are not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. The processor cores <NUM> include a cache (not shown) to cache instructions and/or data. The cache includes, but is not limited to, a level one, level two, and a last level cache (LLC), or any other configuration of the cache memory within the processor <NUM>.

Processing system <NUM> also includes a main memory <NUM> and a secondary storage <NUM> to store program binaries and other data. Data in the secondary storage <NUM> may be stored in blocks referred to as pages, and each page may correspond to a set of physical memory addresses. The virtualization server <NUM> may employ the TDRM/VMM <NUM> in which applications run by the core(s) <NUM>, such as the TDs 190A-190C, use virtual memory addresses that are mapped to guest physical memory addresses, and guest physical memory addresses are mapped to host/system physical addresses by the memory controller <NUM>. The core <NUM> may execute the memory controller <NUM> to load pages from the secondary storage <NUM> into the main memory <NUM> (which includes a volatile memory and/or a non-volatile memory) for faster access by software running on the processor <NUM> (e.g., on the core). When one of the TDs 190A-190C attempts to access a virtual memory address that corresponds to a physical memory address of a page loaded into the main memory <NUM>, the memory controller <NUM> returns the requested data. The core <NUM> may execute the VMM portion of TDRM <NUM> to translate guest virtual addresses to host physical addresses of main memory <NUM>, and provide parameters for a protocol that allows the core <NUM> to read, walk and interpret these mappings.

In one implementation, a TD 190A may be created and launched by the TDRM <NUM>. The TDRM <NUM> creates a TD 190A using a certain TD instruction. The TDRM <NUM> selects a 4KB aligned region of physical memory and provides this as a parameter to the TD create instruction. This region of memory is used as a TDCS <NUM> for the TD 190A. When executed, the TD instruction causes the processor <NUM> to verify that the destination 4KB page is assigned to the TD (using the MOT <NUM>). The TD instruction further causes the processor <NUM> to generate an ephemeral memory encryption key and key ID for the TD 190A, and store the key ID in the TDCS <NUM>. As the TDRM <NUM> assigns physical memory for each TD 190A and190B, the TD architecture includes a MOT <NUM>. The processor <NUM> consults the TDRM-managed MOT <NUM> to assign allocation of memory to TDs. This allows the TDRM <NUM> the full ability to manage memory as a resource without having any visibility into data resident in assigned TD memory.

MOT <NUM> (which may be referred to as TD-MOT) is a structure, such as a table, managed by the processor <NUM> to enforce assignment of physical memory pages to executing TDs, such as TD 190A. The MOT <NUM> structure is used to hold meta-data attributes for each 4KB page of memory aligned with the TD 190A.

In one implementation, the MOT <NUM> is aligned on a 4KB boundary of memory and occupies a physically contiguous region of memory protected from access by software after platform initialization. In an implementation, the MOT <NUM> is a micro-architectural structure and cannot be directly accessed by software. Architecturally, the MOT <NUM> holds the following security attributes for each 4KB page of host physical memory:.

The meta-data for each 4KB page of memory is directly indexed by a physical page address associated with the TD. A 4KB page referenced in the MOT <NUM> can belong to one running instance of a TD 190A. The processor <NUM> uses the MOT <NUM> to enforce that the physical addresses referenced by software operating as a tenant TD 190A or the TDRM <NUM> cannot access memory not explicitly assigned to it. For example, the access control is enforced using the MOT <NUM> during the page walk for memory accesses made by software. Physical memory accesses performed by the processor <NUM> to memory that is not assigned to a tenant TD 190A or TDRM <NUM> fail with Abort page semantics. In some embodiments, the MOT <NUM> enforces the following properties. First, software outside a TD 190A should not be able to access (read/write/execute) in plain-text any memory belonging to a different TD (this includes TDRM <NUM>). Second, memory pages assigned via the MOT <NUM> to specific TDs, such as TD 190A, should be accessible from any processor in the system (where the processor is executing the TD that the memory is assigned to).

In embodiments of the disclosure, the TDRM <NUM> acts as a host and has full control of the cores <NUM> and other platform hardware. A TDRM <NUM> assigns software in a TD 190A-190C with logical processor(s). The TDRM <NUM>, however, cannot access a TD's 190A-190C execution state on the assigned logical processor(s). Similarly, a TDRM <NUM> assigns physical memory and I/O resources to the TDs 190A-190C, but is not privy to access the memory state of a TD 190A due to separate encryption keys, and other integrity and replay controls on memory.

With respect to the separate encryption keys, the processor <NUM> may utilize the MK-TME engine <NUM> to encrypt (and decrypt) memory used during execution. With total memory encryption (TME), any memory accesses by software executing on the core <NUM> can be encrypted in memory with an encryption key. MK-TME is an enhancement to TME that allows use of multiple encryption keys (the number of supported keys is implementation dependent). The processor <NUM> may utilize the MK-TME engine <NUM> to cause different pages to be encrypted using different MK-TME keys. The MK-TME engine <NUM> may be utilized in the TD architecture described herein to support one or more encryption keys per each TD 190A-190C to help achieve the cryptographic isolation between different CSP customer workloads. For example, when MK-TME engine <NUM> is used in the TD architecture, the CPU enforces by default that TD (all pages) are to be encrypted using a TD-specific encryption key.

Each TD 190A-190C may further choose specific TD memory pages to be plain text or encrypted. For example, the TD memory pages may be encrypted using a combination of keys (e.g., ephemeral keys that are generated for each execution of the TD) that are unknown to the TDRM <NUM>, and a binding ("tweak") operation. The binding operation binds the TD memory pages to a particular TD by using a host physical address (HPA) of the page as a parameter to an encryption algorithm which is utilized to encrypt the TD memory page. So if the TD memory page is moved to another location (e.g., in main memory <NUM> or secondary storage <NUM>), the page cannot be decrypted correctly even if the TD-specific encryption key is used.

The TDRM <NUM> on occasion may need to perform a memory paging operations to reclaim memory pages allocated to a first TD by storing contents of the pages to a disk (e.g., an external hard disk). The freed memory page can then be allocated to a second TD that is in need of extra memory. Embodiments of the disclosure provide techniques to support full memory paging between different TDs in compute system <NUM> without losing any of its security properties (e.g., tamper resistant/detection and confidentiality on a per TD basis). In one embodiment, processor <NUM> may implement a memory paging circuit <NUM>. The memory paging circuit <NUM> allows the TDRM <NUM> to create a transportable page for a target TD memory page bound to a specific TD. This transportable page allows the TDRM <NUM> to page out the target TD memory page to use for another TD or a different location in memory.

In some implementations, the memory paging circuit <NUM> may be implemented as part of the TDRM <NUM>. In alternative implementations, the memory paging circuit <NUM> may be implemented in a separate hardware component, circuitry, dedicated logic, programmable logic, and microcode of the processor <NUM> or any combination thereof. In one implementation, the memory paging circuit <NUM> may include a micro-architecture including processor logic and circuits similar to the processing cores <NUM>. In some implementations, the memory paging circuit <NUM> may include a dedicated portion of the same processor logic and circuits used by the processing cores <NUM>.

<FIG> illustrates a block diagram of an apparatus <NUM> including a data structure <NUM> according to one embodiment. In this example, apparatus <NUM> may be the same or similar to processing device <NUM>. For example, apparatus <NUM> includes the memory paging circuit <NUM> of the TDRM <NUM> of <FIG>, which implements processor instructions to support memory paging in virtualized systems using trust domains, such as TDs 190A and 190B. Each TD 190A and 190B is a software environment that can run VMMs, VMs, OSes, and/or applications. For example, TD 190A is depicted as hosting VM 290A. The apparatus <NUM> provides isolation between workloads executed by each of the TDs 190A and 190B.

In some embodiments, each TD is cryptographically isolated in memory using at least one exclusive encryption key of the MK-TME engine <NUM> for encrypting the memory (holding code and/or data) associated with the trust domain. For example, TD 190A may use encryption key 205A to encrypt TD memory page <NUM> of that TD, and TD 190B may use encryption key 205B to encrypt TD memory pages of TD 190D. Each TD may further choose specific TD memory pages to be plain text or encrypted using a combination of keys that are unknown to the TDRM <NUM> and a binding operation. For example, the binding operation binds the TD memory page <NUM> to TD 190A by using a host physical address (HPA) <NUM> of the page as a parameter to an encryption algorithm which is utilized to encrypt the TD memory page <NUM>.

In some embodiments, the TDRM <NUM> may use the memory paging circuit <NUM> to page out a TD memory page <NUM> of TD 190A in order to provide memory to a different TD 190B. The TDRM <NUM> in accordance with the memory paging circuit <NUM> may execute an TD evict instruction <NUM> to evict the TD memory page <NUM> from the TD 190A. In some embodiments, the TD evict instruction <NUM> may only apply to certain memory pages of the TD 190A. For example, these memory pages may include pages with a GKID (e.g., Guest (TD) KeyID)=<NUM> or DRAM pages, since the HKID (e.g., Host KeyID) is known to the TDRM <NUM>. In some embodiments, the GKID are pages that are encrypted with TD's ephemeral key in which TDRM has the associated HKID and thus the encryption key pointer. When the TD evict instruction <NUM> is executed, the TDRM <NUM> marks in a paging table (not shown) that the TD memory page <NUM> is not available for TD 190A. For example, when the target TD memory page <NUM> is selected for eviction, the TDRM <NUM> marks the TD memory page <NUM> (e.g., in a paging table) as unavailable for the TD 190A. The TDRM <NUM> then flushes the page mappings of that page to the TD 190A, and any dirty cache lines for the page.

When TD evict instruction <NUM> is executed by the TDRM <NUM>, a data structure <NUM> also referred to as a transportable page is created. The transportable page <NUM> allows the TDRM <NUM> to page out a TD memory page <NUM> in TD <NUM> for use for in TD 190B without losing any of the page's security properties. In some embodiments, the transportable page <NUM> may include encrypted content that has been extracted from the TD memory page <NUM>. Once transportable page <NUM> is populated, the TDRM <NUM> copies the transportable page <NUM> to a secondary storage (e.g., file/disk). The TDRM <NUM> then invalidates cache lines for the old TD memory page <NUM> and makes the page available to a memory location associated with TD 190B. In some embodiments, rather than making the page immediately available, the TDRM <NUM> may store TD memory page <NUM> in a different location in memory <NUM>. In such a case, the TDRM <NUM> may insert a TD memory page for a previously stored transportable page at the TD 190B.

To extract contents of the TD memory page <NUM> to the transportable page <NUM>, the TDRM <NUM> in accordance with the memory paging circuit <NUM> may execute a TD extract instruction <NUM>. The TD extract instruction <NUM> first removes the binding that binds the TD memory page <NUM> a specific (HPA) memory location <NUM> associated with TD 190A. To unbind the TD memory page <NUM> from the TD 190A, the TD extract instruction <NUM> may read the TD memory page <NUM> on behalf of the TD 190A. For example, the instruction may instruct the TD 190A to read the target TD memory page <NUM>. This in turn decrypts the page within the TD by using the HPA address <NUM> of the page and the ephemeral keys of the TD 190A. In some embodiments, when a TD memory page <NUM> is read in accordance with TD extract instruction <NUM>, the contents of a TD-assigned volatile memory page are extracted from a source memory address of the page to a destination address of the transportable page <NUM>.

Once the binding of the TD memory page <NUM> to the TD 190A is removed, the TDRM <NUM> can use the TD extract instruction <NUM> to encrypt the transportable page <NUM> using the TD-specific encryption key 207A. In one embodiment, the encrypted the transportable page <NUM> may include, but not limited to, a TDCS slot identifier <NUM>, a HPA of the source TD memory page <NUM>, a virtual address (VA) of a region (e.g., <NUM> byte) of memory where a cryptographic MAS is captured for the page content and meta-data, and a VA of a (4KB) page where the encrypted contents of the transportable page <NUM> are stored.

The TDRM <NUM> may then instruct the apparatus <NUM> to transport the transportable page <NUM> to a different location in memory <NUM> or off to a storage device.

In some embodiments, the transportable page <NUM> may be saved with metadata that may include integrity value <NUM> for the page. For example, the integrity value <NUM> may be a cryptographic hash value that is generated based on the contents of the page and the TD-specific encryption key 207A. For example, the integrity value <NUM> can be generated using cryptographic hash algorithm, such as HMAC-SHA256, as the basis for data origin authentication and integrity verification. This integrity value <NUM> is used to verify that the transportable page <NUM> has not been tampered with on the storage device. For example, when the transportable page <NUM> is brought back to be inserted in memory <NUM>, the TDRM <NUM> may check whether the integrity value <NUM> has changed in order to validate the contents of the transportable page <NUM>.

<FIG> illustrates is another example <NUM> of the apparatus <NUM> of <FIG> according to one embodiment. In this example <NUM>, the TDRM <NUM> may insert contents of the memory page that was paged out of TD 190A. For example, when an application (e.g., VM 290A) of TD 190A request access to the contents of the reclaimed memory pages, the TDRM <NUM> takes the memory pages from disk and provides then back to any location in memory <NUM> associated with the TD 190A. When the transportable page <NUM> is brought back to be inserted in memory, the TDRM <NUM> executes a TD insert page instruction <NUM>.

The TD insert page instruction <NUM> first removes the encryption of the transportable page <NUM>. For example, the encrypted contents of transportable page <NUM> are decrypted based on the TD specific encryption key 205A. In one embodiment, the instruction performs an integrity validation operation on the decrypted contents of the transportable page <NUM> to ensure that the page has not been changed. To validate the transportable page <NUM>, the instruction compares the integrity value <NUM> of the transportable page <NUM> to the integrity value <NUM> stored in memory of the TDRM <NUM>. If the integrity validation <NUM> fails because the integrity values <NUM> and <NUM> do not match, the instruction may return an error notification to the TDRM <NUM> of a memory mapping failure associated with the TD 190A. If the integrity values <NUM> and <NUM> match, this indicates that the transportable page <NUM> has not been modified.

On a successful integrity validation of the transportable page <NUM>, the TDRM <NUM> then inserts the transportable page <NUM> at a HPA of a memory page <NUM> in memory <NUM>. The TD insert page instruction <NUM> then instructs the TD 190A to bind the memory page <NUM> to TD 190A by using the ephemeral key associated with the TD 190A and specific HPA location <NUM>. For example, the specific HPA <NUM> may be passed to the TD 190A via the TD insert page instruction <NUM>. In some embodiments, the binding operation binds the memory page <NUM> back to TD 190A by using the HPA <NUM> as a parameter to an encryption algorithm which is utilized to encrypt the page <NUM>. This binding allows the TD 190A to now correctly decrypt the content of the memory page <NUM>, even though the page <NUM> may be at a different physical location from where it was paged out of the TD 190A assigned memory <NUM>. As a result, the TD 190A may now correctly decrypt the contents of the TD memory page <NUM> because the encryption binds the page back to the TD 190A at the new memory location associated with the HPA <NUM>.

<FIG> illustrates a flow diagram of a method <NUM> for supporting memory paging in virtualized systems using trust domains according to one embodiment. Method <NUM> may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as instructions run on a processing device), firmware, or a combination thereof. In one embodiment, the memory paging circuit <NUM> of processing device <NUM> in <FIG> may perform method <NUM>. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated implementations should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every implementation. Other process flows are possible.

Method <NUM> begins at block <NUM> where a memory page <NUM> associated with a trust domain (TD) 190A executed by a processing device <NUM> is evicted. In block <NUM>, a binding 205A of the memory page <NUM> to a first memory location <NUM> of the TD is removed. In block <NUM>, a transportable page <NUM> that comprises encrypted contents <NUM> of the memory page <NUM> is created. Thereupon, the memory page <NUM> is provided to a second memory location 190B.

<FIG> is a block diagram illustrating a micro-architecture for a processor <NUM> that implements techniques for supporting memory paging in virtualized systems using trust domains functionality in accordance with one embodiment of the disclosure. Specifically, processor <NUM> depicts an in-order architecture core and a register renaming logic, out-of-order issue/execution logic to be included in a processor according to at least one embodiment of the disclosure.

Processor <NUM> includes a front-end unit <NUM> coupled to an execution engine unit <NUM>, and both are coupled to a memory unit <NUM>. The processor <NUM> may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, processor <NUM> may include a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like. In one embodiment, processor <NUM> may be a multi-core processor or may part of a multi-processor system.

The decode unit <NUM> (also known as a decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decoder <NUM> may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The instruction cache unit <NUM> is further coupled to the memory unit <NUM>.

The execution engine unit <NUM> includes the rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations (RS), central instruction window, etc. The scheduler unit(s) <NUM> is coupled to the physical register file(s) unit(s) <NUM>. Each of the physical register file(s) units <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s), using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The execution engine unit <NUM> may include for example a power management unit (PMU) <NUM> that governs power functions of the functional units.

Generally, the architectural registers are visible from the outside of the processor or from a programmer's perspective. The registers are not limited to any known particular type of circuit. Various different types of registers are suitable as long as they are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access units <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).

While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units <NUM> is coupled to the memory unit <NUM>, which may include a data prefetcher <NUM>, a data TLB unit <NUM>, a data cache unit (DCU) <NUM>, and a level <NUM> (L2) cache unit <NUM>, to name a few examples. In some embodiments DCU <NUM> is also known as a first level data cache (L1 cache). The DCU <NUM> may handle multiple outstanding cache misses and continue to service incoming stores and loads. It also supports maintaining cache coherency. The data TLB unit <NUM> is a cache used to improve virtual address translation speed by mapping virtual and physical address spaces. The L2 cache unit <NUM> may be coupled to one or more other levels of cache and eventually to a main memory.

In one embodiment, the data prefetcher <NUM> speculatively loads/prefetches data to the DCU <NUM> by automatically predicting which data a program is about to consume. Prefeteching may refer to transferring data stored in one memory location of a memory hierarchy (e.g., lower level caches or memory) to a higher-level memory location that is closer (e.g., yields lower access latency) to the processor before the data is actually demanded by the processor. More specifically, prefetching may refer to the early retrieval of data from one of the lower level caches/memory to a data cache and/or prefetch buffer before the processor issues a demand for the specific data being returned.

In one implementation, processor <NUM> may be the same as processing device <NUM> described with respect to <FIG> to implement techniques for supporting memory paging in virtualized systems using trust domains with respect to implementations of the disclosure.

The processor <NUM> may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA).

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in the in-order architecture. While the illustrated embodiment of the processor also includes a separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level <NUM> (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

<FIG> is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented by processor <NUM> of <FIG> according to some embodiments of the disclosure. The solid lined boxes in <FIG> illustrate an in-order pipeline, while the dashed lined boxes illustrate a register renaming, out-of-order issue/execution pipeline. In some embodiments, the ordering of stages <NUM>-<NUM> may be different than illustrated and are not limited to the specific ordering shown in <FIG>.

<FIG> illustrates a block diagram of the micro-architecture for a processor <NUM> that includes logic circuits to implement techniques for supporting data compression using match-scoring functionality in accordance with one embodiment of the disclosure. In some embodiments, an instruction in accordance with one embodiment can be implemented to operate on data elements having sizes of byte, word, double word, quad word, etc., as well as data types, such as single and double precision integer and floating point datatypes. In one embodiment the in-order front end <NUM> is the part of the processor <NUM> that fetches instructions to be executed and prepares them to be used later in the processor pipeline.

The front end <NUM> may include several units. In one embodiment, the instruction prefetcher <NUM> fetches instructions from memory and feeds them to an instruction decoder <NUM>, which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called "micro-instructions" or "micro-operations" (also called micro op or uops) that the machine can execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, the trace cache <NUM> takes decoded uops and assembles them into program ordered sequences or traces in the uop queue <NUM> for execution. When the trace cache <NUM> encounters a complex instruction, the microcode ROM <NUM> provides the uops needed to complete the operation.

Some instructions are converted into a single micro-op, whereas others need several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, the decoder <NUM> accesses the microcode ROM <NUM> to do the instruction. For one embodiment, an instruction can be decoded into a small number of micro ops for processing at the instruction decoder <NUM>. In another embodiment, an instruction can be stored within the microcode ROM <NUM> should a number of micro-ops be needed to accomplish the operation. The trace cache <NUM> refers to an entry point programmable logic array (PLA) to determine a correct microinstruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from the micro-code ROM <NUM>. After the microcode ROM <NUM> finishes sequencing micro-ops for an instruction, the front end <NUM> of the machine resumes fetching micro-ops from the trace cache <NUM>.

The out-of-order execution engine <NUM> is where the instructions are prepared for execution. The out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler <NUM>, slow/general floating point scheduler <NUM>, and simple floating point scheduler <NUM>. The uop schedulers <NUM>, <NUM>, <NUM>, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation. The fast scheduler <NUM> of one embodiment can schedule on each half of the main clock cycle while the other schedulers can only schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

Register files <NUM>, <NUM> sit between the schedulers <NUM>, <NUM>, <NUM>, and the execution units <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> in the execution block <NUM>. There is a separate register file <NUM>, <NUM>, for integer and floating-point operations, respectively. Each register file <NUM>, <NUM>, of one embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops. The integer register file <NUM> and the floating-point register file <NUM> are also capable of communicating data with the other. For one embodiment, the integer register file <NUM> is split into two separate register files, one register file for the low order <NUM> bits of data and a second register file for the high order <NUM> bits of data. The floating-point register file <NUM> of one embodiment has <NUM> bit wide entries because floating-point instructions typically have operands from <NUM> to <NUM> bits in width.

The execution block <NUM> contains the execution units <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, where the instructions are actually executed. This section includes the register files <NUM>, <NUM>, that store the integer and floating point data operand values that the microinstructions need to execute. The processor <NUM> of one embodiment is comprised of a number of execution units: address generation unit (AGU) <NUM>, AGU <NUM>, fast ALU <NUM>, fast ALU <NUM>, slow ALU <NUM>, floating point ALU <NUM>, floating point move unit <NUM>. For one embodiment, the floating-point execution blocks <NUM>, <NUM>, execute floating point, MMX, SIMD, and SSE, or other operations. The floating point ALU <NUM> of one embodiment includes a <NUM> bit by <NUM> bit floating point divider to execute divide, square root, and remainder micro-ops. For embodiments of the disclosure, instructions involving a floating-point value may be handled with the floating-point hardware.

In one embodiment, the ALU operations go to the high-speed ALU execution units <NUM>, <NUM>. The fast ALUs <NUM>, <NUM>, of one embodiment can execute fast operations with an effective latency of half a clock cycle. For one embodiment, most complex integer operations go to the slow ALU <NUM> as the slow ALU <NUM> includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. The AGUs <NUM>, <NUM>, executes memory load/store operations. For one embodiment, the integer ALUs <NUM>, <NUM>, <NUM>, are described in the context of performing integer operations on <NUM> bit data operands. In alternative embodiments, the ALUs <NUM>, <NUM>, <NUM>, can be implemented to support a variety of data bits including <NUM>, <NUM>, <NUM>, <NUM>, etc. Similarly, the floating-point units <NUM>, <NUM>, can be implemented to support a range of operands having bits of various widths. For one embodiment, the floating-point units <NUM>, <NUM>, can operate on <NUM> bits wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, the uops schedulers <NUM>, <NUM>, <NUM>, dispatch dependent operations before the parent load has finished executing. As uops are speculatively scheduled and executed in processor <NUM>, the processor <NUM> also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations need to be replayed and the independent ones are allowed to complete. The schedulers and replay mechanism of one embodiment of a processor are also designed to catch instruction sequences for text string comparison operations.

The processor <NUM> also includes logic to implement memory paging in virtualized systems using trust domains according to embodiments of the disclosure. In one embodiment, the execution block <NUM> of processor <NUM> may include memory paging circuit <NUM> of <FIG>, for implementing techniques for supporting memory paging in virtualized systems using trust domains functionality. In some embodiments, processor <NUM> may be the processing device <NUM> of <FIG>.

The term "registers" may refer to the on-board processor storage locations that are used as part of instructions to identify operands. In other words, registers may be those that are usable from the outside of the processor (from a programmer's perspective). However, the registers of an embodiment should not be limited in meaning to a particular type of circuit. Rather, a register of an embodiment is capable of storing and providing data, and performing the functions described herein. The registers described herein can be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store <NUM> bit integer data. A register file of one embodiment also may contain an eight multimedia SIMD register for packed data.

For the discussions below, the registers are understood to be data registers designed to hold packed data, such as <NUM> bits wide MMX™ registers (also referred to as 'mm' registers in some instances) in microprocessors enabled with MMX™ technology from Intel Corporation of Santa Clara, California. These MMX™ registers, available in both integer and floating point forms, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, <NUM> bits wide XMM™ registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as "SSEx") technology can also be used to hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not need to differentiate between the two data types. In one embodiment, integer and floating point are either contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

Embodiments may be implemented in many different system types. Referring now to <FIG>, shown is a block diagram illustrating a system <NUM> in which an embodiment of the disclosure may be used. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. While shown with only two processors <NUM>, <NUM>, it is to be understood that the scope of embodiments of the disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor. In one embodiment, the multiprocessor system <NUM> may implement techniques for supporting memory paging in virtualized systems using trust domains functionality as described herein.

Processors <NUM> and <NUM> are shown including integrated memory controller units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may also exchange information with a high-performance graphics circuit <NUM> via a high-performance graphics interface <NUM>.

In one embodiment, first bus <NUM> may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the disclosure is not so limited.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to second bus <NUM>. Note that other architectures are possible. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in which one embodiment of the disclosure may operate. The system <NUM> may include one or more processors <NUM>, <NUM>, which are coupled to graphics memory controller hub (GMCH) <NUM>. The optional nature of additional processors <NUM> is denoted in <FIG> with broken lines. In one embodiment, processors <NUM>, <NUM> implement techniques for supporting memory paging in virtualized systems using trust domains functionality according to embodiments of the disclosure.

Each processor <NUM>, <NUM> may be some version of the circuit, integrated circuit, processor, and/or silicon integrated circuit as described above. However, it should be noted that it is unlikely that integrated graphics logic and integrated memory control units would exist in the processors <NUM>, <NUM>. <FIG> illustrates that the GMCH <NUM> may be coupled to a memory <NUM> that may be, for example, a dynamic random access memory (DRAM). The DRAM may, for at least one embodiment, be associated with a non-volatile cache.

The GMCH <NUM> may be a chipset, or a portion of a chipset. The GMCH <NUM> may communicate with the processor(s) <NUM>, <NUM> and control interaction between the processor(s) <NUM>, <NUM> and memory <NUM>. The GMCH <NUM> may also act as an accelerated bus interface between the processor(s) <NUM>, <NUM> and other elements of the system <NUM>. For at least one embodiment, the GMCH <NUM> communicates with the processor(s) <NUM>, <NUM> via a multi-drop bus, such as a frontside bus (FSB) <NUM>.

Furthermore, GMCH <NUM> is coupled to a display <NUM> (such as a flat panel or touchscreen display). GMCH <NUM> may include an integrated graphics accelerator. GMCH <NUM> is further coupled to an input/output (I/O) controller hub (ICH) <NUM>, which may be used to couple various peripheral devices to system <NUM>. Shown for example in the embodiment of <FIG> is an external graphics device <NUM>, which may be a discrete graphics device, coupled to ICH <NUM>, along with another peripheral device <NUM>.

Alternatively, additional or different processors may also be present in the system <NUM>. For example, additional processor(s) <NUM> may include additional processors(s) that are the same as processor <NUM>, additional processor(s) that are heterogeneous or asymmetric to processor <NUM>, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor. There can be a variety of differences between the processor(s) <NUM>, <NUM> in terms of a spectrum of metrics of merit including architectural, micro-architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processors <NUM>, <NUM>. For at least one embodiment, the various processors <NUM>, <NUM> may reside in the same die package.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in which an embodiment of the disclosure may operate. <FIG> illustrates processors <NUM>, <NUM>. In one embodiment, processors <NUM>, <NUM> may techniques for supporting memory paging in virtualized systems using trust domains functionality as described above. Processors <NUM>, <NUM> may include integrated memory and I/O control logic ("CL") <NUM> and <NUM>, respectively and intercommunicate with each other via point-to-point interconnect <NUM> between point-to-point (P-P) interfaces <NUM> and <NUM> respectively. Processors <NUM>, <NUM> each communicate with chipset <NUM> via point-to-point interconnects <NUM> and <NUM> through the respective P-P interfaces <NUM> to <NUM> and <NUM> to <NUM> as shown. For at least one embodiment, the CL <NUM>, <NUM> may include integrated memory controller units. CLs <NUM>, <NUM> may include I/O control logic. As depicted, memories <NUM>, <NUM> coupled to CLs <NUM>, <NUM> and I/O devices <NUM> are also coupled to the control logic <NUM>, <NUM>. Legacy I/O devices <NUM> are coupled to the chipset <NUM> via interface <NUM>.

Embodiments may be implemented in many different system types. <FIG> is a block diagram of a SoC <NUM> in accordance with an embodiment of the disclosure. Dashed lined boxes are optional features on more advanced SoCs. In <FIG>, an interconnect unit(s) <NUM> is coupled to: an application processor <NUM> which includes a set of one or more cores 1002A-N and shared cache unit(s) <NUM>; a system agent unit <NUM>; a bus controller unit(s) <NUM>; an integrated memory controller unit(s) <NUM>; a set of one or more media processors <NUM> which may include integrated graphics logic <NUM>, an image processor <NUM> for providing still and/or video camera functionality, an audio processor <NUM> for providing hardware audio acceleration, and a video processor <NUM> for providing video encode/decode acceleration; an static random access memory (SRAM) unit <NUM>; a direct memory access (DMA) unit <NUM>; and a display unit <NUM> for coupling to one or more external displays. In one embodiment, a memory module may be included in the integrated memory controller unit(s) <NUM>. In another embodiment, the memory module may be included in one or more other components of the SoC <NUM> that may be used to access and/or control a memory. The application processor <NUM> may include a PMU for implementing the memory paging circuit <NUM> as described in embodiments herein. In some embodiments, application processor <NUM> may be the processing device <NUM> of <FIG>.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units <NUM>, and external memory (not shown) coupled to the set of integrated memory controller units <NUM>. The set of shared cache units <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

In some embodiments, one or more of the cores 1002A-N are capable of multithreading. The system agent <NUM> includes those components coordinating and operating cores 1002A-N. The system agent unit <NUM> may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 1002A-N and the integrated graphics logic <NUM>. The display unit is for driving one or more externally connected displays.

The cores 1002A-N may be homogeneous or heterogeneous in terms of architecture and/or instruction set. For example, some of the cores 1002A-N may be in order while others are out-of-order. As another example, two or more of the cores 1002A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

The application processor <NUM> may be a general-purpose processor, such as a Core™ i3, i5, i7, <NUM> Duo and Quad, Xeon™, Itanium™, Atom™ or Quark™ processor, which are available from Intel™ Corporation, of Santa Clara, Calif. Alternatively, the application processor <NUM> may be from another company, such as ARM Holdings™, Ltd, MIPS™, etc. The application processor <NUM> may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The application processor <NUM> may be implemented on one or more chips. The application processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

<FIG> is a block diagram of an embodiment of a system on-chip (SoC) design in accordance with the disclosure. As a specific illustrative example, SoC <NUM> is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.

Here, SOC <NUM> includes <NUM> cores-<NUM> and <NUM>. Cores <NUM> and <NUM> may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores <NUM> and <NUM> are coupled to cache control <NUM> that is associated with bus interface unit <NUM> and L2 cache <NUM> to communicate with other parts of system <NUM>. Interconnect <NUM> includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described disclosure. In one embodiment, cores <NUM>, <NUM> may implement techniques for supporting memory paging in virtualized systems using trust domains functionality as described in embodiments herein.

Interconnect <NUM> provides communication channels to the other components, such as a Subscriber Identity Module (SIM) <NUM> to interface with a SIM card, a boot ROM <NUM> to hold boot code for execution by cores <NUM> and <NUM> to initialize and boot SoC <NUM>, a SDRAM controller <NUM> to interface with external memory (e.g. DRAM <NUM>), a flash controller <NUM> to interface with non-volatile memory (e.g. Flash <NUM>), a peripheral control <NUM> (e.g. Serial Peripheral Interface) to interface with peripherals, video codecs <NUM> and Video interface <NUM> to display and receive input (e.g. touch enabled input), GPU <NUM> to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the disclosure described herein. In addition, the system <NUM> illustrates peripherals for communication, such as a Bluetooth module <NUM>, <NUM> modem <NUM>, GPS <NUM>, and Wi-Fi <NUM>.

<FIG> illustrates a diagrammatic representation of a machine in the example form of a computer system <NUM> within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The computer system <NUM> includes a processing device <NUM>, a main memory <NUM> (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory <NUM> (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device <NUM>, which communicate with each other via a bus <NUM>.

Processing device <NUM> represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device <NUM> may also be one or more special-purpose processing devices such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. In one embodiment, processing device <NUM> may include one or more processing cores. The processing device <NUM> is configured to execute the processing logic <NUM> for performing the operations and steps discussed herein. In one embodiment, processing device <NUM> is the same as processor architecture <NUM> described with respect to <FIG> that implements techniques for supporting memory paging in virtualized systems using trust domains functionality as described herein with embodiments of the disclosure.

The computer system <NUM> may further include a network interface device <NUM> communicably coupled to a network <NUM>. The computer system <NUM> also may include a video display unit <NUM> (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device <NUM> (e.g., a keyboard), a cursor control device <NUM> (e.g., a mouse), and a signal generation device <NUM> (e.g., a speaker). Furthermore, computer system <NUM> may include a graphics processing unit <NUM>, a video processing unit <NUM>, and an audio processing unit <NUM>.

The data storage device <NUM> may include a non-transitory machine-accessible storage medium <NUM> on which is stored software <NUM> implementing any one or more of the methodologies of functions described herein, such as implementing memory paging in virtualized systems using trust domains on threads in a processing device, such as processing device <NUM> of <FIG>, as described above. The software <NUM> may also reside, completely or at least partially, within the main memory <NUM> as instructions <NUM> and/or within the processing device <NUM> as processing logic <NUM> during execution thereof by the computer system <NUM>; the main memory <NUM> and the processing device <NUM> also constituting machine-accessible storage media.

The non-transitory machine-readable storage medium <NUM> may also be used to store instructions <NUM> implementing the memory paging circuit <NUM> on threads in a processing device such as described with respect to processing device <NUM> in <FIG>, and/or a software library containing methods that call the above applications. While the non-transitory machine-accessible storage medium <NUM> is shown in an example embodiment to be a single medium, the term "machine-accessible storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-accessible storage medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instruction for execution by the machine and that cause the machine to perform any one or more of the methodologies of the disclosure. The term "machine-accessible storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

While the disclosure has been described respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations there from. It is intended that the appended claims cover all such modifications and variations as fall within the scope of this disclosure.

A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the disclosure.

A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

Use of the phrase 'configured to,' in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still 'configured to' perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a <NUM> or a <NUM> during operation. But a logic gate 'configured to' provide an enable signal to a clock does not include every logic gate that may provide a <NUM> or <NUM>. Instead, the logic gate is one coupled in some manner that during operation the <NUM> or <NUM> output is to enable the clock. Note once again that use of the term 'configured to' does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.

Furthermore, use of the phrases 'to,' 'capable of/to,' and/or 'operable to,' in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.

A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as <NUM>'s and <NUM>'s, which simply represents binary logic states. For example, a <NUM> refers to a high logic level and <NUM> refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of <NUM> and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.

Moreover, values or portions of values may represent states. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.

The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.

Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magnetooptical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure.

Claim 1:
A processing device (<NUM>) comprising:
a memory controller (<NUM>); and
a memory paging circuit (<NUM>), operatively coupled to the memory controller (<NUM>), to:
insert a transportable page (<NUM>) into a memory location associated with a trust domain, TD, (190A) executed by the processing device (<NUM>), wherein the transportable page (<NUM>) comprises encrypted contents of a first memory page of the TD (190A), the encrypted contents comprise at least one of a physical address (<NUM>) of the first memory page or a virtual address (<NUM>) of a second memory page where the encrypted contents of the transportable page (<NUM>) are stored, and is encrypted using a key (205A) associated with the TD (190A), wherein the TD (190A) is cryptographically isolated in memory (<NUM>) using the key (205A) for encrypting the memory (<NUM>) associated with the TD (190A);
create a third memory page (<NUM>) associated with the TD (190A) by binding the transportable page (<NUM>) to the TD (190A), wherein binding the transportable page (<NUM>) to the TD (190A) comprises decrypting contents of the transportable page (<NUM>) using the TD specific encryption key (205A), and re-encrypting contents of the transportable page (<NUM>) based on an ephemeral key associated with the TD (190A) and a physical address of the memory location, wherein the ephemeral key is generated for each execution of the TD; and
access contents of the third memory page (<NUM>) by decrypting the contents of the third memory page using the ephemeral key associated with the TD (190A) and the physical address of the memory location.