Patent Description:
Quantum computers are computational machinery that depend on or use quantum mechanical phenomena, such as quantum superposition and quantum entanglement, as operating principles to perform data processing, for example. A unit element (or information itself) capable of storing information using a quantum mechanical principle is called a quantum bit or qubit, which can be used as a basic unit of information in a quantum computer.

Bits used in classical information storage elements have a state of "<NUM>" or "<NUM>", but qubits may have a state of "<NUM>" and "<NUM>" at the same time due to the superposition phenomenon. In addition, interaction between qubits may be achieved by entanglement. Due to the nature of these qubits, <NUM>N information can be generated using N qubits. Therefore, as the number of qubits increases, the amount of information and the processing speed can be exponentially increased compared to classical processing using the classical information storage elements.

<NPL>, discloses a 3D-based circuit quantum electrodynamics device in which qubits are placed between respective readout and storage cavities. <NPL>, discloses a 3D circuit QED architecture comprising a readout cavity structure and a storage cavity structure.

The invention is set out in independent claim <NUM>. Preferred aspects of the invention are set out in the dependent claims.

Also, descriptions of features that are understood in the art, after an understanding of the disclosure of this application, may be omitted for increased clarity and conciseness.

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout, and the size of each component in the drawings may be exaggerated for clarity and convenience of description. In this regard, the one or more embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein.

Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and after an understanding of the disclosure of this application. Terms, such as those defined in commonly used dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure of this application, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Throughout the descriptions of embodiments, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or can be electrically connected or coupled to the other element with intervening elements interposed therebetween. The terms "comprises" and/or "comprising" or "includes" and/or "including" when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements.

Hereinafter, what is described as "upper" or "on" may include not only directly over in contact but also over not in contact, and what is described as "lower" or "below" may include not only directly below in contact but also not in contact.

Herein, it is noted that use of the term "may" with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists where such a feature is included or implemented while all examples and embodiments are not limited thereto.

With respect to one or more embodiments described below, various types of qubits are available, including qubits that use a superconductor (that is, superconducting qubits), which may have an advantage in potential manufacture ease through semiconductor or integrated circuit techniques. For example, one or more embodiments may provide a quantum computing device or system having a high structural scalability.

<FIG> is a perspective view of a quantum computing device according to one or more embodiments. <FIG> is a plan view of the quantum computing device of <FIG>. <FIG> is a cross-sectional view taken along line I-I' of the quantum computing device of <FIG>. <FIG> is a cross-sectional view taken along line II-II' of the quantum computing device of <FIG>.

Referring to <FIG>, a quantum computing device (or system) <NUM> may include a bus chip <NUM>, a qubit chip <NUM>, a readout cavity structure <NUM>, a storage cavity structure <NUM>, and an inner shielding film <NUM>. The bus chip <NUM> may include a bus board <NUM>, a connection pad <NUM>, a transmission pad <NUM>, and a transmission wiring <NUM>. The bus chip <NUM> may provide a signal received from the outside of the quantum computing device <NUM> to the qubit chip <NUM>, e.g., the signal received from the outside may be received at the connection pad <NUM>, and provided to the qubit chip <NUM> through respective interactions between the connection pad <NUM> and the transmission pad <NUM>, between the transmission pad <NUM> and the transmission wiring <NUM>, and between the transmission wiring <NUM> and the qubit chip <NUM>, for example. In an example, the bus board <NUM> may extend in a first direction, e.g., the illustrated first direction DR1, different from a second direction, e.g., the second direction DR2, in which the qubit chip <NUM> extends. The bus board <NUM> may include an insulating material. For example, the bus board <NUM> may include a silicon (Si) board or a sapphire board. The connection pad <NUM> may include a superconducting material. For example, the connection pad <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The transmission pad <NUM> may be spaced apart from the connection pad <NUM> in the first direction DR1, and an end or other portion of the transmission pad <NUM> may face an end or other portion of the connection pad <NUM>. The transmission pad <NUM> may thus be configured to capacitively couple with connection pad <NUM>. For example, the end or other portion of the transmission pad <NUM> may have a length in the second direction DR2 that may be substantially the same as a length in the second direction DR2 of the end or other portion of the connection pad <NUM>. As a non-limiting example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. In such an example, and as illustrated in <FIG>, the length of the end or other portion of the transmission pad <NUM> in the second direction DR2 may be equal to the length of the end or other portion of the connection pad <NUM> in the second direction DR2, while the length of the connection pad <NUM> in the first direction DR1 may be substantially greater than the length of the transmission pad <NUM> in the first direction DR1. The transmission pad <NUM> may include a superconducting material. For example, the transmission pad <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The transmission wiring <NUM> may extend from the transmission pad <NUM> in the first direction DR1, e.g., the transmission wiring <NUM> may be electrically connected to the transmission pad <NUM>. The transmission wiring <NUM> may directly contact transmission pad <NUM>. For example, the transmission wiring <NUM> and the transmission pad <NUM> may be connected to each other without an interface therebetween. The transmission wiring <NUM> may include a superconducting material. For example, the transmission wiring <NUM> may include aluminum (Al), niobium (Nb), indium (In), and a combination thereof, as non-limiting examples.

The qubit chip <NUM> may have a through pad <NUM> and the transmission wiring <NUM> may interact with the through pad <NUM>, which may be configured to interact, e.g., capacitively couple, with a Josephson Junction represented by the qubit element <NUM>, as a non-limiting example. In addition, in an example where the quantum computing device includes a plurality of qubit chips <NUM> respectively arranged with respect to one bus chip <NUM>, the one bus chip <NUM> may further include a plurality of high-frequency resonators <NUM>, e.g., electrically connected or interacting with respective corresponding transmission wirings <NUM>, such that respective high-frequency electromagnetic signals generated by the high-frequency resonators <NUM> may control formation of quantum entanglement between the respective plurality of qubits of the plurality of qubit chips <NUM>. In an alternate example, the plurality of high-frequency resonators <NUM> may be arranged on a plurality of respective bus chips <NUM> corresponding to the plurality of qubit chips <NUM>, as a non-limiting example. Still further, in an example the quantum computing device may be a quantum computing device or system that includes a plurality of quantum computing devices that each include such plurality of qubit chips <NUM>. Such examples of the quantum computing device or system are further explained in greater detail below with respect to <FIG> and further below with respect to <FIG>, for example.

Accordingly, the qubit chip <NUM> may include a qubit board <NUM>, a readout antenna <NUM>, a storage antenna <NUM>, the qubit element <NUM>, a readout wiring <NUM>, a storage wiring <NUM>, the through wiring <NUM>, and the through pad <NUM>. As illustrated in <FIG>, in an example, the qubit board <NUM> may be provided on the bus chip <NUM>. For example, the qubit board <NUM> may extend in the second direction DR2, e.g., extending beyond one or more sides of the bus chip <NUM> in the second direction DR2. From a viewpoint in the third direction DR3, different from the first direction DR1 and the second direction DR2, the qubit board <NUM> may intersect with the bus chip <NUM>. For example, when the first direction DR1 and the second direction DR2 are different directions in a same horizontal plane, as a non-limiting example, the third direction DR3 may be the vertical direction, and thus, the qubit board <NUM> may vertically overlap the bus chip <NUM>. The qubit board <NUM> may include a first end part 210A and an opposite second end part 210B spaced apart from each other in the second direction DR2. From a viewpoint in the third direction DR3, the first end part 210A and the second end part 210B of the qubit board <NUM> may be spaced apart from each other with the bus chip <NUM> arranged therebetween, e.g., with the bus chip <NUM> extending along an example mid-line of the qubit board <NUM> in the first direction DR1. The qubit board <NUM> may include an insulating material. For example, the qubit board <NUM> may include a silicon (Si) board or a sapphire board.

The readout antenna <NUM> may be provided on the first end part 210A of the qubit board <NUM>. For example, the readout antenna <NUM> extends from the first end part 210A of the qubit board <NUM> toward the second end part 210B, e.g., extending to the example readout wiring <NUM>. The readout antenna <NUM> may be capacitively coupled to the readout connector <NUM> described in greater detail below. The readout antenna <NUM> may be configured to receive a high frequency signal provided from the readout connector <NUM> and transmit a high frequency signal to the readout connector <NUM>, e.g., operated to receive a high frequency signal or transmit a high frequency signal. The readout antenna <NUM> may include a superconducting material. For example, the readout antenna <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The storage antenna <NUM> may be provided on the second end part 210B of the qubit board <NUM>. For example, the storage antenna <NUM> extends from the second end part 210B toward the first end part 210A, e.g., extending to the example storage wiring <NUM>. The storage antenna <NUM> may be capacitively coupled to the storage connector <NUM> described below. The storage antenna <NUM> may be configured to receive a high frequency signal provided from the storage connector <NUM> and transmit a high frequency signal to the storage connector <NUM>, e.g., operated to receive a high frequency signal or transmit a high frequency signal. The storage antenna <NUM> may be disposed in a storage cavity <NUM>, described in greater detail below, to increase the coherence state period duration time of the qubit element <NUM> and perform unitary operations. The storage antenna <NUM> may include a superconducting material. For example, the storage antenna <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

As noted above, the qubit element <NUM> may be provided on the qubit board <NUM>. The qubit element <NUM> may be representative of an element having a nonlinear coupling. For example, the qubit element <NUM> may be representative of the aforementioned example Josephson Junction. The Josephson Junction may include a first superconducting material pattern and a second superconducting material pattern facing each other, and a non-superconducting material pattern (e.g., dielectric film) or air gap between the first and second superconducting material patterns. Cooper pairs can tunnel the Josephson Junction. Cooper pairs may refer to electron pairs that do not receive electrical resistance within the superconducting material pattern. Thus, Cooper pairs can represent the same quantum state and can be expressed by the same wave function.

The readout wiring <NUM> may be provided between the readout antenna <NUM> and the qubit element <NUM>. The readout wiring <NUM> may extend in the second direction DR2. The readout wiring <NUM> may be electrically connected to the readout antenna <NUM>. For example, the readout wiring <NUM> may directly contact the readout antenna <NUM>. In an example where the qubit element <NUM> includes the example Josephson Junction, the readout wiring <NUM> may be electrically connected to the first superconducting material pattern of the Josephson Junction. For example, the readout wiring <NUM> may directly contact the first superconducting material pattern. In one example, the readout wiring <NUM>, the readout antenna <NUM>, and the first superconducting material pattern may have a single structure. In other words, the readout wiring <NUM>, the readout antenna <NUM>, and the first superconducting material pattern may be connected to each other without an interface therebetween. The readout wiring <NUM> may include a superconducting material. For example, the readout wiring <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The storage wiring <NUM> may be provided between the storage antenna <NUM> and the qubit element <NUM>. The storage wiring <NUM> may extend in the second direction DR2. The storage wiring <NUM> may be electrically connected to the storage antenna <NUM>. For example, the storage wiring <NUM> may directly contact the storage antenna <NUM>. In an example where the qubit element <NUM> includes the example Josephson Junction, the storage wiring <NUM> may be electrically connected to the second superconducting material pattern of the Josephson Junction. For example, the storage wiring <NUM> may directly contact the second superconducting material pattern. In one example, the storage wiring <NUM>, the storage antenna <NUM>, and the second superconducting material pattern may have a single structure. In other words, the storage wiring <NUM>, the storage antenna <NUM>, and the second superconducting material pattern may be connected to each other without an interface therebetween. The storage wiring <NUM> may include a superconducting material. For example, the storage wiring <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The through wiring <NUM> may be provided in the qubit board <NUM>. The through wiring <NUM> may be provided under the qubit element <NUM>. For example, the through wiring <NUM> may overlap the qubit element <NUM> in the third direction DR3. The through wiring <NUM> may extend to the through pad <NUM> in the third direction DR3 from a position having the same height as the bottom surface of the qubit board <NUM>. As noted above, in an example the through wiring <NUM> may be electrically connected to the transmission wiring <NUM>. For example, the through wiring <NUM> may penetrate the bottom surface of the qubit board <NUM> and directly contact the transmission wiring <NUM>. The through wiring <NUM> may include a superconducting material. For example, the through wiring <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The through pad <NUM> may be provided on or at an end of the through wiring <NUM>. Thus, the through pad <NUM> may be electrically connected to the through wiring <NUM>. For example, the through pad <NUM> may directly contact the upper end part of the through wiring <NUM>. In one example, the through pad <NUM> may have a single structure with the through wiring <NUM>. In other words, the through pad <NUM> and the through wiring <NUM> may be connected to each other without an interface therebetween. In an example, as illustrated in <FIG>, the through pad <NUM> may have a larger perimeter or diameter than the through wiring <NUM>, e.g., compared respectively along the third direction DR3. Said another way, for example, the width of the through pad <NUM> in the first direction DR1 or the second direction DR2 may be greater than a width of the through wiring <NUM> respectively in the first direction DR1 or the second direction DR2. The through pad <NUM> may be proximate to or face the qubit element <NUM>, e.g., with the through pad being configured with respect to the qubit element <NUM> to capacitively couple with the qubit element <NUM>. In an example where the qubit element <NUM> includes a Josephson Junction, the through pad <NUM> may be capacitively coupled to the lower superconducting material pattern of the Josephson Junction. The through pad <NUM> may include a superconducting material. For example, the through pad <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The readout cavity structure <NUM> may surround at least a portion of the first end part 210A of the qubit chip <NUM>, e.g., the readout cavity structure <NUM> may encapsulate at least a portion or all of the readout antenna <NUM>. The readout cavity structure <NUM> can define a readout cavity <NUM> therein. Through configuration of the readout cavity structure <NUM>, the readout cavity <NUM> may be configured to be an element for readout of the qubit and for increasing the coherence state period duration time of the qubit, as only an example. The readout cavity structure <NUM> may include a superconducting material. For example, the readout cavity structure <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The readout connector <NUM> may be provided in or at the readout cavity structure <NUM>. The readout connector <NUM> may be configured to access, pass through, or penetrate the readout cavity structure <NUM>, e.g., in a manner that maintains or provides the benefits of the increase in coherence state period duration time by the configured encapsulating of the portion or all of the readout antenna <NUM> by the readout cavity structure <NUM>. Accordingly, the readout connector <NUM> can provide a capability to access the readout cavity <NUM>. For example, the readout connector <NUM> may be aligned or face the readout antenna <NUM> in the second direction DR2, and may be configured to capacitively couple with the readout antenna <NUM>. The readout connector <NUM> may thus also be configured to receive an electrical signal from a device external to the quantum computing device <NUM>. The readout connector <NUM> may be configured to convert an electrical signal into an electromagnetic wave signal having a high frequency. The location of the readout connector <NUM> may be determined according to the strength of the coupling between the high frequency signal and the readout cavity <NUM>.

The storage cavity structure <NUM> is spaced apart from the readout cavity structure <NUM> in the second direction DR2. For example, the storage cavity structure <NUM> may surround at least a portion of the second end part 210B of the qubit chip <NUM>, e.g., the storage cavity structure <NUM> may encapsulate at least a portion or all of the storage antenna <NUM>. The storage cavity structure <NUM> may define a storage cavity <NUM> therein.

Through configuration of the storage cavity structure <NUM>, the storage cavity <NUM> may be configured to be an element for performing a unitary operation using the qubit and for containing information of the qubit, as only an example. Quantum information may be stored longer in the storage cavity <NUM>. The storage cavity structure <NUM> may include a superconducting material. For example, the storage cavity structure <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The storage connector <NUM> may be provided in or at the storage cavity structure <NUM>. The storage connector <NUM> may be configured to access, pass through, or penetrate the storage cavity structure <NUM>, e.g., in a manner that maintains or provides the benefits of the increase in coherence state period duration time by the configured encapsulating of the portion or all of the storage antenna <NUM> by the storage cavity structure <NUM>. Accordingly, the storage connector <NUM> can provide the capability to access the storage cavity <NUM>. For example, the storage connector <NUM> may be aligned or face the storage antenna <NUM> in the second direction DR2, and may be configured to capacitively couple with the storage antenna <NUM>. The storage connector <NUM> may thus also be configured to receive an electrical signal from a device external to the quantum computing device <NUM>. For example, an input signal for controlling qubit and storaging information may be input from the outside of the quantum computing device <NUM> through the storage connector <NUM>. The storage connector <NUM> may be configured to convert an electrical signal into an electromagnetic wave signal having a high frequency. The number of storage connector <NUM> is not limited to one, and may be determined as needed. The location of the storage connector <NUM> may be determined according to the strength of the coupling between the high frequency signal and the storage cavity <NUM>.

An inner shielding film <NUM> may be provided between the readout cavity structure <NUM> and the storage cavity structure <NUM>. For example, the inner shielding film <NUM> may cover a portion of the bus chip <NUM> and a portion of the qubit chip <NUM>, e.g., the portion of the qubit chip <NUM> not already covered by the readout cavity structure <NUM> and the storage cavity structure <NUM>, and thus may provide a benefit that the bus chip <NUM> and the qubit chip <NUM> may not be affected by unintended electromagnetic waves. In an example, the inner shielding film <NUM> may completely surround or encapsulate the bus chip <NUM> and the qubit chip <NUM> respective portions between the readout cavity structure <NUM> and the storage cavity structure <NUM>. For example, the inner shielding film <NUM> may have a lower inner shielding film <NUM> and an upper inner shielding film <NUM>, and may provide an additional example where the upper inner shielding film <NUM> additionally extends to cover remaining sides of the qubit chip <NUM>, e.g., between adjacent end parts of the lower inner shielding film <NUM> and the upper inner shielding film <NUM> to fully surround or encapsulate the qubit chip <NUM> portion including the qubit element <NUM> and a portion of the bus chip <NUM> overlapped by the qubit chip <NUM>. In such a non-limiting example, the lower inner shielding film <NUM> may contact and support the bus chip <NUM> under the bus chip <NUM>. The shielding films (e.g., the lower inner shielding film <NUM> and the upper inner shielding film <NUM>) may be or include a superconducting material. For example, the shielding films may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

As discussed above with respect to <FIG>, as well as with respect to the below <FIG>, a quantum computing device may include a bus chip, extending in a first direction at least between a readout cavity structure and a storage cavity structure, and qubit chip disposed on the bus chip and reaching into the readout cavity structure and reaching into the storage cavity structure.

In one or more embodiments, such a quantum computing device may include the bus chip, and the qubit chip extending in a different second direction, where the qubit chip includes a qubit element representing the qubit element being formed by an first superconducting material pattern connected to an antenna that is at least partially arranged in the readout cavity structure, and a second superconducting material pattern connected to another antenna that is at least partially arranged in the storage cavity structure. The qubit chip may include an electrical connection to the bus chip that is configured to influence the qubit formation. For the influence of the qubit formation, the electrical connection may include a through wiring and a through pad in the qubit chip being configured for capacitive coupling with the second superconducting material. A remaining portion of the qubit chip, including the qubit element and between the readout cavity structure and the storage cavity structure, may be encapsulated by an inner shielding film that may also cover a portion of the bus chip vertically overlapped by the qubit chip. A portion of the inner shielding film may also support the bus chip. A quantum computing system may include two or more of the qubits chip, the readout cavity, the storage cavity, and high-frequency resonators for control of quantum entanglement formation between the respective two or more qubits of the two or more qubit chips.

Thus, when the numbers of qubit chips, readout cavities, and storage cavities, for example, are further increased, the above quantum computing device or system descriptions may be further applicable to understand implementation of various example multi-qubit structures. Further example quantum computing devices or systems having such multi-qubit structures will be described in greater detail below. Accordingly, various embodiments of the present disclosure may provide a quantum computing device and system with high structural scalability.

<FIG> is a perspective view of a quantum computing device according to one or more embodiments. <FIG> is a plan view of the quantum computing device of <FIG>. <FIG> is a cross-sectional view taken along line III-III' of the quantum computing device of <FIG>. For conciseness of description, descriptions as those given with reference to <FIG> are applicable for same reference numbers, except where indicated otherwise, and accordingly descriptions from the same will not be repeated below.

Referring to <FIG>, a quantum computing device (or system) <NUM> may include a bus chip <NUM>, a plurality of qubit chips <NUM>, a readout cavity structure <NUM>, a storage cavity structure <NUM>, and a plurality of inner shielding films <NUM>. The bus chip <NUM> may include a bus board <NUM>, a first connection pad <NUM>, a second connection pad <NUM>, a transmission pad <NUM>, a transmission wiring <NUM>, and high-frequency resonators <NUM>.

Descriptions of the bus board <NUM>, the connection pad <NUM>, the transmission pad <NUM>, and the transmission wiring <NUM> with respect to <FIG> are respectively applicable to the bus board <NUM>, the first connection pad <NUM>, the transmission pad <NUM>, and the transmission wiring <NUM> with respect to <FIG>, and thus descriptions from the same will not be repeated below.

The second connection pad <NUM> may be a bonding area, as a non-limiting example, configured for connection/bonding with a connection wire connecting the bus chip <NUM> of the quantum computing device <NUM> to the bus chip of another quantum computing device other than the quantum computing device <NUM>. The second connection pad <NUM> may include a superconducting material. For example, the second connection pad <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

The high-frequency resonators <NUM> may be provided between the qubit chips <NUM>, respectively. The high-frequency resonators <NUM> may each include LC resonators for electromagnetic signals having high frequencies. The high-frequency resonators <NUM> may include elements and configurations for forming quantum entanglement between the respective qubits of the qubit chips <NUM>. The shape, arrangement, or form of each of the high-frequency resonators <NUM> is not limited to that shown. Various shapes, arrangements, and forms of the high-frequency resonators <NUM> are included in examples, having respective LC resonator functions for various electromagnetic signals having high frequencies. The high-frequency resonators <NUM> may be sequentially arranged in the first direction DR1. The high-frequency resonators <NUM> may be electrically connected in series with each other. For example, the high-frequency resonators <NUM> directly adjacent to each other may directly contact each other. The respective transmission wirings <NUM> and the high-frequency resonators <NUM> directly adjacent to each other may be electrically connected. For example, the respective transmission wirings <NUM> and the high-frequency resonator <NUM> directly adjacent to each other may directly contact each other.

The qubit chips <NUM> may be sequentially arranged in the first direction DR1, respectively disposed between the high-frequency resonators <NUM>. Descriptions of the qubit chip <NUM> provided above with reference to <FIG> are applicable to each of the qubit chips <NUM> of <FIG>, in view of the discussions herein with respect to the aspects of the quantum computing device <NUM>, and thus descriptions from the same will not be repeated below. However, each of the through wirings <NUM> of each of the qubit chips <NUM> may be electrically connected to a corresponding adjacent high-frequency resonator <NUM>. For example, each through wiring <NUM> may directly contact an area of the bus board <NUM> to which the high-frequency resonators <NUM> directly adjacent to each other are connected.

In addition, in an example, the readout cavity structure <NUM> may be configured to provide a plurality of readout cavities <NUM>, with respective readout antennas <NUM> being respectively disposed in the corresponding readout cavities <NUM>. In addition, although <FIG> and <FIG> illustrate a plurality of readout cavities <NUM> arranged in one readout cavity structure <NUM>, embodiments are not limited thereto. For example, in other embodiments, the readout cavities <NUM> may be disposed within a plurality of readout cavity structures, respectively.

Readout connectors <NUM> may be respectively provided in or at the readout cavity structure <NUM>. For example, each readout connector <NUM> may be configured to access, pass through, or penetrate the readout cavity structure <NUM>, such as discussed above with respect to <FIG>. Thus, the readout connectors <NUM> may each provide a capability to access respective readout cavities <NUM>. The readout connectors <NUM> may be aligned or face readout antennas <NUM> extended in the second direction DR2, respectively. The readout connectors <NUM> may be configured for capacitive coupling to the readout antennas <NUM>, respectively.

The storage cavity structure <NUM> may be configured to provide the storage cavities <NUM>, with respective storage antennas <NUM> being respectively disposed in the corresponding storage cavities <NUM>. In addition, although <FIG> illustrate a plurality of storage cavities <NUM> arranged in one storage cavity structure <NUM>, embodiments are not limited thereto. For example, in other embodiments, the storage cavities <NUM> may be disposed within a plurality of storage cavity structures, respectively.

Storage connectors <NUM> may be respectively provided in or at the storage cavity structure <NUM>. For example, each storage connector <NUM> may be configured to access, pass through, or penetrate the storage cavity structure <NUM>, such as discussed above with respect to <FIG>. Thus, the storage connectors <NUM> may each provide a capability to access respective storage cavities <NUM>. The storage connectors <NUM> may be aligned or face storage antennas <NUM> extended in the second direction DR2, respectively. The storage connectors <NUM> may be configured for capacitive coupling to the storage antennas <NUM>, respectively.

Inner shielding films <NUM> may be provided between the readout cavity structure <NUM> and the storage cavity structure <NUM>. The inner shielding films <NUM> may respectively cover the qubit chips <NUM>. The bus chip <NUM> may extend to penetrate the inner shielding films <NUM>. The high-frequency resonators <NUM> may be exposed between the inner shielding films <NUM>. Further discussions above regarding shielding examples of <FIG> are also applicable with respect to shielding examples of <FIG>.

Quantum entanglement may occur between the qubits of the quantum computing device <NUM>.

Thus, in accordance with one or more embodiments and descriptions of <FIG>, as well as the below descriptions of <FIG>, a quantum computing device or system may include a plurality of qubit chips, readout cavities, and storage cavities arranged in a first direction. Plural qubit chips, plural readout cavities, and plural storage cavities are available, noting that examples are no not limited to the brief descriptions herein. Examples include additional or fewer respective numbers of qubit chips, readout cavities, and storage cavities. Accordingly, various embodiments of the present disclosure may provide quantum computing devices and systems with high structural scalability.

<FIG> is a perspective view of a quantum computing device <NUM> according to one or more embodiments. For conciseness of description, descriptions with respect to <FIG> and <FIG>, as non-limiting examples, are applicable for same and related reference numbers, except where indicated otherwise below, and accordingly descriptions for the same will not be repeated below.

Referring to <FIG>, a quantum computing device (or system) <NUM> may include a first sub-quantum computing device 12a, a second sub-quantum computing device 12b, a third sub-quantum computing device 12c, a fourth sub-quantum computing device 12d, a first interlayer shielding film <NUM>, a second interlayer shielding film <NUM>, a third interlayer shielding film <NUM>, a first wire W1, a second wire W2, a third wire W3, and a fourth wire W4.

Each of the first to fourth sub-quantum computing devices 12a, 12b, 12c, and 12d may each be the same or respectively correspond to any of the examples described above with respect to the quantum computing device <NUM> described with reference to <FIG>, for example, and each may correspond to the any of above quantum computing device descriptions with respect to <FIG> regarding multi-qubit devices or systems. The first to fourth sub-quantum computing devices 12a, 12b, 12c, and 12d may be arranged in the third direction DR3. The first to fourth sub-quantum computing devices 12a, 12b, 12c, and 12d may be arranged in a stair form, for example. From the viewpoint in the third direction DR3, the first connection pad <NUM> and the second connection pad <NUM> of the sub-quantum computing device (e.g., the first sub-quantum computing device 12a) disposed at a low position may be partially exposed by the step shift of the next a sub-quantum computing device (e.g., the second sub-quantum computing device 12b) disposed at a higher position.

The first to third interlayer shielding films <NUM>, <NUM>, and <NUM> may be disposed between the first to fourth sub-quantum computing devices 12a, 12b, 12c, and 12d. The first to third interlayer shielding films <NUM>, <NUM>, and <NUM> may be configured to block unintended electromagnetic waves from being transmitted and received respectively between any of the first to fourth sub-quantum computing devices 12a, 12b, 12c, and 12d. The first to third interlayer shielding films <NUM>, <NUM>, and <NUM> may be or include a superconducting material. For example, the first to third interlayer shielding films <NUM>, <NUM>, and <NUM> may each include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

In an example, the first wire W1 is electrically connected to a high frequency electric signal generation device outside the quantum computing device (system) <NUM>, or outside the first to fourth sub-quantum computing devices 12a, 12b, 12c, and 12d, and also connected to the first connection pad <NUM> of the first sub-quantum computing device 12a, thereby receiving the high frequency electric signal. The first wire W1 may apply the electrical signal generated by the high frequency electrical signal generation device to any one of the first connection pad <NUM> and the second connection pad <NUM> of the first sub-quantum computing device 12a.

The second wire W2 may electrically connect the other of the first connection pad <NUM> and the second connection pad <NUM> of the first sub-quantum computing device 12a to any one of the first connection pad <NUM> and the second connection pad <NUM> of the second sub-quantum computing device 12b.

The third wire W3 may electrically connect the other of the first connection pad <NUM> and the second connection pad <NUM> of the second sub-quantum computing device 12b to any one of the first connection pad <NUM> and the second connection pad <NUM> of the third sub-quantum computing device 12c.

The fourth wire W4 may electrically connect the other of the first connection pad <NUM> and the second connection pad <NUM> of the third sub-quantum computing device 12c to any one of the first connection pad <NUM> and the second connection pad <NUM> of the fourth sub-quantum computing device 12d.

The second to fourth wires W2, W3, and W4 may provide electrical signals generated by the high-frequency electric signal generation device to the second to fourth sub-quantum computing devices 12b, 12c, and 12d, respectively. The first to fourth wires W1, W2, W3, and W4 may each include a superconducting material. For example, the first to fourth wires W1, W2, W3, and W4 may each include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

Thus, in accordance with one or more embodiments and descriptions of <FIG>, as well as the below descriptions of <FIG>, quantum entanglement may occur between qubits of a quantum computing device or system, including a quantum computing system that may include a plurality of quantum computing devices, e.g., stacked in a third direction. Each of the plural quantum computing devices may include a plurality of qubit chips <NUM>, readout cavities <NUM>, and storage cavities <NUM> arranged in a first direction. While a quantum computing device or system with an example plurality of quantum computing devices is discussed for explanation, embodiments are not limited thereto. The number of qubit chips in any one of the quantum computing devices is not limited to the example disclosure herein, the number of qubit chips are not required to be the same in different steps of quantum computing devices, and the number of steps of quantum computing devices also are not limited to the disclosure herein, as various examples exist with various number of steps. Thus, one or more embodiments demonstrate examples that may provide a quantum computing device or system with high structural scalability.

<FIG> is a perspective view of a quantum computing device according to one or more embodiments. <FIG> is a plan view of the quantum computing device of <FIG>. <FIG> is a cross-sectional view taken along line IV-IV' of the quantum computing device of <FIG>. <FIG> is a cross-sectional view taken along line V-V' of the quantum computing device of <FIG>. For conciseness of description, descriptions as those given with reference to <FIG> are applicable for same or related reference numbers, except where indicated otherwise, and accordingly descriptions from the same will not be repeated below.

Referring to <FIG>, a quantum computing device (or system) <NUM> may include a bus chip <NUM>, a qubit chip <NUM>, a readout cavity structure <NUM>, a storage cavity structure <NUM>, an inner shielding film <NUM>, and an outer shielding film <NUM>. The bus chip <NUM> may have a same configuration as the example configurations of the bus chip <NUM> described with reference to <FIG>, for example. The bus chip <NUM> may be disposed in the first direction DR1, and the qubit chip <NUM> may be disposed in a second direction, e.g., in a different second direction DR2, though the bus chip <NUM> with respect to <FIG> does not overlap, or is not overlapped, with respect to the qubit chip <NUM>. In the example of <FIG>, the bus chip <NUM> may be arranged in the second direction DR2 after an arrangement of the readout cavity structure <NUM> in the second direction DR2.

The qubit chip <NUM> may include a qubit board <NUM>, a readout antenna <NUM>, a storage antenna <NUM>, a readout wiring <NUM>, a storage wiring <NUM>, a through wiring <NUM>, a through pad <NUM>, and a lower wiring <NUM>. The readout antenna <NUM>, the storage antenna <NUM>, the readout wiring <NUM>, the storage wiring <NUM>, the through wiring <NUM>, and the through pad <NUM> may be substantially the same as the readout antenna <NUM>, the storage antenna <NUM>, the readout wiring <NUM>, the storage wiring <NUM>, the through wiring <NUM>, and the through pad <NUM> described with reference to <FIG>, respectively.

Similar to the above discussions in <FIG> of connections of the transmission wiring <NUM> to the through wiring <NUM> of the qubit chip <NUM>, the lower wiring <NUM> of <FIG> is configured to connect to the transmission wiring <NUM> of the bus chip <NUM> to the through wiring <NUM> of the qubit chip <NUM>, e.g., as the bus chip <NUM> and the qubit element <NUM> of the qubit chip <NUM> are separated in the example of <FIG> the lower wiring <NUM> may be used to connect the transmission wiring <NUM> to the through wiring <NUM>. For example, the qubit board <NUM> may extend from the bus chip <NUM> into the storage cavity <NUM> in the second direction DR2, where an example one of both end parts in the second direction DR2 of the qubit board <NUM> may be disposed on the bus chip <NUM> while the other end may be disposed within the storage cavity <NUM>. The qubit board <NUM> may be configured to penetrate a pair of sidewalls, e.g., facing each other, in the readout cavity structure <NUM> in the second direction DR2. As a non-limiting example, the sidewall of the readout cavity structure <NUM> facing the bus chip <NUM> may be a sidewall in which the readout connector <NUM> is configured or buried. Herein, while examples exist with respect to any board or chip, as non-limiting examples, penetrating a fully or partially formed cavity structure or shielding film, such examples are also inclusive of examples where such cavity structures or shielding film are formed with respect to any existing structures of such a board or chip to result in such access or penetration. As another example, examples herein with respect to connectors being configured in or at a sidewall or cavity structure, may also include the connectors being buried in the sidewall or cavity structure.

Connecting the transmission wiring <NUM> to the through wiring <NUM> of the qubit chip <NUM>, the lower wiring <NUM> may be provided below the qubit board <NUM>. For example, the lower wiring <NUM> may transit or extend along the bottom of the qubit board <NUM>, and in an example may be buried within an underside of the qubit board <NUM>, e.g., until the through wiring <NUM> is reached below the qubit element <NUM>. For example, the lower wiring <NUM> may extend in the second direction DR2. In an example, the lower wiring <NUM> may directly contact the transmission wiring <NUM> and directly contact the through wiring <NUM>.

An inner shielding film <NUM> surrounding the qubit chip <NUM> may be provided between the readout cavity structure <NUM> and the storage cavity structure <NUM>. The inner shielding film <NUM> may be substantially the same as the inner shielding film <NUM> described with reference to <FIG>.

An outer shielding film <NUM> may be provided from upper and lower sides, for example, of the readout cavity structure <NUM> facing the bus chip <NUM> to cover the bus chip <NUM> and the qubit chip <NUM>. The outer shielding film <NUM> may surround the bus chip <NUM> and the qubit chip <NUM>, e.g., covering respective upper and lower surfaces. In an example, the outer shielding film <NUM> may further completely cover the end part of the qubit chip <NUM>, e.g., thereby encapsulating the bus chip <NUM> and the entirety of the portions of the qubit chip <NUM> extending beyond the readout cavity structure <NUM>. The outer shielding film <NUM> may include a superconducting material. For example, the outer shielding film <NUM> may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

Thus, in accordance with one or more embodiments and descriptions of <FIG>, as well as the below discussions with respect to <FIG>, a quantum computing device may include a bus chip, extending in a first direction, and qubit chip being disposed on the bus chip and extending in a second direction and reaching into the readout cavity structure and reaching into the storage cavity structure. Similar to the above descriptions with respect to the bus chip being arranged with respect to a readout cavity structure, examples include the bus chip being arranged with respect to the readout cavity with respect to the readout cavity structure, though another side of the readout cavity structure than the discussions with respect to <FIG>, and a qubit chip disposed on the bus chip and reaching into the readout cavity structure and reaching into the storage cavity structure. Examples include plural qubit chips, readout cavities, and storage cavities, and thereby may provide a quantum computing device or system with high structural scalability.

<FIG> is a perspective view of a quantum computing device according to one or more embodiments. <FIG> is a plan view of the quantum computing device of <FIG>. <FIG> is a cross-sectional view taken along line VI-VI' of the quantum computing device of <FIG>. For conciseness of description, descriptions as those given with reference to <FIG> are applicable for same or related reference numbers, except where indicated otherwise, and accordingly descriptions from the same will not be repeated below.

Referring to <FIG>, a quantum computing device (or system) <NUM> may include a bus chip <NUM>, qubit chips <NUM>, a readout cavity structure <NUM>, a storage cavity structure <NUM>, inner shielding films <NUM>, and outer shielding films <NUM>. The bus chip <NUM> may include a bus board <NUM>, a first connection pad <NUM>, a second connection pad <NUM>, a transmission pad <NUM>, a transmission wiring <NUM>, and high-frequency resonators <NUM>. The bus board <NUM>, the first connection pad <NUM>, the transmission pad <NUM>, and the transmission wiring <NUM> may be substantially the same as the bus board <NUM>, the connection pad <NUM>, the transmission pad <NUM>, and the transmission wiring <NUM> described with reference to <FIG>, respectively, and related to the bus chip <NUM> of <FIG>, the description of which is also applicable in view of the disclosure of <FIG> and the below.

The high-frequency resonators <NUM> may be provided between the qubit chips <NUM>, respectively. The high-frequency resonators <NUM> may each include LC resonators for electromagnetic signals having high frequencies. The high-frequency resonators <NUM> may include elements and configurations for forming quantum entanglement between the respective qubits of the qubit chips <NUM>. The shape, arrangement, or form of each of the high-frequency resonators <NUM> is not limited to that shown. Various shapes, arrangements, and forms of the high-frequency resonators <NUM> are included in examples, having respective LC resonator functions for various electromagnetic signals having high frequencies. The high-frequency resonators <NUM> may be sequentially arranged in the first direction DR1. The high-frequency resonators <NUM> may be electrically connected in series with each other. For example, the high-frequency resonators <NUM> directly adjacent to each other may directly contact each other. The respective transmission wirings <NUM> and the high-frequency resonators <NUM> directly adjacent to each other may be electrically connected. For example, the respective transmission wirings <NUM> and the high-frequency resonators <NUM> directly adjacent to each other may directly contact each other.

The qubit chips <NUM> may be sequentially arranged in the first direction DR1, respectively disposed between the high-frequency resonators <NUM>. Each of the qubit chips <NUM> may include a qubit board <NUM>, a readout antenna <NUM>, a storage antenna <NUM>, a readout wiring <NUM>, a storage wiring <NUM>, a through wiring <NUM>, a through pad <NUM>, and a lower wiring <NUM>. Each of the qubit chips <NUM> may be substantially the same as the qubit chip <NUM> described with reference to <FIG>. The lower wiring <NUM> may be electrically connected to the high-frequency resonators <NUM>. For example, the lower wirings <NUM> may directly contact the areas to which the high-frequency resonators <NUM> directly adjacent to each other are connected. Adjacent connections, as well as the below discussions regarding the readout cavity structures, readout cavities, readout connectors, storage cavity structures, storage cavity, and storage connectors, storage are also related to the descriptions above with respect to <FIG>, the description also being incorporated with respect to the same reference numeral features in <FIG>.

The readout cavity structure <NUM> may include the respective readout cavities <NUM>. Readout antennas <NUM> may be respectively disposed in the readout cavities <NUM>. Although examples are illustrated with the readout cavities <NUM> being arranged in one readout cavity structure <NUM>, examples are not limited thereto. In another example, the readout cavities <NUM> may be disposed within a plurality of readout cavity structures, respectively.

Readout connectors <NUM> may be respectively provided in or at the readout cavity structure <NUM>. For example, each readout connector <NUM> may be configured to access, pass through, or penetrate the readout cavity structure <NUM>, such as discussed above. Thus, the readout connectors <NUM> may each provide a capability to access respective readout cavities <NUM>. The readout connectors <NUM> may be spaced apart from the qubit boards <NUM> in the third direction DR3, e.g., the readout connectors <NUM> may be slightly misaligned in the third direction DR3 of the readout antenna <NUM>. However, the location and spacing of the readout connectors <NUM> are not limited herein. The readout connectors <NUM> may be capacitively coupled to the readout antennas <NUM>, respectively.

The storage cavity structure <NUM> may include the storage cavities <NUM>. The storage antennas <NUM> may be respectively disposed in the storage cavities <NUM>. Although examples are illustrated with the storage cavities <NUM> being arranged in one storage cavity structure <NUM>, examples are not limited thereto. For example, in another embodiment, the storage cavities <NUM> may be disposed within a plurality of storage cavity structures, respectively.

Storage connectors <NUM> may be respectively provided in or at the storage cavity structure <NUM>. For example, each storage connector <NUM> may be configured to access, pass through, or penetrate the storage cavity structure <NUM>, such as discussed above. Thus, the storage connectors <NUM> may each provide a capability to access respective storage cavities <NUM>. The storage connectors <NUM> may face or be aligned with storage antennas <NUM> in the second direction DR2, respectively. The storage connectors <NUM> may be capacitively coupled to the storage antennas <NUM>, respectively.

Inner shielding films <NUM> may be provided between the readout cavity structure <NUM> and the storage cavity structure <NUM>. The inner shielding films <NUM> may respectively cover the qubit chips <NUM>.

The outer shielding films <NUM> may be provided to respectively cover the qubit chips <NUM>. For example, the outer shielding films <NUM> may completely cover end parts of the qubit chips <NUM>, respectively. The bus chip <NUM> may extend to penetrate the outer shielding films <NUM>. The high-frequency resonators <NUM> may be exposed between the outer shielding films <NUM>.

Quantum entanglement may occur between qubits of the quantum computing device <NUM>.

Thus, in accordance with one or more embodiments and descriptions of <FIG>, as well as the below description of <FIG>, a quantum computing device may include a plurality of qubit chips, readout cavities, and storage cavities arranged in a first direction. Plural qubit chips, plural readout cavities, and plural storage cavities may be provided, noting that examples of the present disclosure are not limited thereto. Various numbers of qubit chips, readout cavities, and storage cavities are available in various examples. Accordingly, various embodiments of the present disclosure may provide quantum computing devices or systems with high structural scalability.

<FIG> is a perspective view of a quantum computing device according to one or more embodiments. For conciseness of description, descriptions as those given with reference to <FIG> are applicable for same or related reference numbers, except where indicated otherwise, and accordingly descriptions from the same will not be repeated below.

Referring to <FIG>, a quantum computing device (or system) <NUM> may include a first sub-quantum computing device 22a, a second sub-quantum computing device 22b, a third sub-quantum computing device 22c, a fourth sub-quantum computing device 22d, a first interlayer shielding film <NUM>, a second interlayer shielding film <NUM>, a third interlayer shielding film <NUM>, a first wire W1, a second wire W2, a third wire W3, and a fourth wire W4. Any or all of the first to fourth sub-quantum computing devices 22a, 22b, 22c, and 22d may respectively be substantially the same as the quantum computing device <NUM> described with reference to <FIG>, with stepping or stacking of quantum computing devices and connection between quantum computing devices also being related to the disclosure of <FIG>, descriptions of which, in view of the below, are incorporated.

The first to fourth sub-quantum computing devices 22a, 22b, 22c, and 22d may be stacked in the third direction DR3. The first to fourth sub-quantum computing devices 22a, 22b, 22c, and 22d may be arranged in a stair or stacked form. From the viewpoint in the third direction DR3, the first connection pad <NUM> and the second connection pad <NUM> of the sub-quantum computing device (e.g., the first sub-quantum computing device 22a) disposed at a low position may be partially exposed by a sub-quantum computing device (e.g., the second sub-quantum computing device 22b) stacked or disposed at a higher position.

The first to third interlayer shielding films <NUM>, <NUM>, and <NUM> may be disposed between the first to fourth sub-quantum computing devices 22a, 22b, 22c, and 22d. The first to third interlayer shielding films <NUM>, <NUM>, and <NUM> may be configured to block unintended electromagnetic waves from being transmitted and received respectively between any of the first to fourth sub-quantum computing devices 22a, 22b, 22c, and 22d. The first to third interlayer shielding films <NUM>, <NUM>, and <NUM> may be or include a superconducting material. For example, the first to third interlayer shielding films <NUM>, <NUM>, and <NUM> may each include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

In an example, the first wire W1 electrically connects a high frequency electric signal generation device outside the quantum computing device (system) <NUM>, or outside the first to fourth sub-quantum computing devices 22a, 22b, 22c, and 22d, an also connected to the first connection pad <NUM> of the first sub-quantum computing device 22a, thereby receiving the high frequency electric signal. The first wire W1 may apply the electrical signal generated by the high frequency electrical signal generation device to any one of the first connection pad <NUM> and the second connection pad <NUM> of the first sub-quantum computing device 22a. The quantum computing device and system examples herein of <FIG> and <FIG> may similarly receive a high frequency electric signal from a high frequency generation device, e.g., with receipt by connection pads <NUM> with respect to <FIG> and <FIG>, or by the first connection pad <NUM> with respect to <FIG> and <FIG>. As respective non-limiting examples, the high frequency generation device may be provided from outside of any of the quantum computing devices or system of <FIG> and <FIG>.

The second wire W2 may electrically connect the other of the first connection pad <NUM> and the second connection pad <NUM> of the first sub-quantum computing device 22a to any one of the connection pad <NUM> and the second connection pad <NUM> of the second sub-quantum computing device 22b.

The third wire W3 may electrically connect the other of the first connection pad <NUM> and the second connection pad <NUM> of the second sub-quantum computing device 22b to any one of the first connection pad <NUM> and the second connection pad <NUM> of the third sub-quantum computing device 22c.

The fourth wire W4 may electrically connect the other of the first connection pad <NUM> and the second connection pad <NUM> of the third sub-quantum computing device 22c to any one of the first connection pad <NUM> and the second connection pad <NUM> of the fourth sub-quantum computing device 22d.

The second to fourth wires W2, W3, and W4 may provide electrical signals generated by the high-frequency electric signal generation device to the second to fourth sub-quantum computing devices 22b, 22c, and 22d, respectively. The first to fourth wires W1, W2, W3, and W4 may include a superconducting material. For example, the first to fourth wires W1, W2, W3, and W4 may each include aluminum (Al), niobium (Nb), indium (In), or a combination thereof, as non-limiting examples.

As discussed above respect to <FIG>, a quantum computing system may include a plurality of quantum computing devices, e.g., stacked in a third direction. Each of the plural quantum computing devices may include a plurality of qubit chips, readout cavities, and storage cavities arranged in a first direction. While plural quantum computing devices are discussed for explanation, embodiments are not limited thereto. The number of qubit chips in any one of the stacked quantum computing devices is not limited to the example disclosure herein, the number of qubit chips are not required to be the same in different steps of quantum computing devices, and the number of steps of quantum computing devices also are not limited to the disclosure herein, as various examples exist with various number of steps. Thus, one or more embodiments demonstrate examples that may provide a quantum computing system or device with high structural scalability.

Claim 1:
A quantum computing device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprising:
a first qubit chip (<NUM>);
a readout cavity structure (<NUM>, <NUM>) surrounding a first end part (210A) of the first qubit chip (<NUM>); and
a storage cavity structure (<NUM>, <NUM>) surrounding a second end part (210B) of the first qubit chip (<NUM>);
wherein the first qubit chip (<NUM>), the readout cavity structure (<NUM>, <NUM>) and the storage cavity structure (<NUM>, <NUM>) longitudinally extend in a first direction (DR2);
wherein the first qubit chip (<NUM>) comprises:
a first readout antenna (<NUM>) disposed in the readout cavity structure (<NUM>, <NUM>);
a first storage antenna (<NUM>) disposed in the storage cavity structure (<NUM>, <NUM>); and
a first qubit element (<NUM>) provided between the first readout antenna (<NUM>) and the first storage antenna (<NUM>), and
wherein the first qubit element (<NUM>) is disposed between the readout cavity structure (<NUM>, <NUM>) and the storage cavity structure (<NUM>, <NUM>);
wherein:
the readout cavity structure (<NUM>, <NUM>) and the storage cavity structure (<NUM>, <NUM>) are spaced apart in the first direction (DR2);
the first readout antenna (<NUM>) extends toward the first qubit element (<NUM>) in the first direction (DR2) such that a portion of the first readout antenna (<NUM>) is disposed between the readout cavity structure (<NUM>, <NUM>) and the storage cavity structure (<NUM>, <NUM>), and
the first storage antenna (<NUM>) extends toward the first qubit element (<NUM>) in the first direction (DR2) such that a portion of the first storage antenna (<NUM>) is disposed between the readout cavity structure (<NUM>, <NUM>) and the storage cavity structure (<NUM>, <NUM>).