Patent Description:
In the related art, a synchronization-type solid-state imaging device that captures image data in synchronization with a synchronization signal such as a vertical synchronization signal has been used in an imaging device and the like. In the typical synchronization-type solid-state imaging device, it is difficult to acquire image data for every period of the synchronization signal (for example, for every <NUM>/<NUM> seconds), and thus it is difficult to cope with cases in which relatively high-speed processing is demanded, such as in fields demanding high speed (e.g. real time) processing, such as autonomous vehicles, robotics, and the like. In this regard, there is suggested a non-synchronization-type solid-state imaging device in which a detection circuit is provided for every pixel to detect a situation in which a light-reception amount exceeds a threshold value as an address event in real time. The non-synchronization-type solid-state imaging device that detects the address event for every pixel is also referred to as a dynamic vision sensor (DVS). From patent application publication <CIT>, a unit pixel of an image sensor is known which operates in global shutter mode. Patent application publication <CIT> describes a plurality of pixels which are two-dimensionally arranged on a semiconductor substrate. The plurality of pixels includes two readout gates for a photodiode and two memories each receiving the charge from the photodiode through an associated one of the two readout gates.

However, in a DVS system, it is necessary to provide a circuit configuration for detecting the address event in addition to a circuit configuration for reading out a pixel signal of a voltage value corresponding to a light-reception amount, and thus an occupation ratio of a light-receiving element on a light-receiving surface decreases. By utilizing shared transistors, embodiments of the present disclosure enable a high resolution imaging device with sufficient sensitivity to be provided. In addition, isolation between different pixels or photodetectors within a DVS system is required in order to reduce cross talk. For example, in prior DVS systems full-thickness dielectric trench (RFTI) isolation has been adopted. However, the implementation of RFTI isolation structures in prior DVS systems has precluded or made difficult the sharing of transistors or other circuit elements between photodetectors. As a result, the quantum efficiency with respect to incident light (hereinafter, referred to as "light-reception efficiency") of DVS systems has been relatively poor.

Therefore, the present disclosure provides a solid-state imaging device and an imaging device which are capable of improving the light-reception efficiency.

According to a first aspect, the invention provides an imaging device in accordance with independent claim <NUM>. According to a second aspect, the invention provides an electronic apparatus in accordance with independent claim <NUM>. Further aspects are set forth in the dependent claims, the drawings, and the following description.

In accordance with embodiments and aspects of the present disclosure, there is provided in imaging device comprising a plurality of photoelectric conversion regions or pixels arranged in an array. Groups of multiple photoelectric conversion regions or pixels that share at least some circuit elements, including but not limited to transistors, are formed within the array. Full-thickness rear deep trench isolation (RFTI) structures are provided between the groups of multiple photoelectric conversion regions. Rear deep trench isolation (RDTI) is provided along at least portions of borders between adjacent photoelectric conversion regions within each group of multiple photoelectric conversion regions.

In accordance with further embodiments and aspects of the present disclosure, some or all of the photoelectric conversion regions are each operatively connected to first and second readout circuits. Moreover, circuit elements shared between photoelectric conversion regions within a group of photoelectric conversion regions can include at least some elements of the first and second readout circuits that are shared between the photoelectric conversion regions within any one group of photoelectric conversion regions. Shared elements can include, but are not limited to, transistors, floating diffusions, and signal lines.

In accordance with still further embodiments and aspects of the present disclosure, at least portions of one or more of the shared elements can be formed underneath an RDTI isolation structure, that is, between an end of an RDTI structure that terminates within a substrate and a non-incident light side surface of the substrate. The present disclosure provides solid-state imaging device and imaging devices with dynamic vision sensing and imaging capabilities that are capable of improved light-reception efficiencies. More particularly, embodiments of the present disclosure provide an imaging device with improved occupation ratios.

Hereinafter, an embodiment of the present disclosure will be described in detail on the basis of the accompanying drawings. Furthermore, in the following embodiments, the same reference numeral will be given to the same portion, and redundant description thereof will be omitted.

A typical dynamic vision sensor (DVS) employs a so-called event-driven type driving method in which the existence or nonexistence of address event ignition is detected for every unit pixel, and a pixel signal is read out from a unit pixel in which the address event ignition is detected.

Furthermore, the unit pixel in this description represents a minimum unit of a pixel including one photoelectric conversion element (also referred to as "light-receiving element"), and can correspond to each dot in image data that is read out from an image sensor as an example. In addition, the address event represents an event that occurs for every address that is allocable to each of a plurality of the unit pixels which are arranged in a two-dimensional lattice shape. An event detection sensor responds to a change in intensity asynchronously. Intensity change is correlated with a change in photocurrent, and if this change exceeds a constant threshold value it could be detected as an event.

<FIG> is a block diagram illustrating a schematic configuration example of an imaging device according to at least some embodiments of the present disclosure. As illustrated in <FIG>, for example, an imaging device <NUM> includes an imaging lens <NUM>, a solid-state imaging device <NUM>, a recording unit <NUM>, and a control unit <NUM>. As examples, the imaging device <NUM> can be provided as or as part of a camera that is mounted in an industrial robot, an in-vehicle camera, and the like are assumed.

The imaging lens <NUM> can include an optical system that directs (e.g. condenses) incident light and images an image of the incident light on a light-receiving surface of the solid-state imaging device <NUM>. The light-receiving surface is a surface on which photoelectric conversion elements in the solid-state imaging device <NUM> are arranged. The solid-state imaging device <NUM> photoelectrically converts the incident light to generate image data. In addition, the solid-state imaging device <NUM> can execute predetermined signal processing such as noise removal and white balance adjustment with respect to the generated image data. A result obtained by the signal processing and a detection signal indicating the existence or nonexistence of an address event ignition are output to the recording unit <NUM> through a signal line <NUM>. Furthermore, a method of generating the detection signal indicating the existence or nonexistence of the address event ignition will be described later.

The recording unit <NUM> is, for example, constituted by a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like, and records data input from the solid-state imaging device <NUM>.

The control unit <NUM> is, for example, constituted by a central processing unit (CPU) and the like, and outputs various instructions through a signal line <NUM> to control respective units such as the solid-state imaging device <NUM> in the imaging device <NUM>.

Next, a configuration example of the solid-state imaging device <NUM> will be described in detail with reference to the accompanying drawings.

<FIG> is a view illustrating a lamination structure example of a solid-state imaging device in accordance with at least some embodiments of the present disclosure. As illustrated in <FIG>, the solid-state imaging device <NUM> can have a structure in which a light-receiving chip <NUM> and a logic chip <NUM> are vertically laminated. In joining of the light-receiving chip <NUM> and the logic chip <NUM>, for example, so-called direct joining in which joining surfaces of the chips are planarized, and the chips are laminated with an inter-electron force can be used. However, there is no limitation thereto, and for example, so-called Cu-Cu joining in which copper (Cu) electrode pads formed on joining surfaces are bonded, bump joining, and the like can also be used.

In addition, the light-receiving chip <NUM> and the logic chip <NUM> are electrically connected to each other, for example, through a connection portion such as a through-silicon via (TSV) that penetrates through a semiconductor substrate. In the connection using the TSV, for example, a so-called twin TSV method in which two TSVs including a TSV that is formed in the light-receiving chip <NUM> and a TSV that is formed from the light-receiving chip <NUM> to the logic chip <NUM> are connected to each other on chip external surfaces, a so-called shared TSV method in which the light-receiving chip <NUM> and the logic chip <NUM> are connected with a TSV that penetrates through both the chips, and the like can be employed.

However, in the case of using the Cu-Cu joining or the bump joining in the joining of the light-receiving chip <NUM> and the logic chip <NUM>, both the light-receiving chip <NUM> and the logic chip <NUM> are electrically connected to each other through a Cu-Cu joint or a bump joint.

<FIG> is a block diagram illustrating a functional configuration example of the solid-state imaging device according to at least some embodiments of the present disclosure. As illustrated in <FIG>, the solid-state imaging device <NUM> includes a drive circuit <NUM>, a signal processing unit <NUM>, an arbiter <NUM>, a column ADC <NUM>, and a pixel array unit <NUM>.

A plurality of unit cells or pixels <NUM> are arranged in the pixel array unit <NUM> in a two-dimensional lattice shape. Details of the unit pixels <NUM> will be described later. For example, each of the unit pixels <NUM> includes a photoelectric conversion element such as a photodiode, and a circuit that generates a pixel signal of a voltage value corresponding to the amount of charges generated in the photoelectric conversion element (hereinafter, referred to as a pixel circuit or a pixel imaging signal generation readout circuit). Here, the pixel circuit may be shared by a plurality of photoelectric conversion elements. In this case, the unit pixels <NUM> each includes one photoelectric conversion element and a pixel circuit that is shared.

The plurality of unit pixels <NUM> are arranged in the pixel array unit <NUM> in a two-dimensional lattice shape. The plurality of unit pixels <NUM> may be grouped into a plurality pixel blocks, each including a predetermined number of unit pixels. Hereinafter, an assembly of unit pixels which are arranged in a horizontal direction is referred to as "row", and an assembly of unit pixels which are arranged in a direction orthogonal to the row is referred to as "column".

Each of the unit pixels <NUM> generates charges corresponding to an amount of light received at the respective photoelectric conversion element. In addition, the unit pixels <NUM>, alone or in combination with one or more other unit pixels <NUM> in the same group, can be operated to detect the existence or nonexistence of address event ignition on the basis of whether or not a value of a current (hereinafter, referred to as a photocurrent) produced by charges generated in the photoelectric conversion element or a variation amount thereof exceeds a predetermined threshold value. In addition, when the address event is ignited, a request for reading out a pixel signal of a voltage value corresponding to the light-reception amount of the photoelectric conversion element is output to the arbiter <NUM>.

The drive circuit <NUM> drives each of the unit pixels <NUM>, and allows each of the unit pixels <NUM> to output a pixel signal to the column ADC <NUM>.

The arbiter <NUM> arbitrates requests from the unit pixels, and transmits a predetermined response to the unit pixel <NUM> which issues the request on the basis of the arbitration result. The unit pixel <NUM> which receives the response supplies a detection signal indicating the existence or nonexistence of the address event ignition (hereinafter, simply referred to as "address event detection signal") to the drive circuit <NUM> and the signal processing unit <NUM>.

For every unit pixel <NUM> column, the column ADC <NUM> converts an analog pixel signal from the column into a digital signal. In addition, the column ADC <NUM> supplies a digital signal generated through the conversion to the signal processing unit <NUM>.

The signal processing unit <NUM> executes predetermined signal processing such as correlated double sampling (CDS) processing (noise removal) and white balance adjustment with respect to the digital signal transmitted from the column ADC <NUM>. In addition, the signal processing unit <NUM> supplies a signal processing result and an address event detection signal to the recording unit <NUM> through the signal line <NUM>.

The unit pixels <NUM> within the pixel array unit <NUM> may be disposed in pixel groups <NUM>. In the configuration illustrated in <FIG>, for example, the pixel array unit <NUM> is constituted by pixel groups <NUM> that include an assembly of unit pixels <NUM> that receive wavelength components necessary to reconstruct a color. For example, in the case of reconstructing a color on the basis of three primary colors of RGB, in the pixel array unit <NUM>, a unit pixel <NUM> that receives light of a red (R) color, a unit pixel <NUM> that receives light of a green (G) color, and a unit pixel <NUM> that receives light of a blue (B) color are arranged in groups 314a according to a predetermined color filter array.

Examples of the color filter array configuration include various arrays such as a Bayer array of <NUM> × <NUM> pixels, a color filter array of <NUM> × <NUM> pixels which is employed in an X-Trans (registered trademark) CMOS sensor (hereinafter, also referred to as "X-Trans (registered trademark) type array"), a Quad Bayer array of <NUM> × <NUM> pixels (also referred to as "Quadra array"), and a color filter of <NUM> × <NUM> pixels in which a white RGB color filter is combined to the Bayer array (hereinafter, also referred to as "white RGB array"). Here, in the following description, a case where the Bayer array is employed as the color filter array will be exemplified.

<FIG> is a schematic view illustrating an array example of unit pixels <NUM> in the case of employing pixel groups <NUM> with an arrangement of unit pixels <NUM> and associated color filters in the color filter array configured to form a plurality of Bayer arrays 310A. As illustrated in <FIG>, in the case of employing the Bayer array as the color filter array configuration, in the pixel array unit <NUM>, a basic pattern 310A including a total of four unit pixels of <NUM> × <NUM> pixels is repetitively arranged in a column direction and a row direction. For example, the basic pattern 310A is constituted by a unit pixel 310R including a color filter of a red (R) color, a unit pixel 310Gr including a color filter of a green (Gr) color, a unit pixel 310Gb including a color filter of a green (Gb) color, and a unit pixel 310B including a color filter of a blue (B) color.

Next, a configuration example of a unit pixel <NUM> will be described. <FIG> is a circuit diagram illustrating a schematic configuration example of the unit pixel <NUM> according to at least some embodiments of the present disclosure. As illustrated in <FIG>, the unit pixel <NUM> includes, for example, a pixel imaging signal generation unit (or readout circuit) <NUM>, a light-receiving unit <NUM>, and an address event detection unit (or readout circuit) <NUM>. According to at least one example embodiment, the readout circuit <NUM> is configured to control the readout circuit <NUM> based on charge generated by one or more photoelectric conversion elements (or photoelectric conversion regions) <NUM>. Each photoelectric conversion element <NUM> can be associated with a unit pixel transistor <NUM>. Furthermore, the logic circuit <NUM> in <FIG> is a logic circuit including, for example, the drive circuit <NUM>, the signal processing unit <NUM>, and the arbiter <NUM> in <FIG>.

For example, the light-receiving unit <NUM> includes a transmission transistor (first transistor) <NUM>, an overflow gate (OFG) transistor (fifth transistor) <NUM>, and a photoelectric conversion element <NUM>. A transmission signal TRG transmitted from the drive circuit <NUM> is supplied to a gate of the pixel group transmission transistor <NUM> of the light-receiving unit <NUM>, and a control signal OFG transmitted from the drive circuit <NUM> is supplied to a gate of the OFG transistor <NUM>. An output through the pixel group transmission transistor <NUM> of the light-receiving unit <NUM> is connected to the pixel imaging signal generation unit <NUM>, and an output through the OFG transistor <NUM> is connected to the address event detection unit <NUM>.

For example, the pixel imaging signal generation unit <NUM> includes a reset transistor (second transistor) <NUM>, an amplification transistor (third transistor) <NUM>, a selection transistor (fourth transistor) <NUM>, and a floating diffusion layer (FD) <NUM>.

The pixel group transmission transistor <NUM> and the OFG transistor <NUM> of the light-receiving unit <NUM> are constituted, for example, by using an N-type metal-oxide-semiconductor (MOS) transistor (hereinafter, simply referred to as "NMOS transistor"). Similarly, the reset transistor <NUM>, the amplification transistor <NUM>, and the selection transistor <NUM> of the pixel imaging signal generation unit <NUM> are each constituted, for example, by using the NMOS transistor.

For example, the address event detection unit <NUM> includes a current-voltage conversion unit <NUM> and a subtractor <NUM>. However, the address event detection unit <NUM> is further provided with a buffer, a quantizer, and a transmission unit. Details of the address event detection unit <NUM> will be described in the following description by using <FIG> and the like.

In the illustrated configuration, the photoelectric conversion element <NUM> of the light-receiving unit <NUM> photoelectrically converts incident light to generate a charge. The pixel group transmission transistor <NUM> transmits a charge generated in the photoelectric conversion element <NUM> to the floating diffusion layer <NUM> in accordance with the transmission signal TRG. The OFG transistor <NUM> supplies an electric signal (photocurrent) based on the charge generated in the photoelectric conversion element <NUM> to the address event detection unit <NUM> in accordance with the control signal OFG.

The floating diffusion layer <NUM> accumulates charges transmitted from the photoelectric conversion element <NUM> through the pixel group transmission transistor <NUM>. The reset transistor <NUM> discharges (initializes) the charges accumulated in the floating diffusion layer <NUM> in accordance with a reset signal transmitted from the drive circuit <NUM>. The amplification transistor <NUM> allows a pixel signal of a voltage value corresponding to a charge amount of charges accumulated in the floating diffusion layer <NUM> to appear in a vertical signal line VSL. The selection transistor <NUM> switches a connection between the amplification transistor <NUM> and the vertical signal line VSL in accordance with a selection signal SEL transmitted from the drive circuit <NUM>. Furthermore, the analog pixel signal that appears in the vertical signal line VSL is read out by the column ADC <NUM>, and is converted into a digital pixel signal.

When an instruction for address event detection initiation is given by the control unit <NUM>, the drive circuit <NUM> in the logic circuit <NUM> outputs the control signal OFG for setting the OFG transistor <NUM> of all light-receiving units <NUM> in the pixel array unit <NUM> to an ON-state. With this arrangement, a photocurrent generated in the photoelectric conversion element <NUM> of the light-receiving unit <NUM> is supplied to the address event detection unit <NUM> of each unit pixel <NUM> through the OFG transistor <NUM>.

When detecting address event ignition on the basis of the photocurrent from the light-receiving unit <NUM>, the address event detection unit <NUM> of each unit pixel <NUM> outputs a request to the arbiter <NUM>. With respect to this, the arbiter <NUM> arbitrates the request transmitted from each of the unit pixels <NUM>, and transmits a predetermined response to the unit pixel <NUM> that issues the request on the basis of the arbitration result. The unit pixel <NUM> that receives the response supplies a detection signal indicating the existence or nonexistence of the address event ignition (hereinafter, referred to as "address event detection signal") to the drive circuit <NUM> and the signal processing unit <NUM> in the logic circuit <NUM>.

The drive circuit <NUM> sets the OFG transistor <NUM> in the unit pixel <NUM> that is a supply source of the address event detection signal to an OFF-state. With this arrangement, a supply of the photocurrent from the light-receiving unit <NUM> to the address event detection unit <NUM> in the unit pixel <NUM> is stopped.

Next, the drive circuit <NUM> sets the pixel group transmission transistor <NUM> in the light-receiving unit <NUM> of the unit pixel <NUM> to an ON-state by the transmission signal TRG. With this arrangement, a charge generated in the photoelectric conversion element <NUM> of the light-receiving unit <NUM> is transmitted to the floating diffusion layer <NUM> through the pixel group transmission transistor <NUM>. In addition, a pixel signal of a voltage value corresponding to a charge amount of charges accumulated in the floating diffusion layer <NUM> appears in the vertical signal line VSL that is connected to the selection transistor <NUM> of the pixel imaging signal generation unit <NUM>.

As described above, in the solid-state imaging device <NUM>, a pixel signal SIG is output from the unit pixel <NUM> in which the address event ignition is detected to the column ADC <NUM>.

Furthermore, for example, the light-receiving unit <NUM>, the pixel imaging signal generation unit <NUM>, and two log (LG) transistors (sixth and seventh transistors) <NUM> and <NUM> and two amplification transistors (eighth and ninth transistors) <NUM> and <NUM> in the current-voltage conversion unit <NUM> of the address event detection unit <NUM> are disposed, for example, in the light-receiving chip <NUM> illustrated in <FIG>, and other components can be disposed, for example, in the logic chip <NUM> that is joined to the light-receiving chip <NUM> through the Cu-Cu joining. Therefore, in the following description, in the unit pixel <NUM>, configurations which are disposed in the light-receiving chip <NUM> are referred to as "upper layer circuit".

<FIG> is a block diagram illustrating a schematic configuration example of the address event detection unit according to at least some embodiments of the present disclosure. As illustrated in <FIG>, the address event detection unit <NUM> includes a current-voltage conversion unit <NUM>, a buffer <NUM>, a subtractor <NUM>, a quantizer <NUM>, and a transmission unit <NUM>.

The current-voltage conversion unit <NUM> converts the photocurrent from the light-receiving unit <NUM> into a voltage signal in a logarithm thereof, and supplies the voltage signal generated through the conversion to the buffer <NUM>.

The buffer <NUM> corrects the voltage signal transmitted from the current-voltage conversion unit <NUM>, and outputs a voltage signal after correction to the subtractor <NUM>.

The subtractor <NUM> lowers a voltage level of the voltage signal transmitted from the buffer <NUM> in accordance with a row drive signal transmitted from the drive circuit <NUM> and, supplies the lowered voltage signal to the quantizer <NUM>.

The quantizer <NUM> quantizes the voltage signal transmitted from the subtractor <NUM> into a digital signal, and outputs the digital signal generated through the quantization to the transmission unit <NUM> as a detection signal.

The transmission unit <NUM> transmits the detection signal transmitted from the quantizer <NUM> to the signal processing unit <NUM> and the like. For example, when address event ignition is detected, the transmission unit <NUM> supplies a request for transmission of an address event detection signal from the transmission unit <NUM> to the drive circuit <NUM> and the signal processing unit <NUM> to the arbiter <NUM>. In addition, when receiving a response with respect to the request from the arbiter <NUM>, the transmission unit <NUM> supplies the detection signal to the drive circuit <NUM> and the signal processing unit <NUM>.

For example, the current-voltage conversion unit <NUM> in the configuration illustrated in <FIG> includes the two LG transistors <NUM> and <NUM>, the two amplification transistors <NUM> and <NUM>, and a constant-current circuit <NUM> as illustrated in <FIG>.

For example, a source of the LG transistor <NUM> and a gate of the amplification transistor <NUM> are connected to a drain of the OFG transistor <NUM> of the light-receiving unit <NUM>. In addition, for example, a drain of the LG transistor <NUM> is connected to a source of the LG transistor <NUM> and a gate of the amplification transistor <NUM>. For example, a drain of the LG transistor <NUM> is connected to a power supply terminal VDD.

In addition, for example, a source of the amplification transistor <NUM> is grounded, and a drain thereof is connected to a gate of the LG transistor <NUM> and a source of the amplification transistor <NUM>. For example, a drain of the amplification transistor <NUM> is connected to a power supply terminal VDD through the constant-current circuit <NUM>. For example, the constant-current circuit <NUM> is constituted by a load MOS transistor such as a p-type MOS transistor.

In this connection relationship, a loop-shaped source follower circuit is constructed. With this arrangement, a photocurrent from the light-receiving unit <NUM> is converted into a voltage signal in a logarithmic value corresponding to a charge amount thereof. Furthermore, the LG transistors <NUM> and <NUM>, and the amplification transistors <NUM> and <NUM> may be each constituted, for example, by an NMOS transistor.

<FIG> is a circuit diagram illustrating a schematic configuration example of the subtractor and the quantizer according to at least some embodiments of the present disclosure. As illustrated in <FIG>, the subtractor <NUM> includes capacitors <NUM> and <NUM>, an inverter <NUM>, and a switch <NUM>. In addition, the quantizer <NUM> includes a comparator <NUM>.

One end of the capacitor <NUM> is connected to an output terminal of the buffer <NUM>, and the other end is connected to an input terminal of the inverter <NUM>. The capacitor <NUM> is connected to the inverter <NUM> in parallel. The switch <NUM> opens or closes a route connecting both ends of the capacitor <NUM> in accordance with a row drive signal.

The inverter <NUM> inverts a voltage signal that is input through the capacitor <NUM>. The inverter <NUM> outputs an inverted signal to a non-inverting input terminal (+) of the comparator <NUM>.

When the switch <NUM> is turned on, a voltage signal Vinit is input to a buffer <NUM> side of the capacitor <NUM>. In addition, the opposite side becomes a virtual ground terminal. A potential of the virtual ground terminal is set to zero for convenience. At this time, when a capacity of the capacitor <NUM> is set as C1, a potential Qinit that is accumulated in the capacitor <NUM> is expressed by the following Expression (<NUM>). On the other hand, both ends of the capacitor <NUM> are short-circuited, and thus an accumulated charge thereof becomes zero.

Next, when considering a case where the switch <NUM> is turned off, and a voltage of the capacitor <NUM> on the buffer <NUM> side varies and reaches Vafter, a charge Qafter accumulated in the capacitor <NUM> is expressed by the following Expression (<NUM>).

On the other hand, when an output voltage is set as Vout, a charge Q2 accumulated in the capacitor <NUM> is expressed by the following Expression (<NUM>).

At this time, a total charge amount of the capacitors <NUM> and <NUM> does not vary, and thus the following Expression (<NUM>) is established.

When Expression (<NUM>) to Expression (<NUM>) are substituted for Expression (<NUM>), the following Expression (<NUM>) is obtained.

Expression (<NUM>) represents a subtraction operation of a voltage signal, and a gain of the subtraction result becomes C1/C2. Typically, it is desired to maximize (or alternatively, improve) the gain, and thus it is preferable to make a design so that C1 becomes large and C2 becomes small. On the other hand, when C2 is excessively small, kTC noise increases, and thus there is a concern that noise characteristics deteriorate. Accordingly, a reduction in the capacity of C2 is limited to a range capable of permitting noise. In addition, since the address event detection unit <NUM> including the subtractor <NUM> is mounted for every unit pixel <NUM>, a restriction on an area is present in capacities C1 and C2. Values of the capacities C1 and C2 are determined in consideration of the restriction.

The comparator <NUM> compares a voltage signal transmitted from the subtractor <NUM> and a predetermined threshold voltage Vth that is applied to an inverting input terminal (-). The comparator <NUM> outputs a signal indicating the comparison result to the transmission unit <NUM> as a detection signal.

In addition, when a conversion gain by the current-voltage conversion unit <NUM> is set as CGlog, and a gain of the buffer <NUM> is set to "<NUM>", a gain A of the entirety of the address event detection unit <NUM> is expressed by the following Expression (<NUM>). <NUM>] <MAT>.

In Expression (<NUM>), iphoto_n represents a photocurrent of an nth unit pixel <NUM>, and a unit thereof is, for example, an ampere (A). N represents the number of the unit pixels <NUM> in a pixel block, and is "<NUM>" in this embodiment.

<FIG> is a block diagram illustrating a schematic configuration example of the column ADC according to at least some embodiments of the present disclosure. The column ADC <NUM> includes a plurality of ADCs <NUM> which are provided for every column of the unit pixels <NUM>.

Each of the ADCs <NUM> converts an analog pixel signal that appears in the vertical signal line VSL into a digital signal. For example, the pixel signal is converted into a digital signal in which a bit length is greater than that of a detection signal. For example, when the detection signal is set to two bits, the pixel signal is converted into a digital signal of three or greater bits (<NUM> bits and the like). The ADC <NUM> supplies a generated digital signal to the signal processing unit <NUM>.

Next, an operation of the solid-state imaging device <NUM> according to at least embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

First, an example of the operation of the solid-state imaging device <NUM> will be described by using a timing chart. <FIG> is a timing chart illustrating an example of the operation of the solid-state imaging device according to the first embodiment.

As illustrated in <FIG>, at a timing T0, when an instruction for address event detection initiation is given by the control unit <NUM>, the drive circuit <NUM> raises the control signal OFG applied to the gate of the OFG transistor <NUM> of all of the light-receiving units <NUM> in the pixel array unit <NUM> to a high level. With this arrangement, a plurality of the OFG transistors <NUM> of all of the light-receiving units <NUM> enter an ON-state, and a photocurrent based on a charge generated in the photoelectric conversion element <NUM> of each of the light-receiving units <NUM> is supplied from each the light-receiving units <NUM> to each of a plurality of the address event detection units <NUM>.

In addition, in a period in which the control signal OFG is in a high level, all of the transmission signals TRG applied to the gate of the pixel group transmission transistor <NUM> in each of the light-receiving units <NUM> are maintained in a low level. Accordingly, in this period, a plurality of the transmission transistors <NUM> in all of the light-receiving units <NUM> are in an OFF-state.

Next, a case where the address event detection unit <NUM> of an arbitrary unit pixel <NUM> detects address event ignition in a period in which the control signal OFG is in a high level will be assumed. In this case, the address event detection unit <NUM> that detects the address event ignition transmits a request to the arbiter <NUM>. With respect to this, the arbiter <NUM> arbitrates the request, and returns a response for the request to the address event detection unit <NUM> that issues the request.

The address event detection unit <NUM> that receives the response raises a detection signal that is input to the drive circuit <NUM> and the signal processing unit <NUM> to a high level, for example, in a period of a timing T1 to a timing T2. Furthermore, in this description, it is assumed that the detection signal is a one-bit signal.

The drive circuit <NUM> to which a high-level detection signal is input from the address event detection unit <NUM> at the timing T1 lowers all control signals OFG to a low level at a subsequent timing T2. With this arrangement, supply of a photocurrent from all of the light-receiving units <NUM> of the pixel array unit <NUM> to the address event detection unit <NUM> is stopped.

In addition, at the timing T2, the drive circuit <NUM> raises a selection signal SEL that is applied to a gate of the selection transistor <NUM> in the pixel imaging signal generation unit <NUM> of the unit pixel <NUM> in which the address event ignition is detected (hereinafter, referred to as "reading-out target unit pixel") to a high level, and raises a reset signal RST that is applied to a gate of the reset transistor <NUM> of the same pixel imaging signal generation unit <NUM> to a high level for a constant pulse period, thereby discharging (initializing) charges accumulated in the floating diffusion layer <NUM> of the pixel imaging signal generation unit <NUM>. In this manner, a voltage, which appears in the vertical signal line VSL in a state in which the floating diffusion layer <NUM> is initialized, is read out by the ADC <NUM> connected to the vertical signal line VSL in the column ADC <NUM> as a reset-level pixel signal (hereinafter, simply referred to as "reset level"), and is converted into a digital signal.

Next, at a timing T3 after reading out the reset level, the drive circuit <NUM> applies a transmission signal TRG of a constant pulse period to the gate of the pixel group transmission transistor <NUM> of the light-receiving unit <NUM> in the reading-out target unit pixel <NUM>. With this arrangement, a charge generated in the photoelectric conversion element <NUM> of the light-receiving unit <NUM> is transmitted to the floating diffusion layer <NUM> in the pixel imaging signal generation unit <NUM>, and a voltage corresponding to charges accumulated in the floating diffusion layer <NUM> appears in the vertical signal line VSL. In this manner, the voltage that appears in the vertical signal line VSL is read out by the ADC <NUM> connected to the vertical signal line VSL in the column ADC <NUM> as a signal-level pixel signal of the light-receiving unit <NUM> (hereinafter, simply referred to as "signal level") and is converted into a digital value.

The signal processing unit <NUM> executes CDS processing in which a difference between the reset level and the signal level which are read out as described above is obtained as a net pixel signal corresponding to a light-reception amount of the photoelectric conversion element <NUM>.

Next, at a timing T4, the drive circuit <NUM> lowers the selection signal SEL that is applied to the gate of the selection transistor <NUM> in the pixel imaging signal generation readout circuit <NUM> of the reading-out target unit pixel <NUM> to a low level, and raises the control signal OFG that is applied to the gate of the OFG transistor <NUM> of all of the light-receiving units <NUM> in the pixel array unit <NUM> to a high level. With this arrangement, address event ignition detection in all of the light-receiving units <NUM> in the pixel array unit <NUM> is restarted.

Next, an example of the operation of the solid-state imaging device <NUM> will be described by using a flowchart. <FIG> is a flowchart illustrating an example of the operation of the solid-state imaging device according to at least some embodiments of the present disclosure. For example, this operation is initiated when a predetermined application for detecting an address event is executed.

As illustrated in <FIG>, in this operation, first, each of the unit pixels <NUM> in the pixel array unit <NUM> detects existence or nonexistence of address event ignition (step S901). In addition, the drive circuit <NUM> determines whether or not address event ignition is detected in any one of the unit pixels <NUM> (step S902).

In a case where the address event ignition is not detected (NO in step S902), this operation proceeds to step S904. On the other hand, in a case where the address event ignition is detected (YES in step S902), the drive circuit <NUM> executes reading-out of a pixel signal with respect to the unit pixel <NUM> in which the address event ignition is detected (step S903), and proceeds to step S904.

In step S904, it is determined whether or not to terminate this operation. In a case where this operation is not terminated (NO in step S904), this operation returns to step S901, and the subsequent operations are repeated. On the other hand, in a case where this operation is terminated (YES in step S904), this operation is terminated.

<FIG> is a circuit diagram illustrating a schematic configuration example of a pixel group circuit <NUM> for a group <NUM> of unit pixels <NUM> in accordance with at least some embodiments of the present disclosure. More particularly, <FIG> illustrates a pixel group circuit <NUM> in which the photoelectric conversion units <NUM> of all of the unit pixels <NUM> included in a group <NUM> of unit pixels <NUM> share elements of the circuit <NUM>. In this example, the unit pixels <NUM> are part of a pixel group <NUM> comprising a basic Bayer array pattern 310A, with a first unit pixel 310R associated with a red color filter, a second unit pixel 310Gb associated with a green color filter, a third unit pixel 310Gr associated with a green color filter, and a fourth unit pixel 310B associated with a blue color filter. Accordingly, this example includes a group <NUM> of four unit pixels <NUM>. However, other arrangements and configurations are possible.

The pixel group circuit <NUM> generally includes a light receiving unit <NUM> having a plurality of photoelectric conversion units <NUM>. As an example, but without limitation, the photoelectric conversion units <NUM> can include photodiodes. In this example, one photoelectric conversion unit <NUM> is included in each unit pixel <NUM>, although other configurations are possible. Moreover, in this circuit <NUM> in which at least some elements are shared between multiple unit pixels <NUM>, the light receiving unit <NUM> includes a plurality of unit pixel transistors <NUM>, with the photoelectric conversion unit <NUM> of each unit pixel <NUM> being selectively connected to the pixel group transmission transistor <NUM> and the pixel group overflow gate transistor <NUM> by a respective unit pixel transmission transistor <NUM>. The pixel group circuit <NUM> also includes a pixel imaging signal generation readout circuit <NUM> and an address event detection readout circuit <NUM>. The pixel imaging signal generation readout circuit <NUM> and the address event detection readout circuit <NUM> can be configured in the same way as or similarly to the readout circuits <NUM> and <NUM> of <FIG>. The address event detection readout circuit <NUM> could also be formed from two transistors, depending on the desired sensitivity and pixel size.

As noted, each photoelectric conversion unit <NUM> is selectively connected to other circuit elements by a respective unit pixel transmission transistor <NUM>. Moreover, one or multiple photoelectric conversion units <NUM> can be connected to other circuit elements simultaneously through operation of the unit pixel transistors <NUM>. For instance, in an imaging mode, the unit pixel transmission transistor <NUM> associated with each selected photoelectric conversion unit <NUM> and the pixel group transmission transistor <NUM> are placed in a conductive state in order to operatively connect the selected photoelectric conversion unit <NUM> to the pixel imaging signal generation readout circuit <NUM>. In an event detection or dynamic vision sensor (DVS) mode, the unit pixel transmission transistor <NUM> associated with each selected photoelectric conversion unit <NUM> and the pixel group overflow gate transistor <NUM> are placed in a conductive state in order to operatively connect the selected photoelectric conversion unit <NUM> to the address event detection readout circuit <NUM>. In a typical operating condition, in the imaging mode a single one of the photoelectric conversion units <NUM> is operable at any one time to provide a signal to the pixel imaging signal generation readout circuit <NUM>, while in a DVS mode one, some, or all of the photoelectric conversion units <NUM> are operable at any one time to provide a signal to the address event detection readout circuit <NUM>.

The connection between any one of the photoelectric conversion units <NUM> and the pixel imaging signal generation readout circuit <NUM> is established by operating the unit pixel transmission transistor 334a-d of a selected photoelectric conversion unit 333a-d and the pixel group transmission transistor <NUM> to allow charge to pass from the selected photoelectric conversion unit <NUM> to the FD <NUM> of the pixel imaging signal generation readout circuit <NUM>. The charge can then be read out from the FD <NUM>, for example as described in connection with <FIG>. Although charge from a single photoelectric conversion unit <NUM> is passed to the pixel imaging signal generation readout circuit <NUM> in a typical imaging operation, other modes in which signals from multiple photoelectric conversion units <NUM>, corresponding to multiple unit pixels <NUM> are passed to the pixel imaging signal generation readout circuit <NUM> are possible. As can be appreciated by one of skill in the art after consideration of the present disclosure, the pixel group overflow gate transistor <NUM> remains closed during an imaging operation. As can further be appreciated by one of skill in the art after consideration of the present disclosure, the operation of the pixel image signal generation circuit <NUM> can be triggered by the detection of an event by the address event detection readout circuit <NUM> for the pixel group <NUM>.

The connection between any one or more of the photoelectric conversion units <NUM> and the address event detection readout circuit <NUM> is established by operating the unit pixel transmission transistor <NUM> of each selected photoelectric conversion unit <NUM> and the pixel group overflow gate transistor <NUM> to allow charge to pass from the selected photoelectric conversion units <NUM> to the address event detection readout circuit <NUM>. In accordance with at least some embodiments of the present disclosure, all of the unit pixel transmission transistors <NUM> and the pixel group overflow gate transistor <NUM> are operated to connect all of the photoelectric conversion units <NUM> within a pixel group <NUM> to the address event detection readout circuit <NUM> for that pixel group <NUM> simultaneously when the pixel group circuit <NUM> is operated in an address event detection mode. As can be appreciated by one of skill in the art after consideration of the present disclosure, the pixel group transmission transistor <NUM> remains closed (off) during an event detection operation.

Accordingly, the circuit configuration of <FIG> is an example of an arrangement in which a plurality of unit pixels <NUM> of an imaging device <NUM> capable of performing both event detection and imaging operations, and in which the photoelectric conversion units <NUM> of the respective unit pixels <NUM> share elements of the event detection <NUM> and pixel imaging signal generation readout <NUM> circuits.

<FIG> is a plan view of a portion of a pixel array unit <NUM>, and <FIG> is a cross section taken along line A-A' in <FIG>, illustrating a pixel group <NUM> configuration <NUM> in accordance with a first exemplary embodiment of the present disclosure. In this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by full thickness dielectric trench isolation or simply full thickness trench isolation (RFTI) structures <NUM>. Within each pixel group <NUM>, unit pixels <NUM> are separated from one another by an inter-pixel group isolation structure <NUM> in the form of deep trench isolation (RDTI) structures <NUM>. The inter pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion 1210a that extends between unit pixels <NUM> in adjacent rows, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns. More particularly, the pixel configuration <NUM> features RDTI structures <NUM> along the entire extent of the boundaries between adjacent unit pixels <NUM> within each pixel group <NUM>, with a first RDTI structure 1212a extending between adjacent rows of unit pixels <NUM> within each pixel group <NUM>, and a second RDTI structure 1212b extending between adjacent columns of unit pixels <NUM> within each pixel group <NUM>. Although in this example four pixel groups <NUM> in a 2x2 array in which each of the pixel groups <NUM> includes four unit pixels <NUM> in a 2x2 sub-array or group array pattern are shown, other configurations are possible.

In accordance with embodiments of the present disclosure, and as illustrated in <FIG>, RFTI structures <NUM> extend through the entire thickness of a substrate <NUM> in which the photodiodes <NUM> of the unit pixels <NUM> are formed. That is, the RFTI structures <NUM> extend from at least a first, light incident surface <NUM>, to a second, non-light incident surface <NUM>, of the substrate <NUM>. The RDTI structures <NUM> extend from a first end <NUM> at or above the first surface <NUM> to a second end <NUM> that is formed towards the second surface <NUM> of the substrate <NUM>. In particular, the RDTI structures <NUM> extend for distance that is less than a thickness of the substrate <NUM>, and thus do not reach the second surface <NUM>. Accordingly, substrate <NUM> material remains between the second end <NUM> of the RDTI structures <NUM> and the second surface <NUM> of the substrate <NUM>. Both the RFTI structures <NUM> and the RDTI structures <NUM> can be formed with a dielectric core <NUM>. As an example, but without limitation, the dielectric core <NUM> can be formed from silicon dioxide.

As also shown in <FIG>, each unit pixel <NUM> can include an insulation or planarizing layer <NUM> formed on the first surface <NUM> of the substrate <NUM>. In addition, a color filter <NUM> can be provided for each unit pixel <NUM>. In this example, a green color filter 1240Gb is provided as part of a first one of the illustrated unit pixels 310Gb, and a blue color filter 1240B is provided as part of a second one of the illustrated unit pixels 310B. Each unit pixel <NUM> can also be provided with an on-chip lens <NUM>. In accordance with still further embodiments, a light shielding element or structure <NUM> can be formed on or as part of the RFTI <NUM> and/or RDTI <NUM> structures at or on the first surface <NUM> of the substrate <NUM>.

The circuit elements associated with each pixel group <NUM> in the example pixel group configuration <NUM> of <FIG> and <FIG> may be the same as or similar to those illustrated in the pixel group circuit <NUM> of <FIG>. In accordance with embodiments of the present disclosure, one or more circuit elements, such as transistor, conductor, or other elements of a pixel group circuit <NUM>, are at least partially formed or located between the second end <NUM> of one or more of the RDTI structures <NUM> within an area of the pixel group <NUM> and the second surface <NUM> of the substrate <NUM>. For instance, in the example of <FIG> and <FIG>, at least a portion of a log transistor <NUM> of the address event detection readout circuit <NUM> for the pixel group circuit <NUM> can be formed between the second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. As a further example, at least a portion of a drain/ source region of amplification transistors <NUM> and <NUM> can be formed in an area between the second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. As still another example, at least a portion of a node <NUM> at which the unit pixel transistors <NUM> are connected to the pixel group transmission transistor <NUM> and the pixel group overflow gate transistor <NUM> can be formed between the second ends <NUM> of two intersecting RDTI structures <NUM> and the second surface <NUM> of the substrate <NUM>.

Accordingly, embodiments of the present disclosure can provide suitable isolation between pixel groups <NUM> using RFTI structures <NUM>, and between unit pixels <NUM> within a pixel group <NUM> using RDTI structures <NUM>, while providing a more favorable ratio of a total area of a pixel group <NUM> to areas of the photoelectric conversion units <NUM> of the unit pixels <NUM> within the pixel group <NUM> by facilitating the sharing of pixel group circuit <NUM> elements, and by enabling the formation of at least portions of elements of the pixel group circuit <NUM> in areas between an end of an RDTI structure <NUM> and a surface of the substrate <NUM>. Moreover, by allowing the area of the photo detector conversion unit <NUM> to be increased relative to the total pixel group <NUM> area, as compared to alternative configurations that do not feature RDTI <NUM> or other partial thickness structures <NUM>, the performance of the unit pixels <NUM> within the pixel group <NUM> can be improved, for example by improving the saturation signal and sensitivity of the unit pixels <NUM> in the group <NUM>.

The advantages of embodiments of the present disclosure can be further appreciated by comparing a pixel group <NUM> configuration <NUM> in accordance with embodiments of the present disclosure to the background pixel group configuration <NUM> depicted in <FIG>. In that background example, the boundaries between unit pixels <NUM> within a pixel group <NUM>, as well as between pixel groups <NUM>, are defined using RFTI structures <NUM>. In particular, in this example background configuration, sharing of transistors or other circuit elements between unit pixels <NUM> is not provided. Moreover, the inclusion of circuit elements in areas also occupied by RFTI structures <NUM> is not possible. As a result, the area of a circuit element portion <NUM> relative to a photoelectric conversion unit portion <NUM> of a unit pixel <NUM> in this prior art example is large. Said another way, the area of the photoelectric conversion unit portion <NUM> of this prior art example is a relatively small proportion of the total unit pixel <NUM> area.

<FIG> is a plan view of a pixel group <NUM> configuration <NUM> in accordance with a second exemplary embodiment of the present disclosure, <FIG> is a cross section of a portion of the second exemplary embodiment taken along line A-A' of <FIG>, and <FIG> is a cross section of another portion of the second exemplary embodiment taken along line B-B' of <FIG>. In this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by RFTI structures <NUM>. In addition, an inter-pixel group isolation structure <NUM> is provided that includes RFTI <NUM> and RDTI <NUM> structures. More particularly, RFTI structures <NUM> form portions of the boundaries between unit pixels <NUM> within different columns of unit pixels <NUM> in the same pixel group <NUM>, and RDTI structures <NUM> form the remaining portions of the boundaries between unit pixels <NUM> within different columns of the unit pixels <NUM> in the same pixel group <NUM>. RDTI structures <NUM> form the boundaries between unit pixels <NUM> within different rows of unit pixels <NUM> in the same pixel group <NUM>. Although in this example four pixel groups <NUM> in a 2x2 array in which each of the pixel groups <NUM> includes four unit pixels <NUM> in a 2x2 sub-array or group array pattern are shown, other configurations are possible.

As depicted in <FIG>, at least portions of various circuit elements can be formed between a second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. For example, as shown in <FIG>, at least portions of an amplification transistor <NUM> and of a pixel group overflow gate transistor <NUM> can be formed between a second end <NUM> of an RDTI structure <NUM> that extends between different rows of unit pixels <NUM> within a pixel group <NUM>. As a further example, and as shown in <FIG>, at least portions of a reset transistor <NUM> and of an amplification transistor <NUM> can be formed between an end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>.

With reference again to <FIG>, the portion of the inter-pixel group isolation structure 1210b between adjacent columns of unit pixels <NUM> within a pixel group <NUM> has a single RDTI structure <NUM> portion that intersects the portion of the inter-pixel group isolation structure 1210a that is formed entirely from an RDTI structure <NUM>. Accordingly, at least a portion of a node <NUM> at which the unit pixel transistors <NUM> are connected to the pixel group transmission transistor <NUM> and the pixel group overflow gate transistor <NUM> can be formed in the area where the two RDTI structures <NUM> within a pixel group <NUM> intersect.

<FIG> is a plan view of a pixel group <NUM> configuration <NUM> in accordance with a third exemplary embodiment of the present disclosure, <FIG> is a cross section of a portion of the third exemplary embodiment taken along line A-A' of <FIG>, and <FIG> is a cross section of another portion of the third exemplary embodiment taken along line B-B' of <FIG>. In this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by RFTI structures <NUM>. In addition, an inter-pixel group isolation structure <NUM> is provided that includes RFTI <NUM> and RDTI <NUM> structures. More particularly, the inter-pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion 1210a that extends between unit pixels <NUM> in adjacent rows and that includes both RFTI <NUM> and RDTI <NUM> structures, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns and that is formed from an RDTI structure <NUM>. Although in this example four pixel groups <NUM> in a 2x2 array in which each of the pixel groups <NUM> includes four unit pixels <NUM> in a 2x2 sub-array or group array pattern are shown, other configurations are possible.

As depicted in <FIG>, at least portions of various circuit elements can be formed between a second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. For example, as shown in <FIG>, at least portions of an amplification transistor <NUM> and of an pixel group overflow gate transistor <NUM> can be formed between a second end <NUM> of an RDTI structure <NUM> that extends between different columns of unit pixels <NUM> within a pixel group <NUM>. As a further example, and as shown in <FIG>, at least portions of a reset transistor <NUM> and of an amplification transistor <NUM> can be formed between an end <NUM> of an RDTI structure <NUM>.

With reference again to <FIG>, the portion of the inter-pixel group isolation structure 1210a between adjacent rows of unit pixels <NUM> within a pixel group <NUM> has a single RDTI structure <NUM> portion that intersects the portion of the inter-pixel group isolation structure 1210b that is formed entirely from an RDTI structure <NUM>. Accordingly, at least a portion of a node <NUM> at which the unit pixel transistors <NUM> are connected to the pixel group transmission transistor <NUM> and the pixel group overflow gate transistor <NUM> can be formed in the area where the two RDTI structures <NUM> within a pixel group <NUM> intersect.

<FIG> is a plan view of a pixel group <NUM> configuration in accordance with a fourth exemplary embodiment of the present disclosure, <FIG> is a cross section of a portion of the fourth exemplary embodiment taken along line A-A' of <FIG>, and <FIG> is a cross section of another portion of the fourth exemplary embodiment taken along line B-B' of <FIG>. In this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by RFTI structures <NUM>. In addition, an interpixel group isolation structure <NUM> is provided that includes RFTI <NUM> and RDTI <NUM> structures. More particularly, the inter-pixel group isolation structure <NUM> within a pixel group can include a horizontal portion that extends between unit pixels <NUM> in adjacent rows that includes both RFTI <NUM> and RDTI <NUM> structures, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns and that includes both RFTI <NUM> and RDTI <NUM> structures. In the example of <FIG>, two segments of RFTI structure <NUM> extend horizontally from the RFTI structures <NUM> located between pixel groups <NUM> in different columns of pixel groups <NUM>, one segment of RFTI <NUM> extends vertically from the RFTI structure <NUM> located along a lower border of the pixel group <NUM>, and one segment of RDTI structure <NUM> extends vertically from the RFTI structure <NUM> along an upper border of the pixel group <NUM>. In addition, a segment of horizontal RDTI structure <NUM> is located between the two segments of horizontal RFTI structures <NUM>.

As depicted in <FIG> and <FIG>, at least portions of various circuit elements can be formed between a second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. For example, as shown in <FIG>, at least a portion of a drain/source region between the pixel group transmission transistor <NUM> and the pixel group overflow gate transistor <NUM>, a portion of the pixel group transmission transistor <NUM>, and/or a portion of the pixel group overflow gate transistor <NUM> can be formed between a second end <NUM> of an RDTI structure <NUM> that extends between different columns of unit pixels <NUM> within a pixel group <NUM>. In addition, at least portions of the boundaries between adjacent unit pixels <NUM> can be separated from one another by portions of an RFTI structure <NUM>. Accordingly, embodiments of the present disclosure allow for the sharing of pixel group circuit <NUM> elements between unit pixels <NUM> within the same pixel group, while also allowing for isolation between those unit pixels <NUM>.

<FIG> also illustrates an example of a pixel group <NUM> configuration in which shared transistors are located in a single row of unit pixels <NUM> within each pixel group <NUM>. For example, the selection transistor <NUM>, the amplification transistor <NUM>, the reset transistor <NUM>, the pixel group transmission transistor <NUM>, the OFG transistor <NUM>, the first <NUM> and second <NUM> log transistors, and amplification transistors <NUM> and <NUM> can all be formed in one of the two rows of unit pixels <NUM>. Moreover, the transistors can all be formed in the row in which an entirety of a division between the adjacent unit pixels <NUM> of any one pixel group within that row is formed by an RDTI structure <NUM>.

<FIG> is a plan view of a pixel configuration in accordance with a fifth exemplary embodiment of the present disclosure, <FIG> is a cross section of a portion of the fifth exemplary embodiment taken along line A-A' in <FIG>, and <FIG> is a cross section of another portion of the fifth exemplary embodiment taken along line B-B' in <FIG>. In this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by RFTI structures <NUM>. In addition, an interpixel group isolation structure <NUM> is provided that includes RFTI <NUM> and RDTI <NUM> structures. More particularly, the inter-pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion that extends between unit pixels <NUM> in adjacent rows that includes both RFTI <NUM> and RDTI <NUM> structures, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns and that includes both RFTI <NUM> and RDTI <NUM> structures. In the example of <FIG>, two segments of RFTI structure <NUM> extend horizontally from the RFTI structures <NUM> between pixel groups <NUM> in different columns of pixel groups <NUM>, and one segment of RDTI structure <NUM> extends horizontally between the two horizontal segments of RFTI structures <NUM>. Two segments of RDTI structures <NUM> extend vertically from the RFTI structures <NUM> at the top and bottom of the pixel group <NUM>, with one vertical segment of RFTI structure <NUM> extending from the vertical RDTI structures <NUM>. Each vertical segment of RFTI structure <NUM> within the pixel group <NUM> is separated from one another by a vertical segment of RDTI structure <NUM> at a middle area of the pixel group <NUM>. The vertical segment of RDTI structure <NUM> also intersects the horizontal segment of RDTI structure <NUM> at the middle area of the pixel group.

As depicted in <FIG>, isolation between adjacent unit pixels <NUM> is provided, while also allowing at least portions of various circuit elements to be formed between a second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. For example, as shown in <FIG>, an RFTI structure <NUM> extends between at least some of a shared border between adjacent unit pixels <NUM>. As shown in <FIG>, at least a portion of a log transistor <NUM> can be formed between a second end <NUM> of an RDTI structure <NUM> that extends between different columns of unit pixels <NUM> within a pixel group <NUM>. Accordingly, embodiments of the present disclosure allow for the sharing of pixel group circuit <NUM> elements between unit pixels <NUM> within the same pixel group, while also allowing for isolation between those unit pixels <NUM>.

<FIG> is a plan view of a pixel configuration in accordance with a sixth exemplary embodiment of the present disclosure, and <FIG> is a cross section of a portion of the sixth exemplary embodiment taken along line A-A' in <FIG>. In this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by RFTI structures <NUM>. In addition, an interpixel group isolation structure <NUM> is provided that includes RFTI <NUM> and RDTI <NUM> structures. More particularly, the inter-pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion 1210a that extends between unit pixels <NUM> in adjacent rows that includes both RFTI <NUM> and RDTI <NUM> structures, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns and that includes both RFTI <NUM> and RDTI <NUM> structures. In the example of <FIG>, two segments of RFTI structure <NUM> extend horizontally from the RFTI structures <NUM> between pixel groups <NUM> in different columns of pixel groups <NUM>, and one segment of RDTI structure <NUM> extends horizontally between the two horizontal segments of RFTI structures <NUM>. In addition, two segments of RFTI structure <NUM> extend vertically from the RFTI structures <NUM> at the top and bottom of the pixel group <NUM>, with one vertical segment of RDTI structure <NUM> extending vertically between the two segments of RFTI structure <NUM>. The vertical segment of RDTI structure <NUM> also intersects the horizontal segment of RDTI structure <NUM> at the middle area of the pixel group.

As depicted in <FIG>, isolation between adjacent unit pixels <NUM> is provided. In particular, an RFTI structure <NUM> extends between at least some of a shared border between adjacent unit pixels <NUM>. Isolation between adjacent unit pixels <NUM> in a center area of the pixel group <NUM> is provided by RDTI structures <NUM>, enabling at least a portion of a node <NUM> at which the unit pixel transistors <NUM> are connected to the pixel group transmission transistor <NUM> and the pixel group overflow gate transistor <NUM> to be formed in the area where the two RDTI structures <NUM> within a pixel group <NUM> intersect. Accordingly, embodiments of the present disclosure allow for the sharing of pixel group circuit <NUM> elements between unit pixels <NUM> within the same pixel group, while also allowing for isolation between those unit pixels <NUM>.

<FIG> is a plan view of a pixel configuration in accordance with a seventh exemplary embodiment of the present disclosure, <FIG> is a cross section of a portion of the seventh exemplary embodiment taken along line A-A' in <FIG>, and <FIG> is a cross section of a portion of the seventh exemplary embodiment taken along line B-B' in <FIG>. In this embodiment, each pixel group <NUM> includes eight unit pixels <NUM>, with the unit pixels <NUM> disposed in four rows and two columns. In addition, the eight unit pixels <NUM> within a pixel group <NUM> share at least some circuit elements. A mix of separation structures <NUM> are applied to provide isolation between adjacent unit pixels <NUM>. In particular, the separation between the first and second rows of unit pixels <NUM> and between the third and fourth rows of unit pixels <NUM> is provided by two horizontal RFTI structures <NUM> that extend from vertical isolation structures <NUM> on either side of the pixel group <NUM>, with a horizontal RDTI structure <NUM> extending between the two horizontal RFTI structures <NUM> in each case. The separation between the second and third rows of unit pixels <NUM> is provided entirely by an RDTI structure <NUM>. The separation between the first and second columns of unit pixels <NUM> is provided entirely by an RDTI structure <NUM>.

As shown in <FIG>, and <FIG>, isolation between adjacent unit pixels <NUM> within a pixel group <NUM> is provided by a mix of RFTI <NUM> and RDTI <NUM> structures. In addition, circuit elements are shared between unit pixels, and at least portions of various circuit elements can be formed in areas of the substrate <NUM> that are at least partially located between an end <NUM> of an RDTI structure <NUM> and a surface <NUM> of the substrate <NUM>. For example, at least portions of two log transistors <NUM> and <NUM> can be formed between an end of an RDTI structure <NUM> and a second surface <NUM> of the substrate <NUM>, and at least a portion of a reset transistor <NUM> can be formed between an end of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. Accordingly, isolation is provided, while making more area available for photoelectric conversion elements <NUM> as compared to prior configurations.

<FIG> is a plan view of a pixel configuration in accordance with an eighth exemplary embodiment of the present disclosure, and <FIG> is a cross section of a portion of the eighth exemplary embodiment taken along line A-A' in <FIG>. In this embodiment, each pixel group <NUM> includes eight unit pixels <NUM>, with the unit pixels <NUM> disposed in four rows and two columns. In addition, the eight unit pixels <NUM> within a pixel group <NUM> share at least some circuit elements. A mix of RFTI <NUM> and RDTI <NUM> separation structures are applied to provide isolation between adjacent unit pixels <NUM>. In particular, the separation between the first and second rows of unit pixels <NUM> and between the third and fourth rows of unit pixels <NUM> is provided by two horizontal RFTI structures <NUM> that extend from vertical isolation structures <NUM> on either side of the pixel group <NUM>, with a horizontal RDTI structure <NUM> extending between the two horizontal RFTI structures <NUM> in each case. The separation between the second and third rows of unit pixels <NUM> is provided entirely by an RDTI structure <NUM>. The separation between the first and second columns of unit pixels <NUM> is provided entirely by an RDTI structure <NUM>. Accordingly, the disposition of separation structures is similar to that of the seventh embodiment. However, there are differences in the locations of elements of the shared circuit between the seventh and eighth example embodiments.

As shown in <FIG>, isolation between adjacent unit pixels <NUM> within a pixel group <NUM> is provided by a mix of RFTI <NUM> and RDTI <NUM> structures. In addition, circuit elements are shared between unit pixels, and at least portions of various circuit elements can be formed in areas of the substrate <NUM> that are at least partially located between an end <NUM> of an RDTI structure <NUM> and a surface <NUM> of the substrate <NUM>. For example, at least portions of the pixel group overflow gate transistor <NUM> can be at least partially formed in an area between a second end <NUM> of an RDTI structure <NUM> and a second surface <NUM> of the substrate <NUM>. Accordingly, isolation is provided, while making more area available for photoelectric conversion elements <NUM> as compared to prior configurations.

<FIG> is a plan view of a pixel configuration in accordance with a ninth exemplary embodiment of the present disclosure, and <FIG> is a cross section of a portion of the ninth exemplary embodiment taken along line A-A' in <FIG>. In this embodiment, each pixel group <NUM> includes eight unit pixels <NUM>, with the unit pixels <NUM> disposed in four rows and two columns. In addition, the eight unit pixels <NUM> within a pixel group <NUM> share at least some circuit elements. A mix of RFTI <NUM> and RDTI <NUM> separation structures are applied to provide isolation between adjacent unit pixels <NUM>. In particular, the separation between the first and second rows of unit pixels <NUM> and between the third and fourth rows of unit pixels <NUM> is provided by two horizontal RFTI structures <NUM> that extend from vertical isolation structures <NUM> on either side of the pixel group <NUM>, with a horizontal RDTI structure <NUM> extending between the two horizontal RFTI structures <NUM> in each case. The separation between the second and third rows of unit pixels <NUM> is provided entirely by an RDTI structure <NUM>. The separation between the first and second columns of unit pixels <NUM> is provided by two vertical RFTI structures that extend from horizontal isolation structures <NUM> at the top and bottom boundaries of the pixel group <NUM> for a distance that is less than an entire vertical extent of a top row and a bottom row of unit pixels <NUM> respectively, and an RDTI structure <NUM> that extends vertically between the two vertical RFTI structures <NUM>. Accordingly, the disposition of separation structures is similar to that of the seventh and eight embodiments. However, there are differences in the locations of elements of the shared circuit between this ninth example embodiment and the seventh and eighth example embodiments.

As shown in <FIG>, isolation between adjacent unit pixels <NUM> within a pixel group <NUM> is provided by a mix of RFTI <NUM> and RDTI <NUM> structures. In addition, circuit elements are shared between unit pixels, and at least portions of various circuit elements can be formed in areas of the substrate <NUM> that are at least partially located between an end <NUM> of an RDTI structure <NUM> and a surface <NUM> of the substrate <NUM>. For example, at least portions of some or all of the select <NUM>, amplification <NUM>, reset <NUM>, transfer gate <NUM>, overflow gate <NUM>, first and second log <NUM> and <NUM>, and first and second amplification <NUM> and <NUM> transistors can be at least partially formed in an area between a second end <NUM> of an RDTI structure <NUM> and a second surface <NUM> of the substrate <NUM>. Accordingly, isolation is provided, while making more area available for photoelectric conversion elements <NUM> as compared to prior configurations.

<FIG> is a plan view of a portion of a pixel array unit <NUM>, and <FIG> is a cross section taken along line A-A' in <FIG>, illustrating a pixel group <NUM> configuration <NUM> in accordance with a tenth exemplary embodiment of the present disclosure. This embodiment is similar to the first example embodiment, except that each pixel group <NUM> includes pixels <NUM> that are sensitive to the same color. As in the first example, and has can be applied to other embodiments of the present disclosure, the groups <NUM> of unit pixels <NUM> are defined and are separated from one another by full thickness dielectric trench isolation (RFTI) structures <NUM>. Within each pixel group <NUM>, unit pixels <NUM> are separated from one another by an inter-pixel group isolation structure <NUM> in the form of deep trench isolation (RDTI) structures <NUM>. The inter pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion 1210a that extends between unit pixels <NUM> in adjacent rows, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns. More particularly, the pixel configuration <NUM> features RDTI structures <NUM> along the entire extent of the boundaries between adjacent unit pixels <NUM> within each pixel group <NUM>, with a first RDTI structure 1212a extending between adjacent rows of unit pixels <NUM> within each pixel group <NUM>, and a second RDTI structure 1212b extending between adjacent columns of unit pixels <NUM> within each pixel group <NUM>.

As illustrated in <FIG>, each unit pixel <NUM> within the same pixel group <NUM> includes a color filter <NUM> of the same color. In addition, as illustrated in <FIG>, the pixel groups <NUM> can be arrayed so that the pixel array unit <NUM> is configured as a Bayer or other imaging sensor pattern on a pixel group <NUM> basis, rather than on a per unit pixel <NUM> basis.

As shown in <FIG>, isolation between adjacent unit pixels <NUM> within a pixel group <NUM> is provided by RDTI <NUM> structures. In addition, circuit elements are shared between unit pixels, and at least portions of various circuit elements can be formed in areas of the substrate <NUM> that are at least partially located between an end <NUM> of an RDTI structure <NUM> and a surface <NUM> of the substrate <NUM>. For example, at least a portion of a log transistor <NUM> of the address event detection readout circuit <NUM> for the pixel group circuit <NUM> can be formed between the second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. As a further example, at least a portion of a drain/source region of amplification transistors <NUM> and <NUM> can be formed in an area between the second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. As still another example, at least a portion of a node <NUM> at which the unit pixel transistors <NUM> are connected to the pixel group transmission transistor <NUM> and the pixel group overflow gate transistor <NUM> can be formed between the second ends <NUM> of two intersecting RDTI structures <NUM> and the second surface <NUM> of the substrate <NUM>.

<FIG> is a plan view of a pixel configuration in accordance with an eleventh exemplary embodiment of the present disclosure, and <FIG> is a cross section of a portion of the eleventh exemplary embodiment taken along line A-A'. This embodiment is similar to the fifth example embodiment, except that each pixel group <NUM> includes pixels <NUM> that are sensitive to the same color. Accordingly, in this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by RFTI structures <NUM>. In addition, an interpixel group isolation structure <NUM> is provided that includes RFTI <NUM> and RDTI <NUM> structures. More particularly, the inter-pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion that extends between unit pixels <NUM> in adjacent rows that includes both RFTI <NUM> and RDTI <NUM> structures, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns and that includes both RFTI <NUM> and RDTI <NUM> structures. In the example of <FIG>, two segments of RFTI structure <NUM> extend horizontally from the RFTI structures <NUM> between pixel groups <NUM> in different columns of pixel groups <NUM>, and one segment of RDTI structure <NUM> extends horizontally between the two horizontal segments of RFTI structures <NUM>. Two segments of RDTI structures <NUM> extend vertically from the RFTI structures <NUM> at the top and bottom of the pixel group <NUM>, with one vertical segment of RFTI structure <NUM> extending from the vertical RDTI structures <NUM>. Each vertical segment of RFTI structure <NUM> within the pixel group <NUM> is separated from one another by a vertical segment of RDTI structure <NUM> at a middle area of the pixel group <NUM>. The vertical segment of RDTI structure <NUM> also intersects the horizontal segment of RDTI structure <NUM> at the middle area of the pixel group.

As depicted in <FIG>, isolation between adjacent unit pixels <NUM> is provided, while also allowing at least portions of various circuit elements to be formed between a second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. For example, as shown in <FIG>, at least a portion of a log transistor <NUM> can be formed between a second end <NUM> of an RDTI structure <NUM> that extends between different columns of unit pixels <NUM> within a pixel group <NUM>. Accordingly, embodiments of the present disclosure allow for the sharing of pixel group circuit <NUM> elements between unit pixels <NUM> within the same pixel group, while also allowing for isolation between those unit pixels <NUM>.

The pixel group circuit <NUM> generally includes a light receiving unit <NUM> having a plurality of photoelectric conversion units <NUM>. As an example, but without limitation, the photoelectric conversion units <NUM> can include photodiodes. In this example, one photoelectric conversion unit <NUM> is included in each unit pixel <NUM>, although other configurations are possible. The pixel group circuit <NUM> also includes a pixel imaging signal generation readout circuit <NUM> and an address event detection readout circuit <NUM>. The pixel imaging signal generation readout circuit <NUM> and the address event detection readout circuit <NUM> can be configured in the same way as or similarly to the readout circuits <NUM> and <NUM> of <FIG> and <FIG>.

The pixel group circuit <NUM> differs from the pixel group circuit <NUM> of <FIG> in that the pixel group circuit <NUM> eliminates the pixel group transmission transistor <NUM> and the pixel group overflow gate transistor <NUM>. Instead, the pixel group circuit <NUM> includes a light receiving unit <NUM> having a unit pixel transmission transistor <NUM> and a unit pixel overflow gate transistor <NUM> for each photoelectric conversion unit <NUM> of each unit pixel <NUM> within the pixel group <NUM>. According to this arrangement, each photoelectric conversion unit <NUM> of each unit pixel <NUM> can be selectively connected to the imaging signal generation readout circuit <NUM> through operation of a selected pixel's unit pixel transmission transistor <NUM>, and to the address event detection readout circuit <NUM> through operation of the selected pixel's unit pixel overflow gate transistor <NUM>.

In an imaging mode, the unit pixel transmission transistor <NUM> associated with each selected photoelectric conversion unit <NUM> is placed in a conductive state in order to operatively connect the selected photoelectric conversion unit <NUM> to the floating diffusion <NUM> of the pixel imaging signal generation readout circuit <NUM>. In an event detection or dynamic vision sensor (DVS) mode, the unit pixel overflow gate transistor <NUM> associated with each selected photoelectric conversion unit <NUM> is placed in a conductive state in order to operatively connect the selected photoelectric conversion unit <NUM> to the address event detection readout circuit <NUM>. In a typical operating condition, in the imaging mode a single one of the photoelectric conversion units <NUM> is operable at any one time to provide a signal to the pixel imaging signal generation readout circuit <NUM>, while in a DVS mode one, some, or all of the photoelectric conversion units <NUM> are operable at any one time to provide a signal to the address event detection readout circuit <NUM>.

Although charge from a single photoelectric conversion unit <NUM> is passed to the pixel imaging signal generation readout circuit <NUM> in a typical imaging operation, other modes in which signals from multiple photoelectric conversion units <NUM>, corresponding to multiple unit pixels <NUM> are passed to the pixel imaging signal generation readout circuit <NUM> are possible. As can be appreciated by one of skill in the art after consideration of the present disclosure, the unit pixel overflow gate transistors <NUM> remain closed during an imaging operation, and the unit pixel transmission transistors <NUM> remain closed during an event detection mode. As can further be appreciated by one of skill in the art after consideration of the present disclosure, the operation of the pixel image signal generation circuit <NUM> can be triggered by the detection of an event by the address event detection readout circuit <NUM> for the pixel group <NUM>.

Accordingly, the circuit configuration <NUM> of <FIG> is an example of an arrangement in which a plurality of unit pixels <NUM> of an imaging device <NUM> are capable of performing both event detection and imaging operations, and in which the photoelectric conversion units <NUM> of the respective unit pixels <NUM> share elements of the event detection <NUM> and pixel imaging signal generation readout <NUM> circuits.

<FIG> is a plan view of a pixel configuration <NUM> in accordance with a twelfth exemplary embodiment of the present disclosure, and <FIG> is a cross section of a portion of the twelfth exemplary embodiment taken along line A-A' in <FIG>. The pixel configuration <NUM> is similar to the pixel configuration <NUM> of <FIG>, except for the inclusion of a unit pixel transmission transistor <NUM> and a unit pixel overflow gate transistor <NUM> for the photoelectric conversion unit <NUM> of each unit pixel <NUM>, and the exclusion of a pixel group transmission transistor <NUM> and an pixel group overflow gate transistor <NUM>. Accordingly, in this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by full thickness dielectric trench isolation (RFTI) structures <NUM>. Within each pixel group <NUM>, unit pixels <NUM> are separated from one another by an inter-pixel group isolation structure <NUM> in the form of deep trench isolation (RDTI) structures <NUM>. The inter pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion 1210a that extends between unit pixels <NUM> in adjacent rows, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns. More particularly, the pixel configuration <NUM> features RDTI structures <NUM> along the entire extent of the boundaries between adjacent unit pixels <NUM> within each pixel group <NUM>, with a first RDTI structure 1212a extending between adjacent rows of unit pixels <NUM> within each pixel group <NUM>, and a second RDTI structure 1212b extending between adjacent columns of unit pixels <NUM> within each pixel group <NUM>. Although in this example four pixel groups <NUM> in a 2x2 array in which each of the pixel groups <NUM> includes four unit pixels <NUM> in a 2x2 sub-array or group array pattern are shown, other configurations are possible.

In accordance with embodiments of the present disclosure, and as illustrated in <FIG>, RFTI structures <NUM> extend through the entire thickness of a substrate <NUM> in which the photodiodes <NUM> of the unit pixels <NUM> are formed. That is, the RFTI structures <NUM> extend from at least a first, light incident surface <NUM>, to a second, non-light incident surface <NUM>, of the substrate <NUM>. The RDTI structures <NUM> extend from a first end <NUM> at or above the first surface <NUM> to a second end <NUM> that is formed towards the second surface <NUM> of the substrate <NUM>. In particular, the RDTI structures <NUM> extend for distance that is less than a thickness of the substrate <NUM>, and thus do not reach the second surface <NUM>. Accordingly, substrate <NUM> material remains between the second end <NUM> of the RDTI structures <NUM> and the second surface <NUM> of the substrate <NUM>.

The circuit elements associated with each pixel group <NUM> in the example pixel group configuration <NUM> of <FIG> may be the same as or similar to those illustrated in the pixel group circuit <NUM> of <FIG>. In accordance with embodiments of the present disclosure, one or more circuit elements, such as transistor, conductor, or other elements of a pixel group circuit <NUM>, are at least partially formed or located between the second end <NUM> of one or more of the RDTI structures <NUM> within an area of the pixel group <NUM> and the second surface <NUM> of the substrate <NUM>. For instance, in the example of <FIG> and 242B, at least a portion of a log transistor <NUM> and/or an amplification transistor <NUM> of the address event detection readout circuit <NUM> for the pixel group circuit <NUM> can be formed between the second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. As another example, at least portions of nodes <NUM> and <NUM> through which the unit pixel transistors <NUM> are connected to the pixel imaging signal generation readout circuit <NUM> and the address event detection readout circuit <NUM> respectively can be formed between the second end <NUM> of an RDTI structure <NUM> and the second surface <NUM>. As still another example, at least portions of at least one of a node <NUM> or <NUM> can be formed between the second ends <NUM> of two intersecting RDTI structures <NUM> and the second surface <NUM> of the substrate <NUM>.

Accordingly, embodiments of the present disclosure can provide suitable isolation between pixel groups <NUM> using RFTI structures <NUM>, and between unit pixels <NUM> within a pixel group <NUM> using RDTI structures <NUM>, while providing a more favorable ratio of a total area of a pixel group <NUM> to areas of the photoelectric conversion units <NUM> of the unit pixels <NUM> within the pixel group <NUM> by facilitating the sharing of pixel group circuit <NUM> elements, and by enabling the formation of at least portions of elements of the pixel group circuit <NUM> in areas between an end of an RDTI structure <NUM> and a surface of the substrate <NUM>.

<FIG> is a plan view of a pixel configuration in accordance with a thirteenth exemplary embodiment of the present disclosure, <FIG> is a cross section of a portion of the thirteenth exemplary embodiment taken along line A-A' in <FIG>, and <FIG> is a cross section of another portion of the thirteenth exemplary embodiment taken along line B-B' in <FIG>. In this example, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by RFTI structures <NUM>. In addition, an interpixel group isolation structure <NUM> is provided that includes RFTI <NUM> and RDTI <NUM> structures. More particularly, the inter-pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion that extends between unit pixels <NUM> in adjacent rows that includes both RFTI <NUM> and RDTI <NUM> structures, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns and that includes both RFTI <NUM> and RDTI <NUM> structures. In the example of <FIG>, two segments of RFTI structure <NUM> extend horizontally from the RFTI structures <NUM> between pixel groups <NUM> in different columns of pixel groups <NUM>, and one segment of RDTI structure <NUM> extends horizontally between the two horizontal segments of RFTI structures <NUM>. Two segments of RDTI structures <NUM> extend vertically from the RFTI structures <NUM> at the top and bottom of the pixel group <NUM>, with one vertical segment of RFTI structure <NUM> extending from the vertical RDTI structures <NUM>. Each vertical segment of RFTI structure <NUM> within the pixel group <NUM> is separated from one another by a vertical segment of RDTI structure <NUM> at a middle area of the pixel group <NUM>. The vertical segment of RDTI structure <NUM> also intersects the horizontal segment of RDTI structure <NUM> at the middle area of the pixel group.

This exemplary embodiment can include a pixel group circuit that is configured the same as or similarly to the pixel group circuit <NUM> of <FIG>. As depicted in <FIG>, <FIG>, isolation between adjacent unit pixels <NUM> is provided, while also allowing at least portions of various circuit elements to be formed between a second end <NUM> of an RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. For example, as shown in <FIG>, an RFTI structure <NUM> extends between at least some of a shared border between adjacent unit pixels <NUM>. As shown in <FIG>, an area is available between a second end <NUM> of an RDTI structure <NUM> that extends between different columns of unit pixels <NUM> within a pixel group <NUM> and the second surface <NUM> of the substrate <NUM>. In addition, at least portions of an amplification transistor <NUM> can be formed between the second end <NUM> of a RDTI structure <NUM> and the second surface <NUM> of the substrate <NUM>. Accordingly, embodiments of the present disclosure allow for the sharing of pixel group circuit <NUM> elements between unit pixels <NUM> within the same pixel group, while also allowing for isolation between those unit pixels <NUM>.

<FIG> is a plan view of a pixel configuration in accordance with a fourteenth exemplary embodiment of the present disclosure, and <FIG> is a cross section of a portion of the fourteenth exemplary embodiment taken along line A-A' of <FIG>. In this embodiment, each pixel group <NUM> includes eight unit pixels <NUM>, with the unit pixels <NUM> disposed in four rows and two columns. In addition, the eight unit pixels <NUM> with a pixel group <NUM> share at least some circuit elements. In addition, each photoelectric conversion element <NUM> of each unit pixel <NUM> is connected to a unit pixel transmission transistor <NUM> and a unit pixel overflow gate transistor <NUM>. A mix of separation structures are applied to provide isolation between adjacent unit pixels <NUM>. In particular, the separation between the first and second rows of unit pixels <NUM> and between the third and fourth rows of unit pixels <NUM> is provided by two horizontal RFTI structures <NUM> that extend from vertical isolation structures <NUM> on either side of the pixel group <NUM>, with a horizontal RDTI structure <NUM> extending between the two horizontal RFTI structures <NUM> in each case. The separation between the second and third rows of unit pixels <NUM> is provided entirely by an RDTI structure <NUM>. The separation between the first and second columns of unit pixels <NUM> is provided entirely by an RDTI structure <NUM>.

As shown in <FIG>, isolation between adjacent unit pixels <NUM> within a pixel group <NUM> is provided by a mix of RFTI <NUM> and RDTI <NUM> structures. In addition, circuit elements are shared between unit pixels, and at least portions of various circuit elements can be formed in areas of the substrate <NUM> that are at least partially located between an end <NUM> of an RDTI structure <NUM> and a surface <NUM> of the substrate <NUM>. For example, at least portions of an amplification transistor <NUM> and/or at least portions of a reset transistor <NUM> can be formed between an end of an RDTI structure <NUM> and a second surface <NUM> of the substrate <NUM>. Accordingly, isolation is provided, while making more area available for photoelectric conversion elements <NUM> as compared to prior configurations.

<FIG> is a plan view of a pixel configuration in accordance with a fifteenth exemplary embodiment of the present disclosure, <FIG> is a cross section of a portion of the fifteenth exemplary embodiment taken from area A of <FIG>, and <FIG> is a cross section of another portion of the fifteenth exemplary embodiment taken from area B of <FIG>. The arrangement of pixel groups <NUM> and of unit pixels <NUM> within the respective pixel groups <NUM> can be the same as or similar to the arrangement depicted in <FIG>. Accordingly, groups <NUM> of unit pixels <NUM> are defined and are separated from one another by full thickness dielectric trench isolation (RFTI) structures <NUM>. Within each pixel group <NUM>, unit pixels <NUM> are separated from one another by an inter-pixel group isolation structure <NUM> in the form of deep trench isolation (RDTI) structures <NUM>. The inter pixel group isolation structure <NUM> within a pixel group <NUM> can include a horizontal portion 1210a that extends between unit pixels <NUM> in adjacent rows, and a vertical portion 1210b that extends between unit pixels <NUM> in adjacent columns. More particularly, the pixel configuration <NUM> features RDTI structures <NUM> along the entire extent of the boundaries between adjacent unit pixels <NUM> within each pixel group <NUM>, with a first RDTI structure 1212a extending between adjacent rows of unit pixels <NUM> within each pixel group <NUM>, and a second RDTI structure 1212b extending between adjacent columns of unit pixels <NUM> within each pixel group <NUM>. Although in this example four pixel groups <NUM> in a 2x2 array in which each of the pixel groups <NUM> includes four unit pixels <NUM> in a 2x2 sub-array or group array pattern are shown, other configurations are possible.

In accordance with embodiments of the present disclosure, and as illustrated in <FIG>, the RFTI structures <NUM> extend through the entire thickness of a substrate <NUM>, and the RDTI structures <NUM> extend from a first end <NUM> at or above the first surface <NUM> to a second end <NUM> that is formed towards the second surface <NUM> of the substrate <NUM>. In the illustrated embodiment, the RFTI <NUM> and RDTI <NUM> structures have a polysilicon core <NUM> that is separated from the substrate <NUM> by a dielectric <NUM>. As an example, but without limitation, the dielectric <NUM> may be in the form of an oxide or a nitride material. Moreover, the use of isolation structures <NUM> and <NUM> with polysilicon cores <NUM> as disclosed in herein can be applied to any of the other pixel group <NUM> configurations and circuit configurations of embodiments of the present disclosure.

<FIG> is a plan view of a pixel configuration in accordance with a sixteenth exemplary embodiment of the present disclosure, <FIG> is a cross section of a portion of the sixteenth exemplary embodiment, and <FIG> is a cross section of another portion of the sixteenth exemplary embodiment. The arrangement of pixel groups <NUM> and of unit pixels <NUM> within the respective pixel groups <NUM> can be the same as or similar to the arrangement depicted in <FIG> and <FIG>. However, in this sixteenth exemplary embodiment, and as shown in <FIG> and <FIG>, the RFTI <NUM> and RDTI structures <NUM> include a tungsten core <NUM> within a dielectric inner layer <NUM>, which is in turn separated from the substrate <NUM> by a passivation layer <NUM>. The use of isolation structures <NUM> and <NUM> with tungsten cores <NUM> as disclosed herein can be applied to any of the other pixel group <NUM> configurations and circuit configurations of embodiments of the present disclosure. Moreover, different isolation structure <NUM> and <NUM> materials can be used in a single pixel array unit <NUM>. For example, some isolation structures <NUM> and <NUM> can include a dielectric core, some isolation structures <NUM> and <NUM> can include a polysilicon core, and some isolation structures can include a tungsten core.

<FIG> is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a moving body control system to which the technology according to the present disclosure is applicable.

A vehicle control system <NUM> includes a plurality of electronic control units which are connected to each other through a communication network <NUM>. In the example illustrated in <FIG>, the vehicle control system <NUM> includes a drive system control unit <NUM>, a body system control unit <NUM>, a vehicle exterior information detection unit <NUM>, a vehicle interior information detection unit <NUM>, and an integrated control unit <NUM>. In addition, as a functional configuration of the integrated control unit <NUM>, a microcomputer <NUM>, a voice and image output unit <NUM>, and an in-vehicle network I/F (interface) <NUM> are illustrated in the drawing.

The drive system control unit <NUM> controls an operation of a device relating to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit <NUM> functions as a control device of a drive force generation device such as an internal combustion engine and a drive motor which generate a drive force of the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, a steering mechanism that adjusts a steering angle of the vehicle, and a braking device that generates a braking force of the vehicle, and the like.

The body system control unit <NUM> controls an operation of various devices which are mounted to a vehicle body in accordance with various programs. For example, the body system control unit <NUM> functions as a control device of a keyless entry system, a smart key system, a power window device, and various lamps such as a head lamp, a back lamp, a brake lamp, a blinker, and a fog lamp. In this case, an electric wave that is transmitted from a portable device that substitutes for a key, or signals of various switches can be input to the body system control unit <NUM>. The body system control unit <NUM> receives input of the electric wave or the signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.

The vehicle exterior information detection unit <NUM> detects information regarding an outer side of the vehicle on which the vehicle control system <NUM> is mounted. For example, an imaging unit <NUM> is connected to the vehicle exterior information detection unit <NUM>. The vehicle exterior information detection unit <NUM> allows the imaging unit <NUM> to capture a vehicle exterior image, and receives the captured image. The vehicle exterior information detection unit <NUM> may perform object detection processing of a person, a vehicle, an obstacle, a sign, a character on a load, or the like or distance detection processing on the basis of the image that is received.

The imaging unit <NUM> is an optical sensor that receives light and outputs an electric signal corresponding to a light-reception amount. The imaging unit <NUM> may output the electric signal as an image or as distance measurement information. In addition, light received by the imaging unit <NUM> may be visible light, or invisible light such as infrared rays.

The vehicle interior information detection unit <NUM> detects vehicle interior information. For example, a driver state detection unit <NUM> that detects a driver state is connected to the vehicle interior information detection unit <NUM>. For example, the driver state detection unit <NUM> includes a camera that images a driver, and the vehicle interior information detection unit <NUM> may calculate the degree of fatigue or the degree of concentration of a driver on the basis of detection information that is input from the driver state detection unit <NUM>, or may determine whether or not the driver drowses.

The microcomputer <NUM> calculates a control target value of the drive force generation device, the steering mechanism, or the braking device on the basis of vehicle interior or exterior information that is acquired by the vehicle exterior information detection unit <NUM> or the vehicle interior information detection unit <NUM>, and can output a control command to the drive system control unit <NUM>. For example, the microcomputer <NUM> can perform a cooperative control to realize a function of an advanced driver assistance system (ADAS) which includes collision avoidance or impact mitigation of the vehicle, following travel based on an inter-vehicle distance, vehicle speed maintenance travel, vehicle collision alarm, vehicle lane deviation alarm, and the like.

In addition, the microcomputer <NUM> can perform a cooperative control for automatic driving and the like in which the vehicle autonomously travels without depending on an operation of a driver by controlling the drive force generation device, the steering mechanism, the braking device, and the like on the basis of information in the vicinity of the vehicle which is acquired by the vehicle exterior information detection unit <NUM> or the vehicle interior information detection unit <NUM>.

In addition, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the vehicle exterior information acquired by the vehicle exterior information detection unit <NUM>. For example, the microcomputer <NUM> can perform a cooperative control to realize glare protection such as switching of a high beam into a low beam by controlling the head lamp in correspondence with a position of a preceding vehicle or an oncoming vehicle which is detected by the vehicle exterior information detection unit <NUM>.

The voice and image output unit <NUM> transmits at least one output signal between a voice and an image to an output device capable of visually or aurally notifying a passenger in a vehicle or an outer side of the vehicle of information. In the example in <FIG>, as the output device, an audio speaker <NUM>, a display unit <NUM>, and an instrument panel <NUM> are exemplified. For example, the display unit <NUM> may include at least one of an on-board display or a head-up display.

<FIG> is a view illustrating an example of an installation position of the imaging unit <NUM>.

In <FIG>, as the imaging unit <NUM>, imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are provided.

For example, the imaging units <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are installed at positions such as a front nose, a side-view mirror, a rear bumper, a back door, and an upper side of a windshield in a vehicle room, of the vehicle <NUM>. The imaging unit <NUM> provided at the front nose, and the imaging unit <NUM> that is provided on an upper side of the windshield in a vehicle room mainly acquire images on a forward side of the vehicle <NUM>. The imaging units <NUM> and <NUM> which are provided in the side-view mirror mainly acquire images on a lateral side of the vehicle <NUM>. The imaging unit <NUM> that is provided in the rear bumper or the back door mainly acquires images on a backward side of the vehicle <NUM>. The imaging unit <NUM> that is provided on an upper side of the windshield in the vehicle room can be mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a vehicle lane, and the like.

Furthermore, <FIG> illustrates an example of a photographing range of the imaging units <NUM> to <NUM>. An image capturing range <NUM> represents an image capturing range of the imaging unit <NUM> that is provided in the front nose, image capturing ranges <NUM> and <NUM> respectively represent image capturing ranges of the imaging units <NUM> and <NUM> which are provided in the side-view mirrors, an image capturing range <NUM> represents an image capturing range of the imaging unit <NUM> that is provided in the rear bumper or the back door. For example, when a plurality of pieces of image data captured by the imaging units <NUM> to <NUM> are superimposed on each other, it is possible to obtain an overlooking image when the vehicle <NUM> is viewed from an upper side.

At least one of the imaging units <NUM> to <NUM> may have a function of acquiring distance information. For example, at least one of the imaging units <NUM> to <NUM> may be a stereo camera including a plurality of imaging elements, or may be an imaging element that includes pixels for phase difference detection.

For example, the microcomputer <NUM> can extract a three-dimensional object, which is a closest three-dimensional object, particularly, on a proceeding path of the vehicle <NUM> and travels in approximately the same direction as that of the vehicle <NUM> that travels at a predetermined velocity (for example, <NUM>/h or greater), as a preceding vehicle by obtaining distances to respective three-dimensional objects in the image capturing ranges <NUM> to <NUM> and a variation of the distances with the passage of time (relative velocity to the vehicle <NUM>) on the basis of the distance information obtained from the imaging units <NUM> to <NUM>. In addition, the microcomputer <NUM> can set a distance between vehicles to be secured in advance in front of the preceding vehicle to perform automatic brake control (also including a following stop control), an automatic acceleration control (also including a following acceleration control), and the like. As described above, it is possible to perform a cooperative control for automatic driving in which a vehicle autonomously travels without depending on an operation by a driver, and the like.

For example, the microcomputer <NUM> can extract three-dimensional object data relating to a three-dimensional object by classifying a plurality of pieces of the three-dimensional object data into data of a two-wheel vehicle, data of typical vehicle, data of a large-sized vehicle, data of pedestrian, and data of other three-dimensional objects such as an electric pole on the basis of the distance information obtained from the imaging units <NUM> to <NUM>, and can use the three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer <NUM> discriminates obstacles at the periphery of the vehicle <NUM> into an obstacle that is visually recognized by a driver of the vehicle <NUM> and an obstacle that is difficult for the driver to visually recognize. In addition, the microcomputer <NUM> determines collision risk indicating the degree of danger of collision with each of the obstacles. In a situation in which the collision risk is equal to or greater than a set value, and collision may occur, the microcomputer <NUM> can assist driving for collision avoidance by outputting an alarm to the driver through the audio speaker <NUM> or the display unit <NUM>, or by performing compulsory deceleration or avoidance steering through the drive system control unit <NUM>.

At least one of the imaging units <NUM> to <NUM> may be an infrared camera that detects infrared rays. For example, the microcomputer <NUM> can recognize a pedestrian by determining whether or not the pedestrian exists in images captured by the imaging units <NUM> to <NUM>. For example, the pedestrian recognition is performed by a procedure of extracting a specific point in the images captured by the imaging units <NUM> to <NUM> as an infrared camera, and a procedure of performing pattern matching processing for a series of specific points indicating a contour line of an object to determine whether or not the object is a pedestrian. When the microcomputer <NUM> determines that a pedestrian exists on the images captured by the imaging units <NUM> to <NUM>, and recognizes the pedestrian, the voice and image output unit <NUM> controls the display unit <NUM> to overlap and display a quadrangular contour line for emphasis on the pedestrian who is recognized. In addition, the voice and image output unit <NUM> may control the display unit <NUM> to display an icon indicating the pedestrian or the like at a desired position.

Claim 1:
An imaging device, comprising:
a pixel array unit (<NUM>), wherein the pixel array unit (<NUM>) includes a plurality of pixel groups (<NUM>), wherein each pixel group (<NUM>) includes:
a plurality of unit pixels (<NUM>), wherein the plurality of unit pixels (<NUM>) includes at least first and second unit pixels (<NUM>);
a plurality of photoelectric conversion regions (<NUM>), wherein each unit pixel (<NUM>) includes at least one of the photoelectric conversion regions (<NUM>);
a first readout circuit (<NUM>) selectively coupled to the plurality of photoelectric conversion regions (<NUM>);
a second readout circuit (<NUM>) selectively coupled to the plurality of photoelectric conversion regions (<NUM>) wherein the second readout circuit (<NUM>) is an address event detection readout circuit (<NUM>); and
an isolation structure (<NUM>), wherein the isolation structure (<NUM>) separates the first unit pixel (<NUM>) from the second unit pixel.