Patent Description:
Voltage reference circuits are used for providing a reliable reference voltage, which may further be used to control electronic circuits. For instance, a power management unit typically uses a voltage reference circuit in order to provide a reliable reference voltage, which can be used to generate direct current (DC) voltages and currents for biasing or supplying to an electronic circuit.

The reference voltage output by the voltage reference circuit should provide a stable voltage level which is not affected or minimally affected by parameter variations, such as temperature variations or variations in supply voltage to the reference voltage circuit.

In addition, the voltage reference circuit should be able to consume very small power levels. In particular, the voltage reference circuit may be used in small devices, such as Internet of Things (IoT) devices that may be almost exclusively in a sleep mode and only awake for brief moments of time. Thus, power consumption of such devices is mainly based on the power consumed during sleep mode. The voltage reference circuit may however be always-on and therefore the power consumption of the voltage reference circuit may be of huge importance.

Further, a compact architecture of the voltage reference circuit is advantageous in ensuring that the voltage reference circuit requires only a small area when being arranged in small devices. Also, a compact architecture may contribute to the voltage reference circuit consuming small power levels.

<FIG> illustrates a known two-transistor (2T) voltage reference circuit <NUM>. In the 2T voltage reference circuit, a zero threshold or native n-type metal-oxide-semiconductor (nMOS) transistor <NUM> is arranged with a gate terminal connected to ground and on top of a thick oxide nMOS transistor <NUM>. This provides a very compact voltage reference circuit. However, the 2T voltage reference circuit may be susceptible to variations in supply voltage such that the output reference voltage may vary based on variations in supply voltage.

In <NPL>, a voltage reference circuit is described for providing an improved insensitivity to supply voltage. However, the voltage reference circuit uses several additional transistors increasing complexity and power consumption of the voltage reference circuit.

The native nMOS transistor as used in the 2T voltage reference circuit can be formed without specially grown oxide, using only a natural thin oxide film that may be formed over silicon during processing of other layers when manufacturing transistors. However, native nMOS transistors may not be available in all transistor manufacturing technologies. For instance, when using fully-depleted silicon-on-insulator (FDSOI) technology, only native p-type metal-oxide-semiconductor (pMOS) transistors may be available. Further, pMOS and nMOS transistors may not be available on a common substrate, such that the 2T voltage reference circuit shown in <FIG> may not be available in such technology.

<CIT> discloses a reference voltage circuit that includes a first output terminal from which a first reference voltage is supplied; a first MOS transistor of a depletion type, the first MOS transistor containing a drain connected to a power supply terminal, a gate connected to a ground terminal, and a source; a first voltage drop circuit including a first end connected to the source of the first MOS transistor and a second end connected to the first output terminal; and a second MOS transistor of a depletion type, the second MOS transistor containing a drain connected to the first output terminal, a gate connected to the ground terminal, and a source connected to the ground terminal.

<CIT> discloses a reference voltage generation circuit that includes: a first field-effect transistor that is an n channel-type field-effect transistor of a depletion-type, wherein one terminal of the first field-effect transistor is connected to a predetermined power source voltage; a second field-effect transistor including a concentrated n-type gate, wherein one terminal of the second field-effect transistor is connected to another terminal of the first field-effect transistor; and a third field-effect transistor including a concentrated p-type gate, wherein one terminal of the third field-effect transistor is connected to another terminal of the second field-effect transistor; wherein a gate of the first field-effect transistor is connected to a part where the first and the second field-effect transistors are connected, each substrate gate of the first and the third field-effect transistors is connected to a ground voltage, a gate and a substrate gate of the second field-effect transistor and a gate of the third field-effect transistor are connected to a connecting part where the second and the third field-effect transistors are connected, and a reference voltage is output from the connecting part.

The present invention relates to a voltage reference circuit according to claim <NUM>. Further features of this reference circuit are disclosed in the dependent claims,.

An objective of the present description is to provide a voltage reference circuit with a compact area and low power consumption, while providing an insensitivity to parameter variations, such as variations in supply voltage and/or temperature. A further objective is to provide a voltage reference circuit which does not require use of native nMOS transistors.

According to a first aspect, there is provided a voltage reference circuit comprising: a first transistor comprising a gate terminal, a source terminal, a drain terminal and a bulk terminal; a second transistor comprising a gate terminal, a source terminal, a drain terminal and a bulk terminal, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a reference voltage is output at an output node between the first transistor and the second transistor; a regulating transistor comprising a gate terminal, a source terminal, a drain terminal and a bulk terminal, wherein the regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein the bulk terminal of the regulating transistor is connected to the output node for compensating changes in the reference voltage at the output node to maintain a stable reference voltage level.

According to the first aspect, a regulating transistor is added to a voltage reference circuit having a first transistor and a second transistor. Hence, the voltage reference circuit may use only three transistors for providing a stable reference voltage level such that the voltage reference circuit may be very compact and may also consume ultra-low power.

The regulating transistor is configured with the bulk terminal connected to the output node such that the reference voltage is provided as feedback to the regulating transistor. This implies that any change in the reference voltage affects the bulk terminal of the regulating transistor such that the reference voltage can be maintained at a stable, unchanged reference voltage level.

The voltage reference circuit is able to provide a reference voltage level which has a high insensitivity to parameter variations. The voltage reference circuit can provide a high line regulation, such that the voltage reference circuit provides a stable reference voltage level (small change in output reference voltage) over a large range of supply voltage values. The voltage reference circuit can further provide good temperature characteristics, such that a low temperature coefficient (variation of the output reference voltage as a function of temperature) is provided.

The voltage reference circuit may be implemented using same type of transistors for the first transistor, the second transistor and the regulating transistor. In particular, the voltage reference circuit need not use any native transistor. This facilitates use of the voltage reference circuit in technologies for which native nMOS transistors are not readily available. On the other hand, the regulating transistor is configured with the bulk terminal connected to the output node such that a bulk terminal should be available. Thus, implementation of the voltage reference circuit in, for instance, FDSOI technology is possible.

It should be realized that although conventional complementary metal-oxide-semiconductor (CMOS) technology may not provide a bulk terminal providing an extra gate terminal for individually controlling transistors, the voltage reference circuit may be implemented in CMOS technology. For instance, the second transistor and the regulating transistor may be implemented as nMOS transistors associated with deep n-wells for providing bulk terminals of the nMOS transistors.

The definition that transistors are arranged in a stacked connection should be understood such that the transistors are connected in series for providing a common direction of current through the transistors in the voltage reference circuit. Thus, a current between drain and source through one transistor may continue between drain and source of the other transistor in the stacked connection. In other words, if the transistors are of same type, the transistors may be connected with drain of one transistor in the stacked connection connected to source of the other transistor in the stacked connection. If the transistors are of opposite type, the transistors may be connected with source of one transistor connected with source of the other transistor in the stacked connection.

Further, the transistors being arranged in stacked connection between two terminals (e.g., first transistor and second transistor are arranged in stacked connection between a terminal connected to ground and a terminal connected to supply voltage) implies that drain or source of one transistor is connected to one of the two terminals and drain or source of the other transistor is connected to the other of the two terminals.

As used herein, the term "connected" should be construed as comprising directly connected, such that no components are arranged between the terminals / devices that are connected.

According to an embodiment, the first transistor, the second transistor and the regulating transistor are n-type metal-oxide-semiconductor (nMOS) transistors, and wherein a drain terminal of the first transistor is connected to a source terminal of the second transistor and a drain terminal of the second transistor is connected to a source terminal of the regulating transistor, and wherein the output node is connected to the drain terminal of the first transistor and the source terminal of the second transistor.

It should however be realized that the first transistor may be a pMOS transistor instead in combination with the second transistor and the regulating transistor being nMOS transistors. In such case, a source terminal of the first transistor may be connected to the source terminal of the second transistor and the output node may be connected to the source terminal of the first transistor.

The drain terminal of the second transistor may thus be connected to the source terminal of the regulating transistor. Further, the source terminal of the second transistor is connected to the output node, which is further connected to the bulk terminal of the regulating transistor. This implies that the drain-to-source voltage of the second transistor (VDS2) is equal to a negative of the bulk-to-source voltage of the regulating transistor (VBS3), i.e., VDS2 = -VBS3. Thus, any fluctuation in parameters, such as change in temperature or supply voltage, causing VDS2 to change will result in the change being sensed by the bulk-to-source voltage of the regulating transistor VBS3 and being directly fed back to change VDS2 in an opposite direction. Thus, the drain current of the second transistor will change to bring the reference voltage at the output node back to an original value. Hence, a stable reference voltage level is maintained.

According to an embodiment, the gate terminal of the regulating transistor is connected to the source terminal of the regulating transistor.

This implies that a gate-to-source voltage of the regulating transistor VGS3 is zero (as the gate and source terminals are connected). Hence, drain current of the regulating transistor may be controlled only by bulk-to-source voltage of the regulating transistor VBS3.

This implies that feedback of the reference voltage to the bulk terminal of the regulating transistor may control the drain current of the regulating transistor and ensure that the stable reference voltage level is maintained.

According to an embodiment, the gate terminal of the second transistor is connected to the source terminal of the second transistor.

This implies that a gate-to-source voltage of the second transistor VGS2 is zero (as the gate and source terminals are connected). Hence, drain current of the second transistor may be controlled only by bulk-to-source voltage of the second transistor VBS2.

The bulk terminal of the second transistor may be connected to ground. This implies that the bulk-to-source voltage of the second transistor VBS2 is negative, since the source terminal is connected to the output node. In particular, the bulk-to-source voltage of the second transistor VBS2 is a negative of the reference voltage.

The second transistor may be configured to operate in saturation at a subthreshold region. If a drain-to-source voltage of the second transistor VDS2 is larger than <NUM>*VT (where VT is thermal voltage), drain current of the second transistor is controlled only by the negative bulk-to-source voltage of the second transistor VBS2. This implies that an extremely low drain current of the second transistor is generated. Hence, the voltage reference circuit may consume ultra-low power.

Further, since the gate-to-source voltage of the second transistor VGS2 is zero and the bulk-to-source voltage of the second transistor VBS2 is also constant (thanks to the bulk-to-source voltage being the negative of the reference voltage, which is maintained constant), the drain current of the second transistor is constant if the drain-to-source voltage is constant. With the drain-to-source voltage of the second transistor VDS2 being equal to a negative of the bulk-to-source voltage of the regulating transistor VBS3, the feedback from the regulating transistor may be used for maintaining the drain-to-source voltage of the second transistor VDS2 constant and ensuring that a constant drain current of the second transistor is provided.

According to an embodiment, the output node is connected to the gate terminal of the second transistor.

When the gate terminal of the second transistor is connected to the source terminal of the second transistor and the source terminal of the second transistor is also connected to the output node, it follows that the output node is connected to the gate terminal of the second transistor.

According to an embodiment, the gate terminal of the first transistor is connected to ground.

The gate and source terminals of the first transistor may further be connected and the drain and bulk terminals of the first transistor may also be connected and connected to the output node. This implies that the reference voltage at the output node corresponds to a bulk-to-source voltage of the first transistor VBS1.

According to another embodiment, the bulk terminal of the first transistor is connected to ground.

The bulk and source terminals of the first transistor may further be connected and the drain and gate terminals of the first transistor may also be connected and connected to the output node. This implies that the reference voltage at the output node corresponds to a gate-to-source voltage of the first transistor VGS1.

With all parameters (size, etc.) of the transistors being equal, the voltage reference circuit having the gate terminal of the first transistor connected to ground may provide a higher reference voltage compared to the voltage reference circuit having the bulk terminal of the first transistor connected to ground. Hence, a connection of the first transistor may be selected in design of the voltage reference circuit depending on a desired reference voltage level to be output.

According to an embodiment, the first transistor, the second transistor and the regulating transistor are input/output transistors.

An integrated circuit may comprise input/output transistors and core transistors. Core transistors may have a relatively thin gate oxide layer and are typically used for high speed operations which may be used internally in the integrated circuit. In comparison to core transistors, input/output transistors may have a relatively thick gate oxide layer and are typically used for communication with external devices and, hence, the transistors may be referred to as input/output transistors. Thus, the first transistor, the second transistor and the regulating transistor being input/output transistors should be construed as the transistors being a particular type of transistor within an integrated circuit rather than the transistors necessarily being arranged to communicate with any external device.

The input/output transistors have a low gate leakage current. This implies that the gate leakage current may be negligible compared to drain current of the transistors. The first transistor, the second transistor and the regulating transistor may further be connected such that an equal drain current is provided through all the transistors. This implies that the current through the transistors may be accurately controlled for ensuring that a stable reference voltage is maintained.

Further, using input/output transistors for the second transistor and the regulating transistor compared to using native transistors implies that an improved temperature insensitivity is provided. Native transistors sharing the same substrate imply that parasitic p-n junction diodes are formed between the substrate and the source terminals of the native transistors. At high temperatures, significant reverse-biased leakage current may occur which may affect the output reference voltage. However, using input/output transistors with separate bulk terminals such leakage current may be avoided.

According to an embodiment, an aspect ratio of the regulating transistor equals an aspect ratio of the second transistor.

This may imply that the circuit is easy to manufacture as the transistors may be identical.

Further, the behavior of the second transistor and the regulating transistor may be identical based on having the same aspect ratios. With equal drain currents flowing through the transistors, voltage levels may be easily controlled when the aspect ratio is equal.

The aspect ratio may be defined as a width of a channel of the transistor divided by a length of the channel.

According to a second aspect, there is provided a power management unit comprising the voltage reference circuit according to any one of the preceding claims, the power management unit being configured to produce a direct current, DC, voltage based on the reference voltage.

Embodiments mentioned in relation to the second aspect are largely compatible with the first aspect.

Power management units typically provide DC voltages and currents for supplying to an electronic circuit. Thanks to the voltage reference circuit providing a stable reference voltage level, the power management unit may also provide reliable supply voltages to electronic circuits connected to the power management unit.

Further, the voltage reference circuit may provide a low power consumption and a compact architecture such that the power management unit may also be compact and provided with low power consumption.

The solutions described in the present description can be applied in numerous electronic circuitry devices and applications.

According to a third aspect, there is provided a neural sensing apparatus comprising the power management unit according to the second aspect.

Effects and features of this third aspect are largely analogous to those described above in connection with the first and second aspects. Embodiments mentioned in relation to the third aspect are largely compatible with the first and second aspects.

For a neural sensing apparatus, such as a neural probe, it is particularly advantageous if the apparatus is small, stable and/or power efficient. Thus, the power management unit utilizing the voltage reference circuit may be particularly advantageous to use in the neural sensing apparatus.

The above, as well as additional objects, features, and advantages of the present inventive concept, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings.

Referring now to <FIG>, a voltage reference circuit <NUM> according to a first embodiment will be described. The voltage reference circuit <NUM> comprises a first transistor <NUM>, a second transistor <NUM> and a regulating transistor <NUM>.

Each of the first transistor <NUM>, the second transistor <NUM> and the regulating transistor <NUM> may be a n-type metal-oxide-semiconductor (nMOS) transistor and the description below is based on the transistors being nMOS transistors. However, it should be realized that the first transistor <NUM> may instead be a p-type metal-oxide-semiconductor (pMOS) transistor. In such case, source and drain terminals of the transistor should switch places with each other.

Each of the first transistor <NUM>, the second transistor <NUM> and the regulating transistor <NUM> may comprise four terminals, a source terminal <NUM>, <NUM>, <NUM>, a drain terminal <NUM>, <NUM>, <NUM>, a gate terminal <NUM>, <NUM>, <NUM>, and a bulk terminal <NUM>, <NUM>, <NUM>. Voltage levels on the gate terminal and the bulk terminal control drain current of the transistors <NUM>, <NUM>, <NUM>.

The first transistor <NUM> and the second transistor <NUM> are arranged in a stacked connection with the drain terminal <NUM> of the first transistor <NUM> connected to the source terminal <NUM> of the second transistor <NUM>. The source terminal <NUM> of the first transistor <NUM> may further be connected to ground and the drain terminal <NUM> of the second transistor <NUM> may be connected to a supply voltage (via the regulating transistor <NUM>).

The second transistor <NUM> and the regulating transistor <NUM> are also arranged in a stacked connection with the drain terminal <NUM> of the second transistor <NUM> connected to the source terminal <NUM> of the regulating transistor <NUM>. The source terminal <NUM> of the second transistor <NUM> may further be connected to ground (via the first transistor <NUM>) and the drain terminal <NUM> of the regulating transistor <NUM> may be connected to the supply voltage.

The first transistor <NUM> and the second transistor <NUM> being in a stacked connection and the second transistor <NUM> and the regulating transistor <NUM> also being in a stacked connection implies that a current may flow between the supply voltage and ground through all transistors <NUM>, <NUM>, <NUM>.

The first transistor <NUM>, the second transistor <NUM> and the regulating transistor <NUM> may be implemented such that a gate leakage current of each transistor is negligible compared with a drain current. This implies that a current drawn from the supply voltage is flowing through all transistors <NUM>, <NUM>, <NUM> equally, the current corresponding to the drain currents of the transistors <NUM>, <NUM>, <NUM>.

According to an embodiment, the first transistor <NUM>, the second transistor <NUM> and the regulating transistor <NUM> may be implemented with thick gate oxide layers in order to ensure that gate leakage current is very low. Such transistors may be referred to as input/output transistors, as transistors used for communication with external devices often are implemented with a thick gate oxide layer.

Although input/output transistors may typically have a high threshold voltage, the transistors <NUM>, <NUM>, <NUM> may have relatively low threshold voltages. The second transistor <NUM> and the regulating transistor <NUM> may have lower threshold voltages than the first transistor <NUM>.

The voltage reference circuit <NUM> is configured to output a reference voltage Vref at an output node <NUM> between the first transistor <NUM> and the second transistor <NUM>. Since the first transistor <NUM> is arranged in a stacked connection with the second transistor <NUM>, the drain terminal <NUM> of the first transistor <NUM> and the source terminal <NUM> of the second transistor <NUM> may be connected to the output node <NUM>.

The output node <NUM> is further connected to the bulk terminal <NUM> of the regulating transistor <NUM> for feedback of the reference voltage to the regulating transistor <NUM>. The regulating transistor <NUM> is configured to provide a compensation for changes in the reference voltage such that the voltage reference circuit <NUM> maintains a stable reference voltage level.

The second transistor <NUM> may be configured to generate current in the voltage reference circuit <NUM>. The gate terminal <NUM> and the source terminal <NUM> of the second transistor <NUM> are connected to each other, which also implies that the gate terminal <NUM> is connected to the output node <NUM>. Since the gate terminal <NUM> and the source terminal <NUM> are connected, the second transistor <NUM> has a zero gate-to-source voltage VGS2. The bulk terminal <NUM> of the second transistor <NUM> may be connected to ground.

The second transistor <NUM> may be configured to operate in saturation at a subthreshold region of the second transistor <NUM>. If a drain-to-source voltage VDS2 of the second transistor <NUM> is larger than <NUM>*VT (where VT is thermal voltage), drain current of the second transistor <NUM> is controlled only by the bulk-to-source voltage VBS2 of the second transistor <NUM>. Since the bulk terminal <NUM> of the second transistor <NUM> is connected to ground, the bulk-to-source voltage VBS2 of the second transistor <NUM> is negative. Further, the source terminal <NUM> of the second transistor <NUM> is connected to the output node <NUM> providing the reference voltage Vref, such that VBS2 = - Vref.

The zero gate-to-source voltage VGS2 and the negative bulk-to-source voltage VBS2 implies that an extremely low drain current ID2 may be generated by the second transistor <NUM>. The generated current is supplied to the first transistor <NUM> and the regulating transistor <NUM>.

Since the gate-to-source voltage VGS2 of the second transistor <NUM> is always zero and the bulk-to-source voltage VBS2 is constant (as the output reference voltage Vref is constant in the voltage reference circuit <NUM> and VBS2 = - Vref), the drain current ID2 will be constant if drain-to-source voltage VDS2 of the second transistor <NUM> is constant.

As will be shown below, the regulating transistor <NUM> ensures that the drain-to-source voltage VDS2 of the second transistor <NUM> is maintained constant.

As discussed above, the drain current of the regulating transistor <NUM> equals the drain current of the second transistor <NUM>. The gate terminal <NUM> of the regulating transistor <NUM> may be connected to the source terminal <NUM> of the regulating transistor <NUM>. This implies that the gate-to-source voltage VGS3 of the regulating transistor <NUM> is zero. Hence, the drain current through the regulating transistor <NUM> is controlled by the bulk-to-source voltage VBS3.

An aspect ratio of the regulating transistor <NUM> may equal an aspect ratio of the second transistor <NUM>. This implies that, with the regulating transistor <NUM> and the second transistor <NUM> conducting the same current, the bulk-to-source voltage VBS3 of the regulating transistor <NUM> equals the bulk-to-source voltage VBS2 of the second transistor <NUM>, i.e., VBS3 = VBS2 = - Vref. Hence, using the same aspect ratio for the regulating transistor <NUM> and the second transistor <NUM> provides an accurate control of the reference voltage.

The bulk terminal <NUM> of the regulating transistor <NUM> is connected to the output node <NUM> and, hence, also connected to the source terminal <NUM> of the second transistor <NUM>. The source terminal <NUM> of the regulating transistor <NUM> is connected to the drain terminal <NUM> of the second transistor <NUM>. This implies that the drain-to-source voltage VDS2 of the second transistor <NUM> is regulated by the condition VDS2 = - VBS3 = Vref.

Thanks to the regulating transistor <NUM>, a stable reference voltage level may be maintained. If a parameter, such as supply voltage or temperature, fluctuates so that the reference voltage level increases, an incremental change will be sensed by the change in the bulk-to-source voltage VBS3 of the regulating transistor <NUM>. The regulating transistor <NUM> will thus reduce the drain-to-source voltage VDS2 of the second transistor <NUM> such that the drain current of the second transistor <NUM> will degenerate and bring the reference voltage back to original value. If the reference voltage level instead decreases, the voltage reference circuit <NUM> operates vice versa to maintain the stable reference voltage level.

According to the embodiment in <FIG>, the bulk terminal <NUM> and the drain terminal <NUM> of the first transistor <NUM> are connected to each other and connected to the output node <NUM>. Further, the gate terminal <NUM> and the source terminal <NUM> of the first transistor <NUM> are connected to each other and further connected to ground. This implies that the bulk-to-source voltage VBS1 of the first transistor corresponds to the reference voltage Vref (bulk connected to reference voltage and source connected to ground).

Referring now to <FIG>, a voltage reference circuit <NUM> according to a second embodiment will be described.

The voltage reference circuit <NUM> comprises a first transistor <NUM>, a second transistor <NUM> and a regulating transistor <NUM> corresponding to the voltage reference circuit <NUM> described above with reference to <FIG>. The drain terminal <NUM>, the source terminal <NUM>, the gate terminal <NUM> and the bulk terminal <NUM> of the second transistor <NUM> are connected in the same manner as described above for the first embodiment. Similarly, the drain terminal <NUM>, the source terminal <NUM>, the gate terminal <NUM> and the bulk terminal <NUM> of the regulating transistor <NUM> are connected in the same manner as described above for the first embodiment. Thus, regulation of the reference voltage may be provided in a same manner as described above.

According to the embodiment in <FIG>, the gate terminal <NUM> and the drain terminal <NUM> of the first transistor <NUM> are connected to each other and connected to the output node <NUM>. Further, the bulk terminal <NUM> and the source terminal <NUM> of the first transistor <NUM> are connected to each other and further connected to ground. This implies that the gate-to-source voltage VGS1 of the first transistor corresponds to the reference voltage Vref (gate connected to reference voltage and source connected to ground).

The connection of the first transistor <NUM>, <NUM> to the output node <NUM>, <NUM> and ground affects the reference voltage level at the output node <NUM>, <NUM>. This implies that, if the same transistors are used, a higher reference voltage level may be provided in the configuration of <FIG> compared to the configuration of <FIG>.

The voltage reference circuits <NUM>, <NUM> have been simulated to analyze the insensitivity of the voltage reference circuits <NUM>, <NUM> to parameter variations.

In the simulations, corresponding transistors in the circuits <NUM>, <NUM> have identical properties. Thus, the first transistor <NUM> of the voltage reference circuit <NUM> is identical to the first transistor <NUM> of the voltage reference circuit <NUM>, the second transistor <NUM> and the regulating transistor <NUM> of the voltage reference circuit <NUM> are identical to the second transistor <NUM> and the regulating transistor <NUM> of the voltage reference circuit <NUM>. The simulations have been based on the following parameters of the transistors:
The circuits are simulated in <NUM> FDSOI technology.

The first transistors <NUM>, <NUM> are transistors with low threshold voltage (Vth~<NUM>. 5V) and having a channel width of <NUM> and a channel length of <NUM>.

The second transistors <NUM>, <NUM> and the regulating transistors <NUM>, <NUM> are transistors with ultra-low threshold voltage (Vth~<NUM>. 4V) and having a channel width of <NUM> and a channel length of <NUM>.

Referring now to <FIG>, an operating range of the supply voltage for the voltage reference circuits <NUM>, <NUM> is illustrated. For the voltage reference circuit <NUM>, the reference voltage assumes a value of approximately <NUM> mV when the supply voltage reaches approximately <NUM> V. Then, the reference voltage remains constant until the supply voltage reaches approximately <NUM> V, defining an operating range of the supply voltage between <NUM> - <NUM> V for which the voltage reference circuit <NUM> provides a constant reference voltage. Similarly, the voltage reference circuit <NUM> provides a constant reference voltage of approximately <NUM> mV in an operating range of the supply voltage of <NUM> - <NUM> V.

Thus, the voltage reference circuits <NUM>, <NUM> provide a large operating range of the supply voltage. In addition, the voltage reference circuits <NUM>, <NUM> provide a good line regulation (LR) (change in output reference voltage in dependence of change in supply voltage).

Referring now to <FIG>, an enlargement of the graph of <FIG> for the voltage reference circuit <NUM> is shown. Here, the output reference voltage as a function of supply voltage is shown for the voltage reference circuit <NUM> (solid line) and also for a voltage reference circuit where the regulating transistor <NUM> has been removed (dashed line). The LR for the circuit without the regulating transistor <NUM> is <NUM>µV/V in the range of <NUM> V - <NUM> V of the supply voltage. The LR for the voltage reference circuit <NUM> including the regulating transistor <NUM> is <NUM>µV/V, indicating impact of the regulating transistor <NUM> on performance of the voltage reference circuit <NUM>.

Referring now to <FIG>, an enlargement of the graph of <FIG> for the voltage reference circuit <NUM> is shown. Again, the output reference voltage as a function of supply voltage is shown for the voltage reference circuit <NUM> (solid line) and also for a voltage reference circuit where the regulating transistor <NUM> has been removed (dashed line). The LR for the circuit without the regulating transistor <NUM> is <NUM>µV/V in the range of <NUM> V - <NUM> V of the supply voltage. The LR for the voltage reference circuit <NUM> including the regulating transistor <NUM> is <NUM>µV/V, indicating impact of the regulating transistor <NUM> on performance of the voltage reference circuit <NUM>.

Referring now to <FIG>, temperature characteristics of the reference voltage output by the voltage reference circuits <NUM>, <NUM> (solid lines) is illustrated as well as temperature characteristics of corresponding circuits without the regulating transistor <NUM>, <NUM>. As is shown in <FIG>, the reference voltage output by the voltage reference circuits <NUM>, <NUM> is stable between -<NUM> to <NUM>. The regulating transistor <NUM>, <NUM> negligibly affects the temperature insensitivity of the voltage reference circuits <NUM>, <NUM> in this range. Within this range, a temperature coefficient (TC) of the reference voltages is 198ppm for the voltage reference circuit <NUM> and <NUM>. 3ppm for the voltage reference circuit <NUM>. The regulating transistor <NUM>, <NUM> starts to affect performance of the voltage reference circuits <NUM>, <NUM> at temperatures below -<NUM>.

Referring now to <FIG>, current consumption of the voltage reference circuits <NUM>, <NUM> is illustrated as a function of temperature, while keeping a supply voltage constant at <NUM> V. As can be seen, currents consumed by the voltage reference circuits <NUM>, <NUM> increases almost exponentially over the temperature. The voltage reference circuit <NUM> consumes approximately ten times higher current than the voltage reference circuit <NUM> for the entire temperature range. At <NUM>, the voltage reference circuit <NUM> consumes <NUM> pA and the voltage reference circuit <NUM> consumes <NUM> pA. Hence, the voltage reference circuits <NUM>, <NUM> have ultra-low power consumption.

It should be realized that the voltage reference circuits <NUM>, <NUM> may be used in any type of circuit or device where a stable voltage reference is desired. For instance, as shown in <FIG>, a power management unit <NUM> may comprise any of the voltage reference circuits <NUM>, <NUM> described above.

The power management unit <NUM> may be configured to control power functions of modules in electronic devices. Thus, the power management unit <NUM> may control whether modules are active or in sleep mode and may control power to modules.

The power management unit <NUM> may be configured to provide a DC voltage to modules of an electronic device, such as to integrated circuits. Thus, the power management unit <NUM> may need to ensure that a stable voltage level of the DC voltage is provided. In this regard, the power management unit <NUM> may be configured to produce the DC voltage based on the reference voltage output by the voltage reference circuit <NUM>, <NUM>.

The power management unit <NUM> may comprise an output interface <NUM> for communicating with modules of the electronic device. The power management unit <NUM> may thus send signals for controlling functionality of the modules and may also supply a DC voltage to the modules over the output interface <NUM>.

Since the power management unit <NUM> controls whether modules are active or in a sleep mode, the power management unit <NUM> may be maintained active when turning off the electronic device in which the power management unit <NUM> is arranged. Thus, power consumption of the power management unit <NUM> is important, in particular, if the power management unit <NUM> is arranged in a battery-powered device which may be awake only for a fraction of time, which may be the case for IoT-devices.

The voltage reference circuit <NUM>, <NUM> consumes very small power, as discussed above. Hence, the voltage reference circuits <NUM>, <NUM> are suited for being used in the power management unit <NUM>.

Referring now to <FIG>, a neural sensing apparatus <NUM> according to an embodiment will be described.

The neural sensing apparatus <NUM> may be in form of a neural probe which may be at least partly inserted into a brain. The neural sensing apparatus <NUM> may comprise electrodes <NUM> for neural sensing and readout circuitry <NUM> for reading out signals from the electrodes <NUM>.

The neural sensing apparatus <NUM> may comprise the power management unit <NUM> for power management of the neural sensing apparatus <NUM>. The power management unit <NUM> may be configured to control whether modules, such as the readout circuitry <NUM>, of the neural sensing apparatus <NUM> are active or in a sleep mode.

Claim 1:
A voltage reference circuit (<NUM>; <NUM>) comprising:
a first transistor (<NUM>; <NUM>) comprising a gate terminal (<NUM>; <NUM>), a source terminal (<NUM>; <NUM>), a drain terminal (<NUM>; <NUM>) and a bulk terminal (<NUM>; <NUM>);
a second transistor (<NUM>; <NUM>) comprising a gate terminal (<NUM>; <NUM>), a source terminal (<NUM>; <NUM>), a drain terminal (<NUM>; <NUM>) and a bulk terminal (<NUM>; <NUM>), wherein the first transistor (<NUM>; <NUM>) and the second transistor (<NUM>; <NUM>) are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a reference voltage is output at an output node (<NUM>; <NUM>) between the first transistor (<NUM>; <NUM>) and the second transistor (<NUM>; <NUM>);
a regulating transistor (<NUM>; <NUM>) comprising a gate terminal (<NUM>; <NUM>), a source terminal (<NUM>; <NUM>), a drain terminal (<NUM>; <NUM>) and a bulk terminal (<NUM>; <NUM>), wherein the regulating transistor (<NUM>; <NUM>) is connected between the supply voltage and the first transistor (<NUM>; <NUM>) in a stacked connection with the second transistor (<NUM>; <NUM>), wherein the bulk terminal (<NUM>; <NUM>) of the regulating transistor (<NUM>; <NUM>) is connected to the output node (<NUM>; <NUM>) for compensating changes in the reference voltage at the output node (<NUM>; <NUM>) to maintain a stable reference voltage level.