Patent Description:
Integrated circuits are being fabricated with increasingly smaller components and interconnects. Metal interconnects, including etched aluminum interconnects and copper damascene interconnects, have difficulty handling increasing current densities. Moreover, it is sometimes desirable to reduce the thickness of the interconnects, exacerbating the current density problem. Graphene, having a very high in-plane electrical conductivity, has been proposed as an interconnect material. However, graphene layers more than a few atomic layers thick tend to exhibit degraded conductivity. Integrating thin layers of graphene into integrated circuits has been problematic, due to distortion of the graphene by dielectric materials contacting the graphene.

<CIT> discloses a damascene Cu interconnect comprising a graphene barrier and an optional hBN layer between the dielectric and the graphene barrier.

In a first aspect, the invention relates to an integrated circuit as defined in claim <NUM>. The integrated circuit includes an interconnect, which includes a metal layer, a layer of graphene on at least one of the top surface of the interconnect or the bottom surface of the interconnect, and a layer of hexagonal boron nitride (hBN) on the layer of graphene, opposite from the metal layer. Dielectric material of the integrated circuit contacts the layer of hBN, opposite from the graphene layer. The layer of graphene is comprised of one or more atomic layers of graphene. The layer of hBN is one to three atomic layers thick.

In a second aspect, the invention relates to methods of forming an integrated circuit comprising an interconnect as defined in claims <NUM> and <NUM>.

The drawings are not drawn to scale. Example embodiments are not limited by the illustrated ordering of acts or events, as some acts or events may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology of example embodiments.

An integrated circuit includes an interconnect disposed in an interconnect region, the interconnect including a metal layer, a layer of graphene on at least one of the top surface of the interconnect or the bottom surface of the interconnect, and a layer of hBN on the layer of graphene, opposite from the metal layer. The layer of graphene is comprised of one or more atomic layers of graphene. The layer of graphene may be, for example, one to ten atomic layers thick, to maintain a desired electron mobility in the graphene. The layer of graphene may include Bernal graphene, which is described in reference to <FIG>. The layer of hBN is one to three atomic layers thick. Dielectric material of the interconnect region of the integrated circuit contacts the layer of hBN. One example is described herein in which the metal layer includes an etched aluminum layer. Another example is described herein in which the metal layer includes a damascene copper layer. The layer of graphene provides a highly electrically conductive surface layer for the interconnect which may advantageously improve electrical conductivity at high frequencies, for example at millimeter wave frequencies or terahertz frequencies. Metal interconnects suffer from increased impedance at high frequencies due the current flowing close to surfaces of the metal, a phenomenon sometimes referred to as the "skin effect. " The layer of graphene provides a highly conductive layer at the top and//or bottom surface of the metal interconnect, thus relieving the skin effect. The interconnect may be used in RF circuits or other high frequency applications. The electrical conductivity of the graphene layer improves by increasing the number of atomic layers to about ten atomic layers. Above ten atomic layers, the electrical conductivity of graphene has been observed to behave similar to graphite. The hBN layer is desirably thick enough to isolate the graphene layer from degradation by contact with the dielectric material, but should be thin enough to provide an adequate electrical connection to the graphene by a contact or via of the integrated circuit. Having one to three atomic layers of hBN has been shown to provide the desired balance between degradation of the graphene and electrical connectivity to the graphene layer.

For the purposes of this description, the term "lateral" refers to a direction parallel to a plane of the top surface of the integrated circuit, and the term "vertical" refers to a direction perpendicular to the plane of the top surface of the integrated circuit.

<FIG> is a cross-section of an example integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer, according to an embodiment. The integrated circuit <NUM> includes a substrate <NUM> and an interconnect region <NUM> disposed over the substrate <NUM>. The substrate <NUM> includes a semiconductor material <NUM> such as silicon, gallium nitride, or the like. Active components <NUM> are disposed in the semiconductor material <NUM>. The active components <NUM> are depicted in <FIG> as metal oxide semiconductor (MOS) transistors <NUM> disposed in doped wells <NUM> of the semiconductor material <NUM>, with gates extending above the semiconductor material <NUM>. Other manifestations of the active components <NUM> are within the scope of this example. The active components <NUM> may be laterally separated by field oxide <NUM> disposed in the substrate <NUM>. The field oxide <NUM> may have a shallow trench isolation (STI) structure, as depicted in <FIG>, or may have a local oxidation of silicon (LOCOS) structure.

The interconnect region <NUM> of this example includes a pre-metal dielectric (PMD) layer <NUM> disposed directly above the substrate <NUM> and the active components <NUM>, a first intra-metal dielectric (IMD) layer <NUM> disposed directly above the PMD layer <NUM>, a first inter-level dielectric (ILD) layer <NUM> disposed directly above the first IMD layer <NUM>, and a second IMD layer <NUM> disposed directly above the first ILD layer <NUM>.

The PMD layer <NUM> includes a plurality of sub-layers of dielectric material, for example a PMD liner of silicon nitride, a gap fill layer of silicon dioxide, a main layer of phosphorus silicate glass (PSG) or boron phosphorus silicate glass (BPSG), and a cap layer of silicon nitride. Contacts <NUM> are disposed through the PMD layer <NUM>, making electrical connections to the active components <NUM>. The contacts <NUM> may include, for example, a first liner of titanium touching the PMD layer <NUM>, a second liner of titanium nitride on the first liner, and a fill metal of tungsten on the second liner.

The first IMD layer <NUM> may include one or more sub-layers of dielectric material, including low-k dielectric material and a cap layer of silicon nitride, silicon carbide, or silicon nitride-carbide. First-level interconnects <NUM> are disposed in the first IMD layer <NUM>. The first-level interconnects <NUM> make electrical connections to tops of the contacts <NUM>. In this example, the first-level interconnects <NUM> include a lower hBN layer <NUM> disposed on the PMD layer <NUM>, a lower graphene layer <NUM> disposed directly on the lower hBN layer <NUM>, a metal layer <NUM> disposed directly on the lower graphene layer <NUM>, an upper graphene layer <NUM> disposed directly on the metal layer <NUM>, and an upper hBN layer <NUM> disposed directly on the upper graphene layer <NUM>. Dielectric material of the PMD layer <NUM> touches the lower hBN layer <NUM>, opposite from the lower graphene layer <NUM>. Dielectric material of the first IMD layer <NUM> touches the upper hBN layer <NUM>, opposite from the upper graphene layer <NUM>. The metal layer <NUM> of this example includes an aluminum layer <NUM> disposed on the lower graphene layer <NUM> and a metal cap layer <NUM> disposed on the aluminum layer <NUM>. The lower hBN layer <NUM> and the upper hBN layer <NUM> are each one to three atomic layers thick. The lower graphene layer <NUM> and the upper graphene layer <NUM> are each comprised of one or more atomic layers of graphene. The aluminum layer <NUM> may be, for example, <NUM> nanometers to <NUM> micrometer thick, and may include a few percent silicon, copper and/or titanium. The metal cap layer <NUM> may be, for example, <NUM> nanometers to <NUM> nanometers thick, and may include, for example, titanium nitride to provide an anti-reflection layer, or may include, for example, copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, gold, or other metal suitable for catalysis of graphene.

The first ILD layer <NUM> may include one or more sub-layers of dielectric material, for example an etch stop layer of silicon nitride, a main layer of silicon dioxide or low-k dielectric material such as organosilicate glass (OSG), and a cap layer of silicon nitride. First-level vias <NUM> extend through the first ILD layer <NUM>, and any portion of the first IMD layer <NUM> over the first-level interconnects <NUM>, to make electrical connections to the first-level interconnects <NUM>. The first-level vias <NUM> may extend to the upper graphene layer <NUM>, the metal cap layer <NUM>, or the aluminum layer <NUM>. The first-level vias <NUM> may include, for example, a liner including titanium or titanium nitride touching the first ILD layer <NUM>, and a fill metal of tungsten on the liner.

The second IMD layer <NUM> may include one or more sub-layers of dielectric material, including low-k dielectric material and a cap layer. Second-level interconnects <NUM> are disposed in the second IMD layer <NUM>, making electrical connections to tops of the first-level vias <NUM>. The second-level interconnects <NUM> may optionally have lower and/or upper graphene and hBN layers, similar to the first-level interconnects <NUM>. The integrated circuit <NUM> may include additional ILD layers and IMD layers, vias and interconnects. The additional interconnects may optionally have lower and/or upper graphene and hBN layers, similar to the first-level interconnects <NUM>.

<FIG> are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer, depicting successive stages of formation, according to an embodiment. Referring to <FIG>, the integrated circuit <NUM> includes a substrate <NUM> with a semiconductor material <NUM>. Active components <NUM>, depicted as MOS transistors <NUM>, are formed in the semiconductor material <NUM>. Field oxide <NUM> may be formed in the substrate <NUM> to laterally separate the active components <NUM>.

A PMD layer <NUM> of an interconnect region of the integrated circuit <NUM> is formed over the substrate <NUM> and the active components <NUM>. The PMD layer <NUM> may be formed by forming a sequence of sub-layers, for example, a PMD liner of silicon nitride using a low pressure chemical vapor deposition (LPCVD) process, a main layer of silicon dioxide-based dielectric material using a plasma enhanced chemical vapor deposition (PECVD) process or a high aspect ratio process (HARP) using ozone. The PMD layer <NUM> may be planarized, for example by an oxide chemical mechanical polish (CMP) process, before forming a cap layer of silicon nitride using a PECVD process.

Contacts <NUM> are formed through the PMD layer <NUM>, extending to the active components <NUM>. The contacts <NUM> may be formed by etching contact holes through the PMD layer <NUM>, and forming a titanium liner, by sputtering or an ionized metal plasma (IMP) process, on the PMD layer <NUM> and extending into the contact holes. A titanium nitride liner is formed, by reactive sputtering or atomic layer deposition (ALD), on the titanium liner. A layer of tungsten is formed, by a metal organic chemical vapor deposition (MOCVD) process, on the titanium nitride liner, filling the contact holes. The tungsten, titanium nitride and titanium are removed from over a top surface of the PMD layer <NUM> by a tungsten CMP process, leaving the tungsten fill metal, titanium nitride liner and titanium liner in the contact holes to provide the contacts <NUM>.

A lower hBN layer is formed over the PMD layer <NUM>. In this example, the lower hBN layer is formed by an ALD process. A first step of the ALD process is depicted in <FIG>. A boron-containing reagent gas, denoted in <FIG> as BORON REAGENT GAS, is flowed over the integrated circuit <NUM>. The boron-containing reagent gas may include, for example, boron trichloride (BCl<NUM>) or borane (BH<NUM>). The boron-containing reagent gas forms a boron-containing layer <NUM> over the PMD layer <NUM> and over tops of the contacts <NUM>. Flow of the boron-containing reagent gas is subsequently ceased, leaving the boron-containing layer <NUM> in place for the second step of the ALD process.

Referring to <FIG>, a nitrogen-containing reagent gas, denoted in <FIG> as NITROGEN REAGENT GAS, is flowed over the integrated circuit <NUM>. The nitrogen-containing reagent gas may include, for example, ammonia gas (NH<NUM>). Nitrogen from the nitrogen-containing reagent gas reacts with the boron-containing layer <NUM> of <FIG> to form an atomic layer of a lower hBN layer <NUM> over the PMD layer <NUM> and over the tops of the contacts <NUM>. Flow of the nitrogen-containing reagent gas is subsequently ceased. The ALD process described in reference to <FIG> may be repeated to form a desired thickness, one to three atomic layers, of the lower hBN layer <NUM>.

Referring to <FIG>, a lower graphene layer <NUM> is formed on the lower hBN layer <NUM> by a transfer process. The lower graphene layer <NUM> is first formed on a growth substrate <NUM>, which may be, for example, a silicon wafer with a catalyst surface layer. The lower graphene layer <NUM> may be formed on the growth substrate by a chemical vapor deposition (CVD) process or a PECVD process at a higher temperature than can be tolerated by the integrated circuit <NUM>, for example, over <NUM>. The lower graphene layer <NUM> is subsequently transferred to the integrated circuit <NUM>, for example by inducing stress between the lower graphene layer <NUM> and the growth substrate <NUM>, causing the lower graphene layer <NUM> to separate from the growth substrate <NUM>. Bonding between the lower graphene layer <NUM> and the lower hBN layer <NUM> may be enhanced by a combination of heat and pressure. The lower graphene layer <NUM> includes one or more atomic layers of graphene.

Referring to <FIG>, a metal layer <NUM>, including an aluminum layer <NUM> and a metal cap layer <NUM>, is formed on the lower graphene layer <NUM>. The aluminum layer <NUM> may include, for example, at least <NUM> percent aluminum and a few percent silicon, copper, and/or titanium. In this example, the metal cap layer <NUM> includes a catalyst such as copper, nickel, palladium, platinum, iridium, rhodium, cerium, osmium, molybdenum, and/or gold. The aluminum layer <NUM> may be formed by a sputter process. The metal cap layer <NUM> may be formed by a sputter process or an evaporation process. A metal isolation layer, not shown, may be formed on the aluminum layer <NUM> before forming the metal cap layer <NUM>, to reduce diffusion of aluminum into the metal cap layer <NUM> and to reduce diffusion of catalyst into the aluminum layer <NUM>. The metal isolation layer may include, for example, titanium nitride or tantalum nitride.

An etch mask <NUM> is formed over the metal layer <NUM> which covers areas for subsequently formed first-level interconnects. The etch mask <NUM> may include photoresist formed by a photolithographic process, and may optionally include an anti-reflection layer such as a bottom anti-reflection coat (BARC) or the like. Alternatively, the etch mask <NUM> may include hard mask materials, such as silicon nitride and/or amorphous carbon.

Referring to <FIG>, the metal layer <NUM> and the lower graphene layer <NUM>, and optionally the lower hBN layer <NUM>, are removed in areas exposed by the etch mask <NUM> by a reactive ion etch (RIE) process using halogen radicals and oxygen radicals <NUM>. The RIE process may alter the type and concentration of the halogen radicals and oxygen radicals <NUM> to remove the assorted materials in the metal cap layer <NUM>, the aluminum layer <NUM>, the lower graphene layer <NUM> and the lower hBN layer <NUM>. After the RIE process is completed, the etch mask <NUM> is removed. Organic material and amorphous carbon in the etch mask <NUM> may be removed by an oxygen plasma process. Silicon nitride or other hard mask materials in the etch mask <NUM> may be removed by a plasma process using fluorine radicals and oxygen radicals.

Referring to <FIG>, an upper graphene layer <NUM> is selectively formed on the metal cap layer <NUM> by a graphene PECVD process. In the graphene PECVD process, the integrated circuit <NUM> is heated, for example to a temperature of <NUM> to <NUM>. A carbon-containing reagent gas, denoted in <FIG> as CARBON REAGENT GAS is flowed over the integrated circuit <NUM> and radio-frequency (RF) power, denoted in <FIG> as RF POWER is applied to the carbon-containing reagent gas to generate carbon radicals above the integrated circuit <NUM>. The carbon-containing reagent gas may include methane, straight chain alkanes such as ethane, propane and/or butane, alcohols such as ethanol, and/or cyclic hydrocarbons such as cyclobutane or benzene. Additional gases, such as hydrogen, argon and/or oxygen, may be flowed over the integrated circuit <NUM>. The catalyst in the metal cap layer <NUM> catalyzes the carbon radicals to react to form the upper graphene layer <NUM> selectively on the metal cap layer <NUM>. The upper graphene layer <NUM> includes one or more atomic layers of graphene. Graphene is not formed on the integrated circuit <NUM> beyond the metal cap layer <NUM>.

Referring to <FIG>, an upper hBN layer <NUM> is formed on the upper graphene layer <NUM> and conformally on lateral surfaces of the metal layer <NUM> and the lower graphene layer <NUM>, extending onto the lower hBN layer <NUM> and/or the PMD layer <NUM>. The upper hBN layer <NUM> is formed in this example by a boron nitride PECVD process. A boron-containing reagent gas, denoted in <FIG> as BORON REAGENT GAS, and a nitrogen-containing reagent gas, denoted as NITROGEN REAGENT GAS, are flowed concurrently over the integrated circuit <NUM>. The boron-containing reagent gas may include, for example, boron trichloride or borane. The nitrogen-containing reagent gas may include, for example, ammonia gas. Additional gases, such as hydrogen and/or argon, may be flowed over the integrated circuit <NUM> with the boron-containing reagent gas and the nitrogen-containing reagent gas. RF power, denoted as RF POWER is applied to the boron-containing reagent gas and the nitrogen-containing reagent gas to generate boron radicals and nitrogen radicals above the integrated circuit <NUM>. The boron radicals and the nitrogen radicals react on the integrated circuit <NUM> to form the upper hBN layer <NUM>. The upper hBN layer <NUM> is one to three atomic layers thick. A combination of the lower hBN layer <NUM>, the lower graphene layer <NUM>, the metal layer <NUM>, the upper graphene layer <NUM> and the upper hBN layer <NUM> provides first-level interconnects <NUM> of the integrated circuit <NUM>.

Referring to <FIG>, a first IMD layer <NUM> is formed over the first-level interconnects <NUM> and the PMD layer <NUM>. The first IMD layer <NUM> may be formed by forming an etch stop layer of silicon nitride, followed by forming a main layer of OSG or silicon dioxide. The various layers of the first IMD layer <NUM> may be formed by separate PECVD processes. The main layer may be planarized by an oxide CMP process, followed by forming a cap layer of silicon nitride. Formation of the integrated circuit <NUM> is continued by forming ILD layers, additional IMD layers, vias and interconnects. Additional interconnects may be formed above the first-level interconnects <NUM> by a similar process to that described in reference to <FIG>.

<FIG> are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer, depicting successive stages of formation, according to another embodiment. Referring to <FIG>, the integrated circuit <NUM> includes a substrate <NUM> with a semiconductor material <NUM>. Active components <NUM>, depicted as MOS transistors <NUM>, are formed in the semiconductor material <NUM>. Field oxide <NUM> may be formed in the substrate <NUM> to laterally separate the active components <NUM>. A PMD layer <NUM> of an interconnect region of the integrated circuit <NUM> is formed over the substrate <NUM> and the active components <NUM>. Contacts <NUM> are formed through the PMD layer <NUM>, extending to the active components <NUM>.

A lower hBN layer <NUM> is formed over the PMD layer <NUM>. In this example, the lower hBN layer <NUM> may be formed by an ALD process using a boron-containing reagent gas, denoted in <FIG> as BORON REAGENT GAS and a nitrogen-containing reagent gas, denoted as NITROGEN REAGENT GAS, for example as described in reference to <FIG>.

Referring to <FIG>, a lower graphene layer <NUM> is formed on the lower hBN layer <NUM> by dispensing graphene flakes <NUM>, possibly combined with a carrier fluid, using an additive process <NUM>, such as an electrostatic deposition process, an inkjet process, or such. The additive process <NUM> may form the lower graphene layer <NUM> in areas for subsequently formed first-level interconnects, simplifying fabrication of the integrated circuit <NUM>. The lower graphene layer <NUM> includes one or more atomic layers of graphene. Because hBN has a lattice spacing and atomic pattern that match graphene very closely, the graphene flakes may align with the lattice of the lower hBN layer <NUM> to produce a continuous layer of graphene in the lower graphene layer <NUM> with desired values of electrical properties such as sheet resistance.

Referring to <FIG>, a metal layer <NUM>, including an aluminum layer <NUM> and an optional metal cap layer <NUM>, is formed on the lower graphene layer <NUM>. In this example, the metal cap layer <NUM> may include titanium nitride to provide an anti-reflection layer and a diffusion barrier to contain the aluminum. The aluminum layer <NUM> may be formed by a sputter process. The metal cap layer <NUM> may be formed by a sputter process or an ALD process.

Referring to <FIG>, an upper graphene layer <NUM> is formed on the metal layer <NUM>. The upper graphene layer <NUM> may be formed by a transfer process from a growth substrate <NUM>, as depicted in <FIG>. The upper graphene layer <NUM> includes one or more atomic layers of graphene. Other methods of forming the upper graphene layer <NUM> are within the scope of this example.

Referring to <FIG>, an upper hBN layer <NUM> is formed on the upper graphene layer <NUM>. The upper hBN layer <NUM> is one to three atomic layers thick. The upper hBN layer <NUM> may be formed by a PECVD process using a boron-containing reagent gas, denoted as BORON REAGENT GAS in <FIG>, and a nitrogen-containing reagent gas, denoted as NITROGEN REAGENT GAS, and one or more other gases. The boron-containing reagent gas may include boron trichloride and/or borane. The nitrogen-containing reagent gas may include ammonia gas. The other gases may include argon, hydrogen and/or oxygen. RF power, denoted RF POWER, is applied to the boron-containing reagent gas, the nitrogen-containing reagent gas, and the other gases to form boron radicals and nitrogen radicals. The boron radicals and nitrogen radicals react to form the upper hBN layer <NUM>. Other processes to form the upper hBN layer <NUM> are within the scope of this example.

Referring to <FIG>, an optional protective layer <NUM> may be formed over the upper hBN layer <NUM>. The protective layer <NUM> may include, for example, <NUM> nanometers to <NUM> nanometers of silicon dioxide formed by a PECVD process using tetraethyl orthosilicate (TEOS). Subsequently, an etch mask <NUM> is formed over the upper hBN layer <NUM>, and over the protective layer <NUM>, if present. The etch mask <NUM> covers areas for subsequently formed first-level interconnects. The etch mask <NUM> may be formed by a similar process to that described in reference to <FIG>. In this example, the etch mask <NUM> is aligned with the lower graphene layer <NUM>. The purpose of the protective layer <NUM> in this example is to protect the upper hBN layer <NUM> during subsequent removal of the etch mask <NUM>.

Referring to <FIG>, the protective layer <NUM>, if present, the upper hBN layer <NUM>, the upper graphene layer <NUM>, the metal layer <NUM>, the lower graphene layer <NUM> and optionally the lower hBN layer <NUM>, are removed in areas exposed by the etch mask <NUM> by an RIE process using halogen radicals and oxygen radicals <NUM>. The types and concentrations of the halogen radicals and oxygen radicals <NUM> may be varied as needed to remove the varying materials with a desired etch profile.

Referring to <FIG>, after the RIE process described in reference to <FIG> is completed, the etch mask <NUM> is removed, for example by an oxygen plasma process using oxygen radicals <NUM>. The protective layer <NUM>, if present, protects the upper hBN layer <NUM> from damage by the oxygen radicals <NUM> during removal of the etch mask <NUM>.

A combination of the lower hBN layer <NUM>, the lower graphene layer <NUM>, the metal layer <NUM>, the upper graphene layer <NUM> and the upper hBN layer <NUM> provides first-level interconnects <NUM> of the integrated circuit <NUM>. Formation of the integrated circuit <NUM> is continued by forming a first IMD layer between the first-level interconnects <NUM>. Formation of the integrated circuit <NUM> is further continued by subsequently forming ILD layers, additional IMD layers, vias, and additional interconnects.

<FIG> is a cross-section of an example integrated circuit including a damascene copper interconnect having a lower graphene layer and an upper graphene layer, according to an embodiment. The integrated circuit <NUM> includes a substrate <NUM> and an interconnect region <NUM> disposed over the substrate <NUM>. The substrate <NUM> includes a semiconductor material <NUM>. Active components <NUM>, shown in <FIG> disposed in doped wells <NUM>, are disposed in the semiconductor material <NUM>. The active components <NUM> may be laterally separated by field oxide <NUM> disposed in the substrate <NUM>.

The interconnect region <NUM> of this example includes a PMD layer <NUM> disposed directly above the substrate <NUM> and the active components <NUM>, a first IMD layer <NUM> disposed directly above the PMD layer <NUM>, and a first ILD layer <NUM> disposed directly above the first IMD layer <NUM>. Additional IMD layers and ILD layers of the integrated circuit <NUM>, not shown in <FIG>, extend above the first ILD layer <NUM>. Contacts <NUM> are disposed through the PMD layer <NUM>, making electrical connections to the active components <NUM>. The PMD layer <NUM> and the contacts <NUM> may have a structure similar to that described in reference to <FIG>.

The first IMD layer <NUM> may include one or more sub-layers of dielectric material, including an etch stop layer of silicon nitride, a main layer of low-k dielectric material and a cap layer of silicon nitride, silicon carbide, or silicon nitride-carbide. First-level interconnects <NUM> are disposed in interconnect trenches in the first IMD layer <NUM>. The first-level interconnects <NUM> make electrical connections to tops of the contacts <NUM>. In this example, the first-level interconnects <NUM> include a lower hBN layer <NUM> disposed on the PMD layer <NUM> and extending up sidewalls of the interconnect trenches to a top surface of the first IMD layer <NUM>, a lower graphene layer <NUM> disposed directly on the lower hBN layer <NUM> and extending up sides of the first-level interconnects <NUM>, a metal layer <NUM> disposed directly on the lower graphene layer <NUM>, an upper graphene layer <NUM> disposed directly on the metal layer <NUM>, and an upper hBN layer <NUM> disposed directly on the upper graphene layer <NUM> and extending over the first IMD layer <NUM> adjacent to the first-level interconnects <NUM>. The metal layer <NUM> of this example includes a damascene liner <NUM> disposed on the lower graphene layer <NUM> and extending up sides of the first-level interconnects <NUM>. The damascene liner <NUM> includes a copper diffusion barrier of tantalum nitride or such. The metal layer <NUM> of this example further includes a damascene copper layer <NUM> disposed on the damascene liner <NUM>. The upper graphene layer <NUM> is disposed directly on the damascene copper layer <NUM>. The lower hBN layer <NUM> and the upper hBN layer <NUM> are each one to three atomic layers thick. The lower graphene layer <NUM> and the upper graphene layer <NUM> each include one or more atomic layers of graphene, for example, one to ten layers. Dielectric material of the PMD layer <NUM> touches the lower hBN layer <NUM>, opposite from the lower graphene layer <NUM>.

The first ILD layer <NUM> may have a structure similar to that described in reference to <FIG>. Dielectric material of the first ILD layer <NUM> touches the upper hBN layer <NUM>, opposite from the upper graphene layer <NUM>.

<FIG> are cross-sections of an integrated circuit including an etched aluminum interconnect having a lower graphene layer and an upper graphene layer, depicting successive stages of formation, according to an embodiment. Referring to <FIG>, the integrated circuit <NUM> includes a substrate <NUM> with a semiconductor material <NUM>. Active components <NUM>, depicted as MOS transistors <NUM>, are formed in the semiconductor material <NUM>. Field oxide <NUM> may be formed in the substrate <NUM> to laterally separate the active components <NUM>. A PMD layer <NUM> is formed over the substrate <NUM> and the active components <NUM>. Contacts <NUM> are formed through the PMD layer <NUM>, making electrical connections to the active components <NUM>.

A first IMD layer <NUM> is formed over the PMD layer <NUM> and the contacts <NUM>. The first IMD layer <NUM> may be formed, for example, by a series of PECVD processes. Interconnect trenches <NUM> are formed through the first IMD layer <NUM>, exposing tops of the contacts <NUM>. The interconnect trenches <NUM> may be formed by an RIE process using an etch mask.

A lower hBN layer <NUM> is formed over the first IMD layer <NUM>, extending into the interconnect trenches <NUM> and onto the PMD layer <NUM> at bottoms of the interconnect trenches <NUM>. The lower hBN layer <NUM> may be formed by an ALD process, by a PECVD process, or by another method. The lower hBN layer <NUM> is one to three atomic layers thick.

Referring to <FIG>, a lower graphene layer <NUM> is formed on the lower hBN layer <NUM>. The lower graphene layer <NUM> extends into the interconnect trenches <NUM> and is continuous along the lower hBN layer <NUM> at the bottoms of the interconnect trenches <NUM>. The lower graphene layer <NUM> may be formed, for example, by a PECVD process or an additive process, which may be advantageous due to the topography of the interconnect trenches <NUM>.

Referring to <FIG>, a damascene liner <NUM> is formed on the lower graphene layer <NUM>. The damascene liner <NUM> may include, for example, tantalum nitride. The damascene liner <NUM> may be formed by an ALD process to provide continuous coverage in the interconnect trenches <NUM>.

Referring to <FIG>, a damascene copper layer <NUM> is formed on the damascene liner <NUM>, filling the interconnect trenches <NUM>. The damascene copper layer <NUM> may be formed, for example, by forming a seed layer of copper, not shown in <FIG>, directly on the damascene liner <NUM> by a sputter process, and subsequently forming a remainder of the damascene copper layer <NUM> on the seed layer by an electroplating process. The electroplating process may use a combination of brighteners, inhibitors and levelers, which are additives to the electroplating bath, to fill the interconnect trenches <NUM> with the damascene copper layer <NUM> while minimizing a thickness of the electroplated copper over the first IMD layer <NUM> adjacent to the interconnect trenches <NUM>.

Referring to <FIG>, the damascene copper layer <NUM>, the damascene liner <NUM>, the lower graphene layer <NUM> and the lower hBN layer <NUM> are removed from over the first IMD layer <NUM> by a copper CMP process, depicted schematically in <FIG> by the copper CMP pad <NUM>. The damascene copper layer <NUM>, the damascene liner <NUM>, the lower graphene layer <NUM> and the lower hBN layer <NUM> are left in place in the interconnect trenches <NUM>.

Referring to <FIG>, an upper graphene layer <NUM> is formed on the damascene copper layer <NUM>. The upper graphene layer <NUM> includes one or more atomic layers of graphene, and does not extend onto the first IMD layer <NUM> adjacent to the interconnect trenches <NUM>. The upper graphene layer <NUM> may be formed, for example, by a PECVD process in which the damascene copper layer <NUM> catalyzes formation of graphene selectively, in a manner similar to the PECVD process described in reference to <FIG>. Alternatively, the upper graphene layer <NUM> may be formed by an additive process, for example as described in reference to <FIG>. Other methods of forming the upper graphene layer <NUM> are within the scope of this example.

Referring to <FIG>, an upper hBN layer <NUM> is formed on an existing top surface of the integrated circuit <NUM>, including the upper graphene layer <NUM>. The upper hBN layer <NUM> may be formed by an ALD process, a PECVD process, or other method. A combination of the lower hBN layer <NUM>, the lower graphene layer <NUM>, the damascene liner <NUM> the damascene copper layer <NUM>, the upper graphene layer <NUM> and the upper hBN layer <NUM> provide the first-level interconnects <NUM> of the integrated circuit <NUM>. Formation of the integrated circuit <NUM> continues with formation of a first ILD layer, not shown in <FIG>, on the upper hBN layer <NUM>. Dielectric material of the first ILD layer touches the upper hBN layer <NUM>.

<FIG> is a cross-section of an example integrated circuit including a Litz wire including a metal interconnect including a plurality of segments, each with a lower graphene layer and an upper graphene layer, according to an embodiment. The integrated circuit <NUM> includes a substrate <NUM> and an interconnect region <NUM> disposed over the substrate <NUM>. The substrate <NUM> includes a semiconductor material and active components, for example as described in reference to <FIG>. The interconnect region <NUM> includes dielectric material <NUM>, for example a stack of dielectric layers as described in reference to <FIG>. In this example, the integrated circuit <NUM> includes a Litz wire <NUM> which includes a plurality of strands of serially-connected interconnect segments <NUM>. In this example, each interconnect segment <NUM> has a metal layer <NUM>, a lower graphene layer <NUM> on a bottom surface of the metal layer <NUM>, a lower hBN layer <NUM> on the lower graphene layer <NUM> opposite from the metal layer <NUM>, an upper graphene layer <NUM> on a top surface of the metal layer <NUM>, and an upper hBN layer <NUM> on the upper graphene layer <NUM> opposite from the metal layer <NUM>. The dielectric material <NUM> contacts the lower hBN layer <NUM> opposite from the lower graphene layer <NUM>, and contacts the upper hBN layer <NUM> opposite from the upper graphene layer <NUM>. In other versions of this example, some of the interconnect segments <NUM> may have the lower graphene layer <NUM> and the lower hBN layer <NUM>, without the upper graphene layer <NUM>. In other versions of this example, some of the interconnect segments <NUM> may have the upper graphene layer <NUM> and upper hBN layer <NUM>, without the lower graphene layer <NUM>. The interconnect segments <NUM> of the Litz wire <NUM> are disposed in a plurality of interconnect levels; in this example, the Litz wire <NUM> includes three interconnect levels of the interconnect segments <NUM>. Connections between sequential interconnect segments <NUM> in each strand are not shown in <FIG>, to more clearly show the arrangement of the interconnect segments <NUM> themselves. Each strand is configured so that a portion of the interconnect segments <NUM> in that strand are located at a periphery of the Litz wire <NUM>. The sequential interconnect segments <NUM> in each strand may be connected, for example, by vias and other interconnects. Each strand includes a portion of the interconnect segments <NUM> in each interconnect level. The Litz wire <NUM> may advantageously exhibit lower impedance at high frequency, due to distribution of the skin effect among the interconnect segments <NUM>, as compared to a monolithic conductor with a similar nominal cross-section area. Each strand is isolated from the other strands by the dielectric material <NUM>, advantageously reducing induced local currents, sometimes referred to as the "proximity effect.

<FIG> is a perspective view of graphene. The layers of graphene in the examples described herein may include Bernal graphene. A first atomic layer of graphene, designated FIRST ATOMIC LAYER in <FIG>, contains carbon atoms, designated CARBON ATOM in <FIG>, in a hexagonal configuration. A second atomic layer of graphene, designated SECOND ATOMIC LAYER in <FIG>, also contains carbon atoms in a hexagonal configuration. In Bernal graphene half Half of the carbon atoms in the first atomic layer are located directly over carbon atoms in the second atomic layer. Additional layers of graphene have similar alignments with respect to immediately underlying graphene layers. Including Bernal graphene in the graphene layers of the graphene heterolayers may advantageously improve electrical conductivity of the graphene heterolayers compared to layers of graphene having other configurations.

Claim 1:
An integrated circuit, comprising:
a substrate (<NUM>) including a semiconductor material;
active components (<NUM>) disposed in the substrate;
an interconnect region disposed over the substrate, the interconnect region including a dielectric material (<NUM>); and
an interconnect (<NUM>) disposed in the interconnect region, the interconnect comprising:
a metal layer (<NUM>);
a graphene layer (<NUM>, <NUM>) disposed on one of a top surface of the metal layer or a bottom surface of the metal layer, the graphene layer having at least one atomic layer of grahene; and
a hexagonal boron nitride (hBN) layer (<NUM>, <NUM>) disposed on the graphene layer opposite from the metal layer, the hBN layer being one to three atomic layers thick, wherein the dielectric material touches the hBN layer opposite from the graphene layer;
and
wherein:
the graphene layer is a lower graphene layer disposed on the bottom surface of the metal layer;
the hBN layer is a lower hBN layer (<NUM>) disposed on the lower graphene layer (<NUM>);
the dielectric material is a first dielectric material;
the interconnect region includes a second dielectric material, (<NUM>) separate from the first dielectric material; and
the interconnect further comprises:
an upper graphene layer (<NUM>) disposed on the top surface of the metal layer, the upper graphene layer having at least one atomic layer of graphene; and
an upper hBN layer (<NUM>) disposed on the upper graphene layer, opposite from the metal layer, the upper graphene layer being one to three atomic layers thick, wherein the second dielectric material touches the upper hBN layer opposite from the upper graphene layer.