Patent Description:
Computers including phones, servers, and personal computers all utilize memory to store data. This memory includes random access memory, cache memory, non-volatile memory, etc., stores data to be utilized during program execution.

<CIT> discloses: Techniques in wavelet filtering for advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element to execute programmed instructions using the data and a router to route the wavelets in accordance with virtual channel specifiers. Each processing element is enabled to perform local filtering of wavelets received at the processing element, selectively, conditionally, and/or optionally discarding zero or more of the received wavelets, thereby preventing further processing of the discarded wavelets. The wavelet filtering is performed by one or more configurable wavelet filters operable in various modes, such as counter, sparse, and range modes.

<CIT> discloses a microprocessor that includes a random number generator (RNG) and an instruction for storing random data bytes generated by the generator. The RNG includes multiple buffers for buffering the random bytes and counters associated with each buffer for keeping a count of the number of bytes in each buffer. The instruction specifies a destination for the bytes to be stored to. In one embodiment, the number of bytes written to memory is variable and is the number of bytes available when the instruction is executed; in another, the instruction specifies the number. If variable, the instruction atomically stores a count specifying the number of valid bytes actually stored. In one embodiment the destination is a location in system memory. The count may be stored to memory with the bytes; or the count may be stored to a user-visible register. An REP prefix may be used.

<CIT> discloses: A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.

<CIT> discloses: The present application discloses a random number generation and retrieval method and device. The generation method includes: generating a random number array, where the random number array includes N storage units, each of the storage units stores a random number, and N is a positive integer; performing random shuffling on the storage units in the random number array; and receiving a random number retrieval instruction, and reading, from a corresponding storage unit in the random number array based on the random number retrieval instruction, a random number stored in the storage unit. In the implementations of the present application, a plurality of random numbers obtained in a relatively short unit time have a low repetition rate, to achieve balanced distribution. Therefore, the random number generation method and device in the present application can achieve relatively high randomness.

Various examples in accordance with the present disclosure will be described with reference to the drawings, in which:.

The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for writing random data to one or more cachelines and/or using random data in instruction execution. According to some examples, an instruction, which when executed, causes circuitry (such as memory access circuitry or execution circuitry) to write random data into one or more cache lines. According to some examples, an instruction, which when executed, causes circuitry (such as execution circuitry) to use random data as an operand without having to identify a particular location for a source of that random data (e.g., without having to identify a particular register or memory location).

There are times that a programmer would like for a particular subset of memory (e.g., a cacheline or cache level) to be initialized to a particular value or type of value. For example, in training a machine learning algorithm, there are times when a random value may be used. Instead of having to generate random value with an instruction, and then use the generated random value in a different instruction, it would be beneficial to have a particular subset of memory that is accessible that already has random value available. Additionally, there are times when a random value is desired such as for performing inference with a machine learning model or training of a machine learning algorithm.

Current cache prefetch instructions fetch a cache line of data from memory at a defined memory location (such as a byte memory location). Whatever data is stored in that location is retrieved. There are no instructions which allow for random data to be prefetched. Additionally, while there are instructions that use implicit operands, there are no known instructions that have an implicit operand which is a random data value.

Detailed below are examples of systems, apparatuses, etc. that allow for the prefetch of cachelines of random data and/or perform an operation with implicitly identified random data. This allows for a cacheline to be primed for a future task or tasks without the need for expending the extra time and energy of first generating a random data value, storing that data value in a particular memory location, and then prefetching that line from the particular memory location, or to use random data without having to identify a particular storage location. In some examples, the use of either of these instructions is particularly useful for training a machine learning algorithm or fine tuning a machine learning model. For example, in a second plus round of calculations the use of random values is a common technique.

<FIG> illustrates examples of aspects of a processor and/or system on a chip involved in a prefetch of random data for one or more cachelines and/or use implicitly referenced random data during instruction execution. A plurality of cores <NUM>(<NUM>)-INV03(N) include instruction processing resources (an exemplary pipeline is detailed later) which include the use of local caches <NUM>(<NUM>)-<NUM>(N). In some examples, at least one of the cores is a graphics processing unit (GPU), accelerator processing unit (APU), etc. The cores <NUM>(<NUM>)-INV03(N) also utilize a shared cache <NUM>. The shared cache <NUM> may be a last level cache (LLC) such as L3, L4, etc. cache. As will be detailed below, the processing of a single instruction of a first instruction set causes one or more cachelines in the local caches <NUM>(<NUM>)-<NUM>(N) or shared cache <NUM> to store random data. In some examples, the single instruction is translated to one or more instructions of a second, different instruction set that causes one or more cachelines in the local caches <NUM>(<NUM>)-<NUM>(N) or shared cache <NUM> to store random data.

A memory controller <NUM> is used to access to main memory <NUM> (e.g., random access memory (RAM)). In particular, the memory controller <NUM> controls reads and writes to main memory <NUM>. In some examples, the memory controller <NUM> is integrated within a processor <NUM>. In other examples, the memory controller <NUM> is external to a processor. Main memory <NUM> includes a plurality of data blocks that store data.

A platform controller <NUM> is used to access to non-volatile memory <NUM> (e.g., hard disk, second level memory (2LM), etc.). In particular, the platform controller <NUM> controls reads and writes to non-volatile memory <NUM>. Non-volatile memory <NUM> includes a plurality of data blocks that store data.

A random number generator (RNG) circuitry <NUM> generates random number to be stored. Note that this circuitry is a part of one or more cores in some examples.

In some examples, certain aspects are integrated as part of a processor <NUM> and/or system on a chip <NUM>.

<FIG> illustrates examples of core and caches in greater detail. As shown, a core <NUM>(<NUM>) at least includes an execution cluster <NUM> which executes instructions. This execution cluster <NUM> may include execution unit(s) circuitry (ALU, etc.) and/or memory access circuitry.

As shown, the random number storage <NUM> is close to the execution cluster <NUM>. In some examples, the random number storage <NUM> is a part of the execution cluster. The random number storage <NUM> is implemented with dedicated registers in some examples. In other examples, the random number storage <NUM> is implemented as a scratch pad. Additionally, in some examples, support for such register usage is indicated via a CPUID leaf.

The execution cluster <NUM>, upon the execution of an instruction (detailed below), pulls one or more random numbers from the random number storage <NUM> and for one or more cache lines of the L1 cache <NUM>, L2 cache <NUM>, and/or shared cache <NUM>. In some examples, the data is actually stored. In other examples, it is made available for cache use. The level of cache to store the line(s) is indicated by the opcode of the instruction in some examples. In other examples, this encoded by bits <NUM> through <NUM> of the mod R/M byte (detailed later). The exemplary levels may include as PF0 - prefetch data for all levels of the cache hierarchy, PF1 - prefetch data for level <NUM> cache (e.g., L2 cache <NUM>) and higher, PF2 - prefetch data for level <NUM> cache (e.g., shared cache <NUM>) and higher, or PFA - prefetch into a non-temporal cache structure.

<FIG> illustrates examples usage of a random number by an execution cluster. As shown, the execution cluster <NUM>, during execution of an instruction, receives data from a first source (source <NUM><NUM>) such as a register or memory location and from random number storage <NUM> and stores the result in destination <NUM> such as a register or memory location. In previous architectures, to use a random number one would first have to generate and store the random number using a first instruction and then execute a second instruction that referenced that stored random number.

<FIG> illustrates examples of a method for using random numbers. A plurality of random numbers is generated and stored at <NUM>. This occurs during boot, during downtime within a processor, etc. This generation allows for the initialization to random numbers have little or no time penalty. In some examples, the random numbers are stored in, or near, the memory to be initialized.

In some examples, a PREFETCHRDM instruction (or equivalent translated instructions) is processed to prefetch previously generated random data for one or more lines of cache at <NUM>. This instruction is detailed below.

In some examples, a {OP}WRND instruction (or equivalent translated instructions) is processed to perform an operation using implicitly addressed random data at <NUM>. This instruction is detailed below.

<FIG> illustrates examples of a method to process a PREFETCHRDM instruction. In some examples, a processor core as shown in <FIG>, a pipeline as detailed below, etc. performs this method. In other examples, a binary translation layer performs aspects of the method, and a processor core performs other aspects of the method.

At <NUM>, a single PREFETCHRDM instruction is fetched. The PREFETCHRDM instruction may come in many different forms depending on the implementation.

An example of a format for a memory initialization instruction is PREFETCHRDM SRC. In some examples, PREFETCHRDM is the opcode mnemonic of the instruction. The PREFETCHRDM instruction, when executed, causes one or more cachelines of random data to be prefetched from random data storage to be used in one or more levels of cache. SRC represents one or more fields that indicate what level(s) of cache to prefetch for. In some examples, this is encoded by bits <NUM> through <NUM> of the mod R/M byte (detailed later). The exemplary levels may include as PF0 - prefetch data for all levels of the cache hierarchy, PF1 - prefetch data for level <NUM> cache (e.g., L2 cache <NUM>) and higher, PF2 - prefetch data for level <NUM> cache (e.g., shared cache <NUM>) and higher, or PFA - prefetch into a non-temporal cache structure.

An example of a format for a memory initialization instruction is PREFETCHRDM{LEVEL}. In some examples, PREFETCHRDM{LEVEL} is the opcode mnemonic of the instruction. The PREFETCHRDM{LEVEL} instruction, when executed, causes one or more cache lines of random data to be prefetched from random data storage to be used in one or more levels of cache. {LEVEL} represents exemplary levels to prefetch for such as, for example, PF0 - prefetch data for all levels of the cache hierarchy, PF1 - prefetch data for level <NUM> cache (e.g., L2 cache <NUM>) and higher, PF2 - prefetch data for level <NUM> cache (e.g., shared cache <NUM>) and higher, or PFA - prefetch into a non-temporal cache structure.

An example of a format for a memory initialization instruction is PREFETCHRDM SRC1, SRC2. In some examples, PREFETCHRDM is the opcode mnemonic of the instruction. The PREFETCHRDM instruction, when executed, causes one or more cachelines of random data to be prefetched from random data storage to be used in one or more levels of cache. SRC1 represents one or more fields of the instruction that indicate what level(s) of cache to prefetch for. In some examples, this is encoded by bits <NUM> through <NUM> of the mod R/M byte (detailed later). The exemplary levels may include as PF0 - prefetch data for all levels of the cache hierarchy, PF1 - prefetch data for level <NUM> cache (e.g., L2 cache <NUM>) and higher, PF2 - prefetch data for level <NUM> cache (e.g., shared cache <NUM>) and higher, or PFA-prefetch into a non-temporal cache structure. SRC2 represents one or more fields of that instruction that indicate what a storage location that is to store a number of cachelines to prefetch.

An example of a format for a memory initialization instruction is PREFETCHRDM SRC1, IMM. In some examples, PREFETCHRDM is the opcode mnemonic of the instruction. The PREFETCHRDM instruction, when executed, causes one or more cachelines of random data to be prefetched from random data storage to be used in one or more levels of cache. SRC1 represents one or more fields of the instruction that indicate what level(s) of cache to prefetch for. In some examples, this is encoded by bits <NUM> through <NUM> of the mod R/M byte (detailed later). The exemplary levels may include as PF0 - prefetch data for all levels of the cache hierarchy, PF1 - prefetch data for level <NUM> cache (e.g., L2 cache <NUM>) and higher, PF2 - prefetch data for level <NUM> cache (e.g., shared cache <NUM>) and higher, or PFA-prefetch into a non-temporal cache structure. IMM represents an immediate field of the instruction that encodes a number of cachelines to prefetch.

An example of a format for a memory initialization instruction is PREFETCHRDM{LEVEL} SRC1. In some examples, PREFETCHRDM{LEVEL} is the opcode mnemonic of the instruction. The PREFETCHRDM{LEVEL} instruction, when executed, causes one or more cache lines of random data to be prefetched from random data storage to be used in one or more levels of cache. {LEVEL} represents exemplary levels to prefetch for such as, for example, PF0 - prefetch data for all levels of the cache hierarchy, PF1 - prefetch data for level <NUM> cache (e.g., L2 cache <NUM>) and higher, PF2 - prefetch data for level <NUM> cache (e.g., shared cache <NUM>) and higher, or PFA - prefetch into a non-temporal cache structure. SRC1 represents one or more fields of the instruction that indicate what a storage location that is to store a number of cachelines to prefetch.

An example of a format for a memory initialization instruction is PREFETCHRDM{LEVEL} IMM. In some examples, PREFETCHRDM{LEVEL} is the opcode mnemonic of the instruction. The PREFETCHRDM{LEVEL} instruction, when executed, causes one or more cachelines of random data to be prefetched from random data storage to be used in one or more levels of cache. {LEVEL} represents exemplary levels to prefetch for such as, for example, PF0 - prefetch data for all levels of the cache hierarchy, PF1 - prefetch data for level <NUM> cache (e.g., L2 cache <NUM>) and higher, PF2 - prefetch data for level <NUM> cache (e.g., shared cache <NUM>) and higher, or PFA - prefetch into a non-temporal cache structure. IMM represents an immediate field of the instruction that encodes a number of cachelines to prefetch.

Examples of instruction formats are shown in <FIG>. In some examples, the opcode of the instruction is found in, for example, field <NUM> and any used immediate is found in <NUM>. In some examples, the type of prefetch to perform is dictated by a prefix. A source is typically indicated using addressing field <NUM> such as using aspects of the mod R/M byte <NUM> like the register field <NUM> to indicate a register as a source, the r/m field <NUM> as another source, etc. Note that sources can be registers and/or memory.

In some examples, the fetched instruction of the first instruction set is translated into one or more instructions of a second instruction set at <NUM>.

The fetched instruction, or the one or more translated instructions of the second instruction set, is/are decoded at <NUM>. In some examples, the translation and decoding are merged.

Data values associated with the source operand(s) of the decoded instruction(s) are retrieved and the instruction(s) scheduled at <NUM>. For example, when one or more of the source operands are memory operands, the data from the indicated memory location is retrieved.

At <NUM>, the decoded instruction(s) is/are executed by execution circuitry (hardware) such as that detailed herein according to the opcode, etc. of the fetched instruction.

In some examples, the instruction(s) is/are committed or retired at <NUM>.

<FIG> illustrates examples of a method to process a {OP}WRND instruction. In some examples, a processor core as shown in <FIG>, a pipeline as detailed below, etc. performs this method. In other examples, a binary translation layer performs aspects of the method, and a processor core performs other aspects of the method.

At <NUM>, a single {OP}WRND instruction is fetched. The {OP}WRND instruction may come in many different forms depending on the implementation.

An example of a format for a memory initialization instruction is {OP}WRND DEST. In some examples, {OP}WRND is the opcode mnemonic of the instruction. {OP} would be replaced with the operation to be performed and, in some examples, is the same as an existing instruction (e.g., PMULUDQ for a multiply packed unsigned doubleword integers). Exemplary operations include arithmetic operations (multiply, add, subtract, divide, fused multiply add, fused multiply accumulate, etc.), Boolean operations, etc. DEST represents a destination of the instruction. A particular destination location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. An implicit source is a random data value that is stored, for example, in random number storage. This may be used for a destructive variant (e.g., DEST = random number OP DEST). The destination and any source may be of integer value (e.g., INT4, INT8, INT16, INT32, etc.), floating point (e.g., FP16, FP32, FP64, BF16, etc.) and may be packed (e.g., a vector register) or scalar.

An example of a format for a memory initialization instruction is {OP}WRND DEST, SRC. In some examples, {OP}WRND is the opcode mnemonic of the instruction. {OP} would be replaced with the operation to be performed and, in some examples, is the same as an existing instruction (e.g., PMULUDQ for a multiply packed unsigned doubleword integers). Exemplary operations include arithmetic operations (multiply, add, subtract, divide, fused multiply add, fused multiply accumulate, etc.), Boolean operations, etc. DEST represents a destination of the instruction. A particular destination location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. SRC represents a first source of the instruction. A particular source location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. An implicit second source is a random data value that is stored, for example, in random number storage. The destination and any source may be of integer value (e.g., INT4, INT8, INT16, INT32, etc.), floating point (e.g., FP16, FP32, FP64, BF16, etc.) and may be packed (e.g., a vector register) or scalar. This may be used for a destructive or non-destructive variant.

An example of a format for a memory initialization instruction is {OP}WRND DEST, SRC1, SRC2. In some examples, {OP}WRND is the opcode mnemonic of the instruction. {OP} would be replaced with the operation to be performed and, in some examples, is the same as an existing instruction (e.g., PMULUDQ for a multiply packed unsigned doubleword integers). Exemplary operations include arithmetic operations (multiply, add, subtract, divide, fused multiply add, fused multiply accumulate, etc.), Boolean operations, etc. DEST represents a destination of the instruction. A particular destination location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. SRC1 and SRC2 represent a first source and second source of the instruction. A particular source location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. An implicit third source is a random data value that is stored, for example, in random number storage. The destination and any source may be of integer value (e.g., INT4, INT8, INT16, INT32, etc.), floating point (e.g., FP16, FP32, FP64, BF16, etc.) and may be packed (e.g., a vector register) or scalar. This may be used for a destructive or non-destructive variant.

An example of a format for a memory initialization instruction is {OP}WRND DEST IMM. In some examples, {OP}WRND is the opcode mnemonic of the instruction. {OP} would be replaced with the operation to be performed and, in some examples, is the same as an existing instruction (e.g., PMULUDQ for a multiply packed unsigned doubleword integers). Exemplary operations include arithmetic operations (multiply, add, subtract, divide, fused multiply add, fused multiply accumulate, etc.), Boolean operations, etc. DEST represents a destination of the instruction. A particular destination location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. IMM represents an immediate field to encode a value to be used during execution. An implicit source is a random data value that is stored, for example, in random number storage. This may be used for a destructive variant (e.g., DEST = random number OP DEST). The destination and any source may be of integer value (e.g., INT4, INT8, INT16, INT32, etc.), floating point (e.g., FP16, FP32, FP64, BF16, etc.) and may be packed (e.g., a vector register) or scalar.

An example of a format for a memory initialization instruction is {OP}WRND DEST, SRC IMM. In some examples, {OP}WRND is the opcode mnemonic of the instruction. {OP} would be replaced with the operation to be performed and, in some examples, is the same as an existing instruction (e.g., PMULUDQ for a multiply packed unsigned doubleword integers). Exemplary operations include arithmetic operations (multiply, add, subtract, divide, fused multiply add, fused multiply accumulate, etc.), Boolean operations, etc. DEST represents a destination of the instruction. A particular destination location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. SRC represents a first source of the instruction. A particular source location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. An implicit second source is a random data value that is stored, for example, in random number storage. IMM represents an immediate field to encode a value to be used during execution. The destination and any source may be of integer value (e.g., INT4, INT8, INT16, INT32, etc.), floating point (e.g., FP16, FP32, FP64, BF16, etc.) and may be packed (e.g., a vector register) or scalar. This may be used for a destructive or non-destructive variant.

An example of a format for a memory initialization instruction is {OP}WRND DEST, SRC1, SRC2 IMM. In some examples, {OP}WRND is the opcode mnemonic of the instruction. {OP} would be replaced with the operation to be performed and, in some examples, is the same as an existing instruction (e.g., PMULUDQ for a multiply packed unsigned doubleword integers). Exemplary operations include arithmetic operations (multiply, add, subtract, divide, fused multiply add, fused multiply accumulate, etc.), Boolean operations, etc. DEST represents a destination of the instruction. A particular destination location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. SRC1 and SRC2 represent a first source and second source of the instruction. A particular source location (e.g., memory or a register) is indicated using one or more fields of the instruction as detailed later. An implicit third source is a random data value that is stored, for example, in random number storage. IMM represents an immediate field to encode a value to be used during execution. The destination and any source may be of integer value (e.g., INT4, INT8, INT16, INT32, etc.), floating point (e.g., FP16, FP32, FP64, BF16, etc.) and may be packed (e.g., a vector register) or scalar. This may be used for a destructive or non-destructive variant.

At <NUM>, the decoded instruction(s) is/are executed by execution circuitry (hardware) such as that detailed herein according to the opcode of the fetched instruction.

<FIG> illustrates examples of hardware to process an instruction such as a random data cache prefetch (PREFETCHRDM) instruction and/or a use random data in an operation ({OP}WRND) instruction. In some examples, this hardware represents aspects of a core. As illustrated, storage <NUM> stores an PREFETCHRDM and/or random data using instruction <NUM> to be executed.

The instruction <NUM> is received by decode circuitry <NUM>. For example, the decode circuitry <NUM> receives this instruction from fetch logic/circuitry. The instruction includes fields for an opcode, first and second sources, and a destination. In some examples, the sources and destination are registers, and in other examples one or more are memory locations. In some examples, the opcode details which arithmetic operation is to be performed.

More detailed examples of at least one instruction format will be detailed later. The decode circuitry <NUM> decodes the instruction into one or more operations. In some examples, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry <NUM>). The decode circuitry <NUM> also decodes instruction prefixes.

In some examples, register renaming, register allocation, and/or scheduling circuitry <NUM> provides functionality for one or more of: <NUM>) renaming logical operand values to physical operand values (e.g., a register alias table in some examples), <NUM>) allocating status bits and flags to the decoded instruction, and <NUM>) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some examples).

Registers (register file) and/or memory <NUM> store data as operands of the instruction to be operated on by execution circuitry <NUM>. Exemplary register types include packed data registers, general purpose registers, and floating-point registers.

In some examples, execution circuitry <NUM> executes the decoded instruction(s) prefetch one or more cachelines with a random data value. In some examples, execution circuitry <NUM> executes the decoded instruction(s) to perform an operation using implicitly addressed storage of random data. Exemplary detailed execution circuitry is shown in <FIG>, <FIG>, etc..

In some examples, retirement/write back circuitry <NUM> architecturally commits the destination register into the registers or memory <NUM> and retires the instruction.

Exemplary architectures, pipelines, cores, systems, instruction formats, etc. in which examples described above may be embodied are detailed below.

Detailed below are describes of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, handheld devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

<FIG> illustrates examples of an exemplary system. Multiprocessor system <NUM> is a point-to-point interconnect system and includes a plurality of processors including a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. In some examples, the first processor <NUM> and the second processor <NUM> are homogeneous. In some examples, first processor <NUM> and the second processor <NUM> are heterogenous.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units circuitry <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its interconnect controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via the point-to-point (P-P) interconnect <NUM> using P-P interface circuits <NUM>, <NUM>. IMCs <NUM> and <NUM> couple the processors <NUM>, <NUM> to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interconnects <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with a coprocessor <NUM> via a high-performance interface <NUM>. In some examples, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor <NUM>, <NUM> or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset <NUM> may be coupled to a first interconnect <NUM> via an interface <NUM>. In some examples, first interconnect <NUM> may be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Express interconnect or another I/O interconnect. In some examples, one of the interconnects couples to a power control unit (PCU) <NUM>, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors <NUM>, <NUM> and/or co-processor <NUM>. PCU <NUM> provides control information to a voltage regulator to cause the voltage regulator to generate the appropriate regulated voltage. PCU <NUM> also provides control information to control the operating voltage generated. In various examples, PCU <NUM> may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).

PCU <NUM> is illustrated as being present as logic separate from the processor <NUM> and/or processor <NUM>. In other cases, PCU <NUM> may execute on a given one or more of cores (not shown) of processor <NUM> or <NUM>. In some cases, PCU <NUM> may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCU <NUM> may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCU <NUM> may be implemented within BIOS or other system software.

Various I/O devices <NUM> may be coupled to first interconnect <NUM>, along with an interconnect (bus) bridge <NUM> which couples first interconnect <NUM> to a second interconnect <NUM>. In some examples, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interconnect <NUM>. In some examples, second interconnect <NUM> may be a low pin count (LPC) interconnect. Various devices may be coupled to second interconnect <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit circuitry <NUM>. Storage unit circuitry <NUM> may be a disk drive or other mass storage device which may include instructions/code and data <NUM>, in some examples. Further, an audio I/O <NUM> may be coupled to second interconnect <NUM>. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system <NUM> may implement a multi-drop interconnect or other such architecture.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

<FIG> illustrates a block diagram of examples of a processor <NUM> that may have more than one core, may have an integrated memory controller, and may have integrated graphics. The solid lined boxes illustrate a processor <NUM> with a single core 902A, a system agent <NUM>, a set of one or more interconnect controller units circuitry <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores <NUM>(A)-(N), a set of one or more integrated memory controller unit(s) circuitry <NUM> in the system agent unit circuitry <NUM>, and special purpose logic <NUM>, as well as a set of one or more interconnect controller units circuitry <NUM>. Note that the processor <NUM> may be one of the processors <NUM> or <NUM>, or co-processor <NUM> or <NUM> of <FIG>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores, not shown), and the cores <NUM>(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); <NUM>) a coprocessor with the cores <NUM>(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores <NUM>(A)-(N) being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit circuitry), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

A memory hierarchy includes one or more levels of cache unit(s) circuitry <NUM>(A)-(N) within the cores <NUM>(A)-(N), a set of one or more shared cache units circuitry <NUM>, and external memory (not shown) coupled to the set of integrated memory controller units circuitry <NUM>. The set of one or more shared cache units circuitry <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples ring-based interconnect network circuitry <NUM> interconnects the special purpose logic <NUM> (e.g., integrated graphics logic), the set of shared cache units circuitry <NUM>, and the system agent unit circuitry <NUM>, alternative examples use any number of well-known techniques for interconnecting such units. In some examples, coherency is maintained between one or more of the shared cache units circuitry <NUM> and cores <NUM>(A)-(N).

In some examples, one or more of the cores <NUM>(A)-(N) are capable of multi-threading. The system agent unit circuitry <NUM> includes those components coordinating and operating cores <NUM>(A)-(N). The system agent unit circuitry <NUM> may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores <NUM>(A)-(N) and/or the special purpose logic <NUM> (e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.

The cores <NUM>(A)-(N) may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores <NUM>(A)-(N) may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of that instruction set or a different instruction set.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to examples. <FIG> is a block diagram illustrating both an exemplary example of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to examples. The solid lined boxes in <FIG>-(B) illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

In <FIG>, a processor pipeline <NUM> includes a fetch stage <NUM>, an optional length decode stage <NUM>, a decode stage <NUM>, an optional allocation stage <NUM>, an optional renaming stage <NUM>, a scheduling (also known as a dispatch or issue) stage <NUM>, an optional register read/memory read stage <NUM>, an execute stage <NUM>, a write back/memory write stage <NUM>, an optional exception handling stage <NUM>, and an optional commit stage <NUM>. One or more operations can be performed in each of these processor pipeline stages. For example, during the fetch stage <NUM>, one or more instructions are fetched from instruction memory, during the decode stage <NUM>, the one or more fetched instructions may be decoded, addresses (e.g., load store unit (LSU) addresses) using forwarded register ports may be generated, and branch forwarding (e.g., immediate offset or an link register (LR)) may be performed. In one example, the decode stage <NUM> and the register read/memory read stage <NUM> may be combined into one pipeline stage. In one example, during the execute stage <NUM>, the decoded instructions may be executed, LSU address/data pipelining to an Advanced Microcontroller Bus (AHB) interface may be performed, multiply and add operations may be performed, arithmetic operations with branch results may be performed, etc..

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline <NUM> as follows: <NUM>) the instruction fetch <NUM> performs the fetch and length decoding stages <NUM> and <NUM>; <NUM>) the decode unit circuitry <NUM> performs the decode stage <NUM>; <NUM>) the rename/allocator unit circuitry <NUM> performs the allocation stage <NUM> and renaming stage <NUM>; <NUM>) the scheduler unit(s) circuitry <NUM> performs the schedule stage <NUM>; <NUM>) the physical register file(s) unit(s) circuitry <NUM> and the memory unit circuitry <NUM> perform the register read/memory read stage <NUM>; the execution cluster <NUM> perform the execute stage <NUM>; <NUM>) the memory unit circuitry <NUM> and the physical register file(s) unit(s) circuitry <NUM> perform the write back/memory write stage <NUM>; <NUM>) various units (unit circuitry) may be involved in the exception handling stage <NUM>; and <NUM>) the retirement unit circuitry <NUM> and the physical register file(s) unit(s) circuitry <NUM> perform the commit stage <NUM>.

<FIG> shows processor core <NUM> including front-end unit circuitry <NUM> coupled to an execution engine unit circuitry <NUM>, and both are coupled to a memory unit circuitry <NUM>.

The front end unit circuitry <NUM> may include branch prediction unit circuitry <NUM> coupled to an instruction cache unit circuitry <NUM>, which is coupled to an instruction translation lookaside buffer (TLB) <NUM>, which is coupled to instruction fetch unit circuitry <NUM>, which is coupled to decode unit circuitry <NUM>. In one example, the instruction cache unit circuitry <NUM> is included in the memory unit circuitry <NUM> rather than the front-end unit circuitry <NUM>. The decode unit circuitry <NUM> (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit circuitry <NUM> may further include an address generation unit circuitry (AGU, not shown). In one example, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode unit circuitry <NUM> may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one example, the core <NUM> includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode unit circuitry <NUM> or otherwise within the front end unit circuitry <NUM>). In one example, the decode unit circuitry <NUM> includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline <NUM>. The decode unit circuitry <NUM> may be coupled to rename/allocator unit circuitry <NUM> in the execution engine unit circuitry <NUM>.

The execution engine circuitry <NUM> includes the rename/allocator unit circuitry <NUM> coupled to a retirement unit circuitry <NUM> and a set of one or more scheduler(s) circuitry <NUM>. The scheduler(s) circuitry <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. In some examples, the scheduler(s) circuitry <NUM> can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, arithmetic generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry <NUM> is coupled to the physical register file(s) circuitry <NUM>. Each of the physical register file(s) circuitry <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one example, the physical register file(s) unit circuitry <NUM> includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) unit(s) circuitry <NUM> is overlapped by the retirement unit circuitry <NUM> (also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry <NUM> and the physical register file(s) circuitry <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units circuitry <NUM> and a set of one or more memory access circuitry <NUM>. The execution units circuitry <NUM> may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some examples may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other examples may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry <NUM>, physical register file(s) unit(s) circuitry <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain examples create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) unit circuitry, and/or execution cluster - and in the case of a separate memory access pipeline, certain examples are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

In some examples, the execution engine unit circuitry <NUM> may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AHB) interface (not shown), and address phase and writeback, data phase load, store, and branches.

The set of memory access circuitry <NUM> is coupled to the memory unit circuitry <NUM>, which includes data TLB unit circuitry <NUM> coupled to a data cache circuitry <NUM> coupled to a level <NUM> (L2) cache circuitry <NUM>. In one exemplary example, the memory access units circuitry <NUM> may include a load unit circuitry, a store address unit circuit, and a store data unit circuitry, each of which is coupled to the data TLB circuitry <NUM> in the memory unit circuitry <NUM>. The instruction cache circuitry <NUM> is further coupled to a level <NUM> (L2) cache unit circuitry <NUM> in the memory unit circuitry <NUM>. In one example, the instruction cache <NUM> and the data cache <NUM> are combined into a single instruction and data cache (not shown) in L2 cache unit circuitry <NUM>, a level <NUM> (L3) cache unit circuitry (not shown), and/or main memory. The L2 cache unit circuitry <NUM> is coupled to one or more other levels of cache and eventually to a main memory.

The core <NUM> may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, the core <NUM> includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

<FIG> illustrates examples of execution unit(s) circuitry, such as execution unit(s) circuitry <NUM> of <FIG>. As illustrated, execution unit(s) circuity <NUM> may include one or more ALU circuits <NUM>, vector/SIMD unit circuits <NUM>, load/store unit circuits <NUM>, and/or branch/jump unit circuits <NUM>. ALU circuits <NUM> perform integer arithmetic and/or Boolean operations. Vector/SIMD unit circuits <NUM> perform vector/SIMD operations on packed data (such as SIMD/vector registers). Load/store unit circuits <NUM> execute load and store instructions to load data from memory into registers or store from registers to memory. Load/store unit circuits <NUM> may also generate addresses. Branch/jump unit circuits <NUM> cause a branch or jump to a memory address depending on the instruction. Floating-point unit (FPU) circuits <NUM> perform floating-point arithmetic. The width of the execution unit(s) circuitry <NUM> varies depending upon the example and can range from <NUM>-bit to <NUM>,<NUM>-bit. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two <NUM>-bit execution units are logically combined to form a <NUM>-bit execution unit).

<FIG> is a block diagram of a register architecture <NUM> according to some examples. As illustrated, there are vector/SIMD registers <NUM> that vary from <NUM>-bit to <NUM>,<NUM> bits width. In some examples, the vector/SIMD registers <NUM> are physically <NUM>-bits and, depending upon the mapping, only some of the lower bits are used. For example, in some examples, the vector/SIMD registers <NUM> are ZMM registers which are <NUM> bits: the lower <NUM> bits are used for YMM registers and the lower <NUM> bits are used for XMM registers. As such, there is an overlay of registers. In some examples, a vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length. Scalar operations are operations performed on the lowest order data element position in a ZMM/YMM/XMM register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the example.

In some examples, the register architecture <NUM> includes writemask/predicate registers <NUM>. For example, in some examples, there are <NUM> writemask/predicate registers (sometimes called k0 through k7) that are each <NUM>-bit, <NUM>-bit, <NUM>-bit, or <NUM>-bit in size. Writemask/predicate registers <NUM> may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given writemask/predicate register <NUM> corresponds to a data element position of the destination. In other examples, the writemask/predicate registers <NUM> are scalable and consists of a set number of enable bits for a given vector element (e.g., <NUM> enable bits per <NUM>-bit vector element).

The register architecture <NUM> includes a plurality of general-purpose registers <NUM>. These registers may be <NUM>-bit, <NUM>-bit, <NUM>-bit, etc. and can be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

In some examples, the register architecture <NUM> includes scalar floating-point register <NUM> which is used for scalar floating-point operations on <NUM>/<NUM>/<NUM>-bit floating-point data using the x87 instruction set extension or as MMX registers to perform operations on <NUM>-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

One or more flag registers <NUM> (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers <NUM> may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, the one or more flag registers <NUM> are called program status and control registers.

Segment registers <NUM> contain segment points for use in accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

Machine specific registers (MSRs) <NUM> control and report on processor performance. Most MSRs <NUM> handle system-related functions and are not accessible to an application program. Machine check registers <NUM> consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors.

One or more instruction pointer register(s) <NUM> store an instruction pointer value. Control register(s) <NUM> (e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM>) and the characteristics of a currently executing task. Debug registers <NUM> control and allow for the monitoring of a processor or core's debugging operations.

Memory management registers <NUM> specify the locations of data structures used in protected mode memory management. These registers may include a GDTR, IDRT, task register, and a LDTR register.

Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, less, or different register files and registers.

An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands.

Examples of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Examples of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

<FIG> illustrates examples of an instruction format. As illustrated, an instruction may include multiple components including, but not limited to, one or more fields for: one or more prefixes <NUM>, an opcode <NUM>, addressing information <NUM> (e.g., register identifiers, memory addressing information, etc.), a displacement value <NUM>, and/or an immediate <NUM>. Note that some instructions utilize some or all of the fields of the format whereas others may only use the field for the opcode <NUM>. In some examples, the order illustrated is the order in which these fields are to be encoded, however, it should be appreciated that in other examples these fields may be encoded in a different order, combined, etc..

The prefix(es) field(s) <NUM>, when used, modifies an instruction. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered "legacy" prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the "legacy" prefixes.

The opcode field <NUM> is used to at least partially define the operation to be performed upon a decoding of the instruction. In some examples, a primary opcode encoded in the opcode field <NUM> is <NUM>, <NUM>, or <NUM> bytes in length. In other examples, a primary opcode can be a different length. An additional <NUM>-bit opcode field is sometimes encoded in another field.

The addressing field <NUM> is used to address one or more operands of the instruction, such as a location in memory or one or more registers. <FIG> illustrates examples of the addressing field <NUM>. In this illustration, an optional ModR/M byte <NUM> and an optional Scale, Index, Base (SIB) byte <NUM> are shown. The ModR/M byte <NUM> and the SIB byte <NUM> are used to encode up to two operands of an instruction, each of which is a direct register or effective memory address. Note that each of these fields are optional in that not all instructions include one or more of these fields. The MOD R/M byte <NUM> includes a MOD field <NUM>, a register field <NUM>, and R/M field <NUM>.

The content of the MOD field <NUM> distinguishes between memory access and non-memory access modes. In some examples, when the MOD field <NUM> has a value of b11, a register-direct addressing mode is utilized, and otherwise register-indirect addressing is used.

The register field <NUM> may encode either the destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The content of register index field <NUM>, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some examples, the register field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing.

The R/M field <NUM> may be used to encode an instruction operand that references a memory address, or may be used to encode either the destination register operand or a source register operand. Note the R/M field <NUM> may be combined with the MOD field <NUM> to dictate an addressing mode in some examples.

The SIB byte <NUM> includes a scale field <NUM>, an index field <NUM>, and a base field <NUM> to be used in the generation of an address. The scale field <NUM> indicates scaling factor. The index field <NUM> specifies an index register to use. In some examples, the index field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing. The base field <NUM> specifies a base register to use. In some examples, the base field <NUM> is supplemented with an additional bit from a prefix (e.g., prefix <NUM>) to allow for greater addressing. In practice, the content of the scale field <NUM> allows for the scaling of the content of the index field <NUM> for memory address generation (e.g., for address generation that uses <NUM>scale * index + base).

Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to <NUM>scale * index + base + displacement, index*scale+displacement, r/m + displacement, instruction pointer (RIP/EIP) + displacement, register + displacement, etc. The displacement may be a <NUM>-byte, <NUM>-byte, <NUM>-byte, etc. value. In some examples, a displacement field <NUM> provides this value. Additionally, in some examples, a displacement factor usage is encoded in the MOD field of the addressing field <NUM> that indicates a compressed displacement scheme for which a displacement value is calculated by multiplying disp8 in conjunction with a scaling factor N that is determined based on the vector length, the value of a b bit, and the input element size of the instruction. The displacement value is stored in the displacement field <NUM>.

In some examples, an immediate field <NUM> specifies an immediate for the instruction. An immediate may be encoded as a <NUM>-byte value, a <NUM>-byte value, a <NUM>-byte value, etc..

<FIG> illustrates examples of a first prefix <NUM>(A). In some examples, the first prefix <NUM>(A) is an example of a REX prefix. Instructions that use this prefix may specify general purpose registers, <NUM>-bit packed data registers (e.g., single instruction, multiple data (SIMD) registers or vector registers), and/or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

Instructions using the first prefix <NUM>(A) may specify up to three registers using <NUM>-bit fields depending on the format: <NUM>) using the reg field <NUM> and the R/M field <NUM> of the Mod R/M byte <NUM>; <NUM>) using the Mod R/M byte <NUM> with the SIB byte <NUM> including using the reg field <NUM> and the base field <NUM> and index field <NUM>; or <NUM>) using the register field of an opcode.

In the first prefix <NUM>(A), bit positions <NUM>:<NUM> are set as <NUM>. Bit position <NUM> (W) can be used to determine the operand size, but may not solely determine operand width. As such, when W = <NUM>, the operand size is determined by a code segment descriptor (CS. D) and when W = <NUM>, the operand size is <NUM>-bit.

Note that the addition of another bit allows for <NUM> (<NUM><NUM>) registers to be addressed, whereas the MOD R/M reg field <NUM> and MOD R/M R/M field <NUM> alone can each only address <NUM> registers.

In the first prefix <NUM>(A), bit position <NUM> (R) may an extension of the MOD R/M reg field <NUM> and may be used to modify the ModR/M reg field <NUM> when that field encodes a general purpose register, a <NUM>-bit packed data register (e.g., a SSE register), or a control or debug register. R is ignored when Mod R/M byte <NUM> specifies other registers or defines an extended opcode.

Bit position <NUM> (X) X bit may modify the SIB byte index field <NUM>.

Bit position B (B) B may modify the base in the Mod R/M R/M field <NUM> or the SIB byte base field <NUM>; or it may modify the opcode register field used for accessing general purpose registers (e.g., general purpose registers <NUM>).

<FIG>-(D) illustrate examples of how the R, X, and B fields of the first prefix <NUM>(A) are used. <FIG> illustrates R and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> and R/M field <NUM> of the MOD R/M byte <NUM> when the SIB byte <NUM> is not used for memory addressing. <FIG> illustrates R and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> and R/M field <NUM> of the MOD R/M byte <NUM> when the SIB byte <NUM> is not used (register-register addressing). <FIG> illustrates R, X, and B from the first prefix <NUM>(A) being used to extend the reg field <NUM> of the MOD R/M byte <NUM> and the index field <NUM> and base field <NUM> when the SIB byte <NUM> being used for memory addressing. <FIG> illustrates B from the first prefix <NUM>(A) being used to extend the reg field <NUM> of the MOD R/M byte <NUM> when a register is encoded in the opcode <NUM>.

<FIG>-(B) illustrate examples of a second prefix <NUM>(B). In some examples, the second prefix <NUM>(B) is an example of a VEX prefix. The second prefix <NUM>(B) encoding allows instructions to have more than two operands, and allows SIMD vector registers (e.g., vector/SIMD registers <NUM>) to be longer than <NUM>-bits (e.g., <NUM>-bit and <NUM>-bit). The use of the second prefix <NUM>(B) provides for three-operand (or more) syntax. For example, previous two-operand instructions performed operations such as A = A + B, which overwrites a source operand. The use of the second prefix <NUM>(B) enables operands to perform nondestructive operations such as A = B + C.

In some examples, the second prefix <NUM>(B) comes in two forms - a two-byte form and a three-byte form. The two-byte second prefix <NUM>(B) is used mainly for <NUM>-bit, scalar, and some <NUM>-bit instructions; while the three-byte second prefix <NUM>(B) provides a compact replacement of the first prefix <NUM>(A) and <NUM>-byte opcode instructions.

<FIG> illustrates examples of a two-byte form of the second prefix <NUM>(B). In one example, a format field <NUM> (byte <NUM><NUM>) contains the value C5H. In one example, byte <NUM> includes a "R" value in bit[<NUM>]. This value is the complement of the same value of the first prefix <NUM>(A). Bit[<NUM>] is used to dictate the length (L) of the vector (where a value of <NUM> is a scalar or <NUM>-bit vector and a value of <NUM> is a <NUM>-bit vector). Bits[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). Bits[<NUM>:<NUM>] shown as vvvv may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

Instructions that use this prefix may use the Mod R/M R/M field <NUM> to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.

Instructions that use this prefix may use the Mod R/M reg field <NUM> to encode either the destination register operand or a source register operand, be treated as an opcode extension and not used to encode any instruction operand.

For instruction syntax that support four operands, vvvv, the Mod R/M R/M field <NUM> and the Mod R/M reg field <NUM> encode three of the four operands. Bits[<NUM>:<NUM>] of the immediate <NUM> are then used to encode the third source register operand.

<FIG> illustrates examples of a three-byte form of the second prefix <NUM>(B). in one example, a format field <NUM> (byte <NUM><NUM>) contains the value C4H. Byte <NUM> includes in bits[<NUM>:<NUM>] "R," "X," and "B" which are the complements of the same values of the first prefix <NUM>(A). Bits[<NUM>:<NUM>] of byte <NUM> (shown as mmmmm) include content to encode, as need, one or more implied leading opcode bytes. For example, <NUM> implies a 0FH leading opcode, <NUM> implies a 0F38H leading opcode, <NUM> implies a leading 0F3AH opcode, etc..

Bit[<NUM>] of byte <NUM><NUM> is used similar to W of the first prefix <NUM>(A) including helping to determine promotable operand sizes. Bit[<NUM>] is used to dictate the length (L) of the vector (where a value of <NUM> is a scalar or <NUM>-bit vector and a value of <NUM> is a <NUM>-bit vector). Bits[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). Bits[<NUM>:<NUM>], shown as vvvv, may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

For instruction syntax that support four operands, vvvv, the Mod R/M R/M field <NUM>, and the Mod R/M reg field <NUM> encode three of the four operands. Bits[<NUM>:<NUM>] of the immediate <NUM> are then used to encode the third source register operand.

<FIG> illustrates examples of a third prefix <NUM>(C). In some examples, the first prefix <NUM>(A) is an example of an EVEX prefix. The third prefix <NUM>(C) is a four-byte prefix.

The third prefix <NUM>(C) can encode <NUM> vector registers (e.g., <NUM>-bit, <NUM>-bit, and <NUM>-bit registers) in <NUM>-bit mode. In some examples, instructions that utilize a writemask/opmask (see discussion of registers in a previous figure, such as <FIG>) or predication utilize this prefix. Opmask register allow for conditional processing or selection control. Opmask instructions, whose source/destination operands are opmask registers and treat the content of an opmask register as a single value, are encoded using the second prefix <NUM>(B).

The third prefix <NUM>(C) may encode functionality that is specific to instruction classes (e.g., a packed instruction with "load+op" semantic can support embedded broadcast functionality, a floating-point instruction with rounding semantic can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantic can support "suppress all exceptions" functionality, etc.).

The first byte of the third prefix <NUM>(C) is a format field <NUM> that has a value, in one example, of <NUM>. Subsequent bytes are referred to as payload bytes <NUM>-<NUM> and collectively form a <NUM>-bit value of P[<NUM>:<NUM>] providing specific capability in the form of one or more fields (detailed herein).

In some examples, P[<NUM>:<NUM>] of payload byte <NUM> are identical to the low two mmmmm bits. P[<NUM>:<NUM>] are reserved in some examples. Bit P[<NUM>] (R') allows access to the high <NUM> vector register set when combined with P[<NUM>] and the ModR/M reg field <NUM>. P[<NUM>] can also provide access to a high <NUM> vector register when SIB-type addressing is not needed. P[<NUM>:<NUM>] consist of an R, X, and B which are operand specifier modifier bits for vector register, general purpose register, memory addressing and allow access to the next set of <NUM> registers beyond the low <NUM> registers when combined with the ModR/M register field <NUM> and ModR/M R/M field <NUM>. P[<NUM>:<NUM>] provide opcode extensionality equivalent to some legacy prefixes (e.g., <NUM> = no prefix, <NUM> = <NUM>, <NUM> = F3H, and <NUM> = F2H). P[<NUM>] in some examples is a fixed value of <NUM>. P[<NUM>:<NUM>], shown as vvvv, may be used to: <NUM>) encode the first source register operand, specified in inverted (<NUM> complement) form and valid for instructions with <NUM> or more source operands; <NUM>) encode the destination register operand, specified in <NUM> complement form for certain vector shifts; or <NUM>) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.

P[<NUM>] is similar to W of the first prefix <NUM>(A) and second prefix <NUM>(B) and may serve as an opcode extension bit or operand size promotion.

P[<NUM>:<NUM>] specify the index of a register in the opmask (writemask) registers (e.g., writemask/predicate registers <NUM>). In one example, the specific value aaa = <NUM> has a special behavior implying no opmask is used for the particular instruction (this may be implemented in a variety of ways including the use of a opmask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one example, preserving the old value of each element of the destination where the corresponding mask bit has a <NUM>. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one example, an element of the destination is set to <NUM> when the corresponding mask bit has a <NUM> value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the opmask field allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While examples are described in which the opmask field's content selects one of a number of opmask registers that contains the opmask to be used (and thus the opmask field's content indirectly identifies that masking to be performed), alternative examples instead or additional allow the mask write field's content to directly specify the masking to be performed.

P[<NUM>] can be combined with P[<NUM>:<NUM>] to encode a second source vector register in a non-destructive source syntax which can access an upper <NUM> vector registers using P[<NUM>]. P[<NUM>] encodes multiple functionalities, which differs across different classes of instructions and can affect the meaning of the vector length/ rounding control specifier field (P[<NUM>:<NUM>]). P[<NUM>] indicates support for merging-writemasking (e.g., when set to <NUM>) or support for zeroing and merging-writemasking (e.g., when set to <NUM>).

Exemplary examples of encoding of registers in instructions using the third prefix <NUM>(C) are detailed in the following tables.

Program code may be applied to input instructions to perform the functions described herein and generate output information. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system.

Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Examples may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein.

Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.

<FIG> illustrates a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to examples. In the illustrated example, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. <FIG> shows a program in a high level language <NUM> may be compiled using a first ISA compiler <NUM> to generate first ISA binary code <NUM> that may be natively executed by a processor with at least one first instruction set core <NUM>. The processor with at least one first ISA instruction set core <NUM> represents any processor that can perform substantially the same functions as an Intel® processor with at least one first ISA instruction set core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the instruction set of the first ISA instruction set core or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one first ISA instruction set core, in order to achieve substantially the same result as a processor with at least one first ISA instruction set core. The first ISA compiler <NUM> represents a compiler that is operable to generate first ISA binary code <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one first ISA instruction set core <NUM>. Similarly, <FIG> shows the program in the high level language <NUM> may be compiled using an alternative instruction set compiler <NUM> to generate alternative instruction set binary code <NUM> that may be natively executed by a processor without a first ISA instruction set core <NUM>. The instruction converter <NUM> is used to convert the first ISA binary code <NUM> into code that may be natively executed by the processor without a first ISA instruction set core <NUM>. This converted code is not likely to be the same as the alternative instruction set binary code <NUM> because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have a first ISA instruction set processor or core to execute the first ISA binary code <NUM>.

References to "one example," "an example," etc., indicate that the example described may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. Further, when a particular feature, structure, or characteristic is described in connection with an example, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other examples whether or not explicitly described.

Moreover, in the various examples described above, unless specifically noted otherwise, disjunctive language such as the phrase "at least one of A, B, or C" is intended to be understood to mean either A, B, or C, or any combination thereof (e.g., A, B, and/or C). As such, disjunctive language is not intended to, nor should it be understood to, imply that a given example requires at least one of A, at least one of B, or at least one of C to each be present.

Claim 1:
A method comprising:
Generating and storing (<NUM>) random numbers;
translating (<NUM>, <NUM>) an instance of a single instruction (<NUM>) from a first instruction set architecture to one or more instructions of a second instruction set architecture, the single instruction at least having a field for an opcode, the opcode to indicate execution circuitry is to perform an operation using the random numbers;
decoding (<NUM>, <NUM>) the one or more instructions of the second instruction set architecture; and
executing (<NUM>, <NUM>) the decoded one or more instructions of the second instruction set architecture according to the opcode of the single instruction;
characterized in that the generating and storing occurs during boot and/or during downtime of a processor.