Patent Description:
<FIG> illustrates a radar system <NUM> comprising multiple radar transceiver modules 101a-d, in this case four modules, all mounted on a common PCB <NUM>. A first module 101a is designated a leader module and the other modules 101b-d are designated follower modules. The follower modules 101b-d each obtain a reference clock signal derived from an oscillator <NUM> on the leader module 101a, the reference clock signal being used to generate an ADC sampling clock in each module. Due to imperfections on the board <NUM> or a mismatch between different paths d1-dn connecting the modules, some phase skew may arise between the reference clock signals received at each module. This results in a clock skew of the sampling clock generated by a PLL clock signal generator on each module and leads to limitations in the spatial and velocity resolution of the complete radar system <NUM>.

If the reference clocks received at each module 101a-d could be properly aligned this issue would be improved. This could be done for example by means of a perfectly designed PCB. The production of such a PCB and the phase adjustment, either automatically or by hand, to remove all production spread among the modules can be very expensive and indeed may not be possible at all.

An alternative solution may be to use delay cells or delay lines, which are able to shift the reference phase for each clocking PLL in the system that generates the individual sampling clock for the ADC on each module. However, this again requires a lot of design effort, as well as requiring area and power. Additionally, a delay line may degrade the phase noise of the complete system considerably.

Inter-module mismatch of the delay of the clock path from the reference clock via the PLL clock signal generator towards the ADC sampling stage is another source of clock skew limiting the radar system resolution even for a perfectly matching reference clock distribution.

A further possible solution to align the ADC sampling is to adjust the ADC sampling clock in each module. A delay line could also be used for this purpose. This provides similar restrictions as for a delay line in the reference path with respect to phase noise and area. This solution also needs considerably more power due to the higher frequency.

<FIG> illustrates a series of clock signals, with a first clock signal <NUM> Clk_ADC_L produced by a PLL clock signal generator on the leader transceiver 101a. Each of the follower transceivers 101b-d generate a version of the clock signal <NUM> Clk_ADC_F via their own PLL clock signal generators, which will tend to vary in phase relative to the first clock signal. A version of the clock signal Clk_ADC_F at each follower transceiver 101b-d therefore needs to be adjusted to align its phase with the leader clock signal <NUM>. This may be done by applying a phase adjustment at each follower transceiver, as shown in <FIG> by Sel_Ph_F=<NUM>,<NUM>,<NUM> and <NUM>. The phase shifted signal 202d applying the phase shift Sel_Ph_F=<NUM> most closely matches the leader clock signal <NUM>, so is used for that particular follower module.

All of the above approaches do not take into consideration variation over temperature, supply voltage and aging effects. The delay line approach also results in limitations on the phase noise performance of the reference clock and hence for the complete system.

<CIT> relates to to radar devices and to methods for generating a sampling clock signal.

<CIT> relates to methods and systems of providing one or more phased clock signals to drive electronic circuits.

<CIT> relates to relates to a PLL and a control method for the PLL.

<CIT> relates to a multiphase signal divider.

According to a first aspect there is provided a radar system comprising a plurality of radar transceiver modules mounted to a common PCB, the plurality of radar transceiver modules comprising a leader module and one or more follower modules, the leader module comprising a first oscillator configured to provide a first clock signal at a first frequency to each follower module, each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising:.

The radar system disclosed herein simplifies implementation of leader-follower multi-chip radar sensors mounted on a common PCB and allows for compromises on the phase alignment of the reference clock distribution because this can be compensated for. The radar system enables phase coherent sampling clocks to be generated for ADCs located in different modules by the use of selectable clock phases output from a feedback differential multiphase divider in a PLL. The phases generated may for example have a duty cycle of <NUM> % out of a divide-by-<NUM> divider. The ability to generate multiple phases is self-contained and does not require a control circuit, only a phase select signal to obtain a required phase.

The output of the multiplexer may be connected to an analog to digital converter, ADC, arranged to receive signals from a radar signal receiver.

The number n may be an odd integer of <NUM> or more. Example values for n may be <NUM>, <NUM>, <NUM> or higher. In alternative arrangements n may be an even number, for example an even integer of <NUM>, <NUM>, <NUM> or more.

The divide-by-n clock divider may comprise a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency.

In some examples, the divide by n clock divider may comprise five flip-flops, FFs, arranged to receive the second clock signal from the second oscillator, three OR gates and one AND gate arranged to receive outputs from the FFs. The divide by n clock divider may comprise three inverters connected to a respective OR gate output, <NUM> of the phase shifted clock signals being output by the OR gates and another <NUM> of the phase shifted clock signals being output by the inverters.

In alternative examples, the divide by n clock divider may comprise eight FFs arranged to receive the second clock signal from the second oscillator and six OR gates arranged to receive outputs from the FFs and provide the 2n phase shifted clock signals.

In alternative examples, the divide by n clock divider may comprises five FFs arranged to receive the second clock signal from the second oscillator, three OR gates arranged to receive outputs from the FFs and provide n of the 2n phase shifted clock signals and three AND gates arranged to receive outputs from the FFs and provide another n of the 2n phase shifted clock signals.

In each of the above examples, NOR gates may be used in place of OR gates and NAND gates may be used in place of AND gates.

The first frequency may for example be in a range between around <NUM> and <NUM>.

The third frequency may for example be in a range between around <NUM> and <NUM>.

The radar system may comprise a non-volatile memory configured to store a value of the input phase select signal, the radar system being configured to retrieve a stored value of the input phase select signal for each module during operation of the radar system.

The feedback device may for example be a divide-by-m clock divider, a time-to-digital converter or a combination of both.

According to a second aspect there is provided a method of calibrating a radar system according to the first aspect, the method comprising:.

The calibration method may be carried out once during manufacture of the radar system, for example after mounting the radar transceiver modules on the common PCB. In case of any variation after manufacture, the calibration method may be carried out periodically after manufacture, for example at yearly service intervals.

According to a third aspect there is provided a method of operating a radar system according to the first aspect, the method comprising:.

Embodiments will be described, by way of example only, with reference to the drawings, in which:.

It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar feature in modified and different embodiments.

If the reference phase between the radar transceiver modules 101a-d is fixed and stable on the PCB <NUM> and does not vary after mounting the modules on the PCB, for example due to aging, the sampling clock in each follower module can be phase aligned with respect to the sampling clock of the leader module.

The aim of the present disclosure is to generate ADC sampling clocks for a radar system comprising one or more follower transceiver modules that can be phase-aligned to a reference clock signal from a leader module, preferably with a resolution of less than <NUM> ps and with a duty cycle of <NUM> % derived from a divide-by-<NUM> clock divider.

An example implementation of a PLL <NUM> for generating a clock signal with a selectable phase is illustrated in <FIG>. The PLL <NUM> comprises a divide-by-<NUM> clock divider <NUM> as part of the feedback loop of the PLL <NUM>, which ensures a constant phase relation between the reference clock of the PLL and not only the output clock of the divider <NUM> but with all signal phases output by the divider <NUM>. A differential clock divider system with a clk_p and a clk_n input signal may be obtained from the oscillator <NUM> which have an accurate <NUM>° phase relation, which is typically available from differential circuits and signal processing. This can be achieved by design measures. A multiplexer <NUM> with a phase select control signal <NUM> determines the phase of the output clock signal <NUM>.

The PLL clock signal generator <NUM> comprises a phase comparator <NUM>, a loop filter <NUM>, an oscillator <NUM>, which may be a voltage controlled oscillator (VCO) or digitally controlled oscillator (DCO), a divide-by-n clock divider <NUM>, a feedback device <NUM> and a multiplexer <NUM>. The feedback device <NUM> may for example be a divide-by-m clock divider, a time-to-digital converter or a combination of both. The phase comparator <NUM> receives a first clock signal <NUM> from an oscillator at the leader module, which in this example is a reference clock signal at a reference frequency fref, and a feedback signal <NUM> at the same frequency from the feedback device <NUM>. An output signal <NUM> of the phase comparator <NUM> is provided to the loop filter <NUM>, which provides a control signal <NUM> to the oscillator <NUM>. The oscillator <NUM> generates a second clock signal <NUM> that is provided to the divide-by-n clock divider <NUM>. In a typical example n may be <NUM>, such that the divider <NUM> outputs a series of clock signals <NUM> at different phases, each having a frequency of <NUM>/<NUM> that of the second clock signal. One of the clock signals <NUM> is provided to the feedback device, which divides the clock signal <NUM> to result in a feedback signal <NUM> at the same frequency fref as the input first clock signal <NUM>.

The multiple clock signals <NUM> are input to a multiplexer <NUM>, which selects one of the clock signals <NUM> according to a phase select signal <NUM>, providing a third clock signal <NUM> that is provided to an ADC of the transceiver module.

The PLL clock signal generator <NUM> may be operated by determining the correct phase for each module during product testing of each transceiver module once mounted on the common PCB and then storing the correct setting in a memory. The required phase will be dominantly determined by the layout of the modules on the PCB and can therefore be assumed to be constant.

<FIG> is a schematic diagram of an example radar system <NUM> comprising a plurality of radar transceiver modules <NUM>, <NUM> mounted on a common PCB <NUM>, a first module <NUM> being a leader module and a second module <NUM> being a follower module. The leader module <NUM> comprises a first oscillator <NUM>, which provides a first clock signal at a first frequency. The first clock signal is provided via connection paths <NUM>, <NUM> between the modules <NUM>, <NUM> to each of the modules <NUM>, <NUM>. The connection paths <NUM>, <NUM> are configured to provide the first clock signal as an input to a PLL clock signal generator <NUM><NUM>, <NUM><NUM> in each module. The clock signal generator <NUM><NUM>, <NUM><NUM> in each module <NUM>, <NUM> is of the form described above in relation to <FIG>, with the phase select signal <NUM> being indicated by the signals Sel_Phase_L (for the leader module <NUM>) and Sel_Phase_F (for the follower module <NUM>). The clock signal generator <NUM><NUM>, <NUM><NUM> in each module provides an output clock signal at the appropriate phase to an analog to digital converter <NUM><NUM>, <NUM><NUM>, which receives signals from a radar receiver <NUM><NUM>, <NUM><NUM> in each module <NUM>, <NUM>. Matching the phases of the clock signals provided to each ADC allows the radar system <NUM> to combine the signals from each module <NUM>, <NUM> to obtain a finer resolution. Other components of the radar transceiver modules <NUM>, <NUM> such as the local oscillator (LO), transmitter (TX), chirp signal generator (Chirp PLL) and signal processor (CSI2) that are required to ensure a high resolution radar system will be known to the skilled person and are therefore not described in detail here.

In a test and calibration procedure during manufacture and assembly, once the modules <NUM>, <NUM> are mounted on the PCB <NUM> the modules <NUM>, <NUM> are operated to detect a known target <NUM>. Signals received from the target by the receivers <NUM><NUM>, <NUM><NUM> in each module can be used to select the appropriate phase signal provided to the ADC in each follower module <NUM>. Although only one follower module <NUM> is shown in <FIG>, it will be appreciated that more than one follower module may be provided, with each additional follower module being essentially identical to the follower module <NUM> shown and receiving the same first clock signal from the leader module <NUM>. Once the appropriate phase is selected for each module, the phase select signal <NUM> is saved in non-volatile memory on the radar system <NUM> to be used when the radar system <NUM> is subsequently operated. Each module <NUM>, <NUM> may for example comprise a non-volatile memory <NUM><NUM>, <NUM><NUM> for storing a phase select value to be used when operating the radar system <NUM>. In alternative arrangements a single non-volatile memory may be provided common to each of the radar modules <NUM>, <NUM> and may be provided on one of the modules or separately from the modules.

<FIG>, <FIG> and <FIG> illustrate three different example divider structures for a divide-by-<NUM> clock divider providing a <NUM>% duty cycle output clock signal, each of which receives the second clock signal <NUM> from the VCO/DCO <NUM> and outputs the 2n phase shifted clock signals <NUM>. Each of these examples have in common a differential clock input provided by the VCO/DCO <NUM> and a divide-by-<NUM> arrangement using multiple flip-flops (FFs) providing output signals with a duty cycle of <NUM>% (i.e. <NUM>/<NUM>) or <NUM>% (<NUM>/<NUM>), which is then used to generate multiple output clock signals with a duty cycle of <NUM>%. A differential input clock signal allows the FFs to operate at rising or falling clock edges by just swapping the clock inputs. To achieve a <NUM>% output duty cycle at the divider requires: i) a clock signal from the VCO or DCO with a <NUM>% duty cycle; ii) a divider core providing the clock division (i.e. the first two FFs in the examples shown); iii) a chain of FFs which operate at alternating edges; and iv) logic gates (AND/NAND, OR/NOR) which combine the output signals of two consecutive FFs in the chain of alternatingly clocked FFs. In a general aspect therefore, the second clock signal has a <NUM>% duty cycle and the divide-by-n clock divider comprises a divider core configured to divide the second clock signal into an intermediate clock signal, a chain of flip-flops configured to receive alternating edges of the intermediate clock signal and a plurality of logic gates arranged to combine outputs from consecutive pairs of the chain of flip-flops to provide the output phase shifted clock signals at the third frequency. The intermediate clock signal will have either a <NUM>/<NUM> or <NUM>/<NUM> duty cycle if n is an odd integer, while the output phase shifted clock signals will have a <NUM>% duty cycle. The divider core may be a pair of flip-flops.

The divider output is delayed by half an input clock cycle a number of times. The output with a <NUM>% duty cycle is generated by combining two delayed signals such that the result provides a <NUM>% duty cycle at the divided frequency. <FIG> illustrates a series of clock signals with the input clock signal <NUM>, three intermediate clock signals <NUM>, <NUM>, <NUM> with a <NUM>% duty cycle and differing phases, various delayed versions <NUM> of the intermediate clock signals and the <NUM>% duty cycle output signals <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> at successive phases ranging from <NUM>° to <NUM>° at <NUM>° intervals, resulting from combinations of the intermediate and delayed signals <NUM>-<NUM>.

In the example divider <NUM> in <FIG>, a combination of five flip flops (FFs) <NUM><NUM>-<NUM>, three OR gates <NUM><NUM>-<NUM>, an AND gate <NUM> and three inverters <NUM><NUM>-<NUM> is used to generate six output clock signals <NUM> having a uniformly distributed range of phases in <NUM>° increments. The divider core of the divider <NUM> consists of the first two FFs <NUM><NUM>,<NUM> and the chain of FFs consists of FFs <NUM><NUM>-<NUM>. Opposing phases (<NUM>° and <NUM>°, <NUM>° and <NUM>°, <NUM>° and <NUM>°) are created by inversion using inverters <NUM><NUM>-<NUM>. If the divider structure <NUM> is completely differential, the inversion can be achieved instead simply by wiring and without any additional gates. This way also accurate phase alignment is achieved. The load for all of the FFs <NUM><NUM>-<NUM> may be identical, which may for example be achieved by loading the final FF <NUM><NUM> with a further FF or an equivalent dummy load.

<FIG> shows an alternative clock divider structure <NUM> with <NUM> FFs <NUM><NUM>-<NUM>, one AND gate <NUM> and <NUM> OR gates <NUM><NUM>-<NUM>. The divider core of the divider <NUM> consists of the first two FFs <NUM><NUM>,<NUM> and the chain of FFs consists of FFs <NUM><NUM>-<NUM>. This structure can be implemented in either single ended or differential versions. In both cases, the expected duty cycle is <NUM>%. As with the divider <NUM> in <FIG>, <NUM>° phase alignment can be achieved from the output clock signals <NUM>. However, the number of components in terms of gates and FFs is larger than in the example in <FIG>. The final FF <NUM><NUM> may be loaded by a dummy device to balance the load of the FFs and therefore the propagation delay of the clock phases.

<FIG> illustrates a further alternative clock divider structure <NUM> that needs <NUM> FFs <NUM><NUM>-<NUM>, <NUM> AND-gates <NUM><NUM>-<NUM> and <NUM> OR-gates <NUM><NUM>-<NUM>. The OR gates <NUM><NUM>-<NUM> output the <NUM>°, <NUM>° and <NUM>° phases, while three of the AND gates <NUM><NUM>-<NUM> output inverted versions of these phases, i.e. the <NUM>°, <NUM>° and <NUM>° phases. The divider core of the divider <NUM> consists of the first two FFs <NUM><NUM>,<NUM> and the chain of FFs consists of FFs <NUM><NUM>-<NUM>. In this case, care needs to be taken to ensure an equal load on each branch and to minimise any different delays of the AND and OR-gates to achieve proper phase- and duty-cycle alignment. If delays of AND- and OR-gates can be balanced, the circuit is advantageous compared to the implementation in <FIG> because it does not use inverters for creating the inverted signals, thereby getting rid of the additional inverter delay that may reduce phase accuracy at high operating frequencies.

In each of the clock divider designs described above and shown in <FIG>, <FIG> and <FIG>, careful design and layout is essential to ensure that every FF and every gate gets the same load, which may include the usage of dummy load stages not shown in <FIG>, <FIG> and <FIG>. Further care needs to be taken to minimize the phase noise contribution of the divider.

It will be appreciated that each of the clock divider structures <NUM>, <NUM>, <NUM> are only examples where n=<NUM> and each may be extended further to higher values for n (where n is an odd integer) by adding further FFs and gates to achieve a higher number of phases in the output signals <NUM>. The concept of overlaying differential phases with a duty cycle that differs from <NUM>% can be extended to any odd divider ratio such as a divide-by-<NUM> or divide-by-<NUM> divider to achieve a duty cycle of <NUM>% and to allow phase selection with a resolution up to <NUM>°/2n, where n is the divider ratio, i.e. a resolution of <NUM>° for a divide by three divider, a resolution of <NUM>° for a divide by <NUM> divider, a resolution of around <NUM>° for a divide by <NUM> divider and so on.

Using such a divider enables a solution to the problem of generating a <NUM>% duty cycle clock signal with an odd division ratio and including a phase shifter for multi-module phase alignment without additional costly circuits such as delay lines.

The clock signal dividers disclosed herein can be used to generate phase coherent sampling clocks for ADCs located in different modules by selecting a clock phase of a feedback differential multiphase divider in a PLL. The phases generated can have an accurate duty cycle of <NUM>% from a divide-by-n divider where n is an odd integer of <NUM> or more.

<FIG> is a schematic diagram illustrating a method of calibrating a radar system of the type disclosed herein. In a first step <NUM>, each of the plurality of radar transceiver modules is operated, and in a second step <NUM> a known target is detected. In step <NUM>, a phase select signal is determined that minimises a difference in phase between the third clock signal in each follower module and in the leader module. In step <NUM>, the phase select signal is stored in memory for each of the radar transceiver modules.

<FIG> is a schematic diagram illustrating a method of operating a radar system of the type disclosed herein. In a first step <NUM>, a phase select signal is retrieved from memory for each of the radar transceiver modules. In a second step <NUM>, the radar transceiver modules are operated using the retrieved phase select signals for the divide by n clock signal divider of each module.

From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of radar systems, and which may be used instead of, or in addition to, features already described herein.

Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment.

Claim 1:
A radar system (<NUM>) comprising a plurality of radar transceiver modules (<NUM>, <NUM>) mounted to a common PCB (<NUM>), the plurality of radar transceiver modules comprising a leader module (<NUM>) and one or more follower modules (<NUM>), the leader module (<NUM>) comprising a first oscillator (<NUM>) configured to provide a first clock signal at a first frequency to each follower module (<NUM>), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (<NUM>) comprising:
a phase comparator (<NUM>) connected to receive the first clock signal and a feedback signal;
a loop filter (<NUM>) connected to receive an output signal from the phase comparator (<NUM>);
a second oscillator (<NUM>) connected to receive an output signal from the loop filter (<NUM>) and generate a second clock signal at a second frequency;
a divide by n clock divider (<NUM>) connected to receive the second clock signal (<NUM>) from the second oscillator (<NUM>) and to output 2n phase shifted clock signals (<NUM>) at a third frequency;
a feedback device (<NUM>) connected to receive one of the phase shifted clock signals from the divide by n clock divider (<NUM>) and provide the feedback signal to the phase comparator (<NUM>); and
a multiplexer (<NUM>) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (<NUM>) and output a third clock signal (<NUM>) selected by an input phase select signal (<NUM>).