Patent Description:
Diffraction gratings are used in many systems. Diffraction gratings can be characterized based on wavelength, angle, efficiency, size, cost, etc. Diffraction gratings with high efficiency and low cost are desirable.

<CIT>, <CIT> and <CIT> disclose some diffraction gratings.

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications consistent with the appended claims.

The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).

Referring now to <FIG> and <FIG>, in one example outside the scope of the claimed invention, a diffraction grating <NUM> has a number of grating lines <NUM> extending from a substrate <NUM>. <FIG> shows a side (or cross-section) view of the diffraction grating <NUM>, and <FIG> shows a top-down view of the diffraction grating <NUM>. In the illustrative example, an anti-reflection coating <NUM> is on a surface of the substrate <NUM> opposite the grating lines <NUM>. <FIG> shows a side (or cross-section) view of the diffraction grating <NUM>. In the illustrative example, each grating line <NUM> includes one or more sub-lines <NUM>, as discussed in more detail below. An anti-reflection coating <NUM> may be on the end of each grating line <NUM>. The grating lines <NUM> may have any suitable spacing, such as <NUM>-<NUM>,<NUM> grating lines per millimeter, depending on the operating wavelength and other parameters. The grating lines <NUM> may extend from the substrate <NUM> by any suitable amount, such as <NUM>-<NUM> micrometers.

In use, light incident on the diffraction grating <NUM> is diffracted into one or more orders. Most of the light is refracted into a first order (or negative first order). The efficiency of the diffraction grating <NUM> is the amount of light that is diffracted into the first order (or negative first order). The diffraction grating <NUM> may be a transmission or reflection grating. The diffraction grating <NUM> may be used in any suitable configuration, such as a Littrow configuration.

The diffraction grating <NUM> may be any suitable dimensions. The diffraction grating <NUM> is formed using photolithography techniques. For example, a diffraction grating <NUM> may be formed from a silicon wafer with a <NUM> millimeter diameter. A single wafer may be formed into a single diffraction grating <NUM>, or a single wafer may be formed into multiple diffraction gratings <NUM>. The diffraction grating <NUM> may have any suitable thickness, such as <NUM>-<NUM>,<NUM> micrometers. In the illustrative embodiment, the diffraction grating <NUM> may be <NUM>-<NUM> micrometers thick. The diffraction grating <NUM> may have any suitable shape, such as square, rectangular, circular, etc. The diffraction grating <NUM> may be designed to operate at any suitable wavelength or wavelength range, such as O band (about <NUM>,<NUM>-<NUM>,<NUM> nanometers), C band (about <NUM>,<NUM>-<NUM>,<NUM> nanometers), L band, S band, etc. In the illustrative embodiment, the diffraction grating <NUM> is designed to operate in the O band. The dispersion of the diffraction grating <NUM> may be any suitable amount, such as <NUM>-<NUM> degrees per nanometer. In some embodiments, the dispersion of the diffraction grating <NUM> may be <NUM>, <NUM>, or <NUM> degrees per nanometer.

The substrate <NUM> and the grating lines <NUM> are silicon. In other embodiments, other substrate material may be used, such as a III-V substrate, an oxide, etc. Each anti-reflection coating <NUM>, <NUM> is silicon nitride. Other materials may be used for the anti-reflection coatings <NUM>, <NUM>, such as silicon oxide. In some embodiments, the grating lines <NUM> may be a different material from the substrate <NUM>. For example, in one embodiment, the grating lines <NUM> may be silicon nitride, and the substrate <NUM> may be silicon, as shown in <FIG>.

Each anti-reflection coating <NUM>, <NUM> may have any suitable thickness. The thickness of the anti-reflection coating <NUM>, <NUM> may be selected so that the reflection from the anti-reflection coating <NUM>, <NUM> approximately cancels the reflection from the substrate <NUM> at a particular wavelength and incidence angle, etc..

Referring now to <FIG>, in one embodiment, one grating line <NUM> has three separate sub-lines, sub-line 106A, 106B, and 106C. Sub-line 106A is the widest, followed by sub-line 106B, followed by 106C. The change in width of the sub-lines <NUM> results in the effective index of refraction of the grating line <NUM> changing as a function of position, which causes a similar effect as blazing the grating.

The spacing between grating lines <NUM> may be any suitable value, such as <NUM>-<NUM> micrometers. In the illustrative embodiment, the spacing between grating lines <NUM> is about one micrometer. The width of and spacing between each sub-line <NUM> may be any suitable value. For example, the width of and/or spacing between each sub-line <NUM> may be <NUM>-<NUM> micrometers. Each sub-line 106A, 106B, 106C has a corresponding anti-reflection coating 108A, 108B, 108C. The length (i.e., the amount of extension from the substrate <NUM>) of each sub-line <NUM> may be any suitable value, such as <NUM>-<NUM> micrometers. The length of each sub-line <NUM> is <NUM>-<NUM> micrometers.

Referring now to <FIG>, in one embodiment, a diffraction grating <NUM> has a substrate <NUM>, a plurality of grating lines <NUM>, and an anti-reflection coating <NUM> on the surface of the substrate <NUM> opposite the grating lines <NUM>. The diffraction grating <NUM> also has an etch stop layer <NUM>. The presence of the etch stop layer <NUM> can improve uniformity of the depth of the grating lines <NUM> as they are etched. The etch stop layer <NUM> may be any suitable material that can resist the etch used to etch the grating lines <NUM>. In the illustrative embodiment, the etch stop layer <NUM> is silicon dioxide. The dimensions and other design and performance parameters of the diffraction grating <NUM> may be similar to those of the diffraction grating <NUM>.

In the illustrative embodiment, the grating lines <NUM> of the diffraction grating <NUM> are a different material from the substrate <NUM>. For example, the grating lines <NUM> may be silicon nitride and the substrate may be silicon. The diffraction grating <NUM> may also include an anti-reflection coating <NUM> between the substrate <NUM> and the etch stop <NUM>.

The dimensions of the substrate <NUM>, anti-reflection coatings <NUM>, <NUM>, and grating lines <NUM> may be any suitable dimensions, similar to the corresponding components of the diffraction grating <NUM>. The etch stop layer <NUM> may have any suitable thickness, such as <NUM>-<NUM> micrometers. In the illustrative embodiment, the anti-reflection coating <NUM> has a thickness of <NUM> micrometers, the substrate <NUM> has a thickness of <NUM> micrometers, the anti-reflection coating <NUM> has a thickness of <NUM> micrometers, the etch stop layer <NUM> has a thickness of <NUM> micrometers, the grating lines <NUM> have a thickness of <NUM> micrometers, each grating line <NUM> has a width of <NUM> micrometers, and the grating line spacing is <NUM> micrometers (i.e., the empty space between each grating line <NUM> is <NUM> micrometers). In the illustrative embodiment, the diffraction grating <NUM> is operated in a Littrow configuration.

In the illustrative embodiment, the grating <NUM> is designed to have gratings lines <NUM> that extend perpendicularly from the substrate <NUM>, as shown in <FIG>. In some embodiments, the grating lines <NUM> may have a slight slope as they extend from the substrate <NUM>, leading to grating lines <NUM> with a trapezoidal shape shown in <FIG>. The slope may be from manufacturing imperfections or may be a design parameter.

Referring now to <FIG>, in one embodiment, a diffraction grating <NUM> has a substrate <NUM>, a plurality of grating lines <NUM>, and an anti-reflection coating <NUM> on the surface of the substrate <NUM> opposite the grating lines <NUM>. The diffraction grating <NUM> also has an etch stop layer <NUM>, and an anti-reflection coating <NUM> between the substrate <NUM> and the etch stop layer <NUM>. The dimensions of the diffraction grating <NUM> may be similar to those of the diffraction grating <NUM>. The gratings lines <NUM>, etch stop <NUM>, and substrate <NUM> may be similar to the corresponding components of the diffraction grating <NUM>.

In the illustrative embodiment, the anti-reflection coating <NUM> includes four layers: a first layer <NUM> of silicon oxide, a first layer <NUM> of silicon nitride, a second layer <NUM> of silicon oxide, and a second layer of silicon nitride <NUM>. In the illustrative embodiment, the layer <NUM> is <NUM> micrometers thick, the layer <NUM> is <NUM> micrometers thick, the layer <NUM> is <NUM> micrometers thick, and the layer <NUM> is <NUM> micrometers thick. The anti-reflection coating <NUM> may be similar to the anti-reflection coating <NUM> in a reverse order. That is, the layer <NUM> may be similar to layer <NUM>, the layer <NUM> may be similar to the layer <NUM>, the layer <NUM> may be similar to the layer <NUM>, and the layer <NUM> may be similar to the layer <NUM>. In the illustrative embodiment the index of refraction of the silicon nitride layers <NUM>, <NUM>, <NUM>, <NUM> is about <NUM>, and the index of refraction of the silicon oxide layers <NUM>, <NUM>, <NUM>, <NUM> is about <NUM>. In the illustrative embodiment, the index of refraction of the silicon oxide etch stop layer is about <NUM>. The etch stop layer <NUM> may be about <NUM> micrometers thick, with about <NUM> micrometers of the etch stop layer <NUM> etched away.

Referring now to <FIG>, in one embodiment, a plot <NUM> shows a simulated efficiency of the diffraction grating <NUM> is shown as a function of different line widths of the grating line <NUM> for several angles of incidence relative to a design angle of incidence. The plot <NUM> includes a line <NUM> showing efficiency for a <NUM> degree angle relative to a design angle, a line <NUM> showing efficiency for an <NUM> degree angle relative to a design angle, a line <NUM> showing efficiency for a negative <NUM> degree angle relative to a design angle, and a line <NUM> showing efficiency for a negative <NUM> degree angle relative to a design angle. As shown in the plot, the efficiency is relatively insensitive to fluctuations in the width of the grating lines <NUM> of, e.g., plus or minus <NUM> nanometers.

Referring now to <FIG>, in one embodiment, a plot <NUM> shows a simulated efficiency of the diffraction grating <NUM> is shown as a function of different a slope of the grating line <NUM> from vertical for several angles of incidence relative to a design angle of incidence. In the illustrative embodiment, the grating lines <NUM> extend perpendicularly out from the substrate <NUM>. The plot <NUM> shows the efficiency of the diffraction grating <NUM> as walls of the grating lines <NUM> slightly deviate from perpendicular to the surface of the substrate <NUM>, forming a trapezoidal shape, as shown in <FIG>. The plot <NUM> includes a line <NUM> showing efficiency for a <NUM> degree angle relative to a design angle, a line <NUM> showing efficiency for an <NUM> degree angle relative to a design angle, a line <NUM> showing efficiency for a negative <NUM> degree angle relative to a design angle, and a line <NUM> showing efficiency for a negative <NUM> degree angle relative to a design angle. As shown in the plot, the efficiency is relatively insensitive to fluctuations in the angle of the walls of the grating lines <NUM> of, e.g., plus or minus <NUM> degrees.

Referring now to <FIG>, in one embodiment, a plot <NUM> shows a simulated efficiency of the diffraction grating <NUM> is shown as a function of different the index of refraction of the grating lines <NUM>. In the illustrative embodiment, the grating lines <NUM> are silicon nitride with an index of refraction of about <NUM>. If the silicon nitride has a different index of refraction due to imperfections or contaminants, the efficiency of the diffraction grating <NUM> may be affected. The plot <NUM> shows the efficiency of the grating <NUM> as a function of the index of refraction. The plot <NUM> includes a line <NUM> showing efficiency for a <NUM> degree angle relative to a design angle, a line <NUM> showing efficiency for an <NUM> degree angle relative to a design angle, a line <NUM> showing efficiency for a negative <NUM> degree angle relative to a design angle, and a line <NUM> showing efficiency for a negative <NUM> degree angle relative to a design angle. As shown in the plot, the efficiency is relatively insensitive to fluctuations in the index of refraction.

Referring now to <FIG>, in one embodiment, a flowchart for a method <NUM> for creating the diffraction grating <NUM>, <NUM> is shown. The method <NUM> may be executed by a technician and/or by one or more automated machines. In some embodiments, one or more machines may be programmed to do some or all of the steps of the method <NUM>. Such a machine may include, e.g., a memory, a processor, data storage, etc. The memory and/or data storage may store instructions that, when executed by the machine, causes the machine to perform some or all of the steps of the method <NUM>. The method <NUM> may use any suitable set of techniques that are used in semiconductor processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, photolithography, ion implantation, dry etching, wet etching, thermal treatments, flip chip, layer transfer, magnetron sputter deposition, pulsed laser deposition, etc. It should be appreciated that the method <NUM> is merely one embodiment of a method to create the diffraction grating <NUM> or <NUM>, and other methods may be used to create the diffraction grating <NUM> or <NUM>. In some embodiments, steps of the method <NUM> may be performed in a different order than that shown in the flowchart.

The method <NUM> begins in block <NUM>, in which an antireflection coating is created on a substrate of a wafer, such as the antireflection coating <NUM> on the substrate <NUM>. The substrate <NUM> may be, e.g., silicon, and the antireflection coating <NUM> may be, e.g., silicon nitride. The wafer may be any suitable size, such as a wafer with a <NUM>-<NUM> millimeter diameter.

In block <NUM>, an etch stop layer may be grown on the substrate (or on the antireflection coating on the substrate). For example, the etch stop layer <NUM> may be grown on the antireflection layer <NUM> or the substrate <NUM>.

In block <NUM>, a layer is grown over the etch stop layer. That layer is the layer that will be etched to form the grating lines of the diffraction grating. The layer may be any suitable material, such as silicon nitride. In block <NUM>, another antireflection coating is applied on top, such as the antireflection coating <NUM>.

In block <NUM>, the grating lines are etched. In the illustrative embodiment, the grating lines are etched in the layer grown in block <NUM> until reaching the etch stop layer deposited in block <NUM>. In other embodiments, the grating lines may be etched directly into the substrate of the wafer. Any suitable etching technique may be used, such as plasma-enhanced etching. In the illustrative embodiment, etching may be done with a precision of less than <NUM> nanometers in all dimensions across the entire wafer, leading to a high yield.

In block <NUM>, in some embodiments, the wafer is flipped over. Before the wafer is flipped, a protective layer may be applied to the diffraction grating to prevent damage. In block <NUM>, an antireflection coating may be applied to the back side of the wafer, such as the antireflection coating <NUM> or <NUM>.

In block <NUM>, the wafer is singulated into dies with diffraction gratings. The diffraction gratings may be integrated with other optics (such as mirrors, lenses, light sources, detectors, etc.) into a package for use.

The diffraction gratings disclosed above may be incorporated into various systems. For example, in one embodiment, a diffraction grating may be incorporated into a light detection and ranging (LIDAR) system. The LIDAR system may be incorporated with an autonomous vehicle, an autonomous robot, a drone, a ranging system, and/or any other suitable system. A system including the diffraction grating may include, e.g., one or more computing devices, processors, memory devices, storage devices, etc..

<FIG> is a top view of a wafer <NUM> and dies <NUM> that may be included in any of the suitable system disclosed herein. The wafer <NUM> may be composed of semiconductor material and may include one or more dies <NUM> having integrated circuit structures formed on a surface of the wafer <NUM>. The individual dies <NUM> may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer <NUM> may undergo a singulation process in which the dies <NUM> are separated from one another to provide discrete "chips" of the integrated circuit product. In some embodiments, the die <NUM> may be or include any of the diffraction gratings disclosed herein. The die <NUM> may include one or more transistors (e.g., some of the transistors <NUM> of <FIG>, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other integrated circuit components. In some embodiments, the wafer <NUM> or the die <NUM> may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die <NUM>. For example, a memory array formed by multiple memory devices may be formed on a same die <NUM> as a processor unit (e.g., the processor unit <NUM> of <FIG>) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. Various ones of the components disclosed herein may be manufactured using a die-to-wafer assembly technique in which some dies are attached to a wafer <NUM> that include others of the dies, and the wafer <NUM> is subsequently singulated.

<FIG> is a cross-sectional side view of an integrated circuit device <NUM> that may be included in any suitable system disclosed herein. One or more of the integrated circuit devices <NUM> may be included in one or more dies <NUM> (<FIG>). The integrated circuit device <NUM> may be formed on a die substrate <NUM> (e.g., the wafer <NUM> of <FIG>) and may be included in a die (e.g., the die <NUM> of <FIG>). The die substrate <NUM> may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate <NUM> may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate <NUM> may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate <NUM>. Although a few examples of materials from which the die substrate <NUM> may be formed are described here, any material that may serve as a foundation for an integrated circuit device <NUM> may be used. The die substrate <NUM> may be part of a singulated die (e.g., the dies <NUM> of <FIG>) or a wafer (e.g., the wafer <NUM> of <FIG>).

The integrated circuit device <NUM> may include one or more device layers <NUM> disposed on the die substrate <NUM>. The device layer <NUM> may include features of one or more transistors <NUM> (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate <NUM>. The transistors <NUM> may include, for example, one or more source and/or drain (S/D) regions <NUM>, a gate <NUM> to control current flow between the S/D regions <NUM>, and one or more S/D contacts <NUM> to route electrical signals to/from the S/D regions <NUM>. The transistors <NUM> may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors <NUM> are not limited to the type and configuration depicted in <FIG> and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non- planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.

<FIG> are simplified perspective views of example planar, FinFET, gate-all-around, and stacked gate-all-around transistors. The transistors illustrated in <FIG> are formed on a substrate <NUM> having a surface <NUM>. Isolation regions <NUM> separate the source and drain regions of the transistors from other transistors and from a bulk region <NUM> of the substrate <NUM>.

<FIG> is a perspective view of an example planar transistor <NUM> comprising a gate <NUM> that controls current flow between a source region <NUM> and a drain region <NUM>. The transistor <NUM> is planar in that the source region <NUM> and the drain region <NUM> are planar with respect to the substrate surface <NUM>.

<FIG> is a perspective view of an example FinFET transistor <NUM> comprising a gate <NUM> that controls current flow between a source region <NUM> and a drain region <NUM>. The transistor <NUM> is non-planar in that the source region <NUM> and the drain region <NUM> comprise "fins" that extend upwards from the substrate surface <NUM>. As the gate <NUM> encompasses three sides of the semiconductor fin that extends from the source region <NUM> to the drain region <NUM>, the transistor <NUM> can be considered a tri-gate transistor. <FIG> illustrates one S/D fin extending through the gate <NUM>, but multiple S/D fins can extend through the gate of a FinFET transistor.

<FIG> is a perspective view of a gate-all-around (GAA) transistor <NUM> comprising a gate <NUM> that controls current flow between a source region <NUM> and a drain region <NUM>. The transistor <NUM> is non-planar in that the source region <NUM> and the drain region <NUM> are elevated from the substrate surface <NUM>.

<FIG> is a perspective view of a GAA transistor <NUM> comprising a gate <NUM> that controls current flow between multiple elevated source regions <NUM> and multiple elevated drain regions <NUM>. The transistor <NUM> is a stacked GAA transistor as the gate controls the flow of current between multiple elevated S/D regions stacked on top of each other. The transistors <NUM> and <NUM> are considered gate-all-around transistors as the gates encompass all sides of the semiconductor portions that extends from the source regions to the drain regions. The transistors <NUM> and <NUM> can alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors depending on the width (e.g., widths <NUM> and <NUM> of transistors <NUM> and <NUM>, respectively) of the semiconductor portions extending through the gate.

Returning to <FIG>, a transistor <NUM> may include a gate <NUM> formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.

The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor <NUM> is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

In some embodiments, when viewed as a cross-section of the transistor <NUM> along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate <NUM> and two sidewall portions that are substantially perpendicular to the top surface of the die substrate <NUM>. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate <NUM> and does not include sidewall portions substantially perpendicular to the top surface of the die substrate <NUM>. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

The S/D regions <NUM> may be formed within the die substrate <NUM> adjacent to the gate <NUM> of individual transistors <NUM>. The S/D regions <NUM> may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate <NUM> to form the S/D regions <NUM>. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate <NUM> may follow the ion-implantation process. In the latter process, the die substrate <NUM> may first be etched to form recesses at the locations of the S/D regions <NUM>. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions <NUM>. In some implementations, the S/D regions <NUM> may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions <NUM> may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions <NUM>.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors <NUM>) of the device layer <NUM> through one or more interconnect layers disposed on the device layer <NUM> (illustrated in <FIG> as interconnect layers <NUM>-<NUM>). For example, electrically conductive features of the device layer <NUM> (e.g., the gate <NUM> and the S/D contacts <NUM>) may be electrically coupled with the interconnect structures <NUM> of the interconnect layers <NUM>-<NUM>. The one or more interconnect layers <NUM>-<NUM> may form a metallization stack (also referred to as an "ILD stack") <NUM> of the integrated circuit device <NUM>.

The interconnect structures <NUM> may be arranged within the interconnect layers <NUM>-<NUM> to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures <NUM> depicted in <FIG>. Although a particular number of interconnect layers <NUM>-<NUM> is depicted in <FIG>, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures <NUM> may include lines 1128a and/or vias 1128b filled with an electrically conductive material such as a metal. The lines 1128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate <NUM> upon which the device layer <NUM> is formed. For example, the lines 1128a may route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias 1128b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate <NUM> upon which the device layer <NUM> is formed. In some embodiments, the vias 1128b may electrically couple lines 1128a of different interconnect layers <NUM>-<NUM> together.

The interconnect layers <NUM>-<NUM> may include a dielectric material <NUM> disposed between the interconnect structures <NUM>, as shown in <FIG>. In some embodiments, dielectric material <NUM> disposed between the interconnect structures <NUM> in different ones of the interconnect layers <NUM>-<NUM> may have different compositions; in other embodiments, the composition of the dielectric material <NUM> between different interconnect layers <NUM>-<NUM> may be the same. The device layer <NUM> may include a dielectric material <NUM> disposed between the transistors <NUM> and a bottom layer of the metallization stack as well. The dielectric material <NUM> included in the device layer <NUM> may have a different composition than the dielectric material <NUM> included in the interconnect layers <NUM>-<NUM>; in other embodiments, the composition of the dielectric material <NUM> in the device layer <NUM> may be the same as a dielectric material <NUM> included in any one of the interconnect layers <NUM>-<NUM>.

A first interconnect layer <NUM> (referred to as Metal <NUM> or "M1") may be formed directly on the device layer <NUM>. In some embodiments, the first interconnect layer <NUM> may include lines 1128a and/or vias 1128b, as shown. The lines 1128a of the first interconnect layer <NUM> may be coupled with contacts (e.g., the S/D contacts <NUM>) of the device layer <NUM>. The vias 1128b of the first interconnect layer <NUM> may be coupled with the lines 1128a of a second interconnect layer <NUM>.

The second interconnect layer <NUM> (referred to as Metal <NUM> or "M2") may be formed directly on the first interconnect layer <NUM>. In some embodiments, the second interconnect layer <NUM> may include via 1128b to couple the lines <NUM> of the second interconnect layer <NUM> with the lines 1128a of a third interconnect layer <NUM>. Although the lines 1128a and the vias 1128b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 1128a and the vias 1128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

The third interconnect layer <NUM> (referred to as Metal <NUM> or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer <NUM> according to similar techniques and configurations described in connection with the second interconnect layer <NUM> or the first interconnect layer <NUM>. In some embodiments, the interconnect layers that are "higher up" in the metallization stack <NUM> in the integrated circuit device <NUM> (i.e., farther away from the device layer <NUM>) may be thicker that the interconnect layers that are lower in the metallization stack <NUM>, with lines 1128a and vias 1128b in the higher interconnect layers being thicker than those in the lower interconnect layers.

The integrated circuit device <NUM> may include a solder resist material <NUM> (e.g., polyimide or similar material) and one or more conductive contacts <NUM> formed on the interconnect layers <NUM>-<NUM>. In <FIG>, the conductive contacts <NUM> are illustrated as taking the form of bond pads. The conductive contacts <NUM> may be electrically coupled with the interconnect structures <NUM> and configured to route the electrical signals of the transistor(s) <NUM> to external devices. For example, solder bonds may be formed on the one or more conductive contacts <NUM> to mechanically and/or electrically couple an integrated circuit die including the integrated circuit device <NUM> with another component (e.g., a printed circuit board). The integrated circuit device <NUM> may include additional or alternate structures to route the electrical signals from the interconnect layers <NUM>-<NUM>; for example, the conductive contacts <NUM> may include other analogous features (e.g., posts) that route the electrical signals to external components.

In some embodiments in which the integrated circuit device <NUM> is a double-sided die, the integrated circuit device <NUM> may include another metallization stack (not shown) on the opposite side of the device layer(s) <NUM>. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers <NUM>-<NUM>, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) <NUM> and additional conductive contacts (not shown) on the opposite side of the integrated circuit device <NUM> from the conductive contacts <NUM>.

In other embodiments in which the integrated circuit device <NUM> is a double-sided die, the integrated circuit device <NUM> may include one or more through silicon vias (TSVs) through the die substrate <NUM>; these TSVs may make contact with the device layer(s) <NUM>, and may provide conductive pathways between the device layer(s) <NUM> and additional conductive contacts (not shown) on the opposite side of the integrated circuit device <NUM> from the conductive contacts <NUM>. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device <NUM> from the conductive contacts <NUM> to the transistors <NUM> and any other components integrated into the die <NUM>, and the metallization stack <NUM> can be used to route I/O signals from the conductive contacts <NUM> to transistors <NUM> and any other components integrated into the die <NUM>.

Multiple integrated circuit devices <NUM> may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

<FIG> is a cross-sectional side view of an integrated circuit device assembly <NUM>. The integrated circuit device assembly <NUM> includes a number of components disposed on a circuit board <NUM> (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly <NUM> includes components disposed on a first face <NUM> of the circuit board <NUM> and an opposing second face <NUM> of the circuit board <NUM>; generally, components may be disposed on one or both faces <NUM> and <NUM>.

In some embodiments, the circuit board <NUM> may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board <NUM>. In other embodiments, the circuit board <NUM> may be a non-PCB substrate. The integrated circuit device assembly <NUM> illustrated in <FIG> includes a package-on-interposer structure <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may electrically and mechanically couple the package-on-interposer structure <NUM> to the circuit board <NUM>, and may include solder balls (as shown in <FIG>), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure <NUM> may include an integrated circuit component <NUM> coupled to an interposer <NUM> by coupling components <NUM>. The coupling components <NUM> may take any suitable form for the application, such as the forms discussed above with reference to the coupling components <NUM>. Although a single integrated circuit component <NUM> is shown in <FIG>, multiple integrated circuit components may be coupled to the interposer <NUM>; indeed, additional interposers may be coupled to the interposer <NUM>. The interposer <NUM> may provide an intervening substrate used to bridge the circuit board <NUM> and the integrated circuit component <NUM>.

The integrated circuit component <NUM> may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die <NUM> of <FIG>, the integrated circuit device <NUM> of <FIG>) and/or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component <NUM>, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer <NUM>. The integrated circuit component <NUM> can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller. In some embodiments, the integrated circuit component <NUM> can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

In embodiments where the integrated circuit component <NUM> comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).

In addition to comprising one or more processor units, the integrated circuit component <NUM> can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as "chiplets". In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.

Generally, the interposer <NUM> may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer <NUM> may couple the integrated circuit component <NUM> to a set of ball grid array (BGA) conductive contacts of the coupling components <NUM> for coupling to the circuit board <NUM>. In the embodiment illustrated in <FIG>, the integrated circuit component <NUM> and the circuit board <NUM> are attached to opposing sides of the interposer <NUM>; in other embodiments, the integrated circuit component <NUM> and the circuit board <NUM> may be attached to a same side of the interposer <NUM>. In some embodiments, three or more components may be interconnected by way of the interposer <NUM>.

In some embodiments, the interposer <NUM> may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through hole vias <NUM>-<NUM> (that extend from a first face <NUM> of the interposer <NUM> to a second face <NUM> of the interposer <NUM>), blind vias <NUM>-<NUM> (that extend from the first or second faces <NUM> or <NUM> of the interposer <NUM> to an internal metal layer), and buried vias <NUM>-<NUM> (that connect internal metal layers).

In some embodiments, the interposer <NUM> can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer <NUM> comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer <NUM> to an opposing second face of the interposer <NUM>.

The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer <NUM>. The package-on-interposer structure <NUM> may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board.

The integrated circuit device assembly <NUM> may include an integrated circuit component <NUM> coupled to the first face <NUM> of the circuit board <NUM> by coupling components <NUM>. The coupling components <NUM> may take the form of any of the embodiments discussed above with reference to the coupling components <NUM>, and the integrated circuit component <NUM> may take the form of any of the embodiments discussed above with reference to the integrated circuit component <NUM>.

The integrated circuit device assembly <NUM> illustrated in <FIG> includes a package-on-package structure <NUM> coupled to the second face <NUM> of the circuit board <NUM> by coupling components <NUM>. The package-on-package structure <NUM> may include an integrated circuit component <NUM> and an integrated circuit component <NUM> coupled together by coupling components <NUM> such that the integrated circuit component <NUM> is disposed between the circuit board <NUM> and the integrated circuit component <NUM>. The coupling components <NUM> and <NUM> may take the form of any of the embodiments of the coupling components <NUM> discussed above, and the integrated circuit components <NUM> and <NUM> may take the form of any of the embodiments of the integrated circuit component <NUM> discussed above. The package-on-package structure <NUM> may be configured in accordance with any of the package-on-package structures known in the art.

<FIG> is a block diagram of an example electrical device <NUM> that may include one or more of the components disclosed herein. For example, any suitable ones of the components of the electrical device <NUM> may include one or more of the integrated circuit device assemblies <NUM>, integrated circuit components <NUM>, integrated circuit devices <NUM>, or integrated circuit dies <NUM> disclosed herein. In some embodiments, the electrical device <NUM> may be a LIDAR system, including a light source, a diffraction grating <NUM>, <NUM>, and a detector. A number of components are illustrated in <FIG> as included in the electrical device <NUM>, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device <NUM> may be attached to one or more motherboards mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device <NUM> may not include one or more of the components illustrated in <FIG>, but the electrical device <NUM> may include interface circuitry for coupling to the one or more components. For example, the electrical device <NUM> may not include a display device <NUM>, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device <NUM> may be coupled. In another set of examples, the electrical device <NUM> may not include an audio input device <NUM> or an audio output device <NUM>, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device <NUM> or audio output device <NUM> may be coupled.

The electrical device <NUM> may include one or more processor units <NUM> (e.g., one or more processor units). As used herein, the terms "processor unit", "processing unit" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit <NUM> may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).

The electrical device <NUM> may include a memory <NUM>, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory <NUM> may include memory that is located on the same integrated circuit die as the processor unit <NUM>. This memory may be used as cache memory (e.g., Level <NUM> (L1), Level <NUM> (L2), Level <NUM> (L3), Level <NUM> (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device <NUM> can comprise one or more processor units <NUM> that are heterogeneous or asymmetric to another processor unit <NUM> in the electrical device <NUM>. There can be a variety of differences between the processing units <NUM> in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units <NUM> in the electrical device <NUM>.

In some embodiments, the electrical device <NUM> may include a communication component <NUM> (e.g., one or more communication components). For example, the communication component <NUM> can manage wireless communications for the transfer of data to and from the electrical device <NUM>. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

The communication component <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE <NUM> family), IEEE <NUM> standards (e.g., IEEE <NUM>-<NUM> Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE <NUM> compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE <NUM> standards. The communication component <NUM> may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component <NUM> may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component <NUM> may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. The communication component <NUM> may operate in accordance with other wireless protocols in other embodiments. The electrical device <NUM> may include an antenna <NUM> to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication component <NUM> may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE <NUM> Ethernet standards). As noted above, the communication component <NUM> may include multiple communication components. For instance, a first communication component <NUM> may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component <NUM> may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component <NUM> may be dedicated to wireless communications, and a second communication component <NUM> may be dedicated to wired communications.

The electrical device <NUM> may include battery/power circuitry <NUM>. The battery/power circuitry <NUM> may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device <NUM> to an energy source separate from the electrical device <NUM> (e.g., AC line power).

The electrical device <NUM> may include a display device <NUM> (or corresponding interface circuitry, as discussed above). The display device <NUM> may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device <NUM> may include an audio output device <NUM> (or corresponding interface circuitry, as discussed above). The audio output device <NUM> may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.

The electrical device <NUM> may include an audio input device <NUM> (or corresponding interface circuitry, as discussed above). The audio input device <NUM> may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device <NUM> may include a Global Navigation Satellite System (GNSS) device <NUM> (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device <NUM> may be in communication with a satellite-based system and may determine a geolocation of the electrical device <NUM> based on information received from one or more GNSS satellites, as known in the art.

The electrical device <NUM> may include an other output device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other output device <NUM> may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device <NUM> may include an other input device <NUM> (or corresponding interface circuitry, as discussed above). Examples of the other input device <NUM> may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

The electrical device <NUM> may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a <NUM>-in-<NUM> convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device <NUM> may be any other electronic device that processes data. In some embodiments, the electrical device <NUM> may comprise multiple discrete physical components. Given the range of devices that the electrical device <NUM> can be manifested as in various embodiments, in some embodiments, the electrical device <NUM> can be referred to as a computing device or a computing system.

Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.

Example <NUM> includes a diffraction grating comprising a silicon substrate; and a plurality of grating lines extending from the silicon substrate to diffract light at one or more wavelengths, wherein individual grating lines of the plurality of grating lines have a length of at least one micrometer as measured from the silicon substrate, wherein a maximum difference in length of any two of the plurality of grating lines is less than <NUM> nanometers.

Example <NUM> includes the subject matter of Example <NUM>, and wherein the substrate comprises silicon.

Example <NUM> includes the subject matter of any of Examples <NUM> and <NUM>, and further including an anti-reflection coating on a surface of the silicon substrate opposite the plurality of grating lines, wherein the anti-reflection coating comprises a composition of silicon and nitrogen.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and further including an anti-reflection coating on a surface of the silicon substrate opposite the plurality of grating lines, wherein the anti-reflection coating comprises a first layer comprising a composition of silicon and nitrogen, a second layer comprising a composition of silicon and oxygen, a third layer comprising a composition of silicon and nitrogen, and a fourth layer comprising a composition of silicon and oxygen.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein individual grating lines of the plurality of grating lines comprise silicon.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein individual grating lines of the plurality of grating lines comprise a composition of silicon and nitrogen.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein the plurality of grating lines is to diffract light at a wavelength between <NUM>,<NUM>-<NUM>,<NUM> nanometers with an efficiency over <NUM>% in a Littrow configuration.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein individual grating lines of the plurality of grating lines comprise a plurality of sub-lines, wherein individual sub-lines of the plurality of sub-lines of the plurality of grating lines are to cause a position-dependent change of an effective index of refraction of the corresponding grating line.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein individual grating lines of the plurality of grating lines have an anti-reflection coating on a distal end of the grating line.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and further including an etch stop layer between the substrate and the plurality of grating lines.

Example <NUM> includes a system comprising a light detection and ranging (LIDAR) system, wherein the LIDAR system comprises the diffraction grating any of Examples <NUM>-<NUM>.

Example <NUM> includes the subject matter of Example <NUM>, and further including an autonomous vehicle, wherein the autonomous vehicle comprises the LIDAR system.

Example <NUM> includes a diffraction grating comprising a substrate; and a plurality of grating lines extending from the substrate to diffract light at one or more wavelengths, wherein the diffraction grating has an efficiency of over <NUM>% into a first order over a range of input angles, wherein the range of input angles spans over <NUM>° around a Littrow angle.

Example <NUM> includes the subject matter of Example <NUM>, and further including an anti-reflection coating on a surface of the substrate opposite the plurality of grating lines, wherein the anti-reflection coating comprises a composition of silicon and nitrogen.

Example <NUM> includes the subject matter of any of Examples <NUM> and <NUM>, and further including an anti-reflection coating on a surface of the substrate opposite the plurality of grating lines, wherein the anti-reflection coating comprises a first layer comprising a composition of silicon and nitrogen, a second layer comprising a composition of silicon and oxygen, a third layer comprising a composition of silicon and nitrogen, and a fourth layer comprising a composition of silicon and oxygen.

Example <NUM> includes a method comprising growing an etch stop layer on a substrate of a wafer; creating a second layer on the etch stop layer; and etching the second layer to create a plurality of grating lines of a diffraction grating on the substrate.

Example <NUM> includes the subject matter of Example <NUM>, and further including flipping the wafer; and creating an anti-reflection coating on a back side of the wafer opposite the plurality of grating lines.

Example <NUM> includes the subject matter of any of Examples <NUM> and <NUM>, and further including creating an anti-reflection coating on the substrate, wherein growing the etch stop layer comprises growing the etch stop layer on the anti-reflection coating.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and further including creating an anti-reflection coating on the substrate, wherein the anti-reflection coating comprises a first layer comprising a composition of silicon and nitrogen, a second layer comprising a composition of silicon and oxygen, a third layer comprising a composition of silicon and nitrogen, and a fourth layer comprising a composition of silicon and oxygen.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein the wafer has a diameter over <NUM> millimeters.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein etching the second layer comprises etching the second layer with a plasma-enhanced etch.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein the substrate comprises silicon.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein the second layer comprises silicon.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein the second layer comprises a composition of silicon and nitrogen.

Example <NUM> includes the subject matter of any of Examples <NUM>-<NUM>, and wherein etching the second layer comprises etching the second layer based on a design of the diffraction grating, wherein an efficiency of the diffraction grating is over <NUM>% for a range of wall slopes of the plurality of grating lines relative to wall slopes of the design and a range of input angles, wherein the range of input angles spans over <NUM>° around a Littrow angle, wherein the range of wall slopes spans over <NUM>°.

Claim 1:
A diffraction grating (<NUM>; <NUM>) comprising:
a silicon substrate (<NUM>; <NUM>);
a plurality of grating lines (<NUM>; <NUM>) extending from the silicon substrate (<NUM>; <NUM>) to diffract light at one or more wavelengths;
an etch stop layer (<NUM>; <NUM>) between the substrate (<NUM>; <NUM>) and the plurality of grating lines (<NUM>; <NUM>); and
an anti-reflection coating (<NUM>; <NUM>) between the substrate (<NUM>; <NUM>) and the etch stop layer (<NUM>; <NUM>);
wherein individual grating lines of the plurality of grating lines (<NUM>; <NUM>) have a length of at least one micrometer as measured from the silicon substrate (<NUM>; <NUM>),
wherein a maximum difference in length of any two of the plurality of grating lines is less than <NUM> nanometers.