Patent Description:
Traction motor control is important for electrical vehicle (EV) applications. Axis rotation angle measurement plays a key role in traction motor control. The rotation angle of the motor axis (also referred to as motor shaft) is usually measured by a resolver.

Resolvers, also known as motor resolvers, are electromagnetic transducers that can be used in a wide variety of position and velocity feedback applications, such as servo motor feedback applications. The resolver is a special type of rotary transformer that consists of a cylindrical rotor and stator. The rotor is attached to the motor shaft and rotates with the motor shaft. The resolver typically has a primary wining and two secondary windings. The primary winding may be a rotor winding on the rotor, and the secondary windings may be two stator windings on the stator. The two secondary windings are mechanically arranged such that their physical relation is shifted by a <NUM>° angle.

The resolver is used for generating output signals that indicate the angular position of the motor shaft, with respect to a reference point, within a space of one complete revolution of the motor shaft or within a corresponding angular displacement space from <NUM>° to <NUM>°. To generate the output signals, a rotor excitation signal (e.g., a sine wave signal) is applied at the primary winding. The physical relation of the secondary windings gives rise to a mathematical/electrical relation, such that a first output signal at a first one of the secondary windings is a sine wave signal amplitude-modulated by sin(<NUM>), and a second output signal at a second one of the secondary windings is a sine wave signal amplitude-modulated by cos(Ø), where <NUM> is the angular position of the motor shaft (may also be referred to as the angle <NUM> of the motor shaft). The resolver output signals are then decoded by a resolver decoder to obtain an estimate of the angle <NUM>. There is a need in the art for resolver decoders that provide accurate estimate of the angle <NUM> with lower hardware cost and/or lower computing power requirements.

Document <CIT>, taken as a model for the preamble of claim <NUM>, discloses a resolver to digital converter including first and second inputs to receive signals from a resolver and an output to provide an estimated angle of a rotor. The sine component signal is multiplied by the cosine of the estimated angle and the cosine component signal is multiplied by the sine of the estimated angle, and a difference between them is calculated to provide an error measurement. The estimated angle is updated by the error measurement.

Document <CIT> discloses a system with magnetic sensors that provide sine and cosine values of an angle to be determined. A pair of delta-sigma modulators performs amplification and analog-to- digital conversion of the values. A pair of decimation filters filter and down- sample bit streams. A pair of normalization stages perform processing of normalization parameters. A processor computes the angle using the output from the stages.

Document <CIT> discloses a synthesis circuit that synthesizes detection signals from a plurality of detection coils to generate a synthesized detection signal indicating a sine component of a rotation angle of a rotor. The detection coils include a detection coil of a salient pole installed at a first electrical angle based on a first pole of the rotor and detection coils of salient poles installed at a second electrical angle different from the first electrical angle based on the first pole, while not including detection coils installed at the first electrical angle based on a second pole.

Document <CIT> discloses an apparatus for determining presence of an abnormality in an angle detection device configured to output an output signal having a value equivalent to a rotational angle of a rotating body. The apparatus includes a smoothing means configured to receive the output signal of the angle detection device to smooth a dependent variable of a function whose independent variable is the rotational angle equivalent value, and a parameter calculation means for calculating an abnormality determination parameter based on the dependent variable smoothed by the smoothing means.

Document <CIT> discloses a capacitive angle encoder for sensing the position of a rotating shaft that includes a transmitter, including multiple segments disposed about the shaft, each segment generating a periodic electrostatic field at a common frequency, but having a different, predetermined phase from the other segments. A receiver generates signals responsive to the fields from the multiple segments such that the strength of reception of each of the fields is modulated by a variation of a capacitance between the transmitter and the receiver as a function of rotation of the shaft. A detector circuit processes the signals so as to generate an output indicative of the rotation angle.

Some embodiments relate to a resolver decoder circuit according to claim <NUM>.

Advantageous developments thereof are recited in claims <NUM> to <NUM>.

Some embodiments relate to a processor according to claim <NUM>, having an integrated resolver decoder circuit.

In the figures, identical reference symbols generally designate the same component parts throughout the various views, which will generally not be re-described in the interest of brevity. For a more complete understanding of the invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:.

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to exemplary embodiments in a specific context, namely digital resolver decoder with hardware filter and hardware rectifier.

<FIG> illustrates a block diagram of a motor system <NUM>, in an embodiment. Note that for simplicity, not all features of the motor system <NUM> are illustrated.

Referring to <FIG>, the motor control system <NUM> includes a motor <NUM>, which may be, e.g., a three-phase motor. The motor <NUM> is driven by a power stage <NUM>, which may include driver circuits that provide the driving voltages for the motor <NUM>. For example, the power stage <NUM> may include three parallel driver circuits, each for driving one of the three-phases of the motor <NUM>. Each of the driver circuits may have its respective power switches (e.g., a high-side power switch and a lower-side power switch). The power stage <NUM> is controlled by a central processing unit (CPU) <NUM>. The CPU <NUM> has a memory module <NUM> (e.g., a non-volatile memory). The memory module <NUM> may store computer programs (e.g. computer codes) for motor control algorithms. In addition, the memory module <NUM> may store various parameters related to, e.g., system settings, or filter coefficients for a filter circuit <NUM>.

As illustrated in <FIG>, the rotor of the resolver <NUM> is coupled to the motor shaft, such that the rotor rotates with the motor shaft. The two secondary windings of the resolver <NUM> provides two output signals 104A and 104B that can be used to determine the angle <NUM> of the motor shaft. <FIG> and <FIG> illustrate details regarding the resolver <NUM> and the output signals 104A and 104B.

Referring temporarily to <FIG>, which shows a primary winding <NUM> of the resolver <NUM> and two secondary windings of the resolver <NUM>, which secondary windings include a first secondary winding <NUM> and a second secondary winding <NUM>. The primary winding <NUM> may be a rotor winding, and the secondary windings <NUM>/<NUM> may be two stator windings. The two secondary windings <NUM>/<NUM> are mechanically arranged such that their coils are shifted by a <NUM>° angle.

The resolver <NUM> generates output signals at the secondary windings <NUM>/<NUM> by energizing or exciting the primary winding <NUM> with an excitation voltage Vin, which is a sine wave signal represented by Vin = A * sin(ωct), where ωc is the angular frequency of the sine wave signal, and A is the amplitude of the sine wave signal. The sine wave signal Vin induces a voltage at each of the secondary windings <NUM>/<NUM>. The output voltages at the secondary windings <NUM>/<NUM> are amplitude-modulated versions of the sine wave signal Vin, where the amplitude of the sine wave signal Vin is modulated by the sine and cosine of the angle Ø of the motor shaft. For example, a voltage Vsin across terminals of the first secondary winding <NUM> and a voltage Vcos across terminals of the second secondary winding <NUM> may be represented by <MAT> <MAT> where K is the transfer ratio of the resolver <NUM>. The transfer ratio K is a constant for a given resolver <NUM>. Since the output voltage Vsin of the first secondary winding <NUM> is amplitude-modulated by sin(Ø), the first secondary winding <NUM> is also referred to as the sine winding of the resolver <NUM>. Similarly, the second secondary winding <NUM> is also referred to as the cosine winding of the resolver <NUM>. In the illustrated example, the output voltage Vsin is the output signal 104A in <FIG>, and the output voltage Vcos is the output signal 104B in <FIG>.

Note that the angle <NUM> of the motor shaft is actually a time varying signal and may be represented by <NUM>(t) = ωmt, where ωm is the angular frequency of the motor shaft. However, the angular frequency ωc of the sine wave signal Vin is chosen to be much higher than the angular frequency ωm of the motor shaft (e.g., ωc » ωm), and therefore, during a period T of the sine wave signal (T = <NUM>π/ωc), the angle of the motor shaft changes very little and can be considered as a constant. As will be discussed in more details hereinafter, the signal processing of the resolver decoder <NUM> processes digital samples of output voltages Vsin and Vcos within one period T (also referred to as a cycle) of the sine wave signal. Therefore, for the purpose of the signal processing performed by the resolver decoder <NUM>, the angle of the motor shaft can be considered as a constant (e.g., constant within each period T), and is denoted as a constant angle <NUM> in the equations hereinafter to simplify the analysis. <FIG> illustrates the input signal Vin and the output signals Vsin and Vcos of the resolver <NUM>, in an embodiment. In addition, <FIG> further illustrates the motor shaft angle <NUM> that modulates the amplitude of the input signal Vin. Three subplots at the top of <FIG> illustrate signals Vin, Vsin, and Vcos, respectively. The subplot at the bottom of <FIG> illustrates the shaft angle Ø. The x-axes of the subplots are aligned and represent time, and the y-axis represents the value of the signals. The curve <NUM> in <FIG> shows that the envelope of the modulated sine wave signal Vsin follows the shape of the slow-changing modulating signal sin (<NUM>). Similarly, the curve <NUM> in <FIG> shows that the envelope of the modulated sine wave signal Vcos follows the shape of the slow-changing modulating signal cos (<NUM>). Referring back to <FIG>, the excitation voltage Vin is generated by an exciting circuit <NUM>, which may be or include a low-pass filter. The exciting circuit <NUM> accepts as input a pulse width modulated (PWM) signal generated by a PWM circuit <NUM>. The PWM circuit <NUM> (also referred to as a PWM peripheral) is controlled by the CPU <NUM> and generates a sequence of PWM pulses which, after being processed (e.g., filtered) by the exciting circuit <NUM>, turn into the sine wave signal Vin.

Still referring to <FIG>, the output signals 104A and 104B from the resolver <NUM> are processed by a buffer circuit <NUM>. The buffer circuit <NUM> performs signal conditioning functions, such as modifying/removing offsets (e.g., DC levels) of the output signals 104A and 104B, and/or voltage conversion. For example, the voltages of the output signals 104A and 104B may have amplitudes between about <NUM> V and about <NUM> V. The buffer circuit <NUM> converts (e.g. scales) the amplitudes of output signals 104A and 104B to a voltage range compatible with an analog-to-digital (ADC) circuit <NUM>, such as between about <NUM> V and about <NUM> V. The outputs of the buffer circuit <NUM> are signals 106A and 106B, which may be scaled versions of the signals 104A and 104B, respectively. In other words, the signal 106A is the signal 104A processed by the buffer circuit <NUM>, and the signal 106B is the signal 104B processed by the buffer circuit <NUM>.

The outputs of the buffer circuit <NUM> are sent to a resolver decoder <NUM> (also referred to as a digital resolver decoder, or a resolver decoder circuit). Based on the digital samples of the signals 106A and 106B, the resolver decoder <NUM> generates an estimated angle Ø̃ of the angle Ø of the motor shaft. As illustrated in <FIG>, the resolver decoder <NUM> includes an analog-to-digital converter (ADC) circuit <NUM>, a filter circuit <NUM>, a hardware rectifier <NUM>, and an angle calculation circuit <NUM>. The ADC circuit <NUM> converts the signals 106A and 106B into digital samples. The filter circuit <NUM> computes a first weighted sum of the digital samples of the signal 106A over a pre-determined period of time (e.g., a duration of T/<NUM>), and computes a second weighted sum of the digital samples of the signal 106B over the predetermined period of time (e.g., a duration of T/<NUM>), where the pre-determined period of time is within the first half or within the second half of a period T of the sine wave signal sin(ωct). The hardware rectifier <NUM> adjusts the signs of the first weighted sum and the second weighted sum, depending on whether the predetermined period of time is within the first half or the second half of the period T of the sine wave signal. The outputs of the hardware rectifier <NUM> are sent to the angle calculation circuit <NUM> to obtain an angle Ø̃ as the estimate for the angle Ø of the motor shaft. More details are discussed herein after with reference to <FIG>, <FIG>, 6A and 6B.

In some embodiments, the angle calculation circuit <NUM> is omitted in the resolver decoder <NUM>, and the function of the angle calculation circuit <NUM> is performed by the CPU <NUM>. In other words, instead of using a dedicated hardware (e.g., the angle calculation circuit <NUM>) to compute the estimated angle Ø̃, the CPU <NUM> computes the estimated angle Ø̃.

In some embodiments, the resolver decoder <NUM>, the CPU <NUM>, the memory module <NUM>, the PWM circuit <NUM> (if formed), and other peripheral modules of the CPU <NUM> are integrated onto a same semiconductor substrate as a single semiconductor device <NUM>, which may be referred to as a processor <NUM>, a micro-controller <NUM> with integrated resolver decoder, or simply a micro-controller <NUM>. Compared with a solution where the resolver decoder <NUM> is implemented in a dedicated semiconductor device (e.g., an application-specific integrated circuit (ASIC)) and the CPU <NUM> is implemented in another device, the disclosed micro-controller <NUM> has the advantage of higher integration density (thus lower cost) for the motor control system <NUM>. Compared with a software solution where CPU <NUM> implements some or all of the functions of the resolver decoder <NUM>, the disclosed structure of the micro-controller <NUM> offloads computation intensive tasks (e.g., the tasks of computing the output of the filter circuit <NUM>) to hardware circuits, so the CPU <NUM> can have more computational resources reserved for other system tasks. As a result, the real-time performance of the motor control system <NUM> is improved. <FIG> illustrates a block diagram of a resolver decoder <NUM>, in an embodiment. The resolver decoder <NUM> of <FIG> shows more details than that of <FIG>, and may be used as the resolver decoder <NUM> of <FIG>.

As illustrated in <FIG>, the signals 106A (e.g., corresponding to the Vsin signal) and 106B (e.g., corresponding to the Vcos signal) are sent to the ADC circuit <NUM> for conversion into digital samples. The ADC circuit <NUM> may include two analog-to-digital converters 118A and 118B, or two input channels 118A and 118B, for converting the signals 106A and 106B synchronously. For example, a same sampling clock signal <NUM> may be used to drive the circuits (e.g., 118A and 118B) for converting the signals 106A and 106B, such that the signals 106A and 106B are sampled at the same time instants. Therefore, pairs of digital samples of the signals 106A and 106B are sent to the filter circuit <NUM>, where the two digital samples in each pair are sampled at the same time instant.

The filter circuit <NUM> has two finite impulse response (FIR) filters 115A and 115B.

The digital samples of the signal 106A are sent to the FIR filter 115A, and the digital samples of the signal 106B are sent to the FIR filter 115B. Details of the FIR filters 115A and 115B are illustrated in <FIG>.

Referring temporarily to <FIG>, which shows the schematic view of the FIR filters 115A and 115B. As illustrated in <FIG>, the FIR filter 115A has a tapped-delay line (TDL) with a plurality of delay elements <NUM>, which TDL may be implemented a plurality of serially concatenated memory elements such as flip-flops. The input to the TDL of the FIR filter 115A is x(n), which are the digital samples of the signal 106A. The TDL has a plurality of taps, and each of the taps has a respective coefficient <NUM> (labeled as ak, k=<NUM>, <NUM>, <NUM>,. , m), which coefficient is used to scale (e.g., multiply with) the values at the tap. In other words, each coefficient <NUM> represents a multiplier with a corresponding scaling factor ak. The FIR filter 115A further has a plurality of adders <NUM>, which sums up all the scaled values to generate the output of the FIR filter 115A. Therefore, the FIR filter 115A calculates a weighted sum of the digital samples that are at the input of the TDL and in the delay elements <NUM>. The FIR filter 115B has an identical structure as the FIR filter 115A, but is used to process input data y(n), which are the digital samples of the signal 106B. In addition, the filter coefficients <NUM> of the FIR filter 115B are denoted as bk, k=<NUM>, <NUM>, <NUM>,. m, which may be chosen independently from the coefficients ak of the FIR filter 115A. The output of the FIR filters 115A and 115B are given by: <MAT> <MAT>.

In the illustrated embodiment, the sampling frequency fs of the ADC circuit <NUM> is chosen to be orders of magnitude higher (e.g., <NUM> times, <NUM> times, <NUM> times, or more) than that frequency fc of the sine wave signal sin(ωct), where fc = ωc/(<NUM>π). In an example embodiment, the ratio between fs and fc is chosen to be 2N, where N is a positive integer (e.g., N≥<NUM>), such as <NUM>, <NUM>, or <NUM>. This means that for each period T of the sine wave signal sin(ωct), 2N digital samples are generated for the signal 106A, and 2N digital samples are generated for the signal 106B. In addition, the number of taps of the FIR filters 115A/115B, which is m + <NUM>, is chosen such that the duration of time covered by the TDL of each FIR filter is equal to or smaller than half of the period T, or equivalently, m≤N.

In some embodiments, the filter coefficients ak and bk are chosen to be <NUM>, such that the FIR filters 115A and 115B simply calculate the sum of all the digital samples within a duration of mTs, where Ts = <NUM>/fs is the sampling period of the ADC circuit <NUM>. When the oldest digital sample in the TDL (e.g., the digital sample stored in the rightmost delay element <NUM> of the TDL) of the FIR filter 115A (or 115B) corresponds to a sample of the signal 106A (or 106B) at the starting point (e.g., t = <NUM>) of a period T of the sine wave signal sin(ωct), the output of the FIR filter 115A (or 115B) is the sum of digital samples disposed within the first half of the period T of the sine wave signal. In particular, where m=N, the digital samples stored in the tapped delay line of the FIR filter 115A (or 115B) covers exactly the first half of the period T of the sine wave signal. With the sampling frequency fs being much higher than the frequency fc of the sine wave signal sin(ωct), the outputs of the FIR filters 115A and 115B in Equation (<NUM>) and (<NUM>) provide close approximations to the following integration values respectively: <MAT> <MAT>.

For similar reasons, when the oldest digital sample stored in the tapped delay line of the FIR filter 115A (or 115B) corresponds to a sample of the signal 106A (or 106B) at mid-point of the period T (e.g., t = T/<NUM>) of the sine wave signal sin(ωct), the outputs of the filters 115A and 115B in Equation (<NUM>) and (<NUM>) provide close approximations to the following integration values respectively: <MAT> <MAT>.

Note that for simplicity, the integration values in Equations (<NUM>) and (<NUM>) (and (<NUM>) and (<NUM>)) omitted a positive constant scale factor, which is determined by, e.g., the positive values A and K in Equations (<NUM>) and (<NUM>), and the positive scaling factor of the buffer circuit <NUM>. As will be discussed hereinafter, a positive constant scale factor in the integration values in Equations (<NUM>) and (<NUM>), or (<NUM>) and (<NUM>), does not change the result of the angle calculation performed later.

Recall that in <FIG>, the PWM pulses, which is used by the exciting circuit <NUM> to generate the sine wave signal sin(ωct), is generated under the control of the CPU <NUM>. Therefore, the timing of the sine wave signal sin(ωct), such as the starting point (e.g., t = <NUM>), the mid-point (e.g., t = T/<NUM>), or the end-point (e.g., t = T) of a period T of the sine wave signal sin(ωct), is known to the CPU <NUM>. In addition, the time delay introduced by the resolver <NUM>, the buffer circuit <NUM>, and the ADC circuit <NUM> is a fixed value, and is either known or can be measured, e.g., by a calibration process. Therefore, the timing information of the digital samples (also referred to as data samples) fed into the FIR filters 115A/115B, such as which digital sample corresponds to the starting point, the mid-point, or the end-point within a period T of the amplitude-modulated sine wave signal, is known to the CPU <NUM> (or the PWM circuit <NUM>). For example, the digital samples x(n) and y(n) at the input of the FIR filters 115A/115B that correspond to the starting point of a period T of the amplitude-modulated sine wave signal can be identified by counting a predetermined number of clock cycles (which correspond to a pre-determined time delay) from the known starting point of the sine wave signal at the output of the exciting circuit <NUM>.

<FIG> shows a control signal path <NUM> from the PWM circuit <NUM> to the hardware rectifier <NUM>. In some embodiments, the control signal path <NUM> is used to send the timing information of the data samples, such as a pulse to indicate that the current data sample x(n) and y(n) at the input of the FIR filters 115A/115B are the samples corresponding to the mid-point of a period T, or equivalently, corresponding to an angle π within a period of <NUM>π of the sine wave signal. The timing formation, such as the pulse discussed above, is used to indicate that the current outputs of the FIR filters 115A/115B correspond to the integration values between angles <NUM> and π (e.g., Equations (<NUM>) and (<NUM>)), or the integration values between angles π and <NUM>π (e.g., Equations (<NUM>) and (<NUM>)). Although <FIG> shows that the timing information is sent from the PWM circuit <NUM> to the hardware rectifier <NUM>, the timing information may alternatively be send from the CPU <NUM> to the hardware rectifier <NUM>.

Note that the integration values Vsin and Vcos in Equations (<NUM>) and (<NUM>) provide scaled versions of sin (<NUM>) and cos (<NUM>), respectively, scaled by <MAT>, which has a positive value because sin (ϕc) has positive values for angles between <NUM> and π. Similarly, the integration values Vsin and Vcos in Equations (<NUM>) and (<NUM>) provide scaled versions of sin (<NUM>) and cos (<NUM>), respectively, scaled by <MAT>, which has a negative value because sin (ϕc) has negative values for angles between π and <NUM>π. The negative scale factor in the integration values of Equations (<NUM>) and (<NUM>) may cause error in the calculation of the estimated shaft angle Ø̃ based on sin (Ø) and cos(Ø). Therefore, the integration values of Equations (<NUM>) and (<NUM>) are adjusted (e.g., corrected) by multiplying with a value of -<NUM>, or equivalently, by changing (or reversing) the signs of the integration values of Equations (<NUM>) and (<NUM>), in some embodiments.

Referring back to <FIG>, the hardware rectifier <NUM> corrects the outputs of the FIR filters 115A/115B by, e.g., multiplying with a value of -<NUM> using the multipliers <NUM> (e.g., 601A and 601B), when the outputs of the FIR filters 115A/115B correspond to integration values of Equations (<NUM>) and (<NUM>), or equivalently, when the data samples stored in the tapped delay lines of the FIR filters 115A/115B are data samples in the second half of a period T (e.g., between angles π and <NUM>π) of the amplitude-modulated sine wave signal. Conversely, when the outputs of the FIR filters 115A/115B correspond to integration values of Equations (<NUM>) and (<NUM>), or equivalently, when the data samples stored in the tapped delay lines of the FIR filters 115A/115B are data samples in the first half of a period T (e.g., between angles <NUM> and π) of the amplitude-modulated sine wave signal, the hardware rectifier <NUM> passes through the outputs of the FIR filters 115A/115B, e.g., by multiplying with a value of <NUM>.

The sign table <NUM> of the hardware rectifier <NUM> keeps track of the signs of the outputs of the FIR filters <NUM>/<NUM>. In other words, the sign table <NUM> determines whether a multiplication value of <NUM> or -<NUM> is used to multiply with the outputs of the FIR filters 115A/115B. As discussed above, the control signal path <NUM> sends timing information of the data samples, or equivalently, timing information regarding whether the outputs of the FIR filters 115A/115B correspond to Equations (<NUM>) and (<NUM>), or Equations (<NUM>) and (<NUM>). For example, the control signal path <NUM> may send a so-called "zero-crossing pulse" once every half of the period T, which zero-crossing pulse indicates whether the current outputs of the FIR filters 115A/115B correspond to Equations (<NUM>) and (<NUM>), or Equations (<NUM>) and (<NUM>). In some embodiments, the sign table <NUM> starts with a multiplication value of <NUM>, and toggles the multiplication value between <NUM> and -<NUM> each time a zero-crossing pulse is received. Therefore, in the illustrated embodiment, the hardware rectifier <NUM> multiplies the outputs of the FIR filters 115A/115B with a value of <NUM> or -<NUM> every half period T, such that the outputs of the hardware rectifier <NUM> are always the values of sin (<NUM>) and cos(Ø) scaled by a positive scale factor.

Still referring to <FIG>, the outputs of the hardware rectifier <NUM> are sent to the angle calculation circuit <NUM>, which performs an arctangent function and a post processing to find an estimated angle Ø̃ of the angle Ø. In particular, the angle calculation circuit <NUM> finds a first angle α by <MAT>.

In some embodiments, the arctangent function is implemented as a look-up table (LUT) as a low-cost solution, where the value of sin(<NUM>) /cos (Ø) is calculated and used as an index of the LUT to find the value of the arctangent function. Note that the angle α calculated by the arctangent function is between —π/<NUM> and π/<NUM>, whereas the angle <NUM> of the motor shaft is between <NUM> and <NUM>π. A post processing is performed to calculate the estimated angle Ø̃ based on the quadrant of the angle <NUM>, which is determined by the signs of sin (<NUM>) and cos(<NUM>). For example, if, based on the signs of sin (<NUM>) and cos(Ø), the angle Ø is in the first quadrant, then Ø̃ = α; if the angle Ø is in the second quadrant, then Ø̃ = π - α; if the angle Ø is in the third quadrant, then Ø̃ = π + α; and if the angle Ø is in the fourth quadrant, then Ø̃ = <NUM>π - α. The estimated angle Ø̃ is then sent to the CPU <NUM>. The CPU <NUM> may, based on the motor control algorithm, determine the driving voltages for the motor <NUM>, such that the motor <NUM> is controlled in a closed-loop controlled fashion. One skilled in the art will readily appreciate that the CPU <NUM> may generate a sine wave signal that lasts continuously over multiple periods of time during the operation of the motor <NUM>. The above described processing, which generates an estimated angle Ø̃ every half period of the sine wave signal, is performed repeatedly for each period T of the sine wave signal, so that the CPU <NUM> gets updated estimates of the angle Ø of the motor shaft twice a period of the sine wave signal. The disclosed FIR filters 115A/115B integrate (e.g., add) the amplitude-modulated sine wave signal over the first half or the second half of a period T of the sine wave signal, which has the advantage of improving the quality (e.g., signal-to-noise ratio (SNR)) of the calculated values for (scaled versions of) sin (<NUM>) and cos(<NUM>). This is because in real systems, the output voltage Vsin and Vcos of the resolver <NUM> has noises (e.g., random noises), which degrade the quality of the output voltages. The integration operation (see Equations (<NUM>) and (<NUM>), or (<NUM>) and (<NUM>)) averages out the random noises, thereby reducing the noise power without adversely affecting the values (sin (<NUM>) and cos(<NUM>)) being calculated. Compared with a method where each pair of digital samples from the ADC circuit <NUM> are used directly to compute the arctangent, the disclosed processing provides significantly improved accuracy in the estimated angle Ø̃.

In the discussion above, the coefficients of the FIR filters 115A/115B are set to a value of <NUM> to simplify the discussion. The coefficients of the FIR filters 115A/115B, however, may be chosen to different values to improve performance. For example, digital samples corresponding to angles proximate to <NUM>, π, and <NUM>π of the sine wave signal has small amplitudes, and due to the random noise in the system, these digital samples have lower quality (e.g., lower SNR) than digital samples corresponding to angles proximate to π/<NUM> or <NUM>π/<NUM>. Therefore, it may be advantageous to assign smaller weights (e.g., filter coefficients with smaller values) for the digital samples with lower quality (e.g., near zero-crossing locations of the sine wave signal), and to assign higher weights for the digital samples with higher quality (e.g., near maximum value locations of the sine wave signal). <FIG> illustrates a weight assignment strategy that improves the quality of the output of the FIR filters 115A and 115B.

Referring to <FIG>, the tap coefficients of the FIR filter 115A (or 115B) (see, e.g., ai, a<NUM>,. , ak in <FIG>) are chosen to be equal to, or proportional to, the values of the sine wave signal at locations corresponding to locations of the filter taps. For example, the amplitudes of the tap coefficients follow the envelope of the sine wave signal (e.g., the envelope in half of a period T).

<FIG> illustrate another strategy for assigning the tap coefficients of the FIR filters 115AA (or 115B). In the example of <FIG>, the tap coefficients do not follow the envelope of the sine wave signal, but are still larger for digital samples having larger amplitudes for resolver output signal, and smaller for digital samples having smaller amplitudes for resolver output signal. For example, the tap coefficient may be calculated by computing the convolution of a vector A with itself, where the values in the vector A follow the envelope of the sine wave signal (e.g., in half of a period T). <FIG> plots an example vector A=[<NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM>]. The tap coefficient, denoted by a vector B, is the convolution of the vector A with itself (e.g., B = A * A). For the above example vector A, the corresponding tap coefficient B=[<NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM><NUM>]. <FIG> plots the tap coefficients B. It is seen from <FIG> that the convolution of such a vector A has a bell shape, which accentuates (e.g., amplifies) the center portion and attenuates (e.g., reduces) the tail portions (e.g., portions at the edges of the bell shape). This further improves the quality of the output of the FIR filters 115A and 115B.

<FIG> illustrates another tap coefficients assignment strategy. In <FIG>, only filter taps corresponding to locations around the peak of the sine wave signal (see the center region Δα around the peak of the sine wave signal in <FIG>) are assigned non-zero values, and filter taps outside the center region (e.g., near zero-crossing locations) are assigned zero values. In other words, only digital samples with high SNRs are used in calculation.

While the integrations in Equations (<NUM>) and (<NUM>) (or (<NUM>) and (<NUM>)) are over the entire first half or the entire second half of a period T of the sine wave signal, one skilled in the art will readily appreciate that these are merely non-limiting examples. The integration ranges, or equivalently, the spans of the tapped delay lines in the FIR filters 115A/115B, do not have to cover the entire first half or the entire second half of a period T of the sine wave signal. Instead, the tapped delay lines in the FIR filters 115A/115B may only cover a portion of the first half or the second half of a period T of the sine wave signal.

<FIG> illustrates a flow chart of a method <NUM> for operating a resolver decoder circuit, in some embodiments. It should be understood that the embodiment method shown in <FIG> is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as illustrated in <FIG> may be added, removed, replaced, rearranged and repeated.

Referring to <FIG>, at block <NUM>, a first analog signal is converted from a sine winding of a resolver into first data samples. At block <NUM>, a second analog signal is converted from a cosine winding of the resolver into second data samples. At block <NUM>, a first weighted sum of the first data samples is calculated over a predetermined period of time. At block <NUM>, a second weighted sum of the second data samples is calculated over the pre-determined period of time. At block <NUM>, a first sign of the first weighted sum and a second sign of the second weighted sum are adjusted based on a location of the pre-determined period of time within a cycle of a sine wave signal. At block <NUM>, after the adjusting, the first weighted sum is divided by the second weighted sum to obtain a value. At block <NUM>, an arctangent of the value is determined to obtain an angle.

Claim 1:
A resolver decoder circuit (<NUM>) comprising:
a first filter circuit (115A) configured to calculate a first weighted sum of a first digital signal over a pre-determined period of time, wherein the first digital signal comprises first digital samples of a first analog signal (106A) from a first secondary winding (<NUM>) of a resolver (<NUM>);
a second filter circuit (115B) configured to calculate a second weighted sum of a second digital signal over the pre-determined period of time, wherein the second digital signal comprises second digital samples of a second analog signal (106B) from a second secondary winding (<NUM>) of the resolver (<NUM>), wherein the first analog signal (106A) and the second analog signal (106B) are configured to be induced by a sine wave signal applied to an input winding (<NUM>) of the resolver (<NUM>); and
a rectifier (<NUM>) configured to generate a first output and a second output by adjusting (<NUM>) a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively,
the circuit characterized in that each of the first filter circuit (115A) and the second filter circuit (115B) comprises:
an input terminal;
an output terminal;
a tapped delay line, TDL (<NUM>) coupled to the input terminal and having taps, wherein each of the taps of the TDL has a respective weight factor (<NUM>); and
a plurality of adders (<NUM>) configured to generate, at the output terminal, a weighted sum of digital values at the taps of the TDL (<NUM>).