Patent Description:
PTP enables new functions for stationary and mobile networks at lower cost than using multiple GNSS receivers. One or a few GNSS receivers may be used and then PTP may be used to synchronize intermediate nodes. Precise timing allows for simultaneous data throughout a vehicle or between different vehicles to be accurately compared. This opens up new capabilities for cooperation between various electronic control units (ECUs) that implement, for example, engine control, powertrain control, airbag systems, antilock brake systems, cruise control, electric power steering, audio systems, window control systems, door control systems, mirror adjustment systems, and battery and recharging systems. Newer automotive systems that support connected operation or connected autonomous operation are requiring GNSS receivers for time synchronization. Within the vehicle, this can entail several modules that need to be time synchronized to output a pulse at the beginning of each new second of GNSS time.

The journal article "<NPL>; discloses sub-ns time synchronization implemented in a real-time Fast Ethernet physical layer (PHY) chip. The chip is fabricated in a <NUM> technology of GLOBALFOUNDRIES. The PHY supports timestamping of ingress and egress frames with a resolution of 500ps. The PHY comprises a <NUM> clock and a phase selection that is controlled via a management data input/output interface. Measurement results demonstrate the synchronization between two PHYs connected by up to <NUM> long category <NUM> unshielded twisted pair cables. The time difference has a standard deviation of only 176ps and a mean offset of <NUM>. Asymmetries in the cable are compensated by a simple calibration algorithm that is run at startup of the link within <NUM>.

The invention is defined by the independent claims <NUM> and <NUM>.

A physical layer device is described with a precision timing. The timing may be applied to time stamps and to a signal output. In an embodiment, a physical layer (PHY) device for a network includes a transmitter configured to transmit data at the PHY device from a host to an external network that is external to the PHY device, a host interface configured to receive the data to transmit from the host and configured to receive configuration commands from the host, a clock independent of a host clock and coupled to the host interface to receive phase and frequency adjustments as configuration commands from the host to thereby adjust the phase and frequency of the clock based on the received configuration commands, a modulus counter configured to count a preconfigured number of timing pulses of the clock, and a timing output interface coupled to the modulus counter to produce a precision timing output signal based on detecting the preconfigured number of timing pulses of the clock.

In an embodiment, the timing output interface is configured to be coupled to an end node and wherein there is a propagation delay of the precision timing output signal from the timing output interface to the end node and wherein the timing output interface is configured to be coupled to the host interface to receive a phase adjustment as a configuration command from the host to thereby compensate for the propagation delay.

In an embodiment, the modulus counter is further configured to determine a timing duration for the precision timing output signal.

In an embodiment, the timing duration is one second and the output timing signal is a one pulse per second (1PPS) timing reference signal.

In an embodiment, the modulus counter is coupled to the host interface to receive a modulus adjustment as a configuration command from the host.

In an embodiment, the clock further comprises a phase-locked loop and a timer/counter,.

An embodiment further comprises a device phase-locked loop coupled to the transmitter and the host interface wherein the PLL is configured provide a timing source that is independent of the clock of the PHY device to thereby align the timing of the transmitter and the host interface.

In an embodiment, the PHY device is configured to be coupled to a grandmaster clock and the phase and frequency adjustments from the host are generated by the host based on a precision timing protocol conducted through the PHY device between the host and the grandmaster clock.

In an embodiment, the phase and frequency adjustments are received on a serial media-independent interface.

In an embodiment, the host interface comprises a system management interface and wherein the phase and frequency adjustments are received through the system management interface as parameter adjustments to thereby adjust the phase and frequency of the clock.

The PHY device further comprises a time stamping engine coupled to the clock and configured to apply a time stamp to the data transmitted by the transmitter based on the clock.

In an embodiment, the transmitter comprises a front-end/hybrid, a transmit physical medium attachment and a transmit physical coding sublayer coupled to the time stamping engine and the host data interface.

An embodiment further comprises a receiver configured to receive data at the PHY device from the external network and provide the data to the host data interface and wherein the time stamping engine is further configured to apply a time stamp to the data received by the receiver based on the clock.

An embodiment includes a method of determining timing on a network that includes transmitting data to network nodes from a PHY device, receiving data from the network nodes at the PHY device, applying a clock of the PHY device to a modulus counter of the PHY device configured to count a preconfigured number of timing pulses of the clock, generating a precision output timing signal based on detecting the preconfigured number of timing pulses of the clock, transmitting the precision output timing signal to external nodes external to the PHY device, receiving phase and frequency adjustments as configuration commands at the PHY device from the host through a host interface and adjusting the phase and frequency of the clock based on the received configuration commands.

The clock of the PHY device is independent of a host clock.

An embodiment further comprises advancing the precision output timing signal in response to a configuration command from the host through the host interface.

The method further comprising time stamping the transmitted data based on the clock of the PHY device, time stamping the received data based on the clock of the PHY device, transmitting the time stamped received data to the host through the host interface.

An embodiment includes a subsystem with precision timing comprising a host, a sensor coupled to the host and configured to provide sensor data to the host, and a physical layer (PHY) device having a receiver to receive data from a network, a host interface configured to transmit data received from the network to the host and to receive sensor data from the host to transmit to the network, the host interface further configured to receive configuration commands from the host, and a time stamping engine having a time stamping clock and configured to apply a time stamp to the data received by the receiver based on the time stamping clock and to apply a time stamp to sensor data transmitted to the network based on the time stamping clock, wherein the time stamping clock is coupled to the host interface to receive phase and frequency adjustments as configuration commands from the host.

In an embodiment, the PHY device further comprises a timing output interface coupled to the time stamping clock to produce a precision timing output signal based on the time stamping clock and coupled to the sensor to provide the precision timing output signal to the sensor.

In an embodiment, the host performs a precision timing protocol to determine phase and frequency adjustment to send to the time stamping clock.

Other aspects in accordance with the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example of the principles of the invention.

The present invention may be embodied in other specific forms without departing from essential characteristics as defined in the independent claims. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

<FIG> depicts an example of an in-vehicle network <NUM> suitable for use with the present invention and incorporating multiple nodes and I/O (Input/Output) devices as described herein. The I/O devices may be packet data switches based on Ethernet or another packet data protocol. Alternatively, one or more of the I/O devices may be physical layer interfaces such as a PHY device. The automotive system includes packet data switches integrated into ECUs (Electronic Control Units) distributed throughout the vehicle. Alternatively, one or more of the switches may be independent of an ECU. As shown, a central compute/central gateway <NUM> includes a gateway switch <NUM> that is coupled to other devices and controllers. The central compute/central gateway <NUM> is further coupled to an OBD (On-Board Diagnostics) port <NUM> for external maintenance, control, and monitoring.

The central compute/central gateway <NUM> is coupled through the gateway switch <NUM> to a powertrain domain controller <NUM>, a body domain controller137, and an ADAS (Advanced Driver Assistance System) domain controller <NUM>. As examples, the powertrain domain controller <NUM> is coupled through its packet data switch to an ECU <NUM>, such as an engine management unit, and a TPMS (Tire Pressure Monitoring System) module <NUM>. Other nodes may also be coupled to the powertrain domain controller <NUM>. The body domain controller <NUM> is coupled through its packet data switch to two or more other body control ECUs <NUM>, <NUM> such as for steering and brakes. The ADAS domain controller <NUM> does not have an integral packet data switch but may have an integrated PHY device (not shown) to pass data directly to a variety of sensors such as vision <NUM>, radar <NUM>, LIDAR <NUM>, and a V2X <NUM>, such as a vehicle DSRC (Digital Short Range Communication) radio for communicating with other vehicles and roadside objects.

A navigation and in-vehicle infotainment system (NAV/IVI) <NUM> may also be coupled to the gateway switch <NUM>. This system may include connection through its own data interfaces (not shown) to a TCU (Telematics Control Unit) <NUM> that may include inertial sensors and satellite positioning receivers, a radio <NUM> and other entertainment signal sources. An audio amplifier <NUM> is coupled to the gateway switch <NUM> and to a loudspeaker system <NUM> through an additional packet data switch of the audio amplifier <NUM>. One or more displays <NUM> are coupled to the gateway switch <NUM> and may also offer user input through touchscreen and physical button and switch interfaces.

In some embodiments, a packet data switch may be configured as part of an ECU or other component as a system on a chip (SoC), system in a package (SiP), or in any other suitable way. The packet data switches connect the processors, such as the ECUs and central compute/central gateway <NUM> and memory to multiple nodes of which several examples are shown. However, more or fewer nodes of more or different types may be used in the system.

Packet data switches may be used to allow each node to communicate with one or more processors, sensors, input, and each output devices. Some of the connections are direct and some of the connections are indirect. Data storage may be incorporated into the processors, on die or on package, or into other nodes and each node may include data storage. Packet data switches also allow other nodes that are not coupled to an ECU to communicate without the expense of an integrated or separate connected packet data switch. Other devices on the network may communicate using only a physical device interface such as an Ethernet PHY (physical layer) device.

Ever more automotive sensors and other nodes are proposed and with this increasing complexity and an increasing desire for autonomous driving, it is increasingly expensive to assure fast reliable operation. Some of the reliability is ensured by providing reliable precision timing across the network. While a packet data switch may be used to generate and synchronize clocks, providing a switch at every network node is expensive and increases power consumption. Using a PHY device when possible, may reduce cost and size for each such node.

<FIG> is a block diagram of an example subsystem suitable for an automotive or stationary context. The components are mounted to a circuit board <NUM> which may contain additional lines and components (not shown) such as power supply, passive components, and isolation and security components. An Ethernet PHY device <NUM> is mounted to the circuit board <NUM> together with a processor <NUM>, such as a host processor or application processor that operates as a host, and some end nodes <NUM>, <NUM>, <NUM> shown in this diagram as three sensors. The processor <NUM> may include an instruction processor and a memory or storage medium to execute computer-readable instructions that are stored in the memory. The end nodes may be vision, radar, lidar, or optical sensors, position or attitude sensors, or any of a variety of other sensors suitable for an automotive environment. Alternatively, the end nodes <NUM>, <NUM>, <NUM> may be actuators, transceivers, interfaces, or any other suitable end node. While three end nodes are shown, there may be more or fewer to suit different implementations.

The processor <NUM> communicates with each end node <NUM>, <NUM>, <NUM> through a respective data connection <NUM>, <NUM>, <NUM> which may use any suitable serial or parallel data interface, depending on the nature of the sensor. For a camera, the processor <NUM> may send command and control information to the end node <NUM> through the data connection <NUM> and receive image data through the same data connection. The type of information that is provided may depend on the particular type of end node.

The processor <NUM> is also coupled to the Ethernet PHY device <NUM> with a data connection <NUM> to send and receive data and timing through the Ethernet PHY device <NUM> to and from an external network <NUM>. The data may be sensor data, command and control information, operations, administration, and maintenance (OAM) data, or any other suitable data. The Ethernet PHY device <NUM> has a time stamping engine, such as time stamping engine <NUM> of <FIG>, to stamp incoming and outgoing packets and data streams with a time determined by a clock, such as time stamping timer/counter <NUM> of <FIG>, within the Ethernet PHY device <NUM>.

The Ethernet PHY device <NUM> also produces a precision timing signal as an output signal based on the clock within the Ethernet PHY device <NUM>, such as a 1PPS (One Pulse per Second) signal. Three different precision timing output signals on each of three different 1PPS signal lines <NUM>, <NUM>, <NUM> may be sent, each to a different end node with different phase or delay. Alternatively, the same 1PPS signal may be provided to one or more of the end nodes <NUM>, <NUM>, <NUM> and may be applied to any one or more of the end nodes, each through a separate 1PPS signal line <NUM>, <NUM>, <NUM>. Additional nodes (not shown) may also be coupled to the processor without receiving a 1PPS signal. The precision timing of the 1PPS signal may be used to synchronize output data between devices or to coordinate action between devices. As an example, if there are two cameras with different external views then, by synchronizing images to a common timing reference, changes between images may be correlated to track motion between the two camera views. There are many other applications for precision timing.

The processor <NUM> may be programmed to determine the meaning of received messages and to generate appropriate outgoing messages and return messages. In some embodiments, the processor <NUM> may include, for example, software applications that are stored in memory of the processor and executed by processing circuits of the processor. The processor operates as a host and may also be implemented as a digital signal processor (DSP), central processing unit (CPU) or microcontroller and may be implemented as a single unit as shown or as multiple units. In an embodiment, the processor <NUM> implements data link layer (i.e., Layer <NUM>) operations which, in an Ethernet-based network, may include Logical Link Control (LLC) sublayer operations and/or media access control (MAC) sublayer operations.

The processor <NUM> receives data from the end nodes <NUM>, <NUM>, <NUM> that are regulated by the precision timing output signal received in each 1PPS signal line <NUM>, <NUM>, <NUM> at each node, respectively. The processor <NUM> may use the received end node data with precision timing information received from the external network <NUM> to provide timing and phase adjustments and absolute timing, among other controls, to the clock within the Ethernet PHY device <NUM> through a timing feedback line <NUM> from the processor <NUM> to the Ethernet PHY device <NUM>. The processor <NUM> has control of the Ethernet PHY device <NUM> such that it can adjust the operating parameters of the Ethernet PHY device <NUM>, using Serial Media-Independent Interface (SMII), System Management Interface (SMI) or another suitable interface. The processor may also receive precision timing information from a grandmaster clock located on the circuit board <NUM> or connected to the processor <NUM> through the external network <NUM>. In some embodiments, the processor is running PTP (Precision Time Protocol) or gPTP per IEEE Std <NUM>™ or IEEE Std <NUM>. In some embodiments, the timing feedback line <NUM> is connected to the external network, so that other Ethernet connected devices that are running PTP or gPTP can control the Ethernet PHY device <NUM>.

The Ethernet PHY device <NUM> is able to output a 1PPS signal based on the clock within the Ethernet PHY device <NUM> that may be time synchronized to any of a variety of different sources. In some embodiments, the signal is synchronized to a GNSS receiver. In some embodiments, the signal is synchronized to a grandmaster clock that is received through an IEEE <NUM>-compliant signal. Other clock sources may alternatively be used. The output 1PPS signal, or other precision timing reference signal, is needed by some remotely controlled electronics and sensor modules to generate time stamps and time synchronized outputs.

Current implementations of common precision timing protocols require an applications processor co-located with each timed device, or end node as described above, to extract a timing reference signal such as the 1PPS signal. In some cases, an Ethernet switch with an integrated processor may be used, however, the switch must also be co-located with the timed device. The additional application processor to generate the 1PPS signal may raise the cost, heat, and power consumption of precision timing. As described in more detail below, the Ethernet PHY device provides precision timing using only a simple clock that is controlled by the host.

<FIG> is a block diagram of an Ethernet PHY device <NUM> for data communications, and may represent the Ethernet PHY device <NUM> of <FIG>. While the device is described as an Ethernet PHY device, it may also support other package or data protocols and formats and may be adapted to other data communication purposes while still providing precision timing as described herein. The Ethernet PHY device <NUM> has a front end/hybrid <NUM> coupled to the network <NUM> and a host data interface <NUM>, coupled to a host <NUM> through a data link <NUM>. The host may be implemented as a processor <NUM> as shown in <FIG> or another type of host processor or application processor. Alternatively, the host may be a remote device in the network <NUM> connected through the network. In some embodiments, the host runs PTP or gPTP when controlling the Ethernet PHY device <NUM>. The host <NUM> provides control and configuration commands to the Ethernet PHY device <NUM> and may use any suitable communications protocol. As examples, such communications protocols include a serial peripheral interface (SPI) or any suitable type of media independent interface (MII), such as reduced MII (RMII), gigabit MII (GMII), reduced gigabit MII (RGMII), or the like, among others.

In some embodiments, the Ethernet PHY device <NUM> is implemented as an Ethernet PHY device <NUM> with a time stamping engine <NUM> that also generates and outputs a precision timing output signal <NUM>, such as a 1PPS signal without the use of an application processor. This eliminates the need for a more expensive switch or a local applications processor associated with the circuit board <NUM> as shown in <FIG> or with each network node of the system. The Ethernet PHY device is a much simpler system than a full switch. The Ethernet PHY device <NUM> may be the same or different from the Ethernet PHY device <NUM> of <FIG> and may be on a similar or very different circuit board.

While embodiments herein are described in the context of Ethernet networks and PHY, the invention is not so limited. The methods and structures described herein may be applied to different network configurations and network protocols. Similarly, while the Ethernet PHY device outputs a 1PPS signal, any other type of reference timing signal may be used and presented instead.

The host data interface <NUM> sends data to the network <NUM> through a data transmitter that includes a transmit physical coding sublayer (PCS-TX) <NUM> and a transmit physical medium attachment (PMA-TX) <NUM>. Similarly, data from the network <NUM> is received through a data receiver that includes a receive physical medium attachment (PMA-RX) <NUM> and a receive physical coding sublayer (PCS-RX) <NUM> to forward data to the host data interface <NUM>. The PMA-TX <NUM> and PMA-RX <NUM> connect to the network <NUM> through a front end/hybrid <NUM> that is connected directly to the transmission medium of the network <NUM>.

Data received from the network <NUM> arrives at the front end/hybrid <NUM> and is passed to the PMA-RX <NUM> which converts the analog signals received over the transmission medium to symbols. The PCS-RX <NUM> converts the symbols to bits and decodes and demultiplexes the symbols for the host data interface <NUM>. The PCS-RX <NUM> forwards packets that require a time stamp to a time stamping engine <NUM>. The packets are then forwarded to the appropriate end node, typically the host through a host data interface (I/F) <NUM>. The time stamping engine <NUM> is coupled to the PCS-TX <NUM> to time stamp outgoing packets, to a 1PPS output generator <NUM> to provide precision timing to other components.

The PHY controller <NUM> may include an instruction processor and a memory or storage medium to execute computer-readable instructions that are stored in the memory. The 1PPS output generator <NUM> generates the precision timing output signal <NUM> for use by other external components, such as processors, interfaces, sensors, and other connected devices including the host <NUM>. The precision timing output signal <NUM> is based on the timing of the time stamping engine <NUM>. In some embodiments the 1PPS output generator <NUM> is a counter that creates the precision timing output signal <NUM> as a pulse after a preconfigured number of time stamping engine pulses.

In some embodiments, packets are sent and received from a grandmaster clock through the network <NUM> in accordance with a PTP or gPTP protocol. The sent packets have a time stamp from the time stamping engine <NUM> and receive a time stamp at the grandmaster clock. The received packets have a time stamp from the grandmaster clock and receive a time stamp upon receipt at the time stamping engine <NUM>. The multiple time stamps may be used to determine precision timing at the host. Many other packets may be provided directly to the host through the host data interface <NUM> without receiving a time stamp from the time stamping engine <NUM>.

The Ethernet PHY device <NUM> further may include a crystal oscillator/clock <NUM> to clock operations on the Ethernet PHY device <NUM>, a phase locked loop (PLL) <NUM> to align timing for components within the Ethernet PHY device <NUM>, and voltage inputs and voltage controls <NUM> to receive voltage inputs, control the received voltage inputs and distribute power throughout the Ethernet PHY device <NUM>. The Ethernet PHY device <NUM> may be controlled by the host <NUM> in any suitable manner. In some embodiments, the data link <NUM> to the host <NUM> includes system management data that is coupled to a system management interface (SMI) <NUM> of the Ethernet PHY device <NUM>. Additional configuration and reset controls may also be provided to configuration and reset controls <NUM> of the Ethernet PHY device. Through the SMI <NUM> and PHY controller <NUM>, configuration and reset control parameters may be propagated through the Ethernet PHY device including PHY mode control <NUM> and top mode control and registers <NUM> to regulate the operation of the Ethernet PHY device <NUM>. MDIO (Management Data Input/Output) may also be used by the host to control operations and parameters on the PHY.

<FIG> is a block diagram of a time stamping engine <NUM> suitable for use with the Ethernet PHY device of <FIG>. The time stamping engine is augmented with precision timing components that may be used to support PTP or gPTP over the network <NUM>. The time stamping engine <NUM> includes transmit time stamping logic <NUM> connected to a PCS-TX <NUM> to time stamp outgoing packets and receive time stamping logic <NUM> connected to a PCS-RX <NUM> to time stamp incoming data. The incoming and outgoing data are connected to a host data interface <NUM> that may use any suitable control and configuration protocol, system management interface, or media independent interface, such as RMII or MII. The transmit and receive time stamping logic <NUM>, <NUM> are coupled to a time stamping timer/counter <NUM> that provides the timing information. In some embodiments, the time stamping engine <NUM> or the entire Ethernet PHY device <NUM> is dedicated to received data. A second time stamping engine <NUM> or Ethernet PHY device processes transmitted data. This may allow for higher date throughput in some configurations.

The time stamping counter/timer <NUM> also optionally provides timing to a 1PPS modulus counter(s) <NUM> which counts the timing from the time stamping counter/timer <NUM> and generates a 1PPS output signal <NUM> at <NUM> second intervals. The 1PPS output signal <NUM> is connected to a 1PPS output interface <NUM> that sends one or more 1PPS output signals to one or more timed nodes as described above. While the present description is presented in the context of a 1PPS output signal, any other precision timing signal with any other timing interval may be used instead. In some examples not falling under the scope of protection, there is no 1PPS modulus counter(s) <NUM> or 1PPS output interface <NUM> and the time stamping counter/timer <NUM> is used only to provide precision timing for the transmit and receive time stamping logic <NUM>, <NUM>.

Some precision timing protocols contemplate that the host determines the precision timing and adjusts, modifies, or changes time stamps for data received through an Ethernet PHY device to show the precision timing instead of the timing from the Ethernet PHY device. To accommodate such a configuration of the host, the time stamping engine may be modified so that the transmit and receive time stamping logic are coupled to a different timing source, such as the crystal oscillator/clock <NUM> or PLL <NUM> of the Ethernet PHY device. In such an embodiment, the precision time components of the time stamping engine are used to support a precision timing output signal such as a 1PPS output interface <NUM>. A clock such as the time stamping PLL <NUM> is coupled to one or more counters to generate the 1PPS output signal <NUM> as a precision timing signal at the 1PPS output interface <NUM> independent of the host and any time stamping functions. Such an embodiment of the time stamping engine <NUM> may be identified as a precision timing reference or clock. The host may still be able to syntonize and synchronize the clock of the Ethernet PHY device in the same way as for time stamping.

The time stamping timer/counter <NUM> is controlled by a time stamping PLL <NUM> that is coupled to the time stamping counter timer/counter <NUM>. The time stamping PLL <NUM> generates a timing reference signal <NUM> that acts as an accurate precision timing signal into the time stamping timer/counter. In some embodiments, the time stamping PLL <NUM> is a separate PLL in the time stamping engine <NUM> that only controls the time stamping engine. The separate time stamping PLL acts independently as a time stamping clock that allows the timing to be synchronized only to an appropriate reference clock source such as a grandmaster clock as defined in precision timing protocols. The time stamping PLL is independent of the Ethernet PHY device PLL and of the host clock. Therefore, the timing reference signal <NUM> controls the timing of the time stamping timer/counter <NUM> which controls the timing of the 1PPS modulus counter(s) <NUM>. As a result, the 1PPS output interface <NUM> generates pulses that are also synchronized with a grandmaster clock independent and separate from any other clock except the time stamping PLL <NUM>.

A PHY controller <NUM> is coupled to the host <NUM> as shown in <FIG> to receive timing and phase adjustment parameters. The PHY controller <NUM> is also coupled to the time stamping PLL <NUM> to provide the timing and phase adjustment parameters to the time stamping PLL <NUM>. The PHY controller <NUM> is coupled to the time stamping timer/counter <NUM> to provide counts and timer/counter register adjustments from the host. The PHY controller <NUM> is coupled to the 1PPS modulus counter(s) <NUM> to provide counts, initial values and modulo values from the host.

Using any suitable communications protocol, such as MDIO, the host may provide adjustment commands to the time stamping engine <NUM> that can make small adjustments to the time stamping PLL <NUM> to syntonize its frequency and synchronize its phase with a timing reference, such as a grandmaster clock or with a harmonic relationship to the grandmaster clock. In some embodiments, these parameters are adjusted through the PHY controller <NUM>. In some embodiments, working through a communications protocol, such as MDIO, the host may write parameter adjustments directly to the time stamping PLL <NUM>, to the time stamping timer/counter <NUM>, to the 1PPS modulus counter(s) <NUM>, and other time stamping engine parameters which can be reset or otherwise controlled as necessary.

As shown, the time stamping timer/counter <NUM> is connected to the 1PPS modulus counter(s) <NUM> and feeds the 1PPS modulus counter(s) <NUM> with a timing signal. Using the input timing signal, the 1PPS modulus counter(s) <NUM> generates one or more 1PPS output signals <NUM> that each have a pulse at one second intervals or any other suitable interval that may be configured by the host. Each 1PPS output signal <NUM> may occur at a beginning of each second of a reference clock, such as a PTP grandmaster clock. Alternatively, each <NUM> PPS output signal <NUM> may begin at some fixed positive or negative delta, representing an advance or a delay, before or after the beginning of each second of the reference clock based on one or more configuration parameters set by the host.

Accordingly, using multiple configuration registers, each 1PPS output signal <NUM> may be individually set for a different specific positive or negative delta, representing an advance or a delay duration, relative to the reference clock as required by the overall needs of the intended end node, such as other electronics on the board.

The value of each delta may be adjusted such that the 1PPS outputs sent from the 1PPS output interface <NUM> arrive at the respective destination on a board or other subsystem at the same time taking into consideration the propagation delay of the 1PPS signals from the Ethernet PHY device and the time stamping PLL <NUM> to the respective receiving end node. By providing sufficient time resolution in the 1PPS modulus counter(s) <NUM> and by accurately measuring propagation delays, each end node may be precisely synchronized. The host may receive measurements and set the operational configuration and parameters of the 1PPS modulus counter(s) <NUM> using a communications protocol through the host data interface, such as SMII to the PHY controller <NUM> or another control entity of the Ethernet PHY device.

In some protocols, a timing pulse, such as a 1PPS output signal <NUM> is received based on a rising edge of the signal. In other protocols, a falling edge or a peak or some other aspect of a waveform may be used. Different end nodes may use different circuits to determine the timing and there may be variations in the signal waveform due to the propagation path and other factors. These effects may all cause different timing inaccuracies, some of which may be referred to as signal jitter. The jitter relative to the desired 1PPS timing for each output may also be compensated for in each 1PPS output signal <NUM>. A relative accuracy may be programmed into the components of the Ethernet PHY device by setting parameters and registers through the SMI or any other communications protocol from the host.

The timing of the time stamping timer/counter <NUM> may be corrected by syntonizing the frequency of the time stamping timer/counter <NUM> with the grandmaster clock. The phase may also be corrected by synchronizing the phase of the time stamping timer/counter <NUM> with the grandmaster clock. In some embodiments, the host <NUM> uses the timestamped information from transmitted and received precision timing packets with the grandmaster clock, to determine how well the time stamping timer/counter <NUM> is syntonized and synchronized to the grandmaster. Having determined the accuracy of the time stamping timer/counter <NUM>, the host can send commands to adjust the frequency and phase of the time stamping PLL <NUM>, consequently adjusting the accuracy of the time stamping timer/counter <NUM>. This process may be repeated until the syntonization and synchronization to the grand master meets the desired system timing accuracy requirements. The adjustment process may then be repeated on a periodic basis. In some embodiments, the host <NUM> is co-located with or directly connected to a timing master such as a GNSS receiver and adjusts the time stamping PLL <NUM> based on the directly connected timing master.

Using the time stamping PLL <NUM> together with the time stamping timer/counter <NUM> and the 1PPS modulus counter(s) <NUM>, the time stamping engine <NUM> is able to generate output timing signals and data time stamps with high precision without any ongoing action from the host <NUM>, the PHY controller <NUM> or any other processing resources of the system. This reduces cost and power consumption at the Ethernet PHY device <NUM>, the host <NUM> and for the overall system. Precise timing may be provided throughout an in-vehicle network <NUM> or other type of network using Ethernet PHY devices similar to that shown and described herein instead of more complex and expensive switches. Precise timing from one or a few grand master clocks may be propagated throughout the network as described herein without the need for additional reference clocks, such as GNSS receivers.

While the host <NUM> or another processor periodically syntonizes and synchronizes the time stamping engine <NUM>, this has a very small impact on the available processing resources. The time stamping engine may be adjusted by the host with a period of seconds or any other suitable interval, while the host may have a clock rate counted in nanoseconds or picoseconds. In alternative configurations, a host may generate the 1PPS signals and adjust the time stamps from each package received through a PHY. The host is able to do this using accurate timing that is known only to the host. By using a time stamping PLL <NUM> that is unique within the time stamping engine <NUM>, as described herein, the host is no longer required to generate precision timing output signals <NUM> nor correct time stamps from the PHY.

<FIG> is a process flow diagram of operating an Ethernet PHY device to provide precision timing as described above. At <NUM>, data are received from a host at a PHY device for transmission by the PHY device. At <NUM>, data are time stamped and transmitted to network nodes from a PHY device. At <NUM>, data are received from network nodes and time stamped at the PHY device. In some embodiments, these are in the form of Ethernet packets, but other data protocols and configurations may be used instead. The time stamps are based on a time stamping clock of a time stamping engine of the PHY device. The time stamping clock may be independent of the host clock and independent of the crystal oscillator and PLL of the PHY device.

At <NUM>, the time stamped received data is transmitted to the host that is coupled to the PHY device through a host interface of the PHY device. The host may be a processor or controller on the same circuit board or even in the same integrated circuit package. The host may be coupled to other devices including sensors and other network nodes. The host may also be configured to control the PHY device through the host interface using any of a variety of different command, control, or management protocols.

At <NUM>, the host calculates phase and frequency adjustment to apply to the time stamping clock. In some embodiments the host is able to determine precision timing by sending and receiving packets with a grandmaster clock or other reference timing source through the PHY device. With PTP, precision timing may be determined by sending a sequence of timestamped packets to the reference timing source and receiving timestamped replies. The host may also be able to determine precision timing by reference to a local reference timing source.

At <NUM>, phase and frequency adjustments are received from the host through the host interface. These adjustments may be received as configuration commands or in another format depending on the control or management interface between the host and the PHY device. The configuration commands are derived by the host using the precision timing that was determined using the PTP or another basis for determining precision timing.

At <NUM>, the phase and frequency of the time stamping clock are adjusted based on the received phase and frequency configuration commands. In some embodiments the commands are received as values to be written to registers of the time stamping engine. In some embodiments, the time stamping engine operates as a state machine and the phase and frequency of the time stamping clock is controlled by stored parameters. The time stamping clock may include a PLL and a counter/timer so that as the phase and frequency of the PLL is modified by configuration registers, the timing is subsequently modified in the counter/timer.

With periodic phase and frequency adjustments by the host, the time stamping clock may be syntonized and synchronized with any desired reference timing source. The time stamping clock maintains this syntonization and synchronization independent of a host clock, a PHY clock or any other clock. In this way the time stamps are aligned with the reference timing source independent of direct action by the host. The host is able to perform other functions and then check and adjust the phase and frequency only periodically.

At <NUM>, a precision timing output signal is generated based on the time stamping clock as applied to a counter. The precision timing output signal may be transmitted to external nodes so that the external nodes are also syntonized and synchronized to the precision timing reference. In some embodiments, the PHY device includes a precision timing output interface coupled to a counter coupled to the time stamping clock. The counter may be a modulus counter(s) that counts timing pulses of the time stamping engine clock to determine a timing duration, such as <NUM> second of the timing reference. The modulus counter(s) may also be coupled to the host through the host interface to receive configuration commands including a modulus adjustment. The precision timing output signal may be sent to one or more local nodes and also to remote network nodes on the network. Multiple precision timing output signals may be generated for different nodes with different advances or delays to suit different external nodes.

<FIG> is an alternative process flow diagram of operating an Ethernet PHY device to provide precision timing as described above. At <NUM>, data received from the host or another node is transmitted to network nodes from a PHY device. At <NUM>, data are received from network nodes at the PHY device and transmitted to the host or other local devices. In some embodiments, these are in the form of Ethernet packets and are time stamped using a local clock or a precision independent clock. In some embodiments, the PHY device has only a transmitter or only a receiver.

At <NUM>, a clock of the PHY device is applied to a modulus counter of the PHY device. The clock may be a precision PLL or any other clock. At <NUM>, a precision output timing signal is generated based on the modulus counter. At <NUM>, the precision timing output signal is transmitted to external nodes so that the external nodes are also syntonized and synchronized to the precision timing reference using the clock and the modulus counter of the PHY device. In some embodiments, the PHY device includes a precision timing output interface coupled to a counter coupled to the time stamping clock. The modulus counter(s) may be coupled to the host through the host interface to receive configuration commands including a modulus adjustment. Multiple precision timing output signals may be generated for different nodes with different advances or delays to suit different external nodes.

At <NUM>, the phase and frequency of the clock are adjusted based on the received phase and frequency configuration commands. These commands may include adjustments to one or more modulus counters and advances or delays to one or more precision output timing signals.

As in the other examples above, the periodic phase and frequency adjustments by the host, syntonize and synchronize the clock on the PHY device with any desired reference timing source. The accuracy of the clock improves at each cycle and the adjustment cycles are repeated to obtain the desired accuracy and to maintain the desired accuracy independent of a host clock and without requiring the host to send reference timing signals directly or indirectly to other components on a board or system level.

Aspects of the above-described operations of the PHY device can be implemented in hardware, firmware, software, or a combination thereof. In an embodiment, the time stamping engine and the time stamping engine control and configuration is implemented with hardware logic circuits. In another embodiment, a PHY chip may include a PHY controller and a host controller that have an instruction processor and storage for instructions and parameters to implement the described functions through computer-readable instructions that are executed by the instruction processor.

It should also be noted that at least some of the operations for the methods described herein may be implemented using software instructions stored on a computer-useable storage medium for execution by a computer. As an example, an embodiment of a computer program product includes a computer-useable storage medium to store a computer-readable program.

The computer-useable or computer-readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device). Examples of non-transitory computer-useable and computer-readable storage media include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include a compact disk with read only memory (CD-ROM), a compact disk with read/write (CD-R/W), and a digital video disk (DVD).

Alternatively, embodiments of the invention may be implemented entirely in hardware or in an implementation containing both hardware and software elements. In embodiments which use software, the software may include but is not limited to firmware, resident software, microcode, etc..

Claim 1:
A physical layer, PHY, device (<NUM>) for a network (<NUM>), the PHY device comprising:
a transmitter (<NUM>, <NUM>) configured to transmit data at the PHY device from a host (<NUM>, <NUM>) to an external network (<NUM>, <NUM>) that is external to the
PHY device; a clock of the PHY device (<NUM>, <NUM>) to align timing for components within the PHY device ;
a host interface (<NUM>) configured to receive the data to transmit from the host (<NUM>) and configured to receive configuration commands from the host;
a time stamping engine (<NUM>) having a time stamping clock and configured to apply a time stamp to the data transmitted by the transmitter based on the time stamping clock,
the time stamping clock being independent of a host clock and coupled to the host interface to receive phase and frequency adjustments as configuration commands from the host to thereby adjust the phase and frequency of the time stamping based on the received configuration commands;
the time stamping engine further comprising a modulus counter (<NUM>) configured to count a preconfigured number of timing pulses of the clock;
wherein the time stamping engine (<NUM>) comprises a time stamping phase-locked loop, PLL, (<NUM>), coupled to the modulus counter (<NUM>), wherein the PLL (<NUM>) is configured provide a timing source that is independent of the clock (<NUM>) of the PHY device; and
a timing output interface (<NUM>) coupled to the modulus counter (<NUM>) to produce a precision timing output signal (<NUM>) based on detecting the preconfigured number of timing pulses of the clock.