Patent Description:
Classical computers have memories made up of bits, where each bit can represent either a zero or a one. Quantum computers maintain sequences of quantum bits, called qubits, where each quantum bit can represent a zero, a one, or any quantum superposition of zeros and ones. Quantum computers operate by setting qubits in an initial state and controlling the qubits, e.g., according to a sequence of quantum logic gates. A calculation may include collapsing the system of qubits into an eigenstate where each qubit represents either a zero or one. Measurements may be made both during and at the end of a calculation. For instance, in a quantum error correction algorithm, measurements are made each cycle to detect errors. In addition, measurements are often carried out on a subset of the qubits as opposed to the entire array.

In <NPL>) a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F<NUM>,<NUM> digitally controlled oscillator required to manipulate the state of qubits.

<NPL>) explores the feasibility of <NUM> (liquid Helium temperature) CMOS data converters to work it as a cryogenic waveform generator to produce the necessary stimuli for the qubits.

<NPL>) describe the operation of a cryogenic instrumentation platform incorporating commercially available field-programmable gate arrays (FPGAs). The functionality of the FPGAs at temperatures approaching <NUM> enables signal routing, multiplexing, and complex digital signal processing in close proximity to cooled devices or detectors within the cryostat. The performance of the FPGAs in a cryogenic environment is evaluated, including clock speed, error rates, and power consumption. Although constructed for the purpose of controlling and reading out quantum computing devices with low latency, the instrument is generic enough to be of broad use in a range of cryogenic applications.

In Korotkov A. "Double-balanced mixer based on MOSFETs" (DOI: <NUM>/S1063739711020053) an analysis of an integrated MOSFET-based Gilbert-cell mixer is presented. Methods are described for calculating its major ac and dc parameters, including those characterizing conversion gain, noise performance, and nonlinear distortions. The performance of the proposed implementation is estimated. Comparisons are made with computer simulations.

<NPL>) demonstrate a universal set of logic gates in a superconducting multi-qubit processor, achieving an average single-qubit gate fidelity of <NUM> per cent and a two-qubit gate fidelity of up to <NUM> per cent. This places Josephson quantum computing at the fault-tolerance threshold for surface code error correction. Thier quantum processor is a first step towards the surface code, using five qubits arranged in a linear array with nearest-neighbour coupling. As a further demonstration, we construct a five-qubit Greenberger-Horne-Zeilinger state using the complete circuit and full set of gates. The results demonstrate that Josephson quantum computing is a high-fidelity technology, with a clear path to scaling up to large-scale, fault-tolerant quantum circuits.

The matter for protection is set out in the appended claims.

The qubit control electronics of the present disclosure may be embodied in an integrated circuit (IC) that includes CMOS integrated circuit elements. The IC may be operated in a low temperature environment such as an intermediate cooling stage (e.g., between about <NUM>-<NUM>) of a cryostat between room temperature and the operating temperature of the superconducting qubits. The qubit control electronics, which may be embodied in the IC, generate qubit control signals, such as qubit XY control signals, using an envelope generator circuit that is electrically coupled to a mixer circuit. The signal envelope generator circuit generates a signal envelope, and includes multiple individual signal sources (e.g., current sources), which may be programmable. In certain implementations, the envelope generator circuit cumulatively sums the outputs from the multiple individual signal sources and provides the summed output to a first mixer circuit of a vector modulator circuit. The first mixer circuit may include, e.g., a double balanced mixer circuit, for up-conversion of the summed output of the envelope generator circuit. The first mixer circuit mixes a summed output from the signal envelope generator circuit with a local oscillator signal to provide the qubit control signal. In some implementations, the qubit control electronics include a second envelope generator circuit coupled to a second mixer circuit of the vector modulator circuit, in which the second envelope generator circuit is constructed in the same manner as the first envelope generator circuit. The output of the second mixer circuit may be combined with the output of the first mixer circuit to provide the qubit control signal.

The qubit control electronics disclosed herein may have various advantages. For example, in some implementations, the qubit control electronics disclosed herein may be used to reduce the cabling requirements of a quantum computing system. The qubit control electronics may also reduce power consumption of a quantum computing system. The qubit control electronics of the present disclosure may be used without adversely affecting error rates while consuming of the order of <NUM> mW/qubit or less, such that cryogenic cooling of the qubit control electronics is feasible. By enabling operation of the qubit control electronics at cryogenic temperatures, power consumption may be reduced even further by allowing the use of lossless superconducting interconnects, rather than room-temperature interconnects, to transfer data between the qubit control electronics and the device on which the qubits are formed.

In general, in certain aspects, the subject matter of the present disclosure may be embodied in a device for generating a qubit control signal, in which the device includes: a first signal envelope generator circuit including a first multiple of signal sources, in which an output of each signal source of the first multiple of signal sources is combined to provide a first cumulative output; and a first mixer circuit coupled to the first signal envelope generator circuit, in which the first cumulative output is coupled to a first input of the first mixer circuit, and an output of the first mixer circuit includes a first qubit control signal.

Implementations of the device may include one or more of the following features. For example, in some implementations, the first multiple of signal sources includes a multiple of current sources. The multiple current sources may include programmable current sources. The output of each current source may be tied to a common node.

In some implementations, the first signal envelope generator circuit includes a variable capacitor coupled to the first cumulative output.

In some implementations, the first signal envelope generator circuit includes a delay circuit coupled to the first multiple of signal sources. The delay circuit may include multiple flip-flops configured to cause sequential activation and deactivation of the first plurality of signal sources.

In some implementations, the first mixer circuit includes a double balanced mixer circuit. The double balanced mixer circuit may include multiple MOSFETS.

In some implementations, the first mixer circuit is configured to mix the first cumulative output with a local oscillator signal received at a second input of the first mixer circuit.

In some implementations, the device includes memory. The device may include a multiplexer array coupled to the memory and to the first signal envelope generator circuit.

The device further includes: a second signal envelope generator circuit including a second multiple of signal sources, in which an output of each signal source of the second multiple of signal sources is combined to provide a second cumulative output; and a second mixer circuit, in which the second cumulative output is coupled to a first input of the second mixer circuit, an output of the second mixer circuit includes a second qubit control signal, and the first qubit control signal is combined with the second qubit control signal to provide a qubit XY control signal. The first mixer circuit may be configured to mix the first cumulative output with a first local oscillator signal received at a second input of the first mixer circuit and the second mixer circuit may be configured to mix the second cumulative output with a second local oscillator signal received at a second input of the second mixer circuit. The first local oscillator signal may be out of phase with the second local oscillator signal. For example, the first local oscillator signal may be out of phase with the second local oscillator signal by any one of <NUM>°, <NUM>°, or <NUM>°.

In some implementations, the device is an integrated circuit chip.

In general, in another aspect, the subject matter of the present disclosure may be embodied in a quantum computing system that includes: a cooling device capable of providing multiple cooling stages, in which each cooling stage is maintained at a different temperature; a qubit chip including a qubit, in which the qubit chip is arranged in the cooling device and maintained at a first cooling stage, in which a temperature of the first cooling stage is between <NUM> and <NUM> mK; and a control circuit for generating a qubit XY control signal arranged in the cooling device and maintained at a second cooling stage, in which a temperature of the second cooling stage is above the temperature of the first cooling stage and below room temperature, and in which the control circuit is coupled to qubit chip. The control circuit for generating the qubit XY control may include any of the qubit control signal generating devices described above.

In general, in another aspect, the subject matter of the present disclosure may be embodied in methods for generating a qubit control signal, the methods including: sequentially activating a first multiple of signal sources; combining an output of the sequentially activated first multiple of signal sources to provide a first combined output; passing the first combined output to a first mixer circuit; and mixing the first combined output with a local oscillator signal in the first mixer circuit to provide a first qubit control signal.

Implementations of the methods may include one or more of the following features. For example, in some implementations, the first multiple of signal sources includes a first multiple of current sources. The first multiple of current sources may be programmable current sources.

In some implementations, the methods include sequentially deactivating the first multiple of signal sources. The first combined output may include a combined output of the sequentially deactivated first multiple of signal sources.

In some implementations, the methods further include smoothing the first combined output prior to passing the first combined output to the first mixer circuit.

In some implementations, the methods further include: sequentially activating a second multiple of signal sources; combining an output of the sequentially activated second multiple of signal sources to provide a second combined output; passing the second combined output to a second mixer circuit; mixing the second combined output with a second local oscillator signal in the second mixer circuit to provide a second qubit control signal; and combining the first qubit control signal with the second qubit control signal to provide a qubit XY control signal. The first local oscillator signal may be out of phase with the second local oscillator signal.

In some implementations, methods are performed in an environment where the temperature is above <NUM> mK and below <NUM>.

The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description.

Quantum computing entails coherently processing quantum information stored in the quantum bits (qubits) of a quantum computer. Superconducting quantum computing is a promising implementation of solid-state quantum computing technology in which quantum information processing systems are formed, in part, from superconducting materials. To operate quantum information processing systems that employ solid-state quantum computing technology, such as superconducting qubits, the systems are maintained at extremely low temperatures, e.g., in the <NUM> of mK. The extreme cooling of the systems keeps superconducting materials below their critical temperature and helps avoid unwanted state transitions. To maintain such low temperatures, the quantum information processing systems may be operated within a cryostat, such as a dilution refrigerator. In some implementations, control signals are generated in higher-temperature environments, and are transmitted to the quantum information processing system using shielded impedance-controlled GHz capable transmission lines, such as coaxial cables. The cryostat may step down from room-temperature (e.g., about <NUM>) to the operating temperature of the qubits in one or more intermediate cooling stages. For instance, the cryostat may employ a first stage maintained at a first temperature range T1 that is colder than room temperature stage by one or two orders of magnitude, e.g., about <NUM>-<NUM> or about <NUM>-<NUM>, and warmer than the operating temperature for the qubits (e.g., about <NUM> mK or less or about <NUM> mK or less).

Even at the extremely low qubit operating temperatures, qubits may still suffer from decoherence and gate errors. As such, large-scale quantum error correction algorithms can be deployed to compensate for the gate errors and qubit decoherence. An error-corrected quantum processor leverages redundancy to synthesize protected logical qubits from ensembles of error-prone qubits. While the required degree of redundancy depends on the error rates of the constituent qubits, in certain implementations, it is expected that at least <NUM>,<NUM> physical qubits may be required to realize a single error-corrected logical qubit. Implementations of current superconducting quantum systems use, e.g., at least two room-temperature co-axial cables per qubit to provide the qubit control signal. Moreover, to solve complex problems using a quantum computer, it is expected that upwards of <NUM>,<NUM> or more error-corrected logical qubits may be necessary. Using present systems, such scaling may require millions of separate cables. Additionally, such a system would require significant power consumption to generate the control signals that drive the qubits of the quantum processor.

The present disclosure is directed to qubit control electronics that may be used to reduce the cabling requirements of a quantum computing system, and that may also reduce power consumption of a quantum computing system. The qubit control electronics of the present disclosure may be used without adversely affecting error rates while consuming of the order of <NUM> mW/qubit or less, such that cryogenic cooling of the qubit control electronics is feasible. By enabling operation of the qubit control electronics at cryogenic temperatures, power consumption may be reduced even further as lossless superconducting interconnects, rather than room-temperature interconnects, may be used to transfer data between the qubit control electronics and the device on which the qubits are formed. In addition, the on-chip waveform memory provides a means to greatly reduce the amount of data transfer required to produce the bandlimited XY control signals.

The qubit control electronics of the present disclosure may be embodied in an integrated circuit (IC) that includes, e.g., CMOS integrated circuit elements on a flat (an in some implementations, monolithic) piece or chip of semiconductor material, such as silicon. The IC may be operated in a low temperature environment such as an intermediate cooling stage (e.g., between about <NUM>-<NUM>) of a cryostat between room temperature and the operating temperature of the superconducting qubits. The qubit control electronics, which may be embodied in the IC, generate qubit control signals using a first signal envelope generator circuit that is electrically coupled to a first mixer circuit. The signal envelope generator circuit generates a signal envelope, and includes multiple individual signal sources (e.g., current sources), which may be programmable. In certain implementations, the envelope generator circuit cumulatively sums the outputs from the multiple individual signal sources and provides the summed output to the first mixer circuit. The first circuit mixer circuit may include, e.g., a double balanced mixer circuit element, for up-conversion of the summed output of the envelope generator circuit. The first mixer circuit mixes a summed output from the first signal envelope generator circuit with a local oscillator signal to provide the qubit control signal. The qubit control electronics include a second signal envelope generator circuit coupled to a second mixer circuit, in which the second signal envelope generator circuit is constructed in the same manner as the first envelope generator circuit. The first and second mixer circuits may form part of a vector modulator circuit. The output of the first mixer circuit may be combined with the output of the second mixer circuit to provide the qubit control signal, such as a qubit XY control signal.

Prior to describing further details of the qubit control electronics, a brief review of a standard quantum computing system including the qubits, the quantum control elements, and quantum measurement is provided.

An ideal qubit is a two level system whose state can be represented as a superposition of its eigenstates, |ψ〉=cos(θ/<NUM>)|<NUM>〉 + exp{jφ}sin(θ/<NUM>)|<NUM>〉. Accordingly, the state of a qubit has a unique interpretation as a point on the surface of the Bloch sphere. In a typical quantum algorithm, a sequence of, e.g., single- and/or two-qubit gates is applied to a collection of qubits, after which the states of a subset of these qubits are measured. Single-qubit gates include well-defined rotations on the surface of the Bloch sphere, whereas two-qubit gates are conditioned rotations on the Bloch sphere.

<FIG> is a schematic diagram that illustrates a single qubit quantum computing system. The quantum computing system includes a qubit chip <NUM> coupled to qubit control electronics <NUM>. The qubit chip <NUM> includes one or more qubits <NUM>, such as superconducting qubits, and may be operated using a cryostat at extremely low temperatures (e.g., at around <NUM> mK or less, such as <NUM> mK, subject to the minimum possible temperature achievable by the cryostat). For the purposes of this disclosure, the qubits operated by the qubit control electronics are assumed to be frequency tunable transmon qubits, which have fast gate times (e.g., <<NUM> ns), low single- and two-qubit error rates (e.g., <<NUM>% and <<NUM>%, respectively), moderate coherence times (e.g., ~<NUM>), and monolithic implementation. However, the qubit control electronics described herein are not limited to working with transmon qubits and may also be used with other qubit configurations, such as fluxmon qubits or gmon qubits, among others. Each qubit <NUM> of the qubit chip <NUM> may be coupled to a Z-drive qubit circuit element <NUM> (e.g., a resonator), an XY -drive qubit circuit element <NUM> (e.g., a capacitor), and a qubit readout resonator <NUM>. The qubits <NUM> and associated circuit elements formed on the qubit chip <NUM> can be formed from patterned superconductor materials on a dielectric substrate (e.g., aluminum on a silicon or sapphire substrate).

The qubit chip <NUM> is coupled to the qubit control electronics <NUM>, which are operated at room temperature (e.g., about <NUM>). Data lines that connect the control electronics <NUM> to the qubit chip <NUM> may pass through one or more low temperature intermediate stages of the cryostat. For instance, the qubit Z-control lines <NUM>, qubit XY control lines <NUM>, and qubit readout lines <NUM> may pass through an intermediate stage of the cryostat that is cooled to below room temperature but above the qubit operating temperature, e.g., at around <NUM>-<NUM>. In some implementations, the control lines may also include attenuators (e.g., attenuator <NUM>, <NUM>) or amplifiers (e.g., amplifier <NUM>). The data lines may be coupled to ports (e.g., ports <NUM>, <NUM>, and <NUM>) on the qubit chip <NUM>.

As shown in <FIG>, the qubit <NUM> is a non-linear resonator that includes a capacitor in parallel with a pair of Josephson Junctions (illustrated as X's) wired in a loop to form a squid whose effective inductance can be tuned by threading the loop with an external magnetic flux drive (e.g., provided by the Z-drive line <NUM>). The nonlinearity associated with the Josephson junction(s) results in an anharmonic energy diagram <NUM> as shown in <FIG>, in which discrete energy levels (<NUM>, <NUM>, <NUM>, <NUM>) are formed. The separation between energy levels may be expressed as ΔE = hfmn, where h is Planck's constant, and fmn is the frequency difference between energy levels m and n. Typical values of f<NUM> and f<NUM> - f<NUM> are <NUM> and <NUM>, respectively. As such, it is possible to exclusively address the |<NUM>〉 to |<NUM>〉 transition using a microwave (XY) drive, thereby approximating the desired two-level qubit.

Microwave gate operations on qubits, such as qubits <NUM>, can be carried out by generating an XY control signal at the control electronics <NUM> and then applying the XY control signal, when the qubit is operating at its resonant frequency, to the XY port <NUM> of the qubit <NUM>, resulting in a deterministic rotation of the qubit state about an axis in the XY plane of the Bloch sphere, where the axis and angle of rotation are determined by the carrier phase and integrated envelope amplitude of the microwave signal, respectively. The finite coherence time of a qubit makes it desirable to minimize the duration of the applied pulse, but a temporally short pulse contains a broad spectrum of frequencies. Thus, there is a tradeoff between pulse duration and population of the |<NUM>〉 state, as energy in the pulse sideband can couple to thef<NUM> transition. As such, the XY pulses employed to drive qubits are typically shaped to minimize leakage to the |<NUM>〉 state, with Gaussian and raised cosine envelopes among the most popular. Exemplary pulse durations and envelope amplitudes, referenced to the XY port <NUM>, are <NUM>-<NUM> ns and <NUM>-<NUM> µV, respectively. The state of the qubit <NUM> can be sensed through a projective measurement in which the reflection coefficient of the readout resonator <NUM> is measured, causing the qubit to collapse to the |<NUM>〉 state with probability of cos<NUM>(θ/<NUM>) and to the |<NUM>〉 state with probability sin<NUM>(θ/<NUM>). Depending on which state the qubit collapses to, the measured reflection coefficient will take on one of two distinct values.

Standard control circuits <NUM> operating at room temperature use high-speed (~ <NUM> GSPS or higher) and high-resolution (~ <NUM>-bit) digital to analog converter (DAC) waveform generators to generate each qubit XY control signal. Such high-speed waveform generators consume a substantial amount of power.

Rather than using high-power, high-speed and extremely high resolution DACs, at least a portion of the qubit control circuit <NUM> can be replaced with control electronics that are capable of generating a wide range of qubit control signals (e.g., qubit XY control signals), use a lower bit resolution, require a lower data rate, and consume less power. Moreover, the integrated circuit can be operated at cryogenic temperatures (e.g., at or below <NUM>-<NUM>, such as <NUM>-<NUM>). Accordingly, the co-axial cables that typically couple the control electronics to the qubit chip can be replaced with superconductor connectors that are lossless if the transition temperature of the superconductor is above the operating cryogenic temperature, further reducing the power consumption of the quantum computing system.

<FIG> is a schematic that illustrates an example of a simplified qubit control circuit <NUM> for generating a qubit control signal, such as a qubit XY control signal, which does not fall within the scope of the claims. The qubit control circuit <NUM> can be used in place of at least a portion of the qubit control circuit <NUM> shown in <FIG>. In some implementations, the qubit control circuit <NUM> can be implemented as an IC, which includes a set of electronic circuits integrated as part of a piece of semiconductor material. In some implementations, the qubit control circuit <NUM> is operated at cryogenic temperatures (e.g., at or below <NUM>-<NUM>, such as <NUM>-<NUM>) instead of at room temperature like the qubit control circuit <NUM> shown in <FIG>.

The qubit control circuit <NUM> includes a signal envelope generator circuit <NUM> coupled to a mixer circuit <NUM>. As shown in the example of <FIG>, the signal envelope generator circuit <NUM> may include a current-mode envelope generator. The current-mode envelope generator includes multiple different current sources <NUM>. Although eleven current sources <NUM> are shown in <FIG> (with the dotted lines representative of current sources that are not depicted), at least two current sources may be used. The current sources <NUM> may be programmable such that each current source <NUM> can be controlled to output a defined current level. In some implementations, the waveforms for each current source <NUM> are stored in memory of the qubit control circuit <NUM>. The multiple current sources <NUM> are coupled in parallel, such that the output of each of the current sources <NUM> is tied to a common output or node <NUM>. When one or more of the current sources <NUM> are activated, the total current output measured at node <NUM> is provided as i(t). A switch <NUM> is provided in series with each current source <NUM>. The switch <NUM> for each source may be opened or closed to allow the output of the current source to be added or removed from the total current output i(t). Although a switch <NUM> is shown in <FIG> as being used to control whether the output of a current source is combined to the total current output, other control mechanisms can be used instead. Furthermore, although the signal envelope generator <NUM> is shown in <FIG> as using multiple programmable current sources, other signal sources may be used instead. For example, multiple programmable voltage sources may be used in place of current sources. Other circuit elements of the qubit control circuit <NUM> may be modified accordingly for use with the programmable voltage sources. For instance, voltage sources may combined in series.

In some implementations, the output of the signal envelope circuit is smoothed before being coupled to the mixer circuit <NUM>. For example, smoothing may be achieved by using a variable capacitor <NUM> placed across the positive and negative output of the signal envelope generator circuit <NUM>. The voltage across the capacitor <NUM> is provided as venv(t). An example of the envelope signal venv(t) is shown in plot <NUM> above circuit <NUM>.

The smoothed output of the signal envelope circuit is coupled to the mixer circuit <NUM>. In some implementations, the mixer circuit <NUM> mixes the output from the signal envelope generator circuit with a local oscillator signal <NUM>. The local oscillator signal <NUM> is at a carrier frequency. As shown in <FIG>, the mixer circuit <NUM> includes a current-mode double balanced mixer circuit. The double balanced mixer circuit provides frequency upconversion of the signal received from the envelope signal generator circuit <NUM>. In the present example, the double balanced mixer is constructed using CMOS integrated circuits <NUM>, such as MOSFETs. The mixer design shown in <FIG> is only one example and does not limit the use of other mixer circuit designs. The output of the mixer circuit <NUM> is coupled to a transformer <NUM> and provided to a load <NUM> as an output signal vout(t).

The signal envelope generator circuit <NUM> can be used to produce various different waveforms, including, but not limited to, symmetric waveforms such as Gaussian and raised cosine waveforms commonly used in quantum computing. In an example signal envelope generation process shown in <FIG>, each of the current sources <NUM> is sequentially activated, such that the total current output i(t) steadily increases to a maximum once all the current sources <NUM> are activated. For instance, a first current source having an output current value of I<NUM>(t) is activated at a first time t<NUM>, whereas a second current source having an output current value of I<NUM>(t) is activated at a second time t<NUM> that is later than t<NUM>, but while the first current source is still active such that the total current output i(t) is the sum of I<NUM>(t) and I<NUM>(t). The current activation continues in that manner until a last current source having an output current value of IN(t) is activated at a time tN, such that the total current output i(t) is the sum of all activated current sources. In this simplified example, once all current sources have been activated, they may be deactivated in the reverse order from which they were turned on. The total current output exhibits a staircase-like profile as shown in <FIG>. As explained herein, the output from the signal envelope generator circuit <NUM> may be smoothed. Smoothing can be achieved, e.g., using a variable capacitor, such as capacitor <NUM>, though other smoothing techniques may be used instead. In some implementations, the timing for which current sources <NUM> are activated and turned off is based on a number of clock cycles that have elapsed. For instance, in some cases, the shortest activation time for a current source <NUM> may be one clock cycle.

Although the qubit control circuit <NUM> shown in <FIG> includes one signal envelope generator circuit <NUM> coupled to one mixer circuit <NUM>, in general, a qubit control circuit <NUM> may include a second identical signal envelope generator circuit coupled to a second mixer circuit. For example, the first and second mixer circuits may be a part of a vector modulator circuit. The outputs of each mixer circuit then may be combined to provide the phase rotation signal. As discussed above, the axis and angle of rotation of the qubit state in the Bloch sphere are determined by the carrier phase and integrated envelope amplitude of the microwave signal, respectively. A simplified schematic of a qubit control circuit illustrating this arrangement is shown in <FIG>. The qubit control circuit <NUM> may be used in place of at least a part of the control circuit <NUM> shown in <FIG>. As with circuit <NUM>, qubit control circuit <NUM> may be implemented as an IC and operated at cryogenic temperatures (e.g., at <NUM>-<NUM>).

Qubit control circuit <NUM> includes a first signal envelope generator circuit <NUM> and a second signal envelope generator circuit <NUM>. Each of first signal envelope generator circuit <NUM> and second signal envelope generator circuit <NUM> may be constructed in the same manner as described herein for circuit <NUM>. For instance, each of circuit <NUM> and <NUM> may include multiple individual programmable current sources that are tied to a common output or node so as to provide a cumulative current output. Moreover, each of circuit <NUM> and <NUM> may include a corresponding smoothing circuit coupled to the respective common node to smooth out the staircase-like appearance of the signal output. Signal envelope generator circuit <NUM> provides a first output, e.g., DAC_I vout(t), whereas signal envelope generator circuit <NUM> provides a second output, e.g., DAC_Q vout(t).

Qubit control circuit <NUM> also includes a first mixer circuit <NUM> and a second mixer circuit <NUM>. In some implementations, the mixer circuits <NUM> and <NUM> are a part of a vector modulator circuit, which includes two mixer circuits and a combiner circuit, where the first and second mixers are driven by sine and cosine waves, respectively. Each of mixer circuits <NUM>, <NUM> may be constructed as described herein with respect to mixer circuit <NUM>. The first mixer circuit <NUM> receives the first output DAC_I vout(t) from circuit <NUM> as an input, whereas the second mixer circuit <NUM> receives DAC_Q vout(t) from circuit <NUM> as an input. In addition, each mixer circuit <NUM>, <NUM> receives a corresponding local oscillator signal. For example, circuit <NUM> receives a local oscillator signal from oscillator <NUM>, whereas circuit <NUM> receives a local oscillator signal from oscillator <NUM>. In some implementations, the local oscillators <NUM>, <NUM> include arbitrary waveform generators that are operated at room temperature and are not a part of the qubit control circuit <NUM>. For example, the local oscillators <NUM>, <NUM> may be a part of the qubit control circuit <NUM> shown in <FIG>. In other implementations, the local oscillators <NUM>, <NUM> are formed as part of the qubit control circuit <NUM>. In some implementations, the local oscillators <NUM>, <NUM> provide a periodic waveform, such as a sine or cosine waveform. In some implementations, the first oscillator <NUM> provides an output signal that is out of phase with the output signal provided by the second oscillator <NUM>. For example, the output signal from the first oscillator <NUM> may be <NUM>°, <NUM>°, or <NUM>° out of phase with the output signal provided by the second oscillator <NUM>. For example, the output signal from the first oscillator <NUM> may be a sine wave, whereas the output signal from the second oscillator <NUM> may be a cosine wave. In some implementations, the oscillator signals are amplified before being passed to the mixer. For example, qubit control circuit <NUM> includes a first amplifier <NUM> to amplify the signal from the first oscillator <NUM>, and includes a second amplifier <NUM> to amplify the signal from the second oscillator <NUM>.

The first mixer <NUM> mixes the first oscillator output with the first output DAC_I vout(t) from circuit <NUM>, whereas the second mixer <NUM> mixes the second oscillator output with the second output DAC_Q vout(t) from circuit <NUM>. The outputs of each of the first mixer <NUM> and the second mixer <NUM> then are added at an adder circuit <NUM> to provide a qubit XY drive signal in the form of an RF output.

<FIG> is a schematic that illustrates an example of qubit control circuit, such as qubit control circuit <NUM>, implemented in an integrated circuit <NUM>. The IC <NUM> may be fabricated using CMOS fabrication techniques. As shown in the example of <FIG>, the integrated circuit <NUM> includes a serial-to-parallel interface (SPI) circuit <NUM> and a configuration/waveform memory <NUM>. Memory <NUM> can include, e.g., flip-flop based memory or random access memory, among others. During operation of the integrated circuit <NUM>, waveform data is loaded into the SPI circuit <NUM> and then transferred to parallel registers in the waveform memory <NUM>. Memory <NUM> allows for multiple different waveforms to be stored, including the individual weightings for each programmable signal source of the signal envelope generators, as well as the weighting for one or more separate reference signal (e.g., current or voltage). The weightings represent magnitudes of currents required for generating a waveform. For example, weightings <NUM> for a first current source are shown in <FIG> as "I1A, I1B. I1N" in memory <NUM>. In some implementations, the memory <NUM> stores <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> different waveforms for each programmable signal source, although other numbers of waveforms can be stored. The waveforms can have different bit depths. For instance, the waveforms can be programmed to have <NUM>-bits of resolution, <NUM>-bits of resolution, <NUM>-bits of resolution or <NUM>-bits of resolution, though other resolutions are possible as well. Waveform data is provided to the DIN pin of the IC <NUM>. In some implementations, at each cycle of a clock signal provided to SCLK, data may be transferred into the SPI circuit <NUM>. Data may be transferred from the SPI circuit <NUM> to the parallel registers in memory <NUM> upon receiving a load signal at the data load pin LD. The SPI circuit <NUM> itself is updated relatively slowly. For instance, the SPI circuit <NUM> may be updated according to a clock cycle having a frequency of several kHz. Both the clock signal at SCLK and the data load signal may be provided by room temperature control electronics. Alternatively, in some implementations, the clock and load signals may be generated on the IC <NUM> itself. In some implementations, there may be an on-chip sequencer to define a series of waveform select signals corresponding to a series of waveforms.

The IC <NUM> also includes a multiplexer array <NUM>, which includes multiple multiplexers <NUM>. In the present example, each multiplexer <NUM> is a <NUM>:<NUM> multiplexer, though other multiplexer configurations including, but not limited to, <NUM>:<NUM>, <NUM>:<NUM>, or <NUM>:<NUM> may be used instead. Waveforms from memory <NUM> are loaded into multiplexers <NUM> of a multiplexer. Thus, for instance, in the example of <FIG>, each multiplexer may receive from memory <NUM> sixteen different waveforms, from which one is selected based on the waveform select signal received at the WFM input to the IC <NUM>. In the present example, the waveform select signal is a <NUM>-bit signal, allowing selection of up to <NUM> different waveforms from each multiplexer <NUM>. The waveform select signal may be generated using room temperature control electronics or on the IC <NUM> itself. In some implementations, the waveform select signal may be generated using an on-chip sequencer.

The output waveform from each multiplexer <NUM> is coupled to a corresponding programmable signal source. Half of the mux outputs are provided to programmable signal sources in the first signal envelope generator <NUM>, whereas the other half of the mux outputs are provided to programmable signal sources in the second signal envelope generator <NUM>. Thus, if each signal envelope generator includes <NUM> programmable signal sources (e.g., <NUM> programmable current sources), then <NUM> multiplexers <NUM> are provided overall, with half coupling to corresponding programmable signal sources in generator <NUM>, and the other half coupling to corresponding programmable signal sources in generator <NUM>.

A more detailed schematic of one of the signal envelope generator circuits <NUM>, <NUM> is provided in <FIG>. Each signal envelope generator <NUM>, <NUM> receives a clock signal from the clock pin CLK, and a trigger signal from the trigger pin TRIG. The trigger and clock signals are used to cycle through activation of the programmable signal sources, as described herein with respect <FIG>. Trigger and clock signals may be provided by room temperature arbitrary waveform generators or may be generated from a source on the IC <NUM>. The outputs of first signal envelope generator circuit <NUM> and second signal envelope generator circuit <NUM> are passed to a vector modulator <NUM>. A more detailed schematic of the vector modulator <NUM> is provided in <FIG>. Vector modulator <NUM> includes a first mixer <NUM> and a second mixer <NUM>, each of which receives a corresponding signal from one of the two signal envelope generator circuits <NUM>, <NUM>. First mixer <NUM> also receives a first local oscillator signal provided at oscillator pin LO_I, whereas second mixer <NUM> receives a second local oscillator signal provided at oscillator pin LO_Q. Amplifiers <NUM> and <NUM> may be provided for amplifying the received oscillator signals. The vector modulator <NUM> also includes a summer circuit <NUM> for summing the outputs of first mixer <NUM> and second mixer <NUM>. The output from summer circuit <NUM> is provided to the RF output pin RF_OUT.

Referring to <FIG>, signal envelope generator circuit <NUM> includes multiple independent <NUM>-bit digital-to-analog converters (DACs) <NUM>. In the particular example shown in <FIG>, <FIG> DACs <NUM> are provided, though other numbers DACs may be used instead. For example, the signal envelope generator circuit <NUM> may include, but is not limited to, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> DACs. Moreover, the DACs may be configured to have different bit resolution. For example, the DACs <NUM> may include, but are not limited to, <NUM>-bit, <NUM>-bit, <NUM>-bit or <NUM>-bit DACs. Though the DACs are shown as current mode, voltage-mode DACs may be used instead. The output of each DAC <NUM> is coupled to a common node <NUM> so that the total current output of signal envelope generator circuit <NUM> corresponds to the sum of the current provided by each DAC <NUM>. The total current may be converted to a voltage signal by providing a load <NUM> (e.g., a resistor) tied to the common node. In some implementations, the combined output signal may be smoothed by providing a capacitor, such as variable capacitor <NUM>, in parallel with the load <NUM>.

Each DAC <NUM> receives weightings for generating a waveform from a corresponding multiplexer <NUM>. In the present example, the weightings are provided with <NUM>-bit resolution, allowing <NUM> different current values to be generated by the DAC <NUM>. The current weightings are passed to the multiplexers <NUM> from the waveform memory <NUM>, which encompasses both the SPI interface circuit <NUM> and the waveform memory circuit <NUM> shown in <FIG>. Waveform memory <NUM> also may store weightings for a reference DAC <NUM>. Reference DAC <NUM> generates a reference current IN that is input to each of the DACs <NUM>. Current IP is a reference current for the reference current IN since current is mirrored. Similar to DACs <NUM>, DAC <NUM> receives the current weightings from a corresponding multiplexer <NUM> that is coupled to the waveform memory <NUM>. The bit-resolution of the waveform provided to the multiplexer coupled to reference DAC <NUM> may be the same or different as the bit resolution provided to the other multiplexers. A select signal (SEL) received at the IC tied to each multiplexer <NUM>, thus allowing selection of one of the different waveform weightings input into each multiplexer <NUM>.

A delay circuit <NUM> is coupled to the DACs <NUM> and allows the DACs to be activated sequentially. In the present example, the delay circuit <NUM> is configured so that the DACs produce a symmetric envelope. In particular, the exemplary delay circuit <NUM> includes a latch RS flip-flop <NUM>, multiple D-type flip-flops <NUM> and logic gates (e.g., AND gates, OR gates, NOT gates, among others) configured to sequentially activate each DAC <NUM> and, after all DACs <NUM> have been activated, to sequentially deactivate each DAC <NUM> in the reverse order from which they were activated. For instance, upon receiving a trigger signal at TRIG, each of the DACs <NUM> will be sequentially activated upon each clock cycle of the clock signal provided at CLK until all DACs <NUM> are activated. Activation of a DAC <NUM> causes the DAC <NUM> to output current at the magnitude specified by the weighting received at the DAC <NUM> from the multiplexer to which the DAC <NUM> is coupled. Following activation of all DACs <NUM>, the latch <NUM> is updated such that each DAC <NUM> is sequentially deactivated. Deactivation causes the DAC <NUM> to cease current output. The width of the combined current pulse produced by the DACs <NUM> is a function of the number of DACs used in the present configuration. For instance, in the present example, there are <NUM> different DACs <NUM>, such that the width of the entire combined current pulse produced by sequential activation and deactivation is <NUM> clock cycles, with the shortest width of an individual current pulse provided by a single DAC being <NUM> clock cycle. The configuration shown in <FIG> is one example of a delay circuit utilizing flip-flops and logic gates, though other delay circuit configurations using flip-flops and/or logic gates are also possible. While the delay circuit <NUM> is configured to provide sequential activation and deactivation of the DACs, other DAC activation and deactivation sequences may be used instead. Additionally, in some implementations, the activation and/or deactivation sequence may be stored in memory rather than determined based on the clock signal. For instance, the IC <NUM> may include a series of different waveforms pre-stored in memory on the chip <NUM>. The circuit <NUM> also may include a shift register coupled to the select lines to dial in a sequence of waveforms to the DACs <NUM>. The different waveforms may be combined in different sequences depending on the select sequence chosen.

In some implementations, there is a provision such that the combined current signal from the DACs <NUM> can have its polarity flipped before being passed to the mixer circuit. To cover all four quadrants of an arbitrary carrier phase, the magnitude of each signal from each signal envelope generator circuit should include both a positive and negative wave. In the present example, the polarity flip is achieved using a polarity switch circuit that includes MOSFETs <NUM>. A first pair of the MOSFETs <NUM> have their sources (or drains) coupled to a common input that receives the combined current output from the DACs <NUM>, whereas the other pair of MOSFETS have their sources (or drains) coupled to a common ground. The gate of one of the MOSFETs <NUM> in the first pair is controlled by a first control signal (POL+) and the gate of the other one of the MOSFETs <NUM> in the first pair is controlled by the complement of the first control signal (POL-). The same configuration is applied to the second pair of MOSFETs <NUM>. The polarity switch thus provides a positive envelope wave (ENV+) and a negative envelope wave (ENV-). Other circuit designs are also possible for achieving the polarity flip. In some implementations, differential current may be used instead to provide the positive and negative waves, eliminating the use of the polarity switch circuitry altogether.

<FIG> is a schematic that illustrates a more detailed configuration of an exemplary vector modulator circuit (e.g., such as vector modulator <NUM> in <FIG>). The positive and negative waveforms (also referred to as baseband currents) provided by each signal envelope generator circuit are upconverted using pair of double-balanced passive mixers: first mixer 708a and second mixer 708b, whose differential outputs are transformer-coupled using transformers 710a, 710b and combined into a single-ended signal RF_OUT in the current domain. Variable capacitor <NUM> allows the center frequency of the transformer to be tuned. In some implementations, an additional DAC may be employed to provide a persistent current to the baseband input of each mixer so as to permit cancellation of LO leakage.

The local oscillator port (LO_I or LO_Q) of each mixer is driven by amplifier chain that provides a tradeoff between power consumption and frequency coverage. Each local oscillator signal is converted from single-ended to differential through a corresponding transformer-based balun (balun 704a and balun 704b) followed by a fully differential gain amplifier (amplifier 706a and amplifier 706b), which serves the purpose of improving common-mode rejection. The differential signals are then amplified using digital blocks 708a, 708b that includes a series of digital gates (e.g., NOT gates and NOR gates), such that the mixer LO ports are driven rail-to-rail. The NOR gate configuration that receives the enable signal ENB prevents more than one signal from being high at the same time. To accommodate the octave bandwidth of operation, tuning capacitors <NUM> may be incorporated on the local oscillator signal input side of each transformer.

A block diagram of an exemplary test setup <NUM> in which the IC <NUM> is used in place of at least a portion of the control electronics <NUM> from <FIG> is shown in <FIG>. As shown in <FIG>, the IC <NUM> is located in an intermediate cooling stage <NUM> of a dilution refrigerator/cryostat. For instance, the IC <NUM> may be located in the <NUM> intermediate cooling stage. Alternatively, the IC <NUM> may be positioned in other intermediate cooling stages of the dilution refrigerator/cryostat. Certain control signals and waveforms provided to the IC <NUM> may be generated at the room temperature stage <NUM>. For example, in some implementations, the data for the SPI interface, the select (SEL) control signal, the trigger (TRIG) control signal, the clock (CLK) signal, and the local oscillator (LO) signal are generated at the room temperature stage <NUM> from control electronics <NUM>. The control electronics <NUM> may include multiple different arbitrary waveform generators for generating one or more signals. The control electronics <NUM> may also generate the Z-drive control signal as well as the readout control signal for driving qubit readout operations. As explained herein, in some implementations, one or more of the signals provided to the IC <NUM> may instead be generated on the IC <NUM>. The IC <NUM> is coupled to the qubit chip <NUM>, which is located in the main cooling stage <NUM> of the dilution refrigerator/cryostat. Each output of the IC <NUM> may be coupled to a different corresponding qubit XY drive line on the qubit chip <NUM>. In some implementations, various attenuators and filters may be provided on the output lines of the IC <NUM> to remove noise and to match the power requirements of the qubits.

In some implementations, the LO signal also is split off to drive an auxiliary path that, after passing through amplitude and phase control units, is weakly coupled to the XY signal path following a <NUM> dB attenuator at the output of the IC <NUM>, allowing for signal leakage to be nulled-out. A secondary use for this auxiliary path permits the qubit XY line to be driven using a room temperature arbitrary waveform generator. In some implementations, a second directional coupler is employed to monitor the RF signal (PULSE MON) propagating down to the qubit chip.

<FIG> is a plot that illustrates an example waveform obtained by a test IC having the same configuration as IC <NUM> shown in <FIG> as well as the signal envelope generator circuit configuration and the vector modulator circuit configuration shown in <FIG>. Waveform <NUM> corresponds to the trigger signal provided to the IC <NUM> that initiates activation of the DACs (e.g., DACs <NUM>). Waveform <NUM> had a frequency period of approximately <NUM> ns. Waveform <NUM> corresponds to the RF output obtained from the IC for a carrier frequency of <NUM>. For this measurement, the IC was initialized to output a series of sixteen different waveforms and the control lines were driven to step through all sixteen of the states. The chip was found to be operational for LO frequencies and clock frequencies exceeding the range of <NUM>-<NUM> and <NUM>-<NUM>, respectively. At a frequency of <NUM>, the minimum power required to drive the LO port, referenced to the input of the quadrature hybrid, was below -<NUM> dBm. The minimum power required to drive the clock port, referenced to the output of the signal generator, was found to be below -<NUM> dBm.

After completion of room temperature measurements, the system was cooled down using the test setup <NUM> shown in <FIG>. The qubit used in the quantum chip was a frequency tunable transmon qubit. After determining the qubit frequency tuning curves and nominal readout parameters using a standard bringup routine, the qubit was tuned to <NUM> and nominal values for the room temperature attenuator and phase shifter were determined such that |<NUM>〉 state occupation was minimized in the absence of an intentional XY drive. Next, a pair of Rabi experiments were carried out using the CMOS integrated circuit. For these experiments-shown in <FIG>-the state probabilities were measured as a function of pulse amplitude when the qubit had been initialized and then driven by either one or two pulses of varying amplitude but a fixed duration of <NUM> ns, corresponding to a <NUM> clock. These measurements were carried out with the weightings of a single quadrature set to produce a nominally raised cosine envelope and the other set of envelope weightings nulled. The amplitude was varied by sweeping through all <NUM> states of the DAC reference current (IN). Sweeps were repeated at a total of eleven different values of IP. At each point, <NUM>,<NUM> measurements were made to compute the state probabilities. While the state-probabilities would nominally be plotted against the envelope amplitude predicted based upon the digital setting, it was found that the DACs producing IN were both non-linear and non-monotonic at cryogenic temperatures. As such, a calibration was carried out in which the chip was triggered at <NUM> and the integrated power in a <NUM> band centered around <NUM> at the output of the monitor port was measured using a spectrum analyzer to estimate the relative pulse amplitude. The results plotted in <FIG> illustrate the anticipated behavior, and the maxima of the |<NUM>〉 and |<NUM>〉 state probabilities are consistent with expectation given the measured readout error rates of <NUM>% and <NUM>% for the |<NUM>〉 and |<NUM>〉 states, respectively.

The power draw was also measured for each configuration of the Rabi sweep with the chip configured to output pulses continuously. The maximum power consumption was then conservatively estimated as that required to produce a continuous stream of π-pulses. Using this procedure an upper limit on the DC power consumption was estimated to be <NUM> mW from the room temperature <NUM> V supply (due to IR drops along the resistive cryogenic wiring, it is estimated that the supplied voltage at the reference plane of the IC was approximately <NUM> mV).

The feasibility of using the fast-switching and phase-control features of the IC to carry out coherent control of the qubit state was evaluated through an experiment based on three pulses, the protocol of which included (<NUM>) initializing the qubit to the |<NUM>〉 state, (<NUM>) applying an X-pulse to produce a rotation of θA degrees about the X-axis, (<NUM>) applying a π-pulse with carrier phase φB to produce a rotation of πdegrees about a vector at an angle of φB from the x-axis in the XY plane, (<NUM>) applying a second X-pulse to produce a rotation of θA degrees about the X-axis, and (<NUM>) reading out the qubit state (see <FIG>). This sequence was carried out over a two dimensional sweep for φB in (<NUM>, 2π) and of pulse amplitudes AA such that θA was estimated to be in the range of <NUM> to π Prior to carrying out this measurement, optimum configuration parameters required to produce a π-pulse were determined as a function of the nominal value of φB, based on digital settings. The results appear in <FIG> along with baseline measurements taken using standard qubit control electronics. The RMS error between the two is <NUM>% and could be improved by further calibration of the CMOS pulse generator. A comparison of the performance of the proposed cryogenic control IC to that of a standard room temperature control system is provided in <FIG>.

<FIG> is a block diagram illustrating an exemplary process <NUM> for generating a qubit XY control signal. The process <NUM> may be performed using the qubit control circuits described herein, such as IC <NUM>. In a first step <NUM>, a first multiple of signal sources are sequentially activated. The signal sources may include current sources or voltage sources as described herein. The output of each signal source is combined (<NUM>) to provide a first combined output. The first combined output is passed (<NUM>) to a first mixer circuit, such as any of the mixer circuits described herein (e.g., mixer circuit <NUM>). The mixer circuit mixes (<NUM>) the first combined output with a local oscillator signal to provide a first qubit control signal. As explained herein, the signal sources may include programmable current sources. The process <NUM> also may include sequentially deactivating the first multiple of signal sources. The first combined output also may include a combined output of the sequentially deactivated first multiple of signal sources. The process <NUM> also may include smoothing the first combined output prior to passing the first combined output to a first mixer. The process <NUM> also may include: sequentially activating a second multiple of signal sources; combining an output of the sequentially activated second multiple of signal sources to provide a second combined output; passing the second combined output to a second mixer circuit; mixing the second combined output with a second local oscillator signal in the second mixer circuit to provide a second qubit control signal; and combining the first qubit control signal with the second qubit control signal to provide a qubit XY control signal. The qubit XY control signal then may be coupled to a qubit on a qubit chip, such as chip <NUM> or chip <NUM>. The first local oscillator signal may be out of phase with the second local oscillator signal. For example, the first oscillator signal may be a sine wave, whereas the second local oscillator signal may be a cosine wave. The process <NUM> may be performed at a temperature of above <NUM> mK (e.g., above <NUM> mK) and below <NUM>.

The discussion of the exemplary control circuit presented herein pertains to using the integrated circuit to implement single qubit gates. However, the control circuit may also be used to implement multiple qubit gates.

Implementations of the quantum subject matter and quantum operations described in this specification can be implemented in suitable quantum circuitry or, more generally, quantum computational systems, also referred to as quantum information processing systems, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The terms "quantum computational systems" and "quantum information processing systems" may include, but are not limited to, quantum computers, quantum cryptography systems, topological quantum computers, or quantum simulators.

The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, e.g., a system that defines the unit of quantum information. In some implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states are possible. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, the quantum circuit elements are configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. Certain quantum circuit elements, such as qubits, can be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), among others.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to transmit data to and/or receive data from the quantum circuit elements through electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuitry, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors.

Fabrication of the quantum circuit elements and classical circuit elements described herein can entail the deposition of one or more materials, such as superconductors, dielectrics and/or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. Processes for fabricating circuit elements described herein can entail the removal of one or more materials from a device during fabrication. Depending on the material to be removed, the removal process can include, e.g., wet etching techniques, dry etching techniques, or lift-off processes. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (e.g., photolithography or e-beam lithography).

During operation of a quantum computational system that uses superconducting quantum circuit elements and/or superconducting classical circuit elements, such as the circuit elements described herein, the superconducting circuit elements are cooled down within a cryostat to temperatures that allow a superconductor material to exhibit superconducting properties. A superconductor (alternatively superconducting) material can be understood as material that exhibits superconducting properties at or below a superconducting critical temperature. Examples of superconducting material include aluminum (superconductive critical temperature of about <NUM> kelvin), indium (superconducting critical temperature of about <NUM> kelvin), NbTi (superconducting critical temperature of about <NUM> kelvin) and niobium (superconducting critical temperature of about <NUM> kelvin). Accordingly, superconducting structures, such as superconducting traces and superconducting ground planes, are formed from material that exhibits superconducting properties at or below a superconducting critical temperature.

Claim 1:
A device for generating a qubit control signal, wherein the device is operable at cryogenic temperatures, the device comprising:
a first signal envelope generator circuit (<NUM>, <NUM>) comprising a first plurality of signal sources (<NUM>), wherein an output of each signal source of the first plurality of signal sources is combined to provide a first cumulative output;
a first mixer circuit (<NUM>, <NUM>) coupled to the first signal envelope generator circuit for up-conversion of the first cumulative output, wherein the first cumulative output is coupled to a first input of the first mixer circuit, an output of the first mixer circuit comprises a first qubit control signal, and the first mixer circuit is configured to mix the first cumulative output with a first local oscillator signal (<NUM>) received at a second input of the first mixer circuit;
a second signal envelope generator circuit (<NUM>) comprising a second plurality of signal sources, wherein an output of each signal source of the second plurality of signal sources is combined to provide a second cumulative output; and
a second mixer circuit (<NUM>) coupled to the second signal envelope generator for up-conversion of the second cumulative output, wherein the second cumulative output is coupled to a first input of the second mixer circuit, an output of the second mixer circuit comprises a second qubit control signal, and the second mixer circuit is configured to mix the second cumulative output with a second local oscillator signal received at a second input of the second mixer circuit, and the first qubit control signal is combined with the second qubit control signal to provide a qubit XY control signal, wherein the first local oscillator signal is out of phase with the second local oscillator signal.