Patent Description:
A storage system generally includes a host and a storage device. The host and the storage device may be connected to each other through a variety of standard interfaces such as universal flash storage (UFS), serial ATA (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), and embedded multi-media card (eMMC). When the storage system is used in a mobile device, a high-speed operation between the host and the storage device may be desired, and because the space for a write buffer in the storage device is limited, it may be beneficial to efficiently use a memory buffer in the host.

<CIT> discloses an input/output (I/O) interceptor logic section having an I/O interface coupled with a storage stack. The I/O interface may intercept write I/Os, read I/Os, and flush requests from an application. Write holding buffers associated with different kinds of non-volatile storage devices may store the write I/Os. A re-order logic section may change an order of the write I/Os, and combine the reordered write I/Os into a combined write I/O. A dynamic heterogeneous flush control logic section may receive the flush requests from the I/O interface, communicate write I/O completion of the write I/Os to the application without write I/Os being committed to the non-volatile storage devices, and cause the combined write I/O to be written to the non-volatile storage device responsive to a dynamic flush threshold, a threshold amount of data being accumulated, or an expiration of a predefined time period.

<CIT> discloses: A method of programming data to a storage device including a nonvolatile memory device includes receiving first to third barrier commands from a host, receiving first to third data corresponding to the first to third barrier commands from the host, merging the first and second barrier commands and programming the first and second data to the nonvolatile memory device sequentially based on an order of the first and second barrier commands, verifying program completion of both the first and second data, mapping in mapping information of the first and second data when the programming of the first and second data is completed, and mapping out the information of both the first and second data when the programming of at least one of the first and second data is not complete, and programming the third data to the nonvolatile memory device after the mapping in or the mapping out.

<CIT> discloses: A memory system includes a nonvolatile memory device including a plurality of planes; and a controller suitable for determining whether a first read operation for the nonvolatile memory device is a random read operation, and accessing at least one first target plane of the first read operation, according to an access merge process, depending on a determination result, wherein the controller simultaneously accesses the first target plane and at least one second target plane included in the nonvolatile memory device, according to the access merge process.

Embodiments of the present disclosure are defined in the appended claims.

The present disclosure provides a storage system in which write performance is improved by generating a write buffer in a host in consideration of characteristics of a storage device, merging write commands and transmitting a merged write command to the storage device.

Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:.

<FIG> illustrates a storage system <NUM> according to an embodiment of the present disclosure.

Referring to <FIG>, the storage system <NUM> may include a host <NUM> and a storage device <NUM>. The host <NUM> and the storage device <NUM> may be connected to each other according to an interface protocol defined in a universal flash storage (UFS) specification, and accordingly, the storage device <NUM> may be a UFS storage device and the host <NUM> may be a UFS host. However, the present disclosure is not limited thereto, and the storage device <NUM> and the host <NUM> may be connected to each other according to various standard interfaces.

The host <NUM> may control a data processing operation for the storage device <NUM>, such as, for example, a data read operation or a data write operation. The host <NUM> may refer to a data processing device capable of processing data, such as a central processing unit (CPU), a processor, a microprocessor, or an application processor (AP). The host <NUM> may execute an operating system (OS) and/or various applications. In an embodiment, the storage system <NUM> may be included in a mobile device, and the host <NUM> may be implemented as an application processor (AP). In an embodiment, the host <NUM> may be implemented as a system-on-a-chip (SoC), and thus may be embedded in an electronic device.

In the present embodiment, a plurality of conceptual hardware configurations, which are included in the host <NUM> and the storage device <NUM>, are illustrated. However, the present disclosure is not limited thereto and other configurations may be made. The host <NUM> may include an interconnect portion <NUM>, which is a host interface, a host controller <NUM>, and a host write buffer <NUM>. The interconnect portion <NUM> may provide an interface <NUM> between the host <NUM> and the storage device <NUM>. The interconnect portion <NUM> may include a physical layer and a link layer. The physical layer of the interconnect portion <NUM> may include physical components for exchanging data with the storage device <NUM>, and may include at least one transmitter TX and at least one receiver RX. The interconnect portion <NUM> of the host <NUM> may include, for example, four transmitters and four receivers. The link layer of the interconnect portion <NUM> may manage data transmission and/or composition, and may manage data integrity and error.

The host controller <NUM> may receive information about the storage device <NUM> from the storage device <NUM> to generate the host write buffer <NUM>. The host controller <NUM> may store a plurality of write commands in the host write buffer <NUM> to generate a merged write command by merging a plurality of write commands generated by the host <NUM>.

The host write buffer <NUM> may be a portion of memory allocated by the host <NUM> for the storage device <NUM>. The host write buffer <NUM> may be generated in a block layer of the host <NUM> or a device driver. The host write buffer <NUM> may receive write input/output (I/O) information optimized for a non-volatile memory <NUM> in an initialization process between the host <NUM> and the storage device <NUM>, and may be statically allocated and operated.

The storage device <NUM> may include an interconnect portion <NUM>, which is a device interface, a storage controller <NUM>, and the non-volatile memory <NUM>. The storage controller <NUM> may control the non-volatile memory <NUM> to write data to the non-volatile memory <NUM> in response to a write request from the host <NUM>, or may control the nonvolatile memory <NUM> to read data stored in the non-volatile memory <NUM> in response to a read request from the host <NUM>.

The interconnect portion <NUM> may provide an interface <NUM> between the storage device <NUM> and the host <NUM>. For example, the interconnect portion <NUM> may include a physical layer and a link layer. The physical layer of the interconnect portion <NUM> may include physical components for exchanging data with the host <NUM>, and may include at least one receiver RX and at least one transmitter TX. The interconnect portion <NUM> of the storage device <NUM> may include, for example, four receivers and four transmitters. The link layer of the interconnect portion <NUM> may manage data transmission and/or combination, and may manage data integrity and errors.

In an embodiment, when the storage system <NUM> is a mobile device, the physical layers of the interconnect portions <NUM> and <NUM> may be defined by the "M-PHY" specification, and the link layers of the interconnect portions <NUM> and <NUM> may be defined by the "UniPro" specification. M-PHY and UniPro are interface protocols proposed by the mobile industry processor interface (MIPI) alliance. The link layers of the interconnect portions <NUM> and <NUM> may each include a physical adapted layer, which may control the physical layers such as managing data symbols or managing power.

The transmitter TX in the interconnect portion <NUM> of the host <NUM> and the receiver RX in the interconnect portion <NUM> of the storage device <NUM> may form one lane. In addition, the transmitter TX in the interconnect portion <NUM> of the storage device <NUM> and the receiver RX in the interconnect portion <NUM> of the host <NUM> may also form one lane.

The non-volatile memory <NUM> may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. In an embodiment, the plurality of memory cells may be NAND flash memory cells. However, the present disclosure is not limited thereto, and in another embodiment, the plurality of memory cells may be resistive memory cells such as resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

In some embodiments, the storage device <NUM> may be implemented as a DRAM-less device, which may refer to a device that does not include a DRAM cache. In this case, the storage controller <NUM> may not include a DRAM controller. For example, the storage device <NUM> may use a portion of the non-volatile memory <NUM> as a buffer memory.

In some embodiments, the storage device <NUM> may be an internal memory that is embedded in an electronic device. For example, the storage device <NUM> may include an embedded UFS memory device, an eMMC, or a solid state drive (SSD). However, the present disclosure is not limited thereto, and the storage device <NUM> may include a nonvolatile memory (e.g., one-time programmable ROM (OTPROM), programmable ROM (PROM), erasable and programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), mask ROM, flash ROM, or the like). In some embodiments, the storage device <NUM> may include an external memory that is detachable from an electronic device. For example, the storage device <NUM> may include at least one of a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro-SD card, a mini-SD card, an extreme digital (xD) card, and a memory stick.

The storage system <NUM> may be implemented as an electronic device, such as a personal computer (PC), a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), an MP3 player, a handheld game console, or an e-book. Also, the storage system <NUM> may be implemented as various types of electronic devices, such as a wrist watch or a wearable device such as a head-mounted display (HMD).

<FIG> illustrates a write command merging process in a storage system according to an embodiment of the present disclosure.

Referring to <FIG>, the storage system may include a file system (FS) <NUM>, a host write buffer (HWB) <NUM>, a data transmission manager (DTM) <NUM>, and a storage device <NUM>. For example, the storage system may include the host and the storage device of <FIG>. For example, the host <NUM> of <FIG> may include the file system <NUM>, the host write buffer <NUM>, and the data transmission manager <NUM> of <FIG>, and the storage device <NUM> of <FIG> may include the storage device <NUM> of <FIG>.

For example, when a first write command WC1 is generated by the file system <NUM> and provided by a first interface signal CI_1 and stored in the host write buffer <NUM>, the host write buffer <NUM> may transmit a first response signal CR_1 to the file system <NUM>. When the first response signal CR_1 is received, the file system <NUM> may recognize that the first write command WC1 has been successfully transmitted and generate a second write command WC2. In addition, the file system <NUM> may simultaneously generate a second write command WC2 to an N-th write command WC_N within a preset range regardless of the first response signal CR_1 during processing of the first write command WC1, and the second write command WC2 to the N-th write command WC_N may be provided by second to N-th interface signals CI_2 to CI_N and stored in the host write buffer <NUM>. For example, the preset range may be determined according to the number of host controller interface command queues supported by the storage system.

For example, the storage system may generate a first merged write command MWC1 by merging the first write command WC1 to the fourth write command WC4 based on information received from the storage device <NUM>. The data transmission manager <NUM> may receive the first merged write command MWC1 from the host write buffer <NUM> and provide a first buffer response BCR <NUM> to the host write buffer <NUM>. The storage device <NUM> may receive the first merged write command MWC1 from the data transmission manager <NUM> and provide a first merged write command response MCR <NUM> to the data transmission manager <NUM>. When the first merged write command response MCR <NUM> is received, the storage system may transmit first merge data corresponding to the first merged write command MWC1 stored in the host write buffer <NUM>. The storage system may transmit the first merge data and merge new write commands generated by the file system <NUM> of the host.

<FIG> illustrate a write command merging process in a storage system according to an embodiment of the present disclosure.

Referring to <FIG>, to efficiently merge a write command and perform merged write command processing, a host write buffer <NUM> may be a doubling buffer including a first host write buffer <NUM> and a second host write buffer <NUM>.

When a write command is generated as much as the size of the host write buffer <NUM>, one host write buffer may process the write command. However, when a write command having a size larger than that of the host write buffer <NUM> is generated, a plurality of host write buffers may be required.

In addition, when a plurality of host write buffers are allocated, the second host write buffer <NUM> may process new write commands, generated by a file system, while the first host write buffer <NUM> processes merged data. The storage system may allocate at least one host write buffer based on the information of a storage device. In the present, a case in which one or two host write buffers are allocated is described for convenience, but the number of host write buffers is limited thereto.

Referring to <FIG>, the host write buffer <NUM> may receive and store a second write command WC2, generated by the file system, while a first write command WC1 is stored. When the second write command WC2 is stored, the host write buffer <NUM> may generate a second write command response signal CR2 and transmit the second write command response signal CR2 to the file system.

For example, the second write command response signal CR2 may be configured in the same form as a response signal received when a write command is transmitted from the file system to the storage device. In this case, because the file system directly receives a response signal from the host write buffer <NUM> before transmitting write commands to the storage device, fast write processing may be performed.

Referring to <FIG>, the host write buffer <NUM> may receive and store a third write command WC3 generated by the file system, and may generate a third write command response signal CR3 and transmit the third write command response signal CR3 to the file system.

The storage system may generate a first merged write command MWC1 by merging the first write command WC1, the second write command WC2, and the third write command WC3, stored in the host write buffer <NUM>. The storage system may transmit the generated first merged write command MWC1 to the storage device through a data transmission manager.

Referring to <FIG>, the host write buffer <NUM> may include the first host write buffer <NUM> and the second host write buffer <NUM>. When the host write buffer <NUM> receives the third write command WC3 larger than a remaining space of the first host write buffer <NUM>, a third_1 write command WC3_1 may be stored in the first host write buffer <NUM> and a third_2 write command WC3_2 may be stored in the second host write buffer <NUM>. After the third write command WC3 is stored, the host write buffer <NUM> may generate a third write command response signal CR3 and transmit the third write command response signal CR3 to the file system.

The storage system may generate a first merged write command MWC1 by merging the first write command WC1, the second write command WC2, and the third_1 write command WC3_1, stored in the first host write buffer <NUM>. The storage system may transmit the generated first merged write command MWC1 to the storage device through the data transmission manager. The host write buffer <NUM> may divide and store a write command larger than a remaining space by using the first host write buffer <NUM> and the second host write buffer <NUM>.

Referring to <FIG>, the host write buffer <NUM> may store a fourth write command WC4 received from the file system in the second host write buffer <NUM> while the first host write buffer <NUM> performs a write command merge and transmits the first merged write command MWC1. The storage system may use the first host write buffer <NUM> and the second host write buffer <NUM>, and transmit the first merged write command MWC1 from the first host write buffer <NUM> and simultaneously receive other write commands from the file system through the second host write buffer <NUM> to store and merge the other write commands.

For example, when the merged write commands have consecutive logical block addresses, there is no need to operate separate metadata, but when write commands having non-consecutive logical block addresses are merged, a meta buffer <NUM> for storing metadata is used. The metadata may include a logical block address and length information of a write command. The meta buffer <NUM> may have a form corresponding to a host write buffer <NUM>.

Referring to <FIG>, the host write buffer <NUM> may receive and store a second write command WC2 generated by a file system while a first write command WC1 is stored. When the second write command WC2 is stored, the host write buffer <NUM> may generate a second write command response signal CR2 and transmit the second write command response signal CR2 to the file system.

When the first write command WC1 is received in the host write buffer <NUM>, a space for storing first metadata MT1 is allocated in the meta buffer <NUM>, and the first metadata MT1 may be stored in the allocated space. The first metadata MT1 may include a logical block address and length information of the first write command WC1. When the second write command WC2 is received in the host write buffer <NUM>, a space for storing second metadata MT2 may be allocated in the meta buffer <NUM>.

Referring to <FIG>, when a third write command WC3 is received in the host write buffer <NUM>, a space in which third metadata MT3 is stored may be allocated in the meta buffer <NUM>. When the third write command WC3 is stored, the host write buffer <NUM> may generate a third write command response signal CR3 and transmit the third write command response signal CR3 to the file system.

The storage system may generate a first merged write command MWC1 by merging the first write command WC1, the second write command WC2, and the third write command WC3, stored in the host write buffer <NUM>. The storage system may transmit the generated first merged write command MWC1 to a storage device through a data transmission manager.

Referring to <FIG>, the host write buffer <NUM> may include a first host write buffer <NUM> and a second host write buffer <NUM>. When the host write buffer <NUM> receives the third write command WC3 larger than a remaining space of the first host write buffer <NUM>, a third_1 write command WC3_1 may be stored in the first host write buffer <NUM> and a third_2 write command WC3_2 may be stored in the second host write buffer <NUM>. After the third write command WC3 is stored, the host write buffer <NUM> may generate a third write command response signal CR3 and transmit the third write command response signal CR3 to the file system.

A meta buffer may be configured to correspond to the first host write buffer <NUM> and the second host write buffer <NUM>. For example, the meta buffer may include a first meta buffer <NUM> and a second meta buffer <NUM>. The first meta buffer <NUM> may store first metadata MT1 and second metadata MT2. A third metadata may be divided and stored in the first meta buffer <NUM> and the second meta buffer <NUM> like the third write command WC3. Third_1 metadata MT3_1 may be stored in the first meta buffer <NUM>, and third_2 metadata MT3_2 may be stored in the second meta buffer <NUM>.

The storage system may generate a first merged write command MWC1 by merging the first write command WC1, the second write command WC2, and the third_1 write command WC3_1, stored in the first host write buffer <NUM>. The storage system may transmit the generated first merged write command MWC1 to the storage device through the data transmission manager. The host write buffer <NUM> may divide and store a write command larger than a remaining space by utilizing the first host write buffer <NUM> and the second host write buffer <NUM>.

While the storage system processes the first metadata MT1, the second metadata MT2, and the third metadata, stored in the first meta buffer <NUM>, the storage system may receive fourth metadata MT4 and store the fourth metadata MT4 in the second meta buffer <NUM>.

<FIG> illustrates metadata transmission according to a merged write command in a storage system according to an embodiment of the present disclosure.

When transmitting a merged write command from a host write buffer <NUM>, the storage system may provide an interface utilizing an extra header segment (EHS) to transmit metadata including a logical block address and length information. The EHS will be supported from UFS specification <NUM> and may be used when an extra header is required in addition to a command header fixed to <NUM> bytes.

The EHS may include an EHS header and meta. The EHS header has a fixed size and may provide scalability in which multiple operations may be performed. The meta may vary depending on the total number of write commands merged in the host write buffer <NUM> and the type of write command to be used (e.g., WRITE <NUM> or WRITE <NUM>). The EHS header may include fields for storing information on whether a merged write command is transmitted, the characteristics of logical block address and length information, whether meta transmission is required, a valid meta size setting, and the number of write commands merged in the host write buffer <NUM>. The meta may include a field for storing a logical block address and length information for each write command.

The storage system may merge write commands stored in the host write buffer <NUM> and transmit a first merged write command MWC1 to a storage device <NUM> through a data transmission manager <NUM>. Meta information corresponding to the first merged write command MWC1 may be transmitted to the storage device <NUM> through an EHS.

The storage system may transmit meta information by using a separate vendor command or a write buffer command of UFS instead of using an EHS. For example, meta information may be transmitted using a first write buffer command WBC1, and a first merged write command MWC1 stored in a host write buffer may be transmitted. The storage system may first transmit the meta information through the first write buffer command WBC1 before the first merged write command MWC1, and thus, validity check for the logical block address and length information may be first performed.

<FIG> illustrates an operating method of a storage system, according to an embodiment of the present disclosure.

Referring to <FIG>, a zeroth write command WC0 and a first write command WC1 may be transmitted to a storage device <NUM> through a host write buffer <NUM> and a meta buffer <NUM>. The zeroth write command WC0 and the first write command WC1 may be write commands having different sizes and addresses.

First, the zeroth write command WC0 having a logical block address of <NUM> and a length of <NUM> may be generated by a file system <NUM> and stored in the host write buffer <NUM>, and a response to the zeroth write command WC0 may be transmitted to the file system <NUM>. Zeroth meta information (a logical block address of <NUM> and a length of <NUM>) may be stored in the meta buffer <NUM> corresponding to the host write buffer <NUM>.

The storage system may store, in the host write buffer <NUM>, the first write command WC1 having a logical block address of <NUM> and a length of <NUM>. Because the size of the first write command WC1 is larger than a remaining space of a first host write buffer in the host write buffer <NUM>, the first write command WC1 may be divided into a first_1 write command WC1_1 and a first_2 write command WC1_2. First_1 meta information MT1_1 corresponding to the first_1 write command WC1_1 may include a logical block address of <NUM> and a length of <NUM>, first_2 meta information MT1_2 may include a logical block address of <NUM> and a length of <NUM>, and the first_1 meta information MT1_1 and the first_2 meta information MT1_2 may be stored separately in a meta buffer area corresponding to the host write buffer <NUM>.

A first merged write command MWC1 may be generated by merging the zeroth write command WC0 and the first_1 write command WC1_1, stored in the first host write buffer. Content stored in the meta buffer <NUM> corresponding to the first merged write command MWC1 may be transmitted through an EHS of the first merged write command MWC1.

When the first merged write command MWC1 is received, the storage device <NUM> may confirm that the first merged write command MWC1 is a command obtained by merging a plurality of write commands, through content stored in an EHS in a command parser. The storage device <NUM> may divide data corresponding to a write command in the first merged write command MWC1 and store the divided data in a non-volatile memory.

<FIG> illustrates an operating method of a storage system supporting a multi-stream, according to an embodiment of the present disclosure.

The storage system may support a multi-stream including streams obtained by dividing the same file or data having properties with similar lifespan patterns. In the storage system, a host write buffer <NUM> may be separated for each stream. A storage device <NUM> may also divide data for each stream and store divided data.

<FIG> illustrates an operating method of a storage system that does not support a multi-stream, according to an embodiment of the present disclosure.

Because a file system <NUM> generates a write command without distinguishing between a first file FILE <NUM> and a second file FILE <NUM>, the first file FILE <NUM> and the second file FILE <NUM> are stored without distinction in a storage device <NUM>.

Because a storage device <NUM> may not operate a host write buffer <NUM> for each stream due to resource limitations, a host may operate the host write buffer <NUM> for each stream and merge write data for each stream to transmit merged write data to the storage device <NUM>. In the storage system, when a write command is transmitted, write data for each stream may be managed by using a stream ID as a delimiter.

For example, a stream ID of a first write command WC1 to a fourth write command WC4 may be A, a stream ID may not be assigned to a fifth write command WC5, and a stream ID of a sixth write command WC6 may be N.

A first host write buffer <NUM> may store data having a stream ID of A, a second host write buffer <NUM> may store data to which a stream ID is not assigned, and an Nth host write buffer <NUM> may store data having a stream ID of N.

When the first write command WC1 to the storage device <NUM> indicates a fast transmission, the storage system may directly transmit data to the storage device <NUM> without going through the host write buffer <NUM>. The storage system may bypass the second write command WC2 and then store data in the host write buffer <NUM> and merge the stored data.

<FIG> illustrates an operating method of a storage system supporting a zone-based interface, according to an embodiment of the present disclosure.

A host write buffer <NUM> may be used in a zone storage system that supports a zone-based interface including zoned block commands (ZBC). For example, the zone storage system may generate the host write buffer <NUM> in a host to compensate for an insufficient buffer space in a zone storage device <NUM>.

In the zone storage system, storage (e.g., non-volatile memory) may be logically divided into zones having a certain size. When a write command is provided from a host file system <NUM> of the zone storage system to the zone storage device <NUM>, data of consecutive logical block addresses may be stored for each zone.

Write commands for consecutive logical block addresses may be generated in a zone A host file system <NUM> of the zone storage system. The generated write commands may be transmitted in reverse order by a scheduler of a block layer. In this case, the zone storage system may transmit, to the zone A storage device <NUM>, meta information on non-consecutive logical block addresses together with a merged write command, and the zone A storage device <NUM> may check the meta information and arrange data of the non-consecutive logical block addresses into consecutive logical block addresses.

The storage system may receive storage device information and generate a host write buffer (operation S510). The size of the host write buffer, may be allocated based on at least one of a program method of a storage device and a unit of interleaving processing for simultaneously processing, by several chips, a request received from a host. The host write buffer may include at least one of a first host write buffer and a second host write buffer based on an input/output scheduling method. The storage system may further include a meta-memory buffer for merging write commands for non-consecutive logical block addresses. The meta-memory buffer may be dynamically allocated according to the number of write commands merged in the host write buffer, and may store meta information including at least one of a logical block address and length information of data corresponding to each of the write commands. The storage system may generate an EHS including the meta information and transmit the generated EHS to the storage device.

The storage system may store a plurality of write commands in the host write buffer (operation S520). The storage system may generate a merged write command by merging the write commands (operation S530). The storage system may transmit the merged write command to the storage device (operation S540).

<FIG> illustrates a system <NUM> to which a storage device according to an embodiment of the present disclosure is applied. The system <NUM> of <FIG> may basically include a mobile system such as a mobile phone, a smart phone, a tablet PC, a wearable device, a healthcare device, or an Internet-of-things (IoT) device. However, the system <NUM> of <FIG> is not limited to the mobile system and may also include a PC, a laptop computer, a server, a media player, or an automotive device such as a navigation device. Hereinafter, subscripts (e.g., a in 1200a and a in 1300a) attached to reference numbers are used to distinguish a plurality of circuits having the same function.

Referring to <FIG>, the system <NUM> may include a main processor <NUM>, memories 1200a and 1200b, and storage devices 1300a and 1300b and may additionally include one or more of an image capturing device <NUM>, a user input device <NUM>, a sensor <NUM>, a communication device <NUM>, a display <NUM>, a speaker <NUM>, a power supplying device <NUM>, and a connecting interface <NUM>.

The main processor <NUM> may control overall operations of the system <NUM>, and more particularly, may control operations of other components constituting the system <NUM>. The main processor <NUM> may be implemented by a general-purpose processor, a dedicated processor, an application processor, or the like.

The main processor <NUM> may include one or more CPU cores <NUM> and may further include a controller <NUM> for controlling the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. According to embodiments, the main processor <NUM> may further include an accelerator block <NUM>, which is a dedicated circuit for high-speed data calculations such as artificial intelligence (AI) data calculations. The accelerator block <NUM> may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and may be implemented by a separate chip that is physically independent of the other components.

The memories 1200a and 1200b may be used as a main memory device and may include volatile memory such as static random access memory (SRAM) and/or dynamic random access memory (DRAM) or may include non-volatile memory such as phase change random access memory (PRAM) and/or resistive random access memory (RRAM). The memories 1200a and 1200b may also be implemented in the same package as the main processor <NUM>.

The storage devices 1300a and 1300b may function as non-volatile storage devices storing data regardless of the supply or not of power, and may have relatively larger storage capacities than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b, and non-volatile storages 1320a and 1320b storing data under the control of the storage controllers 1310a and 1310b, respectively. The non-volatile storages 1320a and 1320b may include V-NAND flash memory having a <NUM>-dimensional (2D) structure or a <NUM>-dimensioonal (3D) structure or may include another type of non-volatile memory such as PRAM and/or RRAM.

The storage devices 1300a and 1300b may be included in the system <NUM> while physically separated from the main processor <NUM> or may be implemented in the same package as the main processor <NUM>. In addition, the storage devices 1300a and 1300b may have a form such as a memory card and thus may be detachably coupled to the other components of the system <NUM> through an interface such as the connecting interface <NUM> described below. The storage devices 1300a and 1300b may include, but are not limited to, devices to which standard specifications such as UFS are applied.

The image capturing device <NUM> may capture still images or moving images and may include a camera, a camcorder, and/or a webcam.

The user input device <NUM> may receive various types of data input by a user of the system <NUM> and may include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor <NUM> may sense various physical quantities, which may be obtained from outside the system <NUM>, and may convert the sensed physical quantities into electrical signals. The sensor <NUM> may include a temperature sensor, a pressure sensor, a luminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope.

The communication device <NUM> may perform transmission and reception of signals between the system <NUM> and other devices outside the system <NUM>, according to various communication protocols. The communication device <NUM> may include an antenna, a transceiver, and/or a modem.

The display <NUM> and the speaker <NUM> may function as output devices outputting visual information and auditory information to the user of the system <NUM>, respectively.

The power supplying device <NUM> may appropriately convert power supplied by a battery (not shown) embedded in the system <NUM> and/or by an external power supply and thus supply the converted power to each of the components of the system <NUM>.

The connecting interface <NUM> may provide a connection between the system <NUM> and an external device that is connected to the system <NUM> and capable of exchanging data with the system <NUM>. The connecting interface <NUM> may be implemented by various interfaces such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), non-volatile memory express (NVMe), IEEE <NUM>, universal serial bus (USB), a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, UFS, embedded Universal Flash Storage (eUFS), and a CF card interface.

<FIG> illustrates a UFS system <NUM> according to an embodiment of the present disclosure. The UFS system <NUM>, which is a system conforming to the UFS standard announced by the Joint Electron Device Engineering Council (JEDEC), may include a UFS host <NUM>, a UFS device <NUM>, and a UFS interface <NUM>. The above descriptions of the system <NUM> of <FIG> may also be applied to the UFS system <NUM> of <FIG> unless conflicting with the following descriptions regarding <FIG>.

Referring to <FIG>, the UFS host <NUM> and the UFS device <NUM> may be connected to each other through the UFS interface <NUM>. When the main processor <NUM> of <FIG> is an application processor, the UFS host <NUM> may be implemented as a portion of a corresponding application processor. A UFS host controller <NUM> and a host memory <NUM> may respectively correspond to the controller <NUM> and the memories 1200a and 1200b of the main processor <NUM> of <FIG>. The UFS device <NUM> may correspond to the storage devices 1300a and 1300b of <FIG>, and a UFS device controller <NUM> and a non-volatile storage <NUM> may respectively correspond to the storage controllers 1310a and 1310b and the non-volatile storages 1320a and 1320b in <FIG>.

The UFS host <NUM> may include the UFS host controller <NUM>, an application <NUM>, a UFS driver <NUM>, the host memory <NUM>, and a UFS interconnect (UIC) layer <NUM>. The UFS device <NUM> may include the UFS device controller <NUM>, the nonvolatile storage <NUM>, a storage interface <NUM>, a device memory <NUM>, a UIC layer <NUM>, and a regulator <NUM>. The non-volatile storage <NUM> may include a plurality of storage units <NUM>, and each storage unit <NUM> may include V-NAND flash memory having a 2D structure or a 3D structure or may include another type of non-volatile memory such as PRAM and/or RRAM. The UFS device controller <NUM> and the nonvolatile storage <NUM> may be connected to each other through the storage interface <NUM>. The storage interface <NUM> may be implemented to conform to a standard specification such as Toggle or ONFI.

The application <NUM> may refer to a program that intends to communicate with the UFS device <NUM> to use a function of the UFS device <NUM>. The application <NUM> may transmit an input-output request to the UFS driver <NUM> to perform input to and output from the UFS device <NUM>. The input-output request may refer to, but is not limited to, a read request, a write request, and/or a discard request of data.

The UFS driver <NUM> may manage the UFS host controller <NUM> through a UFS-host controller interface (HCl). The UFS driver <NUM> may convert the input-output request generated by the application <NUM> into a UFS command defined by the UFS standard, and may transfer the converted UFS command to the UFS host controller <NUM>. One input-output request may be converted into a plurality of UFS commands. Although a UFS command may be basically a command defined by the SCSI standard, the UFS command may also be a UFS standard-dedicated command.

The UFS host controller <NUM> may transmit the UFS command converted by the UFS driver <NUM> to the UIC layer <NUM> of the UFS device <NUM> through the UIC layer <NUM> and the UFS interface <NUM>. In this process, a UFS host register <NUM> of the UFS host controller <NUM> may perform a role as a command queue.

The UIC layer <NUM> of the UFS host <NUM> may include MIPI M-PHY <NUM> and MIPI UniPro <NUM>, and the UIC layer <NUM> of the UFS device <NUM> may also include MIPI M-PHY <NUM> and MIPI UniPro <NUM>.

The UFS interface <NUM> may include a line for transmitting a reference clock signal REF_CLK, a line for transmitting a hardware reset signal RESET_n with respect to the UFS device <NUM>, a pair of lines for transmitting a differential input signal pair DIN_T and DIN_C, and a pair of lines for transmitting a differential output signal pair DOUT_T and DOUT_C.

A frequency value of the reference clock signal REF_CLK provided from the UFS host <NUM> to the UFS device <NUM> may be, but is not limited to, one of <NUM>, <NUM>, <NUM>, and <NUM>. Even while the UFS host <NUM> is being operated, that is, even while data transmission and reception between the UFS host <NUM> and the UFS device <NUM> is being performed, the frequency value of the reference clock signal REF_CLK may be changed. The UFS device <NUM> may generate clock signals having various frequencies from the reference clock signal REF_CLK received from the UFS host <NUM>, by using a phase-locked loop (PLL) or the like. In addition, the UFS host <NUM> may also set a value of a data rate between the UFS host <NUM> and the UFS device <NUM>, based on the frequency value of the reference clock signal REF_CLK. That is, the value of the data rate may be determined according to the frequency value of the reference clock signal REF_CLK.

The UFS interface <NUM> may support a plurality of lanes, and each lane may be implemented by a differential pair. For example, a UFS interface may include one or more reception lanes and one or more transmission lanes. In <FIG>, the pair of lines for transmitting the differential input signal pair DIN_T and DIN_C may constitute a reception lane, and the pair of lines for transmitting the differential output signal pair DOUT_T and DOUT_C may constitute a transmission lane. Although one transmission lane and one reception lane are illustrated in <FIG>, the respective numbers of transmission lanes and reception lanes may be changed.

The reception lane and the transmission lane may transfer data in a serial communication manner, and full-duplex type communication between the UFS host <NUM> and the UFS device <NUM> may be allowed due to a structure in which the reception lane is separated from the transmission lane. That is, even while receiving data from the UFS host <NUM> through the reception lane, the UFS device <NUM> may transmit data to the UFS host <NUM> through the transmission lane. In addition, control data such as a command from the UFS host <NUM> to the UFS device <NUM>, and user data, which the UFS host <NUM> intends to store in the non-volatile storage <NUM> of the UFS device <NUM> or to read from the non-volatile storage <NUM>, may be transferred through the same lane. Accordingly, there is no need to further arrange, between the UFS host <NUM> and the UFS device <NUM>, a separate lane for data transfer, in addition to a pair of reception lanes and a pair of transmission lanes.

The UFS device controller <NUM> of the UFS device <NUM> may take overall control of operations of the UFS device <NUM>. The UFS device controller <NUM> may manage the non-volatile storage <NUM> through a logical unit (LU) <NUM>, which is a logical data storage unit. The number of LUs <NUM> may be, but is not limited to, <NUM>. The UFS device controller <NUM> may include a flash translation layer (FTL) and, by using address mapping information of the FTL, may convert a logical data address, for example, a logical block address (LBA), which is transferred from the UFS host <NUM>, into a physical data address, for example, a physical block address (PBA). In the UFS system <NUM>, a logical block for storing user data may have a size in a certain range. For example, a minimum size of the logical block may be set to be <NUM> Kbyte.

When a command from the UFS host <NUM> is input to the UFS device <NUM> through the UIC layer <NUM>, the UFS device controller <NUM> may perform an operation according to the input command, and when the operation is completed, the UFS device controller <NUM> may transmit a completion response to the UFS host <NUM>.

For example, when the UFS host <NUM> intends to store user data in the UFS device <NUM>, the UFS host <NUM> may transmit a data storage command to the UFS device <NUM>. When a response indicative of being ready to receive the user data is received from the UFS device <NUM>, the UFS host <NUM> may transmit the user data to the UFS device <NUM>. The UFS device controller <NUM> may temporarily store the received user data in the device memory <NUM> and, based on the address mapping information of the FTL, may store the user data temporarily stored in the device memory <NUM> in a selected location of the non-volatile storage <NUM>.

As another example, when the UFS host <NUM> intends to read the user data stored in the UFS device <NUM>, the UFS host <NUM> may transmit a data read command to the UFS device <NUM>. The UFS device controller <NUM> having received the data read command may read the user data from the non-volatile storage <NUM>, based on the data read command, and may temporarily store the read user data in the device memory <NUM>. In this data read process, the UFS device controller <NUM> may detect and correct an error in the read user data, by using an embedded error correction code (ECC) circuit (not shown). In addition, the UFS device controller <NUM> may transmit the user data temporarily stored in the device memory <NUM> to the UFS host <NUM>. Further, the UFS device controller <NUM> may further include an advanced encryption standard (AES) circuit (not shown), and the AES circuit may encrypt or decrypt data, which is input to the UFS device controller <NUM>, by using a symmetric-key algorithm.

The UFS host <NUM> may store commands, which is to be transmitted to the UFS device <NUM>, in the UFS host register <NUM> capable of functioning as a command queue according to an order, and may transmit the commands to the UFS device <NUM> in the order. Here, even when a previously transmitted command is still being processed by the UFS device <NUM>, that is, even before the UFS host <NUM> receives a notification indicating that processing of the previously transmitted command is completed by the UFS device <NUM>, the UFS host <NUM> may transmit the next command on standby in the command queue to the UFS device <NUM>, and thus, the UFS device <NUM> may also receive the next command from the UFS host <NUM> even while processing the previously transmitted command. The maximum number of commands capable of being stored in the command queue (that is, a queue depth) may be, for example, <NUM>. In addition, the command queue may be implemented by a circular queue type in which a start and an end of a command sequence stored in a queue are respectively indicated by a head pointer and a tail pointer.

Each of the plurality of storage units <NUM> may include a memory cell array and a control circuit for controlling an operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells, and each memory cell may be a single level cell (SLC) storing <NUM> bit of information or may be a cell storing <NUM> or more bits of information, such as a multi-level cell (MLC), a triple level cell (TLC), or a quadruple level cell (QLC). The 3D memory cell array may include a vertical NAND string vertically oriented such that at least one memory cell is located on another memory cell.

VCC, VCCQ1, VCCQ2, or the like may be input as a power supply voltage to the UFS device <NUM>. VCC, which is a main power supply voltage for the UFS device <NUM>, may have a value of about <NUM> V to about <NUM> V. VCCQ1, which is a power supply voltage for supplying a voltage in a low-voltage range, is mainly for the UFS device controller <NUM> and may have a value of about <NUM> V to about <NUM> V. VCCQ2, which is a power supply voltage for supplying a voltage in a range higher than VCCQ1 and lower than VCC, is mainly for an input-output interface such as the MIPI M-PHY <NUM> and may have a value of about <NUM> V to about <NUM> V. The power supply voltages set forth above may be supplied for the respective components of the UFS device <NUM> through the regulator <NUM>. The regulator <NUM> may be implemented by a set of unit regulators respectively connected to different ones of the power supply voltages set forth above.

<FIG> illustrates a non-volatile storage 2220a according to an embodiment of the present disclosure.

Referring to <FIG>, the non-volatile storage 2220a may include a memory device <NUM> and a memory controller <NUM>. The non-volatile storage 2220a may support a plurality of channels CH1 to CHm, and the memory device <NUM> may be connected to the memory controller <NUM> through the plurality of channels CH1 to CHm. For example, the non-volatile storage 2220a may be implemented as a storage device such as a solid state drive (SSD).

The memory device <NUM> may include a plurality of non-volatile memory devices NVM11 to NVMmn. Each of the non-volatile memory devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a corresponding way. For example, the non-volatile memory devices NVM11 to NVM1n may be respectively connected to a first channel CH1 through ways W11 to W1n, and the nonvolatile memory devices NVM21 to NVM2n may be respectively connected to a second channel CH2 through ways W21 to W2n. In an example embodiment, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented by any memory unit capable of operating according to an individual command from the memory controller <NUM>. For example, although each of the non-volatile memory devices NVM11 to NVMmn may be implemented by a chip or a die, the present disclosure is not limited thereto.

The memory controller <NUM> may transmit signals to and receive signals from the memory device <NUM> through the plurality of channels CH1 to CHm. For example, the memory controller <NUM> may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device <NUM> through the channels CH1 to CHm or may receive the data DATAa to DATAm from the memory device <NUM>.

The memory controller <NUM> may select, through each channel, one of the nonvolatile memory devices connected to the corresponding channel and may transmit signals to and receive signals from the selected non-volatile memory device. For example, the memory controller <NUM> may select a non-volatile memory device NVM11 from among the non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller <NUM> may transmit the command CMDa, the address ADDRa, and the data DATAa to the selected non-volatile memory device NVM11 or may receive the data DATAa from the selected non-volatile memory device NVM11, through the first channel CH1.

The memory controller <NUM> may transmit signals to and receive signals from the memory device <NUM> in parallel through different channels. For example, the memory controller <NUM> may transmit the command CMDb to the memory device <NUM> through the second channel CH2 while transmitting the command CMDa to the memory device <NUM> through the first channel CH1. For example, the memory controller <NUM> may receive the data DATAb from the memory device <NUM> through the second channel CH2 while receiving the data DATAa from the memory device <NUM> through the first channel CH1.

The memory controller <NUM> may control overall operations of the memory device <NUM>. The memory controller <NUM> may control each of the non-volatile memory devices NVM11 to NVMmn connected to the channels CH1 to CHm by transmitting signals to the channels CH1 to CHm. For example, the memory controller <NUM> may control one selected from among the non-volatile memory devices NVM11 to NVM1n by transmitting the command CMDa and the address ADDRa to the first channel CH1.

Each of the non-volatile memory devices NVM11 to NVMmn may be operated according to control by the memory controller <NUM>. For example, the non-volatile memory device NVM11 may program the data DATAa according to the command CMDa, the address ADDRa, and the data DATAa, which are provided to the first channel CH1. For example, the non-volatile memory device NVM21 may read the data DATAb according to the command CMDb and the address ADDRb, which are provided to the second channel CH2, and may transmit the read data DATAb to the memory controller <NUM>.

Although <FIG> illustrates that the memory device <NUM> communicates with the memory controller <NUM> through m channels and includes n non-volatile memory devices in correspondence with each channel, the number of channels and the number of non-volatile memory devices connected to a single channel may be variously changed.

<FIG> illustrates a non-volatile storage 2220b according to an embodiment of the present disclosure. Referring to <FIG>, the non-volatile storage 2220b may include a memory device <NUM> and a memory controller <NUM>. The memory device <NUM> may correspond to one of the non-volatile memory devices NVM11 to NVMmn communicating with the memory controller <NUM> based on one of the first to m-th channels CH1 to CHm in <FIG>. The memory controller <NUM> may correspond to the memory controller <NUM> in <FIG>.

The memory device <NUM> may include first to eighth pins P11 to P18, a memory interface circuit <NUM>, a control logic circuit <NUM>, and a memory cell array <NUM>.

The memory interface circuit <NUM> may receive a chip enable signal nCE from the memory controller <NUM> through the first pin P11. The memory interface circuit <NUM> may transmit signals to and receive signals from the memory controller <NUM> through the second to eighth pins P12 to P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (for example, a low level), the memory interface circuit <NUM> may transmit signals to and receive signals from the memory controller <NUM> through the second to eighth pins P12 to P18.

The memory interface circuit <NUM> may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller <NUM> through the second to fourth pins P12 to P14, respectively. The memory interface circuit <NUM> may receive a data signal DQ from the memory controller <NUM> or may transmit the data signal DQ to the memory controller <NUM>, through the seventh pin P17. A command CMD, an address ADDR, and data DATA may be transferred through the data signal DQ. For example, the data signal DQ may be transferred through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to a plurality of data signals.

The memory interface circuit <NUM> may obtain the command CMD from the data signal DQ received in an enabled period (for example, a high-level state) of the command latch enable signal CLE, based on toggle timings of the write enable signal nWE. The memory interface circuit <NUM> may obtain the address ADDR from the data signal DQ received in an enabled period (for example, a high-level state) of the address latch enable signal ALE, based on the toggle timings of the write enable signal nWE.

In an example embodiment, the write enable signal nWE may be maintained in a static state (for example, a high level or a low level) and then may toggle between the high level and the low level. For example, the write enable signal nWE may toggle in a period in which the command CMD or the address ADDR is transmitted. Accordingly, the memory interface circuit <NUM> may obtain the command CMD or the address ADDR, based on the toggle timings of the write enable signal nWE.

The memory interface circuit <NUM> may receive a read enable signal nRE from the memory controller <NUM> through the fifth pin P15. The memory interface circuit <NUM> may receive a data strobe signal DQS from the memory controller <NUM> or transmit the data strobe signal DQS to the memory controller <NUM>, through the sixth pin P16.

In a data output operation of the memory device <NUM>, the memory interface circuit <NUM> may receive the read enable signal nRE that toggles, through the fifth pin P15, before the data DATA is output. The memory interface circuit <NUM> may generate the data strobe signal DQS that toggles, based on the toggling of the read enable signal nRE. For example, the memory interface circuit <NUM> may generate the data strobe signal DQS starting to toggle after a preset delay (for example, tDQSRE) from a toggling start time of the read enable signal nRE. The memory interface circuit <NUM> may transmit the data signal DQ including the data DATA, based on a toggle timing of the data strobe signal DQS. Accordingly, the data DATA may be transmitted to the memory controller <NUM> in alignment with the toggle timing of the data strobe signal DQS.

In a data input operation of the memory device <NUM>, when the data signal DQ including the data DATA is received from the memory controller <NUM>, the memory interface circuit <NUM> may receive the data strobe signal DQS that toggles, together with the data DATA, from the memory controller <NUM>. The memory interface circuit <NUM> may obtain the data DATA from the data signal DQ, based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit <NUM> may obtain the data DATA by sampling the data signal DQ at a rising edge and a falling edge of the data strobe signal DQS.

The memory interface circuit <NUM> may transmit a ready/busy output signal nR/B to the memory controller <NUM> through the eighth pin P18. The memory interface circuit <NUM> may transmit state information of the memory device <NUM> to the memory controller <NUM> through the ready/busy output signal nR/B. When the memory device <NUM> is in a busy state (that is, when internal operations of the memory device <NUM> are being performed), the memory interface circuit <NUM> may transmit, to the memory controller <NUM>, the ready/busy output signal nR/B indicating the busy state. When the memory device <NUM> is in a ready state (that is, when the internal operations of the memory device <NUM> are not being performed or are completed), the memory interface circuit <NUM> may transmit, to the memory controller <NUM>, the ready/busy output signal nR/B indicating the ready state. For example, while the memory device <NUM> reads the data DATA from the memory cell array <NUM> in response to a page read command, the memory interface circuit <NUM> may transmit, to the memory controller <NUM>, the ready/busy output signal nR/B indicating the busy state (for example, a low level). For example, while the memory device <NUM> programs the data DATA into the memory cell array <NUM> in response to a program command, the memory interface circuit <NUM> may transmit, to the memory controller <NUM>, the ready/busy output signal nR/B indicating the busy state (for example, a low level).

The control logic circuit <NUM> may generally control various operations of the memory device <NUM>. The control logic circuit <NUM> may receive a command/address CMD/ADDR obtained from the memory interface circuit <NUM>. The control logic circuit <NUM> may generate control signals for controlling the other components of the memory device <NUM>, according to the received command/address CMD/ADDR. For example, the control logic circuit <NUM> may generate various control signals for programming the data DATA into the memory cell array <NUM> or reading the data DATA from the memory cell array <NUM>.

The memory cell array <NUM> may store the data DATA obtained from the memory interface circuit <NUM>, according to control by the control logic circuit <NUM>. The memory cell array <NUM> may output the stored data DATA to the control logic circuit <NUM>, according to control by the control logic circuit <NUM>.

The memory cell array <NUM> may include a plurality of memory cells. For example, the plurality of memory cells may include flash memory cells. However, the present disclosure is not limited thereto, and the memory cells may include RRAM cells, ferroelectric random access memory (FRAM) cells, PRAM cells, thyristor random access memory (TRAM) cells, or magnetic random access memory (MRAM) cells. Hereinafter, an embodiment of the present disclosure, in which the memory cells are NAND flash memory cells, will be mainly described.

The memory controller <NUM> may include first to eighth pins P21 to P28 and a controller interface circuit <NUM>. The first to eighth pins P21 to P28 may respectively correspond to the first to eighth pins P11 to P18 of the memory device <NUM>.

The controller interface circuit <NUM> may transmit the chip enable signal nCE to the memory device <NUM> through the first pin P21. The controller interface circuit <NUM> may transmit signals to and receive signals from the memory device <NUM>, which is selected through the chip enable signal nCE, through the second to eighth pins P22 to P28.

The controller interface circuit <NUM> may transmit the command enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device <NUM> through the second to fourth pins P22 to P24. The controller interface circuit <NUM> may transmit the data signal DQ to the memory device <NUM> or receive the data signal DQ from the memory device <NUM>, through the seventh pin P27.

The controller interface circuit <NUM> may transmit the data signal DQ including the command CMD or the address ADDR, together with the write enable signal nWE that is toggling, to the memory device <NUM>. The controller interface circuit <NUM> may transmit the data signal DQ including the command CMD according to transmitting the command latch enable signal CLE having an enabled state, and the controller interface circuit <NUM> may transmit the data signal DQ including the address ADDR according to transmitting the address latch enable signal ALE having an enabled state.

The controller interface circuit <NUM> may transmit the read enable signal nRE to the memory device <NUM> through the fifth pin P25. The controller interface circuit <NUM> may receive the data strobe signal DQS from the memory device <NUM> or transmit the data strobe signal DQS to the memory device <NUM>, through the sixth pin P26.

In a data output operation of the memory device <NUM>, the controller interface circuit <NUM> may generate the read enable signal nRE that toggles, and may transmit the read enable signal nRE to the memory device <NUM>. For example, the controller interface circuit <NUM> may generate the read enable signal nRE, which changes from a static state (for example, a high level or a low level) to a toggle state, before the data DATA is output. Accordingly, in the memory device <NUM>, the data strobe signal DQS toggling based on the read enable signal nRE may be generated. The controller interface circuit <NUM> may receive the data signal DQ including the data DATA, together with the data strobe signal DQS that toggles, from the memory device <NUM>. The controller interface circuit <NUM> may obtain the data DATA from the data signal DQ, based on the toggle timing of the data strobe signal DQS.

In a data input operation of the memory device <NUM>, the controller interface circuit <NUM> may generate the data strobe signal DQS that toggles. For example, the controller interface circuit <NUM> may generate the data strobe signal DQS, which changes from a static state (for example, a high level or a low level) to a toggle state, before the data DATA is transmitted. The controller interface circuit <NUM> may transmit the data signal DQ including the data DATA to the memory device <NUM>, based on toggle timings of the data strobe signal DQS.

Claim 1:
A processor (<NUM>) configured to control a storage device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, 1300a, 1300b), the processor (<NUM>) comprising:
at least one host write buffer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) generated based on device information of the storage device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, 1300a, 1300b);
a control module configured to control the at least one host write buffer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>),
wherein the control module is further configured:
to store, in the at least one host write buffer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), a plurality of write commands generated by a host (<NUM>, <NUM>),
to merge the plurality of write commands to generate a merged write command, and
to transmit the generated merged write command to the storage device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, 1300a, 1300b); and
wherein a size of the at least one host write buffer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) is allocated based on a unit of interleaving processing for simultaneously processing by several chips in response to a request received from the host (<NUM>, <NUM>),
the processor (<NUM>) further comprising a meta-memory buffer configured to merge write commands of non-consecutive logical block addresses,
wherein the meta-memory buffer is further configured to be dynamically allocated according to a number of write commands merged in the at least one host write buffer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) and store meta information including at least one of a logical block address and length information of data corresponding to each of the write commands, and
wherein the control module, when transmitting a merged write command from a host write buffer (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), is further configured to generate an extra header segment, EHS, including the meta information, to be transmitted to the storage device (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, 1300a, 1300b).