Patent Description:
Some existing quantum state measurement backend technologies define various layers of measurements associated with capturing a quantum state of a quantum bit (qubit). For example, some existing quantum state measurement backend technologies define <NUM> layers of measurements for a qubit state: Level <NUM> is raw data, which is a filtered version of the individual samples that are captured from an analog-to-digital converter (ADC) device: Level <NUM> resolves the raw data through a kernel into a single pair of complex numbers (e.g., an in-phase (I) vector and a quadrature-phase (Q) vector); and Level <NUM> further resolves it to a single binary bit through a discriminator.

Some existing quantum state measurement backend technologies allow an entity (e.g., a user) to specify which level, kernel, and discriminator to apply to each qubit measurement. A problem with such existing quantum state measurement backend technologies is that it is challenging to apply this amount of flexibility to one or more quantum backend computing resources, or to apply this amount of flexibility to different instances of quantum state measurement logic in a single quantum backend computing resource. Such challenges arise because implementations of different quantum backend computing resources may dramatically differ in their capture capabilities, quantity of samples they can capture, and flexibility in selecting different kernels and discriminators to apply to the data. In addition, some existing quantum measurement backend technologies use a compiler to map and schedule an entity's test criteria (e.g., user test criteria) onto instances of measurement logic in a quantum backend computing resource. Given the challenges described above, a problem with such existing quantum state measurement backend technologies is that they involve implementation of a unique compiler for each measurement instance. The publication of <NPL>), discloses a new language version/feature, called Qiskit Pulse added to the original Qiskit. Prior to Qiskit Pulse, user tests only had the ability to describe fixed sequences of quantum gates, with one measurement done on each qubit at the end of the test. Qiskit Pulse introduces enhancements to the language to allow users to do multiple measurements of qubits within the same test, and make decisions on those measurements to change the direction of the test while it was running.

Dependent claims set out particular embodiments. An advantage of such a system is that it can enable a quantum state measurement backend system to more quickly and more efficiently identify a greater quantity of quantum backend computing resources that can capture a quantum state measurement based on one or more entity defined criteria.

One or more embodiments are now described with reference to the drawings, wherein like referenced numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments. It is evident, however, in various cases, that the one or more embodiments can be practiced without these specific details.

Quantum computing is generally the use of quantum-mechanical phenomena for the purpose of performing computing and information processing functions. Quantum computing can be viewed in contrast to classical computing, which generally operates on binary values with transistors. That is, while classical computers can operate on bit values that are either <NUM> or <NUM>, quantum computers operate on quantum bits (qubits) that comprise superpositions of both <NUM> and <NUM>, can entangle multiple quantum bits, and use interference.

Given the problems described above with some existing quantum state measurement backend technologies, the present disclosure can be implemented to produce a solution to these problems in the form of systems, computer-implemented methods, and/or computer program products that can define a data processing function corresponding to at least one storage element in at least one stage of a quantum state measurement pipeline. An advantage of such systems, computer-implemented methods, and/or computer program products is that they can be implemented to enable a quantum state measurement backend system to more quickly and more efficiently identify a greater quantity of quantum backend computing resources that can capture a quantum state measurement based on one or more entity defined criteria.

In some embodiments, the present disclosure can be implemented to produce a solution to the problems described above in the form of systems, computer-implemented methods, and/or computer program products that can define the data processing function based on one or more entity defined criteria corresponding to the quantum state measurement pipeline; and/or define data processing functions corresponding to storage elements in the at least one stage of the quantum state measurement pipeline to enable a defined quantity of quantum backend computing resources to capture a quantum state measurement based on quantum state measurement logic comprising the data processing functions. An advantage of such systems, computer-implemented methods, and/or computer program products is that they can be implemented to enable a quantum state measurement backend system to more quickly and more efficiently identify a greater quantity of quantum backend computing resources that can capture a quantum state measurement based on one or more entity defined criteria.

It will be understood that when an element is referred to herein as being "coupled" to another element, it can describe one or more different types of coupling. For example, when an element is referred to herein as being "coupled" to another element, it can described one or more different types of coupling including, but not limited to, chemical coupling, communicative coupling, capacitive coupling, electrical coupling, electromagnetic coupling, inductive coupling, operative coupling, optical coupling, physical coupling, thermal coupling, and/or another type of coupling.

As referenced herein, an entity can comprise a human, a client, a user, a computing device, a software application, an agent, a machine learning model, an artificial intelligence, and/or another entity. It should be appreciated that such an entity can implement one or more embodiments of the subject disclosure described herein.

<FIG> illustrates a block diagram of an example, non-limiting system <NUM> that can facilitate quantum state measurement logic used in a quantum state measurement backend process in accordance with one or more embodiments described herein. System <NUM> can comprise a quantum state measurement logic system <NUM>, which can be associated with a cloud computing environment. For example, quantum state measurement logic system <NUM> can be associated with cloud computing environment <NUM> described below with reference to <FIG> and/or one or more functional abstraction layers described below with reference to <FIG> (e.g., hardware and software layer <NUM>, virtualization layer <NUM>, management layer <NUM>, and/or workloads layer <NUM>).

Quantum state measurement logic system <NUM> and/or components thereof (e.g., stage control register component <NUM>, compiler component <NUM>, etc.) can employ one or more computing resources of cloud computing environment <NUM> described below with reference to <FIG> and/or one or more functional abstraction layers (e.g., quantum software, etc.) described below with reference to <FIG> to execute one or more operations in accordance with one or more embodiments of the subject disclosure described herein. For example, cloud computing environment <NUM> and/or such one or more functional abstraction layers can comprise one or more classical computing devices (e.g., classical computer, classical processor, virtual machine, server, etc.), quantum hardware, and/or quantum software (e.g., quantum computing device, quantum computer, quantum processor, quantum circuit simulation software, superconducting circuit, etc.) that can be employed by quantum state measurement logic system <NUM> and/or components thereof to execute one or more operations in accordance with one or more embodiments of the subject disclosure described herein. For instance, quantum state measurement logic system <NUM> and/or components thereof can employ such one or more classical and/or quantum computing resources to execute one or more classical and/or quantum: mathematical function, calculation, and/or equation; computing and/or processing script; algorithm; model (e.g., artificial intelligence (AI) model, machine learning (ML) model, etc.); and/or another operation in accordance with one or more embodiments of the subject disclosure described herein.

As illustrated in the example embodiment depicted in <FIG>, quantum state measurement logic system <NUM> can comprise a memory <NUM>, a processor <NUM>, a stage control register component <NUM>, a compiler component <NUM>, and/or a bus <NUM>.

It should be appreciated that the embodiments of the subject disclosure depicted in various figures disclosed herein are for illustration only, and as such, the architecture of such embodiments are not limited to the systems, devices, and/or components depicted therein. For example, in some embodiments, system <NUM> and/or quantum state measurement logic system <NUM> can further comprise various computer and/or computing-based elements described herein with reference to operating environment <NUM> and <FIG>. In several embodiments, such computer and/or computing-based elements can be used in connection with implementing one or more of the systems, devices, components, and/or computer-implemented operations shown and described in connection with <FIG> and/or other figures disclosed herein.

Memory <NUM> can store one or more computer and/or machine readable, writable, and/or executable components and/or instructions that, when executed by processor <NUM> (e.g., a classical processor, a quantum processor, etc.), can facilitate performance of operations defined by the executable component(s) and/or instruction(s). For example, memory <NUM> can store computer and/or machine readable, writable, and/or executable components and/or instructions that, when executed by processor <NUM>, can facilitate execution of the various functions described herein relating to quantum state measurement logic system <NUM>, stage control register component <NUM>, compiler component <NUM>, and/or another component associated with quantum state measurement logic system <NUM> as described herein with or without reference to the various figures of the subject disclosure.

Memory <NUM> can comprise volatile memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), etc.) and/or non-volatile memory (e.g., read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), etc.) that can employ one or more memory architectures. Further examples of memory <NUM> are described below with reference to system memory <NUM> and <FIG>. Such examples of memory <NUM> can be employed to implement any embodiments of the subject disclosure.

Processor <NUM> can comprise one or more types of processors and/or electronic circuitry (e.g., a classical processor, a quantum processor, etc.) that can implement one or more computer and/or machine readable, writable, and/or executable components and/or instructions that can be stored on memory <NUM>. For example, processor <NUM> can perform various operations that can be specified by such computer and/or machine readable, writable, and/or executable components and/or instructions including, but not limited to, logic, control, input/output (I/O), arithmetic, and/or the like. In some embodiments, processor <NUM> can comprise one or more central processing unit, multi-core processor, microprocessor, dual microprocessors, microcontroller, System on a Chip (SOC), array processor, vector processor, quantum processor, and/or another type of processor. Further examples of processor <NUM> are described below with reference to processing unit <NUM> and <FIG>. Such examples of processor <NUM> can be employed to implement any embodiments of the subject disclosure.

Quantum state measurement logic system <NUM>, memory <NUM>, processor <NUM>, stage control register component <NUM>, compiler component <NUM>, and/or another component of quantum state measurement logic system <NUM> as described herein can be communicatively, electrically, operatively, and/or optically coupled to one another via a bus <NUM> to perform functions of system <NUM>, quantum state measurement logic system <NUM>, and/or any components coupled therewith. Bus <NUM> can comprise one or more memory bus, memory controller, peripheral bus, external bus, local bus, a quantum bus, and/or another type of bus that can employ various bus architectures. Further examples of bus <NUM> are described below with reference to system bus <NUM> and <FIG>. Such examples of bus <NUM> can be employed to implement any embodiments of the subject disclosure.

Quantum state measurement logic system <NUM> can comprise any type of component, machine, device, facility, apparatus, and/or instrument that comprises a processor and/or can be capable of effective and/or operative communication with a wired and/or wireless network. All such embodiments are envisioned. For example, quantum state measurement logic system <NUM> can comprise a server device, a computing device, a general-purpose computer, a special-purpose computer, a quantum computing device (e.g., a quantum computer), a tablet computing device, a handheld device, a server class computing machine and/or database, a laptop computer, a notebook computer, a desktop computer, a cell phone, a smart phone, a consumer appliance and/or instrumentation, an industrial and/or commercial device, a digital assistant, a multimedia Internet enabled phone, a multimedia players, and/or another type of device.

Quantum state measurement logic system <NUM> can be coupled (e.g., communicatively, electrically, operatively, optically, etc.) to one or more external systems, sources, and/or devices (e.g., classical and/or quantum computing devices, communication devices, etc.) via a data cable (e.g., High-Definition Multimedia Interface (HDMI), recommended standard (RS) <NUM>, Ethernet cable, etc.). In some embodiments, quantum state measurement logic system <NUM> can be coupled (e.g., communicatively, electrically, operatively, optically, etc.) to one or more external systems, sources, and/or devices (e.g., classical and/or quantum computing devices, communication devices, etc.) via a network.

In some embodiments, such a network can comprise wired and wireless networks, including, but not limited to, a cellular network, a wide area network (WAN) (e.g., the Internet) or a local area network (LAN). For example, quantum state measurement logic system <NUM> can communicate with one or more external systems, sources, and/or devices, for instance, computing devices (and vice versa) using virtually any desired wired or wireless technology, including but not limited to: wireless fidelity (Wi-Fi), global system for mobile communications (GSM), universal mobile telecommunications system (UMTS), worldwide interoperability for microwave access (WiMAX), enhanced general packet radio service (enhanced GPRS), third generation partnership project (3GPP) long term evolution (LTE), third generation partnership project <NUM> (3GPP2) ultra mobile broadband (UMB), high speed packet access (HSPA), Zigbee and other <NUM>. XX wireless technologies and/or legacy telecommunication technologies, BLUETOOTH®, Session Initiation Protocol (SIP), ZIGBEE®, RF4CE protocol, WirelessHART protocol, 6LoWPAN (IPv6 over Low power Wireless Area Networks), Z-Wave, an ANT, an ultra-wideband (UWB) standard protocol, and/or other proprietary and non-proprietary communication protocols. In such an example, quantum state measurement logic system <NUM> can thus include hardware (e.g., a central processing unit (CPU), a transceiver, a decoder, quantum hardware, a quantum processor, etc.), software (e.g., a set of threads, a set of processes, software in execution, quantum pulse schedule, quantum circuit, quantum gates, etc.) or a combination of hardware and software that facilitates communicating information between quantum state measurement logic system <NUM> and external systems, sources, and/or devices (e.g., computing devices, communication devices, etc.).

Quantum state measurement logic system <NUM> can comprise one or more computer and/or machine readable, writable, and/or executable components and/or instructions that, when executed by processor <NUM> (e.g., a classical processor, a quantum processor, etc.), can facilitate performance of operations defined by such component(s) and/or instruction(s). Further, in numerous embodiments, any component associated with quantum state measurement logic system <NUM>, as described herein with or without reference to the various figures of the subject disclosure, can comprise one or more computer and/or machine readable, writable, and/or executable components and/or instructions that, when executed by processor <NUM>, can facilitate performance of operations defined by such component(s) and/or instruction(s). For example, stage control register component <NUM>, compiler component <NUM>, and/or any other components associated with quantum state measurement logic system <NUM> as disclosed herein (e.g., communicatively, electronically, operatively, and/or optically coupled with and/or employed by quantum state measurement logic system <NUM>), can comprise such computer and/or machine readable, writable, and/or executable component(s) and/or instruction(s). Consequently, according to numerous embodiments, quantum state measurement logic system <NUM> and/or any components associated therewith as disclosed herein, can employ processor <NUM> to execute such computer and/or machine readable, writable, and/or executable component(s) and/or instruction(s) to facilitate performance of one or more operations described herein with reference to quantum state measurement logic system <NUM> and/or any such components associated therewith.

Quantum state measurement logic system <NUM> can facilitate (e.g., via processor <NUM>) performance of operations executed by and/or associated with one or more components thereof (e.g., stage control register component <NUM>, compiler component <NUM>, etc.). For example, quantum state measurement logic system <NUM> can facilitate (e.g., via processor <NUM>): defining a data processing function corresponding to at least one storage element in at least one stage of a quantum state measurement pipeline.

In another example, as described in detail below, quantum state measurement logic system <NUM> can further facilitate (e.g., via processor <NUM>): generating quantum state measurement logic based on data processing functions corresponding to storage elements in the at least one stage of the quantum state measurement pipeline; identifying one or more quantum backend computing resources having ability to capture a quantum state measurement based on the quantum state measurement logic; defining the data processing function based on one or more entity defined criteria corresponding to the quantum state measurement pipeline; defining data processing functions corresponding to storage elements in the at least one stage of the quantum state measurement pipeline to enable a defined quantity of quantum backend computing resources to capture a quantum state measurement based on quantum state measurement logic comprising the data processing functions; and/or generating quantum state measurement logic based on a first set of data processing functions or a second set of data processing functions, wherein the first set of data processing functions comprises a reuse function corresponding to a single storage element in a bit stage of the quantum state measurement pipeline and the second set of data processing functions comprises an archive function corresponding to all storage elements in the bit stage, thereby facilitating reduced computational costs associated with one or more quantum backend computing resources that capture a quantum state measurement based on the quantum state measurement logic. In the above examples: the data processing function can comprise an archive function indicative of preserving a current quantum measurement result or a reuse function indicative of overlaying a current quantum measurement result with a subsequent quantum measurement result; and/or the at least one stage can comprise a capture array stage, a kernel stage, a vector pair value stage, a discriminator stage, and/or a bit stage.

Stage control register component <NUM> can define a data processing function corresponding to at least one storage element in at least one stage of a quantum state measurement pipeline. For example, stage control register component <NUM> can define a data processing function that can include, but is not limited to, an archive function indicative of preserving a current quantum measurement result, a reuse function indicative of overlaying a current quantum measurement result with a subsequent quantum measurement result, and/or another data processing function. Stage control register component <NUM> can define such a data processing function corresponding to at least one storage element in at least one stage of a quantum state measurement pipeline, where such at least one stage can include, but is not limited to, a capture array stage, a kernel stage, a vector pair value stage, a discriminator stage, a bit stage, and/or another stage of a quantum state measurement pipeline.

To define a data processing function corresponding to at least one storage element in at least one stage of a quantum state measurement pipeline, stage control register component <NUM> can generate one or more stage control registers that can each correspond to a certain stage of the quantum state measurement pipeline. In various embodiments, each of such one or more stage control registers can comprise at least one data processing function corresponding to at least one storage element in such a certain stage of the quantum state measurement pipeline. It should be appreciated that generation by stage control register component <NUM> of such one or more stage control registers described above can constitute defining a data processing function corresponding to at least one storage element in at least one stage of a quantum state measurement pipeline.

In some embodiments, stage control register component <NUM> can define multiple data processing functions that respectively correspond to multiple storage elements in at least one stage of a quantum state measurement pipeline. For example, stage control register component <NUM> can generate multiple stage control registers that respectively correspond to multiple stages of a quantum state measurement pipeline. In this example, each of such stage control registers can comprise multiple storage elements, where at least two of such multiple storage elements can have a data processing function associated therewith.

In the above example, it should be appreciated that stage control register component <NUM> can define multiple data processing functions that respectively correspond to multiple storage elements in at least one stage of the quantum state measurement pipeline to enable a defined quantity of quantum backend computing resources to capture a quantum state measurement based on quantum state measurement logic comprising the data processing functions. For example, it should be appreciated that stage control register component <NUM> can define multiple data processing functions that respectively correspond to multiple storage elements in at least one stage of the quantum state measurement pipeline to enable a greater quantity of quantum backend computing resources to capture a quantum state measurement based on quantum state measurement logic comprising the data processing functions (e.g., a greater quantity when compared to a certain quantity of quantum backend computing resources that can capture a quantum state measurement without using such quantum state measurement logic comprising the data processing functions).

Stage control register component <NUM> can define a data processing function based on one or more entity defined criteria corresponding to the quantum state measurement pipeline. For example, although not depicted in the figures, in some embodiments, quantum state measurement logic system <NUM> can comprise an interface component (e.g., a graphical user interface (GUI), an application programming interface (API), etc.) that an entity as defined herein can use to input one or more criteria corresponding to the quantum state measurement pipeline. For instance, such an entity can use such an interface component of quantum state measurement logic system <NUM> to: define the number of storage elements in each stage of the quantum state measurement pipeline; define a certain kernel to be used in a kernel stage of the quantum state measurement pipeline; define a certain discriminator to be used in a discriminator stage of the quantum state measurement pipeline; define one or more types of data processing functions (e.g., an archive function, a reuse function, etc.) that can be defined for one or more storage elements in at least one stage of the quantum state measurement pipeline; define a certain data processing function (e.g., an archive function, a reuse function, etc.) for one or more storage elements in at least one stage of the quantum state measurement pipeline; define one or more memory slots to store one or more binary values output by the quantum state measurement pipeline; and/or define another criterion corresponding to the quantum state measurement pipeline. In this example, stage control register component <NUM> can generate one or more of the above described stage control registers based on such one or more entity defined criteria, where each of such one or more stage control registers can correspond to a certain stage of the quantum state measurement pipeline.

Compiler component <NUM> can generate quantum state measurement logic based on data processing functions corresponding to storage elements in at least one stage of a quantum state measurement pipeline. For example, compiler component <NUM> can generate quantum state measurement logic based on (e.g., using) the data processing functions that can be defined by stage control register component <NUM> as described above, where such data processing functions correspond to storage elements in at least one stage of a quantum state measurement pipeline. For instance, compiler component <NUM> can generate quantum state measurement logic comprising the above described one or more stage control registers that can be generated by stage control register component <NUM>, where each state control register can correspond to a certain stage of a quantum state measurement pipeline and each state control register can comprise at least one data processing function corresponding to at least one storage element in the stage.

Compiler component <NUM> can identify one or more quantum backend computing resources having ability to capture a quantum state measurement based on the above described quantum state measurement logic that can be generated by compiler component <NUM>. For example, compiler component <NUM> can identify one or more quantum backend computing resources having ability to capture a quantum state measurement based on (e.g., using) quantum state measurement logic that can be generated by compiler component <NUM> based on (e.g., using) the data processing functions that can be defined by stage control register component <NUM> as described above. In various embodiments, such one or more quantum backend computing resources can include, but are not limited to, quantum based software, quantum hardware (e.g., quantum processor, superconducting circuit, etc.), a quantum device (e.g., a quantum computer, etc.), and/or another quantum backend computing resource. In these embodiments, such one or more quantum backend computing resources can capture a quantum state measurement of one or more qubits based on (e.g., using) quantum state measurement logic that can be generated by compiler component <NUM> as described above.

In an embodiment, compiler component <NUM> can generate quantum state measurement logic based on a first set of data processing functions or a second set of data processing functions. In this embodiment, the first set of data processing functions comprises a reuse function corresponding to a single storage element in a bit stage of a quantum state measurement pipeline and the second set of data processing functions comprises an archive function corresponding to all storage elements in such a bit stage. In this embodiment, stage control register component <NUM> can define such a first set of data processing functions and/or such a second set of data processing functions as described above. It should be appreciated that generation of such quantum state measurement logic based on (e.g., using) the above described first set of data processing functions or second set of data processing functions can thereby facilitate reduced computational costs associated with one or more quantum backend computing resources that capture a quantum state measurement based on the quantum state measurement logic.

<FIG> illustrates a block diagram of an example, non-limiting system <NUM> that can facilitate quantum state measurement logic used in a quantum state measurement backend process in accordance with one or more embodiments described herein. Repetitive description of like elements and/or processes employed in respective embodiments is omitted for sake of brevity.

System <NUM> can comprise an architecture of a quantum state measurement backend system that can facilitate a backend process of capturing a quantum state of one or more qubits. In some embodiments, system <NUM> can comprise an Acquire channel in a quantum state measurement backend system that can facilitate a backend process of capturing a quantum state of one or more qubits.

System <NUM> can comprise a quantum state measurement pipeline <NUM>. Quantum state measurement pipeline <NUM> can comprise a capture array stage <NUM>, a kernel stage <NUM>, a vector pair value stage <NUM>, a discriminator stage <NUM>, and/or a bit stage <NUM>. As illustrated in the example embodiment depicted in <FIG>: capture array stage <NUM> can comprise a capture array storage element 206a; kernel stage <NUM> can comprise a kernel instance 208a; vector pair value stage <NUM> can comprise a vector pair value storage element 210a; discriminator stage <NUM> can comprise a discriminator instance 212a; and/or bit stage <NUM> can comprise a bit storage element 214a.

System <NUM> can further comprise a filter <NUM> that can receive raw data (e.g., voltage values) output by an analog-to-digital converter (ADC), where such raw data can comprise an intermediate frequency (IF) that can be removed by filter <NUM> to yield a "Level <NUM>" data sample (referred to herein and denoted as "L0 samples" in <FIG>) that can comprise a complex number represented by a (real, imaginary) pair of numbers (denoted as "(re,im)" in <FIG>). In various embodiments, the L0 sample output by filter <NUM> can be input to quantum state measurement pipeline <NUM> (e.g., input to capture array stage <NUM> and/or capture array storage element 206a) for further processing by the various stages of quantum state measurement pipeline <NUM> as described below.

Although each stage of quantum state measurement pipeline <NUM> illustrated in the example embodiment depicted in <FIG> comprises only a single component (e.g., a single capture array storage element 206a, a single kernel instance 208a, a single vector pair value storage element 210a, a single discriminator instance 212a, and a single bit storage element 214a), it should be appreciated that the subject disclosure is not so limiting. For example, as described below with reference to <FIG> and <FIG>, each stage of quantum state measurement pipeline <NUM> can comprise multiples of such components (e.g., multiple capture array storage elements, multiple kernel instances, multiple vector pair value storage elements, multiple discriminator instances, and multiple bit storage elements). The example embodiment depicted in <FIG> illustrates how the first storage element and/or first instance of each stage of quantum state measurement pipeline <NUM> can be automatically selected by quantum state measurement logic system <NUM> to store and/or process the initial measurement data captured at the start of a qubit measurement. The example embodiments described below and depicted in <FIG> and <FIG> illustrate how subsequent storage elements and/or subsequent instances of each stage of quantum state measurement pipeline <NUM> can be used by quantum state measurement logic system <NUM> to store and/or process subsequent measurement data captured from one or more qubits.

As illustrated in the example embodiment depicted in <FIG>, at the start of a measurement of a qubit, the initial L0 sample output by filter <NUM> can be provided to capture array stage <NUM> and/or loaded into capture array storage element 206a. In various embodiments, such an L0 sample can comprise a complex numbers that describe the envelope of the signal coming from the qubit during measurement. In these embodiments, the L0 sample value may not be a raw voltage value out of an ADC as data at this level could still contain an intermediate frequency. Therefore, in these embodiments and as described above, filter <NUM> can remove any intermediate frequency, after which each data sample is a complex number represented by a (real, imaginary) pair of numbers. While filtered, in these embodiments, the complex number is still a data sample taken at a moment in time. In some embodiments, to describe the returned waveform, a series of data samples can be used, where an attribute "dtm" defines the time elapsed between data samples.

In the example embodiment illustrated in <FIG>, kernel instance 208a of kernel stage <NUM> can comprise a model, an algorithm, and/or a mathematical function that can convert the L0 sample stored in capture array storage element 206a into two complex numbers called an "IQ Pair" and referred to herein as a "Level <NUM>" data sample and/or an "L1 sample" (denoted as "L1 IQ pairs" in <FIG>). In this example embodiment, such an L1 sample can be stored in vector pair value storage element 210a as illustrated in <FIG>. In various embodiments, by passing the L0 sample through kernel instance 208a of kernel stage <NUM>, the waveform can be reduced to two values, an in-phase (I) value and a quadrature phase (Q) value that, together, can constitute the L1 sample. In these embodiments, the L1 sample can represent a weighted sum of the L0 samples. In some embodiments, kernel stage <NUM> can comprise different kernels that can each produce different weights, but the end goal is to create I and Q values that are distinctly different when the qubit measures in the |<NUM>〉 quantum state versus the |<NUM>〉 quantum state. In some embodiments, weighting can also be used by quantum state measurement logic system <NUM> to ignore samples taken while waiting for the qubit to send useful information at the start and/or end of a measurement interval.

As illustrated in the example embodiment depicted in <FIG>, the L1 samples that can be stored in vector pair value storage element 210a can be provided to discriminator instance 212a of discriminator stage <NUM>. In various embodiments, discriminator instance 212a can comprise a model, an algorithm, and/or a mathematical function that can reduce the L1 sample (e.g., the I and Q values) of the qubit measurement to a single binary value of <NUM> or <NUM>, referred to herein as a "Level <NUM>" data sample and/or an "L2 sample" (denoted as "L2 Bit" in <FIG>). In these embodiments, such an L2 sample (e.g., binary values of <NUM> or <NUM>), can be the most condensed form of measurement results. In these embodiments, as the L2 sample can be a single bit, it can be passed around, combined with other L2 samples, and/or reduced to a single, testable binary condition.

System <NUM> can further comprise one or more memory slots <NUM> (denoted as "memory_slot" in <FIG>) that can correspond to one or more qubits being measured or a certain qubit that is being measured multiple times (e.g., in a test performed by an entity as defined herein that implements quantum state measurement logic system <NUM> to perform the test). In the example embodiment depicted in <FIG>, each memory slot <NUM> can be used by quantum state measurement logic system <NUM> to provide measurement data for a certain qubit that is output by quantum state measurement pipeline <NUM> to an entity as defined herein that can implement quantum state measurement logic system <NUM>. As illustrated in the example embodiment depicted in <FIG>, a certain memory slot <NUM> denoted as "<NUM>" in <FIG> can be used by quantum state measurement logic system <NUM> to provide the L2 sample value (e.g., an L2 bit value of <NUM> or <NUM>) that can be stored in bit storage element 214a to an entity as defined herein that can implement quantum state measurement logic system <NUM>. In some embodiments, such one or more memory slots <NUM> can be defined by such an entity that can implement quantum state measurement logic system <NUM>. For example, such an entity can use an interface component of quantum state measurement logic system <NUM> (e.g., a GUI, an API, etc.) to designate a certain memory slot <NUM> to store L2 sample values (e.g., binary values) output by quantum state measurement pipeline <NUM> (e.g., output by bit storage element 214a of bit stage <NUM> in quantum state measurement pipeline <NUM>).

In some embodiments, one or more memory slots <NUM> depicted in <FIG> can be used by quantum state measurement logic system <NUM> to provide the L0 sample(s), the L1 sample(s), and/or the L2 sample(s) to an entity as defined herein that can implement quantum state measurement logic system <NUM>. The example embodiment described below and depicted in <FIG> illustrates how such different types of data (e.g., the L0, L1, and/or L2 samples) can be stored in one or more memory slots <NUM>.

<FIG> illustrates an example, non-limiting diagram <NUM> that can facilitate quantum state measurement logic used in a quantum state measurement backend process in accordance with one or more embodiments described herein. Repetitive description of like elements and/or processes employed in respective embodiments is omitted for sake of brevity.

Diagram <NUM> can comprise a memory layout corresponding to the above described L0, L1, and/or L2 samples that illustrates how such different types of data can be stored in one or more memory slots <NUM> and/or provided to an entity as defined herein that can implement quantum state measurement logic system <NUM>. Currently, quantum backend hardware of existing quantum state measurement backend systems does not preserve measurement data across experiments but a host can preserve measurement data across experiments and provide such data to an entity implementing such systems. Diagram <NUM> shown in the example embodiment depicted in <FIG> illustrates how quantum state measurement logic system <NUM> can store and/or provide such information via one or more memory slots <NUM> to an entity as defined herein that can implement quantum state measurement logic system <NUM>. In this example embodiment, diagram <NUM> further illustrates how the L0, L1, and/or L2 sample information can be presented to such an entity that can implement quantum state measurement logic system <NUM> (e.g., as real and imaginary floating point values, binary values, etc.).

In the example embodiment depicted in <FIG>, four measurements (denoted as "[<NUM>]," "[<NUM>]," "[<NUM>]," and "[<NUM>]" in <FIG>) can be performed by one or more quantum backend computing resources to capture three L0 samples (denoted as "Sample <NUM>," "Sample <NUM>," and "Sample <NUM>" in <FIG>). In this example embodiment, each L0 sample captured in each measurement can comprise a real and an imaginary value that can be expressed as floating point values as illustrated in <FIG>. In this example embodiment, the attribute "dtm" defines the time elapsed between the data samples (e.g., the time elapsed between Sample <NUM> and Sample <NUM> and the time elapsed between Sample <NUM> and Sample <NUM>). In this example embodiment, the L0 samples captured in each of the four measurements can be averaged (e.g., using a weighted average technique) by, for instance, kernel instance 208a of kernel stage <NUM> as described above with reference to <FIG> to yield a corresponding L1 sample for each of the four measurements. In this example embodiment, the L1 samples can also comprise a real and an imaginary value that can be expressed as floating point values as illustrated in <FIG>. In this example embodiment, the L1 samples of each of the four measurements can be reduced by, for instance, discriminator instance 212a of discriminator stage <NUM> as described above with reference to <FIG> down to yield a binary value of <NUM> or <NUM> (denoted as "Qvalue" and "Binary" in <FIG>).

System <NUM> can comprise an example, non-limiting alternative embodiment of system <NUM> described above with reference to <FIG>. As illustrated in the example embodiment depicted in <FIG>, capture array stage <NUM>, vector pair value stage <NUM>, and /or bit stage <NUM> can each comprise multiple storage elements that can be used in combination with kernel instance 208a and discriminator instance 212a to create multiple quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f. For instance, in the example embodiment illustrated in <FIG>: capture array stage <NUM> can comprise capture array storage elements 206a, 206b, 206c; vector pair value stage <NUM> can comprise vector pair value storage elements 210a, 210b, 210c, 210d, 210e, 210f; and/or bit stage <NUM> can comprise bit storage element 214a, 214b, 214c, 214d, 214e, 214f. In this example embodiment quantum state measurement pipeline 402a can comprise the same structure and/or functionality as that of quantum state measurement pipeline <NUM> described above with reference to <FIG>.

In the example embodiment illustrated in <FIG>, quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f can be generated by quantum state measurement logic system <NUM> using stage control register component <NUM>. For instance, in this example embodiment, stage control register component <NUM> can generate multiple stage control registers (e.g., <NUM>) that respectively correspond to capture array stage <NUM>, kernel stage <NUM>, vector pair value stage <NUM>, discriminator stage <NUM>, and bit stage <NUM>. As described in detail below, stage control register component <NUM> generates such stage control registers such that they respectively define a data processing function that corresponds to at least one instance or storage element in each of such stages. For instance, stage control register component <NUM> can generate such stage control registers such that they respectively define an archive function or a reuse function that corresponds to at least one instance or storage element in each of such stages. In this example, such an archive function can be indicative of preserving a current quantum measurement result and such a reuse function can be indicative of overlaying a current quantum measurement result with a subsequent quantum measurement result. For instance, at the start of an experiment, the first instance or first storage element of each stage can be used by default to process or store quantum state measurement data. As each measurement is taken, the bits of each stage control register generated by stage control register component <NUM> determines whether to switch to the next instance or storage element in the stage or reuse the current instance or storage element after the measurement is complete (e.g., use the current instance or storage element to process or store subsequent quantum state measurement data captured in a subsequent measurement).

As illustrated in the example embodiment depicted in <FIG>, stage control register component <NUM> can generate a stage control register for capture array stage <NUM> such that: capture array storage element 206a is used to store a first L0 sample and is reused to store a second L0 sample; capture array storage element 206b archives a third L0 sample; and capture array storage element 206c is used to store a fourth L0 sample and is reused to store a fifth and a sixth L0 sample. In this example embodiment, stage control register component <NUM> can generate a stage control register for kernel stage <NUM> such that kernel instance 208a is used to convert the first L0 sample to a first L1 sample and is reused to convert the second, third, fourth, fifth, and sixth L0 samples to second, third, fourth, fifth, and sixth L1 samples, respectively. In this example embodiment, stage control register component <NUM> can generate a stage control register for vector pair value stage <NUM> such that vector pair value storage elements 210a, 210b, 210c, 210d, 210e, 210f archive the first, second, third, fourth, fifth, and sixth L1 samples, respectively. In this example embodiment, stage control register component <NUM> can generate a stage control register for discriminator stage <NUM> such that discriminator instance 212a is used to reduce the first L1 sample to a first L2 sample and is reused to reduce the second, third, fourth, fifth, and sixth L1 samples to second, third, fourth, fifth, and sixth L2 samples, respectively. In this example embodiment, stage control register component <NUM> can generate a stage control register for bit stage <NUM> such that: bit storage element 214a archives the first L2 sample; bit storage element 214b is used to store the second L2 sample and is reused to store the third L2 sample; and bit storage elements 214c, 214d, 214e archive the fourth, fifth, and sixth L2 samples, respectively. As illustrated in the example embodiment depicted in <FIG>, each of the first, second, third, fourth, fifth, and sixth L2 samples can be provided via one or more memory slots <NUM> to an entity as defined herein that can implement quantum state measurement logic system <NUM>.

In the example embodiment illustrated in <FIG>, by generating the above described stage control registers for each stage in quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f, quantum state measurement logic system <NUM> and/or stage control register component <NUM> can thereby generate such quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f. Additionally, or alternatively, in this example embodiment, based on such generation of the above described stage control registers for each stage in quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f, compiler component <NUM> can generate quantum state measurement logic <NUM> illustrated in <FIG>. In some embodiments, compiler component <NUM> can identify one or more quantum backend computing resources having ability to capture a quantum state measurement based on (e.g., using) quantum state measurement logic <NUM>.

System <NUM> can comprise an example, non-limiting alternative embodiment of system <NUM> described above with reference to <FIG>. As illustrated in the example embodiment depicted in <FIG>, capture array stage <NUM>, kernel stage <NUM>, vector pair value stage <NUM>, discriminator stage <NUM>, and /or bit stage <NUM> can each comprise multiple instances and/or storage elements that can be used to create multiple quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f. For instance, in the example embodiment illustrated in <FIG>: capture array stage <NUM> can comprise capture array storage elements 206a, 206b, 206c; kernel stage <NUM> can comprise kernel instances 208a, 208b, 208c; vector pair value stage <NUM> can comprise vector pair value storage elements 210a, 210b, 210c, 210d, 210e, 210f; discriminator stage <NUM> can comprise discriminator instances 212a, 212b, 212c; and/or bit stage <NUM> can comprise bit storage element 214a, 214b, 214c, 214d, 214e, 214f. In this example embodiment, quantum state measurement pipeline 502a can comprise the same structure and/or functionality as that of quantum state measurement pipeline 402a described above with reference to <FIG>.

In the example embodiment illustrated in <FIG>, quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f can be generated by quantum state measurement logic system <NUM> using stage control register component <NUM>. For instance, in this example embodiment, stage control register component <NUM> can generate multiple stage control registers (e.g., <NUM>) that respectively correspond to capture array stage <NUM>, kernel stage <NUM>, vector pair value stage <NUM>, discriminator stage <NUM>, and bit stage <NUM>. As described in detail below, stage control register component <NUM> generates such stage control registers such that they respectively define a data processing function that corresponds to at least one instance or storage element in each of such stages. For instance, stage control register component <NUM> can generate such stage control registers such that they respectively define an archive function or a reuse function that corresponds to at least one instance or storage element in each of such stages. In this example, such an archive function can be indicative of preserving a current quantum measurement result and such a reuse function can be indicative of overlaying a current quantum measurement result with a subsequent quantum measurement result. For instance, at the start of an experiment, the first instance or first storage element of each stage can be used by default to process or store quantum state measurement data. As each measurement is taken, the bits of each stage control register generated by stage control register component <NUM> determines whether to switch to the next instance or storage element in the stage or reuse the current instance or storage element after the measurement is complete (e.g., use the current instance or storage element to process or store subsequent quantum state measurement data captured in a subsequent measurement).

As illustrated in the example embodiment depicted in <FIG>, stage control register component <NUM> can generate a stage control register for capture array stage <NUM> such that: capture array storage element 206a is used to store a first L0 sample and is reused to store a second L0 sample; capture array storage element 206b archives a third L0 sample; and capture array storage element 206c is used to store a fourth L0 sample and is reused to store a fifth L0 sample and a sixth L0 sample. In this example embodiment, stage control register component <NUM> can generate a stage control register for kernel stage <NUM> such that: kernel instance 208a is used to convert the first L0 sample to a first L1 sample; kernel instance 208b is used to convert the second L0 sample to a second L1 sample and is reused to convert the third L0 sample to a third L1 sample; and kernel instance 208c is used to convert the fourth L0 sample to a fourth L1 sample and is reused to convert the fifth and sixth L0 samples to a fifth L1 sample and a sixth L1 sample, respectively. In this example embodiment, stage control register component <NUM> can generate a stage control register for vector pair value stage <NUM> such that vector pair value storage elements 210a, 210b, 210c, 210d, 210e, 210f archive the first, second, third, fourth, fifth, and sixth L1 samples, respectively. In this example embodiment, stage control register component <NUM> can generate a stage control register for discriminator stage <NUM> such that: discriminator instance 212a is used to reduce the first L1 sample to a first L2 sample and is reused to reduce the second and third L1 samples to a second L2 sample and a third L2 sample, respectively; and discriminator instance 212b is used to reduce the fourth L1 sample to a fourth L2 sample and is reused to reduce the fifth and sixth L1 samples to a fifth L2 sample and a sixth L2 sample, respectively. In this example embodiment, stage control register component <NUM> can generate a stage control register for bit stage <NUM> such that: bit storage element 214a archives the first L2 sample; bit storage element 214b is used to store the second L2 sample and is reused to store the third L2 sample; and bit storage elements 214c, 214d, 214e archive the fourth, fifth, and sixth L2 samples, respectively. As illustrated in the example embodiment depicted in <FIG>, each of the first, second, third, fourth, fifth, and sixth L2 samples can be provided via one or more memory slots <NUM> to an entity as defined herein that can implement quantum state measurement logic system <NUM>.

In the example embodiment illustrated in <FIG>, by generating the above described stage control registers for each stage in quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f, quantum state measurement logic system <NUM> and/or stage control register component <NUM> can thereby generate such quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f. Additionally, or alternatively, in this example embodiment, based on such generation of the above described stage control registers for each stage in quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f, compiler component <NUM> can generate quantum state measurement logic <NUM> illustrated in <FIG>. In some embodiments, compiler component <NUM> can identify one or more quantum backend computing resources having ability to capture a quantum state measurement based on (e.g., using) quantum state measurement logic <NUM>.

System <NUM> shown in the example embodiment depicted in <FIG> illustrates the logic from a conceptual standpoint that can exist between any two of the above described stages of quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f and/or quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f, where such two stages are denoted as "Stage N" and "Stage N+<NUM>" in <FIG>. In the example embodiments described above with reference to <FIG> and <FIG>, by dynamically changing stage instances and/or storage elements using the above described stage control registers that can be generated by stage control register component <NUM>, it should be appreciated that quantum state measurement logic system <NUM>, system <NUM>, and/or system <NUM> can effectively use a selection mechanism between stages to change which instance and/or storage element is active and use it as the input into the next stage. In the example embodiment depicted in <FIG>, system <NUM> can represent such a selection mechanism. In the example embodiment depicted in <FIG>, system <NUM> illustrates how the above described selection mechanism and stage control registers operate and precisely defines the boundaries used to describe latencies through each pipeline described above (e.g., quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f and quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f).

As described in detail below, bits of each stage control register described above that can be generated by stage control register component <NUM> are used to control the above described selection mechanism represented as system <NUM> in the example embodiment depicted in <FIG>. As described above with reference to the example embodiments depicted in <FIG>, <FIG>, and <FIG>, instance <NUM> and/or storage element <NUM> of each stage and bit <NUM> of the corresponding stage control register generated by stage control register component <NUM> can be set as the active entities at the start of each experiment. In these example embodiments and in the example embodiment illustrated in <FIG>, as end of measurement (EOM) indications are received by system <NUM>, a different bit can be selected from a stage control register <NUM> corresponding to a certain stage (denoted as "Stage N SCR Register" in <FIG>), where stage control register <NUM> can be generated by stage control register component <NUM> as described above. In these example embodiments, the selected bit, the EOM, and knowledge of when the active instance and/or active storage element has completed processing the current measurement are used (e.g., by quantum state measurement logic system <NUM>, stage control register component <NUM>, compiler component <NUM>, system <NUM>, stage control register <NUM>, and/or a selection multiplexer <NUM> of system <NUM>) to determine whether or not to change the active instance and/or active storage element to the next one in line. In these embodiments, it should be noted that changing the active instance and/or active storage element also changes which one serves as the source of the input of the next stage.

The example embodiment depicted in <FIG> also shows where the boundaries exist to describe latency through the above described pipeline stages. For instance, in this example embodiment, such boundaries for latency description are defined to be at the start of each stage instance. In this example embodiment, using this definition, delay through the selection mechanism represented as system <NUM> in <FIG> can be included with the latency of the driving stage instance rather than be part of the next stage latency. In this example embodiment, such a convention works well since the first stage (e.g., capture array stage <NUM>) latency description starts after filtering is complete, and the last stage output (e.g., an L2 sample from an active bit storage element 214a, 214b, 214c, 214d, 214e, or 214f) ends after selection multiplexer <NUM> illustrated in <FIG>.

Quantum state measurement logic system <NUM> can be associated with various technologies. For example, quantum state measurement logic system <NUM> can be associated with quantum computing technologies, quantum hardware and/or software technologies, quantum algorithm technologies, quantum simulation technologies, quantum operator sampling technologies, quantum backend computing technologies, quantum state measurement backend technologies, machine learning technologies, artificial intelligence technologies, cloud computing technologies, and/or other technologies.

Quantum state measurement logic system <NUM> can provide technical improvements to systems, devices, components, operational steps, and/or processing steps associated with the various technologies identified above. For example, quantum state measurement logic system <NUM> can: define a data processing function corresponding to at least one storage element in at least one stage of a quantum state measurement pipeline. In this example, quantum state measurement logic system <NUM> can further: define the data processing function based on one or more entity defined criteria corresponding to the quantum state measurement pipeline; and define data processing functions corresponding to storage elements in the at least one stage of the quantum state measurement pipeline to enable a defined quantity of quantum backend computing resources to capture a quantum state measurement based on quantum state measurement logic comprising the data processing functions.

In the above examples, by defining one or more data processing functions based on one or more entity defined criteria, quantum state measurement logic system <NUM> can improve a quantum state measurement backend system and/or process by enabling a compiler associated with such a system and/or process to more quickly and more efficiently identify a greater quantity of quantum backend computing resources that can capture a quantum state measurement, as such resources only have to support such one or more entity defined criteria. For instance, in embodiments where an entity as defined herein that implements quantum state measurement logic system <NUM> only wants to archive the L0 samples described above, compiler component <NUM> can more quickly and/or more efficiently identify a greater quantity of quantum backend computing resources that can capture a quantum state measurement, as such resources only have to be able to facilitate such archiving of only the L0 samples (e.g., as opposed to being able to facilitate archiving of the L0, L1, and L2 samples described above). In another example, in embodiments where such an entity wants to use a certain kernel instance or a certain discriminator instance, compiler component <NUM> can more quickly and/or more efficiently identify a greater quantity of quantum backend computing resources that can support such a certain kernel instance or such a certain discriminator instance (e.g., as opposed to being able to support various types of kernel instances or various types of discriminator instances).

Quantum state measurement logic system <NUM> can provide technical improvements to a processing unit (e.g., processor <NUM>, etc.) associated with quantum state measurement logic system <NUM>. For example, by enabling the above described compiler (e.g., compiler component <NUM>) to more quickly and/or more efficiently identify a greater quantity of quantum backend computing resources that only have to support one or more specific entity defined criteria, quantum state measurement logic system <NUM> can thereby reduce the number of processing cycles that are performed by a processing unit (e.g., processor <NUM>) in executing software (e.g., instructions, commands, processing threads, etc.) of such a compiler when performing the above described resource identification process. In this example, by reducing the number of processing cycles that are performed by such a processing unit (e.g., processor <NUM>), quantum state measurement logic system <NUM> can thereby facilitate improved performance, improved efficiency, and/or reduced computational costs associated with such a processing unit (e.g., processor <NUM>).

A practical application of quantum state measurement logic system <NUM> is that it can be implemented in a quantum state measurement backend system and/or process to capture quantum state measurements from one or more qubits that can be used to compute one or more solutions (e.g., heuristic(s), etc.) to a variety of problems ranging in complexity (e.g., an estimation problem, an optimization problem, etc.) in a variety of domains (e.g., finance, chemistry, medicine, etc.). For example, a practical application of quantum state measurement logic system <NUM> is that it can be implemented in a quantum state measurement backend system and/or process to capture quantum state measurements from one or more qubits that can be used to compute one or more solutions (e.g., heuristic(s), etc.) to an optimization problem in the domain of chemistry, medicine, and/or finance, where such a solution can be used to engineer, for instance, a new chemical compound, a new medication, and/or a new option premium.

It should be appreciated that quantum state measurement logic system <NUM> provides a new approach driven by relatively new quantum computing technologies. For example, quantum state measurement logic system <NUM> provides a new approach to identify a greater quantity of quantum backend computing resources that can capture quantum state measurement data based on one or more specific entity defined criteria.

Quantum state measurement logic system <NUM> can employ hardware or software to solve problems that are highly technical in nature, that are not abstract and that cannot be performed as a set of mental acts by a human. In some embodiments, one or more of the processes described herein can be performed by one or more specialized computers (e.g., a specialized processing unit, a specialized classical computer, a specialized quantum computer, etc.) to execute defined tasks related to the various technologies identified above. Quantum state measurement logic system <NUM> and/or components thereof, can be employed to solve new problems that arise through advancements in technologies mentioned above, employment of quantum computing systems, cloud computing systems, computer architecture, and/or another technology.

It is to be appreciated that quantum state measurement logic system <NUM> can utilize various combinations of electrical components, mechanical components, and circuitry that cannot be replicated in the mind of a human or performed by a human, as the various operations that can be executed by quantum state measurement logic system <NUM> and/or components thereof as described herein are operations that are greater than the capability of a human mind. For instance, the amount of data processed, the speed of processing such data, or the types of data processed by quantum state measurement logic system <NUM> over a certain period of time can be greater, faster, or different than the amount, speed, or data type that can be processed by a human mind over the same period of time.

According to several embodiments, quantum state measurement logic system <NUM> can also be fully operational towards performing one or more other functions (e.g., fully powered on, fully executed, etc.) while also performing the various operations described herein. It should be appreciated that such simultaneous multi-operational execution is beyond the capability of a human mind. It should also be appreciated that quantum state measurement logic system <NUM> can include information that is impossible to obtain manually by an entity, such as a human user. For example, the type, amount, and/or variety of information included in quantum state measurement logic system <NUM>, stage control register component <NUM>, and/or compiler component <NUM> can be more complex than information obtained manually by a human user.

<FIG> illustrates a flow diagram of an example, non-limiting computer-implemented method <NUM> that can facilitate quantum state measurement logic used in a quantum state measurement backend process in accordance with one or more embodiments described herein. Repetitive description of like elements and/or processes employed in respective embodiments is omitted for sake of brevity.

At <NUM>, computer-implemented method <NUM> can comprise defining, by a system (e.g., via quantum state measurement logic system <NUM> and/or stage control register component <NUM>) operatively coupled to a processor (e.g., processor <NUM>, a quantum processor, etc.), a data processing function (e.g., an archive function or a reuse function) corresponding to at least one storage element in at least one stage (e.g., capture array stage <NUM>, kernel stage <NUM>, vector pair value stage <NUM>, discriminator stage <NUM>, bit stage <NUM>, etc.) of a quantum state measurement pipeline (e.g., quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f and/or quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f). As described above with reference to the example embodiments illustrated in <FIG>, <FIG>, and <FIG>, such at least one storage element can include, but is not limited to, at least one of: capture array storage elements 206a, 206b, 206c; vector pair value storage elements 210a, 210b, 210c, 210d, 210e, 210f; and/or bit storage elements 214a, 214b, 214c, 214d, 214e, 214f. In some embodiments, at <NUM>, computer-implemented method <NUM> can further comprise defining, by the system (e.g., via quantum state measurement logic system <NUM> and/or stage control register component <NUM>), the data processing function (e.g., an archive function or a reuse function) corresponding to at least one instance in the at least one stage of the quantum state measurement pipeline, where such at least one instance can include, but is not limited to, at least one of: kernel instances, 208a, 208b, 208c; and/or discriminator instances 212a, 212b, 212c.

At <NUM>, computer-implemented method <NUM> can comprise generating, by the system (e.g., via quantum state measurement logic system <NUM> and/or compiler component <NUM>), quantum state measurement logic (e.g., quantum state measurement logic <NUM> or quantum state measurement logic <NUM>) based on data processing functions corresponding to storage elements in the at least one stage of the quantum state measurement pipeline.

At <NUM>, computer-implemented method <NUM> can comprise identifying, by the system (e.g., via quantum state measurement logic system <NUM> and/or compiler component <NUM>), one or more quantum backend computing resources (e.g., quantum based software, quantum hardware, quantum processor, superconducting circuit, quantum computer, etc.) having ability to capture a quantum state measurement based on the quantum state measurement logic.

At <NUM>, computer-implemented method <NUM> can comprise defining, by the system (e.g., via quantum state measurement logic system <NUM> and/or stage control register component <NUM>), the data processing function based on one or more entity defined criteria (e.g., the one or more entity defined criteria described above with reference to <FIG>) corresponding to the quantum state measurement pipeline.

At <NUM>, computer-implemented method <NUM> can comprise defining, by the system (e.g., via quantum state measurement logic system <NUM> and/or stage control register component <NUM>), data processing functions corresponding to storage elements in the at least one stage of the quantum state measurement pipeline to enable a defined quantity (e.g., a greater quantity as described above with reference to <FIG>) of quantum backend computing resources to capture a quantum state measurement based on quantum state measurement logic (e.g., quantum state measurement logic <NUM> or quantum state measurement logic <NUM>) comprising the data processing functions.

At <NUM>, computer-implemented method <NUM> can comprise generating, by the system (e.g., via quantum state measurement logic system <NUM> and/or stage control register component <NUM>), quantum state measurement logic (e.g., quantum state measurement logic <NUM> or quantum state measurement logic <NUM>) based on a first set of data processing functions or a second set of data processing functions, wherein the first set of data processing functions comprises a reuse function corresponding to a single storage element (e.g., bit storage element 214a, 214b, 214c, 214d, 214e, or 214f) in a bit stage (e.g., bit stage <NUM>) of the quantum state measurement pipeline and the second set of data processing functions comprises an archive function corresponding to all storage elements (e.g., bit storage element 214a, 214b, 214c, 214d, 214e, and 214f) in the bit stage, thereby facilitating reduced computational costs associated with one or more quantum backend computing resources that capture a quantum state measurement based on the quantum state measurement logic.

In an embodiment, operation <NUM> of computer-implemented method <NUM> described above can constitute collapsing a stage control register that can be generated by stage control register component <NUM> into a single bit that selects "always reuse" or "always advance" (e.g., "always archive"). It should be appreciated that such collapsing of a stage control register at operation <NUM> as described above can facilitate preservation of and/or reduced computational costs of one or more quantum backend computing resources that capture a quantum state measurement based on such first or second set of data processing functions defined above. For instance, as defined, bit stage <NUM> uses one (<NUM>) stage control register bit per data bit and that becomes wasteful as the number of measurements grows. In this example, referencing a single stage control register bit for the control of all storage elements in bit stage <NUM> can be more efficient when individual measurement control is not requested by an entity as defined herein that implements quantum state measurement logic system <NUM>.

At <NUM>, computer-implemented method <NUM> can comprise setting (e.g., via quantum state measurement logic system <NUM>, stage control register component <NUM>, compiler component <NUM>, system <NUM>, stage control register <NUM> (e.g., a stage control register generated by stage control register component <NUM>), and/or selection multiplexer <NUM>) a data processing instance (e.g., capture array storage element 206a, 206b, 206c, kernel instance 208a, 208b, 208c, vector pair value storage element 210a, 210b, 210c, 210d, 210e, 210f, discriminator instance 212a, 212b, 212c, bit storage element 214a, 214b, 214c, 214d, 214e, 214f, etc.) in a stage (e.g., capture array stage <NUM>, kernel stage <NUM>, vector pair value stage <NUM>, discriminator stage <NUM>, bit stage <NUM>, etc.) of a quantum state measurement pipeline (e.g., quantum state measurement pipelines 402a, 402b, 402c, 402d, 402e, 402f, quantum state measurement pipelines 502a, 502b, 502c, 502d, 502e, 502f, etc.) as an active data processing instance (e.g., as the data processing instance that will process a current sample of quantum state measurement data (e.g., a first L0, L1, or L2 sample)).

At <NUM>, computer-implemented method <NUM> can comprise obtaining (e.g., via quantum state measurement logic system <NUM>, a GUI or an API of quantum state measurement logic system <NUM>, filter <NUM>, system <NUM>, system <NUM>, system <NUM>, system <NUM>, etc.) a current sample of quantum state measurement data (e.g., a first L0, L1, or L2 sample).

At <NUM>, computer-implemented method <NUM> can comprise processing (e.g., via quantum state measurement logic system <NUM>, capture array storage element 206a, 206b, 206c, kernel instance 208a, 208b, 208c, vector pair value storage element 210a, 210b, 210c, 210d, 210e, 210f, discriminator instance 212a, 212b, 212c, bit storage element 214a, 214b, 214c, 214d, 214e, 214f, etc.) the current sample of quantum state measurement data using the active data processing instance.

At <NUM>, computer-implemented method <NUM> can comprise determining (e.g., via quantum state measurement logic system <NUM>, stage control register component <NUM>, compiler component <NUM>, system <NUM>, stage control register <NUM> (e.g., a stage control register generated by stage control register component <NUM>), and/or selection multiplexer <NUM>) whether to reuse the active data processing instance to process a subsequent sample of quantum state measurement data (e.g., a second L0, L1, or L2 sample).

If it is determined at <NUM> that the active data processing instance will be reused to process a subsequent sample of quantum state measurement data (e.g., a second L0, L1, or L2 sample), at <NUM>, computer-implemented method <NUM> can comprise obtaining (e.g., via quantum state measurement logic system <NUM>, a GUI or an API of quantum state measurement logic system <NUM>, filter <NUM>, system <NUM>, system <NUM>, system <NUM>, system <NUM>, etc.) the subsequent sample of quantum state measurement data.

At <NUM>, computer-implemented method <NUM> can comprise overlaying (e.g., via quantum state measurement logic system <NUM>, capture array storage element 206a, 206b, 206c, kernel instance 208a, 208b, 208c, vector pair value storage element 210a, 210b, 210c, 210d, 210e, 210f, discriminator instance 212a, 212b, 212c, bit storage element 214a, 214b, 214c, 214d, 214e, 214f, etc.) the current sample of quantum state measurement data in the active data processing instance with the subsequent sample of quantum measurement data.

If it is determined at <NUM> that the active data processing instance will not be reused to process a subsequent sample of quantum state measurement data (e.g., a second L0, L1, or L2 sample), at <NUM>, computer-implemented method <NUM> can comprise preserving (e.g., archiving via quantum state measurement logic system <NUM>, capture array storage element 206a, 206b, 206c, kernel instance 208a, 208b, 208c, vector pair value storage element 210a, 210b, 210c, 210d, 210e, 210f, discriminator instance 212a, 212b, 212c, bit storage element 214a, 214b, 214c, 214d, 214e, 214f, etc.) the current sample of quantum state measurement data in the active data processing instance.

At <NUM>, computer-implemented method <NUM> can comprise setting (e.g., via quantum state measurement logic system <NUM>, stage control register component <NUM>, compiler component <NUM>, system <NUM>, stage control register <NUM> (e.g., a stage control register generated by stage control register component <NUM>), and/or selection multiplexer <NUM>) another data processing instance (e.g., the next data processing instance in line) in the stage of the quantum state measurement pipeline as the active data processing instance (e.g., setting capture array storage element 206b or 206c, kernel instance 208b or 208c, vector pair value storage element 210b, 210c, 210d, 210e, or 210f, discriminator instance 212b or 212c, and/or bit storage element 214b, 214c, 214d, 214e, or 214f as the active data processing instance).

In some embodiments, computer-implemented method <NUM> can comprise repeating operations <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and/or operations <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> can be repeated until all quantum state measurements of one or more qubits have been captured by one or more quantum backend computing resources.

For simplicity of explanation, the computer-implemented methodologies are depicted and described as a series of acts. It is to be understood and appreciated that the subject innovation is not limited by the acts illustrated and/or by the order of acts, for example acts can occur in various orders and/or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts can be required to implement the computer-implemented methodologies in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the computer-implemented methodologies could alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it should be further appreciated that the computer-implemented methodologies disclosed hereinafter and throughout this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methodologies to computers. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage media.

In order to provide a context for the various aspects of the disclosed subject matter, <FIG> as well as the following discussion are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented. <FIG> illustrates a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

With reference to <FIG>, a suitable operating environment <NUM> for implementing various aspects of this disclosure can also include a computer <NUM>. The computer <NUM> can also include a processing unit <NUM>, a system memory <NUM>, and a system bus <NUM>. The system bus <NUM> couples system components including, but not limited to, the system memory <NUM> to the processing unit <NUM>. The processing unit <NUM> can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit <NUM>. The system bus <NUM> can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE <NUM>), and Small Computer Systems Interface (SCSI).

The system memory <NUM> can also include volatile memory <NUM> and nonvolatile memory <NUM>. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer <NUM>, such as during start-up, is stored in nonvolatile memory <NUM>. Computer <NUM> can also include removable/non-removable, volatile/non-volatile computer storage media. <FIG> illustrates, for example, a disk storage <NUM>. Disk storage <NUM> can also include, but is not limited to, devices like a magnetic disk drive, floppy disk drive, tape drive, Jaz drive, Zip drive, LS-<NUM> drive, flash memory card, or memory stick. The disk storage <NUM> also can include storage media separately or in combination with other storage media. To facilitate connection of the disk storage <NUM> to the system bus <NUM>, a removable or non-removable interface is typically used, such as interface <NUM>. <FIG> also depicts software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment <NUM>. Such software can also include, for example, an operating system <NUM>. Operating system <NUM>, which can be stored on disk storage <NUM>, acts to control and allocate resources of the computer <NUM>.

System applications <NUM> take advantage of the management of resources by operating system <NUM> through program modules <NUM> and program data <NUM>, e.g., stored either in system memory <NUM> or on disk storage <NUM>. It is to be appreciated that this disclosure can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer <NUM> through input device(s) <NUM>. Input devices <NUM> include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit <NUM> through the system bus <NUM> via interface port(s) <NUM>. Interface port(s) <NUM> include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s) <NUM> use some of the same type of ports as input device(s) <NUM>. Thus, for example, a USB port can be used to provide input to computer <NUM>, and to output information from computer <NUM> to an output device <NUM>. Output adapter <NUM> is provided to illustrate that there are some output devices <NUM> like monitors, speakers, and printers, among other output devices <NUM>, which require special adapters. The output adapters <NUM> include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device <NUM> and the system bus <NUM>. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s) <NUM>.

Computer <NUM> can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) <NUM>. The remote computer(s) <NUM> can be a computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node and the like, and typically can also include many or all of the elements described relative to computer <NUM>. For purposes of brevity, only a memory storage device <NUM> is illustrated with remote computer(s) <NUM>. Remote computer(s) <NUM> is logically connected to computer <NUM> through a network interface <NUM> and then physically connected via communication connection <NUM>. Network interface <NUM> encompasses wire and/or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL). Communication connection(s) <NUM> refers to the hardware/software employed to connect the network interface <NUM> to the system bus <NUM>. While communication connection <NUM> is shown for illustrative clarity inside computer <NUM>, it can also be external to computer <NUM>. The hardware/software for connection to the network interface <NUM> can also include, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

Referring now to <FIG>, an illustrative cloud computing environment <NUM> is depicted. As shown, cloud computing environment <NUM> includes one or more cloud computing nodes <NUM> with which local computing devices used by cloud consumers, such as, for example, personal digital assistant (PDA) or cellular telephone 1154A, desktop computer 1154B, laptop computer 1154C, and/or automobile computer system 1154N may communicate. Although not illustrated in <FIG>, cloud computing nodes <NUM> can further comprise a quantum platform (e.g., quantum computer, quantum hardware, quantum software, etc.) with which local computing devices used by cloud consumers can communicate. It is understood that the types of computing devices 1154A-N shown in <FIG> are intended to be illustrative only and that computing nodes <NUM> and cloud computing environment <NUM> can communicate with any type of computerized device over any type of network and/or network addressable connection (e.g., using a web browser).

In some embodiments, software components include network application server software <NUM>, database software <NUM>, quantum platform routing software (not illustrated in <FIG>), and/or quantum software (not illustrated in <FIG>).

Workloads layer <NUM> provides examples of functionality for which the cloud computing environment may be utilized. Non-limiting examples of workloads and functions which may be provided from this layer include: mapping and navigation <NUM>; software development and lifecycle management <NUM>; virtual classroom education delivery <NUM>; data analytics processing <NUM>; transaction processing <NUM>; and quantum state measurement logic software <NUM>.

The present invention may be a system, a method, an apparatus and/or a computer program product at any possible technical detail level of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.

These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and/or computers, those skilled in the art will recognize that this disclosure also can or can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and/or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be practiced in distributed computing environments in which tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices. For example, in one or more embodiments, computer executable components can be executed from memory that can include or be comprised of one or more distributed memory units. As used herein, the term "memory" and "memory unit" are interchangeable. Further, one or more embodiments described herein can execute code of the computer executable components in a distributed manner, e.g., multiple processors combining or working cooperatively to execute code from one or more distributed memory units. As used herein, the term "memory" can encompass a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

As used in this application, the terms "component," "system," "platform," "interface," and the like, can refer to and/or can include a computer-related entity or an entity related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In another example, respective components can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other means to execute software or firmware that confers at least in part the functionality of the electronic components. In an aspect, a component can emulate an electronic component via a virtual machine, e.g., within a cloud computing system.

As it is employed in the subject specification, the term "processor" can refer to substantially any computing processing unit or device comprising, but not limited to, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor can also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," data storage," "database," and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to "memory components," entities embodied in a "memory," or components comprising a memory. It is to be appreciated that memory and/or memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM). Volatile memory can include RAM, which can act as external cache memory, for example. By way of illustration and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, without being limited to including, these and any other suitable types of memory.

What has been described above include mere examples of systems and computer-implemented methods. It is, of course, not possible to describe every conceivable combination of components or computer-implemented methods for purposes of describing this disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of this disclosure are possible. Furthermore, to the extent that the terms "includes," "has," "possesses," and the like are used in the detailed description, claims, appendices and drawings such terms are intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim.

Claim 1:
A system (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>), comprising:
a memory (<NUM>) that stores computer executable components; and
a processor (<NUM>) that executes the computer executable components stored in the memory (<NUM>), wherein the computer executable components comprise:
a stage control register component (<NUM>) that defines a data processing function corresponding to at least one storage element (206a, 206b, 206c) in at least one stage of a quantum state measurement pipeline (<NUM>, 402a, 402b, 402c, 402d, 402e, 402f, 502a, 502b, 502c, 502d, 502e, 502f),
a compiler component (<NUM>) that generates quantum state measurement logic based on a first set of data processing functions or a second set of data processing functions, and wherein the first set of data processing functions comprises a reuse function corresponding to a single storage element (206a, 206b, 206c) in a bit stage (<NUM>) of the quantum state measurement pipeline (<NUM>, 402a, 402b, 402c, 402d, 402e, 402f, 502a, 502b, 502c, 502d, 502e, 502f) and the second set of data processing functions comprises an archive function corresponding to all storage elements (206a, 206b, 206c) in the bit stage (<NUM>), thereby facilitating reduced computational costs associated with one or more quantum backend computing resources that capture a quantum state measurement based on the quantum state measurement logic,
wherein bits of each stage control register generated by the stage control register component (<NUM>) determine, as each measurement is taken, whether to switch to the next storage element (206a, 206b, 206c) in the stage or reuse the current storage element (206a, 206b, 206c) after the measurement is complete.