Patent Description:
A light emitting element may have relatively satisfactory durability even under poor environmental conditions, and have excellent performances in terms of lifetime and luminance. Recently, research on the technology of applying such light emitting elements to various display devices has become appreciably more active.

As a part of such research, technologies of manufacturing an LED having a small size corresponding to the micrometer scale or the nanometer scale using an inorganic crystalline structure, e.g., a structure obtained by growing a nitride-based semiconductor are being developed.

<CIT> discloses a pixel, a display device including the pixel, and a method of fabricating the display device wherein a pixel defect resulting from a short-circuit defect, of a light emitting element may be efficiently repaired. <CIT> discloses a configuration of a display apparatus. <CIT> discloses a pixel structure of a display apparatus including an electrode line, at least one ultra-small light emitting diode, and a connection electrode.

Various embodiments of the present disclosure are directed to a display device having enhanced light efficiency, and a method of manufacturing the display device.

The present invention relates to a display device and a method of manufacturing a display device as defined in the appended claims.

A display device and a method of manufacturing the display device in accordance with the present disclosure may have the following effects.

First, light emitted from a light emitting element may be reflected toward a capping layer through a reflective pattern disposed on a bank. Hence, the light efficiency may be enhanced.

Second, a pixel circuit layer, a display element layer, and a light conversion pattern layer all are disposed on the base layer. Therefore, a light path along which light emitted from the light emitting element is emitted to the.

In an embodiment, the partition wall and the bank may be disposed on respective different layers.

In an embodiment, the first electrode and the second electrode may include an identical material provided on a layer identical with a layer on which the reflective pattern is disposed.

In an embodiment, the first electrode and the second electrode may be disposed on a layer different from a layer on which the reflective pattern is disposed.

In an embodiment, the pixel circuit layer may include: at least one transistor disposed on the base layer; and a passivation layer provided on the transistor.

In an embodiment, the passivation layer may be integrally formed with the partition wall and the bank.

In an embodiment, the sub-pixel may include a light conversion pattern layer disposed in space defined by the bank and including color conversion particles converting the light into a specific color of light.

In an embodiment, the display device may include a capping layer disposed on the light conversion pattern layer to overlap with the display area.

In an embodiment, the light conversion pattern layer may further include a color filter.

A method of manufacturing a display device in accordance with an embodiment of the present disclosure include: providing a base layer including a plurality of sub-pixels; and forming a pixel circuit layer on the base layer and forming a display element layer on the pixel circuit layer. Forming the display element layer includes: forming a partition wall in each of the sub-pixels; forming a bank between the sub-pixels adjacent to each other; forming a first electrode and a second electrode spaced apart from each other on the partition wall; forming a reflective pattern on the bank; and forming at least one light emitting element disposed between the first electrode and the second electrode and configured to emit light.

In an embodiment, forming the reflective pattern may include forming the reflective pattern such that the reflective pattern encloses an upper surface and a side surface of the bank.

In an embodiment, the partition wall and the bank may be formed on an identical layer through an identical process.

In an embodiment, the partition wall and the bank may be formed on respective different layers through respective different processes.

In an embodiment, the first electrode and the second electrode may be formed on an identical layer through a process identical with a process of forming the reflective pattern.

In an embodiment, the first electrode and the second electrode may be formed on a layer different from the reflective pattern through a process different from a process of forming the reflective pattern.

In an embodiment, forming the at least one light emitting element may include aligning at least one light emitting element between the first electrode and the second electrode by applying corresponding alignment voltages to the first electrode and the second electrode, respectively.

In an embodiment, the method may further include forming, in space defined by the bank in the sub-pixel, a light conversion pattern layer including color conversion particles converting the light to a specific color of light.

Second, a pixel circuit layer, a display element layer, and a light conversion pattern layer all are disposed on the base layer. Therefore, a light path along which light emitted from the light emitting element is emitted to the outside through a capping layer is reduced, so that light loss may be minimized.

<FIG> display embodiments showing certain aspects of the invention, and <FIG> display embodiments of the invention as claimed.

Like components will be designated by like reference symbols. Furthermore, it should be noted that the drawings may be exaggerated in thickness, ratio, and dimension of components for descriptive convenience and clarity only. The term "and/or" may include any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For instance, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, the second element could also be termed the first element. In the present disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Also, the terms "under", "below", "above", "upper", and the like are used herein for explaining the relationship between one or more components illustrated in the drawings. These terms may be relative terms describing the positions of components in the drawings, but the positions of components are not limited thereto.

It will be further understood that the terms "comprise", "include", "have", etc. when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations of them but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof.

<FIG> is a perspective view illustrating a light emitting element in accordance with an embodiment of the present disclosure.

As illustrated in <FIG>, a light emitting element LD in accordance with an embodiment of the present disclosure may include a first conductive semiconductor layer <NUM>, a second conductive semiconductor layer <NUM>, and an active layer <NUM> interposed between the first conductive semiconductor layer <NUM> and the second conductive semiconductor layer <NUM>.

For example, the light emitting element LD may have a structure formed by successively stacking the first conductive semiconductor layer <NUM>, the active layer <NUM>, and the second conductive semiconductor layer <NUM>. The light emitting element LD may be provided in a rod shape extending in one direction. Here, the words "rod shape" may embrace a rod-like shape or a bar-like shape extending in a longitudinal direction (L) (i.e., having an aspect ratio greater than <NUM>).

The light emitting element LD may have a rod shape formed by successively stacking the first conductive semiconductor layer <NUM>, the active layer <NUM>, and the second conductive semiconductor layer <NUM> in the longitudinal direction (L) of the light emitting element LD, and have a first end and a second end based on the active layer <NUM>. One of the first and second conductive semiconductor layers <NUM> and <NUM> may be disposed on the first end of the light emitting element LD, and the other of the first and second conductive semiconductor layers <NUM> and <NUM> may be disposed on the second end.

The light emitting element LD may be manufactured in a small size having a diameter and/or length corresponding to, e.g., a micro-scale or nano-scale size. However, the size of the light emitting element LD in accordance with an embodiment of the present disclosure is not limited to this, and the size of the light emitting element LD may be changed to satisfy requirements for the display device to which the light emitting element LD is applied.

The first conductive semiconductor layer <NUM> may include, for example, at least one n-type semiconductor layer. For instance, the first conductive semiconductor layer <NUM> may include a semiconductor layer which includes any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a first conductive dopant such as Si, Ge, or Sn. The material forming the first conductive semiconductor layer <NUM> is not limited to this, and the first conductive semiconductor layer <NUM> may be formed of various other materials.

The active layer <NUM> may be formed on the first conductive semiconductor layer <NUM> and have a single or multiple quantum well structure. In accordance with an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed on and/or under the active layer <NUM>. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In addition, material such as AlGaN or AlInGaN may be employed to form the active layer <NUM>.

If an electric field having a predetermined voltage or more is applied to the opposite ends of the light emitting element LD, the light emitting element LD emits light by coupling of electron-hole pairs in the active layer <NUM>.

The second conductive semiconductor layer <NUM> may be provided on the active layer <NUM> and include a semiconductor layer of a type different from that of the first conductive semiconductor layer <NUM>. For example, the second conductive semiconductor layer <NUM> may include at least one p-type semiconductor layer. For instance, the second conductive semiconductor layer <NUM> may include a semiconductor layer which includes any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a second conductive dopant such as Mg. The material forming the second conductive semiconductor layer <NUM> is not limited to this, and the second conductive semiconductor layer <NUM> may be formed of various other materials.

In accordance with an embodiment of the present disclosure, the light emitting element LD may not only include the first conductive semiconductor layer <NUM>, the active layer <NUM>, and the second conductive semiconductor layer <NUM>, but may also include a fluorescent layer, another active layer, another semiconductor layer, and/or an electrode layer provided on and/or under each layer. For example, the light emitting element LD may include an electrode layer disposed on the second conductive semiconductor layer <NUM>.

The light emitting element LD may further include an insulating film <NUM>. In an embodiment of the present disclosure, the insulating film <NUM> may be omitted, or may be provided to cover only some of the first conductive semiconductor layer <NUM>, the active layer <NUM>, and the second conductive semiconductor layer <NUM>.

For example, the insulating film <NUM> may be provided on a portion of the light emitting element LD, other than the opposite ends thereof, so that the opposite ends of the light emitting element LD may be exposed. Although in <FIG> there is illustrated the insulating film <NUM> from which a portion thereof has been removed for the sake of explanation, the light emitting element LD may be formed such that the entirety of the side surface of the cylindrical body thereof is enclosed by the insulating film <NUM>.

The insulating film <NUM> may be provided to enclose at least a portion of an outer circumferential surface of the first conductive semiconductor layer <NUM>, the active layer <NUM>, and/or the second conductive semiconductor layer <NUM>. For example, the insulating film <NUM> may be provided to enclose at least the outer circumferential surface of the active layer <NUM>.

In accordance with an embodiment of the present disclosure, the insulating film <NUM> may include a transparent insulating material. For example, the insulating film <NUM> may include at least one insulating material selected from the group consisting of SiO<NUM>, Si<NUM>N<NUM>, Al<NUM>O<NUM>, and TiO<NUM>, but the present disclosure is not limited thereto. In other words, various materials having insulating properties may be employed.

If the insulating film <NUM> is provided on the light emitting element LD, the active layer <NUM> may be prevented from short-circuiting with a first and/or second electrode (not illustrated).

Thanks to the insulating layer <NUM>, occurrence of a defect on the surface of the light emitting element LD may be minimized, whereby the lifetime and efficiency of the light emitting element LD may be improved. In the case where a plurality of light emitting elements LD are disposed in close contact with each other, the insulating layer <NUM> may prevent an undesired short-circuit from occurring between the light emitting elements LD adjacent to each other.

The light emitting element LD may be employed as a light source for various display devices. For example, the light emitting element LD may be used in a lighting device or a self-emissive display device.

Hereinafter, the display device including the light emitting element LD in accordance with an embodiment of the present disclosure will be described in detail.

<FIG> illustrates a display device in accordance with an embodiment of the present disclosure, and is a schematic plan view illustrating a display device using the light emitting element illustrated in <FIG> as a light emitting source.

For the sake of explanation, <FIG> schematically illustrates the structure of the display device, focused on a display area DA on which an image is displayed. In some embodiments, although not illustrated, at least one driving circuit (e.g., a scan driver and a data driver) and/or a plurality of signal lines may be further provided in the display device.

Referring to <FIG> and <FIG>, the display device in accordance with the embodiment of the present disclosure may include a base layer BSL, a plurality of pixels PXL provided on the base layer BSL and each including at least one light emitting element LD, a driver (not illustrated) provided on the base layer BSL and configured to drive the pixels PXL, and a line component (not illustrated) provided to couple the pixels PXL with the driver.

The display device may be classified into a passive-matrix type display device and an active-matrix type display device according to a method of driving the light emitting element LD. In the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD, and a switching transistor configured to transmit data signals to the driving transistor.

Recently, active-matrix type display devices capable of selectively turning on each pixel PXL taking into account the resolution, the contrast, and the working speed have been mainstreamed. However, the present disclosure is not limited thereto. For example, passive-matrix type display devices in which pixels PXL may be turned on by groups may also employ components (e.g., first and second electrodes) for driving the light emitting element LD.

The base layer BSL may be a substrate of the display device, and include a display area DA and a non-display area NDA. The display area DA may be an area in which the pixels PXL for displaying an image are provided. The non-display area NDA may be an area in which the driver for driving the pixels PXL and some of the line component for coupling the pixels PXL to the driver are provided.

Although in the drawing there is illustrated an example where the display area DA is disposed in a central area of the display device and the non-display area NDA is disposed in a perimeter area of the display device to enclose the display area DA, the present disclosure is not limited thereto, and the locations thereof may be changed.

The display area DA may have various shapes. For example, the display area DA may be provided in various forms such as a closed polygon including sides formed of linear lines, a circle, an ellipse or the like including a side formed of a curved line, and a semicircle, a semi-ellipse or the like including sides formed of a linear line and a curved line. The non-display area NDA may be provided on at least one side of the display area DA. Although in the drawing there is illustrated a structure in which the non-display area NDA encloses the display area DA, the present disclosure is not limited thereto.

The base layer BSL may be a rigid substrate or a flexible substrate, and the present disclosure is not limited thereto. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. Furthermore, the base layer BSL may be a transparent substrate, but it is not limited thereto. In addition, the base layer BSL may be a translucent substrate, an opaque substrate, or a reflective substrate.

The pixels PXL may be provided in the display area DA on the base layer BSL. Each of the pixels PXL refers to a smallest unit for displaying an image, and a plurality of pixels may be provided.

Each of the pixels PXL may include a light emitting element LD configured to be driven in response to a scan signal and a data signal. The light emitting element LD may have a small size corresponding to the nanometer scale or the micrometer scale, and be coupled in parallel to light emitting elements LD disposed adjacent thereto. The light emitting element LD may form a light source of the corresponding pixel PXL.

Furthermore, each of the pixels PXL may include a plurality of sub-pixels SP1, SP2, and SP3. For example, each pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 which are configured to emit different colors of light. For instance, the first sub-pixel SP1 may be a red sub-pixel configured to emit red light, the second sub-pixel SP2 may be a green sub-pixel configured to emit green light, and the third sub-pixel SP3 may be a blue sub-pixel configured to emit blue light. However, the color, type, and/or number of sub-pixels that form each pixel PXL are not limited to the foregoing examples.

Although <FIG> illustrates that the pixels PXL are disposed in the display area DA in the form of a matrix in a first direction DR1 and a second direction DR2 different from the first direction DR1, the disposition of the pixels PXL may be changed in various ways without being limited to the foregoing example. Furthermore, disposition of the plurality of sub-pixels of each of the pixels PXL may also be changed in various ways.

The driver may provide a driving signal to each pixel PXL through the line component and thus control the operation of the pixel PXL. In <FIG>, the line component is omitted for the convenience sake of explanation.

The driver may include a scan driver configured to provide scan signals to the pixels PXL through scan lines, an emission driver configured to provide emission control signals to the pixels PXL through emission control lines, a data driver configured to provide data signals to the pixels PXL through data lines, and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

<FIG> are circuit diagrams illustrating examples of a unit light emitting area of the display device of <FIG> in accordance with various embodiments.

Referring to <FIG>, each of the first to third sub-pixels may be configured of an active pixel. However, the type, the configuration, and/or the driving method of each of the first to third sub-pixels is not particularly limited. For example, each of the first to third sub-pixels may be configured of a pixel of a passive or active display device which can have various known structures.

Furthermore, referring to <FIG>, the first to third sub-pixels may have substantially the same structure or similar structures. Hereinafter, for convenience sake, the first sub-pixel of the first to third sub-pixels will be described as a representative example.

Referring to <FIG>, <FIG>, and <FIG>, the first sub-pixel SP1 may include an emission area EMA configured to generate light having a luminance corresponding to a data signal, and a pixel driving circuit <NUM> configured to drive the emission area EMA.

In an embodiment, the emission area EMA may include a plurality of light emitting elements LD coupled in parallel to each other between a first driving power supply VDD and a second driving power supply VSS. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set as a high-potential power supply, and the second driving power supply VSS may be set as a low-potential power supply. Here, a difference in potential between the first and second driving power supplies VDD and VSS may be set to a threshold voltage of the light emitting elements LD or more during an emission period of the first sub-pixel SP1.

A first electrode (e.g., an anode electrode) of each of the light emitting elements LD may be coupled to the first driving power supply VDD via the pixel driving circuit <NUM>. A second electrode (e.g., a cathode electrode) of each of the light emitting elements LD may be coupled to the second driving power supply VSS. Each of the light emitting elements LD may emit light at a luminance corresponding to driving current that is controlled by the pixel driving circuit <NUM>.

Although <FIG> illustrate that the light emitting elements LD are coupled in parallel to each other in the same direction (e.g., a forward direction) between the first and second driving power supplies VDD and VSS, the present disclosure is not limited thereto. For example, some of the light emitting elements LD may be coupled to each other in the forward direction between the first and second driving power supplies VDD and VSS, and the other light emitting elements LD may be coupled to each other in the reverse direction.

One of the first and second driving power supplies VDD and VSS may be supplied in the form of an AC voltage. In this case, the light emitting elements LD may alternately emit light by the same connection direction groups. Alternatively, the first sub-pixel SP1 may include only a single light emitting element LD.

The pixel driving circuit <NUM> may include first and second transistors T1 and T2, and a storage capacitor Cst. The structure of the pixel driving circuit <NUM> is not limited to that of the embodiment illustrated in <FIG>.

A first electrode of the first transistor (T1; switching transistor) is coupled to a data line Dj, and a second electrode thereof is coupled to a first node N1. Here, the first electrode and the second electrode of the first transistor T1 may be different electrodes. If the first electrode is a source electrode, the second electrode is a drain electrode. A gate electrode of the first transistor T1 is coupled to the scan line Si.

When a scan signal having a voltage (e.g., a low-level voltage) capable of turning on the first transistor T1 is supplied from the scan line Si, the first transistor T1 is turned on to electrically couple the data line Dj with the first node N1. Here, a data signal of a corresponding frame is supplied to the data line Dj, whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged to the storage capacitor Cst.

A first electrode of the second transistor (T2; driving transistor) is coupled to the first driving power supply VDD, and a second electrode of the second transistor (T2; driving transistor) is electrically coupled to the first electrode of each of the light emitting elements LD. A gate electrode of the second transistor T2 is coupled to the first node N1. As such, the second transistor T2 may control the amount of driving current to be supplied to the light emitting elements LD in response to the voltage of the first node N1.

One electrode of the storage capacitor Cst is coupled to the first driving power supply VDD, and the other electrode thereof is coupled to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to a data signal supplied to the first node N1, and maintains the charged voltage until a data signal of a subsequent frame is supplied.

For the sake of explanation, <FIG> illustrates the pixel driving circuit <NUM> having a relatively simple structure including the first transistor T1 configured to transmit the data signal to the first sub-pixel SP1, the storage capacitor Cst configured to store the data signal, and the second transistor T2 configured to supply driving current corresponding to the data signal to the light emitting elements LD.

However, the present disclosure is not limited thereto, and the structure of the pixel driving circuit <NUM> may be changed in various ways. For example, the pixel driving circuit <NUM> may further include at least one transistor element such as a transistor element configured to compensate for the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and/or a transistor element configured to control an emission time of the light emitting elements LD, or other circuit elements such as a boosting capacitor for boosting the voltage of the first node N1.

Furthermore, although <FIG> illustrates that the transistors, e.g., the first and second transistors T1 and T2, included in the pixel driving circuit <NUM> are formed of P-type transistors, the type of the transistor is not limited thereto. For example, at least one of the first and second transistors T1 and T2 included in the pixel driving circuit <NUM> may be an N-type transistor.

As illustrated in <FIG>, the pixel driving circuit <NUM> may further include a third transistor T3 as well as including the first and second transistors T1 and T2. The third transistor T3 may be coupled between the j-th data line Dj and the anode electrode of each of the light emitting elements LD. The gate electrode of the third transistor T3 may be coupled to the control line CLi so that the third transistor T3 may be turned on when a control signal is supplied to the control line CLi, and be turned off in other cases.

For convenience sake, <FIG> illustrates that all of the first to third transistors T1 to T3 are formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to third transistors T1 to T3 included in the pixel driving circuit <NUM> may be formed of an N-type transistor, or all of the first to third transistors T1 to T3 may be N-type transistors.

Next, referring to <FIG>, <FIG>, and <FIG>, the first and second transistors T1 and T2 may be N-type transistors. The configuration and operation of the driving circuit <NUM> illustrated in <FIG>, other than a change in connection positions of some components due to a change in the type of transistor, are similar to those of the pixel driving circuit <NUM> of <FIG>. Therefore, detailed descriptions pertaining to this will be omitted.

Referring to <FIG>, <FIG>, and <FIG>, the pixel driving circuit <NUM> may be coupled to the scan line Si and the data line Dj of the first sub-pixel SP1. For example, if the first sub-pixel SP1 is disposed on an i-th row and a j-th column of the display area DA, the pixel driving circuit <NUM> of the first sub-pixel SP1 may be coupled to an i-th scan line Si and a j-th data line Dj of the display area DA.

Furthermore, the pixel driving circuit <NUM> may also be coupled to at least one other scan line. For example, the first sub-pixel SP1 disposed on the i-th row of the display area DA may be further coupled to an i-<NUM>-th scan line Si-<NUM> and/or an i+<NUM>-th scan line Si+<NUM>.

The pixel driving circuit <NUM> may be coupled not only to the first and second driving power supplies VDD and VSS but also to a third power supply. For example, the pixel driving circuit <NUM> may also be coupled to an initialization power supply Vint.

The pixel driving circuit <NUM> may include first to seventh transistors T1 to T7, and a storage capacitor Cst.

A first electrode of the first transistor (T1; driving transistor), e.g., a source electrode, may be coupled to the first driving power supply VDD via the fifth transistor T5, and a second electrode thereof, e.g., a drain electrode, may be coupled to one ends of light emitting elements LD via the sixth transistor T6. A gate electrode of the first transistor T1 may be coupled to a first node N1. The first transistor T1 may control driving current flowing between the first driving power supply VDD and the second driving power supply VSS via the light emitting elements LD in response to the voltage of the first node N1.

The second transistor (T2; switching transistor) may be coupled between the j-th data line Dj coupled to the first sub-pixel SP1 and the source electrode of the first transistor T1. A gate electrode of the second transistor T2 is coupled to the i-th scan line Si coupled to the first sub-pixel SP1. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si, the second transistor T2 is turned on to electrically couple the j-th data line Dj to the source electrode of the first transistor T1. Hence, if the second transistor T2 is turned on, a data signal supplied from the j-th data line Dj may be transmitted to the first transistor T1.

The third transistor T3 is coupled between the drain electrode of the first transistor T1 and the first node N1. A gate electrode of the third transistor T3 is coupled to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the third transistor T3 is turned on to electrically couple the drain electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. A gate electrode of the fourth transistor T4 is coupled to a preceding scan line, e.g., an i-<NUM>-th scan line Si-<NUM>. When a scan signal of a gate-on voltage is supplied to the i-<NUM>-th scan line Si-<NUM>, the fourth transistor T4 is turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the initialization power supply Vint may have a voltage equal to or less than the minimum voltage of the data signal.

The fifth transistor T5 is coupled between the first driving power supply VDD and the first transistor T1. A gate electrode of the fifth transistor T5 is coupled to a corresponding emission control line, e.g., an i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

The sixth transistor T6 is coupled between the first transistor T1 and first ends of the light emitting elements LD. A gate electrode of the sixth transistor T6 may be coupled to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

The seventh transistor T7 is coupled between the first ends of the light emitting elements LD and the initialization power supply Vint. A gate electrode of the seventh transistor T7 is coupled to any one of scan lines of a subsequent stage, e.g., to the i+<NUM>-th scan line Si+<NUM>. When a scan signal of a gate-on voltage is supplied to the i+<NUM>-th scan line Si+<NUM>, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first ends of the light emitting elements LD.

The storage capacitor Cst is coupled between the first driving power supply VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding both to the data signal applied to the first node N1 during each frame period and to the threshold voltage of the first transistor T1.

For convenience sake, <FIG> illustrates that all of the first to seventh transistors T1 to T7 are formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 included in the pixel driving circuit <NUM> may be formed of an N-type transistor, or all of the first to seventh transistors T1 to T7 may be N-type transistors.

Hereinafter, the pixel of the display device of <FIG> will be described in detail with reference to the accompanying drawings.

<FIG> is a plan view schematically illustrating first to third sub-pixels included in one of the pixels illustrated in <FIG>. <FIG> is a diagram illustrating a bank and a reflective pattern of <FIG>. <FIG> is a sectional view taken along line I-I' of <FIG>.

Although, for the sake of explanation, <FIG> illustrates that a plurality of light emitting elements LD provided in each sub-pixel are horizontally aligned, the arrangement of the light emitting elements LD is not limited thereto. For example, at least some of the light emitting elements LD may be aligned in a direction intersecting with the horizontal direction. Furthermore, for the sake of explanation, illustration of transistors coupled to the light emitting elements LD, and signal lines coupled to the transistors has been omitted in <FIG>. Moreover, although <FIG> and <FIG> illustrate a simplified structure of the one pixel PXL, e.g., showing that each electrode has only a single electrode layer, the present disclosure is not limited thereto.

Referring to <FIG>, the display device in accordance with an embodiment of the present disclosure may include a base layer BSL on which a plurality of pixels PXL are provided.

Each of the pixels PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 which are provided on the base layer BSL. In an embodiment of the present disclosure, the first sub-pixel SP1 may be a red sub-pixel configured to emit red light, the second sub-pixel SP2 may be a green sub-pixel configured to emit green light, and the third sub-pixel SP3 may be a blue sub-pixel configured to emit blue light.

Each of the first to third sub-pixels SP1 to SP3 may include an emission area EMA configured to emit light, and a non-emission area PPA disposed around a perimeter of the emission area EMA.

Each of the first to third sub-pixels SP1 to SP3 may include a base layer BSL, a pixel circuit layer PCL, and a display element layer DPL.

The pixel circuit layer PCL may include a buffer layer BFL disposed on the base layer BSL, first and second transistors T1 and T2 disposed on the buffer layer BFL, and a driving voltage line DVL. Furthermore, the pixel circuit layer PCL of each of the first to third sub-pixels SP1 to SP3 may further include a passivation layer PSV which is disposed on the first and second transistors T1 and T2 and the driving voltage line DVL.

The base layer BSL may be a rigid or flexible substrate, and the material or properties thereof are not particularly limited. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer BSL may be a transparent substrate, but the present disclosure is not limited thereto, and the base layer BSL may be a translucent substrate, an opaque substrate, or a reflective substrate. Furthermore, although in the drawings there is illustrated the case where the base layer BSL has a single-layer structure, the base layer BSL may have a multilayer structure.

The buffer layer BFL may prevent impurities from being diffused into the first and second transistors T1 and T2. The buffer layer BFL may be omitted depending on the material of the substrate SUB or processing conditions.

The first transistor T1 may be electrically coupled with some of the light emitting elements LD provided on the display element layer DPL of the corresponding sub-pixel. In this case, the first transistor T1 may be a driving transistor configured to drive the light emitting elements LD. The second transistor T2 may be a switching transistor configured to switch the first transistor T1.

Each of the first and second transistors T1 and T2 may include a semiconductor layer SCL, a gate electrode GE, a source electrode SE, and a drain electrode DE.

The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a source area which comes into contact with the source electrode SE, and a drain area which comes into contact with the drain electrode DE. An area between the source area and the drain area may be a channel area.

The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel area may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the source area and the drain area may be a semiconductor pattern doped with an impurity.

The gate electrode GE may be provided on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. The source electrode SE and the drain electrode DE may respectively come into contact with the source area and the drain area of the semiconductor layer SCL through corresponding contact holes which pass through an interlayer insulating layer ILD and the gate insulating layer GI.

In the drawings, although the first and second transistors T1 and T2 are LTPS thin-film transistors, the first and second transistors T1 and T2 are not limited thereto.

Furthermore, although in the drawings the driving voltage line DVL is illustrated as being disposed on the interlayer insulating layer ILD, the location of the driving voltage line DVL is not limited thereto. For example, the driving voltage line DVL may be disposed on any one of the insulating layers included in the pixel circuit layer PCL. The second driving power supply (refer to VSS of <FIG>) may be applied to the driving voltage line DVL.

The passivation layer PSV may include a first contact hole CH1 which exposes a portion of the drain electrode DE of the first transistor T1, and a second contact hole CH2 which exposes a portion of the driving voltage line DVL.

The display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a partition wall PW, a bank BNK, a reflective pattern RP, first and second electrodes REL1 and REL2, first and second connection lines CNL1 and CNL2, a plurality of light emitting elements LD, first and second contact electrodes CNE1 and CNE2, etc..

The partition wall PW may be disposed in the first to third sub-pixels SP1 to SP3. In detail, the partition wall PW may be provided on the passivation layer PSV in the emission area EMA of each of the first to third sub-pixels SP1 to SP3. At least two partition walls PW may be disposed in each sub-pixel. The partition walls disposed adjacent to each other are spaced apart from each other by a predetermined distance. In the drawings, there is illustrated the case where three partition walls PW are disposed in each sub-pixel at positions spaced apart from each other by a predetermined distance.

The adjacent partition walls PW may be disposed on the passivation layer PSV and spaced apart from each other by a length L of one light emitting element LD or more. The light emitting elements LD may be disposed between the adjacent partition walls PW in the emission area EMA. In the perimeter of the emission area EMA, the partition walls PW are disposed between the light emitting element LD and the bank BNK.

The partition wall PW may include a curved surface having a cross-sectional shape such as a semicircle, or a semiellipse which is reduced in width upward from one surface of the passivation layer PSV. In the drawings, the partition wall PW is illustrated as having a trapezoidal cross-section. In a sectional view, the shape of each of the partition wall PW is not limited to the foregoing examples, and may be changed in various ways within a range in which the efficiency of light emitted from each of the light emitting elements LD can be enhanced. The two adjacent partition walls PW may be disposed on the same layer on the passivation layer PSV and have the same height.

The bank BNK may be further disposed on the passivation layer PSV. The bank BNK may be disposed between the adjacent sub-pixels SP1 to SP3, separate the adjacent sub-pixels SP1 to SP3 from each other, and prevent light emitted from the sub-pixels SP1 to SP3 from traveling toward the adjacent sub-pixels SP1 to SP3. To this end, the bank BNK may have a thickness T2 greater than a thickness T1 of the partition wall PW.

Furthermore, the bank BNK may define the emission area EMA of each of the sub-pixels SP1 to SP3. Although an area in which the bank BNK is disposed corresponds to the non-emission area PPA of each of the sub-pixels SP1 to SP3, light emitted from the light emitting element LD may be reflected by the reflective pattern RP disposed on the bank BNK and travel upward. Therefore, although the bank BNK is disposed in the non-emission area PPA, the display device according to the present disclosure makes it possible to emit light even in the area in which the bank BNK is disposed.

The partition wall PW and the bank BNK may be formed of the same material on the same layer. For example, although the partition wall PW and the bank BNK may be formed of organic insulating material including organic material, but the present disclosure is not limited thereto.

The bank BNK may be formed of material different from that of the partition wall PW. For example, the bank BNK may include Cr, a double layer including Cr/CrOx, resin including carbon pigment, black dye, graphite, etc. In the case where the bank BNK is formed of resin including carbon pigment, the carbon pigment may be carbon black which is black pigment having a light shielding function. In this case, the bank BNK may function as a black matrix capable of preventing color mixture from being caused between the sub-pixels SP1, SP2, and SP3.

The bank BNK may include a curved surface having a cross-sectional shape such as a semicircle, or a semiellipse which is reduced in width upward from one surface of the passivation layer PSV. In the drawings, the bank BNK is illustrated as having a trapezoidal cross-section. However, in a sectional view, the shape of the bank BNK is not limited to the foregoing embodiments, and may be changed in various ways within a range capable of preventing light interference between the adjacent sub-pixels SP1 to SP3.

The first connection line CNL1 may be electrically coupled with the pixel circuit layer PCL through the first contact hole CH1 formed in the passivation layer PSV. In detail, the first connection line CNL1 may be connected with a portion of the drain electrode DE of the first transistor T1 of the pixel circuit layer PCL. Although <FIG> illustrates that the first contact hole CH1 is formed in the non-emission area PPA, the first contact hole CH1 may be formed in the emission area EMA.

The first connection line CNL1 may extend from each of the first to third sub-pixels SP1 to SP3 in the first direction DR1. The first connection line CNL1 may be provided in only one corresponding sub-pixel so as to independently drive each of the first to third sub-pixels SP1 to SP3.

The second connection line CNL2 may also be electrically coupled with the pixel circuit layer PCL through the second contact hole CH2 formed in the passivation layer PSV. In detail, the second connection line CNL2 may be connected with a portion of the driving voltage line DVL of the pixel circuit layer PCL.

The second connection line CNL2 may extend in a direction parallel to a direction in which the first connection line CNL1 extends. The second connection line CNL2 may be provided in common to the first to third sub-pixels SP1 to SP3. Therefore, the first to third sub-pixels SP1 to SP3 may be coupled in common to the second connection line CNL2.

Each of the first and second electrodes REL1 and REL2 may be provided on the emission area EMA of each of the first to third sub-pixels SP1 to SP3 and extend in the second direction DR2 intersecting with the first direction DR1. The first and second electrodes REL1 and REL2 may be provided on the same plane and spaced apart from each other by a predetermined distance.

The first electrode REL1 may be coupled to the first connection line CNL1. For example, the first electrode REL1 may be integrally coupled with the first connection line CNL1. In the drawings, there is illustrated the case where the first electrode REL1 includes a <NUM>-<NUM>-th electrode REL1_1 and a <NUM>-<NUM>-th electrode REL1_2 which diverge in the second direction DR2 from the first connection line CNL1 extending in the first direction DR1. The <NUM>-<NUM>-th electrode REL1_1, the <NUM>-<NUM>-th electrode REL1_2, and the first connection line CNL1 may be integrally provided and electrically and/or physically coupled to each other.

In the case where the first electrode REL1 and the first connection line CNL1 are formed and/or provided integrally with each other, the first connection line CNL1 may be regarded as one area of the first electrode RELL. However, the present disclosure is not limited thereto. For example, in some embodiments, the first electrode REL1 and the first connection line CNL1 may be individually formed and electrically coupled to each other through a contact hole, via hole, or the like, which is not illustrated.

The second electrode REL2 may be coupled to the second connection line CNL2. For example, the second electrode REL2 may be integrally coupled with the second connection line CNL2. In the drawings, there is illustrated a structure in which the second connection line CNL2 extends in the first direction DR1, and the second electrode REL2 diverges from the second connection line CNL2 in the second direction DR2.

In the case where the second electrode REL2 and the second connection line CNL2 are formed and/or provided integrally with each other, the second connection line CNL2 may be regarded as one area of the second electrode REL2. However, the present disclosure is not limited thereto. For example, in some embodiments, the second electrode REL2 and the second connection line CNL2 may be individually formed and electrically coupled to each other through a contact hole, via hole, or the like, which is not illustrated.

Each of the first and second electrodes REL1 and REL2 may function as an alignment electrode for aligning the light emitting elements LD in the emission area EMA of each of the first to third sub-pixels SP1 to SP3.

In detail, before the light emitting elements LD are aligned in the emission area EMA of each of the first to third sub-pixels SP1 to SP3, a first alignment voltage may be applied to the first electrode REL1 through the first connection line CNL1, and a second alignment voltage may be applied to the second electrode REL2 through the second connection line CNL2. The first alignment voltage and the second alignment voltage may have different voltage levels. As predetermined alignment voltages having different voltage levels are respectively applied to the first electrode REL1 and the second electrode REL2, an electric field may be formed between the first electrode REL1 and the second electrode REL2. Hence, the light emitting elements LD may be aligned between the first electrode REL1 and the second electrode REL2.

In a plan view, the second electrode REL2 may be provided between the <NUM>-<NUM>-th electrode REL1_1 and the <NUM>-<NUM>-th electrode REL1_2 and spaced apart from each of the <NUM>-<NUM>-th and <NUM>-<NUM>-th electrodes REL1_1 and REL1_2 by a predetermined distance.

After the light emitting elements LD are aligned in the emission area EMA of each of the first to third sub-pixels SP1 to SP3, each of the first and second electrodes REL1 and REL2 may function as a driving electrode for driving the light emitting elements LD.

The first and second electrodes REL1 and REL2 each may have a shape corresponding to that of the partition wall PW, and thus may be made of material having a predetermined reflectivity to allow light emitted from the opposite ends EP1 and EP2 of each of the light emitting elements LD to travel in a direction (e.g., in a frontal direction) in which an image of the display device is displayed. In this case, the first and second electrodes REL1 and REL2 may function as reflectors for enhancing the efficiency of light emitted from the light emitting elements LD.

In detail, the first and second electrodes REL1 and REL2, and the first and second connection lines CNL1 and CNL2 may be formed of conductive material having a predetermined reflectivity. Metal, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and an alloy thereof may be used as the conductive material. However, the materials of the first and second electrodes REL1 and REL2, and the first and second connection lines CNL1 and CNL2 are not limited to the foregoing materials.

Although in the drawings there is illustrated the case where each of the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 has a single layer structure, it may have a multilayer structure formed by stacking two or more materials among metals, alloys, conductive oxides, and conductive polymers.

Any one of the first and second electrodes REL1 and REL2 may be an anode electrode, and the other may be a cathode electrode. In an embodiment of the present disclosure, the first electrode REL1 may be an anode electrode, and the second electrode REL2 may be a cathode electrode.

Each of the light emitting elements LD may be formed of a light emitting element which is made of material having an inorganic crystal structure and has a subminiature size, e.g., corresponding to the nanoscale or the microscale.

Although at least two light emitting elements LD are provided in the emission area EMA of each of the first to third sub-pixels SP1 to SP3, the present disclosure is not limited thereto. In an embodiment, the number of light emitting elements LD provided in each sub-pixel may be changed in various ways.

Each of the light emitting elements LD may include a stacked emission pattern formed by successively stacking a first conductive semiconductor layer <NUM>, an active layer <NUM>, and a second conductive semiconductor layer <NUM> in the longitudinal direction (L) of each light emitting element LD. Furthermore, each of the light emitting elements LD may further include an insulating film <NUM> which encloses an outer circumferential surface of the stacked emission pattern. In an embodiment of the present disclosure, each of the light emitting elements LD may have a cylindrical shape. In this case, each light emitting element LD may have a first end EP1 corresponding to any one of a lower portion of the cylinder and an upper portion of the cylinder, and a second end EP2 corresponding to the other of the lower portion of the cylinder and the upper portion of the cylinder. Any one of the first conductive semiconductor layer <NUM> and the second conductive semiconductor layer <NUM> may be disposed on the first end EP1 of each light emitting element LD, and the other of the first conductive semiconductor layer <NUM> and the second conductive semiconductor layer <NUM> may be disposed on the second end EP2 thereof.

In an embodiment of the present disclosure, the light emitting elements LD may be divided into a plurality of first light emitting elements LD1 aligned between the <NUM>-<NUM>-th electrode REL1_1 and the second electrode REL2, and a plurality of second light emitting elements LD2 aligned between the second electrode REL2 and the <NUM>-<NUM>-th electrode REL1_2. A second insulating layer INS2 for covering a portion of an upper surface of each of the light emitting elements LD may be provided on the light emitting elements LD. A first insulating layer INS1 may be provided between each of the light emitting elements LD and the passivation layer PSV.

The first insulating layer INS1 may be charged into space between the passivation layer PSV and each of the light emitting elements LD to stably support the light emitting elements LD and prevent the light emitting elements LD from being removed from the passivation layer PSV. The first insulating layer INS1 may be formed of an inorganic insulating layer including inorganic material, or an organic insulating layer including organic material. Although in an embodiment of the present disclosure the first insulating layer INS1 may be formed of inorganic insulating layer having an advantage in protecting the light emitting elements LD from the pixel circuit layer PCL, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer that has an advantage in planarization of support surfaces of the light emitting elements LD.

Particularly, the first insulating layer INS1 may extend to the non-emission area PPA of the sub-pixels SP1, SP2, and SP3 to cover even a portion of the bank BNK. Although in the drawings there is illustrated the case where the first insulating layer INS1 completely covers a side surface and an upper surface of the bank BNK, the first insulating layer INS1 may be disposed to cover only a portion of the bank BNK.

The reflective pattern RP may be disposed on the bank BNK. The reflective pattern RP may be provided to reflect, upward, light traveling toward sides of each of the sub-pixels SP1, SP2, and SP3.

The light emitting element LD may emit light in the form of Lambertian. In detail, the light emitting elements LD are distributed to have a spherical shape. Thus, in the emission area EMA of each sub-pixel SP1, SP2, SP3, a perimeter of the emission area EMA that is adjacent to the non-emission area PPA is less in the amount of light emitted from the light emitting elements LD than a central portion of the emission area MEA.

In an embodiment of the present disclosure, the reflective pattern RP disposed on the bank BNK may reflect, in a direction in which an image is displayed, light traveling toward the perimeters of the sub-pixels SP1, SP2, and SP3, in other words, light traveling toward the non-emission area PPA, among light emitted from the sub-pixels SP1, SP2, and SP3. Particularly, the reflective pattern RP is formed along the shape of the bank BNK. Therefore, as shown in the drawings, in the case where the bank BNK has a trapezoidal cross-section, light reflected by the reflective pattern RP may efficiently travel in the direction in which an image is displayed.

To this end, the reflective pattern RP may include conductive material having a predetermined reflectivity. Metal, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and an alloy thereof may be used as the conductive material.

The reflective pattern RP may be formed not only on the side surface of the bank BNK but also on the upper surface of the bank BNK. For example, the reflective pattern RP may be formed to completely cover the upper surface and the side surface of the bank BNK.

The second insulating layer INS2 may be disposed on the light emitting elements LD. The second insulating layer INS2 may be an organic insulating layer including organic material. In an embodiment of the present disclosure, the second insulating layer INS2 may be provided on a portion of the upper surface of each of the light emitting elements LD such that the opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside. Furthermore, the second insulating layer INS2 is, in accordance with the invention, disposed on the reflective pattern RP so that the reflective pattern RP can be prevented from being connected with the first or second contact electrodes CNE1 or CNE2.

The first contact electrode CNE1 may be disposed on the first insulating layer INS1 and thus be coupled with the first electrode REL1 that is exposed by removing a portion of the first insulating layer INS1. The first contact electrode CNE1 may electrically and/or physically reliably couple the first electrode REL1 with one of the opposite ends EP1 and EP2 of the light emitting element LD. The first contact electrode CNE1 may be formed of transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the first electrode REL1 in the frontal direction of the display device to travel in the frontal direction without loss.

Here, the first contact electrode CNE1 may include a <NUM>-<NUM>-th contact electrode CNE1_1 provided on the <NUM>-<NUM>-th electrode REL1_1, and a <NUM>-<NUM>-th contact electrode CNE1_2 provided on the <NUM>-<NUM>-th electrode REL1_2.

A third insulating layer INS3 for covering the first contact electrode CNE1 may be provided on the first contact electrode CNE1. The third insulating layer INS3 may prevent the first contact electrode CNE1 from being exposed to the outside, thus preventing the first contact electrode CNE1 from being corroded.

The third insulating layer INS3 may be formed of an inorganic insulating layer including inorganic material, or an organic insulating layer including organic material. Although the third insulating layer INS3 may have a single layer structure as shown in the drawing, the present disclosure is not limited thereto. For example, the third insulating layer INS3 may have a multilayer structure. In the case where the third insulating layer INS3 has a multilayer structure, the third insulating layer INS3 may have a structure formed by alternately stacking a plurality of inorganic insulating layers and a plurality of organic insulating layers. For example, the third insulating layer INS3 may have a structure formed by sequentially stacking a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer.

The second contact electrode CNE2 may also be electrically coupled with the second electrode REL2 that is exposed by removing a portion of the first insulating layer INS1. The second contact electrode CNE2 may electrically and/or physically reliably couple the second electrode REL2 with the other end of the opposite ends EP1 and EP2 of the light emitting element LD, the other end being not connected with the first electrode REL1. The second contact electrode CNE2 may be formed of transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the second electrode REL2 in the frontal direction of the display device to travel in the frontal direction without loss.

As described above, the opposite ends EP1 and EP2 of the light emitting elements LD may be respectively coupled to the first electrode REL1 and the second electrode REL2 through the first and second contact electrodes CNE1 and CNE2 so that predetermined voltages can be respectively applied to the opposite ends EP1 and EP2, and each of the light emitting elements LD can emit light by coupling of electron-hole pairs in the active layer <NUM> of the light emitting element LD. Here, the active layer <NUM> may emit light having a wavelength range from <NUM> to <NUM>. However, the wavelength range of light emitted from the active layer <NUM> is not limited thereto, and may be changed in various ways.

A fourth insulating layer INS4 for covering the second contact electrode CNE2 may be provided on the second contact electrode CNE2. The fourth insulating layer INS4 may prevent the second contact electrode CNE2 from being exposed to the outside, thus preventing the second contact electrode CNE2 from being corroded. The fourth insulating layer INS4 may be formed of either an inorganic insulating layer or an organic insulating layer. Here, in the case where the fourth insulating layer INS4 is formed of an organic insulating layer, a step difference caused by the partition wall PW, the first and second electrodes REL1 and REL2, the first and second contact electrodes CNE1 and CNE2, etc. may be mitigated.

As described above, in an embodiment of the present disclosure, the reflective pattern RP may be formed on the bank BNK, so that light that is emitted from each of the sub-pixels SP1, SP2, and SP3 and travels toward the bank BNK may be reflected by the reflective pattern RP in the direction in which an image is displayed. Hence, in the display device in accordance with an embodiment of the present disclosure, the light output efficiency of the light emitting elements LD may be enhanced, so that the light efficiency of the display device may be enhanced.

Although in the drawings the bank BNK is illustrated as being disposed on the same layer as that of the partition wall PW, the bank BNK may be disposed on a layer different from that of the partition wall PW. Furthermore, although the reflective pattern RP is illustrated as being disposed on a layer different from that of the first and second electrodes REL1 and REL2, the reflective pattern RP may be disposed on the same layer as that of the first and second electrodes REL1 and REL2.

In other words, the positions at which the bank BNK and the reflective pattern RP are formed may be changed in various ways without being limited. Hereinafter, display devices in accordance with embodiments of the present disclosure including the bank BNK and the reflective pattern RP which are formed at various positions will be described with reference to the attached drawings.

<FIG> schematically illustrate display devices in accordance with embodiments of the present disclosure and are sectional views corresponding to line I-I' of <FIG>.

As illustrated in <FIG>, the bank BNK and the partition wall PW may be formed on the same layer. The reflective pattern RP and the first and second electrodes REL1 and REL2 may also be disposed on the same layer.

In detail, the bank BNK and the partition wall PW may be formed on the passivation layer PSV of the pixel circuit layer PCL. In this case, the bank BNK and the partition wall PW may include the same material provided on the same layer. The reflective pattern RP, and the <NUM>-<NUM>-th electrode REL1_1 and the second electrode REL2 may be respectively provided on the bank BNK and the partition wall PW. Here, the reflective pattern RP, the <NUM>-<NUM>-th electrode REL1_1, and the second electrode REL2 may also include the same material provided on the same layer.

The first insulating layer INS1 may be disposed on the passivation layer PSV to cover the reflective pattern RP and the <NUM>-<NUM>-th electrode REL1_1 and the second electrode REL2. The <NUM>-<NUM>-th electrode REL1_1 and the second electrode REL2 may be exposed by removing a portion of the first insulating layer INS1. The exposed <NUM>-<NUM>-th electrode REL1_1 and the exposed second electrode REL2 may be coupled to the light emitting element LD through the <NUM>-<NUM>-th contact electrode CNE1_1 and the second contact electrode CNE2, respectively.

As illustrated in <FIG>, the bank BNK and the partition wall PW may be disposed on different layers.

For example, as illustrated in <FIG>, the bank BNK and the partition wall PW may be disposed on different layers with the first insulating layer INS1 interposed therebetween. For instance, the partition wall PW may be disposed under the first insulating layer INS1, and the bank BNK may be disposed over the first insulating layer INS1. The reflective pattern RP, and the <NUM>-<NUM>-th electrode REL1_1 and the second electrode REL2 may also be disposed on different layers with the first insulating layer INS1 interposed therebetween. For example, the <NUM>-<NUM>-th electrode REL1_1 and the second electrode REL2 may be disposed under the first insulating layer INS1, and the reflective pattern RP may be disposed over the first insulating layer INS1.

As illustrated in <FIG>, although the bank BNK and the partition wall PW may be disposed on different layers, all of the reflective pattern RP and the first and second electrodes REL1 and REL2 may be disposed over the first insulating layer INS1. The reflective pattern RP and the first and the second electrodes REL1 and REL2 may include the same material provided on the same layer.

As described above, <FIG> illustrate some of various embodiments of the present disclosure, and the positions at which the bank BNK, the partition wall PW, the <NUM>-<NUM>-th electrode REL1_1 and the second electrode REL2, and the reflective pattern RP are formed are not limited to that of the foregoing embodiments.

Hereinafter, a display device including a light conversion pattern layer in accordance with an embodiment of the present disclosure will be described.

<FIG> illustrates a display device in accordance with an embodiment of the present disclosure, and is a schematic sectional view illustrating a structure of coupling a light conversion pattern layer to the display device of <FIG>.

<FIG> schematically illustrates a pixel area of one pixel of a plurality of pixels included in the display device, for the convenience sake of explanation. Furthermore, for the convenience sake, in <FIG>, structures of some components equal to those of the display device that are described in detail with reference to <FIG> are schematically illustrated, and detailed explanation thereof will be omitted.

Referring to <FIG>, <FIG>, and <FIG>, a display device DP in accordance with an embodiment of the present disclosure may include a base layer BSL on which at least one pixel PXL including first, second, and third sub-pixels SP1, SP2, and SP3 is provided, and a capping layer CPL coupled with the base layer BSL. Each of the sub-pixels SP1, SP2, and SP3 may include a light conversion pattern layer LCP disposed between the base layer BSL and the capping layer CPL.

The capping layer CPL may be disposed to overlap with a display area of the base layer BSL and cover the display element layer DPL, thus preventing oxygen and water from permeating the display element layer DPL. For example, the capping layer CPL may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. Furthermore, the capping layer CPL may be formed of the same material as that of the base layer BSL, or may be formed of material different from that of the base layer BSL.

The capping layer CPL may be disposed to come into close contact with the uppermost layer of the display element layer DPL. In the drawing, the capping layer CPL is illustrated as coming into close contact with the light conversion pattern layer LCP.

The light conversion pattern layer LCP may include a first light conversion pattern layer LCP1 disposed on the first sub-pixel SP1, a second light conversion pattern layer LCP2 disposed on the second sub-pixel SP2, and a third light conversion pattern layer LCP3 disposed on the third sub-pixel SP3. At least some of the first, second, and third light conversion pattern layers LCP1, LCP2, and LCP3 may include a color conversion layer CCL and/or a color filter CF.

In an embodiment of the present disclosure, there is illustrated the case where each sub-pixel SP1, SP2, and SP3 includes light emitting elements LD configured to emit blue light, e.g., light ranging from <NUM> to <NUM>, the wavelength range of light emitted from the light emitting elements LD is not limited thereto.

For example, the first light conversion pattern layer LCP1 may include a first color conversion layer CCL1 including first color conversion particles corresponding to a first color, and a first color filter CF1 configured to allow the first color of light to selectively pass therethrough. The second light conversion pattern layer LCP2 may also include a second color conversion layer CCL2 including second color conversion particles corresponding to a second color, and a second color filter CF2 configured to allow the second color of light to selectively pass therethrough. The third light conversion pattern layer LCP3 may include at least one of a light scattering layer LSL including light scattering particles SCT, and a third color filter CF3 configured to allow the third color of light to selectively pass therethrough.

In an embodiment of the present disclosure, the light emitting elements LD aligned in the emission area EMA of each of the first to third sub-pixels SP1 to SP3 may emit the same color light. A color conversion layer CCL may be disposed over at least some of the first, second, and third sub-pixels SP1, SP2, and SP3. For example, first and second color conversion layers CCL1 and CCL2 may be respectively disposed over the first and second sub-pixels SP1 and SP2. The display device in accordance with an embodiment of the present disclosure may display a full-color image.

The first color conversion layer CCL1 may be disposed between the base layer BSL and the capping layer CPL to correspond to the first sub-pixel SP1, and more precisely, be directly formed on the display element layer DPL and charged into the emission area EMA of the first sub-pixel SP1. In other words, the first color conversion layer CCL1 may be formed on the base layer BSL so that light emitted from the light emitting elements LD may be directly incident on the first color conversion layer CCL1.

In the case where the first sub-pixel SP1 is a red sub-pixel, the first color conversion layer CCL1 may include, as the first color conversion particles, red quantum dots QDr which convert blue light emitted from the light emitting elements LD to red light.

The first color filter CF1 may be disposed on the first color conversion layer CCL1, and include color filter material which allows the first color of light converted by the first color conversion layer CCL1 to selectively pass therethrough. For example, the first color filter CF1 may be a red color filter.

The second color conversion layer CCL2 may be disposed between the base layer BSL and the capping layer CPL to correspond to the second sub-pixel SP2, and more precisely, be directly formed on the display element layer DPL and charged into the emission area EMA of the second sub-pixel SP2. In the case where the second sub-pixel SP2 is a green sub-pixel, the second color conversion layer CCL2 may include, as the second color conversion particles, green quantum dots QDg which convert blue light emitted from the light emitting elements LD to green light.

The second color filter CF2 may be disposed on the second color conversion layer CCL2, and include color filter material which allows the second color of light converted by the second color conversion layer CCL2 to selectively pass therethrough. For example, the second color filter CF2 may be a green color filter.

The light scattering layer LSL may be disposed between the base layer BSL and the capping layer CPL to correspond to the third sub-pixel SP3, and more precisely, be directly formed on the display element layer DPL and charged into the emission area EMA of the third sub-pixel SP3. Furthermore, the third color filter CF3 may be further provided on the light scattering layer LSL.

The third color filter CF3 may include color filter material which allows a color of light emitted from the light emitting elements LD disposed in the third sub-pixel to selectively pass therethrough. For example, the third color filter CF3 may be a blue color filter.

In the display device having the above-mentioned structure, light emitted from the each sub-pixel SP1, SP2, SP3 may pass through the light conversion pattern layer LCP and be emitted to the outside through the capping layer CPL, whereby the display device may form an image. Here, the capping layer CPL may be directly disposed on the light conversion pattern layer LCP so that the light conversion pattern layer LCP may be charged into space between the bank BNK and the capping layer CPL in each sub-pixel SP1, SP2, SP3. Therefore, the length of a light path along which light emitted from the light emitting elements LD is emitted to the outside through the capping layer CPL may be minimized, so that the light efficiency may be maximized.

Furthermore, in the display device in accordance with the present disclosure, the light conversion pattern layer LCP may be disposed, rather than being formed on a separate substrate, in space defined by the bank BNK by forming the pixel circuit layer PCL, the display element layer DPL, and the light conversion pattern layer LCP directly on the base layer BSL. Hence, the process of manufacturing the display device may be simplified.

In the case where the light conversion pattern layer LCP is formed on a separate substrate, there is the need to perform a process of aligning the base layer BSL with the substrate on which the light conversion pattern layer LCP is formed. However, in the display device according to the present disclosure, the capping layer CPL is directly formed on the light conversion pattern layer LCP, so that process risk is reduced.

Hereinafter, a method of manufacturing the display device in accordance with an embodiment of the present disclosure will be described in detail with reference to the attached drawings.

<FIG> are sectional views sequentially illustrating a method of manufacturing the display device of <FIG>.

Referring to <FIG>, <FIG>, and <FIG>, the pixel circuit layer PCL is formed on the base layer BSL of each of the first to third sub-pixels SP1, SP2, and SP3. The pixel circuit layer PCL may include the first and second transistors T1 and T2, the driving voltage line DVL, and the passivation layer PSV.

The first and second contact holes CH1 and CH2 may be formed in the passivation layer PSV. Although not illustrated, the first contact hole CH1 may expose the drain electrode DE of the first transistor T1, and the second contact hole CH2 may expose the driving voltage line DVL.

Here, the first and second contact holes CH1 and CH2 may be formed at any step before the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 are formed. For example, after the partition wall PW and the bank BNK are formed, the first and second contact holes CH1 and CH2 may be formed.

Referring to <FIG>, <FIG>, and <FIG> the partition wall PW and the bank BNK are formed on the pixel circuit layer PCL. The partition wall PW and the bank BNK may be formed by applying an insulating material layer (not shown) to the passivation layer PSV and patterning the insulating material layer. The partition wall PW may be formed on the passivation layer PSV in the emission area EMA of each of the first to third sub-pixels SP1 to SP3. The bank BNK may be formed in the non-emission area PPA between the adjacent sub-pixels SP1 to SP3.

The partition wall PW and the bank BNK may be formed of the same material through a process using a single mask. In this case, the partition wall PW and the bank BNK may be formed with different thicknesses by using a halftone mask or the like.

Furthermore, the partition wall PW and the bank BNK may be successively formed using different masks.

Referring to <FIG>, <FIG>, and <FIG>, the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 are formed on the passivation layer PSV of each sub-pixel including the partition wall PW and the bank BNK. The first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2 may be formed by patterning conductive material having a high reflectivity.

Each of the first and second electrodes REL1 and REL2 may be provided and/or formed on a corresponding partition wall PW in the emission area EMA of each sub-pixel. Each of the first and second connection lines CNL1 and CNL2 may be provided and/or formed on the non-emission area PPA of each sub-pixel.

Although not illustrated, the first connection line CNL1 may be electrically coupled to the first transistor T1 of the pixel circuit layer PCL through the first contact hole CH1 of the passivation layer PSV. The first connection line CNL1 may be provided integrally with the first electrode REL1 and electrically and/or physically coupled to the first electrode REL1. Hence, a signal (or a voltage) applied to the first transistor T1 may be transmitted to the first electrode REL1 through the first connection line CNL1.

Although not illustrated, the second connection line CNL2 may be electrically coupled to the driving voltage line DVL of the pixel circuit layer PCL through the second contact hole CH2 of the passivation layer PSV. The second connection line CNL2 may be provided integrally with the second electrode REL2 and electrically and/or physically coupled to the second electrode REL2. Consequently, the voltage of the second driving power supply VSS of the driving voltage line DVL may be transmitted to the second electrode REL2 through the second connection line CNL2.

Referring to <FIG>, <FIG>, and <FIG>, the first insulating layer INS1 is formed on the first and second electrodes REL1 and REL2 and the first and second connection lines CNL1 and CNL2. The first insulating layer INS1 may be formed between the first electrode REL1 and the second electrode REL2 in the emission area EMA of each sub-pixel. The first insulating layer INS1 may be formed to extend to an area in which the first insulating layer INS1 overlaps with the bank BNK.

Referring to <FIG>, <FIG>, and <FIG>, the reflective pattern RP is formed on the bank BNK. Here, the first insulating layer INS1 is disposed between the reflective pattern RP and the bank BNK. The reflective pattern RP may be formed by patterning conductive material having a predetermined reflectivity. Metal, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and an alloy thereof may be used as the conductive material.

The reflective pattern RP may function to reflect light traveling toward the bank BNK among light emitted from the sub-pixels SP1, SP2, and SP3, toward an upper portion of the base layer BSL.

Referring to <FIG>, <FIG>, and <FIG>, an electric field is formed between the first electrode REL1 and the second electrode REL2 by respectively applying corresponding alignment voltages to the first and second electrodes REL1 and REL2 of each sub-pixel through the first and second connection lines CNL1 and CNL2. In the case where direct current power or alternating current power having predetermined voltage and period is repeatedly applied several times to each of the first and second electrodes REL1 and REL2 through the first and second connection lines CNL1 and CNL2, an electric field may be formed between the first and second electrodes REL1 and REL2 by a difference in potential between the first and second electrodes REL1 and REL2.

After an electric field is formed between the first electrode REL1 and the second electrode REL2 that are formed in the emission area EMA of each sub-pixel, light emitting elements LD are supplied in an inkjet printing scheme or the like. For example, the light emitting elements LD may be supplied onto the passivation layer PSV of the emission area EMA of such sub-pixel by disposing a nozzle over the passivation layer PSV and dropping a solvent including the light emitting elements LD onto the passivation layer PSV through the nozzle. The solvent may be any one of acetone, water, alcohol, and toluene, but the present disclosure is not limited thereto. For example, the solvent may include material which may be vaporized at the room temperature or by heat. Furthermore, the solvent may have the form of ink or paste. A method of supplying the light emitting elements LD is not limited to the foregoing method. The method of supplying the light emitting elements LD may be changed. Subsequently, the solvent may be removed.

In the case where the light emitting elements LD are input onto the passivation layer PSV, self-alignment of the light emitting elements LD is induced by the electric field formed between the first electrode REL1 and the second electrode REL2, so that the light emitting elements LD can be aligned between the first electrode REL1 and the second electrode REL2. In other words, the light emitting elements LD may be intensively aligned in a target area, e.g., the emission area EMA of each sub-pixel.

Referring to <FIG>, <FIG>, and <FIG>, after the alignment of the light emitting elements LD, the second insulating layer INS2 that covers a portion of the upper surface of each light emitting element LD is formed by applying an insulating material layer (not illustrated) onto the passivation layer PSV and patterning the insulating material layer using a mask (not illustrated). Hence, the opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside.

Here, the second insulating layer INS2 may be formed to completely enclose the reflective pattern RP. The reason for this is to prevent the reflective pattern RP from being connected with the first and second contact electrodes CNE1 and CNE2 to be described below.

Referring to <FIG>, <FIG>, <FIG>, portions of the first electrode REL1 and the second electrode REL2 may be exposed by removing a portion of the first insulating layer INS1.

Thereafter, referring to <FIG>, <FIG>, and <FIG>, the first contact electrode CNE1 to be electrically coupled with the exposed first electrode REL1 is formed. The first contact electrode CNE1 may electrically couple the first electrode REL1 with one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. Therefore, a signal of the first transistor T1 that is applied to the first electrode REL1, for example, the voltage of the first driving power supply VDD, may be transmitted to each of the light emitting elements LD through the first contact electrode CNE1.

The first contact electrode CNE1 may be formed of transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the first electrode REL1 in the frontal direction of the display device, e.g., in the direction in which an image is displayed, to travel in the frontal direction without loss.

Referring to <FIG>, <FIG>, and <FIG>, the third insulating layer INS3 may be formed to cover the first contact electrode CNE1. The third insulating layer INS3 may prevent the first contact electrode CNE1 from being exposed to the outside, thus preventing the first contact electrode CNE1 from being corroded.

Referring to <FIG>, <FIG>, and <FIG>, the second contact electrode CNE2 to be electrically coupled with the exposed second electrode REL2 is formed. The second contact electrode CNE2 may electrically couple the second electrode REL2 with the other end of the opposite ends EP1 and EP2 of each of the light emitting elements LD, the other end being not coupled with the first contact electrode CNE1. Hence, the voltage of the second driving power supply VSS applied to the second electrode REL2 may be transmitted to each of the light emitting elements LD.

The second contact electrode CNE2 may be formed of transparent conductive material to allow light emitted from each of the light emitting elements LD and reflected by the second electrode REL2 in the frontal direction of the display device to travel in the frontal direction without loss.

The fourth insulating layer INS4 for covering the second contact electrode CNE2 may be formed on the second contact electrode CNE2. The fourth insulating layer INS4 may prevent the second contact electrode CNE2 from being exposed to the outside, thus preventing the second contact electrode CNE2 from being corroded. Here, the fourth insulating layer INS4 is formed of an organic insulating layer, so that the fourth insulating layer INS4 may mitigate a step difference caused by the partition wall PW, the first and second electrodes REL1 and REL2, the first and second contact electrodes CNE1 and CNE2, etc..

The number of masks needed to manufacture the display device may be reduced by forming the first and second contact electrodes CNE1 and CNE2 on the same layer.

Hereinafter, a display device in accordance with an embodiment of the present disclosure in which the first and second contact electrodes CNE1 and CNE2 are formed on the same layer will be described in detail with reference to the attached drawings.

<FIG> are sectional views illustrating a display device in accordance with an embodiment of the present disclosure and are sectional views corresponding to line I-I' of <FIG>.

Referring to <FIG>, <FIG>, <FIG>, the display device in accordance with an embodiment of the present disclosure may include a base layer BSL on which a plurality of pixels PXL are provided.

Each of the pixels PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 which are provided on the base layer BSL. Each of the first to third sub-pixels SP1 to SP3 may include an emission area EMA configured to emit light, and a non-emission area PPA disposed around a perimeter of the emission area EMA.

A light shielding pattern SDL may be further provided between the base layer BSL and the buffer layer BFL. The light shielding pattern SDL may be a light shielding layer which is formed of conductive material, insulating material, etc., and blocks light drawn into a rear surface of the base layer BSL so as to block the light from being drawn into the pixel circuit layer PCL of each of the first to third sub-pixels SP1 to SP3.

The light shielding pattern SDL may include Cr, a double layer including Cr/CrOx, resin including carbon pigment, black dye, graphite, etc. In the case where the light shielding pattern SDL is formed of resin including carbon pigment, the carbon pigment may be carbon black which is black pigment having a light shielding function.

The light shielding pattern SDL may be provided on the base layer BSL to correspond to a lower portion of the semiconductor layer SCL of each of the first and second transistors T1 and T2. The light shielding pattern SDL may be formed of metal which is conductive material. The light shielding pattern SDL may be electrically coupled to some components of any one transistor of the first and second transistors T1 and T2. Although in the drawings the light shielding pattern SDL is illustrated as being coupled with the drain electrode DE of the first transistor T1, the present disclosure is not limited thereto.

The display element layer DPL may include a partition wall PW, a bank BNK, first and second electrodes REL1 and REL2, first and second connection lines CNL1 and CNL2, a plurality of light emitting elements LD, first and second contact electrodes CNE1 and CNE2, etc..

The partition wall PW and the bank BNK may be formed on the passivation layer PSV and be formed on the same layer, as illustrated in the drawings. The partition wall PW may be formed and/or provided in the emission area EMA of each sub-pixel. The bank BNK may be formed and/or provided in the non-emission area PPA of each sub-pixel.

The reflective pattern RP disposed on the bank BNK may be provided on the same layer as that of the first and second electrodes REL1 and REL2, or disposed on a layer different from that of the first and second electrodes REL1 and REL2.

For example, as illustrated in <FIG>, the reflective pattern RP may include the same material provided on the same layer as that of the first and second electrodes REL1 and REL2. The first insulating layer INS1 may be disposed to cover the reflective pattern RP and the first and second electrodes REL1 and REL2. A plurality of light emitting elements LD may be disposed on the first insulating layer INS1.

The second insulating layer INS2 may be disposed to cover portions of the upper surfaces of the light emitting elements LD such that the opposite ends of each of the light emitting elements LD are exposed.

The first contact electrode CNE1 and the second contact electrode CNE2 may be respectively coupled to the first electrode REL1 and the second electrode REL2 that are exposed from the first insulating layer INS1. For example, the first contact electrode CNE1 may electrically couple the first end of the light emitting element LD with the first electrode REL1. The second contact electrode CNE2 may electrically couple the second end of the light emitting element LD with the second electrode REL2.

The first contact electrode CNE1 and the second contact electrode CNE2 may be provided on the same plane. The first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart from each other by a predetermined distance on the second insulating layer INS2 and thus electrically and/or physically separated from each other. In other words, the first contact electrode CNE1 and the second contact electrode CNE2 may be provided on the same layer and formed through the same manufacturing process.

The third insulating layer INS3 for covering the first contact electrode CNE1 and the second contact electrode CNE2 may be provided on the first contact electrode CNE1 and the second contact electrode CNE2. The third insulating layer INS3 may prevent the first contact electrode CNE1 and the second contact electrode CNE2 from being exposed to the outside, thus preventing the first contact electrode CNE1 and the second contact electrode CNE2 from being corroded.

Although not illustrated, the fourth insulating layer INS4 for planarization of the display element layer DPL may be further disposed on the third insulating layer INS3.

As illustrated in <FIG>, the reflective pattern RP and the first and second electrodes REL1 and REL2 may be disposed on different layers. For example, the first and second electrodes REL1 and REL2 may be disposed under the first insulating layer INS1, and the reflective pattern RP may be disposed over the first insulating layer INS1. Although the reflective pattern RP and the first and second electrodes REL1 and REL2 are disposed on different layers, the reflective pattern RP and the first and second electrodes REL1 and REL2 may include the same material.

Although <FIG> illustrate that the partition wall PW and the bank BNK are formed on the same layer on the passivation layer PSV, the partition wall PW and the bank BNK may be formed on different layers with the first insulating layer INS1 interposed therebetween, as illustrated in <FIG>.

Claim 1:
A display device comprising:
a base layer (BSL) including a display area (DA) and a non-display area (NDA); and
a plurality of pixels (PXL) provided in the display area (DA), and each including a plurality of sub-pixels (SP1, SP2, SP3),
wherein each of the sub-pixels (SP1, SP2, SP3) comprises a pixel circuit layer (PCL) and a display element layer (DPL) disposed on the pixel circuit layer (PCL),
wherein the display element layer (DPL) comprises:
a partition wall (PW) disposed in each of the sub-pixels (SP1, SP2, SP3);
a bank (BNK) disposed between the sub-pixels (SP1, SP2, SP3) adjacent to each other;
a first electrode (REL1) and a second electrode (REL2) disposed on the partition wall (PW) and provided to be spaced apart from each other; and
at least one light emitting element (LD) disposed between the first electrode (REL1) and the second electrode (REL2) and configured to emit light,
characterised in that the display element layer (DPL) further comprises:
a reflective pattern (RP) disposed on the bank (BNK) and
an insulating layer (INS2) disposed on the reflective pattern (RP) .