Patent Description:
The present application relates to, but not limit to a data transmission circuit and method, and a storage device.

A semiconductor storage device usually includes a storage array area and a peripheral circuit area, wherein the storage array area is provided with a storage unit array including a plurality of storage units; the peripheral circuit area is provided with a control circuit for controlling reading and writing and a mode register for storing mode register data. The mode register data stored in the mode register can be read out by the mode register read command.

If, on the premise of meeting the working parameter requirements of a specific type of semiconductor storage device, the time of reading out the mode register data in response to the mode register read command is set to match the time of reading out the array area data in response to the array area data read command, so the timing of the transmission path of reading out the mode register data in response to the mode register read command is the same as the timing of the transmission path of reading out the array area data in response to the array area data read command.

<CIT> discloses memory devices with a signal control mechanism.

<CIT> discloses a semiconductor memory device that can output a mode signal set in a mode register to outside.

To more clearly describe the technical scheme in the embodiments of the present application, the following will briefly introduce the drawings in the description of the embodiments. It is obvious that the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

Data transmission circuit; <NUM>. Mode register data storage unit; <NUM>. Array area data storage unit; <NUM>. Delay module; <NUM>. First storage unit; <NUM>. Controllable delay module; <NUM>. Mode register data processing unit; <NUM>. Mode register; <NUM>. Reference delay unit; <NUM>. Controllable delay unit; <NUM>. Delay unit; <NUM>. First controllable switch unit; <NUM>. First delay unit; <NUM>. Second delay unit; <NUM>. Third delay unit; <NUM>. The first sub-delay unit; <NUM>. The second sub-delay unit; <NUM>. The first read operation delay unit; <NUM>. The column selection control module; <NUM>. The third read operation delay unit; <NUM>. The first-in first-out pointer processing unit; <NUM>. First-in first-out data processing unit; <NUM>. Mode register read command processing unit; <NUM>. Second storage unit; <NUM>. Storage sub-unit; <NUM>. Driver; <NUM>. Command decoding circuit; <NUM>. Array area data processing unit; <NUM>. Storage unit array; <NUM>. First selector; <NUM>. First-in first-out storage unit; <NUM>. Selection module; <NUM>. Third storage unit; <NUM>. First-in first-out memory; <NUM>. Serial-to-parallel conversion circuit; <NUM>. Data driving module; <NUM>. Data terminal; <NUM>. First flip-flop; <NUM>. Second flip-flop; <NUM>. Third flip-flop; <NUM>. Fourth flip-flop; <NUM>. Delay chain; <NUM>. Storage device; and <NUM>. Delay circuit.

In order to facilitate the understanding of the present application, the following will make a more comprehensive description of the present application with reference to the relevant drawings. The preferred embodiment of the present application is shown in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present application. The terminology used in the specification of the present application herein is only for the purpose of describing specific embodiments, and is not intended to limit the present application.

In addition, certain terms used throughout the specification and the following claims refer to specific elements. Those skilled in the art will understand that manufacturers can refer to components with different names. The present application does not intend to distinguish between components with different names but the same function. In the following description and embodiments, the terms "including" and "include" are used openly, and therefore should be interpreted as "including, but not limited to. Likewise, the term "connected" is intended to express an indirect or direct electrical connection. Correspondingly, if one device is connected to another device, the connection can be done through a direct electrical connection, or through an indirect electrical connection between the other equipment and the connector.

It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

Please refer to <FIG>, in an embodiment of the present application, a data transmission circuit <NUM> is provided, including a mode register data storage unit <NUM> and an array area data storage unit <NUM>. The mode register data storage unit <NUM> is configured to output the mode register data MrrData2 in response to a first clock signal MrrClk; the output terminal of the array area data storage unit <NUM> and the output terminal of the mode register data storage unit <NUM> are both connected to the first node A, and the array area data storage unit <NUM> is configured to receive the array area data ArrayData in response to the first pointer signal FifoIn_array, and output the array area data ArrayData in response to the second pointer signal FifoOut_array.

As an example, please continue to refer to <FIG>, by setting the mode register data storage unit <NUM> to output the mode register data MrrData2 in response to the first clock signal MrrClk, wherein before the mode register data storage unit <NUM> outputs the mode register data MrrData2 in response to the first clock signal MrrClk, the mode register data storage unit <NUM> reads the mode register data MrrDatal from the previous data line; then setting the output terminal of the array area data storage unit <NUM> and the output terminal of the mode register data storage unit <NUM> to be both connected to the first node A, and the array area data storage unit <NUM> to receive the array area data ArrayData in response to the first pointer signal FifoIn_array, and to output the array area data ArrayData in response to the second pointer signal FifoOut_array; the differential control of the mode register data storage unit <NUM> and the array area data storage unit <NUM> is realized, so that the time of reading out the mode register data MrrData2 in response to a mode register read command matches the time of reading out the array area data ArrayData in response to an array area data read command, and accurately control the mode register data MrrData and the array area data ArrayData to be output through the respective output channels in turn. The MrrData1 and MrrData2 here can be the same or can match a preset algorithm.

Further, referring to <FIG>, in an embodiment of the present application, the array area data storage unit <NUM> includes eight first storage units <NUM>, and the output terminal of each first storage unit <NUM> is connected to the first node A, and the input terminal of each first storage unit <NUM> is connected to the first data signal line ArrayDataL, wherein, the first data signal line ArrayDataL is used to transmit the array area data ArrayData, so as to realize the accurate control of the transmission of the array area data ArrayData.

Further, continue to refer to <FIG>, in an embodiment of the present application, the driving clock frequency of the first pointer signal FifoIn_array is the same as the driving clock frequency of the second pointer signal FifoOut_array, so as to set the transmission rate of the input data and output data of the array area data storage unit <NUM> to be consistent, and realize the data in and out at the same time.

Further, referring to <FIG>, in an embodiment of the present application, the data transmission circuit <NUM> further includes a serial-to-parallel conversion circuit <NUM> and a data driving module <NUM>. The input terminal of the serial-to-parallel conversion circuit <NUM> is connected to the first node A; the data driving module <NUM> is connected to the output terminal of the serial-to-parallel conversion circuit <NUM>, and is used to output the mode register data MrrData2 or the array area data ArrayData. By using the serial-to-parallel conversion circuit <NUM> to convert the received data into serial data and then provide the serial data to the data driving module <NUM> for output, it is convenient to improve the efficiency of data transmission.

Further, referring to <FIG>, in an embodiment of the present application, the data transmission circuit <NUM> further includes a mode register data processing unit <NUM>. The mode register data processing unit <NUM> includes a first-in first-out pointer processing unit <NUM>, a first-in first-out data processing unit <NUM> and a mode register read command processing unit <NUM>; wherein the first-in first-out pointer processing unit <NUM> is configured to generate a third pointer signal MrFifoIn and a fourth pointer signal MrFifoOut in response to the mode register read command MrrCmd; the first-in first-out data processing unit <NUM> is connected to both the first-in first-out pointer processing unit <NUM> and the mode register data storage unit <NUM>, and the first-in first-out data processing unit <NUM> is configured to read out the mode register data MrrData0 from the mode register <NUM> in response to the third pointer signal MrFifoIn, and is also configured to output the mode register data MrrData1 to the mode register data storage unit <NUM> in response to the fourth pointer signal MrFifoOut; and the mode register read command processing unit <NUM> is configured to generate the first clock signal MrrClk according to the received mode register read command MrrCmd, the second clock signal Clk, and the preset read delay signal Read Latency. By controlling the time when the mode register data MrrData1 is output through the mode register data storage unit <NUM>, according to the mode register read command MrrCmd, the second clock signal Clk and the preset read delay signal Read Latency, it can accurately control the mode register data MrrData0 and the array area data ArrayData to be output through their respective data output channels in turn. The MrrData0 and MrrData1 here can be the same or can match a preset algorithm.

As an example, please continue to refer to <FIG>, in an embodiment of the present application, the driving clock frequency of the third pointer signal MrFifoIn is the same as the driving clock frequency of the fourth pointer signal MrFifoOut, so as to accurately control the time difference between the read data and the output data of the first-in first-out data processing unit <NUM>.

Further, referring to <FIG> and <FIG>, in an embodiment of the present application, the data transmission circuit <NUM> further includes a command decoding circuit <NUM> and an array area data processing unit <NUM>. The first output terminal of the command decoding circuit <NUM> is connected to both the input terminal of the mode register read command processing unit <NUM> and the input terminal of the first-in first-out pointer processing unit <NUM>, and the command decoding circuit <NUM> is configured to receive the read command Read, decode the read command Read and determine whether the read command is the mode register read command MrrCmd. If so, the mode register read command MrrCmd is output, otherwise, the array area data read command ReadCmd is generated. The input terminal of the array area data processing unit <NUM> is connected to the second output terminal of the command decoding circuit <NUM>, and the array area data processing unit <NUM> is configured to read out the array area data ArrayData from the storage unit array <NUM>, in response to the array area data read command ReadCmd,and provide the array area data ArrayData to the array area data storage unit <NUM>. In this embodiment, the mode register data MrrData2 and the array area data ArrayData are read out via a data transmission circuit <NUM>, compared with reading out the mode register data MrrData and array area data ArrayData through different data transmission paths, the integration of semiconductor storage devices is further improved.

As an example shown in <FIG>, in an embodiment of the present application, the selection module <NUM> is configured to receive the mode register data MrrData1 and the array area data ArrayData; and the output terminal of the selection module <NUM> is connected to the first-in first-out storage unit <NUM>; the first-in first-out storage unit <NUM> includes j third storage units <NUM> connected in parallel, j is a positive integer, and j can be set to be equal to the bit width of the array area data ArrayData. The mode register data MrrData1 and the array area data ArrayData are sequentially output through the first-in first-out storage unit <NUM>, the serial-to-parallel conversion circuit <NUM>, the data driving module <NUM> and the data terminal <NUM> by controlling the switching of the selection module <NUM>. Referring to <FIG> and <FIG> at the same time, the mode register data MrrData0 and the array area data ArrayData in <FIG> are transmitted to the serial-to-parallel conversion circuit <NUM> through different FIFOs (first-in first-out registers); the mode register data MrrData0 and the array area data ArrayData in <FIG> are transmitted to the serial-to-parallel conversion circuit <NUM> through the same FIFO. The technical scheme of <FIG> is more flexible for the timing control of the data transmission circuit, and the technical scheme of <FIG> can make the area of the data transmission circuit smaller.

As an example shown in <FIG>, in an embodiment of the present application, the first-in first-out data processing unit <NUM> includes a second storage unit <NUM>, and the output terminal of each second storage unit <NUM> is connected to the second node O; the second storage unit <NUM> includes a storage subunit <NUM> and a driver <NUM>, the input terminal of the driver <NUM> is connected to the output terminal of the storage subunit <NUM>; the storage subunit <NUM> is driven by the third pointer signal MrFifoIn to receive the mode register data MrrData0; and the driver <NUM> is driven by the fourth pointer signal MrFifoOut to output the mode register data MrrData1. So as to make the first-in first-out data processing unit <NUM> cooperate with the first-in first-out pointer processing unit <NUM> to achieve the accurate control of the time of reading out the mode register data MrrData1 in response to the mode register read command MrrCmd, thereby the time of reading out the mode register data MrrData <NUM> in response to the mode register read command MrrCmd can be accurately controlled to match the time of reading out the array area data ArrayData in response to the array area data read command ReadCmd.

As an example, please refer to <FIG>, in an embodiment of the present application, the data input terminal of each storage subunit <NUM> is connected to the mode register <NUM>, so that each storage subunit <NUM> reads out the mode register data MrrData0 from the mode register <NUM> in response to the third pointer signal MrFifoIn, each driver <NUM> outputs the mode register data MrrData1 in response to the fourth pointer signal MrFifoOut.

As an example shown in <FIG>, in an embodiment of the present application, the driving clock frequency of the third pointer signal MrFifoIn and the driving clock frequency of the fourth pointer signal MrFifoOut are the same, so as to accurately control the time difference between the read data and the output data of the first-in first-out data processing unit <NUM>.

Referring to <FIG>, in an embodiment of the present application, a data transmission circuit <NUM> is provided, including a controllable delay module <NUM>, a mode register data processing unit <NUM>, an array area data storage unit <NUM>, and a mode register data storage unit <NUM>. The controllable delay module <NUM> is configured to generate a preset read delay signal Read Latency in response to the mode register read command MrrCmd; the mode register data processing unit <NUM> is connected to the controllable delay module, and the mode register data processing unit <NUM> is configured to read out the mode register data MrrData0 from the mode register <NUM> in response to the mode register read command MrrCmd, and is also configured to output the mode register data MrrData1 to the mode register data storage unit <NUM> in response to the preset read delay signal Read Latency; the output terminal of the array area data storage unit <NUM> and the output terminal of the mode register data storage unit <NUM> are both connected to the first node A, and the array area data storage unit <NUM> is configured to receive array area data ArrayData in response to the first pointer signal FifoIn_array, and is also configured to output the array area data ArrayData in response to the second pointer signal FifoOut_array; and the mode register data storage unit <NUM> is configured to output the mode register data MrrData2 in response to the first clock signal MrrClk.

As an example, please continue to refer to <FIG>, by setting the controllable delay module <NUM> to generate the preset read delay signal Read Latency in response to the mode register read command MrrCmd, the mode register data processing unit <NUM> reads out the mode register data MrrData0 from the mode register <NUM> in response to the mode register read command MrrCmd, and outputs the mode register data MrrData1 to the mode register data storage unit <NUM> in response to the preset read delay signal Read Latency; and by setting the mode register data storage unit <NUM> to output the mode register data MrrData2 in response to the first clock signal MrrClk, the output terminal of the array area data storage unit <NUM> and the output terminal of the mode register data storage unit <NUM> to be both connected to the first node A, and the array area data storage unit <NUM> to receive the array area data ArrayData in response to the first pointer signal FifoIn_array, and to output the array area data ArrayData in response to the second pointer signal FifoOut_array, the differential control of the mode register data storage unit <NUM> and the array area data storage unit <NUM> is realized, so that the time of reading out the mode register data MrrData2 in response to the mode register read command MrrCmd matches the time of reading out the array area data ArrayData in response to the array area data read command ReadCmd, so as to accurately control the mode register data MrrData2 and array area data ArrayData to be output through their respective output channels in turn. Once the operation delay of the controllable delay module <NUM> in the present application is determined, it is less affected by changes in the working environment, which can effectively avoid control errors in the data transmission path due to the influence of the working environment; and the operation delay of the controllable delay module <NUM> can control and adjust to meet the working parameter requirements of different types of semiconductor storage devices.

As an example, please continue to refer to <FIG>, in an embodiment of the present application, the time difference between the starting time when the mode register data processing unit <NUM> outputs the mode register data MrrData1 and the time when the controllable delay module <NUM> receives the mode register read command MrrCmd is the first preset threshold, so that the time of reading out the mode register data MrrData1 in response to the mode register read command MrrCmd matches the time of reading out the array area data ArrayData in response to the array area data read command ReadCmd.

Further, referring to <FIG>, in an embodiment of the present application, the controllable delay module <NUM> includes a reference delay unit <NUM> and a controllable delay unit <NUM>. The reference delay unit <NUM> is configured to generate an initial preset read delay signal Read Latency in response to the mode register read command MrrCmd; the controllable delay unit <NUM> is connected to the output terminal of the reference delay unit <NUM> and the input terminal of the mode register data processing unit <NUM>, and the controllable delay unit <NUM> is configured to generate a preset read delay signal Read Latency after delaying the preset delay time from the moment of receiving the initial preset read delay signal Read Latency, wherein, the sum of the operation delay of the controllable delay unit <NUM> and the operation delay of the reference delay unit <NUM> is equal to the first preset threshold. By setting the sum of the operation delay of the reference delay unit <NUM> and the operation delay of the controllable delay unit <NUM> to be equal to the first preset threshold, the operation delay range of the controllable delay unit <NUM> is reduced to improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module <NUM> to the first preset threshold.

Further, referring to <FIG>, in an embodiment of the present application, the controllable delay unit <NUM> includes three delay units <NUM> connected in series; wherein, two delay units <NUM> each are connected in parallel with a first controllable switch unit <NUM>; wherein by controlling the on and off of each first controllable switch unit <NUM>, the number of the delay units <NUM> in the controllable delay unit <NUM> connected in series between the reference delay unit <NUM> and the mode register data processing unit <NUM> is changed to adjust the operation delay of the controllable delay unit <NUM>, so as to realize the gradient control of the operation delay of the controllable delay unit <NUM>, to improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module <NUM> to the first preset threshold.

As an example, please refer to <FIG>, in an embodiment of the present application, the array area data storage unit <NUM> includes a plurality of first storage units <NUM>, and the output terminal of each first storage unit <NUM> is connected to the first node A, the input terminal of each first storage unit <NUM> is connected to the first data signal line ArrayDataL, and the first data signal line ArrayDataL is used to transmit the array area data ArrayData, so as to realize the accurate control of the transmission of the array area data ArrayData.

As an example, please continue to refer to <FIG>, in an embodiment of the present application, the driving clock frequency of the first pointer signal FifoIn_array and the driving clock frequency of the second pointer signal FifoOut_array are the same, so as to set the transmission rate of the input data and the output data of the array area data storage unit <NUM> to be consistent, and realize the data in and out at the same time.

Further, referring to <FIG>, in an embodiment of the present application, the mode register data processing unit <NUM> includes a first-in first-out pointer processing unit <NUM>, a first-in first-out data processing unit <NUM>, and a mode register read command processing unit <NUM>. The mode register read command processing unit <NUM> is configured to generate the first clock signal MrrClk according to the received mode register read command MrrCmd, the second clock signal Clk and the preset read delay signal Read Latency; the first-in first-out pointer processing unit <NUM> is configured to generate the third pointer signal MrFifoIn and the fourth pointer signal MrFifoOut in response to the mode register read command MrrCmd; the first-in first-out data processing unit <NUM> is connected with the first-in first-out pointer processing unit <NUM> and the mode register data storage unit <NUM>, and the first-in first-out data processing unit <NUM> is configured to read out the mode register data MrrData0 from the mode register <NUM> in response to the third pointer signal MrFifoIn, and is also configured to output the mode register data MrrData1 to the mode register data storage unit <NUM> in response to the fourth pointer signal MrFifoOut.

As an example, please continue to refer to <FIG>, in an embodiment of the present application, the driving clock frequency of the third pointer signal MrFifoIn and the driving clock frequency of the fourth pointer signal MrFifoOut are the same, so as to accurately control the time difference between the read data and the output data of the first-in first-out data processing unit <NUM>.

Further, referring to <FIG>, in an embodiment of the present application, the data transmission circuit <NUM> further includes a command decoding circuit <NUM> and an array area data processing unit <NUM>, wherein a first output terminal of the command decoding circuit <NUM> is connected to the input terminal of the mode register read command processing unit <NUM> and the input terminal of the first-in first-out pointer processing unit <NUM>, and the command decoding circuit <NUM> is configured to receive the read command, decode the read command Read and determine whether the read command Read is the mode register read command MrrCmd. If so, the mode register read command MrrCmd is output, otherwise, the array area data read command ReadCmd is generated. The input terminal of the array area data processing unit <NUM> is connected to a second output terminal of the command decoding circuit <NUM>, and the array area data processing unit <NUM> is configured to read out the array area data ArrayData from the storage unit array <NUM> in response to the array area data read command ReadCmd to provide the array area data ArrayData to the array area data storage unit <NUM>.

As an example, please refer to <FIG>. It can be set that the reference delay unit <NUM> includes several sub-delay units connected in series, wherein the sub-delay units can be used to copy the operation delay of the functional unit with fixed delay time in the path of array area data read out by the array area data processing unit <NUM> in response to the array area data read command, and set the delay time of the operation delay of the controllable delay unit to match the delay time of the functional unit with variable delay time in the path of the array area data read out by the array area data processing unit <NUM> in response to the array area data reading command, so as to realize the gradient control of the operation delay of the controllable delay unit, to improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module to the first preset threshold.

Please refer to <FIG>. In an embodiment of the present application, a data transmission circuit <NUM> is provided, which includes a delay module <NUM>, a mode register data processing unit <NUM>, an array area data storage unit <NUM>, and a mode register data storage unit <NUM>. The delay module <NUM> is configured to generate a preset read delay signal Read Latency, after delaying a first preset time from the moment of receiving the mode register read command MrrCmd; the mode register data processing unit <NUM> is connected to the delay module <NUM> and the mode register data storage unit <NUM>, and is configured to read out the mode register data MrrData0 from the mode register <NUM> in response to the mode register read command MrrCmd, and is also configured to output the mode register data MrrData1 to the mode register data storage unit <NUM> in response to the preset read delay signal Read Latency; and the output terminal of the array area data storage unit <NUM>, and the output terminal of the mode register data storage unit <NUM> are both connected to the first node A, and the array area data storage unit <NUM> is configured to receive the array area data ArrayData in response to the first pointer signal FifoIn_array, and is also configured to output the array area data ArrayData in response to the second pointer signal FifoOut_array; wherein the mode register data storage unit <NUM> is configured to output the mode register data MrrData2 in response to the first clock signal MrrClk.

As an example, please refer to <FIG>, by setting the delay module <NUM> to generate the preset read delay signal Read Latency, after delaying the first preset time from the moment of receiving the mode register read command MrrCmd, the mode register data processing unit <NUM> reads out the mode register data MrrData0 from the mode register <NUM> in response to the mode register read command MrrCmd, and outputs the mode register data MrrData1 to the mode register data storage unit <NUM> in response to the preset read delay signal Read Latency; and by setting the mode register data storage unit <NUM> to output the mode register data MrrData2 in response to the first clock signal MrrClk, the output terminal of the array area data storage unit <NUM> and the output terminal of the mode register data storage unit <NUM> to be both connected to the first node, and the array area data storage unit <NUM> to receive the array area data ArrayData in response to the first pointer signal FifoIn_array and to output the array area data ArrayData in response to the second pointer signal FifoOut_array, the differential control of the mode register data storage unit <NUM> and array area data storage unit <NUM> is realized, so that the time of reading out the mode register data MrrData2 in response to the mode register read command MrrCmd matches the time of reading out the array area data ArrayData in response to an array area data read command ReadCmd, so as to accurately control the mode register data MrrData2 and array area data ArrayData to be output through their respective output channels in turn.

Further, referring to <FIG>, in an embodiment of the present application, the delay module <NUM> includes a first delay unit <NUM>, a second delay unit <NUM>, and a third delay unit <NUM>. The first delay unit <NUM> is configured to generate a first preset read delay signal, after delaying a second preset time from the moment of receiving the mode register read command MrrCmd; the second delay unit <NUM> is connected to the output terminal of the first delay unit <NUM>, and is configured to generate a second preset read delay signal, after delaying a third preset time from the moment of receiving the first preset read delay signal, and the third preset time is equal to the operation delay of the column selection control module (not shown); the third delay unit <NUM> is connected to the output terminal of the second delay unit <NUM> and the input terminal of the mode register data processing unit 20and is configured to generate a preset read delay signal Read Latency, after delaying a fourth preset time from the moment of receiving the second preset read delay signal; wherein, the sum of the second preset time, the third preset time, and the fourth preset time is equal to the first preset time. This embodiment can avoid the influence of the operation delay of the column selection control module in a specific type of semiconductor storage device on the transmission circuit.

Further, please refer to <FIG>, in an embodiment of the present application, the third delay unit <NUM> includes a first sub-delay unit <NUM> and a second sub-delay unit <NUM>. The first sub-delay unit <NUM> is connected to the output terminal of the second delay unit <NUM>, and is configured to generate a third preset read delay signal, after delaying a fifth preset time from the moment of receiving the second preset read delay signal, and the fifth preset time is equal to the operation delay of the read-write amplifier; the second sub-delay unit <NUM> is connected to the output terminal of the first sub-delay unit <NUM> and the input terminal of the mode register data processing unit <NUM>, and is configured to generate the preset read delay signal Read Latency, after delaying a sixth preset time from the moment of receiving the third preset read delay signal; wherein the sum of the fifth preset time and the sixth preset time is equal to the fourth preset time. This embodiment can avoid the influence of the operation delay of the read-write amplifier in a specific type of semiconductor storage device on the transmission circuit.

As an example, please continue to refer to <FIG>, in an embodiment of the present application, the array area data storage unit <NUM> includes a plurality of first storage units <NUM> (not shown in <FIG>), wherein the output terminal of each first storage unit <NUM> is connected to the first node A, the input terminal of each first storage unit <NUM> is connected to the first data signal line, and the first data signal line is used to transmit array area data ArrayData.

As an example, please continue to refer to <FIG>, in an embodiment of the present application, the driving clock frequency of the first pointer signal FifoIn_array and the driving clock frequency of the second pointer signal FifoOut_array are the same.

Further, referring to <FIG>, in an embodiment of the present application, the mode register data processing unit <NUM> includes a first-in first-out pointer processing unit <NUM>, a first-in first-out data processing unit <NUM>, and a mode register read command processing unit <NUM>. The mode register read command processing unit <NUM> is configured to generate the first clock signal MrrClk according to the received mode register read command MrrCmd, the second clock signal Clk and the preset read delay signal Read Latency; the first-in first-out pointer processing unit <NUM> is configured to generate the third pointer signal MrFifoIn and the fourth pointer signal MrFifoOut in response to the mode register read command MrrCmd; the first-in first-out data processing unit <NUM> is connected with the first-in first-out pointer processing unit <NUM> and the mode register data storage unit <NUM>, and is configured to read out the mode register data MrrData0 from the mode register <NUM> in response to the third pointer signal MrFifoIn, and is also configured to output the mode register data MrrData1 to the mode register data storage unit <NUM> in response to the fourth pointer signal MrFifoOut. In an embodiment of the present application, the driving clock frequency of the third pointer signal MrFifoIn and the driving clock frequency of the fourth pointer signal MrFifoOut are the same.

Further, please refer to <FIG> and <FIG>, in an embodiment of the present application, the data transmission circuit <NUM> further includes a command decoding circuit <NUM> and an array area data processing unit <NUM>, a first output terminal of the command decoding circuit <NUM> is connected to both an input terminal of the mode register read command processing unit <NUM> and an input terminal of the first-in first-out pointer processing unit <NUM>, and the command decoding circuit <NUM> is configured to receive the read command, decode the read command Read and determine whether the read command Read is the mode register read command MrrCmd. If so, the mode register read command MrrCmd is output, otherwise, the array area data read command ReadCmd is generated. The input terminal of the array area data processing unit is connected to the second output terminal of the command decoding circuit <NUM>, and the array area data processing unit is configured to read out the array area data ArrayData from the storage unit array <NUM>, in response to the array area data read command ReadCmd, and provide the array area data ArrayData to the array area data storage unit <NUM>.

As an example, please continue to refer to <FIG>, the delay time of the array area data read out by the array area data processing unit <NUM> in response to the array area data read command can be equivalent to the sum of the delay time of the first read operation delay unit <NUM> and the operation delay of column selection control module <NUM> and the delay time of the third read operation delay unit <NUM>. By setting the second delay unit <NUM> to copy the operation delay of the column selection control module <NUM>, setting the delay time of the first delay unit <NUM> to match the delay time of the first read operation delay unit <NUM>, and setting the delay time of the third delay unit <NUM> to match the delay time of the third read operation delay unit <NUM>, so that the time of reading out the setting parameter MrrData2 in response to the mode register read command MrrCmd matches the time of reading out the array area data in response to the array area data read command.

Further, please continue to refer to <FIG>, in an embodiment of the present application, the difference between the operation delay of the array area data processing unit <NUM> and the first preset time can be set as a preset threshold, so as to meet the working parameter requirements of specific types of semiconductor storage devices, such as dynamic random access memory (DRAM).

As an example, please refer to <FIG>, in an embodiment of the present application, the third pointer signal MrFifoIn can be set to have the same frequency as the mode register read command MrrCmd, the fourth pointer signal MrFifoOut can be set to have the same frequency as the preset read delay signal Read Latency,. the time difference between the driving time of the preset read delay signal Read Latency and the driving time of the mode register read command MrrCmd is set to be the first preset time Td, and the difference between the operation delay of the array area data processing unit <NUM> and the first preset time is set to be the preset threshold, so that the time of reading out the setting parameter MrrData2 in response to the mode register read command MrrCmd matches the time of reading out the array area data ArrayData in response to the array area data read command ReadCmd.

As an example, in an embodiment of the present application, the preset threshold may be set to an integer multiple of the column refresh cycle to meet the working parameter requirements of specific types of semiconductor storage devices, such as LPDDR4.

<FIG> is a delay circuit <NUM> in a data transmission circuit for reading out the setting parameter MrrData0 from the mode register <NUM> in response to the mode register read command MrrCmd, and <FIG> is a schematic diagram of the working time sequence of <FIG>. The delay circuit <NUM> includes a first flip-flop <NUM>, a second flip-flop <NUM>, a third flip-flop <NUM>, a fourth flip-flop <NUM>, and a delay chain <NUM>. The delay chain <NUM> is configured to generate the first clock signal Clk1, the second clock signal Clk2, the third clock signal Clk3, the fourth clock signal Clk4, and the preset read delay signal Read Latency in response to the mode register read command MrrCmd, wherein the first flip-flop <NUM> is configured to receive the setting parameter MrrData0 in response to the first clock signal Clk1, and the second flip-flop <NUM> is configured to receive data provided by the first flip-flop <NUM> in response to the second clock signal Clk2, the third flip-flop <NUM> is configured to receive data provided by the second flip-flop <NUM> in response to the third clock signal Clk3, and the fourth flip-flop <NUM> is configured to receive data provided by the third flip-flop <NUM> and output the setting parameter MrrData1 in response to the fourth clock signal Clk4. By controlling the driving time of the first clock signal Clk1, the second clock signal Clk2, the third clock signal Clk3, the fourth clock signal Clk4, and the preset read delay signal Read Latency generated by the delay chain <NUM>, the time of reading out the setting parameter MrrData2 in response to mode register read command is controlled to match the time of reading out the array area data ArrayData in response to the array area data read command ReadCmd.

Refer to <FIG> at the same time. Each clock (Clk1, Clk2, Clk3, Clk4) in <FIG> needs to be adjusted to ensure the correct timing of MrrData1 to MrrData2. In comparison, <FIG> only needs to adjust the timing from MrrCmd to Read Latency, and the technical scheme of <FIG> is easier to adjust.

In an embodiment of the present application, a storage device is provided, including a storage unit array <NUM>, a mode register <NUM>, and any data transmission circuit in the embodiments of the present application; wherein, the storage unit array <NUM> is configured to store the array area data ArrayData, and the mode register <NUM> is configured to store the mode register data MrrData0. This embodiment realizes the differential control of the mode register data storage unit <NUM> and the array area data storage unit <NUM>, so that the time of reading out the mode register data MrrData2 in response to the mode register read command matches the time of reading out the array area data ArrayData in response to an array area data read command, so as to accurately control the mode register data MrrData2 and array area data ArrayData to be output through their respective output channels in turn.

Referring to <FIG>, a data transmission method is provided according to an embodiment of the present application, the data transmission method includes:.

As an example, please continue to refer to <FIG>, by outputting the mode register data based on the mode register data storage unit in response to the first clock signal, and receiving the array area data based on the array area data storage unit in response to the first pointer signal and outputting the array area data based on the array area data storage unit in response to the second pointer signal, wherein the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the differential control of the mode register data storage unit and the array area data storage unit is realized, so that the time of reading out the mode register data in response to the mode register read command matches the time of reading out the array area data in response to the array area data read command, so as to accurately control the mode register data and the array area data to be output through their respective output channels in turn.

Please refer to <FIG>, in an embodiment of the present application, a data transmission method is provided, including:.

As an example, please continue to refer to <FIG>, based on the controllable delay module responding to the mode register read command to generate the preset read delay signal, so that the mode register data processing unit responds to the mode register read command to read out the mode register data from the mode register, and responds to the preset read delay signal to output the mode register data to the mode register data storage unit; based on the mode register data storage unit responding to the first clock signal to output the mode register data, and based on the array area data storage unit being able to respond to the first pointer signal to receive the array area data and respond to the second pointer signal to output the array area data, wherein the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the differential control of the mode register data storage unit and the array area data storage unit is realized, so that the time of reading out the mode register data in response to the mode register read command matches the time of reading out the array area data in response to the array area data read command, so as to accurately control the mode register data and the array area data to output through their respective output channels in turn. Once the operation delay of the controllable delay module in the present application is determined, it is less affected by changes in the working environment, which can effectively avoid control errors in the data transmission path due to the influence of the working environment; and the operation delay of the controllable delay module can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices. Once the operation delay of the controllable delay module is determined, it is less affected by changes in the working environment, which can effectively avoid control errors in the data transmission path due to the influence of the working environment; and the operation delay of the controllable delay module can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices.

Referring to <FIG>, in an embodiment of the present application, a data transmission method is provided, including:.

As an example, please continue to refer to <FIG>, based on the delay module generating the preset read delay signal after delaying the first preset time from the moment of receiving the mode register read command; so that the mode register data processing unit responds to the mode register read command to read out the mode register data from the mode register, and responds to the preset read delay signal to output the mode register data to the mode register data storage unit; based on the array area data storage unit responding to the first pointer signal to receive the array area data, and responding to the second pointer signal to output the array area data; and based on the mode register data storage unit responding to the first clock signal to output the mode register data; wherein, the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node; the differential control of the mode register data storage unit and the array area data storage unit is realized, so that the time of reading out the mode register data in response to the mode register read command matches the time of reading out the array area data in response to the array area data read command, so as to accurately control the mode register data and the array area data to be output through their respective output channels in turn.

For the specific definition of the data transmission method in the above embodiment, please refer to the above definition of the data transmission circuit, which will not be repeated here.

It should be understood that although the various steps in the flowcharts of <FIG> are displayed in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless there is a clear description in this application, there is no strict order for the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in <FIG> may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The order of execution is not necessarily performed sequentially, but may be performed alternately with other steps or at least a part of the steps or stages in other steps.

A person of ordinary skill in the art can understand that all or part of the processes of realizing the above-mentioned embodiment methods can be implemented by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, when the computer program is executed, it may include the processes of the above-mentioned embodiments of the methods. Wherein, any reference to memory, storage, database or other media used in the embodiments provided in the present application may include non-volatile and/or volatile memory. Non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not a limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc..

Please note that the above-mentioned embodiments are only for illustrative purposes and are not meant to limit the present application.

The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the various technical features of the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be the scope recorded in this specification.

Claim 1:
A data transmission circuit (<NUM>), comprising:
a mode register data processing unit (<NUM>), comprising a mode register read command processing unit (<NUM>), wherein the mode register read command processing unit (<NUM>) is configured to generate a first clock signal according to a received mode register read command, a second clock signal, and a preset read delay signal;
a mode register data storage unit (<NUM>), configured to output mode register data in response to the first clock signal; and
an array area data storage unit (<NUM>), wherein an output terminal of the array area data storage unit (<NUM>) and an output terminal of the mode register data storage unit (<NUM>) are both connected to a first node, and the array area data storage unit (<NUM>) is configured to receive array area data in response to a first pointer signal, and output the array area data in response to a second pointer signal.