Patent Description:
The semiconductor device may be electrically connected to another semiconductor device or a printed circuit board by a through via. Through vias can be used in three-dimensional chip mounting and may deliver faster transfer speeds than conventional solder balls or solder bumps. As semiconductor devices become highly integrated, there is a demand for the development of physically and electrically reliable through vias. <CIT> and <CIT> disclose integrated circuit devices having through silicon via structures and methods of manufacturing the same.

<CIT> describes an integrated circuit device including a through-substrate via.

According to the present invention there is provided a semiconductor device according to claim <NUM>.

Some example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

An aspect of the present disclosure is related to a semiconductor device that includes a crystalline semiconductor substrate. The device may also include an etch stop layer disposed on a first surface of the crystalline semiconductor substrate. The device may also include a conductive through via structure penetrating the crystalline semiconductor substrate and the etch stop layer. The device may also include an insulating separation layer disposed between the conductive through via structure and the crystalline semiconductor substrate. A lower portion of the insulating separation layer may contact a portion of the etch stop layer.

Hereinafter, some embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and duplicate description thereof will be omitted.

<FIG> is a cross-sectional view illustrating a semiconductor device in accordance with example embodiments.

Referring to <FIG>, a semiconductor device may include a semiconductor substrate <NUM>, a wiring layer <NUM>, an etch stop layer <NUM>, a separating layer <NUM>, and a through via structure <NUM>. The semiconductor device may be a semiconductor chip including a memory chip, a logic chip, or a combination thereof. The semiconductor substrate <NUM> may be a wafer level or chip level substrate. The semiconductor substrate <NUM> may be a crystalline semiconductor substrate. For example, the semiconductor substrate <NUM> may be in a single crystal state. The semiconductor substrate <NUM> may be formed of silicon, germanium, or silicon-germanium. The semiconductor substrate <NUM> may have a first surface <NUM> and a second surface <NUM> opposite each other. The first surface <NUM> of the semiconductor substrate <NUM> may be a front surface, and the second surface <NUM> may be a rear surface. The second surface <NUM> of the semiconductor substrate <NUM> may be parallel to the first surface <NUM>.

The etch stop layer <NUM> and the wiring layer <NUM> may be provided on the first surface <NUM> of the semiconductor substrate <NUM>, i.e., layers <NUM>, <NUM> may be provided vertically beneath first surface <NUM> and/or be in contact with first surface <NUM>. It shall be understood that the term "on," as used throughout this disclosure, is to be construed broadly with a meaning understood from the context and example illustrations of this disclosure, e.g., "on" shall encompass a meaning of "on" something from above and "on" something from below and does not require the designated items to be directly adjacent to each other. The etch stop layer <NUM> may be interposed between the semiconductor substrate <NUM> and the wiring layer <NUM>. As another example, the wiring layer <NUM> may include a plurality of insulating layers, and the etch stop layer <NUM> may be interposed between the insulating layers.

The through via structure <NUM> may be formed in the semiconductor substrate <NUM>, and may penetrate at least a portion of the wiring layer <NUM> and the etch stop layer <NUM>. The through via structure <NUM> may be a conductive through via structure. The separating layer <NUM> may be interposed between the through via structure <NUM> and the semiconductor substrate <NUM>. The separating layer <NUM> may be an insulating separation layer. The connection terminal <NUM> may be provided on the bottom surface of the wiring layer <NUM>. The connection terminal <NUM> may include a solder ball. The connection terminal <NUM> may include a conductive material, for example, metal. The connection terminal <NUM> may include, for example, tin, silver, bismuth, and/or alloys thereof. The connection terminal <NUM> may be electrically connected to the through via structure <NUM>. In this disclosure, "electrically connected/contact" may mean direct connection/contact or indirect connection/contact via other conductive components. However, the term "contact," "in contact with," or "contacting," used in the physical sense refers to a direct connection (e.g., touching). The through via structure <NUM> and the connection terminal <NUM> may transmit electrical signals to or from a semiconductor device. In the present disclosure, an electrical connection with the semiconductor device may mean an electrical connection with at least one of the integrated circuits of the semiconductor device. Hereinafter, the semiconductor device according to the example embodiments will be described in more detail.

<FIG> is a cross-sectional view illustrating a semiconductor device in accordance with example embodiments, and is an enlarged view of region A of <FIG>. <FIG> is an enlarged view of region B of <FIG>. <FIG> is cross-sectional view for describing a through via structure and a wiring pattern according to example embodiments, and corresponds to an enlarged view of region B of <FIG>. Hereinafter, descriptions repeating explanations described above will be omitted.

Referring to <FIG>, <FIG>, and <FIG>, a semiconductor device includes a crystalline semiconductor substrate <NUM>, integrated circuits <NUM>, a wiring layer <NUM>, an etch stop layer <NUM>, a separating layer <NUM>, and a through via structure <NUM>. The wiring layer <NUM> is disposed on the first surface <NUM> of the semiconductor substrate <NUM>. For example, wiring layer <NUM> may be disposed underneath the first surface <NUM>. Wiring layer <NUM> may also be disposed between first surface <NUM> and connection terminal <NUM> in a vertical direction. The wiring layer <NUM> may include a first insulating layer <NUM>, a second insulating layer <NUM>, and a wiring structure <NUM>. Integrated circuits <NUM> may be provided in the semiconductor substrate <NUM> or on the first surface <NUM> of the semiconductor substrate <NUM>. Integrated circuits <NUM> may include transistors, for example. Integrated circuits <NUM> may include a doped region <NUM>, which may function as a source/drain region of a transistor. The first insulating layer <NUM> may cover the etch stop layer <NUM> and the integrated circuits <NUM>. The first insulating layer <NUM> may be in contact with and/or disposed on a bottom surface of the first surface <NUM>. The first insulating layer <NUM> may include a semiconductor oxide such as silicon oxide, silicon nitride oxide, or silicon carbide oxide. The first insulating layer <NUM> may be amorphous. The first insulating layer <NUM> may be multiple layers. The second insulating layer <NUM> may be provided on the bottom surface of the first insulating layer <NUM>. The second insulating layer <NUM> may include a plurality of stacked second insulating layers <NUM>. The second insulating layer(s) <NUM> may be amorphous. The second insulating layer(s) <NUM> may include a semiconductor oxide such as silicon oxide, silicon nitride oxide, or silicon carbide oxide.

The wiring structure <NUM> is disposed on the first surface <NUM> of the semiconductor substrate <NUM>, and may be provided in the first and second insulating layers <NUM> and <NUM> or between the insulating layers <NUM> and <NUM>. For example, a portion of wiring structure <NUM> may be disposed beneath the first surface <NUM> and be contact with first surface <NUM>. The wiring structure <NUM> may include contact plugs <NUM>, metal vias <NUM>, and wiring patterns <NUM>. The wiring structure <NUM> may include a conductive material, for example, copper or tungsten. The contact plugs <NUM> pass through the first insulating layer <NUM> and may be connected to the integrated circuits <NUM>. The wiring pattern <NUM> may be provided between the insulating layers <NUM> and <NUM>. At least one of the wiring patterns <NUM> may be electrically connected to the contact plug <NUM>. The metal via <NUM> passes through at least one of the second insulating layers <NUM> and may be connected to a corresponding one of the wiring patterns <NUM>.

An etch stop layer <NUM> is provided on the first surface <NUM> of the semiconductor substrate <NUM>. The etch stop layer <NUM> may be in physical contact with the first surface <NUM> of the semiconductor substrate <NUM>. The etch stop layer <NUM> may be provided between any one of the wiring patterns <NUM> and the semiconductor substrate <NUM>. The etch stop layer <NUM> may be interposed between the semiconductor substrate <NUM> and the first insulating layer <NUM>. The etch stop layer <NUM> may include a material different from the semiconductor substrate <NUM> and the first insulating layer <NUM>. The etch stop layer <NUM> may include a material having an etch selectivity with respect to the semiconductor substrate <NUM> and the first insulating layer <NUM>. The etch stop layer <NUM> may include aluminum (Al), silicon (Si), carbon (C), oxygen (O), nitrogen (N), and/or hydrogen (H). For example, the etch stop layer <NUM> may include silicon nitride (SiNx), silicon carbide nitride (SiCxNy), and/or aluminum oxide (AlOx), where x and y are each independently a positive real number.

The through via structure <NUM> is provided in the semiconductor substrate <NUM>, the etch stop layer <NUM>, and the first insulating layer <NUM>. For example, the through hole <NUM> penetrates the semiconductor substrate <NUM>, the etch stop layer <NUM>, and the first insulating layer <NUM>, and the through via structure <NUM> is provided in the through hole <NUM>. The through via structure <NUM> may be connected to the wiring structure <NUM>. For example, the through via structure <NUM> may contact one of the wiring patterns <NUM>. The height H of the through via structure <NUM> may be relatively much greater than the heights of the metal vias <NUM> and the heights of the contact plugs <NUM>. For example, the height H of the through via structure <NUM> may be about <NUM> to about <NUM>.

The through via structure <NUM> may include a barrier pattern <NUM>, a seed pattern <NUM>, and a conductive via <NUM>. The barrier pattern <NUM> may be provided along the sidewall 500c and the bottom surface 500b of the through via structure <NUM>. The barrier pattern <NUM> may be formed between the conductive via <NUM> and the substrate <NUM>, between the conductive via <NUM> and the etch stop layer <NUM>, between the conductive via <NUM> and the first insulating layer <NUM>, and between the conductive via <NUM> and one of the wiring patterns <NUM>. It may be interposed between the conductive via <NUM> and any one of the wiring patterns <NUM>. The barrier pattern <NUM> may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium, cobalt, and alloys thereof.

The seed pattern <NUM> may extend along the barrier pattern <NUM> on the barrier pattern <NUM>. The seed pattern <NUM> may be interposed between the barrier pattern <NUM> and the conductive via <NUM>. The seed pattern <NUM> may include a conductive material such as metal. The seed pattern <NUM> may include, for example, copper, tungsten, manganese, titanium, or an alloy thereof.

The conductive via <NUM> is provided on the seed pattern <NUM> and fills the through hole <NUM>. The conductive via <NUM> may include a metal such as copper or tungsten. The top surface of the conductive via <NUM> may be disposed at substantially the same level as the top surface of the seed pattern <NUM>, the top surface of the barrier pattern <NUM>, and the top surface of the separating layer <NUM>. It shall be appreciated that terms described as "substantially the same," "substantially equal," and "substantially planar," may be exactly the same, equal, planar, or at the same level or they may be the same, equal, planar, or at the same level within acceptable variations that may occur, for example, due to manufacturing processes.

As shown in <FIG>, the wiring pattern <NUM> may include a barrier metal film <NUM>, a seed metal film <NUM>, and a metal pattern <NUM>. The metal pattern <NUM> may have a first surface 254a and a second surface 254b opposite each other, for example, an upper surface and a lower surface. The first surface 254a of the metal pattern <NUM> may face the first surface <NUM> of the semiconductor substrate <NUM>. The metal pattern <NUM> may include copper or tungsten. The barrier metal film <NUM> and the seed metal film <NUM> may be interposed between the metal pattern <NUM> and the first insulating layer <NUM>. For example, a barrier metal film <NUM> may be interposed between the first surface 254a of the metal pattern <NUM> and the first insulating layer <NUM>, and between the metal pattern <NUM> and the through via structure <NUM>. The through via structure <NUM> may physically contact the barrier metal film <NUM>. For example, the barrier pattern <NUM> (barrier layer) may physically contact the barrier metal film <NUM>. The barrier metal film <NUM> may further extend on the side surface 254c of the metal pattern <NUM> to be interposed between the metal pattern <NUM> and the corresponding one of the second insulating layers <NUM>. The barrier metal film <NUM> may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The seed metal film <NUM> may be provided between the metal pattern <NUM> and the barrier metal film <NUM>. In one embodiment, the seed metal film <NUM> covers the first surface 254a (uppermost surface) and the side surface 254c of the metal pattern <NUM>, and does not cover the second surface 254b (lowermost surface) of the metal pattern <NUM>. The seed metal film <NUM> may include, for example, copper, manganese, titanium, or an alloy thereof.

As shown in <FIG>, the bottom surface 500b of the through via structure <NUM> may be rounded or chamfered. The bottom surface 500b of the through via structure <NUM> may correspond to the bottom surface of the barrier pattern <NUM> (barrier layer). The bottom surface 500b of the through via structure <NUM> may be convex downward. The bottom surface 500b of the through via structure <NUM> may have a center portion and an edge portion. The edge portion may be interposed between the center portion and the sidewall 500c of the through via structure <NUM> in a plan view. The center portion may be disposed at a lower level than the edge portion. As the bottom surface 500b of the through via structure <NUM> is rounded, a contact area between the through via structure <NUM> and the wiring pattern <NUM> may increase. Accordingly, the through via structure <NUM> and the wiring pattern <NUM> may be electrically connected. For example, the through via structure <NUM> may further extend into the seed metal film <NUM> so that the barrier pattern <NUM> contacts the seed metal film <NUM>. As another example, the bottom surface 500b of the through via structure <NUM> may be provided in the barrier metal film <NUM>, and the through via structure <NUM> may not extend all the way to contact the seed metal film <NUM>.

As shown in <FIG>, the bottom surface 500b of the through via structure <NUM> may be substantially flat, smooth, or planar. The center portion of the bottom surface 500b of the through via structure <NUM> may be disposed at substantially the same level as the edge portion of the bottom surface 500b. As shown in this embodiment, the through via structure <NUM> contacts the barrier metal film <NUM>, and does not contact the seed metal film <NUM> or the metal pattern <NUM>.

As illustrated in <FIG>, the wiring pattern <NUM> may include a plurality of wiring patterns <NUM>. For simplicity, the metal pattern <NUM>, the seed metal film <NUM>, and the barrier metal film <NUM> are illustrated in detail in <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. However, each of the wiring patterns <NUM> may include a metal pattern <NUM>, a seed metal film <NUM>, and a barrier metal film <NUM> as illustrated in <FIG>. In each of the wiring patterns <NUM>, the barrier metal film <NUM> may be disposed on the first surface 254a of the metal pattern <NUM>. For simplicity, a singular wiring pattern <NUM>, the barrier metal film <NUM>, and the seed metal film <NUM> will be described below.

The separating layer <NUM> may surround the sidewall 500c of the through via structure <NUM>. The separating layer <NUM> may be disposed adjacent to the through via structure <NUM>. The separating layer <NUM> disposed adjacent to the through via structure <NUM> may be in physical contact with the through via structure <NUM>. The separating layer <NUM> may include a first portion <NUM> and a second portion <NUM>. The first portion <NUM> may be provided between the through via structure <NUM> and the semiconductor substrate <NUM>. The second portion <NUM> may be interposed between the through via structure <NUM> and the etch stop layer <NUM>. The second portion <NUM> may be disposed between the through via structure <NUM> and the etch stop layer <NUM>, be electrically connected to the first portion <NUM>, and may protrude toward a side surface of the etch stop layer <NUM>. The second portion <NUM> of the separating layer <NUM> may include the same material as the first portion <NUM> and may be connected to the first portion <NUM> without any interface. As illustrated in <FIG>, the separating layer <NUM> may have a second portion <NUM> interposed between the first surface <NUM> and the first insulating layer <NUM>. The separating layer <NUM> may not be provided in the first insulating layer <NUM>. For example, the bottom surface of the separating layer <NUM> may be disposed at substantially the same level as the bottom surface of the etch stop layer <NUM>.

The separating layer <NUM> may have an inner wall facing the through via structure <NUM> and an outer wall opposite the inner wall. As illustrated in <FIG>, the inner wall of the separating layer <NUM> may include a first inner wall 410c of the first portion <NUM> and a second inner wall 420c of the second portion <NUM>. The outer wall of the separating layer <NUM> may include a first outer wall 410d of the first portion <NUM> and a second outer wall 420d of the second portion <NUM>. The first inner wall 410c and the second inner wall 420c of the separating layer <NUM> may be in physical contact with the barrier pattern <NUM>. The second inner wall 420c of the separating layer <NUM> may be connected to the first inner wall 410c. The second outer wall 420d of the second portion <NUM> of the separating layer <NUM> may not be aligned with the first outer wall 410d of the first portion <NUM>. The second portion <NUM> of the separating layer <NUM> may protrude toward the etch stop layer <NUM>. For example, the second outer wall 420d may protrude laterally outward with respect to the first outer wall 410d of the first portion <NUM>. The second gap D2 between the second outer wall 420d and the sidewall 500c may be greater than the first gap D1 between the first outer wall 410d and the sidewall 500c of the through via structure <NUM>. The separating layer <NUM> may contact a portion of the etch stop layer <NUM>. For example, a lower portion of the separating layer <NUM> may contact a portion of the etch stop layer <NUM>, and a lower portion of the separating layer <NUM> may correspond to the second portion <NUM>.

The through via structure <NUM> may include a first sidewall and a second sidewall opposite the first sidewall. As illustrated in <FIG>, the separating layer <NUM> may include a first insulating separation pattern <NUM> and a second insulating separation pattern <NUM> facing the first insulating separation pattern <NUM>. The first insulating separation pattern <NUM> (also described as a first insulating isolation pattern) may be disposed on the first sidewall of the through via structure <NUM>. The second insulating separation pattern <NUM> (also described as a second insulating isolation pattern) may be disposed on the second sidewall of the through via structure <NUM>. Each of the first insulating separation pattern <NUM> and the second insulating separation pattern <NUM> may include a first portion <NUM> and a second portion <NUM>.

The separating layer <NUM> may electrically separate the semiconductor substrate <NUM> and the through via structure <NUM>. The leakage current of the through via structure <NUM> may be prevented and/or suppressed by the separating layer <NUM>. The separating layer <NUM> may include an insulating material such as silicon oxide or silicon oxynitride.

The through via structure <NUM> may be spaced apart from the integrated circuits <NUM> by a predetermined distance. For example, the through via structure <NUM> may be horizontally spaced apart from the doped region <NUM>. In the present disclosure, "horizontal" may mean a direction that is parallel to the first surface <NUM> of the semiconductor substrate <NUM>.

As shown in <FIG>, a third insulating layer <NUM> may be further provided on the second surface <NUM> of the semiconductor substrate <NUM> to cover the second surface <NUM> of the semiconductor substrate <NUM>. The through via structure <NUM> may be provided in the third insulating layer <NUM>. The third insulating layer <NUM> may expose the top surface of the through via structure <NUM>. The third insulating layer <NUM> may include a carbon-containing material such as a spin on carbon (SOC) hard mask material. The carbon containing material may be amorphous. As another example, the third insulating layer <NUM> may be omitted.

As shown in <FIG> a conductive pad <NUM> may be provided on the second surface <NUM> of the semiconductor substrate <NUM>, and may cover the top surface of the through via structure <NUM> and the top surface of the third insulating layer <NUM>. The conductive pad <NUM> may be electrically connected to the through via structure <NUM>. The conductive pad <NUM> may be electrically connected to the integrated circuits <NUM> by the through via structure <NUM> and the wiring structure <NUM>. The conductive pad <NUM> may function as a terminal electrically connected to an external device. The external device may be, for example, a semiconductor chip, a passive device, a substrate, or a board. The conductive pad <NUM> may include metals such as copper, aluminum, titanium, and/or alloys thereof.

A terminal pad <NUM> may be disposed on the bottom surface of the wiring layer <NUM>. The terminal pad <NUM> may be electrically connected to the integrated circuits <NUM> or the through via structure <NUM> by the wiring structure <NUM>. The terminal pad <NUM> may include a metal material such as copper, titanium, or aluminum. The connection terminal <NUM> may be further provided on the terminal pad <NUM>. The connection terminal <NUM> may be electrically connected to the terminal pad <NUM>.

A protective layer <NUM> may be further provided on the bottom surface of the wiring layer <NUM>. The protective layer <NUM> may have a terminal opening that exposes the terminal pad <NUM>. The protective layer <NUM> may include an insulating material, for example, an insulating polymer.

<FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are cross-sectional views for describing a method of manufacturing a semiconductor device according to example embodiments. <FIG> is an enlarged view of region B of <FIG>. <FIG> is an enlarged view of region B of <FIG>. Hereinafter, descriptions repeating explanations described above will be omitted. In describing <FIG>, the top surface, the bottom surface, the lowermost portion, and the uppermost portion are described with reference to <FIG>, and the top surface, the bottom surface, the lowermost portion, and the uppermost portion described in <FIG> may be oriented differently than the top surface, the bottom surface, the lowermost portion, and the uppermost portion shown in <FIG> and <FIG>. For example, <FIG> illustrates wiring layer <NUM> as being on top of first surface <NUM> in the vertical direction whereas <FIG> illustrates wiring layer <NUM> as being on the bottom of first surface <NUM> in the vertical direction.

Referring to <FIG> and <FIG>, an etch stop layer <NUM> and a wiring layer <NUM> are formed on the first surface <NUM> (upper surface) of the semiconductor substrate <NUM>. In example embodiments, a semiconductor substrate <NUM> having a crystalline structure is prepared. A doped region <NUM> may be formed by implanting a conductive impurity on the first surface <NUM> of the semiconductor substrate <NUM>. Integrated circuits <NUM> may be formed on the first surface <NUM> of the semiconductor substrate <NUM> or in the semiconductor substrate <NUM>. Forming integrated circuits <NUM> may include forming doped region <NUM>.

An etch stop layer <NUM> is formed on the first surface <NUM> of the semiconductor substrate <NUM> to cover the first surface <NUM> of the semiconductor substrate <NUM>. The etch stop layer <NUM> may be in physical contact with the first surface <NUM> of the semiconductor substrate <NUM>.

The first insulating layer <NUM> is formed on the etch stop layer <NUM> to cover the integrated circuits <NUM>. The first insulating layer <NUM> may include a plurality of insulating layers. The contact plug <NUM> may pass through the first insulating layer <NUM> and may be connected to the integrated circuits <NUM>. The contact plug <NUM> may further pass through the etch stop layer <NUM>. The second insulating layer <NUM> may be formed on the first insulating layer <NUM>.

As illustrated in <FIG>, a trench <NUM> may be formed in the second insulating layer <NUM> to expose the first insulating layer <NUM>. A barrier metal film <NUM> may be formed in the trench <NUM> to conformally cover the bottom and sidewalls of the trench <NUM>. The seed metal film <NUM> may be formed on the barrier metal film <NUM>. By performing an electroplating process using the seed metal film <NUM> (e.g., a seed metal layer) as an electrode, a metal pattern <NUM> may be formed on the seed metal film <NUM> (seed metal layer). Thereafter, a patterning process of the barrier metal film <NUM>, the seed metal film <NUM>, and the metal pattern <NUM> may be further performed. The patterning process may include removing the barrier metal film <NUM>, the seed metal film <NUM>, and the metal pattern <NUM> on the top surface of the second insulating layer <NUM>. Accordingly, the barrier metal film <NUM>, the seed metal film <NUM>, and the metal pattern <NUM> may be disposed in the trench <NUM>. Accordingly, forming the wiring pattern <NUM> can be completed.

The formation of the second insulating layer <NUM> and the formation of the wiring pattern <NUM> may be repeatedly performed. Accordingly, a plurality of stacked second insulating layers <NUM> may be formed as shown in <FIG>, and wiring patterns <NUM> may be formed between the second insulating layers <NUM>. Although not shown in <FIG>, each of the wiring patterns <NUM> may include a barrier metal film <NUM>, a seed metal film <NUM>, and a metal pattern <NUM>. In each of the wiring patterns <NUM>, the barrier metal film <NUM> may be interposed between the semiconductor substrate <NUM> and the metal pattern <NUM>. Metal vias <NUM> may be formed to penetrate at least one of the second insulating layers <NUM>. The wiring patterns <NUM> and the metal vias <NUM> may be formed by, for example, a damascene process, but are not limited thereto. Hereinafter, the single wiring pattern <NUM> will be described.

The terminal pad <NUM> may be formed on the uppermost second insulating layer <NUM> to connect with the wiring structure <NUM>. The protective layer <NUM> may be further formed on the wiring layer <NUM>. The protective layer <NUM> may expose at least a portion of the terminal pad <NUM>.

Referring to <FIG>, the semiconductor substrate <NUM> is turned upside down so that the second surface <NUM> of the semiconductor substrate <NUM> faces upward, i.e., the semiconductor substrate <NUM> may be oriented such that the second surface <NUM> is an upper surface. Afterwards, a portion of the semiconductor substrate <NUM> may be removed to thin the semiconductor substrate <NUM>. The thinning of the semiconductor substrate <NUM> may include performing a planarization process on the second surface <NUM> of the semiconductor substrate <NUM>. The planarization process may be a chemical mechanical polishing process, for example.

Referring to <FIG>, the first mask pattern <NUM> and the second mask pattern <NUM> are formed on the second surface <NUM> of the thinned semiconductor substrate <NUM>. The first mask pattern <NUM> may cover the second surface <NUM> of the semiconductor substrate <NUM>. The first mask pattern <NUM> may be a hard mask layer. The first mask pattern <NUM> may include a carbon-containing material such as a spin on carbon (SOC) hard mask material, for example. The second mask pattern <NUM> may be formed on the first mask pattern <NUM>. The second mask pattern <NUM> may be formed by applying a photoresist material on the first mask pattern <NUM> to form a mask layer and by performing a patterning process on the mask layer to form the second mask pattern <NUM>, for example. The patterning processes may include exposure and development processes. The second mask pattern <NUM> may have a guide opening <NUM>. The first opening <NUM> may be formed in the first mask pattern <NUM> by an etching process using the second mask pattern <NUM>. The first opening <NUM> may be aligned with the guide opening <NUM> and may expose the second surface <NUM> of the semiconductor substrate <NUM>.

Referring to <FIG>, a through hole <NUM> is formed in the semiconductor substrate <NUM> to expose the etch stop layer <NUM>. In the invention a first etching process is performed on the second surface <NUM> of the semiconductor substrate <NUM> exposed by the first opening <NUM> to form the through hole <NUM>. The first etching process may be an anisotropic etching process, for example. The first etching process may include, for example, a dry etching process using a fluorine-containing gas. In the dry etching process, the etch stop layer <NUM> may have an etching selectivity with respect to the semiconductor substrate <NUM>. For example, the etch stop layer <NUM> may have a very low etching rate or may not be etched. Accordingly, after the first etching process is completed, the through hole <NUM> may expose the top surface of the etch stop layer <NUM>.

In the first etching process, an interface defect may be formed on the sidewall of the through hole <NUM>. For example, the interface defect may be formed on the sidewall 100c of the semiconductor substrate <NUM> exposed by the through hole <NUM>.

The through hole <NUM> may be spaced apart from the integrated circuits <NUM> by a predetermined distance. Accordingly, damage to the integrated circuits <NUM> during the first etching process may be prevented.

Referring to <FIG> and <FIG>, the etch stop layer <NUM> is removed to extend the through hole <NUM> into the etch stop layer <NUM>. In the invention a second etching process is performed in the through hole <NUM> and on the etch stop layer <NUM>. The second etching process may include a wet etching process. For example, an ammonium containing material may be used as an etchant during the second etching process. The etch stop layer <NUM> may be removed by the second etching process. Accordingly, the through hole <NUM> may extend into the etch stop layer <NUM>. In the second etching process, the semiconductor substrate <NUM> and the first insulating layer <NUM> may have an etch selectivity with respect to the etch stop layer <NUM>. For example, the semiconductor substrate <NUM> and the first insulating layer <NUM> may have a very low etching rate or may not be etched during the second etching process. The through hole <NUM> may expose the top surface of the first insulating layer <NUM>.

The second etching process may be an isotropic etching process. The etch stop layer <NUM> exposed to the through hole <NUM> may be further removed horizontally to form a recess portion <NUM>. The recess portion <NUM> may be connected to the through hole <NUM>. The recess portion <NUM> may be recessed toward the etch stop layer <NUM> from the sidewall 100c of the semiconductor substrate <NUM>. The recess portion <NUM> may expose the inner side surface 300c of the etch stop layer <NUM>. The recess portion <NUM> may be formed between the first surface <NUM> and the first insulating layer <NUM>.

Referring to <FIG>, a separating layer <NUM> is formed in the through hole <NUM> and the recess portion <NUM>. The separating layer <NUM> may be formed by a deposition process such as an atomic layer deposition process. The separating layer <NUM> may conformally cover the bottom surface and the sidewall of the through hole <NUM>. For example, the separating layer <NUM> may conformally cover the exposed sidewall 100c of the semiconductor substrate <NUM>, the top surface of the first insulating layer <NUM>, and the top surface of the second mask pattern <NUM>. The separating layer <NUM> may be provided in the recess portion <NUM>. The separating layer <NUM> may fill the recess portion <NUM>. For example, the separating layer <NUM> may cover the inner side surface 300c of the etch stop layer <NUM> and the exposed first surface <NUM> of the semiconductor substrate <NUM>.

The separating layer <NUM> may include a first portion <NUM>, a second portion <NUM>, and a third portion <NUM>. The first portion <NUM> may be provided on the sidewall 100c of the semiconductor substrate <NUM>. The second portion <NUM> may be provided in the recess portion <NUM>. The third portion <NUM> may be provided on the top surface of the first insulating layer <NUM> and may not extend into the recess portion <NUM>. The third portion <NUM> may be surrounded by the first portion <NUM> in a plan view.

Referring to <FIG> and <FIG>, the third portion <NUM> and a portion of the first insulating layer <NUM> are removed to extend the through hole <NUM> into the first insulating layer <NUM>. In example embodiments, a third etching process may be performed on the separating layer <NUM> in the through hole <NUM>. The third etching process may be, for example, an anisotropic etching process. The third etching process may be performed by a dry etching process using a fluorine-containing gas, for example. The third portion <NUM> of the separating layer <NUM> and the portion of the first insulating layer <NUM> may be removed by the third etching process. The portion of the first insulating layer <NUM> that is removed may be a portion interposed between the third portion <NUM> and one of the wiring patterns <NUM>. The through hole <NUM> may extend into the first insulating layer <NUM> by the third etching process, and the wiring pattern <NUM> may be exposed. Unless stated otherwise in the following description, a wiring pattern <NUM> may refer to one wiring pattern <NUM> connected to or contacting a through via structure <NUM>, from among a plurality of wiring patterns <NUM>.

During the third etching process, the upper portion of the wiring pattern <NUM> may be partially etched. Accordingly, the upper surface 253a of the wiring pattern <NUM> exposed in the through hole <NUM> may be recessed. The upper surface 253a of the wiring pattern <NUM> exposed to the through hole <NUM> may be disposed at a lower level than the upper surface 253a of the wiring pattern <NUM> covered by the first insulating layer <NUM>. The recessed upper surface 253a of the wiring pattern <NUM> may be rounded or curved. For example, the recessed upper surface 253a of the wiring pattern <NUM> may be convex downward. In another example embodiment, the upper surface 253a of the wiring pattern <NUM> exposed to the through hole <NUM> may be substantially flat.

The separation layer <NUM> on the second mask pattern <NUM> may be further removed by the third etching process to expose the second mask pattern <NUM>. After the third etching process is completed, the first portion <NUM> and the second portion <NUM> of the separating layer <NUM> may remain.

When the etch stop layer <NUM> is omitted and the through hole <NUM> is formed in the semiconductor substrate <NUM> and the first insulating layer <NUM> by a single etching process, it may be difficult to control the etching process. For example, the wiring pattern <NUM> may be damaged during the etching process. Alternatively, in the etching process of the separating layer <NUM>, the separating layer <NUM> may be damaged. In example embodiments, an etch stop layer <NUM> may be formed between the semiconductor substrate <NUM> and the wiring pattern <NUM>, and the etch stop layer <NUM> may be formed between the semiconductor substrate <NUM> and the first insulating layer <NUM>. It may have different etching selectivity with respect to the semiconductor substrate <NUM> and the first insulating layer <NUM>. Accordingly, the through hole <NUM> may be formed through the first etching process, the second etching process, and the third etching process to expose the wiring pattern <NUM>. Since the formation of the through hole <NUM> is performed through a plurality of etching processes, the etching of the through hole <NUM> may be more precisely controlled. Accordingly, unintended etching of the wiring pattern <NUM> or the separating layer may be reduced, suppressed, or prevented.

Referring to <FIG>, the barrier layer <NUM>, the seed layer <NUM>, and the through via layer <NUM> are formed in the through hole <NUM> and on the second surface <NUM> of the semiconductor substrate <NUM>. In example embodiments, the barrier layer <NUM> may be formed by a deposition process to conformally cover the inner sidewall and the bottom surface of the through hole <NUM>. For example, the barrier layer <NUM> may be formed on an upper surface 253a of the wiring pattern <NUM>, an inner sidewall of the first insulating layer <NUM>, a first inner wall of the first portion <NUM>, and a second inner wall of the second portion. The barrier layer <NUM> may be horizontally spaced apart from the etch stop layer <NUM> by the second portion <NUM> of the separating layer <NUM>. The barrier layer <NUM> may be horizontally spaced apart from the semiconductor substrate <NUM> by the first portion <NUM> of the separating layer <NUM>. The barrier layer <NUM> may further extend on the second surface <NUM> of the semiconductor substrate <NUM> to cover the second mask pattern <NUM>. The seed layer <NUM> may be formed on the barrier layer <NUM>. The seed layer <NUM> may conformally cover the barrier layer <NUM> in the through hole <NUM> and on the second surface <NUM> of the semiconductor substrate <NUM>.

A through via layer <NUM> may be formed on the seed layer <NUM> to fill the through hole <NUM>. Formation of the through via layer <NUM> may include performing an electroplating process using the seed layer <NUM> as an electrode. The through via layer <NUM> may extend on the second surface <NUM> of the semiconductor substrate <NUM> to cover the seed layer <NUM>.

Referring back to <FIG> and <FIG>, a planarization process may be performed on the through via layer <NUM> to form a through via structure <NUM>. The through via structure <NUM> may include a barrier pattern <NUM>, a seed pattern <NUM>, and a conductive via <NUM>. According to embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. The barrier layer <NUM>, the seed layer <NUM>, and the through via layer <NUM> may be planarized to form the barrier pattern <NUM>, the seed pattern <NUM>, and the conductive via <NUM>, respectively. The barrier layer <NUM>, the seed layer <NUM>, the through via layer <NUM>, and the separation layer <NUM> on the second surface <NUM> of the semiconductor substrate <NUM> may be removed by the planarization process. The through via structure <NUM> may be disposed in the through hole <NUM>.

The second mask pattern <NUM>, the top portion of the separating layer <NUM>, and the top portion of the first mask pattern <NUM> may be removed by the planarization process. As a result of the planarization process, a lower portion of the remaining first mask pattern <NUM> may form a third insulating layer <NUM>. The top surface of the through via structure <NUM> may be disposed at substantially the same level as the top surface of the third insulating layer <NUM>. In another example embodiment, the planarization process may be performed until the semiconductor substrate <NUM> is exposed.

As described above, when the etch stop layer <NUM> is omitted and the through hole <NUM> is formed in a single etching process, contact resistance can be increased due to damage of the wiring pattern <NUM>. Alternatively, it may be difficult to fill the inside of the through hole <NUM> well enough to adequately form the through via structure <NUM>. When the separating layer <NUM> is excessively etched, at least a portion of the through via structure <NUM> may contact the semiconductor substrate <NUM>. Accordingly, electrical separation between the through via structure <NUM> and the semiconductor substrate <NUM> may be insufficient.

According to some example embodiments, the through hole <NUM> may be formed by the first to third etching processes to prevent unwanted etching of the wiring pattern <NUM> and the separating layer <NUM>. Accordingly, the through via structure <NUM> may satisfactorily fill the inside of the through hole <NUM>, and the contact resistance between the through via structure <NUM> and the wiring pattern <NUM> may be improved. The through via structure <NUM> may be spaced apart from the semiconductor substrate <NUM> by the separating layer <NUM> and may be electrically separated from the semiconductor substrate <NUM>. The reliability of the semiconductor device can be improved.

The through via structure <NUM> may be formed by a via last process. For example, after the process of forming the integrated circuits <NUM> and the wiring layer <NUM> and the process of thinning the semiconductor substrate <NUM>, the through via structure <NUM> may be formed.

The conductive pad <NUM> may be formed on the top surface of the through via structure <NUM> and on the third insulating layer <NUM> to be electrically connected to the through via structure <NUM>. Although not shown, an upper passivation layer may be further formed on the third insulating layer <NUM>. The connection terminal <NUM> may be formed on the bottom surface of the terminal pad <NUM>. As described so far, the manufacturing of the semiconductor device can be completed.

<FIG>, <FIG>, and <FIG> are cross-sectional views for describing a method of manufacturing a semiconductor device, in accordance with some embodiments of the inventive concepts, and correspond to the enlarged views of region A of <FIG>. <FIG> is an enlarged view of region B of <FIG>. <FIG> is an enlarged view of region B of <FIG>. Hereinafter, descriptions repeating explanations described above will be omitted.

Referring to <FIG>, an etch stop layer <NUM> and a wiring layer <NUM> may be formed on the first surface <NUM> of a semiconductor substrate <NUM>. First and second mask patterns <NUM> and <NUM> may be formed on the second surface <NUM> of the semiconductor substrate <NUM>. The through hole <NUM> may be formed in the semiconductor substrate <NUM> by the first etching process. The through hole <NUM> may extend into the etch stop layer <NUM> by the second etching process, and a recess portion <NUM> may be formed. The separating layer <NUM> may be formed on the bottom and inner walls of the through hole <NUM> and in the recess portion <NUM>. The separating layer <NUM> may extend on the sidewalls and the top surface of the second mask pattern <NUM>.

Referring to <FIG>, a capping pattern <NUM> may be formed on the top surface and sidewalls of the second mask pattern <NUM> to cover the separating layer <NUM>. The capping pattern <NUM> may block a part of the guide opening <NUM>. The capping pattern <NUM> may have a second opening <NUM>, and the second opening <NUM> may be connected to the through hole <NUM>. The width W20 of the second opening <NUM> may be narrower than the width W10 of the through hole <NUM> on the second surface <NUM> of the semiconductor substrate <NUM>. The second opening <NUM> may overlap the center area of the through hole <NUM> in a plan view.

The capping pattern <NUM> may include a material having an etch selectivity with respect to the separating layer <NUM>. The capping pattern <NUM> may include a nitrogen-containing material. The capping pattern <NUM> may include, for example, silicon nitride, silicon carbide nitride, and/or silicon oxynitride.

Referring to <FIG> and <FIG>, a third etching process may be performed on the separating layer <NUM> exposed by the second opening <NUM>. The third etching process may be, for example, an isotropic dry etching process. The third portion <NUM> of the separating layer <NUM> and the portion of the first insulating layer <NUM> may be removed by the third etching process, and the top surface of the wiring pattern <NUM> may be exposed. In this case, the third portion <NUM> and the portion of the first insulating layer <NUM> may be vertically overlapped with the second opening <NUM>. The second opening <NUM> may not vertically overlap with the separating layer <NUM> on the sidewall 100c of the semiconductor substrate <NUM>. The capping pattern <NUM> may prevent the first portion <NUM> of the separating layer <NUM> from being etched during the third etching process. As used herein, unless clearly indicated otherwise, "vertical" may mean a direction substantially parallel to a direction perpendicular to the first surface <NUM> of the semiconductor substrate <NUM>. The through hole <NUM> may extend into the first insulating layer <NUM> by the third etching process.

Since the second opening <NUM> has a narrower width W20 than the through hole <NUM>, the width of the through hole <NUM> in the first insulating layer <NUM> can be smaller than the width of the through hole <NUM> in the semiconductor substrate <NUM>. For example, as illustrated in <FIG>, the maximum width W12 of the through hole <NUM> in the first insulating layer <NUM> may be smaller than the minimum width W11 of the through hole <NUM> in the semiconductor substrate <NUM>.

An upper surface of the wiring pattern <NUM> exposed by the third etching process may be further recessed as described in the example of the conductive pad <NUM> with reference to <FIG>. In another example embodiment, the top surface of the wiring pattern <NUM> exposed by the through hole <NUM> may be substantially flat.

Referring to <FIG> and <FIG>, the capping pattern <NUM> (see <FIG>) may be removed, and the through via structure <NUM> may be formed in the through hole <NUM>. The formation of the through via structure <NUM> may be similar as described with reference to <FIG>, <FIG>, and <FIG>. As described with reference to <FIG>, the through via structure <NUM> may be formed by forming the barrier layer <NUM>, the seed layer <NUM> and the through via layer <NUM>, and by planarizing the barrier layer <NUM>, the seed layer <NUM> and the through via layer <NUM> to form the barrier pattern <NUM>, the seed pattern <NUM>, and the conductive via <NUM>, respectively. During the planarization process, the second mask pattern <NUM>, the upper portion of the first mask pattern <NUM>, and the upper portion of the separating layer <NUM> may be removed together. After the planarization process, a lower portion of the remaining first mask pattern <NUM> may form a third insulating layer <NUM>.

According to an embodiment, the through via structure <NUM> may have a shape corresponding to the through hole <NUM>. As shown in <FIG>, the maximum width W22 of the through via structure <NUM> in the first insulating layer <NUM> may be smaller than the minimum width W21 of the through via structure <NUM> in the semiconductor substrate <NUM>. The bottom surface 500b of the through via structure <NUM> may be convex downward. An upper surface of the wiring pattern <NUM> may include a first upper surface in contact with the through via structure <NUM> and a second upper surface in contact with the first insulating layer <NUM>. The first upper surface of wiring pattern <NUM> may be disposed at a lower level than the second upper surface of wiring pattern <NUM>. By the examples described so far, a semiconductor device can be manufactured.

<FIG> is a cross-sectional view illustrating a semiconductor device in accordance with example embodiments, and corresponds to an enlarged view of region A of <FIG>. <FIG> shows an enlarged view of the region B of <FIG>. Hereinafter, descriptions repeating explanations described above will be omitted.

Referring to <FIG> and <FIG>, the semiconductor device may include a semiconductor substrate <NUM>, a wiring layer <NUM>, an etch stop layer <NUM>, a separating layer <NUM>, and a through via structure <NUM>. The semiconductor substrate <NUM>, the wiring layer <NUM>, and the through via structure <NUM> may be the same as or similar to those described with reference to <FIG>. The wiring layer <NUM> may include a first insulating layer <NUM>, second insulating layers <NUM>, and a wiring structure <NUM>. The wiring structure <NUM> may include a contact plug <NUM>, a metal via <NUM>, and a wiring pattern <NUM>. The wiring pattern <NUM> may include a barrier metal film <NUM>, a seed metal film <NUM>, and a metal pattern <NUM> as shown in <FIG>.

Additionally, the etch stop layer <NUM> may be provided between the first insulating layer <NUM> and the uppermost second insulating layer <NUM> and between the first insulating layer <NUM> and the wiring pattern <NUM>. The etch stop layer <NUM> may be in physical contact with the top surface of the wiring pattern <NUM>. For example, the etch stop layer <NUM> may be in physical contact with the barrier metal film <NUM> (barrier metal layer) as shown in <FIG>.

The through via structure <NUM> may be provided in the semiconductor substrate <NUM>, the first insulating layer <NUM>, and the etch stop layer <NUM>. The through via structure <NUM> may be horizontally spaced apart from the integrated circuits <NUM>. The through via structure <NUM> may include a barrier pattern <NUM>, a seed pattern <NUM>, and a conductive via <NUM>. As shown in <FIG>, the bottom surface 500b of the through via structure <NUM> may be substantially flat. The bottom surface 500b of the through via structure <NUM> may contact the barrier metal film <NUM> (barrier metal layer). The through via structure <NUM> may not contact the seed metal film <NUM> (seed metal layer).

The separating layer <NUM> may surround sidewalls of the through via structure <NUM>. The separating layer <NUM> may be interposed between the semiconductor substrate <NUM> and the through via structure <NUM> and between the first insulating layer <NUM> and the through via structure <NUM>. The separation layer <NUM> may not extend into the etch stop layer <NUM>. As shown in <FIG>, the lowermost surface 400b of the separating layer <NUM> may be disposed at a level substantially the same as or higher than that of the upper surface of the etch stop layer <NUM>. The separation layer <NUM> may expose the inner side surface 300c of the etch stop layer <NUM>. The inner wall 400c of the separation layer <NUM> and the inner side surface 300c of the etch stop layer <NUM> may be in physical contact with the through via structure <NUM>. The separating layer <NUM> may contact a portion of the etch stop layer <NUM>. For example, a lower portion of the separating layer <NUM> may contact a portion of the etch stop layer <NUM>, and a lower portion of the separating layer <NUM> may be a portion including a lowermost surface 400b.

<FIG> are cross-sectional views for describing a method of manufacturing a semiconductor device, in accordance with example embodiments. Hereinafter, descriptions repeating explanations described above will be omitted.

Referring to <FIG>, a wiring layer <NUM> and an etch stop layer <NUM> may be formed on the first surface <NUM> of the semiconductor substrate <NUM>. Formation of the wiring layer <NUM> may be performed by similar methods as described above with reference to <FIG>. However, the etch stop layer <NUM> may be formed between the first insulating layer <NUM> and wiring pattern <NUM> and between the first insulating layer <NUM> and the second insulating layer <NUM>. A thinning process may be performed on the second surface <NUM> of the semiconductor substrate <NUM> to remove a portion of the semiconductor substrate <NUM>. The first mask pattern <NUM> and the second mask pattern <NUM> may be formed on the second surface <NUM> of the thinned semiconductor substrate <NUM>.

Referring to <FIG>, a first etching process may be performed as to the semiconductor substrate <NUM> so that a through hole <NUM> may be formed in the semiconductor substrate <NUM> and the first insulating layer <NUM>. In the first etching process, the mask patterns <NUM> and <NUM> may be used as an etching mask. In the first etching process, the etch stop layer <NUM> may have an etching selectivity with respect to the semiconductor substrate <NUM> and the first insulating layer <NUM>. After the first etching process is completed, the through hole <NUM> may expose the top surface of the etch stop layer <NUM>.

Referring to <FIG>, a separating layer <NUM> may be formed in the through hole <NUM> to cover the bottom surface and the sidewall of the through hole <NUM>. For example, the separating layer <NUM> may conformally cover the exposed sidewall 100c of the semiconductor substrate <NUM>, the sidewall of the first insulating layer <NUM>, and the top surface of the etch stop layer <NUM>. The separating layer <NUM> may extend on an upper surface of the second mask pattern <NUM>.

Referring to <FIG>, a third etching process may be performed to remove a portion of the separating layer <NUM>. A portion of the separating layer <NUM> may include a portion of the separating layer <NUM> on the top surface of the etch stop layer <NUM> and a portion of the separating layer <NUM> on the second mask pattern <NUM>. In example embodiments, the third etching process may include an anisotropic dry etching process and may be performed under similar conditions as the example of the third etching process of <FIG>, explained above. In the third etching process, the etch stop layer <NUM> may have an etching selectivity with respect to the separating layer <NUM>. After the third etching process, the through hole <NUM> may expose the top surface of the etch stop layer <NUM>. The separating layer <NUM> may remain on the sidewall 100c of the semiconductor substrate <NUM> and the sidewall of the first insulating layer <NUM>.

Referring to <FIG>, a second etching process may be performed to remove the exposed etch stop layer <NUM>. The second etching process may include a wet etching process. Accordingly, the through hole <NUM> may extend into the etch stop layer <NUM>. The inner side surface 300c of the etch stop layer <NUM> may be exposed to the through hole <NUM>.

In the second etching process, the wiring pattern <NUM> may not be etched. After the second etching process, the through hole <NUM> may expose the upper surface 253a of the wiring pattern <NUM>. The upper surface 253a of the exposed wiring pattern <NUM> may be substantially flat or planar.

Referring back to <FIG> and <FIG>, a through via structure <NUM> may be formed in the through hole <NUM>. Formation of the through via structure <NUM> may be performed in substantially the same manner as described with reference to <FIG>, <FIG>, and <FIG>. As described with reference to <FIG>, the through via structure <NUM> may be formed by forming the barrier layer <NUM> (barrier film), the seed layer <NUM> (seed film) and the through via layer <NUM> (through via film), and then, by planarizing the barrier layer <NUM> (barrier film), the seed layer <NUM> (seed film) and the through via layer <NUM> to form the barrier pattern <NUM>, the seed pattern <NUM> and the conductive via <NUM>, respectively. The second mask pattern <NUM>, the upper portion of the first mask pattern <NUM>, and the upper portion of the separating layer <NUM> may be removed in the planarization process. After the planarization process, a third insulating layer <NUM> may be formed under the remaining first mask pattern <NUM>. Thereafter, the conductive pad <NUM> and the connection terminal <NUM> may be formed. By the example embodiments described so far, a semiconductor device can be manufactured.

<FIG> is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments. Hereinafter, descriptions repeating explanations described above will be omitted.

Referring to <FIG>, the semiconductor package <NUM> includes a package substrate <NUM>, may include first to fourth semiconductor devices <NUM>, <NUM>, <NUM>, and <NUM>, and includes a molding film <NUM>. The package substrate <NUM> may include a printed circuit board or a redistribution layer. The external terminal <NUM> may be disposed on the bottom surface of the package substrate <NUM>. The metal pad <NUM> may be disposed on the top surface of the package substrate <NUM>. The metal pad <NUM> may be electrically connected to the external terminal <NUM> through the internal wiring <NUM>.

Each of the first to the third semiconductor devices <NUM>, <NUM>, and <NUM> may be the same as or similar to the semiconductor device of <FIG>. At least one of the first to the third semiconductor devices <NUM>, <NUM>, and <NUM> may be the same as or similar to the semiconductor device described with reference to <FIG>, the semiconductor device of <FIG> and <FIG>, or the semiconductor device of <FIG> and <FIG>. The first semiconductor device <NUM> may include a first semiconductor substrate <NUM>, a first wiring layer <NUM>, a first etch stop layer <NUM>, a first separating layer <NUM>, and a first through via structure <NUM>. The second semiconductor device <NUM> may include a second semiconductor substrate <NUM>, a second wiring layer <NUM>, a second etch stop layer <NUM>, a second separating layer <NUM>, and a second through via structure <NUM>. The third semiconductor device <NUM> may include a third semiconductor substrate <NUM>, a third wiring layer <NUM>, a third etch stop layer <NUM>, a third separating layer <NUM>, and a third through via structure <NUM>.

The first semiconductor substrate <NUM>, the second semiconductor substrate <NUM>, the third semiconductor substrate <NUM>, and the fourth semiconductor substrate <NUM> may be substantially the same as or similar to the semiconductor substrate <NUM> described in the example of <FIG>, the examples of <FIG>, the examples of <FIG> and <FIG>, or the examples of <FIG> and <FIG>. The first wiring layer <NUM>, the second wiring layer <NUM>, the third wiring layer <NUM>, and the fourth wiring layer <NUM> may be substantially the same as or similar to the wiring layer <NUM> described in the example of <FIG>, the examples of <FIG>, the examples of <FIG> and <FIG>, or the examples of <FIG> and <FIG>. The first etch stop layer <NUM>, the second etch stop layer <NUM>, and the third etch stop layer <NUM> may be substantially the same as or similar to the etching stop layer <NUM> described with reference to the example of <FIG>, the examples of <FIG>, the examples of <FIG> and <FIG>, or the examples of <FIG> and <FIG>. The first separating layer <NUM>, the second separating layer <NUM>, and the third separating layer <NUM> may be substantially the same as or similar to the separating layer <NUM> described above. The first through via structure <NUM>, the second through via structure <NUM>, and the third through via structure <NUM> may be substantially the same as or similar to the through via structure <NUM> described in the example of <FIG>, the examples of <FIG>, the examples of <FIG> and <FIG>, or the examples of <FIG> and <FIG>.

The first semiconductor device <NUM> may be mounted on the package substrate <NUM>. For example, the first connection terminal <NUM> may be connected to the metal pad <NUM>, and the first semiconductor device <NUM> may be electrically connected to the external terminal <NUM> through the first connection terminal <NUM>. The first connection terminal <NUM> may be substantially the same as or similar to the connection terminal <NUM> described with reference to <FIG> and <FIG>.

The second semiconductor device <NUM> may be mounted on the first semiconductor device <NUM>. The second connection terminal <NUM> may be provided between the first semiconductor device <NUM> and the second semiconductor device <NUM>. The second semiconductor device <NUM> may be electrically connected to the first semiconductor device <NUM> and the package substrate <NUM> through the second connection terminal <NUM>. The second connection terminal <NUM> may be substantially the same as or similar to the connection terminal <NUM> described with reference to <FIG> and <FIG>.

The third semiconductor device <NUM> may be mounted on the second semiconductor device <NUM>. The third connection terminal <NUM> may be interposed between the second semiconductor device <NUM> and the third semiconductor device <NUM>. The third semiconductor device <NUM> may be electrically connected to the first semiconductor device <NUM>, the second semiconductor device <NUM>, or the package substrate <NUM> through the third connection terminal <NUM>. The third connection terminal <NUM> may be substantially the same as or similar to the connection terminal <NUM> described with reference to <FIG> and <FIG>.

The fourth semiconductor device <NUM> is a top semiconductor device. The fourth semiconductor device <NUM> may include a fourth semiconductor substrate <NUM> and a fourth wiring layer <NUM>, and may not include a through via structure. The fourth connection terminal <NUM> may be interposed between the fourth semiconductor device <NUM> and the third semiconductor device <NUM>. The fourth semiconductor device <NUM> may be electrically connected to the first semiconductor device <NUM>, the second semiconductor device <NUM>, and the third semiconductor device <NUM> through a fourth connection terminal <NUM>, or may be electrically connected to the package substrate <NUM>. The fourth connection terminal <NUM> may be substantially the same as or similar to the connection terminal <NUM> described with reference to <FIG> and <FIG>.

The number of semiconductor devices <NUM>, <NUM>, <NUM> and <NUM> is not limited, but may be greater than four or less than four.

The molding film <NUM> (molding layer) may be provided on the package substrate <NUM> to cover the first to fourth semiconductor devices <NUM>, <NUM>, <NUM>, and <NUM>. The molding film <NUM> may include an insulating polymer such as an epoxy-based molding compound.

Claim 1:
A method of manufacturing a semiconductor device, the semiconductor device comprising:
a crystalline semiconductor substrate (<NUM>);
an etch stop layer (<NUM>) disposed on a first surface (<NUM>) of the crystalline semiconductor substrate (<NUM>);
a conductive through via structure (<NUM>) penetrating the crystalline semiconductor substrate (<NUM>) and the etch stop layer (<NUM>); and
an insulating separation layer (<NUM>) disposed between the conductive through via structure (<NUM>) and the crystalline semiconductor substrate (<NUM>),
wherein a lower portion of the insulating separation layer (<NUM>) contacts a portion of the etch stop layer (<NUM>).
wherein the method comprises:
performing a first etching process to form a through hole (<NUM>) in the semiconductor substrate (<NUM>) and to expose the etch stop layer (<NUM>); and
performing a second etching process to extend the through hole (<NUM>) into the etch stop layer (<NUM>).