Patent Description:
A VCSEL (Vertical Cavity Surface Emitting Laser) device has a structure in which a light-emitting layer is sandwiched between a pair of reflection mirrors. A current confinement structure is provided in the vicinity of the light-emitting layer, and a current concentrates in a partial region in the light-emitting layer by the current confinement structure to generate spontaneous emission light. The pair of reflection mirrors reflects light of a predetermined wavelength, of the spontaneous emission light, toward the light-emitting layer, thereby causing laser oscillation.

In recent years, infrared emission VCSEL of a <NUM> band has been used as a light source of a three-dimensional sensing system such as face authentication. Although it is effective to increase the light output of the light source in order to increase the authentication accuracy, it is desired to set the light output to a predetermined value or less in order to prevent eyes from being damaged due to the laser beam.

This value is called a damage threshold value and increases as the wavelength of the laser beam is higher. Since the damage threshold value significantly increases from the wavelength of <NUM> or more, the wavelength band of <NUM> or more is called an eye-safe band. Further, the wavelength band of <NUM> is suitable for outdoor use because noise due to sunlight is small. For this reason, a laser light source of the wavelength band of <NUM> is desired as a light source for next-generation sensing. Further, as a structure of a laser beam used for sensing, a VCSEL that is cheaper than an existing edge emitting laser and can be easily arrayed is favorable.

There is an InP substrate as a substrate suitable for a laser beam that oscillates at the wavelength of <NUM>. However, it is not easy to form a current confinement structure on the InP substrate. This is because an excellent oxidized confinement layer such as an AlAs oxidized layer that can be used in a GaAs substrate cannot be used in the InP substrate due to lattice-matching problems. For this reason, a buried tunnel junction is generally used for the current confinement structure.

Further, there is also a method of using an AlInAs layer that can be lattice-matched with an InP substrate in order to form a current confinement structure. However, the oxidation rate of AlInAs is proportional to the Al composition and decreases as the Al composition is lower. Since the Al composition of AlInAs that can be lattice-matched with the InP substrate is low, it is necessary to oxidize at a high temperature in order to achieve a realistic oxidation rate, which inevitably leads to crystal deterioration. To address this problem, Patent Literature <NUM> disclose a current confinement structure that includes an AlInAs oxidized layer including a superlattice of InAs and AlAs.

Patent Literature <NUM>: <CIT> Cited references include <CIT>. It discloses that a surface emitting semiconductor laser diode of a tunnel junction type includes a semiconductor substrate, a first reflector, a second reflector, an active region disposed in series between the first and second reflectors, and a tunnel junction region disposed in series between the first and second reflectors. The tunnel junction region includes a first semiconductor layer of a first conductive type and a second semiconductor layer of a second conductive type that forms a junction with the first semiconductor layer, the first semiconductor layer being composed of a superlattice layer that at least partially includes aluminum and is partially oxidized.

However, the current confinement structure using a buried tunnel junction as described above requires crystal re-growth to form a buried tunnel junction, which causes a problem of production cost. Further, in the current confinement structure using an AlInAs oxidized layer as described in Patent Literature <NUM>, it is necessary to form a superlattice of InAs and AlAs using a molecular beam epitaxy method or the like, which causes a problem of producibility.

In view of the circumstances as described above, it is an object of the present technology to provide a vertical cavity surface emitting laser device that is excellent in producibility and capable of reducing the production cost and a method of producing the vertical cavity surface emitting laser device. Solution to Problem.

A VCSEL (Vertical Cavity Surface Emitting Laser) device according to a first embodiment of the present technology will be described.

<FIG> is a cross-sectional view of a VCSEL device <NUM> according to this embodiment. As shown in the figure, the VCSEL device <NUM> includes a substrate <NUM>, a buffer layer <NUM>, a first reflection mirror <NUM>, a first intermediate layer <NUM>, a light-emitting layer <NUM>, a second intermediate layer <NUM>, a tunnel junction layer <NUM>, a third intermediate layer <NUM>, a second reflection mirror <NUM>, a first electrode <NUM>, a second electrode <NUM>, and an insulation layer <NUM>. Note that in each of the figures, the layer surface direction of the respective layers constituting the VCSEL device <NUM> is an X-Y direction and a direction perpendicular to the layer surface direction is a Z direction.

The substrate <NUM> supports each layer of the VCSEL device <NUM>. The substrate <NUM> is formed of a semiconductor material and can be formed of, for example, n-InP. The buffer layer <NUM> is formed on the substrate <NUM> and buffers the lattice constants of the substrate <NUM> and the first reflection mirror <NUM>. The buffer layer <NUM> is formed of an n-type semiconductor material and can be formed of, for example, n-InP.

The first reflection mirror <NUM> is provided on the buffer layer <NUM>, reflects light of a wavelength λ, and causes light of a wavelength other than that to be transmitted therethrough. The first reflection mirror <NUM> is a DBR (Distributed Bragg Reflector) in which a low-refractive index layer and a high-refractive index layer having an optical film thickness of λ/<NUM> are alternately stacked to obtain a plurality of layers, and can be a semiconductor DBR formed of an n-type semiconductor material. The low-refractive index layer is formed of, for example, n-InP, the high-refractive index layer is formed of, for example, n-AlGaInAs, and the number of times of stacking can be, for example, <NUM> pairs. A dopant can be, for example, Si.

The first intermediate layer <NUM> is a layer that is provided on the first reflection mirror <NUM> and transports carriers to the light-emitting layer <NUM>. The first intermediate layer <NUM> is formed of an n-type semiconductor material and can be formed of, for example, n-InP.

The light-emitting layer <NUM> is provided on the first intermediate layer <NUM> and emits and amplifies spontaneous emission light by carrier recombination. The light-emitting layer <NUM> can be a layer having a multi-quantum well (MQW) structure in which a quantum well layer having a small bandgap and a barrier layer having a bandgap are alternately stacked. The quantum well layer and the barrier layer are formed of, for example, AlGaInAs with different compositions, the emission wavelength can be <NUM>, and the number of wells can be four.

The second intermediate layer <NUM> is formed of a p-type semiconductor material and can be formed of, for example, p-InP.

The tunnel junction layer <NUM> is formed on the second intermediate layer <NUM> to form a tunnel junction. <FIG> is a cross-sectional view of the tunnel junction layer <NUM>. <FIG> is a plan view of the tunnel junction layer <NUM> and is a diagram of the tunnel junction layer <NUM> when viewed from the Z direction.

As shown in <FIG>, the tunnel junction layer <NUM> includes a first highly doped layer <NUM> and a second highly doped layer <NUM>. The first highly doped layer <NUM> is a layer on the side of the second intermediate layer <NUM>, the second highly doped layer <NUM> is a layer on the side of the third intermediate layer <NUM>. Further, as shown in <FIG>, the tunnel junction layer <NUM> has an inner peripheral region 107a and an outer peripheral region 107b. The inner peripheral region 107a is a region located on the inner peripheral side of the tunnel junction layer <NUM>, and the outer peripheral region 107b is an annular region surrounding the inner peripheral region 107a.

The inner peripheral region 107a of the first highly doped layer <NUM> is formed of a highly doped p-type semiconductor material containing Al, and can be formed of, for example, p+-AlInAs. The inner peripheral region 107a of the second highly doped layer <NUM> is formed of a highly doped n-type semiconductor material containing Al, and can be formed of, for example, n+-AlInAs.

Note that the material of the first highly doped layer <NUM> and the second highly doped layer <NUM> is a material lattice-matched with the material of the substrate <NUM>. For example, in the case where the substrate <NUM> is formed of InP, the first highly doped layer <NUM> and the second highly doped layer <NUM> can be formed of Al<NUM>In<NUM>As highly doped with a p-type or n-type dopant.

The outer peripheral region 107b of each of the first highly doped layer <NUM> and the second highly doped layer <NUM> is formed of a material obtained by oxidizing the material of the inner peripheral region 07b and has insulating properties. That is, the outer peripheral region 107b of each of the first highly doped layer <NUM> and the second highly doped layer <NUM> contains an Al oxide, and can be formed of, for example, an AlInAs oxide. The thicknesses of the first highly doped layer <NUM> and the second highly doped layer <NUM> can each be <NUM>. Further, the distance between the tunnel junction layer <NUM> and the light-emitting layer <NUM> is suitably λ/<NUM>.

The third intermediate layer <NUM> is provided on the tunnel junction layer <NUM> and transports carriers from the second electrode <NUM> to the tunnel junction layer <NUM>. The third intermediate layer <NUM> also serves as a contact layer for the second electrode <NUM>. Further, as a contact layer, a highly doped layer may be separately provided between the third intermediate layer <NUM> and the second electrode <NUM>. The third intermediate layer <NUM> is formed of an n-type semiconductor material and can be formed of, for example, n-InP. The third intermediate layer <NUM> and the tunnel junction layer <NUM> form a mesa structure described below.

The second reflection mirror <NUM> is provided on the third intermediate layer <NUM>, reflects light of the wavelength λ, and causes light of a wavelength other than that to be transmitted therethrough. The second reflection mirror <NUM> is a DBR in which a low-refractive index layer and a high-refractive index layer having an optical film thickness of λ/<NUM> are alternately stacked to obtain a plurality of layers, and can be a dielectric DBR formed of a dielectric. The low-refractive index layer is formed of, for example, SiO<NUM>, the high-refractive index layer is formed of, for example, Ta<NUM>O<NUM>, and the number of times of stacking can be eight pairs.

The first electrode <NUM> is provided on the back surface of the substrate <NUM> and functions as one electrode of the VCSEL device <NUM>. The first electrode <NUM> can be formed of, for example, Ti/Pt/Au. The second electrode <NUM> is provided on the third intermediate layer <NUM> and functions as the other electrode of the VCSEL device <NUM>. The second electrode <NUM> can have an annular shape surrounding the second reflection mirror <NUM> and can have, for example, an inner diameter of <NUM> and an outer diameter of <NUM>. The second electrode <NUM> can be formed of, for example, Ti/Pt/Au.

The insulation layer <NUM> is provided on the second intermediate layer <NUM> and the side surface of the mesa structure and insulates the second intermediate layer <NUM> and the side surface of the mesa structure. The insulation layer <NUM> can be formed of an insulating material such as SiN.

The VCSEL device <NUM> has the structure described above. As described above, the buffer layer <NUM>, the first intermediate layer <NUM>, the third intermediate layer <NUM>, and the second highly doped layer <NUM> are each formed of an n-type semiconductor material as a first conductivity type, and the dopant can be Si. The second intermediate layer <NUM> and the first highly doped layer <NUM> are each formed of a p-type semiconductor material as a second conductivity type, and the dopant of the second intermediate layer <NUM> can be Mg. Further, the dopant of the first highly doped layer <NUM> is suitably C that is difficult to diffuse.

The doping concentration is, for example, <NUM>×<NUM><NUM>[cm-<NUM>] for the first highly doped layer <NUM> and the second highly doped layer <NUM> and approximately <NUM>×<NUM><NUM>~<NUM>×<NUM><NUM>[cm-<NUM>] for the other layers. Note that the first conductivity type and the second conductivity type in the VCSEL device <NUM> may be reversed, i.e., the first conductivity type may be the p-type and the second conductivity type may be the n-type.

The VCSEL device <NUM> has a mesa structure. <FIG> is a cross-sectional view showing a partial configuration of the VCSEL device <NUM>, including a mesa structure. <FIG> is a plan view of the mesa structure and is a diagram of the mesa structure when viewed from the Z direction.

As shown in these figures, the tunnel junction layer <NUM> and the third intermediate layer <NUM> are formed in a mesa (plateau) shape to form a mesa structure M. As shown in <FIG>, the mesa structure M can have a circular shape when viewed from the Z direction. The mesa structure M is formed such that the inner peripheral region 107a of the tunnel junction layer <NUM> is located at the center of the mesa structure M and includes a current injection region described below.

As shown in <FIG>, the side surface of the mesa structure M is referred to as a side surface S. The side surface S is the outer peripheral surface of the mesa structure M along the Z direction and can be a cylindrical surface. Further, the end surface of the tunnel junction layer <NUM> is referred to as an end surface P. The end surface P is the outer peripheral surface of the outer peripheral region 107b along the Z direction and can be a cylindrical surface. As shown in <FIG>, the outer peripheral region 107b is formed to a certain depth in the X-Y direction from the end surface P, and the inner peripheral region 107a is separated from the end surface P by the outer peripheral region 107b.

As shown in <FIG>, an outer diameter D1 of the tunnel junction layer <NUM> is formed to be smaller than an outer diameter D2 of the mesa structure M. As a result, as shown in <FIG>, the end surface P is located on the side of the inner peripheral region 107a than the side surface S and is spaced apart from the side surface S. An annular space E is formed between the end surface P and the side surface S. This space E can be a gap. Further, the space E may be filled with an insulator. Note that the outer diameter D1 can be, for example, <NUM>, and the outer diameter D2 can be, for example, <NUM>. Further, an outer diameter D3 of the inner peripheral region 107a can be, for example, <NUM>.

The mesa structure M is formed as described above. Note that the mesa structure M is not limited to the one including only the tunnel junction layer <NUM> and the third intermediate layer <NUM> and may be, for example, one including the second intermediate layer <NUM> in addition thereto. In this case, the end surfaces of the third intermediate layer <NUM> and the second intermediate layer <NUM> are on the same surface as the side surface S. Further, the mesa structure M may be one including the light-emitting layer <NUM>, or one including the light-emitting layer <NUM> and the first intermediate layer <NUM>. In each of the cases, the end surface P is spaced apart from the side surface S, and the end surface of each of the layers other than the tunnel junction layer <NUM> can be located on the same surface as the side surface S.

An operation of the VCSEL device <NUM> will be described. <FIG> is a schematic diagram showing the operation of the VCSEL device <NUM>. When a voltage is applied between the first electrode <NUM> (see <FIG>) and the second electrode <NUM>, a current flows between the first electrode <NUM> and the second electrode <NUM>. Here, since the insulating outer peripheral region 107b is provide in the tunnel junction layer <NUM>, a current (arrows in the figure) passes through only the inner peripheral region 107a as shown in <FIG>. Therefore, a current concentrates in the vicinity of the inner peripheral region 107a to form a current injection region R where a current flowing into the light-emitting layer <NUM> concentrates.

As a result, spontaneous emission light due to carrier recombination occurs in the current injection region R. The spontaneous emission light travels in the stacking direction (Z direction) of the VCSEL device <NUM> and is reflected by the first reflection mirror <NUM> and the second reflection mirror <NUM>. Since the first reflection mirror <NUM> and the second reflection mirror <NUM> are configured to reflect light having the oscillation wavelength λ, a component having the oscillation wavelength λ of spontaneous emission light forms a standing wave between the first reflection mirror <NUM> and the second reflection mirror <NUM> and is amplified by the light-emitting layer <NUM>. When the injected current exceeds a threshold value, the light forming the standing wave performs laser oscillation and a laser beam is emitted passing through the second reflection mirror <NUM>.

As described above, in the VCSEL device <NUM>, by providing the insulating outer peripheral region 107b on the outer periphery side of the tunnel junction layer <NUM>, it is possible to realize a current confinement structure by the tunnel junction layer <NUM>.

A method of producing the VCSEL device <NUM> will be described. <FIG> are each a schematic diagram showing a method of producing the VCSEL device <NUM>.

First, as shown in <FIG>, the buffer layer <NUM>, the first reflection mirror <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, and the third intermediate layer <NUM> are stacked on the substrate <NUM> in this order to form a stacked body. These layers can be stacked by a MOCVD (metal organic chemical vapor deposition) method, and doping of a dopant can be performed simultaneously with the stacking.

Next, as shown in <FIG>, the second electrode <NUM> is formed on the third intermediate layer <NUM>. The second electrode <NUM> can have an annular shape having an inner diameter of <NUM> and an outer diameter of <NUM>. Further, as shown in <FIG>, part of the third intermediate layer <NUM> is removed in accordance with the outer diameter of the second electrode <NUM>. The third intermediate layer <NUM> can be removed by wet etching, and an etchant is suitably one that dissolves the third intermediate layer <NUM> and does not dissolve the tunnel junction layer <NUM>. Specifically, in the case where the third intermediate layer <NUM> is formed of n-InP and the tunnel junction layer <NUM> is formed of p+-AlInAs and n+-AlInAs, a mixed solution containing hydrogen bromide and hydrogen peroxide can be used as an etchant.

Next, as shown in <FIG>, part of the tunnel junction layer <NUM> is removed. The tunnel junction layer <NUM> can be removed by wet etching. An etchant is suitably one that dissolves the tunnel junction layer <NUM> and does not dissolve the third intermediate layer <NUM> and the second intermediate layer <NUM>. Specifically, in the case where the tunnel junction layer <NUM> is formed of p+-AlInAs and n+-AlInAs the third intermediate layer <NUM> is formed of n-InP, and the second intermediate layer <NUM> is formed of p-InP, a mixed aqueous solution containing sulfuric acid and hydrogen peroxide can be used as an etchant.

By the removal of the third intermediate layer <NUM> and the tunnel junction layer <NUM>, the mesa structure M is formed. Here, when performing the removal of the tunnel junction layer <NUM>, not only the tunnel junction layer <NUM> located outside the mesa structure M but also the tunnel junction layer <NUM> located inside the mesa structure M is etched from the outer periphery side toward the inner peripheral side (side etching).

As a result, the end surface P of the tunnel junction layer <NUM> is spaced apart from the side surface S of the mesa structure M (see <FIG>). The etching amount of this side etching can be adjusted by the etching time, and can be set to, for example, <NUM> from the side surface S. In this case, when the outer diameter D2 (see <FIG>) of the second electrode <NUM> and the mesa structure M is <NUM>, the outer diameter D1 of the tunnel junction layer <NUM> is <NUM>.

Subsequently, as shown in <FIG>, the tunnel junction layer <NUM> is selectively oxidized from the outer periphery side. As a result, the constituent material of the tunnel junction layer <NUM> is oxidized in the outer peripheral region 107b, and an Al oxide is generated in the outer peripheral region 107b. The inner peripheral region 107a is not oxidized because it is spaced apart from the end surface P, and is maintained as the material containing Al. This oxidation can be performed by placing a stacked body in an oxidation furnace and heating it to <NUM> to <NUM> in a steam atmosphere.

Since oxidation selectively proceeds in a layer having a high Al composition, only the tunnel junction layer <NUM> can be oxidized by increasing the Al composition of the tunnel junction layer <NUM>. Here, the tunnel junction layer <NUM> is side-etched as described above, and the outer diameter D1 is smaller than the outer diameter D2 (see <FIG>). For this reason, the oxidation can be completed in a short time.

Specifically, as shown in <FIG>, the outer peripheral region 107b can be formed by oxidizing the tunnel junction layer <NUM> to the inside by <NUM> than an opening 111a of the second electrode <NUM>, and the width of the outer peripheral region 107b in the X-Y direction can be <NUM>. In the case where the diameter of the opening 111a is <NUM>, the outer diameter D3 (see <FIG>) of the inner peripheral region 107a is <NUM>.

Subsequently, as shown in <FIG>, the insulation layer <NUM> is formed on the second intermediate layer <NUM> and on the side surface S of the mesa structure M. Further, as shown in <FIG>, the second reflection mirror <NUM> is formed on the opening 111a. The second reflection mirror <NUM> can be formed by uniformly stacking a low-refractive index layer and a high-refractive index layer to obtain a plurality of layers and then removing part thereof except for the vicinity of the opening 111a.

Subsequently, the first electrode <NUM> (see <FIG>) is formed on the substrate <NUM>, and the obtained product can be divided into pieces for each device to produce the VCSEL device <NUM>. The VCSEL device <NUM> can be caused to operate by being mounted on a heat sink or the like and electrically connected by wire bonding or the like.

The VCSEL device <NUM> can be produced in this way. As described above, the tunnel junction layer <NUM> is side-etched before oxidation and the outer diameter D1 is smaller than the outer diameter D2. In general, since the oxidation rate of AlInAs is lower than that of AlAs used for an oxidation confinement layer, it is necessary to oxidize AlInAs at a high temperature of approximately <NUM> in order to oxidize AlInAs at realistic oxidation rate.

However, at this high temperature, there is a problem that P and As are separated and the crystal deteriorates. Here, in the production method according to this embodiment, by reducing the outer diameter D1 by side-etching, it is possible to complete oxidation in a short time even in the case where the tunnel junction layer <NUM> is formed of AlInAs. As a result, it is possible to complete oxidation at <NUM> to <NUM> at which P and As are not significantly separated, and produce the VCSEL device <NUM> having a current confinement structure by a producible method.

A VCSEL device according to a second embodiment of the present technology will be described.

<FIG> is a cross-sectional view of a VCSEL device <NUM> according to this embodiment. Note that the same configurations of the VCSEL device <NUM> according to this embodiment as those of the VCSEL device <NUM> according to the first embodiment will be denoted by the same reference symbols as those of the VCSEL device <NUM>, and description thereof will be omitted.

As shown in <FIG>, the VCSEL device <NUM> includes a substrate <NUM>, a bonding layer <NUM>, a first reflection mirror <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, the third intermediate layer <NUM>, the second reflection mirror <NUM>, a first electrode <NUM>, the second electrode <NUM>, and the insulation layer <NUM>.

The substrate <NUM> supports each layer of the VCSEL device <NUM>. The substrate <NUM> can be formed of, for example, Si. The bonding layer <NUM> bonds the substrate <NUM> and the first intermediate layer <NUM> to each other. The bonding layer <NUM> can be formed of, for example, solder.

The first reflection mirror <NUM> is provided on the back surface of the first intermediate layer <NUM>, reflects light of the wavelength λ, and causes light of a wavelength other than that to be transmitted therethrough. The first reflection mirror <NUM> is a DBR in which a low-refractive index layer and a high-refractive index layer having an optical film thickness of λ/<NUM> are alternately stacked to obtain a plurality of layers, and can be a dielectric DBR formed of a dielectric. The low-refractive index layer is formed of, for example, SiO<NUM>, the high-refractive index layer is formed of, for example, Ta<NUM>O<NUM>, and the number of times of stacking can be <NUM> pairs. The first reflection mirror <NUM> is provided at a position facing the current injection region via other layers in the Z direction.

The first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, the third intermediate layer <NUM>, the second reflection mirror <NUM>, the second electrode <NUM>, and the insulation layer <NUM> have configurations similar to those in the first embodiment. Note that the second reflection mirror <NUM> may be a semiconductor DBR instead of a dielectric DBR.

The first electrode <NUM> is provided on the second intermediate layer <NUM> and functions as one electrode of the VCSEL device <NUM>. The first electrode <NUM> can have an annular shape surrounding the mesa structure M and can be formed of, for example, Ti/Pt/Au.

The VCSEL device <NUM> has the configuration as described above. Note that the thickness of the first intermediate layer <NUM> is suitably 5λ in an optical film thickness. Further, the first conductivity type and the second conductivity type in the VCSEL device <NUM> may be reversed, i.e., the first conductivity type may be the p-type and the second conductivity type may be the n-type.

The mesa structure M of the VCSEL device <NUM> has the same configuration as that of the VCSEL device <NUM>, and is configured such that the end surface P of the tunnel junction layer <NUM> is spaced apart from the side surface S of the mesa structure M (see <FIG>).

Also the operation of the VCSEL device <NUM> is similar to that of the VCSEL device <NUM>. When a voltage is applied between the first electrode <NUM> and the second electrode <NUM>, the current injection region R (see <FIG>) is formed by the current confinement structure of the tunnel junction layer <NUM>. The spontaneous emission light causes laser oscillation by the first reflection mirror <NUM> and the second reflection mirror <NUM>, a laser beam is emitted passing through the second reflection mirror <NUM>.

First, as shown in <FIG>, a buffer layer <NUM>, an etching stop layer <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, and the third intermediate layer <NUM> are stacked on a substrate <NUM> in this order to form a stacked body. These layers can be stacked by a MOCVD method, and doping of a dopant can be performed simultaneously with the stacking. The substrate <NUM> is, for example, an n-InP substrate, the buffer layer <NUM> can be a layer formed of, for example, n-InP, and the etching stop layer <NUM> can be a layer formed of, for example, n-InGaAs.

Next, as shown in <FIG>, the second electrode <NUM> is formed on the third intermediate layer <NUM> and then, part of the third intermediate layer <NUM> and the tunnel junction layer <NUM> is removed. This process can be performed in a way similar to that in the first embodiment. As a result, the mesa structure M is formed and the tunnel junction layer <NUM> is side-etched. Further, the first electrode <NUM> is formed on the second intermediate layer <NUM>.

Subsequently, as shown in <FIG>, the tunnel junction layer <NUM> is oxidized from the outer periphery side to generate an Al oxide in the outer peripheral region 107b and the insulation layer <NUM> is formed on the second intermediate layer <NUM> and on the side surface of the mesa structure M, similarly to the first embodiment. Further, the second reflection mirror <NUM> is formed on the opening 111a.

Subsequently, as shown in <FIG>, the substrate <NUM>, the buffer layer <NUM>, and the etching stop layer <NUM> are removed. The removal of these layers can be performed by attaching the stacked body to a support substrate with wax or the like and then performing etching. Further, the first reflection mirror <NUM> (see <FIG>) is formed on the back surface of the first intermediate layer <NUM>. The second reflection mirror <NUM> can be formed by uniformly stacking a low-refractive index layer and a high-refractive index layer to obtain a plurality of layers and then removing part thereof except for the vicinity of the current injection region.

After that, the bonding layer <NUM> is provided on the back surface of the first intermediate layer <NUM>, the substrate <NUM> is attached thereto, and then, the support substrate is removed. Thus, the obtained product can be divided into pieces for each device to produce the VCSEL device <NUM>. The VCSEL device <NUM> can be caused to operate by being mounted on a heat sink or the like and electrically connected by wire bonding or the like.

Since the tunnel junction layer <NUM> is side-etched also in the VCSEL device <NUM> similarly to the first embodiment, it is possible to complete oxidation in a short time even in the case where the tunnel junction layer <NUM> is formed of AlInAs. Therefore, it is possible to produce the VCSEL device <NUM> having a current confinement structure by a producible method.

A VCSEL device according to a third embodiment of the present technology will be described.

As shown in <FIG>, the VCSEL device <NUM> includes a substrate <NUM>, the buffer layer <NUM>, a first reflection mirror <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, the third intermediate layer <NUM>, the second reflection mirror <NUM>, a first electrode <NUM>, the second electrode <NUM>, the insulation layer <NUM>, and a metal layer <NUM>.

The substrate <NUM> supports each layer of the VCSEL device <NUM>. The substrate <NUM> is formed of a semi-insulating material and can be formed of, for example, semi-insulating InP. A projecting portion 301a for making the first reflection mirror <NUM> have a lens shape is provided on the substrate <NUM>.

The first reflection mirror <NUM> is provided on the back surface of the substrate <NUM>, reflects light of the wavelength λ, and causes light of a wavelength other than that to be transmitted therethrough. The first reflection mirror <NUM> is formed on the projecting portion 301a and is formed in a lens shape that collects light on the current injection region, the lens shape having a recessed surface. The lens shape of the first reflection mirror <NUM> may be a spherical lens shape, a cylindrical lens shape, or another lens shape.

The first reflection mirror <NUM> is a DBR in which a low-refractive index layer and a high-refractive index layer having an optical film thickness of λ/<NUM> are alternately stacked to obtain a plurality of layers, and can be a dielectric DBR formed of a dielectric. The low-refractive index layer is formed of, for example, SiO<NUM>, the high-refractive index layer is formed of, for example, Ta<NUM>O<NUM>, and the number of times of stacking can be <NUM> pairs. The first reflection mirror <NUM> is provided at a position facing the current injection region via other layers in the Z direction.

The buffer layer <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, the third intermediate layer <NUM>, the second reflection mirror <NUM>, the second electrode <NUM>, and the insulation layer <NUM> have configurations similar to those in the first embodiment. Note that the second reflection mirror <NUM> may be formed in a lens shape that collects light on the current injection region, the lens shape having a recessed surface, similarly to the first reflection mirror <NUM>. Further, only the second reflection mirror <NUM> may have a lens shape and the first reflection mirror <NUM> does not necessarily need to have a lens shape.

The metal layer <NUM> is formed of a metal, is provided on the back surface of the substrate <NUM>, and covers the first reflection mirror <NUM>. The metal layer <NUM> has a curved surface having a lens shape in accordance with the shape of the first reflection mirror <NUM>.

Also the operation of the VCSEL device <NUM> is similar to that of the VCSEL device <NUM>. When a voltage is applied between the first electrode <NUM> and the second electrode <NUM>, the current injection region R (see <FIG>) is formed by the current confinement structure of the tunnel junction layer <NUM>. The spontaneous emission light causes laser oscillation by the first reflection mirror <NUM> and the second reflection mirror <NUM>, and a laser beam is emitted passing through the second reflection mirror <NUM>.

In this configuration, since the thickness of the first substrate <NUM> is increased, heat dissipation is further improved. Further, since a lens structure is formed in the first reflection mirror <NUM> and the metal layer <NUM>, light emitted from the light-emitting layer <NUM> is collected in the current injection region R of the light-emitting layer <NUM> by this lens structure, and an optical confinement effect can be achieved. As a result, it is possible to prevent the light emission efficiency from decreasing even in the case where the thickness of the first substrate <NUM> is increased.

First, as shown in <FIG>, the buffer layer <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, and the third intermediate layer <NUM> are stacked on the substrate <NUM> in this order to form a stacked body. These layers can be stacked by a MOCVD method, and doping of a dopant can be performed simultaneously with the stacking.

Subsequently, as shown in <FIG>, the tunnel junction layer <NUM> is oxidized from the outer periphery side to generate an Al oxide in the outer peripheral region 107b and the insulation layer <NUM> is formed on the second intermediate layer <NUM> and on the side surface S of the mesa structure M, similarly to the first embodiment. Further, the second reflection mirror <NUM> is formed on the opening 111a.

Subsequently, as shown in <FIG>, the thickness of the substrate <NUM> is reduced to form the projecting portion 301a. The thickness of the substrate <NUM> can be reduced by attaching the surface of the stacked body to a support substrate with wax or the like and then performing etching. The thickness of the substrate <NUM> can be, for example, <NUM>.

The projecting portion 301a can be formed by forming a columnar resist on the back surface of the substrate <NUM> by photolithography, heating it to ball up, and then, performing etching with dry etching to transfer the recessed surface shape of the resist to the substrate <NUM>. The radius of curvature of the projecting portion 301a can be, for example, approximately <NUM>.

Further, the first reflection mirror <NUM> (see <FIG>) is formed on the back surface of the substrate <NUM>. The first reflection mirror <NUM> can be formed by uniformly stacking a low-refractive index layer and a high-refractive index layer to obtain a plurality of layers and then removing part thereof except for the vicinity of the current injection region. Subsequently, the metal layer <NUM> (see <FIG>) is formed on the back surface of the substrate <NUM>.

After that, the support substrate is removed, and the obtained product can be divided into pieces for each device to produce the VCSEL device <NUM>. The VCSEL device <NUM> can be caused to operate by being mounted on a heat sink or the like and electrically connected by wire bonding or the like.

A VCSEL device according to an example not defined in the claims will be described.

<FIG> is a cross-sectional view of a VCSEL device <NUM> according to this example. Note that the same configurations of the VCSEL device <NUM> according to this example as those of the VCSEL device <NUM> according to the first embodiment will be denoted by the same reference symbols as those of the VCSEL device <NUM>, and description thereof will be omitted.

As shown in <FIG>, the VCSEL device <NUM> includes the substrate <NUM>, the buffer layer <NUM>, the first reflection mirror <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, a tunnel junction layer <NUM>, the third intermediate layer <NUM>, the second reflection mirror <NUM>, the first electrode <NUM>, the second electrode <NUM>, and the insulation layer <NUM>.

The substrate <NUM>, the buffer layer <NUM>, the first reflection mirror <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, the third intermediate layer <NUM>, the second reflection mirror <NUM>, the first electrode <NUM>, the second electrode <NUM>, and the insulation layer <NUM> have configurations similar to those in the first embodiment.

Here, the material of each layer can be different from that in the first embodiment, and the substrate <NUM> can be formed of, for example, n-type GaAs. Other layers are each formed a material that can be lattice-matched with the substrate <NUM>. The buffer layer <NUM> can be formed of, for example, n-GaAs, the first intermediate layer <NUM> can be formed of, for example, n-GaAs, the second intermediate layer <NUM> can be formed of, for example, p-GaAs, and the third intermediate layer <NUM> can be formed of, for example, n-GaAs.

Further, the first reflection mirror <NUM> can be a semiconductor DBR formed of an n-type semiconductor material. The low-refractive index layer can be formed of, for example, n-AlAs and the high-refractive index layer can be formed of, for example, n-GaAs. The number of times of stacking can be, for example, <NUM> pairs. The second reflection mirror <NUM> can be a semiconductor DBR formed of an n-type semiconductor material. The low-refractive index layer can be formed of, for example, n-AlAs and the high-refractive index layer can be formed of, for example, n-GaAs. The number of times of stacking can be formed of, for example, <NUM> pairs. Note that one or both of the first reflection mirror <NUM> and the second reflection mirror <NUM> may be a dielectric DBR.

The light-emitting layer <NUM> can be a layer having a multiple quantum well structure in which a quantum well layer and a barrier layer are alternately stacked. The quantum well layer can be formed of, for example, GaInAs, and the barrier layer can be formed of, for example, AlGaAs. The emission wavelength of the light-emitting layer <NUM> can be <NUM>, and the number of wells can be four.

The tunnel junction layer <NUM> is provided on the second intermediate layer <NUM> to form a tunnel junction. <FIG> is a cross-sectional view of the tunnel junction layer <NUM>. <FIG> is a plan view of the tunnel junction layer <NUM> and is a diagram of the tunnel junction layer <NUM> when viewed from the Z direction.

As shown in <FIG>, the tunnel junction layer <NUM> includes a first highly doped layer <NUM> and a second highly doped layer <NUM>. The first highly doped layer <NUM> is a layer on the side of the second intermediate layer <NUM>, and the second highly doped layer <NUM> is formed on a layer on the side of the third intermediate layer <NUM>.

As shown in <FIG>, the tunnel junction layer <NUM> has an inner peripheral region 407a and an outer peripheral region 407b. The inner peripheral region 407a is a region located on the inner peripheral side of the tunnel junction layer <NUM>, and the outer peripheral region 407b is an annular region surrounding the inner peripheral region 407a.

The inner peripheral region 407a of the first highly doped layer <NUM> is formed of a highly doped p-type semiconductor material containing Al, and can be formed of, for example, p+-AlAs. The inner peripheral region 407a of the second highly doped layer <NUM> is formed of a highly doped n-type semiconductor material containing Al, and can be formed of, for example, n+-AlAs.

The outer peripheral region 407b of each of the first highly doped layer <NUM> and the second highly doped layer <NUM> is formed of a material obtained by oxidizing the material of the inner peripheral region 407a and has insulating properties. That is, the outer peripheral region 407b of each of the first highly doped layer <NUM> and the second highly doped layer <NUM> contains an Al oxide and can be formed of, for example, an AlAs oxide. The thickness of each of the first highly doped layer <NUM> and the second highly doped layer <NUM> can be <NUM>. Further, the distance between the tunnel junction layer <NUM> and the light-emitting layer <NUM> is suitably λ/<NUM>.

The VCSEL device <NUM> has the structure as described above. As described above, the substrate <NUM>, the buffer layer <NUM>, the first reflection mirror <NUM>, the first intermediate layer <NUM>, the third intermediate layer <NUM>, and the second highly doped layer <NUM> are each formed of an n-type semiconductor material as a first conductivity type, and the dopant can be Si. The second intermediate layer <NUM> and the first highly doped layer <NUM> are each formed of a p-type semiconductor material as a second conductivity type, and the dopant of the second intermediate layer <NUM> can be Mg. Further, the dopant of the first highly doped layer <NUM> is suitably C that is difficult to diffuse.

The doping concentration can be, for example, <NUM>×<NUM><NUM>[cm-<NUM>] for the first highly doped layer <NUM> and the second highly doped layer <NUM> and approximately <NUM>×<NUM><NUM> to <NUM>×<NUM><NUM>[cm-<NUM>] for the other layers. Note that the first conductivity type and the second conductivity type in the VCSEL device <NUM> may be reversed, i.e., the first conductivity type may be the p-type and the second conductivity type may be the n-type.

The VCSEL device <NUM> has a mesa structure. <FIG> is a cross-sectional view showing a partial configuration of the VCSEL device <NUM>, including the mesa structure. <FIG> is plan view of the mesa structure and is a diagram of the mesa structure when viewed from the Z direction.

As shown in these figures, the tunnel junction layer <NUM> and the third intermediate layer <NUM> are formed in a mesa shape to form the mesa structure M. As shown in <FIG>, the mesa structure M can have a circular shape when viewed from the Z direction. The mesa structure M is formed such that the inner peripheral region 407a of the tunnel junction layer <NUM> is located at the center of the mesa structure M and includes a current injection region.

As shown in <FIG>, the side surface of the mesa structure M is referred to as the side surface S. The side surface S is the outer peripheral surface of the mesa structure M along the Z direction and can be a cylindrical surface. Further, the end surface of the tunnel junction layer <NUM> can be referred to as the end surface P. The end surface P is the outer peripheral surface of the outer peripheral region 407b along the Z direction and can be a cylindrical surface. As shown in <FIG>, the outer peripheral region 407b is formed to a certain depth in the X-Y direction from the end surface P, and the inner peripheral region 407a is spaced apart from the end surface P by the outer peripheral region 407b.

In this example, the outer diameter of the tunnel junction layer <NUM> corresponds to the outer diameter of the third intermediate layer <NUM>. For this reason, the end surface P is located on the same surface as the side surface S. An outer diameter D4 of the mesa structure M can be, for example, <NUM>. Further, an outer diameter D5 of the inner peripheral region 407a can be, for example, <NUM>.

The mesa structure M is formed as described above. Note that the mesa structure M is not limited to the one including only the tunnel junction layer <NUM> and the third intermediate layer <NUM> and may be, for example, one including the second intermediate layer <NUM> in addition thereto. In this case, the end surfaces of the third intermediate layer <NUM> and the second intermediate layer <NUM> are located on the same surface as the side surface S. Further, the mesa structure M may be one including the light-emitting layer <NUM>, or one including the light-emitting layer <NUM> and the first intermediate layer <NUM>. In each of the cases, the end surface P can be located on the same surface as the side surface S.

First, as shown in <FIG>, the buffer layer <NUM>, the first reflection mirror <NUM>, the first intermediate layer <NUM>, the light-emitting layer <NUM>, the second intermediate layer <NUM>, the tunnel junction layer <NUM>, and the third intermediate layer <NUM> are stacked on the substrate <NUM> in this order to form a stacked body. These layers can be stacked by a MOCVD method, and doping of a dopant can be performed simultaneously with the stacking.

Next, as shown in <FIG>, the second electrode <NUM> is formed on the third intermediate layer <NUM>. The second electrode <NUM> can have an annular shape having an inner diameter of <NUM> and an outer diameter of <NUM>. After that, part of the third intermediate layer <NUM> and the tunnel junction layer <NUM> is removed in accordance with the outer diameter of the second electrode <NUM>. The removal of third intermediate layer <NUM> and the tunnel junction layer <NUM> can be performed with dry etching.

The removal of the third intermediate layer <NUM> and the tunnel junction layer <NUM> forms the mesa structure M. In this example, the tunnel junction layer <NUM> is not side-etched, and the end surface P of the tunnel junction layer <NUM> is located on the same surface as the side surface S of the mesa structure M.

Subsequently, as shown in <FIG>, the tunnel junction layer <NUM> is selectively oxidized from the outer periphery side. As a result, the constituent material of the tunnel junction layer <NUM> is oxidized in the outer peripheral region 407b, and an Al oxide is generated in the outer peripheral region 407b. The inner peripheral region 407a is not oxidized because it is spaced apart from the end surface P, and is maintained as the material containing Al. This oxidation can be performed by placing a stacked body in an oxidation furnace and heating it to <NUM> to <NUM> in a steam atmosphere.

Since oxidation selectively proceeds in a layer having a high Al composition, only the tunnel junction layer <NUM> can be oxidized by increasing the Al composition of the tunnel junction layer <NUM>. Further, in the case where the tunnel junction layer <NUM> is formed of AlAs, it is possible to complete the oxidation in a short time because the oxidation rate of AlAs is high.

Specifically, as shown in <FIG>, the outer peripheral region 407b can be formed by oxidizing the tunnel junction layer <NUM> to the inside by <NUM> than the opening 111a of the second electrode <NUM>. In the case where the diameter of the opening 111a is <NUM>, the outer diameter D5 (see <FIG>) of the inner peripheral region 407a is <NUM>.

Subsequently, as shown in <FIG>, the insulation layer <NUM> is formed on the second intermediate layer <NUM> and on the side surface S of the mesa structure M, and the second reflection mirror <NUM> is formed on the opening 111a. The second reflection mirror <NUM> can be formed by uniformly stacking a low-refractive index layer and a high-refractive index layer to obtain a plurality of layers and then removing part thereof except for the vicinity of the opening 111a.

Subsequently, the first electrode <NUM> (see <FIG>) is formed of the substrate <NUM>, and the obtained product is divided into pieces for each device to produce the VCSEL device <NUM>. The VCSEL device <NUM> can be caused to operate by being mounted on a heat sink or the like and electrically connected by wire bonding or the like.

The VCSEL device <NUM> can be produced as described above. In this example, although the tunnel junction layer <NUM> is not side-etched, it is possible to complete oxidation in a short time by forming the tunnel junction layer <NUM> of AlAs whose oxidation rate is high. Therefore, it is possible to produce the VCSEL device <NUM> having a current confinement structure by a producible method.

Claim 1:
A vertical cavity surface emitting laser device (<NUM>), comprising:
a first reflection mirror (<NUM>) that reflects light of a specific wavelength;
a second reflection mirror (<NUM>) that reflects light of the wavelength;
a first semiconductor layer (<NUM>) that is disposed between the first reflection mirror and the second reflection mirror and is formed of a semiconductor material having a first conductivity type;
a second semiconductor layer (<NUM>) that is disposed between the first reflection mirror and the second reflection mirror and is formed of a semiconductor material having a second conductivity type;
a tunnel junction layer (<NUM>) that is disposed between the first reflection mirror and the second reflection mirror, a highly doped layer (<NUM>) of the first conductivity type and a highly doped layer (<NUM>) of the second conductivity type being joined together in the tunnel junction layer, the tunnel junction layer having an inner peripheral region (107a) on an inner peripheral side when viewed from a direction perpendicular to a layer surface and an outer peripheral region (107b) surrounding the inner peripheral region, the inner peripheral region being formed of a material containing Al, the outer peripheral region being formed of a material containing an Al oxide; and
a light-emitting layer (<NUM>) that is disposed between the first reflection mirror and the second reflection mirror and emits light by carrier recombination,
the vertical cavity surface emitting laser device having a mesa structure that has a current injection region where a current passing through the inner peripheral region and flowing into the light-emitting layer concentrates; wherein
the tunnel junction layer has an end surface (P) that is an outer peripheral surface along the direction of the outer peripheral region,
the mesa structure has a side surface (S) that is an outer peripheral surface along the direction, and
the end surface is spaced apart from the side surface and displaced towards the inner peripheral region.