Patent Description:
Although there is a growing demand to install more peripherals on a single machine, a Peripheral Component Interconnect Express (PCIe) interface provided by a host is limited. To solve this, Input/Output (I/O) switches such as a PCIe switch, a Platform Controller Hub (PCH), and a virtualization card are installed in the machine, allowing peripheral devices to share a limited PCIe interface.

However, when congestion occurs due to saturation of PCIe link capacity of the host due to PCIe traffic of the peripheral devices, information of other tenants may be leaked due to transmission delay. Patent document <CIT> is regarded as relevant prior art.

According to an aspect of the present disclosure, a method includes: receiving, by a storage device, a plurality of read commands generated by a tenant from a host; calculating, based on the plurality of read commands satisfying a predetermined condition, each latency of the plurality of read commands and obtaining the calculated plurality of latencies; calculating a uniformity of the plurality of latencies; and determining, based on the uniformity that is within a predetermined ratio range, that there is an attack from the tenant.

According to another aspect of the present disclosure, a method includes: determining that a command received from a host is an attack by using In-Band (IB) communication; adjusting a latency of the command; and sending, to the host, at least one of an attack detection command to inform that an attack has been detected or a latency adjustment command to inform the host that the latency has been adjusted, by using Out-Of-Band (OOB) communication.

According to another aspect of the present disclosure, a storage device includes: an attack detector configured to determine an attacking tenant from among a plurality of tenants connected to a host based on a determination that there is an attack from the host; a budget calculator configured to calculate a latency range of the attacking tenant based on a service policy of the host; and a latency adjuster configured to adjust a latency for the attacking tenant based on the latency range.

The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the scope of the invention as defined by the claims.

Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In the flowcharts described with reference to the drawings in this specification, the operation order may be changed, various operations may be merged, certain operations may be divided, and certain operations might not be performed.

In addition, a singular form may be intended to include a plural form as well i.e. not exclude a plural form, unless the explicit expression such as "one" or "single" is used. Terms including ordinal numbers such as first, second, and the like will be used only to describe various constituent elements, and are not to be interpreted as limiting these constituent elements. These terms may be used for a purpose of distinguishing one component from other components.

<FIG> illustrates a schematic block diagram of an electronic system according to an embodiment. In <FIG>, an electronic system <NUM> may include a first electronic device <NUM>, a second electronic device <NUM>, and a server <NUM>.

The server <NUM> may manage a plurality of tenants. The plurality of tenants may respectively correspond to a plurality of users. Alternatively, the plurality of tenants may respectively correspond to a plurality of electronic devices. For example, a first tenant of the plurality of tenants may access the server <NUM> by using the first electronic device <NUM>, and a second tenant of the plurality of tenants may access the server <NUM> by using the second electronic device <NUM>.

Each of the first electronic device <NUM> and the second electronic device <NUM> may be a Personal Computer (PC) having a display, or a portable electronic device. Here, the portable electronic device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a Mobile Internet Device (MID), a Personal Digital Assistant (PDA), an Enterprise Digital Assistant (EDA), or a wearable device. The wearable device may include a smart watch, a smart band, and smart glasses.

The first electronic device <NUM> and the second electronic device <NUM> may communicate with the server <NUM> to use components of the server <NUM>. For example, the components of the server <NUM> may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), a Tensor Processing Unit (TPU), a Network Interface Card (NIC), a memory device, a storage device, and the like. The NIC may include an Ethernet NIC, a Remote Direct Memory Access (RDMA) NIC, and the like. The memory device is a Dynamic Random Access Memory (DRAM), and may include a Compute Express Link (CXL) DRAM operating based on a Peripheral Component Interconnect Express (PCIe) interface. The storage device may include a Solid State Drive (SSD) device capable of processing input/output (I/O) through an I/O switch. For example, the SSD device may be a Non-Volatile Memory Express (NVMe) SSD, a CXL SSD, a CXL computational SSD (also referred to as a smart SSD), or the like.

The server <NUM> may communicate with the first electronic device <NUM> or the second electronic device <NUM> by using a network. The network may be a connection structure capable of exchanging information between nodes such as devices and servers. For example, the network may include a Radio Frequency (RF), a 3rd Generation Partnership Project (3GPP) network, a Long Term Evolution (LTE) network, a 5th Generation Partnership Project (5GPP) network, a World Interoperability for Microwave Access (WIMAX) network, Internet, a Local Area Network (LAN), a wireless LAN, a Wide Area Network (WAN), a Personal Area Network (PAN), a Value Added Network (VAN), a Bluetooth network, a Near Field Communication (NFC) network, a satellite broadcasting network, an analog broadcast network, A Digital Multimedia Broadcasting (DMB) network, and the like, but is not limited thereto.

In one embodiment, the first tenant may be a normal tenant (victim), and the second tenant may be an attacking tenant (attacker). The first electronic device <NUM> may use a first component of the server <NUM> as the first tenant. The second electronic device <NUM> may use a second component of the server <NUM> as the second tenant. The first component used by the first electronic device <NUM> and the second component used by the second electronic device <NUM> may be connected to a host of the server <NUM> through an I/O switch. The I/O switch may extend PCIe support of the host. That is, the first component and the second component may share a PCIe link of the host. The I/O switch may be an interconnector based on the PCIe, and may be implemented as a PCIe switch, a CXL switch, a Platform Controller Hub (PCH), a virtualization card, or the like.

The second electronic device <NUM> may perform a side-channel attack by making the PCIe link congested (busy). The second electronic device <NUM> may saturate the PCIe link capacity by generating aggregated PCIe traffics. For example, the second electronic device <NUM> may request the host to send a continuous command to the second component. The host may fill a transmission queue that it sends to the second component with a command. The second electronic device <NUM> may obtain information on the first component used by the first electronic device <NUM> by measuring latency for the command. The latency may mean a processing time of a command.

The server <NUM> may include a defense device <NUM> capable of detecting and responding to a side-channel attack. After detecting and responding to the side-channel attack, the defense device <NUM> may notify the host of the attack detection and attack response.

In one embodiment, the defense device <NUM> may be included in the I/O switch or I/O device of the server <NUM>. In this case, the I/O device may be a GPU, an NPU, a TPU, a Network Interface Card (NIC), or the like. The defense device <NUM> may determine whether a command received through In-Band (IB) communication is an attack, and when it corresponds to the attack, the defense device <NUM> may notify the host of the attack detection and attack response through the IB communication. The IB communication may correspond to a communication through the PCIe link. A processor of the host may perform the IB communication. That is, the defense device <NUM> may notify the processor of the host of the attack detection and attack response. An embodiment in which the defense device <NUM> is included in the I/O device will be described later with reference to <FIG>, <FIG>, and <FIG>.

In one embodiment, the defense device <NUM> may be included in a memory device or a storage device of the server <NUM>. The defense device <NUM> may determine whether a command received through the IB communication is an attack, and when it corresponds to the attack, the defense device <NUM> may notify the host of the attack detection and attack response through Out-Of-Band (OOB) communication. The OOB communication may correspond to a communication through a System Management Bus (SMBus), an inter-integrated circuit (I2C) protocol, or an improved inter integrated circuit (I3C) protocol. A baseboard management controller (BMC) of the host may perform the OOB communication. That is, the defense device <NUM> may notify the BMC of the host of the attack detection and attack response. An embodiment in which the defense device <NUM> is included in the storage device will be described later with reference to <FIG>, <FIG>, and <FIG>.

<FIG> illustrates a schematic block diagram of a defense device according to an embodiment. In <FIG>, the defense device <NUM> may include an attack detector <NUM>, a budget calculator <NUM>, a latency adjuster <NUM>, and a command generator <NUM>.

The attack detector <NUM> may determine whether a command from the host is an attack. For example, the attack detector <NUM> may detect an attack training pattern and an attack I/O pattern. The attack detector <NUM> may determine whether there is an attack when at least one of the attack training pattern or the attack I/O pattern is detected.

The attack training pattern may indicate a pattern in which there is a data transmission having a plurality of settings, thereby causing periodic latency. The data having the plurality of settings may indicate data having different traffic volumes. Taking a command as an example, the data having the plurality of settings may indicate a plurality of commands having the same command type but different volumes. An attacker may find a data transmission setting that generates a desired traffic volume and maintains a high and stable sampling rate through an attack training pattern. That is, the attack detector <NUM> may determine whether an attack training pattern has been received when periodically receiving data having a plurality of settings for finding a uniform latency. For example, the attack detector <NUM> may determine that an attack training pattern has been received when periodically and continuously receiving read commands having different volumes.

The attack I/O pattern may indicate a pattern in which commands are continuously received with the data transmission setting found in the attack training pattern for a predetermined period, and uniformity of latencies of the commands is within a predetermined ratio. The successive reception of commands may indicate that a transmission queue of the host is filled with a plurality of commands with the same command type and the same volume. For example, the attack detector <NUM> may continuously receive <NUM> kilobyte (kB) read commands among read commands having different volumes in the transmission queue of the host. The attack detector <NUM> may measure latencies of the <NUM> kB read commands, and may determine whether uniformity of the latencies is within a predetermined ratio (for example, <NUM> to <NUM> %). The attack detector <NUM> may remove noise when measuring latencies. For example, when the storage device performs an internal operation during command processing, the attack detector <NUM> may remove the corresponding latency. As another example, when there is a write command between the <NUM> kB read commands, the attack detector <NUM> may remove the corresponding latency. The attack detector <NUM> may determine that an attack I/O pattern has been received when the uniformity of the latencies is within a predetermined ratio. The attacker may obtain victim's information through the attack I/O pattern.

In <FIG>, the budget calculator <NUM> may determine a latency range for each tenant. The latency range may include a minimum latency and a maximum latency. The budget calculator <NUM> may determine a latency range based on a service policy designated by the host. The service policy may include tenant priority, bandwidth, timeout limit, and the like. For example, the budget calculator <NUM> may determine the maximum latency for the command of the second electronic device <NUM> (second tenant) to be <NUM> seconds based on a timeout limit designated by the host.

In <FIG>, the latency adjuster <NUM> may adjust the latency in response to the command of the attacker. The latency adjuster <NUM> may adjust the latency within the latency range determined by the budget calculator <NUM>. For example, the component including the defense device <NUM> may process the command of the second electronic device <NUM> in <NUM> seconds. In this case, the latency adjuster <NUM> may adjust the latency within <NUM> seconds determined by the budget calculator <NUM> and send it to the host, without directly sending the processing result to the host.

In <FIG>, the command generator <NUM> may generate a command to be sent to the host. The command generator <NUM> may generate at least one of an attack detection command, a latency adjustment command, and a priority adjustment command. The attack detection command may be a command for notifying that an attack has been detected. The latency adjustment command may be a command for notifying that the latency of the attacker's command has been adjusted in response to the attacker's attack. The priority adjustment command may be a command for notifying that the priority of the attacker has been adjusted in response to the attacker's attack. The server may define a priority as a service policy for a plurality of tenants, and may adjust the priority of a tenant determined as an attacker. The command generator <NUM> may generate a command according to the component type to which the defense device <NUM> belongs.

In one embodiment, when the defense device <NUM> belongs to the storage device of the server <NUM>, the command generator <NUM> may generate a command of a Non-Volatile Memory Express-Management Interface (NVMe-MI) standard. In this case, the defense device <NUM> may send a command to the host by using one of a SMBus, an I2C protocol, or an I3C protocol.

In one embodiment, when the defense device <NUM> belongs to an I/O device such as a GPU or an NIC of the server <NUM>, the command generator <NUM> may generate a command of the PCIe standard. In this case, the defense device <NUM> may send a command to the host by using the PCIe protocol.

<FIG> illustrates that the server <NUM> communicates with the first electronic device <NUM> and the second electronic device <NUM>, but the present disclosure is not limited thereto. For example, the server <NUM> may include three or more tenants, and the tenants may be implemented by using their respective electronic devices to communicate with the server <NUM>.

<FIG> illustrates a server according to an embodiment, and <FIG> illustrates an example of an attack that may occur in the server of <FIG>.

In <FIG>, according to an embodiment, a server <NUM> may include a host <NUM>, an I/O switch <NUM>, and a plurality of I/O devices 330_1 to 330_n. Here, n may be an integer greater than <NUM>.

The host <NUM> may include a processor <NUM> that manages and controls overall operations of the server <NUM>. The processor <NUM> may receive a command from a tenant, may process the command by using the I/O switch <NUM> and at least one of the plurality of I/O devices 330_1 to 330_n, and may send the processing result to the tenant.

The processor <NUM> may be connected to the plurality of I/O devices 330_1 to 330_n through the I/O switch <NUM>. In one embodiment, there may be an I/O device directly connected to the processor <NUM> without using the I/O switch <NUM>.

The I/O switch <NUM> may extend PCIe support of the host <NUM>. The processor <NUM> and the I/O switch <NUM> may be connected by a PCIe link, and the I/O switch <NUM> and the plurality of I/O devices 330_1 to 330_n may be connected by a PCIe link. That is, the plurality of I/O devices 330_1 to 330_n may share the PCIe link of the host <NUM>. In this case, a port through which the I/O switch <NUM> is connected to the host <NUM> may be referred to as an upstream port, and a port connected to the plurality of I/O devices 330_1 to 330_n may be referred to as a downstream port.

The plurality of I/O devices 330_1 to 330_n may be a GPU, an NPU, a TPU, an NIC, a storage device, and the like. For example, the tenant may use an Artificial Intelligence (Al) function through an I/O device that is a GPU. The tenant may use a web search function through an I/O device that is an NIC. The tenant may read, delete, or write data through an I/O device that is a storage device.

The server <NUM> may detect and respond to an attack of the second tenant by using the defense device <NUM> described with reference to <FIG> and <FIG>, and may report it to the processor <NUM>. Here, the attack may be a side-channel attack.

In one embodiment, the I/O switch <NUM> may include the defense device <NUM>. That is, the I/O switch <NUM> may detect and respond to an attack, and may report it to the processor <NUM>.

In one embodiment, at least one of the plurality of I/O devices 330_1 to 330_n may include the defense device <NUM>. That is, the I/O device including the defense device <NUM> may detect and respond to an attack, and may report it to the processor <NUM>.

In <FIG>, a scenario in which two tenants use the server <NUM> of <FIG> may be confirmed. The two tenants may include a first tenant that is a normal tenant, and a second tenant that is an attacking tenant.

The first tenant may get access to the server <NUM> by using the first electronic device <NUM> to use the first I/O device 330_1. For example, the first I/O device 330_1 may be a GPU, and the first tenant may use an AI function by using the first I/O device 330_1.

The second tenant may use the second electronic device <NUM> to get access to the server <NUM> to use the second I/O device 330_2. For example, the second I/O device 330_2 may be an RDMA NIC, and the second tenant may use the second I/O device 330_2 to access a memory area.

The second I/O device 330_2 may include a defense device <NUM> that detects and responds to an attack and reports it to the processor <NUM>. The defense device <NUM> may have substantially the same configuration and operation as the defense device <NUM> of <FIG> and <FIG>.

The defense device <NUM> may determine whether the command received by the second I/O device 330_2 is an attack. The second I/O device 330_2 may receive a command through the PCIe link. For example, the defense device <NUM> may detect an attack training pattern and an attack I/O pattern of the second tenant. When the defense device <NUM> detects at least one of the attack training pattern and the attack I/O pattern, the defense device <NUM> may determine that there is an attack. The defense device <NUM> may notify the processor <NUM> that there is an attack. The defense device <NUM> may notify the processor <NUM> that there is an attack through the PCIe link. The configuration and operation of the defense device <NUM> is the same as the configuration and operation of the defense device <NUM> described with reference to <FIG>, so a detailed description thereof will be omitted.

The defense device <NUM> may determine an attacker based on the attack. The defense device <NUM> may detect at least one of the attack training pattern and the attack I/O pattern, and may determine a subject of an attack command. The defense device <NUM> may notify the processor <NUM> of an attacker or an attacker's identification.

For example, the defense device <NUM> may determine that at least one of the attack training pattern or the attack I/O pattern originates from the second electronic device <NUM> that is a second tenant. The defense device <NUM> may notify the processor <NUM> that the second tenant is the attacker.

The processor <NUM> may determine whether the second tenant is a real attacker. For example, the processor <NUM> may determine whether the attacker determined by the defense device <NUM> is a real attacker based on tenant information. The tenant information may include reliability of the tenant, and the like. When the processor <NUM> determines that the second tenant is a real attacker, it may operate based on a defense policy. When the processor <NUM> determines that the second tenant is not a real attacker, it may ignore the notification of the defense device <NUM>.

The defense device <NUM> may respond to the attack. The defense device <NUM> may determine a latency range of the second tenant determined to be an attacker based on the service policy of the host <NUM>. The latency range may include a minimum latency and a maximum latency. The service policy may include tenant priority, bandwidth, timeout limit, and the like. For example, the defense device <NUM> may determine the maximum latency for the second tenant to be <NUM> seconds based on the timeout limit.

The defense device <NUM> may adjust the latency for the second tenant based on the latency range. For example, even if the second I/O device 330_2 processes the command of the second tenant in only <NUM> seconds, as the defense device <NUM> adjusts the latency within <NUM> seconds, the processing result may not be directly sent to the processor <NUM>.

<FIG> illustrates that the second I/O device 330_2 includes the defense device <NUM>, but the present disclosure is not limited thereto, and other I/O devices (330_1, 330_n,. ) may additionally or optionally include the defense device <NUM>.

<FIG> illustrates a schematic block diagram of a server according to an embodiment. <FIG> illustrates a drawing for explaining an operation of a storage device according to an embodiment. <FIG> illustrates a drawing for explaining an example of an attack that may occur in the server of <FIG>. <FIG> illustrates a command of a storage device according to an embodiment.

In <FIG>, according to an embodiment, a server <NUM> may determine an attacker in substantially the same manner as the server <NUM> of <FIG> and perform a response operation against the attack.

The server <NUM> may include a host <NUM>, an I/O switch <NUM>, a plurality of I/O devices 430_1 to 430_n, and a storage device <NUM>. Here, n may be an integer greater than one (<NUM>).

The host <NUM> may include a processor <NUM> that manages and controls overall operations of the server <NUM> and a BMC <NUM> (that is a management subsystem) that monitors and manages system hardware. The processor <NUM> may perform IB communication, and the BMC <NUM> may perform OOB communication. The processor <NUM> and the BMC <NUM> may independently operate. Accordingly, the BMC <NUM> may operate without affecting the operation of the processor <NUM>, and may operate even when the processor <NUM> is unavailable.

The processor <NUM> may receive a command from a tenant, may process the command by using at least one of the I/O switch <NUM>, the plurality of I/O devices 430_1 to 430_n, and the storage device <NUM>, and may send the processing result to the tenant.

The processor <NUM> may be connected to the plurality of I/O devices 430_1 to 430_n and the storage device <NUM> through the I/O switch <NUM>. In one embodiment, there may be an I/O device directly connected to the processor <NUM> without using the I/O switch <NUM>.

The I/O switch <NUM> may extend PCIe support of the host <NUM>. The processor <NUM> and the I/O switch <NUM> may be connected by one PCIe link. The I/O switch <NUM>, the plurality of I/O devices 430_1 to 430_n, and the storage device <NUM> may be connected by other PCIe links. That is, the plurality of I/O devices 430_1 to 430_n and the storage device <NUM> may share the PCIe link of the host <NUM>.

The plurality of I/O devices 430_1 to 430_n may be a GPU, an NPU, a TPU, an NIC, a storage device, and the like. For example, the tenant may use an AI function through an I/O device that is a GPU. The tenant may use a web search function through an I/O device that is an NIC. The tenant may read, delete, or write data through an I/O device that is a storage device.

The storage device <NUM> may be connected to the BMC <NUM>. That is, the storage device <NUM> may perform IB communication with the processor <NUM> and the I/O switch <NUM>, and may perform OOB communication with the BMC <NUM>.

In <FIG>, the connection relationship between the components of the server <NUM> may be confirmed. The storage device <NUM> may include a controller <NUM>, a Satellite Management Controller (SMC) <NUM>, and a plurality of ports 441_1 to 441_m. Here, m may be an integer greater than <NUM>. The I/O switch <NUM> may include a plurality of ports <NUM>, <NUM>, and 423_1 to 423_n. Here, the port <NUM> may be an upstream port connected to the processor <NUM> of the host <NUM>. The ports <NUM> and 423_1 to 423_n may be downstream ports connecting the plurality of I/O devices 430_1 to 430_n and the storage device <NUM>. The BMC <NUM> may include a plurality of ports <NUM> and <NUM>. The processor <NUM> may include a plurality of ports <NUM> and <NUM>. Each of the plurality of I/O devices 430_1 to 430_n may include a port 433_1 to 433_n.

In one embodiment, the ports <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, 423_1 to 423_n, and 433_1 to 433_n, 441_1 may be PCIe ports. In one embodiment, the ports <NUM> and 441_2 may be SM Bus ports, I2C protocol ports, or I3C protocol ports.

The controller <NUM> of the storage device <NUM> may perform IB communication with the I/O switch <NUM> and the processor <NUM> through the port 441_1. The port 441_1 and the port <NUM> may be connected to form a PCIe link. In addition, the port <NUM> and the port <NUM> may be connected to form a PCIe link.

The PCIe link between the port <NUM> and the port <NUM> may be easily congested by the controller <NUM> and the plurality of I/O devices 430_1 to 430_n due to limited PCIe support of the processor <NUM> of the host <NUM>. The plurality of I/O devices 430_1 to 430_n may perform IB communication with the I/O switch <NUM> and the processor <NUM> through the plurality of ports 433_1 to 433_n. The plurality of ports 423_1 to 423_n and the plurality of ports 433_1 to 433_n may be connected to each other to form a PCIe link. In this case, the attacker may obtain the victim's information by using the congestion of the PCIe link.

The SMC <NUM> may perform OOB communication with the BMC <NUM> of the host <NUM> through the port 441_2. The port 441_2 and the port <NUM> may be connected to form a Management Component Transport Protocol (MCTP) link. The SMC <NUM> may send status information, log information, device health information, and the like of the storage device <NUM> to the BMC <NUM>. The status information of the storage device <NUM> may include whether an attack has occurred, whether to respond to an attack, and the like.

The SMC <NUM> and the controller <NUM> may independently operate. For example, even if the controller <NUM>, main firmware, main power, internal power, and the like in the storage device <NUM> are abnormal, the SMC <NUM> may use a power source of the host <NUM> to send status information, log information, and device health information of the storage device <NUM> to the BMC <NUM>. For example, the SMC <NUM> may use an auxiliary power source of the host <NUM>.

The BMC <NUM> may perform IB communication with the processor <NUM> through the port <NUM>. The port <NUM> and the port <NUM> may be connected to form a PCIe link.

The controller <NUM> and the SMC <NUM> may communicate with each other by using an internal bus of the storage device <NUM>. In one embodiment, each component of the server <NUM> may further include a port as needed.

Referring back to <FIG>, the storage device <NUM> may include a defense device <NUM>. The defense device <NUM> may have substantially the same configuration and operation as the defense device <NUM> of <FIG> and <FIG>.

In one embodiment, the defense device <NUM> of the storage device <NUM> may be included in the controller <NUM>. In this case, the controller <NUM> may notify the SMC <NUM> of the attack detection and attack response based on an operation of the defense device <NUM>. The SMC <NUM> may notify the BMC <NUM> of attack detection and attack response.

In one embodiment, the defense device <NUM> of the storage device <NUM> may be included in the SMC <NUM>. In this case, the SMC <NUM> may notify the BMC <NUM> of attack detection and attack response according to an operation of the defense device <NUM>.

In one embodiment, the defense device <NUM> of the storage device <NUM> may be disposed outside of the controller <NUM> and the SMC <NUM>. In this case, the defense device <NUM> may notify the SMC <NUM> of the attack detection and attack response. The SMC <NUM> may notify the BMC <NUM> of the attack detection and attack response.

In one embodiment, the defense device <NUM> of the storage device <NUM> may be implemented as firmware or software. The SMC <NUM> may notify the BMC <NUM> of attack detection and attack response according to an operation of the defense device <NUM>.

The first tenant may access the server <NUM> by using the first electronic device <NUM> to use the first I/O device 430_1. For example, the first I/O device 430_1 may be a GPU, and the first tenant may use an AI function by using the first I/O device 430_1.

The second tenant may use the second electronic device <NUM> to access the server <NUM> to use the storage device <NUM>. For example, the second tenant may read or delete data of the storage device <NUM>, or may write data to the storage device <NUM>.

The storage device <NUM> may include the defense device <NUM> that detects and responds to an attack and reports it to the BMC <NUM>. The defense device <NUM> may determine whether the command received by the storage device <NUM> is an attack. The storage device <NUM> may receive a command through a PCIe link. For example, the defense device <NUM> may detect an attack training pattern and an attack I/O pattern of the second tenant. When the defense device <NUM> detects at least one of the attack training pattern and the attack I/O pattern, the defense device <NUM> may determine that there is an attack. The configuration and operation of the defense device <NUM> are the same as the configuration and operation of the defense device <NUM> described with reference to <FIG>, so a detailed description thereof will be omitted.

The defense device <NUM> may determine an attacker corresponding to the attack. The defense device <NUM> may detect at least one of the attack training pattern or the attack I/O pattern, and may determine a subject of an attack command. The defense device <NUM> may notify the BMC <NUM> of an attacker. The BMC <NUM> may notify the processor <NUM> of an attacker.

For example, the defense device <NUM> may determine that at least one of the attack training pattern or the attack I/O pattern originates from the second electronic device <NUM> of the second tenant. The defense device <NUM> may notify the BMC <NUM> that the second tenant is the attacker. The BMC <NUM> may notify the processor <NUM> that the second tenant is the attacker.

The defense device <NUM> may communicate with the BMC <NUM> by using SMBus, Intelligent Interface Controller (I2C), Improved Inter-Integrated Circuit (I3C) ports. That is, the defense device <NUM> may notify the BMC <NUM> of attack information by using one of a SMBus, an I2C protocol, and an I3C protocol. The attack information may include the presence of an attack, an attacker, an attack response method, and the like.

In this case, the defense device <NUM> may notify the BMC <NUM> of the attack information by using a command according to the NVMe-MI standard. In one embodiment, the command according to the NVMe-MI standard may be as shown in <FIG>.

In <FIG>, as an example of the command according to the NVMe-MI standard, the BMC <NUM> may send a Non-Volatile Memory (NVM) sub-system health status poll command to the SMC <NUM>. Transmission bytes of the BMC <NUM> are highlighted with gray. In response to this, the SMC <NUM> may send a response to the NVM subsystem health status poll command to the BMC <NUM>. The transmission byte, which is a response (Ack) of the SMC <NUM>, is highlighted with white.

The SMC <NUM> may notify the BMC <NUM> of attack information by using at least one of reserved areas <NUM> to <NUM>. The BMC <NUM> may notify the processor <NUM> of the attack information through the PCIe link.

The processor <NUM> may determine whether the second tenant is a real attacker. When the processor <NUM> determines that the second tenant is a real attacker, the processor <NUM> may operate based on a defense policy. When the processor <NUM> determines that the second tenant is not a real attacker, the processor <NUM> may ignore the notification of the defense device <NUM>.

The defense device <NUM> may respond to an attack. The defense device <NUM> may determine a latency range of the second tenant determined to be an attacker based on the service policy of the host <NUM>. The latency range may include a minimum latency and a maximum latency. The service policy may include tenant priority, bandwidth, timeout limit, and the like. For example, the defense device <NUM> may determine the maximum latency for the second tenant to be <NUM> seconds based on the timeout limit.

The defense device <NUM> may adjust the latency for the second tenant based on the latency range. For example, even if the storage device <NUM> processes the command of the second tenant in only <NUM> seconds, as the defense device <NUM> adjusts the latency within <NUM> seconds, the processing result may not be directly sent to the processor <NUM>. The defense device <NUM> may notify the BMC <NUM> of the time the command is processed by reflecting the adjusted latency.

<FIG> and <FIG> illustrate that the storage device <NUM> includes the defense device <NUM>, but the present disclosure is not limited thereto. For example, the I/O switch <NUM> may include the defense device <NUM>, and/or at least one of the plurality of I/O devices 430_1 to 430_n may include the defense device <NUM>. In addition, the storage device <NUM> described with reference to <FIG> may be replaced with a memory device.

<FIG> illustrates a schematic block diagram of a server according to an embodiment. In <FIG>, according to an embodiment, a server <NUM> may include a host <NUM>, I/O switches <NUM> and <NUM>, and a plurality of I/O devices 540_1 to 540_p and 550_1 to 550_q. Here, p and q may be integers greater than <NUM>.

The host <NUM> may include a processor <NUM> that manages and controls overall operations of the server <NUM>. The processor <NUM> may receive a command from a tenant, may process the command by using at least one of the I/O switches <NUM> and <NUM> and at least one of the plurality of I/O devices 540_1 to 540_p and 550_1 to 550_q, and may send the processing result to the tenant.

As illustrated in <FIG>, the processor <NUM> may be connected to the plurality of I/O devices 540_1 to 540_p through the I/O switch <NUM>. The processor <NUM> may be connected to the plurality of I/O devices 550_1 to 550_q through the I/O switch <NUM>. In one embodiment, there may be an I/O device directly connected to the processor <NUM> without using the I/O switches <NUM> and <NUM>.

The I/O switches <NUM> and <NUM> may extend the PCIe support of the host <NUM>. The processor <NUM> and the I/O switches <NUM> and <NUM> may be connected by a PCIe link. The switches <NUM> and <NUM> and the plurality of I/O devices 540_1 to 540_p and 550_1 to 550_q may be connected by a PCIe link. That is, the plurality of I/O devices 540_1 to 540_p and 550_1 to 550_q may share the PCIe link of the host <NUM>. In this case, a port connected to the host <NUM> in each of the I/O switches <NUM> and <NUM> may be referred to as an upstream port, and a port connected to the plurality of I/O devices 540_1 to 540_p and 550_1 to 550_q may be referred to as a downstream port.

The plurality of I/O devices 540_1 to 540_p and 550_1 to 550_q may be GPUs, NPUs, TPUs, NICs, storage devices, and the like. For example, the tenant may use an AI function through an I/O device that is a GPU. The tenant may use a web search function through an I/O device that is an NIC. The tenant may read, delete, or write data through an I/O device that is a storage device.

The server <NUM> may detect and respond to an attack of the attacking tenant by using the defense device <NUM> described with reference to <FIG> and <FIG>, and may report it to the processor <NUM>. Here, the attack may be a side-channel attack.

In one embodiment, at least one of the I/O switches <NUM> and <NUM> may include the defense device <NUM>. That is, the I/O switch including the defense device <NUM> may detect and respond to an attack, and may report it to the processor <NUM>.

In one embodiment, at least one of the plurality of I/O devices 540_1 to 540_p and 550_1 to 550_q may include the defense device <NUM>. That is, the I/O device including the defense device <NUM> may detect and respond to an attack, and may report it to the processor <NUM>.

The defense device <NUM> may detect and respond to a side-channel attack of the PCIe link to which it belongs. For example, when the defense device <NUM> is in the I/O switch <NUM>, the defense device <NUM> may detect and respond to the side-channel attack through the PCIe link between the processor <NUM> and the I/O switch <NUM>. When the defense device <NUM> is in the I/O device 540_2, the defense device <NUM> may detect and respond to the side-channel attack through the PCIe link between the processor <NUM> and the I/O switch <NUM>.

<FIG> illustrates a schematic block diagram of a server according to an embodiment. In <FIG>, according to an embodiment, the server <NUM> may be the same as the server <NUM> of <FIG>.

The server <NUM> may include a host <NUM>, I/O switches <NUM> and <NUM>, a plurality of I/O devices 640_1 to 640_r and 660_1 to 660_s, and storage devices <NUM> and <NUM>. Here, r and s may be integers greater than <NUM>.

The host <NUM> may include a processor <NUM> that manages and controls overall operations of the server <NUM> and a BMC <NUM> that is a management subsystem that monitors and manages system hardware. The processor <NUM> may perform IB communication, and the BMC <NUM> may perform OOB communication. The processor <NUM> and the BMC <NUM> may independently operate. Accordingly, the BMC <NUM> may operate without affecting the operation of the processor <NUM>, and may operate even when the processor <NUM> is unavailable.

The processor <NUM> may receive a command from a tenant, may process a command by using at least one of the I/O switches <NUM> and <NUM> and at least one of the plurality of I/O devices 640_1 to 640_r and 660_1 to 660_s and the storage devices <NUM> and <NUM>. The processor <NUM> may send the processing result to the tenant.

The processor <NUM> may be connected to the plurality of I/O devices 640_1 to 640_r and 660_1 to 660_s and the storage devices <NUM> and <NUM> through the I/O switches <NUM> and <NUM>. In one embodiment, there may be an I/O device directly connected to the processor <NUM> without using the I/O switches <NUM> and <NUM>.

The I/O switches <NUM> and <NUM> may extend the PCIe support of the host <NUM>. The processor <NUM> and the I/O switches <NUM> and <NUM> may be connected by a PCIe link, and the I/O switches <NUM> and <NUM> and the plurality of I/O devices 640_1 to 640_r and 660_1 to 660_s and the storage devices <NUM> and <NUM> may be connected by a PCIe link. That is, the plurality of I/O devices 640_1 to 640_r and 660_1 to 660_s and the storage devices <NUM> and <NUM> may share the PCIe link of the host <NUM>.

The plurality of I/O devices 640_1 to 640_r and 660_1 to 660_s may be GPUs, NPUs, TPUs, NICs, storage devices, or the like. For example, the tenant may use an AI function through an I/O device that is a GPU. The tenant may use a web search function through an I/O device that is an NIC.

The tenant may use the storage devices <NUM> and <NUM>. For example, the tenant may read or delete data of the storage devices <NUM> and <NUM>, or write data to the storage devices <NUM> and <NUM>.

The storage devices <NUM> and <NUM> may be connected to the BMC <NUM>. That is, the storage devices <NUM> and <NUM> may perform IB communication with the processor <NUM> and the I/O switches <NUM> and <NUM>, and may perform OOB communication with the BMC <NUM>.

The storage devices <NUM> and <NUM> may detect and respond to an attack of an attacking tenant by using the defense device <NUM> described with reference to <FIG> and <FIG>, and may report it to the BMC <NUM>. Here, the attack may be a side-channel attack.

The defense device <NUM> may detect and respond to a side-channel attack of the PCIe link to which it belongs. For example, when the defense device <NUM> is disposed in the storage device <NUM>, the defense device <NUM> may detect and respond to the side-channel attack through the PCIe link between the processor <NUM> and the I/O switch <NUM>. When the defense device <NUM> is in disposed the storage device <NUM>, the defense device <NUM> may detect and respond to the side-channel attack through the PCIe link between the processor <NUM> and the I/O switch <NUM>.

In one embodiment, the defense device <NUM> may notify the BMC <NUM> of attack information by using the command according to the NVMe-MI standard described with reference to <FIG>. The attack information may include the presence of an attack, an attacker, an attack response method, and the like. The BMC <NUM> may send the attack information to the processor <NUM>.

The processor <NUM> may determine whether the attacker determined by the defense device <NUM> is a real attacker. When the processor <NUM> determines that the attacker determined by the defense device <NUM> is a real attacker, the processor <NUM> may operate based on the defense policy. When the processor <NUM> determines that the attacker determined by the defense device <NUM> is not a real attacker, the processor <NUM> may ignore the notification of the defense device <NUM>. At least one of the storage device <NUM> and the storage device <NUM> described with reference to <FIG> may be replaced with a memory device.

<FIG> illustrates a flowchart of an attack detection method according to an embodiment. The storage device may include a defense device that detects an attack. The storage device may be connected to the I/O switch together with other I/O devices. In one embodiment, the I/O switch and the storage device may be connected by a PCIe link, and the I/O switch and the I/O device may be connected by a PCIe link. The defense device may perform an attack detection method of <FIG>. Here, the attack may be a side-channel attack on the I/O device.

The defense device receives a read command from the host (S1110). The host may send the read command to the storage device through the I/O switch according to a request of the tenant. The host may send the read command to the storage device through the PCIe link. The read command may include a random read command, a sequential read command, a constant block read command, and the like.

When the read commands are continuously received for a predetermined period, the defense device calculates the latency of each read command (S1120). The latency may correspond to a processing time of a command.

In one embodiment, the defense device may determine whether a transmission queue of the host is filled with a read command. When the transmission queue of the host is filled with the read command, the latency of each read command may be calculated.

In one embodiment, the latency of the read command may be defined based on four time points. The four time points may include (i) a time point at which the storage device receives the read command, (ii) a time point at which the storage device starts processing the read command, (iii) a time point at which the storage device completes processing of the read command, and (iv) a time point at which the read command processing result is sent to the host (a time point at which the host takes the read command processing result).

In one embodiment, a starting time point of the latency of the read command may be a time point at which the read command is received or a time point at which the read command is started to be processed. In one embodiment, an expiration time point of the latency of the read command may be a time point at which processing of the read command is completed or a time point at which the processing result of the read command is sent to the host.

In one embodiment, the latency of the read command may be defined as a time from a time point of receiving the read command to a time point of sending the processing result of the read command to the host. In one embodiment, the latency of the read command may be defined as a time from a time point at which processing of the read command is started to a time point at which processing of the read command is completed.

In addition, the defense device may exclude latency of a read command in which an internal operation of the storage device is performed during processing. The internal operation may include operations such as garbage collection and wear-leveling.

The defense device may calculate latencies for a plurality of read commands before the internal operation of the storage device occurs, or may calculate latencies for a plurality of read commands after the internal operation is completed. For example, the storage device may sequentially receive the first to tenth read commands, and may perform an internal operation at an arbitrary time point between a processing completion time point of the fourth read command and a processing starting time point of the sixth read command. The defense device may calculate the latencies of the first to fourth read commands, and/or may calculate the latencies of the sixth to tenth read commands.

The defense device calculates uniformity of a plurality of latencies (S1130). The defense device may calculate uniformity of latencies of successive read commands. That is, when a write command or a delete command is included between the read commands, the defense device may not calculate uniformity.

The defense device determines that there is an attack from the tenant when the uniformity is within a predetermined ratio (S1140). For example, the predetermined ratio may be <NUM> %. That is, when a uniform latency is obtained for a predetermined time for successive read commands, the defense device may determine that there is an attack from the tenant. In addition, the defense device may detect the attack and determine the attacking tenant. When the defense device detects the attack, it may respond to the attack.

In one embodiment, when the defense device determines that there is an attack, the defense device may delay the latency of the command of the attacking tenant. The defense device may delay the latency based on a latency range of the attacking tenant. The latency range may include a minimum latency and a maximum latency. The defense device may determine the minimum latency and the maximum latency based on the service policy of the host.

In one embodiment, when the defense device determines that there is an attack, the defense device may adjust the priority of the attacking tenant. The priority may be related to the order in which commands are processed. The defense device may adjust the priority of the attacking tenant based on the latency range of the attacking tenant. For example, the defense device may adjust the priority of the attacking tenant within a range in which the latency of the command of the attacking tenant does not exceed the maximum latency.

<FIG> illustrates a flowchart of an attack detection method according to an embodiment. In <FIG>, after determining that there is an attack from the tenant (S1140), the defense device notifies the host that there is an attack (S1210). For example, the defense device may notify the BMC of the host that there is an attack. In this case, the defense device may notify the host by using the SMBus, the I2C protocol, or the I3C protocol. That is, the defense device may use the SMBus, I2C, or I3C port. The defense devices may use OOB communication to notify the host.

The defense device may notify the host by using the response command of the NVMe-MI standard. In one embodiment, the response command of the NVMe-MI standard may be a response to the NVM sub-system health status poll command. The defense device may notify the host of at least one of an attack detection command, a latency adjustment command, or a priority adjustment command by using the response command of the NVMe-MI standard.

<FIG> illustrates a flowchart of an attack response method according to an embodiment. In <FIG>, when there is an attack, the defense device determines an attacking tenant (S1310). In one embodiment, the defense device may determine that there is an attack when the transmission queue of the host is full of successive commands and is received. In one embodiment, the defense device may determine that there is an attack when the latency according to the successive commands has certain uniformity. The defense device may determine the attacking tenant who is the subject of the attack.

The defense device calculates the latency range of the attacking tenant based on the service policy of the host (S1320). In one embodiment, the service policy of the host may include at least one of a tenant priority, a bandwidth, or a timeout limit. The latency range may include at least one of a minimum latency or a maximum latency. The defense device may calculate at least one of the minimum latency or the maximum latency of the attacking tenant, based on at least one of the tenant priority, the bandwidth, or the timeout limit.

For example, when the read command of the attacking tenant has a highest (first) priority, the defense device may determine the maximum latency of the attacking tenant to be within a latency of a second priority command. When the timeout limit of the attacking tenant is <NUM> seconds, the defense device may determine the maximum latency of the attacking tenant to be <NUM> seconds.

The defense device adjusts the latency for the attacking tenant based on the latency range (S1330). In one embodiment, the defense device may adjust the latency for the command of the attacking tenant within a range that does not exceed the maximum latency. In one embodiment, the defense device may adjust the latency for the command of the attacking tenant by adjusting the priority of the attacking tenant within a range that does not exceed the maximum latency.

<FIG> illustrates a flowchart of an attack response method according to an embodiment. In <FIG>, the defense device determines that the command received from the host is an attack by using IB communication (S1410). The IB communication may use a PCIe link.

The defense device adjusts the latency of the command (S1420). The defense device may adjust the latency according to the service policy of the host for the tenant.

The defense device sends at least one of an attack detection command, a latency adjustment command, or a priority adjustment command to the host by using OOB communication (S1430). The OOB communication may use one of a SMBus, an I2C protocol, or an I3C protocol. The defense device may send at least one of the attack detection command, the latency adjustment command, or the priority adjustment command to the BMC of the host.

The defense device may send at least one of the attack detection command, the latency adjustment command, and the priority adjustment command by using the response command of the NVMe-MI standard. In one embodiment, the response command of the NVMe-MI standard may be a response to the NVM sub-system health status poll command. At least one of the attack detection command, the latency adjustment command, or the priority adjustment command may occupy a reserved area in the response command.

In one embodiment, each component or a combination of two or more components described with reference to <FIG> may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an Application Specific Integrated Circuit (ASIC), or the like.

Claim 1:
A computer implemented method comprising:
receiving, a plurality of read commands generated by a tenant from a host;
calculating, based on the plurality of read commands satisfying a predetermined condition, each latency of the plurality of read commands and obtaining the calculated plurality of latencies;
calculating a uniformity of the plurality of latencies; and
determining, based on the uniformity that is within a predetermined ratio range, that there is an attack from the tenant.