Patent Description:
A fabrication procedure of a display device comprises a bonding process of bonding a circuit structure of a peripheral region of a display panel to an external circuit. However, while the above-described circuit structure of the peripheral region is bonded, an electrode pattern located on a surface of the circuit may be scratched, which further results in a problem such as electrode disconnection.

<CIT> discloses an organic light-emitting diode (OLED) display and a method of manufacturing an OLED display. The display includes a substrate and a thin-film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode formed over the substrate. A gate insulating layer is formed between the active layer and the gate electrode, and an interlayer insulating layer is formed between the gate electrode and the source and drain electrodes. Also, a planarization layer is formed over the source and drain electrodes, and a pixel electrode is formed over the planarization layer. The display also includes capacitor including a first electrode formed on the same layer as the active layer and a second electrode formed of the same material as the pixel electrode. A pixel-defining layer covers opposing ends of the pixel electrode; an emission layer formed over the pixel electrode.

<CIT> provides a light-emitting device in which plural kinds of circuits are formed over the same substrate, and plural kinds of thin film transistors are provided in accordance with characteristics of the plural kinds of circuits. An inverted-coplanar thin film transistor, an oxide semiconductor layer of which overlaps with a source and drain electrode layers, and a channel-etched thin film transistor are used as a thin film transistor for a pixel and a thin film transistor for a driver circuit, respectively. Between the thin film transistor for a pixel and a light-emitting element, a color filter layer is provided so as to overlap with the light-emitting element which is electrically connected to the thin film transistor for a pixel.

It is an object of the present invention to provide a display panel according to claim <NUM>, wherein, one particular objective is to prevent a peripheral circuit of the display panel from being scratched.

The object is achieved by the features of the respective independent claims. Further embodiments are defined in the corresponding dependent claims. Even though the description refers to embodiments or to the invention, it is to be understood that the invention is defined by the claims and embodiments of the invention are those comprising at least all the features of one of the independent claims.

In order to clearly illustrate the the present invention, in the following drawings will be briefly described; the described drawings are only related to some embodiments of the invention and thus are not limitative of the invention that is defined by the claims.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first," "second," etc., which are used in the description and the claims of the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. The terms "comprises," "comprising," "comprises," "comprising," etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases "connect", "connected", etc., are not intended to define a physical connection or mechanical connection, but may comprise an electrical connection, directly or indirectly. "On," "under," "right," "left" and the like are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly.

<FIG> is a structural schematic diagram of a display panel related to the present disclosure. As illustrated in <FIG>, it is a structural schematic diagram of a flexible printed circuit (FPC), a contact electrode <NUM> is provided on a substrate structure <NUM>, and a planarization layer <NUM> is formed on the substrate structure <NUM> on which the contact electrode <NUM> is formed. When the FPC is bonded to an external circuit board, an electrode in the external circuit board may be electrically connected with the contact electrode <NUM>.

<FIG> is a structural schematic diagram of various circuits according to an embodiment of the present disclosure. A display panel <NUM> comprises: an active region A (i.e., a display region) and a peripheral region B, the peripheral region B is provided therein with a peripheral circuit <NUM>, and the peripheral circuit <NUM> may comprise a Chip On Glass (COG) circuit 12A, a FanOut circuit 12B and an FPC 12C. A structure of the FPC 12C may be as illustrated in <FIG>. The COG circuit 12A is configured for bonding to an integrated circuit (IC), the FanOut circuit 12B is configured for connecting with the bonded IC, and the FPC 12C is configured for connecting with an external circuit board.

<FIG> is a structural schematic diagram of the COG circuit 12A according to the present disclosure. A source-drain contact electrode <NUM> is formed on a substrate structure <NUM>, and is easily scratched and disconnected. <FIG> is a structural schematic diagram of the FanOut circuit 12B according to the present disclosure. The source-drain contact electrode <NUM> is formed on the substrate structure <NUM>, and a planarization layer <NUM> and a Pixel definition layer (PDL) <NUM> are formed above the source-drain contact electrode <NUM>. The PDL <NUM> may be made of polyimide (PI), and the planarization layer <NUM> and the pixel definition layer <NUM> are both soft in material, so it is difficult to protect the source-drain contact electrode <NUM> from being scratched.

An embodiment of the present disclosure provides a display panel, comprising: a base substrate; a peripheral circuit located on the base substrate; the peripheral circuit comprising a first circuit, a second circuit and a third circuit, the first circuit, the second circuit and the third circuit respectively comprising a first electrode pattern, a second electrode pattern and a third electrode pattern; and a protection structure, located in at least one circuit of the first circuit, the second circuit and the third circuit, the protection structure comprises at least one of the first electrode pattern, the second electrode pattern and the third electrode pattern, for preventing an electrode pattern located in the at least one circuit from being disconnected.

In at least some embodiments, the first circuit is a Chip On Glass circuit, the second circuit is a flexible printed circuit, and the third circuit is a FanOut circuit.

In at least some embodiments, the protection structure is located in at least two circuits of a Chip On Glass circuit, a flexible printed circuit and a FanOut circuit, or located in each of the above-described circuits.

In at least some embodiments, the first electrode pattern, the second electrode pattern and the third electrode pattern respectively comprise a plurality of source-drain contact electrodes.

In the display panel provided by the embodiments of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern is prevented from being scratched and disconnected, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected while the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

For example, <FIG> is a cross-sectional view of a peripheral circuit of a display panel according to an embodiment of the present disclosure. The display panel <NUM> may comprise: a base substrate <NUM>; a peripheral circuit <NUM> is provided on the base substrate <NUM>, and a source-drain contact electrode pattern <NUM> is provided in the peripheral circuit <NUM>. A protective layer <NUM> is provided on the base substrate <NUM> which is provided with the peripheral circuit <NUM>, and the protective layer <NUM> is configured for preventing the source-drain contact electrode pattern <NUM> from being disconnected.

Hereinafter, the protection structure in each of three circuits comprising a Chip On Glass circuit, a flexible printed circuit and a FanOut circuit will be described in the embodiments of the present disclosure.

For convenience of description, <FIG> and <FIG> only illustrate a Chip On Glass circuit 12A in the peripheral circuit of the display panel, and a structure of the display region of the display panel will not be discussed here.

With reference to <FIG>, in at least some embodiments, a peripheral circuit comprises a Chip On Glass circuit 12A, and a protection structure in the Chip On Glass circuit 12A comprises a dielectric layer <NUM>, an electrode pattern and a protective layer <NUM> sequentially provided on a base substrate <NUM>. The dielectric layer <NUM> comprises at least one first via hole K1, and at least a portion of the electrode pattern is in contact with and overlays a peripheral edge of the at least one first via hole K1. The protective layer <NUM> is in contact with and overlays the at least one portion of the electrode pattern.

In at least some embodiments, an electrode pattern comprises a source-drain contact electrode pattern <NUM>, and the source-drain contact electrode pattern <NUM> comprises a plurality of source-drain contact electrodes <NUM>. <FIG> shows one of the source-drain contact electrodes <NUM>, and the source-drain contact electrode pattern <NUM> may further comprise more than one source-drain contact electrode <NUM>, which will not be specifically illustrated in the embodiments of the present disclosure.

As illustrated in <FIG>, at least a portion of the source-drain contact electrode pattern <NUM> is in contact with and overlays the peripheral edge of the at least one first via hole K1; in other words, the source-drain contact electrode pattern <NUM> surrounds the periphery of the first via hole K1. The first protective layer <NUM> overlays a peripheral edge of each of the plurality of source-drain contact electrodes <NUM>. The protective layer <NUM> may be simultaneously formed with a pixel electrode of the display panel by a single patterning process, without increasing the number of patterning processes. Here, "single patterning process" refers to patterning performed with a same mask, and the "patterning process" refers to, for example, coating a layer of photoresist, exposing and developing with a mask, then etching, and other processes. The protective layer <NUM> is made of a transparent conductive material, which may comprise, for example, Indium tin oxide (ITO). ITO has higher hardness, and is capable of effectively protecting the source-drain contact electrode.

The base substrate <NUM> may be further provided thereon with a buffer layer <NUM>, a gate insulating layer <NUM> is provided on the base substrate <NUM> having the buffer layer <NUM> formed thereon, a gate electrode <NUM> is provided on the base substrate <NUM> having the gate insulating layer <NUM> formed thereon, a dielectric layer <NUM> is provided on the base substrate <NUM> having the gate electrode <NUM> formed thereon, the first via holes K1 in one to one correspondence with the plurality of source-drain contact electrodes <NUM> may be provided on the dielectric layer <NUM>, and each source-drain contact electrode <NUM> may be in contact with the gate electrode <NUM> through one of the first via holes K1 therein. At least a portion of the source-drain contact electrode <NUM> overlays an inner wall of the first via hole K1, and the protective layer <NUM> further extends into the first via hole K1. That is to say, the protective layer <NUM> is in contact with and overlays all surfaces of the source-drain contact electrode <NUM> which protrudes from a surface of the dielectric layer <NUM>.

The Chip On Glass circuit 12A illustrated in <FIG> protects the source-drain contact electrode <NUM> through the protective layer <NUM> which overlays the peripheral edge of the electrode pattern, so that the source-drain contact electrode <NUM> is not easily scratched, which reduces possibility of disconnection. At the same time, the source-drain contact electrode <NUM> has other regions exposed, in addition to edges overlaid by the protection structure, as a result, while the source-drain contact electrode is bonded, a resistance will not be too large, which reduces impact caused by an IR Drop phenomenon.

As illustrated in <FIG>, a Chip On Glass circuit 12A according to another embodiment of the present disclosure comprises a source-drain contact electrode pattern <NUM>, a dielectric layer <NUM> and a gate electrode <NUM>. The dielectric layer <NUM> comprises a plurality of first via holes K1, and the source-drain contact electrode pattern <NUM> comprises a plurality of source-drain contact electrodes <NUM>. The dielectric layer <NUM> may be an inter-layer Dielectric (ILD). Other reference numerals in <FIG> may be referred to those in <FIG>, which will not be repeated here.

The gate electrode <NUM> is provided on a base substrate <NUM>. The dielectric layer <NUM> is provided on the base substrate <NUM> having the gate electrode <NUM> formed thereon. The source-drain contact electrode pattern <NUM> is provided on the base substrate <NUM> having the dielectric layer <NUM> formed thereon, and is in contact with the gate electrode <NUM> through the plurality of first via holes K1; and the plurality of source-drain contact electrodes <NUM> corresponds to the plurality of first via holes K1 one by one.

The source-drain contact electrode <NUM> comprises a plurality of second via holes K2, the second via hole K2 is, for example, located at the bottom of the first via hole K1, the gate electrode <NUM> is exposed at the second via hole K2, and the source-drain contact electrode <NUM> is in contact with the gate electrode <NUM> through the first via hole K1. In this way, the gate electrode <NUM> may be taken as a contact electrode during bonding, and the source-drain contact electrode <NUM> may be configured for protecting the gate electrode <NUM>, to prevent the gate electrode <NUM> from being scratched.

In at least some embodiments, a protection structure in <FIG> further comprises a protective layer <NUM>, which overlays an edge of each of a plurality of source-drain contact electrodes <NUM>. The protective layer <NUM> may be simultaneously formed with a pixel electrode by using same patterning process, and is made of ITO. The protective layer <NUM> may further enhance a scratch-resistant ability of the source-drain contact electrode <NUM>.

As illustrated in <FIG>, in at least some embodiments, a source-drain contact electrode pattern <NUM> is a laminated structure, the laminated structure comprises a first metal layer C1 in contact with a gate electrode <NUM>, a second metal layer C2 in contact with the first metal layer C1, and a third metal layer C3 in contact with the second metal layer C2, and a thickness of the third metal layer C3 is greater than a thickness of the first metal layer C1. In the related art, the thickness of the third metal layer C3 is generally equal to the thickness of the first metal layer C1; and in the embodiment of the present disclosure, the thickness of the top third metal layer C3 is increased, so as to increase a scratch-resistant ability of the source-drain contact electrode pattern <NUM>.

In at least some embodiments, the first metal layer C1 and the third metal layer C3 are titanium metal layers, and the titanium metal layer has a relatively strong scratch-resistant ability; the metal layer is an aluminum metal layer, and the aluminum metal layer has a relatively high electrical conductivity.

For convenience of description, <FIG>, <FIG> only illustrate the flexible printed circuit 12C in the peripheral circuit of the display panel, and a structure of the display region of the display panel will not be discussed here.

For convenience of description, <FIG> and <FIG> only illustrate the Chip On Glass circuit 12A in the peripheral circuit of the display panel, and the related art may be referred to for other structures of the display panel, which will not be repeated here.

In the display panel provided by the above-described embodiments of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern is prevented from being scratched, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected, when the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

As illustrated in <FIG>, the peripheral circuit comprises a flexible printed circuit 12C, the protection structure in the flexible printed circuit 12C comprises a source-drain contact electrode pattern <NUM>, a planarization layer <NUM> and a protective layer <NUM>; and a thickness of the planarization layer <NUM> is greater than a thickness of the source-drain contact electrode pattern <NUM>.

In at least some embodiments, a base substrate <NUM> is provided thereon with a source-drain contact electrode pattern <NUM>, and the source-drain contact electrode pattern <NUM> comprises a plurality of source-drain contact electrodes <NUM>. A planarization layer <NUM> is provided on the base substrate <NUM> having the source-drain contact electrode pattern <NUM> formed thereon, the planarization layer <NUM> comprises a plurality of third via holes K3, and the plurality of third via holes K3 correspond to the plurality of source-drain contact electrodes <NUM> one by one. The source-drain contact electrode <NUM> is provided in the third via hole K3.

A protective layer <NUM> overlays the planarization layer <NUM> and extends to the bottom of the third via hole K3, so as to be in contact with the source-drain contact electrode <NUM>. Since the planarization layer <NUM> is generally soft and easy to be scratched, the planarization layer <NUM> may be covered with the protective layer <NUM>, to enhance a scratch-resistant ability of the planarization layer <NUM>; under protection of the planarization layer <NUM>, the source-drain contact electrode pattern <NUM> is also not easily scratched. The protective layer <NUM> overlays an entire outer surface of the planarization layer <NUM> and acts as an outermost layer. For a material of the protective layer <NUM>, the foregoing embodiments may be referred to.

A buffer layer <NUM> may be further provided on the base substrate <NUM>, a gate insulating layer <NUM> is provided on the base substrate <NUM> having the buffer layer <NUM> formed thereon, and a dielectric layer <NUM> is provided on the base substrate <NUM> having the gate insulating layer <NUM> formed thereon.

As illustrated in <FIG>, in at least some embodiments, a protective layer <NUM> may also be provided only on a side surface of a planarization layer <NUM>, and the side surface is adjacent to a third via hole K3, which may also achieve an effect of enhancing a scratch-resistant ability of the planarization layer <NUM>. Other reference numerals in <FIG> may be referred to those in <FIG>, which will not be repeated here.

As illustrated in <FIG>, in at least some embodiments, a protection structure of a flexible printed circuit 12C comprises a source-drain contact electrode pattern <NUM> and an interlayer insulating layer <NUM>; and the interlayer insulating layer <NUM> is provided with a plurality of fourth via holes K4. The interlayer insulating layer <NUM> may be an inter-layer dielectric.

A source-drain contact electrode pattern <NUM> is provided on a base substrate <NUM> having the interlayer insulating layer <NUM> formed thereon, the source-drain contact electrode pattern <NUM> comprises a plurality of source-drain contact electrodes <NUM>, the plurality of source-drain contact electrodes <NUM> are provided in the plurality of fourth via holes K4, and the plurality of source-drain contact electrodes <NUM> correspond to the plurality of fourth via holes K4 one by one.

A planarization layer <NUM> is provided on the base substrate <NUM> having the source-drain contact electrode pattern <NUM> formed thereon, the planarization layer <NUM> comprises a plurality of third via holes K3, and the plurality of third via holes K3 correspond to the plurality of source-drain contact electrodes <NUM> one by one, so that each source-drain contact electrode <NUM> may be exposed from the third via hole K3. The source-drain contact electrode pattern <NUM> is in contact with and overlays a peripheral edge of the fourth via hole, and the source-drain contact electrode pattern <NUM> extends into a contact region between the planarization layer <NUM> and the interlayer insulating layer <NUM>.

As illustrated in <FIG>, because the source-drain contact electrode pattern <NUM> is buried in the interlayer insulating layer <NUM>, the source-drain contact electrode pattern <NUM> is not easily scratched.

In addition, a protective layer <NUM> as illustrated in <FIG> may also be formed on the planarization layer <NUM> in <FIG>, to further protect the source-drain contact electrode pattern <NUM>.

Other reference numerals in <FIG> may be referred to those in <FIG>, which will not be repeated here.

For convenience of description, <FIG> only show the FanOut circuit 12B in the peripheral circuit of the display panel, and a structure of the display region of the display panel will not be discussed here.

In at least some embodiments, a peripheral circuit comprises a FanOut circuit 12B, and a protection structure in the FanOut circuit 12B comprises a source-drain contact electrode pattern <NUM>, a planarization layer <NUM> and a protective layer <NUM>.

For example, a source-drain contact electrode pattern <NUM> is provided on a base substrate <NUM>, and a planarization layer <NUM> is provided on the base substrate <NUM> having the source-drain contact electrode pattern <NUM> formed thereon. A protective layer <NUM> is provided on the base substrate <NUM> having the planarization layer <NUM> formed thereon, an orthographical projection of the source-drain contact electrode pattern <NUM> on the base substrate <NUM> overlaps with an orthographical projection of the protective layer <NUM> on the base substrate <NUM>, that is, the protective layer <NUM> overlays right above the source-drain contact electrode pattern <NUM> to protect the source-drain contact electrode pattern <NUM>.

In addition, a pixel definition layer may also be formed on the base substrate having the protective layer <NUM> formed thereon, which will not be limited in the embodiment of the present disclosure.

In at least some embodiments, as illustrated in <FIG>, it is a top view of a FanOut circuit 12B in the display panel illustrated in <FIG>. A protective layer <NUM> is composed of a plurality of blocky structures arranged at intervals. A source-drain contact electrode may exist below each blocky structure in <FIG>. The spaced blocky structures may reduce material costs, and will not cause a problem such as disconnection, when the protective layer <NUM> is made of an electrically conductive material.

In at least some embodiments, a display panel comprises a pixel electrode pattern in a display region, and a protective layer <NUM> is provided in a same layer as the pixel electrode pattern. In this way, a protection structure may be provided without increasing the number of patterning processes.

In at least some embodiments, a protective layer <NUM> is made of, for example, indium tin oxide. Indium tin oxide is a harder material and may play a role in scratch resistance.

In the display panel provided by the above-described embodiments of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern is prevented from being scratched and disconnected, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected, when the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

As illustrated in <FIG>, it is a flow chart of a bonding method of a display panel provided by an embodiment of the present disclosure, which may be applied to the display panel illustrated in the above-described respective embodiments, and the bonding method of the display panel comprises:.

The peripheral circuit may comprise a Chip On Glass circuit and a flexible printed circuit.

In the embodiment of the present disclosure, the Chip On Glass circuit and the flexible printed circuit may be separately bonded.

As illustrated in <FIG>, the step may comprise two sub-steps below:.

The bonding may be performed with an anisotropic conductive adhesive film.

In the bonding method of the display panel provided by the above-described embodiment of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern during bonding is prevented from being scratched and disconnected, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected, when the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

Claim 1:
A display panel, comprising:
a base substrate (<NUM>);
a peripheral circuit (<NUM>) located on the base substrate (<NUM>), the peripheral circuit (<NUM>) comprising a first circuit (12A), a second circuit (12C) and a third circuit (12B), and the first circuit (12A), the second circuit (12C) and the third circuit (12B) respectively comprising a first electrode pattern (<NUM>), a second electrode pattern and a third electrode pattern; and
a protection structure, located in at least one circuit of the first circuit (12A), the second circuit (12C) and the third circuit (12B) and configured for preventing an electrode pattern located in the at least one circuit from being disconnected,
wherein the protection structure comprises a first protection structure located in the first circuit (12A), the first protection structure comprises a gate electrode (<NUM>), a dielectric layer (<NUM>) and the first electrode pattern (<NUM>) sequentially provided on the base substrate (<NUM>); the dielectric layer (<NUM>) comprises at least one first via hole (K1), at least a portion of the first electrode pattern (<NUM>) is in contact with and overlays an edge of the at least one first via hole (K1); the first electrode pattern (<NUM>) is in contact with the gate electrode (<NUM>) through the at least one first via hole (K1);
characterized in that
the first electrode pattern (<NUM>) comprises a second via hole (K2) located at a bottom of the first via hole (K1), and
the gate electrode is exposed at the second via hole (K2).