Patent Description:
The present disclosure relates generally to systems and methods for transimpedance amplifier (TIA), and more particularly to detect a base current of a bipolar junction transistor (BJT) in a TIA and to adjust the TIA operation to compensate for changing environmental and/or manufacturing conditions.

A transimpedance amplifier (TIA) may convert an input current source into an output voltage. The current to voltage gain may be based on a feedback resistance. A TIA may provide simple linear signal processing using an operational amplifier and a feedback resistor for dissipating current. The circuit may be able to maintain a constant voltage bias across the input source as the input current changes, which may be beneficial in a network of sensors. Transimpedance amplifiers may be used to process the current output of photodiodes, pressure transducers, accelerometers, and other types of sensors to a voltage formatted as a useable signal output. However, the performance of a TIA may be negatively impacted by <NUM>) a change in environment, e.g. temperature, and <NUM>) silicon wafer manufacturing variations.

Patent <CIT> discloses a transimpedance amplifier with offset cancellation.

Accordingly, what are needed are systems and methods that may detect performance deficiencies due the aforementioned conditions, and provide a recommendation to select either to discard the TIA or to cause adjustments in the operation of the TIA to improve the performance of the TIA.

References will be made to embodiments of the invention, examples of which may be illustrated in the accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in the context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments. Items in the figures are not to scale.

In the following description, for purposes of explanation, specific details are set forth in order to provide an understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these details. Furthermore, one skilled in the art will recognize that embodiments of the present invention, described below, may be implemented in a variety of ways, such as a process, an apparatus, a system, a device, or a method on a tangible computer-readable medium.

Components, or modules, shown in diagrams are illustrative of exemplary embodiments of the invention and are meant to avoid obscuring the invention. It shall also be understood that throughout this discussion that components may be described as separate functional units, which may comprise sub-units, but those skilled in the art will recognize that various components, or portions thereof, may be divided into separate components or may be integrated together, including integrated within a single system or component. It should be noted that functions or operations discussed herein may be implemented as components. Components may be implemented in software, hardware, or a combination thereof.

Furthermore, connections between components or systems within the figures are not intended to be limited to direct connections. Rather, data between these components may be modified, re-formatted, or otherwise changed by intermediary components. Also, additional or fewer connections may be used. It shall also be noted that the terms "coupled," "connected," or "communicatively coupled" shall be understood to include direct connections, indirect connections through one or more intermediary devices, and wireless connections.

Reference in the specification to "one embodiment," "preferred embodiment," "an embodiment," or "embodiments" means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention and may be in more than one embodiment. Also, the appearances of the above-noted phrases in various places in the specification are not necessarily all referring to the same embodiment or embodiments.

The use of certain terms in various places in the specification is for illustration and should not be construed as limiting. A service, function, or resource is not limited to a single service, function, or resource; usage of these terms may refer to a grouping of related services, functions, or resources, which may be distributed or aggregated.

The terms "include," "including," "comprise," and "comprising" shall be understood to be open terms and any lists the follow are examples and not meant to be limited to the listed items. Any headings used herein are for organizational purposes only and shall not be used to limit the scope of the description or the claims. Each reference mentioned in this patent document is incorporate by reference herein in its entirety.

Furthermore, one skilled in the art shall recognize that: (<NUM>) certain steps may optionally be performed; (<NUM>) steps may not be limited to the specific order set forth herein; (<NUM>) certain steps may be performed in different orders; and (<NUM>) certain steps may be done concurrently.

A transimpedance amplifier (TIA) may convert current to voltage. TIAs may be used to process the current output of photodiodes, pressure transducers, accelerometers, and other types of sensors to a voltage formatted as a useable signal output. TIAs provide linear signal processing using an operational amplifier and a feedback resistor for dissipating current. <FIG> shows a basic transimpedance amplifier circuit <NUM>.

In <FIG>, Iin represents the current output from a sensor and the gain (sensitivity) is resistance, R. Using Kirchhoff's Current Law (KCL), the sum of all currents flowing into a node is zero. If one assumes that the current flowing into the op amp is ib, KCL at node N1 provides an equation:<MAT> as noted in <FIG>. The equation provides a voltage output, Vout = R(ib - Iin) + Vn1.

Bipolar Junction Transistor (BJT) is a semiconductor device constructed with three doped Semiconductor Regions (Base, Collector and Emitter) separated by two p-n Junctions. The p-n junction between the Base and the Emitter has a Barrier Voltage (Vo) of about <NUM> V to <NUM> V. <FIG> illustrates BJT <NUM> of a npn BJT. As illustrated in <FIG>, Vo = VBE. A companion BJT has a pnp structure.

Per <FIG>, the current flowing out of BJT <NUM>, emitter current ie, is equal to the currents flowing into BJT <NUM>, collector current ic and base current ib; thus the equation: ie = ic + ib. The current gain, or beta, of BJT <NUM> is equal to the ratio: ic divided by ib (ic/ib). In some embodiments, with a load resistance connected in series with the collector, the current gain (beta) of the common emitter transistor configuration may be quite large. Small changes in current flowing in the base of BJT <NUM> control the current in the emitter-collector circuit. In some embodiments, beta may have a value between <NUM> and <NUM> for general purpose transistors.

The value of beta may vary depending on changes in environment, e.g. <NUM>) temperature, and <NUM>) silicon wafer manufacturing variations. <FIG> illustrates a Gaussian distribution of the value of beta <NUM>, according to embodiments of the present disclosure. One sample of the Gaussian distribution is Beta1, which is associated with transistor BJT1. Beta1 represents a nominal value of beta as it has a maximum number of samples for a particular value of beta. Another sample of the Gaussian distribution is associated with transistor BJT2, which has a beta with a value of Beta2. Beta2 has a lower number of samples of a particular value of beta as compared with Beta1 and represents a reduced value of beta, or a "low beta". In some embodiments, since ic is designed to be a constant current, with the lower value of beta (Beta2), the transistor BJT2 may generate a higher value of ib as compared with transistor BJT1 since ic is essentially constant. A decision may be made to discard transistor BJT2 or adjust the TIA to compensate for the higher value of ib.

In another embodiment, a sample of the Gaussian distribution of <FIG> is Beta3, which is associated with transistor BJT3. Beta3 has a higher number of samples for a particular value of beta as compared with Beta1, and represents an increased value of beta, or a "high beta". Since ic is generally designed to be a constant current, with the higher value of Beta3, transistor BJT3 may generate a lower value of ib as compared with transistor BJT1, which has a beta of Beta1.

<FIG> depicts TIA Base Current Detection and Compensation Functional Blocks <NUM>, hereinafter, "Functional Blocks <NUM>", according to embodiments of the present disclosure. In operation, Vin <NUM> is coupled to TIA <NUM> that amplifies the input current and may generate the voltage, Vout <NUM>. Periodically, there may be a need to update the input current to adapt for changing environmental conditions. In this case, TIA <NUM> measures the status of its performance based on internally generated Intermediate Signal <NUM> having an associated voltage, VF. Voltage VF may indicate deficiencies requiring action. Intermediate Signal <NUM> (voltage VF) and a Reference <NUM> (voltage VR) are voltages, and are coupled to Comparator <NUM> via two corresponding low pass filters, LPF <NUM> and LPF <NUM> via Signal <NUM> and Signal <NUM>. Voltage VR is associated with Reference <NUM>. The output of Comparator <NUM>, COMP_OUT <NUM>, may be coupled to Digital State Machine <NUM>. Digital State Machine <NUM>, when triggered, increments the digital state from a current state to a next state. An output of Digital State Machine <NUM>, Digital State <NUM>, may reflect the state of Digital State Machine <NUM>. In one embodiment, Digital State Machine <NUM> may have <NUM> states.

If the voltage VF for Intermediate Signal <NUM> is greater than the voltage VR of Reference <NUM>, the output of Comparator <NUM> is a "<NUM>", which triggers an increment from a current state to a next state in Digital State Machine <NUM>. In one embodiment, the state may change from State2 to State3. Digital State Machine <NUM> is coupled via Digital State <NUM> to Current Digital-Analog-Converter (Current DAC) <NUM>. Current DAC <NUM> then converts the digital state, i.e., Digital State <NUM>, to a current indicated by Current <NUM>, which is the current output from Current DAC <NUM> (The current of Currrent DAC <NUM> is referred to as idac). In other words, Current DAC <NUM> is a state machine controlled low noise current DAC. In some embodiments, the change for State2 to State3 causes an increased value of current for Current <NUM>. Current <NUM> is in turn coupled to TIA <NUM>. TIA <NUM> then responds to Current <NUM> and implements another cycle of comparing voltage VF to voltage VR.

If the voltage VF for Intermediate Signal <NUM> is less than the voltage VR of Reference <NUM>, the output of Comparator <NUM> maintains a value of "<NUM>". In this case, the state of Digital State Machine <NUM> remains the same, and there is no change in Current <NUM>.

Functional Blocks <NUM> may be utilized in a calibration method in order to detect performance deficiencies and provide a recommendation to select either to discard the TIA or to cause adjustments in the operation of the TIA to improve the performance. Performance may be based on the relationship between a load in the TIA and the voltage VF, as discussed relative to <FIG>. Key elements in the calibration method are the relationships between current idac, and voltages VF and VR. In a beginning state, idac = <NUM>, and VF > VR, causing an increment in the digital code of the state machine (Digital State Machine <NUM>), which causes an increase in idac. Based on the increased idac, the process may repeat. As idac increases, VF decreases. At some point VF < VR, causing the state machine stop incrementing the digital code. At this point, TIA <NUM> may be considered calibrated and the last digital code is recorded.

With the completion of calibration and the digital code of the state machine recorded, the following decisions may be implemented: (<NUM>) compare the recoded digital code to a predetermined code to decide whether to discard the TIA. The predetermined code may be based on design, simulation and expectation parameters. Or, <NUM>) based on the comparison of the recoded digital code to a predetermined code, proceed with operation of the TIA. In this case, the adjusted digital code has compensated for deficiencies in the operation.

An increase in VF may cause degradation in the performance of components of TIA <NUM>. Specifically, the condition of VF being "close" to the supply voltage Vcc may cause TIA <NUM> to be in a non-operating condition. <FIG> illustrates via embodiment <NUM> the conditions for operation of TIA <NUM> based on the relationship between Intermediate Signal <NUM> (voltage VF) and the impedance of a Load <NUM>, ImpL, of TIA <NUM>. The value of the power supply voltage, Vcc and the value of VR are noted on <FIG>. As illustrated, at lower values of VF, ImpL is relatively constant, with minimal declines in the value of the impedance. At a higher value of VF, for example, VF1, ImpL begins to rapidly decrease, significantly impacting the components and performance of TIA <NUM>. In some embodiments, VF1 may be <NUM>% of Vcc, a power supply voltage for TIA <NUM>.

When VF increases to a value of VF2, TIA <NUM> may no longer be operational. The voltage VF2 may be a pre-determined value based on ImpL. This pre-determined value may be based on the design and components of TIA <NUM>. In some embodiments, this pre-determined value of VF2 may be <NUM>% of ImpL. That is, TIA <NUM> may no longer be operational when ImpL has declined in value by <NUM>%, as illustrated in <FIG>.

Alternatively, for pnp bipolar junction transistors, the condition of the value of VF being "low", compared with Vcc may cause the TIA <NUM> to be in a non-operating condition. In embodiment <NUM>, VF5 illustrates a "low" condition. This condition may occur if VF5 is less than a pre-determined value of Vcc. In some embodiments, pre-determined value of VF5 may be <NUM>%. That is, TIA <NUM> may be in a non-operating condition when VF5 is <NUM>% of Vcc.

In summary, an increase in VF (Intermediate Signal Voltage) relative to the Load (ImpL) associated with a TIA, may cause a decrease in component performance of a TIA. As illustrated in embodiment <NUM>, ImpL is relatively constant at lower VF voltages. At voltage VF1, the ImpL begins to rapidly decrease; at voltage VF2,TIA becomes non-operational; at voltage VF3, TIA is operational but with degraded performance; at voltage VF4, TIA is operational with acceptable performance; VR = Reference Voltage; Vcc = power supply voltage. Voltage VF4 refers to a range of voltages below VF1. Voltage VF3 refers to a range of voltages between VF1 and VF2. In sample embodiment <NUM>, VF1 = <NUM> volts; VF2 = <NUM> volts, VF3 = <NUM> volts, VF4 = <NUM> volts; VR = <NUM> volts, Vcc = <NUM> volts. Values are approximate.

As illustrated in embodiment <NUM>, a TIA with an intermediate signal voltage of VF3 is operational but with degraded performance. With a calibration method, the TIA can compensate for deficiencies in component performance and reduce the intermediate signal voltage to VF4 to obtain acceptable performance. In some embodiments with a BJT, the component deficiency may be a high beta.

<FIG> depicts TIA Base Current Detection and Compensation Circuits <NUM> (hereinafter "Circuits <NUM>") according to embodiments of the present disclosure. <FIG> includes a BJT implementation of TIA <NUM> of Functional Blocks <NUM>. Circuits <NUM> implements detection and compensation of the TIA base current utilizing the properties of a BJT. The voltages, VBE1 and VBE2, are determined primarily by the P-N junction of silicon, which is approximately <NUM> volts (barrier voltage).

Circuit <NUM> comprises Current DAC <NUM>, TIA <NUM>, Comparator <NUM>, and Digital State Machine <NUM>. TIA <NUM> comprises several components including two BJTs as illustrated in <FIG>. One BJT is Q<NUM> <NUM>, which is coupled to a feedback resistor, RF <NUM>. Associated with these components are: ib1 - base current of Q<NUM> <NUM>; ibf - current through resistor RF; idac - current from Current DAC <NUM>, where ib1 = ibf + (idac).

An output of Current DAC <NUM> may be coupled to the base of Q<NUM> <NUM> and to one end of RF <NUM>. The collector of Q<NUM> <NUM> may be coupled to Load <NUM> and Buffer <NUM>. An output of Buffer <NUM> may be coupled to the other end of RF <NUM>, hence providing a feedback resistor for Q<NUM> <NUM>. An output of Buffer <NUM> is the Intermediate Signal <NUM> having an associated voltage, VF, where VF = VBE1 + (ibf x RF). Intermediate Signal <NUM> is coupled via R<NUM> <NUM> to the base of Q2 <NUM>. The components Load <NUM>, variable resistor, R<NUM> <NUM>, and Buffer <NUM> collectively operate to generate Vout, an output of the transimpedance amplifier.

Voltage VF and Voltage VR are separately coupled to Comparator <NUM>, which in turn is coupled via COMP_OUT <NUM> to Digital State Machine <NUM>, which in turn is coupled to Current DAC <NUM> via Digital State <NUM>. Current DAC <NUM> generates idac, which is coupled to the base of Q1 <NUM>. The operation of Comparator <NUM>, Digital State Machine <NUM>, and Current DAC <NUM> are equivalent to the previously described operation of Comparator <NUM>, Digital State Machine <NUM>, and Current DAC <NUM> as previous described for <FIG>. The inputs to Comparator <NUM> are filtered by LPF <NUM> and LPF <NUM>.

A goal for the operation of Circuits <NUM> is the detection of performance deficiencies due to <NUM>) a change in environment, e.g. temperature, and <NUM>) silicon wafer manufacturing variations, and provide a recommendation to select either to discard the TIA or to cause adjustments in the operation of the TIA to achieve an acceptable performance. As previously discussed relative to <FIG>, acceptable performance may be defined relative to the relationship between a load of a TIA and the Intermediate Signal Voltage VF. A consideration for Circuits <NUM> is the neutralization of a "high" ibf current due to a "high" ib1 current caused due to low beta. The operation may be described as follows:.

<FIG> graphically illustrates a flowchart <NUM> of a method of calibration to detect and compensate for a high base current in a bipolar junction transistor (BJT) according to embodiments of the current disclosure. The method may be referred to as a calibration process and may be based on utilizing Circuits <NUM>. The method comprises the steps of:.

In summary, A system for detecting and adjusting the operation of a TIA comprises (<NUM>) a current digital to analog converter (DAC) operable to generate an idac current based on a first state level of a digital state machine; (<NUM>) a transimpedance amplifier (TIA) operable to receive the current and to generate an intermediate signal voltage (VF) and generate an output voltage (Vout); (<NUM>) a comparator operable to receive the intermediate signal voltage (VF) and a reference voltage and generate an output; and (<NUM>) the digital state machine operable to generate second state level based on the output of the comparator. The current DAC changes its idac generated current if there is a difference between the first state level and the second state level.

If the intermediate signal voltage is greater than the reference voltage, the output of the comparator is a "<NUM>", causing the digital state machine to increment the first state level to a higher level state for the second state, in turn causing the current DAC to increase the idac current coupled to the TIA. If the intermediate signal voltage is less than the reference voltage, the output of the comparator is a "<NUM>", causing no change in the state level of the digital state machine, and causing no change to idac current coupled to the TIA. The reference voltage is based on a barrier voltage of a bipolar junction transistor (BJT). The barrier voltage varies between <NUM> voltages and <NUM> voltages.

The TIA comprises a first bipolar junction transistor (BJT), and the intermediate signal voltage (VF) is based in part on the value of beta of the first BJT. A first base current (ib1) for the first BJT is equal to the current from the current DAC (idac) plus a feedback current (ibf) received via a feedback resistor, wherein the intermediate signal voltage (VF) equals the barrier voltage plus the feedback current (ibf) times the resistance of the feedback resistor. When VF increases to a pre-determine value, the impedance of the load of the TIA decreases, causing the TIA to no longer operate. If the digital state machine increments to the higher level state, the idac current increases, and the TIA repeats the generation of another value of the intermediate signal voltage (VF) utilizing the increased idac current. If the digital state machine does not increment to a higher level state, a current state is recorded and compared with a pre-determined state, and wherein, based on the comparison, a decision is made to <NUM>) discard the TIA, or <NUM>) continue operation with last adjusted idac current. An operation status of the TIA is based on a relationship between intermediate signal voltage (VF) and an impedance of a load of the TIA, wherein an increase in intermediate signal voltage (VF) causes degradation in the operation status of the TIA.

A variation of a beta of the first BJT causes an inverse variation of the intermediate signal voltage that in turn causes a change in the first base current (ib1) for the first BJT, wherein the change in the first base current (ib1) compensates for the variation in the beta. The reference voltage is based on the barrier voltage of a second BJT in the TIA. The current to voltage gain may be based on a feedback resistance. A goal for the operation of the system is the neutralization of a high ibf current due to a large ib1 current.

A method for detecting and adjusting the operation of a TIA comprises generating a DAC current by a current DAC and coupling the DAC current to a transimpedance amplifier (TIA); generating, by the TIA, an intermediate signal voltage (VE) based on the DAC current, a base current and a value of beta of a bipolar junction transistor of the TIA; comparing, by a comparator, the intermediate signal voltage (VF) and a PN junction bias voltage.

Claim 1:
A system for calibrating a transimpedance amplifier, comprising:
a current digital to analog converter, DAC (<NUM>), operable to generate an idac current,
wherein the current DAC is a DAC controlled by a digital state machine, and a value of the idac current is determined based on a first state level of the digital state machine
a transimpedance amplifier, TIA, operable to receive the idac current and to generate an intermediate signal voltage (VF) and generate an output voltage (Vout), wherein the TIA comprises:
a first bipolar transistor, BJT (<NUM>), having its base connected to receive the idac current from the current DAC,
a load (<NUM>) coupled between a supply voltage and a collector of the first bipolar transistor,
a buffer coupled between the collector of the first bipolar transistor and an intermediate node (<NUM>),
an output of the buffer being an intermediate signal received at the intermediate node, the intermediate signal having the intermediate signal voltage (VF),
a feedback resistor (<NUM>) coupled between the intermediate node and the base of the first bipolar transistor,
a second bipolar transistor, BJT (<NUM>),
a resistor connected between the intermediate signal node and a base of the second bipolar transistor,
a second feedback resistor (<NUM>) connected between the base and the collector of the second bipolar transistor, and
a second load connected to the collector of the second bipolar transistor;
a comparator operable to receive the intermediate signal voltage (VF) and a reference voltage and generate an output indicating whether the intermediate signal voltage (VF) is less than the reference voltage , the reference voltage being a voltage of a node between the resistor and the base of the second bipolar transistor; and
the digital state machine operable to generate a second state level based on the output of the comparator;
wherein, the current DAC changes its generated idac current if there is a difference between the first state level and the second state level during a calibration process of the TIA.