Patent Description:
In a parallel multiple-port charging system, multiple charging ports may be connected in parallel to a power source or power supply unit for providing a shared power pool that can be distributed among individual charging ports. This allows multiple devices - e.g., in case of a Universal Serial Bus (USB) charging system, smartphones, tablets, smartwatches, or any other USB-powered devices - to be charged simultaneously. Thus, each port can deliver its maximum rated power output independently, ensuring efficient and fast charging for each connected device.

Each port of a parallel multiple-port charging system typically operates independently and is typically controlled by a dedicated port controller. The port controllers are typically controlled by a single processor that is programmed, through software, to control the activities for all ports depending on the capabilities of each respective port.

<CIT> discloses systems and methods for USB power delivery.

A typical prior art parallel multiple-port charging system uses one processor to control all activities for all charging ports, i.e., by controlling the port controllers of each port. Such use of a single processor to control all ports has a number of disadvantages. Firstly, the processor may be required to operate at a relatively high speed to ensure timely responses to each port, in particular when the processor handles all ports in serial sequence, which can result in a delay in port response time. Secondly, the software program running on the processor typically includes specific function code for each port, requiring a relatively large size of code memory due to software code being repeated for each port. Thirdly, a failure from one port may cause system failure or affect normal operation of the other ports. Fourthly, when extending the number of ports in the system, more software code needs to be added to for program, requiring even larger memory size and software development (human) resources.

The present disclosure aims to overcome the above identified drawbacks of known parallel multi-port charging systems. Hereto, a parallel multi-port system according to the present disclosure includes multiple processors working in parallel and independently, with each processor controlling a port controller of a port. Software code common to different port controllers and/or ports may be shared by the multiple processors, leaving only port specific, preferably non-sharable, configuration code in addition to the common software code.

The parallel multi-port system according to the present disclosure may advantageously be used for controlling charging ports in parallel multi-port charging systems. Alternatively, or additionally, the parallel multi-port system according to the present disclosure may be used for controlling data ports.

With the multiple processors working in parallel and independently, performance requirements of each processor may be lower compared to the one processor in the known system. Moreover, by using multiple processors, system robustness may be increased by removing the single point of failure in the single processor. By using common program code for multiple processors (and thus for multiple port controllers and/or ports), the code memory size may be reduced by removing repeated software code, complexity of software development may be decreased, chip size may be reduced (e.g., due to smaller firmware size reducing the memory size), and costs of the parallel multi-port system may be reduced.

According to an aspect of the present disclosure, a parallel multiple-port system is presented. The parallel multiple port system includes a plurality of ports. The parallel multiple port system includes a plurality of processors. The parallel multiple port system includes a memory storing software code which, when executed by the plurality of processors causes the processors to control the plurality of ports. A first processor of the plurality of processors is configured to control a first port of the plurality of ports. A second processor of the plurality of processors different from the first processor is configured to control a second port of the plurality of ports different from the first port. The software code includes a common software code portion relevant to the plurality of ports and for execution by the plurality of processors. The software code further includes a port specific code portion including first configuration data for the first port and for execution by the first processor. The port specific code portion further includes second configuration data for the second port and for execution by the second processor.

The parallel multiple-port system further includes a plurality of port controllers. Each port controller is configured to control one of the plurality of ports. The plurality of processors is configured to control the ports via the plurality of port controllers.

In an embodiment, the first processor may be configured to control a first subset of the plurality of ports. The second processor may be configured to control a second subset of the plurality of ports.

In an embodiment, the common software code portion may include boot codes. The boot codes may link each processor to a memory address in the port specific code portion. The memory address may point to configuration data of one port.

In an embodiment, the common software code portion may include function codes. The function codes may include a generic program of the parallel multi-port system without processor or port identifications.

In an embodiment, the ports may be charging ports.

In an embodiment, the parallel multiple-port system may further include a plurality of power loops. Each power loop may be configured to provide power to one of the charging ports.

In an embodiment, the ports may be USB ports.

According to an aspect of the present disclosure, a computer program is presented. The computer program may include instruction which, when the program is executed by a plurality of processors of a parallel multi-port system, cause the plurality of processors to control a plurality of ports, cause a first processor of the plurality of processors to control a first port, and cause a second processor of the plurality of processors different from the first processor to control a second port different from the first port. The program may include a common software code portion relevant to the plurality of ports and for execution by the plurality of processors. The program may further include a port specific code portion including first configuration data for the first port and for execution by the first processor, the port specific code portion further including second configuration data for the second port and for execution by the second processor.

In an embodiment, the common software code portion of the computer program may include boot codes. The boot codes may link each processor to a memory address in the port specific code portion. The memory address may link to configuration data of one port.

Embodiments of the present disclosure will now be described with reference to the accompanying schematic drawings in which corresponding reference symbol indicate corresponding parts, in which:.

The figures are intended for illustrative purposes only, and do not serve as restriction of the scope of the protection as laid down by the claims.

The described embodiments are to be considered in all respects only as illustrative. The scope of the present disclosure is, therefore, indicated by the appended claims. All changes which come within the meaning and range of the claims are to be embraced within their scope.

Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single example of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same example.

Furthermore, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

<FIG> shows a conventional (prior art) structure of a parallel multiple-port charging system <NUM>. Charging ports <NUM>-<NUM> are shown, each controlled by a port controller <NUM>-<NUM> and including a power loop <NUM>-<NUM>. A single processor <NUM> controls all charging ports <NUM>-<NUM> via the port controllers <NUM>-<NUM>. The processor operates based on software code <NUM>. The dots indicate that there may be any number of port controllers/power loops/charging ports.

The one processor <NUM> of the conventional system <NUM> typically controls the activities of the multiple ports in a serial sequence. In a serial sequence, tasks are processed, or instructions are executed one at a time, and each task or instruction must be completed before the next one can begin (i.e., sequentially). The processor <NUM> typically operates at a relatively high speed (i.e., high compared to each processor in the parallel multi-port charging system according to the present disclosure) to ensure timely reaction on ports, which may require a higher-end and more costly processor.

The software code <NUM> typically includes specific function codes for each of the ports <NUM>-<NUM> and/or port controllers <NUM>-<NUM>, resulting in repeated code in the software code <NUM>. The software code <NUM> typically includes all possible combinational scenarios for all ports <NUM>-<NUM> and/or port controllers <NUM>-<NUM>. As a result, when the number of ports increases, the complexity of the software code <NUM> may increase as well. Even when adding ports with functions similar or identical to existing ports, it may be required to add new ports' function codes to the software code <NUM> and modify existing software code in the software code <NUM>.

With all ports <NUM>-<NUM> and port controllers <NUM>-<NUM> being controlled by a single processor <NUM>, a failure in one port or port controller may result in the whole system <NUM> to fail and thus affect the other ports.

An example software code <NUM> for N ports <NUM>-<NUM> may be structured as follows:.

<FIG> shows a structure of a parallel multi-port system <NUM> of an example embodiment of the present disclosure. Ports <NUM>-<NUM> are shown, each controlled by a port controller <NUM>-<NUM>. In case the ports are charging ports, a power loop <NUM>-<NUM> may be included per port. A power loop may be part of a port controller. Multiple processors <NUM>-<NUM> control the ports <NUM>-<NUM> via the port controllers <NUM>-<NUM>, in this example one processor per port and port controller. The processors operate based on software code <NUM>. Software code <NUM> differs from software code <NUM> in that it has been adapted to include a common software code portion common to all processors <NUM>-<NUM> (and thus common to all ports <NUM>-<NUM> and port controllers <NUM>-<NUM>) and a port specific code portion including port specific software code. The dots indicate that there may be any number of processors/port controllers/power loops/ ports.

In the parallel multi-port system <NUM>, each processor <NUM>-<NUM> may control the respective ports' activities in parallel and may operate independently. This allows the processors <NUM>-<NUM> to operate at a lower speed compared to the processor <NUM> of the conventional system <NUM>, thereby lowering processor requirements.

The processors <NUM>-<NUM> may execute the same software code <NUM> including unified (i.e., common) function codes and port specific configuration data, allowing much smaller size of code memory and saving in chip area even with the additional processors.

In the example of <FIG>, each processor <NUM>-<NUM> controls a single port <NUM>-<NUM> and/or port controller <NUM>-<NUM>. As a result, the software code <NUM> need not include complex scenarios for controlling multiple ports and the software code may remain relatively simple when the number of ports increases. When adding a port with existing functions to the system <NUM>, it may not be necessary to modify the unified function code in the common software code portion. Adding port specific configuration data for the additional port to the port specific code portion of the software code <NUM> may suffice when adding a port to the system <NUM>.

The processors <NUM>-<NUM> may operate independently to each other. A failure in one port <NUM>-<NUM> or a failure in one port controller <NUM>-<NUM> may cause the respective processor <NUM>-<NUM> to reboot or switch off without affecting the other ports and port controllers controlled by the other processors. As a result, the whole system <NUM> is much more robust compared to the conventional system <NUM>.

<FIG> shows a structure of a parallel multi-port system <NUM> of another example embodiment of the present disclosure. Ports <NUM>-<NUM> are shown, each controlled by a port controller <NUM>-<NUM>. In case the ports are charging ports, a power loop <NUM>-<NUM> may be included per port. A power loop may be part of a port controller. Multiple processors <NUM>-<NUM> control the ports <NUM>-<NUM> via the port controllers <NUM>-<NUM>, in this example a first processor <NUM> for ports <NUM>-<NUM> and port controllers <NUM>-<NUM> and a second processor <NUM> for ports <NUM>-<NUM> and port controllers <NUM>-<NUM>. The processors operate based on software code <NUM>. Similar to software code <NUM>, software code <NUM> differs from software code <NUM> in that it has been adapted to include a common software code portion common to all processors <NUM>-<NUM> (and thus common to all ports <NUM>-<NUM> and port controllers <NUM>-<NUM>) and a port specific code portion including port specific software code. The dots indicate that there may be any number of processors/port controllers/power loops/ ports.

In <FIG>, each processor <NUM>-<NUM> controls a subsection of the ports <NUM>-<NUM> and/or port controller <NUM>-<NUM>. When adding a port with existing functions to the system <NUM>, it may not be necessary to modify the unified function code in the common software code portion. Adding port specific configuration data for the additional port to the port specific code portion of the software code <NUM> may suffice when adding a port to the system <NUM>.

The processors <NUM>-<NUM> may operate independently to each other. A failure in one port <NUM>-<NUM> or a failure in one port controller <NUM>-<NUM> may cause the respective processor <NUM>-<NUM> to reboot or switch off without affecting the ports and port controllers controlled by the other processors. As a result, the whole system <NUM> is much more robust compared to the conventional system <NUM>.

Preferably, the processors <NUM>-<NUM>, <NUM>-<NUM> make use of a single software code, such as software code <NUM> in the example of <FIG> or software code <NUM> in the example of <FIG>. Alternatively, multiple software codes may be used for multiple processors, such as shown in <FIG>, where a part of a structure of a parallel multiple-port system <NUM> is shown, showing to processors <NUM>, <NUM> and two software codes <NUM>, <NUM>. The software code <NUM> includes, e.g., a common software code portion for the first processor <NUM> and a port and/or port controller specific software code portion for one or more ports controlled by the first processor <NUM>. The software code <NUM> includes, e.g., a common software code portion for the second processor <NUM> and a port and/or port controller specific software code portion for one or more ports controlled by the second processor <NUM>.

The software code <NUM>, <NUM>, <NUM>, <NUM> may be stored in a non-volatile memory (NVM). NVM is commonly used in microcontrollers, embedded systems, and other devices where the program code needs to be stored permanently. It allows the system to retain the code even after power cycles or resets, ensuring that the program instructions are not lost. The software code <NUM>, <NUM>, <NUM>, <NUM> may be part of a firmware of the parallel multiple-port system <NUM>, <NUM>, <NUM>.

<FIG> shows a more detailed example of a structure of a software code <NUM>, which may be used for the software codes <NUM>, <NUM>, <NUM>, <NUM>. The software code <NUM> may include a common software code portion <NUM> and a port and/or port controller specific software code portion <NUM>.

The common software code portion <NUM> may include boot codes <NUM> and/or function codes <NUM> that are executable by multiple processors, e.g., processors <NUM>-<NUM> in the example of <FIG> or processors <NUM>-<NUM> in the example of <FIG>.

The port/port controller specific code portion <NUM> may include port specific and/or port controller specific configuration data <NUM>-<NUM>. In the example of <FIG>, the port/port controller specific configuration data <NUM> defines, e.g., configuration data related to port <NUM>, the port/port controller specific configuration data <NUM> defines, e.g., configuration data related to port <NUM>, and the port/port controller specific configuration data <NUM> defines, e.g., configuration data related to port <NUM>. In the example of <FIG>, the port/port controller specific configuration data <NUM> defines, e.g., configuration data related to port <NUM>, the port/port controller specific configuration data <NUM> defines, e.g., configuration data related to port <NUM>, the port/port controller specific configuration data <NUM> defines, e.g., configuration data related to port <NUM>, and a further port/port controller specific configuration data (not shown in <FIG>) defines, e.g., configuration data related to port <NUM>.

The boot codes <NUM> may include code to identify the configuration area in code memory according to processor identification. In an example of a parallel multi-port system with four ports being controlled by four processors, the boot codes <NUM> (in pseudo code) may be structured as follows:
<IMG>.

Preferably, the function codes <NUM> include a main, generic program without processor or port identifications. In the example with four ports being controlled by four processors, the function codes <NUM> (in pseudo code) may be structured as follows:
<IMG>.

In the example with four ports being controlled by four processors, the port/port controller specific code portion <NUM> may then be structured as follows:.

In the above example, adding a processor and additional port/port controller to the system <NUM> is as simple as adding a configuration start address to the Boot codes <NUM> and adding port specific configuration data to the port/port controller specific code portion <NUM> at the configured configuration start address. Unused configuration start addresses may already be present in the Boot codes <NUM>, enabling that only the configuration data needs to be added to the controller specific code portion <NUM> when adding a processor/port controller/port to the system <NUM>.

The parallel multi-port system <NUM>, <NUM>, <NUM> of the present disclosure may advantageously be used in multiple-port USB adapters including different types of ports, such as type-C USB ports and type-A USB ports. The present disclosure is not limited to USB adapters or these specific USB type ports and may be used in any electronic device with multiple ports, such as chargers, power banks, docking stations, and etcetera.

<FIG> shows an example embodiment of a computing system <NUM> for implementing certain aspects of the present technology. In various examples, the computing system <NUM> can be any computing device making up any part of the parallel multi-processor system <NUM>, <NUM>, <NUM> described herein.

In some implementations, a computing system <NUM> can implement the methods described herein.

The computing system <NUM> can include any component of a computing system described herein which the components of the system are in communication with each other using connection <NUM>. The connection <NUM> can be a physical connection via a bus, or a direct connection into processor <NUM>, such as in a chipset architecture. The connection <NUM> can also be a virtual connection, networked connection, or logical connection.

The example system <NUM> includes at least one processing unit (CPU or processor) <NUM> and a connection <NUM> that couples various system components including system memory <NUM>, such as read-only memory (ROM) <NUM> and random-access memory (RAM) <NUM> to processor <NUM>. The computing system <NUM> can include a cache of high-speed memory <NUM> connected directly with, in close proximity to, or integrated as part of the processor <NUM>.

The processor <NUM> can include any general-purpose processor and a hardware service or software service, such as services <NUM>, <NUM>, and <NUM> stored in storage device <NUM>, configured to control the processor <NUM> as well as a special-purpose processor where software instructions are incorporated into the actual processor design. The processor <NUM> may essentially be a completely self-contained computing system, containing multiple cores or processors, a bus, memory controller, cache, etc. A multi-core processor may be symmetric or asymmetric.

To enable user interaction, the computing system <NUM> may include an input device <NUM>, which can represent any number of input mechanisms, such as a microphone for speech, a touch-sensitive screen for gesture or graphical input, keyboard, mouse, motion input, speech, etc. The computing system <NUM> can also include an output device <NUM>, which can be one or more of a number of output mechanisms known to those of skill in the art. In some instances, multimodal systems can enable a user to provide multiple types of input/output to communicate with the computing system <NUM>. The computing system <NUM> can include a communications interface <NUM>, which can generally govern and manage the user input and system output. There is no restriction on operating on any particular hardware arrangement, and therefore the basic features here may easily be substituted for improved hardware or firmware arrangements as they are developed.

A storage device <NUM> can be a non-volatile memory device and can be a hard disk or other types of computer readable media which can store data that are accessible by a computer, such as magnetic cassettes, flash memory cards, solid state memory devices, digital versatile disks, cartridges, random access memories (RAMs), read-only memory (ROM), and/or some combination of these devices.

Claim 1:
A parallel multiple-port system, comprising:
a plurality of ports;
a plurality of processors; and
a memory storing software code which, when executed by the plurality of processors causes the processors to control the plurality of ports,
wherein the plurality of processors has a first processor that is configured to control a first port of the plurality of ports,
wherein the plurality of processors has a second processor that is different from the first processor and is configured to control a second port of the plurality of ports different from the first port,
wherein the software code comprises a common software code portion relevant to the plurality of ports and for execution by the plurality of processors, and
wherein the software code further comprises a port specific code portion comprising first configuration data for the first port and for execution by the first processor, the port specific code portion further comprising second configuration data for the second port and for execution by the second processor,
wherein the parallel multiple port system further comprising a plurality of port controllers, wherein each port controller is configured to control one of the plurality of ports, and
wherein the plurality of processors are configured to control the ports via the plurality of port controllers, and
wherein each processor controls a different subsection of the ports and/or the port controllers.