Patent Description:
In conventional peripheral circuitries for a semiconductor memory device, for example, pads and data input/output circuits are arranged in a corresponding manner across layers. For example, a semiconductor memory device may include a data input/output circuit. To achieve high speed transmission, the impedance of the data input/output circuit should be controlled. To control the impedance, an external resistance, such as ZQ resistor may be coupled. The semiconductor memory device including a plurality of chips are generally provided with one external ZQ resistor. When two or more chips request to use the ZQ resistor at the same time, an arbiter circuit is typically used to determine which chip should access the ZQ resistor. Accordingly, one chip can access the ZQ resistor, and a subsequent chip may access the ZQ resistor after ZQ calibration for the one chip has been completed.

For example, arbiter circuits may rely on a voltage based arbitration scheme to determine which chip, a master chip or slave chip, has issued a ZQ calibration request. In the voltage based arbitration scheme, a ZQ calibration request issued by the master chip may have a strong pulldown, while a ZQ calibration request issued by the slave chip may have a weak pulldown. Thus, various states of use of the ZQ resistor may be determined, via a ZQ pad voltage. However, chip packages with multiple-chips and/or of a low-power consumption type may not be able to effectively differentiate between multiple states via the ZQ pad voltage by the voltage based arbitration scheme.

For example, some recent semiconductor devices (e.g., low-power double data rate synchronous DRAM), such as Low Power Double Data Rate <NUM> (LPDDR4), adopted a time based arbitration scheme. Under the time based arbitration scheme, each chip sharing a ZQ resistor is programmed with a unique time delay to create a master-slave hierarchy. This time based arbitration scheme enables any number of chips in the semiconductor memory device per package to use the ZQ resistor, although the required time increases exponentially according to the number of chips. For example, the semiconductor memory device including <NUM> chips sharing a single ZQ resistor may need <NUM> different delay variations for the <NUM> chips.

Thus, an arbitration circuit implementing an arbitration scheme is needed for a semiconductor memory device having a larger number of chips to complete the ZQ calibration without extending time for ZQ calibration request arbitration.

A semiconductor package on package memory channels with arbitration for shared calibration resources is known from <CIT>. Therein is disclosed a semiconductor package on package (PoP) apparatus, comprising a first package including a first memory controller and a second memory controller, a second package coupled to the first package, the second package including a first system memory channel and a second system memory channel, a calibration resistor coupled to the first system memory channel and the second system memory channel via a conductive path through the first package, and arbitration circuitry on the first package coupled to the first memory controller and the second memory controller, the arbitration circuitry configured to prevent calibration signals of the first memory controller from overlapping with the calibration signals of the second memory controller.

<CIT> discloses a memory system comprising a memory controller in communication with a memory module, such as a dual-inline memory module (DIMM), having a plurality of memory devices, such as dynamic random access memory (DRAM) components/devices, wherein each memory device utilizes toggling of appropriate data signals (DQ) in conjunction with an issued extended mode register set (EMRS) command (e.g., a calibrate command) to identify individual memory devices that have been granted slots in which they may have exclusive access to a precision resistor on the memory module for calibration purposes.

In accordance with the present invention, there is provided an apparatus and method as defined by claims <NUM> and <NUM>.

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

<FIG> is a schematic block diagram of a semiconductor memory device <NUM> including a plurality of chips <NUM>, <NUM>, <NUM> and <NUM>, in accordance with an embodiment of the present disclosure. The semiconductor memory device <NUM> may include a controller <NUM>, a command/address bus <NUM>, respective I/O buses IO_A <NUM>, IO_B <NUM>, IO_C <NUM>, and IO_D <NUM>, chip A <NUM>, chip B <NUM>, chip C <NUM>, chip D <NUM>, and a ZQ resistor <NUM>. For example, the semiconductor memory device <NUM> may be packaged in a multi-chip package (MCP) or a package on packages (POP). In the following embodiments, the terms chip and die may be used interchangeably. In some embodiments, the controller <NUM> may be a memory controller. The controller <NUM> may be implemented as part of the same chip, a separate chip, or integrated into another chip, such as a microprocessor. The controller <NUM> may be coupled to each of the chips <NUM>, <NUM>, <NUM>, and <NUM>, via a command/address bus <NUM>. The controller <NUM> may further be coupled to each of the chips <NUM>, <NUM>, <NUM>, and <NUM>, respectively, via respective I/O buses <NUM>, <NUM>, <NUM> and <NUM>. Each of the chips <NUM>, <NUM>, <NUM> and <NUM> may then have their calibration terminals coupled to the ZQ resistor <NUM>. Accordingly, the ZQ resistor <NUM> may be shared among the chips <NUM>, <NUM>, <NUM> and <NUM>. For example, each of the chips <NUM>, <NUM>, <NUM> and <NUM> may individually be a memory device, including, without limitation, NAND flash memory, dynamic random access memory (DRAM) and synchronous DRAM (SDRAM). Alternatively, each of the chip may be a semiconductor device, such as a controller (e.g., the controller <NUM>).

In these embodiments, because the ZQ resistor <NUM> is shared among the chips <NUM>, <NUM>, <NUM> and <NUM> and the command/address bus <NUM> coupled to the controller <NUM> may also be shared among the chips <NUM>, <NUM>, <NUM> and <NUM>, each of the chips <NUM>, <NUM>, <NUM> and <NUM> may be configured to receive commands concurrently, including ZQ calibration commands. As previously discussed, ZQ calibration operations may not typically be performed simultaneously among the chips <NUM>, <NUM>, <NUM> and <NUM>, so arbitration is required to determine the order in which the chips <NUM>, <NUM>, <NUM> and <NUM>, requesting ZQ calibration, may perform a ZQ calibration operation. Accordingly, arbiter circuits may be provided to control ZQ calibration operations. Although in <FIG> the command/address bus <NUM> is shared, this should not be taken as a limiting example. Thus, in other embodiments, the command/address bus <NUM> may include respective lines to the chips <NUM>, <NUM>, <NUM> and <NUM> from the controller <NUM>.

<FIG> is a schematic block diagram of a chip <NUM> of the semiconductor memory device <NUM>, in accordance with an embodiment of the present disclosure. For example, the semiconductor memory device <NUM> may include a ZQ resistor (RZQ) <NUM> and a plurality of chips, including the chip <NUM>. For example, the semiconductor memory device <NUM> including the chip <NUM> and the ZQ resistor (RZQ) <NUM> may be used as the semiconductor memory device <NUM> including the chip <NUM> and the ZQ resistor <NUM> previously described regarding <FIG>.

For example, the chip <NUM> may include a clock input circuit <NUM>, an internal clock generator <NUM>, a timing generator <NUM>, an address command input circuit <NUM>, an address decoder <NUM>, a command decoder <NUM>, a plurality of row decoders <NUM>, a memory cell array <NUM> including sense amplifiers <NUM> and transfer gates <NUM>, a plurality of column decoders <NUM>, a plurality of read/write amplifiers <NUM>, an input/output (I/O) circuit <NUM>, the ZQ resistor (RZQ) <NUM>, a ZQ calibration circuit <NUM>, and a voltage generator <NUM>. The semiconductor memory device <NUM> may include a plurality of external terminals including address and command terminals coupled to command/address bus <NUM>, clock terminals CK and /CK, data terminals DQ, DQS, and DM, power supply terminals VDD, VSS, VDDQ, and VSSQ, and a calibration terminal ZQ. The chip <NUM> may be mounted on a substrate <NUM>, for example, a memory module substrate, a mother board or the like.

The memory cell array <NUM> includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL for each bank is performed by a corresponding row decoder <NUM> and the selection of the bit line BL is performed by a corresponding column decoder <NUM>. The plurality of sense amplifiers <NUM> are located for their corresponding bit lines BL and coupled to at least one respective local I/O line further coupled to a respective one of at least two main I/O line pairs, via transfer gates TG <NUM>, which function as switches.

The address/command input circuit <NUM> may receive an address signal and a bank address signal from outside at the command/address terminals via the command/address bus <NUM> and transmit the address signal and the bank address signal to the address decoder <NUM>. The address decoder <NUM> may decode the address signal received from the address/command input circuit <NUM> and provide a row address signal XADD to the row decoder <NUM>, and a column address signal YADD to the column decoder <NUM>. The address decoder <NUM> may also receive the bank address signal and provide the bank address signal BADD to the row decoder <NUM> and the column decoder <NUM>.

The address/command input circuit <NUM> may receive a command signal from outside, such as, for example, a memory controller <NUM> at the command/address terminals via the command/address bus <NUM> and provide the command signal to the command decoder <NUM>. The command decoder <NUM> may decode the command signal and provide generate various internal command signals. For example, the internal command signals may include a row command signal to select a word line, a column command signal, such as a read command or a write command, to select a bit line, and a ZQ calibration command that may activate the ZQ calibration circuit <NUM>.

Accordingly, when a read command is issued and a row address and a column address are timely supplied with the read command, read data is read from a memory cell in the memory cell array <NUM> designated by the row address and the column address. The read/write amplifiers <NUM> may receive the read data DQ and provide the read data DQ to the IO circuit <NUM>. The IO circuit <NUM> may provide the read data DQ to outside via the data terminals DQ, DQS and DM together with a data strobe signal at DQS and a data mask signal at DM. Similarly, when the write command is issued and a row address and a column address are timely supplied with the write command, and then the input/output circuit <NUM> may receive write data at the data terminals DQ, DQS, DM, together with a data strobe signal at DQS and a data mask signal at DM and provide the write data via the read/write amplifiers <NUM> to the memory cell array <NUM>. Thus, the write data may be written in the memory cell designated by the row address and the column address.

Turning to the explanation of the external terminals included in the semiconductor device <NUM>, the clock terminals CK and /CK may receive an external clock signal and a complementary external clock signal, respectively. The external clock signals (including complementary external clock signal) may be supplied to a clock input circuit <NUM>. The clock input circuit <NUM> may receive the external clock signals and generate an internal clock signal ICLK. The clock input circuit <NUM> may provide the internal clock signal ICLK to an internal clock generator <NUM>. The internal clock generator <NUM> may generate a phase controlled internal clock signal LCLK based on the received internal clock signal ICLK and a clock enable signal CKE from the address/command input circuit <NUM>. Although not limited thereto, a DLL circuit may be used as the internal clock generator <NUM>. The internal clock generator <NUM> may provide the phase controlled internal clock signal LCLK to the IO circuit <NUM> and a timing generator <NUM>. The IO circuit <NUM> may use the phase controller internal clock signal LCLK as a timing signal for determining an output timing of read data. The timing generator <NUM> may receive the internal clock signal ICLK and generate various internal clock signals.

The power supply terminals may receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS may be supplied to a voltage generator circuit <NUM>. The voltage generator circuit <NUM> may generate various internal voltages, VPP, VOD, VARY, VPERI, and the like based on the power supply voltages VDD and VSS. The internal voltage VPP is mainly used in the row decoder <NUM>, the internal voltages VOD and VARY are mainly used in the sense amplifiers <NUM> included in the memory cell array <NUM>, and the internal voltage VPERI is used in many other circuit blocks. The power supply terminals may also receive power supply voltages VDDQ and VSSQ. The IO circuit <NUM> may receive the power supply voltages VDDQ and VSSQ. For example, the power supply voltages VDDQ and VSSQ may be the same voltages as the power supply voltages VDD and VSS, respectively. However, the dedicated power supply voltages VDDQ and VSSQ may be used for the IO circuit <NUM> and the ZQ calibration circuit <NUM>.

The calibration terminal ZQ of the semiconductor memory device <NUM> is coupled to the ZQ calibration circuit <NUM>. The ZQ calibration circuit <NUM> performs a calibration operation with reference to an impedance of the ZQ resistor (RZQ) <NUM>. For example, the ZQ resistor (RZQ) <NUM> may be mounted on the substrate <NUM> that is coupled to the calibration terminal ZQ. For example, the ZQ resistor (RZQ) <NUM> may be coupled to a power supply voltage (VDDQ). An impedance code ZQCODE obtained by the calibration operation may be provided to the IO circuit <NUM>, and thus an impedance of an output buffer (not shown) included in the IO circuit <NUM> is specified.

<FIG> is a circuit diagram of a ZQ calibration circuit <NUM> in accordance with an embodiment of the present disclosure. For example, each chip of the plurality of chips <NUM>, <NUM>, <NUM> and <NUM> includes the ZQ calibration circuit <NUM> and a calibration terminal ZQ (e.g., ZQ pad) <NUM>. The ZQ calibration circuit <NUM> includes an arbiter circuit <NUM>. The arbiter circuit <NUM> may be activated responsive to an activation of a chip (e.g., power on, etc.). For example, the arbiter circuit <NUM> may provide a pull-down (PDN) code signal. The ZQ calibration circuit <NUM> may include a combination of a data terminal (DQ) pull-up (PUP) driver circuit <NUM> and a data terminal (DQ) pull-down (PDN) driver circuit <NUM> and a data terminal (DQ) pull-down (PDN) driver circuit <NUM> for arbitration as well as calibration, that are replica circuits of a data terminal (DQ) pull-up (PUP) driver circuit, a data terminal (DQ) pull-down (PDN) driver circuit and a data terminal (DQ) pull-down (PDN) driver circuit attached to actual data terminals DQ. The DQ PDN driver circuit <NUM> may receive the PDN code signal from the arbiter circuit <NUM>, and may pull down a ZQ pad voltage (VZQ) at the calibration terminal ZQ <NUM> responsive to the PDN code signal. The ZQ pad voltage (VZQ) may be provided to a switch <NUM> (e.g., multiplexer Mux). The combination of the DQ PUP driver circuit <NUM> and the DQ PDN driver circuit <NUM> may execute adjustment of an intermediate ZQ voltage (iVZQ) at an intermediate node <NUM> between the combination of the DQ PUP driver circuit <NUM> and the DQ PDN driver circuit <NUM>. For example, the DQ PUP driver circuit <NUM> may include a plurality of transistors coupled in parallel between a power supply terminal VDDQ and the intermediate node <NUM>. The DQ PDN driver circuit <NUM> may include a plurality of transistors coupled in parallel between a power supply terminal VSSQ and the intermediate node <NUM>. The intermediate ZQ voltage (iVZQ) may be provided to the switch <NUM>. The switch <NUM> may provide either the ZQ pad voltage VZQ or the intermediate ZQ voltage iVZQ, depending on whether the ZQ calibration circuit <NUM> is executing arbitration or ZQ calibration, respectively. For example, the ZQ calibration circuit <NUM> may include a comparator <NUM>. The comparator <NUM> may compare either the ZQ pad voltage VZQ or the intermediate ZQ voltage iVZQ provided by the switch <NUM> with a ZQ reference voltage ZQVREF or a ZQ arbitration reference voltage provided by a reference voltage generator <NUM>. For example, the reference voltage generator <NUM> may be included in the ZQ calibration circuit <NUM>, or the voltage generator <NUM> in <FIG> may provide the ZQ reference voltage ZQVREF and the ZQ arbitration reference voltage instead. For example, the comparator <NUM> may determine whether the ZQ pad voltage (VZQ) has been controlled by another requesting chip or the ZQ resistor RZQ <NUM> is currently in use.

The comparator <NUM> may provide a comparator result signal to the arbiter circuit <NUM> and a ZQ calibration code control circuit <NUM>. For example, the arbiter circuit <NUM> may provide ZQ pad voltage control via the DQ PDN driver circuit <NUM> according to a ZQ timing pattern unique to the chip, having a fixed duration common to the plurality of chips. The arbiter circuit <NUM> may provide the PDN code until the ZQ pad voltage (VZQ) at the calibration terminal ZQ <NUM> using the ZQ arbitration reference voltage, which may be different from the ZQ reference voltage ZQVREF. The ZQ timing pattern is unique for each chip, in order to determine whether the requesting chip should gain access to a ZQ resistor RZQ <NUM>. The ZQ timing pattern may be programmed, or otherwise stored for each chip. For example, the arbiter circuit <NUM> for the chip <NUM> may include a register (not shown) for the chip <NUM> that may be programmed with the ZQ timing pattern information specific to the chip <NUM> for a duration common to the chips. Thus, each arbiter circuit <NUM> for each respective chip may be configured to store the ZQ timing pattern information of a duration that is different from ZQ timing pattern information having the same duration, stored on the registers of the other chips. For example, the timing pattern information may be unique to an individual chip among a plurality of chips of the semiconductor memory device <NUM>. The register may include, without limitation, programmable fuses, anti-fuses, a mode register, or other suitable components. Thus, the priority of a chip may be set or programmed via the register. The ZQ calibration code control circuit <NUM> may be included in the ZQ calibration circuit <NUM>. The ZQ calibration code control circuit <NUM> may provide a PUP code and a PDN code to the DQ PUP driver circuit <NUM> and the DQ PDN driver circuit <NUM> respectively, responsive to the comparator result signal until the intermediate ZQ voltage iVZQ at the intermediate node <NUM> may match the ZQ reference voltage ZQVREF.

<FIG> is a flow diagram of a ZQ calibration arbitration in accordance with an embodiment of the present disclosure. <FIG> is a timing diagram of an arbitration clock and a ZQ pad voltage VZQ in the ZQ calibration arbitration in accordance with the embodiment of the present disclosure. For example, the ZQ calibration may start with a fixed length time-based arbitration (S400). Each chip may provide a request for the ZQ calibration using a ZQ resistor (e.g., the ZQ resistor <NUM>, <NUM>). The first step (Step <NUM>, S401) of the fixed length time-based arbitration is header detection. For example, an initial state of the fixed length time-based arbitration may be that the ZQ pad voltage being set to a float high state (e.g., disabling the DQ PDN driver circuit <NUM>) to provide a header. For example, the header may be signaled by the ZQ pad voltage VZQ being maintained at a logic high level for three clock cycles. The ZQ pad voltage VZQ may be compared (e.g., by the comparator <NUM>) with a ZQ arbitration reference voltage at an end of each clock cycle of three clock cycles. For example, the ZQ arbitration reference voltage may be in-between a pull-down voltage range (e.g., substantially 0V) signaling a logic low state and the power supply voltage VDDQ signaling the logic high state. Because the ZQ resistor may be coupled to the power supply voltage VDDQ (or VSS) and the header is at the logic high state (or a logic low state), another chip may be executing either the ZQ calibration arbitration process or the ZQ calibration process, if the ZQ pad voltage VZQ is in the pull-down voltage range, lower than the ZQ arbitration reference voltage. Thus, the current request fails and repeats Step <NUM> of the ZQ arbitration to re-request the ZQ calibration. If the ZQ pad voltage VZQ is higher than the ZQ arbitration reference voltage during Step <NUM>, the request may proceed to the second step. The second step may include pulling down the ZQ pad voltage for a certain period (Step <NUM>, S402) to signal that the ZQ calibration is being requested to the other chip. For example, the duration of this pulling down may be two clock cycles, or other clock cycles, without limitation.

The third step (Step <NUM>, S403) of the fixed length time-based arbitration may include a binary coding and detection. For each chip, a die number that may be a binary code unique to each chip may be assigned and signaled as a unique ZQ timing pattern. The die number may be used to determine chip priority. The ZQ pad voltage VZQ may be compared (e.g., by the comparator <NUM>) with a ZQ arbitration reference voltage at an end of each clock cycle of a fixed duration of the ZQ timing pattern common to the chips. For each chip, pulling down the ZQ pad voltage VZQ may be disabled for one clock cycle if a bit in the die number for the current chip is high. Because the ZQ resistor may be coupled to the power supply voltage VDDQ (or VSS) and the die number for the current chip corresponds to the logic high state (or a logic low state), another chip may be executing either the ZQ calibration arbitration process with priority or the ZQ calibration, if the ZQ pad voltage VZQ is in the pull-down voltage range (or in the pull-up voltage range). Thus, the current request fails and repeats Step <NUM> of the ZQ arbitration to re-request the ZQ calibration. For example, increasing the minimum clock cycles of the logic low state between the two logic high states may improve detection of the comparator's comparator result. After Step <NUM> (S403), the request may include the fourth step of pulling down the ZQ pad voltage for a certain period (Step <NUM>, S405) to signal that the ZQ calibration is being requested to the other chip. For example, the duration of this pulling down may be two clock cycles, or other clock cycles, without limitation.

The fifth step (Step <NUM>, S405) of the fixed length time-based arbitration may include a stop bit detection. For each chip, a common stop bit of a fixed duration (e.g., one clock cycle) of the ZQ timing pattern common to the chips may be signaled by disabling pulling down the ZQ pad voltage VZQ for the fixed duration (e.g., one clock cycle) corresponding to the stop bit. The ZQ pad voltage VZQ may be compared (e.g., by the comparator <NUM>) with a ZQ arbitration reference voltage at an end of the fixed duration (e.g., one clock cycle) signaling the stop bit. The ZQ resistor may be coupled to the power supply voltage VDDQ and the ZQ pad voltage VZQ corresponds to the stop bit is supposed to be at the logic high state. Thus, the arbitration passes and ZQ calibration process for the current chip may be initiated, if the ZQ pad voltage VZQ is at the logic high state (e.g., in the pull-up voltage range). Another chip may be executing either the ZQ calibration arbitration process or the ZQ calibration process, if the ZQ pad voltage VZQ is in the pull-down voltage range, and the current request fails and repeats Step <NUM> of the next ZQ arbitration to re-request the ZQ calibration.

<FIG> is a schematic diagram of an arbiter circuit <NUM> in the ZQ calibration circuit in accordance with an embodiment of the present disclosure. For example, the arbiter circuit <NUM> may be the arbiter circuit <NUM> in <FIG>. The arbiter circuit <NUM> may include a set of fuses indicating a set of die number <<NUM>:<NUM>> signals (e.g., the die number in Step <NUM> S403 of <FIG>) of a current chip (die) among a plurality of chips among in a semiconductor memory device. For example, the arbiter circuit <NUM> may include buffers <NUM>, <NUM>, <NUM> and <NUM> that may receive and provide the die number <<NUM>>, the die number <<NUM>>, the die number <<NUM>> and the die number <<NUM>> respectively in Step <NUM> (S403). The arbiter circuit <NUM> may include output terminals <NUM>, <NUM>, <NUM> and <NUM>. The output terminal <NUM> may provide the die number <<NUM>> signal as a first bit (bit <NUM>) of the ZQ timing pattern in Step <NUM>. The output terminal <NUM> may provide the die number <<NUM>> signal as a second bit (bit <NUM>) of the ZQ timing pattern in Step <NUM>. The output terminal <NUM> may provide the die number <<NUM>> signal as a third bit (bit <NUM>) of the ZQ timing pattern in Step <NUM>. The output terminal <NUM> may provide the die number <<NUM>> signal as a fourth bit (bit <NUM>) of the ZQ timing pattern in Step <NUM>.

The arbiter circuit <NUM> may also include a logic circuit <NUM> (e.g., a NOR circuit) and an output terminal <NUM>. The logic circuit <NUM> may receive the die number <<NUM>>-<<NUM>>signals and provide an active state signal (e.g., at a logic high level) when a chip having all the die number <<NUM>>-<<NUM>> signals are inactive (e.g., a logic low level) is requesting for the ZQ calibration in Step <NUM> (S403). The output terminal <NUM> may provide the active state signal as a fifth bit (bit <NUM>) of the ZQ timing pattern in Step <NUM> to indicate if the chip having all the die number <<NUM>>-<<NUM>> signals is requesting for the ZQ calibration.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. For example, the plurality of chips may include Die0, Die1, Die2 and Die3. In fixed length time-based arbitration, each chip, Die0, Die1, Die2 and Die3 may provide a request for the ZQ calibration using a ZQ resistor (e.g., the ZQ resistor <NUM>, <NUM>). The first step of the fixed length time-based arbitration is the header detection (e.g., Step <NUM>, S401 in <FIG>) that may be executed by the ZQ pad voltage control by setting the ZQ pad voltage to a float high state (e.g., by disabling the DQ PDN driver circuit <NUM>) to provide a header. For example, the header may be signaled for three clock cycles from T0, which is common for any chip of the plurality of chips, Die0, Die1, Die2 and Die3. Each chip requesting the ZQ calibration may compare the ZQ pad voltage VZQ (e.g., by the comparator <NUM>) with a ZQ arbitration reference voltage in-between the pull-down voltage range and the power supply voltage VDDQ at an end of each clock cycle at T1, T2 and T3 during Step <NUM> (S401). Because the ZQ resistor may be coupled to the power supply voltage VDDQ and the ZQ pad voltage control any chip requesting ZQ calibration pulls up the ZQ pad voltage to the logic high state, another chip may be executing either the ZQ calibration arbitration process or the ZQ calibration process, if the ZQ pad voltage VZQ is in the pull-down voltage range, lower than the ZQ arbitration reference voltage. Thus, the current request fails and repeats the ZQ arbitration to re-request the ZQ calibration. If the ZQ pad voltage VZQ is higher than the ZQ arbitration reference voltage for each clock cycle of Step <NUM> (S401), the fixed length time-based arbitration may proceed to a second step (Step <NUM>, S402). The second step, pulling down the ZQ pad voltage for a certain period (Step <NUM>, S402) following Step <NUM> may be executed to signal that the ZQ calibration is being requested to the other chip. For example, the duration of this pulling down may be two clock cycles from T3 to T5 as shown in <FIG>. Alternatively other clock cycles, without limitation may be used for Step <NUM>.

The third step (Step <NUM>, S403) of the fixed length time-based arbitration may include a binary coding and detection, from T5 to T12 as shown in <FIG>. For each chip, a die number that may be a binary code unique to each chip may be assigned and signaled as a unique ZQ timing pattern. The die number may be used to determine chip priority. For each chip, pulling down the ZQ pad voltage VZQ may be disabled for one clock cycle if a bit in the die number for the current chip is high. For example, Die0 may have a die number "<NUM>", and pulling down the ZQ pad voltage VZQ may be disabled for a clock cycle from T11 to T12 corresponding to the third bit "<NUM>" in "<NUM>". Die1 may have a die number "<NUM>", and pulling down the ZQ pad voltage VZQ may be disabled for a clock cycle from T8 to T9 corresponding to the second bit "<NUM>" in "<NUM>". Die2 may have a die number "<NUM>", and pulling down the ZQ pad voltage VZQ may be disabled for a clock cycle from T8 to T9 corresponding to the second bit "<NUM>" in "<NUM>" and a clock cycle from T11 to T12 corresponding to the third bit "<NUM>" in "<NUM>". Die3 may have a die number "<NUM>", and pulling down the ZQ pad voltage VZQ may be disabled for a clock cycle from T5 to T6 corresponding to the first bit "<NUM>" in "<NUM>". The ZQ pad voltage VZQ may be compared (e.g., by the comparator <NUM>) with a ZQ arbitration reference voltage at an end of each clock cycle of a fixed duration of the ZQ timing pattern common to the chips. Another chip may be executing either the ZQ calibration arbitration process with priority or the ZQ calibration, if the ZQ pad voltage VZQ is in the pull-down voltage range, thus the current request fails and repeats Step <NUM> of the ZQ arbitration to re-request the ZQ calibration. After Step <NUM> (S403) is complete, the request may proceed to the fourth step of pulling down the ZQ pad voltage for a certain period (Step <NUM>, S405) to signal that the ZQ calibration is being requested to the other chip. For example, the duration of this pulling down may be two clock cycles (e.g., T12 to T14 in <FIG>), or other clock cycles, without limitation.

The fifth step (Step <NUM>, S405) of the fixed length time-based arbitration may include a stop bit detection. For each chip, a common stop bit of a fixed duration (e.g., from T14 to T15 in <FIG>) of the ZQ timing pattern common to the chips may be signaled by disabling pulling down the ZQ pad voltage VZQ during Step <NUM>. The ZQ pad voltage VZQ may be compared (e.g., by the comparator <NUM>) with a ZQ arbitration reference voltage at an end of the fixed duration (e.g., T15 in <FIG>) signaling the stop bit. Thus, the arbitration passes and ZQ calibration process for the current chip may be initiated, if the ZQ pad voltage VZQ is at the logic high state (e.g., in the pull-up voltage range). Another chip may be executing either the ZQ calibration arbitration process or the ZQ calibration process, if the ZQ pad voltage VZQ is in the pull-down voltage range, and the current request fails and repeats Step <NUM> of the ZQ arbitration to re-request the ZQ calibration.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components and steps (Steps <NUM>, <NUM>, <NUM> and <NUM>) included in and previously described with reference to <FIG> will not be repeated. The third step (Step <NUM>, S403) of the fixed length time-based arbitration may include another binary coding and detection, from T5 to T12 as shown in <FIG>. For example, Die0 may have a die number "<NUM>" and other chips Die1 to Die3 may have die numbers "<NUM>" to "<NUM>" that may be directly binary coded from a die identifier "<NUM>" to "<NUM>".

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components and steps (Steps <NUM>, <NUM>, <NUM> and <NUM>) included in and previously described with reference to <FIG> will not be repeated. The third step (Step <NUM>, S403) of the fixed length time-based arbitration may include another binary coding and detection, from T5 to T21 as shown in <FIG>. The die number binary coded for each chip may be mirrored in the timing diagram of <FIG> to be symmetrical with respect to the center of the ZQ timing pattern (e.g., in a time domain) during Step <NUM>. For example, Die0 may have a die number "<NUM>", Die1 may have a die number binary codes "<NUM>". Die2 may have a die number "<NUM>". Die3 may have a die number "<NUM>". The mirrored ZQ timing pattern may be more resistant to aliasing with large oscillator variation.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components and steps included in and previously described with reference to <FIG> will not be repeated. If a clock cycle of one chip (e.g., Die B) in the plurality of chips is longer than a clock cycle of another chip (e.g., Die A) in the plurality of chips and a pulse width in a logic high state to signal a stop bit in Step <NUM> of the one chip (Die B) may be longer than a period between a first and third strobes in Step <NUM> of the other chip (Die A). Thus, the other chip (Die A) may fail to detect that the one chip (Die B) is proceeding to ZQ calibration. In order to prevent such failure, a pulse width in a float state of the one chip (Die B) may be configured shorter than two clock cycles of the other chip (Die A) as expressed in an inequality below.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components and steps included in and previously described with reference to <FIG> will not be repeated. If a pulse width of a last bit in Step <NUM> in a logic high state of one chip (e.g., Die B) is longer than a clock cycle of another chip (e.g., Die A), and the last bit is followed by the stop bit, the pulse width of the last bit in Step <NUM> of the one chip (Die B) may still overlaps the first and second strobes of Step <NUM> in the other chip (Die A) and the stop bit in Step <NUM> of the one chip (Die B) may coincide with the third strobe of Step <NUM> in the other chip (Die A). Thus, the other chip (Die A) may fail to detect that the one chip (Die B) is proceeding to ZQ calibration. In order to prevent such failure, duration of pulling-down the ZQ pad voltage in Step <NUM> and Step <NUM> may be configured to be longer than two clock cycles and the pulse width in a float high state in Step <NUM> and Step <NUM> may be configured to be shorter than one clock cycle.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components and steps included in and previously described with reference to <FIG> will not be repeated. If a clock cycle of one chip (e.g., Die B) in the plurality of chips is three clock cycles of another chip (e.g., Die A) or longer in the plurality of chips, a pulse width corresponding to a third bit of a die number "<NUM>" for the other chip (Die A) in Step <NUM> in a logic high state may coincide with a first bit of a die number "11xxx (x: don't care)" of the one chip (Die B) in Step <NUM> and a stop bit for the other chip (Die A) in Step <NUM> may coincide with a second bit of the die number of the one chip (Die B). Thus, the one chip (Die B) may fail to detect that the other chip (Die A) is proceeding to ZQ calibration. In order to prevent such failure, a clock cycle difference between chips may be configured to be limited to within ±<NUM>%.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components and steps included in and previously described with reference to <FIG> will not be repeated. Assuming that a clock cycle of one chip (e.g., Die B) in the plurality of chips is about one and half clock cycles of another chip (e.g., Die A) or longer in the plurality of chips, a pulse width corresponding to a third bit of a die number "<NUM>" for the other chip (Die A) in Step <NUM> in a logic high state may coincide with a second bit of a die number "0101x (x: don't care)" of the one chip (Die B) in Step <NUM> and a stop bit for the other chip (Die A) in Step <NUM> may coincide with a fourth bit of the die number of the one chip (Die B). Thus, the one chip (Die B) may fail to detect that the other chip (Die A) is proceeding to ZQ calibration. In order to prevent such failure, a die number "<NUM>" may be classified as illegal and prohibited to use (e.g., instead, use a die number "<NUM>"). Logic levels of signals, particularly a binary coded die number used and/or prohibited in the embodiments described the above are merely examples and not limited to those specifically described in the above.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components and steps included in and previously described with reference to <FIG> will not be repeated. If a clock cycle of one chip (e.g., Die B) in the plurality of chips is two clock cycles of another chip (e.g., Die A) or longer in the plurality of chips, a pulse width corresponding to a second bit, a fourth bit of a die number "<NUM>" for the other chip (Die A) in Step <NUM> in a logic high state and a stop bit in Step <NUM> may coincide with first to third bits of a die number "111xx (x: don't care)" of the one chip (Die B) in Step <NUM>, respectively. Thus, the one chip (Die B) may fail to detect that the other chip (Die A) is proceeding to ZQ calibration. This scenario may be prevented, if a clock cycle difference between chips may be configured to be limited to within ±<NUM>% as described above referring to <FIG>.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components included in and previously described with reference to <FIG> will not be repeated. A first step of time-based arbitration is header detection (e.g., Float and Hi-Detect in <FIG>). For example, the header may be signaled by the ZQ pad voltage VZQ at a logic high level for three clock cycles. If the ZQ pad voltage VZQ is higher than the ZQ arbitration reference voltage during the header detection, the request may proceed to a second step of pulling down the ZQ pad voltage for a certain period (e.g., Oscillator Alignment Pull-down in <FIG>) to signal that the ZQ calibration is being requested to the other chip. For example, the duration of this pulling down may be nine clock cycles, or other clock cycles, without limitation. A third step (e.g., Sync Detect in <FIG>) of the time-based arbitration may include a sync bit detection. For each chip, a common sync bit of a fixed duration (e.g., one clock cycle) of the ZQ timing pattern common to the chips may be signaled by disabling pulling down the ZQ pad voltage VZQ for the fixed duration (e.g., one clock cycle) corresponding to the sync bit. Once the sync bit is detected, a fourth step of the time-based arbitration may include a ZQ calibration request detection (e.g., Staggered Requests in <FIG>). For each chip, a pulse with a same width and a delay unique to the chip may be assigned and signaled as a unique ZQ timing pattern. For example, the delay may be longer, if a priority of ZQ calibration to the chip is higher. If the ZQ pad voltage VZQ is higher than the ZQ arbitration reference voltage during the pulse, the request may proceed to the ZQ calibration.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components included in and previously described with reference to <FIG> and <FIG> will not be repeated. For example, timings (e.g., phases) of the first step including three clock cycles may differ for the plurality of chips. For example, the first step of Die1 may have a delay of a half clock cycle from the first step of Die0 that may have a delay of a half clock cycle from the first steps of Die2 and Die3. For example, durations of the second step including three clock cycles may differ for the plurality of chips due to different clock cycles of oscillators (e.g., oscillator <NUM> in <FIG>) for the plurality of chips, in addition to different timings of the second step for the plurality of chips. For example, Die2 and Die3 may enter the second step at the same time, however, Die2 may proceed to the third step earlier than Die3 proceeds (e.g., three clock cycles before based on a clock signal CLK, as shown in <FIG>).

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components included in and previously described with reference to <FIG> will not be repeated. For example, the ZQ calibration may start with a fixed length time-based arbitration. A first step of the fixed length time-based arbitration is header detection (e.g., Float and Hi-Detect in <FIG>). For example, the header may be signaled by the ZQ pad voltage VZQ at a logic high level for three clock cycles. If the ZQ pad voltage VZQ is higher than the ZQ arbitration reference voltage during the header detection, the request may proceed to a second step of the fixed length time-based arbitration may include a ZQ calibration request detection (e.g., First Detect in <FIG>). For each chip, a pulse with a same width and a delay unique to the chip may be assigned and signaled in a same duration of the second step as a unique ZQ timing pattern. For example, the delay may be longer, if a priority of ZQ calibration to the chip is higher. If the ZQ pad voltage VZQ is lower than the ZQ arbitration reference voltage during the pulse, the request may fail and repeats Step <NUM> of the ZQ arbitration to re- request the ZQ calibration. After the second step, a third step (e.g., Sync and Requests Detect in <FIG>) of the fixed length time-based arbitration may be executed. For each chip, a common request period for a plurality of clock cycles (e.g., six clock cycles in a logic low state in <FIG>) by pulling-down the ZQ pad voltage VZQ followed by a common sync bit by disabling pulling down the ZQ pad voltage VZQ for a fixed duration (e.g., one clock cycle) may be signaled. The arbitration passes and ZQ calibration process for the current chip may be initiated, once the sync bit is detected by detecting the ZQ pad voltage VZQ at the logic high state (e.g., in the pull-up voltage range). Another chip may be executing either the ZQ calibration arbitration process or the ZQ calibration process, if the ZQ pad voltage VZQ is in the pull-down voltage range, and the current request fails and repeats Step <NUM> of the ZQ arbitration to re-request the ZQ calibration.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components included in and previously described with reference to <FIG>, <FIG> and <FIG> will not be repeated. For example, timings (e.g., phases) of the first step including three clock cycles may differ for the plurality of chips. For example, the first step of Die1 may have a delay of a half clock cycle from the first step of Die0 that may have a delay of a half clock cycle from the first steps of Die2 and Die3. For each chip, a pulse with a same number of clock cycle (one clock cycle) and a delay (e.g., a unique number of clock cycles) may be assigned and signaled in a same number of clock cycles for each chip of the second step as a unique ZQ timing pattern. For example, durations of the second step including the pulse may differ for the plurality of chips due to different clock cycles for the plurality of chips in a same number of clock cycles of the second step, in addition to different timings of the second step for the plurality of chips. After the second step, a third step (e.g., Sync and Requests Detect in <FIG>) of the fixed length time-based arbitration may be executed. For example, Die2 and Die3 may enter the second step at the same time, however, Die2 may proceed to the sync bit of the third step earlier than Die3 proceeds (e.g., six clock cycles before, as shown in <FIG>), due to different clock cycles of oscillators (e.g., oscillator <NUM> in <FIG>) for the plurality of chips.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components included in and previously described with reference to <FIG> and <FIG> will not be repeated. In the second step, unlike including one pulse in <FIG>, the ZQ timing pattern includes two pulses. Similarly to <FIG>, the die number linear coded for each chip may be mirrored in the timing diagram of <FIG> to be symmetrical with respect to the center of the second step of the ZQ timing pattern. Thus the first pulse is included in a first period (e.g., First Detect in <FIG>) and the second pulse is included in a second period (e.g., Final Request Detect in <FIG>) in the second step. The mirrored ZQ timing pattern in <FIG> may be more resistant to aliasing with large oscillator variation.

<FIG> is a timing diagram of a plurality of arbitration signal patterns for a plurality of chips in accordance with an embodiment of the present disclosure. Description of components and steps corresponding to components included in and previously described with reference to <FIG>, <FIG> and <FIG> will not be repeated. For example, timings (e.g., phases) of the first step including three clock cycles may differ for the plurality of chips. For each chip, two pulses with a same number of clock cycle (one clock cycle) and a delay (e.g., a unique number of clock cycles) mirrored in the timing diagram of <FIG> to be symmetrical with respect to the center of the second step of the ZQ timing pattern may be assigned and signaled in a same number of clock cycles for each chip of the second step as a unique ZQ timing pattern. For example, durations of the second step including the pulses may differ for the plurality of chips due to different clock cycles for the plurality of chips in a same number of clock cycles of the second step, in addition to different timings of the second step for the plurality of chips. For example, Die2 and Die3 may enter the second step at the same time, however, Die2 may proceed to the ZQ calibration earlier than Die3 proceeds, due to different clock cycles of oscillators (e.g., oscillator <NUM> in <FIG>) for the plurality of chips. The mirrored ZQ timing pattern may be more resistant to aliasing with large oscillator variation.

Logic levels of signals used in the embodiments described the above are merely examples. However, in other embodiments, combinations of the logic levels of signals other than those specifically described in the present disclosure may be used without departing from the scope of the present disclosure.

Claim 1:
A memory device (<NUM>) comprising:
a resistor (<NUM>; <NUM>) coupled between a power supply voltage and a terminal; and
a plurality of chips (<NUM>, <NUM>, <NUM>, <NUM>; <NUM>, <NUM>, <NUM>, <NUM>), wherein each chip comprises:
a terminal (<NUM>) coupled to the resistor;
a calibration circuit (<NUM>) configured to determine whether the resistor is available for impedance calibration based, at least in part, on timing information, wherein the timing information of the chip includes a binary code unique to the corresponding chip of the plurality of chips and having a fixed duration common to the plurality of chips, wherein the binary code includes a combination of at least one first period in a first logic state and at least one second period in a second logic state unique to the chip; and
wherein the calibration circuit comprises:
a driver circuit coupled to the terminal; and
an arbiter circuit configured to:
enable the driver circuit to change the voltage of the terminal to the second logic state in the at least one second period and further configured to disable the driver circuit to change the voltage of the terminal to the first logic state in the at least one first period before determining whether the resistor is available for impedance calibration, based on the binary code; and
determine that the resistor is available for impedance calibration when the voltage of the terminal is at the first logic state in the at least one first period or when the voltage of the terminal is at the second logic state in the at least one second period.