Patent Description:
For next-generation high-performance communication appliances, a semiconductor package including a logic device and high-bandwidth memory (HBM) devices are being studied. Such semiconductor packages may include an interposer mounted on a substrate, and a logic chip and a plurality of memory stacks mounted on the interposer. In particular, semiconductor packages designed to be suitable for mobile communication are manufactured to be thin and, as such, may be very weak against external physical stress, such as warpage. Further, warpage of chips may easily occur in an extension direction of boundary areas (or boundary lines) of the chips. In this case, the resultant semiconductor package may be physically or electrically damaged.

<CIT> discloses a semiconductor package comprising:.

<CIT> discloses a semiconductor package comprising:
a substrate; an interposer on the substrate; and a first logic chip and a second logic chip on the interposer, the first logic chip and the second logic chip are side-by-side so as to be adjacent to each other; memory stacks including a plurality of stacked memory chips, each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip, the memory stacks are disposed on the interposer.

According to an aspect of the present invention, there is provided a semiconductor package according to claim <NUM>.

Embodiments according to the claimed invention provide packages having a stiffening structure capable of avoiding or limiting warpage.

Embodiments according to the claimed invention also provide stiffening structures capable of protecting constituent elements from physical impact.

Various problems to be solved by some example embodiments of the disclosure are concretely described in this specification.

A semiconductor package according to the claimed invention includes a substrate, an interposer on the substrate, and a first logic chip and a second logic chip on the interposer, the first logic chip and the second logic chip are side-by-side so as to be adjacent to each other, memory stacks including a plurality of stacked memory chips, each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip, the memory stacks on the interposer, and stiffening chips on the interposer, the stiffening chips between corresponding ones of the memory stacks, the stiffening chips aligned with an extension line of a boundary area between the first logic chip and the second logic chip.

A semiconductor package according to some example embodiments of the disclosure includes a substrate, an interposer on the substrate, first and second logic chips on the interposer such that the first and second logic chips are adjacent to each other, first memory stacks at opposite side surfaces of the first logic chip, and second memory stacks at opposite side surfaces of the second logic chip, and stiffening chips between the first memory stacks and the second memory stacks. The first and second logic chips may be electrically connected through a wiring inside the interposer. A minimum distance between the first logic chip and the second logic chip may be smaller than a minimum distance between the first memory stacks and the second memory stacks. The stiffening chips are adjacent to a boundary area between the first logic chip and the second logic chip and aligned with an extension line of the boundary area. The stiffening chips have a greater width than the boundary area.

A semiconductor package according to some example embodiments of the disclosure may include a substrate, an interposer on the substrate, a plurality of logic chips on the interposer, adjacent to one another within <NUM>, and the logic chips are electrically connected through the interposer, a plurality of memory stacks on the interposer, each of the memory stacks includes a plurality of stacked memory chips, and through vias extending vertically through the memory chips, and a plurality of stiffening chips on the interposer, longer sides of the stiffening chips are parallel to shorter sides of the memory stacks, shorter sides of the stiffening chips have a length corresponding to <NUM>/<NUM> or less of a length of longer sides of the memory stacks, and each of the stiffening chips has a greater width than a boundary area between corresponding ones of the logic chips such that the stiffening chip horizontally overlaps with portions of the corresponding logic chips, and a molding compound surrounding side surfaces of the interposer, side surfaces of the logic chips, side surfaces of the memory stacks and side surfaces of the stiffening chips.

Various effects according to example embodiments of the disclosure are described in this specification.

<FIG> is a projected top view schematically showing a semiconductor package 100A according to some example embodiments of the disclosure.

Referring to <FIG>, the semiconductor package 100A according to some example embodiments of the disclosure may include an interposer <NUM> disposed on a substrate <NUM>, upper and lower logic chips <NUM> and <NUM>, a plurality of memory stacks 41a to 41d and 42a to 42d, and stiffening chips 51a and 51b.

The interposer <NUM> is mounted on the substrate <NUM>. Each of the substrate <NUM> and the interposer <NUM> may include one of a printed circuit board (PCB), a flexible PCB (FPCB), a silicon-based substrate, a ceramic substrate, a glass substrate, and/or an insulating circuit board. In some example embodiments, the substrate <NUM> may include a PCB or an FPCB. The interposer <NUM> may include a silicon-based substrate or a re-distribution structure.

The upper and lower logic chips <NUM> and <NUM> are disposed side-by-side in a column direction such that upper and lower logic chips <NUM> and <NUM> are disposed adjacent to each other. Each of the upper and lower logic chips <NUM> and <NUM> may include one of a core processor, an application specific integrated circuit (ASIC), a mobile application processor (AP) and/or other processing chips. The terms "upper" and "lower" are used to distinguish the logic chips <NUM> and <NUM> from each other in the drawings. The upper and lower logic chips <NUM> and <NUM> are horizontally disposed at the same level.

The memory stacks 41a to 41d and 42a to 42d may include first to fourth upper memory stacks 41a to 41d disposed side-by-side with respect to the upper logic chip <NUM> in a row direction, and first to fourth lower memory stacks 42a to 42d disposed side-by-side with respect to the lower logic chip <NUM> in the row direction. The row direction and the column direction are relative to each other, and may be interchanged with each other.

The first to fourth upper memory stacks 41a to 41d may be symmetrically disposed in parallel in the row direction at opposite sides of the upper logic chip <NUM>. In detail, the first and second upper memory stacks 41a and 41b may be disposed at a first side surface of the upper logic chip <NUM>, for example, at a left side of the upper logic chip <NUM>, whereas the third and fourth memory stacks 41c and 41d may be disposed at a second side surface of the upper logic chip <NUM>, for example, at a right side of the upper logic chip <NUM>. The first and second upper memory stacks 41a and 41b may be aligned with each other in the column direction while being disposed side-by-side in the column direction. Similarly, the third and fourth upper memory stacks 41c and 41d may be aligned with each other in the column direction while being disposed side-by-side in the column direction. Accordingly, the first and third upper memory stacks 41a and 41c may be disposed at a higher level than the second and fourth upper memory stacks 41b and 41d.

The first to fourth lower memory stacks 42a to 42d may be symmetrically disposed in parallel in the row direction at opposite sides of the lower logic chip <NUM>. In detail, the first and second lower memory stacks 42a and 42b may be disposed at a first side surface of the lower logic chip <NUM>, for example, at a left side of the lower logic chip <NUM>, whereas the third and fourth memory stacks 42c and 42d may be disposed at a second side surface of the lower logic chip <NUM>, for example, at a right side of the lower logic chip <NUM>. The first and second lower memory stacks 42a and 42b may be aligned with each other in the column direction while being disposed side-by-side in the column direction. Similarly, the third and fourth lower memory stacks 42c and 42d may be aligned with each other in the column direction while being disposed side-by-side in the column direction. Accordingly, the first and third lower memory stacks 42a and 42c may be disposed at a higher level than the second and fourth lower memory stacks 42b and 42d.

The stiffening chips 51a and 52b are disposed to be aligned with a boundary area (boundary line) between the upper logic chip <NUM> and the lower logic chip <NUM> in the row direction while overlapping with the boundary area (boundary line) in the row direction. The stiffening chips 51a and 51b have a greater width than the boundary area (boundary line) between the upper logic chip <NUM> and the lower logic chip <NUM>. Accordingly, the stiffening chips 51a and 51b overlap with a portion of the upper logic chip <NUM> and a portion of the lower logic chip <NUM> in the row direction.

The stiffening chips 51a and 51b may include a first stiffening chip 51a disposed at a left side of the boundary area (boundary line) between the upper logic chip <NUM> and the lower logic chip <NUM>, and a second stiffening chip 51b disposed at a right side of the boundary area (boundary line) between the upper logic chip <NUM> and the lower logic chip <NUM>. The first stiffening chip 51a may be aligned with the first and second upper memory stacks 41a and 41b and the first and second lower memory stacks 42a and 42b in the column direction. The second stiffening chip 51b may be aligned with the third and fourth upper memory stacks 41c and 41d and the third and fourth lower memory stacks 42c and 42d in the column direction. For example, the first stiffening chip 51a may be disposed between the second upper memory stack 41b and the first lower memory stack 42a, whereas the second stiffening chip 51b may be disposed between the fourth upper memory stack 41d and the third lower memory stack 42c. The stiffening chips 51a and 51b may be smaller than the memory stacks 41a to 41d and 42a to 42d. Shorter sides of the stiffening chips 51a and 51b have a smaller length than a length of longer sides of the memory stacks 41a to 41d and 42a to 42d such that the shorter-side length is <NUM>/<NUM> or less of the longer-side length. Longer sides of the stiffening chips 51a and 51b may have a smaller length than shorter sides of the memory stacks 41a to 41d and 42a to 42d. The longer sides of the stiffening chips 51a and 51b may be parallel with the shorter sides of the memory stacks 41a to 41d and 42a to 42d. Portions of the shorter sides of the stiffening chips 51a and 51b may be aligned with portions of the memory stacks 41a to 41d and 42a to 42d.

The upper logic chip <NUM> and the lower logic chip <NUM> may be disposed to be spaced apart from each other or adjacent to each other by a distance of about <NUM> to <NUM>. In some example embodiments, the upper logic chip <NUM> and the lower logic chip <NUM> may be disposed to be spaced apart from each other or adjacent to each other by a distance of about <NUM>. That is, the logic chips <NUM> and <NUM> may be disposed to be very closely adjacent to each other. The logic chips <NUM> and <NUM> and the memory stacks 41a to 41d and 42a to 42d may be disposed to be spaced apart from each other or adjacent to each other by a distance of about <NUM> to <NUM>. In some example embodiments, the logic chips <NUM> and <NUM> and the memory stacks 41a to 41d and 42a to 42d may be disposed to be spaced apart from each other or adjacent to each other by a distance of about <NUM>.

When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value include a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical value. Moreover, when the words "generally" and "substantially" are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as "about" or "substantially," it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical values or shapes. While the term "same" or "identical" is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±<NUM>%).

For example, a first gap (e.g., a first minimum distance) between the logic chips <NUM> and <NUM> may be smaller than a second gap (a second minimum distance) between one of the logic chips <NUM> and <NUM> and adjacent one of the memory stacks 41a to 41d and 42a to 42d. A third gap (a third minimum distance) between one the logic chips <NUM> and <NUM> and adjacent one of the stiffening chips 51a and 51b may be greater than the second gap (the second minimum distance). For example, the memory stacks 41a to 41d and 42a to 42d may be disposed nearer to the logic chips <NUM> and <NUM> than the stiffening chips 51a and 51b, respectively. A fourth gap (a fourth minimum distance) between one of the stiffening chips 51a and 51b and adjacent one of the memory stacks 41a to 41d and 42a to 42d may be smaller than a fifth gap (a fifth minimum distance) between adjacent two of the memory stacks 41a to 41d and 42a to 42d.

<FIG> is a cross-sectional view or a projected side view of the semiconductor package 100A shown in <FIG>, taken along line I-I' in <FIG>. <FIG> are cross-sectional views or projected side views of the semiconductor package 100A shown in <FIG>, taken along line II-II' in <FIG>.

Referring to <FIG>, the semiconductor package 100A, 100Aa or 100Ab according to some example embodiments of the disclosure may include the interposer <NUM> disposed on the substrate <NUM>, the logic chips <NUM> and <NUM>, the memory stacks 41a to 41d and 42a to 42d, the stiffening chips 51a and 51b, and a molding compound <NUM>. The semiconductor package 100A, 100Aa or 100Ab may further include substrate bumps <NUM>, interposer bumps <NUM>, chip bumps <NUM>, and underfills <NUM> and <NUM>. The substrate bumps <NUM> may be disposed at a lower portion of the substrate <NUM>. The interposer bumps <NUM> may be disposed between the substrate <NUM> and the interposer <NUM>. The chip bumps <NUM> may be disposed between the interposer <NUM> and the logic chips <NUM> and <NUM> and between the interposer <NUM> and the memory stacks 41a to 41d and 42a to 42d. Each of the substrate bumps <NUM>, the interposer bumps <NUM> and the chip bumps <NUM> may include a solder ball or metal. The stiffening chips 51a and 51b may have a hexahedral or solid shape. In some example embodiments, the stiffening chips 51a and 52a may each include a solid dummy chip and a plurality of stacked dummy chips. That is, each of the stiffening chips 51a and 51b may include a chip stack. The stiffening chips 51a and 51b may include a portion of a silicon wafer (a silicon die), a portion of a printed circuit board, a metal or ceramic die, an epoxy compound, a solidified polymer resin, an inorganic material such as glass, and/or other hard materials.

The substrate <NUM> may have a thickness of about <NUM> to <NUM>. In some example embodiments, the substrate <NUM> may have a thickness of about <NUM>. The interposer <NUM> may be thinner than the substrate <NUM>, or, alternatively, the interposer <NUM> and the substrate <NUM> may have same thickness. For example, the interposer <NUM> may have a thickness of about <NUM> to <NUM>. In some example embodiments, the interposer <NUM> may have a thickness of about <NUM>. That is, the substrate <NUM> and the interposer <NUM> are very thin and, as such, may not provide much protection for electrical connections of the logic chips <NUM>, the memory stacks 41a to 41d and 42a to 42d, the interposer <NUM> and the substrate <NUM> from physical stress such as warpage. The diameter or vertical height of the substrate bumps <NUM> may be about <NUM> to <NUM>. In some example embodiments, the diameter or vertical height of the substrate bumps <NUM> may be about <NUM>. The diameter or vertical height of the interposer bumps <NUM> may be about <NUM> to <NUM> smaller than that of the substrate bumps <NUM>. In some example embodiments, the diameter or vertical height of the interposer bumps <NUM> may be about <NUM>. The diameter or vertical height of the chip bumps <NUM> may be about <NUM> to <NUM>. In some example embodiments, the diameter or vertical height of the chip bumps <NUM> may be about <NUM> smaller than that of the interposer bumps <NUM>. The total height of the semiconductor package 100A may be about <NUM> to <NUM>. In some example embodiments, the total height of the semiconductor package 100A may be <NUM>. The vertical height of the logic chips <NUM> and <NUM> may be about <NUM> to <NUM>. In some example embodiments, the vertical height of the logic chips <NUM> and <NUM> may be about <NUM>. Accordingly, the total vertical height of the interposer bumps <NUM>, the interposer <NUM>, the chip bumps <NUM> and the logic chips <NUM> and <NUM> may be about <NUM> to <NUM>. In some example embodiments, the total vertical height of the interposer bumps <NUM>, the interposer <NUM>, the chip bumps <NUM> and the logic chips <NUM> and <NUM> may be about <NUM>.

The semiconductor package 100A, 100Aa or 100Ab may include substrate bump pads <NUM> disposed at the lower portion of the substrate <NUM>, and interposer bump pads <NUM> disposed at an upper portion of the substrate <NUM>. The substrate bump pads <NUM> and the interposer bump pads <NUM> may be electrically connected through substrate wirings <NUM> and substrate vias <NUM>. The substrate bump pads <NUM> may contact the substrate bumps <NUM>, respectively, and, as such, may be electrically connected to an external circuit board. The interposer bump pads <NUM> may contact respective interposer bumps <NUM> and, as such, may be electrically connected to the interposer <NUM>.

The interposer <NUM> may internally include an interposer wiring <NUM> and interposer vias. The interposer wiring <NUM> and the interposer vias <NUM> may include a conductor such as metal. The interposer wiring <NUM> and the interposer vias <NUM> may electrically connect the interposer bumps <NUM> and the chip bumps <NUM>. The chip bumps <NUM> may electrically connect the interposer <NUM> and the logic chips <NUM> and <NUM> while electrically connecting the interposer <NUM> and the memory stacks 41a to 41d and 42a to 42d. For example, the upper and lower logic chips <NUM> and <NUM> may be electrically connected through the chip bumps <NUM>, the interposer wiring <NUM> and the interposer vias <NUM>, for dual processing thereof. The first to fourth upper memory chips 41a to 41d may be electrically connected to the upper logic chip <NUM> through the chip bumps <NUM>, the interposer wiring <NUM> and the interposer vias <NUM>. The first to fourth lower memory chips 42a to 42d may be electrically connected to the lower logic chip <NUM> through the chip bumps <NUM>, the interposer wiring <NUM> and the interposer vias <NUM>.

The underfills <NUM> and <NUM> may include an interposer underfill <NUM> and a chip underfill <NUM>. The interposer underfill <NUM> may be formed between the substrate <NUM> and the interposer <NUM> to surround the interposer bumps <NUM>. The interposer underfill <NUM> may provide bonding force between the substrate <NUM> and the interposer <NUM>. The chip underfill <NUM> is formed between the interposer <NUM> and the logic chips <NUM> and <NUM> and between the interposer <NUM> and the memory stacks 41a to 41d and 42a to 42d to surround the chip bumps <NUM>. The chip underfill <NUM> may provide bonding force between the interposer <NUM> and the logic chips <NUM> and <NUM> and between the interposer <NUM> and the memory stacks 41a to 41d and 42a to 42d. The underfills <NUM> and <NUM> may include a thermosetting resin.

The molding compound <NUM> may surround an upper surface of the substrate <NUM>, side and upper surfaces of the interposer <NUM>, side surfaces of the logic chips <NUM> and <NUM> and side surfaces of the memory stacks 41a to 41d and 42a to 42d. The molding compound <NUM> may be filled between the logic chips <NUM> and <NUM> and the memory stacks 41a to 41d and 42a to 42d. Upper surfaces of the logic chips <NUM> and <NUM> and the memory stacks 41a to 41d and 42a to 42d may be exposed without being covered by the molding compound <NUM>. In some example embodiments, the upper surfaces of the logic chips <NUM> and <NUM> and the memory stacks 41a to 41d and 42a to 42d may be covered by the molding compound <NUM>. The molding compound <NUM> may include an epoxy molding compound (EMC).

Referring to <FIG>, the interposer <NUM> and the stiffening chip 51a may be connected and fixed through an adhesive structure, for example, the chip bumps <NUM>. The chip bumps <NUM> between the interposer <NUM> and the stiffening chip 51a may also be surrounded by the chip underfill <NUM>. For example, when the stiffening chip 51a includes an under bumped metal (UBM), a metal pad or the like, the stiffening chip 51a, the chip bumps <NUM> and the interposer <NUM> may have physical bonding force. As described above, the chip underfill <NUM> may reinforce bonding force between the interposer <NUM> and the stiffening chip 51a.

Referring to <FIG>, the interposer <NUM> and the stiffening chip 51a may be connected and fixed through an adhesive structure, for example, an adhesive layer <NUM>. The adhesive layer <NUM> may include a curable resin having an adhesive property such as a die attach film (DAF) or a non-conductive film (NCF). When the stiffening chip 51a does not include a UBM or a metal pad, the interposer <NUM> and the stiffening chip 51a may be physically bonded and fixed by the adhesive layer <NUM>. In some example embodiments, when the stiffening chip 51a includes a dummy chip, no electrical connection may be formed between the interposer <NUM> and the stiffening chip 51a.

<FIG> is an enlarged side view of the memory stacks 41a to 41d and 42a to 42d. Referring to <FIG>, each of memory stacks 41x and 42x may include a plurality of stacked memory chips 40a to 40d, through vias <NUM>, and adhesive films <NUM>. The memory chips 40a to 40d in each of the memory stacks 41a to 41d and 42a to 42d may include nonvolatile memory chips such as dynamic random access memory (DRAM), resistive random access memory (RRAM), magneto-resistive random access memory (MRAM), phase-changeable random access memory (PRAM) and/or flash memory or other various memory chips. In some example embodiments, the memory chip of the lowermost layer, that is, the memory chip 40a, may include a base die. The base die may include a test logic circuit such as design for test (DFT), joint test action group (JTAG), or memory built-in self-test (MBIST), a signal interface circuit such as PHY, or the like.

When the lowermost memory chip 40a is a base die, the number of stacked memory chips may be <NUM> or more. In <FIG>, only three memory chips 40x are shown, although the inventive concepts are not limited thereto. The through vias <NUM> may be connected to corresponding ones of the chip bumps <NUM> while extending vertically through the memory chips 40a to 40d. The through vias <NUM> may be vertically aligned with corresponding ones of the chip bumps <NUM>. Each adhesive film <NUM> may be interposed between adjacent ones of the stacked memory chips 40a to 40d. Each adhesive film <NUM> may include a die attach film (DAF). In some example embodiments, each adhesive film <NUM> may include an underfill material.

<FIG> is a projected top view schematically showing a semiconductor package 100B according to some example embodiments of the disclosure. <FIG> is a cross-sectional view or a projected side view of the semiconductor package 100B shown in <FIG>, taken along line III-III' in <FIG>. <FIG> are cross-sectional views or projected side views of the semiconductor package 100B shown in <FIG>, taken along line IV-IV' in <FIG>.

Referring to <FIG>, the semiconductor package 100B according to some example embodiments of the disclosure may include an interposer <NUM> disposed on a substrate <NUM>, logic chips <NUM> and <NUM>, memory stacks 41a to 41d and 42a to 42d, and a stiffening dam <NUM>. The substrate <NUM>, the interposer <NUM>, the logic chips <NUM> and <NUM>, and the memory stacks 41a to 41d and 42a to 42d have been described with reference to <FIG> and, as such, no additional description thereof will be given. The stiffening dam <NUM> may be disposed on the interposer <NUM> in the form of a frame, although the stiffening dam <NUM> may be in another form, for example having a rounded cross-section. The stiffening dam <NUM> may include a portion of a silicon wafer, a portion of a printed circuit board, a metal or ceramic bar, an epoxy compound, a solidified polymer resin, an inorganic material such as glass, or other hard materials.

An upper end of the stiffening dam <NUM> may be lower than upper ends of the logic chips <NUM> and <NUM> and upper ends of the memory stacks 41a to 41d and 42a to 42d such that a molding compound <NUM> may uniformly fill an inside of the stiffening dam <NUM> and an outside of the stiffening dam <NUM>. The stiffening dam <NUM> may be bonded and fixed to an upper surface of the interposer <NUM> by an adhesive material. The stiffening dam <NUM> may have a vertical height of about <NUM> to <NUM>. In some example embodiments, the vertical height of the stiffening dam <NUM> including the adhesive material may be about <NUM>. The vertical height (thickness) of the adhesive material may be about <NUM> to <NUM>. In some example embodiments, the vertical height (thickness) of the adhesive material may be about <NUM>. Referring to <FIG>, a stiffening chip 51a may be connected and fixed to the interposer <NUM> through chip bumps <NUM> and a chip underfill <NUM>. Referring to <FIG>, the stiffening chip 51a may be bonded and fixed to the interposer <NUM> through an adhesive layer <NUM>.

<FIG> are projected top views schematically showing semiconductor packages 100Bc to 100Bf according to respective example embodiments of the disclosure. No description will be given of overlapping constituent elements.

Referring to <FIG>, the semiconductor package 100Bc according to some example embodiments of the disclosure may include stiffening dams <NUM> surrounding upper, lower and opposite lateral sides of logic chips <NUM> and <NUM>, and memory stacks 41a to 41d and 42a to 42d. Each stiffening dam <NUM> may have a bar shape, although other shapes may be used, for example a crescent shape. For example, no stiffening dam <NUM> may be disposed at corners of the interposer <NUM>.

Referring to <FIG>, the semiconductor package 100Bd according to some example embodiments of the disclosure may include stiffening dams <NUM> surrounding opposite lateral sides of logic chips <NUM> and <NUM>, and memory stacks 41a to 41d and 42a to 42d while having a bar shape. For example, the stiffening dams <NUM> disposed at upper and lower sides in <FIG> may be omitted.

Referring to <FIG>, the semiconductor package 100Be according to some example embodiments of the disclosure may include a plurality of stiffening dams <NUM> each having the form of a segment. The segment type stiffening dams <NUM> may be disposed such that a part of the stiffening dams <NUM> are aligned and overlap with an extension line of a boundary area (boundary line) between the logic chips <NUM> and <NUM> in a row direction, and the remaining part of the stiffening dams <NUM> are aligned and overlap with extension lines of boundary areas (boundary lines) between the logic chips <NUM> and <NUM> and the memory stacks 41a to 41d and 42a to 42d in a column direction, respectively.

Referring to <FIG>, the semiconductor package 100Bf according to some example embodiments of the disclosure may include segment type stiffening dams <NUM> aligned and overlapping with an extension line of a boundary area (boundary line) between the logic chips <NUM> and <NUM> in a row direction. For example, as compared to the case of <FIG>, the stiffening dams <NUM>, which are aligned and overlap with the extension lines of the boundary areas (boundary lines) between the logic chips <NUM> and <NUM> and the memory stacks 41a to 41d and 42a to 42d in the column direction, respectively, may be omitted.

<FIG> are cross-sectional views schematically showing semiconductor packages 100Ca and 100Cb according to example embodiments of the disclosure, respectively.

Referring to <FIG>, <FIG>, each of the semiconductor packages 100Ca and 100Cb according to some example embodiments of the disclosure may include an interposer <NUM> disposed on a substrate <NUM>, logic chips <NUM> and <NUM>, memory stacks 41a to 41d and 42a to 42d, stiffening chips 51a and 51b, a molding compound <NUM>, and a stiffening cover <NUM>. The stiffening cover <NUM> may cover the interposer <NUM>, the logic chips <NUM> and <NUM>, the memory stacks 41a to 41d and 42a to 42d, the stiffening chips 51a and 51b, and the molding compound <NUM>. The stiffening cover <NUM> may completely cover upper surfaces of the logic chips <NUM> and <NUM>, the memory stacks 41a to 41d and 42a to 42d, the stiffening chips 51a and 51b, and the molding compound <NUM>, and side surfaces of the molding compound <NUM>. Referring to <FIG>, the stiffening chip 51a may be connected and fixed to the interposer <NUM> through chip bumps <NUM> and a chip underfill <NUM>. Referring to <FIG>, the stiffening chip 51a may be bonded and fixed to the interposer <NUM> through an adhesive layer <NUM>.

<FIG> is a projected top view or a projected layout view of a semiconductor package 100D according to some example embodiments of the disclosure. <FIG> are cross-sectional views or projected side views of the semiconductor package 100D shown in <FIG>, taken along line V-V' in <FIG>.

Referring to <FIG>, the semiconductor package 100D, 100Da or 100Db according to some example embodiments of the disclosure may include an interposer <NUM> disposed on a substrate <NUM>, logic chips <NUM> and <NUM>, memory stacks 41a to 41d and 42a to 42d, and stiffening structures 51a, <NUM>, and <NUM>. The stiffening structures 51a, <NUM>, and <NUM> may include a stiffening chip 51a, a stiffening dam <NUM>, and a stiffening plate <NUM>. The stiffening plate <NUM> may be disposed on the logic chips <NUM> and <NUM>. The stiffening plate <NUM> may have the form of a bar or segments extending to be vertically aligned or overlap with a boundary area (boundary line) between the logic chips <NUM> and <NUM>. The stiffening plate <NUM> may include a material which is hard while exhibiting excellent thermal conductivity, such as metal. Accordingly, the stiffening plate <NUM> may additionally perform a heat dissipation function. In some example embodiments, an upper surface of the stiffening plate <NUM> may have a heat sink structure (e.g., grooves and protrusions).

Referring to <FIG>, the stiffening chip 51a may be connected and fixed to the interposer <NUM> through an adhesive structure such as chip bumps <NUM>. Referring to <FIG>, the stiffening chip 51a may be bonded and fixed to the interposer <NUM> through an adhesive structure such as an adhesive layer <NUM>. Constituent elements not described may be understood by referring to other drawings.

<FIG> are cross-sectional views schematically showing semiconductor packages 100Ea and 100Eb according to example embodiments of the disclosure, respectively. Referring to <FIG>, each of the semiconductor packages 100Ea and 100Eb according to some example embodiments of the disclosure may include an interposer <NUM> disposed on a substrate <NUM>, logic chips <NUM> and <NUM>, memory stacks 41a to 41d and 42a to 42d, a stiffening chip 51a, a stiffening dam <NUM>, a molding compound <NUM>, and a stiffening cover <NUM>. The stiffening cover <NUM> may cover the interposer <NUM>, the logic chips <NUM> and <NUM>, the memory stacks 41a to 41d and 42a to 42d, the stiffening chip 51a, and the molding compound <NUM>. The stiffening cover <NUM> may completely cover upper and side surfaces of the logic chips <NUM> and <NUM>, the memory stacks 41a to 41d and 42a to 42d, the stiffening dam <NUM>, and the molding compound <NUM>. Referring to <FIG>, the stiffening chip 51a may be connected and fixed to the interposer <NUM> through chip bumps <NUM>. Referring to <FIG>, the stiffening chip 51a may be bonded and fixed to the interposer <NUM> through an adhesive layer <NUM>. In some example embodiments, the stiffening dam <NUM> may be omitted.

<FIG> are projected top views of semiconductor packages 100Fa to 100Ff according to example embodiments of the disclosure, respectively.

Referring to <FIG>, the semiconductor package 100Fa according to one example embodiments of the disclosure may include an interposer <NUM> disposed on a substrate <NUM>, a plurality of logic chips <NUM> to <NUM>, memory stacks 41a to 41d, 42a to 42d and 43a to 43d, and stiffening chips 51a, 51b, 52a and 52b. The logic chips <NUM> to <NUM> may be disposed side-by-side to be aligned in a column direction. The memory stacks 41a to 41d, 42a to 42d and 43a to 43d may be disposed in a row direction such that each group of the memory stacks 41a to 41d, 42a to 42d and 43a to 43d is disposed adjacent to two side surfaces of a corresponding one of the logic chips <NUM> to <NUM>. For example, the memory stacks 41a to 41d, 42a to 42d and 43a to 43d may include first and second upper memory stacks 41a and 41b disposed adjacent to a first side surface of the upper logic chip <NUM>, third and fourth upper memory stacks 41c and 41d disposed adjacent to a second side surface of the upper logic chip <NUM>, first and second intermediate memory stacks 42a and 42b disposed adjacent to a first side surface of the intermediate logic chip <NUM>, third and fourth intermediate memory stacks 42c and 42d disposed adjacent to a second side surface of the intermediate logic chip <NUM>, first and second lower memory stacks 43a and 43b disposed adjacent to a first side surface of the lower logic chip <NUM>, and third and fourth lower memory stacks 43c and 43d disposed adjacent to a second side surface of the lower logic chip <NUM>.

A first upper stiffening chip 51a may be disposed between the second upper memory stack 41b and the first intermediate memory stack 42a. A second upper stiffening chip 51b may be disposed between the fourth upper memory stack 41d and the third intermediate memory stack 42c. A first upper stiffening chip 52a may be disposed between the second intermediate memory stack 42b and the first lower memory stack 43a. A second lower stiffening chip 52b may be disposed between the fourth intermediate memory stack 42d and the third lower memory stack 43c. The first and second upper memory stacks 41a and 41b, the first upper stiffening chip 51a, the first and second intermediate memory stacks 42a and 42b, the first lower stiffening chip 52a, and the first and second lower memory stacks 43a and 43b may be aligned in the column direction. The third and fourth upper memory stacks 41c and 41d, the second upper stiffening chip 51b, the third and fourth intermediate memory stacks 42c and 42d, the second lower stiffening chip 52b, and the third and fourth lower memory stacks 43c and 43d may be aligned in the column direction. Referring to <FIG>, the semiconductor package 100Fb according to some example embodiments of the disclosure may further include a stiffening dam <NUM>.

Referring to <FIG>, the semiconductor package 100Fc according to some example embodiments of the disclosure may include an interposer <NUM> disposed on a substrate <NUM>, a plurality of logic chips <NUM> to <NUM>, memory stacks 41a to 41d, 42a to 42d, 43a to 43d and 44a to 44d, and stiffening chips 51a, 51b, 52a, 52b, 53a and 53b. The logic chips <NUM> to <NUM> may be disposed side-by-side to be aligned in a column direction. Each group of the memory stacks 41a to 41d, 42a to 42d, 43a to 43d and 44a to 44d may be disposed at opposite side surfaces of a corresponding one of the logic chips <NUM> to <NUM> in a separated state. For example, the memory stacks 41a to 41d, 42a to 42d, 43a to 43d and 44a to 44d may include first and second upper memory stacks 41a and 41b disposed adjacent to a first side surface of the upper logic chip <NUM>, third and fourth upper memory stacks 41c and 41d disposed adjacent to a second side surface of the upper logic chip <NUM>, first and second intermediate upper memory stacks 42a and 42b disposed adjacent to a first side surface of the intermediate upper logic chip <NUM>, third and fourth intermediate upper memory stacks 42c and 42d disposed adjacent to a second side surface of the intermediate upper logic chip <NUM>, first and second intermediate lower memory stacks 43a and 43b disposed adjacent to a first side surface of the intermediate lower logic chip <NUM>, third and fourth intermediate lower memory stacks 43c and 43d disposed adjacent to a second side surface of the intermediate lower logic chip <NUM>, first and second lower memory stacks 44a and 44b disposed adjacent to a first side surface of the lower logic chip <NUM>, and third and fourth lower memory stacks 44c and 44d disposed adjacent to a second side surface of the lower logic chip <NUM>.

A first upper stiffening chip 51a may be disposed between the second upper memory stack 41b and the first intermediate upper memory stack 42a. A second upper stiffening chip 51b may be disposed between the fourth upper memory stack 41d and the third intermediate upper memory stack 42c. A first intermediate stiffening chip 52a may be disposed between the second intermediate upper memory stack 42b and the first intermediate lower memory stack 43a. A second intermediate stiffening chip 52b may be disposed between the fourth intermediate upper memory stack 42d and the third intermediate lower memory stack 43c. A first lower stiffening chip 53a may be disposed between the second intermediate lower memory stack 43b and the first lower memory stack 44a. A second lower stiffening chip 53b may be disposed between the fourth intermediate lower memory stack 43d and the third lower memory stack 44c. The first and second upper memory stacks 41a and 41b, the first upper stiffening chip 51a, the first and second intermediate upper memory stacks 42a and 42b, the first intermediate stiffening chip 52a, the first and second intermediate lower memory stacks 43a and 43b, the first lower stiffening chip 53a, and the first and second lower memory stacks 44a and 44b may be aligned in the column direction. The third and fourth upper memory stacks 41c and 41d, the second upper stiffening chip 51b, the third and fourth intermediate upper memory stacks 42c and 42d, the second intermediate stiffening chip 52b, the third and fourth intermediate lower memory stacks 43c and 43d, the second lower stiffening chip 52b, and the third and fourth lower memory stacks 44a and 44b may be aligned in the column direction. Referring to <FIG>, the semiconductor package 100Fd according to some example embodiments of the disclosure may further include a stiffening dam <NUM>.

Referring to <FIG>, the semiconductor package 100Fe according to some example embodiments of the disclosure may include an interposer <NUM> disposed on a substrate <NUM>, a plurality of logic chips <NUM> to <NUM>, memory stacks <NUM> to <NUM>, and stiffening chips <NUM>. For example, the logic chips <NUM> to <NUM> may be arranged in the form of a lattice or windows. The memory stacks <NUM> to <NUM> may be disposed around the logic chips <NUM> to <NUM>. For example, the memory stacks <NUM> to <NUM> may be disposed around the logic chips <NUM> to <NUM> such that four memory stacks are allocated to each logic chip. The stiffening chips <NUM> may be disposed to be aligned and overlap with extension lines of boundary areas (boundary lines) of the logic chips <NUM> to <NUM>. For example, each stiffening chip <NUM> may be disposed between corresponding ones of the memory stacks <NUM> to <NUM> while being aligned with another stiffening chip <NUM> in one of row and column directions. Referring to <FIG>, the semiconductor package 100Ff according to some example embodiments of the disclosure may further include a stiffening dam <NUM>.

Semiconductor packages according to example embodiments of the disclosure include a stiffening structure and, as such, may have superior resistance against physical stress such as warpage.

Claim 1:
A semiconductor package (100A, 100B, 100Ca, 100D, 100Ea, 100Fa) comprising:
a substrate (<NUM>);
an interposer (<NUM>) on the substrate (<NUM>); and
a first logic chip (<NUM>) and a second logic chip (<NUM>) on the interposer, the first logic chip (<NUM>) and the second logic chip (<NUM>) are side-by-side so as to be adjacent to each other;
memory stacks (41a - 41d; 42a - 42d) including a plurality of stacked memory chips, each memory stack is adjacent to a corresponding one of the first logic chip (<NUM>) and the second logic chip (<NUM>), the memory stacks on the interposer (<NUM>); and
stiffening chips (51a, 51b) on the interposer (<NUM>), the stiffening chips between corresponding ones of the memory stacks (41a - 41d; 42a - 42d), the stiffening chips (51a, 51b) adjacent to a boundary area between the first logic chip (<NUM>) and the second logic chip (<NUM>) and aligned with an extension line of said boundary area,
wherein each of the stiffening chips (51a, 51b) has a greater width than the boundary area, such that the stiffening chips are adjacent to a portion of the first logic chip (<NUM>) and a portion of the second logic chip (<NUM>) in a row direction.