Patent Description:
Radio-frequency switches (RF switches) configured to turn on and off a radio frequency (RF) are used for front ends of portable communication terminals such as mobile phones. In such radio-frequency switches, a low loss of a radio frequency passing therethrough is an important characteristic. For such a low loss, it is important to reduce a resistance (on-resistance) of an FET in an on state or a capacitance (off-capacitance, Coff) of the FET in an off state, i.e., to reduce the product (Ron*Coff) of the on-resistance and the off-capacitance.

To reduce Coff, a conventional technique is to form an air gap in the dielectric layer above the gate to reduce the parasitic capacitance between the gate and adjacent contact plugs and wires. However, the improvement effect is still limited. Therefore, there is still a need in the art for an improved semiconductor structure to further reduce Coff of the RF switches.

<CIT> discloses a semiconductor structure with an air gap.

It is one purpose of the present invention to provide an improved semiconductor structure with an air gap and a manufacturing method thereof, so as to overcome the deficiencies and disadvantages in the prior art.

One aspect of the invention provides a semiconductor structure with an air gap including a substrate; a dielectric stack comprising a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, and a third dielectric layer disposed on the second dielectric layer; a first conductive layer disposed in the dielectric stack; a second conductive layer disposed in the dielectric stack and spaced apart from the first conductive layer, wherein the first conductive layer and the second conductive layer are coplanar; a cross-like-shaped air gap disposed in the dielectric stack between the first conductive layer and the second conductive layer; an oxide layer disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap; wherein the cross-like-shaped air gap has a widened middle portion in the second dielectric layer, a tapered upper portion in the third dielectric layer, and a tapered lower portion in the first dielectric layer; and wherein the third dielectric layer comprises an extension portion that extends into the cross-like-shaped air gap and conformally covers a sidewall of the first dielectric layer adjacent to the tapered lower portion of the cross-like-shaped air gap and a sidewall of the second dielectric layer adjacent to the widened middle portion of the cross-like-shaped air gap.

According to some embodiments, the oxide layer is a silicon oxide layer.

According to some embodiments, the oxide layer has a thickness of about <NUM>-<NUM> angstroms.

According to some embodiments, the extension portion of the third dielectric layer is in direct contact with the first dielectric layer and the oxide layer.

According to some embodiments, the first conductive layer and the second conductive layer are not exposed within the cross-like-shaped air gap.

According to some embodiments, the first conductive layer and the second conductive layer comprise a copper damascened layer.

According to some embodiments, the semiconductor structure with an air gap further includes: a transistor disposed on the substrate, wherein the transistor comprises a gate, and wherein the cross-like-shaped air gap is disposed over or above the gate.

According to some embodiments, the first dielectric layer has a composition that is different from that of the second dielectric layer and the third dielectric layer.

According to some embodiments, the first dielectric layer comprises a TEOS oxide layer, and wherein the second dielectric layer and the third dielectric layer comprise a low dielectric constant (low-k) or ultra-low k material layer.

According to some embodiments, the semiconductor structure with an air gap further includes: a first capping layer between the first dielectric layer and the second dielectric layer; a second capping layer between the second dielectric layer and the third dielectric layer; and an etch stop layer between the third dielectric layer and the second capping layer.

According to some embodiments, the first capping layer and the second capping layer comprise a silicon carbide layer, and wherein the etch stop layer comprises a silicon nitride layer.

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

The following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

<FIG> is a schematic cross-sectional view of a semiconductor structure having an air gap according to an embodiment of the present invention. As shown in <FIG>, the semiconductor structure <NUM> with an air gap according to the present invention includes: a substrate <NUM>; a dielectric stack DL including a first dielectric layer <NUM> disposed on the substrate <NUM> and a second dielectric layer <NUM> disposed on the first dielectric layer <NUM> and a third dielectric layer <NUM> disposed on the second dielectric layer <NUM>. According to the embodiment of the present invention, the semiconductor structure <NUM> with an air gap further includes: a first capping layer <NUM> located between the first dielectric layer <NUM> and the second dielectric layer <NUM>; a second capping layer <NUM> located between the second dielectric layer <NUM> and the third dielectric layer <NUM>; a first etch stop layer <NUM> between the first dielectric layer <NUM> and the substrate <NUM>, and a second etch stop layer <NUM> between the third dielectric layer <NUM> and the second capping layer <NUM>.

According to an embodiment of the present invention, the substrate <NUM> may include a silicon-on-insulator (SOI) substrate <NUM> including a silicon substrate <NUM>, a buried oxide layer <NUM>, and a device layer <NUM>. The buried oxide layer <NUM> is located between the silicon substrate <NUM> and the device layer <NUM> to isolate the silicon substrate <NUM> from the device layer <NUM>. According to an embodiment of the present invention, the device layer <NUM> may comprise single crystalline silicon, for example, P-type doped single crystalline silicon, but is not limited thereto.

According to the embodiment of the present invention, the first dielectric layer <NUM> has a composition different from that of the second dielectric layer <NUM> and the third dielectric layer <NUM>. According to the embodiment of the present invention, the first dielectric layer <NUM> may include a tetraethoxysilane (TEOS) silicon oxide layer, and the second dielectric layer <NUM> and the third dielectric layer <NUM> may include a low dielectric constant (low-k) or an ultra-low dielectric constant (ultra-low k) material layer. According to an embodiment of the present invention, the first capping layer <NUM> and the second capping layer <NUM> may include a silicon carbide layer, and the first etch stop layer <NUM> and the second etch stop layer <NUM> may include a silicon nitride layer.

According to an embodiment of the present invention, a shallow trench isolation (STI) structure <NUM> is provided in the device layer <NUM>, which defines at least one active area AA, and at least one field effect transistor (FET) T is formed on the active area AA. According to an embodiment of the present invention, the field effect transistor T may include a source doped region S, a drain doped region D, a channel region CH between the source doped region S and the drain doped region D, a gate G located above the channel region CH, and a gate oxide layer GOX interposed between the gate G and the channel region CH. For example, the source doped region S and the drain doped region D may be N+ doped regions.

According to an embodiment of the present invention, the semiconductor structure <NUM> with an air gap further includes: a first conductive layer MI1 provided in the dielectric stack DL; a second conductive layer MI2 provided in the dielectric stack DL and spaced apart from the first conductive layer MI1, wherein the first conductive layer MI1 and the second conductive layer MI2 are coplanar. The first conductive layer MI1 and the second conductive layer MI2 are electrically connected to the source doped region S and the drain doped region D via the first contact plug CT1 and the second contact plug CT2, respectively. According to the embodiment of the present invention, the first contact plug CT1 and the second contact plug CT2 may include tungsten, copper, titanium, titanium nitride, or the like. According to an embodiment of the present invention, the first conductive layer MI1 and the second conductive layer MI2 may include a copper damascened layer.

According to the embodiment of the present invention, the semiconductor structure <NUM> with an air gap further includes: a cross-like-shaped air gap AG disposed in the dielectric stack DL and located between the first conductive layer MI1 and the second conductive layer MI2, wherein the cross-like-shaped air gap AG includes a widened middle portion AG_M located in the second dielectric layer <NUM>, a tapered upper portion AG_U located in the third dielectric layer <NUM>, and a tapered lower portion AG_L located in the first dielectric layer <NUM>.

According to the embodiment of the present invention, the widened middle portion AG_M has a first width W1, the tapered upper portion AG_U has a second width W2, and the tapered lower portion AG_L has a third width W3, wherein the first width W1 is larger than the second width W2 and the third width W3, and the third width W3 is smaller than or equal to the second width W2.

According to an embodiment of the present invention, the third dielectric layer <NUM> includes an extension portion 113e extending into the cross-like-shaped air gap AG and conformally covering the sidewall of the first dielectric adjacent layer <NUM> adjacent to the tapered lower portion AG_L of the cross-like-shaped air gap AG and the sidewall of the second dielectric layer <NUM> adjacent to the widened middle portion AG_M of the cross-like-shaped air gap AG. According to an embodiment of the present invention, the extension portion 113e of the third dielectric layer <NUM> is in direct contact with the first dielectric layer <NUM>. According to the embodiment of the present invention, the first conductive layer MI1 and the second conductive layer MI2 are not exposed in the cross-like-shaped air gap AG.

<FIG> illustrates a cross-sectional profile of a cross-like-shaped air gap according to another embodiment. As shown in <FIG>, the cross-like-shaped air gap AG also includes a widened middle portion AG_M located in the second dielectric layer <NUM>, a tapered upper portion AG_U located in the third dielectric layer <NUM>, and a tapered lower portion AG_L located in the first dielectric layer <NUM>. The cross-like-shaped air gap AG of <FIG> is different from the cross-like-shaped air gap AG of <FIG> in that the tapered upper portion AG_U of the cross-like-shaped air gap AG of <FIG> is relatively sharp, and the tapered lower AG_L is relatively blunt or flat. In addition, the length L2 of the tapered upper portion AG_U in the vertical direction is less than or equal to the length L3 of the tapered lower portion AG_L in the vertical direction.

<FIG> is a schematic cross-sectional view of a semiconductor structure having an air gap according to another embodiment of the present invention. The same elements, regions, or layers are still represented by the same symbols or numeral numbers. As shown in <FIG>, another aspect of the present invention provides a semiconductor structure 1a having an air gap, including: a substrate <NUM>; a dielectric stack DL including a first dielectric layer <NUM> disposed on the substrate <NUM>, a second dielectric layer <NUM> disposed on the first dielectric layer <NUM> and a third dielectric layer <NUM> disposed on the second dielectric layer <NUM>. The semiconductor structure 1a with an air gap further includes: a first conductive layer MI1 provided in the dielectric stack DL; a second conductive layer MI2 provided in the dielectric stack DL and spaced apart from the first conductive layer MI1. The first conductive layer MI1 and the second conductive layer MI2 are coplanar.

According to the embodiment of the present invention, the semiconductor structure 1a having an air gap further includes: a cross-like-shaped air gap AG disposed in the dielectric stack DL and located between the first conductive layer MI1 and the second conductive layer MI2. According to the embodiment of the present invention, the semiconductor structure 1a having an air gap further includes: an oxide layer 112t disposed on the sidewall <NUM> of the second dielectric layer <NUM> in the cross-like-shaped air gap AG. According to an embodiment of the present invention, the oxide layer <NUM> is a silicon oxide layer. According to an embodiment of the present invention, the thickness of the oxide layer 112t is between <NUM> and <NUM> angstroms.

According to the embodiment of the present invention, the cross-like-shaped air gap AG also includes a widened middle portion AG_M located in the second dielectric layer <NUM>, a tapered upper portion AG_U located in the third dielectric layer <NUM>, and a tapered lower portion AG_L located In the first dielectric layer <NUM>. According to an embodiment of the present invention, the third dielectric layer <NUM> includes an extension portion 113e extending into the cross-like-shaped air gap AG and conformally covering the sidewall of the first dielectric adjacent layer <NUM> adjacent to the tapered lower portion AG_L of the cross-like-shaped air gap AG and the sidewall <NUM> of the second dielectric layer <NUM> adjacent to the widened middle portion AG_M of the cross-like-shaped air gap AG. According to an embodiment of the present invention, the extension portion 113e of the third dielectric layer <NUM> is in direct contact with the first dielectric layer <NUM>. According to an embodiment of the present invention, the extension portion 113e of the third dielectric layer <NUM> is in direct contact with the first dielectric layer <NUM> and the oxide layer 112t.

According to the embodiment of the present invention, the first conductive layer MI1 and the second conductive layer MI2 are not exposed in the cross-like-shaped air gap AG. According to an embodiment of the present invention, the first conductive layer MI1 and the second conductive layer MI2 include a copper damascened layer.

According to the embodiment of the present invention, the substrate <NUM> may include an SOI substrate, but is not limited thereto. According to the embodiment of the present invention, the semiconductor structure 1a with an air gap further includes: a transistor T disposed on the substrate <NUM>, wherein the transistor T includes a gate G, and the cross-like-shaped air gap AG is disposed over or above the gate G.

Although the cross-like-shaped air gap AG shown in the figures is positioned directly over the gate G, it is to be understood that in some embodiments the cross-like-shaped air gap AG may be positioned above the gate G with an offset with respect to the underlying gate G.

According to the embodiment of the present invention, the first dielectric layer <NUM> has a composition different from that of the second dielectric layer <NUM> and the third dielectric layer <NUM>. According to the embodiment of the present invention, the first dielectric layer <NUM> includes a TEOS silicon oxide layer, wherein the second dielectric layer <NUM> and the third dielectric layer <NUM> include a low dielectric constant or ultra-low dielectric constant material layer.

According to the embodiment of the present invention, the semiconductor structure 1a with an air gap further includes: a first capping layer <NUM> located between the first dielectric layer <NUM> and the second dielectric layer <NUM>; a second capping layer <NUM> located between the second dielectric layer <NUM> and the third dielectric layer <NUM>; a first etch stop layer <NUM> located between the first dielectric layer <NUM> and the substrate <NUM>; and a second etch stop layer <NUM> located between the third dielectric layer <NUM> and the second capping layer <NUM>. According to an embodiment of the present invention, the first capping layer <NUM> and the second capping layer <NUM> include a silicon carbide layer, and the first etch stop layer <NUM> and the second etch stop layer <NUM> include a silicon nitride layer.

Those skilled in the art should understand that the structures depicted throughs <FIG> are for illustration purposes only. In other embodiments, the air gap AG may also extend to the upper dielectric layer or be located between the upper metal layers to achieve the purposes of further reducing the parasitic capacitance between wires.

Please refer to <FIG>, which are schematic cross-sectional views showing a method for fabricating a semiconductor structure with an air gap according to an embodiment of the present invention. The same elements, regions or layers are still represented by the same symbols or numeral numbers. As shown in <FIG>, a substrate <NUM> such as a semiconductor substrate is first provided. According to an embodiment of the present invention, the substrate <NUM> may be an SOI substrate including a silicon substrate <NUM>, a buried oxide layer <NUM>, and a device layer <NUM>. The buried oxide layer <NUM> is located between the silicon substrate <NUM> and the device layer <NUM> to isolate the silicon substrate <NUM> from the device layer <NUM>. According to an embodiment of the present invention, the device layer <NUM> may be single crystalline silicon, for example, P-type doped single crystalline silicon, but is not limited thereto.

According to an embodiment of the present invention, a shallow trench isolation structure <NUM> is provided in the device layer <NUM>, which defines at least one active area AA, and at least one field effect transistor T is formed on the active area AA. According to an embodiment of the present invention, the field effect transistor T may include a source doped region S, a drain doped region D, a channel region CH between the source doped region S and the drain doped region D, a gate G located above the channel region CH, and a gate oxide layer GOX interposed between the gate G and the channel region CH. For example, the source doped region S and the drain doped region D may be N+ doped regions.

According to an embodiment of the present invention, a chemical vapor deposition (CVD) process may be carried out to sequentially form a first etch stop layer <NUM>, a first dielectric layer <NUM>, a first capping layer <NUM>, a second dielectric layer <NUM>, and a second capping layer <NUM> on the substrate <NUM>. According to an embodiment of the present invention, a first contact plug CT1 and a second contact plug CT2 may be formed in the first etch stop layer <NUM> and the first dielectric layer <NUM>. A first conductive layer MI1 and a second conductive layer MI2 are formed in the first capping layer <NUM>, the second dielectric layer <NUM> and the second capping layer <NUM> above the first contact plug CT1 and a second contact plug CT2, respectively.

According to an embodiment of the invention, the first conductive layer MI1 and the second conductive layer MI2 are coplanar. According to an embodiment of the invention, the first conductive layer MI1 is spaced apart from the second conductive layer MI2. According to an embodiment of the present invention, the first conductive layer MI1 and the second conductive layer MI2 include a copper damascened layer. According to an embodiment of the present invention, the first dielectric layer <NUM> may include a TEOS silicon oxide layer, and the second dielectric layer <NUM> may include a low dielectric constant or ultra-low dielectric constant material layer. According to an embodiment of the present invention, the first capping layer <NUM> and the second capping layer <NUM> may include a silicon carbide layer, and the first etch stop layer <NUM> may include a silicon nitride layer.

Subsequently, a second etch stop layer <NUM> may be formed on the second capping layer <NUM>, the first conductive layer MI1, and the second conductive layer MI2. Then, a pattern transfer layer <NUM>, for example, a hard mask layer <NUM> and an anti-reflection layer <NUM>, may be formed on the second etch stop layer <NUM>. According to an embodiment of the present invention, the second etch stop layer <NUM> may include a silicon nitride layer. According to the embodiment of the present invention, the hard mask layer <NUM> may include a titanium nitride layer, but is not limited thereto. According to the embodiment of the present invention, the anti-reflection layer <NUM> may include a silicon oxynitride layer and/or a silicon oxide layer, but is not limited thereto. A patterned photoresist layer <NUM> is then formed on the anti-reflection layer <NUM>, which includes an opening 150a to expose a part of the anti-reflection layer <NUM>. According to an embodiment of the present invention, the opening 150a is located on the first conductive layer MI1 and the second conductive layer MI2, and is located over or above the gate G.

As shown in <FIG>, an etching process, for example, an anisotropic dry etching process, is performed. The anti-reflection layer <NUM> and the hard mask layer <NUM> are etched downward through the opening 150a of the patterned photoresist layer <NUM> to form an opening 140a. Then, the patterned photoresist layer <NUM> is removed, so that the pattern of the patterned photoresist layer <NUM> can be transferred to the pattern transfer layer <NUM>.

As shown in <FIG>, next, the pattern transfer layer <NUM> is used as an etching resist mask, and another etching process is performed, for example, an anisotropic dry etching process. The second etch stop layer <NUM>, the second capping layer <NUM>, the second dielectric layer <NUM>, the first capping layer <NUM> and the first dielectric layer <NUM> are etched downward through the opening 140a of the pattern transfer layer <NUM>, thereby forming a first trench RT1. According to an embodiment of the present invention, the above-mentioned etching process is stopped in the first dielectric layer <NUM>, so the bottom of the first trench RT1 is the first dielectric layer <NUM>, and the first etch stop layer <NUM> is not exposed. In the first trench RT1, the sidewall <NUM> of the second dielectric layer <NUM> is exposed.

Subsequently, the pattern transfer layer <NUM> is removed, and the second etch stop layer <NUM> is exposed. Although the bottom of the first trench RT1 in <FIG> is a flat surface, in other embodiments, the bottom of the first trench RT1 may be a curved surface, as shown in <FIG>, such a bottom having a curved contour can be achieved by controlling the etching parameters.

Next, as shown in <FIG>, an oxygen plasma treatment process and a dilute hydrofluoric acid (DHF) solution wet etching process are performed. The second dielectric layer <NUM> composed of a low dielectric constant material contacts the oxygen plasma may be etched laterally to form a middle-widened second trench RT2. The sidewall <NUM> of the second dielectric layer <NUM> is recessed inward (toward the first conductive layer MI1 and the second conductive layer MI2, respectively).

At the same time, the above-mentioned oxygen plasma treatment process will form an oxide layer 112t on the sidewall <NUM> of the second dielectric layer <NUM>. According to an embodiment of the present invention, for example, the oxide layer 112t is a silicon oxide layer, and its thickness is between <NUM> and <NUM> angstroms, for example, between <NUM> and <NUM> angstroms. This oxide layer 112t can prevent water or moisture from diffusing into the second dielectric layer <NUM> and making contact with the first conductive layer MI1 and the second conductive layer MI2.

As shown in <FIG>, finally, a chemical vapor deposition (CVD) process or other methods may be performed. A third dielectric layer <NUM> is deposited on the second etch stop layer <NUM> and an interior surface of the second trench RT2. The upper opening of the second trench RT2 is sealed to form a cross-like-shaped air gap AG. According to the embodiment of the present invention, the cross-like-shaped air gap AG includes a widened middle portion AG_M located in the second dielectric layer <NUM>, a tapered upper portion AG_U located in the third dielectric layer <NUM>, and a tapered lower portion AG_L located in the first dielectric layer <NUM>.

Claim 1:
A semiconductor structure with an air gap, comprising:
a substrate (<NUM>, <NUM>);
a dielectric stack comprising a first dielectric layer (<NUM>) disposed on the substrate (<NUM>, <NUM>), a second dielectric layer (<NUM>) disposed on the first dielectric layer (<NUM>), and a third dielectric layer (<NUM>) disposed on the second dielectric layer (<NUM>);
a first conductive layer disposed in the dielectric stack;
a second conductive layer disposed in the dielectric stack and spaced apart from the first conductive layer, wherein the first conductive layer and the second conductive layer are coplanar;
a cross-like-shaped air gap disposed in the dielectric stack between the first conductive layer and the second conductive layer;
an oxide layer (112t) disposed on a sidewall (<NUM>) of the second dielectric layer (<NUM>) within the cross-like-shaped air gap;
wherein the cross-like-shaped air gap has a widened middle portion in the second dielectric layer (<NUM>), a tapered upper portion in the third dielectric layer (<NUM>), and a tapered lower portion in the first dielectric layer (<NUM>); and
wherein the third dielectric layer (<NUM>) comprises an extension portion (113e) that extends into the cross-like-shaped air gap and conformally covers a sidewall (<NUM>) of the first dielectric layer (<NUM>) adjacent to the tapered lower portion of the cross-like-shaped air gap and a sidewall (<NUM>) of the second dielectric layer (<NUM>) adjacent to the widened middle portion of the cross-like-shaped air gap.