Patent Description:
Embodiments of the present invention relate to the field of memory technologies, in particular to a storage cell and a data read/write method and storage array thereof.

A non-volatile magnetic random access memory (MRAM) is a random access memory which stores data according to resistive properties of memory. It uses different memory resistance values caused by different magnetization directions to record data. However, with the development of science and technology and the gradual increase of storage density, how to further improve the comprehensive performance and the integration of the MRAM under the condition of ensuring the writing (or programming) driving capability of the MRAM has become an urgent technical problem to be solved at present.

<CIT> discloses a variable resistance memory and a method of controlling the same. <CIT> discloses a semiconductor storage device.

With respect to the above existing problems, embodiments of the present invention provide a storage cell and a data read/write method and storage array thereof, so as to reduce the size of the storage cell and improve the integration of the storage array including the storage cell.

In a first aspect, the embodiments of the present invention provide a storage cell according to independent claim <NUM>. According to embodiments, the storage cell is according to any one of dependent claims <NUM> to <NUM>.

In a second aspect, the embodiments of the present invention further provide a data read/write method according to independent claim <NUM>. According to embodiments, the data read/write method is according to dependent claim <NUM>.

In a third aspect, the embodiments of the present invention further provide a storage array according to dependent claim <NUM>. According to embodiments, the storage array is according to any one of dependent claims <NUM> to <NUM>.

According to the storage cell and the data read/write method and storage array thereof provided in the embodiments of the present invention, the long-side extension directions of the active regions of the access transistors in the storage cell are configured to be at a first angle θ with the extension direction of the bit line, with the angle Θ ≠ n·(π/<NUM>), n being a natural number <IMG> <NUM>, that is, the active regions of the access transistors are inclined, which enables the access transistors to be densely arranged and is conducive to reducing the size of the storage cell, so that the integration of the storage array can be improved when the storage cell is applied to the storage array.

Only embodiments comprising all the features of independent device claim <NUM> or of independent method claim <NUM> fall under the scope of protection of the present invention.

The present invention is described in further detail below with reference to the accompanying drawings and embodiments. In addition, it should be further noted that, to facilitate description, only some of rather than all of the structures relevant to the present invention are shown in the drawings.

An embodiment of the present invention provides a storage cell that is a non-volatile magnetic storage cell and can be arranged in an MRAM. <FIG> is a schematic structural diagram of an equivalent circuit of a storage cell according to an embodiment of the present invention, and <FIG> is a schematic top view of a storage cell according to an embodiment of the present invention. Referring to <FIG>, a storage cell <NUM> includes a bit line BL, a tunnel junction <NUM>, and four access transistors (<NUM>, <NUM>, <NUM>, <NUM>). The storage cell <NUM> further includes active regions (<NUM>, <NUM>, <NUM>, <NUM>), that is, the access transistor <NUM> is located in the active region <NUM>, the access transistor <NUM> is located in the active region <NUM>, the access transistor <NUM> is located in the active region <NUM>, and the access transistor <NUM> is located in the active region <NUM>. Sources of the access transistors (<NUM>, <NUM>, <NUM>, <NUM>) are all electrically connected to a first end of the tunnel junction <NUM>; and a second end of the tunnel junction <NUM> is electrically connected to the bit line BL. In this way, a magnetization direction of a free layer in the tunnel junction <NUM> can be controlled to change by inputting corresponding electrical signals to the two ends of the tunnel junction <NUM> respectively, so that data signals can be written into the storage cell. Alternatively, data stored in the storage cell <NUM> is read by inputting corresponding electrical signals to the second end of the tunnel junction <NUM> and controlling the access transistors (<NUM>, <NUM>, <NUM>, <NUM>) to switch on. At the same time, since the storage cell <NUM> includes four access transistors (<NUM>, <NUM>, <NUM>, <NUM>) and the sources of the access transistors (<NUM>, <NUM>, <NUM>, <NUM>) are all electrically connected to the first end of the tunnel junction <NUM>, the four access transistors (<NUM>, <NUM>, <NUM>, <NUM>) can be controlled to switch on simultaneously when the data signals are written, so that the four access transistors (<NUM>, <NUM>, <NUM>, <NUM>) all can transmit electrical signals to the first end of the tunnel junction <NUM>, to enable the first end of the tunnel junction <NUM> to receive strong electrical signals, which increases the driving (writing or programming) capability and is conducive to the storage of the data signals. The access transistors (<NUM>, <NUM>, <NUM>, <NUM>) each may further include a gate.

Still referring to <FIG>, the bit line BL of the storage cell <NUM> extends along a first direction Y. In this case, the active regions (<NUM>, <NUM>, <NUM>, <NUM>) corresponding to the access transistors (<NUM>, <NUM>, <NUM>, <NUM>) are isolated from each other, that is, the active region <NUM> corresponding to the access transistor <NUM>, the active region <NUM> corresponding to the access transistor <NUM>, the active region <NUM> corresponding to the access transistor <NUM>, and the active region <NUM> corresponding to the access transistor <NUM> are isolated fromeach other. At the same time, long-side extension directions of the active region <NUM> corresponding to the access transistor <NUM>, the active region <NUM> corresponding to the access transistor <NUM>, the active region <NUM> corresponding to the access transistor <NUM>, and the active region <NUM> corresponding to the access transistor <NUM> are the same, and a first angle θ is formed between the long-side extension directions P of the active region <NUM> corresponding to the access transistor <NUM>, the active region <NUM> corresponding to the access transistor <NUM>, the active region <NUM> corresponding to the access transistor <NUM>, the active region <NUM> corresponding to the access transistor <NUM> and the first direction Y; wherein θ≠n(π/<NUM>), and n is a natural number, that is, θ is a non-right angle. In this way, the first angle θ between the long-side extension directions of the active regions of the access transistor and the extension direction of the bit line is set to an integer multiple of non-<NUM>°, so that the tunnel junction and the four access transistors are closely arranged, so as to reduce the size of the storage cell, which is conducive to improving the integration of the storage cell in the storage array.

Illustratively, still referring to <FIG>, when the four access transistors are the first access transistor <NUM>, the second access transistor <NUM>, the third access transistor <NUM>, and the fourth access transistor <NUM> respectively, a long side of the active region <NUM> of the first access transistor <NUM> is disposed opposite to a long side of the active region <NUM> of the second access transistor <NUM>, and the active region <NUM> of the third access transistor <NUM> and the active region <NUM> of the fourth access transistor <NUM> are located between the active region <NUM> of the first access transistor <NUM> and the active region <NUM> of the second access transistor <NUM>; and a short side of the active region <NUM> of the third access transistor <NUM> is disposed opposite to a short side of the active region <NUM> of the fourth access transistor <NUM>.

Optionally, still referring to <FIG>, when the four access transistors are the first access transistor <NUM>, the second access transistor <NUM>, the third access transistor <NUM>, and the fourth access transistor <NUM> respectively, an orthographic projection of the tunnel junction <NUM> in a film layer where the active region of each access transistor is located covers at least a partial region between the active region <NUM> of the first access transistor <NUM> and the active region <NUM> of the second access transistor <NUM>, and covers at least a partial region between the active region <NUM> of the third access transistor <NUM> and the active region <NUM> of the fourth access transistor <NUM>, thus facilitating electrical connections between the access transistors (<NUM>, <NUM>, <NUM>, <NUM>) and the first end of the tunnel junction.

Optionally, still referring to <FIG>, the storage cell <NUM> may also be provided with a connection structure <NUM>. An orthographic projection of the connection structure <NUM> in the active region of each access transistor overlaps with the active regions of the four access transistors; and the sources of the access transistors are all electrically connected to the first end of the tunnel junction <NUM> through the connection structure <NUM>.

Specifically, when the four access transistors are the first access transistor <NUM>, the second access transistor <NUM>, the third access transistor <NUM>, and the fourth access transistor <NUM> respectively, an orthographic projection of the connection structure <NUM> in the active region of each access transistor overlaps with the active region of the first access transistor <NUM>, the active region of the second access transistor <NUM>, the active region of the third access transistor <NUM>, and the active region of the fourth access transistor <NUM>. In this case, through an electrical contact structure such as a plug, one side of the connection structure <NUM> may be electrically connected to the source of the first access transistor <NUM>, the source of the second access transistor <NUM>, the source of the third access transistor <NUM>, and the source of the fourth access transistor <NUM> respectively, and the other side of the connection structure <NUM> may be directly or indirectly electrically connected to the first end of the tunnel junction <NUM>. In this way, the source of the first access transistor <NUM>, the source of the second access transistor <NUM>, the source of the third access transistor <NUM>, and the source of the fourth access transistor <NUM> can be all electrically connected to the first end of the tunnel junction <NUM> through the connection structure <NUM>, thus simplifying the design, reducing the cost, and improving a product yield.

Optionally, the storage cell further includes at least one word line and at least one source line; the word line extending along a second direction; wherein the first direction intersects with the second direction. In this case, each access transistor further includes a channel region and a drain, and the source and the drain are located on two opposite sides of the channel region respectively; gates of the access transistors are electrically connected to the word line; and the drains of the access transistors are electrically connected to the source line.

In the present specific embodiment, in each access transistor, what is electrically connected to the tunnel junction <NUM> through the connection structure <NUM> is called as a source and what is electrically connected to the source line is called as a drain. This is intended only to make it easy to distinguish two electrodes in the access transistor, so as to more clearly describe the structure of the storage cell provided in the present specific embodiment, and does not thereby limit the protection scope. Those skilled in the art may also, according to an actual requirement, to call, in each access transistor, what is electrically connected to the tunnel junction <NUM> through the connection structure <NUM> as a drain and correspondingly call what is electrically connected to the source line as a source.

Illustratively, <FIG> is a schematic top view of another storage cell according to an embodiment of the present invention. Referring to <FIG> and <FIG>, the four access transistors of the storage cell <NUM> are the first access transistor <NUM>, the second access transistor <NUM>, the third access transistor <NUM>, and the fourth access transistor <NUM> respectively. The at least one word line of the storage cell <NUM> may include a first word line WL1, a second word line WL2, and a third word line WL3, and the first word line WL1, the second word line WL2, and the third word line WL3 are sequentially arranged along the first direction, that is, the first word line WL1, the second word line WL2, and the third word line WL3 are arranged along the extension direction of the bit line BL. The gate of the third access transistor <NUM> is electrically connected to the first word line WL1; the gate of the first access transistor <NUM> and the gate of the second access transistor <NUM> are both electrically connected to the second word line WL2; and the gate of the fourth access transistor <NUM> is electrically connected to the third word line WL3.

In this case, an orthographic projection of the first word line WL1 in the active region of each access transistor overlaps with the active region <NUM> of the first access transistor <NUM> and the active region <NUM> of the third access transistor <NUM>; an orthographic projection of the second word line WL2 in the active region of each access transistor overlaps with the active region <NUM> of the first access transistor <NUM> and the active region <NUM> of the second access transistor <NUM>; and an orthographic projection of the third word line WL3 in the active region of each access transistor overlaps with the active region <NUM> of the fourth access transistor <NUM> and the active region <NUM> of the second access transistor <NUM>.

In this way, a gate control signal transmitted by the first word line WL1 can control the source and the drain of the third access transistor <NUM> to connect, a gate control signal transmitted by the second word line WL2 can control the source and the drain of the first access transistor <NUM> to connect and the source and the drain of the second access transistor <NUM> to connect, and a gate control signal transmitted by the third word line WL3 can control the source and the drain of the fourth access transistor <NUM> to connect, so that data signals can be transmitted to the first end of the tunnel junction <NUM> through the ON access transistors, or data signals stored in the tunnel junction <NUM> can be output through the ON access transistors. Channel doping types of the four access transistors may be the same, so that the first word line WL1, the second word line WL2, and the third word line WL3 transmit the same gate control signal, enabling the sources and the drains of the first access transistor <NUM>, the second access transistor <NUM>, the third access transistor <NUM>, and the fourth access transistor <NUM> to be simultaneous controlled to switch on. At the same time, the bit line BL and the word lines (WL1, WL2, WL3) may be straight lines, the bit line BL may extend along the first direction Y, and the word lines (WL1, WL2, WL3) may extend a second direction X perpendicular to the first direction Y.

Correspondingly, the at least one source line of the storage cell <NUM> may include a first source line SL1, a second source line SL2, and a third source line SL3, the first source line SL1, the second source line SL2, and the third source line SL3 extend in the same direction, the first source line SL1, the second source line SL2, and the third source line SL3 are sequentially arranged along the first direction Y, that is, the first source line SL1, the second source line SL2, and the third source line SL3 are arranged in the same direction as the first word line WL1, the second word line WL2, and the third word line WL3. When the source of the access transistor in the storage cell <NUM> is the source of the access transistor and the drain of the access transistor is the drain of the access transistor, the drain of the third access transistor <NUM> may be electrically connected to the first source line SL1, and the drain of the first access transistor <NUM> and the drain of the second access transistor <NUM> may be both electrically connected to the second source line SL2; and the drain of the fourth access transistor <NUM> may be electrically connected to the third source line SL3.

In this case, an orthographic projection of the first source line SL1 in the active region of each access transistor overlaps with the drain of the third access transistor <NUM>; an orthographic projection of the second source line SL2 in the active region of each access transistor overlaps with both the drain of the first access transistor <NUM> and the drain of the second access transistor <NUM>; and an orthographic projection of the second source line SL2 in a film layer where the active region of each access transistor is located further overlaps with an orthographic projection of the tunnel junction <NUM> in the film layer where the active region of each access transistor is located; and an orthographic projection of the third source line SL3 in the active region of each access transistor overlaps with the drain of the fourth access transistor <NUM>.

In this way, when the source and the drain of the third access transistor <NUM> are controlled to be on, a data signal transmitted by the first source line SL1 can be transmitted to the first end of the tunnel junction <NUM> sequentially through the source and the drain of the third access transistor <NUM>, or a data signal stored in the tunnel junction <NUM> can be output sequentially through the source and the drain of the third access transistor <NUM> and the first source line SL1. When the source and the drain of the first access transistor <NUM> are controlled to be on, a data signal transmitted by the second source line SL2 can be transmitted to the first end of the tunnel junction <NUM> sequentially through the source and the drain of the first access transistor <NUM>, or a data signal stored in the tunnel junction <NUM> can be output sequentially through the source and the drain of the first access transistor <NUM> and the second source line SL2. When the source and the drain of the second access transistor <NUM> are controlled to be on, a data signal transmitted by the second source line SL2 can be transmitted to the first end of the tunnel junction <NUM> sequentially through the source and the drain of the second access transistor <NUM>, or a data signal stored in the tunnel junction <NUM> can be output sequentially through the source and the drain of the second access transistor <NUM> and the second source line SL2. When the source and the drain of the fourth access transistor <NUM> are controlled to be on, a data signal transmitted by the third source line SL3 can be transmitted to the first end of the tunnel junction <NUM> sequentially through the source and the drain of the fourth access transistor <NUM>, or a data signal stored in the tunnel junction <NUM> can be output sequentially through the source and the drain of the fourth access transistor <NUM> and the third source line SL3.

Optionally, when the storage cell includes an access transistor, a tunnel junction, a bit line, a word line, and a source line, corresponding functional film layer can be formed on a substrate. The substrate may be, for example, a silicon substrate or the like. For example, <FIG> is a schematic structural diagram of a film layer of a cross section A-A' in <FIG>. As shown in <FIG>, the storage cell <NUM> may include a substrate <NUM>. The substrate <NUM> may be, for example, a silicon-based substrate. The active regions of the access transistors are isolated from each other by forming shallow trench isolation (STI) <NUM> in a particular region of the substrate <NUM>. It should be noted that, the STI in <FIG> is only illustrative, and its actual structure and size may also be set by those skilled in the art according to a requirement. The active regions (<NUM> and <NUM>) of the access transistors are provided with trenches, and part of the word line (WL2) is located in the trenches of the active regions (<NUM> and <NUM>) of the access transistors, so that the word lines in the trenches can serve as gates of the access transistors. In this case, side walls of the trenches may be provided with corresponding insulation materials, that is, gate insulation layers, so that the gates of the access transistor and channel regions of the active regions thereof are isolated from each other. It should be noted that, the gates in the figure are only illustrative, an actual height of the gates in the trenches may be designed differently due to an actual requirement, which is not limited in the present embodiment and is not limited to the form of a buried-gate transistor, and may also be in a non-buried gate form, such as a planar transistor or a vertical-gate transistor. The source line (SL2) is located on one side of the word line (WL2) away from the substrate <NUM>, and the source line (SL2) may be electrically connected to the drain of the access transistor through a corresponding connection through-hole. The connection structure <NUM> is located on one side of the source line (SL2) away from the substrate <NUM>; in this case, the connection structure <NUM> may be electrically connected to the source of the access transistor through a corresponding plug or connection through-hole or the like. The tunnel junction <NUM> is located on one side of the connection structure <NUM> away from the substrate <NUM>, that is, the first end of the tunnel junction <NUM> may be in direct contact with the connection structure <NUM>, so as to be electrically connected to the source of each access transistor through the connection structure. <FIG> shows a situation where the first end of the tunnel junction <NUM> is in direct contact with the connection structure <NUM>, but the present embodiments is not limited thereto, and those skilled in the art can set a form of indirect electrical connection according to a requirement. The bit line BL is located on one side of the tunnel junction <NUM> away from the substrate <NUM>, that is, the bit line BL may be in direct contact with the second end of the tunnel junction <NUM>, to make the bit line BL directly electrically connected to the second end of the tunnel junction <NUM>. Similarly, the bit line BL may also be indirectly electrically connected to the tunnel junction <NUM>, which is not limited in the present embodiment.

An embodiment of the present invention further provides a data read/write method of a storage cell. The data read/write method may be performed by the storage cell provided in the embodiment of the present invention. Therefore, the data read/write method of the storage cell has beneficial effects of the storage cell provided in the embodiment of the present invention. The same content may be obtained with reference to the above description about the storage cell provided in the embodiment of the present invention, and is not described in detail herein.

Correspondingly, the storage cell includes at least a bit line, a tunnel junction, and four access transistors. Each access transistor includes a source, a drain, and a channel region, and the source and the drain are located on two opposite sides of the channel region respectively. Each access transistor further includes a gate. <FIG> is a flowchart of a data read/write method of a storage cell according to an embodiment of the present invention. As shown in <FIG>, the data read/write method of the storage cell includes: a data write phase S110 and a data read phase S120. The data write phase includes a first write operation and/or a second write operation.

In S110, the second end of the tunnel junction receives a high-level signal transmitted by the bit line, the drain of the access transistor receives a low-level signal, and the gate of each access transistor receives a gate control signal and controls the source and the drain of each access transistor to connect, to perform a first write operation; and/or the second end of the tunnel junction receives a low-level signal transmitted by the bit line, the drain of the access transistor receives a high-level signal, and the gate of each access transistor receives a gate control signal and controls the source and the drain of each access transistor to connect, to perform a second write operation.

In S120, the second end of the tunnel junction receives a high-level signal transmitted by the bit line, the drain of the access transistor receives a low-level signal, and the gate of each access transistor receives a gate control signal to control the source and the drain of each access transistor to connect, to perform a read operation.

Illustratively, taking the storage cell shown in <FIG> and <FIG> as an example, channel doping type of the four access transistors of the storage cell are the samein this case. For example, the channel doping types of the four access transistors of the storage cell are all N-type. In this case, the access transistors may receive the same gate control signal. <FIG> is a timing diagram of a data read/write method of a storage cell according to an embodiment of the present invention. Referring to <FIG>, <FIG>, and <FIG>, the data write phase includes a write phase of data "<NUM>" and a write phase of data "<NUM>". In the write phase t1 of data "<NUM>", high-level gate control signals W1, W2, and W3 transmitted by the word lines WL1, WL2, and WL3 are transmitted to the gates of the access transistors <NUM>, <NUM>, <NUM>, and <NUM> respectively, to enable the sources and the drains of the access transistors to switch on. In this case, low-level signals S1, S2, and S3 transmitted by the source lines SL1, SL2, and SL3 are transmitted to the first end of the tunnel junction <NUM> respectively through the sources and the drains of the access transistors <NUM>, <NUM>, <NUM>, and <NUM>. At the same time, the second end of the tunnel junction <NUM> may receive a high-level read/write signal B transmitted by the bit line BL, so that magnetization directions of a free layer and a fixed layer between the first end and the second end of the tunnel junction <NUM> are parallel, and the tunnel junction presents a low-resistance state. In the write phase t3 of data "<NUM>", high-level gate control signals W1, W2, and W3 transmitted by the word lines WL1, WL2, and WL3 are transmitted to the gates of the access transistors <NUM>, <NUM>, <NUM>, and <NUM> respectively, to enable the sources and the drains of the access transistors to connect. In this case, high-level signals S1, S2, and S3 transmitted by the source lines SL1, SL2, and SL3 are transmitted to the first end of the tunnel junction <NUM> respectively through the sources and the drains of the access transistors <NUM>, <NUM>, <NUM>, and <NUM>. At the same time, the second end of the tunnel junction <NUM> may receive a low-level read/write signal B transmitted by the bit line BL, so that magnetization directions of a free layer and a fixed layer between the first end and the second end of the tunnel junction <NUM> are antiparallel, and the tunnel junction presents a high-resistance state. Certainly, those skilled in the art should understand that, the present embodiment does not specify that "<NUM>" corresponds to the low-resistance state and "<NUM>" to the high resistance state, or vice versa.

Correspondingly, in the data read phase t5, high-level gate control signals W1, W2, and W3 transmitted by the word lines WL1, WL2, and WL3 are transmitted to the gates of the access transistors <NUM>, <NUM>, <NUM>, and <NUM> respectively, to enable the sources and the drains of the access transistors to connect. At the same time, the second end of the tunnel junction <NUM> may receive a high-level read/write signal B transmitted by the bit line BL, and the source lines (SL1, SL2, SL3) apply low-level signals, causing a current to flow from the second end of the tunnel junction <NUM> to the first end of the tunnel junction <NUM>. A corresponding storage state can be read by detecting the resistance of the tunnel junction <NUM>.

In addition, in hold phases t2, t4, and t6 of the storage cell, the low-level signals transmitted by the word lines WL1, WL2, and WL3 make the access transistors <NUM>, <NUM>, <NUM>, and <NUM> in a disconnection state. At the same time, the signal on the bit line BL is also a low-level signal. In this case, neither data write nor data read is performed.

It should be noted that, the terms "high level" and "low level" in the present specific embodiment are relative concepts (that is, a voltage value of the high level is higher than that of the low level corresponding thereto) and do not define the specific voltage value of the high level or the specific voltage value of the low level. Moreover, the terms do not define that high levels applied to different signal lines in the present specific embodiment are all equal, for example, the high level of the bit line and the high level of the word line may be different voltages. The terms do not define that high levels of a particular signal line in different phases are equal, for example, the high levels applied by the bit line when writing "<NUM>" and during the read operation may be different voltage values. Those skilled in the art should understand that the values of the corresponding high and low levels can be set according to process nodes, speed requirements, reliability requirements, and the like.

An embodiment of the present invention further provides a storage array. The storage array includes the storage cell provided in the embodiment of the present invention, and tunnel junctions of the storage cells are arranged in an array. The first direction is a column direction of the tunnel junctions of the storage cells, and the second direction is a row direction of the tunnel junctions of the storage cells. Since the storage array provided in the embodiment of the present invention includes the storage cell provided in the embodiment of the present invention, higher integration can be provided and the comprehensive performance of the storage array can be improved under the condition of guaranteeing the writing or programming capability.

Optionally, <FIG> is a schematic structural diagram of a storage array according to an embodiment of the present invention. As shown in <FIG>, when the four access transistors of each storage cell are a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor respectively, in two storage cells that are in different rows and adjacent to each other, the storage cell in a preceding row is a storage cell <NUM> in the ith row, and the storage cell in a succeeding row is a storage cell <NUM> in the (i+<NUM>)th row. The active region of the fourth access transistor of the storage cell <NUM> in the ith row and the active region of the first access transistor of the storage cell <NUM> in the (i+<NUM>)th row are an integrated structure; and the active region of the second access transistor of the storage cell <NUM> in the ith row and the active region of the third access transistor of the storage cell <NUM> in the (i+<NUM>)th row are an integrated structure. In this way, the action regions of the access transistors in two storage cells that are in different rows and adjacent to each other are set to an integrated structure to further save the space occupied by the storage cells, so as to further improve the integration of the storage array.

Optionally, each storage cell includes at least one word line, at least one source line, and a bit line; the storage cells in the same row share the word line and the source line; and the storage cells in the same column share the bit line.

Illustratively, <FIG> is a schematic structural diagram of another storage array according to an embodiment of the present invention. As shown in <FIG>, when the four access transistors of each storage cell are a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor respectively, each storage cell <NUM> may include three word lines, three source lines, and one bit line. The three word lines are a first word line WL1, a second word line WL2, and a third word line WL3 respectively. The three source lines are a first source line SL1, a second source line SL2, and a third source line SL3 respectively. The word lines (WL1, WL2, WL3) are all straight lines extending along the second direction x, and the word lines (WL1, WL2, WL3) are arranged along the first direction Y. The source lines (SL1, SL2, SL3) are all folding lines, and the source lines (SL1, SL2, SL3) are arranged along the first direction Y. The first access transistors and the third access transistors of the storage cells <NUM> in the same row share the first word line WL1, so that a gate control signal transmitted by the first word line WL1 can control the sources and the drains of the first access transistors and the third access transistors of the storage cells in the same row to switch on. The first access transistors and the second access transistors of the storage cells <NUM> in the same row share the second word line WL2, so that a gate control signal transmitted by the second word line WL2 can control the sources and the drains of the first access transistors and the second access transistors of the storage cells in the same row to switch on. The fourth access transistors and the second access transistors of the storage cells <NUM> in the same row share the third word line WL3, so that a gate control signal transmitted by the third word line WL3 can control the sources and the drains of the fourth access transistors and the second access transistors of the storage cells in the same row to switch on.

The third access transistors of the storage cells <NUM> in the same row share the first source line SL1, so that the drains of the third access transistors of the storage cells <NUM> in the same row can receive a data signal transmitted by the same first source line SL1, or can read data signals stored in the storage cells <NUM> in the same row through the same first source line SL1. The first access transistors and the second access transistors of the storage cells <NUM> in the same row share the second source line SL2, so that the drains of the first access transistors and the second access transistors of the storage cells <NUM> in the same row can receive a data signal transmitted by the same second source line SL2, or can read data signals stored in the storage cells <NUM> in the same row through the same second source line SL2. The fourth access transistors of the storage cells <NUM> in the same row share the third source line SL3, so that the drains of the fourth access transistors of the storage cells <NUM> in the same row can receive a data signal transmitted by the same third source line SL3, or can read data signals stored in the storage cells <NUM> in the same row through the same third source line SL3.

In addition, the storage cells <NUM> in the same column share the bit line BL, so that the second ends of the tunnel junctions of the storage cells in the same column can receive a read/write signal transmitted by the same bit line BL, and corresponding data signals can be written to the corresponding storage cells <NUM>, or data signals stored in the corresponding storage cells <NUM> can be read.

In this way, the storage cells in the same row can share a word line and a source line, and the storage cells in the same column can share a bit line. A row where a storage cell is located can be controlled and positioned through a gate control signal transmitted by the word line, and a column where a storage cell is located can be positioned through the bit line, so that data signals can be written into the storage cells in a one-to-one corresponding manner, or data signals stored in the storage cells can be read in a one-to-one corresponding manner. At the same time, when the storage cells in the same row can share a word line and a source line and the storage cells in the same column can share a bit line, the integration of the storage array can be further improved.

Claim 1:
A storage cell comprising: a bit line, a magnetic tunnel junction (<NUM>), and four access transistors (<NUM>, <NUM>, <NUM>, <NUM>);
sources of the access transistors (<NUM>, <NUM>, <NUM>, <NUM>) being electrically connected to a first end of the magnetic tunnel junction (<NUM>); a second end of the magnetic tunnel junction (<NUM>) being all electrically connected to the bit line; and the bit line extending along a first direction; and
active regions corresponding to the access transistors (<NUM>, <NUM>, <NUM>, <NUM>) being isolated from each other; each active region of each access transistor of the storage cell including a source, a drain and a channel region, the source and the drain being located on two opposite sides of the channel region respectively, each access transistor further including a gate; long-side extension directions of the active regions corresponding to the access transistors (<NUM>, <NUM>, <NUM>, <NUM>) being the same, and a first angle θ being formed between the long-side extension directions of the active regions and the first direction;
wherein the angle <MAT>, n being a natural number,
wherein the four access transistors (<NUM>, <NUM>, <NUM>, <NUM>) comprise a first access transistor (<NUM>) , a second access transistor (<NUM>), a third access transistor (<NUM>), and a fourth access transistor (<NUM>); a long side of an active region (<NUM>) of the first access transistor (<NUM>) is disposed opposite to a long side of an active region (<NUM>)of the second access transistor (<NUM>), and an active region (<NUM>) of the third access transistor (<NUM>) and an active region (<NUM>) of the fourth access transistor (<NUM>) are located between the active region (<NUM>) of the first access transistor (<NUM>) and the active region (<NUM>) of the second access transistor (<NUM>); and a short side of the active region (<NUM>) of the third access transistor (<NUM>) is disposed opposite in a direction along the extension direction of the active regions to a short side of the active region (<NUM>) of the fourth access transistor (<NUM>).