Patent Description:
In plasma assisted etching and plasma assisted layer deposition radio frequency (RF) generators are used to generate a bias voltage for controlling the ion energy. To improve process control, accurate control of the bias voltage and the resulting ion energy distribution (IED) is of importance. Generating this bias voltage is typically done with limited efficiency (wideband) linear amplifiers or with limited flexibility (narrowband) switch-mode amplifiers or dedicated pulse generating amplifiers. Typically the amplifiers control the output voltage waveform only indirectly (e.g. controlling output power or relying on calibration), resulting in limited performance (the generated waveform is less close to the desired output voltage waveform), and a less desired ion energy distribution and limited reproducibility (wafer to wafer variation and system to system variation).

<CIT> describes a waveform generator for a plasma assisted processing apparatus, in which a plurality of bridge legs, each having their own floating DC power source, are connected in a cascaded manner to obtain a switched voltage waveform at an output node. The voltage waveform can include a voltage slope obtained by driving a semiconductor switch according to a current control method such that an output voltage is proportional to a driving signal applied to the semiconductor switch. <CIT> belongs to the prior art according to Article <NUM>(<NUM>) EPC, and discloses a voltage waveform generator for a plasma processing apparatus, whereby the ideal or desired voltage waveform is more precisely approached and/or which allows for faster convergence to such ideal waveform. The voltage waveform generator comprises a power stage topology that comprises different voltage levels which can consecutively be coupled to the output for obtaining the periodic bias voltage. The number of voltage levels is such that resonant commutation during a change of voltage levels of the waveform can be obtained, resulting in fast and lossless commutation.

<CIT> describes a plasma assisted processing apparatus comprising a switch mode power supply for forming a periodic voltage function at an exposed surface of the substrate to be processed. The periodic voltage function effectuates a desired ion energy intensity distribution to perform etching of the substrate or plasma assisted deposition on the substrate.

The above switch mode power supply can generate a waveform of particular shape with a DC current to compensate for the ion current (see <FIG> of <CIT>). To do so, the switch mode power supply comprises two switch components that are coupled in a half-bridge and are controlled based on drive signals generated by a controller as shown in <FIG> of <CIT>.

In current plasma assisted processes, there is a tendency towards higher commutation voltage levels, larger reactors sizes, with higher capacitance.

The inherent plasma reactor capacitance and the stray inductance of the interconnection between reactor and bias voltage generator form an LC circuit having an inherent resonance characteristic. Due to the resonance in the system, slow switching speeds (limited dV/dt on the switch node) or a damping resistance (or snubber) are mandatory to suppress excitation of the resonance which would cause undesired ringing of the sheath voltage. This voltage ringing has a negative influence on the desired lED. However, slow switching speeds result in long discharge time periods effectively reducing the process/discharge ratio, which in turn results in a longer time to process the substrate. A too long discharge time can additionally have a negative influence on the sheath formation or preservation of the sheath. Moreover, a damping resistance (or snubber) would cause additional undesired losses.

It is an aim of the present invention to overcome the above drawbacks. It is an aim of the present invention to provide a voltage waveform generator for use in plasma assisted processing and related method of generating a voltage waveform, which allows for improved control of the voltage waveform. It is an aim to provide such generator and method allowing for generating a more stable voltage signal with reduced oscillations. It is an aim to provide such a voltage waveform generator having a reduced footprint.

It is an aim of the present invention to provide plasma assisted processing apparatuses and related methods that allow for an improved process control. In particular, it is an aim to provide such apparatuses and methods that enable to approach the ideal or desired voltage waveform more precisely and/or which allow for faster convergence to such ideal waveform. The present invention is denned by the appended claims.

According to a first aspect of the present invention, there is provided a voltage waveform generator as set out in claim <NUM> and its dependent claims. The voltage waveform generator according to aspects of the present invention comprises a common node, a voltage waveform generation circuit and a current source. The voltage waveform generation circuit is operably connected to the common node and is configured to apply a voltage signal at the common node. The current source is operably connected to the common node and configured to apply a DC current at the common node, in particular, the DC current is a negative current, i.e. the current source is configured to draw the DC current from the common node.

According to the invention, the current source comprises a first switch node connected to the common node through a first (physical) inductor, and a first power supply connected to the first switch node. The power supply advantageously comprises at least two first voltage nodes, advantageously providing at least two voltage levels, which are advantageously adjustable. The current source is advantageously operable to switch between the at least two first voltage nodes - and hence the at least two voltage levels - at the first switch node.

Such a current source advantageously allows to minimize a ripple on the DC current by appropriate switching between the voltage nodes. In addition, the current source has minimal footprint, and allows for sharing a power source with the voltage waveform generation circuit.

According to a second aspect of the present invention, there is provided an apparatus for plasma assisted processing as set out in claim <NUM>.

According to a third aspect of the invention, there is provided a method of generating a voltage waveform as set out in claim <NUM> and its dependent claims. The methods as described herein are advantageously implemented in the voltage waveform generator, or the apparatus as described herein.

Aspects of the invention will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features.

<FIG> shows one of the typical usages of a bias voltage waveform generator (BVG) <NUM> in an Inductively Coupled Plasma (ICP) apparatus <NUM>, where the BVG <NUM> is controlling the substrate <NUM> (typically a wafer) voltage by controlling the substrate stage voltage. In a plasma reactor <NUM>, a plasma <NUM> is generated by introduction of a plasma forming gas <NUM> in a dielectric tube <NUM> surrounded by an induction coil <NUM>. The arrangement forms a plasma torch which directs the plasma <NUM> towards a platform <NUM> (substrate stage) on which the substrate <NUM> is positioned. Optionally, a precursor <NUM> can be introduced in the plasma reactor <NUM>. A radio frequency (RF) voltage is applied to the induction coil <NUM> through a RF power supply <NUM>, and a matching network <NUM> as known in the art. The RF power supply <NUM>, as well as the BVG <NUM> can be controlled through a system host controller <NUM>. Plasma processes suitable for the present invention are so called low or reduced pressure plasma, i.e. operating at a pressure significantly below atmospheric pressure, e.g. between <NUM> mTorr and <NUM> Torr. To this end, the plasma reactor <NUM> is advantageously airtight and the desired pressure in plasma reactor <NUM> is obtained through a vacuum pump <NUM>.

The BVG <NUM> can also be used in other configurations like a Capacitively Coupled Plasma (CCP) reactor, or a configuration with a direct interconnection (not via the system host controller) of control signals between a source power generator (RF power supply) and BVG. A different source can be used to generate the plasma (e.g. Capacitively Coupled Plasma, Electron Cyclotron Resonance, Magnetron, DC voltage, etc.).

<FIG> represents an electrical model of a plasma reactor <NUM>, showing the load posed by the reactor, the plasma, the sheath and the substrate seen by the BVG <NUM>. The sheath is a boundary layer with a greater density of positive ions, and hence an overall excess positive charge, which forms on the exposed surface of the substrate due to the plasma. The excess positive charge typically balances an opposite negative charge on the exposed surface of the substrate with which it is in contact. Vpl represents the plasma potential at the sheath above the substrate and Ii the ion current in the sheath. vsh represents the voltage across the sheath. The sheath can be modelled as a sheath capacitance Csh with sheath-capacitance current ish representing the limited ion mobility in the sheath, during the process period, while the diode DP represents the high electron mobility in the sheath, during the discharge period. vsub represents the voltage across the substrate <NUM>. Lumped capacitance Csub represents the capacitance of the dielectric substrate. Lpar is a lumped inductance representing the stray inductance of the BVG output power interconnection and return path. Ct is a lumped capacitance representing the capacitance of the substrate stage (e.g. due to the electrostatic (dielectric) chuck holder on / in the substrate stage) and from the substrate stage power interconnection to earth <NUM> with associated voltage vt and current it. The latter capacitance is usually dominated by the capacitance from the substrate table to the dark shield, i.e. a metal shield adjacent the platform <NUM> preventing the plasma to propagate beyond the platform, e.g. into pump <NUM>.

A DC (bias) voltage across the sheath ideally results in a narrow IED, with the level of the DC voltage controlling the level of the (average) ion energy. There is a charge build-up on dielectric substrates and / or substrate stages of dielectric material (e.g. electrostatic chuck holders) caused by the positively charged ions that are collected on the plasma-exposed surface. Due to the charge build-up, an (ever-)decreasing voltage would need to be applied by the BVG in order to keep the sheath voltage constant. This is not achievable in a practical implementation. The charge build-up and therefore the potential over the substrate and / or substrate stage needs to be limited to prevent damage of the substrate and / or substrate stage. This compensation can be achieved by a periodic discharge of the substrate and / or substrate stage during a discharge interval between consecutive (plasma) process periods.

Referring to <FIG>, a process cycle period Tc comprises a plasma processing period Tprocess preceded (or followed) by a discharge period TD. During the plasma processing period Tprocess, the sheath voltage vsh and/or the process voltage on the exposed surface of the substrate, Vprocess = vsh + Vpl is advantageously (directly or indirectly) controlled and kept constant. Typical values of Vprocess range between <NUM> V and -<NUM> V. During the discharge periods TD between consecutive plasma processing periods Tprocess, a positive voltage pulse is applied to the substrate stage allowing removal of electric charge built up on the exposed substrate surface. The discharge period TD is advantageously as small as possible, typically on the order of <NUM> - <NUM> ns, and the voltage pulse generated during this period advantageously features fast rise and fall times and possibly minimized oscillation of the voltage peak.

The voltage shape described above can be obtained by generating a voltage waveform at the substrate stage, by the BVG <NUM>, as depicted in <FIG>. Taking account of the equivalent electric scheme of <FIG>, a voltage slope must be generated by the BVG during Tprocess to compensate for the charge/voltage build-up across the substrate.

Referring to <FIG>, the process currents corresponding to the voltage waveforms of <FIG> are depicted. It can be seen that the voltage pulse of TD is accompanied by a current pulse ish while the plasma current Ii remains substantially constant during the whole cycle period Tc, i.e. ish = <NUM> during Tprocess. At the substrate, a very high current peak isub occurs during TD while ideally isub = -Ii during Tprocess. To generate isub, an even higher current pulse iload must be generated by the BVG during TD, while the current iload that must be generated during Tprocess is typically one order of magnitude smaller (between about <NUM> and <NUM> A, and in relation to the scheme of <FIG>, <MAT>).

To obtain the desired voltage waveforms described above, according to the present invention, a BVG <NUM> is provided as shown schematically in <FIG>. BVG <NUM> comprises a pulse generation circuit <NUM> and a current source <NUM> which are coupled to a common node <NUM>. Common node <NUM> is coupled to the output node <NUM> of the BVG <NUM> through an optional physical DC blocking capacitor Cblock.

The pulse generation circuit <NUM> is configured to generate a voltage pulse during the discharge period TD, which is applied at common node <NUM>, and via DC blocking capacitor Cblock to the output node <NUM>. An optional voltage clamping circuit <NUM> can be coupled to the common node <NUM> to reduce voltage oscillation and/or overshoot at the top plateau of the voltage pulse, as will be described further below. Current source <NUM> is configured to provide a current ics to the common node <NUM> at least during the processing period Tprocess, while pulse generation circuit <NUM> is advantageously inoperative during Tprocess. Hence iload = iCS during Tprocess. It will be convenient to note that iCS is typically negative (current source <NUM> sinks current).

According to one aspect, current source <NUM> operates continuously during the entire cycle Tc to provide ics to common node <NUM>. In the latter case, iload = ics + ipulse during the discharge period TD. However, as is evident from the graphs <FIG>, iCS (between <NUM> A and <NUM> A, preferably between <NUM> A and <NUM> A) is one order of magnitude smaller than ipulse (peak amplitude at least <NUM> A, advantageously at least <NUM> A) during TD, and therefore can have negligible influence in the generation of the voltage pulse.

Referring to <FIG>, the DC-bias voltage vCblock across the DC blocking capacitor Cblock allows to set a bias on the voltage at the common node vCN.

A circuit diagram of the different parts of the BVG <NUM> is represented in <FIG>. In an exemplary embodiment, the pulse generation circuit <NUM> is a neutral-point-clamped (NPC) bridge circuit comprising active switches <NUM> connected to a (DC) power supply having at least two (DC) voltage nodes A-G, with G indicating electrical ground GND. The power supply is advantageously provided as a 'rainstick' converter <NUM>, possibly in combination with an (isolated) DC/DC converter, as shown in <FIG>, providing the at least two voltage nodes A-G (seven voltage nodes in the example of <FIG>, hence six DC-bus voltages A-B, B-C, C-D, D-E, E-F and F-G). By way of example, each DC-bus voltage A-B, or F-G, etc. can provide for a DC voltage between <NUM> V and <NUM> V, advantageously between <NUM> V and <NUM> V. Advantageously, the DC-bus voltages A-B, B-C, etc. are controllable by adjusting operation of the active switches of converter <NUM>.

The voltage nodes A-G are connected to a switch node <NUM> through operable switches <NUM> of the NPC bridge, and which are operably coupled to a control unit <NUM>. Switches <NUM> are advantageously semiconductor switches, e.g. provided as Field Effect Transistors (FETs), and advantageously comprise internal anti-parallel diodes (not shown). Switch node <NUM> is connected to common node <NUM> via a physical inductor (e.g. a coil) Lpulse. Inductor Lpulse advantageously allows for accurately controlling the current ipulse drawn from pulse generation circuit <NUM> and substantially reducing or suppressing the influence of the parasitic inductance of the electrical coupling to the substrate stage (represented by Lpar in <FIG>) in controlling ipulse. Indeed, absent Lpulse, the current ipulse would be largely defined by the parasitic inductance Lpar, and since the latter is unknown, ipulse would be hard to estimate accurately. Advantageously, Lpar is relatively smaller compared to Lpulse. Providing Lpulse allows to lower the LC resonance frequency of the equivalent LC circuit seen by the switch node <NUM>, and to increase the load impedance. When a voltage is applied to switch node <NUM>, the current will rise more slowly making it easier to calculate the timings of the voltage pulses applied to the switch node <NUM> in order to generate a clean discharge pulse.

The voltage clamping circuit <NUM> provides a switchable connection between the common node <NUM> and a DC voltage node, in particular a voltage node of a DC power supply, such as voltage node A of power supply <NUM>. To this end, a first branch <NUM> comprises one active switch or a series arrangement of active switches, e.g. active semiconductor switches <NUM>, to provide for an actively switchable connection between common node <NUM> and voltage node A. Switches <NUM> can be operated through control unit <NUM>. The voltage clamping circuit can comprise a second branch <NUM> in parallel with the first branch <NUM>, which can comprise passive switches, such as one or a series of diodes <NUM> making the time instant at which active switches <NUM> are turned on less critical. The voltage clamping circuit <NUM> can comprise an electrical damping element, such as a resistor <NUM>, advantageously connected in the first branch <NUM> in series with switches <NUM>, or alternatively in the second branch <NUM>, or in both branches <NUM> and <NUM>. Resistor <NUM> allows for reducing/damping voltage oscillations caused by any voltage mismatch when activating the voltage clamping circuit <NUM>.

According to an aspect of the present invention, the current source <NUM> comprises a power supply having at least two voltage levels (nodes) X, Y switchably connected to a switch node <NUM> through switches <NUM>, which can be active semiconductor switches, such as FETs and which can be operably coupled to control unit <NUM>. Switch node <NUM> is advantageously connected to the common node <NUM> via a physical inductor (e.g. a coil) LCS. The current source <NUM> is advantageously provided as a buck converter wherein the duty ratio of switches <NUM> allows for adjusting a DC voltage at the switch node <NUM> of the current source. A DC-bus midpoint GNDCS between voltage nodes X and Y is advantageously provided. The voltage level of the GNDcs is advantageously controlled (e.g. by control unit <NUM>) such that the volt second product across the inductor Lcs is minimized. In one example, the (average) DC voltage at switch node <NUM> in case the duty cycle (duty ratio) of switches <NUM> is set to <NUM> (<NUM>%). In this case, the potentials of X and Y are advantageously symmetric around GNDcs.

Referring to <FIG>, the power supply of current source <NUM> can be provided as a so called 'rainstick' DC/DC converter <NUM> comprising a plurality of voltage nodes X, Y, Z and GNDcs realizing a plurality of DC-bus voltages X-GNDcs, GNDcs-Y, Y-Z, etc.. The voltages of the DC-busses are advantageously adjustable by appropriate switching of switches of the DC/DC converter <NUM> and can be set to suitable values, with voltage difference between consecutive nodes advantageously ranging between <NUM> V and <NUM> V. The node GNDcs acts as a DC-bus midpoint in the buck converter of current source <NUM> and is interposed between node X and Y. Advantageously, the 'rainstick' DC/DC converters <NUM> and the 'rainstick' converter of power supply <NUM> are connected to a shared power supply, in particular the converters/power supplies <NUM> and <NUM> share a DC-bus, e.g. DC-bus E-F is shared between the two.

The operation of an exemplary embodiment of a pulse generation circuit <NUM> for generating a voltage pulse during a discharge period TD will now be described. An enlarged waveform of the voltage pulse vCN generated at the common node <NUM> during TD is shown in solid line in <FIG>. The corresponding current ipulse provided by pulse generation circuit <NUM> and flowing through inductor Lpulse is shown in <FIG>.

The voltage pulse comprises a ramp up period T<NUM>, starting at time instant t<NUM> during which switches <NUM> are operated, e.g. by control unit <NUM>, to connect a high voltage level, e.g. voltage level at node A, to switch node <NUM>. This is shown in <FIG> with the dashed line indicating the voltage vSN at switch node <NUM>. In this case, all switches <NUM> between switch node <NUM> and node A are closed, causing a current to flow through the pulse generation circuit as shown by the grey arrows in <FIG>. The high voltage will cause the current ipulse through Lpulse to increase, as shown in <FIG>. The slope of ipulse is advantageously defined by the inductance of Lpulse. A smaller inductance value will generally allow a faster ramping up of current and voltage, but will typically result in a higher peak current making switching timing as described above more critical and increasing sensitivity to signal oscillation in case of small mismatch in timing of the switches. A larger inductance value of Lpulse will decrease the ramp slope. Therefore, optimal inductance values of Lpulse are between <NUM>µH and <NUM>µH, advantageously between <NUM>µH and <NUM>µH.

At time instant t<NUM>, the switches <NUM> are opened and turn to non-conducting state and all switches <NUM> are maintained in non-conducting state. This signs the end of ramp up period T<NUM> and beginning of a freewheeling period T<NUM>. Time instant t<NUM> can be selected as the time instant at which the voltage at common node <NUM> almost reaches the voltage level at switch node <NUM> (e.g., voltage level of node A). Since the current ipulse through the inductor Lpulse must be continuous, a current path is created from electrical ground at node G, through the internal anti-parallel diodes of the switches <NUM> arranged between node G and switch node <NUM>, as shown by the grey arrows in <FIG>. The voltage vSN at switch node <NUM> drops to the voltage level of node G, while the voltage vCN at common node <NUM> continues to rise somewhat due to the current in inductor Lpulse that is still flowing and is ramping down while releasing its energy to the load capacitance, still charging this capacitance. Voltage vCN can eventually reach the level of node A. The current ipulse through inductor Lpulse will hence decrease to eventually become zero at time instant t<NUM>, signing the end of freewheeling period T<NUM>.

It is alternatively possible to connect switch node <NUM> to an intermediate voltage level B-F during freewheeling period T<NUM>. This will alter the falling slope of ipulse and hence have an impact on the slope of the rising edge of the voltage, and therefore a suitable voltage level can be selected based on a desired waveform. The current path is shown in <FIG> for the exemplary case in which switch node <NUM> is connected to voltage node F. In the latter case, switches 112a is actively closed to create the current path through node F.

At time instant t<NUM>, the voltage at common node <NUM> is advantageously clamped to its maximum level, e.g. level of node A, during a clamping period T<NUM>. The voltage clamping circuit <NUM> is advantageously used for this purpose. Switches <NUM>, which can be active semiconductor switches, e.g. FETs, are operated by control unit <NUM> to turn to a conductive state. As a result, the voltage level at common node <NUM> is clamped to the voltage of node A. Any voltage mismatch between common node <NUM> and voltage node A at turn-on of the switches <NUM> is advantageously suppressed by resistor <NUM>. Since the current ipulse through inductor Lpulse at time instant t<NUM> was zero, and all switches <NUM> are maintained in non-conducting state during T<NUM>, ipulse will remain zero during the entire clamping period T<NUM>. The length of clamping period T<NUM> is advantageously selected based on a desired length TD of the voltage pulse.

It will be convenient to note that diodes <NUM> of clamping branch <NUM> allow clamping the voltage vCN in case it would rise too fast and e.g. reach the level of node A too early, in particular before the current through inductor Lpulse becomes zero. This may be the case when a switching timing mismatch occurs.

A possible current path through the BVG during clamping period T<NUM> is represented by the grey arrows in <FIG>. As the voltage level of common node <NUM> will eventually reach the level of node A at the opposite side of the voltage clamping circuit <NUM>, the diodes <NUM> may start conducting. At this time, switches <NUM> can be switched to non-conducting state.

Alternatively, switches <NUM> can be maintained in conducting state during T<NUM>. This is particularly relevant if the current source <NUM> is operating also during the discharge period TD. The switches <NUM> in that case prevent that the current drawn by the current source <NUM> would discharge the load capacitance during the clamping interval, causing the voltage of common node <NUM> to decrease below A. Switches <NUM> therefore allow to conduct the current drawn by the current source <NUM> and keep the voltage of common node <NUM> clamped to the voltage of voltage node A.

It is alternatively possible to dispense with the clamping period T<NUM>. In such case, voltage clamping circuit <NUM> need not be provided.

Advantageously, a clamping diode (not shown) is provided between the common node <NUM> and voltage node G allowing to limit the magnitude of the voltage spikes as visible in <FIG>. These voltage spikes are induced at turn-off (opening) of the switches <NUM> of the clamping circuit <NUM>, causing the current of the current source <NUM> to be interrupted. A diode between <NUM> and G would clamp this voltage spike.

At time instant t<NUM>, the ramp down of the voltage pulse is initiated. This signs the end of the clamping period T<NUM>, and the start of the ramp down period T<NUM>. To obtain a ramp down, the current ipulse through inductor Lpulse is made to become negative. To this end, switch node <NUM> is connected to a voltage node of DC power supply <NUM> having a voltage potential which is lower than the (instantaneous) voltage potential of common node <NUM>. In the present exemplary embodiment, since common node is bound to voltage level A due to voltage clamping circuit <NUM>, it will be sufficient to select any one of levels B-G. The level selected will of course have an impact on the slope of the ramp down, and therefore a suitable level can be selected based on a desired waveform.

By way of example, the current path through the BVG <NUM> during the ramp down period is shown in <FIG> for the case that switch node <NUM> is connected to voltage node C by operating switches 112b and 112c to become conducting. The voltages vCN and vSN during T<NUM> are shown in <FIG> and the current ipulse through inductor Lpulse is shown in <FIG>.

The ramp down period T<NUM> is followed by a freewheeling period T<NUM> to bring the current ipulse through Lpulse back to zero before ending the discharge period (and hence operation of the pulse generation circuit <NUM>) and starting a new processing period Tprocess. To this end, at t<NUM> switches 112b and 112c are switched back to the non-conducting state and all of switches <NUM> remain in non-conducting state (or any other suitable voltage level can be selected). Since ipulse must remain continuous, the inductor Lpulse will cause a current to flow between switch node <NUM> and voltage node A. Switches <NUM> can be provided with internal anti-parallel diodes, in which case they will conduct this current. Alternatively, external diodes can be provided in anti-parallel with the switches <NUM>. Yet alternatively, other solutions mimicking the operation of such anti-parallel diodes can be used, e.g. switches <NUM> can be GaN normally-off junction gate field effect transistor (JFET) switches, which allow third quadrant operation, i.e. behaving similarly as diodes in reverse conduction. The resulting current path during T<NUM> is represented by the grey arrows in <FIG>. The internal diodes of switches <NUM> will automatically turn to non-conducting state once the current ipulse has become zero at time instant t<NUM> (see <FIG>). This signs the end of a discharge period and the start of a new processing period Tprocess.

The time instants t<NUM>-t<NUM> and the voltage levels A-G applied to switch node <NUM> are advantageously selected to maintain a V. s (volt seconds) balance of the inductor Lpulse. In other words and referring to <FIG>, the resulting area between curves vCN and vSN should be zero over the time span of TD. This allows for maintaining a steady-state condition/operation in which the average value of the current ipulse in inductor Lpulse does not drift away. It will be convenient to note that, when iCS is made to flow continuously over TD, the average value of ipulse over TD (and TC) is not zero and is related to ics and thus to Ii. It will be convenient to note that additional voltage switching states (periods of vSN) can be added, before, after or in between the periods T<NUM> - T<NUM> in order to obtain a desired voltage waveform for vCN.

During a process period Tprocess, the pulse generation circuit <NUM> remains inoperative, and no current ipulse flows through inductor Lpulse. As a result, the voltage over Lpulse is zero and the voltage level at switch node <NUM> will follow the voltage level of the common node <NUM> during Tprocess.

The operation of the current source <NUM> will now be described. To compensate for the charging of the load capacitance Csub due to Ii a current needs to be sunk from Csub (and hence also from Ct). To this end, a voltage slope must be obtained at the common node <NUM> (and hence at the output node <NUM>) during the process period Tprocess, as shown in <FIG>. The current source <NUM> is operated to provide a suitable DC current iCS. The current source <NUM> is advantageously continuously connected to the common node <NUM> to continuously provide a current iCS during an entire cycle period TC, i.e. both during Tprocess and during TD, since this avoids any distortions that would occur when enabling/disabling or connecting/disconnecting the current source <NUM>, and avoids system complexity related with the measures that would need to be taken to implement a connection/disconnection device/circuitry.

Referring to <FIG>, one advantage of the switch node <NUM> of current source <NUM> allowing to switch between different voltage levels (of nodes X-Y), is that the current ripple of ics can be minimized over one period, e.g. one cycle period Tc or one process period Tprocess as the case may be. Switching the voltage vcs of switch node <NUM> allows for making the volt seconds (V. s) over inductor Lcs zero over the given period, as can be seen in <FIG>, where the hatched areas indicating the difference between the voltage vCN at the common node <NUM> and the voltage of vcs fully compensate one another over one period. This also means that the average value of ics will not drift away and a steady-state condition can be achieved. This can be achieved by measuring the average value of iCS (by a current measuring means) and adapting the duty ratio of switches <NUM> such that the average value of ics is equal to a predetermined value (which can be implemented by a current control loop implemented in control unit <NUM>). Alternatively, or in addition, the voltage potentials of nodes X and Y can be suitably adjusted. <FIG> shows the voltage vcs at switch node <NUM> is switched at time instant t<NUM> between nodes X and Y.

The current ripple can be reduced by aligning vcs with vCN in a way that all the individual volt-second areas between the curves of vCS and vCN are minimized. Alternatively, or in addition, the voltage levels of X and Y can be adapted to minimize current ripple of iCS. This is advantageously performed while maintaining a steady-state condition, i.e. zero net volt-second area or in other words: the average of vcs is equal to the average of vCN. A reduced current ripple on ics advantageously results in a reduced ripple of the sheath voltage.

In another aspect, control unit <NUM> is configured to synchronize switching of switches <NUM> of the current source <NUM> and switches <NUM> of pulse generation circuit <NUM>, advantageously both in frequency and phase. This can be achieved by implementing a same clock for operating the switches <NUM> and <NUM> within control unit <NUM>. This allows for synchronizing the voltage switches of switch node <NUM> of the current source with the voltage switches of switch node <NUM> of the pulse generation circuit. As a result, the volt seconds of inductor LCS can be made zero over a given period with greater ease, and avoiding any possible mismatch due to non-synchronous clocks. By so doing, a smaller inductor coil LCS can be used, making the circuit more compact. Additionally, a smaller current ripple on ics is obtained. Advantageously, the inductance of Lcs is between <NUM>µH and <NUM> mH. Advantageously, the switching frequency of switches <NUM> is between <NUM> and <NUM>, in particular between <NUM> and <NUM>.

The current source <NUM> can comprise more than two switchable voltage levels allowing to further reduce the current ripple on ics. This way, the voltage at the switch node <NUM> of the current source can be made to more closely follow the waveform of the voltage vCN of the common node <NUM>. However, this may increase the footprint of the current source circuits and a two-voltage-level circuit (buck converter) can be considered an optimal compromise between performance and footprint.

The current source <NUM> and possibly pulse generation circuit <NUM> and/or the voltage clamping circuit <NUM> can be operated by the control unit <NUM> through open loop. Alternatively, it may be advantageous to implement a closed loop control in control unit <NUM> for operating any one of pulse generation circuit <NUM>, voltage clamping circuit <NUM>, and current source <NUM>. To this end, the BVG <NUM> can comprise measurement devices configured to measure one or a combination of:.

Claim 1:
Voltage waveform generator (<NUM>) for a plasma assisted processing apparatus (<NUM>), comprising:
a common node (<NUM>),
a voltage waveform generation circuit (<NUM>) operably connected to the common node (<NUM>) and configured to apply a voltage signal (vCN) at the common node (<NUM>), and
a current source (<NUM>) operably connected to the common node (<NUM>) and configured to apply a DC current (ics) at the common node (<NUM>),
wherein the current source (<NUM>) comprises:
a first switch node (<NUM>) connected to the common node (<NUM>) through a first inductor (Lcs), and
a first power supply (<NUM>) comprising at least two first voltage nodes (X, Y), connected to the first switch node (<NUM>),
wherein the current source (<NUM>) is operable to switch between the at least two first voltage nodes at the first switch node (<NUM>).