Patent Description:
The present disclosure relates to a display device with a plurality of insulating layers between two electrodes and a method of manufacturing the same.

Generally, an electronic appliance, such as a monitor, a TV, a laptop computer, and a digital camera, may include a display device to realize an image. For example, the display device may include a liquid crystal display device and an organic light-emitting display device.

The display device may include a plurality of pixel areas. Each of the pixel areas may display a color different from adjacent pixel area. For example, the display device may include a blue pixel area realizing a blue color, a red pixel area realizing a red color, a green pixel area realizing a green color, and a white pixel area realizing a white color.

The display device may include various signal lines and thin film transistors for independently driving each pixel area. In the display device, the signal lines and the thin film transistors may be stacked for improving the integration of each pixel area. For example, in the display device, two electrodes disposed in different layers may be connected through a contact hole that penetrates a plurality of insulating layers.

However, in the display device, an area of the contact hole disposed at an upper insulating layer may be larger than an area of the contact hole disposed at a lower insulating layer under the upper insulating layer. Thus, in the display device, the pixels per inch (PPI) or pixel density may be degraded by the area of the contact hole penetrating the stacked insulating layers.

<CIT> describes an active matrix liquid crystal display comprising pixels in which a metallization layer makes contact with an active layer through openings, where inside the openings, the active layer is patterned into the same geometry as the metallization layer, wherein the active layer is patterned in a self-aligned manner according to the pattern of the metallization layer.

<CIT>describes a thin film transistor substrate including a drain electrode including a first conductive film and a second conductive film made of aluminum and stacked on the first conductive film, wherein the second conductive film is spaced apart from a first contact hole by a cavity section formed between the second conductive film and the first contact hole, where the cavity section is in communication with the first contact hole, and a pixel electrode is provided to be out of contact with the second conductive film of the drain electrode.

Accordingly, the present disclosure is directed to a display device with a plurality of insulating layers between two electrodes and method of manufacturing the same that substantially obviate one or more of the issues due to limitations and disadvantages of the related art.

An aspect of the present disclosure is to provide a display device in which a contact hole penetrates a plurality of insulating layers for electrically connecting two electrodes disposed on different layers.

Another aspect of the present disclosure is to provide a display device having a thin film transistor and signal lines stacked without decreasing the pixel density, e.g., number of pixels per inch.

Another aspect of the present disclosure is to provide a display device with a reduced area of a contact hole for two electrodes disposed in different layers.

Additional features and aspects will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and attained by the structure particularly pointed out in the written description, or derivable therefrom, and the claims hereof as well as the appended drawings.

To achieve these and other aspects of the inventive concepts as embodied and broadly described, there is provided a display device and a method of manufacturing a display device according to the independent claims.

Other systems, methods, features and advantages will be, or will become, apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the present disclosure, and be protected by the following claims. Nothing in this section should be taken as a limitation on those claims. Further aspects and advantages are discussed below in conjunction with the embodiments of the disclosure. It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are examples and explanatory, and are intended to provide further explanation of the disclosure as claimed.

The accompanying drawings, that are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain various principles of the disclosure.

Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures.

Reference will now be made in detail to some embodiments of the present disclosure, examples of that may be illustrated in the accompanying drawings. In the following description, when a detailed description of well-known functions or configurations related to this document is determined to unnecessarily cloud a gist of the inventive concept, the detailed description thereof will be omitted. The progression of processing steps and/or operations described is an example; however, the sequence of steps and/or operations is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps and/or operations necessarily occurring in a particular order. Like reference numerals designate like elements throughout. Names of the respective elements used in the following explanations are selected only for convenience of writing the specification and may be thus different from those used in actual products.

In the description of embodiments, when a structure is described as being positioned "on or above" or "under or below" another structure, this description should be construed as including a case in which the structures contact each other as well as a case in which a third structure is disposed therebetween.

<FIG> is a view showing a display device according to an example embodiment of the present disclosure. <FIG> is an enlarged view of a region P in <FIG>. <FIG> and <FIG> are views respectively showing a display device according to another example embodiment of the present disclosure.

With reference to <FIG> and <FIG>, a display device according to an example embodiment of the present disclosure includes a lower substrate <NUM>, thin film transistor <NUM>, a lower passivation layer <NUM>, a lower over-coat layer <NUM> (herein also referred to as first over-coat layer), a connection electrode <NUM>, an upper over-coat layer <NUM> (herein also referred to as second over-coat layer), and a light-emitting structure <NUM>. For example, a display device according to an example embodiment of the present disclosure may be a self-luminous display device.

The lower substrate <NUM> may support the thin film transistor <NUM> and the light-emitting structure <NUM>. The lower substrate <NUM> may include an insulating material. The lower substrate <NUM> may include a transparent material. For example, the lower substrate <NUM> may include glass or plastic.

The thin film transistor <NUM> is disposed on the lower substrate <NUM>. For example, the thin film transistor <NUM> may include a semiconductor pattern <NUM>, a gate insulating layer <NUM>, a gate electrode <NUM>, an interlayer insulating layer <NUM>, a source electrode <NUM>, and a drain electrode <NUM>.

The semiconductor pattern <NUM> may be disposed close to the lower substrate <NUM>. The semiconductor pattern <NUM> may include a semiconductor material. For example, the semiconductor pattern <NUM> may include amorphous silicon or poly-silicon. The semiconductor pattern <NUM> may include an oxide semiconductor material. For example, the semiconductor pattern may include indium gallium zinc oxide (IGZO).

The semiconductor pattern <NUM> may include a source region, a drain region, and a channel region. The channel region may be disposed between the source region and the drain region. The conductivity of the channel region may be lower than the conductivities of the source region and the drain region. For example, the source region and the drain region may include a conductive impurity.

The semiconductor pattern <NUM> of the thin film transistor <NUM> may be in direct contact with the lower substrate <NUM>. In another example, a buffer layer may be between the lower substrate <NUM> and the thin film transistor <NUM>. The buffer layer may include an insulating material. For example, the buffer layer may include silicon oxide.

The gate insulating layer <NUM> may be disposed on the semiconductor pattern <NUM>. The gate insulating layer <NUM> may include an insulating material. For example, the gate insulating layer <NUM> may include silicon oxide and/or silicon nitride. The gate insulating layer <NUM> may include a high-K material. For example, the gate insulating layer <NUM> may include hafnium oxide (HfO) or titanium oxide (TiO). The gate insulating layer <NUM> may have a multi-layer structure.

The gate electrode <NUM> may be disposed on the gate insulating layer <NUM>. The gate electrode <NUM> may overlap the channel region of the semiconductor pattern <NUM>. The gate electrode <NUM> may be insulated from the semiconductor pattern <NUM> by the gate insulating layer <NUM>. For example, the gate insulating layer <NUM> may include a side surface vertically aligned with the gate electrode <NUM>. The side surface of the gate insulating layer <NUM> may be continuous with a side surface of the gate electrode <NUM>.

The gate electrode <NUM> may include a conductive material. For example, the gate electrode <NUM> may include a metal, such as aluminum (Al), chrome (Cr), molybdenum (Mo), and/or tungsten (W). The gate electrode <NUM> may have a multi-layer structure.

The interlayer insulating layer <NUM> may be disposed on the semiconductor pattern <NUM> and the gate electrode <NUM>. The interlayer insulating layer <NUM> may extend beyond the semiconductor pattern <NUM>. The semiconductor pattern <NUM> and the gate electrode <NUM> may be covered by the interlayer insulating layer <NUM>.

The interlayer insulating layer <NUM> may include an insulating material. For example, the interlayer insulating layer <NUM> may include silicon oxide.

The source electrode <NUM> may be disposed on the interlayer insulating layer <NUM>. The source electrode <NUM> may be electrically connected to the source region of the semiconductor pattern <NUM>. For example, the interlayer insulating layer <NUM> may include a contact hole exposing the source region of the semiconductor pattern <NUM>.

The source electrode <NUM> has a multi-layer structure. The source electrode <NUM> includes a lower source electrode <NUM>, an intermediate source electrode <NUM>, and an upper source electrode <NUM>, which may be sequentially stacked. The lower source electrode <NUM>, the intermediate source electrode <NUM> and the upper source electrode <NUM> may include a conductive material. For example, the lower source electrode <NUM>, the intermediate source electrode <NUM>, and the upper source electrode <NUM> may include a metal, such as aluminum (Al), chrome (Cr), molybdenum (Mo), and/or tungsten (W). The intermediate source electrode <NUM> may have a conductivity higher than that of the lower source electrode <NUM> and the upper source electrode <NUM>. The upper source electrode <NUM> may include a material that is same as that of the lower source electrode <NUM>.

The drain electrode <NUM> may be disposed on the interlayer insulating layer <NUM>. The drain electrode <NUM> may be spaced apart from the source electrode <NUM>. The drain electrode <NUM> may be electrically connected to the drain region of the semiconductor pattern <NUM>. For example, the interlayer insulating layer <NUM> may include a contact hole exposing the drain region of the semiconductor pattern <NUM>.

The drain electrode <NUM> has a multi-layer structure. The structure of the drain electrode <NUM> may be the same as the structure of the source electrode <NUM>. The drain electrode <NUM> includes a lower drain electrode <NUM>, an intermediate drain electrode <NUM>, and an upper drain electrode <NUM>, which may be sequentially stacked. The lower drain electrode <NUM>, the intermediate drain electrode <NUM>, and the upper drain electrode <NUM> may include a conductive material. For example, the lower drain electrode <NUM>, the intermediate drain electrode <NUM>, and the upper drain electrode <NUM> may include a metal, such as aluminum (Al), chrome (Cr), molybdenum (Mo), and/or tungsten (W). The intermediate drain electrode <NUM> may have a conductivity higher than that of the lower drain electrode <NUM> and the upper drain electrode <NUM>. The upper drain electrode <NUM> may include a material that is the same as that of the lower drain electrode <NUM>.

The upper drain electrode <NUM> has a tip region 263t extending to the outside direction from the intermediate drain electrode <NUM>. A side surface <NUM> of the intermediate drain electrode <NUM> is disposed closer to the channel region of the semiconductor pattern <NUM> than a side surface <NUM> of the tip region 263t of the upper drain electrode <NUM>. The end portion of the drain electrode <NUM> includes an under-cut region UC by the intermediate drain electrode <NUM> and the tip region 263t of the upper drain electrode <NUM>.

The upper drain electrode <NUM> has an etch selectivity with respect to the intermediate drain electrode <NUM>. An etch rate of the upper drain electrode <NUM> is different from an etch rate of the intermediate drain electrode <NUM>. For example, the upper drain electrode <NUM> may include a material having a etch rate slower than the intermediate drain electrode <NUM>. The side surface <NUM> of the intermediate drain electrode <NUM> may have a positive taper. The side surface <NUM> of the tip region 263t of the upper drain electrode <NUM> may have a negative taper.

An etch rate of the lower drain electrode <NUM> may be slower than the etch rate of the intermediate drain electrode <NUM>. For example, the etch rate of the lower drain electrode <NUM> may be the same as the etch rate of the upper drain electrode <NUM>. The lower drain electrode <NUM> may include a portion overlapping the tip region 263t of the upper drain electrode <NUM>. A side surface <NUM> of the lower drain electrode <NUM> may be disposed outside the intermediate drain electrode <NUM>. For example, the side surface <NUM> of the lower drain electrode <NUM> may have a positive taper.

The thin film transistor <NUM> may include the interlayer insulating layer <NUM> between the gate electrode <NUM> and the source/drain electrodes <NUM>, <NUM>. In another example, the thin film transistor <NUM> may include a gate insulating layer <NUM> and a semiconductor pattern <NUM> between the gate electrode <NUM> and the source/drain electrodes <NUM>, <NUM>.

The lower passivation layer <NUM> is disposed on the thin film transistor <NUM>. The lower passivation layer <NUM> extends beyond the source electrode <NUM> and the drain electrode <NUM>. For example, the lower passivation layer <NUM> may directly contact the interlayer insulating layer <NUM> on the outside of the source/drain electrodes <NUM>, <NUM> of the thin film transistor <NUM>.

The lower passivation layer <NUM> includes an insulating material. For example, the lower passivation layer <NUM> may include silicon oxide and/or silicon nitride. The lower passivation layer <NUM> may have a multi-layer structure.

The lower passivation layer <NUM> is partially cut-off by the tip region 263t of the drain electrode <NUM>. A portion of the lower passivation layer <NUM> overlapping the under-cut region UC of the drain electrode <NUM> is spaced apart from a portion of the lower passivation layer <NUM> disposed at the outside of the end portion of the drain electrode <NUM> including the tip region 263t. The side surface <NUM> of the lower drain electrode <NUM> and the side surface <NUM> of the intermediate drain electrode <NUM> are exposed by the lower passivation layer <NUM>.

The lower over-coat layer <NUM> is disposed on the lower passivation layer <NUM>. The lower over-coat layer <NUM> may remove the thickness difference due to the thin film transistor <NUM>. For example, an upper surface of the lower over-coat layer <NUM> may be parallel with a surface of the lower substrate <NUM>.

The lower over-coat layer <NUM> includes an insulating material. For example, the lower over-coat layer <NUM> may include an organic insulating material. The lower over-coat layer <NUM> may include a curable material. For example, the lower over-coat layer <NUM> may include a thermosetting resin.

The lower over-coat layer <NUM> includes a lower contact hole <NUM> (herein also referred to as first contact hole) overlapping the side surface <NUM> of the tip region 263t of the upper drain electrode <NUM>. The side surface <NUM> of the tip region 263t of the upper drain electrode <NUM> may be disposed closer to the inside of the lower contact hole <NUM> than the side surface <NUM> of the intermediate drain electrode <NUM>. The lower contact hole <NUM> may be connected to the under-cut region UC of the drain electrode <NUM>. The lower contact hole <NUM> exposes a portion of the side surface <NUM> of the lower drain electrode <NUM> and a portion of the side surface <NUM> of the intermediate drain electrode <NUM>, which may not be covered by the lower passivation layer <NUM>.

The connection electrode <NUM> may be disposed on the lower over-coat layer <NUM>. The connection electrode <NUM> may extend to the inside of the lower contact hole <NUM>. the connection electrode <NUM> may be connected to the thin film transistor <NUM> through the lower contact hole <NUM>. For example, the connection electrode <NUM> may directly contact a portion of the side surface <NUM> of the lower drain electrode <NUM> and a portion of the side surface <NUM> of the intermediate drain electrode <NUM> exposed by the lower passivation layer <NUM> and the lower contact hole <NUM>.

The connection electrode <NUM> may include a conductive material. For example, the connection electrode <NUM> may include a metal, such as copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al), and/or tungsten (W). The connection electrode <NUM> may have a multi-layer structure. For example, the connection electrode <NUM> may include a lower connection electrode <NUM> and an upper connection electrode <NUM> disposed on the lower connection electrode <NUM>.

The lower passivation layer <NUM> on the thin film transistor <NUM> partially exposes the side surface <NUM>, <NUM>, and <NUM> of the drain electrode <NUM> of the thin film transistor <NUM> by the under-cur region UC of the drain electrode <NUM>. Thus, a contact hole penetrating the lower passivation layer <NUM> does not include the drain electrode <NUM> of the thin film transistor <NUM> and the connection electrode <NUM>, which is insulated by the lower passivation layer <NUM> and the lower over-coat layer <NUM>. That is, the lower contact hole <NUM>, penetrating the lower over-coat layer <NUM> for connecting the connection electrode <NUM> to the drain electrode <NUM>, may be formed without consideration of a process margin for alignment of contact holes. Thereby, a size of the lower contact hole <NUM> for connecting the drain electrode <NUM> and the connection electrode <NUM>, which may be disposed on different layers, may be reduced.

The upper over-coat layer <NUM> may be disposed on the lower over-coat layer <NUM> and the connection electrode <NUM>. The connection electrode <NUM> may be disposed between the lower over-coat layer <NUM> and the upper over-coat layer <NUM>. The upper over-coat layer <NUM> may remove the thickness difference due to the connection electrode <NUM>. For example, an upper surface of the upper over-coat layer <NUM> may be parallel with the surface of the lower substrate <NUM>.

The upper over-coat layer <NUM> may include an insulating material. For example, the upper over-coat layer <NUM> may include an organic insulating material. The upper over-coat layer <NUM> may include a curable material. The upper over-coat layer <NUM> may include a material different from the lower over-coat layer <NUM>.

The upper over-coat layer <NUM> may include an upper contact hole <NUM> (herein also referred to as second contact hole) overlapping the connection electrode <NUM>. For example, the upper contact hole <NUM> of the upper over-coat layer <NUM> may be disposed on an upper surface of the connection electrode <NUM>.

A display device according to an example embodiment of the present disclosure may further include a connection clad layer <NUM> between the connection electrode <NUM> and the upper over-coat layer <NUM>. The connection clad layer <NUM> may reduce or prevent the connection electrode <NUM> from being damaged by a subsequent process. For example, the connection electrode <NUM> may be covered by the connection clad layer <NUM>.

The connection clad layer <NUM> may include a conductive material. The connection clad layer <NUM> may include a material having lower reactivity. For example, the connection clad layer <NUM> may include a transparent conductive material, such as indium tin oxide (ITO) and/or indium zinc oxide (IZO).

The light-emitting structure <NUM> may realize a particular color. For example, the light-emitting structure <NUM> may include a lower emitting electrode <NUM>, an organic light-emitting layer <NUM>, and an upper emitting electrode <NUM>, which may be sequentially stacked. For example, a display device according to an example embodiment of the present disclosure may be an organic light-emitting display device including the organic light-emitting layer <NUM>.

The light-emitting structure <NUM> may be controlled by the thin film transistor <NUM>. For example, the lower emitting electrode <NUM> of the light-emitting structure <NUM> may be electrically connected to the drain electrode <NUM> of the thin film transistor <NUM>. The light-emitting structure <NUM> may be disposed on the upper over-coat layer <NUM>. The lower emitting electrode <NUM> may extend to the inside of the upper contact hole <NUM> of the upper over-coat layer <NUM>. The lower emitting electrode <NUM> may be connected to the drain electrode <NUM> through the upper contact hole <NUM> and the connection electrode <NUM>.

The lower emitting electrode <NUM> may include a conductive material. The lower emitting electrode <NUM> may include a material having high-reflectivity. For example, the lower emitting electrode <NUM> may include a metal, such as aluminum (Al) and silver (Ag). The lower emitting electrode <NUM> may have a multi-layer structure. For example, the lower emitting electrode <NUM> may have a structure in which the reflective electrode including a material having high-reflectivity may be disposed between transparent electrodes including a transparent conductive material, such as ITO and/or IZO.

The organic light-emitting layer <NUM> may generate light having luminance corresponding to a voltage difference between the lower emitting electrode <NUM> and the upper emitting electrode <NUM>. For example, the organic light-emitting layer <NUM> may include an emitting material layer (EML) having an organic emission material. The organic light-emitting layer <NUM> may have a multi-layer structure, e.g., to increase luminous efficacy. For example, the organic light-emitting layer <NUM> may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

A display device according to an example embodiment of the present disclosure may be described in that the light-emitting structure <NUM> may include the organic light-emitting layer <NUM> having the organic emission material. In another example, the light-emitting structure <NUM> may include a light-emitting layer having an inorganic emission material or a hybrid emission material.

The upper emitting electrode <NUM> may include a conductive material. The upper emitting electrode <NUM> may include a material different from the lower emitting electrode <NUM>. For example, the upper emitting electrode <NUM> may be a transparent electrode. Thus, in a display device according to an example embodiment of the present disclosure, the light generated by the organic light-emitting layer <NUM> may be emitted through the upper emitting electrode <NUM>.

A display device according to an example embodiment of the present disclosure may further comprise a bank insulating layer <NUM> for insulating the light-emitting structures <NUM> of adjacent pixel areas. For example, the bank insulating layer <NUM> may cover an edge of the lower emitting electrode <NUM> of each light-emitting structure <NUM>. The organic light-emitting layer <NUM> and the upper emitting electrode <NUM> may be stacked on a surface of a portion of the lower emitting electrode <NUM>, which may be exposed by the bank insulating layer <NUM>. The bank insulating layer <NUM> may include an insulating material. For example, the bank insulating layer <NUM> may include an organic insulating material, such as benzo cyclo-butene (BCB), polyimide (PI), and/or photo-acryl. The lower over-coat layer <NUM> and the upper over-coat layer <NUM> may include a material different from that of the bank insulating layer <NUM>.

A display device according to an example embodiment of the present disclosure may further comprise an auxiliary electrode <NUM> for reducing or preventing a luminance unevenness due to the voltage drop of the upper emitting electrode <NUM>. For example, the auxiliary electrode <NUM> may be disposed between the lower over-coat layer <NUM> and the upper over-coat layer <NUM>. The upper over-coat layer <NUM> may further include a penetrating hole <NUM> overlapping the auxiliary electrode <NUM>. The auxiliary electrode <NUM> may be spaced apart from the connection electrode <NUM>.

The auxiliary electrode <NUM> may include a conductive material. For example, the auxiliary electrode <NUM> may include a metal, such as copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al), and/or tungsten (W). The structure of the auxiliary electrode <NUM> may be the same as the structure of the connection electrode <NUM>. For example, the auxiliary electrode <NUM> may include a lower auxiliary electrode <NUM> and an upper auxiliary electrode <NUM> disposed on the lower auxiliary electrode <NUM>.

A display device according to an example embodiment of the present disclosure may further comprise an auxiliary clad layer <NUM> between the auxiliary electrode <NUM> and the upper over-coat layer <NUM>. The auxiliary clad layer <NUM> may cover the auxiliary electrode <NUM>. The auxiliary clad layer <NUM> may include a conductive material. For example, the auxiliary clad layer <NUM> may include a material that is the same as the connection clad layer <NUM>. The auxiliary clad layer <NUM> may include a transparent conductive material, such as ITO and/or IZO.

The organic light-emitting layer <NUM> and the upper emitting layer <NUM> extend onto the bank insulating layer <NUM>. A display device according to an example embodiment of the present disclosure may further comprise a partition <NUM> for providing a space in which the upper emitting electrode <NUM> may be electrically connected to the auxiliary electrode <NUM>. For example, a portion of the organic light-emitting layer <NUM> may be separated from another portion of the organic light-emitting layer <NUM> by the partition <NUM>. The upper emitting electrode <NUM> may be electrically connected to the auxiliary electrode <NUM> through a space between the portions of the organic light-emitting layer <NUM> separated by the partition <NUM>. A vertical distance of the partition <NUM> may be larger than a vertical distance of the bank insulating layer <NUM>. For example, the partition <NUM> may include a lower partition <NUM> and an upper partition <NUM> disposed on the lower partition <NUM>. The lower partition <NUM> and the upper partition <NUM> may include an insulating material. For example, the lower partition <NUM> may include a material that is the same as that of the bank insulating layer <NUM>. The upper partition <NUM> may include a material different from the lower partition <NUM>. For example, the upper partition <NUM> may include silicon oxide and/or silicon nitride.

A display device according to an example embodiment of the present disclosure may further comprise an intermediate electrode <NUM> between the auxiliary electrode <NUM> and the bank insulating layer <NUM>. For example, the intermediate electrode <NUM> may be connected to the auxiliary electrode <NUM> through the penetrating hole <NUM> of the upper over-coat layer <NUM>. The partition <NUM> may overlap the intermediate electrode <NUM>. For example, the organic light-emitting layer <NUM> may expose a portion of the intermediate electrode <NUM> by the partition <NUM>. The bank insulating layer <NUM> may cover an edge of the intermediate electrode <NUM>. The partition <NUM> may be disposed between the bank insulating layer <NUM>. The upper emitting electrode <NUM> may be in contact with the portion of the intermediate electrode <NUM> in which the organic light-emitting layer <NUM> may not be formed due to the partition <NUM>. The upper emitting electrode <NUM> may be electrically connected to the auxiliary electrode <NUM> through the intermediate electrode <NUM>. The intermediate electrode <NUM> may include a conductive material. For example, the intermediate electrode <NUM> may include a material that is the same as that of the lower emitting electrode <NUM>. The intermediate electrode <NUM> may have a multi-layer structure. For example, the structure of the intermediate electrode <NUM> may be the same as the structure of the lower emitting electrode <NUM>.

A display device according to an example embodiment of the present disclosure may further comprise an upper substrate <NUM> opposite to the lower substrate <NUM>. For example, the upper substrate <NUM> may be disposed on the light-emitting structure <NUM>. The upper substrate <NUM> may include an insulating material. The upper substrate <NUM> may include a transparent material. For example, the upper substrate <NUM> may include glass or plastic.

In a display device according to an example embodiment of the present disclosure, the light-emitting structure <NUM> of each pixel area may realize a same color. For example, the light-emitting structure <NUM> of each pixel area may include a white organic light-emitting layer <NUM>. A display device according to an example embodiment of the present disclosure may further comprise a black matrix <NUM> and a color filter <NUM> on the upper substrate <NUM>. Thus, in a display device according to an example embodiment of the present disclosure, each pixel area on which the light-emitting structure <NUM> realizing the same color is disposed may display different colors.

A display device according to an example embodiment of the present disclosure may further comprise a filler <NUM> filling a space between the lower substrate <NUM> and the upper substrate <NUM>. The filler <NUM> may reduce or prevent the light-emitting structure <NUM> from damage due to an external impact. For example, the filler <NUM> may extend between the light-emitting structure <NUM> and the black matrix <NUM> and between the light-emitting structure <NUM> and the color filter <NUM>.

A display device according to an example embodiment of the present disclosure may be described in that the light-emitting structure <NUM> may directly contact the filler <NUM>. In another example, a display device according to another example embodiment of the present invention may further comprise an upper passivation layer between the light-emitting structure <NUM> and the filler <NUM>. The upper passivation layer may reduce or prevent the external moisture from permeating into the light-emitting structure <NUM>. The upper passivation layer may have a multi-layer structure. For example, the upper passivation layer may have a structure in which an inorganic layer including an inorganic material and an organic layer including an organic material may be stacked.

Accordingly, in a display device according to an example embodiment of the present disclosure, the lower passivation layer <NUM>, disposed closest to the drain electrode <NUM> among the insulating layers between the drain electrode <NUM> and the connection electrode <NUM>, does not include a contact hole so that an area of the lower contact hole <NUM> penetrating the lower over-coat layer <NUM>, which is disposed between the lower passivation layer <NUM> and the connection electrode <NUM>, may be reduced. Thus, in a display device according to an example embodiment of the present disclosure, the pixel density, e.g., pixels per inch, may be increased. For example, when a display device according to an example embodiment of the present disclosure is a transparent display device including pixel areas having a light-emitting region and a transparent region, an area of the light-emitting region of each pixel area may be decreased and an area of the transparent region of each pixel area may be increased, so that the overall transparency may be improved.

A display device according to an example embodiment of the present disclosure may be described in that the drain electrode <NUM> of the thin film transistor <NUM> may have a three-layer structure. In another example, the drain electrode <NUM> of the thin film transistor <NUM> may have various structures. For example, in the display device according to another embodiment of the present invention, the drain electrode <NUM> of the thin film transistor <NUM> may include a first drain electrode <NUM> and a second drain electrode <NUM> on the first drain electrode <NUM>, as shown in the example of <FIG>. The second drain electrode <NUM> may include a region extending to the outside of the first drain electrode <NUM>. Thus, in a display device according to an example embodiment of the present disclosure, the area of the contact hole may be efficiently reduced.

A display device according to an example embodiment of the present disclosure is described that the thin film transistor <NUM> may be electrically connected to the lower emitting electrode <NUM> of the light-emitting structure <NUM> by the connection electrode <NUM>. In another example, the lower emitting electrode <NUM> of the light-emitting structure <NUM> may be electrically connected to the thin film transistor <NUM> by various methods. For example, the lower emitting electrode <NUM> of the light-emitting structure <NUM> may directly contact the thin film transistor <NUM> by the lower contact hole <NUM> of the lower over-coat layer <NUM>, as shown in the <FIG> example. Thus, the pixel density, e.g., pixels per inch, may be efficiently improved.

<FIG> are views sequentially showing operations of a method of manufacturing a display device according to an example embodiment of the present disclosure.

A method of manufacturing a display device according to an example embodiment of the present disclosure will be described with reference to <FIG>, 2A, and <FIG> to 5J. First, as shown in the <FIG> example, the method of manufacturing a display device according to an example embodiment of the present disclosure includes an operation of forming (or "providing") a semiconductor pattern <NUM> on a lower substrate <NUM>, an operation of forming a gate insulating layer <NUM> and a gate electrode <NUM> on the semiconductor pattern <NUM>, an operation of forming an interlayer insulating layer <NUM> on the semiconductor pattern <NUM> and the gate electrode <NUM>, an operation of forming contact holes exposing a portion of the semiconductor pattern <NUM> in the interlayer insulating layer <NUM>, an operation of forming a first conductive material layer <NUM> connected to the semiconductor pattern <NUM> through the contact holes on the interlayer insulating layer <NUM>, an operation of forming a second conductive material layer <NUM> on the first conductive material layer <NUM>, and an operation of forming a third conductive material layer <NUM> on the second conductive material layer <NUM>.

The third conductive material layer <NUM> includes a conductive material having an etch selectivity with respect to the second conductive material layer <NUM>. For example, the third conductive material layer <NUM> may be formed of a material having an etch rate slower than that of the second conductive material layer <NUM>. For example, the first conductive material layer <NUM> may be formed of a material having an etch rate slower than the second conductive material layer <NUM>. The first conductive material layer <NUM> may be formed of a material that is the same as the material of the third conductive material layer <NUM>.

As shown in the <FIG> example, the method may further include an operation of forming a mask pattern <NUM> and <NUM>, including a half-tone region HT and a full-tone region FT thicker than the half-tone region HT on the third conductive material layer <NUM>. The mask pattern <NUM> and <NUM> may include a first mask pattern <NUM> overlapping the contact hole exposing a portion of the semiconductor pattern <NUM>, and a second mask pattern <NUM> overlapping the contact hole exposing another portion of the semiconductor pattern <NUM>. For example, the portion of the semiconductor pattern <NUM> covered by the first mask pattern <NUM> may be a drain region of the semiconductor patter <NUM>. For example, the portion of the semiconductor pattern <NUM> covered by the second mask pattern <NUM> may be a source region of the semiconductor pattern <NUM>. The gate electrode <NUM> may be disposed between the first mask pattern <NUM> and the second mask pattern <NUM>. The portion of the semiconductor pattern <NUM> overlapping the gate electrode <NUM> may be a channel region.

The half-tone region HT of the first mask pattern <NUM> may be disposed on an end portion toward the second mask pattern <NUM>. The half-tone region HT of the second mask pattern <NUM> may be disposed on an end portion toward the first mask pattern <NUM> and another end portion opposite the end portion. An end portion of the first mask pattern <NUM> opposite the second mask pattern <NUM> may be a full-tone region FT of the first mask pattern <NUM>.

The operation of forming the mask pattern <NUM> and <NUM> may be formed using the half-tone mask. For example, the half-tone region HT of the mask pattern <NUM> and <NUM> may be a region partially exposed by the half-tone mask.

As shown in the <FIG> example, the method may further include an operation of forming a preliminary source electrode 250p and a preliminary drain electrode 260p on the interlayer insulating layer <NUM>. The operation of forming the preliminary source electrode 250p and the preliminary drain electrode 260p may include an operation of sequentially etching the third conductive material layer <NUM>, the second conductive material layer <NUM>, and the first conductive material layer <NUM> using the mask pattern <NUM> and <NUM>. For example, the preliminary source electrode 250p may include a lower preliminary source electrode 251p, an intermediate preliminary source electrode 252p, and an upper preliminary source electrode 253p. For example, the preliminary drain electrode 260p may include a lower preliminary drain electrode 261p, an intermediate preliminary drain electrode 262p, and an upper preliminary drain electrode 263p.

Because the second conductive material layer <NUM> may have an etch rate faster than the third conductive material layer <NUM>, a side surface of the intermediate preliminary source electrode 252p and a side surface of the intermediate preliminary drain electrode 262p may be disposed relatively inward. For example, the upper preliminary drain electrode 263p may include a first preliminary drain tip region 911t and a second preliminary drain tip region 912t, which may be extended to the outside of the intermediate preliminary drain electrode 262p. The first preliminary drain tip region 911t of the upper preliminary drain electrode 263p may extend toward the upper preliminary source electrode 253p. The second preliminary drain tip region 912t of the upper preliminary drain electrode 263p may be opposite the first preliminary drain tip region 911t of the upper preliminary drain electrode 263p. For example, the upper preliminary source electrode 253p may include a first preliminary source tip region 921t and a second preliminary source tip region 922t, which may extend to the outside of the intermediate preliminary source electrode 252p. The first preliminary source tip region 921t of the upper preliminary source electrode 253p may extend toward the upper preliminary drain electrode 263p. The second preliminary source tip region 922t of the upper preliminary source electrode 253p may be opposite the first preliminary source tip region 921t of the upper preliminary source electrode 253p. The lower preliminary source electrode 251p and the lower preliminary drain electrode 261p may each respectively include a region disposed outside the intermediate preliminary source electrode 252p and the intermediate preliminary drain electrode 262p.

A side surface of the lower preliminary source electrode 251p, a side surface of the intermediate preliminary source electrode 252p, a side surface of the lower preliminary drain electrode 261p, and a side surface of the intermediate preliminary drain electrode 262p may each have a positive taper. Each of the upper preliminary source electrode 253p and the upper preliminary drain electrode 263p may have a bottom surface that may be etched faster than a top surface. A side surface of the first preliminary source tip region 921t and a side surface of the second preliminary source tip region 922t may each have a negative taper. A side surface of the first preliminary drain tip region 911t and a side surface of the second preliminary drain tip region 912t may each have a negative taper.

As shown in the <FIG> example, the method may further include an operation of forming a third mask pattern <NUM> on the preliminary drain electrode 260p, and forming a fourth mask pattern <NUM> on the preliminary source electrode 250p. The operation of forming the third mask pattern <NUM> and the fourth mask pattern <NUM> may include an operation of removing the half-tone region HT of the first mask pattern <NUM> and the half-tone region HT of the second mask pattern <NUM>. For example, the operation of forming the third mask pattern <NUM> and the fourth mask pattern <NUM> may include an operation of ashing the mask pattern <NUM> and <NUM>.

The third mask pattern <NUM> may expose the first preliminary drain tip region 911t of the upper preliminary drain electrode 263p. The third mask pattern <NUM> may cover the second preliminary drain tip region 912t of the upper preliminary drain electrode 263p. The second preliminary drain tip region 912t of the upper preliminary drain electrode 263p may be hidden by the third mask pattern <NUM>. The fourth mask pattern <NUM> may expose the first preliminary source tip region 921t and the second preliminary source tip region 922t of the upper preliminary source electrode 253p.

As shown in the <FIG> example, the method may further include an operation of forming a source electrode <NUM> and a drain electrode <NUM> on the interlayer insulating layer <NUM> so that a thin film transistor <NUM> may be completely formed. The operation of forming the source electrode <NUM> and the drain electrode <NUM> may include an operation of removing the tip regions 911t, 921t, and 922t exposed by the third mask pattern <NUM> and the fourth mask pattern <NUM>. The source electrode <NUM> may include a lower source electrode <NUM>, an intermediate source electrode <NUM>, and an upper source electrode <NUM>, which may be sequentially stacked. The source electrode <NUM> may be connected to the source region of the semiconductor pattern <NUM>. The drain electrode <NUM> may include a lower drain electrode <NUM>, an intermediate drain electrode <NUM>, and an upper drain electrode <NUM>, which may be sequentially stacked. The drain electrode <NUM> may be connected to the drain region of the semiconductor pattern <NUM>.

By the operation of removing tip regions 911t, 921t, and 922t exposed by the third mask pattern <NUM> and the fourth mask pattern <NUM>, a side surface of the upper source electrode <NUM> and the upper drain electrode <NUM>, in which the tip regions 911t, 921t and 922t were disposed, may be continuous with respective side surfaces of the intermediate source electrode <NUM> and a side surface of the intermediate drain electrode <NUM>. A side surface of the upper source electrode <NUM> and a side surface of the upper drain electrode <NUM> facing each other may each have a positive taper. A side surface of the upper source electrode <NUM> opposite to the upper drain electrode <NUM> may have a positive taper.

The second preliminary drain tip region 912t covered by the fourth mask pattern <NUM> is not removed. The upper drain electrode <NUM> of the drain electrode <NUM> includes a tip region 263t disposed at an end portion opposite to the source electrode <NUM>. A side surface of the tip region 263t of the drain electrode <NUM> may have a negative taper.

As shown in the <FIG> example, the method may further include an operation of removing the third mask pattern <NUM> and the fourth mask pattern <NUM>. As shown in the <FIG> example, the method further includes an operation of forming a lower passivation layer <NUM> on a lower substrate <NUM> in which the source electrode <NUM> and the drain electrode <NUM> are formed.

The lower passivation layer <NUM> may be formed by a process having lower step coverage. For example, the operation of forming the lower passivation layer <NUM> may include a thermal evaporation process. The lower passivation layer <NUM> partially exposes a side surface of the drain electrode <NUM> by the tip region 263t of the drain electrode <NUM>. For example, the lower passivation layer <NUM> may expose a side surface of the intermediate drain electrode <NUM> and a side surface of the lower drain electrode <NUM> that may overlap the tip region 263t of the upper drain electrode <NUM>.

As shown in the <FIG> example, the method further includes an operation of forming a lower over-coat layer <NUM>, including a lower contact hole <NUM>, on the lower passivation layer <NUM>. The operation of forming the lower over-coat layer <NUM>, including the lower contact hole <NUM>, includes an operation of forming the lower over-coat layer <NUM> on the lower passivation layer <NUM>, and may include an operation of forming the lower contact hole <NUM> overlapping the side surface of the tip region 263t of the upper drain electrode <NUM> in the lower over-coat layer <NUM>. The lower passivation layer <NUM> and the lower contact hole <NUM> exposes a side surface of the intermediate drain electrode <NUM> disposed closer the tip region 263t of the upper drain electrode <NUM>.

As shown in the <FIG> example, the method may further include an operation of forming a connection electrode <NUM>, an auxiliary electrode <NUM>, a connection clad layer <NUM>, and an auxiliary clad layer <NUM> on the lower over-coat layer <NUM>. The auxiliary electrode <NUM> may be formed simultaneously (e.g., in a same process) with the connection electrode <NUM>. For example, the operation of forming the connection electrode <NUM> and the auxiliary electrode <NUM> may include an operation of sequentially forming a lower conductive material layer and an upper conductive material layer on the lower over-coat layer <NUM>, and an operation of patterning the lower conductive material layer and the upper conductive material layer, which may be stacked. The lower conductive material layer and the upper conductive material layer, which may be stacked, may fill the lower contact hole <NUM> of the lower over-coat layer <NUM>. The connection electrode <NUM> may include a portion of the lower conductive material layer and a portion of the upper conductive material layer, which may fill the lower contact hole <NUM> of the lower over-coat layer <NUM>. The auxiliary electrode <NUM> may be spaced apart from the connection electrode <NUM>.

The auxiliary clad layer <NUM> may be formed simultaneously (e.g., in a same process) with the connection clad layer <NUM>. For example, the operation of forming the connection clad layer <NUM> and the auxiliary clad layer <NUM> may include an operation of sequentially forming a clad material layer on the connection electrode <NUM> and the auxiliary electrode <NUM>, and an operation of patterning the clad material layer. The connection clad layer <NUM> may cover the connection electrode <NUM>. The auxiliary clad layer <NUM> may cover the auxiliary electrode <NUM>. The auxiliary clad layer <NUM> may be spaced apart from the connection clad layer <NUM>.

As shown in the <FIG> example, the method may further include an operation of forming an upper over-coat layer <NUM> having an upper contact hole <NUM> and a penetrating hole <NUM> on the connection clad layer <NUM> and the auxiliary clad layer <NUM>, an operation of forming a lower emitting electrode <NUM> electrically connected to the connection electrode <NUM> through the upper contact hole <NUM> and an intermediate electrode <NUM> electrically connected to the auxiliary electrode <NUM> through the penetrating hole <NUM> on the upper over-coat layer <NUM>, an operation of forming a bank insulating layer <NUM> covering an edge of the lower emitting electrode <NUM> and an edge of the intermediate electrode <NUM>, and an operation of forming a partition <NUM> on a surface of the intermediate electrode <NUM> exposed by the bank insulating layer <NUM>. The operation of forming a partition <NUM> may include an operation of forming a lower partition <NUM> partially exposing the surface of the intermediate electrode <NUM> simultaneously (e.g., in a same process) with the bank insulating layer <NUM>, and an operation of forming an upper partition <NUM> on the lower partition <NUM>.

As shown in the examples of <FIG> and 2A, the method may include an operation of sequentially forming an organic light-emitting layer <NUM> and an upper emitting electrode <NUM> on the lower substrate <NUM> including the bank insulating layer <NUM> and the partition <NUM> so that the light-emitting structure may be completely formed. The organic light-emitting layer <NUM> may be formed by a process having a lower step coverage. For example, the operation of forming the organic light-emitting layer <NUM> may include a thermal evaporation process. The organic light-emitting layer <NUM> may expose a portion of the intermediate electrode <NUM> by the partition <NUM>.

The upper electrode <NUM> may be formed by a process having a higher step coverage. For example, the operation of forming the upper electrode <NUM> may include a sputtering process. The upper electrode <NUM> may directly contact the portion of the intermediate electrode <NUM> exposed by the organic light-emitting layer <NUM>.

The method may include an operation of attaching the upper substrate <NUM> including a black matrix <NUM> and a color filter <NUM> to the lower substrate <NUM> including the light-emitting structure <NUM>. The operation of bonding the lower substrate <NUM> and the upper substrate <NUM> may include an operation of filling a filler <NUM> between the light-emitting structure <NUM> and the black matrix <NUM>, and between the light-emitting structure <NUM> and the color filter <NUM>.

In a method of forming a display device according to an example embodiment of the present disclosure, because the side surface of the drain electrode <NUM> of the thin film transistor <NUM> is partially exposed by a process of forming the lower passivation layer <NUM> on the thin film transistor <NUM>, a process of forming a contact hole in the lower passivation layer <NUM> may be omitted. Thus, in a method of forming a display device according to an example embodiment of the present disclosure, the side surface of the drain electrode <NUM>, which is not covered by the lower passivation layer <NUM>, is exposed through the lower contact hole <NUM> of the lower over-coat layer <NUM> disposed on the lower passivation layer <NUM> so that the forming process of the contact hole electrically connecting the connection electrode <NUM> to the drain electrode <NUM> spaced apart by the lower passivation layer <NUM> and the lower over-coat layer <NUM> may be simplified. Also, in a method of forming a display device according to an example embodiment of the present disclosure, the lower contact hole <NUM> of the lower over-coat layer <NUM> may be formed without considering a process margin for the alignment of the contact holes so that the lower contact hole <NUM> may be formed to have a relatively small size. Thereby, in a method of forming a display device according to an example embodiment of the present disclosure, the process cost and the process time may be reduced and the pixel density, e.g., pixels per inch (PPI), may be increased.

As a result, a display device according to an example embodiment of the present disclosure includes an operation of forming an under-cut region at an end portion of the electrode disposed relatively lower so that the insulating layer disposed closest to the electrode may be partially cut-off. Thus, in a display device according to an example embodiment, a process of forming a contact hole in the insulating layer disposed closest to the electrode disposed relatively lower among the insulating layers stacked between two electrodes may be omitted. That is, in a display device according to an example embodiment, the area of the contact hole penetrating the stacked insulating layers between the two electrodes may be reduced. Therefore, in a display device according to an example embodiment, the pixel density, e.g., pixels per inch (PPI), may be improved.

Claim 1:
A display device, comprising:
a lower substrate (<NUM>);
a first over-coat layer (<NUM>) on the lower substrate (<NUM>), the first over-coat layer (<NUM>) comprising a first contact hole (<NUM>);
a thin film transistor between (<NUM>) the lower substrate (<NUM>) and the first over-coat layer (<NUM>), the thin film transistor (<NUM>) comprising a drain electrode (<NUM>) comprising an end portion overlapping the first contact hole (<NUM>), the end portion of the drain electrode (<NUM>) comprising an under-cut region (UC);
a lower passivation layer (<NUM>) between the thin film transistor (<NUM>) and the first over-coat layer (<NUM>), the lower passivation layer (<NUM>) exposing a side surface of the end portion of the drain electrode (<NUM>); and
a light-emitting structure (<NUM>) on the first over-coat layer (<NUM>), the light-emitting structure (<NUM>) being electrically connected to the thin film transistor (<NUM>) through the first contact hole (<NUM>),
wherein the drain electrode (<NUM>) comprises a first drain electrode (<NUM>) and a second drain electrode (<NUM>) disposed between the first drain electrode (<NUM>) and the lower passivation layer (<NUM>), a side surface of the second drain electrode (<NUM>) being closer to a center of the first contact hole (<NUM>) than a side surface of the first drain electrode (<NUM>),
wherein the lower passivation layer (<NUM>) comprises a first portion overlapping the under-cut region (UC) of the drain electrode (<NUM>) and a second portion outside the end portion of the drain electrode (<NUM>), the second portion being spaced apart from the first portion,
wherein the lower passivation layer (<NUM>) exposes the side surface of the first drain electrode (<NUM>), and
wherein each of the first portion and the second portion of the lower passivation layer (<NUM>) includes a region exposed by the first contact hole (<NUM>) of the first over-coat layer (<NUM>),
wherein the first portion and the second portion of the lower passivation layer (<NUM>) are formed by partially cutting off the lower passivation layer (<NUM>) by the under-cut region (UC) of the drain electrode (<NUM>).