Patent Description:
Generally, a lock-in amplifier includes a multiplier that multiplies a measurement signal by a reference signal and a low pass filter that extracts a DC component of a signal acquired through multiplication using the multiplier and is a signal detecting device that detects a specific signal included in a measurement signal. Such a lock-in amplifier has a feature of being able to detect a minute signal embedded in noise with high sensitivity. As types of lock-in amplifier, there are an analog type in which a multiplier and a low pass filter are realized using analog circuits and a digital type in which these are realized using digital circuits.

In <CIT> and <CIT>, an optical fiber characteristics measuring device including a lock-in amplifier is disclosed. This optical fiber characteristics measuring device is a device that detects a temperature distribution and a distortion distribution in a longitudinal direction of an optical fiber by detecting Brillouin scattering light generated in accordance with light incident to an optical fiber. Brillouin scattering light generated inside an optical fiber is extremely weak, and a lock-in amplifier is used for detecting such weak Brillouin scattering light with high sensitivity.

In a conventional lock-in amplifier, as described above, a DC component is extracted from a signal acquired by multiplying a measurement signal with a reference signal using a low pass filter. For this reason, for example, amplitudes of a signal of which frequencies are the same as a frequency of the reference signal, and the amplitude time-divisionally changes (a time-divisional signal) cannot be separated and detected. Even when a measurement signal including such time-divisional signals is input to a conventional lock-in amplifier, only one output acquired by performing low pass filter processing on the time-divisional signals can be acquired from the conventional lock-in amplifier.

In order to solve the problems described above, a first aspect of the present invention is directed to a signal detecting device as defined in claim <NUM>.

According to one or more embodiments, a signal detecting device is configured to receive a measurement signal, a reference signal and an index signal. The signal detecting device comprises: a multiplier configured to multiply the measurement signal by the reference signal having the same frequency as that of a time-divisional signal included in the measurement signal; a filter (a filter processor) configured to filter a multiplication result from the multiplier; a first storage configured to store an internal state of the filter; and a second storage configured to store a filtering result (a processing result) from the filter. The filter is configured to filter the multiplication result using the internal state stored in the first storage. The filter is configured to write or read the internal state in or from a storage area in the first storage corresponding to an index signal representing a type of amplitude of the time-divisional signal included in the measurement signal. The second storage is configured to store the filtering result in a storage area in the second storage corresponding to the index signal.

Embodiments of signal detecting device are defined in the dependent claims.

A second aspect of the present invention is directed to an optical fiber characteristics measuring device as defined in claim <NUM>.

Further features and embodiments of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings.

Embodiments of the present invention will be now described herein with reference to illustrative preferred embodiments. Those skilled in the art will recognize that many alternative preferred embodiments can be accomplished using the teaching of the present invention and that the present invention is not limited to the preferred embodiments illustrated herein for explanatory purposes.

An aspect of the present invention is directed to a signal detecting device. One or more embodiments provide a signal detecting device capable of separating and detecting amplitudes of a time-divisional signal of which the amplitude time-divisionally changes and an optical fiber characteristics measuring device including the signal detecting device.

Hereinafter, a signal detecting device and an optical fiber characteristics measuring device according to one or more embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, first, an overview of one or more embodiments of the present invention will be described, and subsequently, details of one or more embodiments of the present invention will be described in detail.

One or more embodiments of the present invention can separate and detect amplitudes of a time-divisional signal of which the amplitude time-divisionally changes. For example, in the optical fiber characteristics measuring device, in a case in which pulse light is caused to be sequentially incident in an optical fiber, amplitudes of a time-divisional signal acquired by detecting weak Brillouin scattering light sequentially output from the optical fiber are separated and are caused to be detectable.

A lock-in amplifier extracts a DC component from a signal acquired by multiplying a measurement signal by a reference signal using a low pass filter, thereby detecting a minute signal embedded in noise with high sensitivity. In the lock-in amplifier, in a case in which a component of a frequency f included in the measurement signal is extracted, a signal of the frequency f is used as a reference signal. When the measurement signal is multiplied by the reference signal, a DC component and a second harmonic component (a 2f component) can be acquired. In a conventional lock-in amplifier, by extracting only the acquired DC component using a low pass filter, a minute signal embedded in noise is detected with high sensitivity. In addition, a second harmonic component (a 2f component) also can be acquired by using a high pass filter in place of the low pass filter.

When a measurement signal including a time-divisional signal of which an amplitude time-divisionally changes is input to such a conventional lock-in amplifier, only one output acquired by performing low pass filter processing on a time-divisional signal can be acquired from the conventional lock-in amplifier. For this reason, each of amplitudes of a time-divisional signal cannot be separated and detected by the conventional lock-in amplifier.

A signal detecting device according to one or more embodiments of the present invention is a signal detecting device configured to receive a measurement signal, a reference signal and an index signal. - The signal detecting device includes a multiplier configured to multiply the measurement signal by the reference signal having the same frequency as that of a time-divisional signal included in the measurement signal, a filter (a filter processor) configured to filter a multiplication result from the multiplier, a first storage configured to store an internal state of the filter, and a second storage configured to store a filtering result from the filter processor. The filter is configured to filter the multiplication result using the internal state stored in the first storage. The filter is configured to write or read the internal state in or from a storage area in the first storage corresponding to the index signal representing a type of amplitude of the time-divisional signal included in a measurement signal. The second storage is configured to store the filtering result in a storage area in the second storage corresponding to the index signal. In accordance with this, amplitudes of a time-divisional signal of which the amplitude time-divisionally changes can be separated and detected.

<FIG> is a block diagram illustrating a main configuration of a signal detecting device according to a first embodiment of the present invention. As illustrated in <FIG>, the signal detecting device <NUM> according to this embodiment includes an ADC (an analog/digital converter) <NUM> (a first converter), an ADC <NUM> (a second converter), a multiplier <NUM>, a re-sampler <NUM>, a change point detector <NUM> (a detector), a filter processor <NUM>, an internal memory <NUM> (a first storage), and a memory <NUM> (a second storage).

A measurement signal MS, a reference signal RS, and an index signal IS are input to the signal detecting device <NUM>. The signal detecting device <NUM> separates and detects amplitudes of the time-divisional signal DS (see <FIG>) included in the measurement signal MS using the reference signal RS and the index signal IS. In addition, the signal detecting device <NUM> includes a measurement signal input terminal T11 to which the measurement signal MS is input, a reference signal input terminal T12 to which the reference signal RS is input, an index signal input terminal T13 to which the index signal IS is input, and an output terminal T20 to which a detected amplitude is output.

<FIG> are diagrams illustrating examples of signals input to the signal detecting device according to the first embodiment of the present invention. <FIG> is a diagram illustrating an example of the measurement signal MS, <FIG> is a diagram illustrating an example of the reference signal RS, and <FIG> is a diagram illustrating an example of the index signal IS. As illustrated in <FIG>, the measurement signal MS is an analog signal including a time-divisional signal DS of which an amplitude time-divisionally changes. The time-divisional signal DS illustrated in <FIG> is a signal of which an amplitude sequentially changes to A1, A2, and A3 for every two periods and is a weak signal, and thus a noise is superimposed thereon. In addition, for example, the frequency of the time-divisional signal DS is several to several tens of megahertz [MHz].

As illustrated in <FIG>, the reference signal RS is an analog signal that has the same frequency as that of the time-divisional signal DS included in the measurement signal MS and is synchronized with the time-divisional signal DS. As illustrated in <FIG>, the index signal IS is a signal that represents a type of amplitude of the time-divisional signal DS included in the measurement signal MS and is synchronized with the time-divisional signal DS. The index signal IS illustrated in <FIG> represents that a type of amplitude A1 of the time-divisional signal DS is "<NUM>", a type of amplitude A2 of the time-divisional signal DS is "<NUM>", and a type of amplitude A3 of the time-divisional signal DS is "<NUM>". The index signal IS is a digital signal of a plurality of bits (for example, <NUM> bits).

In the examples illustrated in <FIG>, for simplification of description, although a case in which the amplitude of the time-divisional signal DS is three types (amplitudes A1, A2, and A3) is illustrated as an example, the amplitude of the time-divisional signal DS may be two types or four or more types. In a case in which the index signal IS is of <NUM> bits, the number of types of amplitudes of the time-divisional signal DS that can be detected by the signal detecting device <NUM> is a maximum of <NUM>,<NUM> types ( = <NUM> types).

The ADC <NUM> converts a measurement signal MS input from the measurement signal input terminal T11 into a digital signal. The ADC <NUM> converts a reference signal RS input from the reference signal input terminal T12 into a digital signal. The multiplier <NUM> multiplies the measurement signal MS converted into the digital signal by the ADC <NUM> with the reference signal RS converted into the digital signal by the ADC <NUM>. For example, the sampling frequency of the ADCs <NUM> and <NUM> is several hundreds of megahertz [MHz].

When a timing signal TM is output from the change point detector <NUM>, the re-sampler <NUM> resamples a multiplication result acquired by the multiplier <NUM>. Here, a first reason for disposing the re-sampler <NUM> is that processing timings after the re-sampler <NUM> can be aligned at time-divisional timings of the time-divisional signal DS, and thus processing can be easily performed. A second reason for disposing the re-sampler <NUM> is that a DC component included in a multiplication result acquired by the multiplier <NUM> is finally detected by the signal detecting device <NUM>, and thus there is no problem even in a case in which a high frequency component disappears in accordance with re-sampling. For example, a sampling frequency (a re-sampling frequency) of the re-sampler <NUM> is several to several tens of megahertz [MHz]. In addition, the re-sampler <NUM> performs an aliasing noise countermeasure such as a low pass filter processing passing a frequency component of frequencies equal to or lower than <NUM>/<NUM> of the re-sampling frequency on original data (a multiplication result acquired by the multiplier <NUM>) or the like and then performs data thinning.

The change point detector <NUM> detects a timing at which the index signal IS changes. More specifically, the change point detector <NUM> detects a change in the value of the index signal IS and, in a case in which a change thereof has been detected, outputs a timing signal TM at that timing. As described above, the re-sampler <NUM> resamples a multiplication result acquired by the multiplier <NUM> when the timing signal TM is output from the change point detector <NUM>. For this reason, the re-sampler <NUM> can be regarded to re-sample a multiplication result acquired by the multiplier <NUM> at a timing detected by the change point detector <NUM>.

The filter processor <NUM> performs filter processing on a multiplication result, which has been acquired by the multiplier <NUM>, re-sampled by the re-sampler <NUM>. For example, as the filter processing described above, the filter processor <NUM> performs a process using an infinite impulse response (IIR) low pass filter. In addition, as the filter processing described above, the filter processor <NUM> may perform a process using a finite impulse response (FIR) low pass filter. In a case in which the infinite impulse response low pass filter is used, an internal state quantity can be configured to be smaller than that in a case in which the finite impulse response low pass filter is used. For this reason, when a processing load of the filter processor <NUM> and the capacity of the internal memory <NUM> are considered, it is more preferable to use the infinite impulse response low pass filter than the finite impulse response low pass filter.

The internal memory <NUM> is a memory that stores an internal state of the filter processor <NUM>. The internal memory <NUM> performs switching of an area of which an internal state is written and read using the filter processor <NUM> in accordance with the index signal IS. The memory <NUM> is a memory that stores a processing result acquired by the filter processor <NUM>. The memory <NUM> performs switching of an area in which the processing result acquired by the filter processor <NUM> is stored in accordance with the index signal IS.

<FIG> are diagrams illustrating examples of a memory map of the signal detecting device according to the first embodiment of the present invention. <FIG> is a diagram illustrating a memory map of the internal memory <NUM>, and <FIG> is a diagram illustrating a memory map of the memory <NUM>. As illustrated in <FIG>, in each of the internal memory <NUM> and the memory <NUM>, three areas are disposed in accordance with types of amplitude (amplitudes A1, A2, and A3) of the time-divisional signal DS.

An area R11 illustrated in <FIG>, for example, is an area in/from which an internal state is written/read by the filter processor <NUM> in a case in which the index signal IS is "<NUM>". An area R12, for example, is an area in/from which an internal state is written/read by the filter processor <NUM> in a case in which the index signal IS is "<NUM>". An area R13, for example, is an area in/from which an internal state is written/read by the filter processor <NUM> in a case in which the index signal IS is "<NUM>".

An area R21 illustrated in <FIG>, for example, is an area in which a processing result acquired by the filter processor <NUM> is stored in a case in which the index signal IS is "<NUM>". An area R22, for example, is an area in which a processing result acquired by the filter processor <NUM> is stored in a case in which the index signal IS is "<NUM>". An area R23, for example, is an area in which a processing result acquired by the filter processor <NUM> is stored in a case in which the index signal IS is "<NUM>".

In other words, in a case in which filter processing for the time-divisional signal DS of which an amplitude is amplitude A1 illustrated in <FIG> is performed, an internal state stored in the area R11 illustrated in <FIG> is used, and a processing result is stored in the area R21 illustrated in <FIG>. In a case in which filter processing for the time-divisional signal DS of which an amplitude is amplitude A2 illustrated in <FIG> is performed, an internal state stored in the area R12 illustrated in <FIG> is used, and a processing result is stored in the area R22 illustrated in <FIG>. In a case in which filter processing for the time-divisional signal DS of which an amplitude is amplitude A3 illustrated in <FIG> is performed, an internal state stored in the area R13 illustrated in <FIG> is used, and a processing result is stored in the area R23 illustrated in <FIG>.

As illustrated in <FIG>, the number of areas disposed in each of the internal memory <NUM> and the memory <NUM> is a number corresponding to types of amplitudes of the time-divisional signal DS. In a case in which the types of amplitude of the time-divisional signal DS are huge, the number of areas disposed in the internal memory <NUM> and the memory <NUM> also become huge. In such a case, it can be handled by increasing the capacity of each of the internal memory <NUM> and the memory <NUM>.

Next, an operation of the signal detecting device <NUM> in the configuration described above will be described. When the operation of the signal detecting device <NUM> starts, a measurement signal MS, a reference signal RS, and an index signal IS are respectively input from the measurement signal input terminal T11, the reference signal input terminal T12, and the index signal input terminal T13. The time-divisional signal DS, the reference signal RS, and the index signal IS included in the measurement signal MS are synchronized with each other.

The measurement signal MS input from the measurement signal input terminal T11 is converted into a digital signal by the ADC <NUM>, and the reference signal RS input from the reference signal input terminal T12 is converted into a digital signal by the ADC <NUM>. The measurement signal MS and the reference signal RS converted into the digital signals are multiplied with each other by the multiplier <NUM>.

On the other hand, the index signal IS input from the index signal input terminal T13 is input to the change point detector <NUM>, and a change in the value thereof is detected. When a change in the value is detected by the change point detector <NUM>, a timing signal TM is output from the change point detector <NUM> to the re-sampler <NUM>. In addition, the index signal IS is input to the internal memory <NUM> and the memory <NUM>, and an area for storing an internal state of the filter processor <NUM> and an area for storing a processing result acquired by the filter processor <NUM> are set in each thereof.

For example, it is assumed that the input index signal IS input from the index signal input terminal T13 is "<NUM>". At this time, as an area for storing the internal state of the filter processor <NUM>, for example, the area R11 of the internal memory <NUM> illustrated in <FIG> is set. In addition, as an area for storing a processing result acquired by the filter processor <NUM>, for example, the area R21 of the memory <NUM> illustrated in <FIG> is set.

A multiplication result acquired by the multiplier <NUM> is input to the re-sampler <NUM> and is re-sampled with a timing of the timing signal TM output from the change point detector <NUM>. The multiplication result, which has been acquired by the multiplier <NUM>, re-sampled by the re-sampler <NUM> is input to the filter processor <NUM>, and filter processing is performed thereon. More specifically, the filter processor <NUM> performs a process of extracting a DC component by performing a process using an infinite impulse response low pass filter.

In a case in which an internal state is stored in an area (here, the area R11 illustrated in <FIG>) of the internal memory <NUM> set in accordance with the index signal IS, the filter processor <NUM> reads the internal state and performs the filter processing described above. Internal states of the filter processor <NUM> are sequentially written into an area (here, the area R11 illustrated in <FIG>) of the internal memory <NUM> set in accordance with the index signal IS.

A processing result (an extracted DC component) acquired by the filter processor <NUM> is stored in an area (here, the area R21 illustrated in <FIG>) of the memory <NUM> set in accordance with the index signal IS. The DC component extracted here represents a magnitude of the amplitude A1 illustrated in <FIG>.

Next, the index signal IS input from the index signal input terminal T13 is assumed to change from "<NUM>" to "<NUM>". Then, the change of the value is detected by the change point detector <NUM>, and a timing signal TM is output from the change point detector <NUM> to the re-sampler <NUM>. Then, in the re-sampler <NUM>, a multiplication result acquired by the multiplier <NUM> is re-sampled with the timing of the timing signal TM.

In addition, in accordance with the change of the index signal IS, the area for storing the internal state of the filter processor <NUM> and the area for storing a processing result acquired by the filter processor <NUM> are newly set. More specifically, in a case in which the index signal IS has changed to "<NUM>", as the area for storing the internal state of the filter processor <NUM>, for example, the area R12 of the internal memory <NUM> illustrated in <FIG> is newly set. In addition, as the area for storing the processing result acquired by the filter processor <NUM>, for example, the area R22 of the memory <NUM> illustrated in <FIG> is newly set.

The multiplication result, which has been acquired by the multiplier <NUM>, re-sampled by the re-sampler <NUM> is input to the filter processor <NUM>, and filter processing is performed thereon. Here, in a case in which the internal state is stored in an area (hereinafter, the area R12 illustrated in <FIG>) of the internal memory <NUM> set in accordance with the index signal IS, the filter processor <NUM> reads the internal state and performs the filter processing described above. In addition, internal states of the filter processor <NUM> are sequentially written into an area (here, the area R12 illustrated in <FIG>) of the internal memory <NUM> set in accordance with the index signal IS.

A processing result (an extracted DC component) acquired by the filter processor <NUM> is stored in an area (here, the area R22 illustrated in <FIG>) of the memory <NUM> set in accordance with the index signal IS. The DC component extracted here represents a magnitude of the amplitude A2 illustrated in <FIG>.

In addition, in accordance with the change of the index signal IS, the area for storing the internal state of the filter processor <NUM> and the area for storing a processing result acquired by the filter processor <NUM> are newly set. More specifically, in a case in which the index signal IS has changed to "<NUM>", as the area for storing the internal state of the filter processor <NUM>, for example, the area R13 of the internal memory <NUM> illustrated in <FIG> is newly set. In addition, as the area for storing the processing result acquired by the filter processor <NUM>, for example, the area R23 of the memory <NUM> illustrated in <FIG> is newly set.

The multiplication result, which has been acquired by the multiplier <NUM>, re-sampled by the re-sampler <NUM> is input to the filter processor <NUM>, and filter processing is performed thereon. Here, in a case in which the internal state is stored in an area (hereinafter, the area R13 illustrated in <FIG>) of the internal memory <NUM> set in accordance with the index signal IS, the filter processor <NUM> reads the internal state and performs the filter processing described above. In addition, internal states of the filter processor <NUM> are sequentially written into an area (here, the area R13 illustrated in <FIG>) of the internal memory <NUM> set in accordance with the index signal IS.

A processing result (an extracted DC component) acquired by the filter processor <NUM> is stored in an area (here, the area R23 illustrated in <FIG>) of the memory <NUM> set in accordance with the index signal IS. The DC component extracted here represents a magnitude of the amplitude A3 illustrated in <FIG>.

Hereinafter, similarly, when the value of the index signal IS changes, a multiplication result acquired by the multiplier <NUM> is re-sampled with the timing, and an area for storing the internal state of the filter processor <NUM> and an area for storing a processing result acquired by the filter processor <NUM> are set. Here, in a case in which an area according to the value of the index signal IS has been set in advance, the area is set as an area for storing the internal state of the filter processor <NUM> and an area for storing a processing result acquired by the filter processor <NUM>. On the other hand, in a case in which an area according to the value of the index signal IS has not been set, an area for storing the internal state of the filter processor <NUM> and an area for storing a processing result acquired by the filter processor <NUM> are newly set.

For example, the value of the index signal IS is assumed to change to "<NUM>" again. Then, for example, the area R11 of the internal memory <NUM> illustrated in <FIG> and the area R21 of the memory <NUM> illustrated in <FIG> are respectively set as an area for storing the internal state of the filter processor <NUM> and an area for storing a processing result acquired by the filter processor <NUM>. On the other hand, for example, the value of the index signal IS is assumed to become a new value "<NUM>". Then, as an area for storing the internal state of the filter processor <NUM>, for example, an area other than the areas R11 to R13 of the internal memory <NUM> illustrated in <FIG> is newly set. In addition, as an area for storing a processing result acquired by the filter processor <NUM>, for example, an area other than the areas R21 to R23 of the memory <NUM> illustrated in <FIG> is newly set.

By performing the process described above, values representing magnitudes of the amplitudes A1, A2, and A3 of the time-divisional signal DS illustrated in <FIG> are stored in mutually-different areas of the memory <NUM>. For example, a value representing a magnitude of the amplitude A1 is stored in the area R21 of the memory <NUM>, a value representing the magnitude of the amplitude A2 is stored in the area R22 of the memory <NUM>, and a value representing the magnitude of the amplitude A3 is stored in the area R23 of the memory <NUM> (see <FIG>).

For example, each of values stored in mutually-different areas of the memory <NUM> can be read by designating a read address of the memory <NUM>. A value read from the memory <NUM> is output from the output terminal T20 of the signal detecting device <NUM>. In this way, each of amplitudes of a time-divisional signal DS included in a measurement signal MS are separated and detected.

As described above, this embodiment includes the multiplier <NUM> that multiplies a measurement signal MS by a reference signal RS and the filter processor <NUM> that performs filter processing on a multiplication result acquired by the multiplier <NUM>. In addition, this embodiment includes the internal memory <NUM> that stores an internal state of the filter processor <NUM> and the memory <NUM> that stores a processing result acquired by the filter processor <NUM>. Then, the filter processor <NUM> performs filter processing using the internal state stored in the internal memory <NUM>. The internal memory <NUM> performs switching of an area in/from which an internal state is written/read using the filter processor <NUM> in accordance with an index signal IS representing a type of amplitude of a time-divisional signal DS included in a measurement signal MS. The memory <NUM> performs switching of an area in which a processing result acquired by the filter processor <NUM> is stored in accordance with the index signal IS. In accordance with this, each of amplitudes of a time-divisional signal DS of which the amplitude time-divisionally changes can be separated and detected.

<FIG> is a block diagram illustrating a main configuration of a signal detecting device according to a second embodiment of the present invention. In <FIG>, the same reference signs will be assigned to the same blocks as the blocks illustrated in <FIG>. As illustrated in <FIG>, the signal detecting device <NUM> according to this embodiment has a configuration in which the ADC <NUM> and the change point detector <NUM> of the signal detecting device <NUM> illustrated in <FIG> are omitted, and a reference signal generator <NUM> (a first generator) and an index signal generator <NUM> (a second generator) are added.

A measurement signal MS and a start trigger signal TS are input to the signal detecting device <NUM>. The start trigger signal TS is a signal that defines a start timing of a time-divisional signal DS included in a measurement signal MS. The signal detecting device <NUM> generates a reference signal RS and an index signal IS from the start trigger signal TS and separates and detects amplitudes of the time-divisional signal DS (see <FIG>) included in the measurement signal MS using the reference signal RS and the index signal IS that have been generated.

The signal detecting device <NUM> according to this embodiment has such a premise that a frequency of the time-divisional signal DS, a period at which the amplitude of the time-divisional signal DS changes, and types of amplitude of the time-divisional signal DS are known. In the signal detecting device <NUM>, the reference signal input terminal T12 and the index signal input terminal T13 illustrated in <FIG> are omitted, and a start trigger signal input terminal T14 to which the start trigger signal TS is input is included.

The reference signal generator <NUM> starts generation of a reference signal RS at a timing at which the start trigger signal TS is input from the start trigger signal input terminal T14. The reference signal RS generated by the reference signal generator <NUM> is a digital signal having the same frequency as the frequency of the time-divisional signal DS that is known. After the start trigger signal TS is input, the reference signal generator <NUM> generates a timing signal TM every time a period with which the amplitude of the time-divisional signal DS that is known changes elapses. This timing signal TM is a signal representing a division timing of the time-divisional signal DS and is input to the re-sampler <NUM> and the index signal generator <NUM>. In addition, the timing signal TM can be regarded as a signal similar to the timing signal TM output from the change point detector <NUM> in the first embodiment.

The index signal generator <NUM> generates an index signal IS on the basis of the timing signal TM generated by the reference signal generator <NUM>. For example, a case in which the number of types of amplitude of the time-divisional signal DS, which is known, is "<NUM>" will be described. In this case, similar to the index signal IS illustrated in <FIG>, when a timing signal TM is output from the reference signal generator <NUM>, the index signal generator <NUM> generates an index signal IS changing to "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>",.

An operation of the signal detecting device <NUM> in the configuration is basically similar to the operation of the signal detecting device <NUM> according to the first embodiment except that a reference signal RS and an index signal IS are generated inside the signal detecting device <NUM> on the basis of the start trigger signal TS. For this reason, here, the operation of the signal detecting device <NUM> will be briefly described.

When the operation of the signal detecting device <NUM> starts, a measurement signal MS and a start trigger signal TS are respectively input from the measurement signal input terminal T11 and the start trigger signal input terminal T14. The time-divisional signal DS included in the measurement signal MS and the start trigger signal TS are synchronized with each other.

The measurement signal MS input from the measurement signal input terminal T11 is converted into a digital signal by the ADC <NUM>. The start trigger signal TS input from the start trigger signal input terminal T14 is input to the reference signal generator <NUM>. In accordance with this, in the reference signal generator <NUM>, generation of a reference signal RS as a digital signal starts at a timing at which the start trigger signal TS is input. The measurement signal MS converted into the digital signal is multiplied by the reference signal RS generated by the reference signal generator <NUM> using the multiplier <NUM>.

In addition, after the start trigger signal TS is input, every time a period in which the amplitude of the time-divisional signal DS changes elapses, a timing signal TM is generated by the reference signal generator <NUM>. This timing signal TM is input to the re-sampler <NUM> and is input to the index signal generator <NUM>. When the timing signal TM is input to the re-sampler <NUM>, a multiplication result acquired by the multiplier <NUM> is re-sampled with a timing of the timing signal TM by the re-sampler <NUM>. On the other hand, when the timing signal TM is input to the index signal generator <NUM>, an index signal IS is generated by the index signal generator <NUM>.

The multiplication result, which has been acquired by the multiplier <NUM>, re-sampled by the re-sampler <NUM> is input to the filter processor <NUM>, and filter processing is performed thereon. On the other hand, the index signal IS generated by the index signal generator <NUM> is input to the internal memory <NUM> and the memory <NUM>, and, similar to the first embodiment, an area for storing the internal state of the filter processor <NUM> and an area for storing the processing result acquired by the filter processor <NUM> are set.

When a timing signal TM is generated by the reference signal generator <NUM>, the value of the index signal IS generated by the index signal generator <NUM> changes. In accordance with this, the area for storing the internal state of the filter processor <NUM> in the internal memory <NUM> and the area for storing the processing result acquired by the filter processor <NUM> in the memory <NUM> are sequentially switched. By performing such a process, similar to the first embodiment, values representing magnitudes of the amplitudes A1, A2, and A3 of the time-divisional signal DS illustrated in <FIG> are stored in mutually-different areas of the memory <NUM>.

Also in this embodiment, for example, each of the values stored in the different areas of the memory <NUM> can be read by designating a read address of the memory <NUM>. The value read from the memory <NUM> is output from an output terminal T20 of the signal detecting device <NUM>. In this way, amplitudes of the time-divisional signal DS included in the measurement signal MS are separated and detected.

As described above, this embodiment includes the multiplier <NUM> that multiplies a measurement signal MS by a reference signal RS and the filter processor <NUM> that performs filter processing on a multiplication result acquired by the multiplier <NUM>. In addition, this embodiment includes the internal memory <NUM> that stores an internal state of the filter processor <NUM> and the memory <NUM> that stores a processing result acquired by the filter processor <NUM>. Furthermore, this embodiment includes the reference signal generator <NUM> that generates a reference signal RS on the basis of the start trigger signal TS and generates a timing signal TM and the index signal generator <NUM> that generates an index signal IS on the basis of the timing signal TM.

Then, the filter processor <NUM> performs filter processing using the internal state stored in the internal memory <NUM>. The internal memory <NUM> performs switching of an area of which an internal state is written and read using the filter processor <NUM> in accordance with the index signal IS generated by the index signal generator <NUM>. The memory <NUM> performs switching of an area in which the processing result acquired by the filter processor <NUM> is stored in accordance with the index signal IS generated by the index signal generator <NUM>. In accordance with this, amplitudes of the time-divisional signal DS of which the amplitude time-divisionally changes can be separated and detected.

In addition, in this embodiment, a reference signal RS and an index signal IS are generated inside the signal detecting device <NUM> on the basis of the start trigger signal TS input from the outside. In accordance with this, the number of signals input to the signal detecting device <NUM> can be reduced from the number of signals input to the signal detecting device <NUM>, and a noise and a jitter can be reduced. Such a signal detecting device <NUM> can be expect to exhibit performance higher than that of the signal detecting device <NUM>.

<FIG> is a block diagram illustrating a main configuration of an optical fiber characteristics measuring device according to one or more embodiments of the present invention. As illustrated in <FIG>, the optical fiber characteristics measuring device MD according to this embodiment includes a signal generator <NUM>, a light source <NUM>, an optical splitter <NUM> (a first optical splitter), a pulsator <NUM>, a light delayer <NUM>, a light amplifier <NUM>, an optical splitter <NUM> (a second optical splitter), a light amplifier <NUM>, an optical combiner <NUM>, a light detector <NUM> (a first detector), a frequency analyzer <NUM> (an analyzer), a second harmonic component detector <NUM> (a second detector), and a measurer <NUM>.

The optical fiber characteristics measuring device MD according to this embodiment is an optical fiber characteristics measuring device using a so-called Brillouin optical correlation domain reflectometry (BOCDR) method measuring characteristics of an optical fiber under test FUT on the basis of Brillouin scattering light LS acquired by causing pump pulse light P to be incident in the optical fiber under test FUT. In addition, the pump pulse light P described above is acquired by performing pulsation of pump light LP as continuous light for which frequency modulation has been performed. The Brillouin scattering light LS is rear-side scattering light generated in accordance with Brillouin scattering inside an optical fiber under test FUT.

As the optical fiber under test FUT, an arbitrary optical fiber can be used in accordance with a wavelength and the like of pump pulse light P. In this embodiment, it is assumed that a length of the optical fiber under test FUT is longer than an interval dm of correlation peaks, and a plurality of correlation peaks are present in the optical fiber FUT under test.

The signal generator <NUM> generates a modulation signal Sm supplied to the light source <NUM>, a pulsation signal Sp supplied to the pulsator <NUM>, and a start trigger signal TS supplied to the second harmonic component detector <NUM>. The modulation signal Sm is a signal used for outputting continuous light L1 (modulation light) for which frequency modulated has been performed from the light source <NUM>. A frequency (a modulation frequency fm) of the modulation signal Sm is swept in a frequency range defined in advance. The pulsation signal Sp is a signal for pulsating the pump light LP as continuous light. The start trigger signal TS is a signal that causes the second harmonic component detector <NUM> to start detection of a second harmonic component included in a Brillouin gain spectrum acquired by the frequency analyzer <NUM>.

The light source <NUM> includes a light source 31a and a drive signal generator 31b and outputs continuous light L1 for which frequency modulation has been performed using a modulation signal Sm output from the signal generator <NUM>. The light source 31a, for example, includes a semiconductor laser element such as a distributed feed-back laser diode (DFB-LD) and outputs continuous light L1 for which frequency modulation has been performed in accordance with a drive signal D1 output from the drive signal generator 31b. The drive signal generator 31b generates a drive signal D1 used for outputting the frequency-modulated continuous light L1 from the light source 31a using the modulation signal Sm output from the signal generator <NUM>.

The optical splitter <NUM> splits continuous light L1 output from the light source <NUM> into pump light LP and reference light LR having an intensity ratio defined in advance (for example, <NUM>:<NUM>). The pulsator <NUM> pulsates pump light LP split by the first optical splitter <NUM> using a pulsation signal Sp output from the signal generator <NUM>. The reason for disposing the pulsator <NUM> is to acquire pump light P used in a time gate method.

The light delayer <NUM> delays pump light LP formed as a pulse (pump pulse light P) by the pulsator <NUM> by a predetermined time. The light delayer <NUM>, for example, includes an optical fiber of a predetermined length. By changing the length of the optical fiber, the delay time can be adjusted. The reason for disposing the light delayer <NUM> is to dispose a <NUM>-order correlation peak, of which an appearing position does not move even when sweeping of the modulation frequency fm is performed, outside the optical fiber under test FUT.

The light amplifier <NUM> amplifies the pump pulse light P through the light delayer <NUM>. This light amplifier <NUM>, for example, includes a light amplifier such as an Erbium doped fiber amplifier (EDFA) and amplifies the pump pulse light P with a predetermined amplification factor.

The optical splitter <NUM> includes a first port, a second port, and a third port. The first port is connected to the light amplifier <NUM>. The second port is connected to the optical fiber under test FUT. The third port is connected to the light amplifier <NUM>. The optical splitter <NUM> outputs pump pulse light P input from the first port to the second port. In addition, the optical splitter <NUM> outputs Brillouin scattering light LS from the optical fiber under test FUT, which is input from the second port, to the third port. As such an optical splitter <NUM>, for example, an optical circulator can be used.

The light amplifier <NUM> amplifies Brillouin scattering light LS output from the third port of the optical splitter <NUM>. Similar to the light amplifier <NUM>, this light amplifier <NUM>, for example, includes a light amplifier such as an EDFA and amplifies the Brillouin scattering light LS output from the third port of the optical splitter <NUM> with a predetermined amplification factor.

The optical combiner <NUM> combines the Brillouin scattering light LS amplified by the light amplifier <NUM> and the reference light LR split by the optical splitter <NUM>. In addition, the optical combiner <NUM> splits the combined light into two pieces of light having an intensity ratio (for example, <NUM>: <NUM>) defined in advance and outputs the light to the light detector <NUM>. The two pieces of light split by the optical combiner <NUM>, for example, includes <NUM>% of rear-side scattering light from the optical fiber under test FUT and <NUM>% of reference light. As such an optical combiner <NUM>, for example, an optical coupler can be used.

The light detector <NUM> causes the Brillouin scattering light LS and the reference light LR included in two pieces of light output from the optical combiner <NUM> to interfere with each other, thereby performing optical heterodyne detection. The light detector <NUM>, for example, includes a balanced photodiode formed from two photo diodes (PDs) 39a and 39b and an adder 39c. The photodiodes 39a and 39b receive two pieces of light output from the optical combiner <NUM>. Light reception signals of the photodiodes 39a and 39b are input to the adder 39c. From the adder 39c, a detection signal S1 that is an intervention signal (a beat signal) representing a frequency difference between the Brillouin scattering light LS and the reference light LR is output.

The frequency analyzer <NUM> performs a frequency analysis of the detection signal S1 output from the light detector <NUM>. In other words, the frequency analyzer <NUM> acquires a Brillouin gain spectrum from the detection signal S1 output from the light detector <NUM>. The frequency analyzer <NUM>, for example, includes a spectrum analyzer (Electrical Spectrum analyzer (ESA)). The frequency analyzer <NUM> takes in the detection signal S1 output from the light detector <NUM> during a period defined using a time gate method. In accordance with this, even when a plurality of correlation peaks is present in the optical fiber under test FUT, characteristics of the optical fiber under test FUT can be measured without any problem.

In addition, the frequency analyzer <NUM> may be configured to include a time axis measurer such as an oscilloscope and a transformer performing a fast Fourier transform (FFT) in place of the spectrum analyzer. The frequency analyzer <NUM> having such a configuration transforms data, which is continuous in time, acquired by the time axis measurer into spectrum data using the transformer.

The second harmonic component detector <NUM> converts a Brillouin gain spectrum output from the frequency analyzer <NUM> into a digital signal and then detects a second harmonic component included in the Brillouin gain spectrum. Here, the second harmonic component is a component having a frequency (2fm) that is twice the modulation frequency fm of continuous light L1. The reason for detecting such a second harmonic component is to perform stable measurement in a time shorter than that of a conventional case by eliminating a noise superimposed in the Brillouin gain spectrum acquired by the frequency analyzer <NUM> and inhibiting variations of a baseline.

This second harmonic component represents an intensity at the frequency (2fm) of the Brillouin gain spectrum acquired by the frequency analyzer <NUM> and has a magnitude changing in accordance with a position of the optical fiber under test FUT at which the Brillouin gain spectrum has been acquired. For example, in a case in which the Brillouin gain spectrum acquired by the frequency analyzer <NUM> is acquired at a position at which a correlation peak appears, the magnitude of the second harmonic component is the largest.

The second harmonic component detector <NUM> includes the signal detecting device <NUM> illustrated in <FIG>. A Brillouin gain spectrum acquired by the frequency analyzer <NUM> is input to the signal detecting device <NUM> as a measurement signal MS, and a start trigger signal TS output from the signal generator <NUM> is also input to the signal detecting device <NUM>. When the start trigger signal TS is input, the signal detecting device <NUM> generates a reference signal RS having a frequency that is twice the modulation frequency of modulation light and an index signal IS and detects a second harmonic component.

The measurer <NUM> measures characteristics of the optical fiber under test FUT on the basis of the Brillouin gain spectrum that has been converted into a digital signal by the second harmonic component detector <NUM> and the second harmonic component detected by the second harmonic component detector <NUM>. More specifically, the measurer <NUM> acquires a peak frequency of the Brillouin gain spectrum by performing digital processing using the Brillouin gain spectrum that has been converted into a digital signal by the second harmonic component detector <NUM> and the second harmonic component detected by the second harmonic component detector <NUM>. Then, a Brillouin frequency shift amount is acquired from the acquired peak frequency, and this Brillouin frequency shift amount is converted into a magnitude of distortion and a temperature change applied to the optical fiber under test FUT. In addition, the measurer <NUM> may include a display that displays a second harmonic component detected by the second harmonic component detector <NUM>, characteristics of the measured optical fiber under test FUT (for example, a distortion distribution), and the like. For example, the display is a liquid crystal display, an organic electroluminescence (EL) display device, or the like.

In this embodiment, first, continuous light L1 for which frequency modulation has been performed is split into pump light LP and reference light LR, the pump light LP is transformed into pump pulse light P, then, the pump pulse light is incident from one end of the optical fiber under test FUT, and Brillouin scattering light LS generated inside the optical fiber under test is acquired. Next, interference light between the Brillouin scattering light LS and the reference light LR is detected, and a Brillouin gain spectrum that is a spectrum of the Brillouin scattering light is acquired. Then, a second harmonic component having a frequency that is twice the modulation frequency of the modulation light included in the acquired Brillouin gain spectrum is detected by the signal detecting device, and characteristics of the optical fiber under test are measured on the basis of the acquired Brillouin gain spectrum and the detected second harmonic component. In accordance with this, stable measurement can be performed in a time shorter than that of a conventional case.

As above, although the signal detecting device and the optical fiber characteristics measuring device according to embodiments of the present invention have been described, the present invention is not limited to the embodiments described above, and changes can be freely made within the scope of the present invention. For example, the second harmonic component detector <NUM> (see <FIG>) of the optical fiber characteristics measuring device MD described in the embodiment described above is configured to include the signal detecting device <NUM> according to the second embodiment illustrated in <FIG>. However, the second harmonic component detector <NUM> may be configured to include the signal detecting device <NUM> according to the first embodiment illustrated in <FIG>.

As used herein, the following directional terms "front, back, above, downward, right, left, vertical, horizontal, below, transverse, row and column" as well as any other similar directional terms refer to those instructions of a device equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to a device equipped with the present invention.

The term "configured" is used to describe a component, unit or part of a device includes hardware and/or software that is constructed and/or programmed to carry out the desired function.

Moreover, terms that are expressed as "means-plus function" in the claims should include any structure that can be utilized to carry out the function of that part of the present invention.

The term "unit" is used to describe a component, unit or part of a hardware and/or software that is constructed and/or programmed to carry out the desired function. Typical examples of the hardware may include, but are not limited to, a device and a circuit.

While preferred embodiments of the present invention have been described and illustrated above, it should be understood that these are examples of the present invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the present invention. Accordingly, the present invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the claims. The frequency analyzer <NUM> takes in the detection signal S1 output from the light detector <NUM> during a period defined using a time gate method. In accordance with this, even when a plurality of correlation peaks is present in the optical fiber under test FUT, characteristics of the optical fiber under test FUT can be measured without any problem.

Claim 1:
A signal detecting device (<NUM>; <NUM>) configured to receive a measurement signal (MS) and configured to receive or generate a reference signal (RS) and an index signal (IS), the signal detecting device (<NUM>; <NUM>) comprising:
a multiplier (<NUM>) configured to multiply the measurement signal (MS) by the reference signal (RS) having the same frequency as that of a time-divisional signal (DS) and synchronized with the time-divisional signal (DS) included in the measurement signal (MS);
a filter (<NUM>) configured to filter a multiplication result from the multiplier (<NUM>);
a first storage (<NUM>) configured to store an internal state of the filter (<NUM>); and
a second storage (<NUM>) configured to store a filtering result from the filter (<NUM>),
wherein the filter (<NUM>) is configured to filter the multiplication result using the internal state stored in the first storage (<NUM>),
wherein the filter (<NUM>) is configured to write or read the internal state in or from a storage area in the first storage (<NUM>) corresponding to the index signal (IS) representing a type of amplitude of the time-divisional signal (DS) in the measurement signal (MS) and synchronized with the time-divisional signal (DS), and
wherein the second storage (<NUM>) is configured to store the filtering result in a storage area in the second storage (<NUM>) corresponding to the index signal (IS).