Patent Description:
The technology of the disclosure relates generally to vector-processor-based devices, and, in particular, to parallel processing of vectorizable loops using processing elements (PEs) of vector-processor-based devices.

Vector-processor-based devices are computing devices that employ vector processors capable of operating on one-dimensional arrays of data ("vectors") using a single program instruction. Conventional vector processors include multiple processing elements (PEs) that are organized into vector lanes, each of which may perform computations in parallel with each other. As non-limiting examples, each of the PEs provided by conventional vector processors may be an in-order processing unit, or may be a reconfigurable fabric such as a coarse-grained reconfigurable array (CGRA) comprising a programmably interconnected group of functional units. Vector-processor-based devices are particularly useful for processing vectorizable loops that involve a high degree of data level parallelism (DLP).

When processing a vectorizable loop, each PE of a vector processor may perform the same task (e.g., executing a same loop body of the vectorizable loop, using different values for an induction variable of the vectorizable loop) in parallel. When processing vectorizable loops using a conventional vector processor having reconfigurable PEs (e.g., a vector processor in which each PE is a CGRA), the performance of the vector processor is heavily dependent on how the loop body of the vectorizable loop is mapped to the PEs. In an ideal scenario, the PEs of the vector processor are configured a single time, and each PE then processes one loop iteration of the vectorizable loop in parallel until all loop iterations have been executed. However, in practice, the mapping of the loop body of the vectorizable loop to the PEs of the vector processor may result in suboptimal performance under some circumstances. For example, if the loop body is too large to be processed by a single PE (e.g., because the loop body requires more operations than can be performed by the number of functional units provided by the PE), each loop iteration of the loop body must be split into multiple loop partitions, and the PEs must be dynamically reconfigured after execution of each loop partition. Splitting each loop iteration in this manner causes the vector processor to incur performance penalties due to the reconfiguration of the PEs as well as the need to communicate results of each loop partition execution via a vector register file. Moreover, if the number of loop iterations is smaller than the number of PEs, a number of otherwise available PEs will go unused. Finally, in the case of a vectorizable loop in which data dependencies exist between loop iterations, the data dependencies must be communicated from one loop iteration to another via the vector register file, which may be computationally expensive. Attention is drawn to <CIT> describing a scheduler of a reconfigurable array, a method of scheduling commands, and a computing apparatus. To perform a loop operation in a reconfigurable array, a recurrence node, a producer node, and a predecessor node are detected from a data flow graph of the loop operation such that resources are assigned to such nodes so as to increase the loop operating speed. Also, a dedicated path having a fixed delay may be added to the assigned resources.

Aspects disclosed in the detailed description include providing reconfigurable fusion of processing elements (PEs) in vector-processor-based devices. In this regard, a vector-processor-based device provides a vector processor that includes a plurality of PEs and a decode/control circuit that is configured to group multiple PEs into larger "fused" PEs as needed. Some aspects further include a PE communications link that interconnects the plurality of PEs to enable communications between fused PEs and among PEs comprising a fused PE without requiring vector register file access operations. In exemplary operation, the decode/control circuit receives an instruction block containing a vectorizable loop that comprises a loop body. The decode/control circuit determines how many PEs of the plurality of PEs are required to execute the loop body (based on comparing a number of instructions within the loop body with a number of functional units provided by each PE). The decode/control circuit then reconfigures the plurality of PEs into one or more fused PEs, each of which includes a determined number of PEs required to execute the loop body. The plurality of PEs, thus reconfigured into one or more fused PEs, then executes one or more loop iterations of the loop body.

In another aspect, a vector-processor-based device providing reconfigurable fusion of PEs is provided. The vector-processor-based device comprises a vector processor that includes a plurality of PEs, wherein each PE of the plurality of PEs comprises a plurality of heterogeneous functional units. The vector-processor-based device further comprises a decode/control circuit. The decode/control circuit is configured to receive an instruction block containing a vectorizable loop comprising a loop body. The decode/control circuit is further configured to determine a required PE number indicating a number of PEs of the plurality of PEs required to execute the loop body. The decode/control circuit is also configured to reconfigure the plurality of PEs into one or more fused PEs, wherein each fused PE of the one or more fused PEs comprises the required PE number of PEs of the plurality of PEs. The plurality of PEs are configured to execute one or more loop iterations of the loop body as the one or more fused PEs.

In another aspect, a vector-processor-based device providing reconfigurable fusion of PEs is provided. The vector-processor-based device comprises a means for receiving an instruction block containing a vectorizable loop comprising a loop body. The vector-processor-based device further comprises a means for determining a required PE number indicating a number of PEs of a plurality of PEs of a vector processor required to execute the loop body. The vector-processor-based device also comprises a means for reconfiguring the plurality of PEs into one or more fused PEs, wherein each fused PE of the one or more fused PEs comprises the required PE number of PEs of the plurality of PEs. The vector-processor-based device also comprises a means for executing one or more loop iterations of the loop body using the one or more fused PEs.

In another aspect, a method for providing reconfigurable fusion of PEs of a vector processor is provided. The method comprises receiving, by a decode/control circuit of the vector processor, an instruction block containing a vectorizable loop comprising a loop body. The method further comprises determining a required PE number indicating a number of PEs of a plurality of PEs of the vector processor required to execute the loop body, wherein each PE of the plurality of PEs comprises a plurality of heterogeneous functional units. The method also comprises reconfiguring the plurality of PEs into one or more fused PEs, wherein each fused PE of the one or more fused PEs comprises the required PE number of PEs of the plurality of PEs. The method additionally comprises executing one or more loop iterations of the loop body as the one or more fused PEs.

In another aspect, a non-transitory computer-readable medium is provided, having stored thereon computer-executable instructions for causing a vector processor of a vector-processor-based device to receive an instruction block containing a vectorizable loop comprising a loop body. The computer-executable instructions further cause the vector processor to determine a required PE number indicating a number of PEs of a plurality of PEs of the vector processor required to execute the loop body, wherein each PE of the plurality of PEs comprises a plurality of heterogeneous functional units. The computer-executable instructions also cause the vector processor to reconfigure the plurality of PEs into one or more fused PEs, wherein each fused PE of the one or more fused PEs comprises the required PE number of PEs of the plurality of PEs. The computer-executable instructions additionally cause the vector processor to execute one or more loop iterations of the loop body as the one or more fused PEs.

Aspects disclosed in the detailed description include providing reconfigurable fusion of processing elements (PEs) in vector-processor-based devices. In this regard, <FIG> illustrates a vector-processor-based device <NUM> that implements a block-based dataflow instruction set architecture (ISA), and that provides a vector processor <NUM> comprising a decode/control circuit <NUM>. The vector processor <NUM> includes a plurality of PEs <NUM>(<NUM>)-<NUM>(P), each of which may comprise a coarse-grained reconfigurable array (CGRA), an in-order processing unit, or a superscalar processor, as non-limiting examples. Each of the PEs <NUM>(<NUM>)-<NUM>(P) comprises a plurality of heterogeneous functional units <NUM>(<NUM>)-<NUM>(F), <NUM>'(<NUM>)-<NUM>'(F) that are programmably interconnected by functional unit communications links <NUM>, <NUM>'. The functional unit communications links <NUM>, <NUM>' serve as private communications paths within each corresponding PE of the plurality of PEs <NUM>(<NUM>)-<NUM>(P), and are configured to exchange data among the heterogeneous functional units <NUM>(<NUM>)-<NUM>(F), <NUM>'(<NUM>)-<NUM>'(F) comprising each PE of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) during instruction execution. The decode/control circuit <NUM> may programmably reconfigure the interconnections provided by the functional unit communications links <NUM>, <NUM>' depending on the processing requirements of the instructions to be executed by each of the corresponding PEs <NUM>(<NUM>)-<NUM>(P). It is to be understood that the vector-processor-based device <NUM> may include more or fewer vector processors than the vector processor <NUM> illustrated in <FIG>, and/or may provide more or fewer PEs (each having more or fewer heterogeneous functional units <NUM>(<NUM>)-<NUM>(F), <NUM>'(<NUM>)-<NUM>'(F)) than the PEs <NUM>(<NUM>)-<NUM>(P) illustrated in <FIG>.

In the example of <FIG>, the PEs <NUM>(<NUM>)-<NUM>(P) are each communicatively coupled bi-directionally to a crossbar switch <NUM> via channels <NUM>(<NUM>)-<NUM>(P), through which data (e.g., results of executing a loop iteration of a vectorizable loop) may be read from and written to a vector register file <NUM>. The crossbar switch <NUM> in the example of <FIG> is communicatively coupled to a direct memory access (DMA) controller <NUM>, which is configured to perform memory access operations to read data from and write data to a system memory <NUM>. The DMA controller <NUM> of <FIG> is also configured to control the crossbar switch <NUM> to exchange data between the vector register file <NUM>, the system memory <NUM>, and the PEs <NUM>(<NUM>)-<NUM>(P), and store and retrieve vectors and vector elements in the vector register file <NUM>. The system memory <NUM> according to some aspects may comprise a double-data-rate (DDR) memory, as a non-limiting example.

In exemplary operation, dataflow instruction blocks, such as an instruction block <NUM>, are fetched from the system memory <NUM>, and may be cached in an instruction block cache <NUM> to reduce the memory access latency associated with fetching frequently accessed instruction blocks. The instruction block <NUM> is decoded by the decode/control circuit <NUM>, and decoded instructions are assigned to a PE of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) by a scheduler circuit <NUM> for execution. To facilitate execution, the PEs <NUM>(<NUM>)-<NUM>(P) may receive live-in data values from the vector register file <NUM> as input, and, following execution of instructions, may write live-out data values as output to the vector register file <NUM>.

It is to be understood that the vector-processor-based device <NUM> of <FIG> may include more or fewer elements than illustrated in <FIG>. The vector-processor-based device <NUM> may encompass any one of known digital logic elements, semiconductor circuits, processing cores, and/or memory structures, among other elements, or combinations thereof. Aspects described herein are not restricted to any particular arrangement of elements, and the disclosed techniques may be easily extended to various structures and layouts on semiconductor dies or packages.

One application for which the vector-processor-based device <NUM> may be well-suited is processing vectorizable loops. For instance, in <FIG>, the instruction block <NUM> contains a vectorizable loop <NUM> comprising a loop body <NUM>. To process the loop body <NUM>, the decode/control circuit <NUM> maps each loop iteration of the loop body <NUM> to a different PE of the plurality of PEs <NUM>(<NUM>)-<NUM>(P), which then execute the loop iterations in parallel. However, as noted above, the resulting performance of the vector processor <NUM> when processing the loop body <NUM> may depend in large part on how loop iterations of the loop body <NUM> are mapped to the PEs <NUM>(<NUM>)-<NUM>(P). For example, if the loop body <NUM> is too large to be processed by a single PE of the plurality of PEs <NUM>(<NUM>)-<NUM>(P), each loop iteration of the loop body <NUM> must be split into multiple loop partitions, and the PEs <NUM>(<NUM>)-<NUM>(P) must be dynamically reconfigured after execution of each loop partition. This may result in performance penalties due to the reconfiguration of the PEs <NUM>(<NUM>)-<NUM>(P) as well as the need to communicate intermediate results for each loop partition execution and/or data dependencies between loop iterations via the vector register file <NUM>.

Accordingly, in this regard, the decode/control circuit <NUM> of <FIG> is configured to aggregate multiple ones of the PEs <NUM>(<NUM>)-<NUM>(P) into larger "fused" PEs. Upon receiving the instruction block <NUM>, the decode/control circuit <NUM> determines how many PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) are required to execute the loop body <NUM> of the vectorizable loop <NUM>. This number is referred to herein as a "required PE number," and is determined based on, a comparison of a number of instructions within the loop body <NUM> with a number of the heterogeneous functional units <NUM>(<NUM>)-<NUM>(F), <NUM>'(<NUM>)-<NUM>'(F) provided by each of the PEs <NUM>(<NUM>)-<NUM>(P). In some aspects, information regarding the instructions within the loop body <NUM> may be obtained by the decode/control circuit <NUM> from compiler-generated metadata <NUM> provided as part of the instruction block <NUM> (e.g., as part of an instruction block header, as a non-limiting example). The decode/control circuit <NUM> reconfigures the plurality of PEs <NUM>(<NUM>)-<NUM>(P) into one or more fused PEs (not shown), each of which includes the required PE number of the PEs <NUM>(<NUM>)-<NUM>(P) needed to execute the loop body <NUM>. The plurality of PEs <NUM>(<NUM>)-<NUM>(P), reconfigured into the one or more fused PEs, then execute one or more loop iterations of the loop body <NUM>. In use cases in which the plurality of PEs <NUM>(<NUM>)-<NUM>(P) are reconfigured into a plurality of fused PEs, each of the fused PEs may execute one loop iteration of the loop body <NUM> in parallel with other fused PEs of the plurality of fused PEs. If there are more loop iterations than fused PEs, the decode/control circuit <NUM> may perform loop unrolling, such that each fused PE executes a plurality of loop iterations of the loop body <NUM>.

Some aspects of the vector processor <NUM> further provide additional linkages between the PEs <NUM>(<NUM>)-<NUM>(P) to improve system performance both when the PEs <NUM>(<NUM>)-<NUM>(P) are operating as fused PEs, as well as when the PEs <NUM>(<NUM>)-<NUM>(P) are operating in a non-fused mode. In particular, the vector processor <NUM> in the example of <FIG> may include a PE communications link <NUM> that interconnects the PEs <NUM>(<NUM>)-<NUM>(P). When the PEs <NUM>(<NUM>)-<NUM>(P) are operating in a conventional non-fused mode, the PE communications link <NUM> enables data dependencies between loop iterations (e.g., when processing vectorizable loops with reduction operations and/or vectorizable loops with carried dependence, as non-limiting examples) to be communicated between the PEs <NUM>(<NUM>)-<NUM>(P) without requiring access to the vector register file <NUM>. When the PEs <NUM>(<NUM>)-<NUM>(P) are operating as fused PEs, the PE communications link <NUM> communicates inter-iteration data dependencies among the fused PEs, and also facilitates communications among the heterogeneous functional units <NUM>(<NUM>)-<NUM>(F), <NUM>'(<NUM>)-<NUM>'(F) within the different PEs <NUM>(<NUM>)-<NUM>(P) that make up each fused PE. Because the functional unit communications links <NUM>, <NUM>' are private to a given PE <NUM>(<NUM>)-<NUM>(P), the PE communications link <NUM> may effectively act as a data path among the heterogeneous functional units <NUM>(<NUM>)-<NUM>(F), <NUM>'(<NUM>)-<NUM>'(F) that are pooled to make up each fused PE.

To illustrate in greater detail how the mapping of loop bodies (such as the loop body <NUM>) to PEs <NUM>(<NUM>)-<NUM>(P) may negatively impact performance of a conventional vector-processor-based device, <FIG> and <FIG> are provided. <FIG> illustrates an example <NUM> in which a loop body <NUM> of a vectorizable loop <NUM> fits within each PE of a plurality of conventional PEs <NUM>(<NUM>)-<NUM>(P). As seen in <FIG>, the vectorizable loop <NUM> is a "for" loop in which an induction variable i begins with an initial value of zero (<NUM>), and then is incremented with each loop iteration until it reaches a value specified by a number N. For each loop iteration of the vectorizable loop <NUM>, the instructions contained within the loop body <NUM> (i.e., an addition instruction, a shift instruction, and a subtraction instruction) are executed using a current value of the induction variable i for the loop iteration. Accordingly, to execute the vectorizable loop <NUM>, loop iterations <NUM>(<NUM>)-<NUM>(N) of the loop body <NUM> are assigned to corresponding PEs <NUM>(<NUM>)-<NUM>(P), with each of the loop iterations <NUM>(<NUM>)-<NUM>(N) using a different value of the induction variable i. Note that it is assumed in the example of <FIG> that the number N is less than or equal to the number P of the PEs <NUM>(<NUM>)-<NUM>(P), and further that each PE of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) includes a sufficient number of heterogeneous functional units to execute the instructions within the loop body <NUM>. In this manner, the PEs <NUM>(<NUM>)-<NUM>(P) are able to execute all of the loop iterations <NUM>(<NUM>)-<NUM>(N) in parallel for all values of the induction variable i of the loop body <NUM>, resulting in optimal performance.

In contrast, <FIG> illustrates an example <NUM> in which a loop body <NUM> of a vectorizable loop <NUM> does not fit into each PE of a plurality of conventional PEs <NUM>(<NUM>)-<NUM>(P). As seen in <FIG>, the loop body <NUM> is similar to the loop body <NUM> of <FIG>, except the loop body <NUM> includes an additional multiplication instruction. The loop body <NUM> thus requires more operations than can be executed by each PE of the plurality of PEs <NUM>(<NUM>)-<NUM>(P). Consequently, to execute loop iterations <NUM>(<NUM>)-<NUM>(N), the loop iterations <NUM>(<NUM>)-<NUM>(N) are split into two (<NUM>) loop partitions <NUM>(<NUM>), <NUM>(<NUM>) for processing.

During execution, the PEs <NUM>(<NUM>)-<NUM>(P) are first configured to execute the first loop partition <NUM>(<NUM>), as indicated by arrow <NUM>. The PEs <NUM>(<NUM>)-<NUM>(P) are then reconfigured to execute the second loop partition <NUM>(<NUM>), as indicated by arrow <NUM>. If the number N of loop iterations <NUM>(<NUM>)-<NUM>(N) is greater than the number P of the PEs <NUM>(<NUM>)-<NUM>(P), then the PEs <NUM>(<NUM>)-<NUM>(P) must be repeatedly reconfigured during execution, which may incur a significant performance penalty. Moreover, any data dependencies and/or intermediate results generated during execution of the loop partitions <NUM>(<NUM>), <NUM>(<NUM>) must be stored and retrieved by the PEs <NUM>(<NUM>)-<NUM>(P) using a vector register file such as the vector register file <NUM> of <FIG>, which incurs an additional performance penalty.

<FIG> is a block diagram illustrating how the PEs <NUM>(<NUM>)-<NUM>(P) provided by the vector-processor-based device <NUM> of <FIG> may be reconfigured into one or more fused PEs by the decode/control circuit <NUM> of <FIG> to address the scenario illustrated by <FIG>. In the example of <FIG>, the PEs <NUM>(<NUM>)-<NUM>(P) have been organized into a plurality of fused PEs <NUM>(<NUM>)-<NUM>(F), with each fused PE of the plurality of fused PEs <NUM>(<NUM>)-<NUM>(F) comprising two (<NUM>) of the PEs <NUM>(<NUM>)-<NUM>(P). Thus, the fused PE <NUM>(<NUM>) includes the PEs <NUM>(<NUM>), <NUM>(<NUM>), while the fused PE <NUM>(<NUM>) includes the PEs <NUM>(<NUM>), <NUM>(<NUM>), and so on in similar fashion, with each pair of the PEs <NUM>(<NUM>)-<NUM>(P) configured to interact and operate as a single fused PE. As shown in <FIG>, communications among the PEs <NUM>(<NUM>)-<NUM>(P) constituting the fused PEs <NUM>(<NUM>)-<NUM>(F) may be further facilitated in some aspects by the PE communications link <NUM>.

It is to be understood that the decode/control circuit <NUM> may reconfigure the PEs <NUM>(<NUM>)-<NUM>(P) into arrangements of fused PEs <NUM>(<NUM>)-<NUM>(F) other than the arrangement illustrated in <FIG>. For example, the decode/control circuit <NUM> may reconfigure more of the PEs <NUM>(<NUM>)-<NUM>(P) into each fused PE of the fused PEs <NUM>(<NUM>)-<NUM>(F) as needed in order to better balance instruction-level parallelism (ILP) with data-level parallelism (DLP) for particular applications. In extreme cases requiring maximum ILP, the decode/control circuit <NUM> may even reconfigure all of the PEs <NUM>(<NUM>)-<NUM>(P) into a single fused PE <NUM>.

To illustrate exemplary operations for reconfigurable fusion of PEs <NUM>(<NUM>)-<NUM>(P) in the vector-processor-based device <NUM> of <FIG>, <FIG> is provided. For the sake of clarity, elements of <FIG> and <FIG> are referenced in describing <FIG>. Operations in <FIG> begin with the decode/control circuit <NUM> of the vector processor <NUM> receiving the instruction block <NUM> containing the vectorizable loop <NUM> comprising the loop body <NUM> (block <NUM>). In this regard, the decode/control circuit <NUM> may be referred to herein as "a means for receiving an instruction block containing a vectorizable loop comprising a loop body. " The decode/control circuit <NUM> determines a required PE number indicating a number of PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) of the vector processor <NUM> required to execute the loop body <NUM>, wherein each PE of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) comprises a plurality of heterogeneous functional units <NUM>(<NUM>)-<NUM>(F), <NUM>'(<NUM>)-<NUM>'(F) (block <NUM>). Accordingly, the decode/control circuit <NUM> may be referred to herein as "a means for determining a PE number indicating a number of PEs of a plurality of PEs of a vector processor required to execute the loop body. " In some aspects, operations of block <NUM> for determining the required PE number may comprise determining the required PE number based on the compiler-generated metadata <NUM> for the instruction block <NUM> (block <NUM>).

The decode/control circuit <NUM> then reconfigures the plurality of PEs <NUM>(<NUM>)-<NUM>(P) into one or more fused PEs <NUM>(<NUM>)-<NUM>(F), wherein each fused PE of the one or more fused PEs <NUM>(<NUM>)-<NUM>(F) comprises the required PE number of PEs of the plurality of PEs <NUM>(<NUM>)-<NUM>(P) (block <NUM>). The decode/control circuit <NUM> thus may be referred to herein as "a means for reconfiguring the plurality of PEs into one or more fused PEs, wherein each fused PE of the one or more fused PEs comprises the required PE number of PEs of the plurality of PEs. " Processing then continues at block <NUM> of <FIG>.

Referring now to <FIG>, in some aspects, the decode/control circuit <NUM> may determine whether a count of one or more loop iterations to be performed exceeds a count of the one or more fused PEs <NUM>(<NUM>)-<NUM>(F) (block <NUM>). If not, processing resumes at block <NUM>. However, if it is determined at decision block <NUM> that the count of the one or more loop iterations to be performed does exceed the count of the one or more fused PEs <NUM>(<NUM>)-<NUM>(F), the decode/control circuit <NUM> may perform loop unrolling such that each fused PE of the one or more fused PEs <NUM>(<NUM>)-<NUM>(F) executes a plurality of loop iterations of the one or more loop iterations (block <NUM>). Processing then resumes at block <NUM>.

The PEs <NUM>(<NUM>)-<NUM>(P) then execute one or more loop iterations of the loop body <NUM> as the one or more fused PEs <NUM>(<NUM>)-<NUM>(F) (block <NUM>). In this regard, the plurality of PEs <NUM>(<NUM>)-<NUM>(P) may be referred to herein as "a means for executing one or more loop iterations of the loop body using the one or more fused PEs. " In some aspects, operations of block <NUM> for executing the one or more loop iterations of the loop body <NUM> as the one or more fused PEs <NUM>(<NUM>)-<NUM>(F) may comprise the PEs <NUM>(<NUM>)-<NUM>(P) of each of the one or more fused PEs <NUM>(<NUM>)-<NUM>(F) communicating via the PE communications link <NUM> (block <NUM>). Some aspects in which the one or more fused PEs <NUM>(<NUM>)-<NUM>(F) comprise a plurality of fused PEs <NUM>(<NUM>)-<NUM>(F) may provide that operations of block <NUM> for executing the one or more loop iterations of the loop body <NUM> as the one or more fused PEs <NUM>(<NUM>)-<NUM>(F) may comprise executing, by each fused PE of the plurality of fused PEs <NUM>(<NUM>)-<NUM>(F), one loop iteration of the loop body <NUM> in parallel with other fused PEs of the plurality of fused PEs <NUM>(<NUM>)-<NUM>(F) (block <NUM>).

Providing reconfigurable fusion of PEs in vector-processor-based devices according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard, <FIG> illustrates an example of a processor-based system <NUM> that may correspond to the vector-processor-based device <NUM> of <FIG>. The processor-based system <NUM> includes one or more central processing units (CPUs) <NUM>, each including one or more processors <NUM> (which in some aspects may correspond to the PEs <NUM>(<NUM>)-<NUM>(P) of <FIG>) comprising the decode/control circuit <NUM> of <FIG>. The CPU(s) <NUM> may have cache memory <NUM> coupled to the processor(s) <NUM> for rapid access to temporarily stored data. The CPU(s) <NUM> is coupled to a system bus <NUM> and can intercouple master and slave devices included in the processor-based system <NUM>. As is well known, the CPU(s) <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the CPU(s) <NUM> can communicate bus transaction requests to a memory controller <NUM> as an example of a slave device.

Other master and slave devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include a memory system <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, one or more network interface devices <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) <NUM> can be any devices configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) <NUM> can be configured to support any type of communications protocol desired. The memory system <NUM> can include one or more memory units <NUM>(<NUM>)-<NUM>(N).

The CPU(s) <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display controller(s) <NUM> sends information to the display(s) <NUM> to be displayed via one or more video processors <NUM>, which process the information to be displayed into a format suitable for the display(s) <NUM>. The display(s) <NUM> can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc..

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques.

Claim 1:
A vector-processor-based device (<NUM>) providing reconfigurable fusion of processing elements, PEs, comprising a vector processor (<NUM>) comprising:
a plurality of PEs (<NUM>(<NUM>)-<NUM>(P)), wherein each PE of the plurality of PEs comprises a plurality of heterogeneous functional units (<NUM>(<NUM>)-<NUM>(F), <NUM>'(<NUM>)-<NUM>'(F)); and
a decode/control circuit (<NUM>) configured to:
receive an instruction block (<NUM>) containing a vectorizable loop (<NUM>) comprising a loop body (<NUM>);
determine a required PE number indicating a number of PEs of the plurality of PEs required to execute the loop body based on a comparison of a number of instructions within the loop body with a number of the plurality of heterogeneous functional units provided by each PE of the plurality of PEs;
reconfigure the plurality of PEs into one or more fused PEs (<NUM>(<NUM>)-<NUM>(F)), wherein each fused PE of the one or more fused PEs comprises the required PE number of PEs of the plurality of PEs;
wherein the one or more fused PEs comprises a plurality of fused PEs; and
wherein each fused PE among the plurality of fused PEs is configured to execute a loop iteration of the loop body in parallel with other fused PEs of the plurality of fused PEs.