Patent Description:
Memory provides data storage for electronic systems. Flash memory is one type of memory, and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.

NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells. It is desired to develop improved NAND architecture.

<CIT> discloses a NAND string having a vertical stack of alternating conductive and insulative levels with the conductive levels having a conductive core and outer conductive layer. Charge blocking material extends vertically along the stack with charge storage material extending vertically along the charge blocking material and an insulative material extending vertically along the charge-storage material.

<NPL>) describe a Nitride-Oxide-Nitride (NON) tunnel barrier for a floating gate memory.

<CIT> relates to a structure comprising a tunneling dielectric layer where an inner sidewall of an outer silicon oxide layer contacts an outer sidewall of a first silicon oxynitride layer, and an inner sidewall of a second silicon oxynitride layer contacts an outer sidewall of an inner silicon oxide layer. Each tunneling dielectric layer can comprise, from outside to inside, an outer silicon oxide layer, the first silicon oxynitride layer having a first atomic nitrogen concentration, the second silicon oxynitride layer having a second atomic nitrogen concentration that is less than the first atomic nitrogen concentration, and the inner silicon oxide layer that contacts a respective vertical semiconductor channel. The first silicon oxynitride layer has a first atomic oxygen concentration, and the second silicon oxynitride layer has a second atomic oxygen concentration that is greater than the first atomic oxygen concentration.

The present invention relates to an integrated structure as set forth in claim <NUM>.

Operation of NAND memory cells comprises movement of charge between a channel material and a charge-storage material; with movement of the "charge" corresponding to movement of charge carriers (i.e., electrons and holes). For instance, programming of a NAND memory cell may comprise moving charge (i.e., electrons) from the channel material into the charge-storage material, and then storing the charge within the charge-storage material. Erasing of the NAND memory cell may comprise moving holes into the charge-storage material to recombine with electrons stored in the charge-storage material, and thereby release charge from the charge-storage material. The charge-storage material may comprise charge-trapping material (for instance, silicon nitride, metal dots, etc.) which reversibly traps charge carriers. It is desired that the charge-trapping material have appropriate charge-trapping probability and/or charge-trapping rate in order that charge carriers are effectively trapped and retained within the charge-trapping material. Charge-trapping probability and charge-trapping rate of a particular charge-trapping material may be related to the volumetric density of charge traps within charge-trapping material, the energy of the charge traps (i.e., the depths of the charge traps in energy wells), etc..

Channel material may be separated from charge-storage material by insulative material, and such insulative material may be characterized by an effective oxide thickness (EOT). It can be desired that the insulative material have sufficient EOT to preclude undesired back-migration (i.e., leakage) of charges from the charge-storage material to the channel material. However, increasing EOT can increase the difficulty of removing trapped charges from materials having relatively deep charge traps. It is therefore desired to engineer insulative materials suitable for spacing charge-storage material from channel material to achieve desired EOT for precluding undesired leakage, while also permitting deeply-trapped charges to be removed during an ERASE operation. Some embodiments include improved NAND memory cells which incorporate bandgap-engineered charge-passage structures within the insulative material between charge-storage structures and channel material. Example embodiments are described with reference to <FIG>.

Referring to <FIG>, a portion of an integrated structure <NUM> is illustrated, with such portion being a fragment of a three-dimensional NAND memory array <NUM>.

The integrated structure <NUM> comprises a stack <NUM> of alternating first and second levels <NUM> and <NUM>. The levels <NUM> are insulative (i.e. dielectric), and the levels <NUM> are conductive.

The insulative levels <NUM> comprise insulative material <NUM>. Such insulative material may comprise any suitable composition or combination of compositions; and may, for example, comprise silicon dioxide.

The conductive levels <NUM> comprise conductive materials <NUM> and <NUM>. The conductive material <NUM> may be considered to be a conductive core, and the conductive material <NUM> may be considered to be an outer conductive layer surrounding the conductive core. The conductive materials <NUM> and <NUM> may comprise different compositions than one another. In some embodiments, the conductive material <NUM> may comprise, consist essentially of, or consist of one or more metals (for instance, tungsten, titanium, etc.), and the conductive material <NUM> may comprise, consist essentially of, or consist of one or more metal-containing compositions (for instance, metal nitride, metal silicide, metal carbide, etc.). In some embodiments, the conductive core material <NUM> may comprise, consist essentially of, or consist of one or more metals (for instance, tungsten, titanium, etc.), and the surrounding conductive material <NUM> may comprise, consist essentially of, or consist of one or more metal nitrides (for instance, titanium nitride, tungsten nitride, etc.).

Insulative material <NUM> forms an insulative liner surrounding the outer conductive layer of material <NUM>. The insulative material <NUM> may comprise high-k material (for instance, aluminum oxide); where the term "high-k" means a dielectric constant greater than that of silicon dioxide.

The materials <NUM>/<NUM> illustrate an example configuration of the conductive levels <NUM>. In other embodiments, the conductive levels <NUM> may comprise other configurations of conductive material. Generally, the conductive levels <NUM> may comprise conductive material having any suitable composition or combination of compositions; and may comprise, for example, one or more of various metals (for example, tungsten, titanium, etc.), metal-containing compositions (for example, metal nitride, metal carbide, metal silicide, etc.), and conductively-doped semiconductor materials (for example, conductively-doped silicon, conductively-doped germanium, etc.).

In some embodiments, the conductive levels <NUM> may be considered to be wordline levels of a NAND memory array. Terminal ends <NUM> of the wordline levels <NUM> may function as control gates of NAND memory cells <NUM>, with approximate locations of the memory cells <NUM> being indicated with brackets in <FIG>.

The conductive levels <NUM> and insulative levels <NUM> may be of any suitable vertical thicknesses. In some embodiments, the conductive levels <NUM> and the insulative levels <NUM> may have vertical thicknesses within a range of from about <NUM> nanometers (nm) to about <NUM>. In some embodiments, the conductive levels <NUM> may have about the same vertical thicknesses as the insulative levels <NUM>. In other embodiments, the conductive levels <NUM> may have substantially different vertical thicknesses than the insulative levels <NUM>.

The vertically-stacked memory cells <NUM> form a vertical string (such as, for example, a vertical NAND string of memory cells), with the number of memory cells in each string being determined by the number of conductive levels <NUM>. The stack may comprise any suitable number of conductive levels. For instance, the stack may have <NUM> conductive levels, <NUM> conductive levels, <NUM> conductive levels, <NUM> conductive levels, <NUM> conductive levels, <NUM> conductive levels, etc..

In the shown embodiment, the insulative materials <NUM> and <NUM> together form vertical sidewalls <NUM>. The vertical sidewalls <NUM> may be considered to be sidewalls of an opening <NUM> extending through stack <NUM>. The opening <NUM> may have a continuous shape when viewed from above; and may be, for example, circular, elliptical, etc. Accordingly, the sidewalls <NUM> of <FIG> may be comprised by a continuous sidewall that extends around the periphery of opening <NUM>.

Charge-blocking material <NUM> extends vertically along the sidewalls <NUM>, and is adjacent the terminal ends <NUM> of wordline levels <NUM>. The charge-blocking material <NUM> forms charge-blocking regions of the memory cells <NUM>. The charge-blocking material <NUM> may comprise any suitable composition or combination of compositions; including, for example, silicon dioxide, one or more high-k dielectric materials, etc. In some embodiments, the insulative material <NUM> and charge-blocking material <NUM> together form charge-blocking regions of the memory cells <NUM>. A charge block may have the following functions in a memory cell: in a program mode, the charge block may prevent charge carriers from passing out of the charge-storage material (e.g., floating-gate material, charge-trapping material, etc.) toward the control gate; and in an erase mode, the charge block may prevent charge carriers from flowing into the charge-storage material from the control gate.

Charge-storage material <NUM> extends vertically along the charge-blocking material <NUM>. The charge-storage material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments, may comprise floating gate material (for instance, doped or undoped silicon) or charge-trapping material (for instance, silicon nitride, metal dots, etc.). In some embodiments, the charge-storage material <NUM> may comprise, consist essentially of, or consist of silicon nitride. In some embodiments, the charge-storage material <NUM> may consist of silicon nitride, and may have a horizontal thickness within a range of from about 50Å to about 80Å.

Insulative material <NUM> extends vertically along the charge-storage material <NUM>. The insulative material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments, comprises one or more oxides (such as, for example, silicon dioxide, etc.). The insulative material <NUM> may comprise any suitable horizontal thickness; and in some embodiments, may comprise a horizontal thickness within a range of from about 10Å to about 30Å.

A charge-passage structure <NUM> extends vertically along the insulative material <NUM>. The charge-passage structure has a central region <NUM> sandwiched between a first region <NUM> and a second region <NUM>. A dashed line <NUM> is provided to diagrammatically illustrate an approximate boundary between the first region <NUM> and the central region <NUM>, and a dashed line <NUM> is provided to diagrammatically illustrate an approximate boundary between the second region <NUM> and the central region <NUM>. In the shown embodiment, the regions <NUM>, <NUM> and <NUM> are all approximately the same horizontal width as one another. In other embodiments, one or more of the regions <NUM>, <NUM> and <NUM> may be of a different horizontal width as compared to others of the regions <NUM>, <NUM> and <NUM>.

The central region <NUM> has a lower charge-trapping probability (and/or a lower charge-trapping rate) as compared to the first and second regions <NUM> and <NUM>. The lower charge-trapping probability (and/or the lower charge-trapping rate) may be related to the central region <NUM> having a lower volumetric density of charge traps than the first and second regions <NUM> and <NUM>; and/or may be related to the central region <NUM> exhibiting shallower charge-trapping behavior as compared the first and second regions <NUM> and <NUM>.

In embodiments in which the central region <NUM> exhibits shallower charge-trapping behavior than the first and second regions <NUM> and <NUM>, the charge-trapping behavior exhibited by each of the regions <NUM>, <NUM> and <NUM> may be averaged behavior across charge trap of the individual regions. Accordingly, regions <NUM> and <NUM> may each have some shallow charge traps, and region <NUM> may have some deep charge traps; but, on average, region <NUM> exhibits shallower charge-trapping behavior than regions <NUM> and <NUM>.

In some embodiments, the central region <NUM> comprises silicon oxynitride, and the first and second regions <NUM>/<NUM> consist of silicon nitride. In some embodiments, the first region <NUM>, second region <NUM> and central region <NUM> all comprise silicon and nitrogen, and additionally the central region <NUM> comprises a higher total concentration of oxygen than either of the first and second regions <NUM>/<NUM>. The first and second regions <NUM> and <NUM> of the charge-passage structure <NUM> may be the same composition as one another, or may be different compositions relative to one another. It can be desired for the central region to comprise silicon in combination with both nitrogen and oxygen, as opposed to the central region comprising only silicon nitride, in order to alleviate parasitic trapping that may be associated with silicon nitride.

The charge-passage structure <NUM> may comprise any suitable horizontal thickness. In some embodiments, a total horizontal thickness of the charge-passage structure <NUM> may be within a range of from about 20Å to about 150Å. In such embodiments, the central region <NUM> may have a thickness within a range of from about one monolayer to about 70Å. In some embodiments, a total horizontal thickness of the charge-passage structure <NUM> may be within a range of from about 20Å to about 100Å, and the central region <NUM> may comprise a horizontal thickness within a range of from about 10Å to about 30Å.

Gate-dielectric material <NUM> extends vertically along the charge-passage structure <NUM>. The gate-dielectric material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide. The gate-dielectric material can function as a material through which charge carriers tunnel or otherwise pass during programming operations, erasing operations, etc. In some contexts, the gate-dielectric material may be referred to simply as an insulative material or a dielectric material.

In some embodiments, the insulative material <NUM> and gate-dielectric material <NUM> both comprise oxide (for instance, both may comprise, consist essentially of, or consist of silicon dioxide), and are referred to as first and second oxides, respectively. In such embodiments, the first oxide <NUM> is directly against a first side <NUM> of the charge-passage structure <NUM>, and the second oxide <NUM> is directly against a second side <NUM> of the charge-passage structure <NUM>; with the second side <NUM> of the charge-passage structure <NUM> being in opposing relation to the first side <NUM> of the charge-passage structure <NUM>. In some embodiments, the first and second oxides <NUM> and <NUM> may have substantially the same horizontal thickness as one another (with the term "substantially the same" meaning the same to within reasonable tolerances of fabrication and measurement), and in other embodiments the first and second oxides <NUM> and <NUM> may have different horizontal thicknesses relative to one another.

Channel material <NUM> extends vertically along the gate-dielectric material <NUM>. The channel material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of appropriately-doped silicon.

In the illustrated embodiment, an insulative region <NUM> extends along a middle of opening <NUM>. The insulative region <NUM> may comprise any suitable insulative composition; including, for example, silicon dioxide, silicon nitride, etc. Alternatively, at least a portion of the insulative region <NUM> may be a gas-filled void. The illustrated embodiment having the insulative region <NUM> extending down the middle of opening <NUM> is a so-called hollow-channel configuration. In other embodiments, the channel material <NUM> may entirely fill the central region of opening <NUM> to form a vertically-extending pedestal within such central region.

The stack <NUM> is supported by a base <NUM>. A break is provided between the base <NUM> and the stack <NUM> to indicate that there may be additional materials and/or integrated circuit structures between the base <NUM> and the stack <NUM>. In some applications, such additional integrated materials may include, for example, source-side select gate material (SGS material).

The base <NUM> may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base <NUM> may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base <NUM> may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc..

The charge-passage structure <NUM> is engineered to have appropriate bandgap properties, etc. to provide sufficient EOT to preclude undesired back-migration (i.e., leakage) of charges from the charge-storage material <NUM> to the channel material <NUM>, while also permitting deeply-trapped charges within the charge-storage material <NUM> to be removed from material <NUM> (i.e., transferred from charge-storage material <NUM> to channel material <NUM>) during an ERASE operation. Some example embodiments of the charge-passage structure <NUM> are described with reference to <FIG>.

Referring to <FIG>, an example charge-passage structure 48a has a central region <NUM> comprising silicon oxynitride (diagrammatically shown as SiON, where the formula indicates primary constituents rather than a specific stoichiometry), and has the first and second regions <NUM>/<NUM> comprising silicon nitride (diagrammatically shown as SiN, where the formula indicates primary constituents rather than a specific stoichiometry). The right side of <FIG> graphically illustrates oxygen concentration [O] as a function of the location across charge-passage structure 48a, and shows that oxygen is only within the central region <NUM>.

<FIG> shows another example charge-passage structure 48b, and shows that oxygen concentration [O] increases in progressing inwardly from surfaces <NUM>/<NUM> toward the center of the charge-passage structure 48b. In some embodiments, surfaces <NUM>/<NUM> may have no measurable oxygen (e.g. may consist of silicon nitride). The oxygen concentration may ramp in any suitable gradient(s) across the first and second regions <NUM>/<NUM>. The oxygen-concentration gradient across the first region <NUM> may be referred to as a first oxygen-concentration gradient <NUM>, and the oxygen-concentration gradient across the second region <NUM> may be referred to as a second oxygen-concentration gradient <NUM>.

The central region <NUM> comprises a total concentration of oxygen which is greater than the total concentration of oxygen in either of the regions <NUM> and <NUM>. In some embodiments, the central region may comprise, consist essentially of, or consist of, silicon, nitrogen and oxygen.

The right side of <FIG> graphically illustrates oxygen concentration [O] as a function of location across charge-passage structure 48b. Notably, in the illustrated embodiment the first and second oxygen-concentration gradients <NUM> and <NUM> are substantially mirror images of one another. Accordingly, the charge-passage structure 48b is substantially mirror symmetric about a plane <NUM> through the middle of the central region <NUM> and midway between the first and second surfaces <NUM> and <NUM>. The term "substantially mirror symmetric" means mirror symmetric to within reasonable tolerances of fabrication and measurement.

In some embodiments, the charge-passage structure (e.g., <NUM> of <FIG>) will not be mirror symmetric about a plane through the middle of the central region <NUM>. Such may be due to different horizontal thicknesses of the first and second regions <NUM> and <NUM> relative to one another, and/or to different compositions within regions <NUM> and <NUM>. <FIG> shows an example charge-passage structure 48c having a different composition within the first region <NUM> as compared to the second region <NUM>. Specifically, the first region <NUM> comprises no measurable oxygen, and is shown consisting of silicon and nitrogen (illustrated as SiN, where the formula indicates primary constituents rather than a specific stoichiometry); and the second region <NUM> comprises an oxygen gradient <NUM> of the type described above with reference to <FIG>. Accordingly, the charge-passage structure 48c is not mirror symmetric about the plane <NUM> through the middle of the central region <NUM> and midway between the first and second surfaces <NUM> and <NUM>. Such is also graphically illustrated on the right side of <FIG> with a graph of oxygen concentration [O] as a function of location across charge-passage structure 48c.

In some embodiments, the charge-passage structures (e.g., <NUM>/48a/48b/48c) may be considered to comprise a central region <NUM> having a lower charge-trapping probability than first and second outer regions <NUM> and <NUM>. In some embodiments, the charge-passage structures (e.g., <NUM>/48a/48b/48c) may be considered to comprise a central region <NUM> having a lower charge-trapping rate than first and second outer regions <NUM> and <NUM>. The charge-trapping probabilities and/or the charge-trapping rates of the charge-trapping regions <NUM>, <NUM> and <NUM> may be related to the volumetric density of charge traps within charge-trapping materials of such regions and/or to the charge-trapping behavior exhibited by the charge-trapping materials of such regions.

For instance, in some embodiments the charge-trapping probabilities and/or the charge-trapping rates of the charge-trapping regions <NUM>, <NUM> and <NUM> are related to the volumetric density of charge traps within charge-trapping materials of such regions. In such embodiments, the charge-passage structures (e.g., <NUM>/48a/48b/48c) may be considered to comprise a central region <NUM> having relatively low volumetric density of charge traps between a first region <NUM> having first relatively high volumetric density of charge traps, and a second region <NUM> having second relatively high volumetric density of charge traps. Such is diagrammatically illustrated with reference to a charge-passage structure 48d of <FIG>. The volumetric density of charge traps in the first region <NUM> may be the same as the that in the second region <NUM>, or may be different than that of the second region <NUM>.

As another example, in some embodiments the charge-trapping probabilities and/or the charge-trapping rates of the charge-trapping regions <NUM>, <NUM> and <NUM> are related to the charge-trapping behavior exhibited by the charge-trapping materials of such regions. In such embodiments, the charge-passage structures (e.g., <NUM>/48a/48b/48c) may be considered to comprise a central region <NUM> which exhibits relatively-shallow-charge-trapping behavior between a first region <NUM> exhibiting relatively-deep-charge-trapping behavior, and a second region <NUM> exhibiting relatively-deep-charge-trapping behavior. Such is diagrammatically illustrated with reference to a charge-passage structure 48e of <FIG>. The charge-trapping behavior exhibited by regions <NUM> and <NUM> may be the same in some embodiments, or may be different in other embodiments (for instance, regions <NUM> and <NUM> may differ in one or more of the trapping energy, the concentration of charge traps per unit volume, the total number of charge traps, etc.).

The charge-passage structures <NUM>/48a/48b/48c/48d may advantageously improve operational characteristics of a NAND memory as compared to conventional NAND memory lacking such charge-passage structures. For instance, the charge-passage structures <NUM>/48a/48b/48c/48d may be tailored to enable desired retention of charge on charge-storage material (e.g., charge-storage material <NUM> of <FIG>) to alleviate or prevent leakage, while also enabling rapid and relatively complete removal of charge from the charge-storage material during erasing operations. In some embodiments, the charge-passage structures <NUM>/48a/48b/48c/48d may advantageously enable improved erase performance of NAND memory as compared to conventional NAND memory lacking such charge-passage structures, without negatively impacting quick charge loss (QCL).

The structures and assemblies described herein may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc..

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc..

The terms "dielectric" and "insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "insulative" (or "electrically insulative") in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.

When a structure is referred to above as being "on" or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on" or "directly against" another structure, there are no intervening structures present.

Structures (e.g., layers, materials, etc.) may be referred to as "extending vertically" to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include a memory cell comprising, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions.

Some embodiments include an integrated structure comprising a vertical stack of alternating conductive levels and insulative levels. Charge-blocking material extends vertically along the vertical stack. Charge-storage material extends vertically along the charge-blocking material. An insulative material extends vertically along the charge-storage material. A charge-passage structure extends vertically along the insulative material, and has a central region sandwiched between first and second regions. The central region having a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Dielectric material extends vertically along the charge-passage structure. Channel material extends vertically along the dielectric material.

Some embodiments include a NAND memory array comprising a vertical stack of alternating insulative levels and wordline levels. Each of the wordline levels comprises a conductive core surrounded by an outer conductive layer. The conductive core comprises a different composition than the outer conductive layer. Charge-blocking material extends vertically along the vertical stack. Charge-storage material extends vertically along the charge-blocking material. An insulative material extends vertically along the charge-storage material. A charge-passage structure extends vertically along the insulative material, and has a central region sandwiched between first and second regions. The central region exhibiting shallower charge-trapping behavior than the first and second regions. Channel material extends vertically along the dielectric material.

Some embodiments include a NAND memory array comprising a vertical stack of alternating insulative levels and wordline levels. Each of the wordline levels comprises a conductive core surrounded by an outer conductive layer. The conductive core comprises a different composition than the outer conductive layer. Charge-blocking material extends vertically along the vertical stack. Charge-storage material extends vertically along the charge-blocking material. An insulative material extends vertically along the charge-storage material. A charge-passage structure extends vertically along the insulative material, and has a central region sandwiched between first and second regions. The central region having a lower volumetric density of charge traps than the first and second regions. Channel material extends vertically along the dielectric material.

Claim 1:
An integrated structure (<NUM>), comprising:
a vertical stack of alternating conductive levels (<NUM>) and insulative levels (<NUM>), the conductive levels (<NUM>) having a conductive core (<NUM>) and an outer conductive layer (<NUM>) surrounding the conductive core (<NUM>);
charge-blocking material (<NUM>) extending vertically along the vertical stack;
charge-storage material (<NUM>) extending vertically along the charge-blocking material (<NUM>);
an insulative material (<NUM>) extending vertically along the charge-storage material (<NUM>);
a charge-passage structure (<NUM>) extending vertically along the insulative material (<NUM>), and having a central region (<NUM>) sandwiched between first (<NUM>) and second (<NUM>) regions, each of the first region (<NUM>), the second region (<NUM>) and central region (<NUM>) containing silicon and nitrogen; the central region (<NUM>) containing nitrogen throughout, having a higher concentration of oxygen than the first (<NUM>) and second (<NUM>) regions and having a lower probability of trapping charges and/or a lower rate of trapping charges than the first (<NUM>) and second (<NUM>) regions;
dielectric material (<NUM>) extending vertically along the charge-passage structure (<NUM>);
channel material (<NUM>) extending vertically along the dielectric material (<NUM>); and
an insulative region (<NUM>) extending vertically along and laterally surrounded by the channel material (<NUM>).