Patent Description:
In the drawings, which are not necessarily drawn to scale, like numerals describe substantially similar components throughout the several views. Like numerals having different letter suffixes represent different instances of substantially similar components.

Reference will now be made in detail to certain embodiments of the disclosed subject matter, examples of which are illustrated in part in the accompanying drawings. While the disclosed subject matter will be described in conjunction with the enumerated claims, it will be understood that the exemplified subject matter is not intended to limit the claims to the disclosed subject matter.

Throughout this document, values expressed in a range format should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. For example, a range of "about <NUM>% to about <NUM>%" or "about <NUM>% to <NUM>%" should be interpreted to include not just about <NUM>% to about <NUM>%, but also the individual values (e.g., <NUM>%, <NUM>%, <NUM>%, and <NUM>%) and the sub-ranges (e.g., <NUM>% to <NUM>%, <NUM>% to <NUM>%, <NUM>% to <NUM>%) within the indicated range. The statement "about X to Y" has the same meaning as "about X to about Y," unless indicated otherwise. Likewise, the statement "about X, Y, or about Z" has the same meaning as "about X, about Y, or about Z," unless indicated otherwise.

In this document, the terms "a," "an," or "the" are used to include one or more than one unless the context clearly dictates otherwise. The term "or" is used to refer to a nonexclusive "or" unless otherwise indicated. The statement "at least one of A and B" has the same meaning as "A, B, or A and B. " In addition, it is to be understood that the phraseology or terminology employed herein, and not otherwise defined, is for the purpose of description only and not of limitation. Any use of section headings is intended to aid reading of the document and is not to be interpreted as limiting; information that is relevant to a section heading may occur within or outside of that particular section.

In the methods described herein, the acts may be carried out in any order without departing from the principles of the disclosure, except when a temporal or operational sequence is explicitly recited. Furthermore, specified acts may be carried out concurrently unless explicit claim language recites that they be carried out separately. For example, a claimed act of doing X and a claimed act of doing Y may be conducted simultaneously within a single operation, and the resulting process will fall within the literal scope of the claimed process.

The term "about", as used herein, may allow for a degree of variability in a value or range, for example, within <NUM>%, within <NUM>%, or within <NUM>% of a stated value or of a stated limit of a range, and includes the exact stated value or range.

The term "substantially", as used herein, refers to a majority of, or mostly, as in at least about <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, <NUM>%, or at least about <NUM>% or more, or <NUM>%.

<FIG> is a cross-sectional diagram of a semiconductor package using an Embedded Multi-die Interconnect Bridge (EMIB™) architecture. In one example, package <NUM> is formed from substrate <NUM> that exhibits a at least partially embedded bridge die <NUM>, which serves as a communication pathway for the surface first and second dies <NUM> and <NUM>. First and second dies <NUM> and <NUM> can be top-mounted active or passive dies. Embedded bridge die <NUM> can be an active die or a passive die. Cover <NUM> covers substrate <NUM> and dies <NUM> and <NUM>. Cooling solution <NUM> such as cooling fins, as shown in this example, are attached to the top of cover <NUM>. A variety of different cooling solutions <NUM> may be used such as conductive plates, integrated heat spreaders, liquid cooling, heat pipes, or radiative fins as shown depending on the particular embodiment. Alternatively, the device may be fabricated without the cooling solution <NUM> and even without cover <NUM>.

Device substrate <NUM> may include internal low density interconnect routing for communicating between surface dies <NUM> and <NUM>. Substrate <NUM> includes embedded components of a semiconductor material (e.g., a silicon, gallium, indium, germanium, or variations or combinations thereof) and one or more insulating layers, such as organic based build up film, glass-reinforced epoxy, such as FR-<NUM>, polytetrafluorethylene (Teflon), cotton-paper reinforced epoxy (CEM-<NUM>), phenolic-glass (G3), paper-phenolic (FR-<NUM> or FR-<NUM>), polyester-glass (CEM-<NUM>), or any other dielectric layer , that may be used in printed circuit boards (PCBs). Substrate <NUM> may be made using a bumpless buildup layer process (BBUL) or other technique. A BBUL process includes one or more build-up layers formed around an element, such as a high density interconnect element or bridge die <NUM> or die <NUM>, <NUM>. A micro via formation process, such as laser drilling, may form connections between build-up layers and die bond pads. The build-up layers may be formed using a high-density integration patterning technology.

Dies <NUM> and <NUM> may be many types of dies. In one example, die <NUM> may be a memory die and die <NUM> may be a central processing unit (CPU) die. Other examples of dies may include a Wi-Fi transmitter and a global positioning system. In some examples, both dies may be the same or different. Other examples may include more than two dies. Dies <NUM> and <NUM> are coupled through C4 bumps <NUM> and vias <NUM> to a power source outside the device (not shown). While only one pair of C4 bumps <NUM> is shown for each die, <NUM>, <NUM> coupled to a single via <NUM>, there may be many connection points for each die <NUM>, <NUM> coupled through many vias <NUM> to connect the dies <NUM>, <NUM> with the device and to external circuitry. The overall package <NUM> may be connected directly to a printed circuit board (PCB) or coupled to a socket that is attached to some other device such as another (PCB).

Dies <NUM> and <NUM> may include low density interconnect pads <NUM> and <NUM>, such as may be used for power, ground, or other electrical coupling. Low density interconnect pad <NUM> may be electrically coupled, such as through low density interconnect element <NUM>, to a bus (not shown) such as a power, ground, or data bus. The low density interconnect pad <NUM> may also be electrically coupled to an electrically conductive pad, such as through conductive adhesive (not shown). The conductive adhesive may be solder (e.g., solder paste), electroplating, or microball, such as a microball configured for flip device interconnect (e.g., controlled collapse device connection (C4) interconnect).

Embedded within the substrate <NUM> is bridge die <NUM> also known as an interconnect bridge. Bridge die <NUM> is made of silicon and has a silica surface. Bridge die <NUM> connects to CPU die <NUM> and memory die <NUM> through bumps or solder balls <NUM> and <NUM>. Interconnect layers <NUM> within the bridge make connections between the pins or lands on each die to pins or lands on the other die <NUM>, <NUM>. In this way, the CPU and memory may communicate data and control information within the package <NUM>.

In one example, as shown in <FIG>, CPU die <NUM> has a first bridge interconnect area <NUM>, including bumps <NUM> closest to memory die <NUM> for connecting through the embedded bridge die <NUM> to memory die <NUM>. CPU die <NUM> has second bridge interconnect area <NUM>, including bumps <NUM>, for connecting with bridge vias. Bumps <NUM> and <NUM> may include any conductive metal such as copper, gold, silver, aluminum, zinc, nickel, brass, bronze, iron, etc..

Bridge die <NUM> includes electrically conductive pads at least partially on or in a top surface of bridge die <NUM>. The electrically conductive pads may include conductive metal, such as copper, gold, silver, aluminum, zinc, nickel, brass, bronze, iron, etc. Bridge die <NUM> includes contact region <NUM> and contact region <NUM>, which connect vias <NUM> and <NUM>, respectively.

In addition, power rail <NUM> above bridge pad layer <NUM> receives power from outside the device through separate power vias (not shown) and provides this power to memory die <NUM> and CPU die <NUM>. Power rail <NUM> may be formed of metal layers deposited over the substrate <NUM>.

In one example, dielectric layer <NUM> may be formed over bridge die <NUM> and substrate <NUM>. Dielectric layer <NUM> allows for dimensional variations in the placement and embedding of the bridge and electrically isolates all of the interconnection areas. Dielectric layer <NUM> may be formed from an epoxy-based resin such as bisphenol A, epoxy resin, a bisphenol F epoxy resin, a novolac epoxy resin, an aliphatic epoxy resin, a glycidylamine epoxy resin, and a glycidylamine epoxy resin, or any other resin including one or more terminal epoxy groups. In some embodiments, dielectric layer <NUM> includes one layer having a thickness ranging from about <NUM> microns to about <NUM> microns or about <NUM> microns to <NUM> microns, or from <NUM> microns to <NUM> microns or about <NUM>, or less than, equal to, or greater than about <NUM> microns, <NUM> microns, <NUM> microns, <NUM> microns, <NUM> microns, <NUM>, microns, or <NUM> microns.

In some examples of package <NUM>, first die <NUM> and second die <NUM> may differ in size with respect to one another. For example, first die <NUM> and second die <NUM> may differ by at least one of volume or surface area. In these examples, it may be desirable to have a heterogenous distribution of bumps <NUM> and <NUM> with respect to each other. By heterogenous it is meant that an average pitch between adjacent bumps <NUM> is different than an average pitch between adjacent bumps <NUM>. The heterogenous distribution of bumps may be a result of a different size by surface area of first bridge interconnect area <NUM> and second bridge interconnect area <NUM>.

<FIG> is a schematic top view of an embodiment of package <NUM> showing first die <NUM> including both first bridge interconnect region <NUM> and interconnect pad <NUM>; second die <NUM> including interconnect pad <NUM>, second bridge interconnect region <NUM>, and breakout regions <NUM>; and bridge die <NUM> (shown in outline). Individual bumps are not shown.

First bridge interconnect region <NUM> may be in a range for from about <NUM> times to about <NUM> times larger than the second bridge interconnect region <NUM>, about <NUM> times to about <NUM> times larger, or less than, equal to, or greater than about <NUM> times, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or about <NUM> times larger than second bridge interconnect region <NUM>. To translate signal between dies <NUM> and <NUM> through bridge die <NUM>, bumps <NUM> are condensed by way of reducing the average pitch there between with respect to the average pitch between bumps <NUM>. For example, an average pitch between bumps <NUM> of first bridge interconnect region <NUM> may be in a range of from about <NUM> times to about <NUM> times greater than the average pitch between adjacent bumps <NUM> of second bridge interconnect region <NUM> about <NUM> times to about <NUM> times greater, or less than, equal to, or greater than about <NUM> times, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or about <NUM> times greater. As examples, the average pitch between bumps <NUM> of region <NUM> may be in a range of from about <NUM> microns to about <NUM> microns, about <NUM> microns to about <NUM> microns, or less than, equal to, or greater than about <NUM> microns, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>,<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or <NUM> microns. As a further example, the average pitch between bumps <NUM> of region <NUM>, may be in a range of from about <NUM> microns to about <NUM> microns, about <NUM> microns to about <NUM> microns, or less than, equal to, or greater than about <NUM> microns, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or about <NUM> microns.

Breakout regions <NUM> are immediately adjacent to second bridge interconnect region <NUM>, and at least partially circumscribed by bridge die <NUM>. Breakout regions <NUM> include a plurality of conductive bumps located on an external surface of die <NUM>. Relative to bumps <NUM>, a pitch between the adjacent bumps <NUM> of breakout regions <NUM> may be in a range of from about <NUM> times to about <NUM> times larger than the pitch of adjacent bumps <NUM> of region <NUM>, about <NUM> times to about <NUM> times larger, or less than, equal to, or greater than about <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or about <NUM> times larger.

Breakout regions <NUM> may allow for the routing of signals from die <NUM> through bridge die <NUM>. The ability to form breakout regions <NUM> is made possible, in part, by reducing the size of second interconnect region <NUM> relative to first interconnect region <NUM>. That is, the space available on second die <NUM> outside of second interconnect region <NUM>, but in contact with bridge die <NUM>, is available for the bumps <NUM> of breakout region <NUM>.

<FIG> is a schematic view of section <NUM> of package <NUM> taken from <FIG> is a top view showing first interconnect region <NUM> including bumps <NUM>; second interconnect region <NUM> including bumps <NUM>, breakout region <NUM> including bumps <NUM>. <FIG> further shows components of bridge die <NUM> including input/outputs <NUM> connected to bumps <NUM> and exposed on a surface of bridge die <NUM>. Bridge die <NUM> further includes VSS <NUM>, VCC <NUM>, and input outputs <NUM> connecting bumps <NUM> and <NUM>. <FIG> is a side view of package <NUM> taken from <FIG> showing the path of input/outputs <NUM>.

<FIG> is a schematic top view of another example package <NUM>. Package <NUM> may include many of the same features as the example of package <NUM> shown and described with respect to <FIG>. In addition to, or in place of those features, bridge die <NUM> may include a plurality of bumps <NUM> located between dies <NUM> and <NUM>. Bumps <NUM> may be attached to input/outputs to send or receive a signal directly between bridge die <NUM> and any other component.

Package <NUM> may be manufactured according to any suitable method. For example, bumps <NUM>, <NUM>, and <NUM> may be formed on respective interconnect regions <NUM>, <NUM>, and breakout regions <NUM> by depositing a conductive metallic precursor thereon. As an example, the precursor may include electrolytic copper. The electrolytic copper may be deposited as a liquid and electroplated thereon. The bumps may be formed directly on vias of any one of dies <NUM>, <NUM>, or <NUM>. Bumps <NUM>, <NUM>, and <NUM> may be connected to a via or transmission line through soldering the respective bump and transmission line or via.

<FIG> illustrates a system level diagram, according to an embodiment of the invention. For instance, <FIG> depicts an example of an electronic device (e.g., system) including package <NUM>; <FIG> is included to show an example of a higher level device application for the present subject matter. In an embodiment, system <NUM> includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system <NUM> is a system on a chip (SOC) system.

In an embodiment, processor <NUM> has one or more processing cores <NUM> and 612N, where 612N represents the Nth processor core inside processor <NUM> where N is a positive integer. In an embodiment, system <NUM> includes multiple processors including <NUM> and <NUM>, where processor <NUM> has logic similar or identical to the logic of processor <NUM>. In some embodiments, processor core <NUM> includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, and the like. In some embodiments, processor <NUM> has a cache memory <NUM> to cache instructions and/or data for system <NUM>. Cache memory <NUM> may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor <NUM> includes a memory controller <NUM>, which is operable to perform functions that enable the processor <NUM> to access and communicate with memory <NUM> that includes a volatile memory <NUM> and/or a non-volatile memory <NUM>. In some embodiments, processor <NUM> is coupled with memory <NUM> and chipset <NUM>. Processor <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to transmit and/or receive wireless signals. In an embodiment, the wireless antenna <NUM> operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In some embodiments, volatile memory <NUM> includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory <NUM> includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Memory <NUM> stores information and instructions to be executed by processor <NUM>. In an embodiment, memory <NUM> may also store temporary variables or other intermediate information while processor <NUM> is executing instructions. In the illustrated embodiment, chipset <NUM> connects with processor <NUM> via point-to-point (PtP or P-P) interfaces <NUM> and <NUM>. Chipset <NUM> enables processor <NUM> to connect to other elements in system <NUM>. In some embodiments of the invention, interfaces <NUM> and <NUM> operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset <NUM> is operable to communicate with processor <NUM>, 605N, display device <NUM>, and other devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. Chipset <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to transmit and/or receive wireless signals.

Chipset <NUM> connects to display device <NUM> via interface <NUM>. Display device <NUM> may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device <NUM>. In some embodiments of the invention, processor <NUM> and chipset <NUM> are merged into a single SOC. In addition, chipset <NUM> connects to one or more buses <NUM> and <NUM> that interconnect various elements <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Buses <NUM> and <NUM> may be interconnected together via a bus bridge <NUM>. In an embodiment, chipset <NUM> couples with a non-volatile memory <NUM>, a mass storage device(s) <NUM>, a keyboard/mouse <NUM>, and a network interface <NUM> via interface <NUM> and/or <NUM>, smart TV <NUM>, consumer electronics <NUM>, etc..

In an embodiment, mass storage device <NUM> includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In an embodiment, network interface <NUM> is implemented by any type of well known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In an embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

While the modules shown in <FIG> are depicted as separate blocks within the system <NUM>, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory <NUM> is depicted as a separate block within processor <NUM>, cache memory <NUM> (or selected aspects of cache memory <NUM>) may be incorporated into processing core <NUM>.

The terms and expressions that have been employed are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the embodiments of the present disclosure. Thus, it should be understood that although the present disclosure has been specifically disclosed by specific embodiments and optional features, modification and variation of the concepts herein disclosed may be resorted to by those of ordinary skill in the art, and that such modifications and variations are considered to be within the scope of embodiments of the present disclosure.

There are many reasons to use package <NUM>, including the following non-limiting reasons. For example, according to various embodiments, dies <NUM> and <NUM> may differ in size with respect to each other. Varying the pitch of bumps <NUM> and <NUM> with respect to each other may help to ensure that reliable transmission of signals through bridge die <NUM> is maintained. Additionally, the reduced size of second interconnect region <NUM>, compared to first interconnect region <NUM>, creates space on die <NUM> to allow for breakout regions <NUM> to be located thereon. According to some embodiments, breakout regions <NUM> may allow for direct routing of signals from die <NUM>, or any other die that breakout region <NUM> is located on, to be routed directly through bridge die <NUM> to an external component. According to some embodiments, the presence of breakout region <NUM> or bumps <NUM> may allow for testing or debugging signals to be sent directly through bridge die <NUM>.

According to some embodiments, in previous designs bump pitch mismatch between die with a smaller pitch between adjacent bumps results in bumps not related (e.g., differing in pitch) relative to the pitch of the bumps of a bridge die. However, according to some embodiments, syncing the pitch between bumps of first or second dies <NUM> and <NUM> with those of bridge die <NUM> can free up surface area on bridge die <NUM> that may be utilized to escape signals via on-bridge routing to the surface layer of package <NUM> to effectively utilize the surface area. The following examples of semiconductor packages and methods of making semiconductor packages are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

As an example, a semiconductor package is provided. The semiconductor package includes a first die including a first bridge interconnect region. The semiconductor package includes a second die including a second bridge interconnect region. The semiconductor package includes a bridge die including a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. The first bridge interconnect region is larger than the second bridge interconnect region. Each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

An example provides the semiconductor package of other examples, further including a substrate wherein at least one of the first die, the second die, and the bridge die are at least partially embedded therein.

An example provides the semiconductor package of other examples, wherein at least one of the first die, the second die, and the bridge die include silicon.

An example provides the semiconductor package of other examples, wherein at least one of the first die and the second die are independently chosen from a central processing unit, a flash memory, a Wi-Fi transmitter, and a global positioning system.

An example provides the semiconductor package of other examples, wherein an average pitch between bumps of the first bridge interconnect region is in a range of from about <NUM> times to about <NUM> times greater than the average pitch between adjacent bumps of the second bridge interconnect region.

An example provides the semiconductor package of other examples, wherein an average pitch between bumps of the first bridge interconnect region is in a range of from about <NUM> microns to about <NUM> microns.

An example provides the semiconductor package of other examples, wherein an average pitch between bumps of the second bridge interconnect region is in a range of from about <NUM> microns to about <NUM> microns.

An example provides the semiconductor package of other examples, wherein the first die is larger by at least one of surface area and volume than the second die.

An example provides the semiconductor package of other examples, wherein the conductive bumps of at least one of the first bridge interconnect region and the second bridge interconnect region include copper.

An example provides the semiconductor package of other examples, wherein the first bridge interconnect region is in a range of from about <NUM> times to about <NUM> times larger than the second bridge interconnect region.

An example provides the semiconductor package of other examples, wherein the first bridge interconnect region is in a range for from about <NUM> times to about <NUM> times larger than the second bridge interconnect region.

An example provides the semiconductor package of other examples, wherein the second die further includes a first breakout region including a plurality of conductive bumps located adjacent the second interconnect region at a first location.

An example provides the semiconductor package of other examples, wherein the second die further includes a second breakout region including a plurality of conductive bumps located adjacent the second interconnect region at a second location.

An example provides the semiconductor package of other examples, wherein at least one of the first breakout region and the second breakout region are at least partially circumscribed by the bridge die.

An example provides the semiconductor package of other examples, further including a plurality of at least one of inputs and outputs connected to the conductive bumps of at least one of the first breakout region and the second breakout region.

An example provides the semiconductor package of other examples, wherein a pitch between the adjacent bumps of at least one of the first breakout region and the second breakout region is in a range of from about <NUM> times to about <NUM> times larger than the pitch of adjacent bumps of the second interconnect region.

An example provides the semiconductor package of other examples, further including a plurality of conductive bumps located on the bridge die at a location between the first die and the second die.

An example provides the semiconductor package of other examples, wherein a pitch between adjacent conductive bumps of the bridge may be in a range of from about <NUM> to about <NUM>.

An example provides a semiconductor package including a first die including a first bridge interconnect region. The semiconductor package includes a second die including a second bridge interconnect region. The semiconductor package includes a bridge die including a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. The first bridge interconnect region is larger than the second bridge interconnect region. The first die is larger by at least one of surface area and volume than the second die. Each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between bumps of the first bridge interconnect region is in a range of from about <NUM> times to about <NUM> times greater than the average pitch between adjacent bumps of the second bridge interconnect region.

An example provides the semiconductor package of other examples, further including a plurality of conductive bumps located on the bridge at a location between the first die and the second die.

An example provides a method of making a semiconductor package. The method includes connecting a first die to a bridge die along a first bridge interconnect region. The method further includes connecting a second die to the bridge die along a second bridge interconnect region. The first bridge interconnect region is larger than the second bridge interconnect region. Each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

An example provides the method of other examples, further including at least partially embedding at least one of the first die, the second die, and the bridge die in a substrate.

An example provides the semiconductor package of other examples, further comprising a plurality of at least one of inputs and outputs connected to the conductive bumps of at least one of the first breakout region and the second breakout region.

Claim 1:
A semiconductor package (<NUM>) comprising:
a first die (<NUM>) comprising a first bridge interconnect region (<NUM>);
a second die (<NUM>) comprising a second bridge interconnect region (<NUM>);
a bridge die (<NUM>) comprising a first contact area (<NUM>) to connect to the first bridge interconnect region (<NUM>) and a second contact area (<NUM>) to connect to the second bridge interconnect region (<NUM>),
wherein the first bridge interconnect region (<NUM>) is larger than the second bridge interconnect region (<NUM>);
each of the first bridge interconnect region (<NUM>) and the second bridge interconnect region (<NUM>) comprise a plurality of conductive bumps (<NUM>, <NUM>); and
an average pitch between adjacent bumps (<NUM>) of the first bridge interconnect region (<NUM>) is larger than an average pitch between adjacent bumps (<NUM>) of the second bridge interconnect region (<NUM>).