Patent Description:
In electronic systems, such as a radio frequency (RF) transceiver of a mobile phone, a system clock is typically generated using a crystal oscillator. A crystal oscillator comprises an active part and a resonator. The active part comprises an amplifier and is commonly referred to as the oscillator core. The resonator, which comprises a piezoelectric crystal, is coupled between an input of the active part and an output of the active part. The oscillator core may be integrated with a transceiver in an integrated circuit, the crystal being external to the integrated circuit, or the oscillator core and crystal may be implemented in a module, such as a temperature controlled crystal oscillator (TCXO), external to a transceiver integrated circuit.

Shrinking of the dimensions of piezoelectric crystals has led to an increase of motional loss of the crystal, which can be quantified as an increase in resistive loss, or resistance, of the crystal. The spread of resistance between different crystals is typically large compared to the mean value of resistance averaged over many crystals. Indeed, the maximum value of resistance can be much greater than the mean value. For example, a <NUM> crystal in an industry standard <NUM> size package, which has dimensions <NUM> by <NUM>. <NUM>, may have a resistance ranging from 10Ω to 80Ω. This spread makes it challenging to design a crystal oscillator circuit able to cope with the spread of resistance. Additionally, the negative resistance of the oscillator core should be arranged to ensure oscillator start-up, negative resistance being the property whereby a voltage decreases in response to an increasing current, but integrated circuit process variation can result in a spread in the negative resistance of the oscillator core.

There is a requirement for an improved oscillator circuit.

<CIT> discloses an amplitude control circuit that includes a pair of peak detectors. The pair of peak detectors are responsive to a voltage reference generator. The amplitude control circuit is configured to be responsive to an oscillating signal of a crystal oscillator and configured to generate a control signal to control an amplitude of the oscillating signal.

<CIT> discloses an oscillator that includes a reference voltage generator, an oscillation element configured to oscillate by either a drive voltage or a drive current and output an oscillation signal, a peak hold element configured to detect a peak level of the oscillation signal for output; and a controller configured to increase or decrease the drive voltage or drive current in accordance with the reference voltage generated by the reference voltage generator and the peak level output from the peak hold element.

<CIT> discloses an oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.

<CIT> discloses a circuit which controls an oscillation amplitude of a crystal oscillator including a crystal resonator, a current source supplying a bias current, and an output transistor coupled to the crystal resonator and the current source. The circuit includes a peak detector for detecting a peak voltage of an output signal of the crystal oscillator, and a controller coupled to the peak detector and to the current source for controlling the current source in accordance with a difference between the peak voltage and a target voltage, the target voltage being set to be substantially equal to 2Vth, where Vth is a threshold voltage of the output transistor. A frequency control circuit controls a first switched-capacitor array and a second switched-capacitor array coupled to the crystal resonator, and alternately switches a unit capacitor in the first switched-capacitor array and a unit capacitor in the second switched-capacitor array based on a frequency control signal.

<CIT> discloses a semiconductor integrated circuit having a constant voltage generation circuit and an oscillation circuit for generating a clock signal. The constant voltage generation circuit supplies a first voltage to the oscillation circuit until the clock signal is stabilized and the constant voltage generation circuit supplies a second voltage lower than the first voltage to the oscillation circuit after the clock signal has been stabilized.

<CIT> discloses a frequency source having a fast start-up time and low noise in steady state. The frequency source includes an oscillator and a hybrid automatic gain control (AGC) loop that switches between an analog AGC loop at oscillator start up and a digital AGC loop at steady state operation. The analog AGC loop includes a peak detector connected to the oscillator and an error integrator integrating the difference between the peak detector output and a reference voltage. The digital AGC loop includes a comparator comparing the peak detector output and high/low reference voltages, an oscillator counter providing a timer signal, a digital-to-analog converter (DAC) supplied with a digital word, and a low pass filter between the DAC and the oscillator. The timer signal causes a multiplexer to select either the analog AGC loop or the digital AGC loop.

<CIT> discloses an oscillation device that is provided with an inverter for inputting the output amplitude of a crystal oscillation circuit, and for changing an output pulse width according to the change of the output amplitude, and configured to detect the amplitude of the oscillation signal of the crystal oscillation circuit by monitoring the change of the pulse width (duty rate) of a pulse signal outputted from the inverter, and to detect the amplitude of the oscillation signal of the crystal oscillation circuit, and to control the driving voltage VOSC of the crystal oscillation circuit so that the output amplitude of the crystal oscillation circuit can be put in a state immediately before it is saturated based on the detection result.

<CIT> discloses a signal source for generating a well-controlled, predictable oscillating output signal within a short, predetermined and constant start-up time is disclosed. The invention includes a switchable current source for selectively providing an electrical signal to a tank circuit which, in response, provides an oscillating output signal. A control circuit, comprising a comparator is connected to the tank circuit for providing a control signal to the switchable current source which causes the current source to switch in response to the output signal. Particular embodiments of the invention include means for controlling the amplitude of the oscillating output signal, means for controlling the transconductance of the current source, and means for starting the signal source.

According to a first aspect there is provided an oscillator circuit and method as defined in the appended claims.

According to a third aspect, there is provided a wireless communication device comprising the oscillator circuit of the first aspect.

Preferred embodiments are described, by way of example only, with reference to the accompanying drawings.

Referring to <FIG>, a first preferred embodiment of an oscillator circuit <NUM> comprises a crystal oscillator (XO) <NUM>, a bias current generator <NUM> and a feedback stage <NUM>. The crystal oscillator <NUM> has an input <NUM> coupled to an output <NUM> of the bias current generator <NUM> for receiving a bias current is generated by the bias current generator <NUM>, and an output <NUM> coupled to an output <NUM> of the oscillator circuit <NUM> for delivering an oscillation signal SO. The feedback stage <NUM> has an input <NUM> coupled to the output <NUM> of the crystal oscillator <NUM> for receiving the oscillation signal SO, and an output <NUM> for delivering a feedback signal SF.

The feedback stage <NUM> comprises an amplitude detector <NUM> coupled to the input <NUM> of the feedback stage <NUM>. The amplitude detector <NUM> generates an indication SA of the amplitude of the oscillation signal SO. The feedback stage <NUM> also comprises a comparator <NUM> coupled to the amplitude detector <NUM> for receiving the indication SA of the amplitude of the oscillation signal SO. The comparator <NUM> is also coupled to an amplitude threshold REF. When the oscillator circuit <NUM> is powered-up, and consequently the amplitude of the oscillation signal SO increases from zero, the comparator <NUM> generates a feedback signal SF in response to the amplitude of the oscillation signal SO, and therefore the indication SA, reaching the amplitude threshold REF. The comparator <NUM> is coupled to the output <NUM> of the feedback stage <NUM> for delivering the feedback signal SF.

The output <NUM> of the feedback stage <NUM> is coupled to a first input <NUM> of the bias current generator <NUM>. The bias current generator <NUM> has a second input <NUM> for an initialisation signal SI, and a third input <NUM> for a wake-up signal SW. The initialisation signal SI indicates to the oscillator circuit <NUM> when the oscillator circuit <NUM> is required to commence oscillation from an initial power-off state, when initialisation is required, and the wake-up signal SW indicates when the oscillator circuit <NUM> is required to commence oscillation from a subsequent power-off state, when initialisation is not required again. Power supply connections to the oscillator circuit <NUM> are not illustrated in <FIG>, for clarity. The bias current generator <NUM> comprises a current source <NUM> coupled to the output <NUM> of the bias current generator <NUM> for generating the bias current IB. The current source <NUM> has a control input <NUM> for controlling the magnitude of the bias current, as described below.

The bias current generator <NUM> comprises an auxiliary clock signal generator <NUM> that generates an auxiliary clock signal SC. The auxiliary clock signal generator <NUM> comprises an auxiliary oscillator <NUM> that generates an auxiliary oscillation signal SX, coupled to a frequency divider <NUM> that generates the auxiliary clock signal SC by dividing the auxiliary oscillation signal SX. The frequency divider <NUM> may have a division ratio of, for example, one hundred, with the auxiliary oscillation signal SX having a frequency of, for example, <NUM> and the auxiliary clock signal SC having a frequency of <NUM>. An output <NUM> of the auxiliary clock signal generator <NUM>, corresponding to an output of the frequency divider <NUM>, is coupled to a counter <NUM> that generates a count value NC by counting pulses, that is, cycles, of the auxiliary clock signal SC. Therefore, the count value NC increases in a step-wise manner. In a non-illustrated variant of the bias current generator <NUM>, the frequency divider <NUM> may be omitted, in which case the output <NUM> of the auxiliary clock signal generator <NUM> corresponds to an output of the auxiliary oscillator <NUM>, and is coupled to the counter <NUM>. In this case, the auxiliary oscillation signal SX is used as the auxiliary clock signal SC, and the auxiliary clock signal SC has a frequency equal to a frequency of the auxiliary oscillation signal SX, for example <NUM>.

An output <NUM> of the counter <NUM> is coupled to an input <NUM> of a digital-to-analogue (DAC) converter <NUM> via a switch <NUM>. A storage device (STORE) <NUM> is coupled to the input <NUM> of the DAC <NUM>, and therefore is also coupled to the to the output <NUM> of the counter <NUM> via the switch <NUM>. In a first state of the switch <NUM>, in which the switch <NUM> is closed, that is, is in a conducting state, the count value NC is delivered from the output <NUM> of the counter <NUM> to the input <NUM> of the DAC <NUM>, and to the storage device <NUM> for storing the current count value NC. This stored value is denoted NS. In a second state of the switch <NUM>, in which the switch <NUM> is open, that is, is in a non-conducting state, the output <NUM> of the counter <NUM> is de-coupled from the input <NUM> of the DAC <NUM>, and from the storage device <NUM>, and in this state the stored value NS, instead of the increasing count value NC, is delivered to the input <NUM> of the DAC <NUM>. Therefore, depending on the state of the switch <NUM>, the storage device <NUM> is arranged to either store a new count value NC, or to output the stored value NS, as described in detail below. An output <NUM> of the DAC <NUM> is coupled to the control input <NUM> of the current source <NUM> for controlling the magnitude of the bias current IB dependent on the increasing count value NC delivered at the output <NUM> of the counter <NUM>, or the stored value NS which is constant, according to the state of the switch <NUM>.

The bias current generator <NUM> also comprises a controller <NUM> coupled to the first, second and third inputs <NUM>, <NUM>, <NUM> of the bias current generator <NUM> for receiving, respectively, the feedback signal SF, the initialisation signal SI and the wake-up signal SW. The controller <NUM> is also coupled to the auxiliary oscillator <NUM> for starting and stopping generation of the auxiliary clock signal SC, to the counter <NUM> for starting and resetting the counting of the pulses of the auxiliary clock signal SC, to the switch <NUM> for controlling whether the switch <NUM> has the first state or the second state, and to the storage device <NUM> for initiating storage of the current count value NC into the storage device <NUM> and reading of the stored value NS from the storage device <NUM>.

Operation of the oscillator circuit <NUM> is described below with reference to the flow chart of <FIG>, assuming that the oscillator circuit <NUM> is initially switched off, that is, is not supplied with power and therefore is not generating the oscillation signal SO or the auxiliary clock signal SC. At step <NUM>, power is switched on, thereby supplying power to the oscillator circuit <NUM>. This power-on condition is detected in the oscillator circuit <NUM> by means of the initialisation signal SI at the second input <NUM> of the bias current generator <NUM>, which is supplied to the controller <NUM>.

In response to the initialisation signal SI, at step <NUM> the controller <NUM> initialises the count value NC of the counter <NUM> to zero, sets the switch <NUM> into the first state, thereby enabling the count value NC to be routed to the DAC <NUM>, and then enables the auxiliary oscillator <NUM> to start generating the auxiliary clock signal SC. With the count value NC initialised to zero, the bias current IB has a first level that is zero or near zero, being insufficient to sustain oscillation of the crystal oscillator <NUM> for the expected spread of crystal resistance and the expected spread of negative resistance of the active part.

At step <NUM>, the counter <NUM> increments in response to receiving a pulse of the auxiliary clock signal SC from the auxiliary oscillator <NUM>, thereby increasing the count value NC, and consequently increasing the bias current IB supplied to the crystal oscillator <NUM>. Although the count value NC increments in a step-wise manner, smoothing may take place in the current source <NUM> such that the bias current IB increases in a more gradual manner.

At step <NUM>, the amplitude detector <NUM> detects the amplitude of the oscillation signal SO and generates the indication SA of the amplitude of the oscillation signal SO. This amplitude will be zero if the crystal oscillator <NUM> has not yet started to oscillate.

At step <NUM>, the comparator <NUM> compares the indication SA with the amplitude reference REF. If the indication SA is less than the amplitude reference REF, the feedback signal SF is not generated at the output <NUM> of the feedback stage <NUM>, and flow returns to step <NUM> where the counter <NUM> again increments in response to receiving a further pulse of the auxiliary clock signal SC from the auxiliary oscillator <NUM>, thereby further increasing the count value NC, and consequently further increasing the bias current IB supplied to the crystal oscillator <NUM>. The loop comprising steps <NUM>, <NUM> and <NUM> is repeated, thereby successively increasing the bias current IB with each iteration. While the count value NC is low, the bias current IB may be insufficient to sustain oscillation of the crystal oscillator <NUM>. As the count value NC increases, the bias current IB increases to a level sufficient to sustain oscillation of the crystal oscillator <NUM>. As the count value NC increases further, the bias current IB increases further, thereby enabling the amplitude of the oscillation signal SO to increase.

If, at step <NUM>, the comparator <NUM> determines that the indication SA is equal to, or greater than, the amplitude reference REF, flow proceeds to step <NUM> where the feedback signal SF is generated at the output <NUM> of the feedback stage <NUM>. Flow then proceeds to step <NUM>.

At step <NUM>, in response to the feedback signal SF, the controller <NUM> enables the storage device <NUM> to store the current count value NC, that is NS, and sets the switch <NUM> into the second state, thereby enabling the stored value NS to be routed to the DAC <NUM>. Consequently, for subsequent oscillation, the bias current IB becomes constant at a second level dependent on the stored value NS. Also at step <NUM>, the controller <NUM> may disable the auxiliary oscillator <NUM> and the counter <NUM> in order to conserve power.

The rate of increase of the count value NC, and consequently the rate of increase of the bias current IB and of the amplitude of the oscillation signal SO, depends on the frequency of the auxiliary clock signal SC, and this frequency may be selected to ensure that the rate of increase of the amplitude of the oscillation signal SO is sufficiently slow to avoid generation of unwanted parasitic oscillations. For example, if the oscillation signal SO has a frequency of <NUM> and the frequency of the auxiliary clock signal SC is <NUM>, the oscillation signal SO will have <NUM> cycles for each increment of the count value NC and each increment of the bias current IB. If, on average, <NUM> increments are required before the feedback signal SF is generated, the start-up time will on average be about <NUM>. More generally, the auxiliary clock signal SC preferably has a frequency lower than the frequency of the oscillation signal SO, for example not exceeding one tenth, or not exceeding one hundredth, or not exceeding one thousandth of the frequency of the oscillation signal SO.

Furthermore, the rate of increase of the amplitude of the oscillation signal SO, and also the bias current required for the oscillation signal SO to attain the amplitude corresponding to the amplitude reference REF, depends on the characteristics of the crystal oscillator <NUM>, and in particular on the resistance of the crystal employed by the crystal oscillator <NUM> and on the negative resistance of the oscillator core. Therefore the stored value NS will also depend on these factors, and is adapted by the oscillator circuit <NUM> dependent on these factors.

For subsequent powering-on of the oscillator circuit <NUM>, after an intervening power-off period in which power to the oscillator circuit <NUM> is switched off, the level of the bias current IB may be established dependent on the stored value NS, without requiring to perform the initialisation process of increasing the bias current IB in response to the increasing count value NC. Therefore, subsequent start-up of the oscillator circuit <NUM> may be faster than the start-up when the initialisation process is performed. In this case, the storage device <NUM> should be non-volatile, retaining the stored value NS while power is switched off. The initialisation process may be performed when power to the oscillator circuit <NUM> is switched from off to on, for example during manufacture of the oscillator circuit <NUM> or manufacture of a device comprising the oscillator circuit <NUM>, or when a user of a device comprising the oscillator circuit <NUM> initiates powering-on by pushing a power-on button. In a mobile phone, for example, it may be acceptable for such initialisation of the oscillator circuit <NUM> to take <NUM>. For subsequent powering-on of the oscillator circuit <NUM> when the count value NC has previously been stored as the stored value NS, for example when the oscillator circuit <NUM> or a device comprising the oscillator circuit <NUM> wakes up from a sleep mode, initialisation is not required and the level of the bias current IB may be established dependent on the stored value NS. In a mobile phone, for example, such a wake-up may be performed within <NUM>.

Although at step <NUM> the current count value NC is stored in the storage device <NUM>, in a variant of the oscillator circuit <NUM>, the storage device <NUM> and the switch <NUM> may be omitted and, under the control of the controller <NUM>, the counter <NUM> may cease counting and retain the final count value NC reached, with this final count value NC being delivered to the input <NUM> of the DAC <NUM> for subsequent oscillation of the crystal oscillator <NUM>. This variant is suitable in circumstances where, for example, the initialisation is performed every time the oscillator circuit <NUM> is powered-up and the time required to perform the initialisation on each such occasion is tolerable.

Although at step <NUM> the current count value NC is stored, corresponding to the final count value NC, and consequently corresponding to the final level of the bias current IB, reached when the increasing is terminated, in a variant of the oscillator circuit <NUM> the stored value NS may be different from the final count value NC, and in particular may be lower than the final count value NC by a predetermined amount, for example by a single increment. This variant may be employed in circumstances where the amplitude of the oscillation signal SO may overshoot a desired maximum value during the increasing of the bias current IB due to the count value NC being quantised. In this case, the bias current IB supplied during subsequent operation of the crystal oscillator <NUM>, and which is dependent on the stored value NS, may be lower than the final level of the bias current IB reached when the increasing is terminated, thereby ensuring the amplitude of the oscillation signal SO does not exceed the desired maximum, but nevertheless is dependent on this final level. More generally, during subsequent operation of the crystal oscillator <NUM>, that is, after the initialisation process, the bias current IB is supplied at a second level dependent on, and optionally but not necessarily equal to, the final level of the bias current IB reached when the increasing of the bias current IB is terminated. Likewise, when the oscillator circuit <NUM> is subsequently powered-on, after an intervening power-off period in which power to the oscillator circuit <NUM> is switched off, and the bias current IB is dependent on the stored value NS, rather than being determined by performing the initialisation process of increasing the bias current IB, the bias current IB may be at a third level dependent on the stored value NS, the third level being optionally but not necessarily equal to the final level of the bias current IB reached when the increasing of the bias current IB is terminated during the initialisation process. The second and third levels may be equal.

Referring to <FIG>, a second preferred embodiment of an oscillator circuit <NUM> comprises the crystal oscillator <NUM> and the feedback stage <NUM> as described with reference to <FIG> coupled to a bias current generator <NUM> that has the same inputs and outputs as the bias current generator <NUM> described with reference to <FIG>, but a different internal architecture. Therefore, the description in the following paragraphs of the oscillator circuit <NUM> is focussed principally on the internal architecture of the bias current generator <NUM>. The crystal oscillator <NUM> and the feedback stage <NUM> and their connections are not described again.

The bias current generator <NUM> comprises an integrator <NUM> coupled to a power supply voltage Vdd via a switch <NUM>. In <FIG>, the integrator <NUM> is illustrated as a simple resistor-capacitor (RC) network, but other integration circuits may alternatively be used. In response to the switch <NUM> closing, the integrator <NUM> generates an increasing ramp voltage VR at an output <NUM> of the integrator <NUM>. The bias current generator <NUM> also comprises the current source <NUM>, and the output <NUM> of the integrator <NUM> is coupled to the control input <NUM> of the current source <NUM> which therefore generates the bias current IB having a level, that is, magnitude, dependent on the ramp voltage VR. Therefore, the bias current IB increases as the ramp voltage VR at the control input <NUM> of the current source <NUM> increases.

The bias current generator <NUM> also comprises a controller <NUM> coupled to the first, second and third inputs <NUM>, <NUM>, <NUM> of the bias current generator <NUM> for receiving, respectively, the feedback signal SF, the initialisation signal SI and the wake-up signal SW. The controller <NUM> is also coupled to the switch <NUM> for controlling the starting and stopping of the generation of the ramp voltage VR, and to the integrator <NUM> for resetting any voltage stored in the integrator <NUM> to zero or a low value.

Operation of the bias current generator <NUM> is described below assuming that the oscillator circuit <NUM> is initially switched off, that is, is not supplied with power and therefore is not generating the oscillation signal SO, and that the switch <NUM> is initially open, that is, is in a non-conducting state. In response to the initialisation signal SI, the controller <NUM> resets the voltage stored in the integrator <NUM> and closes the switch <NUM>. The voltage stored in the integrator <NUM> starts to increase, thereby providing the ramp voltage VR, and consequently the bias current IB starts to increase in level from a first level which may be zero or small, being insufficient to sustain oscillation of the crystal oscillator <NUM>. When the amplitude of the oscillation signal SO reaches the amplitude reference REF, the feedback signal SF is generated by the feedback stage <NUM>. In response to the feedback signal SF, the controller <NUM> opens the switch <NUM>. Consequently, the ramp voltage VR stops increasing, and the final level reached by the ramp voltage VR is stored in the integrator <NUM>, thereby causing the bias current IB to cease increasing and become constant at a second level, corresponding to the final level of the ramp voltage VR.

In response to the wake-up signal SW, when the oscillator circuit <NUM> is required to commence oscillation from a subsequent power-off state, when initialisation is not required again, the level of the bias current IB is constant at the second level, being dependent on the voltage stored in the integrator <NUM>.

The rate of increase of the bias current IB while the ramp voltage VR is increasing, and consequently the rate of increase of the amplitude of the oscillation signal SO, depends on the integration time constant of the integrator <NUM>, and this time constant may be selected to be sufficiently slow to avoid generation of unwanted parasitic oscillations.

Referring to <FIG>, a wireless communication device <NUM> comprises an antenna <NUM> coupled to an input of a low noise amplifier <NUM> for amplifying an RF signal received by the antenna <NUM>. An output of the low noise amplifier <NUM> is coupled to a first input <NUM> of a down-conversion stage <NUM> for down-converting the amplified RF signal to baseband by mixing the amplified RF signal with quadrature related components of a local oscillator signal present at a second input <NUM> of the down-conversion stage <NUM>. After the down-conversion, therefore, the baseband signal comprises quadrature related components. An output <NUM> of the down-conversion stage <NUM> is coupled to an input <NUM> of a digital signal processor (DSP) <NUM> via an analogue-to-digital converter (ADC) <NUM> that digitises the quadrature related components of the baseband signal. The DSP <NUM> demodulates and decodes the digitised baseband signal. The DSP <NUM> also generates, at an output <NUM> of the DSP <NUM>, quadrature related components of a baseband signal for up-conversion. The output <NUM> of the DSP <NUM> is coupled to a first input <NUM> of an up-conversion stage <NUM> via a DAC <NUM>. The up-conversion stage <NUM> up-converts the baseband signal to RF for transmission by mixing the quadrature related components of the baseband signal with quadrature related components of the local oscillator signal present at a second input <NUM> of the up-conversion stage <NUM>. An output <NUM> of the up-conversion stage <NUM> is coupled to the antenna <NUM> via a power amplifier <NUM> that amplifies the RF signal for transmission. The wireless communication device <NUM> comprises the oscillator circuit <NUM>, or alternatively may comprise the oscillator circuit <NUM>. The output <NUM> of the oscillator circuit <NUM> is coupled to an input <NUM> of a phase shifting element <NUM>. The phase shifting element <NUM> generates from the oscillation signal SO quadrature related components of the local oscillator signal at both a first output <NUM> and also at a second output <NUM> of the phase shifting element <NUM>. The first output <NUM> of the phase shifting element <NUM> is coupled to the second input <NUM> of the down-conversion stage <NUM> for delivering the quadrature related components of a local oscillator signal to the down-conversion stage <NUM>, and the second output <NUM> of the phase shifting element <NUM> is coupled to the second input <NUM> of the up-conversion stage <NUM> for delivering the quadrature related components of the local oscillator signal present to the up-conversion stage <NUM>.

Although embodiments have been described in which the stored value NS, and the stored final value of the ramp voltage VR are constant, these stored values may be updated by repeating the initialisation process. Moreover, these stored values may be updated by an automatic gain control (AGC) scheme in response to fluctuations in the amplitude of the oscillation signal SO, in order to restore the amplitude of the oscillation signal SO to a target level. Nonetheless, such updated values remain dependent on the final level of the bias current IB reached when the increasing of the level of the bias current IB is terminated.

Other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known and which may be used instead of, or in addition to, features described herein. For example, although apparatus and methods for generating the increasing bias current IB have been described, other techniques may alternatively be used.

Features that are described in the context of separate embodiments may be provided in combination in a single embodiment. Conversely, features which are described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

Claim 1:
A method of operating an oscillator circuit (<NUM>), comprising:
in response to a supply of power to the oscillator circuit (<NUM>) being switched on, initialising the oscillator circuit, wherein initialising the oscillator circuit comprises:
generating a bias current with an increasing level commencing at a first level;
supplying the bias current to a crystal oscillator (<NUM>);
generating a feedback signal in response to an amplitude of an oscillation signal generated by the crystal oscillator (<NUM>) reaching an amplitude threshold; and
in response to the feedback signal, terminating the increasing and storing an indication of the final level of the bias current reached when the increasing is terminated; and
during subsequent operation of the crystal oscillator (<NUM>), supplying the bias current at a second level dependent on the final level of the bias current reached when the increasing is terminated,
wherein the method further comprises:
in response to the supply of power to the oscillator circuit (<NUM>) being switched on after an intervening period of operation in a sleep mode in which the supply of power to the oscillator circuit is switched off, generating the bias current at a third level dependent on the stored indication without again initialising the oscillator circuit.