Patent Description:
In an optical network (passive or active) an Optical Line Terminal, OLT is coupled to multiple Optical Network Terminals, ONT, in respective optical endpoints via an Optical Distribution Network, ODN. The ODN typically has a tree and branch architecture and comprises optical fibres and passive splitters/combiners that split the optical signals in the downstream directions from the OLT to the ONTs, and, multiplexes the optical signals in the upstream direction from the ONTs to the OLT. The downstream communication from the OLT to the ONTs is performed by broadcasting data for different ONTs in separate timeslots. In the upstream direction, each ONT is assigned a time slot to transmit its data towards the OLT, resulting in a burst communication.

Due to different optical path losses in the ODN and variations in transmitter power of the different ONTs, the signal arriving at the OLT consists of a sequence of burst with significant amplitude variations and unpredictable phase from one burst to the next. Moreover, in high-speed optical networks, for example <NUM> Gbit/s and <NUM> Gbit/s passive optical networks, the transmission rate of the bursts is further limited by the significant chromatic dispersion which creates Inter-Symbol Interference, ISI.

Patent document <CIT> discloses a solution for shortening the calculation time of a waveform equalization coefficient used for a waveform equalization process of a reception signal when a burst signal is received in a station side device such as OLT in an optical communication system such a TDM-PON. <CIT> proposes that the OLT initializes a waveform equalization coefficient in time with scheduled arrival timing of burst signals from ONUs.

Amongst others, it is an object of embodiments of the present disclosure to provide an OLT with an improved upstream burst reception.

This object is achieved, according to a first example aspect of the present disclosure, by a physical layer, PHY, circuitry comprising:.

wherein the PHY circuitry is further configured to receive a control signal from a medium access control, MAC, circuitry via an input/output interface circuitry, and wherein the control signal comprises an identification of a transmitting ONT, and, wherein the EQ circuitry is configured to preload a pre-determined equalization configuration associated with the identification of the transmitting ONT.

An equalization circuitry may comprise one or more filters which cancel out the phase delay between the frequency components in a signal while preserving its waveform. Due to the different fibre lengths and differences between the ONT's transmitters, the upstream optical signal bursts from different ONTs are affected differently.

As one of the functionalities of a MAC layer circuitry is to allocate transmission opportunities to the different ONTs, the MAC layer circuitry has the information on the next transmitting ONT readily available. By embedding this information in the control signal, the PHY circuitry gains knowledge on the next transmitting ONT.

By deriving the identification of the transmitting ONT from the control signal received from the MAC circuitry via the input/output interface circuitry of the PHY circuitry, the EQ circuitry is preloaded with a pre-determined equalization configuration associated with the identification of the transmitting ONT. Although the PHY and MAC circuitries are implemented as separate circuitries, the received upstream optical signal burst may be equalized in an optimal way, because the equalization is performed from the beginning of the received upstream bursts based on the equalization configuration for the transmitting ONT. Therefore, the upstream burst transmission from the ONTs can be dedicated more to data reception rather than to long training sequences. Therefore, a PHY circuitry with an improved burst reception and therefore the OLT circuitry is enabled.

According to example embodiments, the control signal comprises a bitstream having bits encoding the identification of the transmitting ONT. The number of bits required for encoding the identification of the transmitting ONT depends on the number of ONTs in the optical network. For example, seven bits may be enough for the encoding of the identification of the transmitting ONT. However, if the optical network comprises a limited number of ONTs, a smaller number of bits may suffice, and vice versa. The identification of the ONTs may be an identifier uniquely identifying the transmitting ONT.

By encoding the identification of the transmitting ONT in the control signal, the EQ circuitry may be preloaded with the pre-determined equalization configuration associated to the transmitting ONT, thereby avoiding the need for a long training sequence.

According to other example embodiments, the control signal is indicative for the start of the upstream optical signal bursts. Accordingly, the start of the bitstream may be indicative for the start of the upstream optical signal bursts. Furthermore, the control signal may comprise a length information indicative for the length of the upstream optical signal bursts. Accordingly, the length information may be related to a length of said bitstream. In other words, the control signal transmitted by the MAC circuitry to the PHY circuity may be used as a synchronisation signal comprising indication for at least one of the start time and/or length of the upstream optical signal bursts.

By encoding the start and the length of the upstream optical signal bursts, the operation of the PHY circuitry may be synchronized with burst transmission of the ONTs. In particular, by encoding information about the start time of the upstream burst allows to reset the PHY circuitry to a state ready to receive the upstream burst from the transmitting ONT, while encoding the length of the upstream burst allows to indicate the end of the upstream burst. The PHY circuitry can then use this information for example to shield the clock and data recovery circuitry and EQ circuitry from inter-burst-noise. Furthermore, it allows the EQ circuitry to further optimize the pre-loaded equalization configuration during the active burst.

This allows the clock and data recovery circuitry to generate a local clock with the same frequency and phase as the received upstream burst. Thereby, by generating a local clock synchronized in frequency and phase with the received upstream burst, the PHY circuitry will be clocked in sync with the received upstream burst which allows the upstream optical signal burst to be received correctly.

A signal indicating the start of burst transmission from the MAC circuitry may already be available for synchronization purposes of the PHY circuitry. Existing implementations of OLT circuitries and therefore optical networks implementation may be therefore easily improved by embedding the identification of the transmitting ONT into such a signal.

According to example embodiments, the control signal may be further configured to indicate a quiet window for joining of an ONT. Different possible bitstream configurations for encoding a quiet window may be envisaged. For example, the bits in the bitstream may be set to a high logical value. Alternatively, the first bit and the one or more idle bits may be set to a high logical value, while the bits encoding the identification of the transmitting ONT may be set to a low logical value.

Upon receipt of the quiet window the PHY circuitry may be configured to a so-called ranging mode. The means the PHY circuitry is set to a state ready to receive the upstream burst from an ONT joining the optical network. Accordingly, the EQ circuitry is configured to determine a new equalization configuration associated with the joining ONT. The determined equalization configuration is then stored in a storage circuitry, i.e. the look-up table, which allows the EQ circuitry to be pre-loaded when a transmission from the joining ONT is expected.

By encoding a quiet window in the control signal, the PHY circuitry may be pre-set to a ranging mode in a simple and an efficient way. The need of an additional control signal is avoided. Furthermore, this allows interface between the PHY circuitry and the MAC circuitry to be further simplified.

According to example embodiments, the PHY circuitry further comprises a circuitry configured to decode the identification of the transmitting ONT from the control signal and to retrieve the associated pre-determined equalization configuration. The circuitry may comprise a decoder configured to decode the identification of the transmitting ONT. The decoder may be further configured to decode the start time and the length of the upstream optical signal burst from the transmitting ONT.

Upon decoding the identification of the transmitting ONT the circuitry may retrieve from the storage circuitry the equalization configuration determined during the ranging phase. The circuitry may be further configured to pre-load the EQ circuitry with the pre-determined equalization configuration.

According to further embodiments, the PHY circuitry comprises a clock and data recovery, CDR, circuitry and a synchronizing circuitry. Further, the circuitry may be further configured to output reset signals for resetting at least one of a clock and data recovery, CDR, circuitry and a synchronizing circuitry of the PHY circuitry.

By resetting the clock and data recovery, CDR, circuitry and the synchronizing circuitry, the circuitries are pre-set to adequate initial values, allowing quick new burst acquisition and avoid inter-burst noise interference.

Additionally, the circuitry may be further configured to output a signal to pre-set an optical receiver configured to receive the upstream optical signal burst. By pre-setting the optical receiver to a state ready for reception of the upstream optical signal burst, the upstream optical burst is received correctly. Furthermore, the optical receiver may comprise an amplification circuitry with an automatic gain control. The optical receiver may be completely off because of a preceding noisy but silent period on the transmission medium. Therefore, by pre-setting the gain point of the optical receiver, it is assured that the upstream optical signal bursts are received correctly even if they have significant amplitude variations. Moreover, a faster settling of automatic gain control may be achieved.

According to example embodiments, the PHY circuitry comprising an electrical input pin configured to receive the control signal from the MAC circuitry. The electrical pin may be an input pin of the PHY circuitry standard interface. For example, the input pin typically used for signalling a start of burst transmission of a respective ONT may be re-used. This way a modification of the PHY circuitry standard interface is avoided.

According to a second example aspect a medium access control, MAC, circuitry is disclosed configured to determine an upstream allocation map for optical network terminals, ONTs, and wherein the MAC is further configured to generate a control signal for the PHY circuitry according to the first example aspect via an input/output interface circuitry, wherein the control signal comprises synchronization information for receiving upstream optical signal bursts from a transmitting ONT, the control signal further comprises an identification of the transmitting ONT based on the upstream allocation map.

The medium access control, MAC, circuitry is responsible for the assignment of a unique identifier to a respective ONT and for the determination of the upstream allocation map. Therefore, the MAC circuitry holds information on the identification of a transmitting ONT as well as a synchronization information such as the start time and length of its burst transmission.

Therefore, by configuring the MAC circuitry to output a control signal via its the input/output interface circuitry, with the control signal comprising synchronization information for receiving upstream optical signal bursts from a transmitting ONT and the identification of the transmitting ONT, the PHY circuitry may be pre-set to a state ready to reception of upstream optical signal bursts and the EQ circuitry may be preloaded with a pre-determined equalization configuration associated with the identification of the transmitting ONT. This way long preamble sequences required for the pre-set of the PHY circuitry are avoided. Furthermore, loss of upstream bandwidth is prevented and a high-speed operation of the PHY circuitry and therefore the OLT circuitry is enabled.

According to an example embodiment, the control signal further comprises identification of a length of the upstream optical signal bursts. The length indication allows for example to indicate the end of the upstream burst. The PHY can then use this information for example to shield the clock and data recovery circuitry and EQ circuitry from inter-burst-noise. Furthermore, it allows the EQ circuitry to optimize the pre-loaded equalization configuration further during the active burst.

According to a further example embodiment, MAC circuitry comprising an electrical output pin configured to output the control signal to the physical layer circuitry. The electrical pin may be an output pin of the PHY circuitry standard interface. For example, the output pin used for signalling a start of burst transmission of a respective ONT may be re-used. This way a modification of the MAC circuitry standard interface is avoided.

According to a third example aspect an optical line terminal, OLT, is disclosed comprising a PHY circuitry according to the first example aspect and a MAC circuitry according to the second example aspect.

According to a fourth example aspect a method is disclosed comprising:.

To mitigate the effects of amplitude variations and unpredictable phase of the received upstream bursts as well as the effects of Inter-Symbol Interference, ISI, resulting from chromatic dispersion, a burst-mode electronic distortion (or dispersion) compensation is applied in the physical layer, PHY, circuitry. The burst-mode distortion compensation is performed by the equalization, EQ, circuitry which needs to determine the equalization configurations for the different ONTs in the optical network.

The optical network may be an active or a passive network, such as, a Broadband PON, BPON, an Ethernet PON, EPON, and a Gigabit PON, GPON, and others. The optical network may operate according to ITU-T G. <NUM> and IETF/ITU-T standards.

When joining an optical network, an ONT may undergo an activation procedure. Upon a successful activation procedure, the joining ONT becomes an active ONT. During the activation procedure, the equalization configuration for the ONT joining the optical network are determined by the PHY circuitry which may be stored in a storage circuitry. The storage circuitry may be a look-up-table which preserves the association between the determined equalization configuration and the respective ONT. This allows, during normal operation, the PHY circuitry to perform a burst-mode distortion compensation to the upstream burst transmission from the active ONTs based on their respective pre-determined equalization configuration.

During normal operation of the optical network, the transmitting ONT transmits a preamble sequence at the beginning of its burst transmission which limit the burst's transmission rate and leads to a waste of upstream bandwidth. Furthermore, PHY circuitry has no knowledge which ONT transmitted the upstream optical signal burst and hence the equalization is not optimal.

The MAC circuitry is responsible for determination of an upstream allocation map which comprises synchronization information such as start time and length of the burst transmission of the respective active ONTs in the optical network. By transmitting a control signal to the PHY circuitry embedding the identification of the transmitting ONT will allow to pre-load the EQ circuitry with the pre-determined equalization configuration associated with the transmitting ONT. This way, there is no need, for example, to first identify the transmitting ONT from the received upstream signal and then apply the pre-determined equalization configuration. This enables an improved burst reception. Further, the received burst transmission will be equalization in an optimal way, allowing burst transmission from the ONTs to be dedicated more to data reception.

<FIG> shows an example embodiment of optical line terminal, OLT, <NUM> according to the present disclosure. The OLT comprises an optical receiver <NUM>, a physical layer, PHY, circuitry <NUM> and a medium access control, MAC, circuitry <NUM>. The PHY circuitry implements the Physical Media Dependent, PMD, layer functionalities. The PHY circuitry <NUM> comprises a converter circuitry <NUM>, an equalization, EQ, circuitry <NUM>, a synchronization circuitry <NUM>, a storage circuitry <NUM>, an interface circuitry <NUM> and a control circuitry <NUM>. The MAC circuitry <NUM> implements the medium access control, MAC, layer functionalities and comprises an interface circuitry <NUM>, a clock and data recovery circuitry <NUM>, a synchronization circuitry <NUM> and a MAC logic circuitry <NUM>.

The MAC circuitry and, in particular, the MAC logic circuitry <NUM> determines the upstream allocation map. The MAC logic circuitry <NUM> is further configured to generate a control signal <NUM> which controls the operation of the PHY circuitry <NUM>. The control signal <NUM> comprises synchronization information for receiving the upstream optical signal burst from a transmitting ONT as well as identification of the transmitting ONT based on the upstream allocation map. The control signal <NUM> is outputted by the MAC circuitry <NUM> via its input/output interface <NUM>. The input/output interface <NUM> comprises an electrical output pin <NUM> configured to output the control signal <NUM> to the PHY circuitry.

The PHY circuitry <NUM> is configured to receive the control signal <NUM> via its input/output interface <NUM>. The input/output interface <NUM> comprises an electrical input pin <NUM> configured to receive the control signal <NUM>.

For example, the interface circuitries <NUM> and <NUM> may comprise a high-speed interface for data exchange, such as a gigabit Ethernet interface as defined by IEEE <NUM>. 3ab standard may be used. An example of such a high-speed interface is the Serializer/Deserializer, SerDes, interface. Further, the interface circuitries <NUM> and <NUM> may comprise a synchronous control interface, such as 12C interface, for exchanging control data.

The optical reset pin of the interface circuitries <NUM> and <NUM> may be reused as the input pin <NUM> and output pin <NUM>.

The control circuitry <NUM> controls the operation of the PHY circuitry in accordance with the control signal <NUM>. The functionality of the control circuitry <NUM> and the operation of the PHY circuitry will be explained in more detail below with reference to <FIG> showing a flow-chart illustrating the steps it performs.

The optical receiver <NUM> converts the received upstream optical signal bursts into electrical signal bursts <NUM>. The electrical signal bursts <NUM> are then fed to the PHY circuitry <NUM>, where the electrical signal bursts are digitized by the converter circuitry <NUM> so that a digitized electrical signal bursts <NUM> are obtained. The converter circuit <NUM> may over-sample the electrical signal burst <NUM>. For example, the sampling rate may be set to <NUM> the frequency of the electrical signal burst <NUM> or higher. The digitized signal bursts <NUM> are then fed to the equalization circuitry <NUM> which applies a burst-mode distortions compensation by equalizing the digitized electrical signal bursts <NUM>. Therefore, the inter-symbol interference in the digitized signal bursts is compensated for. The EQ circuitry is allowed to have a variable processing time within certain boundaries. The MAC circuitry <NUM>, on the other hand, requires upstream bursts with a fixed latency. The digitized and compensated signal bursts <NUM> are therefore fed to the MAC circuitry <NUM> for further processing via the synchronization logic <NUM> which assures that the digitized and compensated signal bursts <NUM> are with a fixed latency.

The circuitry <NUM> is configured to output control signals <NUM>, <NUM>, <NUM> and <NUM> in accordance with a control signal <NUM>. The circuitry <NUM> receives <NUM> the control signal <NUM> and decodes <NUM> synchronization information comprising the start time and the length of the upstream optical signal bursts as well as the unique identifier of the transmitting ONT. Accordingly, the circuitry <NUM> outputs <NUM> control signals <NUM>, <NUM> and <NUM> in accordance with the identified start time of the upstream optical signal bursts for synchronizing the PHY circuitry operation with the upstream burst transmission from the ONTs, wherein the control signal <NUM> is configured to pre-set the optical receiver <NUM> while control signals <NUM> and <NUM> are configured to reset the clock and data recovery circuitry (not shown in the figure) of the converter circuitry <NUM> and the synchronization circuitry <NUM>, respectively.

In particular, the control signal <NUM> is configured to pre-set the automatic gain control of the amplifying circuitry (not shown) of the optical receiver <NUM> to a predefined gain point at the start of receipt of upstream optical bursts. For example, the automatic gain control may be pre-set to a mid-point. Control signal <NUM> is fed to the optical receiver <NUM> through the electrical output pin <NUM> of the interface circuitry <NUM>.

Control signal <NUM> is configured to reset the clock and data recovery circuitry of the converter circuitry <NUM> and control signal <NUM> is configured to reset the synchronization circuitry <NUM> respectively. By resetting these circuitries the PHY circuitry <NUM> is reset to a state ready to receive the upstream burst from the transmitting ONT. In turn, the clock and data recovery circuitry generates a local clock <NUM> with the same frequency and phase as the received upstream burst. The local clock <NUM> is used to clock the converter circuitry <NUM>, the EQ circuitry <NUM> as well as the synchronization circuitry <NUM>. This way the operation of the PHY circuitry <NUM> is synchronized in frequency and phase with the received upstream burst which in turn allows the upstream optical signal burst to be received correctly so that the PHY circuitry may perform a correct data decision.

In addition to control signals <NUM>, <NUM> and <NUM>, the control circuitry <NUM> further outputs a control signal <NUM> which pre-loads the EQ circuitry with a pre-determined equalization configuration based on the decoded identifier information. Upon decoding the unique identifier of the transmitting ONT, the control circuitry <NUM> retrieves <NUM> the pre-determined equalization configuration associated with the decoded unique identifier from the storage circuitry <NUM> and pre-loads <NUM> the EQ circuitry with the retrieved pre-determined equalization configuration.

The exact timing relationship between the reset of the optical receiver <NUM>, the reset of the CDR circuitry and the pre-loading of the EQ circuitry <NUM> may be optimized independently from each other.

Alternatively, the control circuitry <NUM> may forward the decoded unique identifier to the EQ circuitry <NUM>, which upon receipt of the ONT's unique identifier, retrieves the pre-determined equalization configuration associated to the transmitting ONT from the storage circuitry <NUM>. The EQ circuitry then pre-loads itself with the retrieved equalization configuration.

<FIG> shows an example of the control signal <NUM> comprising a bitstream with a length <NUM>. The first bit <NUM> of the bitstream may be set to a high logical value to indicate a start of the upstream optical burst transmission while the length of the bitstream may be as indication of the length of the upstream optical signal burst. Further, bits <NUM> of the bitstream may be configured to encode the unique identifier of the transmitting ONT. The bits encoding the unique identifier of the transmitting ONT are separated from the first bit of the bitstream by one or more idle bits <NUM>.

As detailed above, when joining an optical network, an ONT may undergo an activation procedure. During the activation procedure, the PHY circuitry must be pre-set for reception of burst transmission from the ONT joining the optical network. According to other example embodiments, the control signal <NUM> may be configured to indicate a quiet window during which upstream optical signal burst from the joining ONT are received as shown in <FIG>. The control signal <NUM> comprises a bitstream with a length <NUM> and bits, for example, set to a high logical value. The start of the bitstream and its length are indicative for the start time and the length of the burst transmission from the joining ONT.

The bit duration in the bitstream may be set to for example <NUM>. The length of the upstream optical signal burst may be then set as an integer multiple of the bits. For example, an upstream burst length of <NUM> may be encoded in a <NUM> bits bitstream with a bit duration of <NUM>. The electrical standard of the signal can be for example Low-Voltage Transistor-Transistor Logic (LVTTL).

<FIG> shows a computing system <NUM> suitable for performing various steps performed by an optical line terminal, OLT, in an optical network according to various embodiments of the present disclosure. Computing system <NUM> may in general be formed as a suitable general-purpose computer and comprise a bus <NUM>, a processor <NUM>, a local memory <NUM>, one or more optional input interfaces <NUM>, one or more optional output interfaces <NUM>, a communication interface <NUM>, a storage element interface <NUM>, and one or more storage elements <NUM>. Bus <NUM> may comprise one or more conductors that permit communication among the components of the computing system <NUM>. Processor <NUM> may include any type of conventional processor or microprocessor that interprets and executes programming instructions. Local memory <NUM> may include a random-access memory, RAM, or another type of dynamic storage device that stores information and instructions for execution by processor <NUM> and/or a read only memory, ROM, or another type of static storage device that stores static information and instructions for use by processor <NUM>. Input interface <NUM> may comprise one or more conventional mechanisms that permit an operator or user to input information to the computing device <NUM>, such as a keyboard <NUM>, a mouse <NUM>, a pen, voice recognition and/or biometric mechanisms, a camera, etc. Output interface <NUM> may comprise one or more conventional mechanisms that output information to the operator or user, such as a display <NUM>, etc. Communication interface <NUM> may comprise any transceiver-like mechanism such as for example one or more Ethernet interfaces that enables computing system <NUM> to communicate with other devices and/or systems, for example with other computing devices <NUM>, <NUM>, <NUM>. The communication interface <NUM> of computing system <NUM> may be connected to such another computing system by means of a local area network, LAN, or a wide area network, WAN, such as for example the internet. Storage element interface <NUM> may comprise a storage interface such as for example a Serial Advanced Technology Attachment, SATA, interface or a Small Computer System Interface, SCSI, for connecting bus <NUM> to one or more storage elements <NUM>, such as one or more local disks, for example SATA disk drives, and control the reading and writing of data to and/or from these storage elements <NUM>. Although the storage element(s) <NUM> above is/are described as a local disk, in general any other suitable computer-readable media such as a removable magnetic disk, optical storage media such as a CD or DVD, - ROM disk, solid state drives, flash memory cards,. could be used.

According to the present disclosure, the communication interface <NUM> allows an OLT according various embodiments of the present disclosure to exchange control information and data with the ONUs <NUM>, another OLT <NUM> in the optical network as well as an aggregation network <NUM>. According to the example embodiments, the processor may be running a computer program code which allows the OLT to control the operation of its PHY circuitry in accordance with the bandwidth allocation map determined by its respective MAC circuitry. The processing is therefore configured to control the operation of the converter circuitry <NUM> and its clock and data recovery circuitry, the EQ circuitry <NUM>, the control circuit <NUM> as well as the synchronization circuitry <NUM> and the storage circuitry <NUM>. More specifically, during operation the MAC circuitry may receive, via the communication interface <NUM>, information from the ONTs relating to their serial number, their status, etc, based on which the processor may determine an upstream allocation map. The processor will then instruct the received information as well as the determined upstream allocation map to be stored in the memory <NUM>. Prior receipt of upstream optical signal bursts from a transmitting ONT, i.e. based on the upstream allocation map, the processor <NUM> will issue a control message comprising synchronization information and an identification of a transmitting ONT with which it will instruct the OLT circuitry and more specifically, its PHY circuitry, to: pre-set to a state ready for reception of upstream optical signal burst from a respective ONT; to retrieve a pre-determined equalization configuration from the memory <NUM> based on the identification of transmitting ONT; and to preload the EQ circuitry with the retrieved equalization configuration.

Although the present disclosure has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that the present disclosure is not limited to the details of the foregoing illustrative embodiments, and that the present disclosure may be embodied with various changes and modifications without departing from the scope thereof, which is solely defined by the appended claims. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the present disclosure being indicated by the appended claims rather than by the foregoing description, and all changes which come within the scope of the claims are therefore intended to be embraced therein.

Claim 1:
A physical layer, PHY, circuitry (<NUM>) comprising:
- a converter circuitry (<NUM>), configured to digitize upstream optical signal bursts received from respective optical network terminals, ONTs, to digitized upstream signal bursts;
- an equalization, EQ, circuitry (<NUM>) configured to derive data bitstreams from the respective digitized upstream signal bursts based on pre-determined equalization configurations of the EQ circuitry (<NUM>) associated with the respective ONTs;
wherein the PHY circuitry (<NUM>) is further configured to receive a control signal (<NUM>) from a medium access control, MAC, circuitry (<NUM>) via an input/output interface circuitry (<NUM>), and wherein the control signal (<NUM>) comprises an identification of a transmitting ONT, and, wherein the EQ circuitry (<NUM>) is configured to preload a pre-determined equalization configuration associated with the identification of the transmitting ONT.