Patent Description:
When a semiconductor device is provided with an oscillation circuit, in general, a trimming circuit is provided for trimming the frequency characteristics of the oscillation circuit. The trimming circuit includes a resistor and an oscillating frequency of the oscillation circuit can be set to a desired value on a semiconductor device (chip)-by-semiconductor device (chip) basis by adjusting a resistance value of the resistor. As a resistance element used in trimming circuits, there is known a polycrystalline silicon resistor used to form a circuit element such as a transistor. A polycrystalline silicon resistor can be formed without complicating a semiconductor device manufacturing process and is excellent in that it is high in resistivity and a high resistance can be achieved with a small area; however, it is known that its resistance value fluctuates after a package molding process. This fluctuation in resistance value is caused by a change in shape, a piezoelectric effect, or the like as the result of a resistance element (polycrystalline silicon resistor) on a silicon chip being subjected to stress from mold resin. In the technology disclosed in <CIT> (Patent Document <NUM>), a location where a polycrystalline silicon resistor is to be placed is specified so as to reduce stress the polycrystalline silicon resistor is received from mold resin as much as possible.

From document <CIT> a semiconductor device comprising a metal wiring resistor connected in series with a via chain resistance is known. In this device, a change of the resistance value of the metal wiring resistor resulting from a film thickness variation is compensated by a change of the resistance value of the via chain resistor in the opposite direction.

Document <CIT> relates to a semiconductor device in which a resistance value does not change when applying pressure during bonding.

Document <CIT> is directed to an on-chip method for implementing resistors, capacitors and inductors in an integrated circuit using vertical stack vias and interconnects.

In document <CIT>, a circuit element for an integrated circuit is described, whose characteristics can be controlled independently from a semiconductor substrate. Unit resistor elements are formed by connecting metal wires via through holes, whose insides are filled with a resistor material.

The technology in Patent Document <NUM> aims to suppress a coefficient of fluctuation in resistance of a polycrystalline silicon resistor between a state of wafer (completion of trimming) and the completion of a package molding process to within approximately ±<NUM>%. However, in recent years, higher accuracy has been required of trimming circuits and it is preferable to lower a coefficient of fluctuation in resistance as much as possible. Further, in the technology disclosed in Patent Document <NUM>, a location where a polycrystalline silicon resistor can be placed is limited and a degree of freedom in designing is inevitably degraded.

Other problems and novel features will be apparent from the description in the present specification and the accompanying drawings.

As a resistance element suitable for trimming circuits, a resistance element which is formed in a plurality of wiring layers and has main resistance in a direction perpendicular to a semiconductor substrate plane is implemented.

A resistor low in coefficient of fluctuation in resistance after the completion of a package molding process can be implemented.

Aspects of this disclosure which do not fall under the scope of the claims, only serve for explanatory purposes and do not form part of the invention.

According to the invention, a semiconductor device is provided as recited in claim <NUM>.

Hereafter, a description will be given to an embodiment of the present invention with reference to the drawings. <FIG> is a block diagram illustrating a semiconductor device <NUM> in the present embodiment. Active elements, such as a transistor, and passive elements, such as a resistor and a capacitor, are formed on a substrate of the semiconductor device <NUM>. In the semiconductor device <NUM>, various functional blocks are formed using these elements. <FIG> shows CPU (Central Processing Unit) <NUM>, RAM <NUM>, a peripheral IP <NUM>, and a nonvolatile memory <NUM> as examples of functional blocks. An example of the peripheral IP is an A/D converter. Addresses and data are communicated between these functional blocks via a bus <NUM>. A clock generation circuit <NUM> generates a clock from an oscillation signal of an on-chip oscillator <NUM> and distributes the clock to these functional blocks. The on-chip oscillator <NUM> includes a resistor <NUM>. A resistance value of the resistor <NUM> is adjusted to a predetermined value and an oscillating frequency of the on-chip oscillator <NUM> is set to a desired value on a semiconductor device <NUM>-by- semiconductor device <NUM> basis. A trimming code required for trimming is written to the nonvolatile memory <NUM> or the RAM <NUM> and a resistance value of the resistor <NUM> is adjusted to a predetermined value based on a trimming code read through a register <NUM>.

<FIG> is a circuit diagram of an oscillation circuit as an example of the on-chip oscillator <NUM>. The oscillation circuit includes a trimming circuit <NUM>, a constant-current generation circuit <NUM>, capacitors <NUM>, <NUM>, capacitance drive circuits <NUM>, <NUM>, comparators <NUM>, <NUM>, and a latch circuit <NUM>. The capacitance drive circuit <NUM> includes a PMOS transistor <NUM> and an NMOS transistor <NUM> whose source-drain paths are coupled in series. The source of the NMOS transistor <NUM> is coupled to a grounding terminal and the drain thereof is coupled to the drain of the PMOS transistor <NUM>. A junction of the drain of the PMOS transistor <NUM> and the drain of the NMOS transistor <NUM> is an output node of the capacitance drive circuit <NUM> and a capacitor <NUM> is coupled thereto. The source of the PMOS transistor <NUM> is fed with an output current Ir0×m outputted by the constant-current generation circuit <NUM>. A current passed through the source-drain path of a PMOS transistor <NUM> of the constant-current generation circuit <NUM> is Ir0 and the transistor size of a PMOS transistor <NUM> (<NUM>) of the constant-current generation circuit <NUM> is m times the transistor size of the PMOS transistor <NUM>. For this reason, the output current Ir0×m is inputted to the source of the PMOS transistor <NUM>. The gate of the PMOS transistor <NUM> and the gate of the NMOS transistor <NUM> are coupled in common and an output signal Q of the latch circuit <NUM> is inputted thereto. The capacitor <NUM> is coupled between the output node of the capacitance drive circuit <NUM> and the grounding terminal and as a result, a voltage corresponding to an amount of charge accumulated in the capacitor <NUM> is produced at the output node of the capacitance drive circuit <NUM>. This is the same with the capacitance drive circuit <NUM>, which has a capacitor <NUM> coupled to an output node thereof. Though a detailed description will be omitted, the gate of a PMOS transistor <NUM> and the gate of an NMOS transistor <NUM> are coupled in common and an output signal QN of the latch circuit <NUM> is inputted thereto.

An oscillation reference voltage VREF is inputted to the non-inverting input terminal (+) of the comparator <NUM> and an output node voltage VCP0 of the capacitance drive circuit <NUM> is inputted to the inverting input terminal (-) thereof. The comparator <NUM> switches a logic level of a set signal S according to which is higher, the oscillation reference voltage VREF or the output node voltage VCP0. Specifically, the comparator <NUM> brings a set signal S to a high level when the output node voltage VCP0 is higher than the oscillation reference voltage VREF and brings a set signal S to a low level when the output node voltage VCP0 is lower than the oscillation reference voltage VREF. This is the same with a comparator <NUM> that switches a logic level of a reset signal R. Though a detailed description will be omitted, the oscillation reference voltage VREF is inputted to the non-inverting input terminal (+) of the comparator <NUM> and an output node voltage VCP1 of the capacitance drive circuit <NUM> is inputted to the inverting input terminal (-) thereof.

It is preferable that the comparator <NUM> (<NUM>) should be a hysteresis comparator in order to stably switch a logic level of a set signal S (reset signal R). When dh is taken as a hysteresis width, the hysteresis comparator switches a set signal S (reset signal R) from a low level to a high level when the output node voltage VCP0 (VCP1)>the oscillation reference voltage VREF and switches a set signal S (reset signal R) from a high level to a low level when the output node voltage VCP0 (VCP1)+dh<the oscillation reference voltage VREF.

The resistor <NUM> is coupled in series with the source-drain path of the PMOS transistor <NUM> of the constant-current generation circuit <NUM>. A resistance value of the resistor <NUM> is adjusted by the trimming circuit <NUM>. The trimming circuit <NUM> is fed with a trimming code stored in the register <NUM>. A resistance value of the resistor <NUM> is adjusted according to a trimming code and an amount of current Ir0 passed through the source-drain path of the PMOS transistor <NUM> is thereby adjusted. As a result, a frequency of an outputted clock is adjusted.

<FIG> is a conceptual rendering of a resistance element used in the resistor <NUM> in the present embodiment. The resistance element is formed in wiring layers of a semiconductor device. The surface of the semiconductor substrate where a semiconductor element is formed is taken as an XY plane and a direction perpendicular to the XY plane is taken as a Z direction. The resistance element includes: a lower conductive layer <NUM> and an upper conductive layer <NUM> extending in an X direction or a Y direction, respectively; and an interlayer conductive layer <NUM> whose ends are coupled to the lower conductive layer <NUM> and the upper conductive layer <NUM>, respectively and which is extended in the Z direction. The lower conductive layer <NUM>, the interlayer conductive layer <NUM>, and the upper conductive layer <NUM> are coupled in series.

Here, it will be assumed that: a resistance value of the resistance element is R and the resistance element includes k+<NUM> lower conductive layers <NUM>, k upper conductive layers <NUM>, and <NUM> interlayer conductive layers <NUM> coupled in series. Further, it will be assumed that a resistance value of one lower conductive layer <NUM> is Rxy_lower, a resistance value of one upper conductive layer <NUM> is Rxy_upper, and a resistance value of one interlayer conductive layer <NUM> is Rz. At this time, a resistance value R of the resistance element is expressed by (Expression <NUM>): <MAT> This is an expression that holds when the resistance element is coupled with another element at the upper conductive layer <NUM>. Similarly, (Expression <NUM>) holds when the resistance element is coupled with another element at the lower conductive layer <NUM>: <MAT> Since the Z-direction component of the resistance element is taken as main resistance, the relation expressed by (Expression <NUM>) holds: <MAT> As described later, the resistance element in the present embodiment, which is formed in wiring layers and in which the Z-direction component is taken as main resistance, is hardly influenced by stress produced in the semiconductor substrate as the result of a package molding process. For this reason, a placement position of the resistance element in the present embodiment is not limited; and the lower conductive layer <NUM>, the interlayer conductive layer <NUM>, and the upper conductive layer <NUM> only have to be coupled in series such that the resistance element has a desired resistance value. In addition, the disposition or number of the individual conductive layers is not limited.

<FIG> illustrates an example of implementation of the resistance element. The drawing is a top view and a sectional view illustrating the resistance element in <FIG> implemented in a semiconductor device. In the present embodiment, the structure of wiring layers formed in the semiconductor device is utilized for the resistance element. The lower conductive layers <NUM> are formed of a wiring layer M1; the upper conductive layers <NUM> are formed of a wiring layer M4; and the interlayer conductive layers <NUM> are formed of vias V1 to V3 and wiring layers M2, M3. The reason why the interlayer conductive layers <NUM> are formed of a plurality of conductive layers is that a resistance value of the interlayer conductive layers <NUM> is made high as much as possible and the interlayer conductive layers are formed by the same process as for ordinary wiring layers. An interlayer conductive layer 53a includes a via <NUM>, a landing PAD <NUM> formed in the wiring layer M2, a via <NUM>, a landing PAD <NUM> formed in the wiring layer M3, and a via <NUM> which are coupled in series. As the result of the interlayer conductive layers <NUM> being implemented as mentioned above, the resistance element can be formed without adding any change to a wiring process for the semiconductor device.

For example, the wiring layer M1 can be formed of a laminated film of W (main conductive layer)/TiN and the wiring layers M2 to M4 can be formed of a laminated film of TiN/AlCu (main conductive layer)/TiN/Ti. The vias V1 to V3 have a configuration obtained by depositing a Ti layer <NUM> and a TiN layer <NUM> and burying a W layer <NUM> there and a resistance value of the vias depends mainly on a contact resistance between the W layer and the TiN layer. This is just an example. The used wiring layers are not limited to the wiring layers M1 to M4 and this configuration can be implemented by at least two wiring layers and a via buried layer coupling the two wiring layers together. In addition, the via buried layers and the landing PADs formed in the wiring layer M2 and the wiring layer M3 are not limited to the foregoing and any other resistive material such as polysilicon may be adopted. Further, though the vias V1 to V3 are usually formed by burring metal in contact holes formed in an interlayer insulating film, any of the vias V1 to V3 may also be formed by laminating a resistive material such as metal or polysilicon beforehand and filling between the laminated resistive materials with an insulating layer.

Since the resistor <NUM> in the present embodiment is formed by utilizing a structure of wiring layers as mentioned above, a resistance value of each individual conductive layer constituting the resistance element is relatively low. For this reason, to achieve a desired resistance value, a number of conductive layers coupled in series for the resistance element must be increased. <FIG> illustrates a resistance element <NUM> in the form of circuit diagram. Since the resistance element <NUM> is formed of a repetitive pattern of lower conductive layers, interlayer conductive layers, and upper conductive layers, this drawing pseudoly depicts one unit of this repetitive pattern as a unit resistor <NUM>. <FIG> illustrates the resistance element in <FIG> in a layout (top view). Unit resistors coupled in series are continuously Z-folded and compactly disposed. To obtain a resistor having as high resistance as possible with a small area, it is preferable to dispose interlayer conductive layers densely as much as possible. For this reason, in the resistance element in <FIG>, the following measure is taken: in an area where the resistance element <NUM> is formed, vias forming interlayer conductive layers are spread in a matrix pattern in the X direction (in this example, the lengthwise direction of the upper conductive layers and the lower conductive layers is taken as the X direction) and the Y direction; and the interlayer conductive layers are coupled by the lower conductive layers and the upper conductive layers. It is preferable that adjoining interlayer conductive layers should be disposed so as to have the minimum interval of vias prescribed by a layout rule for semiconductor devices (chips). In the example in <FIG>, in both the upper conductive layers and the lower conductive layers, the lengthwise direction thereof is taken as the X direction (except an upper conductive layer placed in a folded area). Alternatively, for example, a layout is also acceptable in which the lengthwise direction of the upper conductive layers is taken as the X direction and the lengthwise direction of the lower conductive layers is taken as the Y direction and the conductive layers are coupled in a zigzag pattern and further Z-folded.

<FIG> is a circuit diagram of a trimming circuit <NUM> using resistance elements <NUM> in the present embodiment. The trimming circuit <NUM> includes: N resistance elements <NUM> coupled in series; and bypass switches <NUM>-i (i=<NUM> to N) provided in parallel with the resistance elements <NUM>-i for bypassing the resistance elements <NUM>-i (i=<NUM> to N). Each resistance element <NUM> includes unit resistors <NUM> coupled in series as illustrated in <FIG>. ON/OFF of each bypass switch <NUM>-i of the trimming circuit <NUM> is determined according to a trimming code. As a result, resistance of the trimming circuit <NUM> is set to a desired resistance value and a potential corresponding to the resistance value occurs at a node NF. Since in the resistance element <NUM> in the present embodiment, there are a large number of series couplings, a yield can be degraded due to a failure caused by, for example, disconnection. To cope with this, degradation in yield can be prevented by keeping ON a relevant bypass switch <NUM>-i in a resistance element <NUM>-i in which a manufacturing defect has occurred.

<FIG> is a layout (top view) of the trimming circuit <NUM> illustrated in <FIG>. The layout of the resistance element <NUM>-i (i=<NUM> to N) is identical with the layout illustrated in <FIG>. Wiring 93W, wiring 94W, wiring 95W, and wiring 96W in <FIG> are equivalent to a node <NUM>, a node <NUM>, a node <NUM>, and a node <NUM> in <FIG>, respectively. A configuration of each bypass switch will be described with the bypass switch <NUM>-<NUM> taken as an example. With respect to the bypass switch, it is preferable that the resistance during conduction should be low; therefore, a comb-shaped gate electrode <NUM> is formed on a diffusion region <NUM> formed on a semiconductor substrate. A drain electrode <NUM> is coupled with the wiring 93W via a contact (not shown) and is coupled to a high concentration region (drain region, not shown) of the diffusion region <NUM>. Over the diffusion region <NUM>, meanwhile, a source electrode <NUM> is disposed in a position opposite the drain electrode <NUM> with the gate electrode <NUM> taken as an axis of symmetry and coupled with the wiring 94W via a contact (not shown) and is further coupled to a high concentration region (source region, not shown) of the diffusion region <NUM>.

<FIG> illustrates a defect relief flow for the trimming circuit <NUM>. This flow is intended to suppress degradation in yield when there is a resistance element <NUM> involving a manufacturing defect as mentioned above. This is done by keeping ON a relevant bypass switch <NUM> to exclude the resistance element from the trimming resistor beforehand. The flow in <FIG> is intended to relieve the trimming circuit <NUM> when there is up to one resistance element involving a manufacturing defect. A control table <NUM> indicates ON(<NUM>)/OFF(<NUM>) control on the bypass switch SW_i (i=<NUM> to N) in a i-th iteration when, for example, a second resistance element <NUM> (<NUM>-<NUM>) of the resistance element <NUM> is defective. First, i is set to <NUM> (S111), and at this time, all the bypass switches SW are turned OFF (S112). When a resistance value of the trimming circuit <NUM> (that is, the sum total of resistance values of the resistance elements <NUM> to N) is within a range of expected values at this time (S113), information that all the resistance elements <NUM> to N are normal is written to a memory (S114). Meanwhile, when the sum total of resistance values of the resistance elements <NUM> to N is out of the range of expected values (S113), it is determined that a defective resistance element is included in the resistance elements <NUM> to N. Consequently, the value of i is incremented (S115) and the bypass switches SW are turned ON(<NUM>)/OFF(<NUM>) according to the control table <NUM> (S116). When a resistance value of the trimming circuit <NUM> at an i-th iteration is within the range of expected values (S117), it is determined that the resistance element i is a defective resistance element and information that the bypass switch SW_i is to be kept ON is written to the memory (S118). The expected values at Step S117 are expected values for the sum total of N-<NUM> resistors and made different from the expected values at Step S113. Meanwhile, when a resistance value of the resistors is still out of the range of expected values (S117), it is determined that the resistance element i is a normal resistance element and information that the bypass switch SW_i is to be turned OFF is written to the memory (S119). The value of i is incremented until the number i of iterations reaches N (S115) and a resistance value of the trimming circuit <NUM> is repeatedly determined. If there are two or more defective resistance elements, any defective resistance element cannot be identified even after the number i of iterations has reached N; therefore, it can be determined that the trimming circuit <NUM> is irrelievably defective.

As the result of the flow in <FIG>, information that a bypass switch corresponding to a resistance element involving a manufacturing defect in the trimming circuit <NUM> is to be kept ON and a bypass switch corresponding to a normal resistance element is to be kept OFF is stored in the nonvolatile memory or the RAM of the semiconductor device. This information is read in user usage (S122) and normal resistance elements used for trimming can be thereby set (S123).

When a resistance value is within the range of expected values at Step S117 in <FIG>, it can be seen that only the relevant resistance element i is defective and the flow may be terminated at this stage. A resistance value of each resistance element may also be measured in terms of determination of a respective defect of each resistance element. However, when a defect relief is performed by controlling ON(<NUM>)/OFF(<NUM>) of the bypass switches as according to the control table <NUM> in <FIG>, a defect determination can be made based on resistance values that would be obtained in actual use of the trimming circuit <NUM> and the reliability of the defect relief flow can be further enhanced.

<FIG> indicates a coefficient of fluctuation in characteristics against package stress on a resistance element. A filled circle indicates a resistance element in the present embodiment and an open circle indicates a P-type polycrystalline silicon resistor taken as a comparative example. In some packages, as large a stress as 250MPa or above is applied to the central part of a chip. A resistance element in the present embodiment and a P-type polycrystalline silicon resistor as a comparative example are formed at a plurality of points on each ship and measurements are made. The graph in <FIG> indicates results of the measurements and in the graph, the horizontal axis indicates stress produced in a location (substrate) where a resistor is formed and the vertical axis indicates a coefficient of fluctuation in resistance value between before and after packaging. As a result, it is found that in the resistance element in the present embodiment, a coefficient of fluctuation in resistance can be suppressed to below <NUM>% wherever it is formed in a chip.

<FIG> is a graph <NUM> indicating intra-chip distribution of package stress. In the graph, the center of a chip <NUM> is taken as the origin and the X-direction package stress, the Y-direction package stress, and the Z-direction package stress produced along an arrow <NUM> on the X axis from the origin to an edge of the chip as the result of molding are determined by simulation and plotted. In the graph <NUM>, package stress produced in the X direction is indicated by a waveform <NUM>; package stress produced in the Y direction is indicated by a waveform <NUM>; and package stress produced in the Z direction is indicated by a waveform <NUM>. The simulation gives a result that intense compressive stress is produced both in the X direction and in the Y direction in almost all the areas while no stress is produced in the Z direction in almost all the areas in the chip. According to the foregoing, it is concluded that in a resistance element in the present embodiment, resistance does not fluctuate between before and after packaging.

Claim 1:
A semiconductor device (<NUM>) comprising:
a semiconductor substrate; and
a plurality of wiring layers (M1, M2, M3, M4) formed over the semiconductor substrate and including at least a first wiring layer (M1) and a second wiring layer (M4),
wherein a resistance element (<NUM>) is formed in the wiring layers (M1, M2, M3, M4),
wherein the resistance element (<NUM>) has a repetitive pattern of a first conductive layer (<NUM>) formed in the first wiring layer (M1), a second conductive layer (<NUM>) formed in the second wiring layer (M4), and an interlayer conductive layer (<NUM>) coupling the first conductive layer (<NUM>) and the second conductive layer (<NUM>) together,
wherein a resistance value of the interlayer conductive layer (<NUM>) is greater than the sum of a resistance value of the first conductive layer (<NUM>) and a resistance value of the second conductive layer (<NUM>),
wherein in the first wiring layer (M1), the lengthwise direction of the first conductive layer (<NUM>) is taken as a first direction (x) and a direction perpendicular to the first direction (x) is taken as a second direction (y),
wherein a plurality of the interlayer conductive layers (<NUM>) included in the resistance element (<NUM>) are arranged in a matrix pattern in the first direction (x) and the second direction (y), and
characterized in that the interlayer conductive layers (<NUM>) are coupled in the first direction (x) by first and second conductive layers (<NUM>) of the resistance element (<NUM>) forming rows in the first direction (x), which are connected to one another at alternating ends via first conductive layers (<NUM>) coupling interlayer conductive layers (<NUM>) in the second direction (y).