Patent Description:
A metal nanowire array is a forest of vertically aligned metal nanowires, such as copper, silver, gold, etc., typically having a density greater than <NUM><NUM> cm-<NUM>. Metal nanowire arrays are known to be used as a mechanism for an efficient and reliable transfer of heat from a source to a heat sink for thermal management of microelectronics. For this application, metal nanowire arrays provide a soft and thermally conductive structure that is able to conform to and fill in gaps, for example, between a silicon die and a copper heat sink. More specifically, metal nanowire arrays are soft and deformable, which allows them to conform to rough surfaces and provide heat transfer capabilities. Furthermore, metal nanowire arrays are soft and compliant and can mitigate thermomechanical stresses at material interfaces, for example, stresses induced at the interface due to coefficient of thermal expansion mismatch. In other words, dense arrays of vertically aligned metal nanowires offer the unique combination of thermal conductance from a constituent metal and mechanical compliance from high aspect ratio geometry to increase interfacial heat transfer and device reliability.

Metal nanowire arrays that are employed for thermal heat transfer purposes are typically fabricated by providing a porous membrane, used as a sacrificial template, such as a ceramic template, filling the pores in the template with metal using an electrodeposition process and then etching away the template. Thus, the length, diameter and density of the nanowires are determined by the geometry of the template, where the available configuration of the template sets the possible configuration of the nanowire array. Therefore, the thickness of the nanowire array is limited by the available thickness of the templates, where the thickness of the template is limited by the processes that form it.

For today's technologies, a typical metal nanowire array has a maximum thickness of about <NUM>. However, certain electrical devices may have gaps that need to be filled between, for example, <NUM> and <NUM>. It is possible to stack metal nanowire arrays on top of each other to accommodate such gaps, but that causes interfaces between the arrays that create loss of heat transfer capabilities. Therefore, other heat sink materials are often employed for larger gaps than <NUM>, such as a polymer fill, that have reduced heat transfer capabilities than metal nanowire arrays.

Further, known single layer metal nanowire arrays that have vertically-aligned nanowires are able to effectively move heat along the length of the nanowires, but have poor lateral conductivity as a result of being nearly completely unidirectional, i.e. vertically aligned. However, for some applications, it may be desirable to laterally spread the heat being removed from the device or conduct electricity along the array. For example, the electrical conduction capability of a metal nanowire array parallels the thermal conduction capability of the array, where the lateral electrical conduction may be desirable for some applications, such as a ground plane.

Prior art can be found in <CIT> which generally relates to aluminum nanowire arrays and methods of preparation and use thereof.

The following discussion of the embodiments of the disclosure directed to a stacked multilayered metal nanowire array including lateral interposers provided between nanowire array layers and a method for fabricating the multilayered metal nanowire is merely exemplary in nature, and is in no way intended to limit the disclosure or its applications or uses. For example, the metal nanowire arrays are described as having application as a heat transfer device. However, as will be appreciated by those skilled in the art, the nanowire arrays may have other applications.

<FIG> show illustrations <NUM> of profile views of a series of sequential steps of a known "on substrate" process for fabricating a metal nanowire array <NUM> including vertically aligned and cylindrical metal nanowires <NUM> on a rigid substrate <NUM>, where the substrate <NUM> may be the component that heat is being drawn away from or the heat sink that the heat is being drawn to. <FIG> shows a thin metal seed layer <NUM>, for example, a <NUM> thick gold layer, that provides an electrical growth surface for the nanowires <NUM> deposited on the substrate <NUM>. A template <NUM>, such as a porous polymer or ceramic membrane, having vertically aligned cylindrical pores <NUM> is positioned on the seed layer <NUM>, such as by positioning the template <NUM> within a fixture (not shown) so that the template <NUM> is held in place from the sides, where the template <NUM> may be, for example, an inch square or a four-inch diameter circle and <NUM> thick. Although the pores <NUM> are cylindrical in this embodiment, it is known to provide templates having pores of other shapes that generate nanowires having that shape. The template <NUM> can be made by any suitable process to provide the pores <NUM>, such as by a hard anodization process known to those skilled in the art.

<FIG> shows that the nanowires <NUM> have been deposited or grown on the seed layer <NUM> and have filled the pores <NUM> such as by a suitable electrochemical deposition or electroplating process, where the seed layer <NUM> is used as a conductive interface for the electroplating process, so that a top of the nanowires <NUM> are even with a top end of the pores <NUM>. This can be obtained by providing a uniform growth where the deposition of the nanowires <NUM> is terminated when they exactly reach the top end of the pores <NUM> or by polishing the top surface of the seed layer <NUM> after the nanowires <NUM> are deposited. The array <NUM> is then subjected to a chemical etch that dissolves and removes the template <NUM> as shown in <FIG> to liberate the nanowires <NUM> and create the nanowire array <NUM>.

<FIG> show illustrations <NUM> of profile views of a series of sequential steps of a known freestanding growth process for fabricating a metal nanowire array <NUM>, where like elements to the illustrations <NUM> shown in <FIG> have the same reference number. In this embodiment, the metal seed layer <NUM> is deposited directly onto the template <NUM>. The seed layer <NUM> may be thickened before being attached to the template <NUM> by a metal backing support layer <NUM>, where the backing layer <NUM> may then be attached to the component that heat is being drawn away from.

As will be discussed in detail below, the present disclosure describes a method for fabricating a multilayered metal nanowire array that includes providing lateral interposers between the individual array layers that are formed by stacked templates. <FIG> show illustrations <NUM> of profile views of a series of sequential steps of an "on substrate" process for fabricating a multilayered metal nanowire array <NUM> including a stack of nanowire array layers <NUM> each including the metal nanowires <NUM> on the substrate <NUM>, where like elements to the illustrations <NUM> shown in <FIG> are identified by the same reference number. <FIG> shows three of the templates <NUM> stacked on top of each other, where they would be placed in a fixture <NUM> to form the stack so that the natural surface roughness of the templates <NUM> creates small lateral gaps <NUM> between the stacked templates <NUM>, where the fixture <NUM> is only shown in <FIG>. It is noted that the space between the top two templates <NUM> indicates that many other templates <NUM> can be provided in the stack, such as ten of the templates <NUM>. It is further noted that although the pores <NUM> from one template <NUM> to the next template <NUM> are shown aligned with each other, this is merely for illustrative purposes where the density of the pores <NUM> is very high, such as <NUM>-<NUM>%, and would be randomly distributed.

<FIG> shows that when the electroplating process is performed to form the nanowires <NUM> in the pores <NUM> the electroplating process also fills the gaps <NUM> with metal to form metal lateral interposers <NUM> that are thermally and electrically coupled to the nanowires <NUM>. The lateral interposers <NUM> allow the nanowires <NUM> from one array layer <NUM> to the next array layer <NUM> to be electrically and thermally coupled, where the array <NUM> is a single metal unit. Further, the interposers <NUM> allow electrical and thermal conduction in a lateral direction across the nanowire array <NUM>. It is noted that although the thickness of the interposers <NUM> are defined by the natural gap <NUM> that forms between the templates <NUM>, in other embodiments, the thickness of the interposers <NUM> can be increased to any suitable thickness by providing mechanical spacers <NUM> between the templates <NUM> in the fixture <NUM>. The spacers <NUM> can be of any suitable configuration and thickness that allows the interposers <NUM> to form around them.

<FIG> show illustrations <NUM> of profile views of a series of sequential steps of a freestanding growth process for fabricating a multilayered metal nanowire array <NUM>, where like elements to the illustrations <NUM> shown in <FIG> have the same reference number. In this embodiment, the seed layer <NUM> is required, but the backing support layer <NUM> is not needed because the interposers <NUM> hold the nanowire layers <NUM> together. Specifically, by providing the interposers <NUM>, the nanowire array <NUM> becomes more robust and easier to handle during the manufacture of the electrical devices. Further, since the nanowire array <NUM> is held together by the interposers <NUM>, tips of the nanowires <NUM> at the top and bottom layers <NUM> can be in contact with the rough surfaces of the various components without the need for a backing support layer.

<FIG> is a side view of an electronic assembly <NUM> including a multilayered metal nanowire array <NUM> positioned between an electrical component <NUM> and a heat sink <NUM>, where heat is being transferred from the component <NUM> to the heat sink <NUM> through the array <NUM>. The nanowire array <NUM> includes three array layers <NUM> having nanowires <NUM> held together by lateral interposers <NUM>. Tips <NUM> of the nanowires <NUM> at one end of the array <NUM> conform to a rough surface <NUM> of the heat sink <NUM> and tips <NUM> of the nanowires <NUM> at an opposite end of the array <NUM> conform to a rough surface <NUM> of the component <NUM> to illustrate how the nanowires <NUM> can conform to a rough surface for increased heat transfer capabilities.

The discussion above shows the nanowire array layers <NUM> are homogeneous in that they all have the same configuration of the nanowires <NUM>. However, in other embodiments, the nanowires layers <NUM> in the multilayer nanowire arrays <NUM> and <NUM> can have different diameter nanowires, different length nanowires, different density nanowires, different thickness of sections, different thickness of the interposers, etc. This may be desirable for certain electrical, thermal, chemical, optical and/or other functional uses of the nanowire array.

To illustrate this, <FIG> is a profile view of a multilayered metal nanowire array <NUM> including three nanowire array layers <NUM>, <NUM> and <NUM> separated by lateral interposers <NUM>, where the layer <NUM> has one thickness and includes nanowires <NUM> of one density and diameter, the layer <NUM> has another thickness and includes nanowires <NUM> of another density and diameter, and the layer <NUM> has a third thickness and includes nanowires <NUM> of a third density and diameter. By selecting different templates for each layer different combinations of individual layer arrays can be stacked in the final multilayered nanowire array.

Claim 1:
A method for fabricating a multilayered metal nanowire array (<NUM>), said method comprising:
stacking a plurality of porous templates (<NUM>) so that a gap (<NUM>) forms between each adjacent pair of templates (<NUM>);
depositing a metal in the pores of the templates (<NUM>) so that the metal produces nanowires (<NUM>) in the templates (<NUM>) and lateral interposers (<NUM>) in the gaps (<NUM>) between the templates; and
dissolving the templates (<NUM>) so as to produce the multilayered nanowire array (<NUM>) including the lateral interposers (<NUM>).