Patent Description:
The DEFLATE compression algorithm is a general-purpose compression algorithm (e.g., implemented in ZLIB, GZIP, etc.). DEFLATE is based on the LZ77 algorithm for finding data matches, and DEFLATE encodes the LZ77 output with Huffman encoded symbols. The compressed stream is composed of a series of blocks, where the block header defines the Huffman tables to be used in that block. In most cases, the Huffman codes are optimized for the contents of the block. This means that there needs to be two passes through the data: one to compute the statistics of the block's data, and one to do the actual compression. Between these two passes, calculations are made to compute a set of Huffman codes based on the statistics from the first pass.

<CIT> (<NUM>-<NUM>-<NUM>) describes a method and apparatus providing for data compression with deflate block overhead reduction through the use of "pseudo-dynamic" Huffman codes to enable single deflate block encoding in a deflate algorithm implementation. Further, provided is data compression with deflate block overhead reduction through the use of "pseudo-dynamic" Huffman codes to enable single deflate block encoding in a deflate algorithm implementation, with inflation detection and mitigation capabilities.

<CIT> (<NUM>-<NUM>-<NUM>) describes a system and method of selecting a predefined Huffman dictionary from a bank of dictionaries. The dictionary selection mechanism effectively breaks the built-in tradeoff between compression ratio and compression rate for both hardware and software compression implementations. A mechanism is provided for automatically creating a predefined Huffman dictionary for a set of input files. The dictionary selection mechanism achieves high compression rate and ratio leveraging predefined Huffman dictionaries and provides a mechanism for dynamically speculating which predefined dictionary to select per input data block, thereby achieving close to a dynamic Huffman ratio at a static Huffman rate. In addition, a feedback loop is used to monitor the ongoing performance of the preset currently selected for use by the hardware accelerator. If the current preset is not optimal it is replaced with an optimal preset.

The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:.

Embodiments discussed herein variously provide techniques and mechanisms for hardware compression. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including integrated circuitry which is operable to provide hardware compression.

In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "in" includes "in" and "on.

The term "device" may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.

The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- <NUM>% of a target value. For example, unless otherwise specified in the explicit context of their use, the terms "substantially equal," "about equal" and "approximately equal" mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/-<NUM>% of a predetermined target value.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For example, the terms "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material "over" a second material in the context of a figure provided herein may also be "under" the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term "between" may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material "between" two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

With reference to <FIG>, an embodiment of an integrated circuit <NUM> may include a hardware compressor <NUM> to compress data. The hardware compressor <NUM> may include circuitry <NUM> to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. In some embodiments, the circuitry <NUM> may be configured to provide multiple modes of operation for the hardware compressor <NUM>. In one mode of operation (e.g., a one-descriptor mode), for example, the circuitry <NUM> may be configured to store an entire set of job data in the history buffer in response to a single job for the hardware compressor <NUM> where a size of the job data is less than or equal to a size of the history buffer, compute the one or more code tables for the job data in response to the single job, compute the compression stream header based on the computed one or more code tables for the job data in response to the single job, and generate compressed output data for the job data stored in the history buffer based on the computed one or more code tables and the computed compression stream header in response to the single job. In one mode of operation (e.g., a two-descriptor mode), the circuitry <NUM> may be configured to store the computed one or more code tables and the computed compression stream header to memory in response to a first job for the hardware compressor <NUM> with job data that exceeds a size of the history buffer, and generate compressed output data for the job data based on the stored one or more code tables and the stored compression stream header in response to a second job for the hardware compressor.

In some embodiments, in one mode of operation (e.g., a statistics-read mode), the circuitry <NUM> may be further configured to read statistics from the input data, and compute the one or more code tables and the compression stream header based on the read statistics. In one mode of operation (e.g., a no-header mode), for example, the circuitry <NUM> may be configured to output the computed one or more code tables without the compression stream header. In one mode of operation (e.g., a complete-tree mode), for example, the circuitry <NUM> may be configured to replace a count of zero for a possible token with a non-zero value. In some embodiments, in one mode of operation (e.g., a hybrid-compress mode), the circuitry <NUM> may be further configured to calculate an expected compressed size for both canned codes and dynamic codes after a first pass, and load a set of code tables and a compression stream header for a second pass that corresponds to either dynamic codes or canned codes based on a lower result of the respective calculated expected compressed sizes. Examples of the various modes of operation are described in additional detail below. The circuitry <NUM> may also be configured to set a maximum code length limit based on a user configurable parameter.

Embodiments of the hardware compressor <NUM> and/or circuitry <NUM> may be incorporated in or integrated with a processor including, for example, the core <NUM> (<FIG>), the cores 1102A-N (<FIG>, <FIG>), the processor <NUM> (<FIG>), the co-processor <NUM> (<FIG>), the processor <NUM> (<FIG>), the processor/coprocessor <NUM> (<FIG>), the coprocessor <NUM> (<FIG>), the coprocessor <NUM> (<FIG>), and/or the processors <NUM>, <NUM> (<FIG>).

With reference to <FIG>, an embodiment of a method <NUM> may include storing input data in a history buffer of a hardware compressor at box <NUM>, computing one or more code tables by the hardware compressor based on the input data at box <NUM>, and computing a compression stream header by the hardware compressor based on the computed one or more code tables at box <NUM>. Some embodiments of the method <NUM> may further include providing multiple modes of operation for the hardware compressor at box <NUM>. For example, in one mode of operation at box <NUM>, the method <NUM> may include storing an entire set of job data in the history buffer in response to a single job for the hardware compressor where a size of the job data is less than or equal to a size of the history buffer at box <NUM>, computing the one or more code tables for the job data in response to the single job at box <NUM>, computing the compression stream header based on the computed one or more code tables for the job data in response to the single job at box <NUM>, and generating compressed output data for the job data stored in the history buffer based on the computed one or more code tables and the computed compression stream header in response to the single job at box <NUM>. In another mode of operation, the method <NUM> may include storing the computed one or more code tables and the computed compression stream header to memory in response to a first job for the hardware compressor with job data that exceeds a size of the history buffer at box <NUM>, and generating compressed output data for the job data based on the stored one or more code tables and the stored compression stream header in response to a second job for the hardware compressor at box <NUM>.

Some embodiments of the method <NUM>, in one mode of operation at box <NUM>, may further include reading statistics from the input data at box <NUM>, and computing the one or more code tables and the compression stream header based on the read statistics at box <NUM>. In another mode of operation, the method <NUM> may include outputting the computed one or more code tables without the compression stream header at box <NUM>. In another mode of operation, the method <NUM> may include replacing a count of zero for a possible token with a non-zero value at box <NUM>. In another mode of operation, the method <NUM> may include calculating an expected compressed size for both canned codes and dynamic codes after a first pass at box <NUM>, and loading a set of code tables and a compression stream header for a second pass that corresponds to either dynamic codes or canned codes based on a lower result of the respective calculated expected compressed sizes at box <NUM>. Some embodiments of the method <NUM> may further include setting a maximum code length limit based on a user configurable parameter at box <NUM>.

As the input data is being processed, the data is being written into the history buffer and the statistics are being accumulated. After the history buffer fills up, the buffer wraps around and starts overwriting the oldest data. After all the data is processed, the code tables (e.g., Huffman tables) and headers (e.g., DEFLATE headers) are computed from the statistics. If the total input size is no bigger than the history buffer, in the one-descriptor mode, the hardware can operate to replay the history buffer back through the input (and back into the history buffer) to generate compressed output data.

With reference to <FIG>, an embodiment of an apparatus <NUM> may include two or more hardware accelerator engines <NUM>, memory <NUM> communicatively coupled to the two or more hardware accelerator engines <NUM> to store one or more jobs for the two or more hardware accelerator engines <NUM>, and a controller <NUM> communicatively coupled to the memory <NUM> and the two or more hardware accelerator engines <NUM> to control the one or more jobs for the two or more hardware accelerator engines <NUM>. Each of the two or more hardware accelerator engines <NUM> may include a hardware decompressor <NUM> and access to a hardware compressor <NUM> shared among the two or more hardware accelerator engines <NUM>. The hardware compressor <NUM> may include circuitry to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. In some embodiments, the circuitry <NUM> may be configured to provide multiple modes of operation for the hardware compressor <NUM>.

In one mode of operation, for example, the circuitry <NUM> may be configured to store an entire set of job data in the history buffer in response to a single job for the hardware compressor <NUM> where a size of the job data is less than or equal to a size of the history buffer, compute the one or more code tables for the job data in response to the single job, compute the compression stream header based on the computed one or more code tables for the job data in response to the single job, and generate compressed output data for the job data stored in the history buffer based on the computed one or more code tables and the computed compression stream header in response to the single job. In another mode of operation, for example, the circuitry <NUM> may be configured to store the computed one or more code tables and the computed compression stream header to the memory in response to a first job for the hardware compressor <NUM> with job data that exceeds a size of the history buffer, and generate compressed output data for the job data based on the stored one or more code tables and the stored compression stream header in response to a second job for the hardware compressor <NUM>.

In another mode of operation, for example, the circuitry <NUM> may be further configured to read statistics from the input data, and compute the one or more code tables and the compression stream header based on the read statistics. In another mode of operation, for example, the circuitry <NUM> may be configured to output the computed one or more code tables without the compression stream header. In some embodiments, in another mode of operation, the circuitry <NUM> may be configured to replace a count of zero for a possible token with a non-zero value. In another mode of operation, the circuitry <NUM> may be further configured to calculate an expected compressed size for both canned codes and dynamic codes after a first pass, and load a set of code tables and a compression stream header for a second pass that corresponds to either dynamic codes or canned codes based on the respective calculated expected compressed sizes. For example, the circuitry <NUM> may also be configured to set a maximum code length limit based on a user configurable parameter.

Embodiments of the hardware accelerator engines <NUM>, the memory <NUM>, and/or the controller <NUM> may be incorporated in or integrated with a processor including, for example, the core <NUM> (<FIG>), the cores 1102A-N (<FIG>, <FIG>), the processor <NUM> (<FIG>), the co-processor <NUM> (<FIG>), the processor <NUM> (<FIG>), the processor/coprocessor <NUM> (<FIG>), the coprocessor <NUM> (<FIG>), the coprocessor <NUM> (<FIG>), and/or the processors <NUM>, <NUM> (<FIG>).

Some embodiments provide technology for efficient and flexible DEFLATE header and Huffman code generation. In some systems, a compression accelerator may perform the matching and encoding, but the computation of the Huffman tables may be performed by a host CPU. For example, the software issues one job to compress the data, generate no compressed output, and count how many times each output token (e.g., literals and match lengths, distances) appeared. The software then takes those statistics, computes the Huffman tables and the DEFLATE header, and then submits a second job to compress the same data a second time, but this time the compression accelerator outputs the generated tokens using the newly constructed Huffman tables.

The matching in the accelerator may be done against a sliding "history window" of the preceding N bytes. The DEFLATE standard supports a history of up to 32KB but, to reduce the accelerator size, the accelerator may support a smaller history size (e.g., 4KB). For example, a hardware accelerator needs enough on-die memory to store that much data, against which to make matches, but more on-die memory increases the area of the accelerator. In some systems, the matching in the accelerator is done fast enough that the matching may be done twice, rather than saving the results of the matching between passes.

As noted above, a traditional approach is that the first pass through the data generates some form of intermediate format output in addition to accumulating the statistics. The second pass then transcodes this intermediate format data using the newly generated Huffman tables. Generating a stream of intermediate format tokens, which are then transcoded after calculation of the Huffman tables is a suitable arrangement for a two-descriptor mode (in this case, a "match descriptor" and a "transcode descriptor"). To do both operations together as a single descriptor, however, storage may be needed in the accelerator for those intermediate format tokens (e.g., in addition to the history buffer, which is needed for the matching). Some embodiments may perform the matching for both passes through the hardware in the one-descriptor mode, as long as the size is small enough, advantageously avoiding the overhead of storing the intermediate tokens by taking advantage of the input data already stored in the history buffer.

Some embodiments may provide hardware support in a compression engine to create the Huffman tables and DEFLATE header. Advantageously, some embodiments may provide an interface to the compression engine that is efficient from a performance point of view, and also efficient from a silicon area point of view, while allowing a great deal of flexibility for software to utilize the compression engine for various different usages. Some embodiments of a hardware compressor may include a hardware Huffman table generator and a hardware DEFLATE header generator, and may support multiple modes of operation to provide efficient and flexible utilization of the various hardware components of the hardware compressor. Non-limiting examples of operation modes for the Huffman table / Header generator include a one-descriptor mode, a two-descriptor mode, a statistics-input mode, a no-header mode, a complete-tree mode, and a hybrid-compress mode.

With reference to <FIG>, an embodiment of hardware compressor <NUM> may include an input data unit <NUM>, a look ahead buffer <NUM>, a history buffer <NUM>, compare logic <NUM>, a Huffman encoder statistics unit <NUM>, a counter / code memory <NUM>, and a Huffman table and DEFLATE header calculator <NUM>, coupled as shown. The look ahead buffer <NUM> contains the next series of input bytes, and the history buffer <NUM> contains the previous 4KB of the input. The compare logic <NUM> tries to find a match between the new data (from the look-ahead buffer <NUM>) and the old data (from the history buffer <NUM>). The comparison generates a stream of tokens (e.g., matches of the form <length, relative distance> or unmatched literal bytes) that go to the Huffman unit <NUM>.

In the first pass, the Huffman unit <NUM> increment counters, and in the second pass, it uses the counter memory <NUM> to load the Huffman tables (created by the Huffman table calculator <NUM>) to Huffman encode the stream of tokens. The local counter / code memory <NUM> has as many rows as there are symbols, and each entry can be viewed as either a counter which is incremented during the first pass or a variable-length code for that symbol that the encoder unit <NUM> uses for the second pass encoding. Advantageously, performing the Huffman table and DEFLATE header calculations in hardware decreases the CPU load and reduces latency.

For scenarios where the one-descriptor mode is applicable, embodiments of the hardware compressor <NUM> further reduces the latency as compared to both two-descriptor mode scenarios or software generation. Advantageously, embodiments may provide the one-descriptor mode with almost no additional area cost. Many memory systems may utilize a 4KB page size. Embodiments of a hardware compressor with a 4KB history buffer may advantageously support memory compression usage (e.g., page-level compression managed by system software) in the one-descriptor mode, with significant reduction in latency.

With reference to <FIG>, an embodiment of a hardware accelerator <NUM> may include an IO fabric interface <NUM>, an address translation cache (ATC) <NUM>, a configuration module <NUM>, and two or more memory mapped I/O (MMIO) portals (MP) <NUM> providing work queues to control logic <NUM>, coupled as shown. The hardware accelerator <NUM> may further include two or more acceleration engines <NUM> communicatively coupled to the I/O fabric interface <NUM>, the ATC <NUM>, the configuration module <NUM>, and the control logic <NUM>. Each of the acceleration engines <NUM> may include a direct memory access (DMA) interface <NUM>, a hardware decompressor <NUM>, a structured query language (SQL) filter engine <NUM>, and access to a shared hardware compressor <NUM>, coupled as shown. For example, the hardware accelerator <NUM> may include two compressor cores shared dynamically across of the acceleration engines <NUM>.

For example, the hardware compressor <NUM> may include one or more features of the embodiments described herein. In particular, embodiments of the hardware compressor <NUM> may include a history buffer, a look ahead buffer, compare logic, a Huffman encoder statistics unit, counter / code memory, Huffman table calculation logic, and DEFLATE header calculation logic, coupled as shown in <FIG>. The hardware compressor <NUM> may be configured to support multiple mode of operation including for example, a one-descriptor mode, a two-descriptor mode, a statistics-input mode, a no-header mode, a complete-tree mode, and a hybrid-compress mode. The hardware compressor <NUM> may also be configured to set a maximum code-length limit based on a user configurable parameter (e.g., set via the configuration module <NUM>).

The one-descriptor mode provides a simplified flow for the software. The software submits a single job and gets the compressed data out from the hardware compressor. In this case, the hardware performs both passes as part of the same job. The history buffer memory is utilized to store the input data between passes, advantageously providing one-descriptor compression with essentially no area cost. Note that the one-descriptor mode can only be used for data no bigger than the history buffer size. Some embodiments may provide a history buffer size which is the same size as a typical memory page (e.g., 4KB).

In one-descriptor mode, because the input is not bigger than the history buffer, the history buffer contains the entire input. After the hardware compressor computes the Huffman tables, rather than writing the tables out, the tables can be used directly for the second pass. The input data is read out of the history buffer (e.g., see the dashed in <FIG>) and fed back in as if it were normal input data. The re-use of the input data stored in the history buffer allows the hardware compressor to do two passes through the data and generate the final Huffman encoded token stream, advantageously without increasing the area footprint and with no wasted mesh/memory bandwidth.

For the two-descriptor mode, the software submits a first job for the first pass. In the first pass, rather than writing the statistics to the output (e.g., for the software to compute the Huffman tables and DEFLATE header), embodiments of the hardware compressor take the statistics, compute the Huffman Tables, compute the DEFLATE header, and then write the information needed for the second pass to memory (e.g., after the first pass has updated the counters, the hardware Huffman table calculation logic will take the counters, compute the Huffman tables, and write those back into the counter memory). In some embodiments, the computed Huffman tables may be written to output. The software then submits a second job for the second pass to generate the compressed output. Advantageously, the software no longer has to do the relatively expensive calculations (e.g., software cost is typically > <NUM> cycles per block) for the tables or the header, saving appreciable time and latency, particularly for smaller buffers. Embodiments of an accelerator engine may support a batch mode where software can submit both descriptors as a batch with a flag that there is a fence (e.g., because job2 uses the results of job1), further reducing latency.

In statistics-input mode, the hardware compressor reads the statistics from the input (e.g., rather than generating the statistics itself from matches), computes the tables and header, and then write that information to memory. The statistics-input mode can be used, for example, to offload the table/header generation for a software matcher operating at a higher level of compression, or with a larger history buffer size (e.g. 32KB).

In the no-header mode, some embodiments may use the table generation functionality for non-DEFLATE usages (e.g., such as proprietary formats), or Huffman encoding of literals (e.g., as in ZSTANDARD). Other standards may not use the DEFLATE, but may use the Huffman tables. The time to sort and construct optimal Huffman trees is substantial in software, and embodiments of the hardware compressor may offload this task even for non-DEFLATE usages.

Normally, Huffman tokens that have a zero count (e.g., aren't being used) do not get a Huffman code assigned to them, which results in a more efficient table. In some cases, however, the user may want to operate in "semi-dynamic" mode. In the semi-dynamic mode, the first block is done in a fully dynamic manner, as described previously. But then if the data in the following blocks has similar statistics, the user can decrease the latency by using the same Huffman tables as for the first block. This avoids one pass on all but the first block.

The issue is that there is no guarantee that a token that happened to not appear in the first block won't appear in a subsequent block (e.g., this scenario may be rare, but not impossible). In order to deal with this, the tables created by the initial block need to be "complete", where all of the possible tokens need to have valid codes created for them.

To support this, some embodiments of the hardware compressor have a setting that causes a zero count for any possible token to be replaced with a count of one (e.g., or another small non-zero value). Replacing a count of zero for a possible token with a count of one results in such tokens being assigned a large code. But if this token appears later, a valid output is generated.

The DEFLATE standard requires that all Huffman codes be no longer than <NUM> bits in length. In some cases, the statistics could result in a set of tables containing longer codes. Because of this, the hardware compressor has logic to adjust the Huffman trees so as to limit the codes to a length of <NUM>.

In some cases, the user may want to limit the maximum code size to a smaller value. For example, if the decoder was processing one token per cycle and trying to speculatively decode a second token at various bit offsets from the main token, decompression latency may be improved (e.g., at the cost of slightly larger compressed size) by limiting the Huffman token length during compression based on the decompressor design.

Other compression standards may also have smaller limits of the code lengths. These other standards may utilize embodiments of the hardware accelerator to generate Huffman codes by specifying an appropriate maximum code-length limit parameter. For example, a configuration tool or interface may provide a user configurable parameter to allow the user to set a maximum code length limit.

DEFLATE prescribes dynamic Huffman coded blocks. However, other methods can be employed such as semi-dynamic described above, or "canned" codes. For example, a canned code is where a code is determined a priori that works well for some type of data (e.g. HTML). Rather than compute codes for each data block, the canned code may be used. Compatibility may be broken with DEFLATE by storing a single copy the header separately, and starting with the first symbol. Some embodiments of an accelerator engine may support canned mode.

Because the header size is on the order of ten of bytes (e.g., typically < <NUM> bytes), the size of the header is often immaterial for large buffers. For sizes of data <= 4KB, however, using canned codes may give a net better size than dynamic codes in some cases. That is, the increased size due to using less-optimized Huffman codes may be smaller than the size of the header. To know which one is better, some embodiments may do a first pass and then decide whether to compress in the second pass with canned codes or dynamic codes.

In some embodiments, if the hardware compressor provides the statistics and the tree/header after the first pass, then the software can calculate the expected size with both canned codes and dynamic codes, and then load the appropriate set of tables for the second pass (e.g., with a DEFLATE header for dynamic codes, or a null header for canned codes).

Those skilled in the art will appreciate that a wide variety of devices may benefit from the foregoing embodiments. The following exemplary core architectures, processors, and computer architectures are non-limiting examples of devices that may beneficially incorporate embodiments of the technology described herein.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: <NUM>) a general purpose in-order core intended for general-purpose computing; <NUM>) a high performance general purpose out-of-order core intended for general-purpose computing; <NUM>) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: <NUM>) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and <NUM>) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: <NUM>) the coprocessor on a separate chip from the CPU; <NUM>) the coprocessor on a separate die in the same package as a CPU; <NUM>) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and <NUM>) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

<FIG> is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. <FIG> is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in <FIG> illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

The execution engine unit <NUM> includes the rename/allocator unit <NUM> coupled to a retirement unit <NUM> and a set of one or more scheduler unit(s) <NUM>. The scheduler unit(s) <NUM> represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) <NUM> is coupled to the physical register file(s) unit(s) <NUM>. Each of the physical register file(s) units <NUM> represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit <NUM> comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) <NUM> is overlapped by the retirement unit <NUM> to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit <NUM> and the physical register file(s) unit(s) <NUM> are coupled to the execution cluster(s) <NUM>. The execution cluster(s) <NUM> includes a set of one or more execution units <NUM> and a set of one or more memory access units <NUM>. The execution units <NUM> may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) <NUM>, physical register file(s) unit(s) <NUM>, and execution cluster(s) <NUM> are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) <NUM>). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units <NUM>/<NUM> and a shared L2 cache unit <NUM>, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level <NUM> (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

<FIG> illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.

<FIG> is a block diagram of a single processor core, along with its connection to the on-die interconnect network <NUM> and with its local subset of the Level <NUM> (L2) cache <NUM>, according to embodiments of the invention. In one embodiment, an instruction decoder <NUM> supports the x86 instruction set with a packed data instruction set extension. An L1 cache <NUM> allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit <NUM> and a vector unit <NUM> use separate register sets (respectively, scalar registers <NUM> and vector registers <NUM>) and data transferred between them is written to memory and then read back in from a level <NUM> (L1) cache <NUM>, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache <NUM> is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache <NUM>. Data read by a processor core is stored in its L2 cache subset <NUM> and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset <NUM> and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is <NUM>-bits wide per direction.

<FIG> is an expanded view of part of the processor core in <FIG> according to embodiments of the invention. <FIG> includes an L1 data cache 1006A part of the L1 cache <NUM>, as well as more detail regarding the vector unit <NUM> and the vector registers <NUM>. Specifically, the vector unit <NUM> is a <NUM>-wide vector processing unit (VPU) (see the <NUM>-wide ALU <NUM>), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit <NUM>, numeric conversion with numeric convert units 1022A-B, and replication with replication unit <NUM> on the memory input. Write mask registers <NUM> allow predicating resulting vector writes.

<FIG> is a block diagram of a processor <NUM> that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in <FIG> illustrate a processor <NUM> with a single core 1102A, a system agent <NUM>, a set of one or more bus controller units <NUM>, while the optional addition of the dashed lined boxes illustrates an alternative processor <NUM> with multiple cores 1102A-N, a set of one or more integrated memory controller unit(s) <NUM> in the system agent unit <NUM>, and special purpose logic <NUM>.

Thus, different implementations of the processor <NUM> may include: <NUM>) a CPU with the special purpose logic <NUM> being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 1102A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); <NUM>) a coprocessor with the cores 1102A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and <NUM>) a coprocessor with the cores 1102A-N being a large number of general purpose in-order cores. Thus, the processor <NUM> may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including <NUM> or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor <NUM> may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of respective caches 1104A-N within the cores 1102A-N, a set or one or more shared cache units <NUM>, and external memory (not shown) coupled to the set of integrated memory controller units <NUM>. The set of shared cache units <NUM> may include one or more mid-level caches, such as level <NUM> (L2), level <NUM> (L3), level <NUM> (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit <NUM> interconnects the integrated graphics logic <NUM>, the set of shared cache units <NUM>, and the system agent unit <NUM>/integrated memory controller unit(s) <NUM>, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units <NUM> and cores <NUM>-A-N.

In some embodiments, one or more of the cores 1102A-N are capable of multithreading. The system agent <NUM> includes those components coordinating and operating cores 1102A-N. The system agent unit <NUM> may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 1102A-N and the integrated graphics logic <NUM>. The display unit is for driving one or more externally connected displays.

The cores 1102A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 1102A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

<FIG> are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to <FIG>, shown is a block diagram of a system <NUM> in accordance with one embodiment of the present invention. The system <NUM> may include one or more processors <NUM>, <NUM>, which are coupled to a controller hub <NUM>. In one embodiment the controller hub <NUM> includes a graphics memory controller hub (GMCH) <NUM> and an Input/Output Hub (IOH) <NUM> (which may be on separate chips); the GMCH <NUM> includes memory and graphics controllers to which are coupled memory <NUM> and a coprocessor <NUM>; the IOH <NUM> couples input/output (I/O) devices <NUM> to the GMCH <NUM>. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory <NUM> and the coprocessor <NUM> are coupled directly to the processor <NUM>, and the controller hub <NUM> in a single chip with the IOH <NUM>.

The optional nature of additional processors <NUM> is denoted in <FIG> with broken lines. Each processor <NUM>, <NUM> may include one or more of the processing cores described herein and may be some version of the processor <NUM>.

The memory <NUM> may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub <NUM> communicates with the processor(s) <NUM>, <NUM> via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection <NUM>.

In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub <NUM> may include an integrated graphics accelerator.

In one embodiment, the processor <NUM> executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor <NUM> recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor <NUM>. Accordingly, the processor <NUM> issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor <NUM>. Coprocessor(s) <NUM> accept and execute the received coprocessor instructions.

Referring now to <FIG>, shown is a block diagram of a first more specific exemplary system <NUM> in accordance with an embodiment of the present invention. As shown in <FIG>, multiprocessor system <NUM> is a point-to-point interconnect system, and includes a first processor <NUM> and a second processor <NUM> coupled via a point-to-point interconnect <NUM>. Each of processors <NUM> and <NUM> may be some version of the processor <NUM>. In one embodiment of the invention, processors <NUM> and <NUM> are respectively processors <NUM> and <NUM>, while coprocessor <NUM> is coprocessor <NUM>. In another embodiment, processors <NUM> and <NUM> are respectively processor <NUM> coprocessor <NUM>.

Processors <NUM> and <NUM> are shown including integrated memory controller (IMC) units <NUM> and <NUM>, respectively. Processor <NUM> also includes as part of its bus controller units point-to-point (P-P) interfaces <NUM> and <NUM>; similarly, second processor <NUM> includes P-P interfaces <NUM> and <NUM>. Processors <NUM>, <NUM> may exchange information via a point-to-point (P-P) interface <NUM> using P-P interface circuits <NUM>, <NUM>. As shown in <FIG>, IMCs <NUM> and <NUM> couple the processors to respective memories, namely a memory <NUM> and a memory <NUM>, which may be portions of main memory locally attached to the respective processors.

Processors <NUM>, <NUM> may each exchange information with a chipset <NUM> via individual P-P interfaces <NUM>, <NUM> using point to point interface circuits <NUM>, <NUM>, <NUM>, <NUM>. Chipset <NUM> may optionally exchange information with the coprocessor <NUM> via a high-performance interface <NUM> and an interface <NUM>. In one embodiment, the coprocessor <NUM> is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

As shown in <FIG>, various I/O devices <NUM> may be coupled to first bus <NUM>, along with a bus bridge <NUM> which couples first bus <NUM> to a second bus <NUM>. In one embodiment, one or more additional processor(s) <NUM>, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus <NUM>. In one embodiment, second bus <NUM> may be a low pin count (LPC) bus. Various devices may be coupled to a second bus <NUM> including, for example, a keyboard and/or mouse <NUM>, communication devices <NUM> and a storage unit <NUM> such as a disk drive or other mass storage device which may include instructions/code and data <NUM>, in one embodiment. Further, an audio I/O <NUM> may be coupled to the second bus <NUM>. Note that other architectures are possible. For example, instead of the point-to-point architecture of <FIG>, a system may implement a multi-drop bus or other such architecture.

Referring now to <FIG>, shown is a block diagram of a second more specific exemplary system <NUM> in accordance with an embodiment of the present invention. Like elements in <FIG> and <FIG> bear like reference numerals, and certain aspects of <FIG> have been omitted from <FIG> in order to avoid obscuring other aspects of <FIG>.

Referring now to <FIG>, shown is a block diagram of a SoC <NUM> in accordance with an embodiment of the present invention. Similar elements in <FIG> bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In <FIG>, an interconnect unit(s) <NUM> is coupled to: an application processor <NUM> which includes a set of one or more cores 1102A-N and shared cache unit(s) <NUM>; a system agent unit <NUM>; a bus controller unit(s) <NUM>; an integrated memory controller unit(s) <NUM>; a set or one or more coprocessors <NUM> which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit <NUM>; a direct memory access (DMA) unit <NUM>; and a display unit <NUM> for coupling to one or more external displays. In one embodiment, the coprocessor(s) <NUM> include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

Emulation (including binary translation, code morphing, etc.).

<FIG> is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. <FIG> shows a program in a high level language <NUM> may be compiled using an x86 compiler <NUM> to generate x86 binary code <NUM> that may be natively executed by a processor with at least one x86 instruction set core <NUM>. The processor with at least one x86 instruction set core <NUM> represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (<NUM>) a substantial portion of the instruction set of the Intel x86 instruction set core or (<NUM>) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler <NUM> represents a compiler that is operable to generate x86 binary code <NUM> (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core <NUM>. Similarly, <FIG> shows the program in the high level language <NUM> may be compiled using an alternative instruction set compiler <NUM> to generate alternative instruction set binary code <NUM> that may be natively executed by a processor without at least one x86 instruction set core <NUM> (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter <NUM> is used to convert the x86 binary code <NUM> into code that may be natively executed by the processor without an x86 instruction set core <NUM>. This converted code is not likely to be the same as the alternative instruction set binary code <NUM> because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter <NUM> represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code <NUM>.

Techniques and architectures for hardware compression are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. It will be apparent, however, to one skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention.

Some portions of the detailed description herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated.

Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Certain embodiments also relate to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description herein. In addition, certain embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.

Claim 1:
An integrated circuit (<NUM>), comprising:
a substrate; and
a hardware compressor (<NUM>) coupled to the substrate to compress data, the hardware compressor including circuitry (<NUM>) to:
store input data in a history buffer (<NUM>),
compute dynamic code tables based on the input data in a first pass of the input data,
compute a compression stream header based on the computed dynamic code tables in the first pass, and
provide multiple modes of operation for the hardware compressor, wherein, in one mode of operation, the circuitry is further to calculate an expected compressed size for both canned codes and the dynamic codes after the first pass, and load a set of code tables and a compression stream header, for a second pass of the input data to compress the input data, that corresponds to either the dynamic codes or the canned codes based on a lower result of the respective calculated expected compressed sizes, wherein
the canned codes are a priori determined, and the compression stream header corresponding to the dynamic codes is the computed compression stream header in the first pass and the compression stream header corresponding to the canned codes is a null header.