Patent Description:
Image sensors in solid-state imaging devices include photoelectric conversion elements generating a photocurrent in proportion to the received radiation intensity. A pixel circuit transforms the small photo current generated by the photoelectric conversion element into a comparatively large output voltage which a downstream analog-to-digital converter converts into a digital signal. Typically, the pixel circuit includes the amplifier portion of a source follower circuit (common-drain amplifier) that passes the pixel output signal to a data signal line. The data signal line is shared by a plurality of pixel circuits assigned to the same pixel column and the pixel output signals of the pixel column are output individually in a time multiplex regime. A column signal processing unit sequentially receives and processes the pixel output signals.

Document <CIT> describes pixel circuits with source follower transistors outputting pixel output signals to a column readout line. A configurable current source is coupled between the column output line and ground. During operation, the configurable current source supplies a fixed current bias to the selected source-follower transistor via the column readout line. The current source is implemented using metal-oxide-semiconductor transistor circuitry and is characterized by parameters such as transconductance and drain saturation voltage. For a given current source configuration, there is a tradeoff between transconductance and drain saturation voltage, such that increased values of the transconductance result in lower values of the drain saturation voltage and vice versa. By changing transconductance and drain saturation voltage, the current source can be adapted to different ambient lighting conditions.

An image sensor described in document <CIT> includes a pixel array having a plurality of pixels. Each pixel generates image data in response to incident light. A bit line which is coupled to a column of pixels of the pixel array is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of the other portion of the bit line.

Document <CIT> describes pixel circuits with source follower transistors outputting pixel output signals to a vertical signal line. A constant current source circuit unit provides the load for the source follower transistors. The constant current source circuit unit includes one constant current source for each single vertical signal line. Each constant current source functions as a load of one of the source follower transistors. The constant current source includes a switch, a capacitor, and a load transistor. The load transistor is electrically connected between the vertical signal line and GND. The switch comes into conduction at a predetermined timing by the control of a system control unit, and a predetermined charge is accumulated in the capacitor. The capacitor applies a predetermined voltage in accordance with the accumulated charge to the gate electrode of the load transistor.

Document <CIT> describes a pixel circuit for a display system. The pixel circuit includes a transistor for providing a pixel current to a light emitting device, and a storage capacitor electrically coupling to the transistor. A time-variant voltage is coupled to the storage capacitors of a plurality of pixel circuits in a predetermined timing for providing a current for turning on the light emitting device. In a first cycle in a programming operation, the time-variant voltage provided to the storage capacitors is changed from a reference voltage to a programming voltage. In a second cycle in the programming operation, the time-variant voltage is maintained at the programming voltage. The capacitive driving technique with the time-variant voltage-controlled storage capacitor improves the settling time of the programming and compensates for display aging.

It is desirable to further improve the dynamic range of image sensor arrays and to reduce noise effects.

The source follower circuits connected to the same data signal line share a common constant current source as emitter resistor, wherein the constant current source is typically an nFET (n channel field effect transistor) with constant gate bias. For a linear response of the source follower circuits, the nFET is operated in the saturation region. Operation in the saturation region requires that a voltage drop between drain and emitter of the nFET is greater than a minimum voltage, e.g. greater than 300mV to 400mV.

The present disclosure mitigates shortcomings of image sensor arrays for intensity read-out attributed to the constant current sources used for pixel read-out.

To this purpose, an image sensor array according to the present disclosure includes a pixel circuit that generates a pixel output signal, wherein an amplitude of the pixel output signal is related to an intensity of detected light. The pixel circuit passes the pixel output signal to a data signal line for a selection period. A current control capacitor supplies a current to the data signal line through a first electrode in the selection period. A ramp generator generates a voltage ramp signal and passes the voltage ramp signal to a second electrode of the current control capacitor in the selection period.

A solid-state imaging device according to the present disclosure includes a plurality of pixel circuits, wherein each pixel circuit generates a pixel output signal with an amplitude related to an intensity of detected light. Each pixel circuit is assigned to one of a plurality of pixel columns. The solid-state imaging device further includes a plurality of data signal lines and a plurality of current control capacitors. Each data signal line receives the pixel output signals of a plurality of pixel circuits assigned to a same pixel column. A selected one of the pixel circuits passes the pixel output signal to the data signal line for a selection period. Each current control capacitor supplies a current to one of the data signal lines through a first electrode in the selection period. A ramp generator generates a voltage ramp signal and passes the voltage ramp signal to second electrodes of the current control capacitors in the selection period.

Embodiments for implementing techniques of the present disclosure (also referred to as "embodiments" in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various numerical values and the like in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

Connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The terms "electrically connected" and "signal-connected" may also include a connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. For example, electronic elements may be electrically connected or signal-connected through resistors, capacitors, and electronic switches such as transistors or transistor circuits, e.g. MOSFETs, transmission gates, and others.

The load path of a transistor is the controlled path of a transistor. For example, a voltage applied to a gate of a field effect transistor (FET) controls by field effect the current flow through the load path between source and drain.

Though in the following a technology for increasing dynamic range for pixel sensors is described in the context of certain types of active image sensors for intensity readout, the technology may also be used for other types of image sensors.

<FIG> illustrates a configuration example of a solid-state imaging device <NUM> including an image sensor assembly <NUM> and a signal processing unit <NUM> according to an embodiment of the present technology.

The image sensor assembly <NUM> may include a pixel array unit <NUM>, a row decoder <NUM>, a pixel driver unit <NUM>, a column signal processing unit <NUM>, and a sensor controller <NUM>.

The pixel array unit <NUM> includes a plurality of pixel circuits <NUM>. Each pixel circuit <NUM> includes a photoelectric conversion element PD and a number of FETs (field effect transistors) for controlling the signal output by the photoelectric conversion element PD. The photoelectric conversion devices PD may be arranged matrix-like in columns and rows. A subset of pixel circuits <NUM> assigned to the same column of photoelectric conversion devices PD forms a pixel column. The outputs of the pixel circuits <NUM> of the same pixel column are successively supplied to a data signal line (vertical signal line) VSL.

The row decoder <NUM> and the pixel driver unit <NUM> control driving of each pixel circuit <NUM> disposed in the pixel array unit <NUM>. In particular, the row decoder <NUM> may supply a control signal for selecting the pixel circuit <NUM> or the row of pixel circuits <NUM> to be driven to the pixel driver unit <NUM> according to an address signal from the sensor controller <NUM>. The pixel driver unit <NUM> may drive the FETs of the selected pixel circuit <NUM> according to driver timing signals supplied from the sensor controller <NUM> and the control signal supplied from the row decoder <NUM>.

The data signal lines VSL pass the output signals of the pixel circuits <NUM> (pixel output signals Vout) to the column signal processing unit <NUM>.

For pixel circuits <NUM> implementing intensity readout, the column signal processing unit <NUM> may include one or more ADCs (analog-to-digital converters <NUM>. The column signal processing unit <NUM> may include as much ADCs <NUM> as the pixel array unit <NUM> includes data signal lines VSL. Alternatively, the number of ADCs <NUM> may be lower than the number of data signal lines VSL and each ADC <NUM> may be multiplexed between two or more of the data signal lines VSLs. Each ADC <NUM> performs an analog-to-digital conversion on the pixel output signals successively passed from the pixel column and passes digital pixel data DPXS to the signal processing unit <NUM>. To this purpose, each ADC <NUM> may include a comparator <NUM>, a digital-to-analog converter <NUM> and a counter <NUM>.

The sensor controller <NUM> controls the components of the image sensor assembly <NUM>. For example, the sensor controller <NUM> may generate and pass the address to the row decoder <NUM>, and may generate and pass driving timing signals to the pixel driver unit <NUM>. In addition, the sensor controller <NUM> may generate and pass one or more control signals to the column signal processing unit <NUM>, e.g. to the ADCs <NUM>.

The pixel circuits <NUM> may be any active pixel sensors for intensity readout. The illustrated example refers to pixel circuits <NUM> for intensity readout with one photoelectric conversion element PD and four transistors (FETs) as active elements.

The photoelectric conversion element PD may include or may be composed of, for example, a photodiode. The FETs may include a transfer transistor <NUM>, a reset transistor <NUM>, an amplification transistor <NUM>, and a selection transistor <NUM>.

The photoelectric conversion element PD photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photoelectric conversion element PD corresponds to the intensity of the incident electromagnetic radiation. For example, the photoelectric conversion element PD may include or consist of a photodiode which converts electromagnetic radiation incident on a detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and/or ultraviolet radiation. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

The transfer transistor <NUM> is connected between the photoelectric conversion element PD and a floating diffusion region FD. The transfer transistor <NUM> serves as transfer element for transferring charge from the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD serves as temporary local charge storage. A transfer signal TG serving as a control signal is supplied to the gate (transfer gate) of the transfer transistor <NUM> through a transfer control line. Thus, the transfer transistor <NUM> may transfer electrons photoelectrically converted by the photoelectric conversion element PD to the floating diffusion region FD.

The reset transistor <NUM> is connected between the floating diffusion region FD and a power supply line to which a positive supply voltage VDD is supplied. A reset signal RES serving as a control signal is supplied to the gate of the reset transistor <NUM> through a reset control line. Thus, the reset transistor <NUM> serving as a reset element resets a floating diffusion potential Vfd of the floating diffusion region FD to that of the power supply line supplying the positive supply voltage VDD.

The floating diffusion region FD is connected to the gate of the amplification transistor <NUM> serving as an amplification element. The floating diffusion region FD functions as the input node of the amplification transistor <NUM>.

The amplification transistor <NUM> and the selection transistor <NUM> are connected in series between the power supply line and the data signal line VSL. Thus, the amplification transistor <NUM> is connected to the data signal line VSL through the selection transistor <NUM>.

A selection signal SEL serving as a control signal corresponding to an address signal is supplied to the gate of the selection transistor <NUM> through a selection control line, and turns on the selection transistor <NUM>. When the selection transistor <NUM> is turned on, the amplification transistor <NUM> amplifies the floating diffusion potential Vfd of the floating diffusion region FD and outputs a voltage corresponding to the floating diffusion potential Vfd to the data signal line VSL. The data signal line VSL passes the pixel output signal Vout from the pixel circuit <NUM> to the column signal processing unit <NUM>.

Since the respective gates of the transfer transistor <NUM>, the reset transistor <NUM>, and the selection transistor <NUM> are, for example, connected in units of pixel rows, these operations may be simultaneously performed for each of the pixel circuits <NUM> of one pixel row.

The data signal line VSL is further connected to a constant current circuit <NUM> that includes a current control capacitor <NUM> and a ramp generator <NUM> controlled by the sensor controller <NUM>. The constant current circuit <NUM> may be configured to be effective as switched capacitor current source supplying at least temporarily a constant current to the data signal line VSL.

The amplifier transistor <NUM> of the pixel circuit <NUM> and the constant current circuit <NUM> complement to a source follower circuit passing a pixel output signal Vout derived from the floating diffusion potential Vfd to the column signal processing unit <NUM> and the ADCs <NUM>. The ADCs <NUM> transform the received pixel output signals Vout into digital pixel data DPXS and pass the digital pixel data DPXS to the signal processing unit <NUM>.

<FIG> refers to details of an image sensor array <NUM> according to the present disclosure.

The image sensor array <NUM> includes a pixel circuit <NUM> that generates a pixel output signal Vout with an amplitude related to an intensity of detected light and passes the pixel output signal Vout to a data signal line VSL for a selection period. A current control capacitor <NUM> supplies a current to the data signal line VSL through a first electrode in the selection period. A ramp generator <NUM> generates a voltage ramp signal Vrmp and passes the voltage ramp signal Vrmp to a second electrode of the current control capacitor <NUM> in the selection period.

In particular, the pixel circuit <NUM> may include an amplification transistor <NUM> with a load path connected between a positive supply voltage VDD and a pixel output node PON. A floating diffusion region may be connected to a gate of the amplification transistor <NUM>. A floating diffusion potential Vfd may be passed to the gate of the amplification transistor <NUM> and controls the amplification transistor <NUM>.

A selection transistor <NUM> is connected with a load path between the pixel output node PON and the data signal line VSL. A gate of the selection transistor <NUM> receives a selection signal SEL. The selection signal SEL is active ("on") and turns on the selection transistor <NUM> for a selection period. Outside the selection period, the selection signal SEL is inactive ("off") and turns off the selection transistor <NUM>.

The substrate bulk for the amplification transistor <NUM> and the selection transistor <NUM> is connected to a bulk potential BLK. The bulk potential BLK may be connected to a voltage reference potential GND or to a negative potential.

A first electrode of the current control capacitor <NUM> (first control capacitor electrode) is signal-connected to the data pixel circuit <NUM> through the data signal line VSL. The first control capacitor electrode may be directly connected to the pixel circuit <NUM>. Alternatively, further elements or circuits facilitating at least temporary signal transmission such as FETs, switches and/or resistors may be electrically connected between the pixel circuit <NUM> and the first control capacitor electrode and signal-connect the pixel circuit <NUM> with the first control capacitor electrode in at least a part of the selection period.

The ramp generator <NUM> generates a voltage ramp signal Vrmp in response to one or more control signals received from the sensor controller and outputs the voltage ramp signal Vrmp at a ramp generator output Out. The ramp generator output Out is signal-connected to the second electrode of the current control capacitor <NUM> (second control capacitor electrode). The ramp generator output Out and the second control capacitor electrode may be directly connected. Alternatively, further elements or circuits allowing at least temporary signal transmission such as FETs, switches and/or resistors may be connected between the ramp generator output Out and the second control capacitor electrode and connect the ramp generator output Out with the second control capacitor electrode for at least a part of the selection period.

When a first capacitor electrode of a capacitor with a capacitance C is kept at constant voltage level while a voltage ramp with a constant slope ratio Vrmp/Trmp is applied to a second capacitor electrode, the first capacitor electrode supplies a constant current Ic = (Vrmp*C)/Trmp to the circuit connected to the first capacitor electrode.

In particular, during the selection period the amplification transistor <NUM> forces the voltage level of the pixel output signal Vout on the data signal line VSL to a level that is a function of the floating diffusion potential Vfd provided that a current source supplies a constant current to the data signal line VSL. The current control capacitor <NUM> supplies the required constant current to the data signal line VSL through the first control capacitor electrode provided that simultaneously a sufficiently steep voltage ramp is supplied to the second control capacitor electrode.

The constant current circuit <NUM> and in particular the current control capacitor <NUM> and the amplification transistor <NUM> complement each other to a source follower circuit, wherein the current control capacitor <NUM> is effective as the constant current source for the output current.

The time charts in <FIG> show the effect of the constant current circuit <NUM> of <FIG>. The upper time chart (first time chart) shows a time response of the floating diffusion potential Vfd. The second time chart shows the voltage ramp signal Vrmp. The third time chart shows the resulting pixel output signal Vout on the data signal line VSL. The pixel circuit may be continuously selected from t=tx0 to t=tx4.

In general, one pixel readout cycle may include a preset phase P and a data phase D. A voltage level of the pixel output signal Vout at the end of the preset phase P may indicate a current pixel offset voltage obtained as output signal of a pixel circuit with unilluminated photoelectric conversion element PD ("dark pixel"). A voltage level of the pixel output signal Vout at the end of the data phase D is a measure for incident light on the illuminated photoelectric conversion element PD. For CDS (correlated double sampling), the kTC noise may be canceled by subtracting the current pixel offset voltage obtained in the preset phase P from the pixel output signal Vout at the end of the data phase D. A settling time after which the voltage level of the pixel output signals Vout is stable after transitions to the preset phase P and to the data phase D determines the readout speed.

At t=tx0 the floating diffusion region is connected to a constant reset potential. For example, the reset transistor <NUM> shown in <FIG> may connect the floating diffusion region to the high supply voltage VDD. Accordingly, the floating diffusion potential Vfd is equal to a reset potential. The reset potential may be about <NUM>.

Prior to tx0, at t=tx0, or shortly later the voltage ramp signal Vrmp supplied to the second control capacitor electrode starts to drop at constant rate. The slope ratio of the voltage ramp is equal to 1V/µs and the capacitance C of the current control capacitor <NUM> in <FIG> is 5pF such that the current control capacitor <NUM> supplies a constant current of 5µA to the data signal line VSL.

At t=tx1, after a settling time of 200ns to 300ns, the pixel output signal Vout reaches a constant voltage level that depends on the reset potential of the floating diffusion region.

At t=tx2 the floating diffusion region is disconnected from the constant reset potential and connected to the photoelectric conversion element of the pixel circuit. The floating diffusion potential Vfd adapts according to the intensity of radiation detected by the photoelectric conversion element and reaches the corresponding final constant voltage level at t=tx3. The different floating diffusion potentials Vfd1,. , Vfd10 correspond to different illumination conditions, wherein the intensity of detected radiation increases from Vfd1 to Vfd10 and wherein Vfd1 is the floating diffusion potential of an unexposed pixel (dark pixel) and Vfd10 is the floating diffusion potential of a fully exposed pixel.

From t=tx0 to t=tx4 the constant current circuit <NUM> steadily supplies a constant current of 5µA such that the pixel output signal Vout follows the floating diffusion potential Vfd accordingly and reaches constant voltage levels for the different illumination conditions at t=tx3.

The lower limit of the output voltage swing for the pixel output signal Vout (pixel output voltage swing) is given by the bulk potential BLK to which the substrate bulks of the amplification transistor <NUM> and the selection transistor <NUM> are connected. In case the bulk potential BLK corresponds to the voltage reference potential GND (0V), the lower limit of the pixel output voltage swing is equal to 0V.

In comparison with a conventional constant current source based on an nFET with constant gate bias, the constant current circuit <NUM> of <FIG> provides a capacitor current source that increases the voltage swing of the pixel output voltage Vout by 300mV to 400mV, in other words, by about <NUM>%. The increased pixel output voltage swing in turn facilitates a higher voltage swing for the floating diffusion potential Vfd and eventually a higher dynamic range. The pixel output voltage swing may be further increased by supplying a negative potential as bulk potential BLK.

Further in comparison with a conventional constant current source based on an nFET with constant gate bias, the capacitor current source eliminates the <NUM>/f and RTS (random telegraph signal) noise inherently introduced by the operation of FETs.

<FIG> shows a capacitance control circuit <NUM> connected between the data signal line VSL and the current control capacitor <NUM>. The capacitance control circuit <NUM> includes an n channel common gate transistor for reducing a capacitive load effective for the pixel output signal Vout.

In particular, if the capacitance Cramp of the current control capacitor <NUM> is large compared to the capacitance of the data signal line VSL, the capacitance control circuit <NUM> may be efficient to reduce the settling time, i.e. the time elapsed until the pixel output signal Vout reaches a specified error band around the final voltage level after a voltage transition. The capacitance control circuit <NUM> may include any circuit that reduces the capacitive load on the data signal line VSL.

For example, the capacitance control circuit <NUM> may include at least one FET <NUM>, wherein a load path of the FET <NUM> is connected between the pixel circuit <NUM> and the first electrode of the current control capacitor <NUM>.

In the illustrated embodiment, the capacitance control circuit <NUM> includes one nFET <NUM> with constant gate bias Vbias.

<FIG> shows a pre-charge circuit <NUM> that pre-charges the data signal line VSL in a pre-charge period outside the selection period.

The data signal line VSL may be pre-charged to a constant voltage lower than the positive supply voltage VDD, for example to the voltage reference potential GND. The pre-charge circuit <NUM> may be active in pre-charge periods prior to settling phases, e.g. prior to each selection period. The pre-charge circuit <NUM> is inactive for the selection periods.

By pre-charging the data signal line VSL with the voltage reference potential GND, the settling of the pixel output signal Vout concerns a transition from a low voltage to a high voltage. The transition from the low voltage to the high voltage is governed by the source follower configuration including the amplification transistor such that the output load is driven by the comparatively high source follower current. Otherwise, if the data signal line VSL is pre-charged with high potential, the settling of the pixel output signal Vout concerns transitions form a high voltage to a low voltage, wherein the output load is driven by the comparatively low current supplied by the constant current circuit <NUM>.

Therefore, in particular if the capacitance Cramp of the current control capacitor <NUM> is small compared to the capacitance of the data signal line VSL, by pre-charging the data signal line VSL prior to the preset phase P and prior to the data phase D with the voltage reference potential GND, the pre-charge circuit <NUM> may efficiently reduce, for a given constant current supplied by the current control capacitor <NUM> ,the settling time, i.e. the time elapsed until the pixel output signal Vout reaches a specified error band around the final voltage level after a voltage transition.

The pre-charge circuit <NUM> may include a first switching element <NUM> that passes the voltage reference potential GND to the data signal line VSL in the pre-charge period. A pre-charge control signal SEL_B may control the first switching element <NUM>.

The pre-charge circuit <NUM> may be configured to start each pre-charge period with end of a preceding selection period and to end each pre-charge period with start of a following selection period.

The selection periods at the data signal line VSL may concern different pixel circuits which are assigned to the same data signal line VSL and selected with different select signals.

The time charts in <FIG> illustrate the effect of the pre-charge circuit <NUM> of <FIG>. The upper time chart (first time chart) shows a time response of the floating diffusion potential Vfd. The second time chart shows a time response of the selection signal SEL. The third time chart shows a time response of the pre-charge signal SEL_B. For simplicity, one single pixel circuit per data signal line is considered in this example, wherein the pre-charge control signal SEL_B may be approximated by the inverted selection signal SEL. The fourth time chart shows the voltage ramp signal Vrmp. The fifth time chart shows the resulting pixel output signal Vout on the data signal line VSL.

Active periods of the selection signal SEL define selection periods. A first selection period defines a preset phase P between t=tr0 and t=tr1. A second selection period defines a data phase D between t=td0 and t=td1.

In the preset phase P, the floating diffusion region is connected to a constant reset potential, e.g., to the high supply voltage VDD. Starting with begin of the preset phase P, the voltage ramp signal Vrmp drops at constant rate. The slope ratio of the voltage ramp may be set such that within the preset phase P the voltage ramp signal drops form a maximum ramp voltage Vrmax to a minimum ramp voltage Vrmin. At t=tx the pixel output signal Vout reaches a constant voltage level that depends on the reset potential of the floating diffusion region. The slope ratio of the voltage ramp is equal to 3V/µs and the capacitance C of the current control capacitor <NUM> in <FIG> is 1pF such that the current control capacitor <NUM> supplies a constant current of 3µA.

At t=tr1 the preset phase P ends. The selection signal SEL becomes inactive and disconnects the pixel circuit <NUM> from the data signal line VSL. The pre-charge control signal SEL_B turns on the first switching element <NUM> and connects the data signal line VSL to the voltage reference potential GND, wherein the data signal line VSL is pre-charged with the voltage reference potential GND. At t=ty the ramp voltage signal Vrmp returns to the maximum ramp voltage Vrmax.

Starting with t=tx2 floating diffusion potential Vfd adapts according to the intensity of radiation detected by the photoelectric conversion element and reaches the corresponding final constant level at t=tx3. Different floating diffusion potentials Vfd1,. , Vfd11 result from different illumination conditions, wherein the intensity of detected radiation increases from Vfd1 to Vfd11.

Starting with begin of the data phase D at t=td0, the voltage ramp signal Vrmp again drops at the same rate as in the preset phase P.

During both the preset phase P and the data phase D the constant current circuit <NUM> steadily supplies a constant current of 3µA such that the pixel output signal Vout follows the floating diffusion potential Vfd accordingly and reaches constant voltage levels for the different illumination conditions at t=tx3.

<FIG> shows a part of an image sensor array <NUM> including a capacitor control circuit <NUM> that decouples the second electrode of the current control capacitor <NUM> from an output of the ramp generator <NUM> in an initial phase at a start of the selection period and/or in a tail phase at an end of the selection period.

The initial phase may start shorty prior to, simultaneously with of shortly after the start of the selection period and ends within the selection period, e.g. within the first quarter of the selection period. The trail phase may start shortly prior to, simultaneously with of shortly after the end of the selection period and ends before the next selection period.

The capacitor control circuit <NUM> may reduce or eliminate detrimental interaction between components of the constant current circuit <NUM> and other circuits connected to the data signal line VSL. For example, the capacitor control circuit <NUM> may be adapted to reduce effects caused by turning on and/or off the selection transistor <NUM> on the ramp generator <NUM>.

In particular, the capacitor control circuit <NUM> may include a second switching element <NUM> configured to disconnect the second electrode of the current control capacitor <NUM> from the output Out of the ramp generator <NUM> for the initial phase of the selection period and/or for the tail phase. A first ramp control signal RMP_CUT may control the second switching element <NUM>.

In particular, the first ramp control signal RMP_CUT may be active during the switching transitions of the selection transistor <NUM> such that the output Out of the ramp generator <NUM> is disconnected from the current control capacitor <NUM> during the switching transitions and current spikes on the ramp generator <NUM> can be reduced. In particular, the ramp generator can be protected from receiving current spikes, in particular from current spikes with transition currents higher than the maximum ramp generator output current.

The second switching element <NUM> may be an FET with a load path connected between the output Out of the ramp generator <NUM> and the second electrode of the current control capacitor <NUM>. The first ramp control signal RMP_CUT may be passed to the gate of the FET.

The capacitor control circuit <NUM> may include a third switching element <NUM> that passes a first constant voltage to the second electrode of the current control capacitor <NUM> in the initial phase of the selection period. The third switching <NUM> element pushes the second electrode of the current control capacitor <NUM> to an appropriate constant potential for the time the current control capacitor <NUM> is disconnected from the ramp generator <NUM>. The first constant voltage may be a high potential, e.g. the positive supply voltage VDD.

A second ramp control signal RMP_PU controls the third switching element <NUM>. The third switching element <NUM> may be an FET with a load path connected between the positive supply voltage VDD and the second electrode of the current control capacitor <NUM>. The second ramp control signal RMP_PU may be passed to the gate of the FET.

The capacitor control circuit <NUM> may include a fourth switching element <NUM> configured to pass a second constant voltage to the second electrode of the current control capacitor <NUM> in the trail phase at the end of the selection period. The fourth switching element <NUM> element pulls the second electrode of the current control capacitor <NUM> to an appropriate constant potential for the time the current control capacitor <NUM> is disconnected from the ramp generator <NUM>. The second constant voltage may be a low potential, e.g. the voltage reference potential GND.

A third ramp control signal RMP_PD controls the fourth switching element <NUM>. The fourth switching element <NUM> may be an FET with a load path connected between the voltage reference potential GND and the second electrode of the current control capacitor <NUM>. The third ramp control signal RMP_PD may be passed to the gate of the FET.

<FIG> shows the time charts for a voltage ramp signal Vrmp, the selection signal SEL and the pre-charge control signal SEL_B as described with reference to <FIG>, and for the first ramp control signal RMP_CUT, the second ramp control signal RMP_PU, and the third ramp control signal RMP_PD.

The first ramp control signal RMP_CUT is inactive and switches off the second switching element <NUM> for initial phases Tinit and for trail phases Ttrail. The initial phases Tinit start at t=ti0 prior to begin of the selection periods P, D at t=tr0 and t=td0 and end at t=ti1 shortly after begin of the selection periods P, D. The trail phases Ttrail start at t=tt0 prior to the end of the selection periods P, D at t=tr1 and t=td1 and end at t=tt1 after the end of the selection periods P, D and prior to the next selection period. Outside the initial phases Tinit and the trail phases Ttrail, the first ramp control signal RMP_CUT is active and the second switching element <NUM> is on.

The second ramp control signal RMP_PU is active and switches on the third switching element <NUM> for pull-up phases Tpu. Each pull-up phase Tpu starts at t=tu0 with or after begin of an initial phase Tinit and ends at t=tu1 shortly prior to or with the end of the initial phase Tinit. Outside the pull-up phases Tpu, the second ramp control signal RMP_PU is inactive and the third switching element <NUM> is off.

The third ramp control signal RMP_PD is active and switches on the fourth switching element <NUM> for pull-down phases Tpd. Each pull-down phase Tpd starts at t=tp0 with or after begin of a trail phase Ttrail and ends at t=tp1 shortly prior to or with the end of the trail phase Ttrail. Outside the pull-down phases Tpd, the fourth ramp control signal RMP_PD is inactive and the fourth switching element <NUM> is off.

The ramp generator <NUM> may be any circuit that creates or approximates a linear rising or falling voltage with respect to time. For example, the ramp generator <NUM> may include an analog ramp generator like a bootstrap ramp generator using an operational amplifier in a voltage follower configuration. According to another example, the ramp generator includes a DAC (digital-to-analog converter stage) generating a stair step voltage ramp.

<FIG> shows a ramp generator <NUM> that includes a DAC stage <NUM> with a plurality of switchable current supply cells <NUM>-<NUM>,. , <NUM>-n connected in parallel and an output resistor <NUM>. Each current supply cell <NUM>-<NUM>,. , <NUM>-n includes a cell current source <NUM>-<NUM>,. , <NUM>-n and a primary switching element <NUM>-<NUM>,. , <NUM>-n connected in series. The output resistor <NUM> is connected in series between the parallel connected current supply cells <NUM>-<NUM>,. , <NUM>-n and a first constant voltage V1. The parallel connected current supply cells <NUM>-<NUM>,. , <NUM>-n are connected in series between a second constant voltage V2 and the output resistor <NUM>.

When the primary switching element <NUM>-x of a switchable current supply cell <NUM>-x is on, the respective cell current source <NUM>-x induces a current flow between the first constant voltage V1 and the second constant voltage V2 through the output resistor <NUM>.

The current supply cells <NUM>-<NUM>,. , <NUM>-n may include FETs with constant gate bias, may be essentially identical and may supply the same current. The primary switching elements <NUM>-<NUM>,. , <NUM>-n may be FETs. Switch control signals Sw1,. , Swn control the primary switching elements <NUM>-<NUM>,. , <NUM>-n and turn on selected ones. The switch control signals Sw1,. , Swn control the current supply cells <NUM>-<NUM>,. , <NUM>-n in a way that the sum current through the output resistor <NUM> continuously increases or decreases with time in steps at a step height corresponding to the voltage drop one single of the cell current sources <NUM>-<NUM>,. , <NUM>-n generates at the output resistor <NUM>.

In the DAC stage <NUM> illustrated in <FIG> each switchable current cell <NUM>-<NUM>,. , <NUM>-n further includes a secondary switching element <NUM>-<NUM>,. , <NUM>-n connected in series between the cell current source <NUM>-<NUM>,. , <NUM>-n and the first constant voltage V1. The inverted switch control signals Sw<NUM>,. , Swn control the secondary switching elements <NUM>-<NUM>,. , <NUM>-n and turn on selected ones such that during operation each cell current source <NUM>-<NUM>,. , <NUM>-n supplies the same current at any time and the total current consumption remains constant.

The illustrated DAC stage <NUM> refers to a ground-based type DAC stage, wherein the first constant voltage V1 is equal to the voltage reference potential GND and the second constant voltage V2 is equal to the positive supply voltage VDD. According to a DAC stage of the supply-based type, the switchable current cells <NUM>-<NUM>,. , <NUM>-n may be connected to the voltage reference potential GND and the output resistor <NUM> may be connected to the positive supply voltage VDD.

<FIG> shows a ramp generator <NUM> that includes a counter <NUM> controlling the switchable current supply cells <NUM>-<NUM>,. , <NUM>-n of any of the DAC stages <NUM> in <FIG>. The counter <NUM> may be a binary counter, increasing a digital count value with each rising or trailing edge of a clock signal and outputting the current digital count value in parallel at data outputs D0,. , Dn-<NUM>. The data outputs D0,. , Dn-<NUM> supply the switch control signals Sw1,.

<FIG> shows a portion of a solid-state imaging device <NUM>. The solid-state imaging device <NUM> includes a plurality of pixel circuits <NUM>, wherein each pixel circuit <NUM> is configured to generate a pixel output signal with an amplitude related to an intensity of detected light, and wherein each pixel circuit <NUM> is assigned to one of a plurality of pixel columns <NUM>.

The solid-state imaging device <NUM> further includes a plurality of data signal lines VSL-<NUM>,. , VSL-m, wherein each data signal line VSL-<NUM>,. , VSL-m is configured to receive the pixel output signals of a plurality of pixel circuits <NUM> assigned to a same pixel column <NUM>, and wherein to each data signal line VSL-<NUM>,. , VSL-m a selected pixel circuit <NUM> passes the pixel output signal Vout for a selection period;.

The solid-state imaging device <NUM> further includes a plurality of current control capacitor s <NUM>-<NUM>,. , <NUM>-m, wherein each current control capacitor <NUM>-<NUM>,. , <NUM>-m is configured to supply a current to one of the data signal lines VSL-<NUM>,. , VSL-m through a first electrode in the selection periods.

A ramp generator <NUM> generates a voltage ramp signal and passes the voltage ramp signal to second electrodes of the current control capacitors <NUM>-<NUM>,. , <NUM>-m in the selection periods.

A row selection signal SEL_1, SEL_2,. , simultaneously selects the pixel circuits <NUM> of the same pixel row, wherein in each pixel column <NUM> the pixel circuit <NUM> assigned to the selected pixel row is selected.

Pre-charge circuits <NUM>-<NUM>,. , <NUM>-m pre-charge the data signal lines VSL-<NUM>,. , VSL-m in pre-charge periods outside the selection periods defined by the active row selection signals SEL_1, SEL_2,. For example, a pre-charge signal SEL_B controlling the pre-charge circuits <NUM>-<NUM>,. , <NUM>-m may be or may approximate the inverted of the ORed row selection signals SEL_1, SEL_2,.

A capacitor control circuit <NUM> may decouple the second electrodes of the current control capacitors <NUM>-<NUM>,. , <NUM>-m from an output of the ramp generator <NUM> in initial phases at start of the selection periods and/or in tail phases at end of the row selection periods as described with reference to <FIG> and <FIG>.

<FIG> refers to a pixel circuit <NUM> including an intensity readout circuit <NUM>-I and a photoreceptor module PR for event detection, wherein the intensity readout circuit <NUM>-<NUM> and the photoreceptor module PR share a common photoelectric conversion element PD. The photoreceptor module PR includes a photoreceptor circuit PRC that converts the photocurrent Iphoto into a photoreceptor signal Vpr, wherein a voltage of the photoreceptor signal Vpr is a function of the photo current Iphoto, and wherein in the range of interest the voltage of the photoreceptor signal Vpr increases with increasing photocurrent Iphoto. The photoreceptor circuit PRC may include a logarithmic amplifier. An event detector circuit <NUM> receives the photoreceptor signal Vpr and generates an event detection signal Ev when a change of the voltage level of the photoreceptor signal Vpr exceeds a predetermined threshold.

The intensity readout circuit <NUM>-<NUM> includes an n-channel anti-blooming transistor <NUM> and an n-channel decoupling transistor <NUM> which are electrically connected in series between the high supply voltage VDD and the photoelectric conversion element PD. The anti-blooming transistor <NUM> and the decoupling transistor <NUM> may be controlled by fixed bias voltages Vb2, Vb1 applied to the gates. Additional elements, e.g. a controlled path of a feedback portion of the photoreceptor circuit PRC may be electrically connected in series between the decoupling transistor <NUM> and the photoelectric conversion element PD.

Decoupling transistor <NUM> may basically decouple the photoreceptor circuit PRC from voltage transients at the center node between the decoupling transistor <NUM> and the anti-blooming transistor <NUM>. The anti-blooming transistor <NUM> may ensure that the voltage at the center node between the decoupling transistor <NUM> and the anti-blooming transistor <NUM> does not fall below a certain level given by the difference between the bias voltage Vb2 at the gate of the anti-blooming transistor <NUM> and the threshold voltage of the anti-blooming transistor <NUM> in order to ensure proper operation of the photoreceptor circuit PRC.

The source of the n-channel transfer transistor <NUM> is electrically connected to the center node between the decoupling transistor <NUM> and the anti-blooming transistor <NUM>. For the further components of the intensity readout circuit <NUM>-<NUM>, reference is made to the description of the pixel circuit <NUM> in <FIG>.

Alternative embodiments of the intensity readout circuit <NUM>-<NUM> may be realized without transfer transistor <NUM>, wherein the reset transistor <NUM> may replace the anti-blooming transistor <NUM>, and wherein the source of the reset transistor <NUM> is directly connected to the gate of the amplifier transistor <NUM>.

In the photoreceptor circuit block of <FIG>, the intensity detection circuit <NUM>-<NUM> and the photoreceptor circuit PRC for event detection are electrically connected in series with respect to the photocurrent Iphoto, wherein evaluation of intensity and detection of events may be performed substantially contemporaneously.

The pixel circuit <NUM> in <FIG> includes a first mode selector <NUM> and a second mode selector <NUM>. The first mode selector <NUM> is connected between the cathode of the photoelectric conversion element PD and a photoreceptor circuit PRC. The second mode selector <NUM> is connected between the cathode of the photoelectric conversion element PD and the amplifier transistor <NUM> of an intensity readout circuit <NUM>-<NUM>. A first mode selector signal TEV controls the first mode selector <NUM>. A second mode selector signal TINT controls the second mode selector <NUM>.

The first and second mode selectors <NUM>, <NUM> electrically connect the photoelectric conversion element PD with the photoreceptor circuit PRC in a first operating state and with the intensity readout circuit <NUM>-<NUM> in a second operating state. In addition, the first and second mode selectors <NUM>, <NUM> may disconnect the photoelectric conversion element PD from the intensity readout circuit <NUM>-<NUM> in the first operating state and may disconnect the photoelectric conversion element PD from the photoreceptor circuit PRC in the second operating state. The first and second mode selectors <NUM>, <NUM> may be electronic switches, for example FETs or transfer gates.

<FIG> is a perspective view showing an example of a laminated structure of a solid-state imaging device <NUM> with a plurality of pixels arranged matrix-like in array form. Each pixel includes at least one photoelectric conversion element.

The solid-state imaging device <NUM> has the laminated structure of a first chip (upper chip) <NUM> and a second chip (lower chip) <NUM>.

The laminated first and second chips <NUM>, <NUM> may be electrically connected to each other through TC(S)Vs (Through Contact (Silicon) Vias) formed in the first chip <NUM>.

The solid-state imaging device <NUM> may be formed to have the laminated structure in such a manner that the first and second chips <NUM> and <NUM> are bonded together at wafer level and cut out by dicing.

In the laminated structure of the upper and lower two chips, the first chip <NUM> may be an analog chip (sensor chip) including at least one analog component of each pixel circuit, e.g., the photoelectric conversion elements arranged in array form.

For example, the first chip <NUM> may include only the photoelectric conversion elements of the pixel circuits as described above with reference to the preceding FIGS. Alternatively, the first chip <NUM> may include further elements of each pixel circuit. For example, the first chip <NUM> may include, in addition to the photoelectric conversion elements, at least the transfer transistor, the reset transistor, the amplification transistor, and/or the selection transistor of the pixel circuits. Alternatively, the first chip <NUM> may include each element of the pixel circuit. Alternatively, the first chip <NUM> may include each element of the pixel circuit and the capacitor control circuit <NUM> of <FIG>.

The second chip <NUM> may be mainly a logic chip (digital chip) that includes the elements complementing the elements on the first chip <NUM> to complete pixel circuits and current control circuits. The second chip <NUM> may also include analog circuits, for example circuits that quantize analog signals transferred from the first chip <NUM> through the TCVs.

The second chip <NUM> may have one or more bonding pads BPD and the first chip <NUM> may have openings OPN for use in wire-bonding to the second chip <NUM>.

The solid-state imaging device <NUM> with the laminated structure of the two chips <NUM>, <NUM> may have the following characteristic configuration:
The electrical connection between the first chip <NUM> and the second chip <NUM> is performed through, for example, the TCVs. The TCVs may be arranged at chip ends or between a pad region and a circuit region. The TCVs for transmitting control signals and supplying power may be mainly concentrated at, for example, the four corners of the solid-state imaging device <NUM>, by which a signal wiring area of the first chip <NUM> can be reduced.

<FIG> shows a possible allocation of elements of a solid-stage imaging device across the first chip <NUM> and the second chip <NUM> of <FIG>.

The first chip <NUM> may include the pixel circuits <NUM> with photoelectric conversion elements. The second chip <NUM> may include inter alia the column signal processing unit <NUM> with the constant current circuit <NUM>. One through contact via <NUM> per pixel circuit <NUM> may be part of the data signal line VSL and passes the pixel output signal Vout from the first chip <NUM> to the second chip <NUM>.

In addition, a capacitance control circuit <NUM> connected between the data signal line VSL and the current control capacitor <NUM> to reduce a capacitive load effective for the pixel output signal Vout may be formed on the first chip <NUM>.

The pre-charge circuit <NUM> may include an n channel FET as first switching element <NUM> that passes the voltage reference potential GND or another low voltage to the data signal line VSL in the pre-charge periods.

The substrate bulk of the transistors of the pixel circuits <NUM> and the capacitance control circuit <NUM> may be connected. A further through contact via <NUM> may pass a bulk potential BLK from the second chip <NUM> to the first chip <NUM>. The n channel FET of the pre-charge circuit <NUM> may be realized on the second chip <NUM> as illustrated, or on the first chip <NUM>. In both cases, the substrate bulk of the n channel FET of the pre-charge circuit <NUM> may be connected to the bulk potential BLK, The source of the n channel FET of the pre-charge circuit <NUM> may be connected to the voltage reference potential GND as illustrated or to the bulk potential BLK.

The bulk potential BLK may be more negative than the voltage reference potential GND to further expand the voltage swing of the pixel output signal Vout.

The vehicle control system <NUM> includes a plurality of electronic control units connected to each other via a communication network <NUM>. In the example depicted in <FIG>, the vehicle control system <NUM> includes a driving system control unit <NUM>, a body system control unit <NUM>, an outside-vehicle information detecting unit <NUM>, an in-vehicle information detecting unit <NUM>, and an integrated control unit <NUM>. In addition, a microcomputer <NUM>, a sound/image output section <NUM>, and a vehicle-mounted network interface <NUM> are illustrated as a functional configuration of the integrated control unit <NUM>.

The outside-vehicle information detecting unit <NUM> detects information about the outside of the vehicle including the vehicle control system <NUM>. For example, the outside-vehicle information detecting unit <NUM> is connected with an imaging section <NUM>. The outside-vehicle information detecting unit <NUM> makes the imaging section <NUM> imaging an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit <NUM> may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section <NUM> may be or may include an image sensor assembly or a solid-state imaging device with a constant current circuit including a current control capacitor and a ramp generator according to the embodiments of the present disclosure. The light received by the imaging section <NUM> may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit <NUM> detects information about the inside of the vehicle and may be or may include an image sensor assembly or a solid-state imaging device with a constant current circuit including a current control capacitor and a ramp generator according to the embodiments of the present disclosure. The driver state detecting section <NUM>, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver.

In addition, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit <NUM>.

The sound/image output section <NUM> transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of <FIG>, an audio speaker <NUM>, a display section <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display section <NUM> may, for example, include at least one of an on-board display or a head-up display.

<FIG> is a diagram depicting an example of the installation position of the imaging section <NUM>, wherein the imaging section <NUM> may include imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>.

The imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle <NUM> as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section <NUM> provided to the front nose and the imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle <NUM>. The imaging sections <NUM> and <NUM> provided to the side view mirrors obtain mainly an image of the sides of the vehicle <NUM>. The imaging section <NUM> provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle <NUM>. The imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, <FIG> depicts an example of photographing ranges of the imaging sections <NUM> to <NUM>. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the front nose. Imaging ranges <NUM> and <NUM> respectively represent the imaging ranges of the imaging sections <NUM> and <NUM> provided to the side view mirrors. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the rear bumper or the back door. A bird's-eye image of the vehicle <NUM> as viewed from above is obtained by superimposing image data imaged by the imaging sections <NUM> to <NUM>, for example.

At least one of the imaging sections <NUM> to <NUM> may have a function of obtaining distance information. For example, at least one of the imaging sections <NUM> to <NUM> may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor assembly or a solid-state imaging device with a constant current circuit including a current control capacitor and a ramp generator according to the embodiments of the present disclosure.

For example, the microcomputer <NUM> can determine a distance to each three-dimensional object within the imaging ranges <NUM> to <NUM> and a temporal change in the distance (relative speed with respect to the vehicle <NUM> on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle <NUM> and which travels in substantially the same direction as the vehicle <NUM> at a predetermined speed (for example, equal to or more than <NUM>/hour). Further, the microcomputer <NUM> can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying the an image sensor assembly or a solid-state imaging device with a constant current circuit including a current control capacitor and a ramp generator according to the embodiments of the present disclosure, the sensors can be provided with higher dynamic range and better signal-to-noise ratio.

Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the claims.

The solid-state imaging device according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, the solid-state imaging device may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

Specifically, in the field of image reproduction, the solid-state imaging device may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, the solid-state imaging device may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

In the field of home appliances, the solid-state imaging device may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly the solid-state imaging device may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device may be integrated in any type of sensor, e.g. a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

Claim 1:
An image sensor array, comprising:
a pixel circuit (<NUM>) configured to generate a pixel output signal with an amplitude related to an intensity of detected light and to pass the pixel output signal to a data signal line (VSL) for a selection period;
a current control capacitor (<NUM>) configured to supply a current to the data signal line (VSL) through a first electrode in the selection period; and
a ramp generator (<NUM>) configured to generate a voltage ramp signal and to pass the voltage ramp signal to a second electrode of the current control capacitor (<NUM>) in the selection period.