Patent Description:
Some sensors, particularly those sensors used to sense characteristics of biological fluids, i.e., biosensors, typically are made using ion-sensitive transistors. These ion-sensitive transistors, for example Darlington pair transistors, provide sensing (e.g., at a base of one of the transistors in the Darlington pair) and amplification. Amplification is required to integrate the sensor with other circuitry (e.g., read out and control circuitry) because generally biosensor signals are very weak.

Monolithic integration of these sensors/biosensors with circuitry such as readout / control circuitry is crucially important for energy-efficient, high-performance, and mass-deployable systems. In particular, amplification circuitry needs to be monolithically integrated in close proximity of a sensor/biosensor for efficient amplification of weak signals. Further, keeping the sensors close to the amplification circuitry eliminates accumulation and build-up of noise that occurs when the sensors are separated from amplification circuitry over longer distances.

These sensors/biosensors are used in highly integrated sensing/biosensing systems including those systems that have uses for artificial intelligence (Al), healthcare monitoring, point-of-care diagnostics, internet of things (IoT), and wearable devices. Some biosensing applications include mobile (portable and wearable) sensing technologies that can non-invasively monitor health using bio-fluids such as sweat, saliva, and urine. These biosensors have the potential to provide cost effective and enhanced healthcare, particularly in the treatment of chronic diseases. It is desirable that these biosensor technologies provide mobile and on-line monitoring of patients to make delivery of health care more efficient and cost effective.

<CIT> discloses a bipolar junction transistor (BJT) containing sensor that includes a vertically oriented stack of an emitter overlying a supporting substrate, a base region present directly atop the emitter and a collector atop the base region.

A first extrinsic base region is in contact with a first sidewall of a vertically orientated base region. The first extrinsic base region is electrically contacted to provide the bias current of the bipolar junction transistor during sensor operation. A second extrinsic base region in contact with a second sidewall of the base region, the second extrinsic base region including a sensing element. The device may further include a sample trench having a trench sidewall provided by the sensing element.

There is a need to provide sensors, particularly biosensors, that are accurate, sensitive, small, and mobile with reduced noise and high signal amplification that easily can be integrated with semiconductor circuitry and inexpensively mass produced by standard semiconductor processes.

A Darlington pair sensor is disclosed. The Darlington pair sensor according to the present invention is defined in claim <NUM>. The Darlington pair sensor has an amplifying/horizontal bipolar junction transistor (BJT) and a sensing/vertical BJT.

The amplifying bipolar junction transistor (BJT) is horizontally disposed on a substrate. The amplifying BJT has a horizontal emitter, a horizontal base, a horizontal collector, and a common extrinsic base/collector. The common extrinsic base/collector is an extrinsic base for the amplifying BJT. The common extrinsic base/collector is in contact with and vertically above (disposed on) the horizontal base.

The sensing BJT has a vertical orientation with respect to the amplifying BJT. The sensing BJT has a vertical emitter, a vertical base, an extrinsic vertical base, and the common extrinsic base/collector (in common with the amplifying BJT) acting as the sensing BJT collector. The extrinsic vertical base is separated into a left extrinsic vertical base and a right extrinsic vertical base. Therefore, the sensing BJT has two (dual) bases. The left extrinsic vertical base can be a sensing base and the right extrinsic vertical base can be a control base, or visa versa.

The left extrinsic vertical base is in contact with a left side of the vertical base and the right extrinsic vertical base in in contact with a right side of the vertical base. The left extrinsic vertical base and right extrinsic vertical base are physically separated from one another by the vertical base, and electrically coupled with one another via the vertical base.

Alternative configurations and BJT polarities are disclosed along with methods of making the Darlington pair BJT sensor. The Darlington pair BJT sensor can be used as a biosensor.

Various embodiments of the present invention will be described below in more detail, with reference to the accompanying drawings, now briefly described. The Figures show various apparatus, structures, and related method steps of the present invention.

It is to be understood that embodiments of the present invention are not limited to the illustrative methods, apparatus, structures, systems and devices disclosed herein but instead are more broadly applicable to other alternative and broader methods, apparatus, structures, systems and devices that become evident to those skilled in the art given this disclosure and are within the scope of the appended claims.

In addition, it is to be understood that the various layers, structures, and/or regions shown in the accompanying drawings are not drawn to scale, and that one or more layers, structures, and/or regions of a type commonly used may not be explicitly shown in a given drawing. This does not imply that the layers, structures, and/or regions not explicitly shown are omitted from the actual devices.

In addition, certain elements may be left out of a view for the sake of clarity and/or simplicity when explanations are not necessarily focused on such omitted elements. Moreover, the same or similar reference numbers used throughout the drawings are used to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures may not be repeated for each of the drawings.

The semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems implemented with embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, expert and artificial intelligence systems, functional circuitry, neural networks, etc. Systems and hardware incorporating the semiconductor devices and structures are contemplated embodiments of the invention.

As used herein, "height" refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional or elevation views measured from a bottom surface to a top surface of the element, and/or measured with respect to a surface on which the element is located.

Conversely, a "depth" refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional or elevation views measured from a top surface to a bottom surface of the element. Terms such as "thick", "thickness", "thin" or derivatives thereof may be used in place of "height" where indicated.

As used herein, "side," and left or right-side to a side surface or element (e.g., a layer, opening, etc.), such as a left or right-side shown in the drawings.

As used herein, "width" or "length" refers to a size of an element (e.g., a layer, trench, hole, opening, etc.) in the drawings measured from a side surface to an opposite surface of the element. Terms such as "thick", "thickness", "thin" or derivatives thereof may be used in place of "width" or "length" where indicated.

As used herein, terms such as "upper", "lower", "above", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. For example, as used herein, "vertical" refers to a direction perpendicular to the top surface of the substrate in the elevation views, and "horizontal" refers to a direction parallel to the top surface of the substrate in the elevation views.

As used herein, unless otherwise specified, terms such as "on", "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element is present on a second element, wherein intervening elements may be present between the first element and the second element. As used herein, unless otherwise specified, the term "directly" used in connection with the terms "on", "overlying", "atop", "on top", "positioned on" or "positioned atop," "disposed on," or the terms "in contact" or "direct contact" means that a first element and a second element are connected without any intervening elements, such as, for example, intermediary conducting, insulating or semiconductor layers, present between the first element and the second element.

It is understood that these terms might be affected by the orientation of the device described. For example, while the meaning of these descriptions might change if the device was rotated upside down, the descriptions remain valid because they describe relative relationships between features of the invention.

Disclosed is a Darlington pair of bipolar junction transistors (BJT) configured as a dual-base Darlington Pair BJT sensor. The Darlington pair BJT sensor has a first or vertical or sensing BJT transistor and a second or lateral or amplifying BJT transistor in the pair of BJTs.

The first BJT transistor of the Darlington pair BJT is a vertical/sensing BJT with a vertical emitter, a vertical base, and a vertical collector (which also serves as the horizontal extrinsic base of the second, horizontal/lateral BJT transistor). The vertical/sensing BJT has a dual base, comprised of a right extrinsic vertical base and left extrinsic vertical extrinsic base. The vertical BJT is also referred to as the sensor/sensing transistor or dual base BJT, without loss of generality.

The left extrinsic vertical base and right extrinsic vertical base are physically separated from one another by the vertical base, and electrically coupled with one another via the vertical base. The left extrinsic vertical base is in contact with a left side of the vertical base and the right extrinsic vertical base in in contact with a right side of the vertical base.

The second part/transistor part of the Darlington pair BJT sensor is a horizontal BJT with a horizontal emitter, a horizontal collector, and a horizontal base. The horizontal BJT also has and uses the horizontal extrinsic base that is in contact with and vertically above the horizontal base. The horizontal extrinsic base is in common with and identical to the vertical collector of the vertical BJT, i.e., they are one in the same element. The horizontal BJT is also referred to as the lateral BJT, integrated BJT, or amplifying BJT, without loss of generality.

The vertical/dual base/sensing BJT has an inherent gain, associated with a BJT. The disclosed Darlington pair BJT sensor boosts this gain "in-situ" (without having to transfer the signal acquired by the sensing BJT to an external amplifier circuit). In some embodiments, the effective gain of the Darlington pair BJT is the product of dual-base sensing (vertical) BJT gain and the horizontal/lateral/integrated BJT gain. Since the horizontal extrinsic base of the lateral BJT is the same element as the vertical collector of the vertical BJT, there is essentially no connection distance between the collector of the vertical/sensing BJT and the base of the lateral BJT, i.e., any noise introduced over this "in-situ connection" is dramatically reduced.

Since the vertical/dual base/sensing BJT is aligned in a perpendicular direction to the lateral BJT, i.e., the sensor BJT sits in a vertical alignment/direction above the horizontal/lateral BJT, essentially no additional surface of the substrate is needed for the Darlington pair BJT sensor beyond that used by the lateral BJT. Accordingly, the Darlington pair BJT sensor enables dense and area-efficient integration with semiconductor circuitry, using standard semiconductor processing methods.

The invention enables the Darlington pair BJT sensor to be made with a complementary Darlington pair configuration, also known as a Sziklai configuration, where the sensing and lateral BJTs are of different polarities. For example, the complementary Darlington pair BJT sensor as described herein may be comprised of a lateral BJT having an n-p-n polarity and a sensing BJT having a p-n-p polarity (<FIG>, and <FIG>), or may be comprised of a lateral BJT having a p-n-p polarity and a sensing BJT having a n-p-n polarity.

<FIG> is a cross section view of an initial structure <NUM> for a Darlington pair BJT sensor including a semiconductor substrate layer <NUM>, a BOX/isolation layer <NUM>, and a horizontal/lateral BJT base layer <NUM>.

In some embodiments, the substrate/bulk <NUM> is made of one or more semiconductor materials. Non-limiting examples of suitable substrate/bulk <NUM> materials include Si (silicon), strained Si, Ge (germanium), SiGe (silicon germanium), Si alloys, Ge alloys, III-V semiconductor materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), Indium Gallium Arsenide (InGaAs), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof.

In an exemplary embodiment, the substrate <NUM> is silicon.

In some silicon-on-insulator (SOI) embodiments, a BOX layer <NUM> is a buried oxide layer (e.g., SiO2) buried in the substrate (wafer) <NUM> typically at the depth ranging from less than <NUM> nanometers (nm) to several micrometers from the wafer surface <NUM>, depending on application. The thickness of BOX layer <NUM> is typically in the range from about <NUM> nanometers (nm) to about <NUM>.

BOX layers <NUM> and, and alternatively isolation layers <NUM>, prevent electric current leakage between adjacent semiconductor components built upon these layers. BOX layers <NUM> and substrates <NUM> are well known.

Example alternative isolation layers <NUM> include known punch through stopper (PTS) doping layers that are also used to prevent current leakage from active layers built upon the PTS layer.

In one embodiment, an available silicon-germanium on insulator (SGOI) wafer comprised of a SiGe layer <NUM>, carrier substrate <NUM> and BOX layer <NUM> is used. The doping of the SiGe layer may be adjusted by known techniques such as ion-implantation and annealing. In some embodiments, epitaxy with in-situ doping maybe used to increase the thickness of the SiGe layer <NUM> to a desired thickness.

In an embodiment with an NPN lateral BJT, the semiconductor layer <NUM> is a silicon-germanium (SiGe) layer with a p-type doping that forms a p-type SiGe-on-Insulator substrate (SGOI) <NUM>.

Alternatively, an available bulk silicon wafer <NUM> with a PTS layer <NUM> and SiGe layer <NUM> can be used.

These techniques and materials are known.

To form an alternative PNP lateral BJT embodiment, an n-type doping material, e.g., phosphorus (P), arsenic (As) and antimony (Sb), would be used for doping the semiconductor (e.g., SiGe) layer <NUM>.

<FIG> is a cross section view of an initial structure <NUM> with a preliminary extrinsic base/collector layer <NUM> deposited on structure <NUM>.

In some embodiments, the preliminary extrinsic base/collector layer <NUM> is epitaxially grown on the semiconductor layer <NUM>. The thickness of the preliminary extrinsic base/collector layer <NUM> is between <NUM> nanometers (nm) and <NUM>, but thinner or thicker layers may be used as well.

The terms "epitaxially growing and/or depositing" and "epitaxially grown and/or deposited" mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, each semiconductor layer of the epitaxial semiconductor material stack has the same crystalline characteristics as the deposition surface on which it is formed.

Examples of various epitaxial growth process apparatuses that can be employed in the present application include, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition typically ranges from <NUM> to <NUM>. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. In some embodiments, the gas source for the epitaxial growth may include a silicon containing gas source and/or an admixture of a germanium containing gas source. Examples of silicon gas sources include silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. Examples of germanium gas sources include germane, digermane, or combinations thereof. In some embodiments, an epitaxial SiGe alloy can be formed from a source gas that includes a compound containing silicon and germanium. Carrier gases like hydrogen, nitrogen, or helium can be used. For the epitaxial growth of a layer an appropriate dopant type is added to the precursor gas or gas mixture. In some embodiments of channel material layers, no dopant is typically present in, or added into, the precursor gas or gas mixture.

In some embodiments, layers are grown by an integrated epitaxy process. In an integrated epitaxy process the structure is epitaxially grown continuously while the type and/or the concentration of dopants changes at different times and time periods to create the different layers with different dopants and dopant concentrations. Some temperature adjustments may be made for one or more of the layers during the epitaxial growth as well.

For embodiments where the lateral BJT is an NPN BJT, the extrinsic-base layer <NUM> is p-doped. For embodiments where the lateral BJT is an PNP BJT, the extrinsic-base layer <NUM> is n-doped.

Dopants may include, for example, in the epitaxial layer <NUM> a p-type dopant selected from a group of boron (B), gallium (Ga), indium (In), and thallium (TI) and in an alternative extrinsic base layer <NUM> an n-type dopant selected from a group of phosphorus (P), arsenic (As) and antimony (Sb), at various concentrations. For example, in a non-limiting example, a dopant concentration range may be <NUM>×<NUM><NUM>cm-<NUM> to <NUM>×<NUM><NUM>cm-<NUM>, or preferably between <NUM>×<NUM><NUM>cm-<NUM> to <NUM>×<NUM><NUM>cm-<NUM>.

<FIG> is a cross section view showing interim structures <NUM> used to create a common extrinsic base/collector <NUM>.

A hard mask <NUM> is deposited in a pattern on the extrinsic-base layer <NUM> where the common extrinsic base/collector(s) <NUM> is/are to be formed.

The hard mask <NUM> is a protective, dielectric material, e.g., a lithographic protective material. In some embodiments, the hard mask <NUM> materials include but are not limited to any one of the following materials: silicon nitride (SiN), siliconborocarbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and silicon oxynitride (SiON).

In some embodiments, the hard mask <NUM> is made of silicon nitride (SiN) or silicon oxide (SiO2) and is deposited by standard techniques like physical vapor deposition (PVD).

An etching step, selective to the material in horizontal/lateral BJT base layer <NUM>, removes all material in the extrinsic-base layer <NUM> unprotected (not under) the hard mask <NUM>. The remaining material (protected by the hard mask <NUM>) becomes the common extrinsic base/collector <NUM>.

A spacer <NUM> material is then conformally deposited, e.g., by known processes like atomic layer deposition (ALD) around the common extrinsic base/collector <NUM>. A known vertical etch, e.g., a reactive ion etch (RIE), removes the spacer material from the horizontal surfaces leaving the spacers <NUM> on the sides of the common extrinsic base/collector <NUM>.

In some embodiments, the vertical etch is selective to the material making up the hard mask <NUM> and the horizontal/lateral BJT base layer <NUM>.

In some embodiments the resulting width/thickness of the spacers <NUM> is between <NUM> and <NUM>. In alternative embodiments, the spacer <NUM> thickness is about <NUM> to <NUM>.

In some embodiments, the spacers <NUM> are made of materials including: dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride (SiN), SiBCN, SiCN, and SiBN), dielectric oxynitrides, (e.g., SiOCN), SiCO, and SiC, or any combination thereof.

Note that selective etching is an etching process with chemistries and conditions that remove one material and/or layer but not another (not etched material). Alternatively, the non-etched material will be etched by the etching process chemistry but at a much lower etching rate than the removed material. Here the measure of selectivity can be a ratio between the etching rate between two given materials. For example, an etching chemistry "selective to" a material means that the etchant will not remove that material or will remove it a slower rate. Therefore, using an etching chemistry selective to materials making the hard mask <NUM> and spacers <NUM> will remove material in the extrinsic-base layer <NUM> without removing (or minimally removing) materials making the hard mask <NUM> and spacers <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after a masked base etch step creates the horizontal base <NUM>. As described above with respect to <FIG>, a directional etch is perform that is selective to the materials making the BOX/isolation layer <NUM>, hard mask <NUM>, and spacers <NUM>.

The material remaining <NUM> in the semiconductor layer <NUM>, i.e., the material protected by (under the vertical projection of) the hard mask <NUM> and spacers <NUM> becomes the horizontal base <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after an ion implantation <NUM> of the sides <NUM> of the implanted horizontal base <NUM>/<NUM>.

In some embodiments, when the horizontal/lateral BJT is a PNP, i.e., the horizontal/lateral intrinsic base <NUM> is N-type doped, an ion implantation <NUM> embodiment is a hot BF2 implantation. In some embodiments, when the horizontal/lateral BJT is a NPN, i.e., the horizontal/lateral intrinsic base <NUM> is P-type doped, an ion implantation <NUM> embodiment is a hot As or P implantation.

In some lateral NPN BJT embodiments, the ion implantation <NUM> is an angle implantation of a first dopant on the emitter side <NUM>/<NUM> of the horizontal/lateral base <NUM> (or lateral intrinsic base <NUM>) and an angle implantation of a second dopant on the collector side <NUM>/<NUM> of the lateral intrinsic base <NUM>. The second dopant polarity and/or species may be the same as, or different from the first dopant.

The implantation can be either hot or cold, however, hot implantation is preferred. Typically, the implantation is an angled ion implantation. These ion-implantations are known. This ion-implanataion step is optional, and may be omitted in some embodiments.

<FIG> is a cross section view showing interim structures <NUM> after a lateral emitter <NUM> and a lateral collector <NUM> for the horizontal/lateral BJT <NUM>/<NUM>/<NUM>/<NUM> are formed by an epitaxial growth step, as explained above. The lateral emitter <NUM> is on the emitter side <NUM> of the lateral intrinsic base <NUM> and the lateral collector <NUM> is on the collector side <NUM> of the lateral intrinsic base <NUM>. The lateral/horizontal emitter <NUM> and the lateral/horizontal collector <NUM> are physically, chemically, and electrically connected to their respective sides <NUM>/<NUM> of the lateral intrinsic base <NUM> to form the horizontal Bipolar Junction Transistor (BJT) <NUM>/<NUM>/<NUM>/<NUM> of the Darlington pair BJT sensor.

<FIG> is a cross section view showing interim structures <NUM> after filling the interim structure with an interlayer dielectric (ILD) <NUM> and applying a chemical-mechanical polishing (CMP) of the top surface <NUM>.

The ILD <NUM> may be formed from, for example, a low-k dielectric material (with k<<NUM>), including but not limited to, silicon oxide, spin-on-glass, a flowable oxide, a high- density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD <NUM> is deposited by a deposition process, including, but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or like processes.

The CMP is a known process for leveling the top surface <NUM> of the structure <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after a hard mask removal CMP removes the hard mask <NUM> and exposes the common extrinsic base/collector <NUM>. In some embodiments, the hard mask removal CMP stops at the top surface <NUM> of the common extrinsic base/collector <NUM> when removed portions of the common extrinsic base/collector <NUM> materials are detected during the hard mask removal CMP. The hard mask removal CMP creates a flat surface of the structure <NUM> with the top surface <NUM> of the common extrinsic base/collector <NUM> exposed.

<FIG> is a cross section view showing interim structures after formation of a bottom spacer <NUM> on the horizontal (or lateral) BJT <NUM>/<NUM>/<NUM>/<NUM>.

The bottom spacer <NUM> can be made from a low-k dielectric formed according to known processes. The term "low-k dielectric" generally refers to an insulating material having a dielectric constant less than silicon dioxide, e.g., less than <NUM>. Exemplary low-k dielectric materials include, but are not limited to, dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., SiN, SiBCN), dielectric oxynitrides (e.g., SiOCN, SiCO), or any combination thereof or the like. Other non-limiting examples of materials for the bottom spacer <NUM> include dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof.

The bottom spacer <NUM> materials are deposited by a deposition process, for example, CVD or PVD. The bottom spacer <NUM> can have a thickness of about <NUM> to about <NUM>, or of about <NUM> to about <NUM>. Deposition processes allow the thickness of the spacer <NUM> to be precisely controlled.

In some embodiments, the bottom spacer is a dielectric nitride.

<FIG> is a cross section view showing interim structures <NUM> after formation of a sacrificial placeholder material <NUM> on the bottom spacer <NUM>.

The sacrificial placeholder material <NUM> is made of, for example, amorphous silicon (a-Si) or polycrystalline silicon (polysilicon). The sacrificial material <NUM> may be deposited by a deposition process, including, but not limited to, PVD, CVD, plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. The sacrificial material has a thickness of about <NUM> to about <NUM>, or from about <NUM> to about <NUM>. Known deposition techniques enable the thickness of the sacrificial placeholder material <NUM> to be controlled precisely.

In some embodiments, the sacrificial placeholder material <NUM> is amorphous silicon.

<FIG> is a cross section view showing interim structures <NUM> after formation of top spacer <NUM> on the sacrificial placeholder material <NUM> followed by formation/deposition of an oxide layer <NUM> on the top spacer <NUM>.

The top spacer <NUM> is made from the same or similar materials and using the same or similar deposition techniques as used to create the bottom spacer <NUM>.

The oxide layer <NUM> is deposited by known techniques, e.g., CVD or PVD, and is made of materials like siliconborocarbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and silicon oxide.

In some embodiments, the oxide layer <NUM> is made of silicon dioxide and the top spacer <NUM> is made of silicon nitride, SiN.

<FIG> is a cross section view showing interim structures <NUM> after formation of a trench <NUM> by etching through the oxide layer <NUM>, the top spacer <NUM>, and the sacrificial placeholder material <NUM> selective to (stopping at) the bottom spacer <NUM>.

In some embodiments, the trench etching can be performed in steps. For example, a first RIE can etch through the oxide layer <NUM>, top spacer <NUM>, and partially through the sacrificial placeholder material <NUM>. A second RIE can then be used that is selective to the material in the bottom spacer <NUM> to remove the remainder of the sacrificial placeholder material <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after formation of a thin, vertical oxide layer <NUM> on the walls <NUM> of the trench <NUM>. The thin, vertical oxide layer <NUM> is made by oxidation of the sacrificial placeholder material <NUM>.

Exposure to a plasma or any other method of oxidation creates the very thin oxide formation <NUM> on the side walls <NUM> of the sacrificial material <NUM> within the trench <NUM>. The bottom spacer <NUM> protects the common extrinsic base/collector <NUM> from being oxidized by the plasma/oxidation.

<FIG> is a cross section view showing interim structures <NUM> after a selective etch (selective to the common extrinsic base/collector <NUM> material) opens the bottom spacer <NUM> at the base <NUM> of the trench <NUM>, exposing the common extrinsic base/collector <NUM> and enabling the common extrinsic base/collector <NUM> to also become the collector of the vertical/sensing BJT of the Darlington pair BJT sensor.

In some embodiments, the width of the trench is between <NUM> and <NUM>, but wider or narrower trenches may be used as well.

<FIG> is a cross section view showing interim structures after formation of a vertical base region <NUM> in the trench <NUM> that will become the vertical base of the vertical BJT.

The epitaxial growth of base material in the vertical base region <NUM> is lattice matched to common extrinsic base/collector <NUM> material. The vertical base region <NUM> is a semiconductor material that epitaxially grows within the trench <NUM> by known methods described above.

In some embodiments, a strained vertical base is formed by lattice matching the material in the vertical base region <NUM> closely but not exactly to the lattice of the common extrinsic base/collector <NUM> material.

In some embodiments, base material in the vertical base region <NUM> is silicon-germanium doped at a concentration of <NUM><NUM>-<NUM><NUM> cm-<NUM>, with concentrations in the range <NUM><NUM>-<NUM>×<NUM><NUM> cm-<NUM>being more typical. If the vertical/sensing BJT has a PNP polarity, the material in the vertical base region <NUM> is N-doped. If the vertical/sensing BJT has a NPN polarity, the material in the vertical base region <NUM> is P-doped.

<FIG> is a cross section view showing interim structures <NUM> after a polishing (e.g., CMP) the top of the vertical base region <NUM> back to and level with the surface <NUM> of the oxide layer <NUM>. The planarization/CMP removes excess epitaxial growth over the surface <NUM> of the oxide layer <NUM> and forms a vertical base <NUM> of the vertical BJT part of the Darlington pair BJT sensor.

<FIG> is a cross section view showing interim structures <NUM> after deposition of more oxide to cover the surface <NUM> of the previous oxide layer <NUM> to increase the thickness resulting in a thicker oxide layer <NUM>. The thicker oxide layer <NUM> covers the vertical base <NUM> and the surface <NUM> of the structure <NUM>. The thicker oxide layer <NUM> is planarized, e.g., by a CMP.

In some embodiments, the oxide deposited is the same material deposited by the same methods as those of the oxide layer <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after deposition of a base region mask <NUM> on the oxide <NUM>, where a vertical projection of the base region mask overlaps both sides of the horizontal, lateral intrinsic base <NUM>. The base region mask <NUM> is made of materials and deposited using methods described above for masks.

In some embodiments, the base region mask <NUM> is made from silicon nitride (SiN).

<FIG> is a cross section view showing interim structures <NUM> after a vertical etching step (e.g., a RIE) removes the exposed (not covered by the base region mask <NUM>) parts of the oxide layer <NUM>, the exposed parts of top spacer <NUM>, and the exposed parts of the sacrificial material <NUM>. In some embodiments, the vertical etch stops in a time (determined experimentally) to leave some of the sacrificial material <NUM> just covering the bottom spacer <NUM>.

The vertical etching leaves void spaces <NUM> around the vertical base <NUM> and the material <NUM>/<NUM>/<NUM> encompassing the vertical base <NUM>. The etched oxide layer <NUM> is what remains of the oxide layer <NUM> after this vertical etching step.

<FIG> is a cross section view showing interim structures <NUM> after the remaining sacrificial material <NUM> is removed, exposing the vertical oxide layer <NUM> on the sides of the vertical base <NUM>.

In some embodiments, the sacrificial placeholder material <NUM> is amorphous silicon. In some embodiments, this material is removed with a dry etch or exposure to ammonium hydroxide (NH<NUM>OH) at higher than room temperature. In some cases, removal is accomplished using a solution of hydrofluoric acid (HF) or a dry chemical oxide etch.

<FIG> is a cross section view showing interim structures <NUM> after removal <NUM> of the thin, vertical oxide layer <NUM> on sides around the vertical base <NUM>. The removal of the thin, vertical oxide layer <NUM> on sides increases the volume of the void spaces <NUM> above the bottom spacer <NUM>.

In some embodiments, the vertical oxide layer <NUM> is accomplished with exposure to a short HF etch, or by using other known techniques.

<FIG> is a cross section view showing interim structures <NUM> after growth of a doped extrinsic vertical base material <NUM> that surrounds the vertical base <NUM>.

The extrinsic vertical base material <NUM> is a semiconductor material that can epitaxially grow from and surround the vertical base <NUM> while filling the void spaces <NUM>. In some embodiments, the extrinsic vertical base material <NUM> can cover the sides of the top spacer <NUM> and some or all the sides of the etched oxide layer <NUM>.

In some embodiments, the extrinsic vertical base material <NUM> may be a defective epitaxy. By "defective epitaxy" is mean that the extrinsic vertical base material <NUM> may include structural defects such as stacking faults and point defects. It is noted that any of these defects do not propagate into the vertical base <NUM> because the vertical base <NUM> is used only as a seed layer for epitaxial growth of the extrinsic vertical base material <NUM>.

Note that defects in the extrinsic vertical base material <NUM> are not found to adversely affect the operation or performance of the completed Darlington pair sensor.

Further note that the shape of the extrinsic vertical base material <NUM> shown in <FIG> is exemplary only.

In some alternative embodiments, the extrinsic vertical base material <NUM> can be a large grain polycrystalline silicon (polysilicon). Rather than growing the extrinsic vertical base material <NUM> epitaxially, the polysilicon may be deposited by a deposition process including, but not limited to, PVD, CVD, plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof.

The extrinsic base material <NUM> has a same doping polarity as the vertical base <NUM>, and a higher doping concentration than the vertical base <NUM>. The doping concentration of the extrinsic base material <NUM> may be, for example, in the range of <NUM><NUM>-<NUM>×<NUM><NUM> cm-<NUM>. In some embodiments, the extrinsic base material <NUM> has a wider bandgap than the vertical base <NUM>. As known, this may be advantageous for reducing the base leakage. For example, if the vertical base <NUM> is comprised of Ge or SiGe, the extrinsic base <NUM> may be comprised of SiGe with higher concentration than that of the vertical base <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after removal of the base region mask <NUM> and deposition of a base separation hard mask <NUM>. The base separation hard mask <NUM> is used to physically separate the left <NUM> and a right 2250R sides of the extrinsic vertical base <NUM> material, as described in more detail in the below series of <FIG>, <FIG>, <FIG>, <FIG>, <FIG> ("separation Figure series").

<FIG> is a cross section view showing interim structures after extrinsic vertical base material <NUM> is etched away where not protected (under) by the base separation hard mask <NUM>, e.g., during a vertical RIE. The extrinsic vertical base material <NUM> remaining forms an extrinsic vertical base <NUM> that has a left <NUM> and right 2450R side that are electrically and physically separated from one another. The process of physically separating the extrinsic vertical base <NUM> into the left <NUM> and right 2450R sides is further described in the separation Figure series, below.

For instance, as described below, some extrinsic vertical base material <NUM> is etched away to expose the ends of the vertical base <NUM> in directions in and out of <FIG> so that the left <NUM> and right 2450R side of the vertical base <NUM> remaining after the vertical etch are physically separated.

In some embodiments, the left <NUM> and right 2450R side of the vertical base <NUM> are physically separated by the vertical base <NUM>. The left extrinsic vertical base <NUM> is in contact with a left side of the vertical base <NUM> and the right extrinsic vertical base 2450R is in contact with a right side of the vertical base <NUM>.

The vertical etch/RIE leaves spatial voids <NUM> above the bottom spacer <NUM> and surrounding the remaining etched oxide layer <NUM>, top spacer <NUM>, and extrinsic vertical base <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after filling the spatial voids <NUM> with interlayer dielectric (ILD) <NUM> using materials and deposition methods described above.

<FIG> is a cross section view showing interim structures after removal of the base separation hard mask <NUM> and a planarization/CMP that makes the tops of the etched oxide layer <NUM> and the ILD <NUM> level.

<FIG> is a cross section view showing interim structures <NUM> after deposition of an emitter mask <NUM> with a pattern deposition or deposition followed by patterning that positions a mask opening <NUM> over the vertical base <NUM>. The emitter mask <NUM> uses mask materials and is deposited by deposition methods that are described above and are well known.

<FIG> is a cross section view showing interim structures <NUM> after recessing the unprotected part of the etched oxide layer <NUM> and exposing the top surface <NUM> of the vertical base <NUM>. The etched oxide layer <NUM> recess can be performed by a direction RIE, e.g., that is selective to the material in the top spacer <NUM>. The recess leaves a spatial void <NUM> above the top surface <NUM> of the vertical base <NUM>.

<FIG> is a cross section view showing interim structures <NUM> filing the spatial void <NUM> by epitaxially growing of the vertical emitter <NUM> on the exposed top surface <NUM> of the vertical base <NUM>, resulting in formation of the vertical/sensing/dual-base BJT <NUM>/<NUM>/<NUM>/<NUM> of the Darlington pair BJT sensor.

The vertical emitter material <NUM> (or a top portion of the vertical emitter material <NUM>) may be made of a defective epitaxy. It is noted that any of these defects do not propagate into the vertical base <NUM> because the vertical base <NUM> is used only as a seed layer for epitaxial growth of the vertical emitter material <NUM>.

Note these defects in the extrinsic vertical emitter material <NUM> are not found to adversely affect the operation or performance of the completed Darlington pair sensor.

Where the vertical/sensing BJT <NUM>/<NUM>/<NUM>/<NUM> is a PNP type, the vertical emitter material <NUM> is P-doped. Where the vertical/sensing BJT <NUM>/<NUM>/<NUM>/<NUM> is a NPN type, the vertical emitter material <NUM> is N-doped. The doping is done by techniques described above that are known.

In alternative embodiments, the vertical emitter material <NUM> is a large grain polycrystalline silicon (polysilicon). Rather than growing the vertical emitter material <NUM> epitaxially, the polysilicon may be deposited in the spatial void <NUM> by a deposition process including, but not limited to, PVD, CVD, plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof.

The vertical emitter material <NUM> may have a doping concentration, for example, in the range of <NUM><NUM>-<NUM>×<NUM><NUM> cm-<NUM>. In some embodiments, a bottom portion of the vertical emitter material <NUM> may have a relatively lower doping concentration, for example, in the range of <NUM><NUM>-<NUM><NUM> cm-<NUM>. As known, the lower doping of the bottom portion may be advantageous in reducing bandgap narrowing, as well as Auger recombination. In some embodiments, the vertical emitter material <NUM> has a wider bandgap than the vertical base <NUM>. As known, this may be advantageous in increasing the emitter transfer ratio and therefore the BJT gain. For example, if the vertical base <NUM> is comprised of Ge or SiGe, the vertical emitter <NUM> may be comprised of SiGe with higher concentration than that of the vertical base <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after removing the emitter mask <NUM> by a CMP. Alternatively, the emitter mask <NUM> can selectively be removed by a known selective etch followed with an optional CMP.

<FIG> is a cross section view showing interim structures after an ILD deposition <NUM> covers the vertical/sensing BJT of the Darlington pair BJT sensor (including the vertical emitter <NUM>) above the lower spacer <NUM>. An optional CMP may follow the ILD deposition. The ILD <NUM> materials and deposition methods are as described above.

<FIG> is a cross section view showing interim structures <NUM> after a masked etching forms a sensing trench <NUM>. For example, the masked etching chemistries removes exposed ILD <NUM> material and is selective to the bottom spacer <NUM> material. The width of the sensing trench <NUM> may be in the range of <NUM>-<NUM>, but narrower and wider sensing trenches may be used as well.

<FIG> is a cross section view showing interim structures <NUM> after a lateral etch of one of the separated sensing sides (here the right side 2450R) of the doped extrinsic vertical base material <NUM> creating a sense contact void <NUM> in contact with the sensing trench <NUM>.

The lateral etch is performed to remove material from the extrinsic vertical base <NUM> on the extrinsic vertical base <NUM> side (left <NUM> or right 2450R) that are in contact with the sensing trench <NUM>. The lateral etch creates the sense contact void <NUM> in the side <NUM>/2450R of the extrinsic vertical base <NUM> in contact with the sensing trench <NUM> so that fluid (e.g., liquid and/or gas) entering the sensing trench <NUM> will contact the side <NUM>/2450R of the extrinsic vertical base <NUM> in contact with the sensing trench <NUM>.

In some embodiments, the sense contact void <NUM> is etched away to a depth into the extrinsic vertical base <NUM> material from <NUM> to <NUM>. Other depths are envisioned.

Therefore, the sensing trench <NUM> is in fluid communication with the sense contact void <NUM> in that any fluid within the sensing trench <NUM> will be in contact with the respective separated side <NUM>/2450R (the side is 2450R shown in <FIG>) of the extrinsic vertical base <NUM>.

The lateral etch that removes material from the exposed side of the extrinsic base <NUM> can be a wet etch or a gaseous etch. However, a wet etch is more preferred.

<FIG> is a cross section view showing interim structures <NUM> after the sensing trench <NUM> and sense contact void <NUM> are filled with metal, i.e., after the sensing trench <NUM> metal fill <NUM>.

The sensing trench <NUM> and sense contact void <NUM> can be filled with a ALD deposition of metal or other conductive material <NUM>. Alternatively, the sensing trench <NUM> and sense contact void <NUM> are lined with a layer of metal or other conductive material, e.g., with an ALD deposition. Then the remainder of the sensing trench <NUM> and sense contact void <NUM> are filled with deposition of metal or other conductive material by as process such as CVD or PVD or plating. In some embodiments, the sensing trench <NUM> and sense contact void <NUM> are filled or lined with a semiconducting or an insulating material such as a high-k dielectric, instead of a metal or a conductive material.

In some embodiments, the fill conductive material/metal <NUM> is Titanium nitride (TiN). However, other fill materials are envisioned. For example, the fill conductive material/metal <NUM> can be chosen because of a chemical and/or electrical reaction to a specific fluid or sensed substance that is to be sensed in the sensing trench <NUM>, as described in more detail below.

<FIG> is a cross section view showing interim structures <NUM> after some of the trench metal fill <NUM> is partially etched to form an etched back trench metal fill <NUM>.

In some embodiments, the trench metal etch back is performed by a timed wet etch with a chemistry that removes the fill conductive material/metal <NUM>. The timing of the wet etch may be experimentally determined. In alternative embodiments, a vertical RIE is used to remove all the metal in the sensing trench in one operation. The etched back trench metal fill <NUM> may be chosen to be metal/substance specific to the sensed material.

<FIG> is a cross section view showing interim structures <NUM> after removing the remaining trench metal fill <NUM> while leaving a metal sliver sensing surface <NUM>. In some embodiments, the metal sliver sensing surface <NUM> remains in the sense contact void <NUM> and in electrical and physical contact with the side of the <NUM>/2450R (2450R is shown in <FIG> as a non-limiting example) of the vertical extrinsic base <NUM> adjacent to the sensing trench <NUM>/<NUM>.

The remaining trench metal fill <NUM> is removed with a directional RIE. Therefore, the sensing trench <NUM>/<NUM> is re-opened to create an open space to receive fluids (liquid or gas), e.g., containing sensed substances <NUM>.

The metal sliver sensing surface <NUM> can have a sensing surface height <NUM> between, for example <NUM> and <NUM>, and a sensing surface area <NUM>. In some embodiments, the sensing surface area <NUM> is approximately equal to the sensing surface height <NUM> times the depth (in the direction in or out of <FIG>) of the sensing trench <NUM>/<NUM>. A larger sensing surface area <NUM> will increase the sensitive of the Darlington pair sensor to sensed substances <NUM> located in the sensing trench <NUM>/<NUM>. In some embodiments, note that the sensing surface area <NUM> may not be a flat surface but might be convex due to the directional RIE.

Sensed substances <NUM> (shown as "xxx") can include molecules and/or ions of material that are located within the sensing trench <NUM>/<NUM>, e.g., in suspension and/or in solution in a fluid (liquid and/or gas) in the sensing trench <NUM>/<NUM>.

Accordingly, in some embodiments, the trench metal fill <NUM> material determines the type of metal/conductive material making up the metal sliver sensing surface <NUM>. In some embodiments, the trench fill <NUM> is comprised of a non-metal/non-conductive material such as a high-k dielectric, thus making up a high-k dielectric sliver sensing surface <NUM>. In some embodiments, the sensing surface <NUM> may be functionalized with a material suitable for the species being sensed. For example, if the sensing surface <NUM> is comprised of a high-k dielectric, self-assembled organic monolayers may be used for functionalization using known approaches.

As non-limiting examples, due to the sliver sensing <NUM> surface <NUM> reaction to a given sensed substance <NUM>, in some embodiments, a TiN trench metal fill <NUM> material is chosen to sense the sense substance hydrogen ion (e.g., pH) <NUM>, AgCl <NUM> is chosen to sense chloride <NUM>, Au <NUM> is chosen to sense DNA <NUM>, and thio material chemistries are chosen <NUM> to sense proteins <NUM>.

Therefore, the sensing trench <NUM>/<NUM> is a spatial void capable of receiving fluids containing or being one or more sensed substances <NUM> which are directed to be in contact and interact with the metal sliver sensing surface <NUM> within the sensing trench <NUM>/<NUM>.

It is noted that due to symmetries of the structure <NUM>, the sensing trench <NUM> and the metal sliver sensing surface <NUM> together can be formed so the metal sliver sensing surface <NUM> is in contact with either the left <NUM> side or right 2450R side of the extrinsic vertical base <NUM>. The side of the extrinsic vertical base <NUM> (either <NUM> or 2450R, respectively) that is in contact with the metal sliver sensing surface <NUM> becomes the sensing base of the sensing/vertical BJT. Accordingly, the extrinsic vertical base (either 2450R or <NUM>, respectively) that is not in contact with the metal sliver sensing surface <NUM> becomes the non-sensing base of the sensing/vertical BJT, control extrinsic vertical base, or the control base. The sensing base and control base are the two bases of the sensing/vertical BJT.

The metal silver sensing surface lies between the sensing trench <NUM> and the respective sensing base and is electrically connected to the respective sensing base. As shown in <FIG> as a non-limiting example, the sensing base is the right side extrinsic vertical base 2450R and the control (non-sensing) extrinsic vertical base (control base) is the left side extrinsic vertical base <NUM>.

It is noted that in the described embodiments, the physical separation of the sides <NUM>/2450R of the extrinsic vertical base <NUM> creates two separate (dual) base terminals, where the sensing base terminal is subject to the electrical/chemical reactions of the sliver sensing <NUM> surface <NUM> via the sensed substances <NUM>, while the control base <NUM>/2450R can be connected to an input (external) signal or bias. The control and senor base terminals are electrically (e.g., electrostatically) coupled to each other, as is the case in any dual-base BJT, and collectively determine the output characteristics (e.g., current-voltage characteristics) of the BJT.

The vertical/sensor BJT <NUM>/<NUM>/<NUM>/<NUM>/<NUM>/2450R is a dual base <NUM>/2450R/<NUM> vertical/sensor BJT of the Darlington pair BJT sensor, including, as a non-limiting example, the sensing base 2450R and the control base <NUM>.

<FIG> is a cross section view showing a completed embodiment <NUM> of the Darlington Pair BJT sensor <NUM> after formation of external contacts <NUM>/<NUM>/<NUM>/<NUM>. Functionalization of the sliver sensing surface <NUM>, if desired, is typically performed at this stage.

An external contact <NUM> connects to the horizontal emitter <NUM> of the horizontal/lateral BJT <NUM>/<NUM>/<NUM>/<NUM>. External contact <NUM> connects to the extrinsic base extrinsic vertical/control base <NUM> (as a non-limiting example, the left side <NUM>). External contact <NUM> connects to the vertical emitter <NUM> of the vertical/sensing BJT <NUM>/<NUM>/<NUM>/<NUM>/<NUM>/2450R/<NUM>. External contact <NUM> connects to the horizontal collector <NUM> of the horizontal/lateral BJT <NUM>/<NUM>/<NUM>/<NUM>.

In some embodiments, there are multiple external contacts <NUM> and <NUM> some of which are electrically connected in or out of the drawing plane and not shown in <FIG>.

External contacts <NUM>/<NUM>/<NUM>/<NUM> are formed by known metallization techniques. For example, external contact trenches are formed, e.g., by laser ablation or a patterned etch. An external contact conductor material is then deposited into contact trenches. Example contact conductor material include an elemental metal such tungsten, cobalt, ruthenium, rhodium, zirconium, copper, aluminum, and platinum. In some embodiments, the contact conductor material is cobalt or tungsten. Any overfill of the external contact trenches can be removed by a CMP.

Additional contacts can be made externally to the structure <NUM> to make alternative configurations of the vertical/sensing BJT and horizontal/lateral BJT depending on the polarities of the respective BJTs in the BJT pair and circuit design criteria. As a non-limiting example, the external emitter contact <NUM> for the vertical/sensing BJT is configured to be externally connected to the external collector contact <NUM> of the horizontal/lateral BJT.

As described above, the lateral/amplifying BJT and the vertical/sensing BJT can be different polarities. For example, the BJT's can be configured in one of the following configurations, the amplifying BJT is PNP and the sensing BJT is NPN, and the amplifying BJT is NPN and the sensing BJT is PNP.

In alternative configurations, two or more of the Darlington pair BJT sensors <NUM> can be configured so the sensing trenches <NUM> of a first Darlington pair BJT sensor <NUM> and one or more second Darlington Pair BJT sensors <NUM> are connected in fluid communication. By fluid communication is meant that a common fluid stream will flow through each of all of the connected sensing trenches <NUM> with no or little resistance to the fluid flow. This enables each of the connected the Darlington pair BJT sensors <NUM> to convey the common fluid through each of the connected sensing trenches <NUM> so each of the Darlington pair BJT sensors <NUM> can sense one or more sensed substances <NUM> in the common fluid flowing through the sensing trenches <NUM>. In this configuration, multiple types of sensed substances <NUM> can be sensed in a single integrate sensor with multiple Darlington pair BJT sensors <NUM>.

<FIG>, in the separation Figure series, is a cross section view showing interim structures <NUM> after growth of the doped extrinsic vertical base material <NUM> surrounding the vertical base <NUM>. See also the description of <FIG> above. The base region mask <NUM> is on the etched oxide layer <NUM> and a vertical projection (not shown) of the base region mask <NUM> overlaps both sides and both ends (front and back, not shown) of the horizontal common extrinsic base/collector <NUM>.

<FIG> is a top view of the interim structure <NUM> shown in <FIG> showing the top surface of the base region mask <NUM> and the part of the surface of the extrinsic vertical base material <NUM> that is unprotected (not under the base region mask <NUM>).

Note again that the shape of the extrinsic vertical base material <NUM> shown in <FIG> is shown for purposes of explanation and that the actual shape of the extrinsic vertical base material <NUM> may differ. Also note that the horizontal emitter <NUM>, common extrinsic base/collector <NUM>, lateral intrinsic base <NUM>, spacers <NUM>, and lateral collector <NUM> are omitted for simplicity.

<FIG>, in the separation Figure series, is a cross section view showing interim structures <NUM> after removing the base region mask <NUM>, as described above, see the description of <FIG>.

<FIG> is a top view <NUM> of the interim structure <NUM> of <FIG> showing the etched oxide layer <NUM> and the non-protected surface of the extrinsic vertical base material <NUM>.

<FIG>, in the separation Figure series, is a cross section view showing interim structures <NUM> after deposition of the base separation hard mask <NUM>.

<FIG> is a top view <NUM> of the interim structure shown in <FIG>. The top surface of the deposited base separation hard mask <NUM> is shown. The top non-protected (not under the base separation hard mask <NUM>) surface of the extrinsic vertical base material <NUM> also is shown. The front edge <NUM> and the back edge <NUM> of the base separation hard mask <NUM> are shown so that their vertical projection down through the structure <NUM> will reveal the front 1650F and back ends 1650B, respectively, of the vertical base <NUM>, as described below in <FIG>. Accordingly, the base separation hard mask <NUM> is "shorter" than the removed base region mask <NUM>.

<FIG> is a cross section view showing interim structures <NUM> after removing the unprotected doped extrinsic vertical base material surrounding the ends 1650F/1650B of and other volumes surrounding the vertical base <NUM> down to the bottom spacer <NUM>. This etch/removal separates the extrinsic vertical base <NUM> material into a right extrinsic vertical base 2450R and left extrinsic vertical base <NUM>. See also the description of <FIG> above.

<FIG> is a top view <NUM> of the interim structure <NUM> shown in <FIG>. The "shortened" base separation hard mask <NUM> allows removal of the extrinsic vertical base <NUM> material to expose a front end 1650F and a back end 1650B of the vertical base <NUM>. By allowing the front end 1650F and a back end 1650B of the vertical base <NUM> to protrude beyond the <NUM> extrinsic vertical base <NUM>, the extrinsic vertical base <NUM> is physically separated into a left <NUM> and right 2450R side by the vertical base <NUM>. This enables embodiments of the Darlington pair BJT sensor (the vertical/sensing BJT) to have a dual base. In some embodiments, one of the bases is used as a sensing base, e.g., the base that is connected to the metal sliver sensing surface <NUM>, for instance 2450R. The other, or non-sensing base or control base, e.g., the base not connected to the metal sliver sensing surface <NUM> (for instance <NUM>), can be used as a separate control base.

<FIG> is a cross section view showing interim structures <NUM> after an interlayer dielectric (ILD) <NUM> fill.

<FIG> is a top view <NUM> of the interim structure <NUM> shown in <FIG>.

Also refer to the description of the ILD fill in <FIG>.

<FIG> is a flow chart of a process <NUM> of making a Darlington pair BJT sensor <NUM>.

Step <NUM> begins the process <NUM> with creating the horizontal/lateral/amplifying BJT <NUM>/<NUM>/<NUM> with the common extrinsic base/collector <NUM> as described in the description of <FIG>.

Step <NUM> creates the vertical/sensing BJT <NUM>/<NUM>/<NUM>/ <NUM> with a dual extrinsic base <NUM>/<NUM>/2450R and the common extrinsic base/collector <NUM> being the extrinsic base <NUM> to the lateral BJT and the vertical collector <NUM> of the vertical/sensing BJT as described in the description of <FIG> and <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>.

Step <NUM> creates the sensing trench <NUM>/<NUM> and the metal sliver sensing surface <NUM> as described in the description of <FIG>.

Step <NUM> creates the external connections <NUM>/<NUM>/<NUM>/<NUM> and external configuration connections as described in the description of <FIG>.

<FIG> is a circuit diagram of a non-limiting example of a dual-base, complementary (Sziklai) Darlington pair BJT sensor <NUM> where the vertical/sensing BJT <NUM> is an PNP BJT with two bases (a control base, external connection <NUM>, and a sensing base, connection <NUM>) and the horizontal/lateral/amplifying BJT <NUM> is an NPN BJT.

As noted above, different BJT polarities and configurations are envisioned.

The vertical/sensing BJT <NUM> has a vertical emitter <NUM> external connection <NUM>. The vertical collector <NUM> is one and the same element with the extrinsic base <NUM> in contact with the horizontal base <NUM> of the horizontal/amplifying BJT <NUM>/<NUM>/<NUM>/<NUM>/<NUM> shown as a common internal connection in <FIG>. The vertical/sensing BJT <NUM> has a separated intrinsic base <NUM>/<NUM>/2450R where the control base, as an example <NUM>, is connected to the external connection <NUM>. The metal sliver sensing surface <NUM> is connected to the right side 2450R (as an example) of the extrinsic vertical base <NUM> and is the sensing base <NUM>. In some embodiments, the emitter of the vertical/sensing BJT <NUM> is external connected/configured to the collector of the horizontal/amplifying BJT <NUM> to complete the configuration of the Darlington pair sensor <NUM>/<NUM>. Other external connections/configurations are envisioned that would enable different configurations of Darlington pair sensors.

Other polarities of the vertical sensing BJT <NUM> and horizontal/amplifying BJT <NUM> are envisioned. For example, a complementary (Sziklai) Darlington pair can be configured where the vertical sensing BJT <NUM> is an NPN BJT and the horizontal/amplifying BJT <NUM> is a PNP BJT.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the appended claims. For example, the semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, expert and artificial intelligence systems, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention.

Claim 1:
A Darlington pair sensor comprising:
an amplifying bipolar junction transistor (BJT) horizontally disposed on a substrate (<NUM>), the amplifying BJT having a horizontal emitter (<NUM>), a horizontal base (<NUM>), a horizontal collector (<NUM>), and a common extrinsic base/collector (<NUM>), the common extrinsic base/collector being an amplifying BJT extrinsic base for the amplifying BJT and the common extrinsic base/collector being in contact with and disposed upon the horizontal base;
a sensing BJT in a vertical orientation with respect to the amplifying BJT, the sensing BJT having a vertical emitter (<NUM>), a vertical base (<NUM>), an extrinsic vertical base (<NUM>) separated into a left extrinsic vertical base and a right extrinsic vertical base (<NUM>, 2450R), and the common extrinsic base/collector, the common extrinsic base/collector also being a sensing BJT collector for the sensing BJT;
wherein the left extrinsic vertical base is in contact with a left side of the vertical base and the right extrinsic vertical base in in contact with a right side of the vertical base and the left extrinsic vertical base and right extrinsic vertical base are separated from one another;
a sensing trench (<NUM>) being a spatial void capable of receiving fluids containing one or more sensed substances, the sensing trench being adjacent to one of the left extrinsic vertical base and the right extrinsic vertical base which is a sensing extrinsic vertical base, the one of the left extrinsic vertical base and the right extrinsic vertical base that is not the sensing extrinsic vertical base being a control extrinsic vertical base; and
a sliver sensing surface (<NUM>), the sliver sensing surface being a conductive material between the sensing trench and the sensing extrinsic vertical base and the sliver sensing surface being in electrical contact with the sensing extrinsic vertical base.