Patent Description:
Microelectronics generally include a central processing unit (CPU). In order to enhance performance, CPU products are increasingly integrating multiple dies within the CPU package in a side-by-side or other multi-chip module (MCM) format. An embedded multi-die interconnect bridge (EMIB) is a way to electrically connecting multiple dies within a microelectronic package. Document <CIT> relates to an organic bridge device. Document <CIT> shows a circuit device comprising resin layers. Document <CIT> shows a package structure including multiple devices.

An embedded multi-die interconnect bridge (EMIB) enables low cost and <NUM>. 5D packaging for high density interconnects between heterogeneous die on a single package. Instead of an expensive silicon (Si) interposer with through silicon vias (TSV), a small silicon bridge chip, termed as EMIB, can be embedded in an organic package substrate, and can enable high-density die-to-die connections only where needed. Standard flip-chip assembly can be used for robust power delivery and to connect high-speed signals directly from a chip to the package substrate using this bridge. EMIBs eliminate the need for TSVs and specialized interposer silicon that add complexity and cost.

While an EMIB offers significant advantages and cost benefits over silicon interposer or high-density substrate surface layers, it does have some issues. The bridge that is Si-based is still manufactured using costly wafer fab processes. In addition, a low coefficient of thermal expansion (CTE) of the Si bridge compared to the buildup dielectric that it is embedded in, EMIB substrates suffer from thermomechanical issues such as heat induced stresses, warpage, delamination, etc both within the substrate as well as post flip chip attachment. The thermomechanical issues can therefore limit the Si bridge size that can be embedded. Furthermore, use of silicon design rules, can restrict creation of metal reference planes that are crucial for high speed input/output (I/O) signaling in the embedded silicon bridge.

As disclosed herein, to overcome the thermomechanical issues, a molded fine line and spaced (FLS) interconnect bridge with graded CTEs can be employed to balance/minimize the CTE mismatch that can occur in EMIB substrates and can be manufactured using low cost substrate, molded embedded pane-level ball (EPLB) grid array packaging processes. A further benefit of this architecture is the ability to use substrate design rule like reference planes in the design in that can truly offer wider flexibility for design in enabling a high-speed embedded bridge.

Turning now to the figures, <FIG> illustrates a microelectronic package <NUM>. <FIG> illustrates a cross-section of the microelectronic package <NUM>. The microelectronic package <NUM> can include a first die <NUM>, a second die <NUM>, an EMIB <NUM>, and substrate <NUM>. As shown in <FIG>, the microelectronic package <NUM> can also include electrical connections <NUM> that can be used to power the first die <NUM> and the second die <NUM> and allow signals to pass between the first die <NUM> and the second die <NUM>. The electrical connections <NUM> can also be used to provide ground references.

As shown in <FIG>, the EMIB <NUM> can be surrounded, or embedded, in the substrate <NUM>. The substrate <NUM> may have a high CTE. For example, the substrate <NUM> may be made of a dielectric with a CTE of approximately <NUM>/°C or higher. The EMIB <NUM> may have a low CTE compared to the substrate <NUM>. For example, the EMIB <NUM> may be made of a silicon (Si) alloy or epoxy/Si material that has a CTE of approximately <NUM>/°C.

The mismatch in CTE between the buildup dielectric and EMIB can cause thermal stresses and warpage within the substrate <NUM>. The thermal stresses and warpage can lead to delamination and fracturing of the various layers that make up the EMIB substrate <NUM>. <FIG> show various solutions to combat the mismatch in CTE in accordance with embodiments disclosed herein.

<FIG> illustrates a layered EMIB <NUM>. As shown in <FIG>, the EMIB <NUM> can include a first layer <NUM>, a second layer <NUM>, a third layer <NUM>, and a fourth layer <NUM> (collectively referred to as layers). During operation, heat generated with the EMIB <NUM> can be dissipated into the substrate <NUM> and other components, such as heat sinks attached to the first die <NUM> and the second die <NUM>. As the heat is both generated and dissipated, the layers within the EMIB <NUM> can heat at different rates due to the amount of electric current flowing through the layers, their proximity to other heat sources and sinks and layer material properties. The layers can be molded layers. As such, each of the layers can include a molded material.

To combat the uneven heating, and hence warpage, delamination, etc., each of the layers can be created to have a different CTE. For example, the CTE of the first layer <NUM> may be <NUM>/°C, the CTE of the second layer <NUM> may be <NUM>/°C, the CTE of the third layer <NUM> may be <NUM>/°C, and the CTE of the fourth layer <NUM> may be <NUM>/°C. The CTE of the layers need not decrease in a direction away from the first die <NUM> and the second die <NUM> and instead may increase. For example, the CTE of the first layer <NUM> may be <NUM>/°C, the CTE of the second layer <NUM> may be <NUM>/°C, the CTE of the third layer <NUM> may be <NUM>/°C, and the CTE of the fourth layer <NUM> may be <NUM>/°C.

The variation in CTE from one layer to another can be adjusted depending on the application and materials used to build the layers. For example, the CTE can vary linearly or non-linearly. The CTE range can also differ from application to application. For example, an EMIB substrate in a liquid cooled computer may able to dissipate heat faster and therefore the CTE range of the EMIB <NUM> may not to be as large as an EMIB substrate in a computer that used a gas (e.g., air) as a cooling fluid.

The variation in CTE can be achieved using differing levels of a dopant used to manufacture the layers. For example, the layers can be manufactured from materials such as, but not limited to, Epoxy Phenol, Epoxy Anhydride, or Epoxy Amine and a filler material such as, but not limited to, silica. By varying the ration of silica to epoxy, the CTE of the layers can be varied. For instance, a layer with an approximately <NUM>:<NUM> ratio of epoxy to filler may have a CTE of <NUM>/°C and a layer with an approximately <NUM>:<NUM> ratio of epoxy to filler may have a CTE of <NUM>/°C.

In addition, the variation in CTE can be achieved by using different filler materials. For example, the layers can be manufactured from Epoxy Phenol and materials such as, but not limited to, silica, alumina, or an organic compound can be used as fillers for different layers. Using the various filler materials, the CTE of the layers can be varied from between approximately <NUM>/°C to approximately <NUM>/°C.

As disclosed herein, each of the layers can be routing layers or ground layers embedded within the substrate <NUM>. Each of the layers can include various traces or other electrically conductive pathways. Each of the layers can be positioned such that adj acent layers have CTEs that vary from one another as described herein.

<FIG> illustrates an encapsulated EMIB <NUM> in accordance with some embodiment disclosed herein. As shown in <FIG>, the EMIB <NUM> can be encapsulated by a mold <NUM>. The mold <NUM> can have a CTE that is close to the CTE of the substrate <NUM> in which the EMIB <NUM> is embedded in. For example, the CTE of the substrate <NUM> may be <NUM>/°C and the CTE of the mold <NUM> may be <NUM>/°C. In addition, the CTE of the mold <NUM> can be close to the CTE of the EMIB <NUM>. For example, the CTE of the EMIB <NUM> may be <NUM>/°C and the CTE of the mold <NUM> may be <NUM>/°C. Furthermore, the CTE of the mold <NUM> can be in between the CTEs of the EMIB <NUM> and the substrate <NUM>. For example, the CTE of the EMIB <NUM> may be <NUM>/°C, the CTE of the substrate <NUM> may be <NUM>/°C, and the CTE of the mold <NUM> may be <NUM>/°C.

Having the CTE of the mold <NUM> be somewhere in between the CTE of the EMIB <NUM> and the substrate <NUM> can allow the mold <NUM> to absorb some of the thermal stresses that can be induced by the heating and CTE differences between the EMIB <NUM> and the substrate <NUM>. In addition, the mold <NUM> can be manufactured of a material that can facilitate heat transfer in a desired direction. For example, to help dissipate heat from the EMIB <NUM> to the substrate <NUM>, the mold <NUM> can be manufactured of a material with a high thermal conductivity. To help insulate the EMIB <NUM> from heat that may be generated within the substrate <NUM>, the mold <NUM> may be manufactured with a material that has a low thermal conductivity. As such, heat generated within the EMIB <NUM> can be directed in a direction towards the first die <NUM> and the second die <NUM>, to be removed from heat sinks attached to the first die <NUM> and the second die <NUM>.

The mold <NUM> can encapsulate all or a portion of the EMIB <NUM>. For example, as shown in <FIG>, the mold <NUM> can surround the EMIB <NUM> on all sides except a side proximate the first die <NUM> and the second die <NUM>. Other sides of the EMIB <NUM> can be exposed.

The mold <NUM> can be manufactured from materials and fillers as described above with respect to the layers. In addition, the mold <NUM> can be manufactured from multiple layers as well. For example, as shown in <FIG>, the mold <NUM> can be manufactured from a first layer <NUM> and a second layer <NUM>. While <FIG> shows only two layers, any number of layers can be used to manufacture the mold <NUM>. Furthermore, the CTE for the layers of the mold <NUM> can be varied as described above.

<FIG> illustrates an encapsulated layered EMIB <NUM> in accordance with some embodiment disclosed herein. As shown in <FIG>, the EMIB <NUM> can include the mold <NUM> and the EMIB <NUM>. The EMIB <NUM> can include the first layer <NUM>, the second layer <NUM>, the third layer <NUM>, and the fourth layer <NUM>. In addition, the mold <NUM> can be layered as described above.

The combination of the mold <NUM> and the layers can allow for the CTE of the EMIB <NUM> to be further customized. For example, the layers can each have different CTEs for thermal management. The mold <NUM> can have a CTE that further reduces the mismatch in CTE between the layers and the substrate <NUM>. For example, the CTEs of the layers can vary from, for example, <NUM>/°C to <NUM>/°C and the CTE of the mold <NUM> can be <NUM>/°C. For a layered mold <NUM>, the CTEs of the layers can range from <NUM>/°C to <NUM>/°C and the layers of the mold <NUM> can vary from <NUM>/°C to <NUM>/°C.

<FIG> illustrates a method <NUM> for manufacturing an EMIB embedded substrate. <FIG> will be discussed with reference to <FIG> and <FIG> showing the process steps for the method <NUM>. The method <NUM> can be implemented in a high volume manufacturing (HVM) processing line.

The method <NUM> can begin at stage <NUM> where a substrate can be provided. From stage <NUM>, the method <NUM> can proceed to stage <NUM> where layers can be created (process stage <NUM>). For example, the very dense and fine line spaced layers can be created using high-resolution lithography. During the creation of the layers, very dense and fine line spaced layers can be created on a first layer using high-resolution lithography. The traces in the subsequent layers may not be as fine as in the first layer. However, the subsequent layers can be handled through fan out routing. In addition, subsequent layers can utilize small filler sizes coupled with less filling to result in CTE variations. For instance, using less filling material can result in progressively higher CTE as subsequent layers are produced. The result can be reasonably fine tracing that can reduce the amount of fan out needed.

As discussed herein, during the creations of the layers, the amount of filler can be varied to alter the CTE of each layer. In addition, the filler can be different for different layers to result in alteration of the CTE from layer to layer. Furthermore, as discussed above, the layers do not have to have a CTE that varies. For instance, the bridge formed by the layers can have a uniform CTE.

From stage <NUM>, the method <NUM> can proceed to stage <NUM> where the layers can be encapsulated by a mold. As discussed above, the mold can have a CTE that is higher than the CTE of the layers forming the bridge. In addition, the mold can be formed of layers that have CTEs that vary from one another.

Encapsulating the layers can include utilizing an EPLB type process flow used to over-mold a high CTE material to encapsulate the layers. The material proximate the substrate can have a CTE that is as close as possible to that of the buildup dielectric.

Note that not all the stages in the method <NUM> have to be performed. For example, the layers can be created with CTEs that vary (stage <NUM>) as described herein and the resulting bridge can be embedded to form the microelectronic package (process stage 704a). Stated another way, stage <NUM> can be omitted from the method <NUM>. In addition, the bridge can be formed with layers that have a uniform CTE and the bridge can then be encapsulated (stage <NUM>) and installed to form the microelectronic package (process stage 704b). Finally, the bridge can be formed with layers having CTEs that vary (stage <NUM>) and the bridge encapsulated (stage <NUM>). The encapsulated bridge can then be embedded to form the microelectronic package (process stage 704c).

<FIG> illustrates a system level diagram, according to one embodiment of the invention. For instance, <FIG> depicts an example of an electronic device (e.g., system) including the microelectronics package <NUM> as described herein. <FIG> is included to show an example of a higher level device application for the present invention. In one embodiment, system <NUM> includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system <NUM> is a system on a chip (SOC) system.

In one embodiment, processor <NUM> has one or more processing cores <NUM> and 812N, where 812N represents the Nth processor core inside processor <NUM> where N is a positive integer. In one embodiment, system <NUM> includes multiple processors including <NUM> and <NUM>, where processor <NUM> has logic similar or identical to the logic of processor <NUM>. In some embodiments, processing core <NUM> includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor <NUM> has a cache memory <NUM> to cache instructions and/or data for system <NUM>. Cache memory <NUM> may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor <NUM> includes a memory controller <NUM>, which is operable to perform functions that enable the processor <NUM> to access and communicate with memory <NUM> that includes a volatile memory <NUM> and/or a non-volatile memory <NUM>. In some embodiments, processor <NUM> is coupled with memory <NUM> and chipset <NUM>. Processor <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna interface <NUM> operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In some embodiments, volatile memory <NUM> includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory <NUM> includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Memory <NUM> stores information and instructions to be executed by processor <NUM>. In one embodiment, memory <NUM> may also store temporary variables or other intermediate information while processor <NUM> is executing instructions. In the illustrated embodiment, chipset <NUM> connects with processor <NUM> via Point-to-Point (PtP or P-P) interfaces <NUM> and <NUM>. Chipset <NUM> enables processor <NUM> to connect to other elements in system <NUM>. In some embodiments of the invention, interfaces <NUM> and <NUM> operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset <NUM> is operable to communicate with processor <NUM>, 805N, display device <NUM>, and other devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. Chipset <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to transmit and/or receive wireless signals.

Chipset <NUM> connects to display device <NUM> via interface <NUM>. Display <NUM> may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the invention, processor <NUM> and chipset <NUM> are merged into a single SOC. In addition, chipset <NUM> connects to one or more buses <NUM> and <NUM> that interconnect various elements <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Buses <NUM> and <NUM> may be interconnected together via a bus bridge <NUM>. In one embodiment, chipset <NUM> couples with a non-volatile memory <NUM>, a mass storage device(s) <NUM>, a keyboard/mouse <NUM>, and a network interface <NUM> via interface <NUM> and/or <NUM>, smart TV <NUM>, consumer electronics <NUM>, etc..

In one embodiment, mass storage device <NUM> includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface <NUM> is implemented by any type of well known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

While the modules shown in <FIG> are depicted as separate blocks within the system <NUM>, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory <NUM> is depicted as a separate block within processor <NUM>, cache memory <NUM> (or selected aspects of <NUM>) can be incorporated into processor core <NUM>.

The following examples are provided as additional information. They are not to be construed as defining the invention. The invention is defined in the claims.

An example includes an embedded multi-die interconnect bridge (EMIB) substrate The EMIB substrate can comprise an organic substrate and a bridge. The bridge can include a plurality of routing layers. The bridge can be embedded in the organic substrate. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer. Further comprising a mold embedded in the organic substrate, the mold encapsulating all or a portion of the bridge and having a CTE between a CTE of the bridge and a CTE of the organic substrate.

An example of the EMIB substrate can optionally include the CTE of each of the plurality of routing layers varying linearly from one routing layer to another.

An example of the EMIB substrate can optionally include the CTE of each of the plurality of routing layers varying non-linearly from one routing layer to another.

An example of the EMIB substrate can optionally include a routing layer of the plurality of routing layers with the lowest CTE being adjacent a die interconnect region of the EMIB substrate.

An example of the EMIB substrate can optionally include a mold having a CTE higher than a highest CTE of one of the plurality of routing layers. The mold can encapsulate a portion of the plurality of routing layers.

An example of the EMIB substrate can optionally include the variation in CTE for each of the plurality of routing layers resulting from each of the plurality of routing layers having a different silica filler content.

An example of the EMIB substrate can optionally include the CTE of the plurality of routing layers varying from about <NUM>/°C to about <NUM>/°C.

An example can include an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge, and a mold. The bridge can include a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. The mold can encapsulate a majority of the plurality of routing layers. The mold can have a coefficient of thermal expansion (CTE) that is greater than a CTE of the plurality of routing layers.

An example of the EMIB substrate can optionally include a routing layer of the plurality of routing layers is adjacent a die interconnect region of the EMIB substrate.

An example of the EMIB substrate can optionally include a variation in CTE for each of the plurality of routing layers resulting from each of the plurality of routing layers having a different silica filler content.

An example of the EMIB substrate can optionally include the CTE of the plurality of routing layers being about <NUM>/°C and the CTE of the mold is about <NUM>/°C.

An example can include an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge, and a mold. The bridge can include a plurality of routing layers. The bridge cam be embedded in the organic substrate. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from about <NUM>/°C to about <NUM>/°C. The mold can have a CTE higher than a highest CTE of one of the plurality of routing layers. The mold can encapsulate a portion of the plurality of routing layers.

An example of the EMIB substrate can optionally include the CTE of the mold being about <NUM>/°C.

An example can include a method of manufacturing an embedded multi-die interconnect bridge (EMIB) substrate. The method can comprise forming a bridge including a plurality of routing layers, each of the plurality of routing layers having a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer; and embedding the bridge in an organic substrate.

An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies linearly from one routing layer to another.

An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies non-linearly from one routing layer to another.

An example of the method can optionally include forming the plurality of routing layers including forming a routing layer of the plurality of routing layers with the lowest CTE adjacent a die interconnect region of the EMIB substrate.

An example of the method can optionally include encapsulating a portion of the plurality of routing layers with a mold. The mold can have a CTE higher than a highest CTE of one of the plurality of routing layers.

An example of the method can optionally include forming the plurality of routing layers including forming each of the plurality of routing layers with a different silica filler content.

An example of the method can optionally include the CTE of the plurality of routing layers varying from about <NUM>/°C to about <NUM>/°C.

An example can include a method of manufacturing an embedded multi-die interconnect bridge (EMIB) substrate. The method can comprise forming a bridge including a plurality of routing layers, each routing layer having a plurality of fine line and spaced (FLS) traces; encapsulating a majority of the plurality of routing layers with a mold, the mold having a coefficient of thermal expansion (CTE) that is greater than a CTE of the plurality of routing layers; and embedding the bridge in an organic substrate.

An example of the method can optionally include forming the plurality of routing layers includes forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies linearly from one routing layer to another.

An example of the method can optionally include forming the plurality of routing layers includes forming each of the plurality of routing layers such that the CTE of each of the plurality of routing layers varies non-linearly from one routing layer to another.

In Example <NUM>, the method can optionally include forming the plurality of routing layers includes forming a routing layer of the plurality of routing layers with the lowest CTE adjacent a die interconnect region of the EMIB substrate.

An example of the method can optionally include forming the plurality of routing layers includes forming each of the plurality of routing layers with a different silica filler content.

An example of the method can optionally include the CTE of the plurality of routing layers being about <NUM>/°C and the CTE of the mold being about <NUM>/°C.

An example can include a method of manufacturing an embedded multi-die interconnect bridge (EMIB) substrate. The method can comprise forming a bridge including a plurality of routing layers, each routing layer having a plurality of traces, each of the plurality of routing layers having a coefficient of thermal expansion (CTE) that varies from about <NUM>/°C to about <NUM>/°C; encapsulating a portion of the plurality of routing layers with a mold having a CTE higher than a highest CTE of one of the plurality of routing layers; and embedding the bridge in an organic substrate.

An example of the method can optionally include forming the plurality of routing layers including forming a routing layer of the plurality of routing layers with the lowest CTE adjacent a die interconnect region of the EMIB.

Claim 1:
An embedded multi-die interconnect bridge, EMIB, substrate comprising:
an organic substrate (<NUM>);
a bridge (<NUM>) embedded in the organic substrate (<NUM>), the bridge (<NUM>) including a
plurality of routing layers (<NUM>), (<NUM>), (<NUM>), (<NUM>) embedded within the bridge (<NUM>), each routing layer having a plurality of traces, each of the plurality of routing layers (<NUM>), (<NUM>), (<NUM>), (<NUM>) having a coefficient of thermal expansion, CTE, that varies from an adjacent routing layer; and
a mold (<NUM>) embedded in the organic substrate (<NUM>), the mold (<NUM>) encapsulating all or a portion of the bridge (<NUM>) and having a CTE between a CTE of the bridge and a CTE of the organic substrate (<NUM>).