Patent Description:
Mobile radio frequency (RF) chip designs (e.g., mobile RF transceivers), including high performance diplexers have migrated to a deep sub-micron process node due to cost and power consumption considerations. The design of such mobile RF transceivers becomes complex at this deep sub-micron process node. The design complexity of these mobile RF transceivers is further complicated by added circuit functions to support communication enhancements, such as carrier aggregation. Further design challenges for mobile RF transceivers include analog/RF performance considerations, including mismatch, noise and other performance considerations. The design of these mobile RF transceivers includes the use of additional passive devices, for example, to suppress resonance, and/or to perform filtering, bypassing and coupling.

<CIT> relates to a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. <CIT> relates to a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. <CIT> relates to a semiconductor device in which a semiconductor film can be crystallized without being affected by a bottom gate electrode, and a method for manufacturing the semiconductor device.

The design of these mobile RF transceivers may include the use of silicon on insulator (SOI) technology. SOI technology replaces conventional silicon substrates with a layered silicon-insulator-silicon substrate to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional, silicon-built devices because the silicon junction is above an electrical isolator, typically a buried oxide (BOX) layer. A reduced thickness BOX layer, however, may not sufficiently reduce the parasitic capacitance caused by the proximity of an active device on the silicon layer and a substrate supporting the BOX layer.

The active devices on the SOI layer may include complementary metal oxide semiconductor (CMOS) transistors. Unfortunately, successful fabrication of transistors using SOI technology may involve the use of raised source/drain regions. Conventionally, a raised source/drain is specified to enable contact between the raised source/drain region and subsequent metallization layers. In addition, a raised source/drain region provides a channel for carriers to travel. As a result, conventional transistors having raised source/drain regions generally suffer from the raised source/drain region problem. The source/drain region problem is characterized by unwanted, parasitic capacitance in the form of fringe capacitance and overlap capacitance between a gate and the source/drain regions of a transistor.

For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings. <FIG> is a schematic diagram of a radio frequency (RF) front end (RFFE) module employing a diplexer according to an aspect of the present disclosure.

A radio frequency (RF) front end module may include an integrated RF circuit structure. The integrated RF circuit structure may include a switch transistor on a front-side semiconductor layer supported by an isolation layer. The switch transistor includes a first source/drain/body region and a raised source/drain/body region coupled to a backside of the first source/drain/body region of the switch transistor. The raised source/drain/body region extends from the backside of the first source/drain/body region toward a backside dielectric layer supporting the isolation layer. The switch transistor also includes a backside metallization coupled to the raised source/drain/body region. The RF front end module may further include an antenna coupled to an output of the switch transistor.

This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

It will be apparent to those skilled in the art, however, that these concepts may be practiced without these specific details. As described herein, the use of the term "and/or" is intended to represent an "inclusive OR", and the use of the term "or" is intended to represent an "exclusive OR".

Mobile radio frequency (RF) chip designs (e.g., mobile RF transceivers) have migrated to a deep sub-micron process node due to cost and power consumption considerations. The design complexity of mobile RF transceivers is further complicated by added circuit functions to support communication enhancements, such as carrier aggregation. Further design challenges for mobile RF transceivers include analog/RF performance considerations, including mismatch, noise and other performance considerations. The design of these mobile RF transceivers includes the use of passive devices, for example, to suppress resonance, and/or to perform filtering, bypassing and coupling.

Successful fabrication of modern semiconductor chip products involves interplay between the materials and the processes employed. In particular, the formation of conductive material plating for semiconductor fabrication in back-end-of-line (BEOL) processes is an increasingly challenging part of the process flow. This is particularly true in terms of maintaining a small feature size. The same challenge of maintaining a small feature size also applies to passive on glass (POG) technology, where high performance components such as inductors and capacitors are built upon a highly insulative substrate that may also have a very low loss to support mobile RF transceiver design.

The design of these mobile RF transceivers may include the use of silicon on insulator (SOI) technology. SOI technology replaces conventional silicon substrates with layered silicon-insulator-silicon substrates to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional, silicon-built devices because the silicon junction is above an electrical isolator, typically a buried oxide (BOX) layer, in which a thickness of the BOX layer may be reduced. A reduced thickness BOX layer, however, may not sufficiently reduce the parasitic capacitance caused by the proximity of an active device on the silicon layer and a substrate supporting the BOX layer. In addition, the active devices on an SOI layer may include complementary metal oxide semiconductor (CMOS) transistor.

Unfortunately, successful fabrication of transistors using SOI technology may involve the use of raised source/drain regions. Conventionally, a raised source/drain enables contact between the raised source/drain region and subsequent metallization layers. In addition, a raised source/drain region provides a channel for carriers to travel. Conventional transistors with raised source/drain regions generally suffer from the raised source/drain region problem. The raised source/drain region problem is characterized by unwanted, parasitic capacitance in the form of fringe capacitance and overlap capacitance between a gate and the source/drain regions. In addition, conventional CMOS technology is limited to epitaxial growth on the front-side of the active devices. As a result, aspects of the present disclosure include a post-layer transfer process to enable backside semiconductor deposition/growth to eliminate the raised source/drain region problem.

Various aspects of the disclosure provide techniques for integrated circuit structures including transistors having backside extended (raised) source/drain/body regions. The process flow for semiconductor fabrication of the integrated circuit structure may include front-end-of-line (FEOL) processes, middle-of-line (MOL) (also referred to as middle end of line (MEOL)) processes, and back-end-of-line (BEOL) processes. The front-end-of-line processes may include the set of process steps that form the active devices, such as transistors, capacitors, diodes. The FEOL processes include ion implantation, anneals, oxidation, chemical vapor deposition (CVD) or atomic layer deposition (ALD), etching, chemical mechanical polishing (CMP), epitaxy. The middle-of-line processes may include the set of process steps that enable connection of the transistors to BEOL interconnect. These steps include silicidation and contact formation as well as stress introduction. The back-end-of-line processes may include the set of process steps that form the interconnect that ties the independent transistors and form circuits. Currently, copper and aluminum provide the interconnects, but with further development of the technology other conductive material may be used.

It will be understood that the term "layer" includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described herein, the term "substrate" may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms chip and die may be used interchangeably unless such interchanging would tax credulity.

Aspects of the present disclosure describe integrated circuit structures including transistors having backside raised source/drain/body regions that may be used as antenna switch transistors in integrated radio frequency (RF) circuit structures for high quality (Q)-factor RF applications. In one configuration, a post layer-transfer process forms the backside raised source/drain/body regions of a transistor. The post-layer transfer process may form a backside semiconductor layer on a backside of the source/drain regions of a transistor. The backside semiconductor layer may extend from a first surface to a second surface of an isolation layer, in which the first surface of the isolation layer supports the transistor.

In this configuration, the post-layer transfer process may include a post-layer deposition process or a post-layer growth process for forming the backside semiconductor layers on the backside of the source/drain regions of the transistor. The raised source/drain/body region is composed of an epitaxially grown, backside semiconductor material. Alternatively, the raised source/drain region may be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other like front-end-of-line fabrication process. In this configuration, the backside raised source/drain regions of the transistor may reduce the parasitic capacitance associated with front-side raised source/drain regions fabricated using conventional CMOS processes. That is, extension of the source/drain regions into a backside of the transistor helps prevent the formation of parasitic capacitance between the body of the transistor and conventional front-side raised source/drain regions.

One goal driving the wireless communication industry is providing consumers with increased bandwidth. The use of carrier aggregation in current generation communications provides one possible solution for achieving this goal. Carrier aggregation enables a wireless carrier, having licenses to two frequency bands (e.g., <NUM> and <NUM>) in a particular geographic area, to maximize bandwidth by simultaneously using both frequencies for a single communication stream. While an increased amount of data is provided to the end user, carrier aggregation implementation is complicated by noise created at the harmonic frequencies due to the frequencies used for data transmission. For example, <NUM> transmissions may create harmonics at <NUM>, which interfere with data broadcast at <NUM> frequencies.

For wireless communication, passive devices are used to process signals in a carrier aggregation system. In carrier aggregation systems, signals are communicated with both high band and low band frequencies. In a chipset, a passive device (e.g., a diplexer) is usually inserted between an antenna and a tuner (or a radio frequency (RF) switch) to ensure high performance. Usually, a diplexer design includes inductors and capacitors. Diplexers can attain high performance by using inductors and capacitors that have a high quality (Q)-factor. High performance diplexers can also be attained by reducing the electromagnetic coupling between components, which may be achieved through an arrangement of the geometry and direction of the components.

<FIG> is a schematic diagram of a radio frequency (RF) front end (RFFE) module <NUM> employing a diplexer <NUM> according to an aspect of the present disclosure. The RF front end module <NUM> includes power amplifiers <NUM>, duplexer/filters <NUM>, and a radio frequency (RF) switch module <NUM>. The power amplifiers <NUM> amplify signal(s) to a certain power level for transmission. The duplexer/filters <NUM> filter the input/output signals according to a variety of different parameters, including frequency, insertion loss, rejection or other like parameters. In addition, the RF switch module <NUM> may select certain portions of the input signals to pass on to the rest of the RF front end module <NUM>.

The RF front end module <NUM> also includes tuner circuitry <NUM> (e.g., first tuner circuitry 112A and second tuner circuitry 112B), the diplexer <NUM>, a capacitor <NUM>, an inductor <NUM>, a ground terminal <NUM> and an antenna <NUM>. The tuner circuitry <NUM> (e.g., the first tuner circuitry 112A and the second tuner circuitry 112B) includes components such as a tuner, a portable data entry terminal (PDET), and a house keeping analog to digital converter (HKADC). The tuner circuitry <NUM> may perform impedance tuning (e.g., a voltage standing wave ratio (VSWR) optimization) for the antenna <NUM>. The RF front end module <NUM> also includes a passive combiner <NUM> coupled to a wireless transceiver (WTR) <NUM>. The passive combiner <NUM> combines the detected power from the first tuner circuitry 112A and the second tuner circuitry 112B. The wireless transceiver <NUM> processes the information from the passive combiner <NUM> and provides this information to a modem <NUM> (e.g., a mobile station modem (MSM)). The modem <NUM> provides a digital signal to an application processor (AP) <NUM>.

As shown in <FIG>, the diplexer <NUM> is between the tuner component of the tuner circuitry <NUM> and the capacitor <NUM>, the inductor <NUM>, and the antenna <NUM>. The diplexer <NUM> may be placed between the antenna <NUM> and the tuner circuitry <NUM> to provide high system performance from the RF front end module <NUM> to a chipset including the wireless transceiver <NUM>, the modem <NUM> and the application processor <NUM>. The diplexer <NUM> also performs frequency domain multiplexing on both high band frequencies and low band frequencies. After the diplexer <NUM> performs its frequency multiplexing functions on the input signals, the output of the diplexer <NUM> is fed to an optional LC (inductor/capacitor) network including the capacitor <NUM> and the inductor <NUM>. The LC network may provide extra impedance matching components for the antenna <NUM>, when desired. Then a signal with the particular frequency is transmitted or received by the antenna <NUM>. Although a single capacitor and inductor are shown, multiple components are also contemplated.

<FIG> is a schematic diagram of a wireless local area network (WLAN) (e.g., WiFi) module <NUM> including a first diplexer <NUM>-<NUM> and an RF front end module <NUM> including a second diplexer <NUM>-<NUM> for a chipset <NUM> to provide carrier aggregation according to an aspect of the present disclosure. The WiFi module <NUM> includes the first diplexer <NUM>-<NUM> communicably coupling an antenna <NUM> to a wireless local area network module (e.g., WLAN module <NUM>). The RF front end module <NUM> includes the second diplexer <NUM>-<NUM> communicably coupling an antenna <NUM> to the wireless transceiver (WTR) <NUM> through a duplexer <NUM>. The wireless transceiver <NUM> and the WLAN module <NUM> of the WiFi module <NUM> are coupled to a modem (MSM, e.g., baseband modem) <NUM> that is powered by a power supply <NUM> through a power management integrated circuit (PMIC) <NUM>. The chipset <NUM> also includes capacitors <NUM> and <NUM>, as well as an inductor(s) <NUM> to provide signal integrity. The PMIC <NUM>, the modem <NUM>, the wireless transceiver <NUM>, and the WLAN module <NUM> each include capacitors (e.g., <NUM>, <NUM>, <NUM>, and <NUM>) and operate according to a clock <NUM>. The geometry and arrangement of the various inductor and capacitor components in the chipset <NUM> may reduce the electromagnetic coupling between the components.

<FIG> is a diagram of a diplexer <NUM> according to an aspect of the present disclosure. The diplexer <NUM> includes a high band (HB) input port <NUM>, a low band (LB) input port <NUM>, and an antenna <NUM>. A high band path of the diplexer <NUM> includes a high band antenna switch <NUM>-<NUM>. A low band path of the diplexer <NUM> includes a low band antenna switch <NUM>-<NUM>. A wireless device including an RF front end module may use the antenna switches <NUM> and the diplexer <NUM> to enable a wide range band for an RF input and an RF output of the wireless device. In addition, the antenna <NUM> may be a multiple input, multiple output (MIMO) antenna. Multiple input, multiple output antennas will be widely used for the RF front end of wireless devices to support features such as carrier aggregation.

<FIG> is a diagram of an RF front end module <NUM> according to an aspect of the present disclosure. The RF front end module <NUM> includes the antenna switch (ASW) <NUM> and diplexer <NUM> (or triplexer) to enable the wide range band noted in <FIG>. In addition, the RF front end module <NUM> includes filters <NUM>, an RF switch <NUM> and power amplifiers <NUM> supported by a substrate <NUM>. The filters <NUM> may include various LC filters, having inductors (L) and capacitors (C) arranged along the substrate <NUM> for forming a diplexer, a triplexer, low pass filters, balun filters, and/or notch filters to prevent high order harmonics in the RF front end module <NUM>. The diplexer <NUM> may be implemented as a surface mount device (SMD) on a system board <NUM> (e.g., printed circuit board (PCB) or package substrate). Alternatively, the diplexer <NUM> may be implemented on the substrate <NUM>.

In this configuration, the RF front end module <NUM> is implemented using silicon on insulator (SOI) technology, which helps reduce high order harmonics in the RF front end module <NUM>. SOI technology replaces conventional silicon substrates with a layered silicon-insulator-silicon substrate to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional silicon-built devices because the silicon junction is above an electrical insulator, typically a buried oxide (BOX) layer. A reduced thickness BOX layer, however, may not sufficiently reduce the parasitic capacitance caused by the proximity between an active device (on the silicon layer) and a substrate supporting the BOX layer. As a result, aspects of the present disclosure include a layer transfer process to further separate the active device from the substrate, as shown in <FIG>.

<FIG> show cross-sectional views of an integrated radio frequency (RF) circuit structure <NUM> during a layer transfer process according to aspects of the present disclosure. As shown in <FIG>, an RF silicon on insulator (SOI) device includes an active device <NUM> on a buried oxide (BOX) layer <NUM> supported by a sacrificial substrate <NUM> (e.g., a bulk wafer). The RF SOI device also includes interconnects <NUM> coupled to the active device <NUM> within a first dielectric layer <NUM>. As shown in <FIG>, a handle substrate <NUM> is bonded to the first dielectric layer <NUM> of the RF SOI device. In addition, the sacrificial substrate <NUM> is removed. Removal of the sacrificial substrate <NUM> using the layer transfer process enables high-performance, low-parasitic RF devices by increasing the dielectric thickness. That is, a parasitic capacitance of the RF SOI device is proportional to the dielectric thickness, which determines the distance between the active device <NUM> and the handle substrate <NUM>.

As shown in <FIG>, the RF SOI device is flipped once the handle substrate <NUM> is secured and the sacrificial substrate <NUM> is removed. As shown in <FIG>, a post layer transfer metallization process is performed using, for example, a regular complementary metal oxide semiconductor (CMOS) process. As shown in <FIG>, an integrated RF circuit structure <NUM> is completed by depositing a passivation layer, opening bond pads, depositing a redistribution layer, and forming conductive bumps/pillars to enable bonding of the integrated RF circuit structure <NUM> to a system board (e.g., a printed circuit board (PCB)).

Referring again to <FIG>, the RF SOI device may include a trap rich layer between the sacrificial substrate <NUM> and the BOX layer <NUM>. In addition, the sacrificial substrate <NUM> may be replaced with the handle substrate, and a thickness of the BOX layer <NUM> may be increased to improve harmonics. Although this arrangement of the RF SOI device may provide improved harmonics relative to a pure silicon or SOI implementation, the RF SOI device is limited by the non-linear responses from the handle substrate, especially when a silicon handle substrate is used. That is, in <FIG>, the increased thickness of the BOX layer <NUM> does not provide sufficient distance between the active device <NUM> and the sacrificial substrate <NUM> relative to the configurations shown in <FIG>. Moreover, a body of the active device <NUM> in the RF SOI device may not be tied.

<FIG> is a cross-sectional view of an integrated RF circuit structure <NUM> fabricated using a layer transfer process according to unclaimed aspects of the present disclosure. Representatively, the integrated RF circuit structure <NUM> includes an active device <NUM> having a gate, a body, and source/drain regions formed on an isolation layer <NUM>. In silicon on insulator (SOI) implementations, the isolation layer <NUM> is a buried oxide (BOX) layer, and the body and source/drain regions are formed from an SOI layer including shallow trench isolation (STI) regions supported by the BOX layer.

The integrated RF circuit structure <NUM> also includes middle-end-of-line (MEOL)/back-end-of-line (BEOL) interconnects coupled to the source/drain regions of the active device <NUM>. As described herein, the MEOL/BEOL layers are referred to as front-side layers. By contrast, the layers supporting the isolation layer <NUM> may be referred to herein as backside layers. According to this nomenclature, a front-side interconnect <NUM> is coupled to the source/drain regions of the active device <NUM> through front-side contact <NUM>, and arranged in a front-side dielectric layer <NUM>. In addition, a handle substrate <NUM> is directly coupled to the front-side dielectric layer <NUM>. In this configuration, a backside dielectric <NUM> is adjacent to and possibly supports the isolation layer <NUM>. In addition, a backside metallization <NUM> is coupled to the front-side interconnect <NUM>.

As shown in <FIG>, a layer transfer process provides increased separation between the active device <NUM> and the handle substrate <NUM> to improve the harmonics of the integrated RF circuit structure <NUM>. While the layer transfer process enables high-performance, low-parasitic RF devices, the integrated RF circuit structure <NUM> may suffer from the floating body effect. Accordingly, the performance of the integrated RF circuit structure <NUM> may be further improved by using a post transfer metallization to provide access to a backside of the active device <NUM> to tie the body region of the active device <NUM>.

Various aspects of the disclosure provide techniques for a post layer transfer deposition/growth process on a backside of active devices of an integrated radio frequency (RF) integrated structure. By contrast, access to active devices, formed during a front-end-of-line (FEOL) process, is conventionally provided during middle-end-of-line (MEOL) processing that provides contacts between the gates and source/drain regions of the active devices and back-end-of-line (BEOL) interconnect layers (e.g., M1, M2, etc.). Aspects of the present disclosure involve a post layer transfer growth/deposition process for forming backside extended (raised) source/drain/body regions of transistors that may be used as antenna switch transistors in integrated radio frequency (RF) circuit structures for high quality (Q)-factor RF applications. Other applications include an active device in a low power amplifier module, a low noise amplifier, and an antenna diversity switch.

<FIG> is a cross-sectional view of an integrated circuit structure <NUM>, in which a post-layer transfer process is performed on a backside of source/drain (S/D) regions of an active device (e.g., a transistor) according to unclaimed aspects of the present
disclosure. Representatively, the integrated circuit structure <NUM> includes an active device <NUM> having a gate, a body, and source/drain (S/D) regions formed on an isolation layer <NUM>. The isolation layer <NUM> may be a buried oxide (BOX) layer for silicon on insulator (SOI) implementation, in which the body and source/drain regions are formed from an SOI layer. In this configuration, shallow trench isolation (STI) regions are also supported by the BOX layer.

The integrated RF circuit structure <NUM> includes a front-side metallization <NUM> (e.g., a first BEOL interconnect (M1)) arranged in a front-side dielectric layer <NUM>. The front-side metallization is coupled to a third portion <NUM>-<NUM> of a backside metallization <NUM> through a via <NUM>, in which the backside metallization <NUM> is arranged in a backside dielectric layer <NUM>. In addition, the gate of the active device <NUM> includes a gate contact <NUM>, which may be composed of a front-side silicide layer. In addition, a handle substrate <NUM> is coupled to the front-side dielectric layer <NUM>. The backside dielectric layer <NUM> is adjacent to and possibly supports the isolation layer <NUM>. In this configuration, a post layer transfer metallization process forms the backside metallization <NUM>.

In aspects of the present disclosure, a post layer transfer process is used to provide a backside semiconductor layer on a backside of the source/drain regions of the active device <NUM>. In aspects of the present disclosure, the backside semiconductor layer may be deposited as an amorphous semiconductor layer. Alternatively, the backside semiconductor layer may be epitaxially grown as part of a post layer transfer growth process. Once formed, the backside semiconductor layer may be optionally subjected to a post deposition anneal process (e.g., a low temperature or a short local, laser anneal) to form raised source/drain (S/D) regions <NUM>. In this configuration, the backside raised source/drain regions <NUM> extend from a backside of the source/drain regions of the active device <NUM> into the isolation layer <NUM>. Once formed, a backside contact <NUM> (e.g., a backside silicide layer) may be deposited on the backside raised source/drain regions <NUM> distal from a front-side of the source/drain regions. A post-layer transfer metallization process is then performed to couple a first portion <NUM>-<NUM> and a second portion <NUM>-<NUM> of the backside metallization <NUM> to the backside contacts <NUM> of the backside raised source/drain regions <NUM> of the active device <NUM>. As shown in <FIG>, the front-side metallization <NUM> is arranged distal from the backside metallization <NUM>.

<FIG> is a cross-sectional view of an integrated circuit structure <NUM>, in which a post-layer transfer process is also performed on a backside of a source/drain (S/D) region <NUM> of an active device <NUM> (e.g., a transistor) according to unclaimed aspects of the present disclosure. As will be recognized, a configuration of the integrated circuit structure <NUM> is similar to the configuration of the integrated circuit structure <NUM> of <FIG>. In the configuration shown in <FIG>, however, the active device <NUM> includes only one of the backside raised source/drain regions <NUM>. Instead, a backside contact <NUM> is directly on a backside of the source/drain region <NUM> of the active device <NUM>. In addition, the second portion <NUM>-<NUM> of the backside metallization <NUM> is coupled to the backside contact <NUM> of the source/drain region <NUM> of the active device <NUM>.

Referring again to <FIG>, the backside raised source/drain regions <NUM> are provided in the isolation layer <NUM> and arranged to enable contact with the backside metallization <NUM>. The extension of the source/drain regions of the active device <NUM> helps prevent the formation of parasitic capacitance between the body of the active device <NUM> and conventional front-side raised source/drain regions. In this configuration, the post-layer transfer process may include a post-layer deposition process or a post-layer growth process for forming the backside raised source/drain regions <NUM>. In this configuration, the backside raised source/drain regions <NUM> may reduce the parasitic capacitance associated with raised source/drain regions fabricated using conventional CMOS processes.

According to aspects of the present disclosure, the handle substrate <NUM> may be composed of a semiconductor material, such as silicon. In this configuration, the handle substrate <NUM> may include at least one other active device. Alternatively, the handle substrate <NUM> may be a passive substrate to further improve harmonics by reducing parasitic capacitance. In this configuration, the handle substrate <NUM> may include at least one other passive device. As described herein, the term "passive substrate" may refer to a substrate of a diced wafer or panel, or may refer to the substrate of a wafer/panel that is not diced. In one configuration, the passive substrate is comprised of glass, air, quartz, sapphire, high-resistivity silicon, or other like passive material. The passive substrate may also be a coreless substrate.

<FIG> are cross-sectional views illustrating a process for fabrication of an integrated circuit structure, including backside extended source/drain regions, according to unclaimed aspects of the present disclosure. As shown in <FIG>, an integrated circuit structure <NUM> is shown in a configuration similar to the configuration of the integrated circuit structure <NUM> shown in <FIG>. In the configuration shown in <FIG>, however, a layer transfer process is performed to bond the handle substrate <NUM> to the front-side dielectric layer <NUM> following formation of the active devices <NUM> (<NUM>-<NUM>, and <NUM>-<NUM>). As shown in <FIG>, a post-layer transfer process begins with the deposition of a backside dielectric layer <NUM>. Although a single layer is shown, it should be recognized that multiple dielectric layers may be deposited.

As shown in <FIG>, the post-layer transfer process continues with patterning and etching of the backside dielectric layer <NUM> and the isolation layer <NUM> to expose a backside of the source/drain regions of the active devices <NUM>. In <FIG>, a post-layer transfer deposition/growth process is performed to fabricate the backside raised source/drain regions <NUM>. In <FIG>, a post-layer transfer metallization process is performed to couple the backside metallization <NUM> to the backside raised source/drain regions <NUM> through the backside contacts <NUM>. In addition, a fifth portion <NUM>-<NUM> of the backside metallization <NUM> is coupled to the front-side metallization <NUM> through the via <NUM>. In this configuration, a third portion <NUM>-<NUM> of the backside metallization <NUM> is coupled to the backside contact <NUM> of one of the backside raised source/drain regions <NUM>, and a fourth portion <NUM>-<NUM> of the backside metallization <NUM> is coupled to the backside contact <NUM> of one of the backside raised source/drain regions <NUM> of a second active device <NUM>-<NUM>.

Different materials can be used in the growth process to stress the active devices. For example, PFET devices can be stressed with Germanium growth, up to <NUM>% in one configuration. NMOS devices can be stressed using, for example, carbondoped silicon, with the percentage of carbon being no more than <NUM>% to four percent. This percentage of carbon prevents dislocations in the silicon. It should be recognized that a raised body region can also include stressors.

<FIG> are cross-sectional views illustrating a process for fabrication of an integrated circuit structure, including backside extended source/drain/body regions according to the claimed invention. As shown in <FIG>, an integrated circuit structure <NUM> is shown in a configuration similar to the configuration of the integrated circuit structure <NUM> shown in <FIG>. In the configuration shown in <FIG>, however, a layer transfer process is performed to bond the handle substrate <NUM> to the front-side dielectric layer <NUM> following formation of the active devices <NUM> (<NUM>-<NUM>, and <NUM>-<NUM>). In addition, a first portion <NUM>-<NUM> of the front-side metallization <NUM> couples a front-side contact <NUM> of a source/drain region of a first active device <NUM>-<NUM> to a gate contact <NUM> of a second active device <NUM>-<NUM>. Also, a second portion <NUM>-<NUM> of the front-side metallization <NUM> couples a front-side contact <NUM> of the source/drain region of the second active device <NUM>-<NUM> to the via <NUM>.

As shown in <FIG>, the post-layer transfer process also begins with the deposition of the backside dielectric layer <NUM>. As shown in <FIG>, the post-layer transfer process also continues with patterning and etching of the backside dielectric layer <NUM> and the isolation layer <NUM> to expose a backside of the source/drain region of the first active device <NUM>-<NUM>. In this aspect of the present disclosure, the post layer transfer process exposes a body of the second active device <NUM>-<NUM>. In <FIG>, a post-layer transfer deposition/growth process is performed to fabricate a backside raised source/drain region <NUM> and a backside raised body region <NUM>.

In <FIG>, a post-layer transfer metallization process is performed to couple the backside metallization <NUM> to the backside raised source/drain regions <NUM> through the backside contacts <NUM>. In addition, a fourth portion <NUM>-<NUM> of the backside metallization <NUM> is coupled to the second portion of front-side metallization <NUM> through the via <NUM>. In this configuration, a third portion <NUM>-<NUM> of the backside metallization <NUM> is coupled to a backside contact <NUM> of the backside raised body region <NUM>. In this aspect of the present disclosure, the backside raised body region <NUM> is doped with a different dopant than the dopant of the backside raised source/drain regions <NUM>. In addition, the backside raised body region <NUM> of the first active device <NUM>-<NUM> is doped with a different dopant than the dopant of the backside raised body region <NUM> of the second active device <NUM>-<NUM>.

<FIG> are cross-sectional views illustrating a process for self-alignment between the source/drain/body regions of an active device and the backside extended source/drain/body regions of the active device according to unclaimed aspects of the present disclosure. As shown in <FIG>, an integrated circuit structure <NUM> is shown in a configuration similar to the configuration of the integrated circuit structure <NUM> shown in <FIG>. In the configuration shown in <FIG>, however, the layer transfer process to bond the handle substrate <NUM> to the front-side dielectric layer <NUM> following formation of the active devices <NUM> (<NUM>-<NUM>, and <NUM>-<NUM>) is not shown. In addition, the configuration of the integrated circuit structure shown in <FIG> also includes the first portion <NUM>-<NUM> of the front-side metallization <NUM> coupling the front-side contact <NUM> of the source/drain region of the first active device <NUM>-<NUM> to the gate contact <NUM> of the second active device <NUM>-<NUM>. Also, the second portion <NUM>-<NUM> of the front-side metallization <NUM> couples the front-side contact <NUM> of the source/drain region of the second active device <NUM>-<NUM> to the via <NUM>.

As shown in <FIG>, an ion implant process is performed to implant impurities into the backside dielectric layer <NUM> by implanting ions in the backside dielectric layer <NUM> and the isolation layer <NUM>. The implanting is performed from a front-side of the integrated circuit structure <NUM>. Specific dopants, e.g., high dose Boron, can be used to damage (create defects in) the buried oxide layer. As shown in <FIG>, the ion implant process is blocked by the gates of the active devices <NUM>. As a result, the implanted defects are generally confined to areas within the backside dielectric layer <NUM> and the isolation layer that are proximate to the source/drain regions of the active devices <NUM>.

As shown in <FIG>, a post-layer transfer mask process is performed by depositing a photoresist <NUM> and exposing the implanted defects within, for example, an under etched semiconductor (e.g., silicon (Si)) layer. As shown in <FIG>, the process continues with etching of the backside dielectric layer <NUM> and the isolation layer <NUM> to expose a backside of the source/drain region of the first active device <NUM>-<NUM> and a backside of the source/drain regions of the second active device <NUM>-<NUM>. In this aspect of the present disclosure, the implanted defects enable self-alignment between the source/drain/body regions of the active devices <NUM> and the backside extended source/drain/body regions. That is, the backside etching does not reach the gates. Alternatively, the implanted defects may provide an etch stop layer and reduce an etch rate to support the backside raised source/drain/body regions.

<FIG> is a process flow diagram illustrating a method <NUM> of constructing an integrated circuit structure, including an active device having backside extended source/drain/body regions, according to an aspect of the present disclosure. In block <NUM>, a transistor is fabricated using a front-side semiconductor layer supported by an isolation layer. For example, as shown in <FIG>, the active device <NUM> is fabricated using a front-side semiconductor layer (e.g., a silicon on insulator (SOI) layer) supported by an isolation layer (e.g., a buried oxide (BOX) layer). In the configuration shown in <FIG>, a front-side metallization is fabricated in a front-side dielectric layer on the active device. For example, as shown in <FIG>, a front-side metallization <NUM> is coupled to a front-side via <NUM> that extends through a shallow trench isolation (STI) region and an isolation layer <NUM>. This portion of the process for fabricating the transistor is performed prior to a layer transfer process.

For example, a layer transfer process is performed, in which a handle substrate <NUM> is bonded to a front-side dielectric layer <NUM>, as shown in <FIG>. The layer transfer process also includes removal of a sacrificial substrate. As shown in <FIG>, the layer-transfer process includes removal of the sacrificial substrate <NUM>. In this aspect of the present disclosure, fabrication of raised backside source/drain/body regions is performed as part of a post layer-transfer process.

Referring again to <FIG>, in block <NUM>, a backside of a first source/drain/body region of the transistor is exposed. For example, as shown in <FIG>, a post-layer transfer raised source/drain/body formation process may begin with deposition of a backside dielectric layer <NUM> on the isolation layer <NUM>. As shown in <FIG>, a backside of the source/drain regions of the active devices <NUM> are exposed. In block <NUM>, a raised source/drain/body region is fabricated. For example, as shown 6D, raised source/drain (S/D) regions are coupled to a backside of the source/drain regions of the active device <NUM>. The raised source/drain regions may extend from the backside of the source/drain regions toward the backside dielectric layer <NUM> supporting the isolation layer <NUM>. Alternatively, a backside a of second source/drain/body region may be exposed to enable formation of another raised source/drain/body region.

According to aspects of the present disclosure, the raised source/drain/body regions may be epitaxially grown or fabricated as part of an amorphous deposition process. For example, as shown in <FIG>, an epitaxial growth process may include selectively growing a backside semiconductor layer on an exposed backside of the raised source/drain regions of the active devices <NUM>. This epitaxial growth process also includes subjecting the backside semiconductor layer to an anneal process to form the raised source/drain regions. Once the raised source/drain regions are formed, etching of a surface of the backside dielectric layer <NUM> and/or the raised source/drain regions of the active devices <NUM> is performed. By providing backside raised source/drain regions that extend away from a front-side of the integrated circuit structure <NUM>, parasitic capacitance between the transistor gate and conventional raised source/drain regions is avoided.

According to aspects of the present disclosure, a post-layer transfer growth/deposition process is described for formation of the backside raised source/drain/body regions. The post-layer transfer growth process may involve a preclean portion, a growth portion, and a post-deposition anneal. The post-deposition anneal may be a low temperature anneal (e.g., below <NUM>°) or a short-local laser anneal. In addition, the backside raised source/drain/body region may or may not be of a single crystal structure. For example, the backside raised source/drain/body region may be formed by a fully amorphous deposition followed by solid phase epitaxy anneal to form a single crystal structure. Alternatively, in cases when a mono crystalline material is not desired, poly silicon, a silicon alloy, or other like semiconductor compound can be deposited to provide the backside semiconductor layer.

When an epitaxial growth process is used to form the backside semiconductor layer, a low temperature epitaxial growth may be performed using trisilane. Trisilane may permit the growth of a backside semiconductor layer (e.g., silicon) at lower temperatures below <NUM>° C due to a specific growth mechanism for enhancing H (hydrogen) desorption. By contrast, conventional semiconductor layers grown at temperatures lower than <NUM>° C are defective, irrespective of the carrier gas, pressure and precursor flow used. In addition, a thickness of the epitaxially grown backside semiconductor layer may be higher or lower than the surface of a wafer on which the layer is grown.

In block <NUM> of <FIG>, a backside metallization is fabricated to couple to the raised source/drain regions. As shown in <FIG>, a backside contact <NUM> is deposited on the backside raised source/drain regions <NUM>. In addition, a second backside dielectric layer <NUM>-<NUM> is deposited on the backside contact <NUM> and a first backside dielectric layer <NUM>-<NUM>. Once deposited, the second backside dielectric layer <NUM>-<NUM> is patterned according to the backside contact <NUM>. The second backside dielectric layer <NUM>-<NUM> is next etched (e.g., a dry plasma etch and clean process) to expose a portion of the backside contact <NUM>. A backside metallization <NUM> is then deposited on the exposed portion of the backside contact <NUM> to contact the source/drain regions of the active devices <NUM>.

According to a further unclaimed aspect of the present disclosure, an integrated circuit structure including a transistor on a front-side semiconductor layer supported by an isolation layer is described. The transistor includes a first source/drain/body region. The integrated circuit structure may also include a means for extending a backside of the first source/drain/body region of the transistor from the isolation layer toward a backside dielectric layer supporting the isolation layer. The integrated circuit structure may further include a backside metallization coupled to the backside of first source/drain/body region through the extending means. The extending means may be the raised source/drain region, shown in <FIG> and <FIG>. The extending means may also be the raised body region, shown in <FIG> and <FIG>. In another aspect, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

Unfortunately, successful fabrication of transistors using silicon on insulator (SOI) technology may involve the use of raised source/drain regions. Conventionally, a raised source/drain enables contact between the raised source/drain region and subsequent metallization layers. In addition, a raised source/drain region provides a channel for carriers to travel. Unfortunately, conventional transistors with raised source/drain regions generally suffer from the raised source/drain region problem. In addition, conventional CMOS technology is limited to epitaxial growth on the front-side of the active devices. As a result, aspects of the present disclosure include a post-layer transfer process to enable backside semiconductor deposition/growth to eliminate the raised source/drain region problem.

Aspects of the present disclosure describe integrated circuit structures including transistors having backside raised source/drain/body regions that may be used as antenna switch transistors in integrated radio frequency (RF) circuit structures for high quality (Q)-factor RF applications. In one configuration, a post layer-transfer metallization is used to form the backside raised source/drain/body regions of a transistor. The post-layer transfer process may form a backside semiconductor layer on a backside of the source/drain regions of a transistor. The backside semiconductor layer may extend from a first surface to a second surface of an isolation layer, in which a first surface of the isolation layer supports the transistor.

In this configuration, the post-layer transfer process may include a post-layer deposition process or a post-layer growth process for forming the backside semiconductor layers on the backside of the source/drain regions of the transistor. A subsequent anneal process is applied to the semiconductor layers to form backside raised source/drain regions of the transistor. In this unclaimed configuration, the backside raised source/drain regions of the transistor may reduce the parasitic capacitance associated with front-side raised source/drain regions fabricated using conventional CMOS processes. That is, extension of the source/drain regions into a backside of the transistor helps prevent the formation of parasitic capacitance between the body of the transistor and conventional front-side raised source/drain regions.

<FIG> is a block diagram showing an exemplary wireless communication system <NUM> in which an aspect of the disclosure may be advantageously employed. For purposes of illustration, <FIG> shows three remote units <NUM>, <NUM>, and <NUM> and two base stations <NUM>. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units <NUM>, <NUM>, and <NUM> include IC devices 1025A, 1025C, and 1025B that include the disclosed backside semiconductor growth. It will be recognized that other devices may also include the disclosed backside semiconductor growth, such as the base stations, switching devices, and network equipment. <FIG> shows forward link signals <NUM> from the base station <NUM> to the remote units <NUM>, <NUM>, and <NUM> and reverse link signals <NUM> from the remote units <NUM>, <NUM>, and <NUM> to base stations <NUM>.

In <FIG>, remote unit <NUM> is shown as a mobile telephone, remote unit <NUM> is shown as a portable computer, and remote unit <NUM> is shown as a fixed location remote unit in a wireless local loop system. For example, a remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit such as a personal digital assistant (PDA), a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit such as a meter reading equipment, or other communications device that stores or retrieve data or computer instructions, or combinations thereof. Although <FIG> illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed RF devices.

<FIG> is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the RF devices disclosed above. A design workstation <NUM> includes a hard disk <NUM> containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation <NUM> also includes a display <NUM> to facilitate design of a circuit <NUM> or a semiconductor component <NUM> such as an RF device. A storage medium <NUM> is provided for tangibly storing the circuit design <NUM> or the semiconductor component <NUM>. The circuit design <NUM> or the semiconductor component <NUM> may be stored on the storage medium <NUM> in a file format such as GDSII or GERBER. The storage medium <NUM> may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation <NUM> includes a drive apparatus <NUM> for accepting input from or writing output to the storage medium <NUM>.

Data recorded on the storage medium <NUM> may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium <NUM> facilitates the design of the circuit design <NUM> or the semiconductor component <NUM> by decreasing the number of processes for designing semiconductor wafers.

For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to types of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

Claim 1:
An integrated circuit structure, comprising:
a transistor (<NUM>-<NUM>) in a semiconductor layer (<NUM>), the transistor (<NUM>-<NUM>) overlaying an oxide layer (<NUM>), the transistor (<NUM>-<NUM>) including a first source/drain region and a body region in the semiconductor layer, the body region in contact with the oxide layer (<NUM>) ;
a raised source/drain region (<NUM>) coupled to a backside of the first source/drain region of the transistor, the raised source/drain region (<NUM>) extending from the backside of the first source/drain region of the transistor into the oxide layer (<NUM>) toward a dielectric layer (<NUM>) arranged to support the oxide layer (<NUM>);
a raised body region (<NUM>) coupled to a backside of the body region of the transistor (<NUM>-<NUM>), the raised body region (<NUM>) extending from the backside of the body region (<NUM>) through the oxide layer (<NUM>) and into the dielectric layer (<NUM>), wherein the raised body region (<NUM>) and the raised source/drain region (<NUM>) are separated via the oxide layer (<NUM>); and
a metallization (<NUM>-<NUM>, <NUM>-<NUM>) coupled to the raised source/drain region (<NUM>) and/or the raised body region (<NUM>) of the transistor.