Patent Description:
Neuromorphic processors are specialized computing hardware processors that include a neuron circuit and a synapse circuit. As only an example, the neuron circuit may generate activations or processing results, or signals corresponding to such activations or processing results, with respect to other activations or processing results (or corresponding signals) of the neuron circuit, e.g., in a hierarchical manner to generate an overall result. The synapse circuit may be configured to provide connections between nodes or processing devices (e.g., processing units) of the neuron circuit. Such a neuromorphic processor may be used to drive various neural networks such as convolutional neural networks (CNNs), recurrent neural networks (RNNs), and feedforward neural networks (FNNs), as non-limiting example, and such as in fields of data classification or image recognition, also as non-limiting examples.

<CIT> discloses a neural network circuit and processing scheme. In some embodiments, there is only one synapse calculation circuit, and a memory read out circuit and a selector selectively supply the synapse weight and input value to be used in the synapse calculation. A one bit adder is used to add the one bit multiplication results.

In one general aspect, a neuromorphic apparatus is provided in accordance with claim <NUM>.

Proposed embodiments may thus provide a multi-bit neuromorphic processor core. Embodiments may, for example, be implemented in chip form and mounted on a server, a mobile phone, or a personal computer (PC).

By way of further example, embodiments may be applicable to: event-based image recognition and classification; image recognition and classification using CNN algorithms; and/or recognition and classification of time series information using RNN algorithms.

A neuromorphic processor core according to a proposed embodiment comprises an axon, a synapse, and a neuron. This configuration may be similar to a conventional core structure. A router may be included for implementing the multi-cores. The axon serves as an input stage (or receives an operation result from a neuron of preceding stage as input). The synapse stores a weight (The weight may be stored in a SRAM and other memories). The neuron may perform operations to generate a result value (spike) using a result of the synapse and default settings of the neuron. A difference in structure between the core of conventional technology and the core according to a proposed embodiment is that the core of a proposed embodiment uses a bit adder rather than a bit counter. In addition to the bit adder, a simple latch circuit may be added. Unlike a conventional core, bit addition is performed using a result value of bit AND operation between the axon and the synapse weight without performing the bit counting. Only the bit addition is performed in the structure. However, the time-division technique is used to adjust the order of operations, it is possible to perform a multi-bit multiplication operation by using one bit adder. The multi-bit multiplication is a fundamental basic operation of neural network driving. In a conventional core, it is not possible to perform multi-bit multiplication because the spike and weight resolution was limited to <NUM>-bit.

Further, proposed embodiments perform multi-bit multiplication, which is a core operation of a neural network, without using a multi-bit multiplier, by using only <NUM>-bit information and only one bit adder.

Accordingly, there may be provide an algorithm to perform a multi-bit operation through time-division operations of information of <NUM>-bit resolution. The controller may be further configured to map i and j such that the i-th bit and the j-th bit are combined differently for the different time periods.

The controller may be further configured to sequentially change values of i and j of the i-th bit and the j-th bit in an ascending bit value order.

The total number of combinations of the i-th bit and the j-th bit may correspond to a value obtained by multiplying n by m.

The single axon circuit and the single synaptic circuit may each process a single bit value for the different time periods.

The single neuron circuit includes a single adder configured to perform an addition operation using synaptic operation values output from the single neuron circuit for the different time periods.

The single neuron circuit may be configured to obtain each bit value of the multi-bit neuromorphic operation result using the single adder to perform an addition operation using, as inputs, at least one of a pre-set initial value, a synaptic operation value output from the single synaptic circuit at a previous time period of the different time periods, a synaptic operation value output from the single synaptic circuit at a current time period of the different time periods, an addition value processed by the single adder at a previous time period of the different time periods, and a carry value determined by the single adder at a previous time period of the different time periods.

At least one of an addition value and a carry value output from the single adder may correspond to a value of one of bits of the multi-bit neuromorphic operation result.

The single adder is reused to obtain a value of another one of bits of the multi-bit neuromorphic operation result after a value of one of the bits indicating the multi-bit neuromorphic operation result is obtained.

The single adder may be further configured to perform the addition operation by receiving, as inputs, synaptic operation values corresponding to the same bit positions between intermediate products for obtaining the multi-bit neuromorphic operation result.

The single neuron circuit may be further configured to output a spike when the multi-bit neuromorphic operation result is equal to or greater than a pre-set threshold value, and to determine whether to output a spike by comparing the multi-bit neuromorphic operation result with the pre-set threshold value upon receipt of each bit of the multi-bit neuromorphic operation result.

In another general aspect, a multi-bit neuromorphic operation is provided in accordance with claim <NUM>.

The i and j may be determined such that the i-th bit and the j-th bit are combined differently for each time period of different time periods.

Changing values of i of the i-th bit and j of the j-th bit may be sequentially change in an ascending bit value order.

A total number of combinations of the i-th bit and the j-th bit may correspond to a value obtained by multiplying n by m.

The obtaining includes obtaining the each bit value based on an addition operation of a single adder using synaptic operation values output from the single neuron circuit at different times.

The obtaining may include obtaining the each bit value of the multi-bit neuromorphic operation result using the single adder to perform an addition operation using, as inputs, at least one of a pre-set initial value, a synaptic operation value output from the single synaptic circuit at a previous time period of the different time periods, a synaptic operation value output from the single synaptic circuit at a current time period of the different time periods, an addition value processed by the single adder at a previous time period of the different time periods, and a carry value determined by the single adder at a previous time period of the different time periods.

At least one of an addition value and a carry value output from the single adder may correspond to a value of one of bits indicating the multi-bit neuromorphic operation result.

The obtaining may include obtaining a value of another one of bits indicating the multi-bit neuromorphic operation result after a value of one of the bits indicating the multi-bit neuromorphic operation result is obtained.

The obtaining may further include performing the addition operation by receiving, as inputs of the single adder, synaptic operation values corresponding to the same bit positions between intermediate products for obtaining the multi-bit neuromorphic operation result.

The method may further include determining, by the single neuron circuit, whether to output a spike by comparing the multi-bit neuromorphic operation result with a pre-set threshold value upon receipt of each bit of the multi-bit neuromorphic operation result.

The neuromorphic processor includes a controller. The controller is configured, for each time period of time periods, to sequentially determine: one bit of n-bits to assign to a single axon circuit; one bit of m-bits to assign to a single synaptic circuit configured to output a synaptic operation value as a function of the one bit of n-bits and the one bit of m-bits; and one of each bit value of a multi-bit neuromorphic operation result between the one bit of n-bits and the one bit of m-bits based on the output synaptic operation value for a single neuron circuit. The controller accumulates the multi-bit neuromorphic operation result for each time period of time periods of n-bits and of m-bits in a byte order, and n and m are each a natural number.

The n-bits and m-bits may be stored in an external memory.

A neuromorphic chip may include the neuromorphic processor.

The neuromorphic chip may further include the external memory.

The single neuron circuit may include a single adder and a comparator.

The single adder is configured to receive an initial value as an augend, the synaptic operation value as an addend, and the initial value as a previous carry value during a first time period of time periods.

The single adder is configured to perform an addition operation to output an addition value and a carry value, wherein the addition value corresponds to a least significant bit (LSB) of the multi-bit neuromorphic operation result and the carry value is input as a previous carry value of an addition operation to be performed in a second time period of time periods.

The single adder is further configured to, for the second time period, perform another addition operation to output another addition value and another carry value, wherein the another addition value corresponds to another bit value of the multi-bit neuromorphic operation result and the another carry value is input as another previous carry value of a subsequent addition operation to be performed in a third time period of time periods.

The neuromorphic processor may be included in an electronic device for driving a neural network.

Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood to which this disclosure of this application pertains in the context of and based on an understanding of this disclosure of this application. Terms, such as those defined in commonly used technical dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and consistent with the disclosure of this application, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the specification, when a region is "connected" to another region, the regions may not only be "directly connected," but may also be "electrically connected" via another device therebetween. Also, when a part "includes" or "comprises" an element, unless there is a particular description contrary thereto, the part may further include other elements, not excluding the other elements.

<FIG> is a diagram of an example of a mathematical model <NUM> stimulating an operation of a biological neuron.

A biological neuron may be simulated by the mathematical model <NUM>. The mathematical model <NUM> is an example of a neuromorphic operation that may be simulated by a hardware computational element or processor, and may include a multiplication operation in which a synaptic weight is multiplied with respect to information from a plurality of neurons, an addition operation Σ with respect to values ω<NUM>x<NUM>, ω<NUM>x<NUM>, and ω<NUM>x<NUM> to which the respective synaptic weights are multiplied, and an operation in which a characteristic function bias (b) and an activation function f are applied with respect to an addition operation result. A simulated neuromorphic operation result may be provided via the disclosed neuromorphic operation where values of x<NUM>, x<NUM>, x<NUM>, etc. may correspond to simulated axon values and values of ω<NUM>, ω<NUM>, ω<NUM>, etc. may correspond to simulated synaptic weights. Herein, it is noted that use of the term "may" with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists in which such a feature is included or implemented while all examples and embodiments are not limited to these examples.

<FIG> is a diagram of an example configuration <NUM> of a <NUM>-dimensional (2D) array circuit for performing a neuromorphic operation.

Referring to <FIG>, the configuration <NUM> of the 2D array circuit includes N axon circuits A<NUM> through AN <NUM>, M neuron circuits N<NUM> through NM <NUM>, and NxM synapse arrays S<NUM> through SNM <NUM>, wherein N and M are each an arbitrary natural number. Herein, with respect to examples and descriptions of <FIG>, as well as remaining examples, the Summary, and the claims, the use of the term "neuron" is not meant to mean that the "neuron" has any other meaning beyond a technological meaning, i.e., it is not meant to mean that that the term "neuron" hereinafter is structurally and operatively the same or analogous in hardware and hardware implementation with respect to chemical and neurological neuron implementations. Similarly, with the terms "neuron circuit", "synapse", "synapse circuit", "axon", or "axon circuit" with respect to examples and descriptions of <FIG>, as well as remaining examples, the Summary, and the claims, the use of the term "neuron", "synapse", "axon", or "axon circuit" is not meant to mean that the "neuron", "synapse", "axon", or "axon circuit" have any other meaning beyond a technological meaning, i.e., it is not meant to mean that that the term "neuron", "synapse", "axon", or "axon circuit" hereinafter is structurally and operatively the same or analogous in hardware and hardware implementation with respect to chemical and neurological neuron implementations. For example, an artificial neural network may be hardware that is configured to have multiple layers of hardware nodes, i.e., referred as such "neurons" below.

Each synapse of the synapse arrays S<NUM> through SNM <NUM> may be arranged at intersections of first direction lines extending in a first direction from the axon circuits A<NUM> through AN <NUM> and second direction lines extending in a second direction from the neuron circuits N<NUM> through NM <NUM>. Here, for the convenience of description, the first direction is a row direction and the second direction is a column direction, but the first and second directions are not limited to these examples, and the first direction may be a column direction and the second direction may be a row direction, as a non-limiting example.

Each of the axon circuits A<NUM> through AN <NUM> may receive and transmit an activation (for example, axons a<NUM> through an) to the first direction lines. The activation corresponds to a neurotransmitter transmitted through a neuron and may denote an electric signal input to each of the axon circuits A<NUM> through AN <NUM>. Meanwhile, each of the axon circuits A<NUM> through AN <NUM> may include a memory, register, or buffer for storing input information. Meanwhile, the activation may be binary activation having a binary value. For example, the binary activation may include <NUM>-bit information corresponding to a logic value <NUM> or <NUM>. However, the activation is not limited to these examples, and may have a ternary value or a multi-bit value.

Each of the synapse arrays S<NUM> through SNM <NUM> may store a synaptic weight corresponding to a connection strength between neurons. In <FIG>, for the convenience of description, w<NUM> through wm are illustrated as examples of the synaptic weights to be stored in each synapse, but other synaptic weights may further be stored in each synapse. Each synapse of the synapse arrays S<NUM> through SNM <NUM> may include a memory device for storing the synaptic weight or may be connected to another memory device storing the synaptic weight. Here, such a memory device may be, for example, a memrister.

Each of the synapse arrays S<NUM> through SNM <NUM> may receive an activation input transmitted from each of the axon circuits A<NUM> through AN <NUM> through a corresponding first direction line or may output a result of a neuromorphic operation between the activation input and the stored synaptic weight. For example, the neuromorphic operation between the activation input and the synaptic weight may be a multiplication operation (i.e., AND operation), but is not limited to this example. In other words, the result of the neuromorphic operation between the activation input and the synaptic weight may be a value obtained via another arbitrary suitable operation for reflecting strength or size of activations adjusted based on connection strengths between neurons.

The size or strength of a signal transmitted from the axon circuits A<NUM> through AN <NUM> to the neuron circuits N<NUM> through NM <NUM> may be adjusted according to the neuromorphic operation between the activation input and the synaptic weight. As such, an operation of adjusting the size or strength of a signal transmitted to a next neuron, according to connection strength between neurons, may be implemented using the synapse arrays S<NUM> through SNM <NUM>.

Each of the neuron circuits N<NUM> through NM <NUM> may receive the result of the neuromorphic operation between the activation input and the synaptic weight through a respective second direction line. Each of the neuron circuits N<NUM> through NM <NUM> may determine whether to output a spike based on the result of the neuromorphic operation. For example, each of the neuron circuits N<NUM> through NM <NUM> may output a spike when an accumulated value of the results of the neuromorphic operation is equal to or greater than a pre-set threshold value. The spikes output from the neuron circuits N<NUM> through NM <NUM> may correspond to activation input to axon circuits of a next stage.

The neuron circuits N<NUM> through NM <NUM> are located at the rear end of the synapse arrays S<NUM> through SNM <NUM>, and thus, may be referred to as post-synaptic neuron circuits. The axon circuits A<NUM> through AN <NUM> are located at the front end of the synapse arrays S<NUM> through SNM <NUM>, and thus, may be referred to as pre-synaptic neuron circuits.

<FIG> is a diagram of an example of symbols for describing components of a neuromorphic processor <NUM> in a neuromorphic apparatus.

Referring to <FIG>, the neuromorphic processor <NUM> may include a single axon circuit <NUM>, a single synaptic circuit <NUM>, and a single neuron circuit <NUM>. Here, the single synaptic circuit <NUM> may receive synaptic weights from an NxM synapse memory array <NUM> included in another external memory device.

The configuration of the 2D array (NxM) circuit described with reference to <FIG> may be embodied using the single axon circuit <NUM>, the single synaptic circuit <NUM>, and/or the single neuron circuit <NUM> of <FIG>, for example. The axon circuits A<NUM> through AN <NUM> of <FIG> may correspond to the single axon circuit <NUM>, the synapse arrays S<NUM> through SNM <NUM> correspond to the single synaptic circuit <NUM>, and/or the neuron circuits N<NUM> through NM <NUM> correspond to the single neuron circuit <NUM>, for example.

In order to operate like the axon circuits A<NUM> through AN <NUM> of <FIG>, the single axon circuit <NUM> processes axon inputs in a time-division manner in the neuromorphic processor <NUM>. Also, similarly, in order to operate like the synapse arrays S<NUM> through SNM <NUM> of <FIG>, the single synaptic circuit <NUM> may store synaptic weights in a time-division manner in the neuromorphic processor <NUM>.

For example, the single axon circuit <NUM> may operate as the axon circuit A<NUM> of <FIG> at a time t<NUM>, operate as the axon circuit A<NUM> of <FIG> at a time t<NUM>, so on, and then operate as the axon circuit AN of <FIG> at a time tN. Also, the single synaptic circuit <NUM> may operate as the synapse S<NUM> of <FIG> at a time t<NUM>-<NUM>, operate as the synapse S<NUM> of <FIG> at a time t<NUM>-<NUM>, so on, and then operate as the synapse SNM of <FIG> at a time tN-M. Meanwhile, the single neuron circuit <NUM> may also operate as the neuron circuits N<NUM> through NM <NUM> in the same manner. Here, times are all arbitrary times and are denoted by different reference numerals so as to be distinguishable.

As such, when each of the single axon circuit <NUM>, the single synaptic circuit <NUM>, and the single neuron circuit <NUM> each operate at specific time points or periods in a time-division manner, the neuromorphic processor <NUM> may operate as if a plurality of circuits NxM are operating, even when only a single circuit (1x1) is included. In other words, the configuration <NUM> of the 2D array (NxM) circuit of <FIG> may be embodied as the neuromorphic processor <NUM> of single circuits (1x1) by operating each single circuit in a time-division manner.

<FIG> is a diagram of an example of symbols for describing components of the single neuron circuit <NUM> of the neuromorphic processor <NUM>.

Referring to <FIG>, the single neuron circuit <NUM> of the neuromorphic processor <NUM> may include a single adder <NUM> and a comparator <NUM>.

The single adder <NUM> may denote a combination circuit having three inputs of an augend B<NUM>, an addend B<NUM>, and a previous carry digit C<NUM>, and two outputs of a non-carry sum S<NUM> and a new carry digit C<NUM>. In other words, the single adder <NUM> may correspond to a full adder.

The comparator <NUM> compares an addition result C<NUM>S<NUM> by the single adder <NUM> and a pre-set threshold value. Here, the pre-set threshold value corresponds to a criterion for determining whether to output a spike to a next neuron. When the comparator <NUM> determines that the addition result C<NUM>S<NUM> is equal to or greater than the pre-set threshold value, the single neuron circuit <NUM> may output a spike.

<FIG> is a block diagram of an example of a hardware configuration of a neuromorphic apparatus <NUM>.

Referring to <FIG>, the neuromorphic apparatus <NUM> includes a neuromorphic chip <NUM> on which a neuromorphic processor <NUM> and an on-chip memory <NUM> are mounted, and an external memory <NUM>. The neuromorphic processor <NUM> includes a single axon circuit <NUM>, a single synaptic circuit <NUM>, a single neuron circuit <NUM>, and a controller <NUM>. However, <FIG> only illustrates components of the neuromorphic apparatus <NUM> related to the current example. Thus, example also includes the neuromorphic apparatus <NUM> further including other general-purpose components, such as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a sensor module, and a communication module, in addition to the components shown in <FIG>.

The neuromorphic processor <NUM>, the single axon circuit <NUM>, the single synaptic circuit <NUM>, and the single neuron circuit <NUM> may correspond to the neuromorphic processor <NUM>, the single axon circuit <NUM>, the single synaptic circuit <NUM>, and the single neuron circuit <NUM> of <FIG>, respectively.

The neuromorphic processor <NUM> may include a single processing unit (or single processor core) embodied as the neuromorphic processor <NUM> of <FIG>, but is not limited to this example, and the neuromorphic processor <NUM> may include a plurality of processing units (or processor cores) each embodied as the neuromorphic processor <NUM> of <FIG>.

The neuromorphic apparatus <NUM> may be, or an apparatus included in various types of electronic devices, such as a server device, a mobile device, and an embedded device. The neuromorphic apparatus <NUM> may be, or correspond to a hardware component included in a smart phone, a tablet device, an augmented reality (AR) device, an Internet of Things (IoT) device, an automatic driving vehicle, a robotics, or a medical device, which may perform voice recognition, image recognition, image classification, or the like by using a neural network. In other words, the neuromorphic apparatus <NUM> may be, or correspond to an exclusive hardware (HW) accelerator mounted on such an electronic device, and may be representative of the electronic device, and the neuromorphic apparatus <NUM> may be an HW accelerator operating like a neural processing unit (NPU), a tensor processing unit (TPU), a neural engine, TrueNorth, or Loihi, which are exclusive modules for neural network driving, but noting examples are not limited to these examples.

The neuromorphic chip <NUM> may control overall functions for driving a neural network in the neuromorphic apparatus <NUM>. For example, the neuromorphic processor <NUM> of the neuromorphic chip <NUM> may control the neuromorphic apparatus <NUM> in general by accessing neuromorphic data (for example, axon input values, synaptic weight values, or the like) stored in the external memory <NUM> in the neuromorphic apparatus <NUM> to execute neuromorphic-related programs. The neuromorphic chip <NUM> may drive the neural network according to control of CPU, GPU, AP, or the like provided inside or outside the neuromorphic apparatus <NUM>.

The external memory <NUM> is implemented in hardware and may be used to store various types of neuromorphic data processed in the neuromorphic chip <NUM> including data processed or to be processed by the neuromorphic chip <NUM>. Also, the external memory <NUM> may store applications, drivers, etc. to be driven by the neuromorphic chip <NUM>. The external memory <NUM> may include a random access memory (RAM), such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), CD-ROM, Blue-ray or another optical disk storage, a hard disk drive (HDD), a solid state drive (SSD), or a flash memory.

The on-chip memory <NUM> of the neuromorphic chip <NUM> may read, from the external memory <NUM>, and store (or buffer) neuromorphic data (axon values, synapse values, etc.) for pre-synaptic neuron circuits, and execute the neural network by using the stored neuromorphic data - for example, the NxM synapse memory array <NUM> of <FIG> may correspond to the on-chip memory <NUM>. The on-chip memory <NUM> may store data for post-synaptic neuron circuits, such as spike values, results of neuromorphic operations generated via execution results of the neural network, etc..

Detailed operations and functions of the single axon circuit <NUM>, the single synaptic circuit <NUM>, the single neuron circuit <NUM>, and the controller <NUM> will be described in greater detail below with reference to other drawings.

<FIG> is a diagram of an example describing inputs of each single circuit of the neuromorphic processor <NUM>.

Referring to <FIG>, the controller <NUM> of the neuromorphic processor <NUM> determines a first input of an i-th lower bit of an n-bit axon <NUM> to be assigned to the single axon circuit <NUM> at each time point, and a second input of a j-th lower bit of an m-bit synaptic weight <NUM> to be assigned to the single synaptic circuit <NUM> at each time point. Here, n and m are each a natural number, wherein i is a natural number between <NUM> and n and j is a natural number between <NUM> and m.

In <FIG>, for the convenience of description, the axon <NUM> and the synaptic weight <NUM> each have a value of total <NUM> bits (n=<NUM> and m=<NUM>); however, the axon <NUM> and the synaptic weight <NUM> according to the current example may have values of various bits.

The controller <NUM> determines a bit value of which bit position (i.e., the i-th lower bit) of the <NUM>-bit axon <NUM> (n=<NUM>) is to be assigned to the single axon circuit <NUM> as the first input at which specific time point (for example, a time tx). In other words, the controller <NUM> determines i to determine the first input to be assigned at the time tx. For example, i may have a value from <NUM> to <NUM>. When i is <NUM>, the first input of the first lower bit corresponds to a bit value of a least significant bit (LSB) of the axon <NUM>, and when i is <NUM>, the first input of the third lower bit corresponds to a bit value of a most significant bit (MSB) of the axon <NUM>.

Herein, it is noted that the endianness of the byte order described using MSB and LSB with respect to the examples in this disclosure may be represented in either a big-endian format or little-endian format.

Also, the controller <NUM> determines a bit value of which bit position (i.e., the j-th lower bit) of the <NUM>-bit synaptic weight <NUM> (m=<NUM>) is to be assigned to the single synaptic circuit <NUM> as the second input at which specific time point (for example, a time ty). In other words, the controller <NUM> determines j to determine the second input to be assigned at the time ty. For example, j may have a value from <NUM> to <NUM>. When j is <NUM>, the second input of the first lower bit corresponds to a bit value of LSB of the synaptic weight <NUM>, and when j is <NUM>, the second input of the third lower bit corresponds to a bit value of MSB of the synaptic weight <NUM>.

As such, the controller <NUM> repeatedly determines the first input and the second input to be assigned respectively to the single axon circuit <NUM> and the single synaptic circuit <NUM> by changing the values of i and j at each time point until a multi-bit neuromorphic operation results from the output of the neuromorphic processor <NUM> based on the byte order of lower and upper bit values. The lower bit value denotes a bit value of LSB of the multi-bit neuromorphic operation result and the upper bit value denotes a bit value of MSB of the multi-bit neuromorphic operation result. Meanwhile, the terms first input and second input only denote values of bit positions determined by the controller <NUM>, wherein the values are newly updated by the controller <NUM> at each time point.

The controller <NUM> maps i and j such that the i-th lower bit and the j-th lower bit are differently combined at each time point. For example, the controller <NUM> may change and map the values of i and j such that combinations from a combination of the i-th lower bit (for example, LSB) and the j-th lower bit (for example, LSB) mapped, such that the summation of i and j is smallest to a combination of the i-th lower bit (for example, MSB) to the j-th lower bit (for example, MSB) mapped such that the summation of i and j is largest, are sequentially assigned to each of the single axon circuit <NUM> and the single synaptic circuit <NUM>. Here, the total number of combinations of the i-th lower bit and the j-th lower bit correspond to a value obtained by multiplying n and m, and in the example of <FIG>, total <NUM> (3x3) combinations exist. For example, the controller <NUM> may initially map a bit value (first input) of LSB (i=<NUM>) of the axon <NUM> and a bit value (second input) of LSB (j=<NUM>) of the synaptic weight <NUM> at an initial time, and lastly map a bit value (first input) of MSB (i=<NUM>) of the axon <NUM> and a bit value (second input) of MSB (j=<NUM>) of the synaptic weight <NUM> at a last time.

The single axon circuit <NUM> of the neuromorphic processor <NUM> receives the first input of the i-th lower bit of the n-bit axon <NUM>, which is determined by the controller <NUM>. Also, the single synaptic circuit <NUM> of the neuromorphic processor <NUM> stores the second input of the j-th lower bit of the m-bit synaptic weight <NUM>, which is determined by the controller <NUM>.

Each of the single axon circuit <NUM> and the single synaptic circuit <NUM> is a circuit capable of processing a single bit value (i.e., <NUM> bit value). Accordingly, the single axon circuit <NUM> and the single synaptic circuit <NUM> may be capable of respectively processing only a bit value (first input) of a certain position of the axon <NUM> and a bit value (second input) of a certain position of the synaptic weight <NUM>.

When the second input of the j-th lower bit is stored in the single synaptic circuit <NUM>, the single synaptic circuit <NUM> outputs a synaptic operation value between the first input received from the single axon circuit <NUM> and the second input stored in the single synaptic circuit <NUM>. A synaptic operation performed by the single synaptic circuit <NUM> may be a multiplication operation (i.e., AND operation) of the first and second inputs, but is not limited to these examples.

The single neuron circuit <NUM> of the neuromorphic processor <NUM> obtains each bit value of the multi-bit neuromorphic operation result between the n-bit axon <NUM> and the m-bit synaptic weight <NUM>, based on the synaptic operation value output from the single synaptic circuit <NUM>. This is described in greater detail below with reference to a corresponding drawing.

<FIG> is a diagram of an example describing a multi-bit neuromorphic operation performable by a neuromorphic apparatus.

Referring to <FIG>, as an example of the multi-bit neuromorphic operation, a multi-bit multiplication operation between <NUM>-bit binary values is illustrated. The multi-bit multiplication operation denotes a multiplication operation in which at least one of operands includes a plurality of bits. When a first operand <NUM> of the multi-bit multiplication operation is ABC<NUM> that is a <NUM>-bit binary value, and a second operand <NUM> is DEF<NUM> that is a <NUM>-bit binary value, a multiplication operation of the first operand <NUM> and the second operand <NUM> may be performed by calculating intermediate products via bitwise multiplication, and then adding the calculated intermediate products according to the same bit positions.

For example, GHI that is a first intermediate product <NUM> is obtained by multiplying F that is LSB of DEF<NUM> of the second operand <NUM> and ABC<NUM> of the first operand <NUM>. JKL of a second intermediate product <NUM> is obtained by multiplying E that is a second lower bit of DEF<NUM> and ABC<NUM>. MNO that is a third intermediate product <NUM> is obtained by multiplying D that is a third lower bit (i.e., MSB) of DEF<NUM> and ABC<NUM> that is the first operand <NUM>. Then, the first through third intermediate products <NUM> through <NUM> are added according to the same bit positions to obtain PQRSTU<NUM> that is a multi-bit multiplication operation result <NUM> between the first operand <NUM> and the second operand <NUM>. Hereinafter, a method by which the neuromorphic processor <NUM> of <FIG> described above performs the multi-bit neuromorphic operation (i.e., the multi-bit multiplication operation) of <FIG> is described.

<FIG> is a diagram of an example describing mapping of operands respectively to an axon <NUM> and a synaptic weight <NUM> to perform a multi-bit neuromorphic operation (i.e., a multi-bit multiplication operation).

Referring to <FIG>, each bit value (A, B, and C) of ABC<NUM> that is the first operand <NUM> of <FIG> is mapped to the synaptic weight <NUM>. MSB of the first operand <NUM> is mapped to MSB of the synaptic weight <NUM> and LSB of the first operand <NUM> is mapped to LSB of the synaptic weight <NUM>.

In the same manner, each bit value (D, E, and F) of DEF<NUM> that is the second operand <NUM> of <FIG> is mapped to the axon <NUM>. MSB of the second operand <NUM> is mapped to MSB of the axon <NUM> and LSB of the second operand <NUM> is mapped to LSB of the axon <NUM>.

However, an embodiment is not limited to these examples, and unlike a mapping method described in <FIG>, the first operand <NUM> and the second operand <NUM> of <FIG> may be mapped to bit positions of the axon <NUM> and the synaptic weight <NUM> in a different mapping scheme. However, when other mapping methods are applied, the controller <NUM> may determine combinations of i and j in a manner different from the above to correspond to mapped bit positions.

<FIG> is a diagram of an example describing the neuromorphic processor <NUM> processing operands and intermediate products of a multi-bit neuromorphic operation (i.e., a multi-bit multiplication operation) in a time-division manner.

Referring to <FIG>, as described with reference to <FIG>, each bit value (A, B, and C) of ABC<NUM> that is a first operand <NUM> is mapped to the synaptic weight <NUM> and each bit value (D, E, and F) of DEF<NUM> that is a second operand <NUM> is mapped to the axon <NUM>.

Bit values of each of a first intermediate product GHI <NUM>, a second intermediate product JKL <NUM>, and a third intermediate product MNO <NUM>, which are generated via multiplication of each bit value (A, B, and C) of the first operand ABC<NUM> <NUM> and each bit value (D, E, and F) of the second operand DEF<NUM> <NUM> in a time-division manner. For example, a bit value I of the first intermediate product GHI <NUM> may be obtained at a time t<NUM>, a bit value H of the first intermediate product GHI <NUM> may be obtained at a time t<NUM>, a bit value L of the second intermediate product JKL <NUM> may be obtained at a time t<NUM>, so on, and a bit value M of the third intermediate product MNO <NUM> may be obtained at a time t<NUM>.

The times t<NUM> through t<NUM> denote different times. For example, a time delayed by a pre-set time from the time t<NUM> may be the time t<NUM>, a time delayed by a pre-set time from the time t<NUM> may be the time t<NUM>; however, an embodiment is not necessarily limited to these examples. Also, throughout the specification, a time t is not for limiting a specific moment, but for distinguishing timing or a time section when related operations are performed. Accordingly, after an understanding of the disclosure, one would understand that operations described to be performed at a specific time point in the specification may not be necessarily simultaneously performed.

A result <NUM> of the multi-bit neuromorphic operation (i.e., multi-bit multiplication operation) of the first operand ABC<NUM> <NUM> and the second operand DEF<NUM> <NUM> is PQRSTU<NUM>.

U corresponding to LSB in the result PQRSTU<NUM> <NUM> is obtained via I of the first intermediate product GHI <NUM>. T in the result PQRSTU<NUM> <NUM> is obtained via the summation of H of the first intermediate product GHI <NUM> and L of the second intermediate product JKL <NUM>. S in the result PQRSTU<NUM> <NUM> is obtained via the summation of G of the first intermediate product GHI <NUM>, K of the second intermediate product JKL <NUM>, O of the third intermediate product MNO <NUM>, and a carry value obtained from a previous bit position. As such, the result PQRSTU<NUM> <NUM> may be sequentially obtained from U corresponding to LSB to P corresponding to MSB. In other words, the result PQRSTU<NUM> <NUM> may be obtained based on the summation of bit values of the first through third intermediate products <NUM> through <NUM> sequentially obtained from the time t<NUM> to time t<NUM>.

<FIG> is a diagram of an example describing virtual synapse array mapping for the neuromorphic processor <NUM> to process a multi-bit neuromorphic operation in a time-division manner.

Referring to <FIG>, as described above, the neuromorphic processor <NUM> includes the single axon circuit <NUM>, the single synaptic circuit <NUM>, the single neuron circuit <NUM>, and the controller <NUM>, but when the neuromorphic processor <NUM> operates in a time-division manner, the neuromorphic processor <NUM> may operate as if a 2D synapse array including at least one axon circuit, at least one synapse, and at least one neuron circuit. In the current embodiment, a 2D synapse array simulated to be processed by the neuromorphic processor <NUM> in the time-division manner is referred to as a virtual synapse array <NUM>, but may alternately be referred to by another term. In other words, physical circuit configurations (for example, at least one axon circuit, at least one synapse, and at least one neuron circuit) of the virtual synapse array <NUM> may not actually be realized in the neuromorphic processor <NUM>.

<FIG> illustrates the 3x3 virtual synapse array <NUM> which will be described in relation to the multi-bit neuromorphic operation (<NUM>-bit x <NUM>-bit multiplication operation) described above with reference to <FIG>. However, alternatively, an array including various numbers of rows and columns may be used.

In the 3x3 virtual synapse array <NUM>, the second operand DEF<NUM> <NUM> of <FIG> is mapped to axons a<NUM>, a<NUM>, and a<NUM>, and the first operand ABC<NUM> <NUM> of <FIG> is mapped to synaptic weights w<NUM>, w<NUM>, and w<NUM>. The bit value I of the first intermediate product GHI <NUM> of <FIG> may be obtained when a synapse operation between the axon (bit value a<NUM>=F) and the synaptic weight (bit value w<NUM>=C) is performed in a synapse provided as the axon a<NUM> and the synaptic weight w<NUM> cross each other. Similarly, bit values of the first through third intermediate products <NUM> through <NUM> may be mapped as shown in <FIG> when synapse operations are performed in synapses provided as the axons a<NUM>, a<NUM>, and a<NUM> and the synapse weights w<NUM>, w<NUM>, and w<NUM> cross each other in the 3x3 virtual synapse array <NUM>.

The controller <NUM> determines each of axons and synaptic weights to be provided to the single axon circuit <NUM> and the single synaptic circuit <NUM> such that mapping is performed in the above manner of the virtual synapse array <NUM>.

<FIG> are diagrams of examples describing an order in which synaptic operations are to be performed by the neuromorphic processor <NUM> in a time-division manner to process a multi-bit neuromorphic operation.

Referring to <FIG>, synaptic operations between axons and synaptic weights are performed in synapses at crossing points between axons and synaptic weights of a virtual synapse array <NUM>. The neuromorphic processor <NUM> may perform the synapse operations at the crossing points of the virtual synapse array <NUM> in the time-division manner.

According to the mapping method described above with reference to <FIG> and <FIG>, the neuromorphic processor <NUM> provides the axon a<NUM> to the single axon circuit <NUM> and the synaptic weight w<NUM> to the single synaptic circuit <NUM> at the time t<NUM>, and obtains a synaptic operation value between the axon a<NUM> and the synaptic weight w<NUM>. Then, the neuromorphic processor <NUM> provides the axon a<NUM> to the single axon circuit <NUM> and the synaptic weight w<NUM> to the single synaptic circuit <NUM> at the time t<NUM>, and obtains a synaptic operation value between the axon a<NUM> and the synaptic weight w<NUM>. In a similar manner, the neuromorphic processor <NUM> sequentially performs synapse operations up to the time t<NUM>.

Referring to <FIG>, the order described in <FIG> is indicated by arrows. In this example, the synaptic operations from time t<NUM> to time t<NUM> are sequentially performed in an order corresponding to diagonal directions in the virtual synapse array <NUM>.

Consequently, such an order is based on a method by which the controller <NUM> changes and maps the values of i and j. The values of i and j are mapped from combinations where the summation of i and j is smallest to combinations where the summation of i and j is largest. Such combinations of the i-th lower bit and the j-th lower bit are sequentially assigned to each of the single axon circuit <NUM> and the single synaptic circuit <NUM> as described above.

<FIG> is a diagram for describing an order in which synaptic operations are performed by a general neuromorphic processor. Referring to <FIG>, the general neuromorphic processor is unable to perform a multi-bit neuromorphic operation, but is able to perform only a <NUM>-bit neuromorphic operation (<NUM>-bit x <NUM>-bit multiplication operation). In other words, referring to a virtual synapse array <NUM>, each of axons and each of synaptic weights do not correspond to some bit values of multi-bit operands, but correspond to <NUM>-bit operands themselves. Also, the general neuromorphic processor performs synaptic operations in an order of a column direction shown in <FIG>, and thus a synaptic operation value obtained at the time t<NUM> and a synaptic operation value obtained at the time t<NUM> are independent synaptic operation values irrelevant to each other.

On the other hand, according to the current example, the neuromorphic processor <NUM> assigns some bit values of multi-bit operands to axons and synaptic weights of the virtual synapse array <NUM> and performs synaptic operations in a time-division manner in an order of the diagonal direction of <FIG>, and thus a multi-bit neuromorphic operation is possible unlike the general neuromorphic processor.

<FIG> are diagrams of examples describing processes of a neuromorphic processor performing a multi-bit neuromorphic operation in a time-division manner.

The processes of performing the multi-bit neuromorphic operation are described in <FIG> by using the examples described above with reference to <FIG>.

The single neuron circuit <NUM> of <FIG> of the neuromorphic processor <NUM> of <FIG> obtains each bit value of a multi-bit neuromorphic operation result between an n-bit axon and an m-bit synaptic weight, based on a synaptic operation value output from the single synaptic circuit <NUM> of <FIG>. The single neuron circuit <NUM> includes a single adder <NUM>.

<FIG> illustrates processes at the time t<NUM>.

The controller <NUM> assigns the axon a<NUM> to the single neuron circuit <NUM> and assigns the synaptic weight w<NUM> to the single synaptic circuit <NUM> at the time t<NUM>.

A synapse <NUM> stores the synaptic weight w<NUM>. After the synaptic weight w<NUM> is stored, the synapse <NUM> performs the synapse operation between the axon a<NUM> and the synaptic weight w<NUM> to obtain the synaptic operation value corresponding to the time t<NUM>.

The single adder <NUM> receives a pre-set initial value <NUM> as an augend, receives the synaptic operation value corresponding to the time t<NUM> as an addend, and receives the pre-set initial value <NUM> as a previous carry value. Upon receiving all inputs, the single adder <NUM> performs an addition operation to output an addition value S<NUM> and a carry value C<NUM>. The addition value S<NUM> corresponds to LSB among bits indicating a result of a multi-bit neuromorphic operation (multi-bit multiplication operation). Also, the carry value C<NUM> is input as a previous carry value of an addition operation to be performed next.

<FIG> illustrates processes at times t<NUM> and t<NUM>.

The controller <NUM> assigns the axon a<NUM> to the single neuron circuit <NUM> and assigns the synaptic weight w<NUM> to the single synaptic circuit <NUM> at the time t<NUM>. When the synaptic weight w<NUM> is stored, a synapse <NUM> performs the synapse operation between the axon a<NUM> and the synaptic weight w<NUM> to obtain the synaptic operation value corresponding to the time t<NUM>. The single adder <NUM> receives the carry value C<NUM> the synaptic operation value corresponding to the time t<NUM>.

The controller <NUM> assigns the axon a<NUM> to the single neuron circuit <NUM> and assigns the synaptic weight w<NUM> to the single synaptic circuit <NUM> at the time t<NUM>. When the synaptic weight w<NUM> is stored, a synapse <NUM> performs the synapse operation between the axon a<NUM> and the synaptic weight w<NUM> to obtain the synaptic operation value corresponding to the time t<NUM>.

Upon receiving all inputs of the carry value C<NUM>, the synaptic operation value corresponding to the time t<NUM>, and the synaptic operation value corresponding to the time t<NUM>, the single adder <NUM> outputs an addition value S<NUM> and a carry value C<NUM> by performing an addition value. The addition value S<NUM> corresponds to a bit value of a second lower bit among the bits indicating the result of the multi-bit neuromorphic operation (multi-bit multiplication operation. Also, the carry value C<NUM> is input as a previous carry value of an addition operation to be performed next.

The controller <NUM> assigns the axon a<NUM> to the single neuron circuit <NUM> and assigns the synaptic weight w<NUM> to the single synaptic circuit <NUM> at the time t<NUM>. A synapse <NUM> obtains a synaptic operation value corresponding to the time t<NUM> and the single adder <NUM> receives the carry value C<NUM> the synaptic operation value corresponding to the time t<NUM>.

The controller <NUM> assigns the axon a<NUM> to the single neuron circuit <NUM> and assigns the synaptic weight w<NUM> to the single synaptic circuit <NUM> at the time t<NUM>. A synapse <NUM> obtains a synaptic operation value corresponding to the time t<NUM>.

Upon receiving all inputs of the carry value C<NUM>, the synaptic operation value corresponding to the time t<NUM>, and the synaptic operation value corresponding to the time t<NUM>, the single adder <NUM> outputs an addition value P<NUM> and a carry value C<NUM> by performing an addition value. The addition value P<NUM> is used as an input for performing a next addition operation at the time t<NUM>. Also, the carry value C<NUM> is input as a previous carry value of the addition operation to be performed next.

Upon receiving all inputs of the synaptic operation value corresponding to the time t<NUM>, the addition value P<NUM> obtained previously, and a pre-set carry value <NUM>, the single adder <NUM> outputs an addition value S<NUM> and a carry value C<NUM> by performing an addition value. The addition value S<NUM> corresponds to a bit value of a third lower bit among the bits indicating the result of the multi-bit neuromorphic operation (multi-bit multiplication operation). Also, the carry value C<NUM> is input as a previous carry value of the addition operation to be performed next.

Upon receiving all inputs of the synaptic operation value corresponding to the time t<NUM>, the pre-set initial value <NUM>, and the carry value C<NUM>, the single adder <NUM> outputs an addition value P<NUM> and a carry value C<NUM> by performing an addition value. The addition value P<NUM> is used as an input for the single adder <NUM> to perform a next addition operation at the time t<NUM>. Also, the carry value C<NUM> is input as a previous carry value of the addition operation to be performed next.

Upon receiving all inputs of the synaptic operation value corresponding to the time t<NUM>, the addition value P<NUM> obtained previously, and the carry value C<NUM>, the single adder <NUM> outputs an addition value S<NUM> and a carry value C<NUM> by performing an addition value. The addition value S<NUM> corresponds to a bit value of a fourth lower bit among the bits indicating the result of the multi-bit neuromorphic operation (multi-bit multiplication operation). Also, the carry value C<NUM> is input as a previous carry value of the addition operation to be performed next.

Upon receiving all inputs of the synaptic operation value corresponding to the time t<NUM>, the carry value C<NUM>, and the carry value C<NUM>, the single adder <NUM> outputs an addition value S<NUM> and a carry value S<NUM> by performing an addition value. The addition value S<NUM> and the carry value S<NUM> respectively correspond to bit values of fifth and sixth lower bits among the bits indicating the result of the multi-bit neuromorphic operation (multi-bit multiplication operation).

As described above, the single adder <NUM> included in the single neuron circuit <NUM> is reused at each time point to perform the addition operation. In other words, the single adder <NUM> may perform the addition operation when all inputs are received, and store previous addition operation results (for example, an addition value, a carry value, etc.) in a memory (a buffer, a register, or the like) connected to the single adder <NUM> to perform a next addition operation. The previous addition operation results stored in the memory may be reset and reused before a next addition operation is performed. In other words, since the neuromorphic processor <NUM> according to the current embodiment performs the multi-bit multiplication operation by reusing the single adder <NUM>, a circuit area for realizing the neuromorphic processor <NUM> may be reduced.

<FIG> is a diagram of an example summarizing and describing the processes of <FIG>.

As described above, the controller <NUM> of the neuromorphic processor <NUM> determines, so as to obtain the multi-bit neuromorphic operation result sequentially from a lower bit value to an upper bit value, the first input of the i-th lower bit of the axon <NUM> to be assigned to the single axon circuit <NUM> at each time point (for example, from the time t<NUM> to the time t<NUM>) and the second input of the j-th lower bit of the synaptic weight <NUM> to be assigned to the single synaptic circuit <NUM> at each time point (for example, from the time t<NUM> to the time t<NUM>). When the second input is stored in the single synaptic circuit <NUM>, the single synaptic circuit <NUM> outputs the synaptic operation value between the first input and the second input. The single neuron circuit <NUM> obtains the bit values S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>, and S<NUM> of the multi-bit neuromorphic operation result between the axon <NUM> and the synaptic weight <NUM>, based on the synaptic operation result output from the single synaptic circuit <NUM>. In other words, the neuromorphic processor <NUM> performs a multi-bit multiplication operation of multi-bit operands by adjusting an operation order and an operation time.

Meanwhile, the bit values S<NUM>, S<NUM>, S<NUM>, S<NUM>, S<NUM>, and S<NUM> of the multi-bit neuromorphic operation result correspond to bit values of the multi-bit neuromorphic operation result PQRSTU<NUM> of <FIG>. Also, the synaptic operation value corresponding to each of the times t<NUM> through t<NUM> described with reference to <FIG> correspond to each bit value of the first through third intermediate products <NUM> through <NUM> described with reference to <FIG>.

<FIG> and <FIG> are diagrams of examples describing results of processing a <NUM>-bit x <NUM>-bit multiplication operation by the neuromorphic processor <NUM>.

Referring to <FIG>, a <NUM>-bit multiplication result of <NUM><NUM> may be obtained when a multi-bit multiplication operation of a <NUM>-bit synaptic weight <NUM><NUM> and a <NUM>-bit axon <NUM><NUM> is performed as described above. Referring to <FIG>, a <NUM>-bit multiplication result of <NUM><NUM> may be obtained when a multi-bit multiplication operation of a <NUM>-bit synaptic weight <NUM><NUM> and a <NUM>-bit axon <NUM><NUM> is performed as described above. Referring to <FIG>, a <NUM>-bit multiplication result of <NUM><NUM> may be obtained when a multi-bit multiplication operation of a <NUM>-bit synaptic weight <NUM><NUM> and a <NUM>-bit axon <NUM><NUM> is performed as described above. Referring to <FIG>, a <NUM>-bit multiplication result of <NUM><NUM> may be obtained when a multi-bit multiplication operation of a <NUM>-bit synaptic weight <NUM><NUM> and a <NUM>-bit axon <NUM><NUM> is performed as described above. Referring to <FIG>, a <NUM>-bit multiplication result of <NUM><NUM> may be obtained when a multi-bit multiplication operation of a <NUM>-bit synaptic weight <NUM><NUM> and a <NUM>-bit axon <NUM><NUM> is performed as described above.

In other words, the neuromorphic processor <NUM> performs a multi-bit neuromorphic operation (multi-bit multiplication operation) according to time-division processes and distribution of bit values of axon and synaptic weight described above.

<FIG> is a diagram of an example describing results of processing a <NUM>-bit x <NUM>-bit multiplication operation by the neuromorphic processor <NUM>. Hereinafter, for the convenience of description, a <NUM>-bit x <NUM>-bit multiplication operation is described as an example of the multi-bit neuromorphic operation. However, example exist with the neuromorphic processor <NUM> performing a multiplication operation of other various bits according to time-division processes and distribution of bit values of axon and synaptic weight described above.

Referring to <FIG>, a <NUM>-bit multiplication result of <NUM><NUM> may be obtained when a multi-bit multiplication operation of a <NUM>-bit synaptic weight <NUM><NUM> and a <NUM>-bit axon <NUM><NUM> is performed as described above.

<FIG> is a diagram of an example describing results of processing a <NUM>-bit x <NUM>-bit multiplication operation by the neuromorphic processor <NUM>. Referring to <FIG>, an <NUM>-bit multiplication result of <NUM><NUM> may be obtained when a multi-bit multiplication operation of a <NUM>-bit synaptic weight <NUM><NUM> <IMG> and a <NUM>-bit axon <NUM><NUM> is performed as described above.

Meanwhile, in a neural network, operation precision may vary according to layers and also according to processor cores that process the neural network in parallel. Here, the neuromorphic processor <NUM> according to the current embodiment may process data of various operation precisions required to execute the neural network without having to change the hardware component by performing distribution of bit values of an axon and synaptic weight based on the respective operation precision and scheduling of time-division processes.

<FIG> is a diagram of an example describing hardware resources of the neuromorphic processor <NUM> in comparison with hardware resources of general neuromorphic processors.

Referring to <FIG>, a general neuromorphic processor using the method described with reference to <FIG> performs addition or integration on synaptic operation values received by using a bit counter <NUM> included in a neuron circuit. However, the general neuromorphic processor using the bit counter <NUM> is unable to perform a multi-bit neuromorphic operation (multi-bit multiplication operation). Meanwhile, there is a general neuromorphic processor that uses a multiplier circuit <NUM> included in a neuron circuit for the multi-bit multiplication operation.

However, comparing hardware resources of such general neuromorphic processors with hardware resources of the neuromorphic processor <NUM> according to the current example, unlike the general neuromorphic processors, examples of the neuromorphic processor <NUM> may include those realizing a circuit with a small area by using fewer circuit devices while simultaneously being capable of multi-bit multiplication operations.

<FIG> is a flowchart of an example a method, performed by the neuromorphic apparatus <NUM>, of processing a multi-bit neuromorphic operation. Referring to <FIG>, the method includes operations processed by the neuromorphic apparatus <NUM> described above in time-series. Thus, the details described above are applicable to the method of <FIG>.

In operation <NUM>, the controller <NUM> of the neuromorphic apparatus <NUM> determines the first input of the i-th lower bit of the n-bit axon to be assigned to the single axon circuit <NUM> at each time point, and the second input of the j-th lower bit of the m-bit synaptic weight to be assigned to the single synaptic circuit <NUM> at each time point. Here, the controller <NUM> repeatedly determines the first input and the second input to be assigned at each time point until the multi-bit neuromorphic operation result is obtained sequentially from the lower bit value to the upper bit value.

In operation <NUM>, the single axon circuit <NUM> receives the determined first input.

In operation <NUM>, the single synaptic circuit <NUM> outputs the synaptic operation value between the first input and the second input when the determined second input is stored.

In operation <NUM>, the single neuron circuit <NUM> obtains each bit value of the multi-bit neuromorphic operation result between the axon and the synaptic weight, based on the output synaptic operation value.

<FIG> is a block diagram of an example of a configuration of an example electronic system <NUM> embodiment.

Referring to <FIG>, the electronic system <NUM> may extract valid information by analyzing input data in real-time based on a neural network, and determine a situation based on the extracted valid information or control components of an electronic device on which the electronic system <NUM> is mounted or is representative of. For example, the electronic system <NUM> may be applied to a robot apparatus, such as a drone or an advanced drivers assistance system (ADAS), a smart TV, a smart phone, a medical device, a mobile device, an image display device, a measuring device, or an IoT device, and may be mounted on at least one of various types of electronic devices.

The electronic system <NUM> may include a processor <NUM>, a RAM <NUM>, a neuromorphic apparatus <NUM>, a memory <NUM>, a sensor module <NUM>, and a communication (Tx/Rx) module <NUM>. The electronic system <NUM> may further include an input/output module, a security module, a power control device, etc. At least some of hardware components of the electronic system <NUM> may be mounted on at least one semiconductor chip.

The processor <NUM> controls overall operations of the electronic system <NUM>. The processor <NUM> may include one processor core (single core) or a plurality of processor cores (multi-core). The processor <NUM> may process or execute programs and/or data stored in the memory <NUM>. According to an example, the processor <NUM> may execute the programs stored in the memory <NUM> to control functions of the neuromorphic apparatus <NUM>. The processor <NUM> may be a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP).

The RAM <NUM> may temporarily store programs, data, or instructions. For example, the programs and/or data stored in the memory <NUM> may be temporarily stored in the RAM <NUM> according to control or a booting code of the processor <NUM>. The RAM <NUM> may be realized as a memory, such as DRAM or SRAM.

The neuromorphic apparatus <NUM> may implement a neural network based on received input data and generate an information signal based on a result of implementing the operation. The neural network may include CNN, RNN, FNN, deep belief network, restricted Boltzmann machines, etc., but is not limited to these examples. The neuromorphic apparatus <NUM> may be a neural network-exclusive hardware accelerator or a device including the same, and may include the neuromorphic apparatus <NUM> of <FIG> described above.

The information signal may include one of the various types of recognition signals, such as a voice recognition signal, an object recognition signal, an image recognition signal, a biometric information recognition signal, etc. For example, the neuromorphic apparatus <NUM> may receive frame data included in a video stream as input data, and generate a recognition signal with respect to an object included in an image indicated by the frame data. However, an embodiment is not limited to these examples, and the neuromorphic apparatus <NUM> may receive any type of input data and generate a recognition signal according to the input data, based on a type or function of an electronic apparatus on which the electronic system <NUM> is mounted.

The memory <NUM> is a storage space for storing data, and may store an operating system (OS), various programs, and various types of data. According to an embodiment, the memory <NUM> may store intermediate results generated while during operations of the neuromorphic apparatus <NUM>.

The memory <NUM> may be DRAM, but is not limited to these examples. The memory <NUM> may include at least one of a volatile memory and a nonvolatile memory. Examples of the nonvolatile memory include ROM, PROM, EPROM, EEPROM, a flash memory, PRAM, MRAM, RRAM, and FRAM. Examples of the volatile memory include DRAM, SRAM, SDRAM, PRAM, MRAM, RRAM, and FeRAM. According to an embodiment, the memory <NUM> may include at least one of HDD, SSD, CF, SD, Micro-SD, Mini-SD, xD, and a memory stick.

The sensor module <NUM> may collect surrounding information of the electronic apparatus on which the electronic system <NUM> is mounted. The sensor module <NUM> may sense or receive a signal (for example, an image signal, a voice signal, a magnetic signal, a biometric signal, or a touch signal) from outside the electronic apparatus, and convert the sensed or received signal to data. In this regard, the sensor module <NUM> may include at least one of various types of sensing devices, such as a microphone, an image pickup device, an image sensor, light detection and ranging (LIDAR) sensor, an infrared sensor, an ultrasound sensor, a bio-sensor, and a touch sensor.

The sensor module <NUM> may provide the converted data to the neuromorphic apparatus <NUM> as input data, or in an example is included in the neuromorphic apparatus <NUM>. For example, the sensor module <NUM> may include an image sensor, and may generate a video stream by photographing an external environment of the electronic apparatus and sequentially obtain or provide consecutive data frames of the video stream to the neuromorphic apparatus <NUM> as the input data. However, an embodiment is not limited to these examples, and the sensor module <NUM> may provide various types of data to the neuromorphic apparatus <NUM>.

The Tx/Rx module <NUM> may include various wired or wireless interfaces capable of communicating with an external device. For example, the Tx/Rx module <NUM> may include a local area network (LAN), a wireless LAN (WLAN) such as wireless fidelity (Wi-Fi), a wireless personal area network (WPAN) such as Bluetooth, and communication interfaces capable of accessing a mobile cellular network, such as wireless universal serial bus (USB), ZigBee, near field communication (NFC), radiofrequency identification (RFID), power line communication (PLC), <NUM>rd generation (<NUM>), <NUM>th generation (<NUM>), or long-term evolution (LTE).

The neuromorphic processors, neuromorphic processors <NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>, the processor <NUM>, the RAM <NUM>, the neural network device <NUM>, the memory <NUM>, the sensor module <NUM>, and the Tx/Rx module <NUM> in <FIG> that perform the operations described in this application are implemented by hardware components configured to perform the operations described in this application that are performed by the hardware components. Examples of hardware components that may be used to perform the operations described in this application where appropriate include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer may be implemented by one or more processing elements, such as an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field-programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices that is configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, a processor or computer includes, or is connected to, one or more memories storing instructions or software that are executed by the processor or computer. Hardware components implemented by a processor or computer may execute instructions or software, such as an operating system (OS) and one or more software applications that run on the OS, to perform the operations described in this application. The hardware components may also access, manipulate, process, create, and store data in response to execution of the instructions or software. For simplicity, the singular term "processor" or "computer" may be used in the description of the examples described in this application, but in other examples multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller, may implement a single hardware component, or two or more hardware components. A hardware component may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single-instruction single-data (SISD) multiprocessing, single-instruction multiple-data (SIMD) multiprocessing, multiple-instruction single-data (MISD) multiprocessing, and multiple-instruction multiple-data (MIMD) multiprocessing.

The method illustrated in <FIG> that performs the operations described in this application is performed by computing hardware, for example, by one or more processors or computers, implemented as described above executing instructions or software to perform the operations described in this application that are performed by the method.

Claim 1:
A neuromorphic apparatus (<NUM>) configured to process a multi-bit neuromorphic operation, wherein the multi-bit neuromorphic operation is a multi-bit multiplication, the neuromorphic apparatus comprising:
a single axon circuit (<NUM>) configured to receive, as a first input, an i-th bit of an n-bit axon (<NUM>);
a single synaptic circuit (<NUM>) configured to store, as a second input, a j-th bit of an m-bit synaptic weight (<NUM>) and output a synaptic operation value between the first input and the second input, wherein the output synaptic operation value corresponds to a result of a multiplication operation of the first and second inputs;
a single neuron circuit (<NUM>) configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value, wherein the single neuron circuit (<NUM>) comprises a single adder (<NUM>) configured to perform an addition operation using synaptic operation values output from the single neuron circuit (<NUM>) for the different time periods, and wherein the adder is configured to receive an input carry value and is configured to output an output carry value; and
a controller (<NUM>) configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit (<NUM>) and the single synaptic circuit (<NUM>), to obtain the multi-bit neuromorphic operation result (<NUM>) in the order starting from a lower bit value to an upper bit value,
wherein n and m are each a natural number, i is a natural number between <NUM> and n, and j is a natural number between <NUM> and m,
wherein the controller (<NUM>) is further configured to determine the first input and the second input that are to be assigned at each time period such that bits indicating the multi-bit neuromorphic operation result (<NUM>) are sequentially obtained by the single neuron circuit (<NUM>) in the order starting from a value of a least significant bit, LSB, to a value of a most significant bit, MSB, and
characterized in that the adder is configured to receive, as the input carry value, an output carry value corresponding to a synaptic operation from a previous time period of the different time periods.