Patent Description:
Conventional technologies related to imaging devices, or the like have used a synchronous solid-state imaging device that captures image data (frames) in synchronization with a synchronization signal such as a vertical synchronization signal. This typical synchronous solid-state imaging device can only acquire image data every synchronization signal period (for example, <NUM>/<NUM> second), making it difficult to deal with faster processing when required in fields related to transportation, robots, or the like. To handle this, there has been proposed an asynchronous solid-state imaging device that detects, for each pixel address, an event that the change amount of the luminance of the pixel has exceeded a threshold, as an address event (refer to Patent Literature <NUM>, for example). The solid-state imaging device that detects an address event for each pixel in this manner is also referred to as an Event-based Vision Sensor (EVS) or a Dynamic Vision Sensor (DVS). European Patent Application Publication <CIT> provides a solid-state imaging element with circuitry for advanced address event detection by generating a result signal and a correction signal. European Patent Application Publication <CIT> is directed to providing a solid-state imaging element that detects an address event by determining, if an electric signal from the photoelectric conversion exceeds a predetermined threshold.

In the above-described asynchronous solid-state imaging device, the transistors constituting an address event detection circuit operate in a subthreshold region, and thus, the dynamic range at low illuminance greatly depends on the SN ratio, being a ratio of the photocurrent (S) to the thermal noise (N) in the transistors. In particular, pixel microfabrication, when performed along with trends of miniaturization and high resolution, would cause a decrease in the photocurrent per pixel, resulting in deterioration of the SN ratio and a narrower dynamic range at low illuminance. This can cause problems such as a decrease in sensitivity to the occurrence of an address event and an increase in errors in detection.

In view of this, the present disclosure proposes a solid-state imaging device and an imaging device capable of obtaining a dynamic range even at low illuminance.

According to a first aspect, the present invention provides a solid-state imaging element according to independent claim <NUM>. Further aspects of the present invention are set forth in the dependent claims, the drawings and the following description.

An embodiment of the present disclosure will be described below in detail with reference to the drawings. In each of the following embodiments, the same parts are denoted by the same reference symbols, and a repetitive description will be omitted.

The present disclosure will be described in the following order.

First, a first embodiment will be described in detail with reference to the drawings.

<FIG> is a block diagram depicting a configuration example of an imaging device <NUM> according to the first embodiment of the present disclosure. The imaging device <NUM> includes an optical section <NUM>, a solid-state imaging device <NUM>, a recording section <NUM>, and a control section <NUM>. Assumed examples of the imaging device <NUM> include devices such as a camera mounted on an industrial robot, and an in-vehicle camera.

The optical section <NUM> condenses incident light and guides the condensed light to the solid-state imaging device <NUM>. The solid-state imaging device <NUM> photoelectrically converts the incident light to generate image data. The solid-state imaging device <NUM> executes predetermined signal processing such as image recognition processing on the generated image data, and outputs the processed data to the recording section <NUM> through a signal line <NUM>.

The recording section <NUM> includes devices such as flash memory, for example, and records data output from the solid-state imaging device <NUM> and data output from the control section <NUM>.

The control section <NUM> includes an information processing device such as an application processor, for example, and controls the solid-state imaging device <NUM> to output image data.

<FIG> is a diagram depicting an example of a stacked structure of the solid-state imaging device <NUM> according to the present embodiment. The solid-state imaging device <NUM> includes a detection chip <NUM> and a light receiving chip <NUM> stacked on the detection chip <NUM>. These chips are electrically connected to each other through a connection portion such as a via. In addition to the via, Cu-Cu bonding or a bump can be used for the connection. For example, the light receiving chip <NUM> may be an example of a first chip in the claims, and the detection chip <NUM> may be an example of a second chip in the claims.

<FIG> is an example of a plan view of the light receiving chip <NUM> according to the present embodiment. The light receiving chip <NUM> includes a light receiving section <NUM> and via arrangement portions <NUM>, <NUM>, and <NUM>.

The via arrangement portions <NUM>, <NUM>, and <NUM> are portions where vias connected to the detection chip <NUM> are arranged. The light receiving section <NUM> is a place where a plurality of shared blocks <NUM> is arranged in a two-dimensional lattice pattern.

In each of the shared blocks <NUM>, one or more logarithmic response sections <NUM> are arranged. For example, four logarithmic response sections <NUM> are arranged in a <NUM> row × <NUM> column pattern for each shared block <NUM>. These four logarithmic response sections <NUM> share a circuit on the detection chip <NUM>. Details of the shared circuit will be described below. The number of logarithmic response sections <NUM> in the shared block <NUM> is not limited to four. In addition, a part or all of the circuit configuration excluding the photoelectric conversion element <NUM> in each logarithmic response section <NUM> may be arranged on the detection chip <NUM> side.

The logarithmic response section <NUM> converts the photocurrent flowing out of the photoelectric conversion element <NUM> into a voltage signal corresponding to the logarithmic value of the photocurrent. A pixel address including a row address and a column address is assigned to each logarithmic response section <NUM>. Note that the pixel in the present disclosure may have a configuration based on a photoelectric conversion element <NUM> to be described below, and the pixel in the present embodiment may have a configuration corresponding to a detection pixel <NUM> to be described below, for example.

<FIG> is an example of a plan view of the detection chip <NUM> according to the present embodiment. The detection chip <NUM> includes via arrangement portions <NUM>, <NUM>, and <NUM>, a signal processing circuit <NUM>, a row drive circuit <NUM>, a column drive circuit <NUM>, and an address event detecting section <NUM>. The via arrangement portions <NUM>, <NUM>, and <NUM> are portions where vias connected to the light receiving chip <NUM> are arranged.

The address event detecting section <NUM> detects the presence or absence of an address event for each logarithmic response section <NUM> and generates a detection signal indicating a detection result.

The row drive circuit <NUM> selects a row address and causes the address event detecting section <NUM> to output a detection signal corresponding to the row address.

The column drive circuit <NUM> selects a column address and causes the address event detecting section <NUM> to output a detection signal corresponding to the column address.

The signal processing circuit <NUM> performs predetermined signal processing on the detection signal output from the address event detecting section <NUM>. The signal processing circuit <NUM> arranges the detection signals as pixel signals in a two-dimensional lattice pattern, and generates image data having <NUM>-bit information for each pixel. The signal processing circuit <NUM> then executes signal processing such as image recognition processing on the image data.

<FIG> is an example of a plan view of the address event detecting section <NUM> according to the present embodiment. The address event detecting section <NUM> is a section in which a plurality of detection blocks <NUM> is arranged. The detection block <NUM> is arranged for each shared block <NUM> on the light receiving chip <NUM>. In a case where the number of the shared blocks <NUM> is N (N is an integer), N detection blocks <NUM> are arranged. Each detection block <NUM> is connected to the corresponding shared block <NUM>.

<FIG> is a circuit diagram depicting a basic configuration example of a logarithmic response section according to the present embodiment. The logarithmic response section <NUM> includes a photoelectric conversion element <NUM>, n-channel metal oxide semiconductor (nMOS) transistors <NUM> and <NUM>, and a p-channel MOS (pMOS) transistor <NUM>. Among these, the two nMOS transistors <NUM> and <NUM> constitute, for example, a logarithmic conversion circuit that converts the photocurrent flowing out of the photoelectric conversion element <NUM> into a voltage signal corresponding to the logarithmic value of the photocurrent. Further, the pMOS transistor <NUM> operates as a load MOS transistor for the logarithmic conversion circuit. Note that the photoelectric conversion element <NUM> and the nMOS transistors <NUM> and <NUM> can be arranged on the light receiving chip <NUM>, while the pMOS transistor <NUM> can be arranged on the detection chip <NUM>, for example.

Regarding the nMOS transistor <NUM>, its source is connected to a cathode of the photoelectric conversion element <NUM>, while is drain is connected to a power supply terminal. The pMOS transistor <NUM> and the nMOS transistor <NUM> are connected in series between the power supply terminal and the ground terminal. Further, a connection point of the pMOS transistor <NUM> and the nMOS transistor <NUM> is connected to a gate of the nMOS transistor <NUM> and an input terminal of the detection block <NUM>. Further, a predetermined bias voltage Vbias1 is applied to the gate of the pMOS transistor <NUM>.

The drains of the nMOS transistors <NUM> and <NUM> are connected to the power supply side, and such a circuit is referred to as a source follower. The two source followers connected in the loop shape converts the photocurrent from the photoelectric conversion element <NUM> into a voltage signal corresponding to the logarithmic value. Further, the pMOS transistor <NUM> supplies a constant current to the nMOS transistor <NUM>.

In addition, the ground of the light receiving chip <NUM> and the ground of the detection chip <NUM> are isolated from each other for a countermeasure against interference.

Although <FIG> is an example of configuration of the source follower type logarithmic response section <NUM>, the configuration of the section is not limited to such an example. <FIG> is a circuit diagram depicting a basic configuration example of a logarithmic response section according to a modification of the present embodiment. As depicted in <FIG>, for example, a logarithmic response section 310A has a configuration, referred to as a gain boost type circuit configuration, including an additional nMOS transistor <NUM>, connected in series between the nMOS transistor <NUM> and a power supply line, and an additional nMOS transistor <NUM>, connected in series between the nMOS transistor <NUM> and the pMOS transistor <NUM>, with respect to the source follower type circuit configuration depicted in <FIG>. The four nMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> constitute, for example, a logarithmic conversion circuit that converts the photocurrent flowing out of the photoelectric conversion element <NUM> into a voltage signal corresponding to the logarithmic value of the photocurrent.

In this manner, even with the use of the gain boost type logarithmic response section 310A, it is possible to convert the photocurrent from the photoelectric conversion element <NUM> into a voltage signal of a logarithmic value corresponding to the charge amount.

<FIG> is a block diagram depicting a configuration example of the detection block <NUM> according to the present embodiment. The detection block <NUM> includes a plurality of buffers <NUM>, a plurality of differentiators <NUM>, a selecting section <NUM>, a comparison section <NUM>, and a transfer circuit <NUM>. The buffer <NUM> and the differentiator <NUM> are arranged for each logarithmic response section <NUM> in the shared block <NUM>. For example, when the number of logarithmic response sections <NUM> in the shared block <NUM> is four, four buffers <NUM> and four differentiators <NUM> are arranged.

The buffer <NUM> outputs the voltage signal from the corresponding logarithmic response section <NUM> to the differentiator <NUM>. The buffer <NUM> can improve the driving force used for driving the subsequent stage. In addition, the buffer <NUM> can ensure isolation of noise associated with a switching operation in the subsequent stage.

The differentiator <NUM> obtains a change amount of the voltage signal, that is, a luminance change of the light incident on the photoelectric conversion element <NUM> as a differential signal. The differentiator <NUM> receives a voltage signal from the corresponding logarithmic response section <NUM> through the buffer <NUM>, and obtains a change amount of the voltage signal by differentiation. Subsequently, the differentiator <NUM> supplies the differential signal to the selecting section <NUM>. An m-th (m is an integer of <NUM> to M,) differential signal Sin in the detection block <NUM> is defined as Sinm. The differentiator <NUM> can correspond to, for example, a first circuit in the claims.

The selecting section <NUM> selects one of the M differential signals according to a selection signal from the row drive circuit <NUM>. The selecting section <NUM> includes selectors <NUM> and <NUM>.

M differential signals Sin are input to the selector <NUM>. The selector <NUM> selects one of these differential signals Sin according to the selection signal, and supplies the selected differential signal Sin to the comparison section <NUM> as Sout+. M differential signals Sin are also input to the selector <NUM>. The selector <NUM> selects one of these differential signals Sin according to the selection signal, and supplies the selected differential signal Sin to the comparison section <NUM> as Sout-.

The comparison section <NUM> compares the differential signal (that is, the change amount) selected by the selecting section <NUM> with a predetermined threshold. The comparison section <NUM> supplies a signal indicating a comparison result to the transfer circuit <NUM> as a detection signal. The comparison section <NUM> can correspond to a second circuit in the claims, for example.

The transfer circuit <NUM> transfers the detection signal to the signal processing circuit <NUM> according to the column drive signal from the column drive circuit <NUM>.

<FIG> is a circuit diagram depicting a configuration example of the differentiator <NUM> according to the present embodiment. The differentiator <NUM> includes capacitors <NUM> and <NUM>, an inverter <NUM>, and a switch <NUM>.

The capacitor <NUM> has one end connected to the output terminal of the buffer <NUM> and the other end connected to the input terminal of the inverter <NUM>. The capacitor <NUM> is connected in parallel to the inverter <NUM>. The switch <NUM> opens and closes a path connecting the ends of the capacitor <NUM> according to the row drive signal.

The inverter <NUM> inverts the voltage signal input through the capacitor <NUM>. The inverter <NUM> outputs the inverted signal to the selecting section <NUM>.

When the switch <NUM> is turned on, a voltage signal Vinit is input to the buffer <NUM> side of the capacitor <NUM>, causing the opposite side to be a virtual ground terminal. The potential of the virtual ground terminal is assumed to zero for convenience. At this time, when the capacitance of the capacitor <NUM> is C1, a potential Qinit accumulated in the capacitor <NUM> is expressed by the following Formula (<NUM>). On the other hand, since both ends of the capacitor <NUM> are short-circuited, accumulated charge is <NUM>.

Next, in an assumed case where the switch <NUM> is turned off and the voltage on the buffer <NUM> side of the capacitor <NUM> has changed to a voltage Vafter, charge Qafter accumulated in the capacitor <NUM> is expressed by the following Formula (<NUM>).

On the other hand, when the output voltage is Vout, charge Q2 accumulated in the capacitor <NUM> is expressed by the following Formula (<NUM>).

At this time, since the total charge amounts of the capacitors <NUM> and <NUM> do not change, the following Formula (<NUM>) holds.

When Formulas (<NUM>) to (<NUM>) are substituted into Formula (<NUM>) and the result can be transformed into the following Formula (<NUM>).

Formula (<NUM>) represents a subtraction operation of the voltage signals, in which the gain for the subtraction result is C1/C2. Since maximized gain is desirable in usual cases, it is preferable to design C1 to be large and C2 to be small. On the other hand, excessively small C2 would increase kTC noise and cause deterioration in noise characteristics. Therefore, capacity reduction of C2 is limited to a noise tolerable range. In addition, since the differentiator <NUM> is provided for each pixel, the capacitances C1 and C2 have area restrictions. In consideration of these, for example, C1 is set to a value of <NUM> to <NUM> femtofarad (fF), and C2 is set to a value of <NUM> to <NUM> femtofarad (fF).

<FIG> is a circuit diagram depicting a configuration example of the comparison section <NUM> according to the present embodiment. The comparison section <NUM> includes comparators <NUM> and <NUM>.

The comparator <NUM> compares the differential signal Sout+ from the selector <NUM> with a predetermined upper threshold Vrefp. The comparator <NUM> supplies a result of the comparison to the transfer circuit <NUM> as a detection signal DET+. The detection signal DET+ indicates the presence or absence of an on-event. Here, the on-event represents an event that the change amount of the luminance exceeds a predetermined upper threshold.

The comparator <NUM> compares the differential signal Sout-from the selector <NUM> with a lower threshold Vrefn lower than the upper threshold Vrefp. The comparator <NUM> supplies a result of the comparison to the transfer circuit <NUM> as a detection signal DET-. The detection signal DET- indicates the presence or absence of an off-event. Here, the off-event represents an event that the change amount of the luminance is less than the predetermined lower threshold. Note that although the comparison section <NUM> detects the presence or absence of both the on-event and the off-event, it is also possible to detect only one of the on-event and the off-event.

Note that, for example, the comparator <NUM> may be an example of a first comparator described in the claims, and the comparator <NUM> may be an example of a second comparator described in the claims. For example, the upper threshold may be an example of a first threshold described in the claims, and the lower threshold may be an example of a second threshold described in the claims.

<FIG> is a circuit diagram depicting a configuration example of the differentiator <NUM>, the selector <NUM>, and the comparator <NUM> in the detection block <NUM> according to the present embodiment.

The differentiator <NUM> includes capacitors <NUM> and <NUM>, pMOS transistors <NUM> and <NUM>, and an nMOS transistor <NUM>. The pMOS transistor <NUM> and the nMOS transistor <NUM> are connected in series between a power supply terminal and a ground terminal with the pMOS transistor <NUM> as a power supply side. The capacitor <NUM> is inserted between the gates of the pMOS transistor <NUM>/nMOS transistor <NUM> and the buffer <NUM>. A connection point of the pMOS transistor <NUM> and the nMOS transistor <NUM> is connected to the selector <NUM>. With this connection configuration, the pMOS transistor <NUM> and the nMOS transistor <NUM> function as the inverter <NUM>.

In addition, the capacitor <NUM> and the pMOS transistor <NUM> are connected in parallel between the connection point connecting the pMOS transistor <NUM> with the nMOS transistor <NUM>, and the capacitor <NUM>. The pMOS transistor <NUM> functions as the switch <NUM>.

Further, the selector <NUM> is provided with a plurality of pMOS transistors <NUM>. The pMOS transistor <NUM> is arranged for each differentiator <NUM>.

The pMOS transistor <NUM> is inserted between the corresponding differentiator <NUM> and the comparator <NUM>. Further, a selection signal SEL is individually input to each of the gates of the pMOS transistor <NUM>. The selection signal SEL of the m-th pMOS transistor <NUM> is referred to as SELm. By these selection signals SEL, the row drive circuit <NUM> can control to turn on one of the M pMOS transistors <NUM> and turn off the remaining others. In addition, the differential signal Sout+ is output to the comparator <NUM> as the selected signal through the pMOS transistor <NUM> in the on state. Note that the circuit configuration of the selector <NUM> is similar to that of the selector <NUM>.

The comparator <NUM> includes a pMOS transistor <NUM> and an nMOS transistor <NUM>. The pMOS transistor <NUM> and the nMOS transistor <NUM> are connected in series between the power supply terminal and the ground terminal. Further, the differential signal Sout+ is input to the gate of the pMOS transistor <NUM>, while the voltage of the upper threshold Vrefp is input to the gate of the nMOS transistor <NUM>. The detection signal DET+ is output from a connection point of the pMOS transistor <NUM> and the nMOS transistor <NUM>. Note that the circuit configuration of the comparator <NUM> is similar to that of the comparator <NUM>.

Note that the circuit configurations of the differentiator <NUM>, the selector <NUM>, and the comparator <NUM> are not limited to an example depicted in <FIG> as long as they have the functions described with reference to <FIG>. For example, the nMOS transistor and the pMOS transistor are interchangeable.

<FIG> is a timing chart depicting an example of control of the row drive circuit <NUM> according to the present embodiment. At timing T0, the row drive circuit <NUM> selects the first row by a row drive signal L1 and drives the differentiator <NUM> of the selected row. The row drive signal L1 initializes the capacitor <NUM> in the differentiator <NUM> in the first row. In addition, the row drive circuit <NUM> selects the upper left of the <NUM> row × <NUM> column pattern in the shared block <NUM> over a certain period of time by a selection signal SEL1, and drives the selecting section <NUM>. With this drive, the presence or absence of the address event is detected in the odd-numbered columns of the first row.

Next, at timing T1, the row drive circuit <NUM> drives the differentiator <NUM> in the first row again by the row drive signal L1. In addition, the row drive circuit <NUM> selects the upper right of the <NUM> row × <NUM> column pattern in the shared block <NUM> over a certain period of time by a selection signal SEL2. Accordingly, the presence or absence of an address event is detected in the even-numbered columns of the first row.

At timing T2, the row drive circuit <NUM> drives the differentiator <NUM> in the second row by the row drive signal L2. The row drive signal L2 initializes the capacitor <NUM> in the differentiator <NUM> in the second row. In addition, the row drive circuit <NUM> selects the lower left of the <NUM> row × <NUM> column pattern in the shared block <NUM> over a certain period of time by the selection signal SEL3. With this drive, the presence or absence of the address event is detected in the odd-numbered columns of the second row.

Subsequently, at timing T3, the row drive circuit <NUM> drives the differentiator <NUM> in the second row again by the row drive signal L2. In addition, the row drive circuit <NUM> selects the lower right of the <NUM> row × <NUM> column pattern in the shared block <NUM> over a certain period of time by a selection signal SEL4. Accordingly, the presence or absence of an address event is detected in the even-numbered columns of the second row.

Thereafter, similarly, the row drive circuit <NUM> sequentially selects the row in which the logarithmic response section <NUM> is arranged, and drives the selected row by the row drive signal. In addition, each time a row is selected, the row drive circuit <NUM> sequentially selects each of the detection pixels <NUM> in the shared block <NUM> of the selected row by a selection signal. For example, in a case where the detection pixels <NUM> of a <NUM> row × <NUM> column pattern are arranged in the shared block <NUM>, each time a row is selected, an odd-numbered column and an even-numbered column in the row are sequentially selected.

Note that the row drive circuit <NUM> can also sequentially select a row (in other words, two rows having the logarithmic response section <NUM>) in which the shared block <NUM> is arranged. In this case, every time a row is selected, four detection pixels in the shared block <NUM> of the row are sequentially selected.

<FIG> is a block diagram depicting a configuration example of the detection pixel <NUM> and a detection circuit <NUM> according to the present embodiment. Among the detection blocks <NUM> shared by the plurality of logarithmic response sections <NUM> in the shared block <NUM>, a circuit including the selecting section <NUM>, the comparison section <NUM>, and the transfer circuit <NUM> is defined as the detection circuit <NUM>. Further, a circuit including the logarithmic response section <NUM>, the buffer <NUM>, and the differentiator <NUM> is defined as the detection pixel <NUM>. As depicted in the drawing, the detection circuit <NUM> is shared by a plurality of the detection pixels <NUM>.

Each of the plurality of detection pixels <NUM> sharing the detection circuit <NUM> generates a voltage signal corresponding to the logarithmic value of the photocurrent. Subsequently, each of the detection pixels <NUM> outputs a differential signal Sin indicating a change amount of the voltage signal to the detection circuit <NUM> according to the row drive signal. In each of the detection pixels <NUM>, a voltage signal corresponding to a logarithmic value is generated by the logarithmic response section <NUM>, while a differential signal is generated by the differentiator <NUM>.

Selection signals such as selection signals SEL1 and SEL2 are commonly input to the selectors <NUM> and <NUM> in the detection circuit <NUM>. The detection circuit <NUM> selects a differential signal (that is, the change amount) of the detection pixel indicated by the selection signal among the plurality of detection pixels <NUM>, and detects whether the change amount exceeds a predetermined threshold. The detection circuit <NUM> then transfers the detection signal to the signal processing circuit <NUM> according to the column drive signal. In the detection circuit <NUM>, the differential signal is selected by the selecting section <NUM>, and the comparison with the threshold is performed by the comparison section <NUM>. In addition, the detection signal is transferred by the transfer circuit <NUM>.

Here, in a typical DVS, the comparison section <NUM> and the transfer circuit <NUM> are arranged for each detection pixel together with the logarithmic response section <NUM>, the buffer <NUM>, and the differentiator <NUM>. In contrast, in the above-described configuration in which the detection circuit <NUM> including the comparison section <NUM> and the transfer circuit <NUM> is shared by the plurality of detection pixels <NUM>, it is possible to reduce the circuit scale of the solid-state imaging device <NUM> as compared with a case where the detection circuit is not shared. This facilitates microfabrication of pixels.

When the stacked structure is adopted in particular, using a conventional configuration with no shared use of the detection circuit <NUM> would lead to the detection chip <NUM> having a larger circuit scale compared to the light receiving chip <NUM>. With this configuration, the density of the pixels is limited by the circuit on the detection chip <NUM>, making it difficult to achieve microfabrication of the pixels. However, by using a configuration in which the plurality of detection pixels <NUM> shares the detection circuit <NUM>, it is possible to reduce the circuit scale of the detection chip <NUM>, facilitating microfabrication of the pixels.

Although the buffer <NUM> is arranged for each detection pixel <NUM>, the configuration is not limited to this configuration, and it is also possible to omit the buffer <NUM>.

In addition, although the photoelectric conversion element <NUM> and the nMOS transistors <NUM> and <NUM> of the logarithmic response section <NUM> are arranged on the light receiving chip <NUM>, and the pMOS transistors <NUM> and subsequent transistors are arranged on the detection chip <NUM>, the configuration is not limited to this example. For example, the photoelectric conversion element <NUM> alone can be arranged on the light receiving chip <NUM>, and the other devices can be arranged on the detection chip <NUM>. Alternatively, the logarithmic response section <NUM> alone can be arranged on the light receiving chip <NUM>, and the buffers <NUM> and the subsequent devices can be arranged on the detection chip <NUM>. Still alternatively, the logarithmic response section <NUM> and the buffer <NUM> can be arranged on the light receiving chip <NUM>, while the differentiator <NUM> and the subsequent devices can be arranged on the detection chip <NUM>. In addition, the logarithmic response section <NUM>, the buffer <NUM>, and the differentiator <NUM> can be arranged on the light receiving chip <NUM>, and the detection circuit <NUM> and the subsequent circuits can be arranged on the detection chip <NUM>. Still alternatively, portions up to the selecting section <NUM> can be arranged on the light receiving chip <NUM>, while the comparison section <NUM> and the subsequent components can be arranged on the detection chip <NUM>.

<FIG> is a flowchart depicting an example of the operation of the solid-state imaging device <NUM> according to the present embodiment. The operation is started at a timing of execution of a predetermined application for detecting the presence or absence of an address event, for example.

The row drive circuit <NUM> selects one of the rows (step S901). The row drive circuit <NUM> selects and drives one of the detection pixels <NUM> in each shared block <NUM> in the selected row (step S902). The detection circuit <NUM> detects the presence or absence of an address event in the selected detection pixel <NUM> (step S903). After step S903, the solid-state imaging device <NUM> repeatedly executes step S901 and subsequent steps.

In this manner, the present embodiment has a configuration in which the detection circuit <NUM> that detects the presence or absence of the address event is shared by the plurality of detection pixels <NUM>, making it possible to reduce the circuit scale as compared with the case where the detection circuit <NUM> is not shared. This facilitates microfabrication of the detection pixel <NUM>.

In the first embodiment described above, the solid-state imaging device <NUM> selects the detection pixels <NUM> one by one, and simultaneously detects an on-event and an off-event for the detection pixels. Alternatively, the solid-state imaging device <NUM> can also select two detection pixels, detect an on-event for one of the detection pixels, and detect an off-event for the other detection pixel. The solid-state imaging device <NUM> according to a modification of the first embodiment is different from that of the first embodiment in that an on-event is detected for one of two detection pixels and an off-event is detected for the other detection pixel.

<FIG> is a block diagram depicting a configuration example of the detection pixel <NUM> and the detection circuit <NUM> according to the modification of the present embodiment. The detection circuit <NUM> according to the modification of the first embodiment is different from that of the first embodiment in that a selection signal such as a selection signal SEL1p or SEL2p is input to the selector <NUM> while a selection signal such as a selection signal SEL1n or SEL2n is input to the selector <NUM>. In the modification of the first embodiment, two detection pixels <NUM> are selected, and the selector <NUM> selects one differential signal according to a selection signal SEL1p, SEL2p, or the like. At the same time, the selector <NUM> selects the other differential signal according to the selection signal SEL1n, SEL2n, or the like.

<FIG> is a timing chart depicting an example of control of the row drive circuit <NUM> in the modification of the present embodiment. At the timings T0 to T2, it is assumed that two pixels are selected, that is, the detection pixel <NUM> that outputs a differential signal Sin1 and the detection pixel <NUM> that outputs a differential signal Sin2. At timings T0 to T1, the row drive circuit <NUM> sets the selection signals SEL1p and SEL2n to the high level and sets the selection signals SEL2p and SEL1n to the low level. With this setting, an on-event is detected for the pixel corresponding to the differential signal Sin1, and an off-event is detected for the pixel corresponding to the differential signal Sin2.

Next, at timings T1 to T2, the row drive circuit <NUM> sets the selection signals SEL1p and SEL2n to the low level and sets the selection signals SEL2p and SEL1n to the high level. With this setting, an on-event is detected for the pixel corresponding to the differential signal Sin2, and an off-event is detected for the pixel corresponding to the differential signal Sin1.

In this manner, according to the modification of the present embodiment, since the on-event is detected for one of the two detection pixels and the off-event is detected for the other detection pixel, it is possible to detect the on-event and the off-event spatially in parallel at the same time.

Next, a more specific configuration example of each shared block <NUM> in the above description will be described in detail below with reference to the drawings. The following description uses, as the logarithmic response section <NUM>, a gain boost type logarithmic response section 310A depicted in <FIG>, as an example. However, the configuration is not limited to this example, and it is allowable to use various circuits that generate a voltage signal according to the logarithmic value of the photocurrent, such as the source follower type logarithmic response section <NUM> depicted in <FIG>, for example. Further, the following description uses an exemplary case where one shared block <NUM> includes a total of four logarithmic response sections 310A in a <NUM> row × <NUM> column pattern. However, the configuration is not limited to this example, and each shared block <NUM> may include one or two or more logarithmic response sections 310A.

<FIG> is a circuit diagram depicting a schematic configuration example of a shared block according to the present embodiment. As depicted in <FIG>, each shared block <NUM> includes four logarithmic response sections 310A1 to 310A4. Each of the logarithmic response sections 310A1 to 310A4 (hereinafter, referred to as the logarithmic response section 310An when logarithmic response sections 310A1 to 310A4 are not distinguished from each other) has a configuration in which two switching transistors <NUM> and <NUM> have been added to the basic configuration of the logarithmic response section 310A depicted in <FIG>. Each of the two switching transistors <NUM> and <NUM> may be either an nMOS transistor or a pMOS transistor. For example, the switching transistor <NUM> may be an example of a first transistor in the claims, and the switching transistor <NUM> may be an example of a second transistor in the claims.

The switching transistor <NUM> is connected, for example, between the cathode of the photoelectric conversion element <NUM>, the drain of the nMOS transistor <NUM>, and the gate of the nMOS transistor <NUM>, and controls the inflow of the photocurrent flowing from the photoelectric conversion element <NUM> into the logarithmic conversion circuit.

The switching transistor <NUM> is connected, for example, between the cathode of the photoelectric conversion element <NUM> and a common line <NUM>. The common line <NUM> is connected with cathodes of the photoelectric conversion elements <NUM> in all the logarithmic response sections 310An included in the same shared block <NUM>, through the switching transistor <NUM>. For example, the common line <NUM> may be an example of a first common line in the claims.

In the above configuration, by turning on the switching transistors <NUM> in two or more logarithmic response sections 310An among the logarithmic response sections 310An included in one shared block <NUM>, turning on the switching transistors <NUM> of one logarithmic response section 310An (referred to as a logarithmic response section 310A1) among the two or more logarithmic response sections 310An, and turning off the switching transistors <NUM> of the other logarithmic response sections 310An, it is possible to allow the photocurrent flowing out of the photoelectric conversion element <NUM> of the logarithmic response section 310A1 and the photocurrent flowing out of the photoelectric conversion element <NUM> of the logarithmic response section 310An in which the switching transistor <NUM> has been turned off to intensively flow into the logarithmic conversion circuit of the logarithmic response section 310A1. That is, it is possible to collect the photocurrent flowing out of the photoelectric conversion element <NUM> of the logarithmic response section 310An in which the switching transistor <NUM> is turned off and the switching transistor <NUM> is turned on into the logarithmic conversion circuit of the logarithmic response section 310An in which both the switching transistors <NUM> and <NUM> are turned on.

In this manner, by adopting a configuration in which the photocurrents flowing out from the plurality of photoelectric conversion elements <NUM> can be aggregated into one logarithmic conversion circuit, it is possible to obtain a larger photocurrent amount, leading to expansion of the dynamic range in photocurrent detection. This makes it possible to obtain a sufficiently wide dynamic range even under the condition such as low illuminance.

On the other hand, in a case where sufficient illuminance can be obtained, by turning off the switching transistor <NUM> and turning on the switching transistor <NUM> in all or a necessary and sufficient number of logarithmic response sections 310An, it is possible to allow all or the necessary and sufficient number of logarithmic response sections 310An to operate as one address event detection pixel, leading to achievement of detection of an address event at high resolution, reduction of operating power, and the like.

Next, a layout example of the shared block <NUM> depicted in <FIG> will be described. <FIG> is a plan view depicting a layout example of the shared block according to the present embodiment. For convenience of explanation, <FIG> depicts a schematic layout example on the element formation surface side of a semiconductor substrate on which the photoelectric conversion element <NUM> is formed and a schematic layout example of a part of a wiring layer formed on the element formation surface of the substrate. Further, for the sake of clarity, <FIG> depicts an arrangement of the nMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> and the switching transistors <NUM> and <NUM> by the position of the gate electrode. <FIG> further depicts, by a thick arrow, an outline of a current path formed in a binning mode to be described below.

Here, in the present embodiment, there are at least two definitions of one pixel. In one definition, a pixel is a pixel on a layout formed in a repeated pattern in the design of the light receiving section <NUM>, and in the other definition, a pixel is a pixel on a circuit that operates as one detection pixel <NUM>. Each pixel on the circuit includes one logarithmic response section 310An. In the following description, a pixel on a layout is referred to as a layout pixel, and a pixel on a circuit is referred to as a circuit pixel. Further, since the configuration of the detection pixel <NUM> arranged in the light receiving section <NUM> is all or a part of the logarithmic response section 310An, here, the logarithmic response section 310An will be described as a circuit pixel.

As depicted in <FIG>, a pixel area in which one layout pixel <NUM> is arranged in the light receiving chip <NUM> is partitioned by a pixel isolation section <NUM> extending in the row direction and the column direction. Each layout pixel <NUM> includes: a photoelectric conversion element <NUM> arranged substantially at the center; a plurality of nMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> arranged along the outer peripheral portion of the pixel area, in other words, arranged so as to surround the photoelectric conversion element <NUM> from at least two directions (three directions in <FIG>); switching transistors <NUM> and <NUM>; and a contact 314c for forming a connection with the pMOS transistor <NUM> arranged on the detection chip <NUM> side.

In the layout example depicted in <FIG>, for example, in each logarithmic response section 310An depicted in <FIG>, the nMOS transistors <NUM> and <NUM> in the left column are arranged on the left side of the photoelectric conversion element <NUM>, and the nMOS transistors <NUM> and <NUM> in the right column are arranged on the right side of the photoelectric conversion element <NUM>. Further, the two switching transistors <NUM> and <NUM> are disposed on the upper or lower side of the photoelectric conversion element <NUM>, for example. In this manner, by adopting a highly symmetric layout in which the photoelectric conversion element <NUM> is sandwiched between two nMOS transistors, it is possible to increase process accuracy and yield at the time of manufacturing.

Further, for example, the two switching transistors <NUM> and <NUM> are arranged on the lower side of the photoelectric conversion element <NUM> in the odd-numbered rows, and are arranged on the upper side of the photoelectric conversion element <NUM> in the even-numbered rows. That is, the layout pixels <NUM> in the even-numbered rows have a layout obtained by vertically inverting the layout pixels <NUM> in the odd-numbered rows. By adopting such a layout, the pattern of one layout pixel <NUM> can be used for all the layout pixels <NUM>, making it possible to facilitate layout design of the light receiving section <NUM>.

Further, by arranging the layout pixel <NUM> in a layout in which the odd-numbered row and the even-numbered row are vertically inverted, the switching transistors <NUM> and <NUM> of the logarithmic response section 310An constituting one shared block <NUM> can be brought close to each other, making it also possible to achieve facilitation of layout design of the common line <NUM>, reduction of the wiring length of the common line <NUM>, and the like.

On the other hand, on the circuit, the photoelectric conversion element <NUM> in a certain layout pixel <NUM>, the two nMOS transistors <NUM> and <NUM> arranged on the left side of the photoelectric conversion element <NUM>, and the two nMOS transistors <NUM> and <NUM> arranged on the right side of the photoelectric conversion element <NUM> in the layout pixel <NUM> adjacent to the layout pixel <NUM> on the left side constitute one circuit pixel (here, the logarithmic response section 310An). That is, in the circuit pixel (here, the logarithmic response section 310An) on the layout, the logarithmic conversion circuit including the four nMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> is configured to be arranged across the pixel isolation section <NUM>.

With this configuration of the logarithmic conversion circuit in one logarithmic response section 310An between the adjacent layout pixels <NUM> in this manner, it is possible to reduce the wiring length of the logarithmic conversion circuit, that is, the wiring length connecting the nMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> constituting the logarithmic conversion circuit, while maintaining the symmetry of the layout pixel <NUM>. This makes it possible to reduce the time constant formed by the wiring constituting the logarithmic conversion circuit, leading to improved response speed of the logarithmic conversion circuit.

Next, an operation example of the imaging device <NUM> according to the present embodiment will be described. As described above, in the present embodiment, by controlling on/off of the switching transistors <NUM> and <NUM>, it is possible to switch between two modes, namely, a mode (hereinafter, referred to as a high-resolution mode) in which one logarithmic response section <NUM> (which may be the logarithmic response section 310A) operates as one pixel and a mode (hereinafter, referred to as a binning mode) in which two or more logarithmic response sections <NUM> in the shared block <NUM> operate as one pixel. In addition, it is also possible to realize a mode (hereinafter, referred to as a ROI mode) in which some of the shared blocks <NUM> are driven in the high-resolution mode and the remaining shared blocks <NUM> are driven in the binning mode. For example, the binning mode and the ROI mode may be an example of a first mode in the claims, and the high-resolution mode may be an example of a second mode in the claims. The binning mode may be an example of a third mode in the claims, and the ROI mode may be an example of a fourth mode in the claims.

<FIG> is a timing chart depicting exemplary control of the switching transistors in the high-resolution mode and the binning mode according to the present embodiment. As depicted in <FIG>, in the high-resolution mode depicted in sections T10 to T11, in each logarithmic response sections 310A1 to 310A4, the switching transistor <NUM> is turned on, and the switching transistor <NUM> is turned off. This leads to formation of a current path through which the photocurrent flowing out of the photoelectric conversion element <NUM> of each logarithmic response sections 310A1 to 310A4 flows into their own logarithmic conversion circuits.

In contrast, in the binning mode depicted in the sections T11 to T12, both the switching transistors <NUM> and <NUM> of the logarithmic response section 310A1 are turned on. On the other hand, in the logarithmic response sections 310A2 to 310A4, the switching transistor <NUM> is turned off while the switching transistor <NUM> is turned on. This leads to formation of a current path through which the photocurrent flowing out of the photoelectric conversion element <NUM> of each logarithmic response sections 310A1 to 310A4 flows into the logarithmic conversion circuit of the logarithmic response section 310A1.

Next, an operation example of the imaging device <NUM> will be described. <FIG> is a flowchart depicting an operation example of the imaging device according to the present embodiment, depicting an operation example of switching between a mode (hereinafter, referred to as an all-pixel binning mode) in which all pixels operate in a binning mode, a mode (hereinafter, referred to as an all-pixel high-resolution mode) in which all pixels operate in a high-resolution mode, and the ROI mode. The present description will describe an exemplary case where the control section <NUM> (refer to <FIG>) in the imaging device <NUM> controls the operation mode of the solid-state imaging device <NUM>. However, control of the operation mode is not limited to this example and the signal processing circuit <NUM> in the solid-state imaging device <NUM> may be configured to control the operation mode. Further, the operation depicted in <FIG> may be terminated by, for example, an interruption operation or the like with respect to the control section <NUM> or the solid-state imaging device <NUM>.

As depicted in <FIG>, in the present operation, after activation, the control section <NUM> sets the operation mode of the solid-state imaging device <NUM> to the all-pixel binning mode, for example (step S101). In the all-pixel binning mode, as described above, all the shared blocks <NUM> of the light receiving section <NUM> are driven in the binning mode. In this case, for example, in the example depicted in <FIG>, the switching transistors <NUM> of all the logarithmic response sections 310A1 to 310A4 in each shared block <NUM> are turned on, the switching transistor <NUM> of the logarithmic response section 310A1 is turned on, and the switching transistors <NUM> of the logarithmic response sections 310A2 to 310A4 are turned off. This leads to formation of a current path through which the photocurrent flowing out of the photoelectric conversion element <NUM> of all the logarithmic response sections 310A1 to 310A4 flows into the logarithmic conversion circuit of the logarithmic response section 310A1.

Next, the control section <NUM> determines whether an object has been detected in the all-pixel binning mode (step S102), and continues the all-pixel binning mode until the object is detected (NO in step S102). The object detection determination may be executed, for example, on the basis of a condition such as whether an address event (on-event and/or off-event) has been detected in any shared block, or whether a region where the address event has been detected has an area or a number of pixels of a certain degree (for example, a preset threshold or more). Detection of an object does not need to be determined in one frame, and may be determined in several consecutive frames. Note that one frame may be, for example, image data including address information (which may include a timestamp) of a pixel on which an address event has been detected within a predetermined period of time. Further, the detection of the object may be executed by processing such as object recognition on the image data.

When an object has been detected (YES in step S102), the control section <NUM> determines, for example, whether the detected object is a wide range object, whether the detected object is a plurality of objects, or the like (step S103). Note that the wide range may be, for example, a range that occupies a preset ratio (for example, <NUM>% of the area or the number of pixels, or the like) or more with respect to the light receiving section <NUM>.

When the detected object is not a wide range object (NO in step S103), the control section <NUM> sets the operation mode of the solid-state imaging device <NUM> to the ROI mode, for example (step S104). The ROI mode is a mode of driving some region including the region where the object is detected in the light receiving section <NUM> in the high-resolution mode, and driving the other region in the binning mode, for example.

Next, the control section <NUM> determines whether an object has been detected (step S105). When no object has been detected (NO in step S105), the control section <NUM> returns the process to step S101 to restart setting the all-pixel binning mode to the solid-state imaging device <NUM>. When an object has been detected (YES in step S105), the control section <NUM> determines, for example, whether the detected object is a wide range object, whether the detected object is a plurality of objects, or the like, similarly to step S103 (step S106). When the detected object is not a wide range object (NO in step S106), the control section <NUM> returns the process to step S105 to continue the ROI mode.

When a wide range object has been detected in step S103 or step S106 (YES in step S103/S106), the control section <NUM> sets the operation mode of the solid-state imaging device <NUM> to the all-pixel high-resolution mode, for example (step S107). As described above, the all-pixel high-resolution mode is a mode in which all the shared blocks <NUM> of the light receiving section <NUM> are driven in the high-resolution mode. In this case, in the example depicted in <FIG>, the switching transistors <NUM> of all the logarithmic response sections 310A1 to 310A4 in each shared block <NUM> are turned off, and the switching transistors <NUM> are turned on, for example. This leads to formation of an individual current path through which the photocurrent flowing out of the photoelectric conversion element <NUM> of each logarithmic response sections 310A1 to 310A4 flows into their own logarithmic conversion circuits.

Next, the control section <NUM> determines whether an object has been detected (step S108). When no object has been detected (NO in step S108), the control section <NUM> returns the process to step S101 to restart setting the all-pixel binning mode to the solid-state imaging device <NUM>. When an object has been detected (YES in step S108), the control section <NUM> determines, for example, whether the detected object is a wide range object, whether the detected object is a plurality of objects, or the like, similarly to step S103 (step S109). When the detected object is a wide range object (YES in step S109), the control section <NUM> returns the process to step S108 to continue the all-pixel high-resolution mode. In contrast, when the detected object is not a wide range object or a plurality of objects (NO in step S109), the control section <NUM> proceeds to step S104, sets the operation mode of the solid-state imaging device <NUM> to the ROI mode and executes subsequent operations.

As described above, according to the present embodiment, with a configuration in which the photocurrent flowing out from the plurality of photoelectric conversion elements <NUM> can be aggregated into one logarithmic conversion circuit, it is possible to obtain a larger photocurrent amount, enabling expansion of the dynamic range in photocurrent detection. This makes it possible to obtain a sufficiently wide dynamic range even under the condition such as low illuminance.

Further, in the binning mode, constantly turning on the switching transistor <NUM> of the shared logarithmic response section 310An (for example, all logarithmic response sections 310An in the shared block <NUM>) will allow constant formation of a current path from each logarithmic response sections 310A2 to 310An to the logarithmic conversion circuit of the logarithmic response section 310A1. This makes it possible to share one logarithmic conversion circuit by the plurality of detection pixels <NUM> without including a charge storage section such as a floating diffusion region, like a case of a CMOS image sensor.

Next, a second embodiment will be described in detail with reference to the drawings. In the present embodiment, another configuration of the shared block <NUM> described with reference to <FIG> in the first embodiment will be described with an example.

In the first embodiment, as described with reference to <FIG> and <FIG>, the photocurrent, which has flowed out of the photoelectric conversion element <NUM> of the logarithmic response sections 310A2 to 310A4 in which the switching transistor <NUM> is turned off in the binning mode, flows through the common line <NUM>, then through the switching transistor <NUM> of the logarithmic response section 310A1, the cathode of the photoelectric conversion element <NUM> and through the switching transistor <NUM>, so as to flow into the logarithmic conversion circuit of the logarithmic response section 310A1. Therefore, it is necessary, in the first embodiment, to implement potential design ranging from the switching transistor <NUM> of the logarithmic response section 310A1 through the cathode of the photoelectric conversion element <NUM> up to the switching transistor <NUM> so that the photocurrent flowing out of the photoelectric conversion elements <NUM> of the logarithmic response sections 310A2 to 310A4 smoothly flows into the logarithmic conversion circuit of the logarithmic response section 310A1. Accordingly, in the second embodiment, a shared block capable of greatly relaxing the restriction on the potential design will be described with an example.

The configurations and operations of the imaging device and the solid-state imaging device according to the present embodiment may be similar to the configurations and operations of the imaging device <NUM> and the solid-state imaging device <NUM> according to the first embodiment described above, and thus, detailed description will be omitted here. However, in the present embodiment, the shared block <NUM> according to the first embodiment is replaced with a shared block <NUM> to be described below.

<FIG> is a circuit diagram depicting a schematic configuration example of the shared block according to the present embodiment. A logarithmic response section 310Bn exemplified below is an example of a logarithmic response section based on the gain boost type logarithmic response section 310A exemplified in <FIG>. However, the configuration is not limited thereto, and it is also allowable, for example, to have a logarithmic response section 310B based on various circuits that generate voltage signals corresponding to logarithmic values of photocurrent, such as the source follower type logarithmic response section <NUM> exemplified in <FIG>. Further, the following description uses an exemplary case where one shared block <NUM> includes a total of four logarithmic response sections 310Bn in a <NUM> row × <NUM> column pattern. However, the configuration is not limited to this example, and each shared block <NUM> may include one or two or more logarithmic response sections 310Bn.

As depicted in <FIG>, logarithmic response sections 310B1 to 310B4 according to the present embodiment (in the present description, represented by using the reference numeral 310Bn when the logarithmic response sections 310B1 to 310B4 are not distinguished from each other) each have a configuration in which a switching transistor <NUM> is further added to a configuration similar to the logarithmic response section 310An described with reference to <FIG> in the first embodiment. The switching transistor <NUM> has the source connected to, for example, the drain of the switching transistor <NUM>, and has the drain connected to the drain of the switching transistor <NUM>, the source of the nMOS transistor <NUM>, and the gate of the nMOS transistor <NUM>, for example. For example, the switching transistor <NUM> may be an example of a third transistor in the claims. Further, for example, a node connecting the drain of the switching transistor <NUM>, the source of the nMOS transistor <NUM>, and the gate of the nMOS transistor <NUM> to each other may be an example of a second node in the claims, while the drain of the switching transistor <NUM> may be an example of the second node in the claims.

Next, a layout example of the shared block <NUM> depicted in <FIG> will be described. <FIG> is a plan view depicting a layout example of the shared block according to the present embodiment. For convenience of explanation, <FIG> depicts a schematic layout example on the element formation surface side of a semiconductor substrate on which the photoelectric conversion element <NUM> is formed and a schematic layout example of a part of a wiring layer formed on the element formation surface of the substrate. Further, for the sake of clarity, <FIG> depicts an arrangement of the nMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> and the switching transistors <NUM> to <NUM> by the position of the gate electrode. <FIG> further depicts, by a thick arrow, an outline of a current path formed in the binning mode to be described below. For example, the nMOS transistor <NUM> may be an example of a fourth transistor in the claims, the nMOS transistor <NUM> may be an example of a fifth transistor in the claims, the nMOS transistor <NUM> may be an example of a sixth transistor in the claims, and the nMOS transistor <NUM> may be an example of a seventh transistor in the claims.

As depicted in <FIG>, each layout pixel <NUM> according to the present embodiment has a configuration in which a switching transistor <NUM> is added on the same side of the switching transistor <NUM> disposed with respect to the photoelectric conversion element <NUM>, in a configuration similar to the layout pixel <NUM> described with reference to <FIG> in the first embodiment. By adopting such a layout, it is possible to reduce the wiring from the common line <NUM> to the switching transistor <NUM>.

Next, an operation example of the logarithmic response section 310Bn will be described. <FIG> is a timing chart depicting exemplary control of the switching transistors in the high-resolution mode and the binning mode according to the present embodiment. As depicted in <FIG>, in the high-resolution mode depicted in sections T20 to T21, in each of the logarithmic response sections 310B1 to 310B4, the switching transistors <NUM> and <NUM> are turned off, and the switching transistor <NUM> is turned on. This leads to formation of a current path through which the photocurrent flowing out of the photoelectric conversion element <NUM> of each logarithmic response sections 310B1 to 310B4 flows into their own logarithmic conversion circuits.

In contrast, in the binning mode depicted in the sections T21 to T22, the switching transistor <NUM> of the logarithmic response section 310B1 is turned on, the switching transistor <NUM> is turned off, and the switching transistor <NUM> is turned on. On the other hand, in the logarithmic response sections 310B2 to 310B4, the switching transistor <NUM> is turned off, the switching transistor <NUM> is turned on, and the switching transistor <NUM> is turned off. This leads to formation of a current path through which the photocurrent flowing out of the photoelectric conversion element <NUM> of each logarithmic response sections 310B1 to 310B4 flows into the logarithmic conversion circuit of the logarithmic response section 310B1.

As described above, according to the present embodiment, it is possible, in the binning mode, to form a current path in which the photocurrent flowing through the common line <NUM> flows into the logarithmic conversion circuit of the logarithmic response section 310B1 through the switching transistor <NUM> of the logarithmic response section 310B1 without passing through the switching transistor <NUM> of the logarithmic response section 310B1, the cathode of the photoelectric conversion element <NUM>, or the switching transistor <NUM>. This makes it is possible to greatly relax the restriction on the potential design ranging from the switching transistor <NUM> to the switching transistor <NUM>.

Since other configurations, operations, and effects may be similar to those in the above-described embodiment, detailed description will be omitted here.

Next, a third embodiment will be described in detail with reference to the drawings. In the present embodiment, still another configuration of the shared block <NUM> described with reference to <FIG> in the first embodiment will be described with an example.

<FIG> is a circuit diagram depicting a schematic configuration example of a shared block according to the present embodiment. A logarithmic response section 310Cn exemplified below is an example of a logarithmic response section based on the gain boost type logarithmic response section 310A exemplified in <FIG>. However, the configuration is not limited thereto, and it is also allowable, for example, to have the logarithmic response section 310B based on various circuits that generate voltage signals corresponding to logarithmic values of photocurrent, such as the source follower type logarithmic response section <NUM> exemplified in <FIG>. Further, the following description uses an exemplary case where one shared block <NUM> includes a total of four logarithmic response sections 310Cn in a <NUM> row × <NUM> column pattern. However, the configuration is not limited to this example, and each shared block <NUM> may include one or two or more logarithmic response sections 310Cn.

As depicted in <FIG>, logarithmic response sections 310C1 to 310C4 according to the present embodiment (in the present description, represented by using the reference numeral 310Cn when the logarithmic response sections 310C1 to 310C4 are not distinguished from each other) each have a configuration in which a switching transistor <NUM> is omitted from a configuration similar to the logarithmic response section 310Bn described with reference to <FIG> in the second embodiment. Further, in the logarithmic response section 310Cn, the drain of the switching transistor <NUM> is connected to the source of the nMOS transistor <NUM>, the source is connected to the gate of the nMOS transistor <NUM> and the cathode of the photoelectric conversion element <NUM>, and the drain of the switching transistor <NUM> is connected to the source of the switching transistor <NUM>, the gate of the nMOS transistor <NUM>, and the cathode of the photoelectric conversion element <NUM>.

Next, an operation example of the logarithmic response section 310Cn will be described. <FIG> is a timing chart depicting exemplary control of the switching transistors in the high-resolution mode and the binning mode according to the present embodiment. As depicted in <FIG>, in the high-resolution mode depicted in sections T30 to T31, in each logarithmic response sections 310C1 to 310B4, the switching transistor <NUM> is turned on, and the switching transistor <NUM> is turned off. This leads to formation of a current path through which the photocurrent flowing out of the photoelectric conversion element <NUM> of each logarithmic response sections 310C1 to 310C4 flows into their own logarithmic conversion circuits.

In contrast, in the binning mode depicted in the sections T31 to T32, both the switching transistors <NUM> and <NUM> of the logarithmic response section 310C1 are turned on. On the other hand, in the logarithmic response sections 310C2 to 310C4, the switching transistor <NUM> is turned off while the switching transistor <NUM> is turned on. This leads to formation of a current path through which the photocurrent flowing out of the photoelectric conversion element <NUM> of each logarithmic response sections 310C1 to 310C4 flows into the logarithmic conversion circuit of the logarithmic response section 310C1.

As described above, according to the present embodiment, for example, as compared with the second embodiment, since the switching transistor <NUM> can be omitted, it is possible to reduce the area occupied by the logarithmic response section 310Cn in the pixel area. This makes it possible increase the area of the light receiving surface of the photoelectric conversion element <NUM>, leading to achievement of sensitivity improvement and the dynamic range expansion of the solid-state imaging device <NUM>. In addition, omission of the switching transistor <NUM> makes it possible to further reduce the drive current.

The above embodiment is an exemplary configuration in which the solid-state imaging device <NUM> outputs frame data (corresponding to image data) including the detection signal indicating the presence or absence of the address event for each pixel. In contrast, the fourth embodiment will be described, with an example, regarding a configuration in which the solid-state imaging device <NUM> can also output image data (hereinafter, also referred to as gradation image data) including a pixel signal according to an exposure amount of each pixel in addition to image data including a detection signal of each pixel.

The configurations and operations of the imaging device and the solid-state imaging device according to the present embodiment may be similar to the configurations and operations of the imaging device <NUM> and the solid-state imaging device <NUM> according to the first embodiment described above, and thus, detailed description will be omitted here. However, in the present embodiment, the shared block <NUM> according to the first embodiment is replaced with a shared block <NUM> to be described below, and the detection chip <NUM> is replaced with a detection chip <NUM> to be described below.

<FIG> is a circuit diagram depicting a schematic configuration example of a shared block according to the present embodiment. The shared block <NUM> exemplified below is based on the shared block <NUM> exemplified in <FIG>. However, the configuration is not limited thereto, and the shared block <NUM> may be based on the shared block <NUM> according to the second embodiment or the shared block <NUM> according to the third embodiment, for example.

As depicted in <FIG>, the shared block <NUM> according to the present embodiment has a configuration in which a readout circuit <NUM> for reading a pixel signal is connected to the common line <NUM> in a configuration similar to the shared block <NUM> described with reference to <FIG> in the first embodiment.

Further, the shared block <NUM> according to the present embodiment can also be formed on the basis of the shared block <NUM> described in the second embodiment with reference to <FIG>, for example. Also in this case, as depicted in <FIG>, the shared block <NUM> has a configuration similar to the shared block <NUM> described with reference to <FIG>, in which a readout circuit <NUM> for reading a pixel signal is connected to the common line <NUM>.

<FIG> is a circuit diagram depicting a schematic configuration example of a readout circuit according to the present embodiment. As depicted in <FIG>, the readout circuit <NUM> according to the present embodiment includes a reset transistor <NUM>, an amplification transistor <NUM>, and a selection transistor <NUM>.

The readout circuit <NUM> operates together with the photoelectric conversion element <NUM> and the switching transistor <NUM> of the logarithmic response sections 310An to function as a gradation pixel <NUM> that generates a pixel signal corresponding to the amount of received light. That is, in the present embodiment, the switching transistor <NUM> of each logarithmic response section 310An also functions as a transfer transistor in the gradation pixel <NUM>. Further, a node to which the drain of the switching transistor <NUM>, the source of the reset transistor <NUM>, and the gate of the amplification transistor <NUM> are connected functions as a floating diffusion region (FD) <NUM> having a current-voltage conversion function, that is, a function of converting accumulated charge into a voltage corresponding to the charge amount.

The drain of the reset transistor <NUM> and the drain of the amplification transistor <NUM> are connected to a power supply voltage VDD, for example. However, the drain of the reset transistor <NUM> may be connected to a reset voltage different from the power supply voltage VDD, for example. A source of the amplification transistor <NUM> is connected to a drain of the selection transistor <NUM>, and a source of the selection transistor <NUM> is connected to a vertical signal line VSL for inputting an analog pixel signal to a column analog to digital converter (column ADC) <NUM> to be described below.

When the pixel signal is read, a high-level transfer signal TRG is applied from the row drive circuit <NUM> to the gate of the switching transistor <NUM>. This turns on the switching transistor <NUM>, causing the charge accumulated in the cathode of the photoelectric conversion element <NUM> to be transferred to the floating diffusion region <NUM> through the switching transistor <NUM>. As a result, a pixel signal having a voltage value corresponding to the charge amount of the charge accumulated in the floating diffusion region <NUM> appears at the source of the amplification transistor <NUM>. Subsequently, by setting the selection signal SEL applied from the row drive circuit <NUM> to the gate of the selection transistor <NUM> to the high level, the pixel signal appearing in the source of the amplification transistor <NUM> appears in the vertical signal line VSL.

Further, when the charge accumulated in the floating diffusion region <NUM> is released to reset the floating diffusion region <NUM>, a high-level reset signal RST is applied from the row drive circuit <NUM> to the gate of the reset transistor <NUM>. This allows the charge accumulated in the floating diffusion region <NUM> to be discharged to the power supply side through the reset transistor <NUM> (FD reset). At that time, by turning on the switching transistor <NUM> during the same period, it is also possible to discharge the charge accumulated in the cathode of the photoelectric conversion element <NUM> to the power supply side (PD reset).

In each shared block <NUM>, the number of photoelectric conversion elements <NUM> simultaneously connected to the readout circuit <NUM> at the time of reading out the gradation image data, that is, the number of switching transistors <NUM> (transfer transistors) turned on during the same period of time is not limited to one, and may be plural. For example, when high-resolution gradation image data is read in each shared block <NUM>, the switching transistors <NUM> may be sequentially connected to the readout circuit <NUM> in time division, and when reading is executed with an expanded dynamic range at low illuminance or the like (at the time of binning), two or more switching transistors <NUM> may be turned on during the same period of time.

<FIG> is an example of a plan view of the detection chip according to the present embodiment. The detection chip <NUM> according to the present embodiment has a configuration in which a column ADC <NUM> for reading an analog pixel signal output from the gradation pixel <NUM> as a digital pixel signal is added to a configuration similar to the detection chip <NUM> described with reference to <FIG> in the first embodiment.

Each gradation pixel <NUM> causes an analog pixel signal to appear on the vertical signal line VSL under the control of the row drive circuit <NUM>, thereby supplying the analog pixel signal to the column ADC <NUM>. The column ADC <NUM> includes, for example, an AD converter for each vertical signal line VSL, and performs analog to digital (AD) conversion on an analog pixel signal input via each vertical signal line VSL. Subsequently, the column ADC <NUM> supplies the digital signal that has undergone AD conversion to the signal processing circuit <NUM>. The signal processing circuit <NUM> performs predetermined image processing on the image data including the digital signals. Note that the column ADC <NUM> may include, for example, a correlated double sampling (CDS) circuit and may reduce kTC noise included in a digital pixel signal.

The readout of the gradation image data may be executed, for example, by reading the pixel signals from all the gradation pixels <NUM> when the occurrence of the address event is detected in any of the detection pixels <NUM>, or may be executed by reading the pixel signals from the gradation pixels <NUM> belonging to the region where the occurrence of the address event is detected, in other words, the region where the object is detected by the detection pixel <NUM>. <FIG> depicts an operation example in which the object detection mode and the grayscale image read mode according to the present embodiment are switched in execution of operation. The present description will describe an exemplary case where the control section <NUM> (refer to <FIG>) in the imaging device <NUM> controls the operation mode of the solid-state imaging device <NUM>. However, control of the operation mode is not limited to this example and the signal processing circuit <NUM> in the solid-state imaging device <NUM> may be configured to control the operation mode. Further, the operation depicted in <FIG> may be terminated by, for example, an interruption operation or the like with respect to the control section <NUM> or the solid-state imaging device <NUM>.

As depicted in <FIG>, in the present operation, after activation, the control section <NUM> sets the object detection mode to the operation mode of the solid-state imaging device <NUM>, for example (step S201). The object detection mode is an operation mode of detecting occurrence of an address event, and may be, for example, a mode of executing the operation described with reference to <FIG> in the first embodiment.

Next, the control section <NUM> determines whether an object has been detected in the object detection mode (step S202), and continues the address event detection mode until the object is detected (NO in step S202). For example, the object detection determination may be similar to the operation described in steps S102, S105, and S108 in <FIG> in the first embodiment.

In a case where an object has been detected (YES in step S202), the control section <NUM> specifies a region where the object has been detected on the basis of frame data output from the solid-state imaging device <NUM> (step S203). Note that the region in which the object has been detected may be, for example, a region including pixels in which an on-event (or an off-event) has been detected.

Next, the control section <NUM> instructs the solid-state imaging device <NUM> to read the pixel signal from the region where the object has been detected (step S204). With this operation, gradation image data including the pixel signals read from the gradation pixel <NUM> belonging to the region where the object has been detected is output from the solid-state imaging device <NUM>.

As described above, according to the present embodiment, it is possible to perform not only the detection of the object based on the presence or absence of the address event but also the acquisition of the gradation image data of the region where the object has been detected or of all the pixels.

The above-described fourth embodiment is an exemplary configuration in which in which the readout circuit <NUM> is connected to the common line <NUM> in the configuration enabling readout of the gradation image data in addition to object detection. In comparison, in the fifth embodiment, a case where the readout circuit <NUM> is connected to a common line different from the common line <NUM> will be described with an example.

The configurations and operations of the imaging device and the solid-state imaging device according to the present embodiment may be similar to the configurations and operations of the imaging device <NUM> and the solid-state imaging device <NUM> according to the fourth embodiment described above, and thus, detailed description will be omitted here. However, in the present embodiment, the shared block <NUM> according to the fourth embodiment is replaced with a shared block <NUM> to be described below.

<FIG> is a circuit diagram depicting a schematic configuration example of a shared block according to the present embodiment. The shared block <NUM> exemplified below is based on the shared block <NUM> exemplified in <FIG>. However, the configuration is not limited thereto, and the shared block <NUM> may also be based on the shared block <NUM> according to the second embodiment or the shared block <NUM> according to the third embodiment, for example.

As depicted in <FIG>, the shared block <NUM> according to the present embodiment has a configuration in which cathodes of photoelectric conversion elements <NUM> in two or more or all logarithmic response sections 310An are connected by a common line <NUM> different from the common line <NUM> in a configuration similar to the shared block <NUM> described with reference to <FIG> in the first embodiment. The readout circuit <NUM> is connected to the common line <NUM>. In addition, a switching transistor <NUM> also functioning as a transfer transistor is provided between the readout circuit <NUM> and the photoelectric conversion element <NUM> of each logarithmic response section 310An, and connection between the photoelectric conversion element <NUM> and the readout circuit <NUM> is controlled by the switching transistor <NUM>. For example, the common line <NUM> may be an example of a second common line in the claims.

Further, the shared block <NUM> according to the present embodiment can also be formed based on the shared block <NUM> described in the second embodiment with reference to <FIG>, for example. Even in this case, as depicted in <FIG>, the shared block <NUM> has a configuration, as a configuration similar to the shared block <NUM> described with reference to <FIG>, in which the cathodes of the photoelectric conversion elements <NUM> in two or more or all of the logarithmic response sections 310An are connected by the common line <NUM>, the readout circuit <NUM> is connected to the common line <NUM>, and the switching transistor <NUM> is provided between the readout circuit <NUM> and the photoelectric conversion element <NUM> of each of the logarithmic response sections 310An.

In the above configuration, at the time of reading the pixel signal from the gradation pixel including the readout circuit <NUM>, the switching transistors <NUM> and <NUM> of all the logarithmic response sections 310An are turned off, and the switching transistors <NUM> of the gradation pixels corresponding to the individual logarithmic response sections 310An are sequentially connected to the readout circuit <NUM> in time division. However, at the time of binning, when reading is executed with an expanded dynamic range at low illuminance or the like, two or more switching transistors <NUM> are turned on during the same period of time, achieving execution of readout with an expanded dynamic range.

The above-described embodiment is an exemplary case in which the synchronous EVS that does not require arbitration of a request for requesting reading of a detection signal output from each shared block <NUM> or the like is applied to the solid-state imaging device <NUM>. However, the configuration is not limited to such an example. For example, as in the solid-state imaging device depicted in <FIG>, it is also allowable to apply an asynchronous EVS including a row arbiter <NUM> that arbitrates requests output from each row of the address event detecting section <NUM> and determines the order of readout rows of detection signals. Note that <FIG> depicts a detection chip <NUM> in the solid-state imaging device according to the present embodiment.

In this manner, even in a case where an asynchronous EVS is applied, it is possible to aggregate the photocurrents flowing out from the plurality of photoelectric conversion elements <NUM> into one logarithmic conversion circuit similarly to the above-described embodiments, making it possible to obtain a larger photocurrent amount. This achieves expansion of the dynamic range in the photocurrent detection, making it possible to obtain a sufficiently wide dynamic range even under conditions such as low illuminance.

On the other hand, in a case where sufficient illuminance can be obtained, by turning off the switching transistor <NUM> and turning on the switching transistor <NUM> in all or a necessary and sufficient number of logarithmic response sections 310An or the like, it is possible to operate all or the necessary and sufficient number of logarithmic response sections 310An or the like as one address event detection pixel, leading to achievement of detection of an address event at high resolution, reduction of operating power, and the like.

The technology according to the present disclosure (the present technology) is applicable to various products. The technology according to the present disclosure may be applied to devices mounted on any of moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots.

The vehicle control system <NUM> includes a plurality of electronic control units connected to each other via a communication network <NUM>. In the example depicted in <FIG>, the vehicle control system <NUM> includes a driving system control unit <NUM>, a body system control unit <NUM>, an outside-vehicle information detecting unit <NUM>, an in-vehicle information detecting unit <NUM>, and an integrated control unit <NUM>. In addition, a microcomputer <NUM>, a sound/image output section <NUM>, and a vehicle-mounted network interface (I/F) <NUM> are illustrated as a functional configuration of the integrated control unit <NUM>.

The outside-vehicle information detecting unit <NUM> detects information about the outside of the vehicle including the vehicle control system <NUM>. For example, the outside-vehicle information detecting unit <NUM> is connected with an imaging section <NUM>. The outside-vehicle information detecting unit <NUM> makes the imaging section <NUM> image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit <NUM> may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section <NUM> is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section <NUM> can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section <NUM> may be visible light, or may be invisible light such as infrared rays or the like.

In addition, the microcomputer <NUM> can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM> or the in-vehicle information detecting unit <NUM>.

In addition, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit <NUM>.

The sound/image output section <NUM> transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of <FIG>, an audio speaker <NUM>, a display section <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display section <NUM> may, for example, include at least one of an on-board display and a head-up display.

The imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle <NUM> as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section <NUM> provided to the front nose and the imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle <NUM>. The imaging sections <NUM> and <NUM> provided to the sideview mirrors obtain mainly an image of the sides of the vehicle <NUM>. The imaging section <NUM> provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle <NUM>. The imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, <FIG> depicts an example of photographing ranges of the imaging sections <NUM> to <NUM>. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the front nose. Imaging ranges <NUM> and <NUM> respectively represent the imaging ranges of the imaging sections <NUM> and <NUM> provided to the sideview mirrors. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the rear bumper or the back door. A bird's-eye image of the vehicle <NUM> as viewed from above is obtained by superimposing image data imaged by the imaging sections <NUM> to <NUM>, for example.

At least one of the imaging sections <NUM> to <NUM> may have a function of obtaining distance information. For example, at least one of the imaging sections <NUM> to <NUM> may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer <NUM> can determine a distance to each three-dimensional object within the imaging ranges <NUM> to <NUM> and a temporal change in the distance (relative speed with respect to the vehicle <NUM>) on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle <NUM> and which travels in substantially the same direction as the vehicle <NUM> at a predetermined speed (for example, equal to or more than <NUM>/hour). Further, the microcomputer <NUM> can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

Hereinabove, an example of the vehicle control system to which the technology according to the present disclosure is applicable has been described. The technology according to the present disclosure can be suitably applied to the imaging section <NUM> among the configurations described above. Specifically, the imaging device <NUM> in <FIG> can be applied to the imaging section <NUM>. By applying the technology according to the present disclosure to the imaging section <NUM>, it is possible to achieve microfabrication of pixels and higher visibility in captured image, leading to alleviation of driver's fatigue.

Note that the above-described embodiment depicts an example for embodying the present technology, and thus, the matters in the embodiment and the invention specifying matters in the claims have a correspondence relationship. Similarly, the matters specifying the invention in the claims and the matters in the embodiments of the present technology denoted by the same names as the matters specifying the invention have a correspondence relationship. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the scope of the invention as defined by the appended claims.

Claim 1:
A solid-state imaging device (<NUM>) comprising:
a plurality of detection pixels configured to each output a luminance change of incident light;
a detection circuit (<NUM>) configured to output an event signal based on the luminance change output from each of the detection pixels (<NUM>); and
a first common line (<NUM>; <NUM>) connecting the plurality of detection pixels (<NUM>) to each other,
wherein each of the detection pixels (<NUM>) includes:
a photoelectric conversion element (<NUM>;
a logarithmic conversion circuit configured to convert a photocurrent flowing out of the photoelectric conversion element (<NUM>) into a voltage signal corresponding to a logarithmic value of the photocurrent;
a first circuit (<NUM>) configured to output a luminance change of incident light incident on the photoelectric conversion element (<NUM>) based on the voltage signal output from the logarithmic conversion circuit;
a first transistor (<NUM>) connected between the photoelectric conversion element (<NUM>) and the logarithmic conversion circuit;
a second transistor (<NUM>) connected between the photoelectric conversion element (<NUM>) and the first common line (<NUM>), and
the detection circuit (<NUM>) includes a second circuit (<NUM>) that outputs the event signal based on the luminance change output from each of the detection pixels (<NUM>);
a second common line (<NUM>; <NUM>) connecting the plurality of detection pixels (<NUM>) to each other;
a plurality of fourth transistors (<NUM>) connected between the photoelectric conversion element (<NUM>) in each of the detection pixels (<NUM>) and the second common line (<NUM>; <NUM>); and
a readout circuit (<NUM>) that is connected to the second common line (<NUM>; <NUM>) generates a pixel signal having a voltage value corresponding to charge accumulated in the photoelectric conversion element (<NUM>); and
wherein the readout circuit (<NUM>) includes:
a reset transistor (<NUM>) connected between the second common line (<NUM>; <NUM>) and a power supply line; and
an amplification transistor (<NUM>) having a gate connected to the second common line (<NUM>; <NUM>).