Patent Description:
Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system.

<CIT> discloses techniques to more accurately read values stored in data cells. In an aspect, one reference cell is provided for each group of data cells having similar configuration (e.g., similar layout and orientation). For split-gate memory cells arranged in pairs, each pair includes two data cells implemented as mirrored image of one another. Two reference cells may then be used, one reference cell for each data cell in a pair. In another aspect, the data paths for the reference and data cells for read operation are matched. This matching may be achieved by using the same circuit design for the data and reference sense amplifiers, using the same layout and orientation for the sense amplifiers, matching the lines for the two data paths, matching the structure (e.g., length and width) and the diffusion region (e.g., doping concentration and contact) for the sense amplifiers and lines, and so on.

<CIT> discloses an integrated circuit device having a memory. A plurality of identical versions of a given piece of data may be stored at different addresses in the memory, and portions thereof read out in time-division fashion through a reduced number of sense amplifiers and common signal lines to majority logic circuitry, so as to enhance reliability while at the same time reducing the amount of area required on an integrated circuit chip.

<CIT> discloses that to provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.

<CIT> discloses that the present invention provides a data processing system wherein the waste of use of each storage area by ECC codes is avoided to improve or increase the number of assurances for rewriting of information stored in a non-volatile memory. A data processing system (<NUM>) has an erasable and programmable non-volatile memory (<NUM>) and a central processing unit (<NUM>). The central processing unit allows only a specified partial storage area (20Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can be avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.

Non-volatile memory systems are well-known in the prior art. <FIG> depicts prior art non-volatile memory system <NUM>. Non-volatile memory system <NUM> comprises array <NUM>, row decoder <NUM>, column decoder <NUM>, and sense amplifier <NUM>. Array <NUM> comprises an array of non-volatile memory cells arranged in rows and columns. Row decoder <NUM> is coupled to each row of non-volatile memory cells in array <NUM> and enables one or more rows for read, erase, or program operations, typically in response to a received row address. Column decoder <NUM> is coupled to each column of non-volatile memory cells in array <NUM> and enables one or more columns for read, erase, or program operations, typically in response to a received column address. When the non-volatile memory cells are flash memory cells, row decoder <NUM> typically is coupled to a word line of each row of cells, and column decoder <NUM> typically is coupled to a bit line of each column of cells. Sense amplifier <NUM> is used during a read operation to sense the value stored in the selected cell or cells.

Various designs of non-volatile memory cells are known in the prior art. For example, <CIT> ("the '<NUM> patent") discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell <NUM> is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in semiconductor substrate <NUM>, with channel region <NUM> there between. Floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. Word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal <NUM> in relation to the substrate region <NUM> which causes electrons on the floating gate <NUM> to tunnel through the intermediate insulation from the floating gate <NUM> to the word line terminal <NUM> via Fowler-Nordheim tunneling.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source region <NUM>. Electrons will flow from the drain region <NUM> toward the source region <NUM>. The electrons will accelerate and become heated when they move through the channel region <NUM> under the gap between the word line terminal <NUM> and the floating gate <NUM>, and the channel region <NUM> under the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM> and the reduction in oxide energy barrier caused by said force.

Memory cell <NUM> is read by placing positive read voltages on the drain region <NUM> and word line terminal <NUM> (which turns on the portion of the channel region <NUM> under the word line terminal) in relation to the source region <NUM>. If the floating gate <NUM> is positively charged (i.e. erased of electrons), then the portion of the channel region <NUM> under the floating gate <NUM> is turned on as well, and current will flow across the channel region <NUM> to the source region <NUM>, which is sensed as the erased or "<NUM>" state. If the floating gate <NUM> is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate <NUM> is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region <NUM> to the source region <NUM>, which is sensed as the programmed or "<NUM>" state.

Table No. <NUM> depicts typical voltage/current ranges that can be applied to the terminals of memory cell <NUM> for performing read, erase, and program operations:.

Other split gate memory cell configurations, which are other types of flash memory cells, are known. For example, <FIG> depicts a four-gate memory cell <NUM> comprising source region <NUM>, drain region <NUM>, floating gate <NUM> over a first portion of channel region <NUM>, a select gate <NUM> (typically coupled to a word line, WL) over a second portion of the channel region <NUM>, a control gate <NUM> over the floating gate <NUM>, and an erase gate <NUM> over the source region <NUM>.

<FIG> depicts a three-gate memory cell <NUM>, which is another type of flash memory cell. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate. The erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of the <FIG> except there is no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line during a program operation to compensate for a lack of control gate bias.

The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbonnanotube) memory, OTP (bi-level or multi-level one time programmable), and CeRAM (correlated electron ram), without limitation.

With reference to <FIG>, prior art non-volatile memory system <NUM> sometimes creates and maintains protected area <NUM> within array <NUM>. Protected area <NUM> can then be used to store configuration data, trim data, fuses, and other types of data that are essential to the operation of non-volatile memory system <NUM>, which will be referred to herein as "system data" or "system bits". User data will not be stored in protected area <NUM>, and, optionally, protected area <NUM> is not accessible for read, erase, and program operations initiated from a source outside of non-volatile memory system <NUM>.

Because the data stored in protected area <NUM> is critical to the accurate functioning of non-volatile memory system <NUM>, the data stored in protected area <NUM> needs extra protection from low-probability data loss events such as charge loss, charge movement, read disturb, radiation-induced soft errors, and other mechanisms which cause changes in the read current/voltage of a small fraction of the cells.

One prior art approach is to store each system bit in protected area <NUM> in two non-volatile memory cells in a redundant fashion. In one approach, the read current from the two cells can be summed and compared against a reference value to determine the stored value.

However, even with redundancy, in some non-volatile memory cell designs, charge loss, charge redistribution, disturb, or other physical changes in the non-volatile memory cells will cause the cells to flip predominantly from a "<NUM>" state to "<NUM>" state, or from a "<NUM>" state to "<NUM>" state depending on the architecture of the non-volatile memory cell.

This can corrupt the system bit. For example, if one of two non-volatile memory cells flips from a"<NUM>" state to a "<NUM>" state, the total read current will exceed the reference current, and the sensed data will flip from "<NUM>" to "<NUM>.

What is needed is an embodiment for storing important system data in a non-volatile memory array so that the system data is less likely to become corrupted from charge loss, charge redistribution, disturb effects, or other physical changes in the non-volatile memory cell which cause a change in the read current or voltage, without limitation.

The present invention is set out in the independent claim.

Advantageous features are defined in dependent claims <NUM> and <NUM>.

<FIG> depict embodiments that are particularly suitable for non-volatile memory (NVM) cell designs where a charge loss, charge redistribution, disturb, or other physical or electrical changes in the NVM cell will cause a cell to gravitate towards a "<NUM>" state, which might flip a stored "<NUM>" to a "<NUM>" but will not affect a stored "<NUM>".

<FIG> depicts system data architecture <NUM>. Each bit of system data is written into two redundant NVM cells, such as cells <NUM> and <NUM>, located in the same row accessible by the same word line, such as wordline <NUM>, and in different columns accessible by different bit lines, such as bit lines <NUM> and <NUM>.

During a read operation, current from NVM cells <NUM> and <NUM> are simultaneously but independently sensed by sense amplifier <NUM> against a reference current to determine their respective logic states. Data read from the two cells as output by sense amplifier <NUM> (which indicates a first value stored one of the two NVM cells <NUM>, <NUM> and a second value stored in the other of the two NVM cells <NUM>, <NUM>) are routed through AND device <NUM> (a logic device performing an AND function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by "Output").

If NVM cells <NUM> and <NUM> originally stored a "<NUM>" and neither cell has flipped, then the output will be a "<NUM>". If NVM cells <NUM> and <NUM> originally stored a "<NUM>" and one of the two NVM cells <NUM>, <NUM> has flipped from a "<NUM>" to a "<NUM>," the output will still be a "<NUM>" because the output of AND device <NUM> will be "<NUM>". The probability of both NVM cells flipping from a "<NUM>" to a "<NUM>" is extremely low.

If NVM cells <NUM> and <NUM> originally stored a <NUM>, then it is expected that both NVM cells <NUM> and <NUM> will still store a "<NUM>" because the underlying NVM cell architecture is assumed to be of the type where a leakage or disturb will cause a "<NUM>" to flip to a "<NUM>" but will not cause a "<NUM>" to flip to a "<NUM>". Bitline <NUM> and wordline <NUM> are shown for completeness.

<FIG> depicts system data architecture <NUM>. Each bit of system data is written into two redundant NVM cells. The redundant NVM cells each can be located in any row and in any column. That is, there is no restriction on where the redundant NVM cells can be placed, and they need not be located in the same row or column or adjacent rows or columns. In this example, a pair of redundant bits are stored in NVM cell <NUM> accessible by wordline <NUM> and bit line <NUM> and in NVM cell <NUM> accessible by wordline <NUM> and bitline <NUM>. Bitline <NUM> and wordline <NUM> are shown for completeness.

During a read operation, current from NVM cells <NUM> and <NUM> are independently sensed by sense amplifier <NUM> against a reference current to determine their respective logic states. Read data from the two NVM cells output by sense amplifier <NUM> (which indicates a first value stored one of the two NVM cells <NUM>, <NUM> and a second value stored in the other of the two NVM cells <NUM>, <NUM>) are processed with AND device <NUM> (a logic device performing an AND function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by "Output").

If NVM cells <NUM> and <NUM> originally stored a "<NUM>" and neither cell has flipped, then the output will be a "<NUM>". If NVM cells <NUM> and <NUM> originally stored a "<NUM>" and one of the two NVM cells <NUM>, <NUM> has flipped from a "<NUM>" to a "<NUM>," the final data will still be a "<NUM>" because the output of the AND operation will be "<NUM>". The probability of both NVM cells <NUM> and <NUM> flipping from a "<NUM>" to a "<NUM>" is extremely low.

If NVM cells <NUM> and <NUM> originally stored a "<NUM>", then it is expected that both will still store a "<NUM>" because the underlying NVM cell architecture is assumed to be of the type where a leakage, disturb, or other changes will cause a "<NUM>" to flip to a "<NUM>" but will not cause a "<NUM>" to flip to a "<NUM>".

<FIG> depicts system data architecture <NUM>. Each bit of system data is written into two redundant NVM cells, such as NVM cells <NUM> and <NUM>, located in the same column accessible by the same bit line, such as bitline <NUM>, but located in different rows accessible by different wordlines, such as wordlines <NUM> and <NUM>. Bitlines <NUM>, <NUM> and wordline <NUM> are shown for completeness.

During a read operation, both wordlines <NUM> and <NUM> are selected. Read current from NVM cells <NUM> and <NUM> are combined in the common bitline <NUM>. The summed current is sensed by sense amplifier <NUM> against a reference current to determine its logic state. The reference current is set to a level within a range which is: higher than the sum of a typical <NUM>-state read current for the NVM cells and the upper limit of a neutral floating gate (FG) read current (for NVM cells which use charge storage in a polysilicon FG, where the upper limit refers to the upper limit of the range of neutral FG read current for NVM cells in the array); or higher than the sum of typical <NUM>-state read current plus the saturation point of <NUM>-state read current movement (for NVM cells which use other storage mechanisms). The reference level is also lower than two times the lower limit of read current of <NUM>-state cells which are read immediately after being set to <NUM>-state.

During production test screen of a device following system data architecture <NUM>, a read with the reference current within the above mentioned range is performed on the protected area <NUM>, to guarantee that the two NVM cells <NUM> and <NUM> can be erased sufficiently to ensure the combined read current exceeds the reference level, under worst-case erase and read conditions, where the "worst case" is the weakest erase and read conditions across specified process/temperature/voltage ranges, which can vary from technology to technology. These conditions typically are captured during testing.

If the stored data in selected NVM cells <NUM> and <NUM> is a "<NUM>" and neither NVM cell flips, then the final data output by sense amplifier <NUM>, (indicated by "Output") is still a "<NUM>". If the stored data in selected NVM calls <NUM> and <NUM> is "<NUM>", and one of the two NVM cells <NUM>, <NUM> has flipped from a "<NUM>" to a "<NUM>," the combined read current of the two NVM cells will saturate before it exceeds the reference current, and the final data will still be deemed by sense amplifier <NUM> to be a "<NUM>". The probability of both NVM cells <NUM>, <NUM> flipping from a "<NUM>" to a "<NUM>" is extremely low.

If NVM cells <NUM> and <NUM> originally stored a "<NUM>", then it is expected that both NVM cells <NUM>, <NUM> will still store a "<NUM>" because the underlying NVM cell architecture is assumed to be of the type where a leakage, disturb, or other changes will cause a "<NUM>" to flip to a "<NUM>" but will not cause a "<NUM>" to flip to a "<NUM>".

<FIG> depict embodiments that are particularly suitable for NVM cell designs where a charge loss, charge redistribution, or disturb will cause a cell to gravitate towards a "<NUM>" state, which might flip a stored "<NUM>" to a "<NUM>" but will not affect a stored "<NUM>".

<FIG> depicts system data architecture <NUM>. Each bit of system data is written into two redundant NVM cells, such as cells <NUM> and <NUM>, located in the same row accessible by the same wordline, such as wordline <NUM>, but located in different columns accessible by different bitlines, such as bitlines <NUM> and <NUM>. Bitline <NUM> and wordlines <NUM>, <NUM> are shown for completeness.

During a read operation, current from NVM cells <NUM> and <NUM> are simultaneously but independently sensed against a reference current by sense amplifier <NUM> to determine a first value stored in NVM cell <NUM> and a second value stored in NVM <NUM>. Read data from the two NVM cells output by sense amplifier <NUM> are processed with OR device <NUM> (a logic device performing an OR function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by "Output").

If NVM cells <NUM> and <NUM> originally stored a "<NUM>" and neither cell has flipped, then the output will be a "<NUM>". If NVM cells <NUM> and <NUM> originally stored a "<NUM>" and one of the two NVM cells has flipped from a "<NUM>" to a "<NUM>," the final data will still be a "<NUM>" because the output of OR device <NUM> will be "<NUM>". The probability of both NVM cells <NUM>, <NUM> flipping from a "<NUM>" to a "<NUM>" is extremely low.

If NVM cells <NUM> and <NUM> originally stored a "<NUM>", then it is expected that both NVM cells <NUM>, <NUM> will still store a "<NUM>" because this scheme will only be used in NVM cell architecture where leakage, disturb, or other changes will cause a "<NUM>" to flip to a "<NUM>" but will not cause a "<NUM>" to flip.

<FIG> depicts system data architecture <NUM>. Each bit of system data is written into two redundant NVM cells. The redundant NVM cells each can be located in any row and column. That is, there is no restriction on where the NVM cells can be placed, and they need not be located in the same row or column or adjacent rows or columns.

In this example, a pair of redundant bits are stored in NVM cell <NUM> accessible by wordline <NUM> and bit line <NUM> and in NVM cell <NUM> accessible by wordline <NUM> and bitline <NUM>. Bitline <NUM> and wordline <NUM> are shown for completeness.

During a read operation, current from NVM cells <NUM> and <NUM> are independently sensed against a reference current by sense amplifier <NUM> to determine a first value stored in NVM cell <NUM> and a second value stored in NVM cell <NUM>. Read data from the two NVM cells output by sense amplifier <NUM> are processed with OR device <NUM> (a logic device performing an OR function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by "Output").

If NVM cells <NUM> and <NUM> originally stored a "<NUM>" and neither NVM cell has flipped, then the output will be a "<NUM>". If NVM cells <NUM> and <NUM> originally stored a "<NUM>" and one of the two NVM cells has flipped from a "<NUM>" to a "<NUM>," the final data will still be a "<NUM>" because the output of OR device <NUM> will be "<NUM>". The probability of both NVM cells <NUM>, <NUM> flipping from a "<NUM>" to a "<NUM>" is extremely low.

<FIG> depicts an embodiment that is suitable for: (<NUM>) NVM cell designs where a charge loss, charge redistribution, disturb, or other physical changes to the cell will cause a cell to gravitate towards a "<NUM>" state, which might flip a stored "<NUM>" to a "<NUM>" but will not affect a stored "<NUM>"; (<NUM>) NVM cell designs where aforementioned changes will cause a cell to gravitate towards a "<NUM>" state, which might flip a stored "<NUM>" to a "<NUM>" but will not affect a stored "<NUM>"; and (<NUM>) NVM cell designs where aforementioned changes will cause an NVM cell to gravitate towards either state, which might flip some stored "<NUM>"s to "<NUM>"s but also might flip some stored "<NUM>"s to "<NUM>"s.

<FIG> depicts system data architecture <NUM>. Here, each word of system data, such as word <NUM>, is stored with associated error correction code data, such as error correction code (ECC) data <NUM> in a row. Each system bit is stored in a word and is stored without redundancy. Multiple words may be stored in a row, each with there associated error correction code data, without exceeding the scope.

Here, ECC data <NUM> is generated for word <NUM> using an ECC, such as the Hamming code, or a code generated by the majority voter algorithm (where data is stored in N redundant physical cells and the value of the stored data is deemed to be the value indicated by a majority of the N cells), to perform error detection and error correction such as <NUM>-bit error detection and <NUM>-bit error correction scheme. In place of ECC data <NUM>, a parity bit scheme may be utilized to indicate error detection without correction. When bit <NUM> is read, the entire word <NUM> and ECC data <NUM> are read by sense amplifier <NUM> and sent to ECC engine <NUM>. That is, sense amplifier <NUM> receives current from the array and outputs a word and error correction code data for the word to ECC engine <NUM>. If any single bit in word <NUM> has flipped in either direction, the error will be detected and/or corrected successfully by ECC engine <NUM>. The probability of more than one bit flipping is extremely low.

In one embodiment, system data architecture <NUM> is additionally implemented with redundancy such as using multiple cells for each system bit to further enhance the reliability such as for functional safety for automotive applications. For example, each system bit can be stored in two cells in two rows or two columns, as described in previous embodiments.

In one embodiment, ECC engine <NUM> is implemented using an external controller or firmware.

Claim 1:
A non-volatile memory system comprising a logic circuit to counteract data corruption, the system, comprising:
an array of non-volatile memory cells arranged into rows and columns, wherein the non-volatile memory cells are of a type that gravitates toward a "<NUM>" state;
a sense amplifier (<NUM>) configured during a read operation to receive current from a first non-volatile memory cell (<NUM>, <NUM>, <NUM>, <NUM>) in a first column of the array and to indicate a first value stored in the first non-volatile memory cell and to receive current from a second non-volatile memory cell (<NUM>, <NUM>, <NUM>, <NUM>) in a second column of the array and to indicate a second value stored in the second non-volatile memory cell, wherein redundant data previously was stored in the first non-volatile memory cell and the second non-volatile memory cell; and
a logic circuit for receiving from the sense amplifier the indicated first value and the indicated second value and for generating a data bit output based on the indicated first value and the indicated second value, the logic circuit comprising:
an AND gate (<NUM>) to perform an AND operation on the indicated first value and the indicated second value wherein a value of "<NUM>" for the data bit output indicates the redundant data was a "<NUM>" and a value of "<NUM>" for the data bit output indicates the redundant date was a "<NUM>".