Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

<CIT> discloses a method of forming a staircase in a semiconductor device using a linear alignmnent control feature. <CIT> discloses semiconductor devices having dummy patterns and methods of fabricating the same.

Embodiments of a marking pattern in forming the staircase structure of a 3D memory device are disclosed.

The present invention relates to a semiconductor device according to claim <NUM>.

Although specific configurations and arrangements are discussed, this should be understood that this is done for illustrative purposes only. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to "one embodiment", "an embodiment", "an example embodiment", "some embodiments", etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic.

Similarly, terms, such as "a", "an", or "the", again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.

As used herein, a staircase structure refers to a set of surfaces that include at least two horizontal surfaces (e.g., along x-y plane) and at least two (e.g., first and second) vertical surfaces (e.g., along z-axis) such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A "step" or "staircase" refers to a vertical shift in the height of a set of adjoined surfaces. In the present disclosure, the term "staircase" and the term "step" refer to one level of a staircase structure and are used interchangeably. In the present disclosure, a horizontal direction can refer to a direction (e.g., the x-axis or the y-axis) parallel with the top surface of the substrate (e.g., the substrate that provides the fabrication platform for formation of structures over it), and a vertical direction can refer to a direction (e.g., the z-axis) perpendicular to the top surface of the structure.

In the present disclosure, a staircase structure is formed from a dielectric stack that includes a plurality of alternatingly arranged dielectric pairs (e.g., insulating material layer/sacrificial material layer pair) by repetitively etching the dielectric pairs using an etch mask, e.g., a PR layer over the dielectric stack layer. The insulating material layer and the underlying sacrificial material layer in one dielectric pair can have the same or different thicknesses. In some embodiments, one or more dielectric pairs can form one step. During the formation of the staircase structure, the PR layer is trimmed (e.g., etched incrementally and inwardly from the boundary of the dielectric stack layer, often from all directions) and used as the etch mask for etching the exposed portion of the dielectric stack. The amount of trimmed PR can be directly related (e.g., determinant) to the dimensions of the staircases. The trimming of the PR layer can be obtained using a suitable etch, e.g., an isotropic dry etch or a wet etch. One or more PR layers can be formed and trimmed consecutively for the formation of the staircase structure. Each dielectric pair can be etched, after the trimming of the PR layer, using suitable etchants to remove a portion of both the insulating material layer and the underlying sacrificial material layer. The etched insulating material layer and the sacrificial material layers are referred to as insulating layers and sacrificial layers. After the formation of the staircase structure, the PR layer can be removed and the sacrificial layers can be replaced with metal/conductor layers (e.g., tungsten). The metal/conductor layers can form the gate electrodes (or word lines) of the 3D memory device.

In the fabrication of 3D memory devices, an etch mask, e.g., a PR layer, is often employed for the etching and formation of 3D features such as staircases. For example, the PR layer is formed to cover a device area and is repetitively trimmed to expose a portion of the device area. The exposed portion of the device area can then be removed. The PR layer can be repetitively trimmed in a fabrication process for the formation of a number of staircases. To meet the demands in higher storage capacity, more memory cells are desired in a 3D memory device. One approach to form an increased number of memory cells is to increase the number of staircases stacking over a substrate of the 3D memory device for the formation of more conductor layers (i.e., gate electrodes) and thus more memory cells. A thicker etch mask is then needed for the formation of the staircases. To ensure the etch mask is trimmed at a desired rate (e.g., so the staircases can have desired dimensions) marking patterns are used to monitor/control the trimming rate of the etch mask during and/or after the trimming process. In an example, a distance between a marking pattern and the PR layer is measured (e.g., repeatedly) in real time to determine and/or monitor the trimming rate of the PR layer.

However, in the existing fabrication process of a 3D memory device, a marking pattern often includes a single marking structure in a marking area neighboring a device area where a stack structure of a plurality of staircases are formed. The pattern density (e.g., a percentage of surface area occupied by features) of the device area can be different from the pattern density of the marking area, causing loading effect (e.g., the difference in etch rate caused by the difference in pattern density) to take place. For example, the pattern density of the device area can be higher than the pattern density of the marking area, causing the etch rate on the marking pattern to be faster than desired. Also, the higher pattern density of device area can cause the marking pattern to be unevenly etched during the formation of the staircases. The resulted marking pattern can "shift" horizontally (e.g., along the x-direction). The change in the horizontal location of the marking pattern can cause the measurement of distance (e.g., along the horizontal direction) between the marking pattern and a staircase to have reduced precision.

<FIG> illustrate the issue. At the beginning (T (time)=t0) of a fabrication process, a marking pattern <NUM> is formed at the same with a staircase pattern <NUM> at a top portion of a stack structure <NUM>. Stack structure <NUM> is over a substrate <NUM>. Stack structure <NUM> includes a stack of interleaved insulating material layers <NUM>-<NUM> (e.g., silicon oxide) and sacrificial material layers <NUM>-<NUM> (e.g., silicon nitride) arranged vertically (along the z-axis) over substrate <NUM>. Stack structure <NUM> is patterned to form marking pattern <NUM>, which includes a single marking structure neighboring a staircase pattern <NUM>. The horizontal location of marking structure <NUM> is reflected by a distance D<NUM> from an edge of staircase pattern <NUM> to the central line (e.g., along the horizontal direction or the x-direction) of marking structure <NUM>. The position of the edge of staircase pattern <NUM> can be transferred to the position of the edge of a bottom staircase in subsequent staircase-forming process. The central line of marking structure <NUM> can be used as a reference for determining a trimming rate of a PR layer in the etching of the staircases.

After the formation of marking structure <NUM>, a PR layer (e.g., "PR" in <FIG>) is formed to cover staircase pattern <NUM>. The PR layer is repetitively trimmed to expose portions of stack structure <NUM>. The exposed portions of stack structure <NUM> are repetitively etched away to form a plurality of staircases stacking along substrate <NUM> along the vertical direction. As shown in <FIG>, after several staircases are formed (e.g., at T=tn), the loading effect already causes a noticeable difference between etching profile of marking pattern <NUM> on the side farther away from the staircases and the etching profile of marking pattern <NUM> on the side closer to the staircases. Marking structure <NUM> "shifts" away from its original horizontal location at T=t0, as shown by a decreased distance between the central line of marking structure <NUM> and the edge of bottom staircase Sn, as reflected by a distance Dn between the central line of marking structure <NUM> and the edge of the bottom staircase Sn. The dimensions of marking structure <NUM> are also reduced at least along the horizontal direction. Marking structure <NUM> thus can cause an error when used for the measuring of trimming rate of the PR.

Various embodiments in accordance with the present disclosure provide marking patterns and a method for photoresist trimming rate control in forming a three-dimensional (3D) memory device. Using the structures and method, a marking structure (also a central line of the marking structure) is less likely to shift horizontally during the etching of staircases, increasing the precision in trimming rate control of the PR layer. A marking pattern is provided to compensate/reduce the loading effect on the marking structure, which is part of the marking pattern. Specifically, the marking pattern can reduce the difference between the etch rates on the side farther away from the staircases and on the side closer to the staircases. The etching of the marking structure can have increased symmetry, reducing the horizontal "shift" of the marking structure in the formation of staircases. In some embodiments, the marking pattern is formed from the etching of a stack structure that includes a plurality of interleaved layers of insulating material and sacrificial material. In some embodiments, each marking structure of the marking pattern includes at least one layer of the insulating material and at least one layer of the sacrificial material, interleaved along the vertical direction (e.g., the z-axis).

<FIG> illustrates a structure <NUM> having a stack structure <NUM> and a marking pattern <NUM> neighboring stack structure <NUM> over a substrate <NUM>, according to some embodiments. Structure <NUM> can be formed after the etching of all the staircases is completed. In some embodiments, stack structure <NUM> is formed in a device area <NUM> and marking pattern <NUM> is formed in a marking area <NUM> neighboring device area <NUM>. Substrate <NUM> can include any suitable material for forming a 3D memory device. For example, substrate <NUM> can include silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), glass, gallium nitride, gallium arsenide, and/or other suitable III-V compounds.

Stack structure <NUM> includes a plurality of interleaved insulating layers and sacrificial layers arranged vertically (along the z-axis) over substrate <NUM>. In some embodiments, each insulating layer and a corresponding sacrificial layer form a staircase. The corresponding sacrificial layer can be directly on top of the insulating layer or directly underlying the insulating layer. For ease of description, in the present disclosure, a staircase includes an insulating layer and an underlying sacrificial layer. In some embodiments, stack structure <NUM> includes a plurality of staircases (S<NUM>,. , Sn-<NUM>, Sn) stacking over substrate <NUM>. The sacrificial layers are subsequently replaced with conductor layers for forming a plurality of word lines of the 3D memory device. In some embodiments, sacrificial layers include any suitable material different from insulating layers. For example, sacrificial layers can include poly-crystalline silicon, silicon nitride, poly-crystalline germanium, and/or poly-crystalline germanium-silicon. In the claimed invention, sacrificial layers include silicon nitride. Insulating layers can include any suitable insulating materials, e.g., silicon oxide. Stack structure <NUM> can be formed by alternatingly depositing sacrificial material layers and insulating material layers over substrate <NUM> and subsequently etching each dielectric pair (e.g., including an insulating material layer and an underlying sacrificial material layer) to form staircases along the z-axis. The deposition of sacrificial material layers and insulating material layers can include any suitable deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and/or atomic layer deposition (ALD). In some embodiments, the sacrificial material layers and the insulating material layers are each formed by CVD.

Marking pattern <NUM> includes a plurality of marking structures (e.g., <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>) located neighboring stack structure <NUM> over substrate <NUM>. The layout of the marking structures in marking pattern <NUM> can reduce the loading effect on the marking structure that is used as the reference for determining a trimming rate of the PR layer. The actual number of marking structures is not reflected in marking pattern <NUM> shown in <FIG>. <FIG> illustrate a first layout <NUM> of marking pattern <NUM>. <FIG> illustrate a second layout <NUM> of marking pattern <NUM>.

<FIG> illustrates a top view of first layout <NUM> of marking pattern <NUM> during a formation of staircases, according to some embodiments. <FIG> illustrates a cross-sectional view of first layout <NUM> during the formation of staircases, according to some embodiments. <FIG> illustrates a cross-sectional view of first layout <NUM> after the formation of staircases, according to some embodiments. As shown in <FIG>, during the formation of staircases in stack structure <NUM>, a PR layer (e.g., "PR" in <FIG>) is trimmed repetitively and functioning as an etching mask for the etching of staircases. Stack structure <NUM> may include a plurality of insulating material layers <NUM>-<NUM> and sacrificial material layers <NUM>-<NUM> arranged alternatingly over substrate <NUM>.

Marking pattern <NUM> may be located in marking area <NUM> and may include a central marking structure <NUM>-<NUM>. A central line of central marking structure <NUM>-<NUM> may be used as a reference to determine a trimming rate of the PR layer. In some embodiments, central marking structure <NUM>-<NUM> (or the central line of central marking structure <NUM>-<NUM>) divides marking area <NUM> into a first marking sub-area <NUM>-<NUM> and a second marking sub-area <NUM>-<NUM>. First marking sub-area <NUM>-<NUM> may be farther away from stack structure <NUM> (or the PR layer). Second marking sub-area <NUM>-<NUM> may be closer to stack structure <NUM> (or the PR layer). In some embodiments, a pattern density of first marking sub-area <NUM>-<NUM> is nominally the same as a pattern density of second marking sub-area <NUM>-<NUM>. The same pattern density of first marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> may reduce the loading effect on the etching of central marking structure <NUM>-<NUM>, resulting in a more evenly etched profile on central marking structure <NUM>-<NUM>.

In some embodiments, the size/range of marking area <NUM> is determined based on the available area that can be used for forming marking area <NUM> on substrate <NUM> and/or stack structure <NUM>. First marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> may have the same or different dimensions. In some embodiments, first marking sub-area <NUM>-<NUM> includes one or more first marking structures and second marking sub-area <NUM>-<NUM> includes one or more second marking structures. The number, distribution, shapes, and/or dimensions of respective marking structures in first marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> are arranged to cause the pattern densities of first marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> to be nominally the same. The specific number, distribution, shapes, and/or dimensions of the marking structures in each sub-area should be determined according to different designs and/or fabrication of the 3D memory device and should not be limited by the embodiments of the present disclosure. In some embodiments, central marking structure <NUM>-<NUM> has symmetric dimensions and shapes about the central line. Central marking structure <NUM>-<NUM> includes a plurality of interleaved layers of insulating material and sacrificial material. For example, as shown in <FIG>, central marking structure <NUM>-<NUM> includes four interleaved layers of insulating material and sacrificial material (e.g., formed from the patterning of two dielectric pairs in marking area <NUM>).

In an example, as shown in <FIG>, first marking sub-area <NUM>-<NUM> includes a first marking structure <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> includes a second marking structure <NUM>-<NUM>. First marking structure <NUM>-<NUM> and second marking structure <NUM>-<NUM> can be evenly spaced from central marking structure <NUM>-<NUM> along the horizontal direction (e.g., the x-axis). In some embodiments, along the horizontal direction, a distance between the central line of central marking structure <NUM>-<NUM> and a central line of first marking structure <NUM>-<NUM> is the same as a distance between the central line of central marking structure <NUM>-<NUM> and a central line of second marking structure <NUM>-<NUM>. The distances are each shown as "d<NUM>" in <FIG>. In some embodiments, first marking structure <NUM>-<NUM> and second marking structure <NUM>-<NUM> have the same shape and dimensions. That is, first marking structure <NUM>-<NUM> and second marking structure <NUM>-<NUM> are distributed symmetrically on opposite sides of central marking structure <NUM>-<NUM> along the horizontal direction. In some embodiments, first marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> have the same dimensions and areas, and all marking structures (e.g., central marking structure <NUM>-<NUM>, first marking structure <NUM>-<NUM>, and second marking structure <NUM>-<NUM>) in marking area <NUM> are identical in shapes and dimensions. The marking structures are distributed symmetrically about the central line of central marking structure <NUM>-<NUM> in marking pattern <NUM>. In some embodiments, first marking structures <NUM>-<NUM> are evenly distributed in first marking sub-area <NUM>-<NUM>, and second marking structures <NUM>-<NUM> are evenly distributed in second marking sub-area <NUM>-<NUM>, respectively by a distance the same as or different from d<NUM>. During the etching of staircases, a distance D<NUM> between the central line of central marking structure <NUM>-<NUM> and the edge of the bottom staircase structure Sn has little or no change. That is, central marking structure <NUM>-<NUM> (or the central line of central marking structure <NUM>-<NUM>) has little or no change from its original horizontal location.

<FIG> illustrates the cross-sectional view of first layout <NUM> after the etching of the staircases are completed, according to some embodiments. As shown in <FIG>, the horizontal dimension (e.g., width) of central marking structure <NUM>-<NUM> has little or no reduction and distance D<NUM> has little or no change. The central line of central marking structure <NUM>-<NUM> can be employed to determine the trimming rate of PR layer with higher precision.

<FIG> illustrates a top view of a second layout <NUM> of marking pattern <NUM> during a formation of staircases, according to some embodiments. <FIG> illustrates a cross-sectional view of second layout <NUM> during the formation of staircases, according to some embodiments. <FIG> illustrates a cross-sectional view of second layout <NUM> after the formation of staircases, according to some embodiments. Marking pattern <NUM>, marking sub-areas (<NUM>-<NUM> and <NUM>-<NUM>), and marking structures (e.g., <NUM>-<NUM>,. , <NUM>-<NUM>) may be the same as or different from the corresponding structure illustrated in <FIG>.

Different from marking pattern <NUM> shown in <FIG>, in marking pattern <NUM> illustrated in <FIG>, not forming part of the claimed invention, the pattern density of first marking sub-area <NUM>-<NUM> is higher than the pattern density of second marking sub-area <NUM>-<NUM>. The higher pattern density of first marking sub-area <NUM>-<NUM> may reduce/compensate the loading effect on the etching of central marking structure <NUM>-<NUM>, resulting in a more evenly etched profile on central marking structure <NUM>-<NUM>. The marking structures in first marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> are distributed asymmetrically the central line of central marking structure <NUM>-<NUM> in first marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM>. The number, distribution, shapes, and/or dimensions of respective marking structures in first marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> are arranged to cause the pattern density of first marking sub-area <NUM>-<NUM> to be higher than the pattern density of second marking sub-area <NUM>-<NUM>. The specific number, distribution, shapes, and/or dimensions of the marking structures in each sub-area should be determined according to different designs and/or fabrication of the 3D memory device and should not be limited by the embodiments of the present disclosure. In some embodiments, central marking structure <NUM>-<NUM> has symmetric dimensions and shapes about the central line. In some embodiments, central marking structure <NUM>-<NUM> includes a plurality of interleaved layers of insulating material and sacrificial material. For example, as shown in <FIG>, central marking structure <NUM>-<NUM> includes four interleaved layers of insulating material and sacrificial material (e.g., formed from the patterning of two dielectric pairs in marking area <NUM>).

In an example, as shown in <FIG>, first marking sub-area <NUM>-<NUM> includes two first marking structures <NUM>-<NUM> and <NUM>-<NUM>, and second marking sub-area <NUM>-<NUM> includes one second marking structure <NUM>-<NUM>. In some embodiments, first marking sub-area <NUM>-<NUM> is located between central marking structure <NUM>-<NUM> and first marking structure <NUM>-<NUM>. In some embodiments, along the horizontal direction, a distance d<NUM> between the central line of central marking structure <NUM>-<NUM> and a central line of first marking structure <NUM>-<NUM> is less than a distance d<NUM> between the central line of central marking structure <NUM>-<NUM> and a central line of second marking structure <NUM>-<NUM>. In some embodiments, along the horizontal direction, a distance d<NUM> between the central lines of first marking structures <NUM>-<NUM> and <NUM>-<NUM> is less than distance d<NUM>. In some embodiments, first marking structures <NUM>-<NUM> are evenly distributed in first marking sub-area <NUM>-<NUM> respectively by distance d<NUM>, and second marking structures <NUM>-<NUM> are evenly distributed in second marking sub-area <NUM>-<NUM> by distance d<NUM>. In some embodiments, first marking structures <NUM>-<NUM> and <NUM>-<NUM> have the same shape and dimensions as second marking structure <NUM>-<NUM>. In some embodiments, first marking sub-area <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> have the same dimensions and areas, and all marking structures (e.g., central marking structure <NUM>-<NUM>, first marking structures <NUM>-<NUM> and <NUM>-<NUM>, and second marking structure <NUM>-<NUM>) in marking area <NUM> are identical in shapes and dimensions.

During the etching of staircases, a distance D<NUM> between the central line of central marking structure <NUM>-<NUM> and the edge of the bottom staircase structure Sn has little or no change. That is, central marking structure <NUM>-<NUM> (or the central line of central marking structure <NUM>-<NUM>) has little or no change from its original horizontal location.

<FIG> illustrates the cross-sectional view of second layout <NUM> after the etching of the staircases are completed, according to some embodiments. As shown in <FIG>, the horizontal dimension (e.g., width) of central marking structure <NUM>-<NUM> has little or no reduction and distance D<NUM> has little or no change. The central line of central marking structure <NUM>-<NUM> can be employed to determine the trimming rate of PR layer with higher precision.

<FIG> and <FIG> illustrate a fabrication process to form a plurality of staircases in a stack structure <NUM>, according to some embodiments. <FIG> is a continuation of <FIG>. <FIG> illustrates a flowchart <NUM> of the fabrication process described in <FIG> and <FIG>. For illustrative purposes, a marking pattern <NUM>, similar to or the same as marking pattern <NUM> illustrated in <FIG>, is illustrated in <FIG> and <FIG>. Marking pattern <NUM> illustrated in <FIG> may be formed in a similar fabrication process and is not repeated herein. Stack structure <NUM> may be the same as or similar to stack structure <NUM> illustrated in <FIG>. For simplicity of illustration, a substrate under stack structure <NUM> is omitted in <FIG> and <FIG>. In some embodiments, central marking structure <NUM>-<NUM> (or the central line of central marking structure <NUM>-<NUM>) can be used as a reference to determine the trimming rate of the PR layer during the formation of staircases.

As shown in <FIG>, at the beginning of the fabrication process, a device area and a marking area neighboring the device area are determined (Operation <NUM>), and patterning process is performed to form a marking pattern in the marking area and a staircase pattern in the device area (Operation <NUM>). <FIG> illustrates a corresponding structure.

As shown in the process (I) of <FIG>, at T=t0, a device area <NUM> and a marking area <NUM> over a stack structure <NUM> are determined. Marking area <NUM> may be neighboring device area <NUM> over stack structure <NUM>, which includes a plurality of interleaved insulating material layers <NUM>-<NUM> (similar to or the same as insulating material layers <NUM>-<NUM>) and sacrificial material layers <NUM>-<NUM> (similar to or the same as sacrificial material layers <NUM>-<NUM>) stacking over a substrate (not shown).

A patterning process may be performed to form a staircase pattern <NUM> in device area <NUM> and a marking pattern <NUM> in marking area <NUM>. In some embodiments, a photolithography process is performed to exposed portions of stack structure <NUM>, and a suitable etching process is performed to remove the exposed portions of stack structure <NUM> until a desired thickness of marking pattern <NUM> or staircase pattern <NUM> is reached. For example, a timed etching process and/or a selective etching process may be performed to remove portions of insulating material layers <NUM>-<NUM> and sacrificial material layers <NUM>-<NUM>. The etching process may include a wet etch and/or a dry etch. In some embodiments, marking pattern <NUM> and staircase pattern <NUM> have the same thickness along the vertical direction (e.g., the z-axis), which includes the thickness of at least one dielectric pair. In some embodiments, marking pattern <NUM> and staircase pattern <NUM> each has the thickness equal to the thickness of two dielectric pairs, e.g., having two layers of insulating material and two layers of sacrificial material layer interleaved along the vertical direction.

In some embodiments, marking pattern <NUM> includes a central marking structure <NUM>-<NUM> that divides marking area <NUM> into a first marking sub-area <NUM>-<NUM> farther away from device area <NUM> and a second marking sub-area <NUM>-<NUM> closer to device area <NUM>. The pattern density of first marking sub-area <NUM>-<NUM> may be greater than or equal to the pattern density of second marking sub-area <NUM>-<NUM>. In some embodiments, the pattern density of first marking sub-area <NUM>-<NUM> is the same as the pattern density of second marking sub-area <NUM>-<NUM>. In some embodiments, first marking sub-area <NUM>-<NUM> includes a first marking structure <NUM>-<NUM> and second marking sub-area <NUM>-<NUM> includes a second marking substrate <NUM>-<NUM>. The specific pattern of marking pattern <NUM> may be referred to the description of marking pattern <NUM> in <FIG> and is not repeated herein.

Referring back to <FIG>, a photoresist layer is formed over the staircase pattern, exposing the marking area (Operation <NUM>) and the photoresist layer is repetitively trimmed and used as the etch mask to form a plurality of staircases in the stack structure (Operation <NUM>). <FIG> and <FIG> illustrate corresponding structures.

As shown in the process (II) of <FIG>, at T=t1, a PR layer is formed to cover staircase pattern <NUM>. The PR layer exposes marking area <NUM>. The PR layer is repetitively trimmed and used as an etch mask to form a plurality of staircases in stack structure <NUM>. A suitable etching process (e.g., dry etch) may be performed to remove the exposed portions of stack structure <NUM>, forming staircases in stack structure <NUM>, and transfer the pattern of marking pattern <NUM> along the vertical direction. As shown in <FIG>, processes (II)-(V) illustrate the formation of staircases and the pattern transfer of marking pattern <NUM> from T=t2 to T=t5. A distance D<NUM> between central marking structure <NUM>-<NUM> (or the central line of central marking structure <NUM>-<NUM>) and the edge of bottom staircase Sn may have little or no change during the etching of stack structure (e.g., pattern transfer of marking pattern <NUM>).

Referring back to <FIG>, a distance between the central marking structure and one or more of a staircase and the PR layer can be measured to determine a trimming rate of the photoresist layer (Operation <NUM>). <FIG> illustrates a corresponding structure.

In some embodiments, a distance Ds between central marking structure <NUM>-<NUM> and a staircase and/or a distance Dp between central marking structure <NUM>-<NUM> and the PR layer can be measured, e.g., during or after the trimming and etching process, using a suitable monitoring means, to determine the trimming rate of the PR layer. The staircase can be any desired staircase that has been formed. Distance Ds may reflect the horizontal location of the edge of the staircase, which relates to the amount and rate at which the PR layer is being trimmed. In some embodiments, distance Ds may be compared with a reference value to determine whether the PR is trimmed at a desired trimming rate and/or whether the staircase is formed at a desired horizontal location. In some embodiments, distance Dp is measured in real time to determine whether the PR layer is trimmed at a desired trimming rate. In some embodiments, distance Dp may be repetitively measured to determine the trimming rate of the PR layer. For example, the trimming rate of the PR layer from T=t3 to T=t5 can be calculated as ΔDp/(t5-t3), where ΔDp represents the difference in distance Dp at T=t3 and T=t5. The specific methods to use central marking structure <NUM>-<NUM> for determining the trimming rate of the PR should not be limited by the embodiments of the present disclosure. In some embodiments, PR trimming parameters, e.g., pressure, gas flow, and/or temperature, can be controlled and/or adjusted so the actual PR trimming rate can approach a desired PR trimming rate.

A semiconductor device according to the present invention includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. The semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

The first marking sub-area includes at least one first marking structure and the second marking sub-area includes at least one second marking structure and a number of the at least one first marking structure is greater than or equal to a number of the at least one second marking structure. Each of the central marking structure, the at least one first marking structure, and the at least one second marking structure includes the plurality of interleaved layers of a first material and a second material, the first material being different from the second material.

The first pattern density of the first marking sub-area is equal to the second pattern density of the second marking sub-area, and the at least one first marking structure and the at least one second marking structure are symmetrically distributed on opposite sides of the central marking structure along the horizontal direction.

In some embodiments, the number of the at least one first marking structure is equal to the number of the at least one second marking structure.

In some embodiments, the at least one first marking structure and the at least one second marking structure have same shapes and same dimensions, the central marking structure and the at least one first marking structure are evenly arranged along the horizontal direction by a same distance in the first marking sub-area, and the central marking structure and the at least one second marking structure are evenly arranged along the horizontal direction by the same distance in the second marking sub-area.

In some embodiments, the number of the at least one first marking structure is greater than the number of the at least one second marking structure.

In some embodiments, the at least one first marking structure and the at least one second marking structure have same shapes and same dimensions. In some embodiments, along the horizontal direction, a distance between two of the at least one first marking structure is less than a distance between two of the at least one second marking structure.

In some embodiments, along the horizontal direction, the central marking structure and the at least one first marking structure are evenly distributed by a first distance in the first marking sub-area, and the central marking structure and the at least one second marking structure are evenly distributed by a second distance in the second marking sub-area, the first distance being less than the second distance.

In some embodiments, the stack structure includes a staircase structure, each of the plurality of insulating layers and a corresponding conductor layer forming a staircase of the staircase structure.

In some embodiments, a height of the central marking structure is equal to a thickness of at least one staircase along the vertical direction.

In some embodiments, a marking pattern for controlling a trimming rate of a photoresist trimming process includes a plurality of interleaved layers, the plurality of interleaved layers including at least two layers of different materials stacking along a vertical direction over a substrate.

A method for forming the semiconductor device of the present invention may include the following operations. First, a device area and a marking area neighboring the device area over a dielectric stack are determined, the dielectric stack including a plurality of insulating material layers and a plurality of sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area may be patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern may have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area may be greater than or equal to a second pattern density of the second marking sub-area. A photoresist layer may be formed to cover the staircase pattern and expose the marking pattern, and the photoresist layer may be trimmed to expose a portion of the dielectric stack along a horizontal direction. An etching process may be performed to maintain the marking pattern and remove the exposed portion of the dielectric stack and form a staircase.

In some embodiments, forming the marking pattern includes forming at least one first marking structure in the first marking sub-area and forming at least one second marking structure in the second marking sub-area. A number of the at least one first marking structure may be greater than or equal to a number of the at least one second marking structure.

In some embodiments, forming the marking pattern includes symmetrically forming the at least one first marking structure and the at least one second marking structure evenly distributed on opposite sides of the central marking structure along the horizontal direction. The first pattern density of the first marking sub-area may be equal to the second pattern density of the second marking sub-area.

In some embodiments, forming the marking pattern includes removing portions of at least one insulating material layer and at least one sacrificial material layer in the marking area to form the central marking structure, the at least one first marking structure, and the at least one second marking structure.

In some embodiments, forming a staircase includes removing a portion of one of the plurality of insulating material layers and a portion of one of the plurality of sacrificial material layers to respectively form an insulating layer and a corresponding sacrificial layer.

In some embodiments, the method further includes measuring a distance between the central marking structure and the photoresist layer.

In some embodiments, the method further includes trimming the photoresist layer to expose another portion of the dielectric stack along the horizontal direction, performing another etching process to transfer a pattern of the marking pattern and remove the other exposed portion of the dielectric stack to form another staircase, measuring another distance between the central marking structure and the photoresist layer, and determining an etch rate of the trimming of the photoresist layer based on the respective distance between the distance, the other distance, and a time interval between times at which the photoresist is trimmed to form the first distance and the other distance.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A semiconductor device comprising:
a stack structure (<NUM>, <NUM>, <NUM>) comprising a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate (<NUM>, <NUM>) along a vertical direction; and
a marking pattern (<NUM>, <NUM>, <NUM>) having at least two pairs of interleaved layers of the plurality of insulating layers alternating with sacrificial material layers, over the substrate (<NUM>, <NUM>) and neighboring the stack structure (<NUM>, <NUM>, <NUM>) the material of the sacrificial layer including silicon nitride, the material of the insulating layers being different from the material of the sacrificial layer, wherein the marking pattern (<NUM>, <NUM>, <NUM>) comprises a central marking structure (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) located in a marking area (<NUM>, <NUM>), the central marking structure (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) dividing the marking area (<NUM>, <NUM>) into a first marking sub-area (<NUM>-<NUM>, <NUM>-<NUM>) farther from the stack structure (<NUM>, <NUM>, <NUM>) and a second marking sub-area (<NUM>-<NUM>, <NUM>-<NUM>) closer to the stack structure (<NUM>, <NUM>, <NUM>), a first pattern density of the first marking sub-area (<NUM>-<NUM>, <NUM>-<NUM>) being equal to a second pattern density of the second marking sub-area (<NUM>-<NUM>, <NUM>-<NUM>),
wherein
the first marking sub-area (<NUM>-<NUM>, <NUM>-<NUM>) comprises at least one first marking structure (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) and the second marking sub-area (<NUM>-<NUM>, <NUM>-<NUM>) comprises at least one second marking structure (<NUM>-<NUM>, <NUM>-<NUM>);
a number of the at least one first marking structure (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) is greater than or equal to a number of the at least one second marking structure (<NUM>-<NUM>, <NUM>-<NUM>); and
each of the central marking structure (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>), the at least one first marking structure (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>), and the at least one second marking structure (<NUM>-<NUM>, <NUM>-<NUM>) comprises the at least two pairs of interleaved layers,
wherein the at least one first marking structure (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) and the at least one second marking structure (<NUM>-<NUM>, <NUM>-<NUM>) are symmetrically distributed on opposite sides of the central marking structure (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) along the horizontal direction.