Patent Description:
As an example, servers in a data center are increasingly consuming large amounts of power. The consumption of power is partly the result of power loss from the dissipation of energy even when the CMOS circuits are inactive. This is because even when such circuits, such as random access memories, are inactive, and are not consuming any dynamic power, they still consume power because of the need to maintain the state of CMOS transistors. In addition, because CMOS circuits are powered using DC voltage, there is a certain amount of current leakage even when the CMOS circuits are inactive. Thus, even when such circuits are not processing operations, such as read/write, a certain amount of power is wasted not only as a result of the requirement to maintain the state of the CMOS transistors, but also as a result of the current leakage.

An alternative approach to CMOS technology based memory is a superconducting logic based memory. <CIT> discloses a memory cell including a Josephson junction and a hysteretic magnetic Josephson junction (HMJJ) arranged in parallel, such that the Josephson junction and the HMJJ are cooperatively arranged as a superconducting quantum interference device (SQUID). It is to be understood that the Josephson junction may also be configured as an HMJJ, and may either be in a static state or may participate together with HMJJ in the storage of a binary value. In response to the read current I RD, the Josephson junction and the HMJJ can trigger a voltage pulse based on their respective critical currents which can result in a total critical current of the memory cell that is approximately equal to Ic <NUM>+Ici when storing a first state of the binary value and approximately equal to Ic <NUM>-lci when storing a second state of the binary value.

<CIT> discloses a phase hysteretic magnetic Josephson junction memory cell.

<CIT> discloses a memory cell which may include a first magnetic Josephson junction (MJJ) device and a second magnetic Josephson junction (MJJ) device. During a read operation, the read word-line (RWL) and the read bit-line (RBL) may receive current from the respective. In one state (e.g., the π state), MJJ may provide a flux bias to the readout SQUID formed by the MJJs. During a read operation, the flux bias from MJJ may add to the flux generated by the current flowing through the local read word-line, causing the readout SQUID to transition to a voltage state. In a second state (e.g., the zero state), MJJ may not provide any flux bias to the readout SQUID. The flux generated as a result of the current flowing through the local read word-line may not be enough to drive the readout SQUID into a voltage state. <NPL>, discloses that MJJs can be a basis for nonvolatile random access memory, programmable digital logic arrays, and other digital application requiring programmable change of a function. Disclosed are SIS'FS MJJs as a scalable reprogrammable element capable to energy-efficient Read/Write operations, long retention times, reliability, etc.
It is the object of the present invention to provide an improved method and system for magnetic Josephson junction driven flux-based memory cells. This object is solved by the subject matter of independent claims <NUM>, <NUM> and <NUM>. Preferred aspects are defined in dependent claims <NUM>-<NUM>, <NUM>-<NUM>.

Only embodiments or examples comprising all the technical features of an independent claim <NUM>, <NUM> or <NUM> are falling under the scope of protection of the present invention.

Examples described in this disclosure relate to superconducting logic-based memory systems, including superconductor memory cells. Certain examples relate to magnetic Josephson junction (MJJ)-driven flux-biased memory cells. The memory cells may be implemented using any single flux quantum (SFQ) compatible logic. One example of such logic is the reciprocal quantum logic (RQL). Thus, certain examples further relate to reciprocal quantum logic (RQL) compatible memory cells. Unlike CMOS transistors, the RQL circuits are superconductor circuits that use Josephson junction based devices. An exemplary Josephson junction may include two superconductors coupled via a region that impedes current. The region that impedes current may be a physical narrowing of the superconductor itself, a metal region, or a thin insulating barrier. As an example, the Superconductor-Insulator-Superconductor (SIS) type of Josephson junctions may be implemented as part of the RQL circuits. As an example, superconductors are materials that can carry a direct electrical current (DC) in the absence of an electric field. Superconductors, such as niobium, have a critical temperature (Tc) below which they have zero resistance. Niobium, one such superconductor, has a critical temperature (Tc) of <NUM> Kelvin degrees. At temperatures below Tc, Niobium is superconductive; however, at temperatures above Tc, it behaves as a normal metal with electrical resistance. Thus, in the SIS type of Josephson junctions, superconductors may be Niobium superconductors and insulators may be Al<NUM>O<NUM> barriers. In SIS type of junctions, the superconducting electrons are described by a quantum mechanical wave-function. A changing phase difference in time of the phase of the superconducting electron wave-function between the two superconductors corresponds to a potential difference between the two superconductors. In RQL circuits, in one example, the SIS type of junction may be part of a superconducting loop. When the potential difference between the two superconductors is integrated with respect to time over one cycle of phase change, the magnetic flux through the loop changes by an integer multiple of a single quantum of magnetic flux. The voltage pulse associated with the single quantum of magnetic flux is referred to as a single-flux-quantum (SFQ) pulse. As an example, overdamped Josephson junctions can create individual single-flux-quantum (SFQ) pulses. In RQL circuits, each Josephson junction may be part of one or more superconducting loops. The phase difference across the junction may be modulated by the magnetic flux applied to the loop.

Various RQL circuits including transmission lines can be formed by coupling multiple Josephson junctions by inductors or other components, as needed. SFQ pulses can travel via these transmission lines under the control of at least one clock. The SFQ pulses can be positive or negative. As an example, when a sinusoidal bias current is supplied to a junction, then both positive and negative pulses can travel rightward, during opposite clock phases, on a transmission line. The RQL circuits may advantageously have zero static power dissipation because of the absence of bias resistors. In addition, the RQL circuits may be powered using alternating current (AC) power thereby eliminating the ground return current. The AC power supply may also act as a stable clock reference signal for the RQL circuits. In one example, the digital data may be encoded using a pair of positive and negative (reciprocal) SFQ pulses. As an example, a logical one bit may be encoded as a reciprocal pair of SFQ pulses generated in the positive and negative phases of a sinusoidal clock. A logical zero bit may be encoded by the absence of positive/negative pulse pairs during a clock cycle. The positive SFQ pulse may arrive during the positive part of the clock, whereas the negative pulse may arrive during the negative part of the clock.

The building blocks of exemplary RQL circuits may include various types of logic gates. Exemplary logic gates include an AND gate, an OR gate, a logical A-and-not-B (AanB) gate, and a logical AND & OR (AndOr) gate. The AanB gate may have two inputs and one output (Q). An input pulse A may propagate to output Q unless an input pulse B comes first. The AndOr gate may have two inputs and two outputs (Q1 and Q2). The first input pulse, input pulse A or input pulse B, goes to output Q1 and the second input pulse goes to output Q2. The logical behavior of these gates may be based on the reciprocal data encoding mentioned earlier. As an example, a positive pulse changes the internal flux state of the inductive loop, but the trailing negative pulse erases the internal state every clock cycle, which in turn produces combinational logic behavior.

In general, microwave signals (e.g., SFQ pulses) may be used to control the state of a memory cell. During read/write operations, word-lines and bit-lines may be selectively activated by SFQ pulses arriving via an address bus. These pulses may, in turn, control word-line and bit-line drivers that may provide word-line and bit-line currents to the relevant memory cells. An example memory cell may include two Magnetic Josephson Junction (MJJ) devices and a niobium superconducting quantum interference device (SQUID). A control line may be configured to inductively flip the two MJJ devices in opposite directions-creating one MJJ device with a low current and the other MJJ device having a relatively higher current. This may generate flux bias in one direction. On the other hand, when the control line flips the two MJJ devices in an opposite manner, then this may generate flux bias in the opposite direction. The niobium SQUID may be configured to serve as a sensor of these changes in the flux biases such that one state of the memory cell may be logic "<NUM>" state and the other state of the memory cell may be logic "<NUM>" state depending upon whether the niobium SQUID generates a voltage pulse or not. The voltage pulse may be sensed by a sense amplifier. The use of the MJJ devices to flux bias the niobium SQUID based on the current direction may advantageously lower the amount of current required to change or sense a state of the memory cell. This is because unlike other memory cells that may use current flow to provide flux biasing, certain examples of the present disclosure provide a solution in which current steering may be used to create the flux biasing. As an example, the MJJ devices may be used to steer current in a clock-wise direction or in an anti-clock-wise direction and thereby provide flux biasing.

In one example, the MJJ device may include at least one fixed magnetic layer and at least one free magnetic layer. In one state, the magnetic polarity associated with the free magnetic layer may be substantially parallel to the magnetic polarity associated with the fixed magnetic layer. This state of the MJJ device may be referred to as the parallel state. In another state, the magnetic polarity associated with the free magnetic layer may be substantially opposite to the magnetic polarity associated with the fixed magnetic layer. This state of the MJJ device may be referred to as the anti-parallel state.

Memory cells may be arranged in rows and columns, such that each row can be activated by a common flux bias (e.g., a read word-line signal) and each bit-line may form a transmission line that may propagate the output of the memory cells in a voltage state to a sense amplifier at one end of the column. Memory cells in a column may be serially biased by a common current source; for example, a flux pump.

<FIG> shows a diagram of a memory cell <NUM> in accordance with one example. In one example, memory cell <NUM> includes a first magnetic Josephson junction (MJJ) device <NUM> and a second magnetic Josephson junction(MJJ) device <NUM> arranged in parallel to each other. The two MJJs form a superconducting quantum interference device (SQUID). Memory cell <NUM> may further include two inductors <NUM> and <NUM>. Memory cell <NUM> further includes a Josephson junction (JJ) <NUM> and a Josephson junction (JJ) <NUM>, arranged in parallel to each other, which form a niobium-based (or another superconducting metal-based) superconducting quantum interference device (SQUID).

With continued reference to <FIG>, memory cell <NUM> may be coupled to word-lines and bit-lines for performing various memory operations, including, for example, read and write operations. As an example, a read word-line (RWL) for performing a read operation may be coupled to memory cell <NUM> via inductor <NUM>. A write word-line (WWL) for performing a write operation may be coupled to memory cell <NUM>. In addition, a read bit-line (RBL) for performing a read operation may be coupled to memory cell <NUM> via inductor <NUM>. A write bit-line (WBL) for performing a write operation may also be coupled to memory cell <NUM>. The write bit-line (WBL) may also be used to form a coupling with MJJ device <NUM>, which may alter the magnetic polarity of the free magnetic layer of MJJ device <NUM>. Additionally, as shown in <FIG>, the write word-line (WWL) may also be used to form a coupling with MJJ device <NUM>, which may alter the magnetic polarity of the free magnetic layer of MJJ device <NUM>. The WWL may also be used to form a coupling, which may alter the magnetic polarity of the free magnetic layer of MJJ device <NUM>. During a write operation, current may be coupled via WBL to MJJ device <NUM> and via WWL to MJJ device <NUM>. Although <FIG> shows WBL coupled to MJJ device <NUM> only, it may be coupled to MJJ device 115as well.

The write bit-line may be magnetically coupled to MJJ device <NUM>. In one example, coupling with MJJ <NUM> may be such that a magnetic field generated by at least one of the magnetic barrier layers of MJJ device <NUM> can be changed by the application of a local read word-line current and by the application of a local bit-line current. In one example, MJJ device <NUM> may be in a first state (e.g., corresponding to a first configuration of magnetization of the at least one free magnetic layer) and a second state (e.g., corresponding to a second configuration of magnetization of the at least one free magnetic layer), where the first configuration of the magnetization may be substantially different from the second configuration of the magnetization. In one example, MJJ device <NUM> may be in one state when the magnetic fields generated by the fixed magnetic layer and the free magnetic layer oppose each other.

Still referring to <FIG>, Icc is a DC bias current, which may be steered based on a state of the SQUID formed by MJJs <NUM> and <NUM>. When both RBL and WWL are selected, the free magnetic layer of MJJ <NUM> may change from the anti-parallel magnetization state (high-Ic) to the parallel magnetization state (low-Ic). The DC bias current Icc may be steered to the high-Ic MJJ, which in turn may create a clock-wise current or a counter-clock-wise current depending upon the MJJ SQUID geometry. In this example, the counter-clock-wise current may create a flux bias in the sensing niobium SQUID (formed by JJ <NUM> and JJ <NUM> of <FIG>). This flux bias may be read by sending a flux bias along the RWL and pulsing the RBL. If the flux bias generated by the MJJ and the flux bias along the RWL are in the same direction, then the niobium SQUID will pulse (representing logic state "<NUM>"). If, on the other hand, the flux bias generated by the MJJ and flux bias along the RWL are in the opposite direction, then the niobium SQUID will not pulse (representing logic state "<NUM>").

<FIG> shows a magnetic Josephson junction (MJJ) device <NUM> in accordance with one example. In one example, MJJ device <NUM> and MJJ device <NUM> of <FIG> may be configured as MJJ device <NUM>. In this example, MJJ device <NUM> may include a conductive layer <NUM> and another conductive layer <NUM>. In this example, conductive layer <NUM> and conductive layer <NUM> may be formed using niobium or another appropriate superconducting metal. In this example, the thickness of each of these conductive layers may be <NUM> Angstroms to <NUM> Angstroms. MJJ device <NUM> may further include non-magnetic layer <NUM>, which may be sandwiched between a free magnetic layer <NUM> and a fixed magnetic layer <NUM>. Thus, in this example, free magnetic layer <NUM> may be formed above non-magnetic layer <NUM> and fixed magnetic layer <NUM> may be formed below non-magnetic layer <NUM>. There could be intervening layers between any of these layers. The terms above and below are merely used to indicate that free magnetic layer <NUM> is on one side of non-magnetic layer <NUM> and fixed magnetic layer <NUM> is formed on the other side of non-magnetic layer <NUM>. These terms do not imply a particular order of creating these layers. In other words, in the context of this disclosure, above may mean below and below may mean above.

In one example, free magnetic layer <NUM> may have very soft magnetic properties to allow for switching of the magnetization direction in response to small magnetic fields. As an example, at liquid helium temperature, free magnetic layer <NUM> may have saturation magnetization below <NUM> emu/cc, a coercivity value of less than <NUM> Oersted, and an anisotropy field value of less than <NUM> Oersted. Free magnetic layer <NUM> may include a first magnetic alloy doped with at least one of Vanadium, Zirconium, Molybdenum, or Hafnium. As an example, free magnetic layer <NUM> may include doped alloy V<NUM>(Ni<NUM>Fe<NUM>)<NUM>. Thus, free magnetic layer <NUM> may include a Nickel-Iron (Ni-Fe) alloy doped with Vanadium (V). Vanadium may have a concentration of <NUM> atomic percent and the Ni-Fe alloy may have a concentration of <NUM> atomic percent. Within the Ni-Fe alloy, Ni may have a concentration of <NUM> atomic percent and Fe may have a concentration of <NUM> atomic percent. In one example, Vanadium may have a concentration in a range between <NUM>-<NUM> atomic percent and the Ni-Fe alloy may have a concentration in a range between <NUM>-<NUM> atomic percent. Within the Ni-Fe alloy, the concentration of Ni may be varied between <NUM> atomic percent to <NUM> atomic percent and the concentration of Fe may be varied between <NUM> atomic percent to <NUM> atomic percent. In one example, free magnetic layer <NUM> may be <NUM> Angstroms in thickness. In this example, fixed magnetic layer <NUM> may be formed using an un-doped magnetic alloy. In another example, fixed magnetic layer <NUM> may have a lower amount of doping than free magnetic layer <NUM>. In one example, fixed magnetic layer <NUM> may have a larger hysteresis than the hysteresis for free magnetic layer <NUM>. Fixed magnetic layer <NUM> may also have a larger coercivity value (He) compared to free magnetic layer <NUM>. Fixed magnetic layer <NUM> may also have a large squareness (remnant magnetization (MR)/saturation magnetization (Ms) ratio). The thickness of fixed magnetic layer <NUM> may be selected to enable the transition of MJJ device between a high current and a low current state. As an example, fixed magnetic layer <NUM> may include doped alloy V<NUM>(Ni<NUM>Fe<NUM>)<NUM>. Thus, fixed magnetic layer <NUM> may include a Ni-Fe alloy doped with Vanadium. Vanadium may have a concentration of <NUM> atomic percent and the Ni-Fe alloy may have a concentration of <NUM> atomic percent. Within the Ni-Fe alloy, Ni may have a concentration of <NUM> atomic percent and Fe may have a concentration of <NUM> atomic percent. In one example, fixed magnetic layer <NUM> may be <NUM> Angstroms in thickness. In general, magnetic layers may have a thickness of <NUM> Angstroms to <NUM> Angstroms. The magnetic alloy may be a Ni-Co alloy, an Fe-Co alloy, or a Co-Ni-Fe alloy. In another example, magnetic layers may include a Ni-Fe alloy doped with Zirconium (Zr), such as Zrz(Ni<NUM>Fe<NUM>)<NUM>-z, where a concentration of Zirconium may be varied in a range between <NUM> atomic percent to <NUM> atomic percent. In other examples, magnetic layers may include a Ni-Fe alloy doped with Molybdenum or Hafnium. Non-magnetic layer <NUM> may include at least one of Vanadium (V), Molybdenum (Mo), Copper (Cu), Aluminum (Al), Tantalum (Ta), or Chromium (Cr). Any of the layers described with respect to <FIG> may be formed using physical vapor deposition (PVD) techniques, such as sputtering. Although <FIG> shows a certain number of layers of MJJ device <NUM> arranged in a certain manner, there could be more or fewer layers arranged differently. As an example, each of MJJ device <NUM> and MJJ device <NUM> may comprise a first superconducting metal layer, a dielectric layer, an anti-ferromagnetic layer, a conductive metal layer, a ferromagnetic layer, and a second superconducting metal layer.

<FIG> shows a schematic of the operation of a memory cell (e.g., memory cell of <NUM> <FIG>) in accordance with one example. As shown at stage <NUM>, using a control line that is inductively coupled to the two MJJ devices, the critical current (Ic) in either of the two MJJ devices can be set to a high Ic value (Hi-Ic) or a low Ic value (Lo-Ic). At stage <NUM>, the two MJJ devices are shown in a first state, where the right MJJ device is set to a high Ic value (Hi-Ic) and the left MJJ device is set to a low Ic value (Lo-Ic). At this stage, the current flowing through the SQUID formed by two MJJ devices will distribute in a manner that it will create a flux into a direction perpendicular to the current flow going inwards towards the center. At stage <NUM>, using the control line, the two MJJ devices are flipped, such that the right MJJ device is set to a low Ic value (Lo-Ic) and the left MJJ device is set to a high Ic value (Hi-Ic). Alternatively, at stage <NUM>, one of the two MJJ devices can be set to a high Ic value (Hi-Ic) or a low Ic value (Lo-Ic) with the other device being unchanged. As a result, the current flowing through the SQUID will create a flux in a direction opposite to the direction in the previous state of the SQUID (e.g., flux will be created in a direction perpendicular to the current flow going outwards out of the center). As shown, at stage <NUM>, the change in the flux is detected by a biased niobium SQUID (shown in the middle). The detection by the niobium SQUID corresponds to whether the flux bias is in one direction or the other. As an example, in one of the directions, the niobium SQUID, when biased correctly, may generate a voltage pulse that can be sensed using a sense amplifier.

With a reference back to <FIG>, during a write operation, the write word-line (WWL) and the write bit-line (WBL) may receive current from respective drivers. A series of timed write pulses provided via the WWL and the WBL may be used to create magnetic fields at the selected memory cell(s) to set the free magnetization layer. That setting in turn may reflect one of the logic states (high or low) of the memory cell.

Referring again to <FIG>, during a read operation, the read word-line (RWL) and the read bit-line (RBL) may receive current from the respective drivers (e.g., word-line drivers and bit-line drivers). In one example, read word-line (RWL) may be coupled to inductor <NUM>. In one example, read bit-line (RBL) may be coupled directly to the niobium SQUID and provide a local bit-line current. In one state (e.g., a high Ic value (Hi-Ic) or a low Ic value (Lo-Ic)), MJJ <NUM> may provide a further flux bias to the niobium SQUID formed by the MJJs. During a read operation, the flux bias from MJJ <NUM> may add to the flux generated by the current flowing through the local read word-line, causing the niobium SQUID to transition to a voltage state. In a second state (e.g., the zero state), MJJ <NUM> may provide much less flux bias to the niobium SQUID. The flux generated as a result of the current flowing through the local read word-line may not be enough to drive the niobium SQUID into a voltage state. The change in an output voltage, current, or any other parameter of memory cell <NUM> may be sensed using a sense amplifier. In one example, the presence or absence of a current pulse, once amplified by the sense amplifier, may determine the state of memory cell <NUM> as logic '<NUM>' or logic '<NUM>'. As an example, the logic '<NUM>' state may correspond to a "voltage state," in which a sense amplifier coupled to the memory cell may sense the voltage as being representative of the logic '<NUM>' state. The logic '<NUM>' state may correspond to a "substantially zero-voltage state," such that the sense amplifier may sense this as being representative of the logic '<NUM>' state.

<FIG> shows a diagram of a memory system <NUM> in accordance with one example. Memory system <NUM> may include an array <NUM> of memory cells arranged in rows and columns. In one example, array <NUM> is an array of memory cells, having the same structure and operation as memory cell <NUM> of <FIG>. Memory system <NUM> may further include a row decoder <NUM> that may be configured to decode row control/address signals. Row decoder <NUM> may further be coupled to word-line drivers <NUM>. Word-line drivers <NUM> may include circuitry to provide word-line read/write current to a subset or all of the memory cells associated with a selected word-line for any read or write operations. Word-line drivers <NUM> may provide such current via word-lines <NUM>. Word-lines <NUM> may include both read word-lines and write word-lines. In other words, different word-lines may be used to provide current to the selected memory cells for read or write operations. Memory system <NUM> may further include column decoder <NUM> that may be configured to decode column control/address signals. Column decoder <NUM> may further be coupled to bit-line drivers <NUM>. Bit-line drivers <NUM> may include circuitry to provide bit-line read current to a subset or all of the memory cells associated with a selected bit-line for any read or write operations. Bit-line drivers <NUM> may provide such current via bit-lines <NUM>. Bit-lines <NUM> may include both read bit-lines and write bit-lines. In other words, different bit-lines may be used to provide current to the selected memory cells for read or write operations. By using row and column addresses, any of the memory cells could be accessed using an address. Each of the bit-lines (e.g., bit-lines <NUM>) may further be coupled to sense amplifier <NUM> for sensing bit-lines to determine the logical state of each of the array <NUM> of memory cells. The coupling between the array <NUM> of memory cells and sense amplifier <NUM> may include radio frequency (RF) transmission lines. The memory cells in each column may be serially current-biased by a common current source (e.g., a flux pump). As described earlier, bit-lines <NUM> may be used to couple this current to each of the memory cells in a column. Although <FIG> shows a certain number of components of memory system <NUM> arranged in a certain manner, there could be more or fewer number of components arranged differently.

<FIG> shows a computing system <NUM> including a processor <NUM> coupled to a memory <NUM> (e.g., memory system <NUM> of <FIG>) via a bus <NUM> in accordance with one example. Processor <NUM> may perform read or write operations on memory <NUM> in a manner as explained earlier. Additionally, processor <NUM> and memory <NUM> may be used along with other superconducting logic-based devices. In general, any superconducting device operating in cryogenic environments and requiring storage of instructions or data may include memory <NUM>. Furthermore, processor <NUM> need not be in a cryogenic environment; instead, it may operate at non-cryogenic temperatures. In this example, memory <NUM> may be in a separate cryogenic environment and may be coupled via connectors to processor <NUM> in a way that the cryogenic environment can be maintained. Memory <NUM> may be used as part of storage in a data center for delivering cloud-based services, such as software as a service, platform as a service, or other services.

It is to be understood that the methods, modules, and components depicted herein are merely exemplary. Alternatively, or in addition, the functionally described herein can be performed, at least in part, by one or more hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), System-on-a-Chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or inter-medial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "coupled," to each other to achieve the desired functionality.

The functionality associated with the examples described in this disclosure can also include instructions stored in a non-transitory media. The term "non-transitory media" as used herein refers to any media storing data and/or instructions that cause a machine, such as processor <NUM>, to operate in a specific manner. Exemplary non-transitory media include non-volatile media and/or volatile media. Non-volatile media include, for example, a hard disk, a solid state drive, a magnetic disk or tape, an optical disk or tape, a flash memory, an EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory, such as, DRAM, SRAM, a cache, or other such media. Non-transitory media is distinct from, but can be used in conjunction with transmission media. Transmission media is used for transferring data and/or instruction to or from a machine. Exemplary transmission media, include coaxial cables, fiber-optic cables, copper wires, and wireless media, such as radio waves.

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Although the disclosure provides specific examples, various modifications and changes can be made without departing from the scope of the disclosure as set forth in the claims below.

Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claim 1:
A memory cell (<NUM>) comprising:
a magnetic Josephson junction, MJJ superconducting quantum interference device, SQUID, comprising a first MJJ device (<NUM>) and a second MJJ device (<NUM>), arranged in parallel to each other, wherein the MJJ SQUID is configured to generate a first flux-bias (<NUM>) or a second flux-bias (<NUM>), wherein the first flux-bias corresponds to a first direction of current flow in the MJJ SQUID and the second flux-bias corresponds to a second direction of current flow in the MJJ SQUID, wherein the first direction is opposite to the second direction, characterized by
a superconducting metal-based superconducting quantum interference device, SQUID, including a first Josephson junction, JJ(<NUM>), and a second JJ (<NUM>), arranged in parallel to each other, wherein each of the first JJ and the second JJ has a critical current responsive to any flux-bias generated by the MJJ SQUID, and wherein in response to a read operation, the superconducting metal-based SQUID is configured to provide an output based at least on the first flux-bias or the second flux-bias.