Patent Description:
Passive optical networks have become a widespread tool in connecting multiple users to an internet server. In a passive optical network, the signal sent from a customer's terminal, known as an optical network unit (ONU) to a central office, known as the optical line terminal (OLT), is a burst signal. Unlike the continuous signals widely used with Ethernet and other technologies, burst signals are multiple data segments (bursts) with a gap in between bursts, allowing burst receiver to acquire the threshold every single burst. Moreover, the distances from customers to the central office vary, which affects the signal strength. For the central office to be able to handle such customer data, these optical burst signals with differing strengths and timings must be converted into electrical signals of fixed strength and timing.

Upstream transmissions in a passive optical network follow a time division multiple access (TDMA) format. Each active optical network unit sends bursts toward the optical line terminal within precisely assigned time slots. The optical fibers from multiple optical network unites are merged into a single optical fiber using a power splitter which is connected to the central station. The length of optical fibers between the optical network units and the power splitter varies. Consequently, the intensities of the optical signals are not uniform. The burst mode receiver must process optical bursts from all active optical network units with different optical power levels, and unpredictable burst-to-burst phase. In particular, the burst mode receiver must be able to maintain high dynamic range (weak signal followed by strong signal and vice versa) of at least 20dB. By a rigorous time-ranging process, time division multiplexed passive optical networks avoid the collision of bursts and provide high bandwidth efficiency.

A typical burst-mode receiver for an optical line terminal consists of an avalanche photodiode (APD), which converts the optical signal into an electrical current signal; a transimpedance amplifier (TIA), which amplifies and converts the current signal into a voltage signal; a limiting amplifier (LA), which converts weak and strong voltages into fixed-amplitude voltage signals and performs offset compensation; and a clock and data recovery (CDR), which extracts the timing clock from this signal and reshapes the signal waveform using the extracted clock signal.

<NPL> discloses an optical receiver with wide dynamic range. As the input stage of the proposed optical receiver, a transimpedance amplifier of a three-cascaded inverting topology with a feedback resistor incorporates dual automatic gain controls to broaden the input dynamic range.

An ideal passive optical network deployment requires not only a high receiver sensitivity, but also a wide dynamic range. The dynamic range allows to handle differential optical distribution network losses that individual optical network unit bursts experience along the different optical paths. In burst mode receivers that are currently known, the transimpedance amplifier (TIA) input signal supports a dynamic range of approximately <NUM> to 25dB. This dynamic range corresponds to the <NUM>-EPON IEEE <NUM>. 3av standard, which specifies a dynamic range of <NUM> dB. In some passive optical networks, however, the received data can vary by a much larger range, for example up to 60dB. This corresponds to approximately a variance of <NUM>,<NUM>:<NUM> between the lowest and highest signal levels.

One reason for the limitation in dynamic range in known burst mode receivers is their method for controlling the gain. Standard burst mode receivers operate based on a "continuous" automatic gain control (AGC) approach. In a receiver with continuous Automatic Gain Control, a gain control signal tracks the average of the input signal power so that it can tolerate fluctuations in the power. However, a continuous automatic gain control system cannot support a dynamic range larger than <NUM>-<NUM> dB, and certainly not up to <NUM> dB. This is because, in continuous systems, a wider dynamic range comes at the expense of a longer settling time and shorter bandwidth.

In addition, in existing burst-mode receivers, the acquisition time for the receiver system, which is the time takes for the receiver circuit to settle to good output signal levels, is on the order of <NUM> nanoseconds. If faster acquisition time is needed, a reset signal needs to be generated by a Media Access Control (MAC) layer of the receiver. The MAC layer is located outside the chip containing the transimpedance amplifier.

For at least the foregoing reasons, a fast-acquisition, high dynamic range, high bandwidth, and low power burst-mode receiver is required, to support modern passive optical networks.

Advantageous features are defined in the dependent claims.

According to a first aspect, a burst mode receiver for a passive optical network includes a high gain circuitry portion having a plurality of cascaded amplifiers. Each of the cascaded amplifiers is configured to increase a gain of an input signal. The high gain circuitry portion also includes a plurality of high gain switches. The burst mode receiver further includes an adaptive gain circuitry portion having at least one inverter. The adaptive gain circuitry portion is configured to adaptively control the gain of the input signal. The adaptive gain circuitry portion further includes a plurality of adaptive gain switches. The high gain circuitry portion and the adaptive gain circuitry portion comprise a shared input portion comprising at least one metal oxide semiconductor transistor. When a peak detector detects input current in a first range, the burst mode receiver is configured to activate the high gain circuitry portion, in which the high gain switches are closed and the adaptive gain switches are opened, and when the peak detector detects input current in a second range, the burst mode receiver is configured to activate the adaptive gain circuitry portion, in which the high gain switches are opened and the adaptive gain switches are closed. The first range is between 3µA and 35µA and the second range is between 25µA and 3mA. Advantageously these ranges are well suited for maximizing the gain implemented by each of the architecture.

Advantageously, by using two different architectures configured to implement different gains, the receiver is able to receive bursts at a wide dynamic range. The dynamic range is not constrained to the dynamic range that would typically be available with a "continuous" automatic gain control (AGC) approach, but can also include dynamic range based on input current that is amplified with the high gain circuitry portion. Furthermore, the peak detector is integrated within the transimpedance amplifier, rather than in an external control, and the adaptive gain and high gain circuitry portions share an input portion. These integrated features allow for switching between the two architectures quickly and efficiently. The receiver is therefore able to receive bursts and operate the signals with a very short acquisition time.

In another implementation according to the first aspect, a dynamic range of the burst mode receiver is <NUM> dB. Advantageously, the receiver is thus capable of receiving bursts from a large number of optical network units, as well as optical network units at a large distance from the receiver.

In another implementation according to the first aspect, a sensitivity of the burst mode receiver is at least -33dBm, and a bit error ratio of the burst mode receiver is no greater than <NUM>-<NUM>. Advantageously, the burst mode receiver combines low sensitivity with high accuracy.

In another implementation according to the first aspect, the peak detector monitors the input current of each burst and the burst mode receiver switches between the high gain circuitry portion and the adaptive gain circuitry portion within an acquisition time of fewer than <NUM> nanoseconds. Advantageously, this quick acquisition time allows for faster receipt of signals from different optical network units, thereby promoting efficiency of the entire passive optical network.

In another implementation according to the first aspect, the high gain circuitry portion includes three or more amplifiers. A first of the amplifiers is the transistor of the shared input portion. Each of the amplifiers is associated with a respective gain stage. Advantageously, the three amplifiers may thus be implemented as cascaded amplifiers, to thereby increase the gain of the high gain circuitry portion.

In another implementation according to the first aspect, the three respective gain stages are used to optimize noise, bandwidth, and gain performance of the input signal. Advantageously, for each amplifier, the adjustment to the gain may be selected based on desired values for noise and bandwidth.

In another implementation according to the first aspect, the high gain circuitry portion includes a feedback resistor and a feedback capacitor. Advantageously, the feedback resistor and capacitor are used to achieve a high gain using a large effective transconductance.

In another implementation according to the first aspect, the feedback resistor has a resistance of approximately <NUM> Ohm and the feedback capacitor has a capacitance of approximately <NUM> fF. Advantageously, a resistor and feedback capacitor with these values are effective for achieving stability high gain using a large effective transconductance.

In another implementation according to the first aspect, an input stage of the transimpedance amplifier comprises two inductors configured in series. Advantageously, the inductors help overcome the effects of parasitic capacitance on the high gain circuitry portion, such as parasitic capacitance resulting from proximity of transistors and an avalanche photodiode.

In another implementation according to the first aspect, the adaptive gain circuitry portion comprises a variable resistor and a variable capacitor. Advantageously, the resistance and capacitance of the variable resistor and variable capacitor may be adjusted with an automatic gain control loopback, in order to control the gain.

In another implementation according to the first aspect, the variable resistor is configured to have a resistance between approximately <NUM> and <NUM> Ohm and the variable capacitor is configured to have a capacitance between approximately <NUM> and <NUM> fF. Advantageously, these ranges of values enable the adaptive gain circuitry portion to implement a gain within desired ranges.

In another implementation according to the first aspect, the inverter is complementary metal oxide semiconductor (CMOS) push-pull inverter. Advantageously, a CMOS push-pull inverter operates with better noise behavior than alternative structures, such as a common-source amplifier, and thus is well suited for use in the adaptive gain circuitry portion.

In another implementation according to the first aspect, the burst mode receiver is configured to deliver data from a plurality of optical network units to an optical line terminal of a passive optical network. Advantageously, the burst mode receiver thus is able to deliver data as part of a fiber-to-the-home portion of a passive optical network.

In another implementation according to the first aspect, the passive optical network comprises at least <NUM> optical network units. Advantageously, the burst mode receiver is configured to deliver and differentiate signals from a number of optical network units that are typically connected to a single optical line terminal.

In another implementation according to the first aspect, the high gain switches and adaptive gain switches are transistors. Advantageously, the transistors may function as switches with a high efficiency and low expenditure of energy.

According to a second aspect, a method includes detecting an input signal entering a burst mode receiver. The burst mode receiver includes: a high gain circuitry portion having a plurality of cascaded amplifiers, each of the cascaded amplifiers configured to increase a gain of the input signal, and a plurality of high gain switches. The burst mode receiver further includes an adaptive gain circuity portion comprising at least one inverter, the adaptive gain circuitry portion configured to adaptively control the gain of the input signal, and a plurality of adaptive gain switches. The high gain circuitry portion and adaptive gain circuitry portion comprise a shared input portion comprising at least one metal oxide semiconductor transistor. The method includes, when a peak detector detects an input current in a first range, activating the high gain circuitry portion, in which the high gain switches are closed and the adaptive gain switches are opened. The method further includes, when the peak detector detects an input current in a second range, activating the adaptive gain circuitry portion, in which the high gain switches are opened and the adaptive gain switches are closed.

Advantageously, the method uses a burst mode receiver that combines two architectures for a trans-impedance amplifier into one circuit. By using two different architectures configured to implement different gains, the receiver is able to receive bursts at a wide dynamic range. The dynamic range is not constrained to the dynamic range that would typically be available with a "continuous" automatic gain control approach, but can also include dynamic range based on input current that is amplified with the high-gain circuitry portion. Furthermore, the peak detector is integrated within the transimpedance amplifier, rather than in an external control, and the adaptive gain and high gain circuitry portions share an input portion. These integrated features allow for switching between the two architectures quickly and efficiently. The receiver is therefore able to receive bursts and operate the signals with a very short acquisition time.

In another implementation according to the second aspect, the detecting step includes detecting current with a dynamic range of <NUM> dB. Advantageously, the method thus is suitable for receiving bursts from a large number of optical network units, as well as optical network units at a large distance from the receiver.

In another implementation according to the second aspect, the method further includes performing the detecting step with a peak detector that monitors the input current of each burst and switches between the first and second states within an acquisition time of fewer than <NUM> nanoseconds. Advantageously, this quick acquisition time allows for faster receipt of signals from different optical network units, thereby promoting efficiency of the entire passive optical network.

In another implementation according to the second aspect, the method further includes, when the detecting step detects an input signal between <NUM>µA and 35µA, activating the high gain circuitry; and when the detecting step detects an input signal between 25µA and <NUM> mA, activating the adaptive gain circuitry. Advantageously, these ranges are well-suited for maximizing the gain implemented by each of the architectures.

In another implementation according to the second aspect, the adaptive gain circuitry comprises a variable resistor and a variable capacitor, and the method further comprises adjusting the resistance of the variable resistor and the capacitance of the variable capacitor to thereby adaptively control the gain. Advantageously, the gain may thereby be controlled effectively.

In another implementation according to the second aspect, the method further includes delivering data from a plurality of optical network units to an optical line terminal through the burst mode receiver. Advantageously, the method is usable to deliver data as part of a fiber-to-the-home portion of a passive optical network.

In another implementation according to the second aspect, the delivering step comprises delivering data from at least <NUM> optical network units. Advantageously, the method is usable for delivering signals from a number of optical network units that are typically connected to a single optical line terminal.

The invention is defined by the appended independent claim and the preferred embodiments are defined by the appended dependent claims.

Referring now to <FIG>, a schematic illustration of a transimpedance amplifier (TIA) chip <NUM> is disclosed. Chip <NUM> is part of a burst mode receiver. The TIA chip <NUM> includes TIA block <NUM>, start & stop detector <NUM>, and automatic gain control loopback <NUM>. The TIA block <NUM> further includes high gain circuitry portion <NUM> and adaptive gain circuitry portion <NUM>.

When a signal is delivered to the TIA chip <NUM>, the Start Detector portion of the start & stop detector <NUM>, also referred to herein as a peak detector, senses the input current received by the TIA block <NUM>. The peak detector is operatively connected to a plurality of switches on the TIA block <NUM>. Depending on the amplitude of the received signal, the peak detector operates the switches to route the signal through high gain circuitry portion <NUM> or adaptive gain circuitry portion <NUM>. The amplified signal is then output from the TIA block <NUM>.

Automatic gain control loopback <NUM> is used to provide an even output signal when the signal is routed through adaptive gain circuitry portion <NUM>, as will be discussed further below.

After amplification and delivery of the signal, the stop detector portion of the start & stop detector <NUM> resets the peak detector, to prepare the start & stop detector <NUM> for receipt of a new signal.

The use of a start & stop detector <NUM> on TIA chip <NUM> differs from signal detectors used in standard burst mode transimpedance amplifiers. In a standard burst mode TIA, a reset signal is provided by a Media Access Control (MAC) chip, which is external to the TIA chip. In such devices, the reset signal sets Start-of-Burst and Stop-of-Burst timing and controls the automatic gain control mechanism. By contrast, in the depicted embodiments, the reset signal is generated from within TIA chip <NUM>. This different design requires a more complex design of the TIA chip <NUM>, but also enables a faster acquisition time for each signal. As used in this disclosure, acquisition time refers to the time that is necessary for the TIA to acquire a new coming burst. In devices with a reset signal based in a MAC chip, the average reset time is around hundreds of nanoseconds (ns). By contrast, in the burst mode amplifier of embodiments disclosed herein, the acquisition time is only around <NUM> ns.

The TIA block <NUM> also includes at its input portion two or more inductors <NUM> connected in series, the function of which will be explained below.

<FIG> are block diagrams of the high gain circuitry portion <NUM> (<FIG>), the adaptive gain circuitry portion <NUM> (<FIG>), and a combined circuitry portion incorporating both the high gain circuitry portion <NUM> and the adaptive gain circuitry portion <NUM> (<FIG> and <FIG>).

Referring to <FIG>, high gain circuitry portion <NUM> includes three transistors M1, M2, M3 arranged in series. In the depicted embodiment, transistors M1, M2, M3 are represented as metal oxide semiconductor field effect transistors (MOSFETs). In an exemplary embodiment, at least transistor M1 is a n-type metal oxide semiconductor (NMOS) Each transistor M1, M2, M3 is connected to a respective resistor R<NUM>, R<NUM>, R<NUM>, and a respective amplifier 32a, 32b, 32c. In an exemplary embodiment, amplifiers 32a, 32b, and 32c are common source amplifiers. High gain circuitry portion further includes feedback resistor RFB1 and feedback capacitor CFB1.

In operation of high gain circuitry portion <NUM>, a signal is input through avalanche photodiode APD. Avalanche photodiode APD is a semiconductor electronic device that exploits the photoelectric effect to convert an optical signal from an optical network unit to electricity. The outputted electric signal proceeds along input trace <NUM> to each of the transistors M1, M2, and M3. Amplifiers 32a, 32b, and 32c are connected in series as cascade amplifiers. A cascade amplifier is a network constructed from a series of amplifiers, where each amplifier sends its output to the input of the next amplifier. The three stages of cascaded amplifiers provide very large gain and low noise. The large gain results from the high output impedance of the input transistor M1, and the low noise is achieved because the spectral intensity noise for a MOSFET transistor is lower than that of a corresponding resistor. The amplified signal is output from the high gain circuitry portion on output trace <NUM>.

The feedback resistor RFB1 and the feedback capacitor CFB1 are used to control the gain and bandwidth of the signal that is output from high gain portion <NUM>. The capacitance of capacitor CFB1 and the resistance of resistor RFB1 are fixed. In an exemplary embodiment, the resistance of the feedback resistor RFB1 is <NUM> KOhm and the capacitance of the feedback capacitor CFB1 is <NUM> fF.

Parasitic capacitance may limit the bandwidth of the high gain circuitry portion <NUM>. In particular, transistors M1-M3 and avalanche photodiode APD may induce parasitic capacitance. To overcome this effect, two inductors <NUM> in series are included in the input stage of the TIA block <NUM> (as seen schematically in <FIG>).

The gain stages in high gain circuitry portion <NUM> are used to optimize noise, bandwidth, and gain performances. The values for noise, bandwidth, and gain are all dependent on each other, as the following discussions and formulas demonstrate:.

Thus, if the resistance is high, the bandwidth is low, which leads to the noise being low. If resistance is low, the bandwidth is high, and the noise is high. Setting the resistance thus involves a trade-off between optimizing for low noise and optimizing for high bandwidth.

Referring now to <FIG>, adaptive gain circuitry portion <NUM> includes, as in high gain circuitry portion <NUM>, avalanche photodiode APD, input trace <NUM>, and transistor M1. Transistor <NUM> is connected to amplifier 32a. These elements function in the same way that they do in high gain circuitry portion <NUM>.

In addition, adaptive gain circuitry portion <NUM> includes inverter transistor M10. Inverter transistor M10 is a single stage complementary metal oxide semiconductor (CMOS) push pull inverter. In an exemplary embodiment, inverter transistor M10 is an p-type metal oxide semiconductor (PMOS). Thus, the combination of NMOS transistor M1 with PMOS transistor M10 forms an inverter gate. Transistors M1 and M10 are biased in their saturation regions to maximize the transconductance and increase the gain bandwidth product of the entire structure of adaptive gain circuitry portion <NUM>.

The resistance of variable feedback resistor RFB2 and the capacitance of variable capacitor CFB2 are controlled by the automatic gain control loopback <NUM> (shown in <FIG>). Automatic gain control loopback <NUM> is a closed-loop feedback regulating circuit, the purpose of which is to maintain a stable signal amplitude at the output of the adaptive gain circuitry portion <NUM>, despite variation of the signal amplitude at the input. The average or peak output signal level is used by the automatic gain control loopback <NUM> to dynamically adjust the resistance of resistor RFB2 and the capacitance of variable capacitor CFB2, thereby correspondingly adjusting the gain. Optionally, there may be more than one automatic gain control loopback <NUM>. The different automatic gain controls may be used for different gains within the adaptive gain circuitry portion <NUM>, with each automatic gain control signal being active for a different input value.

In an exemplary embodiment, the resistance of resistor RFB2 ranges from <NUM> to <NUM> Ohm, and the capacitance of capacitor CFB2 ranges from <NUM> femtoFarad (fF) to <NUM> fF. Such values for resistance and capacitance are suitable for optimizing the gain to fit input signal pulses of approximately <NUM> uA to 3mA.

Reference is now made to <FIG> and <FIG>, in which high gain circuitry portion <NUM> and adaptive gain circuitry portion <NUM> are combined into a single architecture with a shared input portion. As in the embodiment of <FIG>, high gain circuitry portion <NUM> has a plurality of cascaded amplifiers 32a-c. As in the embodiment of <FIG>, adaptive gain portion <NUM> includes at least one inverter M10 and a variable feedback capacitor CFB2 and variable feedback resistor RFB2 controllable by automatic gain control loop <NUM>.

Transistor M1 is circled in <FIG> and <FIG> to indicate that it is activated in both the configuration of <FIG> and the configuration of <FIG>. Thus, transistor M1 (which, in exemplary embodiments, is a metal oxide semiconductor transistor) is part of the shared input portion.

The architecture of <FIG> and <FIG> further includes switches SW<NUM>, SW<NUM>, SW<NUM>, SW<NUM>, SW<NUM>, and SW<NUM>. The switches control whether the high gain portion <NUM> or the adaptive gain portion <NUM> is active. In the configuration of <FIG>, switches SW<NUM>, SW<NUM>, and SW<NUM> are open, switches SW<NUM>, SW<NUM>, and SW<NUM> are closed, and the high gain circuitry portion <NUM> is active. To represent this status, the high gain circuitry portion <NUM> is indicated with a grey background, and the output trace <NUM> of the high gain portion <NUM> is indicated with a thicker line than the output trace <NUM> of adaptive gain portion <NUM>. By contrast, in the configuration of <FIG>, SW<NUM>, SW<NUM>, and SW<NUM> are closed, switches SW<NUM>, SW<NUM>, and SW<NUM> are open, and the adaptive gain circuitry portion <NUM> is active. To represent this status, the adaptive gain circuitry portion <NUM> is indicated with a grey background, and the output trace <NUM> of the adaptive gain portion <NUM> is indicated with a thicker line than the output trace <NUM> of high gain portion <NUM>. As used in this disclosure, switches SW<NUM>, SW<NUM>, and SW<NUM> are collectively referred to as adaptive gain switches, because the adaptive gain portion <NUM> is activated when those switches are closed. Correspondingly, switches SW<NUM>, SW<NUM>, and SW<NUM> are collectively referred to as high gain switches, because the high gain portion <NUM> is activated when those switches are closed. In exemplary embodiments, both the high gain switches and the adaptive gain switches are transistors.

The peak detector (shown in <FIG>) provides information for controlling the status of the high gain switches and the adaptive gain switches. When a burst-mode signal is input to the peak detector, the peak detector detects the current of the input signal. An input current sensing algorithm evaluates each incoming burst. Based on the current of the input signal, the burst mode receiver determines whether the signal should be amplified using the high gain circuitry portion <NUM> or the adaptive gain circuitry portion <NUM>. If the current is in a first range, the burst mode receiver closes the high gain switches and opens the adaptive gain switches, to thereby activate the high gain circuitry portion <NUM>. If the detected current is in a second range, the burst mode receiver closes the adaptive gain switches and opens the high gain switches, to thereby activate the adaptive gain portion <NUM>. This entire process takes place extremely quickly. In some embodiments, the peak detector monitors the input current of each burst, and the burst mode receiver switches between the high gain circuitry portion <NUM> and the adaptive gain circuitry portion <NUM>, within an acquisition time of fewer than <NUM> ns.

In the claimed invention, the burst mode receiver receives signals with a dynamic range of between <NUM>µA and <NUM> mA. In such embodiments, the dynamic range of the burst mode receiver is <NUM> dB. The input current of the first range is between <NUM> and <NUM>µA, and the input current of the second range is between <NUM>µA and <NUM> mA. There is an overlap region of approximately <NUM>µA, in which the signal may be directed to either the high gain circuitry portion <NUM> or the adaptive gain circuitry portion <NUM>. The hysteresis, or overlap, region is set as <NUM>µA. The overlap region is used because it is not realistic to switch at exactly one point along a spectrum of signal currents. The hysteresis region thus enables the burst mode receiver to make a better decision whether to activate the high gain circuitry portion <NUM> or the adaptive gain circuitry portion <NUM>.

<FIG> is a schematic representation of a burst mode receiver <NUM>, of which burst mode transimpedance amplifier <NUM> is a component. In addition to transimpedance amplifier <NUM>, burst mode receiver <NUM> additionally includes burst mode limiting amplifier <NUM> and burst mode clock data recovery <NUM>. The burst mode receiver <NUM> is used to amplify a soft burst signal 110a to an equivalent signal 110b with a larger amplitude. Each incoming burst has a different amplitude. To detect each part of the signal without errors, it is first necessary to detect the amplitude, and then to set a decision threshold at the middle of the burst's amplitude. Each portion of the amplified signal is then evaluated to see whether it is above the decision threshold (and should be assigned a "<NUM>" value) or below the decision threshold (and should be assigned a "<NUM>") value.

The burst mode receiver schematically represented in <FIG> complies with IEEE standard <NUM>. 03av, but improves over the performance of other receivers satisfying the IEEE <NUM>. 03av standard. In a standard burst mode receiver complying with standard <NUM>. 03av, the line rate is <NUM> Gbps, the dynamic range is 22dB, and the sensitivity is -28dBM with a bit error ratio of 1E-<NUM>. In burst mode receivers with the TIA chip of certain embodiments, the dynamic range is <NUM> dB, the sensitivity is -33dBm, and the bit error ratio is 1E-<NUM>. Thus, the dynamic range is greater, the sensitivity is lower, and the bit error ratio is lower.

<FIG> is a schematic representation of a passive optical network <NUM> incorporating the burst mode receiver <NUM>, according to embodiments of the present invention. In the illustrated embodiment, three customers at optical network units 202a, 202b, and 202c transmit data to an optical line terminal (OLT) (not shown) in a time division multiple access (TDMA) format. The number of customers could alternatively be <NUM>, as is typically used in a passive optical network. Alternatively, the increased dynamic range enabled by the disclosed embodiments may allow the passive optical network to include additional customers at various distances from the optical line terminal, for example, double the number of typical customers. In addition or in the alternative, the distance between each optical network unit and the furthest customer may be doubled.

The electrical data generated by each optical network unit 202a-c is converted to optical data using laser drivers 204a-c and laser diodes LD1, LD2, and LD3.

Each customer is located at a different distance from the optical line terminal, as represented by the fibers 206a-206c of different lengths. Fiber 206a is a comparatively short distance from the optical line terminal; fiber 206b is a middle-range distance from the OLT, and fiber 206c is a long distance from the OLT. As a result, the signal is attenuated more along fiber 206c than along fiber 206b, and more along fiber 206b than fiber 206a. All of the optical data is then time multiplexed on optical multiplexer <NUM>, and is transmitted from multiplexer <NUM> on a single optical fiber. The optical data burst is then converted into electrical current by avalanche photodiode APD. In some embodiments, the current Iin has an amplitude ranging from 3uA for the remotest customer 206c to 3mA for the nearest customer 202a (-33dBm to -3dBm).

A TIA chip <NUM> includes a burst mode transimpedance amplifier which amplifies the electric signal. The passive optical network <NUM> further includes limiting amplifier <NUM>, low pass filter <NUM>, and clock & data recovery circuit <NUM>. The low pass filter is used to reduce noises coming from high frequencies, e.g., frequencies above the working frequency. Data and clock information are then output to the optical line terminal.

In an exemplary embodiment, the data is uploaded upstream from the optical network units <NUM> to the optical line terminal at a wavelength <NUM>, and downloaded from the optical line terminal to the optical network units at a wavelength1490 nm. These values are merely exemplary, and other values for the wavelength may similarly be used.

Claim 1:
A burst mode receiver (<NUM>) for a passive optical network, comprising:
(i) a high gain circuitry portion (<NUM>) having a plurality of cascaded amplifiers (32a-c), each of the cascaded amplifiers configured to increase a gain of an input signal, and a plurality of high gain switches (SW3, SW4, SW6); and
(ii) an adaptive gain circuitry portion (<NUM>) having at least one amplifying inverter comprising an p-type metal oxide semiconductor, PMOS, transistor (M10), the adaptive gain circuitry portion (<NUM>) configured to adaptively control the gain of the input signal, and a plurality of adaptive gain switches (SW1, SW2, SW5); and
wherein the high gain circuitry portion (<NUM>) and the adaptive gain circuitry portion (<NUM>) comprise a shared input portion comprising at least one n-type metal oxide semiconductor, NMOS, transistor (M1);
wherein the combination of PMOS transistor (M10) with NMOS transistor (M1) forms the amplifying inverter and a first amplifier (32a) of the plurality of cascaded amplifiers (32a-c) comprises the NMOS transistor (M1);
wherein, when a peak detector (<NUM>) detects input current in a first range, the burst mode receiver (<NUM>) is configured to activate the high gain circuitry portion (<NUM>) and de-activate the adaptive gain circuitry portion (<NUM>), in which the high gain switches (SW3, SW4, SW6) are closed and the adaptive gain switches (SW1, SW2, SW5) are opened, and when the peak detector detects input current in a second range, the burst mode receiver (<NUM>) is configured to activate the adaptive gain circuitry portion (<NUM>) and de-activate the high gain circuitry portion(<NUM>), in which the high gain switches (SW3, SW4, SW6) are opened and the adaptive gain switches (SW1, SW2, SW5) are closed; and
wherein the first range is between <NUM>µA and 35µA, and the second range is between 25µA and <NUM> mA comprising a hysteresis, or overlap, region of <NUM>µA.