Patent Description:
Embodiments of the present disclosure relate in particular to integrated circuits comprising drivers of active loads or capacitive loads and corresponding pre-driver circuits.

Testing cost is one of the major contributions on the overall manufacturing cost of an electronic circuit, specifically of an integrated circuit.

In integrated circuits are for instance used circuit configured to supply a current to a load, for instance, e.g. output drivers, by way of example in transmitting device. Such output drivers usually include a pair of switches, e.g. same type MOSFET transistor, arranged in series or totem pole between a voltage supply, to which the so-called pull-up switch is coupled, and a lower voltage such as ground, to which the so-called pull-down switch is coupled. The switches have a common node, usually the source of the pull-up switch coupled to the drain of the pull-down switch. A load can be represented by an active load or a capacitive load, and can be embodied by a circuit representing the load or a circuit component, e.g. capacitor.

Also, they can be seen as half bridges, where the half bridge is made of two, e.g. N-channel, FET as switches, the low side coupled between ground and phase node, i.e. the common node, and the high side coupled between the battery voltage and phase node.

In order to improve the behavior, for instance the dynamic characteristics, pre-driver circuits are provided which output is coupled to the control electrode, e.g. gate, of a respective switch to drive such switch with the current and/or dynamic required.

Testing cost of gate pre-drivers depends on the number of parameters to be tested (high/low output voltage, current limitation/ peak current, rise/fall time. etc.) in order to guarantee the pre-driver functionality and detect possible defectiveness of manufacturing process. For each of these parameters a test is present at an automatic test equipment (ATE).

In <FIG> it is shown schematically a solution according to the prior art, where with the reference <NUM> is indicated an electronic circuit <NUM>, in particular an integrated electronic circuit, comprising a gate pre-driver <NUM>, schematized as an operational amplifier-based circuit which is driven by a logic integrated circuit <NUM>. With <NUM> is indicated an Automated Testing Equipment <NUM>. The electronic circuit <NUM> comprises a voltage supply input terminal VS, which is coupled to the power supply terminal of the pre-driver <NUM>. A gate output terminal G of the electronic circuit <NUM> is, coupled to the output of the pre-driver <NUM>, while a source terminal S is coupled to the other power supply terminal of the pre-driver <NUM>. Also the integrated electronic circuit <NUM> includes a test command input terminal TMPIN, which is coupled to an input of the integrated circuit logic <NUM>.

The automatic test equipment <NUM>, which is configure to couple through terminals G, S, TMPIN and to the electronic circuit <NUM>, comprises a load circuit <NUM>, which is embodied by a power FET, but also can be embodied by a capacitive load, coupled by its two terminals between gate terminal G and source terminal S. In the case of a power FET, as shown in <FIG>, the gate terminal G is coupled to the gate of the power FET. The automatic test equipment <NUM> further comprises a time measurement unit <NUM> coupled between the same terminals G,S, a voltage power supply <NUM> coupled between the voltage supply terminal VS and ground GND, a PWM generator <NUM> coupled to the test command terminal TMPIN.

Thus, the pre-driver <NUM> is coupled to the load circuit <NUM> in the automatic test equipment <NUM>, the voltage supply of the pre-driver <NUM> is supplied by the voltage power supply <NUM> in the automatic test equipment <NUM> and the logic <NUM> receives test command signal SCMD from the external PWM generator <NUM> in the automatic test equipment through the test command terminal TMPIN.

Time measurements necessary to tests are performed with an automatic test equipment dedicated instrument, the time measurement unit <NUM>.

In <FIG> is not shown the stage configured to supply a driving signal to a load, in particular a driver circuit, which is driven by the pre-driver <NUM>, in order to better understand the coupling of the pre-driver <NUM> to the automatic test equipment <NUM> for test.

In <FIG> it is shown instead a more detailed view of an implementation of the circuits of <FIG>. The IC logic <NUM> generates a pullup command PU CMD and a pull-down command PD CMD for each of a pre-driver 121a and 121b, comprised in pre-driver block <NUM> which are respectively coupled to the gates of a pullup MOSFET 122a and a pull down MOSFET 122b, both N MOSFET in the example, which are the power output devices of a driver circuit <NUM>, which represents a stage configured to supply a driving signal, e.g. current, to a load, and are coupled in a pull-up pull down configuration, i.e. the source of pullup MOSFET 122a is coupled to the drain of the pulldown MOSFET 122b. The voltage supply at terminal VS is supplied to the voltage supply terminal of drivers 121a, 121b and to the drain electrode of the pull-up MOSFET 122a, while the source is coupled to the source terminal S. The central common node of MOSFETS 122a, 122b is coupled to the gate terminal.

In the automatic test equipment <NUM> the gate terminal G is coupled to the gate of a power FET <NUM>, representing the load circuit <NUM>. The drain of the power FET <NUM> is coupled to the voltage supply VCC by a load resistance Rload. The source of the power FET <NUM> is coupled to the source terminal S and to the ground GND. Also an input of the time measuring unit <NUM> is coupled to the gate terminal G, specifically is brought to an input of a comparator 222a and of a comparator 222b, which have programmable thresholds and provide start and stop signals SS, SP, to begin and to halt counting respectively, to a counter <NUM> comprised in the unit <NUM>. As mentioned, a voltage generator embodies the voltage power supply <NUM> and the PWM generator <NUM> supplies pulses to the command terminal TMPIN.

For instance the following steps of a testing procedure are performed, by the arrangement of <FIG> and <FIG>:.

the turn ON time of FET <NUM> is measured by automatic test equipment <NUM>, which includes the time measuring unit coupled to terminal G. The comparators 222a, 222b have configurable thresholds and provide to the counter <NUM> start and stop signals SS, SP.

By such a solution all the parameters of a pre-driver are measured by coupling external instrumentation to pins, i.e. input and output terminals, of the pre-driver in order to read voltage, current or time interval. However, the coupling/decoupling of the automating test equipment is expensive in term of test time and could generate issue on test program repeatability.

Document <CIT> discloses a system comprising an automatic test equipment receiving diagnostic information from a device under test having a built-in self-test system (BIST).

On the basis of the foregoing description, the need is felt for solutions which overcome one or more of the previously outlined drawbacks.

According to one or more embodiments, such an object is achieved through a circuit having the features specifically set forth in the claims that follow. Embodiments moreover concerns a related system as well as a corresponding method.

The claims are an integral part of the technical teaching of the disclosure provided herein.

As mentioned in the foregoing, the present disclosure provides solutions regarding a system for testing comprising an electronic circuit to be tested and an automatic testing equipment,.

In variant embodiments, said time measuring unit receives the signal at the output of the driver stage and compares such signal to at least one threshold.

In variant embodiments, said electronic circuit to be tested comprises said pass fail check module.

In variant embodiments, said electronic circuit to be tested comprises a series of output terminals for coupling the output of said time measuring unit with an input/output interface module in the automatic test equipment.

In variant embodiments, said electronic circuit comprises a series of output terminal for coupling the output of said pass fail check module with an input/output interface module in the automatic test equipment.

In variant embodiments, said automatic test equipment comprises a PWM module configured to send a command signal to said logic module through a command terminal of said electronic circuit to be tested to which the automatic test equipment is coupled.

In variant embodiments, said automatic test equipment comprises an input/output interface module configured to send a command signal to said logic module through input interface terminals to which the automatic test equipment is coupled.

In variant embodiments, said time measuring unit comprises a counter, configured to receive start and stop signal, respectively starting and stopping its count, a first and second comparator having one input coupled to the output node and the other input coupled to said lower potential node through a respective voltage generator generating a respective threshold voltage, a multiplexer receiving as input the outputs of said comparators, and the signals, in particular counterphase signals, at the output of said logic module issued to each of the pre-drivers and which two outputs are coupled so to represent the start and stop signals of said counter, said multiplexer being configured on the basis of a selection signal, in particular generated by the logic module, to select among its inputs said start and stop signals.

In variant embodiments, said comparators correspond to comparators performing a voltage monitoring function, in particular VGS ON and VGS full on comparators, in the pre-driver circuit.

The present disclosure also provides solutions regarding an electronic circuit to be tested configured to operate in the system of any of the embodiments.

The present disclosure also provides solutions regarding a method for operating a system for testing according of any of the embodiments, comprising commanding by the automatic test equipment to the logic the execution of a built-in self-test sequence of commands,
said built-in self-test sequence of commands comprising issuing commands to operate, in particular activate or deactivate, the pre-driver stage according to a given mode of operation and commands to select signals operating said time measuring unit among said commands to operate the pre-driver stage and signals at the output of the stage configured to supply a driving signal to a load.

In variant embodiments, said built-in self-test sequence of commands comprises one or more test procedures including.

In variant embodiments, said built-in self-test sequence of commands comprises a procedure for measuring an ON time or an OFF time respectively of the pre-driver including.

In variant embodiments, said built-in self-test sequence of commands comprises a test procedure for measuring the ON slew rate or OFF slew rate including.

In variant embodiments, said built-in self-test sequence of commands comprises a test procedure for measuring Voltage Output Low logic level or Voltage Output High logic level respectively, including.

In variant embodiments, said test procedure for measuring the ON slew rate or OFF slew rate respectively comprises using a rising edge signal of the first comparator, occurring at a given time as start signal, using a rising edge of the second comparator occurring at a given time as stop signal or using the falling edge signal of the comparator occurring at a given time as start signal, while the stop signal is the falling edge of comparator occurring at a time, respectively.

In variant embodiments, the method includes computing a ON slew rate or OFF slew rate value respectively as ratio of the difference of the thresholds to the difference of time between the rising edges of comparators or ratio of the difference of the thresholds to the difference of time between falling edges of comparators, in particular computing an ON peak current or an OFF peak current as product of an output capacitance and of said ON slew rate or OFF slew rate.

The present disclosure also provides solutions regarding a computer program product that can be loaded into the memory of at least one computer and comprises parts of software code that are able to execute the steps of the method according to any of the previous embodiments when the product is run on at least one computer.

Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:.

In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment.

Figures parts, elements or components which have already been described with reference to <FIG> and <FIG> are denoted by the same references previously used in such Figures; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

The main parameters to be tested for pre-drivers includes delay times, slew rates, output low voltage VOL, output high voltage VOH and ON/OFF peak current. The solution here described provides capability to measure all such parameters by a unique built-in self-test, embedded into the integrated circuit, based on an internal time measuring unit comprising internal configurable voltage monitors and internal counter.

This allows to measure all relevant test parameters inside the integrated circuit and then compare them with expected value, preferably also inside the integrated circuit. The final result of the comparation (Pass/Fail) is sent to the automatic test equipment through a fast communication interface.

In <FIG> it is shown the solution here described of system for testing following the general schematization of <FIG>. Below a simplified scheme of the proposed solution is reported. Same numbers indicate components with a same function.

The system comprises an electronic circuit is indicated with <NUM>', as it includes the same components of circuit <NUM>, i.e. the gate pre-driver <NUM>, which is driven by the logic integrated circuit <NUM>, and an Automated Testing Equipment <NUM>'. The electronic circuit <NUM>' in addition with respect to circuit <NUM> includes a time measuring unit <NUM>, coupled between the gate terminal G and the source terminal S, which output is coupled through interface terminals <NUM> to an I/O interface <NUM> to a fast input output interface <NUM>, for instance a fast SPI (Serial Peripheral Interface) interface in the automatic test equipment <NUM>', which is shown in <FIG>. The automatic test equipment <NUM>' thus differs from the automatic test equipment <NUM> of <FIG> at least in that does not include the time measuring unit <NUM>, which is instead comprised in the electronic circuit, in particular integrated circuit, <NUM>'.

The pre-driver <NUM> is coupled to the POWER FET/capacitive load <NUM> present on the automatic test equipment board <NUM>' as well.

Thus, in general the electronic circuit <NUM>' and the automatic test equipment <NUM> are operated as follows:.

In <FIG> it is shown instead a more detailed view of an implementation of the circuits of <FIG>. Also in this case, with respect to the implementation of prior art circuits of <FIG>, same numbers indicate components with a same function. As mentioned, the electronic circuit <NUM>' includes the time measuring unit <NUM>, coupled between the gate terminal G and the source terminal S, which output is coupled through the I/O interface terminals <NUM> to the interface <NUM>.

The time measuring unit <NUM> comprises a first comparator 142a, i.e. a differential amplifier, which positive input is coupled to the gate terminal G, while its negative input is coupled to the source terminal S, with interposed in series a first threshold generator voltage 141a, which applies a first threshold voltage TH1 to such negative input. The time measuring unit <NUM> further comprises a second comparator 142b, also a differential amplifier, which positive input is coupled to the gate terminal G, while its negative input is coupled to the source terminal S, with interposed in series a second threshold generator voltage 141b, which applies a second threshold voltage TH2 to such negative input. The output of the comparators 141a and 141b are brought to a multiplexer <NUM> which also receives the commands PU CMD and PD CMD, which in particular are counterphase signals, issued by the IC logic <NUM> to the pre-drivers 121a and 121b. The multiplexer <NUM> supplies the start signal SS and stop signal SP to a counter <NUM> under the control of a selection signal SEL also issued by the logic <NUM>. The counter <NUM> supplies its output to a pass/fail check block <NUM>, which in turn supplies its output to the input/output interface terminals <NUM>. As shown, an automatic test equipment <NUM>' corresponds to the automatic test equipment <NUM>, however it does not include the time measuring unit <NUM>. The automatic test equipment <NUM>' includes instead an interface module <NUM> coupled to the input/output interface terminals <NUM> to receive the output of the pass/fail check block <NUM>.

The testing method may thus comprise the following steps:.

The system described with reference to <FIG> and perform thus may be configured to perform a built-in test sequence stored in the logic <NUM> to measure and check different parameters of the pre-driver <NUM>.

This corresponds in general to performing a method for operating a system for testing such as the one of <FIG> or <FIG> comprising commanding SCMD by the automatic test equipment <NUM>' to the logic <NUM> the execution of a built-in self-test sequence of commands,
said built-in self-test sequence of commands comprising issuing commands PU CMD, PD CMD to operate, in particular activate or deactivate, the pre-driver stage <NUM> according to a given mode of operation and commands SEL to select signals SS, SP operating said time measuring unit <NUM> among said commands PU CMD, PD CMD to operate the pre-driver stage <NUM> and signals at the output G of the driver stage 122a, 122b.

Such built-in self-test sequence of commands may comprise one or more test procedures, with reference to <FIG> and related description, including.

For instance, such built-in test sequence may include a Turn ON delay time test. In such test a ON command signal of pre-driver, for instance the command PU CMD low to high transition sent to the pull-up switch 122a, also sent to the multiplexer <NUM>, is used to start (generating start signal SS) the internal counter <NUM>. In other words, the multiplexer <NUM>, under the control of the selection signal SEL issued by the logic <NUM> according to the built-in test sequence, selects the command PU CMD as start signal SS. The stop signal SP is then represented by the rising edge of comparator 142a, which output is also selected by the multiplexer <NUM>, under the control of the selection signal SEL issued by the logic <NUM> according to the built-in test sequence. The time measured by the counter <NUM> is the turn ON time of the pre-driver <NUM>. It is underlined that a comparator coupled to the gate and source terminals is normally present in the pre-driver architectures, named for instance VGS comparator, therefore, such already present comparator can be re-used as comparator 142a, without providing another comparator.

For instance, such built-in test sequence may include a Turn OFF delay time test. In such test the OFF command signal, for instance the PD CMD low to high transition sent to the pull-down switch 122b, also sent to multiplexer <NUM>, is used to start (generating start signal SS) an internal counter <NUM>. In other words, the multiplexer <NUM>, under the control of the selection signal SEL issued by the logic <NUM> according to the built-in test sequence, selects the rising edge of command PD CMD as start signal SS. The stop signal SP is the falling edge of comparator 141b, which output is also selected by the multiplexer <NUM>, under the control of the selection signal SEL issued by the logic <NUM> according to the built-in test sequence. The time measured by the counter <NUM> is the turn OFF time of the predriver. Also a comparator which can be reused as comparator 141b is usually already present into pre-drivers architecture for instance to check the full VGS value.

The counter <NUM> read-out is compared with a customizable pass-fail threshold, TH, in the pass/fail check block <NUM>, if counter <NUM> value is below the threshold TH the check block <NUM> considers the test result good (pass) otherwise it is considered fail.

Thus, a possible test executed by logic <NUM> as part of the built-in test for measuring turn ON time is the following:.

The corresponding signals are shown in <FIG>, which shows a behavior yielding a "pass" result R. As the pullup command PU CMD is issued by logic <NUM>, i.e. start signal SS for the counter <NUM>, the gate source voltage VGS start rising after a delay and when it reaches the ON threshold TH1, the comparator 142a passes from low to high logic level, which is interpreted as stop signal SP for the counter <NUM>. An elapsed time te between the start and stop signal SS, SP is shown. The elapsed time te is lower than the length of the threshold signal TH thus the result R of the test is pass.

The threshold signal TH is shown here as a timeout duration, such as in watchdog counters, thus it may be the counter itself which has a timeout value, i.e. TH, stored, in particular set by the logic <NUM>, and issues a timeout signal if the count of counter <NUM> surpasses the timeout value, which the pass/fail check logic <NUM> is configured to interpret as 'fail'. In other embodiments, the counter <NUM> may simply send the ON duration measured, i.e. its count, to the pass/fail check logic <NUM>, which compares them to the threshold TH, outputting a result R of pass or fail depending on the count being lower or greater than the threshold TH value indicated by the logic <NUM>.

<FIG> in the same way shows a fail result. The slope of the gate source voltage VGS is less steep, resulting in a longer elapsed time before reaching ON threshold TH1, thus the elapsed time te is longer than the threshold signal TH thus the result R of the test is fail for the ON time.

A possible sequence executed by logic <NUM> as part of the built-in test for measuring turn OFF time is the following:.

The corresponding signals are shown in <FIG>, which shows a pass result. As the pulldown command PD CMD is issued by logic <NUM>, i.e. start signal SS for the counter <NUM>, the gate source voltage VGS start decreasing after a delay and when it reaches the OFF threshold TH2, the comparator 142b passes from high to low logic level, which is interpreted as stop signal SP for the counter. The elapsed time te between the start and stop signal SS, SP is shown. The elapsed time te is lower than the threshold signal TH' for OFF time internally configured thus the result R of the test is pass.

<FIG> in the same way shows a fail result. The slope of the gate source voltage VGS is less steep in its decrease, resulting in a longer elapsed time te before reaching OFF threshold TH2, thus the elapsed time te is longer than the threshold signal TH, thus the result R of the test is fail for the OFF time.

Summing up, the method according to embodiments may include that said built-in self-test sequence of commands comprises procedures for measuring an ON time or an OFF time respectively of the pre-driver <NUM> including.

The built-in test sequence may include operation performed by the system of <FIG> and <FIG> to perform also tests on the slew rate.

For instance, an ON Slew rate test may include that a rising edge signal REa of comparator 142a, occurring at time tREa is used to start the internal counter <NUM>, i.e. as start signal SS. The stop signal SP may be represented by a rising edge REb of comparator 142b occurring at time tREb. The time measured by the counter <NUM> allows the calculation of ON slew rate SRON.

Dually, for an OFF Slew rate test, the falling edge signal FEb of comparator 142b occurring at time tFEb is used to start, signal SS, the internal counter <NUM>, while the stop signal SP is the falling edge FEa of comparator 142a occurring at time tFEa. The time measured by the counter <NUM> allows the calculation of OFF slew rate SROFF.

As mentioned, according to an important aspect of the solution here described, comparators 142a and comparators 142b may be already present in the pre-drivers architecture to check the gate source voltage. Thus the solution may simply require to apply thresholds TH1, TH2 to such already present comparators, for instance by having controlled switches coupling the generators 141a, 141b to the respective negative input of comparators 142a, 142b during the built-in test sequence execution.

Thus, a possible test executed by logic <NUM> as part of the built-in test for measuring ON slew rate may be the following:.

This exemplified in time diagram of <FIG> (pass) and <FIG> (fail).

In the same way, a possible test executed by logic <NUM> as part of the built-in test for measuring OFF slew rate is the following:.

Thus, the built-in self-test sequence of commands may comprise a test procedure for measuring the ON slew rate and/or OFF slew rate respectively including.

The system of <FIG> and <FIG> can be used to perform also tests on the value of the Voltage Output Low logic level VOL and of the Voltage Output High logic level VOH.

For instance, to measure Voltage Output Low logic level VOL, the comparator 142b can be configured with a threshold close (above) to the maximum value of the Voltage Output Low logic level VOL. When the pre-driver 121a is in OFF state, the test is considered "pass" if the comparator 142b output state is <NUM>. Otherwise, the test is fail.

Dually, to measure the Voltage Output High logic level VOH, the comparator 142a can be configured with a threshold close (below) to the minimum value of Voltage Output High logic level VOH. When the pre-driver 121a is in ON state, the test is considered "pass" if the comparator output state is <NUM>. Otherwise, the test is fail.

A possible sequence for measuring Voltage Output High logic level VOH comprised in the built-in test sequence performed by logic <NUM> is the following:.

This exemplified in time diagram of <FIG> (pass) and <FIG> (fail), which represent testing Voltage Output Low logic level VOL. In <FIG> the gate source voltage VGS raises, after issuing PD CMD, toggling the first comparator 142a output then the second comparator 142b, i.e. passing thresholds TH1 and TH2, to reach a maximum Voltage Output Low logic level VOLm below the threshold TH1. In <FIG> gate source voltage VGS reaches a level above threshold TH1, therefore the output of second comparator 142b does not toggle. Dually, testing of a Voltage Output High logic level VOH is possible, after issuing PU CMD, by checking the toggling output of the comparators whether a minimum Voltage Output High logic level VOH, above TH2, is reached. This second test is not shown in the figures.

Thus, said built-in self-test sequence of commands may comprises a test procedure for measuring Voltage Output Low logic level VOL or Voltage Output High logic level VOH respectively, including.

The system of <FIG> and <FIG> can be used to perform also tests on the ON/OFF Peak current. This test may be just a calculation based on the previously described slew rate tests, giving values SRON and SROFF. Knowing, the output capacitance Cout associated to load <NUM>, the value of thresholds TH1, TH2 and the measure of the internal counter <NUM>, the ON/OFF peak current can be measured by the following equations: <MAT> <MAT>.

Basically, the test on the ON/OFF Peak current makes use of the previously described method to test the slew rate, which in turns make use of thresholds TH1, TH2. Once SRON and SROFF values are measured with the already described method, peak current Ipeak can be retrieved by means of simple calculation by knowing the output capacitance Cout on gate output terminal G.

Thus, the test procedure for measuring the ON slew rate or OFF slew rate respectively comprises using a rising edge signal Rea of the first comparator 142a, occurring at a given time tREa as start signal SS, using a rising edge REb of the second comparator 142b occurring at a given time tREb as stop signal SP or using the falling edge signal FEb of the comparator 142b occurring at a given time tFEb as start signal (SS), while the stop signal SP is the falling edge FEa of comparator 142a occurring at a time tFEa, respectively.

Then, the test may include computing a ON slew rate SRON or OFF slew rate SROFF value respectively as ratio of the difference of the thresholds TH2, TH1 to the difference of time tREb - tREa, between the rising edges of comparators 142a and 142b or ratio of the difference of the thresholds TH2, TH1 to the difference tFEa - tFEb, of time between falling edges of comparators 142b, 142a, in particular computing an ON peak current or an OFF peak current as product of an output capacitance Cout and of said ON slew rate SRON or OFF slew rate SROFF.

In <FIG> a second embodiment of the system for testing here described is shown. In this case the electronic circuit <NUM>" includes a counter <NUM> which however is coupled to the input/output interface <NUM> through terminals <NUM>, without interposition of the pass/fail check <NUM> of <FIG>. The input/output interface <NUM> feeds the result of the counter <NUM> to a pass/fail check block <NUM> comprised in the automatic test equipment <NUM>". In this case, after the execution of the built-in test at the circuit <NUM>", the automatic test equipment <NUM>" receives the counter <NUM> measured values and can configure test limits and compare it with such measured results to determine pass-fail criteria.

In <FIG> a third embodiment of the system for testing here described is shown. In this case, the electronic circuit <NUM>‴ and automatic test equipment <NUM>‴ correspond to those of <FIG>, with the exception of an input/output test start interface <NUM> being present in the automatic test equipment <NUM>", which is coupled to interface terminals <NUM> on the electronic circuit <NUM>"', which bring signal to the logic <NUM>. In this case the automatic test equipment <NUM>‴ configures the test setup and test start with I/O communication interface <NUM>. At the end of test the information measured is sent to automatic test equipment through I/O interface <NUM>. Automatic test equipment configures test limits and compares it with measured results to determine pass-fail criteria.

The described solution thus has several advantages with respect to the prior art solutions.

The solution proposed reduces test time related cost by replacing all the test of a pre-drivers with built-in self-tests.

Also, the proposed solution has a negligible impact on design activity and requires only SPI communication interface because the test is done internally in the device.

The proposed solution determines also cost saving at automatic test equipment level, since there is no need to connect and disconnect external instruments and no need to configure them.

Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.

As inside a single integrated circuit there are several pre-drivers present, a plurality or all of such pre-drivers can be tested performing the built-in test sequence in parallel decreasing furthermore test time cost.

Claim 1:
A system for testing comprising an electronic circuit to be tested and an automatic testing equipment,
said electronic circuit (<NUM>; <NUM>'; <NUM>"; <NUM>"') to be tested comprising a stage (122a, 122b) configured to supply a driving signal to a load, said stage (122a, 122b) comprising a pullup switch (122a) coupled to the voltage supply (VS) and a pulldown switch coupled to a lower potential than the voltage supply (GND, S), in particular ground, coupled to each other in an output node (G), and a pre-driver stage (<NUM>) comprising pre-driver circuits (121a, 121b) which output is coupled to the control input of respective pullup (122a) and pull down (122b) switch of the stage (122a, 122b) configured to supply a driving signal to a load,
said electronic circuit (<NUM>; <NUM>';<NUM><NUM>"; <NUM>‴) to be tested comprising circuits (<NUM>, <NUM>) for testing the pre-driver stage (<NUM>) under the control (SCMD) of the automatic testing equipment (<NUM>; <NUM>'; <NUM>"; <NUM>‴) comprising a test logic module (<NUM>) configured to operate a built-in test sequence comprising test commands (PU CMD, PD CMD) for the pre-driver stage under the control of an external test signal (SCMD) issued by the automatic test equipment, the automatic test equipment (<NUM>, <NUM>', <NUM>") comprising a test load (<NUM>) to be coupled to said output node (G) of the stage (122a, 122b) configured to supply a driving signal to a load, said system for testing comprising a time measuring unit (<NUM>) configured to measure duration of signals at the output (G) of the stage (122a, 122b) configured to supply a driving signal to a load coupled to a pass fail check module (<NUM>), configured to evaluate if said duration of signals at the output (G) of the stage (122a, 122b) configured to supply a driving signal to a load satisfies a pass criterion,
wherein
said time measuring unit (<NUM>) is comprised in said electronic circuit to be tested and it started and stopped under the control of commands including commands (PU CMD, PD CMD, SEL) issued by said logic (<NUM>) during execution of said bult-in test sequence.