Patent Description:
In many applications the effect of a quantum well can be increased by providing multiple quantum wells in a stack. In the case of an emitter, such as a laser, this may increase the rate of stimulated emission in the emitter, whereas in the case of an absorber, it may increase the rate of absorption.

A commonly commercially utilised material platform for optoelectronic devices is indium phosphide (InP), which allows for integration of optically active and passive functions into so-called photonic integrated circuits (PICs).

<CIT> relates to an optical semiconductor device. <CIT> relates to a semiconductor optical modulator having a quantum well structure for increasing effective photocurrent generating capability.

It is desirable to provide a more reliable method of fabricating a semiconductor structure with multiple quantum wells.

Examples described herein relate to methods of fabricating semiconductor structures. In particular, they relate to fabricating semiconductor structures with multiple quantum wells.

As will be elaborated below, examples described herein provide an improved semiconductor structure. Such a structure may provide reduced scattering of light being transmitted through the structure, may provide increased rates of stimulated emission in light emitting portions and may provide increased rates of absorption in light absorbing portions. This allows for a more efficient optoelectronic devices and therefore for a more efficient PIC.

<FIG> is a flow diagram illustrating, in a general manner, a method <NUM> of fabricating a semiconductor structure with multiple quantum wells, according to examples. A corresponding example semiconductor structure is described below with reference to <FIG>.

At block <NUM>, a substrate is provided. The substrate comprises a binary semiconductor compound having a first lattice constant.

For example, the substrate may be an InP substrate. That is the substrate comprises mainly InP. The substrate <NUM> may be purely InP (within acceptable purity tolerances) or may comprise other materials such as dopants or impurities with the material comprising at least <NUM> % InP. For example, the substrate is doped with a dopant material so that the substrate may be considered n-doped or the substrate is doped with a dopant material so that the substrate may be considered p-doped.

At block <NUM>, the method <NUM> comprises depositing, at least: a first layer on the substrate, and a second layer in contact with the first layer to form a first stack of substantially planar semiconductor layers on the substrate. The first layer is of a first semiconductor alloy comprising InP and the second layer is of a second semiconductor alloy comprising InP.

The first stack comprises a plurality of layers. A number of layers in the first stack is less than a threshold number of layers above which one or more layers of the stack would exhibit a defect. Fabrication of the first stack comprises depositing a number of layers of the first semiconductor alloy interspersed with a corresponding number of layers of the second semiconductor alloy. As described below with reference to <FIG>, at least in some examples, particularly examples in which the first and second layers comprise InP, there is an increasing tendency for defects to occur in the semiconductor layers of the first stack with an increasing number of semiconductor layers.

By saying that the layers are substantially planar, it is envisaged that the layers are for example deposited on the substrate such that the upper surface of each of the layers is parallel with the surface of the substrate on which the first layer is deposited.

In some examples, the first layer is on the substrate in the sense that it is deposited in contact with the substrate. In other examples, the first layer is on the substrate in that it is supported by the substrate but not directly in contact with the substrate. For example, there are one or more intermediate layers such as materials not comprising InP, such as indium aluminium arsenide (InAlAs).

As a general comment in relation to the term "on" used herein, a layer specified as being in contact with a layer (such as an underlying layer) is in direct contact with that layer; whereas, a layer specified as being on a layer (such as an underlying layer) may be in direct contact with that layer or may be supported by the layer, with one or more intermediate layers (such as of a material not comprising InP) therebetween.

In some examples, each of the layers is deposited substantially across the whole surface area of the substrate (e.g. except for areas of the substrate that are clamped by a wafer clamp of a reactor in which the semiconductor is being manufactured).

<FIG> is scanning electron micrograph of a semiconductor structure comprising multiple quantum wells (<NUM> in total) comprising InP; in this example, the quantum wells are formed of thin layers of indium gallium arsenide phosphide (InGaAsP), which are arranged to be unstrained by matching of the lattice constants to that of the substrate. As can be seen in <FIG>, growing many consecutive semiconductor quantum wells comprising InP leads to morphological defects in the layers of the semiconductor structure, which may, as described below, manifest as apparent non-planarity (e.g. undulations) in one or more layers of semiconductor. These defects can lead to failure of the epitaxial growth or to device failures in devices incorporating the semiconductor structure, which limits the number of quantum wells that can be grown in the structure.

As shown in <FIG>, the undulations manifest in the layers of the structure as viewed in cross-section. Theses undulations may not be present at the surface of the processed structure, which may still exhibit a planar surface; this may be due, for example, to the planarizing effects of an InP layer deposited on the layers of the semiconductor structure (for example, to form an electrical contact).

The inventors have therefore appreciated that, when fabricating multiple quantum wells using InP, a problem occurs which, as far as is known, does not appear when fabricating multiple quantum well using other semiconductor material platforms. The inventors determined that, depending on the processing conditions (e.g. pressure and temperature), defects were observed when more than approximately <NUM> quantum wells were grown in a stack.

The number of layers of each of the first and second semiconductor alloys is greater than <NUM> and fewer than <NUM>, such that the total number of layers in the first stack is fewer than <NUM>.

In contrast, <FIG> is a scanning electron micrograph of a semiconductor structure comprising <NUM> quantum wells that do not include InP; in this example, the quantum wells are formed of indium aluminium gallium arsenide (InAlGaAs). As can be seen, the quantum wells shown in <FIG> are substantially planar; this is despite there being many more quantum wells that can be fabricated using InP-containing quantum wells without forming defects such as those seen in <FIG>.

To address the problem described above with reference to <FIG>, at block <NUM>, a third layer comprising a binary semiconductor material having the first lattice constant is deposited in contact with the first stack. For example, where the substrate is of InP, the third layer may also be of InP.

Then, at block <NUM>, the method <NUM> comprises depositing, at least: a fourth layer in contact with the third layer and a fifth layer in contact with the fourth layer to form a second stack of substantially planar semiconductor layers on the third layer. The fourth layer comprises a third semiconductor alloy comprising InP and the fifth layer comprises a fourth semiconductor alloy comprising InP.

As the skilled person will appreciate, various techniques may be used to deposit the layers of semiconductor material in accordance with examples described herein. Such techniques may include chemical vapour deposition techniques such as metalorganic vapour-phase epitaxy (MOVPE) or molecular beam epitaxy (MBE).

<FIG> is a diagram of a semiconductor structure <NUM>, according to examples. The semiconductor structure is fabricated according to the method described above with reference to <FIG>.

The semiconductor structure <NUM> comprises a substrate <NUM> onto which quantum wells are grown.

The semiconductor structure <NUM> includes a first stack <NUM> of quantum wells. The first stack <NUM> comprises multiple, alternating layers of a first semiconductor alloy <NUM> and a second semiconductor alloy <NUM>. A first layer, of the first semiconductor alloy <NUM>, is deposited on the substrate <NUM> and a second layer, of the second semiconductor alloy <NUM> is deposited in contact with the first layer of the first semiconductor alloy <NUM>, as described above with reference to block <NUM> of <FIG>. Multiple quantum wells are fabricated by alternating between the deposition process for depositing the first semiconductor alloy <NUM> and the deposition process for depositing the second semiconductor alloy <NUM>.

For the reasons described above, the first stack <NUM> comprises fewer than <NUM> layers. That is the first stack comprises fewer than <NUM> layers of the first semiconductor alloy <NUM> and fewer than <NUM> layers of the second semiconductor alloy <NUM>.

In some examples, each of the first and second semiconductor alloys <NUM>, <NUM> comprises a ternary semiconductor alloy or a quaternary semiconductor alloy. For example, each of the first and second semiconductor alloys <NUM>, <NUM> comprises InGaAsP, wherein the relative amounts of indium phosphide (InP), gallium arsenide (GaAs), indium arsenide (InAs), and gallium phosphide (GaP) differ between the first and second semiconductor alloys <NUM>, <NUM>. Each of the first and second semiconductor alloys <NUM>, <NUM> may be doped (e.g. p-doped or n-doped).

Although it is envisaged that each of the first and second semiconductor alloys <NUM>, <NUM> is unstrained (e.g. that the lattice constant of one layer is matched to the layers in which that layer is in contact) in some examples it is desirable to select lattice constants that introduce strain to, for example, modify the optical absorption or emission properties of the semiconductor structure <NUM>.

In some examples, the layers of each of the first and second semiconductor alloys <NUM>, <NUM> are less than <NUM> nanometers (nm).

Deposited in contact with the first stack <NUM> is a third layer <NUM>. The third layer <NUM> is a binary semiconductor having a lattice constant substantially equal to a lattice constant of the substrate <NUM>, as described above with reference to block <NUM> of <FIG>. By substantially equal it is meant that no strain is intended to be induced by the introduction of the third layer <NUM>.

The thickness of the third layer <NUM> may be in the range <NUM> to <NUM>.

Inclusion of a third semiconductor layer <NUM> having a lattice constant that is substantially equal to that of the substrate <NUM> means that the fabrication process (e.g. the method of <FIG>) may be performed without modification of the fabrication reactor or any modification of process conditions of the reactor, such as temperature or pressure, prior to fabrication of the third layer <NUM>. This may, in examples, provide for easy integration into existing fabrication processes.

Furthermore, adding only a single, thin layer of binary semiconductor material presents a negligible effect on the overall electro-optical properties of the semiconductor structure <NUM> and so performance of devices incorporating the semiconductor structure <NUM> is not adversely affected by the inclusion of the third layer <NUM>.

Deposited in contact with the third layer <NUM>, is a second stack <NUM> of quantum wells. The second stack <NUM> comprises multiple, alternating layers of a third semiconductor alloy <NUM> and a fourth semiconductor alloy <NUM>. A layer of the third semiconductor alloy <NUM>, is deposited on the third layer <NUM> and a layer of the fourth semiconductor alloy <NUM> is deposited on the layer of the third semiconductor alloy <NUM> deposited in contact with the third layer <NUM>, as described above with reference to block <NUM>. Multiple quantum wells are fabricated by alternating between the deposition process for depositing the third semiconductor alloy <NUM> and the deposition process for depositing the fourth semiconductor alloy <NUM>.

The second stack <NUM> also comprises fewer than <NUM> layers. The first stack comprises fewer than <NUM> layers of the first semiconductor alloy <NUM> and fewer than <NUM> layers of the second semiconductor alloy <NUM>.

In some examples, each of the third and fourth semiconductor alloys <NUM>, <NUM> comprises a ternary semiconductor alloy or a quaternary semiconductor alloy. For example, each of the third and fourth semiconductor alloys <NUM>, <NUM> comprises InGaAsP, wherein the relative amounts of indium phosphide (InP), gallium arsenide (GaAs), indium arsenide (InAs), and gallium phosphide (GaP) differ between the third and fourth semiconductor alloys (<NUM>,<NUM>). Each of the third and fourth semiconductor alloys <NUM>, <NUM> may be doped (e.g. p-doped or n-doped).

Although it is envisaged that each of the third and fourth semiconductor alloys <NUM>,<NUM> is unstrained (e.g. that the lattice constants of one layer is matched to the adjacent layers) in some examples it may be desirable to select lattice constants that introduce strain to, for example, modify the optical absorption or emission properties of the semiconductor structure <NUM>.

In some examples, the processes described with reference to blocks <NUM> and <NUM> of <FIG> may be repeated to further increase the number of quantum wells in the semiconductor structure <NUM>.

Although in the example shown in <FIG>, the first stack <NUM> and the second stack <NUM> have equal numbers of layer so that the third layer <NUM> is in the centre of the overall stack, in other examples, the first stack <NUM> has a different number of quantum well layers to the second stack <NUM>. That is the third layer <NUM> may be elsewhere within the semiconductor structure <NUM>, not necessarily in the exact middle of the layers of quantum wells. For example, in a semiconductor structure <NUM> comprising <NUM> quantum wells layers, the third layer <NUM> may be deposited after <NUM> quantum wells have been fabricated and <NUM> quantum wells may be fabricated above the third layer <NUM>.

<FIG> is a scanning is a scanning electron micrograph of a semiconductor structure comprising <NUM> quantum wells comprising InP; in this example, the quantum wells are formed of thin layers of indium gallium arsenide phosphide (InGaAsP), which are arranged to be unstrained by matching of the lattice constants to that of the substrate. The third layer <NUM> described above is identifiable as a bright band approximately in the centre of a stack of darker bands (which correspond to quantum well structures. As can be seen in <FIG>, introduction of the third layer <NUM>, which is a single thin layer of a material enables a significant increase in the number of InP-containing quantum well layers that can be fabricated in a semiconductor structure before defects such as those shown in <FIG> become present. Accordingly, the method described above with reference to <FIG> provides a simple and efficient way to allow the growth of thicker stacks of quantum wells containing InP.

Increasing the total thickness of a stack of repeating epitaxial quantum well layers can be useful by, for example, increasing optical confinement in the semiconductor. For example, a more efficient electro-absorption or electro-refractive modulator can be produced, because the efficiency of electro-absorption and electro-refractive modulators is related to optical confinement.

Claim 1:
A method of fabricating a semiconductor structure (<NUM>) with multiple quantum wells, the method comprising:
providing (<NUM>) a substrate (<NUM>) comprising a binary semiconductor compound having a first lattice constant;
forming, on the substrate (<NUM>), a first stack (<NUM>) of quantum wells comprising substantially planar semiconductor layers comprising greater than <NUM> and fewer than <NUM> layers (<NUM>) of a first semiconductor alloy comprising InP, and greater than <NUM> and fewer than <NUM> layers (<NUM>) of a second semiconductor alloy comprising InP, by depositing (<NUM>) at least:
a first layer on the substrate (<NUM>), the first layer of the first semiconductor alloy comprising InP, and
a second layer in contact with the first layer, the second layer of the second semiconductor alloy comprising InP;
depositing (<NUM>), in contact with the first stack (<NUM>), a third layer (<NUM>) of a binary semiconductor compound having substantially the first lattice constant of the substrate (<NUM>);
depositing (<NUM>) at least:
a fourth layer (<NUM>) on the third layer (<NUM>), the fourth layer comprising a third semiconductor alloy comprising InP, and
a fifth layer (<NUM>) in contact with the fourth layer (<NUM>), the fifth layer (<NUM>) comprising a fourth semiconductor alloy comprising InP, to form a second stack (<NUM>) of quantum wells comprising of substantially planar semiconductor layers on the third layer (<NUM>).