Patent Description:
In recent years, as semiconductor devices have become highly integrated, the size of elements inside a chip and the interval between the elements have been decreasing. In addition, the decrease in the size of elements and decrease in the interval between the elements are a matter of being able to achieve high speed of the semiconductors. The high integration and high speed may be important not only in a memory field but also in a non-memory field. In a logic device such as a Central Processing Unit (CPU), the speed of the element may be increased by reducing dimensions such as a gate line width, which may be a width of a gate electrode, to achieve high speed of the signal. It may be important to adjust the gate line width for the high integration and speed improvement.

A method for inspecting patterns formed during the manufacturing process of a semiconductor device, involving binarization, is described in patent application <CIT>.

According to a various aspects of the invention, there is provided image processing systems according to claims <NUM> and <NUM>, and image processing methods according to claims <NUM> and <NUM>. Provided is an image processing system in which reliability of line width measured on the basis of an image during process of a semiconductor device is improved.

Provided is an image processing method in which reliability of line width measured on the basis of an image during process of a semiconductor device is improved.

In accordance with an aspect of the disclosure, an image processing system includes an input interface configured to receive a first direction image corresponding to a view of a semiconductor device in a first direction, and a second direction image corresponding to a view of the semiconductor device in a second direction which intersects the first direction at a first height at which the first direction image is generated; a processor configured to perform an edge detection operation for detecting an edge based on the first direction image, and to perform an image binarization operation on the first direction image; and a learning device configured to compare a first line width obtained based on the image binarization operation, and a second line width obtained based on the second direction image through machine learning, and to learn a condition of the image binarization operation which maximizes a correlation between the first line width and the second line width.

In accordance with an aspect of the disclosure, an image processing system includes a communication interface configured to communicate with an outside of the image processing system; an input interface configured to receive a first direction image corresponding to a view of a semiconductor device in a first direction, and a second direction image corresponding to a view of the semiconductor device in a second direction intersecting the first direction at a first height at which the first direction image is generated, through the communication interface; a learning device configured to perform machine learning based on the first direction image and the second direction image; a memory configured to store a machine learning model for performing the machine learning; and a processor configured to control the communication interface, the input interface, the learning device, and the memory, wherein the processor is further configured to: perform an edge detection operation for detecting an edge based on the first direction image, perform an image binarization operation on the first direction image, compare a first line width obtained based on the image binarization operation with a second line width obtained based on the second direction image using the machine learning, and learn a condition of the image binarization operation at which a correlation between the first line width and the second line width is maximized, using the learning device.

In accordance with an aspect of the disclosure, an image processing method includes receiving a first direction image corresponding to a view of a semiconductor device in a first direction, and a second direction image corresponding to a view of the semiconductor device in a second direction intersecting the first direction at a first height at which the first direction image is generated through an input interface; performing an edge detection operation for detecting an edge based on the first direction image, using a processor; performing an image binarization operation on the first direction image, using the processor; and comparing a first line width obtained based on the image binarization operation, and a second line width obtained based on the second direction image using machine learning, and learning a condition of the image binarization operation which maximizes a correlation between the first line width and the second line width, using a learning device.

In accordance with an aspect of the disclosure, an image processing device includes a memory; and at least one processor configured to: obtain a first direction image corresponding to a view of a semiconductor device in a first direction at a first height, and a second direction image corresponding to a view of the semiconductor device in a second direction which intersects the first direction at the first height; detect an edge based on the first direction image; perform binarization on the first direction image to obtain a binarized first direction image; and compare, using machine learning, a first line width obtained based on the binarized first direction image, and a second line width obtained based on the second direction image; learn a binarization condition which maximizes a correlation between the first line width and the second line width, based on the machine learning; and store the binarization condition in the memory.

However, aspects of the present invention are not restricted to the one set forth herein. The above and other aspects of the present invention will be more apparent to one of ordinary skill in the art to which the present invention pertains by referencing the detailed description of the present invention given below.

Embodiments described herein with reference to terms such as units, modules, and blocks used in the detailed description and functional blocks shown in the drawings may be implemented by software or hardware or in the combined forms thereof. As an example, software may be machine code, firmware, embedded code, and application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a pressure sensor, an inertial sensor, a microelectromechanical system (MEMS), a passive element or combinations thereof.

As is traditional in the field, the example embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units, devices, systems modules, circuits, blocks, interfaces, or the like, are physically implemented by analog or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, or the like, and in embodiments may be driven by firmware. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits included in a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block.

<FIG> is a cross-sectional view of a semiconductor device after some steps in the process for forming the semiconductor device, showing After Clean Inspection (ACI) images as an example.

Referring to <FIG>, an image ACI_img(a) taken after some steps of a plurality of process steps for fabricating a semiconductor device is shown.

The image ACI_img(a) may be or represent, for example, an image obtained through a Scanning Electron Microscope (SEM) or an image obtained through a Transmission Electron Microscope (TEM).

The image ACI_img(a) may be, for example, an image showing a result of some of the process steps in which a pad oxide layer <NUM>, a polysilicon layer <NUM>, an anti-reflective layer (ARL) <NUM>, and a photoresist layer <NUM> are formed on a substrate <NUM>.

In embodiments, the semiconductor device in the process described herein may be formed using other process steps.

In embodiments, the image ACI_img(a) of the semiconductor device shown in <FIG> may be an ACI image, after the pad oxide layer <NUM>, the polysilicon layer <NUM>, the ARL <NUM>, and the photoresist layer <NUM> are etched.

That is, after etching the pad oxide layer <NUM>, the polysilicon layer <NUM>, the ARL <NUM>, and the photoresist layer <NUM>, a channel hole CH1a may be formed.

An image of the semiconductor device shown in <FIG> viewed at any height in a second direction y may be generated. An example of a top view of the semiconductor device shown in <FIG> is described below with reference to <FIG>.

<FIG> is a top view of the semiconductor device after some steps in the process for forming the semiconductor device, showing the ACI image as an example.

Referring to <FIG> and <FIG>, the top view ACI_img(b) of the semiconductor device of <FIG> may include a plurality of channel holes CH1a.

The top view ACI_img(b) may be or represent, for example, an image obtained through a SEM or an image obtained through a TEM.

Each channel hole CH1a may be, for example, a channel hole CH1a of <FIG>.

The top view ACI_img(b) may be an image captured after the photoresist layer <NUM> is etched, and a noise due to the photoresist layer <NUM> is not generated.

As shown in <FIG>, an edge between the plurality of channel holes CH1a may be clear.

In embodiments, an edge detection operation for the top view ACI_img(b) may be performed for line width measurement of the semiconductor device shown in <FIG>. An example diagram after the edge detection operation is performed on the top view ACI_img(b) is described below with respect to <FIG>.

<FIG> is a top view showing an image in which the edge detection operation is performed on the image of <FIG> and the edge is detected.

Referring to <FIG>, a diagram ACI_img(c) after the edge detection operation has been performed on the top view ACI_img(b) of <FIG> is shown.

The edge detection operation is performed on the basis of brightness information depending on a position of the pixels of the top view ACI_img(b) of <FIG>. Because a detailed description of the edge detection operation is provided below in connection with <FIG> and <FIG>, it is described only briefly with respect to <FIG> and <FIG>.

An edge detected on the basis of brightness information depending on the position of the pixels of the top view ACI_img(b) of <FIG> is shown in the image ACI_img(c). That is, the image ACI_img(c) may be displayed by being divided into two regions or portions, for example an edge portion and a non-edge portion.

In embodiments, the image ACI_img(c) is an image generated on the basis of the top view ACI_img(b) of <FIG>, and since the top view ACI_img(b) of <FIG> is an image which is captured after etching the photoresist layer <NUM> and in which no noise caused by the photoresist layer <NUM> is generated, the edges for defining the plurality of channels may appear clearly.

In order to check in more detail the edges that define the plurality of channels, the position at which the channel hole CH1b in <FIG> exists is explained below with respect to <FIG>.

<FIG> is an enlarged view showing an enlarged part of the image of <FIG>.

Referring to the image of <FIG>, an edge <NUM> defining the channel hole CH1b may be clearly defined. For example, the edge <NUM> defining the channel hole CH1b may have a closed curve (e.g. circular) shape.

This is because the top view ACI_img(b) of <FIG> is an image which is captured after etching the photoresist layer <NUM>, and in which noise due to the photoresist layer <NUM> is not generated.

In the examples described with respect to <FIG>, the line width, more specifically, the line width of the channel hole, may be measured with high accuracy.

However, there may be a case where the top view includes a relatively large amount of noise, for example more noise than is shown in <FIG>, and the edge of the image generated after the edge detection may not be clear. In this case, the line width, for example the line width of the channel hole, may be measured with low accuracy. In this case, it is possible to improve the measurement accuracy of the line width, more particularly, the line width of the channel holes through the image processing system or image processing method according to some embodiments.

A case where the top view includes a relatively large amount of noise and the edge of the image generated after the edge detection is not clear is described with respect to <FIG> below.

<FIG> is a cross-sectional view of a semiconductor device after some steps in the process for forming the semiconductor device, showing After Development Inspection (ADI) images as an example.

Referring to <FIG>, an image ADI_img(a) taken after some steps in the plurality of process steps for fabricating the semiconductor device is shown.

The image ADI_img(a) may be or represent, for example, an image obtained through a SEM or an image obtained through a TEM.

The image ADI_img(a) may be or represent, for example, an image showing a result of some of the process steps in which the pad oxide layer <NUM>, the polysilicon layer <NUM>, the ARL <NUM>, and the photoresist layer <NUM> are formed on the substrate <NUM>.

In embodiments, the image ADI_img(a) of the semiconductor device shown in <FIG> may be an ADI image, before etching the pad oxide layer <NUM>, the polysilicon layer <NUM>, ARL <NUM>, and the photoresist layer <NUM>. That is, the image ADI_img(a) of the semiconductor device shown in <FIG> may be an image of the semiconductor device during a process in which there is a mask formed after a photographic process on the photoresist layer <NUM>.

That is, the channel hole CH2a may be formed in the photoresist layer <NUM> but may not penetrate into the pad oxide layer <NUM>, the polysilicon layer <NUM>, and the ARL <NUM>.

The channel hole CH2a may be referred to as a channel hole created during the process of forming the channel hole CH1a, and which is formed before the pad oxide layer <NUM>, the polysilicon layer <NUM>, and the ARL <NUM> are etched.

In embodiments, the line width of the channel hole CH2a may vary according to the height in the second direction y.

For example, a line width at a first height P1 in the second direction y may have a first line width CD1a. Also, a line width at a second height P2 in the second direction y may have a second line width CD2a.

The first line width CD1a and the second line width CD2a may be different from each other. For example, the second line width CD2a may be smaller than the first line width CD1a.

For reference, the line widths (e.g., the first line width CD1a and the second line width CD2a) may be sizes measured on a plane in the first direction x and/or the third direction z. The line widths (e.g., the first line width CD1a and the second line width CD2a) <FIG> may correspond to a size (e.g. diameter or width) of the channel hole CH2a extending in the first direction x.

<FIG> is a top view of a semiconductor device after some steps in the process for forming the semiconductor device, showing the ADI image as an example.

Referring to <FIG> and <FIG>, the top view ADI_img(b) of the semiconductor device of <FIG> may include a plurality of channel holes CH2a.

The top view ADI_img(b) may be or represent, for example, an image obtained through a SEM or an image obtained through a TEM.

Each of the channel holes CH2a may be or correspond to, for example, the channel hole CH2a of <FIG>.

The top view ADI_img(b) is an image captured after development of the photoresist layer <NUM> but before the photoresist layer <NUM> is etched, and a noise due to the photoresist layer <NUM> may be generated.

That is, the edge between the plurality of channel holes CH2a may be not clear.

In embodiments, an edge detection operation for the top view ADI_img(b) may be performed for the line width measurement of the semiconductor device shown in <FIG>. A diagram after the edge detection operation is performed on the top view ACI_img(b) is described with respect to <FIG>.

<FIG> is a top view showing an image in which an edge is detected by performing the edge detection operation on the image of <FIG>.

The edge detection operation may be performed on the basis of the brightness information depending on the position of the pixel of the top view ADI_img(b) of <FIG>. Detailed description of an example of the edge detection operation is given with respect to <FIG> and <FIG> below.

<FIG> is a graph showing changes in brightness depending on a position within the image of <FIG>.

Referring to <FIG> and <FIG>, a brightness graph Graph I showing an example brightness according to pixel positions within the top view ADI_img(b) of <FIG> is shown.

Graph I is shown for convenience of explanation, and embodiments are not limited thereto. For example, Graph I may not exactly match the brightness depending on the pixel position in the top view ADI_img(b) of <FIG>.

A horizontal axis of Graph I may represent the pixel position, for example a pixel position in first direction x and third direction z, in the top view ADI_img(b) of <FIG>, and a vertical axis may represent brightness depending on the position.

For example, among the pixels of the top view ADI_img(b) of <FIG>, the brightness may appear as the brightest value at positions (x1, z1), and the brightness may appear as the lowest value at positions (x2, z2).

<FIG> is a graph Graph II showing gradient changes in brightness depending on the position in the image of <FIG>, on the basis of the graph of <FIG>.

Graph II is shown for convenience of explanation, and may not exactly match the gradient value along the horizontal axis of Graph I of <FIG>.

Referring to <FIG>, <FIG>, and <FIG>, Graph II of <FIG> is a graph obtained by taking an absolute value of the gradient value for Graph I of <FIG>.

More specifically, Graph II of <FIG> is a graph obtained by applying the absolute value to the gradient value of Graph I of <FIG> which is a graph of brightness depending on the pixel position of the top view ADI_img(b) of <FIG>.

Referring to the Graph II of <FIG>, for example, it is possible to have the greatest values at positions (x11, z11) and positions (x22, z22). The greatest values may mean that the brightness change at the position (x11, z11) and the position (x22, z22) is maximum, and may mean that this may become an edge which enters from the outside of the channel hole to the inside of the channel hole.

However, the top view ADI_img(b) of <FIG> includes a relatively large amount of noise, and there may be a case where the edge of the channel hole is not clear. Margin for defining the edge may be set for such cases. The margin value may be defined as a threshold gradient value Th(b). The threshold gradient value Th(b) may be a value defined by a user who processes the image.

For example, the threshold gradient value Th(b) may be set to perform the edge detection operation on the top view ADI_img(b) of <FIG>. In embodiments, the positions of pixels whose gradient values depending on the pixel positions of the top view ADI_img(b) of <FIG> have values greater than the threshold gradient value Th(b) may be defined as the edge of the top view ADI_img(b) of <FIG>.

That is, the pixels between positions (x3, z3) and positions (x4, z4) in Graph II of <FIG> and the pixels between positions (x5, z5) and positions (x6, z6) may be defined as the pixels at which the edge of the top view ADI_img(b) of <FIG> is located.

A diagram showing the edge detected on the basis of this operation may be an image ADI_img(c) of <FIG>.

Subsequently, referring to <FIG>, the edge <NUM> detected on the basis of the brightness information depending on the position of the pixel of the top view ADI img(b) of <FIG> is displayed in the image ADI_img(c). That is, the image ADI_img(c) may be displayed by being divided into two regions or portions, for example an edge portion and a non-edge portion.

In embodiments, the image ADI_img(c) is an image generated on the basis of the top view ACI_img(b) of <FIG>, and since the top view ADI_img(b) of <FIG> is an image which is captured before etching the photoresist layer <NUM> and in which a noise due to the photoresist layer <NUM> is generated, the edge defining the plurality of channels may not appear clearly.

In order to check in more detail the edge that defines the plurality of channels, the position at which the channel hole CH2b exists will be explained below with respect to <FIG>.

<FIG> is an enlarged view showing a part of the image ADI_img(c) of <FIG>.

Referring to the image of <FIG>, the edge <NUM> that defines the channel hole CH2b may be not clear. More specifically, it may be understood that the edge for defining the channel hole CH2b has an open (e.g. broken) curved shape.

This is because the top view ADI_img(b) of <FIG> is an image which is captured before the photoresist layer <NUM> is etched, and in which noise due to the photoresist layer <NUM> is generated.

In the examples described with respect to <FIG>, the measurement accuracy of line widths, and more particularly of line widths of the channel hole, may be low.

In other words, when the top view includes a relatively large amount of noise and the edge of the image generated after the edge detection is not clear, the measurement accuracy of the line width, more specifically the line width of the channel hole, may be lowered. In this case, it may be possible to improve the measurement accuracy of the line width, more particularly the line width of the channel holes through the image processing system or image processing method according to some embodiments.

Example configurations and operations for increasing the measurement accuracy of line widths, more specifically, line widths of channel holes, through the image processing system or the image processing method according to some embodiments are described in detail below.

<FIG> is a diagram showing an image obtained by performing an image binarization operation on the image of <FIG>.

Referring to <FIG>, the image binarization image ADI_img(d)_1 obtained by performing the image binarization operation on the image ADI_img(b) of <FIG> subjected to the edge detection operation is shown.

An example of the image binarization operation is described with respect to <FIG>.

Referring to <FIG>, <FIG> and <FIG>, a user who processes the image on the image ADI_img(b) of <FIG> may define a threshold brightness Th(a).

That is, for the image binarization operation on the image ADI_img(b) of <FIG>, by dividing the pixel positions of the image ADI_img(b) of <FIG> into a region having brightness equal to or greater than the threshold brightness Th(a) and a region having no brightness, the image ADI_img(b) of <FIG> may be divided into two regions.

For example, in Graph I, depending on the position of the pixel of the top view ADI_img(b) of <FIG>, pixels having brightness higher than the threshold brightness Th(a) and pixels not having brightness may be dividedly displayed.

That is, in Graph I, depending on the position of the pixels of the top view ADI_img(b) of <FIG>, by dividing the pixels (for example pixels located between positions (x1a, z1a) and the positions (x1b, z1b)) having brightness greater than the threshold brightness Th(a) and the pixels having no brightness, a binarized image obtained by binarizing the top view ADI_img(b) of <FIG>.

The binarized image thus generated may be expressed as in <FIG>, according to embodiments.

Referring to <FIG>, the top view ADI_img(b) of <FIG> may be binarized to binarize the region. An edge inner region, for example inner region <NUM>, and an outer region, for example outer region <NUM>, may be defined accordingly.

In embodiments, the inner region and the outer region of the top view ADI_img(b))of <FIG> is changed by adjusting the threshold brightness Th(a).

An example of this will be described with respect to <FIG>.

<FIG> is a diagram showing another image in which the image binarization operation is performed on the image of <FIG>.

Referring to <FIG>, <FIG> and <FIG>, an example will be described in which a lower threshold brightness Th(aa) is set by the user who processes the image.

In this case, an area defined as the inner region may become larger than a case where the user sets the higher threshold brightness Th(a).

That is, the inner region <NUM> in the binarized image ADI_img(d)_2 of <FIG> may be wider than the inner region <NUM> in the binarized image ADI_img(d)_1 of <FIG>.

In other words, the outer region <NUM> of the binarized image ADI_img(d)_2 of <FIG> may be narrower than the outer region <NUM> of the binarized image ADI_img(d)_1 of <FIG>.

A method for setting a threshold brightness in the image processing system or image processing method according to some embodiments will be described.

The edge <NUM> that makes up the channel hole CH2b may be generated through the edge detection operation through <FIG>. The edge generated through the edge detection operation may be made up as in the image ADI_img(c) of <FIG>.

The binarized images ADI_img(d)_1, ADI_img(d)_2 described in relation to <FIG> and <FIG> may also overlap the pixels of the image ADI_img(c) of <FIG>, and the inner region and the outer region may be dividedly displayed.

That is, as in the binarized image ADI_img(d)_1 of <FIG>, the inner region <NUM> may include fewer edge portions.

In embodiments, as in the binarized image ADI_img(d)_2 of <FIG>, the inner region <NUM> includes more edge portions than the inner region <NUM> of the binarized image ADI_img(d)_1 of <FIG>.

The threshold brightness set in Graph I of <FIG> may be adjusted on the basis of the number of edges (e.g. edge portions) included in the inner region.

More specifically, a ratio value may be defined between the number of edges included in the inner region generated through the binarized image and the number of all edges detected through the edge detection operation.

In embodiments, as in Equation <NUM> below, the ratio value may be defined as a value obtained by dividing the number of edges included in the inner region by the number of all edges in the image (e.g., the image ADI_img(c) of <FIG>) detected through the edge detection operation.

That is, the threshold brightness may be adjusted depending on the ratio value defined by the user who processes the image.

In embodiments, the image processing system or the image processing method according to some embodiments finds the threshold brightness which satisfies the ratio value, while reducing the threshold brightness from a high value to a low value to find a threshold brightness that satisfies the ratio value defined by the user, for example by approaching or equaling the ratio value defined by the user.

For example, when the user defines the ratio value to <NUM>, the ratio value after setting the threshold brightness to a very high value is measured. In embodiments, when the ratio value is <NUM>, the ratio value is measured after the threshold brightness is increased a little. In embodiments, when the ratio value is <NUM>, the threshold brightness is further increased to measure the ratio value. The threshold brightness is increased as described above, and the threshold brightness when the ratio value initially reaches <NUM> is obtained.

The image processing system or the image processing method according to some embodiments adjusts the ratio value to measure the exact line width. This will be described with respect to <FIG> below.

<FIG> is a diagram for explaining targets for which the image processing system according to some embodiments compares and learns the line widths through the machine learning.

<FIG> illustrates an embodiment in which the binarized image ADI_img(d)_2 of <FIG> may be obtained by setting the ratio value to <NUM>.

The image processing system or image processing method according to some embodiments measures the line width CD1b through the inner region <NUM> of the binarized image ADI_img(d)_2 of <FIG>.

In embodiments, the image Img(b) may be a top view image at the first height P1 of the image ADI_img(a) taken after some step processes of the multiple process steps of fabricating the semiconductor device of <FIG>.

Further, the image Img(a) may be a cross-section obtained by taking the image ADI_img(a) after some step processes of the plurality of process steps for fabricating the semiconductor device of <FIG> in the second direction y and viewing the image in the third direction z.

The images Img(a) and Img(b) may be or represent, for example, images obtained through a SEM or images obtained through a TEM.

The image processing system or the image processing method according to some embodiments measures a line width CD1a at a first height P1 of the image Img(a). Additionally, the image processing system or the image processing method according to some embodiments measures a line width CD1b of the image Img(b).

The image processing system or the image processing method according to some embodiments performs learning through machine learning, until the correlation between the line widths CD1a and CD1b is maximized.

Although the machine learning may be performed through, for example, an artificial neural network (ANN), the machine learning performed by the image processing system or the image processing system method according to some embodiments is not limited thereto.

In the image processing system or the image processing method according to some embodiments, the data which is learned and generated through the machine learning may be stored in the memory to build a database.

That is, the image processing system or the image processing method according to some embodiments may continuously learn a ratio value at which the correlation between the line width CD1a and the line width CD1b is maximized, in the process of performing the learning until the correlation between the line width CD1a and the line width CD1b is maximized, through the machine learning.

The learned data in this process may be stored in the memory, and a database may be constructed.

That is, the database constructed by the image processing system or the image processing method according to some embodiments may be helpful in improving the reliability of line width measurements during some step processes of the multiple process steps for fabricating the semiconductor device.

<FIG> is a flow chart for explaining an image processing method <NUM> according to some embodiments;.

Hereinafter, some description which may be redundant or duplicative of description given above may be briefly explained.

Referring to <FIG>, the image processing method according to some embodiments may perform an edge detection operation on the top view at some heights for a semiconductor device at operation S100.

Subsequently, the learning may be performed through the machine learning, until the correlation between a dimension corresponding to a view in a first direction and a dimension corresponding to a view in a second direction intersecting the first direction is maximized at operation S200. In embodiments, the dimension may be a line width, the view in the first direction may be a top view, the view in the second direction may be a side view, and the correlation may be expressed as a ratio between a first line width and a second line width as per operation S300.

Image processing data (e.g., learned data) generated in the image processing process described above may be stored in the memory at operation S400.

<FIG> is a diagram for describing an image processing system according to some embodiments.

Referring to <FIG>, the image processing system <NUM> according to some embodiments may be implemented as, for example, a fixed apparatus or a mobile apparatus such as a TV, a projector, a mobile phone, a smart phone, a desktop computer, a notebook, a digital broadcasting terminal, a personal digital assistants (PDA), a portable multimedia player (PMP), a navigation device, a tablet PC, a wearable device, a set-top box (STB), a digital multimedia broadcasting (DMB) receiver, a radio, a desktop computer, a robot, and a vehicle.

The image processing system <NUM> may include a communication interface <NUM>, an input interface <NUM>, a learning device <NUM>, a processor <NUM>, a memory <NUM>, and an output interface <NUM>. The configuration of the image processing system <NUM> is not limited thereto, and other configurations may be implemented.

The communication interface <NUM> may transmit and receive data to and from one or more other external electronic device (e.g., a device that processes images acquired through a SEM or a device that processes images acquired through a TEM, using wired/wireless communication technology). For example, the communication interface <NUM> may transmit and receive sensor information, user input, learned model, control signal, and the like to and from one or more other external devices.

In embodiments, the communication technology used by the communication interface <NUM> may include, but not limited to, a GSM (Global System for Mobile communication), a CDMA (Code Division Multi Access), a LTE (Long Term Evolution), a <NUM>, a WLAN (Wireless LAN), a Wi-Fi (Wireless-Fidelity), a Bluetooth, a RFID (Radio Frequency Identification), an IrDA (Infrared Data Association), a ZigBee, a NFC (Near Field Communication), and the like.

The input interface <NUM> may acquire various types of data (e.g., the image (ACI_img(b)) of <FIG>, the image (ADI_img(b)) of <FIG>, or the image (Img(a)) of <FIG>).

Various types of data acquired by the input interface <NUM> (e.g., the image (ACI_img(b)) of <FIG>, the image (ADI_img(b)) of <FIG>, or the image (Img(a)) of <FIG>) may be data that are received by the communication interface <NUM> from other electronic devices (e.g. a device that processes images acquired through a SEM or a device that processes images acquired through a TEM).

In embodiments, the input interface <NUM> may include a camera for inputting or receiving video signals, a microphone for receiving audio signals, a user input unit for inputting or receiving information from a user, and the like. Here, the camera and the microphone are treated as sensors, and signals obtained from the camera and the microphone may also be called sensing data or sensor information.

The input interface <NUM> may acquire learned data for training the machine learning model and/or input data (e.g., image ACI_img(b) of <FIG>, the image ADI_img(b) of <FIG> or the image Img(a) of <FIG>) to be used when acquiring the output using the trained machine learning model in the learning device <NUM>.

The input interface <NUM> may obtain raw input data, and in this case, the learning device <NUM> may extract one or more input features as pre-processing steps on the input data received from the input interface <NUM>.

For example, the input interface <NUM> may acquire an image during a semiconductor device and/or a semiconductor device fabricating process (e.g., a SEM image) and transmit it to the learning device <NUM>.

The learning device <NUM> may train a machine learning model made up of an artificial neural network using data (e.g., images) received from the input interface <NUM>. Here, the trained artificial neural network may be called a trained model. The trained model may be used to estimate result values for new input data rather than learned data, and the estimated values can be used as the basis for decisions for performing arbitrary operations.

In embodiments, the learning device <NUM> may perform the machine learning processing through an internal learning processor.

In embodiments, the learning device <NUM> may be implemented, using an external memory directly coupled to the memory <NUM> or a memory held in an external device.

The output interface <NUM> may generate outputs related to sight, hearing, touch, and the like.

In embodiments, the output interface <NUM> may include a display unit that outputs visual information, a speaker that outputs auditory information, a haptic module that outputs tactile information, and the like.

The memory <NUM> may store data that supports various functions of the learning device <NUM>. For example, the memory <NUM> may store input data, learned data, trained models, learned histories, and the like acquired by the input interface <NUM>.

The memory <NUM> may include, for example, a non-volatile memory such as a NAND flash memory.

The trained model may be used to infer result values for new input data rather than the learned data, and the inferred values can be used as the basis for decisions to perform arbitrary operations.

The processor <NUM> may control the overall operations of the image processing system <NUM>. The processor <NUM> may also obtain intent information about the user input and determine user requirements on the basis of the obtained intent information. Further, the processor <NUM> may control at least some of the constituent elements of the learning device <NUM> to drive application programs stored in the memory <NUM>. Further, the processor <NUM> may operate two or more of the constituent elements included in the learning device <NUM> in combination with each other to drive the application program.

For example, processor <NUM> may perform the edge detection operation and/or the image binarization operation described above.

<FIG> is a diagram for describing the memory of the image processing system according to some embodiments.

Referring to <FIG> and <FIG>, the memory <NUM> may include a model storage unit <NUM>. The model storage unit <NUM> may store a model <NUM>, which may be for example an artificial neural network, and which may be trained or has been trained through the learning device <NUM>.

Claim 1:
An image processing system (<NUM>) comprising:
an input interface (<NUM>) configured to receive a first direction image corresponding to a top view of a semiconductor device in a first direction, and a second direction image corresponding to a side view of the semiconductor device in a second direction which intersects the first direction at a first height at which the first direction image is generated;
a processor (<NUM>) configured to:
perform an edge detection operation for detecting an edge of a feature of the semiconductor device based on the first direction image;
perform an image binarization operation on the first direction image to determine pixels having a brightness greater than a threshold brightness to be an inner region, based on brightness information about pixels of the first direction image;
calculate an edge detection ratio value by dividing the number of edges included in the inner region by a total number of edges detected in the first direction image; and a learning device (<NUM>) configured to:
compare a first line width obtained based on the inner region of the image binarization operation, and a second line width obtained based on the second direction image through machine learning; and
learn the edge detection ratio value of the image binarization operation which
maximizes a correlation between the first line width and the second line width by adjusting the threshold brightness.