Patent Description:
Heretofore, fabrication approaches of power MOSFETs based on the dual trench technology includes an increased shield oxide thickness in the termination trench over the oxide thickness in the charge compensation trenches. That is, separate operations are performed to obtain the proper thickness of the oxide layers in the termination trench and the charge compensation trenches. The fabrication approach is described generally, as follows. First, a deposition of the desired shield oxide for the termination trench is performed. This is followed by the deposition of doped poly-silicon to form the electrode in the termination trench. Second, the oxide is removed from the charge compensation trenches. Third, deposition of the desired shield oxide for the charge compensation trenches is performed. This is followed by the deposition of doped poly-silicon to form the electrodes of the charge compensation trenches.

A particular problem with traditional fabrication techniques for dual trench technology is the susceptibility of cracks in one or more of the charge compensation trenches. In particular, during the deposition of the first shield oxide to the required thickness for the termination trench, the charge compensation trenches are completely filled with oxide. This is due to their smaller dimensions. For illustration, PRIOR ART <FIG> shows a device <NUM> having a dual trench technology, including charge compensation trenches 110A and 110B, and a termination trench <NUM>. A crack <NUM> is shown formed within charge compensation trench 110A.

Crack <NUM> is formed from further processing at elevated temperature while the charge compensation trenches are still filled with oxide. In particular, after poly-silicon is deposited into the termination trench and etched back below the semiconductor mesa, an oxide trench refill is performed to protect the poly-silicon in the termination trench. This oxide refill is performed at high temperature. Due to the mismatch in thermal expansion coefficient between silicon and oxide, the oxide filled charge compensation trenches are susceptible to cracking at the higher temperature during the oxide refill due to mechanical stresses. On the other hand, the poly-silicon filled termination trench is less susceptible to cracking. This is more pronounced for devices having deeper trenches.

Additionally, a further processing risk involves a nitride hard mask used to shield the termination trench during the removal of the oxide from the charge compensation trenches. The shielding ability of the nitride hard mask is negatively impacted due to any variation from design in prior process operations. For instance, the oxide within the trench may be etched away due to insufficient protection by the nitride hard mask. <CIT> discloses a semiconductor device and fabrication method, in which the device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device. <CIT> discloses a method for forming a core trench and a termination trench in a substrate. The termination trench is wider than the core trench. In addition, a first oxide can be deposited that fills the core trench and lines the sidewalls and bottom of the termination trench. A first polysilicon is deposited into the termination trench. A second oxide is deposited above the first polysilicon. A mask is deposited above the second oxide and the termination trench. The first oxide is removed from the core trench. A third oxide is deposited that lines the sidewalls and bottom of the core trench. The first oxide within the termination trench is thicker than the third oxide within the core trench. <CIT> discloses a method including the operations of covering a surface of a semiconductor body with a mask body; removing portions of said mask body to define openings extending to said semiconductor body; removing a portion of said semiconductor body from bottoms of said openings in said mask body to define a plurality of gate trenches and a termination trench disposed around said gate trenches, said trenches being spaced from one another by mesas; removing said mask body; oxidizing the sidewalls of said gate trenches; depositing gate electrode material; etching back said gate electrode material to leave gate electrodes in said trenches; implanting channel dopants adjacent said gate trenches after said gate trenches are defined; forming a source mask; implanting source dopants through said source mask; activating said source dopants and said channel dopants to form a base region and source regions; depositing a low density oxide over said semiconductor body; depositing a contact mask; etching said low density oxide through said contact mask; depositing a metal layer atop said semiconductor body; forming a front metal mask atop said metal layer; and etching said metal layer to form at least a source contact, and a gate runner. <CIT> describes a trench Schottky diode and a manufacturing method thereof. A plurality of trenches are formed in A semiconductor substrate. A plurality of doped regions are formed in the semiconductor substrate and under some of the trenches. A gate oxide layer is formed on a surface of the semiconductor substrate and the surfaces of the trenches. A polysilicon structure is formed on the gate oxide layer. Then, the polysilicon structure is etched, so that the gate oxide layer within the trenches is covered by the polysilicon structure. Then, a mask layer is formed to cover the polysilicon structure within a part of the trenches and a part of the gate oxide layer, and the semiconductor substrate uncovered by the mask layer is exposed. Afterwards, a metal sputtering layer is formed to cover a part of the surface of the semiconductor substrate. <CIT> relates to a vertical power trench MOSFET semiconductor device that comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device. <CIT> relates to method for fabricating a drift zone of a vertical semiconductor component and to a vertical semiconductor component having the following features: a semiconductor body having a first side and a second side, a drift zone of a first conduction type which is arranged in the region between the first and the second sides and is formed for the purpose of taking up a reverse voltage, a field electrode arrangement arranged in the drift zone and having at least one electrically conducted field electrode arranged in a manner insulated from the semiconductor body, an electrical potential of the at least one field electrode varying in the vertical direction of the semiconductor body at least when a reverse voltage is applied.

In embodiments of the present invention, a method for fabricating a dual trench structure according to appended claim <NUM> is described. The method includes providing a wafer comprising a semiconductor layer including a top surface. The method further includes providing a plurality of charge compensation trenches open to the top surface and formed within the semiconductor layer. The plurality of charge compensation trenches comprises a plurality of charge compensation trench surfaces. The method also includes providing a termination trench open to the top surface and formed within the semiconductor layer. The termination trench comprises a termination trench surface. The method includes forming a first shield oxide layer of a first predetermined thickness on the plurality of charge compensation surfaces and the termination trench surface. The first predetermined thickness of the first shield oxide layer is sufficient to allow formation of voids through centers of the plurality of charge compensation trenches.

These and other objects and advantages of the various embodiments of the present disclosure will be recognized by those of ordinary skill in the art after reading the following detailed description of the embodiments that are illustrated in the various drawing figures.

The accompanying drawings, which are incorporated in and form a part of this specification and in which like numerals depict like elements, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale. The same reference numbers in different figures denote the same or similar elements, and as such perform similar functionality. Also, descriptions and details of well-known steps and elements are omitted for simplicity of the description.

Reference will now be made in detail to the various embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While described in conjunction with these embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.

In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as "forming," "performing," "providing," "extending," "depositing," "etching" or the like, refer to actions and processes of semiconductor device fabrication.

As used herein , the letter "n" refers to an n-type dopant and the letter "p" refers to a p-type dopant. A plus sign "+" or a minus sign "-" is used to represent, respectively, a relatively high or relatively low concentration of the dopant.

Also, the term "channel" is used herein in the accepted manner. That is, current moves within a MOSFET in a channel, from a source connection to the drain connection. Embodiments of the present invention provide for a dual trench structure suitable for use in the fabrication of either n-channel or p-channel devices. As such, features described herein can be utilized in n-channel devices or p-channel devices.

Accordingly, embodiments of the present invention disclose dual trench structures configured for use in fabricating power MOSFETs, wherein the dual trench structure is not susceptible to cracking within charge compensation trenches during fabrication because there is not a complete oxide fill of those trenches. Further, a nitride deposition and patterning can be avoided during fabrication because the etching of oxide in one or more trenches is avoided, and instead replaced with poly-silicon etching in one or more trenches which uses a photo-resist mask and not the use of a hard nitride mask. Further, selectivity of the poly-silicon etching is high since it does not attack the underlying oxide layer. This selectivity improves process stability because the configuration of the oxide lined trench sidewalls and trench bottom remain the same, even after over-etching.

First described is a process for fabricating a device according to embodiments of the invention. Although specific steps are disclosed, such steps are only examples. That is, embodiments according to the present invention are well suited to performing other steps or variations of the recited steps. Only certain portions of the structures are provided in the figures, as well as the various layers that form those structures, may be shown in there figures. Furthermore, for clarity in the drawings, regions and elements of device structures may be represented with boundaries having generally straight line edges, and angular corners. However, it is understood that due to various fabrication techniques (e.g., diffusion and activation of dopants), these edges may not be straight lines or precise angles. Moreover, other fabrication processes and steps may be performed along with the processes and steps discussed herein; that is, there may be a number of process steps before, in between and/or after the steps shown and described herein. Importantly, embodiments in accordance with the present invention can be implemented in conjunction with these other (perhaps conventional) structures, processes, and steps without significantly perturbing them. Generally speaking, embodiments in accordance with the present invention can replace portions of a conventional device or process without significantly affecting peripheral structures, processes and steps.

<FIG> is a flow diagram <NUM> illustrating a method for fabricating a dual trench structure configured for use in fabricating power MOSFETs that does not include a complete oxide fill of the charge compensation trenches, in accordance with one embodiment of the present disclosure. Because the process flow for the dual trench structure avoids a complete oxide fill of the charge compensation trenches, these trenches are less or not susceptible to cracking during high temperature process steps. <FIG> illustrate various fabricating stages of a dual trench structure, as described in flow diagram <NUM>. Specifically, <FIG> are cross-sectional views showing elements of a dual trench structure configured for use in fabricating power MOSFETs, wherein the dual trench structure is not susceptible to cracking within the charge compensation trenches because there is no complete oxide fill of the charge compensation trenches during fabrication, according to embodiments of the present invention.

Turning now to operation <NUM> and <FIG>, the method includes providing a wafer comprising a semiconductor layer including a top surface <NUM>. Specifically, the semiconductor layer comprises an epitaxial layer <NUM> that is grown over a substrate <NUM>. The epitaxial layer <NUM> may comprise a p-type grown over a heavily doped (p++) substrate <NUM> suitable for fabricating p-channel devices, in one embodiment. In another embodiment, the epitaxial layer <NUM> may comprise an n-type grown over a heavily doped (n++) substrate <NUM> suitable for fabricating n-channel devices. Additional p-type or n-type implants (not shown) can then be carried out to selectively enhance or invert the epitaxial doping.

At operation <NUM>, the method includes providing a plurality of charge compensation trenches <NUM> open to the top surface <NUM> and formed within the semiconductor layer (e.g., epitaxial layer <NUM>). The plurality of charge compensation trenches <NUM> comprises a plurality of charge compensation trench surfaces, wherein the surfaces are associated with trench sidewalls <NUM> and trench bottoms <NUM>. For instance, a surface of a charge compensation trench <NUM> includes trench sidewalls <NUM> and a trench bottom <NUM>.

At operation <NUM>, the method includes providing a termination trench <NUM> open to the top surface <NUM> and formed within the semiconductor layer (e.g., epitaxial layer <NUM>). The termination trench <NUM> comprises a termination trench surface, wherein the surface is associated with trench sidewalls <NUM> and a trench bottom <NUM>.

Formation of the deep trenches may be implemented using various well known techniques to fabricate the two differently shaped trenches described above. In particular, the charge compensation trenches <NUM> are less deep and less wide than the termination trench <NUM>. In general, trench fabrication includes a photolithographic process to selectively deposit photoresist (not shown) in areas outside a region where trenches are to be formed. Additional hard masking may also be performed to isolate one or more trenches. An etching process is performed to etch away the epitaxial layer <NUM> where the charge compensation trenches <NUM> and the termination trench are formed. In one embodiment, the charge compensation trenches <NUM> and the termination trench <NUM> are fabricated using a single etching of the epitaxial layer <NUM>. Thereafter, a resist strip and polymer removal may be performed.

Turning now to operation <NUM> and still with reference to <FIG>, the method includes forming a first shield oxide layer <NUM> of a first predetermined thickness on the plurality of charge compensation surfaces and the termination trench surface. The first shield oxide layer <NUM> overlays exposed surfaces of the semiconductor wafer. For instance, a plasma or TEOS (tetraethyl orthosilicate) oxide is deposited (e.g., <NUM> - <NUM> at <NUM> - <NUM>, with or without annealing) to complete the first shield oxide layer <NUM>.

In particular, <FIG> shows an enlarged partial cross-sectional view of a dual trench structure 300A at a stage in fabrication that includes the shield oxide layer <NUM> deposited over an oxidation layer <NUM>, which is a thin layer of oxide (e.g., silicon dioxide). That is, after trench formation, a thermal oxidation process is performed on the wafer. For instance, an oxidizing agent is diffused into exposed surfaces of the wafer at high temperature, and a subsequent oxidation reaction occurs to create oxidation layer <NUM>. For example, oxidation layer <NUM> may have a thickness of <NUM> -<NUM> Angstroms.

The predetermined thickness <NUM> of the first shield oxide layer <NUM> is configured to allow formation of voids <NUM> through the centers of the plurality of compensation trenches <NUM>. In addition, the predetermined thickness <NUM> of the shield oxide layer <NUM> is configured to allow for the later formation of electrodes in the voids <NUM> of the charge compensation trenches <NUM>.

Shield oxide formation in the charge compensation trenches is complete, since the first predetermined thickness <NUM> is configured for the charge compensation trenches <NUM>. That is, no further deposition or etching of oxide is needed in the formation of the charge compensation trenches <NUM>. Further, as is shown in <FIG>, the first shield oxide layer <NUM> is also deposited within the termination trench <NUM>. Because the shield oxide layer protecting the termination trench <NUM> is thicker than the first predetermined thickness <NUM> sufficient for the charge compensation trench <NUM>, additional oxide deposition and/or etching steps are necessary to complete the shield oxide formation in the termination trench <NUM>, as will be described below. Since the oxide formation is complete in the charge compensation trenches <NUM> and because the oxide does not completely fill the void <NUM> in the charge compensation trenches <NUM>, subsequent oxide formation in the termination trench <NUM> will not adversely affect the formation in the charge compensation trenches <NUM>, and as such, embodiments of the present invention are not susceptible to cracking in the charge compensation trenches.

<FIG> shows an enlarged partial cross-sectional view of a dual trench structure 300B after further steps in fabrication. In particular, the method for fabricating the dual trench structure outlined in <FIG> continues and includes filling the plurality of compensation trenches and the termination trench with doped amorphous or poly-silicon or a combination of both. At this stage, the poly-silicon covers the first shield oxide layer <NUM>, such that the thickness of the poly-silicon overfills the charge compensation trenches <NUM> and the termination trench <NUM>. The poly-silicon is planarized with selective chemical-mechanical planarization/polishing techniques, etch-back techniques, combinations thereof, or the like. For instance, during the planarization process, the overfilled poly-silicon is selectively planarized down to the first shield oxide layer <NUM>. Subsequently, the poly-silicon is etched back down below the top surface <NUM> of the semiconductor or epitaxial layer <NUM>. That is, a recess etching is performed of the poly-silicon to below the top surface <NUM> (e.g., a few nanometers below the top surface <NUM>). As a result, the remaining poly-silicon <NUM> is located in the charge compensation trenches <NUM> and the termination trench, and is etched back from the top surface <NUM>.

The poly-silicon <NUM> in the charge compensation trenches <NUM> form the electrodes. Also, the first shield oxide layer <NUM> is of sufficient thickness to insulate the charge compensation trenches <NUM> for the voltage applied to the electrode in the trench <NUM>. However, the thickness of the oxide layer <NUM> in the termination trench <NUM> is insufficient for the voltage applied in trench <NUM>. Subsequent steps include the additional deposition of shield oxide in the termination trench <NUM> and poly-silicon fill in isolation, as is further described below.

<FIG> shows an enlarged partial cross-sectional view of a dual trench structure 300C after further steps in fabrication. In particular, the method for fabricating the dual trench structure outlined in <FIG> continues and includes performing a photolithographic process to selectively deposit photoresist in all areas outside of the termination trench <NUM>. In this manner, the photoresist <NUM> isolates, in part, the plurality of charge compensation trenches <NUM>. Put another way, the photoresist <NUM> exposes the termination trench <NUM> to further etching and deposition processes, but shields the plurality of charge compensation trenches <NUM> from the same etching and deposition processes.

<FIG> shows an enlarged partial cross-sectional view of a dual trench structure 300D after further steps in fabrication. In particular, the method for fabricating the dual trench structure outlined in <FIG> continues and includes etching poly-silicon from the termination trench <NUM> to expose the first shield oxide layer <NUM>. For example, a dry chemical etch is performed to remove the poly-silicon <NUM>, which leaves a void <NUM>.

<FIG> shows an enlarged partial cross-sectional view of the dual trench structure 300E after further steps in fabrication. In particular, the method for fabricating the dual trench structure outlined in <FIG> continues and includes stripping the photoresist layer <NUM>. In addition, the method includes performing a wet-chemical (e.g., diluted hydrofluoric acid, buffered oxide etch [BOE], etc.) clean treatment in a sink or spin rinse tool. That is, the oxide surface in the termination trench is cleaned to prepare for additional oxide formation. As a result, a well-controlled conditioning of the first shield oxide layer <NUM> is performed.

After cleaning the wafer, the method includes depositing an additional shield oxide layer over the cleaned first shield oxide <NUM> in the termination trench <NUM>. That is, the method includes forming a second shield oxide layer <NUM> over the first shield oxide layer <NUM> that is exposed in the termination trench <NUM>. For example, a TEOS oxide is deposited at high temperature to a certain thickness, with or without annealing. The first and second shield oxide layers combined (<NUM> and <NUM>) formed in the termination trench <NUM> comprise a second predetermined thickness <NUM> - that is sufficient to allow formation of a void <NUM> in the termination trench <NUM>. As a result, as is shown in <FIG>, the shield oxide of the first predetermined thickness <NUM> in the plurality of charge compensation trenches is less thick than the shield oxide of the second predetermined thickness <NUM> in the termination trench. In this manner, the thicker shield oxide (<NUM> and <NUM>) can handle the higher voltage applied to the later formed electrode associated with the termination trench <NUM>, when compared to voltages applied to the charge compensation trenches <NUM>.

As is shown in <FIG>, the second shield oxide layer <NUM> is also deposited over the polysilicon <NUM> in the charge compensation trenches <NUM>.

<FIG> shows an enlarged partial cross-sectional view of the dual trench structure 300F after further steps in fabrication. In particular, the method for fabricating the dual trench structure outlined in <FIG> continues and includes filling the termination trench <NUM> with doped amorphous or poly-silicon or a combination of both <NUM>. At this point, the poly-silicon covers (not shown) the second shield oxide layer <NUM> located in the termination trench <NUM>, mesa regions <NUM>, the plurality of charge compensation trenches <NUM>. That is, the poly-silicon <NUM> overfills the termination trench <NUM>. As such, the poly-silicon is planarized with selective chemical-mechanical planarization/polishing techniques, etch-back techniques, combinations thereof, or the like. For instance, during the planarization process, the poly-silicon is planarized down (not shown) to the surface of the second shield oxide layer <NUM>. Subsequently, the poly-silicon is etched back down below (e.g., a few nanometers below) the top surface <NUM> of the semiconductor or epitaxial layer <NUM>. As a result, the remaining poly-silicon <NUM> is located in the termination trench <NUM>, etched back from the top surface <NUM>, and configured for electrode formation.

As shown in <FIG>, the method outlined in <FIG> continues to include performing a shield oxide layer refill of the termination trench <NUM>. That is, a trench fill is performed to deposit shield oxide <NUM> over the poly-silicon <NUM> exposed in the termination trench <NUM>. The shield oxide <NUM> also is deposited over the second shield oxide layer <NUM> located over the mesas <NUM> separating the trenches <NUM> and <NUM>, and the charge compensation trenches <NUM> and termination trench <NUM>. For example, a TEOS oxide is deposited at high temperature to a certain thickness, with or without annealing.

<FIG> shows an enlarged partial cross-sectional view of the dual trench structure <NUM> after further steps in fabrication. In particular, the method for fabricating the dual trench structure outlined in <FIG> continues and includes performing planarization with selective chemical-mechanical planarization/polishing techniques, etch-back techniques, combinations thereof, or the like to remove shield oxide down to approximately the top surface <NUM> of the semiconductor/epitaxial layer <NUM>. In this manner, shield oxide <NUM> remains over the poly-silicon <NUM> in the charge compensation trenches <NUM>, as well as over the poly-silicon <NUM> in the termination trench <NUM>.

<FIG> is a flow diagram <NUM> illustrating a method for fabricating a dual trench structure configured for use in fabricating power MOSFETs that is not susceptible to cracking within the charge compensation trenches during fabrication, in accordance with one embodiment of the present disclosure. Flow diagram <NUM> illustrates a process flow for manufacturing a dual trench structure without a complete oxide filling of the charge compensation trenches, and without needing a nitride hard- mask. As such, the dual trench structure fabricated using the fabrication process outlined in flow diagram <NUM> is not susceptible to cracking in the charge compensation trenches, especially during higher temperature process steps.

At <NUM>, the method includes simultaneously forming a plurality of charge compensation trenches and a termination trench in a semiconductor layer. The plurality of charge compensation trenches is open to a top surface of the semiconductor layer (e.g., epitaxial layer), and wherein the termination trench is open to the top surface.

At <NUM>, the method optionally includes oxidizing exposed surfaces of the plurality charge compensation trenches and the termination trench. That is, after trench formation, a thermal oxidation process is performed on the wafer.

At <NUM>, the method includes depositing a first shield oxide layer of a first predetermined thickness on the exposed surfaces of the plurality of charge compensation and the termination trench. If oxidization was performed, the first shield oxide layer is deposited on exposed surfaces of the oxidized layer. The first predetermined thickness of the first shield oxide layer is configured for formation of electrodes in the charge compensation trenches, and to provide insulation to the wafer from the voltages applied to those electrodes. That is, the first predetermined thickness is configured to allow formation of voids through centers of the plurality of compensation trenches, wherein electrodes are formed in those voids.

The first shield oxide layer also covers the surface of the termination trench. However, the thickness of the shield oxide is insufficient to insulate the termination trench because of higher voltages applied to that trench.

At this point, the method includes depositing doped poly-silicon over the first shield oxide layer in the plurality of compensation trenches and the termination trench. The poly-silicon in the charge compensation trenches is used to form the electrodes. As such, the method further includes a planarization step (e.g., CMP) to remove poly-silicon until reaching the first shield oxide layer covering the top surface of the semiconductor layer, and a recess step to etch back the polysilicon below a top surface.

To remove the poly-silicon from the termination trench, a photoresist mask is structured to isolate the plurality of charge compensation trenches. By forming the oxide layering the charge compensation trenches first, this avoids the use of a nitride hard mask for protecting the termination trench when preparing the plurality of compensation trenches, as was previously performed in traditional techniques.

This is followed by a dry-etch step to etch the poly-silicon from the termination trench. The etching step exposes the first shield oxide layer deposited in the termination trench. In the current process, even with over-etching, the oxide thickness of the first shield oxide layer is preserved at sidewalls and a bottom of the termination trench. That is, the etching process used to remove poly-silicon does not attack the oxide inside the termination trench once the poly-silicon is etched away. The selectivity of the etching process is high, and therefore the oxide thickness on the trench sidewalls and trench bottom remain the same even with high over-etching time. This retention of oxide thickness during etching improves overall process stability.

The method also includes stripping the photoresist layer. The exposed surfaces of the first shield oxide layer is conditioned. For example, a wet-chemical (e.g., diluted hydrofluoric acid, buffered oxide etch [BOE], etc.) clean treatment is performed using a sink or spin rinse tool.

After conditioning, the thickness of the oxide layer in the termination trench is increased to the appropriate thickness through another oxide deposition step. For instance, the method includes depositing a second shield oxide layer over exposed surfaces of the first shield oxide layer to increase oxide thickness in the termination trench.

As such, the first and second shield oxide layers comprise a second predetermined thickness configured for formation of electrodes in the termination trench. Specifically, the poly-silicon electrode can be formed by depositing a doped poly-silicon layer followed by CMP and a recess step to etch back the poly-silicon below the top surface of the semiconductor layer.

Finally, the planarization of the surface of the wafer is achieved by applying an oxide CMP step. In that manner, the wafer is planarized down to the top surface of the semiconductor layer, wherein the charge compensation trench is lined with oxide of a first predetermined thickness and filled with poly-silicon that form the electrodes, and wherein the termination trench is lined with oxide of a second predetermined thickness and filled with poly-silicon that form its electrode. The first predetermined thickness is less than the second predetermined thickness. Additional steps may be performed to fabricate MOSFET devices in conjunction with the dual trench structure.

Thus, according to embodiments of the present disclosure, an dual trench structure and method for fabricating the same are described, wherein the process flow fabricates dual trench structures that are not susceptible to cracking in the charge compensation trenches in subsequent high temperature steps.

While the foregoing disclosure sets forth various embodiments using specific block diagrams, flowcharts, and examples, each block diagram component, flowchart step, operation, and/or component described and/or illustrated herein may be implemented, individually and/or collectively, using a wide range of hardware, software, or firmware (or any combination thereof) configurations. In addition, any disclosure of components contained within other components should be considered as examples in that many architectural variants can be implemented to achieve the same functionality.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as may be suited to the particular use contemplated.

Claim 1:
A method (<NUM>) for fabricating a dual trench structure (<NUM>), the method comprising:
providing (<NUM>) a wafer comprising a semiconductor layer (<NUM>) including a top surface (<NUM>);
providing (<NUM>) a plurality of charge compensation trenches (<NUM>) open to said top surface and formed within said semiconductor layer, wherein said plurality of charge compensation trenches comprises a plurality of charge compensation trench surfaces (<NUM>, <NUM>);
providing (<NUM>) a termination trench (<NUM>) open to said top surface and formed within said semiconductor layer, wherein said termination trench comprises a termination trench surface (<NUM>, <NUM>);
forming (<NUM>) a first shield oxide layer (<NUM>) of a first predetermined thickness (<NUM>) on said plurality of charge compensation trench surfaces and said termination trench surface;
forming a plurality of voids (<NUM>) through centers of said plurality of charge compensation trenches during formation of said first shield oxide layer, wherein said first predetermined thickness of said first shield oxide layer is sufficient to allow formation of said voids;
filling said plurality of charge compensation trenches (<NUM>) and said termination trench (<NUM>) with poly-silicon (<NUM>) covering said first shield oxide layer (<NUM>), wherein the poly-silicon filling said plurality of charge compensation trenches form electrodes and wherein the poly-silicon filing said termination trench forms sacrificial material;
performing recess etch of said poly-silicon to below said top surface (<NUM>) of said semiconductor layer (<NUM>);
forming a photoresist layer (<NUM>) isolating said plurality of charge compensation trenches (<NUM>); and
etching poly-silicon from said termination trench (<NUM>) to expose said first shield oxide layer (<NUM>) of said first predetermined thickness (<NUM>).