Patent Description:
Increased performance in and yield of circuit devices on a substrate (e.g., integrated circuit (IC) transistors, resistors, capacitors, etc. on a semiconductor (e.g., silicon) substrate) is typically a major factor considered during design, manufacture, and operation of those devices. For example, during design and manufacture or forming of fin based metal oxide semiconductor (MOS) transistor devices, such as those used in a complementary metal oxide semiconductor (CMOS), it is often desired to increase movement of electrons (carriers) in N- type MOS device (n-MOS) channels and to increase movement of positive charged holes (carriers) in P-type MOS device (p-MOS) channels.

A FinFET may be a transistor built around a thin strip of semiconductor material (generally referred to as the fin). The transistor includes the standard field effect transistor (FET) nodes, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer sides of the fin beneath the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a trigate FinFET. Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). There are a number of non-trivial issues associated with fabricating such fin-based transistors.

<CIT> relates to various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins).

Carrier movement in a fin-based transistor can be increased by a strain in the conductive channel caused at an interface between two materials having a different sized crystal lattice structures. However, performance and movement of the carriers may be slowed by physical size limitations of the fins; as well as lattice mismatches and lattice defects generated at interfaces in a between layers of materials used to form the fins or channels.

In the context of Ge containing cladding layers on a Si fin for fabrication of SiGe alloy and Ge channel transistors it is desirable to minimize the width of the silicon fin layer, in some cases, as much as possible. The Si fin is a template (e.g., core) for the cladding layer to be deposited upon or grown from (e.g., epitaxially). In some cases, for improved performance properties of the total fin width (Si core plus any cladding layers), the width of the total fin can be less than <NUM> wide, or <NUM> wide. In an embodiment, just the act of reducing the fin width is enough to provide significant improvement in electrostatic properties of the MOS transistor in terms of reduced threshold gate voltage and lower off-state current leakage. In this embodiment, no additional cladding layers are necessary.

In addition, the quality of the cladding layers (e.g., the crystaline structure and therefore performance of the channel cladding layer) may depend on the quality of the Si fin (e.g., its crystaline structure, such as at its top surface and sidewalls) that is used as the starting template for growth. In the context of Ge containing cladding layers on a Silicon fin for fabrication of SiGe alloy and Ge channel fin based transistors it is desirable to avoid or reduce high energy ion bombardment, oxidation and etch residues on Silicon fin surfaces since these are damaging to the quality of subsequently clad or deposited layers. For example, such bombardment, oxidation and etch residues may create defects in or additional material upon the crystaline structure of the silicon fin top and sidewall surfaces upon which the subsequently clad or deposited layers are grown. Consequently, the crystaline structure of the subsequently clad or deposited layer growth will include defects due to the defects in or additional material upon the crystaline structure of the silicon fin top and sidewall surfaces. Thus, avoiding or reducing such bombardment, oxidation and residues increases transistor performance.

To minimize the width of the silicon fin layer and increase the quality of the cladding layers, embodiments herein form fin transistors (e.g., tri gate) by epitaxially growing a second crystal material on surfaces of etched, thinned first crystal material fins. The etched, thinned fins are formed by first forming wider single crystal fins having a first width (e.g., using a first etch of single crystal material), that will be subsequently etched (e.g., using a second etch) to form narrower single crystal fins having the same crystal lattice, undamaged top and sidewalls for epitaxially growing a second single crystal material. In some cases the wider single crystal fins are fabricated in industry standard ways via lithographic methods and dry etch. Subsequently, a PMOS device is formed by cladding a narrower Si fin with a SiGe channel material.

More specifically, according to embodiments herein, wide Si fins are fabricated in industry standard ways via lithographic methods and dry etch (e.g., a first etch). Then, a second etch is performed using in-situ methods to reducing the fin width (e.g., to form narrower fins) while avoiding excessive damage to the fin (e.g., top and sidewall surfaces of the etched, narrower fins). This may be accomplished while avoiding additional damage to the fin surfaces and maintaining a clean surfaces that are amenable to high quality epitaxial deposition (e.g., of a cladding channel layer on the top and sidewall surfaces). For example, in some cases, the second etch is be a fin-width trim etch that is outside of (e.g., does not include) the epitaxial deposition toolset (ex-situ) that typically relies on dry etching which can involve high energy ion bombardment, oxidation and etch residues that are all damaging to the quality of subsequently deposited layers.

According to some embodiments, a second etch can be performed to further reduce the width of a Si fin that has already been formed, in order to (<NUM>) form a narrow width fin; and (<NUM>) provide fin top surface and sidewalls without ion damage, oxidation and residues. In some cases, ion bombardment is the physical process that occurs in the process equipment. Ion damage is the result on the wafer and it means that atoms are knocked out of place meaning that the regular periodic array of atoms in a crystal is disrupted or damaged. This second etch is performed on existing Si fins to further narrow the portion of the fins exuded above the STI plane. This second etch may be a simultaneous isotropic etching of the top surfaces and the sidewalls of the electronic device fins that does not include high energy ion bombardment, oxidation or etch residues. It forms single crystal (e.g., same crystal lattice as etched surfaces) etched top surfaces and etched sidewalls of electronic device etched fins by etching to remove a thickness of between a <NUM> and <NUM> of the top surfaces and the sidewalls of the electronic device fins. It includes etching the top surfaces and the sidewalls of the electronic device fins using thermal processing that avoids or does not include energetic ions, oxidation and does not create etch residue that could damage the quality of subsequent deposited layers. It may etch the top surfaces and the sidewalls of the electronic device fins while maintaining the single crystal structure of the top and sidewall surfaces of the device fins. This thermal processing includes HCl or CL<NUM> containing gas streams in a hydrogen environment at temperatures below <NUM> or <NUM> respectively.

According to the invention, in order to perform in-situ growth of the cladding layer after etching the top surfaces and the sidewalls of the electronic device fins, a second single crystal material is deposited (e.g., grown or formed) on the top and sidewall surfaces of the etched fins, without air break of the processing chamber. The second single crystal material has a lattice spacing that is larger than a lattice spacing of the fin single crystal material.

<FIG> is a schematic cross section view of a portion of a semiconductor substrate base after forming hardmask patterns on first top surface areas where electronic device fins are desired. <FIG> shows semiconductor substrate or base <NUM> of material <NUM> having top surface <NUM>. Substrate <NUM> may include, be formed from, deposited with, or grown from silicon, polycrystalline silicon, single crystal silicon, or various other suitable technologies for forming a silicon base or substrate, such as a silicon single crystal wafer. For example, according to embodiments, substrate <NUM> may be SOI, bulk Si, float zone or epi Si formed by growing a single crystal silicon substrate base material having a thickness of between <NUM> Angstroms and <NUM> Angstroms of pure silicon. Alternately, substrate <NUM> may be formed by sufficient chemical vapor deposition (CVD) of various appropriate silicon or silicon alloy materials <NUM> to form a layer of material having a thickness between one and three micrometers in thickness, such as by CVD to form a thickness of two micrometers in thickness. It is also considered that substrate <NUM> may be a relaxed, non-relaxed, graded, and/or non-graded silicon alloy material <NUM>. Material <NUM> may be a relaxed material (e.g., have a non-strained lattice) at surface <NUM>. Material <NUM> may be a single crystal silicon material. Substrate <NUM> may be made of silicon and have top surface <NUM> with a (<NUM>) crystal oriented material (e.g., according to Miller Index). Substrate <NUM> may be a "miscut" substrate.

<FIG> shows patterns or masks <NUM> formed on areas <NUM> of top surface <NUM>. Masks <NUM> may be hardmask patterns formed on first top surface areas or locations <NUM> of a single crystal (e.g., Si) substrate where top surfaces of the electronic device fins are desired. In some cases, mask <NUM> is formed by or of photoresist alone, or a photoresist/oxide combination; or a photoresist/nitride combination. Mask <NUM> may have sidewalls <NUM> and <NUM> above surface <NUM>. Sidewalls <NUM> and <NUM> may be planar surfaces perpendicular to surface <NUM>.

<FIG> areas <NUM> of top surface <NUM> between masks <NUM>. Areas <NUM> may be second top surface areas or locations of top surfaces a single crystal (e.g., Si) substrate between or excluding areas <NUM> where electronic device fins are desired. Areas <NUM> may be second top surface areas of the substrate between the first top surface areas <NUM> or between hardmasks <NUM> where trenches are desired or to be formed substrate <NUM> (e.g., in surface <NUM>) in between the first top surface areas <NUM>. The trenches may be formed below the second top surface areas <NUM>, such as between locations or areas <NUM> of the substrate where top surfaces of the electronic device fins are desired.

Areas <NUM> may have width W1, and length L1 into the page (not shown). In some cases, Areas <NUM> and masks <NUM> may have width W1 and Length L1 (not shown but directed into the page of <FIG>). Areas <NUM> may be width W2, and length L1 into the page (not shown). Trenches <NUM> and <NUM> are formed below top surface areas <NUM>, between locations where areas <NUM> or top surfaces of electronic device fins are desired.

<FIG> shows the semiconductor substrate of <FIG> after etching a thickness of the substrate between hardmasks to form sidewalls of the electronic device fins and trenches in the between the hardmasks. <FIG> shows substrate <NUM> after etching a thickness of material <NUM> between hard masks <NUM> or areas <NUM> to form single crystal sidewalls <NUM> and fins <NUM>, <NUM> and <NUM>. In some cases, this etching may include etching a thickness of material <NUM> between hard masks <NUM> or areas <NUM> to create or form single crystal Silicon top surface <NUM> and sidewalls <NUM> and <NUM> of electronic device fins <NUM>, <NUM> and <NUM>. Etching material <NUM> includes etching surface <NUM> at areas <NUM> to form the trenches. Etching to form trenches <NUM> and <NUM> includes etching height H1 of material <NUM> and forming surfaces <NUM>, such as bottom surfaces of the trenches, in or below areas <NUM>. Fins <NUM>, <NUM> and <NUM> may be described as "wide" or "wider" fins, such as fins that will be further etched to form "narrow" or "narrower" fins as noted herein, such as at least with respect to <FIG> and block <NUM>. The etch to form fins <NUM>, <NUM> and <NUM>, may be described as a "first" etch (e.g., to form the thicker fins), such as where the etch at <FIG> (or block <NUM>) is considered a "second" etch to form the narrower fins (e.g., after the first etch).

Etching material <NUM> includes etching a height HI of material <NUM> or substrate <NUM> to form the trenches and the single crystal sidewalls. Fins <NUM>, <NUM> and <NUM> may have height HI width W1 and length L1, into the page (not shown). Such etching may use a "timed" etch, such as an etch for a period of time known to remove height HI of material <NUM>; or may use another process that is known to perform such etching. The fins may be or include an "exposed" device well or channel region extending or disposed surface <NUM>. After etching, sidewalls <NUM> and <NUM> may be adjacent to sidewalls of mask <NUM>. In some cases, inner sidewalls <NUM> and <NUM> may be planar surfaces parallel to and aligned with (e.g., directly below) planar of mask <NUM>.

In some cases, forming fins <NUM>, <NUM> and <NUM> include patterning the top surface of a single crystal substrate (e.g. substrate <NUM>) and etching the substrate between the pattern (e.g. masks <NUM>) to form electronic device fins from a height (e.g. H1) of the substrate extending above etched top surfaces <NUM> of the substrate.

Width W1 may be defined by the horizontal distance between sidewall <NUM> of region <NUM> and side at sidewall <NUM> of region <NUM>. Width W1 may be a width of between <NUM> and <NUM> nanometers (nm). In some cases W1 is approximately <NUM>. Width W2 may be a width of between <NUM> and <NUM> nano-meters (nm). Trench <NUM> may have height HI defined by the vertical distance between top surface <NUM> and top surface <NUM> or <NUM>. Height HI may be a height of between <NUM> and <NUM> nanometers (nm). In some cases HI is approximately <NUM>. Length LI may be defined as the length going into the page and along sidewall <NUM> or sidewall <NUM>. Length LI may be a length of between <NUM> nanometers (nm) and <NUM> micrometers (um). In some cases LI is approximately <NUM>. In some cases LI is equal to (or approximately the same as) W1. According to some embodiments, W1 may be between <NUM> and <NUM> nanometers (nm) and HI may be <NUM> nanometers (nm).

Trenches <NUM> and <NUM> may be formed by patterning and etching as known in the art. This may include patterning and etching material <NUM> to form the trenches. In some cases, patterning and etching material <NUM> includes using a resist or hard mask (e.g., <NUM>) underneath a resist for the patterning materials. In some cases <NUM>, <NUM>, or <NUM> resist layers may be used for the patterning materials. In some cases, patterning and etching material <NUM> to form the trenches includes using an O2 or O2/Ar plasma etch at pressures in the <NUM>-100mTorr range, and at room temperature. Such patterning and etching may also include etching an oxides including STI material, by etching with fluorocarbons (e.g., CF4 and/or C4F8), O2 and Ar, at pressures in the <NUM>-100mTorr range, and at room temperature.

<FIG> shows fins <NUM>, <NUM> and <NUM>; and trenches <NUM> and <NUM> formed in and of substrate <NUM>. However it is contemplated that more, similar fins and trenches may exist on substrate <NUM> (e.g., such as at least hundreds or millions).

Sidewalls <NUM> and <NUM>, and surfaces <NUM> may be subjected to high energy ion bombardment, oxidation, and/or etch residues, depending on the technique used to etch material <NUM>. In some case, the sidewalls and bottom surfaces include crystalline defects that would cause a single crystal material epitaxially grown on them to have defects, and reduced transistor performance if the epitaxially grown material was used as a device channel. If these defects propagate throughout the channel material, they can lead to yield and variations issues in a device built on a device layer formed from epitaxial growth extending above the trench.

<FIG> shows the semiconductor substrate of <FIG> after depositing a thickness of a trench oxide material in the trenches. <FIG> also shows substrate <NUM> after depositing a thickness of trench oxide material <NUM> in trenches <NUM> and <NUM>; and on masks <NUM>. Material <NUM> may have surface <NUM> at or above height H1. Forming material <NUM> may include depositing or forming a thickness of material <NUM> in trenches <NUM> and <NUM>; and on masks <NUM>, up to or above top surfaces <NUM> of fins <NUM>, <NUM> and <NUM>.

In some cases, material <NUM> is a layer of shallow trench isolation (STI) material formed or grown on top surfaces <NUM>, <NUM> (and optionally sidewalls <NUM> and <NUM>) of the substrate <NUM>. Material <NUM> may be formed of an oxide or a nitride or combination thereof. Material <NUM> may be formed of SiC or another material as known in the art. Material <NUM> may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). Material <NUM> is generally deposited via Plasma Enhanced Chemical Deposition (PECVD). In some cases, any of various oxygen precursors, Silane precursors, or generic precursors can be used during a process (e.g., PECVD) to form Material <NUM>, as known in the art. In some cases, Material <NUM> may be formed by a process using TEOS + O2 + RF at <NUM>.

<FIG> shows the semiconductor substrate of <FIG> after polishing the trench oxide material and hardmasks to (e.g., to form) the top surfaces of the fins and etching a thickness of the trench oxide material in the trenches to expose the single crystal sidewalls of the electronic device tins. <FIG> shows substrate <NUM> after polishing oxide material <NUM> to a height of or below the height of surfaces <NUM> to form top surfaces <NUM> of fins <NUM>, <NUM> and <NUM>. Polishing or removing material <NUM> to form surfaces <NUM> may include polishing or removing a thickness of material <NUM> to, or below, height HI of surface <NUM>. Polishing or removing material <NUM> to form surfaces <NUM> may include removing hard masks <NUM> from surfaces <NUM>, thus forming or exposing top surfaces top surfaces <NUM> of fins <NUM>, <NUM> and <NUM>, at height H2, at or from top surfaces <NUM>.

<FIG> also shows substrate <NUM> after etching a thickness of oxide material <NUM> within trenches <NUM> and <NUM> to expose the single crystal sidewalls <NUM> and <NUM> of fins <NUM>, <NUM> and <NUM> may be similar to fins <NUM>, <NUM> and <NUM>, except have height H2 instead of height H1, where height H2 is less than or equal to height H1. Material <NUM> may be top surfaces <NUM> and height H3 in the trenches. Material <NUM> may be width W2 and length L1.

In some cases, etching a thickness of the trench oxide material in the trenches removes thickness H2-H3 of the trench oxide in the trenches and exposes height H2-H3 of the single crystal sidewalls <NUM> and <NUM> of electronic device tins <NUM>, <NUM> and <NUM> to form top surfaces <NUM> of the trench oxide that are recessed or below the top surfaces <NUM> of the electronic device fins. Thickness H2-H3 is shown as thickness or height H21, the height that the fin exudes above the STI plane (e.g., surface <NUM>) and this is the region that may become the channel once the device is fully fabricated. Fins <NUM>, <NUM> and <NUM> may be described as "wide" or "wider" fins, such as fins that will be further etched to form "narrow" or "narrower" fins as noted herein, such as at least with respect to <FIG> and block <NUM>. The etch to form or expose fins <NUM>, <NUM> and <NUM>, may be described as a "first" etch (e.g., to form the thicker fins), such as where the etch at <FIG> (or block <NUM>) is considered a "second" etch to form the narrower fins (e.g., after the first etch).

<FIG> shows trench oxide material <NUM> remaining in trenches <NUM> and <NUM>. Material <NUM> may be a remainder of material <NUM> after etching to remove a height of material <NUM> in the trenches. Etching material <NUM> may include etching material <NUM> at or within areas <NUM>. Etching material <NUM> to form material <NUM> may include etching a thickness H21 of material <NUM>, to remove that thickness of material <NUM> and trenches <NUM> and <NUM>. This etching may also form top surfaces <NUM> of material <NUM> that are recessed or below top surfaces <NUM> of fins <NUM>, <NUM> and <NUM>. In some cases, <FIG> shows substrate <NUM> having single crystal silicon fins <NUM>, <NUM> and <NUM> with STI material <NUM> between those fins. In some cases, <FIG> may show Si wafer <NUM> depositing trench oxide <NUM>, polishing oxide <NUM> and hardmask <NUM> to the level of the top of the fins at H I , and etching oxide <NUM> to recess it below the level of the fins to height H3. In some cases, <FIG> shows substrate <NUM> having single crystal silicon fins <NUM>, <NUM> and <NUM> with STI material <NUM> between those fins. The etch may be a selective etch, such as an etch that selectively etches material <NUM>, but does not etch material <NUM>.

According to some embodiments, fins <NUM>, <NUM> and <NUM> may be formed, grown or produced by other processes. In some cases, fins <NUM>, <NUM> and <NUM> may be grown from a surface of material <NUM> in trenches formed in a layer of trench oxide material formed on a surface of substrate <NUM>. In some cases, fins <NUM>, <NUM> and <NUM> may be formed, grown or produced by processes know in the art. In some cases, fins <NUM>, <NUM> and <NUM> may be conventionally patterned Si fins.

<FIG> shows the semiconductor substrate of <FIG> after etching the top surfaces and the sidewalls of the electronic device fins to form narrower etched single crystal top surfaces and sidewalls of a narrower etched electronic device fins. <FIG> shows substrate <NUM> after etching top surfaces <NUM> and sidewalls <NUM> and <NUM> of fins <NUM>, <NUM> and <NUM> to remove thickness TH2 of material <NUM> to form "narrower" etched single crystal top surfaces <NUM> and sidewalls <NUM> and <NUM> of narrower etched electronic device fins <NUM>, <NUM> and <NUM>. This etch may include forming fins <NUM>, <NUM> and <NUM> having width W3, which is (e.g., extends in width) less than width W1, and having length L1. In some case these fins have a length less than L1. Top surface <NUM> may be at, and fins <NUM>, <NUM> and <NUM> may have height H4 above surface <NUM>. Height H4 may be equal to or less than height H2. For example, surfaces <NUM> may be at or below the height of surfaces <NUM>. Fins <NUM>, <NUM> and <NUM> are shown having height H5 above surface <NUM> of trench oxide material <NUM>, and above surface <NUM> of material <NUM> of substrate <NUM>. The etch to form fins <NUM>, <NUM> and <NUM>, may etch a height of fins <NUM>, <NUM> and <NUM> equal to height H5, such that surface <NUM> is planar with or level with surface <NUM>. In some cases, surface <NUM> is above or below surface <NUM>. The etch to form fins <NUM>, <NUM> and <NUM>, may be described as a "second" etch (e.g., to form the narrower fins), such as where the etch at <FIG> or <FIG> (or block <NUM> or <NUM>) is considered a "first" etch to form the narrower fins (e.g., prior to the second etch).

The etch to form fins <NUM>, <NUM> and <NUM> maybe a trim etch of from <NUM> to <NUM> of each sidewall and the top surface of the fins (e.g., TH1). This etch may depend on the original W1, such as by removing more for greater W1. In some cases, as the width is trimmed, the height will also be reduced by an equal or larger amount. According to embodiments, this reduction in fin height may be undesirable, so in some cases, it is advantageous for the etch to W form fins <NUM>, <NUM> and <NUM> to be in a range of between <NUM> -<NUM> for fin width trimming.

The etch to form fins <NUM>, <NUM> and <NUM> maybe a selective etch, to selectively etch material <NUM>, but not material <NUM>. This etching may include simultaneously etching surfaces <NUM> and sidewalls <NUM> and <NUM>. According to embodiments the etch to form narrower fins <NUM>, <NUM> and <NUM> removes a thickness TH1 of between <NUM> and <NUM> of top surfaces <NUM> and of sidewall surfaces <NUM> and <NUM> of fins <NUM>, <NUM> and <NUM>. In some cases the etch removes thickness TH1 of between <NUM> and <NUM> of those surfaces and sidewalls. In some cases the etch removes thickness TH Z <NUM> of between <NUM> and <NUM> of those surfaces and sidewalls. In some cases the etch removes thickness TH <NUM> of <NUM>, <NUM>, or <NUM> nanometers of those surfaces and sidewalls. In some cases, etching the top surfaces and the sidewalls of the electronic device fins includes forming the etched fins by trimming a width of the device fins from greater than <NUM> to <NUM> to a width of the etched fins of less than <NUM> to <NUM>.

This etch may form surfaces <NUM> and sidewalls <NUM> and <NUM>, which do not contain damaged regions due to excessive high energy bombardment, oxidation, or etch residues; such as compared to the etch to form fins <NUM>, <NUM> and <NUM>; or compared to a dry etch that employs high energy ion bombardment etch (e.g. as known in the art as a physical etch). This etch may exclude or not include a dry etch, a high energy ion bombardment etch; or allowing oxidation of, exposure to oxygen, or residue to form on surfaces <NUM> and sidewalls <NUM> and <NUM>. Thus this etch may reduce or remove defects or damage in a single crystal material subsequently, epitaxially grown on surface <NUM> and sidewalls <NUM> and <NUM>. If such defects were to exist and propagate throughout the channel material, they can lead to yield and drive current reduction issues in a device built on a device layer formed from epitaxial growth on the fin. In some cases, the bits that exude above the STI plane (e.g., portion <NUM> extending above surface <NUM> or <NUM>) are the narrower fin. In some cases, the part below the STI plane (e.g., portion <NUM>) does not conduct a usable or relevant amount of carriers and is defined as a subfin, which has no electronic relevance to the function of the channel.

Such etching may use a "timed" etch, such as an etch for a period of time known to remove thickness TH1 of material <NUM> from surfaces <NUM> and sidewalls <NUM> and <NUM>. The fins may be or include an "exposed" device well or channel region extending or disposed above surface <NUM> or <NUM>. Fins <NUM>, <NUM> and <NUM> may be described as "narrow" or "narrower" fins, such as fins that result after "wide" or "wider" fins are further etched as noted herein, such as at least with respect to <FIG> and block <NUM>.

According to embodiments, etching the top surfaces and the sidewalls of the wider electronic device fins includes using thermal processing. According to the invention, using chlorine based chemistry. According to embodiments, etching the top surfaces and the sidewalls of the wider electronic device fins may include using low ion energy plasma processing (an unclaimed embodiment of the invention) such as using low energy chlorine containing plasma. In some cases, using chlorine or fluorine based chemistry may include using less than <NUM> kW of radio frequency energy, such as for between <NUM> and <NUM> seconds. In some cases, using thermal processing in presence of HCl may include etching in an epitaxial deposition reactor. In some cases, using thermal processing may include using less than <NUM> degrees Celsius heat in a wafer processing chamber, such as for between <NUM> and <NUM> seconds. Another example is anneal in presence of Cl<NUM> at a temperature below <NUM> degrees Celsius for <NUM> sec.

In some cases, <FIG> may show substrate <NUM> after forming trimmed fins <NUM>, <NUM> and <NUM> fins by introducing substrate <NUM> having single crystal silicon fins <NUM>, <NUM> and <NUM> into an epitaxial deposition tool or in epitaxial reactor to etch those fins down to form single crystal silicon fins <NUM>, <NUM> and <NUM>. The tool may use Cl based chemistry using low ion energy plasma processing (an unclaimed aspect of the invention) or thermal processing to trim the fin width (e.g., width W1 of fins <NUM>, <NUM> and <NUM>) from greater than <NUM> (e.g., <NUM>, <NUM> or <NUM>) to a width (e.g., width W3 of fins <NUM>, <NUM> and <NUM>) of <NUM> or below (e.g., <NUM>, <NUM>, <NUM>). In some cases, the low ion energy plasma processing (an unclaimed aspect of the invention) may use an epitaxial deposition tool and a Cl based chemistry using low ion energy plasma processing (an unclaimed aspect of the invention) to achieve a trim etch. One example of this etch includes: using low energy Cl containing plasma, using <NUM> mT, using <NUM> seem CI <NUM>, using <NUM> seem H2, using <NUM> seem Ar, using 500W of radio frequency energy, using ion energy <NUM> eV, and etching for <NUM> seconds, for example. In some cases, the thermal processing may use an epitaxial reactor using low heat processing to achieve a trim etch. One example of this etch includes: using in epi reactor: using <NUM> celsius (C), using <NUM> seem HCl, using <NUM> seem H2, using <NUM> T and etching for <NUM> seconds, for example.

Such fins <NUM>, <NUM> and <NUM> may be used to form fin devices including fin integrated circuit (IC) transistors, resistors, capacitors, etc. formed in or on sidewalls of "fins" grown from or extending above a semiconductor (e.g., silicon) substrate or other material. Such devices may include fin metal oxide semiconductor (MOS) transistor devices, such as those used in a complementary metal oxide semiconductor (CMOS) based on movement of electrons in N-type (e.g., doped to have electron charge carriers) MOS device (n-MOS) channels and movement of positive charged holes in P-type (e.g., doped to have hole charge carriers) MOS device (p-MOS) channels.

According to embodiments, top surfaces and sidewalls of fins <NUM>, <NUM> and <NUM> have or maintain the same atomic lattice and crystal structure as that of fins <NUM>, <NUM> and <NUM>, but contain fewer surface crystal defects, less ion damage, less oxidation and less etch residues than that of fins <NUM>, <NUM> and <NUM>. As a result, there may be fewer defects in or unwanted atoms or material in the crystalline structure of subsequently clad or deposited layers, grown from top surfaces and sidewalls of fins <NUM>, <NUM> and <NUM> (e.g., as compared to that of fins <NUM>, <NUM> and <NUM>). Consequently, the crystalline structure of the subsequently clad or deposited layer growth from fins <NUM>, <NUM> and <NUM> would include defects due to the defects in or additional material upon the crystaline structure of the silicon fin top and sidewall surfaces that will not exist in growth from fins <NUM>, <NUM> and <NUM>. Thus, avoiding or reducing such ion damage, oxidized surfaces and etch residues increases transistor performance.

In some cases, etching using of less energy, lower ion bombardment energy avoids damage to the crystalline structure of the top surface and side walls of the fins while removing atoms during the etch. This type of etching may provide or create narrower fins with clean top and sidewall surfaces of reduced defect crystal lattice (e.g., without defects due to etching to form fin <NUM> from fin <NUM>). This etching may maintain a pure crystal lattice existing below the top and sidewall surfaces of fin <NUM>; may avoid creating amorphized material and avoid vacancy or interstitial atoms on top and sidwall surfaces of fin <NUM>, such as by excluding or avoiding what is considered a "physical etch" i.e. ion damage. For example chlorine ions in the plasma may have an imingement energy equal to or less than <NUM> eV which chemically, rather than physically etches the silicon fin and avoids damage the crystal lattice.

A thermal treatment may be or include an all chemical, no plasma etch that uses HCl Cl<NUM> for example at a high enough temperature that converts the silicon atoms on the surface when the chlorine interacts with those silicon atoms to form SiCl<NUM> gas which is then pumped out of the chamber during treatment, but does not use a high enough temperature to damage or amorphize the crystal lattice of exposed surfaces of the etched fin <NUM>. The thermal etch may be or include a dynamic treatment with no plasma, and be at less than <NUM> degrees Celsius. In some cases, in this recipe no physical sputtering occurs but the chlorine reacts to form SiCl<NUM> gas which evaporates away from the Si surfaces and is pumped out.

According to some embodiments, fins <NUM>, <NUM> and <NUM> are electronic device fins having narrower upper fin portion <NUM> formed on and from wide lower fin portion <NUM>. The upper and lower portions may be formed from substrate <NUM> of a first single crystal material <NUM>. The upper and lower portions may be formed under first top surface area <NUM>. The wide lower fin portion <NUM> may have wide single crystal top surfaces and wide sidewalls with width W1 between first thickness H3 of trench oxide material <NUM> in trenches formed between the first top surface areas. The narrower upper fin portion <NUM> may have narrower single crystal top surfaces and narrower sidewalls with width W3 and with a same single crystal lattice as the wide single crystal top surfaces and the wide sidewalls. The wide single crystal top surfaces and the wide sidewalls with width W1 may have a thickness of between a <NUM> and <NUM> greater than a thickness of the narrower single crystal top surfaces and the narrower sidewalls with width W3. The narrower upper fin portion <NUM> may be exposed above the first thickness H3 of trench oxide material <NUM> in the trenches. In some cases, portion <NUM> may be described as sub-channel. In some cases, portion <NUM> is the channel and hence may conduct most of the carriers while portion <NUM> will be far from the gate electrode and will not be part of the channel.

According to some embodiments, <FIG> provides embodiments where the fins are trimmed and no additional cladding layer is added. In some cases, these narrower tins can be used to create transistors that will be improved by virtue of the better electrostatics of the narrow fin versus an equivalent device with a wide fin.

<FIG> shows the semiconductor substrate of <FIG> after depositing a second single crystal material on the etched top and sidewall surfaces of the narrower etched fins. In some cases, immediately and without air break, after etching to form fins <NUM>, <NUM> and <NUM>, SiGe or Ge deposition of material <NUM> is performed on substrate <NUM> (e.g., on fins <NUM>, <NUM> and <NUM>), such as is shown in <FIG>. In some cases, <FIG> shows epitaxial layer <NUM> deposited on trimmed fins <NUM>, <NUM> and <NUM>. Layer <NUM> may be a second crystal structure grown from the single crystal structure of material <NUM> at top surface <NUM> and from sidewalls <NUM> and <NUM>.

<FIG> shows substrate <NUM> after depositing or growing single crystal material or layer <NUM> on fins <NUM>, <NUM> and <NUM>. Material <NUM> may be epitaxially grown from or on surfaces <NUM> and sidewalls <NUM> and <NUM>. Material <NUM> may be thickness TH2 at surface <NUM> and sidewalls <NUM> and <NUM>. Material <NUM> may be epitaxially grown as a "blanket" layer on surface <NUM> and sidewalls <NUM> and <NUM>. Material <NUM> may have top surface <NUM> and sidewalls <NUM> and <NUM>. Surface <NUM> may be of height H6 of the surface <NUM>. Material <NUM> may be a single crystal material that is the same as or different than the single crystal material <NUM> of substrate <NUM>. In some cases material <NUM> is single crystal silicon, and material <NUM> is single crystal germanium. In some cases material <NUM> is single crystal silicon and material <NUM> is single crystal silicon germanium having a percentage of germanium of between <NUM> and <NUM> percent. In some cases the percentage of germanium is between <NUM> and <NUM>%. In some case the percentage of germanium is <NUM>%, <NUM>%, <NUM>%, or <NUM>%.

Material <NUM> on fins <NUM>, <NUM> and <NUM> may form clad fins <NUM>, having width W4, height H6 above surface <NUM>, and length LI into the page (not shown). Fins <NUM> may be described as etched silicon fins having side-cladding layers (e.g. material <NUM>) of silicon germanium.

In some cases width W4 is less than width W1, but greater than width W3. In some cases width W4 is greater than width W1. In some cases Width W4 is less than or equal to <NUM> wide. In some cases width W4 is <NUM>, <NUM>, <NUM>, <NUM>, or <NUM>.

Material <NUM> may be formed on, grown from, and touching material <NUM> (e.g., surfaces <NUM> and sidewalls <NUM><NUM> and <NUM>). Material <NUM> may be formed to a conformal thickness (e.g., a thickness increasing the "height" on the top surface and "width" on the sidewalls) over fins <NUM>, <NUM> and <NUM>. The conformal thickness TH2 may be between <NUM> and <NUM> nanometers (nm). In some cases the conformal thickness TH2 is between <NUM> and <NUM> nanometers (nm). In some cases the conformal thickness TH2 is approximately <NUM>. In some cases the conformal thickness TH2 is approximately <NUM>. According to some embodiments, forming material <NUM> includes epitaxially cladding or growing material <NUM> along, across, touching or against the sidewall surfaces and the top surface of the electronic device fin <NUM>.

Material <NUM> may be formed by epitaxial growth (e.g., heteroepitaxy growth) using atomic layer epitaxy (ALE), chemical vapor deposition (CVD), Metal-Organic Chemical Vapour Deposition (MOCVD) or Metal-Organic vapour phase epitaxy (MOVPE), and may only grow from "seed" top surface <NUM> and sidewalls <NUM> and <NUM> of material <NUM>, but not grow from oxide <NUM>. In some cases, material <NUM> may be formed by epitaxial growth (e.g., heteroepitaxy). In some cases, material <NUM> may be formed by selective growth, such as by a CVD type of growth, gas source-molecular beam epitaxy (GS-MBE), rapid thermal (RT) CVD, or ultra high vacuum (UHV)-CVD. Choice of growth conditions such as growth temperature, pressure of gas flux, etc may define the selectivity of the epitaxial growth. In some cases, the growth of material <NUM> is grown selectively from material <NUM> by choosing or using a predetermined growth temperature range, pressure, gas flux range, etc., as known for material <NUM> to grow from material <NUM>, but not grow from or initiate on material of the oxide surfaces.

In some cases, material <NUM> may be a "device" layer, such as a layer on or in which circuity devices are formed, as known in the art. Thus, the fins formed from material <NUM> may provide electronic device channel material on or in which defect free fin based devices may be formed.

Material <NUM> may have a bottom surface having a (<NUM>) crystal oriented material grown from surface <NUM>, and side surfaces having a (<NUM>) crystal oriented material along or adjacent to sidewalls <NUM> and <NUM>. Material <NUM> may have a bottom surface along surface <NUM> and sidewalls <NUM> and <NUM> having the same crystal orientation as those surfaces. In some cases, surface <NUM> and sidewalls <NUM> and <NUM> having a same crystal orientation as surface <NUM> and sidewalls <NUM> and <NUM>, such as due to being material grown from those surfaces.

In some cases, material <NUM> may be a "cladding" material that is "selectively" grown only from a desired single crystal material (e.g., surfaces <NUM> and sidewalls <NUM> and <NUM>) but not from other polycrystal, dielectric, oxide, nitride or amorphouse exposed materials (e.g., that are not the desired or are not a single crystal material). In some cases, a "cladding" material (e.g., material <NUM>) may be "selectively" grown only from a desired single crystal material (e.g., surfaces <NUM> and sidewalls <NUM> and <NUM>) by masking or forming oxide layers over materials that it is not desired to have the "cladding" material form or grow from.

In some cases, material <NUM> is a selectively grown epitaxial layer. In some cases, material <NUM> is single crystal Si material; and material <NUM> is a layer of single crystal SiGe material (e.g., <NUM> percent Si, and <NUM> percent Ge) such as for an P-type device formed from fin <NUM>. In some cases, material <NUM> is a layer of single crystal SiGe material (e.g., <NUM> percent Si, and <NUM> percent Ge) such as for an P-type device formed from fin <NUM>.

In some cases, material <NUM> is a channel material or layer for a tri-gate device having the channel conducting charges mostly along or through material <NUM>. This may include conducting charges mostly along or through top surface <NUM> and sidewalls <NUM> and <NUM>.

Fins <NUM> (e.g., clad with material <NUM>) may be used to form fin devices including fin integrated circuit (IC) transistors, resistors, capacitors, etc. formed in or on sidewalls of "fins" grown from or extending above a semiconductor (e.g., silicon) substrate or other material. Such devices may include fin metal oxide semiconductor (MOS) transistor devices, such as those used in a complementary metal oxide semiconductor (CMOS) based on movement of electrons in N-type (e.g., doped to have electron charge carriers) MOS device (n-MOS) channels and movement of positive charged holes in P-type (e.g., doped to have hole charge carriers) MOS device (p-MOS) channels.

According to some embodiments, fins <NUM> further increase in the mobility of the holes (e.g., carriers) in the p-channel (e.g., channel of PMOS device formed by fin <NUM>) by providing a compressive strain to the channel body because the lattice spacing of the Si material <NUM> (e.g., at surfaces <NUM> and sidewalls <NUM> and <NUM>) is smaller than that of the SiGe or Ge material <NUM> grown from or touching those surfaces. This causes a compressive strain in material <NUM> where a majority of the carriers flow through the channel. In some cases, material <NUM> has at least <NUM>% germanium; at least <NUM>% germanium; between <NUM>% and <NUM>% germanium; between <NUM>% and <NUM>% germanium; or between <NUM>% and <NUM>% germanium. In some cases, most carriers in the channel are at the outer surfaces or outer edges of the cladding <NUM>. In some cases, most carriers in the channel are at the inner surfaces or inner edges of the cladding <NUM>.

Λ benefit of having tins with silicon having a width of W3 or material <NUM> having a width of W4 includes that such reduced width tins make it easier to electronically invert the channel by application of gate bias and reduce carrier leakage when the gate is not biased. This is as opposed to wider fins (e.g., fins <NUM>) which may have worse electronic properties than the narrower fins.

In some embodiments, equipment for forming fins <NUM>, <NUM>, <NUM> and <NUM> may include equipment from suppliers that are configured into a system including various chambers and vessels that have a vacuum sealed environment, and a robot for moving wafers between the various chambers. The "in-situ" methods herein may include keeping or maintaining substrate <NUM> and fins within these vessels or within this vacuum environment (e.g., system) so that the substrate and fins are not exposed to air although they may be moved into different chambers of the system, such as by being moved to chambers of the same equipment set without breaking the vacuum seal of the chambers, or without an "air break" during movement of the substrate between chambers.

<FIG> is a schematic perspective view of the semiconductor substrate of <FIG> after forming a gate electronic device on the second single crystal material formed on the etched top and sidewall surfaces of one of the narrower etched fins. <FIG> shows cross sectional view perspective A- A, which may be the perspective of <FIG>. <FIG> may schematically illustrate a perspective view of transistor device <NUM>, in accordance with some embodiments.

<FIG> shows substrate <NUM> after forming gate electronics device <NUM> on material <NUM> formed on surfaces <NUM> and sidewalls <NUM> and <NUM> of narrower etched fins <NUM>, <NUM> and <NUM>. Device <NUM> may have a narrow channel <NUM> that is or includes fin <NUM>. Fin <NUM> has length LI, width W4 and height H6 above surface <NUM> or <NUM>. Narrow channel <NUM> may have top surface <NUM> and sidewalls <NUM> and <NUM>. A gate dielectric (not shown) may be formed over surface <NUM> and sidewalls <NUM> and <NUM> under gate electrode <NUM>, spacers <NUM> may be formed on or beside gate electrode <NUM>. Mass <NUM> may be formed on the top surface of gate electrode <NUM>. Mask <NUM> may be a hard mask that can be removed to form a metal gate contact. Device <NUM> includes fin <NUM> and may be formed on material <NUM>. In some cases, device <NUM> is a PMOS device formed from the clad electronic device fin <NUM>, wherein the PMOS device include gate <NUM> on second single crystal material <NUM>; and junction regions (not shown) on both sides and adjacent to the gate and in the second single crystal material.

According to some embodiments, <FIG> schematically illustrates a perspective view of a transistor device <NUM>, in accordance with some embodiments. In some embodiments, the transistor device <NUM> includes a semiconductor substrate <NUM>, a fin structure <NUM> including a portion composed of SiGe alloy (hereinafter "SiGe material <NUM>") and a portion composed of Si (hereinafter "Si fin <NUM>"), electrically insulative material <NUM>, a gate <NUM> including a gate dielectric (not shown, but between electrode <NUM> and surface <NUM> and sidewalls <NUM> and <NUM>) and gate electrode <NUM>, coupled as can be seen.

The transistor device <NUM> may represent a transistor or part of a transistor in various embodiments. For example, the fin structure <NUM> may extend along a surface of the semiconductor substrate <NUM> (e.g., through material of gate <NUM>). A source and drain (not shown) may be formed on or in portions <NUM> and <NUM> of the fin structure <NUM> that are separated by the gate <NUM> to provide a source and drain for mobile charge carriers (e.g., holes or electrons) that may flow through a channel body formed from the fin structure <NUM>. The gate <NUM> may, for example, be configured to control the flow of the mobile charge carriers through the channel body by application of a threshold voltage to the gate electrode <NUM>. The channel body may include part of a fin structure <NUM> formed from Si of the semiconductor substrate <NUM>. In some embodiments, the channel body may include portions of the SiGe material <NUM> of the tin structure <NUM> and may be disposed in a gate region between the source and the drain.

The semiconductor substrate <NUM> may be composed of Si in some embodiments. For example, the semiconductor substrate <NUM> may include n-type or p-type (<NUM>) off-oriented Si, the crystalline directions of the semiconductor substrate <NUM> being symbolized by the convention (xyz), where x, y, and z represent respective crystallographic planes in three dimensions that are perpendicular to one another. The semiconductor substrate <NUM> may, for example, include material of a (<NUM>) direction off-cut in a range between about <NUM> degrees to about <NUM> degrees towards a (<NUM>) direction. Other off-cut orientations or a semiconductor substrate <NUM> without an off-cut orientation may be used. The semiconductor substrate <NUM> may have a high resistivity between about <NUM>Ω-cm to about <NUM> kΩ-cm. The semiconductor substrate <NUM> may include other materials in other embodiments. In some embodiments, the semiconductor substrate <NUM> is part of a cingulated die of a wafer. In one embodiment, the semiconductor substrate is a p-type substrate.

According to various embodiments, the SiGe material <NUM> of the fin structure <NUM> may be formed by etching fin <NUM> (or <NUM>) to form narrower fin <NUM> and depositing a transistor element such as, for example, the material <NUM> using techniques described herein. In some embodiments, only a portion of the fin structure <NUM> is covered with material <NUM>. The Si tin <NUM> of the fin structure <NUM> may be composed of a defect- free single crystal in some embodiments. In other embodiments, most or all of the transistor element (e.g., tin structure <NUM>) may be covered with material <NUM>.

The transistor device <NUM> may be p-type or n-type. The channel body formed using the SiGe material <NUM> may provide greater mobility of mobile charge carriers for p-type. For example, increasing a concentration of germanium (Ge) in the channel body may increase mobility of electrons or holes by nature of the material. A second mechanism causes further increase in the mobility of the holes in the p-channel (e.g., channel of PMOS device) by providing a compressive strain to the channel body because the lattice spacing of the Si material <NUM> is smaller than that of the SiGe or Ge material <NUM>, thus causing a compressive strain in material <NUM> where a majority of the carriers flow through the channel.

The compressive strain of the SiGe material <NUM> will reduce mobility of electrons for n-channel (e.g., channel of NMOS device). Thus, increasing the concentration of Ge in the n-channel may result in little to no mobility improvement for electrons. In one embodiment, the transistor device <NUM> is p-type (e.g., PMOS device). The PMOS device may have a p- channel that is doped n-type and the NMOS device may have an n-channel that is doped p-type.

The electrically insulative material <NUM> may be deposited on the semiconductor substrate <NUM> and may abut the fin structure <NUM>, as can be seen. The electrically insulative material <NUM> may include any suitable material for shallow trench isolation (STI). In some embodiments, the electrically insulative material <NUM> may include dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon oxide, carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

The gate dielectric (not shown, but between electrode <NUM> and surface <NUM> and sidewalls <NUM> and <NUM>) may be formed on the channel body and may be composed of a material such as silicon dioxide (Si0<NUM>) or a high-k material. Examples of high-k materials that may be used to form the gate dielectric (not shown, but between electrode <NUM> and surface <NUM> and sidewalls <NUM> and <NUM>) include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric (not shown, but between electrode <NUM> and surface <NUM> and sidewalls <NUM> and <NUM>) to improve its quality when a high-k material is used. In some embodiments, the gate dielectric (not shown, but between electrode <NUM> and surface <NUM> and sidewalls <NUM> and <NUM>) may include a dummy oxide that is subsequently removed in a process How together with a dummy gate electrode and replaced with a high-k gate dielectric and metal gate, according to well-known techniques.

The gate electrode <NUM> may be formed on the gate dielectric (not shown, but between electrode <NUM> and surface <NUM> and sidewalls <NUM> and <NUM>) and may be composed of at least one p-type workfunction metal or n-type workfunction metal, depending on whether the transistor is to be a PMOS (e.g., p-type) or an NMOS (e.g., n-type) transistor. In some embodiments, the gate electrode <NUM> may consist of two or more metal layers, where at least one metal layer is a workfunction metal layer and at least one metal layer is a fill metal layer. In some embodiments, the gate electrode <NUM> is a polysilicon gate electrode. In other embodiments, the gate electrode <NUM> is a dummy polysilicon gate electrode that is subsequently removed in a process flow and replaced with a metal gate electrode, according to well-known techniques.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A p-type metal layer may enable the formation of a PMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV. For an NMOS transistor, metals that may be used for the gate electrode <NUM> include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An n-type metal layer may enable the formation of an NMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV.

In some embodiments, a pair of spacers <NUM> may bracket the gate <NUM>. For example, the spacers may be disposed on opposing surfaces of the gate electrode <NUM>. The spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming spacers may generally include deposition and etching processes and/or other well-known techniques.

The transistor device <NUM> of <FIG> depicts a tri-gate configuration. In other embodiments, similar principles and techniques as described herein for converting a transistor element from Si to SiGe may be used for other transistor configurations including, for example, planar, dual-gate, all around gate (AAG) (also referred to as gate all around), wire (e.g., nanowire), and other suitable transistor configurations.

<FIG> is an example process tor forming a gate electronic device on a second single crystal material formed on narrower etched single crystal top and sidewall surfaces of a narrower etched electronic device fin. <FIG> may show process <NUM> for forming fins <NUM>, <NUM> and <NUM><NUM>. In some cases process <NUM> is a process performing clad fins <NUM>. In some cases, the process is <NUM> is or includes part of a process for forming device <NUM>.

<FIG> shows process <NUM> beginning with block <NUM> where, in some optional cases, hardmask patterns are formed on first top surface areas of a single crystal substrate where top surfaces of the electronic device fins are desired. This may include foming masks <NUM> an areas <NUM> as described herein. Block <NUM> may include descriptions herein for <FIG>.

At block <NUM>, a thickness of second top surface areas of the substrate between the first top surface areas is etched to form single crystal sidewalls of the electronic device fins and to form trenches in the between the first top surface areas. This may include foming trenches <NUM> and <NUM>; and sidewalls <NUM> and <NUM> as described herein. Block <NUM> may include descriptions herein for <FIG>. The etch at block <NUM>, may be described as a "first" etch (e.g., to form the thicker fins), such as where the etch at <FIG> (or block <NUM>) is considered a "second" etch to form the narrower fins (e.g., after the first etch).

At block <NUM>, a thickness of a trench oxide material is deposited in the trenches and over the masks. This may include depositing material <NUM> as described herein. Block <NUM> may include descriptions herein for <FIG>.

At block <NUM>, in some optional cases, a thickness of the trench oxide material and the hardmasks are polished down to form the top surfaces of the electronic device fins. This may include removing a thickness of material <NUM> and hardmasks <NUM> to expose surfaces <NUM> as described herein. This may include removing all of hardmasks <NUM> (e.g., of block <NUM>) as described herein. Block <NUM> may include descriptions herein for <FIG>.

At block <NUM>, in some optional cases, a thickness of the trench oxide material in the trenches is etched to expose the single crystal sidewalls of the electronic device fins and to form top surfaces of the trench oxide that are below the top surfaces of the electronic device fins. This may include etching a thickness of material <NUM> in trenches <NUM> and <NUM> down to surfaces <NUM> to form trench oxide <NUM>; to expose the single crystal sidewalls <NUM> and <NUM> of the electronic device fins; and to form top surfaces <NUM> of the trench oxide that are below the top surfaces <NUM> of the electronic device fins as described herein. Block <NUM> may include descriptions herein for <FIG>. The etch at block <NUM> may be described as a "first" etch (e.g., to form the thicker fins), such as where the etch at <FIG> (or block <NUM>) is considered a "second" etch to form the narrower fins (e.g., after the first etch).

At block <NUM>, the top surfaces and the sidewalls of the electronic device fins are (e.g., simultaneously) etched to form single crystal defect free etched top surfaces and etched sidewalls of electronic device etched fins. This may include etching to remove a thickness of between a <NUM> and <NUM> of the top surfaces and the sidewalls of the electronic device fins. This may include simultaneously etching top surfaces <NUM> and the sidewalls <NUM> and <NUM> of electronic device fins <NUM> and <NUM> (e.g., simultaneously) to form single crystal defect free etched top surfaces <NUM> and the sidewalls <NUM> and <NUM> of narrower electronic device fins <NUM> and <NUM> as described herein. Block <NUM> may include descriptions herein for <FIG>. Block <NUM> may include etching the top surfaces and the sidewalls of the electronic device fins to form narrower etched single crystal top surfaces and sidewalls of a narrower etched electronic device fins. In some cases, block <NUM> includes maintaining (e.g., not creating defects in) the single crystal structure of the top and sidewall surfaces of the device fins of the etched top surfaces <NUM> and the sidewalls <NUM> and <NUM>. The etch to form fins <NUM> and <NUM>, may be described as a "second" etch (e.g., to form the narrower fins), such as where the etch at <FIG> or <FIG> (or block <NUM> or <NUM>) is considered a "first" etch to form the narrower fins (e.g., prior to the second etch).

In some cases, block <NUM> includes etching the top surfaces and the sidewalls of the electronic device fins using one of (<NUM>) chlorine based chemistry using low ion energy plasma processing (an unclaimed aspect of the invention), or (<NUM>) thermal processing. In some cases, etching the top surfaces and the sidewalls of the electronic device fins includes forming the etched fins by trimming a width of the device fins from greater than <NUM> to <NUM> to a width of the etched fins of less than <NUM> to <NUM>.

At block <NUM>, a second single crystal material is deposited on or grown from the top and sidewall surfaces of the etched narrow fins (e.g., of block <NUM>). This may include the second single crystal material being deposited on or grown, without air break of the treatment chamber after etching the top surfaces and the sidewalls of the electronic device fins in block <NUM>. The second single crystal material may have a lattice spacing that is different (e.g., larger) than a lattice spacing of the first single crystal material. This may include, without air break of the treatment chamber after etching to form narrower fins <NUM> and <NUM>, depositing second single crystal material <NUM> on the top surfaces <NUM> and sidewalls <NUM> and <NUM> of the etched narrower fins, wherein the second single crystal material has a lattice spacing that is different than a lattice spacing of the first single crystal material as described herein. Block <NUM> may include descriptions herein for <FIG>.

At block <NUM>, in some optional cases, a gate is formed over the second single crystal material, and junction regions are formed in the second single crystal material adjacent to and on either side of the gate. This may include forming gate <NUM> over the second single crystal material <NUM>, and forming junction regions in the second single crystal material <NUM> as described herein. This may include forming a cladding of SiGe material <NUM> of the fin structure <NUM> may be formed by etching fin <NUM> (or <NUM>) to form narrower Si fin <NUM> and depositing a transistor element such as, for example, the material <NUM> as described herein. This may include forming part of or all of device <NUM> as described herein. Block <NUM> may include descriptions herein for <FIG>.

Thus, the processes described herein may avoid or reduce high energy ion bombardment, oxidation and etch residues on Silicon fin surfaces, which are damaging to the quality of subsequently clad or deposited layers. Consequently, the crystaline structure of subsequently clad or deposited layer growth will not include defects due to the defects in or additional material upon the crystaline structure of the silicon fin top and sidewall surfaces. That growth may provide electronic device material (e.g., wells and/or channels) in which defect free fin based devices and transistors may be formed. Thus, avoiding or reducing such bombardment, oxidation and residues increases transistor performance.

Such transistors may include finfets, Ge cladding, SiGe channels, SiGe cladding, trigate transistors. Such transistors may be produced by High Volume Architecture and may be embodied in computer system architecture features and interfaces made in high volumes. Such transistors may be included in or formed by very large scale integration (VLSI) logic processes.

<FIG> illustrates a computing device <NUM> in accordance with one implementation. The computing device <NUM> houses board <NUM>. Board <NUM> may include a number of components, including but not limited to processor <NUM> and at least one communication chip <NUM>. Processor <NUM> is physically and electrically connected to board <NUM>. In some implementations at least one communication chip <NUM> is also physically and electrically connected to board <NUM>. In further implementations, communication chip <NUM> is part of processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically connected to board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

Communication chip <NUM> enables wireless communications for the transfer of data to and from computing device <NUM>. Communication chip <NUM> may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE <NUM> family), WiMAX (IEEE <NUM> family), IEEE <NUM>, long term evolution (L I E), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as <NUM>, <NUM>, <NUM>, and beyond. Computing device <NUM> may include a plurality of communication chips <NUM>.

Processor <NUM> of computing device <NUM> includes an integrated circuit die packaged within processor <NUM>. In some implementations, the integrated circuit die includes transistors formed by epitaxially growing second crystal material <NUM> on surfaces of etched, thinned first crystal material fins (e.g., <NUM>, <NUM> and <NUM>) formed by etching wider fins of the first crystal material, such as described with reference to <FIG>. In some implementations, the integrated circuit die includes electronic device fins having narrower upper fin portion <NUM> formed on and from wide lower fin portion <NUM>, such as described with reference to <FIG>. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip <NUM> also includes an integrated circuit die packaged within communication chip <NUM>. In accordance with another implementation, a package including a communication chip incorporates one or more fin devices having transistors formed by epitaxially growing a second crystal material on surfaces of etched, thinned first crystal material fins formed by etching wider fins of the first crystal material such as described above. In further implementations, another component housed within computing device <NUM> may contain a microelectronic package including a fin device having cladding device layers such as described above. In various implementations, computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device <NUM> may be any other electronic device that processes data.

In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. The particular embodiments described are not provided to limit embodiments of the invention but to illustrate it. The scope of the embodiments of the invention is not to be determined by the specific examples provided above but only by the claims below. In other instances, well-known structures, devices, and operations have been shown in block diagram form or without detail in order to avoid obscuring the understanding of the description. Where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.

Claim 1:
A method to form electronic device fins in one or more chambers that have a vacuum sealed environment, the method comprising:
etching away a thickness of a substrate (<NUM>) between first top surface areas of a substrate of a first single crystal material to form wide electronic device fins (<NUM>) under the first top surface areas and to form trenches (<NUM>, <NUM>) between the first top surface areas, the wide electronic device fins having wide single crystal top surfaces and wide sidewalls;
forming a first thickness of a trench oxide material (<NUM>) in the trenches and below the first top surface areas;
etching a thickness of the wide single crystal top surfaces and the wide sidewalls of the wide electronic device fins to form narrower electronic device fins (<NUM>, <NUM>, <NUM>) from the wide fins, the narrower electronic device fins having narrower single crystal top surfaces and narrower sidewalls with a same single crystal lattice as the wide single crystal top surfaces and the wide sidewalls, wherein etching the thickness of the wide single crystal top surfaces and the wide sidewalls includes removing a thickness of between a <NUM> and <NUM> of the wide single crystal top surfaces and the wide sidewalls, said etching comprising etching using thermal processing, wherein the thermal processing includes using HCl or Cl<NUM> gas streams in a hydrogen environment at temperatures below <NUM> or <NUM>, respectively; and
after etching the thickness of the wide single crystal top surfaces and the wide sidewalls, without an air break of a chamber, depositing a second single crystal material (<NUM>) on the thinned top surfaces and thinned sidewalls to form clad electronic device fins, wherein the second single crystal material has a lattice spacing that is larger than a lattice spacing of the first single crystal material.