Patent Description:
A 3D-NAND memory device is an exemplary device of stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. In a related 3D NAND architecture, periphery circuits take up about <NUM>-<NUM>% of die area, which lowers NAND bit density. As 3D NAND technology continues to progress to <NUM> layers and above, the periphery circuits will likely take up more than <NUM>% of the total die area.

In a cross-stacking structure, the periphery circuits which handle data I/O as well as memory cell operations are processed on a separate wafer (CMOS wafer) using a logic technology node (i.e., <NUM>, <NUM>) that enables the desired I/O speed and functions. Once the processing of a cell array wafer is completed, the two wafers are connected electrically through millions of metal vertical interconnect accesses (VIAs) that are formed simultaneously across the whole wafer in one process step. By using the innovative cross-stacking structure, the periphery circuits are now above cell array chip formed in the cell array wafer, which enables much higher NAND bit density than related 3D NAND with limited increase in total cost.

<CIT> discloses a semiconductor device. <CIT> discloses a stacked three-dimensional heterogeneous memory devices and methods for forming same. <CIT> discloses a three-dimensional memory devices and methods for forming the same.

The inventive concepts relate to formation of a 3D NAND memory device according to claim <NUM>. Another aspect relates to a method for manufacturing a 3D-NAND memory device according to claim <NUM>.

A related 3D-NAND memory device can include two or more n-well regions formed in a top region of a substrate, and two or more array common source (ACS) structures that are formed over the two or more n-well regions. Each of the two or more ACS structures is in contact with a respective n-well region. The related 3D-NAND memory device can also have a plurality of M1 routing lines. The M1 routing lines are electrically coupled to the ACS structures through a plurality of M1 VIAs. A plurality of source lines are positioned over the plurality of M2 routing lines. The source lines are electrically coupled to the M1 routing lines through a plurality of M2 VIAs.

In the related 3D-NAND memory device, an input voltage is applied to the n-well regions through a conductive channel that is formed by the source lines, the M2 VIAs, the M1 routing lines, the M1 VIAs, and the ACS structures. The ACS structures typically are wall-shaped line contacts along a word line (WL) direction of the 3D-NAND memory device. Such a wall-shaped contact needs sufficient conductivity to prevent a ground noise from arising in sensing operations. The ACS structures can be formed with tungsten, polysilicon, or tungsten plus polysilicon because tungsten, polysilicon, or tungsten plus polysilicon are appropriate materials to conformally fill deep and wide contact trenches with minimal voids. Despite of process friendly characteristics, tungsten and polysilicon have relatively high resistivity compared to other contact metals, such as Cu or Al. As a height of 3D NAND stacks increases with its memory density, a height of the ACS structures accordingly grows. A resistance of the ACS structures inevitably surges in a height direction of the 3D NAND stacks. To reduce such resistance increase along the height escalation, a width of the ACS regions should get proportionally larger, which in turn impacts a die size and wafer mechanical stability due to high tungsten stress.

In the present disclosure, a cross-stacking structure is applied to form a 3D-NAND memory device. In the cross-stacking structure, a plurality of transistors are formed over the top surface of a CMOS substrate (or periphery circuit substrate), and a memory cell stack is formed over the top surface of a cell array substrate. The CMOS substrate is bonded through bonding VIAs with the cell array substrate. Here, the top surface of the CMOS substrate and the top surface of the cell array substrate are aligned facing each other.

In the disclosed 3D-NAND memory device, two or more n-well regions extend in the cell array substrate from the top surface of the cell array substrate. A plurality of bottom source lines are formed over a bottom surface of the cell array wafer. The bottom source lines are coupled to the n-well regions through a plurality of VIA contacts. The VIA contacts are formed to extend from the bottom surface of the cell array wafer to reach the n-well regions. In addition, the n-well regions are coupled to a plurality of top source lines through a conductive channel that is formed by two or more ACS structures formed over and coupled to the n-well regions, a plurality of M1 routing lines formed over and coupled to the ACS structures, and a plurality of top source lines formed over and coupled to the M1 routing lines.

By introducing such a cross-point structure mentioned above, the bottom source lines (or bottom source line mesh) can be electrically coupled to n-well regions from a polished backside (i.e., the bottom surface) of the cell array substrate. Accordingly, a resistance of source lines to n-well regions can be decreased. Comparing to the related 3D-NAND memory device, where the n-well regions is coupled to the source line mesh (or source lines) through the conductive channel that is formed by the source lines, the M2 VIAs, the M1 routing lines, the M1 VIAs, and the ACS structures, the present disclosure can have direct connection from source lines to n-well regions through VIA contacts made of conductive metal, such as Cu. In contrast to the related examples, the present disclosure can provide several advantages. For example, the decreased resistance of source lines to n-well regions reduces ground noise that is a undesired voltage increase in the n-well regions. Also, the resistance of the ACS structures does not impact a source side resistance of the memory device and the ground noise. Further, the disclosed structure can eliminate gaps between M1 routing lines that are used to add contacts to connect source line mesh and ACS structures in the related examples, which in turn helps die size reduction in a word line direction.

According to the present invention, a semiconductor device architecture is provided as follows. The semiconductor device includes a first substrate that has a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device also includes a doped region and a first connection structure (also referred to as a first source line mesh). The doped region is formed in the first side of the first substrate and is electrically coupled to at least a source terminal of a transistor (e.g., a source terminal of an end transistor of multiple transistors that are connected in series). The first connection structure is formed over the second side of the first substrate and coupled to the doped region through a first VIA. The first VIA extends from the second side of the first substrate to the doped region.

The semiconductor device further includes a common source structure (also referred to as array common source structure) formed over and coupled to the doped region, a bit line formed over the common source structure that is coupled to the common source structure through a second VIA, and a second connection structure (also referred to as a second source line mesh) positioned over the bit line that is coupled to the bit line through a third VIA. The first connection structure and the second connection structure are coupled to each other.

A transistor is formed in a first side of a second substrate and a bonding VIA formed over and coupled to the transistor. In addition, the first side of the first substrate and the first side of the second substrates are aligned facing each other so that the transistor is coupled to the second connection structure through the bonding VIA.

The semiconductor device can further include a fourth VIA that is formed over the second connection structure and connected to the bonding VIA. The first substrate and the second substrate are bonded each other through the fourth VIA and the bonding VIA.

In some embodiments, the first VIA extends through the doped region and is in contact with the common source structure. The semiconductor device can include a spacer layer disposed between the first VIA and the first substrate so that isolates the first VIA from the first substrate.

Additionally, a highly doped n+ region can be arranged between the first VIA and the doped region, and the doped region is n-type. The first VIA can have at least one of an extended wall-shape that has a tapered cross section or a frustoconical shape.

The semiconductor device further includes a plurality of channel structures extending from the first side of the first substrate, and a plurality of word lines positioned over the first side of the first substrate in a staircase configuration. The plurality of the word lines are spaced apart from each other by a plurality of insulating layers. The channel structures extend through the plurality of word lines and the plurality of the insulating layers. The plurality of channel structures are disposed below the bit line, and the common source structure extends through the plurality of word lines and the plurality of insulating layers and separates the plurality of the channel structures.

According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is disclosed. In the disclosed method, a first VIA that extends from a second side of the first substrate is formed. The first substrate has an opposing first side on which a memory stack is formed. The memory stack includes a doped region positioned in the first side of the first substrate. The doped region is electrically coupled to at least a source terminal of a transistor (e.g., a source terminal of an end transistor of multiple transistors that are connected in series) and the first VIA is in direct contact with the doped region. Further, a first connection structure is formed over the first VIA so that the first connection structure is coupled to the doped region through the first VIA.

In some embodiments, in the disclosed method, a portion of first substrate is removed from the second side of the first substrate. The first VIA is subsequently formed. The first VIA extends from the second side of the first substrate to the doped region. Further, the first connection structure is formed over the first VIA.

Additionally, a common source structure is formed over and coupled to the doped region. A bit line is formed over the common source structure, and the bit line is coupled to the common source structure through a second VIA. Moreover, a second connection structure is formed over the bit line. The second connection structure is coupled to the bit line through a third VIA. The first connection structure and the second connection structure are coupled to each other.

In the disclosed method, a transistor is formed over a first side of a second substrate. A bonding VIA is formed over the transistor. The bonding VIA is electrically coupled to the transistor. Further, the first substrate and the second substrate are bonded through the bonding VIA, where the second connection structure is aligned with the transistor, and coupled to the transistor through the bonding VIA.

In some embodiments, a Through Silicon Via (TSV) is formed that extends from the second side of the first substrate to the first side of the first substrate. The first connection structure and the second connection structure are electrically connected through the TSV. In some embodiments, a n+ region is formed between the first VIA and the doped region, and the doped region is n-type.

The present invention provides for a 3D-NAND memory and its manufacturing method. The 3D-NAND memory includes a transistor formed in a first side of a periphery circuit substrate, a memory cell stack formed over a first side of a cell array substrate, and a first connection structure formed over an opposing second side of the cell array substrate. The memory cell stack further includes a doped region formed in the first side of the cell array substrate. The doped region is coupled to the first connection structure through the first VIA that extends from the second side of the cell array substrate to the doped region. The memory cell stack also includes a common source structure that extends from the doped region toward the first side of the periphery circuit substrate and is coupled to the doped region. In the memory cell, a bit line is positioned between the common source structure and a second connection structure. The bit line is coupled to the common source structure through a second VIA. The second connection structure is coupled to the bit line through a third VIA, and the first side of the cell array substrate and the first side of a periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are in direct contact with each other, and may also include embodiments in which additional features are disposed formed between the first and second features, such that the first and second features may not be in direct contact.

<FIG> is a perspective view of a 3D-NAND memory device <NUM> and <FIG> is a cross-sectional view of the 3D-NAND memory device <NUM>. The cross-sectional view of the 3D-NAND memory device <NUM> in <FIG> is obtained from a line A-A' along a Y-direction (i.e., bit line direction) of the memory device <NUM> in <FIG>.

As shown in <FIG>, the memory device <NUM> can have a first substrate <NUM> that is suitable for complementary metal-oxide-semiconductor (CMOS) technology, and is referred to as CMOS substrate <NUM> or periphery circuit substrate <NUM>. Circuits in the CMOS technology are formed using p-type MOS (PMOS) transistors and n-type MOS (NMOS) transistors. In some examples, the PMOS transistors and NMOS transistors are collectively referred to as CMOS transistors. A plurality of CMOS transistors are formed over a top surface 10a of the CMOS substrate <NUM>. The CMOS transistors can form electric circuits to handle data I/O as well as memory cell operations of the memory device <NUM>. For example, as shown in <FIG>, a plurality of NMOS transistors <NUM> and a plurality of PMOS transistors <NUM> are formed on a top portion of the CMOS substrate <NUM>.

Further, a plurality of bonding VIAs <NUM> are formed over the CMOS transistors and electrically coupled to the CMOS transistors. For example, the bonding VIAs <NUM> can be electrically connected to gates, source regions, or drain regions of the CMOS transistors.

The memory device <NUM> further includes a second substrate <NUM> that is suitable for memory cells and is referred to as cell array substrate <NUM>. A memory cell stack can be formed over a top surface 18a of the cell array substrate <NUM>, and a plurality of bottom source lines <NUM> can be formed over an opposing bottom surface 18b of the cell array substrate <NUM>. In some examples, the bottom source lines <NUM> are connected to form a bottom source line mesh, and the bottom source line mesh can also be referred to as a bottom connection structure. The memory cell stack includes two or more n-well regions <NUM> (shown as 30a and 30b in <FIG>) that extend into the cell array substrate <NUM> from the top surface 18a. The n-well regions <NUM> are coupled to the bottom source lines <NUM> through a plurality of first VIAs <NUM> that extends from the bottom surface 18b of the cell array substrate <NUM> to the n-well regions <NUM>. Two or more array common source (ACS) structures <NUM> that extend from the n-well regions <NUM> toward the top surface 10a of the CMOS substrate <NUM> and are coupled to the n-well regions <NUM>. Each of the two or more n-well regions <NUM> can be in direct contact with a respective ACS structure.

A plurality of M1 routing lines <NUM> are positioned between the ACS structures <NUM> and a plurality of top source lines <NUM>. In some examples, the top source lines <NUM> are connected to form a top source line mesh, and the top source line mesh can also be referred to as a top connection structure. The M1 routing lines <NUM> are coupled to the ACS regions <NUM> through a plurality of second VIAs <NUM>. For example, as shown in <FIG>, an ACS structure 28a can connect to a M1 routing line <NUM> through a second VIA <NUM>. It should be mentioned that the M1 routing lines include a plurality of bit lines that are coupled to a plurality of channel structures <NUM>. The channel structures <NUM> are illustrated in <FIG>.

The top source lines <NUM> are formed over the M1 routing lines <NUM> and coupled to the M1 routing lines through a plurality of third VIAs <NUM>. For example, as shown in <FIG>, a top source line <NUM> is electrically connected to a M1 routing line <NUM> through a third VIA <NUM>. In the disclosed memory device <NUM>, the top surface 18a of the cell array substrate <NUM> and the top surface 10a of the CMOS substrate <NUM> are aligned facing each other so that the transistors are coupled to the top source lines <NUM> through the bonding VIAs <NUM>. As shown in <FIG>, a source line <NUM> is electrically connected to a PMOS transistor <NUM> through a bonding VIA <NUM>.

The cell array substrate <NUM> can include a p-well region <NUM> that is formed in a top region of the cell array substrate <NUM>, where the n-well regions <NUM> can be positioned in the p-well region <NUM>. The p-well region <NUM> can extend into the cell array substrate <NUM> from the top surface 18a with a depth from <NUM> to <NUM> according to the design requirements. The p-well is also known as 'active tub' since voltages are applied to the tub during erasing or programming the memory device <NUM>. The p-well can be also configured to isolate the memory cell stack from adjacent components.

As shown in <FIG>, a top source line <NUM> is electrically coupled to one or more CMOS transistors, such as one of the PMOS transistors <NUM>, through one or more bonding VIAs <NUM>. An M1 routing line <NUM> is electrically coupled to the top source line <NUM> through a third VIA <NUM>. The ACS structure 28a is electrically coupled to M1 routing line <NUM> through a second VIAs <NUM>. An n-well region 30a is in contact with an ACS structures 28a. The n-well regions <NUM> further extend into the cell array substrate <NUM> from the top surface 18a. The first VIAs <NUM> extend into the cell array substrate <NUM> from the bottom surface 18b to the n-well regions <NUM>. The bottom source lines <NUM> are formed over the first VIAs <NUM> and in direct contact with the first VIAs <NUM>.

As shown in <FIG>, the memory device <NUM> also includes the plurality of channel structures <NUM>. The channel structures <NUM> protrude from the top surface 18a of the cell array substrate <NUM> along a height direction (Z-direction) that are perpendicular to the cell array substrate <NUM>. In the memory device <NUM>, a plurality of word lines <NUM> are positioned over the top surface 18a of the cell array substrate18 with a staircase configuration, and are spaced apart from each other by a plurality of insulating layers <NUM>. The channel structures <NUM> extend through the plurality of word lines <NUM> and the plurality of the insulation layers <NUM>. The channel structures <NUM> are electrically coupled to M1 routing lines <NUM> through top channel contacts (not shown). In the <FIG> example, the M1 routing lines <NUM> that are connected to the channel structures <NUM> are configured as bit lines for the memory cell array, and can be referred to as bit lines <NUM>. The M1 routing lines <NUM> extend in a length direction (Y-direction) of the cell array substrate <NUM>. The ACS structures <NUM> extend through the plurality of word lines <NUM> and the plurality of insulating layers <NUM> along the height direction, and further extend in a width direction (X-direction) of the cell array substrate <NUM>. The plurality of the channel structures <NUM> are separated by the ACS regions <NUM>.

In some embodiments, the memory device <NUM> also includes a plurality of dummy channel structures <NUM>. The dummy channel structures <NUM> protrude from the top surface 18a of the cell array substrate <NUM> along the height direction of the cell array substrate <NUM>. Some of the dummy channel structures <NUM> can further extend through the word lines <NUM> and insulating layers <NUM>.

The ACS structures <NUM> have a top portion <NUM>' that is made of tungsten, and a bottom portion <NUM>'' that is made of polysilicon. The channel structures <NUM> can have a cylindrical shape with sidewalls and a bottom region. Of course, other shapes are possible. The channel structures <NUM> are formed along the height direction of the cell array substrate <NUM>, and electrically coupled with the cell array substrate <NUM> VIA bottom channel contacts <NUM> of the channel structures <NUM>. Each of the channel structures <NUM> further includes a respective channel layer, a respective tunneling layer, a respective charge trapping layer, and a respective barrier layer. For simplicity and clarity, the channel layer, tunneling layer, charge trapping layer, and barrier layer are not shown in <FIG>.

In some embodiments, the top source lines <NUM> and the bottom source lines <NUM> are electrically connected through one or more through silicon VIAs (TSVs) that are not shown in <FIG> and <FIG>.

In some embodiments, a plurality of spacer layers <NUM> are formed between the first VIAs <NUM> and the cell array substrate <NUM> in order to isolates the first VIAs <NUM> from the cell array substrate <NUM>. The spacer layers <NUM> can be a dielectric layer, such as a Tetraethyl orthosilicate (TEOS) layer. The first VIAs <NUM> can have an extended wall-shape that has a tapered cross section, a frustoconical shape, or other suitable shapes.

In some embodiments, a plurality of fourth VIAs (not shown) can be formed over the top source lines <NUM>. The fourth VIAs can be bonded with the bonding VIAs <NUM> subsequently so that the top source lines <NUM> are coupled to the transistors through the bonded fourth and bonding VIAs.

In some embodiments, a plurality of n+ regions (not shown) can be arranged between the first VIAs <NUM> and the n-well regions <NUM> to improve conductivity between the first VIAs <NUM> and the n-well regions <NUM>. Each of the n+ regions can be disposed between a respective first VIA and a respective n-well region <NUM>. The n-well regions <NUM> can be doped through an ion implantation process with phosphorus at a dopant concentration from 10e11 cm-<NUM> to 10e14 cm-<NUM>. The N+ regions can be doped with phosphorus at a dopant concentration from 10e14 cm-<NUM> to 10e18 cm-<NUM>.

In some embodiments, a dielectric layer <NUM> can be formed over the bottom surface 18b of the cell array wafer <NUM>, and the bottom source lines <NUM> are formed in the dielectric layer <NUM>. Further, an insulating layer (not shown) can be disposed between the bottom surface 18b of the cell array wafer <NUM> and the bottom source lines <NUM> so that the bottom source lines <NUM> are spaced apart from the cell array <NUM>. Accordingly, the second VIAs <NUM> can extend through the insulating layer, and further extend into the cell array wafer <NUM> from the bottom surface 18b.

The first VIAs <NUM> can be made of Cu, W, Ru, or other suitable material. In some embodiments, a barrier layer can be disposed between the first VIAs <NUM> and the spacer layers <NUM>. The barrier layer can be made of Ta, TaN, Ti, TiN, or other suitable materials. The top source lines <NUM> and the bottom source lines <NUM> can be made of Cu, Al, W, or other suitable materials.

It should be mentioned that <FIG> and <FIG> are merely exemplary embodiments of the disclosed 3D-NAND memory device <NUM>. The 3D-NAND memory device can include other components, structures, and dimensions according to different design requirements.

<FIG> is a schematic perspective view of a related 3D-NAND memory device <NUM> in three-dimensions, in accordance with exemplary embodiments of the disclosure. The memory device <NUM> has a CMOS substrate <NUM>. A plurality of CMOS transistors are formed over a top surface 70a of the CMOS substrate <NUM>. The CMOS transistors can include NMOS transistors <NUM> and PMOS transistors <NUM>. A plurality of bonding VIAs <NUM> are formed over the CMOS transistors and electrically coupled to the CMOS transistors. The bonding VIAs <NUM> can be electrically connected to source regions, drain regions, or gates of the CMOS transistors.

A cell array substrate <NUM> is positioned over the bonding VIAs <NUM>. Two or more n-well regions <NUM> are formed in the cell array substrate <NUM>. The n-well regions <NUM> extend into the cell array substrate <NUM> from a top surface 80a. In the cell array substrate <NUM>, a p-well region <NUM> is formed. The p-well region <NUM> is positioned in a top position of the cell array substrate <NUM>. Over the n-well regions <NUM>, two or more ACS structures <NUM> are formed. Each of the n-well regions <NUM> is in direct contact with a respective ACS structure <NUM>. Over the ACS structures <NUM>, a plurality of M1 VIAs <NUM> are formed. A plurality of M1 routing lines <NUM> are arranged over the ACS structures <NUM>. The M1 routing lines <NUM> are coupled to the ACS structures <NUM> through the M1 VIAs <NUM>.

In the memory device <NUM>, a plurality of M2 VIAs <NUM> are formed over the M1 routing lines <NUM>. Over the M2 VIAs <NUM>, a plurality of source lines (or a source line mesh) <NUM> are formed. The source lines <NUM> are electrically coupled to the M1 routing lines <NUM> through the M2 VIAs <NUM>. The memory device <NUM> further includes a plurality of channel regions <NUM>. The channel regions <NUM> protrude from the top surface 80a and extend along of a height direction (Z-direction) of the cell array substrate <NUM>. The channel structures <NUM> are positioned below the M1 routing lines <NUM> and electrically coupled to the M1 routing lines through top channel contacts (not shown). The M1 routing lines that are connected to the channel structures can be named as bit lines. Similar to the memory device <NUM>, the memory device <NUM> further includes a plurality of word lines (not shown in <FIG>) formed over the top surface 80a of the cell array substrate <NUM>. The word lines are spaced apart from each other by a plurality of insulating layers (not shown in <FIG>). The channel structures <NUM> extend through the word lines and the insulating layers. The ACS structures <NUM> also extend through the word lines and the insulating layers.

In some embodiments, the channel structures <NUM> and the n-well regions <NUM> can be electrically coupled to the CMOS transistors formed in the CMOS substrate <NUM> through the bonding VIAs <NUM>.

In the related 3D-NAND memory device <NUM>, an input voltage can be applied to the n-well regions <NUM> through a conductive channel that is formed by the source lines <NUM>, the M2 VIAs <NUM>, the M1 routing lines <NUM>, the M1 VIAs <NUM>, and the ACS structures <NUM>. The ACS structures <NUM> typically are wall-shaped line contacts along a word line direction (X-direction) of the cell array substrate <NUM>. Such a wall-shaped contact needs sufficient conductivity to prevent an arising ground noise during sensing operations. As the height of 3D NAND stacks increases with density, a height of the ACS structures also increases. The increased height of the ACS structures results in an increased resistance of the ACS structures. In order to reduce the amount of such resistance, a width of the ACS structures can be increased, which in turn impacts a die size and wafer mechanical stability due to high tungsten stress.

<FIG> are perspective and cross-sectional views of various intermediary steps of manufacturing the 3D-NAND memory device <NUM>, in accordance with exemplary embodiments of the disclosure.

<FIG> is a schematic perspective view of a memory cell stack that is formed over the cell array substrate <NUM>. The memory cell stack can be formed through a variety of semiconductor manufacturing processes. The semiconductor manufacturing processes can include a photolithography process, a dry etching process, a wet etching process, a wet clean process, an implantation process, a film deposition process (i.e., CVD, PVD, diffusion, electroplating), a surface planarization process (i.e., CMP), and other suitable semiconductor manufacturing processes. As shown in <FIG>, the memory stack can have a similar configuration that is illustrated in <FIG>. For example, the memory stack can includes the n-well regions <NUM> that extend from the top surface 18a into the cell array substrate <NUM>. The ACS structures <NUM> are formed over the n-well regions <NUM> and in contact with the n-well regions. The ACS regions <NUM> and the M1 routing lines <NUM> are electrically connected through the second VIAs <NUM>. The top source lines (source line mesh) <NUM> are electrically connected to the M1 routing lines <NUM> through the third VIAs <NUM>.

<FIG> is a cross-sectional view of the memory cell stack that has a similar configuration illustrated in <FIG>. The memory cells stack further includes the channel regions <NUM> and the dummy channel regions <NUM>. The channel regions <NUM> and dummy channel regions <NUM> protrude from the top surface 18a and extend along of the height direction of the cell array substrate <NUM>. The channel structures <NUM> are positioned below the M1 routing lines <NUM> and electrically coupled to the M1 routing lines <NUM> through the top channel contacts (not shown). The M1 routing lines that are connected to the channel structures can be named as bit lines. The memory cell stack further includes the word lines <NUM> formed over the top surface 18a of the cell array substrate <NUM>. The word lines <NUM> are spaced apart from each other by the insulating layer <NUM>. The channel structures <NUM> extend through the word lines <NUM> and the insulating layers <NUM>. The ACS structures <NUM> also extend through the word lines <NUM> and the insulating layers <NUM>.

In <FIG> and <FIG>, the memory cell stack can be flipped upside down and the bottom surface 18b of the cell array substrate <NUM> is exposed. A subsequent surface removal process, such as a CMP process, an etching process, or a combination thereof, can be applied to remove a portion of the cell array substrate <NUM> from the bottom surface 18b. After the surface removal process, the thickness of the cell array substrate <NUM> is reduced.

In <FIG> and <FIG>, the plurality of first VIAs <NUM> can be formed through a variety of semiconductor manufacturing processes that include a photolithography process, an etching process, a film deposition process (i.e., CVD, electroplating), and a surface planarization process. For example, a patterned mask layer can be formed over the bottom surface 18b of the cell array substrate <NUM> through the photolithography process. A dry etching process can transfer patterns in the mask layer into the cell array substrate to form a plurality of VIA openings. Based on the film deposition process, a spacer layer <NUM> can be deposited in the VIA openings and a conductive layer (i.e., Cu) can be formed over the spacer layer <NUM> to fill the VIA openings through an electroplating process. A subsequent surface planarization process, such as CMP, can be applied to remove excessive Cu over the bottom surface of the cell array substrate.

The conductive layer that remains in the VIA openings become the first VIAs <NUM>. The first VIAs <NUM> extend into the cell array substrate <NUM> from the bottom surface 18b and land on the n-well regions <NUM> so as to form electrical connection. The second VIAs <NUM> can be made of Cu, W, Ru, or the like. In some embodiments, a barrier layer (not shown) can be formed between the spacer layers <NUM> and the first VIAs <NUM>. The barrier layer can be made of Ti, TiN, TaN, Ta, or other suitable materials.

In some embodiments, a plurality of n+ regions can be formed at exposed area of the n-well regions when the n-well regions are exposed by the plurality of VIA openings. The n+ regions can be made by an ion implantation process. When the n+ regions are formed, the spacer layer <NUM>, and the conductive layer can be subsequently deposited in the VIA openings.

In <FIG> and <FIG>, the bottom source lines <NUM> can be formed over the bottom surface 18a of the cell array substrate <NUM>. In some embodiments, before the formation of the source lines <NUM>, a dielectric layer <NUM>, such as SiO, can be formed over the bottom surface 18a. A subsequent photolithography process can be applied to form trench openings in the dielectric layer <NUM>. A film deposition process can then be applied to fill the trench openings with conductive material, such as Cu, Al, W, or the like. A subsequent CMP process can be applied to remove excessive the conduction material over a top surface of the dielectric layer <NUM>. The conductive material that remains in the trench openings form the bottom source lines <NUM>.

In <FIG>, the plurality of CMOS transistors, such as PMOS <NUM> and NMOS <NUM>, can be formed over the top surface 10a of the CMOS substrate <NUM>. The plurality of bonding VIAs <NUM> can be formed over the CMOS transistors. Subsequently, the cell array substrate <NUM> and the CMOS substrate <NUM> can be bonded together through the bonding VIAs <NUM>. The top surface 10a of the CMOS substrate <NUM> and the top surface 18a of the cell array substrate <NUM> are aligned facing each other so that the transistors are coupled to the top source lines <NUM> through the bonding VIAs <NUM>. After manufacturing steps shown in <FIG>, the 3D-NAND memory device <NUM> is formed, which has a same configuration as the memory device shown in <FIG> and <FIG>.

In some embodiments, the fourth VIAs (not shown) are formed over the top source lines <NUM>, and the fourth VIAs are connected to the bonding VIAs <NUM> so that the cell array substrate <NUM> and the CMOS substrate <NUM> are bonded together.

A plurality of TSVs (not shown) can also be formed. The TSVs can extend into the cell array substrate <NUM> from the bottom surface 18b of the cell array substrate <NUM>, and connect the top source lines <NUM> and bottom source lines <NUM>.

<FIG> is a flowchart of an exemplary process for manufacturing the 3D-NAND memory device <NUM>, in accordance with embodiments of the disclosure. The process <NUM> begins at step <NUM> where a memory cell stack can be formed over a top surface of a first substrate. The first substrate further has an opposing bottom surface. The memory cell stack includes two or more n-well regions formed in the first substrate. The two or more n-well regions extend into the first substrate from the top surface. The memory stack can also include two or more ACS structures formed over the two or more n-well regions. Each of the ACS structures is in direct contact with a respective n-well region. In the memory cell stack, a plurality of M1 routing lines are formed over the ACS structures. The M1 routing lines are electrically coupled to the ACS structures through a plurality of M1 VIAs. Further, a plurality of top source lines formed over the plurality of M1 routing lines. The M1 routing lines are electrically coupled to the top source lines through a plurality of M2 VIAs. In some embodiments, step <NUM> can be performed as illustrated with reference to <FIG>.

The process <NUM> then proceeds to step <NUM> where a portion of the first substrate can be removed from the bottom surface of the first substrate. The bottom portion of the first substrate can be removed through an etching process, a CMP process, or the like, or a combination thereof. In some embodiments, step <NUM> can be performed as illustrated with reference to <FIG>.

In step <NUM>, a plurality of VIA contacts can be formed that extend into the first substrate from the bottom surface to contact the n-well regions. A plurality of bottom source lines can be formed over the VIA contacts. The plurality of bottom source lines are electrically connected to the n-well regions through the VIA contacts. In some embodiments, step <NUM> can be performed as illustrate with reference to <FIG>.

The process <NUM> proceeds to step <NUM> where a plurality of transistors are formed over a top surface of a second substrate, a plurality of bonding VIAs are formed over the transistors. Further, the first substrate and the second substrate are bonded together through the bonding VIAs. The top surface of the first substrate and the top surface of the second substrates are aligned facing each other so that the transistors are coupled to the top source lines through the bonding VIAs. In some embodiments, step <NUM> can be performed as illustrate with reference to <FIG>.

It should be noted that additional steps can be provided before, during, and after the process <NUM>, and some of the steps described can be replaced, eliminated, or performed in different order for additional embodiments of the process <NUM>. In subsequent process steps, various additional interconnect structures (e.g., metallization layers having conductive lines and/or VIAs) may be formed over the semiconductor device <NUM>. Such interconnect structures electrically connect the semiconductor device <NUM> with other contact structures and/or active devices to form functional circuits. Additional device features such as passivation layers, input/output structures, and the like may also be formed.

The various embodiments described herein offer several advantages over related memory devices. In the related memory devices, an input voltage is applied to a n-well region through a conductive channel that is formed by a source line, a M1 routing line, an ACS structure, and the n-well region. A resistance of the conductive channel is inevitably affected by a resistance of the ACS structure. As a height of a 3D NAND stack increases with density, a height of the ACS region accordingly grows. The resistance of the ACS region inevitably increases in the height direction of the 3D NAND stack. The increased resistance of the ACS region results in an elevated resistance of the conductive channel. The elevated resistance of the conductive channel accordingly can cause ground noise arising in sensing operations of the related memory devices.

In the disclosed memory device, by introducing a cross-point structure, the source lines (or source line mesh) can be electrically coupled to the n-well regions from a polished backside (i.e., the bottom surface) of the cell array substrate. Accordingly, a resistance of source lines to n-well regions can be decreased. The decreased resistance of source lines to n-well regions can reduce the ground noise. In addition, the resistance of the ACS structures does not impact a source side resistance of the memory device and the ground noise. Further, the disclosed structure can eliminate gaps between M1 routing lines that are used to add contacts to connect the source line mesh and the ACS structures, which in turn helps a reduction of die size in a word line direction.

Claim 1:
A 3D-NAND memory device (<NUM>), comprising:
a first substrate (<NUM>) having a first side on which a memory stack is formed and a second side that is opposite to the first side;
a doped region formed in the first side of the first substrate (<NUM>) and electrically coupled to at least a source terminal of a memory transistor formed on the first side of the first substrate (<NUM>);
a first connection structure formed over the second side of the first substrate (<NUM>) and coupled to the doped region through a first VIA (<NUM>, <NUM>), the first VIA (<NUM>, <NUM>) extending from the second side of the first substrate (<NUM>) to the doped region;
a common source structure (<NUM>) formed over and coupled to the doped region, wherein the common source structure (<NUM>) comprises a top portion (<NUM>') that is made of tungsten and a bottom portion (<NUM>") that is made of polysilicon;
a bit line formed over the common source structure (<NUM>) that is coupled to the common source structure (<NUM>) through a second VIA;
a second connection structure positioned over the bit line that is coupled to the bit line through a third VIA (<NUM>), the first connection structure and the second connection structure being coupled to each other
a plurality of channel structures (<NUM>, <NUM>) extending from the first side of the first substrate (<NUM>); and
a plurality of word lines (<NUM>) positioned over the first side of the first substrate (<NUM>) in a staircase configuration, wherein:
the plurality of the word lines (<NUM>) are spaced apart from each other by a plurality of insulating layers (<NUM>),
the plurality of channel structures (<NUM>, <NUM>) extend through the plurality of word lines and the plurality of the insulation layers,
the plurality of channel structures (<NUM>, <NUM>) are disposed below the bit line, and
the common source structure extends through the plurality of word lines and the plurality of insulating layers (<NUM>) and separates the plurality of the channel structures (<NUM>, <NUM>).