Patent Description:
As known in the art, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is a non-volatile memory that has come under much scrutiny recently in the industry, which has several advantages over the conventional magnetoresistive random access memory. For example, these advantages include higher endurance, lower-power consumption, and faster operating speed.

In a magneto-tunnel junction (MTJ) including two ferromagnetic layers having a thin insulating layer therebetween, the tunnel resistance varies depending on the relative directions of magnetization of the two ferromagnetic layers. A magnetoresistive random access memory may be a semiconductor device where magnetic elements (MTJ elements) having MTJs utilizing a tunnel magneto resistance (TMR) effect are arranged in a matrix form as a memory cell.

In conventional designs, the source lines (SL) of the MTJ bit cell arrays are arranged to be parallel to the bit line (BL). However, in conventional designs there is no direct and parallel overlap between the source line and bit line due to via and metal spacing rules. Therefore, the minimum bit cell size of conventional designs cannot be reduced or minimized as a result of metal and via spacing rules.

Because the memory includes hundreds of thousands of cells, even small area savings in each cell can result in major advantages in density of the memory. Accordingly, it is highly desirable to provide apparatus and a method of improving the density of MRAM cells in a memory array by reducing the area of individual MRAM cells.

<CIT> discloses a One-Time Programmable (OTP) memory built in at least one of semiconductor fin structures. An OTP cell has fins running vertically and gates running horizontally. A layer defines an active area. The fins have the gates across to divide the fins into drain and source regions, respectively, which are further covered by an N+-implant to construct NMOS devices. The sources or drains of the MOS device formed by the fins and gates can be coupled together by using extended sources/drains (S/D).

The present invention provides an improved magnetic memory device having a shared source line (SL) and a shared bit line (BL), which can solve the shortcomings of the prior art.

One aspect of the invention provides a memory device including a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction, wherein the main source line is electrically connected to the source doped region via the source line extension; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region.

The data storage element comprises a magnetic tunneling junction (MTJ) element. The memory device further includes a landing pad disposed directly under the MTJ element. The memory device further includes a drain contact electrically connecting the landing pad to the drain doped region, a first dielectric layer disposed on the substrate, wherein the landing pad is disposed in the first dielectric layer and is situated in a first horizontal plane; and a second dielectric layer covering the first dielectric layer and the landing pad, wherein the MTJ element is disposed in the second dielectric layer, and wherein the main source line and the source line extension are situated in a second horizontal plane.

According to some embodiments, the bottom electrode is electrically connected to the landing pad.

According to some embodiments, the MTJ element comprises a top electrode.

According to some embodiments, the top electrode is electrically connected to a bit line.

According to some embodiments, the bit line extends along the first direction.

According to some embodiments, the second horizontal plane is lower than the first horizontal plane.

Another aspect of the invention provides a magnetic memory device including a substrate; an active area extending along a first direction on the substrate; an isolation region disposed in the substrate and adjacent to the active area; a plurality of gate lines traversing the active area and the isolation region along a second direction that is not parallel to the first direction, wherein the plurality of gate lines comprises a first gate line, a second gate line, and a third gate line between the first gate line and the second gate line; a first source doped region in the active area and on one side of the first gate line; a first drain doped region in the active area and between the first gate line and the third gate line; a second source doped region in the active area and on one side of the second gate line; a second drain doped region in the active area and between the second gate line and the third gate line; a main source line extending along the first direction overlying the isolation region; a first source line extension and a second source line extension coupled to the main source line and extending along the second direction, wherein the man source line is electrically connected to the first source doped region and the second source doped region via the first source line extension and the second source line extension, respectively; a first magnetic tunneling junction (MTJ) element electrically coupled to the first drain doped region; and a second MTJ element electrically coupled to the second drain doped region. a first landing pad and a second landing pad disposed directly under the first MTJ element and the second MTJ element, respectively, and wherein the first MTJ element comprises a first bottom electrode and the second MTJ element comprises a second bottom electrode.

According to some embodiments, the first MTJ element and the second MTJ element are aligned along the first direction.

According to some embodiments, the first MTJ element and the second MTJ element are not aligned along the first direction.

According to some embodiments, the first MTJ element comprises a first top electrode and the second MTJ element comprises a second top electrode.

According to some embodiments, the first top electrode and the second top electrode are electrically connected to a bit line.

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

Please refer to <FIG> and <FIG>, wherein <FIG> is a schematic diagram of a partial layout of a magnetic memory device <NUM> according to an embodiment of the invention, and <FIG> is a cross-sectional view taken along line I-I' in <FIG>. According to an embodiment of the present invention, as shown in <FIG> and <FIG>, the magnetic memory device <NUM> includes a substrate <NUM>, for example, a P-type silicon substrate, but it is not limited thereto. According to an embodiment of the present invention, a P-well (PW) may be provided in the substrate <NUM>, but is not limited thereto. The substrate <NUM> has a memory array area MA. In the memory array area MA on the substrate <NUM>, memory cells <NUM> arranged in an array are provided. On the substrate <NUM>, there are a plurality of strip-shaped and mutually parallel active areas <NUM> (<FIG> only shows one active area <NUM>). The strip-shaped active areas <NUM> are isolated from one another by the strip-shaped shallow trench isolation (STI) region <NUM> (<FIG> only shows one STI region <NUM>). According to an embodiment of the present invention, the strip-shaped active area <NUM> and the strip-shaped STI area <NUM> both extend along a first direction (for example, the reference X-axis direction).

According to an embodiment of the present invention, there are a plurality of gate lines or word lines on the substrate <NUM> (only two word lines WL<NUM> and WL<NUM> are shown in <FIG>), which traverse the active area <NUM> and extend in a second direction (for example, the reference Y-axis direction) that is not parallel to the first direction. For example, the first direction is orthogonal to the second direction. According to an embodiment of the present invention, the word lines WL<NUM> and WL<NUM> may be polysilicon word lines, but not limited thereto. According to an embodiment of the present invention, the magnetic memory device <NUM> further includes a selection transistor <NUM> located at a position where the word line WL<NUM> crosses the active area <NUM>, for example. According to an embodiment of the present invention, the selection transistor <NUM> may include a gate G, a drain doped region D, and a source doped region S. For example, the overlapping portion of the word line WL<NUM> and the active area <NUM> is the gate G of the selection transistor <NUM>.

According to an embodiment of the present invention, the drain doped region D and the source doped region S are formed in the active areas <NUM> on two opposite sides of the gate G, respectively. For example, the drain doped region D and the source doped region S may be N-type doped regions or P-type doped regions. The source doped region S is provided on the first side of the gate line WL<NUM>. The drain doped region D is disposed on the second side of the gate line WL<NUM> opposite to the first side.

As shown in <FIG>, dielectric layers <NUM>-<NUM> are provided on the substrate <NUM>, but not limited thereto. For example, the dielectric layer <NUM> may be an ultra-low dielectric constant (ultra-low k) material layer. For example, the ultra-low k material layer may be a carbon-containing silicon oxide (SiOC) layer having a dielectric constant ranging from <NUM> to <NUM>, but is not limited thereto. According to an embodiment of the present invention, the dielectric layer <NUM> may be composed of a single layer of insulating material or multiple layers of insulating film. The dielectric layer <NUM> covers the memory array area MA and the selection transistor <NUM>. According to an embodiment of the invention, the dielectric layer <NUM> covers the dielectric layer <NUM>. For example, the dielectric layer <NUM> may include a nitrogen-doped silicon carbide (NDC) layer <NUM>, a silicon oxide layer <NUM> on the NDC layer <NUM>, and an ultra-low k material layer <NUM> on the silicon oxide layer <NUM>. For example, the silicon oxide layer <NUM> may be a TEOS silicon oxide layer. The TEOS silicon oxide layer refers to a silicon oxide layer deposited using tetraethoxysilane (TEOS) as a reactive gas.

According to an embodiment of the present invention, a dielectric layer <NUM> and a dielectric layer <NUM> may be formed on the dielectric layer <NUM>. The dielectric layer <NUM> may include, for example, a NDC layer <NUM> and an ultra-low k material layer <NUM>. The dielectric layer <NUM> may include, for example, a NDC layer <NUM> and an ultra-low k material layer <NUM>.

As shown in <FIG> and <FIG>, the magnetic memory device <NUM> further includes a landing pad MP<NUM>. The landing pad MP<NUM> overlaps the drain doped region D of the selection transistor <NUM>. In addition, the landing pad MP<NUM> may partially overlap the word line WL<NUM>. According to an embodiment of the invention, the landing pad MP<NUM> is disposed in the dielectric layer <NUM>.

According to an embodiment of the present invention, as shown in <FIG>, the landing pad MP<NUM> is located at a first horizontal plane and is electrically connected to the drain doped region D of the selection transistor <NUM>. According to an embodiment of the invention, the landing pad MP<NUM> is located in a first metal (M1) layer. According to an embodiment of the invention, the first metal layer is a damascene copper layer. The landing pad MP<NUM> may be electrically coupled to the drain doped region D of the selection transistor <NUM> via a contact plug (drain contact) C<NUM>. For example, the contact plug C<NUM> may be a tungsten metal plug. According to an embodiment of the present invention, between the landing pad MP<NUM> and the contact plug C<NUM>, a contact pad CP<NUM> may be further provided. The contact pad CP<NUM> may be a tungsten metal contact pad, and may be formed in the zeroth metal (M0) layer.

The magnetic memory device <NUM> further includes a data storage element, for example, cylindrical memory stack MS<NUM>. The cylindrical memory stack MS<NUM> may be arranged in an array, and the cylindrical memory stack MS<NUM> is aligned with the landing pad MP<NUM>. According to an embodiment of the present invention, <FIG> illustrates the via plug VP<NUM> disposed in the silicon oxide layer <NUM> and the NDC layer <NUM>. According to an embodiment of the present invention, <FIG> further illustrates a cylindrical memory stack MS<NUM> provided in the second dielectric layer <NUM>. According to an embodiment of the present invention, the cylindrical memory stack MS<NUM> may include a bottom electrode BE<NUM> electrically coupled to the landing pad MP<NUM> through the via plug VP<NUM>, and a top electrode TE<NUM> electrically coupled to the bit line BL<NUM> in the third dielectric layer <NUM> through the via V<NUM>.

According to an embodiment of the present invention, as shown in <FIG>, the via plug VP<NUM> is electrically connected to the bottom electrode BE<NUM> and the landing pad MP<NUM>. According to an embodiment of the present invention, the via plug VP<NUM> may be a tungsten via plug, but is not limited thereto. According to an embodiment of the present invention, the bit line BL<NUM> and the via V<NUM> may be a dual damascene copper metal structure formed in the third dielectric layer <NUM>.

As shown in <FIG>, the cylindrical memory stack MS<NUM> may include a magnetic tunnel junction element MTJ<NUM>. According to an embodiment of the present invention, a spacer SP<NUM> may be provided on the sidewall of the cylindrical memory stack MS<NUM>. According to an embodiment of the present invention, for example, the spacer SP<NUM> may be a silicon nitride spacer, but is not limited thereto.

According to an embodiment of the present invention, the bottom electrode BE<NUM> may include, for example, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), etc. The multi-layer structure of the magnetic tunnel junction element MTJ<NUM> is a well-known technique, so its details are omitted. For example, the magnetic tunnel junction element MTJ<NUM> may include a fixed layer, a free layer, and a capping layer, but not limited thereto. The fixed layer may be made of antiferromagnetic (AFM) materials, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the direction of the magnetic moment of adjacent layers. The free layer may be composed of a ferromagnetic material, such as iron, cobalt, nickel or alloys thereof such as cobalt-iron-boron (CoFeB), but it is not limited thereto. According to an embodiment of the present invention, for example, the top electrode TE<NUM> may include a ruthenium (Ru) metal layer and a tantalum (Ta) metal layer, but is not limited thereto.

<FIG> illustrates a bit line BL<NUM> extending along the reference X axis. According to an embodiment of the present invention, as shown in <FIG>, the bit line BL<NUM> partially overlaps the underlying strip-shaped active area <NUM>. According to an embodiment of the present invention, the bit line BL<NUM> may be formed in an upper metal interconnection, for example, a second metal (M2) layer or a third metal (M3) layer.

As shown in <FIG> and <FIG>, a main source line SLM<NUM> extending along the reference X axis direction and a source line extension SLE<NUM> extending along the reference Y axis direction are provided on the substrate <NUM>. The source line extension SLE<NUM> is coupled to the main source line SLM<NUM>. The extension direction of the source line extension SLE<NUM> is parallel to the word line WL<NUM> and orthogonal to the main source line SLM<NUM> and the bit line BL<NUM>. As shown in <FIG>, the source line extension SLE<NUM> is disposed between the word lines WL<NUM> and WL<NUM>. As shown in <FIG>, the illustrated source line extension SLE<NUM> is disposed in the first dielectric layer <NUM>. The main source line SLM<NUM> is electrically connected to the source doped region S via the source line extension SLE<NUM>.

According to an embodiment of the present invention, the illustrated main source line SLM<NUM> and source line extension SLE<NUM> may be located at a second horizontal plane. According to an embodiment of the present invention, for example, the second horizontal plane may be lower than the first horizontal plane. In other words, the source line extension SLE<NUM> as illustrated in <FIG> is lower than the landing pad MP<NUM>. According to an embodiment of the present invention, the source line extension SLE<NUM> illustrated in <FIG> may be located in the M0 metal layer. According to an embodiment of the present invention, the M0 metal layer may be a tungsten metal layer.

Please refer to <FIG> and <FIG>. <FIG> is a schematic diagram showing a partial layout of a magnetic memory device 1a according to another embodiment of the invention. <FIG> is a cross-sectional view taken along line II-II' in <FIG>. According to an embodiment of the present invention, as shown in <FIG> and <FIG>, the magnetic memory device 1a includes a substrate <NUM>, for example, a P-type silicon substrate, but is not limited thereto. According to an embodiment of the present invention, a P-well (PW) may be provided in the substrate <NUM>, but is not limited thereto. The substrate <NUM> has a memory array area MA. In the memory array area MA on the substrate <NUM>, a plurality of memory cells 100a, 100b arranged in an array are provided. The substrate <NUM> comprises a plurality of strip-shaped and mutually parallel active areas <NUM> (only one active area <NUM> is shown in <FIG>), which are isolated from one another by STI regions <NUM> (only one STI region <NUM> is shown in <FIG>). According to an embodiment of the present invention, the strip-shaped active area <NUM> and the strip-shaped STI region <NUM> both extend along a first direction (for example, the reference X-axis direction).

According to an embodiment of the present invention, gate lines or word lines are disposed on the substrate <NUM> (only three word lines WL<NUM>, WL<NUM>, WL<NUM> are shown in <FIG>), traversing the active area <NUM> and extending along a second direction (for example, the reference Y-axis direction) not parallel to the first direction. For example, the first direction is orthogonal to the second direction. According to an embodiment of the present invention, the word lines WL<NUM>, WL<NUM>, and WL<NUM> may be polysilicon word lines, but not limited thereto. According to an embodiment of the present invention, the magnetic memory device 1a further includes selection transistors 200a and 200b. For example, the selection transistor 200a is located at a position where the word line WL<NUM> crosses the active area <NUM>, and the selection transistor 200b is located at a position where the word line WL<NUM> crosses the active area <NUM>.

According to an embodiment of the present invention, the selection transistor 200a may include a gate G<NUM>, a drain doped region D<NUM>, and a source doped region S<NUM>. For example, the portion where the word line WL<NUM> overlaps the active area <NUM> is the gate G<NUM> of the selection transistor 200a. According to an embodiment of the present invention, the selection transistor 200b may include a gate G<NUM>, a drain doped region D<NUM>, and a source doped region S<NUM>. For example, the portion where the word line WL<NUM> overlaps the active area <NUM> is the gate G<NUM> of the selection transistor 200b.

According to an embodiment of the present invention, the drain doped region D<NUM> and the source doped region S<NUM> are formed in the active areas <NUM> on two sides of the gate G<NUM>. For example, the drain doped region D<NUM> and the source doped region S<NUM> may be N-type doped regions or P-type doped regions. The source doped region S<NUM> is disposed on the first side of the word line WL<NUM>. The drain doped region D<NUM> is disposed on the second side of the word line WL<NUM> opposite to the first side.

According to embodiments of the present invention, the drain doped region D<NUM> and the source doped region S<NUM> are formed in the active areas <NUM> on two sides of the gate G<NUM>. For example, the drain doped region D<NUM> and the source doped region S<NUM> may be N-type doped regions or P-type doped regions. The source doped region S<NUM> is disposed on the first side of the word line WL<NUM>. The drain doped region D<NUM> is disposed on the second side of the word line WL<NUM> opposite to the first side.

As shown in <FIG>, dielectric layers <NUM>-<NUM> are provided on the substrate <NUM>, but not limited thereto. For example, the dielectric layer <NUM> may be an ultra-low k material layer. For example, the ultra-low k material layer may be a carbon-containing silicon oxide layer having a dielectric constant ranging from <NUM> to <NUM>, but not limited thereto. According to an embodiment of the present invention, the dielectric layer <NUM> may be composed of a single layer of insulating material or multiple layers of insulating film. The dielectric layer <NUM> covers the memory array area MA and the selection transistors 200a and 200b. According to an embodiment of the invention, the dielectric layer <NUM> covers the dielectric layer <NUM>. For example, the dielectric layer <NUM> may include a NDC layer <NUM>, a silicon oxide layer <NUM> on the NDC layer <NUM>, and an ultra-low k material layer <NUM> on the silicon oxide layer <NUM>. For example, the silicon oxide layer <NUM> may be a TEOS silicon oxide layer. The TEOS silicon oxide layer refers to a silicon oxide layer deposited using tetraethoxysilane as a reactive gas.

According to an embodiment of the present invention, a dielectric layer <NUM> and a dielectric layer <NUM> may be formed on the dielectric layer <NUM>. The dielectric layer <NUM> may include, for example, a NDC layer <NUM> and an ultra-low k material layer <NUM>, The dielectric layer <NUM> may include, for example, a NDC layer <NUM> and an ultra-low k material layer <NUM>.

As shown in <FIG> and <FIG>, the magnetic memory device 1a further includes landing pads MP<NUM> and MP<NUM>. The landing pad MP<NUM> overlaps the drain doped region D<NUM> of the selection transistor 200a, and the landing pad MP<NUM> overlaps the drain doped region D<NUM> of the selection transistor 200b. According to the embodiment of the invention, the landing pads MP<NUM> and MP<NUM> are disposed in the dielectric layer <NUM>.

According to an embodiment of the present invention, as shown in <FIG>, the landing pad MP<NUM> is located at a first horizontal plane and is electrically connected to the drain doped region D<NUM> of the selection transistor 200a, and the landing pad MP<NUM> is located at the first horizontal plane and is electrically connected to the drain doped region D<NUM> of the selection transistor 200b. According to an embodiment of the invention, the landing pads MP<NUM> and MP<NUM> are located in the M1 metal layer. According to an embodiment of the invention, the M1 metal layer is a damascene copper layer. The landing pads MP<NUM>, MP<NUM> may be electrically coupled to the drain doped regions D<NUM>, D<NUM> of the transistors 200a, 200b via contact plugs (drain contacts) C<NUM>, C<NUM>, respectively. For example, the contact plugs C<NUM> and C<NUM> may be tungsten metal plugs. According to the embodiment of the present invention, a contact pad CP<NUM> may be further provided between the landing pad MP<NUM> and the contact plug C<NUM>, and a contact pad CP<NUM> may be further provided between the landing pad MP<NUM> and the contact plug C<NUM>. The contact pads CP<NUM> and CP<NUM> may be tungsten metal contact pads, and may be formed in the M0 metal layer.

The magnetic memory device 1a further includes data storage elements, for example, cylindrical memory stacks MS<NUM>, MS<NUM>. The cylindrical memory stacks MS<NUM>, MS<NUM> can be arranged in an array. The cylindrical memory stack MS<NUM> is aligned with the landing pad MP<NUM>. The memory stack MS<NUM> is aligned with the landing pad MP<NUM>. According to an embodiment of the present invention, <FIG> illustrates the via plugs VP<NUM> and VP<NUM> disposed in the silicon oxide layer <NUM> and the NDC layer <NUM>. According to an embodiment of the present invention, <FIG> further illustrates cylindrical memory stacks MS<NUM> and MS<NUM> provided in the second dielectric layer <NUM>. According to an embodiment of the present invention, the cylindrical memory stack MS<NUM> may include a bottom electrode BE<NUM> electrically coupled to the landing pad MP<NUM> through the via plug VP<NUM>, and a top electrode TE<NUM> electrically coupled to the bit line BL<NUM> in the third dielectric layer <NUM> through the via V<NUM>. According to an embodiment of the present invention, the cylindrical memory stack MS<NUM> may include a bottom electrode BE<NUM> electrically coupled to the landing pad MP<NUM> through the via plug VP<NUM>, and a top electrode TE<NUM> electrically coupled to the bit line BL<NUM> in the third dielectric layer <NUM> through the via V<NUM>.

According to an embodiment of the present invention, as shown in <FIG>, the via plug VP<NUM> is electrically connected to the bottom electrode BE<NUM> and the landing pad MP<NUM>, and the via plug VP<NUM> is electrically connected to the bottom electrode BE<NUM> and the landing pad MP<NUM>. According to an embodiment of the present invention, the via plug VP<NUM> may be a tungsten metal via plug, but is not limited thereto. According to an embodiment of the present invention, the bit line BL<NUM> and the vias V<NUM> and V<NUM> may be composed of a dual damascene copper metal structure formed in the third dielectric layer <NUM>.

As shown in <FIG>, the cylindrical memory stacks MS<NUM>, MS<NUM> may respectively include a magnetic tunnel junction element MTJ<NUM>, MTJ<NUM>. The magnetic tunnel junction elements MTJ<NUM> and MTJ<NUM> are aligned along the first direction. In some embodiments, the magnetic tunnel junction elements MTJ<NUM> and MTJ<NUM> may not be aligned along the first direction. According to an embodiment of the present invention, a spacer SP<NUM> may be provided on the sidewall of the cylindrical memory stack MS<NUM>, and a spacer SP<NUM> may be provided on the sidewall of the cylindrical memory stack MS<NUM>. According to an embodiment of the present invention, for example, the spacers SP<NUM> and SP<NUM> may be silicon nitride spacers, but not limited thereto.

According to embodiments of the present invention, the bottom electrodes BE<NUM>, BE<NUM> may include, for example, but not limited to, Ta, Pt, Cu, Au, Al, or the like. The multi-layer structure of the magnetic tunnel junction elements MTJ<NUM> and MTJ<NUM> is a well-known technique, so the details are omitted. For example, the magnetic tunnel junction element MTJ<NUM> may include a fixed layer, a free layer, and a capping layer, but not limited thereto. The fixed layer may be composed of antiferromagnetic materials, such as iron manganese, platinum manganese, iridium manganese, nickel oxide, etc., to fix or limit the direction of the magnetic moment of the adjacent layers. The free layer may be composed of a ferromagnetic material, such as iron, cobalt, nickel or alloys thereof such as cobalt iron boron, but not limited thereto. According to an embodiment of the present invention, for example, the top electrodes TE<NUM> and TE<NUM> may include a ruthenium metal layer and a tantalum metal layer, but not limited thereto.

<FIG> illustrates a bit line BL<NUM> extending along the reference X axis. According to an embodiment of the present invention, as shown in <FIG>, the bit line BL<NUM> partially overlaps the strip-shaped active area <NUM> below. According to an embodiment of the present invention, the bit line BL<NUM> may be formed in an upper metal interconnection, for example, the M2 metal layer or the M3 metal layer.

As shown in <FIG> and <FIG>, a main source line SLM<NUM> extending along the reference X-axis direction directly above the STI region <NUM> and source line extensions SLE<NUM>, SLE<NUM> extending along the reference Y-axis direction are provided on the substrate <NUM>. The source line extensions SLE<NUM>, SLE<NUM> are coupled to the main source line SLM<NUM>. The extension directions of the source line extensions SLE<NUM> and SLE<NUM> are parallel to the word line WL<NUM> and orthogonal to the main source line SLM<NUM> and the bit line BL<NUM>. As shown in <FIG>, the source line extension SLE<NUM> is provided on one side of the word line WL<NUM>. As shown in <FIG>, the illustrated source line extensions SLE<NUM> and SLE<NUM> are provided in the first dielectric layer <NUM>. The main source line SLM<NUM> is electrically connected to the source doped regions S<NUM>, S<NUM> via source line extensions SLE<NUM>, SLE<NUM>.

According to an embodiment of the present invention, the illustrated main source line SLM<NUM> and source line extensions SLE<NUM>, SLE<NUM> may be located at a second horizontal plane. According to an embodiment of the present invention, for example, the second horizontal plane may be lower than the first horizontal plane. In other words, the source line extensions SLE<NUM>, SLE<NUM> as illustrated in <FIG> are lower than the landing pads MP<NUM>, MP<NUM>. According to an embodiment of the present invention, the source line extensions SLE<NUM> and SLE<NUM> illustrated in <FIG> may be located in the M0 metal layer. According to an embodiment of the present invention, the M0 metal layer may be a tungsten metal layer.

Please refer to <FIG> and <FIG>. <FIG> is a schematic diagram of a partial layout of a magnetic memory device 1c according to another embodiment of the present invention, illustrating part of the shared source lines. <FIG> is a layout diagram showing part of bit lines of the magnetic memory device 1c in <FIG>.

As shown in <FIG> and <FIG>, likewise, strip-shaped and mutually parallel active areas 101a, 101b are provided in the memory array area MA, and are separated from one another by strip-shaped STI regions <NUM>. Two adjacent active areas 101a are grouped into the first group, and two adjacent active areas 101b are grouped into the second group. Therefore, there are multiple groups of active areas in the memory array area MA. According to an embodiment of the present invention, the strip-shaped active areas 101a, 101b and the strip-shaped STI region <NUM> both extend along the first direction (for example, the reference X-axis direction).

According to an embodiment of the present invention, the magnetic memory device 1c further includes multiple gate lines or word lines WL<NUM>~WL<NUM>, traversing the active areas 101a, 101b and extending along the second direction (for example, reference Y-axis direction) that is not parallel to the first direction. For example, the first direction is orthogonal to the second direction. According to an embodiment of the present invention, the word lines WL<NUM>~WL<NUM> may be polysilicon word lines, but not limited thereto.

At predetermined positions on the active areas 101a and 101b, a landing pad MP at a first horizontal plane and a data storage element containing a magnetic tunnel junction element MTJ (as described in <FIG>) are provided and electrically connected to the corresponding drain doped region D of the selection transistor <NUM>. Above the active area 101a of the first group, the magnetic memory device 1c further includes a main source line SLM<NUM> extending along the reference X-axis direction, and source line extensions SLE1a~SLE1c extending along the reference Y-axis direction. The source line extensions SLE1a~SLE1c are coupled to the main source line SLM<NUM>. The extension directions of the source line extensions SLE1a ~SLE1c are parallel to the word line WL<NUM> ~WL<NUM> and orthogonal to the main source line SLM<NUM>. The main source line SLM<NUM> is electrically connected to the source doped regions S of the selection transistors <NUM> provided on the active area 101a of the first group via source line extensions SLE1a ~SLE1c.

Similarly, above the active area 101b of the second group, the magnetic memory device 1c further includes a main source line SLM<NUM> extending along the reference X-axis direction, and source line extensions SLE2a~SLE2c extending along the reference Y-axis direction. The source line extensions SLE2a~SLE2c are coupled to the main source line SLM<NUM>. The extension directions of the source line extensions SLE2a~SLE2c are parallel to the word line WL<NUM>~WL<NUM> and orthogonal to the main source line SLM<NUM>. The main source line SLM<NUM> is electrically connected to the source doped regions S of the selection transistors <NUM> provided on the active area 101b of the second group via source line extensions SLE2a ~SLE2c.

According to an embodiment of the present invention, the illustrated main source lines SLM<NUM>, SLM<NUM> and source line extensions SLE1a~SLE1c, SLE2a~SLE2c may be located at the second horizontal plane. According to an embodiment of the present invention, for example, the second horizontal plane may be lower than the first horizontal plane where the landing pad MP is located. In other words, the illustrated main source lines SLM<NUM>, SLM<NUM> and source line extensions SLE1a~SLE1c, SLE2a~SLE2c are lower than the landing pad MP. According to embodiments of the present invention, the illustrated main source lines SLM<NUM>, SLM<NUM> and source line extensions SLE1a~SLE1c, SLE2a~SLE2c may be located in the M0 metal layer. According to an embodiment of the present invention, the M0 metal layer may be a tungsten metal layer.

As shown in <FIG>, the bit lines BL<NUM> ~BL<NUM> of the magnetic memory device 1c are disposed between different groups of active areas and extend along the first direction, and the bit lines BL<NUM> ~BL<NUM> partially overlap the underlying strip-shaped active areas 101a and 101b. For example, the bit line BL<NUM> is disposed between the active area 101a of the first group and the active area 101b of the second group, and the magnetic tunnel junction elements MTJ provided on the active area 101a and the active area 101b are electrically connected to the bit line BL<NUM>. The bit lines BL<NUM> ~BL<NUM> may be formed in the upper metal interconnection, for example, the M2 metal layer or the M3 metal layer. By using the above-mentioned shared source line and shared bit line configuration, a wider pitch P<NUM> between the source line and the landing pad can be released (as shown in <FIG>), and a wider bit line pitch P<NUM> can be released (as shown in <FIG>).

Please refer to <FIG> and <FIG>. <FIG> is a partial layout diagram of a magnetic memory device 1d according to another embodiment of the present invention, illustrating part of the shared source lines. <FIG> is a layout diagram showing part of bit lines of the magnetic memory device 1d in <FIG>.

As shown in <FIG> and <FIG>, four strip-shaped and mutually parallel active areas 101a are exemplified in the memory array area MA, and are separated from each other by the strip-shaped STI region <NUM>. In the array area MA, every four adjacent active areas 101a are divided into a group. Therefore, there can be multiple groups of active areas in the memory array area MA. According to an embodiment of the present invention, the strip-shaped active area 101a and the strip-shaped STI area <NUM> both extend along the first direction (for example, the reference X-axis direction).

In <FIG>, four adjacent active areas 101a in the same group share a main source line SLM<NUM> extending along the reference X-axis direction. The main source line SLM<NUM> is electrically connected the source doped region S of each selection transistor <NUM> provided on the active area 101a of the group via source line extensions SLE1a ~SLE1c extending along the reference Y-axis direction. In <FIG>, the magnetic memory device 1d includes bit lines BL<NUM> ~ BL<NUM> extending along the first direction. The bit lines BL<NUM>, BL<NUM> are disposed between different groups of active areas, and the bit lines BL<NUM>, BL<NUM> may partially overlap with the strip-shaped active area 101a. For example, the bit line BL<NUM> is disposed on the active area 101a, and the magnetic tunnel junction elements MTJ disposed on the active area 101a are all electrically connected to the bit line BL<NUM>. The bit lines BL<NUM>~BL<NUM> may be formed in the upper metal interconnection, for example, the M2 metal layer or the M3 metal layer.

Please refer to <FIG> illustrates the active areas divided in three groups in the memory array area MA. <FIG> illustrates the layout of the shared source line with respect to the three groups of active areas in <FIG> illustrates the layout of the bit lines with respect to the three groups of active areas in <FIG>. In <FIG>, the three groups of active areas GP<NUM>~GP<NUM> are indicated by dotted lines, and each group includes n active areas 101a to 101c extending in the first direction (in <FIG>, n = <NUM>). In <FIG>, it is shown that the active areas in the first group GP<NUM> share a main source line SLM<NUM> extending along the reference X axis direction and a source line extension SLE<NUM> extending along the reference Y axis direction. The active areas in the second group GP<NUM> shares the main source line SLM<NUM> extending along the reference X-axis direction and a source line extension SLE<NUM> extending along the reference Y-axis direction. The active areas in the third group GP<NUM> share a main source line SLM<NUM> extending along the reference X-axis direction and a source line extension SLE<NUM> extending along the reference Y-axis direction. In <FIG>, a plurality of bit lines BL1 to BL19 extending along the reference X-axis direction are shown, where BL<NUM>, BL<NUM>, BL<NUM>, and BL<NUM> are bit lines shared between different groups.

Please refer to <FIG>, which is an equivalent circuit diagram of a single transistor single memory cell (1T1M) memory array MA<NUM> according to another embodiment of the present invention. As shown in <FIG>, the memory array MA<NUM> includes a plurality of selection transistors <NUM>, which are respectively arranged in a plurality of rows R<NUM> ~ Rn, where n may be an integer ranging between <NUM>~<NUM>, for example, n = <NUM>, but is not limited thereto. The selection transistor <NUM> and the data storage element including the magnetic tunnel junction element MTJ together constitute a 1T1M configuration. <FIG> shows at least one group of active areas GP<NUM> for illustration purposes. The active areas in the group GP<NUM> share a main source line SLM<NUM> extending along the reference X axis direction and a source line extension SLE<NUM> extending along the reference Y axis direction. The group of active areas GP<NUM> is provided with a plurality of bit lines BL<NUM>~BLn extending along the reference X-axis direction, where BL<NUM> and BLn are bit lines shared between different groups in the Y-axis direction.

The following illustrates an example of the read and write operation method of the 1T1M memory array MA<NUM> of <FIG>. Taking the reading of the magnetic tunnel junction element MTJ<NUM> in <FIG> as an example, the reading operation conditions include: biasing the word line WL<NUM> to VDD and biasing the bit line BL<NUM> to a lower voltage, for example, 50mV. The main source line SLM<NUM> and the source line extension SLE<NUM> are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ<NUM> in <FIG> to a parallel state (<NUM> state), the writing operation conditions include: biasing the word line WL<NUM> to VDD and biasing the bit line BL<NUM> to VCC. The main source line SLM<NUM> and the source line extension SLE<NUM> are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ<NUM> in <FIG> to the anti-parallel state (<NUM> state), the writing operation conditions include: biasing the word line WL<NUM> to VDD, grounding the bit line BL<NUM>, and biasing the main source line SLM<NUM> and the source line extension SLE<NUM> to VCC. The other word lines are grounded. The other bit lines and main source lines are both floating.

Please refer to <FIG>, which is an equivalent circuit diagram of a dual transistor single memory cell (2T1M) memory array MA<NUM> according to another embodiment of the present invention. As shown in <FIG>, the memory array MA<NUM> includes a plurality of selection transistors 200a and 200b, which are respectively arranged in a plurality of rows R<NUM>~Rn, where n may be an integer ranging between <NUM>~<NUM>, for example, n = <NUM>, but is not limited thereto. The two selection transistors 200a, 200b and the data storage element containing the magnetic tunnel junction element MTJ together constitute a 2T1M configuration. <FIG> shows at least one group of active areas GP<NUM> for illustration purposes. The active areas in the group GP<NUM> share a main source line SLM<NUM> extending along the reference X-axis direction and a source line extension SLE<NUM> extending along the reference Y-axis direction. The group of active areas GP<NUM> is provided with a plurality of bit lines BL<NUM> ~ BLn extending along the reference X-axis direction, where BL<NUM> and BLn are bit lines shared between different groups in the Y-axis direction.

The following illustrates an example of the read and write operation method of the 2T1M memory array MA<NUM> of <FIG>. Taking the reading of the magnetic tunnel junction element MTJ<NUM> in <FIG> as an example, the reading operation conditions include: biasing the word line WL<NUM> to VDD, and biasing the bit line BL<NUM> to a lower voltage, for example, 50mV. The main source line SLM<NUM> and the source line extension SLE<NUM> are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ<NUM> in <FIG> to a parallel state (<NUM> state), the writing operation conditions include: biasing the word line WL<NUM> to VDD, and biasing the bit line BL<NUM> to VCC. The main source line SLM<NUM> and the source line extension SLE<NUM> are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

Please refer to <FIG>, which is an equivalent circuit diagram of a triple transistor dual memory cell (3T2M) memory array MA<NUM> according to another embodiment of the present invention. As shown in <FIG>, the memory array MA<NUM> includes a plurality of selection transistors 200a, 200b, and 200c, which are respectively arranged in a plurality of rows R<NUM>~ Rn, where n may be an integer ranging between <NUM>~<NUM>, for example, n = <NUM>, but is not limited to. The three selection transistors 200a, 200b, 200c and the two data storage elements including the magnetic tunnel junction element MTJ together constitute a 3T2M configuration. <FIG> shows at least one group of active areas GP<NUM> for illustration purposes. The active areas in the group GP<NUM> share a main source line SLM<NUM> extending along the reference X axis direction and a source line extension SLE<NUM> extending along the reference Y axis direction. The group of active areas GP<NUM> is provided with a plurality of bit lines BL<NUM>~ BL2n extending along the reference X-axis direction, where BL<NUM> and BL2n are bit lines shared between different groups in the Y-axis direction.

The following illustrates an example of the read and write operation method of the 3T2M memory array MA<NUM> of <FIG>. Taking the reading of the magnetic tunnel junction element MTJ<NUM> in <FIG> as an example, the reading operation conditions include: biasing the word lines WL<NUM> ~ WL<NUM> to VDD and biasing the bit line BL<NUM> to a lower voltage, for example 50mV. The main source line SLM<NUM> and the source line extension SLE<NUM> are grounded. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ<NUM> in <FIG> to a parallel state (<NUM> state), the writing operation conditions include: biasing the word lines WL<NUM> ~ WL<NUM> to VDD, and biasing the bit line BL<NUM> to VCC, grounding the main source line SLM<NUM> and the source line extension SLE<NUM>. The other word lines are grounded. The other bit lines and main source lines are both floating.

To write the magnetic tunnel junction element MTJ<NUM> in <FIG> to an anti-parallel state (<NUM> state), the writing operation conditions include: biasing the word lines WL<NUM> ~ WL<NUM> to VDD, and grounding the bit line BL<NUM>, The main source line SLM<NUM> and the source line extension SLE<NUM> are biased to VCC. The other word lines are grounded. The other bit lines and main source lines are both floating.

Claim 1:
A memory device (<NUM>), comprising:
a substrate (<NUM>);
an active area (<NUM>) extending along a first direction on the substrate (<NUM>);
a gate line (WL1) traversing the active area (<NUM>) and extending along a second direction that is not parallel to the first direction;
a source doped region (S1) in the active area (<NUM>) and on a first side of the gate line (WL1);
a main source line (SLM1) extending along the first direction;
a source line extension (SLE1) coupled to the main source line (SLM1) and extending along the second direction, wherein the main source line (SLM1) is electrically connected to the source doped region (S1) via the source line extension (SLE1);
a drain doped region (D) in the active area (<NUM>) and on a second side of the gate line (WL1) that is opposite to the first side;
a data storage element (MS1, MS2) electrically coupled to the drain doped region (D), wherein the data storage element (MS1, MS2) comprises a magnetic tunneling junction, MTJ, element;
a landing pad (MP1) disposed directly under the MTJ element, the MTJ element comprising a bottom electrode (BE1) that is electrically connected to the landing pad (MP1);
a drain contact (C1) electrically connecting the landing pad (MP1) to the drain doped region (D);
a first dielectric layer (<NUM>) disposed on the substrate (<NUM>), wherein the landing pad (MP1) is disposed in the first dielectric layer (<NUM>) and is situated in a first horizontal plane; and
a second dielectric layer (<NUM>) covering the first dielectric layer (<NUM>) and the landing pad (MP1), wherein the MTJ element is disposed in the second dielectric layer (<NUM>), and wherein the main source line (SLM1) and the source line extension (SLE1) are situated in a second horizontal plane, wherein the second horizontal plane is lower than the first horizontal plane.