Patent Description:
The statements herein merely provide background information related to the disclosure and may not necessarily constitute the related art. With development and progress of technologies, Thin Film Transistor Liquid Crystal Displays (TFT-LCD) have become the most widely used display in the market, especially in LCD TVs.

At present, the TFT-LCD includes a Data Line (DL)/source line, a Scan Line (SL)/gate line, a common-electrode line, and a Thin Film Transistor (TFT). In an existing TFT-LCD, the SL is perpendicular to DL, and the common-electrode line is parallel to and spaced apart from the SL. Since signals transmitted on various signal lines are different, these signal lines need to be isolated from one another, and these signal lines are opaque since they are made of metal, as a result, an aperture ratio of a pixel is relatively low, which leads to a low display brightness of the display panel. <CIT> discloses an array substrate comprising a base substrate having a first surface and a second surface opposite to the first surface, and a stacked structure disposed on the first surface of the base substrate, the stacked structure comprising a common-electrode layer, and a gate line isolated from the common-electrode layer, and the array substrate further comprising a common-electrode line disposed on the base substrate, wherein an orthographic projection of the gate line on a plane where the common-electrode line is located at least partially overlaps with the common-electrode line. <CIT> discloses an LCD device with an array substrate having a common wiring overlapping with a data line, whereby a corresponding line width of a black matrix on the opposed colour filter substrate can be reduced to increase the pixel aperture ratio, thereby increasing the brightness of the display. Hence, <CIT> is similar to <CIT>, but instead of overlapping the gate line with the common line to increase the pixel aperture ratio, <CIT> uses an overlap between data line with the common line. <CIT> discloses an array substrate having a planar common electrode underneath the pixel electrodes, and including a substrate base having a first side and an opposed second side, wherein a layer stack including the common electrode, the pixel electrodes, gate lines, TFTs, etc. arranged on the 1st side, and data lines arranged on the 2nd side. Conductive vias passing through the substrate connect the data lines to the respective TFTs. The data lines overlap the common electrode to increase pixel aperture.

The disclosure provides an array substrate. The array substrate includes a base substrate, a stacked structure, a common-electrode line, and a conductive structure. The base substrate has a first surface and a second surface opposite to the first surface. The stacked structure is disposed on the first surface of the base substrate. The stacked structure includes a contact pad, a common-electrode layer, and a gate line. The contact pad is disposed on the first surface of the base substrate. The base substrate defines a first via hole at a position corresponding to the contact pad, where the first via hole penetrates the first surface and the second surface of the base substrate. The common-electrode layer is connected with the contact pad. The gate line is isolated from the common-electrode layer and the contact pad. The common-electrode line is disposed on the second surface of the base substrate, where an orthographic projection of the gate line on a plane where the common-electrode line is located at least partially overlaps with the common-electrode line. The conductive structure is connected with the contact pad, and connected to the common-electrode line through the first via hole.

According to the array substrate of the disclosure, the gate line is disposed on the first surface of the array substrate and the common-electrode line is disposed on the second surface of the array substrate opposite to the first surface, and the gate line at least partially overlaps with the common-electrode line, which can reduce a wiring area on the first surface of the array substrate, thereby increasing an area of a pixel-electrode layer in each pixel unit and increasing an aperture ratio of the pixel unit.

The disclosure further provides a display panel. The display panel includes a color-film substrate and an array substrate. The array substrate is opposite to the color-film substrate. The array substrate includes a base substrate, a stacked structure, a common-electrode line, and a conductive structure. The base substrate has a first surface and a second surface opposite to the first surface. The stacked structure is disposed on the first surface of the base substrate. The stacked structure includes a contact pad, a common-electrode layer, and a gate line. The contact pad is disposed on the first surface of the base substrate. The base substrate defines a first via hole at a position corresponding to the contact pad, where the first via hole penetrates the first surface and the second surface of the base substrate. The common-electrode layer is connected with the contact pad. The gate line is isolated from the common-electrode layer and the contact pad. The common-electrode line is disposed on the second surface of the base substrate, where an orthographic projection of the gate line on a plane where the common-electrode line is located at least partially overlaps with the common-electrode line. The conductive structure is connected with the contact pad, and connected to the common-electrode line through the first via hole.

Additional aspects and advantages of the disclosure will be illustrated in part from the following description, and the other part of the additional aspects and the advantages of the disclosure will become apparent from the following description, or may be learned by practice of the disclosure.

The disclosure will be further depicted below with reference to specific implementations and accompanying drawings.

Hereinafter, technical solutions of implementations of the disclosure will be depicted in a clear and comprehensive manner with reference to accompanying drawings intended for these implementations. Apparently, implementations described below merely illustrate some implementations, rather than all implementations, of the disclosure. All other implementations obtained by those of ordinary skill in the art based on the implementations of the disclosure without creative efforts shall fall within the protection scope of the disclosure.

In description of the disclosure, it should be noted that, orientations or positional relationships indicated by the terms "upper", "lower", "left", "right", and the like are based on orientations or positional relationships illustrated in the accompanying drawings, and are only for convenience of describing the disclosure and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the disclosure. In addition, the terms "first", "second", and the like are used for descriptive only and should not be construed to indicate or imply relative importance.

Referring to <FIG> is a schematic top view of an existing array substrate <NUM>". The array substrate <NUM>" includes multiple gate lines <NUM>" (i.e., scan lines) extending along a first direction (an OX direction illustrated in figures), multiple common-electrode lines <NUM>" extending along the first direction, and multiple source lines <NUM>" (i.e., data lines) extending along a second direction (an OY direction illustrated in figures). The multiple gate lines <NUM>" intersect the multiple source lines <NUM>", to define multiple pixel units <NUM>" arranged in an array. Each pixel unit <NUM>" includes a Thin Film Transistor (TFT) <NUM>", a pixel-electrode layer <NUM>", and a common-electrode layer (not illustrated). A source <NUM>" of the TFT <NUM>" is connected with a source line <NUM>" near the source <NUM>", a drain <NUM>" of the TFT <NUM>" is connected with the pixel-electrode layer <NUM>", and a gate <NUM>" of the TFT <NUM>" is connected with a gate line <NUM>" near the gate <NUM>". The common-electrode layer is connected with a common-electrode line <NUM>" nearby. Since the gate lines <NUM>", the source lines <NUM>", and the common-electrode lines <NUM>" of the existing array substrate <NUM>" each occupy part of a wiring area and each are made of metal and opaque, an area of the pixel-electrode layer <NUM>" in each pixel unit <NUM>" is relatively small, which leads to a low aperture ratio of the pixel unit <NUM>" of the array substrate in <NUM>".

In order to solve the problem of the low aperture ratio of the pixel unit in the existing array substrate, the disclosure provides an array substrate <NUM>, referring to <FIG>. According to the array substrate <NUM> of the disclosure, a common-electrode line <NUM> and a gate line <NUM> are respectively disposed on two opposite surfaces of the array substrate <NUM>, and a projection of the gate line <NUM> on a plane where the common-electrode line is located at least partially overlaps with the common-electrode line, which can reduce a wiring area in the array substrate <NUM>, thereby increasing an area of a pixel-electrode layer <NUM> in each pixel unit <NUM> and increasing an aperture ratio of the pixel unit <NUM>.

Specifically, referring to <FIG>, the array substrate <NUM> includes a base substrate <NUM>, a stacked structure <NUM>, a common-electrode line <NUM>, and a conductive structure <NUM>. The base substrate <NUM> has a first surface <NUM> and a second surface <NUM> opposite to the first surface <NUM>.

The stacked structure <NUM> is disposed on the first surface <NUM> of the base substrate <NUM>. The stacked structure <NUM> includes a contact pad <NUM>, a common-electrode layer <NUM>, and a gate line <NUM>. The contact pad <NUM> is disposed on the first surface <NUM> of the base substrate <NUM> and connected with the common-electrode layer <NUM>. The gate line <NUM> is isolated from the common-electrode layer <NUM> and the contact pad <NUM>. The base substrate <NUM> defines a first via hole <NUM> at a position corresponding to the contact pad <NUM>, and the first via hole <NUM> penetrates the first surface <NUM> and the second surface <NUM> of the base substrate <NUM>. The conductive structure <NUM> is connected with the contact pad <NUM> and connected with the common-electrode line <NUM> through the first via hole <NUM>. The first via hole <NUM> may be a circular hole or a square hole, or be in other shapes, which is not limited herein.

The common-electrode line <NUM> is disposed on the second surface <NUM> of the base substrate <NUM>. An orthographic projection of the gate line <NUM> on a plane where the common-electrode line <NUM> is located at least partially overlaps with the common-electrode line <NUM>. In implementations of the disclosure, the orthographic projection of the gate line <NUM> on the plane where the common-electrode line <NUM> is located completely covers the common-electrode line <NUM>. Specifically, the gate line <NUM> includes multiple gate lines <NUM> extending along the first direction, the common-electrode line <NUM> includes multiple common-electrode lines <NUM> extending along the first direction, and the multiple gate lines <NUM> are in one-to-one correspondence with the multiple common-electrode lines <NUM>. It can be understood that, when an overlapping area of the gate lines <NUM> and the common-electrode lines <NUM> is larger, a larger wiring area on the first surface of the array substrate <NUM> can be reduced, which facilitates increasing the aperture ratio of the pixel unit <NUM>. Exemplarily, for each of the gate lines <NUM>, a projection of the gate line <NUM> on the plane where a corresponding common-electrode line <NUM> is located completely overlaps with the common-electrode line <NUM>. Since a wiring area of the common-electrode lines <NUM> in the existing array substrate occupies about <NUM>% of a pixel area, by adopting the array substrate <NUM> of the disclosure, the wiring area on the first surface <NUM> can be reduced by <NUM>% and the area of the pixel-electrode layer <NUM> in each pixel unit <NUM> can be increased by <NUM>%, therefore, the aperture ratio of the pixel unit <NUM> can be increased by about <NUM>%.

It should be noted that, in implementations of the disclosure, each pixel unit <NUM> includes a contact pad <NUM> and a common-electrode layer <NUM>, the base substrate <NUM> defines a first via hole <NUM> at a position corresponding to each contact pad <NUM>, and contact pads <NUM> are connected with common-electrode layers <NUM> in one-to-one correspondence.

Exemplarily, the base substrate <NUM> may be a hard substrate made of a light-guiding and non-metallic material with certain firmness, such as glass, quartz, common resin, etc., or the base substrate <NUM> may also be a flexible substrate made of a flexible material such as Polyimide (PI). The common-electrode layer <NUM> may be made of a metal oxide such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), etc. The conductive structure <NUM> may be formed through a silver paste printing process. The common-electrode line <NUM>, the gate line <NUM>, and the contact pad <NUM> may be made of same or different materials, exemplarily, a conductive metal, for example, at least one of molybdenum, aluminum, chromium, tungsten, tantalum, titanium, or copper.

According to the array substrate <NUM> of the disclosure, the gate line <NUM> is disposed on the first surface <NUM> of the array substrate <NUM> and the common-electrode line <NUM> is disposed on the second surface <NUM> of the array substrate <NUM> opposite to the first surface <NUM>, and the gate line <NUM> at least partially overlaps with the common-electrode line <NUM>, which can reduce the wiring area on the first surface <NUM> of the array substrate <NUM>, thereby increasing the area of the pixel-electrode layer <NUM> in each pixel unit <NUM> and increasing the aperture ratio of the pixel unit <NUM>.

It should be noted that, the number of layered structures in the stacked structure <NUM> and positional relationships between the layered structures can be designed according to requirements, which are not limited in the disclosure.

Exemplarily, in an implementation, as illustrated in <FIG>, the gate line <NUM> and the contact pad <NUM> of the stacked structure <NUM> are disposed in a same layer, and are disposed on the first surface <NUM> of the base substrate <NUM>. The stacked structure <NUM> further includes a first insulating layer <NUM>, a source-drain layer, an active layer <NUM>, a second insulating layer <NUM>, a third insulating layer <NUM>, and a pixel-electrode layer <NUM>.

Specifically, the gate line <NUM> and a gate <NUM> are disposed in a same layer. The first insulating layer <NUM> covers the gate line <NUM>, the gate <NUM>, and the contact pad <NUM>. The source-drain layer and the active layer <NUM> are disposed on the first insulating layer <NUM>. The source-drain layer includes a source <NUM> and a drain <NUM>. A gate <NUM>, a source <NUM>, a drain <NUM>, and an active layer <NUM> in a same pixel unit <NUM> together form a TFT <NUM>. The second insulating layer <NUM> covers the source-drain layer and the active layer <NUM>. The common-electrode layer <NUM> is disposed on the second insulating layer <NUM>. The third insulating layer <NUM> covers the common-electrode layer <NUM>. The pixel-electrode layer <NUM> is disposed on the third insulating layer <NUM>. Exemplarily, an orthographic projection of the pixel-electrode layer <NUM> on the base substrate <NUM> overlaps with an orthographic projection of the common-electrode layer <NUM> on the base substrate <NUM>.

Further, the first insulating layer <NUM> and the second insulating layer <NUM> define a second via hole <NUM> at positions corresponding to the contact pad <NUM>. The common-electrode layer <NUM> is connected with the contact pad <NUM> through the second via hole <NUM>. Specifically, in implementations of the disclosure, a first insulating layer <NUM> and a second insulating layer <NUM> in each pixel unit <NUM> define a second via hole <NUM>, and common-electrode layers <NUM> are connected with contact pads <NUM> in one-to-one correspondence through a corresponding second via hole <NUM>.

In another implementation, as illustrated in <FIG>, a common-electrode layer <NUM>' and a contact pad <NUM>' are disposed in a same layer and connected with each other, and are disposed on a first surface <NUM>' of a base substrate <NUM>'. The stacked structure <NUM>' further includes a first insulating layer <NUM>', a second insulating layer <NUM>', a source-drain layer, an active layer <NUM>', a third insulating layer <NUM>', and a pixel-electrode layer <NUM>'.

Specifically, the first insulating layer <NUM>' covers the contact pad <NUM>' and the common-electrode layer <NUM>'. A gate line <NUM>' and a gate <NUM>' are disposed in a same layer, and are disposed on the first insulating layer <NUM>'. The second insulating layer <NUM>' covers the gate line <NUM>' and the gate <NUM>'. The source-drain layer is disposed on the second insulating layer <NUM>'. The source-drain layer includes a source <NUM>' and a drain <NUM>'. A gate <NUM>', a source <NUM>', a drain <NUM>', and an active layer <NUM>' in a same pixel unit <NUM> jointly constitute a TFT <NUM>'. The third insulating layer <NUM>' covers the source-drain layer. The pixel-electrode layer <NUM>' is disposed on the third insulating layer <NUM>'.

Based on the same inventive concept, implementations of the disclosure further provide a method for manufacturing an array substrate. As illustrated in <FIG>, the method includes the following.

At <NUM>, a base substrate <NUM> is provided. The base substrate <NUM> has a first surface <NUM> and a second surface <NUM> opposite to the first surface <NUM>. Exemplarily, the base substrate <NUM> may be a hard substrate made of a light-guiding and non-metallic material with certain firmness, such as glass, quartz, common resin, etc., or the base substrate <NUM> may also be a flexible substrate made of a flexible material such as PI.

At <NUM>, a stacked structure <NUM> is formed on the first surface <NUM> of the base substrate <NUM>. The stacked structure <NUM> includes a contact pad <NUM>, a common-electrode layer <NUM>, and a gate line <NUM>, where the contact pad <NUM> is formed on the first surface <NUM> of the base substrate <NUM>, the common-electrode layer <NUM> is connected with the contact pad <NUM>, and the gate line <NUM> is isolated from the common-electrode layer <NUM> and the contact pad <NUM>.

At <NUM>, a first via hole <NUM> is formed in the base substrate <NUM> at a position corresponding to the contact pad <NUM>, where the first via hole <NUM> penetrates the first surface <NUM> and second surface <NUM> of the base substrate <NUM>, and the contact pad <NUM> is exposed to outside of the first via hole <NUM>.

It should be noted that, the first via hole <NUM> may be a circular hole or a square hole, or be in other shapes, which is not limited herein. Since an area of a single pixel unit <NUM> is relatively small, the size of the first via hole <NUM> needs to be controlled within a certain range. Exemplarily, the first via hole <NUM> is a circular hole with a diameter of about <NUM>, or a square hole with a side length of about <NUM>. If the base substrate <NUM> is made of glass, HF and O<NUM> can be used to etch glass (SiO<NUM>), and the first via hole <NUM> can be formed through a cyclic dry etching process, where the cyclic dry etching process belongs to an existing technology, which will not be repeated herein. Since each pixel unit <NUM> defines a first via hole <NUM>, the number of first via holes <NUM> on the base substrate <NUM> is relatively large and arrangement of the first via holes <NUM> is relatively dense. If the base substrate <NUM> is made of glass, the requirement for the cyclic dry etching process is relatively high, otherwise, the base substrate may be broken. In the disclosure, the base substrate <NUM> may also be made of polyimide, so that the first via hole <NUM> can be formed through exposure and development, as such, the process is relatively simple, and the base substrate will not be broken. Specifically, a mask with a pattern is covered on the second surface <NUM> of the base substrate <NUM>. An ultraviolet light selectively irradiates the second surface <NUM> of the base substrate <NUM>, and then developer is used to remove polyimide of part of the base substrate <NUM> that was illuminated or polyimide of part of the base substrate <NUM> that was not illuminated, to make the pattern on the mask be formed on the base substrate <NUM>, that is, the first via hole <NUM> is formed.

At <NUM>, a common-electrode line <NUM> is formed on the second surface <NUM> of the base substrate <NUM>, where an orthographic projection of the gate line <NUM> on a plane where the common-electrode line <NUM> is located at least partially overlaps with the common-electrode line <NUM>. In implementations of the disclosure, exemplarily, the common-electrode line <NUM> can be formed through a patterning process. Specifically, multiple common-electrode lines <NUM> in one-to-one correspondence with multiple gate lines <NUM> are formed on the second surface <NUM> of the base substrate <NUM> through a patterning process, where orthographic projections of the multiple gate lines <NUM> on a plane where the common-electrode lines <NUM> are located completely cover the multiple common-electrode lines <NUM>, or, orthographic projections of the multiple common-electrode lines <NUM> on a plane where the gate lines <NUM> are located completely cover the multiple gate lines <NUM>.

The "patterning process" of implementations of the disclosure includes film deposition, photoresist coating, mask exposure, developing, etching, photoresist stripping, and other processes. The deposition may adopt any one or more of sputtering, evaporation, chemical vapor deposition. The coating may be any one or more of spray coating and spin coating. The etching may be any one or more of dry etching and wet etching. Each of the above processes belongs to an existing technology, which will not be repeated herein.

At <NUM>, a conductive structure <NUM> is formed in the first via hole <NUM> and at a preset position of the second surface <NUM> of the base substrate <NUM>, where the contact pad <NUM> is connected to a common-electrode line <NUM> near the first via hole <NUM> through the conductive structure <NUM>. Exemplarily, the conductive structure <NUM> is formed through a silver paste printing process, where the contact pad <NUM> in each pixel unit <NUM> is connected to a nearby common-electrode line <NUM> through a corresponding first via hole <NUM>.

It should be noted that, the disclosure does not limit an order for executing the operations at <NUM> to <NUM>, as long as the operations at <NUM> are after the operations at <NUM>. In another implementation, the operations at <NUM> are performed first, then the operations at <NUM>, and finally the operations at <NUM>. In yet another implementation, the operations at <NUM> are performed first, then the operations at <NUM>, and finally the operations at <NUM>.

As mentioned above, the number of layered structures in the stacked structure <NUM> and positional relationships between the layered structures can be designed according to requirements. The operations at <NUM> correspond to features of the stacked structure <NUM>, which is not limited herein. Exemplarily, in an implementation, as illustrated in <FIG>, the operations at <NUM> specifically include the following.

At <NUM>, the contact pad <NUM> and the gate line <NUM> are formed on the first surface <NUM> of the base substrate <NUM>. In this implementation, a gate <NUM> is also formed on the first surface <NUM> of the base substrate <NUM>. Exemplarily, the contact pad <NUM>, the gate line <NUM>, and the gate <NUM> are made of a same material, and can be formed through a patterning process. Specifically, a contact pad <NUM> is formed in each pixel unit <NUM>.

At <NUM>, a first insulating layer <NUM> is formed on the contact pad <NUM> and the gate line <NUM>. In this implementation, the first insulating layer <NUM> also covers the gate <NUM>. Exemplarily, the first insulating layer <NUM> is made of a material such as silicon nitride, silicon oxide, or silicon oxynitride.

At <NUM>, a second insulating layer <NUM> is formed on the first insulating layer <NUM>.

In implementations of the disclosure, the operations at <NUM> specifically include the following.

At 723a, a source-drain layer and an active layer <NUM> are formed on the first insulating layer <NUM>. The active layer <NUM> may be a semiconductor active layer or an oxide active layer. For example, the active layer <NUM> is a semiconductor active layer made of a semiconductor material such as amorphous silicon or polycrystalline silicon. Exemplarily, the active layer <NUM> is formed through a patterning process, and the source-drain layer is formed through another patterning process.

At 723b, the second insulating layer <NUM> is formed on the source-drain layer and the active layer <NUM>. Exemplarily, the second insulating layer <NUM> is made of a material such as silicon nitride, silicon oxide, or silicon oxynitride.

At <NUM>, a second via hole <NUM> is formed in the first insulating layer <NUM> and the second insulating layer <NUM> at positions corresponding to the contact pad <NUM>, where the contact pad <NUM> is exposed to outside of the second via hole <NUM>. Specifically, the first insulating layer <NUM> and the second insulating layer <NUM> in each pixel unit <NUM> define a second via hole <NUM>.

At <NUM>, the common-electrode layer <NUM> is formed on the second insulating layer <NUM> and in the second via hole, where the common-electrode layer <NUM> is connected with the contact pad <NUM> through the second via hole. Specifically, the common-electrode layer <NUM> in each pixel unit <NUM> is connected with a corresponding contact pad <NUM> through the second via hole <NUM>.

According to the method for manufacturing the array substrate of the disclosure, the gate line <NUM> is formed on the first surface <NUM> of the array substrate <NUM> and the common-electrode line <NUM> is formed on the second surface <NUM> of the array substrate <NUM> opposite to the first surface <NUM>, and the gate line <NUM> at least partially overlaps with the common-electrode line <NUM>, which can reduce a wiring area on the first surface <NUM> of the array substrate <NUM>, thereby increasing an area of the pixel-electrode layer <NUM> in each pixel unit <NUM> and increasing an aperture ratio of the pixel unit <NUM>.

Based on the same inventive concept, referring to <FIG>, the disclosure further provides a display panel <NUM>. The display panel <NUM> includes a color-film substrate <NUM>, the above array substrate <NUM>, and a sealant <NUM>. The array substrate <NUM> is disposed opposite to the color-film substrate <NUM>. The display panel <NUM> further includes a liquid crystal layer (not illustrated) filled between the color-film substrate <NUM> and the array substrate <NUM>. The sealant <NUM> is disposed around the liquid crystal layer, and configured to seal the liquid crystal layer between the array substrate <NUM> and the color-film substrate <NUM>. The display panel <NUM> may further include other structures, for example, a lower polarizer (not illustrated), an upper polarizer (not illustrated), etc., which is not limited herein.

Exemplarily, the display panel <NUM> may be a TFT-LCD with various liquid crystal driving and display modes, including but not limited to, a Twisted Nematic (TN) panel, a Vertical Alignment (VA) panel, an In-Plane Switching (IPS) panel, etc..

Claim 1:
An array substrate (<NUM>, <NUM>'), comprising:
a base substrate (<NUM>, <NUM>') having a first surface and a second surface opposite to the first surface; and
a stacked structure (<NUM>, <NUM>') disposed on the first surface of the base substrate, the stacked structure comprising:
a contact pad (<NUM>, <NUM>') disposed on the first surface of the base substrate,
wherein the base substrate defines a first via hole (<NUM>, <NUM>') at a position corresponding to the contact pad, the first via hole penetrating the first surface and the second surface of the base substrate;
a common-electrode layer (<NUM>, <NUM>') connected with the contact pad; and
a gate line (<NUM>, <NUM>') isolated from the common-electrode layer and the contact pad; and
the array substrate further comprising:
a common-electrode line (<NUM>, <NUM>') disposed on the second surface of the base substrate, wherein an orthographic projection of the gate line on a plane where the common-electrode line is located at least partially overlaps with the common-electrode line; and
a conductive structure (<NUM>, <NUM>') connected with the contact pad, and connected to the common-electrode line through the first via hole.