Patent Description:
Interest in the field of flexible electronics principally arises out of several important advantages provided by this technology. First, the mechanical ruggedness of plastic substrate materials provides electronic devices less susceptible to damage and/or electronic performance degradation caused by mechanical stress. Second, the inherent flexibility of these substrate materials allows them to be integrated into many shapes providing for a large number of useful device configurations not possible with brittle conventional silicon based electronic devices. For example, bendable flexible electronic devices are expected to enable fabrication of new devices, such as electronic paper, wearable computers and large-area high resolution displays, that are not easily achieved with established silicon based technologies. Finally, the combination of solution processable component materials and plastic substrates enables fabrication by continuous, high speed, printing techniques capable of generating electronic devices over large substrate areas at low cost.

The design and fabrication of flexible electronic devices exhibiting good electronic performance, however, present a number of significant challenges. First, the well developed methods of making conventional silicon based electronic devices are incompatible with most plastic materials. For example, traditional high quality inorganic semiconductor components, such as single crystalline silicon or germanium semiconductors, are typically processed by growing thin films at temperatures (> <NUM> degrees Celsius) that significantly exceed the melting or decomposition temperatures of most plastic substrates. In addition, most inorganic semiconductors are not intrinsically soluble in convenient solvents that would allow for solution based processing and delivery. Second, although many amorphous silicon, organic or hybrid organic-inorganic semiconductors are compatible with incorporation into plastic substrates and can be processed at relatively low temperatures, these materials do not have electronic properties capable of providing integrated electronic devices capable of good electronic performance. For example, thin film transistors having semiconductor elements made of these materials exhibit field effect mobilities approximately three orders of magnitude less than complementary single crystalline silicon based devices. As a result of these limitations, flexible electronic devices are presently limited to specific applications not requiring high performance, such as use in switching elements for active matrix flat panel displays with non-emissive pixels and in light emitting diodes.

Progress has recently been made in extending the electronic performance capabilities of integrated electronic devices on plastic substrates to expand their applicability to a wider range of electronics applications. For example, several new thin film transistor (TFT) designs have emerged that are compatible with processing on plastic substrate materials and exhibit significantly higher device performance characteristics than thin film transistors having amorphous silicon, organic or hybrid organic-inorganic semiconductor elements. One class of higher performing flexible electronic devices is based on polycrystalline silicon thin film semiconductor elements fabricated by pulse laser annealing of amorphous silicon thin films. While this class of flexible electronic devices provides enhanced device electronic performance characteristics, use of pulsed laser annealing limits the ease and flexibility of fabrication of such devices, thereby significantly increasing costs. Another promising new class of higher performing flexible electronic devices is devices that employ solution processable nanoscale materials, such as nanowires, nanoribbons, nanoparticles and carbon nanotubes, as active functional components in a number of macroelectronic and microelectronic devices.

Use of discrete single crystalline nanowires or nanoribbons has been evaluated as a possible means of providing printable electronic devices on plastic substrates that exhibit enhanced device performance characteristics. Duan et al. describe thin film transistor designs having a plurality of selectively oriented single crystalline silicon nanowires or CdS nanoribbons as semiconducting channels [<NPL>]. The authors report a fabrication process allegedly compatible with solution processing on plastic substrates in which single crystalline silicon nanowires or CdS nanoribbons having thicknesses less than or equal to <NUM> nanometers are dispersed into solution and assembled onto the surface of a substrate using flow-directed alignment methods to produce the semiconducting element of at thin film transistor. An optical micrograph provided by the authors suggests that the disclosed fabrication process prepares a monolayer of nanowires or nanoribbons in a substantially parallel orientation and spaced apart by about <NUM> nanometers to about <NUM>,<NUM> nanometers. Although the authors report relatively high intrinsic field affect mobilities for individual nanowires or nanoribbons (≈ <NUM><NUM> V-<NUM> s-<NUM>), the overall device field effect mobility has recently been determined to be "approximately two orders of magnitude smaller" than the intrinsic field affect mobility value reported by <NPL>]. This device field effect mobility is several orders of magnitude lower than the device field effect mobilities of conventional single crystalline inorganic thin film transistors, and is likely due to practical challenges in aligning, densely packing and electrically contacting discrete nanowires or nanoribbons using the methods and device configurations disclosed in Duan et al.

Use of a nanocrystal solutions as precursors to polycrystalline inorganic semiconductor thin films has also been explored as a possible means of providing printable electronic devices on plastic substrates that exhibit higher device performance characteristics. Ridley et al. disclose a solution processing fabrication method wherein a solution cadmium selenide nanocrystals having dimensions of about <NUM> nanometers is processed at plastic compatible temperatures to provide a semiconductor element for a field effect transistor. The authors report a method wherein low temperature grain growth in a nanocrystal solution of cadmium selenide provides single crystal areas encompassing hundreds of nanocrystals. Although Ridley et al. report improved electrical properties relative to comparable devices having organic semiconductor elements, the device mobilities achieved by these techniques (≈ <NUM><NUM> V-<NUM> s-<NUM>) are several orders of magnitude lower than the device field effect mobilities of conventional single crystalline inorganic thin film transistors. Limits on the field effect mobilities achieved by the device configurations and fabrication methods of Ridley et al. are likely to arise from the electrical contact established between individual nanoparticles. Particularly, the use of organic end groups to stabilize nanocrystal solutions and prevent agglomeration may impede establishing good electrical contact between adjacent nanoparticles that is necessary for providing high device field effect mobilities.

Although Duan et al. and Ridley et al. provide methods for fabricating thin film transistors on plastic substrates, the device configurations described employ transistors comprising mechanically rigid device components, such as electrodes, semiconductors and/or dielectrics. Selection of a plastic substrate with good mechanical properties may provide electronic devices capable of performing in flexed or distorted orientations. However, such motion is expected to generate mechanical strain on the individual rigid transistor device components. This mechanical strain may induce damage to individual components, for example by cracking, and also may degrade or disrupt electrical contact between device components.

It will be appreciated from the foregoing that there is currently a need in the art for methods and device configurations for fabricating integrated electronic semiconductor-containing devices on plastic substrates. Printable semiconductor elements having good electrical characteristics are needed to allow effective device fabrication at temperatures compatible with assembly on plastic polymer substrates. In addition, methods of printing semiconductor materials onto large areas of plastic substrates are needed to enable continuous, high speed printing of complex integrated electrical circuits over large substrate areas. Finally, fully flexible electronic devices capable of good electronic performance in flexed or deformed device orientations are needed to enable a wide range of new flexible electronic devices.

Document <CIT> discloses a method for fabricating a printable semiconductor element.

The present invention provides the method of claim <NUM>.

In the context of the present invention, the term "printable" relates to materials, structures, device components and/or integrated functional devices that may be transferred, assembled, patterned, organized and and/or integrated onto or into substrates without exposure of the substrate to high temperatures (i.e. at temperatures less than or equal to about <NUM> degrees Celsius).

Printable semiconductor elements may comprise unitary, single crystalline inorganic semiconductor structures. Printable semiconductor elements of the present invention may have a wide range of physical dimensions, for example, thicknesses ranging from about <NUM> nanometers to about <NUM> microns, widths ranging from about <NUM> nanometers to about <NUM> millimeter and lengths ranging from about <NUM> micron to about <NUM> millimeter. Use of semiconductor elements having thicknesses greater than about <NUM> nanometers and widths greater than about <NUM> nanometer are preferred for some application because these dimensions may provide electronic devices exhibiting good electronic performance, such as thin film transistors having a device field effect mobility greater than or equal to about <NUM><NUM> V-<NUM> s-<NUM>, and preferably greater than or equal to about <NUM><NUM> V-<NUM> s-<NUM> and more preferably greater than or equal to about <NUM><NUM> V-<NUM> s-<NUM>. In addition, semiconductor elements having widths greater than about <NUM> nanometers can be assembled on substrates by a range of printing techniques with good placement accuracy and pattern fidelity.

Printable semiconductor elements of the present invention are provided with an alignment maintaining element that mechanically connects the printable semiconductor element to a mother substrate, such as a semiconductor wafer. Alignment maintaining elements are useful for maintaining a selected orientation and/or position of a printable semiconductor element during transfer, assembly and/or integration processing steps. Alignment maintaining elements are also useful for maintaining relative positions and orientations of a plurality of semiconductor elements defining a selected pattern of semiconductor elements during transfer, assembly and/or integration processing steps. In methods of the present invention, alignment maintaining elements preserve selected positions and orientations during contact (and bonding) of the printable semiconductor elements with the contact surface of a conformable transfer device. Useful alignment maintaining elements in this aspect of the present invention are capable of disengaging from the printable semiconductor elements upon movement of the conformable transfer device without significantly changing the selected positions and orientations of the printable semiconductor elements. Disengagement is typically achieved by fracture or release of the alignment maintaining elements during movement of the transfer device.

In one embodiment of the present invention, the printable semiconductor element has a peanut shape characterized by wider ends and a narrow central region. In this embodiment, alignment maintaining elements are provided via incomplete isotropic etching beneath the wider ends and complete isotropic etching beneath the central region. This processing leads to a semiconductor element connected to a mother substrate at two points corresponding to each end of the semiconductor element. In another embodiment, the printable semiconductor element has a ribbon shape extending along a central longitudinal axis. In this embodiment, alignment maintaining elements connect the both ends of the ribbon along the longitudinal axis to the mother substrate. In each embodiment, binding of the ribbon shaped or peanut shaped semiconductor element to the contact surface of a transfer device and movement of the transfer device results in fracture of both alignment maintaining elements and release of the printable semiconductor element from the mother substrate.

In addition, the present methods provide printable semiconductor elements having highly uniform compositions. In this context, uniform composition refers to piece-to-piece uniformity with respect to purity, dopant concentrations, dopant spatial distributions and extents of crystallization. The high purities and good uniformity with respect to the composition of printable semiconductor elements of the present provide functional devices exhibiting enhanced reliability with respect to devices fabricated from conventional semiconductor materials derived from "bottom up" processing techniques, such as nanowire and nanocrystal materials.

The methods of the present invention provide a processing platform enabling fabrication of functional devices exhibiting enhanced reliability with respect to devices based on semiconductor materials generated via "bottom up" processing techniques, such as nanowires and nanocrystals. In this context, reliability refers to the capability of a functional devices to exhibit good electronic properties over extended operating periods and refers to piece-to-piece uniformity with respect to electrical properties of an ensemble of device fabricated using the present methods and compositions. For example, devices of the present invention exhibit very uniform threshold voltages (e.g. standard deviation of less than <NUM>. 08V) and very uniform device mobilities (e.g. standard deviation of less than about <NUM>%). This represents improvements in uniformities of threshold voltages and device mobilities of a factor of about <NUM> and a factor of about <NUM>, respectively, over nanowire based devices. The exceptional reliability of functional devices of the present invention is provided, at least in part, by the high degree of uniformity of the compositions and physical dimensions accessible using printable semiconductor elements of the present invention.

Unclaimed aspects are methods of assembling, positioning, organizing, transferring, patterning and/or integrating printable semiconductor elements onto or into substrates via a range of printing methods, including dry transfer contact printing or solution printing techniques. Printing methods of the present invention are capable of integrating one or more semiconductor elements onto or into a substrate in a manner which does not substantially affect their electrical properties and/or mechanical characteristics. In addition, printing methods of the present invention are capable of assembling semiconductor elements onto or into selected regions of a substrate and in selected spatial orientations. Further, printing methods of the present invention are capable of integrating semiconductor elements and other device components into and/or onto a substrate in a manner providing high performing electronic and optoelectronic devices by establishing good conductivity between selected device components, good insulation between selected device components and/or good spatial alignment and relative positioning between device components.

In one unclaimed example, semiconductor elements are assembled onto a substrate surface by dry transfer contact printing methods, such as soft lithographic microtransfer or nanotransfer methods. In one method, one or more printable semiconductor elements are contacted with a conformable transfer device having one or more contact surface(s). Contact established between the contact surface(s) and the printable semiconductor element(s) binds or associates the semiconductor element(s) to the contact surface(s). Optionally, conformal contact is established between the contact surface(s) and the printable semiconductor element(s) to facilitate binding or associate of these elements. At least a portion of the semiconductor element(s) disposed on the contact surface(s) is subsequently contacted with a receiving surface of the substrate. Optionally, the conformable transfer device also establishes conformal contact between the contact surface(s) having the semiconductor element(s) disposed thereon and at least a portion of the receiving surface. Separation of the contact surface of the conformable transfer device and the semiconductor element(s) transfers the semiconductor element(s) onto the receiving surface, thereby assembling the semiconductor element on the receiving surface of the substrate. In an embodiment preferred for device fabrication applications, printable semiconductor elements are positioned and/or integrated onto the substrate in selected regions and in selected spatial orientations. Optionally, the transfer process is repeated multiple times to provide patterning on large areas of a receiving surface of a substrate. In this embodiment, the transfer stamp having printable semiconductor elements is contacted with a different region of the receiving substrate for each successive patterning step. In this manner very large areas of a receiving surface may be pattern with semiconductor elements derived from a single mother wafer.

An advantage of the use of dry transfer contact printing methods is that patterns of printable semiconductors elements may be transferred and assembled onto substrate surfaces in a manner preserving selected spatial orientations of semiconductor elements which define the pattern. This is particularly beneficial for applications wherein a plurality of printable semiconductor elements are fabricated in well defined positions and relative spatial orientations which directly correspond to a selected device configuration or array of device configurations. Transfer printing methods are capable of transferring, positioning and assembling printable semiconductor elements and/o printable semiconductor containing functional devices including, but not limited to, transistors, optical waveguides, microelectromechanical systems, nanoelectromechanical systems, laser diodes, or fully formed circuits.

One unclaimed example provides selective transfer and assembly methods wherein some, but not all, of the printable semiconductors provided are transferred and assembled onto or into a substrate. In this embodiment, the conformable transfer device is capable of binding selectively to specific printable semiconductor elements provided. For example, the conformable transfer device may have a selected three dimensional relief pattern on its external surface having recessed regions and relief features. In this example, recessed regions and relief features may be positioned such that only selected printable semiconductor elements are contacted by one or more contact surfaces provided by the relief pattern, and subsequently transferred and assembled onto the substrate surface. Alternatively, the conformable transfer device may have a contact surface or plurality of contact surfaces having a selected pattern of binding regions, such as chemically modified regions having hydroxyl groups extending from the contact surface and/or regions having one or more adhesive surface coatings. In this example, only those semiconductor elements that are contacted with the binding regions on the contact surface(s) are bound to the transfer device, and subsequently transferred and assembled onto the substrate surface. An advantage of selective transfer and assembly methods is that a first pattern of printable semiconductor elements characterized by a first set of positions and spatial orientations may be used to generate a second pattern of printable semiconductor elements different from the first pattern and characterized by a second set of positions and spatial orientations, corresponding to a selected device configuration or array of device configurations.

An exemplary conformable transfer device comprises a dry transfer stamp, such as an elastomeric transfer stamp or composite, multi-layer patterning device. Conformable transfer devices useful for the present invention include patterning devices comprising a plurality of polymer layers as described in <CIT>, which is hereby incorporated by reference in its entirety. An exemplary patterning device useable in the methods of the present invention comprises a polymer layer having a low Young's Modulus, such as a poly(dimethylsiloxane) (PDMS) layer, preferably for some applications having a thickness selected from the range of about <NUM> micron to about <NUM> microns. Use of a low modulus polymer layer is beneficial because it provides transfer devices capable of establishing good conformal contact with one or more printable semiconductor elements, particularly printable semiconductor elements having curved, rough, flat, smooth and/or contoured exposed surfaces, and capable of establishing good conformal contact with substrate surfaces having a wide range of surface morphologies, such as curved, rough, flat, smooth and/or contoured substrate surfaces.

Optionally, transfer devices may further comprise a second layer having an external surface opposite an internal surface, and having a high Young's modulus, such as high modulus polymer layer, ceramic layer, glass layer or metal layer. In this example, the internal surface of the first polymer layer and the internal surface of the second high modulus layer are arranged such that a force applied to the external surface of the second high modulus layer is transmitted to the first polymer layer. Use of a high modulus second polymer layer (or backing layer) in transfer devices of the present invention is beneficial because it provides transfer devices having a net flexural rigidity large enough to provide good binding, transfer and assembly characteristics. For example, use of a transfer device having a net flexural rigidity selected from the range of about <NUM> × <NUM>-<NUM> Nm to about <NUM> × <NUM>-<NUM> Nm minimizes distortions of the positions of semiconductor elements and/or other structures bound to the contact surface(s) upon establishing conformal contact with a substrate surface. Use of a high modulus, rigid backing layer also is beneficial for preventing degradation of the printable semiconductor elements during transfer, for example by prevent cracking of the printable semiconductor layers. This attribute provides methods and devices of assembling printable semiconductor elements exhibiting high placement accuracy and good pattern fidelity. Transfer devices may comprise additional layers, including polymer layers, for providing easy handling and maintenance, good thermal properties and for providing uniform distribution of a force applied to the transfer device to the entire contact surface(s), as taught in <CIT> which is incorporated by reference in its entirety herein.

In another approach, the principles of `soft adhesion' are used to guide the transfer. Here, the viscoeleastic nature of the surface material on the transfer element leads to a peel force (i.e. the force that can lift objects from a surface) that depends on peel rate. At high peel rates, this force is large enough to remove objects from a substrate and transfer them onto a transfer element, even when the static surface energy of the transfer element is lower than that of the substrate. At low peel rates, this peel force is low. In some examples, by contacting a transfer element that supports an array of objects against a final substrate, and then peeling the element away slowly leads to the transfer of these objects from the transfer element to the substrate. This approach using controlled peeling rates can be used in combination with the other transfer approaches described herein.

Transfer devices may have a single continuous contact surface or a plurality of discontinuous contact surfaces. The contact surface(s) of transfer devices may be defined by a selected three-dimensional dimensional relief pattern having recessed regions and relief features having selected physical dimensions. Contact surfaces may be capable of binding printable semiconductor elements by van der Waals forces, covalent bonds, adhesive layers, chemically modified regions such as regions having hydroxyl groups disposed on their surfaces, dipole-dipole forces or combinations of these. Transfer devices may have contact surfaces having any area.

Printable semiconductor elements of the present invention may be fabricated from a wide range of materials. Useful precursor materials for fabricating printable semiconductor elements include semiconductor wafer sources, including bulk semiconductor wafers such as single crystalline silicon wafers, polycrystalline silicon wafers, germanium wafers; ultra thin semiconductor wafers such as ultra thin silicon wafers; doped semiconductor wafers such as P-type or N-type doped wafers and wafers with selected spatial distributions of dopants (semiconductor on insulator wafers such as silicon on insulator (e.g. Si-SIO<NUM>, SiGe); and semiconductor on substrate wafers such as silicon on substrate wafers and silicon on insulator. Further, printable semiconductor elements of the present invention may be fabricated from scrape or unused high quality or reprocessed semiconductor materials that are left over from semiconductor device processing using conventional methods. In addition, printable semiconductor elements of the present invention may be fabricated from a variety of nonwafer sources, such as a thin films of amorphous, polycrystalline and single crystal semiconductor materials (e.g. polycrystalline silicon, amorphous silicon, polycrystalline GaAs and amorphous GaAs) that is deposited on a sacrificial layer or substrate (e.g. SiN or SiO<NUM>) and subsequently annealed.

In another embodiment, the present invention provides a method for fabricating a printable semiconductor element connected to a mother wafer via one or more alignment maintaining elements comprising the steps of: (<NUM>) providing the mother wafer having an external surface, the wafer comprising an inorganic semiconductor material; (<NUM>) masking a selected region of the external surface by applying a mask; (<NUM>) etching the external surface of the wafer, thereby generating a relief structure and at least one exposed surface of the wafer, wherein the relief structure has a masked side and one or more unmasked sides; (<NUM>) isotropic etching the exposed surfaces of the wafer; and (<NUM>) stopping etching of the exposed structure so that complete release of the relief structure is prevented, thereby fabricating the printable semiconductor element connected to a mother wafer via one or more alignment maintaining elements. In one embodiment of this method the printable semiconductor element has a peanut shape with a first end and a second end, wherein the alignment maintaining elements connect the first and second ends of the printable semiconductor element to the mother wafer. In another embodiment of this method the printable semiconductor element has a ribbon shape with a first end and a second end, wherein the alignment maintaining elements connect the first and second ends of the printable semiconductor element to the mother wafer.

Referring to the drawings, like numerals indicate like elements and the same number appearing in more than one drawing refers to the same element. In addition, hereinafter, the following definitions apply:
"Printable" relates to materials, structures, device components and/or integrated functional devices that are capable of transfer, assembly, patterning, organizing and/or integrating onto or into substrates without exposure of the substrate to high temperatures (i.e. at temperatures less than or equal to about <NUM> degrees Celsius). Printable materials, elements, device components and devices are capable of transfer, assembly, patterning, organizing and/or integrating onto or into substrates via solution printing or dry transfer contact printing.

"Printable semiconductor elements" comprise semiconductor structures that are able to be assembled and/or integrated onto substrate surfaces, for example using by dry transfer contact printing and/or solution printing methods. In one embodiment, printable semiconductor elements are unitary single crystalline, polycrystalline or microcrystalline inorganic semiconductor structures. In this context of this description, a unitary structure is a monolithic element having features that are mechanically connected. Semiconductor elements may be undoped or doped, may have a selected spatial distribution of dopants and may be doped with a plurality of different dopant materials, including P and N type dopants. Printable semiconductor elements useful in many applications comprises elements derived from "top down" processing of high purity bulk materials, such as high purity crystalline semiconductor wafers generated using conventional high temperature processing techniques.

"Cross sectional dimension" refers to the dimensions of a cross section of device, device component or material. Cross sectional dimensions include width, thickness, radius, and diameter. For example, printable semiconductor elements having a ribbon shape are characterized by a length and two cross sectional dimensions; thickness and width. For example, printable semiconductor elements having a cylindrical shape are characterized by a length and the cross sectional dimension diameter (alternatively radius).

"Supported by a substrate" refers to a structure that is present at least partially on a substrate surface or present at least partially on one or more intermediate structures positioned between the structure and the substrate surface. The term "supported by a substrate" may also refer to structures partially or fully embedded in a substrate.

"Solution printing" is intended to refer to processes whereby one or more structures, such as printable semiconductor elements, are dispersed into a carrier medium and delivered in a concerted manner to selected regions of a substrate surface. In an exemplary solution printing method, delivery of structures to selected regions of a substrate surface is achieved by methods that are independent of the morphology and/or physical characteristics of the substrate surface undergoing patterning. Solution printing methods useable in the present invention include, but are not limited to, ink jet printing, thermal transfer printing, and capillary action printing.

"Substantially longitudinally oriented" refers to an orientation such that the longitudinal axes of a population of elements, such as printable semiconductor elements, are oriented substantially parallel to a selected alignment axis. In the context of this definition, substantially parallel to a selected axis refers to an orientation within <NUM> degrees of an absolutely parallel orientation, more preferably within <NUM> degrees of an absolutely parallel orientation.

"Stretchable" refers to the ability of a material, structure, device or device component to be strained without undergoing fracture. In an exemplary embodiment, a stretchable material, structure, device or device component may undergo strain larger than about <NUM>% without fracturing, preferably for some applications strain larger than about <NUM>% without fracturing and more preferably for some applications strain larger than about <NUM>% without fracturing.

The terms "flexible" and "bendable" are used synonymously in the present description and refer to the ability of a material, structure, device or device component to be deformed into a curved shape without undergoing a transformation that introduces significant strain, such as strain characterizing the failure point of a material, structure, device or device component. In an exemplary embodiment, a flexible material, structure, device or device component may be deformed into a curved shape without introducing strain larger than or equal to about <NUM> %, preferably for some applications larger than or equal to about <NUM> %, and more preferably for some applications larger than or equal to about <NUM> %.

"Semiconductor" refers to any material that is a material that is an insulator at a very low temperature, but which has a appreciable electrical conductivity at a temperatures of about <NUM> Kelvin. In the present description, use of the term semiconductor is intended to be consistent with use of this term in the art of microelectronics and electrical devices. Semiconductors useful in the present invention may comprise element semiconductors, such as silicon, germanium and diamond, and compound semiconductors, such as group IV compound semiconductors such as SiC and SiGe, group III-V semiconductors such as AlSb, AlAs, AIN, AIP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP, group III-V ternary semiconductors alloys such as AlxGa<NUM>-xAs, group II-VI semiconductors such as CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, and ZnTe, group I-VII semiconductors CuCI, group IV-VI semiconductors such as PbS, PbTe and SnS, layer semiconductors such as PbI<NUM>, MoS<NUM> and GaSe, oxide semiconductors such as CuO and Cu<NUM>O. The term semiconductor includes intrinsic semiconductors and extrinsic semiconductors that are doped with one or more selected materials, including semiconductor having p-type doping materials and n-type doping materials, to provide beneficial electrical properties useful for a given application or device. The term semiconductor includes composite materials comprising a mixture of semiconductors and/or dopants. Specific semiconductor materials useful for in some applications of the present invention include, but are not limited to, Si, Ge, SiC, AIP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AllnAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP. Porous silicon semiconductor materials are useful for applications of the present invention in the field of sensors and light emitting materials, such as light emitting diodes (LEDs) and solid state lasers. Impurities of semiconductor materials are atoms, elements, ions and/or molecules other than the semiconductor material(s) themselves or any dopants provided to the semiconductor material. Impurities are undesirable materials present in semiconductor materials which may negatively impact the electrical properties of semiconductor materials, and include but are not limited to oxygen, carbon, and metals including heavy metals. Heavy metal impurities include, but are not limited to, the group of elements between copper and lead on the periodic table, calicum, sodium, and all ions, compounds and/or complexes thereof. Gold is a specific heavy metal impurity which significantly degrades the electrical properties of semiconductors.

"Plastic" refers to any synthetic or naturally occurring material or combination of materials that can be molded or shaped, generally when heated, and hardened into a desired shape. Exemplary plastics useful in the devices and methods of the present invention include, but are not limited to, polymers, resins and cellulose derivatives. In the present description, the term plastic is intended to include composite plastic materials comprising one or more plastics with one or more additives, such as structural enhancers, fillers, fibers, plasticizers, stabilizers or additives which may provide desired chemical or physical properties.

"Dielectric" and "dielectric material" are used synonymously in the present description and refer to a substance that is highly resistant to flow of electric current. Useful dielectric materials include, but are not limited to, SiO<NUM>, Ta<NUM>O<NUM>, TiO<NUM>, ZrO<NUM>, Y<NUM>O<NUM>, SiN<NUM>, STO, BST, PLZT, PMN, and PZT.

"Polymer" refers to a molecule comprising a plurality of repeating chemical groups, typically referred to as monomers. Polymers are often characterized by high molecular masses. Polymers useable in the present invention may be organic polymers or inorganic polymers and may be in amorphous, semi-amorphous, crystalline or partially crystalline states. Polymers may comprise monomers having the same chemical composition or may comprise a plurality of monomers having different chemical compositions, such as a copolymer. Cross linked polymers having linked monomer chains are particularly useful for some applications of the present invention. Polymers useable in the methods, devices and device components of the present invention include, but are not limited to, plastics, elastomers, thermoplastic elastomers, elastoplastics, thermostats, thermoplastics and acrylates. Exemplary polymers include, but are not limited to, acetal polymers, biodegradable polymers, cellulosic polymers, fluoropolymers, nylons, polyacrylonitrile polymers, polyamide-imide polymers, polyimides, polyarylates, polybenzimidazole, polybutylene, polycarbonate, polyesters, polyetherimide, polyethylene, polyethylene copolymers and modified polyethylenes, polyketones, poly(methyl methacrylate, polymethylpentene, polyphenylene oxides and polyphenylene sulfides, polyphthalamide, polypropylene, polyurethanes, styrenic resins, sulphone based resins, vinyl-based resins or any combinations of these.

"Elastomer" refers to a polymeric material which can be stretched or deformed and return to its original shape without substantial permanent deformation. Elastomers commonly undergo substantially elastic deformations. Exemplary elastomers useful in the present invention may comprise, polymers, copolymers, composite materials or mixtures of polymers and copolymers. Elastomeric layer refers to a layer comprising at least one elastomer. Elastomeric layers may also include dopants and other non-elastomeric materials. Elastomers useful in the present invention may include, but are not limited to, thermoplastic elastomers, styrenic materials, olefenic materials, polyolefin, polyurethane thermoplastic elastomers, polyamides, synthetic rubbers, PDMS, polybutadiene, polyisobutylene, poly(styrenebutadiene-styrene), polyurethanes, polychloroprene and silicones.

The term "electromagnetic radiation" refers to waves of electric and magnetic fields. Electromagnetic radiation useful for the methods of the present invention includes, but is not limited to, gamma rays, X-rays, ultraviolet light, visible light, infrared light, microwaves, radio waves or any combination of these.

"Good electronic performance" and "high performance" are used synonymously in the present description and refer to devices and device components have electronic characteristics, such as field effect mobilities, threshold voltages and on - off ratios, providing a desired functionality, such as electronic signal switching and/or amplification. Exemplary printable semiconductor elements of the present invention exhibiting good electronic performance may have intrinsic field effect mobilities greater than or equal <NUM><NUM> V-<NUM> s-<NUM>, preferably for some applications greater than or equal to about <NUM><NUM> V-<NUM> s-<NUM>. Exemplary transistors of the present invention exhibiting good electronic performance may have device field effect mobilities great than or equal to about <NUM><NUM> V-<NUM> s-<NUM>, preferably for some applications greater than or equal to about <NUM><NUM> V-<NUM> s-<NUM>, and more preferably for some applications greater than or equal to about <NUM><NUM> V-<NUM> s-<NUM>. Exemplary transistors of the present invention exhibiting good electronic performance may have threshold voltages less than about <NUM> volts and/or on - off ratios greater than about <NUM> × <NUM><NUM>.

"Large area" refers to an area, such as the area of a receiving surface of a substrate used for device fabrication, greater than or equal to about <NUM><NUM> (<NUM> inches squared).

"Device field effect mobility" refers to the field effect mobility of an electrical device, such as a transistor, as computed using output current data corresponding to the electrical device.

"Conformal contact" refers to contact established between surfaces, coated surfaces, and/or surfaces having materials deposited thereon which may be useful for transferring, assembling, organizing and integrating structures (such as printable semiconductor elements) on a substrate surface. In one aspect, conformal contact involves a macroscopic adaptation of one or more contact surfaces of a conformable transfer device e to the overall shape of a substrate surface. In another aspect, conformal contact involves a microscopic adaptation of one or more contact surfaces of a conformable transfer device to a substrate surface leading to an intimate contact with out voids. The term conformal contact is intended to be consistent with use of this term in the art of soft lithography. Conformal contact may be established between one or more bare contact surfaces of a conformable transfer device and a substrate surface. Alternatively, conformal contact may be established between one or more coated contact surfaces, for example contact surfaces having a transfer material, printable semiconductor element, device component, and/or device deposited thereon, of a conformable transfer device and a substrate surface. Alternatively, conformal contact may be established between one or more bare or coated contact surfaces of a conformable transfer device and a substrate surface coated with a material such as a transfer material, solid photoresist layer, prepolymer layer, liquid, thin film or fluid.

"Placement accuracy" refers to the ability of a transfer method or device to transfer a printable element, such as a printable semiconductor element, to a selected position, either relative to the position of other device components, such as electrodes, or relative to a selected region of a receiving surface. "Good placement" accuracy refers to methods and devices capable of transferring a printable element to a selected position relative to another device or device component or relative to a selected region of a receiving surface with spatial deviations from the absolutely correct position less than or equal to <NUM> microns, more preferably less than or equal to <NUM> microns for some applications and even more preferably less than or equal to <NUM> microns for some applications.

"Fidelity" refers to a measure of how well a selected pattern of elements, such as a pattern of printable semiconductor elements, is transferred to a receiving surface of a substrate. Good fidelity refers to transfer of a selected pattern of elements wherein the relative positions and orientations of individual elements are preserved during transfer, for example wherein spatial deviations of individual elements from their positions in the selected pattern are less than or equal to <NUM> nanometers, more preferably less than or equal to <NUM> nanometers.

"Young's modulus" is a mechanical property of a material, device or layer which refers to the ratio of stress to strain for a given substance. Young's modulus may be provided by the expression; <MAT> wherein E is Young's modulus, L<NUM> is the equilibrium length, ΔL is the length change under the applied stress, F is the force applied and A is the area over which the force is applied. Young's modulus may also be expressed in terms of Lame constants via the equation: <MAT> wherein λ and µ are Lame constants. High Young's modulus (or "high modulus") and low Young's modulus (or "low modulus") are relative descriptors of the magnitude of Young's modulus in a give material, layer or device. In the present invention, a High Young's modulus is larger than a low Young's modulus, preferably about <NUM> times larger for some applications, more preferably about <NUM> times larger for other applications and even more preferably about <NUM> times larger for yet other applications.

The methods of the present invention are capable of generating high performance electronic and optoelectronic devices and arrays of devices, such as thin film transistors on flexible plastic substrates.

<FIG> schematically illustrates exemplary methods for producing and assembling printable semiconductor elements comprising ribbons of single crystalline silicon. The process begins by providing a silicon-on-insulator (SOI) substrate <NUM> having a thin single crystalline silicon layer <NUM>, a buried SiO<NUM> layer <NUM> and Si handling layer <NUM>. Optionally, the surface native oxide layer on thin single crystalline silicon layer <NUM>, if present, may be removed, for example by exposing the surface of the SOI substrate <NUM> to dilute (<NUM>%) HF. Upon adequately stripping the native oxide layer, selected regions of external surface <NUM> of SOI substrate <NUM> are masked, thereby forming a pattern of mask elements <NUM>, masked regions <NUM> and exposed surface regions <NUM> on external surface <NUM>. In the embodiment shown in <FIG>, external surface <NUM> is patterned with rectangular aluminum and gold surface layers which provide mask elements <NUM> that are capable of inhibiting etching of the masked regions <NUM> of external surface <NUM>. Mask elements <NUM> may have any size and shape including, but not limited to, square, rectangular, circular, elliptical, triangular shapes or any combinations of these shapes. In an exemplary embodiment, patterns of Al/Au layers providing mask elements having desired geometries are fabricated using microcontact printing, nanocontact printing techniques, or photolithography, and etching methods (TFA for Au; AL-<NUM> premixed Cyantec etchant for Al). Deposition of mask elements comprising thin metal films may be provided by an electron beam evaporator, such as a Temescal BJD1800, for example by sequential deposition of Al (<NUM>; <NUM>/s) and then Au (<NUM>; <NUM>/s).

External surface <NUM> of SOI substrate <NUM> is anisotropically etched downward. As shown in <FIG>, although material is selectively removed from exposed surface regions <NUM>, mask elements <NUM> prevent etching of masked regions <NUM>, thereby generating a plurality of relief features <NUM> comprising single crystalline silicon structures having slightly angled side walls <NUM>. In an exemplary embodiment wherein relief features have side walls <NUM> having a thickness <NUM> of about <NUM> nanometers, exposed surface regions <NUM> are exposed to tetramethylammonium hydroxide (TMAH) for about <NUM> minutes. In this embodiment, etching generates smooth sidewalls on relief features <NUM> of single crystal silicon having Al/Au mask elements <NUM>, preferably with deviations from average surface positions of less than <NUM> nanometers. Relief features <NUM> may be lifted off of the substrate <NUM> when the underlying SiO<NUM> layer <NUM> is partially or completely isotropically etched away, for example using concentrated (<NUM>%) HF. Liftoff of the relief features <NUM> generates printable semiconductor elements <NUM> comprising discrete single crystalline silicon structures having one surface covered by a mask element. Mask elements <NUM>, Al/Au layers in the present example, may be removed or may be integrated directly into a final device structure, for example, as the source and drain electrodes in a thin film transistor. As shown in <FIG>, the printable semiconductor elements <NUM> may be assembled onto the receiving surface of substrate surface <NUM>, such as a plastic substrate, by either dry transfer contact printing techniques (schematically shown by arrow <NUM>) or by solution casting methods (schematically shown by arrow <NUM>). Both assembly methods may be carried out at room temperature in an ambient environment and, therefore, are compatible with a wide range of substrates, including low cost, flexible plastic substrates.

Use of dry transfer contact printing methods to assemble printable semiconductor elements has the benefit of taking advantage of the known orientations and positions of the printable semiconductor elements just prior to their liftoff from the SOI substrate. In this case, procedures similar to those of soft lithographic transfer printing techniques are used to move the printable semiconductor elements from the SOI (after etching away the SiO<NUM> but before lifting off the silicon) to desired locations on the device substrate. In particular, a conformable elastomeric transfer element picks up the objects from the SOI surface and transfers them to a desired substrate. Similarly, the printable semiconductor elements can be directly transferred onto thin plastic substrates by Au cold welding using receptacle pads defined on the surface of the target substrate.

In an exemplary method, at least a portion of printable semiconductor elements <NUM> are brought into conformal contact with the contact surface <NUM> of a conformable transfer device <NUM>, such as an elastomeric transfer stamp, polymer transfer device or composite polymer transfer device, thereby bonding at least a portion of printable semiconductor elements <NUM> onto the contact surface <NUM>. Printable semiconductor elements <NUM> disposed on the contact surface <NUM> of conformable transfer device <NUM> are brought into contact with a receiving surface of substrate <NUM>, preferably in a manner establishing conformal contact between contact surface <NUM> and the receiving surface of substrate <NUM>. Contact surface <NUM> is separated from printable semiconductor elements <NUM> in contact with receiving surface of substrate <NUM>, thereby assembling printable semiconductor elements <NUM> onto the receiving surface. This embodiment is capable of generating a pattern on the receiving surface comprising printable semiconductor elements <NUM> in well defined positions and spatial orientations. In the embodiment shown in <FIG>, printable semiconductor elements <NUM> are operationally connected to gold pads <NUM> present on the receiving surface of substrate <NUM>.

<FIG> provides a schematic diagram illustrating a selective dry transfer contact printing method for assembling printable semiconductor element on a receiving surface of a substrate. A plurality of printable semiconductor elements <NUM> are fabricated on a mother substrate <NUM> in a first pattern <NUM> of printable semiconductor elements <NUM> characterized by well defined positions and spatial orientations. A conformable transfer device <NUM> having a contact surface <NUM> with a plurality of discrete binding regions <NUM> is brought into conformal contact with at least a portion of printable semiconductor elements <NUM> on mother substrate <NUM>. Binding regions <NUM> on contact surface <NUM> are characterized by an affinity for printable semiconductor elements <NUM>, and may be chemically modified regions, such regions having hydroxyl groups extending from the surface of a PDMS layer, or regions coated with one or more adhesive layers. Conformal contact transfers at least a portion of printable semiconductor elements <NUM> which contact binding regions <NUM> on contact surface <NUM>. Printable semiconductor elements <NUM> transferred to contact surface <NUM> are brought into contact with receiving surface <NUM> of substrate <NUM>, which may be a flexible substrate such as a plastic substrate. Subsequent separation of semiconductor elements <NUM> and contact surface <NUM> results in assembly of the semiconductor elements <NUM> on receiving surface <NUM> of substrate <NUM>, thereby generating a second pattern <NUM> of printable semiconductor elements characterized by well defined positions and spatial orientations different from the first pattern of printable semiconductor elements <NUM>. As shown in <FIG>, the printable semiconductor elements <NUM> that remain on mother substrate <NUM> are characterized by a third pattern <NUM> of printable semiconductor elements different from first and second patterns of printable semiconductor elements. Printable semiconductor elements <NUM> comprising the third pattern <NUM> may be subsequently transferred to and/or assembled onto substrate <NUM> or another substrate using the printing methods of the present invention, including selective dry transfer methods.

<FIG>, are schematic diagrams showing devices, device configurations and device components useful in selective dry transfer contact printing methods. <FIG> shows a plurality of printable semiconductor elements <NUM> on a mother substrate <NUM>, wherein selected printable semiconductor elements <NUM> have one or more adhesive coatings <NUM>. As shown in <FIG>, adhesive coatings <NUM> are provided in a well defined pattern. <FIG> shows a conformable transfer device <NUM> having a contact surface <NUM> with a plurality of discrete binding regions <NUM> provided in a well defined pattern. <FIG> shows a conformable transfer device <NUM> having a three dimensional relief pattern <NUM> comprising relief features <NUM> provided in a well defined pattern. In the embodiment shown in <FIG>, relief pattern <NUM> provides a plurality of contact surfaces <NUM> that may be optionally coated with one or more adhesive layers. Patterns of adhesive coatings <NUM>, binding regions <NUM> and relief features <NUM> preferably corresponding to relative positions and spatial orientations of printable semiconductor elements <NUM> in device configurations or device array configurations, such as thin film transistor array configurations.

Use of dry transfer printing methods are useful in the present invention for assembling, organizing and integrating printable semiconductor elements on substrates having a wide range of compositions and surface morphologies, including curved surfaces. To demonstrate this functional, semiconductor elements comprising silicon photodiodes were printed directly (i.e. no adhesive) onto the curved surfaces of a variety of optical lenses using dry transfer printing methods employing an elastomeric stamp. <FIG> provides a photograph of an array of photodiodes printed onto a spherical surface of a polycarbonate lens (FL <NUM>). <FIG> provides a scanning electron micrograph of an array of photodiodes printed onto the curved surface of a spherical glass lens (FL <NUM>). Contrast in the image provided in <FIG> is slightly enhanced to show p-doped regions. <FIG> provides a plot of electric current (µA) verse bias potential (volts) illustrating the light response of the photodiodes pictured in <FIG>.

<FIG> show a preferred shape of a printable semiconductor element for assembly methods of the present invention using dry transfer contact printing. <FIG> provides a perspective view and <FIG> provides a top plan view. Printable semiconductor element comprises a ribbon <NUM> extending along a central longitudinal axis <NUM> having a first end <NUM>, center region <NUM> and second end <NUM>. As shown in <FIG>, the width of ribbon <NUM> selectively varies along its length. Particularly, first and second ends <NUM> and <NUM> are wider than center region <NUM>. In an exemplary method, ribbon <NUM> is formed by etching mother substrate <NUM>. In this embodiment, mother substrate is isotropically exposed to an etchant until ribbon <NUM> is only attached to mother substrate <NUM> by two alignment maintaining elements comprising sacrificial layers <NUM> proximate to first and second ends <NUM> and <NUM>. At this point in the fabrication process the etching process is stopped, and the ribbon <NUM> is brought into contact with and/or bonded to a conformable transfer device. Sacrificial layers <NUM> are broken and ribbon <NUM> is released as the transfer device is moved away from mother substrate <NUM>. This method may also be applied to dry transfer contact printing of a plurality of printable semiconductor elements having shapes as shown in <FIG>. An advantage of this method of the present invention is that the orientations and relative positions of a plurality of ribbons <NUM> on mother substrate <NUM> may be precisely preserved during transfer, assembly and integration steps. Exemplary ranges for the thickness of the sacrificial layers are ~<NUM> down to -<NUM> with ribbons widths between ~<NUM> and <NUM>. Interestingly, the cleavage of the ribbons typically occurs at the extremity of the objects (very close to the point/edge where the ribbons are attached to the mother wafer). Wide ribbons usually do not distort during the lift-off process are they are bonded to the stamp.

<FIG> show a preferred shape of a printable semiconductor element for assembly methods of the present invention using dry transfer contact printing. <FIG> provides a perspective view and <FIG> provides a top plan view. Printable semiconductor element comprises ribbons <NUM> extending along a parallel central longitudinal axes <NUM>. Ribbons <NUM> are held in a selected position and orientation by alignment maintaining elements <NUM> which connect at least on end of the ribbon along the central longitudinal axes <NUM> to mother substrate <NUM>. alignment maintaining elements <NUM> are fabricated during patterning of ribbons <NUM> by not defining one or both ends of the ribbon along their central longitudinal axes. Alignment maintaining elements <NUM> are broken and ribbons <NUM> are released upon contact with the ribbons with the contact surface of a transfer device and subsequent movement away from mother substrate <NUM>.

<FIG> presents an image of transferred printable semiconductor elements comprising single crystalline silicon microstrips on a PDMS coated polyimide sheet having a thickness of about <NUM> microns. The top inset pictures illustrate the intrinsic flexibility of this system. The bottom inset shows a top view micrograph of printable silicon dense microstrips (<NUM> microns wide, ~<NUM> microns spaced apart) cold welded on a thin Ti/Au coated Mylar sheet. As shown in <FIG>, the printable semiconductor elements comprising silicon microstrips are well aligned and transferred with controlled orientation. No cracking of the printable semiconductor elements induced by assembly was observed upon careful examination using scanning electron microscopy, even when the substrate was bent significantly. Similar results were obtained (without the need of an elastomeric layer) using a Au coated thin Mylar sheet as illustrated by the bottom inset micrograph picture. A coverage density close to <NUM>% can be achieved in this manner.

The following references relate to self assembly techniques which may be used to transfer, assembly and interconnect printable semiconductor elements via contact printing and/or solution printing techniques: (<NUM>) "<NPL>; (<NUM>) "<NPL>; (<NUM>) "<NPL>; and (<NUM>) "<NPL>.

When a group of materials, compositions, components or compounds is disclosed herein, it is understood that all individual members of those groups and all subgroups thereof are disclosed separately. When a Markush group or other grouping is used herein, all individual members of the group and all combinations and subcombinations possible of the group are intended to be individually included in the disclosure. Every formulation or combination of components described or exemplified herein can be used to practice the invention, unless otherwise stated. Whenever a range is given in the specification, for example, a temperature range, a time range, or a composition range, all intermediate ranges and subranges, as well as all individual values included in the ranges given are intended to be included in the disclosure.

As used herein, "comprising" is synonymous with "including," "containing," or "characterized by," and is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. As used herein, "consisting of" excludes any element, step, or ingredient not specified in the claim element. As used herein, "consisting essentially of" does not exclude materials or steps that do not materially affect the basic and novel characteristics of the claim. In each instance herein any of the terms "comprising", "consisting essentially of" and "consisting of" may be replaced with either of the other two terms.

<FIG> presents an optical micrograph image of a thin film transistor having a printable semiconductor element. The illustrated transistor <NUM> comprises source electrode <NUM>, drain electrode <NUM>, printable semiconductor element <NUM>, dielectric (not shown in the micrograph in <FIG>) and gate electrode (also not shown in the micrograph in <FIG>). The thin film transistor is supported by a substrate comprising of a Mylar sheet coated with indium tin oxide (ITO, -<NUM> nanometers thick) as a gate and a photocured epoxy as a gate dielectric (SU8-<NUM>; Microchem Corp). The capacitance of the dielectric (<NUM>. 85nF/cm2) was evaluated using capacitor test structures formed near the device. This device uses a solution cast printable semiconductor element comprising a ~<NUM> millimeter long, <NUM> micron width and <NUM> nanometer thick microstrip fabricated from a p-doped SOI wafer (Soitec) with a <NUM> nanometer device layer thickness and resistivity of <NUM>-<NUM> ohm cm. A <NUM> nanometer thick layer of SiO<NUM> was grown on top of the silicon by dry oxidation in a horizontal quartz tube furnace. Source and drain electrodes of Al (<NUM> nanometer) / Au (<NUM> nanometer) where defined by liftoff techniques. The semiconductor channel length is <NUM> microns and the width is <NUM> microns.

<FIG> and <FIG> show electrical measurements collected from thin film transistors having a printable semiconductor element. The device operates similarly to a back gated SOI device with a top contact configuration. The semiconductor uses a width equal to a <NUM> microns microstrip of single crystal silicon in a channel whose length is equal to <NUM> microns. The printable semiconductor element in this case was patterned by solution casting methods. The source/drain contacts were defined by photolithography and lift off.

<FIG> provides a plot showing current-voltage (IV) characteristics of a device made on a pre-oxidized Si wafer. <FIG> provides a plot showing transfer characteristics measured at VDS=<NUM> V of a device made on a Mylar sheet coated with ITO gate and polymer dielectric. The slope of this curve defines an effective device mobility (using the physical width of the source and drain electrodes, which is equal to the width of the semiconductor element microstrip in this case) of <NUM><NUM>/Vs. The Al/Au metallization for the contacts to the printable semiconductor element provides reasonably low resistance Schottky barrier contacts to the silicon, as expected for an Al (work function of <NUM>. 2eV) metallization on p-doped silicon. Aluminum is well known to diffuse rapidly into silicon, but no special care was taken to avoid localized aluminum-silicon interactions as no post metallization high temperature annealing step was carried out. The on/off ratio of this device is slightly lower than <NUM><NUM>. Analysis of the transfer characteristic of <FIG> indicates a linear field effect mobility of <NUM><NUM> V-<NUM> s-<NUM> using a parallel plate model for the dielectric capacitance. This analysis ignores the effects of contacts and processing induced changes in the threshold voltage.

Even with perfect contacts, there are theoretical arguments to suggest that transistors which incorporate very high aspect ratio (i.e. ultra large length to width ratios) semiconducting elements in the channel region (i.e. nanotubes or nanowires) will have responses that are different than those of conventional devices. To avoid these effects, we chose printable semiconductor elements comprising microstrips having widths on the same order of magnitude with the transistor channel length. The properties (mobilities, normalized transconductance, on/off ratio) observed here are ~<NUM>/<NUM> to those of thin film transistors made on the SOI substrate after etching of the Si but before liftoff. In these measurements the buried SiO<NUM> oxide acts as the dielectric and the silicon supporting substrate acts as the gate electrode. This result demonstrates that the processing steps used to produce the printable semiconductor elements and to transfer it to the device substrate do not alter significantly the properties of the silicon or its surfaces that result from the initial patterning and silicon etching steps. It also indicates that the van der Waals interface with the SU8 dielectric is capable of supporting good device properties.

A principle advantage of the fabrication method of the present example is that it separates the crystal growth and processing of the silicon from the plastic substrate and other components of the devices. In addition, the methods of processing printable semiconductor elements of the present invention are highly flexible in the processing sequences and in the materials choices that are possible. For example, an SiO<NUM> layer can be formed on one side of the silicon (by, for example, growing a thermal oxide before lifting off the Si elements or lifting the SOI buried oxide together with the Si device layer) to yield an integrated dielectric, in a strategy similar to that for the integrated source/drain metallization demonstrated here. A dielectric introduced in this manner may avoid the significant challenges that can be associated with leakage, hysteresis, doping, trapping, etc. in many solution cast thin dielectrics on plastic substrates.

<FIG> provide a schematic diagram illustrating a method for making an array of thin film transistors having composite printable semiconductor elements. As shown in <FIG>, gate electrodes <NUM> are deposited on the surface <NUM> of a thin sheet of a flexible substrate, such as Kapton, Mylar or PET. Gate electrodes may be patterned on the flexible substrate by any means known in the art including but not limited to photolithography, microtransfer printing, nanotransfer printing, soft lithography or combinations of these. As shown in <FIG>, the method further comprises the step of fabricating a plurality of composite printable semiconductor elements <NUM> comprising single crystalline silicon structures <NUM> operationally connected to a SiO<NUM> dielectric element <NUM>. As illustrated in <FIG>, composite printable semiconductor elements <NUM> have a ribbon shape extending a selected length <NUM> along a central longitudinal axis <NUM>. Composite printable semiconductor element <NUM> has a selected thickness <NUM> and a width that varies as a function of thickness.

As shown in <FIG>, the method further comprises the step of assembling composite printable semiconductor elements <NUM> onto gate electrodes <NUM> and substrate <NUM> via dry transfer contact printing or solution printing. Composite printable semiconductor elements <NUM> are oriented such that SiO<NUM> dielectric elements <NUM> are in contact with gate electrodes <NUM>. As shown in <FIG>, the method further comprises the step of spin coating a thin layer of positive photoresist <NUM> on the patterned surface of substrate <NUM>. Alternatively, the thin layer of positive photoresist <NUM> may be applied to the pattern surface of substrate <NUM> using a roller. Regions of photoresist <NUM> not masked by gate electrodes <NUM> are exposed to a beam of electromagnetic radiation transmitted through underside <NUM> of substrate <NUM>. Use of an optically transmissive substrate <NUM> is preferred for this method, particularly a substrate <NUM> that is at least partially transparent in ultraviolet and/or visible regions of the electromagnetic spectrum. As shown in <FIG>, the method further comprises the step of developing the thin photoresist layer. As shown in this figure, the regions of thin photoresist layer <NUM> that are shadow masked by the gate electrodes are undeveloped. As shown in <FIG>, the method further comprises the step of dry or wet etching the integrated SiO<NUM> dielectric, thereby opening contacts for source and drain electrodes. In the embodiment illustrated by <FIG> this is achieved by exposing the patterned surface of substrate <NUM> to a CF<NUM> plasma. As shown in <FIG>, the method further comprises the step of defining source and drain electrodes by shadow mask evaporation. The alignment of semiconductor elements, source electrodes and drain electrodes does not need to be very precise because the semiconductor channels will be defined in the next fabrication step. As shown in <FIG>, the method further comprises the step of defining the semiconductor channel by lifting off the positive resist, for example by exposure to a solvent such as acetone.

<FIG> provide diagrams illustrating a method for making a printable device comprising integrated gate electrode, gate dielectric, semiconductor, source electrode and drain electrode. As shown in <FIG>, a high quality gate dielectric is grown by thermal oxidation of the surface of a SOI wafer. Next, the gate electrode material (such as metal or doped poly-silicon) is deposited. Selected regions of the top surface are subsequently masked using for example a lithography process. In one embodiment, an array of identical patterns with controlled spacing will be defined in a single masking step. Printable semiconductor elements are then fabricated by anisotropically wet and/or dry etching. Preferentially, three different selective etching processes are carried out sequentially to etch away the exposed areas of the gate electrode material, the gate dielectric and the top silicon layer.

A lithography process, as shown in <FIG>, is used to define the channel of the transistors. In this process step, the exposed areas of the gate electrode material are etched away (dry or wet etching). As shown in <FIG>, the photo-resist is then heated above its glass transition, thereby initiating a reflow process. The reflowing distance of the photoresist can be selected by carefully selecting an appropriate thickness of the photo-resist layer, the glass transition temperature of the photo-resist layer or the temperature and duration of the reflow process. The exposed areas of the gate dielectric are then etched using an HF solution.

Next, a metallization process, as shown in <FIG>, is carried out, followed by lifting off the metal deposited onto the photoresist to complete the fabrication of a printable device. The source and drain electrodes are self aligned with the gate, and the spacing between source and drain electrodes may be selected by the adjusting the different parameters, such as temperature and duration, of the reflow process.

The printable device shown in <FIG> may be transferred and assembled onto a substrate, such as a plastic substrate, by the dry transfer or solution printing methods of the present invention. The self aligned process illustrated in <FIG> presents a simple way to integrate all the elements necessary for the realization of a printable device, such as a MOSFET device. A significant advantage of this fabrication method of the present invention is that all processes steps which require temperatures incompatible with plastic substrates (e.g. requiring temperature > about <NUM> Celsius) may be carried on the SOI substrate prior to lifting off and transferring the device to the substrate. For example, additional processing steps such as doping of the source and drain contact areas, formation of silicide layers, and high temperature annealing of the device could be performed prior to transferring the elements onto a plastic substrate.

The methods of the present invention provide a new printing-based fabrication platform for making high performance integrated microelectronic devices and device arrays. Advantages of the present approach to macroelectronic and microelectronic technologies over conventional processing methods include compatibility with a wide range of substrate materials, physical dimensions and surface morphologies. In addition, the present printing-based approach enables a low cost, high efficiency fabrication pathway for making integrated microelectronic devices and device arrays on large areas of substrates that is compatible with pre-exisiting high throughput printing instrumentation and techniques.

The advanced information technologies that shape the structure of modern society depend critically on the use of microelectronic devices, ones that involve ever increasing higher densities of integration. From the initial circuits (ICs) of the late <NUM>'s, ones that incorporated fewer than <NUM> transistors, current state of the art ICs now integrate millions transistors in an essentially equivalent sized package. There has been an increased interest, however, in developing new device form factors, ones in which the capabilities of semiconductor devices are embedded in structure involving either large area and/or flexible materials supports using fabrication method that serve to in an attempt to decrease costs while maintaining high device performance levels. Such devices technologies could find wide application as active matrix pixel display drivers and components of RF identification tags. Recent reports detail the use of solution processing methods to construct models of such circuits, notably ones based on semiconductor nanowires (NWs) or networked nanotubes. Although functional devices prepared in this way are promising, they are generally characterized by significantly lower levels of device performance compared to conventional high temperature semiconductor processing approaches. For example, field effective mobilites ranging from ~<NUM><NUM>/Vs and ~<NUM><NUM>/Vs are reported for thin film transistors (TFTs) prepared using solution processing methods.

In one aspect, the present invention provides a "top down" fabrication strategy using microstructured single-crystalline silicon (µs-Si) ribbons harvested from silicon-on insulator wafers for use in ultra-high performance TFTs. This fabrication technique is compatible with respect to a range of useful semiconductor materials, and has been successfully adapted to other industrially useful semiconductor materials that include GaN, InP and GaAs.

In this example we demonstrate a number of important processing steps useful in the implementation of this technology, including fabrication methods which allow the selective transfer and accurate registration of silicon ribbons across large substrate areas, and versatile printing procedures applicable to both rigid (i.e. glass) and flexible plastic substrates. We specifically report here two methods that can be used to selectively remove µs-Si from an SOI wafer and subsequently transfer them in patterned forms onto a plastic substrate. The processes, for convenience referred to have as Method I (<FIG>) and Method II (<FIG>), use different mechanisms of adhesive bonding to affect the printing-based pattern transfer of the µs-Si. Method I exploits physical bonding between a molded Sylgard <NUM> poly(dimethylsiloxane) (PDMS) stamp (a new experimental, high modulus PDMS product provided by the Dow Corning Corp. ) and µs-Si objects. Method II uses a recently developed masterless soft-lithography technique to chemically bond the µs-Si to a PDMS coated substrate.

<FIG> provides a schematic diagram showing a processing method of the present invention (Method I) for patterning µs-Si elements onto a plastic substrate. In the present example, the plastic substrate comprised a poly(ethyleneterepthalate) (PET) sheet. A peanut shaped photoresist pattern is developed on top of a SOI substrate using standard photolithography techniques. Plasma etching, followed by resist stripping, yields µs-Si "peanuts" that are supported on top of a buried oxide layer. The sample is then etched incompletely using HF to give undercut peanuts held only by a residual oxide layer present at the dumbbell ends of the µs-Si. The SOI wafer is then laminated with a hard <NUM> PDMS stamp molded with features corresponding to the latent image of the desired pattern transfer. The raised features of the stamp correspond to regions where µs-Si is removed selectively from the SOI surface due to strong autoadhesion to the PDMS. The stamp, after pealing it away from the SOI wafer, is then placed in contact with a poly(ethyleneterepthalate) (PET) sheet coated with polyurethane (PU) that had been partially cured using a UV lamp. A bar coating technique is used to deposit the PU adhesion level to ensure a uniform coating thickness over the large area of the (<NUM><NUM>) plastic substrate. The µs-Si on the stamp is then placed in contact with the PU coated side of the plastic sheet, a second UV/Ozone exposure is then preformed from the PET side of the sandwich to fully cure the PU and enhance its bonding to the µs-Si. Pealing the stamp from the plastic substrate results in the detachment of the microstructured silicon from the PDMS, thus completing the transfer to the PU coated substrate.

<FIG> provides a schematic diagram illustrating an alternative processing method of the present invention (Method II) for patterning µs-Si elements onto a plastic substrate. In the present example, the plastic substrate comprised a poly(ethyleneterepthalate) (PET) sheet. This recently reported Decal Transfer Lithography (DTL) technique effects the pattern transfer using a flat, unmolded PDMS slab that is photochemically treated to provide spatially modulated strengths of adhesion. An UV/Ozone (UVO) treatment is patterned across the surface of a slab of conventional Sylgard <NUM> PDMS using a microreactor photomask to pattern the UVO modification with high spatial resolution. After exposure, the photochemically modified PDMS coated PET is placed in contact with a peanut presenting SOI wafer and heated to <NUM> for <NUM> minutes. The fabrication of the peanut shapes on the SOI wafer followed the same procedures of Method I (see <FIG>), with the addition of evaporating a thin film of SiO<NUM> (<NUM>) onto the surface after the HF etching step. This layer facilitates strong chemical bonding to the PDMS. After heating, the PDMS is pealed from the SOI, giving a patterned transfer of µs-Si to the UVO modified regions of the PDMS.

<FIG> shows the design of the so-called peanut shaped µs-Si objects used in methods of the present invention. Inset optical image in <FIG> shows the optimized HF etching condition where the buried oxide under the channel is removed while a sacrificial SiO2 portion remains. The peanut shape is particularly beneficial because its ends are slightly wider than the body of the structure. Upon etching the underlying oxide layer in an HF solution, the timing can be optimized such that the oxide layer under the center is completely removed while a sacrificial portion of SiO<NUM> still remains at either end (the dumbbell region seen in the inset image of <FIG>). It is this residual SiO<NUM> layer that holds the µs-Si in its original position. Without this oxide bridge layer, the order of the µs-Si created on the SOI wafer by photolithography is susceptible to lost. <FIG> shows an example of lost of this order when the Si objects are overetched in HF solution. As shown in <FIG>, Si objects to start to float in the HF solution when the sample was over etched in HF solution. When the µs-Si is removed from the SOI wafer by either Method I or II, fracture occurs at the edges of the sacrificial region.

<FIG> shows a series of micrographs that depicts the progression of each step of the µs-Si transfer as effected using Method I. <FIG> shows the µs-Si on the SOI wafer after optimized undercut HF etching. <FIG> shows the SOI wafer after the PDMS stamp removed a portion of the µs-Si. As shown in <FIG>, the PDMS stamp removes a portion of the µs-Si, thereby leaving the neighboring regions intact on the SOI. Since the unused microstructured silicon objects on the SOI wafer are retained at their original positions, they can be picked up by a stamp and transferred in subsequent printing steps (as discussed below). <FIG> shows µs-Si structures transferred onto the PDMS stamp. The missing center of each end of the µs-Si ribbons reveals the pattern of the fracture occurs during the transfer of the microstructured silicon from the SOI to PDMS stamp. <FIG> shows a representative result for a second transfer of the µs-Si (this time from the PDMS stamp to the PU coated plastic substrate) wherein the µs-Si that adhered to the PU support on the plastic.

Multiple transfers are possible from a small PDMS stamp to a larger plastic surface. <FIG> provide optical images of the selective transfer of the µs-Si onto PU/PET sheet by <NUM> PDMS stamp. As shown in <FIG>, a large area (15x15 cm) transfer where the µs-Si was sparsely transferred onto a plastic substrate by multiple transfers using a 8x8 cm stamp. Each pixel in the image is of the same configuration as that shown in <FIG> and follows the same protocol described for <FIG>. The inset of <FIG> shows a more complex molded form, a "DARPA macroE" lettering composed of peanut µs-Si objects smaller in size than those highlighted in <FIG>. The high pattern fidelity of the transfer is illustrated by the qualities of the objects defining the letter "A" (circle of inset image) as shown in <FIG>. These data demonstrate that only those areas directly touched by the stamp ultimately transfer to the plastic substrate. We note that this transfer is more difficult using conventional Sylgard <NUM> PDMS for two reasons. First, the Sylgard <NUM> sags when the separation distances between features exceeds twenty times the feature height. The examples shown here embrace such design rules and thus precludes high-fidelity transfers using the lower modulus polymer. Second, we also found that the Sylgard <NUM> sometimes does not have enough adhesive force to pickup every µs-Si peanut from the SOI wafer and defects are observed in some applications using stamps prepared form this polymer. The <NUM> PDMS from Dow Corning does not sag appreciably even at an aspect ratios of <NUM>:<NUM> and, perhaps more importantly, its adhesion to the µs-Si objects is stronger than is that of the <NUM> PDMS.

An example of a µs-Si transfer carried out using Method II is shown in <FIG> is an optical micrograph of a section of a Sylgard <NUM> coated PET substrate to which the µs-Si has been chemically bonded and subsequently transferred. A higher magnification image of the µs-Si transferred in this way is shown in <FIG>. It should be noted that the dimensions of the peanuts used in this demonstration are relatively small with ribbon widths of <NUM>. We found, interestingly, that these smaller features have a different fracture point when they are removed from the SOI wafer. In the blowup of <FIG>, one also notes that the PDMS surface is also no longer flat. The reason for this is because of the fact that sections of the PDMS are in fact reciprically transferred to the SOI, being ripped out of the bulk in contacting regions actived by the patterned UVO treatment, regions where the PDMS sagged and touched the wafer surface between the peanuts.

<FIG> illustrates an exemplary device geometry of a device fabricated using the peanut shaped µs-Si based on a transfer using Method I. To construct these devices an Indium-Tin-Oxide (ITO) coated PET sheet is used as the substrate. The ITO served as the gate electrode and diluted SU-<NUM><NUM> (measured capacitance=<NUM> nF/cm<NUM>) is employed as a gate dielectric. <FIG> provides I-V curves of µs-Si TFTs at a range of gate voltage (Vg= -<NUM> V to <NUM> V). As shown in <FIG>, these plastic supported, peanut shaped µs-Si TFTs show an accumulation mode n-channel transistor behavior. The channel length of the device, as shown in the inset image of <FIG>, is <NUM> and the width of the device is <NUM>. <FIG> shows the transfer characteristics, measured at a constant source-drain voltage (Vsd =1V), indicated the effective mobility was <NUM><NUM>/Vs. The inset in <FIG> shows an optical micrograph of actual device of the present invention. The transfer characteristics indicated that the threshold voltage (Vth) is -<NUM> V with an effective mobility was <NUM><NUM>/Vs. These values are consistent with the performance characteristics expected for a <NUM> thick bottom gate structure of this type.

The selective transfer methods described in this example provide an efficient route for transferring microstructured silicon from a SOI wafer to a flexible, macroelectronic system. Using these techniques, and in contrast with conventional solution casting methods, the microstructured silicon objects can be transferred from an SOI mother wafer with precise registration and utilized in ways that minimize waste. The mechanical properties of the new <NUM> PDMS investigated in this work demonstrates that it has a number of important advantages as compared to the commercial Sylgard <NUM> PDMS resin, notably its dimensional stability and higher surface adhesion properties. The printing techniques also proved to be compatible with the construction of macroelectronic systems that incorporate high performance µs-Si thin film transistors.

The fabrication of the µs-Si objects was carried out using a commercial SOI wafer (SOITEC, p-type, top Si thickness=<NUM>, resistivity=<NUM>-<NUM> ohm-cm, <NUM> buried oxide layer). Photolithography (Shipley <NUM> resist) was used to pattern the SOI wafer into the desired peanut-shaped geometry (mid-section length: <NUM>, width: <NUM>, diameter of peanut: <NUM>). Dry etching (Plasmatherm RIE system, SF6 flow, <NUM> sccm, <NUM> Pa (<NUM> mTorr), RF power=<NUM> W, <NUM> sec) was then used to remove the exposed silicon. The underlying SiO<NUM> was then etched for <NUM> seconds in an HF (<NUM>%) solution. For the <NUM> PDMS stamp of Method I, a specialty PDMS (Dow Corning, <NUM>, elastic modulus= <NUM> MPa) and Sylgard <NUM> (Dow corning, elastic modulus= <NUM> MPa) was mixed in a one to one ratio and cured using standard soft-lithographic patterning methods A UV source (ozone active mercury lamp, <NUM>µW/cm<NUM>) was used to cure the PU thin film adhesion layer (Norland optical adhesive, No. <NUM>). These latter films were coated onto a PET substrate (<NUM> in thickness, Mylar film, Southwall technologies) using a bar coating procedure (Meyer bar, RD specialties).

For Method II, the sizes of the peanut shapes used were smaller than the ones used in Method I (mid-section length: <NUM>, width: <NUM>, diameter of ends: <NUM>). A similar fabrication protocol was used to produce these structures with the exception that the RIE etching time was reduced to <NUM> seconds (to minimize sidewall etching) and the buried oxide layer was etched for <NUM> seconds in a concentrated (<NUM>%) HF solution. After the latter etching step, the sample was rinsed in a water bath and dried in an oven at <NUM> for <NUM> minutes. A <NUM>Å SiO<NUM> layer was then evaporated on top of the sample (Temescal FC-<NUM> Electron Beam Evaporator). To bind a thin layer of PDMS onto the PET substrate, a layer of PU was first cast by spinning onto the PET at <NUM> rpm for <NUM> seconds and exposed to UVO (<NUM>µW/cm<NUM>) for <NUM> minutes. A film of PDMS was then spuncast at <NUM> rpm for <NUM> seconds onto the PU a cured thermally at <NUM> for three hours.

The selective area soft lithographic patterning procedure comprised placing the unpatterened PDMS side of the coated PET substrate in contact with the patterned side of the UVO photomask. The fabrication of this microreactor mask followed procedures described by Childs et. The pattern consisted of two interlocking rectangular arrays (<NUM>. The PDMS was then irradiated through the UVO photomask for <NUM> minutes at a distance of ~<NUM> from a mercury bulb (UVOCS T10x10/OES). After exposure, the PDMS stamp was pealed away from the UVO photomask, and the exposed PDMS face was placed into contact with the peanut-bearing SOI wafer. After heating at <NUM> for <NUM> minutes, tweezers were used to slowly peal the PDMS away, removing segments of the µs-Si in registry with the areas of irradiation.

Claim 1:
A method for fabricating a printable semiconductor element connected to a mother wafer via alignment maintaining elements, said method comprising the steps of:
providing said mother wafer having an external surface, said wafer comprising an inorganic semiconductor material;
masking a selected region of said external surface by applying a mask;
etching said external surface of said wafer, thereby generating a relief structure and at least one exposed surface of said inorganic semiconductor material, wherein said relief structure has a masked side and one or more unmasked sides;
isotropic etching said exposed surfaces of said inorganic semiconductor material; and
stopping etching of said exposed surfaces so that complete release of said relief structure is prevented, thereby fabricating said printable semiconductor element connected to said mother wafer via alignment maintaining elements,
wherein said printable semiconductor element has a peanut shape or a ribbon shape with a first end and a second end, wherein said alignment maintaining elements connect said first and second ends of said printable semiconductor element to said mother wafer.