Patent Description:
<CIT> discloses asystem and method for packing optical and electronic components. A module includes an electronic integrated circuit and a plurality of photonic integrated circuits, connected to the electronic integrated circuit by wire bonds or by wire bonds and other conductors. A metal cover of the module is in thermal contact with the electronic integrated circuit and facilitates extraction of heat from the electronic integrated circuit. Arrays of optical fibers are connected to the photonic integrated circuits.

<CIT> discloses an optical transceiver including a transmitter having a photonic integrated circuit, and a receiver having a current-to-voltage converter and a photodetector in electrical communication with the current-to-voltage converter and separate from the photonic integrated circuit. Each of the transmitter and the receiver can include an interconnect member that includes first and second optical paths for the propagation of optical transmit signals and optical receive signals, respectively.

<CIT> discloses a photonic adaptor having a first face side to couple the photonic adaptor to an optical connector and a second face side to couple the photonic adaptor to an optoelectronic substrate. The photonic adaptor comprises a plurality of optical fibers being arranged between the first face side and the second face side of the photonic adaptor. The photonic adaptor comprises at least one alignment pin projecting out of at least the first face side of the photonic adaptor. The at least one alignment pin is configured to be inserted in the optical connector to align optical fibers of an optical cable to the optical fibers of the photonic adaptor.

The appended claims define the subject-matter for which protection is sought.

In an example embodiment, a multi-chip package assembly is disclosed. The multi-chip package assembly includes a substrate, and a first semiconductor chip attached to the substrate, and a second semiconductor chip attached to the substrate, such that a portion of the second semiconductor chip overhangs an edge of the substrate. A first v-groove array for receiving a plurality of optical fibers is present within the portion of the second semiconductor chip that overhangs the edge of the substrate. The multichip package assembly also includes an optical fiber assembly that includes the plurality of optical fibers positioned and secured within the first v-groove array of the second semiconductor chip. The optical fiber assembly includes a second v-groove array configured to align the plurality of optical fibers to the first v-groove array of the second semiconductor chip. The optical fiber assembly includes an optical fiber connector. An end of each of the plurality of optical fibers is exposed for optical coupling within the optical fiber connector. The optical fiber connector is located at a distal end of the optical fiber assembly relative to the second semiconductor chip.

Other aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention.

In the following description, numerous specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details, insofar as the result is still within the subject-matter of the claims. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

In various silicon photonic devices used in the silicon photonics industry for optical data communication, one or more optical fiber(s) is/are coupled to a semiconductor chip so that light (continuous wave (CW) light and/or modulated light) can be transmitted from the one or more optical fiber(s) into the semiconductor chip and/or transmitted from the semiconductor chip into the one or more optical fiber(s). For ease of description the term semiconductor chip as used herein refers to both a semiconductor chip and a semiconductor die. Also, in various embodiments the semiconductor chip referred to herein includes electrical devices, optical devices, electro-optical devices, and/or thermo-optical devices, and corresponding electrical and optical circuitry. The semiconductor chip referred to herein corresponds to any photonicequipped chip (or die) to which one or more optical fiber(s) is/are connected to provide for transmission of light into and/or out of the semiconductor chip. The coupling of an optical fiber to a semiconductor chip is referred to as fiber-to-chip coupling.

The term "light" as used herein refers to electromagnetic radiation within a portion of the electromagnetic spectrum that is usable by optical data communication systems. In some embodiments, the portion of the electromagnetic spectrum includes light having wavelengths within a range extending from about <NUM> nanometers to about <NUM> nanometers (covering from the O-Band to the C-Band, inclusively, of the electromagnetic spectrum). However, it should be understood that the portion of the electromagnetic spectrum as referred to herein can include light having wavelengths either less than <NUM> nanometers or greater than <NUM> nanometers, so long as the light is usable by an optical data communication system for encoding, transmission, and decoding of digital data through modulation/de-modulation of the light. In some embodiments, the light used in optical data communication systems has wavelengths in the nearinfrared portion of the electromagnetic spectrum.

In some semiconductor chip packaging embodiments, in-package optical interconnect relies on <NUM>. 5D or <NUM>. 1D interposer-type packaging technology. The semiconductor chip includes integrated v-grooves configured to facilitate attachment of optical fibers. Also, in some semiconductor chip packaging embodiments, either a 3D packaging approach, e.g., die stacking, or a wire-bonding approach is utilized. However, a silicon photonics package assembly approach utilizing either a 2D packaging approach or <NUM>. 5D packaging approach would be economically beneficial. Embodiments are disclosed herein for multi-chip packaging of silicon photonic devices. In particular, various embodiments are disclosed herein for co-packaging of a plurality of silicon photonic semiconductor chips with a system-on-chip (SOC) semiconductor chip.

<FIG> shows an isometric view of an assembly in which a plurality of semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are flip-chip connected to a substrate <NUM>, in accordance with some embodiments. In the example of <FIG>, the substrate <NUM> includes extension sections 105A, 105B, 105C, 105D that extend outward in the horizontal plane (in a direction parallel to the x-y plane) from the four corners of the substrate <NUM>. However, in some embodiments, the substrate <NUM> has a substantially rectangular-shaped horizontal cross-section (parallel to the x-y plane) and does not include the extension sections 105A, 105B, 105C, 105D. In various embodiments, the horizontal cross-section of the substrate <NUM> can have a substantially rectangular shape, a substantially square shape, or a substantially polygonal shape, among other shapes. In some embodiments, the substrate <NUM> is an organic substrate. In some embodiments, the substrate <NUM> includes an organic substrate combined with a silicon interposer. In various embodiments, the substrate <NUM> is essentially any type of substrate used in the packaging assembly of semiconductor chips, such as a composite substrate, a glass substrate, a ceramic substrate, among other substrate types.

<FIG> shows the semiconductor chip <NUM> connected to the substrate <NUM>. In some embodiments, the semiconductor chip <NUM> is flip-chip connected to the substrate <NUM>. In some embodiments, the semiconductor chip <NUM> is an SOC semiconductor chip. It should be understood, however, that in some embodiments the semiconductor chip <NUM> is not an SOC semiconductor chip. Therefore, in various embodiments, the semiconductor chip <NUM> can be essentially any type of semiconductor chip. For example, in some embodiments, the semiconductor chip <NUM> is a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a field programmable gate array (FPGA) chip, a graphics processor chip, a memory chip (such as a dynamic random access memory (DRAM), or NAND flash memory, or other type of memory), a network processor chip, a switch chip, or an artificial intelligence chip, among essentially any other type of semiconductor chip. In some embodiments, the semiconductor chip <NUM> does not overhang any edge of the substrate <NUM>.

In some embodiments, each of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> is a silicon photonics chip that includes optical devices and/or electro-optical devices and/or thermo-optical devices. In some embodiments, one or more of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> is a TeraPHY™ semiconductor chip as provided by Ayar Labs, Inc. of Santa Clara, California. However, it should be understood that implementation of each of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> as the TeraPHY™ chip is provided by way of example. In various embodiments, each of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> is essentially any type of photonics chip, whether it be the TeraPHY™ chip or another type of photonics chip. In some embodiments, each of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> is configured for optical connection to an optical fiber array and/or to a photonics optical waveguide. Also, it should be understood that in some embodiments, one or more of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> is/are connected to the substrate <NUM>. For example, in some embodiments, one of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> is connected to the substrate <NUM>. In some embodiments, two of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> are connected to the substrate <NUM>. In some embodiments, three of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> are connected to the substrate <NUM>. In some embodiments, all four of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> are connected to the substrate <NUM>. Also, in some embodiments, the substrate <NUM> is sized to accommodate connection of more than the four semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> to the substrate <NUM>.

In some embodiments, the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are flip-chip connected to the substrate <NUM> using a number of C4 (controlled collapse chip connection) solder bumps. In some embodiments, the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are flip-chip connected to the substrate <NUM> using a number of copper pillars. In some embodiments, the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are flip-chip connected to the substrate <NUM> using a combination of C4 solder bumps, copper pillars, and/or any other chip-to-package electrical connection technique that is standard within the semiconductor fabrication industry. In some embodiments, a dielectric underfill material (e.g., epoxy underfill material) is disposed between one or more of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and the substrate <NUM>. However, in some embodiments, the dielectric underfill material is not disposed between some of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and the substrate <NUM>. In some embodiments, the dielectric underfill material is not disposed between any of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and the substrate <NUM>.

<FIG> shows a bottom view of the assembly of <FIG>, in accordance with some embodiments. Each of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> is shaped, sized, and positioned to overhang a corresponding edge of the substrate <NUM> in a cantilevered manner. In some embodiments, the semiconductor chip <NUM> includes a first v-groove array <NUM> and a second v-groove array <NUM>. In some embodiments, the semiconductor chip <NUM> includes a first v-groove array <NUM> and a second v-groove array <NUM>. In some embodiments, the semiconductor chip <NUM> includes a first v-groove array <NUM> and a second v-groove array <NUM>. In some embodiments, the semiconductor chip <NUM> includes a first v-groove array <NUM> and a second v-groove array <NUM>. Each of the v-groove arrays <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> includes a number of v-grooves, with each v-groove configured to receive an optical fiber, such that a core of the optical fiber is optically aligned with an optical waveguide in the corresponding semiconductor chip <NUM>, <NUM>, <NUM>, <NUM> in which the v-groove array <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> is formed. In some embodiments, the v-grooves of the v-groove array <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> are oriented parallel to each other to facilitate connection of an optical fiber ribbon to the corresponding semiconductor chip <NUM>, <NUM>, <NUM>, <NUM> in which the v-groove array <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> is formed. In some embodiments, each of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> is shaped, sized, and positioned to overhang the substrate <NUM> in the cantilevered manner by an extent that provides for exposure of the v-groove arrays <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> to facilitate connection of optical fibers with the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>.

In some embodiments, each of the first v-groove array <NUM> and the second v-groove array <NUM> of semiconductor chip <NUM> has a same number of v-grooves and substantially equal size. In some embodiments, each of the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM> has <NUM> v-grooves. However, it should be understood that in various embodiments, each of the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM> can have essentially any number of v-grooves, from one v-groove to multiple v-grooves (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc., v-grooves). In some embodiments, the first v-groove array <NUM> has a different number of v-grooves than the second v-groove array <NUM>. Also, in some embodiments, the semiconductor chip <NUM> includes one of the first v-groove array <NUM> and the second v-groove array <NUM>, but not the other. And, in some embodiments, the semiconductor chip <NUM> includes both of the first v-groove array <NUM> and the second v-groove array <NUM>, along with one or more additional v-grooves and/or v-groove arrays.

<FIG> shows a side view of the assembly of <FIG>, referenced as View A-A in <FIG>, in accordance with some embodiments. A set of optical fibers <NUM> are positioned within the v-groove array <NUM>. A set of optical fibers <NUM> are positioned within the v-groove array <NUM>. A set of optical fibers <NUM> are positioned within the v-groove array <NUM>. A set of optical fibers <NUM> are positioned within the v-groove array <NUM>.

<FIG> shows an isometric view of the assembly of <FIG> with an Integrated Heat Spreader (IHS) <NUM> attached to a top surface of the substrate <NUM>, in accordance with some embodiments. In some embodiments, the IHS <NUM> also serves as a lid structure. In some embodiments, a thermal interface material (TIM) is disposed between the IHS <NUM> and the exposed upper surfaces of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> that are connected to the substrate <NUM>. In various embodiments, the TIM between the IHS <NUM> and the semiconductor chips/die <NUM>, <NUM>, <NUM>, <NUM>, <NUM> is one or more of an epoxy, a polymer thermal interface material (PTIM), an elastomer, or another type of TIM. Also, in some embodiments, the IHS <NUM> functions as a structural support member to provide structural reinforcement to the substrate <NUM> and/or to the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> that are positioned to overhang the substrate <NUM> in the cantilevered manner. In some embodiments, the IHS <NUM> is formed of one or more material(s) having high thermal conductivity, such as aluminum, copper, tungsten, molybdenum, copper-tungsten alloy, copper-molybdenum alloy, aluminum-nitride, sintered aluminum-silicon carbide, magnesium-silicon carbide, sumicrystal, chemical vapor deposited diamond, copper-diamond, silver-diamond, and/or other similar heat spreader material.

<FIG> shows an isometric view of the bottom of the assembly of <FIG>, in accordance with some embodiments. <FIG> shows a close-up view of an area <NUM> as referenced in <FIG>, in accordance with some embodiments. <FIG> shows the semiconductor chips <NUM> and <NUM>. <FIG> also shows the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM>. <FIG> also shows the substrate <NUM> and the IHS <NUM>. <FIG> also shows a dam structure <NUM> formed on the semiconductor chip <NUM> at a location between the substrate <NUM> and each of the first v-groove array <NUM> and the second v-groove array <NUM>. It should be understood that the other semiconductor chips <NUM>, <NUM>, <NUM> also include a similarly configured dam structure <NUM>. In some embodiments, the dam structure <NUM> does not physically contact the substrate <NUM>, such that a gap <NUM> exists between the dam structure <NUM> and the substrate <NUM>. In some embodiments, the gap <NUM> between the dam structure <NUM> and the substrate <NUM> allows air to escape from the region between the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and the substrate <NUM> during a capillary under-fill (CUF) process in which an underfill material, such as epoxy or other suitable underfill material, is disposed within the open region(s) between the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and the substrate <NUM>. It should be understood that allowing the escape of air from the region between the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and the substrate <NUM> during the CUF process will reduce the creation of voids within the underfill material.

Also, the dam structure <NUM> serves to reduce bleed-out of the underfill material during the CUF process. In this manner, the dam structure <NUM> prevents the underfill material from bleeding-out and fouling the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM> during the CUF process. The dam structure <NUM> separates the underfill material from the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. In some embodiments, the dam structure <NUM> is configured to extend across and physically contact both the semiconductor chip <NUM> and the semiconductor chip <NUM> in a substantially continuous manner. In some embodiments, each of the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM> has their own dam structure <NUM> disposed thereon in the same manner as described with regard to the semiconductor chip <NUM> in <FIG>. It should be understood that in various embodiments the CUF process is performed after the dam structures <NUM> are formed/disposed on the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>.

<FIG> shows a bottom view of the configuration of <FIG>, with an optical fiber assembly 310A connected to the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM>, in accordance with some embodiments. <FIG> shows an isometric view of the configuration of <FIG>, with the optical fiber assembly 310A connected to the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM>, in accordance with some embodiments. In some embodiments, the optical fiber assembly 310A includes a first set of optical fibers 312A that are inserted into the v-grooves of the first v-groove array <NUM> and a second set of optical fibers 314A that are inserted into the v-grooves of the second v-groove array <NUM>. The optical fiber assembly 310A also includes an optical fiber connector 313A, and a v-groove array 311A. The v-groove array 311A is configured to hold the first set of optical fibers 312A at a prescribed pitch. The v-groove array 311A is also configured to hold the second set of optical fibers 314A at the prescribed pitch. The prescribed pitch is a center-to-center spacing between cores of adjacent optical fibers within the v-groove array 311A, as measured perpendicularly between the core axes of the adjacent optical fibers within the v-groove array 311A. In some embodiments, the prescribed pitch of the first set of optical fibers 312A in the v-groove array 311A and/or the second set of optical fibers 314A in the v-groove array 311A is about <NUM> micrometers. In some embodiments, the prescribed pitch of the first set of optical fibers 312A in the v-groove array 311A and/or the second set of optical fibers 314A in the v-groove array 311A is about <NUM> micrometers. In some embodiments, the prescribed pitch of the first set of optical fibers 312A in the v-groove array 311A and/or the second set of optical fibers 314A in the v-groove array 311A is set at a value other than <NUM> micrometers or <NUM> micrometers, so long as the prescribed pitch provides for alignment of the first set of optical fibers 312A with the first v-groove array <NUM> and alignment of the second set of optical fibers 314A with the second v-groove array <NUM>.

The v-groove array 311A of the optical fiber assembly 310A is configured to align the first set of optical fibers 312A with the first v-groove array <NUM> on the semiconductor chip <NUM>. The v-groove array 311A is also configured to align the second set of optical fibers 314A with the second v-groove array <NUM> on the semiconductor chip <NUM>. In some embodiments, a cover structure 315A is secured to the v-groove array 311A in order to stabilize the first set of optical fibers 312A and the second set of optical fibers 314A in the v-groove array 311A. In some embodiments, the cover structure 315A is epoxied to the v-groove array 311A. In some embodiments, the cover structure 315A is fusion-bonded to the v-groove array 311A. In some embodiments, the v-groove array 311A and/or the cover structure 315A is formed of glass or silicon. In other embodiments, the v-groove array 311A and/or the cover structure 315A is formed of aluminum, Invar, nickel, plastic, or essentially any other material that provides required mechanical strength and that is chemically and thermally compatible with the particular application.

In some embodiments, the optical fiber connector 313A is an MT (mechanical transfer) ferrule. In some embodiments, the optical fiber connector 313A is an FC (fixed connection) optical fiber connector, or an LC (Lucent connector) optical fiber connector, or an ST (straight tip) optical fiber connector, or another type of optical fiber connector. The optical fibers in the first set of optical fibers 312A and the optical fibers in the second set of optical fibers 314A have lengths as needed to provide for installation of the optical fiber assembly 310A. It should be understood that the curvature and orientation of the first set of optical fibers 312A and the second set of optical fibers 314A in any of the optical fiber assembly 310A embodiments disclosed herein is provided by way of example, and is in no way limiting. In various embodiments, the first set of optical fibers 312A and the second set of optical fibers 314AB in any of the optical fiber assembly 310A embodiments disclosed herein can be configured and oriented as needed to enable installation of the optical fiber assembly 310A.

In some embodiments, the v-groove arrays <NUM> and <NUM> are respective parts of a same v-groove array. The optical fiber assembly 310A includes the plurality of optical fibers 312A, 314A that are positioned and secured within the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. The optical fiber assembly 310A includes the v-groove array 311A configured to align the plurality of optical fibers 312A, 314A to the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. An end of each of the plurality of optical fibers 312A, 314A is exposed for optical coupling within the optical fiber connector 313A of the optical fiber assembly 310A. The optical fiber connector 313A is located at a distal end of the optical fiber assembly 310A relative to the semiconductor chip <NUM>.

<FIG> shows a isometric bottom view of the configuration of <FIG> with optical fiber assemblies 310A, 310B, 310C, 310D respectively connected to the semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>, in accordance with some embodiments. More specifically, in addition to the first optical fiber assembly 310A being connected to the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM>, a second optical fiber assembly 310B is connected to the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM>, and a third optical fiber assembly 310C is connected to the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM>, and a fourth optical fiber assembly 310D is connected to the first v-groove array <NUM> and the second v-groove array <NUM> of the semiconductor chip <NUM>.

The second optical fiber assembly 310B is configured in the same manner as the optical fiber assembly 310A. Specifically, the second optical fiber assembly 310B includes an optical fiber connector 313B at a first end of the second optical fiber assembly 310B and a v-groove array 311B at a second end of the second optical fiber assembly 310B. The second optical fiber assembly 310B also includes a first set of optical fibers 312B secured within the v-groove array 311B and aligned for connection to the first v-groove array <NUM> of the semiconductor chip <NUM>. The second optical fiber assembly 310B also includes a second set of optical fibers 314B secured within the v-groove array 311B and aligned for connection to the second v-groove array <NUM> of the semiconductor chip <NUM>. The second optical fiber assembly 310B also includes a cover structure 315B secured to the v-groove array 311B.

In some embodiments, the v-groove arrays <NUM> and <NUM> are respective parts of a same v-groove array. The optical fiber assembly 310B includes the plurality of optical fibers 312B, 314B that are positioned and secured within the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. The optical fiber assembly 310B includes the v-groove array 311B configured to align the plurality of optical fibers 312B, 314B to the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. An end of each of the plurality of optical fibers 312B, 314B is exposed for optical coupling within the optical fiber connector 313B of the optical fiber assembly 310B. The optical fiber connector 313B is located at a distal end of the optical fiber assembly 310B relative to the semiconductor chip <NUM>.

The third optical fiber assembly 310C is also configured in the same manner as the optical fiber assembly 310A. Specifically, the third optical fiber assembly 310C includes an optical fiber connector 313C at a first end of the third optical fiber assembly 310C and a v-groove array 311C at a second end of the third optical fiber assembly 310C. The third optical fiber assembly 310C also includes a first set of optical fibers 312C secured within the v-groove array 311C and aligned for connection to the first v-groove array <NUM> of the semiconductor chip <NUM>. The third optical fiber assembly 310C also includes a second set of optical fibers 314C secured within the v-groove array 311C and aligned for connection to the second v-groove array <NUM> of the semiconductor chip <NUM>. The second optical fiber assembly 310C also includes a cover structure 315C secured to the v-groove array 311C.

In some embodiments, the v-groove arrays <NUM> and <NUM> are respective parts of a same v-groove array. The optical fiber assembly 310C includes the plurality of optical fibers 312C, 314C that are positioned and secured within the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. The optical fiber assembly 310C includes the v-groove array 311C configured to align the plurality of optical fibers 312C, 314C to the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. An end of each of the plurality of optical fibers 312C, 314C is exposed for optical coupling within the optical fiber connector 313C of the optical fiber assembly 310C. The optical fiber connector 313C is located at a distal end of the optical fiber assembly 310C relative to the semiconductor chip <NUM>.

The fourth optical fiber assembly 310D is also configured in the same manner as the optical fiber assembly 310A. Specifically, the fourth optical fiber assembly 310D includes an optical fiber connector 313D at a first end of the fourth optical fiber assembly 310D and a v-groove array 311D at a second end of the fourth optical fiber assembly 310D. The fourth optical fiber assembly 310D also includes a first set of optical fibers 312D secured within the v-groove array 311D and aligned for connection to the first v-groove array <NUM> of the semiconductor chip <NUM>. The fourth optical fiber assembly 310D also includes a second set of optical fibers 314D secured within the v-groove array 311D and aligned for connection to the second v-groove array <NUM> of the semiconductor chip <NUM>. The fourth optical fiber assembly 310D also includes a cover structure 315D secured to the v-groove array 311D.

In some embodiments, the v-groove arrays <NUM> and <NUM> are respective parts of a same v-groove array. The optical fiber assembly 310D includes the plurality of optical fibers 312D, 314D that are positioned and secured within the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. The optical fiber assembly 310D includes the v-groove array 311D configured to align the plurality of optical fibers 312D, 314D to the v-groove array <NUM>, <NUM> of the semiconductor chip <NUM>. An end of each of the plurality of optical fibers 312D, 314D is exposed for optical coupling within the optical fiber connector 313D of the optical fiber assembly 310D. The optical fiber connector 313D is located at a distal end of the optical fiber assembly 310D relative to the semiconductor chip <NUM>.

In some embodiments, after connection of the first optical fiber assembly 310A to the semiconductor chip <NUM> and connection of the second optical fiber assembly 310B to the semiconductor chips <NUM>, a dam-and-fill process or a glob-top process is performed in which an adhesive <NUM>, such as an epoxy or other suitable material, is disposed to cover the first set of optical fibers 312A within the v-groove array <NUM>, the second set of optical fibers 314A within the v-groove array <NUM>, the first set of optical fibers 312B within the v-groove array <NUM>, and the second set of optical fibers 314B within the v-groove array <NUM>. Similarly, after connection of the third optical fiber assembly 310C to the semiconductor chip <NUM> and connection of the fourth optical fiber assembly 310D to the semiconductor chips <NUM>, the darn-and-fill process or the glob-top process is performed in which an adhesive <NUM>, such as an epoxy or other suitable material, is disposed to cover the first set of optical fibers 312C within the v-groove array <NUM>, the second set of optical fibers 314C within the v-groove array <NUM>, the first set of optical fibers 312D within the v-groove array <NUM>, and the second set of optical fibers 314D within the v-groove array <NUM>. In some embodiments, an optical adhesive is used to interface with the optical fibers 312A, 314A, 312B, 314B, 312C, 314C, 312D, 314D, particularly at locations between the ends of the optical fibers 312A, 314A, 312B, 314B, 312C, 314C, 312D, 314D and the corresponding semiconductor chips <NUM>, <NUM>, <NUM>, <NUM>.

In some embodiments, the adhesives <NUM> and <NUM> are applied in a manner that avoids creation of voids in the adhesives <NUM> and <NUM>. In some embodiments, the v-groove arrays 311A and 311B of the optical fiber assemblies 310A and 310B, respectively, act as a dam to assist with application of the adhesive <NUM>. Similarly, in some embodiments, the v-groove arrays 311C and 311D of the optical fiber assemblies 310C and 310D, respectively, act as a dam to assist with application of the adhesive <NUM>. It should be understood that the adhesive <NUM> serves to protect the exposed optical fibers within the v-groove arrays <NUM>, <NUM>, <NUM>, and <NUM> and provides for securing of the optical fiber assemblies 310A and 310B to the substrate <NUM> and to the IHS <NUM>. Similarly, the adhesive <NUM> serves to protect the exposed optical fibers within the v-groove arrays <NUM>, <NUM>, <NUM>, and <NUM> and provides for securing the optical fiber assemblies 310C and 310D to the substrate <NUM> and the IHS <NUM>.

<FIG> shows a top isometric view of the configuration of <FIG>, in accordance with some embodiments. <FIG> shows a side view of the configuration of <FIG>, in accordance with some embodiments. <FIG> shows an end view of the configuration of <FIG>, in accordance with some embodiments. <FIG> shows a bottom view of the configuration of <FIG>, in accordance with some embodiments. <FIG> shows a top view of the configuration of <FIG>, in accordance with some embodiments.

<FIG> shows the optical fiber assembly 310A inserted into the v-groove arrays <NUM> and <NUM> of the semiconductor chip <NUM> to form a sub-mount assembly 500A prior to the flip-chip process to connect the semiconductor chip <NUM> to the substrate <NUM>, in accordance with some embodiments. In some embodiments, the cover structure 315A is epoxied to the v-groove array 311A of the optical fiber assembly 310A to stabilize the optical fibers in the first set of optical fibers 312A and the optical fibers in the second set of optical fibers 312B. In some embodiments, after insertion of the first set of optical fibers 312A into the v-groove array <NUM> and insertion of the second set of optical fibers 314A into the v-groove array <NUM>, the dam-and-fill process or the glob-top process is performed to apply the adhesive <NUM>. It should be understood that in some embodiments each of the semiconductor chips <NUM>, <NUM>, and <NUM> are separately connected to the optical fiber assemblies 310B, 310D, 310C, respectively, to form sub-mount assemblies 500B, 500D, 500C, respectively, like that of sub-mount assembly 500A before flip-chip connection of the semiconductor chips <NUM>, <NUM>, <NUM> to the substrate <NUM>.

<FIG> shows the sub-mount assemblies 500A, 500B, 500C, 500D for each of the semiconductor chips <NUM>, <NUM>, <NUM>, and <NUM>, respectively, flip-chip connected to a substrate 100A, in accordance with some embodiments. The substrate 100A is similar to the substrate <NUM>, except that the substrate 100A includes a blind cavity 710A to accommodate positioning and connection of the sub-mount assemblies 500A and 500B for the semiconductor chips <NUM> and <NUM>, respectively, to the substrate 100A. The blind cavity 710A is defined to spatially accommodate the cover structure 315A of the optical fiber assembly 310A and the cover structure 315B of the optical fiber assembly 310B. The substrate 100A also includes a blind cavity 710B to accommodate positioning and connection of the sub-mount assemblies 500C and 500D for the semiconductor chips <NUM> and <NUM>, respectively, to the substrate 100A. The blind cavity 710B is defined to spatially accommodate the cover structure 315C of the optical fiber assembly 310C and the cover structure 315D of the optical fiber assembly 310D.

<FIG> shows a sub-mount assembly 600A in which the sub-mount assembly 500A of <FIG> is attached to a stiffener structure 610A, in accordance with some embodiments. More specifically, in <FIG>, the semiconductor chip <NUM> is attached to the stiffener structure 610A to form the sub-mount assembly 600A. In various embodiments, the stiffener structure 610A can be formed of various materials, such as metal (e.g., copper, aluminum, stainless steel, or other metal or metallic alloy), silicon, ceramic, composite material, among other materials. It should be understood that in some embodiments each of the semiconductor chips <NUM>, <NUM>, and <NUM> are separately connected to stiffener structures 610B, 610D, 610C, respectively, to form sub-mount assemblies 600B, 600D, 600C, respectively, like that of sub-mount assembly 600A before flip-chip connection of the semiconductor chips <NUM>, <NUM>, <NUM> to the substrate 100A.

<FIG> shows the sub-mount assemblies 600A, 600B, 600C, 600D for each of the semiconductor chips <NUM>, <NUM>, <NUM>, and <NUM>, respectively, flip-chip connected to the substrate 100A, in accordance with some embodiments of the present invention. The assembly of <FIG> includes an IHS 110A that is similar to the IHS <NUM>, except that the IHS 110A includes a cut out region 720A to accommodate positioning and connection of the sub-mount assemblies 600A and 600B for the semiconductor chips <NUM> and <NUM>, respectively, to the substrate 100A. The cut out region 720A is defined to spatially accommodate the stiffener structures 610A and 610B of the sub-mount assemblies 600A and 600B. The IHS 110A also includes a cut out region 720B to accommodate positioning and connection of the sub-mount assemblies 600C and 600D for the semiconductor chips <NUM> and <NUM>, respectively, to the substrate 100A. The cut out region 720B is defined to spatially accommodate the stiffener structures 610C and 610D of the sub-mount assemblies 600C and 600D.

<FIG> shows a flowchart of a method for manufacturing a multi-chip package assembly, in accordance with some embodiments which are not according to the claimed invention. The method includes an operation <NUM> for having a substrate (<NUM>). The method includes an operation <NUM> for attaching a first semiconductor chip (<NUM>) to the substrate. In some embodiments, the first semiconductor chip is a system-on-chip. In some embodiments, the first semiconductor chip is attached to the substrate so that the first semiconductor chip does not overhang any edge of the substrate. In some embodiments, the first semiconductor chip is attached to the substrate by a flip-chip connection. The method includes an operation <NUM> for attaching a second semiconductor chip (<NUM>, <NUM>, <NUM>, or <NUM>) to the substrate, such that a portion of the second semiconductor chip overhangs an edge of the substrate. In some embodiments, the second semiconductor chip is a photonic device chip. In some embodiments, the second semiconductor chip is attached to the substrate by a flip-chip connection. A first v-groove array (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) for receiving a plurality of optical fibers (312A/314A, 312B/314B, 312C/314C, 312D/314D) is present within the portion of the second semiconductor chip that overhangs the edge of the substrate. The method also includes an operation <NUM> for attaching an optical fiber assembly (310A, 310B, 310C, 310D) to the second semiconductor chip by positioning and securing the plurality of optical fibers of the optical fiber assembly within the first v-groove array of the second semiconductor chip. An end of each of the plurality of optical fibers is exposed for optical coupling within an optical fiber connector (313A, 313B, 313C, 313D) of the optical fiber assembly. The optical fiber connector is located at a distal end of the optical fiber assembly relative to the second semiconductor chip. In some embodiments, attaching the optical fiber assembly to the second semiconductor chip includes aligning a second v-groove array (311A, 311B, 311C, 311D) of the optical fiber assembly that includes the plurality of optical fibers to the first v-groove array of the second semiconductor chip.

In some embodiments, the method also includes disposing an underfill material between the second semiconductor chip and the substrate, with a dam structure (<NUM>) of the second semiconductor chip preventing the underfill material from being disposed over the first v-groove array of the second semiconductor chip. In some embodiments, the method includes disposing an adhesive (<NUM>, <NUM>) over the plurality of optical fibers within the first v-groove array of the second semiconductor chip. In some embodiments, the method includes securing a cover structure (315A, 315B, 315C, 315D) to the second v-groove array of the optical fiber assembly, such that the cover structure extends over and secures the plurality of optical fibers within the second v-groove array of the optical fiber assembly. In some embodiments, the cover structure is secured to the second v-groove array of the optical fiber assembly by an epoxy. In some embodiments, the method includes attaching both the second semiconductor chip and the second v-groove array of the optical fiber assembly to a stiffener structure (610A, 610B, 610C, 610D) before attaching the second semiconductor chip to the substrate. The second semiconductor chip is positioned between the stiffener structure and the substrate when the second semiconductor chip is attached to the substrate. In some embodiments, the method includes attaching an integrated heat spreader (<NUM>) to the substrate, such that the first semiconductor chip and the second semiconductor chip are located between the integrated heat spreader and the substrate. In some embodiments, the method includes disposing a thermal interface material between the integrated heat spreader and both of the first semiconductor chip and the second semiconductor chip.

In some embodiments, the optical fiber assembly attached in operation <NUM> is a first optical fiber assembly, and the plurality of optical fibers of the first optical fiber assembly is a first plurality of optical fibers, and the optical fiber connector of the first optical assembly is a first optical fiber connector. In these embodiments, the method includes attaching a third semiconductor chip (<NUM>, <NUM>, <NUM>, or <NUM>) to the substrate such that a portion of the third semiconductor chip overhangs an edge of the substrate. A third v-groove array (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) for receiving a second plurality of optical fibers (312A/314A, 312B/314B, 312C/314C, 312D/314D) is present within the portion of the third semiconductor chip that overhangs the edge of the substrate. In these embodiments, the method also includes attaching a second optical fiber assembly (310A, 310B, 310C, 310D) to the third semiconductor chip by positioning and securing the second plurality of optical fibers of the second optical fiber assembly within the third v-groove array of the third semiconductor chip. An end of each of the second plurality of optical fibers is exposed for optical coupling within a second optical fiber connector (313A, 313B, 313C, 313D) of the second optical fiber assembly. The second optical fiber connector is located at a distal end of the second optical fiber assembly relative to the third semiconductor chip. In some embodiments, attaching the third semiconductor chip to the substrate includes positioning the third semiconductor chip adjacent to the second semiconductor chip. In some embodiments, the portion of the second semiconductor chip and the portion of the third semiconductor chip overhang a same edge of the substrate. In some embodiments, the portion of the second semiconductor chip and the portion of the third semiconductor chip overhang different edges of the substrate.

In some embodiments, the method further includes attaching a fourth semiconductor chip (<NUM>, <NUM>, <NUM>, or <NUM>) to the substrate such that a portion of the fourth semiconductor chip overhangs an edge of the substrate. A fifth v-groove array (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) for receiving a third plurality of optical fibers (312A/314A, 312B/314B, 312C/314C, 312D/314D) is present within the portion of the fourth semiconductor chip that overhangs the edge of the substrate. In these embodiments, the method also includes attaching a third optical fiber assembly (310A, 310B, 310C, 310D) to the fourth semiconductor chip by positioning and securing the third plurality of optical fibers of the third optical fiber assembly within the fifth v-groove array of the fourth semiconductor chip. An end of each of the third plurality of optical fibers is exposed for optical coupling within a third optical fiber connector (313A, 313B, 313C, 313D) of the third optical fiber assembly. The third optical fiber connector is located at a distal end of the third optical fiber assembly relative to the fourth semiconductor chip. In some embodiments, attaching the third semiconductor chip to the substrate includes positioning the third semiconductor chip adjacent to the second semiconductor chip, such that the portion of the second semiconductor chip and the portion of the third semiconductor chip overhang a first edge of the substrate, and such that the portion of the fourth semiconductor chip overhangs a second edge of the substrate that is different from the first edge of the substrate. In some of these embodiments, the first edge of the substrate and the second edge of the substrate are on opposite sides of the substrate.

In some embodiments, the method further includes attaching a fifth semiconductor chip (<NUM>, <NUM>, <NUM>, or <NUM>) to the substrate such that a portion of the fifth semiconductor chip overhangs an edge of the substrate. A seventh v-groove array (<NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>, <NUM>/<NUM>) for receiving a fourth plurality of optical fibers (312A/314A, 312B/314B, 312C/314C, 312D/314D) is present within the portion of the fifth semiconductor chip that overhangs the edge of the substrate. In these embodiments, the method includes attaching a fourth optical fiber assembly (310A, 310B, 310C, 310D) to the fifth semiconductor chip by positioning and securing the fourth plurality of optical fibers of the fourth optical fiber assembly within the seventh v-groove array of the fifth semiconductor chip. An end of each of the fourth plurality of optical fibers is exposed for optical coupling within a fourth optical fiber connector (313A, 313B, 313C, 313D) of the fourth optical fiber assembly. The fourth optical fiber connector is located at a distal end of the fourth optical fiber assembly relative to the fifth semiconductor chip. In some embodiments, attaching the third semiconductor chip to the substrate includes positioning the third semiconductor chip adjacent to the second semiconductor chip, such that the portion of the second semiconductor chip and the portion of the third semiconductor chip overhang a first edge of the substrate. Also, the method includes attaching the fourth semiconductor chip to the substrate by positioning the fourth semiconductor chip adjacent to the fifth semiconductor chip, such that the portion of the fourth semiconductor chip and the portion of the fifth semiconductor chip overhang a second edge of the substrate that is different from the first edge of the substrate. In some of these embodiments, the first edge of the substrate and the second edge of the substrate are on opposite sides of the substrate.

It is not intended to be exhaustive or to limit the invention which is defined by the appended claims.

Claim 1:
A multi-chip package assembly, comprising:
a substrate (<NUM>);
a first semiconductor chip (<NUM>) attached to the substrate (<NUM>);
a second semiconductor chip (<NUM>) attached to the substrate (<NUM>) such that a portion of the second semiconductor chip (<NUM>) overhangs an edge of the substrate (<NUM>), wherein a first v-groove array (<NUM>) for receiving a plurality of optical fibers is present within the portion of the second semiconductor chip (<NUM>) that overhangs the edge of the substrate (<NUM>); and
an optical fiber assembly (310B) including the plurality of optical fibers (312B) positioned and secured within the first v-groove array (<NUM>) of the second semiconductor chip (<NUM>), the optical fiber assembly (310B) including a second v-groove array (311B) configured to align the plurality of optical fibers (312B) to the first v-groove array (<NUM>) of the second semiconductor chip (<NUM>), the optical fiber assembly (310B) including an optical fiber connector (313B), wherein an end of each of the plurality of optical fibers (312B) is exposed for optical coupling within the optical fiber connector (313B), the optical fiber connector (313B) located at a distal end of the optical fiber assembly (310B) relative to the second semiconductor chip (<NUM>).