Patent Description:
In the field of computer storage, a system may include a host and one or more storage devices connected to (e.g., communicably coupled to) the host. Such computer storage systems have become increasingly popular, in part, for allowing many different users to share the computing resources of the system. Storage requirements have increased over time as the number of users of such systems and the number and complexity of applications running on such systems have increased.

Accordingly, there may be a need for methods, systems, and devices that are suitable for improving the use of storage devices in storage systems.

The present background section is intended to provide context only, and the disclosure of any embodiment or concept in this section does not constitute an admission that said embodiment or concept is prior art.

<CIT> discloses a method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

Aspects of some embodiments of the present disclosure relate to computer storage systems, and provide improvements to I/O processing.

Embodiments of the present disclosure are set out in the appended claims.

Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity, and have not necessarily been drawn to scale. For example, the dimensions of some of the elements, layers, and regions in the figures may be exaggerated relative to other elements, layers, and regions to help to improve clarity and understanding of various embodiments. Also, common but well-understood elements and parts not related to the description of the embodiments might not be shown to facilitate a less obstructed view of these various embodiments and to make the description clear.

Aspects of the present disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of one or more embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of the present disclosure to those skilled in the art. Accordingly, description of processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present disclosure may be omitted.

Unless otherwise noted, like reference numerals, characters, or combinations thereof denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof will not be repeated. Further, parts not related to the description of the embodiments might not be shown to make the description clear.

In the detailed description, for the purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various embodiments. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements.

It will be understood that, although the terms "zeroth," "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure.

It will be understood that when an element or component is referred to as being "on," "connected to," or "coupled to" another element or component, it can be directly on, connected to, or coupled to the other element or component, or one or more intervening elements or components may be present. However, "directly connected/directly coupled" refers to one component directly connecting or coupling another component without an intermediate component. Meanwhile, other expressions describing relationships between components such as "between," "immediately between" or "adjacent to" and "directly adjacent to" may be construed similarly. In addition, it will also be understood that when an element or component is referred to as being "between" two elements or components, it can be the only element or component between the two elements or components, or one or more intervening elements or components may also be present.

It will be further understood that the terms "comprises," "comprising," "have," "having," "includes," and "including," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, each of the terms "or" and "and/or" includes any and all combinations of one or more of the associated listed items.

For the purposes of this disclosure, expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ.

Any of the components or any combination of the components described (e.g., in any system diagrams included herein) may be used to perform one or more of the operations of any flow chart included herein. Further, (i) the operations are merely examples, and may involve various additional operations not explicitly covered, and (ii) the temporal order of the operations may be varied.

The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present disclosure described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate.

Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present inventive concept belongs.

As mentioned above, in the field of computer storage, a system may include a host and one or more storage devices (e.g., solid-state drives SSDs) communicably coupled to the host. The storage devices may store data associated with applications running on the host. For example, the applications may send input/output (I/O) requests to the storage devices for perform functions on the stored data. The storage devices may be configured to perform background tasks (also referred to as "housekeeping tasks") as part of the maintenance of the storage system. Scheduling of background tasks may be an internal activity of the storage device, which the host may have no control over. For example, a storage device may perform garbage collection (GC) and/or wear levelling (WL). During garbage collection, pending I/O requests may be delayed while the storage device automatically performs processes to free up memory space on the storage device. During wear levelling, pending I/O requests may be delayed while the storage device redistributes data on the storage device to even out reads and writes across storage media (e.g., NAND flash memory) of a storage system (e.g., an all-flash array (AFA)) to extend the life of the storage system.

Such background tasks may slow down the I/O performance of a storage device. For example, background tasks (such as garbage collection, wear levelling, read rescrubbing, and/or the like) may negatively impact I/O latency in a storage system. I/O performance problems may be compounded in multiple storage device systems because a single storage device may slow down multiple (e.g., all) I/O requests in the system. For example, with multi-SSD configurations, a single SSD performing an internal housekeeping activity may slow down the whole system because an I/O operation cannot be completed without fetching all of the data, and the data may be spread across many SSDs in an array. Accordingly, background tasks may increase a latency (e.g., a tail latency) for the overall system.

In some systems, information about the status of internal activity (e.g., background tasks) of a storage device is collected based on extending a protocol interface (e.g., an NVMe interface) associated with the storage device. Such an approach may make such systems protocol dependent and less flexible.

Aspects of some embodiments of the present disclosure provide a system including a machine learning (ML) model and an I/O scheduler to observe a workload on a storage device and predict when a background operation (such as garbage collection, wear levelling, read rescrubbing, and/or the like) will be triggered on the storage device. The prediction may be used to make smart re-routing and I/O buffering decisions in the system. Accordingly, the status of internal activity of the storage device may be estimated (e.g., predicted) without extending a protocol interface associated with the storage device. Thus, aspects of embodiments of the present disclosure may be implemented regardless of a specific protocol associated with the storage device.

Additionally, smart re-routing and I/O buffering decisions may be made automatically and dynamically to reduce latencies for the overall system. Aspects of some embodiments of the present disclosure may be applied to AFA systems, which commonly include garbage collection and wear levelling operations. Furthermore, by using a machine-learning model to estimate when a background task (or background activity) is likely to occur, aspects of embodiments of the present disclosure allow systems to avoid consuming storage device resources used for reporting internal storage device information to a host.

<FIG> is a system diagram depicting a system for scheduling input/output (I/O) requests, according to some embodiments of the present disclosure.

Referring to <FIG>, a storage system <NUM> may include a host <NUM> that is communicably coupled to one or more storage devices <NUM> (individually depicted as a first storage device 300a, a second storage device 300b, and an n-th storage device 300n). It should be understood that the present disclosure may be extended to storage systems including any number of storage devices. The host may include one or more applications <NUM> running on the host <NUM>. Each application <NUM> may perform operations associated with a workload WL. The workloads WL of one or more applications <NUM> may be associated with some of the storage devices <NUM>. For example, the workload WL of an application <NUM> may cause the application <NUM> to send an I/O request <NUM> to access data stored at the first storage device 300a. The host <NUM> may include an I/O scheduler <NUM> to perform scheduling and routing of I/O requests <NUM> received from the applications <NUM>. For example, the I/O scheduler <NUM> may manage a processing of write and read operations associated with the storage devices <NUM>. As discussed in further detail below, with respect to <FIG>, <FIG>, the system <NUM> may characterize application I/O workloads in real time to estimate (or predict) when a storage device is likely to perform a background task (e.g., to estimate that the storage device has a probability of performing the background task that exceeds a threshold probability). In some embodiments, the I/O scheduler <NUM> may include an I/O splitter <NUM> for performing data I/O dividing operations. For example, an I/O request may be divided as part of a redundant array of independent disks (RAID) operation or a Reed-Solomon (RS) operation. For example, the I/O splitter <NUM> may process RAID code or RS code associated with the I/O request <NUM>.

In some embodiments, the I/O scheduler <NUM> may cause data (e.g., data that is frequently accessed or data that is likely to be accessed) to be prefetched from any of the storage devices <NUM> that is likely to perform a background task within a certain period of time (for example within the next few minutes). For example, if the I/O scheduler <NUM> determines that the first storage device 300a is likely to perform a background task within a certain period of time, the I/O scheduler may trigger a data buffering operation <NUM> to copy data stored in the first storage device 300a from the first storage device 300a to a read buffer <NUM>. Accordingly, if the I/O scheduler <NUM> receives a read request for the data while the first storage device 300a is determined to be likely to be performing the background task, the read request may be processed by way of a rerouted read operation <NUM>. The rerouted read operation <NUM> may allow the data to be accessed from the read buffer <NUM>, instead of from the first storage device 300a, without waiting for the first storage device 300a to finish the background task. In some embodiments, the data buffering operation <NUM> may be triggered based on a likelihood of a storage device <NUM> performing a background task within a certain period of time exceeding a high percentage chance (e.g., an <NUM>% chance). In some embodiments, the I/O scheduler <NUM> may refer to a list (e.g., an up-to-date list) of data locations that are most frequently accessed (e.g., "read-hot blocks") for each storage device <NUM> that is likely to perform a background task. For example, the I/O scheduler <NUM> may retrieve a list of read-hot blocks, which include read-hot data, from a read-hot identifier <NUM> that is configured to collect data from an I/O trace (e.g., a block I/O trace) corresponding to applications <NUM>. In some embodiments, the read-hot identifier <NUM> may sort logical blocks by access count. In some embodiments, the read-hot identifier <NUM> may consider data corresponding to data blocks that are accessed in the top <NUM>% of all data blocks, within a storage device that is likely to perform a background task, to be read-hot data. The I/O scheduler <NUM> may buffer the read-hot data into the read buffer <NUM>. While the data buffering operation <NUM> is in progress, read requests may be serviced from the storage device that is likely to perform the background task. A read buffer hit may allow a read request to be processed from data stored in the read buffer. In some embodiments, a read buffer miss may cause a read operation to be issued to the storage device that is likely to be performing the background task. In some embodiments, the read buffer <NUM> may be flushed back to the originally intended storage device <NUM> after the background task has been completed.

In some embodiments, the I/O scheduler <NUM> may include an I/O rerouter <NUM> (e.g., an I/O router that is capable of rerouting I/O requests). The I/O rerouter <NUM> may cause a write operation to be performed at a different one of the storage devices <NUM>. For example, if the I/O scheduler <NUM> determines that the first storage device 300a is likely to perform a background task within a certain period of time, the I/O scheduler may trigger a rerouted write operation <NUM> to write data intended for the first storage device 300a to the second storage device 300b (e.g., a storage device that is not performing and/or or not likely to perform a background task). That is, the I/O request <NUM> may include a command to write data, which would normally be performed via a normal path <NUM> to the first storage device 300a. However, the I/O scheduler <NUM> may reroute the writing of data to the second storage device 300b via the rerouted write operation <NUM>. The rerouted write operation <NUM> may allow the data to be written without waiting for the first storage device 300a to finish the background task. In some embodiments, the rerouted write operation <NUM> may be triggered based on a likelihood of a storage device <NUM> performing a background task within a certain period of time exceeding a high percentage chance (e.g., an <NUM>% chance). In some embodiments, data writes may be rerouted back to the originally intended storage device <NUM> after completion of the background task. In some embodiments, completion of the background task may be determined based on information received via a firmware interface of the storage device <NUM> that has finished the background task. In some embodiments, completion of the background task may be estimated based on an approximate time (e.g., a maximum time) for completing similar background tasks. In some embodiments, completion of the background task may be determined according to a fixed time period to prevent delays that may result from false-positive predictions. In some embodiments, rerouted data that has been written to another storage device <NUM> may be moved to the originally intended storage device <NUM> after the background task has been completed. For example, the rerouted data written to the second storage device 300b may be moved to the first storage device 300a during an idle period (e.g., during a maintenance window).

In some embodiments, the host <NUM> may include a neural network circuit <NUM> that is configured to generate background task information <NUM>. The neural network circuit <NUM> may include a ML model that is trained to predict when a background task may be performed by any storage device. For example, the ML model may be trained to perform sequence forecasting. In some embodiments, the neural network circuit <NUM> may include a recurrent neural network, such as a long short-term memory (LSTM) algorithm. In some embodiments, the neural network circuit <NUM> may include a graphic neural network (GNN) or a convolutional neural network (CNN). The background task information <NUM> may be sent to the I/O scheduler <NUM> to allow the I/O scheduler <NUM> to determine when one or more of the storage devices <NUM> are likely to perform a background task. As discussed in more detail below, with respect to <FIG>, <FIG>, the neural network circuit <NUM> may be trained to estimate or predict when any of the storage devices <NUM> are likely to perform a background task based on observing a workload (or workloads) associated with each of the storage devices <NUM>. For example, the neural network circuit <NUM> may be configured to receive data corresponding to workload characteristics associated with the workloads WL of one or more applications <NUM> running on the host <NUM>. For example, I/O characteristics may be extracted from an I/O trace (e.g., a block I/O trace) corresponding to the I/O request <NUM>, and workload characteristics may be extracted from the I/O characteristics. In some embodiments, wherein the storage devices <NUM> include solid-state drives (SSDs), a block I/O trace may be extracted directly from the I/O request <NUM> because SSDs are block devices. The neural network circuit <NUM> may estimate (or predict) when any of the storage devices <NUM> are likely to perform a background task based on the workload characteristics.

As discussed above, based on determining that one or more of the storage devices <NUM> are likely to perform a background task, the I/O scheduler <NUM> may reroute write requests and/or buffer read-hot data associated with the storage devices <NUM> that are likely to perform a background task. The I/O scheduler <NUM> may determine when the background task is finished and reset the routes and/or flush the read buffer <NUM>. Accordingly, to reduce latencies, aspects of embodiments of the present disclosure allow for processing of I/O requests at storage devices to be modified based on the I/O scheduler <NUM> determining that one or more of the storage devices <NUM> are likely to perform a background task.

<FIG> is a system diagram depicting a system for training a neural network (NN) circuit to predict a background task in a storage device, and <FIG> is a listing of example data associated with workload characteristic information for training the neural network circuit, according to some embodiments of the present disclosure.

Referring to <FIG>, a training system <NUM> may include a simulator <NUM> (e.g., a storage system simulation circuit) and a ML model trainer <NUM>. The simulator <NUM> may include a simulator host <NUM> communicably coupled to one or more simulator storage devices <NUM>. The simulator host <NUM> may include a simulator application <NUM> and a simulator I/O scheduler <NUM>. In some embodiments, the simulator applications <NUM> may run on emulated virtual machines (VMs). The ML model trainer <NUM> may include the neural network circuit <NUM>. To train the neural network circuit <NUM>, the ML model trainer <NUM> may receive data associated with an I/O trace <NUM>. The I/O trace <NUM> may include time stamp information 450a, workload characteristic information 450b, and storage device internal characteristic information 450c.

In some embodiments, the workload characteristic information 450b may be extracted from the I/O trace <NUM> corresponding to a simulator application <NUM> running on the simulator <NUM>. The workload characteristic information 450b may describe the I/O trace <NUM> in detail. An I/O request may be issued from the simulator application <NUM> to the simulator storage devices <NUM> (individually depicted as a first simulator storage device 300Sa, a second simulator storage device 300Sb, and an n-th simulator storage device 300Sn). The simulator storage devices <NUM> may provide the storage device internal characteristic information 450c. For example, the simulator <NUM> may be configured to trace internal activity in the simulator storage devices <NUM> and indicate when a background task (e.g., a simulated background task) is performed by any of the simulator storage devices <NUM>. As used herein, "to trace" refers to observing processing activity and generating information (e.g., generating an I/O trace) to convey details about the processing activity. The storage device internal characteristic information 450c may include data indicating when the background task was performed. In some embodiments, the storage device internal characteristic information 450c may be extracted from housekeeping logs associated with the simulator storage devices <NUM>.

The workload characteristic information 450b and the storage device internal characteristic information 450c may be correlated (e.g., merged) by way of the time stamp information 450a. The workload characteristic information 450b extracted from the I/O trace may be selected based on a relevance (e.g., a significance) with respect to impacting or determining when a background task may be performed in a storage device. For example, in some embodiments, the workload characteristic information 450b may include data (e.g., per-storage-device data) corresponding to write throughput 500a, write-read ratio 500b, overwrite count 500c, storage device capacity utilization 500d, channels in use 500e (e.g., channels within a storage device), and/or change in throughput 500f. Write throughput 500a, which refers to an amount of data written to a device in a given amount of time, may be relevant for determining a fill rate associated with a storage device. Write-read ratio 500b may be relevant because writes may indirectly impact garbage collection. Overwrite count 500c may be relevant because overwrites may cause invalidation. Storage device capacity utilization 500d may be relevant for determining a maximum garbage collection delay possible. Channels in use 500e may be relevant because more channels may cause more garbage collection. Change in throughput 500f may be relevant for indicating the start of internal activity. Accordingly, the workload characteristic information 450b and the storage device internal characteristic information 450c may be input into the ML model trainer <NUM> to train the neural network circuit <NUM> to estimate (or predict) the possibility of a background task getting triggered in the near future in any storage device.

<FIG> is a diagram depicting the processing of an I/O trace to use as an input to the neural network circuit to predict the background task, according to some embodiments of the present disclosure.

Referring to <FIG>, workload characteristics may be extracted from the I/O trace <NUM> collected from the system that issues I/O requests. For example, in the storage system <NUM> (see <FIG>), the host <NUM> may extract workload characteristics from the application <NUM> that issues the I/O request <NUM> to the storage devices <NUM> to generate extracted workload characteristics <NUM> (see <FIG>). In the training system <NUM> (see <FIG>), the simulator <NUM> may extract workload characteristics from the simulator application <NUM> that issues I/O requests to the simulator storage devices <NUM> to generate the extracted workload characteristics <NUM> (see <FIG>). Workload characteristics may be extracted to understand I/O workloads in detail, including the changing dynamics of a workload and the intensity of a workload. In some embodiments, the extracted workload characteristics <NUM> may be selected to capture I/O characteristics that have been tested to be dependent on the internal activity (e.g., the background tasks) of a storage device. In other words, the extracted workload characteristics <NUM> may be selected based on their relevance (e.g., their significance) with respect to impacting or determining when a background task may be performed in a storage device.

To extract workload characteristics, the I/O trace <NUM>, having a first time length T1, may be broken down into (e.g., divided into or sampled in) chunks having a first sample size TS1. For example, the first time length T1 may be <NUM> minutes, and the first sample size TS1 may be one minute. Thus, the I/O trace <NUM> may be dived into <NUM> samples, including a first sample of the first sample size S1a, a second sample of the first sample size S1b, and an n-th sample of the first sample size S1n. Based on each sample of the first sample size TS1, workload characteristics may be extracted across all <NUM> samples to represent the workload corresponding to the I/O trace <NUM>. For example, out of all <NUM> samples, five data points may be extracted for each of the workload characteristics 500a-f, including the minimum value, the <NUM>th percentile value, the <NUM>th percentile value, the <NUM>th percentile value, and the maximum value. For example, with respect to write throughput 500a, the minimum value could be <NUM> Megabyte per second (MB/s), the <NUM>th percentile value could be <NUM> MB/s, the <NUM>th percentile value could be <NUM> MB/s, the <NUM>th percentile value could be <NUM> MB/s, and the maximum value could be <NUM> MB/s. The extracted workload characteristics <NUM> corresponding to the first sample size TS1 may be provided as a first input vector V1 for training the neural network circuit <NUM> and predicting when a background task is likely to be performed by any storage device.

In some embodiments, to improve the accuracy of the neural network circuit <NUM>, workload characteristics may also be extracted based on dividing the I/O trace <NUM> into chunks having a second sample size TS2. For example, the second sample size TS2 may be one second. Thus, the I/O trace <NUM> may be divided into <NUM>,<NUM> samples, including a first sample of the second sample size S2a through an n-th sample of the second sample size S2n, to further represent the workload corresponding to the I/O trace <NUM>. Based on each sample of the second sample size TS2, workload characteristics may be extracted across all <NUM>,<NUM> samples to represent the workload corresponding to the I/O trace <NUM>. For example, out of all <NUM>,<NUM> samples, five data points may be extracted for each of the workload characteristics 500a-f, including the minimum value, the <NUM>th percentile value, the <NUM>th percentile value, the <NUM>th percentile value, and the maximum value. The extracted workload characteristics <NUM> corresponding to the second sample size TS2 may be provided as a second input vector V2 for training the neural network circuit <NUM> and predicting when a background task is likely to be performed by any storage device.

<FIG> is a diagram depicting internal processing aspects of the neural network circuit, according to some embodiments of the present disclosure.

Referring to <FIG>, the input to the neural network circuit <NUM> during training and/or during use may be the workload characteristics from a period of time in the past. For example, as discussed above, the input to the neural network circuit <NUM> may be the workload characteristics for the last <NUM> minutes as extracted from the I/O trace <NUM> of the last <NUM> minutes. The background task information <NUM> that is output from the neural network circuit <NUM> may be the probability of a background task getting triggered in the future (e.g., in the next one to five minutes).

To infer when a background task is likely to occur, based on past workload characteristics, the neural network circuit <NUM> may include a convolutional LSTM model, which is a type of recurrent neural network having the ability to remember relevant information and to forget irrelevant information. LSTM models may be able to remember relevant information from the past without exhibiting (e.g., being free from) the vanishing gradient problem, wherein a neural network learns slower as more layers are used. A "vanishing gradient," as used herein, refers to a problem in the field of machine learning associated with gradients that carry information used in a neural network parameter update. When a gradient approaches a value close to zero, the parameter updates become insignificant, which means that no real learning is done. The vanishing gradient problem may hamper (e.g., impede) the ability of a neural network to learn long data sequences. The ability of an LSTM model to remember and forget information as needed makes such neural networks advantageous for predicting when a background task may be triggered in a storage device. LSTM models use various sigmoid functions, known as gates, to remember and forget information as needed. An LSTM model may have the ability to apply a convolutional filter to extract relevant information from an input vector of workload characteristics.

In some embodiments, each input vector, including the first input vector V1 discussed above, may be provided as inputs to the neural network circuit <NUM> to process during training and during use to predict when a background task is likely to occur on any storage device. For example, the first input vector V1, as discussed above, corresponding to the I/O trace <NUM> and having a time length T1 equal to <NUM> minutes and a number of characteristics n equal to <NUM> may be input to an input layer <NUM> of the neural network circuit <NUM>. The output of the input layer <NUM> may be provided as an input to a convolutional LSTM model <NUM>. An LSTM network is a type of recurrent neural network that may learn long-term dependencies in sequence prediction problems. LSTM may be useful for predicting when a background task may occur based on workload characteristics because workload characteristics may include a long data sequence. The output of the convolutional LSTM model <NUM> may be provided as an input to a normalization layer <NUM>. The output of the normalization layer <NUM> may be provided as an input to a pooling layer <NUM>. The pooling layer <NUM> may reduce the dimensionality of input feature maps. For example, features in the first input vector V1 and other workload characteristic vectors may be associated with input feature maps, which are processed by the neural network circuit <NUM>. The output of the pooling layer <NUM> may be provided as an input to a dense layer <NUM>. The dense layer <NUM> may be a fully connected layer that helps to change the dimension of input vectors to a desired output vector length for further processing. The output of the dense layer <NUM> may correspond to the background task information <NUM> and may indicate a likelihood that a storage device will perform a next background task based on the extracted workload characteristics <NUM> (see <FIG>).

<FIG> is a flowchart depicting a method of processing an I/O request using machine learning to predict the background task in the storage device, according to some embodiments of the present disclosure.

Referring to <FIG>, the method <NUM> may include the following example operations. An I/O scheduler <NUM> (see <FIG>) may receive an I/O request <NUM> associated with a first storage device 300a (operation <NUM>). The I/O scheduler <NUM> may receive background task information <NUM> from a neural network circuit <NUM>, wherein the background task information <NUM> is associated with a background task, such as a garbage cleaning operation or a wear levelling operation, performed by the first storage device 300a (operation <NUM>). The I/O scheduler <NUM> may cause a modification (e.g., may modify) a processing of the I/O request <NUM> at (e.g., by) the first storage device based on the background task information <NUM> (operation <NUM>).

Claim 1:
A method (<NUM>) of scheduling requests (<NUM>) in a storage system (<NUM>), the method (<NUM>) comprising:
receiving (<NUM>), at a scheduler (<NUM>), an input/output, I/O, request (<NUM>) associated with a first storage device (300a);
receiving (<NUM>), at the scheduler (<NUM>), task information (<NUM>) from a neural network circuit (<NUM>), the task information (<NUM>) being associated with a background task performed by the first storage device (300a); and
modifying (<NUM>) a processing of the request (<NUM>) at the first storage device (300a) based on the task information (<NUM>), wherein the task information (<NUM>) comprises an indication that the first storage device (300a) has a probability of performing the background task that exceeds a threshold,
wherein:
a) when the request (<NUM>) comprises a read request, the modifying the processing of the request (<NUM>) at the first storage device (300a) comprises: prefetching data from the first storage device (300a) based on the task information (<NUM>), storing the data at a buffer (<NUM>) associated with the scheduler (<NUM>), and retrieving at least a portion of the data from the buffer (<NUM>) based on the request (<NUM>) and based on the task information (<NUM>); and
b) when the request (<NUM>) comprises a write request, and the modifying the processing of the request (<NUM>) at the first storage device (300a) comprises rerouting the processing of the request (<NUM>) from the first storage device (300a) to a second storage device (300b) based on the task information (<NUM>).