Patent Description:
For the growth of III-N materials (i.e. GaN, AlN and InN and their alloys) on <NUM>, <NUM>, <NUM>, <NUM>, or even larger Si substrates, it is often discovered that although the tensile strain due to thermal mismatch is carefully compensated by a strain engineered buffer, the wafer is fragile during further process handling. The fragility manifests itself e.g. in the GaN-on-Si wafers breaking into large pieces with fairly high frequency during steps involving thermal processing (e.g. anneals, high temperature film deposition/etching etc.) and mechanical handling (e.g. chemo-mechanical polishing, wafer bonding etc.).

For example, it was noticed that the fragility of <NUM> diameter <NUM> thick GaN-on-Si wafers was caused primarily by the formation of slip-lines in the Si substrate during the substrate annealing step e.g. before the Low Temperature (LT)-AlN deposition. This is believed to be due to the presence of vertical and radial temperature variations across the <NUM> Si substrate. The Si crystal slip takes place if the local stress exceeds the yield strength at the annealing temperature (<NUM>) prior to the LT-AlN growth. There are two possible major sources of stress on the Si substrate in MOCVD growth. They are the contact stresses between the wafer and the point at which it contacts the susceptor, and the thermal stress due to temperature non-uniformity in the vertical and radial directions across the wafer. The slip lines originate from the edge of the wafer and propagate toward the center of the wafer. Minimizing radial temperature differences across the <NUM> Si wafer during growth through the optimization of heater zone settings is one key way to reduce slip formation and wafer fragility, but it is not possible to fully eliminate vertical temperature differences through the wafer due to heat only being supplied to the back-side of the wafer. Thus, in almost all cases, wafer fragility remains an issue due to the high growth temperatures involved in III-nitride on Si epitaxy.

<CIT> describes a method of manufacturing an III-N substrate includes bonding a Si substrate to a support substrate, the Si substrate having a (<NUM>) growth surface facing away from the support substrate, thinning the Si substrate at the (<NUM>) growth surface to a thickness of <NUM> or less, and forming III-N material on the (<NUM>) growth surface of the Si substrate after the Si substrate is thinned. The support substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si substrate.

<CIT> describes composite substrates that include a strained III-nitride material seed layer on a support substrate. Methods of producing the composite substrate include developing a desired lattice strain in the III-nitride material to produce a lattice parameter substantially matching a lattice parameter of a device structure to be formed on the composite substrate. The III-nitride material may be formed with a Ga polarity or a N polarity. The desired lattice strain may be developed by forming a buffer layer between the III-nitride material and a growth substrate, implanting a dopant in the III-nitride material to modify its lattice parameter, or forming the III-nitride material with a coefficient of thermal expansion (CTE) on a growth substrate with a different CTE.

<CIT> describes a semiconductor structure including a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about <NUM>.

Embodiments of the present invention seek to address at least one of the above problems.

In accordance with a first aspect of the present invention, there is provided a method of fabricating a device on a Si[<NUM>] substrate as defined in claim <NUM>. Further features of example embodiments are defined in the dependent claims.

In example embodiments of graded AlGaN layers, for example <NUM> graded AlGaN layers with Al content of <NUM>%, <NUM>% and <NUM>% (starting from e.g. a Si (<NUM>) substrate), were grown on top of a AlN/Si structure at a temperature of <NUM>. Example embodiments use a strain compensation method in GaN-on-Si heteroepitaxy. The basic idea is to introduce compressive strain during epitaxial growth by employing the in-plane lattice mismatch in the AlGaN material system to compensate for the large tensile strain due to thermal mismatch generated during cooling from growth temperature to room temperature. The stress evolution of step-graded AlGaN is discussed in detail based on the basic strain engineering principle. While the difficulty in strain engineering on a <NUM> thick <NUM> diameter Si wafer can be reduced by employing a shaped susceptor that decouples the change in thermal conduction from wafer curvature change, example embodiments of the present invention apply Al<NUM>Ga<NUM>N layer thickness adjustment and preferably SiNx in situ masking to tune the final bow of the GaN-on-Si wafers. Usually, a more convex wafer is produced from an increase in Al<NUM>Ga<NUM>N layer thickness and Threading Dislocation Density (TDD), in general, improves as well. However, the composition of screw and edge Threading Dislocation (TD) changes with Al<NUM>Ga<NUM>N layer thickness. Usually, <NUM> of GaN can be deposited with a SiNx in situ masking layer inserted after <NUM> of GaN at <NUM>. In the case of SiNx in situ masking, it decouples the compressive strain of the GaN from the Al<NUM>Ga<NUM>N layer, so the GaN layer is less compressive. TDD monotonically improves with the coverage of SiNx. In preferred embodiments, Al<NUM>Ga<NUM>N layer thickness and SiNx in situ masking duration are combined to advantageously produce a bow-free wafer with minimum TDD on <NUM> thick <NUM> diameter Si wafers.

It is noted that in various embodiments the other e.g. <NUM>% and <NUM>% Al content AlGaN buffer layers can advantageously also help in the strain engineering. However, it is expected that in the step-graded buffer system according to example embodiments, it is the layers with lowest e.g. Al content (i.e. <NUM>% Al and <NUM>% Al == GaN) that adds the most compressive strain to the system, and thus has the greatest effect on bow control.

Example embodiments of the present invention provide a method to replace the initial substrate, Si (<NUM>), that contains slips with a new, slip-free substrate, a Si (<NUM>) substrate. Through this method, the thick buffer layers that may have been used for strain engineering can also be removed and a thin device layer structure on Si can be realized even when buffer layers are used for strain engineering. In addition, the stress of e.g. GaN can be manipulated by adjusting the final GaN thickness. Additionally or alternatively, the Si (<NUM>) substrate can also have the advantage of being accepted and processed in commercial CMOS foundries easily.

<FIG> and <FIG> show a sequence of steps for substrate replacement according to an example embodiment. In this embodiment, the graded layer approach for strain management discussed above has been used, however, different strain engineering methods may be applied in the formation of a starting GaN on Si (<NUM>) substrate, containing e.g. one or more GaN device layers,in different embodiments,.

As shown in <FIG>, prior to the actual epitaxial growth, a Si (<NUM>) substrate <NUM> was first in situ annealed to remove native oxide. Then, a <NUM> low-temperature (LT) AlN nucleation layer 106a was grown at <NUM>. The temperature was increased to grow a high-temperature (HT)-AlN layer 106b, with AlN precursor flow being maintained during the temperature ramping (<NUM> of AlN deposition took place during the temperature ramping). After <NUM> AlN (106a/b) growth, step-graded AlxGa<NUM>-xN layers (<NUM> <NUM>% Al layer <NUM>, <NUM> <NUM>% Al layer <NUM> and <NUM> <NUM>% Al layer <NUM>) are grown to introduce compressive strain to compensate the tensile strain built up in the subsequent grown GaN layers when the wafer is cooled down after growth. Usually, the growth of <NUM> to a few µm u-GaN layer <NUM> with SiNx masking layer <NUM> is carried out before the growth of the device layer(s) <NUM>.

It is noted that in this example embodiment, the epitaxy is Ga-polar/metal-polar, which is the more typical case as will be appreciated by a person skilled in the art. However, N-polar epitaxy is possible in different embodiments. The terms "N-polar" and "Ga-polar/metal-polar" refer to the atomic arrangement at the top (accessible) surface of the wafer, and the polarity/arrangement is generally preserved throughout the various material layers. With reference to <FIG> the polarity of the top (accessible) surface of the GaN device layer(s) <NUM> is Ga-polar in this embodiment, and thus the wafer is considered to have a Ga-polar surface, and correspondingly the bottom of the GaN device layer(s) <NUM> will have an N-polarity. As the polarity is preserved across each layer, it should be noted that the top of the adjacent GaN layer <NUM> will have a Ga-polar surface again, while the bottom of the GaN layer <NUM> will have an N-polarity. The converse is true for all the polarities for a starting/growth wafer with an N-polar surface in different embodiments.

With reference to step <NUM> of <FIG>, in this example embodiment, SiO<NUM> <NUM> was then deposited on the wafer <NUM> (i.e. the Si (<NUM>) substrate <NUM>, the AlN layer 106a/b, <NUM> graded AlGaN buffer layers <NUM>-<NUM> with Al content of <NUM>%, <NUM>% and <NUM>% respectively, GaN layer <NUM> with SiNx masking (not shown), which is considered a buffer layer in example embodiments, followed by the GaN device layer(s) <NUM>) and then densified at high temperature (e.g. ~ <NUM>, several hrs) under N<NUM> ambient. The SiO<NUM> layer <NUM> can be replaced by Si<NUM>N<NUM>, Al<NUM>O<NUM>, AlN (aluminum nitride), BN (boron nitride) and other dielectrics in different embodiments (as well as a combination of different dielectrics, e.g. SiO<NUM>+Si<NUM>N<NUM>) to improve the thermal conductivity as well as bonding strength. To achieve a successful fusion bonding, the RMS roughness of the wafer surface is preferably < <NUM>. Hence, the wafer <NUM>, after dielectric deposition, was polished using Chemical Mechanical Polishing (CMP) followed by RCA clean in example embodiments. Another Si (<NUM>) substrate/wafer <NUM> was used and served as a donor wafer.

Prior to bonding, both wafers (i.e. wafer <NUM>, after dielectric deposition, and Si (<NUM>) substrate <NUM>) were subjected to plasma exposure (e.g. O<NUM>, N<NUM>, H<NUM>, Ar, etc) for several seconds, rinsed with deionized water and then spin-dried in example embodiments. Plasma exposure can increase the surface hydrophilicity of the dielectric (e.g. SiO<NUM> layer <NUM>). The rinsing step terminates the wafers' surfaces with hydroxyl (OH) groups at a sufficiently high density to initiate wafer bonding. After bonding, which is based on van-der-Waals forces between the hydrogen atoms in this example embodiment, the wafer pair <NUM>/<NUM> was annealed at <NUM> in an atmospheric N<NUM> ambient for <NUM> hrs to further enhance the bond strength. It is noted that the bonding can be done with any reasonable Si (<NUM>) wafer's <NUM> starting bow value, e.g. absolute bow < <NUM>, with the final wafer bow being advantageously optimized as described in more detail below, and in general a final wafer bow < <NUM> is desirable to improve the yield of subsequent fabrication processing.

With reference to step <NUM> of <FIG>), grinding of the Si (<NUM>) <NUM> (to <NUM> in this example embodiment) was performed. After that, a protective layer from Brewer Science <NUM> (which is able to survive in acidic environment) was deposited, e.g. spin coated, on the backside of the Si (<NUM>) <NUM> donor wafer to act as a protection layer during the Si removal process from the Si (<NUM>) <NUM> substrate. The remaining Si (<NUM>) is removed in this example embodiment by submerging the wafer bonded pair into the HNA solution (e.g. HF : Nitric acid : Acetic acid = <NUM> : <NUM> : <NUM> in volume, noting that the ratio can be changed to achieve different etching rates as desired). The AlN <NUM> was used as an etch-stop layer in this example embodiment, since the etching selectivity of AlN over Si is high in the HNA solution used. The etching was carried out at room temperature and until the Si was completely removed, which can be determined by noting when effervescence within the etchant ceases. The protective layer was removed by acetone resulting in the structure as shown in step <NUM> of <FIG>.

The AlN <NUM>, the <NUM> AlGaN buffers <NUM>-<NUM>, and the GaN layer can then be removed, e.g. by inductive coupled plasma reactive ion etching (ICP-RIE) or CMP process. According to the claimed invention, one or more of the buffer layers remain, e.g. due to the bow/strain requirements. A GaN device layer <NUM> with an N-polar surface can thus be obtained, as shown in step <NUM> of <FIG>). This is because the wafer has been vertically inverted in the intervening step <NUM>, so what used to be the Ga-polar top (accessible) surface of GaN device layer <NUM> in step <NUM> is now (in step <NUM>) the bottom layer (bonded to the SiO2 layer <NUM>), and thus the new top (accessible) surface is the previous N-polar surface of GaN device layer <NUM> that was adjacent to GaN layer <NUM> (in step <NUM>). To achieve good process yield, it may be preferred to have an appropriate etch-stop layer (not shown) in such embodiment so that the ICP-RIE or CMP process in step <NUM> ends at the proper depth to result in the desired N-polar surface.

To realize a GaN layer <NUM> with a Ga-polar surface from step <NUM> in a continuation of the process of this example embodiment, a SiO<NUM> layer (or other dielectric or a combination of dielectrics) <NUM> was deposited on the wafer of step <NUM> in <FIG> and then densified. CMP process was carried out to smoothen the SiO<NUM> film <NUM> to achieve a successful bonding. After the CMP process, the wafer was RCA cleaned and bonded to another Si (<NUM>) handle substrate <NUM>, as shown in step <NUM> of <FIG>. The bonding process was similar to the one described above with reference to step <NUM> of <FIG>). After the bonding, the same grinding as described above for the removal of the Si (<NUM>) substrate <NUM> with reference to step <NUM>, and tetramethylammonium hydroxide (TMAH) etching is used for the removal of the Si (<NUM>) substrate <NUM>, resulting in the wafer depicted in step <NUM> of <FIG>), with a GaN layer(s) <NUM> with a Ga-polar surface.

It is again noted that if a Ga-polar surface is desired at the end of the etching in step <NUM>, without the <NUM>nd bonding step described above, a way to do it would be to grow an inverted device epi-structure (compare <FIG>) with an N-polar top (accessible) surface of the GaN device layer <NUM>, according to a different embodiment, instead of the Ga-polar top (accessible) surface of GaN device layer <NUM>. This effectively inverts the polarity of the exposed (layer <NUM> in step <NUM>) GaN surface to be Ga-polar at that point, thereby removing the need for steps <NUM> (<NUM>nd bonding step) and <NUM> for obtaining the Ga-polar device layer in such an embodiment. To achieve good process yield, it may again be preferred to have an appropriate etch-stop layer in such embodiment so that the ICP-RIE or CMP process in step <NUM> ends at the proper depth to result in the desired Ga-polar surface.

<FIG> shows a cross-sectional Scanning Electron Microscopy (SEM) image of the structure of step <NUM> in <FIG>, i.e. after the 1st bonding and Si (<NUM>) substrate <NUM> removal.

<FIG> shows a cross-sectional SEM image of the structure of step <NUM> in <FIG>, i.e. after the removal of AlN <NUM>, AlGaN buffers <NUM>-<NUM>, GaN layer <NUM> and parts of GaN layer(s) <NUM> through ICP-RIE.

<FIG> shows experimental results of the analysis of the lattice constant of the GaN for a <NUM> graded AlGaN layers strain engineered example , at different steps of buffer layer/GaN removal, i.e. with different "top" layers exposed to the ambient around the wafer.

As can be seen from the results shown in <FIG>, by controlling the final GaN thickness (compare tB and tC for samples B and C respectively), the stress of the GaN can be manipulated from <NUM> GPa to <NUM> GPa and even higher tensile stress is achievable with a much thinner GaN. Highly tensile strain GaN layer(s) may e.g. be desired to increase the electron mobility and hence improve the performance of High-Electron-Mobility Transistors (HEMTs). Advantageously, since the fragile Si(<NUM>) substrate was replaced by the Si(<NUM>) donor substrate in example embodiments, the high tensile strain of the GaN layer(s) does not cause breaking of the wafer.

<FIG> shows experimental results of the analysis of wafer bow for the <NUM> graded AlGaN layers strain engineered example, at different steps of buffer layer/GaN removal. As can be seen from <FIG>, the final wafer bow (-<NUM>, compare numeral <NUM>) after removing the AIN, AlGaN buffers, u-GaN and parts of n-GaN layers is getting smaller compared to the wafer bow (-<NUM>, compare numeral <NUM>) with all layers, including the buffer layers, present. It is noted that the n-GaN layers as indicated in <FIG> include the device layer(s). As can be seen from <FIG>, bow of the initial GaN/buffers/Si (compare sample A in <FIG>) is -<NUM>, the bow is increased to -<NUM> after removal of AlN buffer layer according to an example embodiment, and the bow is reduced to -<NUM> after removal of AlN+AlGaN1+AlGaN2+AlGaN <NUM> buffers according to another example embodiment. Finally, the bow of the GaN/SiO2/Si (compare sample C in <FIG>) is reduced to -<NUM> after all the buffer layers are removed.

<FIG> shows a flow chart <NUM> illustrating a method of fabricating a device on a carrier substrate, according to an example embodiment. At step <NUM>, a first substrate is provided. At step <NUM>, one or more device layers are formed on the first substrate. At step <NUM>, a second substrate is bonded to the device layers on a side thereof opposite to the first substrate. At step <NUM> the first substrate is removed. The carrier substrate is a Si[<NUM>] substrate and the first substrate is a Si[<NUM>] substrate. The one or more device layers are one or more GaN device layers.

Forming the device layers comprises forming a plurality of AlGaN buffer layers with different compositions and a GaN buffer layer with a SiNx masking layer disposed therein on the plurality of AlGaN buffer layers prior to forming the one or more GaN device layers on the plurality of AlGaN buffer layers and the GaN buffer layer. The plurality of buffer layers and the one or more device layers are grown by epitaxial growth. The method further comprises removing one or more of the plurality of AlGaN buffer layers and the GaN buffer layer such that some of the plurality of AlGaN buffer layers and the GaN buffer layer remain on the first Si[<NUM>] substrate together with the one or more GaN device layers.

The method may further comprise bonding a second substrate to at least a portion of the device layers on a side thereof opposite to the second substrate, and removing the first substrate.

The polarity of the device layers may be inverted as a result of the bonding to the third substrate and the removing of the second substrate. The second substrate is a Si[<NUM>] substrate. The method may further comprise providing another etch-stop layer and using the other etch-stop layer to achieve a desired polarity of the device layers with high yield.

Embodiments of the present invention can have one or more of the following characteristics/advantages:.

It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiments.

For example, in different embodiments not claimed as such, the concept of the present invention can be applicable to other device layer(s), including to other semiconductor material systems. For example, the tensile thermal mismatch in heteroepitaxial InGaP (e.g. for a light emitting device (LED)) on Si with Ge and GaAs buffer cause the wafer to have a large concave bow. In such embodiments, the method to replace the original Si substrate and remove the Ge and GaAs buffer can also be applied to improve wafer stability.

Also, while the use of a graded structure for strain engineering/control has been described in the example embodiments herein, the concept of the present invention can be applied to wafers with different types of strain engineering (e.g. superlattice buffers etc.) in different embodiments not claimed as such.

Claim 1:
A method of fabricating a device on a Si[<NUM>] substrate, the method comprising:
providing a Si[<NUM>] substrate (<NUM>);
forming one or more GaN device layers (<NUM>) on the Si[<NUM>] substrate (<NUM>);
bonding a first Si[<NUM>] substrate (<NUM>) to the one or more GaN device layers (<NUM>) on a side thereof opposite to the Si[<NUM>] substrate (<NUM>); and
removing the Si[<NUM>] substrate (<NUM>);
wherein forming the one or more GaN device layers (<NUM>) comprises forming a plurality of AlGaN buffer layers (<NUM>, <NUM>, <NUM>) with different compositions and a GaN buffer layer (<NUM>) with a SiNx masking layer disposed therein on the plurality of AlGaN buffer layers (<NUM>, <NUM>, <NUM>) prior to forming the one or more GaN device layers (<NUM>) on the plurality of AlGaN buffer layers (<NUM>, <NUM>, <NUM>) and the GaN buffer layer (<NUM>);
wherein the plurality of buffer layers (<NUM>, <NUM>, <NUM>, <NUM>) and the one or more GaN device layers (<NUM>) are grown by epitaxial growth;
the method further comprising removing one or more of the plurality of AlGaN buffer layers (<NUM>, <NUM>, <NUM>) and the GaN buffer layer (<NUM>) such that some of the plurality of AlGaN buffer layers (<NUM>, <NUM>, <NUM>) and the GaN buffer layer (<NUM>) remain on the first Si[<NUM>] substrate (<NUM>) together with the one or more GaN device layers (<NUM>).