Patent Description:
Due to the development of electronics technology, the downscaling of semiconductor devices has rapidly progressed. Thus, a transistor including a channel layer adopting an oxide semiconductor material has been proposed to reduce leakage current through a channel region.

<CIT> discloses a semiconductor memory device including a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

<CIT> discloses a vertical transistor having different doping profiles in an upper channel layer and a lower channel layer to reduce a leakage current while reducing contact resistance and a vertical transistor manufacturing method.

The inventive concept provides a semiconductor device of which reliability is improved by reducing contact resistance between a channel structure and a conductive contact pattern in contact with the channel structure in a transistor including the channel structure adopting an oxide semiconductor material.

According to an aspect of the inventive concept, there is provided a semiconductor device includes an upper conductive line on a substrate, a channel structure adjacent the upper conductive line, a gate dielectric film between the channel structure and the upper conductive line, and a conductive contact pattern electrically connected to the channel structure. The channel structure includes a main channel portion including an oxide semiconductor layer having a first composition, and a channel contact portion between the main channel portion and the conductive contact pattern. The channel contact portion is in contact with the conductive contact pattern and includes a material having a second composition that is different from the first composition. The channel contact portion and the oxide semiconductor layer respectively comprise one or more same elements, and the channel contact portion further comprises at least one dopant, wherein the at least one dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H).

The same reference numerals are used to denote the same elements in the drawings, and repeated descriptions thereof are omitted.

<FIG> is a plan layout diagram of some components of a semiconductor device <NUM> according to embodiments. <FIG> is a cross-sectional view taken along line A - A' of <FIG>, and <FIG> is a cross-sectional view taken along line B - B' of <FIG>. <FIG> is an enlarged cross-sectional view of portion "EX1" of <FIG>.

Referring to <FIG> and <FIG>, the semiconductor device <NUM> may include a substrate <NUM>, a peripheral circuit structure PCA including a plurality of peripheral circuits on the substrate <NUM>, and a plurality of bit lines BL and a plurality of shielding structures SL on the peripheral circuit structure PCA.

In embodiments, the substrate <NUM> may include silicon, for example, single crystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate <NUM> may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In embodiments, the substrate <NUM> may include a conductive region, for example, a doped well or a doped structure.

Each of the plurality of bit lines BL may be connected to at least one of the plurality of peripheral circuits included in the peripheral circuit structure PCA. Elements referred to herein as "connected to" may be electrically and/or physically connected. Each of the plurality of shielding structures SL may be floated, that is, in an electrically floating state. The plurality of bit lines BL and the plurality of shielding structures SL may be insulated from each other by an interlayer insulating film 106F. The plurality of shielding structures SL may be covered by an interlayer insulating film <NUM>, and the plurality of bit lines BL may pass through the interlayer insulating films 106F and <NUM> in a vertical direction (Z direction). The plurality of bit lines BL may be connected to the peripheral circuits included in the peripheral circuit structure PCA through a plurality of conductive plugs (e.g., P1, P2, and P3) included in the peripheral circuit structure PCA and some selected from a plurality of wiring layers (e.g., M1 and M2).

The peripheral circuit structure PCA may include a plurality of core circuits <NUM>. The plurality of core circuits <NUM> may include a first conductive pattern C1 and a second conductive pattern C2, which are sequentially on the substrate <NUM>. The terms "first," "second," etc., may be used herein merely to distinguish one element or layer from another. The first conductive pattern C1 and the second conductive pattern C2 may constitute various circuit elements, which are on the peripheral circuit structure PCA to control the functions of the semiconductor device <NUM>. In embodiments, the peripheral circuit structure PCA may further include various active elements (e.g., transistors) and various passive elements (e.g., capacitors, resistors, and inductors). The terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated elements, but do not preclude the presence of additional elements.

In embodiments, the plurality of peripheral circuits in the peripheral circuit structure PCA may include a sub-word line driver block SWD, a sense amplifier block S/A, and/or a control logic, without being limited thereto. The plurality of peripheral circuits in the peripheral circuit structure PCA may include an NMOS transistor and a PMOS transistor. The plurality of peripheral circuits may be electrically connected to conductive lines (e.g., a plurality of bit lines BL), which are on the peripheral circuit structure PCA, through the plurality of conductive plugs (e.g., P1, P2, and P3), and the plurality of wiring layers (e.g., M1 and M2).

In the peripheral circuit structure PCA, of the plurality of core circuits <NUM>, the plurality of conductive plugs (e.g., P1, P2, and P3), and the plurality of wiring layers (e.g., M1 and M2), portions that need to be insulated from each other may maintain a required insulation distance apart from each other by a plurality of interlayer insulating films (e.g., 106A, 106B, 106C, 106D, and 106E). Each of the plurality of interlayer insulating films (e.g., 106A, 106B, 106C, 106D, and 106E) may include an oxide film, a nitride film, or a combination thereof, without being limited thereto.

In embodiments, the peripheral circuit structure PCA on the substrate <NUM> may be omitted. In this case, the peripheral circuit structure PCA may be in another region apart from the region shown in <FIG> and <FIG> on the substrate <NUM>. In other embodiments, the peripheral circuit structure PCA may be in a region that is spaced apart from a cell array region including a transistor region or a boundary thereof (refer to TRR in <FIG>) in a lateral direction.

The plurality of bit lines BL and the plurality of shielding structures SL may be spaced apart from each other in a first lateral direction (X direction) on the substrate <NUM> and extend long in a second lateral direction (Y direction) that is perpendicular to the first lateral direction (X direction). The plurality of bit lines BL and the plurality of shielding structures SL may extend parallel to each other in the second lateral direction (Y direction). In embodiments, each of the plurality of bit lines BL may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tungsten silicide (WSi), tungsten silicon nitride (WSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), cobalt silicide (CoSi), nickel silicide (NiSi), polysilicon, or a combination thereof, without being limited thereto. As used herein, the bit line BL may be referred to as a lower conductive line. In embodiments, each of the plurality of shielding structures SL may include tungsten (W), aluminum (Al), copper (Cu), or a combination thereof, without being limited thereto. In embodiments, each of the plurality of shielding structures SL may include a conductive film and an air gap or a void in the conductive film. The conductive film may include W, Al, Cu, or a combination thereof.

A mold insulating pattern <NUM> may be on the plurality of bit lines BL and the plurality of shielding structures SL. The mold insulating pattern <NUM> may have a sidewall <NUM> defining the transistor region (refer to TRR in <FIG>). Each of the mold insulating pattern <NUM> and the transistor region TRR, which is defined by the sidewall <NUM> in the mold insulating pattern <NUM>, may extend long in the first lateral direction (X direction). The mold insulating pattern <NUM> may include a silicon oxide film, a silicon nitride film, or a combination thereof.

As shown in <FIG> and <FIG>, in the transistor region TRR, a plurality of channel structures CS1 may be arranged in a line in or aligned along the first lateral direction (X direction). Each of the plurality of channel structures CS1 may include a vertical channel portion VC facing the sidewall <NUM> of the mold insulating pattern <NUM> and a lateral channel portion HC in contact with a top surface of the bit line BL. When elements or layers are referred to herein as being "directly on" or "in direct contact with" one another, no intervening elements or layers are present.

In each of the plurality of channel structures CS1, the vertical channel portion VC may be in contact with the sidewall <NUM> of the mold insulating pattern <NUM> and extend long from the lateral channel portion HC in the vertical direction (Z direction).

Each of the plurality of channel structures CS1 may include a main channel portion <NUM> and a channel contact portion <NUM> on an uppermost surface of the main channel portion <NUM>. In the channel structure CS1, a portion of the vertical channel portion VC and the lateral channel portion HC may include the main channel portion <NUM>. In the channel structure CS1, an end portion of the vertical channel portion VC, which is farthest from the substrate <NUM>, may include the channel contact portion <NUM>. The channel contact portion <NUM> may be at an uppermost portion of the vertical channel portion VC.

A plurality of transistors including the plurality of channel structures CS1 may be in the transistor region TRR. The plurality of transistors may include two transistors, which face each other in the second lateral direction that is perpendicular to the first lateral direction (X direction). The two transistors may share a selected one of the plurality of channel structures CS1 therebetween.

In each of the plurality of channel structures CS1, the main channel portion <NUM> may be in contact with a top surface of a selected one of the plurality of bit lines BL. The main channel portion <NUM> may include an oxide semiconductor layer having a first composition, and the channel contact portion <NUM> may include a material having a second composition. The second composition may be different from the first composition.

In embodiments, the oxide semiconductor layer included in the main channel portion <NUM> may include indium gallium zinc oxide (InGaZnO or IGZO), tin-doped IGZO (Sn-IGZO), indium tungsten oxide (InWO or IWO), indium zinc oxide (InZnO or IZO), zinc tin oxide (ZnSnO or ZTO), zinc oxide (ZnO), yttrium-doped zinc oxide (YZO), indium gallium silicon oxide (InGaSiO or IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), silicon indium zinc oxide (SiInZnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), or a combination thereof. For example, the main channel portion <NUM> may include IGZO.

In embodiments, the channel contact portion <NUM> may include the same elements as those of the oxide semiconductor layer included in the main channel portion <NUM>, and further includes at least one dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H).

In other embodiments, the channel contact portion <NUM> may include a second oxide semiconductor material, which has a different composition from a first oxide semiconductor material included in the main channel portion <NUM>, and further includes at least one dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H). Each of the first oxide semiconductor material and the second oxide semiconductor material may include IGZO, Sn-IGZO, IWO, IZO, ZTO, ZnO, YZO, IGSO, InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, or a combination thereof. In embodiments, the first oxide semiconductor material and the second oxide semiconductor material may include respectively different materials, each of which is selected from the materials described above. In other embodiments, the main channel portion <NUM> may include IGZO, and the channel contact portion <NUM> may include indium aluminum zinc oxide (IAZO).

As shown in <FIG> and <FIG>, a gate dielectric film <NUM> covering the channel structure CS1 and a plurality of word lines WL covering the gate dielectric film <NUM> may be in the transistor region TRR. The plurality of word lines WL may extend long and parallel to each other in the first lateral direction (X direction). <FIG> and <FIG> illustrate a configuration in which two word lines WL are in one transistor region TRR. As used herein, the word line WL may be referred to as an upper conductive line. In the transistor region TRR, the one word line WL may be in contact with the one gate dielectric film <NUM>, and the one word line WL may face the plurality of channel structures CS1 with the one gate dielectric film <NUM> therebetween.

As shown in <FIG>, each of the plurality of word lines WL may include a first portion and a second portion. The first portion may face the channel structure CS1 with the gate dielectric film <NUM> therebetween. The second portion may face the mold insulating pattern <NUM> with only the gate dielectric film <NUM> therebetween without the channel structure CS1. In each of the plurality of word lines WL, the second portion may be closer to the mold insulating pattern <NUM> than the first portion in the second lateral direction (Y direction).

As shown in <FIG>, the bit line BL may be spaced apart from the word line WL with the channel structure CS1 and the gate dielectric film <NUM> therebetween in the vertical direction (Z direction). The bit line BL may have a top surface in contact with the main channel portion <NUM> of the channel structure CS1.

In the transistor region TRR, the channel structure CS1 may face one surface of each of each of two word lines WL in the transistor region TRR. The gate dielectric film <NUM> may include portions in contact with the plurality of channel structures CS1 and portions in contact with a sidewall <NUM> of the mold insulating pattern <NUM>. The gate dielectric film <NUM> may include portions between the one surface of each of the two word lines WL and the vertical channel portion VC of the channel structure CS1 and portions between a bottom surface of each of the two word lines WL and the lateral channel portion HC of the channel structure CS1.

The gate dielectric film <NUM> may be between the channel structure CS1 and the word line WL. An uppermost surface of the channel structure CS1 may be closer to the substrate <NUM> than an uppermost surface of each of the gate dielectric film <NUM>, the plurality of word lines WL, and the mold insulating pattern <NUM>.

In embodiments, the gate dielectric film <NUM> may have a high-k dielectric film having a higher dielectric constant than a silicon oxide film. In embodiments, the gate dielectric film <NUM> may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). Each of the plurality of word lines WL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

A lower insulating partition wall <NUM> may be on the channel structure CS1 between the two word lines WL located in the one transistor region TRR. A top surface of each of the two word lines WL and a top surface of the lower insulating partition wall <NUM> may be covered by an upper insulating partition wall <NUM>. In the second lateral direction (Y direction), a width of the upper insulating partition wall <NUM> may be greater than a width of the lower insulating partition wall <NUM>. Each of the lower insulating partition wall <NUM> and the upper insulating partition wall <NUM> may include a silicon oxide film, a silicon nitride film, or a combination thereof.

A plurality of conductive contact patterns 150P may be on the plurality of channel structures CS1. Each of the plurality of conductive contact patterns 150P may be connected to a selected one of the plurality of channel structures CS1.

As shown in <FIG>, the plurality of conductive contact patterns 150P may be regularly arranged a predetermined distance apart from each other in the first lateral direction (X direction) and the second lateral direction (Y direction). <FIG> illustrates an example in which the plurality of conductive contact patterns 150P are arranged in a matrix or array form on a plane (e.g., X-Y plane) on the substrate <NUM>, but the inventive concept is not limited thereto. For example, the plurality of conductive contact patterns 150P may be arranged in a honeycomb structure or pattern on the plane (e.g., X-Y plane) on the substrate <NUM>. The plurality of conductive contact patterns 150P may be insulated from each other by an isolation insulating film <NUM>.

The main channel portion <NUM> of the channel structure CS1 may be spaced apart from the conductive contact pattern 150P. The channel contact portion <NUM> may be between the main channel portion <NUM> and the conductive contact pattern 150P. Each of the plurality of conductive contact patterns 150P may be spaced apart from the main channel portion <NUM> in the vertical direction (Z direction). Each of the plurality of conductive contact patterns 150P may have a surface in contact with the channel contact portion <NUM>.

The plurality of conductive contact patterns 150P may be spaced apart from the word line WL by the gate dielectric film <NUM>. As shown in <FIG>, each of the plurality of conductive contact patterns 150P may include a lower contact portion <NUM> and an upper pad portion 150U. The lower contact portion <NUM> may be between the gate dielectric film <NUM> and the mold insulating pattern <NUM>. The upper pad portion 150U may be on the lower contact portion <NUM> and integrally connected to the lower contact portion <NUM>. The lower contact portion <NUM> of each of the plurality of conductive contact patterns 150P may have a sidewall facing the gate dielectric film <NUM>, a sidewall facing the mold insulating pattern <NUM>, and a bottom surface in contact with a top surface of the channel contact portion <NUM>. The upper pad portion 150U of each of the plurality of conductive contact patterns 150P may cover a top surface of each of the gate dielectric film <NUM>, the mold insulating pattern <NUM>, and the upper insulating partition wall <NUM>.

Each of the plurality of conductive contact patterns 150P may include a metal-containing film. In embodiments, each of the plurality of conductive contact patterns 150P may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, or a combination thereof. For example, each of the plurality of conductive contact patterns 150P may have a stack structure of a conductive barrier including TiN and a conductive film including W.

The gate dielectric film <NUM> may include a dielectric film barrier liner 130W in contact with the lower contact portion <NUM> of the conductive contact pattern 150P. The dielectric film barrier liner 130W may include a material constituting the gate dielectric film <NUM> and further include a dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H). In embodiments, the dielectric film barrier liner 130W may include a metal oxide film including a dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H). The dielectric film barrier liner 130W may act as a barrier capable of suppressing an undesired reaction of a metal (e.g., tungsten) included in the conductive contact pattern 150P with a material (e.g., oxygen atoms) included in the gate dielectric film <NUM>.

The mold insulating pattern <NUM> may include a mold barrier liner 110W in contact with the lower contact portion <NUM> of the conductive contact pattern 150P. The mold barrier liner 110W may include a material constituting the mold insulating pattern <NUM> and further include a dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H). In embodiments, the mold barrier liner 110W may include a silicon oxide film including the dopant, a silicon nitride film including the dopant, or a combination thereof The mold barrier liner 110W may act as a barrier capable of suppressing an undesired reaction of a metal (e.g., tungsten) included in the conductive contact pattern 150P with a material (e.g., oxygen atoms) included in the mold barrier liner 110W or in the mold insulating pattern <NUM>.

The semiconductor device <NUM> may further include a plurality of capacitor structures CAP on the plurality of conductive contact patterns 150P. An etch stop film <NUM> and an interlayer insulating film <NUM> may be sequentially stacked on the plurality of conductive contact patterns 150P and the isolation insulating film <NUM>. Each of the plurality of capacitor structures CAP may be connected to a selected one of the plurality of conductive contact patterns 150P by passing through the interlayer insulating film <NUM> and the etch stop film <NUM> in the vertical direction (Z direction). The etch stop film <NUM> may include a silicon nitride film, and the interlayer insulating film <NUM> may include a silicon oxide film.

<FIG> is a cross-sectional view of a semiconductor device 100A according to embodiments. <FIG> illustrates an enlarged cross-sectional configuration of a portion corresponding to portion "EX1" of <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG> and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG>, the semiconductor device 100A may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG> and <FIG> to 2C. However, the semiconductor device 100A may include a channel structure CS1A between a gate dielectric film <NUM> and a mold insulating pattern <NUM>. The channel structure CS1A may include a main channel portion 120A and a channel contact portion 122A on an uppermost surface of the main channel portion 120A. The main channel portion 120A and the channel contact portion 122A may respectively have concave top surfaces T1 and T2, which are concave toward a conductive contact pattern 150P. Details of the main channel portion 120A and the channel contact portion 122A may substantially be the same as those of the main channel portion <NUM> and the channel contact portion <NUM>, which have been described with reference to <FIG> and <FIG>.

<FIG> is a cross-sectional view of a semiconductor device 100B according to embodiments. <FIG> illustrates an enlarged cross-sectional configuration of a portion corresponding to portion "EX1" of <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG> and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG>, the semiconductor device 100B may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG> and <FIG> to 2C. However, the semiconductor device 100B may include a conductive contact pattern 150PB. The conductive contact pattern 150PB may include a lower contact portion 150LB and an upper pad portion 150U. The lower contact portion 150LB may be between a gate dielectric film <NUM> and a mold insulating pattern <NUM>. The upper pad portion <NUM> may be on the lower contact portion 150LB and integrally connected to the lower contact portion 150LB.

The mold insulating pattern <NUM> may have a sidewall <NUM> in contact with the conductive contact pattern 150PB, and the sidewall <NUM> may include an inclined surface such that a distance between the sidewall <NUM> of the mold insulating pattern <NUM> and the gate dielectric film <NUM> gradually increases in a direction away from the substrate (refer to <NUM> in <FIG>). The mold barrier liner 110W included in the mold insulating pattern <NUM> may extend along the inclined surface of the sidewall <NUM>. Because the sidewall <NUM> of the mold insulating pattern <NUM> includes the inclined surface, when the conductive contact pattern 150PB is formed in the process of manufacturing the semiconductor device 100B, excellent gap-fill characteristics may be provided during a deposition process for filling a relatively narrow space between the gate dielectric film <NUM> and the mold insulating pattern <NUM> with a conductive material.

The lower contact portion 150LB of the conductive contact pattern 150PB may have a contact surface facing the sidewall <NUM> including the inclined surface, and the contact surface may include an inclined surface having a shape corresponding to the inclined surface of the sidewall <NUM>. Details of the conductive contact pattern 150PB may substantially be the same as those of the conductive contact pattern 150P described with reference to <FIG>, <FIG>, and <FIG>.

<FIG> is a cross-sectional view of a semiconductor device 100C according to embodiments. <FIG> illustrates a cross-sectional configuration of a portion corresponding to a cross-section taken along line A-A' of <FIG> in the semiconductor device 100C. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG> and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG>, the semiconductor device 100C may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG> and <FIG> to 2C. However, the semiconductor device 100C may include a pair of channel structures CSA and CSB, which are spaced apart from each other in a first lateral direction (X direction) and/or in a second lateral direction (Y direction), instead of the channel structure CS1.

The pair of channel structures CSA and CSB may each have an L-shaped vertical cross-sectional shape. The pair of channel structures CSA and CSB may each include a vertical channel portion VC and a lateral channel portion HC in contact with a top surface of the bit line BL. The pair of channel structures CSA and CSB may each include a main channel portion <NUM> and a channel contact portion <NUM> on an uppermost surface of the main channel portion <NUM>. In each of the pair of channel structures CSA and CSB, a portion of the vertical channel portion VC and the lateral channel portion HC may include the main channel portion <NUM>.

The lateral channel portions HC of the pair of channel structures CSA and CSB may be spaced apart from each other with the lower insulating partition wall 142A therebetween in the second lateral direction (Y direction). The lower insulating partition wall 142A may be in contact with the top surface of the bit line BL. Details of the pair of channel structures CSA and CSB and the lower insulating partition wall 142A may substantially be the same as those of the channel structure CS1 and the lower insulating partition wall <NUM>, which have been described with reference to <FIG> and <FIG>.

<FIG> is a cross-sectional view of a semiconductor device <NUM> according to embodiments. <FIG> illustrates an enlarged cross-sectional configuration of a portion corresponding to portion "EX1" of <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG> and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG>, the semiconductor device <NUM> may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG> and <FIG> to 2C. However, the semiconductor device <NUM> may include a channel structure CS2 between a gate dielectric film <NUM> and a mold insulating pattern <NUM>. The channel structure CS2 may include a main channel portion <NUM> and a channel contact portion <NUM> on an uppermost surface of the main channel portion <NUM>. In the channel structure CS2, the main channel portion <NUM> may include a first oxide semiconductor material, and the channel contact portion <NUM> may include a second oxide semiconductor material having a different composition from the first oxide semiconductor material. In embodiments, the main channel portion <NUM> may include IGZO, and the channel contact portion <NUM> may include IAZO, without being limited thereto.

In the semiconductor device <NUM>, the gate dielectric film <NUM> may not include a dielectric film barrier liner 130W. The mold insulating pattern <NUM> may not include a mold barrier liner 110W.

<FIG> is a cross-sectional view of a semiconductor device 200A according to embodiments. <FIG> illustrates an enlarged cross-sectional configuration of a portion corresponding to portion "EX1" of <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG> and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG>, the semiconductor device 200A may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG>. However, the semiconductor device 200A may include a channel structure CS2A and a conductive contact pattern 250PA connected to the channel structure CS2A.

The channel structure CS2A may include a main channel portion <NUM> and a channel contact portion 222A on an uppermost surface of the main channel portion <NUM>. The conductive contact pattern 250PA may be in contact with the channel contact portion 222A, and the main channel portion <NUM> may be spaced apart from the conductive contact pattern 250PA with the channel contact portion 222A therebetween.

The conductive contact pattern 250PA may include a lower contact portion 250LA and an upper pad portion 150U. The lower contact portion 250LA may be between a gate dielectric film <NUM> and a mold insulating pattern <NUM>. The upper pad portion 150U may be on the lower contact portion 250LA and integrally connected to the lower contact portion 250LA.

The mold insulating pattern <NUM> may have a sidewall <NUM> in contact with the conductive contact pattern 250PA, and the sidewall <NUM> may include an inclined surface such that a distance between the sidewall <NUM> of the mold insulating pattern <NUM> and the gate dielectric film <NUM> gradually increases in a direction away from the substrate (refer to <NUM> in <FIG>). The lower contact portion 250LA of the conductive contact pattern 250PA may have a contact surface facing the sidewall <NUM> of the mold insulating pattern <NUM>, and the contact surface may include an inclined surface having a shape corresponding to the inclined surface of the sidewall <NUM>.

Because the sidewall <NUM> of the mold insulating pattern <NUM> includes the inclined surface, when the conductive contact pattern 250PA is formed in the process of manufacturing the semiconductor device 200A, excellent gap-fill characteristics may be provided during a deposition process for filling a relatively narrow space between the gate dielectric film <NUM> and the mold insulating pattern <NUM> with a conductive material.

The channel contact portion 222A of the channel structure CS2A may have a channel surface 222AS facing the sidewall <NUM> of the mold insulating pattern <NUM>, and the channel surface 222AS may include an inclined surface having a shape corresponding to the inclined surface of the sidewall <NUM>.

Details of the conductive contact pattern 250PA and the channel structure CS2A may substantially be the same as those of the conductive contact pattern 150P and the channel structure CS1, which have been described with reference to <FIG> and <FIG>.

<FIG> is a cross-sectional view of a semiconductor device <NUM> according to embodiments, and <FIG> is an enlarged cross-sectional view of portion "EX3" of <FIG> illustrates a cross-sectional configuration of a portion corresponding to the cross-section taken along line A-A' of <FIG> in the semiconductor device <NUM>. In <FIG> and <FIG>, the same reference numerals are used to denote the same elements as in <FIG> and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG> and <FIG>, the semiconductor device <NUM> may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG> and <FIG>. However, the semiconductor device <NUM> may include a mold insulating pattern <NUM>, a channel structure CS3 in contact with a sidewall of the mold insulating pattern <NUM>, and a plurality of conductive contact patterns 350P connected to the channel structure CS3. The plurality of conductive contact patterns 350P may be insulated from each other by an isolation insulating film <NUM>. The isolation insulating film <NUM> may substantially have the same configuration as the isolation insulating film <NUM> described with reference to <FIG>.

The mold insulating pattern <NUM> may include a first mold insulating pattern <NUM> and a second mold insulating pattern <NUM>, which include different materials from each other. The first mold insulating pattern <NUM> and the second mold insulating pattern <NUM> may have different etch selectivities with respect to a predetermined etchant. In embodiments, the first mold insulating pattern <NUM> may include a silicon oxide film, and the second mold insulating pattern <NUM> may include a silicon nitride film, without being limited thereto.

In the mold insulating pattern <NUM>, an uppermost surface of the first mold insulating pattern <NUM> may be at a lower vertical level than an uppermost surface of the channel structure CS3, and an uppermost surface of the second mold insulating pattern <NUM> may be at a higher vertical level than the uppermost surface of the channel structure CS3. As used herein, the term "vertical level" may refer to a vertical distance from a substrate (refer to <NUM> in <FIG>). As used herein, a high(er) vertical level may refer to a relatively great vertical distance from the substrate <NUM>.

The conductive contact pattern 350P may include a lower contact portion <NUM> and an upper pad portion 350U. The lower contact portion <NUM> may be between a gate dielectric film <NUM> and the mold insulating pattern <NUM>. The upper pad portion 350U may be on the lower contact portion <NUM> and integrally connected to the lower contact portion <NUM>.

The channel structure CS3 may include a main channel portion <NUM> and a channel contact portion <NUM> on an uppermost surface of the main channel portion <NUM>. Details of the channel contact portion <NUM> may substantially be the same as those of the channel contact portion <NUM>, which has been described with reference to <FIG> and <FIG>.

The lower contact portion <NUM> of the conductive contact pattern 350P may have a sidewall facing the gate dielectric film <NUM>, surfaces in contact with a top surface and a sidewall of the channel contact portion <NUM>, a surface in contact with an uppermost surface of the first mold insulating pattern <NUM>, and a surface in contact with a sidewall of the second mold insulating pattern <NUM>. The lower contact portion <NUM> of the conductive contact pattern 350P may include a portion between the sidewall of the channel contact portion <NUM> and the sidewall of the second mold insulating pattern <NUM> included in the mold insulating pattern <NUM>.

The first mold insulating pattern <NUM> of the mold insulating pattern <NUM> may include a mold barrier liner 312W in contact with the conductive contact pattern 350P, and the second mold insulating pattern <NUM> of the mold insulating pattern <NUM> may include a mold barrier liner 314W in contact with the conductive contact pattern 350P. Also, the gate dielectric film <NUM> may include a dielectric film barrier liner 130W in contact with the conductive contact pattern 350P. The mold barrier liner 312W may include the same elements as those of the first mold insulating pattern <NUM> and further includes at least one dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H). The mold barrier liner 314W may include the same elements as those of the second mold insulating pattern <NUM> and further includes at least one dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H).

Details of the mold insulating pattern <NUM>, the channel structure CS3, and the conductive contact pattern 350P may substantially be the same as those of the mold insulating pattern <NUM>, the channel structure CS1, and the conductive contact pattern 150P, which have been described with reference to <FIG> and <FIG>.

<FIG> is a cross-sectional view of a semiconductor device 300A according to embodiments. <FIG> illustrates an enlarged cross-sectional configuration of a portion corresponding to portion "EX3" of <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG>, <FIG>, <FIG>, and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG>, the semiconductor device 300A may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG> and <FIG>. However, the semiconductor device 300A may include a conductive contact pattern 350PA. The conductive contact pattern 350PA may be insulated from conductors adjacent thereto by an isolation insulating film <NUM>. The conductive contact pattern 350PA may include a lower contact portion 350LA and an upper pad portion 350U. The lower contact portion 350LA may be between the gate dielectric film <NUM> and the mold insulating pattern <NUM>. The upper pad portion 350U may be on the lower contact portion 350LA and integrally connected to the lower contact portion 350LA.

The second mold insulating pattern <NUM> included in the mold insulating pattern <NUM> may have a sidewall <NUM> in contact with the conductive contact pattern 350PA, and the sidewall <NUM> may include an inclined surface such that a distance between the sidewall <NUM> of the second mold insulating pattern <NUM> and the gate dielectric film <NUM> gradually increases in a direction away from the substrate (refer to <NUM> in <FIG>). The mold barrier liner 314W included in the second mold insulating pattern <NUM> may extend along the inclined surface of the sidewall <NUM>.

The lower contact portion 350LA of the conductive contact pattern 350PA may have a contact surface facing the inclined surface of the sidewall <NUM>, and the contact surface may include an inclined surface having a shape corresponding to the inclined surface of the sidewall <NUM>. Details of the conductive contact pattern 350PA may substantially be the same as those of the conductive contact pattern 350P, which has been described with reference to <FIG> and <FIG>.

<FIG> is a cross-sectional view of a semiconductor device <NUM> according to embodiments, and <FIG> is an enlarged cross-sectional view of portion "EX4" of <FIG> illustrates a cross-sectional configuration of a portion corresponding to the cross-section taken along line A-A' of <FIG> in the semiconductor device <NUM>. In <FIG> and <FIG>, the same reference numerals are used to denote the same elements as in <FIG>, <FIG>, <FIG>, and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG> and <FIG>, the semiconductor device <NUM> may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG> and <FIG>. However, the semiconductor device <NUM> may include a channel structure CS4 in contact with a sidewall of a mold insulating pattern <NUM> and a plurality of conductive contact patterns 450P connected to the channel structure CS4. The plurality of conductive contact patterns 450P may be insulated from each other by an isolation insulating film <NUM>.

In the semiconductor device <NUM>, a gate dielectric film <NUM> may not include the dielectric film barrier liner 130W shown in <FIG> and <FIG>. The mold insulating pattern <NUM> may not include the mold barrier liners 312W and 314W shown in <FIG> and <FIG>.

In the mold insulating pattern <NUM>, an uppermost surface of a first mold insulating pattern <NUM> may be at a lower vertical level than an uppermost surface of the channel structure CS4, and an uppermost surface of a second mold insulating pattern <NUM> may be at a higher vertical level than the uppermost surface of the channel structure CS4.

The conductive contact pattern 450P may include a lower contact portion <NUM> and an upper pad portion 450U. The lower contact portion <NUM> may be between the gate dielectric film <NUM> and the mold insulating pattern <NUM>. The upper pad portion 450U may be on the lower contact portion <NUM> and integrally connected to the lower contact portion <NUM>.

The channel structure CS4 may include a main channel portion <NUM> and a channel contact portion <NUM> on an uppermost surface of the main channel portion <NUM>. Details of the channel contact portion <NUM> may substantially be the same as that of the channel contact portion <NUM>, which has been described with reference to <FIG> and <FIG>.

The lower contact portion <NUM> of the conductive contact pattern 450P may include a sidewall facing the gate dielectric film <NUM>, a sidewall facing the mold insulating pattern <NUM>, surfaces in contact with a top surface and a sidewall of the channel contact portion <NUM>, and an uppermost surface of the first mold insulating pattern <NUM>. The lower contact portion <NUM> of the conductive contact pattern 450P may include a portion between the sidewall of the channel contact portion <NUM> and a sidewall of the second mold insulating pattern <NUM> included in the mold insulating pattern <NUM>.

<FIG> is a cross-sectional view of a semiconductor device 400A according to embodiments. <FIG> illustrates an enlarged cross-sectional configuration of a portion corresponding to portion "EX4" of <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG>, <FIG>, <FIG>, and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG>, the semiconductor device 400A may substantially have the same configuration as the semiconductor device <NUM> described with reference to <FIG> and <FIG>. However, the semiconductor device 400A may include a conductive contact pattern 450PA connected to a channel structure CS4. The conductive contact pattern 450PA may be insulated from conductors adjacent thereto by an isolation insulating film <NUM>.

The conductive contact pattern 450PA may be in contact with a channel contact portion <NUM> of the channel structure CS4, and the main channel portion <NUM> may be spaced apart from the conductive contact pattern 450PA with the channel contact portion <NUM> therebetween.

The conductive contact pattern 450PA may include a portion between a sidewall of a gate dielectric film <NUM> and a sidewall of a second mold insulating pattern <NUM> of a mold insulating pattern <NUM>.

The second mold insulating pattern <NUM> of the mold insulating pattern <NUM> may have a sidewall <NUM> in contact with the conductive contact pattern 450PA, and the sidewall <NUM> may include an inclined surface such that a distance between the sidewall <NUM> of the second mold insulating pattern <NUM> and the gate dielectric film <NUM> gradually increases in a direction away from the substrate (refer to <NUM> in <FIG>). The lower contact portion 450LA of the conductive contact pattern 450PA may have a contact surface facing the sidewall <NUM> of the second mold insulating pattern <NUM>, and the contact surface may include an inclined surface having a shape corresponding to the inclined surface of the sidewall <NUM>.

The semiconductor devices <NUM>, 100A, 100B, 100C, <NUM>, 200A, <NUM>, 300A, <NUM>, and 400A described with reference to <FIG> may include the channel structures CS1, CSA, CSB, CS1A, CS2, CS2A, CS3, and CS4, which adopt an oxide semiconductor material. In the channel structures CS1, CSA, CSB, CS1A, CS2, CS2A, CS3, and CS4, the channel contact portions <NUM>, 122A, <NUM>, 222A, <NUM>, and <NUM> in contact with the conductive contact patterns 150P, 150PB, 250PA, 350P, 350PA, 450P, and 450PA may have different compositions from the main channel portions <NUM> and 120A of the channel structures CS1, CSA, CSB, CS1A, CS2, CS2A, CS3, and CS4. In embodiments, the channel contact portions <NUM>, 122A, <NUM>, 222A, <NUM>, and <NUM> may include the same elements as those of an oxide semiconductor layer included in the main channel portions <NUM> and 120A, and further include at least one dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H). Accordingly, because oxygen atoms included in the channel contact portions <NUM>, 122A, <NUM>, 222A, <NUM>, and <NUM> are bonded with other elements included in the channel contact portions <NUM>, 122A, <NUM>, 222A, <NUM>, and <NUM> with relatively high bond dissociation energy, the oxygen atoms included in the channel contact portions <NUM>, 122A, <NUM>, 222A, <NUM>, and <NUM> may be inhibited from reacting with metal atoms included in the conductive contact patterns 150P, 150PB, 250PA, 350P, 350PA, 450P, and 450PA to form a metal oxide. As a result, contact resistance between the channel structures CS1, CSA, CSB, CS1A, CS2, CS2A, CS3, and CS4 and the conductive contact patterns 150P, 150PB, 250PA, 350P, 350PA, 450P, and 450PA may be reduced. That is, an interface between the channel contact portions and the conductive contact patterns may have a lower contact resistance than an interface between the main channel portions and the conductive contact patterns.

Furthermore, the conductive contact patterns 150PB, 250PA, 350PA, and 450PA, which are in contact with the sidewalls <NUM> and <NUM> including the inclined surfaces, may be provided as in the semiconductor devices 100B, 200A, 300A, and 400A shown in <FIG>, <FIG>, <FIG>, and <FIG>. Alternatively, as shown in <FIG>, the conductive contact patterns 350P, 350PA, 450P, and 450PA, which are in contact with the top surfaces and the sidewalls of the channel contact portions <NUM> and <NUM> included in the channel structures CS3 and CS4 and are between the sidewalls of the channel contact portions <NUM> and <NUM> and the sidewall of the mold insulating pattern <NUM>, may be provided. Thus, an increased contact area may be ensured between a channel structure and a conductive contact pattern. Therefore, the reliability of semiconductor devices may be improved.

Next, a specific example of a method of manufacturing a semiconductor device, according to embodiments, will be described.

<FIG> are diagrams of a process sequence of a method of manufacturing a semiconductor device, according to embodiments. More specifically, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are plan layout diagrams of some components, which illustrate a process sequence of the method of manufacturing the semiconductor device. <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are cross-sectional views taken along lines A-A' of <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, respectively. <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are cross-sectional views taken along lines B-B' of <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, respectively. <FIG>, <FIG>, <FIG>, and <FIG> are cross-sectional views of a region corresponding to the cross-section taken along line A - A' of <FIG>, according to the process sequence. <FIG>, <FIG>, <FIG>, and <FIG> are respectively enlarged cross-sectional views of portions "EX1" of <FIG>, <FIG>, <FIG>, and <FIG>. An example of a method of manufacturing the semiconductor device <NUM> shown in <FIG> and <FIG> will be described with reference to <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG> and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG>, <FIG>, and <FIG>, a plurality of core circuits <NUM> and a plurality of peripheral circuits including a plurality of conductive plugs (e.g., P1, P2, and P3) and a plurality of wiring layers (e.g., M1 and M2) may be formed on a substrate <NUM>. Thus, a peripheral circuit structure PCA may be formed on the substrate <NUM>. Thereafter, a plurality of shielding structures SL and a plurality of bit lines BL may be formed on the peripheral circuit structure PCA. The plurality of shielding structures SL may pass through an interlayer insulating film 106F, and the plurality of bit lines BL may pass through the interlayer insulating film 106F and an interlayer insulating film <NUM>.

Referring to <FIG>, <FIG>, and <FIG>, a mold insulating pattern <NUM> having a plurality of openings <NUM> may be formed on the resultant structure of <FIG>, <FIG>, and <FIG> in which the plurality of bit lines BL are formed. Partial regions of the plurality of bit lines BL may be respectively exposed through the plurality of openings <NUM>. Each of the plurality of openings <NUM> formed in the mold insulating pattern <NUM> may provide a transistor region TRR.

Referring to <FIG>, <FIG>, and <FIG>, a channel layer <NUM> may be formed to conformally cover surfaces exposed at the plurality of openings <NUM> formed in the mold insulating pattern <NUM>. The channel layer <NUM> may include an oxide semiconductor layer. The oxide semiconductor layer may include IGZO, Sn-IGZO, IWO, IZO, ZTO, ZnO, YZO, IGSO, InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, or a combination thereof. For example, the channel layer <NUM> may include IGZO.

In embodiments, the channel layer <NUM> may be formed by using at least one of a chemical vapor deposition (CVD) process, a low-pressure CVD (LPCVD) process, a plasma-enhanced CVD (PECVD) process, a metal-organic CVD (MOCVD) process, and an atomic layer deposition (ALD) process. In embodiments, the channel layer <NUM> may be formed to a thickness of about <NUM> to about <NUM>, without being limited thereto.

Referring to <FIG>, <FIG>, and <FIG>, a sacrificial pattern SM1 covering the channel layer <NUM> may be formed in the resultant structure of <FIG>, <FIG>, and <FIG>, and the channel layer <NUM> may be etched by using the sacrificial pattern SM1 as an etch mask. Thus, the channel layer <NUM> may be divided into a plurality of main channel portions <NUM>. The interlayer insulating film <NUM> may be exposed between every two adjacent ones of the plurality of main channel portions <NUM> inside the plurality of openings <NUM>.

Referring to <FIG>, <FIG>, and <FIG>, the sacrificial pattern SM1 may be removed from the resultant structure of <FIG>, <FIG>, and <FIG> to expose a top surface of each of the plurality of main channel portions <NUM>. Thereafter, a plurality of gate dielectric films <NUM> and a plurality of word lines WL may be formed to sequentially cover the plurality of main channel portions <NUM> inside the mold insulating pattern <NUM>.

In embodiments, to form the plurality of gate dielectric films <NUM> and the plurality of word lines WL, after the top surface of each of the plurality of main channel portions <NUM> is exposed, the gate dielectric film <NUM> may be firstly formed to conformally cover the respective exposed surfaces of the plurality of main channel portions <NUM> and the interlayer insulating film <NUM>. Thereafter, the plurality of word lines WL may be formed on the gate dielectric film <NUM>. In a patterning process for forming the plurality of word lines WL, a portion of the gate dielectric film <NUM> between two word lines WL inside the opening <NUM> may be removed. The top surface of the main channel portion <NUM> may be exposed between the two word lines WL located inside the opening <NUM>.

Subsequently, a lower insulating partition wall <NUM> may be formed to fill a space between the two word lines WL inside the opening <NUM>, and an upper insulating partition wall <NUM> may be formed to cover a top surface of each of the two word lines WL and the lower insulating partition wall <NUM> inside the opening <NUM>. Respective top surfaces of the upper insulating partition wall <NUM>, the gate dielectric film <NUM>, and the mold insulating pattern <NUM> may form one planar surface.

Referring to <FIG> and <FIG>, portions may be removed from the respective top surfaces of the plurality of main channel portions <NUM>, which are exposed in the resultant structure of <FIG>, <FIG>, and 15Ca, and thus, heights of the plurality of main channel portions <NUM> may be reduced. As a result, a plurality of contact spaces CTH, which are defined by a sidewall of the gate dielectric film <NUM> and a sidewall of the mold insulating pattern <NUM>, may be formed on the plurality of main channel portions <NUM>. The process of removing the portions from the respective top surfaces of the plurality of main channel portions <NUM> may be performed by using a wet process, a dry process, or a combination thereof.

Referring to <FIG> and <FIG>, in the resultant structure of <FIG> and <FIG>, an ion implantation process of implanting a dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H) may be performed on the plurality of main channel portions <NUM> through the plurality of contact spaces CTH. As a result, a composition of a partial upper region of each of the plurality of main channel portions <NUM> may be changed, and thus, a channel contact portion <NUM> including an oxide semiconductor layer including the dopant may be formed.

During the formation of the channel contact portion <NUM>, the dopant may be implanted into an exposed sidewall of the gate dielectric film <NUM> and an exposed sidewall of the mold insulating pattern <NUM>. Thus, a dielectric film barrier liner 130W may be formed on the exposed sidewall of the gate dielectric film <NUM>, and a mold barrier liner 110W may be formed on the exposed sidewall of the mold insulating pattern <NUM>.

Referring to <FIG> and <FIG>, in the resultant structure of <FIG> and <FIG>, a conductive layer <NUM> may be formed to fill the plurality of contact spaces CTH and cover the top surface of each of the mold insulating pattern <NUM>, the gate dielectric film <NUM>, and the upper insulating partition wall <NUM>. The conductive layer <NUM> may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, or a combination thereof. For example, the conductive layer <NUM> may have a stack structure of a conductive barrier film including TiN and a conductive film including W.

Referring to <FIG> and <FIG>, in the resultant structure of <FIG> and <FIG>, partial regions of the conductive layer <NUM> may be etched to form an isolation space exposing the upper insulating partition wall <NUM>, and a plurality of conductive contact patterns 150P may be formed from the conductive layer <NUM>. Thereafter, an isolation insulating film <NUM> may be formed to fill the isolation space.

Afterwards, as shown in <FIG> and <FIG>, an etch stop film <NUM> and an interlayer insulating film <NUM> may be formed on the resultant structure including the plurality of conductive contact patterns 150P. A plurality of capacitor structures CAP may be formed to pass through the etch stop film <NUM> and the interlayer insulating film <NUM> and be connected to the plurality of conductive contact patterns 150P.

Although an example of the method of manufacturing the semiconductor device <NUM> shown in <FIG> and <FIG> has been described with reference to <FIG>, it will be understood that semiconductor devices having various structures may be manufactured by making various modifications and changes within the scope of the inventive concept.

For example, to manufacture the semiconductor device 100A shown in <FIG>, in the process described with reference to <FIG> and <FIG>, a portion may be removed from the top surface of each of the main channel portions <NUM> may be removed by using a wet etching process, and thus, a concave top surface T2 may be formed in the main channel portion <NUM>. Afterwards, in a similar manner to that described with reference to <FIG> and <FIG>, a dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H) may be implanted from the concave top surface T2 of the main channel portion <NUM> into the main channel portion <NUM>. Thus, as shown in <FIG>, a main channel portion 120A having a concave top surface T1 and a channel contact portion 122A having the contact top surface T2 may be formed from the main channel portion <NUM>.

To manufacture the semiconductor device 100B shown in <FIG>, while a portion is being removed from the top surface of each of the main channel portions <NUM> as described with reference to <FIG> and <FIG>, a portion of the mold insulating pattern <NUM> may be etched together with the main channel portion <NUM> by controlling an etching atmosphere (e.g., a change in the composition of an etchant or an etching gas). Thus, a sidewall <NUM> including an inclined surface may be formed on the mold insulating pattern <NUM>. Thereafter, while a dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H) is being implanted into the main channel portion <NUM> in a similar manner to that described with reference to <FIG> and <FIG>, a mold barrier liner 110W, which extends slantwise along the sidewall <NUM>, may be formed.

To manufacture the semiconductor device 100C shown in <FIG>, the sacrificial pattern SM1 may be removed from the resultant structure of <FIG>, <FIG>, and <FIG> to expose the top surface of each of the plurality of main channel portions <NUM>. Thereafter, similarly to the descriptions of <FIG>, <FIG>, and <FIG>, a gate dielectric film <NUM> may be firstly formed to conformally cover the exposed surface of each of the plurality of main channel portions <NUM> and the interlayer insulating film <NUM>, and a plurality of word lines WL may be then formed on the gate dielectric film <NUM>. In the process of patterning the plurality of word lines WL, a portion of the gate dielectric film <NUM> between the two word lines WL inside the opening <NUM> may be removed, and thus, the top surface of the main channel portion <NUM> may be exposed between the two word lines WL inside the opening <NUM>. Thereafter, the main channel portion <NUM> exposed inside the opening <NUM> may be etched to divide the main channel portion <NUM> into two portions and expose a top surface of the bit line BL. Subsequently, a lower insulating partition wall 142A may be formed to fill a space between the two word lines WL located inside the opening <NUM> and a space between the two main channel portions <NUM>, and an upper insulating partition wall <NUM> may be formed to cover a top surface of the two word lines WL and the lower insulating partition wall 142A inside the opening <NUM>.

To manufacture the semiconductor device <NUM> shown in <FIG>, a portion may be removed from the top surface of each of the main channel portions <NUM> in a similar manner to that described with reference to <FIG> and <FIG>. Afterwards, the dopant implantation process described with reference to <FIG> and <FIG> may be omitted, and a channel contact portion <NUM> may be formed on the main channel portion <NUM> in the contact space (refer to CTH in <FIG> and <FIG>) before a process of forming the conductive layer <NUM> is performed as described with reference to <FIG> and <FIG>. In embodiments, to form the channel contact portion <NUM>, a second oxide semiconductor material having a different composition from a first oxide semiconductor material included in the main channel portion <NUM> may be deposited on the main channel portion <NUM> exposed in the contact space CTH. Thereafter, a portion of a deposition film including the second oxide semiconductor material may be removed by using an etchback process, and thus, the channel contact portion <NUM> may remain on the main channel portion <NUM>.

To manufacture the semiconductor device 200A shown in <FIG>, a method similar to the above-described method of manufacturing the semiconductor device 100B shown in <FIG> may be used. However, while each of the main channel portions <NUM> is partially removed from the top surface thereof in a similar manner to that described with reference to <FIG> and <FIG>, a sidewall <NUM> including an inclined surface may be formed on the mold insulating pattern <NUM>. The ion implantation process described with reference to <FIG> and <FIG> may be omitted, and a channel contact portion 222A may be formed on the main channel portion <NUM> inside the contact space (refer to CTH in <FIG> and <FIG>) before performing the process of forming the conductive layer <NUM> as described with reference to <FIG> and <FIG>. To form the channel contact portion 222A, processes similar to the above-described process of forming the channel contact portion <NUM> shown in <FIG> may be performed.

<FIG> are diagrams of a process sequence of a method of manufacturing a semiconductor device, according to embodiments. More specifically, <FIG> is a plan layout diagram of the method of manufacturing the semiconductor device. <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> are cross-sectional views of a region corresponding to the cross-section taken along line A - A' of <FIG>, according to the process sequence; <FIG>, <FIG>, <FIG>, and <FIG> are respectively enlarged cross-sectional views of portions "EX3" of <FIG>, <FIG>, <FIG>, and <FIG>. An example of a method of manufacturing the semiconductor device <NUM> shown in <FIG> and <FIG> will be described with reference to <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG>, <FIG>, <FIG>, and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG> and <FIG>, a peripheral circuit structure PCA, a plurality of shielding structures SL, and the plurality of bit lines BL may be formed on a substrate <NUM> in the same manner as described with reference to <FIG>, <FIG>, and <FIG>. Thereafter, a mold insulating pattern <NUM> having a plurality of openings <NUM> may be formed in a similar manner to the process of forming the mold insulating pattern <NUM>, which has been described with reference to <FIG>, <FIG>, and <FIG>. The mold insulating pattern <NUM> may be formed to include a first mold insulating pattern <NUM> and a second mold insulating pattern <NUM>, which include different materials from each other.

Referring to <FIG> and <FIG>, in a similar manner to that described with reference to <FIG>, a main channel portion <NUM>, a plurality of gate dielectric films <NUM>, a plurality of word lines WL, a lower insulating partition wall <NUM>, and an upper insulating partition wall <NUM> may be formed inside the opening <NUM> of the mold insulating pattern <NUM> in the resultant structure of <FIG> and <FIG>.

Referring to <FIG> and <FIG>, a portion may be removed by etching from a top surface of the main channel portion <NUM> in a similar manner to that described with reference to <FIG> and <FIG>. Thus, a height of the main channel portion <NUM> may be removed, and a contact space CTH3 may be formed on the main channel portion <NUM>. In this case, by controlling etching conditions of the main channel portion <NUM>, the first mold insulating pattern <NUM> of the mold insulating pattern <NUM> may be partially etched from a top surface thereof during the etching of the main channel portion <NUM>. As a result, in the contact space CTH3 prepared on the main channel portion <NUM>, the top surface and a sidewall of the main channel portion <NUM>, the sidewall of the gate dielectric film <NUM>, and a sidewall of the second mold insulating pattern <NUM> may be exposed.

Referring to <FIG> and <FIG>, in a similar manner to that described with reference to <FIG> and <FIG>, in the resultant structure of <FIG> and <FIG>, an ion implantation process of implanting a dopant selected from aluminum (Al), boron (B), arsenic (As), fluorine (F), and hydrogen (H) may be performed on the main channel portion <NUM> through the contact space CTH3. As a result, a composition of an upper partial region of each of the plurality of main channel portions <NUM> may be changed, and thus, a channel contact portion <NUM> including an oxide semiconductor layer including a dopant may be formed.

During the formation of the channel contact portion <NUM>, the dopant may also be implanted into the exposed sidewall of the gate dielectric film <NUM> and the exposed surface of the mold insulating pattern <NUM>. Thus, a dielectric film barrier liner 130W may be formed on the exposed sidewall of the gate dielectric film <NUM>, a mold barrier liner 312W may be formed on a top surface of the first mold insulating pattern <NUM>, and a mold barrier liner 314W may be formed on the sidewall of the second mold insulating pattern <NUM>.

Referring to <FIG> and <FIG>, in a similar manner to the process of forming the plurality of conductive contact patterns 150P and an isolation insulating film <NUM> as described with reference to <FIG>, a plurality of conductive contact patterns 350P and an isolation insulating film <NUM> may be formed on the resultant structure of <FIG> and <FIG>.

<FIG> are diagrams of a process sequence of a method of manufacturing a semiconductor device, according to embodiments. More specifically, <FIG> and <FIG> are cross-sectional views of a region corresponding to the cross-section taken along line A - A' of <FIG>, according to the process sequence. <FIG> and <FIG> are respectively enlarged cross-sectional views of portions "EX4" of <FIG> and <FIG>. An example of a method of manufacturing the semiconductor device <NUM> shown in <FIG> and <FIG> will be described with reference to <FIG>. In <FIG>, the same reference numerals are used to denote the same elements as in <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, and repeated descriptions thereof are omitted here.

Referring to <FIG> and <FIG>, after the processes described with reference to <FIG> are formed, a portion of a main channel portion <NUM> may be removed from the resultant structure of <FIG> and <FIG>. Thus, a height of the main channel portion <NUM> may be reduced, and a contact space (not shown) may be formed on the main channel portion <NUM>. Thereafter, a channel contact portion <NUM> may be formed in the contact space. The channel contact portion <NUM> may be formed by using a CVD process or an ALD process.

Referring to <FIG> and <FIG>, the channel contact portion <NUM> may be partially removed from a top surface thereof in the resultant structure of <FIG> and <FIG>, and thus, a height of the channel contact portion <NUM> may be reduced. In this case, in a manner to the process of etching the main channel portion <NUM> as described with reference to <FIG>, the channel contact portion <NUM> may be partially removed by etching from the top surface thereof, and thus, a height of the channel contact portion <NUM> may be reduced, and a contact space CTH4 may be formed on the channel contact portion <NUM>. While a portion the channel contact portion <NUM> is being etched, a first mold insulating pattern <NUM> of a mold insulating pattern <NUM> may also be partially etched from a top surface thereof by controlling etching conditions. As a result, in the contact space CTH4 prepared on the channel contact portion <NUM>, the top surface and a sidewall of the channel contact portion <NUM>, a sidewall of a gate dielectric film <NUM>, and a sidewall of a second mold insulating pattern <NUM> may be exposed.

Thereafter, the semiconductor device <NUM> shown in <FIG> and <FIG> may be manufactured by performing the processes described with reference to <FIG> and <FIG>.

Although examples of the methods of manufacturing the semiconductor device <NUM> shown in <FIG> and <FIG> and the semiconductor device <NUM> shown in <FIG> and <FIG> has been described with reference to <FIG>, it will be understood that the semiconductor devices 300A and 400A shown in <FIG> and <FIG> and semiconductor devices having variously changed structures may be manufactured by applying various modifications and changes to the processes described with reference to <FIG> within the scope of the inventive concept.

Claim 1:
A semiconductor device (<NUM>) comprising:
an upper conductive line (WL) on a substrate (<NUM>);
a channel structure (CS1) adjacent the upper conductive line (WL);
a gate dielectric film (<NUM>) between the channel structure (CS1) and the upper conductive line (WL); and
a conductive contact pattern (150P) electrically connected to the channel structure (CS1),
wherein the channel structure (CS1) comprises:
a main channel portion (<NUM>) comprising an oxide semiconductor layer having a first composition; and
a channel contact portion (<NUM>) between the main channel portion (<NUM>) and the conductive contact pattern (150P), wherein the channel contact portion (<NUM>) is in contact with the conductive contact pattern (150P) and comprises a material having a second composition that is different from the first composition, wherein the channel contact portion (<NUM>) and the oxide semiconductor layer respectively comprise one or more same elements, and the channel contact portion (<NUM>) further comprises at least one dopant, wherein the at least one dopant comprises aluminum (Al), boron (B), arsenic (As), fluorine (F), or hydrogen (H).