Patent Description:
A resistive random-access memory device provides one category of embedded non-volatile memory technology. A bitcell of a resistive random-access memory device typically includes a resistive memory element and an access transistor that controls operations used to write, erase, and read the resistive memory element. Because resistive memory elements are non-volatile, bits of data are retained as stored content by the resistive memory elements when the resistive random-access memory device is unpowered. The non-volatility of a resistive random-access memory device contrasts with volatile memory technologies, such as a static random-access memory device in which the stored content is eventually lost when unpowered and a dynamic random-access memory device in which the stored content is lost unless periodically refreshed.

A resistive memory element includes a switching layer that is positioned in a layer stack between a bottom electrode and a top electrode. The resistive memory element can be programmed by changing the resistance across the switching layer to provide different content-storage conditions, namely a high-resistance state and a low-resistance state, representing the stored bits of data. The switching layer can be modified by applying a programming voltage across the bottom and top electrodes that is sufficient to create one or more conductive filaments bridging across the thickness of the switching layer, which sets the low-resistance state. The conductive filaments can be destroyed, also by the application of a programming voltage, to reset the resistive memory element to the high-resistance state. The content-storage condition can be read by measuring a voltage drop across the resistive memory element after it has been programmed. Resistive random-access memory devices are known from <CIT>, <CIT>, <CIT> and from the publication "<NPL>. Further, magnetoresistive random access memory (MRAM) devices including a magnetic tunnel junction (MTJ) are known from <CIT>. Further, <CIT> describes a resistive memory cell comprising a resistive transition metal oxide layer between an upper electrode and a lower electrode. The upper electrode comprises an upper metal layer and an upper metallic barrier layer, and the lower electrode comprises a lower metallic barrier layer, a lower metal layer and a transition metal compound layer.

Improved structures including a layer stack for a resistive memory element and methods of forming a structure that includes a layer stack for a resistive memory element are needed.

According to an embodiment of the invention, a structure for a random-access resistive memory device is provided. The structure comprises a resistive memory element including a first electrode, a second electrode, and a switching layer disposed between the second electrode and the first electrode. The first electrode includes a first layer and a second layer between the first layer and the switching layer. The switching layer has a first thickness, and the second layer of the first electrode has a second thickness that is less than the first thickness of the switching layer. The second electrode includes a first layer and a second layer, wherein the second layer of the second electrode is between the first layer of the second electrode and the switching layer, and the first layer of the second electrode comprises a metal nitride or tantalum nitride and is disposed on a first portion of the second layer of the second electrode. The structure further comprises a plurality of spacers disposed on respective second portions of the second layer of the second electrode, wherein the plurality of spacers comprise the metal nitride and oxygen or tantalum oxynitride. Additional features of the structure are set forth in dependent claims <NUM> to <NUM>.

According to another embodiment of the invention, a method of forming a structure for a random-access resistive memory device is provided. The method comprises forming a resistive memory element including a first electrode, a second electrode, and a switching layer between the second electrode and the first electrode. The first electrode includes a first layer and a second layer disposed between the first layer and the switching layer. The switching layer has a first thickness, and the second layer of the first electrode has a second thickness that is less than the first thickness of the switching layer. The second electrode includes a first layer and a second layer, wherein the second layer of the second electrode is between the first layer of the second electrode and the switching layer. The forming of the resistive memory element comprises patterning the layers with a reactive ion etching process to form the first layer of the second electrode on a first portion of the second layer of the second electrode and a plurality of spacers on respective second portions of the second layer of the second electrode, wherein the first layer of the second electrode comprises a metal nitride or tantalum nitride, and the plurality of spacers of the second electrode comprise the metal nitride and oxygen or tantalum oxynitride. Additional features of the method are set forth in dependent claims <NUM> to <NUM>.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.

<FIG> are cross-sectional views of a bitcell structure at successive fabrication stages of a processing method in accordance with embodiments of the invention.

With reference to <FIG> and in accordance with embodiments of the invention, a bitcell <NUM> for a resistive random access memory device includes a transistor <NUM> that controls access to a subsequently-formed non-volatile memory element and a metallization level <NUM> of an interconnect structure over the transistor <NUM>. The transistor <NUM> may include a gate electrode <NUM>, a source <NUM>, and a drain <NUM>, and the transistor <NUM> may be formed by front-end-of-line processing of a substrate, such as a silicon-on-insulator substrate or a bulk semiconductor substrate. The gate electrode <NUM> may be comprised of a conductor, such as doped polycrystalline silicon (i.e., polysilicon) or one or more work-function metals, and a gate dielectric comprised of an electrical insulator, such as silicon dioxide or a high-k dielectric material. The source <NUM> and drain <NUM> may be comprised of a doped semiconductor material, such as doped silicon or doped silicon-germanium. The transistor <NUM> may be, for example, an n-type planar field-effect transistor, an n-type fin-type field-effect transistor, or an n-type gate-all-around field-effect transistor.

The metallization level <NUM> may be fabricated by back-end-of-line processing as a wiring layer of the interconnect structure. The metallization level <NUM> may include an interlayer dielectric layer <NUM> and a metal feature <NUM> disposed in the interlayer dielectric layer <NUM>. The interlayer dielectric layer <NUM> may be comprised of a dielectric material, such as silicon dioxide or a low-k dielectric material, that is an electrical insulator, and the metal feature <NUM> may be comprised of a metal, such as copper. The interconnect structure may include additional metallization levels (not shown) between the transistor <NUM> and the metallization level <NUM>, and the drain <NUM> of the transistor <NUM> may be coupled to the metal feature <NUM> by an interconnection <NUM> formed in the additional metallization levels. The interconnection <NUM> to the metal feature <NUM> may include metal islands, vias, and/or contacts arranged in the interlayer dielectric layers of the additional metallization levels.

Dielectric layers <NUM>, <NUM> may be formed over the metallization level <NUM>, and stacked metal features <NUM>, <NUM> may be formed as vias in the dielectric layers <NUM>, <NUM>. The dielectric layer <NUM> may be comprised of a dielectric material, such as silicon-carbon nitride or hydrogenated silicon-carbon nitride, that is an electrical insulator, and the dielectric layer <NUM> may be comprised of a dielectric material, such as silicon dioxide, that is an electrical insulator. The silicon dioxide comprising the dielectric layer <NUM> may be formed by plasma-enhanced chemical vapor deposition using ozone and tetraethylorthosilicate as reactants. The metal features <NUM>, <NUM> may be comprised of a metal, such as tantalum nitride, and the metal features <NUM>, <NUM> may be formed by deposition and planarization in respective openings that are patterned in the dielectric layers <NUM>, <NUM>.

Multiple layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> may be formed in a layer stack over, and on, the dielectric layers <NUM>, <NUM>. The layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> overlap with the underlying metal features <NUM>, <NUM>. The layer <NUM> may be comprised of a metal, such as tantalum nitride, and the layer <NUM> may have a thickness of about <NUM> nanometers. The layer <NUM> may be comprised of a metal capable of gettering a reactive species, such as oxygen, that may be present in, or introduced into, the layer stack. In an embodiment, the layer <NUM> may be comprised of titanium, and the layer <NUM> may have a thickness in a range of about <NUM> nanometers to about <NUM> nanometers. In an embodiment, the thickness of layer <NUM> may be about <NUM> nanometers. The layer <NUM> comprises a material capable of functioning as a switching layer in the completed device. In an embodiment, the layer <NUM> may be comprised of a metal oxide, such as hafnium oxide. In an embodiment, the thickness of the layer <NUM> is less than the thickness of the layer <NUM>. The layer <NUM> may be comprised of a noble metal, such as platinum, and the layer <NUM> may have a thickness of about <NUM> nanometers. The layer <NUM> comprises a metal nitride, such as tantalum nitride, that is capable of reacting with oxygen, and the layer <NUM> may have a thickness that is greater than or equal to <NUM> nanometers. The layer <NUM> may be comprised of a dielectric material, such as silicon nitride.

With reference to <FIG> in which like reference numerals refer to like features in <FIG> and at a subsequent fabrication stage, the layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of the layer stack are patterned by lithography and etching processes to form a non-volatile memory element <NUM>. The layer <NUM> may be initially patterned to define a hardmask that is subsequently used to pattern the underlying layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. The etching process used to pattern the layers <NUM>, <NUM>, <NUM>, <NUM>, <NUM> is a reactive ion etching process that relies on a gas mixture containing argon and oxygen. In an embodiment, the ratio of argon to oxygen in the gas mixture may range from <NUM>:<NUM> to <NUM>:<NUM>. The dielectric layer <NUM> may function as an etch stop during the reactive ion etching process.

The etched layers <NUM>, <NUM>, <NUM>, <NUM> may share sidewalls <NUM> and may have a width W1 between opposite sidewalls <NUM>. The etched layer <NUM> may have a width W2 that is less than the width W1, and spacers <NUM> may be formed at the periphery of the etched layer <NUM>. The etched layer <NUM> is disposed on an inner portion of the etched layer <NUM>, and the spacers <NUM> are disposed on outer portions of the etched layer <NUM>. In an embodiment, the etched layer <NUM> and the spacers <NUM> may fully cover a top surface of the etched layer <NUM> that is opposite to the interface between the etched layer <NUM> and the etched layer <NUM>. In an embodiment, the spacers <NUM> comprises a metal oxynitride, such as tantalum oxynitride. In an embodiment, the spacers <NUM> may be formed by the oxidation of peripheral portions of the metal of the layer <NUM> during the reactive ion etching process patterning the layer stack. The ratio of argon to oxygen in the gas mixture may contribute to minimizing etch damage while also forming the spacers <NUM>. Although not shown, peripheral portions of the etched layer <NUM> may also be oxidized during the reactive etching process.

The etched layer <NUM> may be disposed adjacent to the metal feature <NUM>. The metal feature <NUM>, which may be trapezoidal in shape, may have a width is less than the width W1 and that increases with decreasing distance from the etched layer <NUM>. The metal feature <NUM> may be disposed beneath a central portion of the etched layer <NUM>, and portions of the dielectric layer <NUM> may be disposed beneath outer portions of the etched layer <NUM>. The dielectric layer <NUM> may be recessed adjacent to the sidewalls <NUM> of the etched layers <NUM>, <NUM>, <NUM>, <NUM>. In an alternative embodiment, the sidewalls <NUM> and the spacers <NUM> may be curved with respective convex curvatures.

The etched layer <NUM> and the etched layer <NUM> collectively define a top electrode of the non-volatile memory element <NUM>. The etched layer <NUM> and the etched layer <NUM> collectively define a bottom electrode of the non-volatile memory element <NUM>. The etched layer <NUM> of the bottom electrode is electrically and physically connected to the metal feature <NUM>. The etched layer <NUM> defines a switching layer that is disposed in a vertical direction between the top electrode and the bottom electrode. The etched layer <NUM> of the bottom electrode is disposed between the etched layer <NUM> of the bottom electrode and the switching layer defined by the etched layer <NUM>. The etched layer <NUM> of the top electrode is disposed between the etched layer <NUM> of the top electrode and the switching layer defined by the etched layer <NUM>. In an embodiment, the etched layer <NUM> of the bottom electrode may adjoin the metal feature <NUM>, and the etched layer <NUM> of the bottom electrode may adjoin the switching layer defined by the etched layer <NUM>. In an embodiment, the etched layer <NUM> of the top electrode may adjoin the switching layer defined by the etched layer <NUM>.

With reference to <FIG> in which like reference numerals refer to like features in <FIG> and at a subsequent fabrication stage, dielectric layers <NUM>, <NUM> of a metallization level <NUM> may be formed over the non-volatile memory element <NUM>, and a metal feature <NUM> may be formed in the dielectric layers <NUM>, <NUM>. The dielectric layer <NUM> may be comprised of a dielectric material, such as silicon nitride, that is an electrical insulator, and the dielectric layer <NUM> may define a conformal capping layer that extends across the non-volatile memory element <NUM>. The dielectric layer <NUM> may be comprised of a dielectric material, such as silicon dioxide or a low-k dielectric material, that is an electrical insulator, and the metal feature <NUM> may be comprised of a metal, such as copper. The metal feature <NUM> may be physically and electrically connected to the etched layer <NUM> of the top electrode of the non-volatile memory element <NUM>. In an embodiment, the metal feature <NUM> may adjoin the etched layer <NUM> of the top electrode.

The gas mixture of argon and oxygen used to perform the reactive etching process patterning the non-volatile memory element <NUM> may prevent or reduce etch damage in comparison with other gas mixtures, such as a gas mixture of chlorine and fluorine, used in conventional reactive ion etching processes for the same purpose. The spacers <NUM> are concurrently formed during the reactive ion etching process patterning the layer stack, instead of being formed before the reactive ion etching process. The etched layer <NUM>, which is included in the bottom electrode and disposed immediately below the switching layer, may operate to prevent or reduce the occurrence of open bitcells.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.

References herein to terms modified by language of approximation, such as "about", "approximately", and "substantially", are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/- <NUM>% of the stated value(s).

References herein to terms such as "vertical", "horizontal", etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term "horizontal" as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction in the frame of reference perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction in the frame of reference within the horizontal plane.

A feature "connected" or "coupled" to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to or with another feature if intervening features are absent. A feature may be "indirectly connected" or "indirectly coupled" to or with another feature if at least one intervening feature is present. A feature "on" or "contacting" another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be "directly on" or in "direct contact" with another feature if intervening features are absent. A feature may be "indirectly on" or in "indirect contact" with another feature if at least one intervening feature is present. Different features "overlap" if a feature extends over, and covers a part of, another feature.

Claim 1:
A structure for a random-access resistive memory device, the structure comprising: a resistive memory element (<NUM>) including a first electrode, a second electrode, and a switching layer (<NUM>) disposed between the second electrode and the first electrode, the first electrode including a first layer (<NUM>) and a second layer (<NUM>) between the first layer (<NUM>) and the switching layer (<NUM>), the switching layer (<NUM>) having a first thickness, and the second layer (<NUM>) of the first electrode having a second thickness that is less than the first thickness of the switching layer (<NUM>), the second electrode including a first layer (<NUM>) and a second layer (<NUM>), wherein the second layer (<NUM>) of the second electrode is between the first layer (<NUM>) of the second electrode and the switching layer (<NUM>), characterised in that the first layer (<NUM>) of the second electrode comprises a metal nitride or tantalum nitride and is disposed on a first portion of the second layer (<NUM>) of the second electrode, and further comprising a plurality of spacers (<NUM>) disposed on respective second portions of the second layer (<NUM>) of the second electrode, wherein the plurality of spacers (<NUM>) comprise the metal nitride and oxygen or tantalum oxynitride.