Patent Description:
High speed differential signal traces are widely used in server/storage product designs. Many server/storage products include a chassis that mounts different printed circuit boards for electronic devices. The printed circuit boards include various signal traces to provide signals to the devices on the boards. Signal traces generally are arranged in differential trace pairs for a particular signal line. Such differential traces on a printed circuit board have different modes; including differential mode, common mode, and mode conversion between differential signals during transmission. Since more and more product applications include differential signal transition between different boards or between boards and cables, common mode energy will radiate through connectors over these transitions to holes in a chassis. Common mode energy results in a signal on both differential traces. Common mode energy can therefore generate noise that interrupts the transmission of signals over the traces and create interference problems.

<FIG> is an example of a prior art return current circuit trace <NUM> on a printed circuit board <NUM>. The printed circuit board <NUM> is attached to a ground plane layer <NUM>. The current circuit trace <NUM> includes two differential traces <NUM> and <NUM> on one surface <NUM> of the printed circuit board <NUM>. The ground plane layer <NUM> contacts the opposite surface of the printed circuit board <NUM>. An arrow <NUM> shows the insertion current in the differential trace <NUM>. An arrow <NUM> shows an induction current in the differential trace <NUM>. An arrow <NUM> shows a return current that is generated in the ground plane layer <NUM> under the differential trace <NUM>. As shown in <FIG> common mode energy is generated by the insertion current represented by the arrow <NUM> minus coupling terms.

<FIG> is a graph of electronic signal interference from signals in a server chassis. The server chassis includes boards with differential traces similar to that shown in <FIG>. The server chassis has several boards. The transition between the different boards allows common mode energy to radiate through holes in the chassis. A line <NUM> is the allowed noise for a trace in an FCC Class A digital device while a line <NUM> is the allowed noise for a system in an FCC Class A-AV device. As may be seen, the allowed noise level is lower for the more modern Class A-AV devices. A spike <NUM> represents unacceptable noise radiation at approximately <NUM> frequency generated from an example system such as a server chassis.

The <CIT> discloses a shielded three-layer patterned ground structure in a PCB. The PCB is disposed in a hard disk drive, and the PCBs are being made with only four total layers separated by dielectric material. By providing a shielded three-layer patterned ground structure, the common mode current and the magnitude of electromagnetic interference noise are reduced, without impacting the differential signal. The <CIT> discloses an electromagnetic noise filter device and an equivalent filter circuit thereof. The filter device comprises a substrate, a transmission line and a ground plane having slotted ground structure. The transmission line is configured on the top surface of the substrate, and the grounding plane is configured on the bottom surface of the substrate. At least one pair of impedance elements are configured within the slotted ground structure. The transmission line can be electromagnetic coupled to the slotted ground structure and the impedance elements so as to form an equivalent filter circuit.

The <CIT> discloses a multiple-layer circuit board having a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines is within the signaling layer, and propagates electromagnetic interference along the signaling layer. An element conductively extends inwards from the exterior layer, and as an antenna radiates the electromagnetic interference propagated by the strip lines along the signaling layer outwards from the circuit board. A defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the electromagnetic interference propagated by the strip lines to minimize the electromagnetic interference that the element radiates outwards as the antenna. The <CIT> discloses a common mode filtering method and a device for use with a defected ground structure. The device includes a substrate, coupled microstrip lines formed on the substrate and a ground plane formed underneath the substrate. The common mode filtering method comprises forming at least a defected ground structure on the ground plane and making dual mode signals pass through the coupled microstrip lines, thereby using the defected ground structure to suppress dual model noises within a specific frequency band and prevent signal distortion.

To reduce radiation caused by common mode energy, there is a need for trace design that reduces common mode energy, while maintaining total energy for differential signals. There is a further need for a differential trace that allows different shapes of a return path to reduce common mode energy. There is also a need for determining the length of a return path that causes interference to cancel noise at a specific frequency.

The problem of the present invention is solved by a high speed circuit for a low interference differential trace according to the independent claim <NUM> and by a method of producing a low interference differential trace according to the independent claim <NUM>. The dependent claims refer to further advantageous developments of the present invention.

The above summary is not intended to represent each embodiment or every aspect of the present disclosure. Rather, the foregoing summary merely provides an example of some of the novel aspects and features set forth herein. The above features and advantages, and other features and advantages of the present disclosure, will be readily apparent from the following detailed description of representative embodiments and modes for carrying out the present invention, when taken in connection with the accompanying drawings and the appended claims.

The disclosure will be better understood from the following description of exemplary embodiments together with reference to the accompanying drawings, in which:.

The present disclosure is susceptible to various modifications and alternative forms. Some representative embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed.

The present inventions can be embodied in many different forms. Representative embodiments are shown in the drawings, and will herein be described in detail. For purposes of the present detailed description, unless specifically disclaimed, the singular includes the plural and vice versa; and the word "including" means "including without limitation. " Moreover, words of approximation, such as "about," "almost," "substantially," "approximately," and the like, can be used herein to mean "at," "near," or "nearly at," or "within <NUM>-<NUM>% of," or "within acceptable manufacturing tolerances," or any logical combination thereof, for example.

<FIG> shows an example electronic device <NUM>. The electronic device <NUM> is a server that includes a number of different components contained in a chassis <NUM>. For example, one group of components <NUM> is mounted on one side of the chassis <NUM> above two power supply units <NUM>. Another group of components <NUM> is mounted in vertical slots in the chassis <NUM>. Each of the components in the groups of components <NUM> and <NUM> include printed circuit boards. The printed circuit boards include differential traces that connect the electronic components on the boards and conduct signals between the components. The chassis <NUM> has a number of holes through which noise generated from the circuit boards of the components <NUM> and <NUM> may be emitted.

<FIG> is a graph that shows output noise through the holes in the chassis <NUM> with known differential trace circuits. As shown in <FIG>, the output noise occurs at approximately <NUM> in this example. The output noise is generated due to common mode energy from the differential traces on the circuit boards in the chassis.

In order to decrease this interference, each of the boards of the components <NUM> and <NUM> (in <FIG>) includes differential traces that incorporate a return path design in the ground plane layer that reduces common mode energy at the target frequency of <NUM>. The incorporation of such traces thereby decreases the electronic noise generated by the electronic device <NUM>. The target frequencies are determined by interference testing of the chassis <NUM>. The target frequency depends on the trace data rate transmitted on the boards in the chassis <NUM>.

The process of designing a return trace to reduce common mode energy relies on the fact a differential trace circuit may be modeled using a four port s-parameter. For a four port (<NUM> signal trace) s-parameter, there are insertion terms S31 and S42 and induction terms S41 and S32. The induction terms have an opposite direction to the insertion terms based on Lenz's Law. Based on a mixed mode s-parameter formula, the differential mode output (Sdd21) of the differential signals is:
<MAT>.

The common mode output (Scc21) of the differential signals is:
<MAT>.

In order to reduce common mode output energy, an increase in the coupling terms is desired. As shown in <FIG>, there will be a return current for a differential signal, represented by the arrow <NUM>, in the ground plane <NUM> just underneath the trace <NUM>. The return current represented by the arrow <NUM> flows in the opposite direction of the current represented by arrow <NUM> in the trace <NUM>. Thus, a return current path may be designed that results in destructive interference at a target frequency. In this situation, a nearby trace, such as the trace <NUM>, will be the new path for the return current. This new return current path increases the coupling terms. Hence, the common mode will be greatly reduced. The formula for the length of the new return current path is:
<MAT>.

In this equation, Lpath is the length of the new path. TD is the time delay per mil length (<NUM> mil = <NUM> micrometers) for the differential signal propagating in the trace, and f is the target radiation frequency.

<FIG> is a perspective view of an example trace configuration <NUM> that is designed from the above criteria. <FIG> shows a perspective top view of the example differential trace design in <FIG>. <FIG> is a top-down view of the example trace design in <FIG>. Like elements are labeled with like numerals in <FIG>. The trace design <NUM> in <FIG> is formed on a printed circuit board <NUM>. The printed circuit board <NUM> has a first surface <NUM>, and an opposite second surface <NUM>. The second surface <NUM> is in contact with a ground plane layer <NUM>. Two parallel traces <NUM> and <NUM> are formed on the first surface <NUM> of the printed circuit board <NUM>. The ground plane layer <NUM> has a first surface <NUM> that is in contact with the second surface <NUM> of the circuit board <NUM>. A U-shaped, current return path pattern <NUM> is created in the first surface <NUM> of the ground plane layer <NUM>. The U-shaped pattern <NUM> includes a first void section <NUM> that is located to the side of the trace <NUM> in this example. The void section <NUM> in this example is approximately parallel to the trace <NUM>. The U-shaped pattern <NUM> also includes a void section <NUM> that is located to the side of the trace <NUM> in this example. The void section <NUM> is approximately parallel to the trace <NUM> in this example. A void section <NUM> joins the void sections <NUM> and <NUM>. The void sections <NUM> and <NUM> thus are located in the ground plane layer <NUM> outside of the respective traces <NUM> and <NUM>.

As may be seen in <FIG>, an arrow <NUM> represents the insertion current in the trace <NUM>. An arrow <NUM> represents the induction current that flows through the trace <NUM>. The U-shaped pattern <NUM> causes destructive interference of any return current in the ground plane layer <NUM> at the desired frequency. Thus, an arrow <NUM> shows the return current has been shifted to the parallel trace <NUM>. In so doing, destructive interference from the direction of the induction current <NUM> cancel the current generated from the opposite direction of the insertion current <NUM>. A dashed line <NUM> represents the return current that is eliminated based on the destructive interference from the void sections <NUM>, <NUM> and <NUM> of the U-shaped pattern <NUM>.

In this example, it is desired to avoid a target radiation frequency of <NUM>. The length of the void section <NUM> constitutes the new current return path as determined by the above formula. In this example, given the target radiation frequency is <NUM> and the time delay (TD) per mil is <NUM>*<NUM>-<NUM>, the length of the return path, Lpath, is determined to be <NUM> mil (<NUM>). Comparing the common mode output, Scc21, resulting from the U-shaped pattern <NUM>, and the common mode output from a conventional differential trace without the U-shaped pattern <NUM>, there is deep drop close to <NUM> which meets the design target.

<FIG> is a graph of the noise level generated from the trace circuit <NUM> compared with that of a trace circuit without the U-shaped pattern <NUM> in <FIG>. A first line <NUM> represents a differential trace that does not include the voids of the U-shaped pattern <NUM>. A second line <NUM> represents the drop in return current based on the new return current path in the void section <NUM> in <FIG>. As may be seen in <FIG>, the drop in return current occurs at approximately <NUM>, which results in additional coupling and then reducing the common node noise at the target frequency.

The differential trace circuit <NUM> in <FIG> may be specifically produced to address radiation at a certain frequency. The differential traces <NUM> and <NUM> are formed on the surface <NUM> of the printed circuit board <NUM>. The void section <NUM> is formed on the surface <NUM> of the ground plane layer <NUM>. The length of the void section <NUM> is determined based on a target radiation frequency. As explained above, the length is determined based on the target radiation frequency and the time delay per mil length for the differential signal propagating in the traces <NUM> and <NUM>. The void section <NUM> is formed with the determined length on the surface <NUM> of the ground plane layer <NUM>. The void section <NUM> is formed on one side, in proximity, of the differential trace <NUM>, and the void section <NUM> is formed on one side, in proximity, to the differential trace <NUM>. The void section <NUM> is formed on the ground plane layer <NUM> to join the void section <NUM> and the void section <NUM>. Once the void sections <NUM>, <NUM>, and <NUM> of the U-shaped pattern <NUM> are formed in the ground plane layer <NUM>, the ground plane layer <NUM> is joined to the surface <NUM> of the printed circuit board <NUM>.

Although the void sections <NUM>, <NUM>, and <NUM> in the example U-shaped pattern <NUM> are roughly straight line shapes, the reduction in common mode interference may be accomplished by any shape or pattern of voids in the ground plane <NUM>, as long as the void section for the new return current has a length determined from the desired target radiation frequency. Further, the void sections for a return current pattern in the ground plane <NUM> need only include one void section on one side from the differential trace <NUM>; a second void section in on the opposite side from the differential trace <NUM>; and a third void section connecting the first two void sections. Although the above examples, show the third void section being perpendicular to the first and second void sections, any angle may be selected for the third void section relative to the first and second void sections. The shapes of the void sections such as the void sections <NUM> and <NUM> do not have to be identical. Thus, the shape of the void section <NUM> may be one shape, while the void section <NUM> may have another shape, as long as the void section <NUM> has the sufficient length determined from the target frequency.

<FIG> is a perspective view of another example trace circuit <NUM> with a different shaped return path than that of the U-shaped pattern <NUM> in <FIG>. The trace design <NUM> in <FIG> is formed on a printed circuit board <NUM>. The printed circuit board <NUM> has a top surface <NUM> and an opposite bottom surface. The bottom surface is in contact with a ground plane layer underlying the printed circuit board <NUM>. Two parallel traces <NUM> and <NUM> are formed on the top surface <NUM>. A series of void sections is created on the surface of the ground plane layer in contact with the bottom surface of the printed circuit board <NUM>. The void sections include a continuous segment <NUM> that is located to one side of the trace <NUM>. The void sections also include two segments <NUM> and <NUM> that are parallel to the trace <NUM>. Both of the two segments <NUM> and <NUM> are located to a side of the trace <NUM>. One of the segments <NUM> is located proximally to the side of the trace <NUM>. The other segment <NUM> is offset from the trace <NUM> and located distally to the side of the trace <NUM>. The segments <NUM> and <NUM> are joined together by a cross segment <NUM> to create a ladder shape. A void section <NUM> joins the segments <NUM>, <NUM>, and <NUM>. As may be seen in <FIG>, the shapes and relative locations for the segments <NUM> and <NUM> in relation to the trace <NUM> differ from those of the segment <NUM> in relation to the trace <NUM>.

The overall length of the two segments <NUM> and <NUM>, combined, is determined by the above formula to cancel a target radiation frequency. In this example, given the target radiation frequency is <NUM> and the time delay (TD) per mil is <NUM>*<NUM>-<NUM>, the length of the return path, Lpath, is determined to be <NUM> mil (<NUM>). Thus, the total length of the two segments <NUM> and <NUM> in <FIG> is <NUM> mil (<NUM>).

Similar to the differential trace circuit <NUM> in <FIG>, an insertion current is generated in the trace <NUM>. An induction current flows through the trace <NUM>. The void section of the segments <NUM> and <NUM> causes destructive interference of any return current in the ground plane layer at the desired target frequency. Thus, the return current is shifted to the parallel trace <NUM>. As explained above, the shape and distance to the trace <NUM> of the segment <NUM> may vary and be similar or different from those of the segments <NUM> and <NUM>. Different patterns and locations for the segments <NUM> and <NUM> other than the ladder configuration may be used.

<FIG> is a graph of the noise level generated from the trace circuit <NUM>. A first line <NUM> represents the return current from the differential trace circuit <NUM> in <FIG>. A second line <NUM> represents the return current from the differential trace circuit <NUM> in <FIG>. As may be seen, the configuration of the return path in <FIG> results in roughly the same drop in return current as that of the return path in <FIG>. Thus, the alternate differential trace configuration <NUM> in <FIG> is effective in canceling noise at the target frequency of <NUM>.

As used in this application, the terms "component," "module," "system," or the like, generally refer to a computer-related entity, either hardware (e.g., a circuit), a combination of hardware and software, software, or an entity related to an operational machine with one or more specific functionalities. For example, a component may be, but is not limited to being, a process running on a processor (e.g., digital signal processor), a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a controller, as well as the controller, can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. Further, a "device" can come in the form of specially designed hardware; generalized hardware made specialized by the execution of software thereon that enables the hardware to perform specific function; software stored on a computer-readable medium; or a combination thereof.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or variants thereof, are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Claim 1:
A high speed circuit for a low interference differential trace, the high speed circuit comprising:
a printed circuit board (<NUM>, <NUM>) having a first surface (<NUM>) and an opposite second surface (<NUM>);
a ground plane layer (<NUM>) having a first surface (<NUM>) in contact with the second surface (<NUM>) of the printed circuit board (<NUM>, <NUM>);
a pair of first and second differential traces (<NUM>, <NUM>) on the first surface (<NUM>) of the board structure, the differential traces (<NUM>, <NUM>) carrying an electrical signal;
a first void section (<NUM>) on the first surface (<NUM>) of the ground plane layer (<NUM>), the first void section (<NUM>) on one side of the first differential trace (<NUM>), wherein the first void section (<NUM>) is parallel to the first differential trace (<NUM>);
a second void section (<NUM>) on the first surface (<NUM>) of the ground plane layer (<NUM>), the second void section (<NUM>) on one side of the second differential trace (<NUM>), wherein the second void section (<NUM>) is parallel to the second differential trace (<NUM>); and
a third void section (<NUM>) on the first surface (<NUM>) of the ground plane layer (<NUM>), the third void section (<NUM>) joining the first and second void sections (<NUM>, <NUM>);
characterized in that a length of the first void section (<NUM>) and the second void section (<NUM>) for current returning is determined based on a target radiation frequency which the high speed circuit avoids and a time delay per mil length for a differential signal propagating in the differential traces (<NUM>, <NUM>) according to the equation <MAT>
wherein TD is the time delay per mil length for the differential signal propagating in the differential traces (<NUM>, <NUM>), <NUM> mil = <NUM>,<NUM> micrometers, and f is the target radiation frequency.