Patent Description:
<FIG> illustrates a configuration example of a front end unit of a reception circuit of a serializer/de-serializer (SerDes). <FIG> illustrates an example of an NRZ (Non Return to Zero) reception circuit which receives a binary NRZ signal of "<NUM>" or "<NUM>". In the reception circuit illustrated in <FIG>, an amplifier <NUM> amplifies a binary NRZ signal SIN inputted to a serial signal input terminal, and comparators <NUM>-L0 and <NUM>-L1 which a comparator circuit <NUM> includes and comparators <NUM>-H0 and <NUM>-H1 which a comparator circuit <NUM> includes each perform determination of "<NUM>" and "<NUM>" and output a determination result.

In <FIG>, an example of a half-rate configuration in which data is sampled in a half cycle of a data rate by the comparators <NUM>-L0, <NUM>-L1, <NUM>-H0, and <NUM>-H1 is illustrated. Further, an example of a configuration in which boundary detection related to the binary NRZ signal is performed by comparators <NUM>-C0 and <NUM>-C1 which a comparator circuit 602C includes and a clock data recovery circuit operates with a phase comparator by 2x sampling is illustrated. Therefore, as illustrated in <FIG>, four-phase clocks I, Q, IX, and QX corresponding to phases of <NUM> degrees, <NUM> degrees, <NUM> degrees, and <NUM> degrees respectively are supplied. Operation timings of the comparators <NUM>-L0, <NUM>-L1, <NUM>-H0, and <NUM>-H1 which determine data of the binary NRZ signal are controlled based on the clocks I and IX, and operation timings of the comparators <NUM>-C0 and <NUM>-C1 which perform edge determination of data for phase detection of clock data recovery are controlled based on the clocks Q and QX.

In the example illustrated in <FIG>, in order to remove an effect due to inter symbol interference (ISI) of data which occurs in a transmission path and heighten reception accuracy, a decision feedback equalizer (DFE) which compensates a signal loss due to the inter symbol interference based on a determination result of past data is applied. In <FIG>, in order to compensate the effect due to the inter symbol interference after <NUM> unit interval (UI), a one-tap DFE which compensates the signal loss due to the inter symbol interference based on data before <NUM> UI is applied.

In <FIG>, a determination level of the comparators <NUM>-L0 and <NUM>-L1 which the comparator circuit <NUM> includes and a determination level of the comparators <NUM>-H0 and <NUM>-H1 which the comparator circuit <NUM> includes are deviated, and based on a previous determination result which is before <NUM> UI, a determination result of the comparator which is to be selected is selected by selectors <NUM> and <NUM> provided in a subsequent stage of the comparators. The selected data is used for selection determination of data after next <NUM> UI.

For example, determination results of the comparator <NUM>-L0 and the comparator <NUM>-H0 are inputted to the selector <NUM>. When output data of the selector <NUM> which is a determination result before <NUM> UI is "<NUM>", the selector <NUM> selects the determination result of the comparator <NUM>-L0, which is outputted as output data, and when the output data of the selector <NUM> is "<NUM>", the selector <NUM> selects the determination result of the comparator <NUM>-H0, which is outputted as output data. Further, for example, determination results of the comparator <NUM>-L1 and the comparator <NUM>-H1 are inputted to the selector <NUM>. When output data of the selector <NUM> which is a determination result before <NUM> UI is "<NUM>", the selector <NUM> selects the determination result of the comparator <NUM>-L1, which is outputted as output data, and when the output data of the selector <NUM> is "<NUM>", the selector <NUM> selects the determination result of the comparator <NUM>-H1, which is outputted as output data.

Data is sampled alternately in the reception circuit with the half-rate configuration in this manner, thereby resulting in a determination result of a comparator in which data before <NUM> UI is operated in a phase opposite to a target comparator and allowing the reception circuit of the one-tap DFE to be configured by a simple configuration as illustrated in <FIG>. A timing aligner <NUM> synchronizes data to be inputted at a timing corresponding to each of the four-phase clocks I, Q, IX, and QX and different from one another with a single clock and outputs the data. This makes it possible that a not-illustrated demultiplexer in a subsequent stage performs data processing in the single clock.

<FIG> illustrates another configuration example of a front end unit of a reception circuit of a serializer/de-serializer. <FIG> illustrates an example of a pulse amplitude modulation <NUM> (PAM4) reception circuit which receives not the binary NRZ signal but a <NUM>-valued pulse amplitude modulation signal referred to as PAM4. In the PAM4 reception circuit illustrated in <FIG>, an amplifier <NUM> amplifies a <NUM>-valued PAM4 signal SIN inputted to a serial signal input terminal, and comparators <NUM>-L0 and <NUM>-L1 which a comparator circuit <NUM> includes, comparators <NUM>-Z0 and <NUM>-Z1 which a comparator circuit 702Z includes, and comparators <NUM>-H0 and <NUM>-H1 which a comparator circuit <NUM> includes determine data at three determination levels, thereby determining an input signal as a <NUM>-bit thermometer code. Thermometer codes to be obtained, of "<NUM>", "<NUM>", "<NUM>", and "<NUM>" correspond to four values of <NUM>, <NUM>, <NUM>, and <NUM> respectively, and a logic circuit (PAM4 decoder) <NUM> to which the thermometer codes are inputted via a timing aligner <NUM> performs this conversion.

Also in <FIG>, an example of a configuration in which data is sampled in a half cycle of a data rate is illustrated. Further, an example of a configuration in which boundary detection related to the <NUM>-valued PAM4 signal is performed by comparators <NUM>-C0 and <NUM>-C1 which a comparator circuit 702C includes and a clock data recovery circuit operates with a phase comparator by 2x sampling is illustrated. Operation timings of the comparators <NUM>-L0, <NUM>-L1, <NUM>-Z0, <NUM>-Z1, <NUM>-H0, and <NUM>-H1 which determine data of the <NUM>-valued PAM4 signal are controlled based on the clocks I and IX, and operation timings of comparators <NUM>-C0 and <NUM>-C1 which perform boundary detection for phase detection of clock data recovery are controlled based on clocks Q and QX.

There has been proposed a clock data recovery (CDR) circuit which has both functions of a CDR circuit of a phase locked loop method and a CDR circuit of an over-sampling method and allows switching between both the methods (refer to Patent Document <NUM>). There has been proposed a communication semiconductor integrated circuit in which a ΔΣ (sigma-delta) type analog-digital conversion circuit capable of changing the number of operating comparators among comparators configuring a quantizer according to a communication system, and obtaining a desired noise shape characteristic while corresponding to two communication systems is built (refer to Patent Document <NUM>).

Patent Document <NUM>: <CIT>. Patent Document <NUM>: <CIT>.

Reference may be made to any of: <CIT>, which relates to a system and method for selecting optimal data transition types for clock and data recovery, wherein a clock recovery circuit samples an incoming data stream that includes sequences of signal transitions, a transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and <NUM> PAM signaling schemes, select logic control circuitry analyzes the signal-transition types to determine which of the transition types is best suited for clock recovery - this determination relies upon a number of factors, including for example whether the received signal is a 4PAM signal or a 2PAM signal, the existence of a pattern within the received data, or the relative abundance or scarcity of certain types of transitions; <CIT>, which relates to an apparatus and method for clock and data recovery of N-PAM encoded signals using a conventional <NUM>-PAM CDR circuit; a paper titled "<NPL>) ; and <CIT>, which relates to a decision feedback equalizer for N-level amplitude modulated signals.

A PAM4 signal is capable of communicating data of two bits in one symbol, and therefore it is possible to achieve a double data rate in the PAM4 signal compared with an NRZ signal, but on the other hand, the NRZ signal is excellent in reception accuracy due to a large eye opening compared with the PAM4 signal. It is preferable that communication can be performed by selecting an appropriate modulation method according to a communication situation such as a transmission line and a size of crosstalk in order to take advantage of the features of the respective signals, but when circuits corresponding to the respective modulation methods are each provided, a circuit scale becomes large.

It is an object of the embodiment to provide a reception circuit capable of suppressing an increase in a circuit scale and corresponding to a plurality of modulation methods. The present invention is defined by the independent claim, to which reference should now be made. Specific embodiments are defined in the dependent claims. One aspect of a reception circuit includes: a determination circuit including: a first number of first comparator circuits configured to perform determination of a level of a received signal on the basis of a first clock signal among four clock signals having different phases and output first determination signals; and the first number of second comparator circuits configured to perform determination of a level of the received signal on the basis of a second clock signal among the four clock signals, wherein the phase difference between the first and second clock signals is <NUM> degrees, and output second determination signals, the determination circuit being configured to perform determination by using the first number of the first comparator circuits and the first number of the second comparator circuits when the received signal is a first signal which is a multi-valued signal, and configured to perform determination by using a second number of the first comparator circuits and the second number of the second comparator circuits, the second number being two or more and smaller than the first number, when the received signal is a second signal, a number of possible values of the second signal being smaller than a number of possible values of the first signal;a timing aligner circuit configured to synchronize the first determination signals and the second determination signals with one of the four clock signals and output first synchronized determination signals corresponding to the first determination signals and second synchronized determination signals corresponding to the second determination signals; and a logic circuit configured to generate digital signals based on the first and second synchronized determination signals, the logic circuit being configured to operate as a decoder which decodes the first and second synchronized determination signals and generates the digital signals when the received signal is the first signal, and configured to operate as a selector which selects one of the first synchronized determination signals and one of the second synchronized determination signals and generates the digital signals when the received signal is the second signal.

Hereinafter embodiments will be described with reference to the drawings.

<FIG> is a diagram illustrating a configuration example of a front end unit of a reception circuit in an embodiment. <FIG> illustrates an example of a reception circuit capable of treating a binary non return to zero (NRZ) signal of "<NUM>" or "<NUM>", and a <NUM>-valued pulse amplitude modulation <NUM> (PAM4) signal of "<NUM>", "<NUM>", "<NUM>", and "<NUM>".

An amplifier circuit <NUM> amplifies a received serial signal SIN to be inputted from a serial signal input terminal. The signal amplified by the amplifier circuit <NUM> is inputted to a determination circuit <NUM>. The determination circuit <NUM> includes comparator circuits <NUM>, 12Z, and <NUM> for data determination, and a comparator circuit 12C for boundary detection for phase detection of clock data recovery, and the signal amplified by the amplifier circuit <NUM> is inputted to the comparator circuits <NUM>, 12Z, and <NUM> for data determination and the comparator circuit 12C for boundary detection for phase detection of clock data recovery. In this embodiment, the determination circuit <NUM> includes the three comparator circuits <NUM>, 12Z, and <NUM> for data determination, and this is because the binary NRZ signal and the <NUM>-valued PAM4 signal are treated. When the one having the maximum number of signal levels among pulse amplitude modulation signals to be received is an N-valued PAM signal, the determination circuit <NUM> may include (N - <NUM>) or more comparator circuits for data determination.

Each of the comparator circuits <NUM>, 12Z, and <NUM> includes comparators of ratio numbers of frequency of a comparison cycle of a comparator to a symbol rate of data. For example, in a case of a half-rate operation in which the comparator operates at a rate half of the symbol rate, each of the comparator circuits <NUM>, 12Z, and <NUM> includes two comparators. In this embodiment, an example of a half-rate configuration is given, and the comparator circuit <NUM> includes two comparators <NUM>-L0 and <NUM>-L1, the comparator circuit 12Z includes two comparators <NUM>-Z0 and <NUM>-Z1, and the comparator circuit <NUM> includes two comparators <NUM>-H0 and <NUM>-H1.

Operation timings of the comparators <NUM>-L0, <NUM>-Z0, and <NUM>-H0 are controlled based on a clock I corresponding to a phase of <NUM> degrees among four-phase clocks. The comparators <NUM>-L0, <NUM>-Z0, and <NUM>-H0 determine the signal amplified by the amplifier circuit <NUM> based on thresholds (determination level, comparison reference voltage) and output determination results as signals DLI, DZI, and DHI respectively. Operation timings of the comparators <NUM>-L1, <NUM>-Z1, and <NUM>-H1 are controlled based on a clock IX corresponding to a phase of <NUM> degrees among the four-phase clocks. The comparators <NUM>-L1, <NUM>-Z1, and <NUM>-H1 determine the signal amplified by the amplifier circuit <NUM> based on thresholds (determination level, comparison reference voltage) and output determination results as signals DLIX, DZIX, and DHIX respectively. The thresholds in the comparators <NUM>-L0, <NUM>-Z0, and <NUM>-H0 and the comparators <NUM>-L1, <NUM>-Z1, and <NUM>-H1 are controlled by an equalizer logic circuit or the like illustrated in <FIG>.

The comparator circuit 12C includes the number of comparators according to the number of samplings of boundary detection for a phase adjustment in a clock data recovery circuit. In this embodiment, an example of a configuration in which the clock data recovery circuit operates with a phase comparator by 2x sampling is given, and the comparator circuit 12C includes two comparators <NUM>-C0 and <NUM>-C1. An operation timing of the comparator <NUM>-C0 is controlled based on a clock Q corresponding to a phase of <NUM> degrees among the four-phase clocks. The comparator <NUM>-C0 outputs a determination result as a signal CLQ. An operation timing of the comparator <NUM>-C1 is controlled based on a clock QX corresponding to a phase of <NUM> degrees among the four-phase clocks. The comparator <NUM>-C1 outputs a determination result as a signal CLQX.

A timing aligner <NUM> synchronizes the signals to be inputted from the comparator circuits <NUM>, 12Z, and <NUM> at a timing corresponding to each of the four-phase clocks I, Q, IX, and QX and different from one another with a single clock (for example, any clock of the four-phase clocks I, Q, IX, and QX) and outputs the signals. This makes it possible that a circuit in a subsequent stage performs data processing in the single clock. A logic circuit <NUM>, whose operation mode is switched by a control signal CTL, achieves a function of a decoder for the <NUM>-valued PAM4 signal or a function of a selector of a one-tap decision feedback equalizer (DFE) according to the control signal CTL. In this embodiment, when the control signal CTL is "<NUM>", the logic circuit <NUM> operates as the decoder for the <NUM>-valued PAM4 signal, and when the control signal CTL is "<NUM>", the logic circuit <NUM> operates as the selector of the one-tap DFE.

When the front end unit of the reception circuit illustrated in <FIG> operates as a PAM4 reception circuit which receives the <NUM>-valued PAM4 signal, the comparators which operate with the same phase clock in the comparator circuits <NUM>, 12Z, and <NUM> determine a level of a received signal at thresholds different from one another, and output determination results as a <NUM>-valued thermometer code. Specifically, a threshold of the comparators <NUM>-L0 and <NUM>-L1 which the comparator circuit <NUM> includes is set to a determination level which distinguishes between "<NUM>" and "<NUM>" in a PAM4 signal. A threshold of the comparators <NUM>-Z0 and <NUM>-Z1 which the comparator circuit 12Z includes is set to a determination level which distinguishes between "<NUM>" and "<NUM>" in the PAM4 signal. A threshold of the comparators <NUM>-H0 and <NUM>-H1 which the comparator circuit <NUM> includes is set to a determination level which distinguishes between "<NUM>" and "<NUM>" in the PAM4 signal.

Accordingly, when the PAM4 signal corresponding to a value "<NUM>" is received, all of output signals DLI, DZI, and DHI (DLIX, DZIX, and DHIX) of the comparators <NUM>-L0, <NUM>-Z0, and 12H0 (<NUM>-L1, <NUM>-Z1, and <NUM>-H1) become "<NUM>", and a thermometer code of "<NUM>" is outputted. When the PAM4 signal corresponding to a value "<NUM>" is received, the output signal DLI (DLIX) of the comparator <NUM>-L0 (<NUM>-L1) becomes "<NUM>", and the output signals DZI and DHI (DZIX and DHIX) of the comparators <NUM>-Z0 and 12H0 (<NUM>-Z1 and <NUM>-H1) become "<NUM>", and a thermometer code of "<NUM>" is outputted.

When the PAM4 signal corresponding to a value "<NUM>" is received, the output signals DLI and DZI (DLIX and DZIX) of the comparators <NUM>-L0 and <NUM>-Z0 (<NUM>-L1 and <NUM>-Z1) become "<NUM>", and the output signal DHI (DHIX) of the comparator <NUM>-H0 (<NUM>-H1) becomes "<NUM>", and a thermometer code of "<NUM>" is outputted. When the PAM4 signal corresponding to a value "<NUM>" is received, all of the output signals DLI, DZI, and DHI (DLIX, DZIX, and DHIX) of the comparators <NUM>-L0, <NUM>-<NUM>, and 12H0 (<NUM>-L1, <NUM>-Z1, and <NUM>-H1) become "<NUM>", and a thermometer code of "<NUM>" is outputted.

When the front end unit of the reception circuit illustrated in <FIG> operates as an NRZ reception circuit which receives the binary NRZ signal, two comparator circuits among the three comparator circuits <NUM>, 12Z, and <NUM> are operated as illustrated in <FIG>, for example. <FIG> illustrates a case of operating the comparator circuits <NUM> and <NUM> as one example. Then, the comparators which operate with the same phase clock in the comparator circuits <NUM> and <NUM> determine a level of a received signal at thresholds different from each other, and output determination results. A threshold of the comparators <NUM>-L0 and <NUM>-L1 which the comparator circuit <NUM> includes is set to, for example, a threshold corresponding to "<NUM>" in a determination result before <NUM> unit interval (UI), and a threshold of the comparators <NUM>-H0 and <NUM>-H1 which the comparator circuit <NUM> includes is set to, for example, a threshold corresponding to "<NUM>" in a determination result before <NUM> UI. Note that the thresholds of the comparators <NUM>-L0, <NUM>-L1, <NUM>-H0, and <NUM>-H1 can also be set to thresholds corresponding to a determination result before <NUM> UI or more.

In a case of operating as the NRZ reception circuit which receives the binary NRZ signal, a circuit operation of a comparator circuit (the comparator circuit 12Z in an example illustrated in <FIG>) not to be used may be stopped (powered down). For example, as illustrated in <FIG>, to the comparators <NUM>-H0, <NUM>-Z0, and <NUM>-L0, a clock signal CLK is supplied via AND (logical product operation) gates <NUM>, <NUM>, and <NUM> to which enable signals EN1, EN2, and EN3 are inputted respectively. Note that the enable signals EN1, EN2, and EN3 are outputted from, for example, the equalizer logic circuit or the like illustrated in <FIG>, and "<FIG>" indicates an enable state.

Then, when circuit operations of the comparators <NUM>-H0, <NUM>-Z0, and <NUM>-L0 are stopped (powered down), supply of the clock signal CLK to the comparators is stopped by setting the enable signals EN1, EN2, and EN3 corresponding thereto to "<NUM>". For example, when the circuit operation of the comparator 12Z is stopped (powered down) as in the example illustrated in <FIG>, the enable signal EN2 is set to "<NUM>". Note that a configuration of a circuit according to operation control of the comparators illustrated in <FIG> is one example, and is not limited to this configuration. The circuit operation of the comparator circuit not to be used may be stopped (powered down) by another circuit including a configuration different from the configuration illustrated in <FIG>.

<FIG> is a diagram illustrating one example of the logic circuit <NUM> illustrated in <FIG>. The logic circuit <NUM> includes inverters <NUM> and <NUM>, AND gates <NUM> and <NUM>, selectors <NUM>, <NUM>, <NUM>, and <NUM>, buffers <NUM> and <NUM>, and flip-flops <NUM> to <NUM> as illustrated in <FIG>. The flip-flops <NUM> to <NUM> operate with the same clock as the clock used when the timing aligner <NUM> synchronizes the signals from the comparator circuits <NUM>, 12Z, and <NUM> and outputs the signals.

Note that <FIG> illustrates an example of a case where the comparator circuits <NUM> and <NUM> are operated in operating as the NRZ reception circuit which receives the binary NRZ signal. The signals DHI, DZI, DLI, DHIX, DZIX, and DLIX are signals outputted from the timing aligner <NUM>.

The signal DHI is inputted to the AND gate <NUM> via the inverter <NUM>, and inputted to the selector <NUM>. The signal DZI is inputted to the flip-flop <NUM> via the buffer <NUM>. The signal DLI is inputted to the AND gate <NUM> and the selector <NUM>. The signal DHIX is inputted to the AND gate <NUM> via the inverter <NUM>, and inputted to the selector <NUM>. The signal DZIX is inputted to the flip-flop <NUM> via the buffer <NUM>. The signal DLIX is inputted to the AND gate <NUM> and the selector <NUM>.

The AND gate <NUM> performs a logical product operation on a signal to be inputted and outputs an operation result to the selector <NUM>. The AND gate <NUM> performs a logical product operation on a signal to be inputted and outputs an operation result to the selector <NUM>. The selector <NUM> selects either of the signal DHI and the signal DLI and outputs to the selector <NUM>, according to an output of the flip-flop <NUM>. The selector <NUM> selects either of the signal DHIX and the signal DLIX and outputs to the selector <NUM>, according to an output of the selector <NUM>. Note that the reason why the output of the flip-flop <NUM> is used as a selection signal of the selector <NUM> is because the one before data outputted from the flip-flop <NUM> corresponds to data before <NUM> UI.

The selector <NUM> selects either of an output of the AND gate <NUM> and an output of the selector <NUM> and outputs to the flip-flop <NUM>, according to the control signal CTL. The selector <NUM> selects either of an output of the AND gate <NUM> and an output of the selector <NUM> and outputs to the flip-flop <NUM>, according to the control signal CTL. An output of the flip-flop <NUM> is outputted as an output signal DOI[<NUM>] (a 0th bit of an output signal DOI), and an output of the flip-flop <NUM> is outputted as an output signal DOIX[<NUM>] (a 0th bit of an output signal DOIX). An output of the flip-flop <NUM> is outputted as an output signal DOI[<NUM>] (a 1st bit of the output signal DOI), and an output of the flip-flop <NUM> is outputted as an output signal DOIX[<NUM>] (a 1st bit of the output signal DOIX). The output signals DOI from the flip-flops <NUM> and <NUM> and the output signals DOIX from the flip-flops <NUM> and <NUM> are supplied to a not-illustrated demultiplexer in a subsequent stage.

In this embodiment, when the output of the flip-flop <NUM> is "<NUM>", the selector <NUM> selects and outputs the signal DHI. When the output of the flip-flop <NUM> is "<NUM>", the selector <NUM> selects and outputs the signal DLI. Similarly, when the output of the selector <NUM> is "<NUM>", the selector <NUM> selects and outputs the signal DHIX. When the output of the selector <NUM> is "<NUM>", the selector <NUM> selects and outputs the signal DLIX.

When the control signal CTL is "<NUM>", namely when operating as the PAM4 reception circuit, the selector <NUM> selects and outputs the output of the AND gate <NUM>. When the control signal CTL is "<NUM>", namely when operating as the NRZ reception circuit, the selector <NUM> selects and outputs the output of the selector <NUM>. Similarly, when the control signal CTL is "<NUM>", namely when operating as the PAM4 reception circuit, the selector <NUM> selects and outputs the output of the AND gate <NUM>. When the control signal CTL is "<NUM>", namely when operating as the NRZ reception circuit, the selector <NUM> selects and outputs the output of the selector <NUM>.

The logic circuit <NUM> configured in this manner operates as the decoder for the <NUM>-valued PAM4 signal as follows when the control signal CTL is "<NUM>", namely when operating as the PAM4 reception circuit. The logic circuit <NUM> outputs, an operation result in which a logical product operation is performed by the AND gate <NUM> on an inverted signal of the signal DHI which is a 2nd bit of a thermometer code obtained by sampling based on the clock I and the signal DLI which is a 0th bit thereof, as the output signal DOI[<NUM>] (the 0th bit of the output signal DOI) via the selector <NUM> and the flip-flop <NUM>. Further, the logic circuit <NUM> outputs the signal DZI which is a 1st bit of the thermometer code obtained by sampling based on the clock I, as the output signal DOI[<NUM>] (the 1st bit of the output signal DOI) via the buffer <NUM> and the flip-flop <NUM>.

Similarly, the logic circuit <NUM> outputs, an operation result in which a logical product operation is performed by the AND gate <NUM> on an inverted signal of the signal DHIX which is a 2nd bit of a thermometer code obtained by sampling based on the clock IX and the signal DLIX which is a 0th bit thereof, as the output signal DOIX[<NUM>] (the 0th bit of the output signal DOIX) via the selector <NUM> and the flip-flop <NUM>. Further, the logic circuit <NUM> outputs the signal DZIX which is a 1st bit of the thermometer code obtained by sampling based on the clock IX, as the output signal DOIX[<NUM>] (the 1st bit of the output signal DOIX) via the buffer <NUM> and the flip-flop <NUM>.

In this manner, the logic circuit <NUM> operates as the decoder for the <NUM>-valued PAM4 signal, gray encodes a <NUM>-bit thermometer code to be inputted, and converts it into a <NUM>-bit gray code to output the <NUM>-bit gray code as illustrated in <FIG> when the control signal CTL is "<NUM>", namely when operating as the PAM4 reception circuit. That is, the logic circuit <NUM> converts thermometer codes of "<NUM>", "<NUM>", "<NUM>", and "<NUM>" to be inputted into <NUM>-bit data of "<NUM>", "<NUM>", "<NUM>", and "<NUM>" respectively, and outputs the <NUM>-bit data.

Note that in this embodiment, an example in which a <NUM>-bit thermometer code is converted into a <NUM>-bit gray code and it is outputted is given, but this is not restrictive, and a configuration in which the <NUM>-bit thermometer code is converted into a <NUM>-bit binary code and it is outputted is also applicable. However, in a case of conversion into the <NUM>-bit gray code and an output thereof, only one bit changes between the thermometer code of "<NUM>" and the thermometer code of "<NUM>", and therefore it is possible to reduce a bit error due to a determination error by the comparators <NUM>-Z0 and <NUM>-Z1 which output the signals DZI and DZIX.

Further, the logic circuit <NUM> configured as illustrated in <FIG> operates as the selector of the one-tap DFE in the NRZ reception circuit as follows when the control signal CTL is "<NUM>", namely when operating as the NRZ reception circuit. For example, in the logic circuit <NUM>, the selector <NUM> selects the signal DHI as long as the one before output signal DOI[<NUM>] which is an output before <NUM> UI and is outputted from the flip-flop <NUM> is "<NUM>", and the signal DHI selected by the selector <NUM> is outputted as the output signal DOI[<NUM>] via the selector <NUM> and the flip-flop <NUM>. In the logic circuit <NUM>, the selector <NUM> selects the signal DLI as long as the one before output signal DOI[<NUM>] which is an output before <NUM> UI and is outputted from the flip-flop <NUM> is "<NUM>", and the signal DLI selected by the selector <NUM> is outputted as the output signal DOI[<NUM>] via the selector <NUM> and the flip-flop <NUM>.

Similarly, in the logic circuit <NUM>, the selector <NUM> selects the signal DHIX as long as the output of the selector <NUM> which is an output before <NUM> UI is "<NUM>", and the signal DHIX selected by the selector <NUM> is outputted as the output signal DOIX[<NUM>] via the selector <NUM> and the flip-flop <NUM>. In the logic circuit <NUM>, the selector <NUM> selects the signal DLIX as long as the output of the selector <NUM> which is an output before <NUM> UI is "<NUM>", and the signal DLIX selected by the selector <NUM> is outputted as the output signal DOIX[<NUM>] via the selector <NUM> and the flip-flop <NUM>.

In this manner, the logic circuit <NUM> operates as the selector of the one-tap DFE which selects either of outputs of two comparator circuits (comparators) based on a determination result before <NUM> UI in the NRZ reception circuit, and switches a signal to be outputted according to data before <NUM> UI when the control signal CTL is "<NUM>", namely when operating as the NRZ reception circuit. Note that the output signals DOI[<NUM>] and DOIX[<NUM>] do not have significant information when the control signal CTL is "<NUM>", namely when operating as the NRZ reception circuit, and therefore, for example, they may be processed as invalid bits in a circuit in a subsequent stage, or the like.

According to this embodiment, comparator circuits <NUM> which are used for reception of the <NUM>-valued PAM4 signal are used for reception of the binary NRZ signal, and in addition, an operation of the logic circuit <NUM> is switched according to whether to receive the <NUM>-valued PAM4 signal or to receive the binary NRZ signal, and the function of the PAM4 decoder is achieved by the logic circuit <NUM> in a case of receiving the <NUM>-valued PAM4 signal and the function of the selector of the one-tap DFE is achieved by the logic circuit <NUM> in a case of receiving the binary NRZ signal. This makes it possible to perform an operation as the NRZ reception circuit of the one-tap DFE almost without increasing a circuit scale with the PAM4 reception circuit which receives the <NUM>-valued PAM4 signal being a basic configuration.

For example, when a reception situation in a case of the operation as the PAM4 reception circuit is not good, such control as improves a reception characteristic by switching to the NRZ signal is enabled even though a data rate is halved. Further, in a case of the operation as the NRZ reception circuit, compensation ability according to a signal loss of a transmission path improves by mounting the one-tap DFE, and for example, it is possible to greatly improve a limit (in a Nyquist frequency) of a size of a loss from about <NUM> dB to about <NUM> dB.

Note that the example of the reception circuit capable of treating the binary NRZ signal and the <NUM>-valued PAM4 signal is given, but the embodiments are not limited to this. Changing the number of comparator circuits, or the like according to a pulse amplitude modulation signal to be received makes it possible to also apply to a combination of other pulse amplitude modulation signals in which the number of possible values is different from each other. A symbol rate of a signal to be received is not particularly prescribed, and may be different or the same in a processable range for the symbol rate according to a modulation method.

<FIG> is a diagram illustrating a configuration example of a semiconductor integrated circuit in this embodiment. A semiconductor integrated circuit <NUM> in this embodiment includes a reception circuit <NUM> including a function of a deserializer circuit which converts an input serial signal such as the binary NRZ signal or the <NUM>-valued PAM4 signal into a parallel signal, and an internal circuit <NUM> such as a logic circuit which receives the parallel signal (data) from the reception circuit <NUM> and performs a processing operation.

The reception circuit <NUM> includes a front end unit <NUM>, a logic unit <NUM>, and a clock generating unit <NUM>. The front end unit <NUM> includes a differential amplifier circuit <NUM>, a comparator circuit <NUM>, and a demultiplexer <NUM>. The differential amplifier circuit <NUM> receives differential input serial signals RXIN and RXINX transmitted via transmission paths or the like. The comparator circuit <NUM> includes, for example, the comparator circuits <NUM>, the timing aligner <NUM>, and the logic circuit (PAM4 decoder/DFE selector) <NUM> which are illustrated in <FIG>, and determines values (data) of the input serial signals. The demultiplexer <NUM> performs a serial-parallel conversion with respect to an output of the comparator circuit <NUM>, outputs as a parallel signal RXOUT, and outputs a reception data clock RXCLKO.

The logic unit <NUM> includes a clock data recovery logic circuit <NUM> and an equalizer logic circuit <NUM>. The clock data recovery logic circuit <NUM> controls a phase of a clock signal which the clock generating unit <NUM> outputs based on a received signal. The equalizer logic circuit <NUM> performs control related to the comparator circuit <NUM>, controls a threshold (determination level, comparison reference voltage) in each of the comparators <NUM> of the comparator circuit <NUM>, and outputs an enable signal to control the operation or the stop of the comparators <NUM>, for example. Note that part or all of a function of controlling the threshold (determination level, comparison reference voltage) in each of the comparators <NUM> of the comparator circuit <NUM> and a function of outputting the enable signal to control the operation or the stop of the comparators <NUM> may be provided outside the reception circuit <NUM>.

The comparator circuit <NUM> performs sampling of the input serial signal at an appropriate timing using the clock signal which the clock generating unit <NUM> outputs. The comparator circuit <NUM> and the equalizer logic circuit <NUM> of the reception circuit <NUM> are controlled by the control signal CTL, and, for example, control of an operation mode with respect to the logic circuit <NUM> which the comparator circuit <NUM> includes is performed. Note that the control signal CTL may be a fixed signal which is supplied from the outside, or a signal which an adaptive controlling logic circuit which determinates a reception situation of data and switches the operation mode (modulation method), such as an autonegotiation function, or the like outputs. The parallel signal RXOUT to be outputted from the reception circuit <NUM> is taken in the internal circuit <NUM> by a flip-flop <NUM> which operates with the reception data clock RXCLKO, and processing or the like is performed.

Note that the above embodiments merely illustrate concrete examples of implementing the present invention, and the technical scope of the present invention is not to be construed in a restrictive manner by these embodiments. That is, the present invention may be implemented in various forms without departing from the scope of the claims.

Claim 1:
A reception circuit comprising:
a determination circuit (<NUM>) including:
a first number of first comparator circuits (<NUM>-H0, <NUM>-Z0, <NUM>-L0) configured to perform determination of a level of a received signal on the basis of a first clock signal among four clock signals having different phases and output first determination signals; and
the first number of second comparator circuits (<NUM>-H1, <NUM>-Z1, <NUM>-L1) configured to perform determination of a level of the received signal on the basis of a second clock signal among the four clock signals, wherein the phase difference between the first and second clock signals is <NUM> degrees, and output second determination signals, the determination circuit (<NUM>) being configured to perform determination by using the first number of the first comparator circuits (<NUM>-H0, <NUM>-Z0, <NUM>-L0) and the first number of the second comparator circuits (<NUM>-H1, <NUM>-Z1, <NUM>-L1) when the received signal is a first signal which is a multi-valued signal, and configured to perform determination by using a second number of the first comparator circuits (<NUM>-H0, <NUM>-Z0, <NUM>-L0) and the second number of the second comparator circuits (<NUM>-H1, <NUM>-Z1, <NUM>-L1), the second number being two or more and smaller than the first number, when the received signal is a second signal, a number of possible values of the second signal being smaller than a number of possible values of the first signal;
a timing aligner circuit (<NUM>) configured to synchronize the first determination signals and the second determination signals with one of the four clock signals and output first synchronized determination signals corresponding to the first determination signals and second synchronized determination signals corresponding to the second determination signals; and
a logic circuit (<NUM>) configured to generate digital signals based on the first and second synchronized determination signals, the logic circuit (<NUM>) being configured to operate as a decoder which decodes the first and second synchronized determination signals and generates the digital signals when the received signal is the first signal, and configured to operate as a selector which selects one of the first synchronized determination signals and one of the second synchronized determination signals and generates the digital signals when the received signal is the second signal.