Patent Description:
A photonic integrated circuit (PIC) can produce light or receive light. For example, a PIC can receive electrical power and can produce laser light at a specified wavelength in response to the received electrical power. The electrical power can optionally have a time-varying current or voltage, such as to encode a data signal onto the produced laser light. In another example, a PIC can receive light at a specified wavelength, can direct the received light onto a sensor, and can produce a current or voltage in response to the received light. The received light can optionally have a time-varying power level, such as corresponding to an encoded data signal on the received light, such that the PIC can produce a time-varying current or voltage that corresponds to the encoded data signal.

The PIC can operate within an optical circuit. For example, light can be coupled from the PIC into a fiber or can be coupled from a fiber into the PIC. Efficient coupling (e.g., coupling that includes an optical loss at or below a specified level) can involve relatively tight mechanical tolerances. For example, there may be relatively tight positional and/or angular tolerances on the PIC, on a fiber connector, and/or on any intervening optical elements between the PIC and the fiber connector.

There is ongoing effort to achieve efficient coupling between the PIC and the fiber. It is desired to have an optical circuit that addresses these concerns, and other technical challenges. <CIT> disclosed an optical circuit according to the preamble of claim <NUM>. <CIT> discloses a similar optical circuit.

The present invention provides an optical circuit according to claim <NUM>. The dependent claims relate to special embodiments thereof.

An optical circuit can include a photonic integrated circuit (PIC) attached to a substrate. The substrate can include an optical path that extends through the substrate, the optical path corresponding to a three-dimensional pathway over which the substrate can deliver light to or from the PIC. The substrate can direct an optical beam along the optical path to or from the PIC, such as to direct the optical beam to or from an optical connector (such as to or from an optical fiber). The substrate can optionally include optical elements formed integrally with the substrate, such as, mirrors, and/or isolators. The optical elements can be formed along the optical path using wafer-level techniques, such as photolithography, so that the substrate can deliver or receive the optical beam at an optical port without performing individual alignment of any optical elements on each optical path. The PIC can attach to the substrate using alignment techniques that are precise enough so that the PIC can be placed passively and can operate on a wafer level. The PIC can attach to the substrate using surface tension self-alignment features to achieve alignment in a lateral plane (such as a plane generally parallel to a plane of the substrate) and using contact between a reference surface on the PIC and a reference surface of the substrate to achieve alignment in a direction orthogonal to the lateral plane. The self-alignment features may not be used for electrical connectivity between elements. The surface tension self-alignment features and the reference surfaces can typically achieve positional alignment in all three dimensions to within a fraction of a wavelength of light that is produced or received by the PIC. Such positional tolerances are typically sufficient to allow passive placement of the PIC with respect to the optical path in the substrate. Compared to an assembly technique in which the PIC is actively placed, such as by a robotically controlled pick-and-place machine, the surface tension self-alignment features and the reference surfaces can provide greater precision and can operate on a wafer level, which can provide an economy of scale and can result in cost savings over a pick-and-place technique or other alignment technique that addresses each optical circuit individually.

The above general description is intended merely to provide an overview of the detailed description that follows. The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.

<FIG> shows a side view of an example of an optical circuit <NUM> prior to assembly, in accordance with some embodiments. The optical circuit <NUM> can include a substrate <NUM>, a photonic integrated circuit (PIC) <NUM> that is attachable to the substrate <NUM>, and one or more optional integrated circuits <NUM>, <NUM> that can electrically connect to electrical connections on the PIC <NUM> and/or electrical connections on the substrate <NUM>. The substrate <NUM>, the PIC <NUM>, and the optional integrated circuits <NUM>, <NUM> are shown in <FIG> as being separated from one another, prior to assembly of the completed optical circuit <NUM>. The configuration of <FIG> is but one example of an optical circuit <NUM>; other configurations can also be used.

The optical circuit <NUM> can include a substrate <NUM>. In some examples, the substrate <NUM> can be formed from a rigid material, such as for providing mechanical support for circuitry chips and other elements of the optical circuit <NUM>. In some examples, the substrate <NUM> can include one or more materials that are fully or at least partially transparent at one or more wavelengths. For example, the substrate <NUM> can be formed from silicon, glass, polycarbonate, or other suitable materials. In some examples, the substrate <NUM> can be formed from one or more materials that can be processed at a wafer level, such as by photolithography or other suitable techniques. Wafer-level processing techniques such as photolithography can allow placement of features on or within the substrate <NUM> with placement tolerances that can be significantly smaller than the wavelength. Further, the processing techniques can allow integration of additional optical components within or on the substrate <NUM>, such as, mirrors, and others. Examples of the additional optical components are discussed in detail below.

The substrate <NUM> can have a substrate front surface <NUM>. In some examples, the substrate front surface <NUM> can be referred to as a substrate top surface. It will be understood that designations such as "front" and "top" are but convenient descriptors for particular sides of the substrate <NUM>. For example, a substrate back surface may be located opposite the substrate front surface <NUM>, and a substrate bottom surface may be located opposite the substrate top surface. These descriptors are included merely for convenience and ease in reference, and do not imply an absolute direction to any of the described elements. such that the waveguide can extend to any specified volume within the substrate <NUM>.

The substrate <NUM> can define a cavity <NUM> that extends into the substrate front surface <NUM>. In some examples, the PIC <NUM> can be placed inside the cavity <NUM> during assembly of the optical circuit <NUM>. In some examples, the cavity <NUM> can be rectangular in cross-section, with the cross-section being taken in a plane that is parallel to the substrate front surface <NUM>. In some examples, the cavity <NUM> can be shaped such that corners in the cross-section can include rounded portions. Other cavity shapes can also be used.

The cavity <NUM> can have at least one sidewall <NUM>. In some examples, in which a perimeter of the cavity <NUM> is continuously curved (e.g., without sharp corners), the cavity <NUM> can include a single sidewall <NUM>. In some examples, in which the perimeter of the cavity <NUM> includes at least one corner, the cavity <NUM> can include a plurality of sidewalls <NUM>. The sidewalls <NUM> in the plurality can adjoin adjacent sidewalls <NUM> in the plurality at edges that extend from a top of the cavity <NUM> (e.g., at a plane of the front surface) toward a bottom of the cavity <NUM>. For simplicity, the discussion that follows assumes that a single sidewall <NUM> is present, although it will be understood that multiple sidewalls <NUM> can also be used.

The sidewall <NUM> includes a substrate optical port <NUM>. The substrate optical port <NUM> can align to a corresponding port on the PIC <NUM>, so that when the optical circuit <NUM> is assembled, light can propagate between the substrate <NUM> and the PIC <NUM> with relatively high efficiency (e.g., with a coupling loss that is less than or equal to a loss threshold, such as <NUM> dB, <NUM> dB, <NUM> dB, <NUM> dB, <NUM> dB, or other suitable value).

The substrate <NUM> includes an optical path <NUM> that extends through the substrate <NUM> from a connector optical port <NUM> to the substrate optical port <NUM>. In some examples, the optical path <NUM> can be formed as a volume within an elongated waveguide within the substrate <NUM>. For example, such a waveguide can be formed as an air-filled passage (having a refractive index close to unity) extending within the material of the substrate <NUM>, the material having a refractive index greater than that of the air-filled passage. As another example, the waveguide can be formed as a passage being filled with a solid material (such as glass) having a refractive index less than that of the substrate <NUM> (such as silicon). The waveguide can optionally include bends,.

The optical path <NUM> can include interactions with one or more optical components that can be formed integrally with the substrate <NUM>. Any or all of the optical components can be formed by techniques such as ion exchange, laser direct writing, etching, and others. The substrate <NUM> can includes a lens <NUM> integral with the substrate <NUM>. The lens <NUM> collimates a beam emitted from the PIC <NUM> along the PIC optical axis when the PIC <NUM> is attached to the substrate <NUM>. The lens <NUM> focuses a beam directed toward the PIC <NUM> along the PIC optical axis when the PIC <NUM> is attached to the substrate <NUM>. As another example, the substrate <NUM> can include an isolator <NUM> integral with the substrate <NUM>. In some examples, when the PIC <NUM> is attached to the substrate <NUM>, the isolator <NUM> can pass light that travels in a first direction along the optical path <NUM> and can block light that travels in a second direction opposite in the first direction along the optical path <NUM>. As another example, the substrate <NUM> can include a mirror <NUM> integral with the substrate <NUM>. The mirror <NUM> can reflect light along the optical path <NUM> within the substrate <NUM>. Because the optical components can be formed integrally with the substrate <NUM> (e.g., such as by using semiconductor processes, such as photolithography), the optical components can be formed and located in high volumes (such as, as a wafer level) and can be formed and located with relatively high precision. For example, the location tolerances for photolithography-based features can be tighter than for comparable pick-and-place features. In other words, by forming the optical components at a wafer-level, the optical components can be manufactured more precisely and less costly than comparable components that are manufactured separately and are mechanically (e.g., robotically) placed. The , isolator and mirror are but two examples of optical components that can be integral with the substrate <NUM>; other suitable components can also be used.

The optical circuit <NUM> can include a photonic integrated circuit (PIC) <NUM> that is attachable to the substrate <NUM>. In <FIG>, the PIC <NUM> is shown as being separate from the substrate <NUM> and spaced apart from the substrate <NUM>. During assembly of the optical circuit <NUM>, the PIC <NUM> is placed into the cavity <NUM> in the substrate <NUM>, the PIC <NUM> self-aligns to the substrate <NUM> (using a self-alignment technique discussed in detail below), and the PIC <NUM> is fastened in place with respect to the substrate <NUM>. Because the self-alignment technique is relatively robust and provides alignment precision that is typically a fraction of the wavelength of light used by the PIC <NUM>, the optical elements in the optical path <NUM> can be included with the substrate <NUM>, so that the PIC <NUM> can lack additional optical elements. For example, the PIC <NUM> can lack a lens, an isolator, a mirror, and/or other optical elements.

The PIC <NUM> has a PIC front surface <NUM> that includes a plurality of electrical connections <NUM>. When the PIC <NUM> is positioned in the cavity <NUM>, the PIC front surface <NUM> can be roughly coplanar with the substrate front surface <NUM>. Such rough coplanarity can be sufficient for establishing electrical connections <NUM> but may optionally be less precise than the alignment required for the optical path <NUM>.

The PIC <NUM> has a PIC back surface <NUM>, opposite the PIC front surface <NUM>. The PIC back surface <NUM> can optionally lack electrical connections. The PIC back surface <NUM> can be used to help dissipate heat generated by the PIC <NUM> (described below with regard to <FIG>).

The PIC <NUM> has a PIC edge surface <NUM> that extends around at least a portion of a perimeter of the PIC <NUM> between the PIC front surface <NUM> and the PIC back surface <NUM>. In <FIG>, the PIC edge surface <NUM> is shown as being orthogonal to the PIC front surface <NUM> and/or orthogonal to the PIC back surface <NUM>. The PIC edge surface <NUM> can alternatively include one or more inclined portions, curved portions, steps, and/or ridges. In a specific example, the perimeter of the PIC <NUM> can be rectangular or substantially rectangular, and PIC edge surface <NUM> can include four portions that each extend along a respective side of the rectangle. Other configurations can also be used.

The PIC <NUM> has a PIC optical port <NUM> disposed on the PIC edge surface <NUM>. The PIC optical port <NUM> can accept or emit an optical beam along a PIC optical axis. The PIC optical axis is aligned with the substrate optical port <NUM> when the PIC <NUM> is attached to the substrate <NUM>. The optical beam can be collimated, diverging, or converging as it passes through the PIC optical port <NUM>. The PIC optical port <NUM> can be formed using wafer-level techniques, such as photolithography, such that the location of the PIC optical port <NUM> can be controlled relatively precisely with respect to the self-alignment features, discussed below.

The PIC back surface <NUM> includes a first plurality of surface tension self-alignment features <NUM>. The bottom of the cavity <NUM> includes a second plurality of surface tension self-alignment features <NUM> having locations that correspond to the first plurality of surface tension self-alignment features <NUM>. The first plurality of surface tension self-alignment features <NUM> can self-align via surface tension to the second plurality of surface tension self-alignment features <NUM> when the first plurality of surface tension self-alignment features <NUM> is placed in contact with the second plurality of surface tension self-alignment features <NUM>. The first plurality of surface tension self-alignment features <NUM> and the second plurality of surface tension self-alignment features <NUM> may not be used for electrical connectivity between the PIC <NUM> and the substrate <NUM>.

The first plurality of surface tension self-alignment features <NUM> and the second plurality of surface tension self-alignment features <NUM> can be in a liquid state under a specified physical condition. For example, some or all of the surface tension self-alignment features can be delivered in a solid state, then heated to melt the surface tension self-alignment features. As another example, some or all of the surface tension self-alignment features can be delivered in a liquid state, to remain in the liquid state during self-alignment. As still another example, some or all of the surface tension self-alignment features can be delivered in a liquid state, cooled to a solid state, and melted to return to the liquid state during self-alignment.

The first plurality of surface tension self-alignment features <NUM> can self-align via surface tension to the second plurality of surface tension self-alignment features <NUM> when the first plurality of surface tension self-alignment features <NUM> and the second plurality of surface tension self-alignment features <NUM> are in the liquid state. The first plurality of surface tension self-alignment features <NUM> and the second plurality of surface tension self-alignment features <NUM> can align the PIC <NUM> to the substrate <NUM> in a plane that is parallel to the substrate reference surface (described below), such as the X-Y plane shown in <FIG>. Such self-alignment is discussed in greater detail below with respect to <FIG>.

The PIC <NUM> includes a PIC reference surface <NUM> that lacks surface tension self-alignment features. In some examples, the PIC reference surface <NUM> can include an area of the PIC back surface <NUM> that lacks surface tension self-alignment features. In some examples, the PIC reference surface <NUM> can be separate from the PIC back surface <NUM>. In some examples, the PIC reference surface <NUM> can extend around at least a portion of a perimeter of the PIC <NUM>. The PIC reference surface <NUM> can be formed using wafer-level techniques, such as photolithography, such that the location of the PIC reference surface <NUM> can be controlled relatively precisely with respect to the PIC optical port <NUM> and the surface tension self-alignment features, discussed below.

The substrate <NUM> includes a substrate reference surface <NUM> that lacks surface tension self-alignment features. In some examples, the substrate reference surface <NUM> can include a portion of a bottom of the cavity <NUM>. In some examples, the substrate reference surface <NUM> can include a ledge or a ridge that extends around a perimeter of a bottom of the cavity <NUM>. The substrate reference surface <NUM> can be formed using wafer-level techniques, such as photolithography, such that the location of the substrate reference surface <NUM> can be controlled relatively precisely with respect to the substrate optical port <NUM> and the self-alignment features, discussed below.

The PIC reference surface <NUM> can contact the substrate reference surface <NUM> to align the PIC <NUM> to the substrate <NUM> along a direction that is orthogonal to the substrate reference surface <NUM>, such as the Z-direction shown in <FIG>. When this Z-alignment is combined with the X-Y alignment provided by the surface tension self-aligning features, the PIC <NUM> can be aligned in three dimensions (e.g., X, Y, and Z) to within a fraction of a wavelength of light used by the PIC <NUM>. Such alignment can be precise enough to passively position the PIC optical port <NUM> with respect to the substrate optical port <NUM>, without using additional alignment for each device to improve the coupling efficiency between the PIC <NUM> and the substrate <NUM>.

<FIG> shows a side view of an example of the optical circuit <NUM> of <FIG>, after the PIC <NUM> has been attached to the substrate <NUM>, in accordance with some embodiments.

As described above, the PIC <NUM> and the substrate <NUM> have achieved alignment in the X-Y plane via the surface tension self-alignment features <NUM>, <NUM>. The PIC <NUM> and the substrate <NUM> have achieved alignment in the X-direction via the contacting reference surfaces <NUM>, <NUM>. The surface tension self-alignment features <NUM>, <NUM> and the contacting reference surfaces <NUM>, <NUM> can perform their alignments with enough precision such that no additional (e.g., unit-by-unit) adjustment of position may be needed to achieve sufficiently low loss (e.g., below a specified loss threshold) in the coupling of light between the PIC <NUM> and the substrate <NUM>.

To further reduce loss in the coupling of light between the PIC <NUM> and the substrate <NUM>, an index-matching material <NUM> can be disposed between the PIC edge surface <NUM> and the at least one sidewall <NUM> of the cavity <NUM>. The index-matching material <NUM> can reduce reflections and/or scattering at an interface between the PIC <NUM> and the substrate <NUM>. The index-matching material <NUM> can optionally have a refractive index that lies between a refractive index of a core of the light guide along the optical path <NUM> in the substrate <NUM> and a refractive index of a core of the light guide in the PIC <NUM>, inclusively. In some examples, the index-matching material <NUM> can be injected as a liquid in the cavity <NUM>, in the volume between the PIC <NUM> and the sidewall <NUM>. In some examples, the index-matching material <NUM> can be deposited at the interface between the contacting reference surfaces <NUM>, <NUM>, such that capillary action can move the contacting reference surfaces <NUM>, <NUM> to a portion of the cavity <NUM> between the PIC edge surface <NUM> and the at least one sidewall <NUM> of the cavity <NUM>. In some examples, the index-matching material <NUM> can be cured, such as by ultraviolet light, to change the index-matching material <NUM> from a liquid to a solid. Other configurations can also be used.

Because the PIC back surface <NUM> can be accessible to the substrate <NUM>, the optical circuit <NUM> can use the PIC back surface <NUM> to help dissipate heat from the PIC <NUM>. For example, the substrate <NUM> can include a substrate back surface <NUM> opposite the substrate front surface <NUM>. The substrate <NUM> can include at least one aperture <NUM> extending from the substrate back surface <NUM> to the bottom of the cavity <NUM>. In some examples, the at least one aperture <NUM> can include a central aperture that includes a central portion of the bottom of the cavity <NUM>. At least one thermal connection <NUM> (such as a wire or at least a portion of a metal heat sink) can be disposed in and can extend through the at least one aperture <NUM>. The at least one thermal connection <NUM> can include at least one material (such as a metal) having a greater thermal conductivity than a thermal conductivity of the substrate <NUM>. The at least one thermal connection <NUM> can thermally contact the PIC back surface <NUM> and can direct heat away from the PIC <NUM>.

<FIG> shows a side view of an example of the optical circuit <NUM> of <FIG> and <FIG>, after at least one integrated circuit has electrically connected to the plurality of electrical connections <NUM> on the PIC <NUM>, in accordance with some embodiments.

An integrated circuit <NUM> has electrical connections <NUM> that can electrically connect to the plurality of electrical connections <NUM> on the PIC <NUM> and electrically connect to a second plurality of electrical connections (not shown) on the substrate front surface <NUM>. The electrical connections <NUM> can include balls or volumes of solder that are placed on each chip. The solder volumes are either liquid or are liquified by heating or another liquifying technique. When in liquid form, the solder volumes form their electrical connections between the chips. The solder volumes can then be solidified by allowing the solder volumes to cool or another solidifying technique.

In the example of <FIG>, a second integrated circuit <NUM> has electrical connections <NUM> that can electrically connect to the substrate <NUM>. The second integrated circuit <NUM> can optionally connect to the integrated circuit <NUM> via one or more electrical connections <NUM> that extend in the substrate <NUM> proximate the substrate front surface <NUM>. The second integrated circuit <NUM> can optionally connect via one or more electrical connections <NUM> to one or more electrical connections <NUM> on the substrate back surface <NUM>. The electrical connections <NUM> on the substrate back surface <NUM> can optionally be formed with a different pitch (e.g., spacing) and/or a different volume of the solder ball, such as a larger pitch and a larger solder ball volume, compared with electrical connections (not shown) on the substrate front surface <NUM>. Such a larger size and spacing can allow a less precise (and therefore less expensive) machine to position the substrate <NUM> as needed.

In the examples shown in <FIG>, the PIC <NUM> can interface directly with the substrate <NUM>. For example, the substrate <NUM> can be a package substrate, such as polymer package substrate. As an alternative to any or all of these examples, an interposer can be disposed between the PIC <NUM> and the substrate <NUM>. The interposer can include some or all of the electrical connections shown in the substrate <NUM> of <FIG>, and can attach to a substrate as needed. For the purposes of this document, the term substrate can include a package substrate, and can optionally include an interposer disposed between the package substrate and the PIC <NUM>.

<FIG> show a portion of the PIC <NUM> and a corresponding portion of the substrate <NUM> in various stages of alignment during assembly of the optical circuit <NUM>.

<FIG> shows a side view of a portion of the PIC <NUM> and a portion of the substrate <NUM>, before the PIC <NUM> has been mechanically positioned with respect to the substrate <NUM>, in accordance with some embodiments.

The PIC <NUM> includes the PIC reference surface <NUM> and the first plurality of surface tension self-alignment features <NUM>. The substrate <NUM> includes the substrate reference surface <NUM> and the second plurality of surface tension self-alignment features <NUM>.

<FIG> shows a side view of a portion of the PIC <NUM> and a portion of the substrate <NUM>, after the PIC <NUM> has been mechanically positioned with respect to the substrate <NUM>, in accordance with some embodiments.

The mechanical positioning can be performed by a pick-and-place assembling device or other suitable positioning device. The first plurality of surface tension self-alignment features <NUM> is misaligned with the second plurality of surface tension self-alignment features <NUM> by a distance Y1. The distance Y1 can be less than a diameter of the surface tension self-alignment features, so that each surface tension self-alignment feature in the first plurality can contact a corresponding surface tension self-alignment feature in the second plurality. In most cases, the distance Y1 can be too large to achieve a sufficient coupling efficiency between the PIC <NUM> and the substrate <NUM>.

<FIG> shows a side view of a portion of the PIC <NUM> and a portion of the substrate <NUM>, after the PIC <NUM> has self-aligned to the substrate <NUM> in three dimensions (e.g., X, Y, and Z), in accordance with some embodiments.

The first plurality of surface tension self-alignment features <NUM> has self-aligned to the second plurality of surface tension self-alignment features <NUM> to achieve alignment in the X-Y plane. After self-alignment in X-Y, the first plurality of surface tension self-alignment features <NUM> is misaligned with the second plurality of surface tension self-alignment features <NUM> by a distance Y2, which can be less than distance Y1. After self-alignment in Z, the PIC reference surface <NUM> is in contact with the substrate reference surface <NUM>. After the self-alignment, typical misalignments in X, Y, and Z can be less than <NUM>, and as small as <NUM> or smaller.

<FIG> show an example of a placement scheme for the surface tension self-alignment features.

<FIG> shows a bottom view of an example of a PIC back surface <NUM>, in accordance with some embodiments.

In some examples, the PIC <NUM> can have a polygonal, square, or rectangular footprint. The PIC back surface <NUM> can include PIC back surface corners. The first plurality of surface tension self-alignment features <NUM> can be located in a periphery of the PIC back surface <NUM> proximate the PIC back surface corners.

By positioning the first plurality of surface tension self-alignment features <NUM> at or near the corners of the PIC back surface <NUM>, the optical circuit <NUM> can achieve extremely tight tolerancing with respect to angle in the X-Y plane (e.g., with respect to rotation about the Z-axis). For example, if the positional misalignment of a self-alignment feature is <NUM>, and the PIC back surface <NUM> is <NUM> square, then an angular misalignment (about Z) can be about <NUM> degrees (or about <NUM> milliradians). If the positional misalignment is <NUM>, and the PIC back surface <NUM> is <NUM> square, then an angular misalignment (about Z) can be about <NUM> millidegree (or about <NUM> microradians).

<FIG> shows a top view of an example of a substrate front surface <NUM>, in accordance with some embodiments.

In some examples, the cavity <NUM> can include cavity corners. The second plurality of surface tension self-alignment features <NUM> can be located in a periphery of the cavity <NUM> proximate the cavity corners. During alignment, the PIC <NUM> can be placed with respect to the substrate <NUM> such that such that the first plurality of surface tension self-alignment features <NUM> contacts the second plurality of surface tension self-alignment features <NUM>.

In some examples, the bottom of the cavity <NUM> can optionally include recessed areas <NUM> around the second plurality of surface tension self-alignment features <NUM>. Such recessed areas <NUM> can help provide clearance around the reference surfaces <NUM>, <NUM>, so that the height (e.g., extent in the Z-direction) of the surface tension self-alignment features does not interfere with contact between the reference surfaces <NUM>, <NUM>. In some examples, each corner of the cavity <NUM> can have a corresponding recessed area <NUM> that surrounds the corresponding self-alignment features <NUM>. In some examples, the PIC back surface <NUM> can optionally include recessed areas that can surround the surface tension self-alignment features to help avoid interference between the reference surfaces <NUM>, <NUM>.

The bottom of the cavity <NUM> can include a first area. The substrate <NUM> can include a substrate back surface <NUM> opposite the substrate front surface <NUM>. The substrate <NUM> can include at least one aperture <NUM> extending from the substrate back surface <NUM> to the first area of the bottom of the cavity <NUM>. In some examples, the at least one aperture <NUM> can be a single aperture, such as in a central portion of the bottom of the cavity <NUM>. At least one thermal connection can be disposed in and can extend through the at least one aperture. The at least one thermal connection can include at least one material having a greater thermal conductivity than a thermal conductivity of the substrate <NUM>. The at least one thermal connection can thermally contact the PIC back surface <NUM> and can help dissipate heat generated by the PIC <NUM>.

<FIG> shows a flow chart of an example of a method <NUM> for assembling an optical circuit, in accordance with some embodiments. The method <NUM> can be executed to assemble the optical circuit <NUM> shown in <FIG>, or to assemble other suitable optical circuits. Other methods of assembly can also be used.

At operation <NUM>, a substrate can be provided. The substrate can have a substrate front surface. The substrate can define a cavity that extends into the substrate front surface. The cavity can have at least one sidewall that extends toward a bottom of the cavity. The bottom of the cavity can include a first plurality of surface tension self-alignment features. The cavity can include a substrate reference surface that lacks surface tension self-alignment features.

At operation <NUM>, a photonic integrated circuit (PIC) can be positioned within the cavity. The PIC can have a PIC front surface that includes a plurality of electrical connections. The PIC can have a PIC back surface. The PIC can have a second plurality of surface tension self-alignment features located on the PIC back surface. The PIC can have a PIC reference surface that lacks surface tension self-alignment features.

At operation <NUM>, the second plurality of surface tension self-alignment features can be automatically aligned to the first plurality of surface tension self-alignment features, via surface tension in the first and second pluralities of the surface tension self-alignment features, to align the PIC to the substrate in a plane that is parallel to the substrate reference surface.

At operation <NUM>, the PIC reference surface can contact against the substrate reference surface to align the PIC to the substrate in a direction that is orthogonal to the substrate reference surface, such that when the PIC is aligned to the substrate in the plane that is parallel to the substrate reference surface and in the direction that is orthogonal to the substrate reference surface, a PIC optical port disposed on the PIC is aligned to a substrate optical port disposed on the substrate.

<FIG> shows a system level diagram, depicting an example of an electronic device (e.g., system) that may include an optical circuit (such as <NUM>) and/or methods described above. In one embodiment, system <NUM> includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system <NUM> includes a system on a chip (SOC) system.

In one embodiment, processor <NUM> has one or more processor cores <NUM> and 1012N, where 1012N represents the Nth processor core inside processor <NUM> where N is a positive integer. In one embodiment, system <NUM> includes multiple processors including <NUM> and <NUM>, where processor <NUM> has logic similar or identical to the logic of processor <NUM>. In some embodiments, processing core <NUM> includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor <NUM> has a cache memory <NUM> to cache instructions and/or data for system <NUM>. Cache memory <NUM> may be organized into a hierarchal structure including one or more levels of cache memory.

In some embodiments, processor <NUM> includes a memory controller <NUM>, which is operable to perform functions that enable the processor <NUM> to access and communicate with memory <NUM> that includes a volatile memory <NUM> and/or a non-volatile memory <NUM>. In some embodiments, processor <NUM> is coupled with memory <NUM> and chipset <NUM>. Processor <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna <NUM> operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In some embodiments, volatile memory <NUM> includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory <NUM> includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

Memory <NUM> stores information and instructions to be executed by processor <NUM>. In one embodiment, memory <NUM> may also store temporary variables or other intermediate information while processor <NUM> is executing instructions. In the illustrated embodiment, chipset <NUM> connects with processor <NUM> via Point-to-Point (PtP or P-P) interfaces <NUM> and <NUM>. Chipset <NUM> enables processor <NUM> to connect to other elements in system <NUM>. In some embodiments of the example system, interfaces <NUM> and <NUM> operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In some embodiments, chipset <NUM> is operable to communicate with processor <NUM>, 1005N, display device <NUM>, and other devices, including a bus bridge <NUM>, a smart TV <NUM>, I/O devices <NUM>, nonvolatile memory <NUM>, a storage medium (such as one or more mass storage devices) <NUM>, a keyboard/mouse <NUM>, a network interface <NUM>, and various forms of consumer electronics <NUM> (such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset <NUM> couples with these devices through an interface <NUM>. Chipset <NUM> may also be coupled to a wireless antenna <NUM> to communicate with any device configured to transmit and/or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.

Chipset <NUM> connects to display device <NUM> via interface <NUM>. Display <NUM> may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor <NUM> and chipset <NUM> are merged into a single SOC. In addition, chipset <NUM> connects to one or more buses <NUM> and <NUM> that interconnect various system elements, such as I/O devices <NUM>, nonvolatile memory <NUM>, storage medium <NUM>, a keyboard/mouse <NUM>, and network interface <NUM>. Buses <NUM> and <NUM> may be interconnected together via a bus bridge <NUM>.

In one embodiment, mass storage device <NUM> includes, but is not limited to, a solid-state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface <NUM> is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE <NUM> standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

Claim 1:
An optical circuit (<NUM>), comprising:
a substrate (<NUM>) having a substrate front surface (<NUM>),
the substrate defining a cavity (<NUM>) that extends into the substrate front surface (<NUM>),
the cavity (<NUM>) having at least one sidewall (<NUM>),
the sidewall (<NUM>) including a substrate optical port (<NUM>),
the substrate (<NUM>) including an optical path (<NUM>) that extends through the substrate (<NUM>) from a connector optical port (<NUM>) to the substrate optical port (<NUM>); and
a photonic integrated circuit PIC (<NUM>), attachable to the substrate (<NUM>),
the PIC (<NUM>) having a PIC front surface (<NUM>) that includes a plurality of electrical connections (<NUM>),
the PIC (<NUM>) having a PIC back surface (<NUM>),
the PIC (<NUM>) having a PIC edge surface (<NUM>) that extends around at least a portion of a perimeter of the PIC between the PIC (<NUM>) front surface (<NUM>) and the PIC back surface (<NUM>),
the PIC (<NUM>) having a PIC optical port (<NUM>) disposed on the PIC edge surface (<NUM>) and configured to accept or emit an optical beam along a PIC optical axis,
the PIC optical axis being aligned with the substrate optical port (<NUM>) when the PIC (<NUM>) is attached to the substrate (<NUM>), characterized in that the substrate (<NUM>) includes a lens (<NUM>) integral with the substrate (<NUM>), the lens (<NUM>) configured to collimate a beam emitted from the PIC (<NUM>) along the PIC optical axis when the PIC (<NUM>) is attached to the substrate (<NUM>) or focus a beam directed toward the PIC (<NUM>) along the PIC optical axis when the PIC (<NUM>) is attached to the substrate (<NUM>).