Patent Description:
Numerous embodiments for tuning cells within an analog neuromorphic memory used in an artificial neural network are disclosed.

Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) which are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. <FIG> illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of major challenges in the development of artificial neural networks for highperformance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>. The non-volatile memory arrays operate as analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs.

Each non-volatile memory cells used in the analog neuromorphic must be erased and programmed to hold a very specific and precise amount of charge in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include <NUM>, <NUM>, and <NUM>. The prior art lacks a fast and accurate mechanism for tuning each cell to ensure that the cell contains the desired amount of charge.

What is needed are improved mechanisms and algorithms for tuning an analog neuromorphic memory used in artificial neural networks. <CIT> discloses that non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell threshold level is then verified by applying a 'gate voltage corresponding to the selected threshold voltage to the NVM inverter. The output voltage of the NVM inverter in response to the applied level gate voltage is detected. When the output voltage of the NVM inverter is out of a predefined output voltage window for the selected threshold voltage level, a fine-tuning programming sequence is applied to the NVM cell until the threshold voltage of the NVM cell is inside the correspondent threshold voltage window. This verification and adjustment scheme for a MLC NVM allows the threshold voltage of the multi-level NVM cells for any specific level to be controlled to a desired accuracy. <CIT> discloses that a system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated.

The present invention is defined in appended independent method for programming claim <NUM> to which reference should be made.

Digital non-volatile memories are well known. For example, <CIT> ("the '<NUM> patent") discloses an array of split gate non-volatile memory cells. The memory cell is shown in <FIG>. Each memory cell <NUM> includes source and drain regions <NUM>/<NUM> formed in a semiconductor substrate <NUM>, with a channel region <NUM> there between. A floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the drain region <NUM>. A control gate <NUM> has a first portion 22a that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion 22b that extends up and over the floating gate <NUM>. The floating gate <NUM> and control gate <NUM> are insulated from the substrate <NUM> by a gate oxide <NUM>.

The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the control gate <NUM>, which causes electrons on the floating gate <NUM> to tunnel through the intermediate insulation <NUM> from the floating gate <NUM> to the control gate <NUM> via Fowler-Nordheim tunneling.

The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the control gate <NUM>, and a positive voltage on the drain <NUM>. Electron current will flow from the source <NUM> towards the drain <NUM>. The electrons will accelerate and become heated when they reach the gap between the control gate <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide <NUM> onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

The memory cell is read by placing positive read voltages on the drain <NUM> and control gate <NUM> (which turns on the channel region under the control gate). If the floating gate <NUM> is positively charged (i.e. erased of electrons and positively coupled to the drain <NUM>), then the portion of the channel region under the floating gate <NUM> is turned on as well, and current will flow across the channel region <NUM>, which is sensed as the erased or "<NUM>" state.

The architecture of the prior art memory array is shown in <FIG>. The memory cells <NUM> are arranged in rows and columns. In each column, the memory cells are arranged end to end in mirror fashion, so that they are formed as pairs of memory cells each sharing a common source region <NUM> (S), and each adjacent set of memory cell pairs sharing a common drain region <NUM> (D). All the source regions <NUM> for any given row of memory cells are electrically connected together by a source line 14a. All the drain regions <NUM> for any given column of memory cells are electrically connected together by a bit line 16a. All the control gates <NUM> for any given row of memory cells are electrically connected together by a control gate line 22a. Therefore, while the memory cells can be individually programmed and read, memory cell erasure is performed row by row (each row of memory cells is erased together, by the application of a high voltage on the control gate line 22a). If a particular memory cell is to be erased, all the memory cells in the same row are also erased.

Those skilled in the art understand that the source and drain can be interchangeable, where the floating gate can extend partially over the source instead of the drain, as shown in <FIG> (two-gate memory cell). <FIG> best illustrates the corresponding memory cell architecture, including the memory cells <NUM>, the source lines 14a, the bit lines 16a, and the control gate lines 22a. As is evident from the figures, memory cells <NUM> of the same row share the same source line 14a and the same control gate line 22a, while the drain regions of all cells of the same column are electrically connected to the same bit line 16a. The array design is optimized for digital applications, and permits individual programming of the selected cells, e.g., by applying <NUM> V and <NUM> V to the selected control gate line 22a and source line 14a, respectively, and grounding the selected bit line 16a. Disturbing the non-selected memory cell in the same pair is avoided by applying a voltage greater than <NUM> volts on the unselected bit lines 16a and grounding the remaining lines. The memory cells <NUM> cannot be erased individually because the process responsible for erasure (the Fowler-Nordheim tunneling of electrons from the floating gate <NUM> to the control gate <NUM>) is only weakly affected by the drain voltage (i.e., the only voltage which may be different for two adjacent cells in the row direction sharing the same source line 14a).

Split gate memory cells having more than two gates are also known. For example, four-gate memory cells have source region <NUM>, drain region <NUM>, floating gate <NUM> over a first portion of channel region <NUM>, a select gate <NUM> over a second portion of the channel region <NUM>, a control gate <NUM> over the floating gate <NUM>, and an erase gate <NUM> over the source region <NUM> are known, as shown in <FIG> (see for example <CIT>). Programming is shown by heated electrons from the channel region <NUM> injecting themselves onto the floating gate <NUM>. Erasing is shown by electrons tunneling from the floating gate <NUM> to the erase gate <NUM>.

Another type of prior art split gate three-gate memory cell is shown in <FIG>. The split gate memory cell of <FIG> is identical to the split gate memory cell of <FIG> except that it does not have a separate control gate. The erase operation (erasing through erase gate) and read operation are similar to that of the <FIG> except there is no control gate bias. The programming operation also is done without the control gate bias, hence the program voltage on the source line is higher to compensate for lack of control gate bias.

Table No. <NUM> depicts typical voltage ranges that can be applied to the four terminals for performing read, erase, and program operations:.

The architecture for a four-gate memory cell array can be configured as shown in <FIG>. In this embodiment, each horizontal select gate line 28a electrically connects together all the select gates <NUM> for that row of memory cells. Each horizontal control gate line 22a electrically connects together all the control gates <NUM> for that row of memory cells. Each horizontal source line 14a electrically connects together all the source regions <NUM> for two rows of memory cells that share the source regions <NUM>. Each bit line 16a electrically connects together all the drain regions <NUM> for that column of memory cells. Each erase gate line 30a electrically connects together all the erase gates <NUM> for two rows of memory cells that share the erase gate <NUM>. As with the previous architecture, individual memory cells can be independently programmed and read. However, there is no way to erase cells individually. Erasing is performed by placing a high positive voltage on the erase gate line 30a, which results in the simultaneous erasing of both rows of the memory cells that share the same erase gate line 30a. Exemplary operating voltages can include those in Table <NUM> below (in this embodiment, select gate lines 28a can be referred to as word lines WL):.

In order to utilize the memory arrays comprising one of the types of non-volatile memory cells described above, two modifications are made. First, the lines are reconfigured so that each memory cell can be individually programmed, erased and read without adversely affecting the memory state of other memory cells in the array, as further explained below. Specifically, the memory state (i.e. charge on the floating gate) of each memory cells in the array can be continuously changed from a fully erased state to a fully programmed state, and vice versa, independently and with minimal disturbance of other memory cells.

The neural network weight level assignments as stored in the memory cells can be evenly spaced as shown in <FIG>, or unevenly spaced as shown in <FIG>. Programming of the non-volatile memory cells can be implemented using a bidirectional tuning algorithm such as that shown in <FIG>. Icell is the read current of the target cell being programmed, and Itarget is the desired read current when the cell is ideally programmed. The target cell read current Icell is read (step <NUM>) and compared to the target read current Itarget (step <NUM>). If the target cell read current Icell is greater than the target read current Itarget, a programming tuning process is performed (step <NUM>) to increase the number of electrons on the floating gate (in which a look up table is used to determine the desired programming voltage VCG on the control gate) (steps 3a-3b), which can be repeated as necessary (step 3c). If the target cell read current Icell is less than the target read current Itarget, an erase tuning process is performed (step <NUM>) to decrease the number of electrons on the floating gate (in which a look up table is used to determine the desired erase voltage VEG on the erase gate) (steps 4a-4b), which can be repeated as necessary (step 4c). If a programming tuning process overshoots the target read current, then an erase tuning process is performed (step 3d and starting with step 4a), and vice versa (step 4d and starting with step 3a), until the target read current is achieved (within an acceptable delta value).

Programming of the non-volatile memory cells can instead be implemented using a unidirectional tuning algorithm using programming tuning. With this algorithm, the memory cell is initially fully erased, and then the programming tuning steps 3a-3c in <FIG> are performed until the read current of the target cell reaches the target threshold value. Alternately, the tuning of the non-volatile memory cells can be implemented using the unidirectional tuning algorithm using erasing tuning. In this approach, the memory cell is initially fully programmed, and then the erasing tuning steps 4a-4c in <FIG> are performed until the read current of the target cell reaches the target threshold value.

<FIG> is a diagram illustrating weight mapping using current comparison. The weight digital bits (e.g., <NUM>-bit weight for each synapsis, representing the target digital weight for the memory cell) are input to a digital-to-analog converter (DAC) <NUM>, which converts the bits to voltage Vout (e.g., <NUM> voltage levels - <NUM> bits). Vout is converted to a current Iout (e.g. <NUM> current levels - <NUM> bits) by voltage-to-current converter V/I Conv <NUM>. The current is supplied to a current comparator IComp <NUM>. Program or erase algorithm enabling are input to the memory cell <NUM> (for example, erase: incrementing EG voltage; or program: increment CG voltage). The memory cell current out Icellout (i.e. from a read operation) is supplied to the current comparator IComp <NUM>. The current comparator IComp <NUM> compares the memory cell current Icellout with the current Iout derived from the weight digital bits to produce a signal indicative of the weight stored in the memory cell <NUM>.

<FIG> is a diagram illustrating weight mapping using voltage comparison. The weight digital bits (e.g., <NUM>-bit weight for each synapsis) are input to a digital-to-analog converter (DAC) <NUM>, which converts the bits to voltage Vout (e.g., <NUM> voltage levels - <NUM> bits). Vout is supplied to a voltage comparator VComp <NUM>. Program or erase algorithm enabling are input to the memory cell <NUM> (for example, erase: incrementing EG voltage; or program: increment CG voltage). The memory cell current out Icellout is supplied to current-to-voltage converter I/V Conv <NUM> for conversion to a voltage V2out (e.g. <NUM> voltage levels - <NUM> bits). Voltage V2out is supplied to voltage comparator VComp <NUM>. The voltage comparator VComp <NUM> compares the voltages Vout and V2 out to produce a signal indicative of the weight stored in the memory cell <NUM>.

<FIG> conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses the non-volatile memory array neural net for a facial recognition application, but any other appropriate application could be implemented using a non-volatile memory array based neural network. S0 is the input, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from S0 to C1 have both different sets of weights and shared weights, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, whereby these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first neuron of CB1 for generating a pixel of one of the layers of feature map C1. The 3x3 filter is then shifted one pixel to the right (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, whereby they are multiplied by the same weights and a second single output value is determined by the associated neuron. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

At C1, in the present example, there are <NUM> feature maps, with 30x30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two dimensional array, and thus in this example the synapses CB1 constitutes <NUM> layers of two dimensional arrays (keeping in mind that the neuron layers and arrays referenced herein are logical relationships, not necessarily physical relationships - i.e., the arrays are not necessarily oriented in physical two dimensional arrays). Each of the <NUM> feature maps is generated by one of sixteen different sets of synapse weights applied to the filter scans.

An activation function P1 (pooling) is applied before going from C1 to S1, which pools values from consecutive, non-overlapping 2x2 regions in each feature map. The purpose of the pooling stage is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage. At S1, there are <NUM>15x15 feature maps (i.e., sixteen different arrays of 15x15 pixels each). The synapses and associated neurons in CB2 going from S1 to C2 scan maps in S1 with 4x4 filters, with a filter shift of <NUM> pixel. At C2, there are <NUM>12x12 feature maps. An activation function P2 (pooling) is applied before going from C2 to S2, which pools values from consecutive non-overlapping 2x2 regions in each feature map. At S2, there are <NUM>6x6 feature maps. An activation function is applied at the synapses CB3 going from S2 to C3, where every neuron in C3 connects to every map in S2. At C3, there are <NUM> neurons. The synapses CB4 going from C3 to the output S3 fully connects S3 to C3.

Each level of synapses is implemented using an array, or a portion of an array, of non-volatile memory cells. <FIG> is a block diagram of the vector-by-matrix multiplication (VMM) array that includes the non-volatile memory cells, and is utilized as the synapses between an input layer and the next layer. Specifically, the VMM <NUM> includes an array of non-volatile memory cells <NUM>, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the inputs for the memory array <NUM>. Source line decoder <NUM> in this example also decodes the output of the memory cell array. The memory array serves two purposes. First, it stores the weights that will be used by the VMM. Second, the memory array effectively multiplies the inputs by the weights stored in the memory array to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication function, the memory array negates the need for separate multiplication logic circuits and is also power efficient due to in-situ memory computation.

The output of the memory array is supplied to a differential summer (such as summing op-amp) <NUM>, which sums up the outputs of the memory cell array to create a single value for that convolution. The differential summer is such as to realize summation of positive weight and negative weight with positive input. The summed up output values are then supplied to the activation function circuit <NUM>, which rectifies the output. The activation function may include sigmoid, tanh, or ReLU functions. The rectified output values become an element of a feature map as the next layer (C1 in the description above for example), and are then applied to the next synapse to produce next feature map layer or final layer. Therefore, in this example, the memory array constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summing op-amp <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

<FIG> is a block diagram of the various levels of VMM. As shown in <FIG>, the input is converted from digital to analog by digital-to-analog converter <NUM>, and provided to input VMM 32a. The output generated by the input VMM 32a is provided as an input to the next VMM (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM (hidden level <NUM>) 32b, and so on. The various layers of VMM's <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM can be a stand-alone non-volatile memory array, or multiple VMMs could utilize different portions of the same non-volatile memory array, or multiple VMMs could utilize overlapping portions of the same non-volatile memory array.

<FIG> illustrates an array of four-gate memory cells (i.e., such as that shown in <FIG>) arranged as a drain summing matrix multiplier. The various gate and region lines for the array of <FIG> are the same as that in <FIG> (with the same element numbers for corresponding structure), except that the erase gate lines 30a run vertically instead of horizontally (i.e., each erase gate line 30a connects together all the erase gates <NUM> for that column of memory cells) so that each memory cell <NUM> can be independently programmed, erased and read. After each of the memory cells is programmed with the appropriate weight value for that cell, the array acts as a drain summing matrix multiplier. The matrix inputs are VinO. Vin7 and are placed on select gate lines 28a. The matrix of outputs Iout0. IoutN for the array of <FIG> are produced on the bit lines 16a. Each output Iout is a sum of the cell current I times the weight W stored in the cell, for all the cells in the column: <MAT>.

Each memory cell (or pair of memory cells) acts as a single synapse having a weight value expressed as output current Iout dictated by the sum of the weight values stored in the memory cell (or pair of memory cells) in that column. The output of any given synapse is in the form of current. Therefore, each subsequent VMM stage after the first stage preferably includes circuitry for converting incoming currents from the previous VMM stage into voltages to be used as the input voltages Vin. <FIG> illustrates an example of such current-to-voltage conversion circuitry, which is a modified row of memory cells that log converts the incoming currents Iin0. IinN into the input voltages VinO.

The memory cells described herein are biased in weak inversion, <MAT> <MAT> For the I-to-V log converter using a memory cell to convert input current into an input voltage: <MAT> For a memory array used as a vector matrix multiplier VMM, the output current is: <MAT> namely<MAT> <MAT>.

<FIG> and <FIG> illustrate another configuration of an array of four-gate memory cells (i.e., such as that shown in <FIG>) arranged as a drain summing matrix multiplier. The lines for the array of <FIG> and <FIG> are the same as that in the array of <FIG> and <FIG>, except that the source lines 14a run vertically instead of horizontally (i.e., each source line 14a connects together all the source regions <NUM> for that column of memory cells) and erase gate lines 30a run horizontally instead of vertically (i.e., each erase gate line 30a connects together all the erase gates <NUM> for that row of memory cell pairs), so that each memory cell can be independently programmed, erased and read. The matrix inputs VinO. VinN remain on select gate lines 28a, and the matrix outputs Iout0. IoutN remain on the bit lines 16a.

<FIG> illustrates another configuration of an array of four-gate memory cells (i.e., such as that shown in <FIG>) arranged as a gate coupling/source summing matrix multiplier. The lines for the array of <FIG> are the same as that in <FIG> and <FIG>, except that the select gate lines 28a run vertically and there are two of them for each column of memory cells. Specifically, each column of memory cells include two select gate lines: a first select gate line 28a1 connecting together all the select gates <NUM> of the odd row memory cells, and a second select gate line 28a2 connecting together all the select gates <NUM> of the even row memory cells.

The circuits at the top and bottom of <FIG> serve to log convert the input currents Iin0. IinN into the input voltages Vin0. The matrix inputs shown in this figure are VinO. Vin5 and are placed on the select gate lines 28a1 and 28a2. Specifically, input Vin0 is placed on the select line 28a1 for the odd cells in column <NUM>. Vin1 is placed on the select gate line 28a2 for the even cells in column <NUM>. Vin2 is placed on the select gate line 28a1 for the odd cells in column <NUM>. Vin3 is placed on the select gate line 28a2 for the even cells in column <NUM>, and so on. The matrix outputs Iout0. Iout3 are provided on the source lines 14a. The bit lines 16a are biased at fixed bias voltage VBLrd. Each output Iout is a sum of the cell current I times the weight W stored in the cell, for all the cells in that row of memory cells. Therefore, for this architecture, each row of memory cells acts as a single synapse having a weight value expressed as output current Iout dictated by the sum of the weight values stored in the memory cells in that row.

<FIG> illustrates another configuration of an array of four-gate memory cells (i.e., such as that shown in <FIG>) arranged as a gate coupling/source summing matrix multiplier. The lines for the array of <FIG> are the same as that in <FIG>, except that bit lines <NUM> run vertically and there are two of them for each column of memory cells. Specifically, each column of memory cells include two bit lines: a first bit line 16a1 connecting together all the drain regions of the adjacent twin memory cells (two memory cells sharing the same bit line contact), and a second bit line 16a2 connecting together all the drain regions of the next adjacent twin memory cells. The matrix inputs VinO. VinN remain on select gate lines 28a1 and 28a2, and the matrix outputs Iout0. IoutN remain on the source lines 14a. The set of all the first bit lines 16a1 are biased at a bias level, e.g., <NUM>. 2v, and the set of all the second bit lines 16a2 are biased at another bias level, e.g., 0v. The source lines 14a are biased at a virtual bias level, e.g., <NUM>. For each pair of memory cells sharing a common source line 14a, the output current will be a differential output of the top cell minus the bottom cell. Therefore, each output Iout is a sum of these differential outputs: <MAT> <MAT> Therefore, for this architecture, each row of paired memory cells acts as a single synapse having a weight value expressed as output current Iout which is the sum of differential outputs dictated by the weight values stored in the memory cells in that row of paired memory cells (e.g., one positive weight and one negative weight).

<FIG> illustrates another configuration of an array of four-gate memory cells (i.e., such as that shown in <FIG>) arranged as a gate coupling/source summing matrix multiplier. The lines for the array of <FIG> are the same as that in <FIG>, except that the erase gates 30a run horizontally, and the control gate lines 22a run vertically and there are two of them for each column of memory cells. Specifically, each column of memory cells include two control gate lines: a first control gate line 22a1 connecting together all the control gates 22a of the odd row memory cells, and a second control gate line 22a2 connecting together all the control gates 22a of the even row memory cells. The matrix inputs VinO. VinN remain on select gate lines 28a1 and 28a2, and the matrix outputs Iout0. IoutN remain on the source lines 14a.

<FIG> illustrates another configuration of an array of four-gate memory cells (i.e., such as that shown in <FIG>) arranged as a source summing matrix multiplier. The lines and inputs for the array of <FIG> are the same as that in <FIG>. However, instead of the outputs being provided on the bit lines 16a, they are provided on the source lines 14a. The matrix inputs VinO. VinN remain on select gate lines 28a.

<FIG> illustrates a configuration of an array of two-gate memory cells (i.e., such as that shown in <FIG>) arranged as a drain summing matrix multiplier. The lines for the array of <FIG> are the same as that in <FIG>, except that the horizontal source lines 14a have been replaced with vertical source lines 14a. Specifically, each source line 14a is connected to all the source regions in that column of memory cells. The matrix inputs VinO. VinN are placed on the control gate lines 22a. The matrix outputs Iout0. IoutN are produced on the bit lines 16a. Each output Iout is a sum of the cell current I times the weight W stored in the cell, for all the cells in the column. Each column of memory cells acts as a single synapse having a weight value expressed as output current Iout dictated by the sum of the weight values stored in the memory cells for that column.

<FIG> illustrates a configuration of an array of two-gate memory cells (i.e., such as that shown in <FIG>) arranged as a source summing matrix multiplier. The lines for the array of <FIG> are the same as that in <FIG>, except that the control gate lines 22a run vertically and there are two of them for each column of memory cells. Specifically, each column of memory cells include two control gate lines: a first control gate line 22a1 connecting together all the control gates 22a of the odd row memory cells, and a second control gate line 22a2 connecting together all the control gates 22a of the even row memory cells.

The matrix inputs for this configuration are Vin0. VinN and are placed on the control gate lines 22a1 and 22a2. Specifically, input Vin0 is placed on control gate line 22a1 for the odd row cells in column <NUM>. Vin1 is placed on the control gate line 22a2 for the even row cells in column <NUM>. Vin2 is placed on the control gate line 22a1 for the odd row cells in column <NUM>. Vin3 is placed on the control gate line 22a2 for the even row cells in column <NUM>, and so on. The matrix outputs Iout0. IoutN are produced on the source lines 14a. For each pair of memory cells sharing a common source line 14a, the output current will be a differential output of the top cell minus the bottom cell. Therefore, for this architecture, each row of paired memory cells acts as a single synapse having a weight value expressed as output current Iout which is the sum of differential outputs dictated by the weight values stored in the memory cells in that row of paired memory cells.

Exemplary operational voltages for the embodiments of <FIG>, <FIG> and <FIG> include:.

Exemplary operational voltages for the embodiments of <FIG> and <FIG> include:.

<FIG> illustrates an exemplary current to voltage log converter <NUM> for use with the present invention (WL=select gate line, CG=control gate line, EG=erase gate line). The memory is biased in a weak inversion region, Ids = Io * e (Vg- Vth)/kVt. <FIG> illustrates an exemplary voltage to current log converter <NUM> for use with the present invention. The memory is biased in a weak inversion region. <FIG> illustrates a Gnd-referred current summer <NUM> for use with the present invention. <FIG> below illustrates a Vdd-referred current summer <NUM> for use with the present invention. Examples of the load include a diode, a non-volatile memory cell, and a resistor.

The above described memory array configurations implement a feed-forward classification-engine. The training is completed by storing "weight" values in the memory cells (creating a synapse array), which means subthreshold-slope-factors of the individual cells have been modified. The neurons are implemented by summing the outputs of synapse and firing or not firing depending on the neuron threshold (i.e., making a decision).

The following steps can be used to process input current IE (e.g. the input current is coming directly from the output of feature calculations for image recognition):.

The output of each of the cells (IDRAIN) could be tied together in the read mode to sum up the values of each synapse in the array or sector of the array. Once IDRAIN has been summed up, it can be fed into a current comparator, and output a "logic" <NUM> or <NUM> depending on the comparison for a single perception neural network. One perception (one sector) is described above. The output from each perception can be fed to the next set of sectors for multiple perceptions.

In a memory based Convolutional Neural Network, a set of inputs needs to be multiplied with certain weights to produce a desired result for a hidden layer or output layer. As explained above, one technique is to scan the preceding image (for example an NxN matrix using an MxM filter (kernel) that is shifted by X pixels across the image in both horizontal and vertical directions. The scanning of the pixels can be done at least partially concurrently so long as there are enough inputs to the memory array. For example, as shown in <FIG>, a filter size of M=<NUM> (i.e., a 6x6 array of <NUM> pixels) can be used to scan an NxN image array, using shifts of X=<NUM>. In that example, the first row of six pixels in the filter is provided to the first <NUM> of the inputs to the memory array of N<NUM> inputs. Then, the second row of six pixels in the filter is provided to the first <NUM> of the inputs in the second N inputs of the N<NUM> inputs, and so on. This is represented in the first row of the diagram in <FIG>, where the dots represent the weights stored in the memory array for multiplication by the inputs as set forth above. Then, the filter is shifted to the right by two pixels, and the first row of six pixels in the shifted filter is provided to the third through the eighth inputs of the first N inputs, the second row of six pixels is provided to the third through the eight inputs of the second N inputs, and so on. Once the filter is shifted all the way to the right side of the image, the filter is repositioned back to the left side, but shifted down by two pixels, where the process repeats again, until the entire NxN image is scanned. Each set of horizontally shifted scans can be represented by trapezoidal shapes showing which of the N<NUM> memory array inputs are provided with data for multiplication.

Accordingly, a scan of N×N image array, using a shift of two pixels between scans, and a filter size of <NUM>×<NUM>, requires N<NUM> inputs and ((N-<NUM>)/<NUM>))<NUM> rows. <FIG> graphically shows the trapezoidal shapes indicating how the weights in the memory array are stored for the filter scan. Each row of shaded areas represents weights being applied to the inputs during one set of the horizontal scans. The arrows indicate linear input lines of the memory array (e.g., the input lines 28a in <FIG> that receive the input data extend all the way across the memory array in a linear manner, each one always accessing the same row of memory cells; in the case of the array of <FIG>, each of the input lines always access the same column of memory cells). The white areas indicate where no data is being supplied to the inputs. Therefore, the white areas are indicative of inefficient use of the memory cell array.

Efficiency can be increased, and the total number of inputs reduced, by reconfiguring the memory arrays as shown in <FIG>. Specifically, the input lines of the memory array are shifted periodically to another row or column, thus reducing the unused portions of the array, and therefore reducing the number of repeated input lines over the array needed to perform the scan. Specifically, in the case of the present example where the shift X=<NUM>, the arrows indicate that each input line periodically shifts over by two rows or two columns, transforming the widely spaced apart memory cell utilization trapezoidal shapes to closely spaced memory cell utilization rectangular shapes. While extra space between memory cell portions are needed for wire bundles to implement this shift, the number of inputs needed in the memory cell array is greatly reduced (only 5n+<NUM>).

<FIG> illustrates the array of <FIG>, but with periodic shifts of two rows for lines 28a used as the input lines. The periodic shift in rows for the input lines can be similarly implemented in the arrays of <FIG>, <FIG> and <FIG>. <FIG> illustrates the array of <FIG>, but with periodic shifts of two columns for lines 28a1 and 28a2 used as the input lines. The periodic shift in column for the input lines can be similarly implemented in the arrays of <FIG>, <FIG> and <FIG>.

Embodiments for improved tuning mechanisms and algorithms will now be described. Tuning is the process by which the desired amount of charge is verified as being stored in the floating gate of a non-volatile memory cell, that is, to ensure that the non-volatile memory cell is storing the desired value.

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells, reference array <NUM>, and reference array <NUM>. Reference arrays <NUM> and <NUM> serve to convert current inputs flowing into terminals BLR0-<NUM> into voltage inputs WL0-<NUM>. In effect, the reference memory cells are diode connected through multiplexors with current inputs flowing into them. First, it stores the weights that will be used by the VMM <NUM>. Second, memory array <NUM> effectively multiplies the inputs (current inputs provided in terminals BLR0-<NUM>; reference arrays <NUM> and <NUM> convert these current inputs into the input voltages to supply to wordlines WL0-<NUM>) by the weights stored in the memory array to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication function, the memory array negates the need for separate multiplication logic circuits and is also power efficient. Here, the voltage inputs are provided on the word lines, and the output emerges on the bit line during a read (inference) operation. The current placed on the bit line performs a summing function of all the currents from the memory cells connected to the bitline.

<FIG> depicts operating voltages for VMM <NUM>.

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells, reference array <NUM>, and reference array <NUM>. VMM <NUM> is similar to VMM <NUM> except that in VMM <NUM> the word lines run in the vertical direction. Here, the inputs are provided on the word lines, and the output emerges on the source line during a read operation. The current placed on the source line performs a summing function of all the currents from the memory cells connected to the source line.

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells, reference array <NUM>, and reference array <NUM>. The reference array <NUM> and <NUM> serves to convert current inputs flowing into terminals BLR0-<NUM> into voltage inputs CG0-<NUM>. In effect, the reference memory cells are diode connected through mulitplexors with current inputs flowing into them. First, it stores the weights that will be used by the VMM <NUM>. Second, memory array <NUM> effectively multiplies the inputs (current inputs provided to terminals BLR0-<NUM>; reference arrays <NUM> and <NUM> convert these current inputs into the input voltages to supply to the control gates CG0-<NUM>) by the weights stored in the memory array to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication function, the memory array negates the need for separate multiplication logic circuits and is also power efficient. Here, the inputs are provided on the word lines, and the output emerges on the bitline during a read operation. The current placed on the bitline performs a summing function of all the currents from the memory cells connected to the bitline.

VMM <NUM> implements uni-directional tuning for memory cells in memory array <NUM>. That is, each cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate need to be erased together (to be known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached,.

<FIG> depicts operating voltages for VMM <NUM>.

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells, reference array <NUM>, and reference array <NUM>. VMM <NUM> is similar to VMM <NUM>, except that VMM4100 implements bi-directional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to reach the desired amount of charge on the floating gate. As shown, reference arrays <NUM> and <NUM> convert input current in the terminal BLR0-<NUM> into control gate voltages CG0-<NUM> (through the action of diode-connected reference cells through multiplexors) to be applied to the memory cells in the row direction. The current output (neuron) is in the bitline which sums all currents from the memory cells connected to the bitline.

<FIG> depicts tuning algorithm <NUM>. Tuning algorithm <NUM> recognizes that individual memory cells can be fast or slow. A fast cell is one that can be programmed quickly, whereas a slow cell or a normal cell is one that takes a greater amount of time to achieve the same state during a program operation compared to the fast cell. This difference is due to the physics of the individual cell characteristics and variances.

Tuning algorithm <NUM> comprises the following sequence of steps. First, a page of memory cells is erased (step <NUM>). The system then determines which cells in the memory array are fast cells based on look-up table <NUM> that was populated during a configuration sequence and that can be updated during operation if the characteristics for a cell change (from fast to slow or slow to fast) (step <NUM>). Look-up table <NUM> might include, for instance, a list of addresses of all fast non-volatile memory cells. Or it might contain an entry for each cell in the array, and the entry might be a single bit where a "<NUM>" indicates a fast cell and a "<NUM>" indicates a slow normal cell.

If a cell is a fast cell, a fast tuning algorithm is implemented, where a relatively large charge is added to the floating gate of the fast cell through a partial programming operation (step <NUM>). After each partial programming operation, a verify sequence is performed to determine if Icell through the cell in a read operation is greater than Itarget <NUM> (step <NUM>). If no, then the partial programming operation is performed again. If yes, then it is determined if Icell < Imargin_0V (step <NUM>). If yes, then the desired state has been achieved in the memory cell and the tuning sequence is completed (step <NUM>). If not, then the cell has been programmed faster than intended, and it is marked in look-up table <NUM> as a fast cell (step <NUM>). Because too much charge has been placed on the floating gate, the cell is not used, and it must again be erased (step <NUM>).

If the conclusion of step <NUM> is that a cell is slow cell, a low tuning algorithm is implemented, where a smaller charge is added to the floating gate of the slow cell through a partial programming operation (step <NUM>). After each partial programming operation, a verify sequence is performed to determine if Icell through the cell in a read operation is greater than Itarget <NUM> (step <NUM>). If no, then the partial programming operation is performed again. If yes, then it is determined if Icell < Imargin_0V (step <NUM>). If yes, then the desired state has been achieved in the memory cell and the tuning sequence is completed (step <NUM>). If not, then the cell has been programmed faster than intended, and it is marked in look-up table <NUM> as a fast cell (step <NUM>). Because too much charge has been placed on the floating gate, the cell is not used, and it must again be erased (step <NUM>). The fast tuning algorithm can be implemented with a large write (e.g., program) voltage increment or wide write pulse width, The low tuning algorithm can be implemented with a small write voltage increment or a narrow write pulse width.

<FIG> depicts tuning algorithm <NUM>. Tuning algorithm <NUM> can be used during a configuration sequence to identify the cells in a memory array that are fast cells. Tuning algorithm <NUM> comprises the following sequence of steps. A page is erased (step <NUM>). A cell is programmed at a voltage VCG_diagnosis (step <NUM>). The current, Icell1, is measured through the cell during a read operation (step <NUM>). The cell is programmed at a voltage VCG_diagnosis + d V (step <NUM>). The current, Icell2, is measured through the cell during a read operation (step <NUM>). A determination is made as to whether the difference between Icell2 and I cell <NUM> exceeds Icell_0V (step <NUM>). If no, then the cell is a normal or slow cell (step <NUM>). If yes, then the cell is a fast cell, and it is identified as a fast cell in look-up table <NUM> (step <NUM>). As shown in the graph contained in <FIG>, a fast cell will accumulate charge on its floating gate in response to step <NUM>. The incremental programming voltage d is a small voltage and will not affect the accumulated charge for normal or slow cells. That is, fast cells accumulate charge on their floating gates in response to relatively small programming voltages. Alternatively, two erase pulses can be used to extract the delta current of memory cells that fall into the fast bit region. In this case, all of the cells are deeply programmed first.

<FIG> depicts tuning algorithm <NUM>. Tuning algorithm <NUM> combines a coarse algorithm <NUM> (where a cell is programmed in relatively large increments) and a fine algorithm <NUM> (where the cell is programmed in relatively small increments). This minimizes the occurrence of overshooting the desired voltage and increases the overall speed of the system.

Tuning algorithm <NUM> comprises the following sequence of steps. A page is erased (step <NUM>). Coarse algorithm <NUM> is then performed, which comprises steps <NUM> and <NUM>. A cell is programmed at VCG-C_init + dV-C, N_pulseC=NCi+<NUM> (step <NUM>). The current, Icell, is measured through the cell during a read operation, and a determination is made as to whether Icell > Icell_offset (step <NUM>). If yes, then fine algorithm <NUM> begins, which comprises steps <NUM> and <NUM>. The cell is programmed at VCGFiniti (=VCG-C last - Vstep) + dV-F, N_pulseF=NFi+<NUM> (step <NUM>). The current, Icell, is measured through the cell during a read operation, and a determination is made as to whether Icell > Icell_target (step <NUM>). If yes, then the desired charge has been achieved and the tuning process is complete (step <NUM>). If no, then it is determined if f N_pulseF = N max (step <NUM>). If yes, then the cell is determined to be a bad cell and is marked as such in a look-up table (step <NUM>). If no, then step <NUM> is repeated. If the result of step <NUM> is no, then it is determined ifN_pulseC = NCmax (step <NUM>). If yes, then the cell is determined to be a bad cell and is marked as such in a look-up table (step <NUM>). If no, then step <NUM> is repeated. Alternatively, wide write pulsewidth can be used instead of coarse voltage level, and narrow write pulsewidth can be used instead of fine voltage level.

Additional detail regarding the tuning operations of <FIG> and <FIG> will now be described with reference to <FIG>.

<FIG> depicts exemplary values for uniform step algorithm <NUM>. In this example, the approximate program target voltage is 8V. This target voltage is, for example, extracted from a look-up table or a model of current target Itarget versus target programming voltage. The cell is initially programmed at 4V. Thereafter, fine programming comprises programming in step sizes of <NUM>. 01V, with a maximum number of steps of <NUM>.

<FIG> depicts exemplary values for uniform log step (divided by ten), coarse/fine algorithm <NUM>. In this example, the approximate program target voltage is 8V. The cell is initially programmed at 4V. Thereafter, coarse programming comprises programming in log step sizes of <NUM>. 4V (=4V/<NUM>), with a maximum number of steps of <NUM>. Thereafter, a first fine programming sequence occurs, where a partial erase operation to reduce the voltage of the floating gate by <NUM>. 2V, and thereafter, programming occurs in step sizes of <NUM> V, with a maximum number of steps of <NUM>. Then a second fine programming sequence occurs, where a partial erase operation occurs of <NUM>. 1V, and thereafter, programming occurs in log step sizes of <NUM>. 01V (=<NUM>. 1V/<NUM>), with a maximum number of steps of <NUM>. Thus, the total number of pulses is <NUM>.

<FIG> depicts binary search step, coarse/fine algorithm <NUM>. In this example, the approximate program target voltage again is 8V. The cell is initially programmed at 4V. Thereafter, coarse programming occurs in steps where the delta programming voltage is divided by two, namely 2V, 1V, <NUM>. 25V, <NUM>. 125V, and <NUM>. Thereafter, an erasing step is performed to reduce the voltage of the floating gate by <NUM>. 0625V, and thereafter, fine programming occurs in a fixed increments of <NUM>. 01V with a maximum number of steps of <NUM>. This total number of pulses is <NUM>.

<FIG> depicts an exemplary waveform of algorithm <NUM>. As can be seen, coarse programming increased the voltage until Icell exceeds a threshold. Then a voltage step down is performed to reduce the voltage by <NUM>. 0625V, and thereafter, fine programming occurs. The step down is to avoid the potential program overshoot for the next programming pulse.

<FIG> depicts another exemplary waveform for the coarse-fine algorithms described herein. First, coarse programming occurs. Second, fine programming occurs. Third, once the appropriate voltage is achieved, the total amount of programming charge is recorded and/or the steps recorded, so that thereafter, the appropriate programming level can be achieved with a single constant voltage programming operation at the desired accurate charge. Alternatively, the tuning algorithm can consist of coarse pulses consisting of wide pulse-width and/or a large voltage increment and fine pulses consisting of constant pulsewidth and/or constant voltage pulses.

In alternative embodiments, the embodiments of <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> can be modified such that the inputs are the control gates instead of the select gates (wordlines). Similarly, the embodiments of <FIG> and <FIG> can be modified such that the inputs are the select gates (word lines) instead of control gates.

Claim 1:
A method (<NUM>) for programming a non-volatile analog neuromorphic memory cell, comprising:
erasing the cell (<NUM>);
performing a coarse programming sequence (<NUM>, <NUM>, <NUM>, <NUM>) on the cell, comprising:
performing a first programming operation on the cell with a first voltage increment; and
repeating the first programming operation until the current through the cell during a read operation exceeds a first current threshold;
performing a first fine programming sequence (<NUM>, <NUM>, <NUM>) on the cell, comprising;
removing a portion of the charge on the floating gate of the cell; and
programming the cell with a second voltage increment until the current through the cell during a read operation exceeds the threshold, wherein the second voltage increment is smaller than the first voltage increment; and
performing a second fine programming sequence (<NUM>, <NUM>, <NUM>) on the cell, comprising;
removing a portion of the charge on the floating gate of the cell; programming the cell with a third voltage increment until the current through the cell during a read operation exceeds the threshold, wherein the third voltage increment is smaller than the second voltage increment.