Patent Description:
This disclosure generally relates to self-boosting amplifier techniques.

Switching audio amplifiers can be used to drive speakers for sound reproduction. A class-D amplifier is an amplifier in which amplifying components (e.g., a pair of transistors) operate as electronic switches that rapidly switching back and forth between the supply rails to encode an audio input into a pulse train. Once processed to remove the high-frequency pulses (e.g., by a low-pass filter), the audio signal is provided to a loudspeaker. Since the components (e.g., the transistors) never conduct at the same time, there is no other path for current flow apart from the low-pass filter and the loudspeaker. As such, class-D amplifiers provide high power conversion efficiency along with high-quality signal amplification.

The patent document <CIT> describes a switched-mode audio amplifier.

The patent document <CIT> describes switching amplifiers and switching power converters.

In one aspect, this document describes an apparatus according to claim <NUM>.

Implementations can include one or more of the following features. Both the first Zeta converter and the second Zeta converter may be fourth order converters. Both the first Zeta converter and the second Zeta converter may employ a Zero Voltage Transition (ZVT) switching technique. Each of the first Zeta converter and the second Zeta converter may include an inductor directly connected to ground and a switch directly connected to the power supply. The controller may be connected to the load to receive a feedback signal. The feedback signal may be a voltage feedback signal or a current feedback signal. The controller may use the feedback signal to control delivery of the audio to the first Zeta converter and the second Zeta converter. Each of the first Zeta converter and the second Zeta converter may use integrated magnetics to couple inductors. The converter and/or controller may be configured to initiate moving one or more poles and zeros to positions external to the operating frequency range (e.g., an audio frequency band, a control frequency band, etc.) of the amplifier.

Various implementations described herein may provide one or more of the following advantages. Through the presented design, a self-boosting class-D amplifier can function without needing to employ a separate boost converter, share a boost converter, etc. The design allows an amplifier to provide multiple channels with larger dynamic range for each channel. The design can employ digital dynamic compensation to control the amplifier and reduce distortion. The controller may implement strategies to suppress switching losses.

Two or more of the features described in this disclosure, including those described in this summary section, may be combined to form implementations not specifically described herein.

Increased power conversion efficiency of class-D amplifiers allow for higher current and higher output power into transducers such as audio speakers. When class-D amplifiers are powered from a fixed voltage supply rail, a reduction in transducer impedance facilitates further increments in power output to the transducers when the further power is not achievable with the provided rail voltage and actual transducer impedance. But reducing the transducer impedance can cause losses through connecting wires to become excessive, thereby negating the efficiency benefits of the class-D amplifier itself. An alternative technique can be employed to increase the power delivered to the transducer, for example, supply voltage used by the amplifier may be increased, which would proportionally reduce the magnitude of the current into the transducer. Such an increase in supply voltage may cause increases in losses (due to the switching nature of class-D amplifiers), but this technique is more practical than lowering transducer impedance.

In battery operated environments, such as with portable audio devices, automotive sound applications, etc., providing increased voltage can call for a dedicated voltage step up (e.g. from boost converter, etc.). Such a boost converter supplies power to the amplifier and may need to be employed since available battery voltage is typically lower than the voltage needed to supply the class-D amplifier.

For efficiency (e.g., space and cost savings, etc.), a boost converter can be shared among two or more class-D amplifier power stages. Such a topology can lead to tradeoffs pertaining to the maximum power the boost converter is able to provide, both short term and/or long term. However, some inefficiencies can be introduced through such sharing; for example, only one of the connected amplifiers may require a high output power while the other amplifier(s) remain at a relatively low output level. Channels associated with the lower output amplifier could therefore run with a lower efficiency compared to the one that needs the higher boost voltage. Along with introducing potential inefficiency, the class-D amplifiers should be kept from saturation that can clip output voltage and cause audio distortion along with increasing the probability of damage to the transducer (e.g., speaker) from excess thermal stress. To address potential saturation, voltage compression techniques may be employed to reduce gain when a clipping threshold is approached (e.g., a threshold between <NUM>% - <NUM>% of a maximum voltage output level).

Rather than employing a separate device for boosting, a class-D amplifier design provides this functionality and the ability that drives a transducer while increasing dynamic range. Through this design, an amplifier can be achieved that provides multiple channels with high dynamic range for each channel. Further, physical size can generally be maintained (compared to conventional buck derived class-D amplifiers) and the voltage and power output can be optimized for each individual channel without compromising the efficiency of adjacent channels. In one example, a design includes a fourth order DC to DC converter (referred to as a Zeta converter) that is capable of operating in a step-up mode or a step-down mode (a buck-boost capability). The Zeta converter improves dynamic behavior of the power stage of the amplifier. Additionally, the design employs digital compensation to control the amplifier and reduce distortion.

Further, integrated magnetics can be used to reduce circuitry space needs, and relatively high frequency zero voltage transition (ZVT) techniques can be used to reduce switching losses. For example, ZVT techniques described in <CIT> may be applied. Integrated magnetics can be used not only to couple an input inductor to an output inductor (on the positive and negative sides) but also to cross-couple to each other. For example, integrated magnetics can be employed as described in <CIT>. Along with reducing ripple current, magnetic flux ripple is reduced within the magnetic structure, which reduces magnetic losses using smaller sized components while allowing high switching frequencies. Using cross-coupled magnetics imposes a higher common-mode inductance compared to the differential mode inductance, which reduces high frequency emissions (for electromagnetic compatibility (EMC) considerations). The partial coupling between the input and output inductances also allows for the repositioning of open loop small signal transfer function resonances to aid the stabilization of the amplifier. Referring to <FIG>, control to output gain and phase (versus frequency) charts <NUM> and <NUM> of a Zeta converter are presented for which coupling factor (k) is varies for input and output coils.

By using these design features, a switching class-D push-pull amplifier can be powered by a single constant supply rail relative to ground (e.g., a battery) and produce an output voltage having a single-sided peak voltage above the supply rail relative to ground absent the need to add an external boost power converter. As such, the design provides a self-boosting class-D amplifier that is capable of increasing dynamics and correspondingly deliver higher power to a transducer, and improve sound quality of a sound system, etc. By employing a Zeta converter in the design, the output bias is positive and the appearance of right half plane zeroes can be made absent in the control-to-output transfer function operating frequency range, supply-to-output transfer function, etc. Through this design, small sized amplifiers can be implemented by employing relatively high switching frequencies, which allow for components having low reactive values (e.g., low value inductances for inductors and low value capacitances for capacitors). Using low value reactances, transfer function resonances (conjugate poles) as well as conjugate zeros are moved beyond the upper region of the audio frequency band and a relatively flat gain is provided in the audio band. Using local current feedback techniques, synthesized damping resistances are introduced to reduce the Q of conjugate pole related resonances.

A digital controller should also be employed in the design to assist in the accurate and consistent placement of poles and zeros in a loop controller of the amplifier. The digital controller can also allow for dynamic duty cycle based positioning and repositioning of gain, poles and zeros based on one or more programmed duty cycles. Along with improving stability and dynamics, the use of a digital controller also allows for high-order compensators, thereby allowing for steep magnitude and phase features while providing high closed loop gain without compromising phase margin. The digital controller allows differential mode and common mode aspects of output signals to be separately controlled. In some implementations, feedback is provided by a low latency analog-to-digital converter (ADC) (e.g., a sigma-delta based ADC) and the ADC can take feedback at the output of the amplifier (after output inductors). A digital modulator can be used to drive the power switches of the amplifier to reduce modulator linearity issues. A digital modulator can also be programmed to dynamically control the common mode DC bias at the output to suppress high frequency switching losses by reducing the voltage across the transistors when the differential output levels are relatively low in amplitude.

One or more switching techniques may be employed in the amplifier design; for example, Zero Voltage Transition (ZVT) switching can be used to reduce the switching losses of the amplifier for a larger range of duty cycles. Such techniques allow for high frequency switching with relatively low transistor switching losses and can be realized in a variety of implementations; for example Gallium nitride (GaN) based components, such as field-effect transistors (FETs), may be used in the amplifier. Further, the total resistance between the drain and source in the FETs ("drain-source on resistance, RDS(on)) can be very low facilitating the reduction of transistor conduction losses. High output capacitance can be instrumental as a resonant capacitance to achieve ZVT conditions together with small auxiliary circuits consisting of a small resonant coil and switch.

In some implementations, the power converter of the amplifier includes a reduced number of high power switches (e.g., for a small chip die); for example, a maximum of four main high-power FET switches can be used to provide a cost competitive amplifier (e.g., compared to conventional class-D amplifiers).

<FIG> shows a block diagram of a system <NUM> where a load <NUM> (e.g., a speaker) is driven by class-D amplifiers <NUM> from both sides. <FIG> also shows a detailed view <NUM> of the amplifier <NUM>; the detailed view <NUM> showing examples of various components that can be used in implementing the amplifier <NUM>. As shown in the detailed view <NUM>, the amplifier <NUM> includes two switches <NUM> and <NUM> which can be implemented using active devices such as transistors, FETs, etc. The output generated at a node <NUM> is a variable duty cycle square wave the low-frequency portion of the spectrum of which includes the desired output, and the high-frequency portion of the spectrum of which includes components due to the switching of the power devices.

The output pulse train obtained at node <NUM> is converted to an analog signal suitable for driving the load <NUM> via a low pass filter circuit. In some implementations, the low-pass filter circuit is a passive LC circuit that includes one or more inductors <NUM> and one or more capacitors <NUM>. While <FIG> shows the filter circuit as a part of the detailed view <NUM> for the amplifier <NUM>, in some cases, the filter circuit may be depicted separately from the amplifier <NUM>. In operation, the filter circuit removes or blocks the high-frequency components and recovers the desired low-frequency signal suitable for driving the load <NUM>. Using purely reactive components such as inductors and capacitors results in high efficiency.

The efficiency of switching amplifiers are affected however by switching losses arising out of the switching operations of the active components <NUM> and <NUM>. The switching operations also give rise to undesirable ripple currents. The ripple currents can also be reduced through the component value choices in the LC filter circuit and the relative switching frequency. Higher switching frequencies generally result in lower ripple currents for a given inductance value, while smaller inductance values result in higher ripple currents for a given switching frequency. Therefore, the overall ripple current can be maintained by going to a higher switching frequency and using smaller inductors. This is desirable because smaller inductance values are typically lower cost and size. However, at higher switching frequencies, the switching losses increase, thereby reducing the efficiency of the circuit. In some implementations, the switching frequency can be selected in view of this trade-off.

In the example shown in the detailed view <NUM>, the structure of the class-D amplifier <NUM> is essentially identical to that of a buck converter. In some implementations, such buck converters can be used to form class-D amplifiers for driving a fixed load from both sides. In some implementations, four or more synchronous buck converters configured as two or more H bridges may be used for this purpose. Because the output current and voltage of a class D amplifier can independently change signs, multiple modes of operations are possible in the configuration depicted in <FIG>. For example, the configuration of <FIG> may be operated in a common mode (CM) and one or more differential modes (DM). In a DM, the voltage difference between two load terminals 112a and 112b is given by: <MAT> wherein V<NUM> and V<NUM> are the output voltages of the amplifiers on the two sides of the load, respectively. The CM voltage is average of the output voltages of two amplifiers, and given by: <MAT>.

For a bridge tied load (BTL), where load is connected between two switching bridges, different modulation schemes (e.g., AD, BD) can be used to achieve different goals in terms of DM and CM component of output voltage. In some implementations, higher degrees of freedom can be realized using multiple amplifiers on either side of the load. An example of such a configuration is depicted in <FIG>, which shows a block diagram of a system <NUM> where a load <NUM> is driven by multiple amplifiers 110a, 110b, 110c, and 110d (<NUM>, in general) from both sides.

<FIG> shows a conventional class-D push-pull amplifier <NUM> that is created through the combination of two regular synchronous buck converter power stages <NUM>, <NUM> in a push-pull formation (referred to as a class-D H-bridge), which is similar to the BTL stage shown in <FIG>. Both buck converters <NUM>, <NUM> share a single power supply <NUM> referenced to ground. Similar to the load <NUM> (shown in <FIG> and <FIG>), a load <NUM> (e.g., a speaker) is connected between the buck stages.

The load <NUM> is driven through the modulation of switches <NUM>, <NUM>, <NUM>, and <NUM> (power MOSFETs) of these two power stages <NUM>, <NUM>. When both buck converters <NUM>, <NUM> are modulated with a <NUM>% switching duty cycle the voltages at nodes <NUM> and <NUM> have the same potential, approximately half of the voltage (VCC) provided by power supply <NUM>. This voltage potential is provided since each buck converter <NUM>, <NUM> has a DC transfer characteristic of V(at node <NUM>) VCC = D and V(at node <NUM>)/VCC=<NUM>-D. Due to these transfer characteristics, no current flows through the load due to the zero differential voltage. When buck converter <NUM> is modulated with a duty cycle different from <NUM>% (e.g., <NUM>%), the voltage at node <NUM> increases to <NUM>% of VCC (again, being provided by power supply <NUM>). Due to the inverted phasing of the gates of buck converter <NUM> relative to buck converter <NUM>, the duty cycle of buck converter <NUM> is <NUM>%. As such, the voltage at node <NUM> is <NUM>% of VCC (from the power supply <NUM>). The voltage at node <NUM> being higher than node <NUM>, current flows through the load from node <NUM> to node <NUM>. Similarly, for a duty cycle less than <NUM>%, the current flows from node <NUM> to node <NUM> thereby providing an opposite differential load voltage polarity and the opposite direction of current flow. As such, the amplifier <NUM> produces positive and negative polarities across the load <NUM>.

Each buck converter <NUM>, <NUM> have a linear DC transfer function which provide for an overall DC transfer function of the amplifier <NUM> as being linear (i.e., V(at node <NUM>)-V(at node <NUM>) = 2D-<NUM>). When an audio signal varies the modulation, the output of the amplifier <NUM> is linearly modulated by the audio signal and amplification of the output voltage and current is provided in a linear manner. Referring briefly to <FIG>, a chart <NUM> provides the DC gain versus duty cycle of the class-D amplifier <NUM>, and a line <NUM> represents the linear nature the DC gain provided by the amplifier.

Returning to <FIG>, in this implementation, the polarities of nodes <NUM> and <NUM> are positive relative to ground. As such, the common-mode voltage component of the output voltage across the load <NUM> is also positive. This characteristic of the amplifier <NUM> can be selected for various reasons; for example, for use in single-supply battery operated environments that are realized with integrated circuits. In this implementation, both buck converters <NUM>, <NUM> are synchronous since current flowing from one buck converter (e.g., converter <NUM>) needs to be absorbed by the other buck converter (e.g., converter <NUM>) while the output voltage is positive relative to ground. An asynchronous converter is unable to absorb the current since reverse currents would be blocked.

Linearity of the buck converters <NUM>, <NUM> may be lost due to dead-time control when avoiding current shoot-through in the switches <NUM>, <NUM>, <NUM>, and <NUM>. Such a situation can occur for Zeta amplifiers. During these time periods, output signals can become distorted (e.g., odd harmonics may appear) as the gain changes abruptly through the range of duty cycles. Distortion may have other sources; for example, stiffness of the power supply <NUM> and asymmetric switching edge rates can result in non-linearities of the amplifier <NUM>. One technique to compensate such non-linearities is to employ a feedback scheme (e.g., negative feedback); for example, feedback can be provided by the differential voltage across the load <NUM> since this voltage component contains the desired audio signal to be output by the amplifier <NUM>.

<FIG> shows charts <NUM> and <NUM> that respectively represent the magnitude and phase of the small signal control (e.g. duty cycle) to differential output response of the amplifier <NUM>. Both charts report the magnitude and phase for three different duty cycles (i.e., <NUM>%, <NUM>% and <NUM>%). For <NUM>%, <NUM>%, and <NUM>% duty cycles the responses are approximately the same (since the gain is linear and the location of poles and zeros do not vary with duty cycle). The gain values provided by chart <NUM> (e.g., a forward gain of <NUM> dB) provide for reasonable negative feedback gain for output correction. Due to the bipolar nature of the differential output, the <NUM>° phase changes are reported in chart <NUM> for duty cycles below <NUM>%. From these responses, compensation techniques (e.g., analog or digital techniques) may be employed by a compensator (e.g., a feedback control loop compensator) with only static compensation gain, poles, and zeros.

Referring to <FIG>, charts <NUM> and <NUM> respectively represent the magnitude and phase of the common-mode supply to output response of the amplifier <NUM> for duty cycles of <NUM>%, <NUM>%, and <NUM>%. For buck derived BTL class-D amplifiers (at <NUM>% duty cycle), the common-mode output does not contribute to the differential audio voltage and current in the load <NUM> since voltage would appear equally at node <NUM> and node <NUM> and no differential audio component would be ideally be generated. However, from a practical perspective, slight differences between components of the two buck power converters <NUM> and <NUM>, and a common-mode to differential mode gain is present. For duty cycles other than <NUM>%, the supply ripple translates to the output as the pulse widths on the positive and negative halve of the amplifier are deliberately at different duty cycles. As a result, supply variations translate to the output with fixed gain. The phase of the transfer depends on the duty cycle: For duty cycles larger than <NUM>% the phase is <NUM> degrees out of phase compared to the response for duty cycles smaller than <NUM>% duty cycle. This gain typically appears as an error in the differential response when the voltage of the power supply <NUM> varies (referred to as a power supply rejection ratio (PSRR) response) and can create audio artifacts and generate perceived distortions. By implementing a feedback compensator using negative differential feedback, these artifacts and distortions can be rendered substantially inaudible.

The feedback compensator can also use a common-mode feedback or common-mode feed-forward correction to prevent the common-mode bias voltage across the load from varying in an excessive manner. By using this compensation, large currents in output filter inductors and capacitors of the amplifier are avoided, which can result in losses. In some implementations, the feedback compensator can employ a first order common-mode control loop to attenuate common-mode voltage variations and address the losses. The control loop assists in maintaining the power supply bias voltage across the load even in instances that where variations in the power supply voltage appear. The feedback compensator can also track a relatively slow changing power supply voltage to prevent asymmetric effects in the output voltage. Differential and common-mode control loops provided by a feedback compensator can therefore reduce the needs for a regulated power supply to the amplifier and thereby keep the amplifier power conversion stage small. The common mode feedback compensator can also be used to minimize the voltages across the switches within the converters to reduce the transistor switching losses. The reference of the common mode loop can by adjusted for such purpose.

Referring to <FIG>, charts <NUM> and <NUM> respectively represent the magnitude and phase of the differential output impedance for various duty cycles for the amplifier <NUM>. In this particular implementation, inductance values of approximately <NUM> micro Henry (µH) and capacitance values of approximately <NUM> micro Farad (µF) may be employed; however, in other implementations, other inductance and capacitance values may be used. Similar to the charts shown in <FIG> and <FIG>, the output impedance is the same for all choices of the duty cycles. In general, the output impedance is provided by a combination of parasitic resistances from components of converters stages <NUM>, <NUM> and an output filter. Substantially constant for low audio frequencies, the differential impedance increases with frequency due to inductors in the output filter. In this example, around <NUM> this inductance can resonate with the capacitors in the output stage. Increasing in frequency beyond <NUM>, the output impedance decreases as the capacitors in the filter substantially dominate the output impedance (e.g., limited by the capacitor parasitic equivalent series resistance (ESR)). In this example, the ESR introduces a double zero near <NUM> and the impedance becomes the sum of the ESR of the output filter capacitors. As provided by the charts <NUM>, <NUM>, the differential impedance can vary considerably across frequency even in the audio band. Referring to <FIG>, a chart <NUM> presents the output impedance of a Zeta amplifier for various duty cycles. In general, the magnitude response of the output impedance behaves more resistively due to the selection of smaller inductors and capacitors in the Zeta amplifier due to the higher frequency operation to push response features above the audio frequency band.

Referring to <FIG>, charts <NUM> and <NUM> respectively present the magnitude and phase input impedance of a buck derived class-D BTL amplifier for duty cycles of <NUM>%, <NUM>%, and <NUM>%. Similar if not identical magnitude and phase input impedances would be provided for other duty cycles (e.g., <NUM>%, <NUM>%, and <NUM>%). The buck derived class-D BTL amplifier is derived from a buck regulator and its input current generally has a pulsating characteristic. The BTL configuration of this amplifier assists with mitigating the current situation as the pulsing of the input current is complementary at <NUM>% duty cycle between the positive and negative sides of the amplifier for AD modulation. Statistically, the amplifier spends most time at <NUM>% duty cycle and the system benefits from ripple cancelation most of the time. Through this mitigation, the pulsing input current becomes a quasi-DC current with a superimposed saw-tooth shaped ripple. This can drastically reduce the size of the EMC input filter that is needed in typical applications to avoid conducted and radiated emissions from a supply wire harness. For a <NUM>% duty cycle, a differential output is absent and very little of any input current flows and the impedance is large. The input impedance reduces towards higher frequencies due to the complex impedance of the output filter of the amplifier. At resonance the magnitude response (as shown in chart <NUM>) reaches a minimum and then increases with higher frequencies. At <NUM>% duty cycle the input of the amplifier acts capacitive towards a resonance at <NUM>. At duty cycles away from <NUM>%, the input impedance reduces at low frequencies. The input impedance acts more resistively further away for <NUM>% and the input impedance reduces as the input current increases. However, the resonance introduced by the input filter remains in place. Due to the high-Q nature of the resonance, an abrupt <NUM>-degree phase shift around <NUM> is present (as shown in chart <NUM>). Care should be taken with combining this with EMI input filters, not to create instabilities. Referring to <FIG>, a chart <NUM> presents the input impedance of a Zeta amplifier for various duty cycles. In general, the input impedance includes features that are pushed to higher frequencies out of the audio band. While comparable to a buck derived amplifier, the high frequency features change position with different duty cycles which differs from the buck derived amplifier. These low frequency features behave similar to buck derived amplifier. Referring to <FIG>, one or more designs may be employed for an amplifier that is capable of self-boosting; for example a power converter may be introduced that boosts the output voltage of the amplifier over the input voltage. The DC duty cycle reference can be replaced by a signal that is modulated by an audio signal. The amplifier may employ various designs; for example, a push pull design may be used due to its ability to increase (i.e., double) the output voltage. Such a design generally includes at least two power converters being connected to a load in a manner similar to a buck derived class-D amplifier that includes two buck converters connected to a load. Switch controlling of the two power converters is similarly provided. The two power converters can be driven in complementary manner. For example, one power converter can be driven by a complementary duty cycle relative to the other power converter. Using this design, a two-state modulation or out-of-phase (AD) modulation can be employed, a three-state modulation or in-phase (BD) modulation can be used, etc..

<FIG> shows an exemplary design of power converter based self-boosting amplifier <NUM>. In this example, the amplifier <NUM> is second order and is synchronous so both source and sink currents can provide a bi-directional output. In this example, the amplifier <NUM> includes two boost converter stages <NUM>, <NUM> that are supplied by a power supply <NUM> (e.g., one or more batteries). A controller <NUM> receives an audio signal and provides corresponding modulated signals (highlighted by input lines <NUM> and <NUM>) to each of the boost converter stages <NUM>, <NUM> for delivering the audio to a load <NUM> (e.g., a speaker). In some instances, right half plane zeros (RHPZ) may be present in the control-to-output and supply-to-output transfer characteristics of the amplifier. Frequencies at which the RHPZ occur generally depend on component values and parasitic resistances, and the RHPZ may change its position towards lower frequencies as duty cycle changes from <NUM>%. In general, compensation of the RHPZ with a canceling pole is not achievable along with high open loop gain through employing a feedback compensation technique that reduces gain as the location of the RHPZ in the frequency domain is approached. This is because the zero adds an additional <NUM>-degree phase shift (instead of a lag as is the case with a LHPZ). The normal process of adding a zero-compensating pole adds an additional <NUM> degrees thereby destabilizing the system completely. The feedback adds in phase with the input thereby causing a runaway condition. In this example, the feedback is provided (via signal lines <NUM> and <NUM>) from nodes A and B connected to the load <NUM>. Due to the avoidance of RHPZ compensation, such amplifiers have generally low bandwidth along with low gains at higher audio frequencies which can limit distortion prevention. <FIG> shows one implementation (of the block diagram shown in <FIG>) in which each of the second order boost converters <NUM> and <NUM> include an inductor (e.g., inductors <NUM> and <NUM>) and a capacitor (e.g., capacitors <NUM> and <NUM>). This particular amplifier also provides no intrinsic means to limit the current flow from the battery source which may yield unsafe conditions during an output short to ground.

Referring to <FIG>, other designs may be utilized for such amplifiers. In the illustrated example, an amplifier <NUM> employs a push pull design that includes two Cuk power converters <NUM>, <NUM> that are connected to a load <NUM> (e.g., a speaker). Similar to the previous design, a power supply <NUM> (e.g., a battery) delivers power to the amplifier <NUM> and a controller <NUM> provides a modulated version of an audio signal to the two Cuk power converters <NUM>, <NUM>. In some arrangement, the controller <NUM> may provide other functionality, such as feedback compensation. In general, the Cuk power converters <NUM>, <NUM> employ inductors and capacitors to transfer and convert energy such that their output voltage is larger than the input voltage. A considerable drawback of this arrangement is that the output bias of this amplifier is negative which creates design complications when the circuitry is implemented on an integrated circuit due to possible transistor latch up considerations. As shown in <FIG>, each of the Cuk power converters <NUM>, <NUM> include two inductors (e.g., inductors <NUM> and <NUM> in power converter <NUM>, and inductors <NUM> and <NUM> in power converter <NUM>) and two capacitors (e.g. capacitor <NUM> and <NUM> in power converter <NUM>, and capacitors <NUM> and <NUM> in power converter <NUM>). The negative output bias requires transistors <NUM> and <NUM> to be upside down which may complicate the integrated circuit design.

The amplifier <NUM> is synchronous to allow for both current sourcing and sinking for enabling a bi-polar current at the load <NUM>. In this example, the Cuk power converters <NUM>, <NUM> are 4th order converters and as mentioned above include more components than the amplifier design shown in <FIG>. For this type of amplifier design, the control-to-output and supply-to-output transfer functions can be complex and compensations techniques (e.g., analog feedback compensation techniques) via the controller <NUM> can also be complex. Additionally, the presence of the RHPZ will limit the bandwidth. The design of amplifier <NUM> can also result in conjugate zero and pole pairs that can produce resonances in the audio frequency band that would need to be controlled. In some arrangements, inductor coils are coupled in the Cuk power converter. Further, the RHPZ of this amplifier <NUM> would be required to be placed above the audio band to avoid reducing the audio amplifier audio bandwidth considerably, similar to the amplifier <NUM> (shown in <FIG>). In some instances, the design of amplifier <NUM> can introduce harmonic distortion (due to its non-linearity) and a considerable gain (<NUM> dB) across the audio band may be needed for compensation. The design can also introduce voltage and current stress on switches (e.g., FETs) included in the Cuk power converters <NUM>, <NUM> due to the presence of high component voltages. Similarly, due to the transfer or energy, the capacitors in the Cuk power converters <NUM>, <NUM> can also experience such stresses.

Referring to <FIG>, a design for an amplifier <NUM> is shown that employs a power converter topology, which is fourth order. In general, the amplifier <NUM> has a self-boosting push-pull design and uses a Zeta power converter design that can be compensated to provide full audio bandwidth. Another benefit is that this Zeta topology does not invert the output bias. A benefit is that this amplifier is naturally short circuit protected due to the series switch and capacitor. In this example the amplifier used a synchronous Zeta power converter topology. As shown in the figure, the amplifier <NUM> includes two Zeta power converters <NUM>, <NUM>, that receive power from a power supply <NUM> (e.g., a battery) and drive a load <NUM> (e.g., a speaker). Audio signals received by the amplifier <NUM> are provided by a controller <NUM> to the power converters <NUM>, <NUM>, and nodes A and B located on either side of the load <NUM> provide feedback to the controller <NUM> (e.g., for compensation techniques). The two Zeta power converters <NUM> and <NUM> are driven by a complementary duty cycle relative to one another. Using this design, out-of-phase (AD) modulation or in-phase (BD) modulation may be employed.

As shown in the figure, each of the Zeta power converters <NUM>, <NUM> are fourth order and include two inductors in each of the Zeta converter halves (e.g., boost inductors <NUM> and <NUM> in power converters <NUM> and <NUM> and output inductors <NUM> and <NUM> in power converter <NUM> and <NUM>) and two coupling capacitors (e.g. capacitor <NUM> and <NUM>, and two output capacitors <NUM> and <NUM>). Each Zeta power converter includes two switches (e.g., boost FET switches <NUM> and <NUM> in power converter <NUM> and <NUM>, and two output FET switches <NUM> and <NUM> in power converter <NUM> and <NUM>). Compared to the Cuk power converters <NUM>, <NUM> shown in <FIG>, the circuity of the Zeta power converters <NUM>, <NUM> is different. For example, connections of inductors in the Zeta power converters <NUM>, <NUM> differ from inductor connections of the Cuk power converters <NUM>, <NUM>. In the illustrated examples, the inductors <NUM> and <NUM> of the Zeta power converters <NUM>, <NUM> are connected to ground while the inductors <NUM> and <NUM> of the Cuk power converters <NUM>, <NUM> are connected to the high side of the power source <NUM>. Additionally, positions of connected switches are different for two designs. In particular, the FET switch <NUM> in Zeta power converter <NUM> and the FET switch <NUM> of Zeta power converter <NUM> are connected to the high side of the power source <NUM> while FET switches in the Cuk power converters <NUM>, <NUM> are each connected to ground. Additionally, FET switch <NUM> (of Zeta power converter <NUM>) and FET switch <NUM> (of Zeta power converter <NUM>) are connected upside down compared to the output FET switch <NUM> (of Cuk power converters <NUM>) and output FET switch <NUM> (Cuk power converters <NUM>). As such, the positions of these inductors and switches (e.g., the input inductors and input switches) have been reversed. Comparing the Cuk power converter to the Zeta power converter, the Cuk power converter has reduced input ripple current compared to the Zeta power converter. The Zeta converter's boost inductor voltage switches from positive to negative voltages each cycle which typically calls for design considerations for the gate driver of the input stage when N-MOS transistors are used as the gate driver most float with the source voltages of switches <NUM> and <NUM>. When using P-MOS switches, the gates are just pulled down to ground potential.

Referring to <FIG>, a block diagram <NUM> of a Zeta converter based self-booting push pull amplifier system is presented. A supply voltage reference is provided (e.g., from a battery) into an input <NUM> and audio is received on input <NUM>. The amplifier includes compensators <NUM>, <NUM> that respectively receive parameter data from parameter look up tables (LUTs) <NUM>, <NUM>. In this implementation digital modulators <NUM>, <NUM> provide signals to respective ZVT gate drivers <NUM>, <NUM> that provide signals to a Zeta Power Conversion/ Filter stage <NUM>. Other switching techniques can also be employed. An output signal is provided to a load <NUM> (e.g., a speaker), which is also provided to a low latency analog-to-digital converter <NUM> for providing feedback (e.g., CM and DM) to the compensators <NUM>, <NUM>.

Referring to <FIG>, a compact version of a Zeta-based amplifier <NUM> includes two Zeta power converters <NUM> and <NUM>. Each of the Zeta power converters include two inductors (e.g., inductors <NUM> and <NUM> in power converter <NUM>, and inductors <NUM> and <NUM> in power converter <NUM>) and two capacitors (e.g. capacitor <NUM> and <NUM> in power converter <NUM>, and capacitors <NUM> and <NUM> in power converter <NUM>). Each of the Zeta power converters also includes two switches (e.g., switches <NUM> and <NUM> in power converter <NUM>, and switches <NUM> and <NUM> in power converter <NUM>). Generally, such Zeta amplifiers include approximately the same number of switches as other designs (e.g., buck derived, boost derived and Cuk derived class-D amplifiers) and associated parameters (e.g. die area, cost, etc.) are comparable. In this example FETs are used to implement the switches <NUM> - <NUM>; however, other type of switching technology may be employed in some arrangements.

<FIG> illustrate the functional aspects of the Zeta amplifier <NUM> (shown in <FIG>) during steady state conditions. For this illustration, each of the inductors (e.g., inductors <NUM>, <NUM>, <NUM>, and <NUM>) have equivalent inductance values, and each of the capacitors (e.g., capacitors <NUM>, <NUM>, <NUM>, and <NUM>) have equivalent capacitance values. However, in some implementations, inductance values and/or capacitance values may differ.

In general, using out-of-phase AD modulation, three switch states are cycled through for the Zeta amplifier <NUM> in a repetitive manner (e.g., state <NUM>, state <NUM>, state <NUM>, state <NUM>, state <NUM>, state <NUM>, state <NUM>, state <NUM>. The Zeta amplifier <NUM> is considered to be in a steady-state of operation and the output is <NUM> volt differential mode and thereby has zero load current. Steady-state is considered to mean that the programmed duty cycle (e.g., D=<NUM>%) and differential output voltage are near constant (e.g., <NUM> volt). Referring to <FIG>, the four switches <NUM>, <NUM>, <NUM>, and <NUM> (e.g., FETs as shown in <FIG>) are controlled in an interleaved manner: switch <NUM> being out of phase with switch <NUM>, and switch <NUM> and in phase with <NUM>. During the dead-time phase, all four switches <NUM>, <NUM>, <NUM>, and <NUM> are off. While the described design uses out-of-phase (AD) modulation, in some implementations the design may be adjusted to employ in-phase (BD) modulation or other modulation variants.

Each of the Zeta power converters <NUM> and <NUM> included in the Zeta amplifier <NUM> generally operate in a two-step process to move energy from input to output. Initially, an input inductor is charged from the supply (e.g., the battery) and at the same time, an output inductor is charged by a coupling capacitor. The input inductor then transfers its stored energy to re-charge the coupling capacitor while the output inductor discharges to the output capacitor and the load. There is a dead-time state in between these energy transfers to ensure no shoot-through currents occur from the supply to ground, thus it is a two-step process with three switch states.

In switch state <NUM>, as illustrated in the <FIG>, switch <NUM> is on (in Zeta power converter <NUM>) and switch <NUM> is off. Node <NUM> is effectively connected to the supply <NUM>, which forces the voltage across inductor <NUM> to equal that of the power supply <NUM> (e.g., a <NUM>-volt battery in this instance), causing inductor <NUM> to charge with energy. Node <NUM> voltage is held at that level by the supply <NUM>, while the previously stored voltage across capacitor <NUM> adds in series on top of this voltage, causing the voltage at node <NUM> to go above the battery supply voltage (e.g., to <NUM> volts in this instance). Capacitor <NUM> operates as a voltage source to the output stage, discharging its stored energy into inductor <NUM>, capacitor <NUM>, and subsequently the load <NUM>.

Referring to <FIG>, switch state <NUM> of the Zeta amplifier <NUM> is shown with switch <NUM> being turned off and switch <NUM> being turned on. With switch <NUM> turned off, Inductor <NUM> is no longer connected directly to power supply <NUM> so it is no longer being charged. The current through the inductor is reducing in magnitude and this will cause a self-induced voltage to develop across the inductor in the opposite direction (e.g., to -<NUM> Volts for <NUM>% duty cycle). This polarity-change across inductor <NUM> can be considered as being voluntary (a self-induced voltage rather than a forced voltage from another supply). The current through inductor <NUM> continues to flow in the same direction but is now decreasing in magnitude. This current flows through inductor <NUM>, capacitor <NUM> and switch <NUM> (which has been turned on). Node <NUM> is pulled below ground (e.g., to -<NUM> volts) which also pulls the (-) side of the capacitor <NUM> below ground. Node <NUM> is at ground potential due to the conducting of switch <NUM>. From these operations, capacitor <NUM> is charged to a potential of <NUM> V. Additionally, in switch state <NUM>, the inductor <NUM> transfers stored energy to capacitor <NUM>. The average voltage on the capacitor <NUM> is therefore 12V with the polarity as shown in the figure. In steady state conditions, at <NUM>% duty cycle, capacitor <NUM> can be considered as a voltage source with <NUM> volts across it. When returning to switch state <NUM> (shown in <FIG>), the voltage on node <NUM> returns to the level of the power supply <NUM> (e.g., battery voltage) since switch <NUM> is turned on.

Other operations also occur in switch state <NUM>; for example, inductor <NUM> discharges through switch <NUM>, capacitor <NUM>, and the load <NUM>. Since switch <NUM> is turned on and conducting, node <NUM> is at ground potential and the voltage across inductor <NUM> reverses to maintain current flow to capacitor <NUM>. At a duty cycle of <NUM>%, and based on the need to balance current on the inductor <NUM> and balance charge on capacitor <NUM>, the voltage reversal on the inductor and current flow reversal through the capacitor occur. The average common mode output capacitor <NUM> voltage must therefore equate the average coupling capacitor <NUM> voltage. The output common-mode voltage is the geometric mean of <NUM> volts and <NUM> volts, e.g. <NUM> volts.

The Zeta power converter <NUM> (located on the lower portion of the Zeta amplifier <NUM>) is driven <NUM>° out of phase relative to the Zeta power converter <NUM> (located on the upper portion of the Zeta amplifier <NUM>). Operating on the complementary cycle of the <NUM>% duty cycle, operations of the Zeta power converter <NUM> are similar to the operations of the Zeta power converter <NUM> but with an opposite phase.

Referring to <FIG>, the Zeta amplifier <NUM> being in switch state <NUM> is illustrated. In general, switch state <NUM> represents a transitional dead-time state between switch state <NUM> and switch state <NUM>. During switch state <NUM>, each of the switches <NUM>, <NUM>, <NUM>, and <NUM> are turned off (e.g., for a relatively short period). This switch state avoids current conducting from the power supply <NUM> to ground (e.g., shoot-through conduction flowing through coupling capacitor <NUM> or <NUM>) caused by overlapping conduction due to the switches being non-ideal. Also, during switch state <NUM>, the inductors and the capacitor continue to cause current flow even with all switches being turned off. This current may flow through the silicon substrate back-gate diodes of one or more of the FETs depending on the direction of current flow and node voltages from the previous state before turning off the switches. The magnitude and polarity of circuit node voltages during the dead time (state <NUM>) depend on the operating conditions at the time the input and output switches are all being turned off. The node voltages depend on the direction of the instantaneous currents through the inductors, capacitors and switches and whether the ripple currents toggle from positive to negative direction (or vice versa) during a full switching cycle or not. The conditions will also determine whether each switching edge is 'hard' (e.g. a forced switch node current commutation) or soft (e.g. an automatic switch node current commutation).

Considering the <NUM>% duty cycle (shown in <FIG>), the load current is low enough such that the ripple current in all inductors toggles from a positive to a negative polarity during each switching cycle. Only the positive output side converter <NUM> is considered in this description. Upon exiting state <NUM> and entering state <NUM>, switch <NUM> is on / conducting while switch <NUM> is off / not conducting. The node <NUM> voltage is 12V and node <NUM> voltage ~24V given that the capacitor has 12V across it. Current is flowing from the battery <NUM> into inductor <NUM> and current is flowing through capacitor <NUM> and inductor <NUM> towards the load. When switch <NUM> turns off, the current in inductor <NUM> starts reducing in magnitude and the voltage polarity reverses, maintaining the same current flow direction through inductor <NUM>. The current through switch <NUM> automatically commutates towards the capacitor and switch <NUM>. Switch <NUM> now supports the current through its back-gate diode as it was not turned on yet during state <NUM>. As a result, node voltage <NUM> will now automatically drop to -<NUM>. Node voltage <NUM> will automatically drop to -<NUM>. 7V because the capacitor <NUM> acts as a 12V voltage source. The output capacitances of switches <NUM> is charged and <NUM> is also discharged automatically through this current commutation process. The switch action does not introduce current spikes as a result and the switch action is considered "soft". Turning on switch <NUM> in state <NUM> (<FIG>) changes little to the state of the circuit other than enhancing switch <NUM> fully, thereby removing the final <NUM> V voltage drop across it.

Referring to <FIG>, another example is illustrated with different starting conditions. In particular, the duty cycle is now at <NUM>%. The average load current is towards the load. In this case, the current ripple in both the positive side Zeta converter inductors <NUM> and <NUM> is now strictly positive in polarity over the whole switching cycle. Only the positive output side converter <NUM> is considered in this description. Upon exiting state <NUM> (<FIG>) and entering state <NUM> (<FIG>), switch <NUM> is off / not-conducting while switch <NUM> is was on / conducting. The node <NUM> voltage is at -<NUM> V and node <NUM> voltage is at <NUM> V given that the capacitor has 29V across it. Current is not flowing from the battery <NUM> to converter <NUM>. Current is flowing through switch <NUM> and inductor <NUM> towards the load but decreasing in magnitude. When switch <NUM> also turns off in state <NUM>, the current in inductor <NUM> continues to reduce in magnitude and the voltage polarity across inductor <NUM> stays reversed, maintaining the same current flow direction through inductor <NUM>. This current is now pulled through the back-gate diode of switch <NUM>, which drops the node voltages at <NUM> and <NUM> an additional <NUM> V. Moving on from here to state <NUM> (<FIG>), When switch <NUM> is turned on, the current through inductor <NUM> commutates towards the switch. Only then can node voltage <NUM> changes from - <NUM> V to <NUM> V. This sudden discharged of the output capacitance from -<NUM> V to <NUM> V while the switch is turning on introduces a large current spike. The switch action is considered 'hard'. High switch loss is observed as the current commutation is now 'forced' e.g. not automatic. This condition is now different from the previous example due to different operating conditions. Furthermore, the voltage on node <NUM> rises to <NUM> V as the capacitor acts as a voltage source that stacks upon the voltage at node <NUM> when switch <NUM> is fully on. Switch <NUM> remains off and is not conducting any current. Switch <NUM> output capacitance is charged from <NUM> V to <NUM> V and introduces a current spike as well. The switch action is not automatic and considered 'hard' involving high loss.

The previous two examples cover a few of the possible operating conditions of the zeta amplifier during dead-time state <NUM>. More examples are possible, and each operating condition needs to be carefully considered for its discourse.

Referring to <FIG>, the Zeta amplifier <NUM> may be operated with other duty cycles. For example, when Zeta amplifier <NUM> is set with a duty cycle of approximately <NUM>%, the output assumes a <NUM> volt differential voltage with a positive polarity, which is twice the <NUM> volts value of the power supply <NUM>. Such an increase demonstrates the self-boosting ability of the Zeta amplifier <NUM>. Through the use of flux (volt-second) balance of the inductors and the charge balance of the capacitors as energy storing elements, the steady-state conditions can be quantified.

Referring to <FIG>, switch state <NUM> of the Zeta amplifier <NUM> is illustrated. Similar to <NUM>% duty cycle case (shown in <FIG>), inductor <NUM> is charged with the available voltage of the power supply <NUM> (e.g., the <NUM> volt battery). Due to the duty cycle of switch <NUM> now being <NUM>%, additional time is provided to the current of the inductor <NUM> to ramp to a larger level thus adding more energy. When switch <NUM> is turned off, maintaining volt-second balance, the discharge of the inductor <NUM> generally occurs faster, which produces <NUM> volts across inductor <NUM> based on geometric considerations of the dl/dt in the charge and discharge state of this inductor.

Referring to <FIG>, for state <NUM>, based on the voltage across inductor <NUM>, capacitor <NUM> charges to <NUM> volts since switch <NUM> connects the load side of capacitor <NUM> to ground. Further, since inductor <NUM> is charged for the same amount of time as inductor <NUM> and the need for volt-second balance in steady-state conditions, the voltage across inductor <NUM> is equivalent to the voltage across the inductor <NUM> (if both inductors <NUM> and <NUM> have equivalent inductance values). Based on the determined values, voltages at the nodes of the Zeta power converter <NUM> can be determined. A similar approach can be used for the Zeta power converter <NUM> (illustrated in the bottom half of the Zeta amplifier <NUM>).

Referring to <FIG> the three switch states are illustrated for the Zeta amplifier <NUM> operating at a duty cycle of <NUM>% (a gain of -<NUM>). Operations of the Zeta power converters <NUM> and <NUM> are similar to the operations of the power converters shown in <FIG> operating with a <NUM>% duty cycle. The ability to soft switch is maintained until the DC current in combination with ripple through inductor <NUM> becomes positive. Turning on switch <NUM> now forces the inductor <NUM> to switch polarity rather than it being facilitated by the polarity reversal of the current traversing though zero. At this point increased switching losses are experienced due to voltage stress across the switch <NUM> and the sudden discharging of the output capacitance of switch <NUM> while simultaneously charging the output capacitance of switch <NUM>.

Referring to <FIG>, two charts <NUM> and <NUM> are shown that present the small signal frequency response of the Zeta amplifier <NUM>. In particular, the magnitude of the control to output differential response of the amplifier is provided by chart <NUM> and the control to output differential phase response is provided by chart <NUM> In general, the responses (in particular the phase response) report steep features and peaky behavior. In the phase response, shown in chart <NUM>, a <NUM>° phase shift is experienced at higher frequencies (e.g., around <NUM>,<NUM>). Compared with the responses of a buck derived converter, one or more of the poles and zeros may change position with varying duty cycle. Compensation may be provided by one or more techniques. For example, a digital compensator can be incorporated (e.g., into a controller such as controller <NUM> shown in <FIG>) to dynamically track the poles and zeros to provide compensation and to improve bandwidth.

Features of the magnitude and phase responses (as highlighted by arrows <NUM> and <NUM>) can be clustered and pushed out to higher frequencies beyond the audio band to make sure they don't affect the frequency response negatively. For example, the features can be positioned at the edge of the <NUM>-<NUM> audio bandwidth for providing a relatively flat loop gain in the audio band. Features may be pushed out even further beyond the unity gain open loop bandwidth to avoid compensation of some poles and zeros all together. For example: the deep nulls in the response or right half plane poles.

<FIG> shows the common mode supply to output response of the Zeta amplifier (i.e., magnitude chart <NUM> and phase chart <NUM>). It should be noted that the common mode response represents the PSRR (power supply rejection ratio) of the Zeta amplifier. The small-signal gain in the audio band frequencies is higher than for the buck derived class-D amplifier. This results in lower PSRR due to the positive and negative outputs varying asymmetrically with varying duty cycle. The features in the supply to output response are closely related to the features found in the control to output response. When the features are moved and changed through component value manipulations in the control to output response, the features in the supply to output will also be manipulated in like manner. Chart <NUM> shows the peaky behavior that is observed in the Zeta amplifier's supply to output response. These peaks can be damped through the use of current feedback techniques.

Current feedback techniques may be used to synthesize resistances that will suppress high-Q resonances and associated sharp phase changes in the converter stages of the of the Zeta amplifier. These resonances and phase changes may become a challenge to closing the control loop with a voltage feedback compensator only in a stable manner. A possible implementation is shown in <FIG>. Block diagram <NUM> as shown in <FIG> however an additional current feedback loop is added. The current sensor measures the current through a component somewhere in the converter. The current feedback signal is compensated with a loop filter before it is summed into the modulator control input. The overall effect of this is that a synthetic resistance is added in series with the current sensed component which has a damping effect on any resonances inside the circuit. However, because the resistance is synthesized and not real, it generally does not generate any DC losses detrimental to the overall conversion efficiency. Typically, the current feedback signal is subtracted out of the input signal resulting in a loss of gain however, due to the boosting nature of the Zeta amplifier, this can be corrected for with an increased duty cycle range. More than one current sensing point may be used and be combined into one or more feedback signals. These feedback signals may sum into the modulator control input in differential mode and/or common mode sense.

To implement the design of the Zeta amplifier <NUM>, one or more techniques may be employed. For example, the design can be realized through a silicon (Si) diffusion process; however, other processes such as gallium-nitride (GaN) processes can be employed to use the benefits associated with GaN, being low RDS(ON) and low gate capacitance, and producing high speed operational devices. The output capacitance of a planar GaN HEMT is generally substantially higher than an equivalent vertical Si MOSFET. However, in a resonant design solution, the capacitance can be used to establish resonance and reduce the associated switching loss by establishing zero-voltage transition (ZVT) conditions.

Boost converter stages such as the Zeta power converters <NUM>, <NUM> are non-linear, and negative feedback can be employed to linearize the design for acceptable performance over the audio band. High loop gain across the audio band can be used to correct of the non-linear behavior.

Claim 1:
An apparatus comprising:
an amplifier (<NUM>, <NUM>) comprising:
a first Zeta converter (<NUM>, <NUM>) connected to a power supply (<NUM>) and a load (<NUM>);
a second Zeta converter (<NUM>, <NUM>) connected to the power supply and the load, the second Zeta converter being driven by a complementary duty cycle relative to the first Zeta converter; and
a controller (<NUM>) configured to provide an audio signal to the first Zeta converter and the second Zeta converter for delivery to the load,
wherein the controller is connected to the load to receive a voltage feedback signal and wherein the controller is further configured to receive a current feedback signal from a current sensor that measures a current through a current sensed component of at least one of the first Zeta converter and the second Zeta converter to synthesize a damping resistance in series with the current sensed component to suppress any natural frequencies in the converters