Patent Description:
<FIG> is a cross-sectional view of a packaged integrated circuit employing copper pillar bump flip-chip interconnect technology in some examples. Referring to <FIG>, an integrated circuit die <NUM> is packaged in a flip-chip semiconductor package <NUM>. The front side of the integrated circuit die <NUM>, including the active circuitry and the bond pads for external connections, is faced downward in the package. Copper pillar bumps <NUM> are formed on the bond pads of the integrated circuit <NUM> and are used as the electrical interconnects between the integrated circuit die <NUM> and a package substrate <NUM>, usually formed as a printed circuit board (PCB) substrate. The integrated circuit die <NUM> is flip-chip attached to the package substrate <NUM>. An underfiller material <NUM> and a dam <NUM> may be used in the flip-chip attach process.

The PCB package substrate <NUM> may be a single layer or a multi-layer PCB. The PCB package substrate <NUM> includes conductive traces printed thereon and formed in the PCB for receiving the copper pillar bumps formed on the integrated circuit die <NUM> and for electrically connecting the copper pillar bumps formed on the top side of the substrate to an array of solder balls <NUM> formed on the bottom side of the substrate. The solder balls <NUM> form the external connections of the semiconductor package <NUM>.

In the present illustration, the integrated circuit die is formed as a silicon on insulator integrated circuit. In the case that the integrated circuit die is used in high voltage applications, there can be significant charge build up on the insulator substrate on the backside of integrated circuit die <NUM>. In some examples, the backside of the integrated circuit die <NUM> needs to be grounded. Accordingly, a conductive top substrate <NUM> is formed on the backside of integrated circuit die <NUM> and attached to the backside through a conductive adhesive <NUM>. A bond wire <NUM> is used to electrically connect the top substrate <NUM> to the package substrate <NUM> for the electrical ground connection. The entire structure is then encapsulated in a mold compound <NUM> to form the semiconductor package <NUM>.

In the copper pillar bump flip-chip interconnect process, packaging failures due to die warpage have been observed. <FIG> illustrates the package failure mode due to die warpage in one example. In the flip-chip interconnect process, after the copper pillar bumps are formed on the wafer, the wafer is subjected to backgrinding to a certain desired die thickness. For example, the wafer may have a thickness of <NUM> and is background to about <NUM>. Then, the wafer is diced up into individual die <NUM>. After being diced up, certain stresses on the integrated circuit die <NUM> cause the die to warp, as shown in <FIG>. The warpage on the die <NUM> prevents the die from being properly attached to the package substrate <NUM>. In particular, due to the die warpage, some of the copper pillar bumps will not be able to make physical contact with the conductive traces on the package substrate <NUM>, leading to open connections at the corners of the die, as shown in <FIG>.

The die warpage issue typically affects integrated circuit die having a large die size, such as 10mmx10mm, and a thin die thickness, such as <NUM>. In some cases, the die warpage can be up to <NUM>, which is <NUM>% of the die thickness. The die warpage issue on integrated circuit dies with large die size but thin die thickness makes flip-chip bonding onto a printed circuit board substrate impossible.

Conventional solutions to the die warpage issue involve increasing the die thickness, such as to backgrind the wafer only to <NUM> or <NUM> thickness. However, a thicker die size is sometimes not desirable as the package thickness is also increased, making the semiconductor package undesirable for certain applications, such as in small mobile devices. In some cases, it is believed that the die warpage is due to the polyimide material applied to the front surface of the integrated circuit die during the back end processing to form the copper pillar bumps. Thus, some conventional solution to the die warpage issue involves using polyimide material with lower curing temperature or lower flex modulus property on the integrated circuit die. These substitution materials sometimes increase the cost of the semiconductor package.

For further information the reader is referred to the following background art.

<CIT> relates to a semiconductor device having a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than <NUM>, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

<CIT> relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming stress-reduced conductive joint structures.

<CIT> relates to a semiconductor package and a method of making a semiconductor package. The semiconductor packages comprises an anchor portion extending through at least one dielectric layer.

<CIT> relates to a wafer level package, and more particularly to a wafer level package structure avoiding the open circuit caused by the solder ball cracking due to temperature variation induced stress between the solder balls and a print circuit board. <CIT> relates to a structure of a conductive line, and more particularly to a conductive line with a buffer scheme and the method of forming the same.

The invention can be implemented in numerous ways.

In a preferred embodiment of the invention, a second organic insulation layer is used on top of the redistribution layer, the second organic insulation layer can also be patterned to cover areas surrounding the bond pads and the bump pads and to form islands of the second organic insulation layer. The islands of the second organic insulation layer may be offset from the islands of the organic insulation layer formed under the redistribution layer. In this manner, one or more organic insulation layers are used to provide stress relief from the copper pillar bump process. However, no large, continuous areas of the organic insulation layers are formed so that the stress induced to the semiconductor wafer by the organic insulation layers is significantly reduced.

In the present description, the organic insulation layer refers to the thin film organic insulating material applied to or coating a semiconductor wafer to protect the wafer during back end processing to form copper pillar bumps. The organic insulation layer is also referred to as a post wafer processing dielectric layer as the organic insulation layer is applied after the semiconductor wafer has completed the wafer fabrication process where the semiconductor wafer is formed with a final dielectric layer - the passivation layer - covering the entire surface of the semiconductor wafer and exposing only bond pads. More specifically, the passivation layer, being a silicon dioxide layer or a silicon nitride layer, covers all of the active circuitry of the integrated circuit dies formed on the semiconductor wafer with only the bond pads exposed. The back end processing of the semiconductor wafer involves forming copper pillar bumps on the exposed bond pads of the semiconductor wafer to enable the integrated circuit dies formed on the semiconductor wafer to be subsequently packaged, such as in a flip-chip semiconductor package. The organic insulation layer is formed on the finished semiconductor wafer before the copper pillar bumps are formed and is used to provide a mechanical stress buffer between the semiconductor wafer and the copper pillar bumps formed thereon. The organic insulation layer is typically a thin film polymer material, such as polyimide (PI) or polybenzoxazole (PBO).

In the conventional back end processing steps, the entire surface of the semiconductor wafer is coated with the organic insulating material with openings made on the bond pads for the copper pillar bumps. <FIG>, which includes <FIG>, illustrates the conventional back end processing steps for forming a copper pillar bump on a bond pad of the semiconductor wafer. <FIG>, which includes <FIG>, is a cross-sectional view of a copper pillar bump formed on a semiconductor wafer and a top view of an integrated circuit die having copper pillar bumps formed using the conventional back end processing steps of <FIG>. Referring to both <FIG> and <FIG>, after the front end wafer fabrication process, a semiconductor wafer <NUM> is formed with a passivation layer <NUM> formed on a semiconductor substrate <NUM> having active circuitry formed thereon (<FIG> shows only a portion of the semiconductor wafer <NUM> where a bond pad <NUM> is formed on the semiconductor substrate <NUM>. The semiconductor substrate <NUM> is covered entirely by the passivation layer <NUM> except for the exposed bond pad <NUM>. The bond pad <NUM> is typically an aluminum bond pad or copper bond pad.

At the start of the back end processing steps, the semiconductor wafer <NUM> is coated with an organic insulating material, forming an organic insulation layer <NUM> (<FIG>). More specifically, the copper pillar bump flip chip bonding process introduces a lot of stress to the integrated circuit die. To enhance reliability, a dielectric layer, typically an organic insulating material, is applied to the wafer to seal the bond pad openings before the copper pillar bumps are formed. The organic insulation layer <NUM> coats the wafer surface and exposes only the bond pad <NUM>. The organic insulating material is typically polyimide and the organic insulation layer <NUM> is referred herein as a polyimide layer.

In particular, the polyimide layer <NUM> is patterned, such as by using a mask to pattern a photoresist layer <NUM>, to form an opening <NUM> on the bond pad <NUM>. After the patterning process, the polyimide layer <NUM> covers the entire semiconductor wafer <NUM> except for the opening <NUM> on the bond pad <NUM> (<FIG>). Then, a seed metal layer <NUM> is deposited onto the semiconductor wafer <NUM> (<FIG>), such as by sputtering. The seed metal layer <NUM> is typically formed by sputtering of a titanium-copper (Ti-Cu) layer, or a titanium-nickel-copper (Ti-Ni-Cu) layer, or a titanium/tungsten-copper (TiW-Cu) layer, or an aluminum-nickel-copper (Al-Ni-Cu) layer, or a chromium-chromium/copper-coper (Cr-CrCu-Cu) layer. In other examples, the seed metal layer <NUM> can be deposited by electroless plating of copper to the wafer. The seed metal layer <NUM> is used as a plating seed layer to plate the metal and copper pillars to the final thickness of the pillars.

The copper pillar bump process can then begin. The semiconductor wafer <NUM> is coated with a photoresist layer <NUM> which is patterned to expose an area above the bond pad <NUM> (<FIG>). A copper pillar bump <NUM> is formed in the opening of the photoresist layer <NUM>, typically by metal plating (<FIG>). In the present example, the copper pillar bump <NUM> includes a lower copper layer <NUM>, a nickel adhesion layer <NUM>, and a solder cap layer <NUM>. After the metal plating process, the photoresist layer <NUM> is removed (<FIG>). Then, the seed metal layer <NUM> is etched to remove all exposed seed metal layer <NUM>. Thus, only the portion of the seed metal layer <NUM> under the copper pillar bump <NUM> remains (<FIG>). Then, the semiconductor wafer is subjected to a solder reflow process to complete the formation of the copper pillar bump <NUM>. More specifically, the solder reflow process round out the solder cap layer <NUM> to form a rounded solder cap for the copper pillar bump (<FIG>).

As a result of the conventional back end processing steps, the entire semiconductor wafer is coated with the polyimide layer except where the copper pillar bumps are formed. <FIG> is another cross-sectional view of the semiconductor wafer <NUM> in <FIG> and <FIG> showing a larger portion of the wafer with multiple copper pillar bumps <NUM> formed thereon. As shown in <FIG> and <FIG>, an integrated circuit die <NUM> formed on the semiconductor wafer <NUM> will have its entire surface covered by the polyimide layer <NUM> except at the bond pad areas <NUM> where the copper pillar bumps <NUM> are formed. The polyimide layer <NUM> is used as a barrier layer to protect the semiconductor wafer during the copper pillar bump process and to improve the reliability of the integrated circuit thus formed. However, the polyimide layer introduces stress to the semiconductor wafer, especially during the curing process.

More specifically, polyimide and silicon has a large mismatch in the coefficient of thermal expansion (CTE) with polyimide having a much larger thermal expansion and contraction over temperature as compared to silicon. For example, silicon has a CTE of 4ppm while polyimide has a CTE of 35ppm. The polyimide layer is deposited on the silicon wafer and then cured at high temperature, such as <NUM>. After curing and the temperature of the structure drops, the polyimide layer shrinks much more than the silicon wafer, thereby introducing stress into the silicon wafer. The stress induced in the silicon wafer may not be revealed until the wafer is background and diced up into individual integrated circuit die. Therefore, the wafer is processed through the copper pillar bump process as normal. After backgrinding and wafer dicing, the stress from the polyimide layer often causes the individual die to warp, rending it impossible to attach the die onto a package substrate (<FIG>).

In the above described examples, the copper pillar bump is formed directly on a bond pad. In other examples, the copper pillar bump process can use a redistribution process to form copper pillar bumps away from the bond pads. A redistribution layer (RDL) is a metal layer, such as copper, and is formed on the integrated circuit die to use as runners or traces to re-route bond pads to new bump locations. In this manner, the bump locations can be rearranged on the integrated circuit die and the locations of the copper pillar bumps are not restricted by the layout of the bond pads on the integrated circuit die. <FIG>, which includes <FIG>, is a cross-sectional view of a copper pillar bump formed on a redistribution layer and a top view of an integrated circuit die having copper pillar bumps formed on a redistribution layer in some examples. Referring to <FIG>, a semiconductor wafer is first coated with a first polyimide layer <NUM> which is patterned to expose the bond pad <NUM>. Then, the redistribution layer <NUM> is deposited onto the wafer and in the exposed bond pad area. The redistribution layer <NUM> is typically formed by plating of copper onto an underlying seed metal layer 38a. The redistribution layer <NUM> forms a metal trace to another location on the semiconductor wafer where the copper pillar bump <NUM> is to be formed. The semiconductor wafer is coated with a second polyimide layer <NUM> which is patterned to form an opening at a bump pad area for forming the copper pillar bump <NUM>. The copper pillar bump <NUM> can then be formed using the process described with reference to <FIG>. As shown in <FIG>, the integrated circuit die <NUM> has the two polyimide layers <NUM> and <NUM> covering all surfaces of the die except for the bond pads (the first polyimide layer) and the bump pad area (the second polyimide layer).

According to a semiconductor packaging method for forming copper pillar bumps, the organic insulation layer on the semiconductor wafer patterns only areas surrounding and in the vicinity of the copper pillar bumps only. The organic insulation layer is removed from all other areas of the semiconductor wafer. In this manner, the stress induced onto the semiconductor wafer by the organic insulation layer is significantly reduced or eliminated. The semiconductor packaging method of the present invention enables the use of the copper pillar bumps flip chip technology even for large die size and thin die thickness. For example, the semiconductor packaging method of the present invention can be applied to an integrated circuit die having a die size on the order of <NUM> by <NUM> and a die thickness of <NUM>. Die warpage is avoided by removing the organic insulating material from areas not needed as a barrier protection from the copper pillar bump processing.

<FIG> is a cross-sectional view of a semiconductor wafer having copper pillar bumps formed thereon. Referring to <FIG>, a semiconductor wafer <NUM> includes a semiconductor substrate <NUM> having active circuitry formed thereon. The semiconductor wafer <NUM> has completed front end wafer fabrication process and is covered by a passivation layer <NUM> as the final dielectric layer of the wafer fabrication process. The entire surface of the semiconductor wafer <NUM> is covered by the passivation layer <NUM> except for the bond pads <NUM> which are exposed for external connections. The semiconductor packaging method forms copper pillar bumps <NUM> on the bond pads <NUM>. In particular, an organic insulation layer <NUM> is first formed on the finished semiconductor wafer <NUM>. In particular, an organic insulation layer <NUM> is patterned to remove the organic insulation layer <NUM> from all areas except around and in the vicinity of the areas where the copper pillar bumps are to be formed. The copper pillar bumps <NUM> are then formed with each bump <NUM> formed on a seed metal layer <NUM> and each bump including a lower copper layer <NUM>, a nickel adhesion layer <NUM>, and a solder cap layer <NUM>.

As illustrated by a comparison between <FIG>, the semiconductor packaging method eliminates substantially all of the organic insulating materials from the wafer surface except under, around and in the vicinity of a copper pillar bump. Thus, instead of having the organic insulating material covering all of the semiconductor wafer as in the conventional method (<FIG>), the semiconductor packaging method forms the organic insulation layer so that the organic insulating material covers only a small portion of the semiconductor wafer. In this manner, the stress induced by the organic insulating material onto the semiconductor wafer is significantly reduced or eliminated and die warpage due to the stress is avoided.

<FIG>, which includes <FIG>, is a flowchart illustrating the semiconductor packaging method for forming copper pillar bumps. The semiconductor packaging method of <FIG> will be described with reference to the processing steps illustrated in <FIG> and the cross-sectional and top view illustrated in <FIG>. <FIG>, which includes <FIG>, illustrates the back end processing steps for forming a copper pillar bump on a bond pad of the semiconductor wafer using the semiconductor packaging method in <FIG>. <FIG>, which includes <FIG>, is a cross-sectional view of a copper pillar bump formed on a semiconductor wafer and a top view of an integrated circuit die having copper pillar bumps formed using the back end semiconductor packaging method of <FIG>. Referring to <FIG>, <FIG> and <FIG>, the semiconductor packaging method <NUM> starts with a semiconductor wafer <NUM> having completed front end wafer fabrication processes (<NUM>). After the front end wafer fabrication process, the semiconductor wafer <NUM> is formed with a passivation layer <NUM> formed on a semiconductor substrate <NUM> having active circuitry formed thereon (<FIG> shows only a portion of the semiconductor wafer <NUM> where a bond pad <NUM> is formed on the semiconductor substrate <NUM>. The semiconductor substrate <NUM> is covered entirely by the passivation layer <NUM> except for the exposed bond pad <NUM>. The bond pad <NUM> is typically an aluminum bond pad or copper bond pad.

The semiconductor packaging method <NUM> starts the back end processing by coating the semiconductor wafer <NUM> with an organic insulating material, forming an organic insulation layer <NUM> (<NUM>), as shown in <FIG>. The organic insulating material can be polyimide (PI) or polybenzoxazole (PBO) or other suitable thin film polymer material. The organic insulation layer <NUM> is then patterned, such as by using a mask to pattern a photoresist <NUM>, to remove the organic insulation layer <NUM> everywhere except in areas around the interface between the bond pad <NUM> and passivation layer <NUM> (<NUM>), as shown in <FIG>. More specifically, after the patterning process, the organic insulation layer <NUM> is removed everywhere on the wafer surface but covers an area around the edge of the bond pad <NUM> and the passivation layer <NUM>. The organic insulation layer <NUM> covers and surrounds the interface area of the bond pad and the passivation layer with an overlap width "w" sufficient to act as a stress buffer layer for the copper pillar bump to be formed. The bond pad <NUM> is exposed and the rest of the passivation layer <NUM> is also exposed.

Then, a seed metal layer <NUM> is deposited onto the semiconductor wafer <NUM> (<NUM>), as shown in <FIG>. For example, the seed metal layer <NUM> is formed by sputtering of a metal layer. In some examples, the seed metal layer <NUM> is formed by sputtering of a titanium-copper (Ti-Cu) layer, or a titanium-nickel-copper (Ti-Ni-Cu) layer, or a titanium/tungsten-copper (TiW-Cu) layer, or an aluminum-nickel-copper (Al-Ni-Cu) layer, or a chromium-chromium/copper-coper (Cr-CrCu-Cu) layer. In other examples, the seed metal layer <NUM> can be deposited by electroless plating of copper to the wafer. The seed metal layer <NUM> is used as a plating seed layer to plate the metal and copper pillars to the final thickness of the pillars. In some examples, the seed metal layer <NUM> has a thickness between <NUM> and <NUM>.

The method <NUM> then forms the copper pillar bump on the seed metal layer <NUM> and above the bond pad (<NUM>). In one example, the copper pillar bump can be formed using the method shown in <FIG> where the semiconductor wafer <NUM> is coated with a photoresist layer <NUM> which is patterned to expose an area above the bond pad <NUM> (<NUM>), as shown in <FIG>. The method <NUM> then forms a copper pillar bump structure <NUM> in the opening of the photoresist layer <NUM> (<NUM>), such as by use of metal plating, as shown in <FIG>. In the present embodiment, the copper pillar bump <NUM> includes a lower copper layer <NUM>, a nickel adhesion layer <NUM>, and a solder cap layer <NUM>. After the metal plating process, the photoresist layer <NUM> is removed (<NUM>) and the copper pillar bump is formed as shown in <FIG>. After the copper pillar bump <NUM> is formed, the method <NUM> continues with the etching of the seed metal layer <NUM> to remove all exposed seed metal layer (<NUM>). Thus, only the portion of the seed metal layer <NUM> under the copper pillar bump <NUM> remains, as shown in <FIG>. Then, the method <NUM> performs a solder reflow process on the semiconductor wafer <NUM> to complete the formation of the copper pillar bump <NUM> (<NUM>). More specifically, the solder reflow process round out the solder cap layer <NUM> to form a rounded solder cap for the copper pillar bump, as shown in <FIG>.

As a result of the semiconductor packaging method <NUM>, copper pillar bumps are formed on the semiconductor wafer <NUM> with only small portions of the wafer being covered by the organic insulating material, as shown in <FIG>. In particular, the organic insulation layer <NUM> is patterned to seal the bond pad and passivation layer interface. The organic insulation layer <NUM> can be patterned to have a circular shape or a square or rectangular shape conforming to the bond pads. The organic insulation layer <NUM> as thus formed provides the necessary protection to the semiconductor wafer <NUM> as the bond pad and passivation layer interface areas are the areas that need protection from the stress of the copper pillar bump flip chip bonding process and that can benefit from protection by the organic insulation layer. Other areas of the semiconductor wafer are covered by the passivation layer and do not need the protection of the organic insulation layer <NUM>. The semiconductor packaging method enables the use of copper pillar bump flip chip technology without compromising reliability while avoiding die warpage issues due to the stress of the organic insulation layer.

As described above, the semiconductor packaging method is applied to form copper pillar bumps that are located on the bond pads of a semiconductor wafer. The semiconductor packaging method of the present invention is applied to a copper pillar bump process using a redistribution layer to form the copper pillar bumps away from the bond pads of the semiconductor wafer. When the copper pillar bump is formed on a redistribution layer, the conventional process uses two polyimide layers, as described in <FIG>. According to embodiments of the present invention, the semiconductor packaging method is applied to a copper pillar bump process using a redistribution layer where one or more organic insulation layers are patterned so that no large, continuous areas of the organic insulation layers are formed. In some embodiments, the topmost organic insulation layer is eliminated entirely.

<FIG>, which includes <FIG>, is a cross-sectional view of a copper pillar bump using a redistribution layer and a top view of an integrated circuit die formed using the semiconductor packaging method in one embodiment of the present invention. <FIG> is a flowchart illustrating the semiconductor packaging method for forming copper pillar bumps using a redistribution layer in embodiments of the present invention. Referring to <FIG> and <FIG>, the semiconductor packaging method <NUM> of the present invention starts with a semiconductor wafer <NUM> having completed front end wafer fabrication processes (<NUM>). After the front end wafer fabrication process, the semiconductor wafer <NUM> is formed with a passivation layer <NUM> formed on a semiconductor substrate <NUM> having active circuitry formed thereon. <FIG> shows only a portion of the semiconductor wafer <NUM> where a bond pad <NUM> is formed on the semiconductor substrate <NUM>. The semiconductor substrate <NUM> is covered entirely by the passivation layer <NUM> except for the exposed bond pad <NUM>. The bond pad <NUM> is typically an aluminum bond pad or copper bond pad.

The semiconductor packaging method <NUM> starts the back end processing by coating the semiconductor wafer <NUM> with an organic insulating material, forming a first organic insulation layer <NUM> (<NUM>). The organic insulating material can be polyimide (PI) or polybenzoxazole (PBO) or other suitable thin film polymer material. The first organic insulation layer <NUM> is then patterned, such as by using a mask to pattern a photoresist, to remove the first organic insulation layer <NUM> everywhere except in areas around the interface between the bond pad <NUM> and passivation layer <NUM> and in an area forming the bump pad (<NUM>). The first organic insulation layer <NUM> is patterned to seal the bond pad and passivation layer interface and to form a buffer layer as a bump pad for the copper pillar bump to be formed. The first organic insulation layer <NUM> is further patterned to form islands of the organic material along the path of the redistribution layer to be formed. The islands of organic material may have a size of around <NUM> to <NUM>. More specifically, the organic insulation layer <NUM> remains in areas to act as a stress buffer layer for the copper pillar bump to be formed. The bond pad <NUM> is exposed and the rest of the passivation layer <NUM> is also exposed, as shown in <FIG>.

Then, a first seed metal layer 38a is deposited onto the semiconductor wafer <NUM> (<NUM>). In some examples, the first seed metal layer 38a is formed by sputtering of a metal layer, in the same manner as described above with reference to <FIG>. A redistribution layer <NUM> is then formed on the semiconductor wafer <NUM>, on top of the first seed metal layer 38a (<NUM>). In some examples, the semiconductor wafer <NUM> is patterned using a photoresist to define areas where the runners or tracers of the redistribution layer are to be formed. Then, a plating process is used to form the redistribution metallization on the first seed metal layer 38a. The first seed metal layer 38a is etched at this time to remove the first seed metal layer everywhere except under the redistribution layer <NUM>. In some examples, the first seed metal layer 38a has a thickness between <NUM> to <NUM>. Meanwhile, the redistribution layer has a thickness between <NUM>-<NUM>.

The method <NUM> may continue with forming a second organic insulation layer <NUM> on the semiconductor wafer <NUM> (<NUM>). The second organic insulation layer <NUM> is patterned in a manner similar to the first organic insulation layer (<NUM>). In the example shown in <FIG>, the second organic insulation layer <NUM> is formed covering the bond pad and defining a bump pad which exposes the redistribution layer <NUM> and on which the copper pillar bump will be formed. Furthermore, the second organic insulation layer <NUM> is patterned to form islands of organic insulation material along the path of the redistribution layer formed. The islands of the second organic insulation layer may be offset from the islands of the first organic insulation layer, as shown in <FIG>.

According to embodiments of the present invention, the first and second organic insulation layers are patterned so that sufficient areas of the organic insulation material are provided for stress relief from the copper pillar bump process but no large, continuous areas of the organic insulation material are formed to induce stress into the semiconductor wafer. The pattern, size and shape of the organic insulation layers <NUM> and <NUM> formed on the semiconductor wafer <NUM> in <FIG> are illustrative only and are not intended to be limiting. Other shapes, sizes and pattern of the organic insulation layers may be used to achieve stress relief desired without inducing additional stress into the wafer.

The method <NUM> continues with depositing a second seed metal layer 38b on the semiconductor wafer <NUM> (<NUM>). The method <NUM> then forms the copper pillar bump on the seed metal layer 38b and above the bump pad (<NUM>). In one example, the copper pillar bump can be formed using the method shown in <FIG> and described above. After the copper pillar bump <NUM> is formed, the method <NUM> continues with the etching of the seed metal layer 38b to remove all exposed seed metal layer 38b (<NUM>). Thus, only the portion of the seed metal layer 38b under the copper pillar bump <NUM> remains, as shown in <FIG>. Then, the method <NUM> performs a solder reflow process on the semiconductor wafer <NUM> to complete the formation of the copper pillar bump <NUM> (<NUM>). More specifically, the solder reflow process round out the solder cap layer to form a rounded solder cap for the copper pillar bump.

In an alternate embodiment of the present invention, the semiconductor package method is applied to form a copper pillar bump using a redistribution layer where the second organic insulation layer is entirely omitted, as shown in <FIG>, which includes <FIG>, is a cross-sectional view of a copper pillar bump using a redistribution layer and a top view of an integrated circuit die formed using the semiconductor packaging method in an alternate embodiment of the present invention. <FIG> is a flowchart illustrating the semiconductor packaging method for forming copper pillar bumps using a redistribution layer in embodiments of the present invention. Referring to <FIG> and <FIG>, the semiconductor packaging method <NUM> of the present invention starts with a semiconductor wafer <NUM> having completed front end wafer fabrication processes (<NUM>). After the front end wafer fabrication process, the semiconductor wafer <NUM> is formed with a passivation layer <NUM> formed on a semiconductor substrate <NUM> having active circuitry formed thereon. <FIG> shows only a portion of the semiconductor wafer <NUM> where a bond pad <NUM> is formed on the semiconductor substrate <NUM>. The semiconductor substrate <NUM> is covered entirely by the passivation layer <NUM> except for the exposed bond pad <NUM>. The bond pad <NUM> is typically an aluminum bond pad or copper bond pad.

The semiconductor packaging method <NUM> starts the back end processing by coating the semiconductor wafer <NUM> with an organic insulating material, forming a first organic insulation layer <NUM> (<NUM>). The organic insulating material can be polyimide (PI) or polybenzoxazole (PBO) or other suitable thin film polymer material. The first organic insulation layer <NUM> is then patterned, such as by using a mask to pattern a photoresist, to remove the first organic insulation layer <NUM> everywhere except in areas around the interface between the bond pad <NUM> and passivation layer <NUM> and in an area forming the bump pad (<NUM>). The first organic insulation layer <NUM> is further patterned to form islands of the organic material along the path of the redistribution layer to be formed. In one embodiment, the first organic insulation layer <NUM> is patterned in the same manner as described above with reference to <FIG>.

Then, a first seed metal layer 38a is deposited onto the semiconductor wafer <NUM> (<NUM>), such as by sputtering. A redistribution layer <NUM> is then formed on the semiconductor wafer <NUM>, on top of the first seed metal layer 38a (<NUM>). In some examples, the semiconductor wafer <NUM> is patterned using a photoresist to define areas where the runners or tracers of the redistribution layer are to be formed. Then, a plating process is used to form the redistribution metallization on the first seed metal layer 38a. The first seed metal layer 38a is etched at this time to remove the first seed metal layer everywhere except under the redistribution layer <NUM>.

The method <NUM> then continues with depositing a second seed metal layer 38b on the semiconductor wafer <NUM> (<NUM>), without using any more organic insulation layers. The method <NUM> then forms the copper pillar bump on the seed metal layer 38b and above the bump pad (<NUM>). In one example, the copper pillar bump can be formed using the method shown in <FIG> and described above. After the copper pillar bump <NUM> is formed, the method <NUM> continues with the etching of the seed metal layer 38b to remove all exposed seed metal layer 38b (<NUM>). Thus, only the portion of the seed metal layer 38b under the copper pillar bump <NUM> remains, as shown in <FIG>. Then, the method <NUM> performs a solder reflow process on the semiconductor wafer <NUM> to complete the formation of the copper pillar bump <NUM> (<NUM>). More specifically, the solder reflow process round out the solder cap layer to form a rounded solder cap for the copper pillar bump.

In the embodiment shown in <FIG>, the copper pillar bump <NUM> is formed on the redistribution layer <NUM> without the use of a second organic insulation layer. Although the redistribution layer <NUM> is exposed in the semiconductor wafer in this packaging stage, subsequent packaging process will encapsulate the integrated circuit die, such as using an epoxy material, thereby sealing and protecting the redistribution layer.

Claim 1:
A method (<NUM>, <NUM>) of forming a copper pillar bump semiconductor package, comprising:
providing a finished semiconductor wafer (<NUM>, <NUM>) comprising a semiconductor substrate (<NUM>) having a passivation layer (<NUM>) formed of silicon dioxide or silicon nitride and formed thereon covering a surface of the semiconductor substrate (<NUM>) and exposing only one or more bond pads (<NUM>);
forming a first organic insulation layer (<NUM>) on the semiconductor wafer (<NUM>, <NUM>);
patterning the first organic insulation layer (<NUM>) to cover a first area at an interface of the bond pad (<NUM>) and the passivation layer (<NUM>), to cover a second area of a bump pad to be formed, and to form islands of the first organic insulation layer along a path of a redistribution layer (<NUM>) to be formed from the bond pad (<NUM>) to the bump pad, the first organic insulation layer (<NUM>) being removed from the bond pad (<NUM>) and from the remaining area of the semiconductor wafer (<NUM>, <NUM>) outside the first area, the second area and the islands of first organic insulation layer (<NUM>);
forming a first seed metal layer (38a) on the first organic insulation layer (<NUM>) and the semiconductor wafer (<NUM>, <NUM>);
forming the redistribution layer (<NUM>) on the semiconductor wafer (<NUM>, <NUM>) over the bond pad (<NUM>) and the first organic insulation layer (<NUM>), the redistribution layer (<NUM>) being formed to include the bump pad being spaced apart from the bond pad (<NUM>) and a conductive trace connecting the bond pad (<NUM>) to the bump pad, the bump pad being formed over the second area of the first organic insulation layer (<NUM>) and the conductive trace being formed over the islands of the first organic insulation layer (<NUM>);
removing the first seed metal layer (38a) not formed under the redistribution layer (<NUM>);
forming a second seed metal layer (38b) on the redistribution layer (<NUM>) and the semiconductor wafer (<NUM>, <NUM>);
forming a copper pillar bump (<NUM>) on the second seed metal layer (38b) and above the bump pad;
removing the second seed metal layer (38b) not formed under the copper pillar bump (<NUM>); and
reflowing the copper pillar bump (<NUM>) to form a rounded solder cap for the copper pillar bump (<NUM>) by rounding out a solder cap layer (<NUM>).