Patent Description:
Deep learning is a machine learning method based on artificial neural networks inspired by information processing in biological systems. Deep learning may be used in a wide spectrum of applications, including image processing, machine translation, speech recognition, and many others. In each of these domains, deep neural networks achieve superior accuracy through the use of very large and deep models. These deep models may include reduced-precision methods for data representation and computation. <NPL>") discloses a 2T2R ReRAM structure that supports ternary content addressable memory (TCAM), logic in-memory operations, and in-memory dot product for Deep Neural Networks (DNNs) besides the normal non-volatile memory (NVM) functionality. <NPL>") discloses a bit cell featuring two-transistor-two-resistor (2T2R) architecture and a TaO -based ReRAM stack.

According to the present invention there are provided a circuit, and a method according to the independent claims.

The following detailed description, given by way of example and not intend to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:.

The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiment set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

For purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

Deep learning is a machine learning method based on artificial neural networks. Deep learning may be used in a wide spectrum of applications, including image processing, machine translation, speech recognition, and many others. In each of these domains, deep neural networks achieve superior accuracy through the use of very large and deep models. These deep models may include reduced-precision methods for data representation and computation. Computation for deep neural networks may include both training and forward inference.

Multiplication operations (including convolution and matrix multiplication) are one of the most area and power consuming components in hardware implementation of deep neural networks. Recent advances in reduced-precision optimization suggest that at least a portion of the multiplication operations may be performed at lower precision. This means that the multiplication operations may be performed with a fewer number of bits, without compromising the end-to-end accuracy. This provides opportunities for power and/or area savings by employing analog devices such as resistive random access memory (RRAM) for weight storage. Further, it is desirable to employ analog devices (i.e. memory elements) with multiple (more than two) states, to increase the memory density for a given memory cell or a given memory design.

Conventional memory elements, in practice, are dual state, because they either have a state <NUM> or a state <NUM>. These conventional memory elements cannot have more than two states because of reliability issues. As a result, conventional memory elements may be limited by the practical number of states (typically two).

In theory, increasing the number of memory elements per cell may increase the effective number of states per cell. For example, having two memory elements in each memory cell may increase the number of states from two states to four states, given that each memory element has two states. The two memory elements may be combined to obtain four states by using mathematical permutations of their two states. For example, if the first memory element has a state <NUM>, and the second memory element has a state <NUM>, then the combination of the two memory element states may provide memory cell State <NUM>. If the first memory element has a state <NUM> and the second memory element has a state <NUM>, then the combination of the two memory element states may provide memory cell State <NUM>. If the first memory element has a state <NUM> and the second memory element has a state <NUM>, then the combination of the two memory element states may provide memory cell State <NUM>. If the first memory element has a state <NUM> and the second memory element has a state <NUM>, then the combination of the two memory element states may provide memory cell State <NUM>.

In practice however, additional circuitry and processors such as, for example, transistors, are needed to combine the states of two or more memory elements in a useable way that may then be deployed. Having additional transistors, and corresponding wires, may increase the footprint of the circuit thus reducing memory density. The result may be a single memory cell that includes more than two states but whose footprint is larger than two memory cells, where each cell has two states. As such, there exists a need for a memory cell that includes more than two states and that is smaller than the footprint of two memory cells combined.

Embodiments of the present invention provide a new circuit structure. The new circuit structure is a cross-point memory array that includes a plurality of enhanced state dual memory cells. Each of the dual memory cells includes two transistors and two memory elements. As such, the memory cell may also be referred to as a 2T2R cell. The cross-point memory array, having a plurality of the 2T2R cells may increase the effective number of states per cell when compared to a conventional memory array. In an embodiment, the transistors within the memory cell are configured as complementary pass gates (transmission gates). In an embodiment, the memory cells are configured as RRAM/pass-gate/RRAM vertically-stacked structures thus minimizing the cell footprint and achieving a high density of bits per area.

<FIG> illustrate an exemplary circuit structure that includes a plurality of memory cells. Each memory cell includes two transistors integrated with two memory elements.

Referring now to <FIG>, a memory array <NUM> is shown, in accordance with an embodiment. Although the memory array <NUM> includes two rows and four columns, it should be appreciated that embodiments of the present invention may include the memory array <NUM> with any number of rows and columns. The memory array <NUM> includes a plurality of bit lines <NUM>, a plurality of word lines <NUM>, a plurality of select lines <NUM>. The bit lines <NUM> and select lines <NUM> run parallel to each other and are perpendicular to the word lines <NUM>. The plurality of word lines <NUM> intersect the plurality of bit lines <NUM> and the plurality of select lines <NUM>. The memory array <NUM> also includes a plurality of memory cells <NUM>. Each memory cell <NUM> includes a complimentary pair of transistors 108a, 108b, a first memory element 110a, and a second memory element 110b. Although eight memory cells <NUM> are shown, it should be appreciated that embodiments of the present invention may include any number of memory cells <NUM>.

As stated above, each memory cell <NUM> includes a complimentary pair of transistors 108a, 108b. The transistors 108a, 108b may be bipolar junction transistors (BJTs) or junction field-effect transistors (JFETs). In a preferred embodiment, the transistors 108a, 108b are a complimentary pair of BJTs such that transistor 108a is an NPN type and transistor 108b is a PNP type. In an alternative embodiment, the transistors 108a, 108b are a complimentary pair of JFETs such that transistor 108a is an n-channel JFET (nJFET) and transistor 108b is a p-channel JFET (pJFET). In an embodiment, the transistors 108a, 108b are configured as complementary transmission gates. In an embodiment, the transistor 108b in the memory cell <NUM> and the transistor 108a in a memory cell adjacent to the memory cell <NUM> have a base or a gate terminal connected to the same respective word line 104b. The transistor 108a is an opposite channel type than the transistor 108b.

The first and second memory elements 110a, 110b may be any type of memory element such as, for example, RRAM, phase change memory, magnetic random access memory, or the like. The first memory element 110a is connected between the bit line 102a and a first shared collector emitter terminal (in BJT embodiments) or source drain terminal (in JFET embodiments) of the complimentary pair of transistors 108a, 108b. The second memory element 110b is connected between the select line 106a and a second shared collector emitter or source drain terminal of the complimentary pair of transistors 108a, 108b.

Referring now to <FIG>, an example of a programming, or writing, operation of the first memory element 110a within the memory array <NUM> is shown, in accordance with an embodiment. Embodiments of the present invention provide a method of programming the first memory element 110a without substantially disturbing the second memory element 110b within the memory cell <NUM>. During the programming operation, resistance of the first memory element 110a is decreased to create the programmed state of the memory element (which may be referred to as, for example, <NUM>).

To program the first memory element 110a, a first write voltage is applied to the bit line 102b that is connected to the first memory element 110a. In an embodiment, the word line 104c is connected to the base of the PNP transistor 108b. In an alternative embodiment, the word line 104c is connected to the gate of the pJFET transistor 108b. The first write voltage is a positive supply voltage V+. A second write voltage is applied to the word line 104c. The second write voltage is a negative supply voltage V-. The first write voltage is sufficiently larger than the second write voltage to forward bias the base or the gate junction of the transistor 108b, allowing for the first memory element 110a to be selected to be programmed. For example, if the voltage drop across the forward biased junction is approximately <NUM> volts (typical for a silicon p-n junction), the program voltage selectively applied across the first memory element 110a will be approximately V+ - V- - <NUM> volts.

During the programming of the first memory element 110a as described above, in order to minimize disturbing the second memory element 110b as well as all other memory elements in the rest of memory cells, a first and second intermediate voltages may be applied to certain parts of the memory array <NUM>. In an embodiment, the first intermediate voltage is applied to the select line 106b that is connected to the second memory element 110b. In an alternative embodiment, the select line 106b is connected to a high impedance. The second intermediate voltage is applied to the remaining bit lines <NUM>, word lines <NUM>, and select lines <NUM>. For example, as illustrated in <FIG>, the select line 106b may either be connected to the first intermediate voltage Vm or to a float, which refers to the high impedance. The second intermediate voltage, V<NUM>, is applied to the bit line 102a, the select line 106a, and the word lines 104a, 104b, 104d, and 104e. As stated above, the first write voltage V+ is applied to the bit line 102b and the second write voltage V- is applied to the word line 104c. In this example, voltages are chosen as follows: <MAT> As such, the first write voltage is greater than the first intermediate voltage, the first intermediate voltage is greater than or equal to the second intermediate voltage, and the second intermediate voltage is greater than the second write voltage. As a result, the bias voltages across all memory elements except the first memory element 110a are either negligible, or sufficiently smaller than V+ - V- to not substantially alter their states. In one embodiment, Vm and V<NUM> are both <NUM> volts (i.e. ground potential). In another embodiment, V+ = -V-. In yet another embodiment, the bit line 102a and/or the select line 106a are connected to a float (high impedance) instead of V<NUM>. Further variations and bias configurations may also be contemplated.

As stated above, during the programming operation of the first memory element 110a, current flows through the first memory element 110a and the emitter-base or source-gate junction of transistor 108b. The transistor 108b acts as a two-terminal device during this operation. By choosing the different write and intermediate voltages, described above, the first memory element 110a may be programmed to a desired value without disturbing the second memory element 110b within the memory cell <NUM> or any other memory elements within the other memory cells within the memory array <NUM>. As a result, the first memory element 110a programmed independently.

Referring now to <FIG>, an example of an erase operation of the first memory element 110a within the memory array <NUM> is shown, in accordance with an embodiment. The erase operation is similar to the write operation with opposite voltage polarities transferred across the first memory element 110a. The write operation of the first memory element 110a, illustrated by <FIG>, may be performed via the PNP BJT transistor 108b, whereas the erase operation of the first memory element 110a, illustrated by <FIG>, may be performed via the NPN BJT transistor 108a.

The erase operation independently erases the state of only the first memory element 110a. All other memory elements, including the second memory element 110b within the memory cell <NUM>, are substantially unaffected by this operation. To erase the state of the first memory element 110a, its resistance is increased. This is accomplished by applying a first erase voltage to the word line 104b. The word line 104b is connected to the transistor 108a. In an embodiment, if the transistor 108a is an NPN BJT transistor then the word line 104b is connected to the base of said NPN BJT transistor. In an alternative embodiment, if the transistor 108b is an nJFET transistor, then the word line 104b is connected to the gate of said nJFET transistor. The transistor 108a is connected to the first memory element 110a. The first erase voltage is a positive supply voltage V+. In addition to the first erase voltage, a second erase voltage is applied to the bit line 102b. The bit line 102b is connected to the top terminal of the first memory element 110a. The second erase voltage is a negative supply voltage V-. The first erase voltage is sufficiently larger than the second erase voltage to forward bias the base or the gate junction of the transistor 108b, allowing for the first memory element 110a to be selected to be erased. For example, if the voltage drop across the forward biased junction is approximately <NUM> volts (typical for a silicon p-n junction), the erase voltage selectively applied across the first memory element 110a will be approximately V+ - V- - <NUM>. <NUM> volts.

During the erasing of the first memory element 110a as described above, in order to minimize disturbing the second memory element 110b as well as all other memory elements in the rest of memory cells, a first and second intermediate voltages may be applied to certain parts of the memory array <NUM>. In an embodiment, the first intermediate voltage is applied to the select line 106b that is connected to the second memory element 110b. In an alternative embodiment, the select line 106b is connected to a high impedance. The second intermediate voltage is applied to the remaining bit lines <NUM>, word lines <NUM>, and select lines <NUM>. For example, as illustrated in <FIG>, the select line 106b may either be connected to the first intermediate voltage <MAT> or to a float, which refers to the high impedance. The second intermediate voltage, V<NUM>, is applied to the bit line 102a, the select line 106a, and the word lines 104a, 104c, 104d, and 104e. As stated above, the first erase voltage V+ is applied to the word line 104b and the second erase voltage V- is applied to the bit line 102b. In this example, voltages are chosen as follows: <MAT> As such, the first erase voltage is greater than the second intermediate voltage, the second intermediate voltage is greater than or equal to the first intermediate voltage, and the first intermediate voltage is greater than the second erase voltage. As a result, the bias voltages across all memory elements except the first memory element 110a are either negligible, or sufficiently smaller than V+ - V- to not substantially alter their states. In one embodiment, <MAT> and V<NUM> are both <NUM> volts (i.e. ground potential). In another embodiment, V+ = -V-. In yet another embodiment, the bit line 102a and/or the select line 106a are connected to a float (high impedance) instead of V<NUM>. Further variations and bias configurations may also be contemplated. It should be appreciated that the V+and V- used for the erasing of a state of a memory element may be , and typically are, different from the V+ and V- used for the writing of a state of a memory element. Further, other voltages V<NUM> or <MAT> may also be different.

Referring now to <FIG>, an example of a writing operation of the second memory element 110b within the memory array <NUM> is shown, in accordance with an embodiment. The writing, or programming, of the second memory element 110b is similar to the writing operation of the first memory element 110a, described herein with reference to <FIG>. In the example illustrated in <FIG> the first memory element 110a is written via the transistor 108b whereas, in the example, illustrated in <FIG>, the second memory element 110b is written via the transistor 108a.

In an embodiment, in order to write, or program, the second memory element 110b without substantially disturbing the first memory element 110a within the memory cell <NUM>, or any other memory element within the memory array <NUM>, the first and second write voltages are applied to the word line 104b and the select line 106b, respectively. As described herein with respect to <FIG>, the word line 104b may either be connected to the gate of an nJFET transistor 108a, or to the base of an NPN BJT transistor 108a. The transistor 108a is connected to the second memory element 110b. The select line 106b is connected to the bottom terminal of the second memory element 110b.

During the programming of the second memory element 110b, , the first and second intermediate voltages may be applied to certain bit lines <NUM>, word lines <NUM>, and select lines <NUM>. In an embodiment, the first intermediate voltage is applied to the bit line 102b, which is connected to the top terminal of the first memory element 110a. In an alternative embodiment, the bit line 102b is connected to a high impedance. The second intermediate voltage is applied to the rest of the bit lines <NUM>, word lines <NUM>, and select lines <NUM>. For example, as illustrated in <FIG>, the bit line 102b may either be connected to the first intermediate voltage <MAT> or to a float, which refers to the high impedance. The second intermediate voltage, V<NUM>, is applied to the bit line 102a, the select line 106a, and the word lines 104a, 104c, 104d, and 104e. As stated above, the first write voltage V+ is applied to the word line 104b and the second write voltage V- is applied to the select line 106b. In this example, voltages are chosen as follows: <MAT> As such, the first write voltage is greater than the second intermediate voltage, the second intermediate voltage is greater than or equal to the first intermediate voltage, and the first intermediate voltage is greater than the second write voltage.

Having the first write voltage greater than the second write voltage allows for the second memory element 110b to be selected for the writing operation. The first write voltage is sufficiently larger than the second write voltage to forward bias the base or the gate junction of the transistor 108a. For example, the write voltage selectively applied across the second memory element 110b may be approximately V+ - V- - <NUM>. <NUM> volts. As such, the current flows through the base-emitter or gate-source junction of transistor 108a to the second memory element 110b. The transistor 108a acts as a two terminal device during this operation. When the current flows through the second memory element 110b, the second memory element 110b may be programmed to the desired state without substantially disturbing any other memory elements within the memory array <NUM> or the first memory element 110a within the memory cell <NUM>. As such, the second memory element 110b may be independently programmed.

Referring now to <FIG>, an example of an erase operation of the second memory element 110b within the memory array <NUM> is shown, in accordance with an embodiment. The erasing of the second memory element 110b is similar to the erasing operation of the first memory element 110a, described herein with reference to <FIG>. In the example, illustrated in <FIG>, the first memory element 110a is erased via the transistor 108a whereas, in the example, illustrated in <FIG>, the second memory element 110b is erased via the transistor 108b. As stated above with respect to <FIG>, embodiments of the present invention provide a method of independently erasing the state of one memory element within the memory array <NUM>.

With continued reference to <FIG>, to erase the state of the second memory element 110b, the first erase voltage V+ is applied to the select line 106b that is connected to the bottom terminal of the second memory element 110b, and the second erase voltage V- is applied to the word line 104c. In an embodiment, the word line 104c is connected to the base of the PNP BJT transistor 108b. In an alternative embodiment, the word line 104c is connected to the gate of the pJFET transistor 108b. In both embodiments, the transistor 108b is connected to the second memory element 110b. The first erase voltage is sufficiently larger than the second erase voltage to forward bias the base or the gate junction of the transistor 108b. For example, the erase voltage selectively applied across the second memory element 110b may be approximately V+ - V- - <NUM> volts. As such, the current flows from the second memory element 110b through the emitter-base or source-gate junction of transistor 108b. The transistor 108b acts as a two terminal device during this operation. When the current flows through the second memory element 110b, the second memory element 110b may be erased to the desired state without substantially disturbing any other memory elements within the memory array <NUM> or the first memory element 110a within the memory cell <NUM>. As such, the second memory element 110b may be independently erased.

In addition to the first and second erase voltages, the first and second intermediate voltages may also be applied to certain bit lines <NUM>, word lines <NUM>, and select lines <NUM>. In an embodiment, the first intermediate voltage is applied to the bit line 102b, which is connected to the top terminal of the first memory element 110a. In an alternative embodiment, the bit line 102b is connected to a high impedance. The second intermediate voltage is applied to the bit line 102a, word lines 104a, 104b, 104d, 104e, and select line 106a.

In the example illustrated in <FIG>, voltages are chosen as follows: <MAT> As such, the first erase voltage is greater than the first intermediate voltage, the first intermediate voltage is greater than or equal to the second intermediate voltage, and the second intermediate voltage is greater than the second erase voltage.

Referring now to <FIG>, an example of a reading operation of the memory cell <NUM> within the memory array <NUM> is shown, in accordance with an embodiment. In order to read the memory cell <NUM>, two pairs of read voltages, with the right values in relation to each other, are applied to the memory array <NUM>. The first pair of voltages may include a first read voltage, <MAT>, and a second read voltage, <MAT>. The second pair of voltages may include a first read voltage, <MAT>, and a second read voltage <MAT>. The first read voltage <MAT> of the first pair of read voltages is applied to the bit line 102b that is connected to the first memory element 110a. The second read voltage <MAT> of the first pair of voltages is applied to the select line 106b that is connected to the second memory element 110b. Further, the first read voltage <MAT> of the second pair of read voltages is applied to the word line 104b that is either connected to the base of the NPN BJT transistor 108a, or to the gate of the nJFET transistor 108a. The second read voltage <MAT> of the second pair of read voltages is applied to the word line 104c that is either connected to the base of the PNP BJT transistor 108b, or to the gate of the pJFET transistor 108b. In addition to the two pairs of read voltages, an intermediate voltage is also applied to the rest of the bit lines <NUM>, word lines <NUM>, and select lines <NUM>. As such, bit line 102a, word lines 104a, 104d, 104e, and select line 106a are connected to the intermediate voltage. In some embodiments, the intermediate voltage V<NUM> is the ground voltage (i.e. zero volts).

In the example illustrated in <FIG> the read voltages are chosen as follows: <MAT> As such, the first read voltage of the first pair of read voltages is greater than the first read voltage of the second pair of read voltages, the first read voltage of the second pair of read voltages is greater than the intermediate voltage, the intermediate voltage is greater than the second read voltage of the second pair of read voltages, and the second read voltage of the second pair of read voltages is greater than the second read voltage of the first pair of read voltages. During the read operation, transistors 108a and 108b are biased in the linear (triode) region and the read current flowing through the memory elements 110a and 110b and measured by the external circuitry is <MAT> where Von is the voltage drop across the collector-emitter or drain-source of the parallel-connected transistors 108a and 108b, and R<NUM> and R<NUM> are the resistance values (i.e. previously programmed states) of the memory elements 110a and 110b, respectively. As known, Von is small in the triode region, particularly for a complementary pair of parallel-connected pass transistors; therefore, <MAT> which is inversely proportional to R<NUM> + R<NUM>, the sum of the resistance values of the memory elements 110a and 110b. As such, R<NUM> + R<NUM> can be extracted by the external circuitry. As will be explained below, R<NUM> + R<NUM> may be interpreted as the state of the memory cell. The read voltages are chosen appropriately to obtain the bias conditions described above. For example, <MAT> is chosen sufficiently larger than the turn on voltage of the PNP BJT 108b or the threshold voltage of the pJFET 108b to provide the required overdrive, whereas <MAT> <MAT> and <MAT> are not large enough to overdrive the PNP BJTs or pJFETs in the rest of memory cells. Similarly, <MAT> is chosen sufficiently larger than the turn on voltage of the NPN BJT 108b or the threshold voltage of the nJFET 108b to provide the required overdrive, whereas <MAT> and V<NUM> - <MAT> are not large enough to overdrive the NPN BJTs or nJFETs in the rest of memory cells.

In an embodiment, the first read voltage of the first and second pair of voltages is a positive voltage V+ and the second read voltage of the first and second pair of voltages is a negative voltage V- having the same amplitude as the first read voltage. In another embodiment, the voltages are as follows: <MAT> <MAT> <MAT>.

It should be appreciated that read voltages are typically smaller than the write and erase voltages as known from a memory element operation.

As described above, during the reading of the memory cell <NUM>, read voltages are applied with the use of the external circuitry such that the current flows through both the first memory element 110a and the second memory element 110b, and the read current sensed by the read circuitry is a measure of the combined states of the first and second memory elements 110a, 110b. As a result, the memory cell <NUM> can have a larger number of states when compared to a single memory element <NUM>, as will be further explained below.

In addition, as described above, during the reading of the memory cell <NUM>, both transistors 108a, 108b are turned on such that the transistors 108a, 108b form a complementary pass transistor pair, also known as a transmission gate. As known, this is advantageous since the transmission gate has a lower voltage drop and a higher dynamic range than a single pass transistor. Therefore, the read current measured by the external circuitry is substantially proportional to R<NUM> + R<NUM>, the sum of the resistance values of memory elements 110a and 110b, which may be interpreted as the state of the memory cell. In an embodiment, the first and second memory elements 110a, 110b and the transistors 108a, 108b may be configured as vertically stacked structures. For example, memory element 110a may be stacked on top of transistors 108a and 108b, which are in turn stacked in top of memory element 110b. In addition, transistors 108a and 108b may be vertical transistors with stacked transistor regions. These stacked structures minimize the footprint of the memory cell <NUM> and achieve a high density of memory states per area.

Embodiments of the present invention provide the memory array <NUM> that includes a plurality of memory cells <NUM>. Each of the memory cells <NUM> includes two memory elements and two transistors. The memory cell <NUM> may be programed to a number of states larger than that of each of the memory elements. In some embodiments, a larger number of memory cell states may be possible if the first and second memory elements 110a, 110b, within the memory cell <NUM>, have different characteristics. For example, if the first and second memory elements 110a, 110b are identical, and have a first state RH (denoting a high resistance) and a second state RL(denoting a low resistance) , the memory cell <NUM> may have three states, 2RH, 2RL, and RH+RL. Similarly, if the first memory element 110a and the second memory element 110b have three states, RH, RL, and RM (denoting a medium resistance), there are six possible states 2RH, 2RL, 2RM, RH+RL, RH+RM and RL+RM. More generally, if the two memory elements within the memory cell <NUM> are identical, and if the first memory element 110a and the second memory element 110b have N states, the memory cell <NUM> is programmable to <MAT> states. In this example, it is assumed that memory elements 110a and 110b are symmetric or otherwise biased with the same voltage polarities in the memory cell so that they have the same states as each other. As known, a memory element may be asymmetric where the polarities of the write and erase voltages affect the states of the memory element.

The memory cell <NUM> may have up to N<NUM> states for N bits when the first memory element 110a is different from the second memory element 110b. For example, by using different material compositions, thicknesses, and/or structure, the first memory element 110a may be different from the second memory element 110b. For example, if the first memory element 110a has two states RH1 and RL1, and the second memory element 110b has two states RH2 and RL2, the memory cell <NUM> may have four possible states: RH1+RH2, RH1+RL2, RL1+RH2 and RL1+RL2. Similarly, if the memory elements 110a and 110b are identical, but asymmetric and biased with opposite voltage polarities with respect to each other (e.g. if the bottom terminal of memory element 110a is connected to BL 102b and its top terminal connected to transistors 108a and 108b), the first memory element 110a may have two states RH1 and RL1, and the second memory element 110b may have two states RH2 and RL2, and the memory cell <NUM> may have four possible states: RH1+RH2, RH1+RL2, RL1+RH2 and RL1+RL2. More generally, with N states instead of two, the memory cell <NUM> may have up to N<NUM> states in this manner.

Embodiments of the present invention described herein with reference to <FIG> provide a new circuit structure. The new circuit structure is the cross-point memory array <NUM> that includes a plurality of memory cells <NUM>. The memory cells <NUM> may also be referred to as enhanced state dual memory cells. The memory cells <NUM> are 2T2R memory cells. As described herein above, each of the memory cells <NUM> includes two transistors 108a, 108b and two memory elements 110a, 110b. This combination of transistors and memory elements increases the effective number of states per cell when compared to a conventional memory array.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claim 1:
A circuit (<NUM>) comprising:
a memory array comprising:
a plurality of bit lines (<NUM>);
a plurality of word lines (<NUM>);
a plurality of select lines (<NUM>), the plurality of bit lines and the plurality of select lines intersect the plurality of word lines; and
a plurality of memory cells (<NUM>) each comprising:
a first transistor (108a),
a second transistor (108b),
a first memory element (110a), and
a second memory element (110b), the first and second memory elements are connected to the plurality of word lines by way of the first and second transistors, the first and second memory elements are connected to the plurality of bit lines and the plurality of select lines, and characterised by, wherein:
the first transistor and the second transistor are a complementary pair of bipolar junction pass transistors, the complementary pair of bipolar junction pass transistors comprising an NPN bipolar junction pass transistor and a PNP bipolar junction pass transistor, or
the first transistor and the second transistor are a complementary pair of junction field-effect transistors, the complementary pair of junction field-effect transistors comprising an n-channel junction field-effect transistor and a p-channel junction field effect-transistor; and
wherein the first memory element is connected between one of the plurality of bit lines and a first shared collector emitter or source drain terminal of the complementary pair, and the second memory element is connected between one of the plurality of select lines and a second shared collector emitter or source drain terminal of the complementary pair.