Patent Description:
With the rapid development of wireless communication, automotive electronics and other consumer electronics, electronic devices have a trend of development towards multi-functionality. Therefore, in manufacturing these electronic devices, chips with different functions are usually packaged separately and then integrated, and the integrated components are disposed inside the electronic devices.

Package is an important step in the manufacturing process of the electronic devices. However, the chips in the prior art are prone to the problems of large size and relatively low rate of signal transmission after being packaged.

The <CIT> describes a chip stacking and packaging structure that improves the heat dissipation.

The <CIT> describes a chip packaging structure, manufacturing method and electronic equipment that improves the number of lead-out I/O pins of a packaged packaging module, and improve the integration level of the packaging module and the application range of the packaging module.

Embodiments of the present disclosure provide a chip package structure, a manufacturing method thereof, and an electronic device, for the purposes of reducing the area of the chip package structure and improving the rate of signal transmission.

To fulfill the above objects, the embodiments of the present disclosure have the following technical solutions.

In an aspect, a chip package structure according to claim <NUM> is provided.

In the chip package structure according to the foregoing embodiment of the present disclosure, the second chip is placed above the first chip, such that the package substrate, the first chip, the conductive pillar and the second chip form a stacked structure, which improves the compactness of the chip package structure and helps to reduce the area of the chip package structure. Moreover, the conductive pillar is provided to realize the electrical connection between the second chip and the package substrate, and the conductive pillar is disposed under the first chip <NUM> or the second chip such that the orthographic projection of the conductive pillar on the package substrate is located within the range of the orthographic projection of the first chip <NUM> or the second chip on the package substrate. In this way, the space around the first chip <NUM> or the second chip may not be occupied, which helps to further miniaturize the chip package structure and to further reduce the area of the chip package structure.

In some embodiments, an orthographic projection of the conductive pillar on the package substrate is also located within a range of an orthographic projection of the first chip on the package substrate.

In some embodiments, the chip package structure further includes a package layer, and the package layer is located between the package substrate and the second chip, covers the first chip and surrounds sides of the conductive pillar.

In some embodiments, an orthographic projection of the second chip on the package substrate is located within a range of an orthographic projection of the package layer on the package substrate.

In some embodiments, the chip package structure further includes a first filling portion, and at least part of the first filling portion is located between the package layer and the second chip and the first filling portion surrounds each pin of the second chip.

In some embodiments, the chip package structure further includes an electromagnetic shielding layer, and the electromagnetic shielding layer at least covers the second chip as well as sides of the package layer.

In some embodiments, the package substrate further includes at least one ground wire, and the electromagnetic shielding layer also covers sides of the package substrate and is electrically connected to the ground wire.

In some embodiments, the second chip comprises a plurality of sub-chips sequentially stacked in a direction perpendicular to and away from the package substrate.

In some embodiments, two adjacent sub-chips are electrically connected to each other.

In some embodiments, one of the plurality of sub-chips close to the package substrate is electrically connected to the conductive pillar, and others of the plurality of sub-chips are electrically connected to the package substrate by a wire.

In some embodiments, a number of the conductive pillars is greater than one, and the plurality of conductive pillars are at least located on two opposite sides of the first chip.

In some embodiments, the chip package structure further includes a second filling portion, and at least part of the second filling portion is located between the package substrate and the first chip and the second filling portion surrounds each pin of the first chip.

In some embodiments, the package substrate has a second surface opposite to the first surface, and the chip package structure further comprises a solder ball located on the second surface of the package surface and electrically connected to the package substrate.

In another aspect, another chip package structure is provided. The chip package structure includes: a package substrate having a first surface; a first chip disposed on the first surface of the package substrate and electrically connected to the package substrate; and a second chipset located on a side of the first chip away from the package substrate, electrically connected to the package substrate, and comprising a plurality of second chips sequentially stacked in a direction perpendicular to and away from the package substrate.

In some embodiments, two adjacent second chips are electrically connected to each other.

In some embodiments, each of the plurality of second chips is electrically connected to the package substrate by a wire.

In some embodiments, the chip package structure further includes a package layer, and the package layer is located between the package substrate and the second chipset and covers the first chip.

In some embodiments, an orthographic projection of the second chipset on the package substrate is located within a range of an orthographic projection of the package layer on the package substrate.

In some embodiments, the chip package structure further includes a first filling portion, and at least part of the first filling portion is located between the package layer and the second chipset and the first filling portion surrounds each pin of one second chip close to the package substrate.

In some embodiments, the chip package structure further includes an electromagnetic shielding layer, the electromagnetic shielding layer at least covers the second chipset as well as sides of the package layer.

In some embodiments, the package substrate includes at least one ground wire, and the electromagnetic shielding layer also covers sides of the package substrate and is electrically connected to the ground wire.

In yet another aspect, an electronic device according to claim <NUM> is provided. The electronic device includes the chip package structure as described in some embodiments above.

In still another aspect, a manufacturing method of a chip package structure according to claim <NUM> is provided.

In some embodiments, before the disposing the second chip on the side of the conductive pillar and the first chip away from the package substrate, the manufacturing method further comprises: forming a package film on the first chip and the conductive pillar, the package filmcovering the first chip and the conductive pillar; and thinning the package film to expose the conductive pillar and to obtain a package layer, the package layer covering the first chip.

In some embodiments, the forming the conductive pillar on the first surface of the package substrate comprises: forming a package layer on the first chip, the package layer covering the first chip; forming a via in the package layer, the via exposing a second pad; and filling the via with a conductive material to form the conductive pillar.

In some embodiments, the manufacturing method further includes: filling a first insulating material between the package layer and the second chip to form a first filling portion, the first filling portion surrounding each pin of the second chip.

In some embodiments, the manufacturing method further includes: forming anelectromagnetic shielding layer, the electromagnetic shielding layer at least covering the second chip as well as sides of the package layer.

In some embodiments, the second chip comprises a plurality of sub-chips; and the disposing the second chip on the side of the conductive pillar and the first chip away from the package substrate comprises: sequentially stacking the plurality of sub-chips in a thickness direction of the sub-chips to form the second chip; and soldering the second chip with an end of the conductive pillar away from the package substrate, such that the second chip is electrically connected to the conductive pillar.

In some embodiments, after disposing the first chip and before disposing the second chip, the manufacturing method further includes: filling a second insulating material between the package substrate and the first chip to form a second filling portion, the second filling portion surrounding each pin of the first chip.

In some embodiments, a third pad is disposed on a second surface of the package substrate, and the first surface and the second surface are opposite to each other; and before or after forming the package layer, the manufacturing method further includes: forming a solder ball on the second surface of the package substrate, the solder ball being electrically connected to the third pad.

It can be understood that for the beneficial effects of the electronic device and the manufacturing method of the chip package structure provided by the foregoing embodiments of the present disclosure, a reference may be made to the beneficial effects of the chip package structure described above, which will not be repeated herein.

For clearer descriptions of the technical solutions in the present disclosure, a brief introduction may be given hereinafter to the accompany drawings that may be used in some embodiments of the present disclosure. Apparently, the drawings in the following descriptions are merely for illustrating some embodiments of the present disclosure, and other drawings may be obtained by those of ordinary skill in the art according to these drawings. In addition, the drawings in the following descriptions may be considered as schematic diagrams but not a limitation to the product actual size, the method actual flow, etc. related to the embodiments of the present disclosure.

The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings. Apparently, the described embodiments are only a part of embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present disclosure shall fall within the scope of protection of the present disclosure.

In the descriptions of the present disclosure, it should be understood that directional orpositional relationships indicated by the terms such as "center", "upper", "lower", "front", "back ", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" are directional or positional relationships as shown in the drawings, only for the purposes of the ease in describing the present disclosure and simplification of its descriptions, but not indicating or implying that the specified apparatus or element has to be located in a specific direction, and structured and operated in a specific direction, and therefore, should not be understood as limitations to the present disclosure.

Unless the context otherwise requires, throughout the description and claims, the term "comprise" is interpreted as an open-ended inclusion, i.e., "comprising, but not limited to". In the descriptions, the terms "an embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that a specific feature, structure, material or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific feature, structure, material or characteristic described may be included in any one or more embodiments or examples in any appropriate manner.

Hereinafter, the terms "first" and "second" are only intended for description and shall not be construed to indicate or imply relative importance, or imply the number of the indicated technical features. Therefore, the features defined by "first" and "second" can indicate or imply that one or more features are included. In the descriptions of the embodiments of the present disclosure, unless otherwise stated, "a plurality of" means two or more.

In describing some embodiments, the expressions of "connect" and its extensions may be used. For example, some embodiments may be described by using the term "connect" to indicate that two or more components are in direct physical or electrical contact. For another example, some embodiments may be described by using the term "couple" to indicate that two or more components are in direct physical contact or electrical contact. However, the term "couple" may also mean that two or more components are not in direct contact but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

"At least one of A, B and C" and "at least one of A, B or C" have the same meaning of including the following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes the following three combinations: only A, only B, and a combination of A and B.

In addition, the use of "based on" means openness and inclusiveness, because the process, step, calculation or other actions "based on" one or more conditions or values can be based on additional conditions or beyond the values in practice.

In the present disclosure, the meaning of "on," "above," and "over" should be interpreted in the broadest manner such that "on" not only means "directly on" something but also includes the meaning of "on" something with an intermediate feature or a layer therebetween, and that "above" or "over" not only means the meaning of "above" or " over" something but can also include the meaning it is "above" or "over" something with no intermediate feature or layer therebetween (i.e., directly on something).

The disclosure describes exemplary embodiments with reference to sectional views and/or planar views as idealized illustrative drawings. In the drawings, the thicknesses of layers and areas are enlarged for clarity. It is thus conceivable of the change in shape with respect to the drawings due to, for example, manufacturing techniques and/or tolerances. Therefore, the exemplary embodiments should not be interpreted to be limited to the shape of the area shown herein, but to include the shape deviation due to, for example, manufacturing. For example, an etched area shown as a rectangle will generally have a curved feature. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are neither intended to show the actual shape of the area of the device, nor intended to limit the scope of the exemplary embodiments.

In an implementation , as shown in <FIG>, a first chip <NUM>' and a second chip <NUM>' in a chip package structure <NUM>' are typically disposed side by side on a package substrate <NUM>' in a tiling manner.

A plurality of gold fingers are disposed on a side of the package substrate <NUM>' close to the first chip <NUM>' and the second chip <NUM>'. The first chip <NUM>' and the second chip <NUM>' are respectively connected to the gold fingers by gold wires <NUM>' by using the WB (wire bonding) process, so that the first chip <NUM>' and the second chip <NUM>' may be electrically connected by the respectively connected gold wires <NUM>' and the package substrate <NUM>', thereby realizing communication between the first chip <NUM>' and the second chip <NUM>'.

However, the first chip <NUM>' and the second chip <NUM>' are disposed side by side, which makes the area of the chip package structure <NUM>' larger. Moreover, due to the wire arcs of the gold wires <NUM>' and the existence of the gold fingers, it is necessary to reserve certain areas around the first chip <NUM>' and the second chip <NUM>', which further increases the area of the chip package structure <NUM>'. Generally, the area of the chip package structure <NUM>' obtained after the first chip <NUM>' and the second chip <NUM>' are packaged is increased by at least <NUM>% compared with the sum of the areas of the first chip <NUM>' and the second chip <NUM>'. In addition, due to large lengths and high resistance of the gold wires <NUM>', the rate of signal transmission may be low in the process of transmitting a signal between the first chip <NUM>' and the second chip <NUM>' through the different gold wires <NUM>'.

Accordingly, in some embodiments of the present disclosure, a chip package structure <NUM> is provided. There may be various types of chip package structures <NUM>, such as an embedded multi-media card (EMMC), a universal flash storage (UFS) and a multi-chip package (MCP). As shown in <FIG>, and <FIG>, the chip package structure <NUM> includes a first chip <NUM>, a conductive pillar <NUM>, and a second chip <NUM>.

The first chip <NUM> and the second chip <NUM> may have different functions. For example, the first chip <NUM> may be a controller, and the second chip <NUM> may be a memory chip. The memory chip has a memory structure for providing a storage function. There may be various types of memory chips. For example, the memory chip includes but are not limited to a Nand chip, a resistive memory chip, and a dynamic random-access memory. Of course, the first chip <NUM> may also be a memory chip, and the second chip <NUM> may also be a controller, which is not limited in the embodiments of the present disclosure.

In some examples, the chip package structure <NUM> further includes a package substrate <NUM>. The package substrate <NUM> is rigid and thus may provide support for the first chip <NUM>, the conductive pillar <NUM>, and the second chip <NUM>. A reference may be made to the following descriptions for the conductive pillar <NUM>, which is not explained herein.

Exemplarily, as shown in <FIG>, the package substrate <NUM> includes a plurality of dielectric layers <NUM> and a plurality of metal wiring layers <NUM>, which are alternately disposed. One metal wiring layer <NUM> is disposed between two adjacent dielectric layers <NUM>, and one dielectric layer <NUM> is disposed between two adjacent metal wiring layers <NUM>. Each metal wiring layer <NUM> includes a metal line, and the metal lines in two adjacent metal wiring layers <NUM> may run through the dielectric layer <NUM> between the two metal wiring layers <NUM> and be connected as required.

In some examples, the dielectric layer <NUM> in the package substrate <NUM> is formed by a spin coating process, and the metal wiring layer <NUM> in the package substrate <NUM> is formed by a physical vapor deposition (PVD) process in combination with an electroplating process. Therefore, compared with a package substrate formed by a press-fit process, the package substrate <NUM> constituted by the dielectric layer <NUM> and the metal wiring layer <NUM>, provided by the embodiments of the present disclosure, has a smaller thickness, a smaller spacing between the adjacent metal wiring layers <NUM>, and thus a higher integration rate of the metal lines in the metal wiring layer <NUM>.

Optionally, the number of metal wiring layers <NUM> may be <NUM> or <NUM>. <FIG> illustrates <NUM> metal wiring layers <NUM>.

The dielectric layer <NUM> may be made from, for example, an insulating resin material, which for example, includes but is not limited to polybenzoxazole (PBO), polyimide (PI), and the like.

The metal wiring layer <NUM> may be made from, for example, a conductive material, which for example, includes but is not limited to gold, silver, copper, aluminum, and the like.

Exemplarily, as shown in <FIG>, the package substrate <NUM> may further include a solder resist layer <NUM>. For example, the number of solder resist layers <NUM> may be two. The plurality of dielectric layers <NUM> and the plurality of metal wiring layers <NUM> form a stacked structure, and the two solder resist layers <NUM> are located on the front side and the back side of the stacked structure respectively.

The solder resist layer <NUM> may not only play the role of insulation, but also protect the package substrate <NUM> and prevents the metal lines in the package substrate <NUM> from being oxidized.

Optionally, the solder resist layer <NUM> may be made from an organic material, for example, a solder resist ink, as long as it can play the role of insulation, which is not limited in the embodiments of the present disclosure.

In some examples, as shown in <FIG>, the package substrate <NUM> has a first surface A and a second surface B that are opposite to each other. The first surface is an upper surface of the package substrate shown in <FIG> and the second surface is a lower surface of the package substrate shown in <FIG>.

As shown in <FIG>, the first surface A of the package substrate <NUM> is provided with a first pad <NUM> and a second pad <NUM> disposed at an interval. There may be a plurality of first pads <NUM> and a plurality of second pads <NUM>. <FIG> illustrates nine first pads <NUM> and two second pads <NUM>.

Exemplarily, both of the first pads <NUM> and the second pads <NUM> are located in the uppermost metal wiring layer <NUM> of the package substrate <NUM>. The solder resist layer <NUM> is also provided with a plurality of vias, each of which exposes one first pad <NUM> or one second pad <NUM>.

In some examples, as shown in <FIG>, the first chip <NUM> is located on the first surface A of the package substrate <NUM> and electrically connected to the package substrate <NUM>.

Optionally, the first chip <NUM> is electrically connected to the first pad <NUM> on the package substrate <NUM>.

Exemplarily, in the top views shown in <FIG>, the first chip <NUM> may be disposed in the middle of the package substrate <NUM>, and accordingly, each first pad <NUM> may be located in the middle of the package substrate <NUM>. The first chip <NUM> and the first pad <NUM> may be electrically connected by a soldering process. For example, the soldering process may be a hot pressure soldering process, an ultrasonic pressure soldering process or a thermosonic soldering process.

Of course, the first chip <NUM> and the first pad <NUM> may also be electrically connected by other means, which is not limited in the embodiments of the present disclosure.

In some examples, as shown in <FIG>, the chip package structure <NUM> further includes a conductive pillar <NUM>. The conductive pillar <NUM> is located on the first surface A of the package substrate <NUM> and electrically connected to the package substrate <NUM>.

Optionally, the conductive pillar <NUM> is electrically connected to the second pad <NUM> on the package substrate <NUM>.

Exemplarily, the conductive pillar <NUM> may be made of at least one of metal copper, metal aluminum, metal silver, or tin.

Exemplarily, the conductive pillar <NUM> may be columnar, such as cylindrical and prismatic. Of course, the conductive pillar <NUM> may also be in other irregular shapes, which is not limited in the embodiments of the present disclosure.

In some examples, as shown in <FIG>, the second chip <NUM> is located on the side of the first chip <NUM> and the conductive pillar <NUM> away from the package substrate <NUM>. The second chip <NUM> is electrically connected to the conductive pillar <NUM> and is not in direct electrical connection with the first chip <NUM>.

The electrical connection between the second chip <NUM> and the conductive pillar <NUM> may be realized in various ways. For example, in an embodiment of the present disclosure, the second chip <NUM> may be electrically connected to the conductive pillar <NUM> by means of flip-chip bonding.

It can be understood that flip-chip bonding refers to a process of forming bumps on a connect pad of a chip and directly connecting the bumps to a PCB substrate or a metal substrate.

Exemplarily, as shown in <FIG>, the second chip <NUM> includes a body <NUM> and a pin <NUM> located below the body <NUM>. At this time, the chip package structure <NUM> further includes a first pad <NUM> located between the pin <NUM> and the conductive pillar <NUM>. The second chip <NUM> is electrically connected to the conductive pillar <NUM> by the first pad <NUM>. For example, the pin <NUM> refers to the connect pad, and the first pad <NUM> refers to the bump.

The pin <NUM> may be made from at least one of copper, titanium, nickel, tungsten and silver for example. The first pad <NUM> may be made from tin for example. The second chip <NUM> may be electrically connected to the conductive pillar <NUM> by a soldering process. Exemplarily, the soldering process may be a hot pressure soldering method, an ultrasonic pressure soldering method, a thermosonic soldering process, or the like.

Exemplarily, an orthographic projection of the conductive pillar <NUM> on the package substrate <NUM> is located within an orthographic projection of the first chip <NUM> or the second chip <NUM> on the package substrate <NUM>. For example, it can be seen from <FIG> that the second chip <NUM> may completely cover the conductive pillar <NUM>, and the conductive pillar <NUM> is located within the boundary of the orthographic projection of the second chip <NUM> on the package substrate <NUM>.

In the case that the orthographic projection of the conductive pillar <NUM> on the package substrate <NUM> is located within the orthographic projection of the second chip <NUM> on the package substrate <NUM>, the conductive pillar <NUM> may provide support for the second chip <NUM>, so as to improve the stability of the second chip <NUM> and further improve the structure stability of the chip package structure <NUM>.

Since the conductive pillar <NUM> is located below the second chip <NUM> and electrically connected to a surface on a side of the second chip <NUM> close to the package substrate <NUM>, the conductive pillar <NUM> may extend in a direction perpendicular to the first surface A of the package substrate <NUM> to be in a vertical state. The length of a path of signal transmission between the second chip <NUM> and the package substrate <NUM> substantially equals the height of the conductive pillar <NUM>, or, substantially equals the distance between the first surface A and the surface on the side of the second chip <NUM> close to the package substrate <NUM>. In this way, the path of signal transmission between the first chip <NUM> and the second chip <NUM> can be greatly shortened and the rate of signal transmission can be greatly improved.

In addition, the cross-sectional area of the conductive pillar <NUM> is larger than that of the gold wire, and correspondingly, the resistance of the conductive pillar <NUM> is lower than that of the gold wire, which helps to further improve the rate of signal transmission.

In the case that the orthographic projection of the conductive pillar <NUM> on the package substrate <NUM> is located within the orthographic projection of the first chip <NUM> on the package substrate <NUM>, the orthographic projection of the conductive pillar <NUM> on the package substrate <NUM> may also be located within the orthographic projection of the first chip <NUM> on the package substrate <NUM>. At this time, the area of the orthographic projection of the first chip <NUM> on the package substrate <NUM> may be greater than the area of the orthographic projection of the second chip <NUM> on the package substrate <NUM>, and the conductive pillar <NUM> may be electrically connected to the second chip <NUM> after running through the first chip <NUM>.

Therefore, in the chip package structure <NUM> according to some embodiments of the present disclosure, the second chip <NUM> is placed above the first chip <NUM>, such that the package substrate <NUM>, the first chip <NUM>, the conductive pillar <NUM> and the second chip <NUM> form a stacked structure, which improves the compactness of the chip package structure <NUM> and helps to reduce the area of the chip package structure <NUM>. Moreover, by providing the conductive pillar <NUM> to realize the electrical connection between the second chip <NUM> and the package substrate <NUM>, and by disposing the conductive pillar <NUM> below the first chip <NUM> or the second chip <NUM>, the orthographic projection of the conductive pillar <NUM> on the package substrate <NUM> is located within the range of the orthographic projection of the first chip <NUM> or the second chip <NUM> on the package substrate <NUM>. In this way, the space around the first chip <NUM> or the second chip <NUM> may not be occupied, which helps to further miniaturize the chip package structure <NUM> and to further reduce the area of the chip package structure <NUM>.

In addition, the effective length of the conductive pillar <NUM> substantially equals the distance between the first surface A and the surface on the side of the second chip <NUM> close to the package substrate <NUM>. Compared with the electrical connection between the second chip <NUM> and the package substrate <NUM> realized by the gold wires, the path of signal transmission between the first chip <NUM> and the second chip <NUM> in the embodiment of the present application is shortened, which helps to improve the rate of signal transmission. Moreover, compared with the gold wire, the conductive pillar <NUM> is larger in size and lower in resistance, which helps to further improve the rate of signal transmission between the first chip <NUM> and the second chip <NUM>. Accordingly, the chip package structure <NUM> can be improved in response speed and reduced in power consumption, and electricity can be saved.

It should be noted that in the case the area of the second chip is larger than that of the first chip, in the chip package structure, the size of the package plane is approximate to the size of the area of the second chip, for example.

As shown in <FIG>, a surface on a side of the second chip <NUM> close to the package substrate <NUM> is higher than a surface on a side of the first chip <NUM> away from the package substrate <NUM>, with respect to the first surface A of the package substrate <NUM>. That is, there is a certain distance between the surface on the side of the second chip <NUM> close to the package substrate <NUM> and the surface on the side of the first chip <NUM> away from the package substrate <NUM>. That is, the first chip <NUM> and the second chip <NUM> are disposed at intervals in a direction perpendicular to the first surface A.

Exemplarily, the distance between the surface on the side of the second chip <NUM> close to the package substrate <NUM> and the surface on the side of the first chip <NUM> away from the package substrate <NUM> is greater than or equal to <NUM>. For example, the distance may be <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. The "distance" herein refers to a distance in a direction perpendicular to the first surface.

With the above arrangement, signal interference between the second chip <NUM> and the first chip <NUM> can be avoided, which helps to improve the reliability and reliability of the chip package structure <NUM>.

Optionally, relative to the first surface A of the package substrate <NUM>, ends of the conductive pillars <NUM> away from the package substrate <NUM> are higher than the surface on the side of the first chip <NUM> away from the package substrate <NUM>.

As shown in <FIG>, the distance between the surface on the side of the second chip <NUM> close to the package substrate <NUM> and the first surface A of the package substrate <NUM> is h1, the distance between the surface on the side of the first chip <NUM> away from the package substrate <NUM> and the first surface A of the package substrate <NUM> is h2, and h1 and h2 meet:
<MAT>.

Exemplarily, a value of <MAT> may be, for example, <MAT>, etc..

In some examples, the distance between the surface on the side of the first chip <NUM> away from the package substrate <NUM> and the first surface A of the package substrate <NUM> ranges from <NUM> to <NUM>. At this point, the distance between the surface on the side of the second chip <NUM> close to the package substrate <NUM> and the first surface A of the package substrate <NUM> may be <NUM> to <NUM>. For example, when the distance between the surface on the side of the first chip <NUM> away from the package substrate <NUM> and the first surface A of the package substrate <NUM> is <NUM>, the distance between the surface on the side of the second chip <NUM> close to the package substrate <NUM> and the first surface A of the package substrate <NUM> may be <NUM>. For another example, when the distance between the surface on the side of the first chip <NUM> away from the package substrate <NUM> and the first surface A of the package substrate <NUM> is <NUM>, the distance between the surface on the side of the second chip <NUM> close to the package substrate <NUM> and the first surface A of the package substrate <NUM> may be <NUM>.

With the above arrangement, a certain distance can be ensured between the first chip <NUM> and the second chip <NUM>, thereby avoiding signal interference between the first chip <NUM> and the second chip <NUM>. On this basis, the distance between the first chip <NUM> and the second chip <NUM> can also be prevented from being too large, which ensures a thin and light structure of the chip package structure <NUM>.

In some embodiments, as shown in <FIG>, a number of conductive pillars <NUM> is greater than one. The plurality of conductive pillars <NUM> are at least located on two opposite sides of the first chip <NUM>. Exemplarily, the plurality of conductive pillars <NUM> are located on two opposite sides of the first chip <NUM> (as shown in <FIG>); or the plurality of conductive pillars <NUM> are located on three or four sides of the first chip <NUM> (as shown in <FIG>).

Exemplarily, the number of the conductive pillars <NUM> located on different sides of the first chip <NUM> may be the same or different. The plurality of conductive pillars <NUM> located on the same side of the first chip <NUM> may be regularly arranged in at least one column; of course, the plurality of conductive pillars <NUM> located on the same side of the first chip <NUM> may also be disposed in a staggered way, which is not limited by the embodiment of the present disclosure.

In the present embodiment, the plurality of conductive pillars <NUM> are at least disposed on two opposite sides of the first chip <NUM>, which can not only ensure electrical connection between the second chip <NUM> and the package substrate <NUM>, but also provide a relatively balanced supporting force for the second chip <NUM> and ensure structure stability of the second chip <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the chip package structure <NUM> further includes a package layer <NUM>. The package layer <NUM> is located between the package substrate <NUM> and the second chip <NUM>, covers the first chip <NUM>, and surrounds sides of the conductive pillars <NUM>.

Exemplarily, the package layer <NUM> is a whole layer structure, a surface on a side of the package layer <NUM> away from the package substrate <NUM> is, for example, a flat surface, this surface is, for example, flush with the surfaces on the side of the conductive pillars away from the package substrate <NUM>, and the package layer <NUM> exposes the surfaces on the side of the conductive pillars <NUM> away from the package substrate <NUM>.

Exemplarily, the area of an orthographic projection of the package layer <NUM> on the package substrate <NUM> is basically coincident with the area of the first surface A of the package substrate <NUM>; and a boundary of the orthographic projection of the package layer <NUM> on the package substrate <NUM> is basically coincident with a boundary of the first surface A of the package substrate <NUM>.

Exemplarily, a material of the package layer <NUM> may be a molding compand material. At this point, the package layer <NUM> may be formed by a molding process. The material of the package layer <NUM> may also be other materials, which is not limited by the embodiment of the present disclosure.

With the above arrangement, not only may the first chip <NUM> be packaged by the package layer <NUM>, but also the package layer <NUM> is in contact with the sides of the conductive pillars <NUM> to provide physical protection for the first chip <NUM> and the conductive pillars <NUM>, and to fix the positions of the first chip <NUM> and the conductive pillars <NUM> on the package substrate, which ensures structure integrity and stability of the chip package structure <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the orthographic projection of the second chip <NUM> on the package substrate <NUM> is located within the range of the orthographic projection of the package layer <NUM> on the package substrate <NUM>.

Exemplarily, an area of the orthographic projection of the second chip <NUM> on the package substrate <NUM> is less than an area of the orthographic projection of the package layer <NUM> on the package substrate <NUM>. A boundary of the orthographic projection of the package layer <NUM> on the package substrate <NUM> surrounds a boundary of the orthographic projection of the second chip <NUM> on the package substrate <NUM>, and there is a certain distance between the two boundaries.

With the above arrangement, the package layer <NUM> can provide certain support for the second chip <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the chip package structure <NUM>
further includes a first filling portion <NUM>. At least part of the first filling portion <NUM> is located between the package layer <NUM> and the second chip <NUM>, and the first filling portion <NUM> surrounds each pin of the second chip <NUM>.

Exemplarily, the first filling portion <NUM> is located between the package layer <NUM> and the second chip <NUM>, and the second chip <NUM> covers the first filling portion <NUM>. Alternatively, the first filling portion <NUM> is located not only between the package layer <NUM> and the second chip <NUM>, but also on both sides of the second chip <NUM>, and the orthographic projection of the second chip <NUM> on the package substrate <NUM> is located within the range of an orthographic projection of the first filling portion <NUM> on the package substrate <NUM>.

The first filling portion <NUM> is filled between any two adjacent pins of the second chip <NUM>, so as to avoid short circuit between the two adjacent pins.

Exemplarily, a material of the first filling portion <NUM> may be an epoxy resin material or the
like. When the epoxy resin material or the like is filled between the package layer <NUM> and the second chip <NUM> to form the first filling portion <NUM>, a hole may be formed, and an area of the hole is, for example, less than or equal to <NUM>%.

In the present embodiment, by disposing the first filling portion <NUM> between the package layer <NUM> and the second chip <NUM>, not only can the support be provided for the second chip <NUM>, but also the bonding force between the second chip <NUM> and the package layer <NUM> is enhanced, and the structure stability of the second chip <NUM> is ensured, thereby improving the reliability of the chip package structure <NUM>. The short circuit between any two adjacent pins of the second chip <NUM> can also be avoided, which ensures a yield of the chip package structure <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the chip package structure <NUM> further includes an electromagnetic shielding layer <NUM>. The electromagnetic shielding layer <NUM> at least covers the second chip <NUM> as well as the sides of the package layer <NUM>.

Exemplarily, the electromagnetic shielding layer <NUM> covers the second chip <NUM> as well as the sides of the package layer <NUM>. Alternatively, the electromagnetic shielding layer <NUM> covers not only the second chip <NUM> as well as the sides of the package layer <NUM>, but also other components, for example, the electromagnetic shielding layer <NUM> also covers the sides of the first filling portion <NUM>, etc., which is not limited by the embodiment of the present disclosure.

Exemplarily, the electromagnetic shielding layer <NUM> is made of a ferromagnetic material (such as steel) with a very high magnetic permeability, and the electromagnetic shielding layer <NUM> may electromagnetically shield a covered region thereof.

By disposing the electromagnetic shielding layer <NUM>, the first chip <NUM> and the second chip <NUM> can be effectively prevented from being subjected to electromagnetic interference, thereby improving an anti-electromagnetic interference capability of the chip package structure <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the package substrate <NUM> further includes at least one ground wire <NUM>. The ground wire <NUM> is located on the metal wiring layer <NUM>.

In some examples, as shown in <FIG> and <FIG>, the electromagnetic shielding layer <NUM> also covers the sides of the package substrate <NUM>, and is electrically connected to the ground wire <NUM>.

In the present embodiment, the electromagnetic shielding layer <NUM> covers the second chip <NUM> as well as the sides of the package layer <NUM> and the sides of the package substrate <NUM> to electromagnetically shield the chip package structure <NUM> and effectively prevent the electromagnetic interference. Furthermore, the electromagnetic shielding layer <NUM> is further electrically connected to the ground wire <NUM>, and can lead electromagnetic radiation out through grounding, which realizes double anti-electromagnetic interference and further ensures efficient operation of the chip package structure <NUM>. At this point, the anti-electromagnetic interference capability of the chip package structure <NUM> is realized by the electromagnetic shielding layer <NUM>, which is low in process cost, simple and convenient to implement and suitable for mass production.

In some embodiments, as shown in <FIG>, the second chip <NUM> includes a plurality of sub-chips <NUM>. For example, the plurality of sub-chips <NUM> are sequentially stacked in a direction perpendicular to the package substrate <NUM> and away from the package substrate <NUM>. For example, types of the plurality of sub-chips are the same, and optionally, the sub-chips are all memory chips.

In some examples, an isolation structure <NUM> is disposed between two adjacent sub-chips <NUM>. A material of the isolation structure <NUM> may be an adhesive material. Two adjacent sub-chips <NUM> are connected by the adhesive material.

In some other examples, one sub-chip <NUM> close to the package substrate <NUM> in the plurality of sub-chips <NUM> is electrically connected to the conductive pillar <NUM>, thereby realizing electrical connection with the package substrate <NUM> through the conductive pillar. Other sub-chips <NUM> are electrically connected to the package substrate <NUM> through a wire by a wire bonding process.

Exemplarily, each sub-chip <NUM> is respectively electrically connected to the package substrate <NUM>, so that each sub-chip <NUM> respectively communicates with the first chip <NUM>. At this point, each sub-chip <NUM> can store different information under control of the first chip <NUM>, which ensures storage diversity of the chip package structure <NUM>.

In some other examples, as shown in <FIG>, two adjacent sub-chips <NUM> are electrically connected. For example, two adjacent sub-chips <NUM> may be connected to each other by a gold wire. For another example, the sub-chip <NUM> includes a sub-pin <NUM>, and the chip package structure <NUM> further includes a second pad <NUM> located between two adjacent sub-chips <NUM>. As shown in <FIG>, two adjacent sub-chips <NUM> are electrically connected through the pin and the second pad <NUM>.

Exemplarily, a material of the sub-pin <NUM> includes at least one of metal copper, titanium, nickel, tungsten and silver. A material of the second pad <NUM> may include tin. At this point, two adjacent sub-chips <NUM> may be electrically connected by a soldering process.

Exemplarily, the soldering process may be a hot-press soldering method, an ultrasonic pressure soldering method, a thermal ultrasonic soldering method or the like.

In the present embodiment, by stacking the plurality of sub-chips <NUM> to form the second chip <NUM>, an integration degree of the chip package structure <NUM> can be improved and product performances of the chip package structure <NUM> can be improved on the basis of ensuring a smaller package area.

It should be noted that the first chip <NUM> may also include a plurality of sub-chips. When the first chip <NUM> includes the plurality of sub-chips, the plurality of sub-chips may be sequentially stacked in a direction away from the package substrate <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the chip package structure <NUM> further includes a second filling portion <NUM>. At least part of the second filling portion <NUM> is located between the package substrate <NUM> and the first chip <NUM>, and the second filling portion <NUM> surrounds each pin of the first chip <NUM>.

Exemplarily, the second filling portion <NUM> is located between the package substrate <NUM> and the first chip <NUM>, and the first chip <NUM> covers the second filling portion <NUM>. Alternatively, the second filling portion <NUM> is located not only between the package substrate <NUM> and the first chip <NUM>, but also on both sides of the first chip <NUM>, and the orthographic projection of the first chip <NUM> on the package substrate <NUM> is located within the range of an orthographic projection of the second filling portion <NUM> on the package substrate <NUM>.

The second filling portion <NUM> is filled between any two adjacent pins of the first chip <NUM>, so as to avoid short circuit between the two adjacent pins.

Exemplarily, a material of the second filling portion <NUM> is an epoxy resin material or the like.

When the epoxy resin material or the like is filled between the package substrate <NUM> and the first chip <NUM> to form the second filling portion <NUM>, a hole may be formed, and an area of the hole is , for example, less than or equal to <NUM>%.

In the present embodiment, by disposing the second filling portion <NUM> between the package substrate <NUM> and the first chip <NUM>, not only can the support be provided for the first chip <NUM>, but also the bonding force between the first chip <NUM> and the package substrate <NUM> is enhanced, and structure stability of the first chip <NUM> is ensured, thereby improving the reliability of the chip package structure <NUM>. The short circuit between any two adjacent pins of the first chip <NUM> can also be avoided, which ensures the yield of the chip package structure <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the second surface B of the package substrate <NUM> is provided with third pads <NUM>. The third pads <NUM> are located on the metal wiring layers <NUM>. For example, a number of third pads <NUM> is greater than one.

Exemplarily, the solder resist layers <NUM> are provided with a plurality of vias, and each via exposes one third pad <NUM>.

In some examples, as shown in <FIG> and <FIG>, the chip package structure <NUM> further includes solder balls <NUM>. A number of solder balls <NUM> is greater than one, and the plurality of solder balls <NUM> are located on the second surface B of the package substrate <NUM> and electrically connected to the package substrate <NUM>.

Optionally, the solder balls <NUM> are electrically connected to the third pads <NUM> on the package substrate <NUM>. The plurality of solder balls <NUM> and the plurality of third pads <NUM> may be disposed in one-to-one correspondence.

Exemplarily, the solder balls <NUM> may be soldered on the third pads <NUM> by a ball planting process.

The solder balls <NUM> are electrically connected to the metal wires in the package substrate <NUM> through the third pads <NUM>. At this point, the solder ball <NUM> may serve as an interface between the package substrate <NUM> and outside world, which realizes electrical connection between the chip package structure <NUM> and an external module, and further realizes communication between the chip package structure <NUM> and the external module.

Exemplarily, when the integration rate of the metal wires in the package substrate <NUM> is very high, a signal transmission path between the solder balls <NUM> and the metal wires in the package substrate <NUM> is shortened, which improves the signal transmission speed.

Exemplarily, the pins (i.e., input/output (I/O) terminals) of the first chip <NUM> are redistributed through the package substrate <NUM> and the plurality of solder balls <NUM> located on the second surface B of the package substrate <NUM>. At this point, the chip package structure <NUM> is a fan-out chip package structure, and the fan-out chip package structure is connected to the external module (such as a motherboard or a printed circuit board) through the solder balls <NUM>.

The embodiment of the present disclosure also provides another chip package structure <NUM>. As shown in <FIG> and <FIG>, the chip package structure <NUM> includes the first chip <NUM> and a second chipset <NUM>. The second chipset <NUM> includes a plurality of second chips <NUM>. The plurality of second chips <NUM> are, for example, sequentially stacked in the direction perpendicular to the package substrate <NUM> and away from the package substrate <NUM>.

The first chip <NUM> and the second chip <NUM> may have different functions. For example, the first chip <NUM> may be a controller and the second chip <NUM> may be a memory chip. The memory chip has a memory structure for providing a memory function. There are many types of memory chips.

For example, the memory chip includes but not limited to a Nand chip, a resistive memory chip, a dynamic random-access memory and the like. Of course, the first chip <NUM> may also be the memory chip, and the second chip <NUM> may be the controller, which are not limited by the embodiment of the present disclosure.

In some examples, the chip package structure <NUM> further includes the package substrate <NUM>. The package substrate <NUM> is rigid, and thus can provide support for the first chip <NUM> and the second chip <NUM>.

Exemplarily, as shown in <FIG> and <FIG>, the package substrate <NUM> includes a plurality of dielectric layers <NUM> and a plurality of metal wiring layers <NUM>, which are alternately disposed. One metal wiring layer <NUM> is disposed between two adjacent dielectric layers <NUM>, and one dielectric layer <NUM> is disposed between two adjacent metal wiring layers <NUM>. Each metal wiring layer <NUM> includes a metal line, and the metal lines in two adjacent metal wiring layers <NUM> may run through the dielectric layer <NUM> between the two metal wiring layers <NUM> and be connected as required.

In some examples, as shown in <FIG> and <FIG>, the package substrate <NUM> has a first surface A and a second surface B that are opposite to each other. The first surface is an upper surface of the package substrate shown in <FIG> and <FIG> and the second surface is a lower surface of the package substrate shown in <FIG> and <FIG>.

As shown in <FIG> and <FIG>, the first surface A of the package substrate <NUM> is provided with a first pad <NUM> and a second pad <NUM> disposed at an interval. There may be a plurality of first pads <NUM> and a plurality of second pads <NUM>. <FIG> illustrates nine first pads <NUM> and two second pads <NUM>.

In some examples, as shown in <FIG> and <FIG>, the first chip <NUM> is located on the first surface A of the package substrate <NUM> and electrically connected to the package substrate <NUM>.

Exemplarily, the first chip <NUM> and the first pad <NUM> may be electrically connected by a soldering process. For example, the soldering process may be a hot pressure soldering process, an ultrasonic pressure soldering process or a thermosonic soldering process. Of course, the first chip <NUM> and the first pad <NUM> may also be electrically connected by other means, which is not limited in the embodiments of the present disclosure.

In some examples, as shown in <FIG> and <FIG>, the second chipset <NUM> is located on a side of the first chip <NUM> away from the package substrate <NUM>. The second chipset <NUM> is electrically connected to the package substrate <NUM>, and has no direct electrical connection with the first chip <NUM>.

The second chipset <NUM> and the package substrate <NUM> may be electrically connected in various ways. For example, the second chipset <NUM> and the package substrate <NUM> may be electrically connected through conductive structures <NUM>.

The conductive structures <NUM> are electrically connected to the package substrate <NUM> and the second chipset <NUM>.

Exemplarily, as shown in <FIG>, the conductive structures <NUM> may include wires <NUM>. Ends of the wires <NUM> are electrically connected to the second chipset <NUM>, and the other ends of the wires <NUM> are electrically connected to the exposed metal wiring layers <NUM> on the package substrate <NUM>, so that the second chipset <NUM> is electrically connected to the package substrate <NUM> by bonding leads to the wires <NUM>. At this point, a material of the wires may include at least one of metal gold, metal aluminum, metal silver or metal copper.

Further exemplarily, as shown in <FIG>, the shape of the conductive structure <NUM> may be columnar, for example, cylindrical, prismatic, etc. Of course, the shape of the conductive pillar <NUM> may also be other irregular shapes, which is not limited by the embodiment of the present disclosure. At this point, the material of the conductive structure <NUM> may include at least one of metal copper, metal aluminum, metal silver or tin.

Therefore, in the chip package structure <NUM> according to some embodiments of the present disclosure, the second chipset <NUM> is placed above the first chip <NUM>, so that the package substrate <NUM>, the first chip <NUM> and the second chipset <NUM> form a stacked structure, which improves the compactness of the chip package structure <NUM> and helps to reducing the area of the chip package structure <NUM>. Furthermore, by stacking the plurality of second chips <NUM> to form the second chipset <NUM>, the integration degree of the chip package structure <NUM> can be improved and the product performances of the chip package structure <NUM> can be improved on the basis of ensuring a smaller package area.

Exemplarily, the isolation structure <NUM> is disposed between two adjacent second chips <NUM>. The material of the isolation structures <NUM> may be an adhesive material. Two adjacent second chips <NUM> are connected by the adhesive material.

In some embodiments, two adjacent second chips <NUM> are electrically connected. Two adjacent second chips <NUM> may be electrically connected in various ways.

For example, two adjacent second chips <NUM> may be connected to each other by a wire. The material of the wire may include at least one of metal gold, metal aluminum, metal silver or metal copper.

For another example, the second chip <NUM> has a through silicon via (TSV), and the TSV is filled with a conductive material. The chip package structure <NUM> further includes a third pad <NUM> located between two adjacent second chips <NUM>. As shown in <FIG>, the conductive metal at the TSV and the third pad <NUM> may be electrically connected by a soldering process, thereby realizing electrical connection between two connected second chips <NUM>.

For another example, the second chip <NUM> may include a body and pins located below the body. At this point, the chip package structure <NUM> further includes pads located on the pins and another second chip <NUM>. The second chip <NUM> is electrically connected to another second chip <NUM> through the pads.

With the above arrangement, on the basis of ensuring a smaller package area, the plurality of second chips <NUM> can be directly connected to each other, which shortens the signal transmission path between adjacent second chips <NUM> and improving the signal transmission speed.

In some other embodiments, as shown in <FIG>, in the plurality of second chips <NUM>, each second chip <NUM> is electrically connected to the package substrate <NUM> through the wire <NUM>.

Exemplarily, each second chip <NUM> is respectively electrically connected to the package substrate <NUM>, so that each second chip <NUM> respectively communicates with the first chip <NUM>. At this point, each second chip <NUM> can store different information under control of the first chip <NUM>, which ensures storage diversity of the chip package structure <NUM>.

It should be noted that there may also be a plurality of the first chips <NUM>. When there are a plurality of first chips <NUM>, the plurality of first chips <NUM> may be sequentially stacked in the direction away from the package substrate <NUM>.

As shown in <FIG> and <FIG>, relative to the first surface A of the package substrate <NUM>, a surface on a side of the second chipset <NUM> close to the package substrate <NUM> is higher than a surface on a side of the first chip <NUM> away from the package substrate <NUM>. That is, there is a certain distance between the surface on the side of the second chipset <NUM> close to the package substrate <NUM> and the surface on the side of the first chip <NUM> away from the package substrate <NUM>. That is, in the direction perpendicular to the first surface A, the first chip <NUM> and the second chipset <NUM> are disposed at intervals.

Exemplarily, the distance between the surface on the side of the second chipset <NUM> close to the package substrate <NUM> and the surface on the side of the first chip <NUM> away from the package substrate <NUM> is greater than or equal to <NUM>. For example, the distance may be <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc. The "distance" here refers to the distance in the direction perpendicular to the first surface.

With the above arrangement, signal interference between the second chipset <NUM> and the first chip <NUM> can be avoided, which is beneficial to improving the credibility and reliability of the chip package structure <NUM>.

As shown in <FIG>, the distance between the surface on the side of the second chipset <NUM> close to the package substrate <NUM> and the first surface A of the package substrate <NUM> is h1, the distance between the surface on the side of the first chip <NUM> away from the package substrate <NUM> and the first surface A of the package substrate <NUM> is h2, and h1 and h2 meet:
<MAT>.

In some examples, the distance between the surface on the side of the first chip <NUM> away from the package substrate <NUM> and the first surface A of the package substrate <NUM> ranges from <NUM> to <NUM>. At this point, the distance between the surface on the side of the second chipset <NUM> close to the package substrate <NUM> and the first surface A of the package substrate <NUM> may be <NUM> to <NUM>. For example, when the distance between the surface on the side of the first chip <NUM> away from the package substrate <NUM> and the first surface A of the package substrate <NUM> is <NUM>, the distance between the surface on the side of the second chipset <NUM> close to the package substrate <NUM> and the first surface A of the package substrate <NUM> may be <NUM>. For another example, when the distance between the surface on the side of the first chip <NUM> away from the package substrate <NUM> and the first surface A of the package substrate <NUM> is <NUM>, the distance between the surface on the side of the second chipset <NUM> close to the package substrate <NUM> and the first surface A of the package substrate <NUM> may be <NUM>.

With the above arrangement, a certain distance can be ensured between the first chip <NUM> and the second chipset <NUM>, and then the signal interference between the first chip <NUM> and the second chipset <NUM> can be avoided. On this basis, the distance between the first chip <NUM> and the second chipset <NUM> can be prevented from being too large, which ensures the thin and light structure of the chip package structure <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the chip package structure <NUM> further includes the package layer <NUM>. The package layer <NUM> is located between the package substrate <NUM> and the second chipset <NUM>, and the package layer <NUM> covers the first chip <NUM>.

Exemplarily, the package layer <NUM> is a whole layer structure, and the surface on the side of the package layer <NUM> away from the package substrate <NUM> is, for example, a flat surface. When the shape of the conductive structure <NUM> is columnar, the surface on the side of the package layer <NUM> away from the package substrate <NUM> is, for example, flush with the surface on the side of the conductive structure <NUM> away from the package substrate <NUM>, and the package layer <NUM> exposes the surface on the side of the conductive structure <NUM> away from the package substrate <NUM>.

Exemplarily, the area of the orthographic projection of the package layer <NUM> on the package substrate <NUM> is basically consistent with the area of the first surface A of the package substrate <NUM>; and the boundary of the orthographic projection of the package layer <NUM> on the package substrate <NUM> is basically coincident with the boundary of the first surface A of the package substrate <NUM>.

Exemplarily, the material of the package layer <NUM> may be a molding compand material. At this point, the package layer <NUM> may be formed by a molding process. The material of the package layer <NUM> may also be other materials, which is not limited by the embodiment of the present disclosure.

With the above arrangement, not only can the first chip <NUM> be packaged by the package layer <NUM>, but also the first chip <NUM> can be physically protected by the package layer <NUM>, and the position of the first chip <NUM> on the package substrate can be fixed to ensure the structure integrity and stability of the chip package structure <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, an orthographic projection of the second chipset <NUM> on the package substrate <NUM> is located within the range of the orthographic projection of the package layer <NUM> on the package substrate <NUM>.

Exemplarily, the area of the orthographic projection of the second chipset <NUM> on the package substrate <NUM> is less than the area of the orthographic projection of the package layer <NUM> on the package substrate <NUM>. The boundary of the orthographic projection of the package layer <NUM> on the package substrate <NUM> surrounds a boundary of the orthographic projection of the second chipset <NUM> on the package substrate <NUM>, and there is a certain distance between the two boundaries.

With the above arrangement, the package layer <NUM> can provide certain support for the second chipset <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, the chip package structure <NUM> further includes the first filling portion <NUM>. At least part of the first filling portion <NUM> is located between the package layer <NUM> and the second chipset <NUM>, and the first filling portion <NUM> surrounds each pin of one second chip <NUM> close to the package substrate <NUM>.

Exemplarily, the first filling portion <NUM> is located between the package layer <NUM> and the second chipset <NUM>, and the second chipset <NUM> covers the first filling portion <NUM>. Alternatively, the first filling portion <NUM> is located not only between the package layer <NUM> and the second chipset <NUM>, but also on both sides of one second chip <NUM> close to the package substrate <NUM>, and an orthographic projection of one second chip <NUM> close to the package substrate <NUM> on the package substrate <NUM> is located within the range of an orthographic projection of the first filling portion <NUM> on the package substrate <NUM>.

The first filling portion <NUM> is filled between any two adjacent pins of one second chip <NUM> close to the package substrate <NUM> to avoid short circuit between the two adjacent pins.

Exemplarily, a material of the first filling portion <NUM> may be an epoxy resin material or the like. When the epoxy resin material or the like is filled between the package layer <NUM> and the second chipset <NUM> to form the first filling portion <NUM>, a hole may be formed, and the area of the hole is, for example, less than or equal to <NUM>%.

In the present embodiment, by disposing the first filling portion <NUM> between the package layer <NUM> and the second chipset <NUM>, not only can the support be provided for the second chipset <NUM>, but also the bonding force between the second chipset <NUM> and the package layer <NUM> is enhanced, and structure stability of the second chipset <NUM> is ensured, thereby improving the reliability of the chip package structure <NUM>. The short circuit between any two adjacent pins of one second chip <NUM> close to the package substrate <NUM> can also be avoided, thereby ensuring the yield of the chip package structure <NUM>.

In some embodiments, as shown in <FIG>, the chip package structure <NUM> further includes the electromagnetic shielding layer <NUM>. The electromagnetic shielding layer <NUM> at least covers the second chipset <NUM> as well as sides of the package layer <NUM>.

Exemplarily, the electromagnetic shielding layer <NUM> covers the second chipset <NUM> as well as sides of the package layer <NUM>. Alternatively, the electromagnetic shielding layer <NUM> covers not only the second chipset <NUM> as well as sides of the package layer <NUM>, but also other components, for example, the electromagnetic shielding layer <NUM> also covers sides of the first filling portion <NUM>, etc., which is not limited by the embodiment of the present disclosure.

By disposing the electromagnetic shielding layer <NUM>, the first chip <NUM> and the second chipset <NUM> can be effectively prevented from being subjected to electromagnetic interference, thereby improving the anti-electromagnetic interference capability of the chip package structure <NUM>.

In some embodiments, as shown in <FIG>, the package substrate <NUM> further includes at least one ground wire <NUM>. The ground wire <NUM> is located on the metal wiring layer <NUM>.

In some examples, as shown in <FIG>, the electromagnetic shielding layer <NUM> also covers the sides of the package substrate <NUM>, and is electrically connected to the ground wire <NUM>.

In the present embodiment, the electromagnetic shielding layer <NUM> covers the second chipset <NUM> and the sides of the package layer <NUM> as well as the sides of the package substrate <NUM> to electromagnetically shield the chip package structure <NUM> and effectively prevent electromagnetic interference. Furthermore, the electromagnetic shielding layer <NUM> is electrically connected to the ground wire <NUM>, and can lead electromagnetic radiation out through grounding, which realizes double anti-electromagnetic interference and ensures the efficient operation of the chip package structure <NUM>. At this point, the anti-electromagnetic interference capability of the chip package structure <NUM> is realized by the electromagnetic shielding layer <NUM>, which is low in process cost, simple and convenient to implement and suitable for mass production.

In some embodiments, as shown in <FIG> and <FIG>, the chip package structure <NUM> further includes the second filling portion <NUM>. At least part of the second filling portion <NUM> is located between the package substrate <NUM> and the first chip <NUM>, and the second filling portion <NUM> surrounds each pin of the first chip <NUM>.

Exemplarily, the second filling portion <NUM> is located between the package substrate <NUM> and the first chip <NUM>, and the first chip <NUM> covers the second filling portion <NUM>. Alternatively, the second filling portion <NUM> is located not only between the package substrate <NUM> and the first hip <NUM>, but also on both sides of the first chip <NUM>, and an orthographic projection of the first chip <NUM> on the package substrate <NUM> is located within the range of an orthographic projection of the second filling portion <NUM> on the package substrate <NUM>.

Exemplarily, the material of the second filling portion <NUM> is an epoxy resin material or the like.

When the epoxy resin material or the like is filled between the package substrate <NUM> and the first chip <NUM> to form the second filling portion <NUM>, a hole may be formed, and the area of the hole is, for example, less than or equal to <NUM>%.

In the present embodiment, by disposing the second filling portion <NUM> between the package substrate <NUM> and the first chip <NUM>, not only can the support be provided for the first chip <NUM>, but also the bonding force between the first chip <NUM> and the package substrate <NUM> is enhanced, and the structure stability of the first chip <NUM> is ensured, thereby improving the reliability of the chip package structure <NUM>. The short circuit between any two adjacent pins of the first chip <NUM> can also be avoided, which ensures the yield of the chip package structure <NUM>.

In some embodiments, as shown in <FIG> and <FIG>, third pads <NUM> are disposed on the second surface B of the package substrate <NUM>. The third pads <NUM> are located on the metal wiring layers <NUM>. For example, a number of third pads <NUM> is greater than one.

Exemplarily, the solder resist layer <NUM> is provided with a plurality of vias, and each via exposes one third pad <NUM>.

In some examples, as shown in <FIG> and <FIG>, the chip package structure <NUM> further includes the solder balls <NUM>. A number of solder balls <NUM> is greater than one, and the plurality of solder balls <NUM> are located on the second surface B of the package substrate <NUM> and electrically connected to the package substrate <NUM>.

The solder balls <NUM> are electrically connected to the metal wires in the package substrate <NUM> through the third pads <NUM>. At this point, the solder balls <NUM> may serve as an interface between the package substrate <NUM> and the outside world, which realizes the electrical connection between the chip package structure <NUM> and the external module, and further realizes the communication between the chip package structure <NUM> and the external module.

Exemplarily, when the integration rate of the metal wires in the package substrate <NUM> is very high, the signal transmission path between the solder balls <NUM> and the metal wires in the package substrate <NUM> is shortened, and the signal transmission speed is improved.

The embodiment of the present disclosure also provides an electronic device <NUM>. As shown in <FIG>, the electronic device <NUM> includes the chip package structure <NUM> according to some above embodiments.

Exemplarily, as shown in <FIG>, the electronic device may further include a cover plate <NUM>, a display screen <NUM>, a middle frame <NUM>, and a back shell <NUM>.

The display screen <NUM> may be a liquid crystal display (LCD) screen, and may also be an organic light emitting diode (OLED) display screen, a quantum dot light emitting diode (QLED) display screen, a mini light emitting diode (Mini LED) display screen or a micro light emitting diode (Micro LED) display screen, etc. The OLED display screen, QLED display screen, Mini LED display screen and Micro LED display screen are all self-luminous display screens.

The middle frame <NUM> may include a carrier plate <NUM> and a frame <NUM>. The electronic device <NUM> may further include a circuit board <NUM> disposed on the carrier plate <NUM>. The chip package structure <NUM> is disposed on the circuit board <NUM> and electrically connected to the circuit board <NUM>.

The beneficial effects that can be achieved by the electronic device according to the present disclosure can refer to the above beneficial effects of the semiconductor structure, which will not be repeated here.

The above electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet and smart glasses), a mobile power supply, a game machine, a digital multimedia player, etc..

The embodiment of the present disclosure provides a manufacturing method of a chip package structure, and the manufacturing method is, for example, used for preparing the chip package structure <NUM> according to some above embodiments. <FIG> is a flowchart of a manufacturing method of a chip package structure according to some embodiments of the present disclosure. <FIG>, <FIG>, <FIG>, and <FIG> are respectively structure cross-sectional diagrams corresponding to steps in the manufacturing method of a chip package structure according to some embodiments. It should be understood that the steps shown in <FIG> are not exclusive, and other steps may be executed before, after or between any shown steps. In addition, some of these steps may be executed simultaneously, or may be executed in an order different from that shown in <FIG>.

As shown in <FIG>, the above manufacturing method includes the following steps S1 to S4.

S1: as shown in <FIG>, the package substrate <NUM> is provided.

Exemplarily, the structure of the package substrate <NUM> may refer to the illustrations in some above embodiments, which will not be repeated here.

S2: as shown in <FIG> and <FIG>, the conductive pillars <NUM> are formed on the first surface A of the package substrate <NUM>, and the conductive pillars <NUM> are electrically connected to the package substrate <NUM>.

Exemplarily, the conductive pillars <NUM> may be formed by a sputtering process or an electroplating process. The material of the conductive pillars <NUM> may include at least one of copper, aluminum, silver or tin.

S3: as shown in <FIG>, the first chip <NUM> is disposed on the first surface A of the package substrate <NUM>. The first chip <NUM> is electrically connected to the package substrate <NUM>.

Exemplarily, a connection way of the first chip <NUM> and the package substrate <NUM> may refer to the illustrations in some above embodiments, which will not be repeated here.

S4: as shown in <FIG>, the second chip <NUM> is disposed on a side of the conductive pillars <NUM> and the first chip <NUM> away from the package substrate <NUM>. The second chip <NUM> is electrically connected to the conductive pillars <NUM>.

Exemplarily, the orthographic projections of the conductive pillars <NUM> on the package substrate <NUM> are located within the orthographic projection of the first chip <NUM> or the second chip <NUM> on the package substrate <NUM>.

The manufacturing method disclosed in the above embodiment of the present disclosure has the same structure and beneficial effects as the chip package structure <NUM> according to some above embodiments, which will not be repeated here.

It should be noted that some steps of the above manufacturing method may be executed simultaneously, or may be executed in an order different from that shown in <FIG>. For example, the above steps S2 and S3 may be reversed, that is, the first chip <NUM> is firstly disposed on the first surface A of the package substrate <NUM>, and then the conductive pillars <NUM> are formed on the first surface A of the package substrate <NUM>.

In some embodiments, after the above step S2, the above manufacturing method further includes: S10 to S20.

S10: as shown in <FIG>, a package film <NUM> is formed on the first chip <NUM> and the conductive pillars <NUM>, and the package film <NUM> covers the first chip <NUM> and the conductive pillars <NUM>.

Exemplarily, the embodiment of the present disclosure may use chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form the package film <NUM>. A thickness of the package film is greater than the height of the conductive pillar and the thickness of the first chip, that is, relative to the package substrate, the surface on the side of the package film away from the package substrate is higher than the surface on the side of the conductive pillar away from the package substrate and higher than the surface on the side of the first chip away from the package substrate.

S20: as shown in <FIG>, the package film <NUM> is thinned to expose the conductive pillars <NUM>, and the remaining package film <NUM> forms the package layer <NUM>; the package layer <NUM> covers the first chip <NUM>.

Exemplarily, the package film <NUM> may be thinned by mechanical polishing, chemical mechanical planarization, wet etching and other thinning processes. In the above step S20, in the process of thinning the package film, the height of the conductive pillars <NUM> may also be lowered to ensure that the conductive pillars <NUM> are exposed, thereby improving an electrical connection yield between the conductive pillars <NUM> and the second chip <NUM>.

Specifically, the package film <NUM> covering the first chip <NUM> and the conductive pillars <NUM> may be formed by a molding material through a molding process.

In some embodiments, the above step S2 includes: S21 to S23.

S21: as shown in <FIG>, the package layer <NUM> is formed on the first chip <NUM>, and the package layer <NUM> covers the first chip <NUM>.

Specifically, the covering package layer <NUM> may be formed by the molding material through the molding process.

S22: as shown in <FIG>, vias <NUM> are formed in the package layer <NUM>, and the vias <NUM> expose the second pads <NUM>.

Exemplarily, in the embodiment of the present disclosure, the vias <NUM> may be formed through an etching process. The shape of the vias <NUM> may be columnar, for example, cylindrical and the like. The shape of the vias <NUM> may also be other irregular shapes, which is not limited by the embodiment of the present disclosure.

S23: as shown in <FIG>, a conductive material is filled in the vias to form the conductive pillars <NUM>.

Exemplarily, the material of the conductive pillars <NUM> may be tin or the like. At this point, solder balls may be filled in the vias and reflowed to form solder pillars, which are the above conductive pillars <NUM>.

In some embodiments, as shown in <FIG>, the above manufacturing method further includes: filling a first insulating material between the package layer <NUM> and the second chip <NUM> to form the first filling portion <NUM>, and the first filling portion <NUM> surrounds each pin of the second chip <NUM>.

Exemplarily, the first filling portion <NUM> is located between the package layer <NUM> and the second chip <NUM>, and the second chip <NUM> covers the first filling portion <NUM>. Alternatively, the first filling portion <NUM> is located not only between the package layer <NUM> and the second chip <NUM>, but also on both sides of the second chip <NUM>, and the orthographic projection of the second chip <NUM> on the package substrate <NUM> is located within the range of the orthographic projection of the first filling portion <NUM> on the package substrate <NUM>.

Exemplarily, the first insulating material may be an epoxy resin material or the like.

In the present embodiment, by disposing the first filling portion <NUM> between the package layer <NUM> and the second chip <NUM>, not only can the support be provided for the second chip <NUM>, but also the bonding force between the second chip <NUM> and the package layer <NUM> is enhanced, which ensures the structure stability of the second chip <NUM>, and also avoids short circuit between any two adjacent pins of the second chip <NUM>, thereby further ensuring the yield of the chip package structure <NUM>.

In some embodiments, the above manufacturing method further includes: forming the electromagnetic shielding layer <NUM>, and the electromagnetic shielding layer <NUM> at least covers the second chip <NUM> as well as the sides of the package layer <NUM>, as shown in <FIG>.

Exemplarily, in the embodiment of the present disclosure, the electromagnetic shielding layer <NUM> may be formed on the second chip <NUM> as well as the sides of the package layer <NUM> by means of spraying, electroplating, vacuum sputtering or the like. For example, the ferromagnetic material may be sprayed on the second chip <NUM> as well as the sides of the package layer <NUM> to form the electromagnetic shielding layer <NUM>.

By disposing the electromagnetic shielding layer <NUM>, the first chip <NUM> and the second chip <NUM> can be effectively prevented from being subjected to electromagnetic interference, thereby improving the anti-electromagnetic interference capability of the chip package structure <NUM>.

In some embodiments, the second chip <NUM> includes a plurality of sub-chips <NUM>. At this point, the above step S4 includes: S41 to S42.

S41: as shown in <FIG>, the plurality of sub-chips <NUM> are sequentially stacked along a thickness direction of the sub-chips <NUM> to form the second chip <NUM>.

For example, the plurality of sub-chips <NUM> are stacked in sequence along the direction perpendicular to the package substrate <NUM> and away from the package substrate <NUM>. For example, the types of the plurality of sub-chips are the same, and optionally, the plurality of sub-chips are all memory chips.

In some examples, an isolation structure <NUM> is disposed between two adjacent sub-chips <NUM>. The material of the isolation structure <NUM> may be an adhesive material. Two adjacent sub-chips <NUM> are stacked by the adhesive material.

Exemplarily, there may be a plurality of connection relationships of the plurality of sub-chips <NUM>, and the details may refer to the illustrations in some above embodiments, and will not be repeated here.

S42: as shown in <FIG>, the second chip <NUM> is soldered to ends of the conductive pillars <NUM> away from the package substrate <NUM>, so that the second chip <NUM> is electrically connected to the conductive pillars <NUM>.

Exemplarily, as shown in <FIG>, after the above step S42, the electromagnetic shielding layer <NUM> may be formed, and the electromagnetic shielding layer <NUM> at least covers the plurality of sub-chips <NUM> and the sides of the package layer <NUM>.

In the present embodiment, by stacking the plurality of sub-chips <NUM> to form the second chip <NUM>, the integration degree of the chip package structure <NUM> can be improved and the product performances of the chip package structure <NUM> can be improved on the basis of ensuring a small package volume.

In some embodiments, after the first chip <NUM> is disposed and before the second chip <NUM> is disposed, the above manufacturing method further includes: filling a second insulating material between the package substrate <NUM> and the first chip <NUM> to form the second filling portion <NUM>, and the second filling portion <NUM> surrounds each pin of the first chip <NUM>, as shown in <FIG>.

Exemplarily, the second insulating material may be an epoxy resin material or the like. At this point, in the present embodiment, by disposing the second filling portion <NUM> between the package substrate <NUM> and the first chip <NUM>, not only can the support be provided for the first chip <NUM>, but also the bonding force between the first chip <NUM> and the package substrate <NUM> is improved, and the structure stability of the first chip <NUM> is ensured. The short circuit between any two adjacent pins of the first chip <NUM> can also be avoided, which ensures the yield of the chip package structure <NUM>.

In some embodiments, third pads <NUM> are disposed on the second surface B of the package substrate <NUM>. The first surface A and the second surface B are opposite to each other. Before or after forming the package layer <NUM>, the above manufacturing method further includes: forming the solder balls <NUM> on the second surface B of the package substrate <NUM>, and the solder balls <NUM> are electrically connected to the third pads <NUM>, as shown in <FIG>.

Exemplarily, a number of solder balls <NUM> is greater than one, the plurality of solder balls <NUM> may form a ball grid array (BGA), and the ball grid array may serve as an interface between the chip package structure <NUM> and the outside world.

Claim 1:
A chip package structure (<NUM>, <NUM>'), comprising:
a package substrate (<NUM>, <NUM>') having a first surface;
a first chip (<NUM>, <NUM>') located on the first surface (A) of the package substrate (<NUM>, <NUM>') and electrically connected to the package substrate (<NUM>, <NUM>');
a conductive pillar (<NUM>) located on the first surface (A) of the package substrate (<NUM>, <NUM>') and electrically connected to the package substrate (<NUM>'); and
a second chip (<NUM>', <NUM>) located on a side of the first chip (<NUM>, <NUM>') and the conductive pillar (<NUM>) away from the package substrate (<NUM>, <NUM>') and electrically connected to the conductive pillar (<NUM>), an orthographic projection of the conductive pillar (<NUM>) on the package substrate (<NUM>, <NUM>') being located within a range of an orthographic projection of the first chip (<NUM>, <NUM>') or the second chip (<NUM>', <NUM>) on the package substrate (<NUM>, <NUM>'),
wherein a surface on a side of the second chip (<NUM>', <NUM>) close to the package substrate (<NUM>, <NUM>') is higher than a surface on a side of the first chip (<NUM>, <NUM>') away from the package substrate (<NUM>, <NUM>'), with respect to the first surface (A) of the package substrate (<NUM>, <NUM>'),
characterized in that a distance between the surface on the side of the second chip (<NUM>', <NUM>) close to the package substrate (<NUM>, <NUM>') and the first surface (A) of the package substrate (<NUM>, <NUM>') is h1, a distance between the surface on the side of the first chip (<NUM>, <NUM>') away from the package substrate (<NUM>, <NUM>') and the first surface (A) of the package substrate (<NUM>, <NUM>') is h2, and h1 and h2 meet the following condition: <MAT>