Patent Description:
Such semiconductor packages are known from <CIT> and <CIT>, respectively. <CIT> discloses a bottom chip package having a first side and a second side opposing the first side, the bottom chip package comprising a first semiconductor chip and a second semiconductor chip; a top antenna package mounted on the first side of the bottom chip package, wherein the top antenna package comprises a radiative antenna element; and a first connector disposed on the second side, wherein the top antenna package comprises a substrate, wherein the first radiative antenna element is disposed on a surface of the substrate. <CIT> discloses a microelectronic device that includes a first silicon based substrate having compound semiconductor components. <CIT> discloses a circuit module, which includes a wiring substrate including a mounting surface having first and second areas and a terminal surface on the other side of the mounting surface.

As known in the art, shorter interconnect between chips and antennas is more and more critical in millimeter-wave (mmW) applications. To achieve shorter interconnect between chips and antennas, as well as smaller volume and higher integration of semiconductor packages, Antenna in Package (AiP) that consists of integrated circuit (IC) chips and antenna(s) inside a package has been developed in the field of semiconductor chip packaging.

Unfortunately, demands on the substrate layers are quite different between the antennas and the routing design. Typically, it is required to employ thin build-up layers in the substrate layers so as to enable thin vias and dense interconnects. However, this requirement conflicts with the requirements for antenna design, which typically needs thick, almost evenly spaced substrate layers.

One object of the present disclosure is to provide an improved semiconductor package to overcome the deficiencies and disadvantages of the prior art. Semiconductor package according to the invention is defined in the independent claim. The dependent claims define preferred embodiments thereof.

The invention provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side. The bottom chip package comprises a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package comprises a radiative antenna element. A first connector is disposed on the second side, wherein the top antenna package comprises a substrate, wherein the first radiative antenna element is disposed on a surface of the substrate, a first passive component; and a second passive component, wherein the first passive component and the second passive component comprise discrete capacitors, wherein the first passive component is disposed on the first side and the second passive component is disposed on the second side.

Preferably, the first semiconductor chip comprises a RFIC chip and the second semiconductor chip comprises a power management IC chip.

The top antenna package comprises a substrate.

Preferably, the substrate comprises a ceramic substrate, a semiconductor substrate, a dielectric substrate, or a glass substrate.

Preferably, the substrate comprises at least one plated through-hole to route signals from one side of the substrate to the other side of the substrate.

The first radiative antenna element is disposed on a surface of the substrate.

Preferably, the top antenna package is a low temperature co-fired ceramic (LTCC), a flip-chip chip-scale-package (FCCSP), a laminate-based package, wire-bond type package or a fan-out type chip package.

Preferably, the semiconductor package further includes: a molding compound encapsulating the first semiconductor chip and the second semiconductor chip.

Preferably, the semiconductor package further includes: a metal coating layer on the molding compound.

Preferably, the top antenna package is electrically coupled to the first side of the bottom chip package via a plurality of conductive elements.

Preferably, the plurality of conductive elements comprises solder balls, solder bumps, copper bumps or gold bumps.

Preferably, the connector is coplanar with the first semiconductor chip and the second semiconductor chip on the second side.

Not belonging to the invention but for further explanation of the context, a semiconductor package is provided including a bottom chip package having a first side and a second side opposing the first side. The bottom chip package includes a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package includes a radiative antenna element. A connector is disposed on a bottom surface of the top antenna package.

Not belonging to the invention but for further explanation of the context, the connector is electrically coupled to the bottom chip package through a trace in the top antenna package.

A semiconductor package is provided including a chip package having a first side and a second side opposing the first side. The chip package includes a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. Preferably, multiple antenna packages are mounted on the first side of the chip package. Each of the plurality of antenna packages comprises a radiative antenna element. A first connector is disposed on the second side.

Preferably, the multiple antenna packages are physically separated from one another.

Preferably, the radiative antenna element comprises an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals.

In the drawings:.

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.

The terms "die", "chip", "semiconductor chip", and "semiconductor die" are used interchangeable throughout the specification to mean integrated circuit chip or die. The term "horizontal" as used herein may be defined as a direction parallel to a plane or surface (e.g., surface of a substrate), regardless of its orientation. The term "vertical," as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as "on," "above," "below," "bottom," "top," "side" (as in "sidewall"), "higher," "lower," "upper," "over," and "under," may be referenced with respect to the horizontal plane.

The present disclosure pertains to a semiconductor package including at least one discrete antenna device (or top antenna package) mounted on a bottom semiconductor chip package (or bottom chip package), thereby forming an antenna package-on-package structure. The exemplary semiconductor packages disclosed in various embodiments herein provide the advantages including, but not limited to, lower package cost, shorter lead-time, and/or better design flexibility over the conventional antenna in packages.

<FIG> is a schematic, cross-sectional diagram showing an exemplary semiconductor package 1a including a discrete antenna device mounted on a bottom chip package for further elaborating the context of the invention but not belonging to it. Preferably, the semiconductor package may be a wireless module and the discrete antenna device may be an antenna package. As shown in <FIG>, the semiconductor package 1a comprises a bottom chip package <NUM> and a top antenna package <NUM> mounted on the bottom chip package <NUM>. The bottom chip package <NUM> has a first side 10a and a second side 10b that is opposite to the first side 10a. The top antenna package <NUM> may be mounted on the first side 10a. The bottom chip package <NUM> may comprise a semiconductor chip (or semiconductor die) <NUM> mounted on the second side 10b. For example, the semiconductor chip <NUM> may be a RFIC chip, a base-band IC chip, a System-in-Chip (SOC) die, but is not limited thereto.

Preferably, the bottom chip package <NUM> may comprise a package substrate <NUM> having a core <NUM> with one or more plated through-holes <NUM>, and one or more build-up layers <NUM>. The build-up layers <NUM> may have one or more vias <NUM> and/or conductive traces <NUM> formed therein to route signals, ground, and/or power throughout the bottom chip package <NUM>. Conductive traces <NUM> on a bottom surface of the bottom build-up layer <NUM> may be in the form of one or more pads onto which the semiconductor chip <NUM> may be attached with conductive elements <NUM>. For example, the conductive elements <NUM> may comprise solder balls, solder bumps, copper bumps, gold bumps, or any suitable conductive means known in the art.

For example, the core <NUM> may include any suitable material comprising epoxy laminates of fiberglass sheets, prepreg, FR-<NUM> materials, FR-<NUM> materials, or combinations thereof. The conductive traces <NUM>, <NUM>, the plated through-holes <NUM>, and the vias <NUM> may include any suitable conductive materials comprising copper, silver, gold, nickel, or combinations thereof. The build-up layers <NUM> may include any suitable dielectric materials comprising polyimide, prepreg, polymers, or the like.

Preferably, the bottom chip package <NUM> may further comprise solder mask layers <NUM> on the first side 10a and the second side 10b. For interconnection purposes, the solder mask layers <NUM> may comprise openings for exposing the corresponding pads in the conductive traces <NUM>. Preferably, an array of conductive elements <NUM> may be disposed on the second side 10b of the bottom chip package <NUM> for further interconnection to a printed circuit board or a main board.

The top antenna package <NUM> is electrically coupled to the bottom chip package <NUM> through conductive elements <NUM>, which are coupled to the traces <NUM> on the top surface of the top build-up layer <NUM> in the form of one or more pads and to the traces <NUM> on the bottom surface of the substrate <NUM> in the form of one or more pads. For example, the conductive elements <NUM> may comprise solder balls, solder bumps, copper bumps, gold bumps, or any suitable conductive means known in the art. The top antenna package <NUM> may comprise a substrate <NUM>. The substrate <NUM> may comprise one or more plated through-holes <NUM> to route signals from one side of the substrate <NUM> to the other side of the substrate <NUM>.

For example, the substrate <NUM> may be a ceramic substrate, a semiconductor substrate, a dielectric substrate, a glass substrate, but is not limited thereto. Preferably, the top antenna package <NUM> may be a low temperature co-fired ceramic (LTCC), a flip-chip chip-scale-package (FCCSP), a fan-out type chip package, a laminate-based package or a wire-bond type package and not limited.

Preferably, the top antenna package <NUM> does not include a semiconductor chip or die. The top antenna package <NUM> may further comprise a radiative antenna element <NUM> in the conductive trace <NUM> disposed on a surface of the substrate <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or millimeter-wave (mmW) signals. Although not shown in this figure, it is understood that the radiative antenna element <NUM> may be disposed at a bottom surface of the substrate <NUM> depending upon the design requirements. For example, the radiative antenna element <NUM> may be may be of any suitable type, such as patch antennas, slot-coupled antenna, stacked patches, dipoles, monopoles, etc., and may have different orientations and/or polarizations. Preferably, the radiative antenna element <NUM> could route signals from one side of the substrate <NUM> to the other side of the substrate <NUM> through one or more plated through-holes <NUM> or other conductive traces disposed within the substrate <NUM>.

Besides, the radiative antenna element <NUM> could comprise multiple antenna modules, for example, a dual-band antenna element and a single-band antenna element, and not limited.

<FIG> show some exemplary variants of the semiconductor package as depicted in <FIG> for further elaborating the context of the invention but not belonging to it, wherein like numeral numbers designate like layers, regions, or elements. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.

As shown in <FIG>, the difference between the semiconductor package 1b and the semiconductor package 1a is that the semiconductor chip <NUM> of the semiconductor package 1b is disposed on the same side as the top antenna package <NUM>. For example, the semiconductor chip <NUM> and the top antenna package <NUM> are both mounted on the first side 10a of the bottom chip package <NUM>. Likewise, the semiconductor chip <NUM> may be attached with the corresponding pads in the conductive trace <NUM> through the conductive elements <NUM>. Although not shown in the figures, it is to be understood that an underfill layer may be disposed between the semiconductor chip <NUM> and the first side 10a of the bottom chip package <NUM>. In a non-liming example, the semiconductor chip <NUM> may be mounted directly under the top antenna package <NUM>.

As shown in <FIG>, and briefly to <FIG>, the difference between the semiconductor package 1c and the semiconductor package 1b is that the semiconductor package 1c further comprises a molding compound <NUM> between the top antenna package <NUM> and the bottom chip package <NUM>. Preferably, the molding compound <NUM> may comprise epoxy or polymers, but is not limited thereto. The molding compound <NUM> may cover and encapsulate the semiconductor chip <NUM>. Preferably, the molding compound <NUM> may fill into the gap between the semiconductor chip <NUM> and the first side 10a of the bottom chip package <NUM>. Preferably, the molding compound <NUM> may comprise through mold vias 410a. The conductive elements <NUM> may be disposed within the through mold vias 410a, respectively.

As shown in <FIG>, and briefly to <FIG>, the difference between the semiconductor package 1d and the semiconductor package 1b is that the semiconductor chip <NUM> of the semiconductor package 1d is embedded in the core <NUM> of the package substrate <NUM>. It is understood that the semiconductor chip <NUM> may be directly embedded in the build-up layers <NUM>. For example, the semiconductor chip <NUM> may be mounted on the core <NUM> of the package substrate <NUM> and embedded inside a film of dielectric layer. Preferably, a cavity (not shown) may be formed in the package substrate <NUM> and the semiconductor chip <NUM> is placed inside this cavity. The semiconductor chip <NUM> may be bonded by conventional bonding techniques.

As shown in <FIG>, the semiconductor package 1e comprises multiple semiconductor dies, for example, a semiconductor chip 30a and a semiconductor chip 30b, which may be disposed on the first side 10a and the second side 10b of the bottom chip package <NUM>, respectively. The semiconductor chip 30a may be electrically connected to the package substrate <NUM> through the conductive elements 312a. The semiconductor chip 30b may be electrically connected to the package substrate <NUM> through the conductive elements 312b.

As shown in <FIG>, the semiconductor package 1f comprises multiple semiconductor dies, for example, a semiconductor chip 30a and a semiconductor chip 30b. The semiconductor chip 30a may be disposed on the first side 10a of the bottom chip package <NUM>. The semiconductor chip 30b may be embedded in the package substrate <NUM>.

As shown in <FIG>, likewise, the semiconductor package <NUM> comprises a bottom chip package <NUM> and the top antenna package <NUM> mounted on the first side 10a of the bottom chip package <NUM>. According to the illustrated embodiment, the top antenna package <NUM> may be larger in size than the bottom chip package <NUM>.

As shown in <FIG>, the semiconductor package <NUM> comprises a bottom chip package <NUM> and multiple top antenna packages, for example, top antenna package 20a and top antenna package 20b, mounted on the first side 10a of the bottom chip package <NUM>. The semiconductor chip <NUM> may be mounted on the second side 10b of the bottom chip package <NUM>. According to the illustrated embodiment, the top antenna packages 20a and 20b may be smaller in size than the bottom chip package <NUM>. According to another embodiment, the top antenna packages 20a and 20b may be larger in size than the bottom chip package <NUM>.

As shown in <FIG>, the semiconductor package 1i comprises a bottom chip package <NUM> and a top antenna package <NUM> mounted on the first side 10a of the bottom chip package <NUM>. The top antenna package <NUM> may comprise a radiative antenna element <NUM> in the conductive trace <NUM> disposed on a surface of the substrate <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or millimeter-wave mmW signals.

The semiconductor package 1i may further comprise a radiative antenna element <NUM> in the conductive trace <NUM> disposed on the first side 10a of the bottom chip package <NUM>. The radiative antenna element <NUM> does not overlap with the radiative antenna element <NUM>. In a non-limiting example, the radiative antenna element <NUM> may be a dual-band antenna element, and the radiative antenna element <NUM> may be a single-band antenna element.

It is advantageous to use the present disclosure because by forming the top antenna package <NUM> separately from the bottom chip package <NUM>, lower package cost, shorter lead-time, and better design flexibility may be achieved. The top antenna package <NUM> and the bottom chip package <NUM> may be manufactured with materials, structure, and/or processes that may be relatively optimal for the semiconductor package. For example, the bottom chip package <NUM> may be manufactured with multi-layer interconnect (e.g., multiple build-up layers on either side of the core <NUM>) to accommodate dense routing. The top antenna package <NUM>, on the other hand, in this example, may only have a single layer (e.g., a strip of dielectric with pad interfaces on one side and radiating elements on the other side). In non-limiting examples, a low-k dielectric may be used in the bottom chip package <NUM> to route signals with reduced parasitics (e.g., reduced resistive- capacitive (RC) delays), while relatively higher-k materials may be employed in the top antenna package <NUM> to enable reduced form factor antennas.

<FIG> are schematic, cross-sectional diagram showing some exemplary packages, for example, top antenna packages, for further elaborating the context of the invention but not belonging to it, wherein like numeral numbers designate like layers, regions, or elements. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise. For the sake of simplicity, only germane portions of the exemplary top antenna packages are shown in the figures.

It is to be understood that the structures or features as depicted in <FIG> are not limited to the top antenna packages. It is to be understood that the structures or features as depicted in <FIG> may be employed in the bottom chip packages <NUM> as set forth in previous figures.

As shown in <FIG>, the top antenna package 2a comprises a substrate <NUM>. For example, the substrate <NUM> may be a ceramic substrate, a semiconductor substrate, a dielectric substrate, a glass substrate, but is not limited thereto. Conductive traces <NUM> are formed on opposite surfaces of the substrate <NUM>. The substrate <NUM> may comprise one or more plated through-holes <NUM> to route signals from one side of the substrate <NUM> to the other side of the substrate <NUM>. Preferably, for example, the top antenna package 2a may be a package with a chip or an electronic element. On one surface of the substrate <NUM>, for example, a bottom surface of the substrate <NUM>, a re-wiring layer <NUM> may be disposed on the bottom surface of the substrate <NUM>.

In a non-limiting example, the re-wiring layer <NUM> may comprise a dielectric layer <NUM> laminated on the bottom surface of the substrate <NUM>, a conductor layer <NUM> on the dielectric layer <NUM>, and a protective layer <NUM> on the conductor layer <NUM>. The dielectric layer <NUM> may comprise any suitable insulating layers such as silicon oxide, silicon nitride, polyimide or the like. The conductor layer <NUM> may comprise copper, but is not limited thereto. The protective layer <NUM> may comprise any suitable passivation layers or solder masks. The conductor layer <NUM> may be electrically connected to the conductive trace <NUM> through the vias <NUM> in the dielectric layer <NUM>. In a non-limiting example, a semiconductor chip <NUM> may be mounted on the re-wiring layer <NUM>. The semiconductor chip <NUM> may be electrically connected to the conductor layer <NUM> through the contact elements <NUM> and the conductive elements <NUM>. In some other example, the semiconductor chip <NUM> could be omitted.

A radiative antenna element <NUM> may be disposed in the conductive trace <NUM> on a surface of the substrate <NUM>, for example, the top surface of the substrate <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or mmW signals. Although not shown in this figure, it is understood that the radiative antenna element <NUM> may be disposed at a bottom surface of the substrate <NUM> depending upon the design requirements. For example, the radiative antenna element <NUM> may be may be of any suitable type, such as patch antennas, stacked patches, dipoles, monopoles, etc., and may have different orientations and/or polarizations.

As shown in <FIG>, likewise, the top antenna package 2b comprises a core or a substrate <NUM>. For example, the substrate <NUM> may be a ceramic substrate, a semiconductor substrate, a dielectric substrate, a glass substrate, but is not limited thereto. Dielectric layers <NUM> and conductive traces <NUM>, <NUM> are formed on opposite surfaces of the substrate <NUM>. A protective layer <NUM> may be disposed to cover the conductive trace <NUM> and the dielectric layers <NUM>. The dielectric layer <NUM> may comprise any suitable insulating layers such as silicon oxide, silicon nitride, polyimide or the like. The protective layer <NUM> may comprise any suitable passivation layers or solder masks. The substrate <NUM> may comprise one or more plated through-holes <NUM> to route signals from one side of the substrate <NUM> to the other side of the substrate <NUM>.

Preferably, for example, the top antenna package 2b may be an embedded-chip package, which is a package embedded with a semiconductor chip <NUM>. In a non-limiting example, the semiconductor chip <NUM> may embedded in the substrate <NUM>. The semiconductor chip <NUM> may be electrically connected to the conductive trace <NUM> through the contact elements <NUM>. In some other example, the semiconductor chip <NUM> could be omitted.

A radiative antenna element <NUM> may be disposed in the conductive trace <NUM> disposed on the substrate <NUM>, for example, on the top surface of the substrate <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or mmW signals. Although not shown in this figure, it is understood that the radiative antenna element <NUM> may be disposed at a bottom surface of the substrate <NUM> depending upon the design requirements. For example, the radiative antenna element <NUM> may be may be of any suitable type, such as patch antennas, stacked patches, dipoles, monopoles, etc., and may have different orientations and/or polarizations.

As shown in <FIG>, the top antenna package 2c may be a fan-out type chip package, wherein at least some of the package pads and/or conducting lines connecting the chip to the package pads are located laterally outside of the outline of the chip or do at least intersect the outline of the chip. Furthermore, the top antenna package 2c could be a wafer level chip scale package (WLCSP). In a non-limiting example, the top antenna package 2c may comprise a chip <NUM> encapsulated by a first molding compound <NUM>. The first molding compound <NUM> may cover the inactive bottom surface and four sidewall surfaces of the chip <NUM> and may expose an active surface of the chip <NUM>. On the active surface of the chip <NUM>, a plurality of bonding pads or input/output (I/O) pads <NUM> are arranged. In some other example, the semiconductor chip <NUM> could be omitted.

A re-distribution layer (RDL) structure <NUM> may be disposed on the active surface of the chip <NUM> and on a surface of the first molding compound <NUM> and may be electrically connected to the I/O pads <NUM> of the chip <NUM>. In a non-limiting example, the RDL structure <NUM> may comprise dielectric layers <NUM>, <NUM>, and <NUM>, and conductor layers <NUM>, <NUM> in the dielectric layers <NUM>, <NUM>, and <NUM>. At least one conductive element <NUM> such as a solder bump, a solder ball, or a metal bump/pillar may be formed on the dielectric layer <NUM> for further connection. The dielectric layers <NUM>, <NUM>, and <NUM> may comprise any suitable insulating layers such as silicon oxide, silicon nitride, polyimide or the like. The conductor layers <NUM>, <NUM> may comprise copper, but is not limited thereto.

In a non-limiting example, the top antenna package 2c may comprise a conductive trace <NUM> on the first molding compound <NUM>, a second molding compound <NUM> on the first molding compound <NUM> and on the conductive trace <NUM>, a conductive trace <NUM> on the second molding compound <NUM>, a third molding compound <NUM> on the second molding compound <NUM> and on the conductive trace <NUM>, and a conductive trace <NUM> on the third molding compound <NUM>. Through mold vias <NUM> may be disposed in the first molding compound <NUM> for the signal transmission between the RDL structure <NUM> and the conductive traces <NUM>, <NUM> and <NUM>.

Radiative antenna elements <NUM> may be disposed in the conductive traces <NUM>, <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or mmW signals. Although not shown in this figure, it is understood that the radiative antenna elements <NUM> may be disposed in any layers of the conductive traces <NUM>, <NUM> and <NUM> depending upon the design requirements. For example, the radiative antenna element <NUM> may be may be of any suitable type, such as patch antennas, stacked patches, dipoles, monopoles, etc., and may have different orientations and/or polarizations.

As shown in <FIG>, the top antenna package 2d may have a similar stack structure as that depicted in <FIG>. The difference between the top antenna package 2d and the top antenna package 2c depicted in <FIG> is that the semiconductor chip <NUM> of the top antenna package 2d is externally mounted on the RDL structure <NUM>. Likewise, radiative antenna elements <NUM> may be disposed in the conductive traces <NUM>, <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or mmW signals. Although not shown in this figure, it is understood that the radiative antenna elements <NUM> may be disposed in any layers of the conductive traces <NUM>, <NUM> and <NUM> depending upon the design requirements. For example, the radiative antenna element <NUM> may be may be of any suitable type, such as patch antennas, stacked patches, dipoles, monopoles, etc., and may have different orientations and/or polarizations. In some other example, the semiconductor chip <NUM> could be omitted.

For example, <FIG> illustrates an exemplary fan-out type chip package 2e for the top antenna package. As shown in <FIG>, the fan-out type chip package 2e is a package embedded with a semiconductor chip <NUM>, wherein at least some of the package pads <NUM> and/or conducting lines <NUM> connecting the semiconductor chip <NUM> to the package pads <NUM> are located laterally outside of the outline of the semiconductor chip <NUM> or do at least intersect the outline of the semiconductor chip <NUM>. The fan-out type chip package 2e may comprise a molding compound <NUM> encapsulating the sidewalls and a non-active upper surface of the chip <NUM>. The active surface of the semiconductor chip <NUM> is not covered with the molding compound <NUM>. The input/output (I/O) pads <NUM> on the active surface of the semiconductor chip <NUM> are electrically connected to the re-distribution layer (RDL) structure <NUM> constructed on the active surface of the semiconductor chip <NUM> and on the lower surface of the molding compound <NUM>. The RDL structure <NUM> comprises at least one dielectric layer <NUM>, the conducting lines <NUM> in the at least one dielectric layer <NUM> for connecting the I/O pads <NUM> of the semiconductor chip <NUM> to the package pads <NUM>, and at least a radiative antenna element <NUM> in or on the at least one dielectric layer <NUM>. The conductive elements <NUM> such as bumps or solder balls may be disposed on the package pads <NUM> for further connections. In some other example, the semiconductor chip <NUM> could be omitted.

<FIG> is a schematic, cross-sectional diagram showing an exemplary semiconductor package 3a including a discrete antenna device mounted on a bottom chip package for further elaborating the context of the invention but not belonging to it, wherein like layers, regions or elements are designated by like numeral numbers. Preferably, the semiconductor package may be an antenna module that is suited for <NUM> applications.

As shown in <FIG>, the semiconductor package 3a comprises a bottom chip package <NUM> and a top antenna package <NUM> mounted on the bottom chip package <NUM>. The bottom chip package <NUM> has a first side 10a and a second side 10b that is opposite to the first side 10a. The top antenna package <NUM> may be mounted on the first side 10a. The bottom chip package <NUM> may comprise a first semiconductor chip 30a and a second semiconductor chip 30b mounted on the second side 10b in a side-by-side manner. For example, the first semiconductor chip 30a and the second semiconductor chip 30b may be a RFIC chip, a base-band IC chip, a System-in-Chip (SOC) die, a power management IC chip, or a transceiver, but is not limited thereto. For example, the first semiconductor chip 30a may be a RFIC chip and the second semiconductor chip 30b may be a power management IC chip.

Preferably, the first semiconductor chip 30a and the second semiconductor chip 30b may be bonded to the second side 10b by using flip-chip techniques, but is not limited thereto. Preferably, a first passive component <NUM> and a second passive component <NUM> may be mounted on the second side 10b and may be proximate to the first semiconductor chip 30a and the second semiconductor chip 30b, respectively. For example, the first passive component <NUM> and the second passive component <NUM> may comprise discrete capacitors, discrete inductors, or discrete resistors. Preferably, the first semiconductor chip 30a, the second semiconductor chip 30b, the first passive component <NUM> and the second passive component <NUM> may be encapsulated by a molding compound <NUM>. A metal coating layer <NUM> such as a copper layer may be provided on the surface of the molding compound <NUM> for electromagnetic interference (EMI) shielding. Further, a metal inter-wall <NUM> may be provided in the molding compound <NUM> between the first semiconductor chip 30a, the second semiconductor chip 30b.

Preferably, the semiconductor package 3a further comprises connector <NUM> such as an antenna module connector provided on the second side 10b. Preferably, the connector <NUM> is coplanar with the first semiconductor chip 30a and the second semiconductor chip 30b. Preferably, the connector <NUM> may be electrically coupled to the first semiconductor chip 30a and the second semiconductor chip 30b through, for example, the conductive traces <NUM> in the package substrate <NUM>. Preferably, for example, the connector <NUM> may be electrically coupled to a <NUM> modem through a flex cable (not shown).

For example, the substrate <NUM> may be a ceramic substrate, a semiconductor substrate, a dielectric substrate, a glass substrate, but is not limited thereto. Preferably, the top antenna package <NUM> may be a LTCC, a FCCSP, a fan-out type chip package, a laminate-based package or a wire-bond type package, but not limited thereto.

Preferably, the top antenna package <NUM> does not include a semiconductor chip or die. The top antenna package <NUM> may further comprise a radiative antenna element <NUM> in the conductive trace <NUM> disposed on a surface of the substrate <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or mmW signals. Although not shown in this figure, it is understood that the radiative antenna element <NUM> may be disposed at a bottom surface of the substrate <NUM> depending upon the design requirements. For example, the radiative antenna element <NUM> may be may be of any suitable type, such as patch antennas, slot-coupled antenna, stacked patches, dipoles, monopoles, etc., and may have different orientations and/or polarizations. Preferably, the radiative antenna element <NUM> could route signals from one side of the substrate <NUM> to the other side of the substrate <NUM> through one or more plated through-holes <NUM> or other conductive traces disposed within the substrate <NUM>. Besides, the radiative antenna element <NUM> could comprise multiple antenna modules, for example, a dual-band antenna element and a single-band antenna element, but not limited thereto.

<FIG> is a schematic, cross-sectional diagram showing a semiconductor package 3b including a discrete antenna device mounted on a bottom chip package according to the invention, wherein like layers, regions or elements are designated by like numeral numbers. As shown in <FIG>, the first passive component <NUM> is disposed on the first side 10a and the second passive component <NUM> is disposed on the second side 10b. For example, first passive component <NUM> may be small-size capacitors having a thickness of less than <NUM> micrometers, which can be mounted on the first side 10a by surface mount techniques.

<FIG> is a schematic, cross-sectional diagram showing an exemplary semiconductor package 3c including a discrete antenna device mounted on a bottom chip package for further elaborating the context of the invention but not belonging to it, wherein like layers, regions or elements are designated by like numeral numbers. Preferably, as shown in <FIG>, the connector <NUM> may be mounted on a bottom surface 20b of the substrate <NUM>. The connector <NUM> may be electrically coupled to the bottom chip package <NUM> through the traces <NUM> on the bottom surface 20b of the substrate <NUM>. The radiative antenna element <NUM> is disposed on a top surface 210a of the substrate <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or mmW signals.

<FIG> is a schematic, cross-sectional diagram showing an exemplary semiconductor package 3d including a discrete antenna device mounted on a bottom chip package for further elaborating the context of the invention but not belonging to it, wherein like layers, regions or elements are designated by like numeral numbers. Preferably, as shown in <FIG>, the semiconductor package 3d may comprise multiple antenna packages 20a~20c mounted on the first side 10a of the bottom chip package <NUM>. The physically separated antenna packages 20a~20c may alleviate the package warpage problem. Each of the multiple antenna packages 20a~20c may comprise the radiative antenna element <NUM> on the top surface 210a of the substrate <NUM>. The radiative antenna element <NUM> may comprise an antenna array or a mechanism for radiating and/or receiving electro-magnetic signals such as RF wireless signals or mmW signals. Preferably, the separated antenna packages 20a~20c may comprises different radiative antenna elements. The radiative antenna elements <NUM> of the separated antenna packages may be various combinations of any different suitable types, for example, patch antennas and dipoles antennas, slot-coupled antenna and monopoles antennas, but not limited thereto. Besides, in some other embodiments, the radiative antenna elements <NUM> of the separated antenna packages 20a~20c may comprise multiple antenna modules, for example, a dual-band antenna element and a single-band antenna element, but not limited thereto.

Claim 1:
A semiconductor package, comprising:
a bottom chip package (<NUM>) having a first side (10a) and a second side (10b) opposing the first side (10a), the bottom chip package (<NUM>) comprising a first semiconductor chip (30a) and a second semiconductor chip (30b) arranged in a side-by-side manner on the second side (10b);
a top antenna package (<NUM>) mounted on the first side (10a) of the bottom chip package (<NUM>), wherein the top antenna package (<NUM>) comprises a radiative antenna element (<NUM>); and
a first connector (<NUM>) disposed on the second side (10b),
wherein the top antenna package (<NUM>) comprises a substrate (<NUM>),
wherein the first radiative antenna element (<NUM>) is disposed on a surface of the substrate (<NUM>),
a first passive component (<NUM>); and
a second passive component (<NUM>), wherein the first passive component (<NUM>) and the second passive component (<NUM>) comprise discrete capacitors,
wherein the first passive component (<NUM>) is disposed on the first side (10a) and the second passive component (<NUM>) is disposed on the second side (10b).