Patent Description:
In recent years, the semiconductor industry has been boosting performance of processors by increasing the number of cores in processors (i.e. multi-core processors), based on Moore's law which states that the number of transistors in integrated circuits doubles approximately every two years. Incidentally, this brings challenges to designing a power efficient on-die communication backbone, e.g. a Network-on-Chip (NoC), for delivery of data-bits between the cores and associated memories. It will be appreciated that electrical (metal-based) interconnects have traditionally dominated on-chip communications in modern processors, and insofar satisfy the communication requirements of conventional multi-core processors. However, as a number of cores increases, a power budget allocated to the corresponding multi-core processor then becomes increasingly constrained, not to mention that performance of the processor will also be severely limited due to usage of electrical interconnects, which undesirably suffer from an inherent bandwidth-distance-power trade-off.

New types of interconnects are needed to enable higher scalability for future multi-core processors. Based on literature, optical interconnects are considered to have the potential to overcome the mentioned bandwidth-distance-power trade-off of electrical interconnects. An optical/photonic interconnect generally comprises a light emitting source for generating an information carrier, a modulator for Electrical/Optical (E/O) data transformation, a photodiode for light detection, miscellaneous passive components for light guiding, and peripheral electronic devices for driving and biasing photonic devices. For an optical interconnect, the light emitting source is generally the most important device as it consumes a substantial fraction of the total link power expended. In this respect, existing solutions tend to utilize off-chip lasers as the light emitting source, which however consume a significant amount of power due to their high threshold current. Even when the optical interconnects are used sporadically, power consumption of the lasers remains largely constant because communication data is modulated externally atop of the continuous wavelengths of the lasers, thus resulting in high power consumption by the lasers regardless of an actual amount of data transmission through the optical interconnects.

<CIT> relates to a fabrication procedure of an optoelectronic (OE) system which involves wafer scale fabrication of an epitaxially grown Gallium Arsenide (GaAs) layer and a Silicon IC layer. The two layers are bonded together "face-to-face" and the OE devices fabricated from the GaAs layer thereafter. However, the layers making up the OE devices has to be epitaxially grown in reverse so that when the Silicon IC layer and GaAs layer are bonded "face-to-face", the fabricated OE devices is in the correct orientation.

<CIT> relates to a packaging type solution to forming three dimensional integrated circuit chips wherein the layers may be formed in parallel and the layers are glued together to form laminated chips. However, this method of 3D IC chip fabrication results in low interconnection densities between the circuit elements between layers which limits the complexity of the interconnections that can be made.

<CIT> relates to a semiconductor device having a piercing electrode in a semiconductor chip in order to form a three dimensional semiconductor integrated circuit device by piling films. However, the method of forming the three dimensional semiconductor integrated circuit device is tedious as it requires multiple steps of etching and filing the resulting space.

One object of the present invention is therefore to address at least one of the problems of the prior art and/or to provide a choice that is useful in the art.

According to a <NUM>st aspect of the invention, there is provided an integrated circuit in accordance with claim <NUM>.

The integrated circuit may be formed as a single processor or a portion of a processor.

Embodiments of the invention are disclosed hereinafter with reference to the accompanying drawings, in which:.

<FIG> is a flow diagram <NUM> directed at a method of forming an integrated circuit, according to an example not forming part of the claimed invention. The integrated circuit may be formed as a single processor or as a portion of a processor, but for this example, (as an example) the integrated circuit is taken to be a processor. An overview of the method is set out as follows: at step <NUM>, a Si-CMOS substrate <NUM> (e.g. a silicon-on-insulator (SOI) substrate) is CMOS processed to form at least one transistor (which is silicon-based), and at step <NUM>, a III-V substrate <NUM> is processed to form optoelectronics devices (e.g. LEDs, OLEDs, photodetectors and/or the like) thereon. Needlessly to say, the III-V substrate <NUM> is formed of any suitable III-V materials (e.g. InGaN, or GaN, but not to be construed as limiting). It is highlighted that step <NUM> is carried out using conventional CMOS processing techniques, and so an in-depth explanation is omitted for brevity sake. Also, the Si-CMOS substrate <NUM> with at least one transistor may be considered as a partially processed Si-CMOS substrate. The partially processed Si-CMOS substrate may also be termed as a partially processed Si-CMOS device layer). It is to be appreciated that at least one Si-CMOS device layer is needed. But in this case, the at least one transistor includes a plurality of transistors, which may be configured as processors with associated caches, routers, link drivers or the like. Then at step <NUM>, the processed Si-CMOS and III-V substrates <NUM>, <NUM> are bonded together, and at final step <NUM>, the transistors and optoelectronic devices respectively formed in the processed Si-CMOS and III-V substrates <NUM>, <NUM> are electrically connected. Hence, it will be appreciated that the integrated circuit is monolithically formed as set out above. Detailed description of each step <NUM>-<NUM> is now further provided below.

As mentioned, the integrated circuit is integrally formed from Si-CMOS and III-V materials. For optoelectronics devices to be made using the GaN material, it is to be appreciated that because GaN needs to be grown on a Si(<NUM>) substrate with matched lattice orientation, while Si-CMOS circuits are typically fabricated on a Si(<NUM>) substrate, bonding technology is thus required to integrate the transistors and optoelectronics devices on a single wafer. Considering that temperatures typically used for growing GaN is too high (i.e. around <NUM>) for the transistors to survive, the transistors thus need to be separately fabricated as a front-end substrate through the Si-CMOS substrate, while epitaxy of the optoelectronics devices is performed separately as well, before the processed Si-CMOS and III-V substrates are subsequently bonded together as described in step <NUM>.

<FIG> collectively depict a flow diagram <NUM> of sequential steps <NUM>, <NUM>, <NUM>, which form step <NUM> of the method of <FIG>. In step <NUM> of <FIG>, transistors <NUM> are fabricated using the Si-CMOS substrate <NUM>, which in this case is an SOI substrate (but not to be construed as limiting), and to be referred to as such hereinafter. The SOI substrate <NUM> includes (in a top down order) a top Si(<NUM>) layer 202a, a first SiO<NUM> layer 202b, and a bottom Si(<NUM>) layer 202c. For easy referencing, this is termed as the right-side up arrangement of the SOI substrate <NUM>. The transistors <NUM> are fabricated at the top Si(<NUM>) layer 202a, which upon completion is covered by a second SiO<NUM> layer <NUM>. If necessary, planarization of the second SiO<NUM> layer <NUM> is performed using Chemical Mechanical Polishing (CMP) or other suitable processes. It is to be appreciated that the SOI substrate <NUM> is still orientated in the right-side up arrangement. In step <NUM> of <FIG>, the SOI substrate <NUM> is bonded to a Si handle wafer <NUM>, which is attached adjacent and planar to the second SiO<NUM> layer <NUM>. Next, in step <NUM> of <FIG>, the bottom Si(<NUM>) layer 202c of the SOI substrate <NUM> is removed substantially, until the first SiO<NUM> layer 202b is exposed. With completion of step <NUM> depicted in <FIG>, the processed SOI substrate <NUM> is obtained. The processed SOI substrate <NUM> may be termed as a processor wafer.

Next, <FIG> collectively show a flow diagram <NUM> of sequential steps <NUM>, <NUM>, <NUM>, <NUM> forming step <NUM> of the method of <FIG>. In step <NUM> of <FIG>, optoelectronic devices <NUM> are first fabricated using the III-V substrate <NUM>, which in this case includes (in a top down order) a GaN layer 302a and a Si(<NUM>) layer. It is to be appreciated that for sake of easy explanation in this example, the GaN layer 302a is described herein as a single layer, but not to be construed as limiting since in other variant examples, the GaN layer 302a may comprise multiple GaN layers or multiple layers formed of other materials (e.g. AlGaN or InGaN), instead of GaN. That is, for ease of description, <FIG> only notionally shows where the GaN material and optoelectronic devices <NUM> reside in the III-V substrate <NUM> - it is not actually representative of actual LED layers. For easy referencing, this is termed the right-side up arrangement of the III-V substrate <NUM>. The optoelectronics devices <NUM> fabricated (at the GaN layer 302a) in this instance includes at least one GaN LED and a corresponding photodetector in opposing arrangement. So the optoelectronics devices <NUM> in this case include at least a pair of optoelectronics devices. As understood, the GaN layer 302a (being a III-V material) is different to silicon. Of course, in certain examples, a plurality of such pairs of GaN LED and corresponding photodetector may be formed depending on intended applications. A portion of the GaN layer 302a lying intermediate the GaN LED and corresponding photodetector is then removed via etching to form at least one recess to later accommodate a waveguide <NUM> for coupling the GaN LED and corresponding photodetector together. The definition of etching includes chemical etching. It is to be appreciated that the GaN LED, corresponding photodetector and the waveguide <NUM> thus constitutes an LED-based optical interconnect (i.e. an optical connection) of the integrated circuit. In step <NUM> of <FIG>, a first SiO<NUM> layer <NUM> is deposited to cover the GaN layer 302a and the at least one recess. If necessary, planarization of the first SiO<NUM> layer <NUM> is also performed using CMP.

Then as depicted in step <NUM> of <FIG>, the associated portion of the first SiO<NUM> layer <NUM> which is deposited in the at least one recess (created at step <NUM> of <FIG>) is etched again to partially expose another new recess at the same position. Next, a SiN layer <NUM> (e.g. Si<NUM>N<NUM>) to form the waveguide <NUM> is then deposited into the new recess, which also covers the first SiO<NUM> layer <NUM>. Essentially, the SiN layer <NUM> fills in the recess created at the step <NUM> of <FIG>. If necessary, planarization of the SiN layer <NUM> is performed using CMP. In step <NUM> of <FIG>, the SiN layer <NUM> is then processed using lithography and/or etching to form the waveguide <NUM>. The waveguide <NUM> is adapted to couple the optoelectronics devices <NUM> to form the LED-based optical interconnect. Thereafter, a second SiO<NUM> layer <NUM> is deposited to cover and encapsulate the SiN layer <NUM> (which includes the waveguide <NUM>), and to be followed by performing CMP planarization if required. The processed III-V substrate <NUM> (still in the right-side up arrangement) is then obtained with completion of step <NUM>. The processed III-V substrate <NUM> may be termed as a photonic wafer.

As mentioned, it is to be appreciated that the optoelectronic devices <NUM> may comprise a plurality of layers of different materials/alloys, as understood in the art. For example, in the case of GaN-based LEDs, the different layers may be binary materials such as GaN, AIN and InN, and ternary or quaternary alloys of InAlGaN. Typically, all the layers are formed in a single epitaxial process run (e.g. also at step <NUM> of <FIG>), but it is also possible to first form a GaN buffer/template (complete with required AIN and AlGaN buffer layers), and then perform selective-area regrowth to form subsequent layers so as to directly create the device mesas.

<FIG> illustrate a flow diagram <NUM> of sequential steps <NUM>, <NUM> forming step <NUM> of the method of <FIG>. In step <NUM> of <FIG>, the processed SOI substrate <NUM> (obtained in step <NUM> of <FIG>) and processed III-V substrate <NUM> (obtained in step <NUM> of <FIG>) are aligned accordingly and bonded together. It is to be appreciated that the processed SOI substrate <NUM> is bonded on top of and adjacent to the processed III-V substrate <NUM>. That is, the first SiO<NUM> layer 202b of the processed SOI substrate <NUM> is arranged planar and immediately vertically adjacent to the second SiO<NUM> layer <NUM> of the processed III-V substrate <NUM>. Also, the processed SOI substrate <NUM> and the processed III-V substrate <NUM> (when bonded) are located in disjointed planes (i.e. the transistors <NUM> and optoelectronic devices <NUM> are positioned in different respective planes). In step <NUM> of <FIG>, the Si handle wafer <NUM> of the processed SOI substrate <NUM> is removed. Specifically, the processed SOI substrate <NUM> and processed III-V substrate <NUM> are still in their respective right-side up arrangements. Moreover, it will be appreciated such monolithic integration enables orientation mismatch between the Si(<NUM>) layer 202a of the processed SOI substrate <NUM> and the Si(<NUM>) layer 302b of the processed III-V substrate <NUM> to be avoided.

<FIG> depict a flow diagram <NUM> of sequential steps <NUM>, <NUM>, <NUM>, <NUM>, which collectively form step <NUM> of the method of <FIG>. In step <NUM> of <FIG>, the bonded processed SOI substrate <NUM> and III-V substrate <NUM> (obtained from step <NUM> of <FIG>) undergoes etching/mechanical grinding so that a portion of the processed SOI substrate <NUM> is removed to form a recess. The amount of the portion of the processed SOI substrate <NUM> removed is to depends on requirements but it will be appreciated that performing step <NUM> is to enable removal of the top Si(<NUM>) layer 202a in regions where a plurality of vias <NUM> are to be formed to allow the transistors <NUM> and optoelectronics devices <NUM> to be electrically connected. That is to say, etching/mechanical grinding only needs to be carried out in regions around where the vias <NUM> are intended to be formed, and the etching/mechanical grinding is then stopped at an appropriate determined position within the first SiO<NUM> layer 202b such that both the SiN layer <NUM> and GaN layer 302a are consequently still protected by some amount of SiO<NUM>. That is, access to the LED-based optical interconnect is permitted through the recess. The purpose of forming the recess at this step <NUM> is so to facilitate subsequent electrical connection of the transistors <NUM> (of the processed SOI substrate <NUM>) to the optoelectronics devices <NUM> (of the processed III-V substrate <NUM>). In step <NUM> of <FIG>, the recess is then filled substantially with an electrically insulating material <NUM> (e.g. SiO<NUM>), and followed by CMP planarization if necessary. In step <NUM> of <FIG>, the plurality of vias <NUM> is appropriately formed in the electrically insulating material <NUM>, and the respective vias <NUM> are filled in step <NUM> of <FIG> with an electrically conducting material <NUM> (e.g. a suitable metal) to electrically connect the transistors <NUM> to the optoelectronics devices <NUM> to obtain the completed integrated circuit. If necessary, planarization of the completed integrated circuit is performed using CMP.

For this example, the method of <FIG> is described as being practised by a single entity. But not to be construed as limiting, it is also to be appreciated that for the method of <FIG>, related steps <NUM>-<NUM> may alternatively be performed separately by different entities if required, such as different CMOS foundries. For example, a first CMOS foundry may perform step <NUM>, while a different non-CMOS foundry entity may then perform step <NUM>. Subsequently, a second CMOS foundry may perform step <NUM> and then the first CMOS foundry returns to perform step <NUM>. Of course, the different sub-steps of steps <NUM>, <NUM> and <NUM> may also be assigned to yet further different CMOS foundries if desired, for example if technically possible and economically viable. Also in such a scenario, step <NUM> of <FIG> may then simply be omitted or be re-defined as receiving an already partially processed Si-CMOS substrate, rather than processing the CMOS substrate. An advantage of the above described variant operations is that prior investments made in CMOS technology by the different CMOS foundries may beneficially be leveraged to enable many of the proposed integrated circuit to be manufactured cheaply on a mass production scale. Of course, such an advantage is also shared by the present example. In other examples, step <NUM> need not be performed in CMOS foundries because CMOS foundries may alternatively prefer to receive the combined wafer obtained after completion of step <NUM>, so that the CMOS foundries may only need to carry out standard-CMOS processing in step <NUM>.

<FIG> is a first example <NUM> of the integrated circuit formed using the method of <FIG>, while <FIG> is a simplified diagram of <FIG> depicting schematics of the optoelectronic devices configured in the integrated circuit of <FIG>. For the first example <NUM>, the integrated circuit in <FIG> comprises two (first and second) processors 602a, 602b (formed from the transistors <NUM> of the processed SOI substrate <NUM>), and together with an InGaN LED <NUM> and a corresponding InGaN photodetector <NUM> (formed from the optoelectronics devices <NUM> of the processed III-V substrate <NUM>). A waveguide <NUM> (made of SiNx) couples the InGaN LED <NUM> to the InGaN photodetector <NUM>, while the first processor 602a is electrically connected to the InGaN LED <NUM> for controlling thereof. The second processor 602b is then electrically connected to the InGaN photodetector <NUM> for controlling thereof. It is to be appreciated that SiNx has been widely studied as a material for constructing optical waveguides, because SiNx may easily be integrated with silicon substrates. It is to be appreciated that in this text, SiN and SiNx are used interchangeably to refer to the same dielectric material.

Configured to operate at a wavelength of about <NUM>, the InGaN LED <NUM> and InGaN photodetector <NUM> (of the first example <NUM>) are each identically formed with the following layers (described in a top-down order): a p-GaN layer <NUM>, a p-AlGaN layer <NUM>, an InGaN MQW layer <NUM>, a first n-GaN layer <NUM>, an n-AlGaN layer <NUM>, a second n-GaN layer <NUM>, and a AlGaN buffer layer <NUM>.

Specifically, it is highlighted that dual-function operations relating to light emission and light detection are possible using just the InGaN MQW layer <NUM>, and hence explains why the InGaN LED <NUM> and InGaN photodetector <NUM> are formed similarly. For information, it is to be appreciated that while LEDs with the InGaN/GaN MQWs layers are typically used as solid-state light sources, such LEDs are however typically used only in interior house lightings and there are little literature related to optimizing such LEDs for on-chip communication purposes. It is to be appreciated that key considerations for on-chip communication are high-speed, small-form factor, and high efficiency, which are listed approximately in the order of importance.

<FIG> is a schematic diagram of another InGaN LED <NUM> that may also be formed in the proposed integrated circuit. The different layers of the InGaN LED <NUM> are formed in a similar manner as afore described in <FIG>, and hence description is not repeated for brevity sake. To briefly highlight, various layers are formed to perform specific functions, such as bandgap smoothening, current spreading, optical mode shaping and the like, as will be understood in the art. Particularly, the InGaN LED <NUM> is formed to include the following layers (in a top-down order): a p++-GaN layer <NUM>, a p-GaN layer <NUM>, a p-AlGaN layer <NUM>, five InGaN/GaN MQWs <NUM>, a first n-GaN layer <NUM>, a second n-GaN layer <NUM>, a AIN/graded AlGaN buffer layer <NUM>, and a Si(<NUM>) layer <NUM> functioning as a base substrate. The p++-GaN layer <NUM>, p-GaN layer <NUM>, p-AlGaN layer <NUM>, and five InGaN/GaN MQWs <NUM> collectively form an active light emitting area. A p-contact layer <NUM> is formed adjacent to the p++-GaN layer <NUM>, while two n-contact layers 720a, 720b are formed adjacent to the second n-GaN layer <NUM> to facilitate control of the InGaN LED <NUM>. An (outermost) edge-to-edge distance between the two n-contact layers 720a, 720b is defined as the n-mesa <NUM>. It is to be appreciated that all the layers <NUM>-<NUM> as depicted in <FIG> are deposited via epitaxy, after which device fabrication of the InGaN LED <NUM> then commences. <FIG> is a table <NUM> listing relevant parameters of the respective layers of an epitaxial growth layer structure of a InGaN/GaN photo-detector <NUM> of <FIG>, which is to be elaborated below later. It is to be appreciated that the InGaN LED <NUM>, which is configured with micro-dimensions, may find applications in high-speed communications due to micro-size effects of the InGaN LED <NUM>, as well as enable more efficient usage of injected current.

For <FIG>, it is highlighted that a single contiguous n-contact which may also be arranged to surround all four-sides of the p-mesa (i.e. collectively the p-GaN layer <NUM>, p-AlGaN layer <NUM>, InGaN MQW layer <NUM>, and first n-GaN layer <NUM>), but for this present embodiment, the n-contact formed is restricted to only three sides in order to free up space for forming the waveguide <NUM>. But for other envisaged embodiments, the waveguide <NUM> may be arranged to extend in both directions, i.e. to the left side of the InGaN LED <NUM>, and in that case the n-contact will be limited to at most two sides of the p-mesa. So <FIG> and <FIG> as presented may be viewed as being two different orthogonal cuts of a device with the n-contact arranged to surround three sides of the p-mesa.

Further, it is to be appreciated that the definition of "micro-size effects" in this case refers to differences in behaviour between very small and large devices, most specifically relating to speed, and L-I-V (i.e. Light output power-current-voltage) behaviour. On the other hand, the definition of "injected current" refers to the current used to drive the device - essentially, for a given injected current, more light is generated for a smaller device on a proportional basis, when compared with larger devices, hence the difference in the L-I-V behaviour.

Based on the method <NUM> of <FIG>, <FIG> respectively show a mask layout <NUM> adapted for manufacturing the InGaN LED <NUM> of <FIG>, and a PDK design <NUM> for the InGaN LED <NUM> of <FIG> and an associated transistor (which is configured as a Si-driver in this case) to drive the InGaN LED <NUM>. It is to be appreciated that for targeting the <NUM> technology node layout design rules (used for the mask layout <NUM>) to permit DRC and LVS check similar to for conventional electrical VLSI design are adopted. It is to be appreciated that in the case of an optical interconnect comprising of an LED, a waveguide and a photodetector, there is no transistor and therefore no "gate" is present. However, the "<NUM> technology node" definition still applies in the sense that a smallest feature (e.g. the width of the LED, waveguide and/or photodetector) may be <NUM> µm based on the proposed method. Because the same fabrication tools and design rules are used for making any related RF circuits, the smallest feature size in the said RF circuits (e.g. the gate lengths) is also limited to <NUM>.

Accordingly, <FIG> is a table <NUM> listing various example design parameters for components of the InGaN LED <NUM>, particularly showing a minimum size of each component of the InGaN LED <NUM> and a minimum spacing between the said components. With reference to <FIG>, the components of the InGaN LED <NUM> include a bondpad (which is a landing pad to facilitate external electrical probing of the InGaN LED <NUM>), the p-contact <NUM>, the n-contact 720a, 720b, at least one multi-quantum-well (i.e. the InGaN/GaN MQWs <NUM>), and a mesa (i.e. device-to-device separation). It is also to be appreciated that data for the layout design rules are obtained from consideration of required device requirements, material system and process constraints of the method of <FIG>. The definition of "material system" herein may include choice of materials to use for forming a LED/photodetector, and materials to use for forming an associated waveguide. This affects (or is conversely driven by) a desired light wavelength to be deployed for (or by) the LED/photodetector of interest. To further clarify, a "material system" choice may also mean selecting, for example, between InGaN/GaN (if light of a wavelength of <NUM> is to be used), or InGaAs/GaAs (if light of a wavelength of <NUM> is to be used) to be used for forming the LED/photodetector.

<FIG> is a second example <NUM> of the integrated circuit formed using the method of <FIG>, while <FIG> shows a diagram <NUM> of optical field transmission and coupling loss performance of the second example <NUM> of <FIG>. For the second example <NUM>, the integrated circuit is formed to comprise an InGaN/GaN LED <NUM> and the InGaN/GaN photo-detector <NUM>, which are coupled together by a waveguide <NUM>. The InGaN/GaN LED <NUM> and InGaN/GaN photo-detector <NUM> are formed on top of a Si substrate <NUM>, as will be understood by now. Specifically, the InGaN/GaN LED <NUM> includes (in a top down order) a p-GaN layer 1102a, an InGaN MQW layer 1102b, an n-GaN layer 1102c, and an AlGaN layer 1102d. The InGaN/GaN photo-detector <NUM> includes (in a top down order) a first n-GaN layer 1104a, a InGaN layer 1104b, a first p-GaN layer 1104c, a GaN spacer layer 1104d, a second p-GaN layer 1104e, an InGaN MQW layer 1104f, a second n-GaN layer <NUM> and an AlGaN layer <NUM>. The different layers of the InGaN/GaN LED <NUM> and InGaN/GaN photo-detector <NUM> are formed in a similar manner as afore described in <FIG>, and hence not repeated.

Compared to <FIG>, where the InGaN LED <NUM> and InGaN photodetector <NUM> are each identically formed, the InGaN/GaN LED <NUM> and InGaN/GaN photo-detector <NUM> of the second example <NUM> formed with slightly different structures, although sharing common layers at the bottom of the device stack. Specifically, the common layers are that the p-GaN layer 1102a, InGaN MQW layer 1102b, n-GaN layer 1102c, and AlGaN layer 1102d (all of the InGaN/GaN LED <NUM>) respectively correspond to the second p-GaN layer 1104e, InGaN MQW layer 1104f, second n-GaN layer <NUM> and AlGaN layer <NUM> (all of the InGaN/GaN photo-detector <NUM>). It is to be appreciated that forming the InGaN/GaN LED <NUM> and InGaN/GaN photo-detector <NUM> with different structures have certain benefits and drawbacks. For example, with respect to the InGaN/GaN photo-detector <NUM>, a benefit with arranging the InGaN layer 1104b to be on top of (and separated by a few layers 1104c-1104e from) the InGaN MQW layer 1104f results in better absorption at the LED MQW emitting wavelengths, but a drawback is that the growth process and fabrication process however becomes more complicated. In other embodiments, with selective-area regrowth as mentioned above, it is also possible to selectively grow one or both sides (of the LED and/or photodetector) so that each optoelectronic device may be formed with a different structure.

Separately and consistently with the claimed device, SiNx is adopted as a material used to form the waveguide <NUM> to facilitate transmission of light of visible wavelength emitted by the InGaN/GaN LED <NUM>. The waveguide <NUM> is integrated with the InGaN/GaN LED <NUM> and InGaN/GaN photo-detector <NUM> using the Damascene process. For operating the InGaN/GaN LED <NUM> using a light wavelength of about <NUM> to <NUM>, typical propagation loss of the waveguide <NUM> is lower than 1dB/cm.

Consistently with the claimed device, SiON is utilized as an optical isolation layer <NUM> arranged intermediate the waveguide <NUM> and the Si substrate <NUM>. The tunable refractive index of SiON also provides a flexible design dimension. Simulations show that if the waveguide <NUM> is configured with a length of <NUM> and a core size of <NUM> (with SiON n = <NUM> and SiO2 used as upper cladding), it only supports fundamental TE and TM modes with high confinement factors (i.e. greater than <NUM>%). Coupling loss performance between the InGaN/GaN LED <NUM>, waveguide <NUM>, and InGaN/GaN photo-detector <NUM> is evaluated to be less than 1dB. With reference to <FIG>, after the emitted light enters the InGaN/GaN photo-detector <NUM>, the light first propagates a small distance in the underneath light-emitting layer (i.e. the InGaN MQW layer 1104f) and then couples into the upper photo-detector layer (i.e. the InGaN layer 1104b). It is to be appreciated that the Indium composition shift in the upper photo-detector layer (i.e. the InGaN layer 1104b) and light-emitting layer (i.e. the InGaN MQW layer 1104f) also enhances the light detection efficiency. In this respect, initial evaluation indicates a responsivity of about between <NUM> to <NUM> A/W is achievable at a light wavelength of about <NUM>.

The remaining configurations will be described hereinafter. For the sake of brevity, description of like elements, functionalities and operations that are common between the different configurations are not repeated; reference will instead be made to similar parts of the relevant configuration(s).

It is to be appreciated that conventional designs of photonic Network-on-Chips (NoCs) typically use lasers as light emitting sources and microring resonators as modulators, detectors and routers. Particularly, the conventional photonic NoCs are configured to leverage multiple wavelengths with associated filters, and also arranged with NoC architectures such as buses and token rings which enable one-to-many connections. But unlike the conventional designs, since LED (used in the proposed integrated circuit) is an incoherent light source, and that LED-based circuits are unable to use resonant devices, NoC architectures that allow multiplexing of multiple flows atop of one-to-one connection at ultra-low power are instead adopted in order to fit deployment of the proposed integrated circuit. For example, an NoC with mesh-topology commonly used in modern many-core processors is adoptable to replace one-to-one electrical metal-based interconnects (that link neighbouring cores) with respective LED-based optical interconnects as provided in step <NUM> of the proposed method of <FIG>. Furthermore, it is to be appreciated that conventional electrical routers at each core of the processor are able to readily handle arbitration of multiple flows onto the one-to-one links. But this however leads to a high electrical energy overhead, with the Optical-Electrical-Optical conversion and electrical buffering/switching at each en-routing electrical router, which undesirably reduce benefits of using the LED-based optical interconnects of the proposed integrated circuit for long distance cross-die communications.

In this further embodiment, a variant based on the NoC architecture known as Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) <NUM> as depicted in <FIG>,, which was originally proposed in literature for electrical clock-less repeated links to realize a single-cycle data path across the entire die (i.e. entirely from the source to destination), is adopted. As a background, the SMART micro-architecture <NUM> allows messages to dynamically arbitrate and create multi-hop bypass links across the chip on-demand over a shared network fabric. Messages are only buffered at intermediate routers upon contention. By bypassing intermediate electrical routers, a message is allowed to transverse from source to destination electrical routers, avoiding high-energy overheads of intermediate electrical routers in most cases. Originally proposed as a solution to break the latency barrier for NoCs, the SMART micro-architecture <NUM> however still consumes <NUM>-<NUM> fJ/bit/mm, leading to worst case transmission energy of <NUM> fJ to transmit a bit from one chip edge to another chip edge on a typical <NUM> by <NUM> dimensioned chip.

Accordingly, potential of adopting the proposed LED-based optical interconnects (as provided through step <NUM> of the method of <FIG>) into the SMART micro-architecture <NUM> to further break the power barrier of on-chip communications is envisaged in this embodiment. In this respect, <FIG> shows a variant SMART micro-architecture <NUM> (based upon the SMART micro-architecture <NUM>), in which the bypass links of the SMART micro-architecture <NUM> are now replaced with the said LED-based optical interconnects (as enabled by the method of <FIG>). This SMART micro-architecture <NUM> beneficially allows distance-independent low-power transmission of photonics to be leveraged. Besides, the method of <FIG> also advantageously enables the LED-based optical interconnects to be closely integrated with the Si-CMOS routers and processors.

For comparison, energy efficiencies of the proposed LED-based optical interconnect against a baseline electronic clock-less repeated interconnect in a <NUM> node, and a laser-enabled optical interconnect are then evaluated (i.e. all modelled at an operating frequency of <NUM>) using DSENT (i.e. a timing-driven NoC power-modeling software), and the corresponding performance results are shown in a graph <NUM> in <FIG>. Specifically, the laser-enabled optical interconnect is modelled to constitute an off-chip laser, a microring modulator, receivers and peripheral electrical devices. An electrical LED model is used to estimate the Si-driver size in DSENT. Particularly, the effective capacitance of the LED (i.e. about <NUM> fF) and parasitic capacitance of the vias (i.e. about <NUM> fF) are used to size the Si-driver and its associated power consumption. In addition, waveguide loss is set to be <NUM> dB/cm and responsivity for the photodetector is set to <NUM> A/W for a Ge detector, or <NUM> A/W for an InGaN detector. Within short distances relating to a length of the associated interconnect (i.e. less than <NUM>), most operating powers are consumed by the electrical driving and leakage in the optical interconnect. Therefore, it is shown in <FIG> that energy consumption for the electronic interconnect increases linearly while the LED-based optical interconnect/laser-enabled optical interconnect remains almost constant regardless of transmitting distance. It will clearly be seen from <FIG> that with a power efficiency of <NUM> fJ/b, the proposed LED-based optical interconnect thus easily outperforms the electronic interconnect/laser-enabled optical interconnect.

<FIG> is a graph <NUM> comparing normalized dynamic network energy performance between the SMART micro-architecture <NUM> and variant SMART micro-architecture <NUM> using SPLASH-<NUM> applications on a <NUM>-core processor. Specifically, parallel sections of all <NUM>-threaded SPLASH-<NUM> applications are executed on an <NUM>×<NUM> multicore processor with shared L2 cache, and the multiple applications' results are then averaged. Two electrical NoC baselines are used: a state-of-the-art NoC with a single-cycle-pipeline router and a NoC based on the SMART micro-architecture <NUM>. All results are normalized against the single-cycle router. It is to be appreciated that both electrical NoC baselines are highly optimized, outperforming recent industry chip prototypes such as the Intel <NUM>-core SCC with a <NUM>-cycle router in latency and energy. Performance-wise, the SMART micro-architecture <NUM> delivers five-to-eight times lower latency than the single-cycle router electrical baseline, whereas the variant SMART micro-architecture <NUM> is able to maintain the performance advantages as depicted in <FIG>. The SMART micro-architecture <NUM> has a slight energy advantage over the baseline single-cycle router due to savings in buffering at intermediate routers, while the variant SMART micro-architecture <NUM> substantially reduces link and crossbar dynamic energy consumption by a substantial <NUM>% and <NUM>% respectively, therefore leading to overall energy savings of about <NUM>% over the SMART micro-architecture <NUM>, across all applications.

In summary, with increasing market demand for power efficient on-die communication that scales with upcoming multicore processors, the proposed method of <FIG> enables an integrated circuit with LED-based optical interconnects that meet the objective. Particularly the proposed method uses a monolithic integrated process for bonding an III-V substrate and a silicon substrate, which beneficially is directly compatible with conventional CMOS processing. This thus requires no costly and complex reconfiguration of existing CMOS manufacturing techniques, and will enable easy integration with the CMOS manufacturing techniques to facilitate mass production. For the proposed method, an on-wafer integration technique is specifically devised whereby the transistors <NUM> are CMOS manufactured and the optoelectronic devices <NUM> are formed as III-V semiconductors. So using the proposed method of <FIG>, LED-based optical interconnects are formable, in which each LED-based optical interconnect includes at least a directly modulated, high speed LED (which may be formed using III-nitride), and a corresponding photodetector, which are collectively coupled by an intermediate waveguide. For information sake, it is to be appreciated that LEDs formed using nitride-based materials (being of the III-V family of materials) are more reliable and practical than being formed using other III-V materials. It is to be appreciated that multicore processors (with on-chip networks that link the different cores) may thus be enabled with the proposed LED-based optical interconnects for the on-chip networks to have substantially lower energy consumption, higher bandwidth density, smaller area footprint, and improved performance than conventional electrical-interconnects based designs. In addition, while heating effects may be more prominent for the LED-based optical interconnects since efficient heat dissipation is more challenging in the small-sized LEDs, this heating issue may however be easily addressed via improved packaging of the optoelectronic devices <NUM>.

Broadly, the integrated circuit includes at least one transistor <NUM> arranged in a partially processed CMOS substrate; and at least a pair of optoelectronic devices <NUM> adapted to be coupled by a waveguide, which are collectively arranged on a semiconductor substrate. The semiconductor substrate is arranged adjacent to the partially processed CMOS substrate. The optoelectronic devices are also electrically connected to the transistor, and the optoelectronic devices are formed from a wafer material different to silicon.

Additionally, the proposed method of <FIG> is beneficially able to address the following problems faced by conventional solutions.

It is challenging to realize a wide variety of photonic devices, including high speed LEDs and detectors, and visible light transparent waveguides within a converged process platform. Silicon is typically considered as a future platform of choice for building optoelectronic devices, being able to accommodate both Si-CMOS transistors as well as integrated photonics. However, since silicon has an indirect bandgap that undesirably provides weak interaction between mobile charge carriers and photons, there is thus a hurdle to fabricate active photonic devices (e.g. LEDs) using silicon.

As III-V materials are particularly suitable for manufacturing optoelectronic devices, the proposed method of <FIG> is devised to enable on-chip LED-based optical interconnects as described in step <NUM> of <FIG>, whereby electrical transistors are formed via CMOS processing while the optoelectronic devices are formed from III-V materials (i.e. see <FIG>).

Conventional solutions for enabling on-chip optical interconnects tend to rely on utilising off-chip lasers as the light emitting sources, but there are disadvantages with such an approach. Firstly, lasers consume a significant amount of power due to their high threshold current; even when the connections are used sporadically, power consumption of the lasers remains constant as communication data is modulated externally atop of the continuous wavelengths, resulting in high laser power consumption regardless of actual data transmission through the optical interconnects. Secondly, external modulators require drivers with several amplification stages that consume large amount of driving power especially for high data rate modulation with stringent driving requirements. Furthermore, the insertion loss (which is typically greater than <NUM> dB) of a modulator worsens the optical power budget, thus requiring even greater output power from the lasers.

With the proposed method, an alternative light emitting source for on-chip optical interconnects is envisaged: directly modulated LEDs. Firstly, LED functions as a reliable light emitting source that switches on without a threshold current. Particularly, when an operation voltage of a LED is above a minimum threshold value termed as the turn-on-voltage (ToV), the current flow and light output consequently increase exponentially with voltage. Below the ToV value, the LED is switched off and negligible current conducts through the LED, thus consuming and dissipating minimal power. Secondly, substantial power consumption savings may also be achieved by using LEDs in the on-chip optical interconnects since external modulators are no longer needed.

InGaN/GaN MQWs LED structures are generally used as a solid-state light source. However, LEDs with afore said structures are normally designed for use in interior house lightings. For on-chip communications, it is typically desirable to have as high a modulation bandwidth as possible. But it is to be appreciated that LEDs configured with relatively lower modulation bandwidth, even if lower than <NUM> Gb/s, are still highly useful for on-chip communications. As a comparison, modern telecommunications lasers typically have bandwidths greater than <NUM> Gb/s.

Bandwidth limitation is fundamentally determined by the spontaneous radiative recombination lifetime of injected electrons or holes, presumably in the nanosecond range. However, recent successes (documented in literature) of driving LEDs to high frequencies have been achieved either by increasing the active layer concentration of electrons and holes, or by improving the bimolecular recombination. Accordingly based on the proposed method of <FIG>, integrated InGaN MQW micro-size LEDs for on-chip communication is realisable and feasible. For example, the frequency response of a <NUM> by <NUM> LED, evaluated through simulations, is determined to achieve more than <NUM>. Also, the higher <NUM>-dB bandwidth for an LED with reduced size may be explained by the enhanced radiative recombination rate in smaller LEDs, which is in good agreement with experimental measurements made for an individual microdisk blue LED with diameter of <NUM> (based on literature).

There is a problem of how to easily and cheaply integrate (silicon-based) transistors and optoelectronic devices together with existing known solutions.

Using the proposed method of <FIG>, the InGaN/GaN photodetector and InGaN/GaN LED may be manufactured via a single epitaxial growth process to enable light detection and emission for the LED-based optical interconnect. Efficient light coupling between the light-emitting and absorption layers (e.g. see the InGaN layer 1104b and InGaN MQW layer 1104f respectively of <FIG>) ensures highly-efficient detection with low loss in the underlying light-emitting layer (e.g. the InGaN MQW layer 1104f of <FIG>). The absorption layer is another term for the photo-detector layer. Through performance simulations, it has been determined that the InGaN/GaN photodetector integrated with a waveguide (e.g. made of SiNx) has a higher responsivity than a normal-incidence detector because the light propagation distance in the absorption layer (e.g. the InGaN layer 1104b of <FIG>) is much longer. The high responsivity indicates that lesser light power is required to enable signal receipt and therefore is able to reduce the system's power-budget. The low-loss waveguide (i.e. with a loss of less than 1dB/cm operating under light wavelengths of <NUM> to <NUM>), and low coupling loss (i.e. less than 1dB) between active and passive devices are important to guarantee the low-power operation of the optical interconnect (as enabled using our proposed method).

It is well-established that the power consumed by electrical interconnects relates to capacitance of the electrical interconnects, supply voltage and clock frequency. Since the capacitance increases with length of the interconnect and configured clock frequency (which affects the bandwidth of the interconnect), the power consumption of an electrical interconnect grows with distance and bandwidth. Moreover, in order to improve the interconnect latency, long wires are routinely segmented into smaller sections, with repeaters incorporated in between, increasing total wire coupling capacitance and thus the power consumption of the interconnect. Even with aggressive designing, an electrical interconnect generally still consumes about <NUM>-<NUM> fJ/bit/mm, leading to a worst case transmission energy of <NUM> fJ to transmit a data-bit from one chip edge to another chip edge on a typical <NUM> by <NUM> dimensioned chip.

Using the proposed method of <FIG>, LED-enabled optical interconnects are integrated with the CMOS transistors (which are electrically based) to improve the power efficiency of on-chip communications. Specifically, the proposed method enables the LED-enabled optical interconnects to be closely integrated with the CMOS transistors. As depicted in <FIG> and <FIG>, the CMOS transistors are fabricated on the Si-CMOS substrate <NUM>, while the optoelectronics devices and waveguides are processed on the III-V substrate <NUM>. Also, as discussed, <FIG> shows the variant SMART micro-architecture <NUM>, which is adapted to utilise the LED-based optical interconnects (as enabled by the proposed method). Specifically, the bypass links are replaced with the optical interconnects comprising LEDs, waveguides and couplers to beneficially leverage upon the distance-independent low-power transmission characteristics provided by photonics data communication.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary, and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed invention.

Claim 1:
An integrated circuit comprising:
transistors (<NUM>) arranged in a Si CMOS device layer (202a); and
a photonic wafer (<NUM>) bonded to the Si CMOS device layer (202a) via a first SiO<NUM> layer (202b), the photonic wafer (<NUM>) comprising at least an InGaN/GaN photodetector (<NUM>) and an InGaN/GaN light emitting diode (<NUM>) formed on a Si (<NUM>) substrate (<NUM>), the InGaN/GaN photodetector (<NUM>) and the InGaN/GaN light emitting diode (<NUM>) coupled by a waveguide (<NUM>) to define an optical interconnect, the optical interconnect is arranged below the Si CMOS device layer (202a);
wherein the waveguide (<NUM>) is made of SiNx and facilitates transmission of light of visible wavelength emitted by the InGaN/GaN light emitting diode (<NUM>) to the InGaN/GaN photodetector (<NUM>), the waveguide (<NUM>) is formed between a SiON layer (<NUM>) and a second SiO<NUM> layer (<NUM>) formed to cover the waveguide (<NUM>), and the SiON layer (<NUM>) is arranged intermediate the waveguide (<NUM>) and the Si (<NUM>) substrate (<NUM>); and
wherein the InGaN/GaN photodetector (<NUM>) and the InGaN/GaN light emitting diode (<NUM>) are electrically connected to the transistors (<NUM>) by electrical connections (<NUM>), the electrical connections (<NUM>) extending through an electrically insulating material (<NUM>) in a recess formed in the Si CMOS device layer (202a) and in the first SiO<NUM> layer (202b) and through the second SiO<NUM> layer (<NUM>) via a plurality of vias (<NUM>) to electrically connect the transistors (<NUM>) to the InGaN/GaN photodetector (<NUM>) and the InGaN/GaN light emitting diode (<NUM>).