Patent Description:
Storage systems may be implemented in electronic systems, such as computers, cell phones, hand-held electronic devices, etc. Some storage systems, such as solid state drives (SSDs), embedded Multi-Media Controller (eMMC) devices, Universal Flash Storage (UFS) devices, and the like may include non-volatile storage memories for storing user data from a host. Non-volatile storage memories provide persistent data by retaining stored data when not powered and may include NAND flash memory, phase change memory (PCM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among other types of memory that can be written to a particular number of times throughout their lifetime.

Non-volatile memory cells can be programmed to a desired state. As an example, some memory cells can be programmed to one of multiple states that can correspond to (e.g., be encoded with) different bit patterns. The particular programmed state of a cell can be determined by, for example, comparing the threshold voltage of the cell to a reference voltage In some examples, a threshold voltage (Vt) of a cell can drift, which can make accurate sensing (e.g., reading) difficult since the drift may need to be tracked in order to ensure use of proper demarcation/read voltages.

Patent document <CIT> forms part of the relevant background art and discloses a phase change memory device with memory cells formed by a phase change memory element and a selection switch.

Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

Embodiments of the present disclosure provide a technical advantage over prior approaches by overcoming the problems associated with threshold voltage drift that may occur as some memory cells, such as resistance variable memory cells, age and/or change temperature. For example, during a sensing operation, such as a read operation, the sensing voltage may be applied across a memory cell to determine the state of the memory cell, corresponding to the threshold voltage of the memory cell. However, as the number of times the memory cell is overwritten with new data increases (e.g., as the memory cell ages) and/or the temperature of the memory cell changes, the threshold voltage corresponding to the state of the cell may change, making it difficult to accurately determine the state of the memory cell using the sensing voltage.

However, embodiments of the present disclosure avoid the need to use a sensing voltage, and thus overcome the problems associated with drift. For example, one memory cell of a group of memory cells may be programmed to a particular state such that the memory cell experiences a switching event (e.g., in response to a ramp voltage) before additional memory cells in the group. The states of the additional memory cells in the group may then be determined based on whether they experience a switching event in response to the ramp voltage within a particular time of when the one memory cell programmed to the particular state experiences a switching event. This allows the states of the remaining memory cells to be determined relative the particular state of the one memory cell, thus allowing the sensing to effectively follow the drift of the particular state, thereby overcoming the problems associated with the drift.

<FIG> is a block diagram of an apparatus in the form of a computing system <NUM>, in accordance with a number of embodiments of the present disclosure. Computing system <NUM> includes a memory system <NUM> that can be, for example, a storage system such as an SSD, a UFS device, an embedded eMMC device, etc. However, embodiments are not limited to a particular type of memory system. For example, memory system <NUM> could serve as main memory for system <NUM>.

As shown in <FIG>, the system <NUM> can include a controller <NUM> coupled to a memory <NUM> and host <NUM>. Host <NUM> can be, for example, a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile device (e.g., cellular phone), network server, Internet of Things (IoT) enabled device, or a memory card reader, among various other types of hosts. For instance, host <NUM> can include one or more processors capable of accessing memory <NUM> (e.g., via controller <NUM>) over an interface, which can include a bus. The interface may be a standardized interface, such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe), or a universal serial bus (USB), among various others.

Memory <NUM> can comprise a number of memory devices (e.g., memory dies, chips, etc.), which each can comprise a number of arrays <NUM>. The arrays <NUM> can include two-dimensional (2D) and/or three-dimensional (3D) array structures, such as cross point array structures. The memory cells can include, for example, various types of resistance variable (e.g., PCRAM cells, RRAM cells, 3D cross point cells), which may comprise a resistance variable storage element and/or switch element. In a number of embodiments, the memory cells can be self-selecting memory (SSM) cells in which a single material can serve as both the storage element and the memory element.

As an example, the memory cells can be phase change memory (PCM) cells, which can be chalcogenide based memory cells comprising a single chalcogenide material serving as both a storage element and a switch element for the cells and/or a stack of materials with a first chalcogenide material serving as a switch element and a second chalcogenide serving as a storage element for the cells. However, embodiments are not limited to a particular array architecture and/or memory cell type. For instance, the array <NUM> might comprise NAND flash memory cells and/or NOR flash memory cells, among others.

The memory device <NUM> includes a read component <NUM> that can comprise various circuitry associated with operating memory cells in accordance with embodiments of the present disclosure. For example, as described further below, the read component can include sense amplifiers.

The controller <NUM> can comprise, for example, a state machine, a sequencer, and or some other type of control circuitry, and can communicate with the memory devices <NUM> to control data read, write, and erase operations, among other operations. The controller <NUM> can include, for example, a number of components in the form of hardware (e.g., one or more integrated circuits) and/or software (e.g., instructions, which may be in the form of firmware) for controlling access to the number of memory devices <NUM> and/or for facilitating data transfer between the host <NUM> and memory devices <NUM>. In general, the controller <NUM> can receive and execute commands from the host <NUM> to achieve the desired access to the memory <NUM>. The controller <NUM> can be responsible for, among other things, performing various methods for improved memory operations in accordance with embodiments described herein.

Controller <NUM> can include an encoder/decoder <NUM> that can be used to map between stored data patterns and code patterns, as described further herein. In some examples, a group of memory cells can store data according to an encoding function implemented by encoder/decoder <NUM>. For example, the encoding function can be constrained such that each code pattern corresponding to a data pattern stored by a group of cells includes at least one data unit having particular data value.

Controller <NUM> is configured to perform the methods disclosed herein, such as reading, in accordance with a number of embodiments. For example, a memory cell of a group of memory cells may programmed to have a particular state, such as the lowest state to which the memory cells can be programmed. For a group of two memory cells, for example, controller <NUM> may determine a state of the remaining memory cell based on whether the remaining memory cell experiences a switching event within a particular time after the memory cell at the particular state experiences a switching event. For example, if the remaining memory cell experiences a switching event within the particular time after the memory cell programmed to the particular state experiences a switching event, controller <NUM> may determine that the two memory cells have the same state. Otherwise, controller <NUM> may determine that the two memory cells have different states. For example, the switching event can involve switching from a non-conductive state of the memory cell to a conductive state of the memory cell.

<FIG> illustrates an example of Vt distributions corresponding to states to which memory cells can be programmed, in accordance with a number of embodiments of the present disclosure. Vt distributions <NUM>-<NUM> and <NUM>-<NUM> respectively correspond to a low state (e.g., Vt level) L and a higher state H. A memory cell having a state L can be encoded with code bit of <NUM> (e.g., a logical level <NUM>), and a memory cell having a state H can be encoded with a code bit of <NUM> (e.g., logical level <NUM>). For example, the H state may be referred to as state <NUM>, and the L state may be referred to as state <NUM>.

The states <NUM> and <NUM> may respectively correspond to different resistance levels to which the respective corresponding memory cells are programmed. In some examples, the width W of Vt distribution <NUM>-<NUM> in volts (e.g., the range of Vts corresponding Vt distribution <NUM>-<NUM>) is less than the margin M in volts (e.g., the range of Vts) between Vt distribution <NUM>-<NUM> and Vt distribution <NUM>-<NUM>.

<FIG> shows an example of a portion of memory array <NUM> that may be read using the methods disclosed herein, in accordance with a number of embodiments of the present disclosure. Memory array <NUM> can be a portion of memory array <NUM>, in some examples. Memory array <NUM> includes memory cells <NUM>-<NUM> to <NUM>-N, such as cross-point memory cells, located at intersections of a signal line <NUM>, such as a word line, and signal lines <NUM>-<NUM> to <NUM>-N, such as bit lines. For instance, memory cells <NUM>-<NUM> to <NUM>-N are respectively coupled to signal lines <NUM>-<NUM> to <NUM>-N and are commonly coupled to signal line <NUM>. Signal lines <NUM>-<NUM> to <NUM>-N, and thus memory cells <NUM>-<NUM> to <NUM>-N, can be coupled to a read component <NUM> that can be included in read component <NUM>, for example. Read component <NUM> can include sense amplifiers <NUM>-<NUM> to <NUM>-N that are respectively coupled to signal lines <NUM>-<NUM> to <NUM>-N, and thus to memory cells <NUM>-<NUM> to <NUM>-N.

Sense amplifiers <NUM>-<NUM> to <NUM>-N may respectively output voltages respectively indicative of memory cells <NUM>-<NUM> to <NUM>-N undergoing switching events, such as thresholding events (e.g., snapback events), in response to voltages being applied across memory cells <NUM>-<NUM> to <NUM>-N being greater than or equal to threshold voltages (Vts) of memory cells <NUM>-<NUM> to <NUM>-N. For example, the memory cells may switch from one conductivity state, such as a low conductivity state (e.g., high resistive state), to another conductivity state, such as a high conductivity state (e.g. a low resistive state). A sense amplifier may sense the switching event by sensing a change in current through the memory cell that may be reflected in the output voltage of the sense amplifier.

In some examples, a timewise increasing ramp voltage can be applied to signal line <NUM> while concurrently applying a voltage (e.g., the same voltage) to signal lines <NUM>-<NUM> to <NUM>-N so that a timewise increasing ramp voltage is applied across (e.g., to) memory cells <NUM>-<NUM> to <NUM>-N concurrently. Sense amplifiers <NUM>-<NUM> to <NUM>-N can sense respective switching events of memory cells <NUM>-<NUM> to <NUM>-N in response to applying the ramp voltage across memory cells <NUM>-<NUM> to <NUM>-N.

Memory cells <NUM> are resistance variable memory cells whose respective states (e.g., stored data values) depend on the respective programmed resistances of memory cells. Memory cells <NUM> can be overwritten individually without first being erased, in some examples.

In some examples, a first group of two memory cells, such as memory cells <NUM>-<NUM> (A) and <NUM>-<NUM> (B), may be programmed to a collective state by respectively programming memory cells <NUM>-<NUM> (A) and <NUM>-<NUM> (B) to one of the states <NUM> and <NUM>. Similarly, a second group of two memory cells, such as memory cells <NUM>-<NUM> (C) and <NUM>-<NUM> (D), may be programmed to a collective state by respectively programming memory cells <NUM>-<NUM> (C) and <NUM>-<NUM> (D) to one of the states <NUM> and <NUM>. In other examples, other groups having other numbers of cells, such as three cells, four cells, up to N cells, are envisioned. Hereinafter, memory cells <NUM>-<NUM> (A), <NUM>-<NUM> (B), <NUM>-<NUM> (C), and <NUM>-<NUM> (D) will be respectively referred to as memory cells A, B, C, and D.

<FIG> is a graphical illustration in which two memory cells of a group of memory cells are determined to have the same state, in accordance with a number of embodiments of the present disclosure. <FIG> is a graphical illustration in which two memory cells of a group of memory cells are determined to have different states, in accordance with a number of embodiments of the present disclosure. For example, <FIG> correspond to (e.g., illustrate what occurs during) a read operation performed by controller <NUM>. <FIG> illustrate determining a state of a memory cell, such as memory cell B, based on whether that memory cell experiences a switching event (e.g., switches) within a particular time (e.g., that may be referred to as a threshold delay time) of when (e.g. after) another memory cell, such as memory cell A, experiences a switching event.

As shown in the examples of <FIG>, a timewise increasing ramp voltage <NUM> is applied across memory cells A and B concurrently. For example, a timewise increasing ramp voltage may be applied to access line <NUM> in <FIG> while the same fixed voltage is applied to access lines <NUM>-<NUM> and <NUM>-<NUM> in <FIG> concurrently, resulting in ramp voltage <NUM>.

The Vt distributions corresponding to states <NUM> and <NUM> are superimposed on the voltage V axis in <FIG>. A starting voltage of ramp voltage <NUM> is less than the Vts of the Vt distributions corresponding to state <NUM>, corresponding to the lowest state to which the memory cells can be programmed.

Note that the examples of <FIG> involve determining a collective state of a group of two memory cells (e.g., memory cells A and B) by determining the individual state of each of the two memory cells, but may be applied to groups having any number of memory cells. In some examples, at least one memory cell of a group, such as memory cell A in this example, is to be programmed to a particular state, such as the state <NUM>, and the states of the other memory cells in the group, such as the state memory cell B in this example, are to be determined relative to the particular state. In some examples, the memory cell programmed to the state <NUM> may be referred to as set memory cell and may be the first memory cell in the group to experience a switching event in response to ramp voltage <NUM>. For example, the set memory cell acts as a reference memory cell and requires that each collective state a group of memory cells can have a memory cell with the state <NUM>. For example, the respective states of the memory cells can be determined without utilizing a separate reference voltage to which the respective threshold voltages are compared. The group including memory cells A and B stores data according to an encoding function constrained such that a corresponding code pattern includes at least one data unit having a data value <NUM>, corresponding to state <NUM>.

In <FIG>, memory cell A is the first memory cell to switch as indicated by step <NUM> and may be the set memory cell. For example, memory cell A may be in state <NUM>. Memory cell A switches when the voltage of voltage ramp <NUM> reaches the Vt of memory cell A. Ramp voltage <NUM> is applied to memory cells A and B for the threshold delay time after memory cell A switches. Memory cell B switches when the voltage of voltage ramp <NUM> reaches the Vt of memory cell B as indicated by step <NUM>.

When memory cell B switches within the threshold delay time after memory cell A switches, as shown in <FIG>, it is determined that memory cell B is also in state <NUM>. For example, memory cell A and B are sensed as storing a data value of <NUM>. Therefore, the collective state of memory cells A and B is determined to be <NUM> in <FIG>.

In some examples, ramp voltage <NUM> is removed from the memory cells A and B at the threshold delay time after memory cell A switches. In an example, the threshold delay time may be equal to the width W of the Vt distribution, such as Vt distribution <NUM>-<NUM>, corresponding to the lowest state divided by the slope S (e.g., the rate of change) of ramp voltage <NUM>. For example, threshold delay time may be W/S.

When memory cell B fails to switch within the threshold delay time after memory cell A switches, as shown in <FIG>, it is determined that memory cell B is in state <NUM>. For example, memory cell B may be determined to be in state <NUM> without waiting for memory cell B to switch. For example, when memory cell B fails to switch before ramp voltage <NUM> is removed, it is determined to be in state <NUM>. The collective state of memory cells A and B in <FIG> is determined to be <NUM>, the respective individual states of memory cells A and B determined in <FIG>. Note that the group of memory cells A and B stores data according to an encoding function constrained such that respective code patterns <NUM> and <NUM> include at least one data unit having the data value <NUM>, for example.

Note that memory cell B in <FIG> does not switch until a time tB when the voltage across memory cell B is the voltage VB and indicated by step <NUM> in <FIG>. However, the state of memory cell B can be determined at the threshold delay time after memory cell A switches without waiting until time tB.

The examples of <FIG> are not limited to memory cell A being the set memory cell. For example, memory cells A and B may be interchanged in <FIG>, in which case memory cell B is the set memory cell. Therefore, the collective state in <FIG> will remain the same (e.g., <NUM>) since both memory cell A and memory cell B will be in state <NUM>. However, the collective state in <FIG> will be inverted (e.g., <NUM>) since memory cell A will be in state <NUM> and memory cell B will be in state <NUM>.

<FIG> illustrates the collective states that the group of two-state memory cells A and B can have and the corresponding bit codes, in accordance with a number of embodiments of the present disclosure. For example, the bit codes include the individual bits corresponding the individual states of memory cells A and B. In method described in conjunction with <FIG>, at least one of memory cells A and B may be programmed to state <NUM>, thus precluding the collective state <NUM>-<NUM> in which both memory cells A and B are in state <NUM>. This means that in the remaining collective states <NUM>-<NUM> to <NUM>-<NUM> at least one of the memory cells A and B is in state <NUM>, as shown in <FIG> illustrates an example storing data according to an encoding function constrained such that respective code patterns include at least the data value <NUM>, for example.

In the examples of <FIG>, applying the ramp voltage to memory cells A and B, having a set memory cell that is in the state <NUM>, such as memory cell A, and determining the state of memory cell B based on whether memory cell B switches within the threshold delay time of when memory cell A switches, overcomes the problems associated with drift. This is because the ramp voltage allows the state of memory cell A to be determined regardless of whether state <NUM> drifted and because the state of memory cell B is determined relative to state <NUM> regardless of whether state <NUM> drifted.

In some examples, the method described in conjunction with.

<FIG> may be used to determine the collective states of the group of memory cells C and D in <FIG>. For example, memory cells C and D may be respectively substituted for memory cells A and B in the method described in conjunction with <FIG> and in the example depicted in <FIG>. For instance, the group of memory cells C and D may have the collective states <NUM>-<NUM> to <NUM>-<NUM> depicted in the example of <FIG>.

<FIG> illustrates assigning groups of three data bits (e.g., data states) of a data pattern to the code bits of a code pattern resulting from combining two groups of two memory cells, in accordance with a number of embodiments of the present disclosure. In <FIG>, each of the data bits d1, d2, and d3 correspond to one of the two states <NUM> and <NUM>. Therefore, there are eight possible data states <NUM>-<NUM> to <NUM>-<NUM>, each corresponding to a different data pattern. In <FIG>, the group (e.g., a first group) of memory cells A and B and the group (e.g., a second group) memory cells C and D and their respective collective states are combined. <FIG> shows the nine combined collective states <NUM>-<NUM> to <NUM>-<NUM> of the combined first and second groups, where each collective state corresponds to a different code pattern. In the example of <FIG>, data states <NUM>-<NUM> to <NUM>-<NUM> are respectively assigned to combined collective states <NUM>-<NUM> to <NUM>-<NUM>, thereby leaving combined collective state <NUM>-<NUM> unused. The collective states <NUM>-<NUM> to <NUM>-<NUM> are respectively encoded in accordance with the assigned encodings <NUM>-<NUM> to <NUM>-<NUM>, for example.

In the example of <FIG>, the three-bit data patterns are mapped to four-bit code patterns. In general, an encoding function can map n-bit data patterns (e.g., n = <NUM> in <FIG>) to respective (n+<NUM>)-bit code patterns, where "n" is a number greater than two, and where each of the (n+<NUM>)-bit code patterns is a combined code pattern comprising the code patterns per set of memory cells, such as memory cells A, B, C, and, D in <FIG>.

In some examples, the method described in conjunction with <FIG> may be used to determine the states of the memory cells in groups of memory cells having more than two memory cells. For example, memory cells A, B, C, and D (e.g., each operating as a two-state cell) may be treated as a group of memory cells, and the individual states of memory cells A, B, C, and D, and thus the collective state of the group, may be determined.

For example, one of memory cells A, B, C, and D may be a set memory cell and may be in state <NUM>. Ramp voltage <NUM> may be applied across memory cells A, B, C, and D concurrently, and the first memory cell that switches is in state <NUM> and is the set memory cell. Voltage ramp <NUM> is then applied until the threshold delay time after the set memory cell switches, at which time ramp voltage <NUM> is removed. Any of the remaining memory cells in the group that switches while is ramp voltage <NUM> is being applied is determined to be in state <NUM>, whereas any of the remaining memory cells that do not switch while ramp voltage <NUM> is being applied is in state <NUM>.

<FIG> illustrates the possible collective states that the group of two-state memory cells A, B, C, and D can have and the corresponding bit codes, in accordance with a number of embodiments of the disclosure. For example, the bit codes include the individual bits corresponding the individual states of memory cells A, B, C, and D. However, at least one of memory cells A, B, C, and D (e.g., the set memory cell) is programmed to state <NUM>, thus precluding the collective state <NUM>-<NUM> in which all of memory cells A, B, C, and D are in state <NUM>. This means that in the remaining collective states <NUM>-<NUM> to <NUM>-<NUM> at least one of the memory cells A, B, C, and D is in state <NUM>, as shown in <FIG> illustrates another example storing data according to an encoding function constrained such that respective code patterns include at least the data value <NUM>, for example. The encoding function can be applied on per set basis (e.g., the set including memory cells A, B, C, and D) such that the code patterns per set include only those code patterns having at least one of the first data value, such as the data value <NUM> in <FIG>.

Note that in the example of <FIG>, there are <NUM><NUM> - <NUM> = <NUM> available collective states for two memory cells, and in the example of <FIG>, there are <NUM><NUM> - <NUM> = <NUM> available collective states for four memory cells. In general, there are <NUM>N - <NUM> available collective states for N memory cells. The loss of one state is due the having one memory cell in a group be a set memory cell in state <NUM>. However, the problems associated with drift are overcome by determining the states of the remaining cells according to when the set cell switches.

In the example of <FIG> any one of memory cells A, B, C, and D can be the set cell, as long as it is the first memory cell of the group to switch. For example, memory cells D, C, B, and A are respectively the set memory cells for collective states <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, and <NUM>-<NUM>.

In other examples, the same memory cell in a group may be the set cell, meaning that the same cell in the group will always switch first. The states of the remaining memory cells may then be determined according to whether they switch within the threshold delay time of when the set memory cell switches. For such examples, only the remaining memory cells may be used for data storage and the states of the remaining memory cells may correspond to code bits.

<FIG> illustrates assigning groups of three data bits (e.g., data states) of data patterns to the code bits code patterns corresponding to collective states of a group of memory cells in which the same memory cell of the group is assigned to the same state, in accordance with a number of embodiments. In <FIG>, memory cell D of the group of memory cells A, B, C, and D may always be programmed to state <NUM>, and the remaining memory cells A, B, C can be programed to either state <NUM> or state <NUM>. This means that the number of possible collective states is based on three memory cells and is thus <NUM><NUM> = <NUM>.

In <FIG>, the three data bits d1, d2, d3 of a three-bit data pattern are respectively stored in memory cells A, B, and C. For example, the states of data bits d1, d2, d3 may be as previously described in conjunction with <FIG> correspond one-to-one with the data states of memory cells A, B, and C. The data states <NUM>-<NUM> to <NUM>-<NUM> are respectively assigned to collective states <NUM>-<NUM> to <NUM>-<NUM>, each corresponding to a four-bit code pattern. For example, the collective states <NUM>-<NUM> to <NUM>-<NUM> are respectively encoded in accordance with the assigned encodings <NUM>-<NUM> to <NUM>-<NUM>.

In the example of <FIG>, n-bit (e.g., three-bit) data patterns are mapped to (n + <NUM>)-bit code patterns. In general, an encoding function can map n-bit data patterns to respective (n+<NUM>)-bit code patterns. The encoding function can map each one of the n-bit data patterns to a matching one of the (n+<NUM>)-bit code patterns with an additional bit having a particular data value, such as a data value of <NUM>, added, where the additional bit is a last bit of the (n+<NUM>)-bit code patterns, as shown in <FIG>.

<FIG> illustrates a flowchart of a method <NUM>, such as a read method, that may be implemented by controller <NUM> and that may correspond to <FIG>, in accordance with a number of embodiments of the present disclosure. A ramp voltage is applied to a group of memory cells in block <NUM>. At block <NUM> a first switching event is determined for the group. The ramp voltage is removed at the threshold delay time after the first switching event at block <NUM>. At block <NUM>, the states of the memory cells are determined based on whether they switched while the ramp voltage was being applied. For example, memory cells that switch while the ramp voltage was applied, including the memory cell that switched first, are in state <NUM>. Otherwise, the memory cells are in state <NUM>. Although states <NUM> and <NUM> were used to respectively denote the low and high states of a memory cell, the disclosure is not so limited. For example, states <NUM> and <NUM> can be used to respectively denote the low and high states.

In the preceding detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific examples. In the drawings, like numerals describe substantially similar components throughout the several views. Other examples may be utilized, and structural, logical and/or electrical changes may be made without departing from the scope of the present disclosure.

As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the embodiments of the present disclosure and should not be taken in a limiting sense.

As used herein, "a number of" something can refer to one or more of such things. For example, a number of memory cells can refer to one or more memory cells. A "plurality" of something intends two or more. As used herein, multiple acts being performed concurrently refers to acts overlapping, at least in part, over a particular time period. As used herein, the term "coupled" may include electrically coupled, directly coupled, and/or directly connected with no intervening elements (e.g., by direct physical contact) or indirectly coupled and/or connected with intervening elements. The term coupled may further include two or more elements that co-operate or interact with each other (e.g., as in a cause and effect relationship).

Claim 1:
A method (<NUM>) for sensing memory cells, the method comprising:
applying a voltage ramp (<NUM>) to a group of non-volatile resistance variable memory cells (<NUM>-<NUM>...<NUM>-N) to sense their respective states (<NUM>-<NUM>...<NUM>-<NUM>, <NUM>-<NUM>...<NUM>-<NUM>, <NUM>-<NUM>...<NUM>-<NUM>, <NUM>-<NUM>...<NUM>-<NUM>, <NUM>-<NUM>...<NUM>-<NUM>, <NUM>-<NUM>...<NUM>-<NUM>);
sensing which memory cell of the group is the first memory cell to experience a switching event responsive to the applied voltage ramp;
stopping application of the voltage ramp after a particular amount of time subsequent to when the first memory cell experiences the switching event; and
determining which additional memory cells of the group experience the switching event during the particular amount of time;
wherein the cells of the group determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and the cells of the group determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value; and
wherein the group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.