Patent Description:
A peripheral component interconnect express (peripheral component interconnect express, PCIe) bus is a high-speed bus used by a processor in a computer system to connect to a peripheral device. As a PCIe signal velocity increases and a PCIe bus is more widely applied, a retimer (retimer) with a time sequence recovery function is increasingly widely used between two PCIe devices. Because the retimer has a delay, an extra delay (<NUM> ns to <NUM> ns) is added each time a level of retimer is added, resulting in system performance loss. This impact is unacceptable in some application scenarios, for example, a PCIe memory application scenario. Therefore, how to reduce a retimer delay while ensuring a retimer drive capability (about <NUM> dB) is a problem that needs to be resolved.

<CIT> describes an apparatus, system and method for bypassing equalization at lower data rates.

This application provides a retimer application system, a retimer, and a data transmission method, to reduce a transmission delay. A data transmission method of the invention is defined by claim <NUM>, an apparatus of the invention comprising a retimer and a first storage area is defined by claim <NUM> and a retimer application system of the invention is defined by claim <NUM>.

According to a first aspect, a retimer application system is provided, including a primary chip, a retimer, and a secondary chip. A downstream port of the primary chip is connected to an upstream port of the retimer, and a downstream port of the retimer is connected to an upstream port of the secondary chip. The connection herein includes a direct connection and an indirect connection.

After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, where data stored in the first storage area is not lost when the retimer performs a reset operation;.

Specifically, when detecting that the secondary chip is connected to a link, the primary chip performs the first link training. The primary chip, the secondary chip, and the retimer all participate during the first link training. After the first link training is completed, the retimer stores, in the first storage area, the equalization parameter corresponding to each rate during the first link training. After the first link training is completed, the retimer receives the reset indication, and the retimer performs the reset operation when or after receiving the reset indication. The reset operation may be resetting all upstream ports and downstream ports of the retimer, or resetting the upstream port connected to the primary chip and the downstream port connected to the secondary chip. The reset operation of the retimer triggers the second link training between the primary chip and the secondary chip, where the retimer does not participate in the second link training. During the second link training between the primary chip and the secondary chip, the retimer invokes the equalization parameter, and transparently transmits the training sequence in the second link training between the primary chip and the secondary chip based on the equalization parameter.

In the retimer application system provided in this application, the primary chip, the secondary chip, and the retimer perform the first link training, to implement link load balancing and ensure a link compensation capability. After the first link training is completed, the primary chip and the secondary chip perform the second link training triggered by the reset operation of the retimer. During the second link training, the retimer transparently transmits the training sequence between the primary chip and the secondary chip based on the equalization parameter obtained during the first link training. Therefore, based on implementation of normal second link training, efficiency of the second link training can be further improved. After the second link training is completed, the retimer may transparently transmit service data between the primary chip and the secondary chip, so that a transmission delay can be reduced.

With reference to the first aspect, in a first possible implementation, the first storage area is a storage area in a nonvolatile memory or firmware (firmware) of the retimer. The nonvolatile memory may be, for example, an electrically erasable programmable read-only memory (electrically EPROM, EEPROM).

For example, the retimer may include the first storage area, or the first storage area may be located outside the retimer.

When the first storage area is located inside the retimer, the equalization parameter is stored in the retimer, so that a speed of invoking the equalization parameter can be improved.

In the first aspect, after the first link training is completed, the retimer is configured to bypass (bypass) a plurality of data processing circuits included in the retimer, so that the retimer enters a low-delay mode; and, in a second possible implementation of the first aspect, correspondingly, after the second link training is completed, the retimer is further configured to transparently transmit the service data between the primary chip and the secondary chip in the low-delay mode.

A manner of implementing the transparent transmission transparent transmission of the training sequence) is: after the first link training is completed, the retimer bypasses the plurality of data processing circuits included in the retimer. A working mode is the low-delay mode after the retimer bypasses the plurality of data processing circuits. In other words, after bypassing the plurality of data processing circuits, the retimer enters the low-delay mode. In the low-delay mode, the plurality of data processing circuits are in a bypass state, and the retimer only transparently transmits a received data stream. After or when bypassing the plurality of data processing circuits, in other words, after or when the retimer enters the low-delay mode, the retimer receives the reset indication, where the reset indication triggers the reset operation of the retimer. In this case, because the retimer works in the low-delay mode, the retimer only forwards the training sequence during the second link training triggered by the reset operation. In addition, in the second possible implementation, after the second link training is completed, the retimer transmits the service data between the primary chip and the secondary chip in the low-delay mode, that is, the retimer transparently transmits the service data between the primary chip and the secondary chip.

The retimer performs the first link training, to implement link load balancing and ensure a link compensation capability. After the first link training is completed, the retimer performs the reset operation and invokes the equalization parameter obtained through the first link training. Because the data processing circuit is in the bypass state, the retimer only forwards the received training sequence without processing the training sequence, so that the second link training can be completed quickly. In the second possible implementation, after the second link training, the retimer transmits the service data between the primary chip and the secondary chip in the low-delay mode, so that a transmission delay can be reduced.

With reference to the first aspect, the first possible implementation of the first aspect, or the second possible implementation of the first aspect, in a third possible implementation, the retimer further includes a link state machine (link training and status state machine, LTSSM), where the data processing circuit is configured to convert received serial data into a training sequence for processing by the link state machine, and convert the training sequence processed by the link state machine into serial data.

With reference to the third possible implementation of the first aspect, in a fourth possible implementation, during the first link training, the retimer is further configured to store the equalization parameter in a register; and
after the first link training is completed, the retimer is further configured to store, in the first storage area, the equalization parameter that is stored in the register.

With reference to the fourth possible implementation of the first aspect, in a fifth possible implementation, during the second link training, the retimer is further configured to store the equalization parameter that is stored in the first storage area in the register.

With reference to any one of the first aspect or the first to the fifth possible implementations of the first aspect, in a sixth possible implementation, the application system further includes a basic input/output system (basic input output system, BIOS), and after the first link training is completed, the BIOS is configured to send the reset indication to the retimer.

The BIOS sends the reset indication, and there is no need to specially design the primary chip and the secondary chip or modify a standard negotiation sequence, so that the retimer has quite good commonality.

With reference to any one of the first aspect or the first to the fifth possible implementations of the first aspect, in a seventh possible implementation, after the first link training is completed, the primary chip is configured to send the reset indication to the retimer.

In the first aspect the retimer includes a sending equalization circuit and a receiving equalization circuit, and after the retimer enters the low-delay mode, an output of the receiving equalization circuit is used as an input of the sending equalization circuit.

With reference to any one of the first aspect or the first to seventh possible implementations of the first aspect, in an eighth possible implementation, the receiving equalization circuit may include a continuous time linear equalization (continuous time linear equalization, CTLE)/decision feedback equalization (decision feedback equalization, DFE) circuit. The sending equalization circuit may include a feed forward equalization (feed forward equalization, FFE) circuit.

In the first aspect, the equalization parameter obtained after the first link training includes a receiving equalization parameter of the receiving equalization circuit and a sending equalization parameter of the sending equalization circuit.

With reference to any one of the first aspect or the first to the eighth possible implementations of the first aspect, in a ninth possible implementation, the retimer supports a plurality of protocols, and can select a working protocol used by the primary chip and the secondary chip to work, and the plurality of protocols include at least one of the following:
a peripheral component interconnect express PCIe protocol, a cache coherent interconnect for accelerators (cache coherent interconnect for accelerators, CCIX) protocol, or a universal serial bus (universal serial bus, USB) protocol.

The retimer in this application may support a plurality of high-speed buses, and is widely applied. In addition, during system design, a plurality of types of retimers do not need to be considered for use, so that hardware design complexity and subsequent verification workload can be reduced.

Optionally, a protocol used by the retimer may be selected by pulling up or down a specified pin of the retimer. Alternatively, through a management interface (for example, Smbus) defined in a standard, system software configures, after power-on, a protocol used by the retimer to work. Alternatively, a protocol used by the retimer is configured by using a specific negotiation code stream (for example, denoted as a second negotiation code stream).

With reference to any one of the first aspect or the first to the ninth possible implementations of the first aspect, in a tenth possible implementation, the data processing circuit may include a serial-to-parallel conversion circuit, an elastic buffer (elastic buffer), a descrambling/decoding circuit, a scrambling/encoding circuit, and a parallel-to-serial conversion circuit.

For specific functions and implementations of these modules, refer to the prior art.

In the retimer in this application, in a data transmission process, data only passes through the receiving equalization circuit and the sending equalization circuit, and there is no need to first perform serial-to-parallel conversion, buffering, and descrambling/decoding, and then perform scrambling/encoding and parallel-to-serial conversion on the received data according to a protocol stipulation. Instead, a circuit obtained after equalization implements bitwise processing and forwarding to avoid a delay caused by operations such as serial-to-parallel conversion, buffering, descrambling/decoding, scrambling/encoding, and parallel-to-serial conversion, thereby implementing a low-delay function.

In addition, based on simulation estimation, compared with a retimer in an existing standard, when only the sending equalization circuit and the receiving equalization circuit are reserved, and the serial-to-parallel conversion circuit, the elastic buffer, the descrambling/decoding circuit, the scrambling/encoding circuit, and the parallel-to-serial conversion circuit are bypassed, the retimer provided in this application can reduce a delay to about <NUM> ns, thereby improving system performance.

According to a second aspect, a data transmission method as defined by claim <NUM>
is provided, and the method includes:.

With reference to the second aspect, in a first possible implementation, the first storage area is a storage area in a nonvolatile memory or firmware of the retimer.

In the second aspect, the method further includes:.

With reference to the second aspect or the first possible implementation of the second aspect, in a second possible implementation, the retimer further includes a link state machine, where the data processing circuit is configured to convert received serial data into a training sequence for processing by the link state machine, and convert the training sequence processed by the link state machine into serial data.

With reference to the second aspect, the first possible implementation of the second aspect, or the second possible implementation of the second aspect, in a third possible implementation, the method further includes:.

With reference to the third possible implementation of the second aspect, in a fourth possible implementation, the step of invoking, by the retimer, the equalization parameter specifically includes:
storing, by the retimer, the equalization parameter that is stored in the first storage area in the register.

With reference to any one of the second aspect or the first to the fourth possible implementations of the second aspect, in a fifth possible implementation, the method further includes:
after the first link training is completed, sending, by a basic input/output system BIOS, the reset indication to the retimer.

With reference to any one of the second aspect or the first to the fifth possible implementations of the second aspect, in a sixth possible implementation, the method further includes:
after the first link training is completed, sending, by the primary chip, the reset indication to the retimer.

In the second aspect, the retimer includes a sending equalization circuit and a receiving equalization circuit, and after the retimer enters the low-delay mode, an output of the receiving equalization circuit is used as an input of the sending equalization circuit.

With reference to any one of the second aspect or the first to the sixth possible implementations of the second aspect, in a seventh possible implementation, the retimer supports a plurality of protocols, and can select a working protocol used by the primary chip and the secondary chip to work, and the plurality of protocols include at least one of the following: a peripheral component interconnect express PCIe protocol, a cache coherent interconnect for accelerators CCIX protocol, or a universal serial bus USB protocol.

With reference to any one of the second aspect or the first to the seventh possible implementations of the second aspect, in an eighth possible implementation, the first storage area is a nonvolatile memory.

The method provided in the second aspect may be applied to the retimer application system provided in the first aspect. Specifically, the primary chip, the secondary chip, and the retimer in the second aspect may correspond to the primary chip, the secondary chip, and the retimer in the first aspect. Therefore, for details of the method in the second aspect, refer to the foregoing description of the application system in the first aspect.

According to a third aspect,an apparatus as defined by claim <NUM> comprising a first storage area and retimer is provided, including a control circuit, where.

The retimer provided in this application performs the first link training, to implement link load balancing and ensure a link compensation capability. After the first link training is completed, the primary chip and the secondary chip perform second link training triggered by the reset operation of the retimer. During the second link training, the retimer transparently transmits the training sequence between the primary chip and the secondary chip based on the equalization parameter obtained based on the first link training. Therefore, based on implementation of normal second link training, efficiency of the second link training can be further improved. After the second link training is completed, the retimer may transparently transmit service data between the primary chip and the secondary chip, so that a transmission delay can be reduced.

Optionally, the retimer includes the first storage area.

Optionally, the first storage area is located outside the retimer.

In the third aspect, the retimer further includes a plurality of data processing circuits, where.

With reference to the third aspect or the first possible implementation of the third aspect, in a second possible implementation, the first storage area is a storage area in a nonvolatile memory or firmware of the retimer.

With reference to the first possible implementation of the third aspect, in a third possible implementation, the retimer further includes a link state machine, where the data processing circuit is configured to convert received serial data into a training sequence for processing by the link state machine, and convert the training sequence processed by the link state machine into serial data.

With reference to any one of the third aspect or the first to the third possible implementations of the third aspect, in a fourth possible implementation, during the first link training, the control circuit is further configured to store the equalization parameter in a register; and
after the first link training is completed, the control circuit is further configured to store, in the first storage area, the equalization parameter that is stored in the register.

With reference to the fourth possible implementation of the third aspect, in a fifth possible implementation, during the second link training, the control circuit is further configured to store the equalization parameter that is stored in the first storage area in the register.

In the third aspect the retimer includes a sending equalization circuit and a receiving equalization circuit, and after the retimer enters the low-delay mode, an output of the receiving equalization circuit is used as an input of the sending equalization circuit.

With reference to any one of the third aspect or the first to the fifth possible implementations of the third aspect, in a sixth possible implementation, the retimer supports a plurality of protocols, and the controller can select a working protocol used by the primary chip and the secondary chip to work, and the plurality of protocols include at least one of the following: a peripheral component interconnect express PCIe protocol, a cache coherent interconnect for accelerators CCIX protocol, or a universal serial bus USB protocol.

The retimer provided in the third aspect corresponds to the retimer in the retimer application system in the first aspect. Therefore, for details of the retimer in the third aspect, refer to the foregoing descriptions of the application system in the first aspect and the retimer in the application system.

In the retimer application system provided in this application, the link training is performed, to implement complete equalization and ensure a link compensation capability. After the link training is completed, the data processing circuits are bypassed, so that the retimer only forwards a received data stream without processing the data stream. Therefore, the retimer can transparently transmit the service data between the primary chip and the secondary chip, thereby reducing a transmission delay.

<FIG> is a block diagram of an example of an application topology of a retimer with a time sequence recovery function (hereinafter referred to as a retimer) according to this application. Referring to <FIG>, a downstream port (downstream port, DSP) of a primary chip <NUM> is connected to an upstream port of a secondary chip <NUM> by using a retimer <NUM>. Specifically, a downstream port (downstream port, DSP) of the primary chip <NUM> is connected to an upstream port (upstream port, USP) of the retimer <NUM> by using a link <NUM>, and a downstream port of the retimer <NUM> is connected to the upstream port of the secondary chip <NUM> by using a link <NUM>.

In addition, in this application, a downstream port of the primary chip <NUM> may also be cascaded to a plurality of retimers to connect to an upstream port of the secondary chip <NUM>. For example, <FIG> shows a case in which two retimers are cascaded. Referring to <FIG>, the downstream port of the primary chip <NUM> is connected to an upstream port of a retimer <NUM><NUM> by using a link <NUM>, a downstream port of the retimer <NUM><NUM> is connected to an upstream port of a retimer <NUM><NUM> by using a link <NUM>, and a downstream port of the retimer <NUM><NUM> is connected to the upstream port of the secondary chip <NUM> by using a link <NUM>.

In the topology structure shown in <FIG>, for the retimer <NUM>, the primary chip <NUM> is an upstream chip, and the secondary chip <NUM> is a downstream chip. In the topology structure shown in <FIG>, for the retimer <NUM><NUM>, the primary chip <NUM> is an upstream chip, and the retimer <NUM><NUM> is a downstream chip. For the retimer <NUM><NUM>, the retimer <NUM><NUM> is an upstream chip, and the secondary chip <NUM> is a downstream chip. It should be understood that, if two ends of the link <NUM> are connected to a downstream port of the retimer <NUM><NUM> and another retimer, for example, a retimer <NUM><NUM>, both an upstream chip and a downstream chip of the retimer <NUM><NUM> are retimers.

The primary chip <NUM> may be a chip that includes a downstream port and that is not a retimer. For example, the primary chip <NUM> may be a root complex (root complex, RC), a switch chip (Switch), or the like. The secondary chip <NUM> may be a chip that includes an upstream port and that is not a retimer. For example, the secondary chip <NUM> may be an endpoint device (Endpoint) or a switch chip. The endpoint device may be a video card, a network adapter, an optical channel card, a storage card, a switch chip, or the like.

The links (link) shown in <FIG> and <FIG>, such as the link <NUM> and the link <NUM>, may include one, two, four, eight, sixteen, or another quantity of lanes (lane), and each lane may include a pair of received signals (Rx) and a pair of transmitted signals (Tx). The retimer (for example, the retimer <NUM>, the retimer <NUM><NUM>, and the retimer <NUM><NUM>) complies with a link protocol, to implement communication between the primary chip <NUM> and the secondary chip <NUM>. The link protocol may be, for example, another protocol such as a PCIe protocol, a CCIX protocol, or a USB protocol.

<FIG> is a schematic diagram of a retimer application system <NUM> according to this application. As shown in <FIG>, the application system <NUM> includes a primary chip <NUM>, a secondary chip <NUM>, and a retimer <NUM>. Specifically, a downstream port of the primary chip <NUM> is connected to an upstream port of the retimer <NUM>, and a downstream port of the retimer <NUM> is connected to an upstream port of the secondary chip <NUM>. It should be understood that the "connection" herein includes a direct connection and an indirect connection. For example, the primary chip <NUM>, the secondary chip <NUM>, and the retimer <NUM> may be respectively the primary chip <NUM>, the secondary chip <NUM>, and the retimer <NUM> shown in <FIG>. In this case, the retimer <NUM> is directly connected to the primary chip <NUM> and the secondary chip <NUM>. For another example, the primary chip <NUM> and the secondary chip <NUM> may be the primary chip <NUM> and the secondary chip <NUM> shown in <FIG>, and the retimer <NUM> may be the retimer <NUM><NUM> or the retimer <NUM><NUM> shown in <FIG>. In this case, the retimer <NUM> is indirectly connected to the primary chip <NUM>, or is indirectly connected to the secondary chip <NUM>. Alternatively, the retimer <NUM> is indirectly connected to both the primary chip <NUM> and the secondary chip <NUM>, to be specific, the upstream port of the retimer <NUM> is connected to another retimer, and the downstream port of the retimer <NUM> is also connected to another retimer.

After first link training is completed, the retimer <NUM> is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, where data stored in the first storage area is not lost when the retimer <NUM> performs a reset operation.

The retimer <NUM> is configured to: receive a reset indication, and perform the reset operation according to the reset indication.

Second link training triggered by the reset indication is performed between the primary chip <NUM> and the secondary chip <NUM>.

During the second link training, the retimer <NUM> is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip <NUM> or the secondary chip <NUM> based on the equalization parameter, to complete the second link training between the primary chip <NUM> and the secondary chip <NUM>. It should be noted that the transparent transmission means that a received signal is directly forwarded to another component without being processed. In this application, that the retimer <NUM> transparently transmits the training sequence to the primary chip <NUM> (or the secondary chip <NUM>) means that after receiving the training sequence, the retimer <NUM> directly transmits the training sequence to the primary chip <NUM> (or the secondary chip <NUM>) without processing the training sequence.

The first link training is link training initiated when the primary chip <NUM> detects that the secondary chip <NUM> is connected to a link, or the primary chip <NUM> detects that the secondary chip <NUM> is connected to the primary chip by using a retimer (including the retimer <NUM>).

The second link training refers to link training triggered by the reset operation performed by the retimer <NUM> after the retimer <NUM> receives the reset indication. During the second link training, the retimer <NUM> actually does not participate in the link training, and only transparently transmits the training sequence during the second link training.

The transparent transmission means that the retimer <NUM> does not process a received data stream (for example, the training sequence), it may also mean, for example, that the retimer <NUM> does not perform serial-to-parallel conversion, decoding, parallel-to-serial conversion, encoding, or the like on the received data stream, and instead only forwards the data stream.

Specifically, when detecting that the secondary chip <NUM> is connected to a link, the primary chip <NUM> performs the first link training. The primary chip <NUM>, the secondary chip <NUM>, and the retimer <NUM> all participate during the first link training. For example, the primary chip <NUM>, the secondary chip <NUM>, and the retimer <NUM> are respectively the primary chip <NUM>, the secondary chip <NUM>, and the retimer <NUM> shown in <FIG>. The first link training is link training of the downstream port of the primary chip <NUM> and the upstream port of the retimer <NUM> and link training of the downstream port of the retimer <NUM> and the upstream port of the secondary chip. The first link training includes an equalization process. The retimer <NUM> obtains or acquires during the first link training, the equalization parameter corresponding to each rate. The equalization parameter includes a sending equalization parameter and a receiving equalization parameter of the retimer <NUM>. After the first link training is completed, the retimer <NUM> stores, in the first storage area, the equalization parameter corresponding to each rate during the first link training. After the first link training is completed, the retimer <NUM> receives the reset indication, and the retimer <NUM> performs the reset operation when or after receiving the reset indication. The reset operation may be resetting all upstream ports and downstream ports of the retimer, or may be resetting an upstream port connected to the primary chip <NUM> and a downstream port connected to the secondary chip <NUM>. The reset operation of the retimer <NUM> triggers the second link training between the primary chip <NUM> and the secondary chip <NUM>, where the retimer <NUM> does not participate in the second link training. During the second link training between the primary chip <NUM> and the secondary chip <NUM>, the retimer <NUM> invokes the equalization parameter, and transparently transmits the training sequence in the second link training between the primary chip and the secondary chip based on the equalization parameter.

In the retimer application system provided in this application, the primary chip, the secondary chip, and the retimer perform the first link training, to implement link load balancing and ensure a link compensation capability. After the first link training is completed, the primary chip and the secondary chip perform the second link training triggered by the reset operation of the retimer. During the second link training, the retimer transparently transmits the training sequence between the primary chip and the secondary chip based on the equalization parameter obtained based on the first link training. Therefore, based on implementation of normal second link training, efficiency of the second link training can be further improved. After the second link training is completed, the retimer may transparently transmit service data between the primary chip and the secondary chip, so that a transmission delay can be reduced.

Optionally, in an embodiment of this application, the first storage area may be a storage area in a nonvolatile memory, and the nonvolatile memory may be, for example, an EEPROM. In addition, the first storage area may be alternatively a storage area in a volatile memory. The first storage area may be located inside the retimer <NUM>, or may be located outside the retimer <NUM>. This is not limited in this application.

In addition, the first storage area may be a storage area in firmware (firmware) of the retimer <NUM>. In this case, a register write operation does not need to be performed when the equalization parameter is invoked.

For example, the first storage area may be alternatively an area used to store a parameter corresponding to another port of the retimer <NUM>, and the another port is not connected to the primary chip <NUM> or the secondary chip <NUM>. In this case, the reset operation may be resetting a port that is of the retimer <NUM> and that is connected to the primary chip <NUM> and the secondary chip <NUM>. Because the another port is not reset, the equalization parameter stored in the area used to store the parameter corresponding to the another port is not lost after the reset operation.

Further, the volatile memory may be a memory in the retimer <NUM>. The equalization parameter is stored in the retimer <NUM>, so that a speed of invoking the equalization parameter can be improved.

Optionally, in an embodiment of this application, during the first link training, the retimer <NUM> is further configured to store the equalization parameter in a register. After the first link training is completed, the retimer <NUM> is further configured to store, in the first storage area, the equalization parameter that is stored in the register.

It should be understood that the register may be a register configured to store an initial equalization parameter. However, this is not limited in this application.

Further, during the second link training, the retimer <NUM> is further configured to store the equalization parameter that is stored in the first storage area in the register.

In addition, the primary chip <NUM> and the secondary chip <NUM> may separately store equalization parameters obtained during the first link training corresponding to the primary chip <NUM> and the secondary chip <NUM>. In this way, these equalization parameters may be directly invoked during the second link training, so that the second link training can be quickly completed.

Optionally, in an embodiment of this application, the application system <NUM> further includes system firmware <NUM>. After the first link training is completed, the system firmware <NUM> is configured to send the reset indication to the retimer <NUM>. The system firmware <NUM> may include a BIOS or a drive of the retimer <NUM>.

The system firmware sends the reset indication, and there is no need to specially design the primary chip <NUM> and the secondary chip <NUM> or modify a standard negotiation sequence, so that the retimer <NUM> has quite good commonality.

Optionally, in another embodiment of this application, after the first link training is completed, the primary chip <NUM> is configured to send the reset indication to the retimer <NUM>.

The reset indication sent by the primary chip <NUM> may be a specific negotiation code stream, for example, denoted as a first negotiation code stream. When receiving the first negotiation code stream, the retimer <NUM> performs the reset operation.

Further, reset may be implemented by a program stored in primary chip firmware (different from the system firmware). In a running process of the program, a link is reset, and the retimer invokes a parameter after a control circuit detects that the link is reset. In this implementation, the retimer does not reset the link, and the primary chip resets the link.

Optionally, in an embodiment of this application, the retimer <NUM> may support a plurality of protocols, for example, may support a high-speed bus protocol such as a PCIe protocol, a CCIX protocol, or a USB protocol, and can select one of the protocols for working.

In a possible implementation, protocol selection of the retimer may be implemented in the following manner:.

During system design, in a scenario in which the retimer determines a protocol, one of the protocols may be selected by pulling up or down a specified pin of the retimer. For example, Table <NUM> shows a correspondence between a pin and a protocol.

In Table <NUM>, PIN_A and PIN_B are two pins of the retimer, and protocol selection of the retimer may be implemented by performing a pull-up/pull-down operation on the two pins. For example, the pin PIN_A is pulled up and the pin PIN_B is pulled down, so that the retimer supports the USB protocol. Through a management interface (for example, Smbus) defined in a standard, system software configures, after power-on, a protocol used by the retimer to work. A protocol used by the retimer is configured by using a specific negotiation code stream (for example, denoted as a second negotiation code stream). In other words, a negotiation code stream may correspond to a protocol, and a corresponding protocol may be configured by using a corresponding negotiation code stream. It should be understood that the second negotiation code stream may be identified by the following link state machine <NUM>.

The following describes the retimer <NUM> in the application system <NUM> with reference to <FIG> and <FIG>.

<FIG> is a schematic structural diagram of the retimer <NUM>.

Optionally, in an embodiment of this application, the retimer <NUM> includes a control circuit <NUM>.

The control circuit <NUM> performs the operations of storing the equalization parameter after the first link training is completed, invoking the equalization parameter during the second link training, and transparently transmitting the training sequence during the second link training based on the equalization parameter.

Optionally, in an embodiment of this application, the retimer further includes a plurality of data processing circuits <NUM>.

After the first link training is completed, the retimer <NUM> is further configured to bypass the plurality of data processing circuits <NUM> included in the retimer <NUM>. Correspondingly, after the second link training is completed, the retimer <NUM> is further configured to transparently transmit service data between a primary chip <NUM> and a secondary chip <NUM>.

A manner of implementing the transparent transmission transparent transmission of the training sequence) is: after the first link training is completed, the retimer <NUM> bypasses the plurality of data processing circuits included in the retimer <NUM>. A working mode is the low-delay mode after the retimer <NUM> bypasses the plurality of data processing circuits. In other words, after bypassing the plurality of data processing circuits <NUM>, the retimer <NUM> enters the low-delay mode. In the low-delay mode, the plurality of data processing circuits <NUM> are in a bypass state, and the retimer <NUM> only transparently transmits a received data stream. After or when bypassing the plurality of data processing circuits <NUM>, in other words, after or when the retimer enters the low-delay mode, the retimer <NUM> receives the reset indication, where the reset indication triggers the reset operation of the retimer <NUM>. In this case, because the retimer <NUM> works in the low-delay mode, the retimer only forwards the training sequence during the second link training triggered by the reset operation. In addition, after the second link training is completed, the retimer <NUM> transmits the service data between the primary chip <NUM> and the secondary chip <NUM> in the low-delay mode, that is, the retimer <NUM> transparently transmits the service data between the primary chip <NUM> and the secondary chip <NUM>.

The retimer performs the first link training, to implement link load balancing and ensure a link compensation capability. After the first link training is completed, the retimer performs the reset operation and invokes the equalization parameter obtained through the first link training. Because the data processing circuit is in the bypass state, the retimer only forwards the received training sequence without processing the training sequence, so that the second link training can be completed quickly. After the second link training, the retimer transmits the service data between the primary chip and the secondary chip in the low-delay mode, so that a transmission delay can be reduced.

It is easy to understand that the retimer <NUM> supports a plurality of lanes, and the plurality of lanes are a plurality of lanes connected to the primary chip <NUM> and the secondary chip <NUM>. In addition, each lane corresponds to two data paths, one of the two data paths is used for sending, and the other is used for receiving. Structures of the two data paths used for receiving and sending may be the same, and each data path may correspond to a data processing circuit.

It should be further understood that the control circuit <NUM> in the retimer <NUM> perfroms the foregoing operations of bypassing the plurality of data processing circuits <NUM> and transparently transmitting the service data between the primary chip <NUM> and the secondary chip <NUM> in the low-delay mode.

Optionally, in an embodiment of this application, the retimer <NUM> further includes a link state machine <NUM>. The link state machine <NUM> is configured to perform link training. The data processing circuit <NUM> is configured to: convert received serial data into a training sequence processed by the link state machine <NUM>, and convert the training sequence processed by the link state machine <NUM> into serial data. As another understanding of the data processing circuit <NUM>, the data processing circuit <NUM> may convert serial data into input data of the link state machine <NUM>, and convert output data of the link state machine <NUM> into serial data. It should be understood that the input data and the output data of the link state machine <NUM> are in a same format as that of a link state machine of a retimer in the prior art.

It should be further understood that the link state machine <NUM> may perform the first link training.

Optionally, in an embodiment of this application, after the first link training is completed, the retimer <NUM> may further bypass the link state machine <NUM>. In this way, no data stream passes through the link state machine <NUM>, so that a transmission delay can be further reduced. It should be understood that an operation of bypassing the link state machine <NUM> may be performed by the control circuit <NUM>.

<FIG> is another schematic structural diagram of the retimer <NUM>. It should be understood that <FIG> shows only one data processing circuit <NUM> of the plurality of data circuits <NUM>. A same or similar structure may be used for another data processing circuit <NUM>. It should be further understood that the retimer <NUM> shown in <FIG> may further include the control circuit <NUM> and the link state machine <NUM> shown in <FIG> and not shown in <FIG>.

The retimer <NUM> further includes a receiving equalization circuit <NUM> and a sending equalization circuit <NUM>. After the retimer <NUM> enters the low-delay mode, an output of the receiving equalization circuit <NUM> is used as an input of the sending equalization circuit <NUM>.

Further, the receiving equalization circuit <NUM> and the sending equalization circuit <NUM> are connected by using the data processing circuit <NUM>.

It should be understood that, as described above, each of two data paths corresponding to each of the plurality of lanes supported by the retimer <NUM> may correspond to one data processing circuit. In addition, each data path may further correspond to one receiving equalization circuit <NUM> and one sending equalization circuit <NUM>.

After the plurality of data processing circuits are bypassed, data passes through only the receiving equalization circuit and the sending equalization circuit, and does not pass through the plurality of data processing circuits. Therefore, a delay caused by data processing of the data processing circuit can be avoided.

For example, the receiving equalization circuit <NUM> may include a continuous time linear equalization (continuous time linear equalization, CTLE)/decision feedback equalization (decision feedback equalization, DFE) circuit. The sending equalization circuit <NUM> may include a feed forward equalization (feed forward equalization, FFE) circuit.

Optionally, in an embodiment of this application, the data processing circuit <NUM> may include a serial-to-parallel conversion circuit <NUM>, an elastic buffer <NUM>, a descrambling/decoding circuit <NUM>, a scrambling/encoding circuit <NUM>, and a parallel-to-serial conversion circuit <NUM>.

The serial-to-parallel conversion circuit <NUM> is configured to convert serial data output by the receiving equalization circuit <NUM> into parallel data. The elastic buffer <NUM> may be a first in first out (first in first out, FIFO) queue, and is configured to buffer data. To prevent the elastic buffer <NUM> from overflowing, the link state machine <NUM> may irregularly add or delete an SKP sequence in the elastic buffer circuit <NUM>. The descrambling/decoding circuit <NUM> is configured to descramble/decode data output by the elastic buffer <NUM>. The link state machine <NUM> can identify descrambled/decoded data, and perform corresponding processing according to a property of the descrambled/decoded data. For example, during first link training, the link state machine identifies that the decoded data is a training sequence, and therefore performs link training.

The scrambling/encoding circuit <NUM> is configured to: scramble/encode data that needs to be sent, to obtain data that conforms to a protocol, and output the data to the parallel-to-serial conversion circuit <NUM>. The parallel-to-serial conversion circuit <NUM> is configured to: convert parallel data into serial data and output the serial data to the sending equalization circuit. For example, during the first link training, after the link state machine processes the training sequence, the scrambling/encoding circuit <NUM> scrambles/encodes the training sequence, and then outputs the training sequence to the parallel-to-serial conversion circuit <NUM>. The parallel-to-serial conversion circuit <NUM> converts the training sequence into serial data, and finally the sending equalization circuit <NUM> sends the serial data.

In the retimer in this application, in a data transmission process, data passes through only the receiving equalization circuit and the sending equalization circuit, and there is no need to first perform serial-to-parallel conversion, buffering, and descrambling/decoding, and then perform scrambling/encoding and parallel-to-serial conversion on the received data according to a protocol stipulation. Instead, a circuit obtained after equalization implements bitwise processing and forwarding to avoid a delay caused by operations such as serial-to-parallel conversion, buffering, descrambling/decoding, scrambling/encoding, and parallel-to-serial conversion, thereby implementing a low-delay function.

It should be understood that the foregoing modules included in the data processing circuit <NUM> may be implemented in a manner known to a person skilled in the art, and details are not described herein again. It should be understood that the modules listed herein may be separately implemented by one component or an independent circuit, or a plurality of modules may be implemented by one component or an independent circuit, provided that the data processing circuit <NUM> can implement a function thereof.

It should be further understood that a connection relationship between the modules listed herein is merely an example for description, and the connection relationship between the modules may be alternatively in another form, provided that a basic function of the retimer can be implemented. Alternatively, in actual use, if one or more of the foregoing modules included in the data processing circuit <NUM> are not required to process the training sequence during link training, the data processing circuit <NUM> may correspondingly not include the one or more modules.

In addition, it should be further understood that the retimer may further include another basic functional module, for example, a clock and data recovery (clock and data recovery, CDR) circuit and a phase locked loop (phase locked loop, PLL). However, this is not limited in this application. For details of the CDR circuit and the PLL, refer to descriptions about a CDR circuit and a PLL in an existing retimer.

<FIG> shows a data transmission method according to this application. The method may be applied to the application system shown in <FIG>.

S410: After first link training is completed, a retimer stores, in a first storage area, an equalization parameter corresponding to each rate during the first link training, where data stored in the first storage area is not lost when the retimer performs a reset operation.

S420: The retimer receives a reset indication, and performs the reset operation according to the reset indication.

S430: In a process in which a primary chip and a secondary chip perform second link training triggered by the reset indication, the retimer invokes the equalization parameter, and transparently transmits a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter, to complete the second link training between the primary chip and the secondary chip.

In the method provided in this application, the primary chip, the secondary chip, and the retimer perform the first link training, to implement link load balancing and ensure a link compensation capability. After the first link training is completed, the primary chip and the secondary chip perform the second link training triggered by the reset operation of the retimer. During the second link training, the retimer transparently transmits the training sequence between the primary chip and the secondary chip based on the equalization parameter obtained based on the first link training. Therefore, based on implementation of normal second link training, efficiency of the second link training can be further improved. After the second link training is completed, the retimer may transparently transmit service data between the primary chip and the secondary chip, so that a transmission delay can be reduced.

Optionally, in an embodiment of this application, the first storage area is a storage area in a nonvolatile memory or firmware of a retimer.

Optionally, in an embodiment of this application, the retimer further includes a link state machine, where the data processing circuit is configured to convert received serial data into a training sequence for processing by the link state machine, and convert the training sequence processed by the link state machine into serial data.

Optionally, in an embodiment of this application, the method further includes:.

Optionally, in an embodiment of this application, the step of invoking, by the retimer, the equalization parameter specifically includes:
storing, by the retimer, the equalization parameter that is stored in the first storage area in the register.

Optionally, in an embodiment of this application, the method further includes:
after the first link training is completed, sending, by a basic input/output system BIOS, the reset indication to the retimer.

Optionally, in an embodiment of this application, the method further includes:
after the first link training is completed, sending, by the primary chip, the reset indication to the retimer.

In <FIG>, the retimer includes a sending equalization circuit and a receiving equalization circuit. After the retimer enters the low-delay mode, an output of the receiving equalization circuit is used as an input of the sending equalization circuit.

Optionally, in an embodiment of this application, the retimer supports a plurality of protocols, and can select a working protocol used by the primary chip and the secondary chip to work, and the plurality of protocols include at least one of the following: a peripheral component interconnect express PCIe protocol, a cache coherent interconnect for accelerators CCIX protocol, or a universal serial bus USB protocol.

For details of the method shown in <FIG>, refer to the foregoing description of the application system <NUM>.

This application further provides a retimer. For the retimer, refer to the foregoing description of the retimer <NUM>. Details are not described in this specification.

<FIG> shows another data transmission method according to this application. A retimer in the method may be the retimer <NUM> in the application system <NUM>.

S510: After first link training is completed, the retimer stores, in a first storage area, an equalization parameter corresponding to each rate during the first link training, where data stored in the first storage area is not lost after the retimer performs a reset operation.

S520: The retimer receives a reset indication, and performs the reset operation according to the reset indication.

S530: After the reset operation is performed, the retimer invokes the equalization parameter, and transparently transmits a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter, to complete the second link training between the primary chip and the secondary chip, where the second link training is triggered by the reset operation.

In <FIG>, the retimer further includes a plurality of data processing circuits.

Optionally, in an embodiment of this application, the step of invoking, by the retimer, the equalization parameter specifically includes:
during the second link training, storing, by the retimer, the equalization parameter that is stored in the first storage area in the register.

Optionally, in an embodiment of this application, the receiving, by the retimer, a reset indication includes:
after the first link training is completed, receiving, by the retimer, the reset indication sent by a basic input/output system BIOS.

Optionally, in an embodiment of this application, the receiving, by the retimer, a reset indication includes:
after the first link training is completed, receiving, by the retimer, the reset indication sent by the primary chip.

Optionally, in an embodiment of this application, the method further includes:
selecting, by the retimer from a plurality of indicated protocols, a working protocol used by the primary chip and the secondary chip to work, where the plurality of protocols include at least one of the following: a peripheral component interconnect express PCIe protocol, a cache coherent interconnect for accelerators CCIX protocol, or a universal serial bus USB protocol.

For details of the method shown in <FIG>, refer to the foregoing description of the retimer of the application system <NUM>.

<FIG> is a schematic diagram of another retimer application system <NUM> according to this application. As shown in <FIG>, the application system <NUM> includes a primary chip <NUM>, a secondary chip <NUM>, and a retimer <NUM>. Specifically, a downstream port of the primary chip <NUM> is connected to an upstream port of the retimer <NUM>, and a downstream port of the retimer <NUM> is connected to an upstream port of the secondary chip <NUM>. It should be understood that the "connection" herein includes a direct connection and an indirect connection. For example, the primary chip <NUM>, the secondary chip <NUM>, and the retimer <NUM> may be respectively the primary chip <NUM>, the secondary chip <NUM>, and the retimer <NUM> shown in <FIG>. In this case, the retimer <NUM> is directly connected to the primary chip <NUM> and the secondary chip <NUM>. For another example, the primary chip <NUM> and the secondary chip <NUM> may be the primary chip <NUM> and the secondary chip <NUM> shown in <FIG>, and the retimer <NUM> may be the retimer <NUM><NUM> or the retimer <NUM><NUM> shown in <FIG>. In this case, the retimer <NUM> is indirectly connected to the primary chip <NUM>, or is indirectly connected to the secondary chip <NUM>. Alternatively, the retimer <NUM> is indirectly connected to both the primary chip <NUM> and the secondary chip <NUM>, to be specific, the upstream port of the retimer <NUM> is connected to another retimer, and the downstream port of the retimer <NUM> is also connected to another retimer.

The retimer <NUM> includes a plurality of data processing circuits <NUM>.

After link training is completed, the retimer <NUM> is configured to bypass the plurality of data processing circuits <NUM>, to enter a low-delay mode; and
the retimer transparently transmits service data between the primary chip <NUM> and the secondary chip <NUM> in the low-delay mode.

Specifically, after the retimer <NUM> is powered on, if the primary chip <NUM> determines that the secondary chip <NUM> is connected to a link, the link training is initiated. It should be understood that the link training may be performed in a link training manner known in the art. Details are no longer described in this application. After the link training is completed, the retimer <NUM> bypasses is (bypass) the plurality of data processing circuits <NUM>, so that the retimer <NUM> can enter the low-delay mode. After the retimer <NUM> enters the low-delay mode, the plurality of data processing circuits <NUM> no longer process a data stream. Then, the retimer <NUM> may transparently transmit the service data between the primary chip <NUM> and the secondary chip <NUM> in the low-delay mode.

It is easy to understand that the retimer <NUM> supports a plurality of lanes, and the plurality of lanes are a plurality of lanes connected to the primary chip <NUM> and the secondary chip <NUM>. In addition, each lane corresponds to two data paths, one of the two data paths is used for sending, and the other is used for receiving. Structures of the two data lanes used for receiving and sending may be the same, and each data path may correspond to a data processing circuit <NUM>.

<FIG> is a schematic structural diagram of the retimer <NUM>. Referring to <FIG>, the retimer <NUM> includes a data processing circuit <NUM>. It should be understood that <FIG> shows only one data processing circuit <NUM>, and a structure of another data processing circuit of the plurality of data processing circuits <NUM> is the same or similar.

The retimer <NUM> further includes a control circuit <NUM>. The control circuit is configured to perform the foregoing functions of bypassing the plurality of data processing circuits <NUM> and transparently transmitting the service data between the primary chip <NUM> and the secondary chip <NUM>.

Optionally, in an embodiment of this application, the retimer <NUM> further includes a link state machine <NUM>. The link state machine <NUM> is configured to perform link training, and the data processing circuit <NUM> is configured to: convert received serial data into a training sequence processed by the link state machine <NUM>, and convert the training sequence processed by the link state machine <NUM> into serial data.

As another understanding of the data processing circuit <NUM>, the data processing circuit <NUM> may convert serial data into input data of the link state machine <NUM>, and convert output data of the link state machine <NUM> into serial data. It should be understood that the input data and the output data of the link state machine <NUM> are in a same format as that of a link state machine in a retimer in the prior art.

It should be further understood that the link state machine <NUM> may perform the link training.

In <FIG>, the retimer <NUM> further includes a receiving equalization circuit <NUM> and a sending equalization circuit <NUM>. After the retimer <NUM> enters the low-delay mode, an output of the receiving equalization circuit <NUM> is used as an input of the sending equalization circuit <NUM>.

Optionally, in an embodiment of this application, for a specific structure of the data processing circuit <NUM>, refer to the data processing circuit <NUM> shown in <FIG> and the foregoing description of the data processing circuit <NUM> shown in <FIG>.

In addition, it should be further understood that the retimer <NUM> may further include another basic functional module, for example, a clock and data recovery (clock and data recovery, CDR) circuit and a phase locked loop (phase locked loop, PLL). However, this is not limited in this application. For details of the CDR circuit and the PLL, refer to descriptions about a CDR circuit and a PLL in an existing retimer.

<FIG> is a flowchart of an example of a data transmission method according to this application. The method may be applied to the retimer <NUM> in the application system <NUM>.

S710: After link training is completed, a retimer bypasses a plurality of data processing circuits included in the retimer, to enter a low-delay mode.

S720: The retimer transparently transmits service data between a primary chip and a secondary chip in the low-delay mode.

The retimer further includes a link state machine, where the data processing circuit is configured to convert received serial data into a training sequence for processing by the link state machine, and convert the training sequence processed by the link state machine into serial data.

For details of the method shown in <FIG>, refer to the description about the retimer <NUM> in the application system <NUM>.

<FIG> is a schematic diagram of a system <NUM> that is combined with a technology according to The this application. technology may be incorporated into an interconnection or an interface in the system <NUM>.

Referring to <FIG>, the system <NUM> includes, but is not limited to, a desktop computer, a notebook computer, a network book, a tablet computer, a notebook computer, a personal digital assistant (personal digital assistant, PDA), a server, a workstation, a mobile phone, a mobile computing device, a smartphone, an Internet device, or any other type of computing device.

In a possible implementation, the system <NUM> may include a processor, for example, a processor <NUM>. In another possible implementation, the system <NUM> may include a plurality of processors, for example, include processors <NUM> and <NUM>. The processor <NUM> has logic similar to or the same as that of the processor <NUM>, or the processor <NUM> has logic completely independent of that of the processor <NUM>. The processor may be a central processing unit (Central Processing Unit, CPU), the processor may alternatively be another general purpose processor, a digital signal processor (digital signal processor, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC), a field programmable gate array (field programmable gate array, FPGA) or another programmable logical device, a discrete gate or transistor logic device, or a discrete hardware component. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like.

In a possible implementation, the system <NUM> may include a memory <NUM>. The processor <NUM> can access the memory <NUM> and has a function of communicating with the memory <NUM>. The memory <NUM> stores information and an instruction to be executed by the processor <NUM>. The memory <NUM> may include a volatile memory and/or a nonvolatile memory. The nonvolatile memory may be a read-only memory (read-only memory, ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (electrically EPROM, EEPROM), or a flash memory. The volatile memory may be a random access memory (random access memory, RAM), used as an external cache. Through example but not limitative description, many forms of random access memory (random access memory, RAM) RAMs may be used, for example, a static random access memory (static RAM, SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (synchronous DRAM, SDRAM), a double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), an enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), a synchronous link dynamic random access memory (synchlink DRAM, SLDRAM), and a direct rambus random access memory (direct rambus RAM, DR RAM).

In a possible implementation, the processors <NUM> and <NUM> may communicate with a chipset <NUM>. In a possible implementation, the chipset <NUM> is connected to the processor <NUM> by using point-to-point (point to point, P-P) interfaces <NUM> and <NUM>. The interfaces <NUM> and <NUM> may communicate based on any possible P-P communication protocol.

In a possible implementation, the chipset <NUM> may communicate with a display device <NUM> and another device by using an interface <NUM>. The another device is a bus bridge <NUM>, a smart TV <NUM>, an I/O device <NUM>, a keyboard/mouse <NUM>, and a network interface <NUM> shown in the figure. The display device <NUM> includes, but is not limited to, a liquid crystal display (LCD), a plasma, and a cathode ray tube (CRT).

In a possible implementation, the chipset <NUM> may be connected to the another device for communication by using one or more buses <NUM> and <NUM>. In a possible implementation, the buses <NUM> and <NUM> may be interconnected by using the bus bridge <NUM>.

In a possible implementation, the network interface <NUM> is implemented by using any type of well-known network interface standard, including, but not limited to, an Ethernet interface, a USB interface, a PCIe interface, a CCIX interface, a wireless interface, and/or any other suitable type of interface.

It should be understood that although some modules in <FIG> are depicted as separate modules in the system <NUM>, functions performed by some of these modules may be integrated in a single semiconductor circuit, or may be implemented by using two or more separate integrated circuits.

All or some of the foregoing embodiments may be implemented by means of software, hardware, firmware, or any combination thereof. When software is used to implement the embodiments, the foregoing embodiments may be implemented completely or partially in a form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the program instructions or the computer programs are loaded and executed on the computer, the procedure or functions according to the embodiments of this application are all or partially generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable apparatuses. The computer instructions may be stored in a computer-readable storage medium or may be transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center in a wired (for example, infrared, radio, and microwave, or the like) manner. The computer-readable storage medium may be any usable medium accessible by a computer, or a data storage device, such as a server or a data center, integrating one or more usable media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium may be a solid-state drive.

The term "and/or" in this specification describes only an association relationship for describing associated objects and represents that three relationships may exist.

Claim 1:
A data transmission method through a retimer (<NUM>, <NUM><NUM>, <NUM><NUM>, <NUM>) connected between a primary chip (<NUM>) and a secondary chip (<NUM>), the method comprising:
having the retimer, the primary chip and the secondary chip performing a first link training, wherein said retimer includes a receiving equalization circuit (<NUM>) at its input, a sending equalization circuit (<NUM>) at its output and data processing circuits (<NUM>);
after the first link training is completed, storing (S410), by the retimer in a first storage area, an equalization parameter corresponding to each rate during the first link training, wherein the equalization parameter includes a receiving equalization parameter of the receiving equalization circuit and a sending equalization parameter of the sending equalization circuit, and wherein data stored in the first storage area is not lost when the retimer performs a reset operation;
characterized in that the method further includes:
receiving (S420), by the retimer, a reset indication, and performing the reset operation according to the reset indication;
in a process in which the primary chip and the secondary chip but not the retimer perform (S430) a second link training triggered by the reset indication, invoking (S430), by the retimer, the equalization parameter, and transmitting (S430), by the retimer, based on the equalization parameter, a training sequence in the second link training between the primary chip and the secondary chip by by-passing the data processing circuits such that an output of the receiving equalization circuit is used as an input of the sending equalization circuit, to complete the second link training between the primary chip and the secondary chip.