Patent Description:
Today many integrated circuits are battery powered and rely heavily on low power consumption to achieve extended battery life. These integrated circuits typically include millions of transistors with a significant portion of the transistors consuming dynamic power during normal operation. To minimize dynamic power consumption and extend battery life, there is a need for improved low power techniques.

It is cited the patent application <CIT> that discloses a dynamic CMOS flip-flop where there is a match of the duty cycle of the clock signal to the ratio of the propagation delays of the master and the slave sections.

It is also cited the patent document <CIT> that discloses an adaptive clock pulse width control circuitry with improved power consumption.

The invention is defined in the accompanying claims.

Generally, there is provided, an integrated circuit that includes asymmetrical clock generation circuitry coupled to provide to an asymmetrical clock to one or more storage elements configured in a master-slave arrangement. The asymmetrical clock is generated having a predetermined duty cycle greater than <NUM>% such that intermediate data transitions are inhibited from propagating through master portions of the storage elements. By inhibiting the intermediate data transitions and glitches from propagating through the master portions, significant dynamic power savings can be realized.

<FIG> illustrates, in simplified block diagram form, an example integrated circuit <NUM> in accordance with an embodiment. Integrated circuit <NUM> includes a system bus <NUM>, processor <NUM>, memory <NUM>, other modules <NUM>, clock generator <NUM>, and logic <NUM>. Processor <NUM>, memory <NUM>, other modules <NUM>, clock generator <NUM>, and logic <NUM> are each bi-directionally coupled to system bus <NUM> by way of respective communication buses. In some embodiments, integrated circuit <NUM> may be characterized as a system-on-a-chip (SoC), for example.

System bus <NUM> can be any type of bus for communicating any type of information and/or transferring any type of signals such as address, data, instructions, clocks, reset, and control. System bus <NUM> provides a communication backbone for communications among the processor <NUM>, memory <NUM>, other modules <NUM>, clock generator <NUM>, and logic <NUM>.

Processor <NUM> may be any type of processor, including circuits for processing, computing, etc., such as microprocessor (MPU), microcontroller (MCU), or digital signal processor (DSP), or other type of processing circuitry. Integrated circuit <NUM> may include multiple processors like processor <NUM>. Processor <NUM> is configured to execute instructions in order to carry out designated tasks.

Memory <NUM> may include any suitable type of memory array, such as static random-access memory (SRAM), for example. Memory <NUM> may also be coupled directly or tightly coupled to processor <NUM>. Integrated circuit <NUM> may include multiple memories like memory <NUM> or a combination of different memories. For example, integrated circuit <NUM> may include a flash memory in addition to memory <NUM>.

Other modules <NUM> of integrated circuit <NUM> may include any number of other circuits and functional hardware modules such as accelerators, timers, counters, communications, interfaces, analog-to-digital converters, digital-to-analog converters, PLLs, and the like for example.

Clock generator <NUM> may include one or more PLLs and other clock circuitry to provide clock signals for processor <NUM>, memory <NUM>, other modules <NUM>, and logic <NUM>. Clock generator <NUM> may include a phase-locked loop (PLL) clock and/or other circuitry configured to generate clock signals. In this embodiment, clock generator <NUM> is configured to generate source clock signal labeled CLK for logic <NUM>.

Logic <NUM> may include one or more logic circuits such as combinational logic, storage elements, flip flops, state machines, and the like, for example. Logic <NUM> may also include associated control circuits (e.g., clock generators, reset circuits, mode circuits, etc.). Logic <NUM> may be configured to perform any number of logical functions or operations and may be as characterized as a logic circuit within a larger circuit, functional block, or module. In this embodiment, logic <NUM> is configured to receive the CLK source clock signal from clock generator <NUM>.

<FIG> illustrates, in simplified schematic diagram form, an example clock duty cycle control circuit <NUM> in accordance with an embodiment. In the embodiment depicted in <FIG>, circuit <NUM> includes asymmetrical clock generator (ACG) <NUM>, storage elements <NUM>-<NUM>, and logic circuits <NUM>-<NUM>. In other embodiments, circuit <NUM> may include asymmetrical clock generator <NUM> along with other numbers of storage elements and logic circuits.

The asymmetrical clock generator <NUM> includes an input for receiving a source clock signal labeled CLK and an output for providing an asymmetrical clock signal labeled ASYMCLK. The CLK clock signal may come from a clock generator circuit like clock generator <NUM> depicted in <FIG>. The output of the asymmetrical clock generator <NUM> is coupled to provide the ASYMCLK clock signal at clock inputs of storage elements <NUM>-<NUM> by way of signal lines labeled ASYMCLK. The asymmetrical clock generator <NUM> is configured to provide the ASYMCLK signal having a first phase (e.g., logic high phase) longer than a second phase (e.g., logic low phase). For example, the ASYMCLK signal may have a <NUM>% duty cycle where the first phase is approximately <NUM>% of the ASYMCLK signal period.

The storage elements <NUM>-<NUM> may be any suitable storage elements (e.g., flip flops) having a master-slave circuit structure where the master and slave portions may be clocked on alternate clock phases. Each storage element <NUM>-<NUM> includes a data input labeled D for receiving a data signal, a clock input indicated by a triangular symbol for receiving a clock signal (e.g., ASYMCLK), and an output labeled Q for providing a stored data value. The storage elements <NUM>-<NUM> may include other inputs (e.g., set, reset, scan enable) and outputs (e.g., complement output QB). In this embodiment, storage elements <NUM>-<NUM> may be characterized as D-type or D flip flops, state-retention flip flops, scan flip flops, multi-bit flip flops, and so on.

The logic circuits <NUM>-<NUM> may include any combinational or random logic circuits, gates (e.g., AND,OR, NAND, NOR, XOR, NOT), or other logic circuits configured to perform logical functions or operations. In this embodiment, the logic circuits <NUM>-<NUM> are coupled to storage elements <NUM>-<NUM>. For example, an output of logic circuit <NUM> is coupled to provide a data signal D1 at the D input of storage element <NUM>, and the Q output of storage element <NUM> is coupled to provide an output signal Q1 to logic circuit <NUM>. An output of logic circuit <NUM> is coupled to provide a data signal D2 at the D input of storage element <NUM>, and the Q output of storage element <NUM> is coupled to provide an output signal Q2 to logic circuit <NUM>. An output of logic circuit <NUM> is coupled to provide a data signal D3 at the D input of storage element <NUM>, and so on.

<FIG> illustrates, in simplified schematic diagram form, an example implementation of the asymmetrical clock generator <NUM> in accordance with an embodiment. The asymmetrical clock generator <NUM> includes an input coupled to receive a clock signal labeled CLK and an output for proving an asymmetrical clock signal labeled ASYMCLK. In this embodiment, the asymmetrical clock generator <NUM> includes a counter-based divider circuit portion <NUM> and a phase delay circuit portion <NUM>. The divider circuit <NUM> serves as a coarse adjustment circuit and the delay circuit <NUM> serves as a fine adjustment when generating the asymmetrical clock signal. In this embodiment, the asymmetrical clock generator <NUM> is configured to generate an asymmetrical clock signal having a duty cycle greater than <NUM>%. In some embodiments, the asymmetrical clock generator <NUM> is configured to generate the asymmetrical clock signal having a duty cycle in a range of <NUM>% to <NUM>%.

The divider circuit <NUM> may be any suitable frequency divider circuit configured to generate an output signal having an asymmetrical duty cycle. In this embodiment, divider circuit <NUM> includes a divide-by <NUM> counter and is configured to generate a divide-by <NUM> asymmetrical clock signal having approximately a <NUM>% duty cycle (e.g., two-thirds of the cycle active or at a logic high level). The divider circuit <NUM> includes flip flops <NUM>-<NUM>, AND gate <NUM>, and OR gate <NUM>. Each flip-flop <NUM>-<NUM> includes a data input labeled D, a clock input indicated by a triangular symbol, an output labeled Q, and a complement output labeled QB. The clock inputs of flip flop <NUM>-<NUM> are coupled to receive the CLK signal by way of signal line labeled CLK. The Q output of flip flop <NUM> is coupled to the D input of flip flop <NUM> by way of signal line labeled CD2. The QB output of flip flop <NUM> is coupled to a first input of AND gate <NUM> and a first input of OR gate <NUM> by way of signal line labeled CQB1. The QB output of flip flop <NUM> is coupled to a second input of AND gate <NUM> and a second input of OR gate <NUM> by way of signal line labeled CQB2. An output of AND gate <NUM> is coupled to the D input of flip flop <NUM> by way of signal line labeled CD1. An output of OR gate <NUM> is coupled to provide an asymmetrical, counter-based divided signal labeled ASYMCLKF to the delay circuit <NUM>.

The delay circuit <NUM> may be any suitable delay circuit configured to generate a phase delay by adding time delay to an active phase of a signal for fine adjustments (e.g., <NUM>% to <NUM>% increase) to the duty cycle of the signal. For example, the delay circuit <NUM> may be configured to modify the duty cycle of the ASMYCLKF signal to have approximately a <NUM>% duty cycle by delaying the active phase of the ASMYCLKF signal by an additional <NUM>% of the cycle. The delay circuit <NUM> includes an input coupled to receive the ASMYCLKF signal and an output for providing the asymmetrical clock signal ASYMCLK. In this embodiment, the delay circuit <NUM> includes a first signal path formed by series connected delay inverters <NUM>-<NUM> coupled to a first input of OR gate <NUM> and a second signal path coupled to a second input of OR gate <NUM>. Each inverter <NUM>-<NUM> may be configured to have a predetermined delay amount such that the overall delay of the first signal path meets a desired target. An input of inverter <NUM> is coupled to receive the ASMYCLKF signal and an output of inverter <NUM> is coupled to an input of inverter <NUM> by way of signal line DL1. An output of inverter <NUM> is coupled to an input of inverter <NUM> by way of signal line DL2 and an output of inverter <NUM> is coupled to an input of inverter <NUM> by way of signal line DL3. An output of inverter <NUM> is coupled to the first input of OR gate <NUM> by way of signal line DL4, the second input of OR gate <NUM> is coupled to receive the ASYMCLKF signal, and an output of OR gate <NUM> is coupled to provide the ASYMCLK signal. In this configuration, delay circuit <NUM> add delay to the active phase (e.g., logic high phase) of the ASYMCLKF to form the ASYMCLK signal with a desired duty cycle. In other embodiments, the delay circuit <NUM> may include other elements (e.g., resistors, capacitors) either alone or in combination with one or more delay inverters to form the desired delay of the first signal path. By construction, both the divider circuit <NUM> and delay circuit <NUM> are configured with circuitry which allows the asymmetrical clock generator <NUM> to track process, voltage, and temperature.

<FIG> illustrates, in simplified schematic diagram form, an example implementation of a master-slave flip flop circuit <NUM> in accordance with an embodiment. In an embodiment, flip flop <NUM> is representative of storage elements <NUM>-<NUM>. The flip flop <NUM> may also be referred to as a D-type flip flop, data flip flop, and D flip flop. Flip flop <NUM> includes a first input node labeled C for receiving a clock signal C, a second input node labeled D for receiving a data signal D, and an output node labeled Q for providing a data output signal Q. A complement clock signal is provided at node labeled CB by way of inverter <NUM>. In this example, flip flop <NUM> includes a master circuit portion <NUM> and a slave circuit portion <NUM> coupled in series. Alternative circuits may be used to implement storage elements <NUM>-<NUM> in accordance with an embodiment of the present disclosure.

The master circuit <NUM> includes inverters <NUM>-<NUM> and transmission gates <NUM>-<NUM>. A first terminal of transmission gate <NUM> is coupled at an input labeled D to receive a data signal and a second terminal of transmission gate <NUM> is coupled to an input of inverter <NUM> and a first terminal of transmission gate <NUM>. An active low control input of transmission gate <NUM> is coupled at the C node and an active high control input of transmission gate <NUM> is coupled at the CB node. An output of inverter <NUM> is coupled to inputs of inverters <NUM> and <NUM> and an output of inverter <NUM> is coupled to a second terminal of transmission gate <NUM>. An active high control input of transmission gate <NUM> is coupled at the C node and an active low control input of transmission gate <NUM> is coupled at the CB node. An output of inverter <NUM> is coupled to an input of the slave circuit <NUM> at node labeled QM.

The slave circuit <NUM> includes inverters <NUM>-<NUM> and transmission gates <NUM>-<NUM>. A first terminal of transmission gate <NUM> is coupled at node QM to receive an output data signal QM from the master circuit <NUM>. A second terminal of transmission gate <NUM> is coupled to an input of inverter <NUM> and a first terminal of transmission gate <NUM>. An active high control input of transmission gate <NUM> is coupled at the C node and an active low control input of transmission gate <NUM> is coupled at the CB node. An output of inverter <NUM> is coupled to inputs of inverters <NUM> and <NUM> and an output of inverter <NUM> is coupled to a second terminal of transmission gate <NUM>. An active low control input of transmission gate <NUM> is coupled at the C node and an active high control input of transmission gate <NUM> is coupled at the CB node. An output of inverter <NUM> is coupled at the Q output node and provides the output data signal Q of flip flop <NUM>.

In this example, the master circuit <NUM> is configured to be transparent when the clock signal C is at a logic low level allowing transitions of the data signal D to propagate through to the output QM. While transparent, the transitions can cause a significant amount of unwanted power consumption. The master circuit <NUM> is configured to be non-transparent when the clock signal C is at a logic high level (e.g., active phase) and transitions of the data are essentially stopped or blocked at transmission gate <NUM>. By extending the logic high level (e.g., active phase) duration of the clock signal C to form an asymmetrical clock with a predetermined duty cycle greater than <NUM>%, virtually all of the transitions can be inhibited or blocked from propagating through the master circuit <NUM>, thus saving significant power.

In some embodiments, flip flop <NUM> may be configured as a state retention flip flop having the master circuit supplied by a voltage supply different from that of the slave circuit. For example, the master circuit may be supplied by a first voltage supply that is capable of being disabled during a state retention mode while the slave circuit remains powered by a second voltage supply having a voltage sufficient to retain a stored state in the slave circuit during the state retention mode. In normal operating modes, both first and second voltage supplies my supply a common voltage to respective master and slave circuits.

<FIG> illustrates, in simplified timing diagram form, example signal timing <NUM> of clock duty cycle control circuit of <FIG> in accordance with an embodiment. Signal timing <NUM> includes source clock signal CLK, example <NUM>% duty cycle clock signal CLK50, asymmetrical clock signal ASYMCLK, and example data signal DATA waveforms. As provided above, the example implementation of the asymmetrical clock generator <NUM> as depicted in <FIG> includes counter-based divider circuitry <NUM> and a phase delay circuitry <NUM> for generating a divide-by <NUM> asymmetrical clock signal ASYMCLK. The ASYMCLK waveform is shown having a counter-based divided-by <NUM> active portion from time marker t1 to t3 and a phase delayed portion from time marker t3 to t4. In some embodiments, the phase delayed portion may range from <NUM>% to <NUM>% for fine adjustments to the duty cycle of ASYMCLK. For comparison purposes, the CLK50 signal is shown as a <NUM>% duty cycle version of a divide-by <NUM> clock having an active phase (e.g., logic high level from time marker t1 to t2) approximately equal to <NUM>% of the cycle time (e.g., from time marker t1 to t5).

The data signal DATA is shown transitioning from a logic low value to a logic high value and back to the logic low value several times from time marker t1 to t3. In this example the DATA signal may represent example data signals D1-D3 generated in respective logic circuits <NUM>-<NUM>. Depending on the signal paths and the number of logic gates within those paths, the data signals D1-D3 may include several transitions like those shown in the DATA signal. Storage elements such as flip flops are typically clocked by a <NUM>% duty cycle clock like CLK50. However, intermediate data transitions may occur while the master portion of the flip flops are transparent allowing the intermediate data transitions like those from timing marker t2 to t3 of the DATA waveform to propagate through the master portion. Accordingly, unwanted power consumption can occur. In contrast, when storage elements <NUM>-<NUM> are clocked by the ASYMCLK signal, the intermediate data transitions occur while the master circuit portion is non-transparent, thus resulting in significant power savings.

By now it should be appreciated that there has been provided an integrated circuit that includes asymmetrical clock generation circuitry coupled to provide to an asymmetrical clock to one or more storage elements configured in a master-slave arrangement. The asymmetrical clock is generated having a predetermined duty cycle greater than <NUM>% such that intermediate data transitions are inhibited from propagating through master portions of the storage elements. By inhibiting the intermediate data transitions from propagating through the master portions, significant power savings can be realized.

Generally, there is provided, an integrated circuit including a first master-slave storage element having a data input coupled to receive a data signal; and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the first master-slave storage element, a first phase of the asymmetrical clock signal configured for inhibiting intermediate data signal transitions from propagating through the master portion of the first master-slave storage element. The asymmetrical clock generator may be configured to generate the first phase having a range of <NUM>% to <NUM>% of the asymmetrical clock cycle. The asymmetrical clock generator may include circuitry to generate the first phase of the asymmetrical clock such that the first phase tracks process, voltage, and temperature. The asymmetrical clock generator includes a counter-based divider circuit. The asymmetrical clock generator includes a phase delay circuit. The first master-slave storage element may be characterized as a D-type flip flop or D flip flop. The first master-slave storage element may be characterized as a state retention flip flop having the slave portion supplied by a voltage supply different from the master portion. The integrated circuit may further include a second master-slave storage element having a clock input coupled to receive the asymmetrical clock signal. The integrated circuit may further include a logic circuit coupled between an output of the first master-slave storage element and a data input of the second master-slave storage element, the first phase of the asymmetrical clock signal further configured for inhibiting intermediate data signal transitions from propagating through the master portion of the second master-slave storage element.

In one embodiment, there is provided, an integrated circuit including a first storage element having a master circuit and a slave circuit, the master circuit configured to be transparent during a first phase of a clock signal; and an asymmetrical clock generator coupled to provide the clock signal to the first storage element, the first phase of the clock signal configured to be longer than a second phase of the clock signal. The asymmetrical clock generator is configured to provide the clock signal based on a counter-based divider circuit output signal. The asymmetrical clock generator is configured to provide the clock signal based on a phase delay circuit output signal. The asymmetrical clock generator may be configured to generate the clock signal having a duty cycle in a range of <NUM>% to <NUM>%. The asymmetrical clock generator includes circuitry to generate the first phase of the clock such that the first phase tracks process, voltage, and temperature. The first storage element may be characterized as a D-type flip flop or D flip flop. The integrated circuit may further include a logic circuit coupled between an output of the first storage element and a data input of a second storage element, the second storage element having a clock input coupled to receive the clock signal.

In another embodiment, there is provided, an integrated circuit including a first storage element having a master circuit and a slave circuit, the master circuit coupled to receive a data signal and configured to be transparent during a first phase of a clock signal; and an asymmetrical clock generator coupled to provide the clock signal to the first storage element, the first phase of the clock signal configured for inhibiting intermediate data signal transitions from propagating through the master circuit. The asymmetrical clock generator may be configured to generate the clock signal having a duty cycle in a range of <NUM>% to <NUM>%. The asymmetrical clock generator is configured to provide the clock signal based on a counter-based divider circuit output signal. The integrated circuit may further include a logic circuit coupled between an output of the first storage element and a data input of a second storage element, the second storage element having a clock input coupled to receive the clock signal.

Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.

Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed.

Moreover, the terms "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative.

Claim 1:
An integrated circuit (<NUM>) comprising:
a first master-slave storage element (<NUM>) having a data input coupled to receive a data signal; and
an asymmetrical clock generator (<NUM>) comprising:
a phase delay circuit (<NUM>); and
a counter-based divider circuit (<NUM>);
wherein the asymmetrical clock generator (<NUM>) is coupled to provide an asymmetrical clock signal to the first master-slave storage element, a first phase of the asymmetrical clock signal configured for inhibiting intermediate data signal transitions from propagating through the master portion (<NUM>) of the first master-slave storage element (<NUM>), and wherein the phase delay circuit (<NUM>) is configured to generate the first phase of the asymmetrical clock signal such that the first phase tracks process, voltage, and temperature, and is configured to provide a fine adjustment of the asymmetrical clock signal, and
the counter-based divider circuit (<NUM>) is configured to provide a coarse adjustment of the asymmetrical clock signal.