Patent Description:
Evaporation is used in microfabrication. Evaporation is a common method of thin-film deposition in which the deposition source material is evaporated in a vacuum. During evaporation, a hot source material evaporates and then condenses back to a solid state on the target object (sample). Because the evaporation takes place in a vacuum, vapors other than the source material are almost entirely removed before the process begins. In a high vacuum (with a long mean free path), evaporated particles can travel directly to the deposition target without colliding with the background gas. At a typical pressure of <NUM>-<NUM> Pascals (Pa), a <NUM> nanometer particle has a mean free path of <NUM> meters. Evaporated atoms that collide with foreign particles can react with them. For example, if aluminum is deposited in the presence of oxygen, it will form aluminum oxide. Evaporated materials deposit non-uniformly if the substrate has a rough surface (as integrated circuits often do). Because the evaporated material attacks the substrate mostly from a single direction, protruding features block the evaporated material from some areas. This phenomenon is called "shadowing" or "step coverage.

A common technique for the fabrication of Josephson junctions (JJs) involves double-angle shadow evaporation of aluminum through an offset mask, wherein the tunnel barrier is formed by the diffusive oxidation of the aluminum base layer. Shadow evaporation has been the most successful fabrication approach to date for making long-lived, high-coherence superconducting quantum bits (or qubits).

The Niemeyer-Dolan technique, also called the Dolan technique or the shadow evaporation technique, is a thin-film lithographic method to create nanometer-sized overlapping structures. This technique uses an evaporation mask that is suspended above the substrate. The evaporation mask can be formed from two layers of resist. Depending on the evaporation angle, the shadow image of the mask is projected onto different positions on the substrate. By carefully choosing the angle for each material to be deposited, adjacent openings in the mask can be projected on the same spot, creating an overlay of two thin films with a well-defined geometry. Another technique for fabricating an overlay of two thin films during lithography is known as a Manhattan crossing, named as such because it has intersecting streets and avenues at right angles. In this technique, an evaporation is first done along an avenue at a tilt angle that is typically steeper than that used for a Dolan. This results in deposition of material along the avenue but no deposition within the street because all the material evaporated into the street is intercepted by the evaporation mask such as a resist. The crossing is then formed by performing a similarly steep subsequent evaporation along the street. No material is evaporated within the avenue in the subsequent evaporation because all the material evaporated into the avenue is again intercepted by the evaporation mask. The only area not protected by the evaporation mask is the intercept between the street and the avenue, resulting in a Manhattan crossing overlay.

New shadow mask evaporation techniques are needed to form tunnel junctions, such as Josephson junctions for superconducting quantum computing applications. In particular, new techniques are sought which can reduce variability of fabrication. An example of prior art may be found in patent document <CIT>. The document discloses a method of high-vacuum oblique vapor deposition and a compensated shadow effect of a pre-patterned layer. An example of prior art according to Art. <NUM>(<NUM>) EPC, may be found in patent document <CIT>.

The present invention is directed to a method for correcting an area of overlap between two films created by sequential shadow mask evaporations, as defined in claim <NUM>.

Embodiments and aspects of the invention are described in detail herein. The inventive subject-matter, however, is defined in the appended claims.

The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term "coupled" and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.

In the accompanying figures and following detailed description of the described embodiments, the various elements illustrated in the figures are provided with two or three digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.

For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, technologically-relevant tunnel junctions for application in quantum computing are made with superconductors and have dimensions of about <NUM> nanometers on a side. The two main types of tunnel junctions utilized by researchers in the field of quantum computing are obtained by the Dolan Bridge or Manhattan techniques. A tunnel junction made by the Dolan Bridge technique is referred to as a Dolan junction, while a tunnel junction made by the Manhattan technique is referred to as a Manhattan junction. A Manhattan junction can be fabricated utilizing a pattern known as a Manhattan crossing during lithography, named as such because it has intersecting streets and avenues at right angles.

Turning now to an overview of the aspects of the invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by providing methods for shadow mask area correction for Josephson tunnel junctions (JJs) used in superconducting quantum computing applications. The Josephson junction area is dominated by the width of a layer such as the deposited film or a pre-existing fin. As used in embodiments of the present invention, shadow mask or angle evaporation are fabrication techniques that can be utilized in making high quality superconducting qubits. A Josephson junction is a type of tunnel junction, which consists of superconducting metal on either side of a weak link, such as an oxide layer (known as a tunnel barrier), a short section of non-superconducting metal, or a physical constriction in a superconductor. The superconducting metal (instead of regular metal) makes a Josephson junction a special type of tunnel junction. A superconducting qubit is a special case of a qubit and is made using one or more Josephson junctions. Therefore, the Josephson junction is the required component of a superconducting qubit. Other qubits exist but are not made of Josephson junctions.

More specifically, the above-described aspects of the invention address the shortcomings of the prior art by techniques to correct shadow mask evaporation in superconducting quantum circuits, which corrects the high variability in the tunnel junction lithographic area thereby correcting the variability of the tunnel current Ic. Josephson tunnel junctions utilized in superconducting quantum circuits are typically made with multiple shadow mask evaporations. These evaporation steps utilize a combination of multiple tilt and rotation angles, multiple shadow masking techniques (bridge or bridgeless), and an intermediary in-situ oxidation step without breaking vacuum. The resulting critical currents (Ic) exhibit high variability across a large sample/wafer. Variation in total tilt angle is often assumed to be negligible for fabrication purposes because the distance between the source and sample is <NUM><NUM> times larger than the typical junction lithographic dimensions (<NUM> meter (m) distance versus a <NUM> nanometer (nm) feature size). However, this assumption has been found to be incorrect in multiple experiments. Particularly, for technologically-relevant junction fabrication, evaporation typically originates from a point source, while the sample must be considered as an extended target. The results of several experiments have also found the variation in total tilt angle to be predictable. Therefore, embodiments of the present invention have been designed and implemented as methods to correct the systematic variability in junction area from shadow evaporation across an extended sample. Critical current (Ic) of a Josephson junction is best predicted by the area of the tunnel junction (for a given oxidation condition). Embodiments of the present invention provide methods to correct the area variability induced by the shadow mask tilt angle. Correction of the shadow mask tilt angle can include a set of design (layout), lithographic, and/or process steps. For example, the undercut of the resist as implemented in design can be corrected for position on the wafer, type of shadow mask technique, and sample size (amount of repeated features on the wafer). The feature sizes implemented in design can also be corrected with the same considerations. Alternatively or complementarily with design, the lithographic pattern can include an algorithm (in addition to others, such as optical proximity correction (OPC)) to correct the exposure of the undercut and the feature size under the same considerations along with accounting for the choice of resist thickness and layers. In conjunction with the previous two types of corrections (design and lithographic), the tilt and rotation angles can be corrected to produce the greatest uniformity across the extended target during evaporation, taking into account evaporated film thicknesses as well, which constitutes a process correction. This methodology can be extended to other types of tunnel junctions with similar requirements and can be automated in design and/or lithography (for fixed process parameters), thereby providing a path for large-scale processing.

Turning now to a more detailed description of aspects of the present invention, <FIG> depicts a perspective view of fabricating Josephson junctions (JJs) according to embodiments of the present invention. For simplicity, three lithographic patterns/features <NUM> (left, center, and right pattern) are shown in <FIG>, and each lithographic feature <NUM> results in a die <NUM> (e.g., left die <NUM>, center die <NUM>, and right die <NUM>). A die <NUM> may also be referred to as a chip <NUM>. <FIG> is a top view of the left die according to embodiments of the present invention. <FIG> is a cross-sectional view of the left die according to embodiments of the present invention. <FIG> is a top view of the center die according to embodiments of the present invention. <FIG> is a cross-sectional view of the center die according to embodiments of the present invention.

A resist layer <NUM> is deposited on a substrate <NUM>. The resist layer <NUM> can be a single or bilayer resist, can include one or more underlayers, such as an anti-reflective coating (ARC), a planarizing layer, or hardmask materials, or can be another stack including a resist, as understood by one skilled in the art. In some implementations having a bilayer resist, a bottom resist layer <NUM> is deposited on the substrate <NUM>, and the top resist layer <NUM> is formed on the bottom resist layer <NUM>. The resist layer <NUM> is patterned in an exemplary shape of the lithographic feature <NUM>, and for explanation purposes, the shape of <NUM> is a trench. In some implementations, the resist layer <NUM> can be patterned with a lithographic feature <NUM>, for example, to have a Manhattan crossing of trenches that expose the substrate <NUM> as understood by one skilled in the art.

The substrate <NUM> can be a wafer on a wafer stage <NUM>, and the wafer stage holds and moves the wafer <NUM> substrate during the fabrication as understood by one skilled in the art. The terms sample and wafer are used interchangeably. An evaporation source <NUM> is used to deposit a film layer <NUM>, such as a superconducting metal. In shadow-masking techniques, the sample <NUM> and source <NUM> are tilted relative to each other. This is usually accomplished by tilting the sample stage <NUM> while keeping the source <NUM> fixed. The sample <NUM> is also aligned relative to the stage <NUM> so that the evaporation can occur along an opening in the resist <NUM> and <NUM>, usually along the long direction of the trench. The typical distance L between the source <NUM> and sample <NUM> is (relatively) long, e.g., <NUM> meter (m) (called "throw"). A chip that is at a distance that equals <NUM> inch (<NUM> inch = <NUM>) from the center of the stage <NUM> has an angle deviation of <NUM> ° away from the direct line of sight from the evaporation source <NUM> (geometrically), as shown for example in <FIG>.

As an example scenario for explanation purposes, the typical resist is a bilayer. For example, the thickness of the bottom resist layer <NUM> used for undercut (among possible other purposes) can be about <NUM> in the z-axes and the thickness of the top resist layer <NUM> can be about <NUM>. The total bilayer resist thickness can be about <NUM>. For the chip that is about r = <NUM>" away from the center of the stage <NUM>, the <NUM>° sideway evaporation will displace the pattern by <NUM> × Tan(<NUM>°) ~ <NUM> from the right resist edge of <FIG>, by <NUM> × Tan(<NUM>°) ~ <NUM> from the left resist edge of <FIG>, and shrink its width (for the feature on the left die <NUM> or right die <NUM>) in the x-axis by a net of <NUM> × Tan(<NUM>°) ~ <NUM>. This is a negligible offset for <NUM> micron (µm) features, corresponding to <NUM>% of the <NUM> width, but is non-negligible for <NUM> features (such as lithographic features <NUM>), corresponding to <NUM>% of the <NUM> width. As such, the shrinking of the trench opening in the left and right features <NUM> increases linearly with distance to the center for larger samples (as long as r«L). In the example above, the feature width of film <NUM> is reduced from <NUM> in the center die <NUM> as shown in <FIG> to <NUM> (<NUM>%) in the left die <NUM> in <FIG>. The error will increase by roughly <NUM>% for every inch away from the center of the stage <NUM>. In other words, the same reduction in film width of film <NUM> in the x-axis will occur for the right die <NUM>, and any other dies <NUM> inch away from the center. This reduction in film width of evaporated film <NUM> increases further away from the center.

During evaporation from the evaporation source <NUM> with respect to the left die, the superconducting material is deposited on top of the top resist layer <NUM> as a top deposit layer <NUM>, deposited on the side of the top resist layer <NUM> as a sidewall deposit <NUM>, and deposited in the opening of the top and bottom resist layers <NUM> and <NUM> as film layer <NUM> with width of <NUM> (as depicted in <FIG>). However, there is no sidewall deposit <NUM> in the center die and the film layer <NUM> has a full width of <NUM>, as depicted in <FIG>. The downward arrows represent evaporation (i.e., deposition) of the superconducting material from the evaporation source <NUM>. For simplicity, no top deposit <NUM> is shown in top views of <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>.

Non-limiting examples of suitable materials for the substrate <NUM> include Si (silicon), strained Si, high-resistivity Si, float-zone Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, III-V materials, Al<NUM>O<NUM> (sapphire, corundum), SiO<NUM> (quartz), etc..

The pattern in the resist layers <NUM> and <NUM> can be achieved by lithographic patterning which is followed by development of the resist layers <NUM> and <NUM>. In one case, the patterning of the trenches can be by photolithographic patterning which patterns the resist <NUM>, <NUM> on the substrate <NUM>, and the development process can be, for example, with a tetramethylammonium hydroxide (TMAH) or solvent developer. Additional developers are generally known in the art. The pattern of trenches in the resist layers <NUM> and <NUM> can alternatively be performed by lithographic patterning and followed by an etching. In one case, the patterning of the trenches can be by photolithographic patterning that exposes portions of the resist <NUM> and <NUM> on the substrate <NUM>, and the etching process can be, for example, a wet or reactive ion etching process that removes exposed portions of the resist <NUM> and <NUM> in order to form desired patterns discussed herein.

Additionally, it should be noted that junctions in embodiments of the invention can be made with a single step of lithography. By not having multiple steps of lithography, embodiments of the present invention do not need to remove the resist or perform lift off in between evaporation steps, and then spin resist again and expose another lithographic pattern. Rather, embodiments of the present invention are specifically designed to be used with a single patterning step and multiple evaporations/oxidations done without breaking vacuum in the same evaporator. At least <NUM> types of corrections to be described further can be implemented for a single shadow mask lithographic step. Additionally, it should be understood that any material on top of the resist layers <NUM> and <NUM> will eventually be lifted off when the resist layer <NUM> and <NUM> are removed except where noted otherwise. Likewise, it should be understood that any material attached only to the sidewall of the resist layer <NUM> and <NUM>, as opposed to being attached to another surface (such as the substrate <NUM> or another evaporated film which is anchored on the surface), will eventually be lifted off when the resist layers <NUM> and <NUM> are removed except where noted otherwise. It should be understood that lift off is a way to finish the device. Lift off can be performed by using a solvent, such as Dow® Microposit™ Remover or acetone, to remove the resist layer at the end, along with any materials that are attached to the resist but nothing else. One skilled in the art understands how to perform lift off.

A photoresist is a light-sensitive material. A positive resist is a type of photoresist in which the portion of the photoresist that is exposed to light becomes soluble to the photoresist developer. The unexposed portion of the photoresist remains insoluble to the photoresist developer. In a complementary manner to positive photoresist, a negative photoresist is a type of photoresist in which the portion of the photoresist that is exposed to light becomes insoluble to the photoresist developer. The unexposed portion of the photoresist is dissolved by the photoresist developer.

Additionally, embodiments of the present invention can utilize electron-beam lithography (often abbreviated as e-beam lithography) which is the practice of scanning a focused beam of electrons to draw custom shapes (i.e., exposing) on a surface covered with an electron-beam-sensitive film called an electron-beam (or e-beam) resist. The electron beam changes the solubility of the electron-beam resist, enabling selective removal of either the exposed or non-exposed regions of the resist by immersing it in a developer (e.g., a specific solvent). The purpose, as with photolithography, is to create very small structures in the resist that can subsequently be transferred to the substrate material, often by etching or deposition. Non-limiting examples of suitable electron-beam resists include Poly(methyl methacrylate) (PMMA), which is a type of positive electron-beam resist, and Hydrogen silsesquioxane (HSQ), which is a type of negative electron-beam resist. Analogous to photoresist, a positive electron-beam resist is a type of resist in which the portion of the resist that is exposed to the electron beam (as opposed to light) becomes soluble to the electron-beam resist developer. The unexposed portion of the electron-beam resist remains insoluble to the electron-beam resist developer. On the other hand, a negative electron-beam resist is a type of resist in which the portion of the resist that is exposed to the electron beam (as opposed to light) becomes insoluble to the electron-beam resist developer. The unexposed portion of the electron-beam resist is dissolved by the electron-beam resist developer. Other methods for performing e-beam lithography, for example but not limited to using lift off resist (LOR) or electron-beam resist bilayers, are understood by one skilled in the art.

Using the example scenario, non-limiting examples for several types of corrections are discussed herein. For combinations of multiple corrections, one can build a more specific model. There can be other corrections that are within the scope of the present invention, solely defined by the claims, but not explicitly discussed. Custom correction models can be built using the ideas presented. In the example scenario, provided are area correction methods for shadow evaporations, and designers apply it specifically to Josephson junctions used in quantum computing, where the critical current (Ic) of the junction is sensitive to the area (and oxide or barrier thickness) of the junction. The discussed corrections specify the pattern/dose adjustments needed to achieve the desired feature size/area. This can be implemented in a way that does not necessarily preserve the exact (original) position/coordinates of the structure (within a die). Alternatively and additionally, it can also be implemented in a particular way that does preserve the feature coordinates (also within a die, optional).

Automated corrections can be implemented at the post processing or fracture stage, either in house (e.g., at mask design shops) or in commercial packages, such as CATS or Beamer. For explanation purposes and ease of understanding, the corrections are categorized into the following non-limiting categories:.

Positional tilt corrections discussed herein address corrections along the x or y axis, and any combination thereof can be a vector decomposed into these <NUM> component corrections (i.e., x and y axes).

A single sidewall deposit correction requires <NUM> evaporation steps. Multiple sidewall deposit corrections (for <NUM> or more evaporation steps) in the same trench could require detailed considerations in accordance with embodiments of the present invention, by which a custom model can be generated.

Flashing corrections could require a detailed quantitative understanding of the developed resist profile for the particular process. Possible solutions/corrections include: increasing the available undercut such that flashing does not (or only minimally) occur by undercut engineering, and/or locally correcting the pattern or dose (as discussed in positional corrections) to compensate for reduced feature size due to sidewall flashing.

For explanation purposes, subheading and subtitles are utilized to ease understanding and not for limitation. As noted above, the example scenario explained depicts differences between the center die <NUM> and the left die <NUM> along with the particular corrections that are provided. It should be appreciated that the corrections can be made to dies <NUM> in any location in an array of dies (e.g., hundreds or thousands) on the wafer <NUM> without undue experimentation, according to embodiments of the present invention.

Test case 1A is depicted as <FIG>, <FIG>, and can be corrected using pattern and dose corrections. In this example, the designers correct the pattern exposed on the left such that the developed channel becomes wider and the evaporation on this left die results in <NUM> film width as depicted in <FIG>.

In <FIG>, the positional tilt angle θ = Tan-<NUM> (r/L), where r is the distance between the evaporation target on the sample and the stage center, and L is the distance between the stage center and the evaporation source. For r = <NUM> inch = <NUM> millimeters (mm) from center of the stage <NUM> (which is the center of the wafer <NUM>) to the evaporation target on the sample/wafer <NUM>, and for L = <NUM> = <NUM> from the evaporation source <NUM> to the center of stage <NUM> (i.e., to the wafer <NUM>), the positional tilt angle θ = <NUM>°. By construction, θ = <NUM> at the center of the stage <NUM> (which is the center of the wafer <NUM>). The left die <NUM> (i.e., left lithographic feature) has positional tilt because the left die <NUM> is not positioned at the center of the wafer <NUM>/stage <NUM>, and the evaporation source <NUM> is aligned directly to the center of the wafer <NUM>/stage <NUM>. The left die <NUM> is to the left by <NUM> inch (in this example), and therefore, the positional tilt angle θ = <NUM>° relative to the evaporation source <NUM>. As shown in <FIG> for the left die, the trench is <NUM> wide and a film is to be deposited on the substrate <NUM> with a <NUM> width just like the center die in <FIG> (at the center of the wafer <NUM>/stage <NUM>). However, because the left die is <NUM> inch away from the center of the wafer <NUM>/stage <NUM> as shown in <FIG>, shadow mask evaporation by the evaporation source <NUM> results in a sidewall deposit <NUM> which reduces the width of trench (in the x-axis) such that the depositing superconducting film <NUM> has a width of <NUM> in the left die in <FIG> instead of the desired <NUM> width (of film <NUM>) in the center die in <FIG>. This type of problem is referred to as positional tilt, which is corrected with a positional tilt width correction wpos (to be added to the desired total width) in accordance with embodiments in the invention. Positional tilt can be corrected for by using pattern corrections and dose corrections. For positional tilt corrections, sidewall deposit corrections, and sidewall flashing corrections, a software tool <NUM> (having the logic and algorithms) in <FIG> is configured to make each of the corrections in integrated circuit mask layout, lithographic equipment, and shadow mask equipment, in accordance with embodiments of the invention. Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, semiconductor layers, superconducting layers, etc., that make up the components of the integrated circuit.

First Solution 1A (to Test case 1A): For pattern corrections, with respect to the pattern feature size of the lithographic feature <NUM> (i.e., the trench), the designers widen the resist opening (i.e., widen the trench) on the left die only to result in <NUM> width of the film <NUM> in <FIG> by local design modification in the layout (e.g., layout <NUM>) (which can be performed by software tool <NUM>). In this example, the positional tilt width correction implies a wpos = <NUM> wider opening of the lithographic feature <NUM> (i.e., trench) which will result in a <NUM> wide superconducting film <NUM> in <FIG>, and this is a local design adjustment because the adjustment only occurs to the left die <NUM> and not the center die <NUM>. Analogously, the same positional tilt correction is made to the right die <NUM> (although this correction is not shown). The software tool <NUM> can be configured to implement a single unique solution for each die on the wafer <NUM>, and smaller corrections can be introduced within a die. According to embodiments of the present invention, this solution can be implemented manually by the designer in the layout <NUM> (which may or may not utilize software tools <NUM>) and/or the solution can be implemented by a software algorithm of the software tool <NUM> after layout <NUM> of the desired pattern has been designed. Additionally, the solution can be implemented instead by the lithographic patterning tool <NUM> depicted in <FIG>. The lithographic patterning tool <NUM> is lithographic equipment that forms a feature or pattern in one or more layers, as understood by one skilled in the art. In one implementation, the lithographic patterning tool <NUM> could be integrated with, include, and/or be instructed by the software tool <NUM>.

Second Solution 1A (to Test case 1A): For pattern dose corrections, a larger exposure dose results in a wider feature for positive tone resists (while a smaller exposure dose results in a wider feature for negative tone resists). By locally (i.e., die by die) adjusting the pattern dose (as can be done for e-beam lithography or a stepper/scanner), the feature width of feature <NUM> can be changed to the corrected size (i.e., the trench is changed to be <NUM> wide for the left die (and right die)). This can be accomplished using the software tool <NUM> which can be connected to and/or integrated with the fabrication equipment for e-beam lithography and/or a stepper/scanner. This solution can utilize the same pattern design (which is the original layout <NUM> of the lithographic features <NUM> in the layers <NUM>, <NUM>, <NUM>) and same mask for the original layout of the lithographic features, but requires a local dose adjustment. A local dose adjustment means that each die <NUM> (each feature <NUM>) can receive a different amount of exposure based on the die's distance from the center in order to create a larger width for the trench (i.e., lithographic feature <NUM>). Smaller corrections can be introduced within a die (for e-beam and other direct write lithography). As noted above, the solution can be implemented by a software algorithm (in the software tool <NUM>) after layout (a representation of the design). The solution can be implemented instead by the lithographic patterning tool <NUM>, which can be instructed by, for example, the software tool <NUM>, and/or the software tool <NUM> can be integrated with the lithographic patterning tool. The conversion factor from dose change (i.e., the amount of exposure) to feature size change needs to be calibrated for a specific tool (e.g., for e-beam lithography) and resist stack (the type of resist layers <NUM> and <NUM> and developer being utilized), which is understood by one skilled in the art without undue experimentation in light of the teachings of embodiments of the present invention. As noted herein, the feature <NUM> (such as the trench) is patterned in the resist layer <NUM> and <NUM> to have the desired width in the x-axis.

For first and second solutions 1A, further detail regarding the width correction of the lithographic pattern/feature <NUM> for shadow evaporation is discussed. The positional tilt width correction is wpos = ttop x Tan(θ), where ttop is the nominal thickness of the top resist layer, and θ is the positional tilt angle relative to the vertical z direction. This expression is a geometrical consequence of the top layer <NUM> being engineered to be wider than bottom resist layer <NUM>, therefore defining the effective opening of resist (in the absence of previous sidewall deposits or flashing, as will be discussed). In this example, the top resist layer is layer <NUM> with thickness ttop = <NUM> in z-axes. The tilt shown on the left die (θ=<NUM>°) is for a r = <NUM>" location to the left from the stage center in the x direction, and a L = <NUM> distance to the evaporation source <NUM> (aligned to the stage center), when there is no additional tilt about the y direction (in xz plane), while the feature <NUM> extends in the y direction. Accordingly, the positional tilt width correction wpos = <NUM> x tan (<NUM>°) ~ <NUM>. Therefore, an additional <NUM> was added to the width of the trench (feature <NUM>) using the first solution 1A (designed wider at left location) or second solution 1A (exposed with larger dose at left location than the center location), thereby resulting in the trench with a width of <NUM>.

If there is an additional tilt about the y-axis (in the xz plane), the total tilt on the left die will be the y tilt +/positional tilt, accordingly, though the exact value of the positional tilt angle may change (especially for large stage tilt angles), as detailed below; if stage <NUM> is tilted about the y-axis from x to z in the xz plane, the positional tilt θ is to be added to the stage tilt β, as shown in <FIG>. However, if stage <NUM> is tilted in the y-axis from z to x in the xz plane instead, the positional tilt θ is to be subtracted from the stage tilt β. It is noted that x and y directions are arbitrary in the figures. Although the evaporation (for deposition of film <NUM>) is shown on the z-axis, the evaporation direction can be along the x direction, for example (perpendicular to the feature). The axes shown represent a right-handed Cartesian coordinate system. The total tilt varies continuously across a wafer <NUM>. Discretization of correction is arbitrary and only limited by software and error tolerances for a given application. Correction can vary along a same feature (street or avenue) if necessary (such as if the feature is very long, for example, and the error tolerance requires it).

For illustrative reasons, the positional tilt θ will be shown as being independent of the stage tilt β. This is true as long as the distance r between the center of the stage and the position on the wafer (<NUM> inch) is much smaller than the distance L between the (aligned) center of the stage and the evaporation source (<NUM> meter, aligned to each other), and as long as the stage tilt β is reasonably small (<NUM>° or less). Otherwise, the generalized positional tilt α for a stage tilt β about the y-axis in the xz plane is given by the formula α = Tan-<NUM> [(r/L)Cos(β)/[<NUM>+(r/L)Sin(β)]]. For β = <NUM>°, α= Tan-<NUM> (r/L) = θ, by construction (no stage tilt, therefore total tilt θ' = α + β = α). For β = <NUM>°, then α = <NUM>°, which corresponds to a completely vertical stage (there is only stage tilt, therefore total tilt θ' = α + β = β). For small stage tilt β (less than <NUM>°) and r<<L, α = Tan-<NUM> [(r/L)Cos(β)] ~ Tan-<NUM> (r/L) = θ, which makes the total tilt θ' = a + β ~ θ + β. The correction can utilize approximate formulas or the precise analytical expressions depending on the degree of precision required. It should also be noted that the stage tilt or positional tilt only matters for the purpose of area correction of the overlap between two deposited films if the area of the overlap is modulated by either type of tilt. In this example, if a stage tilt is performed about the x-axis instead, in the yz plane from y to z, the generalized positional tilt becomes independent of the stage tilt for trenches <NUM> that are parallel to the yz plane. This statement is true as long as the tip of the trenches <NUM> do not determine the overlap area (i.e., the overlap area is determined by a crossing away from the tips of the features such as trenches <NUM>).

Test case 1B is depicted in <FIG>, <FIG>, and can be corrected analogously using pattern and dose corrections as discussed above in test case 1A. In the test case 1B, the designers correct the pattern exposed on the top die such that the developed channel becomes wider in the y-axis and the evaporation on this top die results in a <NUM> film width (not shown but analogous to <FIG>). The test case 1B in <FIG> is the same as test case 1A except the stage <NUM> is rotated <NUM>° relative to test case 1A. This means that the parameters and layers are the same in both <FIG> and in <FIG> depicts lithographic patterns/features <NUM>, and each lithographic pattern <NUM> results in a die <NUM> (e.g., top die <NUM>, center die <NUM>, and bottom die <NUM>). <FIG> is a top view of the top die according to embodiments of the present invention. <FIG> is a cross-sectional view of the top die according to embodiments of the present invention. <FIG> is a top view of the center die according to embodiments of the present invention. <FIG> is a cross-sectional view of the center die according to embodiments of the present invention.

Test case 1B utilizes the same solutions as test case 1A except the solutions are in the other direction, i.e., the wpos = <NUM> increase is in the y-axis by pattern design and/or dose. For example, instead of the width increasing in the x-axis as depicted in <FIG>, the width will increase in the y-axis with respect to <FIG>, <FIG> because of the narrower projection of the deposited film through the opening of the top resist layer <NUM>.

Test case 1C is depicted as <FIG>, <FIG>, and can be corrected using pattern and dose corrections as discussed above. In this example, the designers correct the pattern exposed on both the left and center dies such that the developed channel becomes wider and the evaporation on the left and center dies each result in <NUM> film width as depicted in <FIG>.

<FIG> depicts a perspective view of fabricating Josephson junctions according to embodiments of the present invention. <FIG> is similar to <FIG> and <FIG> except for different angles. <FIG> depicts a top view of the left die in <FIG> according to embodiments of the present invention. <FIG> depicts a cross-sectional view of the left die in <FIG> according to embodiments of the present invention. <FIG> depicts a top view of the center die in <FIG> according to embodiments of the present invention. <FIG> depicts a cross-sectional view of the center die in <FIG> according to embodiments of the present invention. Test case 1C addresses stage tilt of the stage <NUM>. This means that the stage <NUM> holding the wafer <NUM> has been tilted, and the amount/angle of stage tilt is β. To illustrate stage tilt, there are two sets of axes. The x, y, z axes as used herein and the x', y, z' axes representing the stage tilt. For explanation purposes, the state tilt β is about the y-axis from the x-axis to the z-axis in the xz plane. In this example, the stage tilt β = <NUM>°. There is already a positional tilt θ = <NUM>° for the left die with respect to the center die prior to tilting the stage, and the positional tilt θ is based on the r = <NUM> inch separation between the lithographic features <NUM> (e.g., from the center of one trench to the center of the nearest trench) all of which is for a distance of L = <NUM> from the evaporation source <NUM> to the wafer <NUM>/stage <NUM>. Since the stage tilt β = <NUM>° is reasonably small (less than <NUM>°) while r«L, the generalized positional tilt α can be approximated by the positional tilt θ as α ~ θ = <NUM>° which is independent of the stage tilt β, and the total tilt will be taken as the sum or subtraction of the positional and stage tilts for simplicity depending on the direction of the stage tilt.

For a total tilt angle θ' with stage tilt β about the y-axis from the x-axis to the z-axis in the xz plane, the designers add positional tilt α to stage tilt β for left-of-center, and the designers subtract positional tilt α from stage tilt β for right-of-center (although the right die is not depicted, for simplicity). A closed formula for the total tilt angle θ' = β ± α = Tan-<NUM> [[Sin(β)±(r/L)]/Cos(β)]. As already discussed, the generalized positional tilt may not vary significantly with stage tilt, such that α ~ θ as long as the stage tilt β is reasonably small and the distance r on the wafer to its center is much smaller than the distance L to the evaporation source.

<FIG> depict the lithographic pattern/feature <NUM> with a wider pattern. <FIG> is a top view of the left die according to embodiments of the present invention. <FIG> is a cross-sectional view of the left die according to embodiments of the present invention. <FIG> is a top view of the center die according to embodiments of the present invention. <FIG> is a cross-sectional view of the center die according to embodiments of the present invention.

As discussed herein, to create the wider pattern for the trench (feature <NUM>) in the x'-axis, the designers can design a wider trench at each location of the die <NUM> (first solution 1A) and/or expose (the resist) with a larger dose at each location of the die <NUM> (second solution 1A). A larger dose can be with a greater beam intensity (i.e., increased magnitude) and/or longer exposure time (as compared to what is needed if the positional corrections were not being made), and this causes a wider trench pattern in the top resist <NUM>. To determine the left correction width for the left die <NUM> in <FIG>, the left positional tilt width correction wpos = ttop × Tan(θ'), where ttop is the nominal thickness of the top resist layer, and θ' = α + β ~ θ +β is the total tilt. This means the left positional tilt width correction wpos = <NUM> × tan (<NUM>°) ~ <NUM>, because θ' ~ θ + β = <NUM>° + <NUM>° = <NUM>° for the left die. The thickness of the top resist layer <NUM> is ttop = <NUM>. The generalized positional tilt in this test case equals α = <NUM>°, and the total tilt θ' = α + β = <NUM>° + <NUM>° = <NUM>°, resulting in a positional tilt width correction wpos = <NUM> × Tan (<NUM>°) ~ <NUM>. Because using θ or a results in the same correction of <NUM> (approximately), this validates the chosen approximation of α ~ θ.

To determine the center positional tilt width correction wpos for the center die <NUM> in <FIG>, the center wpos = ttop x Tan (θ') = <NUM> × Tan (<NUM>°) ~ <NUM>, where α = θ = <NUM> for the center die and θ' = β.

As seen in <FIG>, the trench opening is increased by wpos = <NUM> to be <NUM> for the left die, which results in a deposited film <NUM> of <NUM> in the x'-axis instead of <NUM> in <FIG>. Similarly, as seen in <FIG>, the trench opening is increased by wpos = <NUM> to be <NUM> for the center die, which results in a deposited film <NUM> of <NUM> in the x'-axis instead of <NUM> in <FIG>. It is noted that before the correction, <FIG> shows the film <NUM> with a width of <NUM> in the x'-axis when a <NUM> width was originally designed and <FIG> shows the deposited film <NUM> with a width of <NUM> in the x'-axis when a <NUM> width was originally designed. The solutions implemented by the designers have corrected for both the positional tilt α and the stage tilt β.

A Josephson junction (JJ) produced by the Dolan bridge process with positional tilt corrections is described. Two trenches <NUM> made into resist are separated by a small resist gap along the y axis such as in <FIG>. Both trenches are aligned with each other in their long dimensions along the y axis. The resist gap may be <NUM>. The resist gap contains only top resist layer <NUM> and no bottom resist layer <NUM>, and this resist gap is supported on two opposite sides in the x axis by top resist layer <NUM> which contains bottom resist layer <NUM> under it. The resist gap with suspended top resist is known as a Dolan bridge. An evaporation is then performed along the y axis with a tilt about the x axis from z to y in the yz plane. This tilt can be <NUM>° in some implementations. First film <NUM> will then deposit towards the top trench and under the Dolan bridge. Then, after an oxidation step without breaking vacuum, an evaporation is performed along the y axis with a tilt about the x axis from y to z in the yz plane. This tilt can be <NUM>° in some implementations. Second film <NUM> will then deposit towards the bottom trench and under the Dolan bridge. The respective thicknesses of the top and bottom resist layers may be designed to allow the oxidized first film <NUM> to overlap with the second film <NUM>, creating a tunnel junction. If the trenches are in die <NUM> on the left, with r = <NUM> inch and L = <NUM>, there will be a positional tilt of <NUM>°. If the top resist layer has a thickness ttop = <NUM> and the bottom resist layer has a thickness tbot = <NUM>, the positional tilt will reduce the width of the first and second film <NUM> by <NUM>, as seen in <FIG>. By imposing a positional tilt width correction wpos = <NUM> of additional width on the trench widths in left die <NUM>, the area of the overlap will be corrected and will have the same area as that of the overlap achieved in center die <NUM> (without a correction, since by construction, there is no positional tilt in the center).

The sidewall deposit correction is to correct a channel (e.g., trench) that contains a sidewall deposit from a previous shadow evaporation in order to result in a desired <NUM> film width for the deposited film <NUM> in this example. Manhattan junction fabrication by shadow evaporation is a non-limiting example where sidewall deposit correction is important. <FIG> and <FIG> shows perspective views of the source evaporator <NUM> relative to the wafer <NUM>/stage <NUM>, and these views are not repeated but can be referenced herein.

Test case 2A is depicted in <FIG>, and the solution is depicted in <FIG>.

Solution 2A (to test case 2A) is to calculate how much street width (e.g., the width of the trench) was reduced by the expected width of sidewall deposit from previous evaporation(s) that generate the sidewall deposits. The sidewall width correction wside = Σi [tnom,i x Sin(θ'i)], where tnom,i is the nominal thickness of previous evaporation of index i which landed on the sidewall, θ'i is the total tilt angle relative to the vertical z direction of the evaporation of index i used to create the respective sidewall deposit of index i, and Σi is the sign for summation over all indices i (in which an evaporation landed on the sidewall). As noted above, the total tilt angle θ' for a given evaporation includes both a stage tilt angle β and a generalized positional tilt α (which may be approximated by the positional tilt θ for β < <NUM>° and r«L) such that θ' = α + β. The nominal thickness of an evaporation is a calibrated value which is tracked in real time by a device such as a crystal monitor mounted in the vacuum chamber within an evaporator. It corresponds to the thickness of a given material when deposited onto a flat surface without stage tilt.

For evaporations parallel to the reduced width street (e.g., <NUM>nd evaporation for Manhattan junctions), the designers increase the street width by the amount of sidewall width reduction, either by using pattern or dose corrections. This correction can be in addition to applicable tilt (both positional tilt and stage tilt) corrections (test case 1A, 1B, and 1C), but multiple such corrections are additive to first approximation. In particular, the geometry of each sidewall profile and how each deposit attaches to the sidewall must be taken into account in the model used to apply the corrections.

For subsequent evaporations along the same axis as previous evaporations (e.g., <NUM>nd evaporation for Dolan bridge junctions), the need for a sidewall correction depends on how the subsequent evaporation affects the overlap area between the two or more films.

For sequential evaporations where there is need for a sidewall correction, the total width correction wtot is the result of the addition of the sidewall width correction wside (resulting from previous evaporations) with other types of correction for the subsequent evaporation, such as the positional tilt width correction wpos (or flashing width correction wflash), with minor modifications. For a positional width correction in the subsequent evaporation, the total width correction wtot = wside + teff x Tan(θ'), where teff is the effective thickness of the top layer (modified by the sidewall deposit(s)), and θ' is the total tilt angle relative to the vertical z direction. Once there is sidewall deposit interfering with the shadow evaporation, the effective thickness of the top layer is not equal the top resist layer. The effective thickness depends on the angle of the sidewall deposit evaporation(s), height(s), history of sidewall attachment, and direction of the new evaporation.

<FIG> depicts a top view of the center die according to embodiments of the present invention. <FIG> depicts a cross-sectional view of the center die according to embodiments of the present invention. The positional tilt is θ = <NUM> by construction in the center die, and the stage tilt β from a previous evaporation is about the y-axis from x to z in the xz plane. All evaporation material lands on the top resist <NUM> at this angle with <NUM> opening and sidewall deposit nominal thickness of <NUM> (for example, for a Manhattan crossing). In the top view of <FIG>, evaporation material is not shown on the top, so as not to obscure the figure. The parameters are changed from above. In <FIG> and <FIG>, the thickness of the top resist layer <NUM> in the z'-axis is <NUM> and the thickness of the bottom resist layer <NUM> in the z'-axis is <NUM>. In <FIG>, a previous shadow evaporation (<NUM>st shadow evaporation) resulted in the sidewall deposit <NUM> with a nominal thickness of <NUM> in the direction of evaporation as defined along the original z-axis. Because of the previous shadow evaporation, the width of the trench opening (i.e., feature <NUM>) is reduced from <NUM> to <NUM>. The nominal thickness of the previous shadow evaporation (<NUM>st evaporation) is <NUM> in the evaporation direction (z direction) and performed at a <NUM>° evaporation angle relative to the vertical z direction as shown in <FIG> and <FIG>. The previous shadow evaporation leaves no film <NUM> deposited on sample <NUM> inside trench <NUM>. The previous shadow evaporation leaves film <NUM> deposited inside trenches <NUM> that are not shown and are at a right angle with the trenches <NUM> that are shown. For building a Manhattan junction, the designers must rotate the stage <NUM>° in the xy plane and next evaporate parallel to the trench (i.e., shadow evaporation is along the y-axis), resulting in an overlap of films <NUM> along trenches <NUM> that are shown and right angle trenches <NUM> that are now shown, at the intersections of the two types of trenches. Because there is no positional tilt in the center die, and the next evaporation is performed parallel to the trench <NUM>, there is only a sidewall correction to be applied as a consequence of the sidewall deposit <NUM> shown in <FIG>. The designers increase the width of the trench by <NUM> to get <NUM> deposited film <NUM> (not shown) into the trench in the center in the <NUM>nd evaporation. This can be achieved with design or dose correction as discussed above.

Originally, the trench opening is <NUM> before the <NUM>st shadow evaporation but will result in an <NUM> deposited film after the <NUM>st shadow evaporation in <FIG>. To determine the width of the deposited film for the <NUM>nd shadow evaporation, first the designers calculate the width reduction of the trench width measured by the opening of the top resist layer. This reduction is the same as the sidewall width correction wside = tnom x Sin(θ'), where tnom is the nominal thickness of the evaporation that landed on the sidewall, and θ' is the total stage tilt used to create the respective sidewall deposit. Since the generalized positional tilt in the center die is α = <NUM>, then θ' = α + β = β, where β is the stage tilt used to create the respective sidewall deposit. The designers obtain wside = tnom x Sin(β) = <NUM> x Sin(<NUM>°) = <NUM>. The width of the deposited film in the subsequent evaporation is then obtained by subtracting wside from the width of the opening, <NUM>, which results in a subsequent deposited film width of <NUM>. Therefore, the <NUM>nd shadow evaporation (subsequent, not shown) along the y-axis results in a deposited film with a width of <NUM>, because the trench opening has been effectively reduced to <NUM>. This reduction in width needs to be corrected for.

The solution is depicted in <FIG> is a top view of the center die according to embodiments of the present invention. <FIG> is a cross-sectional view of the center die according to embodiments of the present invention. Accordingly, the trench (feature <NUM>) is corrected to have a trench width of <NUM> in the x'-axis instead of <NUM> (in <FIG>), and this results in a deposited film (from a subsequent evaporation along the y axis, like layer <NUM> but not shown) with width <NUM> in <FIG> instead of <NUM> which as in <FIG>. Using the formula above, the deposited film width in <FIG> is determined by subtracting the same sidewall width correction wside = <NUM> from the width opening, <NUM>, resulting in a deposited film width of <NUM>.

Test case 2B is depicted in <FIG>, <FIG>, and <FIG>. <FIG> is a simplified top view of the stage <NUM> holding the sample <NUM>, without showing the evaporation source <NUM> although it is understood that the evaporation source is present. <FIG> is a top view of the left die of <FIG>. If there is positional tilt to any of the evaporations, those must be taken into account. In this example, the left die is <NUM> inch away left-of-center in the x direction, and this results in a <NUM>° positional tilt correction (i.e., positional tilt θ1 = <NUM>° of first evaporation) in the absence of a stage tilt. Additionally, when the stage <NUM> is tilted <NUM>° (stage tilt β1 = <NUM>° of first evaporation) about the y-axis from the x-axis to the z-axis in the xz plane, the generalized positional tilt α1 of the first evaporation at β1 = <NUM>° on that die becomes <NUM>° (i.e., generalized positional tilt α1 = <NUM>° of first evaporation). The sidewall width correction wside = <NUM> x Sin(<NUM>° + <NUM>°) ~ <NUM>, because the total stage tilt of the first evaporation is θ1' = α1 + β1 = <NUM>° +<NUM>°. As noted herein, the thickness (which is <NUM> in the example scenario) utilized in the calculation is the nominal thickness of the sidewall deposit <NUM> at the angle of evaporation that created the sidewall deposit <NUM>. Calculating <NUM> for the sidewall width correction wside means that the opening of the trench (feature <NUM>) would need to be <NUM> (which is an additional <NUM>) in order to deposit a film <NUM> (not shown) with a width of <NUM> for an evaporation directly along the trench (otherwise there will be a new positional tilt as will be described next). For a Manhattan crossing, there will be another trench <NUM> (not shown) which intersects the trench <NUM> of <FIG> at a right angle (<NUM>°, along the x-axis in <FIG>). At the intersection of the two trenches <NUM>, there can be an overlay. The evaporation that created the sidewall deposit <NUM> also deposited a film along the another trench <NUM> (which is at <NUM>°) that is not shown in <FIG> and is at a right angle to the trench <NUM> shown in <FIG>, and there will be an overlap of both films <NUM> (from first and subsequent evaporations) where both trenches intersect. An oxidation step can be performed without breaking vacuum prior to deposition along the trench <NUM> which is shown in <FIG>. This will create an overlay between the first film <NUM> from the first evaporation (not shown), and the subsequent film <NUM> from the subsequent evaporation.

<FIG> is a simplified top view of the stage <NUM> in <FIG> with a <NUM>° rotation of the stage <NUM> about the z-axis from y to x in the xy plane. <FIG> is a top view of the top die shown in <FIG>. After the <NUM>° rotation of the stage <NUM> about the z-axis from y to x in the xy plane, the left die of <FIG> becomes the top die of <FIG>.

<FIG> is a simplified top view of the stage <NUM> holding the wafer <NUM> as in <FIG>. <FIG> is a top view of the rotated and tilted left die of <FIG>, as shown by the tilted axes (y'and z'). <FIG> is a cross-sectional view of the rotated and tilted left die of <FIG>. In <FIG>, a subsequent evaporation is performed with a subsequent stage tilt of β2 = <NUM>° about the x-axis from the y-axis to the z-axis in the yz plane, resulting in the axes y' and z' after the stage tilt, as shown in <FIG>. The subsequent stage tilt of <NUM>° for the subsequent evaporation has no effect on the generalized positional tilt because it is performed along the trench <NUM> of <FIG>. An overlay is created with the first film deposited during the first evaporation into the another trench <NUM> which intersects the trench <NUM> of <FIG> at a right angle (the another trench <NUM> is not shown). This overlay is a Manhattan crossing, the overlay area of which will require both a sidewall correction and a positional tilt correction. Because the positional tilt for an evaporation along the trench <NUM> is not affected by the stage tilt angle about the x-axis, the generalized positional tilt for the subsequent evaporation a2 is equal to the positional tilt of the subsequent evaporation θ2 = <NUM>° for r = <NUM>" and L = <NUM>. The total tilt of the subsequent shadow evaporation becomes θ2' = θ2 =<NUM>°. For a top resist thickness (for top resist layer <NUM>) ttop = <NUM>, the positional tilt correction from the resist alone would naively be ttop x Tan(θ2') = <NUM> x Tan(<NUM>°) ~ <NUM>, but this turns out to be incorrect because the opening of the trench is reduced from ttop to a value teff as a result of the sidewall deposit <NUM>. Instead, one has to consider the deposit profile as further depicted in <FIG>, and <FIG>.

The effective opening of the trench (feature <NUM>) at the top teff for an evaporation of a film <NUM> landing on the sample <NUM> in the space under the sidewall deposit <NUM> (as in <FIG>) depends on the lower edge (i.e., anchoring point) of the previous sidewall deposit <NUM> on the right and the top edge of the top resist layer <NUM> on the left. Utilizing geometry, the lower anchoring point of the sidewall deposit <NUM> is related to the distance from the top resist layer top edge on the left by wtrench = tanchor × Tan(θ1'), where wtrench is the horizontal distance between anchoring point on the right and the opposite top resist layer side, tanchor is the vertical distance between the anchoring point of the sidewall and the top resist layer top edge on the left, and θ1' is the total tilt of the evaporation that created the sidewall deposit (first evaporation). In <FIG>, there is only one sidewall deposit, so that wtrench = w = opening of the trench = <NUM> (it may differ from the opening of the trench if there are multiple sidewall deposits). Since θ1' = <NUM>° in the first evaporation (taking into account the positional tilt of the first evaporation), this results in tanchor = wtrench / Tan(θ1') = <NUM> / Tan(<NUM>°) ~ <NUM> below the top resist layer top edge on the right. The lower edge of the previous sidewall deposit <NUM> is at a height = tnom × Cos(θ1') = <NUM> × Cos(<NUM>°) ~ <NUM> above the anchoring point. The projection of the subsequent evaporated film through the resist opening, taking into account the sidewall deposit, is determined by the height difference teff between the top edge of the top resist layer on the left and the lower edge of the previous sidewall deposit on the right. Therefore, teff = <NUM> - <NUM> = <NUM>. Finally, the sidewall-corrected positional tilt correction of the opening of w = <NUM> is wpos = teff × Tan(θ2') = <NUM> × Tan(<NUM>°) ~ <NUM>, where the total tilt of the subsequent evaporation is θ2' = θ2 = <NUM>°. The total correction equals the sidewall correction plus the sidewall-corrected positional tilt correction, given by wtot = wside + wpos = <NUM> + <NUM> = <NUM>. This means that the trench opening (feature <NUM>) should be <NUM> to result in a <NUM> width film of the deposited film <NUM> in the subsequent evaporation (without correction, the effective width of the deposited subsequent film <NUM> is <NUM> - wside - wpos = <NUM> - <NUM> = <NUM>). The widening of the trench in the left die of <FIG> (which was rotated by <NUM>° after the first evaporation about the z-axis from y to x in the xy plane) for the purpose of correcting the width of the deposited film can be accomplished with pattern design or dose as discussed above.

Test case 2C is depicted in <FIG>, <FIG>, and <FIG>. <FIG> is a simplified top view of the stage <NUM> holding the wafer <NUM>, without showing the evaporation source <NUM> although it is understood that the evaporation source is present. <FIG> is a top view of the right die of <FIG>. In this example, the right die is <NUM> inch away right-of-center in the x direction, and this results in a <NUM>° positional tilt correction (i.e., positional tilt θ1 = <NUM>° of first evaporation) in the absence of a stage tilt. Additionally, when the stage <NUM> is tilted <NUM>° (stage tilt β1 = <NUM>° of first evaporation) about the y-axis from the x-axis to the z-axis in the xz plane, the generalized positional tilt a1 of the first evaporation at β1 = <NUM>° on that die becomes <NUM>° (i.e., generalized positional tilt a1 = <NUM>° of first evaporation). The sidewall width correction wside = <NUM> x Sin(-<NUM>° + <NUM>°) ~ <NUM>, because the total stage tilt of the first evaporation is θ1' = -α1 + β1 = -<NUM>° +<NUM>° = <NUM>°. The generalized positional tilt is subtracted from the stage tilt because it is right-of-center relative to the stage in the same manner as in <FIG>. As noted herein, the thickness (which is <NUM> in the example scenario) utilized in the calculation is the nominal thickness of the sidewall deposit <NUM> at the angle of evaporation that created the sidewall deposit <NUM>. Calculating <NUM> for the sidewall width correction wside means that the opening of the trench (feature <NUM>) would need to be <NUM> (which is an additional <NUM>) in order to deposit a film <NUM> (not shown) with a width of <NUM> for an evaporation directly along the trench (otherwise there will be a new positional tilt as will be described next). <FIG> is a simplified top view of the stage <NUM> in <FIG> with a <NUM>° rotation of the stage <NUM> about the z-axis from y to x in the xy plane <FIG> is a top view of the bottom die shown in <FIG>. After the <NUM>° rotation of the stage <NUM> about the z-axis from y to x in the xy plane, the right die of <FIG> becomes the bottom die of <FIG>.

Further regarding the test case 2C, <FIG> is a simplified top view of the stage <NUM> holding the wafer <NUM> as in <FIG>. <FIG> is a top view of the rotated and tilted right die of <FIG>, as shown by the tilted axes (y'and z'). <FIG> is a cross-sectional view of the rotated and tilted right die of <FIG>. In <FIG>, a subsequent evaporation is performed with a subsequent stage tilt of β2 = <NUM>° about the x-axis from the y-axis to the z-axis in the yz plane, resulting in the axes y' and z' after the stage tilt, as shown in <FIG>. The subsequent stage tilt of <NUM>° for the subsequent evaporation has no effect on the generalized positional tilt because the evaporation is performed along the trench <NUM> of <FIG>. An overlay is created with the first film deposited during the first evaporation into the another trench <NUM> which intersects the trench <NUM> of <FIG> at a right angle (the another trench <NUM> is not shown). This overlay is a Manhattan crossing, the overlay area of which will require both a sidewall correction and a positional tilt correction. Because the positional tilt for an evaporation along the trench <NUM> is not affected by the stage tilt angle about the x-axis, the generalized positional tilt for the subsequent evaporation α2 is equal to the positional tilt of the subsequent evaporation θ2 = <NUM>° for r = <NUM>" and L = <NUM>. The total tilt of the subsequent shadow evaporation becomes θ2' = θ2 =<NUM>°. The difference between cases 2B and 2C relies on the position of the die relative to the center only, while all stage tilts, rotation angles, and evaporated thicknesses remain the same.

Next, the cross-section will be considered again to calculate the total correction. The effective opening of the trench (feature <NUM>) at the top teff for an evaporation of a film <NUM> landing on the sample <NUM> in the space that is not under the sidewall deposit <NUM> (as in <FIG>, and unlike <FIG>) now depends on the top edge of the previous sidewall deposit <NUM> on the right and the bottom edge of the top resist layer <NUM> on the left. Utilizing geometry, the top edge of the previous sidewall deposit is at a height given by tnom × Cos(θ1') = <NUM> × Cos(<NUM>°) ~ <NUM> above the top edge of the top resist. The projection of the subsequent evaporated film through the resist opening, taking into account the sidewall deposit, is determined by the height difference teff between the top edge of the previous sidewall deposit <NUM> on the right and the bottom edge of the top resist layer <NUM> on the left. Therefore, teff = <NUM> + <NUM> = <NUM>. Finally, the sidewall-corrected positional tilt correction of the opening of w = <NUM> is wpos = teff × Tan(θ2') = <NUM> × Tan(<NUM>°) ~ <NUM>, where the total tilt of the subsequent evaporation is θ2' = θ2 = <NUM>°. The total correction equals the sidewall correction plus the sidewall-corrected positional tilt correction, given by wtot = wside + wpos = <NUM> + <NUM> = <NUM>. This means that the trench opening (feature <NUM>) should be <NUM> to result in a <NUM> width film of the deposited film <NUM> in the subsequent evaporation (without correction, the effective width of the deposited subsequent film <NUM> is <NUM> - wside - wpos = <NUM> - <NUM> = <NUM>). The widening of the trench in the left die of <FIG> (which was rotated by <NUM>° after the first evaporation about the z-axis from y to x in the xy plane) for the purpose of correcting the width of the deposited film can be accomplished with pattern design or dose as discussed above.

Test case <NUM> is depicted in <FIG>, <FIG>, and <FIG>. <FIG> depicts a view of the stage <NUM> and evaporation source <NUM> as discussed herein. <FIG> depicts a top view of the left die <NUM>. <FIG> depicts a cross-sectional view of the left die in <FIG>. An evaporation is projected far enough to the side (due to small resist undercut, high tilt, and/or both) that the deposited film <NUM> partly (and unintentionally) ends upon the undercut sidewall of the bottom resist <NUM> instead of the substrate <NUM>, which (further) reduces the width of the evaporated feature (i.e., film <NUM>) on the substrate <NUM>.

First Solution <NUM> is undercut engineering. Undercut engineering is configured to add/extend sublithographic shapes or partial dose features next to the channel (i.e., trench opening) in order to increase the width of the undercut. The undercut is the curved sidewall of the bottom resist layer <NUM>, which is cut/removed under the top resist layer <NUM>. If the undercut (of bottom resist layer <NUM>) increases sufficiently, the deposited features (i.e., film <NUM>) no longer end up on the undercut sidewall. This can be done quantitatively for specific features and locations, but the undercut can also be increased preventively without quantitative analysis. There is a practical limit to the extent of increasing the undercut.

Second Solution <NUM> is the following. The reduced feature width (film <NUM>) due to sidewall flashing can also be corrected by increasing the channel width (i.e., the opening of the trench feature <NUM>) by the correction amount wflash. A predictive calculation requires detailed quantitative knowledge of the resist profile, particularly the resist thicknesses and the amount of undercut. Additionally, the needed correction can also be determined empirically. The channel width increase can be achieved by pattern or dose correction.

Referring to <FIG>, the deposited film <NUM> abuts and lands (i.e., flashes) on the curved sidewall of the bottom resist layer <NUM>. Flashing on the curved sidewall reduces the width of the film <NUM> in the x'-axis (axes are assumed to be tilted by some arbitrary value, in accordance to previous configurations of the correction to be performed). To address this flashing, <FIG> depicts a top view of the left die, and <FIG> depicts a cross-sectional view of <FIG>. In <FIG>, the left side of the undercut of resist <NUM> is increased, which prevents the film <NUM> from landing on the curved sidewall of the bottom resist <NUM> and allows the entire film <NUM> to be deposited on the substrate <NUM>. This is the first solution <NUM>.

Alternatively (and/or additionally), to address this flashing, <FIG> depicts a top view of the left die, and <FIG> depicts a cross-sectional view of <FIG>. In <FIG>, the width of the trench feature <NUM> is increased to compensate for the sidewall deposit <NUM>. The deposited film <NUM> can still hit or land on the curved sidewall of the bottom resist <NUM>, but the film <NUM> has the correct width in the x'-axis because of the increased trench width (opening) in the x'-axis.

<FIG> depicts a cross-sectional view as examples of <NUM> completed Josephson junctions <NUM> using the one or a combination of any of the shadow evaporation corrections discussed herein according to embodiments of the present invention. As discussed herein, there are <NUM> lithographic features <NUM> formed in the top resist layer <NUM> and bottom resist layer <NUM>, which results in <NUM> dies <NUM>. In order to fabricate the <NUM> Josephson junctions <NUM>, <NUM> shadow evaporations are required. The first shadow evaporation deposits the first film <NUM> on the substrate <NUM>. Corrections, such as positional tilt corrections and/or sidewall flashing corrections, have been applied to the first shadow evaporation. There is no need for sidewall corrections to be applied to the first shadow evaporation from the evaporation source <NUM> because no sidewall deposit <NUM> has occurred prior to the first shadow evaporation.

After the first shadow evaporation to deposit the first film <NUM>, an oxide layer <NUM> is grown on top of first film <NUM>. For example, the superconducting metal of the first film <NUM> can be oxidized to form the oxide layer <NUM>. The oxide is typically grown by oxidizing the existing superconductor metal, such as Aluminum, without breaking vacuum. This is done by introducing oxygen gas into the evaporation chamber or an attached oxidation chamber that the sample can be transferred to and from without vacuum break at this step. Alternatively, an oxide can be deposited instead of grown.

Previously, in the various examples, shadow evaporation was discussed to deposit a film only on the substrate <NUM> for explanation purposes. It is understood to form a Josephson junction that the second film is deposited on the previously deposited film (particularly on the oxide layer), thereby resulting in a Josephson junction. In <FIG>, a second shadow evaporation from the evaporation source <NUM> is performed to deposit the second film <NUM> on top of the oxide layer <NUM>. The second shadow evaporation has been corrected for corrections, such as positional tilt corrections, sidewall flashing corrections, and/or sidewall deposit corrections. It is noted that sidewall deposit corrections are accounted for only after a previous shadow mask evaporation has occurred (e.g., the first shadow mask evaporation).

After the Josephson junctions <NUM> have been formed, the bottom resist layer <NUM>, top resist layer <NUM>, and any deposited material from shadow evaporations (such as the sidewall deposit <NUM> and top deposit <NUM>) formed on the top resist layer <NUM> are removed. This leaves the <NUM> Josephson junctions <NUM> on the substrate <NUM>.

<FIG> depicts example systems configured to perform the corrections discussed herein according to embodiments of the present invention. A computer system <NUM> includes a software tool <NUM> configured with one or more algorithms to perform positional tilt corrections, sidewall deposit corrections, and/or sidewall flashing corrections for design features <NUM> in an original layout <NUM>, in order to generate a corrected layout <NUM>. The software tool <NUM> can include the functionality to allow for layout <NUM> of a design that is to be fabricated and/or can receive loading of the original layout <NUM> in order to perform the corrections discussed herein. The computer system <NUM> includes one or more processors <NUM> configured to execute instructions of the software tool <NUM>, thereby generating the corrected layout <NUM> from the original layout <NUM>.

The computer system <NUM> can transmit the corrected layout <NUM> to a lithographic tool <NUM>. In some implementations, the lithographic tool <NUM> can include the software tool <NUM> and/or functionality of the software tool <NUM> such that the lithographic tool <NUM> is configured to make the corrections to the original layout <NUM> to generate the corrected layout <NUM>.

The lithographic tool <NUM> includes fabrication equipment <NUM> for fabricating semiconductor circuits (including superconducting circuits) as understood by one skilled in the art. The fabrication equipment <NUM> can represent a variety of fabrication devices which can be separate or integrated in a fabrication lab. The lithographic tool <NUM> includes the circuitry <NUM> (hardware along with software) to operate as discussed herein. The lithographic tool <NUM> alone and/or in conjunction with the computer system <NUM> is configured to perform a process in <FIG> and <FIG>. <FIG> and <FIG> depict a flow chart <NUM> of a process for correcting and forming Josephson junctions for superconducting qubits when depositing the films <NUM> of the Josephson junction using sequential shadow mask evaporations. At block <NUM>, the software tool <NUM> receives the choice of critical current Ic values for Josephson junctions in superconducting qubits to be fabricated. At block <NUM>, the software tool <NUM> receives selection of the Josephson junction design/style (e.g., Dolan bridge Josephson junctions, Manhattan Josephson junctions, other shadow-masked Josephson junctions).

At block <NUM>, the software tool <NUM> receives selection of the fabrication process and parameters (e.g., tilt angles for shadow evaporations, oxidation conditions). Further, the design/style for Dolan bridge Josephson junctions and Manhattan Josephson junctions have fabrication process and parameters for height/thickness/multilayer/undercuts, bridge dimensions, tilt angles, rotation angles, film thicknesses, sample size, etc., as understood by one skilled in the art.

At block <NUM>, the software tool <NUM> (which can include the features of a state-of-the-art layout tool) designs the Josephson junctions that nominally confirm with the style and fabrication parameters, thereby creating the original layout <NUM>. The originally layout <NUM> is a file (i.e., computer file). In some embodiments, original layout <NUM> can be created by a state-of-the-art software program, and then loaded to the computer system <NUM> for corrections. At block <NUM>, the corrections discussed herein can be manual or automatic corrections. At block <NUM>, the software tool <NUM> is configured to apply software automated corrections at wafer and die level to the original layout (design) <NUM> for the type of Josephson junctions and shadow mask recipe. This creates the corrected layout (design) <NUM>. Although two layouts are illustrated as the original layout <NUM> and the corrected layout <NUM> for explanation purposes, the corrections can be made to the original layout <NUM> such that original layout <NUM> itself is now corrected/updated (i.e., after the corrections the original layout becomes the corrected layout). Corrected layout <NUM> can be a separate layout in one implementation, and the corrected layout <NUM> can be an updated version of the original layout <NUM>.

A layout is a representation of a design, and often used interchangeably. At the design/layout correction stage, the software (or manual) correction will take each of the features <NUM> in the design and adjust these features <NUM> to achieve the desired effect (i.e., positional tilt correction, sidewall deposit correction, sidewall flashing correction) either at the individual die level (die is a unit of repetition of a mask design on a wafer), or wafer level (that is, corrects features on separate dies differently). The layout becomes a file that can be used for lithography.

Optionally, at block <NUM>, the software tool <NUM> is configured to check if there are any further design corrections that the operator desires to manually make. For example, the software tool <NUM> is configured to display a message asking the operator if he wants to make further manual corrections addressing positional tilt correction, sidewall deposit correction, and/or sidewall flashing correction.

If no manual corrections are needed to the corrected layout <NUM>, the software tool <NUM> is configured to apply any remaining lithographic corrections at the die and wafer level with automated software to the lithographic pattern of a sample, for the type of Josephson junctions and shadow mask recipe at block <NUM>. With respect to the patterning stage, the mask design (i.e., corrected layout file <NUM>) of the previous block is entered as input to a lithographic tool <NUM> such as an e-beam writer (which is a type of fabrication equipment). An e-beam writer or a direct write laser lithography system can be particularly utilized for embodiments of the present invention because of the feature size and versatility afforded. The fabrication equipment <NUM> can also be representative of optical lithography equipment in which an optical mask is a physical object that is fixed in shape and used to pattern the features with light of a fixed wavelength (corresponding to a location in the optical spectrum, e.g., ultraviolet, visible, infrared). The operator and or software tool <NUM> can additionally provide a job file as input to the lithographic tool <NUM>, which manages how to handle the design input which is the corrected layout <NUM>.

Additionally, the lithographic tool <NUM> (for an e-beam writer, for example) can provide a mechanism (such as software tool <NUM>) to receive a mask design (original layout <NUM>) and modify it (to be the corrected layout <NUM>) for the purpose of area correction in the multiple-shadow-mask fabrication. In other words, given an input design (original layout <NUM>), the software tool <NUM> integrated in the lithographic tool <NUM> would post-process the original layout to correct it for that type of fabrication (i.e., e-beam), and the exposures of the pattern on the wafer (or sample) would come out corrected.

At block <NUM>, the software can check (e.g., display a message) whether the operator wants to any manual lithographic patterning corrections. At block <NUM>, the lithographic tool <NUM> makes the Josephson junctions according to the fabrication process and parameters. Fabricating the Josephson junctions can include depositing the resists <NUM>, <NUM> on the wafer <NUM>, exposing the resists <NUM>, <NUM>, etching substrate <NUM>, developing the resists <NUM>, <NUM>, performing shadow mask evaporation (i.e., depositing first and second films <NUM>) and oxidation or oxide deposition (for oxide layer <NUM>) according to the planned shadow mask recipe (i.e., design), and performing lift off of the resists <NUM>, <NUM> leaving Josephson junctions <NUM>.

At block <NUM>, a sample analysis can be performed to verify that the corrections occurred as desired. If yes, the sample is ready, the flow branches to block <NUM>.

Taking the other branch from block <NUM>, the operator can apply manual corrections at wafer and die level to the original layout (design) <NUM> for the type of Josephson junctions and shadow mask recipe. This creates the corrected layout (design) <NUM>. The operator could use the software tool <NUM>.

At block <NUM>, the operator can check if there are further automatic design corrections. If no automatic design corrections needed, the operator can apply any remaining lithographic corrections at the die and wafer level without automated software to the lithographic pattern of a sample, for the type of Josephson junctions and shadow mask recipe at block <NUM>. The operator can use the software tool <NUM>.

At block <NUM>, the operator can check if further automatic lithographic patterning corrections are needed. If yes the flow branches to <NUM>, and if no the flow branches to block <NUM>.

As further information on the hardware side (as would be understood by one skilled in the art), a wafer/sample <NUM> would have resist (spun over it) which is sensitive to the patterning tool exposure method (via the lithographic tool <NUM>). If e-beam is utilized as the fabrication method, the beam is deflected according to the specifications of the mask design and job file (and dose (for e-beam lithography, the dose may be defined as the electric charge per unit area) over areas of the wafer <NUM> to sensitize the e-beam resist (for example, PMMA or equivalent). If optical lithography is utilized as the fabrication method, light of a fixed wavelength shines into the apertures of a physical optical mask, and where the mask is transparent, the resist is sensitized (photoresist). Because optical lithography uses a physical mask, it is not possible to make local dose modifications within a single die (for optical lithography, the dose may be defined as the intensity times the exposure time). A die is typically the result of a single exposure through the physical optical mask. But it is possible to modify the dose applied to different dies within the wafer using optical lithography.

Further, it is noted that after the resist is sensitized, it can be developed using the appropriate developers. If using a positive tone process, the resist is removed where it is sensitized. In the example scenario, embodiments of the present invention have a bilayer of resist (top resist <NUM> and bottom resist <NUM>), where an underlayer (bottom resist <NUM>) is used to provide an undercut, as seen in some of the figures (this is a positive tone process).

The fabrication involves making Josephson Junctions <NUM> of a given area (given by the overlap of two evaporations) using shadow-masking, not breaking vacuum, and schemes such as Dolans or Manhattans (or other structures). Other methods of fabricating Josephson junctions (or other tunnel junctions) where a point evaporation source is involved may also correct for overlap area using the corrections described here. For example, the fabrication of the Josephson junction may result in less variability across a wafer by applying positional or flashing corrections (sidewall corrections can only be applied if there are multiple evaporations prior to stripping the resist (i.e., prior to lift off)).

In any case, the most corrections will occur at the mask design stage, and the automated software tool <NUM> can make the corrections such that the user does not have to make those calculations.

Turning to <FIG>, a flow chart <NUM> is provided of a method for correcting an area of overlap between two films created by sequential shadow mask evaporations according to embodiments of the present invention. Reference can be made to the figures discussed herein.

At block <NUM>, an operator (and/or the software tool <NUM> is configured to) performs at least one process selected from the group consisting of: correcting design features <NUM> in an original layout <NUM> to generate a corrected layout <NUM> using a software tool <NUM>, such that the corrected layout <NUM> has modified shapes of the design features <NUM> at block <NUM>, and/or correcting the design features <NUM> in the original layout <NUM> to generate the corrected layout <NUM> using a lithographic tool <NUM>, such that the corrected layout <NUM> has modified shapes of the design features <NUM> at block <NUM>.

At block <NUM>, the lithography tool <NUM> (which can be instructed by the software tool <NUM> and/or operator) is configured to pattern the modified shapes of the design features <NUM> at locations on a wafer <NUM> according to the corrected layout <NUM>.

At block <NUM>, the lithography tool <NUM> is configured to deposit a first film <NUM> by an initial shadow mask evaporation (as depicted in <FIG>) and a second film <NUM> (as depicted in <FIG>) by a subsequent shadow mask evaporation to produce corrected junctions (e.g., junction <NUM>) at the locations on the wafer <NUM>, such that the first and second films <NUM> have an overlap (as depicted in <FIG>).

The overlap between the first and second films <NUM> defines a tunnel junction. The overlap between the first and second films <NUM> defines a Josephson junction (JJ). The initial and subsequent shadow mask evaporations may utilize a suspended resist bridge. The suspended resist bridge can be formed by the bilayer resist of resist layers <NUM> and <NUM>. The initial and subsequent shadow mask evaporations may utilize a crossing without a suspended resist bridge. The crossing relates to a Manhattan crossing. Corrections (such as positional tilt correction, sidewall deposit correction, and/or sidewall flashing correction) to the original layout <NUM> account for (accommodate) narrowing of the design features <NUM> (e.g., the trench in example scenarios) from previous depositions (by shadow mask evaporation) prior to the subsequent shadow mask evaporation.

An oxide layer <NUM> is between the first film <NUM> and the second film <NUM>.

The corrected layout <NUM> includes a positional tilt correction. The positional tilt correction is configured to modify the shapes (i.e., trench) of the design features <NUM> relative to a position of an evaporation source <NUM> and individual ones of the design features <NUM>.

The corrected layout <NUM> includes a sidewall deposit correction. The sidewall deposit correction is configured to modify the shapes (e.g., trenches) of the design features <NUM> relative to a previous sidewall deposit <NUM> from a previous shadow mask evaporation.

The corrected layout <NUM> includes a sidewall flashing correction. The sidewall flashing correction is configured to modify the shapes of the design features <NUM> to prevent a width of the first film <NUM>, the second film <NUM>, or both the first and second films <NUM> from being reduced by flashing against a sidewall of a resist material (e.g., the bottom resist layer <NUM>).

Corrections in the corrected layout include at least two types of corrections selected from the group consisting of: a positional tilt correction, a sidewall deposit correction, and/or a sidewall flashing correction.

<FIG> depicts a flow chart <NUM> of a method of forming junctions according to embodiments of the present invention. Reference can be made to the figures discussed herein.

At block <NUM>, the operator can utilize the software tool <NUM> and/or the lithographic tool <NUM> to correct the design features <NUM> in an original layout <NUM> to generate a corrected layout <NUM>. At block <NUM>, the operator can utilize the lithographic tool <NUM> to pattern the design features <NUM> of the corrected layout <NUM> at locations on a wafer <NUM>. At block <NUM>, the lithographic tool <NUM> is configured to deposit a first film <NUM> (as depicted in <FIG>) and a second film <NUM> (as depicted in <FIG>) using shadow mask evaporation according to the corrected layout <NUM>, where the corrected layout <NUM> corrects for deposition by the shadow mask evaporation.

An overlap between the first and second films <NUM> defines a tunnel junction. An overlap between the first and second films <NUM> defines a Josephson junction.

Correcting the design features in the original layout to generate the corrected layout comprises widening shapes (i.e., widening the trench) of the design features <NUM> relative (i.e., with respect to angles of evaporation) to an evaporation source.

The oxide layer <NUM> is between the first film and the second film. The corrected layout includes a positional tilt correction. The corrected layout includes a sidewall deposit correction. The corrected layout includes a sidewall flashing correction.

<FIG> depicts a flow chart <NUM> for correcting an area of overlap between two films created by sequential shadow mask evaporations according to embodiments of the present invention. Reference can be made to the figures discussed herein.

At block <NUM>, software tool <NUM> and/or the lithographic tool <NUM> is configured to correct design features <NUM> in an original layout <NUM> to generate a corrected layout <NUM>, where the design features <NUM> in the corrected layout <NUM> have been modified to account in advance for being at different positions relative to an evaporation source <NUM>.

At block <NUM>, the lithographic tool <NUM> (software tool <NUM> can instruct the lithographic tool <NUM>) is configured to pattern the design features <NUM> of the corrected layout <NUM> at locations on a wafer <NUM>.

At block <NUM>, the lithographic tool <NUM> (software tool <NUM> can instruct the lithographic tool <NUM>) is configured to deposit a first film <NUM> (as depicted in <FIG>) and a second film <NUM> (as depicted in <FIG>) using shadow mask evaporation according to the corrected layout <NUM>.

At block <NUM>, the software tool <NUM> and/or the lithographic tool <NUM> is configured to correct design features <NUM> in an original layout <NUM> to generate a corrected layout <NUM>, where the design features <NUM> in the corrected layout <NUM> have been modified to account in advance for sidewall deposits of material (e.g., sidewall deposit <NUM>) on the design features <NUM> from an evaporation source <NUM>.

At block <NUM>, the software tool <NUM> and/or the lithographic tool <NUM> is configured to correct design features <NUM> in an original layout <NUM> to generate a corrected layout <NUM>, where the design features <NUM> in the corrected layout <NUM> have been modified to account in advance for flashing against a sidewall of a resist (e.g., bottom resist layer <NUM> having the curved undercut) during a shadow mask evaporation.

Examples of superconducting materials (at low temperatures, such as about <NUM>-<NUM> millikelvin (mK), or about <NUM>) include niobium, aluminum, tantalum, etc. For example, the Josephson junctions are made of superconducting material, and their tunnel junctions can be made of a thin tunnel barrier, such as an oxide. Any transmission lines (i.e., wires) connecting the various elements are made of a superconducting material.

Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic.

As previously noted herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a semiconductor or superconductor device according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.

Claim 1:
A method for correcting an area of overlap between two (<NUM>) films created by sequential shadow
mask evaporations, the method comprising:
correcting (<NUM>) design features in an original layout to generate a corrected layout using a software tool (<NUM>), such that the corrected layout modifies shapes of the design features;
or
correcting (<NUM>) design features in an original layout to generate a corrected layout using a lithographic tool (<NUM>), such that the corrected layout modifies shapes of the design features;
patterning (<NUM>) the modified shapes of the design features at locations on a wafer (<NUM>) according to the corrected layout using the lithographic tool, wherein the corrected layout includes a sidewall flashing correction, wherein the sidewall flashing correction is configured to modify the shapes of the design features to prevent a width of the first film, the second film, or both the first film and second film from being reduced by flashing against a sidewall of a resist material; and
depositing (<NUM>) a first (<NUM>) film by an initial shadow mask evaporation and a second film (<NUM>) by a subsequent shadow mask evaporation to produce a corrected junction at the locations on the wafer, such that the first film and the second film have an overlap, the overlap defining a tunnel junction.