Patent Description:
A power module is used to supply a high voltage and current in order to drive a motor in a hybrid vehicle or an electric vehicle.

A double-sided cooling power module among the power modules has substrates installed on and below a semiconductor chip, respectively, and has heat sinks provided on the outsides of the substrates, respectively. The use of the double-sided cooling power module tends to be gradually increased because the double-sided cooling power module has more excellent cooling performance than a cross-section cooling power module having a heat sink provided on one side thereof.

The double-sided cooling power module that is used in an electric vehicle, etc. generates high heat due to a high voltage and vibration during driving because a power semiconductor chip made of silicon carbide (SiC), gallium nitride (GaN), etc. is mounted between the two substrates. In order to solve such a problem, it is important to satisfy both high strength and high heat dissipation characteristics. US Patent Application <CIT> discloses a power module comprising: a lower ceramic substrate; an upper ceramic substrate disposed over the lower ceramic substrate; and a PCB substrate disposed over the upper ceramic substrate.

An object of the present disclosure is to provide a power module which has high strength and high heat dissipation characteristics and has an excellent bonding characteristic and which can reduce a volume by minimizing a current path and can improve efficiency and performance.

Furthermore, an object of the present disclosure is to provide a power module capable of minimizing a current path and improving moving efficiency of a high-speed current by applying a three-layer structure including a lower ceramic substrate, an upper ceramic substrate, and a PCB substrate and shortening an electrical connection distance the upper ceramic substrate and the PCB substrate.

Furthermore, an object of the present disclosure is to provide a power module capable of implementing performance thereof without being limited to an area and volume thereof.

Furthermore, an object of the present disclosure is to provide a power module which secures long lifespan and reliability by reducing a stress concentration by forming a curvature inclined part at an edge of a ceramic substrate.

According to a characteristic of the present disclosure for achieving the object, the power module of the present disclosure includes a lower ceramic substrate, an upper ceramic substrate disposed over the lower ceramic substrate and configured to have a semiconductor chip mounted in a flip chip form on a lower surface of the upper ceramic substrate, and a PCB substrate disposed over the upper ceramic substrate.

The power module includes a plurality of through holes formed to correspond to the upper ceramic substrate and the PCB substrate, and a connection pin formed in the through hole of the upper ceramic substrate and the through hole of the PCB substrate in a way to penetrate through the through holes and configured to perpendicularly connect an electrode pattern of the ceramic substrate and an electrode pattern of the PCB substrate.

The connection pin formed in the through hole in a way to penetrate through the through holes is bonded to an electrode pattern at an edge of the through hole by laser welding.

The power module includes a solder layer coated at the edge of the through hole, melted upon the laser welding, and configured to bond the connection pin to the electrode pattern at the edge of the through hole.

The upper ceramic substrate may include a ceramic base, electrode patterns formed on upper and lower surfaces of the ceramic base, a plurality of via holes formed to penetrate the upper ceramic substrate or the ceramic base up and down, and a metal filler filled into the via hole and configured to connect the electrode patterns of the upper and lower surfaces of the ceramic base.

The via hole has a diameter of <NUM> to <NUM>.

The metal filler may be made of one of Ag alloy series, Ag-Pd series, Ag-ceramic series, and Cu alloy series, or a mixed paste of them.

The via hole is uniformly distributed on an entire surface of the upper ceramic substrate or the ceramic base.

The power module includes a heat sink soldering-bonded to a lower surface of the lower ceramic substrate.

Each of the upper ceramic substrate and the lower ceramic substrate may be one of an active metal brazing (AMB) substrate, a direct bonding copper (DBC) substrate, a direct brazed aluminum (DBA) substrate, and a thick printing copper (TPC) substrate.

The power further includes a housing configured to have an empty space, opened up and down, formed at a center thereof and formed of an injection material. The lower ceramic substrate, the upper ceramic substrate, and the PCB substrate are sequentially installed in the empty space of the housing.

The power module includes a spacer disposed between the lower ceramic substrate and the upper ceramic substrate in a plural number and configured to regulate an isolation distance between the lower ceramic substrate and the upper ceramic substrate.

The upper ceramic substrate includes a ceramic base and a metal layer that forms an electrode pattern by being bonded to at least one surface of the ceramic base. A curvature inclined part is formed at an edge of the metal layer. The curvature inclined part protrudes in a direction of an outer circumference of the ceramic base.

The curvature inclined part is formed in a concave shape in a direction of the ceramic base, and has a shape in which a protruded length of the curvature inclined part is increased toward the direction of the ceramic base.

The curvature inclined part may have a multi-stage structure in which a plurality of concave parts is formed and a protruded part is formed at a part where the concave part and the concave part are met.

The protruded part may have a pointed shape.

The curvature inclined part may have a two-stage structure in which two concave parts are formed and a protruded part is formed at a part where the concave part and the concave part are met.

The curvature inclined part formed at the edge of the metal layer may have a mixed structure of a one-stage structure formed in a concave shape in the direction of the ceramic base and a multi-stage structure in which two or more concave parts have been formed in the direction of the ceramic base.

The curvature inclined part may be formed by disposing a photomask on one surface of the metal layer and etching the metal layer exposed by the photomask.

The curvature inclined part of the multi-stage structure may be formed by disposing, on the one surface of the metal layer, a photomask in which two or more holes have been adjacently formed and etching the metal layer exposed by the photomask.

The present disclosure has effects in that it has high strength and high heat dissipation characteristics and has an excellent bonding characteristic, can reduce a volume by minimizing a current path, and can improve efficiency and performance due to optimization for high-speed switching.

Furthermore, the present disclosure has effects in that various output losses can be removed due to a minimized current path, the size of the power module can be reduced, and heat dissipation is also advantageous by fabricating the lower ceramic substrate, the upper ceramic substrate, and the PCB substrate as a three-layer integration type construction and perpendicularly connecting the electrical connection between the upper ceramic substrate and the PCB substrate by using the connection pin.

Furthermore, the present disclosure has effects in that a problem, such as a short or overheating, can be prevented and moving efficiency of a high-speed current can be improved because the distribution of a high current and the current-carrying of a high current are facilitated in a way that the electrode patterns of the upper and lower surfaces of the upper ceramic substrate are connected by forming the via holes in a plural number.

Furthermore, the present disclosure has effects in that the semiconductor chip can be protected because the lower ceramic substrate and the upper ceramic substrate are formed as an upper and lower duplex structure and the semiconductor chip is mounted therebetween and performance can be implemented without being limited to a fabrication area and volume of the power module because a driving element for operating the semiconductor chip is mounted by disposing the PCB substrate over the upper ceramic substrate.

Furthermore, the present disclosure has effects in that a problem, such as a short or overheating, can be prevented and moving efficiency of a high-speed current can be improved because the distribution of a high current and the current-carrying of a high current are facilitated in a way that the electrode patterns of the upper and lower surfaces of the upper ceramic substrate are connected by forming the via holes in the upper ceramic substrate and filling the via holes with the metal filler.

Furthermore, the present disclosure has effects in that long lifespan of the ceramic substrate can be secured and the reliability of the power module can be improved because a stress concentration attributable to heat and a stress concentration attributable to an electrical shock are reduced by forming the curvature inclined part having the one-stage structure or the multi-stage structure at an edge of the ceramic substrate.

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

<FIG> is a perspective view of a power module according to an embodiment of the present disclosure. <FIG> is an exploded perspective view of the power module according to an embodiment of the present disclosure.

As illustrated in <FIG> and <FIG>, the power module <NUM> according to an embodiment of the present disclosure is an electronic part having a package form, which is formed by accommodating, in a housing <NUM>, various components that form the power module. The power module <NUM> is formed in a form in which substrates and elements are disposed and protected within the housing <NUM>.

The power module <NUM> may include multiple substrates and multiple semiconductor chips. The power module <NUM> according to an embodiment includes the housing <NUM>, a lower ceramic substrate <NUM>, an upper ceramic substrate <NUM>, a PCB substrate <NUM>, and a heat sink <NUM>.

An empty space that is opened up and down is formed at the center of the housing <NUM>. First terminals <NUM> and a second terminal <NUM> are disposed on both sides of the housing <NUM>. The heat sink <NUM>, the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> are sequentially stacked in the empty space at the center of the housing <NUM> at regular intervals. Support bolts <NUM> for connecting external terminals are fastened to the first terminals <NUM> and the second terminal <NUM> on both sides of the housing <NUM>. The first terminals <NUM> and the second terminal <NUM> are used as the input and output stages of a power source.

As illustrated in <FIG>, in the power module <NUM>, the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> are sequentially accommodated in the empty space at the center of the housing <NUM>. Specifically, the heat sink <NUM> is disposed at the lower surface of the housing <NUM>. The lower ceramic substrate <NUM> is attached to the upper surface of the heat sink <NUM>. The upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM> at a regular interval. The PCB substrate <NUM> is disposed over the upper ceramic substrate <NUM> at a regular interval.

The state in which the PCB substrate <NUM> has been disposed in the housing <NUM> may be fixed by guide grooves <NUM> and <NUM> formed at an edge of the PCB substrate <NUM> in a way to be concaved and a guide rib <NUM> and a locking projection <NUM> that are formed in the housing <NUM> in a way to correspond to the guide grooves <NUM> and <NUM>. The multiple guide grooves <NUM> and <NUM> are formed to enclose the edge of the PCB substrate <NUM> according to an embodiment. The guide rib <NUM> formed on the inner surface of the housing <NUM> is guided through some guide grooves <NUM> of the multiple guide grooves <NUM> and <NUM>. The locking projection <NUM> formed on the inner surface of the housing <NUM> passes through the remaining some guide grooves <NUM> of the multiple guide grooves <NUM> and <NUM>, and is hung thereto.

Alternatively, the state in which the heat sink <NUM>, the lower ceramic substrate <NUM>, and the upper ceramic substrate <NUM> are accommodated in the empty space at the center of the housing <NUM> and the PCB substrate <NUM> is disposed at the upper surface thereof may also be fixed by a fastening bolt (not illustrated). However, fixing the PCB substrate <NUM> to the housing <NUM> through the guide groove and the locking projection structure reduces an assembly time and has a simple assembly process compared to a case in which the PCB substrate <NUM> is fixed to the housing <NUM> by the fastening bolt.

Fastening holes <NUM> are formed at four corners of the housing <NUM>. The fastening holes <NUM> communicate with the communication holes <NUM> formed in the heat sink <NUM>. Fixing bolts <NUM> are fastened to penetrate the fastening holes <NUM> and the communication holes <NUM>. The ends of the fixing bolts <NUM> that have penetrated the fastening holes <NUM> and the communication holes <NUM> may be fastened to fixing holes of a fixing jig to be disposed at the lower surface of the heat sink <NUM>.

Bus bars <NUM> are connected to the first terminals <NUM> and the second terminal <NUM>. The bus bars <NUM> connect the first terminals <NUM> and the second terminal <NUM> to the upper ceramic substrate <NUM>. Three bus bars <NUM> are provided. One of the bus bars <NUM> connects a + terminal, among the first terminals <NUM>, to a first electrode pattern a of the upper ceramic substrate <NUM>, and another of the bus bars <NUM> connects a - terminal, among the first terminals <NUM>, to a third electrode pattern c. The remainder of the bus bars <NUM> connects the second terminal <NUM> to a second electrode pattern b. For the first electrode pattern a, the second electrode pattern b, and the third electrode pattern c, reference is made to <FIG> and <FIG> to be described later.

<FIG> is a side cross-sectional view of the power module according to an embodiment of the present disclosure.

As illustrated in <FIG>, the power module <NUM> is a duplex structure of the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. A semiconductor chip G is disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The semiconductor chip G may be any one of a gallium nitride (GaN) chip, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), and a high electric mobility transistor (HEMT), but the GaN chip is preferably used as the semiconductor chip G. The gallium nitride (GaN) chip G is a semiconductor chip that functions as a high power (<NUM> A) switch and a high-speed (~<NUM>) switch. The GaN chip has advantages in that it is more resistant to heat than existing silicon-based semiconductor chip and can also reduce the size of the chip.

Each of the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> is formed of a ceramic substrate including a ceramic base and a metal layer brazing-bonded to at least one surface of the ceramic base so that heat dissipation efficiency of heat generated from the semiconductor chip G can be improved.

The ceramic base may be any one of alumina (Al<NUM>O<NUM>), AlN, SiN, and Si<NUM>N<NUM>, for example. The metal layer is a metal foil brazing-bonded to a surface of the ceramic base, and is formed in the form of an electrode pattern on which the semiconductor chip G is mounted and an electrode pattern on which a driving element is mounted. For example, the metal layer is formed in the form of an electrode pattern in an area on which a semiconductor chip or a peripheral part will be mounted. The metal foil is an aluminum foil or a copper foil, for example. The metal foil is sintered on the ceramic base at <NUM> to <NUM> and brazing-bonded to the ceramic base, for example. Such a ceramic substrate is called an AMB substrate. An embodiment is described by taking the AMB substrate as an example, but may apply a DBC substrate, a TPC substrate, or a DBA substrate. However, in terms of durability and heat dissipation efficiency, the AMB substrate is most appropriate. For the reason, the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> are AMB substrates, for example.

The PCB substrate <NUM> is disposed over the upper ceramic substrate <NUM>. That is, the power module <NUM> is constituted with a three-layer structure of the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM>. Heat dissipation efficiency is improved by disposing the semiconductor chip G for control for high power between the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>. Damage to the PCB substrate <NUM> attributable to heat which occurs in the semiconductor chip G is prevented by disposing the PCB substrate <NUM> for control for low power at the top of the power module <NUM>. The lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> are connected or fixed by pins.

The heat sink <NUM> is disposed under the lower ceramic substrate <NUM>. The heat sink <NUM> is for discharging heat that is generated from the semiconductor chip G. The heat sink <NUM> is formed in a quadrangle plate shape having a predetermined thickness. The heat sink <NUM> is formed to have an area corresponding to the housing <NUM>, and may be formed of a copper or aluminum material in order to improve heat dissipation efficiency.

Hereinafter, characteristics for each component of the power module of the present disclosure are more specifically described. In a drawing that describes the characteristics for each component of the power module, there is a portion that has been expressed by enlarging or exaggerating the drawing in order to highlight the characteristics of each component. Accordingly, a portion that is not partially identical with some of the basic drawing illustrated in <FIG> may be present.

<FIG> is a perspective view illustrating a housing according to an embodiment of the present disclosure.

As illustrated in <FIG>, the housing <NUM> has an empty space formed at the center thereof, and has the first terminals <NUM> and the second terminal <NUM> disposed at both ends thereof. The housing <NUM> may have the first terminals <NUM> and the second terminal <NUM> formed at both ends thereof by using an insert injection method in a way to be integrally fixed thereto.

In the existing power module, a connection pin is applied to the housing through insert injection in order to connect isolated circuits. In contrast, in the present embodiment, the housing <NUM> has a shape that is manufactured by excluding the connection pin upon manufacturing. This improves flexibility for torsion moment of the power module by simplifying a shape of the power module because the connection pin is not disposed within the housing <NUM>.

The housing <NUM> has the fastening holes <NUM> formed at the four corners thereof. The fastening holes <NUM> communicate with the communication holes <NUM> formed in the heat sink <NUM>. The first terminals <NUM> and the second terminal <NUM> have support holes <NUM> formed therein. The support bolts <NUM> for connecting the first terminals <NUM> and the second terminal <NUM> to external terminals, such as a motor, are fastened to support holes <NUM> (refer to <FIG>).

The housing <NUM> is formed of an insulating material. The housing <NUM> may be formed of an insulating material so that heat generated from the semiconductor chip G is not delivered to the PCB substrate <NUM> over the housing <NUM>, through the housing <NUM>.

Alternatively, a heat dissipation plastic material may be applied to the housing <NUM>. The heat dissipation plastic material may be applied to the housing <NUM> so that heat generated from the semiconductor chip G can be discharged to the outside through the housing <NUM>. For example, the housing <NUM> may be formed of engineering plastics. The engineering plastics has high heat resistance, excellent strength, chemical resistance, and wear resistance, and may be used for a long time at <NUM> or more. The engineering plastics may be made of one material among polyamide, polycarbonate, polyester, and modified polyphenylene oxide.

The semiconductor chip G performs a repetitive operation as a switch. Accordingly, the housing <NUM> is subjected to stress attributable to a high temperature and a temperature change, but the engineering plastics is relatively stable with respect to a high temperature and a temperature change and is excellent in a heat dissipation characteristic compared to common plastics because the engineering plastics has excellent high temperature stability.

In an embodiment, the housing <NUM> may have been manufactured by applying a terminal made of aluminum or copper to the engineering plastic material through insert injection. The housing <NUM> made of the engineering plastic material discharges heat to the outside by propagating heat. The housing <NUM> may more increase thermal conductivity than a common engineering plastic material and may become light-weight and high heat dissipation engineering plastics, compared to aluminum by filling resin with a high heat conductivity filler.

Alternatively, the housing <NUM> may have a heat dissipation characteristic by coating a graphene heat dissipation coating material on the inside or outside of engineering plastics or high strength plastic material.

<FIG> is a perspective view illustrating a lower ceramic substrate according to an embodiment of the present disclosure.

As illustrated in <FIG> and <FIG>, the lower ceramic substrate <NUM> is attached to the upper surface of the heat sink <NUM>. Specifically, the lower ceramic substrate <NUM> is disposed between the semiconductor chip G and the heat sink <NUM>. The lower ceramic substrate <NUM> plays a role to deliver, to the heat sink <NUM>, heat generated from the semiconductor chip G and to prevent a short by insulating the semiconductor chip G and the heat sink <NUM>.

The lower ceramic substrate <NUM> may be soldered and bonded to the upper surface of the heat sink <NUM>. The heat sink <NUM> is formed to have an area corresponding to the housing <NUM>, and may be formed of a copper material in order to improve heat dissipation efficiency. SnAg, SnAgCu, etc. may be used as a solder for the soldering and bonding.

<FIG> is a diagram illustrating the upper surface and the lower surface of the lower ceramic substrate according to an embodiment of the present disclosure.

As illustrated in <FIG>, the lower ceramic substrate <NUM> includes a ceramic base <NUM> and metal layers <NUM> and <NUM> brazing-bonded to the upper surface and the lower surface of the ceramic base <NUM>. In the lower ceramic substrate <NUM>, the ceramic base <NUM> may have a thickness of <NUM>, and each of the metal layers <NUM> and <NUM> formed at the upper surface and the lower surface of the ceramic base <NUM> may have a thickness of <NUM>, for example.

The metal layer <NUM> at the upper surface 200a of the lower ceramic substrate <NUM> may be an electrode pattern on which a driving element is mounted. The driving element mounted on the lower ceramic substrate <NUM> may be an NTC temperature sensor <NUM>. The NTC temperature sensor <NUM> is mounted on the upper surface of the lower ceramic substrate <NUM>. The NTC temperature sensor <NUM> is for providing information on a temperature within the power module attributable to heat generated from the semiconductor chip G. The metal layer <NUM> at the lower surface 200b of the lower ceramic substrate <NUM> may be formed on the entire lower surface of the lower ceramic substrate <NUM> in order to facilitate the delivery of heat to the heat sink <NUM>.

An insulating spacer <NUM> is bonded to the lower ceramic substrate <NUM>. The insulating spacer <NUM> is bonded to the upper surface of the lower ceramic substrate <NUM>, and defines an isolation distance between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The insulating spacer <NUM> defines the isolation distance between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, thereby increasing heat dissipation efficiency of heat generated from the semiconductor chip G mounted on the lower surface of the upper ceramic substrate <NUM> and preventing an electrical shock, such as a short, by preventing interference between the semiconductor chips G.

Multiple insulating spacers <NUM> are bonded at predetermined intervals by enclosing an edge at the upper surface of the lower ceramic substrate <NUM>. An interval between the insulating spacers <NUM> is used as a space for increasing heat dissipation efficiency. In the drawing, the insulating spacers <NUM> are disposed to enclose the edge of the lower ceramic substrate <NUM>. For example, eight insulating spacers <NUM> are disposed at regular intervals.

The insulating spacers <NUM> are integrally bonded to the lower ceramic substrate <NUM>. The insulating spacers <NUM> may be applied for the purpose of checking the alignment of the upper ceramic substrate <NUM> when the upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM>. In the state in which the insulating spacers <NUM> have been bonded to the lower ceramic substrate <NUM>, when the upper ceramic substrate <NUM> on which the semiconductor chip G has been mounted is disposed over the lower ceramic substrate <NUM>, the insulating spacers <NUM> may be applied for the purpose of checking the alignment of the upper ceramic substrate <NUM>. Furthermore, the insulating spacers <NUM> contribute to preventing the bending of the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> by supporting the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The insulating spacers <NUM> may be formed of a ceramic material in order to insulate a chip mounted on the lower ceramic substrate <NUM> and a chip mounted on the upper ceramic substrate <NUM> and a part. For example, the insulating spacers may be formed of one kind selected among Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN or a mixed alloy of two or more of them. Al<NUM>O<NUM>, ZTA, Si<NUM>N<NUM>, and AlN are insulating materials having excellent mechanical strength and heat-resisting properties.

The insulating spacers <NUM> are brazing-bonded to the lower ceramic substrate <NUM>. The insulating spacers <NUM> are brazing-bonded to the lower ceramic substrate <NUM> because the substrate may be broken due to thermal and mechanical shocks upon soldering or pressurization sintering if the insulating spacers <NUM> are soldered and bonded to the lower ceramic substrate <NUM>. A brazing bonding layer including an AgCu layer and a Ti layer may be used for the brazing bonding. Heat treatment for the brazing may be performed at <NUM> to <NUM>. After the brazing, the insulating spacers <NUM> are integrally formed with the metal layer <NUM> of the lower ceramic substrate <NUM>. The thickness of the brazing bonding layer is <NUM> to <NUM>, which is thin to the extent that the height of the insulating spacers is not affected and has high bonding strength.

An interconnection spacer <NUM> is installed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The interconnection spacer <NUM> may perform an electrical connection between electrode patterns instead of a connection pin in a substrate having an upper and lower duplex structure. The interconnection spacer <NUM> can increase bonding strength and improve electrical characteristics by directly connecting the substrates, while preventing an electrical loss and shot. The interconnection spacer <NUM> may have one end bonded to the electrode pattern of the lower ceramic substrate <NUM> by using a brazing bonding method. Furthermore, the interconnection spacer <NUM> may have the other end opposite to the one end bonded to the electrode pattern of the upper ceramic substrate <NUM> by using a brazing bonding method or a soldering bonding method. The interconnection spacer <NUM> may be a Cu or Cu+CuMo alloy.

<FIG> is a perspective view illustrating an upper ceramic substrate according to an embodiment of the present disclosure. <FIG> is a diagram illustrating the upper surface and the lower surface of the upper ceramic substrate according to an embodiment of the present disclosure.

As illustrated in <FIG>, the upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM>.

The upper ceramic substrate <NUM> is an intermediate substrate having a stack structure. The upper ceramic substrate <NUM> has the semiconductor chip G mounted on a lower surface thereof and a high side circuit and a low side circuit for high-speed switching constructed on the lower surface.

The upper ceramic substrate <NUM> includes a ceramic base <NUM> and metal layers <NUM> and <NUM> brazing-bonded to the upper surface and the lower surface of the ceramic base <NUM>. In the upper ceramic substrate <NUM>, the ceramic base has a thickness of <NUM>, and each of electrode patterns of the upper surface 300a and the lower surface 300b of the ceramic base has a thickness of <NUM>, for example. The ceramic substrate is not twisted upon brazing only when the patterns at the upper surface and the lower surface thereof have the same thickness.

The electrode patterns that are formed by the metal layer <NUM> at the upper surface of the upper ceramic substrate <NUM> are divided into the first electrode pattern a, the second electrode pattern b, and the third electrode pattern c. The electrode patterns that are formed by the metal layer <NUM> at the lower surface of the upper ceramic substrate <NUM> correspond to the electrode patterns that are formed by the metal layer <NUM> at the upper surface of the upper ceramic substrate <NUM>. Dividing the electrode patterns at the upper surface of the upper ceramic substrate <NUM> into the first electrode pattern a, the second electrode pattern b, and the third electrode pattern c is for division into a high side circuit and a low side circuit for high-speed switching.

The semiconductor chip G is provided at the lower surface 300b of the upper ceramic substrate <NUM> in a flip chip form by an adhesive layer, such as a solder or an Ag paste. As the semiconductor chip G is provided in the flip chip form at the lower surface of the upper ceramic substrate <NUM>, an inductance value can be lowered as much as possible because wire bonding is omitted. Accordingly, heat dissipation performance can also be improved.

As illustrated in <FIG>, the semiconductor chip G may be connected in parallel by two for high-speed switching. Two semiconductor chips G are disposed at a location at which the first electrode pattern a and the second electrode pattern b, among the electrode patterns of the upper ceramic substrate <NUM>, are connected. The remaining two semiconductor chips G are disposed in parallel at a location at which the second electrode pattern b and the third electrode pattern c are connected. For example, the capacity of one semiconductor chip G is <NUM> A. Accordingly, the capacity of two semiconductor chips G become <NUM> A by connecting the two semiconductor chips G in parallel. The semiconductor chip G is a GaN chip.

The purpose of the power module using the semiconductor chip G is for high-speed switching. For the high-speed switching, it is important to connect the gate drive IC terminal and a gate terminal of the semiconductor chip G at a very short distance. Accordingly, a connection distance between the gate drive IC and the gate terminal is minimized by connecting the semiconductor chips G in parallel. Furthermore, in order for the semiconductor chip G to switch at high speed, it is important for the gate terminal and source terminal of the semiconductor chip G to maintain the same interval. To this end, the gate terminal and the source terminal may be disposed so that a connection pin is connected to the middle between the semiconductor chip G and the semiconductor chips G. A problem occurs if the gate terminal and the source terminal do not maintain the same interval or the length of a pattern is changed.

The gate terminal is a terminal that turns on/off the semiconductor chip G by using a low voltage. The gate terminal may be connected to the PCB substrate <NUM> through the connection pin. The source terminal is a terminal to and from which a high current is input and output. The semiconductor chip G includes a drain terminal. The source terminal and the drain terminal may change the directions of currents thereof by being divided into an N type and a P type. The source terminal and the drain terminal are responsible for the input and output of a current through the first electrode pattern a, the second electrode pattern b, and the third electrode pattern c, that is, the electrode patterns on which the semiconductor chip G is mounted. The source terminal and the drain terminal are connected to the first terminal <NUM> and the second terminal <NUM> in <FIG>, which are responsible for the input and output of a power source.

Referring to <FIG> and <FIG>, the first terminal <NUM> illustrated in <FIG> includes a + terminal and a - terminal. A power source that is introduced into the + terminal of the first terminal <NUM> is output to the second terminal <NUM> through the first electrode pattern a of the upper ceramic substrate <NUM> illustrated in <FIG>, the semiconductor chip G disposed between the first electrode pattern a and the second electrode pattern b, and the second electrode pattern b. Furthermore, a power source introduced into the second terminal <NUM> illustrated in <FIG> is output to the - terminal of the first terminal <NUM> through the second electrode pattern b illustrated in <FIG>, the semiconductor chip G disposed between the second electrode pattern b and the third electrode pattern c, and the third electrode pattern c. For example, a power that is introduced from the first terminal <NUM> and output to the second terminal <NUM> through the semiconductor chip G becomes a high side. A power source that is introduced from the second terminal <NUM> and output to the first terminal <NUM> through the semiconductor chip G becomes a low side.

As illustrated in <FIG>, the upper ceramic substrate <NUM> may have a cutting part <NUM> formed at a portion corresponding to the NTC temperature sensor <NUM>. The NTC temperature sensor <NUM> is mounted on the upper surface of the lower ceramic substrate <NUM>. The NTC temperature sensor <NUM> is for providing information on a temperature within the power module, which is attributable to heat generated from the semiconductor chip G. However, interference occurs between the NTC temperature sensor <NUM> and the upper ceramic substrate <NUM> because the thickness of the NTC temperature sensor <NUM> is greater than an interval between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. In order to solve such a problem, the cutting part <NUM> is formed by cutting a portion of the upper ceramic substrate <NUM> that interferes with the NTC temperature sensor <NUM>.

A silicon fluid or epoxy for molding may be injected into the space between the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM> through the cutting part <NUM>. In order to insulate the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>, the silicon fluid or the epoxy needs to be injected. In order to inject the silicon fluid or the epoxy into the upper ceramic substrate <NUM> and the lower ceramic substrate <NUM>, the cutting part <NUM> may be formed by cutting one surface of the upper ceramic substrate <NUM>. The cutting part <NUM> is formed at a location corresponding to the NTC temperature sensor <NUM>, and can also prevent interference between the upper ceramic substrate <NUM> and the NTC temperature sensor <NUM>. The silicon fluid or the epoxy may be filled into the space between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> and the space between the upper ceramic substrate <NUM> and the PCB substrate <NUM> for the purposes of protecting the semiconductor chip G, reducing vibration, and insulation.

A through hole <NUM> is formed in the upper ceramic substrate <NUM>. The through hole <NUM> is for connecting the semiconductor chip G mounted on the upper ceramic substrate <NUM> and a driving element mounted on the PCB substrate <NUM> at the shortest distance and connecting the NTC temperature sensor <NUM> mounted on the lower ceramic substrate <NUM> and a driving element mounted on the PCB substrate <NUM> at the shortest distance in an upper and lower duplex substrate structure.

Eight through holes <NUM> are formed at locations at which the semiconductor chip is installed by two. Two through holes <NUM> are installed at a location at which the NTC temperature sensor is installed. A total of ten through holes <NUM> may be formed. Furthermore, multiple through holes <NUM> may be formed at portions of the upper ceramic substrate <NUM> in which the first electrode pattern a and the third electrode pattern c have been formed.

The multiple through holes <NUM> formed in the first electrode pattern a enable a current that is introduced into the first electrode pattern a at the upper surface of the upper ceramic substrate <NUM> to move to the first electrode pattern a formed at the lower surface of the upper ceramic substrate <NUM> and to be introduced into the semiconductor chip G. The multiple through holes <NUM> formed in the third electrode pattern c enable a current that is introduced into the semiconductor chip G to move to the third electrode pattern c at the upper surface of the upper ceramic substrate <NUM> through the third electrode pattern c at the lower surface of the upper ceramic substrate <NUM>.

The diameter of the through hole <NUM> may be <NUM> to <NUM>. A connection pin is installed in the through hole <NUM>, and is connected to the electrode pattern of the PCB substrate, which may be connected to a driving element mounted on the PCB substrate <NUM> through the through hole <NUM>. In the upper and lower duplex substrate structure, the connection between the electrode patterns through the through hole <NUM> and the connection pin installed in the through hole <NUM> can contribute to improving restrictions according to the size of the power module by removing various output losses through the shortest distance connection.

A plurality of via holes <NUM> may be formed in the electrode pattern of the upper ceramic substrate <NUM>. The via holes <NUM> may be processed to be at least <NUM>% or more compared to the area of the substrate. It has been described that the area of the via holes <NUM> is applied as being at least <NUM>% or more compared to the area of the substrate, for example, but the present disclosure is not limited thereto and the area of the via holes <NUM> may be processed to be <NUM>% or less compared to the area of the substrate.

For example, <NUM> via holes may be formed in the first electrode pattern a, <NUM> via holes may be formed in the second electrode pattern b, and <NUM> via holes may be formed in the third electrode pattern c. The plurality of via holes <NUM> formed in each of the electrode patterns is for high current electrification and a high current distribution. If the electrode pattern at the upper surface of the upper ceramic substrate <NUM> and the electrode pattern at the lower surface of the upper ceramic substrate <NUM> become conductive to each other in one slot form, a problem, such as a short or overheating, may occur because a high current flows into only one side.

The via hole <NUM> is filled with a conductive substance. The conductive substance may be Ag or an Ag alloy. The Ag alloy may be an Ag-Pd paste. The conductive substance that is filled into the via hole <NUM> electrically connects the electrode pattern at the upper surface of the upper ceramic substrate <NUM> and the electrode pattern at the lower surface of the upper ceramic substrate <NUM>. The via hole <NUM> may be formed by laser processing. The via hole <NUM> may be seen in the enlarged view of <FIG>.

<FIG> is a perspective view illustrating the state in which pin connections have been coupled to the upper ceramic substrate according to an embodiment of the present disclosure.

As illustrated in <FIG>, a connection pin <NUM> is inserted into the through hole (reference numeral <NUM> in <FIG>) formed at a location adjacent to the semiconductor chip G in the upper ceramic substrate <NUM>. The connection pin <NUM> inserted into the through hole <NUM> formed at the location adjacent to the semiconductor chip G may be inserted into the through holes <NUM> formed at a location corresponding to the PCB substrate (reference numeral <NUM> in <FIG>), and may connect the gate terminal on which the semiconductor chip G is mounted and the electrode pattern of the PCB substrate <NUM>.

Furthermore, the connection pin <NUM> is inserted into the through hole <NUM> formed at a location adjacent to the NTC temperature sensor <NUM> in the upper ceramic substrate <NUM>. The connection pin <NUM> inserted into the through hole <NUM> formed at the location adjacent to the NTC temperature sensor <NUM> may be inserted into the through hole <NUM> formed at the location corresponding to the PCB substrate <NUM>, and may connect the terminal of the NTC temperature sensor <NUM> and the electrode pattern of the PCB substrate <NUM>.

Furthermore, the connection pin <NUM> is inserted into multiple through hole <NUM> that are formed in a row in the first electrode pattern a and third electrode pattern c of the upper ceramic substrate <NUM>. The connection pin <NUM> inserted into the multiple through holes <NUM> formed in the first electrode pattern a and the third electrode pattern c is inserted into the through hole <NUM> formed at the location corresponding to the PCB substrate <NUM>, and may connect the semiconductor chip G to the capacitor <NUM> of the PCB substrate <NUM>.

The connection pin <NUM> removes various output losses and enables high-speed switching by connecting, at the shortest distance, the semiconductor chip G mounted on the upper ceramic substrate <NUM> and a driving element mounted on the PCB substrate <NUM>.

<FIG> is a plan view of a PCB substrate according to an embodiment of the present disclosure.

As illustrated in <FIG>, a driving element for switching the semiconductor chip G or switching a GaN chip (a semiconductor chip) by using information detected by the NTC temperature sensor (reference numeral <NUM> in <FIG>) is mounted on the PCB substrate <NUM>. The driving element includes a gate drive IC.

A capacitor <NUM> is mounted on the upper surface of the PCB substrate <NUM>. The capacitor <NUM> is mounted on the upper surface of the PCB substrate <NUM>, that is, a location between the semiconductor chip G disposed to connect the first electrode pattern a and second electrode pattern b of the upper ceramic substrate <NUM> and the semiconductor chips G is disposed to connect the second electrode pattern b and third electrode pattern c of the upper ceramic substrate <NUM>.

When the capacitor <NUM> is mounted on the upper surface of the PCB substrate <NUM>, that is, the location between the semiconductor chips G, it is more advantageous in high-speed switching because the semiconductor chip G and a drive IC circuit can be connected at the shortest distance by using a connection pin (reference numeral <NUM> in <FIG>). For example, ten capacitors <NUM> may be connected in parallel in order to satisfy the capacity thereof. In order to secure <NUM> µF or more for a decoupling use at the input stage of the capacitors, the capacity can be secured by connecting ten high-voltage capacitors. The gate drive IC circuit includes a high side gate drive IC and a low side gate drive IC.

<FIG> is an internal construction diagram for describing a power module structure according to an embodiment of the present disclosure. Only major parts of the internal construction diagram of <FIG> are exaggerated and illustrated so that an internal structure of the actual power module illustrated in <FIG> can be easily identified. Accordingly, an actual side view of <FIG> and the construction diagram of <FIG> may include some portions that are not identical with each other.

As illustrated in <FIG>, the power module <NUM> has a three-layer integration type structure including the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM>.

The upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM> in a way to be spaced apart from the lower ceramic substrate <NUM>. The semiconductor chip G is mounted on the lower surface of the upper ceramic substrate <NUM>, and is disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The semiconductor chip G for control for high power is disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, and improves heat dissipation efficiency. Furthermore, if the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> are formed as an upper and lower duplex structure and the high-output semiconductor chip G is disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>, performance of the power module <NUM> can be implemented without being limited to an area and volume of the power module <NUM> because the semiconductor chip G is protected against an external environment.

The PCB substrate <NUM> is disposed over the upper ceramic substrate <NUM>. The PCB substrate <NUM> for control for low power is disposed over the upper ceramic substrate <NUM> in a way to be spaced apart from the upper ceramic substrate <NUM>, and prevents damage to the PCB substrate <NUM> attributable to heat generated from the semiconductor chip G.

A driving element for switching the semiconductor chip G, a capacitor for making a voltage continuous, a connector, etc. are mounted on the upper surface of the PCB substrate <NUM>. The driving element may include a gate drive IC circuit. The gate drive IC circuit may include a high side gate drive IC and a low side gate drive IC. The PCB substrate <NUM> may have a multi-layer structure in which an internal electrode pattern is formed between a plurality of insulating layers and an upper electrode pattern is formed at the highest layer of the plurality of insulating layers.

The through holes <NUM> and <NUM> are formed in the upper ceramic substrate <NUM> and the PCB substrate <NUM>. The connection pin <NUM> is formed in the through holes <NUM> and <NUM> formed in the upper ceramic substrate <NUM> and the PCB substrate <NUM> in a way to penetrate through the through holes. The connection pin <NUM> perpendicularly connects the electrode patterns a, b, c, and d that are formed in the upper ceramic substrate <NUM> and the PCB substrate <NUM>.

The connection pin <NUM> that has been installed to penetrate the through hole <NUM> of the upper ceramic substrate <NUM> and the through hole <NUM> of the PCB substrate <NUM> removes various output losses by connecting an electrode pattern a, b, c of the upper ceramic substrate <NUM> and the electrode pattern d of the PCB substrate <NUM> at the shortest distance, and facilitates control of great power at high speed by lowering impedance and inductance.

If impedance is low on the assumption that a voltage is constant, it is easy to control a current at high speed because a movement of the current is easy. Furthermore, if inductance is high, it is important to lower inductance for high-speed switching and heat dissipation because resistance is increased and heat is increased. Impedance and inductance are increased as a connection distance electrode patterns is increased.

If the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> are separately fabricated and are assembled and used if necessary, it is difficult to connect the electrode patterns at the shortest distance, various output losses occur because the electrode patterns need to be connected by using a wire, and there exist limitations in that it is difficult to control a current at high speed due to high impedance and inductance.

Accordingly, the power module of the embodiment minimizes a current path and lowers impedance and inductance by constructing a high output power semiconductor chip module and a drive printed circuit board assembly (PCBA) in an integrated type. The high output power semiconductor chip module means a module having a structure in which the high-output semiconductor chip G is disposed between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The drive PCBA means a PCB assembly in which a driving element, an electrode pattern, etc. are included in the PCB substrate <NUM>.

The semiconductor chip G may be any one of an SiC chip, a GaN chip, an MOSFET, an IGBT, a JFET, and an HEMT. Preferably, the semiconductor chip G is a GaN chip, and is fixed to the lower surface of the upper ceramic substrate <NUM> in a flip chip form. In an embodiment, a surface electrode on the upper surface of the semiconductor chip G is bonded to the metal layer <NUM> of the lower surface of the upper ceramic substrate <NUM>, and the lower surface of the semiconductor chip G is bonded to the metal layer <NUM> on the upper surface of the lower ceramic substrate <NUM>. If the semiconductor chip G is fixed to the upper ceramic substrate <NUM> in the flip chip form as described above, the semiconductor chip G may have the best performance because the distance between the semiconductor chip G and a gate drive IC terminal can be designed as short as possible.

The connection pin <NUM> may connect a gate terminal of the semiconductor chip G mounted on the upper ceramic substrate <NUM> and a drive IC mounted on the PCB substrate <NUM>. The drive IC includes a high gate drive IC (HS gate drive IC) and a low gate drive IC (LS gate drive IC). Furthermore, the connection pin <NUM> may connect the electrode pattern of the upper ceramic substrate <NUM> to a capacitor that is mounted on the PCB substrate <NUM>.

The connection pin <NUM> perpendicularly connects the upper ceramic substrate <NUM> and the PCB substrate <NUM>, but does not come into contact with the lower ceramic substrate <NUM> disposed under the upper ceramic substrate <NUM> in order to prevent a short.

The connection pins <NUM> formed in the through holes <NUM> and <NUM> in a way to penetrate through the through holes are bonded to the electrode patterns a, b, and c at edges of the through holes <NUM> of the upper ceramic substrate <NUM> by laser welding. If the connection pin <NUM> is fit and coupled to the through hole <NUM> and bonded thereto by laser welding, it is easy to fix the connection pin <NUM> to the upper ceramic substrate <NUM>, and the precision of a location is improved. This is advantageous in securing operation reliability of the power module because the connection pins <NUM> are stably connected to the electrode patterns a, b, and c of the upper ceramic substrate <NUM>.

A solder layer <NUM> for bonding the connection pins <NUM> to the electrode patterns a, b, and c of the upper ceramic substrate <NUM> upon laser welding is included. The solder layer <NUM> is coated on the edge of the through hole <NUM> of the upper ceramic substrate <NUM>, and is melted upon laser welding and connect the connection pins <NUM> to the electrode patterns a, b, and c. The connection pin <NUM> may be formed of copper or a copper alloy having conductivity. The connection pin <NUM> may be formed in a cylindrical shape corresponding to the diameter of the through hole <NUM>, <NUM>, and may be formed in a square pillar shape for the ease of production. Alternatively, the connection pin <NUM> may be manufactured in a bundle form, and may be fit and coupled to the through hole <NUM> of the upper ceramic substrate <NUM>.

The diameter of the through hole <NUM>, <NUM> may be <NUM> to <NUM>. When the diameter of the through hole <NUM>, <NUM> is less than <NUM>, it may be difficult to fit and couple the connection pin <NUM>, laser welding may be difficult, and stable fixing may be difficult. When the diameter of the through hole <NUM>, <NUM> is greater than <NUM>, it becomes an obstacle to a reduction in the size of the power module <NUM> because the size of the power module <NUM> needs to be increased due to interference between adjacent electrode patterns.

The heat sink <NUM> attached to the lower surface of the lower ceramic substrate <NUM> is included. The heat sink <NUM> may be soldering-bonded to the lower surface of the lower ceramic substrate <NUM>.

The lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> include the metal layers <NUM> and <NUM>, and <NUM> and <NUM> that are brazing-bonded to the upper and lower surfaces of the ceramic bases <NUM> and <NUM> and the ceramic bases <NUM> and <NUM>. The ceramic bases <NUM> and <NUM> are formed of any one of alumina (Al<NUM>O<NUM>), ZTA, AlN, SiN, and Si<NUM>N<NUM>, and the metal layers <NUM> and <NUM>, and <NUM> and <NUM> are formed of copper or a copper alloy material.

An example which the lower ceramic substrate <NUM> is an active metal brazing (AMB) substrate, the thickness of the ceramic base <NUM> that forms the AMB substrate is <NUM>, and the thickness of each of the metal layers <NUM> and <NUM> on the upper and lower parts of the ceramic base <NUM> is <NUM> may be taken.

An example in which the upper ceramic substrate <NUM> is an active metal brazing (AMB) substrate, the thickness of the ceramic base <NUM> that forms the AMB substrate is <NUM>, and the thickness of each of the metal layers <NUM> and <NUM> on the upper and lower parts of the ceramic base <NUM> is <NUM> may be taken. Furthermore, the metal layer is a copper foil, for example. The metal layers <NUM> and <NUM> form the electrode patterns a, b, and c.

An example in which the PCB substrate <NUM> is an FR4 substrate having a multi-layer structure and the thickness thereof is <NUM> may be taken. An example in which the heat sink <NUM> is formed any one of a copper material, a copper alloy material, a Cu-Mo-Cu three-layer structure, and a Cu-CuMo-Cu three-layer structure and the thickness thereof is <NUM> may be taken.

The via hole <NUM> may be formed in the upper ceramic substrate <NUM>.

<FIG> is a perspective view illustrating a form in which via holes have been formed in the ceramic base of the upper ceramic substrate as an embodiment of the present disclosure. <FIG> is a perspective view illustrating a form in which via holes have been formed in the upper ceramic substrate as a modified example of <FIG> of the present disclosure.

As illustrated in <FIG>, the via hole <NUM> is formed to penetrate the upper ceramic substrate <NUM> up and down. A metal filler P may be filled in the via hole <NUM>, and may connect the electrode patterns a, b, and c on the upper surface and lower surface of the ceramic base <NUM>.

Alternatively, as illustrated in <FIG>, the via hole <NUM> is formed to penetrate the ceramic base <NUM> of an upper ceramic substrate <NUM>'. The via hole <NUM> is formed in a plural number, and the via holes <NUM> are filled with the metal filler P. The metal filler P filled into the via hole <NUM> perpendicularly connects the electrode patterns a, b, and c on the upper surface and lower surface of the ceramic base <NUM>. The metal filler P filled into the via hole <NUM> may protrude the upper and lower parts of the via hole <NUM>, and may be bonded to the electrode patterns a, b, and c on the upper surface and lower surface of the ceramic base <NUM>.

The ceramic base <NUM> of the upper ceramic substrate <NUM>, <NUM>' may be formed of any one of alumina (Al<NUM>O<NUM>), ZTA, AlN, SiN, and Si<NUM>N<NUM>. The metal layers <NUM> and <NUM> are formed of copper or a copper alloy material. The metal layers <NUM> and <NUM> of the upper ceramic substrate <NUM>, <NUM>' form the electrode patterns a, b, and c.

The ceramic base <NUM> has a structure in which an electrical connection between the electrode patterns a, b, and c on the upper and lower surfaces of the ceramic base <NUM> is impossible because the ceramic base <NUM> is formed of an insulating material as described above. The power module requires a loop connection and an electrical circuit connection through the semiconductor chip. If the length of an electrical loop is increased, an inductance value is increased. If the inductance value is increased, it is disadvantageous to a high-speed movement of a current.

Accordingly, in order to make the inductance value advantageous to the high-speed movement of the current by lowering the inductance value, moving efficiency of the current can be improved and the size of the power module can be reduced by connecting the electrode patterns a, b, and c on the upper surface and lower surface of the ceramic base <NUM> by the metal filler P filled into the via holes <NUM>.

The diameter of the via hole <NUM> is in the range of <NUM> to <NUM> in order to facilitate the filling of the metal filler P. The metal filler P is made of conductive metal. For example, the metal filler P is made of one of Ag alloy series, Ag-Pd series, Ag-ceramic series, and Cu alloy series or a mixed paste of them. The metal filler P has low resistance, and improves moving efficiency of a current by connecting the electrode patterns a, b, and c on the upper surface and lower surface of the ceramic base <NUM>.

Preferably, the diameter of the via hole <NUM> is in the range of <NUM> to <NUM>. In the range in which the diameter of the via hole <NUM> is <NUM> to <NUM>, the metal filler P may be filled into the via hole <NUM>, and an excellent current-carrying property can be obtained. If the diameter of the via hole <NUM> is less than <NUM>, it is difficult for a current to pass through the electrode patterns a, b, and c on the upper surface and lower surface of the ceramic base <NUM> because it is difficult to fill the via hole <NUM> with the metal filler P. The via hole <NUM> may be formed to penetrate the upper ceramic substrate <NUM>. If the diameter of the via hole <NUM> is greater than <NUM>, a problem in that the metal filler P comes out from the via hole <NUM> after sintering may occur.

The area of the via hole <NUM> may be <NUM>% or more compared to the area of the upper ceramic substrate <NUM>. The area of the via hole <NUM> is a minimum area for increasing moving efficiency of a current by connecting the electrode patterns a, b, and c on the upper surface and lower surface of the ceramic base <NUM>. If the area of the via hole <NUM> is less than <NUM>% compared to the area of an upper ceramic substrate <NUM>", a problem may occur in the high-speed movement of a current because a moving load of the current is increased. Furthermore, it is preferred that the via hole <NUM> is uniformly distributed on the entire surface of the upper ceramic substrate <NUM>, <NUM>' for the distribution of a high current.

The aforementioned embodiment can easily control great power at high speed by minimizing a current path and lowering impedance and inductance in a way to fabricate the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> as a three-layer integration type.

Furthermore, the plurality of via holes <NUM> is formed in the upper ceramic substrate <NUM>, <NUM>' and connects the electrode patterns a, b, and c of the upper and lower surfaces of the upper ceramic substrate. Accordingly, a problem, such as a short or overheating, can be prevented and moving efficiency of a high-speed current can be improved because the distribution of a high current and the current-carrying of a high current are facilitated.

<FIG> is an internal construction diagram for describing a power module structure according to an embodiment of the present disclosure, and is a diagram that further includes a housing.

As illustrated in <FIG>, the power module <NUM> is fabricated in a module form in which the lower ceramic substrate <NUM> is bonded to the upper surface of the heat sink <NUM>, the upper ceramic substrate <NUM> is disposed over the lower ceramic substrate <NUM> in a way to be spaced apart from the lower ceramic substrate <NUM> through the medium of the insulating spacers <NUM>, the PCB substrate <NUM> is disposed over the upper ceramic substrate <NUM> in a way to be spaced apart from the upper ceramic substrate <NUM> through the medium of the connection pins <NUM>, and the lower ceramic substrate <NUM>, the upper ceramic substrate <NUM>, and the PCB substrate <NUM> are packaged by the housing <NUM>.

The housing <NUM> is formed of an injection material, and has an empty space that is formed at the center thereof and that is opened up and down. The heat sink <NUM> is bonded to the lower surface of the housing <NUM>. The lower ceramic substrate <NUM> is bonded to the upper surface of the heat sink <NUM> exposed to the empty space of the housing <NUM>. The upper ceramic substrate <NUM> and the PCB substrate <NUM> are sequentially installed over the lower ceramic substrate <NUM>. An isolation distance between the upper ceramic substrate <NUM> and the PCB substrate <NUM> is maintained to at least <NUM> in order to prevent damage to an element within the PCB substrate.

Furthermore, a silicon fluid S or epoxy is filled between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The silicon fluid S or epoxy insulates the electrode patterns of the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>.

The power module <NUM> has a duplex structure of the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM>. The semiconductor chip G is mounted between the lower ceramic substrate <NUM> and the upper ceramic substrate <NUM> in order to protect the semiconductor chip G. The power module <NUM> has a duplex structure in which the PCB substrate <NUM> is disposed over the upper ceramic substrate <NUM>, and has a packaging form using the silicon fluid S or epoxy. Accordingly, performance of the power module <NUM> can be implemented while not being limited to the area and volume thereof.

Furthermore, the power module <NUM> can remove various output losses and reduce its size because the electrode patterns of the upper ceramic substrate <NUM> and the PCB substrate <NUM> are connected by fitting and coupling the connection pins <NUM> to the through holes <NUM> and <NUM> formed in the upper ceramic substrate <NUM> and the PCB substrate <NUM>.

Furthermore, the power module <NUM> can prevent a problem, such as a short or overheating, and improve moving efficiency of a high-speed current because the distribution of a high current and the current-carrying of a high current are facilitated by forming the via holes <NUM> in the upper ceramic substrate <NUM>, <NUM>' and filling the via holes <NUM> with the metal filler P.

As described above, the aforementioned embodiment has advantages in that it can improve moving efficiency of a high-speed current by removing various output losses through electrical connections through the through holes and the via holes and can be reduced in size by improving restrictions to the size of the power module.

Meanwhile, as another embodiment, the power module can secure long lifespan and also improve reliability of the power module by forming a curvature inclined part at an edge of the ceramic substrate in order to reduce a stress concentration.

<FIG> is an internal construction diagram for describing a power module structure according to another embodiment of the present disclosure. <FIG> is a cross-sectional view illustrating the upper ceramic substrate in the power module structure according to another embodiment of the present disclosure.

A power module <NUM>' of another embodiment is different from the embodiment in a shape of the upper ceramic substrate.

As illustrated in <FIG>, in the ceramic substrate <NUM>" of another embodiment, a curvature inclined part <NUM>, <NUM>', <NUM>" for reducing a stress concentration is formed at an edge of the metal layer <NUM>", <NUM>". The lifespan of the ceramic substrate may be determined by a material of the ceramic base and a shape of the metal layer <NUM>", <NUM>" that forms the electrode pattern.

The material of the ceramic base <NUM> is formed of any one of alumina (Al<NUM>O<NUM>), AlN, SiN, and Si<NUM>N<NUM> having high strength in order to increase the lifespan of the ceramic base. As the thickness of the edge of the metal layer <NUM>", <NUM>" increases, bonding stress with the ceramic base <NUM> attributable to a stress concentration is increased. When the bonding stress is increased, the metal layer <NUM>", <NUM>" may be separated from the ceramic base <NUM> due to a sudden temperature change.

In order for the metal layer <NUM>", <NUM>" to be prevented from being separated from the ceramic base <NUM>, the bonding stress needs to be minimized while maintaining the bonding strength. Accordingly, the curvature inclined part <NUM>, <NUM>', <NUM>" that is rounded is formed at the edge of the metal layer <NUM>", <NUM>" in order to reduce a stress concentration by gradually reducing the thickness of the edge of the metal layer <NUM>", <NUM>".

The curvature inclined part <NUM>, <NUM>', <NUM>" may include a shape that protrudes to the direction of the outer circumference of the ceramic base <NUM>. For example, the curvature inclined part <NUM>, <NUM>', <NUM>" is formed in a concave shape in the direction of the ceramic base, and the length of the protrusion of the curvature inclined part is increased toward the direction of the ceramic base. Alternatively, the curvature inclined part <NUM>', <NUM>" may have a multi-stage structure in which a plurality of concave parts <NUM>, <NUM>, <NUM>', <NUM>' is formed and a protruded part <NUM>, <NUM>' is formed at a part at which the concave part <NUM>, <NUM> and the concave part <NUM>', <NUM>' are met. The protruded part <NUM>, <NUM>' has a pointed shape.

Alternatively, the curvature inclined part <NUM>', <NUM>" may have a two-stage structure in which two concave parts <NUM>, <NUM>, <NUM>', <NUM>' are formed and the protruded part <NUM>, <NUM>' is formed at a part at which the concave part <NUM>, <NUM> and the concave part <NUM>', <NUM>' are met.

A one-stage structure and the multi-stage structure may be mixed in the curvature inclined part <NUM>, <NUM>', <NUM>" formed at the edge of the metal layer <NUM>", <NUM>". For example, the curvature inclined part <NUM> having the one-stage structure may be formed at the edge of the metal layer <NUM>", <NUM>" on one side thereof, among the edges of the metal layers <NUM>" and <NUM>". The curvature inclined part <NUM>', <NUM>" having the multi-stage structure may be formed at the edge of the metal layer <NUM>", <NUM>" on the other thereof, among the edges of the metal layers <NUM>" and <NUM>". Alternatively, all of the curvature inclined part <NUM>', <NUM>" may be formed as the multi-stage structure along the edge of the metal layer <NUM>", <NUM>".

The length of the curvature inclined part <NUM> having the one-stage structure is formed to be relatively small compared to the thickness of the metal layer <NUM>", <NUM>" in order to strongly maintain the bonding strength while having a stress reduction function.

The curvature inclined part <NUM> having the one-stage structure can maintain the bonding strength although an interval between the metal layers <NUM>" and <NUM>" is narrow because an area where the metal layers <NUM>" and <NUM>" are bonded to the ceramic base <NUM> in the curvature inclined part <NUM> having the one-stage structure is relatively narrower than that in the curvature inclined part <NUM>', <NUM>" having the multi-stage structure.

The curvature inclined part <NUM>', <NUM>" having the multi-stage structure can strongly maintain the bonding strength because an area where the metal layers <NUM>" and <NUM>" are bonded to the ceramic base <NUM> in the curvature inclined part <NUM>', <NUM>" having the multi-stage structure is relatively wider than that in the curvature inclined part <NUM> having the one-stage structure. Instead, since an area where the curvature inclined part <NUM>', <NUM>" protrudes to the direction of the outer circumference of the ceramic base <NUM> is wide, it may be difficult to apply the curvature inclined part <NUM>', <NUM>" if an interval between the metal layers <NUM>" and <NUM>" that neighbor each other is narrow.

The metal layers <NUM>" and <NUM>" may include a curvature inclined part <NUM>', <NUM>" having a different shape on the outer circumference thereof that neighbors another metal layers <NUM>" and <NUM>" depending on an interval between the metal layers <NUM>" and <NUM>" and the another metal layers <NUM>" and <NUM>" adjacent to the metal layers <NUM>" and <NUM>".

The curvature inclined part <NUM>, <NUM>', <NUM>" reduces a thermal and electrical shock by preventing a stress concentration at the edges of the metal layers <NUM>" and <NUM>". Accordingly, long lifespan that is <NUM> to <NUM> times or more of the ceramic substrate <NUM>" is secured, and reliability is secured.

The ceramic substrate <NUM>" illustrated in <FIG> is the upper ceramic substrate on which the semiconductor chip is mounted. In another embodiment, a case in which the curvature inclined part <NUM>, <NUM>', <NUM>" is applied to the edge of the upper ceramic substrate <NUM>" has been described as an example, but the curvature inclined part <NUM>, <NUM>', <NUM>" may also be applied to the lower ceramic substrate.

The ceramic substrate <NUM>" is any one of an active metal brazing (AMB) substrate, a direct bonding copper (DBC) substrate, a direct brazed aluminum (DBA) substrate, and a thick printing copper (TPC) substrate. A case in which the ceramic substrate <NUM>" is the upper ceramic substrate <NUM>" on which the semiconductor chip G is mounted has been described as an example.

<FIG> and <FIG> are process flows for describing a method of manufacturing the upper ceramic substrate according to another embodiment of the present disclosure.

As illustrated in <FIG>, the curvature inclined part <NUM>, <NUM>', <NUM>" is formed by disposing a photomask m on one surface of the metal layer <NUM>", <NUM>" and etching the metal layer <NUM>", <NUM>" exposed by the photomask m.

Furthermore, the curvature inclined part <NUM>', <NUM>" having the multi-stage structure is formed by disposing a photomask m in which two or more holes have been adjacently formed on one surface of the metal layer <NUM>", <NUM>" and etching the metal layer <NUM>", <NUM>" exposed by the photomask m. If the photomask m in which two or more holes have been adjacently formed at a regular interval is used, the curvature inclined part <NUM>', <NUM>" having the multi-stage structure can be formed through one etching.

A process thereof may include step S10 of preparing the ceramic substrate, step S20 of forming the photomask, step S30 of forming the curvature inclined part, and step S40 of removing the photomask.

In step S10 of preparing the ceramic substrate, the ceramic substrate <NUM>, including the ceramic base <NUM> and the metal layers <NUM>" and <NUM>" that have been brazing-bonded to at least one surface of the ceramic base <NUM> is prepared. The ceramic substrate <NUM> may be prepared in which the thickness of the ceramic base <NUM> is <NUM> to <NUM> and the thickness of the metal layer <NUM>", <NUM>" is <NUM>.

In step S20 of forming the photomask, the photomask m in which two or more holes h have been adjacently formed on one surface of the metal layer <NUM>", <NUM>" may be formed. Two or more holes h that have been adjacently formed are for forming the curvature inclined part <NUM>', <NUM>" having the multi-stage structure.

Furthermore, a plurality of photomasks m having an area narrower than that of the metal layer <NUM>", <NUM>" may be formed.

In step S30 of forming the curvature inclined part, the multi-stage curvature inclined part <NUM>', <NUM>" that includes the curvature inclined part <NUM>' having an inclination rounded in the direction of the outer circumference of the ceramic base <NUM> toward the lower part of the metal layer <NUM>", <NUM>" or two or more rounded concave parts <NUM>, <NUM>, <NUM>', <NUM>' are formed by etching the metal layer <NUM>", <NUM>" exposed by the photomask m by using an etchant. Ferric chloride may be used as the etchant.

When the etchant is introduced into the two adjacent holes h, etching of about <NUM>% is performed, and the curvature inclined part <NUM>', <NUM>" having the two-stage structure a degree of etching of which is different may be formed by one etching. In the two-stage structure, a shape and length of the concave part may be adjusted based on the size of an adjacent hole and an interval between the holes.

Furthermore, the shape and length of the concave part may be adjusted by adjusting a concentration and etching time of the etchant.

In step S40 of removing the photomask, after the curvature inclined part <NUM>, <NUM>', <NUM>" is formed in the metal layer <NUM>", <NUM>", the photomask m formed on one surface of the metal layer <NUM>", <NUM>" is etched through an etchant. When the photomask m is removed by etching, the ceramic substrate <NUM>" having a final state is fabricated. The ceramic substrate <NUM>" is used as the upper ceramic substrate, and can increase the lifespan of the substrate by preventing a stress concentration at an edge thereof.

In the ceramic substrate <NUM>" illustrated in <FIG>, the curvature inclined part <NUM>, <NUM>', <NUM>" in which the one-stage structure and the multi-stage structure have been mixed has been illustrated for convenience of description. However, only the curvature inclined part <NUM> having the one-stage structure may be formed at the edge of the ceramic substrate <NUM>", or only the curvature inclined part <NUM>', <NUM>" having the two-stage structure may be formed at the edge of the ceramic substrate <NUM>".

For example, as illustrated in <FIG>, the curvature inclined part <NUM>" having the multi-stage structure may be formed at the edge of the metal layer <NUM>'.

The ceramic substrate <NUM>" fabricated by using the aforementioned method contributes to securing long lifespan and increasing reliability of the power module by being applied to the power module, because a stress concentration attributable to heat and a stress concentration attributable to an electrical shock are reduced at the edge of the ceramic substrate, compared to the upper ceramic substrate <NUM> of the embodiment.

Claim 1:
A power module (<NUM>) comprising:
a lower ceramic substrate (<NUM>);
an upper ceramic substrate (<NUM>, <NUM>', <NUM>") disposed over the lower ceramic substrate (<NUM>) and configured to have a semiconductor chip (G) mounted in a flip chip form on a lower surface of the upper ceramic substrate (<NUM>, <NUM>', <NUM>");
a PCB substrate (<NUM>) disposed over the upper ceramic substrate (<NUM>, <NUM>', <NUM>");a plurality of through holes (<NUM>, <NUM>) formed to correspond to the upper ceramic substrate (<NUM>, <NUM>', <NUM>") and the PCB substrate (<NUM>); and
a connection pin (<NUM>) formed in the through hole (<NUM>) of the upper ceramic substrate (<NUM>, <NUM>', <NUM>") and the through hole (<NUM>) of the PCB substrate (<NUM>) in a way to penetrate through the through holes (<NUM>, <NUM>) and configured to perpendicularly connect an electrode pattern (a, b, c) of the upper ceramic substrate (<NUM>, <NUM>', <NUM>") and an electrode pattern (d) of the PCB substrate (<NUM>);
wherein the connection pin (<NUM>) formed in the through hole (<NUM>, <NUM>) in a way to penetrate through the through holes (<NUM>, <NUM>) is bonded to the electrode pattern (a, b, c) of the upper ceramic substrate (<NUM>, <NUM>', <NUM>") at an edge of the through hole (<NUM>) by laser welding;
the power module further comprises a solder layer (<NUM>) coated on the electrode pattern (a, b, c) at the edge of the through hole (<NUM>) of the upper ceramic substrate (<NUM>, <NUM>', <NUM>"), melted upon the laser welding, and configured to bond the connection pin (<NUM>) to the electrode pattern (a, b, c) at the edge of the through hole (<NUM>) of the upper ceramic substrate (<NUM>, <NUM>', <NUM>").