Patent Description:
Unwanted memory commands have the ability to corrupt data, which may cause failures at the application and system level. Protection of data in a memory array has been proposed using various complex schemes which increase the cost and complexity of the system. At a system level, maintaining voltage sequences are costly when a system shutdown happens because power management is needed to manage these situations. But, without power management, there is always the potential that array data within memory component may be corrupted, for example, during an unsequenced power shutdown.

<CIT>, <CIT> and <CIT> describe systems pertaining to the technological background of the present invention.

The invention is defined in independent claims <NUM> and <NUM>.

Features and advantages of the claimed subject matter will be apparent from the following detailed description of embodiments consistent therewith, which description should be considered with reference to the accompanying drawings, wherein:.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.

Generally, this disclosure describes a system and method for data protection in a memory array. In some embodiments, the memory array is segmented into a plurality of partitions. At least one partition control circuit is provided that controls memory access and/or power management for at least one partition. The at least one partition control circuit is configured to generate an active/idle state signal indicative of whether the partition control circuitry is in an idle/low-power state or in an operational (memory access) state. Memory controller circuitry is configured to receive the state signal from the partition control circuitry and control a clock signal to the partition control circuitry. The memory controller circuitry is also configured to receive a memory access command that may be legitimate or illegitimate. A legitimate command may include, for example, memory read/write commands, force read command, reset only write command,, etc. Illegitimate commands include unwanted and/or spurious commands that may corrupt data in the array, and may include, for example, voltage coupling, power sequence operations, etc. If the command is legitimate, the memory controller may enable the clock signal for the partition control circuit to enable the partition control circuit to decode and process the legitimate command. While processing the legitimate command, the partition control circuit may change the state of the state signal to indicate an active state, and once completed, may change the state signal to indicate an idle state, so that the memory controller circuitry can decouple, or gate, the clock signal from the partition control circuit. Advantageously, this may enable the array partition to enter an idle and/or low power state while being protected from illegitimate commands.

<FIG> illustrates a system block diagram <NUM> consistent with several embodiments of the present disclosure. The system <NUM> includes a memory array <NUM>, partition control circuitry <NUM> that includes a plurality of partition control circuits 104A, 104B,. ,104N, clock multiplexing (MUX) circuitry <NUM> and memory controller circuitry <NUM>. In the embodiments described herein, the memory array <NUM> may be segmented (logically and/or physically) into a plurality of partitions (e.g., plurality of "panels" or "tiles", etc.) 102A, 102B,. The size of each memory partition 102A, 102B,. , 102N may be based on, for example, the size of the overall array <NUM>, memory addresses, physical location of memory structures, etc. Memory array <NUM> may include non-volatile memory structures (e.g., phase change or crosspoint memory, etc.) and/or volatile memory such as random access memory, cache memory, etc. In some embodiments, partition control circuits 104A, 104B,. ,104N are provided to control (e.g., read/write access control, power management control, etc.) of a respective partition 102A, 102B,. , 102N of the memory array <NUM>. In other embodiments, a partition control circuit, e.g., partition control circuitry 104A may control more than one memory partition, e.g., partitions 102A and 102B, and thus there may be less than N number of individual partition control circuits. Memory controller circuitry <NUM> is generally configured to receive a memory access command <NUM> and control application of a clock signal <NUM> to at least one partition control circuit 104A, 104B,. ,104N, as will be described below. The memory access command <NUM> may be generated by, for example, a central processing unit (e.g., system CPU, not shown) and/or subset thereof (e.g., one or more cores of a system CPU, etc., not shown) executing one or more applications (also not shown) which require access to memory array <NUM>.

In one embodiment, partition control circuit 104A, 104B,. ,104N are each configured to generate and propagate an active/idle signal 105A, 105B,. The active/idle signal 105A, 105B,. ,105N is indicative of the state of at least one partition control circuit 104A, 104B,. The "state", as used herein, means either an active state in which at least one partition control circuit 104A, 104B,. , and/or104N is decoding and/or processing a legitimate memory access command, or an idle/low-power state in which the partition control circuit 104A, 104B,. , and/or104N is gated from memory controller circuitry <NUM>. In one embodiment, the first partition control circuit 104A is configured to receive an idle signal <NUM> and propagate the idle signal as the active/idle signal 105A if the partition control circuit 104A is not processing a memory access command. The idle signal <NUM> may include, for example, an available reference voltage (e.g., Vcc, etc.). If any of the partition control circuits 104A, 104B,. , and/or 104N is in an active state, that partition control circuit is configured to change the state of the active/idle signal 105A, 105B,. , and/or 105N to indicate an active state. The last partition control circuit 104N is configured to transmit the active/idle signal 105N to the memory controller circuitry <NUM>. Since any of the partition control circuits 104A, 104B,. , and/or 104N can change the state of a respective active/idle signal 105A, 105B,. , and/or 105N, the last active/idle signal 105N is indicative of all partition control circuits 104A, 104B,. , and 104N being in an idle/low-power state, or at least one partition control circuit 104A, 104B,. , and/or104N being in an active state. In another embodiment, instead of propagating a respective active/idle signal 105A, 105B,. , 105N through each partition control circuitry 104A, 104B,. ,104N , each active/idle signal 105A, 105B,. , 105N may be transmitted directly to memory controller circuitry <NUM>, at the possible expense of additional pinout requirements and/or bus and bus control requirements.

The memory controller circuitry <NUM> is generally configured to gate the application of clock signal <NUM> to at least one partition control circuit 104A, 104B,. , and/or 104N based on, at least in part, the type of memory access command <NUM> received by the memory controller circuitry <NUM>. As described above, a memory access command <NUM> may generally be legitimate or illegitimate. Accordingly, memory controller circuitry <NUM> may also include memory access command determination logic <NUM> generally configured to determine if a memory access command <NUM> is legitimate or illegitimate. To that end, memory access command determination logic <NUM> may be configured to parse an incoming memory access command to determine certain features of the command that trend to demonstrate that the memory access command <NUM> is legitimate or illegitimate. Features that may demonstrate that the memory access command <NUM> is legitimate include, for example, command decode information, proper clock signaling, etc. while features that may demonstrate that the memory access command <NUM> is illegitimate include, for example, voltage coupling, power sequence operations, etc.. Memory controller circuitry <NUM> may remain in a low power/idle state in the absence of a memory access command <NUM>.

If a memory access command <NUM> is determined to be legitimate, memory controller circuitry <NUM> is configured to turn on a clock signal <NUM> to enable at least one partition control circuit 104A, 104B,. , and/or 104N to decode and/or process the memory access command <NUM>. The clock signal <NUM> may include a clock signal <NUM> received from a system clock generator (not shown), etc., and may further include a clock signal <NUM> from a different clock domain. The clock MUX circuitry <NUM> is generally configured to receive a clock signal <NUM> and route a similar clock signal <NUM> to at least one partition control circuit 104A, 104B,. , and/or 104N, depending on, for example, address information identified in the memory access command <NUM>. In some embodiments, clock MUX circuitry <NUM> is configured to route the clock signal <NUM> only to the partition control circuit 104A, 104B,. , and/or 104N that will be processing (or is processing) the memory access command <NUM>. Once the clock signal <NUM> is applied to one or more of the partition control circuitry 104A, 104B,. , and/or 104N, memory controller may transmit a wake up signal, via bus <NUM>, to the place the appropriate partition control circuitry 104A, 104B,. , and/or 104N in a condition to receive and process (decode) the memory access command <NUM>. Once the appropriate partition control circuit 104A, 104B,. , and/or 104N is in a state that is ready to process (which may be verified by a wake-up handshake signal, etc.), the memory access command <NUM> may be transmitted to the appropriate partition control circuit 104A, 104B,. , and/or 104N for decoding/processing, via bus <NUM>. Data associated with the memory access command <NUM> and any data results from the memory access command (e.g., read results) may be transmitted between the memory controller circuitry <NUM> and the appropriate partition control circuit 104A, 104B,. , and/or 104N, via bus <NUM>.

As described above, if at least one partition control circuit 104A, 104B,. , and/or 104N is processing a memory access command <NUM>, the state of the active/idle signal 105A, 105B,. , and/or 105N may indicate an active state. Accordingly, memory controller circuitry <NUM> is configured to enable the clock signal <NUM> for as long as the active/idle signal 105A, 105B,. , and/or 105N indicates an active state. Once any or all of the circuits 104A, 104B,. , and/or 104N has completed processing of a memory access command <NUM>, and the corresponding the active/idle signal 105A, 105B,. , and/or 105N changes state from active to idle, memory controller circuitry <NUM> is configured to disable (e.g., gate) the clock signal <NUM> (and correspondingly, clock signal <NUM>) to the appropriate circuitry 104A, 104B,. , and/or 104N. More than one legitimate memory access command <NUM> for a particular partition 102A, 102B,. , and/or 102N may be received by memory controller circuitry <NUM>. In such a case, memory controller circuitry <NUM> may be configured to queue the memory access commands <NUM> and maintain the clock signal until all such commands have been executed. This may reduce lag time associated with waking up of partition control circuit 104A, 104B,. , and/or 104N between memory access commands <NUM>. If memory access command determination logic <NUM> determines that a memory access command <NUM> is illegitimate, the memory controller circuitry may keep the clock signal <NUM> disabled for all or any of the partition control circuits 104A, 104B,. , and/or 104N. In some embodiments, memory controller circuitry <NUM> may be configured to generate a signal that indicates that the received memory access command <NUM> is illegitimate. Thus, partition control circuitry 104A, 104B,. , and/or 104N and/or corresponding partitions 102A, 102B,. , and/or 102N may enter a low power state and may be protected from spurious and/or unwanted (illegitimate) memory access commands.

<FIG> illustrates a flowchart <NUM> of operations of memory controller circuitry consistent with one embodiment of the present disclosure. The operations may be performed, for example, by memory controller circuitry <NUM> (<FIG>) and/or other memory controller circuitry. Operations of this embodiment include maintaining memory controller circuitry (MCC) in an idle state <NUM>, and determining if a memory access (MA) command is received <NUM>. If no MA is received <NUM>, operations may include maintaining the MCC in an idle state <NUM>. If a MA command is received (<NUM>), operations may also include determining if the MA command is legitimate <NUM>. If the MA command is not legitimate (illegitimate) (<NUM>), operations may include operations may include maintaining the MCC in an idle state <NUM>. If the MA command is legitimate (<NUM>), operations may include determining if a clock (CLK) signal is enabled <NUM>, and if so (indicating that a current MA command is being executed), queuing the MA command <NUM> to be performed after the current command operations are complete. If the CLK signal is not enabled (<NUM>), operations may include enabling the CLK signal to at least one partition control circuit (PCC) <NUM>. Operations may also include transmitting a wake-up signal to the at least one PCC <NUM>. The wake-up signal may be a handshake and/or other signal type to enable the PCC to transition from a low-power and/or idle state to an active state. Operations may also include transmitting the MA command to the PCC <NUM>. Operations may also include determining if there are any queued MA commands <NUM>, and if so, transmitting the queued commands to the PCC <NUM>, thus avoiding unnecessary clock cycling and/or wake-up transitions. Once the MA command is completed by the at least one PCC (and once any results have been transmitted to the MCC), operations may also include disabling the CLK signal <NUM>, to permit, for example, the PCC to transition to a low-power state and to gate illegitimate memory access commands.

<FIG> illustrates a flowchart <NUM> of operations of memory controller circuitry consistent with another embodiment of the present disclosure. The operations may be performed, for example, by memory controller circuitry <NUM> (<FIG>) and/or other memory controller circuitry. Operations of this embodiment include receiving, by a memory controller, an active/idle signal from a partition control circuit <NUM>. The partition control circuit controls at least one partition of a memory array, and the active/idle signal has a state indicative of one of an active state or an idle state of the partition control circuit. Operations may also include receiving, by the memory controller, a memory access command <NUM>. Operations may also include determining, by the memory controller, if the memory access command is legitimate <NUM>. Operations may also include enabling, by the memory controller for the partition control circuit, a clock signal if the memory access command is legitimate and the active/idle signal is in an idle state <NUM>.

<FIG> illustrates a flowchart <NUM> of operations of partition control circuitry consistent with one embodiment of the present disclosure. The operations may be performed, for example, by partition control circuit, e.g., circuit 104A (<FIG>) and/or other circuitry associated with a partition of a memory array. Operations of this embodiment include maintaining the partition control circuit (PCC) in an idle and/or low-power state <NUM>. Operations may also include maintaining an active/idle (A/I) signal in an idle state <NUM>. Operations may also include determining, by the PCC, if a wake-up signal has been received <NUM>. The wake-up signal may be generated by, for example, a memory controller to enable the PCC to transition from an idle state to an active state. If no wake-up signal is received (<NUM>) the PCC may remain in an idle state <NUM>. If a wake-up signal is received (<NUM>), operations may include transitioning the A/I signal to an active state <NUM> and receiving a memory access (MA) command <NUM> from, for example, the memory controller. Operations may also include processing the MA command and returning any results to the memory controller <NUM>. Operations may also include determining if there are any additional MA commands <NUM>, and if so processing those commands <NUM>. Once all commands have been processed, operations may also include transitioning the A/I signal to an idle state <NUM>.

While <FIG> illustrate various operations according various embodiments, it is to be understood that not all of the operations depicted in <FIG>, <FIG> or <FIG> are necessary for other embodiments. Indeed, it is fully contemplated herein that in other embodiments of the present disclosure, the operations depicted in <FIG> , <FIG> and/or <NUM>, and/or other operations described herein may be combined in a manner not specifically shown in any of the drawings, but still fully consistent with the present disclosure. Thus, claims directed to features and/or operations that are not exactly shown in one drawing are deemed within the scope and content of the present disclosure.

As used in any embodiment herein, the term "logic" may refer to an application, software, firmware and/or circuitry configured to perform any of the aforementioned operations. Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on non-transitory computer readable storage device. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices. "Circuitry" and "circuitry", as used in any embodiment herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The circuitry may include a processor and/or controller configured to execute one or more instructions to perform one or more operations described herein. The instructions may be embodied as, for example, an application, software, firmware, etc. configured to cause the circuitry to perform any of the aforementioned operations. Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on a computer-readable storage device. Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices. The circuitry may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), an application-specific integrated circuit (ASIC), a system on-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smart phones, etc..

Any of the operations described herein may be implemented in a system that includes one or more storage devices having stored thereon, individually or in combination, instructions that when executed by one or more processors perform one or more operations. Also, it is intended that operations described herein may be distributed across a plurality of physical devices, such as processing structures at more than one different physical location. The storage devices may include any type of tangible device, for example, any type of disk including hard disks, floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, Solid State Disks (SSDs), magnetic or optical cards, or any type of media suitable for storing electronic instructions. Other embodiments may be implemented as software executed by a programmable control device. As described herein, various embodiments may be implemented using hardware elements, software elements, or any combination thereof.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment.

Claim 1:
An apparatus (<NUM>) comprising:
a memory controller (<NUM>) to receive legitimate and illegitimate memory access commands to access a partition included in a plurality of partitions of a memory array (<NUM>); and
partition control circuitry (<NUM>) to:
receive a clock signal to enable execution of a legitimate memory access command;
indicate, via an active/idle signal, an active state while the legitimate memory access command is executed; and
indicate, via the active/idle signal, an idle state responsive to completion of execution of the legitimate memory access command,
wherein the memory controller is configured to receive the active/idle signal from the partition control circuitry, and to control the clock signal for the partition control circuitry based on the active/idle signal.