Patent Description:
Processing systems can use different types of transactions to move data. A first processing system may use memory-mapped transactions to move data to a specific memory address of a recipient processing system. A second processing system may use a stream transaction to send data to a recipient processing system that is then tasked of determining how to handle the received data. Using different forms of transactions within a system can be inefficient and can complicate memory management. <CIT> describes streaming data packets on peripheral component interconnect and on-chip bus interconnects.

In accordance with the invention, there is provided a multi-processor unified memory management system, and a method for using a unified memory management system, as set forth in the claims.

Embodiments detailed herein disclose the use of a memory management module (MMM) that can allow for a flat memory map to be used across a multiple processor system. The MMM can have the ability to handle both memory map and stream inter-chip transactions. Communication between processors may be performed using stream-based transactions across a high speed interface.

When a memory transaction is to be performed by a programmable processor, such as a field programmable gate array (FPGA), the memory transaction may be routed to an NΠVIM implemented as part of the processor. The MMM may have stored a flat memory map that defines how memory is assigned across multiple processors, including the first processor on which the MMM is implemented. MMMs on the other processors in communication with the first processor can store the same memory map. Based on the received memory transaction, the MMM may determine whether a locally-accessible memory (e.g., random access memory, RAM, local buffer) is to be accessed or if a memory accessible via another processor is to be accessed. If the memory transaction involves the locally-accessible memory, the MMM may perform a memory-mapped transaction directly with the locally-accessible memory. If the memory transaction involves a memory of another processor, the processor may determine the appropriate processor to transmit the memory transaction to and may translate the memory transaction into a stream-based memory transaction. This stream-based memory transaction can include coded memory address data. The stream-based memory transaction may then be sent via a high speed inter-chip link to the appropriate processor. An MMM of the processor that receives the stream-based memory transaction may decode the coded memory address data and store to the appropriate locally-accessible memory. While stream-based memory transactions are typically used for data processing-related memory transactions, all inter-chip memory transactions between MMMs of processors may be handled using stream-based memory transactions.

Such an arrangement can have one or more distinct advantages. For a multiple processor system, a single simple memory map can be implemented that is common across all processors. Each processor can be configured to access and use the entire memory, even though various portions of the memory are only directly accessible via a particular IC. The MMM of each processor can handle routing of memory transactions to the appropriate processor and can handle both memory-mapped and stream based memory transactions. Therefore, when inter-chip communication is necessary for a memory transaction, the MMMs handle conversion, if needed, of the memory transaction into a stream-based transaction that includes encoded memory address data and decoding of the stream-based transaction upon receipt.

Additionally or alternatively, such an arrangement that uses MMMs can allow for priority-based routing among various memory mapped and non-memory-mapped transactions. Such an arrangement can allow for a particular quality of service (QoS) to be realized for particular processes that are dependent on memory transactions being performed within a certain amount of time. Based upon an indicated priority level, certain memory transactions can be performed out-of-turn from other memory transactions in an attempt to realize the QoS.

Further details and benefits of these embodiments and other embodiments are provided in relation to the figures. <FIG> illustrates an embodiment of a multi-processor unified memory management system <NUM> ("system <NUM>"). System <NUM> can include: processor <NUM>; processor <NUM>; memory <NUM>; memory <NUM>; and inter-chip link <NUM>.

Processor <NUM> and processor <NUM> may be various forms of processors on which customized modules can be implemented. For instance, processor <NUM> and processor <NUM> may be various types of FPGAs on which code can be implemented using programmable hardware. For example, one or both of FPGAs may be a multiple processor system on a chip (MPSoC). On each of processors <NUM> and <NUM>, a separate instance of an MMM (<NUM>-<NUM>, <NUM>-<NUM>) may be implemented. Each MMM may handle two primary tasks: <NUM>) routing memory transactions appropriately; and <NUM>) performing any conversion or translation needed to the memory transaction.

Native processing <NUM> of processor <NUM> may be implemented as firmware based on code or as executed software written by a person or obtained from some other source. MMM <NUM>-<NUM> may be implemented as a code module that is similarly implemented as firmware (or software) on processor <NUM>. In other embodiments, MMMs may be implemented using hardware particularly designed for the purpose. Native processing <NUM> may generate either a memory-mapped or a stream-based memory transaction. Regardless of whether the memory transaction output by native processing <NUM> is memory-mapped or stream-based, the transaction can be routed to MMM <NUM>-<NUM>. (Therefore, MMM <NUM>-<NUM> handles all forms of memory transactions for native processing <NUM>. ) MMM <NUM>-<NUM> may maintain a memory map that includes memory <NUM> of processor <NUM> and memory <NUM> of processor <NUM>. A first address range may be mapped to processor <NUM> while a second memory address range may be mapped to processor <NUM>. If a memory transaction received by MMM <NUM>-<NUM> corresponds to a memory address mapped to processor <NUM>, the memory transaction may be performed directly by MMM <NUM>-<NUM> with memory <NUM>. Memory transactions conducted by MMM <NUM>-<NUM> with memory <NUM> can be memory mapped transactions.

If a memory transaction received by MMM <NUM>-<NUM> from native processing <NUM> indicates a memory address mapped to processor <NUM>, the memory transaction may be transmitted by MMM <NUM>-<NUM> via inter-chip link <NUM> to MMM <NUM>-<NUM>. Native processing <NUM> of processor <NUM>, may be able to generate a transaction using a memory mapped protocol (e.g., AXI4-memory mapped transactions) and/or a transaction using a stream protocol (e.g., AXI4-stream protocol data transfer transactions). In a memory mapped transaction, all transactions involve the use of a target memory address. In contrast, a stream transaction does not include a memory address associated with the transaction. A stream transaction (e.g., an AXI stream transaction) can allow for a unidirectional channel for data flow. A stream transaction may tend to provide better performance compared to a memory mapped transaction due to less overhead data being involved. Therefore, for communications between processors, AXI stream based transactions may be preferable.

MMM <NUM>-<NUM> may serve to convert a transaction to a stream transaction prior to sending via inter-chip link <NUM>. The transaction may then be sent to MMM <NUM>-<NUM>. MMM <NUM>-<NUM>, which has the same memory map as MMM <NUM>-<NUM>, may then perform the memory transaction using memory <NUM>. MMM <NUM>-<NUM> may translate the received stream protocol transaction into a memory-mapped transaction to perform the memory transaction with memory <NUM>. Encoded within the stream protocol transaction or sent via a sidelink transaction may be memory address information added by MMM <NUM>-<NUM>. MMM <NUM>-<NUM> may decode these memory address information and use it to create the memory mapped transaction.

The memory address information may be sent by MMM <NUM>-<NUM> to MMM <NUM>-<NUM> using in-band signaling. In-band signally can involve a data header being sent before or after the data payload on the inter-chip link as part of the stream protocol transaction. Alternatively, side-band signaling may be used. An inter-chip link protocol, such as Interlaken, can support built-in low bandwidth sideband bus communications. Such arrangements allow for higher speed data transmissions in-band and lower speed transmissions via a side-band. Side-band signaling can include a memory address and control messages being sent on a low-bandwidth (relative to the high-bandwidth using to transmit the data payload), out-of-band inter-chip link. Therefore, using side-band signaling, a different frequency may be used for communication than the data.

As another alternative, efficient side-band signaling may be used. In efficient side-band signaling, the destination memory address is sent in-band; however, the identity (ID) of the target processor and routing metadata is sent through a low-bandwidth side-band link. Such an arrangement allows for the receiving MMM to not need to decode or analyze the incoming data payload to obtain a memory address. Therefore, the in-band data payload and address can be encrypted when transmitted between MMMs, while using the unencrypted metadata passed on the side-link to facilitate routing and handling of the data payload.

MMM <NUM>-<NUM> may function the same as MMM <NUM>-<NUM>. Therefore, MMMs <NUM> may each handle memory read and write transactions to a local memory and remote memory that are part of a common flat memory map, along with handling any protocol translations necessary between a memory-mapped protocol and a stream protocol. A common piece of code may be used to implement MMMs <NUM>. A difference between MMMs <NUM> may be which address range within a common flat memory map each MMM can access directly. From the point-of-view of native processing <NUM> and native processing <NUM>, the entire memory map can be treated the same. Each MMM of MMMs <NUM> properly routes, translates, and responds to the memory transactions as needed.

<FIG> illustrates another embodiment of a multi-processor unified memory management system <NUM> ("system <NUM>"). In system <NUM>, a more complicated multi-chip architecture is present. It should be understood that the number and arrangement of processors is merely an example. System <NUM> can include: FPGA <NUM>; FPGA <NUM>; FPGA <NUM>; and MPSoC <NUM>. FPGAs <NUM>, <NUM>, and <NUM> can have various modules that are created as code and used to configure the FPGAs. FPGA <NUM> can include native processing <NUM> and MMM <NUM>-<NUM>. MMM <NUM>-<NUM> may communicate directly with memory <NUM>. Only FPGA <NUM> may be able to directly access memory <NUM>; therefore, memory transactions that involve the portion of the system memory map corresponding to memory <NUM> may be required to be performed via MMM <NUM>-<NUM>.

FPGA <NUM> can include native processing <NUM>, MMM <NUM>-<NUM>, and local buffer <NUM>. Native processing <NUM> and MMM <NUM>-<NUM> may function as detailed in relation to the native processing and MMMs of system <NUM>. However, MMM <NUM>-<NUM> may be configured to access an additional type of memory, such as local buffer <NUM>. Local buffer <NUM> can represent high speed memory that is on-board FPGA <NUM>. Local buffer <NUM> can be included as part of the system-wide common flat memory map and may be accessed via memory mapped transactions by MMM <NUM>-<NUM>. Therefore, a memory transaction conducted by any of FPGAs <NUM>, <NUM>, <NUM>, or MPSoC <NUM> may be routed to and handled by MMM <NUM>-<NUM>.

FPGA <NUM> can include native processing <NUM>, MMM <NUM>-<NUM>, and data local area network (LAN) <NUM>. Native processing <NUM> and MMM <NUM>-<NUM> may function as detailed in relation to the native processing and MMMs of system <NUM>. However, MMM <NUM>-<NUM> may be additionally configured to communicate with data LAN <NUM>. Data LAN <NUM> may serve as an interface for input and output of user data, such as via one or more user interfaces. Data exchanged with data LAN <NUM> may be via a stream protocol, therefore transactions conducted between MMM <NUM>-<NUM> and data LAN <NUM> may be converted to a stream protocol, if needed.

MPSoC <NUM> includes multiple on-board processors. For example, MPSoC <NUM> can include FPGA <NUM> and processing subsystem <NUM>. FPGA <NUM> may include native processing <NUM> and MMM <NUM>-<NUM>. Processing subsystem <NUM> may include one or more other types of processors, such as processor <NUM>. Processor <NUM> could be a RISC-based processor (e.g., from ARM). MPSoC <NUM> may have multiple dedicated memories. MMM <NUM>-<NUM> may control access to memory <NUM> and memory <NUM>. A memory mapped protocol may be used by MMM <NUM>-<NUM> for communication with memory <NUM> and memory <NUM>. Further MMM <NUM>-<NUM> may allow for processor <NUM> to perform a memory mapped transaction with FPGA <NUM> or any of FPGAs <NUM>, <NUM>, and <NUM>. MMM <NUM>-<NUM>, similar to the other instances of NΠVIMs <NUM> may translate a memory mapped protocol transaction into a stream protocol transaction. When a memory mapped protocol transaction, the memory address information included as part of the memory mapped protocol transaction may be embedded as part of the stream protocol transaction such that the memory address information can be extracted by the receiving MMM.

Multiple high-speed inter-chip links are present between FPGAs <NUM>, <NUM>, <NUM>, and MPSoC <NUM>. FPGA <NUM> may communicate with FPGA <NUM> via inter-chip link <NUM>. FPGA <NUM> may communicate with FPGA <NUM> via inter-chip link <NUM>. FPGA <NUM> may communicate with FPGA <NUM> via inter-chip link <NUM>. It should be understood that this hub-and-spoke arrangement around FPGA <NUM> is merely an example. Additional or alternate inter-chip links may be present. For example, FPGA <NUM> may have a second inter-chip link to, for example, FPGA <NUM>.

Each MMM of MMMs <NUM> may only have data stored indicating to which processor a memory transaction should be forwarded. For example, the flat memory map maintained by MMM <NUM>-<NUM> may indicate a first range of memory addresses that correspond to memory <NUM>. All other memory addresses may correspond to FPGA <NUM> and MMM <NUM>-<NUM>. However, upon receipt of a memory transaction from MMM <NUM>-<NUM>, MMM <NUM>-<NUM> may need to perform further forwarding, such as to FPGA <NUM> or FPGA <NUM>. Further, each MMM of MMM <NUM> can handle stream-based memory transactions (or another form of non-memory mapped memory transactions) and memory mapped memory transactions in immediate succession.

As an example of such an arrangement, native processing <NUM> may conduct a memory transaction with a particular memory address. The memory transaction may be sent to MMM <NUM>-<NUM> by native processing <NUM>. MMM <NUM>-<NUM> may determine that the memory transaction corresponds to a memory address in the flat memory map that corresponds to FPGA <NUM>. The memory transaction may be sent via a stream transaction to FPGA <NUM> and received by MMM <NUM>-<NUM>. MMM <NUM>-<NUM> may analyze the stream transaction to extract memory address information. MMM <NUM>-<NUM> may access the flat memory map and determine that the memory address corresponds to FPGA <NUM> and MMM <NUM>-<NUM>. A second memory transaction may be sent via a stream transaction to FPGA <NUM> by FPGA <NUM> and received by MMM <NUM>-<NUM>. MMM <NUM>-<NUM> may analyze the stream transaction to extract memory address information and may then conduct the memory transaction locally with memory <NUM>. Therefore, from the point-of-view of MMM <NUM>-<NUM>, the flat memory map indicates that the memory transaction should be sent to FPGA <NUM>. The flat memory map of MMM <NUM>-<NUM>, which corresponds to the same addresses, indicates that the memory transaction is to be sent via inter-chip link <NUM> to FPGA <NUM>. The memory map of MMM <NUM>-<NUM> indicates the memory transaction is to be handled directly with memory <NUM>.

Therefore, an advantage to at least some of the arrangements detailed herein is that the MMM transmitting the memory transaction has the memory address destination, but does not need all of the details of the route for the transaction to the memory address. Rather, the MMM transmitting the memory transaction determines the next MMM to which the memory transaction should be transmitted. This next MMM determines the next hop toward the memory address destination (if a next hop is needed). Such an arrangement can further allow for a stream transaction to be transmitted without the destination memory address being known. Rather, the stream memory transaction can be routed based on a destination processor identifier. A separate memory address space may be maintained that is mapped to only the processor identifier and the local MMM determines the specific memory addresses.

<FIG> illustrates an embodiment of a flat memory map <NUM> created using a unified memory management system. Flat memory map <NUM> may be common across all processors of a unified memory management system, such as system <NUM> of <FIG>. Memory map <NUM> indicates five memory address blocks: memory block <NUM>; memory address block <NUM>; memory address block <NUM>; memory address block <NUM>; and memory address block <NUM>. The version of memory map <NUM> stored by each MMM can include the same data stored at the same memory addresses.

The example of <FIG> corresponds to system <NUM>. In this example, memory address block <NUM> corresponds to a memory (e.g., DDR RAM, local buffer) in direct communication with FPGA <NUM>, memory address block <NUM> corresponds to a memory in direct communication with FPGA <NUM>; memory address block <NUM> corresponds to a memory in direct communication with FPGA <NUM>; memory address block <NUM> corresponds to a memory in communication with FPGA <NUM>; and memory address block <NUM> corresponds to a memory in direct communication with processing subsystem <NUM>.

While each memory map may correspond to the same data, each memory map may differ in how various memory address blocks are mapped for access. From the perspective of MMM <NUM>-<NUM>, memory transactions involving memory address within memory address block <NUM> may be directly handled; memory transactions involving memory addresses within memory address blocks <NUM>-<NUM> may be forwarded to FPGA <NUM> via inter-chip link <NUM>. In contrast, from the perspective of MMM <NUM>-<NUM>, memory transactions involving memory address within memory address block <NUM> may be forwarded to FPGA <NUM> via inter-chip link <NUM>; memory transactions involving memory addresses within memory address block <NUM> may be directly handled, memory transaction involving memory addresses within memory address block <NUM> may be forwarded to FPGA <NUM> via inter-chip link <NUM>; and memory transaction involving memory addresses within memory address blocks <NUM> and <NUM> may be forwarded to FPGA <NUM> via inter-chip link <NUM>. Therefore, while each processor may have access to the entire memory map, the routing of memory transactions within a system can be controlled by MMMs based on stored flat memory maps.

Various methods may be performed using the systems and memory mapping arrangements detailed in relation to <FIG>. <FIG> illustrates an embodiment of a method <NUM> for using a unified memory management system. Method <NUM> can involve the use of systems arranged similar to system <NUM> and system <NUM>.

At block <NUM>, a memory transaction may be received from a local native processing component. Block <NUM> may be performed by an MMM being executed by the processing system that is performing native processing. The memory transaction may be a stream-based memory transaction (or another form of non-memory mapped memory transaction) or a memory mapped memory transaction. The MMM can be configured to handle both types of memory transactions in immediate succession. Therefore, the native processing process may transmit a memory request to the MMM. The native processing process may not have visibility as to whether the memory transaction involves local memory or data stored in memory of another processor.

At block <NUM>, the MMM may determine if the memory transaction involves local or remote memory. The MMM may make the determination by a memory address of the request. Since a single memory map is used across the entire, multi-processor system, one or more ranges of memory addresses are mapped to the local memory.

Block <NUM> is performed if block <NUM> was determined to involve a local memory transaction. At block <NUM>, the MMM may directly access the local memory and perform the memory transaction, such as writing to the memory address or reading from the memory address.

Block <NUM> is performed if block <NUM> was determined to involve a remote memory transaction. That is, the memory transaction involves accessing memory that is only in direction communication with another processor of the system. At block <NUM>, the MMM may translate the memory transaction into a stream-based memory transaction that includes memory location data encoded as part of the transaction output by the MMM. If the processor is in communication with multiple processors, the appropriate processor to which the memory transaction is to be sent may be selected. The appropriate processor may be selected based on the memory address.

At block <NUM>, the memory transaction output by the MMM may be forwarded via an inter-chip link <NUM> to another processor, which may have been selected as part of block <NUM>. At block <NUM>, the memory transaction is received by the other processor via the inter-chip link. The memory transaction may be analyzed by an MMM of the processor that received the memory transaction. The MMM may then determine at block <NUM>, based on the encoded memory location, whether the memory address is directly accessible by the processor that received the memory transaction or if the memory transaction needs to be forwarded again. If forwarded again, the transaction may be translated and forwarded at blocks <NUM> through <NUM> until the memory transaction arrives at the correct processor. In most implementations, no more than four or five processors may be chained together, and thus forwarding of a memory transaction may occur at most only a few times. However, in some implementations many more processors may be chained together and forwarding of the memory transaction may need to be performed many times.

Claim 1:
A multi-processor unified memory management system, comprising:
a first programmable processor system (<NUM>) configured to communicate via an inter-chip link (<NUM>) with a second programmable processor system, wherein the first programmable processor system (<NUM>) comprises:
a first inter-chip memory management module (<NUM>-<NUM>) configured to:
analyze memory access transactions;
translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and
translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and
the second programmable processor system (<NUM>) configured to communicate via the inter-chip link (<NUM>) with the first programmable processor system (<NUM>), wherein the second programmable processor system (<NUM>) comprises:
a second inter-chip memory management module (<NUM>-<NUM>) configured to:
analyze memory access transactions;
translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and
translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and
characterized in that:
the first inter-chip memory management module (<NUM>-<NUM>) and the second inter-chip memory management module (<NUM>-<NUM>) are configured to use a common flat memory map.