Patent Description:
RRAM, also known as ReRAM (resistive random access memory), is a form of nonvolatile data storage that operates by changing the resistance of a specially formulated solid dielectric material. An RRAM device contains a component called a memristor whose resistance varies when different voltages are imposed across it.

Normally, a dielectric material does not conduct electric current. However, if the dielectric material is subjected to a high enough voltage, it will suddenly conduct because of dielectric breakdown. In a conventional dielectric material, dielectric breakdown causes permanent damage and failure of the associated component. In a memristor, the dielectric breakdown is temporary and reversible because of the materials that are used. In one form of memristor, a deliberately applied voltage causes the medium to acquire microscopic conductive paths called filaments. The filaments appear as a result of various phenomena such as metal migration or physical defects. Once a filament appears, it can be broken or reversed by the application of a different external voltage. The controlled formation and destruction of filaments in large numbers allows for storage of digital data. The voltage that is used initially to cause the medium to acquire the microscopic conductive paths is called the forming voltage.

An RRAM device is placed in a low resistance state by applying a forming voltage that causes the dielectric to assume a resistance level that is below a given resistance threshold. RRAM devices that are in a low resistance state (LRS) that are exposed to moisture can exhibit retention failure. The retention failure is characterized by the drifting of bits in a low resistance state to a higher resistance than a given reference resistance level (RL).

In a previous approach a transistor that is more powerful than is conventionally used is employed to generate high write currents in order to program devices into a LRS with a thicker filament. This approach oftentimes requires a larger transistor than is conventionally used. The larger transistors occupy more space and thus can result in reduced memory density. Moreover, the larger RRAM filaments that are formed can result in decreased endurance.

<CIT> discloses a memory cell that includes a first conducting layer, a reversible resistance switching element above the first conducting layer, a second conducting layer above the reversible resistance switching element, and a liner disposed about a sidewall of the reversible resistance switching element. The resistance switching element is made of a stoichiometric metal oxide material such as Al<NUM>O<NUM>, and the liner is formed from the same material.

<CIT> discloses a non-volatile memory device comprising a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; an insulative side wall protective layer comprising silicon nitride or aluminum oxide, for example, covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; an electrically-conductive layer connected to the second electrode; and a connection layer between the second electrode and the electrically conductive layer.

<CIT> discloses a nonvolatile memory device including an insulating layer, oxygen diffusion prevention layers disposed on the insulating layer, a plurality of contact plugs, each of the plurality of the contact plugs penetrating through each of the plurality of the oxygen diffusion prevention layers and at least a part of the insulating layer, and a plurality of resistance-variable elements, each of the plurality of the resistance-variable elements covering each of the plurality of the contact plugs exposed on surfaces of the oxygen diffusion prevention layers and being electrically connected to each of the plurality of the contact plugs. Each resistance-variable element includes a sidewall protection layer which covers the entire periphery of a lower electrode, a resistance-variable layer, and an upper electrode and is formed of, for example, silicon nitride or aluminum oxide. An oxygen diffusion prevention layer, e.g., of oxygen-deficient oxide or silicon nitride, flush with the outer edge of the sidewall protection layer, may be formed thereunder.

<CIT> and <CIT> disclose further similar nonvolatile memory cells, including a transition metal oxide data storage layer extending between first and second electrodes, all protected by a diffusion barrier capping layer of aluminum oxide.

Further advantageous features are set out in the dependent claims.

RRAM retention improvement by high-k encapsulation of RRAM devices is described. It should be appreciated that although embodiments are described herein with reference to example high-k encapsulation of RRAM device implementations, the disclosure is more generally applicable to retention improvement by high-k encapsulation of RRAM device implementations as well as other type retention improvement by high-k encapsulation of RRAM device implementations. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

RRAM devices in the low resistance state (LRS) that are exposed to moisture can experience retention failure. The retention failure is characterized by the drifting of bits in a low resistance state to a resistance that is higher than a given reference resistance level (RL). In a previous approach to addressing retention failure, a transistor that is more powerful than is conventionally used is employed to generate high write currents in order to program devices into a LRS with a thicker filament. This approach oftentimes requires a larger transistor than is conventionally used. The larger transistors occupy more space and thus can result in reduced memory density. Moreover, the larger RRAM filaments can result in poor endurance.

An approach that addresses the shortcomings of previous approaches is disclosed herein. For example, as part of a disclosed process the RRAM device is encapsulated with a thin aluminum oxide (Al<NUM>O<NUM>) layer that prevents moisture from penetrating the RRAM device. Preventing moisture from penetrating the RRAM device significantly improves LRS retention. In particular, the prevention of the penetration of moisture that is effected by the Al<NUM>O<NUM> layer greatly reduces LRS drift to high resistance. This decreases the LRS failure rate by an order of magnitude. Moreover, the retention benefit does not come at the expense of yield or endurance.

In addition, nitrogen may be incorporated into high-k tantalum oxide (Ta<NUM>O<NUM>) by exposing a blanket physical vapor deposition (PVD) Ta<NUM>O<NUM> film to a N<NUM> plasma. Nitrogen can also be doped into the high-k material using ion implantation. The incorporation of nitrogen into the high-k active layer significantly reduces retention failure from the drifting of devices from a low resistance state to a high resistance state. This retention benefit does not increase the set current that is needed for writing the device to LRS.

<FIG> is an illustration of a cross-section of an RRAM device <NUM> according to an embodiment of the present invention.

<FIG> shows bottom electrode underlayer <NUM>, bottom electrode <NUM>, high-k material <NUM>, oxygen exchange layer (OEL) <NUM>, top electrode <NUM>, top contact <NUM>, Al<NUM>O<NUM> layer <NUM>, optional SiN film <NUM>, optional barrier layer <NUM> and optional bit line contact <NUM>.

Referring to <FIG>, the bottom electrode <NUM> is formed on the bottom electrode underlayer <NUM>. The high-k material <NUM> is formed on bottom electrode <NUM>. The OEL <NUM> is formed on the high-k material <NUM>. The top electrode <NUM> is formed on the OEL <NUM>. The top contact <NUM> is formed on the top electrode <NUM>. The Al<NUM>O<NUM> layer <NUM> encapsulates the bottom electrode <NUM>, the high-k material <NUM>, the OEL <NUM>, the top electrode <NUM>, and the top contact <NUM>. The SiN film <NUM> is formed on the Al<NUM>O<NUM> layer <NUM>. The bit line contact <NUM> is formed in the bit line contact space.

According to the present invention, the bottom electrode underlayer <NUM> is formed from a noble metal (Pt, Ru, Ir), TiN, WN or TaN. In an embodiment, the bottom electrode <NUM> can be formed from noble metal or alloy. In other embodiments, the bottom electrode <NUM> can be formed from other materials. In an embodiment, the high-k material <NUM> can be formed from HfO, TaO, or ZrO. In other embodiments, the high-k material <NUM> can be formed from other materials. In an embodiment, the OEL layer <NUM> can be formed from a reactive metal (e.g., can use metal corresponding to high-k material Hf, Ta, Zr, Ti etc.). In other embodiments, the OEL layer <NUM> can be formed from other materials. In an embodiment, the top electrode <NUM> can be formed from TiN, WN, Pt, Ru, Ir or TaN. In other embodiments, the top electrode109 can be formed from other materials. In an embodiment, the top contact <NUM> can be formed from Ta or W. In other embodiments, the top contact <NUM> can be formed from other materials. In an embodiment, the barrier layer <NUM> can be formed from Ta. In other embodiments, the barrier layer <NUM> can be formed from other material. In an embodiment, bit line contact <NUM> can be formed from copper. In other embodiments, bit line contact <NUM> be formed from other materials.

In operation, when a set voltage is applied to the memory cell, a low resistance filament is created and the device is placed into a low resistance state. It should be appreciated that the set voltage causes the diffusion of oxygen from the high-k layer <NUM> into the OEL layer <NUM> to create the low resistance filament in the high-k material. The filament is characterized by oxygen vacancies. In an embodiment, a penetration of moisture into the high-k material can degrade the filament by causing the diffusion of oxygen vacancy eliminating oxygen atoms into the high-k dielectric. The degradation of the low resistance filament in this manner can cause the resistance of the high-k material to drift higher. Thus, the prevention of moisture from penetrating into the high-k dielectric can prevent a LRS drift of the resistance and significantly improve LRS retention. In an embodiment, moisture is prevented from diffusing into the low-k dielectric by the Al<NUM>O<NUM> layer. In an embodiment, this can decrease the LRS failure rate by an order of magnitude. Moreover, the retention benefit does not come at the expense of yield or endurance.

It should be appreciated that the setting and resetting of the RRAM device <NUM> requires a certain level of oxygen atoms that can be removed from, and returned to, the high-k material in order to sufficiently change its resistance level from one resistance state to the other. The loss of oxygen atoms from the RRAM device <NUM> can cause a loss of the ability to reset the device by controlling the diffusion of oxygen into and out of the high-k material <NUM>. Thus, without a mechanism to retain oxygen in the RRAM device <NUM>, the ability to reset the device can be lost after a number of cycles. The number of cycles that it takes to reach this point is referred to as endurance. In an embodiment, the Al<NUM>O<NUM> layer <NUM> prevents oxygen atoms from escaping the RRAM device <NUM>. Thus, in an embodiment, endurance is increased as the Al<NUM>O<NUM> layer <NUM> slows the escape of oxygen from the device. In other embodiments, other materials can be used to prevent the loss of oxygen from the RRAM device <NUM>.

In an embodiment, the RRAM device <NUM> can be formed on blanket RRAM films using lithography. In an embodiment, dry etching can be used to transfer a photomask pattern to underlying RRAM films. In other embodiments, other manner of transferring the photomask pattern can be used. The structure can then be encapsulated with an atomic layer deposition (ALD) aluminum oxide (Al<NUM>O<NUM>) and CVD SiN film. The Al<NUM>O<NUM> film acts as a hermetic barrier to the diffusion of moisture into the high-k active layer of the RRAM device <NUM>. As described herein, the reduced moisture content reduces oxygen diffusion into the device and improves retention of the low resistance state (LRS). Thus, in an embodiment, the Al<NUM>O<NUM> encapsulation significantly reduces retention failures by decreasing the drift of the low resistance state (LRS) to resistances above the reference level (RL).

<FIG> shows a graph <NUM> of plots from a LRS retention test of devices with Al<NUM>O<NUM> encapsulation <NUM> and without high-k encapsulation <NUM>. Both of the device types represented in the retention plots of <FIG>, have a SiN encapsulation layer (e.g., <NUM> in <FIG>). In an embodiment, both device types are programmed to a low resistance state by increasing a SET voltage until the LRS read resistance (LRS resistance before being heated) is below a resistance verify level (VL). The devices are then heated at <NUM> degrees Celsius for <NUM> hours whereupon the resistance is measured at the read voltage. The post bake resistance is compared to a reference resistance level (RL). Devices programmed to the LRS which drift to a resistance level above the RL are considered retention failures. Referring to <FIG>, the post-bake resistance distribution for the group of devices with Al<NUM>O<NUM> encapsulation is tighter than the group with no high-k encapsulation. It should be appreciated that the results shown in <FIG> are exemplary and in other embodiments other results can be provided.

<FIG> is an illustration of a cross-section of a RRAM device <NUM> according to a second embodiment of the present invention. <FIG> shows bottom electrode underlayer <NUM>, bottom electrode <NUM>, high-k material <NUM>, optional oxygen exchange layer (OEL) <NUM>, top electrode <NUM>, top contact <NUM>, Al<NUM>O<NUM> layer <NUM>, optional SiN film <NUM>, optional barrier layer <NUM> and optional bit line contact <NUM>. These structures are similar to those of the RRAM device <NUM> shown in <FIG> and thus are not described again here for purposes of clarity and brevity. In addition to the structures of RRAM device <NUM> shown in <FIG>, RRAM device <NUM> includes a high-k active layer <NUM> that is doped with nitrogen.

Referring to <FIG>, the stoichiometric Ta<NUM>O<NUM> high-k film <NUM>, which serves as the active layer for the RRAM device <NUM>, is doped with nitrogen either by exposure to an N<NUM> plasma or an N implant process. In an embodiment, the RRAM device <NUM> can be doped with nitrogen after the deposition of the Ta<NUM>O<NUM> high-k film <NUM>. In an embodiment, the nitrogen is substitutionally incorporated into the Ta<NUM>O<NUM> lattice displacing oxygen in the film. The N<NUM> plasma treatment significantly reduces retention failures by decreasing the drift of a low resistance state (LRS) resistance to resistances above the reference level (RL).

In operation, the incorporation of nitrogen into the high-k active layer <NUM> the RRAM device <NUM> significantly improves LRS retention. In particular, the incorporation of nitrogen into the high-k active layer significantly reduces retention failure from the drifting of devices from a low resistance state to a high resistance state. This retention benefit does not increase the set current that is needed for writing the device to LRS.

<FIG>, <FIG> and <FIG> show energy-dispersive x-ray spectroscopy (EDX) line scans of a device with no nitrogen incorporation, a device with nitrogen doping and a device with plasma enhanced nitrogen implant. <FIG>, <FIG> and <FIG> include plots with sections that correspond to the OEL <NUM>, the high-k material <NUM> and the bottom electrode <NUM>. Referring to <FIG> and <FIG>, a comparison of the section of the plots that correspond to the high-k material <NUM> show an increased nitrogen concentration in the Ta<NUM>O<NUM> high-k film with nitrogen doping (see <FIG> arrow <NUM>) as compared to the high-k film without doping (see <FIG> arrow <NUM>). Referring to <FIG> and <FIG>, the section of the plots that correspond to the high-k material <NUM> shows an increased nitrogen concentration in the Ta<NUM>O<NUM> high-k film with enhanced nitrogen implant (<FIG>) as compared to the high-k film with doping in (<FIG>). In <FIG> the arrow <NUM> points to a part of the plot that illustrates increased nitrogen concentration in the high-k material of the RRAM device.

<FIG> shows a graph <NUM> of plots of example results from a low resistance state (LRS) retention test between RRAM devices without nitrogen incorporation into high-k material and with N<NUM> plasma treatment. In an embodiment, the RRAM devices are programmed to a low resistance state by increasing the SET voltage until the LRS read resistance (LRS resistance before being heated) is below a given verify level (VL). The RRAM devices are then heated at <NUM> degrees Celsius for <NUM> hours and the resistance is measured at the read voltage. In an embodiment, the resistance after being heated is compared to a reference resistance level (RL). In an embodiment, the RRAM devices that are programmed to LRS that experience a drift to a resistance level above the RL are considered to be retention failures. Referring to <FIG>, the post-bake resistance distribution for the group of devices with N<NUM> plasma treatment <NUM> is tighter than the group <NUM> with no treatment and has no devices with resistance greater than the RL. It should be noted that results shown in <FIG> are exemplary and in other embodiments other results can be provided.

<FIG> is a flowchart <NUM> of a method for forming an RRAM device with improved LRS retention according to an embodiment of the present invention. Referring to <FIG>, the method includes, at <NUM>, forming a bottom electrode, at <NUM>, forming a high-k material on the bottom electrode, at <NUM>, forming a top electrode and forming a top contact on the top electrode, and, at <NUM>, forming an encapsulating layer of Al<NUM>O<NUM> that encapsulates the bottom electrode, the high-k material, the top electrode and the top contact. In an embodiment, the high-k material is configured to store data. In an embodiment, the encapsulating layer of Al<NUM>O<NUM> is configured to block moisture. In an embodiment, a SiN film may be formed on the encapsulating layer. In an embodiment, an oxygen exchange layer (OEL) material may be formed on the high-k material. According to the present invention, a layer that includes a noble metal, TiN, WN or TaN is formed under the encapsulating layer and the bottom electrode.

Implementations of embodiments of the invention may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the scope of the present invention.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. The MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that use can also be made of nonplanar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. An annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. The gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

A pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. The source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. One or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO<NUM>), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

<FIG> illustrates a computing device <NUM>. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The term does not imply that the associated devices do not contain any wires, although in some implementations they might not.

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. The integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

<FIG> illustrates an interposer <NUM>. The interposer <NUM> is an intervening substrate used to bridge a first substrate <NUM> to a second substrate <NUM>. The first substrate <NUM> may be, for instance, an integrated circuit die. The second substrate <NUM> may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer <NUM> is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer <NUM> may couple an integrated circuit die to a ball grid array (BGA) <NUM> that can subsequently be coupled to the second substrate <NUM>. In some implementations, the first and second substrates <NUM>/<NUM> are attached to opposing sides of the interposer <NUM>. In other implementations, the first and second substrates <NUM>/<NUM> are attached to the same side of the interposer <NUM>. And in further implementations, three or more substrates are interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer <NUM>.

Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise.

Claim 1:
An RRAM device (<NUM>), comprising:
a bottom electrode (<NUM>);
a high-k material (<NUM>) on the bottom electrode (<NUM>);
a top electrode (<NUM>);
a top contact (<NUM>) on the top electrode (<NUM>); and
an encapsulating layer (<NUM>) of Al<NUM>O<NUM> that encapsulates the bottom electrode (<NUM>), the high-k material (<NUM>), the top electrode (<NUM>) and the top contact (<NUM>),
characterised by
a layer (<NUM>) including a noble metal, TiN, WN or TaN under the encapsulating layer (<NUM>) and the bottom electrode (<NUM>).