Patent Description:
An SiP (System in Package or System-in-a-Package) includes one or more integrated circuits enclosed in a single module (e.g., a single package). The SiP may perform many (or all) of the functions of an electronic system. An example of an SiP may include several dies combined with passive components (e.g., resistors and capacitors) mounted on a single substrate. Mounting all the components on the single substrate provides a complete functional unit that can be built in a multi-die package and few external components may be needed to make the device work.

For an electronic system having one or more SiP packages, chips or SoC (System on Chip) integrated therein, how to reduce power consumption is always an issue of concern.

Document <CIT> discloses a plurality of chips arranged in one common package.

Document <CIT> discloses that a control signal is relayed from an output of a first functional block to an input of a second functional block.

Document <CIT> discloses that a control signal is relayed from a first processing unit to a second processing unit.

Document <CIT> discloses that a control signal is relayed from a first functional block to a second functional block.

It is one object of the present invention to provide novel structure designs of a semiconductor device realizing or having a serial power system. In the embodiments of the invention, the power consumption can be greatly reduced as compared to the conventional design. In addition, the package-size of the proposed structure is smaller than that of the conventional structure, and the BOM (Bill of Materials) list and circuit area on PCB can also be saved. A semiconductor device according to the invention is defined in the independent claim. The dependent claims define preferred embodiments thereof.

According to one embodiment not belonging to the invention, a semiconductor device comprises a plurality of functional blocks, each being configured to provide at least one predetermined function. The functional blocks at least comprise a first functional block and a second functional block. The first functional block and the second functional block are coupled in serial to enable a predetermined current flowing therethrough, i.e. with a predetermined current flowing therethrough in operation of the semiconductor device.

According to an embodiment of the invention, the semiconductor device comprises a printed circuit board and a plurality of functional blocks. Each functional block is disposed on the printed circuit board and configured to provide at least one predetermined function. The functional blocks at least comprise a first functional block and a second functional block. The first functional block and the second functional block are coupled in serial to enable a first predetermined current flowing therethrough, i.e. with a first predetermined current flowing therethrough in operation of the semiconductor device. The printed circuit board or the printed circuit board and a substrate thereon is adapted so that at least one control signal received from the first functional block is relayed to the second functional block, i.e. at least one control signal received from the first functional block is relayed to the second functional block in operation of the semiconductor device.

According to another embodiment not belonging to the invention, a semiconductor device comprises a plurality of semiconductor dies. Each semiconductor die is configured to provide at least one predetermined function.

The semiconductor dies at least comprise a first semiconductor die and a second semiconductor die. The first semiconductor die has a first power pad and first ground pad. The second semiconductor die has a second power pad and a second ground pad. The first power pad of the first semiconductor die and the second ground pad of the second semiconductor die are electrically connected to each other and equipotential.

In order to reduce power consumption, novel structure designs of a semiconductor device realizing a serial power system is provided.

According to an embodiment not belonging to the invention, a semiconductor device may comprise a plurality of functional blocks. Each functional block is configured to provide at least one predetermined function. For example, each functional block may be configured to provide a CHF (cryptographic hash function) calculation function, such as SHA (Secure Hash Algorithm) calculation function. Preferably, the functional block may be a circuit, a semiconductor die, an IC, a chip, an SoC die, an SoC package, a SiP package, a semiconductor package, or a package assembly.

The functional blocks at least comprise a first functional block and a second functional block. Preferably, the first functional block and the second functional block are coupled in serial with a predetermined current flowing therethrough.

In a first aspect not belonging to the invention, the functional blocks are semiconductor dies packaged in a semiconductor package. The semiconductor dies packaged in one semiconductor package, such as an SiP (System in Package) package, may be coupled in serial between a power node and a ground node with a predetermined current flowing therethrough.

<FIG> is a top view diagram of a semiconductor package according to an embodiment in the first aspect. In this embodiment, the semiconductor device <NUM> may be a semiconductor package or a chip. The semiconductor device <NUM> comprises two semiconductor dies <NUM> and <NUM> packaged therein. The semiconductor dies <NUM> and <NUM> may be configured to provide the same function. The pins (for example, the pins labeled with the numbers <NUM>~<NUM>) marked by the leading term "D1" are the pins associated with the semiconductor die <NUM> and the pins marked by the leading term "D2" are the pins associated with the semiconductor die <NUM>. It should be noted that the pin map shown in <FIG> is only a schematic.

Preferably, the semiconductor dies <NUM> and <NUM> are coupled in serial by electrically connecting the power pad of the semiconductor die <NUM> to the ground pad of the semiconductor die <NUM>. As shown in <FIG>, the power pad (or, the associated power pin) DVDD_1 of the semiconductor die <NUM> is electrically connected to the ground pad (or, the associated ground pin) DVSS_2 of the semiconductor die <NUM>. In addition, the power pad (or, the associated power pin) DVDD_2 of the semiconductor die <NUM> may be configured to receive power from an external power source via a power node or a power pin of the semiconductor device <NUM>, and the ground pad (or, the associated ground pin) DVSS_1 of the semiconductor die <NUM> may be further coupled to a ground node.

Since the power pad DVDD_1 of the semiconductor die <NUM> is electrically connected to the ground pad DVSS_2 of the semiconductor die <NUM>, the power pad DVDD_1 of the semiconductor die <NUM> and the ground pad DVSS_2 of the semiconductor die <NUM> are equipotential.

Preferably, the semiconductor die <NUM>/<NUM> may comprise at least one computing circuit (for example, the computing circuit configured to perform the CHF or SHA calculation), at least one PLL (Phase-Locked Loop) circuit configured to generate an internal clock signal, at least one I/O pad, and may further comprise some peripheral or supplementary components. Those components may be triggered by different power. For example, the power DVDD may be provided for triggering the computing circuit, the power AVDD1V8 may be provided for triggering the PLL circuit, and the power AVDD0V75 may be provided for triggering the I/O pad.

Preferably, the serial power system is implemented by coupling the power DVDD utilized for triggering the computing circuit in a serial manner, where the computing circuit provides the main function of the semiconductor device <NUM>.

<FIG> is an equivalent circuit diagram of two semiconductor dies coupled in serial according to an embodiment in the first aspect. As shown in <FIG>, the semiconductor dies <NUM> and <NUM> are coupled in serial between the power node for receiving the power V_Power and the ground node. The power V_Power may be provided to the power pad P2 of the semiconductor die <NUM>, and the ground pad G1 of the semiconductor die <NUM> may be electrically connected to the ground node. The predetermined current I (that is, the same current) may flow through the semiconductor dies <NUM> and <NUM> when the power V_Power is supplied.

Preferably, the power pad P1 of the semiconductor die <NUM> and the ground pad G2 of the semiconductor die <NUM> are electrically connected to each other within the semiconductor package. For this case, the power pad DVDD_1 of the semiconductor die <NUM> and the ground pad DVSS_2 of the semiconductor die <NUM> as shown in <FIG> may form a whole piece (that is, the black line between the power pad DVDD_1 and the ground pad DVSS_2 in <FIG> should be removed). It should be understood that the black line between the power pad DVDD_1 and the ground pad DVSS_2 in <FIG> are shown for the purpose to allow readers to easily distinguish between two blocks.

Alternatively preferably, the power pad DVDD_1 of the semiconductor die <NUM> and the ground pad DVSS_2 of the semiconductor die <NUM> may be electrically connected to each other via at least one connecting element on a printed circuit board (PCB), an interposer and/or a substrate. Preferably, the connecting element may be, for example but not limited to, the Redistribution Layer (RDL) trace, PCB trace, the connecting bump (such as the solder ball), the bonding wire, through silicon via (TSV) or others.

<FIG> is a schematic, cross-sectional diagram of the semiconductor package as illustrated in <FIG> according to an embodiment in the first aspect. In an embodiment not belonging to the invention, a semiconductor package having exposed dies is provided. The molding compound <NUM> encapsulates the semiconductor dies <NUM> and <NUM>. The stiffener ring <NUM> may be disposed along the perimeter of the package substrate <NUM>. The semiconductor package may be a land grid array (LGA) type package.

Through the connecting elements <NUM>, <NUM>, <NUM> and <NUM>, the semiconductor package may be mounted on PCB <NUM> or a system board. Preferably, for example, the connecting element <NUM> is associated with the ground pad DVSS_1 of the semiconductor die <NUM>, the connecting element <NUM> is associated with the power pad DVDD_1 of the semiconductor die <NUM>, the connecting element <NUM> is associated with the ground pad DVSS_2 of the semiconductor die <NUM>, and the connecting element <NUM> is associated with the power pad DVDD_2 of the semiconductor die <NUM>.

Preferably, the connecting elements <NUM> and <NUM> are electrically connected to each other via the substrate <NUM> and/or the PCB <NUM>. The ground pad DVSS_1 is electrically connected to the ground node and the power pad DVDD_2 is electrically connected to the power node.

Besides implementing the serial power system within the semiconductor package as the embodiments in the first aspect illustrated above, in a second aspect not belonging to the invention, the serial power system may also be implemented within a semiconductor die. In the second aspect, the semiconductor device may be a semiconductor die.

<FIG> is a block diagram showing an on die serial power system according to an embodiment of the second aspect. In this embodiment, the functional block may be a computing circuit macro, and each computing circuit macro may comprise one or more computing circuits. Preferably, the semiconductor die <NUM> may comprise a plurality of computing circuit macros, such as the computing circuit macros M1-M4. The computing circuit macros M1~M4 are coupled in serial. Each computing circuit macro may comprise one or more computing circuits. Each computing circuit is configured to provide the predetermined function, such as CHF calculation, SHA calculation, or others. Therefore, the computing circuit macros M1-M4 may be configured to provide the same function. Preferably, when there is more than one computing circuit comprised in one computing circuit macro, the computing circuits may be coupled in parallel or in serial.

As shown in <FIG>, a power node of the computing circuit macro M4 for receiving the supplied power is coupled to the power node PWR or the power pad (or, the associated power pin) of the semiconductor die <NUM>. A power node of the computing circuit macro M3 is coupled to the ground node of the computing circuit macro M4. A power node of the computing circuit macro M2 is coupled to the ground node of the computing circuit macro M3. A power node of the computing circuit macro M1 is coupled to the ground node of the computing circuit macro M2. The ground node of the computing circuit macro M1 is coupled to the power node GND or the ground pad (or, the associated ground pin) of the semiconductor die <NUM>.

In this embodiment, among two adjacent computing circuit macros coupled in serial, the power node of the lower computing circuit macro and the ground node of the upper computing circuit macro are equipotential. In addition, when the power is supplied, a predetermined current (that is, the same current) will flow through the computing circuit macros M4~M1.

In a third aspect not belonging to the invention, the serial power system may also be implemented on the PCB. In the third aspect, the functional blocks coupled in serial in the semiconductor device may be the semiconductor packages, the ICs or the chips.

<FIG> is a schematic diagram showing two chips coupled in serial on the PCB according to an embodiment not belonging to the invention. As shown in <FIG>, the semiconductor device <NUM> may comprise chips <NUM> and <NUM> mounted on the PCB <NUM> and coupled in serial between the power node for receiving the power V_Power and the ground node. A power pin of the chip <NUM> is electrically connected to the power node. A ground pin of the chip <NUM> is electrically connected to the ground node. A power pin of the chip <NUM> is electrically connected to the ground pin of the chip <NUM>. The power pin of the chip <NUM> and the ground pin of the chip <NUM> are equipotential. The chips <NUM> and <NUM> may be electrically connected to each other via at least one connecting element of the PCB/and or the substrate thereon. When the power V_Power is supplied, a predetermined current (that is, the same current) will flow through the chips <NUM> and <NUM>.

Preferably, the chips <NUM> and <NUM> may comprise one or more semiconductor dies packaged therein, such as the semiconductor dies <NUM> and <NUM>, and are configured to provide the same function. When there are more than one semiconductor die packaged in one chip, the semiconductor dies may be coupled in serial between the power node and the ground node as the embodiment in the first aspect as illustrated above. In addition, each semiconductor die may further comprise one or more computing circuits or one or more computing circuit macros. When there are more than one computing circuit or more than one computing circuit macro comprised in one semiconductor die, the computing circuits or computing circuit macros may be coupled in serial between the power node and the ground node as the embodiment in the second aspect as illustrated above.

It is preferably for the functional blocks coupled in serial and having the current flowing therethrough to have similar characteristics. To be more specific, in the first aspect, the semiconductor dies coupled in serial preferably have similar characteristics. In the second aspect, the computing circuits or computing circuit macros coupled in serial preferably have similar characteristics. In the third aspect, the chips coupled in serial preferably have similar characteristics.

Preferably, the characteristics may be, for example but not limited to, an equivalent impedance, a conducting current, or a leakage temperature of the chip, the semiconductor die, the computing circuit macro or the computing circuit, or others.

Here, 'similar' may refer to that a difference between two corresponding values is less than a predetermined value.

Preferably, a difference between an equivalent impedance of the semiconductor die <NUM> and an equivalent impedance of the semiconductor die <NUM> is less than a predetermined value. Alternatively or additionally preferably, a difference between the equivalent impedance of arbitrary two of the computing circuit macros M1~M4 is less than a predetermined value. Further alternatively or additionally preferably, a difference between an equivalent impedance of the chip <NUM> and an equivalent impedance of the chip <NUM> is less than a predetermined value.

Based on the proposed structures as illustrated above and corresponding routings on the PCB, one or more control signals may be relayed between functional blocks.

<FIG> is a schematic diagram showing two chips (or, semiconductor packages) coupled in serial on the PCB according to another embodiment not belonging to the invention, where each chip has two semiconductor dies packaged therein, and the semiconductor dies packaged in one chip are coupled in serial. In this embodiment, the functional blocks are chips disposed on the PCB and configured to provide at least one predetermined function (e.g. the functional blocks are configured to provide the same function).

As shown in <FIG>, the semiconductor device <NUM> may comprise chips <NUM> and <NUM> mounted on the PCB <NUM> and coupled in serial between the power node for receiving the power V_Power and the ground node. A power pin of the chip <NUM> is electrically connected to the power node. A ground pin of the chip <NUM> is electrically connected to the ground node. A power pin of the chip <NUM> is electrically connected to the ground pin of the chip <NUM>. The chips <NUM> and <NUM> may be electrically connected to each other via at least one connecting element of the PCB and/or the substrate thereon. When the power V_Power is supplied, a predetermined current (that is, the same current) will flow through the chips <NUM> and <NUM>.

Preferably, the chips <NUM> and <NUM> respectively comprise two semiconductor dies packaged therein, such as the semiconductor dies <NUM>-<NUM> and <NUM>-<NUM> and the semiconductor dies <NUM>-<NUM> and <NUM>-<NUM>. The structure of the semiconductor dies coupled in serial and packaged in the chip <NUM> and/or <NUM> is similar to the structure shown in <FIG>. Therefore, descriptions of the circuit structure within the chip or the semiconductor package having semiconductor dies coupled in serial may refer to the descriptions of <FIG>, and are omitted here for brevity. In addition, the structure of the chips or the semiconductor packages coupled in serial on the PCB is similar to the structure shown in <FIG>. Therefore, descriptions of the circuit structure of a semiconductor device having chips or semiconductor packages coupled in serial may refer to the descriptions of <FIG>, and are omitted here for brevity.

Preferably, at least one control signal, such as the clock signal or the strobe signal, is relayed from one chip (e.g. chip <NUM>) (or, one semiconductor package) to another chip (e.g. chip <NUM>) (or, another semiconductor package). Preferably, at least one control signal output pin of chip <NUM> is electrically connected to a control signal input pin of chip <NUM> via at least one connecting element of the PCB and/or the substrate thereon.

As shown in <FIG>, pin <NUM>, which is a clock signal output pin D2CLKO, of chip <NUM> is electrically connected to pin <NUM>, which is a clock signal input pin D1CLKI, of chip <NUM>.

In addition, preferably at least one control signal, such as the clock signal or the strobe signal, is relayed from one semiconductor die to another semiconductor die within the same chip (or, the semiconductor package). For example, at least one control signal output pad of one semiconductor die is electrically connected to a control signal input pad of another semiconductor die within the same chip via at least one connecting element of the PCB and/or the substrate thereon.

As shown in <FIG>, pin <NUM>, which is a clock signal output pin D1CLKO, of chip <NUM> is electrically connected to pin <NUM>, which is a clock signal input pin D2CLKI, of chip <NUM>, where pin <NUM> is the pin associated with the semiconductor die <NUM>-<NUM> and is electrically connected to a corresponding control signal output pad of the semiconductor die <NUM>-<NUM>, and pin <NUM> is the pin associated with the semiconductor die <NUM>-<NUM> and is electrically connected to a corresponding control signal input pad of the semiconductor die <NUM>-<NUM>.

Via the routings on PCB <NUM> and the internal signal transmission paths within chips as shown in <FIG>, a control signal, such as the clock signal CLK, received from an external device, such as a CPU or an external clock source, via pin <NUM> of chip <NUM> may be routed or transmitted from the semiconductor die <NUM>-<NUM> to the semiconductor die <NUM>-<NUM>, then routed or transmitted to the semiconductor die <NUM>-<NUM>, and finally routed or transmitted to the semiconductor die <NUM>-<NUM>. For another signal to be transmitted from the semiconductor device <NUM> to the external device (e.g. an CPU), the signal may be routed or transmitted to the external device in a reverse direction.

Take the pins shown in <FIG> as an example, the clock signal CLK received from an external device via pin <NUM> of chip <NUM> may be routed or transmitted to pin <NUM> of the chip <NUM> via an internal signal transmission path within chip <NUM>, and then routed or transmitted to pin <NUM> of chip <NUM> via a signal transmission path (e.g. the connecting element as illustrated above) on the PCB <NUM>. The clock signal CLK may be further routed or transmitted to pin <NUM> of the chip <NUM> via another internal signal transmission path within chip <NUM>, and then routed or transmitted to pin <NUM> of chip <NUM> via another signal transmission path (e.g. the connecting element as illustrated above) on the PCB <NUM>.

The clock signal CLK may be further routed or transmitted within chip <NUM> in the similar way. In this manner, the control signal received from an external device may be relayed from the semiconductor die <NUM>-<NUM> to the semiconductor die <NUM>-<NUM> and the semiconductor die <NUM>-<NUM>, and then to the semiconductor die <NUM>-<NUM>.

Based on the proposed structures, a smooth layout on package-substrate routing and a straightforward layout on PCB routing, such as the routing shown in <FIG>, can be achieved.

It should be noted that besides the control signal(s), the input/output signal(s) may also be relayed from one chip to another and from one semiconductor die to another based on the routings on the PCB and the proposed structures. As shown in <FIG>, the reception/transmission output pin (e.g. the pins labeled with the ending term "RXO" or "TXO") associated with one semiconductor die may be electrically connected to the reception/transmission input pin (e.g. the pins labeled with the ending term "RXI" or "TXI") associated with another semiconductor die within the same chip. In addition, the reception/transmission output pin of one chip may be electrically connected to the reception/transmission input pin of another chip within the same semiconductor device.

The control signals may also be relayed among more than two functional blocks.

<FIG> is a schematic diagram showing six chips (or, semiconductor packages) on the PCB according to an embodiment of the invention, where each chip has two semiconductor dies packaged therein, and the semiconductor dies packaged in one chip are coupled in serial. The semiconductor dies or chips disposed on the PCB <NUM> are configured to provide the same function.

In this embodiment, the semiconductor device <NUM> comprises chips <NUM>-<NUM> mounted on the PCB <NUM>. The chips <NUM> and <NUM>, <NUM> and <NUM> and <NUM> and <NUM> are respectively coupled in serial between the power node for receiving the power V_Power and the ground node. In addition, the semiconductor device <NUM> may further comprise a parallel structure in which three chip sets (that is, the chip set comprising chips <NUM> and <NUM>, the chip set comprising chips <NUM> and <NUM> and the chip set comprising chips <NUM> and <NUM>) are coupled in parallel.

The power pins of the chips <NUM>, <NUM> and <NUM> are electrically connected to the power node. The ground pins of the chips <NUM>, <NUM> and <NUM> are electrically connected to the ground node. The power pin of the chip <NUM> is electrically connected to the ground pin of the chip <NUM> via at least one connecting element that is at least one connecting element of the PCB <NUM> or of the PCB <NUM> and the substrate thereon according to the invention, and is at least one connecting element of said substrate otherwise. When the power V_Power is supplied, a predetermined current (that is, the same current) will flow through the chips <NUM> and <NUM>. Similarly, the power pin of the chip <NUM> is electrically connected to the ground pin of the chip <NUM> via at least one connecting element that is at least one connecting element of the PCB <NUM> or of the PCB <NUM> and the substrate thereon according to the invention, and is at least one connecting element of said substrate otherwise. When the power V_Power is supplied, a predetermined current (that is, the same current) will flow through the chips <NUM> and <NUM>. Similarly, the power pin of the chip <NUM> is electrically connected to the ground pin of the chip <NUM> via at least one connecting element that is at least one connecting element of the PCB <NUM> or of the PCB and the substrate thereon according to the invention, and is at least one connecting element of said substrate otherwise. When the power V_Power is supplied, a predetermined current (that is, the same current) will flow through the chips <NUM> and <NUM>.

Preferably, the chips <NUM>-<NUM> respectively comprise two semiconductor dies packaged therein, such as the semiconductor dies <NUM>-<NUM> and <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> and <NUM>-<NUM> and <NUM>-<NUM>. The structure of the semiconductor dies coupled in serial and packaged in the chips <NUM>-<NUM> is similar to the structure shown in <FIG>. Therefore, descriptions of the circuit structure within the chip or the semiconductor package having semiconductor dies coupled in serial may refer to the descriptions of <FIG>, and are omitted here for brevity. In addition, the structure of the chips or the semiconductor packages coupled in serial on the PCB is similar to the structure shown in <FIG>. Therefore, descriptions of the circuit structure of a semiconductor device having chips or semiconductor packages coupled in serial may refer to the descriptions of <FIG>, and are omitted here for brevity.

In addition, the signal transmission paths within a chip and among different chips and the pin connections are similar to the embodiment shown in <FIG>. It is readily appreciated for the person of ordinary skill in the art to derive the signal transmission paths within a chip and among different chips of <FIG> based on the descriptions of <FIG>. Therefore, details of the descriptions may refer to the descriptions of <FIG>, and are omitted here for brevity.

In the embodiment shown in <FIG>, a control signal output pin, for example, pin <NUM>, of the chip <NUM> is electrically connected to a control signal input pin, for example, pin <NUM>, of the chip <NUM> via at least one connecting element that is at least one connecting element on the PCB <NUM> or on the PCB <NUM> and the substrate thereon according to the invention, and is at least one connecting element of said substrate otherwise. In addition, another control signal output pin, for example, pin <NUM>, of the chip <NUM> is electrically connected to a control signal input pin, for example, pin <NUM>, of the chip <NUM> via at least one connecting element on the PCB <NUM> or on the PCB <NUM> and the substrate thereon according to the invention, and is at least one connecting element of said substrate otherwise. Similarly, a control signal output pin, for example, pin <NUM>, of the chip <NUM> is electrically connected to a control signal input pin, for example, pin <NUM>, of the chip <NUM> via at least one connecting element that is at least one connecting element of the PCB <NUM> or of the PCB <NUM> and the substrate thereon according to the invention, and is at least one connecting element of said substrate otherwise. The rest may be deduced by analogy.

In the embodiment shown in <FIG>, via the routings on PCB <NUM> and the internal signal transmission paths within chips as shown in <FIG>, a control signal, such as the clock signal CLK, received from an external device via pin <NUM> of chip <NUM> may be routed or transmitted from the semiconductor die <NUM>-<NUM> to the semiconductor die <NUM>-<NUM>, the semiconductor die <NUM>-<NUM>, then routed or transmitted to the semiconductor die <NUM>-<NUM>, the semiconductor die <NUM>-<NUM> and then to the semiconductor die <NUM>-<NUM>. In addition, the control signal may be further routed or transmitted from the semiconductor die <NUM>-<NUM> to the semiconductor die <NUM>-<NUM>, the semiconductor die <NUM>-<NUM>, the semiconductor die <NUM>-<NUM>, then routed or transmitted to the semiconductor die <NUM>-<NUM>, the semiconductor die <NUM>-<NUM> and the semiconductor die <NUM>-<NUM>. For another signal to be transmitted from the semiconductor device <NUM> to the external device (e.g. an CPU), the signal may be routed or transmitted to the external device in a reverse direction.

According to the invention, one semiconductor package may also comprise more than two semiconductor die coupled in serial.

<FIG> is a top view diagram of a semiconductor package according to another embodiment not belonging to the invention. In this embodiment, the semiconductor device <NUM> may be a semiconductor package or a chip. The semiconductor device <NUM> comprises three semiconductor dies <NUM>, <NUM> and <NUM> packaged therein and coupled in serial. The semiconductor dies <NUM>, <NUM> and <NUM> may be configured to provide the same function. The pins (for example, the pins labeled with the numbers <NUM>~<NUM>) marked by the leading term "D1" are the pins associated with the semiconductor die <NUM>, the pins marked by the leading term "D2" are the pins associated with the semiconductor die <NUM> and the pins marked by the leading term "D3" are the pins associated with the semiconductor die <NUM>.

As shown in <FIG>, the power pad (or, the associated power pin) DVDD_1 of the semiconductor die <NUM> is electrically connected to the ground pad (or, the associated ground pin) DVSS_2 of the semiconductor die <NUM> and the power pad (or, the associated power pin) DVDD_2 of the semiconductor die <NUM> is electrically connected to the ground pad (or, the associated ground pin) DVSS_3 of the semiconductor die <NUM>. In addition, the power pad DVDD_3 of the semiconductor die <NUM> may be configured to receive power from an external power source via a power node or a power pin of the semiconductor device <NUM>, and the ground pad (or, the associated ground pin) DVSS_1 of the semiconductor die <NUM> may be further coupled to a ground node.

In this embodiment, among two adjacent semiconductor dies coupled in serial, the power pad (or, the associated power pin) of the lower semiconductor die and the ground pad (or, the associated ground pin) of the upper semiconductor die are equipotential. In addition, when the power V_Power is supplied, a predetermined current (that is, the same current) will flow through the semiconductor dies <NUM>~<NUM>.

<FIG> is a top view diagram of a semiconductor package according to yet another embodiment not belonging to the invention. In this embodiment, the semiconductor device <NUM> may be a semiconductor package or a chip. The semiconductor device <NUM> comprises four semiconductor dies <NUM>, <NUM>, <NUM> and <NUM> packaged therein and coupled in serial. The semiconductor dies <NUM>, <NUM>, <NUM> and <NUM> may be configured to provide the same function. The pins (for example, the pins labeled with the numbers <NUM>~<NUM>) marked by the leading term "D1" are the pins associated with the semiconductor die <NUM>, the pins marked by the leading term "D2" are the pins associated with the semiconductor die <NUM>, the pins marked by the leading term "D3" are the pins associated with the semiconductor die <NUM> and the pins marked by the leading term "D4" are the pins associated with the semiconductor die <NUM>.

As shown in <FIG>, the power pad (or, the associated power pin) DVDD_1 of the semiconductor die <NUM> is electrically connected to the ground pad (or, the associated ground pin) DVSS_2 of the semiconductor die <NUM>, the power pad (or, the associated power pin) DVDD_2 of the semiconductor die <NUM> is electrically connected to the ground pad (or, the associated ground pin) DVSS_3 of the semiconductor die <NUM>, and the power pad (or, the associated power pin) DVDD_3 of the semiconductor die <NUM> is electrically connected to the ground pad (or, the associated ground pin) DVSS_4 of the semiconductor die <NUM>. In addition, the power pad DVDD_4 of the semiconductor die <NUM> may be configured to receive power from an external power source via a power node or a power pin of the semiconductor device <NUM>, and the ground pad (or, the associated ground pin) DVSS_1 of the semiconductor die <NUM> may be further coupled to a ground node.

<FIG> is a schematic diagram showing six chips (or, semiconductor packages) on the PCB according to another embodiment not belonging to the invention, where each chip has three semiconductor dies packaged therein, and the semiconductor dies packaged in one chip are coupled in serial. The semiconductor dies or chips disposed on the PCB <NUM> are configured to provide the same function.

In this embodiment, the semiconductor device <NUM> may comprise chips <NUM>~<NUM> mounted on the PCB <NUM> and/or the substrate. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein.

The chips <NUM> and <NUM>, <NUM> and <NUM> and <NUM> and <NUM> are respectively coupled in serial between the power node for receiving the power V_Power and the ground node. In addition, the semiconductor device <NUM> may further comprise a parallel structure in which three chip sets (that is, the chip set comprising chips <NUM> and <NUM>, the chip set comprising chips <NUM> and <NUM> and the chip set comprising chips <NUM> and <NUM>) are coupled in parallel.

In <FIG>, an exemplary signal routing path within the semiconductor device <NUM> is shown. Via the routings on PCB <NUM> and the internal signal transmission paths within the chips, a signal received from an external device via chip <NUM> may be sequentially routed or transmitted from one semiconductor die to another, and may be sequentially routed or transmitted from one chip to another, as the arrows shown in <FIG>. For another signal to be transmitted from the semiconductor device <NUM> to the external device (e.g. a CPU), the signal may be routed or transmitted to the external device in a reverse direction.

The signal transmission paths within a chip and among different chips and the pin connections are similar to the embodiment shown in <FIG> and <FIG>. It is readily appreciated for the person of ordinary skill in the art to derive the signal transmission paths within a chip and among different chips of <FIG> based on the descriptions of <FIG> and <FIG>. Therefore, details of the descriptions may refer to the descriptions of <FIG> and <FIG>, and are omitted here for brevity.

<FIG> is a schematic diagram showing six chips (or, semiconductor packages) on the PCB according to yet another embodiment not belonging to the invention, where each chip has four semiconductor dies packaged therein, and the semiconductor dies packaged in one chip are coupled in serial. The semiconductor dies or chips disposed on the PCB <NUM> are configured to provide the same function.

In this embodiment, the semiconductor device <NUM> may comprise chips <NUM>-<NUM> mounted on the PCB <NUM>. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein. The chip <NUM> comprises semiconductor dies <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> packaged therein.

In <FIG>, an exemplary signal routing path within the semiconductor device <NUM> is shown. Via the routings on PCB <NUM> and the internal signal transmission paths within the chips, a signal received from an external device via chip <NUM> may be sequentially routed or transmitted from one semiconductor die to another, and may be sequentially routed or transmitted from one chip to another, as the arrows shown in <FIG>. For another signal to be transmitted from the semiconductor device <NUM> to the external device (e.g. an CPU), the signal may be routed or transmitted to the external device in a reverse direction.

It should be noted that although in the embodiments discussed above, the serial power systems having a plurality of functional blocks (e.g. the computing circuits, the computing circuit macros, the semiconductor dies, the semiconductor packages or the chips) coupled in serial are proposed, the functional blocks can function simultaneously after they have been initialized and stabilized. When a great number of functional blocks, such as computing circuits, begin to perform corresponding functions at the same time, it can provide huge computing-power.

In addition, in the embodiments discussed above, since the same current will flow through the functional blocks coupled in serial, the power consumption can be greatly reduced. For example, for two dies connected in serial in one package, the current is half and the power consumption is half as well as compared to the structure having two dies coupled in parallel. In addition, the package-size of the proposed structure (for example, two or more dies connected in serial in one package) is smaller than that of the conventional structure having a single die in one package. Therefore, the BOM (Bill of Materials) list and circuit area on PCB can also be saved.

In addition, as discussed above, in the embodiments discussed above, based on the proposed structures, a smooth layout on package-substrate routing and a straightforward layout on PCB routing can be achieved.

Claim 1:
A semiconductor device (<NUM>) realizing a serial power system, comprising:
a plurality of functional blocks (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), each being configured to provide at least one predetermined function, and
a printed circuit board (<NUM>),
wherein each functional block of the plurality of functional blocks (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) is disposed on the printed circuit board (<NUM>),
wherein the functional blocks at least comprise:
a first functional block (<NUM>) and
a second functional block (<NUM>), and
wherein the first functional block (<NUM>) and the second functional block (<NUM>) are coupled in serial to enable a predetermined current (I) flowing therethrough,
characterized in that
the printed circuit board (<NUM>) is adapted so that at least one control signal received from the first functional block (<NUM>) is relayed to the second functional block (<NUM>),
wherein the functional blocks further comprises a third functional block (<NUM>) and a fourth functional block (<NUM>), the third functional block (<NUM>) and the fourth functional block (<NUM>) are coupled in serial to enable a second predetermined current flowing therethrough and the printed circuit board (<NUM>) is further adapted so that the at least one control signal received from the first functional block (<NUM>) is further relayed from the first functional block (<NUM>) to the third functional block (<NUM>) and relayed from the second functional block (<NUM>) to the fourth functional block (<NUM>);
wherein the first functional block is a first chip (<NUM>), the second functional block is a second chip (<NUM>), the third functional block is a third chip (<NUM>), the fourth functional block is a fourth chip (<NUM>), a first control signal output pin (<NUM>) of the first chip (<NUM>) is electrically connected to a control signal input pin (<NUM>) of the second chip (<NUM>) via a first connecting element on the printed circuit board (<NUM>), a second control signal output pin (<NUM>) of the first chip (<NUM>) is electrically connected to a control signal input pin (<NUM>) of the third chip (<NUM>) via a second connecting element on the printed circuit board (<NUM>), and a control signal output pin (<NUM>) of the second chip (<NUM>) is electrically connected to a control signal input pin (<NUM>) of the fourth chip (<NUM>) via a third connecting element on the printed circuit board (<NUM>).