Patent Description:
Integrated circuits typically comprise power rails (for example for VSS and VDD supply voltage distribution). Conventionally, power rails are encapsulated within a back-end-of-line (BEOL) interconnect structure located above the level of the active physical devices (such as transistors). In contrast, a "buried" power rail (BPR) is at least partly lowered into the substrate, such that the power rail may be located at a level below the active physical devices. Burying power rails enables the cross-section of the power rails to be increased (for example reducing the line resistance) without occupying valuable space in the BEOL interconnect structure which can be used for other purposes, such as for example signal lines. As an example in the context of finFET technology, BPR formation may involve etching trenches in the substrate at positions between pairs of adjacent fins. The trenches may subsequently be filled with metal to form the BPRs.

<CIT> discloses methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

<CIT> discloses a structure and method for forming a contact plug in a contact hole in a dielectric layer on a semiconductor substrate. A polysilicon spacer is formed on the sidewalls and bottom of the contact hole. A metal, such as titanium, is deposited on the sidewalls and bottom of the hole and on the dielectric layer. The substrate is heated to form a metal silicide layer, such as TiSix, and a metal nitride layer, such as TiN, on the side-walls and bottom of the contact hole. Any remaining metal layer and metal nitride layer formed in the heating process is removed. This leaves the titanium silicide layer on the contact hole walls. Tungsten is deposited to fill the contact hole where the metal silicide promotes the nucleation of the tungsten. In a preferred embodiment, to further promote nucleation of the tungsten, a second metal nitride layer is formed on the surface; of the metal silicide layer just prior to tungsten deposition.

<CIT> discloses embodiments directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

It is envisaged that the use of BPR will be challenging in future smaller technology nodes, since it may be difficult to process the BPR with a maintained quality as the critical dimension, CD is reduced and the aspect ratio increased. In particular, quality problems related to trench etching, metal filling and etch-back are envisaged.

In view of this, it is an objective of the present inventive concept to provide an improved method for forming buried power rails, or more generally buried metal lines. Further and alternative objectives may be understood from the following.

According to an aspect of the present inventive concept, there is provided a method for forming a buried metal line in a semiconductor substrate, wherein the method comprises:.

The inventive method allows for a simplified metallisation process for forming the buried metal line. With the present method, the metal line material can be selectively deposited prior to embedding the pair of semiconductor structures in the insulating layer. This is advantageous for several reasons, and in particular over prior art techniques in which the metal line material is deposited in a trench etched through the insulating layer.

Firstly, there is no need to form a trench in the insulating layer, which is then filled with the metal line material and recessed back down to the base of the pair of semiconductor structure. The forming of a trench in the insulating layer is known to be a complicated process, in particular for the increasing aspect ratios associated with the strive for scaling to smaller physical dimensions. The inventive method is advantageous in that the metal line can be defined without requiring the etching of such a trench.

Secondly, forming the metal line through a trench in the insulating layer generally require the metal line material to be etched back in the trench, towards the base of the pair of semiconductor structures. This etch-back process may be impaired with uniformity related issues and risks to damage other structures. Thus, it is an advantage to instead use a selective deposition to form the metal line, which can be done without an etch-back of the metal line material through a trench in the insulating layer.

As used herein, the term "buried metal line" is used to refer to a metal line structure which is at least partially embedded in the substrate. As will be further set out herein, the metal line may be formed with a height less than a height of the metal line trench, wherein the metal line may be completely embedded / buried in the substrate. The metal line may also be formed with a height exceeding a height of the metal line trench, wherein the metal line may be partially embedded / buried in the substrate.

The pair of semiconductor structures may be formed by a pair of semiconductor bodies, such as a pair of semiconductor fins (for example for finFETs), or a pair of nano-sheets or lateral nanowires.

A may be appreciated, the pair of semiconductor structures may comprise a pair of mutually facing sidewall surfaces (i.e. a pair of sidewall surfaces in a mutually facing relationship), which in the following may be referred to as the pair of mutually facing sidewall surfaces of the pair of semiconductor structures. The pair of mutually facing sidewall surfaces of the pair of semiconductor structures may be formed on mutually opposite sides of the metal line trench to be formed.

Reference may herein be made to a "vertical" direction to denote a direction along a normal to the substrate (i.e. a normal to a main/upper surface of the substrate). Meanwhile, "vertical" qualifiers such as "below" and "above" may be used to refer of relative positions with respect to the vertical direction, and do hence not imply an absolute orientation of the substrate. Accordingly, the term "below" may be used to refer to a relative position closer to a main surface of the substrate. The term "above" may be used to a position farther from a main surface of the substrate. For example, a first level or element located below a second level or element implies that the first level or element is closer to the main surface of the substrate than the second level or element is. Conversely, a first level or element located above a second level or element implies that the first level or element is farther from the main surface of the substrate than the second level or element is.

The term "horizontal" may meanwhile be used to denote a direction or orientation parallel to the substrate (i.e. a main plane of extension or main surface thereof), or equivalently transverse to the vertical direction. Further, a lateral direction may be understood as a horizontal direction.

The metal line material may be deposited using several different techniques, as will be discussed in the following in connection with various embodiments.

The metal line is formed by means of an area selective process, in which the metal line material is provided primarily in the metal line trench and deposition of material outside the trench is hindered. The selectivity may be achieved by various means for providing a surface specificity between growth areas, in which the metal line material is desired, and non-growth areas, in which metal line material is not desired. The growth areas may generally be provided within the metal line trench, whereas the non-growth areas may be provided outside the trench. As a result, metal line material may be provided in the metal line trench only. The surface specificity may be achieved by means of for example area selective epitaxy, area selective CVD, and the deactivation of non-growth surfaces. The non-growth areas may for example be provided with a growth-inhibiting layer, which may be provided on surfaces outside the metal line trench. Further, the selective deposition process may be combined with selective etching to remove metal line material that may have formed on non-growth areas.

A growth-promoting layer is provided in the metal line trench in order to promote selective growth of the metal line material in the trench. The growth-promoting layer is provided in the trench prior to the forming of the metal line in the trench, and further serves the purpose of a barrier layer between the metal line material and the substrate. It will be appreciated that the growth-promoting layer may be formed of one or several layers, and that the layer(s) may be provided on the bottom surface and the sidewalls of the trench, or on the bottom surface only.

According to an embodiment, the growth-promoting layer may comprise a silicide. The silicide may for example be formed by deposition of a silicide metal, such as titanium, followed by an anneal in which the silicide metal may reacts with the material of the substrate to form a silicide. The silicide metal may be prevented from forming a silicide in non-growth areas, such as areas outside the metal line trench and on dielectric surfaces of for instance silicon nitride or silicon oxide, by first providing an intermediate layer on the non-growth areas. Thus, the silicide may be formed only on surfaces for which the silicide metal is provided directly on the silicon substrate. The intermediate layer may hence form a barrier between the silicide metal and the underlying silicon, thus preventing silicide to be formed in those areas. The intermediate layer may for example comprise a nitride, such as Si<NUM>N<NUM>, forming a liner on the pair of semiconductor structures. The liner may be provided prior to the forming of the metal line trench, such that the surfaces of the resulting trench are free from the liner material and thus can form a silicide with the silicide metal. The non-reacted silicide metal may be removed after the anneal, for example by means of a wet etch.

The metal line trench may for example be formed in a lithographic process, or by means of a spacer patterning process. Lithographic patterning may be a relatively fast and simple process, whereas spacer patterning may be employed to achieve a self-alignment and provide pattern features with linewidths smaller than can be achieved by conventional lithography. In one example, the metal line trench may be formed by providing a spacer on sidewall surfaces of the pair semiconductor structures so as to define an etch mask protecting the sidewall surfaces while the metal line trench is etched into the substrate between the pair of semiconductor structures.

Forming the spacer may comprise conformally depositing a spacer layer, and anisotropically etching the spacer layer to expose the region between the pair of semiconductor structures in which the metal line trench is to be defined. A thickness of the spacer may be precisely controlled via controlling a thickness of the deposited spacer layer. Owing to the conformal deposition, the spacer layer may be deposited on the sidewall surfaces and the bottom surface of the space between the pair of semiconductor structures. Alternatively, or additionally, lithography may be used to pattern an etch mask through which the spacer layer may be etched to expose the metal line trench region of the substrate.

After the etching of the metal line trench, a growth-promoting layer and barrier layer is provided in the trench (e.g. in a similar manner a described for the embodiment above).

In one example, the trench etch may be followed by the formation of an oxide layer, such as SiO<NUM> in the trench and on the spacer, and thereafter a deposition of a silicidation metal comprising for example titanium. The metal line trench, or at least a bottom part of the trench, may then be provided with a mask layer that protects the underlying silicidation metal in a subsequent etch-back process. The remaining silicidation metal may be used to facilitate selective growth of metal line material in the trench. Preferably, the metal line material is deposited while the spacer remains on the pair of semiconductor structures, such that any metal line material that has deposited on areas outside the metal line trench can be removed together with the spacer so as to further increase the selectivity of metal line material deposition process.

In a further example, the metal line material, which may at least partly fill the metal line trench and the gap defined by the sidewall spacers, may subject to an etch-back process in which the metal line material may be recessed back towards the metal line trench. The etch-back process may determine the height of the metal line, which for example may exceed a depth of the metal line trench so as to facilitate subsequent contacting from above. By allowing the metal line trench to protrude from the metal line trench, the depth of the contact via, required to access the buried metal line through the insulating layer, may be reduced.

<FIG> are cross sections illustrating method steps for forming a buried metal line in a semiconductor substrate.

Methods for forming a buried metal line in a semiconductor substrate will now be described with reference of the figures. The figures all schematically show, in cross-sections, a semiconductor device comprising a substrate <NUM> and a pair of semiconductor structures <NUM>, <NUM> (hereinafter "fins" <NUM>, <NUM>) protruding from the substrate <NUM>. The following methods will be described in relation to a single pair of fins <NUM>, <NUM> and for forming a single buried metal line. However, as also is indicated in some of the figures, the method steps may be applied in parallel at a plurality of positions along the substrate to form buried metal lines between a plurality of pairs of fins. It may further be noted that the relative dimensions of the shown structures, for instance the relative thickness of layers, is merely schematic and may, for the purpose of illustrational clarity, differ from a physical device structure.

In the claimed invention, the substrate <NUM> is a semiconductor substrate, i.e., a substrate comprising at least one semiconductor layer. The substrate <NUM> may be a single-layered semiconductor substrate, for instance formed by a bulk substrate. The substrate may however also be a multi-layered substrate, for instance formed by an epitaxially grown semiconductor layer on a bulk substrate, or a semiconductor-on-insulate (SOI) substrate. The substrate <NUM> may for instance comprise a layer of silicon (Si), germanium (Ge) or silicon germanium (SiGe), to name a few.

As indicated in <FIG>, the fins <NUM>, <NUM> protrude in a vertical direction, or equivalently in parallel to a normal direction with respect to the substrate <NUM>. In the claimed invention, the pair of fins <NUM>, <NUM> are spaced apart along a first horizontal direction and may extend in parallel to each other in a second horizontal direction. The horizontal directions may be mutually perpendicular along the substrate <NUM>. The pair of fins <NUM>, <NUM> may define a pair of mutually facing sidewall surfaces which, as will be shown, may be located on opposite sides of the metal line which is to be formed between the pair of fins <NUM>, <NUM>.

The fins <NUM>, <NUM> may for example comprise Si, Ge or SiGe. The semiconductor structures <NUM>, <NUM> may be homogenous, single-layered semiconductor bodies, for example patterned in a single semiconductor layer of the substrate <NUM>. The semiconductor structures <NUM>, <NUM> may also be multi-layered semiconductor bodies, such as a superlattice of for instance Si/SiGe layers, which may enable lateral gate-all-around (GAA) device formation. The multi-layered semiconductor bodies may for example patterned in a stack of semiconductor layers of the substrate <NUM>. The fins may be formed on the substrate <NUM> in a fin patterning process in a conventional manner. As is known in the art, semiconductor fins may be used for forming horizontal channel devices, such as finFETs extending across the fin.

<FIG> illustrates a plurality of semiconductor structures, i.e., the fins, protruding from the semiconductor substrate <NUM>. In the following, two of the fins <NUM>, <NUM>, forming a pair, will be discussed in order to illustrate the inventive method. The fins <NUM>, <NUM> may for example be patterned in a Si substrate <NUM> by means of a hardmask <NUM> illustrated on top of the fins <NUM>, <NUM>.

In <FIG>, an insulating liner <NUM> has been formed on the fins <NUM>, <NUM> and on the surface of the substrate <NUM> extending between the fins <NUM>, <NUM>. The liner <NUM> may for instance be an ALD oxide or nitride, such as SiO<NUM>, SiN or Si<NUM>N<NUM>. The liner <NUM> may be provided to prevent oxidation of the fins <NUM>, <NUM> during for example shallow trench isolation (STI) deposition and annealing.

In a subsequent steps the metal line trench <NUM> is formed. In the present example, this is done by means of lithography. As shown in <FIG>, an etch mask <NUM>, comprising a stack of spin-on-glass and spin-on-carbon, has been patterned to define the metal line trench between the pair of fins <NUM>, <NUM>. <FIG> shows the result after the metal line trench <NUM> has been etched through the liner <NUM> and into the silicon substrate <NUM> and the etch mask <NUM> removed.

In <FIG> a metal barrier layer <NUM> has been conformally deposited on the liner <NUM>, covering sidewall surfaces of the fins <NUM>, <NUM>, as well as in the metal line trench <NUM>. The metal barrier layer <NUM> may be a layer of TiN, deposited for instance by ALD. However, the metal barrier layer <NUM> may also be formed by any other metal which enables the metal barrier layer <NUM> to act as a barrier and adhesion layer for the subsequent deposited metal line material. Due to the conformal deposition, the sidewalls of the metal line trench <NUM> may be reliably covered.

Preferably, the metal barrier layer <NUM> comprises a silicide metal that is capable of forming a silicide with the silicon in the metal line trench <NUM>. An example shown in <FIG>, in which a layer of TiN <NUM> has been annealed to form a silicide <NUM>. The silicide tends to be selectively formed in the metal line trench <NUM>, since the silicidation metal <NUM> was deposited directly on the silicon surfaces of the metal line trench <NUM>. Outside the trench <NUM> the silicidation metal <NUM> was deposited on the liner <NUM>, which prevents the metal <NUM> from forming a silicide with the silicon.

After anneal the remaining silicidation metal <NUM>, i.e., the parts of the metal barrier layer <NUM> which have not reacted to form the silicide, may be removed by for example a wet etch. The result is illustrated in <FIG>, showing the fin pair <NUM>, <NUM> covered with the liner <NUM> and the metal line trench <NUM> provided with a trench barrier layer <NUM> comprising silicide. The trench barrier layer <NUM> may enable a selective deposition of a metal line material, as will be illustrated in the following.

In <FIG>, a metal line material <NUM> has been selectively deposited in the metal line trench <NUM>. Examples of metals for the metal line include Co, W, Ni, Ru and Al. The metal(s) may be deposited by conventional deposition techniques such as physical vapour deposition (PVD, CVD or ALD), or electroless plating of e.g. Co. The metal <NUM> is selectively deposited on the silicided trench barrier layer <NUM> while not nucleating on the liner <NUM> covering the sidewalls of the fins <NUM>, <NUM>. The metal line material <NUM> may be deposited until the metal line trench <NUM> is filled, and preferably until the resulting metal line <NUM> protrudes above the trench <NUM>. The selective deposition of the metal line material <NUM>, which process also may be referred to as an area selective deposition, ALD, is facilitated by the liner <NUM> acting as a growth-inhibiting layer on non-growth areas, and by the silicide acting as a growth-promoting layer on the growth areas (i.e., the sidewalls of the metal line trench <NUM>).

The surface specificity between growth areas and non-growth areas may be further increased by combining the above deposition with etching, in which any metal line material that may have formed on non-growth areas is removed.

In <FIG>, an additional liner <NUM> of for instance Si<NUM>N<NUM> has been deposited to cover the metal line <NUM> formed by the metal line material <NUM> in the trench <NUM>. Thereafter, an insulating layer <NUM> has been provided, burying the metal line <NUM> in the substrate <NUM> and embedding the fins <NUM>, <NUM>. The insulating layer <NUM> may for example comprise an oxide, such as SiO<NUM>, and may form an STI layer as readily known in the art.

The resulting semiconductor device <NUM> is shown in <FIG>, in which the hardmask <NUM> on the fins <NUM>, <NUM> has been removed and the insulating layer <NUM> recessed to expose an upper portion of the fins <NUM>, <NUM>. The upper portion of the fins <NUM>, <NUM> may provide an active area, or device area, in which for example finFETs may be formed in subsequent processes.

<FIG> show a variation of a method of forming the buried metal line. The method proceeds in a similar manner as outlined in relation to <FIG>, but however differs in the steps for forming the metal line trench <NUM> in the substrate <NUM>. In <FIG>, a spacer <NUM> has been formed on sidewall surfaces of the fins <NUM>, <NUM> and on surface portions of the substrate <NUM> between the fins <NUM>, <NUM>. The spacer <NUM> may for example comprise a conformally deposited layer of for instance SiO<NUM>. As shown in <FIG>, the thickness of the spacer layer <NUM> may, together with the spacing of the fins <NUM>, <NUM>, define a gap between the sidewalls of the fins <NUM>, <NUM> facing each other. This gap may be used to the define the metal line trench in a self-aligned manner.

In <FIG>, an etch mask <NUM>, comprising for instance a stack of spin-on-glass and spin-on-carbon, has been patterned by means of lithography to protect the spacer layer <NUM> while the metal line trench <NUM> is etched. The spacer layer <NUM> may be etched in an anisotropic etch, during which the sidewalls of the fins <NUM>, <NUM> are masked by the spacer layer <NUM>. As shown in <FIG>, the spin-on etch mask <NUM> may be used to protect the horizontal surfaces of the spacer layer <NUM> during the trench definition.

In <FIG>, the metal line trench <NUM> has been formed, the spin-on etch mask <NUM> has been removed and the sidewalls of the metal line trench <NUM> covered with a liner <NUM> and a metal barrier layer <NUM> similar to the ones described in connection with <FIG>. In the present example, the liner <NUM> may comprise for instance SiN or SiO<NUM>.

Two illustrative examples of the deposition of the metal line material in a self-aligned metal line trench, which may be formed by means of the spacer shown in <FIG>, will be discussed in the following. <FIG> outline a first example, whereas <FIG> outline a second example.

<FIG> show the structure of <FIG> after it has been coated with a mask material <NUM>, such as for example a spin-on-carbon. The mask material <NUM> may thus fill the metal line trench <NUM>, the gap between the pair of fins <NUM>, <NUM>, and form a layer above the fins <NUM>, <NUM>.

In <FIG>, the mask material <NUM> has been etched back such that only a portion of the mask material <NUM> remains in the bottom of the metal line trench <NUM>. The remaining mask material <NUM> protects the metal barrier layer <NUM> in the bottom of the metal line trench <NUM> during a subsequent etch, in which the metal barrier layer <NUM> may be removed from the rest of the trench <NUM> and the spacer layer <NUM> defining the gap between the fins <NUM>, <NUM>. The metal barrier layer <NUM>, which for example may be a layer of TiN, can be etched selectively to the mask material, which for example may be a SoC, by means of for instance an ammonia hydroxide-hydrogen peroxide-water mixture (APM) or a dydrochloric acid-hydrogen peroxide-water mixture (HPM). The remaining metal barrier layer <NUM>, which has been protected by the mask material <NUM>, may in this example serve the purpose of facilitating a selective deposition of the metal line material <NUM> in the trench <NUM>. As shown in <FIG>, the metal line material <NUM>, which for instance may comprise Ru or W, may be deposited by means of for example CVD. The metal barrier layer <NUM>, which for instance may comprise TiN, may form a nucleation layer onto which the metal line material <NUM> may grow during the deposition, while the liner <NUM> of for example SiO<NUM> may act as a growth-inhibiting layer.

After deposition the liner <NUM> and the spacer layer <NUM> may be removed in for example a wet etch. This etch will also remove any metal line material <NUM> that may have been deposited outside the trench <NUM>, such as for example on the horizontal surfaces of the spacer layer <NUM> above the fins <NUM>, <NUM> as indicated in <FIG>, and at sidewalls of the fins <NUM>, <NUM>. The result is shown in <FIG>, in which a capping liner <NUM> has been deposited after the removal of the spacer layer <NUM>. The capping liner <NUM> may be similar to the liner <NUM> provided in for example <FIG>, and may in some examples comprise Si<NUM>N<NUM>. The capping liner may further cover the metal line <NUM>, which has been defined by the selective deposition of the metal line material <NUM> in the trench <NUM>.

Thereafter, an insulating layer <NUM> may be provided, burying the metal line <NUM> in the substrate <NUM> and embedding the fins <NUM>, <NUM> as shown in <FIG>. The insulating layer <NUM> may for example comprise an oxide, such as SiO<NUM>, and may form an STI layer as readily known in the art.

The resulting semiconductor device <NUM> is shown in <FIG>, in which the hardmask <NUM> of the fins <NUM>, <NUM> has been removed and the insulating layer <NUM> recessed to expose an upper portion of the fins <NUM>, <NUM> in a similar way as discussed in connection with <FIG>.

<FIG> show a variation of a method of forming the buried metal line. The method proceeds in a similar manner as outlined in relation to <FIG>, but however differs in the steps for depositing the metal line material in the metal line trench <NUM>. <FIG> shows a structure similar to the one in <FIG>, in which the metal line trench <NUM> and the gap defined by the spacer layer on the fins <NUM>, <NUM> have been filled with a metal line material <NUM>. The metal line metal deposition may be followed by a CMP and an etch-back process, in which the metal line material <NUM> and the metal barrier layer <NUM> may be etched back until a desired height of the metal line is achieved. The result is shown in <FIG>. After the etch-back, the liner <NUM> and the spacer layer <NUM> may be removed in a similar manner as indicated in <FIG>.

In the above, the methods have been disclosed with reference to semiconductor structures in the form of fins. However, the methods are applicable also for forming a buried metal line between a pair of semiconductor structure in the form of for instance a pair of lateral semiconductor nanowires, or a pair of vertical semiconductor nanosheets. Nanowires may be formed with a rounded or square cross-sectional shape. Nanosheets may be formed with an oblong rectangular cross-sectional shape (however typically with a length to width ratio smaller than a length to width ratio of a semiconductor fin). A plurality of pillars may be formed on the substrate, for example in an array having a plurality of rows and columns wherein a buried metal line may be formed between pillars of an adjacent pair of rows or columns of the array. The metal line trench may thus be formed to extend between and along a plurality of corresponding pairs of pillars arranged along the same rows (or columns) as the pair of pillars. As is known in the art, nanowires and nanosheets may be used for forming lateral channel devices, such as gate-all-around VFETs.

Claim 1:
A method for forming a buried metal line (<NUM>) in a semiconductor substrate (<NUM>), the method comprising:
at a position between a pair of semiconductor structures (<NUM>, <NUM>) protruding from the semiconductor substrate, forming a metal line trench (<NUM>) in the semiconductor substrate at a level below a base of each semiconductor structure of the pair,
forming the metal line in the metal line trench by means of area selective deposition of a metal line material (<NUM>), followed by
embedding the pair of semiconductor structures in an insulating layer (<NUM>),
characterized in that the method further comprises, prior to forming the metal line in the metal line trench:
forming a barrier layer (<NUM>) in the trench, wherein the barrier layer is adapted to promote selective growth of the metal line material in the metal line trench.