Patent Description:
Artificial neural networks mimic biological neural networks (e.g., the central nervous systems of animals, in particular the brain) which are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown.

<FIG> illustrates an artificial neural network <NUM>, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.

One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.

Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in <CIT>, The non-volatile memory arrays operate as analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. Publication <CIT> discloses a redundant memory module included on chip to allow replacement of any defective regular module. Publication <CIT> discloses redundant nanowires using a learning machine such as a neural network, to detect defective memory elements.

Each non-volatile memory cells used in the analog neuromorphic memory system must be erased and programmed to hold a very specific and precise amount of charge in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include <NUM>, <NUM>, and <NUM>.

One unique characteristic of analog neuromorphic memory systems is that the system must support two different types of read operations. In a normal read operation, an individual memory cell is read as in conventional memory systems. However, in a neural read operation, the entire array of memory cells is read at one time, where each bit line will output a current that is the sum of all currents from the memory cells connected to that bit line.

Supporting both types of read operations leads to several challenges. One challenge is how to provide redundancy for the system. Where multiple redundant rows or columns are being used (due to the occurrence of multiple faulty rows or columns), the system must be able to activate all of the redundant rows or columns at one time during a neural read operation. However, in conventional systems, a read or program operation will operate on only one row or a sector of rows at any given time-and not all of them-and therefore only some of the redundant rows or columns will need to be asserted at any given time. Thus, prior art decoding systems do not support a neural read operation.

What is needed is an improved decoding system to be used with analog neuromorphic memory to provide redundancy during programming, erase, read, and neural read operations.

Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

Digital non-volatile memories are well known. For example, <CIT> ("the '<NUM> patent") discloses an array of split gate non-volatile memory cells, and is incorporated herein by reference for all purposes. Such a memory cell is shown in <FIG>. Each memory cell <NUM> includes source region <NUM> and drain region <NUM> formed in a semiconductor substrate <NUM>, with a channel region <NUM> there between. A floating gate <NUM> is formed over and insulated from (and controls the conductivity of) a first portion of the channel region <NUM>, and over a portion of the source region <NUM>. A word line terminal <NUM> (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region <NUM>, and a second portion that extends up and over the floating gate <NUM>. The floating gate <NUM> and word line terminal <NUM> are insulated from the substrate <NUM> by a gate oxide. Bitline <NUM> is coupled to drain region <NUM>.

Memory cell <NUM> is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal <NUM>, and a positive voltage on the source <NUM>. Electron current will flow from the source <NUM> towards the drain <NUM>. The electrons will accelerate and become heated when they reach the gap between the word line terminal <NUM> and the floating gate <NUM>. Some of the heated electrons will be injected through the gate oxide <NUM> onto the floating gate <NUM> due to the attractive electrostatic force from the floating gate <NUM>.

Memory cell <NUM> is read by placing positive read voltages on the drain <NUM> and word line terminal <NUM> (which turns on the channel region under the word line terminal). If the floating gate <NUM> is positively charged (i.e. erased of electrons and positively coupled to the drain <NUM>), then the portion of the channel region under the floating gate <NUM> is turned on as well, and current will flow across the channel region <NUM>, which is sensed as the erased or "<NUM>" state.

Other split gate memory cell configurations are known. For example, <FIG> depicts four-gate memory cell <NUM> comprising source region <NUM>, drain region <NUM>, floating gate <NUM> over a first portion of channel region <NUM>, a select gate <NUM> (typically coupled to a word line) over a second portion of the channel region <NUM>, a control gate <NUM> over the floating gate <NUM>, and an erase gate <NUM> over the source region <NUM>. This configuration is described in <CIT>, which is incorporated herein by reference for all purposes). Programming is shown by heated electrons from the channel region <NUM> injecting themselves onto the floating gate <NUM>. Erasing is shown by electrons tunneling from the floating gate <NUM> to the erase gate <NUM>.

<FIG> depicts split gate three-gate memory cell <NUM>. Memory cell <NUM> is identical to the memory cell <NUM> of <FIG> except that memory cell <NUM> does not have a separate control gate. The erase operation (erasing through erase gate) and read operation are similar to that of the <FIG> except there is no control gate bias. The programming operation also is done without the control gate bias, hence the program voltage on the source line is higher to compensate for lack of control gate bias.

<FIG> depicts stacked gate memory cell <NUM>. Memory cell <NUM> is similar to memory cell <NUM> of <FIG>, except floating gate <NUM> extends over the entire channel region <NUM>, and control gate <NUM> extends over floating gate <NUM>, separated by an insulating layer. The erase, programming, and read operations operate in a similar manner to that described previously for memory cell <NUM>.

Specifically, the memory state (i.e. charge on the floating gate) of each memory cells in the array can be continuously changed from a fully erased state to a fully programmed state, independently and with minimal disturbance of other memory cells.

<FIG> conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses the non-volatile memory array neural net for a facial recognition application, but any other appropriate application could be implemented using a non-volatile memory array based neural network.

S0 is the input, which for this example is a 32x32 pixel RGB image with <NUM> bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being <NUM> bit precision). The synapses CB1 going from S0 to C1 have both different sets of weights and shared weights, and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by <NUM> pixel (or more than <NUM> pixel as dictated by the model). Specifically, values for <NUM> pixels in a 3x3 portion of the image (i.e., referred to as a filter or kernel) are provided to the synapses CB1, whereby these <NUM> input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first neuron of CB1 for generating a pixel of one of the layers of feature map C1. The 3x3 filter is then shifted one pixel to the right (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the <NUM> pixel values in this newly positioned filter are provided to the synapses CB1, whereby they are multiplied by the same weights and a second single output value is determined by the associated neuron. This process is continued until the 3x3 filter scans across the entire 32x32 pixel image, for all three colors and for all bits (precision values). The process is then repeated using different sets of weights to generate a different feature map of C1, until all the features maps of layer C1 have been calculated.

At C1, in the present example, there are <NUM> feature maps, with 30x30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two dimensional array, and thus in this example the synapses CB1 constitutes <NUM> layers of two dimensional arrays (keeping in mind that the neuron layers and arrays referenced herein are logical relationships, not necessarily physical relationships - i.e., the arrays are not necessarily oriented in physical two dimensional arrays). Each of the <NUM> feature maps is generated by one of sixteen different sets of synapse weights applied to the filter scans.

An activation function P1 (pooling) is applied before going from C1 to S1, which pools values from consecutive, non-overlapping 2x2 regions in each feature map. The purpose of the pooling stage is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage. At S1, there are <NUM>15x15 feature maps (i.e., sixteen different arrays of 15x15 pixels each). The synapses and associated neurons in CB2 going from S1 to C2 scan maps in S1 with 4x4 filters, with a filter shift of <NUM> pixel. At C2, there are <NUM>12x12 feature maps. An activation function P2 (pooling) is applied before going from C2 to S2, which pools values from consecutive non-overlapping 2x2 regions in each feature map. At S2, there are <NUM>6x6 feature maps. An activation function is applied at the synapses CB3 going from S2 to C3, where every neuron in C3 connects to every map in S2. At C3, there are <NUM> neurons. The synapses CB4 going from C3 to the output S3 fully connects S3 to C3.

Each level of synapses is implemented using an array, or a portion of an array, of non-volatile memory cells. <FIG> is a block diagram of the vector-by-matrix multiplication (VMM) array that includes the non-volatile memory cells, and is utilized as the synapses between an input layer and the next layer. Specifically, the VMM <NUM> includes an array of non-volatile memory cells <NUM>, erase gate and word line gate decoder <NUM>, control gate decoder <NUM>, bit line decoder <NUM> and source line decoder <NUM>, which decode the inputs for the memory array <NUM>. Source line decoder <NUM> in this example also decodes the output of the memory cell array. Alternatively, bit line decoder <NUM> can decode the output of the memory array. The memory array serves two purposes. First, it stores the weights that will be used by the VMM. Second, the memory array effectively multiplies the inputs by the weights stored in the memory array and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, the memory array negates the need for separate multiplication and addition logic circuits and is also power efficient due to in-situ memory computation.

The output of the memory array is supplied to a differential summer (such as summing op-amp or summing current mirror) <NUM>, which sums up the outputs of the memory cell array to create a single value for that convolution. The differential summer is such as to realize summation of positive weight and negative weight with positive input. The summed up output values are then supplied to the activation function circuit <NUM>, which rectifies the output. The activation function may include sigmoid, tanh, or ReLU functions. The rectified output values become an element of a feature map as the next layer (C1 in the description above for example), and are then applied to the next synapse to produce next feature map layer or final layer. Therefore, in this example, the memory array constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summing op-amp <NUM> and activation function circuit <NUM> constitute a plurality of neurons.

<FIG> is a block diagram of the various levels of VMM. As shown in <FIG>, the input is converted from digital to analog by digital-to-analog converter <NUM>, and provided to input VMM 32a. The input D/A conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs to appropriate analog levels for the matrix multiplier. The input conversion could also be done by an A/A Converter to convert an external analog input to a mapped analog input to the VMM. The output generated by the input VMM 32a is provided as an input to the next VMM (hidden level <NUM>) 32b, which in turn generates an output that is provided as an input to the next VMM (hidden level <NUM>) 32b, and so on. The various layers of VMM's <NUM> function as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM can be a stand-alone non-volatile memory array, or multiple VMMs could utilize different portions of the same non-volatile memory array, or multiple VMMs could utilize overlapping portions of the same non-volatile memory array. The example shown in <FIG> contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e). One of ordinary skill in the art will appreciate that this is merely exemplary and that a system instead could comprise more than two hidden layers and more than two fully connected layers.

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells and reference array <NUM> (at the top of the array). In VMM <NUM>, control gates line such as control gate line <NUM> run in a vertical direction (hence reference array <NUM> in the row direction, orthogonal to the input control gate lines), and erase gate lines such as erase gate line <NUM> run in a horizontal direction. Here, the inputs are provided on the control gate lines, and the output emerges on the source lines. In one embodiment only even rows are used, and in another embodiment, only odd rows are used. The current placed on the source line performs a summing function of all the currents from the memory cells connected to the source line.

As described herein for neural networks, the flash cells are preferably configured to operate in sub-threshold region.

The memory cells described herein are biased in weak inversion: <MAT> <MAT>.

For an I-to-V log converter using a memory cell to convert input current into an input voltage: <MAT>.

For a memory array used as a vector matrix multiplier VMM, the output current is: <MAT> namely <MAT> <MAT>.

Alternatively, the flash memory cells can be configured to operate in the linear region: <MAT> <MAT>.

For an I-to-V linear converter, a memory cell operating in the linear region can be used to convert linearly an input/output current into an input/output voltage.

Other embodiments for the ESF vector matrix multiplier are as described in <CIT>, which is incorporated by reference herein. A sourceline or a bitline can be used as the neuron output (current summation output).

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells, reference array <NUM>, and reference array <NUM>. Reference arrays <NUM> and <NUM>, in column direction of the array, serve to convert current inputs flowing into terminals BLR0-<NUM> into voltage inputs WL0-<NUM>. In effect, the reference memory cells are diode connected through multiplexors with current inputs flowing into them. The reference cells are tuned (e.g., programmed ) to target reference levels. The target reference levels are provided by a reference mini-array matrix. First, it stores the weights that will be used by the VMM <NUM>. Second, memory array <NUM> effectively multiplies the inputs (current inputs provided in terminals BLR0-<NUM>; reference arrays <NUM> and <NUM> convert these current inputs into the input voltages to supply to wordlines WL0-<NUM>) by the weights stored in the memory array and then add all the results (memory cell currents) to produce the output, which will be the input to the next layer or input to the final layer. Here, the voltage inputs are provided on the word lines, and the output emerges on the bit line during a read (inference) operation. The current placed on the bit line performs a summing function of all the currents from the memory cells connected to the bitline.

<FIG> depicts operating voltages for VMM <NUM>.

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells, reference array <NUM>, and reference array <NUM>. The reference array <NUM> and <NUM> run in row direction of the array VMM <NUM> is similar to VMM <NUM> except that in VMM <NUM> the word lines run in the vertical direction. Here, the inputs are provided on the word lines, and the output emerges on the source line during a read operation. The current placed on the source line performs a summing function of all the currents from the memory cells connected to the source line.

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells, reference array <NUM>, and reference array <NUM>. The reference array <NUM> and <NUM> serves to convert current inputs flowing into terminals BLR0-<NUM> into voltage inputs CG0-<NUM>. In effect, the reference memory cells are diode connected through cascoding mulitplexors <NUM> with current inputs flowing into them. The mux <NUM> includes a mux <NUM> and a cascoding transistor <NUM> to ensure a constant voltage on bitline of reference cells in read. First, it stores the weights that will be used by the VMM <NUM>. Second, memory array <NUM> effectively multiplies the inputs (current inputs provided to terminals BLR0-<NUM>; reference arrays <NUM> and <NUM> convert these current inputs into the input voltages to supply to the control gates CG0-<NUM>) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which will be the input to the next layer or input to the final layer. Here, the inputs are provided on the word lines, and the output emerges on the bitline during a read operation. The current placed on the bitline performs a summing function of all the currents from the memory cells connected to the bitline.

VMM <NUM> implements uni-directional tuning for memory cells in memory array <NUM>. That is, each cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell must be erased and the sequence of partial programming operations must start over. As shown, two rows sharing the same erase gate need to be erased together (to be known as a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached,.

<FIG> depicts operating voltages for VMM <NUM>.

<FIG> depicts neuron VMM <NUM>, which is particularly suited for memory cells of the type shown in <FIG>, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM <NUM> comprises a memory array <NUM> of non-volatile memory cells, reference array <NUM>, and reference array <NUM>. EG lines are run vertically while CG and SL lines are run horizontally. VMM <NUM> is similar to VMM <NUM>, except that VMM1600 implements bi-directional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to reach the desired amount of charge on the floating gate. As shown, reference arrays <NUM> and <NUM> convert input current in the terminal BLR0-<NUM> into control gate voltages CG0-<NUM> (through the action of diode-connected reference cells through multiplexors) to be applied to the memory cells in the row direction. The current output (neuron) is in the bitline which sums all currents from the memory cells connected to the bitline.

The prior art includes a concept known as long short-term memory (LSTM). LSTM units often are used in neural networks. LSTM allows a neural network to remember information over arbitrary time intervals and to use that information in subsequent operations. A conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell. VMMs are particularly useful in LSTM units.

<FIG> depicts exemplary LSTM <NUM>. LSTM in this example comprises cells <NUM>, <NUM>, <NUM>, and <NUM>. Cell <NUM> receives input vector x<NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h3. Additional cells can be used, and an LSTM with four cells is merely an example.

<FIG> depicts an exemplary implementation of LSTM cell <NUM>, which can be used for cells <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>. LSTM cell <NUM> receives input vector x(t) and cell state vector c(t-<NUM>) from a preceding cell and generates cell state(t) and output vector h(t).

LSTM cell <NUM> comprises sigmoid function devices <NUM>, <NUM>, and <NUM>, each of which applies a number between <NUM> and <NUM> to control how much of each component in the input vector is allowed through to the output vector. LSTM cell <NUM> also comprises tanh devices <NUM> and <NUM> to apply a hyperbolic tangent function to an input vector, multiplier devices <NUM>, <NUM>, and <NUM> to multiply two vectors together, and addition device <NUM> to add two vectors together.

<FIG> depicts LSTM cell <NUM>, which is an example of an implementation of LSTM cell <NUM>. For the reader's convenience, the same numbering from <FIG> and LSTM cell <NUM> is used in <FIG> and LSTM cell <NUM>. As can be seen in <FIG>, sigmoid function devices <NUM>, <NUM>, and <NUM> and tanh devices <NUM> and <NUM> each comprise multiple VMM arrays <NUM>. Thus, it can be seen that VMM arrays are particular important in LSTM cells used in certain neural network systems.

It can be further appreciated that LSTM systems will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The embodiments described below therefore attempt to minimize the circuitry required outside of the VMM arrays themselves.

Similarly, an analog VMM implementation can be used for a GRU (gated recurrent unit) system. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, with one notable difference being that GRUs lack an output gate.

<FIG> depicts exemplary GRU <NUM>. GRU in this example comprises cells <NUM>, <NUM>, <NUM>, and <NUM>. Cell <NUM> receives input vector x<NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h<NUM> and cell state vector c<NUM>. Cell <NUM> receives input vector x<NUM>, the output vector (hidden state) h<NUM>, and cell state c<NUM> from cell <NUM> and generates output vector h3. Additional cells can be used, and an GRU with four cells is merely an example.

<FIG> depicts an exemplary implementation of GRU cell <NUM>, which can be used for cells <NUM>, <NUM>, <NUM>, and <NUM> in <FIG>. GRU cell <NUM> receives input vector x(t) and cell state vector h(t-<NUM>) from a preceding cell and generates cell state h(t). GRU cell <NUM> comprises sigmoid function devices <NUM> and <NUM>, each of which applies a number between <NUM> and <NUM> to components from cell state h(t-<NUM>) and input vector x(t). GRU cell <NUM> also comprises tanh device <NUM> to apply a hyperbolic tangent function to an input vector, multiplier devices <NUM>, <NUM>, and <NUM> to multiply two vectors together, addition device <NUM> to add two vectors together, and complementary device <NUM> to subtract an input from <NUM> to generate an output.

<FIG> depicts GRU cell <NUM>, which is an example of an implementation of GRU cell <NUM>. For the reader's convenience, the same numbering from <FIG> and GRU cell <NUM> is used in <FIG> and GRU cell <NUM>. As can be seen in <FIG>, sigmoid function devices <NUM> and <NUM>, and tanh device <NUM> each comprise multiple VMM arrays <NUM>. Thus, it can be seen that VMM arrays are of particular use in GRU cells used in certain neural network systems.

It can be further appreciated that GRU systems will typically comprise multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation circuit block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. The embodiments described below therefore attempt to minimize the circuitry required outside of the VMM arrays themselves.

<FIG> depicts VMM system <NUM>. VMM system <NUM> comprises VMM array <NUM>, low voltage row decoder <NUM>, high voltage row decoder <NUM>, reference cell low voltage column decoder <NUM> (shown for the reference array in the column direction, meaning providing input to output conversion in the row direction), bit line PE driver <NUM>, bit line multiplexor <NUM>, activation function circuit and summer <NUM>, control logic <NUM>, and analog bias circuit <NUM>.

Low voltage row decoder <NUM> provides a bias voltage for read and program operations and provides a decoding signal for high voltage row decoder <NUM>. High voltage row decoder <NUM> provides a high voltage bias signal for program and erase operations. Bit line PE driver <NUM> provides controlling function for bit line in program, verify, and erase. Bias circuit <NUM> is a shared bias block that provides the multiple voltages needed for the various program, erase, program verify, and read operations.

VMM system <NUM> further comprises redundancy array <NUM> and/or redundancy array <NUM>. Redundancy arrays <NUM> and <NUM> each provide array redundancy for replacing a defective portion in array <NUM>, in accordance with the redundancy embodiments described in greater detail below.

VMM system <NUM> further comprises NVR (non-volatile register, aka info sector) sectors <NUM>, which are array sectors used to store user info, device ID, password, security key, trimbits, configuration bits, manufacturing info, etc..

VMM system <NUM> optionally comprises reference sector <NUM> and/or reference system <NUM>. Reference system <NUM> comprises reference array <NUM>, reference array low voltage row decoder <NUM>, reference array high voltage row decoder <NUM>, and reference array low voltage column decoder <NUM>. The reference system can be shared across multiple VMM systems.

Reference array low voltage row decoder <NUM> provides a bias voltage for read and programming operations involving reference array <NUM> and also provides a decoding signal for reference array high voltage row decoder <NUM>. Reference array high voltage row decoder <NUM> provides a high voltage bias for program and operations involving reference array <NUM>. Reference array low voltage column decoder <NUM> provides a decoding function for reference array <NUM>. Reference array <NUM> is such as to provide reference target for program verify or cell margining (searching for marginal cells).

<FIG> depicts prior art memory system <NUM> that provides redundancy for rows containing one or more faulty memory cells during program, erase, or read operations. Memory system <NUM> comprises address comparator <NUM>, logic circuit <NUM>, array <NUM>, redundancy array <NUM>, row decoder <NUM>, and redundancy row decoder <NUM>.

During a testing or configuration phase, each row of memory cells in array <NUM> is tested and verified. Any memory cells deemed to be faulty are identified, and the address for each row that contains one or more faulty memory cells is stored in non-volatile memory (not shown). Thereafter, during operation of memory system <NUM>, each address <NUM> for a read or write operation is compared by address comparator <NUM> against each address in the set of stored addresses corresponding to rows containing one or more faulty memory cells.

If a match is found by address comparator <NUM> with any of the stored addresses, enable signal <NUM> is asserted, which signifies that the received address is for a faulty row. Enable signal <NUM> is received by redundant array row decoder <NUM>, which then selects a row that has been assigned to the row containing the faulty memory cell. Thus, the program, erase, or read operation is directed to the redundant row instead of the row containing the faulty memory cell.

If a match is not found by address comparator <NUM>, then enable signal <NUM> is de-asserted, and row decoder <NUM> is enabled by the output of logic circuit <NUM> (here shown as an inverter). In this situation, the received address <NUM> is used to access a row in array <NUM> for the operation.

By design, only one of the assigned redundant rows can be asserted at any given time. This prior art system therefore could not be used to perform a neural read operation, where all non-faulty rows and assigned redundant rows are asserted.

<FIG> depicts an embodiment of an improved memory system. Memory system <NUM> provides redundancy for rows containing one or more bad memory cells. Unlike memory system <NUM>, memory system <NUM> is able to assert all assigned redundant rows during a neural read operation, and it also can perform a program, erase, or read operation as in memory system <NUM>. Memory system <NUM> contains the same components as memory system <NUM> except that row decoder and redundancy latch block <NUM> is used instead of row decoder <NUM>. Row decoder and redundancy latch block <NUM> contains circuitry that enables all assigned redundant rows to be asserted during a neural read operation.

<FIG> depicts further detail regarding an embodiment of row decoder and redundancy latch block <NUM>, here shown as row decoder and redundancy latch block <NUM>. Memory system <NUM> comprises row decoder and redundancy latch block <NUM>, array <NUM>, redundancy array <NUM>, and high voltage decoder <NUM>. Row decoder and redundancy latch block <NUM> comprises numerous instances of sub-block <NUM>, where each instance of sub-block <NUM> is coupled to a pair of word lines in array <NUM> (here, word lines <NUM> and <NUM>). Thus, in this embodiment, sub-block <NUM> and similar sub-blocks each are coupled to a sector of memory in array <NUM>. In an alternative embodiment, each sub-clock can be coupled to more than two rows.

Row decoder and redundancy latch block <NUM> further comprises redundancy sub-block <NUM> coupled to a pair of word lines in redundancy array <NUM> (here, word lines <NUM> and <NUM>). Additional redundancy sub-blocks similar to redundancy sub-block <NUM> can be included in row decoder and redundancy latch block <NUM>.

Sub-block <NUM> comprises NAND gates <NUM> and <NUM>, inverters <NUM> and <NUM>, NAND gates <NUM> and <NUM>, inverters <NUM> and <NUM>, and latch <NUM>. Latch <NUM> is programmed (or loaded with configuration data at power-up or in response to a redundancy load command) during a testing or configuration phase. If word lines <NUM> or <NUM> are coupled to a row containing one or more faulty memory cells, then a "<NUM>" will be programmed into latch <NUM>. Otherwise, latch <NUM> will store a "<NUM>". During normal operation, when NAND gates <NUM> or <NUM> receive an address corresponding to word lines <NUM> or <NUM>, respectively, latch <NUM> will cause that word line to be de-asserted instead of asserted. Thus, the word line containing the faulty memory cell will not be selected.

Redundancy sub-block <NUM> contains similar components as sub-block <NUM>. Here, latch <NUM> is programmed during a testing or configuration phase. If word lines <NUM> or <NUM> are to be used, then latch <NUM> is programmed with a "<NUM>". Otherwise, latch <NUM> is programmed with a "<NUM>". During normal operation, when the receiving NAND gate receives an address corresponding to word lines <NUM> or <NUM>, latch <NUM> will cause that word line to be asserted. Thus, the word line containing the redundant memory cells will be selected. Notably, multiple redundant rows can be selected at any given time (such as during a neural read operation) by configuring latches such as latch <NUM> with a "<NUM>".

<FIG> depicts further detail regarding another embodiment of row decoder and redundancy latch block <NUM>, here shown as row decoder and redundancy latch block <NUM>. Memory system <NUM> comprises row decoder and redundancy latch block <NUM>, array <NUM>, redundancy array <NUM>, and high voltage decoder <NUM>. Row decoder and redundancy latch block <NUM> contains numerous instances of sub-block <NUM>, where each instance of sub-block <NUM> is coupled to a word line in array <NUM> (here, word line <NUM>). Thus, in this embodiment, sub-block <NUM> and similar sub-blocks each are coupled to a sector of memory in array <NUM>.

Row decoder and redundancy latch block <NUM> further comprises redundancy block <NUM> coupled to a redundant word line in redundancy array <NUM> (here, word line <NUM>).

Sub-block <NUM> comprises NAND gate <NUM>, inverter <NUM>, latch <NUM>, and switches <NUM> and <NUM>. Here, redundancy latch <NUM> is programmed during a configuration stage of memory system <NUM>. If latch <NUM> contains a "<NUM>", then the corresponding row coupled to word line <NUM> in array <NUM> is not faulty. During normal operation, switch <NUM> will be closed and switch <NUM> will be open, and word line <NUM> in array <NUM> will be accessed when the appropriate address is received. If latch <NUM> contains a "<NUM>", then the corresponding row in array <NUM> is faulty. During normal operation, switch <NUM> will be open and switch <NUM> will be closed, and word line <NUM> in array <NUM> will not be accessed when the appropriate address is received. Instead, redundant word line <NUM> in array <NUM> will be accessed through a vertical line <NUM>.

<FIG> depicts another embodiment of the inventive concepts. Memory system <NUM> comprises column decoder and redundancy latch block <NUM>, array <NUM>, and redundancy array <NUM>. Column decoder and redundancy latch block <NUM> contains numerous instances of sub-block <NUM>, where each instance of sub-block <NUM> is selectively coupled to a bit line or a group of bitlines (here, bit line <NUM>) in array <NUM>. Sub-block <NUM> comprises latch <NUM>, switch <NUM>, and switch <NUM>.

Latch <NUM> is programmed during a testing or configuration stage of memory system <NUM>. If latch <NUM> contains a "<NUM>", then the corresponding column coupled to bit line <NUM> is not faulty. During normal operation, switch <NUM> will be closed and switch <NUM> will be open, and bit line <NUM> will be accessed when the appropriate address is received. If latch <NUM> contains a "<NUM>", then the corresponding column in array <NUM> is faulty. During normal operation, switch <NUM> will be open and switch <NUM> will be closed, and bit line <NUM> in array <NUM> will not be accessed when the appropriate address is received. Instead, redundant bit line <NUM> in redundancy array <NUM> will be accessed through a horizontal line <NUM>.

<FIG> depicts program, program verify, and erase method <NUM>. The process starts (step <NUM>). A program, program verify, or erase command is received (step <NUM>). The received address is compared against the addresses for known bad rows or columns in a memory array (step <NUM>).

If a match is found (step <NUM>), that means a bad address exists. The system will disable the bad address (step <NUM>) and enable a corresponding redundant address (step <NUM>). The program, program verify, or erase command is then executed using the redundant address (step <NUM>). The process is then complete (step <NUM>).

If a match is not found (step <NUM>), the received address is enabled (step <NUM>). The program, program verify, or erase command is then executed using the received address (step <NUM>). The process is then complete (step <NUM>).

<FIG> depicts an embodiment for neural read process <NUM>. The process starts (step <NUM>). Redundancy latches are loaded or configured with redundancy information (step <NUM>). A neural read operation occurs, whereby the entire array and redundancy array are enabled except for the bad rows or columns (step <NUM>). The process is them complete (step <NUM>).

<FIG> depicts decoding circuitry <NUM> that is suitable for use with arrays containing memory cells of the type shown in <FIG>. Decoding circuitry <NUM> comprises word line decoder <NUM>, high voltage supply <NUM>, and source line decoder <NUM>. Word line decoder <NUM> comprises PMOS transistor <NUM> and NMOS transistor <NUM>, configured as shown. Source line decoder <NUM> comprises NMOS transistors <NUM>, <NUM>, and <NUM>, configured as shown. High voltage supply <NUM> comprises high voltage logic supply <NUM>.

<FIG> depicts decoding circuitry <NUM> that is suitable for use with arrays containing memory cells of the type shown in <FIG>. Decoding circuitry <NUM> comprises erase gate line decoder <NUM>, control gate decoder <NUM>, source line decoder <NUM>, and high voltage supply <NUM>. Erase gate decoder <NUM> comprises PMOS transistor <NUM> and NMOS transistor <NUM>, configured as shown. Control gate decoder <NUM> comprises PMOS transistor <NUM> and NMOS transistor <NUM>. Source line decoder <NUM> comprises NMOS transistors <NUM>, <NUM>, and <NUM>, configured as shown. High voltage supply <NUM> comprises high voltage logic supply <NUM>.

Claim 1:
A method (<NUM>) of performing a neural read operation in a memory system comprising a memory array and a redundant memory array, the method comprising:
loading data into one or more redundancy latches (<NUM>);
disabling a plurality of bad columns of memory cells in the memory array in response to the one or more latches, wherein another plurality of columns of memory cells in the memory array are non-disabled (<NUM>);
enabling a plurality of columns of memory cells in the redundant memory array (<NUM>);
performing a concurrent read operation of all memory cells in the non-disabled columns in the memory array and all memory cells in the enabled columns in the redundant memory array (<NUM>).