Patent Description:
Modern high-speed integrated circuits (ICs) have complex architectures, with millions of components such as transistors that must operate in concert to transmit data at multi-gigabit data rates required by modern communication networks. One of the critical steps of manufacturing such devices is the testing and calibration of the high-speed devices to ensure the devices do not fail at a later point in time (after integration into a product). One issue with testing and calibration of such high-speed devices stems from the modern design process, in which different components of the device are designed by different companies as "off the shelf" components. To this end, automatic test equipment (ATE) can be implemented by the device engineers to efficiently test high-speed designs at the chip and wafer level. Generally, an ATE system includes one or more computer-controlled equipment or modules that interface with the device under test (DUT) to perform stress testing and analyze individual components with minimal human interaction. Current ATE systems that are configured for electronic or semiconductor devices are not configured to provide rapid testing and calibration of some modern hybrid high-speed devices, such as optical transceivers that process both electricity and light to achieve higher data rates.

<CIT> relates to an optical-electrical device that can implement a feedback-based control loop for temperature of the device during component calibration.

<CIT> relates to an electro-optical circuitry board for contacting photonic integrated circuits.

<CIT> relates to an optoelectronic-device wafer probe and method therefor.

<CIT> relates to a probe for a photonic integrated circuit die with a related test assembly and method.

<CIT> relates to a probe module for testing chips with electrical and optical input/output interconnects, methods of use, and methods of fabrication.

The following description includes discussion of figures having illustrations given by way of example of implementations of embodiments of the disclosure. The drawings should be understood by way of example, and not by way of limitation. As used herein, references to one or more "embodiments" are to be understood as describing a particular feature, structure, or characteristic included in at least one implementation of the inventive subject matter. Thus, phrases such as "in one embodiment" or "in an alternate embodiment" appearing herein describe various embodiments and implementations of the inventive subject matter, and do not necessarily all refer to the same embodiment. However, they are also not necessarily mutually exclusive. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure ("FIG. ") number in which that element or act is first introduced.

Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the disclosure is provided below, followed by a more detailed description with reference to the drawings.

In general, well-known instruction instances, structures, and techniques are not necessarily shown in detail.

Modern ATE systems are not configured to rapidly test, validate, and calibrate modern hybrid high-speed devices, such as optical transceivers, which include both complex electrical and optical modules. To this end, a hybrid optical-electrical ATE system can be implemented that uses one or more electrical interfaces to interface with electrical apparatuses of the ATE system and one or more optical interfaces (e.g., fibers, lens, gratings) to interface with optical components of the ATE system. In some example embodiments, the hybrid optical-electrical ATE system is implemented by augmenting an electrical ATE system (e.g., an available off-the-shelf electrical ATE system) with dual interface optical assembly that couples light from optical test devices (e.g., light sources, optical analysis devices) to the device under test via a handler assembly that actuates the optical interfaces into position via a passive alignment process. In some example embodiments, the dual interfaces include a load board optical interface that couples light to the handler assembly and an optical device interface that couples light from the handler assembly to the optical-electrical device under test. In some example embodiments, the handler assembly includes an optical connector (e.g., fiber) to couple to the two interfaces such that when aligned light can be provided to and received from the device under test. In some example embodiments, the device under test is placed in a socket within a load board mount or docking plate having alignment features that interlock with corresponding alignment features on the mount assembly. To passively align the optical interfaces (e.g., without active actuators or electrical/optical feedback based alignment), the handler assembly can move the mount assembly to interlock the alignment features thereby aligning the two optical interfaces for simultaneous electrical and optical ATE testing.

<FIG> shows an optical and electrical testing system <NUM> for implementing simultaneous optical and electrical testing of photonic devices, according to some example embodiments. As illustrated, a handler <NUM> (e.g., IC handler, chip hander) is a robotic system that can precisely move a DUT <NUM> into position for testing and calibration. A workpress assembly <NUM> is attached to the handler <NUM> to move the DUT <NUM> to the test socket <NUM>. The test socket <NUM> is further positioned on an optical test assembly <NUM>, which provides optical testing of the DUT <NUM> using one or more optical devices modules (e.g., an optical spectrum analyzer) and an electrical ATE <NUM>, which provides electrical automated testing using one or more electrical analyzer modules. The DUT <NUM> is electrically connected via electrical connections <NUM> (e.g., high-speed test socket <NUM>) to the optical test assembly and the ATE <NUM>. Furthermore, the DUT <NUM> can interface optically with the optical test assembly using one or more optical connections <NUM>, including the two interfaces, according to some example embodiments. For example, the optical connections <NUM> can be implemented as optical paths that extend from the optical test assembly <NUM> into the workpress assembly <NUM>, and are turned back towards the topside of the DUT <NUM> (e.g., which can be a top side, or "bottom side" in a flip chip configuration where the "top side" faces towards an interposer or host board). Further functional components and details of the optical test assembly are discussed in further detail below, with reference to <FIG> and <FIG>. Once aligned with the optical and electrical contacts of the optical and electrical testing system <NUM>, the DUT <NUM> can undergo simultaneous electrical and optical testing and calibration.

<FIG> is a block diagram illustrating an optical transceiver <NUM> for transmitting and receiving optical signals, according to some example embodiments. The optical transceiver <NUM> is an example optical-electrical device under test that can be tested using the optical and electrical testing system <NUM> of <FIG>. In the example illustrated in <FIG>, the optical transceiver <NUM> processes data from electrical devices, such as electrical hardware device <NUM>, converts the electrical data into optical data, and sends and receives the optical data with one or more optical devices, such as optical device <NUM>. For example, the electrical hardware device <NUM> can be a host board that "hosts" the optical transceiver <NUM> as a pluggable device that sends and receives data to an optical switch network; where, for example, optical device <NUM> can be other components of an optical switch network (e.g., external transmitter <NUM>). However, it is appreciated that the optical transceiver <NUM> can be implemented to interface with other types of electrical devices and optical devices. For instance, the optical transceiver <NUM> can be implemented as a single chip on a hybrid "motherboard" that uses an optical network (e.g., waveguides, fibers) as an optical bus to interconnect on-board electrical chips that process the data after it is converted from light into binary electrical data, according to some example embodiments.

In some example embodiments, the hardware device <NUM> includes an electrical interface for receiving and mating with an electrical interface of the optical transceiver <NUM>. The optical transceiver <NUM> may be a removable front-end module that may be physically received by and removed from hardware device <NUM> operating as a backend module within a communication system or device. The optical transceiver <NUM> and the hardware device <NUM>, for example, can be components of an optical communication device or system (e.g., a network device) such as a wavelength-division multiplexing (WDM) system or a parallel fiber system (e.g., parallel-single fiber (PSM)), according to some example embodiments.

The data transmitter <NUM> of the optical transceiver <NUM> can receive the electrical signals, which are then converted into optical signals via photonic integrated circuit <NUM> (PIC). The PIC <NUM> can then output the optical signals via optical links, such as fiber or waveguides that interface with the PIC <NUM>. The output light data can then be processed by other components (e.g., switches, endpoint servers, other embedded chips of on a single embedded system), via a network such as a wide area network (WAN), optical switch network, optical waveguide network in an embedded system, and others.

In receiver mode, the optical transceiver <NUM> can receive high data rate optical signals via one or more optical links to optical device <NUM>. The optical signals are converted by the PIC <NUM> from light into electrical signals for further processing by data receiver <NUM>, such as demodulating the data into a lower data rate for output to other devices, such as the electrical hardware device <NUM>. The modulation used by the optical transceiver <NUM> can include pulse amplitude modulation (e.g., <NUM>-level PAM, such as "PAM4"), quadrature phase-shift keying (QPSK), binary phase-shift keying (BPSK), polarization-multiplexed BPSK, M-ary quadrature amplitude modulation (M-QAM), and others.

<FIG> shows an example dual optical interface architecture <NUM> for hybrid optical-electrical ATE testing, according to some example embodiments. In the illustrated example, the handler <NUM> is an ATE device or chip handler that uses the workpress assembly <NUM> to align the optical interfaces for testing. The workpress assembly <NUM> includes a workpress body <NUM> (e.g., metal assembly), and a mount <NUM> that can be customized for different sorts of DUTs (e.g., Blade-Pak™, plastic mount that is customizable for different DUTs).

The DUT <NUM> is positioned on the load board <NUM> by the handler <NUM>. In some example embodiments, the DUT <NUM> can be placed in a socket <NUM> on a docking plate <NUM>. The docking plate <NUM> can include mounting features for handler-based device alignment, such as feature <NUM> which is congruent with feature <NUM> of the mount <NUM>. The features <NUM> and <NUM> are used for approximate or "coarse" alignment to place the dual interface ports near one another for further alignment, according to some example embodiments. In particular, for example, after aligning features <NUM> and <NUM> to place the DUT <NUM> near the mount <NUM>, the dual interfaces are optically aligned using optical alignment features with have integrated fine adjustment features, as discussed in further detail with reference to <FIG> below.

In the example of <FIG>, the optical connector interface comprises port 320A, which is optically coupled to port 320B (e.g., an optical port integrated in DUT <NUM>, a grating of DUT <NUM>); and the load board optical interface includes port 325A which is optically coupled to port 325B. Further, the port 320A and port 325A are optically coupled via a coupling, e.g., fiber <NUM>, to transmit and receive light to the optical receiving side of the DUT <NUM> (e.g., the top-side of DUT <NUM>, though it is appreciated that the DUT <NUM> can be implemented as a "flip-chip" configuration, where the side facing away from the load board <NUM> is referred to the back or bottom side, as is known in the art).

Light can be coupled to the mount <NUM> via fibers <NUM> connected to the port 325B that is fixed in position by the docking plate <NUM>. In some example embodiments, the load board <NUM> is an off-the-shelf load board for a given ATE system (e.g., ATE system of handler <NUM>), and a hole is created in the load board <NUM> through which the fibers <NUM> can pass through to connect to the port 325B.

The top-side of the load board <NUM> functions as a DUT test bench that supports the DUT <NUM> during testing. The top-side of the load board <NUM> can include electrical pathways to electrically connect the electrical circuits of the DUT <NUM> to one or more electrical test devices (e.g., test modules or line cards of the ATE <NUM>, <FIG>).

To physically align the optical device interface and the load board interface, the workpress assembly <NUM> positions the mount <NUM> on the docking plate <NUM> such that device mounting features (e.g., feature <NUM>, a hole) of the mount <NUM> align and interlock with the mounting features of the docking plate <NUM> (e.g., feature <NUM>, a post or extruded feature). To optically align the optical interfaces, optical alignment features which are physically smaller and more precise (higher tolerance) are used for passive optical alignment. Once the coarse alignment features and more precise optical features are aligned, the optical device interface and the load board optical interface are both passively optically aligned (e.g., the port 320A is passively aligned with port 320B and further the port 325A is passively aligned with 325B).

In some example embodiments, the optical device interface (e.g., comprising port 320A and port 320B) is implemented using one or more optical components (e.g., lens, grating, prism) to propagate light over the interface. For example, the port <NUM> can include a micro-lens array or grating that receives light from the fiber <NUM> and directs the light towards port 320B. Further, port 320B can include a grating that receives the light from the port <NUM> and couples the light into an optical port of the DUT <NUM> (e.g., couples light into a grating of the DUT <NUM> for modulation and receives modulated light from the grating of the DUT <NUM> for analysis).

Further, in some example embodiments, the load board interface (e.g., comprising port 325A and port 325B) is implemented using one or more optical components to propagate light over the interface. For example, the port <NUM> can include an optical connector lens that couples light from the fiber <NUM> and directs the light towards the port 325A, which can be implemented as a lens or grating to receive the light and couple it into the fiber <NUM>. In some example embodiments, the ports 320A, 320B, 325A, and 325B can be implemented using different optical devices, such as gratings, lenses, free space optics, butt-coupling optics to one another (e.g., placing terminating ends of fibers side-by-side to optically couple), as so forth.

In some example embodiments, the optical-electrical DUT <NUM> is a multi-channel device, comprising four different optical lanes for four different channels. For example, the optical-electrical DUT <NUM> can be a 400GBASE optical transceiver comprising four channels, where each of the channels manages <NUM> of optical data. In those example embodiments, the optical interconnects from optical test devices <NUM> to the DUT <NUM> are increased for each of the channels. For example, fiber <NUM> can include eight fibers, where four of the fibers transmit light generated by the light sources in the optical test devices <NUM> to the DUT for processing (e.g., modulation) and another four of the fibers are receive fibers for receiving light for each of the channels from DUT (e.g., receiving light modulated by optical modulators on the DUT <NUM>). Likewise, the fiber <NUM> and the ports 320A, 320B, 325A, and 325B each handle four channels (e.g., by having eight gratings, lens, or fibers; four for transmitting to the DUT and four for receiving light from the DUT).

After the optical interfaces of the DUT <NUM> are passively aligned (e.g., by aligning ports 325A (first mount assembly optical port) with port 325B (optical port of device), and 320A (second mount assembly optical port) with port 320B (load board optical port)), the DUT <NUM> can undergo simultaneous electrical and optical testing of DUT <NUM> to more accurately simulate the performance of the DUT <NUM> at operation time (e.g., in the field, after integration in a network device or product). For example, optical transceiver components of the DUT <NUM> can be tested via optical test devices <NUM> while electrical components used to control the optical components are tested and analyzed by electrical test devices <NUM> (e.g., a bit error rate tester, a parametric measurement unit, device power supply). In some example embodiments in which the DUT <NUM> is a multi-channel network device, each of the channels is tested separately, one at a time, where selection is performed via an optical switch. Further details of the switch and physical interconnection structures for the mount <NUM> and the docking plate <NUM> are discussed in "Multi-Lane Optical-Electrical Device Testing Using Automated Testing Equipment,".

<FIG> shows a detailed view <NUM> of the optical interface architecture, according to some example embodiments. In <FIG>, the device alignment features includes feature <NUM> of the docking plate <NUM> which is interlocked with feature <NUM>, which can be a hole in the mount <NUM>. For further optical alignment, an optical interconnect head <NUM> is attached to the mount <NUM> using one or more mechanical adjusters (e.g., screws) and a spring adjuster <NUM>. The optical interconnect head can receive the fiber <NUM> which is further connected to beam <NUM> (e.g., a plastic beam that is slide-able in the vertical, "Z" direction). In the example of <FIG>, the handler <NUM> (not depicted) moves the mount <NUM> until the feature <NUM> is inserted into feature <NUM> to complete approximate alignment. Next, further optical alignment is performed by guiding the mount <NUM> (e.g., via the handler <NUM>, or by hand) until the port 325A on the beam <NUM> couples to port 325B of the docking plate <NUM>. In some example embodiments, the beam <NUM> has receiver feature <NUM> that interlocks with the extruded feature <NUM> to optically couple the ports 325A and 325B (e.g., free space coupler, butt-couple, grating to lens coupling, etc.).

Further, the optical interconnect head <NUM> is actuated by the handler <NUM> (e.g., by an actuator, robotic arm) until a fine optical alignment feature <NUM> (e.g., grooved/interlocking alignment feature) snaps into a corresponding feature <NUM> on the DUT <NUM>. In some example embodiments, the DUT <NUM> does not include alignment features and instead a receptacle is placed on the DUT and the receptable includes the feature <NUM> into which the feature <NUM> interlocks. The features <NUM>, <NUM>, <NUM>, <NUM> are physically smaller to ensure precise passive optical coupling between the ports 320A, 320B, 325A, and 325B without performing active alignment (e.g., using a light source to optically align the ports). For instance, the features <NUM> and <NUM> can be fabricated to be on the same scale as the ports 320A and 320B (e.g., <NUM> wide) to ensure that once the features <NUM> and <NUM> interlocked, the ports 320A and 320B are precisely optically coupled. Further, the features <NUM> and <NUM> are fabricated on a same or similar scale as the ports 325A and 325B (e.g., <NUM>-<NUM> scale) to ensure that once the beam <NUM> interlocks with the docking plate <NUM> (via interconnection of features <NUM> and <NUM>), the ports 325A and 325B are also optically aligned and coupled without using active alignment.

In some example embodiments, the optical interconnect head <NUM> is configured as an optical blind mate-able connector that precisely snaps into place using the spring adjuster <NUM> providing tension in the vertical "Z" direction and X/Y positioning using the mechanical adjusters <NUM>, which can be screws to move the head <NUM> for X/Y alignment. For example, the head <NUM> floats in three dimensions (X, Y, and Z), and the adjusters <NUM> can be adjusted first to adjust the X and Y alignment, followed by lowering the mount <NUM> and the optical interconnected head <NUM> until tension provided by the spring adjuster <NUM> snaps the fine optical alignment features <NUM> and <NUM> into aligned and locking position. In some example embodiments, the head <NUM> floats in three dimensions on springs without the mechanical adjusters. For example, the adjusters <NUM> can be implemented as springs to provide tension in the X axis, Y axis or both. In these example embodiments, the head <NUM> snaps into passive alignment via the tension such that the fine alignment features interlock thereby passively aligning the optical device interface.

<FIG> displays an optical-electrical ATE interconnection architecture <NUM>, according to some example embodiments. The optical-electrical ATE interconnection architecture <NUM> is an example implementation of the optical test assembly <NUM> for optical testing and calibration of optical devices. At a high level, the ATE <NUM> interfaces with the optical-electrical DUT <NUM> and a bit error rate module <NUM> (e.g., an embedded BER tester), according to some example embodiments. Further, and in accordance with some example embodiments, the ATE <NUM> can interface and display data from a compact optical spectrum analyzer <NUM> (OSA) that interfaces electrically with the DUT <NUM> using a data interface (e.g., RS-<NUM>), and optically via one or more fibers and an optical switch <NUM>. In some example embodiments, the DUT <NUM> receives light one or more fibers coupled to a light source <NUM> which couples light into the receive port of the DUT <NUM>. The DUT <NUM> receives the light and generates modulated light using one or more modulators. The fibers extending from the light source <NUM> to the DUT <NUM> and the fibers extending from the DUT <NUM> to the optical switch <NUM> can be implemented as the optical connections <NUM> coupled using the interfaces as discussed in <FIG>, according to some example embodiments. In some example embodiments, the optical switch <NUM> is operable to select one of the available plurality of fibers for output to the compact OSA <NUM>.

<FIG> shows a flow diagram of a method <NUM> for hybrid testing of an optical-electrical DUT, according to some example embodiments. At operation <NUM>, a device handler (e.g., handler <NUM>, chip handler) places the optical-electrical DUT on the hybrid testing platform, such the load board <NUM>. In some example embodiments, the optical-electrical DUT is placed directly on the load board and a socket comprising optical connectors is connected with the DUT to provide optical connectivity. In some example embodiments, the socket having the load board connector is pre-attached to the load board and the optical-electrical DUT is placed on the socket, as in <FIG>. In some example embodiments, the optical-electrical DUT is placed on the load board, and a socket is attached (e.g., epoxied) to the optical-electrical DUT to interlock the mount assembly onto the docking plate via interlocking physical features (e.g., features <NUM>, <NUM>, <NUM>, and <NUM>).

At operation <NUM>, the mount and docking plate are approximately aligned using one or more coarse alignment features. For example, a feature <NUM> is interlocked with a feature <NUM> or hole in the mount <NUM>. At operation <NUM>, the load board optical interface is aligned to couple light from the load board (e.g., from docking plate <NUM>, port 325B, fiber <NUM>) to the handler assembly (e.g., couple with port 325A of the mount <NUM> via interlocking feature <NUM> of beam <NUM> with feature <NUM> of the docking plate <NUM>).

At operation <NUM>, the optical device interface is aligned to couple light to the optical-electrical DUT. For example, the optical device interface is aligned to couple light from the port 320A (e.g., lens array) to port 320B (e.g., grating) which is coupled to an input/output port of the optical-electrical DUT.

In some example embodiments, operations <NUM> and <NUM> are performed simultaneously by moving the mount <NUM> (e.g., via the handler <NUM> or by hand) until both interfaces snap or interlock passively. For example, in order to align the interfaces of the ATE system for hybrid test, the ATE handler can implement a mount assembly having physical features (e.g., posts, grooves) that interlock with congruent interlocking features on the docking plate. In those example embodiments, by aligning the mount to the docking plate using the interlocking physical features, both the load board optical interface and the optical device interface are passively aligned, thereby completing an optical path from optical components of the ATE system (e.g., optical test devices <NUM>) and the optical-electrical DUT without requiring active light based alignment.

At operation <NUM>, the optical-electrical DUT undergoes electrical testing to test and calibrate components of the optical-electrical DUT (e.g., using electrical test device <NUM>, one or more line-cards of an electrical ATE system). At operation <NUM>, the optical-electrical DUT undergoes optical testing to test and calibrate optical components of the optical-electrical DUT (e.g., using optical test devices <NUM>, an OSA). In some example embodiments, the optical-electrical DUT undergoes optical testing using light internally generated by the DUT. For example, the DUT can include one or more integrated light sources (e.g., lasers) that generate light that is modulated and output to the testing device via the optical connections. In some example embodiments, the optical-electrical DUT undergoes testing using one or more external light sources (e.g., light from light source <NUM>, <FIG>), which can be input, modulated and output via the optical connections <NUM>, as discussed above.

In some example embodiments, operations <NUM> and <NUM> are performed simultaneously to better simulate the optical-electrical DUT operating environment. For example, with reference to <FIG>, after the optical-electrical DUT <NUM> is electrically connected to the electrical test device <NUM> via load board <NUM> and optically connected to optical test device <NUM> (e.g., via the optical interfaces), each lane of the optical-electrical DUT <NUM> can be tested to calibrate electrical components (e.g., transmitter circuit, receiver circuit), and optical components (e.g., optical modulator, heaters) at the same time.

<FIG> is an illustration of an optical-electrical device <NUM> (e.g., optical-electrical DUT <NUM>, optical transceiver <NUM>) including one or more optical devices, according to an embodiment of the disclosure. In this embodiment, the optical-electrical device <NUM> is a multi-structure chip package that includes a printed circuit board (PCB) substrate <NUM>, organic substrate <NUM>, application specific integrated circuit <NUM> (ASIC), and photonic integrated circuit <NUM> (PIC). In this embodiment, the PIC <NUM> may include one or more optical structures described above (e.g., PIC <NUM>).

In some example embodiments, the PIC <NUM> includes silicon on insulator (SOI) or silicon-based (e.g., silicon nitride (SiN)) devices, or may comprise devices formed from both silicon and a non-silicon material. Said non-silicon material (alternatively referred to as "heterogeneous material") may comprise one of III-V material, magneto-optic material, or crystal substrate material. III-V semiconductors have elements that are found in group III and group V of the periodic table (e.g., Indium Gallium Arsenide Phosphide (InGaAsP), Gallium Indium Arsenide Nitride (GainAsN)). The carrier dispersion effects of III-V-based materials may be significantly higher than in silicon-based materials, as electron speed in III-V semiconductors is much faster than that in silicon. In addition, III-V materials have a direct bandgap which enables efficient creation of light from electrical pumping. Thus, III-V semiconductor materials enable photonic operations with an increased efficiency over silicon for both generating light and modulating the refractive index of light. Thus, III-V semiconductor materials enable photonic operation with an increased efficiency at generating light from electricity and converting light back into electricity.

The low optical loss and high quality oxides of silicon are thus combined with the electro-optic efficiency of III-V semiconductors in the heterogeneous optical devices described below; in embodiments of the disclosure, said heterogeneous devices utilize low loss heterogeneous optical waveguide transitions between the devices' heterogeneous and silicon-only waveguides.

Magneto-optic materials allow heterogeneous PICs to operate based on the magneto-optic (MO) effect. Such devices may utilize the Faraday Effect, in which the magnetic field associated with an electrical signal modulates an optical beam, offering high bandwidth modulation, and rotates the electric field of the optical mode enabling optical isolators. Said magneto-optic materials may comprise, for example, materials such as iron, cobalt, or yttrium iron garnet (YIG). Further, in some example embodiments, crystal substrate materials provide heterogeneous PICs with a high electro-mechanical coupling, linear electro optic coefficient, low transmission loss, and stable physical and chemical properties. Said crystal substrate materials may comprise, for example, lithium niobate (LiNbO3) or lithium tantalate (LiTaO3). In the example illustrated, the PIC <NUM> exchanges light with fiber <NUM> via prism <NUM>; said prism <NUM> is a misalignment-tolerant device used to couple an optical mode to one or more single-mode optical fibers (e.g., to transmit light to and from an optical network), according to some example embodiments.

In some example embodiments, the optical devices of PIC <NUM> are controlled, at least in part, by control circuitry included in ASIC <NUM>. Both ASIC <NUM> and PIC <NUM> are shown to be disposed on copper pillars <NUM>, which are used for communicatively coupling the ICs via organic substrate <NUM>. PCB <NUM> is coupled to organic substrate <NUM> via ball grid array (BGA) interconnect <NUM>, and may be used to interconnect the organic substrate <NUM> (and thus, ASIC <NUM> and PIC <NUM>) to other components of optical-electrical device <NUM> not shown, such as interconnection modules, power supplies, and so forth.

Claim 1:
A method for testing an optical-electrical device under test, DUT, (<NUM>) using an automated testing equipment, ATE, system (<NUM>), the method comprising:
placing the optical-electrical DUT in a socket (<NUM>) within a docking plate (<NUM>);
passively aligning a load board optical interface between a load board (<NUM>) of the ATE system and a mount assembly of the ATE system, a top-side of the load board supporting the optical-electrical DUT such that an electrical interface side of the optical-electrical DUT interfaces with electrical paths on the top-side of the load board to communicate one or more electrical signals from the optical-electrical DUT, the load board optical interface passively aligned by passively aligning a load board optical port (325B) of the load board with a first mount assembly optical port (325A) of the mount assembly using a receiver feature (<NUM>) of the mount assembly that interlocks with an extruded feature (<NUM>) of the load board;
passively aligning an optical device interface between the mount assembly and the optical-electrical DUT to communicate one or more optical signals generated by the optical-electrical DUT, the optical device interface passively aligned by passively aligning a second mount assembly optical port (320A) of the mount assembly with an optical port (320B) of the optical-electrical DUT that is on an optical interface side of the optical-electrical DUT that is opposite of the electrical interface side that faces the load board using physical features (<NUM>) of the mount assembly that interlock with congruent interlocking features (<NUM>) on the docking plate; and
analyzing the one or more electrical signals while analyzing the one or more optical signals from the optical-electrical DUT using the ATE system, the one or more electrical signals analyzed by an electrical test device (<NUM>) of the ATE system that receives the one or more electrical signals from the electrical paths of the load board, the one or more optical signals analyzed by an optical test device (<NUM>) of the ATE system that receives the one or more optical signals via propagation through the optical device interface and the load board optical interface.