Patent Description:
As display devices have become larger, the non-display area that surrounds the display area has been reduced in size. While this creates a display device with a modem look, there is less available space for disposing the driving circuits and wirings for driving the pixels of the display device, which have traditionally been disposed along the non-display area.

<CIT>, <CIT>, <CIT> and <CIT> disclose display devices.

The invention is about a display device as in claim <NUM>. Further embodiments of the invention are disclosed in the dependent claims. A display device includes a substrate having a display area, a peripheral area at least partially surrounding the display area, and a pad area within the peripheral area. A plurality of data lines is disposed within the display area. A plurality of connection wirings is disposed within the display area, connected to the plurality of data lines, and configured to transmit a data signal supplied from the pad area to the plurality of data lines. The display area includes a first area in which the plurality of connection wirings extend in a first direction, and a second area in which the plurality of connection wirings extend in a second direction that is perpendicular to the first direction.

A more complete appreciation of the present disclosure and many of the attendant aspects thereof will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings in which:.

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like elements throughout the specification and the drawings. In this regard, the present embodiments may have different forms than what is set forth herein.

It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

It will be further understood that the terms "comprises" and/or "comprising" used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components. In contrast, the phrase "consisting of" precludes the addition of unlisted features or components.

It will be understood that when a layer, region, or component is referred to as being "formed on," another layer, region, or component, it may be directly or indirectly formed on the other layer, region, or component. For example, for example, intervening layers, regions, or components may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation.

Hereinafter, embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings. Those components that are the same or are in correspondence are rendered the same reference numeral regardless of the figure number.

<FIG> is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

Referring to <FIG>, a display device <NUM>, according to an exemplary embodiment of the present disclosure, includes a display area AA in which an image is displayed, and a peripheral area PA outside of, and at least partially surrounding, the display area AA. Thus, the substrate <NUM> has the display area AA and the peripheral area PA.

A plurality of pixels PX and wirings for applying an electrical signal to the plurality of pixels PX may be disposed in the display area AA.

Each of the plurality of pixels PX may include a light-emitting device and a circuit portion for driving the light-emitting device. According to an exemplary embodiment of the present disclosure, the light-emitting device may be an organic light-emitting device, and the circuit portion may include a plurality of transistors and a capacitor, in addition to various other supporting elements.

The wirings for applying an electrical signal to the plurality of pixels PX may include a plurality of scan lines SL and a plurality of data lines DL. According to an exemplary embodiment of the present disclosure, the plurality of scan lines SL may be arranged in a plurality of rows and may transmit a scan signal to the pixels PX, and the plurality of data lines DL may be arranged in a plurality of columns and may transmit a data signal to the pixels PX. The plurality of pixels PX may be disposed in a portion where the plurality of scan lines SL and the plurality of data lines DL intersect each other.

Connection wirings <NUM> for transmitting the electrical signal supplied from a pad area PADA to the wirings connected to the pixels PX are disposed in the display area AA. According to the invention as claimed, the connection wirings <NUM> are connected to the data lines DL and transmit the data signal supplied from the pad area PADA to the data lines DL.

Meanwhile, because a length of one side of the display area AA adjacent to the pad area PADA (e.g. the vertical sides, as shown) is greater than a length of the pad area PADA (e.g. the bottom side, as shown), the connection wirings <NUM> have to be widely spread to correspond to one side of the display area AA at a position corresponding to the pad area PADA. To this end, the connection wirings <NUM> may extend in a first direction X, may be bent in a direction parallel to a second direction Y, perpendicular to the first direction X, may extend towards edges of the display area AA, and then may be bent in a direction parallel to the first direction X and may extend in the first direction X, as shown in <FIG>. Thus, the data signal supplied from the center of one side of the display area AA may be transmitted to the data lines DL from an end of one side of the display area AA. Thus, the area of the peripheral area PA may be reduced compared to fan-out wirings according to the related art in the peripheral area PA, so that a dead space of the display device <NUM> may be reduced.

Meanwhile, the display area AA are divided into a plurality of areas according to an extension direction of the connection wirings <NUM>. According to the invention as claimed, the display area AA includes a first area S1 in which the connection wirings <NUM> extend in the direction parallel to the first direction X, a second area S2 in which the connection wirings <NUM> extend in the direction parallel to the second direction Y, and a third area S3 that is the remaining area of the display area AA excluding the first area S1 and the second area S2. The third area S3 may be an area in which the connection wirings <NUM> are not disposed.

There may be a plurality of first areas S1 and a plurality of second areas S2, and each of the plurality of first areas S1 and the plurality of second areas S2 may have a substantially triangular shape. For example, to prevent a short-circuit between the connection wirings <NUM>, an extension length of the connection wirings <NUM> that extend in the first direction X from the middle portion of the central, first area S1 may be greater than the extension length of the connection wirings <NUM> that extend in the first direction X from edges of the first area S1. Thus, the entire shape of the first area S1 may be a triangular shape. Also, because the connection wirings <NUM> may be bent in the direction parallel to the second direction Y and may extend from the central, first area, the shapes of the second areas S2 at both sides of the central, first area S1 may be inverted triangular shapes, and the connection wirings <NUM> may be bent in the -X-direction and may extend from the second areas S2. Thus, the first areas S1 outside the second areas S2 may have triangular shapes.

In the first areas S1 and the second areas S2, extension directions of the connection wirings <NUM> are different from each other. As the connection wirings <NUM> may reflect light, reflection characteristics in the first areas S1 and the second areas S2 may be different from each other and this difference may be noticeable to a user who is viewing the display device <NUM>. As a result, the divisions within the display area AA where the first areas S1 and the second areas S2 meet may be recognized by a user. To reduce or prevent this phenomenon, the connection wirings <NUM> include a plurality of branches that protrude in a direction perpendicular to the extension direction of the connection wirings <NUM>. Thus, the first areas S1 and the second areas S2 may include the same or similar patterns. Thus, a difference in the reflection characteristics between the first areas S1 and the second areas S2 may be reduced. This will be described later with reference to <FIG>.

The peripheral area PA at least partially surrounds the display area AA. The peripheral area PA that is an area in which the pixels P are not disposed, includes the pad area PADA, to which a variety of electronic devices or printed circuit boards (PCBs) are electrically attached. A voltage line for supplying power for driving the light-emitting device may also be disposed in the peripheral area PA.

<FIG> may be understood as a plan view illustrating the substrate <NUM> during a manufacturing process of the display device <NUM>. In an electronic device, such as a finished product display device <NUM> or a smartphone including the display device <NUM>, a portion of the substrate <NUM> may be bent back or behind the display area AA thereof so as to minimize the perceivable area of the peripheral area PA.

For example, as shown in <FIG>, the peripheral area PA may include a bending area BA, and the bending area BA may be defined between the pad area PADA and the display area AA. In this case, the substrate <NUM> may be bent in the bending area BA so that at least some of the pad area PADA may at least partially overlap the display area AA. In this case, the bending direction of the pad area PADA is set so that the pad area PADA may be behind the display area AA. Thus, to the user, the display area AA may appear to make up most of the display device <NUM>. To this end, the substrate <NUM> may include various flexible/bendable materials.

<FIG> is a plan view illustrating an example of a portion A of <FIG>, and <FIG> is a plan view illustrating an example of a portion B of <FIG>. Hereinafter, exemplary embodiments of the present disclosure will be described with reference to <FIG>.

Referring to <FIG>, each of the connection wirings <NUM> includes a plurality of branches <NUM> (e.g. <FIG>) and <NUM> (e.g. <FIG>) that protrude in a direction perpendicular to a lengthwise direction of the connection wirings <NUM>. Hereinafter, for convenience of description, a display area will be divided into a first area S1 and a second area S2.

As shown in <FIG>, in the first area S1, the connection wirings <NUM> may extend in the direction parallel to the first direction X, and the first area S1 may include first branches <NUM> that protrude in the second direction Y.

The first branches <NUM> protrude symmetrically from the connection wirings. For example, the first branches <NUM> protrude from the connection wirings that extend in the first direction X in a both-side direction perpendicular to the lengthwise direction of the connection wirings <NUM>. Also, a pair of first branches <NUM> that protrude from two adjacent connection wirings <NUM> among the connection wirings <NUM> arranged in parallel in the first area S1 towards each other may be disposed in the same line. Thus, as shown in <FIG>, in the first area S1, two adjacent connection wirings <NUM> and the first branches <NUM> that protrude towards each other may divide first unit patterns A1. However, to prevent a short-circuit between the connection wirings <NUM>, ends of the first branches <NUM> that extend from the two adjacent connection wirings <NUM> towards each other are spaced apart from each other.

Also, as shown in <FIG>, in the second area S2, the connection wirings <NUM> may extend in the direction parallel to the second direction Y, and the second area S2 may include second branches <NUM> that protrude in the first direction X.

The second branches <NUM> protrude from the connection wirings that extend in the second direction to be symmetrical to each other. Also, a pair of second branches <NUM> that protrude from two adjacent connection wirings <NUM> towards each other in the second area S2 may be disposed in the same line. Thus, as shown in <FIG>, in the second area S2, two adjacent connection wirings <NUM> and the second branches <NUM> that protrude from the two adjacent connection wirings <NUM> towards each other may divide second unit patterns A2. However, to prevent a short-circuit between the connection wirings <NUM>, ends of the second branches <NUM> that extend from the two adjacent connection wirings <NUM> towards each other are spaced apart from each other.

Thus, one first unit pattern A1 in the first area S1 and one second unit pattern A2 in the second area S2 may have similar shapes. For example, there is only a difference that, in the first unit patterns A1, a gap is formed between the first branches <NUM> that extend towards each other, and in the second unit patterns A2, a gap is formed between the second branches <NUM> that extend towards each other, and the first unit pattern A1 and the second unit pattern A2 may have the same areas, and a total length of the connection wirings <NUM> that surround the first unit pattern A1 and the first branches <NUM> may be the same as a total length of the connection wirings <NUM> that surround the second unit pattern A2 and the second branches <NUM>.

Thus, reflection characteristics of light in the first area S1 and the second area S2 are similar to each other. Thus, a phenomenon in which a display area is divided into the first area S1 and the second area S2, according to incidence angles of light and recognized, may be prevented or minimized.

A third area S3 may include first unit patterns A1 or/and second unit patterns A2. Thus, a phenomenon in which a viewer may be able to distinguish the third area S3 from the first area S1 and the second area S2 may be prevented. For example, because the third area S3 is in contact with the second area S2 having an inverted triangular shape and is continuous to the second area S2, when the third area S3 includes the second unit patterns A2, the phenomenon in which a viewer may be able to distinguish the third area S3 from the first area S1 and/or the second area S2 may be more effectively prevented.

When the third area S3 includes the first unit patterns A1 or/and the second unit patterns A2, the first unit patterns A1 and/or the second unit patterns A2 included in the third area S3 may be in floating states.

First and second dummy patterns <NUM> and <NUM> may be further disposed inside the first unit patterns A1 and the second unit patterns A2. The first and second dummy patterns <NUM> and <NUM> may be disposed between the two adjacent connection wirings <NUM> and disposed in the same layer as a layer in which the connection wirings <NUM> are disposed. In <FIG> and <FIG>, the first dummy patterns <NUM> and the second dummy patterns <NUM> are disposed inside the first unit patterns A1 and the second unit patterns A2, respectively. However, the present invention is not limited thereto, and dummy patterns having a variety of numbers and shapes may be used. The dummy patterns <NUM> and <NUM> may prevent signal interference between the circuit portion and the connection wirings <NUM> from occurring, and may secure a pattern density so that the device may be more easily manufactured.

<FIG> is a plan view illustrating another example of the portion A of <FIG>, and <FIG> is a plan view illustrating another example of the portion B of <FIG>. Hereinafter, this will be described with reference to <FIG>, <FIG>, and <FIG>.

Referring to <FIG>, <FIG>, and <FIG>, each of the connection wirings <NUM> includes a plurality of branches <NUM> and <NUM> that protrude in the direction perpendicular to the lengthwise direction of the connection wirings <NUM>. As shown in <FIG>, the connection wirings <NUM> that extend from the first area S1 in the first direction X, may include the first branches <NUM> that protrude in the second direction Y and as shown in <FIG>, the connection wirings <NUM> that extend from the second area S2 in the second direction Y may include the second branches <NUM> that protrude in the first direction X so that reflection characteristics of light in the first area S1 and the second area S2 may be similar to each other and a phenomenon in which the display area is visibly divided into the first area S1 and the second area S2 may be prevented or minimized. Thus, only differences between what is shown in <FIG> and <FIG> as compared the above description will be described and it is to be understood that to the extent that details have been omitted for certain elements, those elements may be at least similar to corresponding elements that have already been described. Also, for convenience of description, a display area will be divided into the first area S1 and the second area S2.

Referring to <FIG> and <FIG>, in the first area S1, a gap may be formed between the first branches <NUM> that extend from the two adjacent connection wirings <NUM> towards each other. In the second area S2, a gap may be formed between the second branches <NUM> that extend from the two adjacent connection wirings <NUM> towards each other. In this case, first cover patterns <NUM> that cover the gap between the first branches <NUM> may be further disposed in the first area S1, and second cover patterns <NUM> that cover the gap between the second branches <NUM> may be further disposed in the second area S2.

For example, the first cover patterns <NUM> may at least partially overlap ends of the first branches <NUM> that face each other, in the first direction X, i.e., in the same direction as the extension direction of the connection wirings <NUM> and may be apart from the ends of the first branches <NUM> that face each other, so as to prevent a short-circuit of the two adjacent connection wirings <NUM>. Also, the first cover pattern <NUM> may be connected to the first dummy patterns <NUM> or the second dummy patterns <NUM> so as to fix positions of the first cover patterns <NUM>. In <FIG>, based on the drawings, the first cover patterns <NUM> may be disposed at a lower position than the first branches <NUM> and may be connected to the first dummy patterns <NUM>. However, the present invention is not limited thereto, and the first cover patterns <NUM> may be disposed at an upper position than the first branches <NUM> and may be connected to the second dummy patterns <NUM> based on the drawings.

Similarly, as shown in <FIG>, the second cover patterns <NUM> may at least partially overlap ends of the second branches <NUM> in the second direction Y, i.e., in the same direction as an extension direction of the connection wirings <NUM> and may be spaced apart from the ends of the second branches <NUM> so as to prevent a short-circuit of the two adjacent connection wirings <NUM>. Also, the second cover patterns <NUM> may be connected to the first dummy patterns <NUM> or the second dummy patterns <NUM> so as to fix the positions of the second cover patterns <NUM>.

In this way, when the first cover patterns <NUM> that overlap the ends of the first branches <NUM> are further disposed in the first area S1 and the second cover patterns <NUM> that overlap the ends of the second branches <NUM> are further disposed in the second area A1, shapes of the patterns included in the first area S1 and the second area S2 may be more similar to each other. Thus, a phenomenon in which, when the position of the gap between the first branches <NUM> in the first area S1 and the position of the gap between the second branches <NUM> in the second area S2 are different from each other, reflectivities of incident lights at certain angles may be different from each other, may be prevented. Thus, a phenomenon in which a display area may be divided into the first area S1 and the second area S2 and recognized, may be more effectively prevented. The first cover patterns <NUM> and the second cover patterns <NUM> may be disposed in the same layer as the layer in which the connection wirings <NUM> are disposed.

<FIG> is a plan view illustrating another example of the portion A of <FIG>, and <FIG> is a plan view illustrating another example of the portion B. Hereinafter, this will be described with reference to <FIG>, <FIG>, and <FIG>.

Referring to <FIG>, <FIG>, and <FIG>, each of the connection wirings <NUM> includes a plurality of first and second branches <NUM> and <NUM> that protrude in the direction perpendicular to the lengthwise direction of the connection wirings <NUM>. Also, each of the connection wirings <NUM> may include a plurality of first and second slices <NUM> and <NUM> that are spaced apart from each other in the direction parallel to the extension direction of the connection wirings <NUM> and a plurality of bridges <NUM> and <NUM> that electrically connect the plurality of slices <NUM> and <NUM> to each other (e.g. bridges <NUM> connect slices <NUM> to slices <NUM> and bridges <NUM> connect slices <NUM> to slices <NUM>). In this case, the plurality of first and second branches <NUM> and <NUM> may protrude from the plurality of slices <NUM> and <NUM>. Hereinafter, for convenience of description, a display area will be divided into the first area S1 and the second area S2.

First, as shown in <FIG>, each of the connection wirings <NUM> that extend in the first direction X in the first area S1 may include the plurality of first slices <NUM> that are spaced apart from each other in the first direction X and a plurality of first bridges <NUM> that electrically connect the plurality of first slices <NUM>. The plurality of first bridges <NUM> may be disposed in a different layer from a layer in which the plurality of first slices <NUM> are disposed, and may be electrically connected to the first slices <NUM> via a contact hole C.

Also, as shown in <FIG>, each of the connection wirings <NUM> that extend in the second direction Y may include the plurality of second slices <NUM> in the second area S2, and the plurality of second slices <NUM> may be electrically connected to each other via the contact hole C using the plurality of second bridges <NUM>.

As shown in <FIG>, a pair of first branches <NUM> may protrude from each of the plurality of first slices <NUM> in opposite directions and may at least partially overlap ends of a pair of first branches <NUM> in which dummy bridges extend towards each other. The dummy bridges in the first area S1 may be the same as the second bridges <NUM>. However, the first bridges <NUM> may be electrically connected to the first slices <NUM> via the contact hole C, whereas the second bridges <NUM> might not be connected to the first branches <NUM> and may be in insulated states. To this end, an insulating layer may be disposed between ends of the second bridges <NUM> and the pair of first branches <NUM>. Thus, the connection wirings <NUM> that extend in the first direction X in the first area S1 may be prevented from being short circuited to each other via the first branches <NUM>.

Also, each of the plurality of second slices <NUM> may include the second branches <NUM> that protrude from the second slices <NUM> in the direction perpendicular to the second direction Y, and dummy bridges may be disposed at a position where they overlap ends of a pair of second branches <NUM> that extend towards each other. The first bridges <NUM> may be dummy bridges in the second area S2. The first bridges <NUM> that are dummy bridges might not be connected to the second branches <NUM> and may be in an insulated state. Thus, the connection wirings <NUM> that extend in the second direction Y may be prevented from being short circuited to each other via the second branches <NUM>.

For example, in the first area S1 and the second area S2, the first bridges <NUM> and the second bridges <NUM> are disposed at the same position. However, in the first area S1, only the first bridges <NUM> might be electrically connected to the first slices <NUM> via the contact hole C, and the second bridges <NUM> are dummy bridges. On the other hand, in the second area S2, only the second bridges <NUM> might be electrically connected to the second slices <NUM> via the contact hole C, and the first bridges <NUM> are dummy bridges. Thus, the first area S1 and the second area S2 include patterns having the same shapes. Thus, reflection characteristics in the first area S1 and the second area S2 may be the same, and accordingly, a phenomenon in which a display area is visibly divided into the first area S1 and the second area S2 may be prevented.

The first bridge <NUM> and the second bridge <NUM> may be disposed on the connection wirings <NUM>. The first bridge <NUM> and the second bridge <NUM> may be formed of a transparent material, such as an indium tin oxide (ITO) or an opaque material. According to an exemplary embodiment of the present disclosure, the first bridge <NUM> and the second bridge <NUM> may also be disposed under the connection wirings <NUM>. According to an exemplary embodiment of the present disclosure, the first bridge <NUM> and the second bridge <NUM> may be disposed in the same layer in which a source electrode and a drain electrode of a thin-film transistor (TFT) that will be described later are disposed, or in the same layer in which a gate electrode of the TFT is disposed.

A description of the third area S3 including the same patterns as those of the first area S1 or the second area S2 is the same as the above description.

<FIG> is an equivalent circuit diagram of one pixel of the display device of <FIG>. As shown in <FIG>, one pixel PX may include a plurality of TFTs T1, T2, T3, T4, T5, T6, and T7, a capacitor Cst, and an organic light-emitting device (OLED). The plurality of TFTs T1, T2, T3, T4, T5, T6, and T7 or the capacitor Cst may be included in the circuit portion of the pixel PX. The pixel portion is electrically connected to a plurality of signal lines <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> and a power supply line <NUM>.

The TFTs may include a driving TFT T1, a switching TFT T2, a compensation TFT T3, an initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a bypass TFT T7.

The plurality of signal lines may include a scan line <NUM> for transmitting a scan signal Sn, a previous scan line <NUM> for transmitting a previous scan signal Sn-<NUM> to the initialization TFT T4 and the bypass TFT T7, an emission control line <NUM> for transmitting an emission control signal En to the operation control TFT T5 and the emission control TFT T6, a data line <NUM> that intersects the scan line <NUM> and transmits a data signal Dm, and an initialization voltage line <NUM> that transmits an initialization voltage Vint for initializing the driving TFT T1.

The driving TFT T1 receives the data signal Dm according to a switching operation of the switching TFT T2 and supplies a driving current IOLED to the OLED. A gate electrode G1 of the driving TFT T1 may be connected to a capacitor lower electrode Cst1 of the capacitor Cst. A source electrode S1 of the driving TFT T1 may pass through the operation control TFT T5 and may be connected to the power supply line <NUM>. The driving electrode D1 of the driving TFT T1 may pass through the emission control TFT T6 and may be electrically connected to a pixel electrode of the OLED.

A gate electrode G2 of the switching TFT T2 may be connected to the scan line <NUM>. A source electrode S2 of the switching TFT T2 may be connected to the data line <NUM>. A drain electrode D2 of the switching TFT T2 may be connected to the source electrode S1 of the driving TFT T1, may pass through the operation control TFT T5, and may be connected to the power supply line <NUM>. The switching TFT T2 may be turned on according to the scan signal Sn transmitted via the scan line <NUM> and may perform a switching operation of transmitting the data signal Dm transmitted to the data line <NUM> to the source electrode S1 of the driving TFT T1.

A gate electrode G3 of the compensation TFT T3 may be connected to the scan line <NUM>. A source electrode S3 of the compensation TFT T3 may be connected to the drain electrode D1 of the driving TFT T1, may pass through the emission control TFT T6, and may be connected to the pixel electrode of the OLED. A drain electrode D3 of the compensation TFT T3 may be connected to the capacitor lower electrode Cst1 of the capacitor Cst, a drain electrode D4 of the initialization TFT T4 and the gate electrode G1 of the driving TFT T1. The compensation TFT T3 may be turned on according to the scan signal Sn transmitted via the scan line <NUM> and may electrically connect the gate electrode G1 to the drain electrode D1 of the driving TFT T1, thereby diode-connecting the driving TFT T1.

A gate electrode G4 of the initialization TFT T4 may be connected to the previous scan line <NUM>. A source electrode S4 of the initialization TFT T4 may be connected to a drain electrode D7 of the bypass TFT T7 and the initialization voltage line <NUM>. A drain electrode D4 of the initialization TFT T4 may be connected to the capacitor lower electrode Cst1 of the capacitor Cst, the drain electrode D3 of the compensation TFT T3, and the gate electrode G1 of the driving TFT T1. The initialization TFT T4 may be turned on according to the previous scan signal Sn-<NUM> transmitted via the previous scan line <NUM> and may perform an initialization operation of transmitting the initialization voltage Vint to the gate electrode G1 of the driving TFT T1 and initializing a voltage of the gate electrode G1 of the driving TFT T1.

A gate electrode G5 of the operation control TFT T5 may be connected to the emission control line <NUM>. A source electrode S5 of the operation control TFT T5 may be connected to the power supply line <NUM>. A drain electrode D5 of the operation control TFT T5 may be connected to the source electrode S1 of the driving TFT T1 and the drain electrode D2 of the switching TFT T2.

A gate electrode G6 of the emission control TFT T6 may be connected to the emission control line <NUM>. A source electrode S6 of the emission control TFT T6 may be connected to the drain electrode D1 of the driving TFT T1 and the source electrode S3 of the compensation TFT T3. A drain electrode D6 of the emission control TFT T6 may be electrically connected to the source electrode S7 of the bypass TFT T7 and the pixel electrode of the OLED. The operation control TFT T5 and the emission control TFT T6 may be simultaneously turned on according to the emission control signal En transmitted via the emission control line <NUM> and may allow a driving voltage ELVDD to be transmitted to the OLED so that the driving IOLED may flow through the OLED.

A gate electrode G7 of the bypass TFT T7 may be connected to the previous scan line <NUM>. A source electrode S7 of the bypass TFT T7 may be connected to a drain electrode D6 of the emission control TFT T6 and the pixel electrode of the OLED. A drain electrode D7 of the bypass TFT T7 may be connected to the source electrode S4 of the initialization TFT T4 and the initialization voltage line <NUM>. The bypass TFT T7 receives the previous scan signal Sn-<NUM> transmitted via the previous scan line <NUM> from the gate electrode G7. When an electrical signal of a voltage at a certain level at which the bypass TFT T7 may be turned off, is applied from the previous scan signal Sn-<NUM>, the bypass TFT T7 may be in an off state so that some of the driving current Id may be discharged as a bypass current Ibp via the bypass TFT T7.

Even when a minimum current of the driving TFT T1 that displays a black image flows as a driving current and the OLED emits light, the black image might not be properly displayed. Here, the minimum current of the driving TFT T1 refers to a current having conditions on that a gate-source voltage VGS of the driving TFT T1 is smaller than a threshold voltage Vth and the driving TFT T1 is turned off. Thus, even when the minimum current flows as the driving current, to prevent the OLED from emitting light, the bypass TFT T7 may disperse some of the current Id that flows from the driving TFT T1 as the bypass current Ibp along other current paths than the current path toward the OLED. A smaller current than the minimum driving current (for example, a current that is equal to or smaller than <NUM> pA) on conditions that the driving TFT T1 is turned off, may be transmitted to the OLED so that the OLED might not emit light or a degree of emission may be minimized and thus the black image may be realized.

In <FIG>, the initialization TFT T4 and the bypass TFT T7 are connected to the previous scan line <NUM>. However, the present invention is not limited thereto. According to an exemplary embodiment of the present disclosure, the initialization TFT T4 may be connected to the previous scan line <NUM>, may be driven according to the previous scan signal Sn-<NUM>, and the bypass TFT T7 may be connected to an additional wiring and may be driven according to a signal transmitted to the wiring.

A capacitor upper electrode Cst2 of the capacitor Cst may be connected to the power supply line <NUM>, and an opposite electrode of the OLED may be connected to a common voltage ELVSS. Thus, the OLED may receive the driving current IOLED from the driving TFT T1 and may emit light.

In <FIG>, the compensation TFT T3 and the initialization TFT T4 have a dual gate electrode. However, the present invention is not limited thereto. For example, the common TFT T3 and the initialization TFT T4 may have one gate electrode. Also, various other modifications may be made to at least one of the remaining TFTs T1, T2, T5, T6, and T7.

<FIG> is a layout view illustrating positions of thin-film transistors (TFTs) and a capacitor in a pixel included in the display device of <FIG>, <FIG> are layout views illustrating elements, such as a plurality of TFTs and a capacitor of <FIG> according to layers, and <FIG> is a cross-sectional view illustrating some of the display device of <FIG>.

Hereinafter, a detailed structure of the display device of <FIG> will be described with reference to <FIG>.

<FIG> illustrates positions of TFTs and a capacitor of each of a first pixel PX1 in the first area (see S1 of <FIG>) and a second pixel PX2 in the second area (see S2 of <FIG>), and <FIG> illustrate various elements, such as TFTs and a capacitor of each of the first pixel PX1 and the second pixel PX2, according to layers. Also, <FIG> that is a cross-sectional view illustrating some of the display device of <FIG>, for convenience, illustrates a cross-section taken along a line I-I' that passes through an opening OP indicated only in the first pixel PX1 of <FIG>.

As shown in <FIG>, the display device includes a substrate <NUM>.

The substrate <NUM> may include a variety of flexible or bendable materials. For example, the substrate <NUM> may include polymer resin, such as polyethersulphone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC) and/or cellulose acetate propionate (CAP). It is to be understood that the substrate <NUM> may be modified in various ways like having a multi-layer structure including two layers including such polymer resin and a barrier layer including an inorganic material (silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON)) between the two layers.

A plurality of pixels including the first pixel PX1 and the second pixel PX2 may be disposed on the substrate <NUM>. A buffer layer <NUM> may be disposed in the substrate <NUM>. The buffer layer <NUM> may planarize a surface of the substrate <NUM> and/or may prevent impurities from penetrating into a semiconductor layer thereon. The buffer layer <NUM> may have a single layer structure or multi-layer structure including an inorganic insulating material such as SiOx, SiNx, and/or SiON.

The semiconductor layer may be disposed on the buffer layer <NUM>. The semiconductor layer may have various bent shapes, as shown in <FIG>, and the first pixel PX1 and the second pixel PX2 may have semiconductor layers having the same shape. Hereinafter, unless otherwise specified, it may be assumed that layers of each of the first pixel PX1 and the second pixel PX2 have the same shape.

The semiconductor layer may include a driving channel area 131a that corresponds to the driving TFT T1, a switching channel area 131b that corresponds to the switching TFT T2, compensation channel areas 131c1, 131c2, and 131c3 that correspond to the compensation TFT T3, initialization channel areas 131d1, 131d2, and 131d3 that correspond to the initialization TFT T4, an operation control channel area 131e that corresponds to the operation control TFT T5, an emission control channel area 131f that corresponds to the emission control TFT T6, and a bypass channel area <NUM> that corresponds to the bypass TFT T7. For example, the driving channel area 131a, the switching channel area 131b, the compensation channel areas 131c1, 131c2, and 131c3, the initialization channel areas 131d1, 131d2, and 131d3, the operation control channel area 13le, the emission control channel area 131f, and the bypass channel area <NUM> may be some of the areas of the semiconductor layer shown in <FIG>.

The semiconductor layer may include polysilicon. The semiconductor layer may include source areas and drain areas formed by doping impurities at both sides of the channel area. Here, the impurities may be changed according to the type of a TFT and may include N-type impurities or P-type impurities. A channel area, a source area at one side of the channel area, and a drain area at the other side of the channel may be referred to collectively as an active layer. For example, the TFT may have an active layer, and the active layer may include a channel area, a source area, and a drain area.

The source area or drain area formed by doping may be interpreted as either a source electrode or drain electrode of the TFT. For example, the driving source electrode may correspond to a driving source area 176a into which an impurity is doped, near the driving channel area 131a in the semiconductor layer shown in <FIG>, and the driving drain electrode may correspond to a driving drain area 177a into which an impurity is doped, near the driving channel area 131a in the semiconductor layer shown in <FIG>.

A gate insulating layer <NUM> formed of an inorganic insulating material, such as SiOx, SiNx, or SiON, may be disposed in an upper portion of the semiconductor layer.

Conductive layers, such as the gate electrode 125a are disposed on the gate insulating layer <NUM>. Various other conductive layers may be disposed on the gate insulating layer <NUM>. In this way, various conductive layers disposed on the gate insulating layer <NUM> may be referred to as a gate wiring. The gate wiring may include a scan line <NUM>, a previous scan line <NUM>, an emission control line <NUM>, and a capacitor lower electrode, as shown in <FIG>.

The capacitor Cst may at least partially overlap the driving TFT T1. In this case, the capacitor's lower electrode may be a gate electrode 125a of the driving TFT T1. Thus, the area of the capacitor Cst and the driving TFT T1 may be increased, and a high-quality image may be provided. However, the present invention is not limited thereto. According to an exemplary embodiment of the present disclosure, the capacitor Cst might not overlap the driving TFT T1, and the capacitor lower electrode may be a separate independent element from the gate electrode 125a of the driving TFT T1.

As shown in <FIG>, the switching gate electrode 125b and the compensation gate electrodes 125c1 and 125c2 may be portions of the scan line <NUM> that intersects the semiconductor layer, or portions protruding from the scan line <NUM>, and the initialization gate electrodes 125d1 and 125d2 and the bypass gate electrode <NUM> may be portions of the previous scan line <NUM> that intersects the semiconductor layer, or portions protruding from the previous scan line <NUM>, and the operation control gate electrode 125e and the emission control gate electrode 125f may be portions of the emission control line <NUM> that intersects the semiconductor layer, or portions protruding from the emission control line <NUM>.

A first interlayer insulating layer <NUM> may cover a gate wiring. The first interlayer insulating layer <NUM> may be formed of an inorganic insulating material, such as SiNx, SiOx, and/or SiON.

A capacitor's upper electrode <NUM> may be disposed on the first interlayer insulating layer <NUM>. However, the initialization voltage line <NUM> may be disposed in the same layer as a layer in which the capacitor upper electrode <NUM> is disposed.

As shown in <FIG>, an opening <NUM> may be formed in the capacitor's upper electrode <NUM>. Thus, the capacitor's lower electrode and a compensation drain area 177c of the compensation TFT T3 may be electrically connected to each other using a connection member <NUM> to be described later.

A second interlayer insulating layer <NUM> is disposed on the capacitor upper electrode <NUM>. The second interlayer insulating layer <NUM> may be formed of an inorganic insulating material, such as SiNx, SiOx, and/or SiON.

The power supply line <NUM> may be disposed on the second interlayer insulating layer <NUM>. The power supply line <NUM> may be connected to the capacitor upper electrode <NUM> via a contact hole <NUM> formed in the second interlayer insulating layer <NUM> and may be connected to the semiconductor layer thereunder via contact holes <NUM> and <NUM> formed in the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, and the second interlayer insulating layer <NUM>.

Various conductive layers other than the power supply line <NUM> may be disposed on the second interlayer insulating layer <NUM>. As shown in <FIG>, the data line <NUM>, an initialization connection line <NUM>, the connection member <NUM>, and the drain electrode <NUM> are formed on the second interlayer insulating layer <NUM>.

The data line <NUM> may be connected to a switching source area 176b via the contact hole <NUM> formed in the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, and the second interlayer insulating layer <NUM>.

One end of the initialization connection line <NUM> may be connected to the initialization voltage line <NUM> via the contact hole <NUM> formed in the first interlayer insulating layer <NUM> and the second interlayer insulating layer <NUM>. The other end of the initialization connection line <NUM> may be connected to the initialization source area 176d via the contact hole <NUM> formed in the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, and the second interlayer insulating layer <NUM>. The initialization drain area 177d may be a portion of the semiconductor layer into which an impurity at an opposite side to the initialization source area 176d based on the initialization channel area 131d is doped.

One end of the connection member <NUM> may be connected to the compensation drain area 177c and the initialization drain area 177d via the contact hole <NUM> formed in the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, and the second interlayer insulating layer <NUM>, and the other end of the connection member <NUM> may be connected to the capacitor lower electrode via the contact hole <NUM> formed in the first interlayer insulating layer <NUM> and the second interlayer insulating layer <NUM>. In this case, the other end of the connection member <NUM> may be connected to the capacitor lower electrode via an opening <NUM> formed in the capacitor upper electrode <NUM>.

The drain electrode <NUM> may be connected to the emission control drain area 177f via a contact hole <NUM> formed in the gate insulating layer <NUM>, the first interlayer insulating layer <NUM>, and the second interlayer insulating layer <NUM>. The drain electrode <NUM> may be electrically connected to the pixel electrode <NUM>. A source electrode excluding the drain electrode <NUM> may be disposed on the second interlayer insulating layer <NUM>.

A first organic insulating layer <NUM> may be disposed on the power supply line <NUM> and the drain electrode <NUM>, and the connection wirings <NUM> and the dummy patterns <NUM> and <NUM> are formed on the first organic insulating layer <NUM>, as shown in <FIG>. Also, a second organic insulating layer <NUM> may be disposed on the connection wirings <NUM> and the dummy patterns <NUM> and <NUM>.

Each of the first organic insulating layer <NUM> and the second organic insulating layer <NUM> may include imide-based polymer, general-purpose polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, acryl-based polymer, aryl ether-based polymer, amide-based polymer, fluorine (F)-based polymer, p-xylene-based polymer, vinyl alcohol-based polymer, and a blend thereof.

The connection wirings <NUM> and the dummy patterns <NUM> and <NUM> may have a single layer structure or multi-layer structure including aluminum (Al), copper (Cu), titanium (Ti), and/or an alloy thereof.

In the first pixel PX1, the connection wirings <NUM> extend in a direction parallel to the first direction X. For example, the connection wirings <NUM> may at least partially overlap the power supply line <NUM>. The first branches <NUM> that protrude from the connection wirings <NUM> in a direction perpendicular to the lengthwise direction of the connection wirings <NUM> may at least partially overlap the initialization voltage line <NUM> in one example.

In the second pixel PX2, the connection wirings <NUM> may extend in the direction parallel to the second direction Y, and the second branches <NUM> may protrude from the connection wirings <NUM>. For example, in the second pixel PX2, the connection wirings <NUM> may at least partially overlap the initialization voltage line <NUM>, and the second branches <NUM> may at least partially overlap the power supply line <NUM>.

Thus, patterns formed by the connection wirings <NUM> and the first branches <NUM> in the first pixel PX1 and patterns formed by the connection wirings <NUM> and the second branches <NUM> in the second pixel PX2 are similar to each other. Thus, a phenomenon in which a display area may be divided into the first area S1 and the second area S2 and recognized according to an incidence angle of light, may be prevented or minimized.

The first dummy patterns <NUM> and the second dummy patterns <NUM> may prevent signal interference between the circuit portion and the connection wirings <NUM>, as described above, and may secure a pattern density, thereby providing a simplified manufacturing process.

In <FIG>, the connection wirings <NUM> described with reference to <FIG> and <FIG> are used. However, the display device may include the connection wirings <NUM> described with reference to <FIG>.

A light-emitting device <NUM> may be disposed on the second organic insulating layer <NUM>, wherein the light-emitting device <NUM> may include a pixel electrode <NUM>, a common electrode <NUM>, and an intermediate layer <NUM> interposed between the pixel electrode <NUM> and the common electrode <NUM> and including an emission layer. The light-emitting device <NUM> may be an OLED, for example.

The pixel electrode <NUM> may be a (semi-)transparent electrode (i.e. a transparent electrode or a semitransparent electrode) or reflective electrode. When the pixel electrode <NUM> is a (semitransparent electrode, the pixel electrode <NUM> may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In<NUM>O<NUM>), indium gallium oxide (IGO) and/or AZO, for example. When the pixel electrode <NUM> is a reflective electrode, the pixel electrode <NUM> may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and/or a compound thereof, and a layer formed of ITO, IZO, ZnO, In<NUM>O<NUM>, IGO or AZO. The present invention is not limited thereto, and the pixel electrode <NUM> may include various materials, and the pixel electrode <NUM> may be variably modified like having a single layer structure or multi-layer structure.

A pixel-defining layer <NUM> for covering edges of the pixel electrode <NUM> may be disposed on the second organic insulating layer <NUM>. The pixel-defining layer <NUM> may have an opening OP corresponding to each of pixels, i.e., an opening OP through which at least the center of the pixel electrode <NUM> is exposed, thereby defining a pixel. Also, the pixel-defining layer <NUM> increases a distance between the edges of the pixel electrode <NUM> and the common electrode <NUM>, thereby preventing electrical arcing from occurring therebetween. The pixel-defining layer <NUM> may be formed of an organic material, such as polyimide or hexamethyldisiloxane (HMDSO).

The intermediate layer <NUM> may be formed on the pixel electrode <NUM> exposed through the opening OP of the pixel-defining layer <NUM>. The intermediate layer <NUM> may include a small molecular weight material or polymer material. When the intermediate layer <NUM> includes a small molecular weight material, the intermediate layer <NUM> may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL) are stacked in a single or composite structure. The intermediate layer <NUM> may include various organic materials including copper phthalocyanine (CuPc), N,N'-Di(naphthalene-<NUM>-yl)-N,N'-diphenyl-benzidine (NPB), and tris-<NUM>-hydroxyquinoline aluminum)(Alq3). These layers may be formed through a method such as vacuum deposition.

When the intermediate layer <NUM> includes a polymer material, the intermediate layer <NUM> may have a structure including mostly an HTL and an EML. In this case, the HTL may include poly-<NUM>,<NUM>-alkenedioxythiophene (PEDOT), and the EML may include a poly-phenylenevinylene (PPV)-based and polyfluorene-based polymer material. The structure of the intermediate layer <NUM> is not limited to the above description but the intermediate layer <NUM> may have various different structures. For example, the intermediate layer <NUM> may include a layer integrally formed in the plurality of pixel electrodes <NUM> or may include a patterned layer to correspond to each of the plurality of pixel electrodes <NUM>.

The common electrode <NUM> may cover a display area (see AA of <FIG>). For example, the common electrode <NUM> may be formed as one body so as to cover the plurality of light-emitting devices <NUM>. The common electrode <NUM> may be a (semi-)transparent electrode or reflective electrode. When the common electrode <NUM> is a (semi-)transparent electrode, the common electrode <NUM> may have a layer formed of metal having a small work function, e.g., Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, (or another material having a work function within a range established by the aforementioned materials) and/or a compound thereof and a (semi-)transparent conductive layer such as ITO, IZO, ZnO or In<NUM>O<NUM>. When the common electrode <NUM> is a reflective electrode, the common electrode <NUM> may have a layer formed of Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and/or a compound thereof. The configuration and material of the common electrode <NUM> are not limited thereto, and various modifications are possible.

Claim 1:
A display device (<NUM>), comprising:
a substrate (<NUM>) including a display area (AA) in which an image is displayed,
a peripheral area (PA) at least partially surrounding the display area (AA), and
a pad area (PADA) within the peripheral area (PA);
a plurality of data lines (DL) disposed within the display area (AA); and
a plurality of connection wirings (<NUM>) disposed within the display area (AA),
connected to the plurality of data lines (DL), and configured to transmit a data signal from the pad area (PADA) to the plurality of data lines (DL),
wherein
the plurality of connection wirings (<NUM>) are disposed in a
different layer from a layer in which the plurality of data lines (DL) are disposed,
each of the plurality of connection wirings (<NUM>) comprises a plurality of branches (<NUM>) that protrude from the connection wirings (<NUM>) in a direction perpendicular to a direction in which the connection wirings (<NUM>) are primarily extended:
and the display area (AA) comprises a first area (S1) in which the plurality of connection wirings (<NUM>) extend in a first direction (X) and a second area (S2) in which the plurality of connection wirings (<NUM>) extends in a second direction (Y) perpendicular to the first direction (X).