Patent Description:
Heretofore, image sensors using photoelectric conversion have been known. For example, CMOS (Complementary Metal Oxide Semiconductor) type image sensors that have photodiodes are in widespread used. CMOS type image sensors have features such as low power consumption, and accessibility to individual pixels. CMOS type image sensors generally use the so-called rolling shutter method, where exposure and signal charge readout is performed in increments of rows of the pixel array, as the signal readout method.

In rolling shutter operations, the start and end of exposure differs for each pixel array row. Accordingly, in a case of shooting an object moving at high speed, a distorted image may be obtained as the image of the object, and when using a flash, there may be difference in brightness throughout the image. In light of this situation, there is demand for so-called global shutter functions, where all pixels in the pixel array start and end exposure together.

For example, the following PTL <NUM> discloses a CMOS type image sensor capable of global shutter operations. The technology described in PTL <NUM> provides a transfer transistor and a charge storage unit (a capacitor or a diode) to each of multiple pixels. The charge storage unit in each pixel is connected to a photodiode via the transfer transistor.

PTL <NUM>: <CIT> <CIT> relates to an imaging device comprising a plurality of pixel units with a photoelectric conversion layer sandwiched between two electrodes and a charge accumulation portion, wherein a different voltage may be applied to the electrode in an exposure period and a non-exposure period.

<CIT> relates to an image sensor with a photoelectric film, wherein different voltages are applied at the photoelectric film in order to control the sensitivity of the pixel cell.

<CIT> and <CIT> relate to imaging devices comprising a plurality of unit pixels, each including a reset transistor.

<CIT> relates to an image sensor including a semiconductor substrate and a plurality of pixel regions, each comprising an optically sensitive material.

To provide an imaging device capable of realizing global shutter functions while suppressing circuit complexity within pixels.

One non-limiting and exemplary embodiment provides the following.

An imaging device as set out in claim <NUM> includes: unit pixel cells each including a first electrode a second electrode facing the first electrode, a photoelectric conversion layer between the first electrode and second electrode, a charge accumulation region electrically connected to the first electrode, and a signal detection circuit electrically connected to the charge accumulation region; and a voltage supply circuit electrically connected to the second electrode, the voltage supply circuit supplying a first voltage to the second electrode in an exposure period that is a period for accumulating charges generated by photoelectric conversion in the charge accumulation region, the voltage supply circuit supplying a second voltage that is different from the first voltage to the second electrode in a non-exposure period. The start and end of the exposure period is common to the unit pixel cells.

General or specific embodiments may be implemented as an element, a device, an apparatus, a system, an integrated circuit, a method, or a computer program. General or specific embodiments may also be implemented as any selective combination of an element, a device, an apparatus, a system, an integrated circuit, a method, and a computer program.

The benefits and/or advantages may be individually obtained by the various embodiments and features of the specification and drawings, which need not all be provided in order to obtain one or more thereof.

According to an embodiment of the present disclosure, an imaging device capable of realizing global shutter functions can be realized while suppressing circuit complexity within pixels.

Embodiments of the present disclosure will be described below with reference to the drawings. Note that the embodiments described below are each general or specific examples. Values, shapes, materials, components, placements and connected states of components, steps, and the order of steps, and so forth illustrated in the following embodiments, are only exemplary, and do not restrict the present disclosure. Various aspects described in the present specification can be combined as long as there is no contradiction. Components in the following embodiments which are not included in an independent Claim indicating the highest concept are described as being optional components. Components having substantially the same functions may be denoted by common reference symbols in the following description, and description thereof omitted.

<FIG> illustrates an exemplary circuit configuration of an imaging device according to an embodiment of the present disclosure. An imaging device <NUM> illustrated in <FIG> has a pixel array PA that includes multiple unit pixel cells <NUM> arrayed two-dimensionally. <FIG> schematically illustrates an example where unit pixel cells <NUM> are arrayed in a matrix of two rows by two columns. It is needless to say that the number and layout of the unit pixel cells <NUM> in the imaging device <NUM> are not restricted to the example illustrated in <FIG>.

A unit pixel cell <NUM> has a photoelectric conversion unit <NUM> and a signal detection circuit <NUM>. The photoelectric conversion unit <NUM> has a photoelectric conversion layer interposed between two mutually facing electrodes, and generates signals upon receiving incident light. The entire photoelectric conversion unit <NUM> does not need to be an independent element for each unit pixel cell <NUM>, and part of a photoelectric conversion unit <NUM>, for example, may span multiple unit pixel cells <NUM>. The signal detection circuit <NUM> is a circuit that detects signals generated by the photoelectric conversion unit <NUM>. In this example, the signal detection circuit <NUM> includes a signal detection transistor <NUM> and an address transistor <NUM>. The signal detection transistor <NUM> and address transistor <NUM> typically are field-effect transistors (FET). The signal detection transistor <NUM> and address transistor <NUM> here are exemplified as N-channel MOS.

The control terminal (gate here) of the signal detection transistor <NUM> has an electrical connection with the photoelectric conversion unit <NUM>, as schematically illustrated in <FIG>. Signal charges (holes or electrons) generated by the photoelectric conversion unit <NUM> are accumulated in a charge accumulation node (also referred to as "floating diffusion node") <NUM> between the signal detection transistor <NUM> and the photoelectric conversion unit <NUM>. Details of the photoelectric conversion unit <NUM> will be described later.

The photoelectric conversion unit <NUM> of the unit pixel cell <NUM> further has a connection with a sensitivity control line <NUM>. The sensitivity control line <NUM> is connected to a sensitivity control voltage supply circuit <NUM> (hereinafter referred to simply as "voltage supply circuit <NUM>") in the configuration exemplified in <FIG>. This voltage supply circuit <NUM> is a circuit configured to be capable of supplying at least two types of voltage. The voltage supply circuit <NUM> supplies predetermined voltage to the photoelectric conversion unit <NUM> via the sensitivity control line <NUM> when the imaging device <NUM> is operating. The voltage supply circuit <NUM> is not restricted to a particular power source circuit, and may be a circuit that generates a predetermined voltage, or may be a circuit that converts voltage supplied from another power source into predetermined voltage. Starting and ending of accumulation of signal charges from the photoelectric conversion unit <NUM> to the charge accumulation node <NUM> is controlled by the voltage supplied from the voltage supply circuit <NUM> to the photoelectric conversion unit <NUM> being switched among multiple voltages that are different from each other, which will be described later in detail. In other words, electronic shutter operations are executed in the embodiment according to the present disclosure by switching voltage supplied from the voltage supply circuit <NUM> to the photoelectric conversion unit <NUM>. An example of operations of the imaging device <NUM> will be described later.

Each unit pixel cell <NUM> has a connection with a power source line <NUM> that supplies power source voltage VDD. The input terminal (typically the drain) of the signal detection transistor <NUM> is connected to the power source line <NUM>, as illustrated. The signal detection transistor <NUM> amplifies and outputs signals generated by the photoelectric conversion unit <NUM> due to the power source line <NUM> functioning as a source-follower power source.

The output terminal (source here) of the signal detection transistor <NUM> is connected to the input terminal (drain here) of the address transistor <NUM>. The output terminal (source here) of the address transistor <NUM> is connected to one of multiple vertical signal lines <NUM> arranged in each pixel array PA row. The control terminal (gate here) of the address transistor <NUM> is connected to an address control line <NUM>, and the output of the signal detection transistor <NUM> can be selectively read out to the corresponding vertical signal line <NUM> by controlling the potential of the address control line <NUM>.

In the illustrated example, the address control line <NUM> is connected to a vertical scan circuit (also referred to as "row scan circuit") <NUM>. The vertical scan circuit <NUM> selects multiple unit pixel cells <NUM> arranged in each row by applying a predetermined voltage to the address control line <NUM>. This executes readout of signals in the selected unit pixel cells <NUM>, and later-described resetting of pixel electrodes.

The vertical signal line <NUM> is a primary signal line transmitting pixel signals from the pixel array PA to peripheral circuits. A column signal processing circuit (also referred to as "row signal accumulation circuit") <NUM> is connected to the vertical signal line <NUM>. The column signal processing circuit <NUM> performs noise suppression signal processing, of which correlated double sampling is representative, analog-to-digital conversion (AD conversion), and so forth. A column signal processing circuit <NUM> is provided corresponding to each column of unit pixel cells <NUM> in the pixel array PA, as illustrated. Connected to these column signal processing circuits <NUM> are a horizontal signal read circuit (also referred to as "column scan circuit") <NUM>. The horizontal signal read circuit <NUM> sequentially reads out signals from the column signal processing circuits <NUM> to a horizontal common signal line <NUM>.

In the configuration exemplified in <FIG>, the unit pixel cell <NUM> has a reset transistor <NUM>. The reset transistor <NUM> may be a field-effect transistor, in the same way as the signal detection transistor <NUM> and address transistor <NUM>, for example. An example will be described below where an N-channel MOS is applied as the reset transistor <NUM>, unless specifically stated otherwise. As illustrated, the reset transistor <NUM> is connected between a reset voltage line <NUM> that supplies reset voltage Vr and a charge accumulation node <NUM>. The control terminal (gate here) of the reset transistor <NUM> is connected to a reset control line <NUM>, and the potential of the charge accumulation node <NUM> can be reset to the reset voltage Vr by controlling the potential of the reset control line <NUM>. The reset control line <NUM> is connected to the vertical scan circuit <NUM> is this example. Accordingly, multiple unit pixel cells <NUM> arrayed in each row can be reset in increments of rows by the vertical scan circuit <NUM> applying predetermined voltage to the reset control line <NUM>.

In this example, the reset voltage line <NUM> that supplies reset voltage Vr to the reset transistor <NUM> is connected to the reset voltage supply circuit <NUM> (hereinafter referred to simply as "reset voltage source <NUM>"). It is sufficient that the configuration of the reset voltage source <NUM> enables a predetermined reset voltage Vr to be supplied to the reset voltage line <NUM> when the imaging device <NUM> is operating, and is not restricted to any particular power source circuit, the same as with the voltage supply circuit <NUM> described above. The voltage supply circuit <NUM> and reset voltage source <NUM> may each be part of a single voltage supply circuit, or may be independent and separate voltage supply circuits. Note that one or both of the voltage supply circuit <NUM> and reset voltage source <NUM> may be part of the vertical scan circuit <NUM>. Alternatively, sensitivity control voltage from the voltage supply circuit <NUM> and/or reset voltage Vr from the reset voltage source <NUM> may be supplied to each unit pixel cell <NUM> via the vertical scan circuit <NUM>.

Power source voltage VDD of the signal detection circuit <NUM> may be used as the reset voltage Vr. In this case, a voltage supply circuit that supplies power source voltage to each of the unit pixel cells <NUM> (omitted from illustration in <FIG>) and the reset voltage source <NUM> may be commonalized. The power source line <NUM> and reset voltage line <NUM> can also be commonalized, so the wiring of the pixel array PA can be simplified. Note however, that using mutually different voltages for the reset voltage Vr and for the power source voltage VDD of the signal detection circuit <NUM> enables more flexible control of the imaging device <NUM>.

<FIG> schematically illustrates an exemplary device structure of the unit pixel cell <NUM>. The above-described signal detection transistor <NUM>, address transistor <NUM>, and reset transistor <NUM>, are formed on a semiconductor substrate <NUM> in the configuration exemplified in <FIG>. The semiconductor substrate <NUM> is not restricted to a substrate of which the entirety is a semiconductor. The semiconductor substrate <NUM> may be an insulating substrate, where a semiconductor layer has been formed on the surface of a side where a photosensitive region is formed, or the like. An example of using a P-type silicon (Si) substrate as the semiconductor substrate <NUM> will be described here.

The semiconductor substrate <NUM> includes impurity regions (N-type region here) <NUM>, <NUM>, 24d, 28d, and <NUM>, and element separation region 20t for electric separation among unit pixel cells <NUM>. The element separation region 20t is also provided between impurity region 24d and impurity region 28d as well. The element separation region 20t is formed by injecting acceptor ions under predetermined injection conditions, for example.

The impurity regions (N-type region here) <NUM>, <NUM>, 24d, 28d, and <NUM>, typically are diffusion layers formed within the semiconductor substrate <NUM>. The signal detection transistor <NUM> includes the impurity regions <NUM> and 24d, and gate electrode <NUM> (typically a polysilicon electrode), as schematically illustrated in <FIG>. The impurity region <NUM> functions as a source region, for example, of the signal detection transistor <NUM>. The impurity region 24d functions as a drain region, for example, of the signal detection transistor <NUM>. A channel region of the signal detection transistor <NUM> is formed between the impurity regions <NUM> and 24d.

In the same way, the address transistor <NUM> includes the impurity regions <NUM> and <NUM>, and a gate electrode <NUM> (typically a polysilicon electrode) connected to the address control line <NUM> (see <FIG>). In this example, the signal detection transistor <NUM> and address transistor <NUM> are electrically connected to each other by sharing the impurity region <NUM>. The impurity region <NUM> functions as a source region, for example, of the address transistor <NUM>. The impurity region <NUM> has a connection with the vertical signal line <NUM> (see <FIG>) that is omitted from <FIG>.

The reset transistor <NUM> has impurity regions 28d and <NUM>, and a gate electrode <NUM> (typically a polysilicon electrode) connected to the reset control line <NUM> (see <FIG>). The impurity region <NUM> functions as a source region, for example, of the reset transistor <NUM>. The impurity region <NUM> has a connection with the reset voltage line <NUM> (see <FIG>) that is omitted from <FIG>.

An inter-layer insulation layer <NUM> (typically a silicon dioxide layer) is disposed on the semiconductor substrate <NUM>, covering the signal detection transistor <NUM>, address transistor <NUM>, and reset transistor <NUM>. A wiring layer <NUM> may be disposed in the inter-layer insulation layer <NUM>. The wiring layer <NUM> typically is formed of metal such as copper or the like, and can include wiring such as the above-described vertical signal line <NUM> and so forth as a part thereof, for example. The number of layers of the insulating layer in the inter-layer insulation layer <NUM>, and the number of layers of the wiring layer <NUM> disposed in the inter-layer insulation layer <NUM> may be optionally set, and are not restricted to the example illustrated in <FIG>.

The above-described photoelectric conversion unit <NUM> is disposed on the inter-layer insulation layer <NUM>. In other words, the multiple unit pixel cells <NUM> making up the pixel array PA (see <FIG>) are formed on the semiconductor substrate <NUM> in the embodiment according to the present disclosure. The unit pixel cells <NUM> arrayed two-dimensionally on the semiconductor substrate <NUM> form a photosensitive region (pixel region). The distance between two adjacent unit pixel cells <NUM> (pixel pitch) may be around <NUM>, for example.

The photoelectric conversion unit <NUM> includes a pixel electrode <NUM>, an opposing electrode <NUM>, and the photoelectric conversion layer <NUM> interposed therebetween. The opposing electrode <NUM> and photoelectric conversion layer <NUM> are formed spanning multiple unit pixel cells <NUM> in this example. On the other hand, the pixel electrode <NUM> is formed for each unit pixel cell <NUM>, and is electrically separated from pixel electrodes <NUM> of other unit pixel cells <NUM> by being spatially separated from pixel electrodes <NUM> of other unit pixel cells <NUM>.

The opposing electrode <NUM> is typically a transparent electrode formed of a transparent electroconductive material. The opposing electrode <NUM> is disposed at the side where light enters the photoelectric conversion layer <NUM>. Accordingly, light that has passed through the opposing electrode <NUM> enters the photoelectric conversion layer <NUM>. Light detected by the imaging device <NUM> is not restricted to the wavelength range of visible light (e.g., <NUM> or more, and <NUM> or less). The term "transparent" as used in the present specification means that at least part of light of a wavelength range to be detected is transmitted, and transmitting the entire wavelength range of visible light is not essential. For the sake of convenience, the electromagnetic waves in general, including infrared rays and ultraviolet rays, will be expressed as "light". For example, transparent electroconductive oxides (Transparent Conducting Oxide (TCO)) such as ITO, IZO, AZO, FTO, SnO<NUM>, TiO<NUM>, ZnO<NUM>, and so forth, can be used as the opposing electrode <NUM>.

The photoelectric conversion layer <NUM> receives incident light, and generates hole-electron pairs. The photoelectric conversion layer <NUM> typically is formed of an organic material. Specific examples of materials configuring the photoelectric conversion layer <NUM> will be described later.

As described referring to <FIG>, the opposing electrode <NUM> has a connection with the sensitivity control line <NUM> connected to the voltage supply circuit <NUM>. The opposing electrode <NUM> here is formed spanning multiple unit pixel cells <NUM>. Accordingly, sensitivity control voltage of a predetermined magnitude can be applied en bloc from the voltage supply circuit <NUM> to the unit pixel cells <NUM> via the sensitivity control line <NUM>. Note that the opposing electrode <NUM> may be separated for each unit pixel cell <NUM>, as long as sensitivity control voltage of a predetermined magnitude can be applied from the voltage supply circuit <NUM>. In the same way, the photoelectric conversion layer <NUM> may be separated for each unit pixel cell <NUM>.

The voltage supply circuit <NUM> supplies mutually different voltages to the opposing electrode <NUM>, depending on whether during an exposure period or a non-exposure period, which will be described later in detail. The term "exposure period" in the present specification means a period for accumulating one of positive and negative charges (signal charges) generated by photoelectric conversion in the charge accumulation region, and may be referred to as "charge accumulation period". A period during operations of the imaging device other than an exposure period is referred to as "non-exposure period" in the present specification. Note that "non-exposure period" is not restricted to a period when input of light to the photoelectric conversion unit <NUM> is shielded, and may include a period when the photoelectric conversion unit <NUM> is being irradiated by light. "Non-exposure period" also includes a period when signal charges are unintentionally accumulated in the charge accumulation region due to occurrence of parasitic sensitivity.

Controlling the potential of the opposing electrode <NUM> relative to the potential of the pixel electrode <NUM> enables one of holes and electrons, of the hole-electron pairs generated in the photoelectric conversion layer <NUM> by photoelectric conversion, to be collected by the pixel electrode <NUM>. For example, in a case of using holes as signal charges, holes can be selectively collected by the pixel electrode <NUM> by setting the potential of the opposing electrode <NUM> higher than the potential of the pixel electrode <NUM>. A case of using holes as signal charges will be exemplified below. Of course, electrons can be used as signals charges as well.

Applying an appropriate bias voltage between the opposing electrode <NUM> and pixel electrode <NUM> causes the pixel electrode <NUM> facing the opposing electrode <NUM> to collect one of positive and negative charges generated by photoelectric conversion at the photoelectric conversion layer <NUM>. The pixel electrode <NUM> is formed of a metal such as aluminum, copper, or the like, a metal nitride, polysilicon that has been imparted electroconductivity by doping with an impurity, or the like.

The pixel electrode <NUM> may be a light-shielding electrode. For example, forming a TaN electrode <NUM> thick as the pixel electrode <NUM> realizes sufficient light shielding characteristics. Forming the pixel electrode <NUM> as a light-shielding electrode enables light that has passed through the photoelectric conversion layer <NUM> to be suppressed from entering the channel region or impurity region of transistors (at least one of the signal detection transistor <NUM>, address transistor <NUM>, and reset transistor <NUM> in this example) formed on the semiconductor substrate <NUM>. The above-described wiring layer <NUM> may be used to form a light-shielding layer in the inter-layer insulation layer <NUM>. Suppressing light from entering the channel region of transistors formed on the semiconductor substrate <NUM> enables shifting of transistor characteristics (e.g., change in threshold voltage) and so forth to be suppressed. Suppressing light from entering the impurity region formed on the semiconductor substrate <NUM> enables unintended noise due to photoelectric conversion in the impurity region from being included. Thus, suppressing light from entering the semiconductor substrate <NUM> contributes to improved reliability of the imaging device <NUM>.

The pixel electrode <NUM> is connected to the gate electrode <NUM> of the signal detection transistor <NUM> via a plug <NUM>, wiring <NUM>, and a contact plug <NUM>, as schematically illustrated in <FIG>. In other words, the gate of the signal detection transistor <NUM> has electric connection with the pixel electrode <NUM>. The plug <NUM> and wiring <NUM> are formed of metal such as copper, for example. The plug <NUM>, wiring <NUM>, and contact plug <NUM> make up at least part of the charge accumulation node <NUM> (see <FIG>) between the signal detection transistor <NUM> and the photoelectric conversion unit <NUM>. The wiring <NUM> may be part of the wiring layer <NUM>. The pixel electrode <NUM> is also connected to the impurity region 28d via the plug <NUM>, wiring <NUM>, and a contact plug <NUM>. In the configuration illustrated in <FIG>, the gate electrode <NUM> of the signal detection transistor <NUM>, the plug <NUM>, wiring <NUM>, contact plugs <NUM> and <NUM>, and the impurity region 28d that is one of the source region and drain region of the reset transistor <NUM>, function as the charge accumulation region accumulating signal charges collected by the pixel electrode <NUM>.

By collecting signal charges to the pixel electrode <NUM>, voltage corresponding to the quantity of signal charges accumulated in the charge accumulation region is applied to the gate of the signal detection transistor <NUM>. The signal detection transistor <NUM> amplifies this voltage. The voltage amplified by the signal detection transistor <NUM> is selectively read out via the address transistor <NUM> as signal voltage.

As described above, irradiating the photoelectric conversion layer <NUM> by light and applying bias voltage between the pixel electrode <NUM> and opposing electrode <NUM> enables one of positive and negative charges generated by photoelectric conversion to be collected by the pixel electrode <NUM>, and the collected charges to be accumulated in the charge accumulation region. The present inventors have found that movement of signal charges already accumulated in the charge accumulation region to the opposing electrode <NUM> via the photoelectric conversion layer <NUM> can be suppressed by using a photoelectric conversion layer <NUM>, having photocurrent characteristics such as described below, in the photoelectric conversion unit <NUM> and reducing the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> to a certain level. The present inventors have further found that further accumulation of signal charges in the charge accumulation region can be suppressed after reducing the potential difference. That is to say, it has been found that global shutter functions can be realized by controlling the magnitude of bias voltage applied to the photoelectric conversion layer <NUM>, without separately providing elements such as a transfer transistor to each of the multiple pixels. A typical example of operations at the imaging device <NUM> will be described later.

An example of the configuration of the photoelectric conversion layer <NUM>, and photocurrent characteristics of the photoelectric conversion layer <NUM>, will be described below.

The photoelectric conversion layer <NUM> typically contains a semiconductor material. An organic semiconductor material is used here as the semiconductor material.

The photoelectric conversion layer <NUM> includes tin naphthalocyanine expressed by the general formula (<NUM>) below (hereinafter may be referred to simply as "tin naphthalocyanine").

In the general formula (<NUM>), R<NUM> through R<NUM> independently represent a hydrogen atom or substituent group. Substituent groups are not restricted to particular substituent groups. A substituent group may be a deuterium atom, halogen atom, alkylic group (including cycloalkyl group, bicycloalkyl group, tricycloalkyl group), alkenyl group (including cycloalkenyl group and bicycloalkenyl group), alkynyl group, aryl group, heterocyclic group (may also be called hetero ring group), cyano group, hydroxy group, nitro group, carboxy group, alkoxy group, aryloxy group, silyloxy group, heterocyclic oxy group, acyloxy group, carbamoyloxy group, alkoxycarbonyloxy group, aryloxycarbonyloxy group, amino group (including anilino group), ammonio group, acylamino group, aminocarbonyl amino group, alkoxycarbonylamino group, aryloxy carbonylamino group, sulfamoyl amino group, alkylsulfonyl amino group, arylsulfonylamino group, mercapto group, alkylthio group, arylthio group, heterocyclic thio group, sulfamoyl group, sulfo group, alkylsulfinyl group, arylsulfinyl group, alkylsulfonyl group, arylsulfonyl group, acyl group, aryloxycarbonyl group, alkoxycarbonyl group, carbamoyl group, arylazo group, heterocyclic azo group, imide group, phosphino group, phosphinyl group, phosphinyloxy group, hophinyl amino group, phosphono group, silyl group, hydrazino group, ureido group, boronic acid group (-B(OH)<NUM>), phosphato group (-OPO(OH)<NUM>), sulfato group (-OSO<NUM>H), or other known substituent groups.

Commercially-available products can be used for the tin naphthalocyanine in the above-described general formula (<NUM>). Alternatively, the tin naphthalocyanine in the above-described general formula (<NUM>) may be synthesized using a naphthalene derivative shown in the following general formula (<NUM>) as the starting material, as described in <CIT>. R<NUM> through R<NUM> in general formula (<NUM>) may be substituents the same as R<NUM> through R<NUM> in general formula (<NUM>).

From the perspective of ease of controlling the coagulation state of molecules, it is desirable that in the tin naphthalocyanine in the above-described general formula (<NUM>), eight or more of the R<NUM> through R<NUM> are hydrogen atoms or deuterium atoms, more desirable that <NUM> or more of the R<NUM> through R<NUM> are hydrogen atoms or deuterium atoms, and even more desirable that all of the R<NUM> through R<NUM> are hydrogen atoms or deuterium atoms. Further, the tin naphthalocyanine shown in the following general formula (<NUM>) is advantageous from the perspective of ease of synthesis. <CHM>
<CHM>.

The tin naphthalocyanine in the above-described general formula (<NUM>) has absorption in a wavelength band generally <NUM> or more and <NUM> or less. For example, the tin naphthalocyanine in the general formula (<NUM>) has an absorption peak at a position around a wavelength of <NUM>, as illustrated in <FIG> is an example of an absorption spectrum in a photoelectric conversion layer containing the tin naphthalocyanine shown in the general formula (<NUM>). Note that measurement of the absorption spectrum as performed using a sample where a photoelectric conversion layer (thickness: <NUM>) was deposited on a quartz substrate.

It can be seen from <FIG> that a photoelectric conversion layer formed of material including tin naphthalocyanine has absorption in a near-infrared region. That is to say, selecting a material including tin naphthalocyanine as the material for configuring the photoelectric conversion layer <NUM> enables a light sensor that can detect near-infrared rays to be realized, for example.

<FIG> schematically illustrates an example of the configuration of the photoelectric conversion layer <NUM>. in the configuration exemplarily illustrated in <FIG>, the photoelectric conversion layer <NUM> includes a hole blocking layer <NUM>, a photoelectric conversion structure 15A formed using an organic semiconductor material including the tin naphthalocyanine in the above-described general formula (<NUM>), and an electron blocking layer 15e. The hole blocking layer <NUM> is disposed between the photoelectric conversion structure 15A and opposing electrode <NUM>, and the electron blocking layer 15e is disposed between the photoelectric conversion structure 15A and pixel electrode <NUM>.

The photoelectric conversion structure 15A illustrated in <FIG> includes at least one of a p-type semiconductor and n-type semiconductor. In the configuration exemplarily illustrated in <FIG>, the photoelectric conversion structure 15A includes a p-type semiconductor layer 150p, an n-type semiconductor layer 150n, and a mixed layer <NUM> interposed between the p-type semiconductor layer 150p and n-type semiconductor layer 150n. The p-type semiconductor layer 150p is disposed between the electron blocking layer 15e and the mixed layer <NUM>, and has photoelectric conversion and/or hole transporting functions. The n-type semiconductor layer 150n is disposed been the hole blocking layer <NUM> and the mixed layer <NUM>, and has photoelectric conversion and/or electron transporting functions. The mixed layer <NUM> may contain at least one of a p-type semiconductor and an n-type semiconductor, which will be described later.

The p-type semiconductor layer 150p and the n-type semiconductor layer 150n respectively include an organic p-type semiconductor and an organic n-type semiconductor. That is to say, the photoelectric conversion structure 15A includes an organic photoelectric conversion material including the tin naphthalocyanine in the above-described general formula (<NUM>), and at least one of an organic p-type semiconductor and an organic n-type semiconductor.

The organic p-type semiconductor (compound) is a donor organic semiconductor (compound) and is an organic compound that is primarily represented by hole-transporting organic compounds and has a nature of readily donating electrons. More specifically, the organic p-type semiconductor (compound) is an organic compound that has the smaller ionization potential of two organic materials when the two organic materials are used in contact. Accordingly, any organic compound can be used as the donor organic compound as long as it is an electron-donating organic compound. Examples include a triarylamine compound, benzidine compound, pyrazoline compound, styrylamine compound, hydrazone compound, triphenylmethane compound, carbazole compound, polysilane compound, thiophene compound, phthalocyanine compound, cyanine compound, merocyanine compound, oxonol compound, polyamine compound, indole compound, pyrrole compound, pyrazole compound, polyarylene compound, condensed aromatic carbocyclic compound (naphthalene derivative, anthracene derivative, phenanthrene derivative, tetracene derivative, pyrene derivative, perylene derivative, fluoranthene derivative), metallic complex having a nitrogen-containing heterocyclic compound as a ligand, and so forth. Note that donor organic semiconductors are not restricted to those, and any organic compound can be used as the donor organic semiconductors as long as it has an ionization potential smaller than an organic compound used as an n-type (acceptor) compound. The above-described tin naphthalocyanine is an example of an organic p-type semiconductor material.

The organic n-type semiconductor (compound) is an acceptor organic semiconductor (compound) and is an organic compound that is primarily represented by electron-transporting organic compounds and has a nature of readily accepting electrons. More specifically, the organic n-type semiconductor (compound) is an organic compound that has the greater electron affinity of two organic materials when the two organic materials are used in contact. Accordingly, any organic compound can be used as the acceptor organic compound as long as it is an electron-accepting organic compound. Examples include fullerene, fullerene derivative, condensed aromatic carbocyclic compound (naphthalene derivative, anthracene derivative, phenanthrene derivative, tetracene derivative, pyrene derivative, perylene derivative, fluoranthene derivative), five- to seven-membered heterocyclic compounds including nitrogen atoms, oxygen atoms, or sulfur atoms (e.g., pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, piridine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, tribenzazepine, etc.), polyarylene compound, fluorene compound, cyclopentadiene compound, silyl compound, metallic complex having a nitrogen-containing heterocyclic compound as a ligand, and so forth. Note that acceptor organic semiconductors are not restricted to those, and any organic compound can be used as the acceptor organic semiconductor as long as it has an electron affinity greater than an organic compound used as a p-type (donor) compound.

The mixed layer <NUM> may be a bulk heterojunction structure including a p-type semiconductor and an n-type semiconductor, for example. In a case of forming the mixed layer <NUM> as a layer having a bulk heterojunction structure, the tin naphthalocyanine in the above-described general formula (<NUM>) may be used as the p-type semiconductor material. Fullerene and/or a fullerene derivative, for example, may be used as the n-type semiconductor material. It is advantageous for the material making up the p-type semiconductor layer 150p to be the same as the p-type semiconductor material included in the mixed layer <NUM>. In the same way, it is advantageous for the material making up the n-type semiconductor layer 150n to be the same as the n-type semiconductor material included in the mixed layer <NUM>. A bulk heterojunction structure is disclosed in <CIT>.

Using an appropriate material in accordance with the wavelength band regarding which detection is desired enables an imaging device having sensitivity regarding the desired wavelength band to be realized. The photoelectric conversion layer <NUM> may include inorganic semiconductor material such as amorphous silicon and the like. The photoelectric conversion layer <NUM> may include a layer made up of organic material and a layer made up of inorganic material. An example of applying a bulk heterojunction structure, obtained by codeposition of tin naphthalocyanine and C<NUM>, to the photoelectric conversion layer <NUM>, will be described below.

<FIG> illustrates typical photocurrent characteristics of the photoelectric conversion layer <NUM>. The graph with the thick solid line in <FIG> represents exemplary current-voltage characteristics (I-V characteristics) of the photoelectric conversion layer <NUM>. Note that <FIG> also illustrates an example of I-V characteristics in a state where there is no irradiation by light, by the thick dotted line.

<FIG> illustrates change in current density between two principal faces of the photoelectric conversion layer <NUM> when bias voltage applied therebetween is changed. In the present specification, the forward direction and reverse direction in bias voltage is defined as follows. In a case where the photoelectric conversion layer <NUM> has a junction structure of a layered p-type semiconductor and a layered n-type semiconductor, bias voltage where the potential of the p-type semiconductor layer is higher than that of the n-type semiconductor layer is defined as forward bias voltage. On the other hand, bias voltage where the potential of the p-type semiconductor layer is lower than that of the n-type semiconductor layer is defined as reverse bias voltage. Forward and reverse can be defined in a case of using organic semiconductor material, in the same way as a case of using inorganic semiconductor material. In a case where the photoelectric conversion layer <NUM> has a bulk heterojunction structure, more p-type semiconductor than n-type semiconductor appears on one surface of the two principal faces of the bulk heterojunction structure, and more n-type semiconductor than p-type semiconductor appears on the other surface, as schematically illustrated in <FIG> of <CIT> described above. Accordingly, bias voltage where the potential of the principal face where more p-type semiconductor than n-type semiconductor appears, is higher than that of the principal face where more n-type semiconductor than p-type semiconductor appears, is defined as forward bias voltage.

The photocurrent characteristics of the photoelectric conversion layer <NUM> are schematically characterized by three voltage ranges, which are the first through third voltage ranges illustrated in <FIG>. The first voltage range is a reverse bias voltage range, and is a voltage range where the absolute value of output current density increases along with increase in reverse bias voltage. The first voltage range can be said to be a voltage range where photocurrent increases along with increase in bias voltage applied between the principal faces of the photoelectric conversion layer <NUM>. The second voltage range is a forward bias voltage range, and is a voltage range where the absolute value of output current density increases along with increase in forward bias voltage. That is to say, the second voltage range is a voltage range where forward current increases along with increase in bias voltage applied between the principal faces of the photoelectric conversion layer <NUM>. The third voltage range is a voltage range between the first voltage range and the second voltage range.

The first through third voltage ranges are distinguished by the inclination of the photocurrent characteristic graph when a linear vertical axis and a linear horizontal axis are used. For reference, the average inclinations of the graph in the first voltage range and the second voltage range are respectively indicated by a dotted line L1 and dotted line L2. The rate of change of output current density relative to increase of bias voltage differs among the first voltage range, second voltage range, and third voltage range, as exemplarily illustrated in <FIG>. The third voltage range is defined as a voltage range where the rate of change of output current density relative to bias voltage is smaller than the rate of change in the first voltage range and the rate of change in the second voltage range. Alternatively, the third voltage range may be decided based on the position where the graph representing I-V characteristics rises (falls). The third voltage range typically is greater than -<NUM> V and smaller than +<NUM> V. Changing the bias voltage within the third voltage range hardly changes the current density between principal faces of the photoelectric conversion layer <NUM>. The absolute value of current density in the third voltage range typically is <NUM>µmA/cm<NUM> or less.

<FIG> is a diagram for describing an example of operations of the imaging device according to the embodiment of the present disclosure. <FIG> illustrates the timing of the trailing edge (or leading edge) of a synchronization signal, change over time of the magnitude of bias voltage applied to the photoelectric conversion layer <NUM>, and the timing of resetting and exposure in each row of the pixel array PA (see <FIG>). More specifically, the topmost graph in <FIG> indicates the timing of the trailing edge (or leading edge) of a vertical synchronization signal Vss. The second graph from the top indicates the timing of the trailing edge (or leading edge) of a horizontal synchronization signal Hss. Beneath these graphs are illustrated an example of change over time of voltage Vb applied from the voltage supply circuit <NUM> to the opposing electrode <NUM> via the sensitivity control line <NUM>. Under the graph of change over time of voltage Vb is change over time of potential φ of the opposing electrode <NUM> with the potential of the pixel electrode <NUM> as a reference. The both-sided arrow G3 at the potential φ graph indicates the above-described third voltage range. The chart further below schematically illustrates the timing of resetting and exposure at each row in the pixel array PA.

Hereinafter, an example of operations at the imaging device <NUM> will be described with reference to <FIG>, <FIG>, and <FIG>. For the sake of brevity, an example of operations in a case where the number of rows of pixels included in the pixel array PA is the eight rows of row R0 through row R7.

In the acquisition of an image, first, resetting of the charge accumulation region of each unit pixel cell <NUM> in the pixel array PA, and pixel signal readout after resetting, is performed. For example, resetting is started of the multiple pixels belonging to the R0 row, based on the vertical synchronization signal Vss (time t0). Note that the rectangles indicated by dots in <FIG> schematically represent signal readout periods. These readout periods may include a reset period for resetting the potential of the charge accumulation region of the unit pixel cell <NUM> therein.

In the resetting of pixels belonging to the R0 row, the address transistor <NUM> the gate of which is connected to the address control line <NUM> is turned ON by control of the potential of the address control line <NUM> for the row R0, and further, the reset transistor <NUM> the gate of which is connected to the reset control line <NUM> is turned ON by control of the potential of the reset control line <NUM> for the row R0. Accordingly, the charge accumulation node <NUM> and reset voltage line <NUM> are connected to each other, and reset voltage Vr is supplied to the charge accumulation region. That is to say, the potential of the gate electrode <NUM> of the signal detection transistor <NUM> and the pixel electrode <NUM> of the photoelectric conversion unit <NUM> is reset to the reset voltage Vr. Thereafter, after resetting, pixel signals are read out from the unit pixel cells <NUM> in the row RD via the vertical signal line <NUM>. The pixel signals obtained at this time are pixel signals corresponding to the magnitude of the reset voltage Vr. After reading out of the pixel signals, the reset transistor <NUM> and address transistor <NUM> are turned off.

In this example, resetting of pixels belonging to the rows of row R0 through row R7 in accordance with the horizontal synchronization signal Hss is sequentially executed, as schematically illustrated in <FIG>. Hereinafter, intervals between horizontal synchronization signal Hss pulses, i.e., a period from the time when one row is selected to the time when the next row is selected, may be referred to as "one H period". The period from time t0 to time t1 is equivalent to one H period in this example.

During the period from the time when image acquisition starts to the time when resetting and readout of the pixel signal of all pixel arrays PA ends (time t0 through t9), a voltage V3 is applied from the voltage supply circuit <NUM> to the opposing electrode <NUM> such that the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> falls within the above-described third voltage range. That is to say, in the period from starting of image acquisition to starting of the exposure period (time t9), the photoelectric conversion layer <NUM> of the photoelectric conversion unit <NUM> is in a state where bias voltage in the third voltage range is applied.

In a state where bias voltage in the third voltage range is applied to the photoelectric conversion layer <NUM>, any movement of signal charges from the photoelectric conversion layer <NUM> to the charge accumulation region hardly occurs. The reason is estimated to be that in the state where bias voltage of the third voltage range is applied to the photoelectric conversion layer <NUM>, almost all of the positive and negative charges generated by irradiation by light rapidly recouple, and vanish before being collected by the pixel electrode <NUM>. Accordingly, even in a case where light enters the photoelectric conversion layer <NUM>, accumulation of signals charges to the charge accumulation region hardly occurs at all in the state where the bias voltage of the third voltage range is applied to the photoelectric conversion layer <NUM>. Thus, occurrence of unintended sensitivity (may be referred to as "parasitic sensitivity" in the present specification) in a period other than an exposure period is suppressed. In this way, the fact that sensitivity can be quickly dropped to <NUM> by setting the bias voltage to the photoelectric conversion layer <NUM> to fall within the third voltage range is a finding that has been first discovered by the present inventors.

When focusing on a certain row in <FIG> (row R0 for example), the periods of rectangles indicated by oblique lines and rectangles indicated by dots represent non-exposure periods. Note that the voltage V3 for applying bias voltage within the third voltage range to the photoelectric conversion layer <NUM> is not restricted to <NUM> V.

After resetting and reading out of pixel signals for all rows in the pixel array PA has ended, the exposure period is started based on the horizontal synchronization signal Hss (time t9). The white rectangles in <FIG> schematically represent exposure periods at each row. The exposure period is started by the voltage supply circuit <NUM> switching the voltage to be applied to the opposing electrode <NUM> to a voltage Ve that is different from the voltage V3. The voltage Ve typically is a voltage where the potential difference between he pixel electrode <NUM> and opposing electrode <NUM> falls within the above-described first voltage range (e.g., around <NUM> V). Due to the voltage Ve being applied to the opposing electrode <NUM>, signal changes in the photoelectric conversion layer <NUM> (holes in this example) are collected by the pixel electrode <NUM> and accumulated in the charge accumulation region (may be referred to as charge accumulation node <NUM>).

The voltage supply circuit <NUM> switches the voltage applied to the opposing electrode <NUM> to the voltage V3 again, whereby the exposure period ends (time t13). Thus, in the embodiment according to the present disclosure, the exposure period and non-exposure period are switched by switching the voltage applied to the opposing electrode <NUM> between voltage V3 and voltage Ve. It can be seen from <FIG> that the start (time t9) and end (time t13) of the exposure period is held in common among all pixels included in the pixel array PA. That is to say, the operations described here are an example of a global shutter applied to the imaging device <NUM>.

Next, readout of signal charges from the pixels belonging to each of the rows in the pixel array PA is started, based on the horizontal synchronization signal Hss. In this example, readout of signals charges from pixels belonging to the rows of row R0 through R7 is sequentially performed in increments of rows, from time t15. Hereinafter, a period from the time when pixels belonging to a certain row are selected to the time when pixels belonging to that row are selected again may be referred to as "<NUM> V period". A period from time t0 to time <NUM> is equivalent to <NUM> V period in this example.

In the readout of signal charges from the pixels belonging to the row R0 after the exposure period ends, the address transistor <NUM> of the row R0 is turned on. Accordingly, pixel signals corresponding to the amount of charges accumulated in the charge accumulation region during the exposure period are output to the vertical signal line <NUM>. Following readout of the pixel signals, the reset transistor <NUM> may be turned on to reset the pixels. After readout of the pixel signals, the address transistor <NUM> (and reset transistor <NUM>) are turned off. After readout of the signal changes from the pixels belonging to each of the rows on the pixel array PA, the differences between signals from the signal charges and signals read out during time t0 to t9 are obtained, thereby yielding singals from which static noise has been removed.

Since voltage V3 is applied to the opposing electrode <NUM> during the non-exposure period, the photoelectric conversion layer <NUM> of the photoelectric conversion unit <NUM> is in a state where bias voltage within the third voltage range is applied thereto. Accordingly, further accumulation of signal charges to the charge accumulation region hardly occurs even if light enters the photoelectric conversion layer <NUM>. Accordingly, occurrence of noise due to inclusion of unintended changes is suppressed.

An arrangement may be conceived where the exposure period is ended by applying voltage, which has an inverted polarity of the above-described voltage Ve, to the opposing electrode <NUM>, from the perspective of suppressing further accumulation of signal charges to the charge accumulation region. However, simply inverting the polarity of the voltage applied to the opposing electrode <NUM> may cause movement of already-accumulated signal charges to the opposing electrode <NUM> via the photoelectric conversion layer <NUM>. Movement of signal charges to the opposing electrode <NUM> via the photoelectric conversion layer <NUM> will be observed as black spots in the acquired image. That is to say, movement of signal charges from the charge accumulation region to the opposing electrode <NUM> via the photoelectric conversion layer <NUM> can become the cause of negative parasitic sensitivity.

In this example, since the voltage applied to the opposing electrode <NUM> is changed to voltage V3 again after the exposure period has ended, the photoelectric conversion layer <NUM>, after accumulation of signal charges to the charge accumulation region, is in a state where the bias voltage in the third voltage range is applied. In the state where bias voltage in the third voltage range is applied, signal charges already accumulated in the charge accumulation region can be suppressed from moving to the opposing electrode <NUM> via the photoelectric conversion layer <NUM>. In other words, signal changes accumulated during the exposure period can be held in the charge accumulation region by application of the bias voltage in the third voltage range to the photoelectric conversion layer <NUM>. That is to say, occurrence of negative parasitic sensitivity due to loss of signal charges from the charge accumulation region can be suppressed.

Thus, the starting and ending of the exposure period is controlled by voltage Vb applied to the opposing electrode <NUM> in the embodiment of the present disclosure. That is to say, functions of a global shutter can be realized by the embodiment of the present disclosure without providing transfer transistors and so forth within each unit pixel cell <NUM>. An electronic shutter is executed in the embodiment of the present disclosure by controlling the voltage Vb without transferring signal charges via a transfer transistor, so higher speed operations can be realized. Also, the transfer transistor and the like do not have to be provided within each unit pixel cell <NUM>, which is advantageous in miniaturization of pixels.

In the example of operations described with reference to <FIG>, one exposure period is set in common for all pixels within <NUM> V period, and one image is acquired based on signal charges accumulated within that exposure period. In such operations, the total amount of time needed to acquire pixel signals necessary for forming a final image, that is, one frame worth of image can be said to be approximately equal to (<NUM> V period) + (number of rows in pixel array PA) × (readout time of signals) (where "x" means multiplication). The total amount of time needed to acquire pixel signals necessary for forming one frame worth of image will be referred to as "one frame period" in the present specification. In the example illustrated in <FIG>, the readout period for signals is equally set to one H period for each of the rows in the pixel array PA, so one frame period can be said to be (1V + <NUM> × <NUM>).

In the example illustrated in <FIG>, one exposure period is set in common for all pixels in one frame period. However, multiple exposure periods may be set in common for all pixels in one frame period. In other words, multiple exposure may be performed, with one frame image finally being formed. The path of an object that has moved during one frame period (hereinafter may be referred to as "moving body") can be recorded during the recording of one frame in multiple exposure. Multiple exposure is useful in analysis of moving bodies and analysis of high-speed phenomena. Hereinafter, an image formed based on pixel singals obtained by executing multiple exposure will be referred to as a "multiple-exposure image".

<FIG> schematically illustrates an example of an imaging system configured to be able to form multiple-exposure images. The imaging system <NUM> exemplified in <FIG> schematically includes a camera unit <NUM> and a display unit <NUM>. The camera unit <NUM> and display unit <NUM> may be two parts of a single device, or each may be independent and separate devices. In the configuration exemplified in <FIG>, the camera unit <NUM> has an optical system <NUM>, an imaging device <NUM>, a system controller <NUM>, and an image formation circuit <NUM>. The display unit <NUM> includes a signal processing circuit <NUM> and a display device <NUM>.

The optical system <NUM> of the camera unit <NUM> includes a diaphragm, an image stabilization lens, zoom lens, focusing lens, and so forth. The number of lenses that the optical system <NUM> has is decided as appropriate in accordance with the functions that are required. The system controller <NUM> controls the various parts of the camera unit <NUM>. The system controller <NUM> typically is a semiconductor integrated circuit such as a CPU or the like, and sends out control singals to a lens driving circuit in the optical system <NUM>, for example. The system controller <NUM> in this example also controls the operations of the imaging device <NUM>. For example, the system controller <NUM> controls driving of the vertical scan circuit <NUM>. Switching of voltage applied from the voltage supply circuit <NUM> to the sensitivity control line <NUM> may be executed based on control by the system controller <NUM>. The system controller <NUM> may include one or more memory. The image formation circuit <NUM> is configured to form a multiple-exposure image based on output of the imaging device <NUM>. The image formation circuit <NUM> may be a DSP (Digital Signal Processor), FPGA (field-programmable gate array), or the like, for example. The image formation circuit <NUM> may include memory. The operations of the image formation circuit <NUM> may be controlled by the system controller <NUM>. An example of formation of a multiple-exposure image will be described later.

The image formation circuit <NUM> has an output buffer <NUM> in the configuration exemplified in <FIG>. The image formation circuit <NUM> outputs data of a multiple-exposure image to the display unit <NUM> via the output buffer <NUM>. The data output from the image formation circuit <NUM> typically is RAW data, that is <NUM> bit wide, for example. Data output from the image formation circuit <NUM> may be data compressed confirming to the H. <NUM> standard, for example.

The signal processing circuit <NUM> of the display unit <NUM> receives output from the image formation circuit <NUM>. The output from the image formation circuit <NUM> may be temporarily saved in an external recording medium configured to be detachably connected to the camera unit <NUM> (e.g., flash memory). That is to say, output from the image formation circuit <NUM> may be handed to the display unit <NUM> via the external recording medium.

The signal processing circuit <NUM> performs processing such as gamma correction, color interpolation, spatial interpolation, auto white valance, and so forth. The signal processing circuit <NUM> typically is a DSP, ISP (Image Signal Processor), or the like. The display device <NUM> of the display unit <NUM> is a liquid crystal display, organic EL (electroluminescence) display, or the like. The display device <NUM> displays images based on output signals from the signal processing circuit <NUM>. The display unit <NUM> may be a personal computer, smartphone, or the like.

An example of forming a multiple-exposure image will be described below with reference to <FIG>.

<FIG> is a diagram for describing an example of forming a multiple-exposure image. Exposure is executed multiple times in the formation of one frame worth of a multiple-exposure image. First, resetting of pixels belonging to the rows of row R0 through row R7 and readout of pixel signals in accordance with the vertical synchronization signal Vss is sequentially executed in increments of rows, as illustrated in <FIG> (time t00). The voltage supply circuit <NUM> (see <FIG>) applies voltage V3 such that the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> falls within the above-described third voltage range.

Next, the voltage applied to the opposing electrode <NUM> is switched to voltage Ve1, thereby starting the exposure period of all pixels in the pixel array PA in common. The voltage Ve1 is a voltage where the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> falls within the above-described first voltage range, for example. Applying the voltage Ve1 to the opposing electrode <NUM> causes one of positive and negative charges (signal charges) generated by photoelectric conversion to be accumulated in the charge accumulation region. The exposure period ends by the voltage supply circuit <NUM> switching the voltage applied to the opposing electrode <NUM> to voltage V3 again.

Next, readout of pixel signals of pixels belonging to the rows of row R0 through row R7 in accordance with the vertical synchronization signal Vss is sequentially executed in increments of rows (time t01). Accordingly image data corresponding to the exposure period between time t00 and time t01 is acquired. The image data acquired at this time is temporarily saved in memory of the image formation circuit <NUM> (see <FIG>), for example. In this example, resetting of the pixels belonging to the rows of row R0 through row R7 is performed again after readout of the pixel signals.

After executing the second reset, the voltage applied to the opposing electrode <NUM> is switched to voltage Ve2, thereby starting the second exposure period of all pixels in the pixel array PA in common. The second exposure period ends by the voltage supply circuit <NUM> switching the voltage applied to the opposing electrode <NUM> to voltage V3 again. After the second exposure period has ended, readout of pixel signals of pixels belonging to the rows of row R0 through row R7 is sequentially executed in increments of rows (time t02), whereby image data corresponding to the second exposure period is acquired. The point of the image data acquired at this time being temporarily saved in memory of the image formation circuit <NUM> for example, and the point of resetting of the pixels belonging to the rows of row R0 through row R7 being performed again after readout of the pixel signals, are the same as acquisition of image data corresponding to the first exposure period.

Thereafter, the same operations are repeated for a desired number of times. This yields multiple image data corresponding to the exposure periods. The image formation circuit <NUM> overlays these multiple image data, thereby forming a multiple-exposure image.

Voltages of mutually different magnitudes may be supplied from the voltage supply circuit <NUM> to the opposing electrode <NUM> for each of the exposure periods, during the acquisition of multiple image data to form a multiple-exposure image, as illustrated in <FIG>. The voltage supply circuit <NUM> applies voltages Ve1, Ve2, and Ve3, to the opposing electrode <NUM> over the multiple exposure periods in the example illustrated in <FIG>. Ve1 < Ve2 < Ve3 is satisfied here. In a multiple-exposure image, an image of a subject that moves during one frame period appears at different positions in the image. Each of the images of the moving body appearing in the multiple-exposure image can be imparted with change in display properties by changing the bias voltage applied to the photoelectric conversion layer <NUM> for each exposure period, as in the example described here. For example, the lightness may be changed among each of the images of the moving body appearing in the multiple-exposure image. Display attributes changed by change in bias voltage for each exposure period typically are at least one of lightness and color (hue or chroma).

<FIG> illustrate together an exemplary multiple-exposure image acquired by the imaging system <NUM>, and images each including one image of a moving body that have been extracted in time series from the multiple-exposure image. <FIG> is an example of five exposure periods being included in one frame period.

In a multiple-exposure image obtained by changing the bias voltage applied to the photoelectric conversion layer <NUM> for each exposure period, as illustrated to the left side in <FIG>, the display attributes are different for each of the images of the moving body. Accordingly, a string of multiple images indicating the way in which the moving body has moved can be constructed from the multiple-exposure image, as illustrated to the right side in <FIG>. Accordingly, overlaying multiple image data obtained by changing bias voltage during the exposure periods to form a multiple-exposure image enables information regarding the way in which the moving body has moved during the one frame period (path, change in speed, etc.) to be included in the multiple-exposure image. According to this photography method, increase in the amount of data can be suppressed as a case of sending multiple image data corresponding to each of the exposure periods. Note that change in voltage supplied by the voltage supply circuit <NUM> during the exposure periods may be monotonous increase as illustrated in <FIG>, monotonous decrease, or random.

An image of an identifier indicating temporal change of the position of the moving body may be superimposed on the multiple-exposure image, as illustrated in <FIG>. In the example illustrated in <FIG>, an arrow connecting the centers of the multiple images of the moving body is superimposed as the identifier indicating temporal change of the position of the moving body. In the example illustrated in <FIG>, numerals are superimposed as the identifier indicating temporal change of the position of the moving body. Images of the moving body included in the multiple-exposure image exhibit display properties corresponding to the exposure periods. Accordingly, analyzing the display attributes of the images of the moving body included in the multiple-exposure image enables identifiers to be provided after formation of the multiple-exposure image. Text, symbols, or the like may be used as identifiers instead of numerals. Superimposing of the identifier image may be executed by the image formation circuit <NUM>.

Signal charges accumulated in the charge accumulation region are read out in accordance with each exposure period in the example described with reference to <FIG>. However, an arrangement may be made where exposure is performed multiple times, and signal charges accumulated in the charge accumulation region over one entire frame period are read out to form a multiple-exposure image.

<FIG> is a diagram for describing another example of forming a multiple-exposure image. In the example illustrated in <FIG>, first, resetting of pixels belonging to the rows of row R0 through row R7 and readout of pixel signals in accordance with the vertical synchronization signal Vss is sequentially executed in increments of rows (time t00). Next, voltage Ve1 is applied to the opposing electrode <NUM>, thereby executing the first exposure. After the first exposure period, no readout of pixel signals of the pixels is performed, and voltage Ve2 (Ve2 > Ve1 here) is applied to the opposing electrode <NUM>, thereby executing the second exposure. Accordingly, signal charges corresponding to the second exposure period are further accumulated in the charge accumulation region, in addition to the signal charges already accumulated therein. Such accumulation of signal charges is executed a predetermined number of times, while changing the magnitude of voltage applied to the opposing electrode <NUM> during the exposure periods. The number of exposures is five times in this example, with a voltage Ve5 that is different from both Ve1 and Ve2 (Ve1 < Ve2 <. Ve5) being applied to the opposing electrode <NUM> in the fifth exposure period.

After the fifth exposure period has ended, readout of pixel signals is executed based on the vertical synchronization signal Vss (time t04). That is to say, readout of the total signal charges accumulated over multiple exposure periods from the signal detection circuit is performed once during one frame period. In this way, the image formation circuit <NUM> may form a multiple-exposure image based on conclusively acquired pixel signals, instead of compositing multiple image data corresponding to each exposure period.

The image formation circuit <NUM> is not restricted to a processing circuit dedicated to forming multiple-exposure images. Forming of multiple-exposure images may be realized by a combination of a general-purpose processing circuit and a program describing processing for forming multiple-exposure images. This program may be stored in memory of the image formation circuit <NUM>, memory of the system controller <NUM>, or the like.

Referencing <FIG> again, a global shutter is realized in the embodiment of the present disclosure by different voltages being applied to the opposing electrode <NUM> between exposure periods and non-exposure periods, as described earlier. In a non-exposure period, the voltage supply circuit <NUM> (see <FIG>) supplies voltage such that the bias voltage applied to the photoelectric conversion layer <NUM> falls within the above-described third voltage range, to the opposing electrode <NUM> via the sensitivity control line <NUM>. On the other hand, the potential of the pixel electrode <NUM> during a non-exposure period is decided by the reset voltage Vr supplied to the charge accumulation region that partially includes the pixel electrode <NUM> and impurity region 28d. As described earlier, the reset voltage Vr is supplied to the charge accumulation region via the reset transistor <NUM> that has the impurity region 28d as its drain region (or source region). The reset transistor <NUM> has functions of switching between supply and cutoff of the reset voltage Vr to the charge accumulation region.

In the configuration exemplarily illustrated in <FIG>, the reset voltage Vr is supplied from the reset voltage source <NUM> (see <FIG>) to the impurity region <NUM> that is the source region (or drain region) of the reset transistor <NUM>. The reset voltage source <NUM> and voltage supply circuit <NUM> may be commonalized. Note however, that it is advantageous that the voltage supply circuit <NUM> and reset voltage source <NUM> can independently supply voltages of different magnitudes as described later.

<FIG> is a timing chart for describing exemplary operations of the reset voltage source <NUM> during the reset period. The topmost graph in <FIG> illustrates an example of temporal change of voltage Vb applied from the voltage supply circuit <NUM> to the opposing electrode <NUM>, and the second graph illustrates change in voltage level Vrst at the reset control line <NUM> connected to the gate of the reset transistor <NUM>. The graph third from the top illustrates temporal change of potential φfd of the charge accumulation region. The temporal change of the potential φfd can be said to be representing temporal change of the potential of the pixel electrode <NUM>. Temporal change of potential φ at the opposing electrode <NUM> with the potential of the pixel electrode <NUM> as a reference, is illustrated below the graph illustrating the temporal change of potential φfd.

Voltage Vc applied to the opposing electrode <NUM> in a signal readout period including a reset period therein is typically constant, as illustrated in the graph of voltage Vb in <FIG>. When the voltage of the reset control line <NUM> becomes high level in this state, the potential φfd of the charge accumulation region is reset to Vr by the application of the reset voltage Vr via the reset transistor <NUM>. Accordingly, it would seem that if Vc = Vr is satisfied, which is to say that if the same voltage as the voltage Vc applied to the opposing electrode <NUM> is used as the reset voltage Vr, the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> after resetting would be expected to be <NUM>.

However, in reality, when the voltage of the reset control line <NUM> is set to low level and the reset transistor <NUM> turns off, the potential φfd of the charge accumulation region changes due to coupling between the charge accumulation region and the reset transistor <NUM>. In this example, the potential φfd of the charge accumulation region drops by ΔV (ΔV > <NUM>) due to turning-off of the reset transistor <NUM>. Accordingly, when the voltage Vc applied to the opposing electrode <NUM> during the signal readout period is simply set to be the same as the reset voltage Vr, the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> after resetting may be outside of the third voltage range. A situation where the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> after resetting is outside of the third voltage range will result in parasitic sensitivity.

Accordingly, a voltage greater than the voltage Vc applied to the opposing electrode <NUM> during the signal readout period may be used as the reset voltage Vr. For example, using a voltage where ΔV is added to the voltage Vc applied to the opposing electrode <NUM> as the reset voltage Vr, taking into consideration the voltage drop at the charge accumulation region due to coupling, enables the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> after resetting to be brought nearer to <NUM>, and sensitivity due to electric coupling to be cancelled out.

The specific value of ΔV depends primarily on the characteristics of the reset transistor <NUM> (typically the parasitic capacitance between source and gate), and the value can be known beforehand. For example, ΔV may be measured before shipping a product, and the obtained ΔV may be written to memory (e.g., ROM) connected to the system controller <NUM> (see <FIG>), for example. The system controller <NUM> can correct the magnitude of the reset voltage Vr supplied from the reset voltage source <NUM> based on the value of ΔV, by referencing the ΔV stored in memory. Alternatively, the circuit configuration of the reset voltage source <NUM> may be adjusted in accordance with the value of ΔV, so that the output voltage is the desired voltage. Voltage supplied from the voltage supply circuit <NUM> to the opposing electrode <NUM> may also be corrected, either instead of correcting the reset voltage Vr supplied from the reset voltage source <NUM> or along with correction of the reset voltage Vr. Note however, that correction of the reset voltage Vr is more advantageous than correction of voltage supplied from the voltage supply circuit <NUM> to the opposing electrode <NUM>, with regard to the point that correction can be performed for each pixel. Such calibration of reset voltage Vr (and/or voltage supplied to the opposing electrode <NUM>) may be executed before shipping of the imaging device <NUM>, or may be executed by the user of the imaging device <NUM>.

In a case where the reset transistor <NUM> is a P-channel transistor, the potential φfd of the charge accumulation region rises by ΔV due to turning-off of the reset transistor <NUM>, as illustrated in <FIG>. Accordingly, in a case of using a P-channel transistor for the reset transistor <NUM>, a voltage smaller than the voltage Vc applied to the opposing electrode <NUM> in the signal readout period may be used as the reset voltage Vr.

In the example illustrated in <FIG> and <FIG>, the potential φ of the opposing electrode <NUM>, with the potential of the pixel electrode <NUM> as a reference, is outside of the third voltage range, in the period before the reset period. The voltage Vb applied from the voltage supply circuit <NUM> to the opposing electrode <NUM> does not need to be a voltage where the potential difference between the pixel electrode <NUM> and opposing electrode <NUM> is within the third voltage range through the entire non-exposure period, as illustrated in these examples. The potential φ of the opposing electrode <NUM> with the potential of the pixel electrode <NUM> as a reference may be outside of the third voltage range before resetting the pixels.

Thus, using a corrected voltage as the reset voltage Vr enables occurrence of parasitic sensitivity due to electrical coupling to be suppressed. If the correction value used at this time is too great, a great potential difference will occur between the pixel electrode <NUM> and the opposing electrode <NUM>, and there is a possibility of charges in the charge accumulation region flowing to the opposing electrode <NUM> via the photoelectric conversion layer <NUM>. In other words, this is a risk of backflow of charge via the photoelectric conversion layer <NUM>. Accordingly, it is advantageous that the absolute value of the difference between the reset voltage Vr and the voltage Vc that the voltage supply circuit <NUM> applies to the opposing electrode <NUM> is smaller than the breakdown voltage of the photoelectric conversion layer <NUM>. For example, in a case where the reset transistor <NUM> is an N-channel transistor, it is advantageous that the reset voltage Vr does not exceed the voltage Vc. The breakdown voltage of the photoelectric conversion layer <NUM> can be defined as a voltage at which the photoelectric conversion layer <NUM> loses its function due to charges in the charge accumulation region flowing from the pixel electrode <NUM> to the opposing electrode <NUM> via the photoelectric conversion layer <NUM>. Alternatively, it is advantageous that the absolute value of the difference between the reset voltage Vr and the voltage Vc that the voltage supply circuit <NUM> applies to the opposing electrode <NUM> is smaller than the input voltage to the signal detection circuit <NUM> (typically VDD).

<FIG> illustrates a modification of the imaging device <NUM>. In the configuration exemplarily illustrated in <FIG>, the semiconductor substrate <NUM> has a substrate voltage supply circuit <NUM> that supplies a predetermined substrate voltage Vs. The substrate voltage Vs supplied from the substrate voltage supply circuit <NUM> is voltage that is different from <NUM> V.

Setting the reset voltage Vr to a voltage near <NUM> V enables the voltage Vc applied from the voltage supply circuit <NUM> to the opposing electrode <NUM> to be <NUM> V, i.e., enables the opposing electrode <NUM> to serve as a ground, so the circuit configuration of the imaging device <NUM> can be further simplified. However, if the reset voltage Vr is <NUM> V for example, the signal detection transistor <NUM> will not function as a source-follower, so signal voltage cannot be read out.

In the configuration exemplified in <FIG>, substrate voltage Vs that is different from <NUM> V is applied to the semiconductor substrate <NUM>. For example, a negative voltage is applied to the semiconductor substrate <NUM> as substrate voltage Vs, thereby shifting the substrate potential. Shifting the substrate potential enables both suppression of dark current and linearity at the signal detection circuit <NUM> to be realized, even in a case where the reset voltage Vr, and the voltage Vc applied from the voltage supply circuit <NUM> to the opposing electrode <NUM>, are <NUM> V. The substrate voltage supply circuit <NUM> may be commonalized with the above-described voltage supply circuit <NUM> and/or reset voltage source <NUM>. An arrangement where the voltage Vc that is applied from the voltage supply circuit <NUM> to the opposing electrode <NUM> is positive voltage enables the same advances as a case where the reset voltage Vr and voltage Vc are set to <NUM> V to be obtained, while avoiding application of negative voltage to the semiconductor substrate <NUM>.

As described above, according to the embodiment of the present disclosure, controlling the voltage applied to the opposing electrode <NUM> enables accumulation and storage of charges to the charge accumulation region to be controlled. Thus, a global shutter function can be realized with a simpler device structure.

Various other modifications besides the above-described examples can be made to the imaging device according to the embodiment of the present disclosure. For example, global shutter driving and rolling shutter driving may be switched in accordance with the subject. In rolling shutter driving, the voltage that the voltage supply circuit <NUM> applies to the opposing electrode <NUM> can be fixed to voltage Ve for both exposure period and non-exposure period. The exposure period can be stipulated here by the period from the time of resetting the charge accumulation node <NUM> to the time of readout of signals.

Each of the above-described signal detection transistor <NUM>, address transistor <NUM>, and reset transistor <NUM>, may be N-channel MOS, or P-channel MOS. There is no need for all of these to be unified to N-channel MOS or P-channel MOS. Bipolar transistors may be used as the signal detection transistor <NUM> and/or address transistor <NUM>, besides field-effect transistors.

Claim 1:
An imaging device comprising:
unit pixel cells (<NUM>) each including a first electrode (<NUM>), a second electrode (<NUM>) facing the first electrode (<NUM>), a photoelectric conversion layer (<NUM>) between the first electrode (<NUM>) and the second electrode (<NUM>), a charge accumulation region (<NUM>) electrically connected to the first electrode (<NUM>), and a signal detection circuit (<NUM>) electrically connected to the charge accumulation region (<NUM>); and
a voltage supply circuit (<NUM>) electrically connected to the second electrode (<NUM>), the voltage supply circuit (<NUM>) supplying a first voltage to the second electrode (<NUM>) in an exposure period that is a period for accumulating charges generated by photoelectric conversion in the charge accumulation region (<NUM>), the voltage supply circuit (<NUM>) supplying a second voltage (Vc) that is different from the first voltage to the second electrode (<NUM>) in a non-exposure period, wherein
the unit pixel cells (<NUM>) each include a reset transistor (<NUM>) that is electrically connected to the charge accumulation region (<NUM>) and a reset voltage supply circuit (<NUM>) supplying a reset voltage (Vr),
the reset transistor (<NUM>) switching between supply and cutoff of the reset voltage (Vr) in the non-exposure period for initializing the charge accumulation region (<NUM>), and
the start and end of the exposure period is common to the unit pixel cells (<NUM>),
characterized in that
in the non-exposure period, a potential difference (ΔV) between the first electrode (<NUM>) and the second electrode (<NUM>) when the reset voltage (Vr) is supplied is greater than the potential difference (ΔV) between the first electrode (<NUM>) and the second electrode (<NUM>) after the reset voltage (Vr) is cut off, wherein
the reset transistor (<NUM>) is an n-channel field-effect transistor, and the reset voltage (Vr) is greater than the second voltage (Vc), or
the reset transistor (<NUM>) is a p-channel field-effect transistor, and the reset voltage (Vr) is smaller than the second voltage (Vc).