Patent Description:
The imaging apparatus is equipped with an analog-to-digital converter that converts an analog signal (pixel signal) output from a pixel into a digital signal, and a successive approximation resistor (SAR) analog-to-digital converter is used as the analog-to-digital converter (see, for example, Patent Document <NUM>). <CIT> is directed towards analogue-to-digital conversion of an image signal especially in low lighting conditions and provides a digital converting unit and an addition circuit integrating converted pieces of digital values. International Patent Application Publication <CIT> is directed to improving reading speed during analog-to-digital conversion using a comparator which compares the pixel signals to predetermined reference signals.

A successive approximation register analog-to-digital converter is superior to a so-called single-slope analog-to-digital converter in being operable at higher speed and with lower power consumption. A column signal processing system including the successive approximation register analog-to-digital converter is desired to be operated at higher speed and with lower power consumption.

An object of the present disclosure is to provide an imaging apparatus in which a column signal processing system includes a successive approximation register analog-to-digital converter capable of operating at higher speed and with lower power consumption, and an electronic device including the imaging apparatus.

According to a first aspect, the present invention provides an imaging apparatus according to independent claim <NUM>. According to a second aspect, the present invention provides an electronic device according to independent claim <NUM>. Further aspects of the present invention are set forth in the dependent claims. The description and drawings provide further information.

Hereinafter, modes for carrying out the technology according to the present disclosure (hereinafter described as "embodiment") will be described in detail with reference to the drawings. The technology according to the present disclosure is not limited to the embodiments, and various numerical values and the like in the embodiments are examples. In the following description, the same reference signs will be used for the same elements or elements having the same functions, and redundant description will be omitted. Note that the description will be made in the following order.

An imaging apparatus and an electronic device of the present disclosure can have a configuration in which a column amplifier unit includes an amplifier to which a potential of the signal line is input to a non-inverting input terminal, a first switch having one end connected to an output terminal of the amplifier and another end connected to an inverting input terminal of the amplifier, a second switch having one end connected to an output terminal of the amplifier, a first capacitive element having one end connected to another end of the second switch and another end connected to the another end of the first switch and the inverting input terminal of the amplifier, a second capacitive element connected between the another end of the first capacitive element and the inverting input terminal of the amplifier and a base potential node, and a third switch having one end connected to the another end of the second switch and the one end of the first capacitive element, the third switch having another end to which a base voltage is applied.

The imaging apparatus and the electronic device of the present disclosure including the preferred configuration described above can have a configuration in which in the column amplifier unit, when the reset component is input, the first switch is set to a closed state to charge the reset component to the first capacitive element and the second capacitive element, and the third switch is set to a closed state to take in the local base voltage, next, the first switch and the third switch are set to an open state, the second switch is set to a closed state, and a non-inverting amplifier circuit is configured by the first capacitive element, the second capacitive element, and the amplifier, and when the signal component is input, feedback is applied for a voltage at a common connection node between the first capacitive element and the second capacitive element to be identical to a voltage of the signal component.

In addition, the imaging apparatus and the electronic device of the present disclosure including the preferred configuration described above can have a configuration in which, for one successive approximation register analog-to-digital converter of the successive approximation register analog-to-digital conversion unit, potentials of a plurality of the signal lines are each multiplexed and processed through a plurality of column amplifiers corresponding to the plurality of signal lines and the capacitance unit. Furthermore, the successive approximation register analog-to-digital converter can be configured to perform the conversion processing only when the reset component is input and stand by when the signal component is input, or perform the conversion processing not only when the reset component is input but also when the signal component is input.

In addition, in the imaging apparatus and the electronic device of the present disclosure including the preferable configuration described above, the potentials of the plurality of signal lines can be divided into potentials of two systems of signal lines, and the capacitance unit can include three capacitive elements. Then, the three capacitive elements of the capacitance unit can be evenly used for the potentials of two systems of signal lines.

Furthermore, in the imaging apparatus and the electronic device of the present disclosure including the preferable configuration described above, in a column signal processing system including the column amplifier unit, the capacitance unit, and the successive approximation register analog-to-digital conversion unit, the capacitance unit and subsequent portions can have a configuration of a differential circuit. In addition, each of the column amplifiers of the column amplifier unit can include a current reuse column amplifier that performs voltage amplification by using a bias current of each of the signal lines.

Furthermore, in the imaging apparatus and the electronic device of the present disclosure including the preferable configuration described above, the capacitance unit can include a capacitance multiplexer. In addition, the capacitance unit can hold the pixel signal by sampling with a switched capacitor.

First, a basic configuration of an imaging apparatus to which the technology according to the present disclosure is applied will be described. Here, a complementary metal oxide semiconductor (CMOS) image sensor, which is a type of X-Y address imaging apparatus, will be described as an example of the imaging apparatus. The CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process.

<FIG> is a block diagram depicting an outline of a basic configuration of a CMOS image sensor as an example of an imaging apparatus to which the technology according to the present disclosure is applied.

A CMOS image sensor <NUM> of the present example includes a pixel array unit <NUM> and a peripheral circuit unit of the pixel array unit <NUM>. The pixel array unit <NUM> is formed by two-dimensionally arranging pixels (pixel circuits) <NUM> including photoelectric conversion elements in a row direction and a column direction, that is, in a matrix. Here, the row direction refers to an arrangement direction of pixels <NUM> in a pixel row, and the column direction refers to an arrangement direction of the pixels <NUM> in a pixel column. The pixels <NUM> perform photoelectric conversion to generate and accumulate a photoelectric charge corresponding to an amount of received light.

The peripheral circuit unit of the pixel array unit <NUM> includes, for example, a row selection unit <NUM>, a constant current source unit <NUM>, a column amplifier unit <NUM>, an analog-to-digital conversion unit <NUM>, a horizontal transfer scanning unit <NUM>, a signal processing unit <NUM>, a timing control unit <NUM>, and the like.

In the pixel array unit <NUM>, a pixel control line <NUM> (<NUM><NUM> to <NUM>m) is wired along the row direction for each pixel row with respect to a pixel array in a matrix. Furthermore, a signal line <NUM> (<NUM><NUM> to <NUM>n) is wired along the column direction for each pixel column. The pixel control line <NUM> transmits a drive signal for performing driving when a signal is read from the pixels <NUM>. In <FIG>, the pixel control line <NUM> is illustrated as one wire, but is not limited to one. One end of the pixel control line <NUM> is connected to an output end corresponding to each row of the row selection unit <NUM>.

Description will be made of each component of the peripheral circuit unit of the pixel array unit <NUM>, that is, the row selection unit <NUM>, the constant current source unit <NUM>, the column amplifier unit <NUM>, the analog-to-digital conversion unit <NUM>, the horizontal transfer scanning unit <NUM>, the signal processing unit <NUM>, the timing control unit <NUM>, and the like.

The row selection unit <NUM> includes a shift register, an address decoder, and the like, and controls scanning of a pixel row and an address of the pixel row when selecting each pixel <NUM> of the pixel array unit <NUM>. Although a specific configuration of the row selection unit <NUM> is not illustrated, the row selection unit <NUM> generally includes two scanning systems of a read scanning system and a sweep scanning system.

In order to read a pixel signal from the pixel <NUM>, the read scanning system sequentially selects and scans the pixel <NUM> of the pixel array unit <NUM> row by row. The pixel signal read from the pixel <NUM> is an analog signal. The sweep scanning system sweep scans a read row to be read-scanned by the read scanning system prior to the read scanning by a time corresponding to a shutter speed.

By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion elements of the pixels <NUM> in the read row, and thus the photoelectric conversion elements are reset. Then, by sweeping out (resetting) unnecessary charges by the sweep scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding photoelectric charges of the photoelectric conversion element and newly starting exposure (starting accumulation of photoelectric charge).

The constant current source unit <NUM> includes a plurality of load current sources I (see <FIG>) each including, for example, a MOS transistor and connected to each of the signal lines <NUM><NUM> to <NUM>n for each pixel column, and supplies a bias current to each pixel <NUM> of the pixel row selectively scanned by the row selection unit <NUM> through each of the signal lines <NUM><NUM> to <NUM>n.

The column amplifier unit <NUM> includes a set of column amplifiers provided corresponding to each of the signal lines <NUM><NUM> to <NUM>n for each pixel column. Then, each column amplifier of the column amplifier unit <NUM> amplifies the pixel signal read from each pixel <NUM> of the pixel array unit <NUM> and supplied through the signal line <NUM><NUM> to <NUM>n, and supplies the amplified pixel signal to the analog-to-digital conversion unit <NUM>.

The analog-to-digital conversion unit <NUM> is a column-parallel analog-to-digital conversion unit including a set of a plurality of analog-to-digital converters (provided for each pixel column, for example) provided corresponding to the pixel columns of the pixel array unit <NUM>. The analog-to-digital conversion unit <NUM> converts an analog pixel signal output through each of the signal lines <NUM><NUM> to <NUM>n for each pixel column and amplified by the column amplifier unit <NUM> into a digital pixel signal.

The horizontal transfer scanning unit <NUM> includes a shift register, an address decoder, and the like, and controls scanning of a pixel column and an address of the pixel column when a signal of each pixel <NUM> of the pixel array unit <NUM> is read. Under the control of the horizontal transfer scanning unit <NUM>, the pixel signal converted into the digital signal by the analog-to-digital conversion unit <NUM> is read to a horizontal transfer line L in units of pixel columns.

The signal processing unit <NUM> performs predetermined signal processing on the digital pixel signal supplied through the horizontal transfer line L to generate two-dimensional image data. For example, the signal processing unit <NUM> performs digital signal processing such as correction of a vertical line defect or a point defect, parallel-to-serial conversion, compression, encoding, addition, averaging, intermittent operation, and the like. The signal processing unit <NUM> outputs the generated image data to a subsequent device as an output signal of the CMOS image sensor <NUM>.

The timing control unit <NUM> generates various timing signals, clock signals, control signals, and the like, and performs drive control of the row selection unit <NUM>, the constant current source unit <NUM>, the column amplifier unit <NUM>, the analog-to-digital conversion unit <NUM>, the horizontal transfer scanning unit <NUM>, the signal processing unit <NUM>, and the like on the basis of the generated signals.

<FIG> is a circuit diagram depicting an example of a circuit configuration of the pixel (pixel circuit) <NUM>. The pixel <NUM> includes, for example, a photodiode <NUM> as a photoelectric conversion element. The pixel <NUM> includes a transfer transistor <NUM>, a reset transistor <NUM>, an amplification transistor <NUM>, and a selection transistor <NUM> in addition to the photodiode <NUM>.

Examples of the four transistors of the transfer transistor <NUM>, the reset transistor <NUM>, the amplification transistor <NUM>, and the selection transistor <NUM> include an N-channel MOS field effect transistor (FET), for example. However, a combination of conductive types of the four transistors <NUM> to <NUM> exemplified here is merely an example, and this combination is not necessary.

For the pixel <NUM>, as the above-described pixel control line <NUM>, a plurality of pixel control lines is wired in common to each pixel <NUM> of the same pixel row. The plurality of pixel control lines is connected to an output end corresponding to each pixel row of the row selection unit <NUM> in units of pixel rows. The row selection unit <NUM> appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of pixel control lines.

The photodiode <NUM> has an anode electrode connected to a low-potential side power supply (for example, ground), photoelectrically converts received light into photoelectric charge (here, photoelectrons) of a charge amount corresponding to an amount of the light, and accumulates the photoelectric charge. A cathode electrode of the photodiode <NUM> is electrically connected to a gate of the amplification transistor <NUM> via the transfer transistor <NUM>. Here, a region where the gate of the amplification transistor <NUM> is electrically connected is a floating diffusion (floating diffusion region/impurity diffusion region) FD. The floating diffusion FD is a charge-voltage conversion unit that converts a charge into a voltage.

The transfer signal TRG that activates a high level (for example, VDD level) is supplied from the row selection unit <NUM> to a gate of the transfer transistor <NUM>. The transfer transistor <NUM> becomes conductive in response to the transfer signal TRG, and transfers the photoelectric charge photoelectrically converted by the photodiode <NUM> and accumulated in the photodiode <NUM> to the floating diffusion FD.

The reset transistor <NUM> is connected between a node of the high-potential side power supply voltage VDD and the floating diffusion FD. The reset signal RST that activates a high level is provided from the row selection unit <NUM> to a gate of the reset transistor <NUM>. The reset transistor <NUM> becomes conductive in response to the reset signal RST, and resets the floating diffusion FD by discarding the charge of the floating diffusion FD to the node of the voltage VDD.

The amplification transistor <NUM> has a gate connected to the floating diffusion FD and a drain connected to the node of the high-potential side power supply voltage VDD. The amplification transistor <NUM> serves as an input unit of a source follower that reads a signal obtained by photoelectric conversion in the photodiode <NUM>. That is, a source of the amplification transistor <NUM> is connected to the signal line <NUM> via the selection transistor <NUM>. Then, the amplification transistor <NUM> and the load current source I connected to one end of the signal line <NUM> constitute a source follower that converts the voltage of the floating diffusion FD into a potential of the signal line <NUM>.

The selection transistor <NUM> has a drain connected to the source of the amplification transistor <NUM> and a source connected to the signal line <NUM>. The selection signal SEL that activates a high level is provided from the row selection unit <NUM> to a gate of the selection transistor <NUM>. The selection transistor <NUM> becomes conductive in response to the selection signal SEL, and transmits the signal output from the amplification transistor <NUM> to the signal line <NUM> with the pixel <NUM> in a selected state.

Note that, in the circuit example described above, as the circuit configuration of the pixel <NUM>, a 4Tr configuration including the transfer transistor <NUM>, the reset transistor <NUM>, the amplification transistor <NUM>, and the selection transistor <NUM>, that is, including four transistors (Tr) has been described as an example, but this circuit configuration is not necessary. For example, the selection transistor <NUM> may be omitted, and a 3Tr configuration may be adopted in which the amplification transistor <NUM> has a function of the selection transistor <NUM>, or a circuit configuration of 5Tr or more may be adopted in which the number of transistors is increased as necessary.

As a semiconductor chip structure of the CMOS image sensor <NUM> having a configuration described above, a flat semiconductor chip structure and a stacked semiconductor chip structure can be exemplified. In any of the CMOS image sensor <NUM> having the flat semiconductor chip structure and the stacked semiconductor chip structure, when a substrate surface on a side on which a wiring layer is disposed is a front surface (front face), the pixel <NUM> can have a back surface irradiation type pixel structure that captures light emitted from a back surface side on an opposite side of the front surface, or can have a front surface irradiation type pixel structure that captures light emitted from a front surface side. Hereinafter, the flat semiconductor chip structure and the stacked semiconductor chip structure will be described.

<FIG> is a plan view schematically depicting an outline of the flat semiconductor chip structure of the CMOS image sensor <NUM>. As illustrated in <FIG>, the flat semiconductor chip structure has a structure in which a circuit portion around the pixel array unit <NUM> is formed on the same semiconductor chip (semiconductor substrate) <NUM> as the pixel array unit <NUM> in which the pixels <NUM> are arranged in a matrix. Specifically, the row selection unit <NUM>, the constant current source unit <NUM>, the column amplifier unit <NUM>, the analog-to-digital conversion unit <NUM>, the horizontal transfer scanning unit <NUM>, the signal processing unit <NUM>, the timing control unit <NUM>, and the like are formed on the same semiconductor chip <NUM> as the pixel array unit <NUM>.

<FIG> is an exploded perspective view schematically depicting an outline of a stacked chip structure of the CMOS image sensor <NUM>. As illustrated in <FIG>, the stacked semiconductor chip structure is a structure in which at least two semiconductor chips (semiconductor substrates) of a first-layer semiconductor chip <NUM> and a second-layer semiconductor chip <NUM> are stacked. In this stacked structure, the pixel array unit <NUM> is formed on the first-layer semiconductor chip <NUM>. Furthermore, circuit portions such as the row selection unit <NUM>, the constant current source unit <NUM>, the column amplifier unit <NUM>, the analog-to-digital conversion unit <NUM>, the horizontal transfer scanning unit <NUM>, the signal processing unit <NUM>, the timing control unit <NUM> and the like are formed on the second-layer semiconductor chip <NUM>. Then, the first-layer semiconductor chip <NUM> and the second-layer semiconductor chip <NUM> are electrically connected through connection portions (VIA) 44A and 44B such as Cu-Cu connection and the like.

In the CMOS image sensor <NUM> having this stacked structure, the first-layer semiconductor chip <NUM> only needs to have a size (area) enough to form the pixel array unit <NUM>, and thus the size (area) of the first-layer semiconductor chip <NUM> and a size of the entire chip can be reduced. Moreover, since a process suitable for manufacturing the pixel <NUM> can be applied to the first-layer semiconductor chip <NUM> and a process suitable for manufacturing the circuit portion can be applied to the second-layer semiconductor chip <NUM>, there is also an advantage that the process can be optimized in manufacturing the CMOS image sensor <NUM>. In particular, an advanced process can be applied to manufacture the circuit portion.

Note that, here, the stacked structure of a two-layer structure formed by stacking the first-layer semiconductor chip <NUM> and the second-layer semiconductor chip <NUM> has been exemplified, but the stacked structure is not limited to the two-layer structure, and may be a structure of three or more layers. Then, in a stacked structure of three or more layers, circuit portions such as the row selection unit <NUM>, the constant current source unit <NUM>, the column amplifier unit <NUM>, the analog-to-digital conversion unit <NUM>, the horizontal transfer scanning unit <NUM>, the signal processing unit <NUM>, the timing control unit <NUM> and the like can be formed in a distributed manner on the semiconductor chips of the second and subsequent layers.

In the CMOS image sensor <NUM> having the configuration described above, for example, a single-slope analog-to-digital converter has been generally used as the analog-to-digital converter in the analog-to-digital conversion unit <NUM>. Here, the single-slope analog-to-digital converter will be described.

In the single-slope analog-to-digital converter, a signal of an inclined waveform (ramp wave) that linearly changes with a certain inclination is used as a base signal. The single-slope analog-to-digital converter compares an analog pixel signal read from the pixel <NUM> with a base signal of a ramp wave, amplifies and clips a difference between the pixel signal and a base signal to modulate the signal into a phase signal, and then performs sampling to convert the signal into a digital signal. This single-slope analog-to-digital converter has the following problems.

An offset occurs due to a delay during modulation to a phase signal. Therefore, digital correlated double sampling (CDS) for removing fixed pattern noise of the pixel <NUM> is essential, and additional time for two analog-to-digital conversions and auto-zero is required.

When the pixel signal crosses the base signal of the ramp wave, a through current or kickback occurs. Furthermore, time for the crossing depends on a level of the pixel signal, and causes interference with the analog-to-digital converter of other pixel columns.

Since the amplification transistor <NUM> of the pixel <NUM> is used to hold the voltage during analog-to-digital conversion, conversion time limits reading speed of the pixel signal.

Regarding Problem <NUM>, in the single-slope analog-to-digital converter, auto-zero (offset cancellation due to input and output short) of input amplifier is performed to prevent offset. Thus, DC offset can be removed. However, since the base signal of the ramp wave changes with time, AC offset due to a delay cannot be removed. The delay can be reduced by widening a band, but output phase noise increases.

Problem <NUM> is known as a mechanism of an interference phenomenon (streaking) from a bright portion to a dark portion. In the single-slope analog-to-digital converter, when a plurality of pixel columns has the same brightness, switching occurs all at once, and thus an influence of interference increases.

Problem <NUM> is a problem caused by not sampling the potential of the signal line <NUM>. In the amplification transistor <NUM> of the pixel <NUM>, relatively large power is consumed to drive the signal line <NUM> having a large load capacitance. It is therefore not advisable to use the amplification transistor <NUM> only to hold a voltage during analog-to-digital conversion.

In an imaging apparatus (CMOS image sensor as an example) according to a first embodiment of the present disclosure, a successive approximation register (SAR) analog-to-digital converter is used as each analog-to-digital converter of the analog-to-digital conversion unit <NUM>. The successive approximation register analog-to-digital converter can operate at higher speed and with lower power consumption as compared with the single-slope analog-to-digital converter having the various problems described above. In the present embodiment, a column signal processing system including the successive approximation register analog-to-digital converter can be operated at higher speed and with lower power consumption.

<FIG> is a block diagram depicting an outline of a configuration of a CMOS image sensor as an example of an imaging apparatus according to a first embodiment of the present disclosure.

In the CMOS image sensor <NUM> according to the present embodiment, the column amplifier unit <NUM> performs processing (CDS processing) of obtaining a difference between a signal component (so-called D-phase) input from each pixel <NUM> of the pixel array unit <NUM> through the signal line <NUM> and a reset component (so-called P-phase), and outputs the difference as a pixel signal. A capacitance unit <NUM> is provided at a subsequent stage of the column amplifier unit <NUM>.

The capacitance unit <NUM> holds the pixel signal input from the column amplifier unit <NUM> by, for example, sampling with a switched capacitor. A successive approximation register analog-to-digital conversion unit 15A is provided at a subsequent stage of the capacitance unit <NUM>. The successive approximation register analog-to-digital conversion unit 15A includes a plurality of successive approximation register (SAR) analog-to-digital converters capable of operating at higher speed and with low power consumption as compared with the single-slope analog-to-digital converter, and converts an analog pixel signal input from the capacitance unit <NUM> into a digital pixel signal.

In the CMOS image sensor <NUM> according to the present embodiment, each successive approximation register analog-to-digital converter of the successive approximation register analog-to-digital conversion unit 15A performs binary search, and thus is more efficient in principle than a single-slope analog-to-digital converter that performs a sweep when viewed alone. In addition, the number of times of analog-to-digital conversion can be halved by performing the CDS processing that has been conventionally performed by two analog-to-digital conversions in the analog-to-digital converter by the column amplifier unit <NUM> of an analog circuit system. Furthermore, by introducing sampling with a switched capacitor, a potential VSL of the signal line does not need to wait for analog-to-digital conversion, and sampling is always performed all at once regardless of the potential VSL of the signal line <NUM>. Therefore, the influence of interference due to switching is also small.

Hereinafter, description will be made of a specific example of a column signal processing system in the CMOS image sensor <NUM> according to the first embodiment, specifically, a column signal processing system including the column amplifier unit <NUM>, the capacitance unit <NUM>, and the analog-to-digital conversion unit <NUM>.

The first embodiment is an example of an intermittent operation in which the successive approximation register analog-to-digital converter performs conversion processing only during the P-phase in which the reset component is input and stands by during the D-phase in which the signal component is input. <FIG> is a circuit diagram depicting an outline of a configuration of a column signal processing system according to the first embodiment. The column amplifier unit <NUM> includes column amplifiers <NUM> as many as the number of pixel columns provided as the number of pixel columns, and the capacitance unit <NUM> also includes the capacitance multiplexers <NUM> as many as the number of pixel columns.

Here, a configuration will be described as an example in which, for one successive approximation register analog-to-digital converter <NUM> of the successive approximation register analog-to-digital conversion unit 15A, potentials VSL<NUM> to VSL<NUM> of the plurality of signal lines <NUM>, for example, eight signal lines <NUM> are each multiplexed and processed through eight column amplifiers <NUM> and capacitance multiplexers <NUM> corresponding to the eight signal lines <NUM>.

The column amplifier <NUM> includes an amplifier <NUM>, a first switch <NUM>, a second switch <NUM>, a third switch <NUM>, a first capacitive element <NUM>, and a second capacitive element <NUM>. The first capacitive element <NUM> (hereinafter simply described as the "capacitive element <NUM>") has a capacitance value CF, and the second capacitive element <NUM> (hereinafter simply described as the "capacitive element <NUM>") has a capacitance value Cs.

The amplifier <NUM> uses the potential VSL (VSL<NUM> to VSL<NUM>) of the signal line <NUM> as an input of a non-inverting (+) input terminal. The first switch <NUM> (hereinafter simply described as the "switch <NUM>") has one end connected to an output terminal of the amplifier <NUM> and another end connected to an inverting (-) input terminal of the amplifier <NUM>, and performs an on (closed)/off (open) operation in accordance with a polarity (high level/low level) of a switch control signal Sp.

The second switch <NUM> (hereinafter simply described as the "switch <NUM>") has one end connected to the output terminal of the amplifier <NUM>. The capacitive element <NUM> has one end connected to another end of the switch <NUM> and another end connected to the other end of the switch <NUM> and the inverting input terminal of the amplifier <NUM>. The capacitive element <NUM> is connected between the other end of the capacitive element <NUM> and the output terminal of the amplifier <NUM> and a node of a base potential (for example, ground). The switch <NUM> performs an on/off operation in accordance with a polarity of a switch control signal SD.

That is, the switch <NUM>, the capacitive element <NUM>, and the capacitive element <NUM> are connected in series between the output terminal of the amplifier <NUM> and a node of a base potential (for example, ground) in that order. In addition, a common connection node N<NUM> between the capacitive element <NUM> and the capacitive element <NUM> and the other end of the switch <NUM> are electrically connected to each other.

The third switch <NUM> (hereinafter simply described as the "switch <NUM>") has one end connected to a common connection node N<NUM> between the switch <NUM> and the capacitive element <NUM>, and performs an on/off operation in accordance with a polarity of a switch control signal SVR. A local base voltage VR defining zero voltage of an output of the column amplifier <NUM> is applied to another end of the switch <NUM>. That is, the switch <NUM> selectively applies the local base voltage VR to the common connection node N<NUM> between the switch <NUM> and the capacitive element <NUM>.

The capacitance multiplexer <NUM> constituting the capacitance unit <NUM> includes four switches <NUM> to <NUM> and one capacitive element <NUM>, and is configured to perform sampling with a switched capacitor. The capacitive element <NUM> has a capacitance value CIN.

The switch <NUM> has one end connected to an output end of the column amplifier <NUM>, that is, the output terminal of the amplifier <NUM>, and performs an on/off operation in accordance with a polarity of a switch control signal SIN. The switch <NUM> has one end connected to another end of the switch <NUM>, and performs an on/off operation in accordance with a polarity of a switch control signal SVMI0. A specific reference voltage VX is applied to another end of the switch <NUM>. The local base voltage VR may be used as the specific reference voltage VX.

The capacitive element <NUM> has one end connected to the other end of the switch <NUM>. The switch <NUM> has one end connected to another end of the capacitive element <NUM>, and performs an on/off operation in accordance with a polarity of a switch control signal SVM. An intermediate voltage VM used when resetting a capacitor array unit (CDAC) <NUM> of the successive approximation register analog-to-digital converter <NUM> is applied to another end of the switch <NUM>.

The switch <NUM> has one end connected to the other end of the capacitive element <NUM> and the one end of the switch <NUM>, and performs an on/off operation in accordance with a polarity of a switch control signal SSUM0. The switch <NUM> has another end commonly connected among the eight capacitance multiplexers <NUM> corresponding to the potentials VSL<NUM> to VSL<NUM> of the signal line <NUM>, and serves as an output end of the capacitance multiplexer <NUM>.

The successive approximation register analog-to-digital converter <NUM> includes a preamplifier <NUM>, a comparator <NUM>, a SAR logic unit <NUM>, a digital-to-analog converter (DAC) <NUM>, and the capacitor array unit (CDAC) <NUM>.

The preamplifier <NUM> includes an amplifier <NUM> and a switch <NUM>. The amplifier <NUM> uses the analog voltage supplied from the capacitance multiplexer <NUM> as an input of an inverting (-) input terminal, and uses an output common mode reference voltage VCM as an input of a non-inverting (+) input terminal. The switch <NUM> is an auto-zero (offset cancellation by input and output short) switch, is connected between an inverting (-) input terminal and an output terminal of the preamplifier <NUM>, and performs an on/off operation in accordance with a polarity of a switch control signal SAZ.

The comparator <NUM> compares a magnitude of the analog voltage supplied through the preamplifier <NUM> with a magnitude of a comparison base voltage in synchronization with a comparator clock CKI, and supplies a result of the comparison to the SAR logic unit <NUM>.

The SAR logic unit <NUM> includes, for example, an N-bit successive approximation register, stores a comparison result of the comparator <NUM> for each bit in synchronization with the clock CK, and outputs the comparison result as an N-bit digital value DOUT after analog-to-digital conversion.

The digital-to-analog converter <NUM> and the capacitor array unit <NUM> constitute an N-bit capacitive digital-to-analog converter. Then, in this capacitive digital-to-analog converter, the N-bit digital value DOUT output from the SAR logic unit <NUM> is converted into an analog voltage and is applied as an input to an inverting (-) input terminal of the amplifier <NUM>.

Next, a circuit operation of the column signal processing system according to the first embodiment including the column amplifier <NUM>, the capacitance multiplexer <NUM>, and the successive approximation register analog-to-digital converter <NUM> having a configuration described above will be described with reference to a timing chart in <FIG>.

The timing chart in <FIG> illustrates a timing relationship among the potential VSL of the signal line <NUM>, the switch control signals SP and SVR, the switch control signals SD, SIN, and SVM, the switch control signals SVMI0 and SSUM0 to SVMI7 and SSUM7, the clock CK, the switch control signal SAZ, and the comparator clock CKI.

First, the potentials VSL<NUM> to VSL<NUM> of the eight signal lines <NUM> are each input to the corresponding dedicated column amplifiers <NUM>. When the switch control signal SP and the switch control signal SVR are at a high level while each of the potentials VSL<NUM> to VSL<NUM> of the eight signal lines <NUM> is in a state of a reset component (P-phase voltage), the switch <NUM> and the switch <NUM> enter an on (closed) state. Thus, the reset component (P-phase voltage) is charged by the capacitive element <NUM> and the capacitive element <NUM>. At this time, in the voltage at the common connection node N<NUM> between the switch <NUM> and the capacitive element <NUM>, the reset component (P-phase voltage) greatly varies (has low accuracy) depending on the pixel <NUM>, but the local base voltage VR, which is generated on a side of the column amplifier <NUM>, less varies (has high accuracy).

Next, when the switch control signal SP and the switch control signal SVR is at a low level, the switch <NUM> and the switch <NUM> enter an off (open) state, and at the same time, when the switch control signal SD is at a high level, the switch <NUM> enters an on (closed) state. At this time, the capacitive element <NUM>, the capacitive element <NUM>, and the amplifier <NUM> configure a non-inverting amplifier circuit, and the output voltage Vout of the column amplifier <NUM> is substantially the same voltage as the local base voltage VR.

Thereafter, when each of the potentials VSL<NUM> to VSL<NUM> of the eight signal lines <NUM> changes (specifically, descends) to a signal component (D-phase voltage) as a luminance component, feedback is applied so that a voltage at the common connection node N<NUM> between the capacitive element <NUM> and the capacitive element <NUM> becomes the same voltage as the signal component (D-phase voltage). By this series of operations, CDS processing of obtaining a difference between the reset component (P-phase voltage) and the signal component (D-phase voltage) is performed, and the output voltage Vout of the column amplifier <NUM> drops by a voltage amplified to (CF+CS)/CF times the potential VSL of the signal line <NUM>.

The signal component amplified by the column amplifier <NUM> is input to the capacitance multiplexer <NUM> including the same number of capacitive elements <NUM> as the column amplifier <NUM>. In the capacitance multiplexer <NUM>, during the D-phase, the switch control signal SIN and the switch control signal SVM are at a high level. In response to this, the switch <NUM> and the switch <NUM> enter an on state, and thus the intermediate voltage VM is applied to the capacitive element <NUM>. Then, the switch control signal SIN and the switch control signal SVM are at a low level, and in response to this, the switch <NUM> and the switch <NUM> enter an off state. Thus, charges are held in the capacitive element <NUM> having the capacitance value CIN.

Next, during the P-phase, the switch control signal SVMIx (x = <NUM> to <NUM>) and the switch control signal SSUMx (x = <NUM> to <NUM>) sequentially become a high level, and the switch <NUM> and the switch <NUM> are set to an on state. Thus, the charge held in the capacitive element <NUM> is transferred to the successive approximation register analog-to-digital converter <NUM>. The charge is transferred by dividing time of the P-phase into eight. Since the D-phase is used for sampling, the charge can be transferred only in the P-phase.

When the capacitive element <NUM> is connected to an input end of the successive approximation register analog-to-digital converter <NUM> through the switch <NUM>, the comparator clock CKI is input to the comparator <NUM> to start the comparison. The comparison result of the comparator <NUM> is fed back to the digital-to-analog converter <NUM> via the SAR logic unit <NUM>, and is binary-searched so that an input of the preamplifier <NUM> becomes <NUM> V. Finally, almost all the charges accumulated in the capacitive element <NUM> of the capacitance multiplexer <NUM> are transferred to the capacitor array unit (CDAC) <NUM>, and an input of the digital-to-analog converter <NUM> at that time is obtained as an output code.

Note that it is necessary to set the switch <NUM> of the preamplifier <NUM> to an on (closed) state by setting the switch control signal SAZ to a high level and reset the charge of the capacitor array unit (CDAC) <NUM> before the next connection of the capacitive element <NUM>.

As described above, in the circuit operation of the column signal processing system according to the first embodiment, the successive approximation register analog-to-digital converter <NUM> performs the intermittent operation of operating only during the P-phase and standing by without doing anything during the D-phase. In a standby state, the circuit current is stopped so as not to consume power, but a portion that fails to respond at a high-speed cannot be stopped to cause waste. Furthermore, since a power supply current greatly changes between the P-phase and the D-phase, it takes time to stabilize a power supply voltage immediately after recovery.

In addition, in the configuration of the column signal processing system according to the first embodiment, in the capacitance multiplexer <NUM>, the capacitive element <NUM> needs to sample the output of the column amplifier <NUM> in the D-phase, and thus cannot keep holding the charge.

A second embodiment is a modification of the first embodiment, and is an example of a non-intermittent operation in which the successive approximation register analog-to-digital converter performs the conversion processing not only during the P-phase in which the reset component is input but also during the D-phase in which the signal component is input. <FIG> is a circuit diagram depicting an outline of a configuration of a column signal processing system according to a second embodiment.

Assuming that a P-phase period and a D-phase period are approximately the same and the analog-to-digital conversion is performed in half in each phase, in a case where the potentials VSL<NUM> to VSL<NUM> of the eight signal lines <NUM> are each multiplexed and processed, the analog-to-digital conversion is performed four times.

In the column signal processing system according to the second embodiment, as illustrated in <FIG>, the potentials VSL<NUM> to VSL<NUM> of the eight signal lines <NUM> are each divided into the potentials VSL<NUM> to VSL<NUM> of the four signal lines <NUM> in the first half and the potentials VSL<NUM> to VSL<NUM> of the four signal lines <NUM> in the second half and handled.

The analog-to-digital conversion for the potentials VSL<NUM> to VSL<NUM> of the first four signal lines <NUM> is performed during the P-phase, and thus have the same configuration as that in the intermittent operation in the column signal processing system according to the first embodiment. Since the sampling and the analog-to-digital conversion are simultaneously performed for the potentials VSL<NUM> to VSL<NUM> of the four signal lines <NUM> in the latter half during the D-phase, double capacitive elements are prepared, and the capacitive elements are alternately used for each sampling.

Specifically, three systems of circuits that perform sampling by a switched capacitor are provided. A first system is a circuit including a switch <NUM>_A, a switch <NUM>_A, a switch <NUM>_A, a switch <NUM>_A, and a capacitive element <NUM>_A. The switch <NUM>_A, the switch <NUM>_A, and the switch <NUM>_A perform an on/off operation in accordance with polarities of switch control signals SIN0A, SVMIA0, SVMA, and SSUMA0.

A second system is a circuit including a switch <NUM>_B, a switch <NUM>_B, a switch <NUM>_B, a switch <NUM>_B, and a capacitive element <NUM>_B. The switch <NUM>_B, the switch <NUM>_B, and the switch <NUM>_B perform an on/off operation in accordance with polarities of switch control signals SIN1B, SVMIB0, SVMB, and SSUMB0.

A third system is a circuit including a switch <NUM>_C, a switch <NUM>_C, a switch <NUM>_C, a switch <NUM>_C, and a capacitive element <NUM>_C. The switch <NUM>_C, the switch <NUM>_C, and the switch <NUM>_C, and the switch <NUM>_C perform an on/off operation in accordance with polarities of switch control signals SIN1C, SVMIC, SVMC, and SSUMC0.

In the capacitance multiplexer <NUM> of the column signal processing system according to the second embodiment having a configuration described above, during the P-phase, the circuit including the switch <NUM>_A, the switch <NUM>_A, the switch <NUM>_A, the switch <NUM>_A, and the capacitive element <NUM>_A operates for the potentials VSL<NUM> to VSL<NUM> of the four signal lines <NUM> in the first half. During the D-phase, the circuit including the switch <NUM>_B, the switch <NUM>_B, the switch <NUM>_B, the switch <NUM>_B, and the capacitive element <NUM>_B and the circuit including the switch <NUM>_C, the switch <NUM>_C, the switch <NUM>_C, the switch <NUM>_C, and the capacitive element <NUM>_C operate for the potentials VSL<NUM> to VSL<NUM> of the four signal lines <NUM> in the latter half.

A third embodiment is a modification of the second embodiment, and is an example in which three capacitive elements (<NUM>_A, <NUM>_B, and <NUM>_C) of the capacitance unit <NUM> (capacitance multiplexer <NUM>) are evenly used for the potentials VSL<NUM> to VSL<NUM> of the signal lines <NUM> and the potentials VSL<NUM> to VSL<NUM> of the two systems of signal lines <NUM>. <FIG> is a circuit diagram depicting an outline of a configuration of a column signal processing system according to a third embodiment.

In the capacitance multiplexer <NUM> of the column signal processing system according to the third embodiment, two systems of the switch <NUM>_A, the switch <NUM>_B, and the switch <NUM>_C are provided. Then, each of a switch <NUM>_0A, a switch <NUM>_0B, and a switch <NUM>_0C of one system has one end commonly connected to the output end of the column amplifier <NUM> of the potentials VSL<NUM> to VSL<NUM> of the four signal lines <NUM> in the first half, and performs an on/off operation in accordance with polarities of switch control signals SIN0A, SIN0B, and SIN0C.

Furthermore, each of a switch <NUM>_1A, a switch <NUM>_1B, and a switch <NUM>_1C of the other system has one end commonly connected to the output end of the column amplifier <NUM> of the potentials VSL<NUM> to VSL<NUM> of the four signal lines <NUM> in the latter half, and performs an on/off operation in accordance with polarities of switch control signals SIN1A, SIN1B, and SIN1C.

Each of the switch <NUM>_0A and the switch <NUM>_1A has another end commonly connected to an input end of the capacitive element <NUM>_A together with another end of the switch <NUM>_A. Each of the switch <NUM>_0B and the switch <NUM>_1B has another end commonly connected to an input end of the capacitive element <NUM>_B together with another end of the switch <NUM>_B. Each of the switch <NUM>_0C and the switch <NUM>_1C has another end commonly connected to an input end of the capacitive element <NUM>_C together with another end of the switch <NUM>_C.

<FIG> is a timing chart for describing circuit operation of the column signal processing system according to the third embodiment.

The timing chart in <FIG> illustrates a timing relationship among the potential VSL of the signal line <NUM>, the switch control signals SP and SVR, the switch control signals SD, SIN, and SVM, the switch control signals SIN0A and SIN1B, the switch control signals SIN0B and SIN1C, the switch control signals SIN0C and SIN1A, and the switch control signals SVMA, SVMB, and SVMC. The timing chart of <FIG> further illustrates a timing relationship among the switch control signals SVMIA0, SSUMA0 to SVMIA3, and SSUMA3, the switch control signals SVMIB0, SSUMB0 to SVMIB3, and SSUMB3, the switch control signals SVMIC0, SSUMC0 to SVMIC3, and SSUMC3, the clock CK, the switch control signal SAZ, and the comparator clock CKI.

The column amplifier <NUM> outputs a signal in the D-phase. Therefore, sampling in the three capacitive elements (<NUM>_A, <NUM>_B, and <NUM>_C) is performed only in the D-phase, while comparison in the comparator <NUM> is continuously performed in both the P-phase and the D-phase. In an example of the timing chart in <FIG>, in the first D-phase, the potentials VSL<NUM> to VSL<NUM> of the signal line <NUM> are sampled by the capacitive element <NUM>_A, and the potentials VSL<NUM> to VSL<NUM> of the signal line <NUM> are sampled by the capacitive element <NUM>_B.

The potentials VSL<NUM> to VSL<NUM> of the signal line <NUM> are analog-to-digital converted in the immediately subsequent P-phase, and the potentials VSL<NUM> to VSL<NUM> of the signal line <NUM> are analog-to-digital converted in the second D-phase. In the second D-phase, since the capacitive element <NUM>_B is used for analog-to-digital conversion, the output of the column amplifier <NUM> at that time is sampled by the capacitive element <NUM>_C and capacitive element <NUM>_A which are available. At this time, the potentials VSL<NUM> to VSL<NUM> of the signal line <NUM> different from the previous time are sampled in the capacitive element <NUM>_A. Repeating this operation prevents use of the same capacitive element every time for the potential VSL of the specific signal line <NUM>.

In the successive approximation register analog-to-digital converter <NUM>, before every performance of analog-to-digital conversion, the switch <NUM> of the preamplifier <NUM> is set to an on (closed) state to perform auto zero for determining an initial value of the capacitor array unit (CDAC) <NUM>. At this time, the switch <NUM> of the capacitance multiplexer <NUM> is in an off (open) state.

During the auto zero, the capacitor array unit (CDAC) <NUM> is set to an arbitrary reset code, and the reset code at this time is an output code when an input voltage is <NUM> V.

The auto-zero has an effect of canceling the offset of the preamplifier <NUM>, but it should be noted that in this analog-to-digital conversion, the offset cannot be completely canceled since the input capacitance is separated at the time of sampling.

After a lapse of a certain period of time, the switch <NUM> of the preamplifier <NUM> is set to an off (open) state, and the switch <NUM> and the switch <NUM> of the capacitance multiplexer <NUM> are set to an on (closed) state to transfer charges. At the same time, the intermediate voltage VM is applied to all of the capacitor array unit <NUM> (see <FIG>).

After settling, the first pulse of the clock ICK is input to start comparison operation. The clock ICK is input a plurality of times, an analog-to-digital conversion result is determined, and the processing proceeds to the next analog-to-digital conversion. The auto-zero takes more time than settling of the capacitor array unit <NUM>, and thus has a predetermined length. In addition, time from the auto-zero to the first clock ICK is set to a predetermined period.

In the configuration of the column signal processing system according to the second embodiment illustrated in <FIG>, the capacitive element <NUM>_A is always used for sampling the potentials VSL<NUM> to VSL<NUM> of the signal line <NUM>, but the capacitive element <NUM>_B and the capacitive element <NUM>_C are alternately used for sampling the potentials VSL<NUM> to VSL<NUM> of the signal line <NUM>, which may cause a systematic error.

On the other hand, in the configuration of the column signal processing system according to the third embodiment, as is apparent from the circuit operation described above, the three capacitive elements (<NUM>_A, <NUM>_B, and <NUM>_C) are evenly used for the potentials VSL<NUM> to VSL<NUM> of the two systems of signal lines <NUM> and the potentials VSL<NUM> to VSL<NUM> of the signal lines <NUM>. It is therefore possible to avoid occurrence of a systematic error.

A fourth embodiment is an implementation example of the column signal processing system, and is an example in which the capacitance unit <NUM> (capacitance multiplexer <NUM>) and the subsequent portions have a configuration of a differential circuit. <FIG> is a circuit diagram depicting an outline of a configuration of a column signal processing system according to a fourth embodiment.

<FIG> illustrates a base voltage generation unit <NUM> that generates a base voltage used in the column amplifier <NUM>, the capacitance multiplexer <NUM>, and the successive approximation register analog-to-digital converter <NUM>. The base voltage generation unit <NUM> includes a first amplifier unit <NUM>, a second amplifier unit <NUM>, and a third amplifier unit <NUM>.

The first amplifier unit <NUM> generates the local base voltage VR that defines the zero voltage of the output of the column amplifier <NUM>. The local base voltage VR is supplied to the column amplifier <NUM> through a voltage line L<NUM>. The second amplifier unit <NUM> supplies the output common mode reference voltage VCM of the preamplifier <NUM> to the capacitance multiplexer <NUM> through a voltage line L<NUM>. The output common mode reference voltage VCM is also supplied to the successive approximation register analog-to-digital converter <NUM> through a voltage line L<NUM>. The third amplifier unit <NUM> generates a high voltage VH, a medium voltage VM, and a low voltage VL to be used in the capacitor array unit (CDAC) <NUM>. The high voltage VH, the medium voltage VM, and the low voltage VL are supplied to the capacitor array unit (CDAC) <NUM> through voltage lines L<NUM>, L<NUM>, and L<NUM>.

During the P-phase, the capacitive element <NUM> of the column amplifier <NUM> is charged by the local base voltage VR, and in the D-phase, the local base voltage VR is set as a signal input on a negative side of the capacitance multiplexer (CMUX) <NUM>. The capacitance multiplexer <NUM> is configured differentially. The switches <NUM>_A, <NUM>_B, and <NUM>_C on an input side are short-circuited between differentials at the time of comparison of the comparator <NUM>, and are not connected to a common node. In this way, since an input side of the capacitance multiplexer <NUM> is completely separated at the time of comparison of the comparator <NUM>, settling of the capacitor array unit (CDAC) <NUM> in the successive approximation register analog-to-digital converter <NUM> can be accelerated.

Switches <NUM>_AP and <NUM>_AM, switches <NUM>_BP and <NUM>_BM, and switches <NUM>_CP and <NUM>_CM on an output side of the capacitance multiplexer <NUM> are connected to the voltage line L<NUM> that transmits the output common mode reference voltage VCM, and are in an on state at the time of sampling. The output common mode reference voltage VCM is the same voltage as an input operating potential of the preamplifier <NUM>.

The high voltage VH, the medium voltage VM, and the low voltage VL generated by the third amplifier unit <NUM> are base voltages of the capacitor array unit (CDAC) <NUM>. Since the capacitor array unit (CDAC) <NUM> operates at a high speed at the time of comparison of the comparator <NUM>, the high voltage VH and the low voltage VL are required to be able to respond at a high speed and to have a low impedance.

Here, for a specification of the power supply voltage, for example, <NUM> V (VDD_H) and <NUM> V (VDD_L) are assumed. <NUM> V is the same as the voltage used in the pixel <NUM>, and is used for a circuit of a high breakdown voltage transistor. <NUM> V is assumed to be a voltage used in a logic circuit. The potential VSL of the signal line <NUM> is <NUM> V or more at maximum, and cannot be handled by a low breakdown voltage transistor. Therefore, the column amplifier <NUM> needs to be configured by a high breakdown voltage transistor. The successive approximation register analog-to-digital converter <NUM> requires a high-speed comparison operation, and is desirable to be configured by a low breakdown voltage transistor. However, it is necessary to pay attention to a large leakage current of the low breakdown voltage transistor.

In addition, when a plurality of power supplies is involved between loops of the successive approximation register analog-to-digital converter <NUM>, an operation margin for absorbing variations between different power supplies is required, and it is therefore important to configure with a single power supply. The high voltage VH and the low voltage VL are set to <NUM> V (VDD_L) and the same voltage as the ground, respectively, in order to sufficiently apply a gate voltage to the switches constituting the capacitor array unit (CDAC) <NUM>. Since the output of the column amplifier <NUM> has a high voltage, all the switches constituting the capacitance multiplexer <NUM> are configured by high breakdown voltage transistors.

<FIG> illustrates a level diagram. A voltage range of the potential VSL of the signal line <NUM> varies depending on a sensor specification, but here, it is assumed that the voltage decreases in accordance with brightness with <NUM> V as a reference and the voltage drops by <NUM> mV at maximum. The potential VSL of the signal line <NUM> is amplified by the column amplifier <NUM>. As a gain is higher, noise of the successive approximation register analog-to-digital converter <NUM> in the subsequent stage is suppressed, and noise of the column amplifier <NUM> is also reduced. It is therefore desirable to take a gain as large as possible. However, since the power supply voltage is <NUM> V, it is necessary to suppress the output of the column amplifier <NUM> within a range obtained by adding an operation range and a margin of the circuit to the power supply voltage.

Here, the gain is set to four times, and the range is <NUM> V with respect to <NUM> V. The input of the successive approximation register analog-to-digital converter <NUM> is a differential voltage, and an input on a negative side is fixed at a reference voltage. When the pixel <NUM> has a brightness of <NUM>, a differential of <NUM> V is an input to the successive approximation register analog-to-digital converter <NUM>, and a negative differential voltage is applied as the pixel becomes brighter (that is, the potential VSL of the signal line <NUM> decreases). A relationship with the output code of the successive approximation register analog-to-digital converter <NUM> is such that the differential <NUM> V corresponds to <NUM>/<NUM> full scale, and <NUM>/<NUM> full scale is output when <NUM> V is input.

For a small input signal, an input conversion noise can be reduced by increasing the gain. As illustrated in <FIG>, when the gain is eight times (× <NUM>), an input range is halved. Furthermore, although the gain could be increased, since a contribution of the column amplifier <NUM> is dominant in the input conversion noise, setting the gain larger than eight times would not be of great benefit.

Hereinafter, specific configuration examples of the column amplifier <NUM> and the successive approximation register analog-to-digital converter <NUM> will be described.

Here, as an example of a specific configuration of the column amplifier <NUM>, a current reuse column amplifier (CRCA) will be exemplified. Since the current reuse column amplifier performs voltage amplification by using the bias current of the signal line <NUM>, a non-inverting column amplifier having lower power consumption can be achieved. <FIG> is a circuit diagram depicting an example of the configuration of the current reuse column amplifier.

A current reuse column amplifier <NUM> includes a current amplification transistor <NUM>, current source transistors <NUM> and <NUM>, cascode transistors <NUM> and <NUM>, switches <NUM>, <NUM>, and <NUM>, a base side capacitive element <NUM>, and a feedback capacitive element <NUM>.

Here, for example, a P-channel MOS field effect transistor is used as the current amplification transistor <NUM>, the current source transistor <NUM>, and the cascode transistor <NUM>. Furthermore, for example, an N-channel MOS field effect transistor is used as the current source transistor <NUM> and the cascode transistor <NUM>.

The current amplification transistor <NUM> and the current source transistor <NUM> are connected in series between the signal line <NUM> and a node of a base potential (for example, ground) in that order. That is, a source electrode of the current amplification transistor <NUM> is connected to the signal line <NUM>. A predetermined bias voltage nbias is applied to a gate electrode of the current source transistor <NUM>. As a result, the current source transistor <NUM> causes a constant bias current corresponding to the predetermined bias voltage nbias to flow through the signal line <NUM>.

The current source transistor <NUM>, the cascode transistor <NUM>, and the cascode transistor <NUM> are connected in series between a node of the power supply voltage VDD and a drain electrode of the current source transistor <NUM> in that order. A predetermined bias voltage pbias is applied to a gate electrode of the current source transistor <NUM>, a predetermined bias voltage pcas is applied to a gate electrode of the cascode transistor <NUM>, and a predetermined bias voltage ncas is applied to a gate electrode of the cascode transistor <NUM>.

The switch <NUM> is connected between a gate electrode of the current amplification transistor <NUM> and a drain electrode of the cascode transistor <NUM> (a drain electrode of the cascode transistor <NUM>), and performs an on (closed)/off (open) operation in accordance with the polarity of the switch control signal SP.

The base side capacitive element <NUM> is connected between the gate electrode of the current amplification transistor <NUM> and a node of a base potential (for example, ground). The feedback capacitive element <NUM> has one end connected to the gate electrode of the current amplification transistor <NUM>.

A switch <NUM> is connected between another end of the feedback capacitive element <NUM> and the drain electrode of the cascode transistor <NUM> (the drain electrode of the cascode transistor <NUM>), and performs an on/off operation in accordance with the polarity of the switch control signal SD.

The switch <NUM> has one end connected to a common connection node N<NUM> between the feedback capacitive element <NUM> and the switch <NUM>, and performs an on/off operation in accordance with the polarity of the switch control signal SVR. The local base voltage VR is applied to another end of the switch <NUM>. As a result, the switch <NUM> selectively applies the local base voltage VR to the common connection node N<NUM> under the control of the switch control signal SVR.

In the configuration described above, the current reuse column amplifier <NUM> is configured in which the source electrode of the current amplification transistor <NUM> serves as a (+) input end, the gate electrode serves as a (-) input end, and a common connection node N<NUM> between the cascode transistor <NUM> and the cascode transistor <NUM> serves as an output end. The current amplification transistor <NUM>, which uses the bias current of the signal line <NUM>, enables voltage amplification to be efficiently performed.

In the current reuse column amplifier <NUM> having a configuration described above, in a correspondence relationship with the column amplifier <NUM> illustrated in <FIG>, the switch <NUM> corresponds to the switch <NUM> in <FIG>, the switch <NUM> corresponds to the switch <NUM> in <FIG>, and the switch <NUM> corresponds to the switch <NUM> in <FIG>. In addition, the base side capacitive element <NUM> corresponds to the capacitive element <NUM> having the capacitance value CS, and the feedback capacitive element <NUM> corresponds to the capacitive element <NUM> having the capacitance value CF.

The successive approximation register analog-to-digital converter <NUM> is excellent in power efficiency. <FIG> is a detailed circuit diagram of the successive approximation register analog-to-digital converter <NUM>.

A circuit of the successive approximation register analog-to-digital converter <NUM> is configured by a complete differential. In a general successive approximation register analog-to-digital converter, an input capacitance for sampling an input voltage and a DAC capacitance (CDAC) are often integrated, but here, the input capacitance and the DAC capacitance (CDAC) are separated for multiplexing.

<FIG> also illustrates an input capacitance unit that also serves as the capacitance multiplexer <NUM> (hereinafter, for convenience, described as "capacitance multiplexer <NUM>"). Here, for the sake of simplicity, only one of the plurality of input capacitance units (<NUM>) is illustrated.

In the capacitance multiplexer <NUM>, at the time of sampling, switches <NUM>_P and <NUM>_M and switches <NUM>_P and <NUM>_M are in an on (closed) state to charge capacitive elements <NUM>_P and <NUM>_M with electric charges. At the time of analog-to-digital conversion, the switch <NUM> and switches <NUM>_P and <NUM>_M are in an on (closed) state, and thus the capacitance multiplexer <NUM> is connected to the successive approximation register analog-to-digital converter <NUM>.

The switch <NUM> is not connected to a specific reference potential, but only short-circuits between differentials. This is to prevent an in-phase potential on a side of the preamplifier <NUM> from varying due to an in-phase potential of an input. If an output in-phase potential of the preamplifier <NUM> and the output common mode reference voltage VCM are matched, an input in-phase potential of the preamplifier <NUM> is always the same as the output common mode reference voltage VCM.

Since the output of the column amplifier <NUM> is single-ended, the in-phase potential of the input varies depending on the signal, but linearity is improved because the input in-phase potential of the preamplifier <NUM> does not change. The input side has the output (<NUM> V to <NUM> V) of the column amplifier <NUM> and the local base voltage VR (<NUM> V), but since the output common mode reference voltage VCM is fixed at about <NUM> V, the preamplifier <NUM> having the low voltage (VDD_L) can be used.

Although an input differential voltage is as high as <NUM> V, because of connection in series with the DAC capacitance (CDAC) at the time of charge transfer, the input voltage of the preamplifier <NUM> is sufficiently attenuated. In this way, by managing the in-phase and differential voltages, devices other than the capacitance multiplexer <NUM> can be constituted by a thin film low-voltage transistor having a relatively thin film thickness. Incidentally, all the switches of the capacitance multiplexer <NUM> are configured by a high-voltage transistor having a relatively large film thickness.

All the switches of the preamplifier <NUM>, the comparator <NUM>, the SAR logic unit <NUM>, and the DAC capacitance (CDAC) in a comparison loop of the successive approximation register analog-to-digital converter <NUM> use transistors of the same power supply voltage and the same film thickness, and thus enable high-speed operation.

It is also important that the SAR logic unit <NUM> is completely separated from the column amplifier <NUM> and reference nodes other than the high voltage VH and the low voltage VL during operation. Since these nodes are not so fast and low impedance, it is necessary not to affect settling of the DAC capacitance (CDAC).

As illustrated in <FIG>, a capacitance array of the DAC capacitance (CDAC) includes <NUM> capacitances grouped by <NUM>-<NUM>-<NUM>. The first <NUM>-bit group is defined as MSB, the middle <NUM>-bit group is defined as LSB1, and the last <NUM>-bit group is defined as LSB0. Each group is separated by a bridge capacitive element, and a weight per capacitive element changes. When the weight of the MSB is <NUM>, LSB1 is <NUM>/<NUM> and LSB0 is <NUM>/<NUM>.

The weights of the most significant bit in LSB1 and the least significant bit of the MSB have the same value with redundancy. Similarly, in LSB0, the most significant bits overlap. Since the redundancy is <NUM> bits in total, a bit accuracy of the successive approximation register analog-to-digital converter <NUM> is finally <NUM> BIT. The redundancy is for compensating for insufficient settling of upper bits and for correcting nonlinearity due to variations in the bridge capacitive elements.

In order to widen a range of redundancy, redundant bits should be inserted as high as possible, but there will be a trade-off of increasing capacitive elements, and there will be also an increase in noise. Furthermore, in order to correct variations in the bridge capacitive elements, redundant bits need to be inserted into each group.

The capacitance value CB of the bridge capacitive element can be expressed by the following equation, where a ratio of a weight to a lower group is α (< <NUM>), and a total capacitance value of the lower group (further including a lower substantial capacitance value) is CTL.

Since the bridge capacitive element determines a weight of entire lower bits, a deviation in a ratio of the bridge capacitive element and a unit capacitive element causes nonlinearity. Thus, it is necessary to perform implementation without deviation as much as possible, but it is difficult to match the ratio of the bridge capacitive element and the unit capacitive element because the ratio is not an integral multiple and there is no continuity in layout. It is therefore considered necessary to perform digital correction to multiply a non-integer correction coefficient for each group.

A second embodiment of the present disclosure is an example in which the technology according to the present disclosure is applied to an indirect time-of-flight (TOF) distance image sensor. The indirect TOF distance image sensor is a sensor that measures a distance to a measurement object by measuring a light flight time on the basis of detection of an arrival phase difference of a reflected light emitted from a light source and reflected by the measurement object (subject).

<FIG> is a block diagram depicting an example of a system configuration of an indirect TOF distance image sensor according to the second embodiment of the present disclosure.

In an indirect TOF distance image sensor <NUM>, light emitted from a light source <NUM> is reflected by a measurement object (subject), and the reflected light is incident. The indirect TOF distance image sensor <NUM> has a stacked structure including a sensor chip <NUM> and a circuit chip <NUM> stacked on the sensor chip <NUM>. In this stacked structure, the sensor chip <NUM> and the circuit chip <NUM> are electrically connected through a connection portion (not illustrated) such as a via (VIA), a Cu-Cu connection, and the like. Note that <FIG> illustrates a state in which a wire of the sensor chip <NUM> and a wire of the circuit chip <NUM> are electrically connected via the connection portion described above.

A pixel array unit <NUM> is formed on the sensor chip <NUM>. The pixel array unit <NUM> includes a plurality of pixels <NUM> arranged in a matrix (array) in a two-dimensional grid pattern on the sensor chip <NUM>. In the pixel array unit <NUM>, each of the plurality of pixels <NUM> receives incident light (for example, near infrared light), performs photoelectric conversion, and outputs an analog pixel signal. In the pixel array unit <NUM>, two signal lines VSL<NUM> and VSL<NUM> are wired for each pixel column. When the number of pixel columns of the pixel array unit <NUM> is M (M is an integer), a total of (<NUM> × M) signal lines VSL are wired in the pixel array unit <NUM>.

Each of the plurality of pixels <NUM> has first and second taps A and B (details of which will be described later). An analog pixel signal AINP1 based on charge of the first tap A of the pixel <NUM> in the corresponding pixel column is output to the signal line VSL<NUM> of the two signal lines VSL<NUM> and VSL<NUM>. Furthermore, an analog pixel signal AINP2 based on charge of the second tap B of the pixel <NUM> in the corresponding pixel column is output to the signal line VSL<NUM>. The analog pixel signals AINP1 and AINP2 will be described later.

On the circuit chip <NUM>, a row selection unit <NUM>, a column signal processing unit <NUM>, an output circuit unit <NUM>, and a timing control unit <NUM> are disposed. The row selection unit <NUM> drives each pixel <NUM> of the pixel array unit <NUM> in units of pixel rows and outputs the pixel signals AINP1 and AINP2. Under the driving by the row selection unit <NUM>, the analog pixel signals AINP1 and AINP2 output from the pixels <NUM> in selected rows are supplied to the column signal processing unit <NUM> through the two signal lines VSL<NUM> and VSL<NUM>.

The column signal processing unit <NUM> includes a plurality of analog-to-digital converters (ADC) <NUM> provided in correspondence with the pixel columns (for example, for each pixel column) of the pixel array unit <NUM>. The analog-to-digital converter <NUM> performs analog-to-digital conversion processing on the analog pixel signals AINP1 and AINP2 supplied through the signal lines VSL<NUM> and VSL<NUM>, and outputs the pixel signals AINP1 and AINP2 to the output circuit unit <NUM>. The output circuit unit <NUM> performs predetermined signal processing on the digitized pixel signals AINP1 and AINP2 output from the column signal processing unit <NUM>, and outputs the pixel signals AINP1 and AINP2 to outside of the circuit chip <NUM>.

The timing control unit <NUM> generates various timing signals, clock signals, control signals, and the like, and performs drive control of the row selection unit <NUM>, the column signal processing unit <NUM>, the output circuit unit <NUM>, and the like on the basis of the signals.

<FIG> is a circuit diagram depicting an example of a circuit configuration of the pixel <NUM> in the indirect TOF distance image sensor <NUM> according to the second embodiment.

The pixel <NUM> of the present example includes, for example, a photodiode <NUM> as a photoelectric conversion element. In addition to the photodiode <NUM>, the pixel <NUM> includes an overflow transistor <NUM>, two transfer transistors <NUM> and <NUM>, two reset transistors <NUM> and <NUM>, two floating diffusion layers <NUM> and <NUM>, two amplification transistors <NUM> and <NUM>, and two selection transistors <NUM> and <NUM>. The two floating diffusion layers <NUM> and <NUM> correspond to the first and second taps A and B (which may be hereinafter simply described as "taps A and B") illustrated in <FIG>.

The photodiode <NUM> photoelectrically converts received light to generate a charge. The photodiode <NUM> can have, for example, a back surface irradiation type pixel structure. However, the structure is not limited to the back surface irradiation type structure, and may be a front surface irradiation type structure that captures light emitted from a side of a substrate front surface.

The overflow transistor <NUM> is connected between a cathode electrode of the photodiode <NUM> and a power line of the power supply voltage VDD, and has a function of resetting the photodiode <NUM>. Specifically, the overflow transistor <NUM> becomes conductive in response to an overflow gate signal TRG supplied from the row selection unit <NUM>, and thus sequentially transfers charges generated in the photodiode <NUM> to the floating diffusion layers <NUM> and <NUM>.

The floating diffusion layers <NUM> and <NUM> corresponding to the first and second taps A and B accumulate the charge transferred from the photodiode <NUM>, convert the charge into a voltage signal having a voltage value corresponding to an amount of the charge, and generate the pixel signals AINP1 and AINP2.

The two reset transistors <NUM> and <NUM> are respectively connected between the two floating diffusion layers <NUM> and <NUM> and the power line of the power supply voltage VDD. Then, the reset transistors <NUM> and <NUM> become conductive in response to the reset signal RST supplied from the row selection unit <NUM>, and thus extract the charge from the floating diffusion layers <NUM> and <NUM>, respectively, and initialize the charge amount.

The two amplification transistors <NUM> and <NUM> are connected between the power line of the power supply voltage VDD and the two selection transistors <NUM> and <NUM>, respectively, and amplify voltage signals converted from charges to voltages in the floating diffusion layers <NUM> and <NUM>, respectively.

The two selection transistors <NUM> and <NUM> are connected between the two amplification transistors <NUM> and <NUM> and the signal lines VSL<NUM> and VSL<NUM>, respectively. Then, the selection transistors <NUM> and <NUM> become conductive in response to the selection signal SEL supplied from the row selection unit <NUM>, and thus output voltage signals amplified by the amplification transistors <NUM> and <NUM>, respectively, to the two signal lines VSL<NUM> and VSL<NUM> as the analog pixel signals AINP1 and AINP2.

The two signal lines VSL<NUM> and VSL<NUM> are connected to an input end of one analog-to-digital converter <NUM> in the column signal processing unit <NUM> for each pixel column, and transmit the analog pixel signals AINP1 and AINP2 output from the pixels <NUM> for each pixel column to the analog-to-digital converter <NUM>.

Note that the circuit configuration of the pixel <NUM> is not limited to the circuit configuration exemplified in <FIG> as long as the circuit configuration can generate the analog pixel signals AINP1 and AINP2 by photoelectric conversion.

In the indirect TOF distance image sensor <NUM> having a configuration described above, the technology according to the present disclosure can be applied to the column signal processing unit <NUM> including the analog-to-digital converter <NUM>. Specifically, as the column signal processing unit <NUM> including the analog-to-digital converter <NUM>, similarly to a case in the first embodiment, the column signal processing system according to the first embodiment, the second embodiment, the third embodiment, or the fourth embodiment including the column amplifier unit <NUM>, the capacitance unit <NUM>, and the successive approximation register analog-to-digital conversion unit 15A can be used.

Although the technology according to the present disclosure has been described above on the basis of the preferred embodiments, the technology according to the present disclosure is not limited to the embodiments. The configurations and structures of the CMOS image sensor and the indirect TOF distance image sensor illustrated in the embodiments described above are examples, and can be changed as appropriate.

The imaging apparatus (CMOS image sensor) according to the first embodiment can be used for various devices that sense light such as visible light, infrared light, ultraviolet light, X-ray, and the like as illustrated in <FIG>, for example. Specific examples of such various devices are listed below.

The technology according to the present disclosure can be applied to various products. Hereinafter, a more specific application example will be described.

Here, description will be made of a case where the technology according to the present disclosure is applied to an imaging system such as a digital still camera, a video camera, or the like, a mobile terminal device having an imaging function, such as a mobile phone or the like, or an electronic device such as a copier using an imaging apparatus as an image reader.

<FIG> is a block diagram depicting a configuration example of an imaging system as an example of an electronic device of the present disclosure.

As illustrated in <FIG>, an imaging system <NUM> of the present example includes an imaging optical system <NUM> including a lens group and the like, an imaging section <NUM>, a digital signal processor (DSP) circuit <NUM>, a frame memory <NUM>, a display device <NUM>, a recording device <NUM>, an operation system <NUM>, a power supply system <NUM>, and the like. Then, the DSP circuit <NUM>, the frame memory <NUM>, the display device <NUM>, the recording device <NUM>, the operation system <NUM>, and the power supply system <NUM> are connected to one another via a bus line <NUM>.

The imaging optical system <NUM> captures incident light (image light) from a subject and forms an image on an imaging surface of the imaging section <NUM>. The imaging section <NUM> converts a light amount of the incident light from which an image has been formed on the imaging surface by the optical system <NUM> into an electric signal for each pixel and outputs the electric signal as a pixel signal. The DSP circuit <NUM> performs general camera signal processing, such as white balance processing, demosaic processing, gamma correction processing, and the like, for example.

The frame memory <NUM> is appropriately used for storing data in the process of signal processing in the DSP circuit <NUM>. The display device <NUM> includes a panel display device such as a liquid crystal display device, an organic electro luminescence (EL) display device, or the like and displays a moving image or a still image captured by the imaging section <NUM>. The recording device <NUM> records the moving image or the still image captured by the imaging section <NUM> on a recording medium such as a portable semiconductor memory, an optical disk, a hard disk drive (HDD), or the like.

The operation system <NUM> issues operation commands for various functions of the imaging apparatus <NUM> in response to operation of a user. The power supply system <NUM> appropriately supplies various power supplies serving as operation power supply of the DSP circuit <NUM>, the frame memory <NUM>, the display device <NUM>, the recording device <NUM>, and the operation system <NUM> to these supply targets.

In the imaging system <NUM> having a configuration described above, the imaging apparatus according to the first embodiment described above can be used as the imaging section <NUM>. In the imaging apparatus according to the first embodiment, in particular, the successive approximation register analog-to-digital converter is excellent in power efficiency, and thus using the imaging apparatus as the imaging section <NUM> can contribute to lower power consumption of the imaging system <NUM>.

The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be achieved as an imaging apparatus mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, a construction machine, an agricultural machine (tractor), or the like.

<FIG> is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

A vehicle control system <NUM> includes a plurality of electronic control units connected to each other via a communication network <NUM>. In an example depicted in <FIG>, the vehicle control system <NUM> includes a driving system control unit <NUM>, a body system control unit <NUM>, an outside-vehicle information detecting unit <NUM>, an in-vehicle information detecting unit <NUM>, and an integrated control unit <NUM>. Furthermore, as a functional configuration of the integrated control unit <NUM>, a microcomputer <NUM>, a sound/image output section <NUM>, and an in-vehicle network interface (I/F) <NUM> are illustrated.

The driving system control unit <NUM> controls operation of devices related to a driving system of a vehicle in accordance with various kinds of programs. For example, the driving system control unit <NUM> functions as a control device for a driving force generating device that generates a driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism that transmits a driving force to wheels, a steering mechanism that adjusts a steering angle of the vehicle, a braking device that generates a braking force of the vehicle, and the like.

The body system control unit <NUM> controls operation of various kinds of devices provided in the vehicle body in accordance with various kinds of programs.

The outside-vehicle information detecting unit <NUM> detects information about the outside of the vehicle equipped with the vehicle control system <NUM>. For example, an imaging section <NUM> is connected to the outside-vehicle information detecting unit <NUM>. The outside-vehicle information detecting unit <NUM> makes the imaging section <NUM> capture an image of the outside of the vehicle, and receives the captured image. On the basis of the received image, the outside-vehicle information detecting unit <NUM> may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section <NUM> is an optical sensor that receives light and outputs an electric signal corresponding to an amount of the received light. The imaging section <NUM> can output the electric signal as an image or as distance measurement information. Furthermore, the light received by the imaging section <NUM> may be visible light or invisible light such as infrared rays or the like.

The driver state detecting section <NUM> may include a camera imaging a driver, for example.

The microcomputer <NUM> can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of in-vehicle and outside-vehicle information obtained by the outside-vehicle information detecting unit <NUM> or the in-vehicle information detecting unit <NUM>, and output a control command to the driving system control unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, and the like.

In addition, the microcomputer <NUM> can perform cooperative control intended for automated driving, which makes the vehicle to travel automatically without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the surroundings of the vehicle, obtained by the outside-vehicle information detecting unit <NUM> or the in-vehicle information detecting unit <NUM>.

Furthermore, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the outside-vehicle information obtained by the outside-vehicle information detecting unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control for the purpose of preventing glare, such as switching from a high beam to a low beam or the like, by controlling a headlamp in accordance with a position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit <NUM>.

The sound/image output section <NUM> transmits an output signal of at least one of a sound or an image to an output device capable of visually or auditorily notifying an occupant of the vehicle or the outside of the vehicle of information. In an example in <FIG>, an audio speaker <NUM>, a display section <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display section <NUM> may, for example, include at least one of an on-board display or a head-up display.

<FIG> is a diagram depicting an example of an installation position of the imaging section <NUM>.

In <FIG>, a vehicle <NUM> includes imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> as the imaging section <NUM>.

The imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle <NUM>, a position on an upper portion of a windshield within the interior of the vehicle, and the like. The imaging section <NUM> provided at the front nose and the imaging section <NUM> provided at the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle <NUM>. The imaging sections <NUM> and <NUM> provided on the sideview mirrors obtain mainly an image of the sides of the vehicle <NUM>. The imaging section <NUM> provided on the rear bumper or the back door obtains mainly an image of the rear of the vehicle <NUM>. The image of the front obtained by the imaging sections <NUM> and <NUM> is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Note that <FIG> illustrates an example of photographing ranges of the imaging sections <NUM> to <NUM>. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided on the front nose. Imaging ranges <NUM> and <NUM> respectively represent the imaging ranges of the imaging sections <NUM> and <NUM> provided to the sideview mirrors. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided on the rear bumper or the back door. A bird's-eye image of the vehicle <NUM> as viewed from above can be obtained by superimposing image data imaged by the imaging sections <NUM> to <NUM>, for example.

At least one of the imaging sections <NUM> to <NUM> may have a function of obtaining distance information. For example, at least one of the imaging sections <NUM> to <NUM> may be a stereo camera including a plurality of imaging apparatuses, or may be an imaging device having pixels for phase difference detection.

For example, the microcomputer <NUM> obtains a distance to each three-dimensional object in the imaging ranges <NUM> to <NUM> and a temporal change of the distance (relative speed with respect to the vehicle <NUM>) on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, and thus can extract, as a preceding vehicle, a three-dimensional object traveling at a predetermined speed (for example, <NUM>/h or more) in substantially the same direction as the vehicle <NUM>, in particular, the closest three-dimensional object on a traveling path of the vehicle <NUM>. Moreover, the microcomputer <NUM> can set a following distance to be secured in advance in front of the preceding vehicle, and can perform automatic brake control (including following stop control), automatic acceleration control (including following start control), and the like. As described above, it is possible to perform cooperative control for the purpose of automated driving or the like in which the vehicle automatically travels without depending on the operation of the driver.

For example, on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, the microcomputer <NUM> can classify three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles and the like, extract the three-dimensional object data, and use the three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer <NUM> identifies obstacles around the vehicle <NUM> as obstacles that can be visually recognized by the driver of the vehicle <NUM> and obstacles that are difficult to visually recognize. When the collision risk is a set value or more and there is a possibility of collision, the microcomputer can perform driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker <NUM> or the display section <NUM> or performing forced deceleration or avoidance steering via the driving system control unit <NUM>.

For example, the microcomputer <NUM> can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the imaging sections <NUM> to <NUM>. Such recognition of a pedestrian is performed by, for example, a procedure of extracting feature points in the images captured by the imaging sections <NUM> to <NUM> as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points indicating an outline of an object to determine whether or not the object is a pedestrian. When the microcomputer <NUM> determines that a pedestrian is present in the images captured by the imaging sections <NUM> to <NUM> and recognizes the pedestrian, the sound/image output section <NUM> controls the display section <NUM> to superimpose and display a rectangular contour line for emphasis on the recognized pedestrian. Furthermore, the sound/image output section <NUM> may control the display section <NUM> to display an icon or the like indicating a pedestrian at a desired position.

Claim 1:
An imaging apparatus comprising:
a pixel array unit (<NUM>) on which pixels (<NUM>) including a photoelectric conversion element (<NUM>) are arranged;
a column amplifier unit (<NUM>) configured to obtain a difference between a reset component and a signal component input from each of the pixels (<NUM>) of a column of pixels of the pixel array unit (<NUM>) through a signal line (<NUM>) and output the difference as a pixel signal;
a capacitance unit (<NUM>) configured to hold the pixel signal input from the column amplifier unit (<NUM>); and
a successive approximation register analog-to-digital conversion unit (15A) configured to convert an analog signal input from the capacitance unit (<NUM>) into a digital signal, wherein
the column amplifier unit (<NUM>) includes
an amplifier to which a potential of the signal line (<NUM>) is input to a non-inverting input terminal,
a first switch (<NUM>) having one end connected to an output terminal of the amplifier and another end connected to an inverting input terminal of the amplifier,
a second switch (<NUM>) having one end connected to an output terminal of the amplifier,
a first capacitive element (<NUM>) having one end connected to another end of the second switch (<NUM>) and another end connected to the another end of the first switch (<NUM>) and the inverting input terminal of the amplifier,
a second capacitive element (<NUM>) connected between the another end of the first capacitive element (<NUM>) and the inverting input terminal of the amplifier and a base potential node, and
a third switch (<NUM>) having one end connected to the another end of the second switch (<NUM>) and the one end of the first capacitive element (<NUM>), the third switch (<NUM>) having another end to which a local base voltage is applied.