Patent Description:
There is a growing interest in magnetoresistive random-access memory (MRAM) devices as replacements for embedded static random-access memories (SRAMs). An MRAM device can be used for non-volatile storage of data in magnetic tunnel junction (MTJ) devices. The MTJ devices are formed in a dielectric layer in the back-end-of-line (BEOL) processing, where they are interconnected by means of metal layers so as to form the desired electrical circuits. The BEOL processing involves forming metal layers, separated by dielectric layers, having interconnecting wires or lines that are isolated by dielectric material. Further, via connections are formed so as to connect the metal layers to each other.

As there is an ever-increasing demand for smaller and faster semiconductor devices with higher memory density, there is a need for improved semiconductor devices having a more advanced electrical routing. Examples of prior art may be found in documents <CIT> and <CIT>.

An object of at least some of the embodiments of the present invention is to provide an improved semiconductor device wherein the MTJ device can be more efficiently integrated in the BEOL, and in particular in connection with more advanced technology nodes.

At least one of this and other objects of the present invention is achieved by means of a semiconductor device and a method having the features defined in the independent claims. Preferable embodiments of the invention are characterised by the dependent claims.

According to a first aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a first metal layer, a first dielectric layer arranged on the first metal layer, a second metal layer arranged on the first dielectric layer, a second dielectric layer arranged on the second metal layer, and a third metal layer arranged on the second dielectric layer. The first metal layer is electrically connected to the second metal layer by means of a via arranged in the first dielectric layer, and the second metal layer is electrically connected to the third metal layer by means of a via arranged in the second dielectric layer. Further, the semiconductor device comprises a magnetic tunnel junction, MTJ, device that is arranged in the first dielectric layer and the second device layer and is electrically connected to the first metal layer and the third metal layer.

According to a second aspect of the present invention, a method of manufacturing a semiconductor device according to the first aspect is provided. The method comprises forming a first dielectric layer on a first metal layer, and forming a second metal layer on the first dielectric layer. The second metal layer is electrically connected to the first metal layer by means of a via arranged in the first dielectric layer. The method further comprises forming a MTJ device arranged in the first dielectric layer and the first metal layer, forming a second dielectric layer on the second metal layer, and forming a third metal layer on the second dielectric layer, wherein the third metal layer is electrically connected to the second metal layer by means of a via arranged in the second dielectric layer.

In prior art devices, wherein the MTJ device may be formed in the first dielectric layer, the thickness of the dielectric layer is limited by a minimum height of the MTJ device. As the minimum possible height of the MTJ device in turn may be determined by the configuration of the stack of layers required for forming the MTJ device, it may be difficult to reduce the height of the MTJ device below a certain value without compromising the performance of the MTJ device. The present invention is based on the realisation that by forming the MTJ device such that it extends not only in the first dielectric layer but also in the second metal layer, the thickness of the dielectric layer can be reduced below the height of the MTJ device without risking to reduce the performance of the MTJ stack. The present invention hence provides a semiconductor device wherein the MTJ device may be integrated in the first dielectric layer and the second metal layer so as to allow for more advanced technology nodes, such as e.g. <NUM> and below. The MTJ device may in other words be arranged in the extension of a via connection in the first dielectric layer.

The MTJ device may be provided in the back-end-of-line (BEOL) on e.g. a metal line of the first metal layer and arranged to extend through the first dielectric layer into the second metal layer, wherein it may be electrically connected to the third metal layer by means of e.g. a via in the second dielectric layer. The MTJ may in other words be integrated on the first metal layer at the memory area and at the same time in the second metal layer at the logic area of the semiconductor device.

The MTJ device may be formed of a stack of a magnetic reference layer, or pinned layer, and a magnetic free layer separated by a barrier layer. The magnetic reference layer and the magnetic free layer may e.g. comprise CoFeB, whereas the barrier layer may comprises MgO. The reference layer may be adapted to have a fixed magnetisation direction, and the free layer may be adapted to have a variable magnetisation direction. The intermediate barrier layer may be adapted to allow tunnelling of electrons between the reference layer and the free layer.

The relative magnetic orientation of the reference layer and the free layer may determine an electric resistance of the MTJ device. The MTJ device may have a relatively low resistance when the magnetisation of the reference layer and the free layer are aligned in parallel and a relatively high resistance when the magnetisation of the reference layer and the free layer, respectively, are anti-parallel. The difference in electric resistance may be used for storing information in the MTJ device.

The stack may be arranged such that the magnetic reference layer is formed, or electrically connected to, the first metal layer and such that the magnetic free layer is electrically connected to the third metal layer. Such configuration may be referred to as a bottom-pinned configuration. Alternatively, the stack may be arranged in an opposite configuration, with the free layer formed on or electrically connected to the first metal layer and the reference layer electrically connected to the third metal layer. Such configuration may be referred to as a top-pinned configuration.

The MTJ stack may be provided on a bottom electrode arranged on the first metal layer. The bottom electrode may be adapted to provide a desired surface roughness, and in particular to provide a smoother surface as compared to the bare surface of the first metal layer. A relatively smooth surface may be advantageous in subsequent processing steps, when the MTJ stack is formed. The bottom electrode may in some examples form part of the BEOL, whereas it in other examples may form part of the stack forming the MTJ device.

The MTJ device may be a spin-transfer torque (STT) MTJ device utilising spin-aligned electrons to directly torque the magnetic domains of the free layer. The STT MTJ device advantageously allows for a reduction of write currents.

The magnetic reference layer and the magnetic free layer may have a perpendicular magnetic anisotropy allowing for the size of the MTJ device to be reduced, which hence allows for a reduced thickness of the layers of the semiconductor device and a semiconductor device having an increased memory density.

The semiconductor device may e.g. be, or form part of, a magnetoresistive random-access memory (MRAM) using the MTJ device for non-volatile storage of data.

It will be appreciated that the term "layer", e.g. specified as "metal layer" and "dielectric layer", may refer to specific levels or positions in the multilayer stack forming the semiconductor device. A metal layer may therefore comprise both electrically conducting structures or regions, such as metal structures, and dielectric regions. The metal structures may e.g. be provided as metal filled trenches in a dielectric material. Thus, the term "metal layer" may refer to a layer comprising a dielectric material having metal structures. Preferably, the metal layer may be formed of metal interconnecting wires that are electrically isolated or separated from each other by dielectric material. The term "dielectric layer" may refer to an electrically insulating layer structurally arranged between two metal layers.

According to an embodiment, the MTJ device may be arranged on-axis, i.e., on a metal line of the first metal layer. The MTJ device may thereby be directly connected to the first metal layer without any additional wiring or routing to the metal lines of the first metal layer.

According to an embodiment, a total thickness of the first dielectric layer and the second metal layer is less than <NUM>. By using relatively thin layers, the number of layers may be increased so as to allow for a larger number of e.g. MTJ devices to be interconnected. Thus, a semiconductor device may be provided, having an increased memory density.

According to an embodiment, one or several of the metal layers of the semiconductor device may be formed of a plurality of metal lines, or interconnecting wires, and a dielectric material. The metal layer may e.g. be formed by a subtractive method wherein a blanket film of metal is deposited first, patterned and then etched so as to define the interconnecting wires. The dielectric material may then be deposited over the wires. Alternatively, or additionally, the metal layer may be formed by an additive method, also referred to as a Damascene process, wherein a dielectric layer is patterned with open trenches which are filled with a metal such as e.g. copper. Copper may be advantageous over e.g. aluminium, as copper may reduce the electrical resistance in the metal layer. The trenches may be filled by depositing a coating of the metal, such as e.g. copper, on the dielectric layer, wherein metal extending above the top of the dielectric layer (also referred to as overburden) may be removed by chemical-mechanical planarization (CMP). The CMP may leave the metal sunken within the trenches, such that a metal layer with interconnecting wires embedded in an isolating material may be provided. The planarization of the layer may improve the flatness of the surface prior to subsequent processing steps. An improved flatness may e.g. facilitate subsequent lithography steps.

According to an embodiment, the dielectric material of at least one of the first and second metal layer may be a low-κmaterial having a relatively small dielectric constant relative to e.g. silicon dioxide. The low- κ dielectric may reduce parasitic capacitance and crosstalk in the semiconductor device. Examples of low-κ materials may include e.g. silicon dioxide doped with fluorine or carbon, porous silicon dioxide and organic polymeric dielectrics. Alternatively, or additionally, the low-κmaterial may be provided in the first dielectric layer and/or the second dielectric layer.

According to an embodiment, the MTJ device may be connected to a metal line of the third metal layer by means of a via arranged in the second dielectric layer. The MTJ device may be arranged on-axis, i.e., beneath a metal line of the third metal layer, such that the third metal layer is connected to the first metal layer by means of the via and the MTJ device.

It will be appreciated that other embodiments than those described above are also possible. It will also be appreciated that any of the features in the embodiments described for the semiconductor device according to the first aspect of the present invention may be combined with the manufacturing method according to the second aspect. Further objectives, or features of, and advantages with the present invention will become apparent when studying the following detailed disclosure, the drawings and the appended claims. Those skilled in the art will realise that different features of the present invention can be combined to create embodiments other than those described in the following.

The above, as well as additional objects, features and advantages of the present invention, will be better understood through the following illustrative and non-limiting detailed description of preferred embodiments of the present invention, with reference to the appended drawings, in which:.

All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate the embodiments of the present invention, wherein other parts may be omitted or merely suggested.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplifying embodiments of the present invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will convey the scope of the invention to those skilled in the art. Furthermore, like numbers refer to the same or similar elements or components throughout.

With reference to <FIG>, there is shown cross-sectional side view of a semiconductor device <NUM> according to an embodiment of the present invention. The semiconductor device <NUM> comprises a stacked structure of layers that is arranged in the following order: a first metal layer <NUM>, a first dielectric layer <NUM>, a second metal layer <NUM>, a second dielectric layer <NUM> and a third metal layer <NUM>. Further, an MTJ device <NUM> is formed or integrated in the first dielectric layer <NUM> and the second metal layer <NUM>, and is electrically connected to the first metal layer <NUM> and the third metal layer <NUM>. The MTJ device <NUM> may comprise a bottom electrode <NUM> arranged at the interface with the first metal layer <NUM>.

The first metal layer <NUM> comprises metal lines <NUM> or conductor wires that are arranged in a dielectric material <NUM>. The dielectric material <NUM> may e.g. be a layer of silicon dioxide or a low-κ material. In one example, the metal lines <NUM> are formed by a Damascene process, wherein trenches in the dielectric material <NUM> are filled with a metal such as e.g. copper.

The first dielectric layer <NUM> may e.g. comprise a layer of SiCN deposited on the first metal layer <NUM> so as to separate the first metal layer <NUM> and the second metal layer <NUM>. As shown in <FIG>, the first dielectric layer <NUM> comprises an MTJ device <NUM> arranged on a metal line <NUM> of the first metal layer <NUM> and further extending into the second metal layer <NUM>.

Similarly to the first metal layer <NUM>, the second metal layer <NUM> comprises layer of a dielectric material <NUM>, such as a low-κ material or an ultra low- κ material, and metal lines <NUM> that are formed in trenches of the dielectric material <NUM>. One or several of the metal lines <NUM> of the second metal layer <NUM> may be electrically connected to a corresponding metal line <NUM> of the first metal layer <NUM> by means of vias <NUM> arranged in the first dielectric layer <NUM>.

The second dielectric layer <NUM> may be similarly configured as the first dielectric layer <NUM>, and may hence be formed as a layer of e.g. SiCN deposited on the second metal layer <NUM>. Subsequently, the third metal layer <NUM> is formed on the second dielectric layer <NUM> by e.g. deposition of a dielectric material <NUM>, such as e.g. a low-κ material. The third metal layer <NUM> further comprises metal lines <NUM> that are arranged in trenches of the dielectric material of the third metal layer <NUM>. Some of the metal lines <NUM> are connected to the MTJ device <NUM> or a metal line <NUM> of the second metal layer <NUM> by means of a via connections <NUM> arranged in the second dielectric material <NUM>.

Thus, a semiconductor device <NUM> is provided wherein a minimum thickness of the first dielectric layer <NUM> is not limited to a maximum height of the MTJ device <NUM> (including any bottom electrodes <NUM>). As indicated in <FIG>, the MTJ device <NUM> may have a height exceeding the thickness of the first dielectric layer <NUM> as long as the total thickness h of the first dielectric layer <NUM> and the second metal layer <NUM> exceeds the height of the MTJ device.

<FIG> schematically depicts a cross-sectional side view of an MTJ device according to an embodiment of the present invention. The MTJ device may be integrated in a semiconductor device similarly configured as the device discussed with reference to <FIG>. The MTJ device <NUM> comprises a stack of multiple layers, having a magnetic reference or pinned layer <NUM>, a barrier layer <NUM> and a magnetic free layer <NUM>. It should be noted that the order of the magnetic reference layer <NUM> and the free layer <NUM> may be reversed such that the magnetic reference layer <NUM> is arranged above the magnetic free layer <NUM> in the stack. The magnetic reference layer <NUM> and the magnetic free layer <NUM> may e.g. have a perpendicular magnetic anisotropy with a direction that can be altered between e.g. two mutually opposing directions in the magnetic free layer <NUM>.

The reference layer <NUM> and the free layer <NUM> may be formed of, or at least comprise, CoFeB. The CoFeB may e.g. be arranged in one or several layers in the reference layer <NUM> and/or the free layer <NUM>. The barrier layer <NUM> may be formed of, or at least comprise, MgO configured to allow electrons to tunnel between the reference layer <NUM> and the free layer <NUM>.

<FIG>illustrate cross-sectional side views of a semiconductor device at different stages of a manufacturing process according to an embodiment. The resulting semiconductor device may be similarly configured as the devices discussed with reference to <FIG>.

<FIG> shows a first metal layer <NUM> comprising a dielectric material <NUM>, such as e.g. a low-κmaterial, in which trenches have been etched and filled with e.g. copper <NUM>. The overburden has then been removed by CMP such that a planar surface of the first metal layer <NUM> is provided, having exposed conductive metal lines <NUM> embedded in the dielectric material <NUM>. Subsequently, a layer of dielectric material, such as e.g. <NUM> SiCN, has been deposited so as to form the first dielectric layer <NUM>.

In <FIG>, an MTJ device <NUM> has been formed on a metal line <NUM> of the first metal layer <NUM>. The MTJ device <NUM> may be formed by depositing a stack of layers, forming the MTJ device <NUM>, on the first dielectric layer <NUM> (which may have been provided with a trench at the intended position for the MTJ device <NUM>, exposing the underlying metal line <NUM>). A bottom electrode <NUM> may be provided on the metal line <NUM> prior to deposition of the stack. The deposited stack may then be etched through a hardmask so as to define the MTJ device <NUM>, e.g. in the form of a pillar protruding from the surface of the first dielectric layer <NUM>. As shown in <FIG>, the dielectric material <NUM> of the second metal layer <NUM> may then be provided such that at least a portion of the MTJ device <NUM> protrudes into the dielectric material <NUM>.

In <FIG>, the dielectric material <NUM> of the second metal layer <NUM> has been provided with metal lines <NUM> arranged in trenches in a similar manner as described with references to the first metal layer <NUM>. The metal lines <NUM> may be defined by e.g. a CMP process that may be stopped prior to the MTJ device <NUM> is exposed, i.e., leaving at least some of the dielectric material <NUM> on top of the MTJ device <NUM>. Further, an electric interconnect <NUM>, or via connection, has been formed so as to provide a connection between the second metal layer <NUM> and the first metal layer <NUM>.

A dielectric material, such as e.g. SiCN, may then be deposited so as to form the second dielectric layer <NUM> as shown in <FIG>, onto which a further layer of e.g. the low-κmaterial <NUM> may be deposited to form the third metal layer <NUM>. Metal lines <NUM> may be formed in trenches in the third metal layer <NUM> in a similar manner as described with reference to the first metal layer <NUM> and the second metal layer <NUM>. Further, via connections <NUM> are formed in order to provide an electrical connection between a metal line <NUM> of the third metal layer <NUM> and the MTJ device <NUM>, and a metal line <NUM> of the third metal layer <NUM> and a metal line <NUM> of the second metal layer <NUM>.

<FIG> schematically illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention. The semiconductor device may be similarly configured as the semiconductor devices described with reference to <FIG>.

The method comprises the steps of forming <NUM> a first dielectric layer on a first metal layer, and forming <NUM> a via trench in the first dielectric layer so as to expose a metal line of the underlying first metal layer. The method further comprises a step of forming <NUM> a second metal layer on the first dielectric layer by depositing <NUM> a layer of a dielectric material in which an MTJ device and metal wires may be formed <NUM>, <NUM>. Further, a second dielectric layer is formed <NUM>, onto which a third metal layer is provided <NUM>.

In conclusion, a semiconductor device and a method for manufacturing such as device are disclosed. The semiconductor device comprises an MTJ device that is electrically connected to a first metal layer and a third metal layer, and integrated into a first dielectric material and a second metal layer of the semiconductor device.

Claim 1:
A semiconductor device (<NUM>), comprising:
a first metal layer (<NUM>);
a first dielectric layer (<NUM>) arranged on the first metal layer;
a second metal layer (<NUM>) arranged on the first dielectric layer;
a second dielectric layer (<NUM>) arranged on the second metal layer; and
a third metal layer (<NUM>) arranged on the second dielectric layer;
wherein each of the first, second and third metal layers comprises a plurality of conductive lines (<NUM>, <NUM>, <NUM>) embedded in a dielectric material (<NUM>, <NUM>, <NUM>);
a magnetic tunnel junction, MTJ, device (<NUM>) comprising a stack of a reference layer (<NUM>) and a free layer (<NUM>) separated by a barrier layer (<NUM>), the MTJ device being arranged on a conductive line (<NUM>) of the first metal layer and extending through the first dielectric layer and into the second metal layer; and
a via (<NUM>) arranged on the MTJ device and extending through the second dielectric layer up to a conductive line (<NUM>) of the third metal layer to electrically connect the MTJ device to the conductive line of the third metal layer, wherein the reference layer (<NUM>), the barrier layer (<NUM>) and the free layer (<NUM>) of the MTJ device and the via (<NUM>) are arranged between the conductive line (<NUM>) of the first metal layer and the conductive line (<NUM>) of the third metal layer, characterized in that at least one conductive line (<NUM>) of the second metal layer is separated, along a vertical axis, from a corresponding conductive line (<NUM>) <NUM> of the first metal layer by dielectric material (<NUM>).