Patent Description:
<CIT> discloses a photonic integrated circuit that includes a silicon layer including a waveguide and at least one other photonic component. A heat-dissipating radiator can be incorporated into the photonic integrated circuit. <CIT> discloses integrated target waveguide devices and optical analytical systems including such devices. Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems. A photonics chip integrates optical components, such as waveguides, photodetectors, modulators, and optical power splitters, and electronic components, such as field-effect transistors, into a unified platform. Among other factors, layout area, cost, and operational overhead may be reduced by the integration of both types of components on the same chip.

An edge coupler, also known as a spot-size converter, is commonly used for coupling light of a given mode from a light source, such as a laser or an optical fiber, to optical components on the photonics chip. The edge coupler may include a section of a waveguide core that defines an inverse taper having a tip. In the edge coupler construction, the narrow end of the inverse taper provides a facet at the tip that is positioned adjacent to the light source, and the wide end of the inverse taper is connected with another section of the waveguide core that routes the light to the optical components of the photonics chip.

The gradually-varying cross-sectional area of the inverse taper supports mode transformation and mode size variation associated with mode conversion when light is transferred from the light source to the edge coupler. The tip of the inverse taper is unable to fully confine the incident mode received from the light source because the cross-sectional area of the tip is considerably smaller than the mode size. Consequently, a significant percentage of the electromagnetic field of the incident mode is distributed about the tip of the inverse taper. As its width increases, the inverse taper can support the entire incident mode and confine the electromagnetic field.

Conventional edge couplers may be susceptible to power-related damage because of poor power handling capability, which adversely impacts reliability. Particularly susceptive to power-related damage are silicon waveguide cores that are surrounded by low-index cladding containing dielectric materials characterized by poor thermal conductivity. At high optical input powers, non-linear absorption effects in silicon waveguide cores may result in severe thermal heating, and even physical melting, because of an inability to adequately dissipate the generated heat.

Improved structures including an optical component and methods of fabricating a structure including an optical component are needed.

A structure according to the invention includes the features defined in claim <NUM>.

A method according to the invention includes the features defined in claim <NUM>.

Embodiments of the invention include the features of the dependent claims.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.

With reference to <FIG> and in accordance with embodiments of the invention, a structure <NUM> includes a waveguide core <NUM> as an optical component. In a representative embodiment, the waveguide core <NUM> may be an edge coupler in which the waveguide core <NUM> includes an inverse taper <NUM> and has an end surface defining a facet <NUM>. The inverse taper <NUM> increases in width W1 with increasing distance from the facet <NUM>. An inverse taper refers to a tapered section of a waveguide core characterized by a gradual increase in width along a mode propagation direction. The waveguide core <NUM> may be aligned along a longitudinal axis <NUM>, and the waveguide core <NUM> may have opposite sidewalls <NUM>, <NUM> that converge at the facet <NUM>.

The waveguide core <NUM> may be positioned over a dielectric layer <NUM> and a substrate <NUM>. In an embodiment, the dielectric layer <NUM> may be comprised of a dielectric material, such as silicon dioxide, and the substrate <NUM> may be comprised of a semiconductor material, such as single-crystal silicon. In an embodiment, the dielectric layer <NUM> may be a buried oxide layer of a silicon-on-insulator substrate, and the dielectric layer <NUM> may separate the waveguide core <NUM> from the substrate <NUM>. The waveguide core <NUM> may be comprised of a semiconductor material, such as single-crystal silicon. In an embodiment, the waveguide core <NUM> may be formed by patterning a single-crystal silicon device layer of a silicon-on-insulator substrate with lithography and etching processes, and the dielectric layer <NUM> may operate as an etch stop when patterning the waveguide core <NUM>.

In the representative embodiment, the waveguide core <NUM> is embodied in a ridge waveguide core. In an alternative embodiment, the waveguide core <NUM> may be embodied in a rib waveguide core. In an alternative embodiment, the waveguide core <NUM> may be embodied in a slot waveguide core. In the representative embodiment, the waveguide core <NUM> is linear or straight. In an alternative embodiment, the waveguide core <NUM> may be curved. In an alternative embodiment, the waveguide core <NUM> may be non-tapered. In embodiments, the waveguide core <NUM> may be part of another optical component such as a polarization mode converter, an optical coupler, a multi-mode interference region, etc..

With reference to <FIG>, <FIG> in which like reference numerals refer to like features in <FIG> and at a subsequent fabrication stage according to an illustrative example not covered by the claims, a dielectric layer <NUM> is formed over the waveguide core <NUM> and dielectric layer <NUM>. The dielectric layer <NUM> may be comprised of a dielectric material, such as silicon dioxide. The waveguide core <NUM> is embedded in the dielectric layer <NUM>.

A back-end-of-line stack <NUM> is formed over the dielectric layer <NUM>. The back-end-of-line stack <NUM> may include a metallization level <NUM>, a metallization level <NUM>, and a metallization level <NUM>. The metallization level <NUM> is arranged in a vertical direction between the waveguide core <NUM> and the metallization level <NUM>. The metallization level <NUM> is arranged in a vertical direction between the metallization level <NUM> and the metallization level <NUM>. The metallization level <NUM> may include an interlayer dielectric layer <NUM>, the metallization level <NUM> may include an interlayer dielectric layer <NUM>, and the metallization level <NUM> may include an interlayer dielectric layer <NUM>. The interlayer dielectric layers <NUM>, <NUM>, <NUM> may be comprised of silicon dioxide.

A metal feature <NUM> may be formed in the interlayer dielectric layer <NUM> of the metallization level <NUM>, a metal feature <NUM> may be formed in the interlayer dielectric layer <NUM> of the metallization level <NUM>, and a metal feature <NUM> may be formed that connects the metal feature <NUM> to the metal feature <NUM>. The metal features <NUM>, <NUM>, <NUM>, which are arranged in a stack, may be positioned to overlap with a section <NUM> of the waveguide core <NUM>. The overlap is characterized by a portion of each of the metal features <NUM>, <NUM>, <NUM> being laterally positioned between the sidewalls <NUM>, <NUM> of the waveguide core <NUM>. The section <NUM> of the waveguide core <NUM> may be fully overlapped by the metal features <NUM>, <NUM>, <NUM>. The section <NUM> of the waveguide core <NUM> may have a length in a range of <NUM> microns to <NUM> microns.

The interlayer dielectric layer <NUM> of the metallization level <NUM> may be locally free of metal features between the section <NUM> of the waveguide core <NUM> and the metal features <NUM>, <NUM>, <NUM>. The metallization level <NUM> may be the closest metallization level of the back-end-of-line stack <NUM> to the waveguide core <NUM>, and the metallization level <NUM> may be separated from the waveguide core <NUM> by only the metallization level <NUM>. Alternatively, the metallization level <NUM> may be the closest metallization level of the back-end-of-line stack <NUM> to the waveguide core <NUM>, and the dielectric layers of additional metallization levels each locally free of metal features may be positioned between the metallization level <NUM> and the metallization level <NUM>. In an example, the metal features <NUM>, <NUM>, <NUM> are not connected to the waveguide core <NUM> or the substrate <NUM>, and the metal features <NUM>, <NUM>, <NUM> are not connected to other metal features in overlying metallization levels (not shown) of the back-end-of-line stack <NUM>.

The metal features <NUM>, <NUM>, <NUM> may define a heat sink <NUM> that is positioned adjacent to the section <NUM> of the waveguide core <NUM>. The metal features <NUM>, <NUM>, <NUM> may be formed by patterning, deposition, and polishing techniques characteristic of a damascene process. Specifically, the interlayer dielectric layers <NUM>, <NUM> may be deposited and patterned using lithography and etching processes to define trenches that are filled by a planarized metal (e.g., copper) to define the metal features <NUM>, <NUM> and to define a via opening that is filled by the metal to define the metal feature <NUM>. The metal features <NUM>, <NUM>, <NUM> may be spaced in a vertical direction from the section <NUM> of the waveguide core <NUM> by a spacing S, which may range from about <NUM> nanometers to about <NUM> micron. The metal feature <NUM> and the metal feature <NUM> may have a width W2 that is greater than the width W1 of the section <NUM> of the waveguide core <NUM>. For example, the width W2 may be equal to <NUM> microns.

In the illustrative example, the metal features <NUM>, <NUM>, <NUM> are linear or straight. Alternatively, the metal features <NUM>, <NUM>, <NUM> may be curved. Alternatively, the waveguide core <NUM> and the metal features <NUM>, <NUM>, <NUM> may be curved.

Light (e.g., laser light) may be directed from a light source <NUM> toward the facet <NUM> of the waveguide core <NUM>. The light may have a given wavelength, intensity, mode shape, and mode size, and the edge coupler providing the representative optical component may provide spot size conversion for the light. The light source <NUM> may be a semiconductor laser, and the semiconductor laser may be positioned inside a cavity formed in the substrate <NUM> and attached to the substrate <NUM>.

The structure <NUM> as described herein, may be integrated into a photonics chip that includes electronic components and additional optical components. For example, the electronic components may include field-effect transistors that are fabricated by CMOS processing.

The structure <NUM> provides one or more pathways for heat transfer to cool the waveguide core <NUM> and thereby reduce the susceptibility of the waveguide core <NUM> to possible optical power-related damage from, for example, high-power laser light. In particular, the heat sink <NUM> efficiently absorbs heat energy generated by light propagating in the waveguide core <NUM> and conducted as a heat flux through the intervening dielectric material to the metal features <NUM>, <NUM>, <NUM>. For example, the heat sink <NUM> may prevent power-related damage to the section <NUM> of the waveguide core <NUM> in the edge coupler receiving high-power laser light from the light source <NUM>.

With reference to <FIG>, <FIG> and in accordance with another illustrative example not covered by the claims, additional metal features <NUM>, <NUM>, <NUM> similar to the metal features <NUM>, <NUM>, <NUM> may be formed in the metallization levels <NUM>, <NUM> in order to expand the extent of the heat sink <NUM>. The set of metal features <NUM>, <NUM>, <NUM> and the set of metal features <NUM>, <NUM>, <NUM> may be laterally offset in opposite directions relative to the respective sidewalls <NUM>, <NUM> of the waveguide core <NUM>. The offset O1 of the set of metal features <NUM>, <NUM>, <NUM> and the offset O2 of the set of metal features <NUM>, <NUM>, <NUM> may be equal such that the waveguide core <NUM> is symmetrically positioned between the set of metal features <NUM>, <NUM>, <NUM> and the set of metal features <NUM>, <NUM>, <NUM>. The set of metal features <NUM>, <NUM>, <NUM> may be offset to have a non-overlapping arrangement with the waveguide core <NUM>, and the set of metal features <NUM>, <NUM>, <NUM> may also be offset to have a non-overlapping arrangement with the waveguide core <NUM>. The offsets O1, O2 may each be less than the width W2 of the metal features <NUM>, <NUM> and the metal features <NUM>, <NUM>. The metal features <NUM>, <NUM>, <NUM> may be disconnected from the metal features <NUM>, <NUM>, <NUM>.

In the illustrative example, the metal features <NUM>, <NUM>, <NUM> and the metal features <NUM>, <NUM>, <NUM> are linear or straight. Alternatively, the metal features <NUM>, <NUM>, <NUM> and the metal features <NUM>, <NUM>, <NUM> may be curved. Alternatively, the waveguide core <NUM>, the metal features <NUM>, <NUM>, <NUM>, and the metal features <NUM>, <NUM>, <NUM> may be curved.

With reference to <FIG> and in accordance with embodiments of the invention, the metal features <NUM>, <NUM>, <NUM> may be connected to metal features in a portion 25a of the back-end-of-line stack <NUM> that is laterally offset from the waveguide core <NUM> by a distance greater than the offset O1, and the metal features <NUM>, <NUM>, <NUM> may be connected to metal features in a portion 25b of the back-end-of-line stack <NUM> that is laterally offset from the waveguide core <NUM> by a distance greater than the offset O2. For example, the metal feature <NUM> may be physically connected by a bridging metal feature to a metal feature in the portion 25a of the back-end-of-line stack <NUM>, and the metal feature <NUM> may be physically connected by a bridging metal feature to a metal feature in the portion 25b of the back-end-of-line stack <NUM>. The metal features in the portions 25a, 25b of the back-end-of-line stack <NUM> may increase the ability of the heat sink <NUM> to reduce the operating temperature of the section <NUM> of the waveguide core <NUM> during use.

With reference to <FIG> and in accordance with a further illustrative example not covered by the claims, a heat sink <NUM> may include metal features <NUM>, <NUM> that are laterally positioned adjacent to the section <NUM> of the waveguide core <NUM>. The metal features <NUM>, <NUM> are offset in a lateral direction relative to opposite sides of the section <NUM> of the waveguide core <NUM>. The metal features <NUM>, <NUM> extend in a vertical direction to penetrate through the back-end-of-line stack <NUM> and the dielectric layer <NUM> to the substrate <NUM>. The metal features <NUM>, <NUM> may be formed by patterning openings extending through the back-end-of-line stack <NUM> and the dielectric layer <NUM> and then filling the openings with a metal (e.g., copper or tungsten). The connections of the metal features <NUM>, <NUM> to the substrate <NUM> may provide conduction paths that enhance heat transfer away from the section <NUM> of the waveguide core <NUM> and thereby improve cooling during operation.

With reference to <FIG> and in accordance with a further illustrative example not covered by the claims, the optical component represented by the waveguide core <NUM> may be replaced by a different type of optical component, such as a laser <NUM>, that is located adjacent to the metal features <NUM>, <NUM>. The laser <NUM> may be laterally positioned between the metal feature <NUM> and the metal feature <NUM>. The laser <NUM> may be disposed inside a cavity that is patterned in the substrate <NUM>. The heat sink <NUM> may receive heat generated by the laser <NUM> during operation and thereby reduce the operating temperature of the laser <NUM>.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.

References herein to terms modified by language of approximation, such as "about", "approximately", and "substantially", are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/- <NUM>% of the stated value(s).

References herein to terms such as "vertical", "horizontal", etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term "horizontal" as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction within the horizontal plane.

A feature "connected" or "coupled" to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to or with another feature if intervening features are absent. A feature may be "indirectly connected" or "indirectly coupled" to or with another feature if at least one intervening feature is present. A feature "on" or "contacting" another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be "directly on" or in "direct contact" with another feature if intervening features are absent. A feature may be "indirectly on" or in "indirect contact" with another feature if at least one intervening feature is present. Different features may overlap if a feature extends over, and covers a part of, another feature with either direct contact or indirect contact.

Claim 1:
A structure comprising:
a waveguide core (<NUM>) including a section (<NUM>); and
a back-end-of-line stack (<NUM>) including a first metallization level (<NUM>), a second metallization level (<NUM>), and a heat sink (<NUM>), the heat sink (<NUM>) having a first metal feature (<NUM>) being in the second metallization level (<NUM>), a second metal feature (25a) being in a portion of the back-end-of-line stack (<NUM>), and a third metal feature being a bridging metal feature connecting the first metal feature (<NUM>) to the second metal feature (25a), the heat sink (<NUM>) positioned adjacent to the section (<NUM>) of the waveguide core (<NUM>), and the first metallization level (<NUM>) including a dielectric layer positioned between the first metal feature (<NUM>) and the section (<NUM>) of the waveguide core (<NUM>), wherein the first metal feature (<NUM>) is laterally offset relative to the section (<NUM>) of the waveguide core (<NUM>) at a first offset distance (O1) such that the first metal feature (<NUM>) has a non-overlapping relationship with the section (<NUM>) of the waveguide core (<NUM>),
characterized in that
the second metal feature (25a) is laterally offset from the waveguide core (<NUM>) by a second offset distance that is greater than the first offset distance (O1).