Patent Description:
In a hybrid wafer bonding process, semiconductor structures having contact vias may be bonded together. However, the contact vias often have different sizes. This may result in interactions between a surface portion of a contact via of one semiconductor structure and a dielectric layer of the other semiconductor structure. For example, copper in the contact via may diffuse into the dielectric layer and degrade the quality of bonded wafers.

Conventional solutions for blocking metal diffusion include depositing a metal blocking layer on the bonding surface of each wafer. The metal blocking layer and the dielectric layer are made of different materials. When forming the contact via, an etch process may be performed on the metal blocking layer and the dielectric layer. Due to different etching rates, gaps may be formed between the metal blocking layer and the dielectric layer. Consequently, defects may occur in the contact via. <CIT> describes a method of manufacturing of a hybrid wafer bonding structure which includes depositing a blocking layer made of a dielectric different from the dielectric of the first and second insulating layer after etching of contact holes for contact pads. However, this blocking layer has to be consequently removed by etching from the bottom of the contact hole. <CIT> describes a hybrid wafer bonding structure which includes a first and a second wafer bonded to each other. The first wafer comprises a first substrate, a first insulating layer formed on the first substrate, and a first conductive pad embedded in the first insulating layer. The second wafer comprises a second substrate, a second insulating layer formed on the second substrate, and a second conductive pad embedded in the second insulating layer. The method of <CIT> includes depositing of additional first and second barrier layers separating the respective conductive pad from the respective insulating layer. The first and second conductive pads have the same surface area but do not completely overlap on the bonding interface. The blocking layer of <CIT> forms during a bonding process from the material of the first and second barrier layer and the first and second insulating layer in the area where the first and the second conductive pads are not bonded to each other. <CIT> describes a method of manufacture of a hybrid wafer bonding structure which employs air gaps on the bonding interface to block metal diffusion. The method of <CIT> includes thinning out the contact pads on their periphery to provide for a gap after contacting the surface of the first wafer with the surface of the second wafer. These methods require additional steps and are complicated.

The disclosed methods and structures are directed to solve one or more problems set forth above. The invention concerns the hybrid wafer bonding method according to the independent claim <NUM> and the hybrid wafer bonding structure according to the independent claim <NUM>. Dependent claims <NUM> to <NUM> and <NUM> to <NUM> concern various embodiments.

One aspect of the present disclosure includes a hybrid wafer bonding method according to claim <NUM>.

Another aspect of the present disclosure includes a hybrid wafer bonding structure according to claim <NUM>.

The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure.

The following describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings <NUM> to <NUM>. Apparently, the described embodiments are merely some but not all the embodiments of the present invention. Other embodiments obtained by a person skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present disclosure.

The hybrid wafer bonding method includes providing a first semiconductor structure and a second semiconductor structure, and bonding the first semiconductor structure with the second semiconductor structure to form a self-barrier layer that contains a multi-component oxide.

<FIG> illustrates a flowchart of an exemplary hybrid wafer bonding method according to a non-claimed example. Corresponding structures according to the non-claimed example are illustrated in <FIG>.

In S110 of <FIG>, a first semiconductor structure is provided. The first semiconductor structure may include a first substrate, a first dielectric layer formed on the first substrate, and a first via structure formed in the first dielectric layer and on the first substrate. A corresponding structure is shown in <FIG> as an example.

Referring to <FIG>, a first semiconductor structure <NUM> includes a first substrate <NUM>, a first dielectric layer <NUM> formed on the first substrate <NUM>, and a first via structure <NUM> formed in the first dielectric layer <NUM> and on the first substrate <NUM>.

The first substrate <NUM> may include a dielectric material, such as silicon oxide. Alternatively, the first substrate <NUM> may include any other suitable materials.

Referring to <FIG>, the first semiconductor structure <NUM> may further include a first barrier film <NUM> on the first substrate <NUM>. A first combination structure <NUM> may include a first barrier film <NUM>, the first dielectric layer <NUM> on the first barrier film <NUM>, and the first via structure <NUM> surrounded by the first dielectric layer <NUM> and the first barrier film <NUM>.

The first barrier film <NUM> may be a barrier film including a barrier material that blocks copper from diffusing, such as silicon nitride or nitrogen-doped silicon carbide (NDC), or any suitable material that blocks copper from diffusing.

The first dielectric layer <NUM> may be a dielectric layer including a dielectric material, such as silicon oxide.

Referring to <FIG>, the first via structure <NUM> may be a via that contain copper and metal impurities <NUM>. That is, the first via structure <NUM> may be a via that contains metal impurity-doped copper. A via may include conducting metal such as copper and include a portion inside a dielectric layer to form a path for conducting electrical currents.

In some examples, the first via structure <NUM> may be a first contact via that is to be in contact with and bonded with another contact via in the second semiconductor structure.

In some examples, the first via structure <NUM> may include one or more vias.

In some examples, the one or more vias may contain copper and metal impurities. The metal impurities may include at least one of Al, Mn, or Ag.

The first combination structure <NUM> includes a first bonding surface <NUM>. The first bonding surface <NUM> is a bonding surface that is to be bonded with another bonding surface in a second semiconductor structure for bonding the two surfaces and the two semiconductor structures.

In some examples, the first via structure <NUM> may include or may be a first contact via. The first bonding surface <NUM> includes a first contact via surface <NUM> of the first contact via and a first dielectric surface <NUM> in a same plane. The first contact via surface <NUM> is a surface of the first via structure <NUM> at one end of the first via structure <NUM>, and the end of the first via structure <NUM> is to be bonded with the second semiconductor structure. The first dielectric surface <NUM> is a surface of the first dielectric layer <NUM> at one end of the first dielectric layer <NUM>, and the end of the first dielectric layer <NUM> is to be bonded with the second semiconductor structure. In the orientation shown in <FIG>, the first contact via surface <NUM> is a top surface of the first via structure <NUM>, and the first dielectric surface <NUM> is a top surface of the first dielectric layer <NUM>.

In some examples, the first combination structure <NUM> may include a first barrier film <NUM>, a first dielectric layer <NUM> on the first barrier film <NUM>, and a first via structure <NUM>, and the first via structure is surrounded by the first dielectric layer <NUM> and the first barrier film <NUM> at sides of the first via structure <NUM>. In other examples, a first combination structure may include a first dielectric layer and a first via structure, and the first via structure is surrounded by the first dielectric layer at sides of first via structure.

In some examples, forming a combination structure such as the first combination structure may include forming a barrier film, forming a dielectric layer, and forming a via in the dielectric layer or the dielectric layer and the barrier film, where the via contains metal impurity-doped copper.

Forming a via containing copper doped with metal impurities (i.e., metal impurity-doped copper) in a dielectric layer such as a first dielectric layer may include forming a contact hole by etching in the dielectric layer, depositing a barrier layer on an inner surface of the contact hole, filling copper with metal impurities over the barrier layer in the contact hole to form the via. The barrier layer may be deposited on the inner surface of the contact hole to block copper from diffusing through the inner surface of the contact hole to the dielectric layer. The barrier layer may contain a barrier material that can block copper from diffusing, such as Ti, Ta, TiN, TaN, TiSiN or any combination thereof. Filling copper with metal impurities in the contact hole may include depositing a seed layer of metal impurity-doped copper over the barrier layer, electroplating copper in the contact hole, and smoothing a surface for the via and the dielectric layer. Depositing the seed layer of metal impurity-doped copper over the barrier layer may include sputtering a copper target and a target containing the metal impurities to deposit copper and the metal impurities to form the seed layer of metal impurity-doped copper by using a sputtering technique system, such as a magnetron sputtering system. After depositing a seed layer of metal impurity-doped copper over the barrier layer and electroplating copper in the contact hole, excess metal impurity-doped copper and copper may be introduced outside the contact hole, a surface for the via and the dielectric layer may be smoothed to remove the excess metal impurity-doped copper and copper and to obtain a smooth surface. The surface for the via and the dielectric layer may be smoothed by chemical-mechanical planarization (CMP).

In some examples, the first via structure <NUM> may penetrate through the first dielectric layer and the first barrier film in the first combination structure. In other examples, a first via structure may not penetrate through the first dielectric layer and the first barrier film in the first combination structure. For example, a bottom of a first via structure may end inside the first dielectric layer.

In S120 of <FIG>, a second semiconductor structure is provided. The second semiconductor may include a second substrate, a second dielectric layer formed on the second substrate, and a second via structure formed in the second dielectric layer and on the second substrate. A corresponding structure is shown in <FIG> as an example.

Referring to <FIG>, a second semiconductor structure <NUM> includes a second substrate <NUM>, a second dielectric layer <NUM> formed on the second substrate <NUM>, and a second via structure <NUM> formed in the second dielectric layer <NUM> and on the second substrate <NUM>.

The second substrate <NUM> may include a dielectric material, such as silicon oxide. Alternatively, the second substrate <NUM> may include any other suitable materials.

Referring to <FIG>, the second semiconductor structure may further include a second barrier film <NUM> on the second substrate <NUM>. A second combination structure <NUM> may include a second barrier film <NUM>, a second dielectric layer <NUM> on the second barrier film <NUM>, and a second via structure <NUM> surrounded by the second dielectric layer <NUM> and the second barrier film <NUM>.

The second barrier film <NUM> may be a barrier film including a barrier material that blocks copper from diffusing, such as silicon nitride or NDC, or any suitable material that blocks copper from diffusing.

The second dielectric layer <NUM> may be a dielectric layer including a dielectric material, such as silicon oxide.

In some non-claimed examples, referring to <FIG>, the second via structure <NUM> may be a via that contain copper and metal impurities <NUM>. That is, the second via structure <NUM> may be a via that contains metal impurity-doped copper. A via may include conducting metal such as copper and include a portion inside a dielectric layer to form a path for conducting electrical currents.

In some non-claimed examples, the second via structure <NUM> may be a second contact via that is to be in contact with and bonded with the first contact via in the first semiconductor structure.

In some examples, the second via structure <NUM> may include one or more vias.

The second combination structure <NUM> includes a second bonding surface <NUM>. The second bonding surface <NUM> is a bonding surface that is to be bonded with a first bonding surface in the first semiconductor structure for bonding the two surfaces and the two wafers.

In some examples, the second via structure <NUM> may include or may be a second contact via. The second bonding surface <NUM> includes a second contact via surface <NUM> of the second contact via and a second dielectric surface <NUM> in a same plane. The second contact via surface <NUM> is a surface of the second via structure <NUM> at one end of the second via structure <NUM>, the end of the second via structure <NUM> is to be bonded with the first semiconductor structure. The second dielectric surface <NUM> is a surface of the second dielectric layer <NUM> at one end of the second dielectric layer <NUM>, and the end of the second dielectric layer <NUM> is to be bonded with the first semiconductor structure. In the orientation shown in <FIG>, the second contact via surface <NUM> is a top surface of the second via structure <NUM>, and the second dielectric surface <NUM> is a top surface of the second dielectric layer <NUM>.

In some examples, the second combination structure <NUM> may include a second barrier film <NUM>, a second dielectric layer <NUM> on the second barrier film <NUM>, and a second via structure <NUM>; and the second via structure <NUM> is surrounded by the second dielectric layer <NUM> and the second barrier film <NUM> at sides of the second via structure <NUM>. In other embodiments, a second combination structure may include a second dielectric layer and a second via structure; and the second via structure is surrounded by the second dielectric layer at sides of the second via structure.

Forming the second combination structure is same as or similar to forming the first combination structure. In some embodiments, forming a combination structure such as the second combination structure may include forming a barrier layer, forming a dielectric layer, and forming a via containing metal impurity-doped copper in the dielectric layer or in the dielectric layer and the barrier layer. References can be made to the above descriptions for forming the first combination structure.

In some examples, the second via structure <NUM> may penetrate through the second dielectric layer and the second barrier film in the second combination structure. In other examples, a second via structure may not penetrate through the second dielectric layer and the second barrier film in the second combination structure. For example, a bottom of the second via structure may end inside the second dielectric layer.

In some examples, the first contact via surface <NUM> may have a larger bonding area than the second contact via surface <NUM>, and may cover the area of the second contact via surface <NUM> when the first contact via surface <NUM> and the second contact via surface <NUM> are bonded. In other words, the first contact via surface <NUM> may be a bonding surface of the first via structure <NUM>, and the second contact via surface <NUM> may be a bonding surface of the second via structure <NUM>, and the first contact via surface <NUM> may be larger than the second contact via surface <NUM>.

In some examples, the first contact via surface <NUM> may have a larger area than the second contact via surface <NUM>. The one or more vias in the first via structure <NUM> may contain copper and metal impurities. The one or more vias in the second via structure <NUM> may contain copper or contain copper and metal impurities.

<FIG> illustrates a schematic structural diagram of an exemplary structure of hybrid wafer bonding according to a non-claimed example. <FIG> illustrates a schematic structural diagram of another exemplary structure of hybrid wafer bonding according to various non-claimed examples.

In S130 of <FIG>, the first semiconductor structure is bonded with the second semiconductor structure by attaching the first contact via surface with the second contact via surface, where the second contact via surface and the first contact via surface have different surface areas and have an overlapped interface. A corresponding structure is shown in <FIG> as an example.

Referring to <FIG>, the first semiconductor structure is bonded with the second semiconductor structure by attaching the first contact via surface with the second contact via surface, where the second contact via surface and the first contact via surface have different surface areas and have an overlapped interface.

In some examples, the first semiconductor structure and the second semiconductor structure may be oriented such that the first bonding surface <NUM> and the second bonding surface <NUM> face toward each other. For example, the second semiconductor structure may be oriented upside down such that the second bonding surface is oriented downward to face toward the first bonding surface that is facing upward.

The first semiconductor structure and the second semiconductor structure may be oriented in various manners, as long as the second bonding surface and the first bonding surface face toward each other. For example, the first semiconductor structure may be oriented upside down such that the first bonding surface is oriented downward, and the second semiconductor structure may be oriented such that the second bonding surface faces upward. Accordingly, the first bonding surface and the second bonding surface oriented toward each other.

Further, the first bonding surface and the second bonding surface are in direct contact with each other and bonded together. Referring to <FIG>, the second semiconductor structure is upside down, and the first semiconductor structure and the second semiconductor structure are bonded together. The first dielectric layer <NUM> is integrated with the second dielectric layer <NUM>. The first via structure <NUM> is integrated with the second via structure <NUM> to form an integrated via structure <NUM>.

A bonding interface <NUM> is the interface formed at the location where the first bonding surface is in contact with the second bonding surface as the two semiconductor structures are bonded.

The first via structure <NUM> and the second via structure <NUM> are conductive. An electrically conductive path is formed from the bottom to the top of the integrated via structure <NUM>.

In S140 of <FIG>, a self-barrier layer is formed on a non-overlapped surface of one or more of the first and second contact via surfaces by an alloying process between the first semiconductor structure and the second semiconductor structure, where the self-barrier layer is formed by multi-component oxides corresponding to the metal impurities. A corresponding structure is shown in <FIG> as an example.

Referring to <FIG>, a self-barrier layer <NUM> is formed on a non-overlapped surface of one or more of the first and second contact via surfaces by an alloying process between the first semiconductor structure and the second semiconductor structure. The self-barrier layer contains a multi-component oxide and blocks copper from diffusing to the dielectric layers.

In some examples, the alloying process between the first semiconductor structure and the second semiconductor structure may include annealing the first semiconductor structure and the second semiconductor structure to diffuse the metal impurities to the bonding interface to form the self-barrier layer that contains a multi-component oxide. The metal impurities may react with oxides at the interface to form the multi-component oxide. The self-barrier layer that contains the multi-component oxide that blocks copper from diffusing to the dielectric layers, i.e., the first dielectric layer and the second dielectric layer.

In some examples, the alloying process may further include applying a pressure on one or more of the first semiconductor structure and the second semiconductor structure.

The self-barrier layer <NUM> is on a non-overlapped surface of one or more of the first and second contact via surfaces. The self-barrier layer <NUM> corresponds to an orthogonal projection region at the bonding interface <NUM>, referred to as a "self-barrier region. " The self-barrier region is an orthogonal projection of the self-barrier layer <NUM> on the plane of the bonding interface <NUM>. The self-barrier region includes sub-regions that are within the first contact via surface and outside the second contact via surface and sub-regions that are outside the first contact via surface and within the second contact via surface.

The self-barrier layer <NUM> contains the multi-component oxide that is formed by the oxide and one or more metal impurities in the bonded wafers, and hence eliminates the need to perform an extra deposition process for depositing a barrier layer at the bonding interface <NUM>.

In the exemplary scenarios that the first contact via surface covers the second contact via surface, sub-regions that are outside the first contact via surface and within the second contact via surface do not exist and the self-barrier region includes sub-regions that are within the first contact via surface and outside the second contact via surface.

The self-barrier layer <NUM> may contain one or more multi-component oxides. During the annealing process, the metal impurities in the first via structure and/or the second via structure may diffuse to the self-barrier region. Further, the metal impurities may react with the oxide in the dielectric layers at the bonding interface <NUM>, e.g., the oxide in the second dielectric layer, to form a multi-component oxide in the self-barrier layer <NUM>.

The metal impurities in the vias may be at least one of Al, Mn, or Ag. The multi-component oxide may contain Si, O, and the at least one of Al, Mn, or Ag.

In some examples, the metal impurities may be Al, and the oxide may be silicon oxide, and the multi-component oxide may contain Al, Si, and O, such as Six1Aly1Oz1 (i.e., silicon aluminum oxide), where x1, y1, and z1 are suitable numbers.

In some examples, the metal impurities may be Mn, and the oxide may be silicon oxide, and the multi-component oxide may contain Mn, Si, and O, such as Six2Mny2Oz2, where x2, y2, and z2 are suitable numbers.

In some examples, the metal impurities may be Ag, and the oxide may be silicon oxide, and the multi-component oxide may contain Ag, Si, and O, such as Six3Agy3Oz3, where x3, y3, and z3 are suitable numbers.

In some examples, annealing the first semiconductor structure and the second semiconductor structure may include increasing the temperature of the first semiconductor structure and the second semiconductor structure and decreasing the temperature of the first semiconductor structure and the second semiconductor structure.

In some examples, annealing the first semiconductor structure and the second semiconductor structure may include increasing the temperature of the first semiconductor structure and the second semiconductor structure and decreasing slowly the temperature of the first semiconductor structure and the second semiconductor structure.

In some examples, annealing the first semiconductor structure and the second semiconductor structure may include increasing the temperature of the first semiconductor structure and the second semiconductor structure from an original temperature value to a predetermined temperature value, keeping the temperature of the first semiconductor structure and the second semiconductor structure at the predetermined temperature value for a predetermined time interval, and decreasing the temperature of the first semiconductor structure and the second semiconductor structure to the original temperature value. The original temperature value may be a temperature value of room temperature.

The predetermined temperature value may be, for example, about <NUM>. The predetermined time interval may be, for example, approximately <NUM> minutes. That is, the temperature of the first semiconductor structure and the second semiconductor structure may be, for example, increased from an original temperature value to about <NUM>, and kept at about <NUM> for approximately <NUM> minutes, and decreased to the original temperature value.

In some examples, annealing the first semiconductor structure and the second semiconductor structure may include increasing the temperature of the first semiconductor structure and the second semiconductor structure from an original temperature value to a predetermined temperature value, keeping the temperature of the first semiconductor structure and the second semiconductor structure at the predetermined temperature value for a predetermined time interval, and decreasing the temperature of the first semiconductor structure and the second semiconductor structure to the original temperature value at a temperature reducing speed by using a temperature controller that includes a feedback control system. The predetermined temperature value, the predetermined time interval for keeping at the predetermined temperature value, and/or the temperature reducing speed may be determined according to properties associated with the multi-component oxide, the metal impurity, and/or the oxide in the second and first dielectric layers.

The present disclosure provides hybrid wafer bonding method according to the invention.

<FIG> illustrates hybrid wafer bonding method according to various embodiments of the present invention. Corresponding structure are illustrated in <FIG>. For processes of the hybrid wafer bonding method according to the invention is illustrated in <FIG> including S110', S120', S130', and S140', references can be made to the above descriptions of processes of the one or more exemplary methods such as the method described in connection with <FIG>, including S110, S120, S130, and S140.

In S110' of <FIG>, a first semiconductor structure is provided, where a first via structure includes a first switch element and a first contact via. The first semiconductor structure includes a first substrate, a first dielectric layer formed on the first substrate, and a first via structure formed in the first dielectric layer and on the first substrate, where the first via structure includes a first switch element and a first contact via. A corresponding structure is shown in <FIG> as an example.

Referring to <FIG>, a first semiconductor structure <NUM>' includes a first substrate <NUM>, a first dielectric layer <NUM> formed on the first substrate <NUM>, and a first via structure <NUM>' formed in the first dielectric layer <NUM> and on the first substrate <NUM>. The first via structure <NUM>' includes a first switch element <NUM> and a first contact via <NUM>. The first substrate <NUM> includes an insulating layer <NUM> and a conducting layer <NUM>. The first semiconductor structure may further include a first barrier film <NUM> on the first substrate <NUM>.

A first combination structure <NUM> may include the first via structure <NUM>', the first dielectric layer <NUM>. The first combination structure <NUM> may further include the first barrier film <NUM>.

The insulating layer <NUM> may include an insulating material. In some embodiments, the insulating material may be silicon oxide.

In some embodiments, a hole may be formed in the insulating layer <NUM> by etching and the conductive layer <NUM> may be formed in the hole. The conductive layer <NUM> is surrounded by the insulating layer <NUM> at sides of and a bottom of the conductive layer <NUM> and has a top exposed from the insulating layer <NUM>.

In some embodiments, the conductive layer <NUM> may include a metal material such as copper. Further, a barrier layer (not shown in <FIG>) may be formed between the conductive layer <NUM> and the insulating layer <NUM> to block copper in the conductive layer <NUM> from diffusing into the insulating layer <NUM>. For example, a barrier layer may be deposited on inner surfaces of the hole formed in the insulating layer <NUM>, e.g., an inner wall of the hole formed in the insulating layer <NUM> and a surface of the hole at one end of the hole, and further the conductive layer <NUM> is formed over the barrier layer. The barrier layer may contain a barrier material that can block copper from diffusing, such as Ti, Ta, TiN, TaN, TiSiN or any combination thereof.

In some embodiments, referring to <FIG>, the first barrier film <NUM> may be a barrier film including a barrier material that blocks copper of the conductive layer <NUM> from diffusing, such as silicon nitride or NDC, or any suitable material that blocks copper from diffusing.

A first dielectric layer <NUM> may be formed on the first barrier film <NUM>.

In some embodiments, the first dielectric layer <NUM> may be a dielectric layer that contains a dielectric material. The dielectric material may be silicon oxide.

A first via structure <NUM>' includes a first switch element <NUM> and a first contact via <NUM>. The first combination structure <NUM> contains a first bonding surface, and the first switch element <NUM> and the first contact via <NUM> contain copper and metal impurities.

In some embodiments, a first switch element may be a via that penetrates the first dielectric layer and/or the first barrier film and is in contact with the first substrate. The first switch element may penetrate the first dielectric layer and/or the first barrier film by itself or together with one or more other vias, e.g., together with a first contact via.

A contact hole may be formed in the first barrier film <NUM> and the first dielectric layer <NUM> by etching. The contact hole may include a groove on the first substrate and a trench connected to and on the groove. The groove extends from the first dielectric layer <NUM> to a bottom of the first barrier film <NUM> to be in contact with the first substrate. The trench is connected to and on the groove. The trench extends from a top of the first dielectric layer <NUM> to a depth in the first dielectric layer <NUM>. The trench has a larger lateral dimension than the groove.

The first switch element <NUM> may be formed in the groove and the first contact via <NUM> may be formed in contact with the first switch element <NUM> and in the trench. The first switch element <NUM> may be formed penetrating the first barrier film <NUM> between the first substrate <NUM> and the first dielectric layer <NUM> and on the conductive layer <NUM>.

According to the present invention, an orthogonal projection of the first contact via <NUM> on the first substrate <NUM> is greater than an orthogonal projection of the first switch element <NUM> on the first substrate <NUM> in area.

In some embodiments, a barrier layer may be deposited over inner surfaces of the groove and the trench, e.g., the inner walls of the groove and inner walls and surfaces <NUM> of the trench at an end of the trench. The barrier layer may contain a barrier material that can block copper from diffusing, such as Ti, Ta, TiN, TaN, TiSiN or any combination thereof.

Further, a first switch element <NUM> is formed in the groove and the first contact via <NUM> is formed in the trench by introducing copper doped with metal impurities <NUM>. The metal impurities <NUM> may include at least one of Al, Mn, or Ag. One end of the first switch element <NUM> is connected to the first contact via <NUM>. Another end of the first switch element <NUM> is connected to the conductive layer <NUM>.

The first via structure <NUM>' includes the first switch element <NUM> and the first contact via <NUM>. The first combination structure <NUM> may include the first barrier film <NUM>, the first dielectric layer <NUM>, and the first via structure <NUM>'.

The first combination structure <NUM> contains the first bonding surface <NUM>. The first bonding surface <NUM> includes a first contact via surface <NUM> and a first dielectric surface <NUM> in a same plane. In some embodiments, the first contact via surface <NUM> may be a surface of the first contact via <NUM> and a surface of the first via structure <NUM>'.

The first contact via surface <NUM> is a surface of the first via structure <NUM>' at one end of the first via structure <NUM>', and the end of the first via structure <NUM>' is to be bonded with the second semiconductor structure. The first dielectric surface <NUM> is a surface of the first dielectric layer <NUM> at one end of the first dielectric layer <NUM>, and the end of the first dielectric layer <NUM> is to be bonded with the second semiconductor structure. In the orientation shown in <FIG>, the first contact via surface <NUM> is a top surface of the first via structure <NUM>' and a top surface of the first contact via <NUM>, and the first dielectric surface <NUM> is a top surface of the first dielectric layer <NUM>.

In S120' of <FIG>, a second semiconductor structure is provided, where a second via structure includes a second switch element and a second contact via. The second semiconductor includes a second substrate, a second dielectric layer formed on the second substrate, and a second via structure formed in the second dielectric layer and on the second substrate, where a second via structure includes a second switch element and a second contact via. A corresponding structure is shown in <FIG> as an example.

Referring to <FIG>, a second semiconductor structure <NUM>' includes a second substrate <NUM>, a second dielectric layer <NUM> formed on the second substrate <NUM>, and a second via structure <NUM>' formed in the second dielectric layer <NUM> and on the second substrate <NUM>. The second via structure <NUM>' includes a second switch element <NUM> and a second contact via <NUM>. The second substrate <NUM> includes an insulating layer <NUM> and a conducting layer <NUM>. The second semiconductor structure may further include a second barrier film <NUM> on the second substrate <NUM>.

A second combination structure <NUM> may include the second via structure <NUM>' and the second dielectric layer <NUM>. The second combination structure <NUM> may further include the second barrier film <NUM>.

In some embodiments, referring to <FIG>, the insulating layer <NUM> may include an insulating material such as silicon oxide.

In some embodiments, a hole may be formed in the insulating layer <NUM> by etching and the conductive layer <NUM> may be formed in the hole. The conductive layer <NUM> is surrounded by the insulating layer <NUM> at sides of and a bottom of the conductive layer <NUM> and has a top exposed from the insulating layer <NUM>. The second substrate <NUM> includes the insulating layer <NUM> and the conductive layer <NUM>.

In some embodiments, the conductive layer <NUM> may include a metal material such as copper. Further, a barrier layer (not shown in <FIG>) may be formed between the conductive layer <NUM> and the insulating layer <NUM> to block copper in the conductive layer <NUM> from diffusing to the insulating layer <NUM>. For example, a barrier layer may be deposited on inner surfaces of the hole formed in the insulating layer <NUM>, e.g., inner walls and an end, e.g., a bottom, of the hole formed in the insulating layer <NUM>, and further the conductive layer <NUM> is formed over the barrier layer.

A second barrier film <NUM> may be deposited on the second substrate <NUM>.

In some embodiments, referring to <FIG>, the second barrier film <NUM> may be a barrier film including a barrier material that blocks copper in the conductive layer <NUM> from diffusing, such as silicon nitride or NDC, or any suitable material that blocks copper from diffusing.

A second dielectric layer <NUM> may be formed on the second barrier film <NUM>.

In some embodiments, the second dielectric layer <NUM> may be a dielectric layer that contains a dielectric material. The dielectric material may be silicon oxide.

A second via structure <NUM>' includes a second switch element <NUM> and a second contact via <NUM>. The second combination structure <NUM> contains the second bonding surface <NUM>. The second switch element <NUM> and the second contact via <NUM> contain copper, or copper and metal impurities <NUM>.

In some embodiments, a second switch element may be a via that penetrates the second dielectric layer and/or the second barrier film and is in contact with the second substrate. The second switch element may penetrate the second dielectric layer and/or the second barrier film by itself or together with one or more other vias, e.g., together with a second contact via.

A contact hole may be formed in the second barrier film <NUM> and the second dielectric layer <NUM> by etching. The contact hole may include a groove on the second substrate <NUM> and a trench connected to and on the groove. The groove extends from the second dielectric layer <NUM> to a bottom of the second barrier film <NUM> to be in contact with the second substrate <NUM>. The trench is connected to and on the groove. The trench extends from a top of the second dielectric layer <NUM> to a depth in the second dielectric layer <NUM>. The trench has a larger lateral dimension than the groove.

The second switch element <NUM> may be formed in the groove and the second contact via <NUM> may be formed in contact with the second switch element and in the trench. The second switch element may be formed penetrating the second barrier film between the second substrate and the second dielectric layer and on the conductive layer.

In some embodiments, a barrier layer may be deposited over inner surfaces of the groove and the trench, e.g., the inner walls of the groove and inner walls and surfaces <NUM> of the trench at one end of the trench. The barrier layer may contain a barrier material that can block copper from diffusing, such as Ti, Ta, TiN, TaN, TiSiN or any combination thereof.

Further, a second switch element <NUM> is formed in the groove and a second contact via <NUM> is formed in the trench by introducing copper doped with metal impurities <NUM>. The metal impurities may include at least one of Al, Mn, or Ag. One end of the second switch element <NUM> is connected to the second contact via <NUM>. Another end of the second switch element <NUM> is connected to the conductive layer <NUM>.

The second via structure <NUM>' includes the second switch element <NUM> and the second contact via <NUM>. The second combination structure <NUM> includes the second barrier film <NUM>, the second dielectric layer <NUM>, and the second via structure <NUM>'.

The second combination structure <NUM> contains the second bonding surface <NUM>. The second bonding surface <NUM> includes a second contact via surface <NUM> and a second dielectric surface <NUM> in a same plane. In some embodiments, the second contact via surface <NUM> may be a surface of the second contact via <NUM> and a surface of the second via structure <NUM>'.

The second contact via surface <NUM> is a surface of the second via structure <NUM>' at one end of the second via structure <NUM>', and the end of the second via structure <NUM>' is to be bonded with the first semiconductor structure. The second dielectric surface <NUM> is a surface of the second dielectric layer <NUM> at one end of the second dielectric layer <NUM>, and the end of the second dielectric layer <NUM> is to be bonded with the first semiconductor structure. In the orientation shown in <FIG>, the second contact via surface <NUM> is a top surface of the second via structure <NUM>' and a top surface of the second contact via <NUM>, and the second dielectric surface <NUM> is a top surface of the second dielectric layer <NUM>.

In some embodiments, the first contact via surface <NUM> has a larger area than the second contact via surface <NUM>.

In S130' of <FIG>, the first semiconductor structure is bonded with the second semiconductor structure by attaching the first contact via surface with the second contact via surface, where the second contact via surface and the first contact via surface have different surface areas and have an overlapped interface. A corresponding structure is shown in <FIG> as an example.

Referring to <FIG>, the first semiconductor structure is bonded with the second semiconductor structure by attaching the first contact via surface with the second contact via surface, where the second contact via surface and the first contact via surface have different surface areas and have an overlapped interface. The second semiconductor structure is arranged upside down as compared to the orientation of the second semiconductor structure in <FIG>, and the first semiconductor structure and the second semiconductor structure are bonded together. The first dielectric layer <NUM> is integrated with the second dielectric layer <NUM>, and the first via structure <NUM>' is integrated with the second via structure <NUM>' to form an integrated via structure.

The first via structure <NUM>' and the second via structure <NUM>' are conductive. Thus, the conductive layer <NUM> is electrically connected to the conductive layer <NUM> by the first via structure <NUM>' and the second via structure <NUM>'. That is, the conductive layer <NUM> is electrically connected to the conductive layer <NUM> by an electrically conductive path that includes the first switch element <NUM>, the first contact via <NUM>, the second contact via <NUM>, and the second switch element <NUM>.

In S140' of <FIG>, a self-barrier layer is formed on a non-overlapped surface of one or more of the first and second contact via surfaces by an alloying process between the first semiconductor structure and the second semiconductor structure, where the self-barrier layer is formed by one or more multi-component oxides corresponding to the metal impurities. A corresponding structure is shown in <FIG> as an example.

In some embodiments, the alloying process between the first semiconductor structure and the second semiconductor structure may include annealing the first semiconductor structure and the second semiconductor structure to diffuse the metal impurities to the bonding interface to form the self-barrier layer that contains a multi-component oxide. The metal impurities may react with the oxide at the interface to form the multi-component oxide. The self-barrier layer that contains the multi-component oxide blocks copper from diffusing to the dielectric layers, i.e., the first dielectric layer and the second dielectric layer.

In some embodiments, the alloying process may further include applying a pressure on one or more of the first semiconductor structure and the second semiconductor structure.

Referring to <FIG>, the self-barrier layer <NUM> is formed in a region at the bonding interface <NUM>. The self-barrier layer <NUM> corresponds to an orthogonal projection region at the bonding interface, referred to as a "self-barrier region. " The self-barrier region is an orthogonal projection of the self-barrier layer <NUM> on the plane of the bonding interface <NUM>. The self-barrier region includes sub-regions that are within the first contact via surface and outside the second contact via surface and sub-regions that are outside the first contact via surface and within the second contact via surface.

The self-barrier layer <NUM> may contain one or more multi-component oxides. During the annealing process, the metal impurities in the first via structure and/or the second via structure may diffuse to the self-barrier region. Further, the metal impurities may react with the oxide in the dielectric layers at the bonding interface <NUM>, e.g., the oxide in the second dielectric layer, to form a multi-component oxide.

The multi-component oxide may contain Si, O, and at least one of Al, Mn, or Ag.

In some embodiments, the metal impurities may be Al, and the oxide may be silicon oxide, and the multi-component oxide may contain Al, Si, and O. , such as Six1Aly1Oz1, where x1, y1, and z1 are suitable numbers.

In some embodiments, the metal impurities may be Mn, and the oxide may be silicon oxide, and the multi-component oxide may contain Mn, Si, and O, such as Six2Mny2Oz2, where x2, y2, and z2 are suitable numbers.

In some embodiments, the metal impurities may be Ag, and the oxide may be silicon oxide, and the multi-component oxide may contain Ag, Si, and O, such as Six3Agy3Oz3, where x3, y3, and z3 are suitable numbers.

The present disclosure provides a wafer structure of hybrid bonding. The structure contains bonded semiconductor structures and a self-barrier layer that contains a multi-component oxide and blocks copper from diffusing to a dielectric layer in the structure.

<FIG> illustrates an exemplary structure of hybrid wafer bonding according to a non-claimed example.

The structure of hybrid wafer bonding includes a first semiconductor structure, a second semiconductor structure, and a self-barrier layer.

Specifically, the structure of hybrid wafer bonding includes a first substrate <NUM>, a first combination structure <NUM> on the first substrate, a second combination structure <NUM> on the first combination structure <NUM>, and a second substrate <NUM> on the second combination structure <NUM>, a bonding interface <NUM>, and a self-barrier layer <NUM>. The bonding interface <NUM> is formed at the boundary where the second combination structure <NUM> and the first combination structure are in contact with each other.

The first combination structure <NUM> includes a first barrier film <NUM> on the first substrate <NUM>, a first dielectric layer <NUM> on the first barrier film <NUM>, and a first via structure <NUM> surrounded by the first dielectric layer <NUM> and the first barrier film <NUM>.

The first via structure <NUM> includes a via. A via may include conducting metal such as copper and include portions inside a dielectric layer to form a path for conducting electrical currents.

Referring to <FIG>, the second combination structure <NUM> includes a second dielectric layer <NUM>, a second barrier film <NUM> on the second dielectric layer <NUM>, a second via structure <NUM> surrounded by the second dielectric layer <NUM> and the second barrier film <NUM>.

The first via structure <NUM> includes a first contact via surface that is at one end of the first via structure <NUM> and the end of the first via structure <NUM> is bonded with the second semiconductor structure. The second via structure <NUM> includes a second contact via surface that is a surface of the second via structure <NUM> at one end of the second via structure <NUM> and the end of the second via structure <NUM> is bonded with the first semiconductor structure.

The self-barrier layer <NUM> is formed in a region at the bonding interface <NUM>. The self-barrier layer <NUM> corresponds to an orthogonal projection region at the bonding interface <NUM>, referred to as a "self-barrier region. " The self-barrier region is an orthogonal projection of the self-barrier layer <NUM> on the plane of the bonding interface <NUM>. The self-barrier region may include sub-regions that are within the first contact via surface and outside the second contact via surface and sub-regions that are outside the first contact via surface and within the second contact via surface.

For the exemplary structure of hybrid wafer bonding, references can be made to the descriptions for method examples.

The self-barrier layer <NUM> may contain one or more multi-component oxides. During the annealing process, the metal impurities in the first via structure and/or the second via structure may diffuse to the self-barrier region. Further, the metal impurities may react with the oxide in the dielectric layer at the bonding interface <NUM>, e.g., the oxide in the second dielectric layer, to form a multi-component oxide in the self-barrier layer <NUM>.

The metal impurities in the vias may be at least one of Al, Mn, or Ag. The multi-component oxide may contain Si, O, and the at least one of Al, Mn, or Ag. For example, the metal impurities in the vias may be Al, and the oxide may be silicon oxide, and the multi-component oxide may contain Al, Si and O, such as Six1Aly1Oz1, where x1, y1, and z1 are suitable numbers.

The self-barrier layer <NUM> that contains a multi-component oxide and blocks copper from diffusing to the dielectric layers across the bonding interface <NUM>. Barrier layers deposited over the inner surfaces of the contact holes in the first dielectric layer <NUM> and the second dielectric layer <NUM>, such as the inner walls of the contact holes in the first dielectric layer <NUM> and the second dielectric layer <NUM>, may block copper from diffusing to the dielectric layers through the inner surfaces of the contact holes.

The present disclosure provides a structure of hybrid wafer bonding according to the invention. The structure includes bonded semiconductor structure and a self-barrier layer that contains a multi-component oxide to block copper from diffusing to the dielectric layer.

<FIG> illustrates a structure of hybrid wafer bonding according to various embodiments of the present invention.

Specifically, the structure of hybrid wafer bonding includes a first substrate <NUM>, a first combination structure <NUM> on the first substrate, a second combination structure <NUM> on the first combination structure <NUM>, and a second substrate <NUM> on the second combination structure <NUM>, a bonding interface <NUM>, and a self-barrier layer <NUM>. The bonding interface <NUM> is formed at the boundary where the second combination structure <NUM> and the first combination structure <NUM> are in contact with each other.

The first substrate <NUM> includes an insulating layer <NUM> and a conductive layer <NUM> in the insulating layer <NUM>. The conductive layer <NUM> is surrounded by the insulating layer <NUM> at sides of and a bottom of the conductive layer <NUM> and has a top exposed from the insulating layer <NUM>.

The first combination structure <NUM> includes a first barrier film <NUM> on the first substrate <NUM>, a first dielectric layer <NUM> on the first barrier film <NUM>, and a first via structure <NUM>' surrounded by the first dielectric layer <NUM> and the first barrier film <NUM>.

The first via structure <NUM>' includes a first switch element <NUM> and a first contact via <NUM> in contact with one end of the first switch element <NUM>. The first switch element <NUM> has another end in contact with the conductive layer <NUM>. A via may include conducting metal such as copper and include portions inside a dielectric layer to form a path for conducting electrical currents.

The second combination structure <NUM> includes a second dielectric layer <NUM>, a second barrier film <NUM> on the second dielectric layer <NUM>, and a second via structure <NUM>' surrounded by the second dielectric layer <NUM> and the second barrier film <NUM>.

The second via structure <NUM>' includes a second contact via <NUM> and a second switch element <NUM> having one end in contact with the second contact via <NUM>. The second switch element <NUM> has another end in contact with the conductive layer <NUM> of the second substrate <NUM>.

The first via structure <NUM>' includes a first contact via surface that is a surface of the first via structure <NUM>' at one end of the first via structure <NUM>' and the end of the first via structure <NUM>' is bonded with the second semiconductor structure. The second via structure <NUM>' includes a second contact via surface that is a surface of the second via structure <NUM>' at one end of the second via structure <NUM>' and the end of the second via structure <NUM>' is bonded with the first semiconductor structure.

The self-barrier layer <NUM> is formed in a region at the bonding interface <NUM>. The self-barrier layer <NUM> corresponds to an orthogonal projection region at the bonding interface <NUM>, referred to as a "self-barrier region. " The self-barrier region is an orthogonal projection of the self-barrier layer <NUM> on the plane of the bonding interface <NUM>. The self-barrier region includes sub-regions that are within the first contact via surface and outside the second contact via surface and sub-regions that are outside the first contact via surface and within the second contact via surface.

For the self-barrier region, references can be made to the descriptions for method embodiments.

The metal impurities in the vias may be at least one of Al, Mn, or Ag. The multi-component oxide may contain Si, O, and the least one of Al, Mn, or Ag. For example, the metal impurities may be Al, and the oxide may be silicon oxide, and the multi-component oxide may contain Al, Si, and O, such as Six1Aly1Oz1, where x1, y1, and z1 are suitable numbers.

The self-barrier layer <NUM> contains a multi-component oxide and blocks copper from diffusing to the dielectric layers. Barrier layers deposited over the inner surfaces of the contact holes in the first dielectric layer <NUM> and the second dielectric layer <NUM> can block copper from diffusing to the dielectric layers through the inner surfaces of the contact holes.

In some embodiments, the inner surfaces of the contact hole in the first dielectric layer <NUM> and the first barrier film <NUM> may include the inner walls and the surfaces <NUM> of the contact hole in the first dielectric layer <NUM>. The contact hole may include a groove on the first substrate and a trench connected to and on the groove. The surfaces <NUM> of the contact hole in the first dielectric layer <NUM> is at one end of the trench and is outside the groove laterally. The end of the trench is closer to the groove in the first dielectric layer <NUM> than the bonding interface <NUM>.

In some embodiments, the inner surfaces of the contact hole in the second dielectric layer <NUM> and the second barrier film <NUM> may include the inner walls and the surfaces <NUM> of the contact hole in the second dielectric layer <NUM>. The contact hole may include a groove on the second substrate and a trench connected to and on the groove. The surfaces <NUM> of the contact hole in the second dielectric layer <NUM> is at one end of the trench and is outside the groove laterally. The end of the trench is closer to the groove in the second dielectric layer <NUM> than the bonding interface <NUM>.

In some embodiments, the self-barrier layer <NUM> may block copper from diffusing through the bonding interface <NUM> to the dielectric layers including the integrated first dielectric layer <NUM> and second dielectric layer <NUM>. Diffusion of copper through the bonding interface is prevented without the need to deposit barrier layers on the bonding surfaces.

In some embodiments, barrier layers deposited on the inner surfaces of the contact holes in the dielectric layers may block copper from diffusing through the inner surfaces of the contact holes to the dielectric layers. The barrier layer may contain a barrier material that can block copper from diffusing, such as Ti, Ta, TiN, TaN, TiSiN or any combination thereof.

In some embodiments, the conductive layer <NUM> and the conductive layer <NUM> may contain copper. The first barrier film <NUM> may block copper in the conductive layer <NUM> from diffusing to the dielectric layers including the integrated first dielectric layer <NUM> and second dielectric layer <NUM>. Barrier layers (not shown in <FIG>) may be deposited in the hole in the insulating layer <NUM> and further the conductive layer is formed in the hole over the barrier layers to fill the hole. Barrier layers may block copper in the conductive layer <NUM> from diffusing to the insulating layer <NUM> through the sides and the end of the conductive layer <NUM> facing the insulating layer <NUM>. The barrier layer may contain a barrier material that can block copper from diffusing, such as Ti, Ta, TiN, TaN, TiSiN or any combination thereof.

The second barrier film <NUM> may block copper in the conductive layer <NUM> from diffusing to the dielectric layers including the integrated first dielectric layer <NUM> and second dielectric layer <NUM>. Barrier layers (not shown in <FIG>) may be deposited over the hole in the insulating layer <NUM> and further the conductive layer <NUM> is formed in the hole over the barrier layers to fill the hole. The barrier layers may block copper in the conductive layer <NUM> from diffusing to the insulating layer <NUM> through the sides and the end of the conductive layer <NUM> facing the insulating layer <NUM>. The barrier layer may contain a barrier material that can block copper from diffusing, such as Ti, Ta, TiN, TaN, TiSiN or any combination thereof.

The self-barrier region of the self-barrier layer <NUM> at the bonding interface <NUM> may have various shapes according to actual application scenarios. The shape of the self-barrier region of the self-barrier layer <NUM> may vary according to the first contact via surface <NUM> and the second contact via surface <NUM>. That is, the shape of the self-barrier region may vary according to the via surface of the first semiconductor structure and the via surface of the second semiconductor structure that are bonded together at the bonding interface.

<FIG> illustrates an exemplary orthogonal projection region of self-barrier layer according to various embodiments of the present disclosure.

The orthogonal projection region of self-barrier layer refers to the self-barrier region described in method embodiments.

The first contact via surface <NUM> has a circle shape. The second contact via surface <NUM> has a circle shape, and has a smaller area than the first contact via surface <NUM>. The first contact via surface <NUM> and the second contact via surface <NUM> are concentric at the bonding interface. The second contact via surface <NUM> is located within the first contact via surface <NUM> at the bonding interface. That is, an orthogonal projection of the first contact via surface <NUM> on the bonding interface completely covers an orthogonal projection of the second contact via surface <NUM> on the bonding interface.

The self-barrier region <NUM> is in the hatched area that is inside the first contact via surface <NUM> and outside the second contact via surface <NUM>. The self-barrier region <NUM> has an annular shape, where annular ring sizes of the shape have the same value. An annular ring size is a width of self-barrier region <NUM> in a radial direction pointing from the center of the smaller one of the first and second contact via surfaces, e.g., the second contact via surface <NUM>. The inner circle and the outer circle of the self-barrier region <NUM> are concentric.

In some embodiments, one or more vias in the first via structure <NUM> may include metal impurity-doped copper, and one or more vias the second via structure <NUM> may include copper. During the annealing process, the metal impurities in the one or more vias in the first via structure <NUM> may diffuse to the bonding interface <NUM> to react with the oxide in the second dielectric layer to form the self-barrier layer <NUM> in the self-barrier region <NUM>.

In some embodiments, one or more vias in the first via structure <NUM> may include metal impurity-doped copper, and one or more vias in the second via structure <NUM> may include metal impurity-doped copper. During the annealing process, the metal impurities in the one or more vias in the first via structure <NUM> and the second via structure <NUM> may diffuse to the bonding interface <NUM> to react with the oxide in the second dielectric layer to form the self-barrier layer <NUM> in the self-barrier region <NUM>.

<FIG> illustrates another exemplary orthogonal projection region of self-barrier layer according to various embodiments of the present disclosure.

A first contact via surface <NUM>' has a circle shape. The second contact via surface <NUM>' has a circle shape and has a smaller area than the first contact via surface <NUM>'. The first contact via surface <NUM>' and the second contact via surface <NUM>' are non-concentric at the bonding interfere. That is, the center of the first contact via surface <NUM>' is at a different location with respect to the center of the second contact via surface <NUM>' at the bonding interfere. Further, the second contact via surface <NUM>' is located within the first contact via surface <NUM>' at the bonding interface. That is, an orthogonal projection of the first contact via surface <NUM>' on the bonding interface completely covers an orthogonal projection of the second contact via surface <NUM>' on the bonding interface.

The self-barrier region <NUM>' is in the hatched area that is inside the first contact via surface <NUM>' and outside the second contact via surface <NUM>'. The self-barrier region <NUM>' has an irregular annular shape with annular ring sizes having different values, where a annular ring size is a width of self-barrier region <NUM>' in a radial direction pointing from the center of the smaller one of the first and second contact via surfaces, e.g., the second contact via surface <NUM>'. The inner circle and the outer circle of the self-barrier region <NUM>' are non-concentric.

In some embodiments, one or more vias in the first via structure may include metal impurity-doped copper, and one or more vias the second via structure may include copper. During the annealing process, the metal impurities in the one or more vias in the first via structure may diffuse to the bonding interface to react with the oxide in the second dielectric layer to form the self-barrier layer <NUM> in the self-barrier region.

In some embodiments, one or more vias in the first via structure may include metal impurity-doped copper, and one or more vias in the second via structure may include metal impurity-doped copper. During the annealing process, the metal impurities in the one or more vias in the first via structure and the second via structure may diffuse to the bonding interface to react with the oxide in the second dielectric layer to form the self-barrier layer <NUM> in the self-barrier region.

The first contact via surface may have various shapes, such as a circle shape, an ellipse shape, a square shape, a rectangle shape, or any other suitable shape.

The second contact via surface may have various shapes, such as a circle shape, an ellipse shape, a square shape, a rectangle shape, or any other suitable shape.

Claim 1:
A hybrid wafer bonding method, comprising:
providing a first semiconductor structure (<NUM>) including:
a first substrate (<NUM>), a first dielectric layer (<NUM>) formed on the first substrate (<NUM>), and a first via structure (<NUM>) formed in the first dielectric layer (<NUM>) and on the first substrate (<NUM>), wherein:
the first via structure (<NUM>) includes a first switch element (<NUM>), a first contact via in contact with the first switch element (<NUM>), and first metal impurities doped in the first contact via, the first contact via having a first contact via surface (<NUM>); wherein an orthogonal projection of the first contact via on the first substrate (<NUM>) is greater than an orthogonal projection of the first switch element (<NUM>) on the first substrate (<NUM>); and
providing a second semiconductor structure (<NUM>') including:
a second substrate (<NUM>), a second dielectric layer (<NUM>) formed on the second substrate (<NUM>), and a second via structure formed in the second dielectric layer (<NUM>) and on the second substrate (<NUM>), wherein:
the second via structure includes a second switch element (<NUM>), a second contact via in contact with the second switch element (<NUM>), and second metal impurities doped in the second contact via, the second contact via having a second contact via surface (<NUM>); wherein an orthogonal projection of the second contact via on the second substrate (<NUM>) is greater than an orthogonal projection of the second switch element (<NUM>) on the second substrate (<NUM>);
bonding the first semiconductor structure (<NUM>) with the second semiconductor structure (<NUM>') by attaching the first contact via surface (<NUM>) with the second contact via surface (<NUM>), wherein the second contact via surface (<NUM>) and the first contact via surface (<NUM>) have different surface areas and have an overlapped interface; and
forming a self-barrier layer (<NUM>) on a non-overlapped surface of one or more of the first and second contact via surfaces (<NUM>) by an alloying process between the first semiconductor structure (<NUM>) and the second semiconductor structure (<NUM>'), wherein the self-barrier layer (<NUM>) is formed by a multi-component oxide corresponding to the first and second metal impurities.