Patent Description:
With continuing expansion of functionality and features provided by contemporary and emerging digital platforms (e.g., smart phones), increasing demands for data storage capacity and high integration density are placed upon memory devices. In response to reductions in the size of memory cells (required for high integration density), the constituent circuits and wiring structures of memory devices have become quite complex. In order to increase the integration density of memory devices, the number of word lines stacked in a vertical direction perpendicular to a principal substrate has increased. As a result, the number of pass transistors connected to word lines has also increased, thereby driving up the overall size of memory array chips.

<CIT> discloses a nonvolatile memory device including a first memory block connected to first word lines, a second memory block arranged in a direction perpendicular to the first memory block and connected to second word lines, first pass transistors for enabling the first word lines, and second pass transistors for enabling the second word lines.

<CIT> discloses a nonvolatile memory device including a substrate; a memory cell array formed on the substrate in a vertically stacked structure; and a row decoder configured to supply a row line voltage to the memory cell array, the row decoder including a plurality of pass transistors.

The present invention is set out in claim <NUM>. Preferred aspects are defined in dependent claims <NUM>-<NUM>. In the following only embodiments comprising all the technical features of claim <NUM> are falling under the scope of protection of the present invention.

The making and use of the inventive concept may be more clearly understood upon consideration of the following detailed description taken in conjunction with the accompanying drawings in which:.

Throughout the written description and drawings, like reference numbers and labels are used to denote like or similar elements and/or features. Throughout the written description certain geometric terms may be used to highlight relative relationships between elements, components and/or features with respect to certain embodiments of the inventive concept. Those skilled in the art will recognize that such geometric terms are relative in nature, arbitrary in descriptive relationship(s) and/or directed to portion(s) of the illustrated embodiments. Geometric terms may include, for example: height/width; vertical/horizontal; top/bottom; higher/lower; closer/farther; thicker/thinner; proximate/distant; above/below; under/over; upper/lower; center/side; surrounding; overlay/underlay; etc..

Hereinafter, embodiments of the inventive concept will be described in with reference to the accompanying drawings.

Figure (<FIG> is a block diagram illustrating a memory device <NUM> according to embodiments of the inventive concept.

Referring to <FIG>, the memory device <NUM> may generally include a memory cell array <NUM> and a peripheral circuit <NUM>. In this example, the peripheral circuit <NUM> may include a pass transistor circuit <NUM>, a row decoder <NUM>, a control logic circuit <NUM>, and a page buffer <NUM>. Although not shown, the peripheral circuit <NUM> may further include a voltage generator, a data input/output (I/O) circuit, an I/O interface, a temperature sensor, a command decoder, or an address decoder. In some embodiments, the memory device <NUM> may be a nonvolatile memory device.

The memory cell array <NUM> may be connected to the pass transistor circuit <NUM> through word lines WL, string selection lines SSL, and ground selection lines GSL and may be connected to the page buffer <NUM> through bit lines BL. The memory cell array <NUM> may include memory cells (e.g., flash memory cells). Hereinafter, embodiments of the inventive concept will be described assuming the use (or incorporation of) NAND flash memory cells. However, the inventive concept is not limited thereto. Alternately, the memory cells may be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

In some embodiments, the memory cell array <NUM> may be a three-dimensional (3D) memory cell array including NAND strings, wherein each NAND string includes memory cells connected to vertically stacked word lines. One example of this configuration will be described hereafter in relation to <FIG>.

The control logic circuit <NUM> may generate various control signals for programming data into the memory cell array <NUM>, reading data from the memory cell array <NUM>, or erasing data stored in the memory cell array <NUM> based on the command CMD, the address ADDR, and the control signal CTRL. For example, the control logic circuit <NUM> may output a row address X-ADDR and a column address Y-ADDR. Accordingly, the control logic circuit <NUM> may generally control various operations within the memory device <NUM>.

The row decoder <NUM> may output a block selection signal for selecting one of the plurality of memory blocks to the block selection signal lines BS in response to the row address X-ADDR. The row decoder <NUM> may output a word line driving signal for selecting one of the word lines WL of the selected memory block to the word line driving signal lines SI, output a string selection line driving signal for selecting one of the string selection lines SSL to the string selection line driving signal lines SS, and output a ground selection line driving signal for selecting one of the ground selection lines GSL to the ground selection line driving signal lines GS in response to the row address X-ADDR. The page buffer <NUM> may select some of the bit lines BL in response to the column address Y-ADDR. Specifically, the page buffer <NUM> operates as a write driver or sense amplifier according to an operation mode.

The pass transistor circuit <NUM> may be connected to the row decoder <NUM> through the block selection signal lines BS, the string selection line driving signal lines SS, the word line driving signal lines SI, and the ground selection line driving signal lines GS. Collectively or singularly, the string selection line driving signal lines SS, the word line driving signal lines SI, and the ground selection line driving signal lines GS may be referred to throughout the embodiments as "driving signal lines". The pass transistor circuit <NUM> may include pass transistors (See, e.g., <NUM> to <NUM> in <FIG>), wherein the pass transistors may be controlled by block selection signals received through block selection signal lines BS, and may provide string selection line driving signals, word line driving signals, and ground selection line driving signals to the string selection lines SSL, the word lines WL, and the ground selection lines GSL, respectively.

In some embodiments, the pass transistor circuit <NUM> may include an odd number of pass transistor groups corresponding to two adjacent memory blocks (e.g. a first memory block and a second memory block adjacently disposed in a first direction). In this regard, the two memory blocks may be adjacent in a first dirction (e.g., a first horizontal direction). The size of the odd number of pass transistor groups in the first direction may be substantially the same as the size of the two memory blocks in the first direction (i.e., a <NUM>-block height). For example, the pass transistor circuit <NUM> may include three pass transistor groups corresponding to two adjacent memory blocks. However, the inventive concept is not limited thereto, and the pass transistor circuit <NUM> may include one pass transistor group corresponding to two adjacent memory blocks, or may include five or seven pass transistor groups. In one example, the pass transistor circuit <NUM> including an odd number of pass transistor groups may be connected between the driving signal lines SS, SI, GS and the memory cell array <NUM>.

In this example, in one of the odd number of pass transistor groups, pass transistors corresponding to word lines included in different memory blocks and disposed at the same level may be adjacently disposed. Accordingly, the lengths of wirings respectively connecting the word lines to the pass transistors may be substantially the same, and the resistances of the wirings may be substantially the same. Accordingly, loading times for word lines included in different memory blocks and disposed at the same level (e.g., word line set up times) may be similarly implemented.

As such, in some embodiments of the inventive concept, pass transistors corresponding to adjacent memory blocks may be arranged in odd rows, and pass transistors corresponding to word lines included in different memory blocks and disposed at the same level may be disposed adjacent to each other in a second direction. Accordingly, the loading time skew for word lines may be reduced, and overall chip size may also be reduced. Specifically, the length of the wiring between the first word line and the first pass transistor of the first memory block and the length of the wiring between the first word line and the second pass transistor of the second memory block are similarly implemented. Accordingly, variation(s) in path resistance of the first word lines may be reduced, and loading time skew for the first word lines may be reduced.

With continuing development of semiconductor processes, and as the number of stages of memory cells disposed in the memory cell array <NUM> increases (i.e., as the number of vertically stacked word lines WL increases), the number of pass transistors for driving the word lines WL also increases. Accordingly, an area occupied by the pass transistor circuit <NUM> may increase. In some embodiments, the peripheral circuit <NUM> may be vertically disposed above or below the memory cell array <NUM>. That is, the pass transistor circuit <NUM> may be disposed above or below a stair-stepped area (see, e.g., SA in <FIG>) for the word lines WL. Accordingly, because the area where the pass transistor circuit <NUM> is disposed overlaps the stair-stepped area of the word lines WL, despite an increase in the number of pass transistors due to an increase in the number of stacked word lines WL, the chip size of the memory device <NUM> need not necessarily increase. This result may be better understood, for example, upon consideration of the embodiment described in relation to <FIG>.

<FIG> is a perspective diagram illustrating one possible structure for the memory device <NUM> of <FIG>.

Referring to <FIG> and <FIG>, the memory device <NUM> may include a first semiconductor layer L1 and a second semiconductor layer L2, wherein the first semiconductor layer L1 is stacked in a vertical direction VD on the second semiconductor layer L2. Thus, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1, and the second semiconductor layer L2 may be disposed close to a supporting substrate (not specifically shown in <FIG>). In some embodiments, the memory cell array <NUM> may be formed on the first semiconductor layer L1 and the peripheral circuit <NUM> may be formed on the second semiconductor layer L2. Accordingly, the memory device <NUM> may have a structure in which the memory cell array <NUM> is disposed above some peripheral circuits, that is, a Cell Over Periphery (COP) structure.

The first semiconductor layer L1 may include a cell area CA including memory cells and a stair-stepped area SA disposed in the cell area CA. In the first semiconductor layer L1, bit lines BL may extend in a first horizontal direction HD1 and word lines WL may extend in a second horizontal direction HD2. Thus, the respective "ends" of the word lines WL may be implemented in a stair-stepped configuration. Accordingly, as used herein, the term "stair-stepped area" (or "word line extension area") refers to an area including an arrangement of stair-stepped word line WL ends.

Thus, the second semiconductor layer L2 may include a substrate, and the peripheral circuit <NUM> may be formed on the second semiconductor layer L2 by forming a pattern for wiring semiconductor elements such as transistors and elements on the substrate. After the peripheral circuit <NUM> is formed in the second semiconductor layer L2, a first semiconductor layer L1 including the memory cell array <NUM> may be formed, and patterns for electrically connecting the word lines WL and bit lines BL of the memory cell array <NUM> to the peripheral circuit <NUM> formed in the second semiconductor layer L2 may be formed. The second semiconductor layer L2 may include a first area R1 corresponding to the stair-stepped area SA and a second area R2 corresponding to the cell area CA. In some embodiments, the pass transistor circuit <NUM> may be disposed in the first area R1, but the inventive concept is not limited thereto.

As described above, the memory device <NUM> may have a COP structure, and the pass transistor circuit <NUM> may be disposed under the stair-stepped area SA. With this configuration, pass transistors connected to word lines included in different memory blocks and disposed at the same level may be adjacently disposed, such that loading times for the word lines may be similarly implemented. However, the inventive concept is not limited thereto, and the memory device <NUM> may have a non-COP structure. In such a case, the pass transistor circuit <NUM> may be adjacently disposed to the memory cell array <NUM> in a horizontal direction. In one example, a memory device may comprise a first memory block and a second memory block adjacently disposed in a first direction; a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines; and a second pass transistor, connected between a first word line of the second memory block and the first driving signal line, and adjacently disposed to the first pass transistor in a second direction.

<FIG> is a perspective diagram illustrating in one example a memory cell array <NUM> according to embodiments of the inventive concept.

Referring to <FIG>, the memory cell array <NUM> includes multiple memory blocks (e.g., BLKO to BLKi, wherein 'i' is a positive integer) Each of the memory blocks BLKO to BLKi has a 3D structure (or a vertical structure in a vertical direction VD). That is, each of the memory blocks BLKO to BLKi may include vertically arranged NAND strings. In this case, the NAND strings may be provided spaced apart in the first and second horizontal directions HD1 and HD2. The memory blocks BLKO to BLKi may be selected by the row decoder <NUM> of <FIG>. For example, the row decoder <NUM> may select a memory block corresponding to a block address from among the memory blocks BLKO to BLKi.

<FIG> is a block diagram further illustrating the row decoder <NUM> and the pass transistor circuit <NUM> of <FIG> in relation to a first memory block BLKO and a second memory block BLK1 according to embodiments of the inventive concept.

Referring to <FIG>, the pass transistor circuit <NUM> may include pass transistor circuits respectively corresponding to corresponding memory blocks. The first and second memory blocks BLKO and BLK1 may be adjacently disposed, wherein each of the first and second memory blocks BLKO and BLK1 may include a ground selection line GSL, word lines WL0 to WLm, and a string selection line SSL, where 'm' is a positive integer.

The row decoder <NUM> may include a block decoder <NUM> and a driving signal line decoder <NUM>. The pass transistor circuit <NUM> may include a pass transistor circuit <NUM> corresponding to the first memory block BLKO and a pass transistor circuit <NUM> corresponding to the second memory block BLK1. The pass transistor circuit <NUM> may include pass transistors <NUM> to <NUM>, and the pass transistor circuit <NUM> may include pass transistors <NUM> to <NUM>.

The block decoder <NUM> may be connected to the pass transistor circuit <NUM> through a first block selection signal line BS0, and may be connected to the pass transistor circuit <NUM> through a second block selection signal line BS1. The first block selection signal line BS0 may be connected to gates of the plurality of pass transistors <NUM> to <NUM>. For example, when the first block selection signal provided through the first block selection signal line BS0 is activated, the plurality of pass transistors <NUM> to <NUM> may be turned ON, and accordingly, the first memory block BLKO may be selected. Further, the second block selection signal line BS1 may be connected to gates of the pass transistors <NUM> to <NUM>. For example, when the second block selection signal provided through the second block selection signal line BS1 is activated, the plurality of pass transistors <NUM> to <NUM> may be turned ON, and accordingly, the second memory block BLK1 may be selected.

The driving signal line decoder <NUM> may be connected to the pass transistor circuits <NUM> and <NUM> through the string selection line driving signal line SS, the word line driving signal lines SI0 to SIm, and the ground selection line driving signal line GS. That is, the string selection line driving signal line SS, the word line driving signal lines SI0 to SIm, and the ground selection line driving signal line GS may be respectively connected to sources of the pass transistors <NUM> to <NUM> and <NUM> to <NUM>.

The pass transistor circuit <NUM> may be connected to the first memory block BLKO through a ground selection line GSL, word lines WL0 to WLm, and a string selection line SSL. The pass transistor <NUM> may be connected between the ground selection line driving signal line GS and the ground selection line GSL. The pass transistors <NUM> to <NUM> may be respectively connected between the word line driving signal lines SI0 to SIm and the word lines WL0 to WLm. The pass transistor <NUM> may be connected between the string selection line driving signal line SS and the string selection line SSL. For example, when the first block selection signal is activated, the pass transistors <NUM> to <NUM> may provide driving signals, which are provided through the ground selection line driving signal line GS, the word line driving signal lines SI0 to SIm, and the string selection line driving signal line SS, to the ground selection line GSL, the word lines WL0 to WLm, and the string selection line SSL, respectively. Example descriptions of the pass transistor circuit <NUM> that may be applied to the pass transistor circuit <NUM> will be provided hereafter.

<FIG> is a partial circuit diagram further illustrating a pass transistor circuit 211a and a first memory block BLKO according to embodiments of the inventive concept.

Referring to <FIG>, the pass transistor circuit 211a may correspond to an example implementation of the pass transistor circuit <NUM> of <FIG>. In some embodiments, the pass transistor circuit <NUM> may be implemented in a substantially similar manner to the pass transistor circuit 211a, and the second memory block BLK1 may be implemented in a substantially similar manner to the first memory block BLKO. The first memory block BLKO may include NAND strings NS11 to NS33, word lines WL0 to WLm, bit lines BL0 to BL2, ground selection lines GSLO to GSL2, string selection lines SSLO to SSL2 and a common source line CSL. In this example, the number of NAND strings, word lines, bit lines, ground selection lines and string selection lines is a matter of design choice.

The NAND strings NS11, NS21, and NS31 are provided between the bit line BL0 and the common source line CSL, and the NAND strings NS12, NS22, and NS32 are provided between the bit line BL1 and the common source line CSL, and the NAND strings NS13, NS23, and NS33 are provided between the bit line BL2 and the common source line CSL. Each NAND string (e.g., NS33) may include a series connection of a string selection transistor SST, memory cells MCs (e.g., nonvolatile memory cells) and a ground selection transistor GST.

The string selection transistor SST is connected to the corresponding string selection lines SSLO to SSL2. The memory cells MCs may be respectively connected to corresponding word lines WL0 to WLm. The ground selection transistor GST may be connected to the corresponding ground selection lines GSLO to GSL2. The string selection transistor SST may be connected to the corresponding bit lines BL0 to BL2, and the ground selection transistor GST is connected to the common source line CSL.

In some embodiments, word lines (e.g., WL1) at the same height (i.e., word lines arranged at the same level) may be commonly connected, however, the string selection lines SSLO to SSL2 and the ground selection lines GSLO to GSL2 may be separated. In <FIG>, three string selection lines SSLO to SSL2 share a word line at the same height, but the inventive concept is not limited thereto. For example, two string selection lines may share a word line at the same height, or four string selection lines may share a word line at the same height.

The pass transistor circuit 211a may include pass transistors 2111a to 2111c respectively connected to ground selection lines GSLO to GSL2, pass transistors <NUM> to <NUM> respectively connected to the word lines WL0 to WLm, and pass transistors 2116a to 2116c respectively connected to the string selection lines SSLO to SSL2. The pass transistors 2111a to 2111c, <NUM> to <NUM>, and 2116a to 2116c may be turned ON/OFF according to a first block selection signal provided along the first block selection signal line BS0, and may provide driving signals, which are provided through the string selection line driving signal lines SS0 to SS2, the word line driving signal lines SI0 to SIm, and the ground selection line driving signal lines GS0 to GS2, to the string selection lines SSLO to SSL2, the word lines WL0 to WLm, and the ground selection lines GSLO to GSL2, respectively.

<FIG> is a table listing voltage(s) that may be applied as word line driving signals for a variety of memory operations according to embodiments of the inventive concept.

Referring to <FIG>, the selected word line driving signal line SIa may correspond to a driving signal line connected to the selected word line WLsel, and the non-selected word line driving signal line SIb may correspond to a driving signal line connected to the non-selected word line WLunsel. During the program operation, a program voltage Vpgm (e.g., about 20V) may be applied to the selected word line driving signal line SIa, and a pass voltage Vpass (e.g., about 9V) may be applied to the non-selected word line driving signal line SIb. During a read operation, a read voltage Vr (e.g., about 0V) may be applied to the selected word line driving signal line SIa, and a read pass voltage Vread (e.g., about 6V) may be applied to the non-selected word line driving signal line SIb. During the erase operation, an erase voltage Ver (e.g., about 0V) may be applied to both the selected word line driving signal line SIa and the non-selected word line driving signal line SIb.

<FIG> is a plan view further illustrating one example of the pass transistor circuit <NUM> of <FIG>.

Referring to <FIG>, the first and second memory blocks BLKO and BLK1 may be adjacently disposed (e.g., in the first horizontal direction HD1). The size of each of the first and second memory blocks BLKO and BLK1 in the first horizontal direction HD1 may correspond to a first block height H1 (e.g., a one block height). However, the collective size of the first and second memory blocks BLKO and BLK1 in the first horizontal direction HD1 may be referred to as a second block height H2 (e.g., a two block height).

The pass transistor circuit <NUM> may include first pass transistors TR_0 corresponding to the first memory block BLK0, and second pass transistors TR_1 corresponding to the second memory block BLK1. The pass transistor circuit <NUM> may be adjacently disposed to the first and second memory blocks BLKO and BLK1 in the second horizontal direction HD2. The size of the pass transistor circuit <NUM> in the first horizontal direction HD1 may correspond to the second block height H2. For example, as illustrated in <FIG> and <FIG>, the first and second memory blocks BLKO and BLK1 may be disposed on the first semiconductor layer L1, and the pass transistor circuit <NUM> may be disposed in the first area R1 corresponding to the stair-stepped area SA of the word lines WL connected to the first and second memory blocks BLKO and BLK1 in the second semiconductor layer L2.

The first and second pass transistors TR_0 and TR_1 included in the pass transistor circuit <NUM> may be divided into an odd number of pass transistor groups disposed in the first horizontal direction HD1. For example, the first and second pass transistors TR_0 and TR_1 may be divided into first, second and third pass transistor groups GR0, GR1 and GR2. The first pass transistor group GR0 may be disposed in the first stage STAGE0, the second pass transistor group GR1 may be disposed in the second stage STAGE1, and the third pass transistor group GR2 may be disposed in the third stage STAGE2.

In some embodiments, the first pass transistor group GR0 may include some of the first pass transistors TR_0, the second pass transistor group GR1 may include some of the second pass transistors TR_1, and the third pass transistor group GR2 may include the remaining or the rest of the first pass transistors TR_0 and the remaining or the rest of the second pass transistors TR_1. In the third pass transistor group GR2, the first and second pass transistors TR_0 and TR_1 connected to the word lines disposed at the same level as each other may be adjacently disposed.

For example, a first pass transistor TRa_0 and a second pass transistor TRa_1 included in the third pass transistor group GR2 may be connected to a first word line (e.g., WL0 (e.g., WL0 of BLKO and WL0 of BLK1)) disposed at the same level. In addition, for example, a first pass transistor TRb_0 and a second pass transistor TRb_1 included in the third pass transistor group GR2 may be connected to a second word line (e.g., WL1) disposed at the same level. In this case, the first pass transistor TRa_0 and the first pass transistor TRb_0 may be disposed adjacent to each other. In an embodiment, the space between the first pass transistor TRa_0 and the second pass transistor TRa_1 may be equal to the space between the first pass transistor TRa_0 and the first pass transistor TRb_0, but the inventive concept is not limited thereto. In some embodiments, the space between the first pass transistor TRa_0 and the second pass transistor TRa_1 may be larger than the space between the first pass transistor TRa_0 and the first pass transistor TRb_0, but the inventive concept is not limited thereto.

<FIG> is a plan view further illustrating some of the pass transistors included in the pass transistor circuit <NUM> of <FIG>.

Referring to <FIG>, a first pass transistor group GR0 may include first pass transistors TR11 and TR12 disposed in a first stage STAGE0. The first pass transistor TR11 may include a gate G11 connected to the first block selection signal line BS0, a source S11 connected to a word line driving signal line (e.g., SI2), and a drain D11 connected to a word line (e.g., WL2 of BLK0). The first pass transistor TR12 may include a gate G12 connected to the first block selection signal line BS0, a source S12 connected to a word line driving signal line (e.g., SI3), and a drain D12 connected to a word line (e.g., WL3 of BLK0).

The second pass transistor group GR1 may include second pass transistors TR21 and TR22 disposed in the second stage STAGE1. The second pass transistor TR21 may include a gate G21 connected to the second block selection signal line BS1, a source S21 connected to a word line driving signal line (e.g., SI2), and a drain D21 connected to a word line (e.g., WL2 of BLK1). The second pass transistor TR22 may include a gate G22 connected to the second block selection signal line BS1, a source S22 connected to a word line driving signal line (e.g., SI3), and a drain D22 connected to a word line (e.g., WL3 of BLK1).

In the first and second pass transistor groups GR0 and GR1, the active area of the first and second pass transistors TR11 and TR21, TR12 and TR22 adjacent in the first horizontal direction HD1 may be shared. The sources S11 and S21 may be formed in an active area sharing method, and for example, the word line driving signal line SI2 may be connected to the sources S11 and S21. Similarly, the sources S12 and S22 may be formed in an active area sharing method, and for example, the word line driving signal line SI3 may be connected to the sources S12 and S22.

The third pass transistor group GR2 may include a first pass transistor TR32 and a second pass transistor TR31 disposed in the third stage STAGE2. The first pass transistor TR32 may include a gate G32 connected to the first block selection signal line BS0, a source S32 connected to a word line driving signal line (e.g., SI0), and a drain D32 connected to a word line (e.g., WL0 of BLK0). The second pass transistor TR31 may include a gate G31 connected to the second block selection signal line BS1, a source S31 connected to a word line driving signal line (e.g., SI0), and a drain D31 connected to a word line (e.g., WL0 of BLK1). In this way, in the third pass transistor group GR2, the drains D32 and D31, respectively, included in the first and second pass transistors TR32 and TR31 adjacent in the second horizontal direction HD2 may be connected to a word line (e.g., WL0) disposed at the same level.

<FIG> is a plan view illustrating a pass transistor circuit 210a according to embodiments of the inventive concept.

Referring to <FIG>, the pass transistor circuit 210a may be understood as a modified version of the pass transistor circuit <NUM> of <FIG>. Referring to <FIG>, <FIG>, and <FIG>, in the third pass transistor group GR2, the first pass transistor TR_0 corresponding to the first memory block BLKO and the second pass transistor TR_1 corresponding to the second memory block BLK1 may be alternately disposed. For example, the first pass transistor TRa_0 and the second pass transistor TRb_1 may be disposed adjacent to each other. In an embodiment, the space between the first pass transistor TRa_0 and the second pass transistor TRa_1 may be equal to the space between the first pass transistor TRa_0 and the second pass transistor TRb_1, but the inventive concept is not limited thereto.

<FIG> is a plan view illustrating a pass transistor circuit 210b according to embodiments of the inventive concept.

Referring to <FIG>, the pass transistor circuit 210b may be understood as a modified version of the pass transistor circuit <NUM> of <FIG>. Referring to <FIG>, <FIG> and <FIG>, the first and second pass transistors TR_0 and TR_1 included in the pass transistor circuit 210b may be divided into first to fifth pass transistor groups GR0 to GR4 disposed in the first horizontal direction HD1. The first pass transistor group GR0 may be disposed in the first stage STAGE0, the second pass transistor group GR1 may be disposed in the second stage STAGE1, the third pass transistor group GR2 may be disposed in the third stage STAGE2, the fourth pass transistor group GR3 may be disposed in the fourth stage STAGE3, and the fifth pass transistor group GR4 may be disposed in the fifth stage STAGE4.

In an embodiment, the first pass transistor group GR0 may include some of the first pass transistors TR_0, and the second pass transistor group GR1 may include some of the second pass transistors TR_1. The first and second pass transistors TR_0 and TR_1 adjacent in the first horizontal direction HD1 in the first and second pass transistor groups GR0 and GR1 may share an active area. The third pass transistor group GR2 may include another part of the first pass transistors TR_0, and the fourth pass transistor group GR3 may include another part of the second pass transistor TR_1. The first and second pass transistors TR_0 and TR_1 adjacent in the first horizontal direction HD1 in the third and fourth pass transistor groups GR2 and GR3 may share an active area.

The fifth pass transistor group GR4 may include the rest of the first pass transistors TR_0 and the rest of the second pass transistors TR_1. In the fifth pass transistor group GR4, the first and second pass transistors TR_0 and TR_1 connected to the same word line disposed at the same level as each other may be disposed adjacent to each other. For example, the first pass transistor TRa_0 and the second pass transistor TRa_1 included in the fifth pass transistor group GR4 may be connected to a first word line (e.g., WL0) disposed at the same level.

<FIG> is a block diagram illustrating a row decoder <NUM>, pass transistor circuits <NUM> and <NUM>', and first and second memory blocks BLKO and BLK1 according to embodiments of the inventive concept.

Referring to <FIG>, a memory device <NUM>' may include pass transistor circuits <NUM> and <NUM>', and each of the pass transistor circuits <NUM> and <NUM>' may include a plurality of pass transistor circuits respectively corresponding to a plurality of memory blocks. The memory device <NUM>' may be understood as a modified version of the memory device <NUM> of <FIG>.

Referring to <FIG> and <FIG>, the pass transistor circuit <NUM> may be disposed on one side of the first and second memory blocks BLKO and BLK1 (e.g., on the left side), and may include a pass transistor circuit <NUM> corresponding to the first memory block BLKO and a pass transistor circuit <NUM> corresponding to the second memory block BLK1. The pass transistor circuit <NUM>' may be disposed on the other side of the first and second memory blocks BLKO and BLK1 (e.g., on the right side), and may include a pass transistor circuit <NUM>' corresponding to the first memory block BLKO and a pass transistor circuit <NUM>' corresponding to the second memory block BLK1. The pass transistor circuit <NUM>' may include pass transistors <NUM>' to <NUM>', and the second pass transistor circuit <NUM>' may include pass transistors <NUM>' to <NUM>'.

The block decoder <NUM> may be connected to the pass transistor circuits <NUM> and <NUM>' through the first block selection signal line BS0, and may be connected to the pass transistor circuits <NUM> and <NUM>' through the second block selection signal line BS1. The first block selection signal line BS0 may be connected to gates of the pass transistors <NUM> to <NUM> and <NUM>' to <NUM>'. For example, when the first block selection signal provided through the first block selection signal line BS0 is activated, the pass transistors <NUM> to <NUM> and <NUM>' to <NUM>' may be turned ON, and accordingly, the first memory block BLKO may be selected. In addition, the second block selection signal line BS1 may be connected to gates of the pass transistors <NUM> to <NUM> and <NUM>' to <NUM>'. For example, when the second block selection signal provided through the second block selection signal line BS1 is activated, the pass transistors <NUM> to <NUM> and <NUM>' to <NUM>' may be turned ON, and accordingly, the second memory block BLK1 may be selected.

The driving signal line decoder <NUM> may be connected to the pass transistor circuits <NUM>, <NUM>, <NUM>', and <NUM>', through the string selection line driving signal line SS, the word line driving signal lines SI0 to SIm, and the ground selection line driving signal line GS. Specifically, the string selection line driving signal line SS, the word line driving signal lines SI0 to SIm, and the ground selection line driving signal line GS may be connected to sources of the pass transistors <NUM> to <NUM>, <NUM> to <NUM>, <NUM>' to <NUM>', and <NUM>' to <NUM>', respectively.

The first pass transistor circuit <NUM>' may be connected to the first memory block BLKO through a ground selection line GSL, a plurality of word lines WL0 to WLm, and a string selection line SSL. The pass transistor <NUM>' may be connected between the ground selection line driving signal line GS and the ground selection line GSL. The pass transistors <NUM>' to <NUM>' may be connected between the word line driving signal lines SI0 to SIm and the word lines WL0 to WLm, respectively. The pass transistor <NUM>' may be connected between the string selection line driving signal line SS and the string selection line SSL. For example, when the first block selection signal is activated, the pass transistors <NUM>' to <NUM>' may provide driving signals, which are provided through the ground selection line driving signal line GS, the word line driving signal lines SI0 to SIm, and the string selection line driving signal line SS, to the ground selection line GSL, the word lines WL0 to WLm, and the string selection line SSL, respectively. The previous description of the first pass transistor circuit <NUM>' may also be applied to the second pass transistor circuit <NUM>'.

As described above, the pass transistors may be disposed at both ends of the word lines WL0 to WLm of each of the first and second memory blocks BLKO and BLK1. For example, pass transistors <NUM> and <NUM>' may be disposed at both ends of the first word line WL0. However, the inventive concept is not limited thereto, and in some embodiments, pass transistors connected to odd-numbered word lines may be disposed on one side of each memory block, and pass transistors connected to even-numbered word lines may be disposed on the other side.

<FIG> is a plan view illustrating the pass transistor circuits <NUM> and <NUM>' according to embodiments of the inventive concept.

Referring to <FIG>, the first and second memory blocks BLKO and BLK1 may be adjacently disposed in the first horizontal direction HD1. Each of the pass transistor circuits <NUM> and <NUM>' may include first pass transistors TR_0 corresponding to the first memory block BLKO and second pass transistors TR_1 corresponding to the second memory block BLK1. The pass transistor circuit <NUM> may be disposed on the left side of the first and second memory blocks BLKO and BLK1, and the pass transistor circuit <NUM>' may be disposed on the right side of the first and second memory blocks BLKO and BLK1. The size of each of the pass transistor circuits <NUM> and <NUM>' in the first horizontal direction HD1 may be the second block height H2.

The pass transistor circuits <NUM> and <NUM>' may be implemented in substantially the same manner. Hence, the previous description of the pass transistor circuits <NUM>, 210a, and 210b in relation to <FIG> may also be applied here. The first and second pass transistors TR_0 and TR_1 included in the pass transistor circuit <NUM>' may be divided into first to third pass transistor groups GR0' to GR2'. The first pass transistor group GR0' may be disposed in the first stage STAGE0, the second pass transistor group GR1' may be disposed in the second stage STAGE1, and the third pass transistor group GR2' may be disposed in the third stage STAGE2. In this example, in the first and second pass transistor groups GR0' and GR1', the first and second pass transistors TR_0 and TR_1 adjacent in the first horizontal direction HD1 may share an active area.

In some embodiments, the first pass transistor group GR0' may include some of the first pass transistors TR_0, the second pass transistor group GR1' may include some of the second pass transistors TR_1, and the third pass transistor group GR2' may include the rest of the first pass transistors TR_0 and the rest of the second pass transistors TR_1. In the third pass transistor group GR2', the first and second pass transistors TR_0 and TR_1 connected to the same word line disposed at the same level may be adjacently disposed. For example, the first pass transistor TRa_0' and the second pass transistor TRa_1' included in the third pass transistor group GR2' may be connected to a first word line (e.g., WL0) disposed at the same level.

<FIG> is a plan view further illustrating in one example the pass transistor circuit <NUM> of <FIG>.

Referring to <FIG>, the number of first pass transistors TR_0 is assumed to be <NUM>, and the number of second pass transistors TR_1 is assumed to be <NUM>, but these are just working examples and the number may be more or less than <NUM>. In <FIG>, the numbers displayed on the gates of the first and second pass transistors TR_0 and TR1 may correspond to the numbers of levels for the corresponding word lines. For example, in the third pass transistor group GR2, the gates of the first and second pass transistors TRa_0 and TRa_1 display the number <NUM>, and the first and second pass transistors TRa_0 and TRa_1 connected to the first word line WL0 may be adjacently disposed in the second horizontal direction HD2. Specifically, the first pass transistor TRa_0 may be connected to the first word line WL0 of the first memory block BLK0, and the second pass transistor TRa_1 may be connected to the first word line WL0 of the second memory block BLK1. For example, in the third pass transistor group GR2, the first and second pass transistors TRb_0 and TRb_1 connected to the second word line WL1 (the gates of which display the number <NUM>) may be adjacently disposed in the second horizontal direction HD2. That is, the first pass transistor TRb_0 may be connected to the second word line WL1 of the first memory block BLK0, and the second pass transistor TRb_1 may be connected to the second word line WL1 of the second memory block BLK1.

The first pass transistor group GR0 may include first pass transistors TR_0 disposed in the second horizontal direction HD2. For example, the first pass transistor TRc_0 (the gate of which displays the number <NUM>) may be connected to the third word line WL2 of the first memory block BLK0, and the first pass transistor TRd_0 (the gate of which displays the number <NUM>) may be connected to the fourth word line WL3 of the first memory block BLKO. The second pass transistor group GR1 may include second pass transistors TR_1 disposed in the second horizontal direction HD2. For example, the second pass transistor TRc_1 (the gate of which displays the number <NUM>) may be connected to the third word line WL2 of the second memory block BLK1, and the second pass transistor TRd_1 (the gate of which displays the number <NUM>) may be connected to the fourth word line WL3 of the second memory block BLK1. In this way, the first and second pass transistors TRc_0 and TRc_1 connected to the third word line WL2 may be disposed adjacent to each other in the first horizontal direction HD1, and the first and second pass transistors TRd_0 and TRd_1 connected to the fourth word line WL3 may be disposed adjacent to each other in the first horizontal direction HD1.

<FIG> is a plan view illustrating pass transistor circuits 210A and 210A' according to embodiments of the inventive concept.

Referring to <FIG>, the pass transistor circuits 210A and 210A' may be understood as a modified version of the pass transistor circuits <NUM> and <NUM>' of <FIG>. In this example, the first and second pass transistors TR_0 and TR1 adjacent in the first horizontal direction HD1 may not share the active area. The pass transistor circuits 210A and 210A' may be implemented in substantially the same manner. The first and second pass transistors TR_0 and TR_1 included in the pass transistor circuit 210A may be divided into first to third pass transistor groups GR0 to GR2. Similarly, the first and second pass transistors TR_0 and TR_1 included in the pass transistor circuit 210A' may be divided into first to third pass transistor groups GR0' to GR2'.

Each of the first pass transistor groups GR0 and GR0' may include some of the first pass transistors TR_0, each of the third pass transistor groups GR2 and GR2 ' may include some of the second pass transistors TR_1, and each of the second pass transistor groups GR1 and GR1 ' may include the rest of the first pass transistors TR_0 and the rest of the second pass transistors TR_1. In this example, the first pass transistor groups GR0 and GR0' may be disposed in the first stage STAGE0, the third pass transistor groups GR2 and GR2' may be disposed in the second stage STAGE1, and the second pass transistor groups GR1 and GR1' may be disposed in the third stage STAGE2. However, the inventive concept is not limited thereto, and the arrangement order of the first to third pass transistor groups GR0 to GR2 and GR0' to GR2' may be variously changed. For example, the second pass transistor groups GR1 and GR1' may be disposed in the first stage STAGE0.

In the third pass transistor groups GR2 and GR2', the first and second pass transistors TR_0 and TR_1 connected to the same word line disposed at the same level as each other may be disposed adjacent to each other. For example, the first pass transistor TRa_0 and the second pass transistor TRa_1 included in the third pass transistor group GR2 may be connected to a first word line (e.g., WL0) disposed at the same level. For example, the first pass transistor TRa_0' and the second pass transistor TRa_1' included in the third pass transistor group GR2' may be connected to a first word line (e.g., WL0) disposed at the same level.

<FIG> is a plan view further illustrating in one example the pass transistor circuit 210A of <FIG>.

Referring to <FIG>, the pass transistor circuit 210A may be understood as a modified version of the pass transistor circuit <NUM> of <FIG>. Referring to <FIG>, <FIG> and <FIG>, the first and second pass transistors TR_0 and TR_1 disposed in the first to third stages STAGE0 to STAGE2 may not share an active area with each other. In the third pass transistor group GR2, the first and second pass transistors TR_0 and TR_1 connected to the word lines disposed at the same level may be adjacently disposed in the second horizontal direction HD2.

<FIG> is a plan view illustrating pass transistor circuits 210B and 210B' according to embodiments of the inventive concept.

Referring to <FIG>, first to fourth memory blocks BLKO to BLK3 may be disposed in a first horizontal direction HD1. The size of each of the first to fourth memory blocks BLKO to BLK3 in the first horizontal direction HD1 may correspond to the first block height H1, whereas the collective size of the first to fourth memory blocks BLKO to BLK3 in the first horizontal direction HD1 may correspond to a third block height H3 (e.g., a four block height). The pass transistor circuits 210B and 210B' may be respectively understood as modified versions of the pass transistor circuits <NUM> and <NUM>' of <FIG>.

In this example, the pass transistor circuit 210B may include first pass transistors TR_0 corresponding to the first memory block BLK0, second pass transistors TR_1 corresponding to the second memory block BLK1, third pass transistors TR_2 corresponding to the third memory block BLK2, and fourth pass transistors TR_3 corresponding to the fourth memory block BLK3. The pass transistor circuit 210B may be disposed on one side (e.g., on the left side) of the first to fourth memory blocks BLKO to BLK3. The size of the pass transistor circuit 210B in the first horizontal direction HD1 may correspond to the third block height H3. For example, as illustrated in <FIG>, the first to fourth memory blocks BLKO to BLK3 may be disposed on the first semiconductor layer L1, and the pass transistor circuit 210B may be disposed in the first area R1 corresponding to the stair-stepped area SA of the word lines WL connected to the first to fourth memory blocks BLKO to BLK3 in the second semiconductor layer L2.

The first to fourth pass transistors TR_0 to TR_3 included in the pass transistor circuit 210B may be divided into first to sixth pass transistor groups GR0 to GR5. The first pass transistor group GR0 may be disposed in the first stage STAGE0, the second pass transistor group GR1 may be disposed in the second stage STAGE1, the third pass transistor group GR2 may be disposed in the third stage STAGE2, the fourth pass transistor group GR3 may be disposed in the fourth stage STAGE3, the fifth pass transistor group GR4 may be disposed in the fifth stage STAGE4, and the sixth pass transistor group GR5 may be disposed in the sixth stage STAGES.

In some embodiments, the first pass transistor group GR0 may include some of the first pass transistors TR_0, the second pass transistor group GR1 may include some of the second pass transistors TR_1, and the third pass transistor group GR2 may include the rest of the first pass transistors TR_0 and the rest of the second pass transistors TR_1. In the third pass transistor group GR2, the first and second pass transistors TR_0 and TR_1 connected to the word lines disposed at the same level as each other may be disposed adjacent to each other.

In some embodiments, the fifth pass transistor group GR4 may include some of the third pass transistors TR_2, the sixth pass transistor group GR5 may include some of the fourth pass transistors TR_3, and the fourth pass transistor group GR3 may include the rest of the third pass transistors TR_2 and the rest of the fourth pass transistors TR_3. In the fourth pass transistor group GR3, the third and fourth pass transistors TR_2 and TR_3 connected to the word lines disposed at the same level as each other may be disposed adjacent to each other. For example, the third pass transistor TRa_2 and the fourth pass transistor TRb_3 included in the fourth pass transistor group GR3 may be connected to a first word line (e.g., WL0 (e.g., WL0 of BLK2 and WL0 of BLK3)) disposed at the same level. The above description of the pass transistor circuit 210B may also be applied to the pass transistor circuit 210B'.

<FIG> further illustrates some of the pass transistors that may be included in the pass transistor circuit 210B of <FIG>.

Referring to <FIG>, the pass transistor circuit 210B may be understood as a modified version of the pass transistor circuit <NUM> of <FIG>. In this example, the fourth pass transistor group GR3 may include third and fourth pass transistors TR41 and TR42 disposed in the fourth stage STAGE3. The third pass transistor TR41 may include a gate G41 connected to a third block selection signal line, a source S41 connected to the word line driving signal line (e.g., SI0), and a drain D41 connected to the word line (e.g., WL0 of BLK2). The fourth pass transistor TR42 may include a gate G42 connected to a fourth block selection signal line, a source S42 connected to the word line driving signal line (e.g., SI0), and a drain D42 connected to the word line (e.g., WL0 of BLK3).

In the third and fourth pass transistor groups GR2 and GR3, active areas of pass transistors adjacent to the first horizontal direction HD1 may be shared. The sources S31 and S41 may be formed in an active area sharing method, and for example, the word line driving signal line SI0 may be connected to the sources S31 and S41. Similarly, the sources S32 and S42 may be formed in an active area sharing method, and for example, the word line driving signal line SI0 may be connected to the sources S32 and S42.

The fifth pass transistor group GR4 may include third pass transistors TR51 and TR52 disposed in the fifth stage STAGE4. The third pass transistor TR51 may include a gate G51 connected to a third block selection signal line, a source S51 connected to the word line driving signal line (e.g., SI2), and a drain D51 connected to the word line (e.g., WL2 of BLK2). The third pass transistor TR52 may include a gate G52 connected to a third block selection signal line, a source S52 connected to the word line driving signal line (e.g., SI3), and a drain D52 connected to the word line (e.g., WL3 of BLK2).

The sixth pass transistor group GR5 may include fourth pass transistors TR61 and TR62 disposed in the sixth stage STAGES. The fourth pass transistor TR61 may include a gate G61 connected to a fourth block selection signal line, a source S61 connected to the word line driving signal line (e.g., SI2), and a drain D61 connected to the word line (e.g., WL2 of BLK3). The fourth pass transistor TR62 may include a gate G62 connected to a fourth block selection signal line, a source S62 connected to the word line driving signal line (e.g., SI3), and a drain D62 connected to the word line (e.g., WL3 of BLK3).

In the fifth and sixth pass transistor groups GR4 and GR5, active areas of pass transistors adjacent to the first horizontal direction HD1 may be shared. The sources S51 and S61 may be formed in an active area sharing method, and for example, the word line driving signal line SI2 may be connected to the sources S51 and S61. Similarly, the sources S52 and S62 may be formed in an active area sharing method, and for example, the word line driving signal line SI3 may be connected to the sources S52 and S62.

<FIG> is a plan view further illustrating a stair-stepped area SA of a memory device <NUM> according to embodiments of the inventive concept, and <FIG> is an exploded perspective view of the stair-stepped area SA of <FIG>.

Referring to <FIG> and <FIG>, word lines WL (e.g. WLa, WLb, WLc, WLd) may be stacked in the vertical direction VD on the first semiconductor layer L1. In the stair-stepped area SA, word lines WL may be arranged in a stair-stepped configuration. The stair-stepped area SA may be divided into first, second and third stair-stepped areas SA1, SA2 and SA3. A first contact area CA1 may be disposed in the first stair-stepped area SA1, a second contact area CA2 may be disposed in the second stair-stepped area SA2, and a third contact area CA3 may be disposed in the third stair-stepped area SA3.

A first flat pad area FPA1 may be defined between the first contact area CA1 and the second contact area CA2, and a second flat pad area FPA2 may be defined between the second contact area CA2 and the third contact area CA3. Through electrodes (e.g., through silicon vias THV) may be disposed in the first and second flat pad areas FPA1 and FPA2. The through electrodes THV may pass through the word lines WL as they extend in the vertical direction VD. In this case, an insulating layer may be formed between each through electrode THV and the word lines WL, and accordingly, each through electrode THV and the word lines WL may be electrically insulated from each other.

Each of the first to third contact areas CA1 to CA3 may include word line contact areas WLCA, and the number of word line contact areas WLCA may correspond to the number of word lines WL. In each word line contact area WLCA, a contact plug CT1 for connecting a pass transistor corresponding to the word line WL may be disposed. For example, the contact plug CT1 may be disposed in the word line contact area WLCAa, and the contact plug CT2 may be disposed in the source/drain area of the pass transistor TRa.

The contact plugs CT1 and CT2 may be electrically connected using an upper metal layer MT_U and a lower metal layer MT_L. The upper metal layer MT_U may be included in the first semiconductor layer L1 and may extend in the second horizontal direction HD2. The lower metal layer MT_L may be included in the second semiconductor layer L2 and may include first to third metal layers MT1 to MT3. For example, the first and third metal layers MT1 and MT3 may extend in a first horizontal direction HD1, and the second metal layer MT2 may extend in a second horizontal direction HD2.

The second semiconductor layer L2 may include a first area R1 disposed below the stair-stepped area SA in a vertical direction VD, and pass transistors TRa to TRd may be disposed in the first area R1. The first area R1 may be divided into first areas R1a to R1c corresponding to the first to third stair-stepped areas SA1 to SA3, respectively. The word line contact areas included in the first contact area CA1 may be connected to pass transistors disposed in the first area R1a of the second semiconductor layer L2, the word line contact areas included in the second contact area CA2 may be connected to pass transistors disposed in the first area R1b of the second semiconductor layer L2, and the word line contact areas included in the third contact area CA3 may be connected to pass transistors disposed in the first area R1c of the second semiconductor layer L2.

For example, the word line contact area WLCAa (e.g., a contact area of a word line WLa) may be connected to the pass transistor TRa through the contact plug CT1, the upper metal layer MT_U, the through electrode THV, the first to third metal layers MT1 to MT3, and the contact plug CT2. For example, the contact plug CT2 may be formed on the source/drain area (e.g., the drain area) of the pass transistor TRa. Similarly, the word line contact area WLCAb (e.g., a contact area of a word line WLb) may be connected to the pass transistor TRb, the word line contact area WLCAc (e.g., a contact area of a word line WLc) may be connected to the pass transistor TRc, and the word line contact area WLCAd (e.g., a contact area of a word line WLd) may be connected to the pass transistor TRd.

<FIG> illustrates an example of wiring between a pass transistor and a word line contact according to embodiments of the inventive concept.

Referring to <FIG>, <FIG>, and <FIG>, a memory device <NUM> may be understood as a modified version of the memory device <NUM> of <FIG>. Thus, referring to <FIG>, <FIG> and <FIG>, the area shown in <FIG> may correspond to the second stair-stepped area SA2 of <FIG> and <FIG>. Word lines WL may be stacked in a vertical direction VD and word line contact areas WLCA may be disposed in the first semiconductor layer L1. First and second pass transistors TR_0 and TR_1 may be disposed in the second semiconductor layer L2.

For example, the word line contact area WLCA_A may correspond to a contact area of the word line (e.g., WL18) of the second memory block BLK1, and the word line contact area WLCA_A' may correspond to a contact area of the word line (e.g., WL18) of the first memory block BLKO. For example, a pass transistor <NUM> may be connected to a word line (e.g., WL18) of the second memory block BLK1, and a pass transistor <NUM> may be connected to a word line (e.g., WL18) of the first memory block BLKO.

The word line contact area WLCA_A may be connected to the pass transistor <NUM> through the contact plug CT1, the upper metal layer MT_U, the lower metal layer MT_L, and the contact plug CT2, and the first length of the wiring connecting the word line contact area WLCA_A to the pass transistor <NUM> may correspond to the sum of the lengths of the upper metal layer MT_U and the lower metal layer MT_L. Further, the word line contact area WLCA_A' may also be connected to the pass transistor <NUM> through the contact plug CT1, the upper metal layer MT_U, the lower metal layer MT_L, and the contact plug CT2, and the second length of the wiring connecting the word line contact area WLCA_A' to the pass transistor <NUM> may correspond to the sum of the lengths of the upper metal layer MT_U and the lower metal layer MT_L. In this example, the difference between the first length and the second length may not be large (e.g. the first length and the second length in <FIG> may be substantially the same), and accordingly, pass resistances of the word line (e.g., WL18) of the first memory block BLKO and the word line (e.g., WL18) of the second memory block BLK1 may be similar to each other (e.g. substantially the same).

<FIG> illustrates an example of wiring between a pass transistor and a word line contact according to a comparative example for certain embodiments of the inventive concept.

Referring to <FIG>, <FIG>, and <FIG>, in a comparative memory device <NUM>, for example, the word line contact area WLCA_A may correspond to a contact area of the word line (e.g., WL18) of the second memory block BLK1, and the word line contact area WLCA_A' may correspond to a contact area of the word line (e.g., WL18) of the first memory block BLKO. For example, the pass transistor <NUM> may be connected to a word line (e.g., WL18) of the second memory block BLK1, and the pass transistor <NUM> may be connected to a word line (e.g., WL18) of the first memory block BLKO.

The word line contact area WLCA_A may be connected to the pass transistor <NUM> through the contact plug CT1, the upper metal layer MT_U, the lower metal layer MT_L, and the contact plug CT2, and the first length of the wiring connecting the word line contact area WLCA_A to the pass transistor <NUM> may correspond to the sum of the lengths of the upper metal layer MT_U and the lower metal layer MT_L. Meanwhile, the word line contact area WLCA_A' may also be connected to the pass transistor <NUM> through the contact plug CT1, the upper metal layer MT_U, the lower metal layer MT_L, and the contact plug CT2, and the second length of the wiring connecting the word line contact area WLCA_A' to the pass transistor <NUM> may correspond to the sum of the lengths of the upper metal layer MT_U and the lower metal layer MT_L.

Comparing the embodiment of <FIG> and the comparative example of <FIG>, a difference between the first length and the second length in <FIG> is notable (e.g. significantly different). Accordingly, pass resistances of the word line (e.g., WL18) of the first memory block BLKO and the word line (e.g., WL18) of the second memory block BLK1 may be significantly different, and as a result, loading time skews between word lines may occur. However, according to embodiments of the inventive concept, like those variously illustrated in <FIG>, since the pass resistance of the word lines of the same level as each other is substantially the same, it is possible to reduce or eliminate loading time skews between the word lines of the same level.

<FIG> is a cross-sectional view illustrating a memory device <NUM> according to embodiments of the inventive concept.

Referring to <FIG>, the memory device <NUM> includes a first semiconductor layer L1 and a second semiconductor layer L2, and may be formed in a COP structure. The first semiconductor layer L1 may include a cell area CA and first and second stair-stepped areas SAa and SAb. A plurality of channel structures CHS may be formed in the cell area CA. Word line contact areas may be formed in the first and second stair-stepped areas SAa and SAb, and a contact plug CT1 may be disposed in each word line contact area. The contact plug CT1 may be connected to the through electrode THV through the upper metal layer MT_U, and the through electrode THV may penetrate the plurality of word lines WL.

Pass transistor circuits <NUM> and <NUM>' each including a plurality of pass transistors TR may be disposed on the second semiconductor layer L2. Specifically, in the second semiconductor layer L2, a pass transistor circuit <NUM> may be disposed in an area corresponding to the first stair-stepped area SAa, and a pass transistor circuit <NUM>' may be disposed in an area corresponding to the second stair-stepped area SAb.

Referring to <FIG>, the memory device <NUM> includes a first chip CHIP1 and a second chip CHIP2, and may be formed in a chip to chip (C2C) structure. Here, the C2C structure may mean that after fabricating an upper chip including a cell area CA on the first wafer, that is, a first chip CHIP1, and fabricating a lower chip including the peripheral circuit area PERI, that is, a second chip CHIP2 on a second wafer different from the first wafer, the first chip CHIP1 and the second chip CHIP2 are connected to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the uppermost metal layer of the first chip CHIP1 and the bonding metal formed on the uppermost metal layer of the second chip CHIP2. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

The first chip (CHIP1) may include a cell area CA and first and second stair-stepped areas SAa and SAb. Channel structures CHS may be formed in the cell area CA. Word line contact areas may be formed in the first and second stair-stepped areas SAa and SAb, and a contact plug CT1 may be disposed in each word line contact area. The contact plug CT1 may be connected to the upper bonding pad BP_U through the upper metal layer MT_U. Pass transistor circuits <NUM> and <NUM>' each including pass transistors TR may be disposed on the second chip (CHIP2). That is, in the second semiconductor layer L2, a pass transistor circuit <NUM> may be disposed in an area corresponding to the first stair-stepped area SAa, and a pass transistor circuit <NUM>' may be disposed in an area corresponding to the second stair-stepped area SAb. A contact plug CT2 may be disposed on the source/drain area of the pass transistor TR, and may be connected to the lower bonding pad BP_L through the lower metal layer MT_L. The word line contact area may be electrically connected to the pass transistor TR through the connection between the upper bonding pad BP_U and the lower bonding pad BP_L.

Referring to <FIG>, the memory device <NUM> may have a C2C structure. The embodiments illustrated in <FIG> may be implemented similar to the memory device <NUM>. That is, the pass transistor circuit described above with reference to <FIG> may be disposed in the peripheral circuit area (PERI). Each of the peripheral circuit area and the cell area (CELL) of the memory device <NUM> may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. The peripheral circuit area may include a first substrate <NUM>, an interlayer insulating layer <NUM>, circuit elements 320a, 320b, and 320c formed on the first substrate <NUM>, first metal layers 330a, 330b, and 330c respectively connected to the circuit elements 320a, 320b, and 320c, and second metal layers 340a, 340b, 340c formed on the first metal layers 330a, 330b, 330c. In some embodiments, the first metal layers 330a, 330b, and 330c may be formed of tungsten having a relatively high resistance, and the second metal layers 340a, 340b and 340c may be formed of copper having a relatively low resistance.

In this example, only the first metal layers 330a, 330b, and 330c and the second metal layers 340a, 340b, and 340c are shown and described, but the inventive concept is not limited thereto, and at least one metal layer may be further formed on the second metal layers 340a, 340b, and 340c. At least some of the one or more metal layers formed on the second metal layers 340a, 340b, and 340c may be formed of aluminum or the like having a lower resistance than copper forming the second metal layers 340a, 340b, and 340c.

The interlayer insulating layer <NUM> may be disposed on the first substrate <NUM> to cover the plurality of circuit elements 320a, 320b, and 320c, the first metal layers 330a, 330b, and 330c, and the second metal layers 340a, 340b, and 340c, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 371b and 372b may be formed on the second metal layer 340b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 371b and 372b of the peripheral circuit area may be electrically connected to each other by a bonding method with the upper bonding metals 471b and 472b of the cell area, and the lower bonding metals 371b and 372b and the upper bonding metals 471b and 472b may be formed of aluminum, copper, or tungsten. The upper bonding metals 471b and 472b of the cell area may be referred to as first metal pads, and the lower bonding metals 371b and 372b of the peripheral circuit area may be referred to as second metal pads.

The cell area may provide at least one memory block. The cell area may include a second substrate <NUM> and a common source line <NUM>. On the second substrate <NUM>, word lines <NUM> to <NUM> (i.e., <NUM>) may be stacked along a direction VD perpendicular to the upper surface of the second substrate <NUM>. String selection lines and ground selection lines may be disposed on each of the upper and lower portions of the word lines <NUM>, and the word lines <NUM> may be disposed between the string selection lines and the ground selection line.

In the bit line bonding area BLBA, the channel structure CHS may extend in a direction perpendicular to the upper surface of the second substrate <NUM> to pass through the word lines <NUM>, the string selection lines, and the ground selection lines. The channel structure CHS may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 450c and the second metal layer 460c. For example, the first metal layer 450c may be a bit line contact, and the second metal layer 460c may be a bit line. In an embodiment, the bit line 460c may extend in a first horizontal direction HD1 parallel to the upper surface of the second substrate <NUM>.

In the embodiment illustrated in <FIG>, an area where the channel structure CHS and the bit line 460c are disposed may be defined as the bit line bonding area BLBA. The bit line 460c may be electrically connected to the circuit elements 320c providing the page buffer <NUM> in the peripheral circuit area in the bit line bonding area BLBA. As an example, the bit line 460c is connected to the upper bonding metals 471c and 472c in the peripheral circuit area, and the upper bonding metals 471c and 472c may be connected to the lower bonding metals 371c and 372c connected to the circuit elements 320c of the page buffer <NUM>.

In the word line bonding area WLBA, the word lines <NUM> may extend along a second horizontal direction HD2 parallel to the upper surface of the second substrate <NUM>, and may be connected to a plurality of cell contact plugs <NUM> to <NUM> (i.e., <NUM>). The word lines <NUM> and the cell contact plugs <NUM> may be connected to each other by pads provided by extending at least some of the word lines <NUM> to different lengths along the second horizontal direction. The first metal layer 450b and the second metal layer 460b may be sequentially connected to the upper portions of the cell contact plugs <NUM> connected to the word lines <NUM>. The cell contact plugs <NUM> may be connected to the peripheral circuit area through the upper bonding metals 471b and 472b of the cell area and the lower bonding metals 371b and 372b of the peripheral circuit area in the word line bonding area WLBA.

The cell contact plugs <NUM> may be electrically connected to the circuit elements 320b providing the row decoder <NUM> in the peripheral circuit area PERI. In an embodiment, operating voltages of the circuit elements 320b providing the row decoder <NUM> may be different from the operating voltages of the circuit elements 320c providing the page buffer <NUM>. For example, the operating voltages of the circuit elements 320c providing the page buffer <NUM> may be greater than the operating voltages of the circuit elements 320b providing the row decoder <NUM>.

A common source line contact plug <NUM> may be disposed in the outer pad bonding area PA. The common source line contact plug <NUM> is formed of a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source line <NUM>. A first metal layer 450a and a second metal layer 460a may be sequentially stacked on the common source line contact plug <NUM>. For example, an area where the common source line contact plug <NUM>, the first metal layer 450a, and the second metal layer 460a are disposed may be defined as an outer pad bonding area PA.

Further, I/O pads <NUM> and <NUM> may be disposed in the outer pad bonding area PA. Referring to <FIG>, a lower insulating layer <NUM> covering a lower surface of the first substrate <NUM> may be formed under the first substrate <NUM>, and a first I/O pad <NUM> may be formed on the lower insulating layer <NUM>. The first I/O pad <NUM> may be connected to at least one of the plurality of circuit elements 320a, 320b, and 320c disposed in the peripheral circuit area through the first I/O contact plug <NUM>, and may be separated from the first substrate <NUM> by the lower insulating layer <NUM>. In addition, a side insulating layer may be disposed between the first I/O contact plug <NUM> and the first substrate <NUM> to electrically separate the first I/O contact plug <NUM> from the first substrate <NUM>.

Referring to <FIG>, an upper insulating layer <NUM> covering an upper surface of the second substrate <NUM> may be formed on the second substrate <NUM>, and a second I/O pad <NUM> may be disposed on the upper insulating layer <NUM>. The second I/O pad <NUM> may be connected to at least one of the plurality of circuit elements 320a, 320b, and 320c disposed in the peripheral circuit area PERI through the second I/O contact plug <NUM>. For example, the second I/O pad <NUM> may be connected to the circuit elements 320a through the second I/O contact plug <NUM>, the upper metal patterns of the memory cell area CELL, and the lower metal patterns 372a and 371a of the peripheral circuit area PERI.

According to embodiments, the second substrate <NUM> and the common source line <NUM> may not be disposed in an area where the second I/O contact plug <NUM> is disposed. Also, the second I/O pad <NUM> may not overlap with the word lines <NUM> in the vertical direction (e.g., the Z-axis direction). Referring to <FIG>, the second I/O contact plug <NUM> may be separated from the second substrate <NUM> in a direction (e.g., the X-axis direction) parallel to the upper surface of the second substrate <NUM>, and may pass through the interlayer insulating layer <NUM> of the cell area to be connected to the second I/O pad <NUM>.

In some embodiments, the first I/O pad <NUM> and the second I/O pad <NUM> may be selectively formed. For example, the memory device <NUM> may include only the first I/O pad <NUM> disposed on the first substrate <NUM>, or may include only the second I/O pad <NUM> disposed on the second substrate <NUM>. Alternatively, the memory device <NUM> may include both the first I/O pad <NUM> and the second I/O pad <NUM>.

In each of the outer pad bonding area PA and the bit line bonding area BLBA respectively included in the cell area and the peripheral circuit area, the metal pattern of the uppermost metal layer may exist as a dummy pattern, or the uppermost metal layer may be empty.

In relation to the memory device <NUM>, a lower metal pattern 373a having the same shape as the upper metal pattern 472a of the cell area may be formed on the uppermost metal layer of the peripheral circuit area in correspondence to the upper metal pattern 472a formed on the uppermost metal layer of the cell area in the outer pad bonding area PA. The lower metal pattern 373a formed on the uppermost metal layer of the peripheral circuit area may not be connected to a separate contact in the peripheral circuit area. Similarly, in correspondence to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area in the outer pad bonding area PA, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit area may be formed on the upper metal layer of the cell area.

Lower bonding metals 371b and 372b may be formed on the second metal layer 340b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 371b and 372b of the peripheral circuit area may be electrically connected to each other through a bonding method with the upper bonding metals 471b and 472b of the cell area.

Also, in the bit line bonding area BLBA, in correspondence to the lower metal pattern <NUM> formed on the uppermost metal layer of the peripheral circuit area, an upper metal pattern <NUM> having the same shape as the lower metal pattern <NUM> of the peripheral circuit area may be formed on the uppermost metal layer of the cell area. A contact may not be formed on the upper metal pattern <NUM> formed on the uppermost metal layer of the cell area.

Referring to <FIG>, in contrast to the memory device <NUM> of <FIG>, the memory device <NUM> may include two or more upper chips on the cell area. That is, the memory device <NUM> may have a structure in which the first upper chip including the first cell area (CELL1), the second upper chip including the second cell area (CELL2), and the lower chip including the peripheral circuit area (PERI) are connected by a bonding method. However, the number of upper chips is not limited thereto. Among the descriptions of the first cell area, the second cell area, and the peripheral circuit area, portions previous provided in relation to <FIG> will be omitted. Hereinafter, the cell area may refer to at least one of the first cell area and/or the second cell area.

The cell area may include a lower channel LCH and an upper channel UCH connected to each other in the bit line bonding area BLBA. The lower channel LCH and the upper channel UCH may be connected to each other to form one channel structure CHS. That is, in contrast to the channel structure CHS of <FIG>, the channel structure CHS of <FIG> may be formed through a process for the lower channel LCH and a process for the upper channel UCH. In the first cell area CELL1, the lower channel LCH extends in a direction perpendicular to the upper surface of the third substrate <NUM> to pass through the common source line <NUM> and the lower word lines <NUM> to <NUM>. The lower channel LCH may include a data storage layer, a channel layer, and a buried insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may pass through the upper word lines <NUM> to <NUM>. The upper channel UCH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal layer 650c and the second metal layer 660c. As the length of the channel increases, it may be difficult to form a channel having a constant width due to process reasons. The memory device <NUM> according to embodiments of the inventive concept may include a channel having improved width uniformity through the lower channel LCH and the upper channel UCH formed through a sequential process.

As described above, a string selection line and a ground selection line may be disposed above and below the word lines <NUM> (i.e. <NUM>-<NUM>) and <NUM> (i.e. <NUM>-<NUM>), respectively. In some embodiments, a word line adjacent to a string selection line or a word line adjacent to a ground selection line may be a dummy word line. Further, in the memory device <NUM> of <FIG>, a word line positioned near a boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, the word line <NUM> and the word line <NUM> forming a boundary between the lower channel LCH and the upper channel UCH may be dummy word lines.

In the bit line bonding area BLBA, the first cell area may include a first through electrode THV1, and the second cell area may include a second through electrode THV2. The first through electrode THV1 may pass through the common source line <NUM> and the plurality of word lines <NUM>. The first through electrode THV1 may further penetrate the third substrate <NUM>. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may also be the same as the first through electrode THV1. The first through electrode THV1 and the second through electrode THV2 may be electrically connected through the first through upper metal pattern 672b and the second through lower metal pattern 771d. The first through upper metal pattern 672b may be formed at an upper end of the first upper chip including the first cell area, and the second through lower metal pattern 771d may be formed at a lower end of the second upper chip including the second cell area. The first through electrode THV1 may be electrically connected to the first metal layer 650c and the second metal layer 660c. A first through via 671b may be formed between the second metal layer 660c and the first through upper metal pattern 672b, and a second through via 772d may be formed between the second through electrode THV2 and the second through lower metal pattern 771d. The first through upper metal pattern 672b and the second through lower metal pattern 771d may be connected by a bonding method.

In some embodiments, a first upper metal pattern 672a may be formed on an upper end of the first cell area, and a first lower metal pattern 771e may be formed on a lower end of the second cell area. The first upper metal pattern 672a of the first cell area and the first lower metal pattern 771e of the second cell area may be connected in the outer pad bonding area PA by a bonding method. Further, a second upper metal pattern 772a may be formed at an upper end of the second cell area and a second lower metal pattern 873a may be formed at a lower end of the peripheral circuit area PERI. The second upper metal pattern 772a of the second cell area and the second lower metal pattern 873a of the peripheral circuit area PERI may be connected in the outer pad bonding area PA by a bonding method.

The peripheral circuit area PERI may include a first substrate <NUM>, an interlayer insulating layer <NUM>, circuit elements 820a, 820b, and 820c formed on the first substrate <NUM>, first metal layers 830a, 830b, and 830c respectively connected to the circuit elements 820a, 820b, and 820c, and second metal layers 840a, 840b, 840c formed on the first metal layers 830a, 830b, 830c. In some embodiments, the first metal layers 830a, 830b, and 830c may be formed of tungsten having a relatively high resistance, and the second metal layers 840a, 840b and 840c may be formed of copper having a relatively low resistance.

In this example, only the first metal layers 830a, 830b, and 830c and the second metal layers 840a, 840b, and 840c are shown and described, but the inventive concept is not limited thereto, and at least one metal layer may be further formed on the second metal layers 840a, 840b, and 840c. At least some of the one or more metal layers formed on the second metal layers 840a, 840b, and 840c may be formed of aluminum or the like having a lower resistance than copper forming the second metal layers 840a, 840b, and 840c.

The interlayer insulating layer <NUM> may be disposed on the first substrate <NUM> to cover the plurality of circuit elements 820a, 820b, and 820c, the first metal layers 830a, 830b, and 830c, and the second metal layers 840a, 840b, and 840c, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 871b and 872b may be formed on the second metal layer 840b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 871b and 872b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method with upper bonding metals 771b and 772b of the second cell area CELL2, and the lower bonding metals 871b and 872b and the upper bonding metals 771b and 772b may be formed of aluminum, copper, or tungsten. The upper bonding metals 771b and 772b of the second cell area CELL2 may be referred to as first metal pads, and the lower bonding metals 871b and 872b of the peripheral circuit area PERI may be referred to as second metal pads.

The second cell area CELL2 may include a second substrate <NUM> and a common source line <NUM>. On the second substrate <NUM>, word lines <NUM> to <NUM> (i.e., <NUM>) may be stacked along a vertical direction Z perpendicular to the upper surface of the second substrate <NUM>. String selection lines and ground selection lines may be disposed on each of the upper and lower portions of the word lines <NUM>, and the word lines <NUM> may be disposed between the string selection lines and the ground selection line.

For example, the first metal layer 750c may be a bit line contact, and the second metal layer 760c may be a bit line. In an embodiment, the bit line 760c may extend in a first horizontal direction Y parallel to the upper surface of the second substrate <NUM>. The bit line 760c may be electrically connected to the circuit elements 820c providing a page buffer <NUM> in the peripheral circuit area PERI in the bit line bonding area BLBA. As an example, the bit line 760c is connected to the upper bonding metals 771c and 772c, and the upper bonding metals 771c and 772c may be connected to lower bonding metals 871c and 872c connected to the circuit elements 820c of the page buffer <NUM>.

In the word line bonding area WLBA, the word lines <NUM> may extend along a second horizontal direction X parallel to the upper surface of the second substrate <NUM>, and may be connected to a plurality of cell contact plugs <NUM> to <NUM> (i.e., <NUM>). The word lines <NUM> and the cell contact plugs <NUM> may be connected to each other by pads provided by extending at least some of the word lines <NUM> to different lengths along the second horizontal direction X. A first metal layer 750b and a second metal layer 760b may be sequentially connected to the upper portions of the cell contact plugs <NUM> connected to the word lines <NUM>. The cell contact plugs <NUM> may be connected to the peripheral circuit area PERI through the upper bonding metals 771b and 772b of the second cell area CELL2 and the lower bonding metals 871b and 872b of the peripheral circuit area PERI in the word line bonding area WLBA.

The cell contact plugs <NUM> may be electrically connected to the circuit elements 820b providing a row decoder <NUM> in the peripheral circuit area PERI. In an embodiment, operating voltages of the circuit elements 820b providing the row decoder <NUM> may be different from the operating voltages of the circuit elements 820c providing the page buffer <NUM>. For example, the operating voltages of the circuit elements 820c providing the page buffer <NUM> may be greater than the operating voltages of the circuit elements 820b providing the row decoder <NUM>.

A common source line contact plug <NUM> may be disposed in the outer pad bonding area PA. The common source line contact plug <NUM> is formed of a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source line <NUM>. A first metal layer 750a and a second metal layer 760a may be sequentially stacked on the common source line contact plug <NUM>. For example, an area where the common source line contact plug <NUM>, the first metal layer 750a, and the second metal layer 760a are disposed may be defined as an outer pad bonding area PA. The second metal layer 760a is connected to upper bonding metal 771a.

The first cell area CELL1 may include a first substrate <NUM> and a common source line <NUM>. On the third substrate <NUM>, word lines <NUM> to <NUM> (i.e., <NUM>) may be stacked along the vertical direction Z perpendicular to the upper surface of the third substrate <NUM>. String selection lines and ground selection lines may be disposed on each of the upper and lower portions of the word lines <NUM>, and the word lines <NUM> may be disposed between the string selection lines and the ground selection line.

For example, a first metal layer 650c may be a bit line contact, and a second metal layer 660c may be a bit line. In an embodiment, the bit line 660c may extend in the first horizontal direction Y parallel to the upper surface of the third substrate <NUM>. The bit line 660c may be electrically connected to the circuit elements 620c providing the page buffer <NUM> in the peripheral circuit area PERI in the bit line bonding area BLBA.

In the word line bonding area WLBA, the word lines <NUM> may extend along the second horizontal direction X parallel to the upper surface of the third substrate <NUM>, and may be connected to a plurality of cell contact plugs <NUM> to <NUM> (i.e., <NUM>). The word lines <NUM> and the cell contact plugs <NUM> may be connected to each other by pads provided by extending at least some of the word lines <NUM> to different lengths along the second horizontal direction X. For example, the cell contact plug <NUM> is connected to a contact plug <NUM> of the second cell area CELL2.

A common source line contact plug <NUM> may be disposed in the outer pad bonding area PA. The common source line contact plug <NUM> is formed of a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source line <NUM>. A first metal layer 650a and a second metal layer 760a may be sequentially stacked on the common source line contact plug <NUM>. For example, an area where the common source line contact plug <NUM>, the first metal layer 650a, and a second metal layer 660a are disposed may be defined as an outer pad bonding area PA. The second metal layer 660a is connected to the first metal layer 750a through upper bonding metals 671a and 672a and a contact plug <NUM>.

Further, I/O pads <NUM> and <NUM> may be disposed in the outer pad bonding area PA. Referring to <FIG>, a lower insulating layer <NUM> covering a lower surface of the first substrate <NUM> may be formed under the first substrate <NUM>, and a first I/O pad <NUM> may be formed on the lower insulating layer <NUM>. The first I/O pad <NUM> may be connected to at least one of the plurality of circuit elements 820a, 820b, and 820c disposed in the peripheral circuit area through a first I/O contact plug <NUM>, and may be separated from the first substrate <NUM> by the lower insulating layer <NUM>. In addition, a side insulating layer may be disposed between the first I/O contact plug <NUM> and the first substrate <NUM> to electrically separate the first I/O contact plug <NUM> from the first substrate <NUM>.

Referring to <FIG>, an upper insulating layer <NUM> covering an upper surface of the third substrate <NUM> may be formed on the third substrate <NUM>, and a second I/O pad <NUM> may be disposed on the upper insulating layer <NUM>. The second I/O pad <NUM> may be connected to at least one of the plurality of circuit elements 820a, 820b, and 820c disposed in the peripheral circuit area PERI through a third I/O contact plug <NUM> and a second I/O contact plug <NUM>. For example, the second I/O pad <NUM> may be connected to the circuit elements 820a through the second I/O contact plug <NUM>, the upper metal patterns of the second memory cell area CELL2, and lower metal patterns 872a and 871a of the peripheral circuit area PERI.

According to embodiments, the second substrate <NUM> and the common source line <NUM> may not be disposed in an area where the second I/O contact plug <NUM> is disposed. Also, the second I/O pad <NUM> may not overlap with the word lines <NUM> and <NUM> in the vertical direction Z. Referring to <FIG>, the second I/O contact plug <NUM> may be separated from the second substrate <NUM> in the second horizontal direction X parallel to the upper surface of the second substrate <NUM>, and may pass through an interlayer insulating layer <NUM> of the second cell area CELL2. The third I/O contact plug <NUM> may be separated from the third substrate <NUM> in the second horizontal direction X parallel to the upper surface of the third substrate <NUM>, and may pass through an interlayer insulating layer <NUM> of the first cell area CELL1 to be connected to the second I/O pad <NUM>.

In some embodiments, the first I/O pad <NUM> and the second I/O pad <NUM> may be selectively formed. For example, the memory device <NUM> may include only the first I/O pad <NUM> disposed on the first substrate <NUM>, or may include only the second I/O pad <NUM> disposed on the third substrate <NUM>. Alternatively, the memory device <NUM> may include both the first I/O pad <NUM> and the second I/O pad <NUM>.

In each of the outer pad bonding area PA and the bit line bonding area BLBA respectively included in the first and second cell areas and the peripheral circuit area, the metal pattern of the uppermost metal layer may exist as a dummy pattern, or the uppermost metal layer may be empty.

Lower bonding metals 871b and 872b may be formed on the second metal layer 840b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 871b and 872b of the peripheral circuit area may be electrically connected to each other through a bonding method with the upper bonding metals 771b and 772b of the second cell area CELL2.

Also, in the bit line bonding area BLBA, in correspondence to the lower metal pattern <NUM> formed on the uppermost metal layer of the peripheral circuit area, an upper metal pattern <NUM> having the same shape as the lower metal pattern <NUM> of the peripheral circuit area PERI may be formed on the uppermost metal layer of the second cell area CELL2. A contact may not be formed on the upper metal pattern <NUM> formed on the uppermost metal layer of the second cell area CELL2.

<FIG> is a block diagram illustrating a memory device according to embodiments of the inventive concept, as applied to an SSD system <NUM>.

Referring to <FIG>, the SSD system <NUM> may include a host <NUM> and an SSD <NUM>. The SSD <NUM> exchanges signals SIG with the host <NUM> through a signal connector, and receives power PWR through a power connector. The SSD <NUM> may include an SSD controller <NUM>, an auxiliary power supply device <NUM>, and memory devices <NUM>, <NUM>, and <NUM>. The memory devices <NUM>, <NUM>, and <NUM> may be vertically stacked NAND flash memory devices(e.g., MEM <NUM> to MEM n, where n is a positive integer). The memory devices <NUM>, <NUM>, and <NUM> may communicate with the SSD controller <NUM> through channels Ch1 to Chn. In this case, the SSD <NUM> may be implemented using the embodiments described above with reference to <FIG> and <FIG>.

Claim 1:
A memory device (<NUM>) comprising:
a three-dimensional memory cell array (<NUM>) including a first memory block (BLK0) and a second memory block (BLK1) adjacently disposed in a first horizontal direction (HD1);
driving signal lines (SS, SI, GS) respectively corresponding to vertically stacked word lines (WL); and
a pass transistor circuit (<NUM>; <NUM>'; 210a; 210A; 210A'; 210B; 210B') including an odd number of pass transistor groups (GRO, GR1, GR2) and connected between the driving signal lines and the three-dimensional memory cell array (<NUM>),
wherein the odd number of pass transistor groups (GRO, GR1, GR2) are arranged along the first horizontal direction (HD1), and one of the odd number of pass transistor groups includes:
a first pass transistor (TRa_0; TR32) connected between a first word line (WL0) of the first memory block (BLK0) and a first driving signal line among the driving signal lines, and
a second pass transistor (TRa_1; TR31) connected between a first word line of the second memory block (BLK0) and the first driving signal line and adjacently disposed to the first pass transistor (TRa_0) in a second horizontal direction (HD2).