Patent Description:
Phased array antennas (also referred to as "phased arrays") are used in communication, radar, and direction-finding systems as well as in other multifunction radio frequency (RF) systems. The phased array antenna typically includes an array of individual radiating antenna elements. The selection of the individual radiating element and arrangement of such elements affect the ability to efficiently transmit and receive RF signals having multiple polarizations.

One example of an architecture used to facilitate a phase array antenna is referred to as a "PCB array. " The PCB array architecture typically implements two separate array packages on opposite surfaces of a relatively long printed circuit boards (PCBs), thus giving rise to the name of a "PCB" array. The large surface area existing across the depth of each individual PCB provides a large area to mount components and transmit/receive modules, while also distributing thermal loads across a large volume.

<CIT> describes perpendicular end fire antenna. <NPL> describe a dual polarized millimeter-wave multibeam phased array.

According to the present invention, a dual-polarized PCB array antenna is provided as set forth in claim <NUM>. Preferred embodiments are set forth in dependent claims. According to a non-limiting embodiment, a dual-polarized PCB array antenna is provided. The dual-polarized PCB array antenna comprises a plurality of PCBS and a radiating antenna array. The plurality of PCBs, each PCB extends along a first axis to define a PCB width, a second axis orthogonal to the first axis to define a PCB height, and a third axis orthogonal to the first axis and the second axis to define a PCB length. Each PCB has a PCB mounting surface that extends along the second axis from a first PCB end to an opposing second PCB end and along the third axis from a third PCB end to a fourth PCB end. The radiating antenna array includes a plurality of radiator substrates. Each radiator substrate has a patch mounting surface that extends along the first axis from a first substrate end to an opposing second substrate end and the third axis from a third substrate end to an opposing fourth substrate end. The dual-polarized PCB array antenna further comprises a plurality of orthogonal interfaces configured to arrange the patch mounting surface of the plurality of radiator substrates in an orthogonal position with respect to the PCB mounting surface of the plurality of PCBs. The radiating antenna array includes a plurality of radiating antenna elements disposed on the patch mounting surface, wherein each radiator substrate is disposed on the first PCB end of a respective PCB, wherein a given orthogonal interface among the plurality of orthogonal interfaces arranges the patch mounting surface of a given radiator substrate in an orthogonal position with respect to the PCB mounting surface of a given PCB, and wherein the given orthogonal interface comprises: a plurality of electrically conductive traces formed on the given PCB mounting surface and comprises a plurality of electrically conductive pins extending through the patch mounting surface and contacting the electrically conductive traces.

According to yet another non-limiting embodiment, the contact between the plurality of electrically conductive traces and the plurality of electrically conductive pins establishes a shielded channel interface. The shielded channel interface may include a ground-signal-ground configuration or a signal-ground-signal configuration.

Additional features and advantages are realized through the techniques of the present disclosure. For a better understanding of the disclosure with the advantages and the features, refer to the description and to the drawings.

Various non-limiting embodiments described herein provide an orthogonal printed circuit board (PCB) interface for implementation in a dual-polarized PCB array antenna. The orthogonal printed circuit board (PCB) interface overcomes a technology gap that involves using only single PCB, while facilitating efficient dual-polarization via dual-polarized patch and stacked patch radiators integrated on a respective radiator substrate that is arranged orthogonally with respect to a mating PCB.

According to at least one non-limiting embodiment, the orthogonal PCB interface provides a high-efficiency connection between a radiator substrate arranged in an orthogonal position with respect to a PCB and completes the needed functionality to exchange signals in a phased array front-end. In addition, the orthogonal PCB interface provides minimal reflection coefficient performance within an operating frequency range compatible with contemporary phased arrays, along with also providing a minimal interference with electronic circuits and/or components (e.g., amplifiers, switches or hybrid circuits) included in the radiator substrate and the PCB. The orthogonal PCB interface also establishes a structural interface that provides a sufficient thermal boundary and exchange medium between the radiator substrate and the PCB. In this manner, the orthogonal PCB interface is capable of withstanding contemporary manufacturing processes and expected stress during phased array operation, transportation, and storage.

With reference now to <FIG>, a dual-polarized PCB array antenna <NUM> is illustrated according to a non-limiting embodiment. The dual-polarized PCB array antenna <NUM> includes a plurality of individual PCBs <NUM> and a radiating antenna array <NUM>. The PCBs <NUM> are arranged side-by-side along a first axis (e.g., an X-axis) and separated from one another by an air gap <NUM>. Each PCB <NUM> extends along the first axis (e.g., the X-axis) to define a PCB width (Wst), a second axis (e.g., a Y-axis) orthogonal to the first axis to define a PCB height (Hst), and a third axis (e.g., a Z-axis) orthogonal to the X-axis and the Y-axis to define a PCB length (Lst). The PCBs <NUM> can be formed from various materials that provide a dielectric constant (k) ranging, for example, from about <NUM> to about <NUM>, a dielectric loss tangent (tan δ) ranging, for example, from about. <NUM> to about. <NUM>, a coefficient of thermal expansion (CTE) ranging, for example, from about 10ppm/°C to about 220ppm/°C. In one or more embodiments, the PCBs <NUM> can be fabricated as a printed circuit board (PCB) that includes various circuits, traces, and/or electrical components.

Each PCB <NUM> has a PCB mounting surface <NUM> that extends along the Y-axis from a first PCB end (e.g., an upper end) to an opposing second PCB end (e.g., a lower end) and along the Z-axis from a third PCB end (e.g., a left end) to a fourth PCB end (e.g., a right end). The PCB mounting surface <NUM> includes a plurality of trace clusters <NUM> arranged side-by-side along the Z-axis. The trace clusters <NUM> assist in facilitating an interface between a given PCB <NUM> and the radiating antenna array <NUM> as described in greater detail below.

The radiating antenna array <NUM> is disposed on the first PCB end of the plurality of PCBs <NUM> and is arranged orthogonally with respect to the PCB mounting surface <NUM>. The radiating antenna array <NUM> includes a plurality of individual radiator substrates <NUM> arranged side-by-side along the X-axis. In one or more embodiments, the radiator substrates <NUM> can be fabricated as a printed circuit board (PCB) that includes various circuits, traces, and/or electrical component.

Each radiator substrate <NUM> is disposed on the first end of a respective PCB <NUM>, and extends along the first axis (e.g., the X-axis) to define a substrate width (Ws), a second axis (e.g., a Y-axis) orthogonal to the first axis to define a substrate height (Hs), and a third axis (e.g., a Z-axis) orthogonal to the X-axis and the Y-axis to define a substrate length (Ls). The radiator substrates <NUM> can be formed from various materials that provide a dielectric constant (k) ranging, for example, from about <NUM> to about <NUM>, a dielectric loss tangent (tan δ) ranging, for example, from about. <NUM> to about. <NUM>, a coefficient of thermal expansion (CTE) ranging, for example, from about 10ppm/°C to about 220ppm/°C. In one or more embodiments, the radiator substrates <NUM> can be fabricated as a printed circuit board (PCB) that includes various circuits, traces, and/or electrical components.

Each radiator substrate <NUM> has a patch mounting surface <NUM> and an opposing contact surface <NUM> that extend along the X-axis from a first substrate end to an opposing second substrate end and the Z-axis from a third substrate end to an opposing fourth substrate end. Accordingly, the contact surface <NUM> is disposed directly against the first end of a respective PCB <NUM> such that the patch mounting surface <NUM> is arranged orthogonally with respect to the PCB mounting surface <NUM>. In one or more non-limiting embodiments, the first and second ends of the radiator substrates <NUM> directly contact one another.

Each radiator substrate <NUM> includes a plurality of radiating antenna elements <NUM> disposed on the patch mounting surface <NUM> and arranged side-by-side along the Z-axis. Although the radiating antenna elements <NUM> are described as patch antennas <NUM> going forward, other types of radiating antenna elements <NUM> can be implemented without departing from the scope of the invention.

Referring to <FIG>, a PCB <NUM> and a radiator substrate <NUM> included in the dual-polarized PCB array antenna <NUM> are illustrated in greater detail. The PCB <NUM> is illustrated with trace clusters <NUM> that include a plurality of electrically conductive traces <NUM> formed on the PCB mounting surface <NUM>. The traces <NUM> include an electrically conductive material (e.g., copper) and can be formed on the PCB mounting surface <NUM> using various fabrication processes such as, for example, printed circuit board (PCB) etching processes, additive manufacturing, (e.g., three-dimensional printing), etc. Although five traces <NUM> are shown, it should be appreciated that the trace clusters <NUM> can include more or less traces <NUM> without departing from the scope of the invention.

Still referring to <FIG> with additional reference to <FIG> and <FIG>, the radiator substrate <NUM> has a plurality of through-hole clusters <NUM> arranged side-by-side along the Z-axis (see <FIG>). Each through-hole cluster <NUM> is interposed between a given patch antenna <NUM> and the first end <NUM> of the patch mounting surface <NUM>. Each through-hole cluster <NUM> includes a plurality of through-holes <NUM> formed in the radiator substrate <NUM> and extending completely there through from the patch mounting surface <NUM> to the contact surface <NUM>. Each through-hole <NUM> is aligned with a respective trace <NUM> along the Y-axis (shown e.g., in <FIG>).

The through-holes <NUM> are configured to receive electrically conductive pins <NUM> to provide a plurality of pin clusters <NUM>, which are arranged side-by-side along the Z-axis. The pins <NUM> are formed from an electrically conductive material such as copper, for example, so as to serve as terminals. Each electrically conductive pin <NUM> extends from a mounting end <NUM> to an opposing contact end <NUM> and is disposed in a respective through-hole <NUM> (see <FIG>). Accordingly, the mounting end <NUM> abuts against the patch mounting surface <NUM> and the contact end <NUM> contacts an aligned trace <NUM> as shown in <FIG>. In one or more non-limiting embodiments, the radiator substrate <NUM> can include one or more substrate traces (not shown) connecting a given patch antenna <NUM> to the pins <NUM> included in an adjacent pin cluster <NUM>. In this manner, signals (e.g., RF signals) applied to the traces <NUM> of a given trace cluster <NUM> on the PCB <NUM> can be deliver to the patch antenna <NUM> on the radiator substrate <NUM> via the respectively aligned pins <NUM>. Although five pins <NUM> are shown, more or less pins <NUM> can be included based on the number of traces <NUM> formed on the PCB mounting surface <NUM>.

Referring again to <FIG>, the assembly of the PCB <NUM>, the traces <NUM>, the radiator substrate <NUM>, and the pins <NUM> establishes an orthogonal PCB interface <NUM>. As described herein, the orthogonal PCB interface <NUM> arranges the patch mounting surface <NUM> of the radiator substrate <NUM> in an orthogonal position with respect to the PCB mounting surface <NUM> of the PCB <NUM>. This orthogonal arrangement allows for integrating dual-polarized patch antennas or stacked patch radiators with the PCBs <NUM> to enable a dual-polarized PCB array antenna <NUM>. In addition, the electrical connection established by the traces <NUM> and the pins <NUM> can facilitate a shielded channel interface between the PCB <NUM> and the patch antennas <NUM> as described in greater detail below.

The connection between the pins <NUM> and the traces <NUM> also facilitates dual-polarization RF signal transmission and/or reception without the need to implement large, bulky right-angle connectors. <FIG> illustrate one example of establishing the pin/trace connection. The pins <NUM> can be aligned above the traces <NUM> using, for example a pick-and-place device as understood by those of ordinary skill in the art. Once aligned, the radiator substrate <NUM> can be placed (as indicated by the dashed arrow) against the PCB <NUM> such that the contact surface <NUM> abuts against the first end <NUM> of the PCB <NUM> and the pins <NUM> contact the traces <NUM> (see <FIG>). An electrically conductive filler <NUM> such as solder, for example, can then be deposited on the PCB mounting surface <NUM> so as to form an electrically conductive node between the contact end <NUM> of the pins <NUM> and the traces <NUM> (see <FIG>). Although the electrically conductive filler <NUM> is shown as covering a portion of the pin contact end <NUM>, it should be appreciated that the electrically conductive filler <NUM> can be deposited to cover the entire contact end <NUM>.

Turning to <FIG>, a shielded channel interface <NUM> is provided by a dual-polarized PCB array antenna <NUM> is illustrated according to a non-limiting embodiment. As described herein, the dual-polarized PCB array antenna <NUM> includes a one or more PCBs <NUM> arranged orthogonally with respect to a radiator substrates <NUM> via an orthogonal PCB interface <NUM>. Although a single PCB <NUM> and a single radiator substrate <NUM> are illustrated, it should be appreciated that additional PCBs <NUM> and additional substrates <NUM> can be implemented without departing from the scope of the invention.

According to a non-limiting embodiment shown in <FIG>, the PCB <NUM> includes a first plurality of electrically conductive elements 111a, 111b and 111c. In one or more non-limiting embodiments, the first plurality of electrically conductive elements include a first electrically conductive trace 111a, a second electrically conductive trace 111b, and a third electrically conductive trace 111c. In at least one non-limiting embodiment, one or more of the electrically conductive traces 111a-111c are formed on the PCB mounting surface <NUM> and extend from the first PCB end to the second PCB end. The first trace 111a can be connected to a first port <NUM>, the trace 111b can be connected to a second port <NUM>, and the third electrically conductive trace 111c can be connected to a ground plane using a via (not shown) embedded in the PCB <NUM>. Although the first and second ports <NUM> and <NUM> is shown located at the second PCB end, the locations of the first and second ports <NUM> and <NUM> are not limited thereto and may be implemented at different locations.

The radiator substrate <NUM> includes a second plurality of electrically conductive elements 122a, 122b, 122c, 122d, and 122e (collectively referred to as 122a-122e). In at least one non-limiting embodiment, the electrically conductive elements 122a-122e can be formed as electrically conductive pins as described herein, which serve as a plurality of terminals to facilitate the shielded channel interface <NUM> In at least one non-limiting embodiment, the electrically conductive elements 122a-122e extend perpendicular with respect to the patch mounting surface <NUM> of the radiator substrate <NUM>. Accordingly, a second electrically conductive element (e.g., a pin 122a-122e) can contact a respective first electrically conductive element (e.g., a trace 111a-111c).

As shown in <FIG>, for example, terminal 122b can be connected to the first trace 111a while terminal 122d can be connected to the second trace 111b. Terminals 122a, 122c and 122e can be connected to vias (not shown), which are embedded in the PCB <NUM>, and are shorted to a ground plane. Accordingly, a ground-signal-ground-signal-ground (GSGSG) shielded channel interface <NUM> is established that allows for maintaining ground potentials between both the PCB <NUM> and the radiator substrate <NUM> throughout the system while RF signals are applied to terminals 122b and 122d and delivered to the first and second terminals 111a and 111b, respectively. It should be appreciated that the terminals 122a-122e are not limited to a GSGSG configuration, and that other terminal configurations capable of establishing a shielded channel interface <NUM> can be employed without departing from the scope of the present disclosure.

According to a non-limiting embodiment shown in <FIG>, a shielded channel interface <NUM> can be established by utilizing the inner terminals 122b, 122c and 122d without utilizing the outer-most terminals 122a and 122e. In this example, terminal 122c can serve as a ground terminal that is interposed (i.e., sandwiched) between first and second RF terminals 122b and 122d. Accordingly, an RF signal-ground-signal (SGS) shielded channel interface <NUM> is established that facilitates a signal interface between the PCB <NUM> and the radiator substrate <NUM>. Although a SGS shielded channel interface <NUM> is described, the configuration is not limited thereto. For example, a ground-signal-ground (GSG) shielded channel interface <NUM> can be established without departing from the scope of the present disclosure by utilizing terminal 122c as an RF terminal that is interposed (i.e., sandwiched) between first and second ground terminals 122b and 122d.

As described herein, various non-limiting embodiments provide an orthogonal interface for implementation in a dual-polarized PCB array antenna. The orthogonal interface overcomes the need to implement twin PCBs, while facilitating efficient dual-polarization via dual-polarized patch and stacked patch radiators integrated on one or more PCBs.

The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claim 1:
A dual-polarized printed circuit board, PCB, array antenna (<NUM>) comprising:
a plurality of PCBs (<NUM>), each PCB extending along a first axis to define a PCB width (Wst), a second axis orthogonal to the first axis to define a PCB height (Hst), and a third axis orthogonal to the first axis and the second axis to define a PCB length (Lst), each PCB having a PCB mounting surface (<NUM>) that extends along the second axis from a first PCB end to an opposing second PCB end and along the third axis from a third PCB end to a fourth PCB end,
a radiating antenna array (<NUM>) including a plurality of radiator substrates (<NUM>), each radiator substrate having a patch mounting surface (<NUM>) that extends along the first axis from a first radiator substrate end to an opposing second radiator substrate end and the third axis from a third radiator substrate end to an opposing fourth radiator substrate end; and
a plurality of orthogonal interfaces configured to arrange the patch mounting surface of a given radiator substrate among the plurality of radiator substrates in an orthogonal position with respect to the PCB mounting surface of a given PCB among the plurality of PCBs
wherein the radiating antenna array includes a plurality of radiating antenna elements (<NUM>) disposed on the patch mounting surface, wherein each radiator substrate is disposed on the first PCB end of a respective PCB, wherein a given orthogonal interface among the plurality of orthogonal interfaces arranges the patch mounting surface of a given radiator substrate in an orthogonal position with respect to the PCB mounting surface of a given PCB,
and wherein the given orthogonal interface comprises:
a plurality of electrically conductive traces (<NUM>) formed on the given PCB mounting surface; and characterized in that the given orthogonal interface further comprises
a plurality of electrically conductive pins (<NUM>) extending through the patch mounting surface and contacting the electrically conductive traces (111a-111c).