Patent Description:
A clock signal is usually used in electronic devices as shown e.g. in documents <CIT>, <CIT> and <CIT>. The clock signal is generally used in synchronization circuits as a timer, ensuring relevant electronic components operate synchronously. In some application scenarios, a frequency of the clock signal is required to be detected. In general, a more complex circuit needs to be designed for a specific value of the frequency of the clock signal being accurately detected.

However, in other application scenarios, it is enough to detect a change of the frequency of the clock signal is enough, and the specific value of the frequency is not required to be detected.

The invention is defined by the appended claims and relates to a frequency-detecting circuit, a DCC, and an electronic device.

To solve the above technical problem, the present disclosure provides a frequency-detecting circuit, including a control-signal generating circuit, configured to receive a to-be-detected clock signal and generate a first control signal corresponding to the to-be-detected clock signal and a second control signal delayed relative to the first control signal; a charging and discharging path, coupled to the control-signal generating circuit, and performing a charging process or a discharging process under control of the second control signal, wherein during a period with a pulse width when the second control signal is at a high level, the charging and discharging path performs the discharging process, and the charging and discharging path performs the charging process during another period when the second control signal is at a low level; and a control-voltage generating circuit, coupled to an output terminal of the charging and discharging path and the control-signal generating circuit, and configured to sample values of a voltage (ND1) of the output terminal of the charging and discharging path before the discharging process during a period with a pulse width when the first control signal is at the high level, to output a corresponding first voltage signal; wherein a voltage value of the first voltage signal (V<NUM>) is related to a frequency of the to-be-detected clock signal (CKin).

To solve the above technical problem, the present disclosure provides a DCC. The DCC includes a filtering circuit, an input terminal of the filtering circuit being configured to input a first clock signal; a DC bias amplifying circuit, an input terminal of the DC bias amplifying circuit being coupled to an output terminal of the filtering circuit, and an output terminal of the DC bias amplifying circuit being configured to output a second clock signal; and an attenuation adjusting circuit, an input terminal of the attenuation adjusting circuit being coupled to the input terminal of the filtering circuit, and an output terminal of the attenuation adjusting circuit being coupled to the input terminal of the DC bias amplifying circuit; the attenuation adjusting circuit includes a frequency-detecting circuit above; the first clock signal is as the to-be-detected clock signal, the attenuation adjusting circuit performs an attenuation adjusting process for a signal output by the filtering circuit based on the frequency of the first clock signal.

To solve the above technical problem, the present disclosure provides an electronic device, and the electronic device includes the frequency-detecting circuit described above.

The present disclosure may achieve the following benefits. Different from prior arts, the frequency-detecting circuit provided in some embodiments of the present disclosure includes a control-signal generating circuit, a charging and discharging path, and a control-voltage generating circuit. The control-signal generating circuit is configured to receive a to-be-detected clock signal and generate a first control signal corresponding to the to-be-detected clock signal and a second control signal delayed relative to the first control signal; the charging and discharging path is coupled to the control-signal generating circuit, and performing a charging process or a discharging process under control of the second control signal, during a period with a pulse width when the second control signal is at a high level, the charging and discharging path performs the discharging process, and the charging and discharging path performs the charging process during another period when the second control signal is at a low level; and the control-voltage generating circuit is coupled to an output terminal of the charging and discharging path and the control-signal generating circuit, and configured to sample values of a voltage of an output terminal of the charging and discharging path before the discharging process during a period with a pulse width when the first control signal is at the high level, to output a corresponding first voltage signal. In these embodiments, a corresponding voltage signal is generated based on the frequency of the clock signal, so as to correspondingly determine a magnitude of the frequency of the clock signal through detecting a voltage value of the voltage signal. Further, in some scenarios where an accurate frequency of the clock signal is not required to be acquired and only the magnitude of the frequency needs to be determined, the magnitude of the frequency of the clock signal may be directly reflected through determining a magnitude of a voltage value of a generated voltage signal. In addition, the voltage signal may be directly configured as an input of a subsequent circuit to indicate the frequency of the clock signal.

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, a brief description of the accompanying drawings to be used in the description of the embodiments will be given below. It will be obvious that the accompanying drawings in the following description are only some embodiments of the present disclosure, and that other accompanying drawings may be obtained on the basis of these drawings without any creative effort for those skilled in the art.

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of the present disclosure.

As shown in <FIG> is a structural schematic view of a frequency-detecting circuit according to a first embodiment of the present disclosure. The frequency-detecting circuit <NUM> includes a control-signal generating circuit <NUM>, a charging and discharging path <NUM>, and a control-voltage generating circuit <NUM>.

The control-signal generating circuit <NUM> is configured to receive a to-be-detected clock signal CKin and generate a first control signal CKP corresponding to the to-be-detected clock signal CKin and a second control signal CKPD delayed relative to the first control signal CKP.

The charging and discharging path <NUM> is coupled to the control-signal generating circuit <NUM>, and performs a charging process or a discharging process under control of the second control signal CKPD. During a period with a pulse width when the second control signal CKPD is at a high level, the charging and discharging path <NUM> performs the discharging process, and the charging and discharging path <NUM> performs the charging process during another period when the second control signal CKPD is at a low level.

The control-voltage generating circuit <NUM> is coupled to an output terminal of the charging and discharging path <NUM> and the control-signal generating circuit <NUM>, and configured to sample values of a voltage signal ND1 of an output terminal of the charging and discharging path <NUM> before the discharging process during a period with a pulse width when the first control signal CKP is at the high level, to output a first voltage signal V<NUM>.

In some embodiments, the less the frequency of the to-be-detected clock signal CKin is, the greater the voltage value of the first voltage signal V<NUM> is.

In some embodiments, a frequency of the second control signal CKPD is the same as the frequency of the to-be-detected clock signal CKin, and the pulse width during which the second control signal CKPD is at the high level remains unchanged. Therefore, a discharging period of the charging and discharging path <NUM> in a clock cycle of the second control signal CKPD is fixed, and a charging period of the charging and discharging path <NUM> is determined by a length of the second control signal CKPD being at the low level, therefore, the charging period of the charging and discharging path <NUM> is determined by a cycle length of the second control signal CKPD. The less the frequency of the second control signal CKPD is, the greater the cycle length is, and the longer the charging period of the charging and discharging path <NUM> is, the greater a voltage value of the voltage signal ND1 of the output terminal of the charging and discharging path <NUM> is. Therefore, the voltage value of the voltage signal ND1 of the output terminal of the charging and discharging path <NUM> may reflect a magnitude of the frequency of the to-be-detected clock signal CKin. Since the voltage signal ND1 of the output terminal of the charging and discharging path <NUM> has a saw tooth shape as the charging and discharging path <NUM> being periodically charged and discharged, the control-voltage generating circuit <NUM> further samples the voltage signal ND1 during the period with the pulse width when the first control signal CKP is at the high level and outputs a sampled voltage signal as the first voltage signal V<NUM>. Since a high-level pulse of the first control signal CKP is earlier than a high-level pulse of the second control signal CKPD, a sampling time point being before the discharging process of each cycle of the charging and discharging path <NUM> may be guaranteed. The sampled voltage signal reflects a voltage value reached in each charging process, and is output as the first voltage signal V<NUM>. Therefore, a magnitude of the first voltage signal V<NUM> reflects a magnitude of the cycle length (i.e., the frequency) of the second control signal CKPD, i.e., the first voltage signal V<NUM> reflects the frequency of the to-be-detected clock signal CKin.

Different from the prior arts, the frequency-detecting circuit provided in this embodiment of the present disclosure includes the control-signal generating circuit, the charging and discharging path, and the control-voltage generating circuit. The control-signal generating circuit is configured to receive the to-be-detected clock signal and generate the first control signal corresponding to the to-be-detected clock signal and the second control signal delayed relative to the first control signal; the charging and discharging path is coupled to the control-signal generating circuit, and performing the charging process or a discharging process under the control of the second control signal, during the period with the pulse width when the second control signal is at the high level, the charging and discharging path performs the discharging process, and the charging and discharging path performs the charging process during another period when the second control signal is at the low level; and the control-voltage generating circuit is coupled to the output terminal of the charging and discharging path and the control-signal generating circuit, and configured to sample values of the voltage of the output terminal of the charging and discharging path before the discharging process during the period with the pulse width when the first control signal is at the high level, to output the corresponding first voltage signal. In this way, the corresponding voltage signal is generated based on the frequency of the clock signal, so as to correspondingly determine the magnitude of the frequency of the clock signal through detecting the voltage value of the voltage signal. Further, in some scenarios where the accurate frequency of the clock signal is not required to be acquired and only the magnitude of the frequency needs to be determined, the magnitude of the frequency of the clock signal may be directly reflected through determining the magnitude of the voltage value of the generated voltage signal. In addition, the voltage signal may be directly configured as the input of the subsequent circuit to indicate the frequency of the clock signal.

As shown in <FIG> is a structural schematic view of the frequency-detecting circuit according to a second embodiment of the present disclosure. The frequency-detecting circuit <NUM> includes the control-signal generating circuit <NUM>, the charging and discharging path <NUM>, and the control-voltage generating circuit <NUM>.

The control-signal generating circuit <NUM> is configured to receive the to-be-detected clock signal CKin and generate the first control signal CKP corresponding to the to-be-detected clock signal CKin and the second control signal CKPD delayed relative to the first control signal CKP.

The charging and discharging path <NUM> is coupled to the control-signal generating circuit <NUM>, and performs the charging process or the discharging process under the control of the second control signal CKPD. During the period with the pulse width when the second control signal CKPD is at the high level, the charging and discharging path <NUM> performs the discharging process, and the charging and discharging path <NUM> performs the charging process during another period when the second control signal CKPD is at the low level.

The control-voltage generating circuit <NUM> is coupled to the output terminal of the charging and discharging path <NUM> and the control-signal generating circuit <NUM>, and configured to sample values of the voltage signal ND1 of the output terminal of the charging and discharging path <NUM> before the discharging process during the period with the pulse width when the first control signal CKP is at the high level, to output the first voltage signal V<NUM>. The less the frequency of the to-be-detected clock signal CKin is, the greater the voltage value of the first voltage signal V<NUM> is.

Specifically, in this embodiment, the charging and discharging path <NUM> further includes a power supply A, a first switch S<NUM> and a first capacitor C<NUM>. A first terminal of the first capacitor C<NUM> is coupled to the power supply A, and a second terminal of the first capacitor C<NUM> is grounded. A first terminal of the first switch S<NUM> is coupled to the first terminal of the first capacitor C<NUM>, a second terminal of the first switch S<NUM> is grounded, and a control terminal of the first switch S<NUM> inputs the second control signal CKPD. The control-voltage generating circuit <NUM> further includes a second switch S<NUM> and a second capacitor C<NUM>. A first terminal of the second switch S<NUM> is coupled to the first terminal of the first capacitor C<NUM> (i.e., the output terminal ND1 of the charging and discharging path <NUM>), and a control terminal of the second switch S<NUM> inputs the first control signal CKP. A first terminal of the second capacitor C<NUM> is coupled to a second terminal of the second switch S<NUM> and configured to output the first voltage signal V<NUM>, and a second terminal of the second capacitor C<NUM> is grounded.

An operating principle of circuits of this embodiment will be described in the following with reference to <FIG> is a schematic view of a waveform of a signal at each node according to the second embodiment of the present disclosure. In this embodiment, the first switch S<NUM> and the second switch S<NUM> are turned on when control terminals thereof are at a logic high level "<NUM>", and turned off when the control terminals thereof are at a logic low level "<NUM>".

When the first control signal CKP is the logic high level "<NUM>" and the second control signal CKPD is the logic low level "<NUM>", the second switch S<NUM> is turned on, the first switch S<NUM> is turned off, and the power supply A charges for the first capacitor C<NUM> and the second capacitor C<NUM>, a voltage of a first node signal ND<NUM> is increased, and the first voltage signal V<NUM> is increased. When the first control signal CKP is the logic high level "<NUM>" and the second control signal CKPD is the logic low level "<NUM>", the power supply A continues to charge for the first capacitor C<NUM>. It can be seen that a charging period of the first capacitor C<NUM> is determined by a length of a period when the second control signal CKPD is the logic low level "<NUM>". Since a pulse width when the first control signal CKP is the logic high level "<NUM>" and a pulse width when the second control signal CKPD is the logic high level "<NUM>" are fixed (a method for fixing the pulse width will be described in the following). A length of a period when the first control signal CKP is the logic low level "<NUM>" is determined by the cycle length of the first control signal CKP. The length of the period when the second control signal CKPD is the logic low level "<NUM>" is determined by the cycle length of the second control signal CKPD. Since both the first control signal CKP and the second control signal CKPD are generated by processing the to-be-detected clock signal CKin, both the first control signal CKP and the second control signal CKPD have the same cycle with the to-be-detected clock signal CKin Therefore, a period of the power supply A charging for the first capacitor C<NUM> is determined by the cycle (or frequency) of the to-be-detected clock signal CKin. The less the frequency of the to-be-detected clock signal CKin is, the greater the cycle is, the greater the period of the power supply A charging for the first capacitor C<NUM> is. When the first control signal CKP is the logic low level "<NUM>" and the second control signal CKPD is the logic high level "<NUM>", the second switch S<NUM> is turned off, the first switch S<NUM> is turned on, the first capacitor C<NUM> is discharged, and the second capacitor C<NUM> is maintained. The voltage of the first node signal ND<NUM> is decreased, and the first voltage signal V<NUM> is maintained. After multiple clock cycles, the first capacitor C<NUM> is charged and discharged cyclically, the voltage of the first node signal ND<NUM> has the saw tooth shape. The second capacitor C<NUM> is charged multiple times, and the first voltage signal V<NUM> is increased through a charge share between the first capacitor C<NUM> and the second capacitor C<NUM>. Under a condition that the frequency of the to-be-detected clock signal CKin is stable, a stable voltage value is finally reached. The stable voltage value may reflect a value reached in each charging cycle of the first node signal ND<NUM>, that is, the stable voltage value may reflect the magnitude of the cycle length of the second control signal CKPD, i.e., the magnitude of the frequency of the to-be-detected clock signal CKin.

As shown in <FIG> is a structural schematic view of the frequency-detecting circuit according to a third embodiment of the present disclosure. The frequency-detecting circuit <NUM> includes the control-signal generating circuit <NUM>, the charging and discharging path <NUM>, and the control-voltage generating circuit <NUM>.

Specifically, in this embodiment, the charging and discharging path <NUM> further includes a power supply A, a first switch S<NUM> and a first capacitor C<NUM>. A first terminal of the first capacitor C<NUM> is coupled to the power supply, and a second terminal of the first capacitor C<NUM> is grounded. A first terminal of the first switch S<NUM> is coupled to the first terminal of the first capacitor C<NUM>, a second terminal of the first switch S<NUM> is grounded, and a control terminal of the first switch S<NUM> inputs the second control signal CKPD. The control-voltage generating circuit <NUM> further includes a second switch S<NUM> and a second capacitor C<NUM>, a third switch S<NUM> and a third capacitor C<NUM>. The first terminal of the second switch S<NUM> is coupled to the first terminal of the first capacitor C<NUM> (i.e., the output terminal of the charging and discharging path <NUM>), and the control terminal of the second switch S<NUM> inputs the first control signal CKP. The first terminal of the second capacitor C<NUM> is coupled to the second terminal of the second switch S<NUM>, and the second terminal of the second capacitor C<NUM> is grounded. A first terminal of the third switch S<NUM> is coupled to the first terminal of the second capacitor C<NUM>, and a control terminal of the third switch inputs the second control signal CKPD. A first terminal of the third capacitor C<NUM> is coupled to a second terminal of the third switch S<NUM> and configured to output the first voltage signal V<NUM>, and a second terminal of the third capacitor C<NUM> is grounded.

Different from the second embodiments, in this embodiment, a third switch S<NUM> and a third capacitor C<NUM> are further added, and the first terminal of the third capacitor C<NUM> is configured as the output terminal of the first voltage signal V<NUM>.

The operating principle of the circuits of this embodiment will be described in the following with reference to <FIG> is a schematic view of the waveform of the signal at each node according to the third embodiment of the present disclosure. In this embodiment, the first switch S<NUM>, the second switch S<NUM>, and the third switch S<NUM> are turned on when control terminals thereof are at the logic high level "<NUM>", and turned off when the control terminals thereof are at the logic low level "<NUM>".

When the first control signal CKP is the logic high level "<NUM>" and the second control signal CKPD is the logic low level "<NUM>", the second switch S<NUM> is turned on, the first switch S<NUM> and the third switch S<NUM> are turned off, and the power supply A charges for the first capacitor C<NUM> and the second capacitor C<NUM>, the voltage of the first node signal ND<NUM> and a voltage of a second node signal ND<NUM> are increased. When the first control signal CKP is the logic high level "<NUM>" and the second control signal CKPD is the logic low level "<NUM>", the power supply A continues to charge for the first capacitor C<NUM>. It can be seen that the charging period of the first capacitor C<NUM> is determined by the length of the period when the second control signal CKPD is the logic low level "<NUM>". Since the pulse width when the first control signal CKP is the logic high level "<NUM>" and the pulse width when the second control signal CKPD is the logic high level "<NUM>" are fixed (the method for fixing the pulse width will be described in the following). The length of the period when the first control signal CKP is the logic low level "<NUM>" is determined by the cycle length of the first control signal CKP. The length of the period when the second control signal CKPD is the logic low level "<NUM>" is determined by the cycle length of the second control signal CKPD. Since both the first control signal CKP and the second control signal CKPD are generated by processing the to-be-detected clock signal CKin, both the first control signal CKP and the second control signal CKPD have the same cycle with the to-be-detected clock signal CKin. Therefore, the period of the power supply A charging for the first capacitor C<NUM> is determined by the cycle (or frequency) of the to-be-detected clock signal CKin. The less the frequency of the to-be-detected clock signal CKin is, the greater the cycle is, the greater the period of the power supply A charging for the first capacitor C<NUM> is. When the first control signal CKP is the logic low level "<NUM>" and the second control signal CKPD is the logic high level "<NUM>", the second switch S<NUM> is turned off, the first switch S<NUM> and the third switch S<NUM> are turned on, the first capacitor C<NUM> is discharged, the second capacitor C<NUM> is maintained, and the third capacitor C<NUM> is charged. The voltage of the first node signal ND<NUM> is decreased, the voltage of the second node signal ND<NUM> is maintained, and the first voltage signal V<NUM> is increased. After the multiple clock cycles, the first capacitor C<NUM> is charged and discharged cyclically, the voltage of the first node signal ND<NUM> has the saw tooth shape. The second capacitor C<NUM> is charged multiple times, and the voltage of the second node signal ND<NUM> is increased through the charge share between the first capacitor C<NUM> and the second capacitor C<NUM>. The third capacitor C<NUM> is charged multiple times, the first voltage signal V<NUM> is increased through a charge share between the third capacitor C<NUM> and the second capacitor C<NUM>, and finally reached a stable voltage value (Under the condition that the frequency of the to-be-detected clock signal CKin is stable). The stable voltage value may reflect the value reached in each charging cycle of the first node signal ND<NUM>, that is, the stable voltage value may reflect the magnitude of the cycle length of the second control signal CKPD, i.e., the magnitude of the frequency of the to-be-detected clock signal CKin. However, different from the second embodiment, since the second node signal ND<NUM> is still in the saw tooth shape although the second node signal ND<NUM> is continuously increased, a quality of an output voltage may be affected. Therefore, the third capacitor C<NUM> is added on the basis of the second embodiment. It can be seen from <FIG> that a voltage effect of the first voltage signal V<NUM> is better than that of the second node signal ND<NUM>.

As shown in <FIG> is a structural schematic view of the frequency-detecting circuit according to a fourth embodiment of the present disclosure. The frequency-detecting circuit <NUM> includes the control-signal generating circuit <NUM>, the charging and discharging path <NUM>, and the control-voltage generating circuit <NUM>.

In some embodiments, the control-signal generating circuit <NUM> may include a first AND gate unit A<NUM>, a first delay unit D<NUM>, a first inversion unit N<NUM> (non-gate unit), a second AND gate unit A<NUM>, and a second delay unit D<NUM>. A first terminal of the first AND gate unit A<NUM> inputs the to-be-detected clock signal CKin, and a second terminal of the first AND gate unit A<NUM> inputs an enable signal EN (being the logic high level "<NUM>" during operating). An input terminal of the first delay unit D<NUM> is coupled to an output terminal of the first AND gate unit A<NUM> (In some embodiments, the control-signal generating circuit <NUM> may not include the first AND gate unit A<NUM>, and the input terminal of the first delay unit D<NUM> is directly connected to the to-be-detected clock signal CKin). An input terminal of the first inversion unit N<NUM> is coupled to the output terminal of the first delay unit D<NUM>. A first input terminal of the second AND gate unit A<NUM> is coupled to the input terminal of first delay unit D<NUM>, a second input terminal of the second AND gate unit A<NUM> is coupled to an output terminal of the first inversion unit N<NUM>, and an output terminal of the second AND gate unit A<NUM> outputs the first control signal CKP. An input terminal of the second delay unit D<NUM> is coupled to the output terminal of the second AND gate unit, and an output terminal of the second delay unit D<NUM> outputs the second control signal CKPD.

Specifically, in this embodiment, the charging and discharging path <NUM> further includes the power supply A, the first switch S<NUM> and the first capacitor C<NUM>. The first terminal of the first capacitor C<NUM> is coupled to the power supply, and the second terminal of the first capacitor C<NUM> is grounded. The first terminal of the first switch S<NUM> is coupled to the first terminal of the first capacitor C<NUM>, the second terminal of the first switch S<NUM> is grounded, and the control terminal of the first switch S<NUM> inputs the second control signal CKPD. The control-voltage generating circuit <NUM> further includes the second switch S<NUM> and the second capacitor C<NUM>, the third switch S<NUM> and the third capacitor C<NUM>. The first terminal of the second switch S<NUM> is coupled to the first terminal of the first capacitor C<NUM> (i.e., the output terminal of the charging and discharging path <NUM>), and the control terminal of the second switch S<NUM> inputs the first control signal CKP. The first terminal of the second capacitor C<NUM> is coupled to the second terminal of the second switch S<NUM>, and the second terminal of the second capacitor C<NUM> is grounded. The first terminal of the third switch S<NUM> is coupled to the first terminal of the second capacitor C<NUM>, and the control terminal of the third switch inputting the second control signal CKPD. The first terminal of the third capacitor C<NUM> is coupled to the second terminal of the third switch S<NUM> and configured to output the first voltage signal V<NUM>, and the second terminal of the third capacitor C<NUM> is grounded.

In some embodiments, the first switch S<NUM>, the second switch S<NUM>, and the third switch S<NUM> are implemented by an nMOS transistor, or a transmission gate formed of an nMOS transistor and a pMOS transistor.

The operating principle of the circuits of this embodiment will be described in the following with reference to <FIG> is a schematic view of the waveforms of the signal according to the fourth embodiment of the present disclosure. In this embodiment, the first switch S<NUM>, the second switch S<NUM>, and the third switch S<NUM> are turned on when the control terminals thereof are at the logic high level "<NUM>", and turned off when the control terminals thereof are at the logic low level "<NUM>".

A reference clock signal CKref is obtained after the to-be-detected clock signal CKin is processed by the first delay unit D1 and the first inversion unit N<NUM>. The reference clock signal CKref is opposite to the to-be-detected clock signal CKin and has a certain delay relative to the to-be-detected clock signal CKin. A "AND" logic process may be performed for the to-be-detected clock signal CKin and the reference clock signal CKref, and the first control signal CKP may be obtained. In this way, both the cycle length of the first control signal CKP and the cycle length of the second control signal CKPD are the same with a cycle length of the to-be-detected clock signal CKin. The pulse width when the first control signal CKP is the logic high level "<NUM>" and the pulse width when the second control signal CKPD is the logic high level "<NUM>"are fixed, which both are determined the first delay unit D<NUM>.

When the first control signal CKP is the logic high level "<NUM>" and the second control signal CKPD is the logic low level "<NUM>", the second switch S<NUM> is turned on, the first switch S<NUM> and the third switch S<NUM> are turned off, and the power supply A charges for the first capacitor C<NUM> and the second capacitor C<NUM>, the voltage of the first node signal ND<NUM> and a voltage of a second node signal ND<NUM> are increased. When the first control signal CKP is the logic high level "<NUM>" and the second control signal CKPD is the logic low level "<NUM>", the power supply A continues to charge for the first capacitor C<NUM>. It can be seen that the charging period of the first capacitor C<NUM> is determined by the length of the period when the second control signal CKPD is the logic low level "<NUM>". Since the pulse width when the first control signal CKP is the logic high level "<NUM>" and the pulse width when the second control signal CKPD is the logic high level "<NUM>" are fixed. The length of the period when the first control signal CKP is the logic low level "<NUM>" is determined by the cycle length of the first control signal CKP. The length of the period when the second control signal CKPD is the logic low level "<NUM>" is determined by the cycle length of the second control signal CKPD. Since both the first control signal CKP and the second control signal CKPD are generated by processing the to-be-detected clock signal CKin, both the first control signal CKP and the second control signal CKPD have the same cycle with the to-be-detected clock signal CKin Therefore, the period of the power supply A charging for the first capacitor C<NUM> is determined by the cycle (or frequency) of the to-be-detected clock signal CKin. The less the frequency of the to-be-detected clock signal CKin is, the greater the cycle is, the greater the period of the power supply A charging for the first capacitor C<NUM> is. When the first control signal CKP is the logic low level "<NUM>" and the second control signal CKPD is the logic high level "<NUM>", the second switch S<NUM> is turned off, the first switch S<NUM> and the third switch S<NUM> are turned on, the first capacitor C<NUM> is discharged, the second capacitor C<NUM> is maintained, and the third capacitor C<NUM> is charged. The voltage of the first node signal ND<NUM> is decreased, the voltage of the second node signal ND<NUM> is maintained, and the first voltage signal V<NUM> is increased. After the multiple clock cycles, the first capacitor C<NUM> is charged and discharged cyclically, the voltage of the first node signal ND<NUM> has the saw tooth shape. The second capacitor C<NUM> is charged multiple times, and the voltage of the second node signal ND<NUM> is increased through the charge share between the first capacitor C<NUM> and the second capacitor C<NUM>. The third capacitor C<NUM> is charged multiple times, the first voltage signal V<NUM> is increased through the charge share between the third capacitor C<NUM> and the second capacitor C<NUM>, and finally reached the stable voltage value (Under the condition that the frequency of the to-be-detected clock signal CKin is stable). The stable voltage value may reflect the value reached in each charging cycle of the first node signal ND<NUM>, that is, the stable voltage value may reflect the magnitude of the cycle length of the second control signal CKPD, i.e., the magnitude of the frequency of the to-be-detected clock signal CKin. However, different from the second embodiment, since the second node signal ND<NUM> is still in the saw tooth shape although the second node signal ND<NUM> is continuously increased, a quality of an output voltage may be affected. Therefore, the third capacitor C<NUM> is added on the basis of the second embodiment. It can be seen from <FIG> that the voltage effect of the first voltage signal V<NUM> is better than that of the second node signal ND<NUM>.

As shown in <FIG> is a structural schematic view of the frequency-detecting circuit according to a fifth embodiment of the present disclosure. The frequency-detecting circuit <NUM> includes the control-signal generating circuit <NUM>, the charging and discharging path <NUM>, the control-voltage generating circuit <NUM>, a comparing circuit <NUM>, and a low-dropout linear regulator <NUM>.

In some embodiments, the control-signal generating circuit <NUM> is configured to receive the to-be-detected clock signal CKin and generate the first control signal CKP corresponding to the to-be-detected clock signal CKin and the second control signal CKPD delayed relative to the first control signal CKP. The charging and discharging path <NUM> is coupled to the control-signal generating circuit <NUM>, and performs the charging process or the discharging process under the control of the second control signal CKPD. During the period with the pulse width when the second control signal CKPD is at the high level, the charging and discharging path <NUM> performs the discharging process, and the charging and discharging path <NUM> performs the charging process during another period when the second control signal CKPD is at the low level. The control-voltage generating circuit <NUM> is coupled to the output terminal of the charging and discharging path <NUM> and the control-signal generating circuit <NUM>, and configured to sample values of the voltage signal ND1 of the output terminal of the charging and discharging path <NUM> before the discharging process during the period with the pulse width when the first control signal CKP is at the high level, to output the first voltage signal V<NUM>. The less the frequency of the to-be-detected clock signal CKin is, the greater the voltage value of the first voltage signal V<NUM> is.

In this embodiment, the comparing circuit <NUM> is coupled to the control-voltage generating circuit, and configured to compare the voltage value of the first voltage signal with a voltage value of at least one preset reference-voltage signal Vref, to obtain a corresponding comparing-result signal Vcomp. The low-dropout linear regulator <NUM> is coupled to an output terminal of the comparing circuit <NUM> and configured to generate a matched second voltage signal V<NUM> according to the comparing-result signal Vcomp.

In some embodiments, the frequency value of the to-be-detected clock signal CKin is negatively correlated with a voltage value of the first voltage signal V<NUM>. That is, the less the frequency value of the to-be-detected clock signal CKin, the greater the voltage value of the first voltage signal V<NUM>. The comparing circuit <NUM> may adopt a hysteresis comparator, a non-inverting input terminal of the hysteresis comparator inputs the reference voltage signal Vref, and an inverting input terminal of the hysteresis comparator inputs the first voltage signal V<NUM>. Adopting the hysteresis comparator may avoid a problem that the comparing circuit <NUM> flips back and forth due to a jitter of a frequency of the to-be-detected clock signal CKin. In other embodiments, the comparing circuit <NUM> may also be implemented by adopting comparators of other types.

Combining the embodiments in reference with <FIG>, the frequency-detecting circuit above may be applied to a delay-locked circuit. As shown in <FIG> is a structural schematic view of a delay-locked circuit according to an embodiment of the present disclosure. The delay-locked circuit <NUM> includes a delay circuit <NUM>, a phase-detecting circuit <NUM>, a controlling circuit <NUM>, and the frequency-detecting circuit <NUM> described in the above embodiments.

<FIG> is a structural schematic view of the delay circuit <NUM> according to an embodiment of the present disclosure. The delay circuit <NUM> includes a delay line. Each operation of adjusting of the delay circuit <NUM> is achieved by changing control signals D<NUM>, D<NUM>. Dn (only D<NUM> and D<NUM> are shown in <FIG> for a simplicity) to adjust the number of gate circuits accessed to the delay line, such that a total delay of a second clock signal CKout relative to a first clock signal CKin (i.e., the to-be-detected clock signal CKin) may be adjusted, and adjusting step by step until an edge of the first clock signal CKin may be aligned to an edge of the second clock signal CKout (i.e., locked). For example, at the beginning, the control signal D<NUM> is <NUM>, and the first clock signal CKin only passes through a first delay path formed by the two leftmost NOT-AND (NAND) gates (i.e., an NAND gate <NUM> and an NAND gate <NUM>) and is output as the second clock signal CKout. When the "locked" above cannot be achieved, the control signal D<NUM> is changed to be <NUM>, and the control signal D<NUM> is <NUM>. The first clock signal CKin passes through a second delay path formed by four NAND gates (i.e., the NAND gate <NUM>, the NAND gate <NUM>, an NAND gate <NUM>, and an NAND gate <NUM>) and is output as the second clock signal CKout. , and so on. Through changing the control signals step by step, the delay path may be changed until the total delay generated by the delay line allow the edge of the first clock signal CKin to be aligned to the edge of the first clock signal CKin (i.e., locked).

The structure of the delay circuit <NUM> in <FIG> is only an example, and the delay line may also be implemented by other gate circuits. It can be seen that an adjusting amount (i.e., a length of each operation) of the delay in each operation of the delay line is related to a delay generated by a single gate circuit. The delay of the single gate circuit is adjusted by adjusting a voltage of the power supply in the above embodiments described with reference to <FIG>.

In other embodiments, the frequency-detecting circuit <NUM> in <FIG> may not include the low-dropout linear regulator <NUM>. A delaying device may be added to each delay node of each delay path of the delay line, the delay device may be an MOS capacitor <NUM>,. , or an MOS capacitor n shown in <FIG> (only the MOS capacitor <NUM> and the MOS capacitor <NUM> are shown in <FIG> for the simplicity). The MOS capacitors are turned on or off in response to a logic level of the comparing result signal Vcomp, thereby adjusting the delay of each delay path of the delay line, i.e., the delay (i.e., the length of each operation) of the delay line in each operation of adjusting. Specifically, when the first clock signal CKin is less than a preset threshold, the comprising result signal Vcomp controls the MOS capacitor of each delay node to be turned on, such that both the delay of the first delay path and the delay of the second delay path are increased correspondingly, and thereby increasing the delay (i.e., the length of each operation) of the delay line in each operation of adjusting. When the first clock signal CKin is greater than a preset threshold, the comprising result signal Vcomp controls the MOS capacitor of each delay node to be turned off, such that both the delay of the first delay path and the delay of the second delay path are reduced correspondingly, and thereby reducing the delay (i.e., the length of each operation) of the delay line in each operation of adjusting. A principle of an MOS tube forming the capacitor is that a gate oxide layer between a gate and a channel is configured as an insulating medium, the gate is configured as an upper electrode plate, and three terminals (i.e., a source, a drain, and a substrate) are electrically connected together to form a lower electrode plate.

Combining the embodiments described in reference with <FIG>, the first voltage signal V<NUM> output by the frequency-detecting circuit above may be applied to multiple application scenarios requiring the frequency of the to-be-detected clock signal CKin changing. For example, the first voltage signal V<NUM> may be applied to a DCC. As shown in <FIG> is a structural schematic view of a DCC according to an embodiment of the present disclosure. The DCC <NUM> includes a filtering circuit <NUM>, a DC bias amplifying circuit <NUM>, and an attenuation adjusting circuit <NUM>.

In some embodiments, an input terminal of the filtering circuit <NUM> is configured to input a first clock signal CKin. An input terminal of the DC bias amplifying circuit <NUM> is coupled to an output terminal of the filtering circuit <NUM>, and an output terminal of the DC bias amplifying circuit <NUM> is configured to output a second clock signal CKout. An input terminal of the attenuation adjusting circuit <NUM> is coupled to the input terminal of the filtering circuit <NUM>, and an output terminal of the attenuation adjusting circuit <NUM> is coupled to the input terminal of the DC bias amplifying circuit <NUM>. The attenuation adjusting circuit <NUM> includes the frequency-detecting circuit described above, as shown in <FIG>. The first clock signal CKin is as the to-be-detected clock signal CKin in <FIG>. The attenuation adjusting circuit <NUM> performs an attenuation adjusting process for a signal output by the filtering circuit <NUM> based on a frequency of the first clock signal CKin. In an embodiment, the less the frequency of the first clock signal CKin is, the greater a corresponding attenuation amplitude is.

It can be understood that in some embodiments, the DCC does not include the attenuation adjusting circuit <NUM>. Components of the first clock signal CKin after being processed by the filtering circuit <NUM> also include a low-frequency component having a greater ratio and a greater signal amplitude. The low-frequency component having the greater ratio may have an influence on a DC bias point of the DC bias amplifying circuit <NUM> in a subsequent level, which may deteriorate a DCC correcting capability.

As shown in <FIG> is a schematic view of changes of duty cycles of a first clock signal and a second clock signal without an attenuation process. Different curves in <FIG> correspond to first clock signals CKin of different frequencies. It can be seen that the greater the frequency of the first clock signal CKin is, the closer to an ideal value <NUM>% the duty cycle of the second clock signal CKout obtained after a converting process is. On the contrary, the less the frequency of the first clock signal CKin is, the greater a difference between the duty cycle of the second clock signal CKout obtained after the converting process and the ideal value <NUM>% is, which is not expected.

Therefore, in this embodiment, the attenuation adjusting circuit <NUM> is added. The attenuation adjusting circuit <NUM> is configured to perform the attenuation adjusting process for the signal output by the filtering circuit <NUM> based on the frequency of the first clock signal CKin, and the less the frequency of the first clock signal CKin is, the greater the corresponding attenuation amplitude is. In this way, an amplitude of the low-frequency component of a signal input into the DC bias amplifying circuit <NUM> may be reduced, and the influence of the low-frequency component on the DC bias point of the DC bias amplifying circuit <NUM> in the subsequent level may be reduced. Further, since the greater the frequency of the first clock signal CKin is, the less the corresponding attenuation amplitude is, which will not cause much influence on an original circuit.

Comparing <FIG> with <FIG> is a schematic view of the changes of the duty cycles of the first clock signal and the second clock signal after the attenuation process. Different curves in <FIG> correspond to the first clock signals CKin of the different frequencies. Comparing <FIG> with <FIG>, the greater the frequency of the first clock signal CKin is, the closer to the ideal value <NUM>% the duty cycle of the second clock signal CKout obtained after the converting process is. However, when the frequency of the first clock signals CKin becomes less, the difference between the duty cycle of the second clock signal CKout obtained after the converting process and the ideal value <NUM>% is reduced relative to <FIG>, i.e., closer to the ideal value <NUM>% than <FIG>.

As shown in <FIG> is a structural schematic view of the DCC according to another embodiment of the present disclosure. The DCC includes the filtering circuit <NUM>, the DC bias amplifying circuit <NUM>, and the attenuation adjusting circuit <NUM>. The attenuation adjusting circuit <NUM> includes the frequency-detecting circuit <NUM> described in the above embodiments.

In some embodiments, the attenuation adjusting circuit <NUM> further includes an adjustable resistance device <NUM>. A first terminal of the adjustable resistance device <NUM> is coupled to the output terminal of the filtering circuit <NUM>, a second terminal of the adjustable resistance device <NUM> is coupled to the input terminal of the DC bias amplifying circuit <NUM>, and the greater an on-resistance of the adjustable resistance device <NUM>, the less a DC component of a signal Vout of the input terminal of the DC bias amplifying circuit <NUM>. An input terminal of the frequency-detecting circuit <NUM> is coupled to the input terminal of the filtering circuit <NUM>, and an output terminal of the frequency-detecting circuit <NUM> is coupled to a control terminal of the adjustable resistance device <NUM>. The first voltage signal V<NUM> is generated by the frequency-detecting circuit based on the frequency of the first clock signal CKin, the control terminal of the adjustable resistance device is configured to input the first voltage signal, and the on-resistance of the adjustable resistance device <NUM> changes in response to a voltage value of the first voltage signal V<NUM> changing.

In some embodiments, the frequency-detecting circuit <NUM> generates the corresponding first voltage signal V<NUM> based on a frequency of the first clock signal CKin, the on-resistance of the adjustable resistance device <NUM> changes in response to a voltage value of the first voltage signal V<NUM> changing.

In an embodiment, the less the frequency of the first clock signal CKin is, the greater the voltage value of the first voltage signal V<NUM> correspondingly generated by the frequency-detecting circuit <NUM> is, the greater the on-resistance of the adjustable resistance device <NUM> is, the greater an attenuating degree of a corresponding signal Vin output by the filtering circuit <NUM> is, that is, the less the generated low-frequency DC component of the signal Vout of the input terminal of the DC bias amplifying circuit <NUM> is. Specifically, since a relationship between the signal Vin output by the filtering circuit <NUM> and the signal Vout of the input terminal of the DC bias amplifying circuit <NUM> satisfies the following formula:
<MAT>.

Rin is the on-resistance of the adjustable resistance device <NUM>, and Rout is a total resistance of N numbers of resistors R<NUM> connected in series in the DC bias amplifying circuit <NUM> (as shown in the following description about <FIG> for details). The less the frequency of the first clock signal CKin is, the greater the voltage value of the first voltage signal V<NUM> is, the greater the on-resistance Rin of a changeable resistor is, and the less the signal Vout of the input terminal of the DC bias amplifying circuit <NUM> is, i.e., the greater the attenuating degree of a corresponding signal Vin output by the filtering circuit <NUM> is. In this way, the first clock signal CKin in a low frequency adjusting the duty cycle of the second clock signal CKout output by the DCC <NUM> may be achieved.

As shown in <FIG> is a structural schematic view of the DCC according to a yet embodiment of the present disclosure. The DCC <NUM> includes the filtering circuit <NUM>, the DC bias amplifying circuit <NUM>, and the attenuation adjusting circuit <NUM>. The attenuation adjusting circuit <NUM> includes the frequency-detecting circuit <NUM> described in the above embodiments.

In some embodiments, the attenuation adjusting circuit <NUM> further includes the adjustable resistance device <NUM>. The first terminal of the adjustable resistance device <NUM> is coupled to the output terminal of the filtering circuit <NUM>, the second terminal of the adjustable resistance device <NUM> is coupled to the input terminal of the DC bias amplifying circuit <NUM>, and the greater an on-resistance of the adjustable resistance device <NUM>, the less the DC component of the signal Vout of the input terminal of the DC bias amplifying circuit <NUM>. The input terminal of the frequency-detecting circuit <NUM> is coupled to the input terminal of the filtering circuit <NUM>, and the output terminal of the frequency-detecting circuit <NUM> is coupled to the control terminal of the adjustable resistance device <NUM>. The first voltage signal V<NUM> is generated by the frequency-detecting circuit based on the frequency of the first clock signal CKin, the control terminal of the adjustable resistance device is configured to input the first voltage signal, and the on-resistance of the adjustable resistance device <NUM> changes in response to the voltage value of the first voltage signal V<NUM> changing.

In this embodiment, the adjustable resistance device <NUM> is a transmission gate unit. The transmission gate unit includes an nMOS transistor and a pMOS transistor. A first terminal of the nMOS transistor is coupled to the output terminal of the filtering circuit <NUM>, a second terminal of the nMOS transistor is coupled to the input terminal of the DC bias amplifying circuit <NUM>, and a control terminal of the nMOS transistor is coupled to the output terminal of the frequency-detecting circuit <NUM>. A first terminal of the pMOS transistor is coupled to the output terminal of the filtering circuit <NUM>, a second terminal of the pMOS transistor is coupled to the input terminal of the DC bias amplifying circuit <NUM>, and a control terminal of the pMOS transistor is coupled to the output terminal of the frequency-detecting circuit <NUM>.

As shown in <FIG> is a diagram showing a relationship between an on-resistance and a control-terminal voltage of a transmission gate according to some embodiments of the present disclosure. It can be seen from <FIG> that when a control-terminal voltage of the transmission gate (i.e., a gate voltage of the nMOS transistor and a gate voltage of the pMOS transistor) is a threshold voltage V<NUM>, a resistance of the transmission gate is the greatest. When the control-terminal voltage is decreased or increased on the basis of V<NUM>, the resistance of the transmission gate gradually decreases. Therefore, in this embodiment, a changing range of the first voltage signal V<NUM> output by the frequency-detecting circuit <NUM> may be controlled to be between <NUM>-V<NUM>, such that the resistance of the transmission gate may increase with the first voltage signal V<NUM> increasing.

In an embodiment, the filtering circuit <NUM> includes a low-pass filtering circuit and a high-pass filtering circuit. An input terminal of the low-pass filtering circuit is configured to input the first clock signal CKin, an input terminal of the high-pass filtering circuit is coupled to an output terminal of the low-pass filtering circuit, and an output terminal of the high-pass filtering circuit is coupled to the input terminal of the DC bias amplifying circuit <NUM>.

Specifically, the low-pass filtering circuit is configured to filter the low-frequency component in the signal. The low-pass filtering circuit includes a first resistor R<NUM> and a fourth capacitor C<NUM>. A first terminal of the first resistor R<NUM> is configured to input the first clock signal CKin. A first terminal of the fourth capacitor C<NUM> is coupled to a second terminal of the first resistor R<NUM>, and a second terminal of the fourth capacitor C<NUM> is grounded.

Specifically, the high-pass filtering circuit is configured to filter a high-frequency component in the signal. The high-pass filtering circuit includes a fifth capacitor C<NUM> and a sixth capacitor C<NUM>. A first terminal of the fifth capacitor C<NUM> is coupled to the second terminal of the fourth capacitor C<NUM>, and a second terminal of the fifth capacitor C<NUM> is coupled to the input terminal of the DC bias amplifying circuit <NUM>. A first terminal of the sixth capacitor C<NUM> is coupled to the second terminal of the fifth capacitor C<NUM>, and a second terminal of the sixth capacitor C<NUM> is grounded.

In an embodiment, the DC bias amplifying circuit <NUM> includes an inverting unit group, a resistance unit group, and a capacitor group. The inverting unit group includes N numbers of inverting units N<NUM>, the N numbers of inverting units N<NUM> are connected in series in sequence, and an input terminal of the first inverting unit N<NUM> in the N numbers of inverting units N<NUM> is coupled to the output terminal of the filtering circuit <NUM>. An output terminal of the last inverting unit N<NUM> in the N numbers of inverting units N<NUM> is configured to output the second clock signal CKout. The resistance unit group includes N numbers of resistors R<NUM>, the N numbers of resistors R<NUM> are connected in series in sequence, and the resistance unit group and the inverting unit group are connected in parallel. The capacitor group includes N-<NUM> numbers of capacitors C<NUM>, a first terminal of each capacitor C<NUM> of the N-<NUM> numbers of capacitors C<NUM> is sequentially coupled between two adjacent resistors R<NUM> of the N numbers of resistors R<NUM>, and a second terminal of each capacitor C<NUM> of the N-<NUM> numbers of capacitors C<NUM> is grounded. N is an odd number greater than <NUM>.

The DCC <NUM> further includes a second inverting unit N<NUM>, an input terminal of the second inverting unit N<NUM> is coupled to the output terminal of the last inverting unit N<NUM> in the N inverting units N<NUM>, and an output terminal of the second inverting unit N<NUM> is configured to output the second clock signal CKout.

It can be understood that multiple inverting units are inversely shaped step by step, and multiple RC units (including R<NUM> and C<NUM>) provide the DC bias point.

In an embodiment, the DCC <NUM> further includes a first buffer unit H<NUM> and a second buffer unit H<NUM>, an input terminal of the first buffering unit H<NUM> is configured to input the first clock signal CKin, and an output terminal of the first buffering unit H<NUM> is coupled to the input terminal of the filtering circuit <NUM>. An input terminal of the second buffering unit H<NUM> is coupled to the output terminal of the DC bias amplifying circuit <NUM>, and an output terminal of the second buffering unit H<NUM> is configured to output the second clock signal CKout. Different from the prior art, the DCC provided in the embodiments of the present disclosure includes the filter circuit, the DC bias amplifying circuit, and then attenuation adjusting circuit. The input terminal of the filtering circuit is configured to input the first clock signal. The input terminal of the DC bias amplifying circuit is coupled to the output terminal of the filtering circuit, and the output terminal of the DC bias amplifying circuit is configured to output the second clock signal. The input terminal of the attenuation adjusting circuit is coupled to the input terminal of the filtering circuit, and the output terminal of the attenuation adjusting circuit is coupled to the input terminal of the DC bias amplifying circuit. The attenuation adjusting circuit includes the frequency-detecting circuit, and the first clock signal is as the to-be-detected clock signal. the attenuation adjusting circuit performs the attenuation adjusting process for the signal output by the filtering circuit based on the frequency of the first clock signal, and the less the frequency of the first clock signal is, the greater the corresponding attenuation amplitude is. Accordingly, when the frequency of the first clock signal input, the attenuation adjusting process is correspondingly performed for an output signal of the filtering circuit, such that an amplitude of a low-frequency DC component of the output signal of the filtering circuit may be attenuated. In this way, after the output signal is input into the subsequent DC bias amplifying circuit, an influence of the low-frequency DC component on the DC bias amplifying circuit may be reduced, which may improve a correcting capability of the duty cycle, such that when the frequency of the input first clock signal is less, the duty cycle of the second clock signal after the duty cycle is adjusted may be close to the ideal value, such as <NUM>%.

As shown in <FIG> is a structural schematic view of an electronic device according to an embodiment of the present disclosure. The electronic device <NUM> includes the frequency-detecting circuit <NUM> in the embodiments described above.

As shown in <FIG> is a structural schematic view of a storage device according to an embodiment of the present disclosure. The storage device <NUM> includes a DCC <NUM>. The DCC <NUM> is the same as the DCC provided in the above embodiments, and has a structure and an operating principle similar to those of the DCC provided in the above embodiments, which is not repeated herein. The storage device <NUM> may be the dynamic random access memory (DRAM), such as a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random-Access Memory).

Claim 1:
A frequency-detecting circuit (<NUM>), characterized by comprising:
a control-signal generating circuit (<NUM>), configured to receive a to-be-detected clock signal (CKin) and generate a first control signal (CKp) corresponding to the to-be-detected clock signal (CKin) and a second control signal (CKPD) delayed relative to the first control signal (CKp);
a charging and discharging path (<NUM>), coupled to the control-signal generating circuit (<NUM>), and performing a charging process or a discharging process under control of the second control signal (CKPD), wherein during a period with a pulse width when the second control signal (CKPD) is at a high level, the charging and discharging path (<NUM>) performs the discharging process, and the charging and discharging path (<NUM>) performs the charging process during another period when the second control signal (CKPD) is at a low level; and
a control-voltage generating circuit (<NUM>), coupled to an output terminal of the charging and discharging path (<NUM>) and the control-signal generating circuit (<NUM>), and configured to sample values of a voltage (ND1) of the output terminal of the charging and discharging path (<NUM>) before the discharging process during a period with a pulse width when the first control signal (CKp) is at the high level, to output a corresponding first voltage signal (V<NUM>);
wherein a voltage value of the first voltage signal (V<NUM>) is related to a frequency of the to-be-detected clock signal (CKin).