Patent Description:
Various electronic devices, such as a display device, may include a thin film transistor array panel which includes a thin film transistor.

The thin film transistor includes a gate electrode and a semiconductor member. The semiconductor member overlaps the gate electrode with an insulating layer interposed therebetween, and forms a channel region in the overlapping area. Amorphous or polycrystalline silicon (Si), oxide semiconductor, and the like are widely used as materials for the semiconductor member.

The semiconductor member also includes a source region and a drain region that are connected to the channel region, and also respectively connected to a source electrode and a drain electrode that are formed in a different layer from the semiconductor member.

The quality of the electronic device including the thin film transistor array panel is affected by characteristics of the thin film transistor.

<CIT> relates to an array substrate, a display device, and a method for manufacturing an array substrate.

<CIT> relates to a thin film transistor with a protective layer and method of manufacturing the same.

<CIT> relates to a method for fabricating a thin film transistor.

<CIT> relates to a thin film transistor and a manufacturing method thereof.

According to an aspect of the current invention, there is provided a thin film transistor array panel according to claim <NUM>. According to another aspect of the current invention, there is provided a method for manufacturing a thin film transistor array panel according to claim <NUM>.

Exemplary embodiments of the present invention provide enhanced characteristics of a thin film transistor in a thin film transistor array panel, and high resolution of a display device including the thin film transistor array panel.

According to exemplary embodiments of the present invention, in the thin film transistor array panel, parasitic capacitance between the gate electrode and the source electrode or the drain electrode is reduced such that characteristics of the thin film transistor may be enhanced, high resolution of the display device including the thin film transistor array panel may be obtained, and a variety of effects may be additionally provided.

The passivation layer may include a portion positioned in the first hole.

A plane separation distance between the data conductor and the gate electrode may be zero or greater than zero.

An insulating barrier layer on the channel region may be further included, a width of the insulating barrier layer in a first direction may be smaller than a width of the semiconductor member in the first direction, and a width of the first hole in the first direction may be equal to or greater than a width of the channel region in the first direction.

The passivation layer may be in contact with an upper surface of the insulating barrier layer in the first hole.

Exemplary embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

Since the drawings in <FIG> are intended for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity.

The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. As those skilled in the art would realize, the described exemplary embodiments herein may be modified in various different. The scope of the present invention is defined by the claims.

To clearly explain the present invention, portions that are not directly related to the present invention are omitted, and the same reference numerals are referred to the same or similar constituent elements throughout the entire specification.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Further, in the specification, the word "on" or "above" may mean positioned on or below the object portion, and does not necessarily mean positioned on the upper side of the object portion based on a gravitational direction.

Now, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to <FIG> and <FIG>.

The thin film transistor array panel according to an exemplary embodiment of the present invention includes a thin film transistor Q. The thin film transistor Q may be positioned on one surface of a substrate <NUM>. The substrate <NUM> may include an insulating material such as glass or plastic, and may be a film type.

A first direction Dr1 and a second direction Dr2 shown in <FIG> as directions parallel to a main surface of the substrate <NUM> are perpendicular to each other, and a third direction Dr3 shown in <FIG> as a direction perpendicular to the first and second directions Dr1 and Dr2 is a direction substantially perpendicular to the main surface of the substrate <NUM>. The third direction Dr3 may be mainly expressed in a cross-sectional structure, and may be referred to as a cross-sectional direction. A structure shown when observing the surface parallel in the first direction Dr1 and the second direction Dr2 is referred to as a plane structure. The plane structure may disregard any separation in the third direction Dr3 for those components of the structure under observation. For example, the plane structure may be shown as a top plan view structure.

The thin film transistor Q includes a gate electrode <NUM> positioned on one surface of the substrate <NUM>. The gate electrode <NUM> may include a metal such as, for example, aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti), or an alloy thereof, and may have a structure of a single layer or a multilayer including at least one of these materials.

A gate insulating layer 140a is positioned on the gate electrode <NUM>. The gate insulating layer 140a may include a portion that overlaps the gate electrode <NUM>, and a portion that is positioned on the substrate <NUM> and does not overlap the gate electrode <NUM>.

The gate insulating layer 140a may include an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), or an organic insulating material, and may have a structure of a single layer or a multilayer including at least one of these materials. Particularly, the gate insulating layer 140a of the single layer or a highest layer of the gate insulating layer 140a of the multilayer includes an oxide-based insulating material in which a content of hydrogen (H) is relatively low, thereby preventing hydrogen (H) from inflowing to a semiconductor member <NUM>.

The semiconductor member <NUM> is positioned on the gate insulating layer 140a. The semiconductor member <NUM> may include, for example, amorphous silicon, polysilicon, oxide semiconductor, or the like, and may have a structure of a single layer or a multilayer including at least one of these materials. In this case, the oxide semiconductor, for example, may be formed of an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or the like, or an oxide of a combination of metals such as at least two of zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), and the like. For example, the oxide semiconductor may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), and indium-zinc-tin oxide (IZTO).

The semiconductor member <NUM> includes a channel region <NUM>, a source region <NUM>, and a drain region <NUM>. The channel region <NUM> is interposed between the source region <NUM> and the drain region <NUM>.

The channel region <NUM> is a region where the channel is formed when the thin film transistor Q is turned on, and overlaps the gate electrode <NUM> with the gate insulating layer 140a interposed therebetween. In the plane structure, the channel region <NUM> may be completely superimposed with the gate electrode <NUM>. In detail, a width of the gate electrode <NUM> in the first direction Dr1 may be substantially the same as or larger than the width of the channel region <NUM> in the first direction Dr1.

Right and left edges of the channel region <NUM>, that is, a boundary between the channel region <NUM> and the source region <NUM> and a boundary between the channel region <NUM> and the drain region <NUM>, may be aligned with the right and left edges of the gate electrode <NUM>. In this case, the right and left edges of the gate electrode <NUM> that may be aligned with the right and left edges of the channel region <NUM> may each be an edge shown outermost in the plane structure. In this case, the width of the channel region <NUM> in the first direction Dr1 may be substantially the same as that of the gate electrode <NUM> in the first direction Dr1. Alternatively, the edge of the gate electrode <NUM> may overlap the source region <NUM> and the drain region <NUM> on a plane. In this case, the width of the gate electrode <NUM> in the first direction Dr1 may be slightly larger than the width of the channel region <NUM> in the first direction Dr1.

The source region <NUM> and the drain region <NUM> are positioned at respective sides of the channel region <NUM> and are separated from each other. The source region <NUM> and the drain region <NUM> are positioned at the same layer as the channel region <NUM> and are connected to the channel region <NUM>. A carrier concentration of the source region <NUM> and the drain region <NUM> may be larger than a carrier concentration of the channel region <NUM>, and the source region <NUM> and the drain region <NUM> may be conductive. A gradient region where the carrier concentration is gradually changed may be formed between the source region <NUM> and the channel region <NUM>, and between the drain region <NUM> and the channel region <NUM>.

When the semiconductor member <NUM> includes oxide semiconductor, the source region <NUM> and the drain region <NUM> may include a material in which the amount of the oxide semiconductor is reduced. For example, the source region <NUM> and the drain region <NUM> may further include at least one of fluorine (F), hydrogen (H), and sulfur (S), as opposed to the channel region <NUM>. A metal included in a semiconductor member <NUM> may be precipitated at the surface of the source region <NUM> and the drain region <NUM>.

The gate electrode <NUM> and the semiconductor member <NUM> together form the thin film transistor Q.

An insulating barrier layer <NUM> is positioned on the channel region <NUM>. A lower surface of the insulating barrier layer <NUM> may be in contact with an upper surface of the channel region <NUM>.

In the plane structure, the insulating barrier layer <NUM> may completely overlap the channel region <NUM>. In detail, the width of the insulating barrier layer <NUM> in the first direction Dr1 may be substantially equal to or larger than the width of the channel region <NUM> in the first direction Dr1. In other words, the right and left edges of the channel region <NUM>, that is, the boundary between the channel region <NUM> and the source region <NUM> and the boundary between the channel region <NUM> and the drain region <NUM>, may be aligned with the right and left edges of the insulating barrier layer <NUM>, or the right and left edges of the channel region <NUM> may overlap the insulating barrier layer <NUM> on a plane. The width of the insulating barrier layer <NUM> in the first direction Dr1 is smaller than the width of the semiconductor member <NUM> in the first direction Dr1.

The insulating barrier layer <NUM> may include an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), or an organic insulating material, and may have a structure of a single layer or a multilayer including at least one of these materials. Particularly, in the case that the semiconductor member <NUM> includes oxide semiconductor, the insulating barrier layer <NUM> of the single layer or a lowest layer of the insulating barrier layer <NUM> of the multilayer may include the inorganic insulating material of which an amount of hydrogen (H) is relatively low such as silicon oxide (SiOx) for protection of the channel region <NUM>.

In an example not falling within the scope of the claims, the insulating barrier layer <NUM> may be omitted, if necessary.

An interlayer insulating layer <NUM> is positioned on the semiconductor member <NUM>. The interlayer insulating layer <NUM> may be a layer that is separately formed in a process different from that of the insulating barrier layer <NUM> after forming the insulating barrier layer <NUM>. The interlayer insulating layer <NUM> has a plurality of holes <NUM>, <NUM>, and <NUM> in which the interlayer insulating layer <NUM> is removed. The hole <NUM> overlaps the insulating barrier layer <NUM> and is formed on the insulating barrier layer <NUM>, the hole <NUM> overlaps the source region <NUM> and is formed on the source region <NUM>, and the hole <NUM> overlaps the drain region <NUM> and is formed on the drain region <NUM>.

Referring to <FIG>, the interlayer insulating layer <NUM> may not cover most of the insulating barrier layer <NUM> in the hole <NUM>, and the insulating barrier layer <NUM> may be positioned in the hole <NUM>. Also, the channel region <NUM> may completely overlap the hole <NUM>, and a plane size of the hole <NUM> may be equal to or slightly larger than the plane size of the channel region <NUM>. In other words, the width of the hole <NUM> in the first direction Dr1 may be greater than the width of the channel region <NUM> in the first direction Dr1. The width of the hole <NUM> in the first direction Dr1 may be smaller than the width of the semiconductor member <NUM> in the first direction Dr1.

The thin film transistor Q may be configured differently from <FIG>. For example, the interlayer insulating layer <NUM> may cover and overlap an edge part of the insulating barrier layer <NUM>.

The interlayer insulating layer <NUM> may include an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxyfluoride (SiOF), or an organic insulating material, and may be a single layer or a multilayer including at least one of these materials. Particularly, when the semiconductor member <NUM> includes oxide semiconductor, the interlayer insulating layer <NUM> of the single layer or the lowest layer of the interlayer insulating layer <NUM> of the multilayer may include a nitride-based inorganic insulating material containing a relatively large amount of hydrogen (H) such as silicon nitride (SiNx). Alternatively, in a case of the multi-layered interlayer insulating layer <NUM>, a layer including silicon oxide (SiOx), for example, may be positioned on the lowest layer.

A data conductor including a first connection part <NUM> and a second connection part <NUM> is positioned on the interlayer insulating layer <NUM>. The first connection part <NUM> is electrically connected to the source region <NUM> of the thin film transistor Q through the hole <NUM> of the interlayer insulating layer <NUM>, and the second connection part <NUM> is electrically connected to the drain region <NUM> of the thin film transistor Q through the hole <NUM> of the interlayer insulating layer <NUM>. The first connection part <NUM> and the second connection part <NUM> do not overlap the gate electrode <NUM> on a plane. That is, in the plane structure, a separation distance W between the first connection part <NUM> or the second connection part <NUM> and the gate electrode <NUM> may be zero or greater than zero. In other words, the first connection part <NUM> or the second connection part <NUM> may have its edge superimposed on or separated from the edge of the gate electrode <NUM> in the plane structure.

The first connection part <NUM> and the second connection part <NUM> may include a conductive material of a metal such as, for example, aluminum, silver, copper, molybdenum, chromium, tantalum, or titanium, or an alloy thereof, and may have a structure of a single layer or a multilayer including at least one of these materials.

The source region <NUM> and the first connection part <NUM> connected thereto may function as a source electrode of the thin film transistor Q, and the drain region <NUM> and the second connection part <NUM> connected thereto may function as a drain electrode of the thin film transistor Q.

At least one of the first connection part <NUM> and the second connection part <NUM> may be omitted depending on the kind of the thin film transistor Q to be formed.

A passivation layer <NUM> may be positioned on the insulating barrier layer <NUM>, and the first connection part <NUM> and the second connection part <NUM>. The passivation layer <NUM> may include an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), or aluminum oxide (AlOx), or an organic insulating material, and may have a structure of a single layer or a multilayer. An upper surface of the passivation layer <NUM> may be substantially flat.

The passivation layer <NUM> may directly contact the upper surface of the insulating barrier layer <NUM> and the upper surface of the interlayer insulating layer <NUM>. The passivation layer <NUM> may include a part positioned in the hole <NUM>. Even if the passivation layer <NUM> includes a material the same as that of the insulating barrier layer <NUM> or the interlayer insulating layer <NUM>, layer qualities thereof are different from each other such that a boundary may be formed between the insulating barrier layer <NUM> and the passivation layer <NUM> or between the interlayer insulating layer <NUM> and the passivation layer <NUM>.

A characteristic of the thin film transistor Q according to the present exemplary embodiment will be described with reference to the structure of the thin film transistor according to a conventional art shown in <FIG> and a characteristic graph of the thin film transistor shown in <FIG>.

<FIG> are cross-sectional views of a part of a thin film transistor array panel according to a conventional art, respectively.

Referring to <FIG>, a thin film transistor Qr according to a conventional art includes a semiconductor member 131r positioned on a substrate 111r and including a source region 133r, a drain region 135r, and a channel region 134r, a gate insulating layer 144r positioned on the channel region 134r, and a gate electrode 124r positioned on the gate insulating layer 144r. An insulating layer 160r is positioned on the thin film transistor Qr, and a first connection part 173r and a second connection part 175r positioned on the insulating layer 160r may be connected to the source region 133r and the drain region 135r through holes 163r and 165r of the insulating layer 16or, respectively.

Referring to <FIG>, a thin film transistor Qre having a structure different from that of the thin film transistor Qr according to a conventional art includes a gate electrode 124re positioned on a substrate 111re, a gate insulating layer 140re positioned on the gate electrode 124re, a semiconductor member 131re positioned on the gate insulating layer 140re, an etch stopper 160re positioned on the semiconductor member 131re, a source electrode 173re and a drain electrode 175re positioned on the semiconductor member 131re and the etch stopper 160re, and a passivation layer 180re positioned on the source electrode 173re and the drain electrode 175re.

<FIG> shows a drain current Id vs a gate voltage Vg (Id-Vg) characteristic depending on various drain voltages (Vd=<NUM> V, <NUM> V) before applying a stress to the thin film transistor Qre according to the conventional art shown in <FIG> (Initial), and a drain current Id vs a gate voltage Vg (Id-Vg) characteristic depending on various drain voltages (Vd=<NUM> V, <NUM> V) after applying the stress (After stress). The stress applied to the thin film transistor Qre, for example, may be one in which a source-drain voltage Vds is a very high voltage (e.g., Vds=<NUM> V, Vgs=<NUM> V). As shown in the graph of <FIG>, compared with before applying the stress to the thin film transistor Qre, the Id-Vg characteristic change of the thin film transistor Qre is large after applying the stress.

<FIG> is a graph showing a drain current (Id) vs a gate voltage (Vg) (Id-Vg) characteristic of a thin film transistor included in a thin film transistor array panel according to an exemplary embodiment of the present invention. Referring to <FIG>, the thin film transistor Q according to an exemplary embodiment of the present invention exhibits the same Id-Vg characteristic before receiving the stress and after receiving the stress in the same condition as the thin film transistor Qre such that it may be confirmed that the Id-Vg characteristic of the thin film transistor Q is enhanced.

In the case of the thin film transistor Qre according to the conventional art shown in <FIG>, since the source electrode 173re and the drain electrode 175re are directly connected to the semiconductor region of the semiconductor member 131re, a strong electric field is formed near the connection part thereof, particularly, the semiconductor member 131re is weak against the stress for the high voltage in the high source-drain voltage Vds such that the reliability of the thin film transistor Qre is reduced. However, according to the present exemplary embodiment, while the gate electrode <NUM> is disposed under the semiconductor member <NUM> like the thin film transistor Qre shown in <FIG>, the first connection part <NUM> and the second connection part <NUM> functioning as the source electrode and the drain electrode are not directly connected with the channel region <NUM>, but are connected to the channel region <NUM> through the source region <NUM> and the drain region <NUM>, thus even if the high source-drain voltage Vds is applied, a relatively small electric field is formed on the semiconductor member <NUM> such that the reliability against the high voltage stress of the thin film transistor Q may be enhanced.

In the case of the thin film transistor Qre according to the conventional art shown in <FIG>, the gate electrode 124re vertically overlaps the source electrode 173re and the drain electrode 175re in the third direction. Accordingly, a parasitic capacitance Cgs is generated between the gate electrode 124re and the source electrode 173re or between the gate electrode 124e and the drain electrode 175re such that there are problems associated with a voltage being insufficiently applied to another electrode (e.g., a pixel electrode) connected to the thin film transistor Qre due to an RC delay, so a kickback voltage and a consumption power increases. However, according to an exemplary embodiment of the present invention, because the gate electrode <NUM> only mainly overlaps the channel region <NUM> but does not vertically overlap the source region <NUM>, the drain region <NUM>, the first connection part <NUM> and the second connection part <NUM> in the third direction (vertical direction), the parasitic capacitance Cgs is not generated between the gate electrode <NUM> and the source region <NUM>, the drain region <NUM>, the first connection part <NUM>, and the second connection part <NUM>, and accordingly the problems due to the parasitic capacitance Cgs are not generated and the thin film transistor Q and electrical elements connected thereto may be driven by lower power.

<FIG> is a graph showing the drain current (Id) vs the gate voltage (Vg) (Id-Vg) characteristic of the thin film transistor Qr depending on different amounts of time (<NUM>-<NUM>) in which a negative bias is applied to the gate electrode 124r of the thin film transistor Qr according to the conventional art shown in <FIG>. As shown in the graph of <FIG>, the Id-Vg characteristic change of the thin film transistor Qr is large depending on the amount of time that the negative bias is applied to the gate electrode 124r of the thin film transistor Qr.

<FIG> is the graph showing the drain current (Id) vs the gate voltage (Vg) (Id-Vg) characteristic of the thin film transistor Q depending on different amounts of time (<NUM> sec-<NUM> hrs) in which the negative bias is applied to the gate electrode <NUM> of the thin film transistor Q included in the thin film transistor array panel according to an exemplary embodiment of the present invention. Referring to <FIG>, for the thin film transistor Q according to an exemplary embodiment of the present invention, it may be confirmed that the Id-Vg characteristic change of the thin film transistor Q is small compared with that of the thin film transistor Qre of the conventional art.

In the case of the thin film transistor Qr according to the conventional art shown in <FIG>, the gate electrode 124r is positioned at the same side as the first connection part 173r and the second connection part 175r based on the semiconductor member 131r such that there is a risk of short being generated between the gate electrode 124r, and the first connection part 173r and the second connection part 175r, thereby between the gate electrode 124r, and the first connection part 173r and the second connection part 175r, each must be formed with a space margin having a predetermined distance. The predetermined distance is a smallest distance sufficient to prevent short between the gate electrode 124r and the first connection part 173r or between the gate electrode 124r and the second connection part 175r. That is, it must be designed such that a plane separation distance Wr between the gate electrode 124r and the first connection part 173r or between the gate electrode 124r and the second connection part 175r shown in <FIG> has a predetermined value or a value larger than the predetermined value. However, according to an exemplary embodiment of the present invention, the gate electrode <NUM> is positioned at the opposite side to the first connection part <NUM> and the second connection part <NUM> based on the semiconductor member <NUM> and other conductors are not positioned on the channel region <NUM> such that the risk of short being generated between the first connection part <NUM> and the second connection part <NUM>, and the gate electrode <NUM>, or between other conductors on the channel region <NUM>, is small, thereby reducing a space margin on a plane between the gate electrode <NUM> and the first connection part <NUM> or between the gate electrode <NUM> and the second connection part <NUM>. That is, the plane separation distance W, a separation distance in the first direction Dr1 here, between the gate electrode <NUM> and the first connection part <NUM> or the second connection part <NUM> shown in <FIG> and <FIG> may be reduced and the plane separation distance W may be zero or greater than zero. Accordingly, a plane size of the thin film transistor Q may be reduced compared with that of the conventional art, thereby realizing high resolution for the thin film transistor array panel.

In the case of the thin film transistor Qr according to the conventional art shown in <FIG>, the gate electrode 124r is positioned at the same side as the first connection part 173r and the second connection part 175r based on the semiconductor member 131r such that the parasitic capacitance Cgs on a plane is generated between the gate electrode 124r and the first connection part 173r and between the gate electrode 124r and the second connection part 175r, thereby causing the above-described problems due to the parasitic capacitance Cgs. However, according to an exemplary embodiment of the present invention, the gate electrode <NUM> is positioned at the opposite side to the first connection part <NUM> and the second connection part <NUM> based on the semiconductor member <NUM> such that the first connection part <NUM> and the second connection part <NUM> are not adjacent to the gate electrode <NUM> on a plane. Also, other conductors adjacent to the first and second connection parts <NUM> and <NUM> do not exist on the channel region <NUM>. Accordingly, the plane parasitic capacitance Cgs is not generated between the gate electrode <NUM> and the first connection part <NUM> and between the gate electrode <NUM> and the second connection part <NUM>, such that the problems due to the parasitic capacitance Cgs are not generated and the thin film transistor Q and the electrical elements connected thereto may be driven by lower power.

As described above, the thin film transistor Q according to an exemplary embodiment of the present invention has the merits of solving all drawbacks compared with the thin film transistor of any structure according to the conventional art, such that the thin film transistor array panel having high resolution and driven with low power may be provided, and the thin film transistor having the enhanced characteristic in any voltage condition and time condition may be provided.

A manufacturing method of the thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to <FIG> along with the above-described drawings. Particularly, the manufacturing method of the thin film transistor array panel according to the above-described exemplary embodiment shown in <FIG> and <FIG> will be described.

First, referring to <FIG>, a conductive material, for example, at least one of the metals such as, for example, aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), and the like, or alloys thereof, is deposited on a substrate <NUM> including an insulating material of glass or plastic, and is patterned to form a gate electrode <NUM> with a structure of a single layer or a multilayer.

Next, an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), or an organic insulating material is deposited on the gate electrode <NUM> and the substrate <NUM> to form a gate insulating layer 140a with a structure of a single layer or a multilayer.

Referring to <FIG>, amorphous silicon, polysilicon, or an oxide semiconductor material such as, for example, zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), or indium-zinc-tin oxide (IZTO) is then deposited on the gate insulating layer 140a and patterned to form a semiconductor member <NUM>.

Next, an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride, or an organic insulating material is deposited on the semiconductor member <NUM> and the gate insulating layer 140a to form an insulating layer 140b with a structure of a single layer or a multilayer. Particularly, when the semiconductor member <NUM> includes the oxide semiconductor described above, the insulating layer 140b of the single layer or the lowest layer of the insulating layer 140b of the multilayer may include the inorganic insulating material in which hydrogen (H) is less included in a gas used in the film formation process, such as silicon oxide (SiOx).

Next, a doping barrier layer <NUM> is formed on the insulating layer 140b. The doping barrier layer <NUM> may include a material such as a metal for preventing an impurity such as hydrogen (H), which may be used to dope the semiconductor member <NUM> to make a conductive region in the later process step, from passing through. For example, when the semiconductor member <NUM> includes the oxide semiconductor described above, the doping barrier layer <NUM> may include a metal material such as titanium (Ti) or an oxide semiconductor material.

Next, referring to <FIG>, a mask pattern <NUM> such as a photoresist is formed on the doping barrier layer <NUM>, and the doping barrier layer <NUM> and the insulating layer 140b are etched by using the mask pattern <NUM> as an etching mask to form a barrier pattern <NUM> and an insulating barrier layer <NUM> under the barrier pattern <NUM>. In this case, the left and right edges of the barrier pattern <NUM> and the insulating barrier layer <NUM> may be substantially aligned with the left and right edges of the gate electrode <NUM> or may be positioned at a position overlapping the gate electrode <NUM>. Accordingly, a part of the semiconductor member <NUM> is exposed.

Next, referring to <FIG>, the mask pattern <NUM> is removed, and an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxyfluoride (SiOF), or an organic insulating material is deposited on the barrier pattern <NUM>, the semiconductor member <NUM>, and the gate insulating layer 140a to form an interlayer insulating layer <NUM> with a structure of a single layer or a multilayer. Particularly, when the semiconductor member <NUM> includes the oxide semiconductor described above, the interlayer insulating layer <NUM> of the single layer or the lowest layer of the interlayer insulating layer <NUM> of the multilayer may include a nitride-based inorganic insulating material such as silicon nitride (SiNx), using a gas including hydrogen such as silane (SiH4) and ammonia (NH3) in the film formation process.

In the film formation process of the interlayer insulating layer <NUM>, a hydrogen (H) component of the gas including hydrogen (H) is penetrated or doped to the semiconductor member <NUM> that is not covered by the barrier pattern <NUM>, thereby forming a source region <NUM> and a drain region <NUM> having conductivity. Hydrogen or the impurity is not penetrated into the semiconductor member <NUM> covered by the barrier pattern <NUM> through the barrier pattern <NUM>, thereby forming the channel region <NUM> maintaining a semiconductor characteristic. Accordingly, the semiconductor member <NUM> including the source region <NUM>, the drain region <NUM>, and the channel region <NUM> is formed. After the film formation of the interlayer insulating layer <NUM>, the impurity included in the interlayer insulating layer <NUM> such as hydrogen may be diffused into the source region <NUM> and the drain region <NUM>.

According to an exemplary embodiment of the present invention, before forming the interlayer insulating layer <NUM>, the semiconductor member <NUM> that is not covered by the barrier pattern <NUM> may be subjected to a reduction treatment or an n+ doping treatment to form the source region <NUM> and the drain region <NUM>. In this case, as the treatment method, for example, there may be a heat treatment in a reduction atmosphere, a plasma treatment method using a gas plasma such as, for example, hydrogen (H2), helium (He), phosphine (PH3), ammonia (NH3), silane (SiH4), methane (CH4), acetylene (C2H2), diborane (B2H6), carbon dioxide (CO2), germane (GeH4), hydrogen selenide (H2Se), hydrogen sulfide (H2S), argon (Ar), nitrogen (N2), nitrogen oxide (N2O), fluoroform (CHF3), or any combination thereof.

Next, referring to <FIG>, the interlayer insulating layer <NUM> is patterned by a method such as an etching to form a hole <NUM> exposing the source region <NUM>, a hole <NUM> exposing the drain region <NUM>, and a hole <NUM> exposing the barrier pattern <NUM>. The hole <NUM> may expose the entire portion of the barrier pattern <NUM>, as shown in <FIG>. At least one of the hole <NUM> and the hole <NUM> may be omitted depending on the kind of the thin film transistor to be formed.

Next, referring to <FIG>, the conductive material including a metal such as, for example, aluminum, silver, copper, molybdenum, chromium, tantalum, or titanium, or any alloy thereof, is deposited on the interlayer insulating layer <NUM> to form a conductive layer <NUM> with a structure of a single layer or a multilayer.

Next, referring to <FIG>, the conductive layer <NUM> is patterned through an etching to form a data conductor including a first connection part <NUM> connected to the source region <NUM> and a second connection part <NUM> connected to the drain region <NUM>. The barrier pattern <NUM> may be removed by the etching along with the patterning of the conductive layer <NUM>. Alternatively, the barrier pattern <NUM> may be removed by an etching after patterning the conductive layer <NUM>. Accordingly, as shown in <FIG>, the upper surface of the insulating barrier layer <NUM> may be exposed. As described above, because the barrier pattern <NUM> is removed, the conductor causing the short of the first connection part <NUM> and the second connection part <NUM> is removed on the channel region <NUM>, thereby realizing high resolution for the thin film transistor array panel and the display device including the same.

As described above, referring to <FIG> and <FIG>, at least one of an inorganic insulating material and an organic insulating material is deposited on the insulating barrier layer <NUM>, the first connection part <NUM>, and the second connection part <NUM> to form a passivation layer <NUM> with a structure of a single layer or a multilayer.

According to an exemplary embodiment of the present invention, the thin film transistor may be manufactured differently from that shown in <FIG>. For example, the doping barrier layer <NUM> and the barrier pattern <NUM> may be omitted and only the insulating barrier layer <NUM> may prevent the semiconductor member <NUM> from being doped with hydrogen or the impurity. In this case, the insulating barrier layer <NUM> may have a sufficient thickness to prevent the penetration of hydrogen or the impurity.

Next, the thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to <FIG> and <FIG>. Like reference numerals are provided for the same constituent elements as in the above-described exemplary embodiment, the same description thereof is omitted, and differences are mainly described.

The thin film transistor array panel according to an exemplary embodiment of the present invention includes the thin film transistor Qa. The thin film transistor array panel according to the present exemplary embodiment is almost the same as the thin film transistor array panel according to the exemplary embodiment shown in <FIG> and <FIG> except for a structure of a semiconductor member 131A, an insulating barrier layer 144A, and an interlayer insulating layer <NUM>.

The semiconductor member 131A may be positioned on a gate insulating layer 140a and may include a channel region 134A, a source region <NUM>, a drain region <NUM>, and a buffer region <NUM>. The channel region 134A, the source region <NUM>, and the drain region <NUM> are the same as the channel region <NUM>, the source region <NUM>, and the drain region <NUM> of the above-described exemplary embodiment such that the detailed description thereof is omitted.

The buffer region <NUM> is positioned between the channel region 134A and the source region <NUM> and between the channel region 134A and the drain region <NUM>, and is referred to as a low conductive region. A carrier concentration of the buffer region <NUM> is higher than a carrier concentration of the channel region 134A, but is lower than a carrier concentration of the source region <NUM> and the drain region <NUM>. The buffer region <NUM> may have lower conductivity than the source region <NUM> and the drain region <NUM>. Also, the carrier concentration of the buffer region <NUM> may be gradually reduced from the source region <NUM> and the drain region <NUM> toward the channel region 134A.

The metal such as indium (In) included in the semiconductor member 131A may be precipitated at the surface of the buffer region <NUM>.

An insulating barrier layer 144A is positioned on the semiconductor member 131A. The insulating barrier layer 144A is almost the same as the insulating barrier layer <NUM> of the above-described exemplary embodiment, but the insulating barrier layer 144A may also include an outer part <NUM> positioned on the buffer region <NUM> as well as the channel region 134A. The outer part <NUM> may overlap the buffer region <NUM> on a plane. Accordingly, the width of the insulating barrier layer 144A in the first direction Dr1 may be substantially the same as or slightly larger than the entire width including the channel region 134A and the buffer regions <NUM> of both sides in the first direction Dr1. In other words, the entire left and right edges of the channel region 134A and both sides of the buffer region <NUM>, that is, the boundary between the buffer region <NUM> and the source region <NUM> and the boundary between the buffer region <NUM> and the drain region <NUM>, may be aligned with the right and left edges of the insulating barrier layer 144A or overlap the insulating barrier layer 144A on a plane. On the other hand, the right and left edges of the gate electrode <NUM> may be aligned with the right and left boundaries between the channel region 134A and the buffer regions <NUM>.

The interlayer insulating layer <NUM> positioned on the semiconductor member 131A is almost the same as the interlayer insulating layer <NUM> of the above-described exemplary embodiment, however the interlayer insulating layer <NUM> may not cover most of the insulating barrier layer 144A in the hole <NUM>. The interlayer insulating layer <NUM>, as shown in <FIG>, may cover and overlap a part of the left and right edges of the insulating barrier layer 144A. The width of the hole <NUM> in the first direction Dr1 may be equal to or larger than the width of the channel region 134A in the first direction Dr1, and the plane size of the hole <NUM> may be equal to or larger than the plane size of the channel region 134A. The width of the hole <NUM> in the first direction Dr1 may be smaller than the width of the semiconductor member 131A in the first direction Dr1.

According to the present exemplary embodiment, the carrier concentration between the channel region 134A and the source region <NUM> or between the channel region 134A and the drain region <NUM> is gradually changed such that generation of a hot carrier may be suppressed and a channel length of the channel region 134A may be prevented from being shortened. Accordingly, a sharp increase of the current flowing into the channel region 134A may be prevented. Also, even if the high source-drain voltage (Vds) is applied to the thin film transistor Qa, intensity of the electric field applied to the semiconductor member 131A by the buffer region <NUM> is smoothened such that the reliability against the high voltage stress of the thin film transistor Qa may be further enhanced and a stable characteristic may appear.

Next, the manufacturing method of a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to <FIG> along with the above-described drawings. Particularly, the manufacturing method of the thin film transistor array panel according to the exemplary embodiment shown in <FIG> and <FIG> will be described.

As shown in <FIG> and as described above, a gate electrode <NUM>, a gate insulating layer 140a, a semiconductor member <NUM>, an insulating layer 140b, and a doping barrier layer <NUM> are sequentially formed on a substrate <NUM>.

Next, referring to <FIG>, a mask pattern 50A such as a photoresist is formed on the doping barrier layer <NUM>. The mask pattern 50A may include a first portion <NUM> of which the cross-sectional thickness is relatively thick and a second portion <NUM> of which the cross-sectional thickness is relatively thin. The boundaries between the first portion <NUM> and the second portion <NUM> may be almost aligned with the left and right edges of the gate electrode <NUM>.

Next, referring to <FIG>, the doping barrier layer <NUM> and the insulating layer 140b are etched by using the mask pattern 50A as an etching mask to form a barrier pattern <NUM> and an insulating layer pattern <NUM> under the barrier pattern <NUM>. In this case, the width of the barrier pattern <NUM> and the insulating layer pattern <NUM> in the first direction Dr1 may be larger than the width of the gate electrode <NUM> in the first direction Dr1.

Next, referring to <FIG>, the thickness of the mask pattern 50A is reduced by a method such as ashing to remove the second portion <NUM> and to form a mask pattern 51A. Accordingly, an edge part of the barrier pattern <NUM> is exposed.

Next, the exposed edge part of the barrier pattern <NUM> is etched by using the mask pattern 51A as an etching mask to form a barrier pattern 154A. The insulating layer pattern <NUM> becomes the insulating barrier layer 144A including the portion that is covered by the barrier pattern 154A, and an outer part <NUM> that is not covered by the barrier pattern 154A and is exposed. That is, the edge part (the outer part <NUM>) of the insulating barrier layer 144A is not covered by the barrier pattern 154A, and is exposed.

Next, referring to <FIG>, the mask pattern 51A is removed by a method such as ashing.

Referring to <FIG>, the reduction treatment or the n+ doping treatment is then performed on the semiconductor member 131A that is not covered by the barrier pattern 154A to form the source region <NUM>, the drain region <NUM>, and the buffer region <NUM>. In this case, heat treatment in a reduction atmosphere or plasma treatment using a gas plasma such as hydrogen (H2) may be performed.

The semiconductor member 131A covered by the barrier pattern 154A forms the channel region 134A. The semiconductor member 131A that only overlaps the insulating barrier layer 144A while not being overlapped with the barrier pattern 154A, that is, the region of the semiconductor member 131A overlapping the outer part <NUM> of the insulating barrier layer 144A, has the treatment weaker than the treatment of the source region <NUM> and the drain region <NUM>, thereby forming the buffer region <NUM> having a conductivity lower than that of the source region <NUM> and the drain region <NUM>. The carrier concentration is gradually changed in the buffer region <NUM> between the channel region 134A and the source region <NUM> or in the buffer region <NUM> between the channel region 134A and the drain region <NUM>.

During the reduction treatment of the semiconductor member 131A, the metal component of the semiconductor material may be precipitated onto the surface of the source region <NUM>, the drain region <NUM>, and the buffer region <NUM>.

Next, an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxyfluoride (SiOF), or an organic insulating material is deposited on the barrier pattern 154A, the semiconductor member 131A, and the gate insulating layer 140a. Accordingly, the above-described interlayer insulating layer <NUM> as shown in <FIG> and <FIG> is formed.

In the film formation of the interlayer insulating layer <NUM>, the hydrogen (H) component of the gas including hydrogen (H) is penetrated or doped into the semiconductor member 131A that is not covered by the barrier pattern 154A, such that the source region <NUM>, the drain region <NUM>, and the buffer region <NUM> having conductivity may be formed. In this case, before forming the above-described interlayer insulating layer <NUM>, the treatment for the semiconductor member <NUM> may not be executed.

Next, the interlayer insulating layer <NUM> is patterned to form a hole <NUM> exposing the source region <NUM>, a hole <NUM> exposing the drain region <NUM>, and a hole <NUM> exposing the barrier pattern 154A, and then a conductive layer such as a metal is formed on the interlayer insulating layer <NUM> and is patterned to form a data conductor including a first connection part <NUM> connected to the source region <NUM> and a second connection part <NUM> connected to the drain region <NUM>. In this case, the barrier pattern 154A may also be removed along with the patterning of the conductive layer or after the patterning of the conductive layer. Next, a passivation layer <NUM> may be formed on the insulating barrier layer 144A, the first connection part <NUM>, and the second connection part <NUM>.

The thin film transistor array panel according to an example not falling within the scope of the claims will now be described with reference to <FIG> and <FIG>. Like reference numerals are provided for the same constituent elements as in the above-described exemplary embodiment, the same description thereof is omitted, and differences are mainly described.

A thin film transistor array panel according to an example not falling within the scope of the claims includes a thin film transistor Qb. The thin film transistor array panel according to the present example is almost the same as the thin film transistor array panel according to the exemplary embodiment shown in <FIG> and <FIG>, however the insulating barrier layer <NUM> of the above-described exemplary embodiment may not be positioned between the channel region <NUM> and the passivation layer <NUM>, and the structure of the interlayer insulating layer <NUM> may be different from the structure of the interlayer insulating layer <NUM> of the above-described exemplary embodiment.

The interlayer insulating layer <NUM> may have a hole 163A overlapping the source region <NUM>, a hole 165A overlapping the drain region <NUM>, and a hole 164A overlapping the channel region <NUM> and positioned on the channel region <NUM>.

The first connection part <NUM> and the second connection part <NUM> may be connected directly to the source region <NUM> and the drain region <NUM> in the holes 163A and 165A, respectively, and may cover the right and left edges of the semiconductor member <NUM>.

In the hole 164A, the interlayer insulating layer <NUM> may not cover most of the channel region <NUM>. The channel region <NUM> may completely overlap the hole 164A, and the plane size of the hole 164A may be equal to or larger than the plane size of the channel region <NUM>.

The thin film transistor Qb may be configured differently from that shown in <FIG>. For example, the interlayer insulating layer <NUM> positioned on the semiconductor member <NUM> may all be removed.

The passivation layer <NUM> may be in contact with the upper surface of the channel region <NUM>, and may be in the hole 164A.

Next, a manufacturing method of the thin film transistor array panel according to an example not falling within the scope of the claims will be described with reference to <FIG> along with the above-described drawings.

First, after sequentially forming a gate electrode <NUM>, a gate insulating layer 140a, and a semiconductor member <NUM> on a substrate <NUM>, a doping barrier layer <NUM> is formed on the semiconductor member <NUM> and the gate insulating layer 140a. The doping barrier layer <NUM> may include a material, such as a metal, for preventing the material such as hydrogen (H) or the impurity from passing through. For example, when the semiconductor member <NUM> includes the oxide semiconductor described above, the doping barrier layer <NUM> may include a metal material such as titanium (Ti).

Next, referring to <FIG>, the doping barrier layer <NUM> is patterned to form a barrier pattern <NUM>. The left and right edges of the barrier pattern <NUM> may be almost aligned with the left and right edges of the gate electrode <NUM> or may overlap the gate electrode <NUM> on a plane.

Next, referring to <FIG>, an interlayer insulating layer <NUM> is formed on the barrier pattern <NUM>, the semiconductor member <NUM>, and the gate insulating layer 140a. As described above, in the film formation process of the interlayer insulating layer <NUM>, the semiconductor member <NUM> that is not covered by the barrier pattern <NUM> becomes the source region <NUM> and the drain region <NUM> having conductivity, and the semiconductor member <NUM> covered by the barrier pattern <NUM> becomes the channel region <NUM>, thereby forming the semiconductor member <NUM>.

According to an example not falling within the scope of the claims, before forming the interlayer insulating layer <NUM>, the semiconductor member <NUM> that is not covered by the barrier pattern <NUM> may be subjected to the reduction treatment or the n+ doping treatment to form the source region <NUM> and the drain region <NUM>.

Next, referring to <FIG>, the interlayer insulating layer <NUM> is patterned to form a hole 163A exposing the source region <NUM>, a hole 165A exposing the drain region <NUM>, and a hole 164A exposing the barrier pattern <NUM>. The hole 164A may expose the entire barrier pattern <NUM>. Alternatively, most of the interlayer insulating layer <NUM> positioned on the semiconductor member <NUM> may be removed.

Next, referring to <FIG>, a conductive layer <NUM> including a metal is formed on the interlayer insulating layer <NUM>. The conductive layer <NUM> may be in contact with the upper surface of the barrier pattern <NUM>.

Next, referring to <FIG>, the conductive layer <NUM> is patterned to form the data conductor including the first connection part <NUM> and the second connection part <NUM>. The barrier pattern <NUM> is also removed along with the patterning of the conductive layer <NUM> such that the upper surface of the channel region <NUM> may be exposed. Alternatively, the barrier pattern <NUM> may be removed by etching after patterning of the conductive layer <NUM>.

Next, referring to <FIG> and <FIG>, a passivation layer <NUM> is formed on the first connection part <NUM> and the second connection part <NUM>.

A structure of the thin film transistor array panel according to an exemplary embodiment of the present invention will now be described with reference to <FIG> and <FIG>. The same constituent elements as in the structure described above are designated by the same reference numerals, a duplicated description is omitted, and differences will be mainly described.

Referring to <FIG> and <FIG>, one pixel PX as a unit displaying an image in the thin film transistor array panel according to an example not falling within the scope of the claims includes a driving transistor Qd positioned on one surface of a substrate <NUM>, and the driving transistor Qd has a structure the same as those of the thin film transistors Q, Qa, and Qb according to the above-described exemplary embodiments. <FIG> shows a cross-sectional structure of the driving transistor Qd with the structure the same as that of the thin film transistor Q according to the exemplary embodiment shown in <FIG> and <FIG>.

Referring to <FIG>, a gate line <NUM> transmitting a gate signal, a data line <NUM> transmitting a data signal, a driving voltage line <NUM> transmitting a driving voltage, a switching transistor Qs including a switching semiconductor member <NUM> and a switching gate electrode <NUM>, a third connection part <NUM>, and a fourth connection part <NUM> may be further positioned on the substrate <NUM>.

The gate line <NUM> may mainly extend in the first direction Dr1, and the data line <NUM> and the driving voltage line <NUM> may mainly extend in the second direction Dr2.

The first connection part <NUM> connected to the driving transistor Qd is connected to the driving voltage line <NUM>, thereby receiving the driving voltage.

The switching semiconductor member <NUM> includes a channel region <NUM> in which the channel of the switching transistor Qs is formed, and a source region <NUM> and a drain region <NUM> positioned at respective sides of the channel region <NUM>. The switching semiconductor member <NUM> may include a material the same as that of the semiconductor member <NUM>, thereby being positioned at the same layer as the semiconductor member <NUM>, or may include a different semiconductor material, thereby being positioned at a different layer from the semiconductor member <NUM>. For example, the switching semiconductor member <NUM> may include polysilicon, and the semiconductor member <NUM> may include oxide semiconductor.

The switching gate electrode <NUM> overlaps the channel region <NUM> with the gate insulating layer 140a or another insulating layer interposed therebetween. The switching gate electrode <NUM> may be positioned at the same layer as the gate electrode <NUM> of the driving transistor Qd. The switching gate electrode <NUM> is connected to the gate line <NUM> thereby receiving the gate signal.

The interlayer insulating layer <NUM> may have a hole <NUM> positioned on the source region <NUM> and a hole <NUM> positioned on the drain region <NUM> of the switching transistor Qs, and the interlayer insulating layer <NUM> and the gate insulating layer 140a may have a hole <NUM> positioned on the fourth connection part <NUM>.

The third connection part <NUM> and the fourth connection part <NUM> may be positioned on the interlayer insulating layer <NUM>. The third connection part <NUM> may be electrically connected to the source region <NUM> through the hole <NUM>, and the fourth connection part <NUM> may be electrically connected to the drain region <NUM> through the hole <NUM>. The third connection part <NUM> may be connected to the data line <NUM> to receive a data signal and transmit the data signal to the switching transistor Qs. The fourth connection part <NUM> may be electrically connected to the gate electrode <NUM> of the driving transistor Qd through the hole <NUM>.

The gate electrode <NUM> may be connected to a conductor <NUM>. The conductor <NUM> may mainly overlap the driving voltage line <NUM> with the interlayer insulating layer <NUM> and the gate insulating layer 140a interposed therebetween.

The passivation layer <NUM> is positioned on the second connection part <NUM>, and may have a hole <NUM> overlapping the second connection part <NUM>.

A pixel electrode <NUM> may be positioned on the passivation layer <NUM>. The pixel electrode <NUM> is connected to the second connection part <NUM> through the hole <NUM> thereby receiving the drain voltage. A pixel definition layer <NUM> may be positioned on the passivation layer <NUM>. The pixel definition layer <NUM> may cover a part of the edge of the pixel electrode <NUM>. An emission layer <NUM> is positioned on the pixel electrode <NUM> that is not covered by the pixel definition layer <NUM>, and a common electrode <NUM> is positioned on the emission layer <NUM>. The pixel electrode <NUM>, the emission layer <NUM>, and the common electrode <NUM> may together form an organic light emitting diode.

As described above, the display device including the thin film transistor array panel according to an exemplary embodiment of the present invention may easily realize high resolution as described above and may be driven with lower power, and may provide an image with good quality by the thin film transistor having the enhanced characteristic.

Claim 1:
A thin film transistor comprising:
a substrate (<NUM>);
a gate electrode (<NUM>) on the substrate;
a gate insulating layer (140a) on the gate electrode;
a semiconductor member (<NUM>) including a channel region (<NUM>) overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region (<NUM>) and a drain region (<NUM>) that face each other with the channel region interposed therebetween;
an interlayer insulating layer (<NUM>) directly on the semiconductor member;
a data conductor (<NUM>, <NUM>) on the interlayer insulating layer; and
a passivation layer (<NUM>) on the data conductor,
an insulating barrier layer (<NUM>) on the channel region,
wherein the interlayer insulating layer has a first hole (<NUM>) on the channel region, and a second hole (<NUM>, <NUM>) formed up to the source region (<NUM>) or the drain region (<NUM>),
wherein the first hole (<NUM>) and the second hole (<NUM>, <NUM>) are separated from each other such that the interlayer insulating layer (<NUM>) remains between the first hole (<NUM>) and the second hole (<NUM>, <NUM>) in a plan view,
wherein no part of the interlayer insulating layer (<NUM>) between the first hole (<NUM>) and the second hole (<NUM>, <NUM>) overlaps any part of the channel region (<NUM>) in the plan view, and wherein the insulating barrier layer (<NUM>) covers the channel region (<NUM>) so that no portion of the channel region is exposed in the first hole (<NUM>) of the interlayer insulating layer;
wherein the data conductor (<NUM>, <NUM>) is connected to and contacts the source region (<NUM>) or the drain region (<NUM>) via the second hole (<NUM>, <NUM>), and
wherein no part of the data conductor overlaps any part of the gate electrode when viewed in a plan view of the thin film transistor.