Patent Description:
Display devices may present visual information. It is generally desirable for a display device to be slim, lightweight, and energy-saving. It is also generally desirable for a display device to have a minimum non-display area and a maximum display area.

<CIT> relates to an electro-optical device. The electro-optical device includes a plurality of pixels that are arranged above a surface of a substrate, corresponding to intersections of a plurality of scanning lines and a plurality of data lines, a sampling circuit that samples image signals and supplies the sampled image signals from the data lines to the pixels when the scanning lines are selected; electrostatic protection circuits that include switching elements having first terminals and second terminals, the first terminals is electrically connected to the second terminals when an overvoltage is applied to the first terminals; static potential wiring lines that are formed on a surface of a first insulating layer covering the switching elements and are connected to the second terminals of the switching elements via contact holes of the first insulating layer, substantially constant potentials being applied to the static potential wiring lines; and image signal lines that transmit the image signals supplied to input terminals to the sampling circuit. The image signal lines include first wiring line portions formed of the same conductive film as the static potential wiring lines, the first wiring line portions being spaced apart from the static potential lines, and connected to the first terminals of the switching elements via the contact holes of the first insulating layer, and a second wiring line portion formed on a surface of a second insulating layer covering the static potential wiring lines and the first wiring line portions, connected to the first wiring line portion via contact holes of the second insulating layer, and extends to intersect with the static potential wiring lines when viewed from a direction perpendicular to the surface of the substrate.

<CIT> relates to an electrostatic protection circuit comprising an external circuit connection terminal, a video signal line, and a first electrostatic protection circuit. The first electrostatic protection circuit includes an n-type transistor and a p-type transistor. A gate and a source of the n-type transistor are connected to a low power source wiring. A drain of the n-type transistor and a drain of the p-type transistor are connected to a video signal line. A gate of the p-type transistor and a source of the p-type transistor are connected to a high potential power source wiring. A semiconductor layer of the n-type transistor is arranged to contact to a region which is going to be a source and a region which is going to be a channel, otherwise, a low concentration impurity region is arranged between a region which is going to be a source and a region which is going to be a channel.

<CIT> relates to a thin film transistor protection circuit including an outer short-circuit line formed around a pixel electrode driving thin film transistor on an array substrate, and a discharging thin film transistor having a gate electrode and a current path connected between a wiring line connected to the pixel electrode driving thin film transistor and the outer short-circuit line. The protection circuit further includes a charging circuit for charging the gate electrode of the discharging thin film transistor according to a difference in potential between the conductive and wiring lines.

<CIT> discloses a display device including a substrate, scan lines and data lines that are disposed on the substrate, and a data voltage transmission line connected to the data lines.

One or more embodiments may be related a display device with a minimum non-display area. The display device may prevent damage potentially caused by static electricity.

According to an aspect, there is provided a display device as set out in claim <NUM>. Preferred features are set out in claims <NUM> to <NUM>.

Example embodiments are described with reference to the accompanying drawings, wherein like reference numerals may refer to like elements.

Although the terms "first," "second," etc. may be used to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. A first component may be termed a second component without departing from teachings of one or more embodiments. The description of a component as a "first" component may not require or imply the presence of a second component or other components. The terms "first," "second," etc. may be used to differentiate different categories or sets of components. For conciseness, the terms "first," "second," etc. may represent "first-type (or first-set)," "second-type (or second-set)," etc., respectively.

The singular forms "a," "an," and "the" may include the plural forms as well, unless the context clearly indicates otherwise.

When a first element is referred to as being "on" a second element, the first element can be directly or indirectly on the second element. One or more intervening elements may be present between the first element and the second element.

Sizes of elements in the drawings may be exaggerated for convenience of explanation.

The term "connect" may mean "electrically connect. " The term "positioned between" may mean "substantially positioned between. " The term "positioned on the same layer" may mean "positioned on the same layer and made of the same material(s). " The term "support" may mean "mechanically support.

<FIG> is a perspective view illustrating a part of a display device according to an embodiment. <FIG> is a plan view illustrating the display device according to an embodiment. Each of <FIG> and <FIG> is an enlarged view of a part of the display device according to an embodiment.

Referring to <FIG> and <FIG>, a display device <NUM> includes a display area DA for displaying an image and includes a peripheral area PA outside the display area DA. A substrate <NUM> of the display device <NUM> includes a display area and a peripheral area PA respectively corresponding to the display area DA and the peripheral area PA.

In an electronic device including the display device <NUM>, a portion of the substrate <NUM> may be bent (or may bend) in order to minimize the area of the peripheral area PA visible to a user.

The display area DA may include a first display unit <NUM> and second through fifth display units <NUM>, <NUM>, <NUM>, and <NUM> around the first display unit <NUM>.

The first display unit <NUM> may be positioned in the center of the substrate <NUM>, may be substantially flat, and may have a polygonal shape. For example, the first display unit <NUM> may have a rectangular shape including two sides that extend in a first direction (X-direction) and two sides that extend in a second direction (Y-direction).

The second through fifth display units <NUM>, <NUM>, <NUM>, and <NUM> may extend from the first display unit <NUM>. The second through fifth display units <NUM>, <NUM>, <NUM>, and <NUM> may have curved surfaces each having a predetermined curvature radius. The second display unit <NUM> may be positioned in a first bending area BA1 that is bent with reference to a first bending line BL1 extending in the second direction at a first side (lower side) of the first display unit <NUM>. The second display unit <NUM> may include an edge display unit <NUM>' that is bent with a certain curvature and a side display unit <NUM>" that is oriented substantially perpendicular to the first display unit <NUM>. The third display unit <NUM> may be positioned in a second bending area BA2 that is bent with reference to a second bending line BL2 extending in the first direction at a second side (right side) of the first display unit <NUM>. The third display unit <NUM> may include an edge display unit <NUM>' that is bent with a certain curvature and a side display unit <NUM>" that is oriented substantially perpendicular to the first display unit <NUM>. The fourth display unit <NUM> may be positioned in a third bending area BA3 that is bent with reference to a third bending line BL3 extending in the first direction at a third side (left side) of the first display unit <NUM>. The fourth display unit <NUM> may include an edge display unit <NUM>' that is bent with a certain curvature and a side display unit <NUM>" that is oriented substantially perpendicular to the first display unit <NUM>. The fifth display unit <NUM> may be positioned in a fourth bending area BA4 that is bent with reference to a fourth bending line BL4 extending in the second direction at a fourth side (upper side) of the first display unit <NUM>. The fifth display unit <NUM> may include an edge display unit <NUM>' that is bent with a certain curvature and a side display unit <NUM>" that is oriented substantially perpendicular to the first display unit <NUM>.

The display area DA may include a round corner part <NUM>. Round corner parts <NUM> may be respectively positioned between the second display unit <NUM> and the third display unit <NUM>, between the third display unit <NUM> and the fifth display unit <NUM>, between the second display unit <NUM> and the fourth display unit <NUM>, and between the fourth display unit <NUM> and the fifth display unit <NUM>.

In a front view, there is no bezel in the edge of the display device <NUM>, and the display area DA in the front view may be maximized.

A pad area PADA is in the peripheral area PA. The pad area PADA may accommodate electronic components and/or printed circuit boards (PCBs). For example, a driving circuit unit that supplies signals to pixels PX in the display area DA may be positioned in the pad area PADA. The driving circuit unit may include a data driving unit for applying data signals to a plurality of data lines DL. The driving circuit unit may be implemented in the form of an integrated circuit chip and may be mounted on the substrate <NUM>. A plurality of pads PAD (see <FIG>) are positioned in the pad area PADA. The driving circuit unit may supply signals to the display area DA via the plurality of pads PAD. The substrate <NUM> may be bent (or may bend) in the first bending area BA1, and the driving circuit unit in the pad area PADA may overlap the display area DA. The bending direction of the pad area PADA is set so that the pad area PADA may be behind the display area DA. Thus, from the user's perspective, the display area DA takes the most part of the display device <NUM>.

Pixels PX and wires for applying electrical signals to the pixels PX are positioned in the display area DA. Each of the pixels PX includes a display element and a circuit unit for driving the display element. In an example, the display element may include an organic light-emitting diode, and the circuit unit may include a plurality of transistors and a capacitor.

The wires for applying electrical signals to the pixels PX include scan lines SL and data lines DL. The scan lines SL may be arranged in rows and may transmit scan signals to the pixels PX, and the data lines DL may be arranged in columns and may transmit data signals to the pixels PX. The pixels PX may be positioned at/near intersections of the scan lines SL and the data lines DL.

Referring to <FIG> and <FIG>, connection lines <NUM> for transmitting electrical signals supplied from the pads PAD to wires connected to the pixels PX are positioned on the substrate <NUM>. The connection lines <NUM> are positioned (and connected) between the data lines DL and the pads PAD and are configured to transmit data signals supplied from the pads PAD to the data lines DL.

The connection lines <NUM> include a first connection line <NUM>, and may further include a second connection line <NUM>, and a third connection line <NUM>. The first connection line <NUM> is substantially positioned in the display area DA, and the second connection line <NUM> and the third connection line <NUM> may be positioned in the peripheral area PA. The second connection line <NUM> and the third connection line <NUM> may be positioned in the first bending area BA1.

One end of the first connection line <NUM> is connected to the corresponding data line DL via a first contact part CNT1, and the other end of the first connection line <NUM> may be connected to the corresponding second connection line <NUM> via a second contact part CNT2. The first connection line <NUM> may extend in the first direction (+X direction), may be bent (or may bend) to extend in the second direction (Y direction) that is perpendicular to the first direction, and may be further bent (or may bend) to extend in the first direction (-X direction). One end of the second connection line <NUM> may be connected to the first connection line <NUM> via a second contact part CNT2, and the other end of the second connection line <NUM> may be connected to the corresponding pad PAD among the pads PAD. One end of the third connection line <NUM> may be connected to the corresponding data line DL via a third contact part CNT3, and the other end of the third connection line <NUM> may be connected to the corresponding pad among the pads PAD.

First connection lines <NUM> and second connection lines <NUM> connect data lines DL arranged in the third display unit <NUM> (in the second bending area BA2) and the fourth display unit <NUM> (in the fourth bending area BA4) to pads PAD in the pad area PADA. The second connection line <NUM> may be positioned in the peripheral area PA and may be indirectly connected through the first connection line <NUM> to the data line DL. Thus, the display area DA of the round corner part <NUM> between the second bending area BA2 and the first bending area BA1 and the display area DA of the round corner part <NUM> between the third bending area BA3 and the first bending area BA1 may not be reduced, and the peripheral area PA may not be enlarged. The non-display area may be minimized.

The display area DA may be partitioned into areas according to an extension direction of the first connection lines <NUM>. For example, the display area DA may include a first area S1 in which (first segments of) the first connection lines <NUM> extend in the first direction (+X direction and -X direction), a second area S2 in which (second segments of) the first connection lines <NUM> extend in the second direction (Y direction), and a third area S3 excluding the first area S1 and the second area S2. The third area S3 may accommodate no first connection lines <NUM>. The display device may include multiple first areas S1 and multiple second areas S2.

The peripheral area PA may surround the display area DA. The peripheral area PA may accommodate no pixels PX, may include the pad area PADA, and may accommodate voltage lines for supplying power for driving the display elements.

The connection lines <NUM> positioned in the peripheral area PA may be vulnerable to static electricity introduced from entities outside the display device <NUM>. In order to prevent damage, the connection lines <NUM> are connected to an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may be positioned in at least one of a portion A, a portion B, a portion E, and a portion D of the display device <NUM> indicated in <FIG>. The portion A is in the display area DA. The portions B, E, and D may be in the peripheral area PA.

<FIG> and <FIG> are plan views illustrating the portion A of <FIG> according to embodiments. <FIG> are cross-sectional views taken along a line I-I' of <FIG> according to embodiments.

In an embodiment, ESD protection circuits is positioned in the first area S1 of the display area DA. Referring to <FIG>, <FIG>, <FIG>, and <FIG>, in the first area S1, a first connection line <NUM> may extend in the first direction and includes sections <NUM> that are spaced from one another in the first direction. The first connection line <NUM> is connected to the corresponding ESD protection circuit. The ESD protection circuit includes a bridge <NUM> that electrically connects the sections <NUM>. The number of the sections <NUM> and the number of the bridges <NUM> may be configured according to lengths of the first connection lines <NUM>. <FIG> illustrates one bridge <NUM> that connects two sections <NUM> of each of the first connection lines <NUM>, and <FIG> illustrates two bridges <NUM> that connect three sections <NUM> of each of the first connection lines <NUM>. The number of contact holes C in which the bridges <NUM> connect the sections <NUM> may be configured according to embodiments.

Referring to <FIG>, a bridge <NUM> may be arranged on a layer different from a layer on which sections <NUM> are positioned, and may be electrically connected to the sections <NUM> via contact holes C.

As shown in <FIG>, a bridge <NUM> may overlap sections <NUM> of a first connection line <NUM> with at least one intervening insulating layer IL. The first connection line <NUM> may be positioned on an insulation surface <NUM> and may be positioned between the insulation surface <NUM> and the bridge <NUM>. The insulation surface <NUM> may be a top surface of an insulating layer between the substrate <NUM> and the first connection lines <NUM>.

As shown in <FIG>, a bridge <NUM> may be positioned between an insulation surface <NUM> and each of two sections <NUM> of a first connection lines <NUM>. At least one insulating layer IL may be positioned between the bridge <NUM> and each of the sections <NUM>. The bridge <NUM> may be positioned on the insulation surface <NUM>. The insulation surface <NUM> may be a top surface of an insulating layer between the substrate <NUM> and the bridges <NUM>.

<FIG> is an equivalent circuit diagram of pixels shown in <FIG> according to an embodiment.

Referring to <FIG>, pixels PX include a display element and a pixel circuit for driving the display element by receiving signals from the wires. Hereinafter, pixels PX in which an OLED is used as a display element, will be described as an example.

<FIG> illustrates the case where signal lines <NUM>, <NUM>, <NUM>, and <NUM>, an initialization voltage line <NUM> and a power supply voltage line <NUM> are provided in each pixel PX. In another embodiment, at least one of the signal lines <NUM>, <NUM>, <NUM>, and <NUM>, the initialization voltage line <NUM> or/and the power supply voltage line <NUM> may be shared in neighboring pixels.

The signal lines <NUM>, <NUM>, <NUM>, and <NUM> include a first scan line <NUM> for transmitting a first scan signal GW, a second scan line <NUM> for transmitting a second scan signal GI, an emission control line <NUM> for transmitting an emission control signal EM, and a data line <NUM> that crosses the first scan line <NUM> and transmits a data signal DATA. The second scan line <NUM> may be connected to the first scan line <NUM> in the next row or the previous row, and the second scan signal GI may be the first scan signal GW in the next row or the previous row.

The power supply voltage line <NUM> may transmit a first power supply voltage ELVDD to a first transistor T1, and the initialization voltage line <NUM> may transmit an initialization voltage VINT for initializing the first transistor T1 and a pixel electrode to each pixel PX.

The pixel circuit of each pixel PX may include transistors T1 through T7 and a capacitor Cst. First electrodes E11 through E71 and second electrodes E12 through E72 of <FIG> may be source electrodes (source regions) or drain electrodes (drain regions) according to the type (p-type or n-type) of a transistor and operation conditions thereof. The first through seventh transistors T1 through T7 may be thin-film transistors (TFTs).

A first transistor T1 may include a gate electrode G1 connected to a first electrode Cst1 of the capacitor Cst, a first electrode E11 connected to the power supply voltage line <NUM> via a fifth transistor T5, and a second electrode E12 electrically connected to a pixel electrode of the OLED via a sixth transistor T6. The first transistor T1 serves as a driving transistor and supplies a current to the OLED by receiving a data signal DATA according to a switching operation of the second transistor T2.

The second transistor T2 may include a gate electrode G2 connected to the first scan line <NUM>, a first electrode E21 connected to the data line <NUM>, and a second electrode E22 connected to the first electrode E11 of the first transistor T1. The second transistor T2 may be turned on according to the first scan signal GW received via the first scan line <NUM> and may perform a switching operation of transmitting the data signal DATA transmitted to the data line <NUM> to the first electrode E11 of the first transistor T1.

The third transistor T3 may include a gate electrode G3 connected to the first scan line <NUM>, a first electrode E31 connected to the second electrode E12 of the first transistor T1, and a second electrode E32 connected to the first electrode Cst1 of the capacitor Cst, a second electrode E42 of the fourth transistor T4, and the gate electrode G1 of the first transistor T1. The first electrode E31 is connected to the pixel electrode of the OLED via a sixth transistor T6. The third transistor T3 may be turned on according to the first scan signal GW received via the first scan line <NUM>, thereby diode-connecting the first transistor T1.

The fourth transistor T4 may include a gate electrode G4 connected to the second scan line <NUM>, a first electrode E41 connected to the initialization voltage line <NUM>, and a second electrode E42 connected to the first electrode Cst1 of the capacitor Cst, the second electrode E32 of the third transistor T3, and the gate electrode G1 of the first transistor T1. The fourth transistor T4 may be turned on according to the second scan signal GI received via the second scan line <NUM> and may transmit the initialization voltage VINT to the gate electrode G1 of the first transistor T1, thereby initializing a gate voltage of the first transistor T1.

The fifth transistor T5 may include a gate electrode G5 connected to the emission control line <NUM>, a first electrode E51 connected to the power supply voltage line <NUM>, and a second electrode E52 connected to the first electrode E11 of the first transistor T1 and the second electrode E22 of the second transistor T2.

The sixth transistor T6 may include a gate electrode G6 connected to the emission control line <NUM>, a first electrode E61 connected to the second electrode E12 of the first transistor T1 and the first electrode E31 of the third transistor T3, and a second electrode E62 connected to the pixel electrode of the OLED.

The fifth transistor T5 and the sixth transistor T6 may be turned simultaneously according to the emission control signal EM transmitted via the emission control line <NUM> and thus, a current may flow through the OLED.

The seventh transistor T7 may include a gate electrode G7 connected to the second scan line <NUM>, a first electrode E71 connected to the second electrode E62 of the sixth transistor T6 and the pixel electrode of the OLED, and a second electrode E72 connected to the initialization voltage line <NUM>. The seventh transistor T7 may be turned on according to the second scan signal GI transmitted via the second scan line <NUM> so as to initialize a voltage of the pixel electrode of the OLED. The seventh transistor T7 may be omitted.

In <FIG>, the fourth transistor T4 and the seventh transistor T7 are connected to the second scan line <NUM>. In an embodiment, the fourth transistor T4 may be connected to the second scan line <NUM>, and the seventh transistor T7 may be connected to an additional wiring and thus may be driven according to a signal to be transmitted to the wiring.

The capacitor Cst may include a first electrode Cst1 connected to the gate electrode G1 of the first transistor T1 and a second electrode Cst2 connected to the power supply voltage line <NUM>. The first electrode Cst1 of the capacitor Cst may be connected to the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4.

The OLED may include a pixel electrode and a common electrode that faces the pixel electrode. A second power supply voltage ELVSS may be applied to the common electrode. The OLED may emit light by receiving the current loled from the first transistor T1, thereby displaying an image.

<FIG> is a layout diagram illustrating pixels of the display device <NUM> according to an embodiment. The transistors illustrated in <FIG> may be TFTs and may be analogous to the transistors described with reference to <FIG>.

<FIG> illustrates a pixel PXa in the first area S1 of <FIG> and a pixel PXb in the second area S2 of <FIG>.

The pixel PXa and the pixel PXb may include wires that extend in the first direction (X-direction) and wires that extend in the second direction (Y-direction). The first scan line <NUM>, the second scan line <NUM>, the emission control line <NUM>, and the initialization voltage line <NUM> may extend in the second direction. The data line <NUM> and the power supply voltage line <NUM> may extend in the first direction.

Each of the pixel PXa and the pixel PXb may include first through seventh TFTs T1 through T7 and may include a capacitor Cst. Each of the first through seventh TFTs T1 through T7 may include a semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region, and a gate electrode positioned to correspond to the channel region and being insulated from the semiconductor layer Each of the first electrode and the second electrode of each of the transistors of <FIG> may be a source electrode (source region) or a drain electrode (drain region).

A first connection line <NUM> having a first segment that extends in the first direction (X-direction) may be positioned in the pixel PXa in the first area S1. A first connection line <NUM> having a second segment that extends in the second direction (Y-direction) may be positioned in the pixel PXb in the second area S2. The first connection line <NUM> may be positioned in an upper layer of the data line <NUM> and the power supply voltage line <NUM>. The first connection line <NUM> may be positioned in a layer between the data line <NUM>, the power supply voltage line <NUM>, and the pixel electrode.

<FIG> is a layout diagram illustrating pixels according to an embodiment. <FIG> are layout diagrams illustrating elements of the pixels of <FIG> in different layers according to one or more embodiments. <FIG> is a cross-sectional view illustrating a part of the display device of <FIG>. <FIG> illustrates a cross-section taken along a line II-II' that passes through a pixel electrode of <FIG>.

<FIG> illustrates a first pixel PX1 and a second pixel PX2 that are in or adjacent to the first area S1 of <FIG>. The first pixel PX1 and the second pixel PX2 are a pair of pixels arranged in the same row of adjacent columns. Structures of the first pixel PX1 may be analogous to structures of the second pixel PX2. Structures of the first pixel PX1 are described with reference to <FIG>.

As shown in <FIG>, a display device (e.g., the display device <NUM>) includes a substrate <NUM>.

The substrate <NUM> may include one or more flexible or bendable materials. For example, the substrate <NUM> may include polymer resin, such as polyethersulphone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate, (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate <NUM> may have a multi-layer structure including two polymer resin layers and may include an inorganic material layer (such as a silicon oxide, silicon nitride, or silicon oxynitride layer) positioned between the two polymer resin layers.

The first pixel PX1 and the second pixel PX2 may be positioned on the substrate <NUM>. A buffer layer <NUM> may be positioned on the substrate <NUM> as necessary. The buffer layer <NUM> may planarize a surface of the substrate <NUM> or may prevent an impurity from penetrating into the semiconductor layer on the substrate <NUM>. The buffer layer <NUM> may have a single layer/multi-layer structure including an inorganic insulating material, such as a silicon oxide, a silicon nitride, or a silicon oxynitride. The buffer layer <NUM> may be omitted.

The semiconductor layer may be positioned on the buffer layer <NUM>. The semiconductor layer may have various curved shapes, as shown in <FIG>. Each of the first pixel PX1 and the second pixel PX2 may include a semiconductor layer having the same shape. Hereinafter, when each layer of the first pixel PX1 and the second pixel PX2 has the same shape, this will not be described with discrimination. The semiconductor layer of each of the first through seventh TFTs T1 through T7 may include a channel region, a source region and a drain region, wherein the channel region is between the source region and the drain region.

The semiconductor layer may include a channel region 131a of the first TFT T1, a channel region 131b of the second TFT T2, channel regions 131c1 and 131c2 of the third TFT T3, channel regions 131d1 and 131d2 of the fourth TFT T4, a channel region 131e of the fifth TFT T5, a channel region 131f of the sixth TFT T6, and a channel region <NUM> of the seventh TFT T7. That is, it will be understood that each channel region of the first through seventh TFTs T1 through T7 is some of the semiconductor layer, as shown in <FIG>. The channel region 131a of the first TFT T1 may have a curvature and thus may be formed long. Thus, the driving range of a gate voltage applied to the gate electrode G1 may be increased. There may be various embodiments of the shape of the channel region 131a of the first TFT T1, including 'C'-, 'Z'-, '<IMG>'-, '<IMG>'-, 'S'-, 'M'-, and 'W'-shapes.

The semiconductor layer may include polysilicon. The semiconductor layer may include source regions and drain regions with intervening channel regions. Each of the source regions and the drain regions may be a region into which an impurity is doped. The impurity may vary according to the type of a TFT and may include an N-type impurity or a P-type impurity. A channel region, a source region in one side of the channel region, and a drain region in the other side of the channel region may be referred to as an active layer. That is, the TFT has an active layer and the active layer includes a channel region, a source region and a drain region.

As shown in <FIG>, the semiconductor layer may include a source region 176a and a drain region 177a of the first transistor T1, a source region 176b and a drain region 177b of the second transistor T2, a source region 176c and a drain region 177c of the third transistor T3, a source region 176d and a drain region 177d of the fourth transistor T4, a source region 176e and a drain region 177e of the fifth transistor T5, a source region 176f and a drain region 177f of the sixth transistor T6, and a source region <NUM> and a drain region <NUM> of the seventh transistor T7. The source region or the drain region may be interpreted as a source electrode or drain electrode of a TFT in some cases. That is, for example, each of the source electrode and the drain electrode of the first TFT T1 may be a source region 176a and a drain region 177a into which an impurity is doped, in the vicinity of the channel region 131a in the semiconductor layer shown in <FIG>.

A first insulating layer <NUM> including an inorganic insulating material, such as a silicon nitride, a silicon oxide, or a silicon oxynitride, may be on the semiconductor layer.

A gate electrode 125a of the first TFT, a gate electrode 125b of the second TFT T2, gate electrodes 125c1 and 125c2 of the third TFT T3, gate electrodes 125d1 and 125d2 of the fourth TFT T4, a gate electrode 125e of the fifth TFT T5, a gate electrode 125f of the sixth TFT T6, and a gate electrode <NUM> of the seventh TFT T7 may be positioned on the first insulating layer <NUM>. The first scan line <NUM>, the second scan line <NUM>, and the emission control line <NUM> each including the same material as a material for forming the gate electrodes of the first through seventh TFTs T1 through T7 and each being positioned on the same layer may be positioned on the first insulating layer <NUM> and extend in the second direction.

As shown in <FIG>, the gate electrode 125b of the second TFT T2 and the gate electrodes 125c1 and 125c2 of the third TFT T3 may be parts of the first scan line <NUM> that crosses the semiconductor layer or protrudes from the first scan line <NUM>, and the gate electrodes 125d1 and 125d2 of the fourth TFT T4 and the gate electrode <NUM> of the seventh TFT T7 may be parts of the second scan line <NUM> that crosses the semiconductor layer or protrudes from the second scan line <NUM>, and the gate electrode 125e of the fifth TFT T5 and the gate electrode 125f of the sixth TFT T6 may be parts of the emission control line <NUM> that crosses the semiconductor layer or protrudes from the emission control line <NUM>. The gate electrode 125a of the first TFT T1 may be of an island type.

In <FIG> and <FIG>, each of the third TFT T3 and the fourth TFT T4 has a dual gate electrode. In embodiments, each of the third TFT T3 and the fourth TFT T4 may have one gate electrode. There may be various modifications, wherein at least one of other TFTs T1, T2, T5, T6, and T7 than the third TFT T3 and the fourth TFT T4 may have a dual gate electrode.

The capacitor Cst may overlap the first TFT T1. A first electrode that is a lower electrode of the capacitor may be the gate electrode 125a of the first TFT T1. In an embodiment, the capacitor Cst may not overlap the first TFT T1, and the first electrode 125a of the capacitor Cst may be a separate independent component from the gate electrode 125a of the first TFT T1.

A second insulating layer <NUM> may be positioned on gate electrodes of the first through seventh TFTs T1 through T7. The second insulating layer <NUM> may include an inorganic insulating material, such as a silicon nitride, a silicon oxide, or a silicon oxynitride.

A second electrode <NUM> that is an upper electrode of the capacitor Cst may be positioned on the second insulating layer <NUM>. As shown in <FIG>, an opening <NUM> may be formed in the second electrode <NUM> of the capacitor Cst. A connection member <NUM> may be used to electrically connect the first electrode 125a of the capacitor Cst to the drain region 177c of the third TFT T3 via the opening <NUM>. An initialization voltage line <NUM> may be positioned on the same layer as the second electrode <NUM> of the capacitor Cst on the second insulating layer <NUM>.

A third insulating layer <NUM> may be positioned on the second electrode <NUM> of the capacitor Cst. The third insulating layer <NUM> may include an inorganic insulating material, such as a silicon nitride, a silicon oxide, or a silicon oxynitride.

A data line <NUM> and a power supply voltage line <NUM> may be positioned on the third insulating layer <NUM>. The data line <NUM> may be connected to the source region 176b of the second TFT T2 via a contact hole <NUM>, which is formed in the first insulating layer <NUM>, the second insulating layer <NUM>, and the third insulating layer <NUM>. The power supply voltage line <NUM> may be connected to the second electrode <NUM> of the capacitor Cst via a contact hole <NUM> formed in the third insulating layer <NUM> and may be connected to a lower semiconductor layer via contact holes <NUM> and <NUM>, which are formed in the first insulating layer <NUM>, the second insulating layer <NUM>, and the third insulating layer <NUM>.

The conductive layers may be further positioned on the third insulating layer <NUM>. For example, connection members <NUM>, <NUM>, and <NUM> may be formed on the third insulating layer <NUM>, as shown in <FIG>. One end of the connection member <NUM> may be connected to the initialization voltage line <NUM> via a contact hole <NUM>, which is formed in the second insulating layer <NUM> and the third insulating layer <NUM>, and the other end of the connection member <NUM> may be connected to the source region 176d of the fourth TFT T4 via the contact hole <NUM>, which is formed in the first insulating layer <NUM>, the second insulating layer <NUM>, and the third insulating layer <NUM>. One end of the connection member <NUM> may be connected to the drain region 177c of the third TFT T3 via a contact hole <NUM>, which is formed in the first insulating layer <NUM>, the second insulating layer <NUM>, and the third insulating layer <NUM>, and the other end of the connection member <NUM> may be connected to the gate electrode 125a of the first TFT T1 via a contact hole <NUM>, which is formed in the second insulating layer <NUM> and the third insulating layer <NUM>. In this case, the other end of the connection member <NUM> may be connected to the gate electrode 125a of the first TFT T1 (or the first electrode 125a of the capacitor Cst) via the opening <NUM> formed in the second electrode <NUM> of the capacitor Cst. The connection member <NUM> may be connected to the drain region 177f of the sixth TFT T6 via the contact hole <NUM>, which is formed in the first insulating layer <NUM>, the second insulating layer <NUM>, and the third insulating layer <NUM>. The connection member <NUM> may be electrically connected to the pixel electrode <NUM>.

A fourth insulating layer <NUM> may be positioned on the data line <NUM> and the power supply voltage line <NUM>. A first connection line <NUM> may be positioned on the fourth insulating layer <NUM>, as shown in <FIG>. In the first area S1, the first connection line <NUM> may include sections <NUM>, which are separated from one another. The first connection line <NUM> may have a single layer or multi-layer structure including at least one of aluminum (Al), copper (Cu), titanium (Ti), and an alloy of some of the metals. The first connection line <NUM> may extend in the first direction. The first connection line <NUM> may overlap at least some of the power supply voltage line <NUM>. The position of a gap GAP1 of the sections <NUM> of the first connection line <NUM> in the first pixel PX1 and the position of a gap GAP2 of the sections <NUM> of the first connection line <NUM> in the second pixel PX2 may be different from each other. A fifth insulating layer <NUM> may be positioned on the first connection line <NUM>.

Each of the fourth insulating layer <NUM> and the fifth insulating layer <NUM> may include general-purpose polymer, such as imide-based polymer, polymethylmethacrylate (PMMA), polystyrene (PS), a polymer derivative having a phenol-based group, acryl-based polymer, arylether-based polymer, amide-based polymer, fluorine-based polymer, p-xylene-based polymer, vinyl alcohol-based polymer, and a blend of some of the polymers.

An OLED <NUM> may be positioned on the fifth insulating layer <NUM>. The OLED <NUM> may include a pixel electrode <NUM>, an opposite electrode <NUM>, and an intermediate layer <NUM> between the pixel electrode <NUM> and the opposite electrode <NUM>.

The pixel electrode <NUM> may be a (semi-)transparent electrode or reflective electrode. When the pixel electrode <NUM> is a (semi-)transparent electrode, the pixel electrode <NUM> may include an indium tin oxide (ITO), an indium zinc oxide (IZO), a zinc oxide (ZnO), In<NUM>O<NUM>, an indium gallium oxide (IGO), or an aluminum zinc oxide (AZO). When the pixel electrode <NUM> is a reflective electrode, the pixel electrode <NUM> may have a reflective layer including silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and a compound thereof, and a layer including an ITO, an IZO, a ZnO, In<NUM>O<NUM>, an IGO, or an AZO. The pixel electrode <NUM> may have a single layer or multi-layer structure.

A shielding member <NUM> may be further positioned on the fifth insulating layer <NUM>. The shielding member <NUM> may extend in the second direction along some of the edge of the pixel electrode <NUM> not to overlap the pixel electrode in a plan view and may be positioned at an upper side or lower side of each row. The shielding member <NUM> may have the shape of a straight line that extends in the second direction or a zigzag shape according to the arrangement of the pixel electrodes <NUM> in the same row. The shielding member <NUM> may include light-shielding metal. For example, the shielding member <NUM> may include molybdenum (Mo), Al, Cu, Ti, and the like and may have a multi-layer or single layer structure including the above-described materials. In an embodiment, the shielding member <NUM> may have a multi-layer structure of Ti/AI/Ti. The shielding member <NUM> may include the same material as a material for forming the pixel electrode <NUM>. The shielding members <NUM> may be spaced from one another and independently provided in each row. The shielding members <NUM> may be floated and may be electrically connected to a constant voltage wiring, and a constant voltage may be applied to the shielding members <NUM>. The constant voltage may be an initialization voltage VINT.

As shown in <FIG> <FIG>, and <FIG>, a bridge <NUM> that electrically connects the sections <NUM> of the first connection line <NUM> may be positioned on the fifth insulating layer <NUM>. The bridge <NUM> may include the same material as a material for forming the pixel electrode <NUM> and may be positioned on the same layer as the pixel electrode <NUM>. The bridge <NUM> may electrically connect the sections <NUM> of the first connection line <NUM> arranged in a lower layer via contact holes C formed in the fifth insulating layer <NUM>. The bridge <NUM> may not overlap the pixel electrode <NUM> and the shielding member <NUM> in a direction perpendicular to the substrate <NUM>. As shown in <FIG>, the bridges <NUM> arranged in the same row may be positioned in a zigzag form in the second direction according to the arrangement of the pixel electrodes <NUM>. A virtual line IL1 that connects centers of the bridges <NUM> in the same row may not be in parallel to the first direction or the second direction. The centers of the bridges <NUM> may not be aligned. The position of the gap GAP1 of the sections <NUM> of the first connection line <NUM> arranged in the first pixel PX1 and the position of the gap GAP2 of the sections <NUM> of the first connection line <NUM> arranged in the second pixel PX2 may be determined according to positions of the bridges <NUM>.

A sixth insulating layer <NUM> that covers the end of the pixel electrode <NUM> may be positioned on the fifth insulating layer <NUM>. The sixth insulating layer <NUM> may have an opening OP for exposing a portion of the pixel electrode <NUM>, thereby defining a pixel. The sixth insulating layer <NUM> may include an organic material, such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Alternatively, the sixth insulating layer <NUM> may include one or more inorganic materials.

An intermediate layer <NUM> may be formed on the pixel electrode <NUM> exposed by the opening OP of the sixth insulating layer <NUM>. The intermediate layer <NUM> may include at least an emissive layer (EML) and may further include at least one functional layer of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). In an embodiment, the intermediate layer <NUM> may include a first functional layer arranged under the EML and/or a second functional layer arranged on the EML. The first functional layer and/or the second functional layer may include an integral layer in the entirety of the pixel electrodes <NUM>, or a layer patterned to correspond to each of the pixel electrodes <NUM>. The EML may include a red emissive layer, a green emissive layer, or a blue emissive layer. Alternatively, the EML may have a multi-layer structure in which the red emissive layer, the green emissive layer and the blue emissive layer are stacked on one another, so as to emit white light, or a single layer structure including a red emissive material, a green emissive material, and a blue emissive material.

The opposite electrode <NUM> may cover the display area (see DA of <FIG>) and may be positioned on the intermediate layer <NUM> and on an upper portion of the sixth insulating layer <NUM>. The opposite electrode <NUM> may cover some of the peripheral area (see PA of <FIG>). The opposite electrode <NUM> may include a semipermeable reflective layer including at least one selected from the group consisting of lithium (Li), calcium (Ca), lithium fluoride (LiF), Al, Mg, and Ag, or a light-transmitting metal oxide, such as ITO, IZO, or ZnO, and may have a single layer or multi-layer structure.

<FIG> is a layout diagram illustrating pixels of the display device <NUM> according to an embodiment. <FIG> are layout diagrams illustrating elements of the pixels in different layers according to one or more embodiments. <FIG> is a cross-sectional view illustrating a part of the display device of <FIG>. <FIG> illustrates a cross-section taken along a line III-III' that passes through a pixel electrode of <FIG> according to an embodiment. Some structures illustrated in one or more of <FIG> may be identical to or analogous to some structures described with reference to one or more of <FIG>, and related description may not be repeated.

As shown in <FIG> and <FIG>, a pixel (e.g., the first pixel PX1 or the second pixel PX2) may be positioned on a substrate <NUM>. Each of the first pixel PX1 and the second pixel PX2 may include first through seventh TFTs T1 through T7 and a capacitor Cst. Each of the first through seventh TFTs T1 through T7 may include a semiconductor layer and a gate electrode.

As shown in <FIG>, <FIG>, and <FIG>, a semiconductor layer of each of the first through seventh TFTs T1 through T7 may be positioned on the buffer layer <NUM>. The semiconductor layer may include a source region, a drain region, and a channel region between the source region and the drain region of each of the first through seventh TFTs T1 through T7. A first insulating layer <NUM> may be positioned on the semiconductor layer.

As shown in <FIG>, <FIG>, and <FIG>, gate electrodes of the first through seventh TFTs T1 through T7, a first scan line <NUM>, a second scan line <NUM>, and an emission control line <NUM> may be positioned on the first insulating layer <NUM>. A first electrode that is a lower electrode of the capacitor Cst may be a gate electrode 125a of the first TFT T1. A second insulating layer <NUM> may be positioned on the gate electrodes of the first through seventh TFTs T1 through T7.

As shown in <FIG>, <FIG>, and <FIG>, a second electrode <NUM> that is an upper electrode of the capacitor Cst may be positioned on the second insulating layer <NUM>. An opening <NUM> may be formed in the second electrode <NUM> of the capacitor Cst. A third insulating layer <NUM> may be positioned on the second electrode <NUM> of the capacitor Cst. An initialization voltage line <NUM> may be positioned on the same layer as the second electrode <NUM> of the capacitor Cst.

As shown in <FIG> and <FIG>, a data line <NUM> and a power supply voltage line <NUM> may be positioned on the third insulating layer <NUM>. Connection members <NUM>, <NUM>, and <NUM> may be further positioned on the third insulating layer <NUM>. A bridge <NUM> that electrically connects the sections <NUM> of the first connection line <NUM> may be further positioned on the third insulating layer <NUM>. The bridge <NUM> may include the same material as a material for forming the data line <NUM> and may be formed on the same layer as the data line <NUM>. The bridge <NUM> may not overlap the data line <NUM>, the power supply voltage line <NUM>, and the connection members <NUM>, <NUM>, and <NUM> in a direction perpendicular to the substrate <NUM>. The relative position of the bridge <NUM> in the first pixel PX1 and the relative position of the bridge <NUM> in the second pixel PX2 may be substantially the same. A virtual line IL2 that connects centers of the bridges <NUM> arranged in the same row may be parallel to the second direction. The centers of the bridges <NUM> arranged in the same row may be aligned in the second direction. A fourth insulating layer <NUM> may be positioned on the data line <NUM> and the power supply voltage line <NUM>.

As shown in <FIG> and <FIG>, sections <NUM> of the first connection line <NUM> may be positioned on the fourth insulating layer <NUM>. The first connection line <NUM> extends in the first direction. The first connection line <NUM> may overlap at least some of portions of the semiconductor layer that extend in the first direction. Each of the position of a gap GAP1 of the sections <NUM> of the first connection line <NUM> arranged in the first pixel PX1 and the position of a gap GAP2 of the sections <NUM> of the first connection line <NUM> arranged in the second pixel PX2 may correspond to positions of the lower bridges <NUM>. The sections <NUM> of the first connection line <NUM> may be electrically connected to the corresponding bridges <NUM> arranged in a lower layer via contact holes C formed in the fourth insulating layer <NUM>. A fifth insulating layer <NUM> may be positioned on the first connection line <NUM>.

As shown in <FIG> and <FIG>, an OLED <NUM> may be positioned on the fifth insulating layer <NUM>. The OLED <NUM> may include a pixel electrode <NUM>, an opposite electrode <NUM>, and an intermediate layer <NUM> between the pixel electrode <NUM> and the opposite electrode <NUM>. A shielding member <NUM> may be further positioned on the fifth insulating layer <NUM>.

A sixth insulating layer <NUM> that covers the pixel electrode <NUM> and the shielding member <NUM> may be positioned on the fifth insulating layer <NUM>. An opening OP for exposing a portion of the pixel electrode <NUM> may be formed in the sixth insulating layer <NUM>. An intermediate layer <NUM> may be formed on the pixel electrode <NUM> exposed by the opening OP of the sixth insulating layer <NUM>.

<FIG> is a plan view illustrating the portion B of <FIG> according to an embodiment. <FIG> are cross-sectional views taken along a line IV-IV' of <FIG> according to embodiments.

In an embodiment, an ESD protection circuit may be provided in a peripheral area PA, may be positioned adjacent to a boundary between a display area DA and the peripheral area PA, and may be connected to a first connection line <NUM>. Referring to <FIG>, the first connection line <NUM> may be electrically connected to the corresponding data line <NUM> (or data line DL) at a first contact part CNT1. The first connection line <NUM> may extend from the display area DA to the peripheral area PA. The first connection line <NUM> may include a first section <NUM> positioned in both the display area DA and the peripheral area PA and may include a second section <NUM> spaced from the first section <NUM> and positioned in the peripheral area PA. That is, the first section <NUM> comprises an extension part, and the extension part extends beyond the display area DA toward the pad area PADA. Each section of the first connection line <NUM> may be connected to the corresponding ESD protection circuit. The ESD protection circuit may be/include a bridge 250a that electrically connects the first section <NUM> to the second section <NUM> near the boundary between the display area DA and the peripheral area PA.

Referring to <FIG>, the bridge 250a may be positioned on a layer different from a layer on which the first section <NUM> and the second section <NUM> are positioned, and may be electrically connected to the first section <NUM> and the second section <NUM> via contact holes C.

In an embodiment, as shown in <FIG>, the first section <NUM> and the second section <NUM> of the first connection line <NUM> may be substantially positioned between the fourth insulating layer <NUM> and the fifth insulating layer <NUM>. The bridge 250a may be positioned on the fifth insulating layer <NUM>. The bridge 250a may be positioned on the same layer as the pixel electrode <NUM>. The bridge 250a may connect the first section <NUM> to the second section <NUM> via contact holes C. The second section <NUM> may be electrically connected to the corresponding data line <NUM> lower than the second section <NUM> via a contact hole C at the first contact part CNT1. The data line <NUM> may be positioned on an insulation surface <NUM> of the third insulating layer <NUM> (shown in <FIG> or <FIG>) and may be positioned between the second section <NUM> and the third insulating layer <NUM>. The first contact part CNT1 and the bridge 250a may be positioned in the peripheral area PA and may be positioned adjacent to the boundary between the display area DA and the peripheral area PA.

In an embodiment, as shown in <FIG>, the first section <NUM> and the second section <NUM> of the first connection line <NUM> may be positioned on the fourth insulating layer <NUM>. The bridge 250a may be positioned on an insulation surface <NUM> of the third insulating layer <NUM> (shown in <FIG> or <FIG>) and may be positioned between the first connection line <NUM> and the third insulating layer <NUM>. The bridge 250a may be positioned on the same layer as data line <NUM>. The bridge 250a may connect the first section <NUM> to the second section <NUM> via contact holes C. The second section <NUM> may be electrically connected to the corresponding data line <NUM> (positioned between the second section <NUM> and the third insulating layer <NUM>) via a contact hole C at the first contact part CNT1. The first contact part CNT1 and the bridge 250a may be positioned in the peripheral area PA and may be adjacent to the boundary between the display area DA and the peripheral area PA.

<FIG> is a plan view illustrating the portion E of <FIG> according to an embodiment. <FIG> and <FIG> are cross-sectional views taken along lines V-V' and VI-VI' of <FIG> according to embodiments.

In an embodiment, an ESD protection circuit may be provided in a peripheral area PA, may be positioned adjacent to a boundary between the display area DA and the peripheral area PA, and may be connected to a second connection line <NUM> and/or a third connection line <NUM> (shown in <FIG> and <FIG>). Referring to <FIG>, <FIG>, and <FIG>, the second connection line <NUM> may include sections <NUM>, which are spaced from one another in the first direction in the peripheral area PA. Each section of the second connection line <NUM> may be connected to the corresponding ESD protection circuit. The ESD protection circuit may be/include a bridge 250b that electrically connects the sections <NUM>. Similarly, the third connection line <NUM> may include sections <NUM>, which are spaced from one another in the first direction in the peripheral area PA. Each section of the third connection lines <NUM> may be connected to the corresponding ESD protection circuit. The ESD protection circuit may be/include a bridge 250c that electrically connects the sections <NUM>.

Referring to <FIG> and <FIG>, bridges 250b may be positioned on a layer different from a layer on which the sections <NUM> of the second connection line <NUM> are positioned, and may be electrically connected to the sections <NUM> of the second connection line <NUM> via contact holes C. A bridge 250c may be positioned on a layer different from a layer on which sections <NUM> of the third connection line <NUM> are positioned, and may be electrically connected to the sections <NUM> of the third connection line <NUM> via contact holes C.

In an embodiment, as shown in <FIG>, the sections <NUM> of the second connection line <NUM> and the sections <NUM> of the third connection line <NUM> may be positioned on an insulation surface <NUM> of the first insulating layer <NUM> or the second insulating layer <NUM> (shown in <FIG> or <FIG>). The third insulating layer <NUM> (and the second insulating layer <NUM>) may be substantially positioned between the second connection line <NUM> and the data line <NUM> and between the third connection line <NUM> and the data line <NUM>. The data line <NUM> may be positioned between the third insulating layer <NUM> and the fourth insulating layer <NUM>. The first connection line <NUM> may be positioned between the fourth insulating layer <NUM> and the fifth insulating layer <NUM>. The bridges 250b and 250c may be positioned on the fifth insulating layer <NUM>. The bridges 250b and 250c may be positioned on the same layer as the pixel electrode <NUM> (shown in <FIG> or <FIG>). The bridge 250b may connect the sections <NUM> of the second connection line <NUM> (positioned between the bridge 250b and the substrate <NUM>) via contact holes C. The sections <NUM> of the second connection line <NUM> may be electrically connected to the corresponding first connection line <NUM> (positioned between the sections <NUM> and the fifth insulating layer <NUM>) via a contact hole C at the second contact part CNT2. The bridge 250c may connect the sections <NUM> of the third connection line <NUM> (positioned between the bridge 250c and the substrate <NUM>) via contact holes C. The sections <NUM> of the third connection line <NUM> may be electrically connected to the data line <NUM> (positioned between the sections <NUM> and the fourth insulating layer <NUM>) via a contact holes C at a third contact part CNT3. The second contact part CNT2, the third contact part CNT3, and the bridges 250b and 250c may be positioned in the peripheral area PA and may be positioned adjacent to the boundary between the display area DA and the peripheral area PA.

In an embodiment, as shown in <FIG>, the bridges 250b and 250c may be positioned on the third insulating layer <NUM>. The bridges 250b and 250c may be positioned on the same layer as the data line <NUM>. The bridge 250b may connect the sections <NUM> of the second connection line <NUM> (positioned between the bridge 250b and the substrate <NUM>) via contact holes C. The sections <NUM> of the second connection line <NUM> may be electrically connected to the corresponding first connection line <NUM> via a contact hole C at the second contract part CNT2. The bridge 250c may connect the sections <NUM> of the third connection line <NUM> (positioned between the bridge 250c and the substrate <NUM>) via contact holes C. The sections <NUM> of the third connection line <NUM> may be electrically connected to the corresponding data line <NUM> (positioned between the sections <NUM> and the fourth insulating layer <NUM>) via a contact hole C at the third contact part CNT3. The second contact part CNT2, the third contact part CNT3, and the bridges 250b and 250c may be positioned in the peripheral area PA and positioned adjacent to the boundary between the display area DA and the peripheral area PA.

<FIG> is a plan view illustrating the portion D of <FIG> according to an embodiment. <FIG> and <FIG> are cross-sectional views taken along lines VII-VII' and VIII-VIII' of <FIG> according to embodiments.

In an embodiment, an ESD protection circuit may be provided adjacent to the pad area PADA of the peripheral area PA and may be connected to a second connection line <NUM> and/or a third connection line <NUM> (shown in <FIG> and <FIG>). Referring to <FIG>, <FIG>, and <FIG>, the second connection line <NUM> may include sections <NUM>, which are spaced from one another in the first direction in the peripheral area PA. Each section of the second connection line <NUM> may be connected to an ESD protection circuit. The ESD protection circuit may be/include bridges 250d that electrically connect the sections <NUM>. Similarly, the third connection line <NUM> may include sections <NUM>, which are spaced from one another in the first direction in the peripheral area PA. Each section of the third connection line <NUM> may be connected to an ESD protection circuit. The ESD protection circuit may be/include bridges 250e that electrically connect the sections <NUM>.

Referring to <FIG> and <FIG>, the bridge 250d may be positioned on a layer different from a layer on which the sections <NUM> of the second connection line <NUM> are positioned, and may be electrically connected to the sections <NUM> of the second connection line <NUM> via contact holes C. The bridge 250e may be positioned on a layer different from a layer on which the sections <NUM> of the third connection line <NUM> are positioned, and may be electrically connected to the sections <NUM> of the third connection line <NUM> via contact holes C.

In an embodiment, as shown in <FIG>, the sections <NUM> of the second connection line <NUM> and the sections <NUM> of the third connection line <NUM> may be positioned on an insulation surface <NUM> of the first insulating layer <NUM> or the second insulating layer <NUM> (shown in <FIG> or <FIG>). The bridges 250d and 250e may be positioned on the fifth insulating layer <NUM>. The third insulating layer <NUM>, the fourth insulating layer <NUM>, and the fifth insulating layer <NUM> (and the second insulating layer <NUM>) may be positioned between the second connection line <NUM> and the bridge 250d and between the third connection line <NUM> and the bridge 250e. The bridges 250d and 250e may be positioned on the same layer as the pixel electrode <NUM>. The bridges 250d may connect the sections <NUM> of the second connection line <NUM> (positioned between the bridge 250d and the substrate <NUM>) via contact holes C. The bridge 250e may connect the sections <NUM> of the third connection line <NUM> (positioned between the bridge 250e and the substrate <NUM>) via the contact holes C.

In an embodiment, as shown in <FIG>, the sections <NUM> of the second connection line <NUM> and the sections <NUM> of the third connection line <NUM> may be positioned on an insulation surface <NUM> of the first insulating layer <NUM> or the second insulating layer <NUM> (shown in <FIG> or <FIG>). The bridges 250d and 250e may be positioned on the third insulating layer <NUM>. The bridges 250d and 250e may be positioned on the same layer as the data line <NUM>. The third insulating layer <NUM> (and the second insulating layer <NUM>) may be positioned between the second connection line <NUM> and the bridges 250d and between the third connection line <NUM> and the bridges 250e. The bridges 250d may connect the sections <NUM> of the second connection line <NUM> (positioned between the bridges 250d and the substrate <NUM>) via contact holes C. The bridges 250e may connect the sections <NUM> of the third connection line <NUM> (positioned between the bridges 250e and the substrate <NUM>) via contact holes C.

<FIG> is a plan view illustrating a part of a display device according to an embodiment.

A display device <NUM>' shown in <FIG> has first through third bending areas BA1, BA2, and BA3. The display device <NUM>' may include features that are analogous to or identical to some of the above-described features. The third and fourth display units <NUM> and <NUM> may extend from the first display unit <NUM>. Each of the third display unit <NUM> and the fourth display unit <NUM> may include an edge display unit and a side display unit. Analogous to features shown in <FIG> and <FIG>, a first connection line <NUM> may be positioned in the display area DA of the display device <NUM>', and a second connection line <NUM> and a third connection line <NUM> may be positioned in the peripheral area PA of the first bending area BA1 of the display device <NUM>'. The first connection line <NUM>, the second connection line <NUM>, and the third connection line <NUM> may be connected to at least one ESD protection circuit, analogous to features described above.

Embodiments provide a display device according to appended claim <NUM>.

Preferred embodiments are defined in the appended dependent claims.

Claim 1:
A display device (<NUM>) comprising:
a substrate (<NUM>) comprising a display area (DA) and a peripheral area (PA), wherein a display element is on the display area (DA), and the peripheral area (PA) is positioned outside the display area (DA) and comprises a pad area (PADA),
a data line (DL) on the display area (DA);
a pad (PAD) on the pad area (PADA);
a first connection line (<NUM>) partly on the display area (DA) and electrically connected to the data line (DL) and the pad (PAD), and configured to transmit a signal from the pad (PAD) to the data line (DL),
wherein the first connection line (<NUM>) is electrically connected to the data line (DL) via a contact part (CNT1); and characterised by
an electrostatic discharge protection circuit electrically connected to the first connection line (<NUM>), and
wherein the first connection line (<NUM>) comprises a first section (<NUM>) and a second section (<NUM>),
the electrostatic discharge protection circuit comprises a first bridge (<NUM>) in the display area (DA), and
the first section (<NUM>) is spaced from the second section (<NUM>) in an extension direction of the first connection line (<NUM>) and is electrically connected through the first bridge (<NUM>) to the second section (<NUM>).