Patent Description:
With the advancement of information-oriented society, various requirements for display devices for displaying an image are increasing. Therefore, various display devices such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, organic light emitting display devices, etc. are being used recently.

As a type of display device, organic light emitting display devices are self-emitting display devices and are better in viewing angle and contrast ratio than LCD devices. Also, since the organic light emitting display devices do not need a separate backlight, it is possible to lighten and make thin the organic light emitting display devices, and the organic light emitting display devices are excellent in power consumption. Furthermore, the organic light emitting display devices are driven with a low direct current (DC) voltage, have a fast response time, and are low in manufacturing cost.

The organic light emitting display devices each include a plurality of pixels each including an organic light emitting device. In the organic light emitting device of <CIT>, a bank divides the pixels for defining the pixels. The bank may act as a pixel defining layer. The organic light emitting device includes an anode electrode, a hole transporting layer, an organic light emitting layer, and an electron transporting layer, and a cathode electrode. In this instance, when a high-level voltage is applied to the anode electrode and a low-level voltage is applied to the cathode electrode, a hole and an electron respectively move to the organic light emitting layer through the hole transporting layer and the electron transporting layer and are combined with each other in the organic light emitting layer to emit light.

The organic light emitting device includes a red organic light emitting device emitting red light, a green organic light emitting device emitting green light, and a blue organic light emitting device emitting blue light, or include only a white organic light emitting device emitting white light. If the organic light emitting device includes the white organic light emitting device, the organic light emitting layer and the cathode electrode may be provided in the pixels in common. That is, the organic light emitting layer and the cathode electrode may be connected to each other between adjacent pixels.

In order to enhance a color reproduction rate and emission efficiency, the white organic light emitting device may be provided in a tandem structure of two or more stacks where two or more organic light emitting layers are stacked. The tandem structure of two or more stacks needs a charge generating layer disposed between adjacent organic light emitting layers. However, in a structure where the organic light emitting layer and the cathode electrode are connected to each other between adjacent pixels, a current can be leaked from one pixel to an adjacent pixel due to the charge generating layer. That is, the adjacent pixel is affected by the leaked current. In this instance, the adjacent pixel cannot emit desired light due to the leaked current, causing a reduction in a color reproduction rate. Particularly, in high-resolution small display devices applied to virtual reality (VR) devices, smartphones, etc., an interval between pixels is narrow, and for this reason, the adjacent pixel is more affected by the leaked current.

<CIT> describes an organic light emitting display device that includes an anode electrode on a substrate; an organic emitting layer on the anode electrode; a cathode electrode on the organic emitting layer; an auxiliary electrode electrically connected with the cathode electrode; and a contact electrode that is on a same layer as the auxiliary electrode, the contact electrode horizontally spaced apart from the auxiliary electrode, the contact electrode directly connected with both the auxiliary electrode and the cathode electrode to connect together the auxiliary electrode and a portion of the cathode electrode that is on a same layer as the auxiliary electrode.

<CIT>l describes a display device in which variations in luminance due to variations in characteristics of transistors are reduced, and image quality degradation due to variations in resistance values is prevented. The invention comprises a transistor whose channel portion is formed of an amorphous semiconductor or an organic semiconductor, a connecting wiring connected to a source electrode or a drain electrode of the transistor, a light emitting element having a laminated structure which includes a pixel electrode, an electro luminescent layer, and a counter electrode, an insulating layer surrounding an end portion of the pixel electrode, and an auxiliary wiring formed in the same layer as a gate electrode of the transistor, a connecting wiring, or the pixel electrode. Further, the connecting wiring is connected to the pixel electrode, and the auxiliary wiring is connected to the counter electrode via an opening portion provided in the insulating layer.

Accordingly, the present disclosure is directed to provide an organic light emitting display device and a method of manufacturing the same that substantially address one or more problems due to limitations and disadvantages of the related art.

The present disclosure concerns an organic light emitting display device and a method of manufacturing the same, in which in a white organic light emitting device, an adjacent pixel is prevented from being affected by a leakage current.

Aspects of the present disclosure are defined in the appended claims.

Additional advantages and features of the disclosure will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the disclosure. The objectives and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

It is to be understood that both the foregoing general description and the following detailed description are by way of example, and intended to provide further explanation of the disclosure.

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments and, together with the description, merely serve to explain the principles of the disclosure. In the drawings:.

Reference will now be made in detail to the example, examples of which are illustrated in the accompanying drawings.

Advantages and features of the present disclosure, and implementation methods thereof, will be clarified through the following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing the embodiments are merely an example, and thus, the present disclosure is not limited to the illustrated details. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted.

In instances where 'comprise', 'have', and 'include' are used in the present specification, another part may be added unless 'only' is used. The terms of a singular form may include plural forms unless referred to the contrary.

In describing a position relationship, for example, when a position relation between two parts is described as 'on~', 'over~', 'under~', and 'next~', one or more other parts may be disposed between the two parts unless 'just' or 'direct' is used.

In describing a time relationship, for example, when the temporal order is described as 'after~', 'subsequent~', 'next~', and 'before~', an instance which is not continuous may be included unless 'just' or 'direct' is used.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms.

An X axis direction, a Y axis direction, and a Z axis direction should not be construed as only a geometric relationship where a relationship therebetween is vertical, and may denote having a broader directionality within a scope where elements of the present disclosure operate functionally.

The term "at least one" should be understood as including any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of a first item, a second item, and a third item" denotes the combination of all items proposed from two or more of the first item, the second item, and the third item as well as the first item, the second item, or the third item.

Features of various embodiments may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The embodiments may be carried out independently from each other, or may be carried out together in a co-dependent relationship.

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

<FIG> is a perspective view illustrating an organic light emitting display device <NUM> according to an embodiment. <FIG> is a plan view illustrating a first substrate, a gate driver, a source drive integrated circuit (IC), a flexible film, a circuit board, and a timing controller of <FIG>.

Referring to <FIG>, the organic light emitting display device <NUM> according to an embodiment may include a display panel <NUM>, a gate driver <NUM>, a source drive IC <NUM>, a flexible film <NUM>, a circuit board <NUM>, and a timing controller <NUM>.

The display panel <NUM> may include a first substrate <NUM> and a second substrate <NUM>. The second substrate <NUM> may be an encapsulation substrate. The first substrate <NUM> and the second substrate <NUM> may each be plastic, glass, or the like.

A plurality of gate lines, a plurality of data lines, and a plurality of pixels may be provided on one surface of the first substrate <NUM> facing the second substrate <NUM>. The pixels may be respectively provided in a plurality of areas defined by an intersection structure of the gate lines and the data lines.

Each of the pixels may include a thin film transistor (TFT) and an organic light emitting device which includes a first electrode, an organic light emitting layer, and a second electrode. When a gate signal is input through a gate line, each of the pixels may supply a certain current to the organic light emitting device by using the TFT according to a data voltage supplied through a data line. Therefore, the organic light emitting device of each of the pixels may emit light having certain brightness according to the certain current. A structure of each of the pixels will be described in detail with reference to <FIG>.

The display panel <NUM>, as illustrated in <FIG>, may be divided into a display area DA, where the pixels are provided to display an image, and a non-display area NDA which does not display an image. The gate lines, the data lines, and the pixels may be provided in the display area DA. The gate driver <NUM> and a plurality of pads may be provided in the non-display area NDA.

The gate driver <NUM> may sequentially supply gate signals to the gate lines according to a gate control signal input from the timing controller <NUM>. The gate driver <NUM> may be provided in the non-display area NDA outside one side or both sides of the display area DA of the display panel <NUM> in a gate driver-in panel (GIP) type. Alternatively, the gate driver <NUM> may be manufactured as a driving chip and may be mounted on a flexible film, and moreover, may be attached on the non-display area NDA outside the one side or the both sides of the display area DA of the display panel <NUM> in a tape automated bonding (TAB) type.

The source drive IC <NUM> may receive digital video data and a source control signal from the timing controller <NUM>. The source driver IC <NUM> may convert the digital video data into analog data voltages according to the source control signal and may respectively supply the analog data voltages to the data lines. If the source drive IC <NUM> is manufactured as a driving chip, the source drive IC <NUM> may be mounted on the flexible film <NUM> in a chip-on film (COF) type or a chip-on plastic (COP) type.

A plurality of pads such as data pads may be provided in the non-display area NDA of the display panel <NUM>. Lines connecting the pads to the source drive IC <NUM> and lines connecting the pads to lines of the circuit board <NUM> may be provided on the flexible film <NUM>. The flexible film <NUM> may be attached to the pads by using an anisotropic conductive film, and thus, the pads may be connected to the lines of the flexible film <NUM>.

The circuit board <NUM> may be attached to the flexible film <NUM> which is provided in plurality. A plurality of circuits implemented as driving chips may be mounted on the circuit board <NUM>. For example, the timing controller <NUM> may be mounted on the circuit board <NUM>. The circuit board <NUM> may be a printed circuit board (PCB) or a flexible printed circuit board (FPCB).

The timing controller <NUM> may receive the digital video data and a timing signal from an external system board through a cable of the circuit board <NUM>. The timing controller <NUM> may generate a gate control signal for controlling an operation timing of the gate driver <NUM> and a source control signal for controlling the source drive IC <NUM> which is provided in plurality, based on the timing signal. The timing controller <NUM> may supply the gate control signal to the gate driver <NUM> and may supply the source control signal to the plurality of source drive ICs <NUM>.

<FIG> is a plan view illustrating an example where a hole and emissive areas of pixels are arranged in a display area. In <FIG>, for convenience of description, only a hole H and emissive areas RE, GE, BE, and WE of pixels are illustrated.

Each of the pixels may include one emissive area. The emissive area may denote an area where a first electrode corresponding to an anode electrode, an organic light emitting layer, and a second electrode corresponding to a cathode electrode are sequentially stacked, and a hole from the first electrode and an electron from the second electrode are combined with each other in the organic light emitting layer to emit light. The first electrode is connected to a thin film transistor through a contact hole CT2. The contact hole CT2 is between each emissive area and the hole H.

The emissive area may be divided into a red emissive area RE which emits red light by using a red color filter, a green emissive area GE which emits green light by using a green color filter, a blue emissive area BE which emits blue light by using a blue color filter, and a white emissive area WE which emits white light without a color filter. A pixel including the red emissive area RE, a pixel including the green emissive area GE, a pixel including the blue emissive area BE, and a pixel including the white emissive area WE may be defined as one unit pixel.

The hole H may be disposed to surround each of the emissive areas RE, GE, BE, and WE as in <FIG>. Alternatively, as in <FIG>, the hole H may be disposed between two adjacent emissive areas of the emissive areas RE, GE, BE, and WE. For this reason, an organic light emitting layer of one pixel may not be connected to an organic light emitting layer of another pixel adjacent to the one pixel. Accordingly, according to an embodiment, a current is prevented from being leaked from one pixel to another pixel adjacent thereto due to a hole transporting layer and/or a charge generating layer of an organic light emitting layer. That is, according to an embodiment, the other pixel adjacent to the one pixel is prevented from being affected by the current leaked from the one pixel.

<FIG> is a cross-sectional view illustrating an example taken along line I-I' of <FIG>.

Referring to <FIG>, a buffer layer may be formed on one surface of the first substrate <NUM> facing the second substrate <NUM>. The buffer layer may be formed on the one surface of the first substrate <NUM>, for protecting a plurality of TFTs <NUM> and a plurality of organic light emitting devices <NUM> from water which penetrates through the first substrate <NUM> vulnerable to penetration of water. The buffer layer may include a plurality of inorganic layers which are alternately stacked. For example, the buffer layer may be formed of a multilayer where one or more inorganic layers of silicon oxide (SiOx), silicon nitride (SiNx), and SiON are alternately stacked. The buffer layer may be omitted.

The TFTs <NUM> may be formed on the buffer layer. Each of the TFTs <NUM> may include an active layer <NUM>, a gate electrode <NUM>, a source electrode <NUM>, and a drain electrode <NUM>. In <FIG>, the TFTs <NUM> are by example illustrated as being formed in a top gate type where the gate electrode <NUM> is disposed on the active layer <NUM>, but is not limited thereto. In other embodiments, the TFTs <NUM> may be formed in a bottom gate type where the gate electrode <NUM> is disposed under the active layer <NUM> or a double gate type where the gate electrode <NUM> is disposed both on and under the active layer <NUM>.

The active layer <NUM> may be formed on the buffer layer. The active layer <NUM> may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. A light blocking layer for blocking external light incident on the active layer <NUM> may be formed between the buffer layer and the active layer <NUM>.

A gate insulation layer <NUM> may be formed on the active layer <NUM>. The gate insulation layer <NUM> may be formed of an inorganic layer, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

The gate electrode <NUM> and a gate line may be formed on the gate insulation layer <NUM>. The gate electrode <NUM> and the gate line may each be formed of a single layer or a multilayer which includes one of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

An interlayer dielectric <NUM> may be formed on the gate electrode <NUM> and the gate line. The interlayer dielectric <NUM> may be formed of an inorganic layer, for example, SiOx, SiNx, or a multilayer thereof.

The source electrode <NUM>, the drain electrode <NUM>, and a data line may be formed on the interlayer dielectric <NUM>. Each of the source electrode <NUM> and the drain electrode <NUM> may contact the active layer <NUM> through a corresponding contact hole CT1 which passes through the gate insulation layer <NUM> and the interlayer dielectric <NUM>. The source electrode <NUM>, the drain electrode <NUM>, and the data line may each be formed of a single layer or a multilayer which includes one of Mo, Cr, Ti, Ni, Nd, and Cu, or an alloy thereof.

A passivation layer <NUM> for insulating the TFTs <NUM> may be formed on the source electrode <NUM>, the drain electrode <NUM>, and the data line. The passivation layer <NUM> may be formed of an inorganic layer, for example, SiOx, SiNx, or a multilayer thereof.

A planarization layer <NUM> for planarizing a step height caused by the TFTs <NUM> may be formed on the passivation layer <NUM>. The planarization layer <NUM> may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and/or the like.

An organic light emitting device <NUM> and a pixel defining layer <NUM> are formed on the planarization layer <NUM>. The organic light emitting device <NUM> includes a first electrode <NUM>, an organic light emitting layer <NUM>, and a second electrode <NUM>. The first electrode <NUM> may be an anode electrode, and the second electrode <NUM> may be a cathode electrode.

The first electrode <NUM> may be formed on the planarization layer <NUM>. The first electrode <NUM> may be connected to the source electrode <NUM> or the drain electrode <NUM> of the TFT <NUM> through a contact hole CT2 which passes through the passivation layer <NUM> and the planarization layer <NUM>. The first electrode <NUM> may be formed of a metal material, having a high reflectivity, such as a stacked structure (Ti/Al/Ti) of aluminum (Al) and titanium (Ti), a stacked structure (ITO/Al/ITO) of Al and ITO, an APC alloy, a stacked structure (ITO/APC/ITO) of an APC alloy and ITO, and/or the like. The APC alloy may be an alloy of Ag, palladium (Pd), and Cu.

The hole H is provided in the planarization layer. That is, the hole H is a recessed portion of the planarization layer <NUM>. The hole H is formed between adjacent first electrodes <NUM>. As in <FIG>, a width W1 of the hole H is set wider than a distance D between the adjacent first electrodes <NUM>. That is, the hole H may be formed in a pot shape where a width of a floor is wider than that of an entrance. Alternatively (in an embodiment not forming part of the claimed invention), as in <FIG>, a width W2 of the hole H may be set equal to or narrower than the distance D between the adjacent first electrodes <NUM>. The hole H may be formed in a form of a trench. The hole H may be generally defined as an interruption, a disconnection, or a cut.

A pixel defining layer <NUM> is formed on a portion of the first electrode <NUM> and in the hole H. For example, the pixel defining layer <NUM> may be formed on the first electrode <NUM> in the contact hole CT2, and on the first electrode <NUM> between the contact hole CT2 and the hole H. An emissive area EA is defined as an area where the first electrode <NUM>, the organic light emitting layer <NUM>, and the second electrode <NUM> are sequentially stacked to emit light. The first electrode <NUM>, the organic light emitting layer <NUM>, and the second electrode <NUM> are sequentially stacked in an area where the pixel defining layer <NUM> is not provided. Accordingly, the pixel defining layer <NUM> may divide the emissive area EA to define the emissive area EA for each pixel.

The pixel defining layer <NUM> may be formed in an atomic layer deposition (ALD) process or an initiated chemical vapor deposition (iCVD) process. If the pixel defining layer <NUM> is formed in the ALD process, the pixel defining layer <NUM> may be formed to have a thickness of about <NUM> µm to <NUM> µm, and if the pixel defining layer <NUM> is formed in the iCVD process, the pixel defining layer <NUM> may be formed to have a thickness of about <NUM> µm to <NUM> µm. That is, the pixel defining layer <NUM> may be formed to fill a portion, instead of a whole portion, of the hole H and may be formed to divide the emissive area EA.

Moreover, a layer formed by the ALD process or the iCVD process is good in step coverage characteristic, and thus, even when the width W1 of the hole H is set wider than the distance D between the adjacent first electrodes <NUM> as in <FIG>, the pixel defining layer <NUM> may be formed on both a sidewall and a floor of the hole H. Particularly, the pixel defining layer <NUM> may also be formed under the first electrode <NUM>. The step coverage denotes that a layer deposited by a deposition process is continuously connected without being disconnected even in a portion where a step height is formed.

The organic light emitting layer <NUM> may be formed on the first electrode <NUM> and the pixel defining layer <NUM>. The organic light emitting layer <NUM> may be a white light emitting layer emitting white light. In this instance, the organic light emitting layer <NUM> may be formed in a tandem structure of two or more stacks. The two or more stacks may each include a hole transporting layer, at least one light emitting layer, and an electron transporting layer. That is, the organic light emitting layer <NUM> may include the hole transporting layer, the at least one light emitting layer, and the electron transporting layer.

Moreover, a charge generating layer may be formed between adjacent stacks. The charge generating layer may include an n-type charge generating layer, disposed adjacent to a lower stack, and a p-type charge generating layer which is formed on the n-type charge generating layer and is disposed adjacent to an upper stack. The n-type charge generating layer may inject an electron into the lower stack, and the p-type charge generating layer may inject a hole into the upper stack. The n-type charge generating layer may be formed of an organic layer which is doped with alkali metal, such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs), or alkali earth metal such as magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra). The p-type charge generating layer may be an organic layer which is formed by doping a dopant on an organic host material having an ability to transport holes.

The organic light emitting layer <NUM> may be formed in a deposition process or a solution process, and if the organic light emitting layer <NUM> is formed in the deposition process, the organic light emitting layer <NUM> may be formed in an evaporation process. A layer formed in the evaporation process is not good in step coverage characteristic.

Therefore, if the width W1 of the hole H is set wider than the distance D between the adjacent first electrodes <NUM> as in <FIG>, the organic light emitting layer <NUM> may be disconnectedly formed in the hole H. That is, since the organic light emitting layer <NUM> is formed in the deposition process which is not good in step coverage characteristic, the organic light emitting layer <NUM> may be formed on only the floor of the hole H without being formed on the sidewall of the hole H.

Alternatively (in an embodiment not forming part of the claimed invention), if the width W2 of the hole H is set equal to or narrower than the distance D between the adjacent first electrodes <NUM> as in <FIG>, a thickness of the organic light emitting layer <NUM> on the sidewall of the hole H may be set thinner than that of the organic light emitting layer <NUM> on the floor of the hole H. That is, since an angle "θ" of the sidewall of the hole H is large and the organic light emitting layer <NUM> is formed in the deposition process which is not good in step coverage characteristic, the organic light emitting layer <NUM> may be formed thinner on the sidewall of the hole H than the floor of the hole H.

As a result, since the organic light emitting layer <NUM> is disconnectedly formed in the hole H due to a step height caused by the hole H, an organic light emitting layer of one pixel may not be connected to an organic light emitting layer of another pixel adjacent to the one pixel. Alternatively, since a thickness of the organic light emitting layer <NUM> on the sidewall of the hole H is set thinner than that of the organic light emitting layer <NUM> on the floor of the hole H, a resistance of the organic light emitting layer <NUM> increases between adjacent pixels. Therefore, according to an embodiment, the amount of current leaked from one pixel to another pixel adjacent thereto due to the hole transporting layer and/or the charge generating layer of the organic light emitting layer <NUM> is minimized. Accordingly, according to an embodiment, the other pixel adjacent to the one pixel is prevented from being affected by the current leaked from the one pixel.

The angle "θ" of the sidewall of the hole H may be set to <NUM> degrees or more, but an embodiment is not limited thereto. That is, the angle "θ" of the sidewall of the hole H may be set to a degree to which since the organic light emitting layer <NUM> is formed thinner on the sidewall than the floor of the hole H, the resistance of the organic light emitting layer <NUM> increases, and thus, another pixel adjacent to one pixel is prevented from being affected by a leakage current leaked from the one pixel. For example, the angle "θ" of the sidewall of the hole H may be set to <NUM> degrees in an instance where even when the angle "θ" of the sidewall of the hole H is <NUM> degrees, the resistance of the organic light emitting layer <NUM> increases, and thus, another pixel adjacent to one pixel is prevented from being affected by a leakage current leaked from the one pixel.

The second electrode <NUM> is formed on the organic light emitting layer <NUM>. The second electrode <NUM> may be formed of a transparent conductive material (or TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO) capable of transmitting light, or a semi-transmissive conductive material such as Mg, Ag, or an alloy of Mg and Ag. A capping layer may be formed on the second electrode <NUM>.

The second electrode <NUM> may be formed in a physical vapor deposition (PVD) process such as a sputtering process. A layer formed in the PVD process such as the sputtering process is good in step coverage characteristic. Accordingly, the second electrode <NUM> may be continuously connected without being disconnected despite a step height caused by the hole H.

An encapsulation layer <NUM> is formed on the second electrode <NUM>. The encapsulation layer <NUM> may be formed to fill the contact hole CT2 and the hole H. That is, in order for the organic light emitting layer <NUM> to be disconnected in the hole H due to the step height caused by the hole H, the pixel defining layer <NUM> may be thinly formed by the ALD process or the iCVD process. Therefore, the hole H may be filled not by the pixel defining layer <NUM> but by the encapsulation layer <NUM>.

The encapsulation layer <NUM> prevents oxygen or water from penetrating into the organic light emitting layer <NUM> and the second electrode <NUM>. To this end, the encapsulation layer <NUM> may include at least one inorganic layer and at least one organic layer.

For example, the encapsulation layer <NUM> may include a first inorganic layer, an organic layer, and a second inorganic layer. In this instance, the first inorganic layer may be formed on the second electrode <NUM> to cover the second electrode <NUM>. The organic layer may be formed on the first inorganic layer to cover the first inorganic layer. The organic layer may be formed to have a sufficient thickness for preventing particles from penetrating into the organic light emitting layer <NUM> and the second electrode <NUM> via the first inorganic layer. The second inorganic layer may be formed on the organic layer to cover the organic layer.

The first and second inorganic layers may each be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, and/or the like. The organic layer may be formed of acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and/or the like.

A plurality of color filters <NUM> and <NUM> and a black matrix <NUM> may be formed on one surface of the second substrate <NUM> facing the first substrate <NUM>. A red color filter <NUM> may be formed in a red emissive area RE, a green color filter <NUM> may be formed in a green emissive area GE, and a blue color filter may be formed in a blue emissive area. The emissive area EA illustrated in <FIG> and <FIG> may be the red emissive area RE.

The black matrix <NUM> may be disposed between the color filters <NUM> and <NUM>. The black matrix <NUM> may be provided in a non-emissive area instead of the emissive area EA, and thus, may be disposed to overlap the pixel defining layer <NUM>.

The encapsulation layer <NUM> of the first substrate <NUM> may be adhered to the color filters <NUM> and <NUM> of the second substrate <NUM> by using an adhesive layer <NUM>, and thus, the first substrate <NUM> may be bonded to the second substrate <NUM>. The adhesive layer <NUM> may be a transparent adhesive resin.

As described above, in an embodiment, the hole H corresponding to the recessed portion of the planarization layer <NUM> may be formed between adjacent first electrodes <NUM>, and the pixel defining layer <NUM> may be thinly formed by the ALD process or the iCVD process. As a result, according to an embodiment, since the hole H is not filled with the pixel defining layer <NUM>, the organic light emitting layer <NUM> may be formed with an interruption between light emitting layers <NUM> of first and second emissive areas that are separated by the hole H. The interruption may comprise an electrical disconnection or an increased resistance. In particular, the organic light emitting layer <NUM> may be disconnected in the hole H due to a step height caused by the hole H, or may be thinly formed on the sidewall of the hole H. Therefore, according to an embodiment, the amount of current leaked from one pixel to another pixel adjacent thereto due to the hole transporting layer and/or the charge generating layer of the organic light emitting layer is minimized. Accordingly, according to an embodiment, the other pixel adjacent to the one pixel is prevented from being affected by the current leaked from the one pixel.

<FIG> is a cross-sectional view illustrating another example (not forming part of the claimed invention) taken along line I-I' of <FIG>.

Except for pixel defining layer <NUM>, the organic light emitting display device illustrated in <FIG> is substantially as described above with reference to <FIG> and <FIG>. In <FIG>, therefore, detailed descriptions of elements other than the pixel defining layer <NUM> are omitted.

Referring to <FIG>, the pixel defining layer <NUM> may be only formed on the first electrode <NUM> in the contact hole CT2 and in the hole H. Therefore, an emissive area EA where a first electrode <NUM>, an organic light emitting layer <NUM>, and a second electrode <NUM> are sequentially stacked may be provided outside both sides of the contact hole CT2, and thus, an area of the emissive area EA may increase. Accordingly, the area of the emissive area EA is enlarged in the organic light emitting display device of <FIG> than the organic light emitting display device illustrated in <FIG> and <FIG>, and thus, an emission efficiency of an organic light emitting device is enhanced.

<FIG> is a flowchart illustrating a method of manufacturing an organic light emitting display device according to an embodiment. <FIG> are cross-sectional views taken along line I-I' of <FIG> for describing a method of manufacturing an organic light emitting display device according to an embodiment. The cross-sectional views illustrated in <FIG> relate to the method of manufacturing the organic light emitting display device illustrated in <FIG>, and thus, like reference numerals refer to like elements. Hereinafter, a method of manufacturing an organic light emitting display device according to an embodiment o will be described in detail with reference to <FIG> and <FIG>.

First, as in <FIG>, a TFT <NUM> and a planarization layer <NUM> may be formed, and a first electrode <NUM> may be formed on the planarization layer <NUM>.

Before the TFT <NUM> is formed, a buffer layer may be formed on a first substrate <NUM>, for protecting the TFT <NUM> from water penetrating through a substrate <NUM>. The buffer layer may include a plurality of inorganic layers which are alternately stacked, for protecting the TFT <NUM> and an organic light emitting device <NUM> from water which penetrates through the first substrate <NUM> vulnerable to penetration of water. For example, the buffer layer may be formed of a multilayer where one or more inorganic layers of silicon oxide (SiOx), silicon nitride (SiNx), and SiON are alternately stacked. The buffer layer may be formed by using a chemical vapor deposition (CVD) process.

Subsequently, an active layer <NUM> of the TFT <NUM> may be formed on the buffer layer. In detail, an active metal layer may be formed all over the buffer layer by using a sputtering process, a metal organic chemical vapor (MOCVD) process, and/or the like. Subsequently, the active layer <NUM> may be formed by patterning the active metal layer through a mask process using a photoresist pattern. The active layer <NUM> may be formed of a silicon-based semiconductor material, an oxide-based semiconductor material, and/or the like.

Subsequently, a gate insulation layer <NUM> may be formed on the active layer <NUM>. The gate insulation layer <NUM> may be formed of an inorganic layer, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

Subsequently, a gate electrode <NUM> of the TFT <NUM> may be formed on the gate insulation layer <NUM>. In detail, a first metal layer may be formed all over the gate insulation layer <NUM> by using a sputtering process, an MOCVD process, and/or the like. Subsequently, the gate electrode <NUM> may be formed by patterning the first metal layer through a mask process using a photoresist pattern. The gate electrode <NUM> may be formed of a single layer or a multilayer which includes one of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

Subsequently, an interlayer dielectric <NUM> may be formed on the gate electrode <NUM>. The interlayer dielectric <NUM> may be formed of an inorganic layer, for example, SiOx, SiNx, or a multilayer thereof.

Subsequently, a plurality of contact holes CT1 which pass through the gate insulation layer <NUM> and the interlayer dielectric <NUM> to expose the active layer <NUM> may be formed.

Subsequently, a source electrode <NUM> and a drain electrode <NUM> of the TFT <NUM> may be formed on the interlayer dielectric <NUM>. In detail, a second metal layer may be formed all over the interlayer dielectric <NUM> by using a sputtering process, an MOCVD process, and/or the like. Subsequently, the source electrode <NUM> and the drain electrode <NUM> may be formed by patterning the second metal layer through a mask process using a photoresist pattern. Each of the source electrode <NUM> and the drain electrode <NUM> may contact the active layer <NUM> through a corresponding contact hole CT1 which passes through the gate insulation layer <NUM> and the interlayer dielectric <NUM>. The source electrode <NUM> and the drain electrode <NUM> may each be formed of a single layer or a multilayer which includes one of Mo, Cr, Ti, Ni, Nd, and Cu, or an alloy thereof.

Subsequently, a passivation layer <NUM> may be formed on the source electrode <NUM> and the drain electrode <NUM> of the TFT <NUM>. The passivation layer <NUM> may be formed of an inorganic layer, for example, SiOx, SiNx, or a multilayer thereof. The passivation layer <NUM> may be formed by using a CVD process.

Subsequently, a planarization layer <NUM> for planarizing a step height caused by the TFT <NUM> is formed on the passivation layer <NUM>. The passivation layer <NUM> may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and/or the like.

Subsequently, a first electrode <NUM> of the organic light emitting device <NUM> is formed on the planarization layer <NUM>. In detail, a third metal layer may be formed all over the planarization layer <NUM> by using a sputtering process, an MOCVD process, and/or the like. Subsequently, the first electrode <NUM> may be formed by patterning the third metal layer through a mask process using a photoresist pattern. The first electrode <NUM> may be connected to the source electrode <NUM> of the TFT <NUM> through a contact hole CT2 which passes through the passivation layer <NUM> and the planarization layer <NUM>. The first electrode <NUM> may be formed of a metal material, having a high reflectivity, such as a stacked structure (Ti/Al/Ti) of aluminum (Al) and titanium (Ti), a stacked structure (ITO/Al/ITO) of Al and ITO, an APC alloy, a stacked structure (ITO/APC/ITO) of an APC alloy and ITO, and/or the like (S101 of <FIG>).

Second, as in <FIG>, a hole H corresponding to a recessed portion of the planarization layer <NUM> is formed between adjacent first electrodes <NUM>. In detail, by dry-etching the planarization layer <NUM> with the first electrodes <NUM> as a mask, the hole H corresponding to the recessed portion of the planarization layer <NUM> is formed between the adjacent first electrodes <NUM>. A material applied to the dry-etching may be O<NUM> or a mixed gas of O<NUM> and CF<NUM>.

As in <FIG>, a width W1 of the hole H is set wider than a distance D between the adjacent first electrodes <NUM>. Alternatively (in an embodiment not forming part of the claimed invention), as in <FIG>, a width W2 of the hole H may be set equal to or narrower than the distance D between the adjacent first electrodes <NUM> (S102 of <FIG>).

Third, as in <FIG>, a pixel defining layer <NUM> is formed on the planarization layer <NUM> disposed in the hole H and the first electrode <NUM>. That is, the pixel defining layer <NUM> may be formed all over the first substrate <NUM>. The pixel defining layer <NUM> may be an insulation layer.

The pixel defining layer <NUM> may be formed in an atomic layer deposition (ALD) process or an initiated chemical vapor deposition (iCVD) process. If the pixel defining layer <NUM> is formed in the ALD process, the pixel defining layer <NUM> may be formed to have a thickness of about <NUM> µm to <NUM> µm, and if the pixel defining layer <NUM> is formed in the iCVD process, the pixel defining layer <NUM> may be formed to have a thickness of about <NUM> µm to <NUM> µm.

A layer formed in the ALD process or the iCVD process is good in step coverage characteristic. Therefore, a layer formed by the ALD process or the iCVD process is good in step coverage characteristic, and thus, even when the width W1 of the hole H is set wider than the distance D between the adjacent first electrodes <NUM> as in <FIG>, the pixel defining layer <NUM> may be formed on both a sidewall and a floor of the hole H. Particularly, the pixel defining layer <NUM> may also be formed under the first electrode <NUM>. That is, the pixel defining layer <NUM> may be continuously connected without being disconnected despite a step height caused by the hole H (S103 of <FIG>).

Fourth, as in <FIG>, a photoresist pattern PR may be formed on the pixel defining layer <NUM>. The photoresist pattern PR may be formed in an area other than an emissive area EA (S104 of <FIG>).

Fifth, as in <FIG>, the pixel defining layer <NUM> uncovered by the photoresist pattern PR may be dry-etched. Therefore, a portion of the first electrode <NUM> corresponding to the emissive area EA may be exposed (S105 of <FIG>).

Sixth, as in <FIG>, the photoresist pattern PR may be removed (S106 of <FIG>).

Seventh, as in <FIG>, an organic light emitting layer <NUM>, a second electrode <NUM>, and an encapsulation layer <NUM> are sequentially formed on the first electrode <NUM> and the pixel defining layer <NUM>.

In detail, the organic light emitting layer <NUM> may be formed on the first electrode <NUM> and the pixel defining layer <NUM> in a deposition process or a solution process. If the organic light emitting layer <NUM> is formed in the deposition process, the organic light emitting layer <NUM> may be formed in an evaporation process. A layer formed in the evaporation process is not good in step coverage characteristic.

Therefore, when the width W1 of the hole H is set wider than the distance D between the adjacent first electrodes <NUM> as in <FIG>, the organic light emitting layer <NUM> may be disconnectedly formed in the hole H. That is, since the organic light emitting layer <NUM> is formed in the deposition process which is not good in step coverage characteristic, the organic light emitting layer <NUM> may be formed on only the floor of the hole H without being formed on the sidewall of the hole H.

Subsequently, the second electrode <NUM> is formed on the organic light emitting layer <NUM>. The second electrode <NUM> may be formed of a transparent conductive material (or TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO) capable of transmitting light, or a semi-transmissive conductive material such as Mg, Ag, or an alloy of Mg and Ag. The second electrode <NUM> may be formed in a physical vapor deposition (PVD) process such as a sputtering process. A layer formed in the PVD process such as the sputtering process is good in step coverage characteristic. Accordingly, the second electrode <NUM> may be continuously connected without being disconnected despite a step height caused by the hole H.

Subsequently, a capping layer may be formed on the second electrode <NUM>.

Subsequently, an encapsulation layer <NUM> is formed on the second electrode <NUM>. The encapsulation layer <NUM> may be formed to fill the contact hole CT2 and the hole H.

The first and second inorganic layers may each be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, and/or the like. The organic layer may be formed of acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and/or the like (S107 of <FIG>).

Eighth, as in <FIG>, the encapsulation layer <NUM> of the first substrate <NUM> may be adhered to the color filters <NUM> and <NUM> of the second substrate <NUM> by using an adhesive layer <NUM>. Therefore, the first substrate <NUM> may be bonded to the second substrate <NUM>. The adhesive layer <NUM> may be a transparent adhesive resin (S108 of <FIG>).

As described above, in an embodiment, the hole H corresponding to the recessed portion of the planarization layer <NUM> is formed between adjacent first electrodes <NUM>, and the pixel defining layer <NUM> may be thinly formed by the ALD process or the iCVD process. As a result, according to an embodiment, since the hole H is not filled with the pixel defining layer <NUM>, the organic light emitting layer <NUM> may be disconnected in the hole H due to a step height caused by the hole H, or may be thinly formed on the sidewall of the hole H. Therefore, according to an embodiment, the amount of current leaked from one pixel to another pixel adjacent thereto due to the hole transporting layer and/or the charge generating layer of the organic light emitting layer is minimized. Accordingly, according to an embodiment, the other pixel adjacent to the one pixel is prevented from being affected by the current leaked from the one pixel.

Moreover, according to the embodiments, the hole is formed in order for the planarization layer to be recessed between the first electrodes, and the pixel defining layer may be thinly formed by the ALD process or the iCVD process. As a result, according to the embodiments, since the hole is not filled with the pixel defining layer, the organic light emitting layer may be disconnected in the hole due to a step height caused by the hole, or may be thinly formed on a sidewall of the hole. Therefore, according to the embodiments, the amount of current leaked from one pixel to another pixel adjacent thereto due to the hole transporting layer and/or the charge generating layer of the organic light emitting layer is minimized. Accordingly, according to the embodiments, the other pixel adjacent to the one pixel is prevented from being affected by the current leaked from the one pixel.

Claim 1:
An organic light emitting display device comprising:
a substrate (<NUM>);
a thin film transistor (<NUM>) on the substrate (<NUM>);
a planarization layer (<NUM>) on the thin film transistor (<NUM>); and
a contact hole (CT2) passing through the planarization layer (<NUM>) to expose a source or drain electrode (<NUM>, <NUM>) of the thin film transistor (<NUM>);
a plurality of emissive areas (EA) each having a first electrode (<NUM>), a light emitting layer (<NUM>) on the first electrode (<NUM>), and a second electrode (<NUM>) on the light emitting layer (<NUM>);
a hole (H) between a first emissive area and a second emissive area of the plurality of emissive areas to provide an interruption between the light emitting layer (<NUM>) of the first emissive area and the light emitting layer (<NUM>) of the second emissive area; and
a pixel defining layer (<NUM>) on a portion of one first electrode (<NUM>) and in the hole (H), wherein the first and second emissive areas are divided by the pixel defining layer (<NUM>),
wherein a width (W1) of the hole (H) is wider than a distance (D) between one first electrode (<NUM>) of the first emissive area and one first electrode (<NUM>) of the second emissive area.