Patent Description:
A challenge with multilevel signaling in high speed, high bandwidth, low power memory systems is non-idealities that negatively affect system performance, for example, with regards to signal voltage levels, signal voltage margins. An example is the inability for signal drivers to fully drive the voltage levels of the multilevel signals to a high supply voltage or to a low supply voltage within a data period due to non-ideal performance of the circuits (e.g., pull-up and pull-down transistors) of the signal drivers. Variations in power, temperature, and fabrication process may further degrade system performance. As a result, the voltage range for the multilevel signals is reduced, which decreases the voltage margins for the different voltage levels. More generally, the signal drivers may be unable to adequately drive the multilevel signals to the correct voltage levels, which may result in data errors. <CIT> discloses a booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition. <CIT> discloses apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection circuit, a driver adjust circuit, and a data driver. The detection circuit is configured to detect a characteristic(s) of a group of input data signals to be driven onto adjacent signal lines. A characteristic could be, for example, a particular combination of logic levels and/or transitions for, the group of input data signals. The driver adjust circuit is configured to provide a driver adjustment signal based at least in part on a detection signal, that is provided by the detection circuit. A data driver is configured to drive a respective one of the group of input data signals as a respective one of the output data signals, wherein the data drive is adjusted based at least in part on the driver adjustment signal. <CIT> discloses a magnetic memory device such as a magnetic random access memory (MRAM), and a memory module and a memory system on which the magnetic memory device is mounted are disclosed. The MRAM includes magnetic memory cells each of which varies between at least two states according to a magnetization direction and an interface unit that provides various interface functions. The memory module includes a module board and at least one MRAM chip mounted on the module board, and further includes a buffer chip that manages an operation of the at least one MRAM chip. The memory system includes the MRAM and a memory controller that communicates with the MRAM, and may communicate an electric-to-optical conversion signal or an optical-to-electric conversion signal by using an optical link that is connected between the MRAM and the memory controller.

Certain details are set forth below to provide a sufficient understanding of examples of the disclosure. However, it will be clear to one having skill in the art that examples of the disclosure may be practiced without these particular details. Moreover, the particular examples of the present disclosure described herein should not be construed to limit the scope of the disclosure to these particular examples. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the disclosure. Additionally, terms such as "couples" and "coupled" mean that two components may be directly or indirectly electrically coupled. Indirectly coupled may imply that two components are coupled through one or more intermediate components.

<FIG> is a block diagram of an apparatus <NUM> according to an embodiment of the present disclosure. The apparatus <NUM> includes a first device <NUM> that communicates with a second device <NUM> over an input/output (I/O) bus. The first device <NUM> includes an I/O interface circuit <NUM> that includes signal driver <NUM> and receiver and decoder circuit <NUM> for communication over the I/O bus. The second device <NUM> includes an I/O interface circuit <NUM> that includes signal driver <NUM> and receiver and decoder circuit <NUM> for communication over the I/O bus. The I/O bus may support a multilevel communication architecture that includes a plurality of channels. In some embodiments, each channel may be single-ended and may include a single signal line. In other embodiments, each channel may include more than one signal line. In one embodiment, the first device <NUM>, the second device <NUM>, and the I/O bus may support a channel that includes conversion of M bitstreams to N multilevel signals, where M is greater than N.

A bitstream includes a plurality of bits provided serially, wherein each bit of the bitstream is provided over a period of time, that may be referred to as a data period. For example, a first bit is provided for a first period, and a second bit is provided for a second period following the first period, and a third bit is provided for a third period following the second period, and so on. The successive bits provided in this serial manner represent a stream of bits. The corresponding bits of each bitstream for a data period represents data M bits wide. The N multilevel signals may be transmitted over the I/O bus. Each multilevel signal is provided over a data period having a voltage
corresponding to one of multiple voltage levels (e.g., <NUM> different voltage levels, <NUM> different voltage levels, <NUM> different voltage levels, etc.), where each of the multiple voltage levels represents different data. In one example, <NUM> bit streams may be converted to <NUM> tri-level signals. In another example, pulse-amplitude modulation (PAM) may be used to convert <NUM>, <NUM>, or <NUM> bitstreams into a single multilevel signal having <NUM>, <NUM>, <NUM>, etc., levels.

In some examples, the first device <NUM> may include a memory controller or processing system and/or the second device <NUM> may include a memory, including volatile memory and/or non-volatile memory. In some examples, the second device <NUM> may include a dynamic random access memory (DRAM), such as a double-data-rate (DDR) DRAM or a low power DDR DRAM. It should be noted, however, that a memory is not a necessary component of the disclosure. Rather, the disclosure may be applied to any two or more devices, on or off-chip, that communicate with one another using multilevel signaling.

The signal driver <NUM> may include circuitry that applies a bitstream conversion to a set of M bitstreams to generate N multilevel signals and drives the N multilevel signals as channels on the I/O bus. Similarly, the signal driver <NUM> may include circuitry that applies a bitstream conversion to a set of M bitstreams to generate N multilevel signals and drives the N multilevel signals as channels on the I/O bus. In some examples, the signal driver <NUM> may include modifications to existing DDR drivers to drive the multilevel signals onto the channels of the I/O bus.

For each channel, the receiver and decoder circuit <NUM> may include decoders configured to recover the set of M bitstreams by decoding the N multilevel signals received via the channels of the I/O bus as provided by the signal driver <NUM>. Further, the receiver and decoder circuit <NUM> may include decoders configured to recover the set of M bitstreams by decoding the N multilevel signals received via the channels of the I/O bus as provided by the signal driver <NUM>. In some embodiments, the receiver and decoder circuit <NUM> and the receiver and decoder circuit <NUM> may include comparators and decoding logic to recover the set of M bitstreams.

In operation, the first device <NUM> and the second device <NUM> may communicate over the I/O bus to transfer information, such as data, addresses, commands, etc. While the I/O bus is shown to be bidirectional, the I/O bus may also be a unidirectional bus. The I/O interface circuit <NUM> and I/O interface circuit <NUM> may implement a multilevel communication architecture. In a multilevel communication architecture, data is sent over a channel during a data period. Data may include a single value on a signal line of a channel, or may be a combination of values provided on a plurality of signal lines of a channel. The data may represent a channel state. A receiver may determine an output signal value based on the value transmitted on the signal line(s) of a channel. In a single-ended architecture, the signal line value may be compared against one or more reference values to determine the output signal value. A receiver has a time period to determine and latch the output signal value from the time the output signal transitions to the current value to the time the output signal transitions to the next value. The transition time may be determined based on a clock signal, as well as a setup and hold time based on a transition from one value to another. In a multilevel communication architecture with a fixed slew rate or fixed rise/fall times, inherent jitter may occur due to differing magnitude shifts (e.g., from VH to VL vs. from VMID to VH or VL). The amount of jitter may be based on the slew rate, the rise/fall times, the multilevel magnitudes values, or combinations thereof. In some examples, the transition times may also be affected by process, voltage, and temperature variations.

In an example, the signal driver <NUM> may generate data for a channel by converting a bit from each of the M bitstreams during a data period into N multilevel signals. The data may be transmitted to the receiver and decoder circuit <NUM> via N signal lines of the I/O bus. The receiver and decoder circuit <NUM> may detect levels on the N signal lines and decode the levels to retrieve the bit from each of the M streams. By using multilevel signal lines, more data can be transmitted during a data period as compared with using binary signal line levels. In an example, M is <NUM> and N is <NUM>, and the signal lines of the I/O bus are capable of being driven to three independent voltage levels. In another example, M is <NUM> and N is <NUM>, and the signal lines of the I/O bus are capable of being driven to four independent voltage levels (e.g., in a PAM implementation). Communication protocol between the signal driver <NUM> and the receiver and decoder circuit <NUM> may be similar to the communication protocol between the encoder and signal driver <NUM> and the receiver and decoder circuit <NUM>. The signal driver <NUM> may include a DRAM driver that has been segmented to drive multiple (e.g., more than <NUM>) voltage levels on a signal line.

<FIG> is a block diagram of an apparatus for a multilevel communication architecture according to an embodiment of the disclosure. The apparatus includes a signal driver <NUM> coupled to a receiver <NUM> via an I/O bus. The signal driver <NUM> may be implemented in the signal driver <NUM> and/or the signal driver <NUM> of <FIG> and the receiver <NUM> may be implemented in the receiver and decoder circuit <NUM> and/or the receiver and decoder circuit <NUM> of <FIG>.

The signal driver <NUM> includes a driver circuit <NUM>. The driver circuit <NUM> receives bitstreams IN<<NUM>> and IN<<NUM>> and drive an output signal OUT in response. The IN<<NUM>> and IN<<NUM>> bitstreams may represent a stream of two-bit data. The output signal OUT driven by the driver circuit <NUM> is based on the IN<<NUM>> and IN<<NUM>> bitstreams. For example, the signal may be a multilevel signal representing data of the IN<<NUM>> and IN<<NUM>> bitstreams. In some embodiments of the disclosure, the driver circuit <NUM> may include one or more signal line drivers having a pull-up (e.g., p-type) transistor coupled in series with a pull-down (e.g., n-type) transistor. A source of the pull-up transistor is coupled to a high supply voltage and the source of the pull-down transistor is coupled to a low supply voltage. In some embodiments, the high supply voltage is <NUM> V and the low supply voltage is ground. The output signal OUT is provided at a common node to which the pull-up and pull-down transistors are coupled. Gates of the pull-up and pull-down transistors of the driver circuit <NUM> are provided with the IN<<NUM>> and IN<<NUM>> bitstreams. In other embodiments of the disclosure, the driver circuit <NUM> may be implemented using other configurations.

The signal driver <NUM> further includes a boost control circuit <NUM> and a boost circuit <NUM>. The boost control circuit <NUM> provides control signals to control the boost circuit <NUM> according to the IN<<NUM>> and IN<<NUM>> bitstreams. The boost circuit <NUM> may be controlled to provide increased pull-up capability and/or increased pull-down capability for the driver circuit <NUM> based on current data of the IN<<NUM>> and IN<<NUM>> bitstreams.

The receiver <NUM> includes comparator block <NUM> coupled to a decoder <NUM>. The comparator block <NUM> is configured to receive the signal from the I/O bus and provide Z0-Zn signals (n is a whole number) to the decoder <NUM>. The comparator block <NUM> may include circuits (not shown in <FIG>) configured to compare the signal from the I/O bus against reference signals to provide the Z0-Zn signals. For example,
the comparator block <NUM> may include comparators that compare the OUT signal from the I/O bus against various reference signals to provide the Z0-Zn signals. The decoder <NUM> may include logic to generate the bitstreams RX<<NUM>> and RX<<NUM>> based on the Z0-Zn signals from the comparator block <NUM>. The RX<<NUM>> and RX<<NUM>> bitstreams may be logical equivalents of data transmitted by the IN<<NUM>> and IN<<NUM>> bitstreams. The RX<<NUM>> and RX<<NUM>> bitstreams may represent a stream of two-bit received data.

In operation, the IN<<NUM>> and IN<<NUM>> may be bitstreams to be transmitted over the I/O bus. Rather than send each bitstream on a separate signal line, the signal driver <NUM> may provide a signal based on the IN<<NUM>> and IN<<NUM>> bitstreams to be transmitted over a signal line using a multilevel signal. For example, the signal driver <NUM> may receive the IN<<NUM>> and IN<<NUM>> bitstreams, and during each data period, the driver circuit <NUM> may drive the signal line of the I/O bus with a voltage that will be used by the receiver <NUM> to provide the RX<<NUM>> and RX<<NUM>> bitstreams. The multilevel signal may be used to represent data of the IN<<NUM>> and IN<<NUM>> bitstreams using fewer signal lines than one signal line per bitstream. For example, as in the embodiment of <FIG>, data of the IN<<NUM>> and IN<<NUM>> bitstreams are provided to the receiver <NUM> on fewer than two signal lines (e.g., one signal on the I/O bus rather than one signal line for the IN<<NUM>> bitstream and another signal line for the IN<<NUM>> bitstream). Although <FIG> illustrates operation with bitstreams IN<<NUM>> and IN<<NUM>> for providing bitstreams RX<<NUM>> and RX<<NUM>>, the number of bitstreams may be different in other embodiments of the disclosure. For example, in some embodiments of the disclosure, a third bitstream IN<<NUM>> may also be provided to the signal driver <NUM> in addition to the IN<<NUM>> and IN<<NUM>> bitstreams and a multilevel signal may be provided over the I/O bus representing the data from the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams. Such embodiments are within the scope of the present disclosure.

<FIG> is a schematic drawing of a signal driver <NUM> according to an embodiment of the disclosure. The signal driver <NUM> may be used for a multilevel signal architecture implementing pulse-amplitude modulation (PAM). The signal driver <NUM> may be used as the signal driver <NUM> in embodiments of the disclosure.

The signal driver <NUM> includes a driver circuit including six signal line drivers coupled to a common node that is an output. The output may represent an output terminal. Each of the signal line drivers are coupled to a high supply voltage (e.g., VDDQ) and to a low supply voltage (e.g., VSSQ). The driver circuit may be a driver in a DRAM, such as a double data rate (DDR) DRAM driver. In some embodiments of the disclosure, each of the signal line drivers has an impedance of <NUM> ohms. The driver circuit includes a first driver section <NUM> and a second driver section <NUM> configured to drive an output signal OUT to a common node to which the first and second driver sections <NUM> and <NUM> are coupled. A signal line is coupled to the common node. The output signal OUT driven by the first and second driver sections <NUM> and <NUM> is based on IN<<NUM>> and IN<<NUM>> bitstreams, which are provided to the signal line drivers of the driver circuit. The output signal OUT is a multilevel signal representing data of the IN<<NUM>> and IN<<NUM>> bitstreams that drives the I/O bus. In some embodiments of the disclosure, "<NUM>" data is represented by the IN<<NUM>> signal or IN<<NUM>> signal having a voltage of <NUM> V, and "<NUM>" data is represented by the IN<<NUM>> signal or IN<<NUM>> signal having a voltage of <NUM> V. However, other voltage levels may be used to represent the "<NUM>" and "<NUM>" data in other embodiments of the disclosure.

The first driver section <NUM> includes four signal line drivers coupled to the common node, each controlled responsive to the IN<<NUM>> bitstream. Each signal line driver includes a pull-up (e.g., p-type) transistor and a pull-down (e.g., n-type) transistor. The complement of the IN<<NUM>> bitstream is provided to the gates of the pull-up and pull-down transistors by an inverter circuit that receives the IN<<NUM>> bitstream. The second driver section <NUM> includes two signal line drivers coupled to the common node, each controlled responsive to the IN<<NUM>> bitstream, and each signal line driver includes a pull-up (e.g., p-type) transistor and a pull-down (e.g., n-type) transistor. The complement of the IN<<NUM>> bitstream is provided to the gates of the pull-up and pull-down transistors by an inverter circuit that receives the IN<<NUM>> bitstream. In an embodiment of the disclosure where each signal line driver has an impedance of <NUM> ohms, the first driver section <NUM> has an effective impedance of <NUM> ohms, the second driver section <NUM> has an effective impedance of <NUM> ohms. With each of the signal line drivers having the same impedance, the signal line drivers have the same drive strength.

The signal driver <NUM> further includes a boost circuit <NUM> that receives control signals BoostHi and BoostLo from boost control circuit <NUM>. The boost control circuit <NUM> includes logic circuits and provides control signals BoostHi and BoostLo to the boost circuit <NUM> based on the IN<<NUM>> and IN<<NUM>> bitstreams. In some embodiments of the disclosure, a BoostHi signal or BoostLo signal having the high logic level is represented by a signal of <NUM> V, and a BoostHi signal or BoostLo signal having the low logic level is represented by a signal of <NUM> V. However, other voltage levels may be used to represent the "<NUM>" and "<NUM>" data in other embodiments of the disclosure.

The boost circuit <NUM> is coupled to the common node and includes a pull-up (e.g., p-type) transistor and a pull-down (e.g., n-type) transistor, which are controlled by the BoostHi and BoostLo signals, respectively. The boost circuit <NUM> may also be referred to as another driver section of the driver circuit. The complement of the BoostHi signal is provided to the gate of the pull-up transistor by an inverter circuit that receives the BoostHi signal. In the embodiment of <FIG>, the BoostHi signal provided by the boost control circuit <NUM> is active when at a high logic level to activate the pull-up transistor and the BoostLo signal is active when at a high logic level to activate the pull-down transistor. When activated by an active BoostHi signal from the boost control circuit <NUM>, the pull-up transistor provides additional drive to pull up the level of the signal line. Similarly, when activated by an active BoostLo signal from the boost control circuit <NUM>, the pull-down transistor provides additional drive to pull down the level of the signal line. As previously discussed, in an embodiment of the disclosure where each signal line driver has an impedance of <NUM> ohms, the first driver section <NUM> has an effective impedance of <NUM> ohms, the second driver section <NUM> has an effective impedance of <NUM> ohms. The boost circuit <NUM> would have an impedance of <NUM> ohms. As a result, the first driver section <NUM>, second driver section <NUM>, and boost circuit (e.g., third driver section) have different drive strengths from one another.

As will be described in more detail below, the pull-up transistor of the boost circuit <NUM> may be activated when the IN<<NUM>> and IN<<NUM>> bitstreams represent data corresponding to a voltage level of a high supply voltage (e.g., representing data "<NUM>"), and the pull-down transistor may be activated when the IN<<NUM>> and IN<<NUM>> bitstreams represent data corresponding to a voltage level of a low supply voltage (e.g., representing data "<NUM>"). While <FIG> shows the boost circuit <NUM> as including one pull-up transistor and one pull-down transistor, in other embodiments of the disclosure, the boost circuit <NUM> may include a greater number of pull-up and/or pull-down transistors. Thus, the embodiment of <FIG> is not intended to limit boost circuits, or more generally, driver circuits, to embodiments having the specific configuration shown in <FIG>.

In operation, the signal driver <NUM> may drive the OUT signal responsive to the IN<<NUM>> and IN<<NUM>> bitstreams. The IN<<NUM>> and IN<<NUM>> bitstreams are provided to the signal line drivers of the driver sections <NUM> and <NUM> to provide an output signal OUT having an appropriate voltage for the multilevel signal, for example, using PAM to convert a plurality of bitstreams into a multilevel signal.

In some embodiments of the disclosure, PAM4 is used to convert two bitstreams (e.g., the IN<<NUM>> and IN<<NUM>> bitstreams) into an OUT signal having one of four different voltage levels. The IN<<NUM>> bitstream may be provided to the signal line drivers of the first driver section <NUM> and the IN<<NUM>> bitstream may be provided to the signal line drivers of the second driver section <NUM>. The resulting output signal will have one of four different voltages corresponding to the data of the IN<<NUM>> and IN<<NUM>> bitstreams. For example, where a current data of the IN<<NUM>> and IN<<NUM>> bitstreams is a "<NUM>", the pull-down transistors of both the driver sections <NUM> and <NUM> are activated to drive (e.g., pull down) the common node to the low supply voltage to provide an output signal OUT having the voltage of the low supply voltage. Additionally, as previously described, a current data of "<NUM>" also causes the pull-down transistor of the boost circuit <NUM> to provide additional drive to pull down the common node to the low supply voltage. Where a current data of the IN<<NUM>> and IN<<NUM>> bitstream is a "<NUM>", the pull-up transistors of both the driver sections <NUM> and <NUM> are activated to drive (e.g., pull up) the common node to the high supply voltage to provide an output signal OUT having the voltage of the high supply voltage. Additionally, as previously described, a current data of "<NUM>" also causes the pull-up transistor of the boost circuit <NUM> to provide additional drive to pull up the common node to the high supply voltage. As illustrated by the example, the pull-up transistor of the boost circuit <NUM> is activated to drive the common node to the high supply voltage when the first and second driver sections <NUM> and <NUM> drive the common node to the high supply voltage. Similarly, the pull-down transistor of the boost circuit <NUM> is activated to drive the common node to the low supply voltage when the first and second driver sections <NUM><NUM> and <NUM> drive the common node to the low supply voltage.

For current data of the IN<<NUM>> and IN<<NUM>> bitstream is a "<NUM>", the pull-down transistors of the driver section <NUM> are activated and the pull-down transistors of the driver section <NUM> are activated to provide a voltage to the common node that results in an output signal OUT having an intermediate-low voltage. Lastly, for current data of the IN<<NUM>> and IN<<NUM>> bitstream is a "<NUM>", the pull-up transistors of the driver section <NUM> are activated and the pull-down transistors of the driver section <NUM> are activated to provide a voltage to the common node that results in an output signal OUT having an intermediate-high voltage. For a current data of "<NUM>" or "<NUM>", that is, where the first and second driver sections <NUM> and <NUM> are driving the common node to different supply voltages, neither the pull-up nor pull-down transistors of the boost circuit <NUM> are activated to provide any additional drive to change the voltage of the common node. With both the pull-up and pull-down transistors of the boost circuit <NUM> deactivated, the boost circuit <NUM> is in a high-impedance state.

While the first driver section <NUM>, the second driver section <NUM>, and the boost circuit <NUM> are shown in <FIG> as including p-type pull-up transistors and n-type pull-down transistors. That is, the pull-up and pull-down transistors have different conductivity types. In other embodiments of the disclosure, the first driver section <NUM>, the second driver section <NUM>, and the boost circuit <NUM> may include n-type pull-up transistors, or a combination of p-type and n-type pull-up transistors. In embodiments of the disclosure using n-type pull-up transistors, which are activated by a high logic level signal (e.g., having the high supply voltage), the logic level of the signals provided to gates of the n-type pull-up transistors will have a complementary logic level to signals provided to the gates of p-type pull-up transistors. A signal having a complementary logic level may be provided by using an inverter circuit.

<FIG> is a schematic diagram of a boost control circuit <NUM> according to an embodiment of the disclosure. The boost control circuit <NUM> may be included in the boost control circuit <NUM> of the signal driver <NUM> of <FIG> in some embodiments of the disclosure. The boost control circuit <NUM> may control the boost circuit <NUM> to provide additional drive capability to the driver sections <NUM> and <NUM> and drive the common node to provide a voltage level of the high supply voltage (e.g., when the IN<<NUM>> and IN<<NUM>> bitstreams represent "<NUM>" data). The boost control circuit <NUM> includes an AND
logic circuit that receives the IN<<NUM>> and IN<<NUM>> bitstreams and provides the BoostHi signal resulting from a logic AND operation of the IN<<NUM>> and IN<<NUM>> bitstreams.

In operation, the boost control circuit <NUM> provides an active BoostHi signal (e.g., active when a high logic level) when the current data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", which causes the signal driver <NUM> to provide the output signal OUT having the voltage of the high supply voltage (e.g., current data of the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>"). That is, with the IN<<NUM>> a "<NUM>" and the IN<<NUM>> a "<NUM>", the high logic level of the IN<<NUM>> bitstream is provided to the line drivers of the first driver section <NUM> to cause the pull-up transistors to be activated and the high logic level of the IN<<NUM>> bitstream is provided to the line drivers of the second driver section <NUM> to cause the pull-up transistors to be activated. As a result, the common node to which the first and second driver sections <NUM> and <NUM> are coupled is pulled up to the voltage of the high supply voltage. Additionally, the high logic levels of the IN<<NUM>> and IN<<NUM>> bitstreams are provided to the AND logic circuit of the boost control circuit <NUM> and a logical AND operation is performed to provide an active (e.g., a high logic level) BoostHi signal. The pull-up transistor of the boost circuit <NUM> is activated by the active BoostHi signal to provide additional drive to further pull up the common node to the voltage of the high supply voltage. Thus, as illustrated by the example operation, the pull-up transistor of the boost circuit <NUM> is activated to assist in pulling up the common node when the output signal OUT is to be provided having the voltage of the high supply voltage.

<FIG> is a schematic diagram of a boost control circuit <NUM> according to an embodiment of the disclosure. The boost control circuit <NUM> may be included in the boost control circuit <NUM> of the signal driver <NUM> of <FIG> in some embodiments of the disclosure. The boost control circuit <NUM> may control the boost circuit <NUM> to provide additional drive capability to the driver sections <NUM> and <NUM> and drive the common node to provide a voltage level of the low supply voltage (e.g., when the IN<<NUM>> and IN<<NUM>> bitstreams represent "<NUM>" data). The boost control circuit <NUM> includes an exclusive OR (XOR) logic circuit <NUM> that receives the IN<<NUM>> and IN<<NUM>> bitstreams and an inverter circuit <NUM> that receives the IN<<NUM>> bitstream. The signals provided by the XOR logic circuit <NUM> and the inverter circuit <NUM> are provided to an AND logic
circuit <NUM> which provides the BoostLo signal resulting from a logic AND operation of the signals provided by the XOR logic circuit <NUM> and the inverter circuit <NUM>.

In operation, the boost control circuit <NUM> provides an active BoostLo signal (e.g., active when a high logic level) when the current data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is a "<NUM>", which causes the signal driver <NUM> to provide the output signal OUT having the voltage of the low supply voltage (e.g., current data of the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>"). That is, with the IN<<NUM>> a "<NUM>" and the IN<<NUM>> a "<NUM>", the low logic level of the IN<<NUM>> bitstream is provided to the line drivers of the first driver section <NUM> to cause the pull-down transistors to be activated and the low logic level of the IN<<NUM>> bitstream is provided to the line drivers of the second driver section <NUM> to cause the pull-down transistors to be activated. As a result, the common node to which the first and second driver sections <NUM> and <NUM> are coupled is pulled down to the voltage of the low supply voltage. Additionally, the low logic levels of the IN<<NUM>> and IN<<NUM>> bitstreams are provided to the XOR logic circuit <NUM> of the boost control circuit <NUM> and the IN<<NUM>> bitstream is provided to the inverter circuit <NUM>. The outputs of the XOR logic circuit <NUM> and the inverter circuit <NUM> are provided to the AND logic circuit <NUM>, and a logical NAND operation is performed to provide an active (e.g., a high logic level) BoostLo signal. The pull-down transistor of the boost circuit <NUM> is activated by the active BoostLo signal to provide additional drive to further pull down the common node to the voltage of the low supply voltage. Thus, as illustrated by the example operation, the pull-down transistor of the boost circuit <NUM> is activated to assist in pulling down the common node when the output signal OUT is to be provided having the voltage of the low supply voltage.

<FIG> is a diagram showing operation of the first and second driver sections <NUM> and <NUM>, and the boost circuit <NUM>, of the signal driver <NUM> for driving a load that is terminated to a high supply voltage (e.g., VDDQ) according to an embodiment of the disclosure. In such a situation, a typical signal driver may not fully drive an output signal OUT to a low supply voltage (e.g., VSSQ, as shown as "w/o Boost"). The high supply voltage may represent a high logic level (e.g., "<NUM>") output signal OUT and the low supply voltage may represent a low logic level (e.g., "<NUM>") output signal OUT in some embodiments of the disclosure. The inability for the signal driver to fully drive the output signal OUT to the high supply voltage may be due to, for example, variations in circuit performance. The variation in circuit performance may be due to variations in the process when fabricating the circuits, variations in the supply voltages powering the circuits, and/or operating temperature of the circuits. As a result, actual circuit performance may deviate from ideal circuit performance. By not fully driving the output signal OUT to the low supply voltage, the voltage margin between the different voltage levels representing the different data is reduced, which may be more susceptible to data errors.

As shown in <FIG> (as shown as "w/Boost"), the boost circuit <NUM> may be used to assist driving the output signal OUT. In particular, the pull-down transistor of the boost circuit <NUM> may be used to provide additional drive to fully drive the output signal OUT to the low supply voltage when the signal driver <NUM> provides an output signal OUT having a low logic level. As previously described, the pull-down transistor of the boost circuit <NUM> may be activated by an active BoostLo signal, which may be provided by boost control circuit (e.g., boost control circuit <NUM>). The BoostLo signal may be active when the signal driver <NUM> is driving a low logic level output signal OUT.

<FIG> is a diagram showing operation of the first and second driver sections <NUM> and <NUM>, and the boost circuit <NUM>, of the signal driver <NUM> for driving a line terminated load according to an embodiment of the disclosure. In such a situation, a typical signal driver may not fully drive an output signal OUT to either a high or low supply voltage (e.g., VDDQ or VSSQ, as shown as "w/o Boost"). The high supply voltage may represent a high logic level (e.g., "<NUM>") output signal OUT and the low supply voltage may represent a low logic level (e.g., "<NUM>") output signal OUT in some embodiments of the disclosure. As previously described, the inability for the signal driver to fully drive the output signal OUT to the high supply voltage may be due to, for example, variations in circuit performance. The variation in circuit performance may be due to variations in the process when fabricating the circuits, variations in the supply voltages powering the circuits, and/or operating temperature of the circuits. As a result, actual circuit performance may deviate from ideal circuit performance. As further described, by not fully driving the output signal OUT to either of the high or low supply voltages, the voltage margin between the different voltage levels representing the different data is reduced, which may be more susceptible to data errors.

As shown in <FIG> (as shown as "w/Boost"), the boost circuit <NUM> may be used to assist driving the output signal OUT. In particular, the pull-down transistor of the boost circuit <NUM> may be used to provide additional drive to fully drive the output signal OUT to the low supply voltage when the signal driver <NUM> provides an output signal OUT having a low logic level. Additionally, the pull-up transistor of the boost circuit <NUM> may be used to provide additional drive to fully drive the output signal OUT to the high supply voltage when the signal driver <NUM> provides an output signal OUT having a high logic level. As previously described, the pull-down transistor of the boost circuit <NUM> may be activated by an active BoostLo signal and the pull-up transistor of the boost circuit <NUM> may be activated by an active BoostHi signal. The BoostLo and BoostHi signals may be provided by a boost control circuit (e.g., boost control circuit <NUM>). The BoostLo signal may be active when the signal driver <NUM> is driving a low logic level output signal OUT and the BoostHi signal may be active when the signal driver <NUM> is driving a high logic level output signal OUT.

<FIG> is a diagram showing operation of the first and second driver sections <NUM> and <NUM>, and the boost circuit <NUM>, of the signal driver <NUM> for driving a load that is terminated to a low supply voltage (e.g., VSSQ) according to an embodiment of the disclosure. In such a situation, a typical signal driver may not fully drive an output signal OUT to a high supply voltage (e.g., VDDQ, as shown as "w/o Boost"). The high supply voltage may represent a high logic level (e.g., "<NUM>") output signal OUT and the low supply voltage may represent a low logic level (e.g., "<NUM>") output signal OUT in some embodiments of the disclosure.

As shown in <FIG> (as shown as "w/Boost"), the boost circuit <NUM> may be used to assist driving the output signal OUT. In particular, the pull-up transistor of the boost circuit <NUM> may be used to provide additional drive to fully drive the output signal OUT to the high supply voltage when the signal driver <NUM> provides an output signal OUT having a high logic level. As previously described, the pull-up transistor of the boost circuit <NUM> may be activated by an active BoostHi signal, which may be provided by boost control circuit (e.g., boost control circuit <NUM>). The BoostHi signal may be active when the signal driver <NUM> is driving a high logic level output signal OUT.

In some embodiments of the disclosure, the boost circuit <NUM> may provide additional drive for data corresponding to just one of the supply voltages. For example, in some embodiments of the disclosure, data corresponding to the low supply voltage is boosted, but data corresponding to the high supply voltage is not. The pull-up transistor of the boost circuit <NUM> may be disabled, circuits for providing signals to activate a pull-up transistor of the boost circuit <NUM> may not be included in the boost control circuit, circuits for providing signals to activate a pull-up transistor of the boost circuit <NUM> may not be enabled, or other approaches may be used to not provide boost for data corresponding to the high supply voltage. In other embodiments of the disclosure, the pull-down transistor of the boost circuit <NUM> may be disabled, so that data corresponding to the high supply voltage is boosted, but data corresponding to the low supply voltage is not. The pull-down transistor of the boost circuit <NUM> may be disabled, circuits for providing signals to activate a pull-down transistor of the boost circuit <NUM> may not be included in the boost control circuit, circuits for providing signals to activate a pull-down transistor of the boost circuit <NUM> may not be enabled, or other approaches may be used to not provide boost for data corresponding to the low supply voltage. In some embodiments of the disclosure, the boost circuit <NUM> is activated to provide additional drive for data corresponding to both the high supply voltage and the low supply voltage. In such embodiments, the boost control circuit <NUM> and the boost control circuit <NUM> may be included together.

<FIG> is a block diagram of an apparatus for a multilevel communication architecture according to an embodiment of the disclosure. The apparatus of <FIG> is similar to the apparatus of <FIG>, and consequently, the same reference numbers are used in <FIG> as in <FIG> to identify the same components as previously described. In contrast to the apparatus of <FIG>, the apparatus of <FIG> includes a signal driver <NUM> coupled to the receiver <NUM> via an I/O bus. The receiver <NUM> may be as previously described with reference to the apparatus of <FIG>.

The signal driver <NUM> may be implemented in the signal driver <NUM> and/or the signal driver <NUM> of <FIG> and the receiver <NUM> may be implemented in the receiver and decoder circuit <NUM> and/or the receiver and decoder circuit <NUM> of <FIG>. The signal driver <NUM> may include an input circuit <NUM> that receives bitstreams IN<<NUM>> and IN<<NUM>> and provides output signals to a boost control circuit <NUM> and a driver circuit <NUM>. The driver circuit <NUM> may be as previously described with reference to the apparatus of <FIG>. The boost control circuit <NUM> provides control signals to control the boost circuit <NUM> according to the output signals from the input circuit <NUM>. The boost circuit <NUM> may be controlled to provide increased pull-up capability and/or increased pull-down capability for the driver circuit <NUM> based on current data of the IN<<NUM>> and IN<<NUM>> bitstreams.

In operation, the signal driver <NUM> may receive the IN<<NUM>> and IN<<NUM>> bitstreams, and during each data period, the driver circuit <NUM> may drive the signal line of the I/O bus with a voltage that will be used by the receiver <NUM> to provide the RX<<NUM>> and RX<<NUM>> bitstreams. The multilevel signal may be used to represent data of the IN<<NUM>> and IN<<NUM>> bitstreams using fewer signal lines than one signal line per bitstream. Although <FIG> illustrates operation with bitstreams IN<<NUM>> and IN<<NUM>> for providing bitstreams RX<<NUM>> and RX<<NUM>>, the number of bitstreams may be different in other embodiments of the disclosure. For example, in some embodiments of the disclosure, a third bitstream IN<<NUM>> may also be provided to the signal driver <NUM> in addition to the IN<<NUM>> and IN<<NUM>> bitstreams and a multilevel signal may be provided over the I/O bus representing the data from the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams. Such embodiments are within the scope of the present disclosure.

<FIG> is a schematic diagram of an input circuit <NUM> according to an embodiment of the disclosure. The input circuit <NUM> may be included in the input circuit <NUM> of <FIG> in some embodiments of the disclosure. The input circuit <NUM> includes D flip-flop circuits <NUM> and <NUM>, and D flip-flop circuits <NUM> and <NUM>. The D flip-flop circuit <NUM> receives the IN<<NUM>> bitstream and the D flip-flop circuit <NUM> receives the IN<<NUM>> bitstream. The D flip-flop circuit <NUM> and the D flip-flop circuit <NUM> are clocked by a clock signal CLK, and the D flip-flop circuit <NUM> and the D flip-flop circuit <NUM> are clocked by a clock signal CLKF, which is the complement to the CLK signal. That is, a rising edge of the CLK signal corresponds to a falling edge of the CLKF signal, and a falling edge of the CLK signal corresponds to a rising edge of the CLKF signal. In some embodiments of the disclosure, the CLK signal may be a system clock signal or a clock signal derived from the system clock signal. The system clock signal may be a clock signal provided to different circuits of a larger system in order to synchronize operations, for example, for providing data between the different circuits. The D flip-flop circuits <NUM>, <NUM>, <NUM>, and <NUM> may be reset to provide an output having a known logic level when an active reset signal RST is provided to the D flip-flop circuits. The D flip-flop circuits <NUM>, <NUM>, <NUM>, and <NUM> may be reset, for example, upon reset of the semiconductor device, as part of a power up sequence, etc..

In operation, the D flip-flop circuit <NUM> latches a current logic level of the IN<<NUM>> bitstream responsive to a rising edge of the CLK signal and provides an output signal D<<NUM>> having the same logic level as the latched logic level. The D flip-flop circuit <NUM> latches the logic level of the D<<NUM>> signal responsive to a rising edge of the CLKF signal and provides an output signal IND<<NUM>> having the same logic level as the latched logic level. Likewise, the D flip-flop circuit <NUM> latches a current logic level of the IN<<NUM>> bitstream responsive to a rising edge of the CLK signal and provides an output signal D<<NUM>> having the same logic level as the latched logic level. The D flip-flop circuit <NUM> latches the logic level of the D<<NUM>> signal responsive to a rising edge of the CLKF signal and provides an output signal IND<<NUM>> having the same logic level as the latched logic level. With reference to the CLK signal, the IN<<NUM>> and IN<<NUM>> bitstreams are latched and the D<<NUM>> and D<<NUM>> signals provided responsive to a rising edge of the CLK signal, and the D<<NUM>> and D<<NUM>> signals are latched and the IND<<NUM>> and IND<<NUM>> signals are provided responsive to a falling edge of the CLK signal (i.e., the rising edge of the CLKF signal). Thus, the IND<<NUM>> and IND<<NUM>> signals have the logic levels of the D<<NUM>> and D<<NUM>> signals delayed by one-half a clock period of the CLK signal.

<FIG> is a schematic diagram of a pull-up logic circuit <NUM> according to an embodiment of the disclosure. The pull-up logic circuit <NUM> may be included in the boost control circuit <NUM> of <FIG> in some embodiments of the disclosure. The pull-up logic circuit <NUM> includes a NAND logic circuit <NUM> that receives the D<<NUM>> and D<<NUM>> signals, for example, from the input circuit <NUM>, and provides an output signal IN_11F that results from a NAND logic operation of the D<<NUM>> and D<<NUM>> signals. The pull-up logic circuit <NUM> further includes a NAND logic circuit <NUM> that receives the IND<<NUM>> and IND<<NUM>> signals, for example from the input circuit <NUM>. The NAND logic circuit <NUM> provides an output signal IND_11F resulting from a NAND logic operation on the IND<<NUM>> and IND<<NUM>> signals to an inverter circuit <NUM>. The inverter circuit <NUM> provides an output signal IND_11 that is the complement of the IND_11F signal. A NOR logic circuit receives the IN_11F signal from the NAND logic circuit <NUM> and the IND_11 signal from the inverter circuit <NUM> and provides an output signal PREPU that resulting from a NOR logic operation.

In operation, the logic circuit <NUM> provides an active PREPU signal (e.g., active high logic level) when the data of the IN<<NUM>> and IN<<NUM>> bitstreams changes from a previous value to a current data of "<NUM>". That is, where the previous data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", "<NUM>", or "<NUM>", and the data changes to a current data of "<NUM>", the logic circuit <NUM> provides an active PREPU signal. The logic circuit <NUM> provides an inactive PREPU signal for other changes from a previous data to a current data represented by the IN<<NUM>> and IN<<NUM>> bitstreams. That is, the logic circuit <NUM> provides an inactive PREPU signal for the IN<<NUM>> and IN<<NUM>> bitstreams changing from a previous data to current data of "<NUM>", "<NUM>", or "<NUM>". The active PREPU signal provided by the logic circuit <NUM> may be used to activate a boost circuit, for example, the boost circuit <NUM> of the signal driver <NUM>, to provide additional drive to assist driving the common node to the high supply voltage to provide an OUT signal having a voltage of the high supply voltage. As will be described in more detail below, the PREPU signal is active for a portion of the data period of the OUT signal. For example, in some embodiments of the disclosure, the PREPU signal is limited to being active to assist the driving of the common node to the high supply voltage.

The NAND logic circuit <NUM> provides a low logic level IN_11F signal when D<<NUM>> and D<<NUM>> are both a high logic level (i.e., resulting from the IN<<NUM>> and IN<<NUM>> bitstreams representing a current data of "<NUM>"). The inverter circuit <NUM> coupled to the NAND logic circuit <NUM> to receive the IND_11F signal provides a low logic level IND_11 when IND<<NUM>> and IND<<NUM>> are both a high logic level (i.e., resulting from D<<NUM>> and D<<NUM>> both a high logic level). Recall that the IND<<NUM>> and IND<<NUM>> are delayed relative to D<<NUM>> and D<<NUM>>, for example, by one-half a clock period of the CLK signal. The NOR logic gate provides an active PREPU signal (e.g. active high logic level) when the IN_11F and IND_11 signals have low logic levels. As a result, the PREPU signal is active when D<<NUM>> and D<<NUM>> are both at a high logic level, and for one-half a clock cycle of the CLK signal following a rising edge of the CLK signal. The PREPU signal is active for one-half a clock cycle of the CLK signal because the one-half clock cycle delay of the IND<<NUM>> and IND<<NUM>> relative to D<<NUM>> and D<<NUM>> will result in the IND_11 signal being at a low logic level while the IN_11F signal is at a low logic level (from D<<NUM>> and D<<NUM>> both being a high logic level), but for one-half a clock cycle of the CLK signal before both IND<<NUM>> and IND<<NUM>> also become a high logic level (resulting from the D<<NUM>> and D<<NUM>> both being at the high logic level). As a result, the PREPU signal is active for one-half a clock cycle of the CLK signal.

<FIG> is a schematic diagram of a pull-down logic circuit <NUM> according to an embodiment of the disclosure. The pull-down logic circuit <NUM> may be included in the boost control circuit <NUM> of <FIG> in some embodiments of the disclosure. The pull-down logic circuit <NUM> includes a NOR logic circuit <NUM> that receives the D<<NUM>> and D<<NUM>> signals, for example, from the input circuit <NUM>, and provides an output signal IN_00 that results from a NOR logic operation of the D<<NUM>> and D<<NUM>> signals. The IN_00 signal is provided to an inverter circuit <NUM>. The inverter circuit <NUM> provides an output signal IN_00F that is the complement of the IN_00 signal. The pull-down logic circuit <NUM> further includes a NOR logic circuit <NUM> that receives the IND<<NUM>> and IND<<NUM>> signals, for example from the input circuit <NUM>, and provides an output signal IND_00 resulting from a NOR logic operation on the IND<<NUM>> and IND<<NUM>> signals. A NOR logic circuit receives the IN_00F signal from the inverter circuit <NUM> and the IND_00 signal from the NOR logic circuit <NUM> and provides an output signal PREPD that resulting from a NOR logic operation.

In operation, the logic circuit <NUM> provides an active PREPD signal (e.g., active high logic level) when the data of the IN<<NUM>> and IN<<NUM>> bitstreams changes from a previous value to a current data of "<NUM>". That is, where the previous data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", "<NUM>", or "<NUM>", and the data changes to a current data of "<NUM>", the logic circuit <NUM> provides an active PREPD signal. The logic circuit <NUM> provides and inactive PREPD signal for other changes from a previous data to a current data represented by the IN<<NUM>> and IN<<NUM>> bitstreams. That is, the logic circuit <NUM> provides an inactive PREPD signal for the IN<<NUM>> and IN<<NUM>> bitstreams changing from a previous data to current data of "<NUM>", "<NUM>", or "<NUM>". The active PREPD signal provided by the logic circuit <NUM> may be used to activate a boost circuit, for example, the boost circuit <NUM> of the signal driver <NUM>, to provide additional drive to assist driving the common node to the low supply voltage to provide an OUT signal having a voltage of the low supply voltage. As will be described in more detail below, the PREPD signal is active for a portion of the data period of the OUT signal. For example, in some embodiments of the disclosure, the PREPD signal is limited to being active to assist the driving of the common node to the low supply voltage.

The inverter circuit <NUM> coupled to the NOR logic circuit <NUM> provides a low logic level IN_00F signal when D<<NUM>> and D<<NUM>> are both a low logic level. (i.e., resulting from the IN<<NUM>> and IN<<NUM>> bitstreams representing a current data of "<NUM>"). The NOR logic circuit <NUM> provides a high logic level IND_00 signal when IND<<NUM>> and IND<<NUM>> are both a low logic level (i.e., resulting from D<<NUM>> and D<<NUM>> both a low logic level). Recall that the IND<<NUM>> and IND<<NUM>> are delayed relative to D<<NUM>> and D<<NUM>>, for example, by one-half a clock period of the CLK signal. The NOR logic gate <NUM> provides an active PREPD signal (e.g. active high logic level) when the IN_00F and IND_00 signals have low logic levels. As a result, the PREPD signal is active when D<<NUM>> and D<<NUM>> are both at a low logic level, and for one-half a clock cycle of the CLK signal following a rising edge of the CLK signal. The PREPD signal is active for one-half a clock cycle of the CLK signal because the one-half clock cycle delay of the IND<<NUM>> and IND<<NUM>> relative to D<<NUM>> and D<<NUM>> will result in the IND_00 signal being at a low logic level while the IN_00F signal is at a low logic level (from D<<NUM>> and D<<NUM>> both being a low logic level), but for one-half a clock cycle of the CLK signal before both IND<<NUM>> and IND<<NUM>> also become a low logic level (resulting from the D<<NUM>> and D<<NUM>> both being at the low logic level) and the NOR logic circuit <NUM> provides a high logic level IND_00. As a result, the PREPD signal is active for one-half a clock cycle of the CLK signal.

In some embodiments of the disclosure, the boost circuit <NUM> of the signal driver <NUM> is activated to provide additional drive for data corresponding to both the high supply voltage and the low supply voltage. In such embodiments, the boost control circuit <NUM> and <NUM> may be used together to control the boost circuit <NUM>.

<FIG> is a timing diagram showing various signals during operation of signal driver <NUM> with the input circuit <NUM> and pull-up and pull-down logic circuits <NUM> and <NUM> according to an embodiment of the disclosure. In the present example, the IND<<NUM>> signal is provided to the first driver section <NUM> instead of the IN<<NUM>> bitstream and the IND<<NUM>> signal is provided to the second driver section <NUM> instead of the IN<<NUM>> bitstream. The PREPU and PREPD signals are provided to the boost circuit <NUM> instead of the BoostHi and BoostLo signals. In the example of <FIG>, the output is terminated to a high supply voltage, resulting in "<NUM>" data represented by <NUM> V, "<NUM>" data represented by <NUM> V, "<NUM>" data represented by <NUM> V, and "<NUM>" data represented by <NUM> V. Other embodiments of the disclosure may use other voltage levels to represent the data values.

At time T0 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal (shown in <FIG> as corresponding to a falling edge of the CLKF signal) and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. In the present example, the data at time T0 is "<NUM>". The D flip-flop <NUM> provides a high logic level D<<NUM>> signal and the D flip-flop <NUM> provides a low logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T0. At time T1, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal (corresponding to a falling edge of the CLK signal). The high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal and the low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal (not shown in <FIG>) shortly after time T1. The IND<<NUM>> and IND<<NUM>> signals are provided to the driver circuit <NUM> to cause the pull-up transistors of the first driver section <NUM> to be activated and to cause the pull-down transistors of the second driver section <NUM> to be activated, resulting in providing an OUT signal having an intermediate-high voltage (corresponding to output data of "<NUM>") at time TA. Neither the pull-up nor pull-down transistors of the boost circuit <NUM> are activated by the current data of "<NUM>".

At time T2. the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. The data at time T2 is "<NUM>". The D flip-flop <NUM> maintains a high logic level D<<NUM>> signal and the D flip-flop <NUM> provides a high logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T2. The NAND logic circuit <NUM> of the pull-up logic circuit <NUM> provides a low logic level IN_11F signal due to the high logic levels of the D<<NUM>> and D<<NUM>> signals. With the IND_11 signal provided by the inverter circuit <NUM> still at a low logic level from the previous data of "<NUM>", the XOR logic circuit <NUM> provides an active PREPU signal at time TB. The active PREPU signal activates the pull-up transistor of the boost circuit <NUM> to provide additional drive to pull up the common node in providing the OUT signal.

At time T3, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal. The high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to maintain a high logic level IND<<NUM>> signal and the high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal (not shown in <FIG>) shortly after time T3. The IND<<NUM>> and IND<<NUM>> signals are provided to the signal driver <NUM> to cause the pull-up transistors of the first driver section <NUM> to be activated and to cause the pull-up transistors of the second driver section <NUM> to be activated, along with the activated pull-up transistor of the boost circuit <NUM> that provides additional drive to the common node. As a result, an OUT signal is provided having a voltage of the high supply voltage (corresponding to output data of "<NUM>") at time TC.

After the IND<<NUM>> and IND<<NUM>> signals propagate through the NAND logic circuit <NUM> and the inverter circuit <NUM> of the pull-up logic circuit <NUM>, the IND_11 signal switches to a high logic level, which causes the XOR logic circuit <NUM> to provide an inactive PREPU signal. The change of the PREPU signal to inactive deactivates the pull-up transistor of the boost circuit <NUM>. Thus, when the present data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", the boost circuit <NUM> provides additional drive to pull up the common node to the high supply voltage for a portion of the data period of the OUT signal, for example, during the transition of the OUT signal to the high supply voltage. The voltage of the OUT signal changes during the transition from one voltage level to another.

At time T4 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. The data at time T4 is "<NUM>". The D flip-flop <NUM> provides a low logic level D<<NUM>> signal and the D flip-flop <NUM> provides a low logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T4. The inverter circuit <NUM> of the pull-down logic circuit <NUM> provides a low logic level IN_00F signal when the NOR logic circuit <NUM> receives low logic level D<<NUM>> and D<<NUM>> signals. At this time, the IND_00 signal provided by the NAND logic circuit <NUM> is still at a low logic level from the previous data of "<NUM>", which results in the NOR logic circuit <NUM> providing an active PREPD signal at time TD. The active PREPD signal activates the pull-down transistor of the boost circuit <NUM> to provide additional drive to pull down the common node in providing the OUT signal.

At time T5, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal. The low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal and the low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal (not shown in <FIG>) shortly after time T5. The IND<<NUM>> and IND<<NUM>> signals are provided to the signal driver <NUM> to cause the pull-down transistors of the first driver section <NUM> to be activated and to cause the pull-down transistors of the second driver section <NUM> to be activated, along with the activated pull-down transistor of the boost circuit <NUM> that provides additional drive to the common node. As a result, an OUT signal is provided having a voltage of the low supply voltage (corresponding to output data of "<NUM>") at time TE.

After the IND<<NUM>> and IND<<NUM>> signals propagate through the NOR logic circuit <NUM> of the pull-down logic circuit <NUM>, the IND_00 signal switches to a high logic level, which causes the XOR logic circuit <NUM> to provide an inactive PREPD signal. The change of the PREPD signal to inactive deactivates the pull-down transistor of the boost circuit <NUM>. Thus, when the present data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", the boost circuit <NUM> provides additional drive to pull down the common node to the low supply voltage for a portion of the data period of the OUT signal, for example, during the transition of the OUT signal to the low supply voltage. As previously described, the voltage of the OUT signal changes during the transition from one voltage level to another.

At time T6 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. The data at time T6 is "<NUM>". The D flip-flop <NUM> provides a high logic level D<<NUM>> signal and the D flip-flop <NUM> provides a high logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T6. The pull-up logic circuit <NUM> responds by providing an active PREPU signal at time TF to activate the pull-up transistor of the boost circuit <NUM> to provide additional drive to pull up the common node in providing the OUT signal.

At time T7, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal. The high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal and the high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal (not shown in <FIG>) shortly after time T7. The pull-up transistors of the first and second driver sections <NUM> and <NUM> of the signal driver circuit <NUM> are activated, along with the activated pull-up transistor of the boost circuit <NUM> to drive the common node to the voltage of the high supply voltage and provide an OUT signal having a voltage of the high supply voltage (corresponding to output data of "<NUM>") at time TG. After the IND<<NUM>> and IND<<NUM>> signals propagate through the NAND logic circuit <NUM> and the inverter circuit <NUM> of the pull-up logic circuit <NUM>, the IND_11 signal switches to a high logic level and the XOR logic circuit <NUM> provides an inactive PREPU signal. The inactive PREPU signal deactivates the pull-up transistor of the boost circuit <NUM>.

At time T8 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. The data at time T8 is "<NUM>". The D flip-flop <NUM> provides a low logic level D<<NUM>> signal and the D flip-flop <NUM> provides a high logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T8. At time T9, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal. The low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal and the high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal (not shown in <FIG>) shortly after time T9. The IND<<NUM>> and IND<<NUM>> signals are provided to the signal driver <NUM> to cause the pull-down transistors of the first driver section <NUM> to be activated and to cause the pull-up transistors of the second driver section <NUM> to be activated, resulting in providing an OUT signal having an intermediate-low voltage (corresponding to output data of "<NUM>") at time TH. Neither the pull-up nor pull-down transistors of the boost circuit <NUM> are activated by the current data of "<NUM>".

<FIG> is a schematic diagram of a pull-up logic circuit <NUM> according to an embodiment of the disclosure. The pull-up logic circuit <NUM> may be included in the boost control circuit <NUM> of <FIG> in some embodiments of the disclosure. The pull-up logic circuit <NUM> includes a NAND logic circuit <NUM> that receives the D<<NUM>> and INDF<<NUM>> signals. The input circuit <NUM> may provide the D<<NUM>> signal, and the input circuit <NUM> may further provide an IND<<NUM>> signal. The INDF<<NUM>> signal is the complement of the IND<<NUM>> signal, and may be provided by an inverter circuit (not shown) that receives the IND<<NUM>> signal from the input circuit <NUM> and provides the INDF<<NUM>> signal. The NAND logic circuit <NUM> provides an output signal ndpu0 that results from a NAND logic operation of the D<<NUM>> and INDF<<NUM>> signals. The pull-up logic circuit <NUM> further includes NAND logic circuits <NUM> and <NUM>. The NAND logic circuit <NUM> receives the D<<NUM>>, INDF<<NUM>>, INDF<<NUM>> signals. The input circuit <NUM> may provide the D<<NUM>> signal, and the input circuit <NUM> may further provide a IND<<NUM>> signal. The INDF<<NUM>> signal is the complement of the IND<<NUM>> signal, and may be provided by an inverter circuit (not shown) that receives the IND<<NUM>> signal from the input circuit <NUM> and provides the INDF<<NUM>> signal. The NAND logic circuit <NUM> provides an output signal ndpu1 that results from a NAND logic operation of the D<<NUM>>, INDF<<NUM>>, and INDF<<NUM>> signals. The NAND logic circuit <NUM> receives the D<<NUM>>, D<<NUM>>, and INDF<<NUM>> signals. The NAND logic circuit <NUM> provides an output signal ndpu2 that results from a NAND logic operation of the D<<NUM>>, D<<NUM>>, and INDF<<NUM>> signals. A NAND logic circuit <NUM> receives the ndpu0, ndpu1, and ndpu2 signals from the NAND logic circuits <NUM>, <NUM>, and <NUM> and provides an output signal PREPU that results from a NAND logic operation. The PREPU signal may be used to control the pull-up transistor of the boost circuit <NUM>.

In operation, the pull-up logic circuit <NUM> provides an active PREPU signal (e.g., active high logic level) when the data of the IN<<NUM>> and IN<<NUM>> bitstreams changes from a previous data to a current data that is represented by a higher voltage than the previous data. That is, where the previous data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", the pull-up logic circuit <NUM> provides an active PREPU signal for a current data of "<NUM>", "<NUM>", and "<NUM>"; where the previous data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", the pull-up logic circuit <NUM> provides an active PREPU signal for a current data of "<NUM>" and "<NUM>"; and where the previous data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", the pull-up logic circuit <NUM> provides an active PREPU signal for a current data of "<NUM>". The active PREPU signal provided by the logic circuit <NUM> may be used to activate a boost circuit, for example, the boost circuit <NUM> of the signal driver <NUM>, to provide additional drive to assist driving the common node to a higher voltage to provide an OUT signal. As will be described in more detail below, the PREPU signal is active for a portion of the data period of the OUT signal. For example, in some embodiments of the disclosure, the PREPU signal is limited to being active to assist the driving of the common node during a transition to a higher voltage when changing to current data that is represented by a higher voltage than the previous data. That is, the voltage of the OUT signal changes during the transition from one voltage level to another.

<FIG> is a schematic diagram of a pull-down logic circuit <NUM> according to an embodiment of the disclosure. The pull-down logic circuit <NUM> may be included in the boost control circuit <NUM> of <FIG> in some embodiments of the disclosure. The pull-down logic circuit <NUM> includes a NAND logic circuit <NUM> that receives the IND<<NUM>> and DDF<<NUM>> signals. The input circuit <NUM> may provide the IND<<NUM>> signal, and the input circuit <NUM> may further provide a D<<NUM>> signal. The DDF<<NUM>> signal is the complement of the D<<NUM>> signal, and may be provided by an inverter circuit (not shown) that receives the D<<NUM>> signal from the input circuit <NUM> and provides the DDF<<NUM>> signal. The NAND logic circuit <NUM> provides an output signal ndpd0 that results from a NAND logic operation of the DDF<<NUM>> and IND<<NUM>> signals. The pull-down logic circuit <NUM> further includes NAND logic circuits <NUM> and <NUM>. The NAND logic circuit <NUM> receives the IND<O>, DDF<<NUM>>, DDF<<NUM>> signals. The input circuit <NUM> may provide the IND<<NUM>> signal, and the input circuit <NUM> may further provide a D<<NUM>> signal. The DDF<<NUM>> signal is the complement of the D<<NUM>> signal, and may be provided by an inverter circuit (not shown) that receives the D<<NUM>> signal from the input circuit <NUM> and provides the DDF<<NUM>> signal. The NAND logic circuit <NUM> provides an output signal ndpd1 that results from a NAND logic operation of the IND<<NUM>>, DDF<<NUM>>, and DDF<<NUM>> signals. The NAND logic circuit <NUM> receives the IND<<NUM>>, IND<<NUM>>, and DDF<<NUM>> signals. The NAND logic circuit <NUM> provides an output signal ndpd2 that results from a NAND logic operation of the IND<<NUM>>, IND<<NUM>>, and DDF<<NUM>> signals. A NAND logic circuit <NUM> receives the ndpd0, ndpd1, and ndpd2 signals from the NAND logic circuits <NUM>, <NUM>, and <NUM> and provides an output signal PREPD that results from a NAND logic operation. The PREPD signal may be used to control the pull-down transistor of the boost circuit <NUM>.

In operation, the pull-down logic circuit <NUM> provides an active PREPD signal (e.g., active high logic level) when the data of the IN<<NUM>> and IN<<NUM>> bitstreams changes from a previous data to a current data that is represented by a lower voltage than the previous data. That is, where the previous data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", the pull-down logic circuit <NUM> provides an active PREPD signal for a current data of "<NUM>", "<NUM>", and "<NUM>"; where the previous data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", the pull-down logic circuit <NUM> provides an active PREPD signal for a current data of "<NUM>" and "<NUM>"; and where the previous data represented by the IN<<NUM>> and IN<<NUM>> bitstreams is "<NUM>", the pull-up logic circuit <NUM> provides an active PREPD signal for a current data of "<NUM>". The active PREPD signal provided by the logic circuit <NUM> may be used to activate a boost circuit, for example, the boost circuit <NUM> of the signal driver <NUM>, to provide additional drive to assist driving the common node to a lower voltage to provide an OUT signal. As will be described in more detail below, the PREPD signal is active for a portion of the data period of the OUT signal. For example, in some embodiments of the disclosure, the PREPD signal is limited to being active to assist the driving of the common node during a transition to a lower voltage when changing to current data that is represented by a lower voltage than the previous data. That is, the voltage of the OUT signal changes during the transition from one voltage level to another.

At time T0 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal (shown in <FIG> as corresponding to a falling edge of the CLKF signal) and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. In the present example, the previous data prior to time T0 is "<NUM>" and the current data at time T0 is "<NUM>". Latching of the current data "<NUM>" results in the D flip-flop <NUM> providing a high logic level D<<NUM>> signal and the D flip-flop <NUM> providing a low logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T0. With reference to the pull-up logic circuit <NUM>, the INDF<<NUM>> is at a high logic level and the INDF<<NUM>> signal is at a low logic level based on the previous data due to the D flip-flops <NUM> and <NUM> of the input circuit not yet clocked by a rising edge of the CLKF signal. As a result, the NAND logic circuit <NUM> provides an active PREPU signal at time TA. The active PREPU signal activates the pull-up transistor of the boost circuit <NUM> to provide additional drive to pull up the common node in providing the OUT signal. As previously described, the boost circuit <NUM> is activated to assist with driving the common node to a higher voltage when the data of the IN<<NUM>> and IN<<NUM>> bitstreams changes from a previous data to a current data that is represented by a higher voltage than the previous data, such as in the present example where the previous data was "<NUM>" and the current data is "<NUM>".

At time T1, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal (corresponding to a falling edge of the CLK signal). The high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal (also resulting in a low logic level INDF<<NUM>> signal) and the low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal (not shown in <FIG>, also resulting in a high logic level INDF<<NUM>> signal) shortly after time T1. The IND<<NUM>> and IND<<NUM>> signals are provided to the signal driver <NUM> to cause the pull-up transistors of the first driver section <NUM> to be activated and to cause the pull-down transistors of the second driver section <NUM> to be activated, along with the activated pull-up transistor of the boost circuit <NUM> that provides additional drive to the common node. As a result, an OUT signal is provided having an intermediate-high voltage (corresponding to output data of "<NUM>") at time TB. After the INDF<<NUM>> and INDF<<NUM>> signals propagate through the NAND logic circuits <NUM>, <NUM>, <NUM>, and <NUM> of the pull-up logic circuit <NUM>, the PREPU signal changes to inactive. The change of the PREPU signal to inactive deactivates the pull-up transistor of the boost circuit <NUM>. Thus, when the current data is represented by a higher voltage than the previous data, the boost circuit <NUM> provides additional drive to pull up the common node for a portion of the data period of the OUT signal, for example, during the transition of the OUT signal to a higher voltage. The voltage of the OUT signal changes during the transition from one voltage level to another.

At time T2 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. In the present example, the previous data prior to time T2 is "<NUM>" and the current data at time T2 is "<NUM>". Latching of the current data "<NUM>" results in the D flip-flop <NUM> providing a high logic level D<<NUM>> signal and the D flip-flop <NUM> providing a high logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T2. The INDF<I> is at a low logic level and the INDF<<NUM>> signal is at a high logic level based on the previous data due to the D flip-flops <NUM> and <NUM> of the input circuit not yet clocked by a rising edge of the CLKF signal. As a result, the NAND logic circuit <NUM> provides an active PREPU signal at time TC to activate the pull-up transistor of the boost circuit <NUM> and provide additional drive to pull up the common node in providing the OUT signal. The activated boost circuit <NUM> assists with driving the common node to a higher voltage of the current data "<NUM>" from the voltage of the previous data "<NUM>".

At time T3, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal. The high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal (also resulting in a low logic level INDF<<NUM>> signal) and the high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal (not shown in <FIG>, also resulting in a low logic level INDF<<NUM>> signal) shortly after time T3. The IND<<NUM>> and IND<<NUM>> signals are provided to the signal driver <NUM> to cause the pull-up transistors of the first and second driver sections <NUM> and <NUM> to be activated, along with the activated pull-up transistor of the boost circuit <NUM> that provides additional drive to the common node. As a result, an OUT signal is provided having the high supply voltage (corresponding to output data of "<NUM>") at time TD. After the INDF<<NUM>> and INDF<<NUM>> signals propagate through the NAND logic circuits <NUM>, <NUM>, <NUM>, and <NUM> of the pull-up logic circuit <NUM>, the PREPU signal changes to inactive to deactivate the pull-up transistor of the boost circuit <NUM> after providing additional drive to pull up the common node during the transition of the OUT signal to a higher voltage. The voltage of the OUT signal changes during the transition from one voltage level to another.

At time T4 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. In the present example, the previous data prior to time T4 is "<NUM>" and the current data at time T4 is "<NUM>". Latching of the current data "<NUM>" results in the D flip-flop <NUM> providing a low logic level D<<NUM>> signal and the D flip-flop <NUM> providing a low logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T4. Due to the complementary nature of the DDF<<NUM>> and DDF<<NUM>> signals, the DDF<<NUM>> signal is a high logic level and the DDF<<NUM>> signal is a high logic level. With reference to the pull-down logic circuit <NUM>, the IND<<NUM>> is at a high logic level and the IND<<NUM>> signal is at a high logic level based on the previous data due to the D flip-flops <NUM> and <NUM> of the input circuit not yet clocked by a rising edge of the CLKF signal. As a result, the NAND logic circuit <NUM> provides an active PREPD signal at time TE to activate the pull-down transistor of the boost circuit <NUM> and provide additional drive to pull down the common node in providing the OUT signal. The activated boost circuit <NUM> assists with driving the common node to a lower voltage of the current data "<NUM>" from the voltage of the previous data "<NUM>".

At time T5, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal. The low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal and the low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal (not shown in <FIG>) shortly after time T5. The IND<<NUM>> and IND<<NUM>> signals are provided to the signal driver <NUM> to cause the pull-down transistors of the first and second driver sections <NUM> and <NUM> to be activated, along with the activated pull-down transistor of the boost circuit <NUM> that provides additional drive to the common node. As a result, an OUT signal is provided having a voltage of the low supply voltage (corresponding to output data of "<NUM>") at time TF. After the IND<<NUM>> and IND<<NUM>> signals propagate through the NAND logic circuits <NUM>, <NUM>, <NUM>, and <NUM> of the pull-down logic circuit <NUM>, the PREPD signal changes to inactive. The change of the PREPD signal to inactive deactivates the pull-down transistor of the boost circuit <NUM>. Thus, when the current data is represented by a lower voltage than the previous data, the boost circuit <NUM> provides additional drive to pull down the common node for a portion of the data period of the OUT signal, for example, during the transition of the OUT signal to a lower voltage. The voltage of the OUT signal changes during the transition from one voltage level to another.

At time T6 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. In the present example, the previous data prior to time T6 is "<NUM>" and the current data at time T6 is "<NUM>". Latching of the current data "<NUM>" results in the D flip-flop <NUM> providing a high logic level D<<NUM>> signal and the D flip-flop <NUM> providing a low logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T6. Additionally, the DDF<<NUM>> signal is a low logic level and the DDF<<NUM>> signal is a high logic level. The IND<<NUM>> is at a high logic level and the IND<<NUM>> signal is at a high logic level based on the previous data due to the D flip-flops <NUM> and <NUM> of the input circuit not yet clocked by a rising edge of the CLKF signal. As a result, the NAND logic circuit <NUM> provides an active PREPD signal at time TG to activate the pull-down transistor of the boost circuit <NUM> and provide additional drive to pull down the common node in providing the OUT signal. The activated boost circuit <NUM> assists with driving the common node to a lower voltage of the current data "<NUM>" from the voltage of the previous data "<NUM>".

At time T7, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal. The high logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a high logic level IND<<NUM>> signal and the low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal (not shown in <FIG>) shortly after time T7. The IND<<NUM>> and IND<<NUM>> signals are provided to the signal driver <NUM> to cause the pull-up transistors of the first driver section <NUM> to be activated and the pull-down transistors of the second driver section <NUM> to be activated, along with the activated pull-down transistor of the boost circuit <NUM> that provides additional drive to the common node. As a result, an OUT signal is provided having an intermediate-high voltage (corresponding to output data of "<NUM>") at time TH. After the IND<<NUM>> and IND<<NUM>> signals propagate through the NAND logic circuits <NUM>, <NUM>, <NUM>, and <NUM> of the pull-down logic circuit <NUM>, the PREPD signal changes to inactive. The change of the PREPD signal to inactive deactivates the pull-down transistor of the boost circuit <NUM>. Thus, when the current data is represented by a lower voltage than the previous data, the boost circuit <NUM> provides additional drive to pull down the common node for a portion of the data period of the OUT signal, for example, during the transition of the OUT signal to a lower voltage. The voltage of the OUT signal changes during the transition from one voltage level to another.

At time T8 the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLK signal and the data of the IN<<NUM>> and IN<<NUM>> bitstreams is latched to provide the D<<NUM>> and D<<NUM>> signals. In the present example, the previous data prior to time T8 is "<NUM>" and the current data at time T8 is "<NUM>". Latching of the current data "<NUM>" results in the D flip-flop <NUM> providing a low logic level D<<NUM>> signal and the D flip-flop <NUM> providing a low logic level D<<NUM>> signal (not shown in <FIG>) shortly after time T8. Additionally, the DDF<<NUM>> signal is a high logic level and the DDF<<NUM>> signal is a high logic level. The IND<<NUM>> is at a high logic level and the IND<<NUM>> signal is at a low logic level based on the previous data due to the D flip-flops <NUM> and <NUM> of the input circuit not yet clocked by a rising edge of the CLKF signal. As a result, the NAND logic circuit <NUM> provides an active PREPD signal at time TI to activate the pull-down transistor of the boost circuit <NUM> and provide additional drive to pull down the common node in providing the OUT signal. The activated boost circuit <NUM> assists with driving the common node to a lower voltage of the current data "<NUM>" from the voltage of the previous data "<NUM>".

At time T9, the D flip-flops <NUM> and <NUM> of the input circuit <NUM> are clocked by a rising edge of the CLKF signal. The low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal and the low logic level of the D<<NUM>> signal is latched by the D flip-flop <NUM> to provide a low logic level IND<<NUM>> signal (not shown in <FIG>) shortly after time T9. The IND<<NUM>> and IND<<NUM>> signals are provided to the signal driver <NUM> to cause the pull-down transistors of the first and second driver sections <NUM> and <NUM> to be activated, along with the activated pull-down transistor of the boost circuit <NUM> that provides additional drive to the common node. As a result, an OUT signal is provided having a voltage of the low supply voltage (corresponding to output data of "<NUM>") at time TJ. After the IND<<NUM>> and IND<<NUM>> signals propagate through the NAND logic circuits <NUM>, <NUM>, <NUM>, and <NUM> of the pull-down logic circuit <NUM>, the PREPD signal changes to inactive. The change of the PREPD signal to inactive deactivates the pull-down transistor of the boost circuit <NUM>. Thus, when the current data is represented by a lower voltage than the previous data, the boost circuit <NUM> provides additional drive to pull down the common node for a portion of the data period of the OUT signal, for example, during the transition of the OUT signal to a lower voltage. The voltage of the OUT signal changes during the transition from one voltage level to another.

In some embodiments of the disclosure, PAM8 is used to convert three bitstreams (e.g., IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams) into an OUT output signal having one of eight different voltage levels.

<FIG> is a schematic diagram of a signal driver <NUM> according to an embodiment of the disclosure. The signal driver <NUM> may be used for a multilevel signal architecture implementing PAM8 encoding. The driver circuit <NUM> may be included in the driver circuit <NUM> of <FIG> in embodiments of the disclosure. The signal driver <NUM> includes a driver circuit including seven line drivers coupled to a common node that is an output. Each of the signal line drivers are coupled to a high supply voltage (e.g., VDDQ) and to a low supply voltage (e.g., VSSQ). The signal driver <NUM> may be a driver in a DRAM, such as a double data rate (DDR) DRAM driver. In some embodiments of the disclosure, each of the signal line drivers has an impedance of <NUM> ohms.

The driver circuit <NUM> may include a first driver section <NUM>, a second driver section <NUM>, and a third driver section <NUM> configured to drive an output signal OUT to a common node to which the first, second, and third driver sections <NUM>, <NUM>, and <NUM> are coupled. A signal line may be coupled to the common node. The output signal OUT may be driven by the first, second, and third driver sections <NUM>, <NUM>, and <NUM> based on IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams. As will be described in more detail below, signals DD<<NUM>>, DD<<NUM>>, and DD<<NUM>>, which are based on the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams, respectively, may be provided to the signal line drivers of the driver circuit <NUM>. The output signal OUT may be a multilevel signal representing data of the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams that drives the I/O bus. In some embodiments of the disclosure, "<NUM>" data is represented by the IN<<NUM>> signal, IN<<NUM>> signal, or IN<<NUM>> signal having a voltage of <NUM> V, and "<NUM>" data is represented by the IN<<NUM>>, IN<<NUM>> signal, or IN<<NUM>> signal having a voltage of <NUM> V. However, other voltage levels may be used to represent the "<NUM>" and "<NUM>" data in other embodiments of the disclosure.

The first driver section <NUM> may include four signal line drivers coupled to the common node, each controlled responsive to the DD<<NUM>> signal. Each signal line driver may include a pull-up (e.g., p-type) transistor and a pull-down (e.g., n-type) transistor. The second driver section <NUM> may include two signal line drivers coupled to the common node, each controlled responsive to the DD<<NUM>> signal, and each signal line driver may include a pull-up (e.g., p-type) transistor and a pull-down (e.g., n-type) transistor. The third driver section <NUM> may include one signal line driver coupled to the common node and controlled responsive to the DD<<NUM>> signal. The signal line driver of the third driver section <NUM> may include a pull-up (e.g., p-type) transistor and a pull-down (e.g., n-type) transistor. In an embodiment of the disclosure, where each signal line driver has an impedance of <NUM> ohms, the first driver section <NUM> has an effective impedance of <NUM> ohms, the second driver section <NUM> has an effective impedance of <NUM> ohms, and the third driver section <NUM> has an effective impedance of <NUM> ohms.

The signal driver <NUM> further includes a boost circuit <NUM> that receives control signals PREPU and PREPD from boost control circuit <NUM>. The boost control circuit <NUM> includes logic circuits and provides control signals PREPU and PREPD to the signal driver <NUM> based on the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams. The boost circuit <NUM> is coupled to the common node and includes a pull-up (e.g., p-type) transistor and a pull-down (e.g., n-type) transistor, which are controlled by the PREPU and PREPD signals, respectively. In the embodiment of <FIG>, the PREPU signal is active when at a high logic level to activate the pull-up transistor and the PREPD signal is active when at a high logic level to activate the pull-down transistor. When activated by an active PREPU signal from the boost control circuit <NUM>, the pull-up transistor provides additional drive to pull up the level of the signal line. Similarly, when activated by an active PREPD signal from the boost control circuit <NUM>, the pull-down transistor provides additional drive to pull down the level of the signal line. In some embodiments of the disclosure, a PREPU signal or PREPD signal having the high logic level is represented by a signal of <NUM> V, and a PREPU signal or PREPD signal having the low logic level is represented by a signal of <NUM> V. However, other voltage levels may be used to represent the "<NUM>" and "<NUM>" data in other embodiments of the disclosure.

As will be described in more detail below, the pull-up transistor of the boost circuit <NUM> may be activated when the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams represent data corresponding to a voltage level of a high supply voltage (e.g., representing data "<NUM>"), and the pull-down transistor may be activated when the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams represent data corresponding to a voltage level of a low supply voltage (e.g., representing data "<NUM>"). While <FIG> shows the boost circuit <NUM> as including one pull-up transistor and one pull-down transistor, in other embodiments of the disclosure, the boost circuit <NUM> may include a greater number of pull-up and/or pull-down transistors. Thus, the embodiment of <FIG> is not intended to limit boost circuits, or more generally, driver circuits, to embodiments of the disclosure having the specific configuration shown in <FIG>.

In operation, the signal driver <NUM> may drive the OUT signal responsive to the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams. The DD<<NUM>>, DD<<NUM>>, DD<<NUM>> signals, which are based on the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams, are provided to the signal line drivers of the driver sections <NUM>, <NUM>, and <NUM> to provide an output signal OUT having appropriate voltage for the multilevel signal, for example, using PAM to convert a plurality of bitstreams into a multilevel signal.

In some embodiments of the disclosure, PAM8 is used to convert three bitstreams (e.g., the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams) into an OUT signal having one of eight different voltage levels. By way of the DD<<NUM>> signal, the IN<<NUM>> bitstream may be provided to the signal line drivers of the first driver section <NUM>; by way of the DD<<NUM>> signal, the IN<<NUM>> bitstream may be provided to the signal line drivers of the second driver section <NUM>; and by way of the DD<<NUM>> signal, the IN<<NUM>> bitstream may be provided to the signal line drivers of the third driver section <NUM>. The resulting output signal will have one of eight different voltages corresponding to the data of the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams.

For example, where a current data of the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams is a "<NUM>", the pull-down transistors of the driver sections <NUM>, <NUM>, and <NUM> are activated to pull down the common node to the low supply voltage to provide an output signal OUT having the voltage of the low supply voltage. Where a current data of the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstream is a "<NUM>", the pull-up transistors of the driver sections <NUM>, <NUM>, and <NUM> are activated to pull up the common node to the high supply voltage to provide an output signal OUT having the voltage of the high supply voltage. The six other data represented by the three bits may have intermediate voltages between the high and low supply voltages.

The first driver section <NUM>, the second driver section <NUM>, the third driver section <NUM>, and the boost circuit <NUM> are shown in <FIG> as including p-type pull-up transistors and n-type pull-down transistors. That is, the pull-up and pull-down transistors have different conductivity types. In other embodiments of the disclosure, the first driver section <NUM>, the second driver section <NUM>, and the boost circuit <NUM> may include n-type pull-up transistors, or a combination of p-type and n-type pull-up transistors. In embodiments of the disclosure using n-type pull-up transistors, which are activated by a high logic level signal (e.g., having the high supply voltage), the logic level of the signals provided to gates of the n-type pull-up transistors will have a complementary logic level to signals provided to the gates of p-type pull-up transistors. A signal having a complementary logic level may be provided by using an inverter circuit.

<FIG> is a schematic diagram of an input circuit <NUM> according to an embodiment of the disclosure. The input circuit <NUM> may be included in the input circuit <NUM> of <FIG> for some embodiments of the disclosure. The input circuit <NUM> includes D flip-flop circuits <NUM> and <NUM>, D flip-flop circuits <NUM> and <NUM>, and D flip-flop circuits <NUM> and <NUM>. The D flip-flop circuit <NUM> receives the IN<<NUM>> bitstream, the D flip-flop circuit <NUM> receives the IN<<NUM>> bitstream and the D flip-flop circuit <NUM> receives the IN<<NUM>> bitstream. The D flip-flop circuits <NUM>, <NUM>, and <NUM> are clocked by a clock signal CLK. The D flip-flop circuits <NUM>, <NUM>, and <NUM> are clocked by a clock signal CLKF, which is the complement to the CLK signal. The D flip-flop circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be reset to provide an output having a known logic level when an active reset signal RST is provided to the D flip-flop circuits. The D flip-flop circuits <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be reset, for example, upon reset of the semiconductor device, as part of a power up sequence, etc..

In operation, the D flip-flop circuit <NUM> latches a current logic level of the IN<<NUM>> bitstream responsive to a rising edge of the CLK signal and provides an output signal D<<NUM>> having the same logic level as the latched logic level. The D flip-flop circuit <NUM> latches the logic level of the D<<NUM>> signal responsive to a rising edge of the CLKF signal and provides an output signal DD<<NUM>> having the same logic level as the latched logic level. The D flip-flop circuit <NUM> latches a current logic level of the IN<<NUM>> bitstream responsive to a rising edge of the CLK signal and provides an output signal D<<NUM>> having the same logic level as the latched logic level. The D flip-flop circuit <NUM> latches the logic level of the D<<NUM>> signal responsive to a rising edge of the CLKF signal and provides an output signal DD<<NUM>> having the same logic level as the latched logic level. Likewise, the D flip-flop circuit <NUM> latches a current logic level of the IN<<NUM>> bitstream responsive to a rising edge of the CLK signal and provides an output signal D<<NUM>> having the same logic level as the latched logic level. The D flip-flop circuit <NUM> latches the logic level of the D<<NUM>> signal responsive to a rising edge of the CLKF signal and provides an output signal DD<<NUM>> having the same logic level as the latched logic level. As previously described, the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals, which are based on the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams, are provided to the driver sections <NUM>, <NUM>, and <NUM>, all respectively, of the signal driver <NUM>.

With reference to the CLK signal, the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams are latched and the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals provided responsive to a rising edge of the CLK signal, and the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals are latched and the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals are provided responsive to a falling edge of the CLK signal (i.e., the rising edge of the CLKF signal). Thus, the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals have the logic levels of the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals delayed by one-half a clock period of the CLK signal.

<FIG> is a schematic diagram of a pull-up logic circuit <NUM> according to an embodiment of the disclosure. The pull-up logic circuit <NUM> may be included in the boost control circuit <NUM> of <FIG> in some embodiments of the disclosure. The pull-up logic circuit <NUM> includes a NAND logic circuit <NUM> that receives the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals, for example, from the input circuit <NUM>, and provides an output signal D_1 11F that results from a NAND logic operation of the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals. "The pull-up logic circuit <NUM> further includes a NAND logic circuit <NUM> that receives the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals, for example from the input circuit <NUM>. The NAND logic circuit <NUM> provides an output signal DD_111F resulting from a NAND logic operation on the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals to an inverter circuit <NUM>. The inverter circuit <NUM> provides an output signal DD_111 that is the complement of the DD_111F signal. A NOR logic circuit receives the D_111F signal from the NAND logic circuit <NUM> and the DD_111 signal from the inverter circuit <NUM> and provides an output signal PREPU that results from a NOR logic operation.

In operation, the logic circuit <NUM> provides an active PREPU signal (e.g., active high logic level) when the data of the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams changes from a previous value to a current data of "<NUM>". That is, where the previous data represented by the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams is "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>", or "<NUM>", and the data changes to a current data of "<NUM>", the logic circuit <NUM> provides an active PREPU signal. The logic circuit <NUM> provides an inactive PREPU signal for other changes from a previous data to a current data represented by the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams. That is, the logic circuit <NUM> provides an inactive PREPU signal for the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams changing from a previous data to current data of "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>", or "<NUM>". The active PREPU signal provided by the logic circuit <NUM> may be used to activate a boost circuit, for example, the boost circuit <NUM> of the signal driver <NUM>, to provide additional drive to assist driving the common node to the high supply voltage to provide an OUT signal having a voltage of the high supply voltage. The PREPU signal is active for a portion of the data period of the OUT signal. For example, in some embodiments of the disclosure, the PREPU signal is limited to being active to assist the driving of the common node to the high supply voltage.

The NAND logic circuit <NUM> provides a low logic level D_111F signal when D<<NUM>>, D<<NUM>>, and D<<NUM>> are all a high logic level (i.e., resulting from the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams representing a current data of "<NUM>"). The inverter circuit <NUM> coupled to the NAND logic circuit <NUM> provides a low logic level DD_111 when DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals are all a high logic level (i.e., resulting from D<<NUM>>, D<<NUM>>, and D<<NUM>> all a high logic level). Recall that the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals are delayed relative to the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals, for example, by one-half a clock period of the CLK signal. The NOR logic gate <NUM> provides an active PREPU signal (e.g. active high logic level) when the D_111F and DD_111 signals have low logic levels. As a result, the PREPU signal is active when the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals are at a high logic level, and for one-half a clock cycle of the CLK signal following a rising edge of the CLK signal. The PREPU signal is active for one-half a clock cycle of the CLK signal because the one-half clock cycle delay of the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals relative to the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals will result in the DD_111 signal being at a low logic level while the D_111F signal is at a low logic level (from D<<NUM>>, D<<NUM>>, and D<<NUM>> being a high logic level), but for one-half a clock cycle of the CLK signal before DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> also become a high logic level (resulting from the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals being at the high logic level). As a result, the PREPU signal is active for one-half a clock cycle of the CLK signal.

<FIG> is a schematic diagram of a pull-down logic circuit <NUM> according to an embodiment of the disclosure. The pull-down logic circuit <NUM> may be included in the boost control circuit <NUM> of <FIG> in some embodiments of the disclosure. The pull-down logic circuit <NUM> includes a NOR logic circuit <NUM> that receives the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals, for example, from the input circuit <NUM>, and provides an output signal D_000 that results from a NOR logic operation of the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals. The D_000 signal is provided to an inverter circuit <NUM>. The inverter circuit <NUM> provides an output signal D_000F that is the complement of the D_000 signal. The pull-down logic circuit <NUM> further includes a NOR logic circuit <NUM> that receives the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals, for example from the input circuit <NUM>, and provides an output signal DD_000 resulting from a NOR logic operation on the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals. A NOR logic circuit <NUM> receives the D_000F signal from the inverter circuit <NUM> and the DD_000 signal from the NOR logic circuit <NUM> and provides an output signal PREPD that resulting from a NOR logic operation.

In operation, the logic circuit <NUM> provides an active PREPD signal (e.g., active high logic level) when the data of the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams changes from a previous value to a current data of "<NUM>". That is, where the previous data represented by the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams is "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>", or "<NUM>", and the data changes to a current data of "<NUM>", the logic circuit <NUM> provides an active PREPD signal. The logic circuit <NUM> provides an inactive PREPD signal for other changes from a previous data to a current data represented by the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams. That is, the logic circuit <NUM> provides an inactive PREPD signal for the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams changing from a previous data to current data of "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>", "<NUM>", or "<NUM>". The active PREPD signal provided by the logic circuit <NUM> may be used to activate a boost circuit, for example, the boost circuit <NUM> of the signal driver <NUM>, to provide additional drive to assist driving the common node to the low supply voltage to provide an OUT signal having a voltage of the low supply voltage. As will be described in more detail below, the PREPD signal is active for a portion of the data period of the OUT signal. For example, in some embodiments of the disclosure, the PREPD signal is limited to being active to assist the driving of the common node to the low supply voltage.

The inverter circuit <NUM> coupled to the NOR logic circuit <NUM> provides a low logic level D_000F signal when D<<NUM>>, D<<NUM>>, and D<<NUM>> are all a low logic level (i.e., resulting from the IN<<NUM>>, IN<<NUM>>, and IN<<NUM>> bitstreams representing a current data of "<NUM>"). The NOR logic circuit <NUM> provides a high logic level DD_000 signal when DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> are all a low logic level (i.e., resulting from D<<NUM>>, D<<NUM>>, and D<<NUM>> all a low logic level). Recall that the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals are delayed relative to the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals, for example, by one-half a clock period of the CLK signal. The NOR logic gate <NUM> provides an active PREPD signal (e.g. active high logic level) when the D_000F and DD_000 signals have low logic levels. As a result, the PREPD signal is active when D<<NUM>>, D<<NUM>>, and D<<NUM>> are at a low logic level, and for one-half a clock cycle of the CLK signal following a rising edge of the CLK signal. The PREPD signal is active for one-half a clock cycle of the CLK signal because the one-half clock cycle delay of the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> relative to D<<NUM>>, D<<NUM>>, and D<<NUM>> will result in the DD_000 signal being at a low logic level while the D 000F signal is at a low logic level (from D<<NUM>>, D<<NUM>>, and D<<NUM>> being a low logic level), but for one-half a clock cycle of the CLK signal before the DD<<NUM>>, DD<<NUM>>, and DD<<NUM>> signals also become a low logic level (resulting from the D<<NUM>>, D<<NUM>>, and D<<NUM>> signals being at the low logic level) and the NOR logic circuit <NUM> provides a high logic level DD_000. As a result, the PREPD signal is active for one-half a clock cycle of the CLK signal.

<FIG> illustrates a portion of a memory <NUM> according to an embodiment of the present disclosure. The memory <NUM> includes an array <NUM> of memory cells, which may be, for example, volatile memory cells, non-volatile memory cells, DRAM memory cells, SRAM memory cells, flash memory cells, or some other types of memory cells. The memory <NUM> includes a command decoder <NUM> that receives memory commands through a command bus <NUM>. The command decoder <NUM> responds to memory commands received through the memory bus <NUM> to perform various operations on the array <NUM>. For example, the command decoder <NUM> provides control signals to read data from and write data to the array <NUM> for read commands and write commands.

The memory <NUM> further includes an address latch <NUM> that receives memory addresses through an address bus <NUM>, for example, row and column addresses. The address latch <NUM> then outputs separate column addresses and separate row addresses. The row and column addresses are provided by the address latch <NUM> to a row address decoder <NUM> and a column address decoder <NUM>, respectively. The column address decoder <NUM> selects bit lines extending through the array <NUM> corresponding to respective column addresses. The row address decoder <NUM> is connected to word line driver <NUM> that activates respective rows of memory cells in the array <NUM> corresponding to received row addresses.

The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to a read/write circuitry <NUM> to provide read data to a data output circuit <NUM> via an input-output data bus <NUM>. The data output circuit <NUM> may include multilevel signal drivers <NUM> that are configured to drive multilevel voltages on signal lines of an output data bus. The multilevel signal drivers <NUM> may include signal drivers according to embodiments of the disclosure, including for example, the signal drivers and circuits previously shown and described, or combinations thereof. Write data to be written to the array <NUM> are received by the data input circuit <NUM> and provided over the input-output data bus <NUM> to the read/write circuitry <NUM>. The data is then written to the array <NUM> in the memory cells corresponding to the row and column addresses of the write command.

Claim 1:
An apparatus, comprising:
a driver circuit (<NUM>) configured to provide at a node an output signal, wherein the output signal is a multilevel signal having a voltage indicative of a value of the data represented by a plurality of input bitstreams, and wherein a first value of the data is indicated by the output signal having one of:
a voltage of the high supply voltage;
a voltage of the low supply voltage;
a voltage that is greater than a voltage of the output signal indicative of a second value of the data; and
a voltage that is less than a voltage of the output signal indicative of a second value of the data;
wherein the driver circuit comprises:
a first driver section (<NUM>) configured to be activated responsive to bit values of a first bitstream of the plurality of bitstreams; and
a second driver section (<NUM>) configured to be activated responsive to bit values of a second bitstream of the plurality of bitstreams;
a boost circuit (<NUM>) coupled to the node and configured to drive the node to at least one of a high supply voltage or a low supply voltage based on a state of a boost signal; and
a boost control circuit (<NUM>) configured to provide the boost signal to cause the boost circuit to drive the node to at least one of the high supply voltage or the low supply voltage, wherein the state of the boost signal is provided responsive to the data represented by the plurality of input bitstreams, wherein the boost control circuit is configured to activate the boost circuit to provide additional drive to change the voltage of the node when a voltage of the output signal changes.