Patent Description:
A non-volatile memory may retain stored data even when power thereto is cut off. Recently, a storage device including a flash-based nonvolatile memory such as an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Solid State Drive (SSD), and a memory card has been widely used. These storage devices are useful to store or move a large amount of data.

A data processing system including a storage device may be referred to as a storage system, and the storage system may include a host and a storage device. Hosts and storage devices may be connected to one another through a variety of interface standards.

<CIT> discloses methods, systems, and computer readable media for solid state drive caching across a host bus.

<CIT> discloses a modified or host driver operable on a host controller that communicates with a host interface of a PCIe adapter.

Aspects of the invention are set out in claims <NUM>, <NUM> and the claims dependent thereon.

The disclosure relates to a storage system and method of operating the same, in which a host memory is also used as a cache memory, and a write operation or a read operation is completed without data transmission between a host device and a storage device, thereby improving write speed and read speed.

According to an aspect of the disclosure, there is provided a method of operating a storage system including a host device and a storage device, the method including: transmitting, by the host device, a first write command and a logical address to the storage device; transmitting, by the storage device, first normal offset information about a normal area and first cache offset information about a cache area included in a host memory of the host device to the host device; copying, by the host device, first write data stored in the normal area to the cache area based on the first normal offset information and the first cache offset information; and omitting reception of the first write data from the host device and transmitting, by the storage device, a first response to the first write command to the host device, wherein a reception of the first write data from the host device before transmitting the first response is omitted.

According to another aspect of the disclosure, there is provided a storage system including a host device including a memory including a normal area and a cache area; and a storage device including a memory cell array, configured to receive a write command and a logical address from the host device, and to transmit first address information for the cache area to the host device, wherein the host device is configured to copy write data stored in the normal area to the cache area based on the first address information, and wherein the storage device is configured to transmit a response to the write command to the host device before receiving the write data from the host device.

According to another aspect of the disclosure, there is provided a method of operating a storage system including a host device and a storage device, the method including: transmitting, by the host device, a first read command and a logical address to the storage device; transmitting, by the storage device, first normal offset information about a normal area and first cache offset information about a cache area, and read data in the cache area to the host device, wherein the normal area and the cache area are included in a host memory of the host device; storing, by the host device, the read data in the normal area and the cache area based on the first normal offset information and the first cache offset information; transmitting a second read command and the logical address to the storage device by the host device; transmitting, by the storage device, the first cache offset information to the host device; and copying, by the host device, the read data stored in the cache area to the normal area based on the first cache offset information.

Embodiments of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:.

Hereinafter, various embodiments of the disclosure will be described with reference to the accompanying drawings. As used herein, an expression "at least one of" preceding a list of elements modifies the entire list of the elements and does not modify the individual elements of the list. For example, an expression, "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

<FIG> is a block diagram illustrating a storage system according to an embodiment.

Referring to <FIG>, a storage system <NUM> may include a host device <NUM> and a storage device <NUM>.

The host <NUM> may include a host memory <NUM>. The host memory <NUM> may include at least one of a dynamic random access memory (DRAM), a static random access memory (SRAM), and a non-volatile memory. The host memory <NUM> may store at least one command or program executed by the host <NUM>. Furthermore, the host memory <NUM> may store data to be provided to the storage device <NUM> or data provided from the storage device <NUM>.

The host memory <NUM> may include a normal area <NUM> and a cache area <NUM>. The normal area <NUM> may store write data to be provided to the storage device <NUM> or read data received from the storage device <NUM>. The normal area <NUM> may include a write normal area in which write data is stored and a read normal area in which read data is stored. The cache area <NUM> may also store write data and read data according to a request from the storage device <NUM>. According to a request from the storage device <NUM>, write data stored in the normal area <NUM> may be copied to the cache area <NUM>, and read data stored in the normal area <NUM> may be copied to the cache area <NUM>. The cache area <NUM> may include a write cache area in which write data is stored and a read cache area in which read data is stored. Data stored in the cache area <NUM> may be provided to the storage device <NUM> according to a request from the storage device <NUM>.

The host <NUM> may provide logical addresses and commands to the storage device <NUM>. During a write operation, the host <NUM> may request the storage device <NUM> to program write data in a storage area of a non-volatile memory <NUM> corresponding to the logical address. During a read operation, the host <NUM> may request the storage device <NUM> for data read from the storage area of the non-volatile memory <NUM> corresponding to the logical address.

A write operation or a read operation for one logical address may be performed a plurality of times. Herein, a write operation or a read operation previously performed for one logical address may be referred to as a first write operation or a first read operation, and a write operation or a read operation performed later on the same logical address may be referred to as a second write operation or a second read operation. The second read operation may also be referred to as a cache read operation.

According to an embodiment of the disclosure, during the first write operation, the host <NUM> and the storage device <NUM> may complete a write operation without transmitting/receiving write data there-between. For example, the host <NUM> may provide a logical address and a write command to the storage device <NUM> without providing write data to the storage device <NUM>. The storage device <NUM> may request the host <NUM> to copy write data from the normal area <NUM> to the cache area <NUM>. The storage device <NUM> may provide the host <NUM> with address information about the normal area <NUM> in which write data is stored and address information about the cache area <NUM> to which the write data is to be copied. Herein, address information may also be referred to as offset information. Offset information may be referred to as data buffer offset information. Offset information about the normal area <NUM> may be referred to as normal offset information, and offset information about the cache area <NUM> may be referred to as cache offset information. The storage device <NUM> may manage a mapping relationship between logical addresses and offset information (e.g., the L2C map of <FIG>). The host <NUM> may copy write data in the normal area <NUM> to the cache area <NUM> based on the normal offset information and the cache offset information. The storage device <NUM> may provide the host with a response to the write command from the host <NUM>. The storage device <NUM> may request transmission of write data from the host <NUM> during an idle time when data transmission between the host <NUM> and the storage device <NUM> is low. The idle time may be determined as at least one of a data rate between the host device <NUM> and the storage device <NUM>, a reference clock signal of the host device <NUM>, an amount of data traffic in a predetermined time unit between the host device <NUM> and the storage device <NUM>, and a predetermined time after the storage device <NUM> transmits the response to the write command to the host device <NUM>, not being limited thereto. A flush operation in which write data stored in the cache area <NUM> is stored in the non-volatile memory <NUM> may be performed according to a request from the storage device <NUM>. According to an embodiment, as the host <NUM> receives the response from the storage device <NUM> without transmitting write data to the storage device <NUM>, the write operation may be completed quickly.

During the first read operation, the host <NUM> may provide a logical address and a read command to the storage device <NUM>. The storage device <NUM> may read data stored in the non-volatile memory <NUM> in response to the read command, and may provide the read data to the host <NUM>. The storage device <NUM> may provide the host <NUM> with normal offset information about a normal area <NUM> in which read data is to be stored and cache offset information about a cache area <NUM> in which read data is to be stored. The storage device <NUM> may manage a mapping relationship between logical addresses, normal offset information, and cache offset information. The host <NUM> may store read data provided from the storage device <NUM> in the normal area <NUM> and the cache area <NUM> based on the normal offset information and the cache offset information, respectively.

The second write operation may be a write-after-write operation performed on the same logical address after the first write operation, or may be a write-after-read operation performed on the same logical address after the first read operation. During the second write operation, the cache area <NUM> may be in a state storing read data or write data. The storage device <NUM> may determine a cache hit or a cache miss based on the logical address. When the logical address received from the host <NUM> is included as valid data in the L2C map, it may be determined to be a cache hit, and when a logical address received from the host <NUM> is not included as valid data in the L2C map, it may be determined to be a cache miss.

During the second write operation, the host <NUM> may provide a logical address and a write command to the storage device <NUM> without providing write data. The storage device <NUM> may provide the host <NUM> with new normal offset information about the normal area <NUM> in which the new write data is stored and new cache offset information about the cache area <NUM> in which the new write data is to be copied. The storage device <NUM> may update the new normal offset information and the new cache offset information mapped to logical addresses. The host <NUM> may copy new write data from the normal area <NUM> to the cache area <NUM> based on the new normal offset information and the new cache offset information. The storage device <NUM> may provide the host <NUM> with a response to the write command from the host <NUM>. The storage device <NUM> may request transmission of the new write data from the host <NUM> during an idle time when data transmission between the host <NUM> and the storage device <NUM> is low. A flush operation in which data stored in the cache area <NUM> is stored in the non-volatile memory <NUM> may be performed according to a request of the storage device <NUM>. According to an embodiment, as the host <NUM> receives the response from the storage device <NUM> without transmitting write data, the write operation may be completed quickly.

The second read operation may be a read-after-write operation performed after the first write operation or a read-after-read operation performed after the first read operation. During the second read operation, the cache area <NUM> may be in a state storing read data or write data. A second read operation may be performed in case of a cache hit, and a first read operation may be performed in case of a cache miss.

During the second read operation, the host <NUM> may provide a read command and a logical address to the storage device <NUM>. The storage device <NUM> may omit an operation of reading data from the non-volatile memory <NUM>, and provide cache offset information corresponding to the logical address to the host <NUM> based on the mapping relationship. The host <NUM> may copy data stored in the cache area <NUM> to the normal area <NUM> based on the cache offset information received from the storage device <NUM>. That is, the host <NUM> may obtain read data by copying the data already stored in the cache area <NUM> to the normal area <NUM> without directly receiving the data from the storage device <NUM>. During the second read operation, as the data is copied inside the host memory <NUM> without the data being transmitted/received between the host <NUM> and the storage device <NUM>, the second read operation may be completed quickly. The capacity of the cache area <NUM> in the host <NUM> may be greater than that of an internal cache in the storage device <NUM>. Accordingly, because a large amount of data may be stored in the cache area <NUM>, a cache hit probability may increase, and an amount of data transmission between the host <NUM> and the storage device <NUM> may be reduced.

In some embodiments, during a first or second write operation, the host <NUM> may copy write data in the normal area <NUM> to the cache area <NUM> based on a data stream identifier. For example, the host <NUM> may allocate a stream identifier to write data, divide the cache area <NUM> into a plurality of regions based on the stream identifier, and store the write data in one or more regions among the plurality of regions according to the stream identifier. During an idle time, the storage device <NUM> may request transmission of data having the stream identifier, and the host <NUM> may transmit data in the one or more regions in the cache area <NUM> allocated to the stream identifier to the storage device <NUM>. The stream identifier may be information different from a logical address or a physical address of a memory or offset information about the memory.

In some embodiments, during a first or second write operation, the host <NUM> may copy write data in the normal area <NUM> to the cache area <NUM> based on a program unit of data. A program unit may refer to the number of bits stored in one memory cell included in the non-volatile memory <NUM>, such as a single-level cell (SLC) unit, a multi-level cell (MLC) unit, a triple-level cell (TLC) unit, a quad-level cell (QLC) unit, and the like. For example, when data is stored in QLC units in the non-volatile memory <NUM>, since four (<NUM>) bits are stored in one memory cell, four times more data may be stored in the cache area <NUM> than when data is stored in SLC units. Accordingly, the host <NUM> may copy data of different sizes to the cache area <NUM> according to data program units.

The storage device <NUM> may include a memory controller <NUM> and a non-volatile memory <NUM>. The memory controller <NUM> may provide overall control of the storage device <NUM>. Data read from the non-volatile memory <NUM> may be provided to the host <NUM>, and data provided from the host <NUM> may be programmed into the non-volatile memory <NUM>, according to control of the memory controller <NUM>.

<FIG> is a block diagram illustrating a host <NUM> according to an embodiment. The host <NUM> shown in <FIG> may be the same as or correspond to the host <NUM> shown in <FIG>.

Referring to <FIG>, the host <NUM> may include a host driver <NUM>, the host memory <NUM>, and a host controller interface <NUM>. According to an embodiment, the host <NUM> may be a UFS host complying with a UFS standard, but the disclosure is not limited thereto.

In some embodiments, the host driver <NUM> may convert an input/output request generated by an application into a UFS command defined by the UFS standard, and pass the UFS command to the host controller interface <NUM>. One input-output request may be converted into multiple UFS commands. The input/output requests may also be referred to as task requests. A UFS command may be a concept including a UFS Protocol Information Unit (UPIU) according to the UFS standard. A UFS command may be basically a command defined by a small computer system interface (SCSI) standard, but may also be a command dedicated to the UFS standard.

The host controller interface <NUM> may transmit the UFS command converted by a UFS driver to the storage device <NUM>. In <FIG>, the host memory <NUM> is shown as a separate configuration from the host controller interface <NUM>, but in some embodiments, the host memory <NUM> may be included in the host controller interface <NUM>. The host controller interface <NUM> may copy data in the normal area <NUM> to the cache area <NUM> by controlling the host memory <NUM>. The host controller interface <NUM> may transmit a logical address (e.g., a logical block address (LBA)) to the storage device <NUM>.

<FIG> is a block diagram illustrating a storage device <NUM> according to an embodiment. <FIG> is described with reference to <FIG>. The storage device <NUM> shown in <FIG> may be the same as or correspond to the storage device <NUM> shown in <FIG>.

Referring to <FIG>, the storage device <NUM> may include a memory controller <NUM>, a device memory <NUM>, and a non-volatile memory (NVM) <NUM>. Descriptions of the memory controller <NUM> and the non-volatile memory <NUM> may be omitted since they have been given above with reference to <FIG>.

The device memory <NUM> may temporarily store data to be programmed in the non-volatile memory <NUM> or data read from the non-volatile memory <NUM>. The device memory <NUM> may include a static random access memory (SRAM) or dynamic random access memory (DRAM). The device memory <NUM> may store an L2C map which will be described later with reference to <FIG>. The storage device <NUM> may update the L2C map during a write operation or a read operation. The L2C map may be referred to as an L2C table. In some embodiments, the capacity of the device memory <NUM> may be smaller than the capacity of the host memory <NUM>. Accordingly, the storage device <NUM> may use the host memory <NUM> as a cache memory, according to an embodiment. The host <NUM> and the storage device <NUM> may provide improved write speed or read speed by performing a cache operation based on a cache having a sufficient capacity.

<FIG> is a diagram explaining a writing method of a storage system according to a comparative example. <FIG> is described with reference to <FIG>.

Referring to <FIG>, the host <NUM> may provide a write command WR CMD and a logical address LBA to the storage device <NUM> in operation S410. When the host <NUM> is a UFS host and the storage device <NUM> is a UFS device, the write command WR CMD may be one of packets referred to as a UPIU. In some embodiments, the logical address LBA may be included in the write command WR CMD.

The storage device <NUM> may provide a ready-to-transfer (RTT) packet including offset information ofs_N about the normal area <NUM> of the host <NUM> to the host <NUM> in operation S420. The offset information ofs_N may indicate a location where write data is stored in the normal area <NUM>. When the host <NUM> is a UFS host and the storage device <NUM> is a UFS device, the RTT packet may be a packet referred to as a UPIU.

The host <NUM> may provide a data-out command DATA-OUT CMD including write data WR DATA to the storage device <NUM> in operation S430. The host <NUM> may obtain write data WR DATA based on the offset information ofs_N.

The storage device <NUM> may provide the host <NUM> with a response indicating that the write operation for the write data WR DATA has been completed in operation S440.

According to the comparative example, since the write operation is completed after the write data is transmitted from the host <NUM> to the storage device <NUM>, the write operation time may be delayed according to the size of the write data.

<FIG> is a diagram illustrating a writing method of a storage system according to an embodiment. <FIG> may explain the first write operation described above with reference to <FIG>. <FIG> may be described with reference to <FIG>.

Referring to <FIG>, the host <NUM> may provide a write command WR CMD and a logical address LBA to the storage device <NUM> in operation S510. The host <NUM> and the storage device <NUM> may transmit and receive to/from each other data in the form of packets. In some embodiments, the logical address LBA may be included in the write command WR CMD. In some embodiments, when the host <NUM> is a UFS host and the storage device <NUM> is a UFS device, the host <NUM> and the storage device <NUM> may transmit/receive a packet referred to as a UPIU to/from each other. A description of the UPIU is provided later with reference to <FIG>. A command UPIU corresponding to the write command WR CMD is described later in detail with reference to <FIG>.

The storage device <NUM> may provide the host <NUM> with an RTT packet including normal offset information ofs_N and cache offset information ofs_C in operation S520. In some embodiments, the RTT packet may include normal transfer count information cnt_N indicating the length of data to be copied from the normal area <NUM> to the cache area <NUM>, and/or cache transfer count information cnt_C indicating the length of data to be stored in the cache area <NUM>. The RTT packet may be described later in detail with reference to <FIG>.

The host <NUM> may copy data in the normal area <NUM> to the cache area <NUM> based on the normal offset information and the cache offset information ofs_N and ofs_C in operation S530. For example, data in a region indicated by the normal offset information ofs_N may be stored in a region indicated by the cache offset information ofs_C.

The host <NUM> may provide a data-out command DATA-OUT CMD to the storage device <NUM> in operation S540. In some embodiments, the data-out command DATA-OUT CMD may be referred to as a data-out UPIU. The data-out command DATA-OUT CMD may include cache offset information ofs_C about the cache area <NUM> storing the copied data. The data-out command DATA-OUT CMD may not include write data. That is, the host <NUM> may provide the storage device <NUM> with only cache offset information ofs_C about the cache area <NUM> in which write data is stored. The host <NUM> may provide write data to the storage device <NUM> during an idle time or when the storage device <NUM> requests a flush operation.

The storage device <NUM> may update the L2C map in operation S550. The L2C map may indicate a mapping relationship between a logical address LBA and cache offset information ofs_C. In some embodiments, the L2C map may indicate a mapping relationship between a logical address LBA, cache offset information ofs_C, and normal offset information ofs_N.

In response to operation S540, the storage device <NUM> may confirm that write data is stored in a region indicated by the cache offset information ofs_C by receiving the cache offset information ofs_C. Accordingly, when a read command for the logical address LBA is received later from the host <NUM>, instead of providing read data to the host <NUM>, the storage device <NUM> may instruct the host <NUM> to read data from the cache area <NUM> by providing the cache offset information ofs_C to the host <NUM>.

The storage device <NUM> may provide the host <NUM> with a response indicating that the write operation of the write data has been completed in operation S560.

The write command, RTT packet, data-out command or response of <FIG> may include a flag related to a function of storing the write data in the cache area <NUM>.

The host <NUM> may subsequently provide the write data to the storage device <NUM> during an idle time or when requested by the storage device <NUM> in operation S570.

According to <FIG>, since the storage device <NUM> provides a response to the host <NUM> before actually receiving the write data, the write operation speed may be improved.

<FIG> is a diagram explaining a read method of a storage system according to a comparative example. <FIG> may be described with reference to <FIG>.

The host <NUM> may provide a read command RD CMD and a logical address LBA to the storage device <NUM> in operation S610. In some embodiments, the logical address LBA may be included in the read command RD CMD. The read command RD CMD may be a command UPIU of <FIG> to be described later.

The storage device <NUM> may read data from an area of the non-volatile memory <NUM> corresponding to the logical address LBA in operation S620. The storage device <NUM> may convert the logical address LBA into a physical address PBA, and read data from the non-volatile memory <NUM> based on the physical address PBA.

The storage device <NUM> may provide the host <NUM> with a data-in command DATA-IN CMD including normal offset information ofs_N indicating a location in the normal area <NUM> where read data RD DATA is to be stored, in operation S630. The data-in command DATA-IN CMD may include the read data RD DATA. The data-in command DATA-IN CMD may be a data-in UPIU of <FIG>.

The host <NUM> may store the read data RD DATA in the location in the normal area <NUM> indicated by the normal offset information ofs_N in operation S640.

In some embodiments, operations S620 to S640 may be performed for a predetermined data unit. Accordingly, in the case of a read operation for data exceeding a data unit, operations S620 to S640 may be repeatedly performed.

When all read data requested by the host <NUM> is transmitted to the host <NUM>, the storage device <NUM> may provide a response, indicating that the read operation has been completed, to the host <NUM> in operation S650. The response may be the response UPIU of <FIG>.

<FIG> is a diagram illustrating a read method of a storage system according to an embodiment. <FIG> may be described with reference to <FIG>. <FIG> may explain the first read operation described above with reference to <FIG>.

The host <NUM> may provide a read command RD CMD and a logical address LBA to the storage device <NUM> in operation S710. The read command RD CMD may be a command UPIU of <FIG> to be described later. The read command RD CMD may include a flag related to a function for storing read data in the cache area <NUM>.

The storage device <NUM> may read data from an area of the non-volatile memory <NUM> corresponding to the logical address LBA in operation S720. The storage device <NUM> may convert the logical address LBA into a physical address PBA and read data based on the physical address PBA.

The storage device <NUM> may provide the host <NUM> with read data RD DATA, normal offset information ofs_N indicating a location in the normal area <NUM> where the read data RD DATA is to be stored, and a data-in command DATA-IN CMD including cache offset information ofs_C indicating a location in the cache area <NUM> in operation S730. The data-in command DATA-IN CMD may be a data-in UPIU of <FIG> to be described later. For example, the storage device <NUM> may provide only the normal offset information ofs_N to the host <NUM> as shown in <FIG> based on the flag included in the read command CMD, or as shown in <FIG>, provide normal offset information ofs_N and cache offset information ofs_C to the host <NUM>. The data-in command DATA-IN CMD of <FIG> may include the flag related to a function of storing read data in the cache area <NUM>.

The host <NUM> may store the read data RD DATA in the normal area <NUM> and the cache area <NUM> based on the normal offset information ofs_N and the cache offset information ofs_C in operation S740. In some embodiments, the read data RD DATA may be first stored in the normal area <NUM> and later stored in the cache area <NUM>, and in some embodiments, the read data RD DATA may be first stored in the cache area <NUM> and stored later in the normal area <NUM>.

The storage device <NUM> may update an L2C map representing a mapping relationship between logical addresses and cache offset information ofs_C in operation S750.

In some embodiments, operations S720 to S750 may be performed for a predetermined data unit. Accordingly, in the case of a read operation for data exceeding a data unit, S720 to S750 may be repeatedly performed.

When all data requested by the host <NUM> is transmitted to the host <NUM>, the storage device <NUM> may provide a response indicating that the read operation has been completed to the host <NUM> in operation S760. The response may be the response UPIU of <FIG>.

<FIG> is a diagram illustrating a write method of a storage system according to an embodiment. <FIG> may explain the second write operation described above with reference to <FIG>. <FIG> may be described with reference to <FIG>.

The host <NUM> may provide a write command WR CMD and a logical address LBA to the storage device <NUM> in operation S810. The logical address LBA may be a logical address of data stored in the cache area <NUM> according to the embodiment of <FIG> or <FIG>.

The storage device <NUM> may provide an RTT packet including new cache offset information new ofs_C and normal offset information ofs_N to the host <NUM> in operation S820. For example, a write operation may be requested again for the logical address LBA for which a read or write operation has already been performed. In this case, the storage device <NUM> may include new cache offset information new ofs_C rather than the old cache offset information old ofs_C in the RTT packet. The normal offset information ofs_N may be old normal offset information old ofs_N or new normal offset information new ofs_N.

The host <NUM> may copy the data in the normal area <NUM> indicated by the normal offset information ofs_N to the cache area <NUM> indicated by the new cache offset information ofs_C in operation S830.

Operations S840 to S870 may be substantially the same as operations S530 to S570 of <FIG>. The write command, RTT packet, data-out command or response of <FIG> may include a flag related to a function of storing write data in the cache area <NUM>.

<FIG> is a diagram illustrating a read method of a storage system according to an embodiment. <FIG> may explain the second read operation described above with reference to <FIG>. <FIG> may be described with reference to <FIG>.

The host <NUM> may provide a read command RD CMD and a logical address LBA to the storage device <NUM> in operation S910.

The storage device <NUM> may identify cache offset information ofs_C corresponding to the logical address LBA based on the L2C map in operation S920. That is, the cache offset information ofs_C mapped to the logical address LBA may be identified by searching the L2C map formed according to the embodiment of <FIG> or <FIG>.

The storage device <NUM> may provide a data-in command DATA-IN CMD including the identified cache offset information ofs_C to the host <NUM> in operation S930. Unlike the data-in command of <FIG> or <FIG>, the data-in command DATA-IN CMD may not include read data RD DATA. Accordingly, the storage device <NUM> may omit an operation of reading data from the non-volatile memory <NUM>. In some embodiments, the data-in command DATA-IN CMD provides the host <NUM> with normal offset information ofs_N indicating the location of the normal area <NUM> to which the data in the cache area <NUM> will be copied.

The host <NUM> may copy data in the cache area <NUM> to the normal area <NUM> based on the cache offset information ofs_C. Accordingly, even if read data is not included in the data-in command DATA-IN CMD, the host <NUM> may obtain the read data requested from the storage device <NUM>.

The storage device <NUM> may provide the host <NUM> with a response indicating that the read operation has been completed.

<FIG> is a diagram illustrating an L2C map according to an embodiment. <FIG> may be described with reference to <FIG>.

Referring to <FIG>, the L2C map may indicate a mapping relationship between a logical address LBA, normal offset information ofs_N, cache offset information ofs_C, a program unit PGM unit, and a stream identifier STR ID.

For example, the logical address LBA1, normal offset information ofs_N1, and cache offset information ofs_C1 are mapped, as described above with reference to <FIG> or <FIG>. Thus, data at a location indicated by the normal offset information ofs_N1 in the normal area <NUM> may be copied to a location indicated by the cache offset information ofs_C1 in the cache area <NUM>.

Alternatively or additionally, as described above with reference to <FIG>, the storage device <NUM> may provide cache offset information ofs_C1 corresponding to the logical address LBA1 to the host <NUM> based on the L2C map, and the host <NUM> may copy data at a location indicated by the cache offset information ofs_C1 to the normal area <NUM>.

Referring to <FIG>, the storage device <NUM> may manage program units of data stored in the cache area <NUM> using the L2C map. That is, as described above with reference to operation S570 in <FIG> or operation S880 in <FIG>, when requesting data transmission from the host <NUM>, the storage device <NUM> may request data of different sizes from the host <NUM> according to program units.

<FIG> is a diagram for explaining a method of storing data in a cache area based on program units according to an embodiment. <FIG> may be described with reference to <FIG>.

Referring to <FIG>, the host <NUM> may copy write data WD1, WD2, WD3, and WD4 of the normal area <NUM> to the cache area <NUM> based on a program unit. For example, each of the write data WD1, WD2, WD3, and WD4 may be data stored in a physical page of the non-volatile memory <NUM>. One physical page may refer to memory cells connected to one word line.

When data is stored in the storage device <NUM> in SLC units, each of the write data WD1, WD2, WD3, and WD4 may be stored in a different page, for example. In this case, the write data WD1, WD2, WD3, and WD4 may be stored in the cache area <NUM> without being merged. Then, when there is a request from the storage device <NUM>, each of the write data WD1, WD2, WD3, and WD4 may be individually provided to the storage device <NUM>.

When data is stored in the storage device <NUM> in MLC units, write data WD1 and WD2 may be stored in a first page, and write data WD1 and WD2 may be stored in a second page, for example. In this case, the write data WD1 and WD2 may be merged and stored in the cache area <NUM>, and the write data WD3 and WD4 may be merged and stored in the cache area <NUM>. Then, when there is a request from the storage device <NUM>, the write data WD1 and WD2 may be continuously provided to the storage device <NUM> and write data WD3 and WD4 may be continuously provided to the storage device <NUM>. For example, the write data WD1 and WD2 may be provided to the storage device at the same time, at a substantially same time, in a concatenated form, and/or in a merged form.

When data is stored in the storage device <NUM> in units of TLC, write data WD1, WD2, and WD3 may be stored in a first page, and write data WD4 may be stored in a second page together with other write data, for example. In this case, the write data WD1, WD2, and WD3 may be merged and stored in the cache area <NUM>, and the write data WD4 may be individually stored in the cache area <NUM>. Thereafter, if there is a request from the storage device <NUM>, the write data WD1, WD2, and WD3 may be continuously provided to the storage device <NUM>. Write data WD4 may be continuously provided to the storage device <NUM> with two additional logical pages. A logical page may refer to data stored in a physical page. That is, a plurality of logical pages may be stored in one physical page according to a program unit.

When data is stored in the storage device <NUM> in QLC units, write data WD1, WD2, WD3, and WD4 may be stored in a same page. Accordingly, the write data WD1, WD2, WD3, and WD4 may be merged and stored in the cache area <NUM>. Then, when there is a request from the storage device <NUM>, the write data WD1, WD2, WD3, and WD4 may be continuously provided to the storage device <NUM>.

<FIG> is a diagram for explaining a method of storing data in a cache area based on a stream identifier according to an embodiment. <FIG> may be described with reference to <FIG>.

Referring to <FIG>, the host <NUM> copies write data A, B, C, D, E, F, G, and H of the normal area <NUM> to the cache area <NUM> based on the stream identifier.

For example, the host <NUM> may allocate an identifier A to the write data A and D, merge the write data A and D, and store the merged write data A and D in the cache area <NUM>. Thereafter, if there is a request from the storage device <NUM>, the write data A and D may be continuously provided to the storage device <NUM>. For example, the write data A and D may be provided to the storage device, at the same time or at a substantially same time, in the merged form.

The host <NUM> may allocate an identifier B to the write data B, E and G, merge the write data B, E, and G, and store the merged write data B, E and G in the cache area <NUM>. Thereafter, if there is a request from the storage device <NUM>, the write data B, E and G may be continuously provided to the storage device <NUM>. For example, the write data B, E and G may be provided to the storage device, at the same time or at a substantially same time, in the merged form.

The host <NUM> may allocate an identifier C to the write data C, F, and H, merge the write data C, F, and H, and store the merged write data C, F, and H in the cache area <NUM>. Thereafter, if there is a request from the storage device <NUM>, the write data C, F and H may be continuously provided to the storage device <NUM>. For example, the write data C, F and H may be provided to the storage device, at the same time or at a substantially same time, in the merged form.

<FIG> is a diagram illustrating a data structure of a general UPIU according to an embodiment.

Referring to <FIG>, a general UPIU may have a structure including a Transaction Type field, a Flags field, a Logical Unit Number (LUN) field, a Task Tag field, an Initiator ID field, a Command Set Type field, a Query Function and Task Management Function field, a Response field, a Status field, a Total Extra Header Segment (EHS) Length field, a Device Information field, a Data Segment Length field (referred to as header), Transaction Specific Fields, an Extra Header Segment field, a Header End-to-End Cyclic Redundancy Check (E2ECRC) field, a Data Segment field, and a Data E2ECRC field. The length of the header may be <NUM> bytes, but is not limited thereto. The length of the UPIU may be a minimum of <NUM> bytes and a maximum of <NUM> bytes, but is not limited thereto.

The Transaction Type field may indicate the type of request or response included in the data structure. For example, the Transaction Type field may include a transaction code, and the transaction code may define contents, functions, or use of the UPIU. The Flags field may have different values according to transaction types. According to an embodiment, the flag field may have a value indicating a cache operation.

The LUN field may include a LUN within a target device to which a request is sent. The target device may be, for example, the storage device <NUM> of <FIG>, and a storage area in the storage device <NUM> may match at least one LUN.

The Task Tag field may be a value corresponding to a task request, and may be a value that increases whenever a new task request is generated. When a plurality of UPIUs are generated for one task request, all UPIUs may have the same Task Tag field value. For example, the Task Tag field may consist of eight (<NUM>) bits.

The Initiator ID field may include an identifier for a device that initiated the UPIU.

The Command Set Type field may indicate a command set type associated with a command UPIU and a response UPIU. The command UPIU may be a UPIU provided by the host <NUM> to the storage device <NUM>, and the response UPIU may be a UPIU provided by the storage device <NUM> to the host <NUM>.

The Query Function and Task Management Function field may be fields used in a query request UPIU and a query response UPIU to define query functions, and may be fields used in a task management request UPIU to define task management functions.

When a response is requested from the storage device <NUM>, the Response field may indicate success or failure of the requested function.

The Status field may include a small computer system interface (SCSI) status when the UPIU is a response UPIU.

The Total EHS Length field may indicate the length of an additional header segment in the UPIU. The length of the additional header segment may be a multiple of four (<NUM>) bytes.

The Device Information field may provide information about the storage device <NUM>, for example, device level information, within the response UPIU.

The Data Segment Length field may indicate the number of valid bytes of a data segment in the UPIU.

The Transaction Specific Fields may be one or more additional fields required by a certain transaction code.

The Extra Header Segment field may be present when the Total EHS Length field has a value other than <NUM>, and may have a length corresponding to a multiple of four (<NUM>) bytes.

The Data Segment field may have a length corresponding to a multiple of four (<NUM>) bytes, and may include a data payload.

The header E2ECRC field may include CRC data for correcting errors in the header, and the data E2ECRC field may include CRC data for correcting errors in the data segment.

<FIG> is a diagram illustrating a data structure of a command UPIU according to an embodiment. <FIG> may be described with reference to <FIG> and <FIG>.

The command UPIU may be a packet provided by the host <NUM> to the storage device <NUM>. Referring to <FIG> and <FIG>, a transaction code of the command UPIU in a field corresponding to the Transaction Type field of the general UPIU (shown in <FIG>) may be xx00 0001b, for example.

A flag field of the command UPIU corresponding to the Flags field of the general UPIU may have a value indicating a cache read operation or cache write operation described above.

The command UPIU may include an additional task tag field EXT_Task Tag and EXT_IID. The additional task tag field EXT_Task Tag may include a value for identifying one task request. According to embodiments, the number of operations that may be performed by the host <NUM> and the storage device <NUM> may be increased by a write operation or a read operation using the cache offset information ofs_C. Accordingly, since it may be difficult to identify all task requests between the host <NUM> and the storage device <NUM> using only the Task Tag field of <FIG>, various task requests may be identified through the additional task tag field EXT_Task Tag.

The command UPIU may include an expected data transfer length field. The expected data transfer length field may indicate the length of write data to be transmitted. For example, the expected data transfer length field of the write command WR CMD of <FIG> may indicate the length of the write data WR DATA.

The command UPIU may include a Command Descriptor Blocks (CDB) field. The CDB field may include an operation code (opcode) of a command. The command UPIU may correspond to a write command UPIU or a read command UPIU according to an opcode. The CDB field may include a logical address.

<FIG> is a diagram illustrating a data structure of a response UPIU according to an embodiment. <FIG> may be described with reference to <FIG> and <FIG>.

The response UPIU may be a packet provided by the storage device <NUM> to the host <NUM>. Referring to <FIG> and <FIG>, a transaction code of the response UPIU in a field corresponding to the Transaction Type field of the general UPIU (shown in <FIG>) may be xx10 0001b, for example.

A flag field of the response UPIU corresponding to the Flags field of the general UPIU may have a value indicating a cache read operation or cache write operation described above.

Like the command UPIU of <FIG>, the response UPIU may include an additional task tag field EXT_Task Tag and EXT_IID. The additional task tag field EXT_Task Tag may replace the Query Function and Task Management Function fields of the general UPIU of <FIG>. In some embodiments, the additional task tag field EXT_Task Tag may replace the Status field of <FIG> or <FIG>.

The response UPIU may include a residual transfer count field. The residual transfer count field may indicate the number of unit sizes not transferred to the host <NUM>.

The response UPIU may include a sense data field and a sense data length field. The sense data field may be a field indicating whether a previously executed command has an error. The sense data field may be <NUM> if a previously executed command was successfully executed. The sense data length field may be a field indicating the length of effective sense data.

<FIG> is a diagram illustrating a data structure of a data-out UPIU according to an embodiment. <FIG> may be described with reference to <FIG>, <FIG>, <FIG> and <FIG>.

The data-out UPIU may be a packet provided by the host <NUM> to the storage device <NUM>. Referring to <FIG> and <FIG>, a transaction code of the data-out UPIU may be xx00 0010b in a field corresponding to the Transaction Type field of the general UPIU (shown in <FIG>), for example.

A flag field of the data-out UPIU corresponding to the Flags field of the general UPIU may have a value indicating the cache read operation or cache write operation described above.

The data-out UPIU may include an additional task tag field EXT_Task Tag and EXT_IID like the command UPIU and response UPIU of <FIG> and <FIG>.

The data-out UPIU may include offset information about the cache area <NUM>, for example, cache offset information ofs_C, and the number of data transmissions copied to the cache area <NUM>, which may be cache transfer count information cnt_C. A unit of data transmission may be four (<NUM>) KB, and the size of data copied to the cache area <NUM> may be determined according to the cache count information cnt_C. For example, when the cache count information cnt_C indicates one (<NUM>), 4KB data may be copied to the cache area <NUM>.

The data-out UPIU may correspond to the data-out command DATA-OUT CMD described above for operation S540 of <FIG> and operation S840 of <FIG>. Although the data-out command DATA-OUT CMD of <FIG> and <FIG> includes only cache offset information, the embodiment is not limited thereto, and the data-out UPIU may further include cache transfer count information cnt_C.

<FIG> is a diagram explaining a data structure of a data-in UPIU according to an embodiment. <FIG> may be described with reference to <FIG>, <FIG>, <FIG>, and <FIG>.

The data-in UPIU may be a packet provided by the storage device <NUM> to the host <NUM>. Referring to <FIG> and <FIG>, a transaction code of the data-in UPIU may be xx10 0010b in a field corresponding to the Transaction Type field of the general UPIU (shown in <FIG>), for example.

A flag field of the data-in UPIU corresponding to the Flags field of the general UPIU may have a value indicating the aforementioned cache read operation or cache write operation.

The data-in UPIU may include an additional task tag field EXT_Task Tag and EXT_IID like the command UPIU and response UPIU of <FIG> and <FIG> and the data-out UPIU of <FIG>.

The data-in UPIU may include offset information about the cache area <NUM>, for example, cache offset information ofs_C, and the number of data transmissions copied from the cache area <NUM>, which may be cache transfer count information cnt_C. For example, upon a cache hit, the host <NUM> may copy the size according to the cache transfer count information cnt_C from the cache area <NUM> indicated by the cache offset information ofs_C to the normal area <NUM>.

In some embodiments, the data-in UPIU may include offset information about the normal area <NUM>, for example, normal offset information ofs_N and the number of data transmissions copied from the normal area <NUM>, which may be normal transfer count information cnt_N. In some embodiments, upon a cache miss, the host <NUM> may store read data RD DATA in a region indicated by the normal offset information ofs_N. Also, the host <NUM> may copy data having the size of the normal transfer count information cnt_N from the normal area <NUM> to the cache area <NUM>.

Although the data-in UPIU of <FIG> does not include a data field, in a cache miss situation, the data-in UPIU may include a data field during a read operation. Additionally or alternatively, the data-in UPIU may include read data RD DATA. The data-in UPIU may correspond to the data-in command DATA-IN CMD described above for operation S730 of <FIG> and operation S930 of <FIG>.

<FIG> is a diagram illustrating a data structure of an RTT UPIU according to an embodiment. <FIG> may be described with reference to <FIG>, <FIG>, <FIG> and <FIG>.

The RTT UPIU may be a packet provided by the storage device <NUM> to the host <NUM>. Referring to <FIG> and <FIG>, a transaction code of the RTT UPIU may be xx00 0001b in a field corresponding to the Transaction Type field of the general UPIU (shown in <FIG>), but is not limited thereto.

A flag field of the RTT UPIU may have a value indicating the aforementioned cache read operation or cache write operation.

The RTT UPIU may include an additional task tag field EXT_Task Tag like the command UPIU and response UPIU of <FIG> and <FIG>, the data-out UPIU of <FIG>, and the data in UPIU of <FIG>.

The RTT UPIU may include a normal offset information field including normal offset information ofs_N about the normal area <NUM> and a cache offset information field including cache offset information ofs_C of the cache area <NUM>.

The RTT UPIU may include normal transfer count information cnt_N indicating the length of data copied from the normal area <NUM> in case of a cache miss, and cache transfer count information cnt_N indicating the length of data cached from the cache area <NUM> in case of a cache hit. The RTT UPIU may correspond to the RTT packet described above for operation S520 of <FIG> and operation S820 of <FIG>.

<FIG> is a diagram illustrating a write operation according to an embodiment. <FIG> may be described with reference to <FIG>.

The host driver <NUM> may store write data WR DATA in the normal area <NUM> of the host memory <NUM> in operation S1001. The host driver <NUM> may provide a write request WR REQ to the host controller interface (HCI) <NUM> in operation S1002. The host controller interface <NUM> may provide a command UPIU and a logical address LBA to the memory controller <NUM> in operation S1003. Operation S1003 may be the same as operation S510. The memory controller may provide an RTT packet to the host controller interface <NUM> in operation S1004. Operation S1004 may be the same as operation S520.

The host controller interface <NUM> may copy the write data WR DATA in the normal area <NUM> to the cache area <NUM> in operation S1005. Operation S1005 may be the same as operation S530. The host controller interface <NUM> may provide the data-out UPIU to the memory controller <NUM> in operation S1006. Operation S1006 may be the same as operation S540. The memory controller <NUM> may update an L2C map in operation S1007. Operation S1007 may be the same as operation S550. The memory controller <NUM> may provide a response UPIU indicating that the write operation has been completed to the host controller interface <NUM> in operation S1008. Operation S1008 may be the same as operation S560. The memory controller <NUM> may provide a flush request to the host controller interface <NUM> in operation S1009, and the host memory <NUM> may store the write data WR DATA stored in the cache area <NUM> in the non-volatile memory (NVM) <NUM> in response to the flush request in operation S1010. Operation S1010 may be the same as operation S570.

<FIG> is a diagram illustrating a read operation according to an embodiment. <FIG> may be described with reference to <FIG>.

The host driver <NUM> may provide a read request RD REQ to the host controller interface <NUM> in operation S1101. Operations S1102 to S1105 are implemented by the subject of execution by the host memory <NUM>, the host controller interface <NUM>, and the memory controller <NUM>, and may be substantially the same as operations S920 to S940 of <FIG>. Thus, duplicate descriptions are omitted herein.

The host <NUM> may provide the storage device <NUM> with a response UPIU indicating that the read operation has been completed in operation S1106.

The host driver <NUM> may store write data in the normal area <NUM> of the host memory <NUM> in operation S1201, and provide a write request WR REQ to the host controller interface <NUM> in operation S1202. Operations S1203 to S1209 are implemented by the subject of execution by the host memory <NUM>, the host controller interface <NUM>, and the memory controller <NUM> and may be substantially the same as operations S810 to S860 of <FIG>. Thus, duplicate descriptions are omitted herein.

Meanwhile, the memory controller <NUM> may provide a flush request FLUSH REQ to the host controller interface <NUM> in operation S1210, and in response to the flush request FLUSH REQ, write data stored in the cache area <NUM> may be stored in the non-volatile memory <NUM> in operation S1211.

<FIG> is a diagram of a UFS system <NUM> according to an embodiment. The UFS system <NUM> may be a system conforming to a UFS standard announced by Joint Electron Device Engineering Council (JEDEC) and include a UFS host <NUM>, a UFS device <NUM>, and a UFS interface <NUM>. The above description of the storage system <NUM> of <FIG> may also be applied to the UFS system <NUM> of <FIG> within a range that does not conflict with the following description of <FIG>.

Referring to <FIG>, the UFS host <NUM> may be connected to the UFS device <NUM> through the UFS interface <NUM>. The UFS host <NUM> may correspond to the host <NUM> of <FIG>. The UFS device controller <NUM> and NVM storage <NUM> may correspond to the memory controller <NUM> and NVM <NUM> of <FIG>, respectively.

The UFS host <NUM> may include a UFS host controller <NUM>, an application <NUM>, a UFS driver <NUM>, a host memory <NUM>, and a UFS interconnect (UIC) layer <NUM>. The UFS device <NUM> may include the UFS device controller <NUM>, the NVM <NUM>, a storage interface <NUM>, a device memory <NUM>, a UIC layer <NUM>, and a regulator <NUM>. The NVM <NUM> may include a plurality of memory units (e.g. storage units) <NUM>. Although each of the memory units <NUM> may include a V-NAND flash memory having a 2D structure or a 3D structure, each of the memory units <NUM> may include another kind of NVM, such as phase change random access memory (PRAM) and/or resistive random access memory (RRAM). The UFS device controller <NUM> may be connected to the NVM <NUM> through the storage interface <NUM>. The storage interface <NUM> may be configured to comply with a standard protocol, such as Toggle or open NAND flash interface (ONFI).

The application <NUM> may refer to a program that wants to communicate with the UFS device <NUM> to use functions of the UFS device <NUM>. The application <NUM> may transmit input-output requests (IORs) to the UFS driver <NUM> for input/output (I/O) operations on the UFS device <NUM>. The IORs may refer to a data read request, a data storage (or write) request, and/or a data erase (or discard) request, without being limited thereto.

The UFS driver <NUM> may manage the UFS host controller <NUM> through a UFS-host controller interface (UFS-HCI). The UFS driver <NUM> may convert the IOR generated by the application <NUM> into a UFS command defined by the UFS standard, and transmit the UFS command to the UFS host controller <NUM>. One IOR may be converted into a plurality of UFS commands. Although the UFS command may basically be defined by an SCSI standard, the UFS command may be a command dedicated to the UFS standard.

The UFS host controller <NUM> may transmit the UFS command converted by the UFS driver <NUM> to the UIC layer <NUM> of the UFS device <NUM> through the UIC layer <NUM> and the UFS interface <NUM>. During the transmission of the UFS command, a UFS host register <NUM> of the UFS host controller <NUM> may serve as a command queue (CQ).

The UIC layer <NUM> on the side of the UFS host <NUM> may include a mobile industry processor interface (MIPI) M-PHY <NUM> and an MIPI UniPro <NUM>, and the UIC layer <NUM> on the side of the UFS device <NUM> may also include an MIPI M-PHY <NUM> and an MIPI UniPro <NUM>.

The UFS interface <NUM> may include a line configured to transmit a reference clock signal REF_CLK, a line configured to transmit a hardware reset signal RESET_n for the UFS device <NUM>, a pair of lines configured to transmit a pair of differential input signals DIN_t and DIN_c, and a pair of lines configured to transmit a pair of differential output signals DOUT_t and DOUT_c.

A frequency of a reference clock signal REF_CLK provided from the UFS host <NUM> to the UFS device <NUM> may be one of <NUM>, <NUM>, <NUM>, and <NUM>, without being limited thereto. The UFS host <NUM> may change the frequency of the reference clock signal REF_CLK during an operation, for example, during data transmission/receiving operations between the UFS host <NUM> and the UFS device <NUM>. The UFS device <NUM> may generate cock signals having various frequencies from the reference clock signal REF_CLK provided from the UFS host <NUM>, by using a phase-locked loop (PLL). Also, the UFS host <NUM> may set a data rate between the UFS host <NUM> and the UFS device <NUM> by using the frequency of the reference clock signal REF_CLK. That is, the data rate may be determined depending on the frequency of the reference clock signal REF_CLK.

The UFS interface <NUM> may support a plurality of lanes, each of which may be implemented as a pair of differential lines. For example, the UFS interface <NUM> may include at least one receiving lane and at least one transmission lane. In <FIG>, a pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C may constitute a receiving lane, and a pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C may constitute a transmission lane. Although one transmission lane and one receiving lane are illustrated in <FIG>, the number of transmission lanes and the number of receiving lanes may be changed.

The receiving lane and the transmission lane may transmit data based on a serial communication scheme. Full-duplex communications between the UFS host <NUM> and the UFS device <NUM> may be enabled due to a structure in which the receiving lane is separated from the transmission lane. That is, while receiving data from the UFS host <NUM> through the receiving lane, the UFS device <NUM> may transmit data to the UFS host <NUM> through the transmission lane. In addition, control data (e.g., a command) from the UFS host <NUM> to the UFS device <NUM> and user data to be stored in or read from the NVM <NUM> of the UFS device <NUM> by the UFS host <NUM> may be transmitted through the same lane. Accordingly, between the UFS host <NUM> and the UFS device <NUM>, there may be no need to further provide a separate lane for data transmission in addition to a pair of receiving lanes and a pair of transmission lanes.

The UFS device controller <NUM> of the UFS device <NUM> may control all operations of the UFS device <NUM>. The UFS device controller <NUM> may manage the NVM <NUM> by using a logical unit (LU) <NUM>, which is a logical data storage unit. The number of LUs <NUM> may be eight (<NUM>), without being limited thereto. The UFS device controller <NUM> may include a flash translation layer (FTL), and may convert a logical data address (e.g., an LBA) received from the UFS host <NUM> into a physical data address (e.g., a physical block address (PBA)) by using address mapping information about the FTL. A logical block configured to store user data in the UFS system <NUM> may have a size in a predetermined range. For example, a minimum size of the logical block may be set to <NUM> Kbyte.

When a command from the UFS host <NUM> is applied through the UIC layer <NUM> to the UFS device <NUM>, the UFS device controller <NUM> may perform an operation in response to the command and transmit a completion response to the UFS host <NUM> when the operation is completed.

As an example, when the UFS host <NUM> intends to store user data in the UFS device <NUM>, the UFS host <NUM> may transmit a data storage command to the UFS device <NUM>. When a response (a 'ready-to-transfer' response) indicating that the UFS host <NUM> is ready to receive user data (ready-to-transfer) is received from the UFS device <NUM>, the UFS host <NUM> may transmit user data to the UFS device <NUM>. The UFS device controller <NUM> may temporarily store the received user data in the device memory <NUM> and store the user data, which is temporarily stored in the device memory <NUM>, at a selected position of the NVM <NUM> based on the address mapping information about the FTL.

As another example, when the UFS host <NUM> intends to read the user data stored in the UFS device <NUM>, the UFS host <NUM> may transmit a data read command to the UFS device <NUM>. The UFS device controller <NUM>, which has received the command, may read the user data from the NVM <NUM> based on the data read command and temporarily store the read user data in the device memory <NUM>. During the read operation, the UFS device controller <NUM> may detect and correct an error in the read user data by using an error-correction code (ECC) engine embedded therein. The ECC engine may generate parity bits for write data to be written to the NVM <NUM>, and the generated parity bits may be stored in the NVM <NUM> along with the write data. During the reading of data from the NVM <NUM>, the ECC engine may correct an error in read data by using the parity bits read from the NVM <NUM> along with the read data, and output error-corrected read data.

In addition, the UFS device controller <NUM> may transmit user data, which is temporarily stored in the device memory <NUM>, to the UFS host <NUM>. In addition, the UFS device controller <NUM> may further include an advanced encryption standard (AES) engine. The AES engine may perform at least of an encryption operation and a decryption operation on data transmitted to the UFS device controller <NUM> by using a symmetric-key algorithm.

The UFS host <NUM> may sequentially store commands, which are to be transmitted to the UFS device <NUM>, in the UFS host register <NUM>, which may serve as a common queue, and sequentially transmit the commands to the UFS device <NUM>. In this case, even while a previously transmitted command is still being processed by the UFS device <NUM>, for example, even before receiving a notification that the previously transmitted command has been processed by the UFS device <NUM>, the UFS host <NUM> may transmit a next command, which is on standby in the CQ, to the UFS device <NUM>. Thus, the UFS device <NUM> may also receive a next command from the UFS host <NUM> during the processing of the previously transmitted command. A maximum number (or queue depth) of commands that may be stored in the CQ may be, for example, <NUM>. Also, the CQ may be implemented as a circular queue in which a start and an end of a command line stored in a queue are indicated by a head pointer and a tail pointer.

Each of the plurality of memory units <NUM> may include a memory cell array (not shown) and a control circuit (not shown) configured to control an operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells. Although each of the memory cells is an SLC configured to store <NUM>-bit information, each of the memory cells may be a cell configured to store information about two (<NUM>) bits or more, such as an MLC, a TLC, and a quadruple-level cell (QLC). The 3D memory cell array may include a vertical NAND string in which at least one memory cell is vertically oriented and located on another memory cell.

Voltages VCC, VCCQ, and VCCQ2 may be applied as power supply voltages to the UFS device <NUM>. The voltage VCC may be a main power supply voltage for the UFS device <NUM> and be in a range of <NUM> V to <NUM> V. The voltage VCCQ may be a power supply voltage for supplying a low voltage mainly to the UFS device controller <NUM> and may be in a range of <NUM> V to <NUM> V. The voltage VCCQ2 may be a power supply voltage for supplying a voltage, which is lower than the voltage VCC and higher than the voltage VCCQ, mainly to an I/O interface, such as the MIPI M-PHY <NUM>, and may be in a range of <NUM> V to <NUM> V. The power supply voltages may be supplied through the regulator <NUM> to respective components of the UFS device <NUM>. The regulator <NUM> may be implemented as a set of unit regulators respectively connected to different ones of the power supply voltages described above.

<FIG> is a block diagram illustrating the non-volatile memory of <FIG>. The non-volatile memory <NUM> of <FIG> may be referred to as a memory device <NUM>. Referring to <FIG>, a memory device <NUM> may include a memory interface circuit <NUM>, a control logic circuit <NUM>, a memory cell array <NUM>, a page buffer unit <NUM>, a voltage generator <NUM>, and a row decoder <NUM>. Although not shown in <FIG>, the memory device <NUM> may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

The control logic circuit <NUM> may have overall control of various operations within the memory device <NUM>. The control logic circuit <NUM> may output various control signals in response to a command CMD and/or an address ADDR from the memory interface circuit <NUM>. For example, the control logic circuit <NUM> may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array <NUM> may include a plurality of memory blocks BLK1 to BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cell array <NUM> may be connected to the page buffer unit <NUM> through bit lines BL, and may be connected to the row decoder <NUM> through word lines WL, string select lines SSL, and ground select lines GSL.

In an embodiment, the memory cell array <NUM> may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines stacked vertically on the substrate. <CIT>, <CIT>, <CIT>, <CIT>, and <CIT> provide further information on this kind of arrangement. In an embodiment, the memory cell array <NUM> may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings.

The page buffer unit <NUM> may include a plurality of page buffers PB1 to PBn (n is an integer greater than or equal to <NUM>), and the plurality of page buffers PB1 to PBn may be respectively connected to memory cells through a plurality of bit lines BL The page buffer unit <NUM> may select at least one bit line among the bit lines BL in response to the column address Y-ADDR. The page buffer unit <NUM> may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program (e.g. write) operation, the page buffer unit <NUM> may apply a bit line voltage corresponding to data to be programmed (written) to a selected bit line. During a read operation, the page buffer unit <NUM> may sense data stored in the memory cell by sensing the current or voltage of the selected bit line.

The voltage generator <NUM> may generate various types of voltages for performing program (write), read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator <NUM> may generate a program voltage, a read voltage, a program verify voltage, an erase voltage, and the like as the word line voltage VWL.

The row decoder <NUM> may select one of the plurality of word lines WL in response to the row address X-ADDR, and may select one of the plurality of string select lines SSL. For example, the row decoder <NUM> may apply a program voltage and a program verify voltage to the selected word line during a program (write) operation, and may apply a read voltage to the selected word line during a read operation.

<FIG> is a view illustrating a memory device <NUM> according to some embodiments of the disclosure.

Referring to <FIG>, the memory device <NUM> may have a chip-to-chip (C2C) structure. At least one upper chip including a cell region and a lower chip including a peripheral circuit region PERI may be manufactured separately, and then, the at least one upper chip and the lower chip may be connected to each other by a bonding method to realize the C2C structure. For example, the bonding method may mean a method of electrically or physically connecting a bonding metal pattern formed in an uppermost metal layer of the upper chip to a bonding metal pattern formed in an uppermost metal layer of the lower chip. For example, in a case in which the bonding metal patterns are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal patterns may be formed of aluminum (Al) or tungsten (W).

The memory device <NUM> may include the at least one upper chip including the cell region. For example, as illustrated in <FIG>, the memory device <NUM> may include two upper chips. However, the number of the upper chips is not limited thereto. In the case in which the memory device <NUM> includes the two upper chips, a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2 and the lower chip including the peripheral circuit region PERI may be manufactured separately, and then, the first upper chip, the second upper chip and the lower chip may be connected to each other by the bonding method to manufacture the memory device <NUM>. The first upper chip may be turned over and then may be connected to the lower chip by the bonding method, and the second upper chip may also be turned over and then may be connected to the first upper chip by the bonding method. Hereinafter, upper and lower portions of each of the first and second upper chips will be defined based on before each of the first and second upper chips is turned over. In other words, an upper portion of the lower chip may mean an upper portion defined based on a +Z-axis direction, and the upper portion of each of the first and second upper chips may mean an upper portion defined based on a -Z-axis direction in <FIG>. However, embodiments of the disclosure are not limited thereto. In certain embodiments, one of the first upper chip and the second upper chip may be turned over and then may be connected to a corresponding chip by the bonding method.

Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device <NUM> may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA. In some embodiments, the memory cell array <NUM> of <FIG> may be formed in the first and second cell regions CELL1 and CELL2 and the peripheral circuits excluding the memory cell array <NUM> may be formed in the peripheral circuit region PERI.

The peripheral circuit region PERI may include a first substrate <NUM> and a plurality of circuit elements 220a, 220b and 220c formed on the first substrate <NUM>. An interlayer insulating layer <NUM> including one or more insulating layers may be provided on the plurality of circuit elements 220a, 220b and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b and 220c may be provided in the interlayer insulating layer <NUM>. For example, the plurality of metal lines may include first metal lines 230a, 230b and 230c connected to the plurality of circuit elements 220a, 220b and 220c, and second metal lines 240a, 240b and 240c formed on the first metal lines 230a, 230b and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230a, 230b and 230c may be formed of tungsten having a relatively high electrical resistivity, and the second metal lines 240a, 240b and 240c may be formed of copper having a relatively low electrical resistivity.

The first metal lines 230a, 230b and 230c and the second metal lines 240a, 240b and 240c are illustrated and described in the present embodiments. However, embodiments of the disclosure are not limited thereto. In certain embodiments, at least one or more additional metal lines may further be formed on the second metal lines 240a, 240b and 240c. In this case, the second metal lines 240a, 240b and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b and 240c may be formed of copper having an electrical resistivity lower than that of aluminum of the second metal lines 240a, 240b and 240c.

The interlayer insulating layer <NUM> may be disposed on the first substrate <NUM>, and may include an insulating material such as silicon oxide and/or silicon nitride.

Each of the first and second cell regions CELL1 and CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate <NUM> and a common source line <NUM>. A plurality of word lines <NUM> (<NUM> to <NUM>) may be stacked on the second substrate <NUM> in a direction (i.e., the Z-axis direction) perpendicular to a top surface of the second substrate <NUM>. String selection lines and a ground selection line may be disposed on and under the word lines <NUM>, and the plurality of word lines <NUM> may be disposed between the string selection lines and the ground selection line. Likewise, the second cell region CELL2 may include a third substrate <NUM> and a common source line <NUM>, and a plurality of word lines <NUM> (<NUM> to <NUM>) may be stacked on the third substrate <NUM> in a direction (i.e., the Z-axis direction) perpendicular to a top surface of the third substrate <NUM>. Each of the second substrate <NUM> and the third substrate <NUM> may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystalline epitaxial layer grown on a single-crystalline silicon substrate. A plurality of channel structures CH may be formed in each of the first and second cell regions CELL1 and CELL2.

In some embodiments, as illustrated in a region 'A1', the channel structure CH may be provided in the bit line bonding region BLBA, and may extend in the direction perpendicular to the top surface of the second substrate <NUM> to penetrate the word lines <NUM>, the string selection lines, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulation layer. The channel layer may be electrically connected to a first metal line 350c and a second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line, and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate <NUM>.

In some embodiments, as illustrated in a region 'A2', the channel structure CH may include a lower channel LCH and an upper channel UCH, which are connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in the direction perpendicular to the top surface of the second substrate <NUM> to penetrate the common source line <NUM> and lower word lines <NUM> and <NUM>. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulation layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate upper word lines <NUM> to <NUM>. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulation layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As a length of a channel increases, due to characteristics of manufacturing processes, it may be difficult to form a channel having a substantially uniform width. The memory device <NUM> according to the present embodiments may include a channel having improved width uniformity due to the lower channel LCH and the upper channel UCH which are formed by the processes performed sequentially.

In the case in which the channel structure CH includes the lower channel LCH and the upper channel UCH as illustrated in the region 'A2', a word line located near to a boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, the word lines <NUM> and <NUM> adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word line may be less than the number of pages corresponding to the memory cells connected to a general word line. A level of a voltage applied to the dummy word line may be different from a level of a voltage applied to the general word line, and thus it is possible to reduce an influence of a non-uniform channel width between the lower and upper channels LCH and UCH on an operation of the memory device <NUM>.

Meanwhile, the number of the lower word lines <NUM> and <NUM> penetrated by the lower channel LCH is less than the number of the upper word lines <NUM> to <NUM> penetrated by the upper channel UCH in the region 'A2'. However, embodiments of the disclosure are not limited thereto. In certain embodiments, the number of the lower word lines penetrated by the lower channel LCH may be equal to or more than the number of the upper word lines penetrated by the upper channel UCH. In addition, structural features and connection relation of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as those of the channel structure CH disposed in the first cell region CELL1.

In the bit line bonding region BLBA, a first through-electrode THV1 may be provided in the first cell region CELL1, and a second through-electrode THV2 may be provided in the second cell region CELL2. As illustrated in <FIG>, the first through-electrode THV1 may penetrate the common source line <NUM> and the plurality of word lines <NUM>. In certain embodiments, the first through-electrode THV1 may further penetrate the second substrate <NUM>. The first through-electrode THV1 may include a conductive material. Alternatively, the first through-electrode THV1 may include a conductive material surrounded by an insulating material. The second through-electrode THV2 may have the same shape and structure as the first through-electrode THV1.

In some embodiments, the first through-electrode THV1 and the second through-electrode THV2 may be electrically connected to each other through a first through-metal pattern 372d and a second through-metal pattern 472d. The first through-metal pattern 372d may be formed at a bottom end of the first upper chip including the first cell region CELL1, and the second through-metal pattern 472d may be formed at a top end of the second upper chip including the second cell region CELL2. The first through-electrode THV1 may be electrically connected to the first metal line 350c and the second metal line 360c. A lower via 371d may be formed between the first through-electrode THV1 and the first through-metal pattern 372d, and an upper via 471d may be formed between the second through-electrode THV2 and the second through-metal pattern 472d. The first through-metal pattern 372d and the second through-metal pattern 472d may be connected to each other by the bonding method.

In addition, in the bit line bonding region BLBA, an upper metal pattern <NUM> may be formed in an uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern <NUM> having the same shape as the upper metal pattern <NUM> may be formed in an uppermost metal layer of the first cell region CELL1. The upper metal pattern <NUM> of the first cell region CELL1 and the upper metal pattern <NUM> of the peripheral circuit region PERI may be electrically connected to each other by the bonding method. In the bit line bonding region BLBA, the bit line 360c may be electrically connected to a page buffer included in the peripheral circuit region PERI. For example, some of the circuit elements 220c of the peripheral circuit region PERI may constitute the page buffer, and the bit line 360c may be electrically connected to the circuit elements 220c constituting the page buffer through an upper bonding metal pattern 370c of the first cell region CELL1 and an upper bonding metal pattern 270c of the peripheral circuit region PERI.

Referring continuously to <FIG>, in the word line bonding region WLBA, the word lines <NUM> of the first cell region CELL1 may extend in a second direction (e.g., an X-axis direction) parallel to the top surface of the second substrate <NUM> and may be connected to a plurality of cell contact plugs <NUM> (<NUM> to <NUM>). First metal lines 350b and second metal lines 360b may be sequentially connected onto the cell contact plugs <NUM> connected to the word lines <NUM>. In the word line bonding region WLBA, the cell contact plugs <NUM> may be connected to the peripheral circuit region PERI through upper bonding metal patterns 370b of the first cell region CELL1 and upper bonding metal patterns 270b of the peripheral circuit region PERI.

The cell contact plugs <NUM> may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some of the circuit elements 220b of the peripheral circuit region PERI may constitute the row decoder, and the cell contact plugs <NUM> may be electrically connected to the circuit elements 220b constituting the row decoder through the upper bonding metal patterns 370b of the first cell region CELL1 and the upper bonding metal patterns 270b of the peripheral circuit region PERI. In some embodiments, an operating voltage of the circuit elements 220b constituting the row decoder may be different from an operating voltage of the circuit elements 220c constituting the page buffer. For example, the operating voltage of the circuit elements 220c constituting the page buffer may be greater than the operating voltage of the circuit elements 220b constituting the row decoder.

Likewise, in the word line bonding region WLBA, the word lines <NUM> of the second cell region CELL2 may extend in the second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate <NUM> and may be connected to a plurality of cell contact plugs <NUM> (<NUM> to <NUM>). The cell contact plugs <NUM> may be connected to the peripheral circuit region PERI through an upper metal pattern of the second cell region CELL2 and lower and upper metal patterns and a cell contact plug <NUM> of the first cell region CELL1.

In the word line bonding region WLBA, the upper bonding metal patterns 370b may be formed in the first cell region CELL1, and the upper bonding metal patterns 270b may be formed in the peripheral circuit region PERI. The upper bonding metal patterns 370b of the first cell region CELL1 and the upper bonding metal patterns 270b of the peripheral circuit region PERI may be electrically connected to each other by the bonding method. The upper bonding metal patterns 370b and the upper bonding metal patterns 270b may be formed of aluminum, copper, or tungsten.

In the external pad bonding region PA, a lower metal pattern 371e may be formed in a lower portion of the first cell region CELL1, and an upper metal pattern 472a may be formed in an upper portion of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 may be connected to each other by the bonding method in the external pad bonding region PA. Likewise, an upper metal pattern 372a may be formed in an upper portion of the first cell region CELL1, and an upper metal pattern 272a may be formed in an upper portion of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI may be connected to each other by the bonding method.

Common source line contact plugs <NUM> and <NUM> may be disposed in the external pad bonding region PA. The common source line contact plugs <NUM> and <NUM> may be formed of a conductive material such as a metal, a metal compound, and/or doped polysilicon. The common source line contact plug <NUM> of the first cell region CELL1 may be electrically connected to the common source line <NUM>, and the common source line contact plug <NUM> of the second cell region CELL2 may be electrically connected to the common source line <NUM>. A first metal line 350a and a second metal line 360a may be sequentially stacked on the common source line contact plug <NUM> of the first cell region CELL1, and a first metal line 450a and a second metal line 460a may be sequentially stacked on the common source line contact plug <NUM> of the second cell region CELL2.

Input/output pads <NUM>, <NUM> and <NUM> may be disposed in the external pad bonding region PA. Referring to <FIG>, a lower insulating layer <NUM> may cover a bottom surface of the first substrate <NUM>, and a first input/output pad <NUM> may be formed on the lower insulating layer <NUM>. The first input/output pad <NUM> may be connected to at least one of a plurality of the circuit elements 220a disposed in the peripheral circuit region PERI through a first input/output contact plug <NUM> and may be separated from the first substrate <NUM> by the lower insulating layer <NUM>. In addition, a side insulating layer may be disposed between the first input/output contact plug <NUM> and the first substrate <NUM> to electrically isolate the first input/output contact plug <NUM> from the first substrate <NUM>.

An upper insulating layer <NUM> covering a top surface of the third substrate <NUM> may be formed on the third substrate <NUM>. A second input/output pad <NUM> and/or a third input/output pad <NUM> may be disposed on the upper insulating layer <NUM>. The second input/output pad <NUM> may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through second input/output contact plugs <NUM> and <NUM>, and the third input/output pad <NUM> may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through third input/output contact plugs <NUM> and <NUM>.

In some embodiments, the third substrate <NUM> may not be disposed in a region in which the input/output contact plug is disposed. For example, as illustrated in a region 'B', the third input/output contact plug <NUM> may be separated from the third substrate <NUM> in a direction parallel to the top surface of the third substrate <NUM> and may penetrate an interlayer insulating layer <NUM> of the second cell region CELL2 so as to be connected to the third input/output pad <NUM>. In this case, the third input/output contact plug <NUM> may be formed by at least one of various processes.

In some embodiments, as illustrated in a region 'B <NUM>', the third input/output contact plug <NUM> may extend in a third direction (e.g., the Z-axis direction), and a diameter of the third input/output contact plug <NUM> may become progressively greater toward the upper insulating layer <NUM>. In other words, a diameter of the channel structure CH described in the region 'A1' may become progressively less toward the upper insulating layer <NUM>, but the diameter of the third input/output contact plug <NUM> may become progressively greater toward the upper insulating layer <NUM>. For example, the third input/output contact plug <NUM> may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other by the bonding method.

In certain embodiments, as illustrated in a region 'B2', the third input/output contact plug <NUM> may extend in the third direction (e.g., the Z-axis direction), and a diameter of the third input/output contact plug <NUM> may become progressively less toward the upper insulating layer <NUM>. In other words, like the channel structure CH, the diameter of the third input/output contact plug <NUM> may become progressively less toward the upper insulating layer <NUM>. For example, the third input/output contact plug <NUM> may be formed together with the cell contact plugs <NUM> before the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

In certain embodiments, the input/output contact plug may overlap with the third substrate <NUM>. For example, as illustrated in a region 'C', the second input/output contact plug <NUM> may penetrate the interlayer insulating layer <NUM> of the second cell region CELL2 in the third direction (e.g., the Z-axis direction) and may be electrically connected to the second input/output pad <NUM> through the third substrate <NUM>. In this case, a connection structure of the second input/output contact plug <NUM> and the second input/output pad <NUM> may be realized by various methods.

In some embodiments, as illustrated in a region 'C1', an opening <NUM> may be formed to penetrate the third substrate <NUM>, and the second input/output contact plug <NUM> may be connected directly to the second input/output pad <NUM> through the opening <NUM> formed in the third substrate <NUM>. In this case, as illustrated in the region 'C1', a diameter of the second input/output contact plug <NUM> may become progressively greater toward the second input/output pad <NUM>. However, embodiments of the disclosure are not limited thereto, and in certain embodiments, the diameter of the second input/output contact plug <NUM> may become progressively less toward the second input/output pad <NUM>.

In certain embodiments, as illustrated in a region 'C2', the opening <NUM> penetrating the third substrate <NUM> may be formed, and a contact <NUM> may be formed in the opening <NUM>. An end of the contact <NUM> may be connected to the second input/output pad <NUM>, and another end of the contact <NUM> may be connected to the second input/output contact plug <NUM>. Thus, the second input/output contact plug <NUM> may be electrically connected to the second input/output pad <NUM> through the contact <NUM> in the opening <NUM>. In this case, as illustrated in the region 'C2', a diameter of the contact <NUM> may become progressively greater toward the second input/output pad <NUM>, and a diameter of the second input/output contact plug <NUM> may become progressively less toward the second input/output pad <NUM>. For example, the second input/output contact plug <NUM> may be formed together with the cell contact plugs <NUM> before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact <NUM> may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

In certain embodiments illustrated in a region 'C3', a stopper <NUM> may further be formed on a bottom end of the opening <NUM> of the third substrate <NUM>, as compared with the embodiments of the region 'C2'. The stopper <NUM> may be a metal line formed in the same layer as the common source line <NUM>. Alternatively, the stopper <NUM> may be a metal line formed in the same layer as at least one of the word lines <NUM>. The second input/output contact plug <NUM> may be electrically connected to the second input/output pad <NUM> through the contact <NUM> and the stopper <NUM>.

Like the second and third input/output contact plugs <NUM> and <NUM> of the second cell region CELL2, a diameter of each of the second and third input/output contact plugs <NUM> and <NUM> of the first cell region CELL1 may become progressively less toward the lower metal pattern 371e or may become progressively greater toward the lower metal pattern 371e.

Meanwhile, in some embodiments, a slit <NUM> may be formed in the third substrate <NUM>. For example, the slit <NUM> may be formed at a certain position of the external pad bonding region PA. For example, as illustrated in a region 'D', the slit <NUM> may be located between the second input/output pad <NUM> and the cell contact plugs <NUM> when viewed in a plan view. Alternatively, the second input/output pad <NUM> may be located between the slit <NUM> and the cell contact plugs <NUM> when viewed in a plan view.

In some embodiments, as illustrated in a region 'D1', the slit <NUM> may be formed to penetrate the third substrate <NUM>. For example, the slit <NUM> may be used to prevent the third substrate <NUM> from being finely cracked when the opening <NUM> is formed. However, embodiments of the disclosure are not limited thereto, and in certain embodiments, the slit <NUM> may be formed to have a depth ranging from about <NUM>% to about <NUM>% of a thickness of the third substrate <NUM>.

In certain embodiments, as illustrated in a region 'D2', a conductive material <NUM> may be formed in the slit <NUM>. For example, the conductive material <NUM> may be used to discharge a leakage current occurring in driving of the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material <NUM> may be connected to an external ground line.

In certain embodiments, as illustrated in a region 'D3', an insulating material <NUM> may be formed in the slit <NUM>. For example, the insulating material <NUM> may be used to electrically isolate the second input/output pad <NUM> and the second input/output contact plug <NUM> disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material <NUM> is formed in the slit <NUM>, it is possible to prevent a voltage provided through the second input/output pad <NUM> from affecting a metal layer disposed on the third substrate <NUM> in the word line bonding region WLBA.

Meanwhile, in certain embodiments, the first to third input/output pads <NUM>, <NUM> and <NUM> may be selectively formed. For example, the memory device <NUM> may be realized to include only the first input/output pad <NUM> disposed on the first substrate <NUM>, to include only the second input/output pad <NUM> disposed on the third substrate <NUM>, or to include only the third input/output pad <NUM> disposed on the upper insulating layer <NUM>.

In some embodiments, at least one of the second substrate <NUM> of the first cell region CELL1 or the third substrate <NUM> of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after a bonding process. An additional layer may be stacked after the removal of the substrate. For example, the second substrate <NUM> of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then, an insulating layer covering a top surface of the common source line <NUM> or a conductive layer for connection may be formed. Likewise, the third substrate <NUM> of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then, the upper insulating layer <NUM> covering a top surface of the common source line <NUM> or a conductive layer for connection may be formed.

According to example embodiments, At least one of the components, elements, modules and units (collectively "components" in this paragraph) represented by a block in the drawings may use a direct circuit structure, such as a processor, a logic circuit, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. These components may include the memory controller <NUM>, the control logic <NUM>, etc. shown in <FIG> and <FIG>, not being limited thereto. Also, at least one of these components may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Further, at least one of these components may include or may be implemented by a processor such as a central processing unit (CPU), a microprocessor, or the like that performs the respective functions.

Claim 1:
A method of operating a storage system comprising a host device (<NUM>) and a storage device (<NUM>), the method comprising:
transmitting (S510), by the host device, a first write command and a logical address to the storage device;
transmitting (S520), by the storage device, first normal offset information about a normal area and first cache offset information about a cache area included in a host memory of the host device to the host device;
merging, by the host device, first write data with second write data to form merged write data, based on one of a program unit or a stream identifier, the first write data and the second write data stored in the normal area;
copying (S530), by the host device, the merged write data to the cache area based on the first normal offset information and the first cache offset information; and
transmitting (S560), by the storage device, a first response to the first write command to the host device, wherein reception of the merged write data from the host device before transmitting the first response is omitted.