Patent Description:
A power conversion apparatus such as an active filter, connected to each power supply line of a three-phase AC power supply to which a load of an electric apparatus or the like is connected, in parallel with the load, to suppress harmonic components included in a current flowing in the load, is known (for example, <CIT>).

<CIT> discloses a power conversion apparatus configured to connect to power supply lines of a three-phase AC power supply to which a load is connected, in parallel with the load, includes a multi-level converter and a controller. The multi-level converter includes clusters configured to connect to each of the power supply lines. The controller is configured to detect harmonic components of load currents flowing to the load, obtain compensation currents made to flow to each of the power supply lines to suppress the harmonic components of the load currents flowing to the load, and control output voltages of the clusters of the multi-level converter to obtain the compensation currents.

<CIT> discloses a seven-level static synchronous compensator based on an unbalanced power grid.

<NPL>, shows a zero-sequence current controller for modular multilevel converters in HVDC applications under unbalanced grid conditions.

<NPL>, shows an application of modular multilevel cascaded converters for combined active harmonic current elimination and reactive power compensation in a power distribution line.

When unbalance occurs in the voltage of the three-phase AC power supply, unbalance occurs in each phase current flowing between each power supply line and the power conversion apparatus. When unbalance occurs in each phase current flowing between each power supply line and the power conversion apparatus, the currents concentrate in the switch elements and capacitors of a specific phase in the power conversion apparatus, which may lead to the destruction of the switch elements and a decrease in the life of the capacitors.

In general, a power conversion apparatus configured to connect to power supply lines of a three-phase AC power supply to which a load is connected, in parallel with the load, includes a multi-level converter and a controller. The multi-level converter includes clusters configured to connect to each of the power supply lines. The controller is configured to detect harmonic components of load currents flowing to the load, obtain compensation currents made to flow to each of the power supply lines to suppress the harmonic components of the load currents flowing to the load, and control output voltages of the clusters of the multi-level converter to obtain the compensation currents. The controller is configured to compare each of effective values of currents between the power supply lines and the clusters of the multi-level converter with a threshold value, and control values of the compensation currents such that the effective values of the currents fall within the threshold value.

A detail description of the teachings of the present disclosure is made hereinafter with reference to the accompanying drawings.

As shown in <FIG>, for example, an air conditioning apparatus <NUM> which is a load is connected to R-, S-, and T-phase power supply lines (first, second, and third power supply lines) Lr, Ls, and Lt of a three-phase AC power supply <NUM>. The air conditioning apparatus <NUM> includes a rectifier circuit <NUM> that rectifies power supply voltages Er, Es, and Et of the power supply lines Lr, Ls, and Lt by a plurality of diodes in bridge connection, a DC capacitor <NUM> to which an output voltage of the rectifier circuit <NUM> is applied via a DC reactor <NUM>, an inverter <NUM> to which a voltage of the DC capacitor <NUM> is converted into an AC voltage of a predetermined frequency and is output, a compressor motor <NUM> that is operated by the output of the inverter <NUM>, and the like.

A power conversion apparatus <NUM> is connected to the power supply lines Lr, Ls, and Lt to which the air conditioning apparatus <NUM> is connected, in parallel with the air conditioning apparatus <NUM>.

The power conversion apparatus <NUM> includes an initial charging circuit A, buffer reactors 11r, <NUM>, and 11t, clusters (first, second, and third clusters) 12r, <NUM>, and 12t having one-side ends connected to the power supply lines Lr, Ls, and Lt via the initial charging circuit A and the buffer reactors 11r, <NUM>, and 11t and having the other ends interconnected (star connection), a detection section (first detection section) <NUM> which is located on the air conditioning apparatus <NUM> side with respect to the connection position of the initial charging circuit A in the power supply lines Lr, Ls, and Lt to detect currents (load currents) Ir, Is, and It flowing to the power supply voltages Er, Es, and Et and the air conditioning apparatus <NUM>, a detection section (second detection section) <NUM> which is arranged in current paths between the initial charging circuit A and the buffer reactors 11r, <NUM>, and 11t to detect currents Irm, Ism, and Itm flowing between the power supply lines Lr, Ls, and Lt and the clusters 12r, <NUM>, and 12t, a detection section <NUM> which is connected to the power supply lines Lr, Ls, and Lt to detect the zero crossing point of line voltages Ers, Est, and Etr, and a controller <NUM> which controls the clusters 12r, <NUM>, and 12t according to the detection results of the detection sections <NUM>, <NUM>, and <NUM>. A multi-level converter <NUM> is composed of clusters 12r, <NUM>, and 12t. The controller <NUM> controls the multi-level converter <NUM>.

The above initial charging circuit A includes resistors Rr, Rs, and Rt inserted into current paths between the power lines Lr, Ls, and Lt and the buffer reactors 11r, <NUM>, and 11t, and switchgear Sr, Ss, and St connected in parallel to the resistors Rr, Rs, and Rt. The switchgear Sr, Ss, and St is relay contacts or semiconductor switches whose opening and closing are controlled by the controller <NUM>, forms current paths for charging the capacitor via the resistors Rr, Rs, and Rt by continuing the off state which has been made at the power-on of the three-phase AC power supply <NUM>, and forms bypass current paths for the resistors Rr, Rs, and Rt by turning on after a predetermined time has elapsed after the power-on. The predetermined time is the time required for the capacitor <NUM> in each of unit converters 20r to 20t in the clusters 12r, <NUM>, and 12t to be sufficiently charged. The resistors Rr, Rs, and Rt may be replaced with a plurality of positive characteristic thermistors.

The above cluster 12r connected to the power supply line Lr is a so-called multi-series converter cluster in which a plurality of unit converters (cells) 20r each selectively generating and outputting a plurality of levels of (multi-level) DC voltages are connected in series (cascade connection), and generates and outputs an AC voltage Vrm with a waveform similar to a sine wave to reduce harmonics by summing output voltages (cell output voltages) of the respective unit converters 20r.

Each unit converter 20r includes a pair of output terminals, switch elements <NUM>, <NUM>, <NUM>, and <NUM> each including a parasitic diode D, a capacitor (DC capacitor) <NUM> connected to the pair of output terminals via the switch elements <NUM> to <NUM>, a voltage detection section <NUM> which detects a voltage (capacitor voltage) Vc of the capacitor <NUM> and notifies the controller <NUM> of the voltage, and the like, and generates and outputs DC voltages of a plurality of levels (positive, zero, and negative levels) by selective formation of a plurality of current paths caused by turning on and off (opening and closing) the switch elements <NUM> to <NUM>. The switch elements <NUM> to <NUM> are semiconductor switch elements and, for example, MOSFETs or IGBTs are used as the switch elements.

The above cluster <NUM> connected to the power supply line Ls is a so-called multi-series converter cluster in which a plurality of unit converters <NUM> each selectively generating and outputting a plurality of levels of DC voltages are connected in series, and generates and outputs an AC voltage Vsm with a waveform similar to a sine wave to reduce harmonics by summing output voltages (cell output voltages) of the respective unit converters <NUM>. A configuration of each unit converter <NUM> is the same as that of each unit converter 20r.

The above cluster 12t connected to the power supply line Lt is a so-called multi-series converter cluster in which a plurality of unit converters 20t each selectively generating and outputting a plurality of levels of DC voltages are connected in series, and generates and outputs an AC voltage Vtm with a waveform similar to a sine wave to reduce harmonics by summing output voltages (cell output voltages) of the respective unit converters 20t. A configuration of each unit converter 20t is the same as that of each unit converter 20r.

The above detection section <NUM> detects the zero crossing points of the line voltages Ers, Est, and Etr and includes zero crossing point detection circuits of the configuration shown in <FIG> for three phases. Configurations of these zero crossing point detection circuits are the same as each other. The configuration of the zero crossing point detection circuit for the line voltage Ers is shown in <FIG> as a representative example.

The zero crossing point detection circuit for the line voltage Ers adds the line voltage Ers of the power supply lines Lr and Ls to a photodiode 33a of a photocoupler <NUM> via a diode <NUM> and a resistor <NUM>, adds a constant DC voltage V between a collector and an emitter of a phototransistor 33b of the photocoupler <NUM> via a resistor <NUM>, and outputs a voltage Vro generated between the collector and emitter of the phototransistor 33b as a zero crossing point detection signal. In other words, the photodiode 33a repeatedly emitting and quenching light in response to changes in the line voltage Ers, and outputs the zero crossing point detection signal Vro of the waveform whose voltage changes between high and low levels at each zero crossing point of the line voltage Ers as shown in <FIG> by turning on and off the phototransistor 33b in accordance with the light emission and quenching.

The point at which the zero crossing point detection signal Vro changes from a high level to a low level and changes from a low level to a high level is the zero crossing point. Similarly, the zero crossing point detection circuit for the line voltage Est outputs a zero crossing point detection signal Vso, and the zero crossing point detection circuit for the line voltage Etr outputs a zero crossing point detection signal Vto.

The controller <NUM> detects harmonic components of the load currents Ir, Is, and It detected in detection section <NUM> to make currents flowing to the power supply, i.e., currents (Ir+Irm), (Is+Ism), and (It+Itm) to be described below as close as possible to sine waves synchronized with the power supply voltages Er, Es, and Et, calculates compensation currents (compensation currents to be added to the load currents Ir, Is, and It) which need to flow to power supply lines Lr, Ls, and Lt to suppress the harmonic components, calculates the output voltages (AC voltages) Vrm, Vsm, and Vtm of the multi-level converter necessary to obtain the compensation currents, and controls switching of each of the unit converters 20r to 20t in the multi-level converter <NUM> to obtain the output voltages Vrm, Vsm, and Vtm.

The harmonic components included in the load currents Ir, Is, and It can be suppressed by supplying the AC voltages Vrm, Vsm, and Vtm from the multi-level converter <NUM> to the power supply lines Lr, Ls, and Lt. In other words, the power conversion apparatus <NUM> operates as a so-called active filter.

In particular, the controller <NUM> controls (feedback control) the values of the above compensation currents such that the effective values of the currents Irm, Ism, and Itm flowing between the power supply lines Lr, Ls, and Lt and the multi-level converter <NUM> fall within a threshold value (predetermined upper limit). The currents Irm, Ism, and Itm are hereinafter referred to as the input currents to the multi-level converter <NUM>.

The controller <NUM> includes as specific means for performing these controls, a harmonic detection section <NUM>, a compensation current calculation section <NUM>, a gain multiplication section <NUM>, a voltage control section <NUM>, a coordinate conversion section <NUM>, an effective value calculation section <NUM>, and a gain control section <NUM> as shown in <FIG>.

The harmonic detection section <NUM> detects harmonic components Irh, Ish, and Ith of the load currents Ir, Is, and It detected by the detection section <NUM>. The compensation current calculation section <NUM> calculates command values (referred to as compensation current command values) Id and Iq on rotary coordinate axes of compensation current (compensation to be added to the load currents Ir, Is, and It) which are to flow to the power supply lines Lr, Ls, and Lt to suppress the harmonic components Irh, Ish, and Ith detected by the harmonic detection section <NUM>. The gain multiplication section <NUM> multiplies the compensation current command values Id and Iq calculated in the compensation current calculation section <NUM> by gain K, and outputs results of the multiplication as compensation current command values Idref and Iqref. The voltage control section <NUM> calculates the output voltages (AC voltages) Vrm, Vsm, and Vtm of the multi-level converter <NUM> required to generate the input currents Irm, Ism, and Itm following the compensation current command values Idref and Iqref output from the gain multiplication section <NUM>.

The controller <NUM> controls the output voltages of the unit converters 20r to 20t in the multilevel converter <NUM> such that the output voltages Vrm, Vsm, and Vtm calculated in the voltage control section <NUM> can be obtained by the multi-level converter <NUM>.

The coordinate conversion section <NUM> converts the compensation current command values Id and Iq calculated in the compensation current calculation section <NUM> into input current command values Irm_ref, Ism_ref, and Itm_ref on the stationary coordinate axes by coordinate conversion. The effective value calculation section <NUM> calculates effective values Irm_rms, Ism_rms, and Itm_rms of the current input currents Irm, Ism, and Itm to the multi-level converter <NUM>, based on the input current command values Irm_ref, Ism_ref, and Itm_ref obtained in the coordinate conversion section <NUM>.

The gain control section <NUM> compares the effective values Irm_rms, Ism_rms, and Itm_rms calculated in the effective value calculation section <NUM> with a predetermined threshold value Im, and controls the gain K of the multiplication section <NUM> in accordance with results of the comparison. More specifically, the gain control section <NUM> sets the gain K to "<NUM>" when the effective values Irm_rms, Ism_rms, and Itm_rms are less than or equal to the threshold value Im (K = "<NUM>"). More specifically, if any of the effective values Irm_rms, Ism_rms, and Itm_rms is greater than the threshold value Im, the gain control section <NUM> sets a ratio of the threshold value Im to the maximum value among the effective values Irm_rms, Ism_rms, and Itm_rms (Im / maximum effective value) as the gain K (= less than "<NUM>").

Examples of the line voltages Ers, Est, and Etr and the load currents Ir, Is, and It in a case where the power supply voltages Er, Es, and Et are in an unbalanced state are shown in <FIG>, and examples of accompanying changes in the effective values Irm_rms, Ism_rms, and Itm_rms of the input currents Irm, Ism, and Itm are shown in <FIG>.

In other words, when the power supply voltages Er, Es, and Et are in an unbalanced state, the load currents Ir, Is, and It become unbalanced. Since the multi-level converter <NUM> outputs the currents Irm, Ism, and Itm that compensate for the unbalanced load currents Ir, Is, and Itm, the currents may be concentrated in clusters of specific phases, and the effective value Ir_rms of the input current Irm may rise significantly and exceed the threshold value Im as shown in, for example, <FIG>, which may lead to the destruction of the switch elements <NUM> to <NUM> of the respective unit converters 20r in the cluster 12r and the decrease in life of the capacitor <NUM>.

Therefore, when the effective value Irm_rms of the input current Irm reaches the threshold value Im, the gain K to the compensation current command values Id and Iq for harmonic suppression is set to a value less than the usual "<NUM>" such that the effective value Irm_rms of the input current Irm can be suppressed below the threshold value Im. The ratio of the threshold value Im to the maximum value among the effective values Irm_rms, Ism_rms, and Itm_rms (Im / maximum effective value) is set as the gain K. This setting allows the current indicating the maximum value among the effective values Irm_rms, Ism_rms, and Itm_rms to fall within the threshold value Im.

The currents of the effective values that are not the maximum are controlled to lower values in accordance with the decrease of the gain K. Each of the effective values Irm_rms, Ism_rms, and Itm_rms is reduced by a uniform ratio (gain K). The compensation currents for harmonic suppression are reduced by the same ratio. The destruction of the switch elements <NUM> to <NUM> of the respective unit converters 20r in the cluster 12r and the decrease in life of the capacitor <NUM> can be thereby prevented.

Changes in the capacitor voltages Vc at initial charging of each of the capacitors <NUM> in the clusters 12r, <NUM>, and 12t in a case where the power supply voltages Er, Es, and Et are in the unbalanced state are shown in <FIG>. Vcr is an average value of the capacitor voltages Vc in the multi-level converter 12r, Vcs is an average value of the capacitor voltage Vc in the multi-level converter <NUM>, and Vet is an average value of the capacitor voltages Vc in the multi-level converter 12t. In this example, the average capacitor voltage values Vcr and Vcs remain substantially the same, while the average capacitor voltage value Vct is lower than the average capacitor voltage values Vcr and Vcs. In other words, the average capacitor voltage values Vcr, Vcs, and Vet become unbalanced.

The controller <NUM> obtains the line voltages Ers, Est, and Etr by the following computation using the zero crossing point signals Vro, Vso, and Vto obtained in the detection section <NUM>, the average value Vcr of the capacitor voltages Vc detected in the voltage detection sections <NUM> of the respective unit converters 20r in the cluster 12r, the average value Vcs of the capacitor voltages Vc detected in the voltage detection sections <NUM> of the respective unit converters <NUM> in the cluster <NUM>, the average value Vcs of the capacitor voltages Vc detected in the voltage detection sections <NUM> of the respective unit converters 20t in the cluster 12t, number N of the unit converters 20r in the cluster 12r, number N of the unit converters <NUM> in the cluster <NUM>, and number N of the unit converters 20t in the cluster 12t. √<NUM> is a square root of "<NUM>". <MAT> <MAT> <MAT>.

Then, controller <NUM> calculates the unbalance rate by the following equation using the obtained line voltages Ers, Est, and Etr.

The average voltage Eave is an average value of the line voltages Ers, Est, and Etr and is obtained as (Ers + Est + Etr) / <NUM>. When a value obtained by dividing the largest value among differences (absolute values) between this average voltage Eave and the line voltages Ers, Est, Etr, i.e., Eave-Ers, Eave-Est, and Eave-Est by the average voltage Eave is expressed as a percentage, the value is the unbalance ratio.

As shown in the flowchart of <FIG>, the controller <NUM> calculates the unbalance rate of the power supply voltages Er, Es, and Et (S1) and determines whether the calculated unbalance rate is less than a set value, for example, less than <NUM>% (S2).

If the unbalance rate is less than <NUM>% (YES in S2), the controller <NUM> continues the operation of the multi-level converter <NUM> to reduce harmonics by determining that the effective values Irm_rms, Ism_rms, and Itm_rms of the input currents Irm, Ism, and Itm can be suppressed below the threshold value Im by controlling the gain K (S3).

If the unbalance rate is <NUM>% or more (NO in S2), the controller <NUM> stops the multi-level converter <NUM> to protect the multi-level converter <NUM> by determining that it is difficult to suppress the effective values Irm_rms, Ism_rms, and Itm_rms of the input currents Irm, Ism, and Itm below the threshold value Im.

In the foregoing, a power conversion apparatus in which the other ends of the clusters 12r, <NUM>, and 12t are interconnected (star connection) has been described, but a power conversion apparatus in which the clusters 12r, <NUM>, and 12t are connected between the power supply lines Lr, Ls, and Lt, i.e., by so-called delta connection can also be carried out.

Claim 1:
A power conversion apparatus configured to connect to power supply lines (Lr, Ls, and Lt) of a three-phase AC power supply (<NUM>) to which a load (<NUM>) is connected, in parallel with the load (<NUM>), the power conversion apparatus comprising:
a multi-level converter (<NUM>) including clusters (12r, <NUM>, and 12t) configured to connect to each of the power supply lines (Lr, Ls, and Lt); and
a controller (<NUM>) configured to detect harmonic components (Irh, Ish, and Ith) of load currents (Ir, Is, and It) flowing to the load (<NUM>), obtain compensation currents made to flow to each of the power supply lines (Lr, Ls, and Lt) to suppress the harmonic components (Irh, Ish, and Ith) of the load currents (Ir, Is, and It) flowing to the load (<NUM>), and control output voltages (Vrm, Vsm, and Vtm) of the clusters (12r, <NUM>, 12t) of the multi-level converter (<NUM>) to obtain the compensation currents,
characterized in that
the controller (<NUM>) is configured to compare each of effective values (Irm_rms, Ism_rms, and Itm_rms) of currents (Irm, Ism, and Itm) between the power supply lines (Lr, Ls, and Lt) and the clusters (12r, <NUM>, and 12t) of the multi-level converter (<NUM>) with a threshold value (Im), and control values of the compensation currents such that the effective values (Irm_rms, Ism_rms, and Itm_rms) of the currents (Irm, Ism, and Itm) fall within the threshold value (Im).