Patent Description:
The semiconductor body comprises an active region. There, for instance a vertical field effect transistor can be formed, having a vertical channel in a body region laterally aside a gate region. By applying a gate voltage, the channel formation can be controlled, namely the vertical current flow between source and drain. In case of a power transistor device, a drift region can additionally be arranged between the body and the drain region. This shall illustrate a possible device formed in the active region, without limiting the universality of the claims and the description.

<CIT> discloses a MOSgated device with a sodium stopper, which is filled with aluminum, and an aluminum frontside metallization on top.

<CIT> describes a process for filling a groove in an insulation layer with tungsten.

<CIT> relates to MOSFETs and IGBTs and shows a frontside metallization partially covered with a passivation layer.

<CIT> discloses a diffusion barrier in a trench, which is filled with silicon nitride and imide.

<CIT> relates to a device with a channel stop trench filled with a channel stop structure. Also <CIT> discloses a die with a channel stopper.

Document <CIT> discloses a vertical groove intersecting the insulation layer serving as an oxide peeling stopper.

It is an object of the present application to provide a semiconductor die with an improved design, as well a method of manufacturing such a die.

This object is achieved by the semiconductor die of claim <NUM>. Moreover, it is achieved by the method of claim <NUM>.

Therein, the die comprises a sodium stopper formed in an insulation layer arranged on the semiconductor body. The sodium stopper is formed of tungsten filled insulation layer groove which intersects the insulation layer in the vertical direction. Laterally, namely perpendicularly to the vertical direction, the insulation layer groove extends around the active region.

A sodium diffusion can in particular occur in undoped layers, and the vertical intersection formed by the sodium stopper can cut a diffusion path in the insulation layer. In particular, it can prevent a sodium diffusion from the edge of the die via the insulation layer into the active region. Therein, the tungsten material filler can allow for a compact design, namely a reduced lateral width of the insulation layer groove (e. in comparison to an aluminum material filler).

The insulation layer groove can for instance have a lateral width of not more than <NUM>, <NUM> or <NUM>, possible lower limits being for instance <NUM>, <NUM> or <NUM>. In general words, an idea of this application is to interrupt the insulation layer with a rather narrow insulation layer groove (e. with a lateral width between <NUM>-<NUM>), which can for instance reduce the area consumption of the edge termination region.

Particular embodiments and features are provided in this description and in the dependent claims. Therein, the individual features shall be disclosed independently of a specific claim category, the disclosure relates to apparatus and device aspects, but also to method and use aspects. If for instance a die or wafer manufactured in a specific way is described, this is also a disclosure of a respective manufacturing process, and vice versa.

The "vertical" direction lies perpendicular to a surface of a layer of the die or wafer, for instance a surface of the insulation layer and/or a surface of the semiconductor body. For instance, the frontside of the insulation layer lies vertically opposite to the semiconductor body. The insulation layer groove intersects the insulation layer vertically, namely extends vertically over the whole distance from the frontside of the insulation layer to the backside thereof. It can for instance also extend further downwards into the semiconductor body (e.g. to form a drain contact). In particular, the insulation layer groove can extend steplessly into the semiconductor body, e.g. without a step between the insulation layer and the semiconductor body, for instance without a discontinuity in diameter. Seen in a vertical cross-section, to avoid a sodium diffusion path circumventing the sodium stopper, a vertical axis through the insulation layer groove does for instance not intersect any insulating material being in contact with the insulation layer, in particular no oxide. For instance, no trench is formed in the semiconductor body vertically below the insulation layer groove, e.g. no trench which is partially or completely filled with an insulation layer material, in particular no trench filled partially or completely with oxide.

The lateral directions lie perpendicular to the vertical direction, and the insulation layer groove or sodium stopper extends laterally around the active region. Seen in a top view, namely in a vertical viewing direction, the insulation layer groove / sodium stopper can extend around the active region over a partial or in particular over a whole circumference. It can separate the active region from the die edge in all lateral directions, forming for instance a closed line seen in the top view (e. with a rectangular shape). The sodium stopper is arranged in the edge termination region between the active region and the edge of the die.

In the active region, a frontside metallization can be arranged on the frontside of the insulation layer, for instance copper or in particular aluminum, e. It can have a thickness of several micrometers and form a source contact. In the semiconductor body, a transistor device can be arranged in the active region, for example a lateral device (with a lateral channel) or in particular a vertical device. As a power device, the transistor can for instance have a breakdown voltage of at least <NUM> V, <NUM> V or <NUM> V, with possible upper limits of for instance not more than <NUM> V, <NUM> V, <NUM> V, <NUM> V or <NUM> V.

A vertical device can comprise a source region formed at the frontside in the semiconductor body, e. adjacent to the insulation layer, and a drain region formed vertically opposite thereto, e. at the backside of the semiconductor body. The drain region can extend over the whole backside of the wafer or die, and a backside metallization for contacting the drain region can be arranged on the backside. Vertically below the source region, the body region can be formed, wherein the gate region can be arranged laterally aside, for instance in a gate trench. The latter can extend into the semiconductor body from the frontside thereof, it can be filled with a gate dielectric covering at least a side wall of the trench and a gate electrode made of an electrically conductive material, for instance polysilicon. Vertically in between the body and the drain region, a drift region can be arranged, being of the same conductivity type as the body region but having a lower doping concentration.

In general, a field electrode can additionally be arranged in the gate trench below the gate electrode ("split gate"). In addition or in particular as an alternative, a field electrode can be arranged in a separate field electrode trench laterally aside the gate trench. Seen in a vertical cross-section, the gate and the field electrode trenches are arranged consecutive in a lateral direction. The gate trenches can for instance be longitudinal trenches which, seen in a top view, can for example form a grid in the active region, the grid defining cells, e. rectangular or in particular quadratic cells. In each cell, a needle shaped field electrode trench can be arranged, e. centrally in the cell. In the needle trench, a spicular or columnar field electrode can be formed, separated from the semiconductor body by a field oxide. Together, the field oxide and the field electrode form a field electrode region.

Independently of the design in the active region, the semiconductor body can for instance comprise a semiconductor substrate (e. silicon), additionally it can comprise an epitaxial layer on the substrate. In the epitaxial layer, the source and body region can be formed, as well as the drift region. The insulation layer is formed on the semiconductor body, it can comprise an oxide, for instance silicon oxide and/or a Borophosphorsilicate glass (BPSG). In particular, the insulation layer can be formed of stacked sublayers, for instance a lower oxide layer and a BPSG layer on top. In general, the tungsten material can fill the insulation layer groove only partly, e. only a lower portion of the groove. Alternatively, it can fill the insulation layer groove entirely, from its lower end to the upper end.

According to the invention a metallization layer made of tungsten material is formed on the frontside of the insulation layer. It is arranged in the edge termination region and covers at least a lateral section of the insulation layer groove. It can cover the entire insulation layer groove or only a lateral portion thereof, e. a portion arranged at a corner of the die. The tungsten metallization layer can for instance be advantageous due to its mechanical stability, in particular in comparison to AlCu. This can reduce a ratcheting or buckling, for example in the corners of the die, and a thin tungsten layer can also be structured more precisely. The metallization layer made of the tungsten material can for instance have a vertical thickness of at least <NUM> or <NUM>, possible upper limits being for instance <NUM>, <NUM> or <NUM>. Limiting the thickness can be advantageous in terms of the mechanical stress, e. prevent a damage of the insulation layer.

In an embodiment, the tungsten material filling the insulation layer groove and the tungsten material forming the metallization layer can be deposited in the same process step, namely with a single tungsten deposition. Alternatively, a multistep process can be applied, the insulation layer groove being filled in a first step, and the metallization layer being formed in a separate second step subsequently. In between the first and the second step, excess tungsten can be removed from the frontside of the passivation layer, e. by a planarization, for instance chemical-mechanical-polishing (CMP). In general, a titanium and/or titanium nitride deposition can precede any tungsten deposition, independently of whether the metallization layer or the tungsten filler is formed.

Above, a possible reduction of the area consumption in the edge termination region has been discussed. In this respect, the metallization layer can for instance have a lateral width of not more than <NUM>, <NUM>, <NUM>, <NUM> or <NUM>, possible lower limits being for instance at least <NUM>, <NUM> or <NUM>. The lateral width can be taken in a vertical cross-section, the sectional plane intersecting the die for instance diagonally, namely along a diagonal from one corner of the die to the diagonally opposite corner. In sum, the metallization layer can for example have an area in a range between <NUM>,<NUM><NUM> and <NUM><NUM>, depending also on the die size.

In an embodiment, the metallization layer is covered by a passivation layer, for instance imide. When the tungsten material forms the metallization layer, for instance no other metal material is arranged vertically between the tungsten and the passivation layer. In other words, the passivation layer can be formed in a direct contact with the tungsten metallization layer, it can for instance be deposited directly onto the latter. Laterally, the passivation layer can cover a portion or in particular the whole metallization layer.

In an embodiment, the tungsten material arranged in the insulation layer groove forms also a drain contact electrically connected to a drain region of the die. As discussed above, the drain region can be formed at a backside of the semiconductor body, wherein the electrical potential is gradually reduced towards the frontside in the active region, reaching the source potential for instance at the body region, e. where the body region is contacted. In contrast, in the edge termination region where the sodium stopper is formed, the semiconductor body below the insulation layer can also be on drain potential. In particular, an epitaxial layer comprising source and body in the active region can be on the drain potential in the edge termination region.

To form the drain contact, the insulation layer groove can extend into the semiconductor body, in particular into the epitaxial layer. Consequently, the tungsten material filler extends into the semiconductor body as well. To enhance the electrical contact, a contact region of the semiconductor body, which is intersected by the tungsten material filler, can for instance be doped, in particular with a higher doping concentration compared to the drift region. It can for example be doped like a source region formed in the active region. Alternatively, it can be formed of polysilicon, e. doped polysilicon. Laterally, the drain contact or the contact region does not necessarily extend along the whole length of the sodium stopper.

In an embodiment, the edge termination region comprises an additional channel stopper in a channel stopper trench. The trench can be filled with a conductive material, e.g. polysilicon, and by applying an electrical potential it can prevent ions from entering. In particular, the channel stopper trench can have the same vertical extension as a gate trench formed in the active region. Like the sodium stopper, the channel stopper is arranged laterally between the active region and the die edge, for instance laterally between the sodium stopper and the die edge. When the sodium stopper forms also a drain contact (see above), the latter can be arranged closer to the active region, namely closer to the active region than the channel stopper. Seen in a vertical cross-section, the insulation layer groove can for instance have a smaller lateral width than the channel stopper trench in the semiconductor body. To apply the electrical potential for the channel stopper function, the channel stopper can for instance be contacted via the same tungsten material frontside metallization like the sodium stopper.

In an embodiment, a chipping stopper trench is additionally formed in the edge termination region, in addition to the sodium stopper and/or the channel stopper. In particular, the chipping stopper trench can extend deeper into the semiconductor body than the channel stopper trench. This combination of a channel trench and a chipping stopper trench having a different depth shall also be disclosed independently of the sodium stopper of claim <NUM>, in particular independently of a sodium stopper with a tungsten material filler. The channel stopper trench can for instance have a vertical depth of <NUM> at minimum and <NUM> at maximum. The vertical depth of the chipping stopper trench can for instance be <NUM> at minimum and <NUM> at maximum. A depth difference between the channel and the chipping stopper trenches can for instance be at least <NUM>, <NUM>, <NUM> or <NUM>, possible upper limits being for instance <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> or <NUM>.

The channel stopper trench can have the same vertical depth as a gate trench in the active region. It can for instance be etched and/or filled in the same process step or steps like the gate trench. The chipping stopper trench can for example have the same vertical depth as a field electrode trench in the active region, e. a needle trench disclosed above. The chipping stopper trench can be etched and/or filled in the same process step or steps as the field electrode trench.

The chipping stopper trench can act as a predetermined cracking or breaking point, stopping for instance a die cracking by releasing the mechanical stress at a defined location. In an embodiment, the chipping stopper trench is filled with an electrically conductive material and serves also as a channel stopper. In particular, the electrically conductive material in the chipping stopper trench can be contacted via the tungsten material metallization layer which contacts also the sodium stopper and/or the channel stopper discussed above. The electrically conductive material can for instance be polysilicon, the chipping stopper trench being filled e. with oxide and polysilicon. In particular, it can be filled like a field electrode trench in the active region. Above the chipping stopper trench, a groove can be formed in the insulation layer vertically aligned with the chipping stopper trench, the groove being filled with an electrically conductive material (e. tungsten material) which electrically connects the filler of the chipping stopper trench to the metallization layer.

In total, e. at least two chipping stopper trenches can be formed between the active region and the die edge, in particular at least two combined channel and chipping stoppers. Possible upper limits can be eight or six chipping stoppers at maximum, in particular not more than three combined channel and chipping stoppers. In the edge termination region, the sodium stopper can for instance be arranged laterally between the at least two combined channel and chipping stoppers, one combined channel and chipping stopper being arranged laterally between the active region and the sodium stopper, another combined channel and chipping stopper being arranged laterally between the sodium stopper and the die edge. When the sodium stopper is also used as a drain contact (see above), for instance one combined channel and chipping stopper at maximum can be arranged laterally between the drain contact and the active region, the drain contact being arranged comparably close to the active region. When the lateral relative arrangement of edge termination structures is discussed, this relates in particular to the arrangement of the structures on the same of the active region in a cross-sectional view.

In an embodiment, a vertical groove intersecting the insulation layer can be formed vertically aligned with the chipping stopper trench, the groove acting as an oxide peeling stopper. It can for instance be arranged laterally in between the sodium stopper and the die edge and/or laterally in between a channel stopper, e. the channel stopper formed in a trench having a reduced depth, and the die edge. The combined chipping and oxide peeling structure can in particular be an alternative to a combined channel and chipping stopper, differing from the latter e. in that no metallization layer is formed on the frontside of the insulation layer vertically above the chipping and oxide peeling stopper. However, the oxide peeling stopper groove can for instance be covered by a passivation layer, e.

The oxide peeling stopper groove can be filled, for instance like the other groove or grooves in the insulation layer (of the sodium and/or channel stopper), e. with a tungsten material. The chipping stopper trench below the oxide peeling stopper groove can be filled like a field electrode trench in the active region, e. with a field dielectric and an electrode material (for instance oxide and polysilicon). In total, for instance at least two combined chipping and oxide peeling stoppers can be arranged in the edge termination region, possible upper limits being for instance not more than six or four combined chipping and oxide peeling stoppers. Laterally, the combined chipping and oxide peeling stopper(s) can be arranged between the sodium stopper and the die edge and/or between the channel stopper and the die edge.

The invention relates also to a method for manufacturing a semiconductor wafer and/or respective semiconductor die. Therein, the sodium stopper(s) is or are formed by etching the insulation layer groove(s) and filling them at least partly or completely with the tungsten material.

Regarding further manufacturing details, reference is made to the description above and/or to the exemplary embodiments.

In an embodiment, a chipping stopper trench discussed above is etched in the same process step as a needle trench in the active region and/or in the dicing region. Therein, the chipping stopper trench is etched as a longitudinal trench in the edge termination region, wherein needle trenches are etched in the active region and/or dicing region.

Below, the semiconductor die or wafer and the manufacturing of the same are explained in further detail by means of exemplary embodiments. Therein, the individual features can also be relevant for the invention in a different combination.

<FIG> shows a portion of a semiconductor die <NUM> in a vertical cross-section. The sectional plane lies at a corner of the die <NUM>, see <FIG> for illustration. The die <NUM> comprises a semiconductor body <NUM> with an active region <NUM> (see <FIG> and <FIG> in detail). On the semiconductor body <NUM>, an insulation layer <NUM> is formed, namely a BPSG layer in the embodiment here. The insulation layer <NUM> is interrupted by a sodium stopper <NUM> preventing a sodium diffusion in the insulation layer <NUM> into the active region <NUM>. The sodium stopper <NUM> is formed of a tungsten material <NUM>, which can allow for a compact design. On a frontside <NUM> of the insulation layer <NUM>, a metallization layer <NUM> is arranged, which is also made of tungsten material <NUM>. A passivation layer <NUM> is deposited directly onto the metallization layer <NUM>, made of imide in this example.

In the following, reference is also made to the enlarged view of <FIG>. The metallization layer <NUM> has a vertical thickness <NUM> of about <NUM>-<NUM>, which can enable a precise structuring. An insulation layer groove <NUM>, in which the tungsten material <NUM> of the sodium stopper <NUM> is arranged, intersects the insulation layer <NUM> vertically. It extends even further down into the semiconductor body <NUM>, forming a drain contact <NUM> there. To improve the electrical connection, it intersects a doped region <NUM>.

In the edge termination region <NUM>, in which the sodium stopper <NUM> is formed, further etch termination structures are provided. A channel stopper <NUM> in a channel stopper trench <NUM> can be electrically contacted via the metallization layer <NUM>. Applying an electrical potential to the channel stopper <NUM> can for instance prevent ions from entering into the active region <NUM>. Furthermore, chipping stoppers <NUM> are formed in the semiconductor body <NUM> in respective chipping stopper trenches <NUM>. The sodium stopper <NUM> is arranged laterally in between two chipping stoppers <NUM>. In this example, the chipping stopper trenches <NUM> are respectively filled with an electrically conductive material <NUM> contacted via the metallization layer <NUM>, the chipping stoppers <NUM> serving also as channel stoppers <NUM>. They are on the same electrical potential as the channel stopper <NUM>, the sodium stopper <NUM> and the drain contact <NUM>.

Laterally between the sodium stopper <NUM> and an edge <NUM> of the die <NUM>, further chipping stoppers <NUM> in chipping stopper trenches <NUM> are formed (four in total, two of them being shown in <FIG>). In contrast to the chipping stopper trenches <NUM>, the chipping stopper trenches <NUM> are not connected to the metallization layer <NUM>. Nevertheless, a respective vertical groove <NUM> is formed in the insulation layer <NUM> above each trench <NUM>, the grooves <NUM> acting as oxide peeling stoppers <NUM>. In this example, each groove <NUM>, <NUM> or interconnect <NUM> formed in the insulation layer <NUM> is filled with tungsten material <NUM>.

<FIG> shows a portion of a wafer <NUM> in a vertical cross-section, the cross sectional plane lying not at a die corner in contrast to <FIG> and <FIG> (see <FIG>). In addition to the active region <NUM> and the edge termination region <NUM>, a dicing region <NUM> is visible. The dicing region <NUM> is arranged in between active regions, which belong to separate dies after the separation process, e. laser dicing. A comparison between <FIG> and <FIG> illustrates, that the metallization layer <NUM> connecting and contacting the different edge termination structures is only formed at the corner of the die. However the sodium stopper <NUM> extends over the whole circumference around the active region <NUM>, the same applies for the channel/chipping and oxide peeling stoppers <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. As mentioned above, two further combined chipping and oxide peeling stoppers <NUM>, <NUM> are arranged between the die edge <NUM> or dicing region <NUM> and the active region <NUM>.

In the dicing region <NUM>, first trenches <NUM> and second trenches <NUM> are formed. The first trenches <NUM> extend deeper into the semiconductor body <NUM> than the second trenches <NUM>. In this example, the first trenches <NUM> have the same depth like the chipping stopper trenches <NUM>, <NUM>, and the second trenches <NUM> have the same depth as the channel stopper trench <NUM>. For orientation, a vertical direction <NUM> and a lateral direction <NUM> are shown.

<FIG> illustrates a portion of the wafer <NUM> in a top view showing a corner <NUM> of the die <NUM> and the dicing regions <NUM> formed there (the die <NUM> is not separated from the wafer <NUM> yet). The first trenches <NUM> are needle trenches <NUM>. They are arranged in a grid <NUM> formed by the second trenches <NUM> which are elongated trenches <NUM>. In this example, the elongated trenches <NUM> form quadratic cells <NUM>, wherein a needle trench <NUM> is arranged centrally in each cell <NUM>. Furthermore, the top view illustrates the lateral extension of the die edge termination structures discussed above, in the top and in the cross-sectional view the same reference numerals are used for the same structure respectively. For illustration, the sectional planes A-A of <FIG>/<FIG> and B-B of <FIG> are indicated.

<FIG> shows a vertical cross-section of a semiconductor transistor device <NUM> that can be formed in an active region <NUM>. It comprises a source region <NUM>, a body region <NUM>, and a drift region <NUM> formed vertically between the body region <NUM> and the drain region <NUM>. Further, it comprises a gate region <NUM> laterally aside the body region <NUM>. In the gate region <NUM>, a gate electrode <NUM> is arranged, separated from the body region <NUM> by an interlayer dielectric <NUM>. By applying a voltage to the gate electrode <NUM>, a channel formation in the body region <NUM> can be controlled.

The source and the body region <NUM>, <NUM> are electrically contacted by the same frontside metallization <NUM>. In this example, the source region <NUM>, the drift region <NUM> and the drain region <NUM> are n-type, wherein the body region <NUM> is p-type. The frontside metallization <NUM> contacts further a field electrode <NUM> separated from the body and the drift region <NUM>, <NUM> by a field dielectric <NUM>. The field electrode <NUM> and the field dielectric <NUM> form a field electrode region <NUM>. The field electrode region <NUM> is arranged in a field electrode trench <NUM>, and the gate region <NUM> is arranged in a gate trench <NUM>. In <FIG> the lateral arrangement of these trenches <NUM>, <NUM> is shown (in a portion of the active region <NUM>), the gate trenches <NUM> are longitudinal trenches <NUM> forming a grid <NUM> defining cells <NUM>, wherein in each cell <NUM> a field electrode trench <NUM> formed as a needle trench <NUM> is arranged.

Claim 1:
A semiconductor die (<NUM>), having
a semiconductor body (<NUM>) comprising an active region (<NUM>),
an insulation layer (<NUM>) formed on the semiconductor body (<NUM>),
a sodium stopper (<NUM>) formed in the insulation layer (<NUM>),
the sodium stopper (<NUM>) being arranged in an insulation layer groove (<NUM>), which intersects the insulation layer (<NUM>) vertically and extends around the active region (<NUM>), wherein a metallization layer (<NUM>) is formed on a frontside (<NUM>) of the insulation layer (<NUM>), the metallization layer (<NUM>) covering at least a section of the insulation layer groove (<NUM>),
characterized in that
the sodium stopper (<NUM>) is formed of a tungsten material (<NUM>) filling the insulation layer groove (<NUM>) and the metallization layer (<NUM>) is formed of a tungsten material (<NUM>).