Patent Description:
Brain-inspired neuromorphic spiking neural network (SNN) emulators form distributed, parallel, and event-driven systems offering capabilities such as adaptation, self-organization, and learning. These emulators implement several concepts, e.g. activity-dependent short-term and long-term plasticity, which are experimentally demonstrated.

Input information is encoded by patterns of activity occurring over populations of neurons, and the synapses (which each form a connection from one neuron to a subsequent neuron) can adapt their function depending on the pulses (e.g. in the form of a spatio-temporal spike train) they receive, providing signal transmission energy-efficiency, and flexibility to store and recall information.

The synapses perform a dual function, i.e. the synapses implement memory storage capabilities in addition to their functioning as complex nonlinear operators, which perform distributed computation. Due to the separation of processing elements and memory, traditional, von Neumann-based computing systems are not optimized for computational tasks involving large amounts of high-dimensional data, e.g. image processing, object recognition, probabilistic inference, or speech recognition; these computational tasks can be efficiently completed with powerful, and yet conceptually simple and highly parallel methods, such as SNNs, where memory and processing elements are co-localized. Neuromorphic systems are driven directly by the input data, i.e. synapses receive spikes and neurons generate spikes, respectively, at the rate of the incoming data. Consequently, only when the circuit is processing data, dynamic power consumption occurs. For applications where the spatial-temporal signal activity is sparse, most neurons are non-active at each particular moment, leading to a minimal power consumption.

Neuromorphic computational elements, i.e. neurons and synapses, display a wide range of spiking behaviours, typically represented as dynamical systems of various complexity, representing various trade-offs between the biophysical accuracy and computational capabilities. Several distinctive, hardware implementations of biologically-plausible, biologically-inspired and integrate-and-fire neuron models incorporate membrane dynamics (modelling charge leakage across the membrane); ion channel dynamics (governing ions flow); axonal models (with associated delay components); and dendritic models (modelling influence of the pre- and post-synaptic neurons).

Hardware implementations of the synaptic models, which are repurposed for the advancement and employment of new materials, mainly focus on optimizing the synapse implementation. More complex synapse models include a plasticity mechanism (e.g. both short-term and long-term potentiation and depression, see <NPL>), or for more biologically-inspired neuromorphic networks include the chemical interactions of synapses (see <NPL>). Synapses are also utilized as a homeostasis mechanisms for stabilization of the network activity (see <NPL>).

Modern deep learning architectures typically consist of multiple layers, where each layer consists of a vector matrix multiplication implemented by a synaptic matrix, the result of which is used as input for a specific non-linear activation function (e.g. sigmoid function, rectified linear unit (ReLU) activation function, or an activation function based on membrane potential dynamics) at a neuron. The activation function at the neuron is also called the neuron activation function. The neurosynaptic array adopts a hybrid analog-digital signal representation, i.e. the trains of pulses/spikes transmit analog information in the timing of the events, which are converted back into analog signals at the inputs of the synaptic matrix. Analog crossbar arrays inherently realize dot-product operations (which form an essential operation in dense vector matrix multiplication). In analog domain, by applying a vector of voltage signals to the rows of a synaptic crossbar, multiplication by each synapse (weight w) is performed by the Kirchhoff's Current Law (KCL) rule, and the current is summed across each column. i.e. the outputs of the synapses are usually in the current domain, since signal summing in the current domain is simply wiring all outputs together. This (post-) synaptic current denotes the multiplication result, while the signal summing as well as the non-linear functionality are provided by neuron dynamics represented by the neuron activation function.

In general, two distinctive approaches are utilized to derive a weighted input, as exemplified by <FIG> respectively.

<FIG> discloses a known first approach where all synapses have two symmetric output currents, which are first separately summed. Consequently, the difference of the two sums is then the weighted input. <FIG> indeed shows an example of a portion of a prior art spiking neural network <NUM>, including synaptic input signals <NUM>, m synaptic elements <NUM>, current mirror <NUM>, synaptic output currents <NUM>, weighted synaptic output <NUM>, an output neuron <NUM> and a neuron output signal <NUM>. The synaptic elements <NUM> are configured to receive synaptic input signals <NUM>, the synaptic input signals being spatio-temporal spike trains. The synaptic elements <NUM> convert an input spike in the synaptic input signal <NUM> to a current, in order to then each apply a weight w<NUM>, w<NUM>,. , wm<NUM> (here the first index indicates the row of the synaptic matrix, while the second index indicates the column of the synapse matrix) to generate two synaptic symmetric output currents <NUM>. The difference of these currents is calculated by the current mirror <NUM> to generate a final weighted synaptic output <NUM>. The output neuron <NUM> then generates a neuron output signal <NUM> based on the weighted synaptic output <NUM>. It should be noted that each of the synaptic elements <NUM> is configured to perform both the integration of the synaptic input signals <NUM> to generate a current, and the subsequent application of a weight to this current to generate synaptic output currents <NUM>.

<FIG> discloses a known second approach, where all synapses have one bipolar (positive/negative, excitatory/inhibitory) output current, and the weighted input is then the sum of these bipolar output currents. <FIG> indeed shows another example of a portion of a prior art spiking neural network <NUM>, including synaptic input signals <NUM>, synaptic elements <NUM>, synaptic output currents <NUM>, an output neuron <NUM> and a neuron output signal <NUM>. Like in the previous example, the synaptic elements <NUM> perform the functions of both integration of synaptic input signals and subsequent weight application with weight w<NUM>, w<NUM>,. However, in this method the synaptic elements <NUM> are configured to generate a positive or negative output current <NUM>, corresponding to an excitatory or inhibitory signal, such that no subtraction of signals is necessary to generate a correct weighted output.

Since each synapse usually includes a current mirror, each synapse requires a larger chip area. However, the wiring in this example is simplified as all building blocks are identical, i.e. the current mirror(s) do not need to be re-designed when implementing a neuron with a higher or lower dimensional input vector, i.e. when the number of synaptic elements m is changed.

<FIG> discloses a known neurosynaptic array consisting of a neural network matrix that connects m × n programmable synapses to n neurons. Neurosynaptic computational elements are able to generate complex spatio-temporal dynamics, extendable towards specific features of the target signal processing function. The neuron spiking properties are controlled through specific parameter sets. Indeed, <FIG> shows a prior art neurosynaptic array <NUM> forming part of a spiking neural network, comprising a neural network matrix <NUM> connecting multiple groups of programmable synaptic elements <NUM> to an array <NUM> of n output neurons <NUM> comprising neurons N<NUM>, N<NUM>,. , Nn, wherein the synaptic elements <NUM> receive synaptic input signals <NUM> to generate synaptic output currents <NUM>, and wherein the output neurons <NUM> are configured to generate neuron output signals <NUM>. While each of the neurons <NUM> is connected to a different column of synaptic elements <NUM>, the synaptic input signal <NUM> received by each row of synaptic elements <NUM> is the same, though different weight values wi<NUM>, wi<NUM>,. , win may be applied by different synaptic elements <NUM> in the same row with row index i. Finally, the neurons are configurable by one or more neuron control signals <NUM>. These neuron control signals <NUM> can control the neuron dynamics represented by the neuron activation function, for example by changing a parameter of the neuron activation function. Again, each of the synaptic elements <NUM> are configured to perform both the integration of synaptic input signal and subsequent weight application functions.

In a fully connected network, synaptic integration capacitance is the largest contributor to the total area of the array. Capacitors take up a lot of space and consume relatively big amounts of energy. In prior art hardware implementations of spiking neural networks, capacitors are required for synaptic integration in the synaptic elements. Consequently, a prior art spiking neural network comprising many layers of synapses and neurons is not optimized with respect to area and energy use. Accordingly, a need exists in the industry for a more efficient spiking neural network.

The document <NPL>, discloses the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. The choices made in this document were: <NUM>) emulate all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; <NUM>) realize all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and <NUM>) interconnect neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time using <NUM> Neurocores integrated on a board that consumes three watts.

In this patent application, to enable area- and power-efficient design, we report a novel distributed multi-component synaptic structure, where each of the distributed components implements distinctive computational characteristics and can be optimized towards specifics of the predefined signal processing function.

Embodiments will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:.

Hereinafter, certain embodiments will be described in further detail. It should be appreciated, however, that these embodiments may not be construed as limiting the scope of protection for the present disclosure.

As mentioned above, in a fully connected network with m × n synapses, the capacitors used for synaptic integration is the largest contributor to the total area of the array. For area-optimized design (and subsequently energy-efficient design), instead of using one circuit to reproduce synaptic dynamics (as in <FIG>), the current invention reproduces synaptic dynamics with two dedicated circuits (<FIG>), each implementing a well-defined function, the first circuit performing pulse (spike) integration, and the second circuit performing weight application. Consequently, only a single spike integrator (and thus a single capacitor, instead of n capacitors) for every input signal is required. This thus results in an area-efficient design, where the pre-integration is shared per row of weight application elements <NUM>. Furthermore, since only a single pre-integration instead of n pre-integrations now need to be performed, the invention provides for a more power-efficient implementation of the synaptic matrix.

<FIG> shows a part of a spiking neural network <NUM> according to an exemplary embodiment, which may form a sub-network (or ensemble) within a larger neural network comprising a plurality of sub-networks, and may be implemented as a neuro-synaptic core. <FIG> shows output neurons <NUM>, which are connected to weight application elements <NUM>, which are connected to presynaptic integrators <NUM>. Exemplary embodiments include at least one presynaptic integrator <NUM>, a plurality <NUM> of weight application elements <NUM> and a plurality <NUM> of output neurons <NUM>. In some embodiments, the spiking neural network <NUM> comprises several layers, such that the spatio-temporal spike train output signal <NUM> generated by the output neurons <NUM> may form the presynaptic signal <NUM> received by a presynaptic integrator <NUM> in a next layer, and such that the presynaptic pulse signal <NUM> received by a presynaptic integrator <NUM> may be generated by an input neuron, i.e. an output neuron <NUM> from a previous layer. In order to not clutter the image, only a small number of neurons <NUM>, presynaptic integrators <NUM> and weight application elements <NUM> are shown, and only some have a reference numeral attached to them.

Synaptic dynamics are replicated by the presynaptic integrator <NUM> and the weight application elements <NUM>. The presynaptic integrator <NUM>, performs the function of presynaptic pulse (spike) integration, such that a presynaptic (fast) pulse signal <NUM> is translated into a (long-lasting) synaptic input signal <NUM>. In some embodiments, the synaptic input signal <NUM> may be an exponentially decreasing spike, similar to a signal emitted by an AMPA-receptor. In some embodiments, the synaptic input signal <NUM> may be a synaptic input current. In some embodiments, the synaptic input signal <NUM> may be a synaptic input voltage. In some embodiments, the presynaptic integrator <NUM> is configurable by a control signal <NUM>, preferably wherein the control signal <NUM> controls the temporal shape of the synaptic input signals <NUM> generated by the presynaptic integrator <NUM>.

Each weight application element <NUM> performs the typical synaptic function, connecting input and output neurons and applying a weight value, stored in a corresponding weight storage element <NUM>, to the synaptic input signal <NUM> to generate a synaptic output current <NUM>. In particular, the applied weight value determines the strength of the synaptic output current <NUM>. In some embodiments, the weight application element applies a factor ranging from zero to one to attenuate its synaptic input signal to generate a synaptic output current comprising a selected portion of the synaptic input signal. In some embodiments, the weight value stored by a weight storage element <NUM> is adjustable, preferably according to a learning rule.

The output neurons <NUM> are configured to receive at least one synaptic output current <NUM> from a weight application element <NUM> to generate a spatio-temporal spike train output signal based on the received one or more synaptic output currents. In some embodiments, the output neurons <NUM> are configurable by a neuron control signal <NUM>. These neuron control signals <NUM> can e.g. control the neuron dynamics represented by the neuron activation function, for example by changing a parameter of the neuron activation function.

In an alternative embodiment, the spiking neural network further comprises a row spike decoder <NUM>, configured to decode and allocate the presynaptic pulse signals <NUM> to the corresponding presynaptic integrators <NUM>, based on a presynaptic input spike <NUM>. Which presynaptic pulse signals to send to which presynaptic integrator <NUM> depends of the configuration of the spiking neural network. Decoding the presynaptic input spike <NUM> encompasses.

<FIG> shows a another example of a part of a spiking neural network <NUM> according to another exemplary embodiment, which may form a sub-network (or ensemble) within a larger neural network comprising a plurality of sub-networks, and may be implemented as a neuro-synaptic core. The output neurons <NUM> are connected to weight application elements <NUM>, which are connected to presynaptic integrators <NUM>. Exemplary embodiments include at least one presynaptic integrator <NUM>, a plurality <NUM> of weight application elements <NUM> and a plurality <NUM> of output neurons <NUM>. In some embodiments, the spiking neural network <NUM> comprises several layers, such that the spatio-temporal spike train output signal <NUM> generated by the output neurons <NUM> may form the presynaptic signal <NUM> received by a presynaptic integrator <NUM> in a next layer, and such that the presynaptic pulse signal <NUM> received by a presynaptic integrator <NUM> may be generated by an input neuron, i.e. an output neuron <NUM> from a previous layer. In order to not clutter the image, only a small number of neurons <NUM>, presynaptic integrators <NUM> and weight application elements <NUM> are shown, and only some have a reference numeral attached to them.

This embodiment further comprises a neurosynaptic core control element <NUM>, a neuron control element <NUM>, a neuron decoder element <NUM> and a row spike decoder <NUM> analogous to the row spike decoder <NUM> from <FIG>, such that a the row spike decoder <NUM> decodes and allocates presynaptic pulse signals <NUM> to presynaptic integrators <NUM> based on a presynaptic input spike <NUM>.

A plurality of neurosynaptic cores arranged in an array of cores arranges a high-level architecture for learning systems. Each core comprises a network of neurons implemented in hardware, the neurons interconnected by synaptic elements. A single core may implement a complete spiking neural network, or a portion of a spiking neural network forming a separate sub-network. In this way, a large spiking neural network can be partitioned into a number of smaller sub-networks, each sub-network being implemented in one of the cores of the array. In one embodiment, the cores may implement a spiking neural network with associated input data ports, output ports, and/or control and configuration interface, for example each core implementing one or more sub-networks including the arrangement of <FIG> or <FIG>.

By partitioning large spiking neural networks into smaller sub-networks and implementing each of the sub-networks on one or more cores, each with their own requisite circuitry, some of the non-idealities of circuits operating at smaller process geometries, and lower operating currents are mitigated, especially for large arrays. The core-based implementation approach thus reduces the impact of physical non-idealities.

A sub-network, or ensemble of neurons that form a co-operative group can for example form a classifier, an ensemble of classifiers, groups of neurons that handle data conversion, feature encoding or solely the classification, et cetera.

In such a regime, a large network of ensembles is partitioned and mapped onto an array of cores, each of which contains a programmable network of spiking neurons. Each core consequently implements a single ensemble, multiple small ensembles (in relation to the number of neurons and synapses in the core), or in the case of large ensembles, only a part of a single ensemble, with other parts implemented on other cores of the array. The modalities of how ensembles are partitioned and mapped to cores is determined by a mapping methodology. The mapping methodology can comprise a constraint-driven partitioning. The constraint can be a performance metric linked to the function of each respective sub-network. The performance metric could be dependent on power-area limitations, memory structures, memory access, time constants, biasing, technology restrictions, resilience, a level of accepted mismatch, and network or physical artifacts.

The neurosynaptic core control element <NUM> is configured to receive a spike input <NUM>, possibly from a previous layer of input neurons, to send the presynaptic input spike <NUM> to the row spike decoder <NUM>, and to send the control signals <NUM> to the presynaptic integrators <NUM>. Further, the neurosynaptic core control element <NUM> is configured to receive and subsequently transmit a neuron spike output signal <NUM> from the neuron decoder element <NUM>. Additionally, the neurosynaptic core control element <NUM> is configured to control both the neuron control element <NUM> and the neuron decoder element <NUM>. Finally, the neurosynaptic core control element is configurable by a configuration signal <NUM>.

The neuron control element <NUM> is configured to control the plurality <NUM> of output neurons <NUM> through a neuron control signal <NUM>. The neuron decoder element <NUM> is configured to generate a neuron spike output signal <NUM> based on at least one spatio-temporal spike train output signal <NUM>, generated by an output neuron <NUM> based on a synaptic output current <NUM>.

The neuro-synaptic core disclosed in the present invention can thus be organized as repeating arrays of synaptic circuits and neuron units, where each unit can form a cell assembly. The system can incorporate the presence of electronic synapses at the junctions of the array. The periphery of the array can include rows of the synaptic circuits which mimic the action of the soma and axon hillock of biological neurons.

Further, each neuro-synaptic core in the array can have a local router, which communicates to the routers of other cores within a dedicated real-time reconfigurable network-on-chip. A classifier can e.g. be assumed to have a set of output neurons (one for each class) each of which fires an event (spike) according to its firing probability distribution.

Next, presynaptic integration circuits according to the invention will be described.

<FIG> shows a presynaptic integration circuit <NUM> according to an exemplary embodiment not falling under the scope of the appended claims of a presynaptic integrator <NUM>, <NUM>, comprising a positive voltage supply <NUM> (also called a drain with voltage VDD), a negative voltage supply <NUM> (also called a source with voltage VSS), a capacitor <NUM>, several field effect transistors (FETs), in particular an input FET <NUM>, a leakage FET <NUM>, an output FET <NUM>, and a current mirror <NUM>. The presynaptic integrator <NUM>, <NUM> operates in the sub-threshold region and offers a low area and linear filtering properties. The presynaptic integrator <NUM>, <NUM> translates fast presynaptic pulse signals <NUM>, <NUM> into (long-lasting) synaptic input signals <NUM>, <NUM>. The synaptic input signals may, for example, be shaped like an exponentially decreasing spike (while preserving AMPA-like receptor temporal dynamics). The presynaptic integrator <NUM>, <NUM> offers the possibility of multiplexing time spikes originating from different neurons, and provides tunable gain independent from the (tunable) time constant.

In this embodiment, the presynaptic pulse signal <NUM>, <NUM> from the row spike decoder <NUM>, <NUM> forms the gate-source voltage over the input FET <NUM>. When the gate-source voltage is positive, corresponding to a spike in the presynaptic pulse signal, the input FET <NUM> turns on, enabling a drain-source current to flow.

Some embodiments may further include a control FET <NUM>, configured to control the temporal dynamic of the synaptic input signal <NUM>, <NUM> based on a control signal which is the gate-source voltage over the control FET <NUM>. In this embodiment, the control signal is the control signal <NUM>, <NUM> from the row spike decoder <NUM> or neurosynaptic core control element <NUM>. When the gate-source voltage is e.g. positive, the control FET <NUM> turns on, enabling a drain-source current to flow.

The capacitor <NUM> is connected to input FET <NUM> and possibly to control FET <NUM> such that when both input FET <NUM> and control FET <NUM> are turned on, a closed circuit is formed, connecting the positive voltage supply <NUM> to the negative voltage supply <NUM> through the capacitor <NUM>, such that the capacitor <NUM> accumulates charge until the connection ends.

If the capacitor <NUM> has accumulated charge, the output FET <NUM> turns on, as its gate-source voltage is equal to the charge accumulated by the capacitor <NUM>. When the output FET <NUM> is turned on, a drain-source current flow is enabled from the positive voltage supply <NUM> to the negative voltage supply <NUM>, through the output FET <NUM> and the current mirror <NUM>. The output FET <NUM> may be configured to operate in its sub-threshold region, such that if the charge on capacitor <NUM> is decreasing linearly, the drain-source current over the output FET <NUM> decreases exponentially. In some embodiments, the output FET <NUM> operates in its sub-threshold region, and, hence, offers an exponential relationship between its gate-source voltage and its source-drain current. Consequently, a linear decrease in the charge on the capacitor <NUM> is converted to an exponential decay in the drain-source current.

The leakage FET <NUM> is configured to discharge the capacitor <NUM> if it is turned on. Due to the constant current through leakage FET <NUM>, the charge accumulated by the capacitor <NUM> decreases linearly In some embodiments, the leakage FET <NUM> is controlled by a time constant, the time constant determining the gate-source voltage of the leakage FET <NUM>. The time constant may be chosen such that e.g. AMPA, NDMA, GABAA or GABAB temporal dynamics are realised.

If a current flows through the current mirror <NUM>, a voltage signal is generated proportional to the strength of said current. In this embodiment, the synaptic input signal <NUM>, <NUM> generated by the presynaptic integrator <NUM>, <NUM> is this voltage signal. In effect, the current flowing through current mirror <NUM> is replicated as a voltage signal. Alternatively, or in addition, the current mirror <NUM> may be a cascode current mirror such that the synaptic input signal <NUM>, <NUM> comprises two voltage signals, for reduced variation and increased accuracy of current replication. Namely, the cascode implementation improves the output drive strength, by improving impedance.

<FIG> shows a presynaptic integration circuit <NUM> according to another exemplary embodiment not falling under the scope of the appended claims of a presynaptic integrator <NUM>, <NUM>, comprising a positive voltage supply <NUM>, a negative voltage supply <NUM>, a capacitor <NUM>, several field effect transistors (FETs), in particular input FETs <NUM>, a control FET <NUM> a leakage FET <NUM>, an output FET <NUM>, a mirror FET <NUM> and a cascode current mirror <NUM>. To make the amount of charge accumulated by the capacitor independent of the capacitance value of capacitor <NUM> (which can vary up to <NUM>% due to manufacturing variability), the circuit in <FIG> is employed. Hence, the circuit no longer depends on the duration a spike in the presynaptic pulse signal <NUM>, <NUM>, as long as it is long enough to stabilize the charge on capacitor <NUM>. This embodiment further includes an output control element, comprising an output control FET <NUM>, a current control FET <NUM> and an inverter <NUM>.

In this embodiment, the presynaptic pulse signal <NUM>, <NUM> is the gate-source voltage over the input FETs <NUM>. If the gate-source voltage over input FETs <NUM> goes high when an input pulse is applied, a current starts to flow, through control FET <NUM>, charging capacitor <NUM> to the diode voltage of mirror FET <NUM>. It is important to note that gate-source voltage pulse on input FETS <NUM> needs to be long enough in order for the amount of charge accumulated by the capacitor <NUM> to reach a constant value.

The control FET <NUM> is configured to control the temporal dynamic of the synaptic input signal <NUM>, <NUM> based on the control signal <NUM>, <NUM>. In this embodiment, the control signal <NUM>, <NUM> is the gate-source voltage over the control FET <NUM>. When the gate-source voltage is positive, the control FET <NUM> turns on, enabling a drain-source current to flow. In this embodiment, the control signal <NUM>, <NUM> is configured to regulate the accumulation of charge by the capacitor, such that the amount of charge accumulated by the capacitor is independent of a duration of a spike in the spatio-temporal spike train and the capacitance value of the capacitor, and to regulate the temporal shape and maximum amplitude of the synaptic input signal by controlling the maximum charge on the capacitor. In some embodiments, control FET <NUM> is a constant current source.

The capacitor <NUM> is connected to input FETs <NUM> and control FET <NUM> such that when both input FETs <NUM> and control FET <NUM> are turned on, a closed circuit is formed, connecting the positive voltage supply <NUM> to the negative voltage supply <NUM> through the capacitor <NUM>, such that the capacitor <NUM> accumulates charge until the connection ends.

If the capacitor <NUM> has accumulated charge, the output FET <NUM> turns on, as its gate-source voltage is equal to the charge accumulated by the capacitor <NUM>. When the presynaptic pulse signal <NUM>, <NUM> goes low, the output is enabled; as leakage FET <NUM> discharges capacitor <NUM> over time, the drain-source current over output FET <NUM> will decrease accordingly When both the output FET <NUM> and the output control FET <NUM> are turned on, a drain-source current flow is enabled from the positive voltage supply <NUM> to the negative voltage supply <NUM>, through the output FET <NUM>, the output control FET <NUM> and the cascode current mirror <NUM>. The output FET <NUM> may be configured to operate in its sub-threshold region, such that if the charge on capacitor <NUM> is decreasing linearly, the drain-source current over the output FET <NUM> decreases exponentially.

The output stage can employ a cascode current mirror <NUM> for reduced variation and increased accuracy of the current replication. If a current flows through the cascode current mirror <NUM>, two voltage signals are generated proportional to the strength of said current. In this embodiment, the synaptic input signal <NUM>, <NUM> generated by the presynaptic integrator <NUM>, <NUM> thus comprises two voltage signals. In effect, the current flowing through cascode current mirror <NUM> is replicated as two voltage signals. Alternatively, the cascode current mirror <NUM> may be a regular current mirror producing one voltage signal instead as was seen in the embodiment of <FIG>, not falling under the scope of the appended claims.

The output control element comprising the inverter <NUM>, the output control FET <NUM> and current control FET <NUM>, is configured to regulate the flow of an output current. Arrow <NUM> denotes the direction of the output current over the drain-source of output FET <NUM>. However, this current only flows if both the output FET <NUM> and output control FET <NUM> are turned on. The inverter <NUM> is connected to an input FET <NUM>, such that a positive voltage is generated at its output if the presynaptic input signal <NUM>, <NUM> is negative, and a negative voltage is generated at the output of inverter <NUM> if the presynaptic input signal <NUM>, <NUM> is positive. As a consequence, the output control FET <NUM> only turns on if the presynaptic input signal is negative, that is, when the presynaptic input signal is not spiking. Output current flow over FETs <NUM> and <NUM> is thus only possible after a spike in the spatio-temporal spike train has ended. Additionally, the current control FET <NUM> is only turned on when the presynaptic pulse signal <NUM>, <NUM> is spiking. As a consequence, discharging of the capacitor <NUM> by the drain-source current over either of FETs <NUM> and <NUM> is not possible after a spike has ended, making sure that the discharging of capacitor <NUM> is controlled by the leakage FET <NUM>.

The leakage FET <NUM> is configured to discharge the capacitor <NUM> through its drain-source current (current direction indicated by arrow <NUM>), if it is turned on. When the presynaptic pulse signal <NUM>, <NUM> goes low and the charge circuit is closed, capacitor <NUM> discharges with a constant current through leakage FET <NUM>. In some embodiments, the leakage FET <NUM> is controlled by a time constant, the time constant determining the gate-source voltage of the leakage FET <NUM>. The time constant may be chosen such that AMPA, NDMA, GABAA or GABAB temporal dynamics are realised.

The mirror FET <NUM> is coupled to the output FET <NUM>, such that the mirror FET <NUM> and output FET <NUM> together form a current mirror, ensuring that the drain-source current over the output FET <NUM> is identical to the drain-source current over the mirror FET <NUM>. Therefore the voltage induced by the capacitor within the pre-integration circuit does not matter anymore for the functioning of the pre-integration circuit.

Next, weight application circuits according to the invention will be described.

The weight application (multiplication) circuit of <FIG> and <FIG> is fully distributed and performs the typical synaptic function, connecting the input and output neurons and applying a stored weight. The linearity of the multiplier should be preserved in order to not-degrade learning. The digitally stored weights are transformed to an analog domain through a current-steering D/A converter based on an R-2R architecture, which is shown in <FIG> and <FIG>. The weight application element may apply a factor ranging from zero to one on its input current, attenuating it, and sending the selected portion of the input current to its output.

To minimize sensitivity for weight-errors, it is advantageous to have a small transconductance. Since the design is based on a current-steering D/A conversion, the outputs of multiple weight application elements can be summed straightforwardly.

<FIG> shows a weight application circuit <NUM> according to an exemplary embodiment not falling under the scope of the appended claims of a weight application element <NUM>, <NUM>. In order to not clutter the image, only some elements have a reference numeral attached to them, and repeated elements are only shown a limited number of times. The weight application circuit <NUM> comprises a positive voltage supply <NUM>, a negative voltage supply <NUM>, a first synaptic input receiver <NUM>, a second synaptic input receiver <NUM>, an output terminal <NUM>, and a ladder of output selection elements <NUM>, each comprising dual resistance FETs <NUM>, a single resistance FET <NUM>, a positive output FET <NUM> and a negative output FET <NUM>. FET <NUM> and FET <NUM> can also be connected to the positive voltage supply <NUM>.

The synaptic input receivers <NUM> and <NUM> are configured to receive a synaptic input signal <NUM>, <NUM> in the form of a gate-source voltage. With reference to <FIG> not falling under the scope of the appended claims, the synaptic input signal <NUM>, <NUM> may be provided by output current mirror <NUM>. The gate-source voltages over synaptic input receivers <NUM>, <NUM> enable current flow through the rest of the weight application circuit <NUM>, particularly along the ladder of output selection elements <NUM> to the output terminal <NUM>.

The output selection elements <NUM> are connected sequentially, such that the current flowing through synaptic input receiver <NUM> is distributed among the output selection elements <NUM>. Each of the output selection elements <NUM> comprises a single resistance transistor <NUM> and dual resistance transistors <NUM>, which are positioned such that the current from the synaptic input receiver <NUM> is divided by two for each output selection element <NUM> it passes. Thus, the first output selection element <NUM> receives half of the synaptic input current, the second output selection element <NUM> receives a fourth, the third output selection element <NUM> receives an eighth, and so on. The more output selection elements <NUM> are included, the more accuracy is attainable in weight application.

Each of the output selection elements <NUM> comprises a positive output FET <NUM> and a negative output FET <NUM>. The gate-source voltages over these FETs are determined by the digitally stored weight values, stored in the weight storage elements <NUM>. The weight values are stored as bits, with the amount of bits equal to the amount of output control elements <NUM>. Each bit of the stored weight value determines the setting of an output control element, such that either the positive output FET <NUM> or the negative output FET <NUM> is turned on. If the positive output FET <NUM> is turned on, the portion of the synaptic input current that is allocated to the corresponding output selection element is connected to the output terminal <NUM>. If the negative output FET <NUM> is turned on, the selected portion of the synaptic input current does not contribute to the synaptic output current. As such, a weight application based on a stored binary weight value is realized.

<FIG> shows a weight application circuit <NUM> according to another exemplary embodiment not falling under the scope of the appended claims of a weight application element <NUM>, <NUM>. In this circuit, the synaptic input receivers <NUM>, <NUM> each comprise two field effect transistors, configured to receive the synaptic input signal <NUM>, <NUM> in the form of two gate-source voltages. With reference to <FIG> not falling under the scope of the appended claims, the synaptic input signal <NUM>, <NUM> may be provided by output cascode current mirror <NUM>.

Next, a polarity selection circuit according to the invention will be described.

<FIG> shows a polarity selection circuit <NUM> according to an exemplary embodiment not falling under the scope of the appended claims, comprising a polarity selection The polarity of the output of a weight application element <NUM>, <NUM> may be configurated to generate inhibitory spikes, corresponding to the behaviour of GABA receptors. The polarity selection circuit <NUM> employs a sourcing current mirror <NUM> sourcing current and a sinking current mirror <NUM> sinking current. The polarity selection circuit further comprises a positive voltage supply <NUM>, a negative voltage supply <NUM>, a polarity output element <NUM>, a first passage FET <NUM>, a second passage FET <NUM>, a sourcing selection FET <NUM>, a sinking selection FET <NUM>, and a polarity input element <NUM> configured to receive the synaptic output current <NUM>, <NUM>. The direction of the synaptic output current <NUM>, <NUM> is indicated by arrow <NUM>. Depending on whether the voltage applied to the polarity selection terminal <NUM> is set high or low, the sourcing current mirror or sinking current mirror is enabled, corresponding to an excitatory or inhibitory synapse, respectively.

The polarity input element <NUM> is configured to receive the synaptic output current as a drain-source current, and to translate this current to a gate-source voltage. This gate-source voltage is applied to the gate terminal of either the sourcing current mirror <NUM> or the sourcing current mirror <NUM>.

The passage FETs <NUM> and <NUM> are configured to pass the signal received by the polarity input element <NUM> to the sinking current mirror, if applicable. If a voltage is applied to the gate of the first passage FET <NUM>, a drain-source current starts to flow. This drain source current determines the drain-source current flowing through the second passage FET <NUM>, which determines the gate-source voltage of the second passage FET <NUM>. This gate-source voltage applied to passage FET <NUM> may then be applied to the sinking current mirror <NUM>, if the sinking selection FET <NUM> is turned on. The gate-source voltage over the second passage FET <NUM> will be identical to the gate-source voltage generated by polarity input element <NUM>.

If either a high or a low voltage is applied to polarity selection terminal <NUM>, either the sourcing selection FET <NUM> is turned on, or the sinking selection FET <NUM> is turned on.

If the sourcing selection FET <NUM> is turned on, a drain-source current over the sourcing selection FET <NUM> is enabled. As a consequence, the gate-source voltage over the polarity input element <NUM> is also applied to sourcing current mirror <NUM>, turning the sourcing current mirror <NUM> on. If the sourcing current mirror <NUM> is turned on, a current starts to flow from the positive voltage supply <NUM> to the polarity output element <NUM>, which is identical to the synaptic output current received by the polarity input element <NUM>.

If the sinking selection FET <NUM> is turned on, a drain-source current over the sinking selection FET <NUM> is enabled. As a consequence, the gate-source voltage over the polarity input element <NUM> is also applied to sinking current mirror <NUM>, turning the sinking current mirror <NUM> on. If the sinking current mirror <NUM> is turned on, a current starts to flow from the polarity output element <NUM> to the negative voltage supply <NUM>. Thus, a current equal to the inverted synaptic input current received by the polarity input element <NUM> flows through the polarity output element <NUM>.

Through the use of a polarity selection circuit, the spiking neural network can be implemented, without loss of generality, as a conductance-based integrate and fire model, which is one possible implementation of a generalized integrate and fire model.

Next, possible signal patterns achievable by the invention will be described.

A spiking neural network according to the present invention can display a wide range of pattern activity, for example full synchrony, cluster or asynchronous states, depending on the excitatory/inhibitory network interaction conditions, heterogeneities in the input patterns, and the spatio-temporal dynamics implemented in the presynaptic integrators.

<FIG> shows a graph <NUM> plotting excitatory synaptic output current (or excitatory postsynaptic current, i.e. synaptic EPSC current) <NUM> in Amperes as a function of time <NUM> in seconds, wherein the excitatory synaptic output current <NUM> is one exemplary embodiment of a synaptic output current <NUM>, <NUM>.

<FIG> show graphs <NUM>, <NUM> plotting voltage of a spatio-temporal spike train <NUM>, <NUM> in Volts as a function of time <NUM>, <NUM> in seconds wherein the spatio-temporal spike train is an exemplary embodiment of a spatio-temporal spike train <NUM>, <NUM>. In particular, <FIG> shows that accumulating charge on the membrane of a neuron (node) leads to spike generation. In <FIG>, non-linear spiking behaviour and frequency adaptability is shown.

The current invention is implemented on an integrated circuit, and can be in particular on a microcontroller integrated circuit. For example, the cores in the core array can form a network-on-chip on the microcontroller integrated circuit. The network-on-chip improves the scalability and the power efficiency of the microcontroller integrated circuit. The network-on-chip can be real-time reconfigurable, or statically defined during the production phase. When the network-on-chip is real-time reconfigurable, the settings of the cores in the core array and their interconnect structure settings can be altered. This alteration can be done based for example on changing input or output of the microcontroller integrated circuit, different demands on accuracy or stability of the classification, the evolution of the network based on its learning rules and a change in communication protocols.

The current invention provides implementation of distributed multi-component hardware structure that enables optimal area and power design of synaptic processing functions. It can realize increase in synaptic structure dimensionality by allowing per-component optimization of individual signal processing characteristics and functions within the spiking neural network.

The current invention provides implementation of an area- and power-efficient presynaptic adaptation mechanism that is robust against array inhomogeneities, where only a single spike integrator (instead of n) for every input neuron is required.

The current invention provides implementation of presynaptic adaptation (presynaptic integration and current generation) mechanism that minimize effects of synaptic capacitance variation. Furthermore, it provides implementation of an efficient mechanism for transformation of a digitally stored weights to an analog domain by applying a factor ranging on its input current, and sending the selected portion of the input current to its output.

Claim 1:
An integrated circuit implementing a spiking neural network (<NUM>) comprising a plurality of presynaptic integrators (<NUM>), a plurality of weight application elements (<NUM>), and a plurality of output neurons (<NUM>);
wherein each of the plurality of presynaptic integrators (<NUM>) is adapted to receive a presynaptic pulse signal (<NUM>) which incites accumulation of charge within the presynaptic integrator in a capacitor configured to accumulate the charge in response to the presynaptic pulse signal, and generate a synaptic input signal (<NUM>) based on the accumulated charge such that the synaptic input signal has a pre-determined temporal dynamic;
wherein a first group of weight application elements (<NUM>) of the plurality of weight application elements (<NUM>) is connected to receive the synaptic input signal (<NUM>) from a first one of the plurality of presynaptic integrators (<NUM>);
wherein each weight application element (<NUM>) of the first group of weight application elements is adapted to apply a weight value to the synaptic input signal (<NUM>) to generate a synaptic output current (<NUM>), wherein the strength of the synaptic output current is a function of the applied weight value; and
wherein each of the plurality of output neurons (<NUM>) is connected to receive a synaptic output current (<NUM>) from a second group of weight application elements of the plurality of weight application elements, and generate a spatio-temporal spike train output signal (<NUM>) based on the received one or more synaptic output currents such that each of the plurality of output neurons (<NUM>) has its own set of weight application elements from which it receives synaptic output currents, this set of weight application elements forming a second group of weight application elements, and each of these weight application elements of this own set of weight application elements receive the synaptic input signal (<NUM>) from a different one of the plurality of presynaptic integrators and thus each of these weight application elements of this own set of weight application elements are respectively comprised in a different first group of weight application elements.