Patent Description:
Embodiments generally relate to erasing memory structures.

NAND-type flash memory ("NAND memory") may be erased in blocks of memory. Developments in NAND lithography may have resulted in larger erase blocks that may be managed internally by the NAND memory in sub-blocks (e.g., <NUM>/<NUM> of a block). Under conventional solutions, however, a sub-block erase failure may cause the entire block to be treated as defective even though the NAND memory may be able to contain the failure to the sub-block in question. Accordingly, user exposable memory capacity may be wasted unnecessarily. Additionally, redundancy overhead (e.g., to protect against failure) may be relatively high due to the large size of the erase blocks. <CIT> discloses a sub-block erase verification scheme for NAND Flash memories.

To retain write bandwidth in NAND-type flash memory ("NAND memory") semiconductor dies, the page size and erase block sizes may be increased. After each erase operation, the successful completion of the erase operation is verified by reading all targeted bits and ensuring that they are set to one. Upon failure of verification, an erase failure may be reported to indicate that the erase block is defective. With denser geometries, each erase block may be divided into a smaller number of sub-blocks (e.g., <NUM>) and erase failures may be detected at the sub-block granularity. As will be discussed in greater detail, upon encountering erase failures, a non-volatile memory controller may detect the sub-block(s) that failed and mark the sub-block(s) as defective to prevent the storage of data to the failed sub-block(s).

Turning now to <FIG>, an array organization <NUM> for a non-volatile memory (NVM) such as, for example, NAND memory is shown. The illustrated array organization <NUM> may be used for a NAND flash memory, three-dimensional (3D) NAND memory array devices, or other memory devices. Non-volatile memory is a storage medium that does not require power to maintain the state of data stored by the medium. Non-limiting examples of nonvolatile memory may include any or a combination of: solid state memory (such as planar or 3D NAND flash memory or NOR flash memory), 3D crosspoint memory, storage devices that use chalcogenide phase change material (e.g., chalcogenide glass), byte addressable nonvolatile memory devices, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM) ovonic memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), other various types of non-volatile random access memories (RAMs), and magnetic storage memory. In some embodiments, 3D crosspoint memory may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of words lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In particular embodiments, a memory module with non-volatile memory may comply with one or more standards promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-<NUM>, JESD223B, JESD223-<NUM>, or other suitable standard (the JEDEC standards cited herein are available at jedec.

The array may be generally organized into a cache register <NUM>, a data register <NUM> and a logical unit node (LUN) <NUM>. The illustrated LUN <NUM> includes a certain number of blocks <NUM> (e.g., <NUM>,<NUM> blocks). The array may be further partitioned into multiple planes (e.g., "Plane <NUM>", "Plane <NUM>"), wherein each plane may include a certain number of blocks <NUM> (e.g., <NUM>,<NUM> blocks per plane). The size of a block <NUM> might be, for example, a certain number of pages (e.g., <NUM> pages) and each page may include a certain number of bytes (e.g., <NUM> + <NUM>,<NUM> bytes). Accordingly, each block <NUM> may be relatively large. As will be discussed in greater detail, each block <NUM> may include a plurality of sub-blocks, wherein erase failures may be contained at the sub-block level of granularity. Moreover, the erase failures may be tracked at the sub-block level so that exposure of available memory to users may be optimized and redundancy overhead may be minimized.

<FIG> shows an example in which a NAND memory <NUM> is organized into a plurality of blocks (i.e., "Block <NUM>", "Block <NUM>",. "Block N"). Each block also includes a plurality of sub-blocks that are individually tracked for success or failure of erase operations. In the illustrated example, an erase command that identifies a target block <NUM> (e.g., "Block i") results in a sub-block erase failure <NUM> (e.g., at "Sub-block <NUM>"). Thus, the target block <NUM> may be considered as having two subsets of sub-blocks - a first subset with failed erases and a second subset with successful erases. By tracking the erase failures, more memory may be made available to users because the entire target block <NUM> need not be treated as defective/faulty. Although a single sub-block erase failure <NUM> is shown for ease of discussion, multiple (and non-contiguous) sub-block erase failures may be tracked per block as described herein. Tracking the erase failures may be conducted in several different ways, depending on the circumstances.

<FIG> shows a method <NUM> of operating a memory device. The method <NUM> may generally be implemented in a memory device containing a NAND memory such as, for example, the NAND memory <NUM> (<FIG>), having an array organization such as, for example, the array organization <NUM> (<FIG>), already discussed. More particularly, the method <NUM> may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed-functionality logic hardware using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

Illustrated processing block <NUM> provides for initiating an erase of a block of NAND memory in response to an erase command, wherein the block includes a plurality of sub-blocks. The erase command may identify the entire block of NAND memory (e.g., as a targeted "erase block"). Processing block <NUM> may track a failure of the erase with respect to a first subset of the plurality of sub-blocks on an individual sub-block basis, wherein the erase is successful with respect to a second subset of the plurality of sub-blocks. As already noted, the erase failures may be tracked in a number of different ways.

For example, processing block <NUM> may include transferring a new type of command such as, for example, an "erase status enhanced command" from a solid state drive (SSD) controller to the NAND memory (e.g., in response to receiving an erase failure from the NAND memory) and transferring an identification of each sub-block in the first subset from the NAND memory to the SSD controller in response to the erase status enhanced command.

With continuing reference to <FIG>, processing block <NUM> includes transferring an indication of the number of sub-blocks in the first subset and an identification of each sub-block in the first subset from the NAND memory to the SSD controller in a variable number of bytes. Thus, an erase status enhanced command <NUM> directed to a particular address may cause an initial output byte <NUM> from the NAND memory to contain the number of sub-block failures, wherein a subsequent output byte <NUM> identifies a particular sub-block having an erase failure. In the illustrated example, after a certain time delay ("tdelay"), the NAND will provide the sub-block failure information.

<FIG> demonstrates that the response to the erase status enhanced command <NUM> may be formed in a fixed number of bytes <NUM> in order to achieve a more deterministic result. Thus, five bytes might be returned, with the first output byte containing the total number of sub-blocks in error and the remaining four bytes indicating which sub-blocks encountered an error. In such a case, one's or zeroes may be packed into the 32bits of the four bytes. Moreover, if no sub-blocks encountered erase errors, the first output byte may be zero, with subsequent bytes containing no useful information.

Returning now to <FIG>, processing block <NUM> may also include documenting each sub-block in the first subset in a table such as, for example, an internal table of the SSD controller. In the illustrated example, use of the first subset of the plurality of blocks is prevented at processing block <NUM>. Block <NUM> might include, for example, exposing the table of defective sub-blocks to a host platform and/or operating system (OS), generating a warning, etc., or any combination thereof. By contrast, illustrated block <NUM> permits use of the second subset of the plurality of sub-blocks. Block <NUM> may therefore result in more available memory being exposed. The illustrated method <NUM> may also enable a reduction in redundancy overhead (e.g., fewer XOR operations to calculate checksums).

<FIG> shows a memory-based computing system <NUM>. The system <NUM> may be part of a server (e.g., data center), desktop computer, notebook computer, tablet computer, convertible tablet, smart phone, personal digital assistant (PDA), media player, etc., or any combination thereof. The illustrated system <NUM> includes a compute subsystem <NUM> (e.g., host platform) and a communications interface <NUM> (e.g., switching fabric) coupled to the compute subsystem. The communications interface <NUM> may operate in compliance with, for example, NVMe (NVM Express) over PCIe (Peripheral Components Interconnect Express), SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI/Small Computer System Interface), PCIe, and so forth. In addition, a memory device <NUM> may be coupled to the communications interface <NUM>. In one example, the memory device <NUM> is an SSD. The memory device <NUM> may generally implement one or more aspects of the method <NUM> (<FIG>), already discussed. More particularly, the memory device <NUM> may include a NAND memory <NUM> such as, for example, the NAND memory <NUM> (<FIG>), also already discussed.

The NAND memory <NUM> may initiate an erase of a block of the NAND memory <NUM> in response to an erase command (e.g., that identifies the block), wherein the block includes a plurality of sub-blocks. Additionally, a controller <NUM> (e.g., memory/host interface controller) may be communicatively coupled to the NAND memory <NUM> via an interface <NUM> such as, for an ONFI (Open NAND Flash Interface, e.g., ONFI <NUM>, April <NUM>) bus. The controller <NUM>, which may include firmware, may track a failure of the erase with respect to a first subset of the plurality of sub-blocks on an individual sub-block basis. The erase may be successful with respect to a second subset of the plurality of sub-blocks. The controller <NUM> may document each sub-block in the first subset in a table (e.g., an internal table), not shown.

In one example, the controller <NUM> is configured to transfer an erase status enhanced (ESE) command to the NAND memory <NUM> and the NAND memory <NUM> is configured to transfer an identification of each sub-block in the first subset to the controller <NUM> in response to the ESE command. In another example, the NAND memory <NUM> may transfer an indication of the number of sub-blocks in the first subset and an identification of each sub-block in the first subset to the controller <NUM> in a variable number of bytes. In yet another example, the NAND memory <NUM> may transfer the indication of the number of sub-blocks in the first subset and the identification of each sub-block in the first subset to the controller <NUM> in a fixed number of bytes.

The controller <NUM> may permit use of the second subset of the plurality of sub-blocks as well as prevent use of the first subset of the plurality of sub-blocks. Accordingly, the illustrated memory device <NUM> reduces redundancy overhead and minimizes the amount of storage that is excluded when defects occur.

Techniques described herein may provide a NAND interface that achieves a reduction of redundancy for improved uncorrectable bit error rate and reduction in defect reserve overhead. Indeed, with 3D NAND, the isolation granularity for word line shorts may be isolated to a "tile" granularity that is much smaller than the size of a page. Since XOR redundancy may generally be used to protect against such a failure mode, techniques described herein may recognize the "tile" granularity and minimize the XOR overhead.

Embodiments are applicable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

Claim 1:
A memory-based computing system (<NUM>) comprising:
a compute subsystem (<NUM>);
a communications interface (<NUM>) coupled to the compute subsystem (<NUM>); and
a memory device (<NUM>) coupled to the communications interface (<NUM>), the memory device (<NUM>) including:
a non-volatile memory (<NUM>, <NUM>) to initiate an erase of a block of the non-volatile memory in response to an erase command, wherein the block is to include a plurality of sub-blocks; and
a non-volatile memory controller (<NUM>) communicatively coupled to the non-volatile memory (<NUM>, <NUM>), the non-volatile memory controller (<NUM>) is configured to track an erase failure of the block with respect to a first subset of the plurality of sub-blocks on an individual sub-block basis, wherein the erase is to be successful with respect to a second subset of the plurality of sub-blocks,
characterised in that
the non-volatile memory controller (<NUM>) is configured to transfer in a variable or fixed number of bytes, an indication of the number of sub-blocks in the first subset and an identification of each sub-block in the first subset to the non-volatile memory controller (<NUM>),
wherein an initial output byte of the variable number of bytes comprises the indication of the number of sub-blocks in the first subset and wherein a subsequent output byte of the variable number of bytes comprises the identification of the each sub-block in the first subset, and
wherein a first output byte of the fixed number of bytes comprises the indication of a number of sub-blocks in the first subset, and wherein remaining bytes of the fixed number of bytes comprises the identification of the each sub-block in the first subset.