Patent Description:
The present invention relates generally to refrigeration, and more particularly to a cooler device with superconductor shunts.

Solid-state electron cooling by the tunneling of "hot" electrons across a normal metal - insulator -superconductor (NIS) junction, using a bias voltage, has been proven to work below <NUM>, substantially operating like the more familiar near roomtemperature Peltier thermo-electric refrigerator. These NIS cryo-coolers are built from the same materials as Josephson junctions used in the superconducting circuitry and by the same lithography fabrication foundry tools, and are fundamentally completely compatible with the Josephson junction components. They could be integrated alongside the Josephson junctions themselves, fabricated concurrently. However, currently NIS coolers have a very limited temperature throw, with a maximum temperature difference between hot and cold sides of ~<NUM> mK.

One of the main limitations to NIS coolers' full performance is the presence in the superconducting leads of non-equilibrium quasi-particles arising from the high current running through the device. The low quasi-particle relaxation rate and thermal conductivity in a superconductor bind these hot particles in the vicinity of the junction and lead to severe overheating in the superconducting electrodes. There are several methods for reducing the accumulation of quasi-particles in a superconductor. The most common method is to use a normal metal coupled to the superconductor referred to as a quasiparticle trap, such that quasi-particles migrate to the normal metal and relax their energy there through electron-electron and electron-phonon interaction. This device is referred to as a normal metal - insulator -superconductor - normal metal (NISN) junction.

<CIT> illustrates a solid state cooler device that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer.

JPH1041558 A discloses a method for forming an oxide superconducting device where a substrate having a single crystal structure and including the oxide semiconductor is prepared. The oxide semiconductor uses a SrTiO<NUM> substrate doped with Nb and whereafter a Ba<NUM>-xKxBiO<NUM> thin film is directly deposited on the surface of the SrTiO<NUM> substrate.

The scientific publication tilted " <NPL> reveals electronic coolers based on large-area NIS junctions made of an Al/AlOx/Cu multilayer.

The current invention concerns a solid state cooler device according to the independent device claim <NUM> and a method of fabricating a solid state cooler device according to the independent method claim <NUM>.

The disclosure relates to a solid state cooler device that includes a plurality of NIS or NISN junctions in which a superconductor shunt layer is disposed on the surface of the normal layer (N) of the NIS or both normal layers of NISN devices that forms the junctions. The superconductor shunt layer shunts current from the normal metal layer by providing a lower resistance path. The currents that would flow in the normal metal instead flow through the superconductor shunt layer and eliminate the ohmic losses associated with the normal metal layers. Therefore, the superconductor acts to prevent I<NUM>*R losses in the normal metal improving the overall efficiency of the NIS cooler.

The current distribution through the junction is important because the junction is designed to operate at a particular A/cm<NUM>. If the current passing through a junction concentrates into a smaller area then the local A/cm<NUM> is higher than designed with the result that the junction is driven normal and begins producing heat. The current distribution through the bump bonds is also of concern because they are sized for a particular current and when that current increases then they also begin producing heat. Therefore, having superconductor shunts on the normal layers of the NIS junction or both normal layers of the NISN junctions prevents uneven current distribution through the bump bonds and prevents the current from concentrating locally as it passes through the junction. The superconductor shunts promote uniform current density through the NIS junctions and the bump bonds to mitigate heat generation due to nonuniform current flow through the NIS junctions.

In some implementations, NIS or NISN junctions are formed using copper as the normal metal. In order for NIS or NISN fabrication to be compatible with current foundry processes the normal metal needs to be deposited before the junction is formed. Therefore, a normal metal needs to be used that is compatible with a superconductor foundry process. These compatible normal metals have very high resistances which will incur large I<NUM>*R losses in the normal metal layer below the tunnel junction in the NIS or NISN Cooler. The superconductor shunt layer provides a low resistance path for the current that runs through the normal metal layer of the NIS or NISN junctions to reduce the I<NUM>*R losses, and promote uniform current density.

In one example, the NIS or NISN junctions each include a normal metal layer formed of titanium tungsten alloy (TiW) or titanium (Ti), an insulator formed of aluminum oxide or some other insulator, and a superconductor layer formed of indium, niobium, aluminum, or some other superconducting metal. A normal metal is a metal that does not superconduct at cryogenic operational device temperatures. It is to be appreciated that the insulator in a NIS or NISN device facilitates controlled band gaps between the normal metal and superconductor material since the relative levels of the bands can vary at the interface of the two materials. This insulator also hinders the return of heat back to the normal metal from the superconductor metal due to the hindering of the return of heat back to the cold normal metal.

<FIG> illustrates a cross-sectional view of an example of a solid state cooler device <NUM> that employs one or more NIS or NISN devices with superconductor shunt layers to facilitate uniform current density. The solid state cooler device <NUM> can be configured as a refrigeration stage employed in a cryogenic cooling application in which the solid state structure is one of a plurality of solid state cooler devices disposed about a refrigeration container that resides in a vacuum and holds superconducting circuitry. The plurality of solid state structures can provide the final stage in a cryogenic refrigeration system, and allow for efficient cooling by removal of heat from a cold side of the refrigeration stage, and prevent the return of heat from the hot side of the last refrigeration stage within a plurality of refrigeration stages.

As illustrated in <FIG>, the solid state cooler device <NUM> includes a first substrate <NUM> that is disposed on a cold side of a refrigeration stage, and a second substrate <NUM> that is disposed on a hot side of the refrigeration stage. The first substrate <NUM> can be a first chip containing superconducting circuitry and the second substrate <NUM> can be a second chip containing conventional or superconducting circuitry. Alternatively, the first and second substrates <NUM> and <NUM> can be a solid block of material such as a semiconductor or an insulator. A first superconductor shunt layer <NUM> is disposed within the first substrate <NUM> and a second superconductor shunt layer <NUM> is disposed within the first substrate <NUM> adjacent the first superconductor shunt layer <NUM> and separated by a gap <NUM>. A first normal metal pad <NUM> is disposed on a top side of the first superconductor shunt layer <NUM>, and a second normal metal pad <NUM> is disposed on a top side of the superconductor shunt layer <NUM>. The first normal metal pad <NUM> and the second normal metal pad <NUM> are disposed in a dielectric layer <NUM>, and formed of a normal metal, such as titanium tungsten (TiW) or titanium (Ti). The first superconductor shunt layer <NUM> and the second superconductor shunt layer <NUM> can be formed of a superconductor material such as niobium (Nb). A temperature sensor <NUM> resides on a bottom side of the first substrate <NUM> and can be formed of ruthenium oxide.

A first insulator layer <NUM> is disposed on a first end of the first normal metal pad <NUM> and a second insulator layer <NUM> is disposed on a second end of the first normal metal pad <NUM> separated from one another by a gap <NUM>. A third insulator layer <NUM> is disposed on a first end of the second normal metal pad <NUM> and a fourth insulator layer <NUM> is disposed on a second end of the second normal metal pad <NUM> separated from one another by a gap <NUM>. In one example, the first, second, third and fourth insulator layers are formed of aluminum oxide. The first insulator layer <NUM> is capped with a first superconductor pad <NUM>, the second insulator layer <NUM> is capped with a second superconductor pad <NUM>, the third insulator layer <NUM> is capped with a third superconductor pad <NUM>, and the fourth insulator layer <NUM> is capped with a fourth superconductor pad <NUM>.

The first, second, third and fourth insulator layers <NUM>, <NUM>, <NUM> and <NUM> are selected to have a thickness (e.g., about <NUM> Angstroms) thick enough to provide an insulator for a NIS or NISN tunnel junction. The first normal metal pad <NUM>, the first insulator layer <NUM>, and the first superconductor pad <NUM> form a first NIS junction <NUM>. The first normal metal pad <NUM>, the second insulator layer <NUM> and the second superconductor pad <NUM> form a second NIS junction <NUM>. The second normal metal pad <NUM>, the third insulator layer <NUM> and the third superconductor pad <NUM> form a third NIS junction <NUM>, and the second normal metal pad <NUM>, the fourth insulator layer <NUM> and the fourth superconductor pad <NUM> form a fourth NIS junction <NUM>.

Each of the first, second, third and fourth NIS junctions <NUM>, <NUM>, <NUM> and <NUM> are coupled to the second substrate <NUM> through a plurality of conductive contacts <NUM> (e.g., normal metal such as gold) to a plurality of conductive pads (e.g., gold pads). Although the first, second, third and fourth NIS junctions <NUM>, <NUM>, <NUM> and <NUM> are illustrated as being above the first substrate <NUM>, the first, second, third and fourth NIS junctions <NUM>, <NUM>, <NUM> and <NUM> or a portion thereof could be emedded within the first substrate <NUM>. The plurality of conductive contacts <NUM> can be a plurality of bump bonds that funtion to both transport electrical current and heat along with functioning as a mechanical bond of the first substrate <NUM> to the second substrate <NUM>.

A first conductive pad <NUM> resides in the second substrate <NUM> and is coupled to the first superconductor pad <NUM> via a first set of conductive contacts. The first conductive pad <NUM> can function as a quasi-particle trap for the first NIS junction <NUM> to form a first NISN junction. A second conductive pad <NUM> resides in the second substrate <NUM> and has a first end coupled the second superconductor pad <NUM> via a second set of conductive contacts, and the second end of the second conductive pad <NUM> is coupled to the third superconductor pad <NUM> via a third set of conductive contacts. A third conductive pad <NUM> resides in the second substrate <NUM> and is coupled to the fourth superconductor pad <NUM> via a fourth set of conductive contacts.

A third superconductor shunt layer <NUM> is disposed over the first conductive pad <NUM>, a fourth superconductor shunt layer <NUM> is disposed over the second conductive pad <NUM>, and a fifth superconductor shunt layer <NUM> is disposed over the third conductive pad <NUM>. The third superconductor shunt layer <NUM> has a first overhang region that extends beyond the first conductive pad <NUM>, and the fifth superconductor shunt layer <NUM> has a second overhang region that extends beyond the third conductive pad <NUM>. A first contact terminal <NUM> is embedded in the second substrate <NUM> and coupled to a first overhang region of the third supercondcutor shunt layer <NUM> and and also connected to a first electrical wire <NUM>. A second contact terminal <NUM> is embedded in the second substrate <NUM> and coupled to a second overhang region of the fifth superconductor shunt layer <NUM>, and and also connected to a second electrical wire <NUM>. Alternatively, the first conductive pad <NUM>, the second conductive pad <NUM>, and the third conductive pad <NUM> (and <NUM> and <NUM>) can overlay the second substrate <NUM>.

In operation, a bias voltage is applied between the first electrical wire <NUM> and the second electrical wire <NUM> causing a current to flow from the first contact terminal <NUM> to the second contact terminal <NUM>. That is the current flows from the first contact terminal <NUM> through the third superconductor shunt layer <NUM>, the first conductive pad <NUM>, the first NISN junction <NUM>, the first superconducting shunt layer <NUM>, the second NISN junction <NUM>, the second conductive pad <NUM>, the fourth superconductor shunt layer <NUM>, back through the second conductive pad <NUM>, the third NISN junction <NUM>, the second superconducting shunt layer <NUM>, the fourth NISN junction <NUM>, the third conductive pad <NUM>, the fifth superconductor shunt layer <NUM> to the second contact terminal <NUM>. The bias voltage raises the energy level of the hot electrons and the hot holes on the first normal metal pad <NUM> and the second normal metal pad <NUM>, where hot electrons above the Fermi level and the hot holes below the Fermi level tunnel across the insulatating layers into the superconductor pads to the conductive pads, thus removing heat from the first and second normal metal pads <NUM> and <NUM>. This provides for a reduction of temperature and an increase delta temperature between the hot side and cold side of the solid state cooler device <NUM>.

The normal metals in the device <NUM> can be formed of normal metals such as gold, platinum, or a metal that is above its superconducting transition temperature, such as titanium, ruthenium, or chromium, or a combination thereof. The superconducting metals can be formed of a superconductor such as indium, niobium, aluminum, or some other superconducting metal. Although the example of <FIG> is shown as having <NUM> NIS or NISN devices, any multiple of <NUM> NIS or NISN devices will allow the solid state cooler to operate as described.

<FIG> illustrates a current density flow diagram <NUM> of current flowing between a first NISN junction <NUM> junction and a second NISN junction <NUM> with top and bottom normal metal pads, while <FIG> illustrates current density flow diagram <NUM> of current flowing between a first NISN junction <NUM> junction and a second NISN junction <NUM> with top and bottom superconductor shunts. In <FIG>, the two junctions <NUM> and <NUM> are connected using a normal metal trace top and bottom. The current chooses to follow the path of least resistance, therefore, the majority of the current flows through an incoming end of the top normal metal layer, through a first bump bond closest to the incoming end of the top normal metal layer, through the superconductor layer of the NISN junction and through the connecting end of the bottom normal metal layer connected closest to the second NISN junction. This means that the current doesn't evenly cross the boundary between the top normal metal layer, the superconductor layer, the insulator, and the bottom normal metal layer of either the first or second NISN junctions <NUM> and <NUM>. The result is inefficiency in the performance of the junctions.

In <FIG>, the two junctions are connected using a superconductor shunt on the top and bottom of the first and second NISN junctions. <FIG> illustrates that the current evenly distributes itself as it moves through the device. That is current evenly distributes through the top superconductor shunt, the top normal metal layer, through the bump bonds, through the superconductor layer, the insulator and normal metal layers of each NISN junctions and finally through the bottom superconductor shunt. This is the result of the superconductor shunts at the top and bottom of each NISN junction. The path of least resistance is through the superconductor shunts allowing for even distribution at all points on the junctions.

Turning now to <FIG>, fabrication is discussed in connection with formation of the solid state cooler of <FIG>. Although the present example is illustrated as a first portion and second portion of the solid state cooler being fabricated serially, it is to be appreciated that both portions could be fabricated concurrently or in a reverse order with the second portion being fabricated first and the second portion being fabricated second.

<FIG> illustrates a cross-sectional view of a first portion of a solid state cooler in its early stages of fabrication. A photoresist material layer <NUM> overlies a first substrate <NUM> and is patterned and developed to expose openings <NUM> in the photoresist material layer <NUM> in accordance with a pattern. The photoresist material layer <NUM> can have a thickness that varies in correspondence with the wavelength of radiation used to pattern the photoresist material layer <NUM>. The photoresist material layer <NUM> may be formed over the first substrate <NUM> via spin-coating or spin casting deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form openings <NUM>.

<FIG> also illustrates performing of an etch <NUM> (e.g., anisotropic reactive ion etching (RIE)) on the first substrate <NUM> to form extended openings <NUM> (<FIG>) in first substrate <NUM> based on the pattern in the photoresist material layer <NUM>. The photoresist material layer <NUM> is thereafter stripped (e.g., ashing in an O<NUM> plasma) so as to result in the structure shown in <FIG>. Next, the structure undergoes a contact material fill to deposit superconductor <NUM> into the openings <NUM>, as illustrated in <FIG>. The superconductor can be deposited employing a standard contact material deposition. Alternatively, a photoresist lift-off process could be employed. Following deposition of the superconductor, the superconductor material is polished by, for example, a chemical mechanical polish (CMP) down to the surface of the substrate <NUM> to form a first superconductor shunt <NUM> adjacent a second superconductor shunt <NUM> separated by a gap <NUM>, as illustrated in <FIG>.

Next, a first normal metal pad <NUM> and a second normal metal pad <NUM> are disposed within a dielectric layer <NUM> (e.g., silicon oxide (SiO<NUM>)) that collectively reside over a first substrate <NUM> to form the structure of <FIG>. The first normal metal pad <NUM> and the second normal metal pad <NUM> are formed of a normal metal, such as titanium tungsten alloy (TiW) or titanium (Ti) with the first normal metal pad <NUM> being disposed above the first superconductor shunt <NUM>, and the second normal metal pad <NUM> being disposed over the second superconductor shunt <NUM>. The first normal metal pad <NUM> and the second normal metal pad <NUM> can be formed by the following: deposition of a dielectric layer <NUM> onto the substrate <NUM>, a photolithography process of a normal metal layout in a patterned photoresist layer, etching of the normal metal layout into the dielectric layer <NUM> to form extended openings into the dielectric layer <NUM> and the stripping of the resist; deposition of normal metal such as chemical vapor deposition of tungsten (W) over a deposited physical vapor deposition titanium (Ti) / titanium nitride (TiN) liner; and a chemical mechanical polish (CMP) process on the normal metal to planarize the normal metal with the dielectric layer <NUM>.

Next, the structure undergoes a material deposition to form an insulator layer <NUM> (e.g., aluminum oxide) over the structure of <FIG> to provide the resultant structure of <FIG>. The insulator layer <NUM> can be deposited employing a standard contact material deposition. Alternatively, an aluminum layer can be deposited and oxidized to form an aluminum oxide layer. The insulator layer <NUM> should have a thickness of at least <NUM> Angstroms to function as a tunnel barrier. A superconductor material layer <NUM> (e.g., niobium) is then deposited over the insulator layer <NUM> to provide the resultant structure of <FIG>. The superconductor material layer <NUM> can be deposited employing a standard contact material deposition.

Next, a photoresist material layer <NUM> is formed over the structure of <FIG>, and patterned with openings <NUM> over the superconductor material layer <NUM> to provide the structure of <FIG>. An etch process <NUM> is then performed on the structure of <FIG> to extend the patterned openings <NUM> to the dieletric layer <NUM>, the first normal metal pad <NUM> and the second normal metal pad <NUM>. The photoresist material layer <NUM> is then removed to provide the resultant structure of <FIG> that includes a first NIS junction <NUM>, a second NIS junction <NUM>, a third NIS junction <NUM>, and a fourth NIS junction <NUM>.

The first NIS junction <NUM> is formed of the first normal metal pad <NUM>, a first insulator layer <NUM> and a first superconductor pad <NUM>. The second NIS junction <NUM> is formed of the first normal metal pad <NUM>, a second insulator layer <NUM> and a second superconductor pad <NUM>. The third NIS junction <NUM> is formed of the second normal metal pad <NUM>, a third insulator layer <NUM> and a third superconductor pad <NUM>, and the fourth NIS junction <NUM> is formed of the second normal metal pad <NUM>, a fourth insulator layer <NUM> and a fourth superconductor pad <NUM>. The first, second, third and fourth insulator layers <NUM>, <NUM>, <NUM> and <NUM> are selected to have a thickness (e.g., about <NUM> Angstroms) thick enough to provide an insulator for a NIS or NISN tunnel junction.

Next, the backside of the first substrate <NUM> is thinned down by grinding or a chemical mechanical polish. An optional temperature sensor <NUM> can be formed on the backside of the first substrate <NUM> by depositing a layer of ruthenium oxide, which is then covered by a patterned photoresist material, and etched to provide the resultant temperature sensor <NUM> that resides on a bottom side of the first substrate <NUM>, as illustrate in <FIG>.

<FIG> illustrates a second portion of a solid state cooler in its early stages of fabrication. A photoresist material layer <NUM> overlies a dielectric layer <NUM> that overlies a second substrate <NUM>. The second substrate <NUM> includes a third superconductor shunt <NUM>, a fourth superconductor shunt <NUM> and a fifth superconductor shunt <NUM>. <FIG> also illustrates performing of an etch <NUM> (e.g., anisotropic reactive ion etching (RIE)) on the dielectric layer <NUM> to form extended openings <NUM> and <NUM> (<FIG>) in the dielectric layer <NUM> based on the pattern in the photoresist material layer <NUM> to exposed the surface of the third superconductor shunt <NUM>, the fourth superconductor shunt <NUM> and the fifth superconductor shunt <NUM>. The photoresist material layer <NUM> is thereafter stripped (e.g., ashing in an O<NUM> plasma) so as to result in the structure shown in <FIG>.

Next, the structure undergoes a contact material fill to deposit gold into the openings <NUM> and <NUM>. The gold can be deposited employing a standard contact material deposition. Following deposition of the gold, a first conductive pad <NUM> spaced apart from a first contact terminal are both formed overlying the third superconductor shunt <NUM>, a second conductive pad <NUM> is formed overlying the fourth superconductor shunt <NUM>, and a third conductive pad <NUM> spaced apart from a second contact terminal are both formed overlying the fifth superconductor shunt <NUM>. Alternatively, the processes shown in <FIG> can be replaced by a photoresist deposition and patterning, metal evaporation into the patterned openings and an excess metal and photoresist lift-off process.

Next, a plurality of conductive contacts <NUM> (e.g., bump bonds) are formed on the surface of the first conductive pad <NUM>, the second conductive pad <NUM> and the third conductive pad <NUM>. The conductive contacts <NUM> can be either fabricated from a superconducting metal and/or a normal metal. The conductive contacts <NUM> can be formed using a standard liftoff process or through etching. Alternatively, the conductive contacts could be deposited. The conductive contacts can be formed on either the conductive pads as shown or on the superconductor pads of <FIG>.

The second substrate <NUM> is then flipped and disposed over the first substrate <NUM> and bonded, such that the third conductive pad <NUM> is aligned and coupled to the first superconductor pad <NUM>, a first end of the second conductive pad <NUM> is aligned and coupled to the second superconductor pad <NUM>, a second end of the second conductive pad <NUM> is aligned and coupled to the third superconductor pad <NUM>, and the first conductive pad <NUM> is aligned and coupled to the fourth superconductor pad <NUM>. The resultant structure is illustrated in <FIG>.

<FIG> illustrates a block diagram of a refrigeration system <NUM> that employs solid state devices such as the solid state device <NUM> of <FIG>. The refrigeration system <NUM> includes a plurality of stages labeled stage #<NUM> to stage #N, where N is an integer greater than or equal to <NUM>. Each refrigeration stage provides an additional temperature drop from the previous stage, such that the Nth stage is the final stage and provides the last temperature drop and lowest temperature of the refrigeration system <NUM>. In other examples, the Nth stage is a first or intermediary stage as opposed to the last stage. Stage #N in the refrigeration system <NUM> includes a refrigeration container <NUM> with a plurality of solid state devices <NUM> simlar to that illustrated in <FIG> disposed about the container and cooperating to provide the final lowest temperature of the refrigeration system <NUM> within the container <NUM>. The container <NUM> can be in a vacuum environment and be configured to house superconducting circuitry. In another example, one or more of the other stages employ solid state devices similar to those in stage #N to provide incremental temperature drops across the refrigeration system <NUM>. In other examples, the refrigeration container <NUM> can be formed of a normal metal that provides the final normal metal layer of each solid state device <NUM>.

Claim 1:
A solid state cooler device (<NUM>) comprising:
a first superconductor shunt (<NUM>);
a first normal metal pad (<NUM>) disposed on the first superconductor shunt (<NUM>);
a first insulator layer (<NUM>) and a second insulator layer (<NUM>) disposed on the normal metal pad (<NUM>) and separated from one another by a gap (<NUM>);
a first superconductor pad (<NUM>) disposed on the first insulator layer (<NUM>) and a second superconductor pad (<NUM>) disposed on the second insulator layer (<NUM>);
a first conductive pad (<NUM>) coupled to the first superconductor pad (<NUM>), and a second conductive pad (<NUM>) coupled to the second superconductor pad (<NUM>); and
wherein the solid state cooler device is configured to remove hot electrons from the first normal metal pad (<NUM>) when a bias voltage is applied between the first conductive pad (<NUM>) and the second conductive pad (<NUM>), and wherein first superconductor shunt (<NUM>) is configured to facilitate even current distribution through the device (<NUM>).