Patent Description:
A solid-state drive (SSD) is a data storage device that uses non-volatile memory such as NAND (Not-And) or NOR (Not-Or) non-volatile memory to store persistent digitally encoded data. The SSD is configured to emulate a hard disk drive, i.e., a device that stores persistent digitally encoded data on magnetic surfaces of rapidly rotating platters and replaces a hard disk drive (HDD) in many applications.

A host is typically coupled to the SSD to read data from the SSD, write data to the SSD, and erase data from the SSD. To facilitate the reading, writing, and erasing of the data, the SSD has an SSD controller with a host interface for communicating with the host and a non-volatile memory interface for managing the non-volatile memory. The host interface includes addressing, a data bus, and control for communicating with the host and conforms to a data communication protocol such as Serial Advanced Technology Attachment (SATA), Serial Attached Small Computer System Interface (SAS), Non-Volatile Memory Express (NVMe) or Universal Serial Bus (USB), while the non-volatile memory interface includes addressing, a data bus, and control for managing the non-volatile memory and conforms to a data communication protocol such as open NAND flash interface (ONFI) for NAND non-volatile memory.

The host issues write, read, and erase requests to perform a write, read, and erase operation, respectively, on the SSD. To perform the write operation, the host sends a write request to the SSD. The write request indicates data to write and a data address where to write the data. The write request is received at the host interface of the SSD. The SSD controller then executes hardware and/or firmware to write the data in the non-volatile memory based on the data address, via the non-volatile memory interface. To perform the read operation, the host sends a read request to the SSD. The read request indicates a data address to read. The read request is received at the host interface of the SSD. The SSD controller executes hardware and/or firmware to read data in the non-volatile memory based on the data address. The SSD controller receives the data that is read from the non-volatile memory via the non-volatile memory interface and provides the read data to the host via the host interface. To perform the erase operation, the host sends an erase request to the SSD. The erase request indicates a data address to erase. The erase request is received at the host interface of the SSD. The SSD controller executes hardware and/or firmware to perform an erase operation in the non-volatile memory based on the data address.

The SSD has a latency and throughput that depends on a type of non-volatile memory used by the SSD. For example, NOR non-volatile memory might read and/or write data faster than NAND non-volatile memory. The SSD also has a latency and throughput that depends on an SSD controller implementation. SSD controllers may be designed with different firmware parameters associated with reading and/or writing data, have different non-volatile memory interface speeds, and have different host interface speeds. In this regard, SSDs using different controllers or different types of non-volatile memory will perform differently.

A manufacturer builds SSDs with the different SSD controllers and non-volatile memory types depending on cost and/or component availability. In this regard, the SSDs from the same manufacturer will perform differently depending on components in the SSD. Because the SSDs use different components, the manufacturer cannot guarantee a same level of latency and throughput of the SSDs, even though in some situations customers might expect a same level of performance.

<CIT> discloses, performing a status read operation to determine the status of a memory command, after a hold off time following the issuance of a memory command If the memory command has not yet completed, a polling interval is used to perform a status read operation and repeating the process until the memory command has been completed.

<CIT> relates to methods, systems and computer program products for implementing a polling process among one or more flash memory devices. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device.

<CIT> relates to an apparatus which includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.

It is the object of the present invention to provide an improved adaptation of non-volatile memory access timers.

Preferred embodiments of the invention are defined by the dependent claims.

This disclosure relates to controlling performance of solid state drives (SSD), namely controlling latency and throughput of SSDs by adjusting wait time duration and/or polling time duration associated with reading, writing, and/or erasing data in the non-volatile memory of the SSD. The adjustment of the wait time duration and/or polling time duration allows for controlling performance of SSDs even though the SSDs use different SSD controller implementations or non-volatile memory types.

According to an aspect of the described system and techniques, a method comprises receiving a storage access request to access a solid state drive (SSD); setting a non-volatile memory access timer with a time duration, wherein the time duration is based on a desired performance of the SSD; sending a non-volatile memory command associated with the storage access request to non-volatile memory; starting the non-volatile memory access timer; determining whether the non-volatile memory completed execution of the non-volatile memory command after the non-volatile memory access timer indicates that the time duration elapsed; providing an indication that the storage access request is complete if the non-volatile memory completed execution of the non-volatile memory command; and resetting the non-volatile memory access timer based on the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.

According to another aspect of the described system and techniques, a non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to at least: receive a storage access request to access a solid state drive (SSD); set a non-volatile memory access timer with a time duration, wherein the time duration is based on a desired performance of the SSD; send a non-volatile memory command associated with the storage access request to non-volatile memory; start the non-volatile memory access timer; determine whether the non-volatile memory completed execution the non-volatile memory command after the non-volatile memory access timer indicates that the time duration elapsed; provide an indication that the storage access request is complete if the non-volatile memory completed execution of the non-volatile memory command; and reset the non-volatile memory access timer based on the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.

According to yet another aspect of the described system and techniques, an SSD comprises: an SSD controller having a non-volatile memory access timer; a non-volatile memory; instructions stored in memory of the SSD controller and that, when executed by one or more processors of the SSD controller, cause the SSD controller to at least: receive a storage access request to access the SSD; set the non-volatile memory access timer with a time duration, wherein the time duration is based on a desired performance of the SSD; send a non-volatile memory command associated with the storage access request to the non-volatile memory; start the non-volatile memory access timer; determine whether the non-volatile memory completed execution of the non-volatile memory command after the non-volatile memory access timer indicates that the time duration elapsed; provide an indication that the storage access request is complete if the non-volatile memory completed execution of the non-volatile memory command; and reset the non-volatile memory access timer based on the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.

In this regard, mechanisms are provided for controlling performance of SSDs.

The drawings are for the purpose of illustrating example embodiments, but it is understood that the embodiments are not limited to the arrangements and instrumentality shown in the drawings.

This disclosure provides examples and details for controlling performance of a solid state drive (SSD), namely controlling latency and throughput associated with read, write, and erase operations on the SSD, by controlling a wait time duration and polling time duration associated with non-volatile memory of the SSD. The latency is indicative of a delay to complete a read, write, or erase operation and the throughput is indicative of a rate by which the operations are completed. By controlling the wait time duration and the polling time duration, SSDs that use different SSD controller implementations or non-volatile memory types is arranged to have similar performance. The principles described herein is applied to controlling performance of other type of storage devices, such as a hard disk drive (HDD) or hybrid SSD/HDD drives where a storage medium is accessed.

<FIG> illustrates an example SSD arranged with functionality to control latency and throughput of the SSD. The SSD <NUM> includes an SSD controller <NUM> and non-volatile memory (NVM) array <NUM>. The SSD <NUM> is coupled to a host <NUM> such as a computer system for performing read, write, and erase operations on the SSD <NUM>.

The SSD controller <NUM> has a host interface <NUM> and a non-volatile memory interface <NUM>. The host interface <NUM> facilitates communicating with the host <NUM>. The host interface <NUM> includes addressing, a data bus, and control for communicating with the host <NUM> and conforms to a data communication protocol such as Serial Advanced Technology Attachment (SATA), Serial Attached Small Computer System Interface (SAS), Non-Volatile Memory Express (NVMe) or Universal Serial Bus (USB). For example, the host interface <NUM> receives data to be stored on the SSD <NUM> from the host <NUM> and transmits data stored on the SSD <NUM> to the host <NUM>. The non-volatile memory interface <NUM> facilitates management of the non-volatile memory array <NUM>. The non-volatile memory interface <NUM> includes addressing, a data bus, and control for managing the non-volatile memory array <NUM> and conforms to a data communication protocol such as open NAND ("Not-And") flash interface (ONFI) for NAND flash. The SSD controller <NUM> facilitates performing read, write, and erase operations on the non-volatile memory array <NUM>.

During a write operation, the host <NUM> writes data to the SSD <NUM>. The SSD controller <NUM> receives this data from the host <NUM> via a write request which also identifies a logical block address (LBA) where to write the data. The SSD controller <NUM> maps the LBA to a physical address in the non-volatile memory array <NUM> and cause the non-volatile memory array <NUM> to write the data to the corresponding physical address. The SSD <NUM> has one or more of volatile memory <NUM>, nonvolatile memory <NUM>, or other memory (e.g., memory within the SSD controller) to store mapping information that associates an LBA with a physical address.

During a read operation, the host <NUM> reads data from the SSD <NUM>. For example, the host <NUM> sends a read request to the SSD controller <NUM> with a logical block address (LBA) where to read the data. The SSD controller <NUM> receives the read request from the host <NUM>. The SSD controller <NUM> maps the LBA to a physical address in the non-volatile memory array <NUM> and cause the non-volatile memory array <NUM> to read the data from the corresponding physical address and provide it to the SSD controller <NUM>. The SSD controller <NUM> then provides the read data to the host <NUM> via the host interface <NUM>.

During an erase operation, the host <NUM> erases data from the SSD <NUM>. For example, the host sends an erase request to the SSD controller <NUM> with an LBA where data is to be erased. The SSD controller <NUM> receives the erase request from the host <NUM>. The SSD controller <NUM> maps the LBA to a physical address in the non-volatile memory array <NUM> and cause the non-volatile memory array <NUM> to erase the data from the corresponding physical address in the non-volatile memory array <NUM>.

The non-volatile memory array <NUM> includes one or more non-volatile memory <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>. <NUM>-n, referred to collectively as non-volatile memory <NUM> or the non-volatile memory array <NUM>. In some examples, each non-volatile memory <NUM>-<NUM>. <NUM>-n store data in a plurality of blocks, and each of the blocks includes a plurality of addressable s pages. Each of the addressable pages is a physical memory location that corresponds to a physical address, which in turn is associated with an LBA. Accordingly, each LBA written to or read by the host <NUM> corresponds to a physical location in one of the non-volatile memories <NUM>-<NUM>. <NUM><NUM>-n that is accessed according to one of the addressable pages. The non-volatile memory array <NUM> implements NAND non-volatile memory, NOR (Not-Or) non-volatile memory, a combination of NAND and NOR non-volatile memory, or other types of storage media.

The SSD controller <NUM> also has one or more non-volatile memory timers, shown as a wait timer <NUM> and status polling timer <NUM>. The non-volatile memory timer is set with a given time duration and provide an indication when the given time duration has elapsed after starting the non-volatile memory timer. For example, the non-volatile memory timer is set with the given time duration (e.g., <NUM> microseconds) and the non-volatile memory timer started. The non-volatile memory timer has a counter or timer for determining that the given time duration elapsed since when the non-volatile memory timer was started. After the time duration elapsed, the non-volatile memory timer provides the indication.

The non-volatile memory timer in the form of the wait timer <NUM> and status polling timer <NUM> are used to facilitate reading, writing, and/or erase operations in the non-volatile memory array <NUM>. The wait timer <NUM> and status-polling timer <NUM> is set to a respective time duration and started when a read, write, or erase command is issued to the non-volatile memory <NUM> array as part of the read, write, or erase operation. The wait timer <NUM> and status polling timer <NUM> provides respective indications when the respective time duration has elapsed. After the time duration of the wait timer <NUM> and/or status polling timer <NUM> elapses, SSD controller <NUM> performs a status polling to determine completion of the read, write, or erase command by the non-volatile memory array <NUM>. If the SSD controller <NUM> determines that the read, write, or erase command is complete, then SSD provides an indication to the host <NUM> via the host interface <NUM> that the read, write, or erase operation is complete. Otherwise, the wait timer <NUM> and status polling timer <NUM> is reset and the SSD controller <NUM> performs additional status polling requests based on the wait timer <NUM> and status polling timer <NUM> until the read, write, or erase command is complete.

In examples, the SSD controller <NUM> has a timer controller <NUM> to facilitate setting the wait timer <NUM> and/or status polling timer <NUM> with the time duration to control performance of the SSD <NUM>, such as latency and/or throughput, during storage operations such as the read, write, or erase operation. The latency is indicative of a delay to complete the read, write, or erase operation and the throughput is indicative of a rate by which the read, write, or erase operation is completed. Setting the wait timer <NUM> and/or status polling timer <NUM> with a longer time duration results in a longer latency and/or less throughput of the SSD <NUM>. Setting the wait timer <NUM> and/or status polling timer <NUM> with a shorter time duration results in a shorter latency and/or more throughput of the SSD <NUM>. SSD controller <NUM> is shown to have both a wait timer <NUM> and status polling timer <NUM>, but in some examples, the SSD controller <NUM> has one or the other timer, or additional timers. In other examples, the wait timer <NUM> and status polling timer <NUM> is located on other systems of the SSD <NUM>.

Setting the non-volatile memory access timer with the given time duration allows for artificially tuning the SSD to meet performance criteria such as a latency and/or throughput of the SSD. The given time duration is set in many ways, examples of which are provided below.

In various examples, the given time duration of the non-volatile memory access timer is set based on a configuration of the SSD such as the non-volatile memory in the SSD or SSD controller implementation. For example, an SSD with NOR non-volatile memory might read and/or write data faster than an SSD with NAND non-volatile memory. If the SSD has a NAND non-volatile memory, the time duration is set to one time value stored in the SSD controller <NUM> while if the SSD has a NOR non-volatile memory, the time duration is set to another time value stored in the SSD controller <NUM> to achieve a desired performance of the SSD for the configuration of the SSD. As another example, SSD controllers is designed with different firmware parameters associated with reading and/or writing data, have different non-volatile memory interface speeds, and have different host interface speeds. The wait timer and/or polling timer is set with respective time durations to achieve a desired performance of the SSD for the configuration of the SSD controller.

For example, the SSD controller stores a mapping of different host interface speeds, non-volatile memory interface speeds, and/or firmware parameters of the SSD to different time durations. Based on a current host interface speed, non-volatile memory interface speed, and/or firmware parameters of the SSD, the SSD controller identifies the mapped time durations and set the wait timer and/or status polling timer with the time durations. The polling time duration and/or wait time duration is increased to increase latency and decrease throughput while the polling time duration and/or wait time duration is decreased to decrease latency and increase throughput to achieve a desired performance of the SSD for the configuration of the SSD. In this regard, latency and/or throughput of the SSD is artificially controlled by changing one or more of the polling time duration and wait time duration. Further, by controlling the wait time duration and the polling time duration, SSDs that use different SSD controller implementations or non-volatile memory is arranged to have similar performance. For example, if one SSD has different components than another SSD, one or more of the polling time duration and wait time duration for each SSD is set so that performance of each SSD is similar despite use of the different components.

In various examples, the wait time duration and/or polling time duration is set based on a storage access request. For example, the storage access request is a read request to read data stored in the SSD, a write request to write data to the SSD, or an erase request to erase data in the SSD. The time duration is set so that the SSD meets performance criteria associated with the SSD.

<FIG> is a flow chart of example functions associated with setting the wait time duration and/or polling time duration to control performance of the SSD based on the storage access request. The functions is implemented by the SSD controller in hardware, firmware, and/or a combination of hardware and firmware.

At <NUM>, a storage access request is received. The storage access request is received from a host at a host interface of the SSD controller.

At <NUM>, a determination is made as to the type of the storage access request that is received. The storage access request is a read request, write request or erase request. Each type of storage access request is associated with a given time duration associated with the wait timer and status polling timer such as a respective wait time duration and polling time duration stored in the SSD controller.

At <NUM>, the non-volatile memory access timer is set with a time duration based on the type of the storage access request. For example, if the type of storage access request is a write request and the non-volatile memory access timer is a status polling timer, then the status polling timer is set to a polling time duration stored in the SSD controller which is associated with the write request. As another example, if the type of storage access request is a write request and the non-volatile memory access timer is a wait timer, then the wait timer is set to a wait time duration stored in the SSD controller which is associated with the write request. The wait timer and status polling timer is similarly set to the respective wait time duration and polling time duration associated with the read request or erase request if the storage access request is a read request or erase request. In some examples, the wait time duration is the same for each of the requests and the polling time duration differs.

In various examples, the wait time duration and/or polling time duration is defined by a configuration command. The configuration command is indicative of a desired performance of the SSD.

<FIG> is an example of a configuration command that might be used to set the time duration. The configuration command <NUM> is sent from the host or generated by the SSD controller. The configuration command <NUM> includes a type field <NUM> and a timer field <NUM>. The type field <NUM> indicates that the command is a configuration command by a unique code such as string of bits. The timer field <NUM> defines one or more time durations. As illustrated, the timer field <NUM> takes the form of one or more of a wait time duration field <NUM> and a polling time duration field <NUM>, both of which are shown in the configuration command <NUM>. The wait time duration field <NUM> and a polling time duration field <NUM> indicates the wait time duration and polling time duration associated with the wait timer and status polling timer, respectively. Based on identification of the configuration command by the type field, the SSD controller sets the respective non-volatile memory timer with the time durations in the timer field <NUM>. For example, the wait timer is set with the wait time duration in the wait time duration field <NUM> and the status polling timer is set with the polling time duration in the polling time duration field <NUM>.

In some examples, the SSD controller stores an indication of a preset polling time duration and preset wait time duration in memory which is then accessed and associated with the status polling timer and wait timer respectively. The configuration command provides an indication to select a particular preset polling time duration and preset wait time duration from a plurality of options stored on the SSD controller rather than specifying an actual polling time duration and wait time duration in the configuration command itself. This way firmware overhead for obtaining the wait time duration or polling time duration is reduced since the time durations are already stored locally, for example, in a register of the SSD controller.

<FIG> is an example flow chart <NUM> of example functions associated with controlling performance of the SSD by setting the wait timer and/or status polling timer associated with storage operations. The functions implements on the SSD controller in firmware, hardware, or a combination of firmware and hardware. Setting the wait timer and/or status polling timer with a given time duration allows for artificially tuning the SSD to meet performance criteria such as a latency and/or throughput of the SSD.

At <NUM>, the SSD controller receives a storage access request from the host. The host interface of the SSD controller receives the storage access request. The storage access request takes many forms. For example, the storage access request is the read request with an indication of a logical address associated with the data to be read. As another example, the storage access operation is the write request with an indication of the data to write to the SSD and the logical address where the data is to be written. As another example, the storage access operation is an erase request with an indication of the logical address having the data to be erased. The storage access request takes other forms as well.

At <NUM>, the SSD controller sets a non-volatile memory access timer with a given time duration, where the given time duration is based on a desired performance of the SSD. The non-volatile memory access timer takes the form of the wait timer and/or status polling timer. The wait timer and status polling timer is set with a respective wait time duration and polling time duration to control the performance of the SSD. The respective wait time duration and polling time duration is determined in many ways as described above. The setting of the wait timer and status polling timer with the respective wait time duration and polling time duration artificially tunes the SSD to meet performance criteria such as a latency and/or throughput of the SSD.

At <NUM>, the SSD controller sends a non-volatile memory command to the non-volatile memory array based on the storage access request. For example, a read command identifies the physical address in the non-volatile memory to be read which corresponds to the logical address to be read, indicated by the read request. As another example, a write command identifies.

At <NUM>, the SSD controller performs the status polling after the wait time duration elapses. The status polling is a check on a status of whether the non-volatile memory array has completed execution of the non-volatile memory command. The status polling takes the form of checking a register in the non-volatile memory which indicates whether the execution is complete. As another example, the status polling takes the form of sending a status message to the non-volatile memory requesting an indication whether the execution is complete.

At <NUM>, a response to the status polling is received and, at <NUM>, the response to the status polling is checked. The response is a message from the non-volatile memory which indicates whether execution is complete or a result of checking the register which indicates whether execution is complete. If the response indicates that execution of the non-volatile memory command is complete, then at <NUM>, an indication is provided to the host that the storage access request is complete. For example, if the non-volatile memory command is a read command, then the execution is complete when the data to be read is available to the SSD controller. As another example, if the non-volatile memory command is a write command, then the execution is complete when the data is written to the non-volatile memory. In yet another example, if the non-volatile memory command is an erase command, then the execution is complete when the data to be erased is erased by the non-volatile memory. If the non-volatile memory command is a read command, the SSD controller requests the read data from the non-volatile memory which is provided to the SSD controller. The indication to the host is the data that is read. For write or erase requests, the indication is a message or status indication that the respective write or erase request has been performed.

In some examples, the non-volatile memory array has not completed execution of the non-volatile memory command even after the SSD controller performs the initial status polling. In such a case, the SSD controller performs additional status polling requests. The status polling timer controls how frequently the controller shall issue the additional status polling requests.

The status polling timer is set to the time duration equal to the polling time duration at <NUM>. At <NUM>, the SSD controller starts the status polling timer and wait for the polling time duration to elapse. At <NUM>, the status polling timer indicates that the polling time duration has elapsed, at which point the status polling is performed, and not performed otherwise. After the status polling is performed, processing continues to <NUM>. Blocks <NUM>, <NUM>, <NUM>, and <NUM> are executed until the host is provided with an indication that the storage access request is complete at block <NUM>.

In some examples, block <NUM> includes setting the status polling timer with the polling time duration before starting the status polling timer if the status polling timer is not set with the polling time duration before being started. In some examples, the SSD controller varies
the polling time duration after one or more times the status polling timer is reset for the storage access operation. For instance, the SSD controller has a counter which counts how many times the status polling has been performed for the storage access request. The status polling timer duration is increased and/or decreased based on the count so that performance criteria is met and latency and/or throughput of the SSD is fine tuned.

The time duration which the wait timer and status polling timer are set allows for controlling a latency and throughput of the SSD. For example, setting the wait timer to a longer wait time duration and/or setting the status polling timer to a longer polling time duration increases
a time to perform the storage access operation. As another example, setting the wait timer to a shorter wait time duration and/or setting the status polling timer to a shorter polling time duration decreases a time to perform the storage access operation. This way performance of the SSD is adjusted for various SSD controller and/or non-volatile memory configurations so that performance across a plurality of SSDs is the same or different.

<FIG> illustrates graphically how the setting of the wait time duration of the wait timer might change latency and/or throughput performance of the SSD. Two message flows <NUM> and <NUM> are shown as a result of issuing a read command <NUM>. A horizontal axis <NUM> indicates time.

Message flow <NUM> is associated with a first wait time duration. At <NUM>, a read request is received and at <NUM>, an address associated with the data to read is received. The wait timer is set with the wait time duration. The read command is issued to the non-volatile memory array and at <NUM>, a status polling performed at T1 after the wait timer indicates that the wait time duration has elapsed. A response to the status polling performed at T1 indicates that the read command has been completed. If execution of the read operation is complete, then the SSD controller requests that the non-volatile memory array provide the data to be read which is received at T2. An example of the request is shown as "<NUM>, Address, E0h" which results in data <NUM> being received.

If the wait time duration is increased, then the latency and performance of the SSD increases. Message flow <NUM> is associated with a second wait time duration longer than the first wait time duration. At <NUM>, a read request is received and at <NUM>, an address associated with the data to read is received. The wait timer is set with the wait time duration which is longer than the wait time duration described in the flow <NUM>. The read command is issued to the non-volatile memory array and at <NUM>, a status polling performed at T3 after the wait timer indicates that the wait time duration elapsed. T3 is after T1, indicating that the wait time is longer. A response to the status polling performed at T3 indicates that the read command has been completed. If execution of the read operation is complete, then the SSD controller requests that the non-volatile memory array provide the data to be read which is received at T4. An example of the request is shown as "<NUM>, Address, E0h" which results in data <NUM> being received.

In message flow <NUM>, the data is not received until T4 which is longer than T2 because the time associated with the wait time duration is longer. In this regard, a wait time duration associated with wait timer is directly related to a read time (tRead) and latency and/or throughput of reading data from the SSD. Similarly, a polling time duration associated with the status polling timer (not shown) is directly related to the latency and throughput of reading data from the SSD. For example, one or more status polling requests is sent to the non-volatile memory, each separated by a polling time duration until the read operation is complete. Further, the wait time duration and polling time duration are directly related to latency and throughput of writing and erasing data in the SSD.

<FIG> shows an example of how the performance of the SSD changes with a change of the wait time duration. The horizontal axis <NUM> shows the wait timer set to different wait time durations ranging from <NUM> microseconds to <NUM> microseconds for a read command. The axis <NUM> shows how latency in terms of data rate associated with128K sequential reads decreases as the wait time duration (also referred to as "delay to first status check") increases. The axis <NUM> shows how throughput in terms of kilo input output operations (klOPS) decreases as the wait time duration increases. This decrease becomes apparent generally after the wait time duration exceeds <NUM> microseconds. In this regard, adjusting the wait time duration allows for configuration of the latency and/or throughput of the SSD. Performance of the SSD similarly changes by setting the status polling timer to different polling time durations.

<FIG> is a block diagram of an example SSD controller <NUM> for controlling performance of the SSD. The SSD controller <NUM> includes a processor <NUM> (possibly including multiple processors, multiple cores, multiple nodes, and/or implementing multi-threading, etc.). The SSD controller <NUM> includes memory <NUM>. The memory <NUM> is system memory (e.g., one or more of cache, random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), zero capacitor RAM, Twin Transistor RAM, embedded DRAM (eDRAM), extended data output RAM (EDO RAM), double data rate RAM (DDR RAM), electrically erasable programmable read only memory (EEPROM), Nano-RAM (NRAM), resistive RAM (RRAM), silicon-oxide-nitride-oxide-silicon memory (SONOS), parameter random access memory (PRAM), etc.) or any one or more other possible realizations of non-transitory machine-readable media/medium. In examples, the memory <NUM> stores timer durations which are used to set the non-volatile memory timer. In examples, the stored timer durations is associated with different SSD configurations and/or different storage commands. The association facilitates identifying the timer duration associated with the current configuration of the SSD or storage access request being executed and setting the non-volatile memory timer with the identified timer duration. In some examples, the memory <NUM> includes registers to store an indication of a wait time duration and/or polling time duration for setting the wait timer and status polling timer.

The SSD controller <NUM> also includes a bus <NUM> (e.g., Peripheral Component Interconnect (PCI), Industry Standard Architecture (ISA), PCI-Express, New Bus (NuBus), etc.). Coupled to the bus <NUM> is interface <NUM> which facilitates communication with the non-volatile memory array of the SSD and the host. In this regard, the interface <NUM> includes the host interface and the non-volatile memory interface. The SSD controller <NUM> has a wait timer <NUM> and status polling timer <NUM>.

A timer control <NUM> of the SSD controller <NUM> implements any one of the previously described functionalities for setting the timers to control performance of the SSD partially, (or entirely) in hardware and/or software (e.g., computer code, program instructions, program code, computer instructions) stored on a non-transitory machine readable medium/media. In some instances, the processor <NUM> and memory <NUM> implements or facilitate implementing the functionalities instead of or in addition to the timer control <NUM>. Further, realizations can include fewer or additional components not illustrated in <FIG> (e.g., video cards, audio cards, additional network interfaces, peripheral devices, etc.). The processor <NUM> and the memory <NUM> are coupled to the bus <NUM>. Although illustrated as being coupled to the bus <NUM>, the memory <NUM> can be coupled to the processor <NUM>.

A few implementations have been described in detail above, and various modifications are possible. The disclosed subject matter, including the functional operations described in this specification, can be implemented in electronic circuitry, computer hardware, firmware, software, or in combinations of them, such as the structural means disclosed in this specification and structural equivalents thereof: including potentially a program operable to cause one or more data processing apparatus such as a processor to perform the operations described (such as a program encoded in a non-transitory computer-readable medium, which can be a memory device, a storage device, a machine-readable storage substrate, or other physical, machine readable medium, or a combination of one or more of them).

A program (also known as a computer program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program does not necessarily correspond to a file in a file system. A program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

While this specification contains many specifics, these should not be construed as limitations on the scope of what is claimed, but rather as descriptions of features that is specific to particular implementations. Moreover, although features is described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination is directed to a subcombination or variation of a subcombination.

Claim 1:
A method for controlling a time to execute a storage access request in a solid state drive, SSD, (<NUM>) to achieve a performance of the SSD similar to a performance of another SSD, the time being based on a configuration of the SSD (<NUM>) and on the performance of the another SSD (<NUM>), the SSD (<NUM>) having non-volatile memory and a controller (<NUM>), the method comprising:
storing in the controller (<NUM>) time values and associating the time values with different SSD (<NUM>) configurations;
receiving, by the controller (<NUM>), the storage access request to access the SSD (<NUM>);
setting, by the controller (<NUM>), a non-volatile memory access timer with a time duration which controls the time to execute the storage access request, wherein the time duration is defined by;
the performance of the other SSD, and
the configuration of the SSD (<NUM>), including setting the non-volatile memory access timer with a first time value of the time values stored in the controller (<NUM>) if the non-volatile memory of the SSD (<NUM>) is a NAND non-volatile memory, and setting the non-volatile memory access timer with a second time value stored in the controller (<NUM>) if the non-volatile memory of the SSD (<NUM>) is a NOR non-volatile memory;
sending, by the controller (<NUM>), a non-volatile memory command associated with the storage access request to the non-volatile memory;
starting, by the controller (<NUM>), the non-volatile memory access timer based on the non-volatile memory command being sent to the non-volatile memory;
after the non-volatile memory access timer indicates that the time duration elapsed determining, by the controller (<NUM>), whether or not the non-volatile memory completed execution of the non-volatile memory command;
if the non-volatile memory is determined to have completed execution of the non-volatile memory command, providing, by the controller (<NUM>), an indication that the storage access request is complete; and
if the non-volatile memory is determined not to have completed execution of the non-volatile memory command, repeating resetting, by the controller (<NUM>), the non-volatile memory access timer with the time duration and determining whether or not the non-volatile memory completed execution of the non-volatile memory command until the non-volatile memory completes the execution of the non-volatile memory command.