Patent Description:
The embodiments of the present disclosure relate to the technical field of semiconductor manufacturing, and particularly relate to a method for manufacturing a DRAM structure and the DRAM structure.

With the gradual development of the storage device technology, a Dynamic Random-Access Memory (DRAM) is gradually applied to various electronic devices due to its higher density and faster reading and writing speed. The DRAM includes a bit line structure, a capacitor structure and a transistor structure. The bit line structure and the capacitor structure are respectively connected with the transistor structure. The data stored in the capacitor structure is read through the control of the transistor structure.

However, at present, the performance of the DRAM still needs to be improved. Related technologies are known from <CIT>, <CIT> and <CIT>.

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings required for description in the embodiments or the prior art will be briefly described below. It is apparent that the drawings in the following description are some embodiments of the present disclosure. Those skilled in the art can also obtain other drawings according to these drawings without any creative work.

In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is apparent that the described embodiments are a part of the embodiments of the present disclosure, but are not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure.

This embodiment provides a method for manufacturing a DRAM structure and the DRAM structure to improve the performance of the semiconductor structure.

As shown in <FIG>, the method for manufacturing the semiconductor structure provided in this embodiment includes:.

The substrate serves as the basis of a subsequent film layer and can achieve a support effect on the subsequent film layer. Exemplarily, the material of the substrate can be a semiconductor material, including silicon, germanium, silicon germanium, etc. This embodiment does not limit the material of the substrate.

Referring to <FIG>, shallow trench isolation structures <NUM> and active region structures <NUM> arranged at intervals can be formed on the substrate (not shown), so as to facilitate the formation of a transistor structure.

After the substrate is formed, the method for manufacturing the semiconductor structure provided in this embodiment further includes:.

In S102, a plurality of bit line structures distributed at intervals are formed on the substrate, each of the bit line structures includes a conductive layer, a transition layer and a covering layer stacked sequentially, and the width of the transition layer is smaller than the width of the conductive layer.

Continuing to refer to <FIG>, a conductive layer <NUM>, a transition layer <NUM> and a covering layer <NUM> are stacked, the transition layer <NUM> is located between the covering layer <NUM> and the conductive layer <NUM>, and the conductive layer <NUM> is arranged close to the substrate. According to the claimed invention, the conductive layer <NUM> is connected with an active structure <NUM>. Exemplarily, the conductive layer <NUM> can be connected with a source electrode or a gate electrode of the active structure <NUM>.

The specific steps of forming the conductive layer <NUM> can include: as shown in <FIG>, a conductive initial layer <NUM> is formed. Exemplarily, a first conductive initial layer <NUM>, a conductive contact initial layer <NUM> and a second conductive initial layer <NUM> are sequentially stacked along a direction distal from the substrate. The conductive contact initial layer <NUM> is located between the first conductive initial layer <NUM> and the second conductive initial layer <NUM>. The conductive contact initial layer <NUM> can prevent the materials constituting the first conductive initial layer <NUM> and the second conductive initial layer <NUM> from permeating, and can also reduce the contact resistance between the first conductive initial layer <NUM> and the second conductive initial layer <NUM>. Exemplarily, the material of the first conductive initial layer <NUM> can include polysilicon, the material of the second conductive initial layer <NUM> can include tungsten, and the material of the conductive contact initial layer <NUM> can include titanium nitride or tungsten nitride.

According to the claimed invention, the width of the transition layer <NUM> is smaller than the width of the conductive layer <NUM> (taking the orientation shown in <FIG> as an example, the width is a size in a horizontal direction). After the conductive initial layer <NUM> is formed, a transition initial layer <NUM> and a covering initial layer <NUM> which are stacked are formed, and a mask layer <NUM> having a mask pattern is formed on the covering initial layer <NUM>. As shown in <FIG>, then the covering initial layer <NUM>, the transition initial layer <NUM> and the conductive initial layer <NUM> are etched by taking the mask layer <NUM> as a mask, so as to form the covering layer <NUM>, the transition layer <NUM> and the conductive layer <NUM>. At this time, the covering layer <NUM>, the transition layer <NUM> and the conductive layer <NUM> have the same width. After that, the transition layer <NUM> is etched horizontally to remove a portion of the transition layer <NUM> to form grooves <NUM>, such that the width of the finally formed transition layer <NUM> is smaller than the width of the conductive layer <NUM>. Exemplarily, a portion of the transition layer <NUM> can be removed by a wet process. In other examples, when the covering initial layer <NUM>, the transition initial layer <NUM> and the conductive initial layer <NUM> are etched by taking the mask layer <NUM> as a mask, a portion of the transition initial layer <NUM> that is partially located below the covering layer <NUM> is etched simultaneously, such that the width of the formed transition layer <NUM> is smaller than the width of the conductive layer <NUM>. Exemplarily, when the transition initial layer <NUM> is etched, the gas with a higher etching selection ratio of the transition initial layer <NUM> to the conductive initial layer <NUM> and the covering initial layer <NUM> can be selected for etching, and then, a portion of the transition initial layer <NUM> below the covering layer <NUM> is etched along a width direction, such that the width of the finally formed transition layer <NUM> is smaller than the width of the conductive layer <NUM>.

In this embodiment, a plurality of bit line structures <NUM> are distributed at intervals. Exemplarily, a plurality of bit line structures <NUM> extend in a line shape along a direction parallel to the substrate, a plurality of bit line structures <NUM> can be located in the same plane parallel to the substrate, and a plurality of bit line structures <NUM> are arranged in parallel and at intervals. Of course, the bit line structures <NUM> in this embodiment can also be distributed on the substrate in other forms, which is not limited in this embodiment.

After a plurality of bit line structures <NUM> distributed at intervals are formed, the method for manufacturing the semiconductor structure provided in this embodiment further includes:.

In S103, air gaps are formed on the top surface of the conductive layer and the side surfaces of the transition layer.

As shown in <FIG>, according to the claimed invention, the width of the transition layer <NUM> in the bit line structure <NUM> is smaller than the width of the conductive layer <NUM>, such that the bit line structure <NUM> forms grooves <NUM> on two sides of the transition layer <NUM> along a width direction. In order to form air gaps <NUM>, the bit line structure <NUM> can include insulation sealing layers <NUM> covering the side walls of the conductive layer <NUM> and the side walls of the covering layer <NUM>. At this time, the insulation sealing layers <NUM> seal the grooves <NUM> to form the air gaps <NUM> located on two sides of the transition layer <NUM> along the width direction.

Exemplarily, the insulation sealing layers <NUM> can be formed by CVD or ALD, and the grooves <NUM> are prevented from being filled with the insulation sealing layers <NUM> at the same time, such that the air gaps <NUM> are enclosed by the insulation sealing layers <NUM>, the conductive layer <NUM>, the transition layer <NUM> and the covering layer <NUM>.

Exemplarily, the material of the insulation sealing layer <NUM> can be the same as the material of the covering layer <NUM>. For example, the material of both the insulation sealing layer <NUM> and the covering layer <NUM> can be silicon nitride, silicon oxide, etc. Since the material of the insulation sealing layer <NUM> is the same as the material of the covering layer <NUM>, after the insulation sealing layers <NUM> are formed, the covering layer <NUM> and the insulation sealing layers <NUM> can be formed into an integrated structure to improve the strength of a coating layer <NUM>.

According to the method for manufacturing the semiconductor structure provided in this embodiment, a plurality of bit line structures <NUM> are distributed on the substrate, each of the bit line structures <NUM> includes a conductive layer <NUM>, a transition layer <NUM> and a covering layer <NUM> stacked sequentially, the width of the transition layer <NUM> is smaller than the width of the conductive layer <NUM>, and the air gaps <NUM> are formed on the top surface of the conductive layer <NUM> and the side surfaces of the transition layer <NUM>. By forming the air gaps <NUM> on the top surface of the conductive layer <NUM> and the side surfaces of the transition layer <NUM>, the influence of the covering layer <NUM> on the conductive layer <NUM> is reduced. For example, when the material of the covering layer <NUM> is silicon nitride and the material of the conductive layer <NUM> is tungsten, the existence of the air gaps <NUM> can reduce the degree to which nitrogen in the covering layer <NUM> migrates to the conductive layer <NUM> to nitride the conductive layer <NUM> to form tungsten nitride so as to prevent the resistance of the conductive layer <NUM> from increasing, and also can reduce the parasitic capacitance between the bit line structures <NUM> and the surrounding structures thereof, thereby improving the performance of the semiconductor structure.

In some embodiments, the width of the covering layer <NUM> can be greater than the width of the conductive layer <NUM>, and the formed air gaps <NUM> can protrude from the side surfaces of the conductive layer <NUM>. By such arrangement, the contact area between the air gaps <NUM> and the top surface of the conductive layer <NUM> can be increased to improve the protective effect on the top surface of the conductive layer <NUM>. At the same time, the volume of the air gaps <NUM> can be increased to further improve the parasitic capacitance between the bit line structures <NUM> and the surrounding structures (such as conductive plugs <NUM>).

Continuing to refer to <FIG>, the method for manufacturing the semiconductor structure provided in this embodiment further includes: a conductive plug <NUM> is formed on the substrate between the bit line structures <NUM>, the conductive plug <NUM> is located between adjacent bit line structures <NUM>, and the conductive plug <NUM> is used to connect the active region structure <NUM>. According to the claimed invention, the conductive plug <NUM> is also used to connect a capacitor storage structure.

Exemplarily, the conductive plug <NUM> includes a first conductive portion <NUM> and a second conductive portion <NUM> which are sequentially stacked along a direction perpendicular to the substrate. In other words, the second conductive portion <NUM> is located over the first conductive portion <NUM>, the first conductive portion <NUM> is connected with the active region structure <NUM>, and the second conductive portion <NUM> can be used to connect a capacitor. Exemplarily, the material of the first conductive portion <NUM> can include polysilicon, etc., and the material of the second conductive portion <NUM> can include tungsten, etc. In order to prevent the materials of the first conductive portion <NUM> and the second conductive portion <NUM> from permeating each other, a conductive barrier film can be arranged between the first conductive portion <NUM> and the second conductive portion <NUM>. The material of the conductive barrier film can include titanium nitride, etc..

The bottom portion of the second conductive portion <NUM> has an inclined surface <NUM> facing the bit line structure <NUM>.

According to the claimed invention, the bottom of the inclined surface <NUM> is higher than the top of the conductive layer <NUM>, and the top of the inclined surface <NUM> is lower than the top of the transition layer <NUM>, such that the top of the transition layer <NUM> is located between the top and bottom of the inclined surface <NUM>. At this time, the formed conductive layer <NUM> can be as high as possible and has smaller resistance.

Exemplarily, the bottom portion of the second conductive portion <NUM> further includes a bottom surface <NUM>, a first straight surface <NUM> and a second straight surface <NUM>. The bottom surface <NUM> is in direct contact with the top surface of the first conductive portion <NUM>, and two ends of the bottom surface <NUM> are respectively connected with the first straight surface <NUM> and the second straight surface <NUM>. The first straight surface <NUM> is also connected with the inclined surface <NUM>.

According to the claimed invention, the vertical distance between the top corner of the transition layer <NUM> and the inclined surface <NUM> is smaller than the vertical distance between the top corner of the conductive layer <NUM> and the inclined surface <NUM>. The top corner of the transition layer <NUM> is a first vertex a of the top end of the transition layer <NUM> close to the inclined surface <NUM> in a cross section perpendicular to the substrate and perpendicular to the extension direction of the bit line structure <NUM> (in the cross section as shown in <FIG>). The vertical distance between the top corner of the transition layer <NUM> and the inclined surface <NUM> is a vertical distance d1 between the first vertex a and the inclined surface <NUM>. Correspondingly, the top corner of the conductive layer <NUM> is a second vertex b of the top end of the conductive layer <NUM> close to the inclined surface <NUM> in a cross section perpendicular to the substrate and perpendicular to the extension direction of the bit line structure <NUM> (in the cross section as shown in <FIG>). The vertical distance between the top corner of the conductive layer <NUM> and the inclined surface <NUM> is a vertical distance d2 between the second vertex b and the inclined surface <NUM>.

In other examples not forming part of the claimed invention, the vertical distance d1 between the top corner of the transition layer <NUM> and the inclined surface <NUM> is greater than the vertical distance d2 between the top corner of the conductive layer <NUM> and the inclined surface <NUM>. By such arrangement, when the transition layer <NUM> is a conductor, the resistance of the bit line structure <NUM> can be reduced, and the parasitic capacitance between the bit line structure <NUM> and the conductive plug <NUM> can also be further reduced.

In some embodiments, the width of the transition layer <NUM> is <NUM>/<NUM> to <NUM>/<NUM> of the width of the conductive layer <NUM>. Such arrangement can reduce the influence of the covering layer <NUM> on the conductive layer <NUM>, ensure the supporting force for the covering layer <NUM>, and avoid the covering layer <NUM> collapsing due to a too small width of the transition layer <NUM>.

The material of the transition layer <NUM> provided in this embodiment can include metal-rich nitride (such as tungsten nitride, molybdenum nitride, titanium nitride, etc.) or metal-rich silicide (such as titanium silicide, tungsten silicide, etc.). By such arrangement, the metal-rich nitride and the metal-rich silicide can capture nitrogen atoms migrated from the covering layer <NUM> to the conductive layer <NUM>, so as to further avoid the influence of the conductive layer <NUM> on the covering layer <NUM> to prevent the resistance of the conductive layer <NUM> from increasing. Exemplarily, the metal-rich nitride means that the molar ratio of metal atoms to nitrogen atoms is greater than <NUM>, such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc., and the metal-rich silicide means that the molar ratio of metal atoms to silicon atoms is greater than <NUM>, such as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc..

Continuing to refer to <FIG>, this embodiment further provides a DRAM structure which can be manufactured by the method for manufacturing the semiconductor structure provided by any one of the above embodiments. Each of the bit line structures of the semiconductor structure includes a conductive layer <NUM>, a transition layer <NUM> and a covering layer <NUM> stacked sequentially. The width of the transition layer <NUM> is smaller than the width of the conductive layer <NUM>, and air gaps <NUM> are formed on the top surface of the conductive layer <NUM> and the side surfaces of the transition layer <NUM>. The transition layer <NUM> and the air gaps <NUM> reduce the influence of the covering layer <NUM> on the conductive layer <NUM> to prevent the resistance of the conductive layer <NUM> from increasing, thereby improving the performance of the semiconductor structure.

The semiconductor structure provided in this embodiment includes a substrate and a plurality of bit line structures distributed at intervals on the substrate. Each of the bit line structures includes a conductive layer <NUM>, a transition layer <NUM> and a covering layer <NUM> stacked sequentially. The width of the transition layer <NUM> is smaller than the width of the conductive layer <NUM>.

Exemplarily, the material of the substrate can include silicon, germanium, silicon germanium, etc. The material of the substrate is not limited in this embodiment. Shallow trench isolation structures <NUM> and active region structures <NUM> arranged at intervals can be formed on the substrate, so as to facilitate the formation of a transistor structure.

The conductive layer <NUM>, the transition layer <NUM> and the covering layer <NUM> are stacked, the transition layer <NUM> is located between the covering layer <NUM> and the conductive layer <NUM>, and the conductive layer <NUM> is arranged close to the substrate. The conductive layer <NUM> can include a first conductive layer <NUM>, a conductive contact layer <NUM> and a second conductive layer <NUM> which are sequentially stacked along a direction distal from the substrate. The conductive contact layer <NUM> is located between the first conductive layer <NUM> and the second conductive layer <NUM>, and the conductive contact layer <NUM> can prevent the materials constituting the first conductive layer <NUM> and the second conductive layer <NUM> from permeating. Exemplarily, the material of the first conductive layer <NUM> can include polysilicon, the material of the second conductive layer <NUM> can include tungsten, and the material of the conductive contact layer <NUM> can include titanium nitride.

In this embodiment, a plurality of bit line structures are distributed at intervals. Exemplarily, a plurality of bit line structures extend in a line shape along a direction parallel to the substrate, a plurality of bit line structures can be located in the same plane parallel to the substrate, and a plurality of bit line structures are arranged in parallel and at intervals. Of course, the bit line structures in this embodiment can also be distributed on the substrate in other forms, which is not limited in this embodiment.

Continuing to refer to <FIG>, the air gaps <NUM> are located on the top surface of the conductive layer <NUM> and the side surfaces of the transition layer <NUM>. In other words, the air gaps <NUM> are formed between the side surfaces of the transition layer <NUM> and the top surface of the conductive layer <NUM>.

In some implementation manners, a coating layer <NUM> can include a covering layer <NUM> located at the upper portion of the transition layer <NUM> and insulation sealing layers <NUM> covering the side walls of the covering layer <NUM> and the side walls of the conductive layer <NUM>. Since the width of the transition layer <NUM> is smaller than the width of the conductive layer <NUM>, grooves can be formed on two sides of the transition layer <NUM>. After the insulation sealing layers are formed, the insulation sealing layers <NUM> cover the grooves to form the air gaps <NUM>.

In some embodiments, the width of the covering layer <NUM> is greater than the width of the conductive layer <NUM>.

In some embodiments, the air gaps <NUM> protrude from the side surfaces of the conductive layer <NUM>, that is, the air gaps <NUM> protrude outward from the side surfaces of the conductive layer <NUM>. By such arrangement, the contact area between the air gaps <NUM> and the top surface of the conductive layer <NUM> can be increased to improve the protection effect on the top surface of the conductive layer <NUM>. At the same time, the volume of the air gaps <NUM> can be increased to further improve the parasitic capacitance between the bit line structures <NUM> and the surrounding structures (such as conductive plugs <NUM>).

Continuing to refer to <FIG>, the semiconductor structure provided in this embodiment further includes conductive plugs <NUM> located between the bit line structures, each of the conductive plugs <NUM> is located between adjacent bit line structures <NUM>, and the conductive plug <NUM> is used to connect the active region structure <NUM>. According to the claimed invention, the conductive plug <NUM> is also used to connect a capacitor storage structure.

Exemplarily, the conductive plug <NUM> includes a first conductive portion <NUM> and a second conductive portion <NUM> which are sequentially stacked along a direction perpendicular to the substrate. In other words, the second conductive portion <NUM> is located over the first conductive portion <NUM>, the first conductive portion <NUM> is connected with the active region structure <NUM>, and the second conductive portion <NUM> is used to connect a capacitor storage structure. Exemplarily, the material of the first conductive portion <NUM> can include polysilicon, etc., and the material of the second conductive portion <NUM> can include tungsten, etc. In order to prevent the materials of the first conductive portion <NUM> and the second conductive portion <NUM> from permeating each other, a conductive barrier film can be arranged between the first conductive portion <NUM> and the second conductive portion <NUM>. The material of the conductive barrier film can include titanium nitride, etc..

The bottom portion of the second conductive portion <NUM> has an inclined surface <NUM> facing the bit line structure <NUM>, and the bottom of the inclined surface <NUM> is higher than the top of the conductive layer <NUM> and lower than the top of the transition layer <NUM>, such that the top of the transition layer <NUM> is located between the top and bottom of the inclined surface <NUM>.

Exemplarily, the bottom portion of the second conductive portion further includes a bottom surface <NUM>, a first straight surface <NUM> and a second straight surface <NUM>. The bottom surface <NUM> is in direct contact with the top surface of the first conductive portion <NUM>, and two ends of the bottom surface <NUM> are respectively connected with the first straight surface <NUM> and the second straight surface <NUM>. The first straight surface <NUM> is also connected with the inclined surface <NUM>. By the arrangement of the first straight surface <NUM> and the second straight surface <NUM>, the distance between the transition layer <NUM> and the second conductive portion <NUM> of the conductive plug <NUM> can be further increased to reduce the parasitic capacitance between the two, and at the same time, short circuit defects can be reduced to improve the yield.

In some embodimnets, the width of the transition layer <NUM> is <NUM>/<NUM> to <NUM>/<NUM> of the width of the conductive layer <NUM>. Such arrangement can reduce the influence of the covering layer <NUM> on the conductive layer <NUM>, ensure the supporting force for the covering layer <NUM>, and avoid the covering layer <NUM> collapsing due to a too small width of the transition layer <NUM>.

Claim 1:
A method for manufacturing a DRAM structure, comprising:
providing (S101) a substrate;
forming (S102) a plurality of bit line structures (<NUM>) distributed at intervals on the substrate, each of the bit line structures comprising a conductive layer (<NUM>), a transition layer (<NUM>) and a covering layer (<NUM>) stacked sequentially, and a width of the transition layer being smaller than a width of the conductive layer, the conductive layer being connected with an active structure (<NUM>) of a transistor structure;
forming (S103) air gaps (<NUM>) on a top surface of the conductive layer and side surfaces of the transition layer; and
forming a conductive plug (<NUM>) comprising a first conductive portion (<NUM>) and a second conductive portion (<NUM>) on the substrate between the bit line structures, and forming the second conductive portion over the first conductive portion, the conductive plug configured to be connected to a capacitor storage structure,
characterized in that
a bottom portion of the second conductive portion has an inclined surface (<NUM>) facing the bit line structure,
a vertical distance between a top corner of the transition layer and the inclined surface is smaller than a vertical distance between a top corner of the conductive layer and the inclined surface, and
a bottom of the inclined surface is higher than a top of the conductive layer and lower than a top of the transition layer.