Patent Description:
Ge-on-Si microelectronic devices (e.g. diodes and transistors) and optoelectronic devices (e.g. photodiodes) are known. The high carrier mobility in Ge compared to that in Si is advantageous for high-speed electronics. Furthermore, the ability of Ge to absorb light in the infrared band of <NUM> to <NUM> (also referred to as the short wave infrared or "SWIR" band) led to the development of Ge-based devices on the telecommunication and infrared (IR) imaging markets. With the development of various epitaxial Ge deposition/growth methods such as chemical vapor deposition (CVD), an interest in the integration of Ge materials in complementary metal oxide semiconductor (CMOS) circuit technology has developed.

In CVD of Ge on Si, due to high lattice mismatch of around <NUM>% between Si and Ge, the surface tension causes the Ge lattice to develop high a treading dislocation density (TDD), which degrades device performance. Various methods to suppress the high TDD during growth have been proposed. Known methods include growing a graded buffer layer of SixGe<NUM>-x alloy material between the Ge and the Si, varying Ge growth parameters, and using a Ge seed layer. The latter involves the patterning and etching of an insulator (e.g. a SiO<NUM> layer) that covers the silicon substrate, exposing only small portion of the Si wafer (defined as "seed region") to the CVD growth of Ge seed-like structures. The patterning and etching of the SiO<NUM> causes epitaxial lateral overgrowth of Ge layers outside of the Ge seed area. As the threading dislocations are not parallel to the growth direction, this process forces them to glide from the Si/Ge interface to the edge of the oxide, and to annihilate them in the seed region, allowing the Ge overgrowth to be relatively free from threading dislocations. This in turn enhances the electrical properties of the device.

The use of variously known techniques as above still leaves Ge-on-Si devices with leakage (or "parasitic") currents that diminish device performance. When the seed is grown directly on the Si wafer, there is no barrier for carrier movement from the Si to the seed and vice versa, and thus there is carrier transport in the seed. In many Ge devices formed on a Si carrier wafer, the Si carrier wafer is biased to ground and a leakage of carriers can be transported through the seed into the Ge layer and can be measured as an undesired transport current.

Therefor there is a need for, and it would be advantageous to have structures and methods that minimize or completely block the leakage current and which separate electrically the Si and Ge layers in Ge-on-Si photo-devices.

<NPL>, , discloses: In order to facilitate the integration of photonic systems onto an electronic chip, near infrared photodiodes utilizing novel materials such as germanium must be monolithically integrated onto the Si CMOS platform. Such near-infrared photodiodes can be utilized for a plethora of applications such as optoelectronic ADCs, optical interconnects, photonic integrated circuits, and near infrared cameras. In this work, the maj or focus is on investigating processes utilizing a Low Pressure Chemical Vapor Deposition (LPCVD) Applied Materials Epi CenturaTM system to deposit germanium onto silicon substrates (Ge-on-Si). A growth space is identified to deposit blanket and selective epitaxial <NUM> to <NUM> rim-thick Ge-on-Si films via a two-step process. These deposited Ge-on-Si films have a low root-mean-square surface roughness (below <NUM>) and a moderate threading dislocation density (- <NUM>-<NUM>) after an annealing process. Utilizing these Ge-on-Si films, vertically illuminated Ge-on-Si pin photodiodes are fabricated in a CMOS compatible process. The best photodiodes fabricated in this work have low dark current values (below <NUM> mA/cm2), high responsivity (- <NUM> A/W at <NUM> pim wavelengths) and <NUM>-dB frequency response in the gigahertz range. Due to the importance of the photodiode reverse bias leakage current for circuit applications, the reverse bias leakage current is investigated and characterized in detail for various Ge-on-Si pin photodiodes. Trap assisted tunneling was found to be the dominant reverse bias leakage mechanism. These Ge-on-Si films show great promise for leveraging the integration of photonic devices onto the Very Large Scale Integration (VLSI) platform, and once there is improved reproducibility in the fabrication process, specifically the passivation of germanium surface states, the promise of these Ge-on-Si films can be fully realized. (Abstract).

Embodiments disclosed herein teach structures that block leakage currents at the Ge/Si seed interface and separate electrically the Ge layer for the Si substrate (wafer), and methods for their formation and use. In an embodiment, the Si substrate is doped locally prior to Ge epitaxial layer growth (in an area to be referred to henceforth as a "locally doped Si region"). The local doping is of opposite type to that of the Si substrate as well as to that of the Ge seed. For example, if the Si substrate and the Ge seed are N doped, then the locally doped Si region is P doped. For example, if the Si substrate and the Ge seed are P doped, then the locally doped Si region is N doped. The doping in the Ge seed and the intermediate layer may be uniform or non-uniform (varying). The structure formed locally (in the Ge seed area) is thus similar to that of a bipolar junction transistor (BJT) with two "back-to-back" (or "head-to-head") diodes. That is, this "local" structure in the Ge seed area includes a PN (or NP) junction connected to a NP (or PN) junction in series. When a voltage is applied between the seed layer and the substrate (and through the locally doped Si region), it reduces the barrier of one junction but increases the barrier of the other junction, resulting in current blocking. Consequently, the undesired leakage current can be reduced, especially when the Ge epitaxial layer is designed to be part of an optoelectronic component such as a photodiode (PD), in which the leakage current is a "dark" current that needs to be reduced as much as possible. The advantage of this structure and its method of use is in the reduced sensitivity of the dark current on voltage polarity, where there is always one junction in reverse bias mode, in contrast with a single standard PN junction where the behavior of the junction is less controlled and where the energy barrier depends on the voltage polarity.

In the invention, there are provided semiconductor structures in the form of photodiodes comprising: a Si substrate, a Ge seed layer and a Ge epitaxial layer separated by respective interfaces that share a common plane normal, wherein the Si substrate and the Ge seed layer have a same first doping type with a first doping level; a locally doped region formed in the Si layer adjacent to the Ge seed layer and having a second doping type with a second doping level, wherein the locally doped region is designed to reduce leakage currents between the Si substrate and the Ge epitaxial layer when an electrical bias is applied to the structure; a third doped region having the second doping type formed in the Ge epitaxial layer at a top surface of the Ge epitaxial layer and above the Ge seed layer;.

In the invention, there are also provided methods comprising: forming a photodiode comprising a Si substrate, a Ge seed layer and a Ge epitaxial layer separated by respective interfaces that share a common plane normal, wherein the Si substrate and the Ge seed layer have a same first doping type with a first doping level; and a locally doped region formed in the Si layer adjacent to the Ge seed layer and having a second doping type with a second doping level, wherein the locally doped region is designed to reduce leakage currents between the Si substrate and the Ge epitaxial layer when an electrical bias is applied to the photodiode, forming a third doped region having the second doping type in the Ge epitaxial layer at a top surface of the Ge epitaxial layer and above the Ge seed layer, and fourth doped regions having the first doping type with a third doping level being higher than the first doping level in the Ge epitaxial layer at the top surface of the Ge epitaxial layer and on the side of the third doping region, and positioning an electrical contact on the third doped region and electrical contacts on each fourth doped region to form biasing means for the photodiode.

In some embodiments, a method further comprises forming biasing means for applying the electrical bias between the Si substrate and the Ge epitaxial layer.

In some of the structures and optoelectronic devices, the first doping type is n-type and wherein the second doping type is p-type.

In some of the structures and optoelectronic devices, the first doping type is p-type and wherein the second doping type is n-type.

In some of the structures and optoelectronic devices, the Ge epitaxial layer has a doping type that is the same as the first doping type.

In some of the structures and optoelectronic devices, the Ge epitaxial layer has intrinsic doping.

In some of the structures and optoelectronic devices, the second doping level is higher than the first doping level.

In general, optoelectronic devices disclosed herein are useful for light detection in the SWIR range.

Non-limiting examples of embodiments disclosed herein are described below with reference to figures attached hereto that are listed following this paragraph. The drawings and descriptions are meant to illuminate and clarify embodiments disclosed herein, and should not be considered limiting in any way. Like elements in different drawings may be indicated by like numerals. Elements in the drawings are not necessarily drawn to scale. In the drawings:.

Embodiments disclosed herein teach inventive leakage-reducing structures, methods of fabricating such structures in the Ge-Si material system, and photo-devices based on such structures. The structures include certain doping profiles through a Ge seed layer and the underlying Si substrate. In general, this simple, highly efficient and low-cost method can be used when using a Ge seed and lateral overgrowth epitaxy on a Si substrate.

Referring now to the drawings, <FIG> illustrates schematically in a side view an embodiment of a Ge/locally doped Si/Si substrate structure numbered 100a disclosed herein. <FIG> illustrates schematically in a side view an embodiment of a Ge/locally doped Si/Si substrate structure numbered 100b disclosed herein. Structure 100a includes a Si substrate (or "layer") <NUM>, a Ge seed layer <NUM> grown in an opening (e.g. etched region) of an insulator (dielectric) layer (e.g. SiO<NUM>) <NUM> and a Ge epitaxial layer <NUM> laterally overgrown from the seed over the insulator layer to form a Ge-on-Si structure. Layer <NUM> is separated from layer <NUM> (and insulator <NUM>) by an interface <NUM> and layer <NUM> (and insulator <NUM>) is separated from layer <NUM> by an interface <NUM>. Interfaces <NUM> and <NUM> share a plane normal "n". Structure 100a further includes locally, in a region marked by an oval <NUM>, a locally n-doped doped Si region <NUM>. In a vertical (Y according to the exemplary coordinate system) direction, oval <NUM> marks a structure comprising Ge seed <NUM> (and epitaxial layer <NUM>) doped p-type, locally n-type doped Si region <NUM> and Si substrate <NUM> doped p-type. Therefore, the structure marked by oval <NUM> may be referred to as PNP structure <NUM>.

Similarly, structure 100b has in a region marked by an oval <NUM>' (also referred to as "locally doped region") and in a vertical (Y) direction, a NPN structure comprising Ge seed <NUM> (and epitaxial layer <NUM>) doped n-type, a locally Si region <NUM>' doped p-type and Si substrate <NUM> doped n-type. Therefore, the structure marked by oval <NUM>' may be referred to as NPN structure <NUM>'.

PNP structure <NUM> may be obtained for example as follows: starting with a p-type Si substrate <NUM>, an intrinsic or doped Ge layer <NUM> is overgrown over insulator <NUM> from an p-type Ge seed layer <NUM>. The p-type doping of the seed is formed using, for example, an in-situ doping method. The seed pattern is defined using standard lithography and etching in the dielectric layer. Prior to the Ge layer growth, locally n-type doped region <NUM> is formed in Si substrate <NUM> at the interface between the Ge seed and the Si wafer, for example, by ion implantation or diffusion. Given the ion implantation or diffusion conditions, the resulting doping profile of region <NUM> is known. An exemplary profile can be seen in <FIG>.

NPN structure <NUM>' may be similarly obtained for example as follows: starting with a n-type Si substrate <NUM>, an intrinsic or doped Ge layer <NUM> is overgrown over insulator <NUM> from a n-type Ge seed layer <NUM>. The n-type doping of the seed is formed using, for example, an in-situ doping method. The seed pattern is defined using standard lithography and etching in the dielectric layer. Prior to the Ge layer growth, locally p-type doped region <NUM>' is formed in Si substrate <NUM> at the interface between the Ge seed and the Si wafer, for example, by ion implantation or diffusion. Given the ion implantation or diffusion conditions, the resulting doping profile of region <NUM>' is known. An exemplary profile can be seen in <FIG>.

The doping levels (dopant concentrations) of the layers in PNP structure <NUM> or NPN structure <NUM>' may vary as follows: the doping (P or N) of the Si substrate may vary between <NUM>×<NUM><NUM> cm-<NUM> and <NUM>×<NUM><NUM> cm-<NUM>, the doping (N or P) of locally doped region <NUM> or <NUM>' may vary between <NUM>×<NUM><NUM> cm-<NUM> and 1x <NUM><NUM> cm-<NUM>and the doping (P or N) of the Ge seed may vary between <NUM>×<NUM><NUM> cm-<NUM> and <NUM>×<NUM><NUM> cm-<NUM>. In a non-limiting example, the locally doped region thickness may be about <NUM>.

In a particular and non-limiting example of a PNP structure <NUM>, Si substrate <NUM> may be p-type doped with boron to a level of about <NUM>×<NUM><NUM> cm-<NUM>, locally doped Si region <NUM> may be n-type doped with phosphor or arsenic to a level of about <NUM>×<NUM><NUM> cm-<NUM> and Ge seed <NUM> may be p-type doped with boron, gallium or aluminum to about a level of <NUM>×<NUM><NUM> cm-<NUM>.

In a particular and non-limiting example of a NPN structure <NUM>, Si substrate <NUM> may be n-type doped with arsenic or phosphor to a level of about <NUM>×<NUM><NUM> cm-<NUM>, locally doped Si region <NUM> may be p-type doped with boron, gallium or aluminum to a level of about <NUM>×<NUM><NUM> cm-<NUM> and Ge seed <NUM> may be n-type doped with arsenic or phosphor to about a level of <NUM>×<NUM><NUM> cm-<NUM>.

<FIG> illustrates schematically an energy band profile of the PNP structure in <FIG>, and <FIG> illustrates schematically an energy band profile of the NPN structure in <FIG>. The energy bands are similar to those of heterojunction BJTs, except in this case a BJT structure is formed only locally in the Ge seed region and the Si substrate. The term "substrate/seed interface" in these figures is equivalent to the "locally doped region" mentioned above and below. The resulting band structure is instrumental for reducing the leakage current through the seed layer into the Si substrate by forming two opposite PN junctions. Specifically, there will always be an energy barrier for the carriers such that the carriers cannot be transported from the Ge seed to the silicon substrate and vice versa. This is true for zero bias between the silicon substrate and the Ge seedas well as for a between bias the silicon and the Ge seed. The voltage drops on such a structure always have one junction in reverse bias mode, a feature used to block unnecessary leakage current.

<FIG> illustrates simulated transport current through an example of a PNP structure like structure 100a. The structure is doped as follows: The Si substrate is p-type doped to a level of <NUM>×<NUM><NUM>cm-<NUM>, the locally doped Si region is n-type doped to a level of <NUM>×<NUM><NUM>cm-<NUM>, and the Ge seed is p-type doped to a level of <NUM>×<NUM><NUM>cm-<NUM>. The obtained current is compared to that of a Si/Ge PN junction consisting of p-type Si (doping of <NUM>×<NUM><NUM>cm-<NUM>) and n-type Ge region having doping of <NUM>×<NUM><NUM>cm-<NUM>. The simulated current through the PNP device shows reduced leakage current. For example, for a positive voltage (bias) of <NUM>. 1V, there is reduction of almost <NUM> orders of magnitude in the leakage current. Bias" refers to the difference in electric potential between the Ge and the Si substrate. For a positive <NUM>. 5V bias, the reduction is even higher, about <NUM> orders of magnitude. For a negative bias of -<NUM>. 1V there is improvement of about <NUM> orders of magnitude. For a higher negative bias of about -<NUM>. 3V the improvement becomes negligible.

Moreover, if the seed (<NUM>) and the substrate (<NUM>) have the same level of doping without the additional layer (i.e. without the locally doped region <NUM> or <NUM>'), e.g. pp or nn doping, the leakage current through the seed is expected to be higher and will most likely reduce the device performance.

<FIG> shows a flow diagram of an exemplary and non-limiting embodiment of a process (method) for fabricating a structure such as 100a or 100b with a desired local PNP or NPN doping profile. The process starts at step <NUM> with a preconditioned doped Si substrate (also referred to as "layer") serving as the carrier wafer for the epitaxy growth process. The preconditioning can include for example cleaning or adding a protection layer. A dielectric (insulator) layer, for example SiO<NUM>, is deposited on the Si wafer in step <NUM>. A standard lithography process defines a window in the dielectric layer in step <NUM> and the window is etched into the dielectric layer all the way through the dielectric layer to reach the Si wafer in step <NUM>. An ion implantation process followed by dopant activation (e.g. using rapid thermal annealing or diffusion) is used to form the locally doped region <NUM> or <NUM>' in the silicon in step <NUM>. The doping type is opposite to the doping of the Si wafer. For example, in a PNP structure, starting with a Si wafer doped to a level of <NUM>×<NUM><NUM>cm-<NUM> with boron, the n-type locally doped region may be formed by implantation of phosphor at <NUM> KV and dose of <NUM>×<NUM><NUM> ions/cm<NUM>, followed by diffusion of about <NUM> minutes at <NUM>° C. Subsequently, in step <NUM>, the Ge seed is grown in the window with in-situ doping identical to that of the Si wafer. The in-situ doping provides a uniformly doped seed layer. Finally, an intrinsic or doped Ge epitaxial layer <NUM> is overgrown over the insulator from the seed in step <NUM>.

<FIG> shows an exemplary photodiode numbered <NUM> fabricated in a structure of Ge grown on a Si substrate by the seed layer technique. The structure is similar to that in <FIG>, with the addition of a n-doped region <NUM>, p+ doped regions <NUM> and electrical contacts <NUM> and <NUM>, which form exemplary biasing means for the PD. Light can arrive in both back-side illumination or frontside illumination, as shown. In general, the direction of the light entering the PD is substantially parallel to the Y axis, up to an acceptance angle of optics (not shown) coupled to the PD.

Photodiodes like PD <NUM> can be formed as (arranged in) an array (not shown), and be integrated with a standard read out circuitry (ROIC) to form a CMOS type imager.

It should be understood that where the claims or specification refer to "a" or "an" element, such reference is not to be construed as there being only one of that element.

Claim 1:
A semiconductor structure in the form of a photodiode, comprising:
a silicon (Si) substrate (<NUM>), a Germanium (Ge) seed layer (<NUM>) on the Si substrate and separated from the Si substrate by a first interface (<NUM>), and a Ge epitaxial layer (<NUM>) on the Ge seed layer and separated from the Ge seed layer by a second interface (<NUM>), the first and second interfaces sharing a common plane normal (n), wherein the Si substrate and the Ge seed layer have a same first doping type with a first doping level;
a locally doped region (<NUM>) formed in the Si substrate adjacent to the Ge seed layer and having a second doping type with a second doping level, wherein the locally doped region is designed to reduce leakage currents between the Si substrate and the Ge epitaxial layer when an electrical bias is applied to the structure;
a third doped region (<NUM>) having the second doping type and formed in the Ge epitaxial layer at a top surface of the Ge epitaxial layer and above the Ge seed layer;
fourth doped regions (<NUM>) having the first doping type with a third doping level being higher than the first doping level and formed in the Ge epitaxial layer at the top surface of the Ge epitaxial layer and on the side of the third doping region (<NUM>); and
an electrical contact (<NUM>) positioned on the third doped region and an electrical contact (<NUM>) positioned on each fourth doped region, the electrical contacts (<NUM>, <NUM>) forming means for the photodiode.