Patent Description:
Integrated circuit devices communicate with one another using input/output (I/O) circuits that are configured to transmit and receive multi-bit data over a plurality of signal lines. When multiple output drivers on the circuits change state at the same time at a high speed to transmit the multi-bit data, the changing current drawn from a power supply by the output drivers induces a voltage that results in power supply disturbance, commonly referred to as simultaneous switching output ("SSO") noise (or simultaneous switching noise ("SSN)). SSN can cause undesired transient behavior among the output drivers, input receivers or internal logic on the circuits.

<CIT> discloses a circuit, comprising an encoder configured to receive data and to generate encoded data. The encoded data are transmitted together with a strobe signal that in a first state indicating that the receiver shall ignore the transmitted data while in a second state indicating that the receiver shall not ignore the transmitted data. The encoded data are also transmitted together with a data mask signal, the encoder configured to encode a first subset of the data with data bus inversion when the data mask signal is in a first state and a second subset of the data with no inversion when the data mask signal is in a second state.

Techniques used for reducing SSN on parallel links include data bus inversion (DBI), also referred to as dynamic bus inversion. DBI inverts some of the multi-bit data to be transferred based on the previous bits transmitted over the parallel communication link, for example, to reduce SSN by decreasing the number of transmitter switching transitions that occur across the link.

A data mask (dm) signal is used by one circuit to indicate to another circuit that the data sent by the one circuit should be disregarded by the other circuit. For example, the data mask signal may be used by a memory controller to indicate to a memory device that the data transmitted by the memory controller to the memory device should be ignored. The data mask signal can be a voltage level on a pin of the memory controller integrated circuit or part of a command transmitted between the memory controller and the memory device.

Embodiments of the present disclosure include a data encoding scheme for transmission of data from one circuit to another circuit that combines DBI encoding and non-DBI encoding and uses a data mask signal to indicate the type of encoding used. Here, the term "non-DBI encoding" is used to refer to any encoding scheme that is different from DBI. The data mask signal in a first state indicates that the data transmitted from one circuit to said another circuit is to be ignored, and the data mask signal in a second state indicates that the data transmitted from one circuit to said another circuit is not to be ignored. If the data mask signal is in the second state, a first subset of the data is encoded with data bus inversion and a second subset of the data is encoded differently from data bus inversion. The encoding scheme according to the embodiments described herein has the advantage that SSO noise can be dramatically reduced when the encoded data is transmitted from one circuit to another circuit.

Reference will now be made to several embodiments of the present disclosure, examples of which are illustrated in the accompanying figures. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.

<FIG> illustrates a system including an encoder and decoder capable of coding and decoding data, according to one embodiment. The system of <FIG> includes two circuits communicating with each other on a parallel communication link <NUM>. For example, circuit <NUM> may be a memory controller, and circuit <NUM> may be a memory device such as a DRAM or SRAM. However, circuits <NUM>, <NUM> may be other types of circuits communicating data between each other.

The parallel communication link <NUM> may be a bus on a circuit board on which the circuits <NUM>, <NUM> reside, and has a data width (n+<NUM> bits) larger than the number of bits (n bits) of data Dn to be transmitted from memory controller <NUM> to memory device <NUM>. Here, n is a positive integer greater than one (n > <NUM>). The n-bit data Dn have varying Hamming Weights (HWs) depending upon the number of logic level "<NUM>"s in the n-bit data Dn. Here, Hamming Weight refers to the number of non-zero (i.e., logic level "<NUM>") bits in the n-bit data Dn. Although the link <NUM> is shown herein as a single-ended parallel communication link, note that link <NUM> can also be a link configured to transmit differential signals or multi-wire signals.

Memory controller <NUM> includes an encoder <NUM> and a transmitter (Tx) <NUM>. Data Dn can be provided to encoder <NUM> as, for example, serial or parallel data. Memory device <NUM> also includes decoder <NUM> and a receiver (Rx) <NUM>. In addition, memory device <NUM> may also include another encoder and a transmitter for transmitting encoded data to memory controller <NUM>, and memory controller <NUM> may also include a receiver and a decoder for receiving and decoding the encoded data received from memory device <NUM>. However, the encoder and transmitter of memory device <NUM> and the receiver and decoder of memory controller <NUM> are not shown in <FIG> as they are not necessary for explaining the embodiments of the present disclosure.

Encoder <NUM> receives the n-bit data Dn and a <NUM>-bit data mask signal (dm) from other circuits (not shown) or other circuit components (e.g., state machines, not shown) within memory controller <NUM>. As explained above, the data mask signal (dm) is used for memory controller <NUM> to indicate to memory device <NUM> to ignore the data received from memory controller <NUM> (i.e., to indicate no-write operation). The dm signal can be a voltage level on a pin, which is offset or accompanies data being sent from the memory controller <NUM> to the memory device. Alternatively, masking information conveyed by the dm signal may be included as part of a command transmitted between the memory controller <NUM> and the memory device <NUM>, and thus no physical data mask signal dm need be present on the parallel link <NUM>. Encoder <NUM> includes combinatorial logic gates or look-up tables (LUTs) that are configured to perform encoding of the n-bit data Dn it receives to convert the n-bit data to n-bit encoded data DQn and a DBI bit (<NUM>-bit). Encoder <NUM> also converts the data mask (dm) signal to a modified data mask (DM) signal. As will be explained in more detail below with reference to <FIG> and <FIG>, encoder <NUM> uses DBI encoding in some instances of the n-bit data Dn and non-DBI encoding in other instances of the n-bit data Dn to encode the n-bit data Dn, depending upon the Hamming Weights of the n-bit data Dn. Encoder <NUM> also generates the modified data mask signal (DM) to indicate to memory device <NUM> the type of encoding used in the n-bit encoded data DQn in those different instances.

In addition, encoder <NUM> also receives a mode signal <NUM>. In one embodiment, when mode signal <NUM> is asserted (e.g., logic high), encoder <NUM> encodes the n-bit data Dn using the encoding scheme according to the embodiments of the present disclosure as described herein. When mode signal <NUM> is not asserted (e.g., logic low), encoder <NUM> uses DBI encoding (that is independent of the use of masking information) to encode the n-bit data Dn.

In an embodiment, transmitter (Tx) <NUM> transmits the encoded data DQn, DBI bit, and the DM bit over the parallel link <NUM> to the receiver (Rx) <NUM> of memory device <NUM>. In doing so, transmitter (Tx) <NUM> draws supply current Idd from a power supply (not shown) providing the supply voltage (Vdd), consuming power from the power supply and generating SSO noise. However, the SSO noise generated by transmitter (Tx) <NUM> can be reduced according to the embodiments of the present disclosure.

In an embodiment, receiver <NUM> receives the encoded data DQn, DBI bit, and the DM bit over the parallel link <NUM> from memory controller <NUM>. In doing so, receiver <NUM> also draws supply current Idd from a power supply (not shown) providing the supply voltage (Vdd), consuming power from the power supply and generating SSO noise. Again, the SSO noise generated by receiver (Rx) <NUM> can be reduced according to the embodiments of the present disclosure.

Receiver <NUM> provides the received encoded data DQn, DBI bit, and the DM bit to decoder <NUM>. Decoder <NUM> decodes the encoded data DQn and DBI bit back to n-bit data Dn and converts the modified data mask signal (DM) back to the data mask signal (dm), as will be explained in more detail below with reference to <FIG> and <FIG>.

In addition, decoder <NUM> also receives a mode signal <NUM>. In one embodiment, when mode signal <NUM> is asserted (e.g., logic high), decoder <NUM> decodes the n-bit encoded data DQn using the decoding scheme according to the embodiments of the present disclosure as described herein. When mode signal <NUM> is not asserted (i.e., logic low), decoder logic <NUM> uses DBI decoding (that is independent of the use of masking information) to decode the n-bit encoded data DQn.

<FIG> is a flow chart illustrating a method of encoding data, according to one embodiment. According to the encoding scheme of the embodiment of <FIG>, a combination of DBI encoding and non-DBI encoding is used to encode the n-bit data Dn depending upon the Hamming Weight of the n-bit data Dn. i.e., the number of non-zero (i.e., logic level "<NUM>") bits in the n-bit data Dn.

First, it is determined <NUM> whether the data mask signal (dm) is asserted (in this example "<NUM>" or logic high). If the data mask signal (dm) is asserted, the n-bit data Dn is encoded such that the n+<NUM> bit encoded data [DBI, DQn] is a predetermined (n+<NUM>)-bit data pattern (DQM) indicative of a mask signal to memory device <NUM>. Also, the modified data mask signal (DM) is set to "<NUM>" or logic high. On the other hand, if the data mask signal (dm) is not asserted ("<NUM>" or logic low), then it is further determined <NUM> whether the n-bit data Dn, when DBI encoded, has a Hamming Weight lower than a predetermined threshold. In other words, in step <NUM> it is further determined whether the uncoded n-bit data Dn has a Hamming Weight lower than a first predetermined threshold or higher than a second predetermined threshold. For example, when Dn is <NUM>-bit data, a threshold of Hamming Weight <NUM> may be used such that the <NUM>-bit data Dn is considered low Hamming Weight data if the <NUM>-bit data Dn, when DBI encoded, has Hamming Weight lower than <NUM> (i.e., HW of DBI-encoded Dn is <NUM>, <NUM>, <NUM>, or <NUM>), i.e., when the uncoded <NUM>-bit data Dn has Hamming Weight lower than <NUM> (i.e., HW of uncoded Dn is <NUM>, <NUM>, <NUM>, or <NUM>) or higher than <NUM> (i.e., HW of uncoded Dn is <NUM>, <NUM>, or <NUM>).

If the DBI-encoded n-bit data Dn is not low Hamming Weight data in step <NUM>, then the n-bit data Dn is encoded such that the n+<NUM> bit encoded data [DBI, DQn] is DBI encoded. For example, when n-bit data Dn is <NUM>-bit data and has Hamming Weight of <NUM>, no inversion of the data bits occurs and the DBI bit is not asserted (i.e., logic low). On the other hand, if the <NUM>-bit data Dn has Hamming Weight of <NUM>, inversion of the data bits occurs and the DBI bit is asserted (i.e., logic high). Thus, for <NUM>-bit input data Dn, the n+<NUM> bit encoded data [DBI, DQn] with DBI encoding in step <NUM> will have Hamming Weight of only <NUM>. Also, the modified data mask signal (DM) is not asserted ("<NUM>" or logic low) in step <NUM>.

On the other hand, if the n-bit DBI-encoded data Dn is low Hamming Weight data in step <NUM>, then the n-bit data Dn is encoded using a non-DBI encoding scheme. In some embodiments, all or most of the n+<NUM> bit encoded data [DBI, DQn] is encoded to be non-low Hamming Weight Data. For example, when n-bit data Dn is <NUM>-bit data, the <NUM>-bit data Dn is encoded with a non-DBI encoding scheme that results in most (<NUM>) of the <NUM> bit encoded data [DBI, DQn] having Hamming Weights of four and merely some (<NUM>) of the <NUM> bit encoded data [DBI, DQn] having Hamming Weights of three. Also, the modified data mask signal (DM) is asserted ("<NUM>" or logic high) even when the original data mask signal (dm) is not asserted to indicate to memory device <NUM> that a non-DBI encoding scheme was used to encode the n+<NUM> bit encoded data [DBI, DQn]. Thus, the modified data mask signal (DM) is used to indicate to the memory device <NUM> whether DBI encoding or non-DBI encoding was used to encode the n+<NUM> bit encoded data [DBI, DQn]. The encoding scheme of the embodiment of <FIG> significantly reduces SSO noise because the Hamming Weights of the encoded data [DBI, DQn] are limited to a small range of variations (for example, Hamming Weights of <NUM> or <NUM> in the example of <NUM> bit data Dn).

Table <NUM> below illustrates an example of combinatorial logic that may be used to encode <NUM>-bit input data Dn to <NUM>-bit encoded data [DBI, DQn] according to the embodiment as shown in <FIG>. The combinatorial logic shown in Table <NUM> is merely exemplary, and other combinatorial logic may be used to perform the encoding as illustrated in <FIG>.

As can be seen from Table <NUM> above, when the data mask signal (dm) is asserted, the encoded data [DBI, DQn] is DQM (<NUM>). On the other hand, when the data mask signal (dm) is not asserted, then data Dn with Hamming Weights of <NUM> or <NUM> are encoded using DBI such that the data bits of data Dn with Hamming Weight of <NUM> are not inverted and the DBI bit is set to <NUM> while the data bits of data Dn with Hamming Weight of <NUM> are inverted and the DBI bit is set to <NUM>. The DBI-encoded data [DBI, DQn] has Hamming Weight of <NUM> only. Also, when the data mask signal (dm) is not asserted, then data Dn with Hamming Weights of <NUM>, <NUM>, <NUM>, or <NUM> (lower than <NUM>) or <NUM>, <NUM>, or <NUM> (higher than <NUM>) are encoded using a non-DBI encoding scheme as shown above in Table <NUM> that limits the Hamming Weights of the encoded data [DBI, DQn] to Hamming Weights of <NUM> or <NUM>.

More specifically, as shown in Table <NUM>, <NUM>-bit data pattern in the form of <NUM> with HW of zero is encoded to the <NUM>-bit encoded data pattern <NUM> with HW of three. <NUM>-bit data in the form of x, x<NUM> x<NUM> x<NUM> <NUM> with HW of one are encoded into <NUM>-bit data in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, and <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of one are encoded to <NUM>-bit encoded data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, where xn is the n-th bit from a least significant bit of the <NUM>-bit data pattern and xn is the complement of xn. <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of two are encoded to <NUM>-bit encoded data patterns in the form of <NUM> x, x, x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, <NUM>-bit data patterns in the form of <NUM> x, x<NUM> x<NUM> x<NUM> x, x<NUM> with HW of two are encoded to <NUM>-bit encoded data patterns in the form of <NUM> y<NUM> y<NUM> y, y<NUM> with HW of four, <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of two are encoded to <NUM>-bit encoded data patterns in the form of <NUM> y<NUM> y<NUM> y<NUM> y<NUM> with HW of four, and <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of two are encoded to <NUM>-bit encoded data pattern <NUM> with HW of three, where xn is the n-th bit from a least significant bit of the <NUM>-bit data pattern, y<NUM> = x<NUM> + x<NUM> + x<NUM> , y<NUM> = x<NUM> + x<NUM> + x<NUM> , y<NUM> = x<NUM> + x<NUM> + x<NUM> , and y<NUM> = x<NUM> + x<NUM> + x<NUM> and where + is OR operation.

For another example, <NUM>-bit data patterns in the form of x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of three are encoded to <NUM>-bit encoded data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, where xn is the n-th bit from a least significant bit of the <NUM>-bit data pattern. <NUM>-bit data patterns in the form of x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four are DBI-encoded to <NUM>-bit encoded data patterns <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, where xn is the n-th bit from a least significant bit of the <NUM>-bit data pattern. <NUM>-bit data patterns in the form of x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of five are also DBI-encoded to the <NUM>-bit encoded data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, where xn is the n-th bit from a least significant bit of the <NUM>-bit data pattern and xn is the complement (inverse) of x.

For still another example, <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of six are encoded to <NUM>-bit encoded data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of six are encoded to <NUM>-bit encoded data patterns <NUM> z<NUM> z<NUM> z<NUM> z<NUM> with HW of four, <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of six are encoded to <NUM>-bit encoded data patterns <NUM> z<NUM> z<NUM> z<NUM> z<NUM> with HW of four, and <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of six are encoded to <NUM>-bit encoded data patterns <NUM> with HW of three, where xn is the n-th bit from a least significant bit of the <NUM>-bit data pattern, z<NUM> = x<NUM> + x<NUM> + x<NUM> , z<NUM> = + x<NUM> + x<NUM> , z<NUM> = x<NUM> + x<NUM> + x<NUM> , and z<NUM> = x<NUM> + x<NUM> + x<NUM> , xn is complement of xn, and "+" is OR operation. <NUM>-bit data patterns in the form of x<NUM> x<NUM> x<NUM> x<NUM> <NUM> with HW of seven are encoded to <NUM>-bit encoded data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, and <NUM>-bit data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of seven are encoded to <NUM>-bit encoded data patterns in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four, where xn is n-th bit from a least significant bit of the <NUM>-bit data pattern and xn is complement of xn. For still another example, <NUM>-bit data pattern <NUM> with HW of eight is encoded to <NUM>-bit encoded data pattern <NUM> with HW of three. Also, the DQM data pattern is set to be <NUM>.

Although the n-bit data Dn to be transmitted from memory controller <NUM> to memory device <NUM> is assumed to be <NUM>-bit data in the examples above, the use of <NUM>-bit data herein is merely exemplary. Thus, the encoding scheme described herein may be used with any number of bits of data to be transmitted from memory controller <NUM> to memory device <NUM>. Mappings between <NUM>-bit uncoded data and <NUM>-bit coded data such as those shown in Table <NUM> above may be predetermined and stored in a LUT (not shown) on a memory controller <NUM>. That way, encoding of data according the embodiments described herein may be performed rapidly.

<FIG> illustrates one example of an encoder circuit, according to one embodiment. The encoder circuit of <FIG> is one example of a circuit configured to perform the encoding scheme as described above with reference to <FIG>, although different circuit configurations may be available with the same functions to perform the encoding scheme of <FIG>. The encoder <NUM> includes a DBI encoder <NUM>, a non-DBI encoder <NUM>, an AND gate <NUM>, an OR gate <NUM>, and multiplexers <NUM>, <NUM>. DBI encoder <NUM> is configured to conduct DBI encoding on the input data Dn as explained above with step <NUM> of <FIG> and non-DBI encoder <NUM> is configured to conduct non-DBI encoding on the input data Dn as explained above with step <NUM> of <FIG>, for example as shown above in Table <NUM>. Mode signal <NUM> is used to indicate to encoder <NUM> whether the encoding scheme according to the embodiments herein (<FIG>) should be used (when mode <NUM> is asserted) or DBI encoding (that is independent of the use of masking information) should be used (when mode <NUM> is not asserted). For purposes of illustration herein of the encoding scheme of <FIG>, mode signal <NUM> will be assumed asserted (logic high).

Turning to the operation of the encoder circuit <NUM>, when data mask signal (dm) <NUM> is asserted ("<NUM>" or logic high), the modified data mask signal DM <NUM> output from OR gate <NUM> is also "<NUM>" or logic high. In addition, data mask signal (dm) <NUM> also causes multiplexer <NUM> to select the predetermined bit pattern DQM <NUM> as its output <NUM>.

On the other hand, if the data mask signal (dm) <NUM> is not asserted ("<NUM>" or logic low), the multiplexer <NUM> selects the output <NUM> of multiplexer <NUM> as its encoded data [DBI, DQ,]. The output <NUM> of multiplexer <NUM> is either the output <NUM> of DBI encoder <NUM> or the output <NUM> of non-DBI encoder <NUM>, selected according to the output <NUM> of AND gate <NUM>. In this regard, DBI encoder <NUM> includes logic (not shown) configured to determine whether the input data Dn, when DBI-encoded by DBI encoder <NUM>, has a Hamming Weight lower than a predetermined threshold. In other words, DBI encoder <NUM> is also configured to determine whether the uncoded n-bit data Dn has a Hamming Weight lower than a first predetermined threshold or higher than a second predetermined threshold. When the input data Dn, when DBI-encoded by DBI encoder <NUM>, has a Hamming Weight lower than a predetermined threshold, DBI encoder <NUM> generates the low HW signal <NUM> to be logic high ("<NUM>"), but otherwise generates the low HW signal <NUM> to be logic low ("<NUM>").

Since mode signal <NUM> is set to be logic high, the output <NUM> of AND gate <NUM> becomes logic high if the input data Dn, when DBI-encoded by DBI encoder <NUM>, has a Hamming Weight lower than a predetermined threshold and thus the low HW signal <NUM> is asserted. As a result, multiplexer <NUM> selects the output <NUM> of non-DBI encoder <NUM> as its output <NUM>. In addition, the output <NUM> of OR gate <NUM> also becomes logic high (modified data mask signal DM=<NUM>) even through the original data mask signal dm <NUM> is not asserted. Thus, the modified data mask signal DM <NUM> at logic high can indicate to the memory device <NUM> that a non-DBI encoding has been used to encode the input data Dn.

On the other hand, the output <NUM> of AND gate <NUM> becomes logic low if the input data Dn, when DBI-encoded by DBI encoder <NUM>, has a Hamming Weight not lower than a predetermined threshold and thus the low HW signal <NUM> is not asserted. As a result, multiplexer <NUM> selects the output <NUM> of DBI encoder <NUM> as its output <NUM>. In addition, the output <NUM> of OR gate <NUM> also becomes logic low (modified data mask signal DM=<NUM>) when the original data mask signal (dm) <NUM> is not asserted. Thus, the modified data mask signal DM <NUM> at logic low can indicate to the memory device <NUM> that DBI encoding has been used to encode the input data Dn.

Finally, when mode signal <NUM> is at logic low ("<NUM>"), then the output <NUM> of AND gate <NUM> is always at logic low regardless of the low HW signal <NUM>. Thus, the modified data mask signal (DM) <NUM> output from OR gate <NUM> follows the original data mask signal (dm) <NUM>, and multiplexer <NUM> always selects the output <NUM> of DBI encoder <NUM>. Thus, when the original data mask signal (dm) <NUM> is not asserted, multiplexer <NUM> selects the output <NUM> of multiplexer <NUM>, which is always the output <NUM> of DBI encoder, resulting in DBI encoding regardless of the Hamming Weight of the input data Dn. When the original data mask signal (dm) <NUM> is asserted, multiplexer <NUM> selects the DQM signal to indicate a mask signal to the memory device <NUM>. Thus, when mode signal <NUM> is at logic low, the encoder <NUM> performs DBI encoding (that is independent of the use of masking information), and thus the encoder <NUM> is completely backward compatible with conventional DBI encoding schemes. For example, mode signal <NUM> may stored as a value in a programmable configuration register or hard wired by means of a fuse or metal mask, etc..

<FIG> is a flow chart illustrating a method of decoding data, according to one embodiment. The decoding scheme of the embodiment of <FIG> is used to decode the data [DBI, DQn] encoded using a combination of DBI encoding and non-DBI encoding according to the encoding scheme as explained above with reference to <FIG>.

First, it is determined <NUM> whether the modified data mask signal (DM) is asserted ("<NUM>" or logic high). If the modified data mask signal (DM) is not asserted, that means the data [DBI, DQn] was DBI-encoded (step <NUM> of <FIG>). Thus, data [DBI, DQn] is decoded using DBI and the data mask signal (dm) is set to "<NUM>" to indicate that the decoded data Dn should not be ignored. On the other hand, if the modified data mask (DM) signal is not asserted, then it is further determined <NUM> whether the encoded data [DBI, DQn] matches the predetermined data pattern DQM.

If the encoded data [DBI, DQ,] matches the predetermined data pattern DQM, that means the original data mask signal (dm) was asserted (step <NUM> of <FIG>). Thus, the data mask signal (dm) is set to "<NUM>" to indicate that the encoded data DQn should be ignored and DQ. is disregarded by memory device <NUM>. On the other hand, if the encoded data [DBI, DQn] does not match the predetermined data pattern DQM, then that means the data [DBI, DQn] was encoded using non-DBI encoding (step <NUM> of <FIG>). Thus, the data [DBI, DQn] is decoded using non-DBI decoding and the data mask signal (dm) is set to "<NUM>.

Note that decoding of the data [DBI, DQn] can be performed simply by reversing the combinatorial logic used to encode the data DQn. For example, when <NUM>-bit data DQn is encoded to <NUM>-bit data [DBI, DQn] using combinatorial logic shown in Table <NUM>, the <NUM>-bit data [DBI, DQn] can be decoded to recover the <NUM>-bit data DQn simply by reversing the combinatorial logic shown in Table <NUM>. For example, <NUM>-bit data in the form of <NUM> x<NUM> x<NUM> x<NUM> x<NUM> with HW of four can be decoded into <NUM> bit data x<NUM> x<NUM> x<NUM> x<NUM> <NUM> with HW of one. Numerous other examples of reversing the combinatorial logic for decoding are apparent from Table <NUM>. In some embodiments, such reverse mappings of logic may also be predetermined and stored in a LUT.

<FIG> illustrates one example of a decoder circuit, according to one embodiment. The decoder circuit of <FIG> is one example of a circuit configured to perform the decoding scheme as described above with reference to <FIG>, although different circuit configurations may be available with the same functions to perform the decoding scheme of <FIG>. The decoder <NUM> includes a DBI decoder <NUM>, a non-DBI decoder <NUM>, AND gates <NUM>, <NUM>, an OR gate <NUM>, a comparator <NUM>, and a multiplexer <NUM>. DBI decoder <NUM> is configured to conduct DBI decoding on the encoded data [DBI, DQn] as explained above with step <NUM> of <FIG> and non-DBI encoder <NUM> is configured to conduct non-DBI decoding on the encoded data [DBI, DQn] as explained above with step <NUM> of <FIG>. Mode signal <NUM> is used to indicate to decoder <NUM> whether the decoding scheme according to the embodiments herein (<FIG>) should be used (when mode signal <NUM> is asserted) or DBI decoding (that is independent of the use of masking information) should be used (when mode signal <NUM> is not asserted). For purposes of illustration herein of the decoding scheme of <FIG>, mode signal <NUM> will be assumed asserted (logic high).

Turning to the operation of the decoder circuit <NUM>, when the modified data mask signal (DM) <NUM> is not asserted ("<NUM>" or logic low), that means that the data [DBI, DQn] was DBI-encoded (step <NUM> of <FIG>). Thus, the data mask signal (dm) <NUM> output from AND gate <NUM> is set at logic low ("<NUM>"). In addition, the output <NUM> of AND gate <NUM> is also at logic low, thereby causing multiplexer <NUM> to select the output <NUM> of DBI decoder <NUM> as its output DQn <NUM>. Thus, the data [DBI, DQn] is decoded using DBI (step <NUM> of <FIG>).

When the modified data mask signal (DM) <NUM> is asserted ("<NUM>" or logic high), the output data mask signal (dm) <NUM> of AND gate <NUM> is at logic high if the output <NUM> of comparator <NUM> is at logic high, i.e., when the encoded data [DBI, DQn] matches the predetermined data pattern DQM as in step <NUM> of <FIG>. When data mask signal (dm) <NUM> is at logic high, the encoded data is disregarded (step <NUM> of <FIG>).

On the other hand, if the output <NUM> of comparator <NUM> is at logic low (i.e., when the encoded data [DBI, DQn] does not match the predetermined data pattern DQM), the output <NUM> of OR gate <NUM> is also at logic low ("<NUM>") and thus the data mask signal (dm) <NUM> output from AND gate <NUM> is also set at logic low. In addition, the output <NUM> of AND gate <NUM> is also at logic high, thereby causing multiplexer <NUM> to select the output <NUM> of non-DBI decoder <NUM> as its output DQn <NUM>. Thus, the data [DBI, DQn] is decoded using non-DBI decoding (step <NUM> of <FIG>).

Finally, when mode signal <NUM> is at logic low ("<NUM>"), then the output <NUM> of AND gate <NUM> is also always at logic low regardless of the state of the modified data mask signal (DM) <NUM>, thereby causing multiplexer <NUM> to always select the output <NUM> of DBI decoder <NUM> as its output DQn <NUM>. In addition, the output <NUM> of OR gate <NUM> is always at logic high if mode signal <NUM> is at logic low, and thus the data mask signal (dm) <NUM> output from AND gate <NUM> follows the state of the modified data mask signal (DM) <NUM>. Thus, the data [DBI, DQn] is always decoded using DBI decoding when mode signal <NUM> is not asserted. In other words, when mode signal <NUM> is at logic low, the decoder <NUM> performs DBI decoding (that is independent of the use of masking information), and thus the decoder <NUM> is completely backward compatible with conventional DBI decoding schemes. For example, mode signal <NUM> may stored as a value in a programmable configuration register or hard wired by means of a fuse or metal mask, etc..

With the encoding technique in accordance with the embodiments described herein, SSN can be reduced significantly and AC current drawn from the power supply may also be reduced significantly compared to conventional encoding methods such as DBI. This is explained in more detail with reference to <FIG> and <FIG>. <FIG> illustrates Hamming Weights (HWs) present in <NUM> bit data including <NUM> bit uncoded data and a DBI bit, and <FIG> illustrates Hamming Weights present in <NUM> bit coded data including a DBI bit and <NUM> bit coded data encoded according to one embodiment.

Referring to <FIG>, the HW histogram illustrates the distribution of HWs in the <NUM>-bit data including DBI (<NUM> bit) and <NUM> bit uncoded data, and the HW histograms <NUM> when such uncoded <NUM> bit data is encoded using conventional DBI ([DBI + <NUM> bit DBI-encoded data]). Among the possible data patterns (<NUM><NUM>) of the <NUM>-bit parallel uncoded data, there is <NUM> data pattern with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data pattern with HW=<NUM>, and <NUM> data pattern with HW=<NUM>. The maximum possible variation in the HWs in the <NUM>-bit uncoded data pattern is thus <NUM> (between HW=<NUM> and HW=<NUM>), which results in significant SSN if transmitted uncoded.

Still referring to <FIG>, the HW histograms <NUM> illustrates that only Hamming Weights <NUM> to <NUM> would be present when such <NUM> bit data is encoded using DBI ([DBI + <NUM> bit DBI-encoded data]), since data with Hamming Weights <NUM> through <NUM> would be inverted. Among the possible data patterns (<NUM><NUM>) of the <NUM>-bit parallel coded data, there is <NUM> data pattern with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data patterns with HW=<NUM>, <NUM> data patterns with HW=<NUM> and <NUM> data patterns with HW=<NUM>. The maximum possible variation in the HWs in the <NUM>-bit DBI-encoded data pattern is thus <NUM> (between HW=<NUM> and HW=<NUM>), which results in reduced SSN compared to when the data is transmitted uncoded.

Referring to <FIG>, the HW histogram <NUM> illustrates the distribution of HWs in the <NUM>-bit data ([DBI + <NUM> bit encoded data]) including encoded according to the combined data mask and DBI encoding scheme as described above with reference to <FIG>. Among the possible data patterns (<NUM><NUM>) of the <NUM>-bit parallel coded data, there are <NUM> data patterns with HW=<NUM> (including the DQM pattern) and <NUM> data patterns with HW=<NUM>. The maximum possible variation in the HWs in the <NUM>-bit data pattern is thus only <NUM> (between HW=<NUM> and HW=<NUM>), which results in significant reduction of SSN compared to the SSN when the data is transmitted uncoded or conventional DBI-coded.

These advantages are shown more specifically in Table <NUM> below, which shows the current (Idd) that would be drawn by transmitter (Tx) <NUM> (<FIG>) when the data Dn is transmitted uncoded, conventional DBI-coded, and coded with combined DM/DBI according to the embodiments herein, referencing the supply current Idd to be drawn when data Dn is transmitted uncoded as the reference (<NUM>%).

Claim 1:
A circuit, comprising:
an encoder (<NUM>) configured to receive, based on a mode, data and a data mask signal and to generate encoded data,
the data mask signal in a first state indicating that the data transmitted from the circuit to another circuit is to be ignored and the data mask signal in a second state indicating that the data transmitted from the circuit to said another circuit is not to be ignored,
the encoder (<NUM>) configured to encode a first subset of the data with data bus inversion and a second subset of the data differently from data bus inversion to generate the encoded data responsive to the data mask signal being in the second state; and
a transmitter (<NUM>) configured to transmit the encoded data over a communication link,
characterized in that the encoder (<NUM>) is further configured to generate a modified data mask signal, the modified data mask signal being in the first state responsive to the data mask signal being in the first state or the encoder (<NUM>) encoding the second subset of the data differently from data bus inversion.