Patent Description:
In order to ensure the continued miniaturization and multi-functionality of electric products and communication devices, it is desired that semiconductor packages be small in size, support multi-pin connection, operate at high speeds, and have high functionality. The impact of this will be pressure on semiconductor package fabricators to develop fan-out semiconductor packages. However, the increased amount of input/output connections of a multi-functional chip package may induce thermal electrical problems, for example, problems with heat dissipation, cross talk, signal propagation delay, electromagnetic interference in RF circuits, etc. The thermal electrical problems may affect the reliability and quality of products.

Thus, a novel semiconductor package assembly is desirable.

<CIT> discloses a substrate that comprises a core layer and, on each surface thereof, a dielectric structure and a solder mask layer, wherein the dielectric layers and the solder mask layers can be of the same material. The material may be bismaleimide-triazine or epoxy resin.

<CIT> and <CIT> describe semiconductor packages that include a substrate, wherein a patterned conductive layer is embedded in a dielectric layer and wherein conductive posts extend through openings in the dielectric layer.

<CIT> discloses a semiconductor device in which a first insulating layer is in contact with a base material layer and a second insulating layer is in contact with the first insulating layer. A linear expansion coefficient of the first insulating layer is equal to or larger than a linear expansion coefficient of the base material layer, the linear expansion coefficient of the first insulating layer is equal to or smaller than a linear expansion coefficient of the second insulating layer, and the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the second insulating layer.

An integrated circuit packaging system is known from <CIT> that includes a patterned first conductive plating, a moulding on the patterned first conductive plating, a through via through the moulding, a second conductive plating on the moulding and the through via, the protection layer partially covering the first conductive plating, the second conductive plating, and the moulding, and a device on the first conductive plating, wherein an external connector is attached to the second conductive plating.

<CIT> discloses a method for controlling warping of a substrate by forming first and second solder masks of different materials on opposed sides of the substrate. The different materials may correspond to materials having different thermal coefficients.

The invention refers to a semiconductor package assembly according to claim <NUM>.

According to the invention, the semiconductor package assembly 500c includes a base 250c. The base 250c includes a core substrate 200b, device pads <NUM>, a conductive plug structure <NUM> and a solder mask layer 216a. The base 250c of the semiconductor package assembly 500c requires only a single solder mask layer 216a disposed between the semiconductor device <NUM> and the core substrate of the base 250c. The core substrate and the solder mask layer on the device-attach surface of the core substrate are formed of the same material. This reduces the mismatch of CTE between the core substrate and the solder mask layer. Therefore, the thermal cycling reliability of the semiconductor package assembly is improved.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:.

Embodiments provide a semiconductor package assembly. The semiconductor package assembly includes a base including a core substrate having a device-attach surface and a solder-bump-attach surface opposite to the device-attach surface. According to the invention, the core substrate and a single solder mask layer covering the device-attach surface of the core substrate are formed of the same material (e.g. a thermosetting material). This reduces the stress between the solder mask layer and the core substrate. Therefore, the reliability of the semiconductor package assembly is improved.

<FIG> a cross-sectional view of a semiconductor package assembly 500a in accordance with some examples not corresponding to the invention as defined in the claims but useful for the understanding thereof. In some embodiments, the semiconductor package assembly 500a can be a flip chip package using conductive structures, for example, copper pillar bumps, connecting a semiconductor device to a base. In some embodiments, the semiconductor package assembly 500a can be a package using wire bonding technology to connect a semiconductor device to a base. Please refer to <FIG>, the semiconductor package assembly 500a includes a base 250a. In some embodiments, the base 250a includes a core substrate 200a, device pads <NUM>, bump pads <NUM>, conductive traces <NUM> and <NUM>, a through via plug <NUM>, solder mask layers 216a and <NUM>. In some embodiments, the base 250a includes a printed circuit board (PCB).

In some embodiments, as shown in <FIG>, the core substrate 200a of the base 250a includes a device-attach surface <NUM> and a solder-bump-attach surface <NUM> opposite to the device-attach surface <NUM>. The device-attach surface <NUM> of the core substrate 200a is provided for a semiconductor device <NUM> disposed thereon. The solder-bump-attach surface <NUM> of the core substrate 200a is provided for solder-bump structures <NUM> disposed thereon. In some embodiments, the core substrate 200a is formed of thermosetting materials. In some embodiments, the core substrate 200a is formed of resin-base materials. For example, the core substrate 200a may be formed of paper phenolic resin, composite epoxy, polyimide resin BT (Bismaleimide-Triazine) resin or polypropylene (PP) resin. In some embodiments, the core substrate 200a includes glass fibers <NUM> dispersed therein to reinforce the strength of the base 250a. In some embodiments, the glass fibers <NUM> are optional.

As shown in <FIG> the device pads <NUM> and the conductive traces <NUM> are disposed on the device-attach surface <NUM> of the core substrate 200a. The bump pads <NUM> and a conductive trace <NUM> are disposed on the solder-bump-attach surface <NUM> of the core substrate 200a. In some embodiments, the device pads <NUM> are electrically connected to a semiconductor device <NUM>, and the bump pads <NUM> are electrically connected to corresponding solder-bump structures <NUM>. In some embodiments, one or more through via plugs <NUM> are formed passing through the core substrate 200a. Two terminals (not shown) of the through via plugs <NUM> are respectively exposed to the device-attach surface <NUM> and the solder-bump-attach surface <NUM> of the core substrate 200a. In addition, the two terminals of through via plug <NUM> are in contact with and electrically connected to the corresponding conductive trace <NUM> and the corresponding conductive trace <NUM>, respectively. In some embodiments, the conductive trace <NUM> and the conductive trace <NUM> may include power trace segments, signal trace segments or ground trace segments. In some embodiments, the conductive trace <NUM> has a portion <NUM> serving as a bump pad region of the base <NUM>. The device pads <NUM>, the bump pads <NUM>, the conductive traces <NUM>, the conductive trace <NUM> and the through via plug <NUM> may be configured to provide input/output (I/O) connections of the semiconductor device <NUM> mounted directly onto the base 250a. The device pads <NUM>, the bump pads <NUM>, the conductive traces <NUM>, the conductive trace <NUM> and the through via plug <NUM> may be formed of conductive metals including copper or copper alloy. The device pads <NUM>, the bump pads <NUM>, the conductive traces <NUM>, the conductive trace <NUM> may be formed by the electronic plating process and the subsequent patterning process. The through via plug <NUM> may be formed by the laser drilling process and the electronic plating process. In some embodiments, Ni/Au layer structures <NUM> are formed on the device pads <NUM> and the bump pads <NUM> by the electro-plating process. In some embodiments, Ni/Au layer structures <NUM> are optional.

In some embodiments, as shown in <FIG>, a solder mask layer 216a covers the device-attach surface <NUM> of the core substrate 200a. The solder mask layer 216a may cover the conductive trace <NUM> directly on the through via plug <NUM>. The solder mask layer 216a may prevent oxidation of the underlying conductive trace <NUM>. In some embodiments, the solder mask layer 216a has one or more openings 218a to expose the device pads <NUM>. Also, the openings 218a of the solder mask layer 216a may be separated from the device pads <NUM> by a distance D. The openings 218a of the solder mask layer 216a are separated from the device pads <NUM> to prevent conductive structures <NUM> of the semiconductor device <NUM> disposed on the device pads <NUM> from short-circuiting with other conductive lines and device pads. Also, the openings 218a of the solder mask layer 216a may provide positions for the conductive structures <NUM> of the semiconductor device <NUM> to be bonded thereon. In some embodiments, the solder mask layer 216a includes solder-resistant materials. In some embodiments, the solder mask layer 216a may include photocuring materials, such as photoimageable solder mask materials. In some embodiments, the solder mask layer 216a may include solder mask, or insulating materials including polyimide, Ajinomoto build-up film (ABF), epoxy, polymethylmethacrylate (PMMA) resin, a composite including epoxy and PMMA resin, or polypropylene (PP) resin. In some embodiments, the solder mask layer 216a may be formed by a coating, a printing process, an adhesion process, a laminating process or another appropriate process.

In some embodiments, as shown in <FIG>, another solder mask layer <NUM> covers the solder-ball-attach surface <NUM> of the core substrate 200a. In addition, the solder mask layer <NUM> may cover the conductive trace <NUM> directly on the through via plug <NUM>. The solder mask layer <NUM> may prevent oxidation of the underlying conductive trace <NUM>. In some embodiments, the solder mask layer <NUM> has one or more openings <NUM> to expose the bump pads <NUM> and the pad portion <NUM> of the conductive trace <NUM>. Also, the openings 218a of the solder mask layer 216a may be positioned within boundaries of the bump pads <NUM>. In other words, the solder mask layer 216a may partially cover the bump pads <NUM>. The solder mask layer 216a may be adjacent to the bump pads <NUM>. The openings <NUM> of the solder mask layer <NUM> may prevent the solder-bump structures <NUM> disposed on the bump pads <NUM> from short-circuiting with other conductive lines and bump pads. Also, the openings <NUM> of the solder mask layer <NUM> may provide positions for the solder-bump structures <NUM> to be formed thereon.

In some embodiments, the solder mask layer <NUM> and the core substrate 200a are formed of the same materials. For example, the solder mask layer <NUM> and the core substrate 200a may be formed of thermosetting materials, such as polypropylene (PP) resin. In some other embodiments, the solder mask layer 216a is formed of Ajinomoto build-up film (ABF). In some embodiments, the solder mask layer <NUM> may include glass fibers <NUM> dispersed therein to reinforce the strength of the solder mask layer <NUM>. In some embodiments, the glass fibers <NUM> are optional.

In some embodiments, as shown in <FIG>, the semiconductor device <NUM> is mounted on the device-attach surface <NUM> of the core substrate 200a of the base 250a with an active surface of the semiconductor device <NUM> facing the base 250a by a bonding process. In some embodiments, the semiconductor device <NUM> included a die, a package, or a wafer-level package. In some embodiments, as shown in <FIG>, the semiconductor device <NUM> is a flip chip package. As shown in <FIG>, the semiconductor device <NUM> may include a body <NUM>, metal pads <NUM> overlying the semiconductor body <NUM>, and an insulation layer <NUM> covering the metal pads <NUM>. The circuitry of the semiconductor device <NUM> is disposed on the active surface, and the metal pads <NUM> are disposed on the top of the circuitry. The circuitry of the semiconductor device <NUM> is interconnected to the device pads <NUM> and the conductive trace <NUM> on the device-attach surface <NUM> of the core substrate 200a via a plurality of conductive structures <NUM> disposed on the active surface of the semiconductor device <NUM>. However, it should be noted that the conductive structures <NUM> shown in <FIG> are only an example and is not a limitation to the present invention.

In some embodiments, the conductive structure <NUM> may include a conductive bump structure such as a copper bump or a solder-bump structure, a conductive wire structure, or a conductive paste structure. In some embodiments, as shown in <FIG>, the conductive structure <NUM> may be a copper bump structure composed of a metal stack comprising a UBM (under-bump metallurgy) layer <NUM>, a copper layer <NUM> such as a plated copper layer, a conductive buffer layer <NUM>, and a solder cap <NUM>. In some embodiments, the UBM layer <NUM> can be formed on the exposed metal pads <NUM> within the openings by a deposition method such as a sputtering or plating method and a subsequent anisotropic etching process. The anisotropic etching process is performed after forming conductive pillars. The UBM layer <NUM> may also extend onto a top surface of the insulation layer <NUM>. In some embodiments, the UBM layer <NUM> may include titanium, copper, or a combination thereof. A copper layer <NUM> such as an electroplated copper layer can be formed on the UBM layer <NUM>. The opening can be filled with the copper layer <NUM> and the UBM layer <NUM>, and the copper layer <NUM> and the UBM layer <NUM> within the opening may form an integral plug of the conductive structure <NUM>. The formation position of the copper layer <NUM> is defined by a dry film photoresist or liquid photoresist patterns (not shown).

In some embodiments, an underfill material or the underfill <NUM> can be introduced into the gap between the semiconductor device <NUM> and the base 250a. In some embodiments, the underfill <NUM> may include a capillary underfill (CUF), molded underfill (MUF), or a combination thereof.

In some embodiments, the solder-bump structures <NUM> are formed on the solder-bump-attach surface <NUM> of the core substrate 200a. In addition, the solder-bump structures <NUM> may be formed filling the openings <NUM> of the solder mask layer <NUM> and be electrically connected to the corresponding bump pads <NUM>. In some embodiments, the solder-bump structures <NUM> may be formed covering portions of a surface of the solder mask layer <NUM> close to the openings <NUM>. In some embodiments, the solder-bump structures <NUM> may be formed of materials such as a solder paste. The solder-bump structures <NUM> may be formed on the bump pads <NUM> by a deposition process and a patterning process, or printing process/ball attachment process.

Because the solder mask layer 216a are disposed on the device-attach surface <NUM> of the core substrate 200a, the core substrate 200a may suffer the stress due to the mismatch of thermal expansion of the coefficient (CTE) between the solder mask layer 216a formed of photocuring material and the core substrate 200a formed of thermosetting material. In consideration of the direction of the stress on the core substrate 200a, the solder mask layer <NUM> covers the solder-bump-attach surface <NUM> of the core substrate 200a may be formed of the materials that is similar to or the same as the material of the core substrate 200a. The solder mask layer <NUM> may help to balance the stress form the solder mask layer 216a, so that the thermal cycling reliability of semiconductor package assembly 500a is improved.

<FIG> is a cross-sectional view of a semiconductor package assembly 500b in accordance with some examples not corresponding to the invention as defined in the claims but useful for the understanding thereof. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference to <FIG>, are not repeated for brevity.

The differences between the semiconductor package assembly 500a (<FIG>) and the semiconductor package assembly 500b is that the semiconductor package assembly 500b includes a base 250b. The base 250b includes a solder mask layer 216b covers the device-attach surface <NUM> of the core substrate 200a of the base 250b. The solder mask layer 216b may cover the conductive trace <NUM> directly on the through via plug <NUM>. The solder mask layer 216b may prevent oxidation of the underlying conductive trace <NUM>. In some embodiments, the solder mask layer 216b has one or more openings 218b to expose the device pads <NUM>. Also, the openings 218b of the solder mask layer 216b may be separated from the device pads <NUM> by a distance D. The openings 218b are separated from the device pads <NUM> to prevent conductive structures <NUM> of the semiconductor device <NUM> disposed on the device pads <NUM> from short-circuiting with other conductive lines and device pads. Also, the openings 218b of the solder mask layer 216b may provide positions for the conductive structures <NUM> of the semiconductor device <NUM> to be bonded thereon.

In some embodiments, the solder mask layer 216b and the solder mask layer <NUM> are formed of the same materials. In some embodiments, the solder mask layer 216b and the core substrate 200a are formed of the same materials. For example, the solder mask layer 216b may be formed of thermosetting materials, such as polypropylene (PP) resin. In some other embodiments, the solder mask layer 216b is formed of Ajinomoto build-up film (ABF). In some embodiments, the solder mask layer 216b may include glass fibers <NUM> dispersed therein to reinforce the strength of the solder mask layer <NUM>.

<FIG> is a cross-sectional view of a semiconductor package assembly 500c in accordance with some embodiments of the invention. Elements of the embodiments hereinafter, that are the same or similar as those previously described with reference to <FIG>, are not repeated for brevity.

The differences between the semiconductor package assembly 500a (<FIG>) and the semiconductor package assembly 500c is that the semiconductor package assembly 500c includes a base 250c. The base 250c includes a core substrate 200b, device pads <NUM>, a conductive plug structure <NUM> and the solder mask layer 216a. In addition, the semiconductor package assembly 500c is fabricated without the solder mask layer <NUM> shown in <FIG> and <FIG>. In other words, the base 250c of the semiconductor package assembly 500c requires only a single solder mask layer (i.e.the solder mask layer 216a) disposed between a semiconductor device (i.e. the the semiconductor device <NUM>) and the core substrate of the base 250c. In some embodiments, the base 250c includes a printed circuit board (PCB).

In some embodiments, <FIG> is also used to illustrate one exemplary embodiment of a method for fabricating the base 250c.

In some embodiments, as shown in <FIG>, the core substrate 200b of the base 250c is provided. The core substrate 200b includes a device-attach surface <NUM> and a solder-bump-attach surface <NUM> opposite to the device-attach surface <NUM>. The device-attach surface <NUM> of the core substrate 200b is provided for the semiconductor device <NUM> disposed thereon. The solder-bump-attach surface <NUM> of the core substrate 200b is provided for the solder-bump structures <NUM> disposed thereon. In some embodiments, the core substrate 200b is formed of thermosetting materials. In some embodiments, the core substrate 200b is formed of resin-base materials. For example, the core substrate 200b may be formed of paper phenolic resin, composite epoxy, polyimide resin BT (Bismaleimide-Triazine) resin or polypropylene (PP) resin. In some embodiments, the core substrate 200b comprises glass fibers <NUM> dispersed therein to reinforce the strength of the base 250c. In some embodiments, the glass fibers <NUM> are optional.

According to the invention, the core substrate 200b includes a trench <NUM> formed therein. In some embodiments, as shown in <FIG>, trenches <NUM> are formed in a portion of the core substrate 200b and close to the device-attach surface <NUM> of the core substrate 200b. The trenches <NUM> may be extended downwardly from the device-attach surface <NUM> of the core substrate 200b. In some embodiments, the trenches <NUM> are formed by the laser drilling process or chemical etching process, and the subsequent cleaning process (e.g. a desmear process).

In some embodiments, as shown in <FIG>, the conductive plug structures <NUM> of the base 250c are respectively formed filling the trenches <NUM> after the formation of the trenches <NUM>. In other words, the conductive plug structures <NUM> may be formed passing through a portion of the core substrate 200b. In addition, the device pads <NUM> are formed on the device-attach surface <NUM> of the core substrate 200b. In some embodiments, the device pads <NUM> are formed simultaneously with the conductive plug structures <NUM>. In some embodiments, each of the conductive plug structures <NUM> has a top portion <NUM> and a bottom portion <NUM> connecting to the top portion <NUM>. The top portion <NUM> of the each of the conductive plug structures <NUM> may be formed on the device-attach surface <NUM> of the core substrate 200b. The bottom portion <NUM> of the each of the conductive plug structures <NUM> may be embedded in the base 250c and surrounded by the core substrate 200b. In some embodiments, the conductive plug structures <NUM> and the device pads <NUM> are formed by the electro-plating process and the subsequent patterning process.

Next, as shown in <FIG>, the solder mask layer 216a is formed covering the device-attach surface <NUM> of the core substrate 200b. The solder mask layer 216a may cover the conductive plug structures <NUM>. The solder mask layer 216a may prevent oxidation of the underlying conductive plug structures <NUM>. In some embodiments, the solder mask layer 216a has one or more openings 218a to expose the device pads <NUM>. Also, the openings 218a of the solder mask layer 216a may be separated from the device pads <NUM> by a distance D. The openings 218a are separated from the device pads <NUM> to prevent conductive structures <NUM> of the semiconductor device <NUM> disposed on the device pads <NUM> from short-circuiting with other conductive lines and device pads. Also, the openings 218a of the solder mask layer 216a may provide positions for the conductive structures <NUM> of the semiconductor device <NUM> to be bonded thereon. In some embodiments, the solder mask layer 216a includes solder-resistant materials. In some embodiments, the solder mask layer 216a may include photocuring materials, such as photoimageable solder mask materials. In some embodiments, the solder mask layer 216a may include solder mask, or insulating materials including polyimide, Ajinomoto build-up film (ABF), epoxy, polymethylmethacrylate (PMMA) resin, a composite including epoxy and PMMA resin, or polypropylene (PP) resin. In some embodiments, the solder mask layer 216a may be formed by a coating, a printing process, an adhesion process, a laminating process or another appropriate process.

In some other embodiments, the solder mask layer 216a of the semiconductor package assembly 500c is replaced by the solder mask layer 216b shown in <FIG>. According to the invention, the solder mask layer 216a and the core substrate 200b are formed of the same materials.

Next, as shown in <FIG>, trenches <NUM> are formed in a portion of the core substrate 200b and close to the solder-bump-attach surface <NUM> of the core substrate 200b after the formation of the solder mask layer 216a. The trenches <NUM> may be aligned to the corresponding trenches <NUM>. The trenches <NUM> may be extended upwardly from the solder-bump-attach surface <NUM> of the core substrate 200b. In addition, the bottom portion <NUM> of the each of the conductive plug structures <NUM> is exposed to a bottom of the corresponding trench <NUM>. In some embodiments, the trenches <NUM> are formed by the laser drilling process or chemical etching process, and the subsequent cleaning process (e.g. a desmear process). After performing the aforementioned processes, the base 250c is formed, as shown in <FIG> in accordance with some embodiments.

In some embodiments, Ni/Au layer structures <NUM> are formed on the device pads <NUM> and the bottom portion <NUM> of the each of the conductive plug structures <NUM> by the electro-plating process. In some embodiments, the Ni/Au layer structures <NUM> are optional.

According to the invention, as shown in <FIG>, the semiconductor device <NUM> is mounted on the device-attach surface <NUM> of the core substrate 200b of the base 250c with an active surface of the semiconductor device <NUM> facing the base 250c by a bonding process. According to the invention, the solder-bump structures <NUM> are formed on the bottom portion <NUM> of the corresponding conductive plug structures <NUM>. In addition, the solder-bump structures <NUM> may be formed filling the trenches <NUM> of the core substrate 200b and electrically connected to the bottom portions <NUM> of the corresponding conductive plug structures <NUM>. Therefore, the bottom portion <NUM> of the conductive plug structures <NUM> may serve as bump pad of the base 250c. In some embodiments, a surface <NUM> of the bump pad (i.e. the bottom portion <NUM> of the conductive plug structure <NUM>) is between the device-attach surface <NUM> and the solder-bump structures <NUM> of the core substrate 200b. Because the bump pad of the base 250a is the bottom portion <NUM> of the conductive plug structure <NUM>, a boundary <NUM> of the bump pad (i.e. the bottom portion <NUM> of the conductive plug structure <NUM>) is (or is aligned to) a boundary of the conductive plug structure <NUM>. In some embodiments, the solder-bump structures <NUM> may be formed on the bottom portions <NUM> of the corresponding conductive plug structures <NUM> by a deposition process and a patterning process, or printing process/ball attachment process.

In some embodiments, the bottom portion <NUM> of the conductive plug structure <NUM> serves as a bump pad of the base 250c. The solder-bump structure <NUM> (e.g. a solder-ball) may be formed extended a portion of the core substrate 200b form the solder-bump-attach surface <NUM> to electrically connect to a corresponding bump pad (i.e. the bottom portion <NUM> of the conductive plug structure <NUM>). The base 250c of the semiconductor package assembly 500c is fabricated without forming an additional solder mask layer on the solder-bump surface <NUM> of the core substrate 200b. Therefore, the semiconductor package assembly 500c requires a single solder mask layer (e.g. the solder mask layer 216a or 216b) disposed on the device-attach surface <NUM> of the core substrate 200b. The problem of cracks forming at the interface between the solder-bump structure and the solder mask layer on the solder-bump-attach surface of the core substrate of the base is avoided.

The invention provides a semiconductor package assembly. The semiconductor package assembly may include a base including the core substrate having the device-attach surface and the solder-bump-attach surface opposite to the device-attach surface. The base of the semiconductor package assembly includes a solder mask layer disposed on the device-attach surface.

According to the invention, the core substrate and the solder mask layer on the device-attach surface of the core substrate are formed of the same material, for example, a thermosetting material. The solder mask layer of the base may further reduce the mismatch of CTE between the core substrate and the solder mask layer disposed on the device-attach surface of the core substrate. Therefore, the thermal cycling reliability of the semiconductor package assembly is improved.

Claim 1:
A semiconductor package assembly (500c), comprising:
a base (250c) comprising:
a core substrate (200b) having a first surface (<NUM>) and a second surface (<NUM>) opposite to the first surface (<NUM>);
a first pad (<NUM>) disposed on the first surface (<NUM>) of the core substrate (200b);
a solder mask layer (216a) covering the first surface (<NUM>) of the core substrate (200b); and
a conductive plug structure (<NUM>) having a top portion (<NUM>) on the first surface (<NUM>) of the core substrate (200b) and a bottom portion (<NUM>) between the first surface (<NUM>) and the second surface (<NUM>) of the core substrate (200b);
wherein the core substrate (200b) comprises a trench (<NUM>) formed extended into a portion of the core substrate (200b) from the second surface (<NUM>) of the core substrate (200b), and the bottom portion (<NUM>) of the conductive plug structure (<NUM>) is exposed to a bottom of the trench (<NUM>);
wherein the semiconductor package assembly (500c) further comprises a semiconductor device (<NUM>) arranged on the first surface (<NUM>) of the core substrate (200b), wherein the solder mask layer (216a) is the only solder mask layer of the base (250c) and is arranged
between the semiconductor device (<NUM>) and the core substrate (200b) of the base (250c); and
solder bump structures (<NUM>) arranged on the second surface (<NUM>) of the core substrate (200b);
characterised in that the core substrate (200b) and the solder mask layer (216a) are formed of the same material.