Patent Description:
One or more embodiments can be applied, for instance, to power semiconductor devices, including gallium nitride (GaN) or silicon carbide (SiC) devices.

The trend towards semiconductor die miniaturization, as fueled, e.g., by gallium nitride (GaN) or silicon carbide (SiC) devices, leads to seeking improved thermal dissipation performance in packages for small dice.

An approach to achieve such improved performance may involve die pad enlargement at leadframe design level.

This affects the leadframe dimensions and the length of wires in wire bonding patterns.

Another solution is to rely on leadframes including leads overhanging die pads.

While notionally attractive, this approach may turn out to be quite complex and expensive to implement.

Document <CIT> discloses a method for manufacturing an electronic semiconductor package, wherein an electronic chip is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated. At least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating - that is, electrically non-conductive - thermal interface structure, which electrically decouples the carrier with respect to its surroundings.

An object of one or more embodiments is to contribute in adequately addressing the issues discussed in the foregoing.

According to one or more embodiments, such an object can be achieved via a method having the features set forth in the claims that follow.

One or more embodiments may relate to a corresponding semiconductor device.

The claims are an integral part of the technical teaching on the embodiments as provided herein.

Examples presented herein involve increasing (that is, enlarging) the back or bottom area of a die pad without otherwise affecting die size and die-to-lead bond length.

For instance, a laser beam can be used to form a recess around the periphery of the bottom surface of a die pad. Thermally conductive material (metal as copper, for instance) is filled (e.g., grown) in the recess to extend the die pad area on the bottom side of the package.

A seed layer or the full desired thickness of copper can be jet-printed, optionally followed by electroplating.

Laser direct structuring (LDS) material can be used as a package molding material, and thermally conductive material (metal as copper, for instance) can be grown in the recess resorting to conventional in standard LDS processing (electroless plus electroplating).

Thermally conductive material (metal as copper, for instance) can also be grown in the recess resorting to laser-induced forward transfer (LIFT) processing.

The thickness of the die pad extension created can be equal to or different from the thickness of the leadframe die pad.

One or more embodiments involve using molding material compatible with laser direct structuring (LDS).

This processing is applicable in conjunction with conventional mold equipment and known packages. The higher cost of LDS compound hardly affects the total package cost due to the small quantity of LDS material involved and is advantageously less than any cost related to possible package redesign.

Embodiments of the present description being used can be recognized, e.g., via a different surface morphology of a basic die pad v. the material grown therearound to increase the die pad size. Leads in a leadframe "overhanging" the die pad may otherwise indicate that the die pad has been enlarged after leadframe manufacturing by additional material grown therearound. Molding compound analysis can otherwise highlight the use of a mold compound compatible with laser direct structuring (LDS) processing.

The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.

In the ensuing description one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description.

For simplicity and ease of explanation, throughout this description:.

<FIG> are partial cross-sectional views exemplary of certain steps or phases in manufacturing a semiconductor device <NUM> with a plastic package.

As otherwise conventional in the art, the device <NUM> comprises a substrate (leadframe) having arranged thereon one or more semiconductor chips or dice.

As used herein, the terms chip/s and die/dice are regarded as synonymous.

<FIG> refer by way of example to a semiconductor device <NUM> comprising a die pad 12A in a leadframe that also includes an array of leads 12B around the die pad 12A having a semiconductor chip or die <NUM> attached thereon, e.g., via a die attach film of DAF <NUM>.

The designation "leadframe" (or "lead frame") is currently used (see, for instance the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame that provides support for an integrated circuit chip or die as well as electrical leads to interconnect the integrated circuit in the chip or die to other electrical components or contacts.

Essentially, a leadframe comprises an array of electrically-conductive formations (or leads, e.g., 12B) that from an outline location extend inwardly in the direction of a semiconductor chip or die (e.g., <NUM>) thus forming an array of electrically-conductive formations from a die pad (e.g., 12A) configured to have - at least one - semiconductor chip or die attached thereon.

Certain semiconductor devices may in fact include plural die pads and/or plural dice or chips attached on the or each die pad: this description refers for simplicity and ease of explanation to a device <NUM> including a single die pad 12A having attached thereon (at a first surface, facing upwards in the figures) a single chip or die.

Electrically conductive formations are provided to electrically couple the semiconductor chip <NUM> to selected ones of the leads 12B in the leadframe.

As illustrated in <FIG>, these electrically conductive formations may comprise a wire bonding pattern <NUM> coupling the chip <NUM> to selected ones of the leads 12B. The wires in the wire bonding patterns <NUM> are coupled to die pads (not visible for scale reasons) provided at the front or top surfaces of the chip <NUM>.

An insulating encapsulation <NUM> (e.g., an epoxy resin) is molded on the assembly thus formed to complete the plastic body of the device <NUM>.

Laser direct structuring (LDS - oftentimes referred to also as direct copper interconnection or DCI technology) is a laser-based machining technique now widely used in various sectors of the industrial and consumer electronics markets, for instance for high-performance antenna integration, where an antenna design can be directly formed onto a molded plastic part.

In an exemplary process, the molded parts can be produced with commercially available insulating resins that include additives suitable for the LDS process; a broad range of resins such as polymer resins like PC, PC/ABS, ABS, LCP are currently available for that purpose.

In LDS, a laser beam can be used to transfer ("structure") a desired electrically-conductive pattern onto a plastic molding that may then be subjected to metallization to finalize a desired conductive pattern.

Metallization may involve electroless plating followed by electrolytic plating.

Electroless plating, also known as chemical plating, is a class of industrial chemical processes that creates metal coatings on various materials by autocatalytic chemical reduction of metal cations in a liquid bath.

In electrolytic plating, an electric field between an anode and a workpiece, acting as a cathode, forces positively charged metal ions to move to the cathode where they give up their charge and deposit themselves as metal on the surface of the work piece.

Documents such as <CIT>, <CIT>, <CIT>, <CIT>, <CIT>, <CIT>, <CIT>, or <CIT> (all assigned to the same assignee of the present application) are exemplary of the possibility of applying LDS technology in manufacturing semiconductor devices.

As illustrated in <FIG>, LDS technology facilitates replacing wires such as <NUM> with lines/vias created by laser beam processing of an LDS material followed by metallization (growing metal such as copper via a plating process, for instance).

Electrically conductive die-to-lead coupling formations can be provided (as discussed in the commonly assigned applications cited in the foregoing, for instance) in an insulated encapsulation <NUM> of LDS material (once consolidated, e.g., via thermosetting).

As illustrated in <FIG>, these die-to-lead coupling formations comprise:.

Providing the electrically conductive die-to-lead formations <NUM>, <NUM>, and <NUM> essentially involves (see <FIG>):.

Growing electrically conductive material may involve deposition of metal such as copper via electroless/electrolytic metal growth to facilitate electrical conductivity of the structured formations.

Growing electrically conductive material may also be via a LIFT process. The acronym LIFT denotes a deposition process where material from a donor tape or sheet is transferred to an acceptor substrate (here, the LDS material) facilitated by laser pulses.

General information on the LIFT process can be found, for instance, in <NPL>.

The half-split arrangement of <FIG> is intended to highlight that the processing leading to augmenting (that is, making greater or larger by adding to it, increasing in size) the die pad 12A as discussed in the following can be applied:.

A certain device <NUM> will thus expectedly adopt either one of the solutions i) or ii) above, thus being comprised of:.

The term "roughly" is intended to take into account the fact that neither a wire bonding pattern such as <NUM> (in the "wired" version of <FIG>) nor electrically conductive formations such as <NUM>, <NUM>, and <NUM> (in the "laser structured" version of <FIG>) will necessarily have a strictly mirror-symmetrical routing pattern of wires/lines with respect to any intermediate plane of the device <NUM>.

It will be otherwise appreciated that examples as discussed herein are primarily concerned with package thermal performance of a device such as device <NUM> rather that with specific details of electrical die-to-lead (or die-to-die) coupling therein.

Package thermal performance of a device <NUM> as considered herein is determined by package design and material selection and can be modelled based on various parameters.

The parameters introduced in the foregoing are measured in units of °K/W.

As discussed in the introductory portion to this description, semiconductor (silicon) miniaturization is leading to changes in package design. These involve reducing die pad (or heat sink) dimensions, which - per se - would have a negative effect on thermal performance.

The current trend towards die miniaturization dictates improved (higher) package thermal dissipation, while package design is not always compatible with this specification: when hosting a smaller die, die pad dimensions are reduced to reduce lengths of connections as well.

Indeed, thermal dissipation improves in response to die pad dimensions being increased. New technologies (such as gallium nitride (GaN) or silicon carbide (SiC) may dictate stricter thermal dissipation specifications, leading to package selection constraints.

Package redesign or changes in package can be considered as an option to address this problem: package redesign however involves higher development costs and may not meet customer requirements.

Other options may involve modification in materials, e.g., reduction of die thickness or improvements in die attach materials. These measures are however less effective than package redesign.

Being able to enhance package thermal properties without adversely affecting wire connections and leadframe design (and the range of applicability and customization, thus device flexibility) is thus desirable.

Examples as proposed herein "enlarge" (augment) the back or bottom area of a die pad 12A (facing downwards in <FIG>) without otherwise affecting die size and die-to-lead bond length.

<FIG> are exemplary of steps or phases wherein at least one semiconductor chip <NUM> is arranged on a first surface (facing upwards in the figures) of a thermally conductive (e.g., metal as copper) die pad 12A in a substrate (leadframe).

The die pad 12A has a second surface (facing downwards in the figures) opposite the first surface and an encapsulation <NUM>, <NUM> of insulating material is molded (in a manner known per se to those of skill in the art) onto the die pad 12A having the (at least one) semiconductor chip <NUM> arranged on the first surface.

As a result of molding, at the second surface of the die pad 12A, the encapsulation <NUM>, <NUM> borders on the second surface of the die pad 12A (substantially flush therewith) along a borderline around the die pad 12A, that is along the peripheral contour of the second surface of the die pad 12A.

As exemplified in <FIG>, a recess or groove (continuous/discontinuous) 120A can be formed around the periphery of the second (back or bottom) surface of the die pad 12A.

As exemplified in <FIG>, thermally (and electrically) conductive material (metal as copper, for instance) is grown (filled-in) in the recess 120A to augment (that is, to make greater by adding to it and thus increase) the die pad area at the bottom side of the package as indicated by 122A.

Forming the recess 120A may involve, for instance, selectively removing encapsulation material.

Ablation via laser beam, as schematically represented at LB in <FIG>, was found to be advantageous in view of its flexibility (e.g., etching masks can be dispensed with).

Growing (filling-in) thermally conductive material 122A in the recess 120A as schematically represented at MG in <FIG>, can be likewise implemented in different ways.

For example, a seed layer or the full desired thickness of material such as copper can be jet-printed into the recess 120A, optionally followed by electroplating.

Using laser direct structuring (LDS) material for the encapsulation <NUM> represents an advantageous option insofar as:.

Laser direct structuring (LDS) material can be used also for an encapsulation <NUM> as illustrated in <FIG>, that is an encapsulation intended to encapsulate a wire bonding pattern such as the wire bonding pattern <NUM> in a "wired" version of the device <NUM>.

Also in this latter case, laser beam energy LB can be used to drill/ablate) LDS material of the encapsulation to form the recess 120A with, e.g., plating (electroless plus electrolytic deposition, for instance), LIFT processing (or jet-printing) used to grow electrically/thermally conductive material at the recess 120A to extend the - heat dissipating - die pad area at the bottom side of the package at 122A.

It is noted that laser beam energy LB drills/ablates some LDS material (thus providing a shaping effect or action) and, in doing so, also activates the LDS material (thus influencing the properties of the surface of the LDS molding compound.

Laser direct structuring (LDS) is applicable in conjunction with conventional mold equipment and known packages.

Examples as presented herein facilitate enlarging the area of a die pad 12A without otherwise affecting package design. Die pad enlargement is performed after molding and does not affect leadframe design. Leadframe features (like short connections from die to lead) can be maintained with thermal dissipation performance improved.

This is evidenced by the functional flow charts of <FIG>. These flow charts refer to a conventional sequence of steps in manufacturing semiconductor devices (<FIG>) and a sequence of steps in manufacturing semiconductor devices according to embodiments of the present description (<FIG>), respectively.

It will be otherwise appreciated that the sequences of steps of <FIG> are merely exemplary insofar as:.

In both <FIG>, block <NUM> indicates collectively those steps that - in a manner known to those of skill in the art - produce the basic structure of a semiconductor device (e.g., attaching one or more chips or dice <NUM> on a die pad 12A, and so on) prior to molding thereon an insulating encapsulation.

This step (e.g., molding a conventional encapsulation <NUM> of an epoxy resin, for instance) is indicated at <NUM> in <FIG> followed by (tin) plating and "cropping" as represented by blocks <NUM> and <NUM> in <FIG>.

A resulting "standard" die pad 12A is shown at the bottom of <FIG>: this can be regarded as a schematic view of a device <NUM> as observed from its back or bottom side.

In the exemplary case presented in <FIG> block <NUM> is followed by a sequence <NUM>' of a molding step of an encapsulation of LDS material <NUM> followed by LDS processing at 102B.

As discussed previously in connection with <FIG>, such processing may involve applying laser beam energy LB to form the recess 120A at the back or bottom surface of the device <NUM> and to structure the vias <NUM>, <NUM> and the lines or traces <NUM> at the front or top surface of the device <NUM>.

In <FIG>, plating at <NUM>' may denote copper plating + tin plating (electroless plus electrolytic deposition, for instance) or LIFT processing used to grow electrically/thermally conductive material (metal such as copper, for instance) both at the recess 120A to extend the - heat dissipating - die pad area at the bottom side of the package at 122A and to facilitate electrical conductivity of the vias <NUM>, <NUM> and the lines or traces <NUM> at the front or top surface of the device <NUM>.

A resulting standard die pad 12A "augmented" at 122A is shown at the bottom of <FIG>: this can be regarded as a schematic view of a device <NUM> as observed from its back or bottom side.

While represented here as a continuous and contiguous frame surrounding the original die pad 12A, in certain embodiments the augmented portion 122A may be discontinuous (that is comprise plural segments or dots in a dashed/dotted pattern) and/or non-contiguous (that is, have a separation gap) to the original die pad 12A.

It will be appreciated that enlarging the die pad 12A at 122A (thus improving the thermal dissipation of the device <NUM>) takes place without increasing the overall size of the device <NUM> and, more to the point, without increasing the length of the electrical connection paths (e.g., wires <NUM> or "LDS-structured" formations <NUM>, <NUM>, <NUM>) between the semiconductor chip <NUM> and the leads 12B.

In fact, as visible in the examples presented herein, the leads 12B can be caused to project above (overhang) the enlarged portion 122A of the die pad 12A.

The examples presented herein can be virtually applied to any leadframe-based plastic package.

The table below report comparison data obtained via TRAC simulation for a PSSO36 package with die dimensions in um (X x Y x Z): <NUM> x <NUM> x <NUM>. Wired version. Die attach material: soft solder.

Claim 1:
A method, comprising:
arranging at least one semiconductor die (<NUM>) on a first surface of a thermally and electrically conductive die pad (12A) in a substrate, the die pad (12A) having a second surface opposite the first surface,
molding an encapsulation (<NUM>, <NUM>) of insulating material onto the die pad (12A) having the at least one semiconductor die (<NUM>) arranged on the first surface, wherein, at the second surface of the die pad (12A), the encapsulation (<NUM>, <NUM>) borders on the die pad (12A) at a borderline around the die pad (12A),
providing at said borderline around the die pad (12A) a recessed portion (120A) of the encapsulation (<NUM>, <NUM>) around the die pad (12A), and
filling thermally and electrically conductive material (122A) in said recessed portion (120A) of the encapsulation (<NUM>, <NUM>), wherein the thermally and electrically conductive die pad (12A) is augmented by thermally and electrically conductive material (122A) in said recessed portion (120A) of the encapsulation (<NUM>, <NUM>).