Patent Description:
<CIT> discloses a PSFB converter and a drive scheme for operating switches in an full bridge of the PSFB converter. In addition, this reference discloses an LLC converter that includes a resonant circuit coupled to a primary winding of a transformer.

Conventionally, PSFB converters are designed with a large output capacitor to bridge the time when the AC line voltage is interrupted. However, this means that the PSFB converter has a duty cycle which does not yield optimal efficiency. When the AC line voltage drops, duty cycle increases to maintain regulation. Conventional PSFB converters have maximum duty for minimum AC line voltage conditions to achieve better efficiency. However, this means lower duty under nominal AC line voltage conditions which in turn yields lower efficiency. Operating a PSFB converter with a limited (e.g. <NUM>%) duty cycle during nominal AC line voltage conditions results in less efficient operation and more power dissipating losses, because each power transfer cycle includes a freewheeling period. No power transfer happens during the freewheeling period, but circulation losses do arise.

Hence, there is a need for a more efficient technique of operating a PSFB converter during nominal AC line voltage conditions while maintaining output voltage regulation during interruptions in the AC line voltage input.

The invention provides a phase shift full bridge converter according to claim <NUM>, and a method of operating a phase shift full bridge converter according to claim <NUM>.

Embodiments are depicted in the drawings and are detailed in the description which follows.

Embodiments described herein provide a control technique which increases the efficiency of a PSFB converter during nominal AC line voltage conditions while maintaining output voltage regulation during interruptions in the AC line voltage input. Under nominal input voltage conditions for the PSFB, the full-bridge on the primary side of the PSFB is switched at a nominal switching frequency. Under reduced input voltage conditions for the PSFB, the full-bridge on the primary side of the PSFB is switched at a frequency lower than the nominal switching frequency. This way, the PSFB converter has a more ideal duty cycle under nominal input voltage, and when the input voltage, the switching frequency of the PSFB is reduced to ensure adequate freewheeling time and thus continued output voltage regulation.

<FIG> illustrates an embodiment an AC/DC converter <NUM>. The AC/DC converter <NUM> includes an AC/DC stage <NUM> and a PSFB converter <NUM> coupled to the AC/DC stage <NUM>. The AC/DC stage <NUM> converts an AC line voltage ('AC Line In') to a DC link voltage ('Vin'). In one embodiment, the AC/DC stage <NUM> includes EMI (electromagnetic interference) and bridge rectification circuitry <NUM> for filtering noise and converting the filter input to a rectified signal ('Vsin Rect'). The AC/DC stage <NUM> may also include a PFC (power factor correction) boost converter <NUM> for shaping the input current of the AC/DC converter to be in synchronization with the AC line voltage input, and thus providing a DC link voltage ('Vin') to the PSFB converter <NUM>.

The PSFB converter <NUM> provides voltage translation between the DC link voltage ('Vin') and the DC output voltage ('Vout') of the AC/DC converter <NUM> and also provides isolation from the AC line voltage input ('AC Line In'). The PSFB converter <NUM> includes an isolation transformer <NUM>, a full-bridge <NUM> coupled to the primary side of the isolation transformer <NUM>, a rectifier <NUM> coupled to the secondary side of the isolation transformer <NUM>, and a controller <NUM> to control switching of the full bridge <NUM> and optionally the rectifier <NUM>. The transformer <NUM> is illustrated as a dashed line in <FIG>, to indicate the isolation between the primary (left-hand) and secondary (righthand) sides of the PSFB converter <NUM>. The controller <NUM> is shown on the primary side of the PSFB converter <NUM> in <FIG>, but instead may be on the secondary side and coupled to the primary side by, e.g., an optocoupler. Operation of the PSFB converter <NUM> is described next in more detail.

<FIG> illustrates an embodiment of the PSFB converter <NUM>. The load powered by the PSFB converter <NUM> is generically illustrated as a resistor RO in <FIG>. The PSFB converter <NUM> includes a primary side having a plurality of switch devices QA, QB, QC, QD that form the full bridge <NUM>, and a secondary side having a plurality of switch devices QE1, QE2, QF1, QF2 that form the rectifier <NUM>. The secondary side also includes an output filter coupled to the rectifier <NUM>, the output filter including an output inductor Lo and an output capacitor Co. The DC link voltage Vin output by the AC/DC stage <NUM> to the PSFB converter <NUM> is represented as a battery in <FIG>.

On the primary side of the PSFB converter <NUM>, high-side switch device QA is connected in series with low-side switch device QB at node 'n1'/'A' to form a first leg QA/QB of the full bridge <NUM>, and high-side switch device QC is connected in series with low-side switch device QD at node 'n2'/'B' to form a second leg QC/QD of the full bridge <NUM>. Node n1 is coupled to a first terminal 'TP1' of the primary side of the isolation transformer <NUM> and node n2 is coupled to a second terminal 'TP2' of the primary side of the isolation transformer <NUM>. The isolation transformer <NUM> is shown as being split between the primary side (Trp) and the secondary side (Trs) for ease of illustration.

Similarly on the secondary side, high-side switch device QE1 is connected in series with low-side switch device QF1 at node 'n3' to form a first leg QE1/QF1 of the rectifier <NUM>, and high-side switch device QF2 is connected in series with low-side switch device QE2 at node 'n4' to form a second leg QF2/QE2 of the rectifier <NUM>. Node n3 is coupled to a first terminal 'TS1' of the secondary side of the isolation transformer <NUM> and node n2 is coupled to a second terminal 'TS2' of the secondary side of the isolation transformer <NUM>.

Those skilled in the art will readily understand that a different type of rectifier may be used on the secondary side of the PSFB converter <NUM> such as, but not limited to, a current-fed push-pull, center-taped or current doubler rectification stage, etc. Also, the primary-side switch devices QA, through QD and the secondary-side switch devices QE1 through QF2 of the PSFB converter <NUM> are illustrated as power MOSFETs each having a corresponding freewheeling diode DA-DD and DE1-DF2 and parasitic capacitance CA-CD and CE1-CF2. However, any suitable power transistor can be used for the primary-side switch devices QA, through QD and the secondary-side switch devices QE1 through QF2 of the PSFB converter <NUM>, such as but not limited to power MOSFETs, IGBTs (insulated gate bipolar transistors), HEMTs (high-electron mobility transistors), etc..

The PSFB controller <NUM>, which may be located on the primary or secondary side of the converter <NUM>, controls the primary-side switch devices QA, through QD and the secondary-side switch devices QE1 through QF2 during nominal AC line voltage conditions and during interruptions in the AC line voltage input. For example, the nominal DC link voltage 'Vin' to the PSFB converter <NUM> may be 400V during nominal AC line voltage conditions and may drop to about 300V, plus or minus, during an AC outage. Under nominal AC line voltage conditions, the controller <NUM> switches the legs QA/QB, QC/QD of switch devices QA, QB, QC, QD out of phase with each other to transfer energy from the primary side of the PSFB converter <NUM> to the secondary side. If the legs QA/QB, QC/QD of switch devices QA, QB, QC, QD are switched in phase with each other, no energy transfer will occur. This is a defining characteristic of PSFB converters. Under reduced AC line voltage conditions, the controller <NUM> switches the legs QA/QB, QC/QD of switch devices QA, QB, QC, QD out of phase with each other at a frequency lower than the nominal switching frequency to transfer energy to the secondary side of the PSFB converter <NUM> and maintain regulation.

<FIG> illustrate operation of the PSFB converter <NUM> during different stages of a power transfer interval, and the corresponding control signals generated by the controller <NUM>. In phase-shift full bridge converter topology, the range of zero voltage switching (ZVS) is given by the energy stored in the magnetics Lr, Llkg, Lo and Lm where Lr is the external resonant inductance of the PSFB converter <NUM>, Llkg is the leakage inductance of the isolation transformer <NUM>, Lo is the inductance of the output inductor Lo on the secondary side of the converter <NUM>, and Lm is the magnetizing inductance in the primary of the transformer <NUM>. The two legs (QA/QB, QC/QD) of the half bridge <NUM> on the primary side behave differently during switching transitions. One leg of the full bridge <NUM> turns on-off after a power transfer from the primary side to the secondary side, also referred to herein as a lagging power transfer, as shown in <FIG>. The other leg of the full bridge <NUM> leads the following power transfer, also referred to herein as a leading power transfer, also as shown in <FIG>.

<FIG> shows current flow in the primary and secondary sides of the PSFB converter <NUM> during a lagging power transfer, whereas <FIG> shows current flow in the primary and secondary sides of the PSFB converter <NUM> during a leading power transfer. The current flows in the primary and secondary sides of the PSFB converter <NUM> are illustrated as thick dashed lines with arrows in <FIG> and <FIG>, and the primary-side switch devices which are turned off are illustrated with a dashed 'X'.

During a lagging power transfer, the lagging leg (leg QA/QB in <FIG> and <FIG>) transition occurs just after a power transfer from the primary side which includes the full bridge <NUM> to the secondary side which includes the rectifier <NUM>. During the lagging leg transition, which is illustrated in <FIG>, switch device QB has turned OFF and energy of the inductances flows into parasitic capacitances CA, CB until the diode DA in parallel with switch device QA conducts, thereby enabling ZVS. The current path through the diode DA in parallel with switch device QA is illustrated as a thick dashed line with an arrow in <FIG>.

Because the filter inductance Lo is effectively connected through the full bridge <NUM> by the isolation transformer <NUM> during the transition in the lagging power transfer, the energy available for charging/discharging the parasitic capacitances CA, CB of the lagging leg QA/QB of the full bridge <NUM> is given by: <MAT>.

To achieve full ZVS on the lagging leg QA/QB of the full bridge <NUM>, the available energy should be bigger than the total energy Eoss of the output capacitance of the lagging leg QA/QB of the full bridge <NUM> plus other stray capacitances of the half bridge node, as given by: <MAT> where Lo' is the equivalent reflected value of the output filter inductance through the transformer and which is given by: <MAT>.

For a step-down converter in which the number of transformer windings (Np) on the primary side is greater than the number of transformer windings (Ns) of the secondary side, the contribution of energy by the output filter inductance Lo is in general much higher than the contribution by the other inductances. Accordingly, ZVS is typically achieved through all load ranges for the lagging leg QA/QB of the full bridge <NUM>.

The leading leg (leg QC/QD in <FIG> and <FIG>) transition occurs before a power transfer from the primary side to the secondary side and after a freewheeling phase, as shown in <FIG>. No power transfer happens during the freewheeling phase, but circulation losses do arise. The PSFB control techniques described minimize the freewheeling phase under nominal input voltage conditions for the PSFB, thereby avoiding most if not all of the circulation losses which would otherwise occur.

During the leading leg transition, which is illustrated in <FIG>, switch device QC has turned OFF and energy of the inductances flows into parasitic capacitances CC, CD until the diode D<NUM> in parallel with switch device QD conducts, thereby enabling ZVS. The current path through the diode D<NUM> in parallel with switch device QD is illustrated as a thick dashed line with an arrow in <FIG>.

If the freewheeling phase occurs, the isolation transformer <NUM> is effectively shorted by the rectifier <NUM> during the freewheeling phase and the output filter inductance Lo does not contribute to the leading leg transition as shown in <FIG>. Under these conditions, the energy available for charging/discharging the parasitic capacitances CC, CD of the leading leg QC/QD of the full bridge <NUM> is given by: <MAT>.

To achieve full ZVS on the leading leg QC/QD of the full bridge <NUM>, the available energy should be bigger than the total energy Eoss of the output capacitance of the leading leg QC/QD of the full bridge <NUM> plus other stray capacitances of the half bridge node, as given by: <MAT>.

In this case, ZVS does not occur easily along all load ranges and typically requires careful design of the isolation transformer <NUM> and/or external resonant inductances. In general, increasing Lr, Llkg or reducing Lm increases the available energy. However, decreasing Lm increases the primary circulating current and therefore increases conduction losses. Increasing Lr and Llkg reduces the available duty cycle and thus limits the maximum load at which the PSFB converter <NUM> can regulate. To mitigate these problems, the PSFB controller <NUM> switches the (legs) pairs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD at a nominal switching frequency under nominal input voltage conditions for the PSFB converter <NUM> and switches the (legs) pairs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD at a frequency lower than the nominal switching frequency under reduced input voltage conditions for the PSFB converter <NUM>. This way, the PSFB converter <NUM> operates with a more efficient (higher) duty cycle and lower (or no) freewheeling period during nominal AC line voltage conditions while still maintaining output voltage regulation during interruptions in the AC line voltage input. The effect duty cycle has on PSFB converter efficiency during nominal AC line voltage conditions is described next in more detail.

The effective duty of the PSFB converter <NUM> depends on the ratio of input to output voltages and the transformer ratio (Np/Ns) and is constant along load, as given by: <MAT>.

The duty loss ('Lost duty' in <FIG>) due to the time needed to reverse primary current along the inductances Lr, Llkg reduces freewheeling time and depends on load, as primary current is the reflected secondary current plus the primary transformer magnetizing current, where: <MAT> <MAT> <MAT> Ip is the primary current, Is is the secondary current, and Fswitch is the switching frequency of the PSFB converter <NUM>.

Freewheeling duty should be bigger than or equal to zero for the PSFB converter <NUM> to maintain regulation, as indicated in <FIG> which illustrates an extreme case in which no more available regulation window available.

For best efficiency, freewheeling time should be at or near zero at full load. This allows for maximum ZVS range for the full bridge <NUM>, specifically for the leading leg. Also, there is less circulating current in the primary side of the PSFB converter <NUM> when freewheeling time is minimal. Maximum effective duty is also achieved, as is lower secondary side reflected voltage which allows for the use better secondary side voltage class switch devices.

However, in a full AC/DC converter design as shown in <FIG>, the PSFB converter <NUM> should maintain output regulation at full load and during during interruptions in the AC line voltage input ('AC Line In'). During an interruption of the AC line voltage input, the output voltage ('DC Link') of the AC/DC stage <NUM> drops (e.g. from 400V to 350V or even lower). The PSFB controller <NUM> ensures the PSFB converter <NUM>, which is coupled to the AC/DC stage <NUM>, maintains regulation over the entire input voltage range of interest by switching the full bridge <NUM> at a frequency lower than the nominal switching frequency under reduced AC line voltage conditions.

As explained above, the effective duty time depends on the ratio of input to output voltages and the transformer ratio and is constant along load. The effective duty time also depends on switching frequency Fswitch of the PSFB converter <NUM> as given by: <MAT> The transformer frequency is <NUM> times the switching frequency Fswitch of the legs QA/QB, QC/QD of the full bridge <NUM>.

The time taken to reverse the primary current along inductances Lr, Llkg, i.e. lost duty, reduces the freewheeling time and depends on load, since the primary current is the reflected secondary current plus the primary transformer magnetizing current, which is dismissed in the simplified models provided herein but also based on switching frequency Fswitch of the full bridge <NUM>. Hence, equations (<NUM>) and (<NUM>) may be reformulated as given by: <MAT> <MAT>.

Based on equations (<NUM>) and (<NUM>), the available regulation (freewheeling) time for the PSFB converter <NUM> depends on the switching frequency Fswitch as given by: <MAT>.

Equation (<NUM>) can be further simplified. With all other conditions fixed, freewheeling time increases when switching frequency Fswitch of the PSFB converter <NUM> decreases as given by: <MAT> where <MAT>.

<FIG> illustrates freewheeling time dependency as a function of switching frequency Fswitch for a typical PSFB converter at different DC link input voltages ranging from 400V down to 330V, with all other conditions fixed. The vertical line with terminating arrows indicates the frequency trajectory of a typical PSFB modulation scheme in which a fixed duty cycle of e.g. <NUM>% is used across the entire input voltage range, including during nominal operation and during reduced AC line voltage conditions ('Hold up operation' in <FIG> shows that for the same PSFB input voltage, reducing the switching frequency Fswitch of the PSFB converter <NUM> increases freewheeling time.

The PSFB controller <NUM> modifies the switching frequency Fswitch of the PSFB converter <NUM> to compensate for the loss of duty cycle due to the drop-in input voltage. The controller <NUM> employs a more ideal duty cycle under nominal AC line voltage conditions, and when the input voltage to the PSFB converter <NUM> drops, the controller <NUM> reduces the switching frequency Fswitch of the PSFB converter <NUM> to ensure adequate freewheeling time under reduced AC line voltage conditions. The PSFB converter control scheme described herein allows for optimal performance at nominal conditions while fulfilling required specifications under reduced AC line voltage conditions.

Equations (<NUM>) through (<NUM>) may be reformulated so as to obtain a switching frequency Fswitch based on design parameters and load conditions, as given by: <MAT>.

The PSFB controller <NUM> modifies the switching frequency Fswitch of the PSFB converter <NUM> depending on the DC input voltage ('Vin') to the PSFB converter <NUM>. The controller <NUM> can modify the switching frequency Fswitch based on the PSFB input voltage whenever an input voltage measurement is available to the controller <NUM> and/or whenever the input voltage can be calculated based on other measurements available to the controller <NUM>.

<FIG> illustrates two different embodiments of Fswitch control based on PSFB input voltage, as implemented by the controller <NUM> of the PSFB converter <NUM>. In one embodiment, under reduced input voltage conditions, the controller <NUM> switches the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD at a first discrete frequency Fswitch1 under nominal input voltage conditions and switches the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD at a second discrete frequency Fswitch2 lower than the first discrete frequency under reduced input voltage conditions. The discrete Fswitch adjustment trajectory is labelled 'Hold up Trajectory B' in <FIG>.

The controller <NUM> may compare the PSFB input voltage or an estimate of the PSFB input voltage to a voltage threshold and change the switching frequency of the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD from the first discrete frequency Fswitch1 to the second (lower) discrete frequency Fswitch2 if the PSFB input voltage or an estimate of the PSFB input voltage is below the voltage threshold. The controller <NUM> may change the frequency at which the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD are switched from the second discrete frequency Fswitch2 back to the first (higher) discrete frequency Fswitch1 if the PSFB input voltage or an estimate of the PSFB input voltage increases above the voltage threshold. The controller <NUM> may utilize hysteresis to avoid frequent changes in Fswitch for PSFB input voltage changes near the voltage threshold. For example, the controller <NUM> may include a comparator with hysteresis and be configured to indicate when the PFSB input voltage or an estimate of the PSFB input voltage drops below the voltage threshold. The discrete adjustment of the PSFB switching frequency Fswitch resumes when the comparison result falls outside the hysteresis window.

In another embodiment, under reduced input voltage conditions, the controller <NUM> continually adjusts the switching frequency Fswitch of the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD based on the input voltage to the PSFB converter <NUM>. That is, the controller <NUM> modifies Fswitch so that Fswitch tracks the PSFB input voltage, e.g., using linear control. By using linear control, the controller <NUM> may linearly adjust the switching frequency Fswitch of the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD based on the PSFB input voltage or an estimate thereof. The continual Fswitch adjustment trajectory is labelled 'Hold up Trajectory A' in <FIG>.

The controller <NUM> may compare the input voltage Vin to the PSFB converter <NUM> or an estimate of the PSFB input voltage Vin to a voltage threshold and continually adjust the switching frequency Fswitch of the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD if the PSFB input voltage Vin or an estimate of the PSFB input voltage Vin is below the voltage threshold. As explained above, the controller <NUM> may utilize hysteresis to avoid frequent changes in Fswitch for input voltage changes near the voltage threshold. For example, the controller <NUM> may include a comparator with hysteresis and be configured to indicate when the PSFB input voltage Vin or an estimate of the PSFB input voltage Vin drops below a voltage threshold. The continual adjustment of the PSFB switching frequency Fswitch resumes when the comparison result falls outside the hysteresis window.

<FIG> illustrates the discrete and continual Fswitch frequency control techniques shown in <FIG>, as a function of PSFB input voltage. The continual Fswitch control trajectory is labeled 'Trajectory A' in <FIG>, and the discrete Fswitch control trajectory is labeled 'Trajectory B'. Trajectory A maintains constant freewheeling time. Trajectory B implements two voltage windows 'Vin1', 'Vin2' with different frequencies 'Fswitch1', 'Fswitch2', respectively.

<FIG> illustrates an embodiment of the control method implemented by the PSFB controller <NUM> for carrying out Trajectory A in <FIG>, i.e., continual Fswitch adjustment. According to this embodiment, the controller <NUM> continually adjusts the switching frequency Fswitch at which the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD are switched based on the PSFB input voltage Vin by comparing the input voltage Vin or an estimate of the input voltage Vin to a first voltage threshold Vth_1 (Block <NUM>). As explained above, the legs QA/QB, QC/QD of the full bridge <NUM> are switched out of phase to transfer energy from the primary side of the PSFB converter <NUM> to the secondary side. If the input voltage Vin or estimate thereof is below the first voltage threshold Vth_1, the controller <NUM> continually adjusts Fswitch as a function of Vin, e.g., by linear control (Block <NUM>). The controller <NUM> maintains continual adjustment of Fswitch if the input voltage Vin remains below a second threshold Vth_2 (Block <NUM>). If the input voltage Vin rises above the second threshold Vth_2, the controller <NUM> sets Fsw to a nominal frequency Frq_2 (Block <NUM>). The controller <NUM> maintains Fsw = Frq_2 until the input voltage Vin once again drops below the first threshold Vth_1 (Block <NUM>). In some cases, Vth_1 may equal Vth_2 with hysteresis to avoid.

<FIG> illustrates an embodiment of the control method implemented by the PSFB controller <NUM> for carrying out Trajectory B in <FIG>, i.e., discrete Fswitch adjustment. According to this embodiment, the controller <NUM> compares the input voltage Vin or an estimate of the input voltage Vin to the first voltage threshold Vth_1 (Block <NUM>). If the input voltage Vin or estimate thereof is below the first voltage threshold Vth_1, the controller <NUM> lowers the frequency Fswitch at which the legs QA/QB, QC/QD of full bridge switch devices QA, QB, QC, QD are switched to a reduced discrete frequency Frq_1 (Block <NUM>). As explained above, the legs QA/QB, QC/QD of the full bridge <NUM> are switched out of phase to transfer energy from the primary side of the PSFB converter <NUM> to the secondary side. The PSFB switching frequency Fswitch remains set at the reduced discrete frequency Frq_1 if the input voltage Vin remains below a second threshold Vth_2 (Block <NUM>). If the input voltage Vin rises above the second threshold Vth_2, the controller <NUM> sets Fsw to a higher discrete frequency Frq_2 (Block <NUM>). The controller <NUM> maintains Fsw = Frq_2 until the input voltage Vin once again drops below the first threshold Vth_1 (Block <NUM>). In some cases, Vth_1 may equal Vth_2 with hysteresis to avoid.

The switching frequency adjustment implemented by the PSFB controller <NUM> may follow some other trajectory based on the frequency-input voltage relationship.

In the case of digital control, the controller <NUM> may be readily programmed via code to implement any of the Fswitch adjustment techniques described herein or any other trajectory based on the frequency-input voltage relationship of the PSFB converter <NUM>. For example, for Trajectory A in <FIG> and the related method of <FIG>, the controller <NUM> may implement continual Fswitch adjustment by acquiring information about the DC link voltage (Vin), e.g., by direct measurement, estimation, etc. Based on the DC link voltage information, the controller <NUM> performs linear modulation of the PSFB switching frequency Fswitch. For Trajectory B in <FIG> and the related method of <FIG>, the controller <NUM> may implement discrete Fswitch adjustment by storing different Fswitch values, e.g., in a PWM (pulse width modulation) registry. If the PSFB input voltage Vin is less than some value, the controller <NUM> uses a reduced switching frequency Fswitch_min as the PSFB switching frequency. Otherwise, the controller <NUM> uses a maximum switching frequency Fswitch_max as the PSFB switching frequency. The controller <NUM> may base the Fswitch adjustment decision on a simple threshold comparison.

In the case of analog control, additional circuitry may be included in the PSFB converter system for providing PSFB switching frequency control based on input voltage. For example, the controller <NUM> may be a PI (proportional-integral) controller and Vin may be given by a resistor. The controller <NUM> may perform analog modulation based on Vin variation. The analog implementation depends on the specific type of analog controller.

<FIG> illustrates an embodiment of an analog implementation of the PSFB controller <NUM> for implementing the continual Fswitch Trajectory A in <FIG> and related method of <FIG>. According to this embodiment, the controller <NUM> includes a hysteretic comparator <NUM> for indicating whether changes in the input voltage fall within a hysteresis window. The controller <NUM> also includes a PWM controller <NUM> with at least one frequency setting input and a conditioning circuit <NUM> for determining one of the frequency setting inputs of the PWM controller <NUM>. If the input voltage Vin or estimate therefor falls within the hysteresis window, the conditioning circuit <NUM> sets the corresponding frequency setting input of the PWM controller <NUM> to a nominal (higher) frequency. Otherwise, the conditioning circuit <NUM> adjusts the corresponding frequency setting input of the PWM controller <NUM> as a function of the input voltage Vin so as to provide sufficient duty time under reduced input voltage conditions. The input voltage Vin or estimate thereof is an input to the conditioning circuit <NUM> according to this embodiment, so that the conditioning circuit <NUM> can adjust Fswitch as a function of Vin. The PWM controller <NUM> may have more than one frequency setting input, even though only one frequency setting input (from the conditioning circuit <NUM>) is shown in <FIG>.

<FIG> illustrates an embodiment of an analog implementation of the PSFB controller <NUM> for implementing the discrete Fswitch Trajectory B in <FIG> and related method of <FIG>. The embodiment in <FIG> is similar to the embodiment in <FIG>. However, the implementation of the conditioning circuit <NUM> is simpler in <FIG> since the controller <NUM> makes discrete adjustments to Fswitch instead of continual adjustments. As in <FIG>, the hysteretic comparator <NUM> indicates whether changes in the input voltage Vin fall within a hysteresis window. If the input voltage Vin or estimate thereof falls within the hysteresis window, the conditioning circuit <NUM> sets the corresponding frequency setting input of the PWM controller <NUM> to the nominal (higher) frequency. Otherwise, the conditioning circuit <NUM> sets the corresponding frequency setting input of the PWM controller <NUM> to a reduced (discrete) frequency which provides sufficient duty time under reduced input voltage conditions. The input voltage Vin or estimate thereof is not an input to the conditioning circuit <NUM> in <FIG>, since the conditioning circuit <NUM> makes discrete adjustments to Fswitch in this embodiment.

Claim 1:
A phase shift full bridge, PSFB, converter (<NUM>), comprising:
an isolation transformer (<NUM>) having a primary side and a secondary side;
a full-bridge (<NUM>) comprising a first pair of switch devices (QA, QB) connected in series at a first node (A) coupled to a first terminal of the primary side of the isolation transformer (<NUM>), and a second pair of switch (QC, QD) devices connected in series at a second node (B) coupled to a second terminal of the primary side of the isolation transformer (<NUM>);
a rectifier (<NUM>) coupled to the secondary side of the isolation transformer (<NUM>);
an output filter comprising an output inductor (Lo) and an output capacitor (Co) coupled to the rectifier (<NUM>); and
a controller (<NUM>) configured to switch the first and the second pairs of switch devices (QA, QB, QC, QD) out of phase with each other,
characterised in that
under nominal input voltage conditions for the PSFB converter (<NUM>), the controller is (<NUM>) configured to switch the first and the second pairs of switch devices (QA, QB, QC, QD) at a nominal switching frequency, and
under reduced input voltage conditions for the PSFB converter (<NUM>), the controller (<NUM>) is configured to switch the first and the second pairs of switch devices (QA, QB, QC, QD) at a frequency lower than the nominal switching frequency.