Patent Description:
<CIT> relates to a method of a PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth.

<CIT>relates to a PLL circuitry in a FMCW system for generating a frequency chirp.

<CIT> relates to a PLL for generating a radar chirp using fast chirp modulation schemes.

<CIT> relates to a PLL for generating a radar chirp using fast modulation schemes while maintaining low phase noise.

<FIG> illustrate techniques for improving the performance of an FMCW radar system by injecting a calibrated current at the FMCW generator during the reset portion and acquisition portion of each chirp period. In particular, the FMCW generator employs "gear-switching" to reduce PLL bandwidth during an acquisition phase and to increase the PLL bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.

In at least one embodiment, the PLL circuit employs a current injector (e.g., a current injection digital-to-analog converter (DAC)) to inject current at the LPF capacitors of the PLL circuit. During a calibration period of the radar system, the amount of current provided by the current injector is calibrated to achieve a specified frequency bandwidth for the PLL circuit during normal operation. For example, in at least one embodiment, during the calibration period, the PLL circuit is placed in a closed loop configuration and is operated at the specified frequency bandwidth. The LPF capacitors are fed by a set of buffers of the current injector. However, the injection current is not used to feed the PLL circuit; instead, the injection current is compared to the buffer current being provided to the LPF capacitors, and the level of the injection current is adjusted until it closely matches the current provided by the LPF capacitors during a closed loop operation. A chirp injection current profile is thus set for an effective charge pump current along the chirp slope, resulting in an accurate level of injection current that accounts for variables such as temperature and process variations, non-linearity of the PLL voltage control oscillator, and the like.

<FIG> is a block diagram of a radar system <NUM> employing a FMCW generator <NUM> according to some embodiments. The radar system <NUM> is generally configured to generate an output signal <NUM> (also referred to as a radar signal) that is reflected from an object as reflected signal <NUM>. Based on the reflected signal <NUM>, the radar system <NUM> determines the distance of the object from the system, or from a device including the radar system <NUM>. Accordingly, the radar system <NUM> can be employed in a wide variety of devices to, for example, identify when a device is within a threshold distance of an object. For example, the radar system <NUM> can be employed in a proximity sensor incorporated in an automobile to provide feedback to a driver, and in particular to indicate when the automobile is close to an object.

To support generation of the radar signal <NUM> and determination of the distance to the object, the radar system <NUM> includes the FMCW generator <NUM>, antennas <NUM> and <NUM>, a low noise amplifier <NUM>, a mixer <NUM>, a low-pass filter <NUM>, and a power amplifier <NUM>. The FMCW generator <NUM> employs a PLL, described further below, is configured to generate a signal that is supplied to the power amplifier (PA) <NUM>, which amplifies the received signal to generate the radar signal <NUM>. As described below, the FMCW generator <NUM> uses the PLL to generate a chirp sequence which provides a frequency ramp that forms the radar signal <NUM>. The antenna <NUM> transmits the radar signal <NUM> in the proximity of the radar system <NUM> including towards the object that reflects the signal as reflected signal <NUM>.

The FMCW <NUM> provides the PLL output signal to the mixer <NUM>. The receiver antenna <NUM> conveys the reflected signal <NUM> pulse to the low-noise amplifier (LNA) <NUM>, which amplifies the reflected signal and provides the amplified signal to the mixer <NUM> The mixer <NUM> then mixes the FMCW signal with the amplified reflected signal <NUM> and provides the mixed signal to the low-pass filter (LPF <NUM>). Based on the mixed signal, the LPF <NUM> generates an output signal indicative of the distance of the object. For example, in at least some embodiments the frequency of the output signal of the LPF <NUM> is proportional to the distance to the object.

The resolution of the distance indicated by the output signal is based on the frequency bandwidth of the output signal of the FMCW <NUM>, as indicated by the following formula: <MAT> where dr is the resolution, c is the speed of light, and BWchirp is the bandwidth of the output signal of the FMCW <NUM>. Accordingly, to support good distance resolution, in operation the FMCW <NUM> is configured to repeatedly sweep the output signal across a specified frequency range. Each sweep takes place during a period of time referred to as a chirp period, and each chirp period, as described further below, is composed of an acquisition portion, during which the signal is swept over the frequency bandwidth, and a reset portion during which the PLL is reset to an initial state so that another frequency sweep can be initiated. During the reset period, the PLL consumes system resources (such as power) but the radar system <NUM> is unable to determine distance to the object. Accordingly, it is typically desirable to reduce the length of the reset period, the dwell phase time, and a settling time.

Accordingly, to reduce the reset period, the FMCW <NUM> is configured to employ an injection current and gear switching, wherein during each acquisition phase the bandwidth of the PLL circuit is maintained at a relatively low level by providing relatively high capacitance from a set of PLL low pass filter (LPF) capacitors and relatively low current from a PLL charge pump. During each reset portion the configuration of the PLL is changed so that the LPF capacitors provide a relatively low capacitance and the charge pump provides a relatively high level of current, thus setting the PLL bandwidth to a relatively high level. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system <NUM> while maintaining good performance.

<FIG> is a block diagram of a PLL circuit <NUM> for use in a radar system according to some embodiments. In some embodiments, the PLL circuit <NUM> is employed within the FMCW generator <NUM> of the radar system <NUM> of <FIG> to generate a chirp sequence. The chirp sequence provides a defined frequency ramp which is used to create the radar signal <NUM> for the radar system <NUM>. The PLL circuit <NUM> includes a phase frequency detector (PFD) <NUM>, charge pump (CP) <NUM>, a low-pass filter (LPF) <NUM>, a voltage controlled oscillator (VCO) <NUM>, and a divider <NUM>. Together, these components form a feedback loop so that the output signal ωout has a fixed frequency and phase relationship to a reference signal ωref. To illustrate, the VCO <NUM> generates the output signal ωout, based on a signal Vtune. To generate the signal Vtune the PFD <NUM> measures the difference between, comparing the frequency of a signal ωdiv to a frequency of the reference signal ωref. The reference signal ωref is a signal having a constant and known frequency. Based on the difference in the frequency of the input signals, the PFD <NUM> provides an error signal designated "Up, Down", to the CP <NUM>. Based on the error signal, the CP <NUM> increases or reduces the charge of a signal designated "Icp" and provides the Icp signal to the LPF <NUM>, which filters the Icp signal to generate the signal Vtune.

In some embodiments, the output of the VCO <NUM> ωout is provided to the divider <NUM> which changes the frequency of the VCO <NUM> output signal ωout to generate the signal so that the signal ωout has a divided frequency with respect to the signal ωout. is then provided to the PFD <NUM>. The PFD <NUM> performs actions to adjust the VCO <NUM> to make sure the output frequency ωout is correct based on its measurement of the divided frequency ωdiv. As discussed below, in some embodiments, the PFD <NUM> adjusts the output frequency of the VCO <NUM> through the CP <NUM> and the LPF <NUM>.

As discussed above, the VCO <NUM> provides an output signal with an output frequency ωout that is divided by the divider <NUM> which sends the divided signal with the divided frequency ωdiv to the PFD <NUM>. In at least one embodiment, the PFD <NUM> measures the divided frequency against the reference signal ωref to correct frequency variations from the reference signal ωref. In some embodiments, the PFD <NUM> reacts to variations from the reference signal ωref and provides up/down signals to the VCO <NUM> to effect the changes in its output frequency ωout. In at least one embodiment, the CP <NUM> performs this correction by outputting a charge current Icp to the LPF <NUM> which then submits a tuning voltage Vtune to the VCO <NUM>. Thus, in some embodiments, the VCO <NUM> is controlled by the tuning voltage Vtune. In an example when the PFD <NUM> observes the output frequency ωout, via the divided frequency ωdiv, is too low when compared to the frequency of the reference signal ωref, the PFD <NUM> provides an up instruction to the CP <NUM>, which in turn causes the LPF <NUM> to provide a positive voltage to the VCO <NUM>, thereby causing the VCO <NUM> to increase its frequency. In another example, the LPF <NUM> provides a negative voltage to the VCO <NUM> in response to a down instruction from the PFD <NUM> to the CP <NUM> when the PFD <NUM> observes the output frequency ωout is high when compared to the frequency of the reference signal ωref.

Similarly, in another example when the PFD <NUM> observes the output frequency ωout, via the divided frequency ωdiv, is too high when compared to the frequency of the reference signal ωref, the PFD <NUM> provides a down signal to the CP <NUM> which sends a negative charge current Icp to the LPF <NUM>. As a result, the LPF <NUM> provides a negative tuning voltage Vtune to the VCO <NUM> to cause the VCO <NUM> to decrease its frequency ωout. As can be observed, in at least one embodiment, the control of the output of PLL circuit <NUM> can be accomplished simply by changing the value by which the divider <NUM> divides, or in some instances, multiplies the output of the VCO <NUM> before feeding the divided frequency ωdiv to the PFD <NUM>.

In some embodiments, the LPF <NUM> includes, as illustrated within the box defined by long, dashed lines of <FIG>, a buffer <NUM> connected with a bank of capacitors <NUM> including first and second capacitors <NUM> and <NUM>. First and second capacitors <NUM> and <NUM> can represent one or more capacitors grouped together within the arrangement in the PLL <NUM>. In some embodiments, the buffer <NUM> acts to copy a voltage, which as illustrated in <FIG>, is the tuning voltage Vtune from within the VCO <NUM> itself after the charge current Icp is received from the CP <NUM>. In some embodiments, the buffer <NUM> receives the tuning voltage Vtune at its non-inverting input, designated by the "+" sign. The buffer <NUM> also receives its own output at its inverting input, designated with a "-" sign. In some embodiments, the output from the buffer <NUM>, called the buffer current Ibuf, is provided to the digital search engine <NUM> during a calibration phase to be measured. In effect, the calibration results in current injection values equivalent to a CP current that effectively creates a frequency ramp for the chirp. During an operational phase, the buffer current Ibuf is provided to the first capacitors <NUM> of the capacitor bank <NUM> by the injection DAC <NUM>, as described further below. In some embodiments, the buffer current Ibuf is provided according to a chirp injection current profile which was determined by the calibration phase.

In operation, the LPF <NUM> also removes noise and unwanted frequencies that may occur and that may distract the PFD <NUM>. In some instances, the reference signal ωref could be noisy while in other instances, the PFD <NUM> itself may introduce noise. In some embodiments, the LPF <NUM> also acts to stabilize the PLL circuit <NUM> itself by changing the PLL circuit's response to transients. While in some examples, it may be preferable to have a slow frequency change, necessitating a narrow loop bandwidth, in the PLL circuit <NUM> in other instances, a fast PLL circuit response, requiring a wide loop bandwidth, may be desired. As discussed further below, gear switching includes changing the capacitance of capacitors, such through as the capacitor bank <NUM>, within the LPF <NUM> can effectuate these changes in PLL circuit <NUM> bandwidth, along with adjusting the charge pump current.

Additional elements, such as the divider <NUM> can help the PLL circuit <NUM> produce different frequencies by changing the input given to the PFD <NUM>. In operation, the divider <NUM> gives the PLL circuit <NUM> the ability to produce frequencies different than that of the reference signal ωref. For example, if a <NUM> reference signal is provided as the reference signal ωref and it is desired for the PLL circuit to output a frequency ωout of <NUM>, the divider would divide the ωout frequency from the VCO <NUM> by a factor of <NUM>. The result of this division would result in the PFD <NUM> observing a nominal <NUM> output from the VCO <NUM> and measuring that frequency against the reference signal ωref. Thus, in this example, if the VCO <NUM> were to output a <NUM> signal, the PFD <NUM>, would observe that the divided frequency ωdiv is a <NUM> signal and the PFD <NUM> would begin signaling the CP <NUM> with a down signal to start lowering the tuning voltage Vtune provided to the VCO <NUM> to slow down its output frequency ωout.

In addition, as discussed above, the PFD <NUM> is provided with the reference frequency ωref and a divided frequency ωdiv output from the divider <NUM>. The PFD <NUM> provides an up, down signal to the CP <NUM> based on the deviation of the divided frequency ωdiv from the reference frequency ωref. The CP <NUM> outputs a charge current Icp to the LPF <NUM> which then submits a tuning voltage Vtune to the VCO <NUM>. Thus, the VCO <NUM> is controlled by the tuning voltage Vtune. Before the chirp sequence in the operational phase, the tuning voltage is set to a starting value Vtune_start to ensure the chirp starts at a proper frequency. In some embodiments, as discussed below the PLL circuit <NUM>, through the injection DAC <NUM> and the divider <NUM> creates frequency chirps through the VCO <NUM> that start at a start frequency fstart and the tuning voltage Vtune starting value of Vtune_start.

Thus, the PLL circuit <NUM> is able to create different output signals having different output frequencies ωout. As discussed above, in some embodiments, the PLL circuit <NUM> creates a frequency ramp for use in radar systems employing, for example, the FMCW generator <NUM> of <FIG>, to provide a frequency chirp to supply the signal needed for the frequency sweep being output as a signal across a specified frequency range. A frequency chirp output from the PLL circuit <NUM> in the FWCW generator <NUM> will form the radar signal being amplified by the PA <NUM> and then emitted by the antenna <NUM>. In some embodiments, to generate this frequency chirp, the chirp timing engine <NUM> within the PLL circuit <NUM> organizes the various elements of the PLL circuit <NUM> to employ both gear switching and a calibrated injection current via a chirp injection current profile. The use of gear switching allows the PLL circuit <NUM> is change its bandwidth as necessary. The use of the calibrated injection current profile further refines the accuracy of the frequency ramp for the frequency chirp in the acquisition phase. In some embodiments, the chirp timing engine <NUM> controls the injection DAC <NUM> to create the frequency ramp via the chirp injection current profile provided to the PLL capacitors <NUM> of the LPF <NUM>. That is, the chirp injection current profile is the current output by the injection DAC <NUM> to create an accurate frequency ramp for a chirp in the acquisition phase. In some embodiments, the chirp timing engine can control the capacitance values of the capacitors in the capacitor bank <NUM> of the LPF <NUM> to further change the bandwidth of the PLL circuit <NUM>. In some examples, the chirp timing engine <NUM> introduces a programmable delay that can be advanced or delayed as required for an optimal timing for the chirp and to account for possible delays arising between analog and digital elements of the PLL circuit <NUM> system.

In some embodiments, the chirp timing engine <NUM> also performs calibration of the injection current to create the calibrated injection current for the functional chirp which may be referred to as a chirp injection current profile. In a calibration operation of the PLL circuit <NUM>, the PLL is closed and operates at the intended bandwidth for the chirp. In addition, first capacitors, such as the first capacitors <NUM> of the LPF <NUM> which are fed by a buffer current, as in a normal chirp operation. Next, an injection current is compared to a buffer current Ibuf in the PLL capacitors <NUM>. As explained below, the digital search engine <NUM> tracks the injection current to the buffer current to ultimately create the chirp injection current profile based on the injection current and measured buffer current.

In some embodiments, after the calibration phase is finished, the chirp timing engine <NUM> provides the injection settings, or the calibrated chirp injection current profile, to the injection DAC <NUM> to be used in the operational phase. As discussed above, the timing engine <NUM> can coordinate the analog and digital portions of the PLL circuit <NUM> to provide an accurate frequency sweep in the acquisition timing portion of the chirp and to reduce settling time and reset time within the chirp cycle. In some embodiments, in the operational chirp phase, the chirp timing engine <NUM> directs the injection DAC <NUM> to adjust its output to feed a current into the PLL capacitors <NUM> of the capacitor bank <NUM> of LPF <NUM> used as a part of the PLL <NUM> to create the frequency ramp from the start frequency fchirp,start to the stop frequency fchirp,stop, as well as reducing the reset phase period.

Thus, embodiments of the invention perform a calibration phase to determine injection current values that are equivalent to an effective charge pump current along the desired chirp slope of the PLL circuit <NUM>. The chirp timing engine <NUM> can then use the resulting chirp injection slope profile to control the elements of the PLL circuit <NUM>, including the injection DAC <NUM>, the divider <NUM>, CP <NUM>, and LPF <NUM> to create the frequency chirp during an operational phase. The frequency chirp is therefore initiated with a current profile that will reduce reset and settling time. In doing so, embodiments of the invention can account for chirp parameters and process and temperature variations, as well as non-linearity or other errors that may occur within the VCO <NUM>. Furthermore, the calibration phase is performed in closed loop under the same conditions as the actual closed loop condition of the chirp process itself. In some embodiments where the closed loop system PLL is used to generate the FCMW signal, the chirp timing engine <NUM> preforms an error analysis is to determine which bandwidth is needed to guarantee a certain frequency error of its control system. Thus, the calibration process avoids additional costs that may arise from an open loop calibration of the PLL circuit <NUM> and is autonomous, not requiring additional external communications or assistance, which reduces the complexity of the system and time necessary to calibrate the PLL <NUM>.

In at least one embodiment, the LPF <NUM> includes a capacitor bank <NUM>. In some embodiments, the capacitor bank <NUM> includes first capacitors <NUM> and second capacitors <NUM> which are connectable as part of the PLL of the PLL circuit <NUM>. It can be appreciated that the capacitor bank can includes any number of different capacitors which can be switched as desired from the PLL to a buffer <NUM> in operation. In one embodiment, the first capacitors <NUM> are charged by the buffer current Ibuf provided by the buffer <NUM>. <FIG> illustrates the capacitors <NUM> and <NUM> can be connected to the PLL as illustrated via the dashed lines. In at least one embodiment, as discussed below in <FIG>, the various capacitors <NUM> and <NUM> of the capacitor bank <NUM> will be switched on command to be connected to either one of the PLL <NUM> or the buffer <NUM>.

As discussed further below, in some embodiments, there are two loop configurations, a high bandwidth configuration and a low bandwidth configuration. These configurations are achieved by connecting a low capacitance, where in some examples the second capacitor <NUM> has a lower capacitance value, and a high capacitance, where in some examples, the first capacitor <NUM> has a higher capacitance value, in the loop. The other capacitance (i.e., the capacitors not used in the loop at that time) is charged by the buffer <NUM>.

In the calibration phase, the smaller dashed lines show the CP current Icp is provided to the PLL via capacitor <NUM>. In addition, in the calibration phase, the first capacitors are fed by the buffer current Ibuf as shown by the long-short, dashed lines. During the calibration phase, the injection DAC <NUM> is not providing a current to feel the PLL but instead it is being compared to the resulting buffer current Ibuf by the digital search engine <NUM>. The profile generated by the digital search engine <NUM> is then used to generate a calibrated chirp injection current profile for the PLL circuit <NUM> during an operational phase. In some embodiments, the chirp injection current profile matches a charge pump current from the CP <NUM> that produces the desired chirp slope. After the calibration phase, in the operational phase, the digital search engine <NUM> communicates with the chirp timing engine <NUM> to provide the resulting chirp injection current profile so the chirp timing engine can direct the injection DAC <NUM> to use the chirp injection current profile for injection of a calibrated current into the LPF <NUM>.

Next, in some embodiments, in the operational phase, the first capacitors <NUM> and second capacitors <NUM> switch places, as the first capacitors <NUM> are used in PLL <NUM> and the second capacitors <NUM> are fed by the buffer current Ibuf from the buffer <NUM>. In the operational phase, the DAC current idac from the injection DAC <NUM> is provided to first capacitors <NUM> while second capacitors <NUM> are charged (through the buffer <NUM>) to a same voltage as Vtune. During the reset phase, the second capacitors <NUM> will be used for high PLL bandwidth mode and because the second capacitors <NUM> are pre-charged to a same voltage as the Vtune signal, this transition will happen fast and without any glitching or settling. In addition, the digital search engine <NUM> is disabled. In addition, the current required to generate a desired chirp slope is available in digital search engine <NUM> as generated profile for the chirp.

<FIG> illustrate the different bandwidth configurations of the PLL circuit <NUM> of <FIG> during the calibration, acquisition, and reset phases in accordance with some embodiments. <FIG> is an illustration of the PLL circuit <NUM> in a high bandwidth configuration. In some embodiments, the high bandwidth configuration occurs during the calibration phase. During the calibration phase, no output signal is transmitted. In the calibration phase, the PLL is locked and the VCO tuning voltage Vtune is shaped by the loop in order to produce an intended frequency ramp at the VCO output. This frequency ramp is represented as a calibration ramp <NUM> for the calibration phase. In addition, the buffer <NUM> is copying the Vtune ramp on capacitor <NUM>. The copy of the buffer output current Ibuf is provided to an ADC provided in the IDAC, or injection DAC, <NUM>. In some examples, the buffer output current Ibuf may be referred to as a test current. In addition, the calibration ramp <NUM> has an opposite shape from the ramp of the functional chirp <NUM>. That is, in some embodiments, the calibration ramp is reversed from the intended frequency ramp. By reversing the calibration ramp, the buffer current Ibuf is the same as during the acquisition phase. In addition, the calibration loop settles at the start frequency for the acquisition phase. Accordingly, settings for the injection DAC <NUM> are thus set at the proper calibration points.

During the calibration phase, the IDAC <NUM> works to match the current from the first capacitors <NUM> which is needed to produce the intended frequency ramp at the VCO output during the acquisition phase. The calibration phase also provides the reset phase injection current after applying a correction factor by the digital engine. In some examples, the accuracy for the reset phase calibration current is less demanding than that required for the acquisition phase injection current. As such, application of the correction factor itself is sufficient for the reset injection current. During the dummy chirp of the calibration phase, capacitor <NUM> is charged by Vtune through the buffer <NUM> and the buffer current Ibuf provided by the buffer <NUM> is extracted, from which a chirp current profile is derived, which is representative of the chirp slope for the intended frequency ramp. This current is typically constant during the dummy chirp and injection DAC <NUM> is calibrated to this current. Although, in some examples, the current may include non-linearities, and other deviations such as temperature, for which the calibration compensates.

<FIG> is an illustration of the PLL in a low bandwidth configuration. In some embodiments, the low bandwidth configuration is for the acquisition phase which takes place after the calibration phase is complete. In this example, the PLL has switched from the high bandwidth mode to a low bandwidth mode. In the acquisition phase, the first capacitors <NUM> are connected to the PLL and the PLL is operating at its intended start frequency. In addition, the injection DAC <NUM> outputs a current idac that matches the current needed to shape the first capacitors <NUM>'s voltage in order to produce the intended frequency ramp at the VCO output as illustrated by the first acquisition chirp ramp <NUM>.

<FIG> is an illustration of the PLL in a high bandwidth mode during the reset portion of the chirp. During the reset portion <NUM>, the frequency of the PLL is returned to its starting frequency as illustrated by the reset ramp <NUM>. In this example, the PLL switches to the high bandwidth mode where capacitor <NUM> is in the PLL. When the reset portion is complete, the next chirp cycle can start. Because of the calibration phase <NUM>, in some embodiments, multiple chirp cycles can be repeated without another calibration until the chirp parameters or other environmental factors affect the PLL's performance change.

<FIG> is an illustration of creating a frequency chirp with certain frequency bandwidth (FMCW) signal as performed by some embodiments of the FMCW circuit <NUM> of <FIG> and employing the PLL circuit <NUM> of <FIG>. In some embodiments, an operational chirp is produced in the operational phase, or chirp sequence. Thus, in <FIG>, the operational phase described above with respect to the PLL circuit <NUM> of <FIG> is illustrated.

<FIG> illustrates the process <NUM> of producing a chirp sequence containing two consecutive chirp signals by the PLL circuit <NUM> of <FIG>. The first chirp signal includes a ramp up region which begins at a start frequency fchirp,start <NUM> and then the frequency of the chirp increases at certain rate until it reaches the stop frequency fchirp,stop <NUM>. As can be observed, the first chirp cycle begins in a dwell phase that ends at the time marked tdwell,<NUM> <NUM> for the dwell phase. The acquisition phase begins at the start frequency fchirp,start <NUM>. Within the acquisition phase, a settle period takes place which ends at tsettle,<NUM> <NUM> for the first chirp cycle. At the end of the acquisition phase, which occurs when the first chirp reaches the stop frequency fchirp,stop <NUM>, the reset phase begins as shown at treset. During the reset phase, the frequency of the PLL circuit is reduced from the stop frequency fchirp,stop to the start frequency fchirp,start, as illustrated at <NUM>. The reset phase ends at <NUM> and the second chirp cycle starts at <NUM> with tdwell,<NUM> leading to the second acquisition phase and the second settle portion tsettle,<NUM> at <NUM> until the next treset at <NUM>. During the chirp cycles, tN,ADCsamples show the portion of the acquisition phases from which useful data can be collected, such as by an analog-to-digital converter (not shown) that is employed by the radar system <NUM> to process the output signal from the LPF <NUM>.

In an operation of a radar system employing PLL circuit <NUM> of <FIG>, for example, the ramp up region, as illustrated for example with a dashed line and marked as "window activates", is utilized to extract information from the reflected radar signal. The extracted information can include information about distance, speed, and acceleration. This region forms the acquisition region, because this portion of the chirp cycle when the radar system can acquire useful data. The reset time is required by the PLL circuit after the ramp-up region to bring the frequency of the PLL circuit, in this case the frequency being output by the VCO <NUM> of <FIG>, back to the start frequency. In addition, a dwell time is necessary because time is also required for the PLL circuit to be ready to initiate the next ramp-up phase once the PLL circuit is back to the start frequency fchirp,start. In addition, a settle time within the ramp-up region is another period of time likewise required before the actual acquisition phase begins. The reset slope determines the phase noise performance of the PLL circuit. During the reset phase, gear switching is employed to increase the PLL bandwidth. In some examples, the PLL bandwidth is increased by a factor of <NUM>. In additional embodiments, the injection DAC <NUM> of <FIG> would introduce a calibrated injection current, or chirp injection current profile, to further reduce the settling time. Ideally, the chirp reset time and settling time should be as short as possible in order to reduce the total period of time necessary to produce the frequency chirp as this would effectively result in a better dynamic range of the radar system and lower power consumption. If the reset slope increases while PLL bandwidth is kept constant, the phase difference during the reset phase will increase, where the dynamic range of a phase frequency detector-charge pump, such as the PFD <NUM> and CP <NUM> of <FIG>, will be reached and a cycle-slip will occur, meaning that the reset time in a closed loop system would take longer than if the PLL bandwidth was increased.

<FIG> is an illustration of creating a frequency chirp signal <NUM> in embodiments of the PLL circuit <NUM> of <FIG>. <FIG> illustrates the concepts of gear switching and injection current calibration that have thus far been discussed and how these techniques are used to reduce the reset time and settling time of a frequency chirp cycle within a PLL circuit, such as the PLL circuit <NUM> of <FIG>, and as further shown in the chirp signals <NUM> of <FIG>. Referring to <FIG>, the PLL circuit signal <NUM> is an example of a frequency chirp cycle and the chirp's frequency is shown changing across a time period for two chirp cycles to occur. Thus, the acquisition phase begins, as illustrated with the time <NUM>, and ends at time <NUM>. After the time marked <NUM>, the reset phase begins, and continues until time <NUM>. As discussed below, various changes take place to make this portion of the frequency chirp cycle as short as possible. Next, as illustrated between time <NUM> and time <NUM>, the dwell phase takes place. Time <NUM> illustrates the start of another acquisition phase that ends at time <NUM>. The settling time is also illustrated as taking place between time <NUM> and the portion illustrated by reference number <NUM> on the time axis.

In some embodiments, referring to the PLL circuit <NUM> of <FIG>, the chirp timing engine <NUM> instructs the LPF <NUM> to change the capacitance of the second capacitors <NUM> within the capacitor bank <NUM>. In addition, the CPO <NUM> issues a charge pump current. In some embodiments, the injection DAC <NUM> provides an injection current according to the chirp injection current profile to the LPF <NUM>. In some embodiments, the chirp timing engine <NUM> also controls the CPO <NUM>, LPF <NUM>, VCO <NUM>, and other elements of the PLL circuit <NUM> during the chirp cycle according to the chirp injection current profile. In this example, the second capacitors <NUM> include three separate capacitors that are variably connected in the PLL <NUM> or the buffer <NUM>, resulting in variable capacitance values C1, C2, and C3, the capacitance values of which are illustrated by the time marked <NUM>. In some embodiments, the acquisition phase calibration of the injection current is individually performed for each of capacitors C1, C2, and C3. The individual calibrations for capacitors C1, C2, and C3 are performed in parallel during the same calibration phase. In other embodiments, individual capacitors of capacitors C1, C2, and C3 can be omitted from the calibration sequence, such as in examples where a capacitance value of one of the capacitors C1, C2, and C3 is relatively small compared to system performance.

<FIG> further illustrates the bandwidth of the PLL circuit at the time marked <NUM>. In some embodiments, the gear switching achieves a low PLL bandwidth <NUM> during an acquisition phase, as illustrated by the region between times <NUM> and <NUM>. The low PLL bandwidth <NUM> is achieved by employing a high capacitance value <NUM> at capacitors C1, C2, and C3 and a low charge pump current <NUM>. In addition, during the reset phase, as illustrated by the region between time <NUM> and <NUM>, a high PLL bandwidth <NUM> is induced by switching the capacitance values <NUM> of capacitors C1, C2, and C3 to a low value while increasing the charge pump current <NUM> to a high value. In at least one embodiment, the capacitance switching is performed by connecting and disconnecting some of the capacitors to be part of the PLL while others are charged by the buffer current. In some embodiments, during the reset phase, <NUM>/8th of the LPF's capacitor bank <NUM> will be part of the PLL and the remaining <NUM>/<NUM>th of the capacitance value will be charged by the buffer current. Similarly, in some embodiments, during an acquisition phase, <NUM>/<NUM>th of the capacitance value is part of the PLL while the remaining <NUM>/<NUM>th is charged by the buffer current.

In some embodiments, the chirp timing engine <NUM> controls the injection DAC <NUM> of the PLL circuit <NUM> of <FIG> to further reduce the settling time of the ramp-up phase and the rest time of the reset phase. The injection DAC current <NUM> is provided to each capacitor C1, C2, and C3 to create an accurate voltage ramp during the ramp-up phase. As discussed above, the ramp-up phase includes the settle phase and the acquisition phase. The injection current <NUM> has a first value during the dwell phase, a second value during the settle phase and acquisition phase of the ramp up phase, and then a third value for the reset phase. In some examples, as the first value occurs during the dwell time portion, the first value may be zero as the slope is zero at that time. The values of the injection current <NUM> shift from an initial value, such as the first portion illustrated before time <NUM>, to an injection current value for the reset phase -Iinj_reset value, as illustrated in the reset phase shown, for example, between times <NUM> and <NUM> and then again after time <NUM>. Next, an injection current value for the acquisition phase, an +Iinj_acq value is illustrated between times <NUM> and <NUM> and again between times <NUM> and <NUM>. In some embodiments, the injection current values <NUM> are calibrated to achieve a minimal settling time independent of chirp settings, programmed PLL bandwidth, Kvco, and other process variations, such as the temperature. Furthermore, the calibrated injection current values <NUM>, provided at an accurate time within the ramp up phase, generate the desired chirp slope of the acquisition phase.

<FIG> is a flow diagram illustrating a method <NUM> of generating a chirp injection current profile. The method <NUM> is implemented in some embodiments of PLL circuit <NUM> shown in <FIG>.

In some embodiments, the injection DAC <NUM> of <FIG> is switched or directed to measure the current in a buffer <NUM> within the LPF <NUM>, including the first capacitors <NUM> of the LPF <NUM>. The buffer current is representative of the chirp slope of the dummy chirp during the calibration phase. The injection DAC current idac is searched until it is equal to the buffer current Ibuf, meaning that it is equivalent to the chirp slope. To begin the calibration phase, at block <NUM>, the PLL main loop is set to a high PLL bandwidth where the capacitance is in a low capacitance value mode, as previously illustrated, for example, in <FIG> discussed above. On the LPF <NUM> buffer side, a high capacitance value is provided. Next, at block <NUM>, the dummy chirp is executed which provides a representative current. As discussed below, this current is used to set the chirp injection profile.

At block <NUM>, the resulting current in the buffer <NUM> is tracked and measured. In some embodiments, this measurement can produce a chirp current injection profile similar to the illustrated example of <FIG> where the injection current is derived from the buffer current. At block <NUM>, the measured buffer current is used to generate the chirp current injection profile based on the measured buffer current. As discussed above, the timing engine <NUM> of <FIG> uses the chirp injection current profile as well as gear switching settings when applicable to direct the operation of the injection DAC <NUM>, CPO <NUM>, LPF <NUM>, VCO <NUM>, and other elements of the PLL circuit <NUM>.

<FIG> is a flow diagram illustrating a method <NUM> of executing a chirp using gear switching and injection current calibration. The method <NUM> is implemented in some embodiments of PLL circuit <NUM> shown in <FIG>. At block <NUM>, the PLL bandwidth is set to low where a high capacitance mode is engaged, as previously show, for example in <FIG>. In some embodiments, the process of gear switching includes changing the values of used capacitances in a low pass filter as illustrated, for example, with the capacitance values <NUM> of C1, C2, and C3 shown in <FIG>.

In some embodiments, the chirp injection current profile is obtained at block <NUM>. In some embodiments, the chirp injection current profile was determined as illustrated in method <NUM> of <FIG>. In block <NUM>, the chirp timing engine is programmed based on the chirp injection profile. In block <NUM>, the chirp is executed. In some embodiments, the chirp matches the execution as shown in <FIG> where the injection DAC <NUM> of <FIG> supplies an injection current <NUM> according to the chirp injection current profile. In addition, the execution of the chirp provides the execution as illustrated by process <NUM> in <FIG> for as many chirp cycles, having accurate frequency ramps and reset phases, as desired.

<FIG> is a flow diagram illustrating a method <NUM> of executing a chirp using gear switching and injection current calibration. The method <NUM> is implemented in some embodiments of PLL circuit <NUM> shown in <FIG>. At block <NUM>, it is determined whether the PLL circuit calibrated. If the PLL circuit is not calibrated, meaning the chirp injection profile is current, then at block <NUM> the PLL is placed into the calibration configuration and then the buffer current is tracked in block <NUM> where the current is measured at the buffer output and equalized (calibrated) buffer current to measure the buffer current to generate the calibrated chirp injection profile. In some embodiments, the PLL may be considered calibrated for a predetermined number of chirp cycles. In some other embodiments, a change in operating conditions for the PLL may be observed, such as a change in temperature, and the PLL would then be considered not calibrated. The calibration phase of blocks <NUM> and <NUM> reflect, in some embodiments, the method <NUM> of <FIG> where a dummy chirp is employed to generate a chirp injection current profile.

In some embodiments, where it is determined the PLL circuit <NUM> is calibrated, method <NUM> proceeds to block <NUM>, for an active chirp cycle, where the current status of the chirp process is evaluated. That is, block <NUM> determines whether the active chirp is in the settle and acquisition phase (Tsettle+Acq) or in the reset and dwell phase (Reset+Tdwell). In the reset and dwell phase portion of the functional chirp phase, which corresponds to the beginning step of a chirp process, the PLL bandwidth is set to high at block <NUM>. In addition, at block <NUM>, the low pass filter capacitance is set to low and the charge pump current is high. As discussed above, and as illustrated by the capacitance values <NUM> in <FIG>, the first capacitance ratio value is the same value for the dwell phase and the ramp up phase In some embodiments of the dwell and acquisition phases, <NUM>/<NUM>th of the capacitance value of the capacitance bank <NUM> is provided to the PLL while the remaining <NUM>/<NUM>th value is charged by the buffer current. At block <NUM>, in some embodiments, in order to effect a rapid reset portion, an inverted current is injected at the start of Treset until the dwell time. In additional embodiments, a correction factor related to the inversion is applied. Upon completion of the dwell phase, method <NUM> returns to block <NUM> to evaluate the next step of the chirp process.

At block <NUM>, when it is determined that the reset and dwell phase has been completed, method <NUM> proceeds to block <NUM>. As discussed above and reflected in the capacitance value variations <NUM> of the LPF <NUM> in <FIG>, the PLL bandwidth is set to a low bandwidth where the LPF <NUM> has a high capacitance value, and the charge pump current is low. In some examples, the second capacitance ratio value may be set to a value where <NUM>/<NUM>th of the capacitance value is part of the PLL while the other <NUM>/<NUM>th is charged by the buffer current as part of the gear switching adjustment of the PLL circuit <NUM>. Next, in block <NUM>, the injection current is applied to the LPF <NUM> at the start of Tsettle until the end of the acquisition phase at Tacq. During the acquisition phase, the antenna <NUM> of <FIG>, for example, would be able to obtain a reflection having useful information from a radar pulse <NUM> emitted by the antenna <NUM> of radar system <NUM>. Next, method <NUM> proceeds to block <NUM> to determine if another function chirp phase will be initiated or if a calibration phase is required.

<FIG> is an illustration of injection current tracking of a test chirp in accordance with some embodiments of the calibration phase of <FIG>, for example, being created by embodiments of the PLL circuit <NUM> of <FIG>, which in some embodiments, is employed in the radar device <NUM> of <FIG>. In the calibration phase of <FIG>, for example, the current from the buffer can be measured. The buffer current is illustrated with the dashed line while the measured representation of the buffer current is the solid line. Various types of measurement and tracking of the buffer current may be employed. In this embodiment, a binary search is used to create an accurate chirp injection current profile for the Injection DAC <NUM> of <FIG> to program the chirp timing engine <NUM> with the chirp injection current profile. Thus, the solid line represents the chirp injection current profile which will be used during the functional chirp to generate the acquisition phase. In some embodiments, the calibration focuses on matching closely the current in capacitor <NUM> needed to generate a voltage slope in order to produce an intended frequency ramp at the VCO <NUM> of <FIG>, for example, that is output during the acquisition phase where an exact current matching is employed. That is, in some embodiments, in the illustration of the chirp cycles <NUM> of <FIG> the resulting chirp injection current profile defines the shape of the injection current <NUM> line.

Such storage media can include, but is not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-Ray disc), magnetic media (e.g., floppy disc , magnetic tape, or magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or Flash memory), or microelectromechanical systems (MEMS)-based storage media.

Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure as set forth in the claims below.

Claim 1:
A method, comprising:
switching a first set of capacitors (<NUM>) of a capacitor bank (<NUM>) of a low pass filter, LPF, (<NUM>) of a phase-locked loop, PLL, (<NUM>) from the LPF to an output of a buffer (<NUM>) during a calibration phase of the PLL, wherein in the calibration phase, a loop of the PLL is locked and a voltage controlled oscillator, VCO, tuning voltage is shaped by the loop in order to produce a calibration ramp (<NUM>) of a dummy chirp at a VCO output,
during the calibration phase, the buffer (<NUM>) of the PLL is copying the VCO tuning voltage on the first set of capacitors resulting in providing the calibration ramp to the first set of capacitors, measuring a buffer output current provided to the first set of capacitors during the calibration phase,
matching a chirp injection current profile with the measured buffer output current,
switching the first set of capacitors from the output of the buffer (<NUM>) to the LPF during an acquisition phase of the PLL,
generating a frequency chirp based on the chirp injection current profile during the acquisition phase of the PLL.