Patent Description:
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.

The integrated circuit industry requires inspection tools with increasingly higher resolution to resolve ever smaller features of integrated circuits, photomasks, reticles, solar cells, charge coupled devices etc., as well as detect defects whose sizes are of the order of, or smaller than, those feature sizes.

Inspection systems operating at short wavelengths, e.g. wavelengths shorter than about <NUM>, can provide such resolution in many cases. In particular for photomask or reticle inspection, it is desirable to inspect using a wavelength identical, or close, to the wavelength that will be used for lithography, i.e. close to <NUM> for current generation lithography and close to <NUM> for future EUV lithography, as the phase-shifts of the inspection light caused by the patterns will be identical or very similar to those caused during lithography. For inspecting semiconductor patterned wafers, inspection systems operating over a relatively broad range of wavelengths, such as a wavelength range that includes wavelengths in the near UV, DUV, and/or VUV ranges, can be advantageous because a broad range of wavelengths can reduce the sensitivity to small changes in layer thicknesses or pattern dimensions that can cause large changes in reflectivity at an individual wavelength.

In order to detect small defects or particles on photomasks, reticles, and semiconductor wafers, high signal-to-noise ratios are required. High photon flux densities are required to ensure high signal-to-noise ratios when inspecting at high speed because statistical fluctuations in the numbers of photons detected (Poisson noise) is a fundamental limit on the signal-to-noise ratio. In many cases, approximately <NUM>,<NUM> or more photons per pixel are needed. Because inspection systems are typically in use <NUM> hours per day with only short stoppages, the sensors are exposed to large doses of radiation after only a few months of operation.

A photon with a vacuum wavelength of <NUM> has energy of approximately <NUM> eV. The bandgap of silicon dioxide is about <NUM> eV. Although it may appear such wavelength photons cannot be absorbed by silicon dioxide, silicon dioxide as grown on a silicon surface must have some dangling bonds at the interface with the silicon because the silicon dioxide structure cannot perfectly match that of the silicon crystal. In addition, because the single dioxide is amorphous, there will be dangling bonds within the material. In practice, there will be a non-negligible density of defects and impurities within the oxide, as well as at the interface to underlying semiconductor, that can absorb photons with DUV wavelengths, particularly those shorter than about <NUM> in wavelength. Furthermore, under high radiation flux density, two high-energy photons may arrive near the same location within a very short time interval (nanoseconds or picoseconds), which can lead to electrons being excited to the conduction band of the silicon dioxide by two absorption events in rapid succession or by two-photon absorption.

A further requirement for sensors used for inspection, metrology and related applications is high sensitivity. As explained above, high signal-to-noise ratios are required. If the sensor does not convert a large fraction of the incident photons into signal, then a higher intensity light source would be required in order to maintain the same inspection or measurement speed compared with an inspection or metrology system with a more efficient sensor. A higher intensity light source would expose the instruments optics and the sample being inspected or measured to higher light intensities, possibly causing damage or degradation over time. A higher intensity light source would also be more expensive or, particularly at DUV and VUV wavelengths, may not be available. Silicon reflects a high percentage of DUV and VUV light incident on it. For example, near <NUM> in wavelength, silicon with a <NUM> oxide layer on its surface (such as a native oxide layer) reflects approximately <NUM>% of the light incident on it. Growing an oxide layer of about <NUM> on the silicon surface reduces the reflectivity to close to <NUM>% for wavelengths near <NUM>. A detector with <NUM>% reflectivity is significantly more efficient than one with <NUM>% reflectivity, but lower reflectivity, and hence higher efficiency, is desirable.

Anti-reflection coatings are commonly used on optical elements such as lenses and mirrors. However, many coating materials and processes commonly used for optical elements are often not compatible with silicon-based sensors. For example, electron and ion-assisted deposition techniques are commonly used for optical coatings. Such coating processes cannot generally be used to coat semiconductor devices because the electrons or ions can deposit sufficient charge on the surface of the semiconductor device to cause electrical breakdown resulting in damage to the circuits fabricated on the semiconductor.

DUV and VUV wavelengths are strongly absorbed by silicon. Such wavelengths may be mostly absorbed within about <NUM> or a few tens of nm of the surface of the silicon. The efficiency of a sensor operating at DUV or VUV wavelengths depends on how large a fraction of the electrons created by the absorbed photons can be collected before the electrons recombine. Silicon dioxide can form a high-quality interface with silicon with a low density of defects. Most other materials including many of those commonly used for anti-reflection coatings, if deposited directly on silicon, result in a very high density of electrical defects at the surface of silicon. A high density of electrical defects on the surface of silicon may not be an issue for a sensor intended to operate at visible wavelengths, as such wavelengths may typically travel about <NUM> or more into the silicon before being absorbed and may, therefore, be little affected by electrical defects on the silicon surface. However, DUV and VUV wavelengths are absorbed so close to the silicon surface that electrical defects on the surface and/or trapped charged within the layer(s) on the surface can result in a significant fraction of the electrons created recombining at, or near, the silicon surface and being lost, resulting in a low efficiency sensor.

<CIT>, <CIT> and <CIT>, all to Chern et al. , describe image sensor structures and methods of making image sensors that include a boron layer deposited on, at least, an exposed back surface of the image sensor. Different ranges of temperature for deposition of the boron are disclosed, including a range of about <NUM>-<NUM> and a range of about <NUM>-<NUM>. The inventors have discovered that one advantage of a higher deposition temperature for the boron, such as a deposition temperature between about <NUM> and about <NUM>, is that at such temperatures boron diffuses into the silicon providing a very thin, heavily p-type doped silicon layer on the light-sensitive back surface. This p-type doped silicon layer is important for ensuring a high quantum efficiency to DUV and VUV radiation because it creates a static electric field near the surface that accelerates electrons away from the surface into the silicon layer. The p-type silicon also increases the conductivity of the back surface of the silicon, which is important for high-speed operation of an image sensor, since a return path is needed for ground currents induced by the switching of signals on electrodes on the front surface of the sensor.

However, processing temperatures higher than <NUM> cannot be used on semiconductor wafers that include conventional CMOS circuits because <NUM> is close to the melting point metals such as aluminum and copper commonly used in fabricating CMOS devices. At high temperatures, such as those greater than <NUM>, these metals expand, become soft and can delaminate. Furthermore, at high temperatures copper can easily diffuse through silicon which will modify the electrical properties of the CMOS circuits. Thinning a wafer before any metals are deposited on it allows a boron layer to be deposited on the back surface as described in the aforementioned patents at a temperature between <NUM> and <NUM> enabling boron to diffuse into the surface during, or subsequent to, the deposition of the boron layer. Subsequently metal interconnects can be formed on the front surface. After the image sensor regions of the wafer have been thinned, for example to a thickness of about <NUM> or thinner, the thinned region can be significantly warped and may have peak-to-valley non-flatness of many tens of microns or more. So, it is necessary to use relatively wide metal interconnect lines and vias, such as multiple microns wide or more, to ensure that the lines and vias connect in spite of any misalignment caused by the non-flatness. Such wide metal interconnects and vias increase the capacitance per unit area associated with those lines and vias. Furthermore, wide interconnects and vias can make it difficult, or impossible, to interconnect all the signals on a large area sensor with about one million or more pixels. In some cases, polysilicon jumpers may be needed to connect together metal interconnects, but polysilicon has much higher resistivity than any metal, so the use of such jumpers can limit the maximum operating speed of a sensor.

<CIT> describes a delta-doping technique for image sensors that may be performed at a temperature of <NUM> or lower. This technique includes a <NUM> cap layer of nominally undoped silicon. This cap layer may be deliberately oxidized or may oxidize due to water and oxygen in the environment. This oxide layer will degrade under high intensity DUV, VUV, EUV or charged-particle radiation and can cause the sensor to degrade.

Therefore, a need arises for an image sensor capable of efficiently detecting high-energy photons without degrading yet overcoming some, or all, of the above disadvantages. In particular, a method of fabricating a back-thinned image sensor with a boron layer and boron doping on its back surface while allowing formation of metal interconnects on a relatively flat wafer (i.e. with a flatness of about <NUM> or less) would allow the use of finer design rules (such as the design rules corresponding to a <NUM> process or finer). Such a method would allow narrower metal lines connecting to critical features such as the floating diffusion, enabling smaller floating-diffusion capacitance and higher charge to voltage conversions ratios. Finer design rules also allow more interconnect lines per unit area of the sensor and allow more flexibility in connecting the circuits on the image sensor.

<CIT> discloses a back-illuminated solid-state imaging element.

Image sensors and methods of fabricating image sensors with high-quantum-efficiency for imaging DUV, VUV, EUV, X-rays and/or charged particles (such as electrons) are described. These image sensors are capable of long-life operation under high fluxes of radiation. These methods include process steps to form light sensitive active and/or passive circuit elements in a layer on a semiconductor (preferably silicon) wafer, as well as forming metal interconnections between the electrical elements of the sensor. These image sensors can include fine metal interconnects and vias (such as those conforming to about <NUM>, or finer, design rules), while having a backside surface coated with an amorphous boron layer and having a highly doped p-type silicon layer immediately adjacent to the boron layer. The metal interconnections may comprise tungsten, aluminum, copper or other metals used in fabricating interconnects in known CMOS processes.

An exemplary method of fabricating an image sensor is recited in claim <NUM>.

An image sensor as recited in claim <NUM> is also provided.

Although claimed subject matter will be described in terms of certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordingly, the scope of the disclosure is defined only by reference to the appended claims.

The following description is presented to enable one of ordinary skill in the art to make and use the disclosure as provided in the context of a particular application and its requirements. As used herein, directional terms such as "top," "bottom,", "front," "back," "over," "under," "upper," "upward," "lower," "down," and "downward" are intended to provide relative positions for purposes of description, and are not intended to designate an absolute frame of reference. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present disclosure is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

<FIG> is a cross-sectional side view depicting a portion of an image sensor <NUM> configured to sense deep ultraviolet (DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme ultraviolet (EUV) radiation or charged particles according to an exemplary embodiment of the present invention. Image sensor <NUM> includes a semiconductor membrane <NUM> including a circuit element <NUM> formed on an upper (first) surface 102U of a first epitaxial layer and metal interconnects <NUM> and <NUM> formed over circuit element <NUM>, a second epitaxial layer <NUM> disposed on a lower (second) surface <NUM> of first epitaxial layer <NUM>, a pure boron layer <NUM> disposed on a lower surface <NUM> of second epitaxial layer <NUM>, and an optional anti-reflection coating <NUM> disposed on a lower (outward-facing) surface <NUM> of pure boron layer <NUM>.

In one embodiment, first epitaxial layer <NUM> comprises a layer of lightly p-doped epitaxial silicon having a thickness T1 in a range of <NUM> to <NUM> and a p-type (e.g., boron) dopant concentration in a range of about <NUM><NUM> cm-<NUM> to <NUM><NUM> cm-<NUM>.

Circuit element <NUM> includes a sensor device (e.g., a light sensitive device such as a photodiode) and associated control transistors that are formed on (i.e., into and over) an upper (first) surface 102U of first epitaxial layer <NUM> using known techniques. In the depicted exemplary embodiment, circuit element <NUM> includes spaced-apart n+ doped diffusion regions <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> that extend from upper surface 102U into corresponding portions of epitaxial layer <NUM>, and polycrystalline silicon (polysilicon) gate structures <NUM>-<NUM> and <NUM>-<NUM> that are respectively separated from upper surface 102U by intervening gate oxide layers. First metal interconnects <NUM> and second metal interconnects <NUM>, along with corresponding first metal vias <NUM> and second metal vias <NUM>, are formed over circuit element <NUM> and are operably electrically connected to associated regions of circuit element <NUM> using known techniques. First metal interconnects <NUM> are formed in or on one or more dielectric layers <NUM> deposited over circuit element <NUM>, and first metal vias <NUM> extend through dielectric layers <NUM> using known via formation techniques. Second metal interconnects <NUM> are formed in a second dielectric layer <NUM> that is disposed over first metal interconnects <NUM>, and second metal vias <NUM> extend through one or both dielectric layers <NUM> and <NUM>. In one embodiment, a protection layer (not shown in <FIG>) is formed between first metal interconnects <NUM> and second metal interconnects <NUM>, and all second metal vias <NUM> comprise at least one of aluminum and copper and extend through this protection layer. The exemplary diffusion regions and gate structures forming circuit element <NUM> depicted in <FIG>, along with the exemplary metal interconnects <NUM> and <NUM> and metal vias <NUM> and <NUM>, are arbitrarily configured for illustrative purposes and provided solely to for purposes of describing exemplary circuit element structures and is not intended to represent a functional sensor device or to limit the appended claims.

Second epitaxial layer <NUM> is disposed on lower surface <NUM> of first epitaxial layer <NUM> and has a thickness T2 in the range of <NUM> to <NUM>, and more preferably in the range of about <NUM> and about <NUM>.

Referring to the bubble located at the bottom of <FIG>, according to an aspect of the present invention, second epitaxial layer <NUM> is formed using processing techniques described below such that second epitaxial layer <NUM> has a p-type dopant concentration gradient dnp that systematically increases from a minimum (lowest) p-type doping concentration np-min at lower surface <NUM> to a maximum (highest) p-type doping concentration np-max at upper surface 106U. A benefit gained by simultaneoulsy forming p-type dopant concentration gradient dnp and second epitaxial layer <NUM> in this manner is the ability to create p-type dopant concentration gradient dnp at substantially lower processing temperatures (i.e., about <NUM> or lower) than that required to form a similar p-type dopant concentration gradient within first epitaxial layer <NUM> (i.e., forming a similar gradient by diffusing a p-type dopant into first epitaxial layer <NUM> requires a processing temperature of at least <NUM>, preferably about <NUM> or higher), thereby preserving thermal budget and reducing total manufacturing costs by way of facilitating the use of low-cost metallization materials (e.g., aluminum and copper). In addition, forming p-type dopant concentration gradient dnp within second epitaxial layer <NUM> greatly enhances control over the rate at which the p-type dopant concentration changes within gradient dnp, which facilitates different gradient patterns (e.g., linear or parabolic) that may be used to further enhance the ability of image sensor (circuit element) <NUM> to efficiently detect high-energy photons. For example, the exemplary embodiment of <FIG> depicts the systematic increase of p-type dopant concentration gradient dnp as a continuous linear increase as a function of the negative-Y-axis direction. In other embodiments the gradual increase of p-type dopant concentration gradient dnp may be defined by any function of the thickness (negative-Y-axis) direction, such as a continuously curved increase (e.g., the change in doping concentration as a function of layer thickness follows a parabolic curve) or a discontinuous (step-wise) increase by way of varying the introduction of P-type dopant material during the second epitaxial layer formation process. In any case, first-to-be-formed layer portions (i.e., incremental layer portions generated during a given time period that occurs relatively early in the second epitaxial layer formation process) have a lower p-type doping concentration than at least one subsequently formed layer portion. For example, a p-type dopant concentration np1 of a (first) intermediate layer portion <NUM>-<NUM> of second epitaxial layer <NUM> is equal to or lower than a p-type dopant concentration np2 of a (second) intermediate layer portion <NUM>-<NUM> of second epitaxial layer <NUM>. When p-type dopant concentration gradient dnp varies in a continuously increasing manner relative to thickness (e.g., consistent with the linear function depicted in the example shown in <FIG>, or based on a parabolically increasing rate), p-type dopant concentration np1 of intermediate layer portion <NUM>-<NUM> is higher (greater) than minimum p-type doping concentration np-min and p-type dopant concentration np2 of intermediate layer portion <NUM>-<NUM> is lower (less) than maximum p-type doping concentration np-max. However, when p-type dopant concentration gradient dnp varies in a step-wise increasing manner, a particular p-type dopant concentration may remain the same for thickness-wise regions of second epitaxial layer <NUM> (e.g., p-type dopant concentration np1 of intermediate layer portion <NUM>-<NUM> may be equal to minimum p-type doping concentration np-min). In an exemplary embodiment, maximum p-type doping concentration np-max is approximately <NUM><NUM> cm-<NUM>, and minimum p-type doping concentration np-min is greater than or approximately equal to a dopant concentration of first epitaxial layer <NUM>.

In one embodiment, pure boron layer <NUM> is formed using techniques described below such that pure boron layer <NUM> has a thickness T3 in the range of <NUM> and <NUM>. In one embodiment, pure boron layer <NUM> comprises a boron concentration of <NUM>% or higher, with inter-diffused silicon atoms and oxygen atoms predominantly making up the remaining <NUM>% or less.

In one specific embodiment, thickness T3 of pure boron layer <NUM> is in the range of <NUM> to <NUM>, and optional anti-reflection coating <NUM> comprises a silicon dioxide layer deposited on a lower (outward-facing) surface <NUM> of pure boron layer <NUM>.

<FIG> illustrates an exemplary technique <NUM> for fabricating an image sensor. In this embodiment, the circuit elements can be created in step <NUM> using standard semiconductor processing steps including lithography, deposition, ion implantation, annealing, and etching. In one embodiment, CCD and/or CMOS sensor elements and devices may also be created in step <NUM>. These circuit elements are created in a first epitaxial (epi) layer on the front-side surface of the wafer. In preferred embodiments, the first epitaxial layer is about <NUM> to <NUM> thick. The first epitaxial layer is lightly p (p-) doped. In one embodiment, the first epitaxial layer resistivity is between about <NUM> and <NUM>Ω cm. Metal interconnects are created in step <NUM> using any suitable metal including aluminum, copper, tungsten, molybdenum or cobalt. The use of refractory metals, such as tungsten or molybdenum to form first metal interconnects and associated metal vias may allow high temperatures (such as temperatures greater than about <NUM>) in subsequent steps, in particular in steps <NUM> and/or <NUM>. However, when the temperatures in subsequent steps are limited to about <NUM> or lower, any convenient metal, including copper and aluminum may be used to form second metal interconnects and associated metal vias.

In step <NUM>, the front-side surface of the wafer can be protected. This protection may include depositing one or more protective layers on top of the circuit elements formed during step <NUM>. The one or more protective layers may comprise silicon dioxide, silicon nitride or other material. This protection may include attaching the wafer to a handling wafer, such as a silicon wafer, a quartz wafer, or a wafer made of other material. The handling wafer may include through-wafer vias for connecting to the circuit elements.

Step <NUM> involves thinning the wafer from the back-side so as to expose the first epitaxial layer in, at least, the active sensor areas. This step may involve polishing, etching, or both. In some embodiments, the entire wafer is back-thinned. In other embodiments, only the active sensor areas are thinned all the way to the first epitaxial layer.

Step <NUM> includes cleaning and preparing the back-side surface prior to deposition of a second epitaxial layer. During this cleaning, the native oxide and any contaminants, including organics and metals, should be removed from the back-side surface. In one embodiment, this cleaning can be performed using a dilute HF solution or using an RCA clean process. After cleaning, the wafer can be dried using the Marangoni drying technique or a similar technique to leave the surface dry and free of water marks.

In preferred embodiments, the wafer is protected in a controlled environment between steps <NUM> and <NUM> (e.g. in a vacuum environment or in an environment purged with a dry, inert gas such as nitrogen) to minimize native oxide regrowth after the cleaning.

In step <NUM>, a second epitaxial silicon layer is grown (deposited) on, at least, the exposed portion of the first epitaxial layer. In one embodiment the second epitaxial layer is grown by molecular-beam epitaxy (MBE) or other process at a temperature of about <NUM> or lower. In another embodiment, the second epitaxial layer is grown by a chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD) process at a temperature of about <NUM> or lower. As depicted in <FIG>, second epitaxial layer 105A may be grown in a reaction chamber using a gas G containing both silicon and a p-type dopant such as boron, so as to create a p-doped epitaxial silicon layer. Referring to <FIG>, early in the deposition process gas G includes a relatively low amount P0 of p-type dopant, whereby a first layer portion 105A0 is formed such that a minimum p-type dopant concentration np-min is generated adjacent to surface <NUM> of first epi layer <NUM>. As the deposition progresses, the amount (concentration) of the p-type dopant in gas G is increased according to a selected schedule while maintaining the same amount of silicon such that the p-type dopant concentration in the second epitaxial layer portions disposed further from the first epitaxial layer is increased. For example, as indicated in <FIG>, during an intermediate stage of the epitaxial deposition process the deposition process gas G includes an intermediate amount P1 of p-type dopant that is greater than amount P0 used at the point indicated in <FIG>, whereby an intermediate layer portion 105A1 is formed with an intermediate p-type dopant concentration np-int that is greater than minimum p-type dopant concentration np-min. Similarly, as indicated in <FIG>, during a final stage of the epitaxial deposition process the deposition process gas G includes a final amount P2 of p-type dopant that is greater than intermediate amount P1, whereby a final layer portion 105A2 is formed with maximum p-type dopant concentration np-max that is greater than intermediate p-type dopant concentration np-int. In alternative embodiments, gas G used to grow the second epitaxial layer may include silicon or boron in elemental form, or may include precursors such as silane for silicon or diborane for boron.

In step <NUM>, boron is deposited on the surface of the second epitaxial layer. In one preferred embodiment, this deposition can be done using diborane, or a diborane-hydrogen mixture, diluted in nitrogen at a temperature between about <NUM> and about <NUM>, thereby creating a high-purity amorphous boron layer. In an alternative embodiment, the deposition may be done at a temperature lower than about <NUM>, for example, by using a gas containing elemental boron. The thickness of the deposited boron layer depends on the intended application for the sensor. Typically, the boron layer thickness will be between about <NUM> and <NUM>, preferably between about <NUM> and <NUM>. The minimum thickness is set by the need for a pinhole-free uniform film, whereas the maximum thickness depends on the absorption of the photons or charged particles of interest by the boron, as well as the maximum length of time that the wafer can be kept at the deposition temperature.

More details on depositing boron from diborane gas can be found in "<NPL>.

After step <NUM>, other layers may be deposited on top of the boron layer. These other layers may include anti-reflection coatings comprised of one or more materials, such as silicon dioxide, silicon nitride, aluminum oxide, hafnium dioxide, magnesium fluoride, and lithium fluoride. These other layers may include a thin protective layer comprising a metal such as aluminum, ruthenium, tungsten or molybdenum. One or more of these other layers may be deposited using ALD. An advantage of using an ALD process for depositing these layers is that ALD processes typically allow very precise (single monolayer) control of the thickness of the deposited layer(s). In an alternative embodiment, other layers may be deposited on top of the boron layer after step <NUM>.

In one embodiment, the protective front-side layer may be removed in step <NUM>. In another embodiment, in step <NUM>, holes or vias can be opened or exposed in the handling wafer and/or protective front-side layer, or through-silicon vias around the edges of the device can be exposed, thereby allowing connection to the circuit elements.

In step <NUM>, the resulting structure may be packed in a suitable package. The packing step may comprise flip-chip bonding or wire bonding of the device to a substrate. The package may include a window that transmits wavelengths of interest, or may comprise a flange or seal for interface to a vacuum seal.

<FIG> illustrate exemplary cross-sections of a wafer subjected to method <NUM> (<FIG>). <FIG> illustrates a first epitaxial (epi) layer <NUM> formed on the front side of a substrate <NUM>. First epi layer <NUM> is preferably a p- epi layer. In one embodiment, the first epi layer resistivity is between about <NUM> and <NUM>Ω cm.

<FIG> illustrates various circuit elements <NUM> including interconnects that can be formed on the first epi layer <NUM> as described in step <NUM> above). Because the interconnects are formed on the wafer while the substrate is still hundreds of microns thick and hence not severely warped, these interconnects can be formed using normal sub-micron CMOS processing techniques and may include multiple layers of high-density metal interconnects. The metal interconnects comprise a metal such as copper, aluminum, tungsten, molybdenum or cobalt. In one embodiment, the metal interconnects consist entirely of refractory metals. In one embodiment, multiple through-silicon vias (TSV) 403A are created around one, or more, edges of the image sensor array in order to allow connection to the circuit elements <NUM>.

<FIG> illustrates a handling wafer <NUM> attached to the top surface of first epi layer <NUM> over circuit elements <NUM> (step <NUM>). Note that the through-silicon vias are shown but not labeled so as not to overly complicate the drawings. In an alternative embodiment, a protective layer can be used instead of, or in addition to, handling wafer <NUM>. In one embodiment (not shown), vias are formed in handling wafer <NUM> to allow connection to the circuit elements <NUM>.

<FIG> illustrates the wafer after the substrate (e.g., substrate <NUM> shown in <FIG>) is back-thinned to form the semiconductor membrane mentioned above or removed to expose a back-side (lower) surface <NUM> of first epi layer <NUM> (i.e., opposite to the surface on which circuit elements <NUM> are formed and to which handling wafer <NUM> is attached). As depicted in <FIG>, a native oxide may form on back-side surface <NUM>, which is exposed by the back-thinning process.

<FIG> illustrates the wafer after a cleaning and preparation of the back-side surface <NUM> is completed (step <NUM>) to prepare first epi layer <NUM> for the formation of a second epitaxial (epi) layer.

<FIG> illustrates the wafer after a second epi layer <NUM> is formed on back-side surface <NUM> of first epi layer <NUM>, and a pure boron layer <NUM> is formed on a lower surface <NUM> of second epi layer 405are respectively (steps <NUM> and <NUM>). In-situ p-type doping of the second epi layer <NUM> during growth (as described above for step <NUM>) creates a dopant concentration profile that increases from the bottom (back-side) surface <NUM> of first epi layer <NUM> to lower surface <NUM> of pure boron layer <NUM>.

<FIG> illustrates one or more optional anti-reflection or protection layers <NUM> deposited bottom/lower surface <NUM> of pure boron layer <NUM>. At least one of the layers may be deposited using an ALD process.

<FIG> illustrates the wafer after etching and deposition steps create metal pads <NUM> so as to allow electrical connection to the TSVs 403A (step <NUM>). Note that if vias are formed in handling wafer <NUM>, then metal pad <NUM> should be formed on the top surface of handling wafer <NUM>.

The above examples are not meant to limit the scope of the invention disclosed herein. They are meant merely as illustrations of how a p-type doped second epitaxial layer may be deposited on a back-side surface of a first epitaxial layer. The second epitaxial layer is subsequently coated with a boron layer on its photo-sensitive surface. Because the second epitaxial layer includes a concentration gradient of the p-type dopant which has its maximum value adjacent to the boron, the image sensor has high efficiency even for short-wavelength light, or low-energy charged particles, which may penetrate only a few nm, or a few tens of nm into the epitaxial layers.

<FIG> illustrates an exemplary detector assembly <NUM> incorporating an image sensor <NUM>, a silicon interposer <NUM> and other electronics in accordance with certain embodiments of the present invention.

In one aspect of the present invention, the detector assembly <NUM> may include one or more light sensitive sensors <NUM> disposed on the surface of an interposer <NUM>. In one embodiment, the one or more interposers <NUM> of the assembly <NUM> may include, but are not limited to, a silicon interposer. In a further aspect of the present invention, the one or more light sensitive sensors <NUM> of the assembly <NUM> are back-thinned and further configured for back-illumination including a boron layer and a p-type doped second epitaxial layer adjacent to the boron layer as described above.

In another aspect of the present invention, various circuit elements of the assembly <NUM> may be disposed on or built into the interposer <NUM>. In one embodiment, one or more amplification circuits (e.g., charge conversion amplifier) (not shown) may be disposed on or built into the interposer <NUM>. In another embodiment, one or more conversion circuits <NUM> (e.g., analog-to-digital conversion circuits, i.e. digitizers <NUM>) may be disposed on or built into the interposer <NUM>. In another embodiment, one or more driver circuits <NUM> may be disposed on or built into the interposer <NUM>. For example, the one or more driver circuits <NUM> may include a timing/serial drive circuit. For instance, the one or more driver circuits <NUM> may include, but are not limited to, clock driver circuitry or reset driver circuitry. In another embodiment, one or more decoupling capacitors (not shown) may be disposed on or built into the interposer <NUM>. In a further embodiment, one or more serial transmitters (not shown in <FIG>) maybe disposed on or built into the interposer <NUM>. In another embodiment, one or more of amplification circuits, analog-to-digital converter circuits and driver circuits may be included in light sensitive sensor <NUM>, reducing the number of (or eliminating the need for) circuits such as <NUM> and <NUM>.

In another aspect of the present invention, one or more support structures may be disposed between the bottom surface of the light sensitive array sensor <NUM> and the top surface of the interposer <NUM> in order to provide physical support to the sensor <NUM>. In one embodiment, a plurality of solder balls <NUM> may be disposed between the bottom surface of the light sensitive array sensor <NUM> and the top surface of the interposer <NUM> in order to provide physical support to the sensor <NUM>. It is recognized herein that while the imaging region of the sensor <NUM> might not include external electrical connections, the back-thinning of the sensor <NUM> causes the sensor <NUM> to become increasingly flexible. As such, solder balls <NUM> may be utilized to connect the sensor <NUM> to the interposer <NUM> in a manner that reinforces the imaging portion of the sensor <NUM>. In an alternative embodiment, an underfill material may be disposed between the bottom surface of the light sensitive array sensor <NUM> and the top surface of the interposer <NUM> in order to provide physical support to the sensor <NUM>. For example, an epoxy resin may be disposed between the bottom surface of the light sensitive array sensor <NUM> and the top surface of the interposer <NUM>.

In another aspect of the present invention, the interposer <NUM> and the various additional circuitry (e.g., amplification circuit, driver circuits <NUM>, digitizer circuits <NUM>, and the like) are disposed on a surface of a substrate <NUM>. In a further aspect, the substrate <NUM> includes a substrate having high thermal conductivity (e.g., ceramic substrate). In this regard, the substrate <NUM> is configured to provide physical support to the sensor <NUM>/interposer <NUM> assembly, while also providing a means for the assembly <NUM> to efficiently conduct heat away from the imaging sensor <NUM> and the various other circuitry (e.g., digitizer <NUM>, driver circuitry <NUM>, amplifier, and the like). It is recognized herein that the substrate may include any rigid highly heat conductive substrate material known in the art. For example, the substrate <NUM> may include, but is not limited to, a ceramic substrate. For instance, the substrate <NUM> may include, but is not limited to, aluminum nitride.

Claim 1:
A method of fabricating an image sensor, the method comprising:
forming a first epitaxial layer (<NUM>) on a substrate (<NUM>);
forming a circuit element (<NUM>) on the first epitaxial layer (<NUM>) ;
thinning the substrate (<NUM>) to generate a thinned substrate, the thinned substrate exposing at least a surface portion (<NUM>) of the first epitaxial layer (<NUM>, <NUM>);
forming a second epitaxial layer (<NUM>) on the exposed portion of the first epitaxial layer; and
forming a pure boron layer (<NUM>, <NUM>) on the second epitaxial layer (<NUM>),
wherein forming the second epitaxial layer (<NUM>, <NUM>) includes generating a p-type dopant concentration gradient in the second epitaxial layer (<NUM>, <NUM>) by gradually increasing a concentration of a p-type dopant used during formation of the second epitaxial layer (<NUM>, <NUM>) such that a first layer portion (<NUM>-<NUM>) of the second epitaxial layer (<NUM>) has a lower p-type dopant concentration than a subsequently formed second layer portion (<NUM>-<NUM>) of the second epitaxial layer (<NUM>), and a highest p-type dopant concentration of the second epitaxial layer (<NUM>) is adjacent to the pure boron layer (<NUM>).