Patent Description:
In recent years, advanced integrated circuit (IC) devices have been become increasingly multifunctional and have been scaled down in size. Although the scaling down process generally increases production efficiency and lowers associated costs, it has also increased the complexity of processing and manufacturing IC devices. For example, Fin Field-Effect Transistors (FinFETs) have been introduced to replace planar transistors. Among these FinFETs, the gate-all-around (GAA) structures such as nanosheet metal-oxide-semiconductor field-effect transistors (MOSFET) have been developed to possess excellent electrical characteristics, such as improved power performance and area scaling compared to the current FinFET technologies.

Although existing semiconductor structures including nanosheet transistors and methods for manufacturing the same have been adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, in a semiconductor structure including nanosheet transistors, each of the multilayered fins includes several channel layers stacked over the substrate and the channel layers in one of the multilayered fins are apart from each other in the direction vertical to the substrate. Those multilayered fins are relatively tall, and it is difficult to fill the empty space in the deeper position of the fins with the desired material(s), such as filling the empty space near the bottom of the multilayered fins with the material(s) of the gate electrode layer. The thicknesses of the gate electrode layers between the nanosheet transistors controlled by the same gate stack are not uniform. Thus, the threshold voltages between the nanosheet transistors controlled by the same gate stack would be different, which affects the electrical performance of the semiconductor structure during operation. Therefore, there are still some problems to be overcome in regards to semiconductor structures including nanosheet transistors in the semiconductor integrated circuits and technology.

<CIT> discloses a semiconductor structure according to the preamble of claim <NUM>.

<CIT> describes a FinFET device comprising a fin structure with a multilayered stack of silicon germanium nanowires, wherein the germanium content increases from bottom to top.

<CIT> discloses a semiconductor device comprising lower semiconductor wires made of an N-type semiconductor material and upper semiconductor wires made of a P-type semiconductor material, which can be SiGe. The lower semiconductor wires have the same material composition.

<CIT> describes the use of a work function adjustment film for adjusting a work function in a semiconductor device.

The present invention refers to a semiconductor structure according to claim <NUM>. Preferred embodiments of the invention are defined in the appendended dependent claims.

The following description is of the best-contemplated mode of carrying out the invention and of the examples not belonging to the invention but useful for understanding the invention. The scope of the invention is determined by reference to the appended claims.

The inventive concept is described fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The advantages and features of the inventive concept and methods of achieving them will be apparent from the following exemplary embodiments that will be described in more detail with reference to the accompanying drawings. The drawings as illustrated are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be understood that when an element is referred to as being "connected" or "contacting" to another element, it may be directly connected or contacting to the other element or intervening elements may be present.

Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" means that there are no intervening elements. It should be understood that the terms "comprises", "comprising", "includes" and/or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in figures. It should be understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present invention. Exemplary embodiments of aspects of the present inventive concept explained and illustrated herein include their complementary counterparts. The same or similar reference numerals or reference designators denote the same or similar elements throughout the specification.

<FIG> is a top view of a semiconductor structure over a substrate. In some examples, the semiconductor structure is a three-dimensional or non-planar transistor. In some examples, the semiconductor structure is a field-effect transistor (FET) structure including nanosheet transistors.

Referring to <FIG>, a semiconductor structure <NUM> includes several multilayered fins M1 and M2 over a substrate <NUM>, and a gate structure GE across the multilayered fins M1 and M2 to form semiconductor stacks M1G and M2G. To simplify the diagram, only two multilayered fins M1 and M2 are depicted herein. The multilayered fins M1 and M2 may extend in the first direction D1 (such as X-direction), and the gate structure GE may extend in the second direction D2. In some examples, the semiconductor stacks M1G and M2G are nanosheet stacks, and each of the semiconductor stacks includes nanosheet transistors. As shown in <FIG>, adjacent multilayered fins M1 and M2 (or adjacent semiconductor stacks M1G and M2G) are spaced apart from each other in the second direction D2 (such as Y-direction), wherein the second direction D2 is different from the first direction D1. For example, the second direction D2 is perpendicular to the first direction D1.

Each of the semiconductor stacks (such as M1G and M2G) in a semiconductor structure includes nanosheet transistors, and the channel layers of each of the semiconductor stacks are designed to improve the electrical performances. Examples of the designs include altering the spaces between adjacent channel layers in each of the semiconductor stacks, changing compositions of the channel layers in each of the semiconductor stacks, or a combination of the aforementioned changes. Therefore, improved electrical performances including uniform threshold voltages of the nanosheet transistors in each of the semiconductor stacks can be obtained.

A method for forming a semiconductor structure having semiconductor stacks is described below, wherein the spaces between adjacent channel layers in each of the semiconductor stacks are designed to improve the electrical performances of the nanosheet transistors. However, the present invention is not limited to the method provided herein. Those steps provided herein are merely described as one example of the fabrication.

<FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> are cross-sectional views of intermediate stages of a method for forming a semiconductor structure, in accordance with some examples not belonging to the invention as defined in the claims but useful for the understanding thereof. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG> are cross-sectional views taken along sectional line A-A of the semiconductor structure in <FIG>. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG> are cross-sectional views taken along sectional line B-B of the semiconductor structure in <FIG>.

Referring to <FIG>, a substrate <NUM> is provided, and several semiconductor strips S1 and S2 are formed over the substrate <NUM>, wherein the adjacent semiconductor strips S1 and S2 are spaced apart from each other in the second direction D2 (such as Y-direction). In some examples, each of the semiconductor strips S1 and S2 may include several sacrificial layers <NUM> and several channel layers <NUM> on the substrate <NUM>. According to some examples, the space in the third direction D3 (such as Z- direction) between the two lowermost channel layers is greater than the space between the two uppermost channel layers.

In some examples, the substrate <NUM> is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the substrate <NUM> includes silicon or other elementary semiconductor materials such as germanium. The substrate <NUM> may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some examples, the substrate <NUM> includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof. In some other examples, the substrate <NUM> includes a multi-layered structure. For example, the substrate <NUM> includes a silicon-germanium layer formed on a bulk silicon layer.

The semiconductor strips S1 and S2 may be formed/patterned by any suitable method. The steps below are provided for describing one applicable method for forming the semiconductor strips S1 and S2. In some examples, several sacrificial layers <NUM> and several channel layers <NUM> are alternately deposited over the substrate <NUM>, followed by depositing a patterned hardmask layer <NUM> on the uppermost sacrificial layer. Then, the sacrificial layers <NUM> and the channel layers <NUM> are patterned using the patterned hardmask layer <NUM>, thereby forming the semiconductor strips S1 and S2 on the substrate <NUM>. The patterned hardmask layer <NUM> may be a silicon nitride layer or a patterned layer formed by one or more other suitable materials. The semiconductor strips S1 and S2 are separated by the first trench <NUM>. In some examples, the semiconductor strips S1 and S2 extend in the first direction D1 (such as X-direction), as shown in <FIG>. Also, the semiconductor strips S1 and S2 are arranged along the second direction D2 (such as Y-direction), as shown in <FIG>. That is, the semiconductor strips S1 and S2 are spaced apart from each other in the second direction D2.

To simplify the diagram, three channel layers <NUM> (such as the first channel layer <NUM>-<NUM>, the second channel layer <NUM>-<NUM> and the third channel layer <NUM>-<NUM>) and four sacrificial layers <NUM> (such as the first sacrificial layer <NUM>-<NUM>, the second sacrificial layer <NUM>-<NUM>, the third sacrificial layer <NUM>-<NUM> and the fourth sacrificial layer <NUM>-<NUM>) are depicted herein for illustrating the material layers of each of the semiconductor strips S1 and S2. Also, although two semiconductor strips S1 and S2 are depicted herein to simplify the diagram of the example, more semiconductor strips may be formed on the substrate <NUM>, and adjacent two semiconductor strips are separated by the first trench <NUM>.

Also, as shown in <FIG>, in each of the semiconductor strips S1 and S2, the channel layers <NUM> (such as the first channel layer <NUM>-<NUM>, the second channel layer <NUM>-<NUM> and the third channel layer <NUM>-<NUM>) above the substrate <NUM> are spaced apart from each other in the third direction D3 (such as Z- direction). The third direction D3 is vertical to the first direction D1 and the second direction D2. According to the present invention, the space between the first channel layer <NUM>-<NUM> and the second channel layer <NUM>-<NUM> is greater than the space between the second channel layer <NUM>-<NUM> and the third channel layer <NUM>-<NUM>.

Specifically, as shown in <FIG>, the first sacrificial layer <NUM>-<NUM>, the second sacrificial layer <NUM>-<NUM>, the third sacrificial layer <NUM>-<NUM> and the fourth sacrificial layer <NUM>-<NUM> have the thicknesses t1, t2, t3 and t4, respectively. A distance in the third direction D3 between the first channel layer <NUM>-<NUM> and the second channel layer <NUM>-<NUM> (e.g. the two lowermost channel layers in this example) is defined as the first space, and the first space is identical to the thickness t2 of the second sacrificial layer <NUM>-<NUM>. A distance in the third direction D3 between the second channel layer <NUM>-<NUM> and the third channel layer <NUM>-<NUM> (e.g. the two uppermost channel layers in this example) is defined as the second space, and the second space is identical to the thickness t3 of the third sacrificial layer <NUM>-<NUM>. According to some examples, the first space (e.g. equal to the thickness t2) is greater than the second space (e.g. equal to the thickness t3) (t2 > t3). In addition, the thickness t1 of the first sacrificial layer <NUM>-<NUM> may be equal to or greater than the thickness t2 of the second sacrificial layer <NUM>-<NUM>, and the thickness t4 of the fourth sacrificial layer <NUM>-<NUM> may be equal to or greater than the thickness t3 of the third sacrificial layer <NUM>-<NUM>.

The channel layers <NUM> include SiGe. In some examples, the channel layers <NUM> include one or more elements selected from group IV semiconductor materials, such as Si (intrinsic Si or lightly doped Si), Ge (intrinsic Ge or lightly doped Ge), or a compound including Sn or Pb. In some embodiments, the channel layers <NUM> include a compound formed by elements selected from group III-V semiconductor materials, such as GaAs, InAs or InSb. It should be noted that the channel layer <NUM> of the present invention is not limited to include the aforementioned materials.

In addition, the channel layers <NUM> in one of the semiconductor strips may be made of the same material or the same compound with the same molar ratio of two or more elements. In some examples, the channel layers <NUM> in one semiconductor strip are made of silicon (Si). According to an exemplary non-claimed configuration, the channel layers <NUM> in one semiconductor strip are made of silicon germanium, wherein the molar ratios of silicon and germanium in each of the channel layers <NUM> are identical. For example, the channel layers <NUM> in one semiconductor strip are respectively formed by Si(<NUM>-x)Gex, Si(<NUM>-y)Gey, Si(<NUM>-z)Gez, wherein x = y = z. Also, the sacrificial layers <NUM> can be formed by a material different from the material of the channel layers <NUM>, and will be removed in the later process. In this example, the channel layers <NUM> are made of silicon (Si), and the sacrificial layers <NUM> are made of silicon germanium (SiGe).

Next, referring to <FIG>, in some examples, an insulating layer <NUM> is deposited over the semiconductor strips S1 and S2 and fills the first trench <NUM> between the semiconductor strips S1 and S2. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove the excess portion of the insulating layer <NUM> above the patterned hardmask layer <NUM>. Then, a patterned mask <NUM> can be formed on the patterned hardmask layer <NUM> and the insulating layer <NUM>. The semiconductor strips S1 and S2 can be (optionally) patterned to form the second trenches <NUM>, thereby defining several multilayered fins covered by the patterned mask <NUM>. Numbers of the multilayered fins depend on the design requirements in applications. As shown in <FIG>, two second trenches <NUM> extending in the second direction D2 define three multilayered fins, and one multilayered fin M1 with a full width in the first direction D1 is illustrated to simplify the diagram of the example. As shown in <FIG>, the patterned mask <NUM> is formed on the multilayered fins M1 and M2, wherein the multilayered fins M1 and M2 are spaced apart from each other in the second direction D2 (such as Y-direction).

In some examples, the patterned mask <NUM> may include an organic planarizing layer, an anti-reflective coating (ARC) film, a photoresist layer, or other suitable materials. The patterned mask <NUM> can be applied in different layout configurations to define the number and the lengths of multilayered fins M1 and M2. The length L1 of the multilayered fin M1 in the first direction D1 is shown in <FIG>.

To form nanosheet transistors of the semiconductor structure in accordance with some examples, the sacrificial layers <NUM> in the multilayered fins have to be removed, followed by forming a gate structure across selected multilayered fins and wrapping around the channel layers of the selected multilayered fins.

One of the applicable processes (i.e. <FIG>, <FIG>, <FIG>) is provided below for exemplifying the removal of the sacrificial layers <NUM> in the multilayered fins.

Referring to <FIG>, in some examples, the patterned mask <NUM> is removed, and the material of the patterned hardmask layer <NUM> is deposited on the multilayered fins M1 and M2 and fills the second trenches <NUM>. A planarization process, such as a chemical mechanical polishing (CMP) process, can be performed to remove the excess portion of the insulating layer <NUM> above the insulating layer <NUM>, thereby exposing the insulating layer <NUM>. As shown in <FIG>, the material of the patterned hardmask layer <NUM> fills the second trenches <NUM> between the multilayered fins arranged separately in the first direction D1. Also, as shown in <FIG>, the insulating layer <NUM> filling the first trenches <NUM> is exposed between the multilayered fins M1 and M2 arranged separately in the second direction D2.

Next, referring to <FIG>, in some examples, the insulating layer <NUM> is removed from the first trenches <NUM>. After removing the insulating layer <NUM>, two opposite sidewalls of the sacrificial layers <NUM> and the channel layers <NUM> of the multilayered fins M1 and M2 are exposed in the first trenches <NUM> (<FIG>), and the other two opposite sidewalls of the sacrificial layers <NUM> and the channel layers <NUM> of the multilayered fins M1 and M2 are covered by the material of the patterned hardmask layer <NUM> filling in the second trenches <NUM>.

Specifically, in the multilayered fins M1 and M2 as shown in <FIG>, the sidewalls <NUM>-<NUM> of the first sacrificial layer <NUM>-<NUM>, the sidewalls <NUM>-<NUM> of the first channel layer <NUM>-<NUM>, the sidewalls <NUM>-<NUM> of the second sacrificial layer <NUM>-<NUM>, the sidewalls <NUM>-<NUM> of the second channel layer <NUM>-<NUM>, the sidewalls <NUM>-<NUM> of the third sacrificial layer <NUM>-<NUM>, the sidewalls <NUM>-<NUM> of the third channel layer <NUM>-<NUM>, the sidewalls <NUM>-<NUM> of the fourth sacrificial layer <NUM>-<NUM> and the sidewalls <NUM>-S of the patterned hardmask layer <NUM> are revealed by the first trenches <NUM>. Also, take the multilayered fin M1 as an example, the sidewalls <NUM>-1E of the first sacrificial layer <NUM>-<NUM>, the sidewalls <NUM>-1E of the first channel layer <NUM>-<NUM>, the sidewalls <NUM>-2E of the second sacrificial layer <NUM>-<NUM>, the sidewalls <NUM>-2E of the second channel layer <NUM>-<NUM>, the sidewalls <NUM>-3E of the third sacrificial layer <NUM>-<NUM>, the sidewalls <NUM>-3E of the third channel layer <NUM>-<NUM> and the sidewalls <NUM>-4E of the fourth sacrificial layer <NUM>-<NUM> are covered by the material of the patterned hardmask layer <NUM> filling in the second trenches <NUM>, as shown in <FIG>. That is, two opposite sidewalls (e.g. the sidewalls <NUM>-1E, <NUM>-2E and <NUM>-3E) of the channel layers <NUM> of the multilayered fins M1 and M2 are secured (or anchored) by the material of the patterned hardmask layer <NUM> in the second trenches <NUM>.

Next, referring to <FIG>, in some examples, the sacrificial layers <NUM> (including the first sacrificial layer <NUM>-<NUM>, the second sacrificial layer <NUM>-<NUM>, the third sacrificial layer <NUM>-<NUM> and the fourth sacrificial layer <NUM>-<NUM>) are removed from the multilayered fins M1 and M2, thereby forming the empty spaces <NUM>, <NUM>, <NUM> and <NUM> (as shown in <FIG>). The sacrificial layers <NUM> can be removed using an isotropic dry or wet etching process that is selective to the channel layers <NUM>. In <FIG>, the channel layers <NUM> in the multilayered fins M1 and M2 appear to be floating. However, the material of the patterned hardmask layer <NUM> in the second trenches <NUM> secure two ends of the channel layers <NUM>. As clearly shown in <FIG>, two opposite sidewalls (e.g. the sidewalls <NUM>-1E, <NUM>-2E and <NUM>-3E) of the channel layers <NUM> of the multilayered fins M1 and M2 are fixed to the material of the patterned hardmask layer <NUM> in the second trenches <NUM>.

After the sacrificial layers <NUM> (such as the SiGe layers) have been removed, formation of a gate structure that is across selected multilayered fins and surrounds the channel layers of the selected multilayered fins is performed. One of the applicable processes (such as steps in <FIG>, <FIG>, <FIG>) is provided below for exemplifying the formation of a gate structure in the multilayered fins.

Referring to <FIG>, according to some examples, the portions of the patterned hardmask layer <NUM> above the third channel layer <NUM>-<NUM> (including the patterned hardmask layer <NUM> and a portion of the material of the patterned hardmask layer <NUM> in the second trenches <NUM>) are removed. Then, a dummy gate stack <NUM> is formed across selected multilayered fins, and then spacers <NUM> are formed on the sidewalls of the dummy gate stack <NUM>, thereby defining a region for forming nanosheet stacks. In some examples, the dummy gate stack <NUM> may include silicon (such as polysilicon) or other suitable materials. The dummy gate stack <NUM> can be a single layer or a multi-layered structure. The spacers <NUM> may include a low-k dielectric material, such as silicon boron carbon nitride (SiBCN), silicon oxycarbonitride (SiOCN), or silicon oxynitride (SiON). The spacers <NUM> can be a single layer or a multi-layered structure.

Also, in this example, three regions for forming nanosheet stacks arranged in the first direction D1 are shown for exemplification, as shown in <FIG>. Also, each dummy gate stack <NUM> extending in the second direction D2 and across two multilayered fins M1 and M2 are shown for exemplification, as shown in <FIG>. However, those regions for forming nanosheet stacks and the two multilayered fins crossed by the dummy gate stack <NUM> in <FIG> are merely illustrated for exemplification. It should be noted that the present invention is not limited to the intermediate structure in <FIG>.

Next, referring to <FIG>, the dummy gate stacks <NUM> are removed. The remained spacers <NUM> define the regions for forming gate structure surrounding the channel layers <NUM>. According to the invention, each of the gate structures includes a gate dielectric layer <NUM> and a gate electrode GE. After the dummy gate stacks <NUM> are removed, the gate dielectric layers <NUM> are formed for surrounding the respective channel layers <NUM>. Specifically, as shown in <FIG>, the gate dielectric layers <NUM>, <NUM> and <NUM> are formed on two opposite sidewalls, the top surfaces and the bottom surfaces of the channel layers <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM>, respectively. Also, in some examples, the gate dielectric layer <NUM> includes one or more high-k dielectric materials, such as the dielectric materials with a dielectric constant (k) greater than that of silicon dioxide, wherein the dielectric constant of silicon dioxide is about <NUM> to <NUM>.

Next, referring to <FIG>, the gate electrodes GE fill the regions defined by the spacers <NUM>. Each of the gate electrodes GE is formed at least on the sidewalls of the gate dielectric layers <NUM> and the top surfaces of the uppermost gate dielectric layers <NUM> of the gate dielectric layers <NUM>. After the gate electrodes GE are formed, the multilayered fins M1 and M2 and the portions of the gate electrodes GE over the multilayered fins M1 and M2 can be referred as semiconductor stacks M1G and M2G in the description below. Also, after the gate electrodes GE are formed, the spacers <NUM> can be removed.

In some examples, as shown in <FIG>, the gate electrode GE fully fills the empty spaces between the gate dielectric layers <NUM> and the empty space between the lowermost channel layer <NUM>-<NUM> and the substrate <NUM> within the defined region. However, it is not limited to the intermediate structure herein. In some other examples, the gate electrode GE may not fully fill the empty space around the lowermost channel layer <NUM>-<NUM>.

Each of the gate structures may include a gate dielectric layer <NUM> and a gate electrode GE. In some examples as described above, the gate electrode GE of the gate structures may not include a work function tuning layer. However, in some other examples, the gate electrode GE may include work function tuning layers <NUM> and a metal filling layer <NUM>.

<FIG> is a cross-sectional view of a semiconductor structure in accordance with some examples, which depicts the work function tuning layers <NUM> surrounding the gate dielectric layers <NUM>, and a metal filling layer <NUM> around the work function tuning layers <NUM>. In some embodiments, the gate dielectric layers <NUM> may electrically insulate the channel layers <NUM> from the gate electrode GE, wherein the gate electrode GE may include the metal filling layer <NUM>, or a combination of the work function tuning metal layer <NUM> and the metal filling layer <NUM>.

The work function tuning layer <NUM> of the gate electrode GE may be used to provide the desired work function for nanosheet transistors to enhance electrical performance including improved threshold voltage. In some examples, the work function tuning layer <NUM> includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. Also, in some other examples, the work function tuning layer <NUM> is an aluminum-containing layer. For example, the aluminum-containing layer includes TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof. In addition, in some examples, the work function tuning layer <NUM> may include metal, metal carbide, metal nitride, other suitable materials, or a combination thereof. For example, the work function tuning layer <NUM> includes tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials, or a combination thereof. The work function tuning layer <NUM> may be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

In some examples, the metal filling layer <NUM> may fill the spaces between adjacent work function tuning layers <NUM>, <NUM> and <NUM>, as shown in <FIG> and <FIG>. However, the present invention is not limited to those configurations of the metal filling layer <NUM>. In some other examples, the spaces between the work function tuning layers around the upper channel layers (e.g. the two uppermost channel layers) in one of the semiconductor stacks (such as M1G and M2G) are fully filled with the metal filling layer <NUM>, but the spaces between the work function tuning layers around the lower channel layers in the semiconductor stacks (such as M1G and M2G) may not be fully filled with the metal filling layer <NUM> (not shown in the drawings). The electrical performances of the nanosheet transistors in a semiconductor stack (such as M1G or M2G) can be improved (e.g. uniform threshold voltages of the nanosheet transistors) as long as the thicknesses of the work function tuning layers and the metal filling layer surrounding the lower channel layers (such as the lowermost channel layer) approximate to that surrounding the other channel layers.

In addition, in some examples, the metal filling layer <NUM> may be made of or includes tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. The metal filling layer <NUM> may be deposited using an ALD process, a PVD process, a CVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

After the structures as shown in <FIG> and <FIG> are formed, the subsequent processes are performed to complete a FET structure including nanosheet transistors. For example, the source/drain features (not shown) are formed to contact the channel layers <NUM> of the semiconductor stacks M1G and M2G, followed by forming source/drain contacts and gate contacts, in accordance with some examples. Details of the subsequent processes for forming the FET structure including nanosheet transistors are not described herein.

In the current fabrication process for forming FET nanosheet stacks, high multilayered fins (such as M1 and M2) are formed, and it is difficult to fill the empty space in the deeper position with the desired material(s), such as filling the empty space near the bottom of the multilayered fins with the material(s) of the gate electrode. This would cause significant difference of the electrical performances between the nanosheet transistors in each of the semiconductor stacks after formation of the gate electrode GE. Specifically, during deposition of the gate electrode GE, the GE material layer (such as a metal filling layer, or a combination of work function tuning layers and the metal layer) surrounding the lowermost channel layer would be much thinner than that surrounding the other channel layers, even incompletely surrounding the lowermost channel layer. The thinner the GE material layer, the larger the threshold voltages of the nanosheet transistor. Therefore, the thinner GE material layer surrounding the lowermost channel layer causes a higher threshold voltage of the lowermost nanosheet transistor, thereby inducing significant difference of the threshold voltages between the nanosheet transistors in each of the semiconductor stacks. According to the present invention, at least the space around the lowermost channel layer is enlarged to solve the difficulty of depositing the GE material layer (such as the metal layer, or a combination of the work function tuning layer and the metal layer) surrounding the lowermost channel layer. Accordingly, the difference of the electrical performances between the nanosheet transistors in each of the semiconductor stacks can be significantly reduced. For example, more uniform threshold voltages of the nanosheet transistors including the channel layers <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> in each semiconductor stack can be obtained, in accordance with the invention.

<FIG> schematically illustrates I-V (drain current vs. gate voltage) characteristics of a semiconductor stack including nanosheet transistors having non-uniform threshold voltages. The circled region on the I-V curve <NUM>-I in <FIG> may be caused by the higher threshold voltage of the lowermost nanosheet transistor in the semiconductor stack. For example, the first nanosheet transistor (including the lowermost channel layer in a semiconductor stack) has a threshold voltage of about 25V and the other nanosheet transistors (including the other channel layers) have threshold voltages of about <NUM>. When the voltage applied to the gate electrode is increased, a flat section is shown in the middle of the I-V curve <NUM>-I, such as the circled flat section in <FIG> schematically illustrates I-V (drain current vs. gate voltage) characteristics of a semiconductor stack including nanosheet transistors having uniform threshold voltages. Compared with the I-V curve <NUM>-I as shown in <FIG>, the drain current of the I-V curve <NUM>-II shown in <FIG> increases gradually and smoothly with the increase of the voltage applied to the gate electrode, and no flat section shown in the middle of the I-V curve <NUM>-II.

In addition, as shown in <FIG> and <FIG>, the first space SP1 (in the third direction D3) between the two lowermost channel layers (such as the channel layers <NUM>-<NUM> and <NUM>-<NUM>) is greater than the second space SP2 (SP1 > SP2) between the two uppermost channel layers (such as the channel layers <NUM>-<NUM> and <NUM>-<NUM>), thereby reducing the threshold voltage difference between the nanosheet transistors including the channel layers in each semiconductor stack (M1G or M2G). Thus, more uniform threshold voltages of the nanosheet transistors including the channel layers <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> in each semiconductor stack (M1G or M2G) can be obtained. The difference between the first space SP1 and the second space SP2 is greater than <NUM>. The difference between the first space SP1 and the second space SP2 is within a range of about <NUM> to about <NUM>.

Besides altering the spaces between adjacent channel layers in each semiconductor stack as described above, the compositions of the channel layers in each of the semiconductor stacks (M1G or M2G) can be changed to improve the electrical performances of the nanosheet transistors in the semiconductor stack.

<FIG> is a cross-sectional view of a semiconductor structure in accordance with some examples not belonging to the invention as defined in the claims but useful for the understanding thereof. Each of the multilayered fins M1 and M2 (extending in the first direction D1) includes several channel layers alternating over the substrate <NUM>. Also, the gate dielectric layers <NUM> surround the respective channel layers <NUM>, and a gate electrodes GE extends in the second direction D2 and across the multilayered fins M1 and M2 to form the semiconductor stacks M1G and M2G. In one example, as shown in <FIG>, the first channel layer <NUM>-<NUM>, the second channel layer <NUM>-<NUM> and the third channel layer <NUM>-<NUM> are alternately arranged over the substrate <NUM>, and the gate dielectric layers <NUM>, <NUM> and <NUM> surround the first channel layer <NUM>-<NUM>, the second channel layer <NUM>-<NUM> and the third channel layer <NUM>-<NUM>, respectively. Also, the work function tuning layers <NUM>, <NUM> and <NUM> of the gate electrodes GE surround the respective gate dielectric layers <NUM>, <NUM> and <NUM>, and the metal filling layer <NUM> fills between the work function tuning layers <NUM>, <NUM> and <NUM>.

The same or similar reference numerals or reference designators denote the same or similar elements in <FIG> and <FIG>. It is noted that structures and material(s) of the elements in <FIG> are similar to those in <FIG> for the previously described example, so that the details of the elements will not be redundantly repeated herein. In addition, a method for forming the semiconductor structure in <FIG> is similar to those for the previously described example, and the details will not be repeated herein.

In some examples, the channel layers <NUM> in one of the semiconductor stacks M1G and M2G as shown in <FIG> and <FIG> are made of the same material or compound including elements with identical molar ratios, wherein the spaces between adjacent channel layers in each semiconductor stack are changed (e.g. SP1>SP2) to improve the electrical performances of the nanosheet transistors in the semiconductor stack. However, the invention is not limited thereto. The electrical performances of the nanosheet transistors can be improved by modifying the compositions of the channel layers in each semiconductor stack without changing the spaces between adjacent channel layers, although the present invention refers to semiconductor structures having SP1>SP2.

In some examples not belonging to the invention as defined in the claims but useful for the understanding thereof, as shown in <FIG>, the spaces between adjacent channel layers <NUM> in each semiconductor stack are the same (e.g. SP1 = SP2). The channel layers <NUM> in one of the semiconductor stacks M1G and M2G may include a compound formed by at least two elements with different molar ratio. In some examples, the channel layers <NUM> include a compound formed by at least two elements selected from group IV semiconductor materials, such as Si, Ge, SiGe, or a compound including Sn or Pb. In some embodiments, the channel layers <NUM> includes compound formed by elements selected from group III-V semiconductor materials, such as GaAs, InAs or InSb. It should be noted that the channel layer <NUM> of the present example is not limited the aforementioned materials.

According to the invention, the lowermost channel layer (such as channel layer <NUM>-<NUM>) in one of the semiconductor stacks M1G and M2G has a higher germanium content than any of the other channel layers (such as channel layers <NUM>-<NUM> and <NUM>-<NUM>) in the semiconductor stack. In some embodiments, the lowermost channel layer (such as channel layer <NUM>-<NUM>) comprises no more than <NUM> molar ratio of germanium. In some other embodiments, the germanium content of the channel layers <NUM> decreases as the distance (also referred as the vertical distance) in the third direction D<NUM> (e.g. the Z-direction) between the channel layers <NUM> and the substrate <NUM> increases.

According to the invention, the channel layers <NUM> are made of silicon germanium, and the molar ratios of silicon and germanium in each of the channel layers <NUM> are different. For example, the channel layers <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> in one of the semiconductor stacks M1G and M2G are respectively made of Si(<NUM>-z)Gez, Si(<NUM>-y)Gey, Si(<NUM>-x)Gex, wherein Z > Y > X. In some embodiments, Z is greater than Y and less than <NUM> (<NUM> > Z > Y), Y is greater than o and less than Z (Z > Y > o), and X is greater than o (Y >X > o). In some embodiments, the difference between Z and Y is within a range of about <NUM> to about <NUM>, and the difference between Y and X is within a range of about <NUM> to about <NUM>. According to some embodiments of the present invention, the higher the germanium content of the channel layer, the lower the threshold voltage of the nanosheet transistor.

Thus, according to the invention, the lowermost channel layer (such as the channel layer <NUM>-<NUM>) in one of the semiconductor stacks has a higher germanium content than any of the other channel layers (such as channel layer <NUM>-<NUM> and <NUM>-<NUM>). Since it is difficult to fill the empty space near the bottom of the multilayered fins and the lowermost channel layer would be surrounded by a thinner GE material layer (which induces a higher threshold voltage) as discussed above, the defects of threshold voltage difference between the nanosheet transistors in the semiconductor stack (such as M1G or M2G) can be compensated for by increasing the germanium content of the lowermost channel layer (such as the molar ratios of germanium to silicon in a SiGe channel layer) to decrease the threshold voltage. Thus, more uniform threshold voltages of the nanosheet transistors including the channel layers <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> in one of the semiconductor stacks (such as M1G and M2G) can be obtained.

In addition, the electrical performances of the nanosheet transistors in a semiconductor stack can be improved (e.g. uniform threshold voltages of the nanosheet transistors) by altering the spaces between adjacent channel layers in the semiconductor stack and changing the compositions of the channel layers in the semiconductor stack, in accordance with the present invention.

<FIG> is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention. According to the invention, the lowermost channel layer in one of the semiconductor stacks (such as M1G and M2G) includes a higher germanium content than the other channel layers in the semiconductor stack, and the spaces between adjacent channel layers in one of the semiconductor stacks (such as M1G and M2G) are also changed to enlarge the space around the lowermost channel layer. For example, the space (in the third direction D3) between the two lowermost channel layers is greater than the space between the two uppermost channel layers.

As shown in <FIG>, the channel layers <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> in one of the semiconductor stacks M1G and M2G are respectively formed by Si(<NUM>-z)Gez, Si(<NUM>-y)Gey, Si(<NUM>-x)Gex, wherein Z > Y > X. Also, the first space SP1 in the third direction D3 between the first channel layers <NUM>-<NUM> and the second channel layer <NUM>-<NUM> (i.e. the two lowermost channel layers) is greater than the second space SP2 (SP1 > SP2) in the third direction D3 between the second channel layer <NUM>-<NUM> and the third channel layer <NUM>-<NUM> (i.e. the two uppermost channel layers). Thus, uniform threshold voltages of the nanosheet transistors including the channel layers <NUM>-<NUM>, <NUM>-<NUM> and <NUM>-<NUM> in each semiconductor stack can be obtained, in accordance with some embodiments of the present invention.

After the structures as shown in <FIG> are formed, the subsequent processes are performed to complete a FET structure including nanosheet transistors. For example, the source/drain features (not shown) are formed to contact the channel layers <NUM> of the semiconductor stacks M1G and M2G, followed by forming source/drain contacts and gate contacts. Details of the subsequent processes for forming the FET structure including nanosheet transistors are not described herein.

Claim 1:
A semiconductor structure, comprising:
semiconductor stacks (M1G, M2G) over a substrate (<NUM>), wherein each of the semiconductor stacks (M1G, M2G) extends in a first direction (D1), and adjacent semiconductor stacks (M1G, M2G) are spaced apart from each other in a second direction (D2), which is different from the first direction (D1), wherein each of the semiconductor stacks (M1G, M2G) comprises:
channel layers (<NUM>) above the substrate (<NUM>) and spaced apart from each other in a third direction (D3), wherein the third direction (D3) is vertical to the first direction (D1) and the second direction (D2); and
a gate structure, comprising:
gate dielectric layers (<NUM>) around the respective channel layers (<NUM>); and
a gate electrode (GE) along sidewalls of the gate dielectric layers (<NUM>) and a top surface of an uppermost gate dielectric layer (<NUM>) of the gate dielectric layers (<NUM>),
wherein a space (SP1) in the third direction (D3) between the two lowermost channel layers (<NUM>-<NUM>, <NUM>-<NUM>) of the channel layers (<NUM>) is greater than a space (SP2) in the third direction (D3) between the two uppermost channel layers (<NUM>-<NUM>, <NUM>-<NUM>) of the channel layers (<NUM>);
characterised in that a lowermost channel layer (<NUM>-<NUM>) of the channel layers (<NUM>) in one of the semiconductor stacks (M1G, M2G) includes a higher germanium content than a germanium content of the other respective channel layers (<NUM>-<NUM>, <NUM>-<NUM>) in said semiconductor stack, wherein the channel layers (<NUM>) in said one of the semiconductor stacks (M1G, M2G) comprise silicon germanium, and wherein molar ratios of silicon and germanium in each of the channel layers (<NUM>) in said one of the semiconductor stacks (M1G, M2G) are different.