Patent Description:
The disclosure relates to a printed circuit board, and more particularly to a printed circuit board, which includes a circuit pattern having a curved surface in a portion of a lateral side thereof and a surface treatment layer formed through electrolytic plating, and a method of fabricating the same.

A printed circuit board (PCB), which is formed by printing a circuit line pattern on an electrically insulating substrate using a conductive material, such as copper (Cu), signifies a board immediately before electronic components are mounted thereon. That is to say, the PCB signifies a circuit board in which the mounting positions of the electronic components are determined, and circuit patterns are printed on and fixed to the surface of a flat plate to connect the electronic components with each other, in order to densely mount various types of electronic devices on the flat plate.

In general, for the surface treatment of the circuit patterns formed on the PCB, Organic Solderability Preservative (OSP) has been used, and electrolytic nickel/gold, electrolytic nickel/gold-cobalt alloy, or electroless nickel/palladium/gold has been used.

In this case, various surface treatment schemes may be employed according to the use purposes thereof. For example, the surface treatment schemes for soldering, wirebonding, and a connector may be used.

<FIG> is a sectional view showing a PCB according to the related art.

Referring to <FIG>, the PCB includes an insulating layer <NUM>, a plating seed layer <NUM>, a circuit pattern <NUM>, a protective layer <NUM>, a first surface treatment layer <NUM>, and a second surface treatment layer <NUM>.

<FIG> show the insulating layer <NUM>, the plating seed layer <NUM>, the circuit pattern <NUM>, the first surface treatment layer <NUM>, and the second surface treatment layer <NUM> having the same structures except for protective layers <NUM> having different structures according to the used shape thereof.

In other words, the protective layer <NUM> shown in <FIG> covers the entire exposed surface of the insulating layer <NUM> while covering at least a portion of a top surface of the circuit pattern <NUM>, and has a shape of protruding upward from the surface of the second surface treatment layer <NUM>.

The protective layer <NUM> shown in <FIG> serves only as an embankment. Accordingly, the protective layer <NUM> exposes at least a portion of the surface of the insulating layer <NUM> in the state that the protective layer <NUM> does not make contact with the circuit pattern <NUM>.

Meanwhile, the above PCB according to the related art includes the first surface treatment layer <NUM> including nickel (Ni) and the second surface treatment layer <NUM> including gold (Au) for the surface treatment of the circuit pattern <NUM>.

In this case, the first surface treatment layer <NUM> and the second surface treatment layer <NUM> are generally formed through electroless plating since a seed layer for electroplating does not separately exist.

In addition, to form the first and second surface treatment layers <NUM> and <NUM> through the electrolytic plating, a plating seed layer must be additionally formed.

However, design limitations may exist as the additional seed layer is formed in order to perform the electroplating even though the surface treatment of the PCB is generally performed through the electroless plating.

In addition, the surface treatment of the PCB essentially requires the formation of the first surface treatment layer <NUM> including metal, such as Ni, for the diffusion of the circuit pattern <NUM> including Cu. <CIT> discloses a manufacturing method of a printed wiring board comprising: a step of separating a carrier base material from a laminate sheet where a copper foil with a carrier base material is laminated on at least one surface of an insulation layer; a step of forming a metal layer thicker than a copper foil layer entirely or selectively on the copper foil layer; and a step of obtaining a pattern of a conductive circuit composed of the copper foil layer and the metal layer by etching at least the copper foil layer. <CIT>l discloses a printed circuit board where a wiring cover layer is formed on a base insulating layer with a conductor trace sandwiched therebetween, and a cover insulating layer is formed on the base insulating layer to cover the wiring cover layer, and a terminal cover layer is formed to cover a terminal portion of the conductor trace. <CIT> discloses a trace structure comprising a plating seed layer over a base layer, a copper line over the plating seed layer and a protection layer over the copper line. The two edges of the protecting layer hang over the copper line.

The invention is defined in independent claims <NUM> and <NUM>.

Hereinafter, embodiments of the disclosure will be described in detail with reference to accompanying drawings so that those skilled in the art can easily replicate with the embodiments. However, the embodiments may have various modifications, and the disclosure is not limited thereto.

In the following description, when a predetermined part "includes" a predetermined element, the predetermined part does not exclude other elements, but may further include other components unless otherwise indicated.

The thickness and size of each layer shown in the drawings may be exaggerated, omitted or schematically drawn for the purpose of convenience or clarity. In addition, the size of elements does not utterly reflect an actual size. The same reference numbers will be assigned the same elements throughout the drawings.

In the description of the embodiments, it will be understood that, when a layer, a film, a region, or a plate is referred to as being "on" another layer, another film, another region, or another plate, it can be "directly" on the other layer, film, region, plate, or one or more intervening layers may also be present. Meanwhile, it will be understood that, when a layer, a film, a region, or a plate is referred to as being "directly on" another layer, another film, another region, or another plate, any intervening layer is not present.

The disclosure provides a printed circuit board, in which a conventional Ni surface treatment layer may be omitted by forming a surface treatment layer using a removable film-type material and an additional seed layer, and a portion of the top surface of the circuit pattern may be removed together with the seed layer when the seed layer is removed.

<FIG> is a sectional view showing the structure of a printed circuit board according to the first embodiment of the disclosure. <FIG> is a sectional view showing the circuit pattern of <FIG> in detail.

Referring to <FIG> and <FIG>, a printed circuit board <NUM> includes an insulating layer <NUM>, a plating seed layer <NUM>, a circuit pattern <NUM>, and a surface treatment layer <NUM>.

The insulating layer <NUM> may mean a support substrate of the printed circuit board <NUM> having a single circuit pattern, and mean an insulating layer area having one circuit pattern <NUM> in a printed circuit board having a plurality of lamination structures.

When the insulating layer <NUM> means one insulating layer constituting the plural lamination structures, a plurality of circuit patterns may be continuously formed on top and bottom surfaces of the insulating layer <NUM>.

The insulating layer <NUM> may constitute an insulating plate, and may include a thermosetting or thermoplastic polymeric substrate, a ceramic substrate, an organic-inorganic composite substrate, or a glass fiber impregnated substrate. If the insulating layer <NUM> includes the polymeric resin, the insulating layer may include epoxy insulating resin, or may include polyimide based resin.

The insulating layer <NUM> is formed thereon with the circuit pattern <NUM>.

Preferably, the plating seed layer <NUM> to be used when the circuit pattern <NUM> is formed is formed between the insulating layer <NUM> and the circuit pattern <NUM>.

The top and bottom surfaces of the plating seed layer <NUM> may have equal widths.

Then, the circuit pattern <NUM> is formed on the plating seed layer <NUM>.

Differently from the plating seed layer <NUM>, the circuit pattern <NUM> may be formed in a shape in which the top and bottom surfaces thereof have mutually different widths. In this case, the width of the bottom surface of the circuit pattern <NUM> may be equal to the width of the top surface or the bottom surface of the plating seed layer <NUM>, and the width of the top surface of the circuit pattern <NUM> may be narrower than that of the bottom surface of the circuit pattern <NUM>.

The plating seed layer <NUM> and the circuit pattern <NUM> may be formed of metal including copper (Cu) and having electrical conductivity.

The circuit pattern <NUM> may be formed through an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP), which is a typical process of fabricating a printed circuit board, and the details thereof will be omitted.

Although drawings show that a single circuit pattern <NUM> is formed on the insulating layer <NUM>, a plurality of circuit patterns <NUM> may be formed on at least one of the top and bottom surfaces of the insulating layer <NUM> while being spaced apart from each other.

Hereinafter, the circuit pattern <NUM> will be described in more detail with reference to <FIG>. The circuit pattern <NUM> includes a first part <NUM> formed on the plating seed layer <NUM> to have a bottom surface making contact with the top surface of the plating seed layer <NUM>, and a second part <NUM> formed on the first part <NUM> to have at least a portion of a top surface making contact with the bottom surface of the surface treatment layer <NUM>.

Although the circuit pattern <NUM> includes the first part <NUM> and the second part <NUM>, the first and second parts <NUM> and <NUM> are provided only for the purpose of explaining the shape of the circuit pattern <NUM>. Actually, the first and second parts <NUM> and <NUM> may be integrated with each other as one component.

The bottom surface of the first part <NUM> of the circuit pattern <NUM> directly makes contact with the top surface of the plating seed layer <NUM>.

In this case, the first part <NUM> of the circuit pattern <NUM> may have a shape in which the top and bottom surfaces of the first part <NUM> have equal widths.

In addition, the second part <NUM> of the circuit pattern <NUM> has mutually different widths at the bottom and top surfaces thereof.

In other words, in the second part <NUM> of the circuit pattern <NUM>, the width of the top surface is narrower than that of the bottom surface. Accordingly, the lateral side of the second part <NUM> is formed with a predetermined curvature lengthwise.

In this case, the second part <NUM> of the circuit pattern <NUM> may include a first lateral side having a first curvature and a second lateral side having a second curvature. In addition, the first curvature of the first lateral side may be substantially equal to the second curvature of the second lateral side.

Therefore, the circuit pattern <NUM> has left and right lateral sides. Each of the left and right lateral sides includes a first portion substantially perpendicular to a main surface and a second portion extending from the first portion and including a curved surface having a predetermined curvature.

The surface treatment layer <NUM> is formed on the circuit pattern <NUM> for the surface treatment of the circuit pattern <NUM>.

The surface treatment layer <NUM> may be formed of metal including gold (Au) or the alloy including Au.

When the surface treatment layer <NUM> is formed of the alloy including Au, the surface treatment layer <NUM> may be formed of the Au alloy including cobalt (Co). In this case, the surface treatment layer <NUM> is formed through the electrolytic plating.

Preferably, the surface treatment layer <NUM> is formed by performing the electroplating with respect to the plating seed layer <NUM> that is the same as the plating seed layer used when the circuit pattern <NUM> is formed.

The surface treatment layer <NUM> is formed on the circuit pattern <NUM>. Accordingly, the bottom surface of the surface treatment layer <NUM> directly makes contact with the top surface of the circuit pattern <NUM>.

In this case, the surface treatment layer <NUM> includes the bottom surface having the width wider than that of the top surface of the circuit pattern <NUM>.

Accordingly, the bottom surface of the surface treatment layer <NUM> includes a first bottom surface directly making contact with the top surface of the circuit pattern <NUM> and a second bottom surface that does not make contact with the top surface of the circuit pattern <NUM>.

In this case, the first bottom surface of the surface treatment layer <NUM> may be the central area of the bottom surface of the surface treatment layer <NUM>, and second bottom surfaces of the surface treatment layer <NUM> may be left and right areas of the surface treatment layer <NUM>.

In addition, the surface treatment layer <NUM> may have a shape in which the width of the top surface is equal to that of the bottom surface.

Meanwhile, the top and bottom surfaces of the surface treatment layer <NUM> may have widths narrower than that of the bottom surface of the circuit pattern <NUM>.

Accordingly, as shown in <FIG>, the surface treatment layer <NUM> has an eave structure of protruding outward from the upper lateral side of the circuit pattern <NUM>.

As described above, according to the disclosure, the surface treatment layer <NUM> including Au is formed using the plating seed layer <NUM> used when the circuit pattern <NUM> is formed, the nickel (Ni) surface treatment layer serving as the seed layer of the gold (Au) surface treatment layer may be removed.

In addition, as described above, according to the disclosure, the conventional nickel (Ni) surface treatment layer is omitted, and the surface treatment layer <NUM> including gold (Au) is formed directly on the circuit pattern <NUM>, thereby increasing the electrical conductivity, and reducing the electrical resistance. Accordingly, the RF characteristic may be improved.

In addition, as described above, according to the disclosure, the surface treatment layer <NUM> formed on the circuit pattern <NUM> has an eave structure of protruding outward from the upper lateral side of the circuit pattern <NUM>, so that the mounting area of the components mounted on the circuit pattern may be increased. Accordingly, the reliability of a customer may be improved.

Hereinafter, the relationship between the circuit pattern <NUM> and the surface treatment layer <NUM> will be described in more detail.

Referring to <FIG>, the circuit pattern <NUM> has the top surface and the bottom surface having widths different from each other. In this case, the bottom surface of the circuit pattern <NUM> has a first width W1, and the top surface of the circuit pattern <NUM> has the second width W2 narrower than the first width W1.

Accordingly, the bottom surface of the circuit pattern <NUM> includes a second area vertically overlapped with the top surface of the circuit pattern <NUM>, and a first area that is not overlapped with the top surface of the circuit pattern <NUM>.

In addition, the surface treatment layer <NUM> is formed on the circuit pattern <NUM>, and the top surface and the bottom surface of the surface treatment layer <NUM> have equal third widths W3.

In this case, the third width W3 is narrower than the first width W1 and wider than the second width W2.

Accordingly, the bottom surface of the surface treatment layer <NUM> includes a contact area making contact with the top surface of the circuit pattern <NUM> and a non-contact area that protrudes outward of the top surface of the circuit pattern <NUM> beyond the contact area and does not make contact with the top surface of the circuit pattern <NUM>.

In this case, the bottom surface of the circuit pattern <NUM> may have a width wider than that of the top surface of the circuit pattern <NUM> by a fourth width W4.

That is to say, the first area of the circuit pattern <NUM> may have the fourth width W4.

In this case, the first area of the circuit pattern <NUM> is partially overlapped with the non-contact area of the surface treatment layer <NUM>.

In other words, the first area of the circuit pattern <NUM> includes a third area that is not vertically overlapped with the non-contact area of the surface treatment layer <NUM> and has a fifth width W5, and a fourth area that is vertically overlapped with the non-contact area of the surface treatment layer <NUM> and has a sixth width W6.

In this case, preferably, the fifth width W5 of the third area is wider than the sixth width W6 of the fourth area.

More preferably, the ratio of the fifth width W5 to the sixth width W6 is in the range of <NUM> to <NUM>.

In other words, when the ratio of the fifth width W5 to the sixth width W6 is less than <NUM>, the non-contact area of the surface treatment layer <NUM> has a wider area. In this case, the non-contact area of the surface treatment layer <NUM> protruding outward of the top surface of the circuit pattern <NUM> has an unstable structure, so that the non-contact area may be collapsed, thereby causing the electrical short.

In addition, when the ratio of the fifth width W5 to the sixth width W6 is more than <NUM>, the non-contact area of the surface treatment layer <NUM> has a narrower width. In this case, as the entire width of the surface treatment layer <NUM> is narrowed, the mounting area may be narrowed.

Therefore, according to the disclosure, when the surface treatment layer <NUM> having the eave structure is formed as described above, the ratio of the fifth width W5 to the sixth width W6 satisfies the range of <NUM> to <NUM>. In this case, the fifth width W5 is wider than the sixth width W6, so that the fifth width W5 has a value ranging from <NUM> to <NUM> times that of the sixth width W6.

Hereinafter, a method of fabricating the printed circuit board shown in <FIG> will be described in detail with reference to <FIG>.

<FIG> are sectional views showing the method of fabricating the printed circuit board of <FIG> in process sequence.

Referring to <FIG>, after preparing the insulating layer <NUM>, the plating seed layer <NUM> is formed on the prepared insulating layer <NUM>.

The plating seed layer <NUM> may be formed by performing electroless plating with respect to the insulating layer <NUM> using metal including Cu.

The insulating layer <NUM> may include a thermosetting or thermoplastic polymeric substrate, a ceramic substrate, an organic-inorganic composite substrate, or a glass fiber impregnated substrate. If the insulating layer <NUM> includes the polymeric resin, the insulating layer <NUM> may include epoxy insulating resin, or may include polyimide based resin.

The plating seed layer <NUM> may be formed by performing typical copper clad laminate (CCL) instead of the electroless plating with respect to the surface of the insulating layer <NUM>.

In this case, when the plating seed layer <NUM> is formed through the electroless plating, surface roughness is applied to the top surface of the insulating layer <NUM>, so that the electroless plating may be smoothly performed.

The electroless plating scheme may be performed in the sequence of a degreasing process, a soft etching process, a pre-catalyst process, a catalyst treatment process, an accelerator process, an electroless plating process, and an anti-oxidation treatment process. In addition, the plating seed layer <NUM> may be formed by sputtering metallic particles using plasma.

In this case, before forming the plating seed layer <NUM> through the plating process, a desmear process of removing smears from the surface of the insulating layer <NUM> may be additionally performed. The desmear process is performed to enhance plating power for the formation of the plating seed layer <NUM> by applying surface roughness onto the surface of the insulating layer <NUM>.

Thereafter, referring to <FIG>, a first mask <NUM> is formed on the plating seed layer <NUM>. In this case, the first mask <NUM> may include a dry film.

In this case, the first mask <NUM> has an opening a to expose at least a portion of the top surface of the plating seed layer <NUM>.

In this case, the top surface of the plating seed layer <NUM> exposed by the opening a of the first mask <NUM> corresponds to an area for the circuit pattern <NUM>.

In other words, the first mask <NUM> having the opening a to expose the area for the circuit pattern <NUM> in the top surface of the plating seed layer <NUM> is formed on the plating seed layer <NUM>.

In this case, the first mask <NUM> may be formed to cover the whole top surface of the plating seed layer <NUM>. Accordingly, the opening a may be formed by removing a portion of an area of the plating seed layer <NUM> for the formation of the circuit pattern <NUM>.

Next, referring to <FIG>, the circuit pattern <NUM> is formed on the plating seed layer <NUM> so that the circuit pattern <NUM> is filled in at least a portion of the opening a of the first mask <NUM>.

The circuit pattern <NUM> may be formed while being filled in the at least a portion of the opening a of the first mask <NUM> by performing electroplating with respect to the plating seed layer <NUM> serving as a seed layer using a conductive material, preferably, the alloy including Cu.

Next, referring to <FIG>, the first mask <NUM> is removed from the plating seed layer <NUM>.

In this case, after the first mask <NUM> has been removed, the residues of the first mask <NUM> may remain on the surface of the plating seed layer <NUM>. Accordingly, an additional process of removing the residues of the first mask <NUM> may be performed.

Then, referring to <FIG>, a second mask <NUM> is formed on the plating seed layer <NUM>.

In this case, preferably, the second mask <NUM> may include a dry film having strong heat resistance and an easy removable property.

The second mask <NUM> includes an opening b to expose the top surface of the circuit pattern <NUM>.

In this case, the opening b of the second mask <NUM> is formed with a width narrower than that of the top surface of the circuit pattern <NUM>.

Accordingly, at least a portion of the top surface of the circuit pattern <NUM> is covered by the second mask <NUM>. Preferably, the central area of the top surface of the circuit pattern <NUM> is exposed to the outside by the opening b of the second mask <NUM>, and the edge areas of the top surface of the circuit pattern <NUM> is covered by the second mask <NUM>.

Next, referring to <FIG>, the surface treatment layer <NUM> is formed on the circuit pattern <NUM> by employing both of the plating seed layer <NUM> and the circuit pattern <NUM> as a seed layer.

In this case, the surface treatment layer <NUM> is formed with a width equal to that of the opening b of the second mask <NUM>.

The surface treatment layer <NUM> may be formed of metal including only gold (Au) or the alloy including Au.

When the surface treatment layer <NUM> is formed of the alloy including Au, the surface treatment layer <NUM> may be formed of the Au alloy including Co. In this case, the surface treatment layer <NUM> may be formed through the electroless plating.

Preferably, the surface treatment layer <NUM> is formed by performing the electroplating with respect to the plating seed layer <NUM> which is the same as a plating seed layer used when the circuit pattern <NUM> is formed. In other words, the surface treatment layer <NUM> is formed through the electroplating as the plating seed layer <NUM> is connected with the circuit pattern <NUM> so that a short occurs between the plating seed layer <NUM> and the circuit pattern <NUM>.

The surface treatment layer <NUM> is formed on the circuit pattern <NUM> so that the bottom surface of the surface treatment layer <NUM> directly makes contact with the top surface of the circuit pattern <NUM>.

In this case, the surface treatment layer <NUM>, which exists before the plating seed layer <NUM> is removed, includes top and bottom surfaces having widths narrower than that of the top surface of the circuit pattern <NUM>.

Accordingly, the top surface of the circuit pattern <NUM> includes a part that makes contact with the surface treatment layer <NUM> and a part that does not make contact with the surface treatment layer <NUM>.

Next, referring to <FIG>, the second mask <NUM> formed on the plating seed layer <NUM> is removed.

In this case, if the second mask <NUM> is removed similarly to the process of removing the first mask <NUM>, an additional process may be performed to remove the residues of the second mask <NUM> remaining on the plating seed layer <NUM>.

Thereafter, referring to <FIG>, a process of removing a portion of the plating seed layer <NUM>, which is formed on the insulating layer <NUM> and has no the-circuit pattern <NUM>, is performed.

In other words, after the second mask <NUM> has been removed, the process of removing the portion of the plating seed layer <NUM> formed on the insulating layer <NUM> is performed. In this case, when the process of removing the plating seed layer <NUM> is performed, a portion of the plating seed layer <NUM> which is formed under the circuit pattern <NUM> is not removed due to the circuit pattern <NUM>, but only the portion of the plating seed layer <NUM> having no circuit pattern <NUM> is selectively removed.

In this case, edge areas of the top surface of the circuit pattern <NUM> have no the surface treatment layer <NUM>. Accordingly, when the process of removing the portion of the plating seed layer <NUM>, which is formed on the insulating layer <NUM> and has no the circuit pattern <NUM>, is performed, the edge areas of the top surface of the circuit pattern <NUM>, which are not covered by the surface treatment layer <NUM>, are also removed.

In this case, only a portion of the top surface of the circuit pattern <NUM>, which is not covered by the surface treatment layer <NUM>, is removed.

Accordingly, upper lateral sides of the circuit pattern <NUM> are removed with a predetermined curvature differently from the lower portion of the circuit pattern <NUM>.

Therefore, the bottom surface of the surface treatment layer <NUM> may have the width wider than that of the top surface of the circuit pattern <NUM>.

In addition, due to the process of removing the above plating seed layer <NUM>, the bottom surface of the surface treatment layer <NUM> includes a first bottom surface directly making contact with the top surface of the circuit pattern <NUM> and second bottoms surface that does not make contact with the top surface of the circuit pattern <NUM>.

In this case, the first bottom surface of the surface treatment layer <NUM> may be the central area of the bottom surface of the surface treatment layer <NUM>, and the second bottom surfaces of the surface treatment layer <NUM> may be left and right areas of the surface treatment layer <NUM>.

Meanwhile, the top and bottom surfaces of the surface treatment layer <NUM> may have the widths narrower than the width of the bottom surface of the circuit pattern <NUM>.

In other words, as the edge areas of the upper portion of the circuit pattern <NUM> are removed in the process of removing the plating seed layer <NUM>, the circuit pattern <NUM> may be divided into the first part <NUM> and the second part <NUM> as described above.

In this case, the first part <NUM> of the circuit pattern <NUM> has a shape in which the top surface and the bottom surface of the first part <NUM> have equal widths.

In addition, the second part <NUM> of the circuit pattern <NUM> has a shape in which the top surface and the bottom surface have mutually different widths.

In other words, in the second part <NUM> of the circuit pattern <NUM>, the width of the top surface is narrower than that of the bottom surface. Accordingly, the lateral sides of the second part <NUM> are formed with a predetermined curvature lengthwise.

In this case, the second part <NUM> of the circuit pattern <NUM> may include the first lateral side having the first curvature and the second lateral side having the second curvature. In addition, the first curvature of the first lateral side may be substantially equal to the second curvature of the second lateral side.

Therefore, the circuit pattern <NUM> has left and right lateral sides, and each of the left and right lateral sides includes a first portion substantially perpendicular to a main surface and a second portion extending from the first portion and including a curved surface having a predetermined curvature.

Accordingly, as shown in <FIG>, the surface treatment layer <NUM> has the eave structure of protruding outward from the upper lateral side of the circuit pattern <NUM>.

As described above, according to the disclosure, the surface treatment layer <NUM> including Au is formed by utilizing the plating seed layer <NUM> used when the circuit pattern <NUM> is formed, so that the nickel (Ni) surface treatment layer serving as the seed layer for the gold (Au) surface treatment layer may be omitted.

In addition, as described above, according to the disclosure, the surface treatment layer <NUM> formed on the circuit pattern <NUM> has the eave structure of protruding outward from the upper lateral side of the circuit pattern <NUM>, so that the mounting area of the components mounted on the circuit pattern may be increased. Accordingly, the reliability of a customer may be improved.

<FIG> is a sectional view showing the structure of a printed circuit board according to the second embodiment of the disclosure.

Referring to <FIG>, a printed circuit board <NUM> includes an insulating layer <NUM>, a plating seed layer <NUM>, a circuit pattern <NUM>, and a surface treatment layer <NUM>.

The insulating layer <NUM> may constitute an insulating plate, and may include a thermosetting or thermoplastic polymeric substrate, a ceramic substrate, an organic-inorganic composite substrate, or a glass fiber impregnated substrate. If the insulating layer <NUM> includes the polymeric resin, the insulating layer <NUM> may include epoxy insulating resin, or may include polyimide based resin.

The circuit pattern <NUM> is formed on the insulating layer <NUM>.

Preferably, the plating seed layer <NUM> for the formation of the circuit pattern <NUM> is formed between the insulating layer <NUM> and the circuit pattern <NUM>.

In addition, the circuit pattern <NUM> is formed on the plating seed layer <NUM>.

Differently from the plating seed layer <NUM>, the circuit pattern <NUM> may have a shape in which the top and bottom surfaces thereof have mutually different widths. In this case, the width of the bottom surface of the circuit pattern <NUM> may be equal to that of the top surface or the bottom surface of the plating seed layer <NUM>. The width of the top surface of the circuit pattern <NUM> may be narrower than that of the bottom surface of the circuit pattern <NUM>.

The plating seed layer <NUM> and the circuit pattern <NUM> are formed of metal including Cu and having electrical conductivity.

Although drawings show that a single circuit pattern <NUM> is formed on the insulating layer <NUM>, a plurality of circuit patterns <NUM> may be formed on at least one of the top surface and the bottom surface of the insulating layer <NUM> while being spaced apart from each other by a predetermined distance.

In this case, the circuit pattern <NUM> may have a shape similar to that of the circuit pattern <NUM> according to the first embodiment. Although both lateral sides of the circuit pattern <NUM> according to the first embodiment have a predetermined curvature, the circuit pattern <NUM> according to the second embodiment has a predetermined curvature only at an upper right lateral side thereof.

In other words, the left lateral side of the circuit pattern <NUM> is substantially perpendicular to the bottom surface of the circuit pattern <NUM>, and the right lateral side of the circuit pattern <NUM> has a portion substantially perpendicular to the bottom surface of the circuit pattern <NUM> and a curved surface portion extending from the perpendicular portion and having a predetermined curvature.

The surface treatment layer <NUM> is formed on the circuit pattern <NUM> to perform the surface treatment of the circuit pattern <NUM>.

The surface treatment layer <NUM> may be formed of metal including only Au or the alloy including Au.

When the surface treatment layer <NUM> is formed of the alloy including Au, the surface treatment layer <NUM> may be formed of the Au alloy including Co. In this case, the surface treatment layer <NUM> is formed through electroless plating.

Preferably, the surface treatment layer <NUM> is formed by performing the electroplating with respect to the plating seed layer <NUM> which is the same as the plating seed layer used when the circuit pattern <NUM> is formed.

The surface treatment layer <NUM> is formed on the circuit pattern <NUM>, so that the bottom surface of the surface treatment layer <NUM> directly makes contact with the top surface of the circuit pattern <NUM>.

In this case, the surface treatment layer <NUM> includes the bottom surface having a width wider than that of the top surface of the circuit pattern <NUM>.

Accordingly, the bottom surface of the surface treatment layer <NUM> includes a first bottom surface that directly makes contact with the top surface of the circuit pattern <NUM> and a second bottom surface that does not make contact with the top surface of the circuit pattern <NUM>.

In this case, the first bottom surface of the surface treatment layer <NUM> may include the central area and a left area of the bottom surface of the surface treatment layer <NUM>, and the second bottom surface of the surface treatment layer <NUM> may include a right area of the surface treatment layer <NUM>.

In addition, the surface treatment layer <NUM> may have a shape in which the top and bottom surfaces thereof have equal widths.

Meanwhile, both of the top and bottom surfaces of the surface treatment layer <NUM> may have widths narrower than that of the bottom surface of the circuit pattern <NUM>.

Accordingly, differently from that of the first embodiment, the surface treatment layer <NUM> according to the second embodiment has an eave structure of protruding outward from only the upper lateral side of the circuit pattern <NUM>.

As described above, according to the disclosure, the surface treatment layer <NUM> including Au is formed utilizing the plating seed layer <NUM> used when the circuit pattern <NUM> is formed, so that the nickel (Ni) surface treatment layer serving as the seed layer for the gold (Au) surface treatment layer may be omitted.

In addition, as described above, according to the disclosure, the surface treatment layer <NUM> formed on the circuit pattern <NUM> has an eave structure of protruding outward from the upper right lateral side of the circuit pattern <NUM>, so that the mounting area of the components mounted on the circuit pattern <NUM> may be increased. Accordingly, the reliability of a customer may be improved.

Hereinafter, a method of fabricating the printed circuit board shown in <FIG> will be described with reference to <FIG>.

<FIG> are sectional views showing the method of fabricating the printed circuit board shown in <FIG> in process sequence.

First, referring to <FIG>, after preparing the insulating layer <NUM>, the plating seed layer <NUM> is formed on the prepared insulating layer <NUM>.

Next, the circuit pattern <NUM> is formed by performing electroplating with respect to the plating seed layer <NUM> serving as a seed layer using a conductive material, preferably, the alloy including Cu.

Thereafter, a mask <NUM> is formed on the plating seed layer <NUM>.

In this case, preferably, the mask <NUM> may include a dry film having strong heat resistance and an easy removable property.

The mask <NUM> includes an opening B to expose the top surface of the circuit pattern <NUM>.

The width of the opening B of the mask <NUM> is narrower than that of the top surface of the circuit pattern <NUM>.

Accordingly, at least a portion of the top surface of the circuit pattern <NUM> is covered by the mask <NUM>. Preferably, the central area and the left area of the top surface of the circuit pattern <NUM> are exposed to the outside by the opening B of the mask <NUM>, and the right edge area of the top surface of the circuit pattern <NUM> is covered by the mask <NUM>.

Next, referring to <FIG>, the surface treatment layer <NUM> is formed on the circuit pattern <NUM> by employing the plating seed layer <NUM> and the circuit pattern <NUM> as a seed layer.

In this case, the surface treatment layer <NUM> has a width equal to that of the opening B of the mask <NUM>.

Preferably, the surface treatment layer <NUM> is formed by performing the electroplating with respect to the plating seed layer <NUM> which is the same as the plating seed layer used when the circuit pattern <NUM> is formed. In other words, the surface treatment layer <NUM> is formed through the electroplating as the plating seed layer <NUM> is connected with the circuit pattern <NUM> so that a short occurs between the plating seed layer <NUM> and the circuit pattern <NUM>.

In this case, the surface treatment layer <NUM>, which exists before the plating seed layer <NUM> is removed, includes top and bottom surfaces having a width narrower than that of the top surface of the circuit pattern <NUM>.

Accordingly, the top surface of the circuit pattern <NUM> includes a portion, which makes contact with the surface treatment layer <NUM>, and a portion which does not make contact with the surface treatment layer <NUM>.

Thereafter, referring to <FIG>, the mask <NUM> is removed from the plating seed layer <NUM>.

Then, a process of removing a portion of the plating seed layer <NUM>, which is formed on the insulating layer <NUM> and has no circuit pattern <NUM>, is performed.

In other words, after the mask <NUM> has been removed, the process of removing the portion of the plating seed layer <NUM>, which is formed on the insulating layer <NUM> and has no circuit pattern <NUM>, is performed. In this case, when the process of removing the portion of the plating seed layer <NUM>, which is formed on the insulating layer <NUM> and has no circuit pattern <NUM>, is performed, a portion of the plating seed layer <NUM> which is formed under the circuit pattern <NUM> is not removed due to the circuit pattern <NUM>, but only the portion of the plating seed layer <NUM> having no circuit pattern <NUM> is selectively removed.

In this case, a right edge area of the top surface of the circuit pattern <NUM> has no surface treatment layer <NUM>. Accordingly, when the process of removing the plating seed layer <NUM> is performed, the right edge area of the top surface of the circuit pattern <NUM>, which are not covered by the surface treatment layer <NUM>, are also removed.

In this case, only the upper portion of the circuit pattern <NUM>, which is not covered by the surface treatment layer <NUM>, is removed.

Accordingly, the upper right portion of the circuit pattern <NUM>, which is not covered by the surface treatment layer <NUM>, has a lateral side with a predetermined curvature differently from that of the lower portion of the circuit pattern <NUM>.

Accordingly, the bottom surface of the surface treatment layer <NUM> has a width wider than that of the top surface of the circuit pattern <NUM>.

The bottom surface of the surface treatment layer <NUM> includes a first bottom surface, which directly makes contact with the top surface of the circuit pattern <NUM>, and a second bottom surface which does not make contact with the top surface of the circuit pattern <NUM> due to the process of removing the plating seed layer <NUM>.

In this case, the first bottom surfaces of the surface treatment layer <NUM> may include the central area and a left area of the bottom surface of the surface treatment layer <NUM>, and the second bottom surface of the surface treatment layer <NUM> may include the right area of the surface treatment layer <NUM>.

In addition, the upper right lateral side of the circuit pattern <NUM> is formed with a predetermined curvature lengthwise.

Accordingly, as shown in <FIG>, the surface treatment layer <NUM> has an eave structure of protruding outward from the upper right lateral side of the circuit pattern <NUM>.

As described above, according to the disclosure, the surface treatment layer <NUM> including Au is formed using the plating seed layer <NUM> used when the circuit pattern <NUM> is formed, so that the nickel (Ni) surface treatment layer serving as the seed layer for the gold (Au) surface treatment layer may be omitted.

<FIG> is a sectional view showing the structure of a printed circuit board according to the third embodiment of the disclosure.

In this case, since the insulating layer <NUM> and the plating seed layer <NUM> are the same as those of the first embodiment and the second embodiment, the details thereof will be omitted.

In addition, the circuit pattern <NUM> according to the second embodiment includes an upper right lateral side having a predetermined curvature.

However, the circuit pattern <NUM> according to the third embodiment of the disclosure has an upper left lateral side having a predetermined curvature, and a right lateral side is formed to be substantially perpendicular to the bottom surface.

<FIG> is a sectional view showing a printed circuit board <NUM> according to a fourth embodiment of the disclosure.

Referring to <FIG>, the printed circuit board <NUM> includes an insulating layer <NUM>, a plating seed layer <NUM>, a circuit pattern <NUM>, a surface treatment layer <NUM>, and a protective layer <NUM>.

In this case, since the insulating layer <NUM>, the plating seed layer <NUM>, the circuit pattern <NUM>, and the surface treatment layer <NUM> are the same as those of the printed circuit board according to the first embodiment of the disclosure shown in <FIG>, the details thereof will be omitted.

The printed circuit board <NUM> according to the fourth embodiment further includes a protective layer <NUM> formed on the insulating layer <NUM> to cover the surface of the insulating layer <NUM>, the lateral side of the plating seed layer <NUM>, the lateral side of the circuit pattern <NUM>, and a portion of the top surface of the surface treatment layer <NUM>.

The protective layer <NUM> protrudes from the top surface of the surface treatment layer <NUM> by a predetermined height.

The protective layer <NUM> may include solder resist, protect the surface of the insulating layer <NUM>, and at least a portion of the top surface of the surface treatment layer <NUM> of the circuit pattern formed on the insulating layer <NUM>.

The protective layer <NUM> according to the fourth embodiment covers the exposed entire surface of the insulating layer <NUM>.

<FIG> is a sectional view showing a printed circuit board according to a fifth embodiment.

Referring to <FIG>, a printed circuit board <NUM> includes an insulating layer <NUM>, a plating seed layer <NUM>, a circuit pattern <NUM>, a surface treatment layer <NUM>, and a protective layer <NUM>.

Since the insulating layer <NUM>, the plating seed layer <NUM>, the circuit pattern <NUM>, and the surface treatment layer <NUM> are the same as those of the printed circuit board according to the first embodiment of the disclosure shown in <FIG>, the details thereof will be omitted.

The printed circuit board <NUM> according to the fifth embodiment further includes the protective layer <NUM> formed on the insulating layer <NUM> to cover a portion of the surface of the insulating layer <NUM>.

The protective layer <NUM> is formed on the insulating layer <NUM> and spaced apart from the circuit pattern <NUM> by a predetermined distance.

The protective layer <NUM> may include solder resist, protect the surface of the insulating layer <NUM>, and expose the top surface of the surface treatment layer <NUM> of the circuit pattern formed on the insulating layer <NUM> and a portion of the surface of the insulating layer <NUM>.

According to the embodiment of the disclosure, the surface treatment layer is formed by utilizing a removable film-type material and a plating seed layer used in the circuit pattern, so that the electrolytic surface treatment and the electroless surface treatment may be selectively used without the limitation on the design.

According to the embodiment of the disclosure, the surface treatment layer including Au is formed using the plating seed layer used when the circuit pattern is formed, so that a Ni surface treatment layer serving as a seed layer for the Au surface treatment layer according to the related art may be omitted. Accordingly, the thickness of a product may be reduced, and product cost may be reduced due to the omission of the Ni surface treatment layer.

In addition, according to the disclosure, the conventional nickel (Ni) surface treatment layer is omitted, and the surface treatment layer <NUM> including gold (Au) is formed directly on the circuit pattern <NUM>, thereby increasing the electrical conductivity, and reducing the electrical resistance. Accordingly, the RF characteristic may be improved.

Further, according to the embodiment of the disclosure, the surface treatment layer formed on the circuit pattern has an eave structure of protruding outward from the upper lateral side of the circuit pattern, so that the mounting area of the components mounted on the circuit pattern may be increased. Accordingly, the reliability of a customer may be improved.

Any reference in this specification to "one embodiment," "an embodiment," "example embodiment," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments.

Claim 1:
A printed circuit board (<NUM>) comprising:
an insulating layer (<NUM>);
a plating seed layer (<NUM>) on the insulating layer (<NUM>);
a circuit pattern (<NUM>) on the plating seed layer (<NUM>); and
a surface treatment layer (<NUM>) on the circuit pattern (<NUM>),
wherein the surface treatment layer (<NUM>) includes a bottom surface having a width wider than a width of a top surface of the circuit pattern (<NUM>),
wherein the bottom surface of the surface treatment layer (<NUM>) comprises:
a first portion contacted with the top surface of the circuit pattern (<NUM>), and
a second portion spaced apart from the insulating layer (<NUM>), the plating seed layer (<NUM>) and the circuit pattern (<NUM>) by a predetermined distance,
wherein the width of the top surface of the circuit pattern (<NUM>) is narrower than a width of a bottom surface of the circuit pattern (<NUM>),
the bottom surface of the circuit pattern (<NUM>) comprises a first area vertically overlapped with the top surface of the circuit pattern (<NUM>) and a second area except for the first area,
wherein the second area of the circuit pattern (<NUM>) comprises a third area that is not vertically overlapped with the second portion of the surface treatment layer (<NUM>) and a fourth area vertically overlapped with the second portion of the surface treatment layer (<NUM>), and
wherein the third area has a width wider than a width of the fourth area,
wherein the plating seed layer (<NUM>) serves as a seed layer for the circuit pattern (<NUM>) and the surface treatment layer (<NUM>),
wherein each of the plating seed layer (<NUM>) and the circuit pattern (<NUM>) is formed of metal including copper, Cu, and having electrical conductivity,
wherein the surface treatment layer (<NUM>) is formed of metal including gold, Au, or an alloy including Au.