Patent Description:
Such a multi-gate transistor uses a three-dimensional channel, which facilitates scaling. In addition, a current control capability may be improved without increasing a gate length of the multi-gate transistor. Furthermore, a short channel effect (SCE), where a channel region potential is adversely affected by a drain voltage, may be suppressed.

Meanwhile, as a pitch size of the semiconductor device decreases, research has focused on decreasing a capacitance and securing electrical stability between contacts in the semiconductor device.

<CIT> discloses a semiconductor device that includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

Aspects of the present invention provide a semiconductor device with improved reliability.

A semiconductor device according to the invention is defined by independent claim <NUM>. Further developments of the semiconductor device according to the invention are specified by the dependent claims.

The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

The terms "first", "second", and the like as used herein are used to describe various elements or components, but these elements or components are not limited by these terms. These terms are used only in order to distinguish one element or component from another element or component. Accordingly, a first element or component mentioned below may also be a second element or component within the technical spirit of the present disclosure.

In the drawings of a semiconductor device, a fin field effect transistor (FinFET) including a channel region having a fin-shaped pattern shape, a transistor including a nanowire or a nanosheet, and a multi-bridge channel field effect transistor (MBCFET™) or a vertical field effect transistor (vertical FET) have been illustrated by way of example, but the present disclosure is not limited thereto. The semiconductor device may include a tunneling field effect transistor (tunneling FET) or a three-dimensional (3D) transistor. The semiconductor device may include a planar transistor. In addition, the technical concept of the present disclosure may be applied to two-dimensional (2D) material-based FETs and heterostructures thereof.

In addition, the semiconductor device may include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, or the like.

<FIG> is an example of a layout diagram for describing a semiconductor device <NUM>. <FIG> is a cross-sectional view taken along line A-A of <FIG>. <FIG> is a cross-sectional view taken along line B-B of <FIG>. <FIG> is a cross-sectional view taken along line C-C of <FIG>. For convenience of explanation, via plugs <NUM> and <NUM> have not been illustrated in <FIG>.

Referring to <FIG>, a semiconductor device <NUM> may include one or more first active patterns AP1, one or more second active patterns AP2, a plurality of gate electrodes <NUM>, first source/drain contacts <NUM>, second source/drain contacts <NUM>, gate contacts <NUM>, a power rail PR, a power rail via PVA, and a buried conductive pattern <NUM>. In the implementations illustrated herein, the phrase source/drain contacts may be understood to mean a contact connected to a source terminal region or a drain terminal region of a transistor. The phrase source/drain barrier film can refer to a barrier film for a source terminal region or a drain terminal region of a transistor. In some implementations, whether a region is a source or drain terminal region can depend on the applied voltage.

First, a substrate <NUM> may be provided. The substrate <NUM> may include a plurality of active regions and a field region. Each of the plurality of active regions may be an area where the first active pattern AP1 or the second active pattern AP2 is disposed. The field region may be formed immediately adjacent to the plurality of active regions. The field region may border the plurality of active regions.

The plurality of active regions are spaced apart from each other. The plurality of active regions may be separated from each other by the field region. In other words, an element isolation film may be disposed around the plurality of active regions spaced apart from each other. In this case, a portion of the element isolation film positioned between the plurality of active regions may be the field region. For example, a portion where a channel region of a transistor, which may be an example of the semiconductor device, is formed may be the active region, and a portion dividing the channel region of the transistor formed in the active region may be the field region. Alternatively, the active region may be a region where a fin-shaped pattern or a nanosheet used as a channel region of a transistor is formed, and the field region may be a region where the fin-shaped pattern or the nanosheet used as the channel region is not formed.

The substrate <NUM> may include a first surface <NUM> and a second surface 100BS opposite to each other in a first direction D1. The substrate <NUM> may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate <NUM> may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, a lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

Each of the first active patterns AP1 and the second active patterns AP2 may be disposed on the first surface <NUM> of the substrate <NUM>. Each of the first active patterns AP1 and the second active patterns AP2 may extend to be elongated along a second direction D2 on the substrate <NUM>. The first active patterns AP1 and the second active patterns AP2 may be spaced apart from each other in a third direction D3.

Each of the first active patterns AP1 and the second active patterns AP2 may include long sides extending in the second direction D2 and short sides extending in the third direction D3. Here, the second direction D2 is not parallel to the third direction D3 and the first direction D1. In addition, the third direction D3 is not parallel to the first direction D1. The first direction D1 may be a thickness direction of the substrate <NUM>.

Each of the first active patterns AP1 and the second active patterns AP2 may be a multi-channel active pattern. In the semiconductor device, each of the first active patterns AP1 and the second active patterns AP2 may be, for example, a fin-shaped pattern. Each of the first active patterns AP1 and the second active patterns AP2 may be used as the channel region of the transistor. It has been illustrated that the number of each of first active patterns AP1 and second active pattern AP2 is three, but this is only for convenience of explanation, and the present disclosure is not limited thereto. The number of each of first active patterns AP1 and second active pattern AP2 may be one or more.

The first active patterns AP1 and the second active patterns AP2 may be portions of the substrate <NUM>, respectively, and may include epitaxial layers grown from the substrate <NUM>. The first active pattern AP1 and the second active pattern AP2 may include, for example, silicon or germanium, which is an elemental semiconductor material. In addition, the first active pattern AP1 and the second active pattern AP2 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping carbon (C), silicon (Si), germanium (Ge), and tin (Sn) with a group IV element.

The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements, with each other.

In some implementations, the first active pattern AP1 and the second active pattern AP2 may include the same material. For example, each of the first active pattern AP1 and the second active pattern AP2 may be a silicon fin-shaped pattern. Alternatively, for example, each of the first active pattern AP1 and the second active pattern AP2 may be a fin-shaped pattern including a silicon-germanium pattern. As another example, the first active pattern AP1 and the second active pattern AP2 may include different materials. For example, some of the first active patterns AP1 and the second active patterns AP2 may be silicon fin-shaped patterns, and the others of the first active patterns AP1 and the second active patterns AP2 may be fin-shaped patterns including silicon-germanium patterns.

A field insulating film <NUM> is formed on the substrate <NUM>. The field insulating film <NUM> is formed on the first surface <NUM> of the substrate <NUM>. The field insulating film <NUM> may be disposed on a buried conductive pattern <NUM> to be described later. The field insulating film <NUM> may cover an upper surface of the buried conductive pattern <NUM>.

In some implementations, a bottom surface of the field insulating film <NUM> defining the buried conductive pattern <NUM> may be flat. For example, the bottom surface of the field insulating film <NUM> defining the buried conductive pattern <NUM> may be coplanar with the first surface <NUM> of the substrate <NUM>. However, implementations of the present disclosure is not limited thereto.

The field insulating film <NUM> covers sidewalls of the first active patterns AP1 and sidewalls of the second active patterns AP2. The field insulating film <NUM> may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. It has been illustrated that the field insulating film <NUM> is a single film, but the present disclosure is not limited thereto. Although not illustrated, the field insulating film <NUM> may include a field liner extending along sidewalls and bottom surfaces of fin trenches defining the first and second active patterns AP1 and AP2 and a field filling film disposed on the field liner.

The plurality of gate electrodes <NUM> may be disposed on the substrate <NUM>. For example, the plurality of gate electrodes <NUM> may be disposed on the field insulating film <NUM>. Each of the plurality of gate electrodes <NUM> may extend in the third direction D3. The plurality of gate electrodes <NUM> may be spaced apart from each other in the second direction D2.

The plurality of gate electrodes <NUM> may be disposed on the first active patterns AP1 and the second active patterns AP2. The plurality of gate electrodes <NUM> may cover the first active patterns AP1 and the second active patterns AP2. The plurality of gate electrodes <NUM> may cross the first active patterns AP1 and the second active patterns AP2. Each of the plurality of gate electrodes <NUM> may include long sides extending in the third direction D3 and short sides extending in the second direction D2.

In <FIG> and <FIG>, an upper surface of each of the plurality of gate electrodes <NUM> may be a convex curved surface recessed toward an upper surface of the first active pattern AP1, but is not limited thereto. That is, Although not illustrated in <FIG> and <FIG>, the upper surface of each of the plurality of gate electrodes <NUM> may be a flat plane.

The plurality of gate electrodes <NUM> may include, for example, at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

Each of the plurality of gate electrodes <NUM> may include conductive metal oxide, conductive metal oxynitride, or the like, and may include a form in which the above-described material is oxidized.

The plurality of gate electrodes <NUM> may be disposed on both sides of a first source/drain pattern <NUM> to be described later. Although not illustrated, the plurality of gate electrodes <NUM> may be disposed on both sides of a second source/drain pattern <NUM>.

As an example, both of the gate electrodes <NUM> disposed on both sides of the first source/drain pattern <NUM> or both sides of the second source/drain pattern <NUM> may be normal gate electrodes used as gates of the transistor. As another example, the gate electrode <NUM> disposed on one side of the first source/drain pattern <NUM> or one side of the second source/drain pattern <NUM> may be used as a gate of the transistor, but the gate electrode <NUM> disposed on the other side of the first source/drain pattern <NUM> or the other side of the second source/drain pattern <NUM> may be a dummy gate electrode.

A plurality of gate spacers <NUM> may be disposed on sidewalls of each of the plurality of gate electrodes <NUM>. The plurality of gate spacers <NUM> are not in contact with the plurality of gate electrodes <NUM>. A gate insulating film <NUM> may be disposed between the gate spacer <NUM> and the sidewalls of the gate electrode <NUM>. Each of the plurality of gate spacers <NUM> may extend in the third direction D3. The plurality of gate spacers <NUM> may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO<NUM>), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

The gate insulating film <NUM> may extend along the sidewalls and a bottom surface of each of the plurality of gate electrodes <NUM>. The gate insulating film <NUM> may be formed on the first active patterns AP1, the second active patterns AP2, and the field insulating film <NUM>. The gate insulating film <NUM> may be formed between the plurality of gate electrodes <NUM> and the plurality of gate spacers <NUM>.

The gate insulating film <NUM> may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of the silicon oxide. The high-k material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

It has been illustrated that the gate insulating film <NUM> is a single film, but this is only for convenience of explanation, and the present disclosure is not limited thereto. The gate insulating film <NUM> may include a plurality of films. The gate insulating film <NUM> may include an interfacial layer and a high-k insulating film disposed between the first active patterns AP1 and the gate electrodes <NUM> and between the second active patterns AP2 and the plurality of gate electrodes <NUM>.

The semiconductor device may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating film <NUM> may include a ferroelectric material film having ferroelectric characteristics and a paraelectric material film having paraelectric characteristics.

The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected to each other in series and a capacitance of each capacitor has a positive value, a total capacitance decreases as compared with a capacitance of each individual capacitor. On the other hand, when at least one of capacitances of two or more capacitors connected to each other in series has a negative value, a total capacitance may have a positive value and be greater than an absolute value of each individual capacitance.

When the ferroelectric material film having the negative capacitance and the paraelectric material film having the positive capacitance are connected to each other in series, a total capacitance value of the ferroelectric material film and the paraelectric material film connected to each other in series may increase. A transistor including the ferroelectric material film may have a subthreshold swing (SS) less than <NUM> mV/decade at room temperature using the increase in the total capacitance value.

The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). A type of dopant included in the ferroelectric material film may change depending on a type of ferroelectric material included in the ferroelectric material film.

When the ferroelectric material film includes the hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

When the dopant is aluminum (Al), the ferroelectric material film may include <NUM> to <NUM> atomic % (at%) of aluminum. Here, a ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material film may include <NUM> to <NUM> at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film may include <NUM> to <NUM> at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include <NUM> to <NUM> at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include <NUM> to <NUM> at% of zirconium.

The paraelectric material film may have the paraelectric characteristics. The paraelectric material film may include, for example, at least one of silicon oxide and metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have the ferroelectric characteristics, but the paraelectric material film may not have the ferroelectric characteristics. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, a crystal structure of the hafnium oxide included in the ferroelectric material film is different from a crystal structure of the hafnium oxide included in the paraelectric material film.

The ferroelectric material film may have a thickness sufficient to exhibit ferroelectric characteristics. The thickness of the ferroelectric material film may be, for example, <NUM> to <NUM>, but is not limited thereto. Since a critical thickness representing the ferroelectric characteristics may change for each ferroelectric material, the thickness of the ferroelectric material film may change depending on a ferroelectric material.

As an example, the gate insulating film <NUM> may include one ferroelectric material film. As another example, the gate insulating film <NUM> may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film <NUM> may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

A plurality of gate capping films <NUM> may be disposed on the upper surfaces of the plurality of gate electrodes <NUM> and upper surfaces of the plurality of gate spacers <NUM>, respectively. The plurality of gate capping films <NUM> may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO<NUM>), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

The first source/drain patterns <NUM> may be disposed on the substrate <NUM>. The first source/drain patterns <NUM> may be formed on the first active patterns AP1. The first source/drain patterns <NUM> are connected to the first active patterns AP1. Bottom surfaces of the first source/drain patterns <NUM> are in contact with the first active patterns AP1.

The first source/drain patterns <NUM> may be disposed on side surfaces of each of the plurality of gate electrodes <NUM>. The first source/drain patterns <NUM> may be disposed between the plurality of gate electrodes <NUM>.

For example, the first source/drain patterns <NUM> may be disposed on both sides of the plurality of gate electrodes <NUM>. Although not illustrated, the first source/drain patterns <NUM> may be disposed on one sides of the plurality of gate electrodes <NUM> and may not be disposed on the other sides of the plurality of gate electrodes <NUM>.

The first source/drain pattern <NUM> may include an epitaxial pattern. The first source/drain pattern <NUM> may include a semiconductor material. The first source/drain pattern <NUM> may be included in a source/drain of the transistor using the first active pattern AP1 as the channel region.

The first source/drain pattern <NUM> may be connected to the channel region used as a channel in the first active pattern AP1. It has been illustrated that three epitaxial patterns formed on each of the first active patterns AP1 are merged with each other as the first source/drain patterns <NUM>, but this is only for convenience of explanation, but the present disclosure is not limited thereto. That is, the epitaxial patterns formed on each of the first active patterns AP1 may be separated from each other.

As an example, an air gap may be disposed in a space between the first source/drain patterns <NUM> merged with the field insulating film <NUM>. As another example, an insulating material may be filled in a space between the first source/drain patterns <NUM> merged with the field insulating film <NUM>.

The second source/drain patterns <NUM> may be disposed on the substrate <NUM>. The second source/drain patterns <NUM> may be formed on the second active patterns AP2. The second source/drain patterns <NUM> are connected to the second active patterns AP2. Bottom surfaces of the second source/drain patterns <NUM> are in contact with the second active patterns AP2.

The second source/drain patterns <NUM> may be disposed on side surfaces of each of the plurality of gate electrodes <NUM>. The second source/drain patterns <NUM> may be disposed between the plurality of gate electrodes <NUM>.

For example, the second source/drain patterns <NUM> may be disposed on both sides of the plurality of gate electrodes <NUM>. Although not illustrated, the second source/drain patterns <NUM> may be disposed on one side of the plurality of gate electrodes <NUM> and may not be disposed on the other sides of the plurality of gate electrodes <NUM>.

The second source/drain pattern <NUM> may include an epitaxial pattern. The second source/drain pattern <NUM> may include a semiconductor material. The second source/drain pattern <NUM> may be included in a source/drain of a transistor using the second active pattern AP2 as a channel region.

The second source/drain pattern <NUM> may be connected to the channel region used as a channel in the second active pattern AP2. Three epitaxial patterns formed on each of the second active patterns AP2 are merged with each other as the second source/drain patterns <NUM> has been illustrated, but this is only for convenience of explanation, and the present disclosure is not limited thereto. That is, the epitaxial patterns formed on each of the second active patterns AP2 may be separated from each other.

As an example, an air gap may be disposed in a space between the second source/drain patterns <NUM> merged with the field insulating film <NUM>. As another example, an insulating material may be filled in a space between the second source/drain patterns <NUM> merged with the field insulating film <NUM>.

An etch stop film <NUM> may extend along an upper surface of the field insulating film <NUM>, sidewalls of the plurality of gate spacers <NUM>, and profiles of the first source/drain pattern <NUM> and the second source/drain pattern <NUM>. The etch stop film <NUM> may be disposed on an upper surface of the first source/drain pattern <NUM>, sidewalls of the first source/drain pattern <NUM>, an upper surface of the second source/drain pattern <NUM>, sidewalls of the second source/drain pattern <NUM>, and the sidewalls of the plurality of gate spacers <NUM>. In some implementations, the etch stop film <NUM> is not disposed on sidewalls of the gate capping film <NUM>. That is, the gate capping film <NUM> may be disposed on an upper surface of the etch stop film <NUM>. In addition, sidewalls of the etch stop film <NUM> may be connected to outer sidewalls of the gate capping film <NUM>. Although not illustrated, the etch stop film <NUM> may also be disposed on the sidewalls of the gate capping film <NUM>.

The etch stop film <NUM> may include a material having an etch selectivity with respect to a first interlayer insulating film <NUM> to be described later. The etch stop film <NUM> may include a nitride-based insulating material. For example, the etch stop film <NUM> may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboronitride (SiOBN), and combinations thereof.

The first interlayer insulating film <NUM> is disposed on the etch stop film <NUM>. The first interlayer insulating film <NUM> may be formed on the field insulating film <NUM>. The first interlayer insulating film <NUM> may be disposed on the first source/drain pattern <NUM> and the second source/drain pattern <NUM>. The first interlayer insulating film <NUM> may not cover an upper surface of the gate capping film <NUM>. For example, an upper surface of the first interlayer insulating film <NUM> may be coplanar with the upper surface of the gate capping film <NUM>.

The first interlayer insulating film <NUM> may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material may include, for example, fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonen silazen (TOSZ), fluoride silicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon doped silicon oxide (CDO), organo silicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogels, silica xerogels, mesoporous silica, or combinations thereof, but is not limited thereto.

The first source/drain contact <NUM> may be disposed on the first source/drain pattern <NUM> on the first active pattern AP1. The second source/drain contact <NUM> may be disposed on the second source/drain pattern <NUM> on the second active pattern AP2. The first source/drain contact <NUM> may be connected to the first source/drain pattern <NUM>. The second source/drain contact <NUM> may be connected to the second source/drain pattern <NUM>.

The gate contacts <NUM> may be connected to some of the plurality of gate electrodes <NUM>. The gate contacts <NUM> may be disposed at positions overlapping the plurality of gate electrodes <NUM>.

The first source/drain contact <NUM> may penetrate through the etch stop film <NUM> and be connected to the first source/drain pattern <NUM>. The first source/drain contact <NUM> may be disposed on the first source/drain pattern <NUM>.

The first source/drain contact <NUM> may be disposed within the first interlayer insulating film <NUM>. The first source/drain contact <NUM> may be surrounded by the first interlayer insulating film <NUM>.

A first contact silicide film <NUM> may be disposed between the first source/drain contact <NUM> and the first source/drain pattern <NUM>. The first contact silicide film <NUM> being formed along a profile of an interface between the first source/drain pattern <NUM> and the first source/drain contact <NUM> has been illustrated, but the present disclosure is not limited thereto. The first contact silicide film <NUM> may include, for example, a metal silicide material.

The first interlayer insulating film <NUM> does not cover an upper surface of the first source/drain contact <NUM>. As an example, the upper surface of the first source/drain contact <NUM> may not protrude above the upper surface of the gate capping film <NUM>. The upper surface of the first source/drain contact <NUM> may be coplanar with the upper surface of the gate capping film <NUM>. Although not illustrated, as another example, the upper surface of the first source/drain contact <NUM> may protrude above the upper surface of the gate capping film <NUM>.

In addition, the upper surface of the first source/drain contact <NUM> may be coplanar with an upper surface of the gate contact <NUM>. The upper surface of the first source/drain contact <NUM> may be coplanar with an upper surface of the power rail via PVA.

In some implementations, the first source/drain contact <NUM> may include a first source/drain barrier film 170a and a first source/drain filling film 170b disposed on the first source/drain barrier film 170a.

A bottom surface of the first source/drain contact <NUM> having a flat shape has been illustrated, but the present disclosure is not limited thereto. Although not illustrated, the bottom surface of the first source/drain contact <NUM> may have a wavy shape.

The first source/drain barrier film 170a may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material. In the semiconductor device, the 2D material may be a metallic material and/or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound, for example, at least one of graphene, molybdenum disulfide (MoS<NUM>), molybdenum diselenide (MoSe<NUM>), tungsten diselenide (WSe<NUM>), and tungsten disulfide (WS<NUM>), but is not limited thereto. That is, the above-described 2D materials have been enumerated only as an example, and thus, the 2D material that may be included in the semiconductor device according to the present disclosure is not limited by the above-described materials.

The first source/drain filling film 170b may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), copper (Cu), and molybdenum (Mo).

The first source/drain contact <NUM> including a plurality of conductive films has been illustrated, but the present disclosure is not limited thereto. Although not illustrated, the first source/drain contact <NUM> may be a single film.

The second source/drain contact <NUM> may penetrate through the etch stop film <NUM> and be connected to the second source/drain pattern <NUM>. The second source/drain contact <NUM> may be disposed on the second source/drain pattern <NUM>.

The second source/drain contact <NUM> may be disposed within the first interlayer insulating film <NUM>. The second source/drain contact <NUM> may be surrounded by the first interlayer insulating film <NUM>.

A second contact silicide film <NUM> may be disposed between the second source/drain contact <NUM> and the second source/drain pattern <NUM>. It has been illustrated that the second contact silicide film <NUM> is formed along a profile of an interface between the second source/drain pattern <NUM> and the second source/drain contact <NUM>, but the present disclosure is not limited thereto. The second contact silicide film <NUM> may include, for example, a metal silicide material.

The first interlayer insulating film <NUM> does not cover an upper surface of the second source/drain contact <NUM>. As an example, the upper surface of the second source/drain contact <NUM> may not protrude above the upper surface of the gate capping film <NUM>. The upper surface of the second source/drain contact <NUM> may be coplanar with the upper surface of the gate capping film <NUM>. Although not illustrated, as another example, the upper surface of the second source/drain contact <NUM> may protrude above the upper surface of the gate capping film <NUM>.

In addition, the upper surface of the second source/drain contact <NUM> may be coplanar with the upper surface of the gate contact <NUM>. The upper surface of the second source/drain contact <NUM> may be coplanar with the upper surface of the power rail via PVA.

In some implementations, the second source/drain contact <NUM> may include a second source/drain barrier film 270a and a second source/drain filling film 270b disposed on the second source/drain barrier film 270a.

A bottom surface of the second source/drain contact <NUM> having a flat shape has been illustrated, but the present disclosure is not limited thereto. Although not illustrated, the bottom surface of the second source/drain contact <NUM> may have a wavy shape.

A material included in the second source/drain barrier film 270a may be the same as the material included in the first source/drain barrier film 170a. A material included in the second source/drain filling film 270b may be the same as the material included in the first source/drain filling film 170b.

The second source/drain contact <NUM> including a plurality of conductive films has been illustrated, but the present disclosure is not limited thereto. Although not illustrated, the second source/drain contact <NUM> may be a single film.

The gate contact <NUM> may be disposed on the gate electrode <NUM>. The gate contact <NUM> may penetrate through the gate capping film <NUM> and be connected to the gate electrode <NUM>.

As an example, the upper surface of the gate contact <NUM> may be coplanar with the upper surface of the gate capping film <NUM>. Although not illustrated, as another example, the upper surface of the gate contact <NUM> may protrude above the upper surface of the gate capping film <NUM>.

The gate contact <NUM> may include a gate barrier film 180a and a gate filling film 180b disposed on the gate barrier film 180a. Descriptions of materials included in the gate barrier film 180a and the gate filling film 180b may be the same as those of the materials included in the first source/drain barrier film 170a and the first source/drain filling film 170b, respectively.

The gate contact <NUM> including a plurality of conductive films has been illustrated, but the present disclosure is not limited thereto. Although not illustrated, the gate contact <NUM> may be a single film.

The semiconductor device may further include a lower insulating film <NUM>. The lower insulating film <NUM> may be disposed on the second surface 100BS of the substrate <NUM>. The lower insulating film <NUM> may be in contact with the second surface 100BS of the substrate <NUM>.

The lower insulating film <NUM> may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material may include, for example, fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonen silazen (TOSZ), fluoride silicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon doped silicon oxide (CDO), organo silicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogels, silica xerogels, mesoporous silica, or combinations thereof, but is not limited thereto.

The power rail PR may be disposed between the first active pattern AP1 and the second active pattern AP2. The power rail PR may be disposed within the lower insulating film <NUM>. The lower insulating film <NUM> may surround the power rail PR. The power rail PR may extend to be elongated in the second direction D2, but is not limited thereto.

The power rail PR is disposed on the second surface 100BS of the substrate <NUM>. The power rail PR is disposed within the lower insulating film <NUM>. The power rail PR may be in contact with a bottom surface of the buried conductive pattern <NUM>. The power rail PR may be electrically connected to the buried conductive pattern <NUM>.

In some implementations, the power rail PR may be connected to the first source/drain pattern <NUM>. For example, the power rail PR may be connected to the first source/drain pattern <NUM> through the buried conductive pattern <NUM>, the power rail via PVA, a first via plug <NUM>, and the first source/drain contact <NUM>. A voltage may be applied to the first source/drain pattern <NUM> through the power rail PR.

In some implementations, the power rail PR may include a power rail barrier film PR_a and a power rail filling film PR_b disposed on the power rail barrier film PR_a. Descriptions of materials included in the power rail barrier film PR_a and the power rail filling film PR_b may be the same as those of the materials included in the first source/drain barrier film 170a and the first source/drain filling film 170b, respectively. It has been illustrated that the power rail PR includes a plurality of conductive films, but the present disclosure is not limited thereto. Although not illustrated, the power rail PR may be a single film.

In some implementations, the buried conductive pattern <NUM> may be disposed within the substrate <NUM>. The buried conductive pattern <NUM> may be disposed on the power rail PR. The buried conductive pattern <NUM> may be interposed between the power rail PR and the power rail via PVA. The buried conductive pattern <NUM> may be connected to the power rail PR and the power rail via PVA.

In some implementations, the bottom surface of the buried conductive pattern <NUM> may be coplanar with the second surface 100BS of the substrate <NUM>. The bottom surface of the buried conductive pattern <NUM> may extend in parallel with the second surface 100BS of the substrate <NUM>.

In <FIG> and <FIG>, a width of the buried conductive pattern <NUM> in the third direction D3 may gradually decrease from the second surface 100BS of the substrate <NUM> toward the first surface <NUM> of the substrate <NUM>. In <FIG>, a width of the buried conductive pattern <NUM> in the second direction D2 may gradually decrease from the second surface 100BS of the substrate <NUM> toward the first surface <NUM> of the substrate <NUM>.

The buried conductive pattern <NUM> may include a buried conductive pattern barrier film 115a and a buried conductive pattern filling film 115b disposed on the buried conductive pattern barrier film 115a. Descriptions of materials included in the buried conductive pattern barrier film 115a and the buried conductive pattern filling film 115b may be the same as those of the materials included in the first source/drain barrier film 170a and the first source/drain filling film 170b, respectively. Although not illustrated, the buried conductive pattern <NUM> may be a single film.

The semiconductor device further includes a via trench PVA_T penetrating through the first interlayer insulating film <NUM> and the field insulating film <NUM>.

The via trench PVA_T may be defined by via insulating liners <NUM> to be described later. The via trench PVA_T may expose the buried conductive pattern <NUM>. The via trench PVA_T may expose the upper surface of the buried conductive pattern <NUM>. The via trench PVA_T may be disposed on the buried conductive pattern <NUM>. The via trench PVA_T may be disposed between the plurality of gate electrodes <NUM>. The via trench PVA_T may be disposed between the first active pattern AP1 and the second active pattern AP2. The via trench PVA_T may be disposed between the first source/drain pattern <NUM> and the second source/drain pattern <NUM>. The via trench PVA_T may be disposed between the first source/drain contact <NUM> and the second source/drain contact <NUM>. The via trench PVA_T may penetrate through the first interlayer insulating film <NUM>, the etch stop film <NUM>, and penetrates through the field insulating film <NUM>.

A via insulating liner <NUM> is disposed on outer sidewalls of the via trench PVA_T. The via insulating liner <NUM> extends along sidewalls of a power rail via PVA to be described later. The via insulating liner <NUM> may be interposed between the power rail via PVA and the first source/drain pattern <NUM>. The via insulating liner <NUM> may be interposed between the power rail via PVA and the first source/drain contact <NUM>. The via insulating liner <NUM> may be interposed between the power rail via PVA and the second source/drain pattern <NUM>. The via insulating liner <NUM> may be interposed between the power rail via PVA and the second source/drain contact <NUM>. The via insulating liner <NUM> includes an insulating material. As an example, the via insulating liner <NUM> may be formed as a silicon oxide film, but the present disclosure is not limited thereto.

In some implementations, the via insulating liner <NUM> does not protrude above the upper surface of the first interlayer insulating film <NUM>. For example, the via insulating liner <NUM> may not protrude above the upper surface of the first source/drain contact <NUM> and the upper surface of the second source/drain contact <NUM>.

The power rail via PVA is disposed within the via trench PVA_T. The power rail via PVA may be interposed between the via insulating liners <NUM>. The power rail via PVA may be disposed on the power rail PR. The power rail via PVA may be disposed on the buried conductive pattern <NUM>. The power rail via PVA may be connected to the power rail PR through the buried conductive pattern <NUM>. The power rail via PVA may be disposed between the plurality of gate electrodes <NUM>. In addition, the power rail via PVA may be disposed between the first active pattern AP1 and the second active pattern AP2. The power rail via PVA may be disposed between the first source/drain pattern <NUM> and the second source/drain pattern <NUM>. The power rail via PVA may also be disposed between the first source/drain contact <NUM> and the second source/drain contact <NUM>.

The power rail via PVA may penetrate through the first interlayer insulating film <NUM>, the etch stop film <NUM>, and the field insulating film <NUM> and be connected to the buried conductive pattern <NUM>. A bottom surface of the power rail via PVA may be in contact with the upper surface of the buried conductive pattern <NUM>.

The first interlayer insulating film <NUM> may not cover the upper surface of the power rail via PVA. For example, the upper surface of the power rail via PVA and the upper surface of the first interlayer insulating film <NUM> may be coplanar with each other. In addition, the upper surface of the power rail via PVA may be coplanar with the upper surface of the first source/drain contact <NUM> and the upper surface of the second source/drain contact <NUM>. In addition, the upper surface of the power rail via PVA may be coplanar with the upper surface of the gate contact <NUM> and the upper surface of the gate capping film <NUM>.

The power rail via PVA includes a first sub-film PVA_1 and a second sub-film PVA_2. The first sub-film PVA_1 is disposed at a lower portion of the via trench PVA_T. The second sub-film PVA_2 is disposed at an upper portion of the via trench PVA_T. That is, the second sub-film PVA_2 is disposed on the first sub-film PVA_1. The first sub-film PVA_1 may be connected to the buried conductive pattern <NUM>, and the second sub-film PVA_2 may be connected to the first via plug <NUM>. Alternatively, the first sub-film PVA_1 may be connected to the buried conductive pattern <NUM>, and the second sub-film PVA_2 may be connected to the first source/drain contact <NUM>.

The first sub-film PVA_1 is formed as a single film, e.g., a single continuous film of a single material. The first sub-film PVA_1 may be interposed between the via insulating liners <NUM>. Sidewalls of the first sub-film PVA_1 may be in contact with the via insulating liners <NUM>. A bottom surface of the first sub-film PVA_1 may be in contact with the upper surface of the buried conductive pattern <NUM>. An upper surface of the first sub-film PVA_1 may be in contact with a bottom surface of the second sub-film PVA_2.

The second sub-film PVA_2 is formed as multiple films. The second sub-film PVA_2 includes a barrier film PVA_2a and a filling film PVA_2b.

The barrier film PVA_2a of the second sub-film PVA_2 may extend along inner sidewalls of the upper portion of the via trench PVA_T. The barrier films PVA_2a of the second sub-film PVA_2 are disposed on sidewalls of the via insulating liners <NUM>. The barrier films PVA_2a of the second sub-film PVA_2 does not extend along the upper surface of the first sub-film PVA_1. The barrier films PVA_2a of the second sub-film PVA_2 may be disposed only on the inner sidewalls of the upper portion of the via trench PVA_T.

The filling film PVA_2b of the second sub-film PVA_2 may be disposed on the barrier films PVA_2a of the second sub-film PVA_2. The filling film PVA_2b of the second sub-film PVA_2 may be disposed between the barrier films PVA_2a of the second sub-film PVA_2. A bottom surface of the filling film PVA_2b of the second sub-film PVA_2 may be in contact with the upper surface of the first sub-film PVA_1.

The power rail via PVA of the semiconductor device includes the first sub-film PVA_1 formed as the single film and the second sub-film PVA_2 formed as the multiple films. The first sub-film PVA_1 does not include a barrier film. Accordingly, resistance of the power rail via PVA may be decreased. Accordingly, performance and reliability of the semiconductor device including the power rail via PVA may be improved.

The first sub-film PVA_1 may include a conductive material. For example, the first sub-film PVA_1 may include at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), copper (Cu), and molybdenum (Mo).

The barrier film PVA_2a of the second sub-film PVA_2 may include a conductive material. The barrier film PVA_2a of the second sub-film PVA_2 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material.

The filling film PVA_2b of the second sub-film PVA_2 may include a conductive material. For example, the filling film PVA_2b of the second sub-film PVA_2 may include at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), copper (Cu), and molybdenum (Mo).

In some implementations, the first sub-film PVA_1 and the filling film PVA_2b of the second sub-film PVA_2 may be made of the same material. In this case, a boundary between the first sub-film PVA_1 and the filling film PVA_2b of the second sub-film PVA_2 may not be apparent. In some implementations, the first sub-film PVA_1 and the filling film PVA_2b of the second sub-film PVA_2 may be made of different materials. In this case, a boundary between the upper surface of the first sub-film PVA_1 and the bottom surface of the filling film PVA_2b of the second sub-film PVA_2 may be apparent.

In <FIG>, a height H1 from the second surface 100BS of the substrate <NUM> to the upper surface of the first sub-film PVA_1 is greater than a height H2 from the second surface 100BS of the substrate <NUM> to the upper surface of the field insulating film <NUM>. The height H1 from the second surface 100BS of the substrate <NUM> to the upper surface of the first sub-film PVA_1 is greater than a height from the second surface 100BS of the substrate <NUM> to the upper surface of the first source/drain pattern <NUM> and the upper surface of the second source/drain pattern <NUM>.

That is, the first sub-film PVA_1 overlaps the first active pattern AP1 and the second active pattern AP2 when viewed along the third direction D3. The first sub-film PVA_1 overlaps the first source/drain pattern <NUM> and the second source/drain pattern <NUM> when viewed along the third direction D3. However, at least a portion of the first sub-film PVA_1 does not overlap the first source/drain contact <NUM> and the second source/drain contact <NUM> when viewed along the third direction D3.

In addition, the barrier film PVA_2a of the second sub-film PVA_2 does not completely overlap the field insulating film <NUM> when viewed along the third direction D3. The barrier film PVA_2a of the second sub-film PVA_2 does not completely overlap the first active pattern AP1 and the second active pattern AP2 when viewed along the third direction D3. The barrier film PVA_2a of the second sub-film PVA_2 does not completely overlap the first source/drain pattern <NUM> and the second source/drain pattern <NUM> when viewed along the third direction D3. At least a portion of the barrier film PVA_2a of the second sub-film PVA_2 overlaps the first source/drain contact <NUM> and the second source/drain contact <NUM> when viewed along the third direction D3.

In addition, in <FIG>, the first sub-film PVA_1 overlaps the plurality of gate electrodes <NUM> when viewed along the second direction D2. A portion of the first sub-film PVA_1 does not overlap the plurality of gate electrodes <NUM> when viewed along the second direction D2. The first sub-film PVA_1 does not overlap the gate capping film <NUM> when viewed along the second direction D2. However, the present disclosure is not limited thereto. At least a portion of the first sub-film PVA_1 may overlap the gate capping film <NUM> when viewed along the second direction D2, and the first sub-film PVA_1 may completely overlap the plurality of gate electrodes <NUM> when viewed along the second direction D2.

An upper stop film <NUM> may be disposed on the first interlayer insulating film <NUM>, the gate capping film <NUM>, the first source/drain contact <NUM>, the second source/drain contact <NUM>, the power rail via PVA, and the gate contact <NUM>. A second interlayer insulating film <NUM> is disposed on the upper stop film <NUM>.

The upper stop film <NUM> may include a material having an etch selectivity with respect to the second interlayer insulating film <NUM>. The upper stop film <NUM> may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), and combinations thereof. The upper stop film <NUM> being a single film has been illustrated, but the present disclosure is not limited thereto. Although not illustrated, the upper stop film <NUM> may not be formed. The second interlayer insulating film <NUM> may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low-k material.

The first via plug <NUM> may be disposed within the second interlayer insulating film <NUM>. The first via plug <NUM> may penetrate through the upper stop film <NUM> and be directly connected to the first source/drain contact <NUM> and the power rail via PVA.

A portion of the first via plug <NUM> may completely cover the upper surface of the first source/drain contact <NUM> and the upper surface of the power rail via PVA. That is, the first source/drain contact <NUM> and the power rail via PVA may be connected to one first via plug <NUM>.

The first via plug <NUM> may include a first via barrier film 195a and a first via filling film 195b. The first via barrier film 195a may extend along sidewalls and a bottom surface of the first via filling film 195b. The first via barrier film 195a may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), nickel boron (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a 2D material. The first via filling film 195b may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), copper (Cu), and molybdenum (Mo).

A second via plug <NUM> may be disposed within the second interlayer insulating film <NUM>. The second via plug <NUM> may penetrate through the upper stop film <NUM> and be connected to the second source/drain contact <NUM>. A portion of the second via plug <NUM> may completely cover the upper surface of the second source/drain contact <NUM>.

The second via plug <NUM> may include a second via barrier film 295a and a second via filling film 295b. The second via barrier film 295a may extend along sidewalls and a bottom surface of the second via filling film 295b. A material included in the second via barrier film 295a may be the same as the material included in the first via barrier film 195a. A material included in the second via filling film 295b may be the same as the material included in the first via filling film 195b.

Hereinafter, more examples of semiconductor devices be described with reference to <FIG>. For convenience of explanation, mainly contents different from those described with reference to <FIG> will be described.

<FIG> are views for describing examples of semiconductor devices. For reference, <FIG>, <FIG>, <FIG>, and <FIG> are illustrative cross-sectional views taken along line A-A of <FIG>. <FIG> and <FIG> are illustrative cross-sectional views taken along line C-C of <FIG>.

Referring to <FIG>, the height H1 from the second surface 100BS of the substrate <NUM> to the upper surface of the first sub-film PVA_1 is greater than the height H2 from the second surface 100BS of the substrate <NUM> to the upper surface of the field insulating film <NUM>. On the other hand, the height H1 from the second surface 100BS of the substrate <NUM> to the upper surface of the first sub-film PVA_1 is smaller than a height from the second surface 100BS of the substrate <NUM> to the bottom surface of the first source/drain contact <NUM>. The height H1 from the second surface 100BS of the substrate <NUM> to the upper surface of the first sub-film PVA_1 is smaller than a height from the second surface 100BS of the substrate <NUM> to the bottom surface of the second source/drain contact <NUM>.

That is, the first sub-film PVA_1 may not completely overlap the first source/drain contact <NUM> and the second source/drain contact <NUM> when viewed along the third direction D3. At least a portion of the first sub-film PVA_1 may not overlap the first source/drain pattern <NUM> and the second source/drain pattern <NUM> when viewed along the third direction D3.

At least a portion of the barrier film PVA_2a of the second sub-film PVA_2 may overlap the first source/drain pattern <NUM> and the second source/drain pattern <NUM> when viewed along the third direction D3. Another portion of the barrier film PVA_2a of the second sub-film PVA_2 does not overlap the first source/drain pattern <NUM> and the second source/drain pattern <NUM> when viewed along the third direction D3.

Referring to <FIG> and <FIG>, the height H1 from the second surface 100BS of the substrate <NUM> to the upper surface of the first sub-film PVA_1 is smaller than the height H2 from the second surface 100BS of the substrate <NUM> to the upper surface of the field insulating film <NUM>.

The first sub-film PVA_1 does not penetrate through the field insulating film <NUM>. At least a portion of the first sub-film PVA_1 does not overlap the field insulating film <NUM> when viewed along the third direction D3 and/or the second direction D2. At least a portion of the first sub-film PVA_1 does not overlap the first active pattern AP1 and the second active pattern AP2 when viewed along the third direction D3. The first sub-film PVA_1 does not completely overlap the plurality of gate electrodes <NUM> when viewed along the second direction D2.

The barrier film PVA_2a of the second sub-film PVA_2 completely overlaps the first source/drain contact <NUM> and the second source/drain contact <NUM> when viewed along the third direction D3. At least a portion of the barrier film PVA_2a of the second sub-film PVA_2 is disposed within the field insulating film <NUM>. At least a portion of the barrier film PVA_2a of the second sub-film PVA_2 overlaps the first active pattern AP1 and the second active patterns AP2 when viewed along the third direction D3. At least a portion of the barrier film PVA_2a of the second sub-film PVA_2 does not overlap the plurality of gate electrodes <NUM> when viewed along the second direction D2.

Referring to <FIG> and <FIG>, the barrier film PVA_2a of the second sub-film PVA_2 may include a portion extending along the upper surface of the first sub-film PVA_1.

For example, the barrier film PVA_2a of the second sub-film PVA_2 may be disposed in a 'U' shape within the upper portion of the via trench PVA_T. The barrier film PVA_2a of the second sub-film PVA_2 is disposed along the sidewalls of the via insulating liners <NUM> and the upper surface of the first sub-film PVA_1.

The filling film PVA_2b of the second sub-film PVA_2 may not be in contact with the first sub-film PVA_1. The barrier film PVA_2a of the second sub-film PVA_2 may be disposed between the filling film PVA_2b of the second sub-film PVA_2 and the first sub-film PVA_1. That is, the upper surface of the first sub-film PVA_1 may be in contact with the barrier film PVA_2a of the second sub-film PVA_2.

Referring to <FIG>, the first source/drain contact <NUM> may extend to be elongated in the third direction D3. The first source/drain contact <NUM> may overlap at least a portion of the buried conductive pattern <NUM> when viewed along the first direction D1. The first source/drain contact <NUM> may overlap the power rail via PVA when viewed along the first direction D1.

In some implementations, an upper surface of the via trench PVA_T may expose the bottom surface of the first source/drain contact <NUM>. The via trench PVA_T does not extend up to the upper surface of the first interlayer insulating film <NUM>. The via trench PVA_T may extend from the first surface <NUM> of the substrate <NUM> to the bottom surface of the first source/drain contact <NUM>. The bottom surface of the first source/drain contact <NUM> may be in contact with the upper surface of the power rail via PVA. The bottom surface of the first source/drain contact <NUM> may be in contact with the second sub-film PVA_2 of the power rail via PVA.

In <FIG>, the height H1 from the second surface 100BS of the substrate <NUM> to the upper surface of the first sub-film PVA_1 is greater than the height H2 from the second surface 100BS of the substrate <NUM> to the upper surface of the field insulating film <NUM>. However, the first sub-film PVA_1 does not overlap the first source/drain contact <NUM> and the second source/drain contact <NUM> when viewed along the third direction D3.

Referring to <FIG>, the height H1 from the second surface 100BS of the substrate <NUM> to the upper surface of the first sub-film PVA_1 is smaller than the height H2 from the second surface 100BS of the substrate <NUM> to the upper surface of the field insulating film <NUM>. The first sub-film PVA_1 does not overlap the first source/drain pattern <NUM> and the second source/drain pattern <NUM> when viewed along the third direction D3.

Referring to <FIG>, a portion of the first source/drain contact <NUM> may be disposed within the via trench PVA_T. A portion of the first source/drain contact <NUM> may overlap the power rail via PVA when viewed along the first direction D1.

<FIG> are views for describing examples of a semiconductor device.

<FIG> is an example of a layout diagram for describing a semiconductor device. <FIG> is a cross-sectional view taken along line D-D of <FIG>. <FIG> are cross-sectional views taken along line E-E of <FIG>. For convenience, mainly contents different from those described with reference to <FIG> will be described.

Referring to <FIG>, in a semiconductor device, the first active pattern AP1 may include a first lower pattern BP1 and one or more first sheet patterns SP1. Although not illustrated, the second active pattern AP2 may include a second lower pattern BP2 and one or more second sheet patterns. Hereinafter, a description of the second lower pattern BP2 may be the same as that of the first lower pattern BP1, and will thus be omitted. In addition, a description of the second sheet pattern may be the same as that of the first sheet pattern SP1, and will thus be omitted.

Each of the first lower pattern BP1 and the second lower pattern BP2 may extend along the second direction D2. The first sheet patterns SP1 may be disposed on the first lower pattern BP1 so as to be spaced apart from the first lower pattern BP1.

The number of first sheet patterns SP1 may be one or more. For example, the first sheet patterns SP1 may be a plurality of sheet patterns stacked in the first direction D1. The number of first sheet patterns SP1 is three in <FIG>, but the present disclosure is not limited thereto. An upper surface of the first sheet pattern SP1 disposed at the uppermost portion among the first sheet patterns SP1 may be an upper surface of the first active pattern AP1.

The first sheet pattern SP1 may be connected to the first source/drain pattern <NUM>. The first sheet pattern SP1 may be a channel pattern used as a channel region of a transistor. For example, the first sheet pattern SP1 may be a nanosheet or a nanowire.

The first lower pattern BP1 may include, for example, silicon or germanium, which is an elemental semiconductor material. Alternatively, the first lower pattern BP1 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The first sheet pattern SP1 may include, for example, silicon or germanium, which is an elemental semiconductor material. Alternatively, the first sheet pattern SP1 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The first source/drain pattern <NUM> may be disposed on the first lower pattern BP1. The first source/drain patterns <NUM> may be disposed between the plurality of gate electrodes <NUM>. The first source/drain pattern <NUM> may be connected to the first sheet pattern SP1.

The second source/drain pattern <NUM> may be disposed on the second lower pattern BP2. The second source/drain patterns <NUM> may be disposed between the plurality of gate electrodes <NUM>. The second source/drain pattern <NUM> may be connected to the second sheet pattern.

The power rail via PVA may be disposed on one side of the first lower pattern BP1. The power rail via PVA is disposed on one side of the first source/drain pattern <NUM>. In addition, the power rail via PVA may be disposed between the plurality of gate electrodes <NUM>. The power rail via PVA may be disposed on one side of the second lower pattern BP2. The power rail via PVA is disposed on one side of the second source/drain pattern <NUM>.

Although not illustrated, the gate insulating film <NUM> may extend along an upper surface of the first lower pattern BP1 and the upper surface of the field insulating film <NUM>. The gate insulating film <NUM> may surround circumferences of the first sheet patterns SP1.

The gate electrode <NUM> is disposed on the first lower pattern BP1 and the second lower pattern BP2. The gate electrode <NUM> crosses the first lower pattern BP1 and the second lower pattern BP2. The gate electrode <NUM> may surround circumferences of the first sheet patterns SP1. The gate electrode <NUM> may surround circumferences of the second sheet patterns.

In <FIG>, the gate spacer <NUM> includes an outer spacer <NUM> and inner spacers <NUM>. The inner spacers <NUM> may be disposed between the first lower pattern BP1 and the first sheet pattern SP1 and between adjacent first sheet patterns SP1. Although not illustrated, the inner spacers <NUM> may be disposed between the second lower pattern BP2 and the second sheet pattern and between adjacent second sheet patterns.

In <FIG>, the gate spacer <NUM> includes only an outer spacer. The inner spacers are not disposed between the first lower pattern BP1 and the first sheet pattern SP1 and between adjacent first sheet patterns SP1. The inner spacers are not disposed between the second lower pattern BP2 and the second sheet pattern and between adjacent second sheet patterns.

In <FIG>, sidewalls of the first source/drain pattern <NUM> have a wavy shape. For example, the sidewalls of the first source/drain pattern <NUM> are concave toward the first sheet patterns SP1. The sidewalls of the first source/drain pattern <NUM> may be convex toward the gate electrode <NUM>. However, the the present disclosure is not limited thereto. The sidewalls of the first source/drain patterns <NUM> may also be convex toward the first sheet patterns SP1.

<FIG> are views for describing intermediate steps of a method of manufacturing a semiconductor device. For reference, <FIG> may be cross-sectional views taken along line A-A of <FIG>. Hereinafter, a method of manufacturing a semiconductor device will be described with reference to cross-sectional views.

Referring to <FIG>, the substrate <NUM> may be provided. The first active patterns AP1 and the second active patterns AP2 may be formed on the substrate <NUM>. Each of the first active patterns AP1 and the second active patterns AP2 may extend in the second direction D2. The first active patterns AP1 and the second active patterns AP2 may be spaced apart from each other in the third direction D3. Each of the first active patterns AP1 and the second active patterns AP2 may protrude from the substrate <NUM> in the first direction D1.

The field insulating film <NUM> may be formed on the substrate <NUM>. The field insulating film <NUM> may cover the sidewalls of the first active patterns AP1 and the sidewalls of the second active patterns AP2. The upper surface of the field insulating film <NUM> may be coplanar with the upper surface of the first active pattern AP1 and an upper surface of the second active pattern AP2.

Subsequently, the first source/drain pattern <NUM> may be formed on the first active patterns AP1. The second source/drain pattern <NUM> may be formed on the second active patterns AP2. The etch stop film <NUM> may be formed along the profile of the first source/drain pattern <NUM>, the profile of the second source/drain pattern <NUM>, and the upper surface of the field insulating film <NUM>. The first interlayer insulating film <NUM> may be formed on the etch stop film <NUM>.

Subsequently, the first source/drain contact <NUM> may be formed on the first source/drain pattern <NUM>. The first source/drain contact <NUM> may penetrate through the first interlayer insulating film <NUM> and be connected to the first source/drain pattern <NUM>. The first contact silicide film <NUM> may be formed at a boundary between the first source/drain contact <NUM> and the first source/drain pattern <NUM>. The second source/drain contact <NUM> may be formed on the second source/drain pattern <NUM>. The second source/drain contact <NUM> may penetrate through the first interlayer insulating film <NUM> and be connected to the second source/drain pattern <NUM>. The second contact silicide film <NUM> may be formed at a boundary between the second source/drain contact <NUM> and the second source/drain pattern <NUM>.

Referring to <FIG>, a preliminary trench TR is formed. The preliminary trench TR may penetrate through the first interlayer insulating film <NUM>, the etch stop film <NUM>, and the field insulating film <NUM>. The preliminary trench TR may expose the first surface <NUM> of the substrate <NUM>.

Referring to <FIG>, the via insulating liners <NUM> is formed on sidewalls of the preliminary trench TR. The via insulating liners <NUM> may define the via trench PVA_T. The via insulating liners <NUM> are not formed on the first surface <NUM> of the substrate <NUM>.

Referring to <FIG>, the first sub-film PVA_1 may be formed within the via trench PVA_T.

The first sub-film PVA_1 may be formed in a bottom up manner. The "bottom up" manner may refer to a method in which a film to be deposited is deposited in a certain direction. For example, the first sub-film PVA_1 may be deposited in the first direction D1 on the first surface <NUM> of the substrate <NUM>. In this case, the first sub-film PVA_1 may be formed as a single film.

Referring to <FIG>, the barrier films PVA_2a of the second sub-film PVA_2 are formed. The barrier films PVA_2a of the second sub-film PVA_2 may be formed on the via insulating liners <NUM>. The barrier films PVA_2a of the second sub-film PVA_2 may be disposed on the inner sidewalls of the via trench PVA_T. The barrier films PVA_2a of the second sub-film PVA_2 are not formed along the upper surface of the first sub-film PVA_1.

Referring to <FIG>, the second sub-film PVA_2 are formed by forming the filling film PVA_2b of the second sub-film PVA_2. The power rail via PVA may be formed by forming the second sub-film PVA_2.

The filling film PVA_2b of the second sub-film PVA_2 may be formed between the barrier films PVA_2a of the second sub-film PVA_2. The filling film PVA_2b of the second sub-film PVA_2 may be formed on the upper surface of the first sub-film PVA_1. The filling film PVA_2b of the second sub-film PVA_2 may be in contact with the upper surface of the first sub-film PVA <NUM>.

Referring to <FIG>, the upper stop film <NUM>, the second interlayer insulating film <NUM>, the first via plug <NUM>, and the second via plug <NUM> are formed on the first source/drain contact <NUM>, the power rail via PVA, the second source/drain contact <NUM>, and the first interlayer insulating film <NUM>. The first via plug <NUM> may be connected to the first source/drain contact <NUM> and the power rail via PVA. The second via plug <NUM> may be connected to the second source/drain contact <NUM>.

The reference frames in <FIG> are rotated by <NUM>° relative to the reference frame in <FIG>. Although not illustrated, a capping substrate may be formed on the second interlayer insulating film <NUM>, the second via plug <NUM>, and the first via plug <NUM>. The capping substrate may be a glass substrate or be a silicon substrate.

Subsequently, a buried trench exposing the power rail via PVA may be formed. The buried trench may be formed by etching the substrate <NUM>. The buried trench may expose the power rail via PVA. A width of the buried trench may be greater than a width of the power rail via PVA, but is not limited thereto.

Referring to <FIG>, the buried conductive pattern <NUM> is formed. First, the buried conductive pattern barrier film 115a may be formed along sidewalls and a bottom surface of the buried trench. The buried conductive pattern filling film 115b may be formed on the buried conductive pattern barrier film 115a.

Referring to <FIG>, the lower insulating film <NUM> may be formed on the second surface 100BS of the substrate <NUM>. The power rail PR may be formed within the lower insulating film <NUM>. The power rail PR may be connected to the buried conductive pattern <NUM>.

While this disclosure contains many specific implementation details, these should not be construed as limitations on the scope of what is claimed.

Claim 1:
A semiconductor device comprising:
a substrate (<NUM>) including a first surface (<NUM>) and a second surface (100BS) opposite to each other in a first direction (D1);
a first active pattern (AP1) disposed on the first surface (<NUM>) of the substrate (<NUM>) and extending in a second direction (D2) intersecting the first direction (D1);
a field insulating film (<NUM>) disposed on the first surface (<NUM>) of the substrate (<NUM>) and covering sidewalls of the first active pattern (AP1);
a power rail (PR) disposed on the second surface (100BS) of the substrate (<NUM>) and extending in the second direction (D2);
a via trench (PVA_T) disposed on one side of the first active pattern (AP1) and penetrating through the field insulating film (<NUM>);
a power rail via (PVA) filling the via trench (PVA_T) and connected to the power rail (PR); and
a via insulating liner (<NUM>) disposed between sidewalls of the via trench (PVA_T) and sidewalls of the power rail via (PVA),wherein the power rail via (PVA) includes:
a first sub-film (PVA_1) formed as a single film and filling
a lower portion of the via trench (PVA_T); and
a second sub-film (PVA_2) disposed at an upper portion of the via trench (PVA_T) on the first sub-film (PVA_1), wherein the second sub-film (PVA_2) includes a filling film (PVA_2b) and a barrier film (PVA_2a) disposed between sidewalls of the filling film (PVA_2b) and the via insulating liner (<NUM>), and
wherein
sidewalls of the first sub-film (PVA_1) are in contact with the via insulating liner (<NUM>).