Patent Description:
A transistor is a semiconductor device that performs an electrical switching function, and is used in various semiconductor products, such as memories and driving integrated circuits (ICs). When the size of semiconductor devices is reduced, more semiconductor devices may be integrated on one wafer and the driving speed of semiconductor devices is also increased. Therefore, studies have been actively conducted to reduce the size of semiconductor devices.

Recently, studies have been conducted to reduce the size of semiconductor devices by using two-dimensional materials. Two-dimensional materials have stable and excellent properties even at a small thickness of <NUM> or less. Therefore, two-dimensional materials attract attention as a material capable of overcoming the limitation of performance degradation due to a reduction in the size of semiconductor devices.

US Patent Application Number <CIT> describes an electronic device with a two-dimensional material layer.

<NPL>) describes the selective deopisiton of metal at graphene line defects.

<NPL>) describes the selective deposition of Ru onto defect sites in graphene sheets.

Patent Applications <CIT> and <CIT> disclose electronic devices provided with two-dimensional channel layers and metallic nanoparticles provided thereon.

Provided are a semiconductor device including a two-dimensional material and a method of fabricating the same.

According to an aspect of the present invention, there is provided a semiconductor device according to claim <NUM>.

In some embodiments, the two-dimensional semiconductor material may include a material having a bandgap of <NUM> eV or more and <NUM> eV or less.

In some embodiments, the two-dimensional semiconductor material may include a transition metal dichalcogenide (TMD).

In some embodiments, the TMD may include a metal element and a chalcogen element. The metal element may include one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re. The chalcogen element may include one of S, Se, and Te.

In some embodiments, the two-dimensional semiconductor material may include black phosphorus.

In some embodiments, the two-dimensional material layer may include one to ten layers.

In some embodiments, the two-dimensional material layer may include one to five layers.

In some embodiments, when the metallic nanoparticles are on the second region of the two-dimensional material layer at a higher density than a density of the metallic nanoparticles on the first region of the two-dimensional material layer, the metallic nanoparticles may be only on the second region of the two-dimensional material layer.

In some embodiments, the metallic nanoparticles may include Ru, RuO, Mo, W, Co, TiN, Ti, or Al.

In some embodiments, the metallic nanoparticles may include a material having a work function greater than a work function of the two-dimensional semiconductor material.

In some embodiments, the metallic nanoparticles may include a material having a work function less than a work function of the two-dimensional semiconductor material.

In some embodiments, an electronic device may include the semiconductor device.

According to another aspect of the present invention, there is provided a method for fabricating a semiconductor device according to claim <NUM>.

For example, "at least one of A, B, and C," and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.

When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical value. Moreover, when the words "generally" and "substantially" are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as "about" or "substantially," it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±<NUM>%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as increments of <NUM>%.

In the following drawings, the same reference numerals denote the same elements, and the size of each element in the drawings may be exaggerated for clarity and convenience of explanation. Embodiments described herein are merely examples, and various modifications may be made thereto from these embodiments.

Hereinafter, the terms "above" or "on" may include not only those that are directly above, below, left, or right in a contact manner, but also those that are above, below, left, or right in a non-contact manner. The singular forms "a," "an," and "the" as used herein are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be understood that the terms "comprise," "include," or "have" as used herein specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements.

The use of the term "the" and similar demonstratives may correspond to both the singular and the plural. Steps constituting methods may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context, and are not necessarily limited to the stated order.

Also, the terms such as ". er/or" and "module" described in the specification mean units that process at least one function or operation, and may be implemented as hardware, software, or a combination of hardware and software.

Connecting lines or connecting members illustrated in the drawings are intended to represent exemplary functional relationships and/or physical or logical connections between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device.

The use of all illustrations or illustrative terms in the embodiments is simply to describe the embodiment in detail, and the scope of the disclosure is not limited due to the illustrations or illustrative terms unless they are limited by claims.

<FIG> is a cross-sectional view of a semiconductor device <NUM> according to an embodiment which is not claimed but which is useful for understanding the invention. The semiconductor device <NUM> illustrated in <FIG> may be, for example, a field effect transistor (FET).

Referring to <FIG>, a channel layer <NUM> is provided on a substrate <NUM>. The substrate <NUM> may include various materials, such as a semiconductor material, an insulating material, or a metal material. When a two-dimensional material layer <NUM> to be described below is formed by depositing a two-dimensional semiconductor material on the substrate <NUM>, the substrate <NUM> may be a substrate for growth of the two-dimensional semiconductor material.

The channel layer <NUM> may include a two-dimensional material layer <NUM> provided on the substrate <NUM> and metallic nanoparticles <NUM> partially deposited on the two-dimensional material layer <NUM>.

The two-dimensional material layer <NUM> may include a two-dimensional semiconductor material having a polycrystalline structure. The two-dimensional semiconductor material refers to a two-dimensional material having a layered structure in which constituent atoms are two-dimensionally bonded. The two-dimensional semiconductor material may have excellent electrical properties and may maintain high mobility without significant change in properties thereof even when the thickness thereof is reduced to a nanoscale.

The two-dimensional semiconductor material may include a material having a bandgap of about <NUM> eV or more and about <NUM> eV or less. For example, the two-dimensional semiconductor material may include transition metal dichalcogenide (TMD) or black phosphorus. However, the disclosure is not limited thereto.

The TMD is a two-dimensional material having semiconductor properties and is a compound of a transition metal and a chalcogen element. The transition metal may include, for example, at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, and Re, and the chalcogen element may include, for example, at least one of S, Se, and Te. As a specific example, the TMD may include MoS<NUM>, MoSe<NUM>, MoTe<NUM>, WS<NUM>, WSe<NUM>, WTe<NUM>, ZrS<NUM>, ZrSe<NUM>, HfS<NUM>, HfSe<NUM>, NbSe<NUM>, ReSe<NUM>, and the like. However, the disclosure is not limited thereto. The black phosphorus is a semiconductor material having a structure in which phosphorus (P) atoms are two-dimensionally bonded.

The two-dimensional semiconductor material may be doped with a p-type dopant or an n-type dopant in order to control mobility. The two-dimensional material layer <NUM> may have a monolayer or multilayer structure, and each layer may have an atomic level thickness. The two-dimensional material layer <NUM> may include, for example, one to ten layers. As a specific example, the two-dimensional material layer <NUM> may include one to five layers. However, the disclosure is not limited thereto.

The two-dimensional material layer <NUM> may include a first region 110a and a second region 110b respectively on both sides of the first region 110a. The first region 110a may be located in the central portion of the two-dimensional material layer <NUM>. The first region 110a may be a channel region corresponding to a gate electrode <NUM> to be described below. The second regions 110b may be respectively located on both sides of the two-dimensional material layer <NUM>. The second regions 110b may be respectively a source region and a drain region provided to correspond to a source electrode <NUM> and a drain electrode <NUM> to be described below.

The metallic nanoparticles <NUM> are partially deposited on the upper surface of the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> may be deposited on at least one of defects and grain boundaries of a two-dimensional semiconductor material having a polycrystalline structure.

<FIG> is a plan view of the two-dimensional material layer <NUM> including a two-dimensional semiconductor material having a polycrystalline structure. Referring to <FIG>, defects <NUM> may be present inside crystal grains <NUM> in a two-dimensional semiconductor material having a polycrystalline structure, and grain boundaries <NUM> may be present between the crystal grains <NUM>.

<FIG> illustrates a state in which the metallic nanoparticles <NUM> are selectively deposited on the defects <NUM> and the grain boundaries <NUM> of the two-dimensional material layer <NUM> illustrated in <FIG>. As described below, when the metallic nanoparticles <NUM> are deposited on the two-dimensional material layer <NUM> by ALD or chemical vapor deposition (CVD), the metallic nanoparticles <NUM> may be selectively deposited only on the defects <NUM> and/or the grain boundaries <NUM> having dangling bonds.

The metallic nanoparticles <NUM> may include a material having excellent conductivity. The metallic nanoparticles <NUM> may include, for example, Ru, RuO, Mo, W, Co, TiN, Ti, or Al. However, the disclosure is not limited thereto.

The metallic nanoparticles <NUM> may include a material having a work function greater than a work function of the two-dimensional semiconductor material constituting the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> may include, for example, Ru, RuO, Mo, W, Co, or the like, but this is only an example. In this case, the two-dimensional material layer <NUM> may have a p-type channel polarity.

The metallic nanoparticles <NUM> may include a material having a work function less than a work function of the two-dimensional semiconductor material constituting the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> may include, for example, TiN, Ti, Al, or the like, but this is only an example. In this case, the two-dimensional material layer <NUM> may have an n-type channel polarity.

The metallic nanoparticles <NUM> may be deposited on the first and second regions 110a and 110b of the two-dimensional material layer <NUM> at a substantially uniform density. Specifically, the metallic nanoparticles <NUM> may be deposited on the surface of the first region 110a acting as the channel region and the surfaces of the second regions 110b acting as the source and drain regions at a uniform density as a whole. The surfaces of the second regions 110b may constitute a contact region between the source electrode <NUM> and the source region and a contact region between the drain electrode <NUM> and the drain region.

A gate insulating layer <NUM> and a gate electrode <NUM> are sequentially stacked on the first region 110a of the two-dimensional material layer <NUM> in this stated order. The gate insulating layer <NUM> may include, for example, silicon nitride, but is not limited thereto.

The gate electrode <NUM> may include a metal material or a conductive oxide. The metal material may include, for example, at least one selected from Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. The conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like. However, this is only an example.

The source electrode <NUM> and the drain electrode <NUM> are respectively provided on both sides of the gate electrode <NUM>. The source electrode <NUM> and the drain electrode <NUM> are respectively provided on the second regions 110b of the two-dimensional material layer <NUM>, that is, the source region and the drain region. The source electrode <NUM> may be provided in contact with the source region of the two-dimensional material layer <NUM>, and the drain electrode <NUM> may be provided in contact with the drain region of the two-dimensional material layer <NUM>. The source electrode <NUM> and the drain electrode <NUM> may include, for example, a metal material having excellent electrical conductivity, such as Ag, Au, Pt, or Cu, but is not limited thereto.

In a conventional silicon (Si)-based semiconductor device, as a channel thickness decreases, mobility decreases and a threshold voltage distribution increases, and as a channel length decreases, performance degradation due to a short channel effect becomes severe. Accordingly, there is a limitation in reducing a size of a semiconductor device.

Because the semiconductor device <NUM> uses the two-dimensional semiconductor material as the channel, the semiconductor device <NUM> may have excellent performance even with a small thickness of <NUM> or less. In addition, a short channel effect may be reduced. Accordingly, the limitation of performance degradation due to the reduction in the size of the semiconductor device <NUM> may be overcome.

When the two-dimensional material layer includes a two-dimensional semiconductor material having a polycrystalline structure, defects may be formed inside grains and grain boundaries may be formed between the grains. Accordingly, when the two-dimensional semiconductor material having the polycrystalline structure is used as a channel material, defects or grain boundaries formed in the two-dimensional semiconductor material interfere with the movement of charges, thus causing a degradation in characteristics of the semiconductor device. For example, the semiconductor device may be degraded because a contact resistance increases in the source and drain regions of the two-dimensional material layer and on-current decreases in the channel region of the two-dimensional material layer due to an increase in channel resistance.

In the semiconductor device <NUM>, because the metallic nanoparticles <NUM> are selectively deposited on the two-dimensional material layer <NUM> constituting the channel layer, charges may move through the metallic nanoparticles <NUM>, and thus, electrical conductivity of the two-dimensional material layer <NUM> may be improved. Accordingly, a contact resistance may increase in the source and drain regions of the two-dimensional material layer <NUM>, and on-current may be improved due to a decrease in channel resistance in the channel region of the two-dimensional material layer <NUM>. In addition, the doping degree of the two-dimensional material layer <NUM> may be controlled by adjusting the material type and/or the deposition amount of the metallic nanoparticles <NUM> selectively deposited on the two-dimensional material layer <NUM>. Accordingly, the channel polarity, threshold voltage, on-current, off-current, and the like of the semiconductor device <NUM> may be controlled.

<FIG> are scanning electron microscope (SEM) images of MoS<NUM> thin-films when Ru nanoparticles are deposited on the MoS<NUM> thin-films by ALD according to cycles, respectively.

<FIG> illustrates a polycrystalline MoS<NUM> thin-film on which Ru nanoparticles are not deposited, and <FIG> and <FIG> illustrate a state when Ru nanoparticles are deposited on polycrystalline MoS<NUM> thin-films by ALD at <NUM> cycles and <NUM> cycles, respectively. Referring to <FIG>, it may be confirmed that the amount of Ru nanoparticles selectively deposited on defects and grain boundaries of the polycrystalline MoS<NUM> thin-film increases as the deposition cycle increases.

<FIG> is a transmission electron microscope (TEM) image of a cross-section of a MoS<NUM> thin-film when Ru nanoparticles are deposited on the MoS<NUM> thin-film by ALD at <NUM> cycles. Referring to <FIG>, it may be confirmed that Ru nanoparticles are selectively deposited on defects and grain boundaries of the polycrystalline MoS<NUM> thin-film.

Hereinafter, a method of fabricating the semiconductor device <NUM> according to the above-described, not claimed embodiment is described. <FIG> are diagrams for describing a method of fabricating a semiconductor device, according to an embodiment which is not claimed but which is useful for understanding the invention.

Referring to <FIG>, a two-dimensional material layer <NUM> is formed on a substrate <NUM>. The two-dimensional material layer <NUM> includes a two-dimensional semiconductor material having a polycrystalline structure. The substrate <NUM> may include various materials, such as a semiconductor material, an insulating material, or a metal material. The two-dimensional material layer <NUM> may be formed by depositing and growing a two-dimensional semiconductor material on the surface of the substrate <NUM>. The depositing of the two-dimensional semiconductor material <NUM> may be performed by, for example, CVD, physical vapor deposition (PVD), or the like, but this is only an example.

The two-dimensional semiconductor material may include a material having a bandgap of about <NUM> eV or more and about <NUM> eV or less. For example, the two-dimensional semiconductor material may include TMD or black phosphorus. However, the disclosure is not limited thereto.

The TMD is a two-dimensional material having semiconductor properties and is a compound of a transition metal and a chalcogen element. The transition metal may include, for example, at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, and Re, and the chalcogen element may include, for example, at least one of S, Se, and Te. As a specific example, the TMD may include MoS<NUM>, MoSe<NUM>, MoTe<NUM>, WS<NUM>, WSe<NUM>, WTe<NUM>, ZrS<NUM>, ZrSe<NUM>, HfS<NUM>, HfSe<NUM>, NbSe<NUM>, ReSe<NUM>, and the like. However, the disclosure is not limited thereto. The black phosphorus is a semiconductor material having a structure in which phosphorus (P) atoms are two-dimensionally bonded. The two-dimensional semiconductor material may be doped with a p-type dopant or an n-type dopant in order to control mobility.

The two-dimensional material layer <NUM> may have a monolayer or multilayer structure, and each layer may have an atomic level thickness. The two-dimensional material layer <NUM> may include, for example, one to ten layers. As a specific example, the two-dimensional material layer <NUM> may include one to five layers. However, the disclosure is not limited thereto.

The two-dimensional material layer <NUM>, which is deposited and grown on the substrate <NUM>, may have a polycrystalline structure. In the two-dimensional material layer <NUM> having the polycrystalline structure, defects may be present inside the grains and grain boundaries may be present between the grains. The presence of the defects and the grain boundaries may interfere with the movement of charges.

Referring to <FIG>, metallic nanoparticles <NUM> are selectively deposited on a certain portion of the two-dimensional material layer <NUM>. Accordingly, a channel layer <NUM> including the two-dimensional material layer <NUM> and the metallic nanoparticles <NUM> is formed on the substrate <NUM>. The depositing of the metallic nanoparticles <NUM> may be performed by, for example, ALD or CVD. In the depositing process, the metallic nanoparticles <NUM> may be selectively deposited only on the defects and/or the grain boundaries of the two-dimensional material layer <NUM>. Specifically, the defects and the grain boundaries present in the two-dimensional material layer <NUM> having the polycrystalline structure have dangling bonds. In the depositing process, the metallic nanoparticles <NUM> may be selectively deposited only on the defects and the grain boundaries having dangling bonds. Accordingly, the movement of charges may be improved through the metallic nanoparticles <NUM>, and electrical conductivity of the two-dimensional material layer <NUM> may be improved.

The metallic nanoparticles <NUM> may include a material having a work function greater than a work function of the two-dimensional semiconductor material constituting the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> may include, for example, Ru, RuO, Mo, W, Co, or the like, but this is only an example. The metallic nanoparticles <NUM> may include a material having a work function less than a work function of the two-dimensional semiconductor material constituting the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> may include, for example, TiN, Ti, Al, or the like, but this is only an example.

The two-dimensional material layer <NUM> may include a first region 110a located in the central portion of the two-dimensional material layer and second regions 110b respectively on both sides of the first region 110a. The first region 110a may be a channel region, and the second regions 110b may be source and drain regions. The metallic nanoparticles <NUM> may be formed to have a substantially uniform density in the entire region of the two-dimensional material layer.

Referring to <FIG>, a gate insulating layer <NUM> is formed in the first region 110a of the two-dimensional material layer <NUM>. The gate insulating layer <NUM> may include, for example, silicon nitride, but is not limited thereto.

Referring to <FIG>, a gate electrode <NUM> is deposited on the gate insulating layer <NUM>, and a source electrode <NUM> and a drain electrode <NUM> are respectively deposited on the second regions 110b of the two-dimensional material layer <NUM>. The gate electrode <NUM> may be provided on the first region 110a of the two-dimensional material layer <NUM>. The source electrode <NUM> and the drain electrode <NUM> are respectively provided on the second regions 110b of the two-dimensional material layer <NUM>, that is, the source region and the drain region. The source electrode <NUM> may be provided in contact with the source region of the two-dimensional material layer <NUM>, and the drain electrode <NUM> may be provided in contact with the drain region of the two-dimensional material layer <NUM>.

A case where the metallic nanoparticles <NUM> are deposited on the entire first and second regions 110a and 110b of the two-dimensional material layer <NUM> at a substantially uniform density has been described above. However, this is only an example. For example, as described below, the metallic nanoparticles <NUM> may be deposited on the second region 110b at a higher density than on the first region 110a, or the metallic nanoparticles <NUM> may be deposited only on the second region 110b. In addition, first metallic nanoparticles may be deposited on the first region 110a and second metallic nanoparticles may be deposited on the second region 110b.

<FIG> is a cross-sectional view of a semiconductor device <NUM> according to an embodiment of the invention. Hereinafter, differences from the above-described non claimed embodiment are mainly described.

Referring to <FIG>, a channel layer <NUM> includes a two-dimensional material layer <NUM> provided on a substrate <NUM>, and metallic nanoparticles <NUM> selectively deposited on a certain portion of the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> are selectively deposited only on defects and/or grain boundaries of the two-dimensional material layer <NUM>. Because the two-dimensional material layer <NUM> and the metallic nanoparticles <NUM> have been described above, a detailed description thereof is omitted.

In the present embodiment, the metallic nanoparticles <NUM> are deposited on second regions (source and drain regions) 210b at a higher density than on a first region (a channel region) 210a of the two-dimensional material layer <NUM>. Specifically, the metallic nanoparticles <NUM> may be deposited at a relatively high density in contact regions of source and drain electrodes <NUM> and <NUM> and the source and drain regions 210b. In an ALD or CVD process, the metallic nanoparticles <NUM> with a controlled deposition amount may be deposited on desired regions of the two-dimensional material layer <NUM> by a photolithography process. Accordingly, the contact resistance between the source and drain electrodes <NUM> and <NUM> and the source and drain regions 210b may be further reduced, and off current in the channel region 210a may be prevented from increasing.

<FIG> is a cross-sectional view of a semiconductor device <NUM> according to another embodiment.

Referring to <FIG>, a channel layer <NUM> includes a two-dimensional material layer <NUM> provided on a substrate <NUM>, and metallic nanoparticles <NUM> selectively deposited on a certain portion of the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> are selectively deposited only on defects and/or grain boundaries of the two-dimensional material layer <NUM>.

In the present embodiment, the metallic nanoparticles <NUM> are deposited only on second regions (source and drain regions) 310b, without being deposited on a first region (a channel region) 310a of the two-dimensional material layer <NUM>. Specifically, the metallic nanoparticles <NUM> may be deposited only in contact regions of source and drain electrodes <NUM> and <NUM> and the source and drain regions 310b. In an ALD or CVD process, the metallic nanoparticles <NUM> may be deposited in desired regions of the two-dimensional material layer <NUM> by a photolithography process. Accordingly, the contact resistance between the source and drain electrodes <NUM> and <NUM> and the source and drain regions 310b may be further reduced, and an increase in off current in the channel region may be prevented.

<FIG> are cross-sectional views of semiconductor devices according to some embodiments.

Referring to <FIG>, in a semiconductor device <NUM> according to another embodiment of the invention, a channel layer <NUM> includes a two-dimensional material layer <NUM> provided on a substrate <NUM>, and metallic nanoparticles <NUM> selectively deposited on a certain portion of the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> are selectively deposited only on defects and/or grain boundaries of the two-dimensional material layer <NUM>.

In the present embodiment, the metallic nanoparticles <NUM> include first metallic nanoparticles 420a and second metallic nanoparticles 420b including a material that is different from the first metallic nanoparticles 420a. The first metallic nanoparticles 420a are deposited on a first region (a channel region) 410a of the two-dimensional material layer <NUM>, and the second metallic nanoparticles 420b are deposited on second regions (source and drain regions) 410b of the two-dimensional material layer <NUM>.

The difference in work function between the second metallic nanoparticles 420b and the two-dimensional material layer <NUM> deposited on the second region 410b may be greater than the difference in work function between the first metallic nanoparticles 420a and the two-dimensional material layers <NUM> deposited on the first region 410a. Accordingly, the contact resistance between source and drain electrodes <NUM> and <NUM> and the source and drain regions 410b may be further reduced, and off current in the channel region 210a may be prevented from increasing.

Referring to <FIG>, a semiconductor device <NUM> according to another embodiment may be the same as the semiconductor device <NUM> in <FIG> except third metallic nanoparticles 420c instead of the second metallic nanoparticles 420b may be deposited on a portion of the second region 410b of the two-dimensional material layer <NUM> under the source electrode <NUM>. The semiconductor device <NUM> may include the second metallic nanoparticles 420b on the portion of the second region 410b of the two-dimensional material layer <NUM> under the drain electrode <NUM>. The third metallic nanoparticles 420c may include a different material than a material of the second metallic nanoparticles 420b and a material of the first metallic nanoparticles 420a. The first to third metallic nanoparticles 420a, 420b, and 420b may includes different ones of Ru, RuO, Mo, W, Co, TiN, Ti, or Al, but example embodiments are not limited thereto.

Referring to <FIG>, a semiconductor device <NUM> according to another not claimed embodiment may be the same as the semiconductor device <NUM> in <FIG> except both the first metallic nanoparticles 420a and the second metallic nanoparticles 420b may be deposited on the first region 410a of the two-dimensional material layer <NUM>. In the semiconductor device <NUM>, the first metallic nanoparticles 420a may not be deposited on the second region 410b of the two-dimensional material layer <NUM>.

Referring to <FIG>, a semiconductor device <NUM> according to another not claimed embodiment may be the same as the semiconductor device <NUM> in <FIG> except both the first metallic nanoparticles 420a and the second metallic nanoparticles 420b may be deposited on the first region 410a and the second region 410b of the two-dimensional material layer <NUM>.

In the embodiments described above, the semiconductor devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> having a sheet channel structure have been exemplarily described. However, the disclosure is not limited thereto. For example, a semiconductor device having a fin channel structure (FinFET) or a semiconductor device having a gate-all-around channel structure (MBCFET; multi bridge channel FET) may be provided.

<FIG> is a perspective view illustrating a semiconductor device (FinFET) <NUM> according to another embodiment, and <FIG> is a cross-sectional view taken along line A-A' of <FIG>.

Referring to <FIG> and <FIG>, an insulator <NUM> is provided on a substrate <NUM> so as to be perpendicular to the substrate <NUM>, and a channel layer <NUM> is provided to cover the insulator <NUM>. The channel layer <NUM> may have a fin shape.

The channel layer <NUM> may include a two-dimensional material layer <NUM> and metallic nanoparticles <NUM> selectively deposited on a certain portion of the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> may be selectively deposited only on defects and/or grain boundaries of the two-dimensional material layer <NUM>. Because the two-dimensional material layer <NUM> and the metallic nanoparticles <NUM> have been described above, a detailed description thereof is omitted.

The two-dimensional material layer <NUM> may include a first region 510a and second regions 510b respectively on both sides of the first region 510a. The first region 510a may be a channel region located in the central portion of the two-dimensional material layer <NUM>. The second regions 510b may be source and drain regions respectively on both sides of the two-dimensional material layer <NUM>.

A gate insulating layer <NUM> is provided on the first region 510a of the two-dimensional material layer <NUM>, and a gate electrode <NUM> is provided on the gate insulating layer <NUM>. The gate insulating layer <NUM> may be provided to surround the channel layer <NUM>, specifically three surfaces of the first region 510a of the two-dimensional material layer <NUM>, and the gate electrode <NUM> may be provided to surround three surfaces of the gate insulating layer <NUM>. On the other hand, although not illustrated, the source and drain electrodes may be respectively provided on the second regions 510b of the two-dimensional material layer <NUM>.

According to a not claimed embodiment, the metallic nanoparticles <NUM> may be deposited on the first and second regions 510a and 510b of the two-dimensional material layer <NUM> at a substantially uniform density. According to the invention, the metallic nanoparticles <NUM> are deposited on the second regions 510b at a higher density than on the first region 510a of the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> may be deposited only on the second regions 510b of the two-dimensional material layer <NUM>. According to the invention, first metallic nanoparticles are deposited on the first region 510a of the two-dimensional material layer <NUM>, and second metallic nanoparticles are deposited on the second regions 510b of the two-dimensional material layer <NUM>, a material of the second metallic nanoparticles is different from a material of the first metallic nanoparticles.

<FIG> is a perspective view illustrating a semiconductor device (MBCFET) <NUM> according to another embodiment, and <FIG> is a cross-sectional view taken along line B-B' of <FIG>.

Referring to <FIG> and <FIG>, at least one channel layer <NUM> is disposed over a substrate <NUM> so as to be spaced apart from the substrate <NUM>. The at least one channel layer <NUM> may each have a sheet shape disposed in parallel to the substrate <NUM>. <FIG> and <FIG> illustrate a case where two channel layers <NUM> are vertically disposed over the substrate <NUM>.

According to a not claimed embodiment, the two channel layers <NUM> may each include a two-dimensional material layer <NUM> and metallic nanoparticles <NUM> selectively deposited on a certain portion of the two-dimensional material layer <NUM>. The metallic nanoparticles <NUM> may be selectively deposited only on defects and/or grain boundaries of the two-dimensional material layer <NUM>. Because the two-dimensional material layer <NUM> and the metallic nanoparticles <NUM> have been described above, a detailed description thereof is omitted.

The two-dimensional material layer <NUM> may include a first region 610a and second regions 610b respectively on both sides of the first region 610a. The first region 610a may be a channel region located in the central portion of the two-dimensional material layer <NUM>. The second regions 610b may be source and drain regions respectively on both sides of the two-dimensional material layer <NUM>.

A gate insulating layer <NUM> is provided on the first region 610a of the two-dimensional material layer <NUM>, and a gate electrode <NUM> is provided on the gate insulating layer <NUM>. The gate insulating layer <NUM> may be provided to surround the channel layer <NUM>, specifically four surfaces of the first region 610a of the two-dimensional material layer <NUM>, and the gate electrode <NUM> may be provided to surround four surfaces of the gate insulating layer <NUM>. Although not illustrated, the source and drain electrodes may be respectively provided on the second regions 610b of the two-dimensional material layer <NUM>. On the other hand, an insulator (not illustrated) may be disposed over the substrate <NUM> in parallel to the substrate <NUM>, and the channel layer <NUM> may be provided to surround the insulator.

The semiconductor devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above may be applied to, for example, a memory device, such as dynamic random access memory (DRAM). The memory device may have a structure in which each of the semiconductor devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above is connected to a capacitor. Also, the semiconductor devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be applied to various electronic devices. For example, the semiconductor devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above may be used for arithmetic operations, program execution, temporary data retention, and the like in electronic devices, such as mobile devices, computers, laptops, sensors, network devices, and neuromorphic devices.

<FIG> and <FIG> are conceptual diagrams schematically illustrating electronic device architectures applicable to an electronic device, according to an embodiment.

Referring to <FIG>, an electronic device architecture <NUM> may include a memory unit <NUM>, an arithmetic logic unit (ALU) <NUM>, and a control unit <NUM>. The memory unit <NUM>, the ALU <NUM>, and the control unit <NUM> may be electrically connected to each other. For example, the electronic device architecture <NUM> may be implemented as a single chip including the memory unit <NUM>, the ALU <NUM>, and the control unit <NUM>.

Specifically, the memory unit <NUM>, the ALU <NUM>, and the control unit <NUM> may be interconnected to each other via metal lines in an on-chip manner and may be configured to perform direct communication. The memory unit <NUM>, the ALU <NUM>, and the control unit <NUM> may be monolithically integrated on a single substrate to constitute a single chip. Input/output devices <NUM> may be connected to the electronic device architecture (chip) <NUM>.

The ALU <NUM> and the control unit <NUM> may each independently include the semiconductor devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> described above, and the memory unit <NUM> may include the semiconductor devices <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, a capacitor, or a combination thereof. The memory unit <NUM> may include both a main memory and a cache memory. The electronic device architecture (chip) <NUM> may be an on-chip memory processing unit.

Referring to the <FIG>, a cache memory <NUM>, an ALU <NUM>, and a control unit <NUM> may constitute a central processing unit (CPU) <NUM>. The cache memory <NUM> may include static random access memory (SRAM), and may include the semiconductor devices <NUM> to <NUM> described above. Apart from the CPU <NUM>, the electronic device architecture may include a main memory <NUM> and an auxiliary storage <NUM>. The main memory <NUM> may include DRAM.

In some cases, the electronic device architecture may be implemented in a form in which computing unit elements and memory unit elements are adjacent to each other on a single chip, without distinction of sub-units.

Because the semiconductor device according to the embodiment uses the two-dimensional semiconductor material as the channel layer, the semiconductor device may have excellent performance even with a small thickness of <NUM> or less. In addition, a short channel effect may be reduced. Accordingly, the limitation of performance degradation due to the reduction in the size of the semiconductor device may be overcome.

In addition, in the semiconductor device according to the embodiment, because the metallic nanoparticles are selectively deposited on the two-dimensional material layer constituting the channel layer, charges may be moved through the metallic nanoparticles, and thus, the electrical conductivity of the two-dimensional material layer may be improved. Accordingly, the contact resistance may increase in the source and drain regions of the two-dimensional material layer, and on-current may be improved due to a decrease in channel resistance in the channel region of the two-dimensional material layer. Also, the doping degree of the two-dimensional material layer may be controlled by adjusting the material type and/or the deposition amount of the metallic nanoparticles selectively deposited on the two-dimensional material layer. Accordingly, the channel polarity, threshold voltage, on-current, off-current, and the like of the semiconductor device may be controlled.

Claim 1:
A semiconductor device (<NUM>) comprising:
a two-dimensional material layer (<NUM>) including a two-dimensional semiconductor material having a polycrystalline structure;
metallic nanoparticles (<NUM>) partially on the two-dimensional material layer, wherein the metallic nanoparticles are on at least one of a defect of the two-dimensional semiconductor material and a grain boundary of the two-dimensional semiconductor material;
a source electrode (<NUM>) and a drain electrode (<NUM>) respectively on both sides of the two-dimensional material layer; and
a gate insulating layer (<NUM>) and a gate electrode (<NUM>) on the two-dimensional material layer between the source electrode and the drain electrode,
wherein the two-dimensional material layer comprises a first region (110a) and a second region (110b),
the gate electrode is on the first region of the two-dimensional material layer, and
the source electrode and the drain electrode are on the second region of the two-dimensional material layer, and
characterized in that at least one of:
the metallic nanoparticles are on the second region of the two-dimensional material layer at a higher density than a density of the metallic nanoparticles on the first region of the two-dimensional material layer; and
the metallic nanoparticles comprise first metallic nanoparticles and second metallic nanoparticles, the first metallic nanoparticles are on the first region of the two-dimensional material layer, the second metallic nanoparticles are on the second region of the two-dimensional material layer, and a material of the second metallic nanoparticles is different from a material of the first metallic nanoparticles.