Patent Description:
In high speed serial links, a repeating <NUM> pattern may occur. Such a clock pattern creates an issue for baud rate (i.e., symbol spaced) timing recovery. For example, a regular pseudorandom binary sequence (PRBS) may be transmitted and a <NUM> pattern may appear in a data link. To continuously extract information, a clock data and recovery (CDR) system may need to determine whether to increase or decrease a frequency. However, there is no information to indicate whether to increase or decrease the frequency. That is, a receiver is continuously tracking the changes in the frequency of the transmitter by either increasing (UP) or decreasing (DOWN) its own frequency. This information whether to increase or decrease comes from the CDR phase detection logic. In the case of a <NUM> pattern, the logic does not give any information to the CDR system, and the CDR system doesn't know whether to go UP or DOWN. Thus, the CDR system does not receive any new information (i.e., UP/DOWN). The previously performed update is then slightly off the true value and gets stuck in a memory, causing the CDR system to drift in a wrong direction until a random pattern is resumed. Document<NPL>, relates to a timing recovery system using a correlator and an accumulator to detect a reference pattern.

In accordance with an aspect of an example embodiment, a clock and data recovery (CDR) system is set forth according to appended claim <NUM>.

In accordance with an aspect of an example embodiment, an operating method of a CDR system is set forth according to appended claim <NUM>.

In accordance with an aspect of an example embodiment, an electronic device is set forth according to appended claim <NUM>.

Additional aspects will be set forth in part in the description that follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

The above and other aspects, features, and aspects of embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:.

The following detailed description of example embodiments refers to the accompanying drawings.

<FIG> is a diagram of a system according to an embodiment. <FIG> includes a client device <NUM>, a server device <NUM>, and a network <NUM>. The client device <NUM> and the server device <NUM> may interconnect via through the network <NUM> providing wired connections, wireless connections, or a combination of wired and wireless connections.

The client device <NUM> may include a computing device (e.g., a desktop computer, a laptop computer, a tablet computer, a handheld computer, a smart speaker, a server device, etc.), a mobile phone (e.g., a smart phone, a radiotelephone, etc.), a camera device, a wearable device (e.g., a pair of smart glasses or a smart watch), or a similar device, according to embodiments.

The server device <NUM> may include one or more devices. For example, the server device <NUM> may be a server device, a computing device, or the like which includes hardware such as processors and memories, software modules and a combination thereof to perform corresponding functions.

The network <NUM> may include one or more wired and/or wireless networks. For example, network <NUM> may include a cellular network (e.g., a fifth generation (<NUM>) network, a long-term evolution (LTE) network, a third generation (<NUM>) network, a code division multiple access (CDMA) network, etc.), a public land mobile network (PLMN), a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), a telephone network (e.g., the Public Switched Telephone Network (PSTN)), a private network, an ad hoc network, an intranet, the Internet, a fiber optic-based network, or the like, and/or a combination of these or other types of networks.

Additionally, or alternatively, a set of devices (e.g., one or more devices) may perform one or more functions described as being performed by another set of devices.

<FIG> is a diagram of components of one or more devices of <FIG> according to an embodiment. Device <NUM> shown in <FIG> may correspond to the user device <NUM> and/or the server device <NUM>.

As shown in <FIG>, the device <NUM> may include a bus <NUM>, a processor <NUM>, a memory <NUM>, a storage component <NUM>, an input component <NUM>, an output component <NUM>, and a communication interface <NUM>.

The bus <NUM> may include a component that permits communication among the components of the device <NUM>. The processor <NUM> may be implemented in hardware, software, firmware, or a combination thereof. The processor <NUM> may be implemented by one or more of a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and another type of processing component. The processor <NUM> may include one or more processors capable of being programmed to perform a corresponding function.

The memory <NUM> may include a random access memory (RAM), a read only memory (ROM), and/or another type of dynamic or static storage device (e.g., a flash memory, a magnetic memory, and/or an optical memory) that stores information and/or instructions for use by the processor <NUM>.

The storage component <NUM> may store information and/or software related to the operation and use of the device <NUM>. For example, the storage component <NUM> may include a hard disk (e.g., a magnetic disk, an optical disk, a magneto-optic disk, and/or a solid state disk), a compact disc (CD), a digital versatile disc (DVD), a floppy disk, a cartridge, a magnetic tape, and/or another type of non-transitory computer-readable medium, along with a corresponding drive.

The input component <NUM> may include a component that permits the device <NUM> to receive information, such as via user input (e.g., a touch screen display, a keyboard, a keypad, a mouse, a button, a switch, and/or a microphone). The input component <NUM> may also include a sensor for sensing information (e.g., a global positioning system (GPS) component, an accelerometer, a gyroscope, and/or an actuator).

The output component <NUM> may include a component that provides output information from the device <NUM> (e.g., a display, a speaker, and/or one or more light-emitting diodes (LEDs)).

The communication interface <NUM> may include a transceiver-like component (e.g., a transceiver and/or a separate receiver and transmitter) that enables the device <NUM> to communicate with other devices, such as via a wired connection, a wireless connection, or a combination of wired and wireless connections. The communication interface <NUM> may permit device <NUM> to receive information from another device and/or provide information to another device. For example, the communication interface <NUM> may include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, a radio frequency (RF) interface, a universal serial bus (USB) interface, a Wi-Fi interface, a cellular network interface, or the like.

The device <NUM> may perform one or more processes described herein. The device <NUM> may perform operations based on the processor <NUM> executing software instructions stored in a non-transitory computer-readable medium, such as the memory <NUM> and/or the storage component <NUM>. A computer-readable medium is defined herein as a non-transitory memory device. A memory device includes memory space within a single physical storage device or memory space spread across multiple physical storage devices.

Software instructions may be read into the memory <NUM> and/or the storage component <NUM> from another computer-readable medium or from another device via the communication interface <NUM>. When executed, software instructions stored in the memory <NUM> and/or storage component <NUM> may cause the processor <NUM> to perform one or more processes described herein.

Thus, embodiments described herein are not limited to any specific combination of hardware circuitry and software.

Provided are a system, method and device that detect and correct a repeated <NUM> pattern, according to an embodiment. As used herein, a "<NUM> pattern" may refer to a data pattern in a pseudorandom binary sequence (PRBS) where the bit pattern of "<NUM>" is repeated. The systems, methods and devices according to embodiments may utilize a correlator that may include a single delay element and may be configured to detect a long string of a <NUM> pattern. The correlator may be configured to receive the incoming pattern. Since the correlator may be configured to detect a <NUM> pattern (i.e., the correlator may be configured to detect a particular pattern), the correlator may be implemented with a single delay line in the overall structure.

Based on detecting the <NUM> pattern, the system, method and device in the present embodiment may correct for the effects of long periods of a <NUM> clock pattern by supplying a running average of the history in a Kf register. The running average may be determined by a leaky integrator. The system, method and device may include a relief integrator, and a delay line which stores a previous value.

<FIG> is a diagram of a clock and data recovery (CDR) system, according to an embodiment. The system may include a transmitter (TX) <NUM> configured to transmit data based on a TX clock (CLK) signal <NUM> to a channel plus analog front end (AFE) <NUM> (the CLK signal <NUM> may be recovered at a receiver implementing a CDR circuit based on the data that is based on the CLK signal <NUM>). The output of the channel + AFE <NUM> may be accumulated with noise by an adder <NUM>, and the output of the adder <NUM> may be sent to a data slicer <NUM>. A phase detector <NUM> may receive the output of the data slicer <NUM>. Further, based on the output of the phase detector <NUM> and an input error, the phase detector <NUM> may generate a signal that is output to a proportional-integral loop filter <NUM>. The proportional-integral loop filter <NUM> may include an adder <NUM>, a delay line <NUM>, a Kp register <NUM>, a Kf register <NUM>, an adder <NUM>, and a gain function <NUM>. The signal output by the proportional-integral loop filter <NUM> may be sent to a voltage-controlled oscillator (VCO) <NUM>. The signal from the VCO <NUM> (e.g., CLOCK (Øin)) may be looped back to the data slicer <NUM>.

The adder <NUM> may accumulate the output of the delay line <NUM> which stores the previous value of the Kf register <NUM>. The output of the phase detector <NUM> may be either <NUM>, <NUM> or -<NUM>. When the data is a <NUM> pattern, the output of the phase detector <NUM> is <NUM>. In this case, the output of the Kp register <NUM> is <NUM>, and the output of the Kf register <NUM> is not the true value. Therefore, the VCO <NUM> may drift. The delay line <NUM> may become stuck because it is storing the previous value of the Kf register <NUM>, which, in this case, is not the true value.

When a CDR is running an open loop (i.e., when an error input (e.g., <NUM>) occurs, no action is taken, which happens during a <NUM> pattern), the memory of the Kf register <NUM> may cause various problems. The value in the Kf register <NUM> should be one constant value. However, due to noise and loop dynamics, the run time value may move around the constant value. When the loop stops updating under the <NUM> pattern, the Kf register <NUM> may be stuck at a random value around the desired/ideal value, causing phase drift in one direction, resulting in the CDR losing the lock.

The CDR system shown in <FIG> (as well as in other embodiments disclosed herein) may be implemented in a variety of devices, including a display device. For example, the TX <NUM> may be implemented in s display device controller and a receiver with a CDR circuit in communication with the TX <NUM> may be connected a component of pixel drivers. The CDR circuit may be configured to extract a clock from data signals (e.g., pixel data) sent by the TX <NUM>.

<FIG> is a graph showing output values of a CDR system, according to an embodiment. True/ideal values <NUM> are shown to fluctuate. However, when a <NUM> pattern enters the system, as shown in the output values <NUM>, output values <NUM> are no longer fluctuating, the output of the Kf register may not be the true value, and the VCO may drift.

<FIG>, <FIG> and <FIG> are diagrams of a CDR system, according to an embodiment. The CDR system of <FIG> may include components similar to those of the CDR system of <FIG> except that the CDR system of <FIG> further includes an additional <NUM> pattern detection and correction block <NUM>. Thus, duplicate descriptions may be omitted herebelow for brevity purposes.

The detection and correction block <NUM> may detect the output of the data slicer <NUM>. The detection and correction block <NUM> may include a correlator <NUM>, an accumulator <NUM>, and a state machine <NUM>. The correlator <NUM> may be a <NUM>-tap correlator including a delay line <NUM>, a logical inverter or NOT gate <NUM> (or some other component configured to multiply the input by -<NUM>), and an adder <NUM>. The adder <NUM> may have a different bitwidth (e.g., smaller) than other adders in the CDR system. Some correlators may include a number of delay lines to detect a pattern being detected, as the specific pattern attempting to be detected may not be previously known or targeted. That is, in a correlator configured to detect an unknown pattern or multiple patterns, the number of components (e.g., the number of delay lines) is increased. However, according to embodiments, the single delay line <NUM> may be utilized to take advantage of the fact that the pattern attempting to be detected is a particular repeating pattern (i.e., <NUM> pattern). The correlator <NUM> may be configured to receive data (e.g., data from data slicer <NUM>), determine a first value of the received data, and output a second value corresponding to the received data. For example, the correlator <NUM> may be configured to output a value of <NUM> when a previous bit and a current bit are the same, and then output a different value when the previous bit and current bit are different (e.g., <NUM> or <NUM> depending on the bitwidth of the adder <NUM>).

The accumulator <NUM> may include an adder <NUM> and a delay line <NUM> that stores a previous value output from the adder <NUM>. The accumulator <NUM> may receive the output from the correlator <NUM>, and generate an output that is received by the state machine <NUM>.

The state machine <NUM> may determine whether a <NUM> pattern is occurring by comparing the output of the accumulator <NUM> with a predetermined threshold value. For example, the state machine <NUM> may compare the output of the accumulator <NUM> at each cycle of a predetermined number of cycles (e.g., N cycles). Based on the state machine <NUM> determining that the output of the accumulator <NUM> exceeds (or is greater than or equal to) the predetermined threshold, the state machine <NUM> may set a flag value based on the determination (e.g., FLAG = <NUM>). Based on the state machine <NUM> determining that the output of the accumulator <NUM> does not exceed (or is less than or equal to) the predetermined threshold, the state machine <NUM> may set a flag value based on the determination (e.g., FLAG = <NUM>). The state machine <NUM> may also reset the delay line <NUM>, for example, during each of a predetermined number of cycles.

As shown in <FIG>, The state machine <NUM> may output the flag value to the proportional-integral loop filter <NUM> as is described further below. As shown in <FIG>, the state machine <NUM> may output the flag value to the delay line <NUM>. As shown in <FIG>, the state machine <NUM> may output the flag value to the adder <NUM>.

<FIG> is a graph showing detection of a <NUM> pattern by a state machine, according to an embodiment. In the example shown in <FIG>, a clock cycle is shown against a value of an accumulator (e.g., accumulator <NUM>), and a threshold value <NUM> is set as <NUM> (although it will be understood to those of skill in the art that other threshold values may be utilized).

As shown in <FIG>, random data occurs before and after the <NUM> pattern. The <NUM> pattern causes the output value of accumulator to exceed the threshold value <NUM>, such that the state machine (e.g., the state machine <NUM>) may determine the occurrence of the <NUM> pattern. Although <FIG> depicts an example where the threshold value <NUM> is exceeded eight times, the system may be configured to set a predetermined number of occurrences of exceeding the threshold value <NUM> before determining that a <NUM> pattern has occurred. As the state machine may determine that the <NUM> pattern has occurred, the state machine may set a flag value accordingly and output the flag value to a proportional-integral loop filter, as is described further below.

<FIG> is a diagram of CDR system data without detection and correction of a <NUM> pattern, according to an embodiment. Graph <NUM> shows a fraction of a symbol period versus an input voltage. As shown in graph <NUM>, random data occurs before and after a <NUM> pattern, and the <NUM> pattern causes bit slip (e.g., errors).

<FIG> is a diagram of CDR system data with detection and correction of a <NUM> pattern, according to an embodiment. Graph <NUM> shows a fraction of a symbol period versus an input voltage. As shown in graph <NUM>, random data occurs before and after a <NUM> pattern, but due to the correction, no bit slips (e.g., no errors) occur.

<FIG> and <FIG> are diagrams of a CDR system, according to an embodiment. The CDR system of <FIG> and <FIG> is similar to the CDR system of <FIG>. Thus, duplicate descriptions are omitted herein. However, the CDR system of <FIG> and <FIG> may further include an integrator <NUM> and a multiplier <NUM>. The output of the correlator <NUM> may be integrated to exploit the advantage of the repetition in the pattern without adding extra delay lines. That is, by knowing that the pattern sought to be detected is a repeating pattern of <NUM> (i.e., the system does not want to detect other specific patterns), delay lines may be omitted that would ordinarily be implemented for general pattern detection.

As shown in <FIG>, the state machine <NUM> may output the flag value to the proportional-integral loop filter <NUM> and, in particular, as shown in <FIG>, to the delay line <NUM> (as well as other components in the proportional-integral loop filter <NUM> as will be understood by those of skill in the art from the disclosure herein).

<FIG> is a diagram of a CDR system, according to an embodiment. The CDR system of <FIG> is similar to the CDR systems of <FIG> and <FIG>. Thus, duplicate descriptions are omitted herein. However, the CDR system of <FIG>, in the proportional-integral loop filter <NUM>, may further include a leaky integrator <NUM> and a multiplexer (MUX) <NUM>.

The leaky integrator <NUM> may be configured to monitor or determine a running average of the Kf register <NUM> and output the running average to the MUX <NUM>. The output of the delay line <NUM> may also be sent to the MUX <NUM>. The aforementioned flag value generated by the state machine <NUM> may be sent to the MUX <NUM>. Based on the flag value being set to <NUM> (e.g., the state machine <NUM> determines that the value of the accumulator <NUM> does not exceed (or is at least equal to) the predetermined threshold value), the MUX <NUM> may select the value of the delay line <NUM> to be output to the accumulator <NUM> (i.e., the CDR system continues to operate in a normal/regular mode). Based on the flag value being set to <NUM> (e.g., the state machine <NUM> determines that the value of the accumulator <NUM> does exceed (or is at least equal to) the predetermined threshold value), the MUX <NUM> may select the value of the leaky integrator <NUM> to be output to the accumulator <NUM>. That is, the CDR system may determine the presence of a <NUM> pattern, and that the Kf register <NUM> may be stuck, thereby resetting the system based on a previous value of the Kf register <NUM> that is determined from a running average determined by the leaky integrator <NUM>.

<FIG> is a graph showing leaky integrator data, according to an embodiment. The graph <NUM> shows a value in a Kf register over time. The line <NUM> indicates a running average value of the Kf register that is determined by the leaky integrator. As shown by section <NUM>, a <NUM> pattern causes the running average value of the Kf register to decrease drastically. Thus, when the flag value indicates that the running average value of the Kf register should be used, the leaky integrator may be configured to output a value from a predetermined time point prior to a value decrease point <NUM>. An input of the leaky integrator may be X(n), and an output of the leaky integrator may be Y(n) = α Y(n-<NUM>) + (<NUM>- α) X(n), where α = <NUM> - <NUM> -R, and R: <NUM>, <NUM>,.

<FIG> is a flowchart of a method of a CDR system, according to an embodiment. In operation <NUM>, the CDR system may receive data. For example, the correlator <NUM> may receive data from an output of the data slicer <NUM>. In operation <NUM>, the CDR system may determine a first value of the received data. For example, the correlator may determine the first value using delay line <NUM>, the logical inverter/NOT gate <NUM> and the adder <NUM>. In operation <NUM>, the CDR system may output a second value corresponding to the received data. For example, the correlator <NUM> may output the second value from the adder <NUM>. In operation <NUM>, the system may generate an accumulation value by accumulating the second value. For example, the accumulator <NUM> may accumulate the second value with the adder <NUM>. In operation <NUM>, the CDR system may output the accumulation value. For example, the accumulator <NUM> may output the accumulation value from the adder <NUM>. In operation <NUM>, the system may determine whether a repeating pattern is present in the CDR system based on the accumulation value. For example, the state machine <NUM> may receive the accumulation value and determine whether a repeating pattern is present in the CDR system based on the accumulation value.

Some embodiments may relate to a system, a method, and/or a computer readable medium at any possible technical detail level of integration. The computer readable medium may include a computer-readable non-transitory storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out operations.

Computer readable program code/instructions for carrying out operations may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the "C" programming language or similar programming languages. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects or operations.

At least one of the components, elements, modules or units (collectively refer to "components" in this paragraph) represented by a block in the drawings including <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG> and <FIG> may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an example embodiment. According to example embodiments, at least one of these components may use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Further, at least one of these components may include or may be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Two or more of these components may be combined into one single component which performs all operations or functions of the combined two or more components. Also, at least part of functions of at least one of these components may be performed by another of these components. Functional aspects of the above example embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.

The flowchart and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer readable media according to various embodiments. The method, computer system, and computer readable medium may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in the Figures. For example, two blocks shown in succession may, in fact, be executed concurrently or substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles "a" and "an" are intended to include one or more items, and may be used interchangeably with "one or more. " Furthermore, as used herein, the term "set" is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.), and may be used interchangeably with "one or more. " Where only one item is intended, the term "one" or similar language is used. Also, as used herein, the terms "has," "have," "having," or the like are intended to be open-ended terms. Further, the phrase "based on" is intended to mean "based, at least in part, on" unless explicitly stated otherwise.

Claim 1:
A clock and data recovery system, hereafter CDR system, comprising:
a correlator (<NUM>) configured to:
receive data;
determine a first value of the received data; and
output a second value corresponding to the received data;
an accumulator (<NUM>) configured to:
generate an accumulation value by accumulating the second value output from the correlator; and
output the accumulation value; and
a state machine (<NUM>) configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value, wherein the repeating pattern comprises a repeating <NUM> pattern,
wherein the CDR system further comprises a loop filter comprising a delay line, a leaky integrator (<NUM>), a multiplexer (<NUM>), and a register (<NUM>),
wherein the state machine is further configured to, based on determining that the repeating pattern is present in the CDR system, send a flag value to the multiplexer causing the loop filter to use a third value stored in the leaky integrator; and
wherein the state machine is further configured to, based on determining that the repeating pattern is not present in the CDR system, send a flag value to the multiplexer causing the loop filter to use a fourth value stored in the delay line.