Patent Description:
Embodiments of the present disclosure relate to semiconductor devices and fabrication methods thereof.

In modern mobile devices (e.g., smartphones, tablets, etc.), multiple complicated system-on-chips (SOCs) are used to enable various functionalities, such as application processor, dynamic random-access memory (DRAM), Flash memory, various controllers for Bluetooth, Wi-Fi, global positioning system (GPS), frequency modulation (FM) radio, display, etc., and baseband processor, which are formed as discrete chips. For example, application processor typically is large in size including central processing units (CPUs), graphics processing units (GPUs), on-chip memory, accelerating function hardware, and other analog components.

<CIT> discloses a prefetching from dynamic random access memory to a static random access memory. <CIT> discloses a 3D Compute Circuit with High Density Z-Axis In more details, <CIT> discloses:
A semiconductor device comprising: a first semiconductor structure comprising a processor, memory cells and a first bonding layer comprising a plurality of first bonding contacts; a second semiconductor structure comprising an array of memory cells and a second bonding layer comprising a plurality of second bonding contacts, wherein the first semiconductor structure comprises a peripheral circuit of the array of DRAM cells and an interconnect layer vertically between the first bonding layer and the processor above a device layer to transfer electrical signals to and from the processor, the memory cells and the peripheral circuit, wherein the device layer comprises the processor, memory cells and the peripheral circuit; and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface, wherein the first semiconductor structure comprises: a substrate; the processor on the substrate; the memory cells on the substrate and outside of the processor; and the first bonding layer above the processor and the memory cells.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed herein.

One aspect of the present invention is a semiconductor device according to claim <NUM>.

Another aspect of the present invention is a method for forming a semiconductor device according to claim <NUM>.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

Moreover, such phrases do not necessarily refer to the same embodiments.

As used herein, a "wafer" is a piece of a semiconductor material for semiconductor devices to build in and/or on it and that can undergo various fabrication processes before being separated into dies.

As modern processor (also known as "microprocessor") developed into more advanced generations, the cache size is playing an incrementally important role for processor performance enhancement. In some cases, cache occupied half or even more chip real estate in microprocessor chip. Also, the resistive-capacitive (RC) delay from the cache to the processor core logic could become significant to degrade performance. Moreover, a bus interface unit is needed to electrically connect the processor to external main memory. The bus interface unit itself, however, occupies additional chip area, and its electrical connection to main memory needs additional region for metal routing and introduces additional RC delay.

Various embodiments in accordance with the present disclosure provide a semiconductor device with a processor core, cache, and main memory integrated on a bonded chip to achieve better cache performance (faster data transfer with higher efficiency), wider data bandwidth, fewer bus interface units, and faster memory interface speed. The semiconductor device disclosed herein includes a first semiconductor structure having a processor core and SRAM (e.g., as cache) and a second semiconductor structure having DRAM (e.g., as main memory) bonded to the first semiconductor structure with a large number of short-distanced vertical metal interconnects instead of the peripherally-distributed, long-distanced metal routing, or even conventional through silicon vias (TSVs). In some embodiments, the cache module can be divided into smaller cache regions, distributing randomly according to bonding contact design.

As a result, shorter manufacturing cycle time with higher yield can be achieved due to less interactive influences from manufacturing processes of the processor wafer and the DRAM wafer as well as the known good hybrid bonding yield. The shorter connection distance between the processor and DRAM, such as from millimeter or centimeter-level to micrometer-level, can improve the processor performance with faster data transfer rate, improve processor core logic efficiency with wider bandwidth, and improve system speed.

<FIG> illustrates a schematic view of a cross-section of an exemplary semiconductor device <NUM>, according to some embodiments. Semiconductor device <NUM> represents an example of a bonded chip. The components of semiconductor device <NUM> (e.g., processors/SRAM and DRAM) are formed separately on different substrates and then jointed to form a bonded chip. Semiconductor device <NUM> includes a first semiconductor structure <NUM> including a processor and an array of SRAM cells. In some embodiments, the processor and SRAM cell array in first semiconductor structure <NUM> use complementary metal-oxide-semiconductor (CMOS) technology. Both the processor and the SRAM cell array can be implemented with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.) to achieve high speed.

The processor can include a specialized processor including, but not limited to, CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), vision processing unit (VPU), neural processing unit (NPU), synergistic processing unit (SPU), physics processing unit (PPU), and image signal processor (ISP). The processor can also include an SoC that combines multiple specialized processors, such as an application processor, baseband processor, and so on. In some embodiments in which semiconductor device <NUM> is used in mobile devices (e.g., smartphones, tablets, eyeglasses, wrist watches, virtual reality/augmented reality headsets, laptop computers, etc.), an application processor handles applications running in an operating system environment, and a baseband processor handles the cellular communications, such as the second-generation (<NUM>), the third-generation (<NUM>), the fourth-generation (<NUM>), the fifth-generation (<NUM>), the sixth-generation (<NUM>) cellular communications, and so on.

Other processing units (also known as "logic circuits") besides the processor can are formed in first semiconductor structure <NUM> as well, such as one or more controllers and/or the entirety or part of the peripheral circuits of the DRAM of a second semiconductor structure <NUM>. A controller can handle a specific operation in an embedded system. In some embodiments in which semiconductor device <NUM> is used in mobile devices, each controller can handle a specific operation of the mobile device, for example, communications other than cellular communication (e.g., Bluetooth communication, Wi-Fi communication, FM radio, etc.), power management, display drive, positioning and navigation, touch screen, camera, etc. First semiconductor structure <NUM> of semiconductor device <NUM> thus can further include a Bluetooth controller, a Wi-Fi controller, a FM radio controller, a power controller, a display controller, a GPS controller, a touch screen controller, a camera controller, to name a few, each of which is configured to control operations of the corresponding component in a mobile device.

The first semiconductor structure <NUM> of semiconductor device <NUM> further includes the entirety or part the peripheral circuits of the DRAM of second semiconductor structure <NUM>. The peripheral circuits (also known as control and sensing circuits) can include any suitable digital, analog, and/or mixed-signal circuits used for facilitating the operations of the DRAM. The peripheral circuits on the first semiconductor structure <NUM> at least include an input/output buffer, a decoder (e.g., a row decoder and a column decoder), and a sense amplifier. The peripheral circuits can further include any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors).

The SRAM is integrated on the same substrate of the logic circuits (i.e., the processor and peripheral circuits), allowing wider bus and higher operation speed, which is also known as "on-die SRAM". The memory controller of the SRAM can be embedded as part of the peripheral circuits. In some embodiments, each SRAM cell includes a plurality of transistors for storing a bit of data as a positive or negative electrical charge as well as one or more transistors that control access to it. In one example, each SRAM cell has six transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)), for example, four transistors for storing a bit of data and two transistors for controlling access to the data. The SRAM cells can locate in the area that is not occupied by the logic circuits (e.g., the processor and peripheral circuits) and thus, do not need extra space to be formed. The on-die SRAM can enable high-speed operations of semiconductor device <NUM>, used as one or more caches (e.g., instruction cache or data cache) and/or data buffers.

Semiconductor device <NUM> also includes second semiconductor structure <NUM> including an array of DRAM cells. That is, second semiconductor structure <NUM> can be a DRAM memory device. DRAM requires periodic refreshing of the memory cells. The memory controller for refreshing the DRAM can be embedded as another example of the controllers and peripheral circuits described above. In some embodiments, each DRAM cell includes a capacitor for storing a bit of data as a positive or negative electrical charge as well as one or more transistors that control access to it. In one example, each DRAM cell is a one-transistor, one-capacitor (1T1C) cell.

As shown in <FIG>, semiconductor device <NUM> further includes a bonding interface <NUM> vertically between first semiconductor structure <NUM> and second semiconductor structure <NUM>. As described below in detail, first and second semiconductor structures <NUM> and <NUM> can be fabricated separately (and in parallel in some embodiments) such that the thermal budget of fabricating one of first and second semiconductor structures <NUM> and <NUM> does not limit the processes of fabricating another one of first and second semiconductor structures <NUM> and <NUM>. Moreover, a large number of interconnects (e.g., bonding contacts) can be formed through bonding interface <NUM> to make direct, short-distance (e.g., micron-level) electrical connections between first semiconductor structure <NUM> and second semiconductor structure <NUM>, as opposed to the long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on the circuit board, such as printed circuit board (PCB), thereby eliminating chip interface delay and achieving high-speed I/O throughput with reduced power consumption. Data transfer between the DRAM in second semiconductor structure <NUM> and the processor in first semiconductor structure <NUM> as well as between the DRAM in second semiconductor structure <NUM> and the SRAM in first semiconductor structure <NUM> are performed through the interconnects (e.g., bonding contacts) across bonding interface <NUM>. By vertically integrating first and second semiconductor structures <NUM> and <NUM>, the chip size can be reduced, and the memory cell density can be increased. Furthermore, as a "unified" chip, by integrating multiple discrete chips (e.g., various processors, controllers, and memories) into a single bonded chip (e.g., semiconductor device <NUM>), faster system speed and smaller PCB size can be achieved as well.

<FIG> is not part of the claim invention but is useful for understanding it. It is understood that the relative positions of stacked first and second semiconductor structures <NUM> and <NUM> are not limited. <FIG> illustrates a schematic view of a cross-section of another exemplary semiconductor device <NUM>. Being different from semiconductor device <NUM> in <FIG> in which second semiconductor structure <NUM> including the array of DRAM cells is above first semiconductor structure <NUM> including the processor and the array of SRAM cells, in semiconductor device <NUM> in <FIG>, first semiconductor structure <NUM> including the processor and the array of SRAM cells is above second semiconductor structure <NUM> including the array of DRAM cells. Nevertheless, bonding interface <NUM> is formed vertically between first and second semiconductor structures <NUM> and <NUM> in semiconductor device <NUM>, and first and second semiconductor structures <NUM> and <NUM> are jointed vertically through bonding (e.g., hybrid bonding) according to some embodiments. Data transfer between the DRAM in second semiconductor structure <NUM> and the processor in first semiconductor structure <NUM> as well as the data transfer between the DRAM in second semiconductor structure <NUM> and the SRAM in first semiconductor structure <NUM> can be performed through the interconnects (e.g., bonding contacts) across bonding interface <NUM>.

<FIG> illustrates a schematic plan view of an exemplary semiconductor structure <NUM> having a processor and SRAM, according to some embodiments. Semiconductor structure <NUM> can include a processor <NUM> on the same substrate as SRAM <NUM> and fabricated using the same logic process as SRAM <NUM>. Processor <NUM> can include one or more of CPUs, GPUs, DSPs, application processors, baseband processors, to name a few. SRAM <NUM> can be disposed outside of processor <NUM>. For example, <FIG> shows an exemplary layout of SRAM <NUM> in which the array of SRAM cells are distributed in a plurality of separate regions in semiconductor structure <NUM>, which is outside of processor <NUM>. That is, the cache module formed by SRAM <NUM> can be divided into smaller cache regions, distributing outside of processor <NUM> in semiconductor structure <NUM>. In one example, the distribution of the cache regions may be based on the design of the bonding contacts, e.g., occupying the areas without bonding contacts. In another example, the distribution of the cache regions may be random. As a result, more internal cache (e.g., using on-die SRAM) can be arranged surrounding processor <NUM> without occupying additional chip area.

<FIG> illustrates a schematic plan view of an exemplary semiconductor structure <NUM> having DRAM and peripheral circuits, according to some embodiments. Semiconductor structure <NUM> can include DRAM <NUM> on the same substrate as the peripheral circuits of DRAM <NUM>. Semiconductor structure <NUM> can include all the peripheral circuits for controlling and sensing DRAM <NUM>, including, for example, row decoders <NUM>, column decoders <NUM>, and any other suitable devices. <FIG> shows an exemplary layout of the peripheral circuit (e.g., row decoders <NUM>, column decoders <NUM>) and DRAM <NUM> in which the peripheral circuit (e.g., row decoders <NUM>, column decoders <NUM>) and DRAM <NUM> are formed in different regions on the same plane. For example, the peripheral circuit (e.g., row decoders <NUM>, column decoders <NUM>) may be formed outside of DRAM <NUM>.

It is understood that the layouts of semiconductor structures <NUM> and <NUM> are not limited to the exemplary layouts in <FIG>. In accordance with the claimed invention, part of the peripheral circuits of DRAM <NUM> including a decoder (e.g., one or more of row decoders <NUM>, column decoders <NUM>), an input/output buffer and a sense amplifier is in semiconductor structure <NUM> having processor <NUM> and SRAM <NUM>. That is, the peripheral circuits of DRAM <NUM> may be distributed on both semiconductor structures <NUM> and <NUM>, according to some other embodiments. In some embodiments, at least some of the peripheral circuits (e.g., row decoders <NUM>, column decoders <NUM>) and DRAM <NUM> (e.g., the array of DRAM cells) are stacked one over another, i.e., in different planes. For example, DRAM <NUM> (e.g., the array of DRAM cells) is formed above the peripheral circuits to further reduce the chip size. Similarly, in some embodiments, at least part of SRAM <NUM> (e.g., the array of SRAM cells) and processor <NUM> are stacked one over another, i.e., in different planes. For example, SRAM <NUM> (e.g., the array of SRAM cells) may be formed above or below processor <NUM> to further reduce the chip size.

<FIG> illustrates a schematic plan view of an exemplary semiconductor structure <NUM> having a processor, SRAM, and peripheral circuits. Semiconductor structure <NUM> is one example of first semiconductor structure <NUM>. Semiconductor structure <NUM> includes processor <NUM> on the same substrate as SRAM <NUM> and the peripheral circuits (e.g., row decoders <NUM>, column decoders <NUM>) and fabricated using the same logic process as SRAM <NUM> and the peripheral circuits. Processor <NUM> can include one or more of CPUs, GPUs, DSPs, application processors, baseband processors, to name a few. Both SRAM <NUM> and the peripheral circuits (e.g., row decoders <NUM>, column decoders <NUM>) are disposed outside of processor <NUM>. For example, <FIG> shows an exemplary layout of SRAM <NUM> in which the array of SRAM cells are distributed in a plurality of separate regions in semiconductor structure <NUM>, which is outside of processor <NUM>. Semiconductor structure <NUM> includes all the peripheral circuits for controlling and sensing DRAM <NUM>, including, for example, row decoders <NUM>, column decoders <NUM>, and any other suitable devices. <FIG> shows an exemplary layout of the peripheral circuits (e.g., row decoders <NUM>, column decoders <NUM>) in which the peripheral circuits (e.g., row decoders <NUM>, column decoders <NUM>) and SRAM <NUM> are formed in different regions on the same plane outside of processor <NUM>. It is understood that in some embodiments, at least some of the peripheral circuits (e.g., row decoders <NUM>, column decoders <NUM>), SRAM <NUM> (e.g., the array of SRAM cells), and processor <NUM> are stacked one over another, i.e., in different planes. For example, SRAM <NUM> (e.g., the array of SRAM cells) may be formed above or below the peripheral circuits to further reduce the chip size.

<FIG> illustrates a schematic plan view of an exemplary semiconductor structure <NUM> having DRAM. Semiconductor structure <NUM> may be one example of second semiconductor structure <NUM>. By moving all the peripheral circuits (e.g., row decoders <NUM>, column decoders <NUM>) away from semiconductor structure <NUM> (e.g., to semiconductor structure <NUM>), the size of DRAM <NUM> (e.g., the number of DRAM cells) in semiconductor structure <NUM> can be increased.

<FIG> illustrates a cross-section of an exemplary semiconductor device <NUM>, in accordance with the claimed invention. As one example of semiconductor device <NUM> described above with respect to <FIG>, semiconductor device <NUM> is a bonded chip including a first semiconductor structure <NUM> and a second semiconductor structure <NUM> stacked over first semiconductor structure <NUM>. First and second semiconductor structures <NUM> and <NUM> are jointed at a bonding interface <NUM> therebetween. As shown in <FIG>, first semiconductor structure <NUM> includes a substrate <NUM>, which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials.

First semiconductor structure <NUM> of semiconductor device <NUM> includes a device layer <NUM> above substrate <NUM>. It is noted that x- and y-axes are added in <FIG> to further illustrate the spatial relationship of the components in semiconductor device <NUM>. Substrate <NUM> includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (the lateral direction or width direction). As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., semiconductor device <NUM>) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM>) in the y-direction (the vertical direction or thickness direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure.

Device layer <NUM> includes a processor <NUM> on substrate <NUM> and an array of SRAM cells <NUM> on substrate <NUM> and outside of processor <NUM>. Device layer <NUM> further includes a peripheral circuit <NUM> on substrate <NUM> and outside of processor <NUM>. Peripheral circuit <NUM> is part or the entirety of the peripheral circuits for controlling and sensing the DRAM of semiconductor device <NUM> as described below in detail. In some embodiments, processor <NUM> includes a plurality of transistors <NUM> forming any suitable specialized processors and/or SoCs as described above in detail. In some embodiments, transistors <NUM> also form array of SRAM cells <NUM> used as, for example, cache and/or data buffer of semiconductor device <NUM>. For example, array of SRAM cells <NUM> may function as the internal instruction cache and/or data cache of processor <NUM>. Array of SRAM cells <NUM> can be distributed in a plurality of separate regions in first semiconductor structure <NUM>. Transistors <NUM> further form peripheral circuit <NUM>, i.e., any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of the DRAM including, but not limited to, an input/output buffer, a decoder (e.g., a row decoder and a column decoder), and a sense amplifier.

Transistors <NUM> can be formed "on" substrate <NUM>, in which the entirety or part of transistors <NUM> are formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of transistors <NUM>) can be formed in substrate <NUM> as well. Transistors <NUM> are high-speed with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.), according to some embodiments.

The first semiconductor structure <NUM> of semiconductor device <NUM> further includes an interconnect layer <NUM> above device layer <NUM> to transfer electrical signals to and from processor <NUM> and array of SRAM cells <NUM> and peripheral circuit <NUM>. Interconnect layer <NUM> can include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect access (via) contacts. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. Interconnect layer <NUM> can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the interconnect lines and via contacts can form. That is, interconnect layer <NUM> can include interconnect lines and via contacts in multiple ILD layers. The interconnect lines and via contacts in interconnect layer <NUM> can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, the devices in device layer <NUM> are electrically connected to one another through the interconnects in interconnect layer <NUM>. For example, array of SRAM cells <NUM> may be electrically connected to processor <NUM> through interconnect layer <NUM>.

As shown in <FIG>, first semiconductor structure <NUM> of semiconductor device <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and device layer <NUM> (including processor <NUM> and array of SRAM cells <NUM>). Bonding layer <NUM> includes a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of semiconductor device <NUM> also includes a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer <NUM> includes a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding. Bonding contacts <NUM> are in contact with bonding contacts <NUM> at bonding interface <NUM>, according to the claimed invention.

As described above, second semiconductor structure <NUM> is bonded on top of first semiconductor structure <NUM> in a face-to-face manner at bonding interface <NUM>. Bonding interface <NUM> is disposed between bonding layers <NUM> and <NUM> as a result of hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. Bonding interface <NUM> is the place at which bonding layers <NUM> and <NUM> are met and bonded. In practice, bonding interface <NUM> can be a layer with a certain thickness that includes the top surface of bonding layer <NUM> of first semiconductor structure <NUM> and the bottom surface of bonding layer <NUM> of second semiconductor structure <NUM>.

In some embodiments, second semiconductor structure <NUM> of semiconductor device <NUM> further includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in interconnect layer <NUM> also include local interconnects, such as bit line contacts and word line contacts. Interconnect layer <NUM> can further include one or more ILD layers in which the interconnect lines and via contacts can form. The interconnect lines and via contacts in interconnect layer <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

Second semiconductor structure <NUM> of semiconductor device <NUM> can further include a device layer <NUM> above interconnect layer <NUM> and bonding layer <NUM>. Device layer <NUM> includes an array of DRAM cells <NUM> above interconnect layer <NUM> and bonding layer <NUM>. In some embodiments, each DRAM cell <NUM> includes a DRAM selection transistor <NUM> and a capacitor <NUM>. DRAM cell <NUM> can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that DRAM cell <NUM> may be of any suitable configurations, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors <NUM> are formed "on" a semiconductor layer <NUM>, in which the entirety or part of DRAM selection transistors <NUM> are formed in semiconductor layer <NUM> (e.g., below the top surface of semiconductor layer <NUM>) and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of DRAM selection transistors <NUM>) can be formed in semiconductor layer <NUM> as well. In some embodiments, capacitors <NUM> are disposed below DRAM selection transistors <NUM>. Each capacitor <NUM> includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor <NUM>, according to some embodiments. Another node of each DRAM selection transistor <NUM> is electrically connected to a bit line <NUM> of DRAM, according to some embodiments. Another electrode of each capacitor <NUM> can be electrically connected to a common plate <NUM>, e.g., a common ground. It is understood that the structure and configuration of DRAM cell <NUM> are not limited to the example in <FIG> and may include any suitable structure and configuration. For example, capacitor <NUM> may be a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor.

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above device layer <NUM>. Semiconductor layer <NUM> can be above and in contact with array of DRAM cells <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which DRAM selection transistors <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions (e.g., as the sources and drains of DRAM selection transistors <NUM>).

As shown in <FIG>, second semiconductor structure <NUM> of semiconductor device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> can include interconnects, e.g., contact pads <NUM>, in one or more ILD layers. Pad-out interconnect layer <NUM> and interconnect layer <NUM> can be formed at opposite sides of semiconductor layer <NUM>. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between semiconductor device <NUM> and outside circuits, e.g., for pad-out purposes.

In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, processor <NUM>, array of SRAM cells <NUM>, and peripheral circuit <NUM> can be electrically connected to array of DRAM cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, processor <NUM>, array of SRAM cells <NUM>, and array of DRAM cells <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> is not part of the claimed invention but is useful for understanding it. <FIG> illustrates a cross-section of another exemplary semiconductor device <NUM>, according to some embodiments. As one example of semiconductor device <NUM> described above with respect to <FIG>, semiconductor device <NUM> is a bonded chip including a second semiconductor structure <NUM> and a first semiconductor structure <NUM> stacked over second semiconductor structure <NUM>. Similar to semiconductor device <NUM> described above in <FIG>, semiconductor device <NUM> represents an example of a bonded chip in which first semiconductor structure <NUM> including a processor and SRAM and second semiconductor structure <NUM> including DRAM are formed separately and bonded in a face-to-face manner at a bonding interface <NUM>. Different from semiconductor device <NUM> described above in <FIG> in which first semiconductor structure <NUM> including the processor and SRAM is below second semiconductor structure <NUM> including the DRAM, semiconductor device <NUM> in <FIG> includes first semiconductor structure <NUM> including the processor and SRAM disposed above second semiconductor structure <NUM> including the DRAM. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both semiconductor devices <NUM> and <NUM> may not be repeated below.

Second semiconductor structure <NUM> of semiconductor device <NUM> can include a substrate <NUM> and a device layer <NUM> above substrate <NUM>. Device layer <NUM> can include an array of DRAM cells <NUM> on substrate <NUM>. In some embodiments, each DRAM cell <NUM> includes a DRAM selection transistor <NUM> and a capacitor <NUM>. DRAM cell <NUM> can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that DRAM cell <NUM> may be of any suitable configuration, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors <NUM> are formed "on" substrate <NUM>, in which the entirety or part of DRAM selection transistors <NUM> are formed in substrate <NUM> and/or directly on substrate <NUM>. In some embodiments, capacitors <NUM> are disposed above DRAM selection transistors <NUM>. Each capacitor <NUM> includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor <NUM>, according to some embodiments. Another node of each DRAM selection transistor <NUM> is electrically connected to a bit line <NUM> of DRAM, according to some embodiments. Another electrode of each capacitor <NUM> can be electrically connected to a common plate <NUM>, e.g., a common ground. It is understood that the structure and configuration of DRAM cell <NUM> are not limited to the example in <FIG> and may include any suitable structure and configuration.

In some embodiments, second semiconductor structure <NUM> of semiconductor device <NUM> also includes an interconnect layer <NUM> above device layer <NUM> to transfer electrical signals to and from array of DRAM cells <NUM>. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer <NUM> also include local interconnects, such as bit line contacts and word line contacts. In some embodiments, second semiconductor structure <NUM> of semiconductor device <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and device layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>.

As shown in <FIG>, first semiconductor structure <NUM> of semiconductor device <NUM> includes another bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> are in contact with bonding contacts <NUM> at bonding interface <NUM>, according to some embodiments. In some embodiments, first semiconductor structure <NUM> of semiconductor device <NUM> also includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts.

First semiconductor structure <NUM> of semiconductor device <NUM> can further include a device layer <NUM> above interconnect layer <NUM> and bonding layer <NUM>. In some embodiments, device layer <NUM> includes a processor <NUM> above interconnect layer <NUM> and bonding layer <NUM>, and an array of SRAM cells <NUM> above interconnect layer <NUM> and bonding layer <NUM> and outside of processor <NUM>. In some embodiments, device layer <NUM> further includes a peripheral circuit <NUM> above interconnect layer <NUM> and bonding layer <NUM> and outside of processor <NUM>. For example, peripheral circuit <NUM> may be part or the entirety of the peripheral circuits for controlling and sensing array of DRAM cells <NUM>. In some embodiments, the devices in device layer <NUM> are electrically connected to one another through the interconnects in interconnect layer <NUM>. For example, array of SRAM cells <NUM> may be electrically connected to processor <NUM> through interconnect layer <NUM>.

In some embodiments, processor <NUM> includes a plurality of transistors <NUM> forming any suitable specialized processors and/or SoCs. Transistors <NUM> can be formed "on" a semiconductor layer <NUM>, in which the entirety or part of transistors <NUM> are formed in semiconductor layer <NUM> and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of transistors <NUM>) can be formed in semiconductor layer <NUM> as well. Transistors <NUM> can form array of SRAM cells <NUM> (and peripheral circuit <NUM> if any). Transistors <NUM> are high-speed with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.), according to some embodiments.

In some embodiments, first semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above device layer <NUM>. Semiconductor layer <NUM> can be above and in contact with processor <NUM> and array of SRAM cells <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which transistors <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions.

As shown in <FIG>, first semiconductor structure <NUM> of semiconductor device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> can include interconnects, e.g., contact pads <NUM>, in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between semiconductor device <NUM> and outside circuits, e.g., for pad-out purposes. In some embodiments, first semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, processor <NUM> and array of SRAM cells <NUM> (and peripheral circuit <NUM> if any) can also be electrically connected to array of DRAM cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, processor <NUM>, array of SRAM cells <NUM>, and array of DRAM cells <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrates a cross-section of still another exemplary semiconductor device <NUM>, according to an embodiment, which does not form part of the claimed invention but is useful for understanding the invention. Similar to semiconductor device <NUM> described above in <FIG>, semiconductor device <NUM> represents an example of a bonded chip including a first semiconductor structure <NUM> having a processor <NUM> and an array of SRAM cells <NUM>, and a second semiconductor structure <NUM> having an array of DRAM cells <NUM> above first semiconductor structure <NUM>. Different from semiconductor device <NUM> described above in <FIG> in which peripheral circuit <NUM> is in first semiconductor structure <NUM>, but not in second semiconductor structure <NUM>, peripheral circuits <NUM> are formed in second semiconductor structure <NUM> in which array of DRAM cells <NUM> are formed. Similar to semiconductor device <NUM> described above in <FIG>, first and second semiconductor structures <NUM> and <NUM> of semiconductor device <NUM> are bonded in a face-to-face manner at a bonding interface <NUM>, as shown in <FIG>. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both semiconductor devices <NUM> and <NUM> may not be repeated below.

First semiconductor structure <NUM> of semiconductor device <NUM> can include a device layer <NUM> above a substrate <NUM>. In some embodiments, device layer <NUM> includes processor <NUM> on substrate <NUM>, and array of SRAM cells <NUM> on substrate <NUM> and outside of processor <NUM>. In some embodiments, processor <NUM> includes a plurality of transistors <NUM> forming any suitable specialized processors and/or SoCs as described above in detail. In some embodiments, transistors <NUM> also form array of SRAM cells <NUM> used as, for example, cache and/or data buffer of semiconductor device <NUM>.

In some embodiments, first semiconductor structure <NUM> of semiconductor device <NUM> also includes an interconnect layer <NUM> above device layer <NUM> to transfer electrical signals to and from processor <NUM> and array of SRAM cells <NUM>. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, first semiconductor structure <NUM> of semiconductor device <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and device layer <NUM> (including processor <NUM> and array of SRAM cells <NUM>). Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of semiconductor device <NUM> can also include a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> are in contact with bonding contacts <NUM> at bonding interface <NUM>, according to some embodiments. In some embodiments, second semiconductor structure <NUM> of semiconductor device <NUM> also includes an interconnect layer <NUM> above bonding layer <NUM> to transfer electrical signals. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts.

Second semiconductor structure <NUM> of semiconductor device <NUM> can further include a device layer <NUM> above interconnect layer <NUM> and bonding layer <NUM>. In some embodiments, device layer <NUM> includes array of DRAM cells <NUM> above interconnect layer <NUM> and bonding layer <NUM>. In some embodiments, each DRAM cell <NUM> includes a DRAM selection transistor <NUM> and a capacitor <NUM>. DRAM cell <NUM> can be a 1T1C cell consisting of one transistor and one capacitor. It is understood that DRAM cell <NUM> may be of any suitable configurations, such as 2T1C cell, 3T1C cell, etc. In some embodiments, DRAM selection transistors <NUM> are formed "on" a semiconductor layer <NUM>, in which the entirety or part of DRAM selection transistors <NUM> are formed in semiconductor layer <NUM> (e.g., below the top surface of semiconductor layer <NUM>) and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of DRAM selection transistors <NUM>) can be formed in semiconductor layer <NUM> as well. In some embodiments, capacitors <NUM> are disposed below DRAM selection transistors <NUM>. Each capacitor <NUM> includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor <NUM>, according to some embodiments. Another node of each DRAM selection transistor <NUM> is electrically connected to a bit line <NUM> of DRAM, according to some embodiments. Another electrode of each capacitor <NUM> can be electrically connected to a common plate <NUM>, e.g., a common ground. It is understood that the structure and configuration of DRAM cell <NUM> are not limited to the example in <FIG> and may include any suitable structure and configuration.

In some embodiments, device layer <NUM> further includes peripheral circuits <NUM> above interconnect layer <NUM> and bonding layer <NUM> and outside of array of DRAM cells <NUM>. For example, peripheral circuits <NUM> may be part or the entirety of the peripheral circuits for controlling and sensing array of DRAM cells <NUM>. In some embodiments, peripheral circuits <NUM> include a plurality of transistors <NUM> forming any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of array of DRAM cells <NUM> including, but not limited to, an input/output buffer, a decoder (e.g., a row decoder and a column decoder), and a sense amplifier. Peripheral circuits <NUM> and array of DRAM cells <NUM> can be electrically connected through the interconnects of interconnect layer <NUM>.

In some embodiments, second semiconductor structure <NUM> further includes semiconductor layer <NUM> disposed above device layer <NUM>. Semiconductor layer <NUM> can be above and in contact with array of DRAM cells <NUM>. Semiconductor layer <NUM> can be a thinned substrate on which transistors <NUM> and DRAM selection transistors <NUM> are formed. In some embodiments, semiconductor layer <NUM> includes single-crystal silicon. In some embodiments, semiconductor layer <NUM> can include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable materials. Semiconductor layer <NUM> can also include isolation regions and doped regions.

<FIG> is not part of the claimed invention but is useful for understanding it. As shown in <FIG>, second semiconductor structure <NUM> of semiconductor device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> includes interconnects, e.g., contact pads <NUM>, in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between semiconductor device <NUM> and outside circuits, e.g., for pad-out purposes. In some embodiments, second semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, processor <NUM> and array of SRAM cells <NUM> can be electrically connected to array of DRAM cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, processor <NUM>, array of SRAM cells <NUM>, and array of DRAM cells <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> is not part of the claimed invention but is useful for understanding it. <FIG> illustrates a cross-section of yet another exemplary semiconductor device <NUM>, according to some embodiments. As one example of semiconductor device <NUM> described above with respect to <FIG>, semiconductor device <NUM> is a bonded chip including a second semiconductor structure <NUM> and a first semiconductor structure <NUM> stacked over second semiconductor structure <NUM>. Similar to semiconductor device <NUM> described above in <FIG>, semiconductor device <NUM> represents an example of a bonded chip in which first semiconductor structure <NUM> including a processor and SRAM and second semiconductor structure <NUM> including peripheral circuits and DRAM are formed separately and bonded in a face-to-face manner at a bonding interface <NUM>. Different from semiconductor device <NUM> described above in <FIG> in which first semiconductor structure <NUM> including the processor and SRAM is below second semiconductor structure <NUM> including the peripheral circuits and DRAM, semiconductor device <NUM> in <FIG> includes first semiconductor structure <NUM> including the processor and SRAM disposed above second semiconductor structure <NUM> including the peripheral circuits and DRAM. It is understood that the details of similar structures (e.g., materials, fabrication process, functions, etc.) in both semiconductor devices <NUM> and <NUM> may not be repeated below.

In some embodiments, device layer <NUM> further includes peripheral circuits <NUM> on substrate <NUM> and outside of array of DRAM cells <NUM>. For example, peripheral circuits <NUM> may be part or the entirety of the peripheral circuits for controlling and sensing array of DRAM cells <NUM>. In some embodiments, peripheral circuits <NUM> include a plurality of transistors <NUM> forming any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of array of DRAM cells <NUM> including, but not limited to, an input/output buffer, a decoder (e.g., a row decoder and a column decoder), and a sense amplifier.

In some embodiments, second semiconductor structure <NUM> of semiconductor device <NUM> also includes an interconnect layer <NUM> above device layer <NUM> to transfer electrical signals to and from array of DRAM cells <NUM>. Interconnect layer <NUM> can include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer <NUM> also include local interconnects, such as bit line contacts and word line contacts. Peripheral circuits <NUM> and array of DRAM cells <NUM> can be electrically connected through the interconnects of interconnect layer <NUM>. In some embodiments, second semiconductor structure <NUM> of semiconductor device <NUM> further includes a bonding layer <NUM> at bonding interface <NUM> and above interconnect layer <NUM> and device layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics surrounding and electrically isolating bonding contacts <NUM>.

First semiconductor structure <NUM> of semiconductor device <NUM> can further include a device layer <NUM> above interconnect layer <NUM> and bonding layer <NUM>. In some embodiments, device layer <NUM> includes a processor <NUM> above interconnect layer <NUM> and bonding layer <NUM>, and an array of SRAM cells <NUM> above interconnect layer <NUM> and bonding layer <NUM> and outside of processor <NUM>. In some embodiments, the devices in device layer <NUM> are electrically connected to one another through the interconnects in interconnect layer <NUM>. For example, array of SRAM cells <NUM> may be electrically connected to processor <NUM> through interconnect layer <NUM>.

In some embodiments, processor <NUM> includes a plurality of transistors <NUM> forming any suitable specialized processors and/or SoCs. Transistors <NUM> can be formed "on" a semiconductor layer <NUM>, in which the entirety or part of transistors <NUM> are formed in semiconductor layer <NUM> and/or directly on semiconductor layer <NUM>. Isolation regions (e.g., STIs) and doped regions (e.g., source regions and drain regions of transistors <NUM>) can be formed in semiconductor layer <NUM> as well. Transistors <NUM> can also form array of SRAM cells <NUM>. Transistors <NUM> are high-speed with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.), according to some embodiments.

As shown in <FIG>, first semiconductor structure <NUM> of semiconductor device <NUM> can further include a pad-out interconnect layer <NUM> above semiconductor layer <NUM>. Pad-out interconnect layer <NUM> includes interconnects, e.g., contact pads <NUM>, in one or more ILD layers. In some embodiments, the interconnects in pad-out interconnect layer <NUM> can transfer electrical signals between semiconductor device <NUM> and outside circuits, e.g., for pad-out purposes. In some embodiments, first semiconductor structure <NUM> further includes one or more contacts <NUM> extending through semiconductor layer <NUM> to electrically connect pad-out interconnect layer <NUM> and interconnect layers <NUM> and <NUM>. As a result, processor <NUM> and array of SRAM cells <NUM> can be electrically connected to array of DRAM cells <NUM> through interconnect layers <NUM> and <NUM> as well as bonding contacts <NUM> and <NUM>. Moreover, processor <NUM>, array of SRAM cells <NUM>, and array of DRAM cells <NUM> can be electrically connected to outside circuits through contacts <NUM> and pad-out interconnect layer <NUM>.

<FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having a processor, SRAM, and peripheral circuits, according to some embodiments. <FIG> illustrate a fabrication process for forming an exemplary semiconductor structure having DRAM and peripheral circuits, according to some embodiments. <FIG> and <FIG> illustrate a fabrication process for forming an exemplary semiconductor device, according to some embodiments. <FIG> illustrate a fabrication process for bonding and dicing an exemplary semiconductor structure, according to some embodiments. <FIG> illustrate a fabrication process for dicing and bonding an exemplary semiconductor structure, according to some embodiments. <FIG> is a flowchart of an exemplary method <NUM> for forming a semiconductor device, according to some embodiments. <FIG> is a flowchart of another exemplary method <NUM> for forming a semiconductor device, according to some embodiments. Examples of the semiconductor device depicted in <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> include semiconductor devices <NUM>, <NUM>, <NUM>, <NUM> depicted in <FIG>, <FIG>, <FIG>, and <FIG>, respectively. <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG> will be described together. It is understood that the operations shown in methods <NUM> and <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG> and <FIG>.

As depicted in <FIG>, a first semiconductor structure including a processor, an array of SRAM cells, a peripheral circuit, and a first bonding layer including a plurality of first bonding contacts is formed. As depicted in <FIG>, a second semiconductor structure including an array of DRAM cells, peripheral circuits, and a second bonding layer including a plurality of second bonding contacts is formed. As depicted in <FIG> and <FIG>, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. The first wafer can be a silicon wafer. In some embodiments, to form the plurality of first semiconductor structures, the processor and the array of SRAM cells are formed on the first wafer. In some embodiments, to form the processor and the array of SRAM cells, a plurality of transistors are formed on the first wafer. To form the plurality of first semiconductor structures, a peripheral circuit of the array of DRAM cells is also formed on the first wafer.

As illustrated in <FIG>, a plurality of first semiconductor structures <NUM> are formed on a first wafer <NUM>. First wafer <NUM> can include a plurality of shots separated by scribing lines. Each shot of first wafer <NUM> includes one or more first semiconductor structures <NUM>, according to some embodiments. <FIG> illustrate one example of the formation of first semiconductor structure <NUM>.

As illustrated in <FIG>, a plurality of transistors <NUM> are formed on a silicon substrate <NUM> (as part of first wafer <NUM>, e.g., a silicon wafer). Transistors <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of transistors <NUM>. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate <NUM> by wet/dry etch and thin film deposition. Transistors <NUM> can form a device layer <NUM> on silicon substrate <NUM>. In some embodiments, device layer <NUM> includes a processor <NUM>, an array of SRAM cells <NUM>, and a peripheral circuit <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first interconnect layer is formed above the processor and the array of SRAM cells. The first interconnect layer can include a first plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above device layer <NUM> including processor <NUM> and array of SRAM cells <NUM>. Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with device layer <NUM>. In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. Fabrication processes to form the interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a first bonding layer is formed above the first interconnect layer. The first bonding layer includes a plurality of first bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesion layer, and/or a seed layer before depositing the conductor.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a plurality of second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The second wafer can be a silicon wafer. In some embodiments, to form the plurality of second semiconductor structures, the array of DRAM cells are formed on the second wafer. In some embodiments, to form the array of DRAM cells, a plurality of transistors are formed on the second wafer, and a plurality of capacitors are formed above and in contact with at least some of the transistors. In some embodiments, to form the plurality of second semiconductor structures, a peripheral circuit of the array of DRAM cells is also formed on the second wafer.

As illustrated in <FIG>, a plurality of second semiconductor structures <NUM> are formed on a second wafer <NUM>. Second wafer <NUM> can include a plurality of shots separated by scribing lines. Each shot of second wafer <NUM> includes one or more second semiconductor structures <NUM>, according to some embodiments. <FIG> illustrate one example of the formation of second semiconductor structure <NUM>.

As illustrated in <FIG>, a plurality of transistors <NUM> are formed on a silicon substrate <NUM> (as part of second wafer <NUM>, e.g., a silicon wafer). Transistors <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of transistors <NUM>. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate <NUM> by wet/dry etch and thin film deposition.

As illustrated in <FIG>, a plurality of capacitors <NUM> are formed above and in contact with at least some of transistors <NUM>, i.e., the DRAM selection transistors. Each capacitor <NUM> can be patterned by photography to be aligned with a respective DRAM selection transistor to form a 1T1C memory cell, for example, by electrically connecting one electrode of capacitor <NUM> with one node of the respective DRAM selection transistor. In some embodiments, bit lines <NUM> and common plates <NUM> are formed as well for electrically connecting the DRAM selection transistors and capacitors <NUM>. Capacitors <NUM> can be formed by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. A device layer <NUM> including an array of DRAM cells <NUM> (each having a DRAM selection transistor and capacitor <NUM>) and peripheral circuits <NUM> (having transistors <NUM> other than the DRAM selection transistors) is thereby formed.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second interconnect layer is formed above the array of DRAM cells. The second interconnect layer can include a second plurality of interconnects in one or more ILD layers. As illustrated in <FIG>, an interconnect layer <NUM> can be formed above array of DRAM cells <NUM>. Interconnect layer <NUM> can include interconnects of MEOL and/or BEOL in a plurality of ILD layers to make electrical connections with array of DRAM cells <NUM> (and peripheral circuits <NUM> if any). In some embodiments, interconnect layer <NUM> includes multiple ILD layers and interconnects therein formed in multiple processes. For example, the interconnects in interconnect layers <NUM> can include conductive materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Fabrication processes to form the interconnects can also include photolithography, CMP, wet/dry etch, or any other suitable processes. The ILD layers can include dielectric materials deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects illustrated in <FIG> can be collectively referred to as interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a second bonding layer is formed above the second interconnect layer. The second bonding layer includes a plurality of second bonding contacts. As illustrated in <FIG>, a bonding layer <NUM> is formed above interconnect layer <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> surrounded by dielectrics. In some embodiments, a dielectric layer is deposited on the top surface of interconnect layer <NUM> by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Bonding contacts <NUM> then can be formed through the dielectric layer and in contact with the interconnects in interconnect layer <NUM> by first patterning contact holes through the dielectric layer using patterning process (e.g., photolithography and dry/wet etch of dielectric materials in the dielectric layer). The contact holes can be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing an adhesion (glue) layer, a barrier layer, and/or a seed layer before depositing the conductor.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonding can be hybrid bonding. The second semiconductor structure is above the first semiconductor structure after the bonding. In some embodiments, the first semiconductor structure is above the second semiconductor structure after the bonding.

As illustrated in <FIG>, first wafer <NUM> and second wafer <NUM> are bonded in a face-to-face manner, such that at least one of first semiconductor structures <NUM> is bonded to at least one of second semiconductor structures <NUM> at a bonding interface <NUM>. Although first wafer <NUM> is above second wafer <NUM> after the bonding as shown in <FIG>, it is understood that second wafer <NUM> is above first wafer <NUM> after the bonding. <FIG> illustrates one example of the formation of bonded first and second semiconductor structures <NUM> and <NUM>.

As illustrated in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., device layer <NUM> including array of DRAM cells <NUM>) are flipped upside down. Bonding layer <NUM> facing down is bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming a bonding interface <NUM> (as shown in <FIG>). In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. Although not shown in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., device layer <NUM> including processor <NUM>, array of SRAM cells <NUM>, and peripheral circuit <NUM>) can be flipped upside down, and bonding layer <NUM> facing down can be bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming bonding interface <NUM>. After the bonding, bonding contacts <NUM> in bonding layer <NUM> and bonding contacts <NUM> in bonding layer <NUM> are aligned and in contact with one another, such that device layer <NUM> (e.g., array of DRAM cells <NUM> therein) can be electrically connected to device layer <NUM> (e.g., processor <NUM>, array of SRAM cells <NUM>, and peripheral circuit <NUM> therein). It is understood that in the bonded chip, device layer <NUM> (e.g., processor <NUM>, array of SRAM cells <NUM>, and peripheral circuit <NUM> therein) may be either above or below device layer <NUM> (e.g., array of DRAM cells <NUM> therein). Nevertheless, bonding interface <NUM> can be formed between device layer <NUM> (e.g., processor <NUM>, array of SRAM cells <NUM>, and peripheral circuit <NUM> therein) and device layer <NUM> (e.g., array of DRAM cells <NUM> therein) after the bonding as illustrated in <FIG>. It is understood that although device layer <NUM> in <FIG> does not include peripheral circuits <NUM> (as shown in <FIG>), in some embodiments which do not form part of the claimed invention, peripheral circuits <NUM> are included as part of device layer <NUM> in the bonded chip. It is further understood that although device layer <NUM> in <FIG> includes peripheral circuits <NUM>, in some embodiments which do not form part of the claimed invention, peripheral circuits <NUM> may not be included as part of device layer <NUM> in the bonded chip.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first wafer or the second wafer is thinned to form a semiconductor layer. In some embodiments, the first wafer of the first semiconductor structure, which is above the second wafer of the second semiconductor structure after the bonding, is thinned to form the semiconductor layer. In some embodiments, the second wafer of the second semiconductor structure, which is above the first wafer of the first semiconductor structure after the bonding, is thinned to form the semiconductor layer.

As illustrated in <FIG>, the substrate at the top of the bonded chip (e.g., silicon substrate <NUM> as shown in <FIG>) is thinned, so that the thinned top substrate can serve as a semiconductor layer <NUM>, for example, a single-crystal silicon layer. The thickness of the thinned substrate can be between about <NUM> and about <NUM>, such as between <NUM> and <NUM>, or between about <NUM> and about <NUM>, such as between <NUM> and <NUM>. Silicon substrate <NUM> can be thinned by processes including, but not limited to, wafer grinding, dry etch, wet etch, CMP, any other suitable processes, or any combination thereof. It is understood that when silicon substrate <NUM> is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning silicon substrate <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a pad-out interconnect layer is formed above the semiconductor layer. As illustrated in <FIG>, a pad-out interconnect layer <NUM> is formed above semiconductor layer <NUM> (the thinned top substrate). Pad-out interconnect layer <NUM> can include interconnects, such as pad contacts <NUM>, formed in one or more ILD layers. Pad contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after the bonding and thinning, contacts <NUM> are formed extending vertically through semiconductor layer <NUM>, for example by wet/dry etch followed by depositing conductive materials. Contacts <NUM> can be in contact with the interconnects in pad-out interconnect layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the bonded first and second wafers are diced into a plurality of dies. At least one of the dies includes the bonded first and second semiconductor structures. As illustrated in <FIG>, bonded first and second wafers <NUM> and <NUM> (as shown in <FIG>) are diced into a plurality of dies <NUM>. At least one of dies <NUM> includes bonded first and second semiconductor structures <NUM> and <NUM>. In some embodiments, each shot of bonded first and second wafers <NUM> and <NUM> is cut from bonded first and second wafers <NUM> and <NUM> along the scribing lines using wafer laser dicing and/or mechanical dicing techniques, thereby becoming respective die <NUM>. Die <NUM> can include bonded first and second semiconductor structures <NUM> and <NUM>, for example, the bonded structure as shown in <FIG>.

Instead of packaging scheme based on wafer-level bonding before dicing as described above with respect to <FIG> and <FIG>, <FIG> and <FIG> illustrate another packaging scheme based on die-level bonding after dicing, according to some embodiments. Operations <NUM>, <NUM>, and <NUM> of method <NUM> in <FIG> are described above with respect to method <NUM> in <FIG> and thus, are not repeated. As illustrated in <FIG>, a plurality of first semiconductor structures <NUM> are formed on a first wafer <NUM>. First wafer <NUM> can include a plurality of shots separated by scribing lines. Each shot of first wafer <NUM> includes one or more first semiconductor structures <NUM>, according to some embodiments. <FIG> illustrate one example of the formation of first semiconductor structure <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first wafer is diced into a plurality of first dies, such that at least one of the first dies includes the at least one of the first semiconductor structures. As illustrated in <FIG>, first wafer <NUM> (as shown in <FIG>) is diced into a plurality of dies <NUM>, such that at least one die <NUM> includes first semiconductor structure <NUM>. In some embodiments, each shot of first wafer <NUM> is cut from first wafer <NUM> along the scribing lines using wafer laser dicing and/or mechanical dicing techniques, thereby becoming respective die <NUM>. Die <NUM> can include first semiconductor structure <NUM>, for example, the structure as shown in <FIG>.

Operations <NUM>, <NUM>, and <NUM> of method <NUM> in <FIG> are described above with respect to method <NUM> in <FIG> and thus, are not repeated. As illustrated in <FIG>, a plurality of second semiconductor structures <NUM> are formed on a second wafer <NUM>. Second wafer <NUM> can include a plurality of shots separated by scribing lines. Each shot of second wafer <NUM> includes one or more second semiconductor structures <NUM>, according to some embodiments. <FIG> illustrate one example of the formation of second semiconductor structure <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the second wafer is diced into a plurality of second dies, such that at least one of the second dies includes the at least one of the second semiconductor structures. As illustrated in <FIG>, second wafer <NUM> (as shown in <FIG>) is diced into a plurality of dies <NUM>, such that at least one die <NUM> includes second semiconductor structure <NUM>. In some embodiments, each shot of second wafer <NUM> is cut from second wafer <NUM> along the scribing lines using wafer laser dicing and/or mechanical dicing techniques, thereby becoming respective die <NUM>. Die <NUM> can include second semiconductor structure <NUM>, for example, the structure as shown in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first die and the second die are bonded in a face-to-face manner, such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. As illustrated in <FIG>, die <NUM> including first semiconductor structure <NUM> and die <NUM> including second semiconductor structure <NUM> are bonded in a face-to-face manner, such that first semiconductor structure <NUM> is bonded to second semiconductor structure <NUM> at a bonding interface <NUM>. Although first semiconductor structure <NUM> is above second semiconductor structure <NUM> after the bonding as shown in <FIG>, it is understood that second semiconductor structure <NUM> may be above first semiconductor structure <NUM> after the bonding in some embodiments. <FIG> illustrates one example of the formation of bonded first and second semiconductor structures <NUM> and <NUM>.

Claim 1:
A semiconductor device (<NUM>, <NUM>), comprising:
a first semiconductor structure (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprising a processor (<NUM>, <NUM>, <NUM>), an array of static random-access memory, SRAM, cells (<NUM>, <NUM>, <NUM>), and a first bonding layer (<NUM>, <NUM>) comprising a plurality of first bonding contacts (<NUM>, <NUM>);
a second semiconductor structure (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprising an array of dynamic random-access memory, DRAM, cells (<NUM>, <NUM>) and a second bonding layer (<NUM>, <NUM>) comprising a plurality of second bonding contacts (<NUM>, <NUM>), wherein the first semiconductor structure (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprises a peripheral circuit (<NUM>, <NUM>) of the array of DRAM cells (<NUM>, <NUM>), wherein transistors (<NUM>) form the peripheral circuit (<NUM>, <NUM>) including an input/output buffer, a decoder, and a sense amplifier and an interconnect layer (<NUM>) vertically between the first bonding layer (<NUM>, <NUM>) and the processor (<NUM>, <NUM>, <NUM>) above a device layer (<NUM>) to transfer electrical signals to and from the processor (<NUM>, <NUM>, <NUM>), the array of SRAM cells (<NUM>, <NUM>, <NUM>) and the peripheral circuit (<NUM>, <NUM>), wherein the device layer (<NUM>) comprises the processor (<NUM>, <NUM>, <NUM>), an array of SRAM cells (<NUM>, <NUM>, <NUM>) and the peripheral circuit (<NUM>, <NUM>); and
a bonding interface (<NUM>, <NUM>, <NUM>, <NUM>) between the first bonding layer (<NUM>, <NUM>) and the second bonding layer (<NUM>, <NUM>), wherein the first bonding contacts (<NUM>, <NUM>) are in contact with the second bonding contacts (<NUM>, <NUM>) at the bonding interface (<NUM>, <NUM>, <NUM>, <NUM>), wherein the first semiconductor structure (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprises:
a substrate (<NUM>, <NUM>)
the processor (<NUM>, <NUM>, <NUM>) on the substrate (<NUM>, <NUM>);
the array of SRAM cells (<NUM>, <NUM>, <NUM>) on the substrate (<NUM>, <NUM>, <NUM>) and outside of the processor (<NUM>, <NUM>, <NUM>); and
the first bonding layer (<NUM>, <NUM>) above the processor (<NUM>, <NUM>, <NUM>) and the array of SRAM cells (<NUM>, <NUM>, <NUM>).