Patent Description:
A storage device may store data on behalf of an application executing at a computing device. During execution, the application may issue one or more commands to the storage device that may alter the data.

The above information disclosed in this background section is only for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not constitute prior art.

<CIT> relates to sequential data optimized sub-regions in storage devices. In particular this document discloses that varying granularities are stored permanently in a non-volatile memory array. Multiple granularities can be used for regions of a storage device.

<CIT> discloses a memory access request comprising a given memory access granularity. The memory is accessed at the requested granularity.

In various embodiments, described herein include systems, methods, and apparatuses related to sending commands to storage devices.

A method includes storing, at a computing device, access granularity criteria associated with a memory area. The method further includes receiving a memory operation request requesting access to a first portion of the memory area at the first access granularity. The method further includes in response to the memory operation request satisfying the access granularity criteria, sending, from the computing device, a command to a storage device based on the memory operation request.

A computer readable storage device storing instructions executable by a processor to perform operations including storing, at a computing device, access granularity criteria associated with a memory area. The operations further include receiving a memory operation request requesting access to a first portion of the memory area at the first access granularity. The operations further include, in response to the memory operation request satisfying the access granularity criteria, sending, from the computing device, a command to a storage device based on the memory operation request.

A system includes a storage device and a computing device. The computing device is configured to store access granularity criteria associated with a memory area of the storage device. The computing device is further configured to receive a memory operation request requesting access to a first portion of the memory area at the first access granularity. The computing device is further configured to, in response to the memory operation request satisfying the access granularity criteria, send a command to the storage device based on the memory operation request.

The above-mentioned aspects and other aspects of the present techniques will be better understood when the present application is read in view of the following figures in which like numbers indicate similar or identical elements:.

The details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the description below.

Various embodiments of the present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments are shown. Indeed, the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The term "or" is used herein in both the alternative and conjunctive sense, unless otherwise indicated. The terms "illustrative" and "example" are used to be examples with no indication of quality level. Arrows in each of the figures depict bi-directional data flow and/or bi-directional data flow capabilities. The terms "path," "pathway" and "route" are used interchangeably herein.

Embodiments of the present disclosure may be implemented in various ways, including as computer program products that comprise articles of manufacture. A computer program product may include a non-transitory computer-readable storage medium storing applications, programs, program components, scripts, source code, program code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and/or the like (also referred to herein as executable instructions, instructions for execution, computer program products, program code, and/or similar terms used herein interchangeably). Such non-transitory computer-readable storage media include all computer-readable media (including volatile and non-volatile media).

In one embodiment, a non-volatile computer-readable storage medium may include a floppy disk, flexible disk, hard disk, solid-state storage (SSS) (for example a solid-state drive (SSD)), solid state card (SSC), solid state component (SSM), enterprise flash drive, magnetic tape, or any other non-transitory magnetic medium, and/or the like. A non-volatile computer-readable storage medium may also include a punch card, paper tape, optical mark sheet (or any other physical medium with patterns of holes or other optically recognizable indicia), compact disc read only memory (CD-ROM), compact disc-rewritable (CD-RW), digital versatile disc (DVD), Blu-ray disc (BD), any other non-transitory optical medium, and/or the like. Such a non-volatile computer-readable storage medium may also include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (for example Serial, NAND, NOR, and/or the like), multimedia memory cards (MMC), secure digital (SD) memory cards, SmartMedia cards, CompactFlash (CF) cards, Memory Sticks, and/or the like. Further, a non-volatile computer-readable storage medium may also include conductive-bridging random access memory (CBRAM), phase-change random access memory (PRAM), ferroelectric random-access memory (FeRAM), non-volatile random-access memory (NVRAM), magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), Silicon-Oxide-Nitride-Oxide-Silicon memory (SONOS), floating junction gate random access memory (FJG RAM), Millipede memory, racetrack memory, and/or the like.

In one embodiment, a volatile computer-readable storage medium may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), fast page mode dynamic random access memory (FPM DRAM), extended data-out dynamic random access memory (EDO DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), double data rate type two synchronous dynamic random access memory (DDR2 SDRAM), double data rate type three synchronous dynamic random access memory (DDR3 SDRAM), Rambus dynamic random access memory (RDRAM), Twin Transistor RAM (TTRAM), Thyristor RAM (T-RAM), Zero-capacitor (Z-RAM), Rambus in-line memory component (RIMM), dual in-line memory component (DIMM), single in-line memory component (SIMM), video random access memory (VRAM), cache memory (including various levels), flash memory, register memory, and/or the like. It will be appreciated that where embodiments are described to use a computer-readable storage medium, other types of computer-readable storage media may be substituted for or used in addition to the computer-readable storage media described above.

As should be appreciated, various embodiments of the present disclosure may also be implemented as methods, apparatus, systems, computing devices, computing entities, and/or the like. As such, embodiments of the present disclosure may take the form of an apparatus, system, computing device, computing entity, and/or the like executing instructions stored on a computer-readable storage medium to perform certain steps or operations. Thus, embodiments of the present disclosure may also take the form of an entirely hardware embodiment, an entirely computer program product embodiment, and/or an embodiment that comprises combination of computer program products and hardware performing certain steps or operations.

Embodiments of the present disclosure are described below with reference to block diagrams and flowchart illustrations. Thus, it should be understood that each block of the block diagrams and flowchart illustrations may be implemented in the form of a computer program product, an entirely hardware embodiment, a combination of hardware and computer program products, and/or apparatus, systems, computing devices, computing entities, and/or the like carrying out instructions, operations, steps, and similar words used interchangeably (for example the executable instructions, instructions for execution, program code, and/or the like) on a computer-readable storage medium for execution. For example, retrieval, loading, and execution of code may be performed sequentially such that one instruction is retrieved, loaded, and executed at a time. In some example embodiments, retrieval, loading, and/or execution may be performed in parallel such that multiple instructions are retrieved, loaded, and/or executed together. Thus, such embodiments can produce specifically-configured machines performing the steps or operations specified in the block diagrams and flowchart illustrations. Accordingly, the block diagrams and flowchart illustrations support various combinations of embodiments for performing the specified instructions, operations, or steps.

Systems and methods for sending commands to a storage device are disclosed. These systems and methods may selectively send requested commands to a storage device be based on access granularity in order to maintain a coherent view of data stored at the storage device.

A storage device may support accesses of varying granularity. For example, the storage device may support block level (e.g., <NUM> kilobytes (KB), <NUM> bytes (B), etc.) and byte level access. Other granularities may be supported by the storage device and more than two granularities may be supported. Accessing a memory area at different granularities may result in corrupted data. For example, different granularity access paths may have different caching systems. Accordingly, altering a particular memory address using one granularity access may cause coherency issues if another access path has cached the memory address. The disclosure provides systems and methods for controlling memory accesses based on granularity of the access (or an associated factor, such as an access path associated with a granularity). Accordingly, the disclosed systems and methods may provide coherent access to a storage device at various granularities.

Referring to <FIG>, a system <NUM> for sending commands to a storage device is shown. The system <NUM> may support more than one access granularity for memory commands. The system <NUM> includes a computing device <NUM> and a storage device <NUM>. The computing device <NUM> includes a processor <NUM> and a memory device <NUM>.

The processor <NUM> includes a central processor unit (CPU), a graphics processor unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), another type of processor, or any combination thereof. The processor <NUM> may be implemented with a complex instruction set computer (CISC) architecture, a reduced instruction set computer (RISC) architecture, another type of computer architecture, or any combination thereof.

The memory device <NUM> includes volatile memory, non-volatile memory, another type of memory, or any combination thereof. Examples of volatile memory include dynamic random access memory (DRAM), static random access memory (SRAM), resistive random access memory (ReRAM), etc. Examples of non-volatile memory include read only memory (ROM), programmable read only memory (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, hard disk drive, etc..

The computing device <NUM> may correspond to personal computer, a mobile phone device, a server computer, another type of computer, or any combination thereof. The storage device <NUM> includes volatile memory, non-volatile memory, another type of memory, or any combination thereof. In some implementations, the storage device <NUM> is a component of the computing device <NUM>.

The computing device <NUM> is connected, directly or indirectly, to the storage device <NUM>. An indirect connection refers to a connection that includes an intermediate device, whereas an indirect connection refers to a connection that does not include an intermediate device. A connection may be wireless or wired. As will be discussed further herein, In a particular example, the computing device <NUM> communicate with the storage device <NUM> using compute express link (CXL) protocol (or another cache coherent protocol) over a peripheral component interconnect express (PCIe) link (or other link).

The memory device <NUM> stores access granularity criteria <NUM> associated with a memory area. The access granularity criteria <NUM> may be an association between the memory area and a first access granularity (e.g., 4KB, 64B, etc.). The access granularity criteria <NUM> may be placed in the memory device <NUM> by an application executed by the processor <NUM>, by an operating system executed by the processor <NUM>, by other software executed by the processor <NUM>, or by another source. The memory area may correspond to a physical memory space (e.g., address range) of the storage device <NUM> or to a virtualized address space that may be translated to addresses of the storage device <NUM>. In some examples, the memory area corresponds to a file or a region of a file. The access granularity criteria <NUM> may be explicitly between the memory area and the first access granularity or may be between the memory area and an attribute correlated with the first access granularity. For example, the access granularity criteria <NUM> may between the memory area and an access path, protocol, etc. that correlates to the first access granularity. In a particular example, the access granularity criteria <NUM> corresponds to lock indicating that the memory area is to be accessed exclusively using the first granularity (or corresponding attribute, such as an access path, protocol, etc.). In another example, the memory area may include a physical address range of the storage device <NUM> that may be mapped to more than one virtual memory address used by the computing device <NUM>. Each of the more than one virtual memory addresses may be utilized by the computing device <NUM> to access the physical address range at a different granularity. The access granularity criteria <NUM> between the memory area and the first access granularity may correspond to a lock on one or more of the more than one virtual memory addresses.

In operation, the processor <NUM> receives a memory operation request <NUM> (e.g., a read command, a write command, or another type of memory access command). The memory operation request <NUM> may be received from an application executing at the processor <NUM> in some examples. The memory operation request <NUM> indicates a first portion of the memory area. Based on (e.g., in response to) the memory operation request <NUM>, the processor <NUM> may determine that a memory operation request <NUM> satisfies (e.g., has an access granularity indicated as permitted for the memory area, is associated with an access protocol that is permitted to access the memory area, targets a virtual memory address that is associated with the memory area and is unlocked, targets a virtual memory address that is not locked, etc.) the access granularity criteria <NUM>. Based on the memory operation request <NUM> satisfying the access granularity criteria <NUM>, the processor <NUM> may issue a command <NUM> that is based on the memory operation request <NUM> to the storage device. The command <NUM> may simply be the memory operation request <NUM> or may correspond to a translation of the memory operation request <NUM>. The command <NUM> corresponds to a memory operation (e.g., a read, write, etc.) targeting the first portion of the memory area at the first granularity. Accordingly, commands that satisfy the stored access granularity criteria <NUM> may be passed to the storage device <NUM> by the processor <NUM>.

In a particular example, the memory operation request <NUM> indicates that the memory area is to be accessed using a non-volatile memory express (NVMe) protocol over CXL. io (e.g., accesses according to this protocol may be associated with a 4KB granularity). The access granularity criteria <NUM> may correspond to a lock that indicates the memory area (e.g., a range of physical addresses on the storage device <NUM>) is locked to NVMe protocol (e.g., 4KB granularity) access). The processor <NUM> may confirm that the access granularity criteria <NUM> is satisfied by a first access granularity (e.g., the NVMe protocol command type of the memory operation request <NUM>) of the memory operation request <NUM>, and based on the determination, issue the command <NUM> to the storage device <NUM>. In this example, the command <NUM> may correspond to an NVMe command.

In another example, the access granularity criteria <NUM> may indicate that a virtual memory address range utilized by a load/store access path (e.g., a CXL. mem path) to access a physical address range of the storage device at a 64B granularity is unlocked. The memory operation request <NUM> may target a virtual memory address in the unlocked virtual memory address range. Accordingly, the processor <NUM> may pass the command <NUM> on to the storage device <NUM>. The command <NUM> may include the virtual memory address or a translation of the virtual memory address. Alternatively, the access granularity criteria <NUM> may not include information regarding the virtual memory address range utilized by the load/store access path (e.g., may not include a lock for this range). In this case too, the processor <NUM> may consider the virtual memory address to satisfy the access granularity criteria.

Controlling access to the storage device <NUM> based on requested access granularity (or associated attribute, such as access path/protocol/etc.) may provide a mechanism for coherent access to the storage device <NUM> at different granularities.

<FIG> illustrates an example in which the system <NUM> rejects a memory operation request based on access granularity. In operation, the processor <NUM> receives a second memory operation request <NUM> (e.g., a read command, a write command, or another type of memory access command). The second memory operation request <NUM> may be received from an application executing at the processor <NUM> in some examples. The second memory operation request <NUM> indicates a second portion of the memory area. Based on (e.g., in response to) the second memory operation request <NUM>, the processor <NUM> may determine that a second access granularity of the second memory operation request <NUM> fails to satisfy the access granularity criteria <NUM> (e.g., has a different access granularity than is not permitted to access the memory area, is associated with a protocol or access path that is not permitted to access the memory area, targets a virtual address that is associated with the memory area and is locked, etc.). Based on the second memory operation request <NUM> failing to satisfy the access granularity criteria <NUM>, the processor <NUM> may issue an indication of rejection <NUM> (e.g., to an application that generated the second memory operation request <NUM>). Accordingly, requests that do not satisfy the stored access granularity criteria <NUM> are trc rejected by the processor <NUM>.

In a particular example, the second memory operation request <NUM> indicates that the memory area is to be accessed using a load or store operation over CXL. mem (e.g., accesses according to this protocol may be associated with a 64B granularity). The access granularity criteria <NUM> may correspond to a lock that indicates the memory area (e.g., a range of physical addresses on the storage device <NUM>) is locked to NVMe protocol (e.g., 4KB granularity) access). The processor <NUM> may confirm that the access granularity criteria <NUM> is not satisfied by the second memory operation request <NUM> (e.g., the load/store command type of the second memory operation request <NUM>), and based on the determination, issue the indication of rejection <NUM>.

In another example, the access granularity criteria <NUM> may indicate that a virtual memory address range utilized by an NVMe access path to access a physical address range of the storage device at a block granularity is locked. The second memory operation request <NUM> may target a virtual memory address in the locked virtual memory address range. Accordingly, the processor <NUM> issues the rejection <NUM>.

Rejecting access to a memory location in the storage device <NUM> based on requested access granularity (or associated attribute, such as access path, protocol, targeted virtual address, etc.) may prevent access to a memory location by different access paths that have different caching systems. Accordingly, coherency of data stored in the storage device <NUM> may be maintained.

<FIG> illustrates an example in which the system <NUM> updates an access granularity criteria. In operation, the processor <NUM> receives a request <NUM> to update the access granularity criteria associated with the memory area. For example, the request <NUM> may indicate a new permitted access granularity, a new disallowed access granularity, a new permitted access path or protocol (e.g., associated with a particular access granularity), a new disallowed access path or protocol, a new unlocked virtual address (associated with a particular access granularity), a new locked virtual address, or a combination thereof. The request <NUM> may be received from an application or an operating system executing at the processor <NUM>. The processor <NUM> stores updated access granularity criteria <NUM> in the memory device <NUM>. The updated access granularity criteria <NUM> is associated with the memory area.

<FIG> illustrates that the system <NUM> may send commands to the storage device <NUM> based on the updated access granularity criteria <NUM>. In the illustrated example, the computing device <NUM> receives the second memory operation request <NUM>. Based on the second memory operation request <NUM> satisfying the updated access granularity criteria <NUM>, the processor <NUM> issues a second command <NUM> to the storage device. Determination by the processor <NUM> that the second memory operation request <NUM> satisfies the updated access granularity criteria <NUM> may follow the same process as determination by the processor <NUM> that the memory operation request <NUM> satisfies the access granularity criteria <NUM> described with respect to <FIG>.

Accordingly, the system <NUM> may switch between supported access granularities for a particular memory area in the storage device <NUM>. In some implementations, once the system <NUM> locks the particular memory area to a particular access granularity, memory access requests at other granularities are disallowed until the lock is removed (e.g., by an application executing at the processor <NUM>).

The system <NUM> of <FIG> may include various components other than those shown. For example, the computing device <NUM> may include additional processors, communications interfaces, memory devices, output devices, etc. Further, the storage device <NUM> may include a processor, storage media, communications interfaces, etc..

Referring to <FIG> a system <NUM> that controls commands sent to a CXL storage device based on access granularity is shown. The system <NUM> may correspond to the system <NUM> described above. The system <NUM> includes a computing device <NUM> and a CXL storage device.

The computing device <NUM> executes an application <NUM> and an operating system <NUM>. The computing device <NUM> may correspond to the computing device <NUM> of <FIG>. The computing device <NUM> may include a personal computer, a mobile device, such as a smart phone device, a server computer, or other type of computing device. The computing device <NUM> executes (e.g., at a processor, such as the processor <NUM>) an application <NUM> and an operating system <NUM>. The application <NUM> may correspond to any computing application that accesses memory. In some implementations, the application <NUM> includes a deep learning recommendation model (DLRM) application. DLRM applications may access relatively large amounts of data (e.g., terabytes). Accordingly, data accesses at a first, relatively large, granularity (e.g., <NUM> B or 4KB blocks) may be efficient. However, some functions of the DLRM application may depend on a relatively small amount of data. Accessing the relatively small amount of data using the first access granularity may result in movement of more data that the DLRM application will use for some functions. Accordingly, data accesses at a second, relatively smaller, granularity (e.g., 64B) may be more efficient for some functions.

The operating system <NUM> manages memory spaces accessible to the application <NUM>. Managing the memory spaces may include translating between virtual addresses used by the application <NUM> and addresses recognized by the CXL storage device <NUM> (e.g., physical addresses or further virtual addresses). In some implementations, the operating system <NUM> sends commands of a first access granularity (e.g., NVMe commands) to the CXL storage device <NUM> over a first protocol (e.g., CXL. io) and sends commands of a second access granularity (e.g., memory load/store commands) over a second protocol (e.g., CXL. Managing the memory spaces may further include placing locks (e.g., access criteria) on portions of memory (e.g., memory ranges, objects (such as files), etc.). In some instances, a locks may restrict all access to a portion of memory, restrict access to a particular access granularity, restrict access to a particular access protocol (e.g., NVMe, load/store, CXL. io, etc.), restrict access to another criteria, or a combination thereof.

The computing device includes a PCIe connector <NUM>. The PCIe connector <NUM> may include a u. <NUM> connector, an m. <NUM> connector, or another type of connector.

The CXL storage device <NUM> includes a PCIe connector <NUM>, an FPGA <NUM>, and a PCIe storage device <NUM>. The PCIe storage device <NUM> may include a solid state drive, hard disk drive, other storage device, or a combination thereof configured to operate over PCIe. The CXL storage device <NUM> is configured to provide access to the PCIe storage device <NUM> over the PCIe connector <NUM> at more than one access granularity. The PCIe connector <NUM> may include a u. <NUM> connector, an m. <NUM> connector, or another type of connector.

The FPGA <NUM> includes a CXL endpoint (EP) intellectual property (IP) block <NUM>. The CXL EP IP <NUM> block <NUM> is configured to manage CXL protocol messages exchanged between the computing device <NUM> and the CXL storage device <NUM>.

The FPGA <NUM> further includes a cache <NUM>. The cache <NUM> may include DRAM, SRAM, another type of memory, or a combination thereof. The cache <NUM> is configured to cache data retrieved from the PCIe storage device <NUM> at a first granularity (e.g., 512B or 4KB blocks) to provide access at a second granularity (e.g., 64B granularity). The cache <NUM> may further be configured to store data to be written to the PCIe storage device <NUM> at the second granularity. This data may eventually be written to the PCIe storage device <NUM> at the first granularity.

The FPGA <NUM> further includes a NVMe request generator IP block <NUM>. The NVMe request generator IP block <NUM> is configured to generate NVMe requests based on signals from the CXL EP IP block <NUM>. These NVMe requests are sent to the PCIe storage device <NUM>. For example, the CXL EP IP block <NUM> may instruct the NVMe request generator IP block <NUM> to generate an NVMe request for a block of data in response to a cache miss at the cache <NUM>.

The FPGA <NUM> further includes a CXL-to-PCI IP block <NUM>. The CXL-to-PCI IP block <NUM> is configured to convert messages received over CXL. io (e.g., NVMe over CXL messages) to PCIe messages (e.g., NVMe over PCIe) based on signals from the CXL EP IP block <NUM>. For example, the CXL-to-PCI IP block <NUM> may extract a NVMe read request from a CXL. io messages and encapsulate the NVMe read request in a PCIe message for transmission to the PCIe storage device <NUM>.

The FPGA <NUM> further includes a PCIe IP block <NUM>. The PCIe IP block <NUM> is configured to exchange PCIe messages with the PCIe storage device <NUM>. In some examples, the PCIe IP block includes a u. <NUM> connector, an m. <NUM> connector, or another type of PCIe connector.

In a first example operation, the application <NUM> sends a write command targeting a virtual address to the operating system <NUM>. The operating system <NUM> translates the virtual address to a translated address associated with the CXL storage device <NUM>, generates an NVMe command targeting the translated address, and sends the NVMe command to the CXL storage device <NUM> over the PCIe connector <NUM> using the CXL. io protocol. The CXL storage device <NUM> receives the NVMe command at the PCIe connector <NUM>. The CXL EP IP block <NUM> forwards the NVMe over CXL. io message to the CXL-to-PCI IP block <NUM>. The CXL-to-PCI IP block <NUM> converts the NVMe over CXL. io message to an NVMe over PCIe message and sends this to the PCIe IP block <NUM> for transmission to the PCIe storage device <NUM>. Based on the NVMe command, the PCIe storage device <NUM> writes data to the PCIe storage device at the first granularity (e.g., 512B or 4KB block).

In a second example operation, the application <NUM> sends a read command targeting a virtual address to the operating system <NUM>. The operating system <NUM> translates the virtual address to a translated address associated with the CXL storage device <NUM>, generates an NVMe command targeting the translated address, and sends the NVMe command to the CXL storage device <NUM> over the PCIe connector <NUM> using the CXL. io protocol. The CXL storage device <NUM> receives the NVMe command at the PCIe connector <NUM>. The CXL EP IP block <NUM> forwards the NVMe over CXL. io message to the CXL-to-PCI IP block <NUM>. The CXL-to-PCI IP block <NUM> converts the NVMe over CXL. io message to an NVMe over PCIe message and sends this to the PCIe IP block <NUM> for transmission to the PCIe storage device <NUM>. Based on the NVMe command, the PCIe storage device <NUM> returns data to the computing device <NUM> at the first granularity.

In a third example operation, the application <NUM> sends a store command targeting a virtual address to the operating system <NUM>. The operating system <NUM> translates the virtual address to a translated address associated with the CXL storage device <NUM>, generates a memory store command targeting the translated address, and sends the memory store command to the CXL storage device <NUM> over the PCIe connector <NUM> using the CXL. mem protocol. The CXL storage device <NUM> receives the memory store command at the PCIe connector <NUM>. The CXL EP IP block <NUM> determines whether the translated address is cached in the cache <NUM>. In response to the cache <NUM> caching the translated address, the CXL EP IP block <NUM> is configured to overwrite a cache entry for the translated address at a second access granularity (e.g., 64B). In response to a cache miss for the translated address, the CXL EP IP block <NUM> is configured to store data in the cache <NUM> in a new entry. The CXL EP IP block <NUM> is configured to trigger writes to the NVMe request generator IP block <NUM> to generate a NVMe request to write data to the PCIe storage device <NUM> at the first granularity according to a cache eviction policy. The PCIe IP block <NUM> transfers the NVMe request to the PCIe storage device <NUM> and the PCIe storage device <NUM> writes the data at the first granularity to storage media of the PCIe storage device <NUM>.

In a fourth example operation, the application <NUM> sends a load command targeting a virtual address to the operating system <NUM>. The operating system <NUM> translates the virtual address to a translated address associated with the CXL storage device <NUM>, generates a memory load command targeting the translated address, and sends the memory load to the CXL storage device <NUM> over the PCIe connector <NUM> using the CXL. mem protocol. The CXL storage device <NUM> receives the memory load command at the PCIe connector <NUM>. The CXL EP IP block <NUM> determines whether the translated address is cached in the cache <NUM>. In response to the cache <NUM> caching the translated address, the CXL EP IP block <NUM> is configured to return a cache entry for the translated address at a second access granularity (e.g., 64B) to the computing device <NUM>. In response to a cache miss for the translated address, the CXL EP IP block <NUM> is configured to the NVMe request generator IP block <NUM> to generate a NVMe request to requesting data at the translated address from the PCIe storage device <NUM> at the first granularity. The PCIe IP block <NUM> transfers the NVMe request to the PCIe storage device <NUM> and the PCIe storage device <NUM> returns the data at the first granularity to the FPGA <NUM> for storage in the cache <NUM>. The CXL EP IP block <NUM> then returns an entry of the cache <NUM> at the second granularity to the computing device <NUM>.

Accordingly, the CXL storage device <NUM> supports access at more than one access granularity despite an underlying storage device supporting one access granularity by implementing a first access path that operates at a native access granularity of the PCIe storage device <NUM> (e.g., CXL. io) and a second access path (e.g., CXL. mem) that utilizes a cache to cache data from the underlying storage device at the first access granularity so that the data can be accessed and manipulated at the second access granularity with fewer transactions sent to the underlying storage device. Since different caching structures are used in each access path, the computing device <NUM> may receive conflicting views of data stored in the PCIe storage device <NUM> if a particular physical address of the PCIe storage device <NUM> were to be accessed over both paths simultaneously. In order to prevent an incoherent view of data stored at the PCIe storage device <NUM>, the computing device <NUM> manages accesses to the CXL storage device <NUM> based on access granularity criteria, as described herein.

It should be noted that the system <NUM> is provided for illustration purposes and may be modified or replaced with other systems that provide accesses to a storage device at varying access granularities. For example, the computing device <NUM> and the CXL storage device <NUM> may communicate over a protocol other than PCIe, such as Ethernet. As another example, the CXL storage device <NUM> may be replaced with a storage device that supports other multi-protocol access. Accordingly, the computing device <NUM> may send access requests over protocols other than CXL. io and CXL. As another example, the FPGA <NUM> may be replaced by an ASIC, a central processor unit, or other type of processor. In some implementations, functionality of the FPGA <NUM> is implemented by a controller (e.g., an ASIC or other processing device) of the PCIe storage device <NUM>. Accordingly, the computing device <NUM> may communicate directly with the PCIe storage device <NUM> over a PCIe connection. In some implementations, the PCIe storage device <NUM> may be replaced with another type of storage device, such as a serial ATA (SATA), universal serial bus, serial attached SCSI (SAS), or other type of storage device. Further, the storage device may operate according to a protocol other than NVMe. As with other diagrams illustrated and described herein, additional components than those illustrated may be included in examples.

<FIG> is a diagram illustrating abstraction of memory address space in a system <NUM> for sending commands to a storage device. In some examples, the system <NUM> corresponds to the system <NUM> or to the system <NUM>. The system <NUM> includes a computing device <NUM>, such as the computing device <NUM> or the computing device <NUM>. The computing device <NUM> executes an application <NUM> and an operating system <NUM>. The application <NUM> accesses one or more memory spaces managed by the operating system <NUM>. The application <NUM> may correspond to the application <NUM> and the operating system <NUM> may correspond to the operating system <NUM>.

The system <NUM> further includes a memory device <NUM> and a storage device <NUM>. The memory spaces managed by the operating system <NUM> may correspond to physical storage space in the memory device <NUM>, in the storage device <NUM>, or a combination thereof. The memory device <NUM> may include a volatile memory device, such as a DRAM, SRAM, etc. The storage device <NUM> may include non-volatile memory, such as a solid state drive, a hard disc drive, another type of non-volatile memory or a combination thereof. The storage device <NUM> may also include volatile memory. In some examples, the memory device <NUM>, the storage device <NUM>, or a combination thereof correspond to components of the CXL storage device <NUM>. The storage device <NUM> may correspond to the PCIe storage device <NUM>.

The operating system <NUM> provides a file system <NUM> space for first access granularity memory operations to the application <NUM>. Further, the operating system <NUM> provides a virtual memory address range <NUM> to the application <NUM> for second granularity memory access operations.

The operating system <NUM> is configured to map the virtual memory <NUM> to a memory pool including a first portion <NUM> and a second portion <NUM>. For example, the operating system <NUM> may receive a memory access request (e.g., a load or store operation) from the application <NUM>. The memory access request may identify a virtual address in the virtual memory <NUM>. The operating system <NUM> may then translate the virtual address to a translated address in the memory pool and output a command including the translated address to the storage device <NUM> (e.g., the CXL storage device <NUM> or the storage device <NUM>).

Further, the operating system <NUM> is configured to map the file system <NUM> to a storage pool <NUM>. For example, the operating system <NUM> may receive a memory access request (e.g., a read or write request) from the application <NUM>. The memory access request may identify a virtual address or object in the file system <NUM>. The operating system <NUM> may then translate the virtual address or address to a translated address in the storage pool <NUM> and output a command including the translated address to the storage device <NUM> (e.g., the CXL storage device <NUM> or the storage device <NUM>).

The operating system <NUM> is configured to send memory accesses for the first portion <NUM> of the memory pool to the memory device <NUM> and memory accesses for the second portion <NUM> of the memory pool to the storage device <NUM>. The storage device <NUM> is configured to map the second portion <NUM> of the memory pool to physical addresses in the storage device <NUM>. The storage device <NUM> is further configured to map the storage pool <NUM> to physical addresses in the storage device <NUM>. Accordingly, physical addresses in the storage device <NUM> may be accessible by both a first path through the file system <NUM> and a second path through the virtual memory <NUM>. The application <NUM> may issue memory access requests of a first granularity to the file system <NUM> and issue memory access requests of a second granularity to the virtual memory <NUM>.

In operation, the application <NUM> may issue a command to write a file <NUM> to the file system <NUM>. The operating system <NUM> may then issue commands (e.g., NVMe commands) to write the file to the storage pool <NUM> at first storage pool location <NUM>, second storage pool location <NUM>, at third storage pool location <NUM>, and at fourth storage pool location <NUM>. The storage device <NUM> may translate the storage pool locations <NUM>, <NUM>, <NUM>, <NUM> to physical addresses in the storage device <NUM> and write the file to the physical addresses.

The application <NUM> may further issue a memory mapping command <NUM> to the operating system <NUM> to map a file in the file system <NUM> to the virtual memory <NUM> at virtual memory address range <NUM>. Based on the memory mapping command <NUM>, the operating system <NUM> places the file at a file mapped virtual memory address range <NUM> in the virtual memory <NUM> and instructs the storage device <NUM> to place the file <NUM> into the second portion <NUM> of the memory pool at first location <NUM>, second location <NUM>, third location <NUM>, and fourth location <NUM>. Rather than moving the data in the storage device <NUM>, the storage device <NUM> may map the physical addresses of the file <NUM> in the storage device <NUM> to the locations <NUM>, <NUM>, <NUM>, <NUM> in the second portion <NUM> of the memory pool. In order to prevent an incoherent view of the file <NUM>, the operating system <NUM> may place a lock on virtual addresses in the file system <NUM> corresponding to the file <NUM>. Because memory accesses through the virtual memory <NUM> and the file system <NUM> use different access granularities, the lock may be considered an access granularity criteria. Based on the lock, the operating system <NUM> may deny memory access requests directed to the file <NUM> in the file system <NUM>. Accordingly, the system <NUM> may provide a consistent view of the file <NUM> by employing access granularity based control of memory accesses.

In some implementations, the operating system <NUM> may create mappings between the locations <NUM>, <NUM>, <NUM>, <NUM> and the physical address range in the storage device <NUM> in response to the memory mapping command <NUM> with no intervening commands. In other implementations, the operating system <NUM> may create mappings between the locations <NUM>, <NUM>, <NUM>, <NUM> as memory access commands are received from the application <NUM> for corresponding portions of the file <NUM>. For example, in response to an access request from the application <NUM> for a virtual memory address in the address range <NUM>, the operating system <NUM> may add a first portion of the file <NUM> to the first location <NUM>. Waiting to add portions of the file <NUM> to the memory pool may reduce overhead associated with creating and maintaining mappings (e.g., page tables) between the memory pool and the storage device <NUM>.

The operating system <NUM> may release the lock based on a command from the application <NUM>. In some implementations, releasing the lock on the file <NUM> in the file system <NUM> may include placing a lock on the virtual memory address range <NUM>. Releasing the lock may further include the operating system <NUM> issuing a command to the storage device <NUM> (e.g., the CXL storage device <NUM> or the storage device <NUM>) to flush cache (e.g., evict) entries associated with the virtual memory address range <NUM> to the storage device <NUM>. For example, the operating system <NUM> may issue a command to the CXL EP IP block <NUM> to flush entries of the cache <NUM> corresponding to the memory locations <NUM>, <NUM>, <NUM>, <NUM> to the PCIe storage device <NUM>. Accordingly, the CXL EP IP block <NUM> may instruct the NVMe request generator IP block <NUM> to generate one or more NVMe requests to write the entries of the cache to the PCIe storage device <NUM> (e.g., at block granularity).

Referring to <FIG>, a method <NUM> of sending commands to a storage device is shown. The method <NUM> may be performed by a computing device, such as the computing device <NUM>, by the computing device <NUM>, or the computing device <NUM>. The method <NUM> includes storing access granularity criteria associated with a memory area, at <NUM>. For example, the computing device <NUM> (e.g., the processor <NUM> of the computing device <NUM>) may store access granularity criteria <NUM> associated with a memory area in the memory device <NUM>. The access granularity criteria <NUM> may include a lock on a memory object (e.g., a file), a memory address (e.g., a virtual address or a physical memory address of the storage device <NUM>), or a memory range (e.g., a virtual memory address range or a physical memory address range of the storage device <NUM>). The memory object, memory address, or memory range may be associated with accessing data at the storage device <NUM> at a particular access granularity (e.g., over a particular access path, such as CXL. mem, associated with a particular access granularity). The lock may prevent access to particular physical addresses of the storage device <NUM> at the particular access granularity. The access granularity criteria <NUM> may correspond to an association between a memory object, a memory address, or a memory address range and an access granularity or a characteristic associated with an access granularity (such as an access path (e.g., CXL. mem) or access protocol (e.g., NVMe or memory load/store). The association may indicate that the access granularity is allowed or disallowed access to the memory object, memory address, or memory address range.

As another example, the operating system <NUM> may store a lock for a particular memory object, memory address, or memory address range associated with accessing a physical address of the PCIe storage device <NUM> using a block based NVMe commands or may store a lock for a particular memory object, memory address, or memory address range associated with accessing the physical address of the PCIe storage device <NUM> using byte addressable memory/load store commands.

As another example, the operating system <NUM> may store a lock preventing access to the file <NUM> in the file system <NUM>. Accordingly, block level access to the file may be disabled. Alternatively, the operating system <NUM> may store a lock preventing access to the virtual memory address range <NUM>. Accordingly, byte level access to the file may be disabled.

The method <NUM> further includes receiving a memory operation request requesting access to a first portion of the memory area at a first access granularity, at <NUM>. For example, the processor <NUM> may receive the memory operation request <NUM> requesting access to a first portion of the memory area. The memory operation request <NUM> may explicitly indicate a requested access granularity or implicitly indicate the requested access granularity (e.g., based on an indicated memory address, memory object, memory range, access protocol, access path, etc.).

As another example, the application <NUM> may issue a memory operation command to the operating system <NUM>. The memory operation command may include an address associated with using the CXL. mem path (e.g., byte level granularity) or CXL. io path (e.g., block level granularity) to access data stored at the PCIe storage device <NUM>.

As another example, the application <NUM> may issue a memory operation command to the operating system <NUM>. The memory operation command may include an address of the file system <NUM> (e.g., virtual addresses used for block level access of data on the storage device <NUM>) or an address in the virtual memory <NUM> (virtual addresses used for byte level access of data on the storage device <NUM>).

The method <NUM> further includes, in response to the memory operation request satisfying the access granularity criteria, sending a command to a storage device based on the memory operation request, at <NUM>. For example, the processor <NUM> may send the command <NUM> in response to the memory operation request <NUM> satisfying the access granularity criteria <NUM> associated with the memory area. To illustrate, the processor <NUM> may send the command <NUM> in response to the access granularity criteria <NUM> indicating that an address targeted by the memory operation request <NUM> is unlocked (e.g., by including an explicit indication that the address is unlocked or by not including an indication that the address is locked) or in response to an access granularity or associated characteristic of the memory operation request <NUM> corresponding to a permitted access granularity or associated characteristic for the memory area, as indicated by the access granularity criteria <NUM>.

As another example, the operating system <NUM> may issue a command to the CXL storage device <NUM> over CXL. mem or CXL. io in response to determining that the target address of a request from the application <NUM> is unlocked.

As another example, the operating system <NUM> may issue a command to the storage device <NUM> in response to determining that the target address of a request from the application <NUM> is unlocked.

Thus, the method <NUM> may selectively issue memory commands to a storage device based on access granularity criteria. Accordingly, the method <NUM> may be utilized in a system that supports multiple access granularities for accesses to a storage device in order to present a coherent view of data in the storage device. In some implementations, a storage device, such as the CXL storage device <NUM>, may perform the method <NUM> to selectively issue commands to another storage device (e.g., the PCIe storage device <NUM>). For example, the CXL EP IP block <NUM> of the FPGA <NUM> may be configured to perform the method <NUM>.

Referring to <FIG>, a method <NUM> of selectively sending or rejecting commands to a storage device is shown. The method <NUM> may be performed by a computing device, such as the computing device <NUM>, the computing device <NUM>, or the computing device <NUM>. Further the method <NUM> may be performed by a storage device that manages access to another storage device (e.g., by the CXL storage device <NUM>).

The method <NUM> includes receiving a memory operation request requesting access to a first portion of a memory area, at <NUM>. For example, the processor <NUM> may receive the memory operation request <NUM> or a second memory operation request <NUM> (e.g., from an application executing at the processor <NUM>). The requests <NUM>, <NUM> may include a memory load request, a memory store request, a write request (e.g., NVMe write), a read request (e.g., NVMe read), another type of memory access, or a combination thereof. The requests <NUM>, <NUM> may target a memory area (e.g., a physical memory range) of the storage device <NUM>.

The method <NUM> further includes determining whether the memory operation request satisfies access granularity criteria, at <NUM>. For example, the processor <NUM> may determine whether the memory operation request <NUM> or the memory operation request <NUM> satisfies the access granularity criteria <NUM> associated with the memory area. This determination may include determining whether the requests <NUM>, <NUM> target a locked (or unlocked) memory address, memory address range, memory object, etc., as indicated by the access granularity criteria <NUM>. The determination may include determining whether an access granularity or associated characteristic (e.g., access path, access protocol, etc.) of the requests <NUM>, <NUM> satisfies an association stored in the access granularity criteria <NUM>. The access granularity criteria <NUM> may indicate allowed accesses, disallowed accesses, or a combination thereof.

The method <NUM> further includes sending a command to a storage device based on the memory operation request in response to the memory operation request satisfying the access granularity criteria, at <NUM>. For example, the processor <NUM> may send the command <NUM> to the storage device <NUM> in response to the memory operation request <NUM> satisfying the access granularity criteria <NUM>. The command may correspond to a translation of the memory operation request <NUM>. For example, the command <NUM> may include a translation of an address indicated by the memory operation request <NUM>, the command <NUM> may be translated into a different protocol compared to the memory operation request <NUM>, the command <NUM> may encapsulate the memory operation request <NUM>, or a combination thereof.

The method <NUM> further includes outputting an indication of rejection in response to the memory operation request failing to satisfy the access granularity criteria, at <NUM>. For example, the processor <NUM> outputs the indication of rejection <NUM> in response to the second memory operation request <NUM> failing to satisfy the access granularity criteria <NUM>. The indication of rejection <NUM> may be output to an application executing at the processor <NUM>. In some implementations, the indication of rejection <NUM> corresponds to an error message or to an error flag.

Thus, the method <NUM> selectively sends send memory commands or rejections based on access granularity criteria. Accordingly, The method <NUM> may present a coherent view of data stored at a storage device that supports multiple access granularities (e.g., over different access paths).

Referring to <FIG>, a method <NUM> of mapping a memory area to a second space is shown. The method <NUM> may be performed by a computing device, such as the computing device <NUM>, the computing device <NUM>, or the computing device <NUM>. Further the method <NUM> may be performed by a storage device that manages access to another storage device (e.g., by the CXL storage device <NUM>).

The method <NUM> includes mapping a memory area to a first space associated with first access granularity, at <NUM>. For example, the operating system <NUM> may place the file <NUM> in the file system <NUM> and map the file <NUM> in the file system <NUM> to storage pool locations <NUM>, <NUM>, <NUM>, <NUM>. The storage pool locations <NUM>, <NUM>, <NUM>, <NUM> may be mapped (e.g., by the operating system <NUM> or by the storage device <NUM>, such as the CXL storage device <NUM>) to physical addresses in the storage device <NUM> (e.g., memory area). The location of the file <NUM> in the file system <NUM> or the storage pool locations <NUM>, <NUM>, <NUM>, <NUM> may correspond to the first space. Accessing the file <NUM> through the file system <NUM> is associated with a first access granularity (e.g., 512B or 5KB blocks).

In another example, the operating system <NUM> may map virtual addresses associated with CXL. mem access to a physical address range of the PCIe storage device <NUM> at 64B granularity.

The method <NUM> further includes receiving a request to map the memory area to a second space associated with a second access granularity, at <NUM>. For example, the operating system <NUM> may receive the memory mapping command <NUM> from the application <NUM>. The memory mapping command <NUM> may request that the file <NUM> be placed into the virtual memory <NUM>. The virtual memory <NUM> is associated with a second access granularity (e.g., 64B).

In another example, the operating system <NUM> may receive a request to map the physical address range of the PCIe storage device <NUM> to virtual addresses associated with CXL. io access at 512B or 4KB block granularity.

The method <NUM> further includes imitating a cache flush, at <NUM>. For example, the operating system <NUM> may flush any caches of data stored at the file system <NUM> maintained by the computing device <NUM>, the storage device <NUM>, or the storage device <NUM>.

In another example the operating system <NUM> may instruct the CXL EP IP block <NUM> to flush entries associated with the physical address range in the cache <NUM> to the PCIe storage device <NUM>.

The method <NUM> further includes mapping the memory area to the second space associated with the second access granularity. For example, the operating system <NUM> may map the address range <NUM> in the virtual memory <NUM> to memory pool locations <NUM>, <NUM>, <NUM>, <NUM> that are mapped to the physical address range of the storage device <NUM>.

In another example, the operating system <NUM> maps the physical address range of the PCIe storage device <NUM> to virtual addresses associated with CXL. io access at 512B or 4KB block granularity.

Thus, the method <NUM> may flush caches associated with one access granularity in response based on a request to access the data at another access granularity. It should be noted that more caches in an access path may be flushed than shown in the drawings. For example, the computing device <NUM>, the computing device <NUM>, or the computing device <NUM> may maintain one or more caches associated with one or more access granularities and these may be flushed based on requests to access data at a different access granularity. Similarly, the storage device <NUM>, the CXL storage device <NUM>, the PCIe storage device <NUM>, or the storage device <NUM> may include additional caching mechanisms than are illustrated. A caching mechanism associated with one access granularity may be flushed in response to a request to access data at a different access granularity.

Referring to <FIG>, a computing device <NUM> is device including a processor <NUM> and a computer readable storage device <NUM> is shown. The computer readable storage device <NUM> may include non-volatile memory, volatile memory, an optical storage device, another type of storage device, or a combination thereof. The computer readable storage device <NUM> stores access granularity based control instructions <NUM> that are executable by the processor <NUM> to perform one or more of the methods or operations described herein with respect to <FIG>. A similar computer readable storage device may store instructions to program an FPGA to perform one or more of the operations described herein.

In some examples, X corresponds to Y based on X matching Y. For example, a first ID may be determined to correspond to a second ID that matches (e.g., has a same value as) the first ID. In other examples, X correspond to Y based on X being associated with (e.g., linked to) Y. For example, X may be associated to Y by a mapping data structure.

Certain embodiments may be implemented in one or a combination of hardware, firmware, and software. Other embodiments may also be implemented as instructions stored on a computer-readable storage device, which may be read and executed by at least one processor to perform the operations described herein. A computer-readable storage device may include any non-transitory memory mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a computer-readable storage device may include read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash-memory devices, and other storage devices and media.

As used within this document, the term "communicate" is intended to include transmitting, or receiving, or both transmitting and receiving. This may be particularly useful in claims when describing the organization of data that is being transmitted by one device and received by another, but only the functionality of one of those devices is required to infringe the claim. Similarly, the bidirectional exchange of data between two devices (both devices transmit and receive during the exchange) may be described as 'communicating', when only the functionality of one of those devices is being claimed. The term "communicating" as used herein with respect to a wireless communication signal includes transmitting the wireless communication signal and/or receiving the wireless communication signal. For example, a wireless communication unit, which is capable of communicating a wireless communication signal, may include a wireless transmitter to transmit the wireless communication signal to at least one other wireless communication unit, and/or a wireless communication receiver to receive the wireless communication signal from at least one other wireless communication unit.

Some embodiments may be used in conjunction with various devices and systems, for example, a Personal Computer (PC), a desktop computer, a mobile computer, a laptop computer, a notebook computer, a tablet computer, a server computer, a handheld computer, a handheld device, a Personal Digital Assistant (PDA) device, a handheld PDA device, an on-board device, an off-board device, a hybrid device, a vehicular device, a non-vehicular device, a mobile or portable device, a consumer device, a non-mobile or non-portable device, a wireless communication station, a wireless communication device, a wireless Access Point (AP), a wired or wireless router, a wired or wireless modem, a video device, an audio device, an audio-video (A/V) device, a wired or wireless network, a wireless area network, a Wireless Video Area Network (WVAN), a Local Area Network (LAN), a Wireless LAN (WLAN), a Personal Area Network (PAN), a Wireless PAN (WPAN), and the like.

Some embodiments may be used in conjunction with one way and/or two-way radio communication systems, cellular radio-telephone communication systems, a mobile phone, a cellular telephone, a wireless telephone, a Personal Communication Systems (PCS) device, a PDA device which incorporates a wireless communication device, a mobile or portable Global Positioning System (GPS) device, a device which incorporates a GPS receiver or transceiver or chip, a device which incorporates an radio frequency identification (RFID) element or chip, a Multiple Input Multiple Output (MIMO) transceiver or device, a Single Input Multiple Output (SIMO) transceiver or device, a Multiple Input Single Output (MISO) transceiver or device, a device having one or more internal antennas and/or external antennas, Digital Video Broadcast (DVB) devices or systems, multi-standard radio devices or systems, a wired or wireless handheld device, e.g., a Smartphone, a Wireless Application Protocol (WAP) device, or the like.

Some embodiments may be used in conjunction with one or more types of wireless communication signals and/or systems following one or more wireless communication protocols, for example, Radio Frequency (RF), Infrared (IR), Frequency-Division Multiplexing (FDM), Orthogonal FDM (OFDM), Time-Division Multiplexing (TDM), Time-Division Multiple Access (TDMA), Extended TDMA (E-TDMA), General Packet Radio Service (GPRS), extended GPRS, Code-Division Multiple Access (CDMA), Wideband CDMA (WCDMA), CDMA <NUM>, single-carrier CDMA, multi-carrier CDMA, Multi-Carrier Modulation (MDM), Discrete Multi-Tone (DMT), BluetoothTM, Global Positioning System (GPS), Wi-Fi, Wi-Max, ZigBeeTM, Ultra-Wideband (UWB), Global System for Mobile communication (GSM), <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, Fifth Generation (<NUM>) mobile networks, 3GPP, Long Term Evolution (LTE), LTE advanced, Enhanced Data rates for GSM Evolution (EDGE), or the like. Other embodiments may be used in various other devices, systems, and/or networks.

Although an example processing system has been described above, embodiments of the subject matter and the functional operations described herein can be implemented in other types of digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.

Embodiments of the subject matter and the operations described herein can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described herein can be implemented as one or more computer programs, i.e., one or more components of computer program instructions, encoded on computer storage medium for execution by, or to control the operation of, information/data processing apparatus. Alternatively, or in addition, the program instructions can be encoded on an artificially-generated propagated signal, for example a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information/data for transmission to suitable receiver apparatus for execution by an information/data processing apparatus. The computer storage medium can also be, or be included in, one or more separate physical components or media (for example multiple CDs, disks, or other storage devices).

The operations described herein can be implemented as operations performed by an information/data processing apparatus on information/data stored on one or more computer-readable storage devices or received from other sources.

The apparatus can include special purpose logic circuitry, for example an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, for example code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of them.

A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a component, component, subroutine, object, or other unit suitable for use in a computing environment. A program can be stored in a portion of a file that holds other programs or information/data (for example one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (for example files that store one or more components, sub-programs, or portions of code).

The processes and logic flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input information/data and generating output. Generally, a processor will receive instructions and information/data from a read-only memory or a random access memory or both. Elements of a computer are a processor for performing actions in accordance with instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive information/data from or transfer information/data to, or both, one or more mass storage devices for storing data, for example magnetic, magneto-optical disks, or optical disks. Devices suitable for storing computer program instructions and information/data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, for example EPROM, EEPROM, and flash memory devices; magnetic disks, for example internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

To provide for interaction with a user, embodiments of the subject matter described herein can be implemented on a computer having a display device, for example a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information/data to the user and a keyboard and a pointing device, for example a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, for example visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input.

Embodiments of the subject matter described herein can be implemented in a computing system that includes a back-end component, for example as an information/data server, or that includes a middleware component, for example an application server, or that includes a front-end component, for example a client computer having a graphical user interface or a web browser through which a user can interact with an embodiment of the subject matter described herein, or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital information/data communication, for example a communication network. Examples of communication networks include a local area network ("LAN") and a wide area network ("WAN"), an inter-network (for example the Internet), and peer-to-peer networks (for example ad hoc peer-to-peer networks).

In some embodiments, a server transmits information/data (for example an HTML page) to a client device (for example for purposes of displaying information/data to and receiving user input from a user interacting with the client device). Information/data generated at the client device (for example a result of the user interaction) can be received from the client device at the server.

While this specification contains many specific embodiment details, these should not be construed as limitations on the scope of any embodiment or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

Claim 1:
A method comprising:
storing (<NUM>), at a computing device (<NUM>), access granularity criteria (<NUM>) associated with a memory area;
receiving (<NUM>) a memory operation request (<NUM>) requesting access to a first portion of the memory area at a first access granularity;
in response to the memory operation request (<NUM>) satisfying the access granularity criteria (<NUM>), sending (<NUM>), from the computing device (<NUM>), a command (<NUM>) to a storage device (<NUM>) based on the memory operation request (<NUM>);
receiving (<NUM>) a second memory operation request (<NUM>) requesting access to a second portion of the memory area at a second access granularity different from the first access granularity; and
outputting (<NUM>), based on the access granularity criteria (<NUM>), an indication (<NUM>) that the second memory operation request (<NUM>) is rejected.