Patent Description:
Embodiments of the invention relate generally to a display apparatus.

With the rapid development of the field of displays that visually express various pieces of electric signal information, various display apparatuses having excellent characteristics such as being lightweight, being thinner, and having low power consumption have been introduced.

Display apparatuses may include liquid-crystal display apparatuses that use light from a backlight unit without spontaneously emitting light or light-emitting display apparatuses that include display elements emitting light. A light-emitting display apparatus may include display elements including an emission layer.

<CIT> discloses a display apparatus. <CIT> discloses a display device.

Devices constructed according to illustrative implementations of the invention are capable of preventing a parasitic capacitance between a sensing line and a neighboring electrode (e.g., a first electrode of a light-emitting diode) of a display device, to thereby improve the operability of the display device.

One or more embodiments include a display apparatus, and more particularly, include a structure regarding a light-emitting display apparatus.

According to an aspect, there is provided a display apparatus as set out in claim <NUM>. Additional features are set out in claims <NUM> to <NUM>.

It is to be understood that both the foregoing general description and the following detailed description are illustrative and explanatory and are intended to provide further explanation of the invention as claimed.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate illustrative embodiments of the invention, and together with the description serve to explain the inventive concepts.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the invention. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments. Further, various embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concepts.

Unless otherwise specified, the illustrated embodiments are to be understood as providing illustrative features of varying detail of some ways in which the inventive concepts may be implemented in practice.

When an embodiment may be implemented differently, a specific process order may be performed differently from the described order.

Further, the x-axis, the y-axis, and the z-axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.

Thus, the term "below" can encompass both an orientation of above and below.

Various embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized embodiments and/or intermediate structures. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing.

<FIG> is a perspective view of a display apparatus DV according to an embodiment that is constructed according to principles of the invention, <FIG> is a cross-sectional view of the display apparatus DV taken along line II-II' in <FIG> according to an embodiment, and <FIG> is a view of respective portions of a color conversion-transmission layer of <FIG>.

Referring to <FIG>, the display apparatus DV may include a display area DA and a non-display area NDA outside the display area DA. The display apparatus DV may display an image through an array of a plurality of pixels two-dimensionally arranged on an x-y plane.

Each pixel is a region that may emit light of a preset color. The display apparatus DV may display an image by using pieces of light emitted from the pixels. As an example, each pixel may emit red, green, or blue light.

The non-display area NDA is a region in which an image is not displayed and may surround the display area DA entirely. A driver or a main power line may be arranged in the non-display area NDA, the driver or the main power line being for providing electric signals or power to the pixels. A pad may be included in the non-display area NDA, the pad being a region to which electronic elements or a printed circuit board may be electrically connected.

As shown in <FIG>, the display area DA may have a polygonal shape including a quadrangle. As an example, the display area DA may have a rectangular shape in which a horizontal length thereof is greater than a vertical length thereof, have a rectangular shape in which a horizontal length thereof is less than a vertical length thereof, or have a square shape. Alternatively, the display area DA may have various shapes such as an elliptical shape or a circular shape.

In an embodiment, the display apparatus DV may include a light-emitting panel <NUM> and a color panel <NUM> that are stacked in a thickness direction (e.g. a z-direction). Referring to <FIG>, the light-emitting panel <NUM> may include first to third pixel circuits PC1, PC2, and PC3 and first to third light-emitting diodes LED1, LED2, and LED3 respectively connected thereto, the first to third pixel circuits PC1, PC2, and PC3 being on a first substrate <NUM>.

Beams of light (e.g. blue light Lb) emitted from the first to third light-emitting diodes LED1, LED2, and LED3 may be converted to red light Lr or green light Lg, or pass as blue light Lb while passing through the color panel <NUM>. A region from which red light Lr is emitted may correspond to a red pixel Pr, a region from which green light Lg is emitted may correspond to a green pixel Pg, and a region from which blue light Lb is emitted may correspond to a blue pixel Pb.

The color panel <NUM> may include a color-conversion transmission layer and a color layer, the color-conversion transmission layer including a first color converter 40a, a second color converter 40b, and a transmission portion 40c, and the color layer including a first color filter 30a, a second color filter 30b, and a third color filter 30c.

A first color region of the color panel <NUM> may include the first color converter 40a that overlaps the first color filter 30a, a second color region of the color panel <NUM> may include the second color converter 40b that overlaps the second color filter 30b, and a third color region of the color panel <NUM> may include the transmission portion 40c that overlaps the third color filter 30c.

The color panel <NUM> may include a light-blocking region arranged to surround each of the first to third color regions. The light-blocking region may include a first light-blocking layer <NUM> on a second substrate <NUM>. The first light-blocking layer <NUM> may include a plurality of holes formed as a result of portions thereof corresponding to the red pixel Pr, the green pixel Pg, and the blue pixel Pb being removed. The first light-blocking layer <NUM> may include a material portion arranged in the non-pixel area NPA. The material portion may include various materials that may absorb light.

The light-blocking region may include a second light-blocking layer <NUM> on the first light-blocking layer <NUM>. The second light-blocking layer <NUM> may also include a material portion arranged in the non-pixel area NPA. The second light-blocking layer <NUM> (e.g., the material portion of the second light-blocking layer <NUM>) may include various materials that may absorb light. The second light-blocking layer <NUM> may include a material same as or different from that of the first light-blocking layer <NUM>. The first light-blocking layer <NUM> and/or the second light-blocking layer <NUM> may include an opaque inorganic insulating material such as chrome oxide or molybdenum oxide, or include an opaque organic insulating material such as a black resin.

Blue light Lb emitted from the first light-emitting diode LED1 of the light-emitting panel <NUM> may pass through the first color region. Blue light Lb may be converted and filtered into red light Lr while passing through the color panel <NUM>. The first color converter 40a and the first color filter 30a of the first color region overlap the first light-emitting diode LED1. Blue light Lb emitted from the first light-emitting diode LED1 may be converted at the first color converter 40a and then may pass through the first color filter 30a. The first color converter 40a may convert blue light Lb incident thereto into red light Lr. As shown in <FIG>, the first color converter 40a may include a first photosensitive polymer <NUM>, and first quantum dots <NUM> and first scattering particles <NUM> dispersed in the first photosensitive polymer <NUM>.

The first quantum dots <NUM> may be excited by blue light Lb and may isotropically emit red light Lr having a wavelength longer than that of the blue light Lb. The first photosensitive polymer <NUM> may include an organic material having a light transmission characteristic. The first scattering particles <NUM> scatter blue light Lb that is not absorbed in the first quantum dots <NUM> and allow more first quantum dots <NUM> to be excited, thereby increasing a color conversion efficiency. The first scattering particles <NUM> may include, for example, metal oxide such as TiO<NUM> or particles including metal. The first quantum dots1152 may be one of a Group II-Group VI compound, a Group II-Group V compound, a Group IV-Group VI compound, a Group IV element, a Group IV compound, and a combination thereof.

Red light Lr converted by the first color converter 40a may improve color purity thereof while passing through the first color filter 30a. The first color filter 30a may include pigment or dye of a first color (e.g. a red color).

Blue light Lb emitted from the second light-emitting diode LED2 of the light-emitting panel <NUM> may pass through the second color region of the color panel <NUM>. Blue light Lb may be converted and filtered into green light Lg while passing through the color panel <NUM>. The second color converter 40b and the second color filter 30b of the second color region may overlap the second light-emitting diode LED2. Blue light Lb emitted from the second light-emitting diode LED2 may be converted at the second color converter 40b and then may pass through the second color filter 30b.

The second color converter 40b may convert blue light Lb incident thereto into green light Lg. The second color converter 40b may overlap the second color filter 30b. As shown in <FIG>, the second color converter 40b may include a second photosensitive polymer <NUM>, and second quantum dots <NUM> and second scattering particles <NUM> dispersed in the second photosensitive polymer <NUM>.

The second quantum dots <NUM> may be excited by blue light Lb and may isotropically emit green light Lg having a wavelength longer than that of the blue light Lb. The second photosensitive polymer <NUM> may include an organic material having a light transmission characteristic.

The second scattering particles <NUM> scatter blue light Lb that is not absorbed in the second quantum dots <NUM> and allow more second quantum dots <NUM> to be excited, thereby increasing a color conversion efficiency. The second scattering particles <NUM> may include, for example, metal oxide such as TiO<NUM> or particles including metal. The second quantum dots1162 may be one of a Group II-Group VI compound, a Group II-Group V compound, a Group IV-Group VI compound, a Group IV element, a Group IV compound, and a combination thereof.

In an embodiment, the first quantum dots <NUM> and the second quantum dots <NUM> may include the same material. In this case, the size of the first quantum dots <NUM> may be greater than the size of the second quantum dots <NUM>.

Green light Lg converted by the second color converter 40b may improve color purity thereof while passing through the second color filter 30b. The second color filter 30b may include pigment or dye of a second color (e.g. a green color).

Blue light Lb emitted from the third light-emitting diode LED3 of the light-emitting panel <NUM> may pass through the third color region of the color panel <NUM>. The transmission portion 40c and the third color filter 30c of the third color region may overlap the third light-emitting diode LED3. Blue light Lb emitted from the third light-emitting diode LED3 may pass through the transmission portion 40c without color conversion and be emitted to the outside through the third color filter 30c.

The transmission portion 40c may transmit blue light Lb incident to the transmission portion 40c without color conversion. As shown in <FIG>, the transmission portion 40c may include a third photosensitive polymer <NUM> in which third scattering particles <NUM> are dispersed. The third photosensitive polymer <NUM> may include an organic material having a light transmission characteristic, for example, a silicon resin, an epoxy resin, and the like and may include the same material as those of the first and second photosensitive polymers <NUM> and <NUM>. The third scattering particles <NUM> may scatter and emit blue light Lb and include the same material as those of the first and second scattering particles <NUM> and <NUM>. The third scattering particles <NUM> may include, for example, metal oxide such as TiO<NUM> or particles including metal.

Blue light Lb that passes through the transmission portion 40c may improve color purity thereof while passing through the third color filter 30c.

The first to third light-emitting diodes LED1, LED2, and LED3 may include organic light-emitting diodes including an organic material. In another embodiment, the first to third light-emitting diodes LED1, LED2, and LED3 may include inorganic light-emitting diodes including an inorganic material. An inorganic light-emitting diode may include a PN-junction diode including inorganic semiconductor-based materials. When a forward voltage is applied to a PN-junction diode, holes and electrons are injected, energy created due to recombination of holes and electrons is converted to light energy, and light of a present color may be emitted. The inorganic light-emitting diode may have a width of several micrometers to hundreds of micrometers or a width of several nanometers to hundreds of nano meters. In an embodiment, the light-emitting diode may be a light-emitting diode including quantum dots. As described above, an emission layer of the light-emitting diode LED may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

The display apparatus DV may include mobile phones, televisions, advertisement boards, monitors, tablet personal computers (PC), and notebook computers.

<FIG> is an equivalent circuit diagram of a light-emitting diode and a pixel circuit PC electrically connected to the light-emitting diode, included in a light-emitting panel of a display apparatus according to an embodiment.

Referring to <FIG>, a first electrode (e.g., an anode) of the light-emitting diode LED may be connected to the pixel circuit PC, and a second electrode (e.g., a cathode) of the light-emitting diode LED may be connected to a common voltage line VSL providing a common power voltage ELVSS. The light-emitting diode LED may emit light at brightness corresponding to the amount of current supplied from the pixel circuit PC.

The light-emitting diode LED of <FIG> may correspond to each of the first to third light-emitting diodes LED1, LED2, and LED3 shown in <FIG>, and the pixel circuit PC of <FIG> may correspond to each of the first to third pixel circuits PC1, PC2, and PC3 shown above in <FIG>.

The pixel circuit PC may control the amount of current flowing from a driving power voltage ELVDD to the common power voltage ELVSS through the light-emitting diode LED according to a data signal. The pixel circuit PC may include a driving transistor M1, a switching transistor M2, a sensing transistor M3, and a storage capacitor Cst.

Each of the driving transistor M1, the switching transistor M2, and the sensing transistor M3 may be an oxide semiconductor thin-film transistor including a semiconductor layer including an oxide semiconductor, or a silicon semiconductor thin-film transistor including a semiconductor layer including polycrystalline silicon. A first electrode may be one of a source electrode and a drain electrode, and a second electrode may be the other of the source electrode and the drain electrode depending on the type of a transistor.

The first electrode of the driving transistor M1 may be connected to a driving voltage line VDL configured to supply the driving power voltage ELVDD, and the second electrode may be connected to the first electrode of the light-emitting diode LED. A gate electrode of the driving transistor M1 may be connected to a first node N1. The driving transistor M1 may control the amount of current flowing from the driving power voltage ELVDD to the light-emitting diode LED according to the voltage of the first node N1.

The switching transistor M2 may be a switching transistor. A first electrode of the switching transistor M2 may be connected to a data line DL, and a second electrode of the switching transistor M2 may be connected to the first node N1. A gate electrode of the switching transistor M2 may be connected to a scan line SL. The switching transistor M2 may be turned on when a scan signal is supplied through the scan line SL and may electrically connect the data line DL to the first node N1.

The sensing transistor M3 may be an initialization transistor and/or a sensing transistor. A first electrode of the sensing transistor M3 may be connected to a second node N2, and a second electrode of the sensing transistor M3 may be connected to a sensing line SEL. A gate electrode of the sensing transistor M3 may be connected to a control line CL.

The storage capacitor Cst may be connected between the first node N1 and the second node N2. As an example, a first capacitor electrode of the storage capacitor Cst may be connected to the gate electrode of the driving transistor M1, and a second capacitor electrode of the storage capacitor Cst may be connected to the first electrode of the light-emitting diode LED.

In an embodiment, a method of driving the pixel circuit PC during an image display section is described below.

During a first section in which the switching transistor M2 receives an on-voltage of the scan line SL, the switching transistor M2 is turned on according to an on-voltage of a scan signal. When the switching transistor M2 is turned on, a data voltage of the data line DL is applied to the gate electrode of the driving transistor M1 connected to the first node N1 and is stored in the storage capacitor Cst.

The driving transistor M1 is turned on based on a data voltage, and a driving current flows through the first electrode (e.g., an anode) of the light-emitting diode LED based on the driving power voltage ELVDD. The light-emitting diode LED may display an image by emitting light according to the driving current corresponding to the data voltage.

During a second section in which the sensing transistor M3 receives an on-voltage of the control line CL, the sensing transistor M3 is turned on according to the on-voltage of a control signal. An initialization voltage of the sensing line SEL is applied to the second node N2, for example, the first electrode of the light-emitting diode LED. Accordingly, the first electrode of the light-emitting diode LED may be initialized.

A method of driving the pixel circuit PC during a sensing section is described below.

The switching transistor M2 is turned off according to an off-voltage of a scan signal, and the sensing transistor M3 is turned on according to an on-voltage of a control signal. A sensing signal applied to the second node N2 may be provided to a controller (or a sensing portion) through the sensing line SEL, the second node N2 being connected to the second electrode of the driving transistor M1 and the first electrode of the light-emitting diode LED. The controller may generate sensing data, which is digital data, by using a sensing signal and compensate for and correct image data by using the sensing data.

Though it is shown in <FIG> that the driving transistor M1, the switching transistor M2, and the sensing transistor M3 include n-channel metal oxide semiconductor (NMOS), the embodiment is not limited thereto. As an example, at least one of the driving transistor M1, the switching transistor M2, and the sensing transistor M3 may include a p-channel metal oxide semiconductor (PMOS).

Though <FIG> shows three transistors, the embodiment is not limited thereto. The pixel circuit PC may include four or more transistors.

<FIG> is a plan view of pixel circuits of a light-emitting panel according to an example, not falling under the scope of the claimed invention, and <FIG> is a plan view of light-emitting diodes arranged on pixel circuits of <FIG>. In an embodiment, <FIG> shows the case where a light-emitting diode is an organic light-emitting diode.

Referring to <FIG>, the scan line SL and the control line CL may extend in an x-direction, and a plurality of data lines, for example, first to third data lines DL1, DL2, and DL3 may extend in a y-direction crossing the x-direction. The sensing line SEL, the driving voltage line VDL, and the common voltage line VSL may extend in the y-direction.

In an embodiment, two common voltage lines VSL that are adjacent to each other may be apart from each other. The first to third data lines DL1, DL2, and DL3, the sensing line SEL, and the driving voltage line VDL may be arranged between the two common voltage lines VSL that are adjacent to each other. The sensing line SEL and the driving voltage line VDL may be adjacent to each other and adjacent to one of the common voltage lines VSL. The first to third data lines DL1, DL2, and DL3 may be adjacent to each other and adjacent to the other of the common voltage lines VSL. As an example, the sensing line SEL and the driving voltage line VDL may be arranged on one side (e.g., the left side) of first to third storage capacitors Cst1, Cst2, and Cst3. The first to third data lines DL1, DL2, and DL3 may be arranged on the other side (e.g., the right side) of the first to third storage capacitors Cst1, Cst2, and Cst3. Through this structure, the space of the display panel may be efficiently used.

Auxiliary lines AL may extend, for example, in the x-direction to cross the common voltage line VSL and the driving voltage line VDL. The auxiliary lines AL may be apart from each other with the first to third storage capacitors Cst1, Cst2, and Cst3 therebetween. As an example, one of the auxiliary lines AL may be adjacent to the scan line SL, and another may be adjacent to the control line CL. One of the auxiliary lines AL may be electrically connected to the common voltage line VSL. In an embodiment, as shown in <FIG>, one of the auxiliary lines AL may be electrically connected to the common voltage line VSL, and another may not be electrically connected to the common voltage line VSL. In another embodiment, one of the auxiliary lines AL that are adjacent to each other may be electrically connected to the common voltage line VSL, and another may be electrically connected to the driving voltage line VDL.

The display panel may have a structure in which the structure shown in <FIG> is repeated in the x-direction and the y-direction, and accordingly, the plurality of auxiliary lines AL and the plurality of common voltage lines VSL provided to the display panel may constitute a mesh structure in a plan view. Likewise, the plurality of auxiliary lines AL and the plurality of driving voltage lines VDL electrically connected to each other may constitute a mesh structure in a plan view.

The transistors and the storage capacitors may be arranged in an approximately quadrangular space surrounded by the common voltage lines VSL adjacent to each other and the auxiliary lines AL adjacent to each other. The transistors and the storage capacitors may be respectively electrically connected to corresponding light-emitting diodes. With regard to this, it is shown in <FIG> that first electrodes <NUM>, <NUM>, and <NUM> of first to third organic light-emitting diodes OLED1, OLED2, and OLED3 are respectively electrically connected to the corresponding pixel circuits.

The first electrode <NUM> of the first organic light-emitting diode OLED1 may be electrically connected to the first pixel circuit PC1. As shown in <FIG>, the first pixel circuit PC1 may include a first driving transistor M11, a first switching transistor M12, a first sensing transistor M13, and the first storage capacitor Cst1.

The first electrode <NUM> of the second organic light-emitting diode OLED2 may be electrically connected to the second pixel circuit PC2. The second pixel circuit PC2 may include a second driving transistor M21, a second switching transistor M22, a second sensing transistor M23, and the second storage capacitor Cst2.

The first electrode <NUM> of the third organic light-emitting diode OLED3 may be electrically connected to the third pixel circuit PC3. The third pixel circuit PC3 may include a third driving transistor M31, a third switching transistor M32, a third sensing transistor M33, and the third storage capacitor Cst3.

The first to third storage capacitors Cst1, Cst2, and Cst3 may be arranged in one direction, for example, the y-direction. The first storage capacitor Cst1 may be arranged relatively closest to the control line CL, the third storage capacitor Cst3 may be arranged relatively closest to the scan line SL, and the second storage capacitor Cst2 may be arranged between the first storage capacitor Cst1 and the third storage capacitor Cst3.

The first driving transistor M11 may include a first driving semiconductor layer A11 and a first driving gate electrode G11. The first driving semiconductor layer A11 may include an oxide semiconductor or a silicon-based semiconductor. The first driving semiconductor layer A11 may include a first low-resistance region B11 and a second low-resistance region C11. A first channel region may be arranged between the first low-resistance region B11 and the second low-resistance region C11. The first low-resistance region B11 and the second low-resistance region C11 are regions having a resistance less than that of the first channel region and may be formed through a process of doping impurities or a process of making conductive. The first driving gate electrode G11 may overlap the first channel region of the first driving semiconductor layer A11. One of the first low-resistance region B11 and the second low-resistance region C11 may correspond to a source region, and the other may correspond to a drain region.

One of the first low-resistance region B11 and the second low-resistance region C11 of the first driving semiconductor layer A11 may be connected to the first storage capacitor Cst1, and the other may be connected to the driving voltage line VDL. As an example, the first low-resistance region B11 may be connected to a portion (e.g., a second sub-electrode CE2t of a second capacitor electrode CE2) of the second capacitor electrode CE2 of the first storage capacitor Cst1 through a first contact hole CT1. The second low-resistance region C11 may be connected to a first connector NM1 through a second contact hole CT2, and the first connector NM1 may be connected to the driving voltage line VDL through a third contact hole CT3. The second low-resistance region C11 may be electrically connected to the driving voltage line VDL through the first connector NM1.

The first switching transistor M12 may include a first switching semiconductor layer A12 and a first switching gate electrode G12. The first switching semiconductor layer A12 may include an oxide semiconductor or a silicon-based semiconductor. The first switching semiconductor layer A12 may include a first low-resistance region B12 and a second low-resistance region C12. A second channel region may be arranged between the first low-resistance region B12 and the second low-resistance region C12. The first switching gate electrode G12 may overlap the second channel region of the first switching semiconductor layer A12. The first switching gate electrode G12 may correspond to a portion of the scan line SL, for example, a portion of a branch (hereinafter referred to as a first branch SL-B) extending in a direction crossing the scan line SL.

The scan line SL may include gate electrodes of first to third switching transistors M12, M22, and M32. As an example, the scan line SL may include the first branch SL-B extending in the y-direction. Portions of the first branch SL-B may correspond to the gate electrodes of first to third switching transistors M12, M22, and M32. The first branch SL-B may extend between a group of the first to third storage capacitors Cst1, Cst2, and Cst3, and a group of the first to third data lines DL1, DL2, and DL3.

One of the first low-resistance region B12 and the second low-resistance region C12 of the first switching semiconductor layer A12 may be electrically connected to the first data line DL1, and the other may be electrically connected to the first storage capacitor Cst1. As an example, the first low-resistance region B12 may be connected to a second connector NM2 through a fourth contact hole CT4, and the second connector NM2 may be connected to a first capacitor electrode CE1 of the first storage capacitor Cst1 through a fifth contact hole CT5. Accordingly, the first low-resistance region B12 may be electrically connected to the first capacitor electrode CE1 of the first storage capacitor Cst1 through the second connector NM2. The second low-resistance region C12 may be connected to a third connector NM3 through a sixth contact hole CT6, and the third connector NM3 may be connected to the first data line DL1 through a seventh contact hole CT7. The second low-resistance region C12 may be connected to the first data line DL1 through the third connector NM3.

The first sensing transistor M13 may include a first sensing semiconductor layer A13 and a first sensing gate electrode G13. The first sensing semiconductor layer A13 may include an oxide semiconductor or a silicon-based semiconductor. The first sensing semiconductor layer A13 may include a first low-resistance region B13 and a second low-resistance region C13. A third channel region may be arranged between the first low-resistance region B13 and the second low-resistance region C13. The first sensing gate electrode G13 may overlap the third channel region of the first sensing semiconductor layer A13.

The control line CL may include gate electrodes of first to third sensing transistors M13, M23, and M33. As an example, the control line CL may include a branch (thereinafter referred to as a second branch CL-B) extending in the y-direction. Portions of the second branch CL-B may correspond to the gate electrodes of the first to third sensing transistors M13, M23, and M33. The second branch CL-B may extend between the driving voltage line VDL and the sensing line SEL.

One of the first low-resistance region B13 and the second low-resistance region C13 of the first sensing semiconductor layer A13 may be electrically connected to the sensing line SEL, and the other may be electrically connected to the first storage capacitor Cst1. As an example, the first low-resistance region B13 may be connected to an auxiliary sensing line a-SEL through an eighth contact hole CT8, and the auxiliary sensing line a-SEL may be connected to the sensing line SEL through a ninth contact hole CT9. Accordingly, the first low-resistance region B13 may be electrically connected to the sensing line SEL through the auxiliary sensing line a-SEL. The auxiliary sensing line a-SEL may extending in an extension direction (the y-direction) of the sensing line SEL while overlapping the sensing line SEL. In a plan view, the auxiliary sensing line a-SEL may be arranged between the scan line SL and the control line CL and may have a length less than a separation distance (a separation distance in the y-direction) between the scan line SL and the control line CL. The second low-resistance region C13 may be electrically connected to a portion of the second capacitor electrode CE2 of the first storage capacitor Cst1, for example, the second sub-electrode CE2t of the second capacitor electrode CE2 through a tenth contact hole CT10.

The first storage capacitor Cst1 may include at least two electrodes. In an embodiment, the first storage capacitor Cst1 may include the first capacitor electrode CE1 and the second capacitor electrode CE2.

The first capacitor electrode CE1 may be formed as one body with the first driving gate electrode G11. In other words, a portion of the first capacitor electrode CE1 may include the first driving gate electrode G11.

The second capacitor electrode CE2 may include a first sub-electrode CE2b and a second sub-electrode CE2t, the first sub-electrode CE2b being under the first capacitor electrode CE1, and the second sub-electrode CE2t being on the first capacitor electrode CE1. The first sub-electrode CE2b may be connected to the second sub-electrode CE2t through an eleventh contact hole CT11.

The specific structures and materials of the second driving transistor M21 and the third driving transistor M31 are the same as those of the first driving transistor M11 described above. The second switching transistor M22 and the third switching transistor M32 are the same as the first switching transistor M12 described above except that the second switching transistor M22 and the third switching transistor M32 are respectively connected to the second data line DL2 and the third data line DL3. The specific structures and materials of the second sensing transistor M23 and the third sensing transistor M33 are the same as those of the first sensing transistor M13 described above. The structure of the second storage capacitor Cst2 and the third storage capacitor Cst3 are the same as that of the first storage capacitor Cst1 described above.

The first organic light-emitting diode OLED1 may be electrically connected to the first pixel circuit through a first via hole VH1 as shown in <FIG>. As an example, the first electrode <NUM> of the first organic light-emitting diode OLED1 may be connected to the second sub-electrode CE2t (see <FIG>) of the first storage capacitor Cst1 through the first via hole VH1.

The second organic light-emitting diode OLED2 may be electrically connected to the second pixel circuit through a second via hole VH2 as shown in <FIG>. As an example, the first electrode <NUM> of the second organic light-emitting diode OLED2 may be connected to the second sub-electrode of the second storage capacitor Cst2 through the second via hole VH2.

The third organic light-emitting diode OLED3 may be electrically connected to the third pixel circuit through a third via hole VH3 as shown in <FIG>. As an example, the first electrode <NUM> of the third organic light-emitting diode OLED3 may be connected to the second sub-electrode of the third storage capacitor Cst3 through the third via hole VH3.

As shown in <FIG> and <FIG>, the first electrodes <NUM>, <NUM>, and <NUM> of the first to third organic light-emitting diodes OLED1, OLED2, and OLED3 may overlap portions of the elements therebelow, for example, the lines, the storage capacitors, and/or the transistors and may not overlap the sensing line SEL and the auxiliary sensing line a-SEL electrically connected to the sensing line SEL. With regard to this, it is shown in <FIG> that the first electrode <NUM> of the first organic light-emitting diode OLED1 overlaps a portion of the first sensing transistor M13, a portion of the second sensing transistor M23, and a portion of the driving voltage line VDL, but does not overlap the sensing line SEL and the auxiliary sensing line a-SEL.

<FIG> is a cross-sectional view of the light-emitting diode taken along line V-V' of <FIG>.

The sensing line SEL may be arranged on the first substrate <NUM>, and the first substrate <NUM> may include glass or a resin material. Glass may include transparent glass including SiO<NUM> as a main component. The resin material may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose tri acetate, and cellulose acetate propionate. In the case where the first substrate <NUM> includes the polymer resin, the first substrate <NUM> may be flexible, rollable, and bendable.

The sensing line SEL may include metal such as molybdenum (Mo), copper (Cu), and titanium (Ti). The sensing line SEL may be arranged directly on the first substrate <NUM> and may directly contact the first substrate <NUM>. Alternatively, an insulating layer may be arranged between the sensing line SEL and the first substrate <NUM>.

A buffer layer <NUM> (a first insulating layer) may be arranged on the sensing line SEL, and a semiconductor layer may be arranged on the buffer layer101. With regard to this, it is shown in <FIG> that a first sensing semiconductor layer A13 of the first sensing transistor M13 is arranged on the buffer layer <NUM>. The semiconductor layers of all of the other transistors may be arranged on the buffer layer <NUM>.

The buffer layer <NUM> may prevent impurities from penetrating into the semiconductor layers. The buffer layer <NUM> may include an inorganic insulating material such as silicon nitride, silicon oxide, and/or silicon oxynitride.

A gate insulating layer <NUM> (a second insulating layer) is arranged on the semiconductor layer. With regard to this, it is shown in <FIG> that the gate insulating layer <NUM> is arranged on the first sensing semiconductor layer A13. The gate insulating layer <NUM> may include an inorganic insulating material such as silicon nitride, silicon oxide, and/or silicon oxynitride, or include an organic insulating material. The gate insulating layer <NUM> may include a single-layered structure or a multi-layered structure including the above materials.

A gate electrode may overlap a channel region of a corresponding semiconductor layer with the gate insulating layer <NUM> therebetween. With regard to this, it is shown in <FIG> that the first sensing gate electrode G13 overlaps the channel region of the first sensing semiconductor layer A13 with the gate insulating layer <NUM> therebetween. The first sensing semiconductor layer A13 may include the channel region, the first low-resistance region B13, and the second low-resistance region C13, the channel region overlapping the first sensing gate electrode G13, and the first low-resistance region B13 and the second low-resistance region C13 being arranged on two opposite sides of the channel region. The first sensing gate electrode G13 may include at least one of molybdenum (Mo), copper (Cu), and titanium (Ti) and have a single-layered structure or a multi-layered structure including the above material.

An interlayer insulating layer <NUM> (a third insulating layer) may be arranged on the gate insulating layer <NUM>. With regard to this, <FIG> shows an interlayer insulating layer <NUM> on the first sensing gate electrode G13. The interlayer insulating layer <NUM> may include an inorganic insulating material such as silicon nitride, silicon oxide, and/or silicon oxynitride, or include an organic insulating material.

The auxiliary sensing line a-SEL may be arranged on the interlayer insulating layer <NUM> and electrically connected to the sensing line SEL through a contact hole passing through the interlayer insulating layer <NUM>. As an example, the auxiliary sensing line a-SEL may be electrically connected to the sensing line SEL through the ninth contact hole CT9 passing through the buffer layer <NUM>, the gate insulating layer <NUM>, and the interlayer insulating layer <NUM>. Because the auxiliary sensing line a-SEL has a preset length and is electrically connected to the sensing line SEL, a local voltage drop due to a resistance of the sensing line SEL may be prevented. A portion of the auxiliary sensing line a-SEL may be electrically connected to the sensing semiconductor layer through the eighth contact hole CT8 passing through the gate insulating layer <NUM> and the interlayer insulating layer <NUM>. With regard to this, it is shown that the auxiliary sensing line a-SEL is connected to the first low-resistance region B13 of the first sensing semiconductor layer A13 through the eighth contact hole CT8. The second low-resistance region C13 of the first sensing semiconductor layer A13 may be electrically connected to the second capacitor electrode, for example, the second sub-electrode CE2t through the tenth contact hole CT10.

A via insulating layer <NUM> may be arranged on that the auxiliary sensing line a-SEL. The via insulating layer <NUM> may include an organic insulating material and/or an inorganic insulating material. The organic insulating material may include, for example, a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

The first electrode of the light-emitting diode may be arranged on the via insulating layer <NUM>. With regard to this, it is shown in <FIG> that the first electrode <NUM> of the first organic light-emitting diode OLED1 is arranged on the via insulating layer <NUM>.

A bank layer <NUM> is arranged on the first electrode <NUM>, the bank layer <NUM> including an opening that exposes a portion of the first electrode <NUM>. An emission layer <NUM> and a second electrode <NUM> may be arranged to overlap the first electrode <NUM> through the opening of the bank layer <NUM>. The first electrode <NUM> may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In<NUM>O<NUM>), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode <NUM> may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), or a compound thereof. In another embodiment, the first electrode <NUM> may further include a layer on/under the reflective layer, the layer including ITO, IZO, ZnO, or In<NUM>O<NUM>. In an embodiment, the first electrode <NUM> may have a three-layered structure of an ITO layer, an Ag layer, and an ITO layer. Though <FIG> describes the first electrode <NUM> of the first organic light-emitting diode OLED1, the first electrodes <NUM> and <NUM> of the second and third organic light-emitting diodes OLED2 and OLED3 may be arranged in the same layer as the first electrode <NUM> of the first organic light-emitting diode OLED1 and may include the same material as that of the first electrode <NUM> of the first organic light-emitting diode OLED1.

The emission layer <NUM> may include a polymer organic material or a low-molecular weight organic material that emits blue light. The emission layer <NUM> may be formed to cover the first substrate <NUM> entirely. As an example, the emission layer <NUM> may be formed as one body to entirely cover the first to third organic light-emitting diodes OLED1, OLED2, and OLED3 described above with reference to <FIG>. The second electrode <NUM> may be also formed to cover the first substrate <NUM> entirely.

The second electrode <NUM> may be a semi-transmissive electrode or a transmissive electrode. The second electrode <NUM> may be a semi-transmissive electrode including an ultra thin-film metal including magnesium (Mg), silver (Ag), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), or a compound thereof. The second electrode <NUM> may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In<NUM>O<NUM>), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

Referring to <FIG> and <FIG>, the first electrodes <NUM>, <NUM>, and <NUM> of the first to third organic light-emitting diodes OLED1, OLED2, and OLED3 do not overlap the sensing line SEL and the auxiliary sensing line a-SEL electrically connected to the sensing line SEL.

As a comparative example, in the case where the first to third organic light-emitting diodes OLED1, OLED2, and OLED3 overlap the sensing line SEL and the auxiliary sensing line a-SEL electrically connected to the sensing line SEL, a parasitic capacitance may occur between the auxiliary sensing line a-SEL and the first electrode of one of the first to third organic light-emitting diodes OLED1, OLED2, and OLED3. The parasitic capacitance may influence brightness of other pixels. In addition, the parasitic capacitance changes a current value sensed during a sensing operation that uses the sensing transistor (e.g., the first to third sensing transistors M13, M23, and M33), and thus, makes accurate sensing impossible. In contrast, according to an embodiment, as shown in <FIG> and <FIG>, the first to third organic light-emitting diodes OLED1, OLED2, and OLED3 are designed not to overlap the sensing line SEL and the auxiliary sensing line a-SEL electrically connected to the sensing line SEL, and thus, the above issue may be prevented.

<FIG> is a plan view of pixel circuits of a light-emitting panel according to an embodiment of the claimed invention, <FIG> is a plan view of light-emitting diodes arranged on pixel circuits of <FIG>, <FIG> is a cross-sectional view of the light-emitting diode taken along line VIII-VIII' of <FIG>, and <FIG> is a cross-sectional view of the light-emitting diode taken along line IX-IX' of <FIG>. It is shown in <FIG> that the light-emitting diode is an organic light-emitting diode. With regard to this, <FIG> shows the first to third organic light-emitting diodes OLED1, OLED2, and OLED3 electrically connected to corresponding pixel circuits through the first to third via holes VH1, VH2, and VH3 respectively.

Referring to <FIG>, the light-emitting panel may include the scan line SL, the control line CL, and the auxiliary line AL each extending in the x-direction and include the first to third data lines DL1, DL2, and DL3, the sensing line SEL, the driving voltage line VDL, and the common voltage line VSL each extending in the y-direction.

Transistors and the storage capacitors corresponding to the first to third pixel circuits may be arranged between two common voltage lines VSL that are adjacent to each other. With regard to this, <FIG> shows the first to third driving transistors M11, M21, and M31, the first to third switching transistors M12, M22, and M32, the first to third sensing transistors M13, M23, and M33, and the first to third storage capacitors Cst1, Cst2, and Cst3.

According to the embodiment described above with reference to <FIG>, it is shown that the auxiliary sensing line a-SEL electrically connected to the sensing line SEL overlaps the sensing line SEL and is arranged on the gate electrode, for example, the first sensing gate electrode G13, the embodiment is not limited thereto. According to the claimed invention, an auxiliary sensing line a-SEL' is arranged in the same layer as the gate electrode of the transistors and may include the same material as that of the gate electrode of the transistors and/or the first capacitor electrode. With regard to this, it is shown in <FIG> that the auxiliary sensing line a-SEL' is arranged in the same layer as the first branch SL-B, the second branch CL-B, and the first capacitor electrode CE1 and includes the same material as that of the first branch SL-B, the second branch CL-B, and the first capacitor electrode CE1.

The auxiliary sensing line a-SEL' may extend in the same direction as a direction in which the sensing line SEL extends. The auxiliary sensing line a-SEL' may extend to have a length less than a separation distance (e.g., a separation distance in the y-direction) between the scan line SL and the control line CL.

The auxiliary sensing line a-SEL' may be electrically connected to the sensing line SEL arranged below the auxiliary sensing line a-SEL' through a connector. With regard to this, it is shown in <FIG> that the auxiliary sensing line a-SEL' is electrically connected to the sensing line SEL through a fourth connector NM4 and a sixth connector NM6.

The fourth connector NM4 may be arranged on the sensing line SEL and the auxiliary sensing line a-SEL' and connected to the sensing line SEL through a twelfth contact hole CT12 and connected to the auxiliary sensing line a-SEL' through a thirteenth contact hole CT13. The sixth connector NM6 may be arranged on the sensing line SEL and the auxiliary sensing line a-SEL' and connected to the sensing line SEL through a fifteenth contact hole CT15 and connected to the auxiliary sensing line a-SEL' through a sixteenth contact hole CT16.

The fourth connector NM4 may electrically connect the sensing line SEL to the sensing transistor, for example, the third sensing transistor M33. The fourth connector NM4 may be connected to the sensing semiconductor layer of the third sensing transistor M33 through a fourteenth contact hole CT14. Other sensing transistors, for example, the first and second sensing transistors M13 and M23 may be electrically connected to the sensing line SEL through a fifth connector NM5. For example, the fifth connector NM5 may be connected to the auxiliary sensing line a-SEL' connected to the sensing line SEL through a nineteenth contact hole CT19, and be connected to the low-resistance region (e.g., the first low-resistance region B13 of <FIG>) of the first and second sensing transistors M13 and M23 through a twentieth contact hole CT20. Referring to <FIG>, one of the low-resistance regions B13 and C13 of the first sensing transistor M13 may be connected to the auxiliary sensing line a-SEL' through the ninth and twentieth contact holes CT19 and CT20, and the other may be connected to the second sub-electrode CE2t through the tenth contact hole CT10.

Though it is shown in <FIG> that the length of the auxiliary sensing line a-SEL' in the y-direction is less than the separation distance between the scan line SL and the control line CL and thus the auxiliary sensing line a-SEL' does not overlap the scan line SL and the control line CL, the embodiment is not limited thereto. Because the auxiliary sensing line a-SEL' is arranged in a layer different from the scan line SL and the control line CL, a portion of the auxiliary sensing line a-SEL' may extend to overlap one of the scan line SL and the control line CL. As an example, a portion of the auxiliary sensing line a-SEL' shown in <FIG> may extend below the control line CL to overlap the control line CL, and in this case, the sixth connector NM6 may be omitted in some implementations of this embodiment.

As shown in <FIG> and <FIG> below, in the case where the auxiliary sensing line a-SEL' is arranged in the same layer as the gate electrode and/or the first capacitor electrode, the first electrode of the organic light-emitting diode may overlap the auxiliary sensing line a-SEL' and the sensing line SEL as shown in <FIG> and <FIG>. With regard to this, it is shown in <FIG> that the first electrode <NUM> of the first organic light-emitting diode OLED1 overlaps the auxiliary sensing line a-SEL' and the sensing line SEL. The first electrode <NUM> of the first organic light-emitting diode OLED1 may overlap the first sensing transistor M13, the second sensing transistor M23, and the driving voltage line VDL. As an example, the first electrode <NUM> of the first organic light-emitting diode OLED1 may overlap the first sensing semiconductor layer A13 and the first sensing gate electrode G13 of the first sensing transistor M13, overlap the second sensing semiconductor layer and the second sensing gate electrode of the second sensing transistor M23, and overlap the driving voltage line VDL.

Referring to <FIG>, the common voltage line VSL, the sensing line SEL, and the driving voltage line VDL may be arranged on the first substrate <NUM>. The buffer layer <NUM> may be arranged on the common voltage line VSL, the sensing line SEL, and the driving voltage line VDL. The first to third data lines DL1, DL2, and DL3 shown in <FIG> may be also arranged on the same layer(for example, on the first substrate <NUM>) as the sensing line SEL.

An auxiliary common voltage line may be arranged on the common voltage line VSL, the auxiliary common voltage line being electrically connected to the common voltage line VSL. With regard to this, <FIG> and <FIG> show a first auxiliary common voltage line a-VSL and a second auxiliary common voltage line a'-VSL. The first auxiliary common voltage line a-VSL may be arranged on the interlayer insulating layer <NUM> and electrically connected to the common voltage line VSL through a seventeenth contact hole CT17 passing through the buffer layer <NUM>, the gate insulating layer <NUM>, and the interlayer insulating layer <NUM>. The second auxiliary common voltage line a'-VSL may be arranged on the gate insulating layer <NUM> and electrically connected to the common voltage line VSL through an eighteenth contact hole CT18 passing through the buffer layer <NUM> and the gate insulating layer <NUM>.

The auxiliary sensing line a-SEL' is arranged in the same layer as the first sensing gate electrode G13. As an example, the auxiliary sensing line a-SEL' may be arranged on the gate insulating layer <NUM>. The auxiliary sensing line a-SEL' overlaps the sensing line SEL and may be electrically connected to the sensing line SEL through the sixth connector NM6 arranged over the auxiliary sensing line a-SEL' and the sensing line SEL. The sixth connector NM6 may be connected to the sensing line SEL through a fifteenth contact hole CNT15 and connected to the auxiliary sensing line a-SEL' through a sixteenth contact hole CNT16.

The semiconductor layer may be arranged on the buffer layer <NUM>. With regard to this, it is shown in <FIG> that the first sensing semiconductor layer A13 of the first sensing transistor M13 is arranged on the buffer layer <NUM>. The semiconductor layers of the other transistors are arranged on the buffer layer <NUM> as described above.

The first sensing semiconductor layer A13 includes the channel region, the first low-resistance region B13, and the second low-resistance region C13, the channel region overlapping first sensing gate electrode G13 (a portion of the second branch CL-B of the control line) with the gate insulating layer <NUM> therebetween, and the first low-resistance region B13 and the second low-resistance region C13 being on two opposite sides of the channel region. The first low-resistance region B13 may be electrically connected to the sensing line SEL. Like the sixth connector NM6, the fifth connector NM5 may be arranged on the interlayer insulating layer <NUM>, connected to the auxiliary sensing line a-SEL' through the nineteenth contact hole CT19 of the interlayer insulating layer <NUM>, and connected to the first low-resistance region B13 through the twentieth contact hole CT20 passing through the interlayer insulating layer <NUM> and the gate insulating layer <NUM>. The second low-resistance region C13 may be connected to the electrode of the first storage capacitor Cst1 (see <FIG>), for example, to the second sub-electrode CE2t on the interlayer insulating layer <NUM>.

The first electrode <NUM> of the first organic light-emitting diode OLED1 may be arranged on the via insulating layer <NUM> and may overlap the sensing line SEL and the auxiliary sensing line a-SEL' as shown in <FIG> and <FIG>. The first organic light-emitting diode OLED1 may include the emission layer <NUM> and the second electrode <NUM> on the first electrode <NUM>.

According to the example described with reference to <FIG>, because the auxiliary sensing line a-SEL is arranged on the interlayer insulating layer <NUM>, in the case where the first electrode of the organic light-emitting diode overlaps the auxiliary sensing line a-SEL, a parasitic capacitance occurs therebetween. In contrast, according to the embodiment shown in <FIG>, because the auxiliary sensing line a-SEL' is formed on the gate insulating layer <NUM>, a vertical distance (a distance in a z-direction) between the first electrode <NUM> and the auxiliary sensing line a-SEL' may be sufficiently secure, and thus, the occurrence of a parasitic capacitance between the first electrode <NUM> and the auxiliary sensing line a-SEL' may be reduced. Accordingly, the first electrode <NUM> of the first organic light-emitting diode OLED1 may be arranged without limitation in the positions of the sensing line SEL and the auxiliary sensing line a-SEL'.

In the case where the display apparatus includes a relatively large display area, a resistance thereof increases according to the length of the sensing line SEL crossing the display area. However, as described above, a voltage drop due to the length increase of the sensing line SEL may be prevented and simultaneously the occurrence of the parasitic capacitance may be reduced through the auxiliary sensing line a-SEL' on the gate insulating layer <NUM>.

Because the fifth connector NM5 is electrically connected to the auxiliary sensing line a-SEL' and overlaps a portion of the first electrode <NUM>, a parasitic capacitance may occur therebetween theoretically. However, because the area of the fifth connector NM5 is very small, the occurrence of the parasitic capacitance is very trivial, and thus, distortion issue of sensing information almost does not occur.

Referring to <FIG>, the sensing line SEL extends in the y-direction. The auxiliary sensing line a-SEL' is arranged on the gate insulating layer <NUM> as described above with reference to <FIG>. It is shown in <FIG> that the auxiliary sensing line a-SEL' is electrically connected to the sensing line SEL through the fourth connector NM4 arranged over the auxiliary sensing line a-SEL'. The fourth connector NM4 may be arranged on the interlayer insulating layer <NUM>, connected to the auxiliary sensing line a-SEL' through the thirteenth contact hole CT13 passing through the interlayer insulating layer <NUM>, and connected to the sensing line SEL through the twelfth contact hole CT12 passing through the interlayer insulating layer <NUM>, the gate insulating layer <NUM>, and the buffer layer <NUM>.

As shown in <FIG>, the fourth connector NM4 may be arranged in the same layer as the scan line SL and the auxiliary line AL, for example, on the interlayer insulating layer <NUM>. The control line CL (see <FIG>) may be also arranged on the interlayer insulating layer <NUM>.

<FIG> is a plan view of pixel circuits of a light-emitting panel according to another example, not falling under the scope of the claimed invention, <FIG> is a plan view of light-emitting diodes arranged on pixel circuits of <FIG>, and <FIG> is a cross-sectional view of the light-emitting diode taken along line XII-XII' of <FIG>.

Referring to <FIG>, the light-emitting panel may include the scan line SL, the control line CL, and the auxiliary line AL extending in the x-direction, and the first to third data lines DL1, DL2, and DL3, the sensing line SEL, the driving voltage line VDL, and the common voltage line VSL extending in the y-direction.

The transistors and the storage capacitors corresponding to the first to third pixel circuits may be arranged between two common voltage lines VSL that are adjacent to each other. With regard to this, <FIG> shows the first to third driving transistors M11, M21, and M31, the first to third switching transistors M12, M22, and M32, the first to third sensing transistors M13, M23, and M33, and the first to third storage capacitors Cst1, Cst2, and Cst3.

The first electrode of the light-emitting diode may overlap the transistor(s) and/or a line therebelow. In an embodiment, as shown in <FIG>, the first electrode <NUM> of the first organic light-emitting diode OLED1 may overlap the first sensing transistor M13, the second sensing transistor M23, and the driving voltage line VDL. As an example, the first electrode <NUM> of the first organic light-emitting diode OLED1 may overlap the first sensing semiconductor layer A13 and the first sensing gate electrode G13 of the first sensing transistor M13, overlap the second sensing semiconductor layer and the second sensing gate electrode of the second sensing transistor M23, and overlap the driving voltage line VDL.

<FIG> shows the auxiliary common voltage lines a-VSL and a'-VSL and the corresponding structures are the same as those described with reference to <FIG> and <FIG>. The structures of the auxiliary common voltage lines a-VSL and a'-VSL shown in <FIG> are applicable to the embodiment described with reference to <FIG> and embodiments described below (see <FIG> and <FIG>).

According to the examples and described with reference to <FIG> and <FIG>, though it is shown that the auxiliary sensing lines a-SEL and a-SEL' electrically connected to the sensing line SEL overlap the sensing line SEL, the light-emitting panel does not include the auxiliary sensing lines a-SEL and a-SEL' according to the embodiment of <FIG>. The first electrode of the organic light-emitting diode, for example, the first electrode <NUM> of the first organic light-emitting diode OLED1 may overlap the sensing line SEL shown in <FIG>.

The sensing line SEL is electrically connected to the sensing transistors, for example, the first to third sensing transistors M13, M23, and M33. With regard to this, it is shown in <FIG> that the sensing line SEL is electrically connected to the first to third sensing transistors M13, M23, and M33 through a seventh connector NM7.

Referring to <FIG>, the sensing line SEL may be arranged on the first substrate <NUM> and covered by the buffer layer <NUM>. As described above, the semiconductor layer may be arranged on the buffer layer <NUM>. With regard to this, <FIG> shows the first sensing semiconductor layer A13.

The first sensing semiconductor layer A13 includes the channel region, the first low-resistance region B13, and the second low-resistance region C13, the channel region overlapping the first sensing gate electrode G13, and the first low-resistance region B13 and the second low-resistance region C13 being on two opposite sides of the channel region. The first low-resistance region B13 may be connected to the sensing line SEL through the seventh connector NM7. The seventh connector NM7 may be connected to the sensing line SEL through a <NUM>st contact hole CT21 passing through the buffer layer <NUM>, the gate insulating layer <NUM>, and the interlayer insulating layer <NUM> and connected to the first low-resistance region B13 through a <NUM>nd contact hole CT22 passing through the gate insulating layer <NUM> and the interlayer insulating layer <NUM>. The second low-resistance region C13 may be electrically connected to the second capacitor electrode, for example, the second sub-electrode CE2t through the tenth contact hole CT10.

The first organic light-emitting diode OLED1 may overlap the sensing line SEL while being arranged on the via insulating layer <NUM>. With regard to this, it shown in <FIG> that the first electrode <NUM> of the first organic light-emitting diode OLED1 is arranged on the via insulating layer <NUM> and overlaps the sensing line SEL. The first organic light-emitting diode OLED1 includes the emission layer <NUM> and the second electrode <NUM> on the first electrode <NUM>, and specific structure and material thereof are the same as those described above.

According to the embodiment shown in <FIG>, because the auxiliary sensing line a-SEL (see <FIG>) is not provided on the interlayer insulating layer <NUM>, a parasitic capacitance does not occur between the auxiliary sensing line a-SEL and the first electrode <NUM>. In addition, because a distance (a distance in the z-direction) between the sensing line SEL and the first electrode <NUM> is sufficiently secured, a parasitic capacitance does not occur between the sensing line SEL and the first electrode <NUM>. Though the seventh connector NM7 is electrically connected to the sensing line SEL and overlaps the first electrode <NUM> of the first organic light-emitting diode OLED1 in the z-direction, the overlapping area of the seventh connector NM7 and the first electrode <NUM> is very small. Accordingly, distortion of sensing information due to the occurrence of the parasitic capacitance may not occur. Accordingly, the first electrode <NUM> may be arranged without limitation of the position of the sensing line SEL, and an emission area (an aperture ratio) of the first organic light-emitting diode OLED1 may be sufficiently secured.

<FIG> is a plan view of pixel circuits of a light-emitting panel according to another example, not falling under the scope of the claimed invention, and <FIG> is a plan view of light-emitting diodes arranged on pixel circuits of <FIG>.

Referring to <FIG>, the light-emitting panel may include transistors and storage capacitors corresponding to the first to third pixel circuits arranged between two common voltage lines VSL that are adjacent to each other. As shown in <FIG>, the first to third driving transistors M11, M21, and M31, the first to third switching transistors M12, M22, and M32, the first to third sensing transistors M13, M23, and M33, and the first to third storage capacitors Cst1, Cst2, and Cst3 may be arranged in a region between the two common voltage lines VSL adjacent to each other and between the two auxiliary lines AL adjacent to each other.

The configuration of the pixel circuits shown in <FIG> includes the structures described above with reference to <FIG> and may further include a conductive part arranged on the sensing line SEL. With regard to this, <FIG> shows two conductive parts, for example, a first conductive part CP1 and a second conductive part CP2 overlapping the sensing line SEL and arranged between the scan line SL and the control line CL in a plan view. Though <FIG> shows two conductive parts, the number of conductive parts may be variously changed. As an example, one conductive part may be arranged between the scan line SL and the control line CL or three or more conductive parts may be arranged between the scan line SL and the control line CL.

The conductive part, for example, the first conductive part CP1 and the second conductive part CP2 may be electrically connected to the sensing line SEL to reduce the resistance of the sensing line SEL. The first conductive part CP1 and the second conductive part CP2 may be connected to the sensing line SEL through a <NUM>rd contact hole CT23. Each of the first conductive part CP1 and the second conductive part CP2 may a length thereof greater than a width thereof, the length extending in a lengthwise direction (the y-direction) of the sensing line SEL, and the width extending in the x-direction. As an example, it is shown in <FIG> that a width W of the first conductive part CP1 in the x-direction is less than a length L in the y-direction. Though <FIG> shows a width W and a length L of the first conductive part CP1, the width of the second conductive part CP2 in the x-direction may be less than a length in the y-direction.

In this case, the conductive part does not overlap the first electrodes <NUM>, <NUM>, and <NUM> of the first to third organic light-emitting diodes OLED1, OLED2, and OLED3. With regard to this, it is shown in <FIG> that the first conductive part CP1 and the second conductive part CP2 are apart from each other around the first electrode <NUM>.

<FIG> is a cross-sectional view of the light-emitting diode taken along line XV-XV' of <FIG>, and <FIG> is a cross-sectional view of a portion the light-emitting diode taken along line XVI-XVI' of <FIG>.

Referring to <FIG>, the first conductive part CP1 may be arranged over the sensing line SEL with an insulating layer therebetween. The first conductive part CP1 may be connected to the sensing line SEL through a <NUM>rd contact hole CT23 passing through the buffer layer <NUM>, the gate insulating layer <NUM>, and the interlayer insulating layer <NUM>. The first conductive part CP1 may be arranged on the interlayer insulating layer <NUM>.

The sensing line SEL is electrically connected to the sensing transistor. With regard to this, it is shown in <FIG> that the seventh connector NM7 on the interlayer insulating layer <NUM> is connected to the sensing line SEL through the <NUM>st contact hole CT21 and connected to the first low-resistance region B13 of the first sensing semiconductor layer A13 through the <NUM>nd contact hole CT22. The structure of the first sensing transistor M13 including the first sensing semiconductor layer A13 is the same as that described above.

The first electrode of the organic light-emitting diode, for example, the first electrode <NUM> of the first organic light-emitting diode OLED1 does not overlap the first conductive part CP1. Because the first conductive part CP1 connected to the sensing line SEL has a preset length (e.g. the width of the first conductive part CP1 in the x-direction is less than a length thereof in the y-direction), the resistance of the sensing line SEL may be reduced. Though the seventh connector NM7 connected to the sensing line SEL overlaps the first electrode <NUM> of the first organic light-emitting diode OLED1 over the interlayer insulating layer <NUM>, the overlapping area of the seventh connector NM7 and the first electrode <NUM> of the first organic light-emitting diode OLED1 is very small. Accordingly, distortion of sensing information due to a parasitic capacitance may be ignored. That is, referring to <FIG> and <FIG>, the occurrence of a parasitic capacitance may be prevented while the resistance of the sensing line SEL is reduced through a conductive part having a width in the x-direction less than a length in the y-direction and not overlapping the first electrode of the light-emitting diode, for example, the first and second conductive parts CP1 and CP2.

Referring to <FIG>, the second conductive part CP2 may be arranged on the interlayer insulating layer <NUM>. The second conductive part CP2 may be connected to the sensing line SEL through the <NUM>rd contact hole CT23 passing through insulating layers therebetween, for example, the buffer layer <NUM>, the gate insulating layer <NUM>, and the interlayer insulating layer <NUM>. Like the first conductive part CP1, the second conductive part CP2 may have a preset length (e.g., a length thereof in the y-direction is greater than a width thereof in the x-direction) and be electrically connected to the sensing line SEL to reduce the resistance of the sensing line SEL.

The second conductive part CP2 may be one body with the seventh connector NM7. As shown in <FIG> and <FIG>, the seventh connector NM7 overlapping the first electrode <NUM> of the first organic light-emitting diode OLED1 and electrically connected to the first and second sensing transistors M13 and M23 is apart from the first conductive part CP1. In contrast, the connector not overlapping the first electrode <NUM> of the first organic light-emitting diode OLED1, for example, the seventh connector NM7 electrically connected to the third sensing transistor M33 may be formed as one body with the second conductive part CP2.

The seventh connector NM7 may be connected to the first low-resistance region B33 of the third sensing semiconductor layer A33 of the third sensing transistor M33. A second low-resistance region C33 of the third sensing semiconductor layer A33 may be connected to the second capacitor electrode, for example, the second sub-electrode CE2t. The third sensing gate electrode G33 may overlap the channel region of the third sensing semiconductor layer A33 with the gate insulating layer <NUM> therebetween.

As shown in <FIG>, the first conductive part CP1 and the second conductive part CP2 do not overlap the first electrode <NUM>. That is, when projected in a direction (the z-direction) perpendicular to the first substrate <NUM>, the first electrode <NUM> does not overlap the first conductive part CP1 and the second conductive part CP2. Because the first conductive part CP1 and the second conductive part CP2 are electrically connected to the sensing line SEL, in the case where a parasitic capacitance occurs between the first electrode <NUM> and the second conductive part CP2, it is difficult to obtain sensing information through the sensing line SEL due to the parasitic capacitance. In contrast, in the case where the second conductive part CP2 does not overlap the first electrode <NUM> of the first organic light-emitting diode OLED1, the occurrence of the parasitic capacitance may be reduced while the resistance of the sensing line SEL is reduced.

<FIG> is a plan view of pixel circuits of a light-emitting panel according to another example, not falling under the scope of the claimed invention, <FIG> is a plan view of light-emitting diodes arranged on pixel circuits of <FIG>, and <FIG> is a cross-sectional view of the light-emitting diode taken along line XIX-XIX' of <FIG>.

Referring to <FIG>, the light-emitting panel may include the scan line SL, the control line CL, and the auxiliary line extending in the x-direction, and the first to third data lines DL1, DL2, and DL3, the sensing line SEL, the driving voltage line VDL, and the common voltage line VSL extending in the y-direction.

The structure of the pixel circuits shown in <FIG> includes the structure described above with reference to <FIG> and is different in that a portion of the auxiliary common voltage line electrically connected to the common voltage line VSL extends between the sensing line SEL and the first electrode of the organic light-emitting diode.

The auxiliary common voltage line electrically connected to the common voltage line VSL may be arranged on the common voltage line VSL. With regard to this, <FIG> shows the first auxiliary common voltage line a-VSL and the second auxiliary common voltage line a'-VSL.

The first auxiliary common voltage line a-VSL may be arranged on the interlayer insulating layer <NUM>, and the second auxiliary common voltage line a'-VSL may be arranged on the gate insulating layer <NUM>. As shown in <FIG> and <FIG>, the first auxiliary common voltage line a-VSL may be electrically connected to the common voltage line VSL through a <NUM>th contact hole CT24. Similarly, the second auxiliary common voltage line a'-VSL may be electrically connected to the common voltage line VSL through a <NUM>th contact hole CT25 as shown in <FIG> and <FIG>.

At least one of the first auxiliary common voltage line a-VSL and the second auxiliary common voltage line a'-VSL electrically connected to the common voltage line VSL may include a main portion and an extension portion, the main portion overlapping the common voltage line VSL, and the extension portion extending from the main portion and being arranged between the sensing line SEL and the first electrode of the organic light-emitting diode. The extension portion of at least one of the first auxiliary common voltage line a-VSL and the second auxiliary common voltage line a'-VSL extending between the sensing line SEL and the first electrode of the organic light-emitting diode may have a voltage level same as that of the common voltage line VSL, which has a constant voltage. The extension portion may suppress the parasitic capacitance between the sensing line SEL and the first electrode of the organic light-emitting diode.

With regard to this, it is shown in <FIG> and <FIG> that the first auxiliary common voltage line a-VSL includes a main portion a-VSLm and an extension portion a-VSLe, the extension portion a-VSLe extending from the main portion a-VSLm and being arranged between the first electrode <NUM> of the first organic light-emitting diode OLED1 and the sensing line SEL. The main portion a-VSLm of the first auxiliary common voltage line a-VSL may overlap the common voltage line VSL, and the extension portion a-VSLe of the first auxiliary common voltage line a-VSL may overlap the first electrode <NUM> of the first organic light-emitting diode OLED1 and the sensing line SEL. When projected in the direction (the z-direction) perpendicular to the first substrate <NUM>, a portion of the first electrode <NUM> of the first organic light-emitting diode OLED1, a portion of the extension portion a-VSLe of the first auxiliary common voltage line a-VSL, and a portion of the sensing line SEL may overlap one another.

Though it is shown in <FIG> that the extension portion a-VSLe of the first auxiliary common voltage line a-VSL is arranged between the first electrode <NUM> of the first organic light-emitting diode OLED1 and the sensing line SEL, the extension portion a-VSLe being formed in the same layer as the second sub-electrode CE2t of the second capacitor electrodes and including the same material as that of the second sub-electrode CE2t, the embodiment is not limited thereto. In another embodiment, a portion of the second auxiliary common voltage line a'-VSL may overlap the first electrode <NUM> of the first organic light-emitting diode OLED1 and the sensing line SEL between the first electrode <NUM> of the first organic light-emitting diode OLED1 and the sensing line SEL. The second auxiliary common voltage line a'-VSL may be formed in the same layer as the first sensing gate electrode G13 and may include the same material as that of the first sensing gate electrode G13.

According to the examples and embodiments described with reference to <FIG>, it is shown that the first electrode <NUM> of the first organic light-emitting diode OLED1 among the first to third organic light-emitting diodes OLED1, OLED2, and OLED3 overlaps the first sensing transistor M13. As an example, though the above embodiments describe that the first electrode <NUM> of the first organic light-emitting diode OLED1 overlaps the sensing semiconductor layer A13 and the first sensing gate electrode G13 of the first sensing transistor M13, the embodiment is not limited thereto. In another embodiment, the configurations of the first to third organic light-emitting diodes OLED1, OLED2, and OLED3 may be different from that shown in <FIG>, <FIG>, <FIG>, <FIG> and <FIG>. In this case, the first electrode of one of the second and third organic light-emitting diodes OLED2 and OLED3 may overlap the first sensing transistor M11.

According to the embodiments described with reference to <FIG>, though the first electrode of the light-emitting diode, for example, the organic light-emitting diode overlaps the first sensing transistor M13, the embodiment is not limited thereto. In another embodiment, the first electrode of the organic light-emitting diode may overlap another sensing transistor, for example, the second and/or third sensing transistors M23 and/or M33 instead of the first sensing transistor M13.

As discussed, embodiments can provide a display apparatus comprising: a first substrate; a scan line that extends in a first direction over the first substrate; a data line that extends in a second direction crossing the first direction; a sensing line that extends in the second direction; a switching transistor electrically connected to the scan line and the data line; a driving transistor electrically connected to the switching transistor; a sensing transistor electrically connected to the driving transistor and electrically connected to the sensing line; a first insulating layer arranged between the first substrate and a sensing semiconductor layer of the sensing transistor; a via insulating layer provided on the switching transistor, the driving transistor, and the sensing transistor; and a light-emitting diode including a first electrode, an emission layer, and a second electrode, the first electrode being provided on the via insulating layer, the emission layer being provided on the first electrode, and the second electrode being provided on the emission layer, wherein the sensing line is arranged below the first insulating layer and overlaps the first electrode of the light-emitting diode.

A first electrode of the switching transistor may be connected to the data line, and a second electrode of the switching transistor may be connected to a first node. A gate electrode of the switching transistor may be connected to the scan line. The switching transistor may be turned on when a scan signal is supplied through the scan line and may electrically connect the data line to the first node.

A first electrode of the sensing transistor may be connected to a second node, and a second electrode of the sensing transistor may be connected to the sensing line. A gate electrode of the sensing transistor may be connected to a control line.

A storage capacitor may be connected between the first node and the second node. A first capacitor electrode of the storage capacitor may be connected to the gate electrode of the driving transistor, and a second capacitor electrode of the storage capacitor may be connected to the first electrode of the light-emitting diode.

A first electrode of the driving transistor may be connected to a driving voltage line configured to supply a driving power voltage, and a second electrode of the driving transistor may be connected to the first electrode of the light-emitting diode (e.g. via the second node). A gate electrode of the driving transistor may be connected to the first node.

The second electrode of the light-emitting diode may be connected to a common voltage line providing a common power voltage.

According to the embodiments, a parasitic capacitance between the sensing line and neighboring electrode (e.g., the first electrode of the light-emitting diode) may be prevented. However, the scope of the present disclosure is not limited by this effect.

Claim 1:
A display apparatus comprising:
a first substrate (<NUM>);
a scan line (SL) that extends in a first direction over the first substrate;
a data line (DL) that extends in a second direction crossing the first direction;
a sensing line (SEL) that extends in the second direction;
a switching transistor (M2) electrically connected to the scan line (SL) and the data line (DL);
a driving transistor (M1) electrically connected to the switching transistor (M1);
a sensing transistor (M3, M13) electrically connected to the driving transistor (M1) and electrically connected to the sensing line (SEL);
a first insulating layer (<NUM>) arranged between the first substrate (<NUM>) and a sensing semiconductor layer (A13) of the sensing transistor (M3);
a via insulating layer (<NUM>) provided on the switching transistor (M2), the driving transistor (M1), and the sensing transistor (M3); and
a light-emitting diode (OLED1, OLED2, OLED3) including a first electrode (<NUM>), an emission layer (<NUM>), and a second electrode (<NUM>), the first electrode (<NUM>) being provided on the via insulating layer (<NUM>), the emission layer (<NUM>) being provided on the first electrode (<NUM>), and the second electrode (<NUM>) being provided on the emission layer (<NUM>),
wherein the sensing line (SEL) is arranged below the first insulating layer (<NUM>) and overlaps the first electrode (<NUM>) of the light-emitting diode,
wherein the display apparatus further comprises:
an auxiliary sensing line that overlaps the sensing line and that is arranged in a same layer as a sensing gate electrode of the sensing transistor.