Patent Description:
With the development of multimedia, display devices are becoming more important. In response to the development, various types of display devices, such as organic light emitting diode (OLED) display devices, liquid crystal display (LCD) devices, and the like, are being used.

A device for displaying an image of a display device includes a display panel such as an OLED panel or an LCD panel. Among the above panels, a light emitting display panel may include a light emitting element. For example, an LED includes an OLED using an organic material as a fluorescent material, and an inorganic LED using an inorganic material as a fluorescent material.

The inorganic LED using an inorganic semiconductor as a fluorescent material has durability in a high temperature environment and has an advantage of high efficiency of blue light as compared with the OLED. Further, even in a manufacturing process which has been pointed out as a limitation of the conventional inorganic LED element, a transfer method using dielectrophoresis (DEP) has been developed. Therefore, research is being carried out on inorganic LEDs having excellent durability and excellent efficiency as compared with OLEDs. <CIT> discloses a display apparatus that includes a substrate, a first electrode on the substrate, the first electrode including a first portion that has a flat upper surface and a second portion that protrudes from the first portion and has an inclined surface, a second electrode facing the first electrode in parallel on the substrate, the second electrode including a first portion that has a flat upper surface and a second portion that protrudes from the first portion and has an inclined surface, and a plurality of light-emitting devices separate from each other on the first electrode and the second electrode, the light-emitting devices each having a first end contacting the upper surface of the first portion of the first electrode and a second end contacting the upper surface of the first portion of the second electrode.

<CIT> discloses a pixel structure of a display apparatus that includes an electrode line, at least one light-emitting diode, and a connection electrode. The electrode line includes a second electrode separated from a first electrode and at a same level as the first electrode on a base substrate. The at least one light-emitting diode is on the base substrate and has a length less than a distance between the first and second electrodes. A connection electrode includes a first contact electrode connecting the first electrode to the light-emitting diode and a second contact electrode connecting the second electrode to the light-emitting diode.

<CIT> disclose a thin film transistor substrate and a display device using the same. The TFT substrate includes a first TFT including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode deposited on a substrate, a second TFT separated from the first TFT, the second TFT including a second gate electrode, an oxide semiconductor layer, a second source electrode, and a second drain electrode deposited on the first gate electrode, and a plurality of storage capacitors separated from the first and second TFTs, each storage capacitor including a first dummy semiconductor layer, a first gate insulating layer on the first dummy semiconductor layer, a first dummy gate electrode on the first gate insulating layer, and an intermediate insulating layer on the first dummy gate electrode.

<CIT> describes a display device based on nano-sized light emitting diodes.

The present invention is directed to providing a display device including an oxide thin film transistor as a circuit element layer for driving a light-emitting element having a fine size.

It should be noted that objects of the present invention are not limited to the above-described objects, and other objects of the present invention as defined by the appended claims will be apparent to those skilled in the art from the following descriptions.

According to an aspect, there is provided a display device as set out in claim <NUM>. Additional features are set out in claims <NUM> to <NUM>. According to an aspect, there is provided a display device as set out in claim <NUM>. Additional features are set out in claim <NUM>.

The details of other embodiments are included in the detailed description and the accompanying drawings.

In accordance with the present invention, a display device includes a light-emitting element having a micrometer or nanometer unit size.

In accordance with the present invention, the display device includes a driving transistor including an oxide semiconductor and can drive the light-emitting element having the fine size.

The effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in this disclosure.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention which is defined by the appended claims, to those skilled in the art.

It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numbers indicate the same components throughout the specification.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For instance, a first element discussed below could be termed a second element without departing from the teachings of the present invention. Similarly, the second element could also be termed the first element.

<FIG> is a perspective view illustrating a display device according to one embodiment. <FIG> is a schematic block diagram illustrating the display device according to one embodiment. <FIG> is a schematic plan view illustrating a display panel of <FIG>.

Referring to <FIG>, a display device <NUM> according to one embodiment includes a display panel <NUM>, an integrated driving circuit <NUM>, a scan driver <NUM>, a circuit board <NUM>, and a power supply circuit <NUM>. The integrated driving circuit <NUM> may include a data driver <NUM> and a timing controller <NUM>.

In this specification, the terms "upper portion," "top," and "upper surface" indicate a Z-axis direction, and the terms "lower portion," "bottom," and "lower surface" indicate a direction opposite to the Z-axis direction. In addition, terms "left," "right," "upper," and "lower" refer to directions when the display panel <NUM> is viewed from a plan. For example, the term "left" refers to a direction opposite to an X-axis direction, the term "right" refers to the X-axis direction, the term "upper" refers to a Y-axis direction, and the term "lower" refers to a direction opposite the Y-axis direction.

The display panel <NUM> may be formed in a rectangular shape when viewed in a plan view. For example, as shown in <FIG>, the display panel <NUM> may have a planar form of a rectangular shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). A corner at which the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) meet may be formed at a right angle or formed to be rounded to have a predetermined curvature. The planar form of the display panel <NUM> is not limited to a rectangular shape and may be formed in a polygonal shape, a circular shape, or an elliptical shape which is different from the rectangular shape. In addition, although the display panel <NUM> has been formed to be flat in <FIG>, the present invention is not limited thereto. At least one side of the display panel <NUM> may be formed to be bent at a predetermined curvature.

The display panel <NUM> may be divided into a display area DA and a non-display area NDA disposed in a peripheral area of the display area DA. The display area DA is an area in which a plurality of pixels PX are formed to display an image. The display panel <NUM> may include data lines DL1 to DLm (m is an integer of two or more), scan lines SL1 to SLn (n is an integer of two or more) crossing the data lines DL1 to DLm, first voltage lines QVDDL which supply a first voltage, second voltage lines QVSSL which supply a second voltage, and pixels PX connected to the data lines DL1 to DLm and the scan lines SL1 to SLn.

Each pixel PX may include one or more light-emitting elements <NUM>, which emit light in a specific wavelength range, to display a color. The light emitted from the light-emitting element <NUM> may be displayed to the outside through the display area DA of the display panel <NUM>.

Each pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 may emit light of a first color, the second sub-pixel PX2 may emit light of a second color, and the third sub-pixel PX3 may emit light of a third color. The first color may be red, the second color may be green, and the third color may be blue, but the present invention is not limited thereto. In some cases, sub-pixels PXn may emit pieces of light having the same color. In addition, although each pixel PX has been illustrated as including three sub-pixels in <FIG>, the present invention is not limited thereto, and each pixel PX may include four or more sub-pixels.

The integrated driving circuit <NUM> outputs signals and voltages for driving the display panel <NUM>. To this end, the integrated driving circuit <NUM> may include a data driver <NUM> and a timing controller <NUM>.

The data driver <NUM> receives digital video data DATA and a source control signal DCS from the timing controller <NUM>. In response to the source control signal DCS, the data driver <NUM> converts the digital video data DATA into analog data voltages and supplies the analog data voltages to the data lines DL1 to DLm of the display panel <NUM>.

The timing controller <NUM> may receive the digital video data DATA and timing signals from a host system. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The host system may be an application processor of a smartphone or a tablet personal computer (PC), or a system on chip of a monitor or a television (TV).

The timing controller <NUM> generates control signals to control operation timings of the data driver <NUM> and the scan driver <NUM>. The control signals may include the source control signal DCS for controlling an operation timing of the data driver <NUM> and a scan control signal SCS for controlling an operation timing of the scan driver <NUM>.

The integrated driving circuit <NUM> may be disposed in the non-display area NDA provided on one side of the display panel <NUM>. The integrated driving circuit <NUM> may be formed as an integrated circuit (IC) and disposed on the display panel <NUM> through a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. However, the present invention is not limited thereto. For example, the integrated driving circuit <NUM> may be mounted on the circuit board <NUM> instead of the display panel <NUM>.

In addition, although the integrated driving circuit <NUM> has been shown as including the data driver <NUM> and the timing controller <NUM> in <FIG>, the present invention is not limited thereto. The data driver <NUM> and timing controller <NUM> may not formed as a single integrated circuit but may be formed as separate ICs. In this case, the data driver <NUM> may be mounted on the display panel <NUM> through a COG method, a COP method, or an ultrasonic bonding method, and the timing controller <NUM> may be mounted on the circuit board <NUM>.

The scan driver <NUM> receives the scan control signal SCS from the timing controller <NUM>. In response to the scan control signal SCS, the scan driver <NUM> generates scan signals and supplies the scan signals to the scan lines SL1 to SLn of the display panel <NUM>. The scan driver <NUM> may include a plurality of transistors and may be formed in the non-display area NDA of the display panel <NUM>. Alternatively, the scan driver <NUM> may be formed as an IC, and in this case, the scan driver <NUM> may be mounted on a gate flexible film attached to one side of the display panel <NUM>.

The circuit board <NUM> may be attached on pads provided at an edge of one side of the display panel <NUM> using an anisotropic conductive film. Consequently, lead lines of the circuit board <NUM> may be electrically connected to the pads. The circuit board <NUM> may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip on film. The circuit board <NUM> may be bent downward from the display panel <NUM>. In this case, one side of the circuit board <NUM> may be attached to an edge of one side of the display panel <NUM>, and the other side thereof may be disposed below the display panel <NUM> and connected to a system board on which the host system is mounted.

The power supply circuit <NUM> may generate voltages required to drive the display panel <NUM> from main power applied from the system board and supply the voltages to the display panel <NUM>. For example, the power supply circuit <NUM> may generate a first voltage QVDD and a second voltage QVSS for driving the light-emitting elements <NUM> of the display panel <NUM> from the main power and supply the first voltage QVDD and the second voltage QVSS to the first voltage line QVDDL and the second voltage line QVSSL. In addition, the power supply circuit <NUM> may generate and supply driving voltages for driving the integrated driving circuit <NUM> and the scan driver <NUM> from the main power.

Although the power supply circuit <NUM> has been formed as the IC to be mounted on the circuit board <NUM> in <FIG>, the embodiment of the present invention is not limited thereto. For example, the power supply circuit <NUM> may be formed to be integrated into the integrated driving circuit <NUM>.

<FIG> illustrates a plan view of the display panel <NUM> of <FIG> in a relatively detailed manner. In <FIG>, for convenience of description, only data pads DP1 to DPp (p is an integer of two or more), floating pads FD1 and FD2, power pads PP1 and PP2, floating lines FL1 and FL2, the second voltage line QVSSL, the data lines DL1 to DLm, first electrode lines <NUM>, and second electrode lines <NUM> are illustrated for convenience of description.

Referring to <FIG>, the plurality of pixels PX may be disposed in the display area DA of the display panel <NUM>, and the plurality of electrode lines <NUM> and <NUM> and the light-emitting element <NUM> between the plurality of electrode lines <NUM> and <NUM> may be aligned in each pixel PX. In the drawing, the plurality of pixels PX may be disposed in the first direction (X-axis direction) which is a horizontal direction and the second direction (Y-axis direction) that is a longitudinal direction. Although three sub-pixels PX1, PX2, and PX3 have been illustrated in portion A of <FIG>, it is obvious that the display panel <NUM> may include a greater number of pixels PX or sub-pixels PX1, PX2, and PX3.

The first sub-pixel PX1, second sub-pixel PX2, and third sub-pixel PX3 of each pixel PX may be disposed in regions which are defined in the form of a matrix by the first electrode lines <NUM>, the second electrode lines <NUM>, and the data lines DL1 to DLm.

In addition, the pixel PX of <FIG> may be divided into a plurality of pixels so that each of the pixels may constitute one pixel PX. As shown in <FIG>, pixels are not necessarily disposed to be parallel in the first direction (X-axis direction) and the second direction (Y-axis direction) and may be disposed in various structures such as the pixels being disposed in a zigzag shape or the like.

The non-display area NDA may be defined as an area in which the pixels PX are not disposed and an area other than the display area DA in the display panel <NUM>. The non-display area NDA may be covered by specific members so as not to be visibly recognized from the outside of the display panel <NUM>. Various members for driving the light-emitting elements <NUM> disposed in the display area DA may be disposed in the non-display area NDA. As shown in <FIG>, in the display panel <NUM>, a plurality of pads DP, FP, and PP may be disposed on one side of the display area DA, for example, on the non-display area NDA located in an upper portion when viewed in a plan view.

The plurality of pads may include data pads DP, power pads PP, and floating pads FP. The data pads DP may be connected to a plurality of data lines DL extending to the pixels PX of the display area DA. The data pads DP may transmit data signals for driving the pixels PX to the pixels PX through the data lines DL. One data pad DP may be connected to one data line DL, and the display panel <NUM> may include as many data pad DPs as the number of sub-pixels PXn disposed in the first direction (X-axis direction) of the display area DA.

The data lines DL1 to DLm may extend to be long in the second direction (Y-axis direction). One sides of the data lines DL1 to DLm may be connected to the integrated driving circuit <NUM>. Thus, data voltages of the integrated driving circuit <NUM> may be applied to the data lines DL1 to DLm.

The first electrode lines <NUM> may be disposed to be spaced at predetermined intervals in the first direction (X-axis direction). Thus, the first electrode lines <NUM> may not overlap the data lines DL1 to DLm. When the display panel <NUM> is manufactured, the first electrode lines <NUM> are formed such that two end portions of one electrode line are respectively connected to a first floating line FL1 and a second floating line FL2 of the non-display area NDA and then disconnected in each pixel PX or each sub-pixel PXn.

Each of the second electrode lines <NUM> may extend to be long in the first direction (X-axis direction). Thus, the second electrode lines <NUM> may overlap the data lines DL1 to DLm. In addition, unlike the first electrode lines <NUM>, the second electrode lines <NUM> may be connected to the second voltage line QVSSL in the non-display area NDA. Thus, the second voltages QVSS of the second voltage lines QVSSL may be applied to the second electrode lines <NUM>.

In the non-display area NDA of the display panel <NUM>, a pad portion PA including the data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2, the integrated driving circuit <NUM>, the first floating line FL1, the second floating line FL2, and the second voltage lines QVSSL may be disposed.

The pad portion PA including the data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2 may be disposed on an edge of one side of the display panel <NUM>, for example, disposed on an edge of a lower side of the display panel <NUM>. The data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2 may be disposed to be parallel in a first direction (X-axis direction) in the pad portion PA.

The circuit board <NUM> may be bonded on the data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2 using an anisotropic conductive film. Thus, the circuit board <NUM> may be electrically connected to the data pads DP1 to DPp, the floating pads FD1 and FD2, and the power pads PP1 and PP2.

The integrated driving circuit <NUM> may be connected to the data pads DP1 to DPp through link lines LL. The integrated driving circuit <NUM> may receive digital video data DATA and timing signals through the data pads DP1 to DPp. The integrated driving circuit <NUM> may convert the digital video data DATA into analog data voltages and supply the analog data voltages to the data lines DL1 to DLm of the display panel <NUM>.

The second voltage lines QVSSL may be connected to the first power pad PP1 and the second power pad PP2 of the pad portion PA. The second voltage lines QVSSL may extend to be long in the second direction (Y-axis direction) in the non-display area NDA on a left outer side and a right outer side of the display area DA. The second voltage lines QVSSL may be connected to the second electrode lines <NUM>. Thus, the second voltage QVSS of the power supply circuit <NUM> may be applied to the second electrode lines <NUM> through the circuit board <NUM>, the first power pad PP1, the second power pad PP2, and the second voltage lines QVSSL.

The first floating line FL1 may be connected to a first floating pad FD1 of the pad portion PA. The first floating line FL1 may extend to be long in the second direction (Y-axis direction) in the non-display area NDA on the left outer side and the right outer side of the display area DA.

The second floating line FL2 may be connected to a second floating pad FD2 of the pad portion PA. The second floating line FL2 may extend to be long in the second direction (Y-axis direction) in the non-display area NDA on the left outer side and the right outer side of the display area DA. The first and second floating pads FD1 and FD2 and the first and second floating lines FL1 and FL2 may be dummy pads and dummy lines to which any voltage is not applied.

The first floating line FL1 and the second floating line FL2 are lines for applying an alignment signal during a manufacturing process, and no voltage may be applied to the first floating line FL1 and the second floating line FL2 in the completed display device. Alternatively, a ground voltage may be applied to the first floating line FL1 and the second floating line FL2 so as to prevent static electricity in the completed display device.

In addition, although not shown in the drawings, in the display panel <NUM>, the first voltage line QVDDL for applying the first voltage QVDD to each pixel PX may be further disposed. One side of the first voltage line QVDDL may be connected to another pad (not shown) to apply a predetermined voltage to each pixel PX or each sub-pixel PXn.

Meanwhile, during the manufacturing process of the display panel <NUM>, an electric field may be formed in each pixel PX or each sub-pixel PXn so as to align the light-emitting elements <NUM>. Specifically, during the manufacturing process, a dielectrophoretic force may be applied to the light-emitting elements <NUM> using a dielectrophoresis method to align the light-emitting elements <NUM>. Since the ground voltage is applied to the first electrode lines <NUM> and an alternating voltage (AC) is applied to the second electrode lines <NUM> to form an electric field in the pixel PX or the sub-pixel PXn, the light-emitting elements <NUM> may receive the dielectrophoretic force through the electric field to be aligned between electrodes.

<FIG> is a circuit diagram illustrating one pixel of <FIG>.

Each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may be connected to at least one among the data lines DL1 to DLm, at least one among the scan lines SL1 to SLn, and the first voltage line QVDDL. The data lines DLj may transmit data signals to the sub-pixels PXn, a scan line SLk may transmit scan signals GW and GB to the sub-pixels PXn, and the first voltage line QVDDL may transmit a driving current or an alignment signal to the sub-pixels PXn.

Meanwhile, in this disclosure, terms "first," "second," and the like are used to refer to each of components, but these are used to simply distinguish the components from each other and do not necessarily refer to a corresponding component. That is, the components defined as first, second, and the like are not necessarily limited to a specific structure or location and, in some cases, other numbers may be assigned to the components. Therefore, the number assigned to each component may be described through the drawings and the following description, and a first component mentioned below may be a second component within the technical idea of the present invention.

Each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may include the light-emitting elements <NUM>, a plurality of transistors for supplying a current to the light-emitting elements <NUM>, and at least one capacitor.

The plurality of transistors includes a first transistor TR1 for applying a driving voltage to the light-emitting elements <NUM>, and a second transistor TR2 for applying a data signal DATA to a gate electrode of the first transistor TR1.

In <FIG>, although the sub-pixel PXn has been illustrated as being a two transistor-one capacitor (2T1C) structure having one first transistor TR1, one second transistor TR2, and one capacitor Cst, the present invention is not limited thereto. The sub-pixel PXn may include a greater number of transistors and a plurality of capacitors.

Each of the first and second transistors TR1 and TR2 includes a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other thereof may be a drain electrode.

Each of the first and second transistors TR1 and TR2 may be formed of a thin film transistor. In addition, in <FIG>, although each of the first and second transistors TR1 and TR2 has been described as being formed of a p-type metal oxide semiconductor field effect transistor (MOSFET), the present invention is not limited thereto. Each of the first transistor TR1 and the second transistor TR2 may be formed of an n-type MOSFET. In this case, positions of the source electrode and the drain electrode of each of the first transistor TR1 and the second transistor TR2 may be changed. Hereinafter, a case in which each of the first and second transistors TR1 and TR2 is formed of a P-type MOSFET will be described.

One end of the light-emitting element <NUM> is connected to the first electrode line <NUM> of the display panel <NUM>, and the other end thereof is connected to the second electrode line <NUM>. As described below, one of the first electrode line <NUM> and the second electrode line <NUM> may be an anode electrode, and the other one thereof may be a cathode electrode. However, the present invention is not limited thereto and may be possible to be reversed. Hereinafter, a case in which the first electrode line <NUM> is an anode electrode and the second electrode line <NUM> is a cathode electrode will be described.

The first electrode line <NUM> connected to the light-emitting element <NUM> may be connected to a third node N3 of <FIG>, and the second electrode line <NUM> may be connected to the second voltage line QVSSL. The light-emitting element <NUM> may receive a predetermined current or a predetermined signal transmitted to a first node N1 through the third node N3.

The first transistor TR1 (or a driving transistor) may include a first electrode connected (or electrically connected) to the first node N1, a second electrode connected to the first voltage line QVDDL, and a gate electrode connected to a second node N2. The first transistor TR1 may provide a driving voltage applied from the first voltage line QVDDL to the light-emitting element <NUM> based on a voltage of the second node N2 (or a voltage stored in the capacitor Cst which will described below).

The second transistor TR2 (or a switching transistor) may include a first electrode connected to the data line DLj (j is an integer satisfying <NUM>≤j≤m), a second electrode connected to the second node N2, and a gate electrode connected to the first scan line SLk (k is an integer satisfying <NUM>≤k≤n) which supplies a first scan signal GW. In response to the first scan signal GW, the second transistor TR2 may be turned to transmit the data signal DATA, which is transmitted from the data line DLj, to the first node N2.

The capacitor Cst may be connected between the second node N2 and the first voltage line QVDDL. The capacitor Cst may store or maintain the data signal DATA which is provided.

Hereinafter, structures and arrangements of members disposed in each sub-pixel PXn will be described.

<FIG> is an enlarged schematic diagram of portion A of <FIG>. <FIG> may be understood as an enlarged view by rotating portion A of <FIG> by as much as <NUM>°.

Referring to <FIG>, each pixel PX may include the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3. The first sub-pixel PX1, second sub-pixel PX2, and third sub-pixel PX3 of each pixel PX may be disposed in the form of a matrix in regions by a cross structure of scan lines SLk and SLk+<NUM> and data lines DLj, DLj+<NUM>, DLj+<NUM>, and DLj+<NUM>. The scan lines SLk and SLk+<NUM> may be disposed to extend to be long in the first direction (X-axis direction), and the data lines DLj, DLj+<NUM>, DLj+<NUM>, and DLj+<NUM> may be disposed to extend to be long in the second direction (Y-axis direction) intersecting the first direction (X-axis direction).

Each of the first sub-pixel PX1, second sub-pixel PX2, and third sub-pixel PX3 includes the first electrode line <NUM>, the second electrode line <NUM>, and the plurality of light-emitting elements <NUM>. The first electrode line <NUM> and the second electrode line <NUM> are electrically connected to the light-emitting elements <NUM> and each receives a voltage so as to allow the light-emitting elements <NUM> to emit light. Here, the voltage applied to allow the light-emitting elements <NUM> to emit light is transmitted through the first transistor TR1 of <FIG>.

In addition, at least a portion of each of the electrode lines <NUM> and <NUM> may be utilized to form an electric field in the pixel PX so as to align the light-emitting elements <NUM>. The voltage applied to allow the light-emitting elements <NUM> to be aligned may be transmitted through the first transistor TR1 of <FIG>.

A plurality of electrode lines <NUM> and <NUM> includes a first electrode line <NUM> and a second electrode line <NUM>. In an example, the first electrode line <NUM> may be a pixel electrode which is separated in each pixel PX, and the second electrode line <NUM> may be a common electrode which is commonly connected along the plurality of pixels PX. One of the first electrode line <NUM> and the second electrode line <NUM> may be an anode electrode of the light-emitting element <NUM>, and the other one thereof may be a cathode electrode of the light-emitting element <NUM>. However, the present invention is not limited thereto and may be possible to be reversed.

The first electrode line <NUM> and the second electrode line <NUM> may include electrode stem portions <NUM> and <NUM> disposed to extend in the first direction (X-axis direction) and at least one electrode branch portions 210B and 220B extending in the second direction (Y-axis direction) intersecting the first direction and branching off from the electrode stem portions <NUM> and <NUM>.

Specifically, the first electrode line <NUM> may include the first electrode stem portion <NUM> disposed to extend in the first direction (X-axis direction), and at least one first electrode branch portion 210B branching off from the first electrode stem portion <NUM> to extend in the second direction (Y-axis direction).

The first electrode stem portion <NUM> of any one pixel may be disposed substantially collinear with a first electrode stem portion <NUM> of an adjacent sub-pixel PXn (e.g., which is adjacent in the first direction (X-axis direction) belonging to the same row. In other words, two ends of the first electrode stem portion <NUM> of one pixel are spaced apart and terminated between the pixels PX, and a first electrode stem portion <NUM> of an adjacent pixel may be aligned with an extension line of the first electrode stem portion <NUM> of the one pixel. Thus, the first electrode stem portion <NUM> disposed in each pixel PXn may apply different electrical signals to first electrode branch portions 21B, and the first electrode branch portions 210B may be driven separately.

An arrangement of the first electrode stem portion <NUM> may be formed such that a single connected stem electrode is formed during the manufacturing process and then disconnected through a laser or the like before the light-emitting elements <NUM> are aligned.

The first electrode branch portion 21B may branch off from at least a portion of the first electrode stem portion <NUM> and may be disposed to extend in the second direction (Y-axis direction). The first electrode branch portion 210B may be terminated in a state of being spaced apart from the second electrode stem portion <NUM> which is disposed to be opposite to the first electrode stem portion <NUM>.

In addition, one or more first electrode branch portions 210B may be disposed in each pixel PX. <FIG> illustrates that two first electrode branch portions 210B are disposed, and the second electrode branch portion 220B is disposed therebetween, but the present invention is not limited thereto, and a greater number of first electrode branch portions 210B may be disposed. In some embodiments, the second electrode branch portion 220B is disposed between the first electrode branch portions 210B so that each sub-pixel PXn may have a symmetrical structure based on the second electrode branch portion 220B. However, the present invention is not limited thereto.

The second electrode line <NUM> may include the second electrode stem portion <NUM> which extends in the first direction (X-axis direction) and is disposed to be spaced apart from and opposite to the first electrode stem portion <NUM>, and at least one second electrode branch portion 220B which branches off from the second electrode stem portion <NUM> and extends in the second direction (Y-axis direction) to be spaced apart from and opposite to the first electrode branch portion 210B. However, one end portion of the second electrode stem portion <NUM> may extend to a plurality of adjacent pixels PXn in a first direction D1. Thus, the two ends of the second electrode stem portion <NUM> of any one pixel may be connected to one end of a second electrode stem portion <NUM> of an adjacent pixel among the pixels PX.

The second electrode branch portion 220B may be spaced apart from and opposite to the first electrode branch portion 210B and terminated in a state of being spaced apart from the first electrode stem portion <NUM>. That is, one end portion of the second electrode branch portion 220B may be connected to the second electrode stem portion <NUM>, and the other end portion thereof may be disposed in the pixel PX in a state of being spaced apart from the first electrode stem portion <NUM>.

The first electrode branch portion 210B extends in one direction of the second direction (Y-axis direction), and the second electrode branch portion 220B extends in the other direction of the second direction (Y-axis direction) so that the one end portions of the branch portions may be disposed in opposite directions based on a central portion of the pixel PX. However, the present invention is not limited thereto, and the first electrode stem portion <NUM> and the second electrode stem portion <NUM> may be disposed to be spaced apart from each other in the same direction based on the central portion of the pixel PX. In this case, the first electrode branch portion 210B and the second electrode branch portion 220B branching off from the electrode stem portions <NUM> and <NUM>, respectively, may extend in the same direction.

The plurality of light-emitting elements <NUM> may be disposed between the first electrode branch portion 210B and the second electrode branch portion 220B. One end portions of at least some of the plurality of light-emitting elements <NUM> may be electrically connected to the first electrode branch portion 210B and the other end portions thereof may be electrically connected to the second electrode branch portion 220B.

The plurality of light-emitting elements <NUM> may be spaced apart from each other in the second direction (Y-axis direction) and disposed substantially parallel to each other. A separation gap between the light-emitting elements <NUM> is not particularly limited. In some cases, the plurality of light-emitting elements <NUM> may be disposed adjacent to each other to form a group, and a plurality of other light-emitting elements <NUM> may be grouped in a state of being spaced at regular intervals from each other, may have a nonuniform density, and may be oriented and aligned in one direction.

A contact electrode <NUM> may be disposed on each of the first electrode branch portion 210B and the second electrode branch portion 220B.

A plurality of contact electrodes <NUM> is disposed to extend in the second direction (Y-axis direction) and disposed to be spaced apart from each other in the first direction (X-axis direction). The contact electrode <NUM> is in contact with at least one end portion of the light-emitting element <NUM>, and the contact electrode <NUM> is in contact with the first electrode line <NUM> or the second electrode line <NUM> to receive an electrical signal. Thus, the contact electrode <NUM> transmits an electrical signal, which is transmitted from each of the electrode lines <NUM> and <NUM>, to the light-emitting element <NUM>.

The contact electrode <NUM> may be disposed to partially cover the electrode branch portions 210B and 220B on each of the electrode branch portions 210B and 220B and includes a first contact electrode <NUM> and a second contact electrode <NUM> which are in contact with one end portion or the other end portion of the light-emitting element <NUM>.

The first contact electrode <NUM> may be disposed on the first electrode branch portion 210B and may be in contact with one end portion of the light-emitting element <NUM> which is electrically connected to the first electrode line <NUM>. The second contact electrode <NUM> may be disposed on the second electrode branch portion 220B and may be in contact with the other end portion of the light-emitting element <NUM> which is electrically connected to the second electrode line <NUM>.

In some embodiments, the two end portions of the light-emitting element <NUM> electrically connected to the first electrode branch portion 210B or the second electrode branch portion 220B may be conductive semiconductor layers doped with an n-type or p-type. When one end portion of the light-emitting element <NUM> electrically connected to the first electrode branch portion 210B is a conductive semiconductor layer doped with a p-type, the other end portion of the light-emitting element <NUM> electrically connected to the second electrode branch portion 220B may be a conductive semiconductor layer doped with an n-type. However, the present invention is not limited thereto and may be possible to be reversed.

Meanwhile, the first electrode stem portion <NUM> may be electrically connected to the first transistor TR1, which will be described below, through an electrode contact hole CNTD. In addition, although not shown in the drawings, the second electrode stem portion <NUM> may be connected to the second voltage line QVSSL through an electrode contact hole located in the non-display area NDA. In this case, unlike the first electrode stem portion <NUM>, in each sub-pixel PXn, a separate electrode contact hole may be omitted from the second electrode stem portion <NUM>. However, the present invention is not limited thereto, and a predetermined electrode contact hole may be formed even in the second electrode stem portion <NUM> so that the second electrode stem portion <NUM> may be electrically connected to the second voltage line QVSSL.

Meanwhile, <FIG> illustrates only a plan view in which the first electrode line <NUM>, the second electrode line <NUM>, and the light-emitting elements <NUM> of the display panel <NUM> are disposed. However, as described below, the first electrode line <NUM> and the second electrode line <NUM> of the display panel <NUM> may be electrically connected to members disposed in the circuit element layer which is located below the first electrode line <NUM> and the second electrode line <NUM>. The members disposed in the circuit element layer may constitute, including a semiconductor layer and a plurality of conductive layers, a plurality of elements.

Hereinafter, a specific configuration of the display panel <NUM> will be described in detail with reference to a plan view and a cross-sectional view of the display panel <NUM>.

<FIG> is a cross-sectional view illustrating a circuit element layer taken along line I-I' of <FIG>. <FIG> is a partial plan view illustrating the circuit element layer according to one embodiment, and <FIG> is a cross-sectional view taken along line IIa-IIa' of <FIG>. <FIG> is a cross-sectional view illustrating the display element layer taken along lines I-I' and II-II' of <FIG>.

According to one embodiment, the display panel <NUM> includes a circuit element layer 10a and a display element layer 10b. The circuit element layer 10a includes the first and second transistors TR1 and TR2 and the capacitor Cst, which are described with reference to <FIG>, and the display element layer 10b includes the first electrode line <NUM>, the second electrode line <NUM>, and the light-emitting element <NUM>. In the drawings, only a layout diagram with respect to one sub-pixel PXn is illustrated, but it is obvious that other sub-pixels PXn have the same layout. Hereinafter, a description will be made based on one sub-pixel PXn.

In addition, in the following description, even when some components are substantially the same as those mentioned in <FIG>, in order to easily describe an arrangement and a coupling relationship between the components, new reference numerals are assigned to these components.

Meanwhile, lines I-I' and II-II' of <FIG> may correspond to lines I-I' and II-II' of <FIG>, respectively. That is, it may be understood that the cross-sectional view shown in <FIG> illustrates components located in the circuit element layer 10a of the plan view of <FIG>. In addition, lines I-I' and II-II' of <FIG> correspond to lines I-I' and II-II' of <FIG>, and it may be understood that <FIG> partially illustrates components located in the display element layer 10b. Hereinafter, a plurality of members of the display panel <NUM> will be described in detail with reference to <FIG>.

Referring to <FIG>, the circuit element layer 10a includes a first transistor <NUM>, a second transistor <NUM>, a data line <NUM>, a conductive pattern <NUM>, a voltage line <NUM>, and a via layer <NUM>.

The display element layer 10b is disposed on the via layer <NUM> and includes banks <NUM> and <NUM>, reflective layers <NUM> and <NUM>, electrode layers <NUM> and <NUM>, a first insulating layer <NUM>, a first contact electrode <NUM>, a second contact electrode <NUM>, a second insulating layer <NUM>, and a passivation layer <NUM>. The reflective layers <NUM> and <NUM> and the electrode layers <NUM> and <NUM> may constitute the electrodes <NUM> and <NUM>.

Each of the above-described layers may be formed of a single layer or may also be formed of a stacked layer including a plurality of layers. In addition, another layer may be further disposed between the above-described layers. In particular, the circuit element layer 10a is not limited to the structure shown in <FIG>, and a greater number of conductive layers, insulating layers, and signal lines may be further disposed in the circuit element layer 10a.

Hereinafter, the circuit element layer 10a of the display panel <NUM> will be described with reference to <FIG>, and then the display element layer 10b will be described with reference to <FIG> and <FIG>.

First, referring to <FIG>, a substrate <NUM> supports layers disposed thereon. The substrate <NUM> may be an insulating substrate made of an insulating material such as glass, quartz, a polymer resin, or the like. Examples of a polymer material may include polyethersulphone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and a combination thereof. The substrate <NUM> may include a metal material.

In addition, the substrate <NUM> may be a rigid substrate or a flexible substrate which is bendable, foldable, rollable, and the like. However, the present invention is not limited thereto.

A buffer layer <NUM> may be disposed on the substrate <NUM>. The buffer layer <NUM> may prevent diffusion of impurity ions and infiltration of water or outdoor air and perform a surface planarization function. The buffer layer <NUM> may include silicon nitride, silicon oxide, silicon oxynitride, or the like. Meanwhile, a plurality of other layers may be further disposed between the substrate <NUM> and the buffer layer <NUM>.

The first transistor <NUM> (<NUM>, <NUM>, <NUM>, and <NUM>) and the second transistor <NUM> (<NUM>, <NUM>, <NUM>, and <NUM>) are disposed on the substrate <NUM>. The first transistor <NUM> is a driving transistor for driving the display element layer 10b as the first transistor TR1 of <FIG>, and the second transistor <NUM> is a switching transistor for transmitting the data signal DATA to the first transistor TR1 as the second transistor TR2 of <FIG>.

The first transistor <NUM> includes a first gate electrode <NUM>, a first active layer <NUM>, a first source electrode <NUM>, and a first drain electrode <NUM>. The second transistor <NUM> includes a second gate electrode <NUM>, a second active layer <NUM>, a second source electrode <NUM>, and a second drain electrode <NUM>.

The first gate electrode <NUM> and the second gate electrode <NUM> are disposed on the buffer layer <NUM>. The first gate electrode <NUM> constitutes a gate electrode of the first transistor <NUM>, and the second gate electrode <NUM> constitutes a gate electrode of the second transistor <NUM>. Each of the first gate electrode <NUM> and the second gate electrode <NUM> may be formed of a conductive metal layer. For example, each of the first gate electrode <NUM> and the second gate electrode <NUM> may include one or more metals selected from among molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

The first gate insulating film <NUM> is disposed on the first gate electrode <NUM> and the second gate electrode <NUM>. The first gate insulating film <NUM> is a gate insulating film having a gate insulating function. The first gate insulating film <NUM> may include a silicon compound, metal oxide, or the like. For example, the first gate insulating film <NUM> may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These may be used alone or as a combination thereof. The first gate insulating film <NUM> may be a single layer or a multiple layer made of stacked layers of different materials.

The first active layer <NUM> and the second active layer <NUM> are disposed on the first gate insulating film <NUM>. The first active layer <NUM> and the second active layer <NUM> are active layers forming channels of the first transistor <NUM> and the second transistor <NUM>. Each of the first active layer <NUM> and the second active layer <NUM> includes a channel region.

The first active layer <NUM> may overlap the first gate electrode <NUM> with the first gate insulating film <NUM> interposed therebetween, and the overlapping region may form a first channel region. The second active layer <NUM> may overlap the second gate electrode <NUM> with the first gate insulating film <NUM> interposed therebetween, and the overlapping region may form a second channel region.

Each of the first active layer <NUM> and the second active layer <NUM> is made of an oxide semiconductor. The oxide semiconductor may include a binary compound (ABx), a ternary compound (ABxCy), or a tetra compound (ABxCyDz), which contains indium, zinc, gallium, tin, Ti, Al, hafnium (Hf), zirconium (Zr), Mg, and the like. In one embodiment, the oxide semiconductor may include an indium tin zinc oxide (ITZO) (which is an oxide including indium, tin, and Ti) or indium gallium zinc oxide (IGZO) (which is an oxide including indium, gallium, and tin). That is, according to one embodiment, each of the first transistor <NUM> and the second transistor <NUM> may have a bottom-gate structure in which a channel region is disposed above the gate electrodes <NUM> or <NUM>, and the channel region may include an oxide semiconductor. Thus, when the display device <NUM> is manufactured, a manufacturing cost of the circuit element layer 10a may be reduced.

The first source/drain electrodes <NUM> and <NUM> and the second source/drain electrodes <NUM> and <NUM> are disposed on the first active layer <NUM> and the second active layer <NUM> on the first gate insulating film <NUM>. The first source electrode <NUM> is disposed on one side of the first active layer <NUM>, and the first drain electrode <NUM> is disposed on the other side of the first active layer <NUM>. The second source electrode <NUM> is disposed on one side of the second active layer <NUM>, and the second drain electrode <NUM> is disposed on the other side of the second active layer <NUM>. Each of the first source/drain electrodes <NUM> and <NUM> and the second source/drain electrodes <NUM> and <NUM> may include one or more metals selected from among Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu.

Meanwhile, the data line <NUM> and the conductive pattern <NUM> are further disposed on the first gate insulating film <NUM>. The data line <NUM> may transmit a data signal (hereinafter referred to as a "data signal DATA" in <FIG>). One side of the conductive pattern <NUM> is disposed on the data line <NUM>, and the other side thereof is disposed on the second source electrode <NUM> of the second transistor <NUM>. The second transistor <NUM> may receive the data signal DATA transmitted to the data line <NUM> through the conductive pattern <NUM>.

Specifically, to describe with reference to <FIG>, <FIG>, and <FIG>, the data line <NUM> may extend in one direction. As shown in <FIG>, the data line <NUM> may extend in the second direction (Y-axis direction) and cross the boundary of the pixel PX or the sub-pixel PXn to extend to an adjacent pixel PX or sub-pixel PX. The data line <NUM> may be disposed on one side of one pixel or one sub-pixel, for example, disposed adjacent to a left of one pixel or one sub-pixel.

The gate line GL may extend in one direction and may partially overlap the data line <NUM>. The gate line GL may extend in the first direction (X-axis direction) and overlap the data line <NUM> which extends in the second direction (Y-axis direction). According to one embodiment, the data line <NUM> may include a protrusion 191a protruding in the first direction (X-axis direction) in a region overlapping the gate line GL.

The protrusion 191a of <FIG> may be the data line <NUM> of <FIG>. The protrusion 191a of the data line <NUM> may protrude in the first direction (X-axis direction) and may be spaced apart from the second source electrode <NUM> of the second transistor <NUM> and terminated. The protrusion 191a of the data line <NUM> and the second source electrode <NUM> of the second transistor <NUM> may be disposed to be spaced apart from each other, and the conductive pattern <NUM> may be disposed between the protrusion 191a and the second source electrode <NUM>.

The data line <NUM> and the conductive pattern <NUM> may include the same material as the second source electrode <NUM>. That is, the conductive pattern <NUM> may include a conductive metal material and may electrically connect the data line <NUM> to the second source electrode <NUM>. The data signal DATA transmitted from the data line <NUM> may be transmitted to the second source electrode <NUM> of the second transistor <NUM> through the protrusion 191a and the conductive pattern <NUM>.

A first protection film <NUM> is disposed on the first source/drain electrodes <NUM> and <NUM>, the second source/drain electrodes <NUM> and <NUM>, the data line <NUM>, and the conductive pattern <NUM>. The first protection film <NUM> may be formed of an inorganic layer, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer thereof.

The voltage line <NUM> is disposed on the first protection film <NUM>. Although not shown in the drawings, the voltage line <NUM> may be electrically connected to the first transistor <NUM> to transmit a voltage signal "QVDD" or "QVSS" (see <FIG>) thereto. The voltage line <NUM> may extend in one direction. The voltage line <NUM> may extend in the second direction (Y-axis direction) and cross the boundary of the pixel PX or the sub-pixel PXn to extend to an adjacent pixel PX or sub-pixel PX. The voltage line <NUM> may be disposed on one side of one pixel or one sub-pixel, for example, disposed adjacent to a right of one pixel or one sub-pixel.

A second protection film <NUM> is disposed on the voltage line <NUM> and the first protection film <NUM>. The second protection film <NUM> may be disposed to cover, including the voltage line <NUM>, other members not shown in the drawings. The second protection film <NUM> may perform substantially the same function as the first protection film <NUM>.

The via layer <NUM> may be formed on the second protection film <NUM>. The via layer <NUM> may be disposed to cover an entirety of the circuit element layer 10a and may perform a function of supporting members of the display element layer 10b, which will be described below. In addition, the via layer <NUM> may perform a function of planarizing a step due to the first and second transistors <NUM> and <NUM> of the circuit element layer 10a and the voltage line <NUM>. The via layer <NUM> may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

Meanwhile, as described below, the first drain electrode <NUM> of the first transistor <NUM> may be electrically connected to the first electrode line <NUM> of the display element layer 10b, which will be described below, through the electrode contact hole CNTD passing through the via layer <NUM>, the second protection film <NUM>, and the first protection film <NUM>. The first transistor <NUM> may be connected to the voltage line <NUM> and the second drain electrode <NUM> of the second transistor <NUM> and may transmit an electrical signal to the first electrode line <NUM> of the display element layer 10b.

In <FIG>, only some members of the circuit element layer 10a have been illustrated, and the present embodiment is not limited thereto. The circuit element layer 10a may include a greater number of members not shown in the drawings.

Next, the display element layer 10b will be described with reference to <FIG> and <FIG>.

A plurality of banks <NUM>, <NUM>, and <NUM> are disposed on the via layer <NUM>. The plurality of banks <NUM>, <NUM>, and <NUM> are disposed to be separated from each other in each sub-pixel PXn. The plurality of banks <NUM>, <NUM>, and <NUM> includes the first bank <NUM> and the second bank <NUM> which are disposed adjacent to a central portion of the sub-pixel PXn, and the third bank <NUM> disposed at a boundary between the sub-pixels PXn.

When an ink I is sprayed using an inkjet printing device during the manufacturing of the display panel <NUM>, the third bank <NUM> may perform a function of blocking the ink I from crossing a boundary of the sub-pixel PXn. In addition, when the display panel <NUM> further includes other members, the other members may be disposed on the third bank <NUM> and the third bank <NUM> may perform a function of supporting the other members. However, the present invention is not limited thereto.

The first bank <NUM> and the second bank <NUM> are disposed to be separated from and opposite to each other. The first electrode line <NUM> is disposed on the first bank <NUM>, and the second electrode line <NUM> is disposed on the second bank <NUM>. Referring to <FIG> and <FIG>, it can be understood that the first electrode branch portion 210B is disposed on the first bank <NUM>, and the second bank <NUM> is disposed on the second bank <NUM>.

As described above, the first bank <NUM>, the second bank <NUM>, and the third bank <NUM> may be formed substantially in the same process. Thus, the banks <NUM>, <NUM>, and <NUM> may constitute a single grid pattern. Each of the plurality of banks <NUM>, <NUM>, and <NUM> may include polyimide (PI).

Each of the plurality of banks <NUM>, <NUM>, and <NUM> may have a structure in which at least a portion protrudes from the via layer <NUM>. The banks <NUM>, <NUM>, and <NUM> may protrude upward from a flat surface on which the light-emitting element <NUM> is disposed, and at least a part of each of the protruding portions may have a slope. A shape of each of the banks <NUM>, <NUM>, and <NUM> having the protruding structures is not particularly limited. As shown in the drawing, the first bank <NUM> and the second bank <NUM> protrude to the same height, and the third bank <NUM> may have a shape protruding to a higher position.

Reflective layers <NUM> and <NUM> may be disposed on the first bank <NUM> and the second bank <NUM>, and electrode layers <NUM> and <NUM> may be disposed on the reflective layers <NUM> and <NUM>. The reflective layers <NUM> and <NUM> and the electrode layers <NUM> and <NUM> may constitute the electrodes <NUM> and <NUM>.

The reflective layers <NUM> and <NUM> include a first reflective layer <NUM> and a second reflective layer <NUM>. The first reflective layer <NUM> may cover the first bank <NUM>, and the second reflective layer <NUM> may cover the second bank <NUM>. Portions of the reflective layers <NUM> and <NUM> are electrically connected to the circuit element layer 10a through a contact hole passing through the via layer <NUM>.

Each of the reflective layers <NUM> and <NUM> may include a material having high reflectance to reflect light emitted from the light-emitting element <NUM>. For example, each of the reflective layers <NUM> and <NUM> include a material such as Ag, Cu, ITO, IZO, or ITZO, but the present invention is not limited thereto.

The electrode layers <NUM> and <NUM> include a first electrode layer 210B and a second electrode layer 220B. The electrode layers <NUM> and <NUM> may have patterns substantially equal to patterns of the reflective layers <NUM> and <NUM>. The first reflective layer <NUM> and the first electrode layer 210B are disposed to be spaced apart from the second reflective layer <NUM> and the second electrode layer 220B.

Each of the electrode layers <NUM> and <NUM> includes a transparent conductive material, and thus light emitted from the light-emitting element <NUM> may be incident on the reflective layers <NUM> and <NUM>. For example, each of the electrode layers <NUM> and <NUM> may include a material such as ITO, IZO, or ITZO, but the present invention is not limited thereto.

In some embodiments, the reflective layers <NUM> and <NUM> and the electrode layers <NUM> and <NUM> may form a structure in which one or more transparent conductive layers including ITO, IZO, or ITZO, and one or more metal layers including Ag or Cu are stacked. For example, the reflective layers <NUM> and <NUM> and the electrode layers <NUM> and <NUM> may form a stacked structure of ITO/Ag/ITO/IZO.

Meanwhile, in some embodiments, the first electrode line <NUM> and the second electrode line <NUM> may be formed as a single layer. That is, the reflective layers <NUM> and <NUM> and the electrode layers <NUM> and <NUM> may be formed as a single layer to transmit an electrical signal to the light-emitting element <NUM> and, simultaneously, reflect light. For example, each of the first electrode line <NUM> and the second electrode line <NUM> may include an alloy containing Al, Ni, and lanthanum (La) as a conductive material having high reflectance. However, the present invention is not limited thereto.

The first insulating layer <NUM> is disposed to partially cover the first electrode line <NUM> and the second electrode line <NUM>. The first insulating layer <NUM> may be disposed to cover most of upper surfaces of the first electrode line <NUM> and the second electrode line <NUM> and may expose portions of the first electrode line <NUM> and the second electrode line <NUM>. The first insulating layer <NUM> may be disposed to partially cover an area in which the first electrode line <NUM> is spaced apart from the second electrode line <NUM> and an area opposite to the area in which the first electrode line <NUM> is spaced apart from the second electrode line <NUM>.

The first insulating layer <NUM> is disposed to expose relatively flat upper surfaces of the first electrode line <NUM> and the second electrode line <NUM> and disposed to allow the electrode lines <NUM> and <NUM> to overlap inclined surfaces of the first bank <NUM> and the second bank <NUM>. The first insulating layer <NUM> forms a flat upper surface to allow the light-emitting element <NUM> to be disposed, and the flat upper surface extend toward the first electrode line <NUM><NUM> and the second electrode line <NUM> in one direction. The extension portion of the first insulating layer <NUM> is terminated at inclined surfaces of the first electrode line <NUM> and the second electrode line <NUM>. Thus, the contact electrodes <NUM> may be in contact with the exposed first electrode line <NUM> and the exposed second electrode line <NUM> and may be in smooth contact with the light-emitting element <NUM> on the flat upper surface of the first insulating layer <NUM>.

The first insulating layer <NUM> may protect the first electrode line <NUM> and the second electrode line <NUM> and, simultaneously, insulate the first electrode line <NUM> from the second electrode line <NUM>. In addition, the first insulating layer <NUM> may prevent the light-emitting element <NUM> disposed thereon from being damaged due to a direct contact with other members.

The light-emitting element <NUM> is disposed on the first insulating layer <NUM>. At least one light-emitting element <NUM> is disposed on the first insulating layer <NUM> between the first electrode line <NUM> and the second electrode line <NUM>. The light-emitting element <NUM> may include a plurality of layers disposed in a direction horizontal to the via layer <NUM>.

The light-emitting element <NUM> of the display panel <NUM> according to one embodiment includes the conductive semiconductors and the active layer, which are described above, and the conductive semiconductors and the active layer are sequentially disposed on the via layer <NUM> in a horizontal direction. As shown in the drawing, in the light-emitting element <NUM>, a first conductivity type semiconductor <NUM>, an active material layer <NUM>, a second conductivity type semiconductor <NUM>, and a conductive electrode layer <NUM> are sequentially disposed on the via layer <NUM> in the horizontal direction. However, the present invention is not limited thereto. The order of the plurality of layers disposed in the light-emitting element <NUM> may be the opposite. In some cases, when the light-emitting element <NUM> has another structure, the plurality of layers may be disposed in a direction perpendicular to the via layer <NUM>.

The second insulating layer <NUM> is partially disposed on the light-emitting element <NUM>. The second insulating layer <NUM> may protect the light-emitting element <NUM> and, simultaneously, perform a function of fixing the light-emitting element <NUM> during a process of manufacturing the display panel <NUM>. The second insulating layer <NUM> may be disposed to surround an outer surface of the light-emitting element <NUM>. That is, a portion of a material of the second insulating layer <NUM> may be disposed between a bottom surface of the light-emitting element <NUM> and the first insulating layer <NUM>. The second insulating layer <NUM> may extend between the first electrode branch portion 210B and the second electrode branch portion 220B in the second direction D2 to have an island shape or a linear shape when viewed in a plan view.

The contact electrodes <NUM> are disposed on the electrode lines <NUM> and <NUM> and the second insulating layer <NUM>. The first contact electrode <NUM> and the second contact electrode <NUM> are disposed to be spaced apart from each other on the second insulating layer <NUM>. Thus, the second insulating layer <NUM> may insulate the first contact electrode <NUM> from the second contact electrode <NUM>.

The first contact electrode <NUM> is in contact with at least the first electrode line <NUM>, which is exposed due to patterning of the first insulating layer <NUM>, and at least one end portion of the light-emitting element <NUM>. The second contact electrode <NUM> may be in contact with at least the second electrode line <NUM>, which is exposed due to the patterning of the first insulating layer <NUM>, and at least the other end portion of the light-emitting element <NUM>. The first and second contact electrodes 26a and 26b may be in contact side surfaces of the two end portions of the light-emitting element <NUM>, for example, the first conductivity type semiconductor <NUM>, the second conductivity type semiconductor <NUM>, or the conductive electrode layer <NUM>. As described above, the first insulating layer <NUM> forms the flat upper surface so that the contact electrodes <NUM> may be in smooth contact with the side surfaces of the light-emitting element <NUM>.

The contact electrode <NUM> may include a conductive material. For example, the contact electrode <NUM> may include ITO, IZO, ITZO, Al, or the like. However, the present invention is not limited thereto.

The passivation layer <NUM> may be formed on the second insulating layer <NUM> and the second contact electrode <NUM> and may perform a function of protecting the members of the display element layer 10b from an external environment.

Each of the first insulating layer <NUM>, the second insulating layer <NUM>, and the passivation layer <NUM>, which are described above, may include an inorganic insulating material or an organic insulating material. In an example, each of the first insulating layer <NUM>, and the passivation layer <NUM> may include a material such as SiOx, SiNx, SiOxNy, Al<NUM>O<NUM>, aluminum nitride (AlN), or the like. The second insulating layer <NUM> may be made of an organic insulating material including a photoresist or the like. However, the present invention is not limited thereto.

Hereinafter, the circuit element layer 10a of the display panel <NUM> according to another embodiment will be described.

<FIG> illustrate the above described display panel <NUM> including the first and second transistors <NUM> and <NUM> of the circuit element layer 10a, which have a structure in which the active layers <NUM> and <NUM>, each having a channel region, are formed above the gate electrodes <NUM> and <NUM>. However, the present invention is not limited thereto, and for example, the first and second transistors <NUM> and <NUM> may have other structures in which the active layers <NUM> and <NUM> are formed below the gate electrodes <NUM> and <NUM> or other conductive layers may further be included.

<FIG> is a cross-sectional view illustrating a circuit element layer according to another embodiment.

Referring to <FIG>, gate electrodes <NUM> and <NUM> are formed on active layers <NUM> and <NUM> including channel regions in a first transistor <NUM> and a second transistor <NUM>. That is, each of the first and second transistors <NUM> and <NUM> may have a top-gate structure.

The first active layer <NUM> and the second active layer <NUM> are disposed on a buffer layer <NUM>. The first active layer <NUM> and the second active layer <NUM> may include first conductorized regions 126a and 146a, second conductorized regions 126b and 146b, and channel regions 126c and 146c. The channel regions 126c and 146c may be disposed between the first conductorized regions 126a and 146a and the second conductorized regions 126b and 146b. As described above, each of the first and second active layers <NUM> and <NUM> may be an oxide semiconductor.

A first gate insulating film <NUM> is disposed on the first active layer <NUM> and the second active layer <NUM>. The first and second gate electrodes <NUM> and <NUM> are disposed on the first gate insulating film <NUM>. The first active layer <NUM> may overlap the first gate electrode <NUM> with the first gate insulating film <NUM> interposed therebetween, and the first channel region 126c is formed in the overlapping region. The second active layer <NUM> may overlap the second gate electrode <NUM> with the first gate insulating film <NUM> interposed therebetween, and the second channel region 146c is formed in the overlapping region.

Meanwhile, in the drawing, although the first gate insulating film <NUM> is disposed only between the first and second gate electrodes <NUM> and <NUM> and the first and second active layers <NUM> and <NUM>, the present invention is not limited thereto. That is, as shown in <FIG>, the first gate insulating film <NUM> may be disposed on an entirety of the buffer layer <NUM>, including the first and second active layers <NUM> and <NUM>.

The interlayer insulating film <NUM> is disposed on the first and second gate electrodes <NUM> and <NUM> and is disposed to cover an entirety of the first and second active layers <NUM> and <NUM> and the buffer layer <NUM>. A first contact hole CNT1 passing through the interlayer insulating film <NUM> to expose a portion of an upper surface of the first active layer <NUM>, and a second contact hole CNT2 exposing another portion of the upper surface thereof are formed in the interlayer insulating film <NUM>. A third contact hole CNT3 passing through the interlayer insulating film <NUM> to expose a portion of an upper surface of the second active layer <NUM>, and a fourth contact hole CNT4 exposing another portion of the upper surface thereof are formed in the interlayer insulating film <NUM>. The first contact hole CNT1 may expose a first conductorized region 126a of the first active layer <NUM>, the second contact hole CNT2 may expose a second conductorized region 126b of the first active layer <NUM>, the third contact hole CNT3 may expose a first conductorized region 146a of the second active layer <NUM>, and the fourth contact hole CNT4 may expose a second conductorized region 146b of the second active layer <NUM>.

First source/drain electrodes <NUM> and <NUM> and second source/drain electrodes <NUM> and <NUM> may be disposed on the first gate insulating film <NUM>. The first source electrode <NUM> is in contact with the first conductorized region 126a formed on one side of the first active layer <NUM> through the first contact hole CNT1. The first drain electrode <NUM> is in contact with the second conductorized region 126ba formed on the other side of the first active layer <NUM> through the second contact hole CNT2. The second source electrode <NUM> is in contact with the first conductorized region 146a formed on one side of the second active layer <NUM> through the third contact hole CNT3. The second drain electrode <NUM> is in contact with the second conductorized region 146b formed on the other side of the second active layer <NUM> through the fourth contact hole CNT4.

According to one embodiment, in the first transistor <NUM> and the second transistor <NUM>, gate electrodes <NUM> and <NUM> may be formed on the active layers <NUM> and <NUM>, and the active layers <NUM> and <NUM> include oxide semiconductors, and thus the channel regions 126c and 146c may be formed. Description of other members are the same as described above, and thus detailed description thereof will be omitted herein.

<FIG> is a cross-sectional view illustrating a circuit element layer according to still another embodiment.

Referring to <FIG>, a circuit element layer 10a according to one embodiment may further include a light blocking layer <NUM> disposed between a substrate <NUM> and a buffer layer <NUM>. In <FIG>, only a first transistor <NUM> is shown as one transistor, but this may be equally applied to a second transistor <NUM>.

At least one light blocking layer <NUM> may be disposed on the substrate <NUM>. The light blocking layer <NUM> may be disposed between the substrate <NUM> and the buffer layer <NUM> and may perform a function of blocking light incident on a first active layer <NUM> from the substrate <NUM>. The light blocking layer <NUM> is disposed to overlap the first active layer <NUM> disposed on the buffer layer <NUM>. For example, an area in which the light blocking layer <NUM> is disposed to cover the first active layer <NUM> may be greater than an area of the first active layer <NUM>. The light blocking layer <NUM> may include a material which absorbs incident light or blocks transmission of the incident light. For example, the light blocking layer <NUM> may be formed of a single layer or a multi-layer made of any one among Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof.

Meanwhile, the first transistor <NUM> and the second transistor <NUM> may be formed to have different structures and disposed on different layers.

<FIG> is a cross-sectional view illustrating a circuit element layer according to yet another embodiment.

Referring to <FIG>, in a circuit element layer 10a according to one embodiment, a plurality of interlayer insulating films 132a and 132b are disposed on a first active layer <NUM> of a first transistor <NUM>, and a second gate electrode <NUM> of a second transistor <NUM> is disposed between the interlayer insulating films 132a and 132b. The interlayer insulating films 132a and 132b include a first interlayer insulating film 132a and a second interlayer insulating film 132b, and the first interlayer insulating film 132a and the second interlayer insulating film 132b are sequentially disposed on the first active layer <NUM>. The second gate electrode <NUM> is disposed on the first interlayer insulating film 132a, and a second active layer <NUM> is disposed on the second interlayer insulating film 132b.

In <FIG>, the first transistor <NUM> may have a structure in which the first gate electrode <NUM> is formed on the first active layer <NUM> and may have substantially the same shape as the first transistor <NUM> of <FIG>. The first transistor <NUM> of <FIG> is the same as the first transistor <NUM> of <FIG>, except that the first contact hole CNT1 and the second contact hole CNT2 exposing the first conductorized region 126a and the second conductorized region 126b pass through the first and second interlayer insulating films 132a and 132b.

Meanwhile, in this case, the first active layer <NUM> of the first transistor <NUM> may include other semiconductor materials in addition to the oxide semiconductor. For example, the first active layer <NUM> may include polycrystalline silicon. The polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of the crystallization method may include a rapid thermal annealing (RTA) method, a solid phase crystallization (SPC) method, an excimer laser annealing (ELA) method, a metal induced crystallization (MIC) method, a metal induced lateral crystallization (MILC) method, a sequential lateral solidification (SLS) method, and the like, but the present invention is not limited thereto. Alternatively, the first active layer <NUM> may include monocrystalline silicon, low temperature polycrystalline silicon, amorphous silicon, or the like. However, the present invention is not limited thereto.

Hereinafter, a detailed description of the first transistor <NUM> will be omitted herein, and the second transistor <NUM> will be described.

The second transistor <NUM> includes the second gate electrode <NUM> disposed on the first interlayer insulating film 132a, the second active layer <NUM> disposed on the second interlayer insulating film 132b, and the second source/drain electrodes <NUM> and <NUM>. The data line <NUM> to which the data signal DATA is applied and the conductive pattern <NUM> connecting the data line <NUM> to the second source electrode <NUM> is also disposed on the second interlayer insulating film 132b.

The first active layer <NUM>, the second active layer <NUM>, the first gate electrode <NUM>, and the second gate electrode <NUM> are disposed on different layers. The first active layer <NUM> and the second active layer <NUM>, each including a semiconductor, may constitute a lower semiconductor layer and an upper semiconductor layer in the circuit element layer 10a.

In addition, in this case, the first transistor <NUM> and the second transistor <NUM> may be formed of different types of transistors. In the above description, although the first and second transistors <NUM> and <NUM> have been described as being formed as p-type MOSFETs, at least one of the first and second transistors <NUM> and <NUM> may be formed as an n-type MOSFET. In addition, one of the first and second transistors <NUM> and <NUM> may be formed as a p-type MOSFET, and the other one thereof may be formed as an n-type MOSFET. Detailed description of other members will be omitted herein.

Meanwhile, the light-emitting element <NUM> may include a semiconductor crystal to emit light of a specific wavelength range. The light-emitting element <NUM> may emit light toward an upper portion of the display element layer 10b.

<FIG> is a schematic diagram illustrating the light-emitting element according to one embodiment.

The light-emitting element <NUM> may be a light emitting diode (LED). Specifically, the light-emitting element <NUM> may be an inorganic LED having a micrometer unit or nanometer unit size and made of an inorganic material. The inorganic light emitting diode may be aligned between two electrodes in which polarity is formed by forming an electric field in a specific direction between the two electrodes facing each other. The light-emitting element <NUM> may be aligned between two electrodes due to an electric field formed on the two electrodes.

The light-emitting element <NUM> includes a semiconductor crystal doped with an arbitrary conductivity type (e.g., p-type or n-type) impurity. The semiconductor crystal may receive an electrical signal applied from an external power source and emit light in a specific wavelength range.

Referring to <FIG>, the light-emitting element <NUM> according to one embodiment may include a first conductivity type semiconductor <NUM>, a second conductivity type semiconductor <NUM>, an active material layer <NUM>, and an insulating film <NUM>. In addition, the light-emitting element <NUM> according to one embodiment may further include at least one conductive electrode layer <NUM>. Although the light-emitting element <NUM> has been illustrated as further including one conductive electrode layer <NUM> in <FIG>, the present invention is not limited thereto. In some cases, the light-emitting element <NUM> may include a greater number of conductive electrode layers <NUM> or the conductive electrode layers <NUM> may be omitted. A description of the light-emitting element <NUM>, which will be made below, may be identically applied even when the number of conductive electrode layers <NUM> is varied or another structure is further included.

The light-emitting element <NUM> may have a shape extending in one direction. The light-emitting element <NUM> may have a shape of nanorods, nanowires, nanotubes, or the like. In an embodiment, the light-emitting element <NUM> may have a cylindrical shape or a rod shape. However, the shape of the light-emitting element <NUM> is not limited thereto and may have various shapes such as a regular hexahedral shape, a rectangular parallelepiped shape, a hexagonal column shape, and the like. A plurality of semiconductors included in the light-emitting element <NUM>, which will be described below, may have a structure in which the semiconductors are sequentially disposed or stacked in the one direction.

The light-emitting element <NUM> according to one embodiment may emit light in a specific wavelength range. In an example, the active material layer <NUM> may emit blue light having a central wavelength range ranging from <NUM> to <NUM>. However, the central wavelength range of the blue light is not limited to the above range, and it should be understood that the central wavelength range includes all wavelength ranges which can be recognized as a blue color in the art. Further, the light emitted from the active material layer <NUM> of the light-emitting element <NUM> is not limited thereto, and the light may be green light having a central wavelength range ranging from <NUM> to <NUM> or red light having a central wavelength range ranging from <NUM> to <NUM>.

To describe the light-emitting element <NUM> in detail with reference to <FIG>, the first conductivity type semiconductor <NUM> may be an n-type semiconductor having, for example, a first conductivity type. For example, when the light-emitting element <NUM> emits light in a blue wavelength range, the first conductivity type semiconductor <NUM> may include a semiconductor material having a chemical formula of InxAlyGa<NUM>-x-yN (<NUM>≤x≤<NUM>, <NUM>≤y≤<NUM>, and <NUM>≤x+y≤<NUM>). For example, the semiconductor material may be one or more among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN which are doped with an n-type impurity. The first conductivity type semiconductor <NUM>' may be doped with a first conductive dopant. For example, the first conductivity type dopant may be Si, Ge, Sn, or the like. In an example, the first conductivity type semiconductor <NUM> may be n-GaN doped with n-type Si. A length of the first conductivity type semiconductor <NUM> may range from <NUM> to <NUM>, but the present invention is not limited thereto.

The second conductivity type semiconductor <NUM> is disposed on the active material layer <NUM> which will be described below. For example, the second conductivity type semiconductor <NUM> may be a p-type semiconductor having a second conductivity type. For example, when the light-emitting element <NUM> emits light in a blue or green wavelength range, the second conductivity type semiconductor <NUM> may include a semiconductor material having a chemical formula of InxAlyGa<NUM>-x-yN(<NUM>≤x≤<NUM>, <NUM>≤y≤<NUM>, and <NUM>≤x+y≤<NUM>). For example, the semiconductor material may be one or more among InAlGaN, GaN, AlGaNN, InGaN, AlN, and InN which are doped with an p-type impurity. The second conductivity type semiconductor <NUM> may be doped with a second conductive dopant. For example, the second conductive dopant may be Mg, Zn, Ca, Se, Ba, or the like. In an example, the second conductivity type semiconductor <NUM> may be p-GaN doped with p-type Mg. A length of the second conductivity type semiconductor <NUM> may range from <NUM> to <NUM>, but the present invention is not limited thereto.

Meanwhile, in the drawing, although each of the first conductivity type semiconductor <NUM> and the second conductivity type semiconductor <NUM> has been illustrated as being formed as one layer, the present invention is not limited thereto. In some cases, each of the first conductivity type semiconductor <NUM> and the second conductivity type semiconductor <NUM> may further include a greater number of layers, for example, a clad layer or a tensile strain barrier reducing (TSBR) layer according to a material of the active material layer <NUM>.

The active material layer <NUM> is disposed between the first conductivity type semiconductor <NUM> and the second conductivity type semiconductor <NUM>. The active material layer <NUM> may include a material having a single or multiple quantum well structure. When the active material layer <NUM> includes a material having a multiple quantum well structure, the active material layer <NUM> may have a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. The active material layer <NUM> may emit light due to a combination of electron-hole pairs in response to an electrical signal applied through the first conductivity type semiconductor <NUM> and the second conductivity type semiconductor <NUM>. An example, when the active material layer <NUM> emits light in a blue wavelength range, the active material layer <NUM> may include a material such as AlGaN, AlInGaN, or the like. In particular, when the active material layer <NUM> has a multi-quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layer may include a material such as AlGaN or AlInGaN, and the well layer may include a material such as GaN or AlInN. In an example, the active material layer <NUM> includes AlGaInN as the quantum layer and AlInN as the well layer. As described above, the active material layer <NUM> may emit blue light having a central wavelength range ranging from <NUM> to <NUM>.

However, the present invention is not limited thereto, and the active material layer <NUM> may have a structure in which a semiconductor material having large band gap energy and a semiconductor material having small band gap energy are alternately stacked or include different Group III to V semiconductor materials according to a wavelength range of emitted light. The active material layer <NUM> is not limited to emit light in the blue wavelength range, and in some cases, the active material layer <NUM> may emit light in a red or green wavelength range. A length of the active material layer <NUM> may range from <NUM> to <NUM>, but the present invention is not limited thereto.

Meanwhile, the light emitted from the active material layer <NUM> may be emitted to an outer surface of the light-emitting element <NUM> in a length direction and both side surfaces thereof. Directivity of the light emitted from the active material layer <NUM> is not limited in one direction.

The conductive electrode layer <NUM> may be an ohmic contact electrode. However, the present invention is not limited thereto, and the conductive electrode layer <NUM> may be a Schottky contact electrode. The conductive electrode layer <NUM> may include a conductive metal. For example, the conductive electrode layer <NUM> may include at least one among Al, Ti, In, Au, Ag, ITO, IZO, and ITZO. In addition, the conductive electrode layer <NUM> may include a semiconductor material doped with an n-type or p-type impurity. The conductive electrode layer <NUM> may include the same material or different materials, but the present invention is not limited thereto.

The insulating film <NUM> is disposed to surround the outer surfaces of the plurality of semiconductors which are described above. In an example, the insulating film <NUM> may be disposed to surround at least the outer surface of the active material layer <NUM> and may extend in one direction in which the light-emitting element <NUM> extends. The insulating film <NUM> may perform a function of protecting the members. As an example, the insulating film <NUM> may be formed to surround side surfaces of the members and expose two end portions of the light-emitting element <NUM> in the length direction.

In the drawing, the insulating film <NUM> has been illustrated as being formed to extend in the length direction of the light-emitting element <NUM> to cover from the first conductivity type semiconductor <NUM> to the conductive electrode layer <NUM>, but the present invention in not limited thereto. The insulating film <NUM> covers only the outer surfaces of some semiconductor layers including the active material layer <NUM> or covers only a portion of the outer surface of the conductive electrode layer <NUM> so that a portion of the outer surface of the conductive electrode layer <NUM> may be exposed.

A thickness of the insulating film <NUM> may range from <NUM> to <NUM>, but the present invention is not limited thereto. Preferably, the thickness of the insulating film <NUM> may be <NUM>.

The insulating film <NUM> may include materials having insulation properties, for example, SiOx, SiNx, SiOxNy, AlN, Al<NUM>O<NUM>, and the like. Thus, it is possible to prevent an electrical short circuit which may occur when the active material layer <NUM> is in direct contact with an electrode through which an electrical signal is transmitted to the light-emitting element <NUM>. In addition, since the insulating film <NUM> protects the outer surface of the light-emitting element <NUM> including the active material layer <NUM>, it is possible to prevent degradation in light emission efficiency.

In addition, in some embodiments, the outer surface of the insulating film <NUM> may be surface treated. When the display panel <NUM> is manufactured, the light-emitting element <NUM> may be sprayed onto an electrode in a state of being dispersed in a predetermined ink. Here, in order to allow the light-emitting element <NUM> to maintain the dispersed state without being agglomerated with adjacent another light-emitting element <NUM> in the ink, the insulating film <NUM> may be hydrophobically or hydrophilically surface treated.

Meanwhile, the light-emitting element <NUM> may have a length H ranging from <NUM> to <NUM> or from <NUM> to <NUM>, and preferably, about <NUM>. In addition, a diameter of the light-emitting element <NUM> may range from <NUM> to <NUM>, and an aspect ratio of the light-emitting element <NUM> may range from <NUM> to <NUM>. However, the present invention is not limited thereto, and the plurality of light-emitting elements <NUM> included in the display panel <NUM> may have different diameters according to a difference in composition of the active material layers <NUM>. Preferably, the diameter of the light-emitting element <NUM> may have a range of about <NUM>.

Meanwhile, the display panel <NUM> may further include a light-emitting element <NUM> having a structure different from the structure of the light-emitting element <NUM> of <FIG>.

<FIG> is a schematic diagram illustrating a light-emitting element according to another embodiment.

Referring to <FIG>, a light-emitting element <NUM>' may be formed such that a plurality of layers are not stacked in one direction and each of the plurality of layers surrounds an outer surface of another layer. The light-emitting element <NUM>' of <FIG> is the same as the light-emitting element <NUM> of <FIG> except that shapes of the layers are partially different from each other. Hereinafter, the same content will be omitted and differences will be described.

According to one embodiment, a first conductivity type semiconductor <NUM>' may extend in one direction and both end portions thereof may be formed to be inclined toward a central portion thereof. The first conductivity type semiconductor <NUM>' of <FIG> may have a shape in which a rod-shaped or cylindrical main body and conical-shaped end portions on upper and lower portions of the main body are formed. An upper end portion of the main body may have a slope that is steeper than a slope of a lower end portion thereof.

An active material layer <NUM>' is disposed to surround an outer surface of the main body of the first conductivity type semiconductor <NUM>'. The active material layer <NUM>' may have an annular shape extending in one direction. The active material layer <NUM>' may not be formed on upper and lower end portions of the first conductivity type semiconductor <NUM>'. That is, the active material layer <NUM>' may be in contact with only a parallel side surface of the first conductivity type semiconductor <NUM>'.

A second conductivity type semiconductor <NUM>' is disposed to surround an outer surface of the active material layer <NUM>' and the upper end portion of the first conductivity type semiconductor <NUM>'. The second conductivity type semiconductor <NUM>' may include an annular-shaped main body extending in one direction and an upper end portion having a side surface formed to be inclined. That is, the second conductivity type semiconductor <NUM>' may be in direct contact with a parallel side surface of the active material layer <NUM>' and an inclined upper end portion of the first conductivity type semiconductor <NUM>. However, the second conductivity type semiconductor <NUM>' is not formed in the lower end portion of the first conductivity type semiconductor <NUM>'.

An electrode material layer <NUM>' is disposed to surround an outer surface of the second conductivity type semiconductor <NUM>'. That is, a shape of the electrode material layer <NUM>' may be substantially the same as a shape of the second conductivity type semiconductor <NUM>'. That is, the electrode material layer <NUM>' may be entirely in contact with the outer surface of the second conductivity type semiconductor <NUM>'.

An insulating film <NUM>' may be disposed to surround the electrode material layer <NUM>' and the outer surface of the first conductivity type semiconductor <NUM>'. The insulating film <NUM>' may be in direct contact with, in addition to the electrode material layer <NUM>', the lower end portion of the first conductivity type semiconductor <NUM>', and exposed lower end portions of the active material layer <NUM>' and the second conductivity type semiconductor <NUM>'.

Claim 1:
A display device comprising:
a substrate (<NUM>);
a first transistor (<NUM>) disposed on the substrate;
a second transistor (<NUM>) disposed on the substrate, and configured to transmit a data signal to the first transistor,
a via layer (<NUM>) covering the first transistor and the second transistor to perform a function of planarizing a step due to first and second transistors;
a first bank (<NUM>) and a second bank (<NUM>) disposed on the via layer, and spaced apart from each other;
a first electrode line (<NUM>) disposed on the first bank;
a second electrode line (<NUM>) disposed on the second bank and spaced apart from the first electrode;
a first insulating layer (<NUM>) disposed to partially cover the first electrode line and the second electrode line;
a light-emitting element (<NUM>) disposed on the first insulating layer, and disposed between the first bank and the second bank, wherein the first transistor is configured to transmit a driving current to the light-emitting element;
a second insulating layer (<NUM>) partially disposed on the light-emitting element;
a first contact electrode (<NUM>) disposed on the first electrode line and the second insulating layer, and in contact with the light-emitting element; and
a second contact electrode (<NUM>) disposed on the second electrode line and the second insulating layer, and in contact with the light-emitting element,
wherein the first transistor includes a first active layer (<NUM>),
the second transistor includes a second active layer (<NUM>) containing an oxide semiconductor, and
the light-emitting element includes a first conductivity type semiconductor (<NUM>) having a first polarity;
a second conductivity type semiconductor (<NUM>) having a second polarity different from the first polarity; and
an active material layer (<NUM>) disposed between the first conductivity type semiconductor and the second conductivity type semiconductor.