Patent Description:
For a detailed description of various examples, reference will now be made to the accompanying drawings in which.

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to. " Also, the term "couple" or "couples" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. The recitation "based on" is intended to mean "based at least in part on. " Therefore, if X is based on Y, X may be based on Y and any number of other factors.

The following discussion is directed to various embodiments of the disclosure. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodirnent.

DAC circuits convert digital signals into analog signals. High DAC accuracy (e.g., <NUM> bit resolution) is desirable in many applications, such as medical devices, optical devices industrial control products, display drivers, etc. Higher accuracy DACs typically occupy significant circuit area, and increased bit accuracy generally results in significant increases in the number of switches and resistor elements. In addition, more calibration memory and calibration time are required for DAC circuits that provide high bit accuracy.

Conventional DAC circuits for microcontrollers provide either <NUM>-bit or lower resolution or have high die costs, a long calibration path, and/or a high degree of complexity. For example, some conventional DAC circuits require a relatively large number of switches for MSB interpolation. Additionally, some conventional DAC circuits include an interpolation amplifier adding complexity to the circuit. Therefore, it would be desirable for a DAC circuit to provide a highly accurate (e. g, <NUM> bit resolution), low cost, low complexity digital-to-analog conversion.

In accordance with various examples, a segmented DAC circuit is provided that utilizes an interpolation RDAC and a general buffer amplifier to generate an analog output signal from a digital input signal. The interpolation RDAC includes a MSB R-2R DAC to provide a coarse interpolation of the input signal and an ISB resistor ladder to generate the final interpolation of the input signal. The buffer amplifier receives the resulting interpolation signal and provides a unity voltage gain to the interpolation signal with a current gain. The resulting analog output signal is highly accurate (e.g., <NUM> bits) with a relatively low complexity (due to the use of the ISB resistor ladder instead and buffer amplifier instead of an interpolation amplifier) and cost. Such a DAC can be used in a wide variety of applications. In other words, the broad topology of such a circuit can be used for different function circuits. For example, such a DAC can be used for a digital control oscillator, a dot matrix LCD driver, etc..

<FIG> shows a block diagram of an illustrative segmented DAC circuit <NUM> in accordance with various examples. The segmented DAC <NUM> is configured to receive a K-bit binary-coded digital input signal (CODE) <NUM> (e.g., a <NUM> bit digital signal) and convert the CODE <NUM> into an analog output signal (VOUT) <NUM> which represents the value of the CODE <NUM>. The CODE <NUM> can be received from any suitable digital signal source (e.g., a microcontroller). The segmented DAC circuit <NUM> includes, in an embodiment, an input decoder <NUM>, calibration circuit <NUM>, calibration and dynamic element matching (DEM) circuit <NUM>, interpolation RDAC <NUM>, buffer amplifier <NUM>, ordered element matching (OEM) memory <NUM>, and multiplexers <NUM>-<NUM>. The decoder <NUM> is configured to receive the CODE <NUM> and buffer and parse the CODE <NUM> into three signals, MSB <NUM>, ISB 126I, and LSB, <NUM> without modification, For example, the CODE <NUM> includes an M-bit first subword (MSB), an I-bit second subword (ISB), and an L-bit third subword (LSB), where M, I, and L are each greater than <NUM>, and K= M+I+L. The first subword is referred to herein as an "MSB subword" with M bits that includes a most significant bit of the CODE <NUM>. The second subword is referred to herein as an "ISB" subword with I bits that includes intermediate significant bits of the CODE <NUM>. The third subword is referred to herein as an "LSB subword" with L bits that include the least significant bit of the CODE <NUM>. The decoder <NUM> buffers and parses the CODE <NUM> to output the M-bit first subword MSB <NUM> to an address input of calibration circuit <NUM>. The decoder <NUM> also outputs the I-bit second subword ISB 126I to an address input of calibration circuit <NUM> and the L-bit third subword LSB <NUM>. In an embodiment, for a <NUM> bit CODE <NUM>, the decoder <NUM> outputs a <NUM> bit MSB <NUM>, a <NUM> bit ISB 126I, and a <NUM> bit LSB <NUM>. In some embodiments, the decoder <NUM> performs additional, other digital signal operations on the CODE <NUM>. Furthermore, in some embodiments, the decoder <NUM> is omitted.

The calibration circuit <NUM>, in an embodiment, is configured to store calibration data indexed according to the first subword MSB <NUM> received at a first address input from the decoder <NUM> or according to the second subword ISB 126I received at a second address input from the decoder <NUM>. For example, the calibration circuit <NUM> can store a first set of K x M bits of calibration data for calibration of the first subword MSB <NUM> and a second set of K x M bits of calibration data for calibration of the second subword ISB <NUM>. In some embodiments, the calibration circuit <NUM> provides a calibration code CAL CODE from the calibration data based on the CODE <NUM>.

In addition to calibration circuit <NUM> receiving the first subword MSB <NUM>, the multiplexer <NUM> also, in an embodiment, is configured to receive the first subword MSB <NUM> as a first input. The second input of the multiplexer <NUM> is an M-bit OEM signal <NUM> received from the OEM memory <NUM>. Thus, in an embodiment, the OEM signal <NUM> has the same number of bits as the first subword MSB <NUM>. The enable or select signal OEM_EN <NUM> is also received by the multiplexer <NUM> which provides a signal for the multiplexer <NUM> to output, labelled as output signal <NUM>, either the OEM signal <NUM> or the first subword MSB <NUM>,.

The calibration and OEM circuit <NUM> is configured to receive a calibration code from the calibration circuit <NUM>. The calibration and DEM circuit <NUM>, in some embodiments, also receives the second subword ISB 126I and third subword LSB <NUM> from the decoder <NUM>. The calibration and OEM circuit <NUM> includes, in an embodiment, a sigma delta modulator (SDM) <NUM> which is a first-order modulator; however, in other embodiments, second order or higher order modulators can be used. The calibration and DEM circuit <NUM> generates a modulator code SDCODE for the SDM <NUM> based on the calibration code received from the calibration circuit <NUM>, the second subword ISB <NUM>, and the third subword LSB <NUM>. In an embodiment, the SDM <NUM> modulates the modulator code SDCODE to generate an N-bit digital interpolation code signal ICODE <NUM> that represents a value of the second subword ISB 126I and third subword LSB <NUM> where N is less than I+L,.

The multiplexer <NUM>, in an embodiment, is configured to receive the third subword LSB <NUM> as a first input and the ICODE <NUM> as a second input. The enable or select signal RES_SEL <NUM> is also received by the multiplexer <NUM> which provides a signal for the multiplexer <NUM> to output, labelled as output signal <NUM>, either the third subword LSB <NUM> or the ICODE <NUM>. For example, in one state of RES_SEL <NUM>, the multiplexer <NUM> provides the N-bit ICODE <NUM> to the interpolation RDAC <NUM> for (M+I+L)-bit resolution (e.g., <NUM> bit resolution for a <NUM>-bit CODE <NUM>). In another state of RES_SEL <NUM>, the multiplexer <NUM> provides the third subword LSB <NUM> to the interpolation RDAC <NUM> for lower resolution.

The interpolation RDAC <NUM> is configured to receive, in an embodiment, the output signal <NUM> from multiplexer <NUM> and the output signal <NUM> from multiplexer <NUM>. The interpolation RDAC <NUM> includes an M-bit MSB R-2R DAC <NUM> and an I-bit ISB resistor ladder <NUM>. In an embodiment, the MSB R-2R DAC <NUM> receives the output signal <NUM> from the multiplexer <NUM>. The MSB R-2R DAC <NUM> includes, in some embodiments, a resistor circuit and a switching circuit that operates according to the M-bit input from the output signal <NUM>. The MSB R-2R DAC <NUM> operates according to a reference voltage and an analog voltage divider to output a first analog output signal. For example, the MSB R-2R DAC <NUM> is configured to receive reference voltages VrefH <NUM> and VrefL <NUM>. A voltage divider circuit is formed by resistors in the MSB R-2R DAC <NUM> to provide the first analog output signal at or between the levels of the reference voltages VrefH <NUM> and VrefL <NUM> according to the M-bit input from the multiplexer <NUM>. In operation, when the multiplexer <NUM> delivers the first subword MSB <NUM>, the first analog output signal represents the value of the first subword MSB <NUM>. In the example shown in <FIG>, the MSB R-2R DAC <NUM> generates a differential first analog output signal VH <NUM>, VL <NUM>. In other embodiments, the MSB R-2R DAC <NUM> generates a single-ended first analog output signal. In some embodiments, the MSB R-2R DAC <NUM> includes a resistive chopper circuit operating according to a single or multi-bit chopper switching control signal (chop) <NUM>,.

The ISB resistor ladder <NUM> is configured to receive the first analog output signal VH <NUM>, VL <NUM> from the MSB R-2R DAC <NUM>. The ISB resistor ladder <NUM> is, in an embodiment, a resistor ladder that generates an analog interpolated signal <NUM>. The analog interpolated signal <NUM> is an analog version of the CODE <NUM>.

The buffer amplifier <NUM> is configured to receive the analog interpolated signal <NUM> from the interpolation RDAC <NUM>. In some embodiments, the buffer amplifier <NUM> is a unity gain buffer amplifier that applies a negative feedback to an operational amplifier to generate VOUT <NUM>, Thus, the voltage gain of the analog interpolated signal <NUM> is, in an embodiment, one (i. e <NUM> dB). However, in some embodiments, the buffer amplifier <NUM> generates current gain of greater than one. For example, the input impedance of the buffer amplifier <NUM> is, in an embodiment, relatively high (e.g., greater than 1MΩ) while the output impedance is relatively low. Therefore, the buffer amplifier <NUM> generates VOUT <NUM> as if it were a voltage source. In some embodiments, the buffer amplifier <NUM> includes a resistive chopper circuit operating according to a single or multi-bit chopper switching control signal (chop) <NUM>. Additionally, in some embodiments, an offset cancellation is applied within the general buffer <NUM> if any offset is introduced in the DAC circuit <NUM>,.

<FIG> shows an illustrative digital input signal CODE <NUM> that is received by DAC circuit <NUM> in accordance with various examples. In the example shown in <FIG>, CODE <NUM> is <NUM>-bit (K=<NUM>). The <NUM>-bit example CODE <NUM> includes a <NUM>-bit first subword MSB <NUM> (M=<NUM>), a <NUM>-bit second subword ISB 126I (I=<NUM>), and a <NUM>-bit third subword LSB <NUM> (L=<NUM>). The first subword MSB <NUM> includes bits dac<<NUM>:<NUM>> (dacm<<NUM>:<NUM>%). The second subword ISB 126I includes bits dac<<NUM>:<NUM>>. The third subword LSB <NUM> includes bits dac<<NUM>:<NUM>>.

<FIG> shows an illustrative circuit diagram of a <NUM>-bit MSB R-2R DAC <NUM> for the interpolation RDAC <NUM> of the segmented DAC circuit <NUM> in accordance with various examples. In the example shown in <FIG>, the MSB R-2R DAC <NUM> also includes chopper circuits and OEM circuitry which are not required for all possible implementations. As discussed above, the MSB R-2R DAC <NUM> is configured, in an embodiment, to generate the first analog output signal VH <NUM>, VL <NUM> utilizing VrefH <NUM> and VrefL <NUM> as reference voltage signals.

The <NUM>-bit MSB R-2R DAC <NUM> includes, in an embodiment, a resistor circuit <NUM>. The resistor circuit <NUM> includes an R-2R circuit <NUM> and a first switching circuit <NUM>. The resistors in the resistor circuit <NUM> are formed into resistor elements of resistance values of 1R (unity resistor) and 2R (<NUM> x the unity resistor and/or <NUM> unity resistors in series). In other words, the resistors in the resistor circuit <NUM> are, in an embodiment, based on the value of a unity resistor. The resistor circuit <NUM> is configured as a series of segments that each individually include a tap node (e.g., tap node <NUM>).

The R-2R circuit <NUM> includes, in an embodiment, M or fewer segments. For example, for a first subword <NUM>-bit MSB <NUM>, the R-2R circuit <NUM> includes <NUM> or fewer segments. Each segment includes two R-2R portioris individually associated with a corresponding one of the differential outputs <NUM>. Each of the portions includes a resistor element with a resistance value of 1R connected in series with the 1R elements of the other segments, as well as a resistor element having a resistance 2R connected to the switching circuit <NUM> at a corresponding tap node (e.g., tap node <NUM>). The illustrated example is a differential R-2R. However, as discussed above, single-ended implementations are possible with a single output line <NUM>, and each R-2R segment including a single 1R resistor element and a single 2R resistor element. The individual resistor elements (1R and/or 2R) can be single resistor components or can be multiple resistor components connected in any suitable series and/or parallel configuration to provide the corresponding 1R or 2R resistance.

The first switching circuit <NUM> includes, in an embodiment, a plurality of switches (e.g., switch <NUM>) individually connected between a corresponding one of the tap nodes (e.g., tap node <NUM>) and the input reference voltages VrefH <NUM> and VrefL <NUM>. In the illustrated differential example, the switching circuit <NUM> includes a first and second switch for each R-2R segment. Each switch is connected between the segment tap node and a corresponding one of the input reference voltages VrefH <NUM> and VrefL <NUM>. The switches of switching circuit <NUM> are operated in complementary fashion according to a corresponding one of the first subword bits dacm<<NUM>:<NUM>> (dac<<NUM>:<NUM>>) to connect the corresponding tap node with the input VrefH <NUM> or VrefL <NUM>.

In the example of <FIG>, the resistor circuit <NUM> includes <NUM> segments switched according to the first <NUM> MSB bits dacm <<NUM>:<NUM>>, and the remaining <NUM> MSB bits dacm<<NUM>:<NUM>> (e.g.. the <NUM> most significant bits of the MSB bits) are provided as inputs to a thermocouple decoder <NUM>. Thus, in the example of <FIG>, the MSB R-2R DAC <NUM> is a <NUM>-bit thermal decode and <NUM>-bit binary decode circuit. The thermocouple decoder <NUM> includes, in an embodirnent, an output <NUM> that provides thermocouple coded switching control signals T<<NUM>:<NUM>> to operate an OEM switching circuit <NUM>. Ordered element matching is implemented by a resistive OEM circuit <NUM> with, in the example shown in <FIG>, <FIG> sets of OEM resistor elements. In an embodiment, the resistor elements of the OEM circuit <NUM> have resistances of 2R. A 2R resistor element of each set of OEM resistor elements is connected between an OEM tap node (e.g., OEM tap node <NUM>) and a corresponding one of the outputs VH <NUM>, VL <NUM>. The OEM switching circuit <NUM> includes, in the example shown in <FIG>, <FIG> sets of two OEM switches (e.g., OEM switch <NUM>) to selectively connect a corresponding one of the OEM resistor elements between the inputs VrefH <NUM>, VrefL <NUM> and the outputs VH <NUM>, VL <NUM> based on an OEM code set by the switching control signals T<<NUM>:<NUM>> from the thermocouple decoder <NUM>, The OEM switches of OEM switching circuit <NUM> are operated in complementary fashion according to a corresponding one of the control signals T<<NUM>:<NUM>> to connect the corresponding OEM tap node (e.g. OEM tap node <NUM>) with the input VrefH <NUM> or VrefL <NUM>.

The number of thermocouple bits that are decoded in the <NUM>-bit MSB R-2R DAC <NUM> and whether there is a <NUM> LSB shift determines, in some embodiments, the total resistance in the resistor ladder <NUM>. The table below shows the total resistance utilized by the resistor ladder <NUM> for <NUM>-bit interpolation:.

The MSB R-2R DAC <NUM> in <FIG> also includes a resistive chopper circuit <NUM> with a plurality of chopper resistors of resistance value 2R and a chopper switching circuit <NUM>-<NUM>. The chopper switching circuit <NUM> includes, in an embodiment, a plurality of chopper switches (e.g., chopper switch <NUM>) to selectively and concurrently connect a corresponding one of the chopper resistors to the inputs VrefH <NUM>, VrefL <NUM>. Additionally, the chopper switching circuit <NUM> is configured to receive the chopper code "chop" <NUM>. The chopper circuitry (e.g., resistive chopper circuit <NUM> and chopper switching circuit <NUM>) can be omitted in some embodiments, with the R-2R circuitry (e.g., R-2R circuit <NUM>, first switching circuit <NUM>, OEM circuit <NUM>, OEM switching circuit <NUM>, and/or thermocouple decoder <NUM>) providing component segments for all the MSB bits dacm<<NUM>:<NUM>>.

The MSB R-2R DAC <NUM> in <FIG> operates according to the MSB bits <<NUM>:<NUM>>. The switches of the first switching circuit <NUM> are switched between V=<NUM> (logic <NUM>) and V = Vref (logic <NUM>), where Vref = VrefH <NUM> - VrefL <NUM> in the illustrated differential example. The R-2R network causes the MSB digital bits to be weighted in their contribution to the outputs VH <NUM>, VL <NUM> and thus, voltage VOUT <NUM>. Depending on which bits are set to <NUM> and which to <NUM>, the output VOUT <NUM> has a corresponding stepped value between <NUM> and Vref minus the value of the minimal step, corresponding to bit <NUM> (dacm<<NUM>>). The actual value of Vref (and the voltage of logic <NUM>) will depend on the type of technology used to generate the digital signals. An R-2R DAC is a binary weighted voltage divider. The 2R leg in parallel with each 1R resistor in series creates a binary weighting, and only one bit of the first subword MSB <NUM> is needed for each bit of resolution. The switch is either connected to ground or to the reference voltage. In addition, the equivalent impedance of the resistor ladder is typically lower than that of conventional string DACs, and therefore, the MSB R-2R DAC <NUM> has lower noise.

<FIG> show illustrative circuit diagrams of the chopper switching circuit <NUM> in accordance with various examples. In <FIG>, the chopper switching circuit <NUM> is configured such that switches <NUM> and <NUM> are connected to VrefH <NUM> while switches <NUM> and <NUM> are connected to VrefL <NUM>. <FIG> shows an example configuration of the switches when the chop <NUM> is LOW (equals zero). In such a configuration, switches <NUM> and <NUM> are open while switches <NUM> and <NUM> are closed. <FIG> shows an example configuration of the switches when the chop <NUM> is HIGH (equals <NUM>). In such a configuration, switches <NUM> and <NUM> are closed while switches <NUM> and <NUM> are open.

In <FIG>, the chopper switching circuit <NUM> is configured such that switches <NUM> and <NUM> are connected to VrefH <NUM> while switches <NUM> and <NUM> are connected to VrefL <NUM>. <FIG> shows an example configuration of the switches when the chop <NUM> is LOW (equals zero). In such a configuration, switches <NUM> and <NUM> are open while switches <NUM> and <NUM> are closed. <FIG> shows an example configuration of the switches when the chop <NUM> is HIGH (equals <NUM>). In such a configuration, switches <NUM> and <NUM> are closed while switches <NUM> and <NUM> are open,.

<FIG> show illustrative circuit diagrams of a <NUM>-bit ISB resistor ladder <NUM> for the interpolation RDAC <NUM> with a <NUM>-bit MSB R-2R DAC <NUM> that has <NUM> thermocouple bits as shown in <FIG> in accordance with various examples. As discussed above, the ISB resistor ladder <NUM> is configured, in an embodiment to generate the analog interpolated signal <NUM> utilizing the first analog output signal VH <NUM>, VL <NUM>. In the examples shown in <FIG>, a <NUM> LSB shift is provided in the analog interpolated signal <NUM>.

The ISB resistor ladder <NUM> of <FIG> includes in an embodiment, a resistor circuit <NUM> and a switching circuit <NUM>. The resistors in the resistor circuit <NUM> are formed into resistor elements of resistance values of ½ R (half of a unity resistor and/or <NUM> unity resistors in parallel). In other words, the resistors in the resistor circuit <NUM> are, in an embodiment, based on the value of a unity resistor. The resistor circuit <NUM> is composed, in an embodiment, of a series of resistor elements (<NUM> resistor elements in the example of <FIG> in order to generate <NUM> voltage levels for a <NUM> LSB shift), separated by tap nodes (e.g., tap node <NUM>), For example, the resistor elements can be connected in series with one another to define a plurality of tap nodes between adjacent ones of the resistor elements. The switching circuit <NUM> includes, in an embodiment, a plurality of switches (e.g., switch <NUM>) individually connected between a corresponding one of the tap nodes (e.g., tap node <NUM>) and the output of the ISB resistor ladder <NUM>.

In the example of <FIG>, the <NUM> ISB bits dac<<NUM>:<NUM>> are provided as inputs to a binary decoder <NUM>, The binary decoder <NUM> provides switching control signals c<<NUM>:<NUM>> by activating one of the eight output bits for each input value from <NUM> to <NUM> to operate the switching circuit <NUM>. The switches of switching circuit <NUM> are operated in complementary fashion according to a corresponding one of the control signals c<<NUM>:<NUM>> from the binary decoder <NUM> to connect the corresponding tap node, (e.g., tap node <NUM>) with the output of the ISB resistor ladder <NUM> to generate the analog interpolated signal <NUM>. The example shown in <FIG> is for a circuit in which the chop <NUM> is LOW while the example shown in <FIG> is for a circuit in which the chop <NUM> is HIGH.

The table below shows an example of the decoding and ideal analog iriterpolated signal <NUM> that can be generated by the resistor ladder <NUM> as shown in <FIG>.

The chop <NUM> swaps the decoder output c<<NUM>:<NUM>> so that the output voltage is the same for the same dacm <<NUM>:<NUM>>.

<FIG> show an illustrative circuit diagram of a <NUM>-bit ISB resistor ladder <NUM> for the interpolation RDAC <NUM> with a <NUM>-bit MSB R-2R DAC <NUM> that has <NUM> thermocouple bits as shown in <FIG> in accordance with various examples, The example I-SB resistor ladder <NUM> shown in <FIG> operates in a similar manner as the ISB resistor ladder <NUM> shown in <FIG>. However, the example ISB resistor ladder <NUM> in <FIG> includes only <NUM> resistor elements. For example, the decoder of <FIG> and <FIG>, in an embodiment, generates <NUM> voltage levels to generate the <NUM>-<NUM> LSB values utilizing the chopper switching circuit <NUM> of <FIG> and then to generate the <NUM> LSB or <NUM> LSB value utilizing the chopper switching circuit <NUM> of <FIG> to generate a <NUM>-<NUM> LSB or <NUM>-<NUM> LSB analog interpolated signal <NUM>. In the example of <FIG>, each of the resistor elements have a resistance of ¼ R (a quarter of a unity resistor and/or <NUM> unity resistors in parallel). Therefore, the output of the example ISB resistor ladder <NUM> shown in <FIG> provides no LSB shift to generate the analog interpolated signal <NUM>. The example shown in <FIG> is for a circuit in which the chop <NUM> is LOW while the example shown in <FIG> is for a circuit in which the chop <NUM> is HIGH.

In some ernbodiments, the decoder of <FIG> and <FIG> is not a general decoder (e.g., <NUM>-<NUM> decoder). The table below shows an example of the decoding and ideal analog interpolated signal <NUM> that can be generated by the resistor ladder <NUM> as shown in <FIG> from <NUM>~<NUM>.

<FIG> generates the same output as <FIG>, but with fewer actual resistors. As discussed above, the resistor ladder <NUM> of <FIG> includes a resistance of 6R. In <FIG>, <NUM> unity resistors can be utilized to generate the 6R resistance. However, in <FIG>, <FIG> unity resistors can be utilized to generate the 6R resistance and generate the same analog interpolated signal <NUM>,.

<FIG> shows an illustrative circuit diagram of an <NUM>-bit MSB R-2R DAC <NUM> for the interpolation RDAC <NUM> of the segmented DAC circuit <NUM> in accordance with various examples, The example <NUM>-bit R-2R DAC <NUM> works in a similar manner as the <NUM>-bit R-2R DAC <NUM> illustrated in <FIG>. However, the <NUM>-bit R-2R DAC utilizes, in an embodiment, <NUM> bits for the MSB <NUM> and a <NUM> bit thermal decode. In other words, the <NUM>-bit R-2R DAC <NUM> shown in <FIG> is a <NUM>-bit thermal decode with a <NUM>-bit binary decode. In other embodiments, more or less bits may be used for the thermal decode.

The number of thermocouple bits that are decoded in the <NUM>-bit MSB R-2R DAC <NUM>, in some embodiments, corresponds with and/or determines the total resistance in the resistor ladder <NUM>-<NUM>. The table below shows the total resistance utilized by the resistor ladder <NUM> for <NUM>-bit interpolation in conjunction with the <NUM>-bit MSB R-2R DAC <NUM>:.

<FIG> show an illustrative circuit diagram of a <NUM>-bit ISB resistor ladder <NUM> for the interpolation RDAC <NUM> with an <NUM>-bit MSB R-2R DAC <NUM> that has <NUM> thermocouple bits as shown in <FIG> in accordance with various examples. The example ISB resistor ladder <NUM> shown in <FIG> operates in a similar manner as the ISB resistor ladder <NUM> shown in <FIG>. However, the example ISB resistor ladder <NUM> in <FIG> include <NUM> taps. In the example of <FIG>, each of the resistor elements have a resistance of ½ R (half of a unity resistor and/or <NUM> unity resistors in parallel). Therefore, the output of the example ISB resistor ladder <NUM> shown in <FIG> provides no LSB shift to generate the analog interpolated signal <NUM>. The example shown in <FIG> is for a circuit in which the chop <NUM> is LOW while the example shown in <FIG> is for a circuit in which the chop <NUM> is HIGH.

In some embodiments, the decoder of <FIG> and BB is not a general decoder (e.g., a general <NUM>-<NUM> decoder). The table below shows an example of the decoding and ideal analog interpolated signal <NUM> that can be generated by the resistor ladder <NUM> as shown in <FIG>.

<FIG> show illustrative circuit diagrams of a <NUM>-bit ISB resistor ladder <NUM> for the interpolation RDAC <NUM> with an <NUM>-bit MSB R-2R DAC <NUM> that has <NUM> thermocouple bits in accordance with various examples. The example ISB resistor ladder <NUM> shown in <FIG> operates in a similar manner as the ISB resistor ladder <NUM> shown in <FIG>. However, in the example of <FIG>, each of the resistor elements have a resistance of ¼ R (a quarter of a unity resistor and/or <NUM> unity resistors in parallel). Therefore, the output of the example ISB resistor ladder <NUM> shown in <FIG> provides no LSB shift to generate the analog interpolated signal <NUM>. The example shown in <FIG> is for a circuit in which the chop <NUM> is LOW.

<FIG> generates the same output as <FIG>, but with fewer actual resistors, As discussed above, the resistor ladder <NUM> of <FIG> includes a resistance of 6R. In <FIG>, <NUM> unity resistors can be utilized to generate the <NUM>. 5R resistance. However, in <FIG>, <NUM> unity resistors can be utilized to generate the <NUM>. 5R resistance and generate the same analog interpolated signal <NUM>.

The interpolation RDAC <NUM> advantageously employs an MSB R-2R DAC <NUM> to convert the first subword MSB <NUM> to the first analog output signal VH <NUM>, VL <NUM> using significantly fewer switches than traditional resistor ladder MSB DACs. The interpolation RDAC <NUM> also provides interpolation through an ISB resistor ladder <NUM> which reduces the need for an interpolation amplifier. Thus, the calibration memory requirement is reduced and the complexity of a conventional system introduced by an interpolation amplifier is also reduced. The SDM <NUM> can be selectively employed to achieve additional resolution of the segmented DAC circuit <NUM>, and no additional calibration DAC is required to achieve <NUM>-bit resolution. The reduction in switches and memory capacity, as well as the reduction in complexity, reduces circuit area and power consumption while increasing speed compared with conventional DACs.

<FIG> show illustrative chopper functionality in the segmented DAC circuit <NUM> in accordance with various examples. <FIG> illustrates application of the chop signal <NUM> to the interpolation RDAC <NUM>. The chop signal <NUM> causes the interconnection of the first analog output signals <NUM> to swap between the output of the MSB R-2R DAC <NUM> and the ISB resistor ladder <NUM>. More particularly, the chop signal <NUM> is provided, in an embodiment, to the input of the MSB R-2R DAC <NUM> to switch VH <NUM> and VL <NUM> provided to the input of the ISB resistor ladder <NUM>.

<FIG> illustrates application of the chop signal <NUM> to the interpolation RDAC <NUM> and the buffer amplifier <NUM>. Like in the example of <FIG>, in the example of <FIG>, the chop signal <NUM> is provided, in an embodiment, to the input of the MSB R-2R DAC <NUM> to switch VH <NUM> and VL <NUM> provided to the input of the ISB resistor ladder <NUM>. Additionally, the buffer amplifier <NUM> includes a chopper amplifier <NUM> to break up the analog interpolated signal <NUM> received from the interpolation RDAC <NUM> to be processed as an AC signal. Once processed, the signal is integrated back to a DC signal at the output to generate VOUT <NUM>.

<FIG> illustrates application of the chop signal <NUM> to the buffer amplifier <NUM>. Like in the example of <FIG>, in the example of <FIG>, the buffer amplifier <NUM> includes a chopper amplifier <NUM> to break up the analog interpolated signal <NUM> received from the interpolation RDAC <NUM> to be processed as an AC signal. Once processed, the signal is integrated back to a DC signal at the output to generate VOUT <NUM>.

The segmented DAC circuit <NUM> using the interpolation RDAC <NUM> (including the MSB R-2R DAC <NUM> of <FIG> and <FIG> and the ISB resistor ladder <NUM> of <FIG> and <FIG>) also facilitates reduced calibration memory requirements and shortens factory calibration times. In certain examples, high performance for low integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) can be achieved. For a <NUM>-bit case, for example, INL and DNL of less than +/-1LSB can be achieved over a +/- 32LSB calibration range with +/- ¼ calibration step. Calibration memory in one <NUM>-bit example using the <NUM>-bit MSB DAC <NUM> requires only <NUM> x <NUM>-bits of memory <NUM> for the MSB calibration with chopper functionality, <NUM> x <NUM>-bits of memory for the MSB calibration without chopper functions and <NUM> x <NUM>-bits of memory for the LSB calibration. No additional calibration DAC is used in this example.

<FIG> shows an illustrative flow diagram of a method <NUM> for calibrating a DAC in accordance with various examples. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel, Addionally, some embodiments may perform only some of the actions shown. In some embodiments, at least some of the operations of the method <NUM>, as well as other operations described herein, are performed by the segmented DAC circuit <NUM>. More particularly, at least some of the operations of the method <NUM>, as well as other operations described herein, are performed by the decoder <NUM>, the calibration circuit <NUM>, the calibration and DEM circuit (including the SDM <NUM>), the interpolation DAC <NUM> (including the MSB R-2R DAC <NUM> and/or the ISB resistor ladder <NUM>), the buffer amplifier <NUM>, the OEM memory <NUM>, and/or the multiplexers <NUM>, <NUM>, and implemented in logic.

The method <NUM> provides calibration for a DAC circuit that converts a K-bit digital input signal (e.g., CODE <NUM> above) that includes an M-bit first subword MSB that includes a most significant bit of the digital input signal, an I-bit second subword ISB, and an L-bit third subword LSB that includes the least significant bit of the digital input signal. The method <NUM> in an embodiment is implemented during manufacturing of the segmented DAC circuit <NUM>. The calibration method <NUM>, moreover, provides significant advantages with respect to calibration memory utilization and calibration time compared with traditional calibration processes, In contrast to the traditional calibration process, the method <NUM> does not require trimming of a calibration DAC, and can be implemented using significantly less calibration memory than traditional techniques.

The method <NUM> begins in block <NUM> with measuring DAC output voltages, including output voltages of an R-2R DAC for a corresponding set of values of a first subword, measuring output voltages of a resistor ladder for a corresponding set of values of a second subword, and measuring output voltages of an SDM for a corresponding set of third subword values. At <NUM>, the method includes calculating an output voltage value of a segmented DAC based on the measured output voltages. At <NUM>, the method provides for calculating calibration codes for the R-2R DAC, the resistor ladder, and the SDM, as well as calculating and storing a K-bit calibration code for the DAC circuit based on the calibration codes. Thereafter at <NUM>, the method includes calculating a calibrated DAC INL and DNL. The method <NUM> is described in the context of a <NUM>-bit segmented DAC circuit <NUM> as described above, including an M = <NUM>-bit first subword MSB, an I = <NUM>-bit second subword ISB and an L = <NUM>-bit third subword LSB, but the method <NUM> can be used in connection with calibration of other segmented DAC systems having other values for M, I and/or L.

The output voltage measurements at <NUM> includes, in an embodiment, blocks <NUM>-<NUM>. In block <NUM>, the method <NUM> begins with measuring M+<NUM> output voltages VH, VL, such as VH <NUM> and VL <NUM>, of an M-bit MSB R-2R DAC, such as MSB R-2R DAC <NUM>, for a corresponding set of M+<NUM> values of the first subword MSB. In the illustrated example, the set of M+<NUM> values of the first subword MSB includes a first set with all bits set to <NUM> and M values in which only a single bit is set to <NUM>. Because M+<NUM> output voltages VH, VL are measured, <NUM> values of the first subword MSB are evaluated for measurements at <NUM>. This significantly saves measurement time compared with conventional resistor ladder DACs of a segmented DAC system. The method <NUM> continues in block <NUM> with measuring <NUM>I (e.g., <NUM>) output voltages, such as analog interpolated signal <NUM>, of the I-bit ISB resistor ladder, such as ISB resistor ladder <NUM>, for a corresponding set of <NUM>I unique values of the second subword ISB. For example, in block <NUM>, the method <NUM> continues with measuring <NUM>L (e.g., <NUM>) output voltages, such as ICODE <NUM>, for the L-bit SDM, such as SDM <NUM>, for a corresponding set of <NUM>L unique values of the third subword LSB.

The calculating at <NUM> includes, in an embodiment, blocks <NUM>-<NUM>. In block <NUM>, the method <NUM> continues with calculating a K-bit output voltage value DAC VOUT, such as VOUT <NUM>, based on the measured output voltages VH, VL, the analog interpolated signal, and ICODE. In block <NUM>, the method <NUM> continues with calculating an INL and a DNL based on the K-bit output voltage value DAC VOUT computed at <NUM>.

The processing at <NUM> includes, in an embodiment, blocks <NUM>-<NUM>. In block <NUM>, the method <NUM> continues with calculating calibration code CAL_MSB for the MSB R-2R DAC. In an embodiment, calculating calibration code CAL_MSB includes calculating the <NUM>-bit MSB calibration code code_9_bits_MSB according to the following formula: code_9_bits_MSB = (VH-VL_ideal) / (<NUM> * LSB), for ISB = VREF/<NUM>. The method <NUM> continues in block <NUM> with calculating calibration code CAL_ISB for the ISB resistor ladder. In an embodiment, calculating calibration code CAL_ISB includes calculating a <NUM>-bit ISB calibration code "code_3_bits_ISB" according to the following formula: code_3_bits_ISB = (analog interpolated signal-an ideal analog interpolated signal) / (<NUM> * LSB). In block <NUM>, the method <NUM> continues with calculating calibration code CAL_LSB for the SDM. The method <NUM> continues in block <NUM> with calculating a K-bit calibration code for the segmented DAC circuit <NUM> based on the calibration codes CAL_MSB, CAL_ISB CAL_LSB and storing the K-bit calibration code in calibration memory, such as calibration memory <NUM>, The calibrated <NUM>-bit DAC INL and DNL values can then be calculated at <NUM>,.

<FIG> shows an illustrative flow diagram of a method <NUM> of converting a digital input signal into a corresponding analog output signal in accordance with various examples. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform only some of the actions shown. In some embodiments, at least some of the operations of the method <NUM>, as well as other operations described herein, are performed by the segmented DAC circuit <NUM>, More particularly, at least some of the operations of the method <NUM>, as well as other operations described herein, are performed by the decoder <NUM>, the calibration circuit <NUM>, the calibration and DEM circuit (including the SDM <NUM>), the interpolation DAC <NUM> (including the MSB R-2R DAC <NUM> and/or the ISB resistor ladder <NUM>), the buffer amplifier <NUM>, the OEM memory <NUM>, and/or the multiplexers <NUM>, <NUM>, and implemented in logic.

The method <NUM> begins in block <NUM> with receiving a first subword of a digital input signal. The first subword includes an integer number M bits that include a MSB of the digital input signal, For example, the M-BIT MSB R-2R DAC <NUM> can receive first subword MSB <NUM> from a decoder that receives the original digital signal (e.g., CODE <NUM>). As discussed above, in some embodiments, the first subword is <NUM> bits. In block <NUM>, the method <NUM> continues with generating, by an R-2R DAC, an analog output signal with a voltage representative of the first subword For example, the MSB R-2R DAC <NUM> can generate VH <NUM> and VL <NUM> as a differential signal that is representative of the first subword MSB <NUM>.

The method <NUM> continues in block <NUM> with generating, by a resistor ladder, an analog signal based on the analog output signal and a second subword of the digital input signal The second subword includes an integer number I bits that include an ISB of the digital input signal For example, the I-bit ISB resistor ladder <NUM> can receive VH <NUM>, VL <NUM>, and the second subword ISB <NUM>. As discussed above, in some embodiments, the second subword is <NUM> bits. The ISB resistor ladder, utilizing VH <NUM>, VL <NUM>, and second subword ISB 126I, can generate the analog interpolated signal <NUM>. In block <NUM>, the method <NUM> continues with generating, by a buffer amplifier, an analog output signal based on the analog interpolated signal. For example, the buffer amplifier <NUM> can receive the analog interpolated signal <NUM> and generate VOUT <NUM> which, in some embodiments, is a unity voltage gain with higher current version of the analog interpolated signal <NUM>.

Claim 1:
A segmented digital-to-analog converter, DAC, (<NUM>) configured to receive a K-bit digital input signal (<NUM>) that is decoded into a M-bit first subword (<NUM>) including the most significant bit MSB (dac<<NUM>>) of the K-bit digital input signal (<NUM>), a I-bit second subword (126I) including intermediate significant bits ISB (dac<<NUM>> - dac<<NUM>>) of the K-bit digital input signal (<NUM>), and a L-bit third subword (<NUM>) including the least significant bit LSB (dac<<NUM>>) of the K-bit digital input signal (<NUM>), where M, I, and L are each greater than <NUM>, and K = M + I + L, the segmented DAC (<NUM>) including:
an interpolation resistor digital-to-analog converter, RDAC, (<NUM>) including:
a resistor-two-resistor, R-2R, DAC (<NUM>) configured to receive the first subword (<NUM>) and
generate an analog output signal (<NUM>, <NUM>) of the R-2R DAC (<NUM>) that is a voltage representative of the first subword (<NUM>), wherein the R-2R DAC (<NUM>) includes:
an R-2R circuit (<NUM>) that includes a plurality of resistors; and
a first switching circuit (<NUM>) connected to the R-2R circuit (<NUM>) at a plurality of tap nodes (<NUM>),
the first switching circuit (<NUM>) including a plurality of switches (<NUM>) individually
connected between a corresponding one of the tap nodes (<NUM>) and one of two reference voltages (<NUM>, <NUM>), wherein one of the reference voltages is preferably ground; and
a resistor ladder (<NUM>) configured to receive the analog output signal (<NUM>, <NUM>) of the R-2R DAC (<NUM>) and an N-bit digital interpolation code signal (<NUM>) that represents a value of the second subword (126I), the third subword (<NUM>) and a calibration code, where N is less than I+L, and generate an analog interpolated signal (<NUM>);
a buffer amplifier (<NUM>) configured to receive the analog interpolated signal (<NUM>) and generate an output signal (<NUM>) for the segmented DAC.