Patent Description:
Superconducting digital technology has provided computing and/or communications resources that benefit from unprecedented high speed, low power dissipation, and low operating temperature. For decades, superconducting digital technology has lacked random-access memory (RAM) with adequate capacity and speed relative to logic circuits. This has been a major obstacle to industrialization for current applications of superconducting technology in telecommunications and signal intelligence, and can be especially forbidding for high-end and quantum computing. All concepts currently considered for superconducting memory have been based on quantization of magnetic flux quanta in a superconducting inductive loop. Such memories can be readily adapted to high speed register files given a foundry process with adequate yield, but can never achieve the integration density of complementary metal-oxide semiconductor (CMOS), as they are fundamentally limited by the size of the inductive loop. One hybrid memory solution has been proposed where the memory core implements CMOS technology and the bit-line detection is done with Josephson devices. However, such a configuration yields only nominally higher performance than standard CMOS and suffers from relatively high power dissipation for a cryogenic environment. <CIT> proposes a JMRAM memory cell system.

One example includes a memory cell system that includes a quantizing loop that conducts a quantizing current in a first direction corresponding to a first stored memory state and to conduct the quantizing current in a second direction corresponding to a second stored memory state. The system also includes a bias element configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state. The stored memory state can be read from the memory cell system in response to the substantially constant flux bias, a read current that is provided to the memory cell system, and the circulating quantizing current. The system further includes a tunable energy element that is responsive to a write current that is provided to the memory cell system to change the state of the stored memory state between the first state and the second state.

Another example includes a method for controlling a memory cell system. The method includes providing a bit-write current on a bit-write line of the memory cell system, the bit-write line being inductively coupled to a quantizing loop. The method includes providing a word-write current on a word-write line of the memory cell system. The word-write line can be inductively coupled to a tunable energy element to reduce an energy barrier between two quantum states of the quantizing loop to provide a quantizing current in one of a first direction and a second direction in the quantizing loop based on the bit-write current in a memory write operation. The first direction of the quantizing current can correspond to a first state of a stored memory state of the memory cell system and the second direction of the quantizing current corresponding to storage of a second state of the stored memory state of the memory cell system. The method also includes providing a word-read current on a word-read line of the memory cell system. The word-read line can be inductively coupled to at least one Josephson junction. The method further includes providing a bit-read current on a bit-read line of the memory cell system to trigger the at least one Josephson junction in response to the first direction of the quantizing current to indicate the first state in a memory read operation and to not trigger the at least one Josephson junction in response to the second direction of the quantizing current to indicate the second state in the memory read operation.

Another example includes a memory array comprising an array of memory cell systems arranged in rows and columns. Each of the memory cell systems includes a quantizing loop configured to conduct a quantizing current in a first direction corresponding to storage of a first state of a stored memory state of the memory cell system and to conduct the quantizing current in a second direction opposite the first direction corresponding to storage of a second state of the stored memory state of the memory cell system. Each of the memory cell systems also includes a tunable energy element in the quantizing loop that is responsive to a word-write current provided on a word-write line associated with each of the memory cell systems of a respective one of the rows and to a bit-write current provided on a bit-write line associated with each of the memory cell systems of a respective one of the columns to change the state of the stored memory state between the first state and the second state. Each of the memory cell systems further includes a bias element configured to provide a substantially constant flux bias of the quantizing loop in the first direction of the quantizing loop in each of the first and second states of the stored memory state. The stored memory state can be read from the memory cell system in response to the substantially constant bias, a word-read current provided on a word-read line associated with each of the memory cell systems of the respective one of the rows, and a bit-read current provided on a bit-read line associated with each of the memory cell systems of the respective one of the columns.

This disclosure relates generally to classical and quantum computing systems, and more specifically to a quantizing loop memory cell system. The memory cell system includes a quantizing loop configured to conduct a quantizing current that has a current direction corresponding to a stored memory state. The stored memory state can correspond to the quantizing current having a first direction corresponding to a first state (e.g., a logic-<NUM> state) or can correspond to the quantizing current having a second direction opposite the first direction corresponding to a second state (e.g., a logic-<NUM> state). The memory cell system can also include a bias element and a tunable energy element that are each part of the quantizing loop. The bias element is configured to provide a substantially constant flux bias in the first direction of the quantizing loop. As an example, the bias element can be configured as a hysteretic magnetic Josephson junction (HMJJ) that is arranged substantially constantly in a π-state, and thus can provide a superconducting phase in the first direction of the quantizing loop. As another example, the bias element can be configured as a secondary winding of a transformer that is configured to inductively provide a current as the substantially constant flux bias. The stored memory state of the memory cell system can be read from the memory cell system in response to a read current and the substantially constant flux bias. For example, the read current can include a word-read current provided on a word-read line that is associated with a row of memory cell systems of a memory array and a bit-read current provided on a bit-read line that is associated with a column of memory cell systems of the memory array.

The tunable energy element is configured to be responsive to a write current to affect an energy level of the quantizing loop to set the stored memory state between the first and second states, and thus to set the current direction between the first direction and the second direction. For example, the tunable energy element can be configured as a tunable superconducting quantum interference device (SQUID) that is responsive to the write current to reduce an energy barrier between two quantum states of the quantizing loop to provide the quantizing current in one of the first and second directions. As another example, the tunable energy element can correspond to a magnetic field generator that can set the magnetic state of the bias element configured as a two-layer synthetic antiferromagnet (SAF) HMJJ. Therefore, the magnetic state of the bias element can be temporarily modified during a write operation to change the state of the quantizing loop.

<FIG> illustrates an example of a memory cell system <NUM>. The memory cell system <NUM> can be implemented in any of a variety of different applications, such as a classical and/or quantum computer system to store data. For example, the memory cell system <NUM> can be one memory cell of an array of memory cells arranged in rows and columns, such that the array can be configured to store multiple words of data.

The memory cell system <NUM> includes a quantizing loop <NUM> configured to conduct a quantizing current that has a current direction corresponding to a stored memory state. The stored memory state can correspond to the quantizing current having a first direction corresponding to a first state (e.g., a logic-<NUM> state) or can correspond to the quantizing current having a second direction opposite the first direction corresponding to a second state (e.g., a logic-<NUM> state). The memory cell system <NUM> also includes a bias element <NUM>. As an example, the bias element <NUM> can form part of the quantizing loop, such that the quantizing current flows through the bias element <NUM>. The bias element <NUM> is configured to provide a substantially constant flux bias in the first direction of the quantizing loop. As an example, the bias element <NUM> can be configured as a hysteretic magnetic Josephson junction (HMJJ) that is arranged substantially constantly in a π-state, and thus can provide a superconducting phase in the first direction of the quantizing loop. As another example, the bias element <NUM> can be configured as a secondary winding of a transformer that is configured to inductively provide a current as the substantially constant flux bias.

The memory cell system <NUM> further includes a tunable energy element <NUM>. The tunable energy element <NUM> is configured to be responsive to at least one write current to affect an energy level of the quantizing loop <NUM> to set the current direction between the first direction and the second direction, and thus to set the stored memory state between the first and second states. In the example of <FIG>, the write current(s) are demonstrated as a word-write current WLW and a bit-write current BLW. As an example, the word-write current WLW can be provided on a word-write line that is associated with all of the memory cell systems <NUM> in a row of an associated memory array, and the bit-write current BLW can be provided on a bit-write line that is associated with all of the memory cell systems <NUM> in a column of the associated memory array.

As an example, the tunable energy element <NUM> can be configured as a tunable superconducting quantum interference device (SQUID) that is responsive to the write currents WLW and BLW to reduce an energy barrier between two quantum states of the quantizing loop to provide the quantizing current in one of the first and second directions. As another example, the tunable energy element <NUM> can correspond to a magnetic field generator that can set the magnetic state of the bias element <NUM> configured as a two-layer synthetic antiferromagnet (SAF) HMJJ. Therefore, in the example of the tunable energy element <NUM> being configured as the magnetic field generator to change the magnetic state of the bias element <NUM> arranged as a two-layer SAF HMJJ, the magnetic state of the bias element <NUM> can be temporarily modified during a write operation to change the state of the quantizing loop <NUM>.

The stored memory state of the memory cell system <NUM> can be read from the memory cell system <NUM> in response to at least one read current and the substantially constant flux bias provided by the bias element <NUM>. In the example of <FIG>, the read current(s) are demonstrated as a word-read current WLR provided on a word-read line that is associated with the row of memory cell systems <NUM> of a memory array, and a bit-read current BLR provided on a bit-read line that is associated with the column of memory cell systems <NUM> of the memory array. As an example, the substantially constant flux bias can combine with the current direction of the quantizing current to indicate the stored memory state of the memory cell system <NUM> based on the word-read current WLR and the bit-read current BLR.

For example, in a first current direction of the quantizing current that is in the same current direction as the substantially constant flux bias, the quantizing current and the substantially constant flux bias can additively combine to bias at least one Josephson junction associated with the memory cell system <NUM>. Therefore, the at least one Josephson junction can trigger in response to the word-read current WLR and the bit-read current BLR to indicate a first state of the stored magnetic state of the memory cell system <NUM> (e.g., a logic-<NUM>) based on the at least one Josephson junction entering a voltage state, such as detected by a sense register associated with the associated memory array. As another example, in a second current direction of the quantizing current that is in the opposite current direction as the substantially constant flux bias, the quantizing current and the substantially constant flux bias can subtractively combine to reduce the bias of the at least one Josephson junction associated with the memory cell system <NUM>. Therefore, the at least one Josephson junction does not trigger in response to the word-read current WLR and the bit-read current BLR to indicate a second state of the stored magnetic state of the memory cell system <NUM> (e.g., a logic-<NUM>) based on the at least one Josephson junction not entering a voltage state, such as detected by the sense register associated with the associated memory array.

Therefore, as described herein, the memory cell system <NUM> implements the bias element <NUM> as a passive circuit element or as a field-tunable element that facilitates storage of the memory state in a more simplistic manner relative to other memory cells, such as hysteretic magnetic Josephson junction devices, such as a typical Josephson magnetic random-access memory (JMRAM), that are latched or unlatched to store the memory state. For example, in a typical HMJJ-based memory cell system, such as the JMRAM, a magnetic spin-valve is implemented as a barrier in an HMJJ, such that the memory state is stored in a latched parallel or anti-parallel alignment of the spin-valve layer moments. Such latching may require careful and specific tuning of the magnetic layer thickness to provide zero or π-phase shift in the HMJJ, and requires that one of the magnetic layers be switchable at a low applied magnetic field, while the other layer of the HMJJ be fixed and not affected by magnetic fields. Such requirements may complicate the optimization of the HMJJ of the JMRAM system. However, by implementing the bias element <NUM> as a passive circuit element or as a field-tunable element, the magnetic cell system <NUM> can be operated with much simpler optimization criteria while maintaining the desirable operating margins of writing data to and reading data from the memory cell system <NUM>.

<FIG> illustrates another example of a memory cell system <NUM>. The memory cell system <NUM> can correspond to the memory cell system <NUM> in the example of <FIG>, and can thus be one memory cell of an array of memory cells arranged in rows and columns.

The memory cell system <NUM> includes a first transformer T<NUM> and a second transformer T<NUM>, with the first transformer T<NUM> including a primary winding L<NUM> and a secondary winding L<NUM> and the second transformer T<NUM> including a primary winding L<NUM> and a secondary winding L<NUM>. The primary windings L<NUM> and L<NUM> are configured to propagate a bit-write current BLW that is provided during a write operation to store a memory state in the memory cell system <NUM>. The bit-write line can be associated with each memory cell system <NUM> in a column of memory cell systems <NUM> in a memory array, such that the bit-write current BLW can be provided through primary inductors L<NUM> and L<NUM> of each of the memory cell systems <NUM> in the column concurrently during the write operation. The secondary windings L<NUM> and L<NUM> are configured to inductively conduct a current in response to the bit-write current BLW during the write operation.

The memory cell system <NUM> also includes an HMJJ JJB1. The HMJJ JJB1 can correspond to the bias element <NUM> in the example of <FIG>, and is therefore demonstrated in the example of <FIG> as providing a current Iπ that can correspond to the substantially constant flux bias. For example, the HMJJ JJB1 can be set to a fixed π-state, such that the substantially constant flux bias associated with the current Iπ can correspond to a superconducting phase that is substantially constantly provided. As described herein, the term "superconducting phase" corresponds to a spontaneous supercurrent provided by the HMJJ JJB1 in response to the HMJJ JJB1 being set to the fixed π-state, with the supercurrent having an amplitude based on an internal superconductor flux quantum divided by an inductance term (e.g., the amplitude can be one-half a flux quantum divided by the inductance term).

In the example of <FIG>, the memory cell system <NUM> also includes a SQUID <NUM> formed by a pair of Josephson junctions JJT1 and JJT2 in parallel, and which is arranged in series with the HMJJ JJB1. The SQUID <NUM> can correspond to the tunable energy element <NUM> in the example of <FIG>, as described in greater detail herein. In the example of <FIG>, the series arrangement of the SQUID <NUM> and the HMJJ JJB1 are in parallel with the secondary windings L<NUM> and L<NUM> of the transformers T<NUM> and T<NUM>, respectively, and thus form a quantizing loop <NUM> configured to conduct a quantizing current that has a current direction corresponding to a stored memory state. The quantizing loop <NUM> can correspond to the quantizing loop <NUM> in the example of <FIG>, and can thus have either a first direction corresponding to a first state (e.g., a logic-<NUM> state) or a second direction opposite the first direction corresponding to a second state (e.g., a logic-<NUM> state).

The SQUID <NUM> is demonstrated as being inductively coupled to a word-write line that is configured to propagate a word-write current WLW. In the example of <FIG>, the inductive coupling is demonstrated at <NUM>. As an example, the word-write line can be associated with each memory cell system <NUM> in a row of memory cell systems <NUM> in a memory array, such that the word-write current WLW can be inductively coupled to a SQUID <NUM> of each of the memory cell systems <NUM> in the row concurrently during the write operation. As described in greater detail herein, the word-write current WLW can be configured to induce a current in the SQUID <NUM> to reduce an energy barrier of the quantizing loop <NUM> during the write operation. As a result of the reduction of the energy barrier based on the word-write current WLW, and in response to the state of the bit-write current BLW, the quantizing loop <NUM> can be configured to conduct a quantizing current IQ in either a first direction corresponding to a first state of the stored memory state (e.g., a logic-<NUM>) or a second direction corresponding to a second state of the stored memory state (e.g., a logic-<NUM>).

The memory cell system <NUM> further includes a pair of Josephson junctions JJ<NUM> and JJ<NUM> that are arranged in series with the parallel combination of the series combination of the bias element <NUM> and the HMJJ JJB1 in parallel with the series combination of inductors L<NUM> and L<NUM>. The Josephson junctions JJ<NUM> and JJ<NUM> can be configured to trigger or not trigger during a read operation to indicate the stored memory state of the memory cell system <NUM>. In the example of <FIG>, a bit-read line is provided to a node <NUM> between the secondary windings L<NUM> and L<NUM> of the transformers T<NUM> and T<NUM>, respectively, and extends from a node <NUM> between the Josephson junctions JJ<NUM> and JJ<NUM>. The bit-read line can be configured to propagate a bit-read current BLR that can, for example, be substantially constantly provided. As an example, the bit-read line can be associated with each memory cell system <NUM> in the column of memory cell systems <NUM> in a memory array, such that the bit-read current BLR can be provided through each of the memory cell systems <NUM> in the column concurrently during the read operation.

Additionally, a word-read line that propagates a word-read current WLR is inductively coupled, demonstrated at <NUM>, to the node <NUM>. The word-read current WLR can thus inductively provide a bias current to the Josephson junctions JJ<NUM> and JJ<NUM> during a read operation. As an example, the word-read line can be associated with each memory cell system <NUM> in a row of memory cell systems <NUM> in a memory array, such that the word-read current WLR can inductively provide a bias current to the Josephson junctions JJ<NUM> and JJ<NUM> of each of the memory cell systems <NUM> in the row concurrently during the read operation. Therefore, the stored memory state of the memory cell system <NUM> can be read from the memory cell system <NUM> in response to the word-read current WLR and the bit-read current BLR, and based on the substantially constant flux bias provided by the HMJJ JJB1 and the state of the SQUID <NUM>.

<FIG> illustrates an example diagram <NUM> of the memory cell <NUM>. Therefore, reference is to be made to the example of <FIG> in the following description of the example of <FIG>. In the example of <FIG>, the quantizing current IQ is demonstrated as flowing in the quantizing loop <NUM> in a first direction, demonstrated as a counter-clockwise direction. Because the memory cell system <NUM> can operate in a superconducting environment, the quantizing current IQ can be a superconducting current that flows consistently in the zero-resistance superconducting quantizing loop <NUM>.

In the example of <FIG>, the counter-clockwise current direction of the quantizing current IQ is thus provided in the same current direction as the substantially constant flux bias Iπ. Therefore, quantizing current IQ and the substantially constant flux bias Iπ can additively combine to bias the Josephson junctions JJ<NUM> and JJ<NUM>. Therefore, during a read operation, the word-read current WLR can induce a current in the loop formed by the SQUID <NUM>, the HMJJ JJB1, and the Josephson Junctions JJ<NUM> and JJ<NUM>. For example, the current induced by the word-read current WLR can provide a clock-wise current in the loop formed by the SQUID <NUM>, the HMJJ JJB1, and the Josephson Junctions JJ<NUM> and JJ<NUM>. Therefore, when the current induced by the word-read current WLR is combined with the bit-read current BLR and the additively combined quantizing current IQ and substantially constant flux bias Iπ, can trigger the Josephson junctions JJ<NUM> and JJ<NUM> and put them into the voltage state. The voltage state can thus be detected on the bit-read line, such as by a sense register, to detect the first stored memory state (e.g., logic-<NUM>) of the memory cell system <NUM>.

<FIG> illustrates an example diagram <NUM> of the memory cell <NUM>. Therefore, reference is to be made to the example of <FIG> in the following description of the example of <FIG>. In the example of <FIG>, the quantizing current IQ is demonstrated as flowing in the quantizing loop <NUM> in a second direction, demonstrated as a clockwise direction. Similar to as described previously, the quantizing current IQ can be a superconducting current that flows consistently in the zero-resistance superconducting quantizing loop <NUM>.

In the example of <FIG>, the clockwise current direction of the quantizing current IQ is thus provided in an opposite current direction as the substantially constant flux bias Iπ. In addition, in response to setting the direction of the quantizing current IQ during a write operation based on applying the word-write current WLW and the current direction of the bit-write current BLW, as described in greater detail herein, the SQUID <NUM> can have a flux quantum bias IFQ in an opposite direction with respect to the substantially constant flux bias Iπ. As an example, the flux quantum bias IFQ and the substantially constant flux bias Iπ can have approximately equal and opposite amplitudes with respect to each other, such that the quantizing current IQ can have an amplitude that is approximately twice the amplitude of the substantially constant flux bias Iπ. Therefore, the combination of the quantizing current IQ and the substantially constant flux bias Iπ can subtractively combine to reduce the bias of the Josephson junctions JJ<NUM> and JJ<NUM>. Therefore, during a read operation, the word-read current WLR can induce a current in the loop formed by the SQUID <NUM>, the HMJJ JJB1, and the Josephson Junctions JJ<NUM> and JJ<NUM>. For example, the current induced by the word-read current WLR can provide a clock-wise current in the loop formed by the SQUID <NUM>, the HMJJ JJB1, and the Josephson Junctions JJ<NUM> and JJ<NUM>. Therefore, when the current induced by the word-read current WLR is combined with the bit-read current BLR and the combined quantizing current IQ and substantially constant flux bias Iπ, the Josephson junctions JJ<NUM> and JJ<NUM> do not trigger. Therefore, the Josephson junctions JJ<NUM> and JJ<NUM> do not enter the voltage state. As a result, an approximately zero voltage can be detected on the bit-read line, such as by the sense register, to detect the second stored memory state (e.g., logic-<NUM>) of the memory cell system <NUM>.

<FIG> illustrates an example diagram <NUM> of a memory write operation. The diagram <NUM> demonstrates a sequence of graphs of energy E on the Y-axis plotted as a function of phase Φ on the X-axis. As an example, the diagram <NUM> demonstrates a sequence in which the memory cell system <NUM> changes from the second state (e.g., logic-<NUM>) of the stored memory state to the first state (e.g., logic-<NUM>) of the stored memory state. The diagram <NUM> demonstrates the graph of each of a first step <NUM>, a second step <NUM>, a third step <NUM>, a fourth step <NUM>, and a fifth step <NUM> in the sequence of the write operation. In each of the steps <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> the graph includes a phase-energy curve <NUM>.

In the first step <NUM>, the phase-energy curve <NUM> includes a first well <NUM> and a second well <NUM> that are separated by a barrier <NUM>. The first and second wells <NUM> and <NUM> each have an approximately equal energy of E<NUM>, with the barrier <NUM> having an energy E<NUM> that is greater than the energy E<NUM>. Therefore, the energy state of the quantizing loop <NUM>, demonstrated at <NUM>, is substantially stable at a phase Φ<NUM>, which can be representative of the clockwise current direction of the quantizing current IQ, such as demonstrated in the example of <FIG>. Therefore, the first step <NUM> demonstrates a substantially stable energy state <NUM> at the phase Φ<NUM>, and thus the stable second state of the stored memory state of the memory cell system <NUM>.

The second step <NUM> can demonstrate application of the bit-write current BLW in a first direction, and thus the effect of induced current in the quantizing loop <NUM>. In the example of <FIG>, the second step <NUM> demonstrates that the phase-energy curve <NUM> "tilts" in a first direction, such that the first well <NUM> increases in energy to an energy E<NUM> and the second well <NUM> decreases in energy to an energy Es that is less than the energy E<NUM>. Therefore, the relative energy levels of the first and second wells <NUM> and <NUM> are separated. However, during the second step <NUM>, the energy state <NUM> of the quantizing loop <NUM> remains at the phase Φ<NUM> due to the barrier <NUM> between the first and second wells <NUM> and <NUM>. The tilt of the phase-energy curve <NUM> can be maintained during application of the bit-write current BLW.

The third step <NUM> can demonstrate application of the word-write current WLW, and thus the effect of induced current in the tunable energy element (e.g., the SQUID <NUM>). In the example of <FIG>, the third step <NUM> demonstrates that the barrier <NUM> of the phase-energy curve <NUM> is reduced, such that the barrier <NUM> decreases to an energy E<NUM> that can be less than the energy E<NUM> and greater than the energy E<NUM>. As a result, the barrier <NUM> no longer separates the first and second wells <NUM> and <NUM>. Therefore, the energy state <NUM> of the quantizing loop <NUM> decreases from the energy E<NUM> to the energy E<NUM>, demonstrated by the arrow <NUM>, and thus increases in phase from the phase Φ<NUM> to the phase Φ<NUM>.

The fourth step <NUM> can demonstrate cessation of the application of the word-write current WLW, and thus cessation of the induced current in the tunable energy element (e.g., the SQUID <NUM>). In the example of <FIG>, the fourth step <NUM> demonstrates that the barrier <NUM> of the phase-energy curve <NUM> is increased back to approximately the energy E<NUM>, and thus to an energy that is greater than the energy levels E<NUM> and E<NUM>. Therefore, the energy state <NUM> of the quantizing loop <NUM> is substantially stable at the phase Φ<NUM>, which can be representative of the counter-clockwise current direction of the quantizing current IQ, such as demonstrated in the example of <FIG>. The fifth step <NUM> can demonstrate cessation of the application of the bit-write current BLW. Thus, the phase-energy curve <NUM> returns to the nominal stable state demonstrated in the first step <NUM>. Therefore, the fifth step <NUM> demonstrates a substantially stable energy state <NUM> at the phase Φ<NUM>, and thus the stable first state of the stored memory state of the memory cell system <NUM>.

<FIG> illustrates an example diagram <NUM> of a memory write operation. Similar to the example of <FIG>, the diagram <NUM> demonstrates a sequence of graphs of energy E on the Y-axis plotted as a function of phase Φ on the X-axis. As an example, the diagram <NUM> demonstrates a sequence in which the memory cell system <NUM> changes from the first state (e.g., logic-<NUM>) of the stored memory state to the second state (e.g., logic-<NUM>) of the stored memory state. The diagram <NUM> demonstrates the graph of each of a first step <NUM>, a second step <NUM>, a third step <NUM>, a fourth step <NUM>, and a fifth state <NUM> in the sequence of the write operation. In each of the steps <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, the graph includes a phase-energy curve <NUM>.

In the first step <NUM>, the phase-energy curve <NUM> includes a first well <NUM> and a second well <NUM> that are separated by a barrier <NUM>. The first and second wells <NUM> and <NUM> each have an approximately equal energy of E<NUM>, with the barrier <NUM> having an energy E<NUM> that is greater than the energy E<NUM>. Therefore, the energy state of the quantizing loop <NUM>, demonstrated at <NUM>, is substantially stable at a phase Φ<NUM>, which can be representative of the counter-clockwise current direction of the quantizing current IQ, such as demonstrated in the example of <FIG>. Therefore, the first step <NUM> demonstrates a substantially stable energy state <NUM> at the phase Φ<NUM>, and thus the stable first state of the stored memory state of the memory cell system <NUM>.

The second step <NUM> can demonstrate application of the bit-write current BLW in a second direction opposite the first direction (as provided in the second step <NUM> in the example of <FIG>), and thus the effect of induced current in the quantizing loop <NUM>. In the example of <FIG>, the second step <NUM> demonstrates that the phase-energy curve <NUM> "tilts" in a second direction opposite the first direction (as provided in the second step <NUM> in the example of <FIG>), such that the first well <NUM> decreases in energy to the energy E<NUM> and the second well <NUM> increases in energy to the energy E<NUM> that is more than the energy E<NUM>. Therefore, the relative energy levels of the first and second wells <NUM> and <NUM> are separated. However, during the second step <NUM>, the energy state <NUM> of the quantizing loop <NUM> remains at the phase Φ<NUM> due to the barrier <NUM> between the first and second wells <NUM> and <NUM>.

The third step <NUM> can demonstrate application of the word-write current WLW, and thus the effect of induced current in the tunable energy element (e.g., the SQUID <NUM>). In the example of <FIG>, the third step <NUM> demonstrates that the barrier <NUM> of the phase-energy curve <NUM> is reduced, such that the barrier <NUM> decreases to the energy E<NUM> that can be less than the energy E<NUM> and greater than the energy E<NUM>. As a result, the barrier <NUM> no longer separates the first and second wells <NUM> and <NUM>. Therefore, the energy state <NUM> of the quantizing loop <NUM> decreases from the energy E<NUM> to the energy E<NUM>, demonstrated by the arrow <NUM>, and thus decreases in phase from the phase Φ<NUM> to the phase Φ<NUM>.

The fourth step <NUM> can demonstrate cessation of the application of the word-write current WLW, and thus cessation of the induced current in the tunable energy element (e.g., the SQUID <NUM>). In the example of <FIG>, the fourth step <NUM> demonstrates that the barrier <NUM> of the phase-energy curve <NUM> is increased back to approximately the energy E<NUM>, and thus to an energy that is greater than the energy levels E<NUM> and E<NUM>. Therefore, the energy state <NUM> of the quantizing loop <NUM> is substantially stable at the phase Φ<NUM>, which can be representative of the clockwise current direction of the quantizing current IQ, such as demonstrated in the example of <FIG>. The fifth step <NUM> can demonstrate cessation of the application of the bit-write current BLW. Thus, the phase-energy curve <NUM> returns to the nominal stable state demonstrated in the first step <NUM>. Therefore, the fifth step <NUM> demonstrates a substantially stable energy state <NUM> at the phase Φ<NUM>, and thus the stable first state of the stored memory state of the memory cell system <NUM>.

The memory cell system <NUM> also includes a third transformer T<NUM>, with the third transformer T<NUM> including a primary winding L<NUM> and a secondary winding L<NUM>. The primary winding L<NUM> is configured to propagate a bias current IBIAS that is substantially constantly provided. Therefore, the secondary winding L<NUM> substantially constantly provides an induced current. The secondary winding L<NUM> can correspond to the bias element <NUM> in the example of <FIG>, and therefore, the substantially constant induced current is demonstrated in the example of <FIG> as the current Iπ that can correspond to the substantially constant flux bias. Accordingly, the memory cell system <NUM> can be configured substantially the same as the memory cell system <NUM> in the examples of <FIG>, except with the HMJJ JJB1 being replaced by the transformer T<NUM> to provide the substantially constant flux bias via the secondary winding L<NUM>. Thus, the memory cell system <NUM> also includes a SQUID <NUM> formed by a pair of Josephson junctions JJT1 and JJT2 in parallel, and which is arranged in series with the secondary winding L<NUM>. Accordingly, the series arrangement of the SQUID <NUM> and the secondary winding L<NUM> in parallel with the secondary windings L<NUM> and L<NUM> of the transformers T<NUM> and T<NUM>, respectively, form a quantizing loop <NUM> configured to conduct the quantizing current IQ, similar to as described previously.

Additionally, a word-read line that propagates a word-read current WLR is inductively coupled, as demonstrated at <NUM>, to the node <NUM>. The word-read current WLR can thus inductively provide a bias current to the Josephson junctions JJ<NUM> and JJ<NUM> during a read operation. As an example, the word-read line can be associated with each memory cell system <NUM> in a row of memory cell systems <NUM> in a memory array, such that the word-read current WLR can inductively provide a bias current to the Josephson junctions JJ<NUM> and JJ<NUM> of each of the memory cell systems <NUM> in the row concurrently during the read operation. Therefore, the stored memory state of the memory cell system <NUM> can be read from the memory cell system <NUM> in response to the word-read current WLR and the bit-read current BLR, and based on the substantially constant flux bias provided by the secondary winding L<NUM>.

For example, the stored memory state of the memory cell system <NUM> can be read during a read operation in substantially the same manner as described previously in the examples of <FIG>. Similarly, the stored memory state of the memory cell system <NUM> can be written during a write operation in substantially the same manner as described previously in the examples of <FIG> and <FIG>.

The memory cell system <NUM> also includes an HMJJ JJB2 arranged in parallel with the secondary windings L<NUM> and L<NUM>. The HMJJ JJB2 can correspond to the bias element <NUM> in the example of <FIG>, and is therefore demonstrated in the example of <FIG> as providing a current Iπ that can correspond to the substantially constant flux bias. For example, the HMJJ JJB2 can be set to a fixed π-state, such that the substantially constant flux bias associated with the current Iπ can correspond to a superconducting phase that is substantially constantly provided. As an example, the HMJJ JJB2 can be configured as a two-layer synthetic antiferromagnet (SAF) HMJJ, and can thus have a magnetic state that can be modified in response to an orthogonal magnetic field, as described in greater detail herein. The parallel arrangement of the HMJJ JJB2 with the secondary windings L<NUM> and L<NUM> of the transformers T<NUM> and T<NUM>, respectively, form a quantizing loop <NUM> configured to conduct the quantizing current IQ, similar to as described previously.

Additionally, the memory cell system <NUM> also includes a magnetic field element <NUM> arranged proximal with the HMJJ JJB2. The magnetic field element <NUM> is demonstrated as being coupled to the word-write line that is configured to propagate the word-write current WLW. As an example, the magnetic field element <NUM> can be configured as an inductor that is configured to provide a magnetic field in response to the word-write current WLW, with the magnetic field being oriented orthogonally with respect to the terminals of the HMJJ JJB2 and in-plane with respect to the quantizing loop <NUM>. For example, the word-write line can be associated with each memory cell system <NUM> in a row of memory cell systems <NUM> in a memory array, such that the word-write current WLW can be provided through the magnetic field element <NUM> of each of the memory cell systems <NUM> in the row concurrently during the write operation.

As described in greater detail herein, the word-write current WLW can be configured to activate the magnetic field generator <NUM> to generate a magnetic field that is provided orthogonally with respect to the HMJJ JJB2 to reduce an energy barrier (e.g., the barrier <NUM> and <NUM> in the respective examples of <FIG> and <FIG>) of the quantizing loop <NUM> during the write operation. As a result of the reduction of the energy barrier based on the word-write current WLW, and in response to the state of the bit-write current BLW, the quantizing loop <NUM> can be configured to conduct a quantizing current IQ in either a first direction corresponding to a first state of the stored memory state (e.g., a logic-<NUM>) or a second direction corresponding to a second state of the stored memory state (e.g., a logic-<NUM>). Accordingly, the memory cell system <NUM> can be configured substantially the same as the memory cell system <NUM> in the examples of <FIG>, except with the HMJJ JJB1 being replaced by the HMJJ JJB2 arranged as a two-layer SAF HMJJ to provide the substantially constant flux bias, and the SQUID <NUM> can be replaced by the magnetic field generator <NUM>.

Additionally, a word-read line that propagates a word-read current WLR is inductively coupled to the node <NUM>. The word-read current WLR can thus inductively provide a bias current to the Josephson junctions JJ<NUM> and JJ<NUM> during a read operation. As an example, the word-read line can be associated with each memory cell system <NUM> in a row of memory cell systems <NUM> in a memory array, such that the word-read current WLR can inductively provide a bias current to the Josephson junctions JJ<NUM> and JJ<NUM> of each of the memory cell systems <NUM> in the row concurrently during the read operation. Therefore, the stored memory state of the memory cell system <NUM> can be read from the memory cell system <NUM> in response to the word-read current WLR and the bit-read current BLR, and based on the substantially constant flux bias provided by the HMJJ JJB2. For example, the stored memory state of the memory cell system <NUM> can be read during a read operation in substantially the same manner as described previously in the examples of <FIG>.

<FIG> illustrates another example diagram <NUM> of the memory cell <NUM>. The diagram <NUM> demonstrates the memory cell system <NUM>, and thus, reference is to be made to the example of <FIG> in the following description of the example of <FIG>. As described previously, the HMJJ JJB2 can be configured as a two-layer SAF HMJJ, such that the two layers of the HMJJ JJB2 can be strongly magnetically coupled to each other in the anti-parallel direction with respect to each other. As an example, the thicknesses of the SAF layers of the HMJJ JJB2 can be configured such that at an approximately zero magnetic field provided through the HMJJ JJB2, the HMJJ JJB2 is in the π-state. The example of <FIG> thus demonstrates the HMJJ JJB2 at <NUM>, with the HMJJ JJB2 having anti-parallel magnetic coupling.

<FIG> illustrates another example diagram <NUM> of the memory cell <NUM>. The diagram <NUM> demonstrates the memory cell system <NUM>, and thus, reference is to be made to the example of <FIG> and <FIG> in the following description of the example of <FIG>. In the example of <FIG>, the magnetic field element <NUM> is demonstrated as generating a magnetic field, demonstrated at <NUM>, in a direction that is orthogonal with the anti-parallel magnetic coupling of the HMJJ JJB2, as provided in the example of <FIG>. Therefore, as demonstrated in the example of <FIG>, the applied magnetic field <NUM> causes the magnetic field of the layers of the HMJJ JJB2 to substantially align themselves with the applied magnetic field <NUM>. The alignment of the magnetic field of the layers of the HMJJ JJB2 initially decreases the critical current of the HMJJ JJB2, and eventually, in response to the applied magnetic field <NUM> having sufficiently high amplitude, the HMJJ JJB2 can transition to a zero-phase state.

The zero-phase state of the HMJJ JJB2 removes the energy barrier between the left- and right circulating current states of the quantizing loop <NUM>, similar to as demonstrated at <NUM> and <NUM> in the examples of <FIG> and <FIG>, respectively. As a result, the memory cell system <NUM> can be written substantially similarly to as demonstrated in the examples of <FIG> and <FIG>, with the magnetic field element <NUM> providing the magnetic field <NUM> in response to the word-write current WLW to reduce the energy barrier between the states of the quantizing loop <NUM>. Upon deactivating the magnetic field <NUM>, the HMJJ JJB2 returns to an anti-parallel π-phase configuration which re-establishes the double-well potential of the phase-energy curve (e.g., similar to as described at <NUM> and <NUM> in the respective examples of <FIG> and <FIG>). Accordingly, in the absence of the applied magnetic field, the HMJJ JJB2 provides the substantially constant flux bias Iπ to facilitate reading the stored memory state, similar to as described previously.

The memory cell system <NUM> includes a first transformer T<NUM>, with the first transformer T<NUM> including a primary winding L<NUM> and a secondary winding L<NUM> and an inductor L<NUM>. The primary winding L<NUM> is configured to propagate a bit-write current BLW that is provided during a write operation to store a memory state in the memory cell system <NUM>. The bit-write line can be associated with each memory cell system <NUM> in a column of memory cell systems <NUM> in a memory array, such that the bit-write current BLW can be provided through primary inductor L<NUM> of each of the memory cell systems <NUM> in the column concurrently during the write operation. The secondary winding L<NUM> is configured to inductively conduct a current in response to the bit-write current BLW during the write operation.

The memory cell system <NUM> also includes an HMJJ JJB3 arranged in parallel with the secondary winding L<NUM>. The HMJJ JJB3 can correspond to the bias element <NUM> in the example of <FIG>, and is therefore demonstrated in the example of <FIG> as providing a current Iπ that can correspond to the substantially constant flux bias. For example, the HMJJ JJB3 can be set to a fixed π-state, such that the substantially constant flux bias associated with the current Iπ can correspond to a superconducting phase that is substantially constantly provided. As an example, the HMJJ JJB3 can be configured as an HMJJ, similar to as described in the example of <FIG>, or as a two-layer SAF HMJJ, similar to as described in the example of <FIG>. In the example of <FIG>, the HHMJ JJB3 is coupled to a node <NUM> arranged between the secondary winding L<NUM> of the transformer T<NUM> and an inductor L<NUM>, respectively.

Thus, the memory cell system <NUM> also includes a SQUID <NUM> formed by a pair of Josephson junctions JJT1 and JJT2 in parallel, and which is arranged in series with the HMJJ JJB3. Accordingly, the series arrangement of the SQUID <NUM> and the HMJJ JJB3 in parallel with the secondary winding L<NUM> of the transformer T<NUM> forms a quantizing loop <NUM> configured to conduct the quantizing current IQ, similar to as described previously. The SQUID <NUM> is demonstrated as being inductively coupled to a word-write line that is configured to propagate a word-write current WLW. In the example of <FIG>, the inductive coupling is demonstrated at <NUM>. As an example, the word-write line can be associated with each memory cell system <NUM> in a row of memory cell systems <NUM> in a memory array, such that the word-write current WLW can be inductively coupled to a SQUID <NUM> of each of the memory cell systems <NUM> in the row concurrently during the write operation. As described in greater detail herein, the word-write current WLW can be configured to induce a current in the SQUID <NUM> to reduce an energy barrier of the quantizing loop <NUM> during the write operation. As a result of the reduction of the energy barrier based on the word-write current WLW, and in response to the state of the bit-write current BLW, the quantizing loop <NUM> can be configured to conduct a quantizing current IQ in either a first direction corresponding to a first state of the stored memory state (e.g., a logic-<NUM>") or a second direction corresponding to a second state of the stored memory state (e.g., a logic-<NUM>).

The memory cell system <NUM> further includes a pair of Josephson junctions JJ<NUM> and JJ<NUM> that are coupled to the secondary winding L<NUM> of the transformers T<NUM> and the inductor L<NUM>. The Josephson junctions JJ<NUM> and JJ<NUM> can be configured to trigger or not trigger during a read operation to indicate the stored memory state of the memory cell system <NUM>. In the example of <FIG>, a bit-read line is provided to the node <NUM> between the secondary winding L<NUM> of the transformer T<NUM> and the inductor L<NUM>, and extends from a node <NUM> between the Josephson junctions JJ<NUM> and JJ<NUM>. The bit-read line can be configured to propagate a bit-read current BLR that can, for example, be substantially constantly provided. As an example, the bit-read line can be associated with each memory cell system <NUM> in the column of memory cell systems <NUM> in a memory array, such that the bit-read current BLR can be provided through each of the memory cell systems <NUM> in the column concurrently during the read operation. Additionally, a word-read line that propagates a word-read current WLR is inductively coupled, as demonstrated at <NUM>, to the node <NUM>. The word-read current WLR can thus inductively provide a bias current to the Josephson junctions JJ<NUM> and JJ<NUM> during a read operation. For example, the stored memory state of the memory cell system <NUM> can be read during a read operation in substantially the same manner as described previously in the examples of <FIG>.

In addition, based on the coupling of the HMJJ JJB3 to the node <NUM>, and because the bit-read current BLR can be substantially constantly provided, the memory state of the memory cell system <NUM> can be written based on unidirectional application of the bit-write current BLW. For example, because the bit-read current BLR is substantially constantly provided, and because the inductor L<NUM> is not part of the quantizing loop <NUM>, the bit-read current BLR provides a positive unidirectional current component in the quantizing loop <NUM>, as opposed to being provided substantially equally and oppositely through the secondary winding L<NUM> and the inductor L<NUM>, as provided in the examples of <FIG>, <FIG>. Therefore, the memory state can be written to set the current direction in the quantizing loop <NUM> based on application of the bit-write current BLW in a first direction to write the first state and based on a zero amplitude of the bit-write current BLW to write the second state. In other words, the bit-read current BLR provides the suitable bias in the opposite direction of the unidirectional bit-write current BLW to provide the second current direction of the quantizing current IQ, and thus to write the second state of the stored memory state.

<FIG> illustrates an example of a memory system <NUM> in accordance with an aspect of the invention. The JMRAM system <NUM> can be implemented as a memory structure in a variety of computing applications.

The memory system <NUM> is demonstrated in the example of <FIG> as being arranged as an array of memory cells <NUM>. Specifically, the memory cells <NUM> are arranged in rows <NUM> that each correspond to a data word, demonstrated as WORD <NUM> through WORD Y, where Y is an integer greater than <NUM>. Each of the rows <NUM> includes a set of memory cells <NUM> that form X columns <NUM> across the rows <NUM>, with the memory cells <NUM> in WORD <NUM> being demonstrated in the example of <FIG> as C<NUM> to CX, where X is an integer greater than <NUM>. Therefore, each of the memory cells <NUM> in the array of the memory system <NUM> can be individually addressable by row <NUM> and column <NUM>.

In the example of <FIG>, each of the rows <NUM> is demonstrated as having an associated word-write line <NUM> and word-read line <NUM>, demonstrated as WLW<NUM> and WLR<NUM> through WLWY and WLRY, respectively. The word-write line <NUM> and word-read line <NUM> can be inductively and/or magnetically coupled to each of the memory cells <NUM> in each of the rows <NUM> of the memory system <NUM>. In addition, each of the memory cells <NUM> is demonstrated as having an associated bit-write line <NUM> and bit-read line <NUM>, demonstrated as BLW<NUM> and BLR<NUM> through BLWX and BLRX, respectively. The bit-write line <NUM> and bit-read line <NUM> can be coupled to each corresponding numbered memory cell <NUM> in each of the rows <NUM> of the memory system <NUM>, such that the memory cells <NUM> in each column <NUM> are arranged in series with respect to the bit-write line <NUM> and bit-read line <NUM>. Although the example of <FIG> describes that the word-write lines <NUM> and word-read lines <NUM> and the bit-write lines <NUM> and bit-read lines <NUM> are arranged in series with other adjacent memory cells in the respective row and column, the word-write lines <NUM> and word-read lines <NUM> and the bit-write lines <NUM> and bit-read lines <NUM> could instead be dedicated with respect to each memory cell <NUM>.

Each of the memory cells <NUM> is configured to store a single bit of data. Specifically, each of the memory cells <NUM> can include at least one phase hysteretic magnetic Josephson junction that can be configured to store a digital state corresponding to a binary logic-<NUM> or a binary logic-<NUM>. The digital state can be set in response to a word-write current that is provided on the respective word-write line <NUM> and a bit-write current that is provided on the respective bit-write line <NUM>. Similarly, the respective digital state that is stored in each of the memory cells <NUM> can be read from the memory cells <NUM> based on a word-read current that is provided on the respective word-read line <NUM> to select a given one of the rows <NUM> and a bit-read current that is provided on the respective bit-read line <NUM>. Specifically, the bit-read line <NUM> of each of the columns <NUM> is coupled to a sense register <NUM> that is configured to measure the respective bit-read line <NUM> to determine whether digital state of each of the memory cells <NUM> of an associated row <NUM> correspond to a binary logic-<NUM> state or a binary logic-<NUM> state in response to the word-read current and the bit-read current during a data read operation. As an example, the sense register <NUM> can measure a voltage or a current associated with the bit-read line <NUM>, as described in greater detail herein.

In view of the foregoing structural and functional features described above, a methodology in accordance with various aspects of the present invention will be better appreciated with reference to <FIG>. While, for purposes of simplicity of explanation, the methodology of <FIG> is shown and described as executing serially, it is to be understood and appreciated that the present invention is not limited by the illustrated order, as some aspects could, in accordance with the present invention, occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, not all illustrated features may be required to implement a methodology in accordance with an aspect of the present invention.

Claim 1:
A memory cell system (<NUM>) comprising:
a quantizing loop (<NUM>) configured to conduct a quantizing current in a first direction corresponding to storage of a first state of a stored memory state of the memory cell system and to conduct the quantizing current in a second direction opposite the first direction corresponding to storage of a second state of the stored memory state of the memory cell system;
a bias element (<NUM>) configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state, the stored memory state being read from the memory cell system in response to the substantially constant flux bias and a read current that is provided to the memory cell system; and
a tunable energy element (<NUM>) that is responsive to a write current that is provided to the memory cell system to change the state of the stored memory state between the first state and the second state.