Patent Description:
Quantum computing is a relatively new computing method that takes advantage of quantum effects, such as superposition of basis states and entanglement to perform certain computations more efficiently than a classical digital computer. In contrast to a digital computer, which stores and manipulates information in the form of bits (e.g., a "<NUM>" or "<NUM>"), quantum computing systems can manipulate information using qubits. A qubit can refer to a quantum device that enables the superposition of multiple states (e.g., data in both the "<NUM>" and "<NUM>" state) and/or to the superposition of data, itself, in the multiple states. In accordance with conventional terminology, the superposition of a "<NUM>" and "<NUM>" state in a quantum system may be represented, e.g., as α | <NUM>> + β | <NUM>>. The "<NUM>" and "<NUM>" states of a digital computer are analogous to the | <NUM>> and | <NUM>> basis states, respectively of a qubit. The value |α|<NUM> represents the probability that a qubit is in | <NUM>> state, whereas the value |β|<NUM> represents the probability that a qubit is in the | <NUM>> basis state. <NPL>) describes an arrangement in which Xmon qubits are placed in a checkerboard pattern in a single layer, with data qubits and measurement qubits. Control, readout, and wiring are placed in other layers; connections between the layers are made by capacitive coupling, and by bump bonds and vias for galvanic connections.

In general, in some aspects, the present disclosure relates to one or more devices that include a first chip including a superconducting qubit, where the superconducting qubit includes a superconducting quantum interference device (SQUID) region, a control region, and a readout region, and a second chip bonded to the first chip, where the second chip includes a first control element overlapping with the SQUID region, a second control element displaced laterally from the control region and without overlapping the control region, and a readout device overlapping the readout region.

In some implementations, the pad element is symmetrically aligned with the readout region.

In some implementations, a surface area of the readout region facing the second chip and overlapped by the pad element is less than a surface area of the pad element facing the first chip.

In some implementations, the pad element is operable to capacitively couple to the readout region.

In some implementations, the first chip includes a superconductor ground plane with an edge aligned with the control region of the superconducting qubit, such that the edge includes a recessed region where a portion of the superconductor ground plane is removed and where the control element is aligned over the recessed region.

In some implementations, a surface area of the second control element facing the first chip is less than a surface area of the recessed region facing the second chip.

In some implementations, the second control element is operable to capacitively couple to the control region.

In some implementations, the second element is operable to excite the superconducting qubit.

In some implementations, the first control element includes a bias coil, where the bias coil includes a layer of superconductor material arranged in a loop, and where the SQUID region includes a SQUID arranged in a ring.

In some implementations, the loop includes an inner loop edge and an outer loop edge, where the inner loop edge is aligned within an inner area of the ring, and the outer loop edge is aligned outside the inner area of the ring.

In some implementations, a lateral distance between the inner loop edge and an edge of the ring defining the inner area of the ring is at least <NUM> microns, and a lateral distance between the outer loop edge and the edge of the ring defined by the inner area of the ring is at least <NUM> microns.

In some implementations, the loop includes an inner loop edge and an outer loop edge, where the outer loop edge is aligned within an inner area of the ring.

In some implementations, a lateral distance between the outer loop edge and an edge of the ring defining the inner area of the ring is at least <NUM> microns.

In some implementations, the first control element is operable to tune the superconducting qubit.

In some implementations, the first control element is operable to inductively couple to the SQUID region.

In some implementations, the first chip is bump bonded to the second chip.

In some implementations, there is a gap between the first chip and the second chip, where a height of the gap between the first chip and the second chip is <NUM>-<NUM> microns.

In some implementations, the first control element, the second control element, and the readout device include superconductor material.

In some implementations, the superconducting qubit is a transmon qubit, a flux qubit, or a gmon qubit.

Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages. For example, in some embodiments, devices and methods disclosed herein increase chip misalignment tolerance to preserve qubit coherence and qubit coupling strength, while reducing stray coupling effects in a stacked quantum computing device (e.g., a flip-chip architecture). Additionally, in some embodiments, the devices and methods disclosed herein allow an increase in qubit density (e.g., from one-dimensional chains of superconducting qubits to two-dimensional arrays of superconducting qubits) and/or an increase in qubit coupling through 3D integration. Moreover, in some embodiments, the devices and methods disclosed herein can reduce energy loss and dissipation in quantum circuit elements that may be caused by deposited dielectric materials.

Quantum computing entails coherently processing quantum information stored in the quantum bits (qubits) of a quantum computer. Superconducting quantum computing is a promising implementation of quantum computing technology in which quantum computing circuit elements are formed, in part, from superconductor materials. Superconducting quantum computers are typically multilevel systems, in which only the first two levels are used as the computational basis. In certain implementations, quantum circuit elements (e.g., quantum computing circuit elements), such as qubits, are operated at very low temperatures so that superconductivity can be achieved and so that thermal fluctuations do not cause transitions between energy levels. Additionally, it may be preferable that the quantum computing circuit elements are operated with low energy loss and dissipation (e.g., the quantum computing circuit elements exhibit a high quality factor, Q). Low energy loss and dissipation may help to avoid, e.g., quantum decoherence.

In certain types of quantum computing processors, such as quantum annealers, the qubits of the quantum processor are operatively coupled together in a controllable manner such that the quantum state of each qubit affects the corresponding quantum states of the other qubits to which it is coupled. Depending on the processor design, the chosen architecture may limit the density and total number of qubits available for coupling, and thus limit the ability of the processor to perform complex problems requiring large numbers of qubits. Furthermore, in certain quantum computing designs, the qubits may suffer energy loss and decoherence due to interactions with two level systems. The two-level systems (TLS) are material defects inherently present in a dielectric substrate, originating from the tunnelling between two configurations of atoms within the dielectric substrate, or in some implementations at the interface between material layers. For instance, in quantum computers that use qubits formed from superconductor materials, the presence of lossy non-superconductor materials from, e.g., deposited dielectrics, classical circuit elements with which the quantum computers communicate, and from the connections between the classical circuit elements and the quantum circuit elements can lead to increased decoherence. To increase qubit density and expand the number of qubits available for coupling in a quantum processor, such as a quantum annealer having superconductor quantum circuit elements, the processor and associated circuit elements can be constructed using 3D integration. That is, instead of fabricating the quantum circuit elements of the processor within a single plane of a chip that extends along one and/or two dimensions (e.g., x- and/or y- directions), the quantum circuit elements can also be formed in multiple chips that are coupled together along a third dimension (e.g., z-direction). An approach for achieving 3D integration, without introducing lossy processing/dielectrics, is to couple the chips using bump bonding, in which the chips are joined to one another by, e.g., superconductor bump bonds. In some implementations, bump bonds may be used to electrically couple together components from the different chips in addition to physical coupling of the chips. Alternatively, bump bonds solely may be used to provide physical coupling of different chips together. By using superconductor bump bonds for coupling, it is possible to achieve a reduction in the energy loss and decoherence that can otherwise occur with lossy non-superconductor materials.

Alignment is a challenge in the fabrication process of a stacked quantum computing device, specifically between interacting elements located on separate chips, which can be electrically and mechanically connected through the use of bump bonds.

The present disclosure relates to devices and methods for coupling stacked quantum computing devices. In particular, in some implementations, the present disclosure relates to providing multiple chips arranged in a stack, in which a first chip in the stack includes a two-dimensional array of qubits and at least a second chip in the stack includes control elements for coupling to the qubits in the first chip.

<FIG> is a schematic illustrating an example of a two-dimensional array of superconducting qubits <NUM>. The array of superconducting qubits <NUM> may be a part of a quantum computational system (e.g., a quantum annealer) for performing quantum computing operations. In the example shown in <FIG>, each superconducting qubit is an xmon qubit, illustrated generally in the shape of a "plus" sign having four arms. Qubits <NUM> may include, but are not limited to, other types of qubits such as flux qubits, transmon qubits, and gmon qubits. <FIG> depicts a four-by-four array of superconducting qubits <NUM>, but any number of qubits may be implemented in a one-dimensional (1D) or two-dimensional (2D) array. Operating a quantum computational system that includes an array of superconducting qubits, such as the array of superconducting qubits <NUM>, entails, in some implementations, coupling the superconducting qubits of the array together. For instance, nearest neighbor qubits 102a and 102b may couple to one another through their neighboring arms. Similarly, each of the inner qubits (e.g., qubits 102c and 102d) in the 2D array may directly couple to four nearest neighbor qubits. For example, qubit 102c may couple with qubits 102b, 102d, 102e, and 102f.

With increasing the number of qubits in a 2D array, coupling to the qubits rapidly becomes very challenging. For instance, in a qubit array, such as array <NUM>, each inner qubit may be required to make <NUM> separate connections (e.g., <NUM> connections to each nearest neighbor qubit and <NUM> connections for readout control, Z-control and XY-control). As the number of qubits within the array increases, the space for providing wiring decreases. One option is to wire the qubits using traditional complementary metal-oxide-semiconductor (CMOS) techniques, such as forming the wiring in multiple layers of deposited dielectrics. However, such dielectrics are associated with high loss that causes qubits to decohere.

Another approach to address qubit wiring is to locate the wiring and other control elements on a separate chip that is coupled to a chip that contains the qubits. For example, wiring for the respective control elements (e.g., Z-control and XY-control) and a readout resonator for each superconducting qubit in array <NUM> can be moved from a chip on which the qubits are formed to a separate second chip. In some implementations, the first chip containing the qubit array <NUM> is electrically and mechanically connected to the second chip containing wiring and qubit control elements using, e.g., superconductor bump bonds such as indium.

<FIG> is a schematic illustrating an example of a stacked quantum computing device <NUM> including a first chip <NUM> and a second chip <NUM>. The first chip <NUM> includes a two-dimensional array <NUM> of superconducting qubits. Each superconducting qubit in the example array <NUM> is an xmon qubit, though other qubits may be used instead. The second chip <NUM> includes readout device <NUM> and control elements <NUM>, <NUM>. Each of the first chip <NUM> and the second chip <NUM> may also include one or more circuit elements for performing data processing operations.

The superconducting qubits of the first chip <NUM> may be formed on a substrate. The substrate of the first chip may be formed from, e.g., a low loss and single crystalline dielectric, such as a silicon or sapphire wafer. A low loss dielectric can be defined, in part, by having a small loss tangent at microwave frequencies (<NUM>-<NUM>) at or less than 1e-<NUM>. Other materials may be used for the substrate instead.

The readout device <NUM> of the second chip <NUM> may include, for example, readout resonators. The control elements <NUM>, <NUM> may include, e.g., a first control element <NUM> (e.g., Z-control) and a second control element <NUM> (e.g., XY-control). A superconducting qubit Z-control element is operable to tune an operating frequency of a superconducting qubit to which the control element is coupled upon application of a control pulse to the Z-control element. A superconducting qubit XY-control element is operable to excite a superconducting qubit to which the XY-control element is coupled, upon application of a control signal to the XY-control element. A readout device is operable to readout a state of a superconducting qubit to which the readout device is capacitively coupled by probing the frequency of the resonator element.

Similar to the first chip <NUM>, the second chip <NUM> also may include a substrate formed from a low loss dielectric material suitable for quantum circuits, such as single crystalline silicon or sapphire. The thickness of the substrate may be between, e.g., approximately <NUM> microns and approximately <NUM> microns.

The first chip <NUM> is bonded electrically and/or mechanically to the second chip through bonds <NUM> (e.g., bump bonds).

<FIG> are schematics illustrating different views of an example of a stacked quantum computing device. <FIG> shows a cross-sectional view of a stacked quantum computing device <NUM> of a first chip <NUM> aligned on top of a second chip <NUM> and connected electrically and/or mechanically using bump bonds <NUM>. The bump bonds <NUM> may include superconductor material to avoid energy loss and decoherence of qubits that may be located, e.g., on the first chip <NUM>. For instance, suitable superconductor material for use as a bump bond <NUM> includes, but is not limited to, indium, lead, rhenium, palladium, or niobium having a thin layer of gold.

The thickness of the bump bonds <NUM> may be set so that the first chip <NUM> and the second chip <NUM> are spaced at a gap <NUM> apart. The approximate height of the gap <NUM> may be within an uncertainty based on the accuracy and/or precision limitations of the deposition technique(s) used to deposit and/or remove material to form the bump bonds <NUM> (and/or other components that may affect the distance) as well as of the metrology technique(s) with which the height of the gap is measured. In some implementations, the height of the gap between the first chip <NUM> and the second chip <NUM> is at least <NUM> microns.

<FIG> shows a schematic illustrating a top-view through the second chip <NUM> of a stacked quantum computing device layout <NUM> where the second chip <NUM> is aligned over the first chip <NUM>. The first chip <NUM> includes a superconducting qubit <NUM>, which includes a readout region <NUM>, a superconducting quantum interface device (SQUID) region <NUM>, and a control region <NUM>. The readout region <NUM> of the superconducting qubit <NUM> corresponds to an area of the superconducting qubit <NUM> defined around a center of the superconducting qubit <NUM>, and follows the outline of the central portion of the superconducting qubit <NUM> within the dashed outline. For example, with respect to the example shown in <FIG>, superconducting qubit <NUM> is an Xmon style qubit exhibiting a cross-like shape having four long arms, and additionally including a portion of a shorter arm in the upper-left quadrant branching out from the center of the superconducting qubit <NUM> (e.g., corresponding to the SQUID loop of the superconducting qubit). The readout region <NUM> can be shaped to cover the area of the superconducting qubit <NUM> when the first chip and the second chip are aligned with respect to one another including a central portion, a portion of each of the four arms, and optionally including a portion of the branch corresponding to the SQUID loop of the superconducting qubit <NUM>. Readout region <NUM> is discussed in more detail with reference to <FIG> below.

The SQUID region <NUM> of the superconducting qubit <NUM> corresponds to an area of the superconducting qubit <NUM> including a portion of the shorter arm in the upper left quadrant branching out of the center (e.g., corresponding to the SQUID loop) of the superconducting qubit <NUM> within the dashed outline. SQUID region <NUM> is discussed in more detail with reference to <FIG> below.

The control region <NUM> of the superconducting qubit <NUM> corresponds to an area of the superconducting qubit <NUM> (e.g., including a portion of one arm of the superconducting qubit <NUM>). The control region <NUM> is adjacent to a recessed region <NUM> which is formed within an edge of the ground plane that faces the control region <NUM>, where a "tab" potion of the superconductor ground plane that has been removed directly adjacent to the superconducting qubit <NUM>. For example, with respect to the example shown in <FIG>, superconducting qubit <NUM> is an Xmon style qubit and where recessed region <NUM> is a portion of the superconductor ground plane adjacent to one of the arms of the superconducting qubit <NUM> that has been removed. The control region <NUM> and the recessed region <NUM> are discussed in more detail with reference to <FIG> below.

Though qubit <NUM> is shown as an Xmon style qubit, other qubits may be used instead, each of which also include a corresponding readout region, SQUID region and control region as detailed herein.

The second chip <NUM> includes a readout device <NUM>, the readout device including a resonator element <NUM> electrically coupled to a pad element <NUM>. The second chip <NUM> can also include wiring elements <NUM>. Bump bonds (e.g., <NUM>) contact the first chip <NUM> and the second chip <NUM>. Additionally, the second chip <NUM> can include a first control element <NUM> (e.g., a Z-control element), and a second control element <NUM> (e.g., an XY control element).

In some implementations, the pad element <NUM> on the second chip <NUM> is oriented on the second chip <NUM> such that when the first chip <NUM> and the second chip <NUM> are aligned (e.g., as seen in <FIG>), the pad element <NUM> is symmetrically aligned with the readout region <NUM> of a corresponding superconducting qubit <NUM> on the first chip <NUM> such that the pad element <NUM> can electromagnetically couple (e.g., capacitively) to the readout region <NUM> of the second chip. In some implementations, if the pad element <NUM> and the readout region <NUM> are of the same shape, they can be symmetrically aligned such that their centers coincide with one another and their edges (or, when the edges are curved, the tangents to their edges) are disposed substantially parallel to one another. Additionally, the resonator element <NUM> of the readout device <NUM> on the second chip <NUM> is oriented on the second chip <NUM> such that when the first chip <NUM> and the second chip <NUM> are aligned (e.g., as seen in <FIG>), superconducting qubit <NUM> on the first chip <NUM> is not located directly underneath the resonator element <NUM>. More detail of the readout device is discussed with reference to <FIG>.

In some implementations, the first control element <NUM> is arranged on the second chip <NUM> so that the SQUID region <NUM> of the superconducting qubit <NUM> on the first chip <NUM> is aligned directly underneath with respect to the first control element <NUM> on the second chip <NUM>. By positioning the SQUID region <NUM> directly beneath the first control element <NUM>, the first control element <NUM> can electromagnetically couple (e.g., inductively) couple to the qubit through the SQUID region <NUM>. The alignment of the SQUID region <NUM> with respect to the first control element <NUM> is discussed in more detail with reference to <FIG> below.

The second control element <NUM> is arranged on the second chip <NUM> so that the second control element <NUM> is displaced laterally from and does not overlap the control region <NUM> of the superconducting qubit. Rather, the second control element <NUM> is aligned over the recessed region <NUM> of the superconducting qubit <NUM> on the first chip <NUM>. By positioning the recessed region <NUM> directly beneath the second control element <NUM> and displacing the second control element <NUM> from the control region <NUM>, the second control element <NUM> can electromagnetically couple (e.g., by mutual capacitance of the fringing fields) to the qubit through the control region <NUM>. The alignment of the control region <NUM> with respect to the second control element <NUM> is discussed in more detail with reference to <FIG> below.

In some implementations, the gap <NUM> between a first chip <NUM> and a second chip <NUM>, as depicted in <FIG>, is set to achieve a desired capacitive or inductive coupling between circuit elements on the first chip <NUM> and on the second chip <NUM> (e.g., a readout region <NUM> of a superconducting qubit <NUM> on the first chip <NUM> and a readout device <NUM> on the second chip <NUM>).

For example, a height of the gap <NUM> between the device surface of the first chip <NUM> and the structural element surface of the second chip <NUM> may be set to be between approximately <NUM> and approximately <NUM> (e.g., between approximately <NUM> and approximately <NUM>, between approximately <NUM> and <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, between approximately <NUM> and approximately <NUM>, or between approximately <NUM> and approximately <NUM>).

<FIG> is a schematic illustrating a top-view <NUM> through a second chip of a stacked quantum computing device, where a second chip <NUM> is aligned to a first chip <NUM> with bump bonds (e.g., superconductor bump bonds <NUM>) bonding the two chips together. In the schematic of <FIG>, the white regions correspond to superconductor material, the shaded regions correspond to an exposed surface of the substrate. In the schematic of <FIG> the superconductor layer and substrate of the second chip <NUM> are transparent and respective circuit elements on the second chip <NUM> are depicted as outlines defined by the regions where the substrate of the second chip is exposed (e.g., regions where the superconductor layer has been removed) only.

The first chip <NUM> includes a superconducting qubit <NUM>, where the white regions correspond to superconductor material (e.g., aluminum) and the dark regions correspond to exposed surface of the substrate (e.g., dielectric substrate). The superconducting qubit <NUM> depicted in <FIG> is an Xmon type superconducting qubit. Other qubit types, for example, gmon, fluxmon, or transmon qubits may be used instead. A readout region <NUM>, a SQUID region <NUM>, and a recessed region <NUM> adjacent to an edge of a control region <NUM> of the superconducting qubit <NUM> on the first chip 302are identified by respective dashed outlines.

The second chip <NUM> includes a readout device <NUM>, which includes an electrically coupled pad element <NUM> and a resonator element <NUM>. The pad element <NUM> includes a cross-shape superconductor pad aligned over the center of the superconducting qubit <NUM>. As depicted in <FIG>, the pad element <NUM> is shown as a transparent cross-shape outline aligned within the dashed outline of the readout region <NUM>, however, the interior portion of the cross-shaped outline is to be understood to be composed of superconductor material. The resonator element <NUM> includes, e.g., an elongated superconductor co-planar waveguide trace. The resonant frequency/mode of the resonator element <NUM> is determined, in part, by its length and effective permittivity. To conserve space on the second chip <NUM>, the resonator element <NUM> is arranged in a serpentine-like shape.

The second chip <NUM> additionally includes a first control element <NUM> which overlaps the SQUID region <NUM> of the superconducting qubit <NUM> on the first chip <NUM>, when the first chip <NUM> and the second chip <NUM> are aligned and bonded together (e.g., by bump bonds <NUM>). The first control element <NUM> is depicted in <FIG> such that the superconductor layer (e.g., aluminum) of the first control element <NUM> is transparent, and the outline of the first control element <NUM> (e.g., regions where the superconductor material has been removed and the substrate is exposed) is depicted in black. Further details of the first control element <NUM> is discussed with reference to <FIG> and <FIG> below.

The second chip <NUM> further includes a second control element <NUM> which overlaps the recessed region <NUM> of the superconducting qubit <NUM> on the first chip <NUM> when the first chip <NUM> and the second chip <NUM> are aligned and bonded together (e.g., by bump bonds <NUM>). The second control element <NUM> is depicted in <FIG> such that the superconductor layer (e.g., aluminum) of the second control element <NUM> is transparent, and the outline of the second control element <NUM> (e.g., regions where the superconductor material has been removed and the substrate is exposed) is depicted in black. Further details of the second control element <NUM> is discussed with reference to <FIG> and <FIG> below.

<FIG> is a schematic illustrating a top-view of an exemplary readout device <NUM>, formed on a second chip <NUM> of a stacked quantum computing device and that will face the first chip (e.g., first chip <NUM> shown in <FIG>) when the first chip and the second chip are bonded together. White areas in <FIG> correspond to regions where at least a layer superconductor material is present, whereas grey/black areas correspond to regions where there is an absence of superconductor material and where the substrate may be exposed. Readout device <NUM> (corresponding to the elements within the dashed line region shown in <FIG>) includes, e.g., a pad element <NUM> and a resonator element <NUM>, and can be made of a superconductor material (e.g., aluminum). An example of readout device <NUM> includes a quarter-wave co-planar waveguide resonator.

In some implementations the resonator element <NUM> is a distributed element resonator or a lumped element resonator, such as a co-planar waveguide resonator formed from superconductor material (e.g., aluminum) where the frequency of the resonator is determined in part by the resonator length.

During operation of the stacked quantum computing device, the pad element <NUM> may be electromagnetically coupled (e.g., capacitively coupled) to a superconducting qubit (e.g., superconducting qubit <NUM> in <FIG>) on the first chip (e.g., first chip <NUM> in <FIG>), in which the qubit is located directly beneath the pad element <NUM>. The superconducting qubit <NUM> on the first chip <NUM> then may be read during operation of the stacked quantum computing device by probing the frequency of the resonator element <NUM>. Pad element <NUM> can have various surface area geometries, depending in part on the respective shape of the superconducting qubit and an amount of capacitance required. For example, as depicted in <FIG>, superconducting qubit <NUM> is an Xmon style qubit exhibiting a cross-like shape having four long arms, and additionally including a portion of a shorter arm in the upper-right quadrant branching out from the center of the superconducting qubit <NUM> (e.g., corresponding to the SQUID loop of the superconducting qubit). The pad element <NUM> shown in <FIG>, can be cross-shaped such that when the first chip and the second chip are aligned, the area of the superconducting qubit <NUM> that is covered by the pad element <NUM> includes a central portion, a portion of each of the four arms of the superconducting qubit <NUM>. In some implementations a portion of the branch corresponding to the SQUID loop of the superconducting qubit <NUM> is also covered by the pad element <NUM>. In another example, for a gmon qubit, a pad element may have a square or rectangular shape.

In some implementations, the resonator element <NUM> and the pad element <NUM> shown in <FIG> are formed from a same layer on the second chip <NUM>. In some implementations the resonator element <NUM> and the pad element <NUM> are formed in different layers on the second chip <NUM>.

<FIG> is a schematic illustrating a top-view of an exemplary superconducting qubit <NUM> formed on a first chip <NUM>, in which the first chip <NUM> is to be bonded to the second chip <NUM>. White areas correspond to regions where superconductor material is present whereas shaded areas correspond to regions where there is an absence of superconductor material and where the substrate may be exposed. The first chip <NUM> includes a superconducting qubit <NUM>, such as an Xmon qubit, though other types of superconducting qubits may be used instead. In the example shown in <FIG>, a readout region <NUM> of the superconducting qubit <NUM> corresponds to an area around a center of the superconducting qubit <NUM>, and follows the outline of the central portion of the superconducting qubit <NUM> including at least a portion of each of the four arms of the superconducting qubit <NUM>. Additionally, in some implementations, a portion of the branch <NUM> corresponding to a SQUID loop that extends from the center to the upper-right corner of the superconducting qubit <NUM> is also included in the readout region <NUM> of the superconducting qubit <NUM>.

<FIG> is a schematic that illustrates a top-view through the second chip <NUM> of a stacked quantum computing device that includes the second chip <NUM> bonded to the first chip <NUM> such that outlines of the circuit elements on the first chip as aligned with the circuit elements on the second chip are visible. As shown in <FIG>, the readout device <NUM>, which includes pad element <NUM>, resonator element <NUM>, is aligned such that the pad element <NUM> is located directly over the readout region <NUM> of the superconducting qubit <NUM> on the first chip <NUM>. In contrast, the resonator element <NUM> is laterally displaced so that it does not directly overlap the superconducting qubit <NUM> on the first chip <NUM>. This arrangement can reduce undesired coupling and/or interference between the resonator element <NUM> and the superconducting qubit <NUM>.

During operation of the stacked quantum computing device, the readout device <NUM> may be electromagnetically coupled to the portion of the superconducting qubit <NUM> located in the readout region <NUM>. For example, the pad element <NUM> may be capacitively coupled to the readout region <NUM> of the superconducting qubit <NUM>. An amount of capacitance between the pad element <NUM> and the qubit can vary depending on the relative sizes of the pad element <NUM> and the qubit <NUM>, the overlap between the two, and the gap distance between the first and second chip. In some implementations, the dimensions of the pad element <NUM> may be modified to achieve a particular capacitance. For example, the dimensions of the pad element <NUM> are adjusted to achieve a capacitance between qubit <NUM> and pad element <NUM> of between approximately <NUM> and <NUM> femtofarads. Other capacitance values are possible as well.

In some implementations, the surface area of the superconducting qubit <NUM> included in the readout region <NUM> of the superconducting qubit <NUM> on the first chip (e.g., the area of the superconducting qubit <NUM> that is within the dashed outline depicted in <FIG>) that faces the pad element <NUM> on the second chip is less than the surface area of the pad element <NUM> facing the first chip. For example, one or more dimensions (e.g., width <NUM>) of one or more respective arms of the cross-shaped pad element <NUM> may be enlarged to allow for a misalignment between the bonded first chip and second chip. That is, even if there is slight misalignment between the first chip and the second chip, the magnitude of mutual coupling between the readout device <NUM> and the superconducting qubit <NUM> remains substantially the same because the pad element <NUM> would still be aligned over a same area of the superconducting qubit <NUM>. An example misalignment can include, e.g., a few microns in the y-direction. Thus, adding a few microns to width <NUM> on the arm of the pad element <NUM> such that the width is several microns larger than a corresponding width of an arm of the superconducting qubit <NUM> within the readout region <NUM> (e.g., width <NUM>) allows for a misalignment of the respective readout region <NUM> and the superconducting qubit <NUM> during a bonding process of the first and second chips.

In some implementations, a length (e.g., length <NUM>) of one or more arms of the cross-shaped pad element <NUM> may be altered to adjust a capacitance between the qubit <NUM> and the pad element <NUM>. In general, the amount of overlap between the surface area of the pad element <NUM> and the surface area of the qubit <NUM> in the readout region <NUM> dictates in part the capacitance between the qubit <NUM> and the pad element <NUM> in the form of parallel plate capacitance.

<FIG> is a schematic illustrating a top-view of a first control element <NUM>, such as control element <NUM> in <FIG>, formed on a second chip. White areas correspond to regions where there is at least a layer of superconductor material, whereas shaded areas correspond to regions where there is an absence of superconductor material and where the substrate may be exposed. The first control element <NUM> can include, e.g., a qubit Z-control element. A qubit Z-control element is operable to tune an operating frequency of a superconducting qubit to which the first control element <NUM> is coupled upon application of a control pulse to the Z-control element. The first control element <NUM> shown in <FIG> includes bias coil formed from a layer of superconductor material arranged on a surface of a substrate. The bias coil formed from a superconductor layer includes a first portion <NUM> coupled to a ground plane <NUM>, a second portion <NUM> that, during operation of the stacked quantum computing device, is coupled to a source that provides the control pulse, and a third loop portion <NUM>.

The loop portion <NUM> of the bias coil includes an inner loop edge <NUM> and an outer loop edge <NUM>. The outer loop edge <NUM> is separated from the superconductor ground plane <NUM> by a gap <NUM>. As shown in <FIG>, the width <NUM> of the superconductor material in first portion <NUM> and second portion <NUM> is much narrower than the width <NUM> of the superconductor material in the loop portion <NUM>. This reduces the footprint of the bias line. To prevent unexpected return currents, ground connections are connected where the bias line is shorted. This may be achieved using bump bonds, such as bump bonds <NUM> shown in <FIG> on either side of the bias line region <NUM>. Inner loop edge <NUM> and outer loop edge <NUM> are formed on the second chip such that the inner loop edge is within a SQUID region <NUM> of a superconducting qubit on a first chip when the first chip and second chip are aligned and bonded together (e.g., the inner loop edge is contained within an inner ring area <NUM> of the SQUID region <NUM>). Outer loop edge <NUM> is formed such that the inner ring area <NUM> of the SQUID region <NUM> of the superconducting qubit on the first chip is fully contained by the outer loop edge <NUM> of the loop portion <NUM> on the second chip when the first chip and the second chip are aligned.

<FIG> is a schematic that illustrates a top-view of an example of a superconducting quantum interference device (SQUID) region <NUM> of a superconducting qubit, such as the superconducting qubit <NUM> shown in <FIG>. White areas correspond to regions where a layer of superconductor material is present, whereas shaded areas correspond to regions where the superconductor material is absent and the substrate of the first chip may be exposed. In the example shown in <FIG>, the SQUID within the SQUID region <NUM> is physically coupled to and extends from a center region of a superconducting qubit. The SQUID region <NUM> includes a layer of superconductor material arranged in a generally ring shape, in which the superconductor material is interrupted in multiple locations by Josephson junctions <NUM>. The superconductor wires of the Josephson junctions <NUM> are depicted in black. A portion of the SQUID region <NUM> may be formed by a superconductor ground plane <NUM>. In the present example, the SQUID region <NUM> therefore has an inner ring area <NUM> in which no superconductor is present. The area/perimeter of the inner ring area <NUM> is defined by the edges <NUM> of the superconductor material.

When aligning the first chip to the second chip to provide the stacked quantum computing device, the first control element <NUM> is aligned over the SQUID region <NUM> of a corresponding qubit. During operation of the stacked quantum computing device, the first control element <NUM> may be electromagnetically coupled (e.g., inductively coupled) to the SQUID within the SQUID region <NUM>. Upon application of a control pulse to the first control element <NUM>, the inductive coupling allows the operating frequency of the qubit to be tuned. The first control element <NUM> and the SQUID of the SQUID region <NUM> are associated with a mutual inductance. For example, the mutual inductance may be between about <NUM> pH to about <NUM> pH.

<FIG> is a schematic that illustrates a top-view of the first control element <NUM> aligned over the SQUID region <NUM>. In general, for superconductor circuit elements, current flows primarily along the edges of the superconductor layer that forms the circuit element. As a result, variations in the location of the edges of the superconductor material that forms the first control element bias coil <NUM> relative to the superconductor material the forms the SQUID inner ring area <NUM> can lead to variations in the desired mutual inductance between the first control element and the SQUID region, as well as increase stray mutual inductance, which can lead to qubit decoherence. Such variations can be due to, e.g., misalignment between the first chip and the second chip during the bonding process.

To achieve high coupling to the SQUID region <NUM> and reduce stray mutual inductance and to avoid variations in the desired mutual inductance caused by misalignment when bonding, the bias coil <NUM> of the first control element <NUM> is kept substantially symmetric. For example, by providing the inner loop portion <NUM> of the bias coil <NUM> to have a shape that is symmetric with respect to the outer loop edge <NUM> of the bias coil <NUM> (e.g., such that the stray magnetic fields of each are equal and opposite), stray flux from the loop portion <NUM> cancels itself out through symmetric cancellation, while maintaining high coupling to the SQUID region <NUM>. Furthermore, the SQUID region <NUM> is located near the ground plane and away from other features of the superconducting qubit (e.g., a readout region or a control region of the superconducting qubit), such that the influence of flux from those other features (e.g., other features excluding the SQUID region <NUM>, or other adjacent superconducting qubits) is reduced.

Additionally, the area of the loop portion <NUM> of the bias coil is made large relative to the inner ring area <NUM> of the SQUID region <NUM> to provide some tolerance for misalignment. That is, when there is misalignment error between the first and second chip, the location of the inner loop edge <NUM> of the bias coil is likelier to remain located at a position that is directly over the inner ring area <NUM>. Additionally, the location of the outer loop edge <NUM> is likelier to remain located far from the inner ring area <NUM>, such that stray mutual inductance resulting from current traveling along the outer loop edge <NUM>. For example, a lateral distance between the inner loop edge <NUM> and an edge <NUM> of the inner ring area <NUM> (e.g., lateral distance <NUM>) ranges between about <NUM> micron to about <NUM> microns. Additionally, in some implementations, a lateral distance between the edge <NUM> of the inner ring area and an edge <NUM> of the outer loop (e.g., lateral distance <NUM>) ranges between about <NUM> micron to about <NUM> microns. The range of lateral distances <NUM> and <NUM> can depend on an alignment error of the stacked quantum computing device configuration. For example, if the alignment error includes <NUM> microns of misalignment along the X-axis or Y-axis, the range of lateral distances <NUM> and <NUM> can be set to <NUM> microns.

In some implementations, the inner loop edge <NUM> and the outer loop edge <NUM> of the bias coil <NUM> may be located within the inner ring area <NUM> when the first chip is aligned and bonded to the second chip. In such cases, the outer loop edge <NUM> is a lateral distance of at least <NUM> micron within an edge <NUM> of the inner ring area <NUM>.

<FIG> is a schematic illustrating a top-view of an example of a second control element <NUM>, such as second control element <NUM> of <FIG>, on a second chip. White areas correspond to regions where superconductor material is present whereas shaded areas correspond to regions where there is an absence of superconductor material and where the substrate may be exposed. The second control element <NUM> can include, e.g., a qubit XY-control element. A superconducting qubit XY-control element is operable to excite a qubit to which the XY-control element is coupled, upon application of a control signal to the XY-control element. The second control element <NUM> shown in <FIG> includes a pad element <NUM> and a wiring element <NUM>. The pad element <NUM> is located at an end of a wiring element <NUM>. The wiring element <NUM> may be coupled to a signal source that provides the control signal to the XY-control element. The pad element <NUM> and the wiring element <NUM> are formed in a superconductor layer (e.g., a superconductor thin film) on the second chip, where the pad element <NUM> and wiring element <NUM> are separated from the superconductor ground plane <NUM> through a gap <NUM> in the superconductor layer (e.g., by exposing the substrate). Pad element <NUM> includes a pad element length <NUM> and a pad element width <NUM>.

<FIG> is a schematic illustrating a top-view of a control region <NUM> of a superconducting qubit, such as the superconducting qubit <NUM> of <FIG>, on a first chip. In general, the control region of the superconducting qubit includes an area of the superconducting qubit (e.g., a portion of an arm of the superconducting qubit) in which the superconducting qubit on a first chip may be excited by a second control element <NUM> (e.g., an XY-control element) on the second chip to which the second control element is coupled upon application of a control signal by the second control element <NUM>. In the example where the superconducting qubit is an Xmon qubit type, the control region <NUM> of the superconducting qubit includes at least a portion of one arm of the superconducting qubit.

White areas correspond to regions where superconductor material is present whereas shaded areas correspond to regions where there is an absence of superconductor material and where the substrate may be exposed. Also shown in <FIG> is a superconductor ground plane <NUM>. An edge <NUM> of the ground plane <NUM> is aligned parallel with an edge <NUM> of the control region <NUM>, and is separated from the edge <NUM> by a gap <NUM> in the superconductor material (e.g., an area where the substrate is exposed). The edge <NUM> of the ground plane <NUM> further includes a recessed (or notch or indentation) region <NUM> where there is an absence of superconductor material and where the substrate may be exposed. Recessed region <NUM> includes a recessed region length <NUM> and a recessed region width <NUM>, which can be larger than the pad element length <NUM> and pad element width <NUM>, respectively.

<FIG> is a schematic that illustrates a top-view of the second control element <NUM> of <FIG> aligned over the recessed region <NUM> of <FIG>. The schematic in <FIG> also illustrates an outline of the control region <NUM> of the superconducting qubit adjacent to the recessed region <NUM> of <FIG> and aligned relative to the second control element <NUM>. A ground plane <NUM> on the first chip also is shown. As shown in <FIG>, the pad element <NUM> of the second control element <NUM> is displaced laterally from and does not overlap the control region <NUM> of the superconducting qubit. Rather, the second control element <NUM> is aligned over the recessed region <NUM>. By laterally displacing the second control element <NUM> from the control region <NUM> as shown in <FIG>, substantial over-coupling (that may otherwise occur if the second control element <NUM> were placed directly on or overlapping with the control region <NUM>) can be avoided. With the arrangement shown in <FIG>, the second control element <NUM> and the control region <NUM> of the superconducting qubit are capacitively coupled by mutual capacitance of the fringing fields between the second control element <NUM> and the control region <NUM> of the superconducting qubit. For example, the second control element <NUM> and the control region <NUM> of the superconducting qubit have a mutual capacitance of <NUM> attofarads to achieve control (e.g., XY-control) of the superconducting qubit.

In some implementations, the second control element <NUM> is aligned to be entirely within the area of the recessed region <NUM> when the first chip and the second chip are bonded together. The surface area of the recessed region <NUM> is selected to account for misalignment of the bonding process, such that the edges of the second control element <NUM> are entirely aligned within the recessed region <NUM>. Furthermore, in some implementations, a total surface area of the second control element <NUM> facing the first chip (which includes the superconducting qubit) is less than a total surface area of the recessed region <NUM> facing the second chip that includes the second control element <NUM>. For example, as shown in <FIG>, the pad element <NUM> has a rectangular shape with a length <NUM> and a width <NUM> that defines the total surface area of the pad element <NUM>. As shown in <FIG>, In the present example, the recessed region <NUM> has a rectangular shape with a length <NUM> and a width <NUM> that defines the total surface area of the recessed region <NUM>. Other shapes may be used instead for the pad element <NUM> and the recessed region <NUM>. By providing a second control element <NUM> with a total surface area facing the first chip that is less than a total surface area of the recessed region facing the second chip, it is possible to reduce the stray coupling that may occur due to misalignment.

<FIG> is a schematic illustrating a top-view of an exemplary stacked quantum computing device having a first chip (such as chip <NUM> in <FIG>) bonded to a second chip (such as chip <NUM> in <FIG>). The view is obtained through the first chip, where the superconducting material of the first chip is depicted as transparent. As shown in <FIG>, an Xmon qubit <NUM> is provided on the first chip and includes a readout region <NUM>, a SQUID region <NUM>, and a control region <NUM> of the superconducting qubit <NUM>. A recessed region <NUM> is formed within an edge of the ground plane that faces the control region <NUM>. A readout device <NUM> of the second chip is aligned with the readout region <NUM> of the first chip. For example, a portion of a pad element <NUM> (e.g., pad element <NUM>) of the readout device <NUM> is aligned under the readout region <NUM>. Additionally, a loop portion <NUM> (e.g. inner loop <NUM>) of a bias coil <NUM> of a first control element <NUM> (e.g., first control element <NUM>) is aligned within an inner ring area (e.g., inner ring area <NUM>) of the SQUID region <NUM>. Furthermore, a second control element <NUM> (e.g., control element <NUM>) is aligned within the recessed region <NUM> such that an edge of the control element is aligned within the recessed region and displaced from the qubit.

A superconducting (alternatively superconductor) material can be understood as material that exhibits superconducting properties at or below a superconducting critical temperature. Examples of superconducting material include aluminum (superconducting critical temperature of <NUM> kelvin) and niobium (superconducting critical temperature of <NUM> kelvin). The superconductor material used to form the devices disclosed herein may have thicknesses in the range of, e.g., about <NUM> to about <NUM>.

An example of a superconductor material that can be used in the formation of quantum computing circuit elements is aluminum. Aluminum may be used in combination with a dielectric to establish Josephson junctions, which are a common component of quantum computing circuit elements. Examples of quantum computing circuit elements that may be formed with aluminum include circuit elements such as superconductor co-planar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), inductors, capacitors, transmission lines, ground planes, among others.

For certain circuit elements disclosed herein, such as Josephson junctions, it may be necessary to introduce one or more layers of dielectric material. Such dielectric material layers can be formed to have a thickness in the range of, e.g., about <NUM> and about <NUM>.

Processes described herein may entail the deposition of one or more materials, such as superconductors, dielectrics and/or metals. Depending on the selected material, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. Processes described herein may also entail the removal of one or more materials from a device during fabrication. Depending on the material to be removed, the removal process may include, e.g., wet etching techniques, dry etching techniques, or lift-off processes.

Implementations of the quantum subject matter and quantum operations described in this specification may be implemented in suitable quantum circuitry or, more generally, quantum computational systems, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term "quantum computational systems" may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, e.g., a system that defines the unit of quantum information. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Quantum circuit elements (e.g., quantum computing circuit elements) include circuit elements used to perform quantum processing operations. That is, the quantum circuit elements may be configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a nondeterministic manner. Certain quantum circuit elements, such as qubits, may be configured to represent and operate on information in more than one state simultaneously. Examples of superconductor quantum circuit elements that may be formed with the processes disclosed herein include circuit elements such as co-planar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), inductors, capacitors, transmission lines, ground planes, among others.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements may be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements may be used to transmit data to and/or receive data from the quantum computing circuit elements through electrical or electromagnetic connections. Examples of classical circuit elements that may be formed with the processes disclosed herein include rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors. Other classical circuit elements may be formed with the processes disclosed herein as well.

Claim 1:
A device comprising:
a first chip (<NUM>) comprising a superconducting qubit (<NUM>), and a superconductor ground plane (<NUM>), the qubit comprising a superconducting quantum interference device, SQUID region (<NUM>), a control region (<NUM>), and a readout region (<NUM>); and
a second chip (<NUM>) bonded to the first chip, the second chip comprising a first control element (<NUM>), a second control element (<NUM>), and a readout device (<NUM>),
wherein the readout device comprises a resonator element (<NUM>) electrically coupled to a pad element (<NUM>), wherein the pad element is arranged to electromagnetically couple to a portion of the readout region, wherein the qubit is located directly beneath the pad element and the resonator element is laterally displaced so it does not directly overlap the qubit,
wherein the first control element is aligned directly over the SQUID region to electromagnetically couple to the SQUID region, and
wherein the second control element is aligned directly over a recessed region (<NUM>) within the ground plane (<NUM>) and does not overlap the control region, wherein the second control element is arranged to electromagnetically couple to the qubit through the control region, and
wherein the recessed region includes an absence of superconductor material in the ground plane and is laterally displaced from and adjacent to the control region.