Patent Description:
Leadless semiconductor die packages have several advantages over packages having leads extending beyond a perimeter of the package. Such semiconductor die packages may have a low profile as compared to other types of semiconductor die packages. Such semiconductor die packages may take up less space and thereby have a smaller "footprint" on a printed circuit board than conventional packages having leads extending beyond the perimeter of the semiconductor die packages. Such leadless semiconductor die packages may also have better thermal performance as compared to packages having leads extending beyond the perimeter of the package.

An issue within the relevant industry as it concerns QFN and DFN packages relates to the inspection of the solder connections to the leads of the packages. In order to ensure proper solder connections to QFN and DFN packages, it is necessary to inspect the connections. These inspections can be performed by x-ray, for example, or by automated optical inspection (AOI). Automated optical inspection (AOI) systems are used to inspect, for example, semiconductor devices and printed circuit boards (PCBs), for defects. QFN and DFN packages can allow for AOI, which is less costly than x-ray inspections, if the leads are oriented in such a manner that the portions of the sides or "flanks" of the leads are wettable by solder, such as by having solder wick up the sides or sidewalls of the exposed leads.

Conventional lead wettable devices may be formed by processes which require one or more cuts prior to plating one or more surfaces to create wettable flanks. Such cuts may require additional equipment or may require a greater number of steps to create the wettable flanks.

For example, a method for manufacturing a plurality of leadless semiconductor packages is disclosed in <CIT>. Further, <CIT> describes a mechanism by which optically-inspectable features formed during surface mount bonding of no-lead packages are enhanced and <CIT> discloses a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe as well as methods of manufacturing the same.

There is therefore the need for an efficient method of manufacturing a semiconductor die packages having wettable flanks.

The invention is defined by independent claims <NUM> and <NUM>.

In an aspect of the present invention, a method for fabricating lead wettable surfaces is disclosed. The method includes providing a lead frame including a plurality of lead sets, each lead set including a die lead and bond lead having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. The method further includes applying a mold chase to the plating surface of each of the die leads and the bond leads, the mold chase contacting the plurality of lead sets, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The method further includes partially embedding the lead frame assembly in a mold encapsulation such that portions of the mold encapsulation contact the peak surface of each of the mold chase extensions. The method further includes removing the mold chase to expose the vias, each via comprising a first lead sidewall of the die lead of each lead set and the second lead sidewall of the bond lead of each lead set and plating the plating surface of each of the die leads and the bond leads and plating the first lead sidewall and the second lead sidewall with an electrical plating.

In an aspect of the present invention, a device is disclosed that includes a lead frame including a plurality of lead sets, each lead set including a die lead and bond lead having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. The device also includes a mold chase on the plating surface of each of the die leads and the bond leads, the mold chase contacting the plurality of lead sets, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface and a mold encapsulation comprising portions of the mold encapsulation that contact the peak surface of each of the mold chase extensions.

Certain terminology is used in the following description for convenience only and is not limiting. The words "right," "left," "top," and "bottom" designate directions in the drawings to which reference is made. However, it will be understood that such orientation-based terms are for reference only and that the embodiments may be implemented in different directions such that such terms may be applied as adjusted based on such respective different directions. The words "a" and "one," as used in the claims and in the corresponding portions of the specification, are defined as including one or more of the referenced item unless specifically stated otherwise. This terminology includes the words above specifically mentioned, derivatives thereof, and words of similar import. The phrase "at least one" followed by a list of two or more items, such as "A, B, or C," means any individual one of A, B or C as well as any combination thereof.

The description provided herein is to enable those skilled in the art to make and use the described embodiments set forth.

Techniques are disclosed herein for forming bottom and sidewall wettable flanks on semiconductor die packages, and, preferably, DFN semiconductor die packages. The techniques include a package assembly having multiple non-singulated semiconductor die packages. The package assembly includes a lead frame having dies and other internal package components (e.g., wire bonds) coupled thereto. The dies and other components form different regions of non-singulated semiconductor die packages, as further disclosed herein. The lead frame provides a continuous electrical connection between one end of the package assembly and the other, and between the various exposed leads and die paddles of the semiconductor die packages. Elements such as wire bonds or tie bars may assist with forming the electrical connection. This electrical connection may be used for current flow during electroplating, which may be a step that occurs in the process for forming bottom and sidewall wettable flanks on DFN.

<FIG> shows a flow diagram of a process <NUM> for forming a semiconductor die packages from a package assembly, according to an aspect of the present invention. The process <NUM> of <FIG> is discussed in conjunction with <FIG>, which illustrate stages of a package assembly <NUM> as the process <NUM> proceeds. A lead frame <NUM>, as referenced herein, may be cut from a lead frame material such as a sheet of copper. A lead frame assembly, as referenced herein, may be the lead frame <NUM> having a plurality of lead sets <NUM> with first lead 22a and second lead 22b. The lead frame assembly may include any metal alloy. The lead sets <NUM> may be etched into portions of the lead frame <NUM>. Although a lead set <NUM> is disclosed to include two leads (i.e., 22a and 22b), it will be understood that a lead set may include a different number of leads greater than one (e.g., <NUM> leads).

The package assembly <NUM> is shown with a top surface <NUM> and a bottom surface <NUM>, as indicated in <FIG>. A lead frame <NUM> includes a plurality of lead sets <NUM>, each lead set including at least a die lead 22a and a bond lead 22b. The lead frame <NUM> includes vias <NUM> between adjacent lead sets <NUM>, as shown in <FIG>. The vias <NUM> may correspond to or otherwise be referred to as spaces, holes, through holes, gaps, voids, or the like. Each via <NUM> may be formed between sidewall <NUM> of bond leads 22b and sidewall <NUM> of die leads 22a of adjacent lead sets <NUM>. Although the vias <NUM> are shown between adjacent lead sets <NUM> in the X direction in <FIG>, it will be understood that vias <NUM> may be provided in a lead frame <NUM> in any applicable direction, such as the Y direction, and the examples shown in <FIG> are not limiting.

At step <NUM>, one or more of the integrated circuit dies <NUM>, which are referred to herein as "dies", for simplicity, are deposited on the die leads 22a of the lead sets <NUM> of the lead frame <NUM>. The lead frame assembly may include multiple lead sets <NUM> integrated into a single part or unit. A plurality of semiconductor die packages may be formed in an array of die packages in the package assembly <NUM>, which are then cut (e.g., singulated) into individual semiconductor die packages, as further disclosed herein. Each semiconductor die package includes a lead set <NUM> including a die lead 22a and a bond lead 22b, a die <NUM> on the die lead 22a, the die <NUM> bonded to the bond lead 22b via a wire <NUM> that connects the die <NUM> to the bond lead 22b. A mold encapsulation <NUM>, as shown in <FIG>, is also part of a semiconductor die package, as further disclosed herein. A singulated semiconductor die package is a semiconductor die package that is separated from one or more other semiconductor die packages in the package assembly, as further described herein.

At step <NUM>, other components, such as wires <NUM>, conductive clips (elements within the semiconductor die package that couple the die(s) to one or more leads), or other elements are deposited to form a plurality of semiconductor die packages. Notably, at step <NUM>, each of a plurality of die <NUM> may be bonded to each corresponding bond lead 22b via a wire <NUM> that connects the die <NUM> to the bond lead 22b, as shown in <FIG>.

<FIG> shows a top view of a package assembly <NUM> with a top surface <NUM>, after step <NUM> of the process <NUM> of <FIG>. As shown in <FIG>, a plurality of lead sets <NUM> are provided as part of a lead frame <NUM>. Each lead set <NUM> includes a die lead 22a and a bond lead 22b. A die <NUM> is deposited on each of the die leads 22a on a die surface 27a (e.g., top surface, as shown in <FIG>). As shown in <FIG>, dies <NUM> are deposited on die leads 22a of a lead sets <NUM> and the dies <NUM> are electrically connected to a bond lead 22b of the same lead set <NUM>. The electrical connection may be implemented using wire <NUM> bonded to a given die <NUM> deposited on a die surface 27a of the die lead 22a of a lead set <NUM>, the given wire <NUM> connecting to a die surface 27a of a bond lead 22b.

<FIG> shows a cross-sectional view of the package assembly <NUM> of <FIG>, after step <NUM> of the process <NUM> of <FIG>. As shown in <FIG>, the plurality of lead sets <NUM> each including a die lead 22a and bond lead 22b are provided as part of a lead frame <NUM>. A plurality of dies <NUM> are deposited onto the die leads 22a of the lead sets <NUM>. The dies <NUM> may be electrically connected to the bond leads 22b of the respective lead sets <NUM>. The electrical connection between the dies <NUM> to respective bond leads 22b may be made using the wires <NUM>, as disclosed in reference to <FIG>.

<FIG> shows a bottom view of the package assembly <NUM> of <FIG>, after step <NUM> of the process <NUM> of <FIG>. As shown in <FIG>, a plurality of lead sets <NUM> may be arranged in an array configuration. <FIG> shows the plating surface 27b (e.g., bottom surface) of the die leads 22a and bond leads 22b of the lead sets <NUM>. As shown, a via <NUM> is provided in the lead frame <NUM> between lead sets <NUM> that are adjacent to each other in an X direction. Although the vias <NUM> are shown between adjacent lead sets <NUM> in the X direction in <FIG>, it will be understood that vias <NUM> may be provided in a lead frame <NUM> in any applicable direction such as the Y direction and that the examples shown in <FIG> are not limiting. As further noted herein, lead sets <NUM> that are adjacent to each other in a Y direction (e.g., top and bottom in <FIG>) may be electrically independent from each other during the semiconductor package fabrication, as disclosed herein.

At step <NUM> of process <NUM> of <FIG> and as shown in <FIG>, a mold chase <NUM> taping may be applied to the bottom surface <NUM> of the package assembly <NUM>. The mold chase <NUM> may include mold chase extensions 31a that extend into the vias <NUM> between the lead sets <NUM>, as further disclosed herein. Further, a mold encapsulation <NUM> is deposited around the lead frame <NUM> and other components of the semiconductor die packages and a portion of the mold encapsulation <NUM> may extend to and terminate at a peak surface 31b of the mold chase extensions 31a. Notably, the mold chase <NUM> is applied to the bottom portion <NUM> of the package assembly <NUM>. The mold chase <NUM> prevents the mold encapsulation <NUM> deposited at step <NUM> from extending past the base of the lead frame <NUM> and a portion of the mold encapsulation <NUM> extends up to and stop at the peak surface 31b of the mold chase extensions 31a.

As shown in <FIG>, the mold chase <NUM> is applied to the bottom surface <NUM> of the package assembly <NUM> and covers the plating surface 27b of the die lead 22a and bond lead 22b of lead sets <NUM> of the package assembly <NUM>. The mold chase <NUM> includes mold chase extensions 31a that extend into the vias <NUM> (shown in <FIG>) of the lead frame <NUM>. The mold chase extensions 31a may extend partially or fully through the vias <NUM>. As shown in <FIG>, the mold chase extensions 31a may extend from a first plane parallel to the plating surface 27b of the lead sets <NUM> to the peak surface 31b of each of the mold chase extensions 31a. The peak surface 31b of each of the mold chase extensions 31a may be parallel to the die surface 27a of the die leads 22a and bond leads 22b of each lead set <NUM>. The mold chase extensions 31a are adjacent to and between the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a of each adjacent lead set <NUM>. As shown in <FIG>, the mold chase extensions 31a may fill in the entire space between sidewalls <NUM> and <NUM>. Notably, the mold chase extensions 31a fill the entire surface between the sidewalls <NUM> and <NUM> such that the mold encapsulation <NUM> does not extend into the vias <NUM> and, therefore, does not cover the sidewalls <NUM> and <NUM>.

According to an embodiment, the mold chase <NUM> is pre-shaped to include mold shape extensions 31a prior to the mold chase <NUM> being applied to the bottom surface <NUM> of the package assembly <NUM>. The mold chase <NUM> may be shaped to include the mold chase extensions 31a through any applicable process such as lithography, etching, annealing, or the like. According to this embodiment, the location of the mold shape extensions 31a may be pre-aligned with the vias <NUM> of the lead frame <NUM>. The mold chase <NUM> may be applied to the bottom surface <NUM> of the package assembly <NUM> and the mold chase extensions 31a may be molded into the vias <NUM> such that they extend into the vias <NUM> up to a peak surface 31b of the mold chase extensions 31a, as shown in <FIG>. According to this embodiment, the material for the mold chase <NUM> may be malleable such that when pressure and/or heat is applied to the mold chase <NUM> while the mold chase <NUM> is on the bottom surface <NUM> of the package assembly <NUM>, the material of the mold chase <NUM> extends into the vias <NUM> to create the mold chase extensions 31a. As shown in <FIG>, the mold chase extensions 31a may be shaped as a convex bulge that is shaped to fill the vias <NUM>.

As shown in <FIG>, at step <NUM> of the process <NUM> of <FIG> dies <NUM> and other components (e.g., wires <NUM>) may be encapsulated within the mold encapsulation <NUM> (also referred to as a "molding," "mold," "encapsulation," "encapsulation material," "mold encapsulation material", or other similar term herein). The mold encapsulation <NUM> may be non-conductive and may cover all or most of the package components but may not cover the plating surface 27b of the die leads 22a and bond leads 22b of each lead set <NUM> and may also not cover the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a as a result of being blocked from doing so by the mold chase extensions 31a. The mold encapsulation <NUM> may include a top major surface 32a that is opposite to the bottom surface 27b of the die leads 22a and bond leads 22b of each lead set <NUM>. The mold encapsulation <NUM> may have a bottom major surface 32b that is adjacent and substantially parallel to the bottom surface <NUM> of the plurality of the die leads 22a and bond leads 22b of each lead set <NUM> except for the vias <NUM>.

Portions of mold encapsulation <NUM> are shown in <FIG>, though it will be understood that the mold encapsulation <NUM> may cover the lead frame <NUM> and associated components (e.g., dies <NUM> and wires <NUM>), as seen from the cross-sectional view shown in <FIG>. In an embodiment, the mold encapsulation <NUM> may be partially or fully opaque and may be of a given color (e.g., black, grey, etc.) such that the lead frame <NUM> and associated components may not be visible from a top view. However, it will be understood that in the top view, as shown in <FIG>, the mold encapsulation <NUM> is shown as transparent for illustrative purposes, such that the lead frame and associated components are visible in <FIG>. As shown, mold encapsulation <NUM> encapsulates the dies <NUM>, plurality of leads die leads 22a and bond leads 22b of each lead set <NUM> and is provided between the space between die leads 22a and bond leads 22b of each lead set <NUM>.

The mold encapsulation <NUM> may provide a physical and electrical barrier for the components of the package assembly <NUM>. The mold encapsulation <NUM> may be a silica-filled resin, a ceramic, a halide-free material, or other protective encapsulation material, or a combination thereof. The mold encapsulation <NUM> may be formed by molding thermosetting materials in a process where a plastic is softened by heat and pressure in a transfer chamber, then forced at high pressure through suitable sprues, runners, and gates into a closed mold for final curing. The mold encapsulation <NUM> may also be formed by using a liquid which may be heated to form a solid by curing in a UV or ambient atmosphere, or by using a solid that is heated to form a liquid and then cooled to form a solid mold.

According to an embodiment, as shown in <FIG>, prior to the mold chase <NUM> being applied, a film <NUM> may be applied to the plating surface 27b of each of the die leads 22a and bond leads 22b and the film <NUM> may extend into the vias <NUM> such that it covers the sidewalls <NUM> and <NUM>. The film <NUM> may also extend between gaps between die leads 22a and bond leads 22b of each lead set <NUM>, as shown in <FIG>. According to this embodiment, the mold chase <NUM> may be applied to the surface of the film <NUM> that is opposite from the plating surface 27b of the die leads 22a and bond leads 22b of lead sets <NUM>. Accordingly, the mold chase <NUM> may cover the film <NUM> below the plating surface 27b and the mold chase extensions <NUM> may cover the film <NUM> within the vias <NUM>. Alternatively, the film <NUM> may be applied to a pre-shaped mold chase <NUM> prior to the mold chase <NUM> being applied to the bottom surface <NUM> of the package assembly <NUM>.

At step <NUM> of the process <NUM> of <FIG>, the film <NUM> and/or mold chase <NUM> may be removed from the lead frame <NUM>, after step <NUM>, as shown in <FIG>. One or more markings (not shown) may be applied to the lead frame assembly <NUM>. The markings may include one or more fiducial marks which are marks detectable by a machine that allow the machine to align itself for cutting. After step <NUM>, a package assembly <NUM> is provided that includes multiple non-singulated semiconductor die packages with package components (e.g., dies, the lead frame, and the components that couple the dies to the lead frame) encapsulated within a molding material <NUM>. Notably, as shown in <FIG> the plating surface 27b of the die leads 22a and bond leads 22b of each lead set <NUM> are exposed. Further, the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a are be exposed, as shown in <FIG>.

At step <NUM> of the process <NUM> of <FIG>, the plating surface 27b of the plurality of die leads 22a and bond leads 22b of each lead set <NUM> as well as the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a are plated with an electrical plating <NUM> and electrical plating <NUM>, respectively, as shown in <FIG>. As disclosed herein, the plating surface 27b of the plurality of die leads 22a and bond leads 22b of each lead set <NUM> is the surface that is opposite from the surface of the plurality of die leads 22a and bond leads 22b of each lead set <NUM> that is bonded to the wires <NUM> deposited at step <NUM>. Notably, the plating surface 27b and the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a surfaces that are exposed after the removal of the film <NUM> and/or mold chase <NUM>.

The electrical plating <NUM> and electrical plating <NUM> may be the same or may include two different electrical plating materials. The electrical plating <NUM> and electrical plating <NUM> may be applied at the same time or in two different steps. The electrical plating <NUM> and electrical plating <NUM> may be applied by an electroplating process, at step <NUM> of the process <NUM> of <FIG>, as shown in <FIG>. The electrical plating <NUM> and/or electrical plating <NUM> may include one or more layers of a metal, such as tin or a tin alloy, plated on the plating surface 27b of the plurality of die leads 22a and bond leads 22b of each lead set <NUM> (i.e., electrical plating <NUM>) as well as the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a (i.e., electrical plating <NUM>) and may protect the plating surface 27b and sidewalls <NUM> and <NUM> from oxidation. Further, the electrical plating <NUM> and/or electrical plating <NUM> may provide a wettable surface for soldering. Application of the electrical plating <NUM> and/or electrical plating <NUM> in the electroplating process includes depositing a conductive plating material that covers the plating surfaces 27b (e.g., bottom surface) and sidewalls <NUM> and <NUM> and allows for solder to adhere to the plurality of die leads 22a and bond leads 22b of each lead set <NUM> as well as the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a. An electrical plating <NUM> and/or electrical plating <NUM> material is deposited on the exposed plating surfaces 27b and sidewalls <NUM> and <NUM>. During the electroplating process of step <NUM>, the lead frame <NUM> may be dipped in a bath and the lead frame <NUM> may be electrically coupled to the cathode of an electrolytic plating device (not shown). The anode of the electrolytic plating device may be coupled to the plating material, which is also dipped in the bath. An electrical current may be applied to the lead frame which causes the plating material to be deposited on the plating surface 27b of the plurality of die leads 22a and bond leads 22b of each lead set <NUM> as well as the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a so that, for example, the plating surface 27b of the plurality of die leads 22a and bond leads 22b of each lead set <NUM> as well as the sidewalls <NUM> of bond leads 22b and sidewalls <NUM> of die leads 22a are plated with the plating material. The electrical plating <NUM> material may be any of a variety of plating materials, such as tin, gold, palladium, or silver.

At step <NUM> of the process <NUM> of <FIG>, a connecting film <NUM> may be applied to the top major surface 32a of the mold encapsulation <NUM>, as shown in <FIG>. As shown, the connecting film <NUM> may be applied over a plurality of the lead sets <NUM>. The connecting film <NUM> may be any applicable film that attaches to the top major surface 32a of the mold encapsulation <NUM>. The connecting film <NUM> may attach to the top major surface of the mold encapsulation <NUM> using any applicable adhesive material.

At step <NUM> of the process <NUM> of <FIG> a singulation process may be applied, as shown in <FIG>. As shown in <FIG>, the lead frame <NUM> may be singulated into individual semiconductor die packages <NUM> after step <NUM>. The singulation process at step <NUM> may be implemented using an applicable cutting device and/or technique such as a saw having a saw blade, or a laser cutter, a plasma cutter, or a water jet cutter, or any other acceptable cutting device and/or technique as known to those of skill in the art. As further described herein, the singulation process at step <NUM> may include making one or more cuts <NUM> (e.g., 71a and/or 71b). Cuts 71a may extend in an X direction (e.g., from a left side to a right side of the package assembly <NUM> shown in <FIG>), and start from a bottom major surface 32b of the mold encapsulation <NUM> and extend up through the top major surface 32a of the mold encapsulation <NUM>. According to an embodiment, the cuts 71a may also cut through lead connectors <NUM>, as shown in <FIG>. As applied herein, lead connectors <NUM> may connect two adjacent leads and may be part of a lead frame (e.g., lead frame <NUM>) itself or may be formed from one or more other materials. Cuts 71b may be made between adjacent lead sets <NUM> and may extend in the Y direction and be made through the vias <NUM> starting at the bottom surface of the mold encapsulation <NUM> that corresponds the peak surfaces 31b of removed mold chase extensions 31a, and may extend through the top major surface 32a of the mold encapsulation <NUM> to create one or more channels <NUM>. The channels <NUM> may each include the sidewalls <NUM> and <NUM> plated with electrical plating <NUM>, on each side of each of a portion of the channels <NUM>. After the singulation process at step <NUM>, the package assembly <NUM> may be singulated into individual semiconductor die packages <NUM> connected only by the connecting film <NUM>. According to embodiments, a portion of the channels <NUM> that does not correspond to the vias <NUM> is smaller than the vias <NUM> (e.g., the walls of the channels <NUM> have a width that is less than the distance between sidewall <NUM> to sidewall <NUM>).

<FIG> shows a cross-section view of the package assembly <NUM> of <FIG>, during step <NUM> of the process <NUM> of <FIG>. <FIG> shows a series of parallel cuts 71b made in the Y direction to create a plurality of channels <NUM>. Notably, the series of parallel cuts 71b in the Y direction start at the vias <NUM> and extend through the mold encapsulation <NUM>. <FIG> shows the channels <NUM> extending partially into the connecting film <NUM>, though it will be understood that, according to an embodiment, the channels <NUM> may be formed up to, but not through a portion of the connecting film <NUM>. As shown in <FIG>, at least a portion of the connecting film <NUM> is contiguous over the major peak surface 32a of the mold encapsulation <NUM> across multiple lead sets <NUM>.

As shown in the bottom view of <FIG>, the singulation process at step <NUM> may include making a first series of parallel cuts 71a along a first direction (e.g., an X direction) cutting through the bottom major surface 32b of the mold encapsulation <NUM>. The first series of parallel cuts may extend to a depth up to the connecting film <NUM> or a portion of the connecting film <NUM>. Notably, this first series of parallel cuts 71a only cut through lead connectors <NUM> and/or the area between adjacent electrically unconnected lead sets <NUM> (e.g., leads arranged above or below each other if viewing the package assembly <NUM> from a top view, as shown in <FIG> or from a bottom view as shown in <FIG>), and do not cut through the lead sets <NUM>. The singulation process at step <NUM> may further include making a second series of parallel cuts 71b along a second direction (e.g., a Y direction), the second direction substantially perpendicular to the first direction. The second series of parallel cuts 71b may starting from the vias <NUM> and, specifically, from the bottom surface of the mold encapsulation <NUM> that corresponds to the peak surfaces 31b of removed mold chase extensions 31a, and may extend through the top major surface 32a of the mold encapsulation <NUM> to a depth up to the connecting film <NUM> or a portion of the connecting film <NUM> to create channels <NUM>.

The first and second series of parallel cuts 71a and 71b may be made up to a depth that does not extend fully through the connecting film <NUM>, to allow the semiconductor die packages <NUM> to remain as a single package assembly <NUM> during the singulation process at step <NUM>. Notably, the connecting film <NUM> may have properties (e.g., strength, rigidity, elasticity, etc.) that enable the connecting film <NUM> to maintain the plurality of semiconductor die packages <NUM> of the package assembly <NUM>, that are separated by the channels <NUM>, to remain as part of a single unit connected by the connecting film <NUM>. For example, the connecting film <NUM> may enable the semiconductor die packages <NUM> of the package assembly <NUM> plus the plurality of channels <NUM> to have a width, in an X direction, that is substantially equal to the width of the package assembly <NUM> before the singulation at step <NUM> (e.g., the width of the package assembly <NUM> prior to step <NUM>, as shown in <FIG>). The connecting film <NUM> may be made from any applicable material that may or may not conduct electricity.

Alternatively, according to an embodiment, at step <NUM>, instead of taping the top surface <NUM> of the package assembly <NUM> with connecting tape <NUM>, the connecting tape <NUM> may be applied to the bottom surface <NUM> of the package assembly <NUM> (not shown). For example, the singulation process at step <NUM> may include making one or more of the cuts <NUM> (e.g., 71a and/or 71b) from the top major surface 32a of the mold encapsulation <NUM> while the connecting tape <NUM> is applied to the bottom surface <NUM>. According to this embodiment, cuts 71a may extend in an X direction, and start from the top major surface 32a of the mold encapsulation <NUM> and extend down through the mold encapsulation to a bottom major surface 32b of the mold encapsulation <NUM>. According to an embodiment, the cuts 71a may also cut through a portion of the lead frame <NUM> (e.g., if the lead connectors <NUM> are part of the lead frame <NUM>). Cuts 71b may be made between adjacent lead sets <NUM> and may extend in the Y direction and be made through the vias <NUM> starting at the top major surface 32a of the mold encapsulation <NUM> and extend down through the mold encapsulation <NUM> to a bottom surface of the mold encapsulation <NUM> that corresponds to the peak surfaces 31b of removed mold chase extensions 31a, to create one or more channels <NUM>. The channels <NUM> may each include the sidewalls <NUM> and <NUM> plated with electrical plating <NUM>, on each side of each of a portion of the channels <NUM>. According to embodiments, a portion of the channels <NUM> that does not correspond to the vias <NUM> is smaller than the vias <NUM> (e.g., the walls of the channels <NUM> have a width that is less than the distance between sidewall <NUM> to sidewall <NUM>).

At step <NUM> of the process <NUM> of <FIG>, the connecting film <NUM> is removed, as shown in <FIG>. As shown, after removal of the connecting film <NUM> at step <NUM>, only the plurality of semiconductor die packages <NUM>, of package assembly <NUM>, remain. Each of the plurality of semiconductor die packages <NUM> include a lead set <NUM> with a die lead 22a and a bond lead 22b, a die <NUM> bonded to each die lead 22a of each lead set <NUM>, a wire <NUM> electrically connecting the die <NUM> to a corresponding bond lead 22b of each lead set <NUM>. Additionally, each of the plurality of semiconductor die packages <NUM> include electrical plating material (e.g., electrical plating material <NUM>) on the plating surfaces 27b of the die leads 22a and bond leads 22b, and as well as the lead sidewalls <NUM> and <NUM> (e.g., electrical plating material <NUM>) of each lead set <NUM>. The electrical plating material (e.g., <NUM> and/or <NUM>) may serve to mount a given semiconductor die package to a printed circuit board (PCB).

Although a specific number and configuration of leads in lead sets (e.g., die leads 22a and bond leads 22b in lead sets <NUM>) is shown and/or described herein, the techniques of the present disclosure are applicable to assembly packages having any configuration of leads and/or dies.

<FIG> show a DFN package with wettable flanks <NUM> with a first electrical plating material <NUM> on the bottom of two corresponding leads (not shown) as well as a second electrical plating <NUM> on the lead sidewalls (not shown) of the DFN package <NUM>. The first plating material <NUM> and the second plating material <NUM> may be plated in accordance with the process <NUM> of <FIG>, as disclosed herein. Additionally, as shown in <FIG> a tie bar area <NUM> may also be plated (e.g., with second electrical plating <NUM>). The tie bar area <NUM> may assist with, as disclosed herein, forming an electrical connection for current flow during electroplating (e.g., during the first electrical plating <NUM> and/or second electrical plating <NUM>.

<FIG> - for illustrative purposes - show a QFN package <NUM> with a first electrical plating material <NUM> on the bottom of corresponding leads (not shown) as well as a second electrical plating <NUM> on the lead sidewalls (not shown) of the QFN package <NUM>. The first plating material <NUM> and the second plating material <NUM> may be plated in accordance with the process <NUM> of <FIG>, as disclosed herein.

Claim 1:
A method for fabricating lead wettable surfaces, the method comprising:
providing a lead frame (<NUM>) comprising a plurality of lead sets (<NUM>), each lead set (<NUM>) comprising a die lead (22a) and bond lead (22b) having a die surface (27a) and a plating surface (27b), vias (<NUM>) between adjacent lead sets (<NUM>) in a first direction, and an integrated circuit die (<NUM>) arranged on the die surface (27a) of each die lead (22a);
applying a mold chase (<NUM>) to the plating surface (27b) of each of the die leads (22a) and the bond leads (22b), the mold chase (<NUM>) contacting the plurality of lead sets (<NUM>), the mold chase (<NUM>) comprising mold chase extensions (31a) extending into the vias (<NUM>) between each adjacent lead set (<NUM>) in the first direction, each mold chase extension (31a) having a peak surface (31b),
wherein the mold chase extensions (31a) fill in the entire space between the sidewalls (<NUM>, <NUM>) of the vias (<NUM>);
partially embedding the lead frame (<NUM>) assembly in a mold encapsulation (<NUM>) such that portions of the mold encapsulation (<NUM>) contact the peak surface (31b) of each of the mold chase extensions (31a);
removing the mold chase (<NUM>) to expose the vias (<NUM>), each via (<NUM>) comprising a first lead sidewall (<NUM>) of the die lead (22a) of each lead set (<NUM>) and the second lead sidewall (<NUM>) of the bond lead (22b) of each lead set (<NUM>); and
plating the plating surface (27b) of each of the die leads (22a) and the bond leads (22b) and plating the first lead sidewall (<NUM>) and the second lead sidewall (<NUM>) with an electrical plating (<NUM>).