Patent Description:
Prior art documents <CIT>, <CIT>, <CIT>, and <CIT> teach open-circuit detectors.

According to the invention, there is provided an open-circuit detector, comprising: a first current source configured to inject a current at an output of a closed-loop circuit; a detector configured to monitor a voltage of the closed-loop circuit; wherein the detector is configured to indicate whether the voltage monitored exceeds a predetermined threshold voltage; a controller configured to regulate the current injected by the first current source; wherein the controller is configured to set an open-circuit flag if the current injected caused the voltage to exceed the predetermined threshold voltage. The controller causes the first current source to inject the current while the closed-loop circuit is operating.

In an example embodiment, the controller is configured to set the open-circuit flag if the voltage exceeded the predetermined threshold voltage within a predetermined time after the current was injected.

In another example embodiment, the voltage monitored by the detector is at a regulated output of the closed-loop circuit.

In another example embodiment, the voltage monitored by the detector is at a node internal to the closed-loop circuit.

In another example embodiment, the controller is configured to cause the first current source to inject the current at multiple intervals after the closed-loop circuit starts operating and before the closed-loop circuit stops operating.

In another example embodiment, the controller is configured to adjust an amplitude or duration of the current injected by the first current source based on a load current drawn at the output of the closed-loop circuit.

In another example embodiment, further comprising a current drain coupled between the output and a ground; wherein the controller is configured to adjust an amount of a current drained by the current drain based on a discharge time of an external load capacitor coupled to the output.

In another example embodiment, the output of the closed-loop circuit is configured to be coupled an external capacitor configured to keep the output voltage within a predetermined ripple voltage range; and the current injected by the current source does not cause the output voltage to exceed the predetermined ripple voltage range.

In another example embodiment, the closed-loop circuit is a voltage regulator including an output driver and a compensation capacitor; the compensation capacitor is coupled to a gate of the output driver; further comprising a second current source coupled in parallel with the first current source; wherein the controller is configured to adjust a duration or amplitude of the current injected by the second current source based on a value of the compensation capacitor.

In another example embodiment, the closed-loop circuit is a voltage regulator.

In another example embodiment, the voltage regulator is a low drop out (LDO) regulator.

In another example embodiment, the current is a pull up current injected at an output lead of the voltage regulator.

In another example embodiment, the open-circuit detector is embedded within an integrated circuit.

In another example embodiment, the detector is coupled to monitor the voltage at an output pin of a chip package.

In another example embodiment, the detector is coupled to monitor the voltage at a wire bond between an integrated circuit die and a lead-frame within a chip package.

In another example embodiment, the voltage monitored by the detector is at an output of an operational amplifier internal to the closed-loop circuit.

The above discussion is not intended to represent every example embodiment or every implementation within the scope of the invention as claimed. The Figures and Detailed Description that follow also exemplify various example embodiments.

Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings.

It should be understood, however, that other embodiments, beyond the particular embodiments described, are possible as well. All modifications, equivalents, and alternative embodiments falling within the scope of the appended claims are covered as well.

Open-circuit detection within integrated circuit dies, chip packages, and between a chip package and a circuit board is often necessary for a safe shut-down of a circuit or to place a larger system into a safe-mode.

Discussed herein are various example embodiments of an open-circuit detector configured to detect various pin-lift conditions in a monitored circuit. Such circuits may include closed-loop circuits, such as voltage regulators, LDO (low drop out) regulators, PMICs (Power Management Integrated Circuits), etc., as well as other circuits. In some example embodiments, the open-circuit detector is used to detect a pin-lift condition of a closed-loop circuit having a weak pull down.

Pin-lift is herein defined as anything that would interfere with continuity (e.g. broken wire, broken wire-bond, broken integrated circuit trace, solder break, un-plugging a device, etc.), either internal to an integrated circuit, internal to a chip package, on a printed circuit board (PCB), or within an electronic system.

Example embodiments of this open-circuit detector use a current source to inject a fixed current into the monitored circuit and a detection circuit to monitor one or more nodes in the circuit. In some example embodiments, the current is injected periodically by a controller (e.g. state machine) and continuous monitoring is done to check for any pin-lift conditions during operation, at power up, at power down, under load, and under no load.

The voltage developed on the output pin during the current injection is monitored by a detector circuit. If a pin-lift condition is present, the injected current will quickly pull up the pin causing the comparator to trip and flag an overvoltage at the pin. If conditions are normal, the injected current is absorbed by the load (on the pin) and no overvoltage condition is generated.

The open-circuit detector is designed to be added onto existing voltage regulators (e.g. LDOs) and does not require any changes to the functional or parametric requirements of the voltage regulators to work. No additional pin is required for this open-circuit detector.

<FIG> represents a first example <NUM> of an open-circuit detector. The example <NUM> shows internal circuits <NUM> (e.g. IC, chip, die, etc.) and external circuits <NUM> (e.g. PCB, load, etc.).

The internal circuits <NUM> include a closed-loop circuit <NUM> and the open-circuit detector which includes a first current source <NUM>, a detector <NUM>, and a controller <NUM> (e.g. digital state-machine). The external circuits <NUM> in this example include an external output capacitor (Cout) and a load current (Iload). For example embodiments where the closed-loop circuit <NUM> is a voltage regulator (e.g. LDO), the external output capacitor supports fast transient loads as well as provides DC stability for the voltage regulator.

The open-circuit detector works by the controller <NUM> closing switch S1 and thereby injecting a current Ipu periodically at an output pin <NUM> of the closed-loop circuit <NUM> (e.g. voltage regulator). Ipu is periodically injected by the controller <NUM> digitally controlling the switch S1.

The detector <NUM> monitors a voltage at the output pin <NUM>, and compares the voltage to a predetermined threshold voltage, which if exceeded during the Ipu current injection, sets the OV flag <NUM>.

In various example embodiments, the closed-loop circuit <NUM> can be any linear regulator (PMOS or NMOS) with the ability to source current from the supply Vin_ldo. The supply voltages Vin_op_amp and Vin_ldo may or may not be the same depending on the architecture of the closed-loop circuit <NUM> and this has no effect on the working of the open-circuit detector.

For example voltage regulator embodiments, Vin_cs is a voltage that is greater than the regulated output voltage of the voltage regulator. Vin_cs can be connected to a highest supply on this chip, or it can be connected to Vin_ldo. If Vin_ldo is shorted to Vin_cs the headroom requirement of current source Ipu becomes smaller. If Vin_cs is connected to a higher supply voltage, high voltage devices may be required which occupies more circuit area for the same current density.

S1 is a switch with low Rdson digitally controlled by the controller <NUM>. A timing (Tperiod) of this control is dictated by the acceptable ripple allowed on Cout and the sampling time (Ton) of the failure detection. For example for an allowed a 5mV ripple for a <NUM>. 3V/5V output with a pin-lift failure being detected within <NUM> can use a Ton of <NUM> and Tperiod of <NUM>.

The open-circuit detector has at least two operating modes (e.g. a normal, no-fault mode and a pin-lift, fault mode.

In normal, no-fault operation of the voltage regulator, the injected current Ipu will either be absorbed by the load (Iload) or integrated over the external capacitor (Cout) depending on the value of the load. For light load conditions, the periodically injected current Ipu causes an output ripple on the output voltage of the external capacitor. This ripple is relatively small and within the acceptable accuracy of the voltage regulator.

However, during pin-lift, fault operation, the external capacitor (Cout) and load (Iload) are disconnected. The periodically injected current Ipu instantly pulls up the voltage regulator's output. This overvoltage is detected to produce an OV flag <NUM> to notify the controller <NUM> that a fault has occurred. While the <FIG> example shows the OV flag <NUM> being set by detecting a overvoltage at the output pin <NUM>, in other example embodiments a different voltage internal to the closed-loop circuit <NUM> may instead be monitored.

<FIG> represents an example no-fault timing diagram <NUM> of the first example <NUM> open-circuit detector. Shown is the switch S1 state having a Tperiod and Ton time when current is injected at the output pin <NUM>. The Cout voltage is monitored by the detector <NUM> and is the same as the voltage at the output pin <NUM>. An "acceptable ripple" is also shown based on an application that will not violate the application's design rules.

V1 is the predetermined threshold voltage, which if exceeded during the Ton current injection, sets the OV flag <NUM>. During normal mode, the value of V1 is given by Vout + ((Ipu/Cout)*Ton). This calculation assumes an external load current (Iload) of 0A, which is a worst case scenario when the acceptable voltage ripple design specification is considered. If the external load current is sufficiently larger than Ipu, Ipu will be absorbed by the load and the ripple becomes even smaller than V1.

Tdis_chg is determined by Ileakage. Ileakage models internal resistor dividers and/or other current leakage paths that are connected to the output of closed-loop circuit <NUM>. These resistors may provide the following functions including but not limited to output voltage detection, feedback for stability, sampling the output voltage for an ADC.

<FIG> represents an example fault state <NUM> detectable by the first example <NUM> open-circuit detector. The circuit in this example fault state <NUM> is the same as for example <NUM> except for an open-circuit (e.g. Pin Lift) event <NUM>.

<FIG> represents a first example fault timing diagram <NUM> of the first open-circuit detector. When the pin-lift event <NUM> occurs (see <FIG>), capacitor Cout is disconnected from the closed-loop circuit <NUM> output. Thus, when switch S1 is closed by the controller <NUM> then the current Ipu pulls the output voltage of the closed-loop circuit <NUM> higher than the overvoltage detection threshold after the pin-lift event <NUM> occurs. This overvoltage condition is detected by the detector <NUM> which then sets the OV flag <NUM> (e.g. indicator) after a digital filter. In this example embodiment, Ipu is sufficiently large to overcome the leakage current Ileakage. Note that Cout voltage decays over time due to the external load or other leakage.

<FIG> represents a second example <NUM> of the open-circuit detector. The second example <NUM> is substantially same as the first example <NUM> except for the addition of a current drain <NUM>. The closed-loop circuit <NUM>, first current source <NUM>, detector <NUM>, and controller <NUM> are still present in the second example <NUM> but are not labeled here to increase clarity.

The second example <NUM> of the open-circuit detector is applicable to example embodiments where the closed-loop circuit's <NUM> value of Tdis_chg (see <FIG>) is larger than Toff (i.e. time during Tperiod not including Ton). In such example embodiments capacitor Cout is not be sufficiently discharged before the next current pulse is injected. This is occurs if Ileakage is relatively small.

To assist with the discharge, the current drain <NUM>, having a drain current Ipd and a switch S2, is added to provided to more quickly discharge Cout. The switch S2 is also controlled by the controller <NUM>.

<FIG> represents a second example fault timing diagram <NUM> of the first example <NUM> open-circuit detector. Linear voltage regulators for loop stability are often compensated with an internal capacitor (Ccomp) connected to a gate of the regulators output driver (as shown in <FIG>). The value of the internal capacitor Ccomp is usually smaller than Cout by <NUM> to <NUM> orders of magnitude.

However, during an open-circuit (e.g. Pin Lift) event <NUM>, the compensation capacitor (Ccomp) in the closed-loop circuit <NUM> may need to be charged up by current source Ipu. If the current Ipu if is not large enough, the compensation capacitor (Ccomp) will take longer to charge and the closed-loop circuit <NUM> output voltage may not trigger an overvoltage flag within Ton as shown in <FIG>. If Ipu is simply increased to charge the internal compensation capacitor (Ccomp) faster during a fault mode, design constraints on the acceptable ripple (see <FIG>) during normal mode may be violated. <FIG> shows an example solution to this concern.

<FIG> represents a third example <NUM> of the open-circuit detector. The third example <NUM> is substantially same as the first example <NUM> except for the addition of a second current source <NUM> (Icomp) and identification of an output driver <NUM>. The closed-loop circuit <NUM>, first current source <NUM>, detector <NUM>, and controller <NUM> are still present in the third example <NUM> but are not labeled here to increase clarity. The second current source <NUM> (Icomp) is activated by a third switch S3 by the controller <NUM> to overcome this issue, and is switched in parallel with the first current source <NUM>, having the current (Ipu) and the switch (S1), to charge the compensation capacitor (Ccomp) faster for at least a part of the Ton time.

<FIG> represents a first example timing diagram <NUM> of the third example <NUM> open-circuit detector. The first example timing diagram <NUM> shows various waveforms for the third example <NUM> open-circuit detector, including showing an OV (over voltage) duration with auxiliary current injection by the second current source <NUM> (Icomp).

<FIG> represents a second example timing diagram <NUM> of the third example <NUM> open-circuit detector. The second example timing diagram <NUM> shows various waveforms for the third example <NUM> open-circuit detector, including showing an OV (over voltage) duration without auxiliary current injection by the second current source <NUM> (Icomp).

<FIG> represents a fourth example <NUM> of the open-circuit detector. The fourth example <NUM> is an example implemented version of the first example <NUM> of the open-circuit detector. This example implemented version is configured to detect both an overvoltage and an undervoltage at Vout. Ileakage is modelled as resistors R1-<NUM> and R3-<NUM>.

<FIG> represents a fifth example <NUM> of the open-circuit detector. The fifth example <NUM> of the open-circuit detector includes a closed-loop circuit <NUM>, and an open-circuit detector. The open-circuit detector includes a current source <NUM>, a detector <NUM>, and a controller <NUM>. The detector <NUM> monitors a voltage at an output pin <NUM>, and compares the voltage to a predetermined threshold voltage, which if exceeded during the Ipu current injection by the current source <NUM>, sets an OV flag <NUM>.

An op-amp present in the closed-loop circuit <NUM> (e.g. linear voltage regulator) can be used as a comparator to detect a pin-lift event. When a pin-lift occurs, a gate of the linear regulator begins to turn an output FET of the closed-loop circuit <NUM> off. The gate voltage is monitored to set the OV flag <NUM> (e.g. indicator).

Transistor M1 is a PMOS with its gate tied to the gate of the output FET of the closed-loop circuit <NUM>. The sources of M1 and the output FET are also shorted together. M1 is biased using a current source Ibias. M1 and current source Ibias essential form an internal comparator.

During a pin-lift event, the gate is pulled down, turning M1 ON and pulling its drain up. A level shifter in the detector <NUM> is used to level shift this voltage to the digital supply before the flag is sent to the controller <NUM>.

An advantage of the fifth example <NUM> of the open-circuit detector is a conventional two input comparator is not required. However, a speed of detection depends on the gm, bias currents and internal compensation capacitors within the closed-loop circuit <NUM>.

Various instructions and/or operational steps discussed in the above Figures can be executed in any order, unless a specific order is explicitly stated. Also, those skilled in the art will recognize that while some example sets of instructions/steps have been discussed, the material in this specification can be combined in a variety of ways to yield other examples as well, and are to be understood within a context provided by this detailed description.

In some example embodiments these instructions/steps are implemented as functional and software instructions. In other embodiments, the instructions can be implemented either using logic gates, application specific chips, firmware, as well as other hardware forms.

When the instructions are embodied as a set of executable instructions in a non-transitory computer-readable or computer-usable media which are effected on a computer or machine programmed with and controlled by said executable instructions. Said instructions are loaded for execution on a processor (such as one or more CPUs). Said processor includes microprocessors, microcontrollers, processor modules or subsystems (including one or more microprocessors or microcontrollers), or other control or computing devices. Said computer-readable or computer-usable storage medium or media is (are) considered to be part of an article (or article of manufacture). The non-transitory machine or computer-usable media or mediums as defined herein excludes signals, but such media or mediums may be capable of receiving and processing information from signals and/or other transitory mediums.

Thus, the detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning of the claims are to be embraced within their scope.

Claim 1:
An open-circuit detector, comprising:
a first current source (<NUM>) configured to inject a current at an output of a closed-loop circuit (<NUM>)
a detector (<NUM>) configured to monitor a voltage of the closed-loop circuit;
wherein the detector is configured to indicate whether the voltage monitored exceeds a predetermined threshold voltage;
a controller (<NUM>) configured to regulate the current injected by the first current source;
wherein the controller is configured to set an open-circuit flag if the current injected caused the voltage to exceed the predetermined threshold voltage;
characterized in that
the controller is configured to cause the first current source to inject the current while the closed-loop circuit is operating.