Patent Description:
A display device is an apparatus visually displaying data. Recently, applications of the display device have become more diversified. Also, as the display devices become thinner and lighter, their range of use has been greatly extended.

To protect a display area from external moisture and impurities, the display area of the display device may be encapsulated with an encapsulation member. Recently, as the demand for slim and flexible display devices increases, a thin-film encapsulation layer including a flexible organic insulating layer and/or a flexible inorganic insulating layer instead of metal or glass has been used as the encapsulation member. However, during a subsequent process after a process of forming the thin-film encapsulation layer as the encapsulation member, a defect may occur in which the thin-film encapsulation layer is exfoliated from a back plane of the display device.

<CIT> discloses an organic light emitting display device comprises a partition wall formed on a bank that covers a portion of an auxiliary electrode. The organic light emitting display device includes a first electrode, an auxiliary electrode, a first bank, and a partition wall. The first electrode may be connected to a driving transistor, and the auxiliary electrode may be disposed on the same layer as the first electrode. The first bank may cover a portion of the first electrode and a portion of the auxiliary electrode. A portion of a bottom surface of the partition wall may contact a top surface of the first bank, and the other portion except the portion of the bottom surface may be disposed on the auxiliary electrode.

<CIT> discloses an organic light emitting display device and a method of manufacturing the same. In the organic light emitting display, an anode connected to a thin film transistor and a bank disposed along the edge of the anode are simultaneously formed through one mask process, and a partition is formed to cover the side surface of the anode, thereby preventing damage to a pad cover electrode by an etching solution or etching gas of the anode without any separate pad protective film.

<CIT> dislcoses an organic light emitting display apparatus and a method of manufacturing the same, which prevent an organic light emitting layer from being peeled from an anode electrode.

<CIT> discloses a display panel and a display device including a first electrode disposed on a substrate, at least one spacer disposed on the bank, the outer edge of the spacer includes a first outer edge portion corresponding to from the bank to a first height above the bank and a second outer edge portion corresponding to a predetermined height from the first height. The first outer edge portion has a second tapering shape, and the second outer edge portion includes a part having a first tapering shape or a part having a convex shape.

Exemplary embodiments of the present disclosure include a display device and a method of manufacturing the same, in which a defect that a thin-film encapsulation layer is exfoliated from a back plane of the display device is reduced. However, it should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for limitation of the present disclosure.

Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the exemplary embodiments of the present disclosure.

According to an aspect, there is provide a display device as set out in claim <NUM>. Additional features are set out in claims <NUM> to <NUM>.

The above and other aspects and features of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:.

Since the drawings in <FIG> are intended for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity purpose.

It will be further understood that the terms "comprises" and/or "comprising" used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

It will be understood that when a layer, region, or component is referred to as being "formed on," another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present.

When a certain exemplary embodiment may be implemented differently, a specific process order may be performed differently from the described order.

It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, it may be "directly connected" to the other layer, region, or component and/or may be "indirectly connected" to the other layer, region, or component with other layer, region, or component interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, it may be "directly electrically connected" to the other layer, region, or component and/or may be "indirectly electrically connected" to the other layer, region, or component with other layer, region, or component interposed therebetween.

A display device according to an exemplary embodiment of the present disclosure is an apparatus displaying an image and may be various ones, for example, a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a field emission display, a surface-conduction electron-emitter display, a plasma display, and a cathode ray display.

Hereinafter, although the display device according to an exemplary embodiment of the present disclosure is described as an organic light-emitting display device as an example, a display device according to embodiments of the present disclosure is not limited thereto and may be various ones.

<FIG> is a plan view of a display device <NUM> according to an exemplary embodiment of the present disclosure, <FIG> and <FIG> are equivalent circuit diagrams of examples of one pixel included in the display device <NUM> according to an exemplary embodiment of the present disclosure, <FIG> is a plan view of region III of <FIG>, and <FIG> is a cross-sectional view of the display device <NUM> taken along line IVA-IVB of <FIG>.

Referring to <FIG>, the display device <NUM> includes a display area DA arranged over a substrate <NUM>. The display area DA includes pixels P connected to a data line DL and a scan line SL, with the data line DL extending in a first direction, and the scan line SL extending in a second direction intersecting with the first direction. Each pixel P may be connected to a driving voltage line PL extending in the first direction. In an exemplary embodiment of the present disclosure, a plurality of pixels may be arranged in a matrix shape, but embodiments of the present disclosure are not limited thereto. For example, the plurality of pixels may be arranged in a pentile matrix shape, or a diamond shape.

One pixel P may emit, for example, red, green, blue, or white light and may include, for example, an organic light-emitting diode. Also, each pixel P may further include an element such as a thin film transistor and a capacitor. The display area DA may provide a predetermined image using light emitted from the pixels P. For example, in the display area DA, a plurality of pixels, for example, an array of pixels, may be arranged, and the predetermined image may be displayed via the array of pixels.

The display device <NUM> may include a non-display area NDA in which the pixels P emitting light are not arranged. The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2, with the first non-display area NDA1 being arranged outside the display area DA and surrounding the display area DA, and the second non-display area NDA2 surrounding an opening area OA that is at least partially surrounded by the display area DA. For example, as shown in <FIG>, the second non-display area NDA2 and the opening area OA are entirely surrounded by the display area DA. However, embodiments of the present disclosure are not limited thereto. For example, in an exemplary embodiment of the present disclosure, a portion of the opening area OA is not surrounded by the display area DA.

A first power voltage line <NUM> and a second power voltage line <NUM> may be arranged in the first non-display area NDA1, with the second power voltage line <NUM> providing a voltage different from a voltage of the first power voltage line <NUM>.

The first power voltage line <NUM> may include a first main voltage line <NUM> and a first connection line <NUM> each arranged on one side of the display area DA. For example, in the case where the display area DA is a rectangle, the first main voltage line <NUM> may be arranged to correspond to one of the sides of the display area DA. The first connection line <NUM> may extend in the first direction from the first main voltage line <NUM>, and may be connected to a first terminal <NUM> of a terminal unit <NUM>.

The second power voltage line <NUM> may include a second main voltage line <NUM> and a second connection line <NUM>, with the second main voltage line <NUM> surrounding two opposite end portions of the first main voltage line <NUM> and partially surrounding the display area DA, and the second connection line <NUM> extending in the first direction from the second main voltage line <NUM>. For example, in the case where the display area DA is a rectangle, the second main voltage line <NUM> may extend along the two opposite end portions of the first main voltage line <NUM> and the rest of the sides of the display area DA excluding one side of the display area DA that neighbors the first main voltage line <NUM>. The second connection line <NUM> extends in the first direction in parallel to the first connection line <NUM> and is connected to a second terminal <NUM> of the terminal unit <NUM>. The second power voltage line <NUM> may be bent to surround the end portions of the first power voltage line <NUM>.

The terminal unit <NUM> is arranged on one end portion of the substrate <NUM> and includes the plurality of terminals, that is, the first, second, and third terminals <NUM>, <NUM>, and <NUM>. The terminal unit <NUM> may be exposed and electrically connected to a controller such as a flexible printed circuit board (FPCB) or a driving driver integrated circuit (IC) chip by not being covered by an insulating layer. In an exemplary embodiment of the present disclosure, the FPCB may be electrically connected to the terminal unit <NUM> located at a side of the display device <NUM> in the first non-display area NDA1. The FPCB may be bent and electrically connected to the display device <NUM>. Accordingly, the FPCB functioning as the controller may output a signal to the display device <NUM> or receive a signal from the display device <NUM> through the terminal unit <NUM>.

The controller may be configured to convert a plurality of image signals transferred from the outside to a plurality of image data signals and transfer the plurality of image data signals to the display area DA through the third terminal <NUM>. Also, the controller may be configured to receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, generate control signals for controlling an operation of first and second gate drivers, and transfer the generated control signals to the first and second gate drivers through terminals. Each of the control signals generated by the controller may include a vertical start signal for controlling the operation of the first and second gate drivers and at least one clock signal for determining the output timing of signals.

The controller may be configured to respectively transfer different voltages to the first power voltage line <NUM> and the second power voltage line <NUM> through the first terminal <NUM> and the second terminal <NUM>.

The first power voltage line <NUM> may provide a first power voltage ELVDD (see <FIG> and <FIG>) to each pixel P, and the second power voltage line <NUM> may provide a second power voltage ELVSS (see <FIG> and <FIG>) to each pixel P.

The first power voltage ELVDD may be provided to each pixel P through the driving voltage line PL connected to the first power voltage line <NUM>. The second power voltage ELVSS may be provided to a cathode of an organic light-emitting diode OLED (see <FIG> and <FIG>) provided to each pixel P. In this case, the second main voltage line <NUM> of the second power voltage line <NUM> may be connected to the cathode of the organic light-emitting diode OLED in the first non-display area NDA1.

A scan driver, a data driver, etc. may be further arranged in the first non-display area NDA1, with the scan driver providing a scan signal to a scan line SL of each pixel, and the data driver providing a data signal to a data line DL of each pixel. The data driver may be located on one edge of the substrate <NUM>, or may be located on the FPCB electrically connected to the terminal unit <NUM> located at a side of the display device <NUM> in the first non-display area NDA1.

A first dam portion <NUM> may be apart from a second dam portion <NUM> in the first non-display area NDA1, with the first and second dam portions <NUM> and <NUM> each surrounding the display area DA.

The first and second dam portions <NUM> and <NUM> may serve as dams blocking an organic material flowing in an edge direction of the substrate <NUM> while forming, by using an inkjet process, an organic encapsulation layer <NUM> (see <FIG> and <FIG>) including the organic material such as a monomer constituting a thin-film encapsulation layer <NUM> (see <FIG>). Therefore, the first and second dam portions <NUM> and <NUM> may prevent an edge tail of the organic encapsulation layer <NUM> from being formed at an edge of the substrate <NUM> (see <FIG>). As shown in <FIG>, the first and second dam portions <NUM> and <NUM> may surround the display area DA.

Referring to <FIG>, each pixel P includes a pixel circuit PC and the organic light-emitting diode OLED connected to the pixel circuit PC, with the pixel circuit PC being connected to the scan line SL and the data line DL. Each of the pixels P may emit, for example, red light, green light, or blue light, or may emit red light, green light, blue light, or white light, via the organic light-emitting diode OLED.

The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 for controlling turn-on and turn-off of the pixel P is configured to transfer a data signal Dm input through the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input through the scan line SL.

The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL and may be configured to store a voltage corresponding to a difference between a voltage transferred from the switching thin film transistor T2 and the first power voltage ELVDD (or a driving voltage) supplied to the driving voltage line PL.

The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst and may be configured to control a driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL, in response to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED may be configured to emit light having a predetermined brightness according to the driving current. The turn-on time of the driving thin film transistor T1 may be determined according to the amount of voltage stored in the storage capacitor Cst. The driving thin film transistor T1 may then provide to the organic light-emitting diode OLED the first power voltage ELVDD transmitted through the driving voltage line PL during the turn-on time.

Although it is shown in <FIG> that the pixel circuit PC includes two thin film transistors and one storage capacitor, embodiments of the present disclosure are not limited thereto. For example, the pixel circuit PC may include three, four, five, six, seven, or more transistors instead of the above two transistors. Also, more than one storage capacitors may be included in the pixel circuit PC.

Referring to <FIG>, the pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, a first emission control thin film transistor T5, a second emission control thin film transistor T6, and a second initialization thin film transistor T7.

Although it is shown in <FIG> that each pixel P includes signal lines SLn, SLn-<NUM>, EL, and DL, an initialization voltage line VL, and the driving voltage line PL, embodiments of the present disclosure are not limited thereto. For example, in an exemplary embodiment of the present disclosure, at least one of the signal lines SLn, SLn-<NUM>, EL, or DL, and/or the initialization voltage line VL may be shared by pixels that neighbor each other.

A drain electrode of the driving thin film transistor T1 may be electrically connected to the anode of the organic light-emitting diode OLED through the second emission control thin film transistor T6. The driving thin film transistor T1 is configured to receive a data signal Dm depending on a switching operation of the switching thin film transistor T2, and to supply the driving current to the organic light-emitting diode OLED.

A gate electrode of the switching thin film transistor T2 is connected to the first scan line SLn, and a source electrode of the switching thin film transistor T2 is connected to the data line DL. A drain electrode of the switching thin film transistor T2 may be connected to a source electrode of the driving thin film transistor T1 and simultaneously connected to the driving voltage line PL through the first emission control thin film transistor T5.

The switching thin film transistor T2 is turned on in response to a first scan signal Sn transferred through the first scan line SLn and is configured to perform a switching operation of transferring a data signal Dm transferred through the data line DL to the source electrode of the driving thin film transistor T1.

A gate electrode of the compensation thin film transistor T3 may be connected to the first scan line SLn. A source electrode of the compensation thin film transistor T3 may be connected to a drain electrode of the driving thin film transistor T1 and simultaneously connected to a pixel electrode of the organic light-emitting diode OLED through the second emission control thin film transistor T6. A drain electrode of the compensation thin film transistor T3 may be connected to one of the electrodes of the storage capacitor Cst, a source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1, simultaneously. The compensation thin film transistor T3 is turned on in response to a first scan signal Sn transferred through the first scan line SL and is configured to diode-connect the driving thin film transistor T1 by connecting the gate electrode of the driving thin film transistor T1 to the drain electrode of the driving thin film transistor T1.

A gate electrode of the first initialization thin film transistor T4 may be connected to a second scan line SLn-<NUM> (also referred to as a previous scan line). A drain electrode of the first initialization thin film transistor T4 may be connected to the initialization voltage line VL. A source electrode of the first initialization thin film transistor T4 may be connected to one of the electrodes of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1, simultaneously. The first initialization thin film transistor T4 may be turned on in response to a second scan signal Sn-<NUM> transferred through the second scan line SLn-<NUM> and is configured to transfer an initialization voltage VINT to the gate electrode of the driving thin film transistor T1, thereby performing an initialization operation of initializing a voltage of the gate electrode of the driving thin film transistor T1.

A gate electrode of the first emission control thin film transistor T5 may be connected to the emission control line EL. A source electrode of the first emission control thin film transistor T5 may be connected to the driving voltage line PL. A drain electrode of the first emission control thin film transistor T5 is connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

A gate electrode of the second emission control thin film transistor T6 may be connected to the emission control line EL. A source electrode of the second emission control thin film transistor T6 may be connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. A drain electrode of the second emission control thin film transistor T6 may be electrically connected to the pixel electrode of the organic light-emitting diode OLED. The first emission control thin film transistor T5 and the second emission control thin film transistor T6 are simultaneously turned on in response to an emission control signal En received through the emission control line EL, the first power voltage ELVDD is transferred to the organic light-emitting diode OLED, and the driving current flows through the organic light-emitting diode OLED.

A gate electrode of the second initialization thin film transistor T7 may be connected to the second scan line SLn-<NUM>. A source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the organic light-emitting diode OLED. A drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on in response to a second scan signal Sn-<NUM> transferred through the second scan line SLn-<NUM> to initialize the pixel electrode of the organic light-emitting diode OLED.

Although it is shown in <FIG> that the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the second scan line SLn-<NUM>, embodiments of the present disclosure are not limited thereto. For example, in an exemplary embodiment of the present disclosure, the first initialization thin film transistor T4 may be connected to the second scan line SLn-<NUM>, which is the previous scan line, and driven in response to a second scan signal Sn-<NUM>, and the second initialization thin film transistor T7 may be connected to a separate signal line (for example, the next scan line) and driven in response to a signal transferred through the separate signal line.

One of the electrodes of the storage capacitor Cst may be simultaneously connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4. The other electrode of the storage capacitor Cst may be connected to the driving voltage line PL. In an exemplary embodiment of the present disclosure, an additional capacitor may be formed to cause the potential on the gate electrode of the driving thin film transistor T1 to increase to a predetermined level by the voltage of the first scan signal Sn. One end of the additional capacitor may be connected to the first scan line SLn, and the other end of the additional capacitor may be connected to the drain electrode of the compensation thin film transistor T3 and the gate electrode of the driving thin film transistor T1.

An opposite electrode (e.g. a cathode) of the organic light-emitting diode OLED is configured to receive the second power voltage ELVSS (or a common power voltage). The organic light-emitting diode OLED receives the driving current from the driving thin film transistor T1, and emits light to display an image.

The pixel circuit PC is not limited to the number of thin film transistors, the number of capacitors, and the circuit design described with reference to <FIG> and <FIG>. The number of thin film transistors, the number of capacitors, and the circuit design may be variously changed in embodiments.

Referring to <FIG>, a plurality of pixels P are arranged in region III of <FIG>. The plurality of pixels P are surrounded by a pixel-defining layer <NUM>, and a first spacer <NUM>-<NUM> is arranged on the pixel-defining layer <NUM>. A plurality of first holes TH1 are arranged between the pixels P, with the plurality of first holes TH1 passing through an insulating layer.

Althought it is shown in <FIG> that the pixels P have a quadrangular shape of a same size, this is provided as an example, and embodiments of the present disclosure are not limited thereto. For example, the size, the shape, and the arrangement of the pixels P may be changed.

The first spacer <NUM>-<NUM> may be arranged between some pixels P among the plurality of pixels P. During a process of depositing an intermediate layer <NUM> (see <FIG>) including an emission layer by using a mask, the first spacer <NUM>-<NUM> maintains a separation between the mask and the substrate <NUM> to prevent the intermediate layer <NUM> from being chopped or torn by the mask during the deposition process.

The first spacer <NUM>-<NUM> may include a material the same as that of the pixel-defining layer <NUM>. While the pixel-defining layer <NUM> is formed by using a half-tone mask, the first spacer <NUM>-<NUM> may be simultaneously formed with the pixel-defining layer <NUM> at a height different from the height of the pixel-defining layer <NUM> by using a material the same as that of the pixel-defining layer <NUM>.

The first hole TH1 may be arranged between some pixels P among the plurality of pixels P, and may include a predetermined opening space passing through a portion of the first spacer <NUM>-<NUM> and a portion of the pixel-defining layer <NUM> to fix the thin-film encapsulation layer <NUM> described below to a back plane. The back plane may be a structure of the display device <NUM> right before the thin-film encapsulation layer <NUM> is formed. For example, the first hole TH1 may serve as an anchor and thus may increase contact strength between the thin-film encapsulation layer <NUM> and the back plane.

Referring to <FIG>, a buffer layer <NUM> is arranged on the substrate <NUM>. The driving thin film transistor T1, the switching thin film transistor T2, and the storage capacitor Cst are arranged on the buffer layer <NUM>.

The substrate <NUM> may include various materials such as, for example, glass, metal, or plastic. For example, the substrate <NUM> may include a flexible substrate including a polymer resin such as, for example, polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAr), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

The buffer layer <NUM> may be provided on the substrate <NUM>, and may include an inorganic insulating (insulative) material such as, for example, silicon oxide (SiOx), silicon oxynitride (SiON), and/or silicon nitride (SiNx), and may be formed to prevent the penetration of impurities. The buffer layer <NUM> may be a single layer or multiple layers including the inorganic insulating material.

The driving thin film transistor T1 includes a driving semiconductor layer A1 and a driving gate electrode G1, and the switching thin film transistor T2 includes a switching semiconductor layer A2 and a switching gate electrode G2. A first gate insulating layer <NUM> is arranged between the driving semiconductor layer A1 and the driving gate electrode G1 and between the switching semiconductor layer A2 and the switching gate electrode G2. The first gate insulating layer <NUM> may include an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al<NUM>O<NUM>), titanium oxide (TiO<NUM>), tantalum oxide (Ta<NUM>O<NUM>), lanthanum oxide (La<NUM>O<NUM>), zirconium oxide (ZrO<NUM>), hafnium oxide (HfO<NUM>), etc. The first gate insulating layer <NUM> may be a single layer or a multi-layer including the aforementioned materials.

The driving semiconductor layer A1 and the switching semiconductor layer A2 may include amorphous silicon (a-Si) or polycrystalline silicon (p-Si). In an exemplary embodiment of the present disclosure, the driving semiconductor layer A1 and the switching semiconductor layer A2 may include an oxide of at least one of, for example, indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), or zinc (Zn).

The driving semiconductor layer A1 may include a driving channel region, a driving source region, and a driving drain region, with the driving channel region overlapping the driving gate electrode G1 and not doped with impurities, and the driving source region and the driving drain region being on two opposite sides of the driving channel region and doped with impurities. For example, the driving source region and the driving drain region may be doped with an n-type dopant or a p-type dopant. A driving source electrode S1 and a driving drain electrode D1 may be respectively connected to the driving source region and the driving drain region.

The switching semiconductor layer A2 may include a switching channel region, a switching source region, and a switching drain region, with the switching channel region overlapping the switching gate electrode G2 and not doped with impurities, and the switching source region and the switching drain region being on two opposite sides of the switching channel region and doped with impurities. For example, the switching source region and the switching drain region may be doped with an n-type dopant or a p-type dopant. A switching source electrode S2 and a switching drain electrode D2 may be respectively connected to the switching source region and the switching drain region.

The driving source electrode S1, the driving drain electrode D1, the switching source electrode S2 and the switching drain electrode D2 may each include a highly conductive material. Each of the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2 and the switching drain electrode D2 may include a conductive material including, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), an alloy thereof, etc., and may be a multi-layer or a single layer including the aforementioned materials. In an exemplary embodiment of the present disclosure, each of the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2 and the switching drain electrode D2 may be formed as a multi-layer of titanium/aluminum/titanium (Ti/Al/Ti).

The driving gate electrode G1 and the switching gate electrode G2 may each include a single layer or a multi-layer including at least one of, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), or an alloy thereof.

In an exemplary embodiment of the present disclosure, the storage capacitor Cst may overlap the driving thin film transistor T1. In this case, the areas of the storage capacitor Cst and the driving thin film transistor T1 may be increased and a high-quality image may be provided. For example, the driving gate electrode G1 may serve as a first storage capacitor plate CE1 of the storage capacitor Cst. A second storage capacitor plate CE2 of the storage capacitor Cst may overlap the first storage capacitor plate CE1 with a second gate insulating layer <NUM> interposed therebetween. The second gate insulating layer <NUM> may include an inorganic insulating material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON). The upper electrode CE2 of the storage capacitor Cst may include a conductive material including, for example, silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), titanium (Ti), an alloy thereof, etc., and may be a multi-layer or a single layer including the aforementioned materials.

The driving thin film transistor T1, the switching thin film transistor T2, and the storage capacitor Cst may be covered by an interlayer insulating layer <NUM>.

The interlayer insulating layer <NUM> may include an inorganic material such as, for example, silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON).

A data line DL is arranged on the interlayer insulating layer <NUM>. The data line DL is connected to the switching semiconductor layer A2 of the switching thin film transistor T2 through a contact hole passing through the interlayer insulating layer <NUM>. The data line DL may serve as the switching source electrode S2.

The driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may be arranged on the interlayer insulating layer <NUM> and may be connected to the driving semiconductor layer A1 or the switching semiconductor layer A2 through contact holes passing through the interlayer insulating layer <NUM>.

The data line DL, the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2, and the switching drain electrode D2 may be covered by an inorganic protective layer.

The inorganic protective layer may include a single layer or a multi-layer including at least one of silicon oxide (SiOx) and silicon nitride (SiNx). The inorganic protective layer may prevent some wirings exposed in the first non-display area NDA1, for example, wirings simultaneously formed during a process the same as a process of forming the data line DL, from being damaged by etchant used while the pixel electrode <NUM> is patterned.

The driving voltage line PL may be arranged on a layer different from a layer on which the data line DL is arranged. In the present specification, when A and B are referred to as being arranged on different layers, at least one insulating layer is arranged between A and B, one of A and B is arranged below the at least one insulating layer, and the other of A and B is arranged over the at least one insulating layer. A first planarization layer <NUM> may be arranged between the driving voltage line PL and the data line DL, and the driving voltage line PL may be covered by a second planarization layer <NUM>.

The driving voltage line PL may include a single layer or a multi-layer including at least one of, for example, aluminum (Al), copper (Cu), titanium (Ti), or an alloy thereof. In an exemplary embodiment of the present disclosure, the driving voltage line PL may include a triple layer of titanium/aluminum/titanium (Ti/Al/Ti).

Although <FIG> shows a configuration in which the driving voltage line PL is arranged on the first planarization layer <NUM>, embodiments of the present disclosure are not limited thereto. For example, in an exemplary embodiment of the present disclosure, the driving voltage line PL may be connected to a lower additional voltage line through a through hole formed in the first planarization layer <NUM> to reduce a resistance, with the lower additional voltage line being arranged on a layer the same as a layer on which the data line DL is arranged.

Each of the first planarization layer <NUM> and the second planarization layer <NUM> may include a single layer or a multi-layer.

The first planarization layer <NUM> and the second planarization layer <NUM> may include an organic insulating material. For example, the organic insulating material may include a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

The first planarization layer <NUM> and the second planarization layer <NUM> may include an inorganic insulating material. For example, the inorganic insulating material may include, for example, silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON).

The organic light-emitting diode OLED may be located on the second planarization layer <NUM>, and may include the pixel electrode <NUM>, an opposite electrode <NUM>, and the intermediate layer <NUM> interposed therebetween, with the intermediate layer <NUM> including an emission layer 320b.

The pixel electrode <NUM> is connected to a connection line CL formed on the first planarization layer <NUM>, and the connection line CL is connected to the driving drain electrode D1 of the driving thin film transistor T1. The connection line CL may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), an alloy thereof, etc., and may be formed as a multi-layer or a single layer including the aforementioned materials. The connection line CL may include a material the same as that included in the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2 and the switching drain electrode D2. For example, the connection line CL may be formed as a multi-layer of titanium/aluminum/titanium (Ti/Al/Ti).

The pixel electrode <NUM> may include a transparent electrode or a reflective electrode.

In the case where the pixel electrode <NUM> includes a transparent electrode, the pixel electrode <NUM> may include a transparent conductive layer. The transparent conductive layer may include at least one of, for example. indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In<NUM>O<NUM>), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In this case, the pixel electrode <NUM> may further include a semi-transmissive layer to improve a light efficiency in addition to the transparent conductive layer, with the semi-transmissive layer including a thin film ranging from several micrometers to tens of micrometers and including at least one of, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or ytterbium (Yb).

In the case where the pixel electrode <NUM> includes a reflective electrode, the pixel electrode <NUM> may include a reflective layer and a transparent conductive layer on and/or under the reflective layer, with the reflective layer including at least one of, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. The transparent conductive layer may include at least one of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In<NUM>O<NUM>), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). However, embodiments of the present disclosure are not limited thereto, and the pixel electrode <NUM> may include various materials and have various structures including a single layer and/or a multi-layer.

The pixel-defining layer <NUM> may be arranged on the pixel electrode <NUM>.

The pixel-defining layer <NUM> defines a pixel P by including a first opening OP1 exposing the pixel electrode <NUM>, and may cover an edge of the pixel electrode <NUM>. Also, the pixel-defining layer <NUM> may prevent an arc from occurring at end portions of the pixel electrode <NUM> by increasing a distance between edges of the pixel electrode <NUM> and the opposite electrode <NUM>. The pixel-defining layer <NUM> may include an organic material such as, for example, polyimide (PI) or hexamethyldisiloxane (HMDSO).

The intermediate layer <NUM> includes the emission layer 320b. The intermediate layer <NUM> includes a first functional layer 320a and/or a second functional layer 320c, with the first functional layer 320a being arranged under the emission layer 320b, and the second functional layer 320c being arranged on the emission layer 320b. The emission layer 320b may include a polymer organic material or a low molecular weight organic material each emitting light having a predetermined color. In an exemplary embodiment of the present disclosure, the emission layer 320b may include at least one of materials emitting red, green, or blue light, and may include a fluorescent material or a phosphorescent material.

The first functional layer 320a may include a single layer or a multi-layer. For example, in the case the first functional layer 320a includes a polymer material, the first functional layer 320a is a hole transport layer (HTL), which has a single-layered structure, and may include poly(<NUM>,<NUM>-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). In the case where the first functional layer 320a includes a low molecular weight material, the first functional layer 320a may include a hole injection layer (HIL) and a hole transport layer (HTL).

The second functional layer 320c may be omitted. For example, in the case where the first functional layer 320a and the emission layer 320b include a polymer material, the second functional layer 320c may be formed. The second functional layer 320c may include a single layer or a multi-layer. The second functional layer 320c may include an electron transport layer (ETL) and/or an electron injection layer (EIL). For example, the intermediate layer <NUM> may include at least one of a hole transport layer (HTL), a hole injection layer (HIL), an electron injection layer (EIL), or an electron transport layer (ETL).

The emission layer 320b of the intermediate layer <NUM> may be arranged for each pixel P in the display area DA. The emission layer 320b may be formed on a portion of the pixel electrode <NUM> that is exposed through the first opening OP1 of the pixel-defining layer <NUM>. The emission layer 320b may be arranged to overlap the first opening OP1 of the pixel-defining layer <NUM> and/or the pixel electrode <NUM>. The first and second functional layers 320a and 320c of the intermediate layer <NUM> may be formed as an integral layer that is common to the plurality of pixel electrodes <NUM>, and accordingly may be formed not only in the display area DA but also in the first non-display area NDA1, while the emission layer 320b is formed only in the display area DA. The intermediate layer <NUM> may be formed by various methods such as vacuum deposition.

The opposite electrode <NUM> may be arranged in the display area DA and may cover the display area DA. That is, the opposite electrode <NUM> may be formed as one body over the plurality of organic light-emitting diodes OLED to correspond to the plurality of pixel electrodes <NUM>. The opposite electrode <NUM> is electrically connected to the second power voltage line <NUM> described below.

The opposite electrode <NUM> may include a transparent electrode or a reflective electrode. In the case where the opposite electrode <NUM> includes a transparent electrode, the opposite electrode <NUM> may include at least one of, for example, silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), calcium (Ca), copper (Cu), lithium fluoride/calcium (LiF/Ca), lithium fluoride/aluminum (LiF/Al), magnesium-silver (MgAg), or calcium-silver (CaAg), and may include a thin film having a thickness ranging from several micrometers to tens of micrometers. Alternatively, the opposite electrode <NUM> may include a thin film having a thickness ranging from several nanometers to hundreds of nanometers.

In the case where the opposite electrode <NUM> includes a reflective electrode, the opposite electrode <NUM> may include at least one of, for example, silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), calcium (Ca), copper (Cu), lithium fluoride/calcium (LiF/Ca), lithium fluoride/aluminum (LiF/Al), magnesium-silver (MgAg), or calcium-silver (CaAg). However, the composition and the material of the opposite electrode <NUM> are not limited thereto and may be variously changed in embodiments. The opposite electrode <NUM> may be formed not only in the display area DA but also in the first non-display area NDA1.

The first spacer <NUM>-<NUM> is arranged on the pixel-defining layer <NUM>, and protrudes in a direction from the pixel-defining layer <NUM> to the thin-film encapsulation layer <NUM>. During a process of depositing the intermediate layer <NUM> including the emission layer 320b by using a mask, the first spacer <NUM>-<NUM> maintains a separation between the mask and the substrate <NUM> to prevent the intermediate layer <NUM> from being chopped or torn by the mask during the deposition process.

The first spacer <NUM>-<NUM> may include an organic material such as, for example, polyimide (PI) or hexamethyldisiloxane (HMDSO). For example, the first spacer <NUM>-<NUM> may include a material the same as that of the pixel-defining layer <NUM>. The first spacer <NUM>-<NUM> may be arranged on at least one of the first and second dam portions <NUM> and <NUM> described below, may be used for preventing moisture transmission, and may form a step difference of the dam portions.

Since the organic light-emitting diode OLED may be easily damaged by external moisture or oxygen, the organic light-emitting diode OLED may be covered and protected by the thin-film encapsulation layer <NUM>.

The thin-film encapsulation layer <NUM> may cover the display area DA and extend outside the display area DA. For example, the thin-film encapsulation layer <NUM> may encapsulate the display area DA. Since the display area DA includes a plurality of pixels, the thin-film encapsulation layer <NUM> may encapsulate the plurality of pixels. The thin-film encapsulation layer <NUM> may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In an exemplary embodiment of the present disclosure, the thin-film encapsulation layer <NUM> may include a first inorganic encapsulation layer <NUM>, an organic encapsulation layer <NUM>, and a second inorganic encapsulation layer <NUM>.

The first inorganic encapsulation layer <NUM> may entirely cover the opposite electrode <NUM>, and may include, for example, silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON).

When needed, other layers such as a capping layer may be arranged between the first inorganic encapsulation layer <NUM> and the opposite electrode <NUM>. For example, to enhance a light efficiency, the capping layer may include at least one organic material or inorganic material selected from among silicon oxide (SiOx), silicon nitride (SiNx), zinc oxide (ZnO), titanium oxide (TiO<NUM>), zirconium oxide (ZrO<NUM>), indium tin oxide (ITO), indium zinc oxide (IZO), tris-(<NUM>-hydroxyquinoline) aluminum (Alq<NUM>), copper(II) phthalocyanine (CuPc), (<NUM>,<NUM>'-N,N'-dicarbazole) biphenyl (CBP), and N,N'-di-[(<NUM>-naphthyl)-N,N'-diphenyl]-<NUM>,<NUM>'-biphenyl)-<NUM>,<NUM>'-diamine (a-NPB). In an exemplary embodiment of the present disclosure, the capping layer may allow plasmon resonance to occur with respect to light generated by the organic light-emitting diode OLED. For example, the capping layer may include nano particles. The capping layer may prevent the organic light-emitting diode OLED from being damaged by heat, plasma, etc. occurring during a chemical vapor deposition (CVD) process or a sputtering process for forming the thin-film encapsulation layer <NUM>. For example, the capping layer may include an epoxy-based material including at least one of, for example, a bisphenol-type epoxy resin, an epoxidized butadiene resin, a fluorine-type epoxy resin, or a novolac epoxy resin. The capping layer may have an area larger than that of the opposite electrode <NUM> such that an end of the opposite electrode <NUM> is covered, thereby preventing oxidation of the opposite electrode <NUM> during the chemical vapor deposition (CVD) process or the sputtering process of forming the thin-film encapsulation layer <NUM>.

When needed, a layer including lithium fluoride (LiF), etc. may be arranged between the first inorganic encapsulation layer <NUM> and the capping layer.

Since the first inorganic encapsulation layer <NUM> is formed along a structure thereunder, a top surface of the first inorganic encapsulation layer <NUM> is not flat. For example, the first inorganic encapsulation layer <NUM> may be conformally formed on the structure thereunder. The organic encapsulation layer <NUM> covers the first inorganic encapsulation layer <NUM>, and may be planarized. For example, the organic encapsulation layer <NUM> may be formed on the first inorganic encapsulation layer <NUM> by a spin coating process. A top surface of the organic encapsulation layer <NUM> corresponding to the display area DA may be approximately flat.

The organic encapsulation layer <NUM> may include, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyimide (PI), polyethylene sulfonate (PES), polyoxymethylene (POM), polyarylate (PAr), hexamethyldisiloxane (HMDSO), an acrylic resin (e.g. polymethylmethacrylate (PMMA), a polyacrylic acid (PAA), etc.), or an arbitrary combination thereof.

The second inorganic encapsulation layer <NUM> may cover the organic encapsulation layer <NUM>, and may include, for example, silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON). Since the second inorganic encapsulation layer <NUM> is deposited to directly contact the first inorganic encapsulation layer <NUM> in an edge area of the display device <NUM>, the second inorganic encapsulation layer <NUM> may seal the organic encapsulation layer <NUM> such that the organic encapsulation layer <NUM> is not exposed to the outside. Accordingly, external moisture or oxygen may be prevented or reduced from being infiltrated into the display area DA through the organic encapsulation layer <NUM>.

During a subsequent process after the thin-film encapsulation layer <NUM> is formed, for example, a process of removing a protective film that has been stuck on the thin-film encapsulation layer <NUM> before forming a touch sensor layer on the thin-film encapsulation layer <NUM> or attaching a polarization film on the thin-film encapsulation layer <NUM>, a defect may occur in which the thin-film encapsulation layer <NUM> may be exfoliated from a back plane of the display device <NUM>. The back plane may be a structure of the display device <NUM> right before the thin-film encapsulation layer <NUM> is formed. For example, in the case where the opposite electrode <NUM> is formed right before the thin-film encapsulation layer <NUM> is formed, an exfoliation defect may occur between the thin-film encapsulation layer <NUM> and the display device <NUM> including the opposite electrode <NUM>. For example, in the case where the capping layer is formed between the thin-film encapsulation layer <NUM> and the opposite electrode <NUM> right before the thin-film encapsulation layer <NUM> is formed, an exfoliation defect may occur between the thin-film encapsulation layer <NUM> and the display device <NUM> including the capping layer. For example, in the case where a layer including LiF is formed on the capping layer and the first inorganic encapsulation layer <NUM>, an exfoliation defect may occur between the thin-film encapsulation layer <NUM> and the display device <NUM> including the layer including LiF. In addition, in the case where another functional layer is further added between the opposite electrode <NUM> and the thin-film encapsulation layer <NUM> right before the thin-film encapsulation layer <NUM> is formed, the display device <NUM> including the organic light-emitting diode OLED and the functional layer may be understood as the back plane.

To reduce an exfoliation defect of the thin-film encapsulation layer <NUM>, the present exemplary embodiment may increase contact strength between the thin-film encapsulation layer <NUM> and the back plane by forming the plurality of first holes TH1 serving as anchors for the thin-film encapsulation layer <NUM> between the plurality of pixels in the display area DA. For example, the plurality of first holes TH1 may reinforce adhesive force between the thin-film encapsulation layer <NUM> and the back plane, thereby reducing an exfoliation defect of the thin-film encapsulation layer <NUM>.

The first hole TH1 is formed to pass through a portion of the first spacer <NUM>-<NUM> and a portion of the pixel-defining layer <NUM>, and may have a predetermined opening space, with the first hole TH1 being arranged in a location apart from the pixel electrode <NUM>.

The first hole TH1 may have a first upper end UE1 and a second upper end UE2 having different heights from the substrate <NUM>. A first height H1 from the substrate <NUM> to the first upper end UE1 of the first hole TH1 is the same as a height from the substrate <NUM> to the top surface of the pixel-defining layer <NUM>, and a second height H2 from the substrate <NUM> to the second upper end UE2 of the first hole TH1 is the same as a height from the substrate <NUM> to the upper surface of the second portion SP2 of the first spacer <NUM>-<NUM>. That is, the second height H2 is greater than the first height H1.

In a virtual boundary surface located between the first portion SP1 and the second portion SP2 of the first spacer <NUM>-<NUM>, the bottom surface of the first portion SP1 of the first spacer <NUM>-<NUM> may coincide with the top surface of the second portion SP2 of the first spacer <NUM>-<NUM>. On the other hand, because the first portion SP1 of the first spacer <NUM>-<NUM> is located above the second portion SP2, a third height H3, which is the height from the substrate <NUM> to the upper surface of the first portion SP1 , is higher than the second height H2.

Referring to <FIG>, which is a cross-sectional view of the shapes of the pixel-defining layer 113and the first spacer <NUM>-<NUM>, in which the first hole TH1 is formed, in region V of <FIG>, the first hole TH1 is formed to have an undercut shape UC in a second portion SP2 of the first spacer <NUM>-<NUM> and the pixel-defining layer <NUM>.

The first spacer <NUM>-<NUM> includes the first portion SP1 and a second portion SP2, with the first portion SP1 having a width that increases toward the substrate <NUM> from a direction away from the substrate <NUM>, and the second portion SP2 being arranged between the first portion SP1 and the substrate <NUM> and having a width that is reduced toward the substrate <NUM>. For example, a first width W1 of the first spacer <NUM>-<NUM> at an arbitrary point of the first portion SP1 in a direction parallel to the substrate <NUM> increases from a point L2 to a point L1, with the point L2 being farthest away from the substrate <NUM>, and the point L1 being closer to the substrate <NUM> than the point L2. A second width W2 of the first spacer <NUM>-<NUM> at an arbitrary point of the second portion SP2 in the direction parallel to the substrate <NUM> may be reduced from the point L1 to a point L0. As shown in <FIG>, the point L0 may be at the lowest level of the first spacer <NUM>-<NUM>, the point L2 may be at the highest level of the first spacer <NUM>-<NUM>, and the point L1 may be at a level where the first portion SP1 and the second portion SP2 meet, for example, at the interface between the first portion SP1 and the second portion SP2. Alternatively, a tangential line ℓ1 at an arbitrary point (e.g., a point chosen at the right surface of the the first spacer <NUM>-<NUM>) on a surface of the first portion SP1 of the first spacer <NUM>-<NUM> may form an acute angle θ1 in a clockwise direction with respect to a virtual line parallel to the substrate <NUM>. A tangential line ℓ2 at an arbitrary point (e.g., a point chosen at the right surface of the the first spacer <NUM>-<NUM>) on a surface of the second portion SP2 of the first spacer <NUM>-<NUM> may form an obtuse angle θ2 in the clockwise direction with respect to a virtual line parallel to the substrate <NUM>. That is, the first portion SP1, which is a top region of the first spacer <NUM>-<NUM>, may be a forward-tapered shape, and the second portion SP2, which is a bottom region of the first spacer <NUM>-<NUM>, may be an inverse-tapered shape.

When the top region of the first spacer <NUM>-<NUM> is formed as an inverse-tapered shape, a contact area between a mask and the first spacer <NUM>-<NUM> increases during a process of depositing the intermediate layer <NUM> including the emission layer 320b by using the mask, the number of particles generated by the mask may increase. In contrast, according to the present exemplary embodiment, since the top region of the first spacer <NUM>-<NUM> is formed as a forward-tapered shape, the number of particles generated by the mask may be reduced.

Since the second portion SP2, which is the bottom region of the first spacer <NUM>-<NUM>, is formed as an inverse-tapered shape, the second portion SP2 constitutes the first hole TH1 in cooperation with a portion of the pixel-defining layer <NUM>, with the first hole TH1 constituting a predetermined opening space.

Referring to <FIG> again, the intermediate layer <NUM> and the opposite electrode <NUM> are formed on a bottom surface of the first hole TH1. The deposition of the intermediate layer <NUM> and the opposite electrode <NUM> on the bottom surface of the first hole TH1 may be non-conformal.

The first functional layer 320a and the second functional layer 320c of the intermediate layer <NUM> are formed inside the first hole TH1, and the emission layer 320b of the intermediate layer <NUM> is not be formed inside the first hole TH1. This is because the emission layer 320b may be deposited on only an emission area that is patterned for each pixel through a patterned metal mask, and the first and second functional layers 320a and 320c may be deposited as common layers over all the pixels without being patterned for each pixel. For example, the first and second functional layers 320a and 320c may be formed not only in areas over the pixels but also in areas between the pixels. Like the first and second functional layers 320a and 320c, the opposite electrode <NUM> may be deposited as a common layer over all the pixels. The opposite electrode <NUM> is formed not only in areas over the pixels but also in areas between the pixels.

The first inorganic encapsulation layer <NUM> of the thin-film encapsulation layer <NUM> is formed on the opposite electrode <NUM> inside the first hole TH1. The first inorganic encapsulation layer <NUM> is formed on not only the bottom surface of the first hole TH1 but also an entire inner surface of the first hole TH1 including the bottom surface of the first hole TH1 above the opposite electrode <NUM>. The deposition of first inorganic encapsulation layer <NUM> on the bottom surface of the first hole TH1 above the opposite electrode <NUM> may be conformal.

Although the first inorganic encapsulation layer <NUM> directly contacts the opposite electrode <NUM> on the bottom surface inside the first hole TH1, the first inorganic encapsulation layer <NUM> may directly contact the pixel-defining layer <NUM> and the first spacer <NUM>-<NUM> on a lateral surface of the first hole TH1. Therefore, contact areas between the first inorganic encapsulation layer <NUM> and the organic insulating layers increase and thus adhesive force of the thin-film encapsulation layer <NUM> may be reinforced.

The organic encapsulation layer <NUM> fills an entire inside of the first hole TH1. Particularly, according to the present exemplary embodiment, since the shape of the opening formed in the first hole TH1 is an undercut shape in which the first portion SP1 further protrudes than the second portion SP2 on an interface between the first portion SP1 and the second portion SP2 of the first spacer <NUM>-<NUM>, and the organic encapsulation layer <NUM> fills the opening having the undercut shape, the first hole TH1 serves as an anchor and thus may increase contact strength between the thin-film encapsulation layer <NUM> and the back plane.

As described above, the display device according to the present exemplary embodiment may increase contact strength between the thin-film encapsulation layer <NUM> and the back plane by forming the plurality of first holes TH1 between the plurality of pixels in the display area DA, thereby reducing a defect in which the thin-film encapsulation layer <NUM> is exfoliated from the back plane. Also, particles generated by a deposition mask may be reduced by forming the top portion of the first spacer <NUM>-<NUM> as a forward-tapered shape, and contact strength between the thin-film encapsulation layer <NUM> and the back plane may be increased by forming the bottom region of the first spacer <NUM>-<NUM> as an inverse-tapered shape and thus disconnecting the intermediate layer <NUM> and the common electrode <NUM> (or the opposite electrode <NUM>) inside and outside the first hole TH1 in which the undercut is formed.

Hereinafter, a manufacturing process of forming the first hole TH1 of <FIG> is described with reference to <FIG>.

<FIG> are cross-sectional views of a manufacturing process of forming the first hole TH1 in region V of <FIG> according to an exemplary embodiment of the present disclosure.

Referring to <FIG>, the first spacer <NUM>-<NUM> is located on the pixel-defining layer <NUM>. Although it is shown in <FIG> that the pixel-defining layer <NUM> and the first spacer <NUM>-<NUM> are expressed as different layers with different hatchings, embodiments of the present disclosure are not limited thereto. For example, the pixel-defining layer <NUM> and the first spacer <NUM>-<NUM> may include the same material. For example, the pixel-defining layer <NUM> and the first spacer <NUM>-<NUM> may be simultaneously formed by using a halftone mask during the same process. For example, the pixel-defining layer <NUM> and the first spacer <NUM>-<NUM> may each include an organic material such as, for example, polyimide (PI) or hexamethyldisiloxane (HMDSO).

Referring to <FIG>, a barrier layer BL is formed on the structure of <FIG> by a deposition process, and a second opening OP2 is formed by patterning the barrier layer BL, with the second opening OP2 exposing a portion of the pixel-defining layer <NUM> and a partial surface of a bottom region of the first spacer <NUM>-<NUM>.

Referring to <FIG>, the first hole TH1 is formed by etching a portion of the pixel-defining layer <NUM> and a portion of the first spacer <NUM>-<NUM> each corresponding to the second opening OP2 using the barrier layer BL as an etch mask. The first hole TH1 may be formed by dry etching.

Referring to <FIG>, the barrier layer BL is removed by wet etching.

The second portion SP2, which is a region of the first spacer <NUM>-<NUM> that is dry-etched, may have an inverse-tapered shape in which the second width W2 of the first spacer <NUM>-<NUM> is reduced toward the substrate <NUM>, and the first portion SP1, which is a region of the first spacer <NUM>-<NUM> that is not etched, may have a forward-tapered shape in which the first width W1 of the first spacer <NUM>-<NUM> increases toward the substrate <NUM>. Therefore, the first hole TH1 may have the undercut shape UC in which the first portion SP1 further protrudes than the second portion SP2 at an interface between the first portion SP1 and the second portion SP2 of the first spacer <NUM>-<NUM>. For example, the undercut shape UC of the first hole TH1 is formed in the second portion SP2 of the first spacer <NUM>-<NUM> and the pixel-defining layer <NUM> on a side of the first spacer <NUM>-<NUM>, with the first hole TH1 passing through a portion of the first spacer <NUM>-<NUM> and a portion of the pixel-defining layer <NUM>.

Referring to <FIG>, the intermediate layer <NUM> and the opposite electrode <NUM> are deposited in the first hole TH1. The intermediate layer <NUM> and the opposite electrode <NUM> are formed on the bottom surface of the first hole TH1, a top surface of the pixel-defining layer <NUM> outside the first hole TH1, and a top surface of the first spacer <NUM>-<NUM>. That is, the intermediate layer <NUM> and the opposite electrode <NUM> may be disconnected around the undercut UC of the first hole TH1. For example, the intermediate layer <NUM> and the opposite electrode <NUM> may be formed inside and outside the first hole TH1, such that the intermediate layer <NUM> and the opposite electrode <NUM> are disconnected inside and outside the first hole TH1. The intermediate layer <NUM> formed in the first hole TH1 may include the first functional layer 320a and the second functional layer 320c and may not include the emission layer 320b.

The intermediate layer <NUM> and the opposite electrode <NUM> may be formed by physical vapor deposition (PVD) which has poor step coverage. Thus, the intermediate layer <NUM> and the opposite electrode <NUM> may be non-conformally formed on the bottom surface of the first hole TH1, a top surface of the pixel-defining layer <NUM> outside the first hole TH1, and a top surface of the first spacer <NUM>-<NUM>. For example, the intermediate layer <NUM> and the opposite electrode <NUM> may be formed by one of, for example, sputtering, thermal evaporation, E-beam evaporation, laser molecular beam epitaxy, or pulsed laser deposition.

Referring to <FIG>, the thin-film encapsulation layer <NUM> is formed in the first hole TH1, with the thin-film encapsulation layer <NUM> including the first inorganic encapsulation layer <NUM>, the organic encapsulation layer <NUM>, and the second inorganic encapsulation layer <NUM>.

The first inorganic encapsulation layer <NUM> is stacked not only on the bottom surface of the first hole TH1 above the opposite electrode <NUM> inside the first hole TH1 but also over an entire inner surface of the first hole TH1. Also, the first inorganic encapsulation layer <NUM> is formed on a top surface of the pixel-defining layer <NUM> outside the first hole TH1 and on a top surface and a lateral surface of the first spacer <NUM>-<NUM>. That is, despite the undercut UC, the first inorganic encapsulation layer <NUM> may be continuously formed inside and outside the first hole TH1 without disconnection.

The first inorganic encapsulation layer <NUM> may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) having excellent step coverage compared to physical vapor deposition (PVD). Thus, the first inorganic encapsulation layer <NUM> may be conformally formed on the entire inner surface of the first hole TH1, on a top surface of the opposite electrode <NUM> outside the first hole TH1, and on a top surface and a lateral surface of the first spacer <NUM>-<NUM>. For example, the first inorganic encapsulation layer <NUM> may be formed by one of, for example, thermal CVD, plasma CVD, metal-organic (MO) CVD, or hydride vapor phase epitaxy (HVPE).

After the first inorganic encapsulation layer <NUM> is formed, the organic encapsulation layer <NUM> is formed. The organic encapsulation layer <NUM> fills an entire inner portion of the first hole TH1 and may have a planarized top surface. For example, the organic encapsulation layer <NUM> may be formed on the first inorganic encapsulation layer <NUM> by a spin coating process. After the organic encapsulation layer <NUM> is formed, the second inorganic encapsulation layer <NUM> is formed.

<FIG> is a cross-sectional view of a portion of a display device <NUM> according to an exemplary embodiment of the present disclosure. Hereinafter, differences between the exemplary embodiment of <FIG> and the exemplary embodiment of <FIG> are mainly described.

Referring to <FIG>, a first etching prevention layer ES1 is located on a portion of the first planarization layer <NUM> above which the first hole TH1 is formed. For example, the first etching prevention layer ES1 may be arranged under a bottom surface of the first hole TH1. The first hole TH1 is not only formed in the second portion SP2, which is the bottom region of the first spacer <NUM>-<NUM>, and the pixel-defining layer <NUM>, but also extends into the second planarization layer <NUM>.

The first etching prevention layer ES1 may be apart from the connection line CL, may include a material the same as that of the connection line CL, and may be formed during a process the same as a process of forming the connection line CL. The first etching prevention layer ES1 may prevent the deterioration of the first planarization layer <NUM> and various wirings, an electrode, a circuit, etc. of the display device <NUM> that are arranged thereunder during a process of forming the first hole TH1, for example, while the opening space of the first hole TH1 is formed by dry etching.

In the present exemplary embodiment, the intermediate layer <NUM> and the opposite electrode <NUM> are formed on the bottom surface of the first hole TH1, and the intermediate layer <NUM> may include the first functional layer 320a and the second functional layer 320c and may not include the emission layer 320b. Also, the first inorganic encapsulation layer <NUM> is not only stacked on the bottom surface of the first hole TH1 above the opposite electrode <NUM> but also continuously formed on the entire inner surface of the first hole TH1 including the bottom surface of the first hole TH1 and outside the first hole TH1, and the organic encapsulation layer <NUM> fills the inner portion of the first hole TH1. Therefore, adhesive force of the thin-film encapsulation layer <NUM> may be reinforced. For example, the plurality of first holes TH1 may serve as anchors for the thin-film encapsulation layer <NUM> between the plurality of pixels in the display area DA, and may reinforce adhesive force between the thin-film encapsulation layer <NUM> and the back plane, thereby reducing an exfoliation defect of the thin-film encapsulation layer <NUM>.

<FIG> is a cross-sectional view of a portion of a display device <NUM> according to an exemplary embodiment of the present disclosure. Hereinafter, differences between the exemplary embodiment of <FIG> and the exemplary embodiment of <FIG> are mainly described. <FIG> shows a cross-sectional region taken along line VIIIA-VIIIB of <FIG>, and a portion of the display area DA.

Referring to <FIG>, in the present exemplary embodiment, a plurality of second holes TH2 are formed in the first non-display area NDA1, and the first dam portion <NUM> and the second dam portion <NUM> are located outside the second hole TH2. The first dam portion <NUM> may be apart from a second dam portion <NUM> in the first non-display area NDA1, and each may surround the display area DA. Although, like the exemplary embodiment of <FIG>, the first holes TH1 may be formed in the display area DA in the present exemplary embodiment, the case where the second holes TH2 are formed in the first non-display area NDA1 is mainly described in the present exemplary embodiment.

The first planarization layer <NUM>, the second planarization layer <NUM>, and the pixel-defining layer <NUM> each extending from the display area DA are located in the first non-display area NDA1, and a second spacer <NUM>-<NUM> is located in the first non-display area NDA1, with the second spacer <NUM>-<NUM> including a material the same as that of the first spacer <NUM>-<NUM>.

The second hole TH2 is formed to pass through a portion of the second spacer <NUM>-<NUM> and a portion of the pixel-defining layer <NUM>, and may have a predetermined opening space. A structure of the second hole TH2 is similar to the structure of the first hole TH1. For example, a first portion SP1, which is a top region of the second spacer <NUM>-<NUM>, may be a forward-tapered shape, and a second portion SP2, which is a bottom region of the second spacer <NUM>-<NUM>, may be an inverse-tapered shape.

The intermediate layer <NUM> and the opposite electrode <NUM> may be formed not only in the display area DA but also in a portion of the first non-display area NDA1 outside the display area DA. That is, the intermediate layer <NUM> and the opposite electrode <NUM> may be formed on a bottom surface of the second hole TH2.

The first functional layer 320a and the second functional layer 320c of the intermediate layer <NUM> may be formed inside the second hole TH2, and the emission layer 320b of the intermediate layer <NUM> may not be formed inside the second hole TH2. Like the intermediate layer <NUM>, the opposite electrode <NUM> is formed on the bottom surface of the second hole TH2 and is not formed on a lateral surface of the second hole TH2. For example, the intermediate layer <NUM> and the opposite electrode <NUM> may be formed inside and outside the second hole TH2, such that the intermediate layer <NUM> and the opposite electrode <NUM> are disconnected inside and outside the second hole TH2. Like the first and second functional layers 320a and 320c, the opposite electrode <NUM> may be deposited as a common layer over all the pixels. Similar to the first spacer <NUM>-<NUM>, during a process of depositing the intermediate layer <NUM> including the emission layer 320b by using a mask, the second spacer <NUM>-<NUM> may maintain a separation between the mask and the substrate <NUM> to prevent the intermediate layer <NUM> from being chopped or torn by the mask during the deposition process.

When viewed from a side parallel to the substrate <NUM>, since the opposite electrode <NUM> is entirely connected outside the opening in which the second holes TH2 are formed, the opposite electrode <NUM> extending from the display area DA may be electrically connected to the second power voltage line <NUM> through a pixel electrode connection line 310a.

The first inorganic encapsulation layer <NUM> is formed on the opposite electrode <NUM>. The first inorganic encapsulation layer <NUM> is not only stacked on the bottom surface of the second hole TH2 above the opposite electrode <NUM> but also formed on the entire inner surface of the second hole TH2 including the bottom surface of the second hole TH2, extends to the outside of the second hole TH2, and extends to the first dam portion <NUM> and the second dam portion <NUM>.

Although the first inorganic encapsulation layer <NUM> directly contacts the opposite electrode <NUM> on the bottom surface inside the second hole TH2, the first inorganic encapsulation layer <NUM> may directly contact the pixel-defining layer <NUM> and the second spacer <NUM>-<NUM> on the lateral surface of the second hole TH2. Therefore, contact areas between the first inorganic encapsulation layer <NUM> and the organic insulating layers increase and thus adhesive force of the thin-film encapsulation layer <NUM> may be reinforced.

The organic encapsulation layer <NUM> fills an entire inner portion of the second hole TH2. Since the shape of the opening formed in the second hole TH2 is an undercut shape in which the first portion SP1 further protrudes than the second portion SP2 on an interface between the first portion SP1 and the second portion SP2 of the second spacer <NUM>-<NUM>, and the organic encapsulation layer <NUM> fills the opening having the undercut shape, the second hole TH2 serves as an anchor and thus may increase contact strength between the thin-film encapsulation layer <NUM> and the back plane. For example, a plurality of second holes TH2 may serve as anchors for the thin-film encapsulation layer <NUM> in the first non-display area NDA1, and may reinforce adhesive force between the thin-film encapsulation layer <NUM> and the back plane, thereby reducing an exfoliation defect of the thin-film encapsulation layer <NUM>.

Since the first hole TH1 described in <FIG> is provided as a plurality of first holes TH1 in the display area DA, when the first holes TH1 are additionally arranged in the display area DA between the pixels P, space limitation occurs as the resolution is raised. In contrast, since the second holes TH2 according to the present exemplary embodiment are formed in the first non-display area NDA1, a greater number of holes per unit area may be formed with high density without space limitation.

The first dam portion <NUM> and the second dam portion <NUM> are arranged at locations overlapping the second power voltage line <NUM> outside the second hole TH2.

The first dam portion <NUM> may include a first layer 111a, a second layer 113a, and a third layer 115a, with the first layer 111a including a material the same as that of the second planarization layer <NUM>, the second layer 113a including a material the same as that of the pixel-defining layer <NUM>, and the third layer 115a including a material the same as that of the first spacer <NUM>-<NUM> and the second spacer <NUM>-<NUM>. However, the layers constituting the first dam portion <NUM> are not limited thereto and the number of layers and the material of layers may be changed in embodiments. For example, in an exemplary embodiment of the present disclosure, the first dam portion <NUM> may further include an additional layer including a material the same as that of the first planarization layer <NUM> to form a four-layered structure.

A portion of the first dam portion <NUM> may overlap the opposite electrode <NUM> extending from the display area DA. Since an end portion of the opposite electrode <NUM> extends to the second power voltage line <NUM>, a noise that may influence a touch sensor layer may be blocked, with the touch sensor layer being formed on the thin-film encapsulation layer <NUM>.

The second dam portion <NUM> may include a first layer 109b, a second layer 111b, a third layer 113b, and a fourth layer 115b, with the first layer 109b including a material the same as that of the first planarization layer <NUM>, the second layer 111b including a material the same as that of the second planarization layer <NUM>, and the third layer 113b including a material the same as that of the pixel-defining layer <NUM>, and the fourth layer 115b including a material the same as that of the first spacer <NUM>-<NUM> and the second spacer <NUM>-<NUM>. However, the layers constituting the second dam portion <NUM> are not limited thereto and the number of layers and the material of layers may be changed in embodiments.

The first and second dam portions <NUM> and <NUM> may serve as dams blocking an organic material flowing in an edge direction of the substrate <NUM> while forming the organic encapsulation layer <NUM> including the organic material (see <FIG>). The second dam portion <NUM> may be higher than the first dam portion <NUM>. Since a height of the second dam portion <NUM> is higher than a height of the first dam portion <NUM>, the organic encapsulation layer <NUM> may be prevented from flooding over the second dam portion <NUM> to generate an edge tail. Also, during a process of depositing the intermediate layer <NUM> by using a mask, the second dam portion <NUM> maintains a separation between the mask and the substrate <NUM> to prevent the intermediate layer <NUM> from being chopped or torn by the mask during the deposition process.

The first layer 109b of the second dam portion <NUM> may clad an end portion of the second power voltage line <NUM> to prevent the second power voltage line <NUM> from being deteriorated during wet etching.

The first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> cover the first dam portion <NUM> and the second dam portion <NUM> beyond the display area DA and the area in which the second hole TH2 is formed, and extend to an edge portion of the substrate <NUM>. The first inorganic encapsulation layer <NUM> may directly contact the second inorganic encapsulation layer <NUM> outside the second dam portion <NUM> to prevent external moisture or impurities from propagating into the display device through the organic encapsulation layer <NUM>.

According to the present exemplary embodiment, the second hole TH2 formed in the first non-display area NDA1 may prevent exfoliation of the thin-film encapsulation layer <NUM> by reinforcing adhesion strength between the thin-film encapsulation layer <NUM> and the back plane as described above. Also, since an opening space is formed in a direction perpendicular to the substrate <NUM> by a depth of the second hole TH2 formed in the second spacer <NUM>-<NUM> and the pixel-defining layer <NUM>, the second hole TH2 may reduce reflow velocity of an organic insulating material during a process of forming the organic encapsulation layer <NUM> by using the organic insulating material having fluidity.

The organic encapsulation layer <NUM> may be prevented from flooding over the second dam portion <NUM> to generate an edge tail at an edge of the substrate <NUM> by forming the height of the second dam portion <NUM> higher than the height of the first dam portion <NUM>. However, in the case where an interval between first dam portion <NUM> and the second dam portion <NUM> is reduced to reduce a width of a dead space, it may be difficult to control a reflow velocity of the organic encapsulation layer <NUM>, and the organic encapsulation layer <NUM> may flood over the second dam portion <NUM>. In this case, without the second holes TH2, the first and second dam portions <NUM> and <NUM> may not be sufficient to prevent the organic insulating material of the organic encapsulation layer <NUM> from flooding over the second dam portion <NUM> to generate an edge tail at an edge of the substrate <NUM>.

The second holes TH2 according to the present exemplary embodiment are a plurality of opening spaces formed between the display area DA and the first dam portion <NUM>. The second holes TH2 may prevent the generation of the edge tail due to the organic insulating material by reducing a reflow velocity of the organic insulating material flowing in an edge direction of the substrate <NUM> and allowing the organic insulating material to be sufficiently hardened before the organic insulating material reaches the second dam portion <NUM>.

Referring to <FIG>, the plurality of second holes TH2 are formed in the first non-display area NDA1, and the first dam portion <NUM> and the second dam portion <NUM> are located outside the second hole TH2.

A second etching prevention layer ES2 is located on the first planarization layer <NUM> extending from the display area DA to the first non-display area NDA1. For example, the second etching prevention layer ES2 may be arranged under a bottom surface of the second hole TH2. The second hole TH2 is not only formed in the second portion SP2, which is the bottom region of the second spacer <NUM>-<NUM>, and the pixel-defining layer <NUM>, but also extends into the second planarization layer <NUM>. In addition, the second hole TH2 may extend to the second etching prevention layer ES2, for example, to a top surface of the second etching prevention layer ES2.

The second etching prevention layer ES2 may be apart from the connection line CL, may include a material the same as that of the connection line CL, and may be formed during a process the same as a process of forming the connection line CL. The second etching prevention layer ES2 may prevent the deterioration of the first planarization layer <NUM> and various wirings, an electrode, a circuit, etc. of the display device <NUM> that are arranged thereunder during a process of forming the second hole TH2, for example, while the opening space of the second hole TH2 is formed by dry etching.

In the present exemplary embodiment, the intermediate layer <NUM> and the opposite electrode <NUM> are formed on the bottom surface of the second hole TH2, and the intermediate layer <NUM> may include the first functional layer 320a and the second functional layer 320c and may not include the emission layer 320b. Also, the first inorganic encapsulation layer <NUM> is not only stacked on the bottom surface of the second hole TH2 above the opposite electrode <NUM> but also continuously formed on the entire inner surface of the second hole TH2 including the bottom surface of the second hole TH2 and outside the second hole TH2, and the organic encapsulation layer <NUM> fills the inner portion of the second hole TH2. Therefore, adhesive force of the thin-film encapsulation layer <NUM> may be reinforced. For example, a plurality of second holes TH2 may serve as anchors for the thin-film encapsulation layer <NUM> in the first non-display area NDA1, and may reinforce adhesive force between the thin-film encapsulation layer <NUM> and the back plane, thereby reducing an exfoliation defect of the thin-film encapsulation layer <NUM>.

Since the second holes TH2 are formed in the first non-display area NDA1, a greater number of holes per unit area may be formed at high density without space limitation, and a reflow velocity of the organic insulating material may be reduced by making a depth of the second hole TH2 deeper. Accordingly, the second holes TH2 with deeper depth may prevent the generation of the edge tail due to the organic insulating material by reducing a reflow velocity of the organic insulating material flowing in an edge direction of the substrate <NUM> and allowing the organic insulating material to be sufficiently hardened before the organic insulating material reaches the second dam portion <NUM>, during the process of forming the organic encapsulation layer <NUM> including the organic insulating material.

<FIG> is a cross-sectional view of the display device taken along line XA-XB of <FIG>, <FIG> is a cross-sectional view of a portion of a display device <NUM> according to an exemplary embodiment of the present disclosure, <FIG> is a cross-sectional view of region XII of <FIG>, and <FIG> is a cross-sectional view of region XIII of <FIG>. Hereinafter, differences between the exemplary embodiment of <FIG> and the exemplary embodiment of <FIG> are mainly described.

Referring to <FIG>, the display device <NUM> (see <FIG>) may include an input sensing layer <NUM>, an optical functional layer <NUM>, and a window <NUM> each arranged on a display panel <NUM>', with the window <NUM> covering the input sensing layer <NUM> and the optical functional layer <NUM>.

The display panel <NUM>' may be understood as a structure including the back plane and the thin-film encapsulation layer <NUM> in the display devices <NUM>, <NUM>, <NUM>, and <NUM> of the previous exemplary embodiments. The input sensing layer <NUM> arranged on the display panel <NUM>' may obtain coordinate information corresponding to an external input, for example, a touch event, and the optical functional layer <NUM> may include a reflection prevention layer including a phase retarder and a polarizer. The input sensing layer <NUM> may sense an external input according to a mutual capacitance method or a self-capacitance method. For example, the input sensing layer <NUM> may obtain information on the external input through a change in capacitance between two sensing electrodes. Although the input sensing layer <NUM> is located between the display panel <NUM>' and the optical functional layer <NUM> as shown in <FIG>, embodiments of the present disclosure are not limited thereto. For example, in an exemplary embodiment of the present disclosure, the input sensing layer <NUM> may be located over the optical functional layer <NUM>.

In an exemplary embodiment of the present disclosure, the optical functional layer <NUM> may include a black matrix and a color filter, and may include a lens layer. The color filters may be arranged by taking into account the colors of light beams emitted by the pixels of the display panel <NUM>'. Thus, the desired color may be realized by filtering the light emitted by each of the pixels with the color filter. The lens layer may enhance the emission efficiency or reduce color deviation of light emitted from the display panel <NUM>'. In an exemplary embodiment of the present disclosure, an array of lenses of the lens layer may cover an array of pixels, in which at least one of the lenses may cover at least one of the pixels.

Openings <NUM>, <NUM>, and <NUM> may be formed in an opening area OA surrounded by the display area DA, the openings <NUM>, <NUM>, and <NUM> respectively passing through the display panel <NUM>', the input sensing layer <NUM>, and the optical functional layer <NUM>.

Various components <NUM>' such as, for example, a sensor, a camera, a speaker, a lamp, etc. may be arranged in the opening area OA. The component <NUM>' may detect an external object received through the opening area OA or provide a sound signal such as voice to the outside through the opening area OA. In addition, the component <NUM>' may include a plurality of configurations, and is not limited to any one exemplary embodiment. Also, as shown in a dotted line, the component <NUM>' may be arranged below the display panel <NUM>'. In this case, at least one of the display panel <NUM>', the input sensing layer <NUM>, or the optical functional layer <NUM> may not include an opening.

Although <FIG> and <FIG> show a structure in which one circular opening area OA is entirely surrounded by the display area DA, embodiments of the present disclosure are not limited thereto. For example, the number of opening areas OA, the shape and the arrangement of the opening area OA may be variously changed. For example, in an exemplary embodiment of the present disclosure, the shape of the opening area OA may be modified in various ways such as, for example, a circular shape, an elliptical shape, a polygonal shape, a star shape, or a diamond shape. When two or more opening areas OA are provided, the opening areas OA may have the same shape or different shapes, and may have the same size or different sizes. Also, the second non-display area NDA2 may be located around the opening area OA, and the second non-display area NDA2 may be surrounded by the display area DA.

Referring to <FIG>, according to the present exemplary embodiment, a plurality of third holes TH3 and a plurality of grooves G1, G2, and G3 are formed in the second non-display area NDA2. Like the exemplary embodiment of <FIG>, the first holes TH1 may be formed in the display area DA in the present exemplary embodiment, and like the exemplary embodiment of <FIG>, the second holes TH2 may be formed in the first non-display area NDA1 in the present exemplary embodiment. However, the present exemplary embodiment mainly describes the case where the third holes TH3 are formed in the second non-display area NDA2 surrounding the opening area OA.

A partition wall <NUM> may be located in the second non-display area NDA2, with the partition wall <NUM> including the first planarization layer <NUM>, the second planarization layer <NUM>, and the pixel-defining layer <NUM> each extending from the display area DA.

The partition wall <NUM> may surround the opening area OA, and may prevent the organic encapsulation layer <NUM> from penetrating into the opening area OA by controlling the reflow of the organic encapsulation layer <NUM>, thereby preventing external impurities from progressing to the display area DA through the organic encapsulation layer <NUM> through the opening area OA. The number of partition walls <NUM>, the height and the material of the partition wall <NUM> are not limited to those of <FIG> and may be variously changed in embodiments.

A third spacer <NUM>-<NUM> may be located on a base layer 113c in the second non-display area NDA2, with the base layer 113c including a material the same as that of the pixel-defining layer <NUM>. The third spacer <NUM>-<NUM> may include a material the same as that of the first spacer <NUM>-<NUM>. Also, the third spacer <NUM>-<NUM> may include a material the same as that of the second spacer <NUM>-<NUM> (see <FIG>).

The third hole TH3 is formed to pass through a portion of the third spacer <NUM>-<NUM> and a portion of the base layer 113c, and may have a predetermined opening space. A structure of the third hole TH3 is similar to the structure of the first hole TH1. For example, a first portion SP1, which is a top region of the third spacer <NUM>-<NUM>, may be a forward-tapered shape, and a second portion SP2, which is a bottom region of the third spacer <NUM>-<NUM>, may be an inverse-tapered shape.

The plurality of grooves G1, G2, and G3 are located in the second non-display area NDA2, with the plurality of grooves G1, G2, and G3 exposing a portion of the substrate <NUM>. The first groove G1, the second groove G2, and the third groove G3 are arranged in a sequence close to the display area DA. Although three grooves are shown in <FIG>, embodiments of the present disclosure are not limited thereto and the number of grooves may be adjusted. Also, each of the grooves may have a ring shape entirely surrounding the opening area OA in plan view.

Referring to <FIG>, the intermediate layer <NUM> and the opposite electrode <NUM> may be formed not only in the display area DA but also in a portion of the second non-display area NDA2 surrounding the opening area OA. The intermediate layer <NUM> and the opposite electrode <NUM> may be formed on bottom surfaces of the third hole TH3 and the third groove G3.

The first functional layer 320a and the second functional layer 320c of the intermediate layer <NUM> may be formed inside the third hole TH3 and the third groove G3, and the emission layer 320b of the intermediate layer <NUM> may not be formed inside the third hole TH3 and the third groove G3. Like the intermediate layer <NUM>, the opposite electrode <NUM> is formed on the bottom surfaces of the third hole TH3 and the third groove G3, and is not formed on lateral surfaces of the third hole TH3 and the third groove G3.

The first inorganic encapsulation layer <NUM> is formed on the opposite electrode <NUM>. The first inorganic encapsulation layer <NUM> is not only stacked on the bottom surface of the third hole TH3 above the opposite electrode <NUM> but also formed on the entire inner surface of the third hole TH3 including the bottom surface of the third hole TH3, and extends to the outside of the third hole TH3. Also, the first inorganic encapsulation layer <NUM> is not only stacked on the bottom surface of the third groove G3 but also formed on the entire inner surface of the third groove G3 including the bottom surface of the third groove G3, and extends to the outside of the third groove G3 to entirely encapsulate the second non-display area NDA2 in cooperation with the first inorganic encapsulation layer <NUM> extending from the third hole TH3.

Unlike the previous exemplary embodiments, according to the present exemplary embodiment, the second inorganic encapsulation layer <NUM> is connected inside and outside the third hole TH3 and the third groove G3 without disconnection to entirely encapsulate the second non-display area NDA2. The first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> each connected inside and outside the third hole TH3 and the third groove G3 without disconnection may reinforce adhesive force of the thin-film encapsulation layer <NUM> by increasing a contact area thereof. Also, since the first inorganic encapsulation layer <NUM> and the second inorganic encapsulation layer <NUM> extend to the opening area OA without the organic encapsulation layer <NUM>, external impurities through the opening area OA may be prevented from progressing to the display area DA through the organic encapsulation layer <NUM>.

In this case, only the first inorganic encapsulation layer <NUM> may be connected without disconnection inside and outside the first groove G1 formed between the partition wall <NUM> and the display area DA, and the organic encapsulation layer <NUM> may fill the inner portion of the first groove G1.

In the case where an adhesive layer including an organic insulating material is further formed on the second inorganic encapsulation layer <NUM> of the display panel <NUM>', the adhesive layer may fill an inner portion of the third hole TH3 and the third groove G3 to reinforce adhesive force between the adhesive layer and the display panel <NUM>'. For example, the third hole TH3 and the third groove G3 may serve as anchors for the thin-film encapsulation layer <NUM> and the adhesive layer in the second non-display area NDA2, and may reinforce adhesive force between the adhesive layer/the thin-film encapsulation layer <NUM> and the back plane, thereby reducing an exfoliation defect of the thin-film encapsulation layer <NUM> and the adhesive layer.

Hereinafter, a manufacturing process of forming the third hole TH3 of <FIG> is described with reference to <FIG>.

<FIG> are cross-sectional views of a process of manufacturing the display device of <FIG> according an exemplary embodiment of the present disclosure.

Referring to <FIG>, the partition wall <NUM> is formed in the second non-display area NDA2, with the partition wall <NUM> including the first planarization layer <NUM>, the second planarization layer <NUM>, and the pixel-defining layer <NUM> each extending from the display area DA. The third spacer <NUM>-<NUM> is formed on the base layer 113c including a material the same as that of the pixel-defining layer <NUM> in the display area DA.

Although it is shown in <FIG> that the base layer 113c and the third spacer <NUM>-<NUM> are expressed as different layers with different hatchings, embodiments of the present disclosure are not limited thereto. For example, the base layer 113c and the third spacer <NUM>-<NUM> may include the same material. For example, the base layer 113c and the third spacer <NUM>-<NUM> may be simultaneously formed by using a halftone mask during the same process.

Referring to <FIG>, a barrier layer BL is formed on the structure of <FIG> by a deposition process, and a third opening OP3 is formed by patterning the barrier layer BL, with the third opening OP3 exposing a portion of the base layer 113c and a partial surface of a bottom region of the third spacer <NUM>-<NUM>. In this case, a third opening OP3 exposing a partial surface of the buffer layer <NUM> on the substrate <NUM> is simultaneously formed.

Referring to <FIG>, the third hole TH3 is formed by etching a portion of the base layer 113c and a portion of the third spacer <NUM>-<NUM> each corresponding to the third opening OP3 using the barrier layer BL as an etch mask, and the first to third grooves G1, G2, and G3 are formed by etching a portion of the buffer layer <NUM> and a portion of the substrate <NUM> each corresponding to the third opening OP3 using the barrier layer BL as an etch mask. The third hole TH3 and the first to third grooves G1, G2, and G3 may be formed by dry etching.

The second portion SP2 of the third spacer <NUM>-<NUM>, which is dry-etched, may have an inverse-tapered shape, and the first portion SP1 of the third spacer <NUM>-<NUM>, which is not etched, may have a forward-tapered shape. Therefore, the third hole TH3 may have an undercut shape UC in which the first portion SP1 further protrudes than the second portion SP2 at an interface between the first portion SP1 and the second portion SP2 of the third spacer <NUM>-<NUM>.

End portions of the buffer layer <NUM> may further protrude than lateral sides of the substrate <NUM> with respect to a surface on which the buffer layer <NUM> contacts the substrate <NUM> in a region in which the first to third grooves G1, G2, and G3 are formed. Therefore, the buffer layer <NUM> may have an undercut shape.

Referring to <FIG>, the intermediate layer <NUM> and the opposite electrode <NUM> are deposited on the structure of <FIG>.

The intermediate layer <NUM> and the opposite electrode <NUM> may be formed on a bottom surface of each of the third hole TH3 and the first to third grooves G1, G2, and G3 and may be disconnected without being connected to the outside of the third hole TH3 and the first to third grooves G1, G2, and G3. The intermediate layer <NUM> formed in the third hole TH3 and the first to third grooves G1, G2, and G3 may include the first functional layer 320a and the second functional layer 320c and may not include the emission layer 320b.

The intermediate layer <NUM> and the opposite electrode <NUM> may be formed by physical vapor deposition (PVD) which has poor step coverage. Thus, the intermediate layer <NUM> and the opposite electrode <NUM> may be non-conformally formed on the bottom surfaces of the third hole TH3 and the first to third grooves G1, G2, and G3, and on other surfaces outside the third hole TH3 and the first to third grooves G1, G2, and G3. For example, the intermediate layer <NUM> and the opposite electrode <NUM> may be formed by one of, for example, sputtering, thermal evaporation, E-beam evaporation, laser molecular beam epitaxy, or pulsed laser deposition.

Referring to <FIG>, the thin-film encapsulation layer <NUM> is formed on the structure of <FIG>, with the thin-film encapsulation layer <NUM> including the first inorganic encapsulation layer <NUM>, the organic encapsulation layer <NUM>, and the second inorganic encapsulation layer <NUM>.

The first inorganic encapsulation layer <NUM> is not only stacked on the bottom surface of each of the third hole TH3 and the first to third grooves G1, G2, and G3 but also formed on an entire inner surface of each of the third hole TH3 and the first to third grooves G1, G2, and G3. Also, the first inorganic encapsulation layer <NUM> is formed on a top surface of the base layer 113c outside the third hole TH3 and on a top surface and lateral sides of the third spacer <NUM>-<NUM>. Also, the first inorganic encapsulation layer <NUM> is formed on a top surface of the buffer layer <NUM> outside the first to third grooves G1, G2, and G3. That is, despite the undercut UC, the first inorganic encapsulation layer <NUM> may be continuously formed without disconnection inside and outside the third hole TH3 and the first to third grooves G1, G2, and G3.

The first inorganic encapsulation layer <NUM> may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) having excellent step coverage compared to physical vapor deposition (PVD). Thus, the first inorganic encapsulation layer <NUM> may be conformally formed on the entire inner surfaces of the third hole TH3 and the first to third grooves G1, G2, and G3, and on other surfaces outside the third hole TH3 and the first to third grooves G1, G2, and G3. For example, the first inorganic encapsulation layer <NUM> may be formed by one of, for example, thermal CVD, plasma CVD, metal-organic (MO) CVD, or hydride vapor phase epitaxy (HVPE).

After the first inorganic encapsulation layer <NUM> is formed, the organic encapsulation layer <NUM> is formed. The organic encapsulation layer <NUM> is adjusted by the partition wall <NUM> and does not flood over the partition wall <NUM>. The organic encapsulation layer <NUM> may fill an entire inner portion of the first groove G1.

After the organic encapsulation layer <NUM> is formed, the second inorganic encapsulation layer <NUM> is formed. The second inorganic encapsulation layer <NUM> may include a material the same as that of the first inorganic encapsulation layer <NUM>, and may be formed using a process the same as a process of forming the first inorganic encapsulation layer <NUM>. The second inorganic encapsulation layer <NUM> is not only stacked on the bottom surface of each of the third hole TH3 and the second and third grooves G2 and G3 above the first inorganic encapsulation layer <NUM> but also formed on an entire inner surface of each of the third hole TH3 and the second and third grooves G2 and G3. Also, the second inorganic encapsulation layer <NUM> is formed on a top surface of the base layer 113c outside the third hole TH3 and on a top surface and lateral sides of the third spacer <NUM>-<NUM>. Also, the second inorganic encapsulation layer <NUM> is formed on a top surface of the buffer layer <NUM> outside the first to third grooves G1, G2, and G3. That is, despite the undercut UC, the second inorganic encapsulation layer <NUM> may be continuously formed without disconnection inside and outside the third hole TH3 and the second and third grooves G2 and G3.

Claim 1:
A display device comprising (<NUM>):
a display area (DA) located over a substrate (<NUM>), the display area including a plurality of pixels (P) of which each includes a first electrode (<NUM>),
a second electrode (<NUM>) and an intermediate layer (<NUM>) including an emission layer (320b) and at least one functional layer (320a, 320c), and arranged between the first electrode (<NUM>) and the second electrode (<NUM>);
a pixel-defining layer (<NUM>) covering edges of the first electrode of each of the plurality of pixels;
a first spacer (<NUM>-<NUM>) arranged on the pixel-defining layer and including a first portion (SP1) and a second portion (SP2), and the second portion of the first spacer being arranged between the first portion of the first spacer and the substrate; and
a first hole (TH1) arranged apart from the first electrode (<NUM>) in the display area, the first hole being formed in the second portion of the first spacer and the pixel-defining layer,
wherein the first hole has a first upper end (UE1) and a second upper end (UE2), a first height of the first upper end from the substrate (H1) being different from a second height of the second upper end from the substrate (H2);
characterized in that the first portion (SP1) of the first spacer has a width increasing toward the substrate and the second portion (SP2) of the first spacer has a width decreasing toward the substrate;
wherein the least one functional layer (320a, 320c) and the second electrode (<NUM>) are located inside the first hole (TH1), and the emission layer (320b) is not located inside the first hole (TH1).