Patent Description:
The present invention is related to crystal oscillators, and more particularly, to a crystal oscillator and a phase noise reduction method thereof.

For an electronic system such as a phase-locked loop, a reference clock is required. More particularly, phase noise of the reference clock severely impact overall performance of the electronic system, and phase noise related performance is therefore demanding. In general, the reference clock can be generated by a crystal oscillator such as a Pierce oscillator or a Colpitts oscillator. Proposed methods and related architecture in a related art greatly increase additional circuits to improve overall performance of the crystal oscillator (e.g. reduce phase noise thereof). Thus, there is a need for a novel architecture and related method, to reduce phase noise of the crystal oscillator (more particularly, to reduce the phase noise of the reference clock) without introducing any side effect or in a way that is less likely to introduce side effects.

<CIT> discloses a low phase noise technique for use with a crystal oscillator, in which a bias control circuit sets a bias voltage on the gate of a first transistor needed to sink or source an amount of current corresponding to a sensed common mode signal. The sensed common mode signal is sensed with a common mode sense circuit that is coupled across two ports of the crystal oscillator, and current is provided by a current source. The bias voltage is set by a bias controller that uses a second transistor coupled to the common mode sense circuit and the first transistor.

<CIT> discloses a crystal oscillator configured to limit crystal drive level in the crystal oscillator by clamping via a diode-resistor branch, voltage applied to a drain pad of the crystal oscillator. The crystal oscillator is a Pierce crystal oscillator based implementation. The crystal oscillator comprises an on-chip main branch, comprising at least one transistor element; an on-chip drain branch connecting the main branch to a drain pad; an on-chip gate branch connecting the main branch to a gate pad. The diode-resistor branch is connected to the drain branch, and comprises at least one diode and at least one resistor element. The at least one diode and the at least one resistor element are connected in series in the diode-resistor branch. The clamped voltage is applied from an off-chip drain node, through the drain pad.

<CIT> discloses a crystal oscillator comprising: an inverter configured to receive a first voltage at a first node and output a second voltage at a second node; a feedback network inserted between the first node and the second node, wherein the feedback network includes a serial connection of a first feedback resistor, a clamp network, and a second feedback resistor; a first optional resistor inserted between the second node and a third node; a second optional resistor inserted between a fourth node and the first node; a crystal inserted between the third node and the fourth node; a first shunt capacitor inserted between the third node and a ground node; and a second shunt capacitor inserted between the fourth node to and the ground node.

<CIT> discloses a crystal oscillation circuit including a crystal oscillator coupled between an input pad node and an output pad node, a current mirror inverting amplifier configured to have a first input terminal coupled to the input pad node and an output terminal coupled to the output pad node, a detection logic circuit configured to detect a signal of the output pad node to generate an output pad node detection signal, and an automatic control logic circuit configured to apply a pull-up driver control signal to a second input terminal of the current mirror inverting amplifier in response to the output pad node detection signal. The current mirror inverting amplifier operates with a first gain or a second gain lower than the first gain according to the pull-up driver control signal.

This in mind, an objective of the present invention is to provide a crystal oscillator and a phase noise reduction method thereof, to improve phase noise related performance of an electronic system, and more particularly, to reduce phase noise of a reference clock output from a crystal oscillator of the electronic system.

The crystal oscillator and the phase noise reduction method of the present invention can reduce phase noise without calibrating the timing of performing the phase noise reset operation, and overall costs of implementing the phase noise reduction can be greatly reduced in comparison with the related art. Thus, the present invention can reduce phase noise of the crystal oscillator (more particularly, to reduce phase noise of a reference clock such as a pulse wave output from the crystal oscillator) without introducing any side effect or in a way that is less likely to introduce side effects.

Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

<FIG> is a diagram illustrating a crystal oscillator <NUM>. The crystal oscillator <NUM> may comprise a crystal oscillator core circuit <NUM>, a bias circuit such as a direct current (DC) bias circuit <NUM>, a bias resistor Rbias and a pulse wave buffer such as a square wave buffer <NUM> (which is labeled "NBUF" for brevity). The crystal oscillator core circuit <NUM> may be a Colpitts oscillator as shown in <FIG>, which comprises a crystal tank XTAL (which may be referred to as "crystal oscillator (XO)"), capacitors C1 and C2, a transistor and a current source. The crystal oscillator core circuit <NUM> may be replaced with a Pierce oscillator. The DC bias circuit <NUM> is coupled to an output terminal of the crystal oscillator <NUM> through the bias resistor Rbias, and the square wave buffer <NUM> is coupled to the output terminal of the crystal oscillator <NUM>. For example, the output terminal of the crystal oscillator and an input terminal of the square wave buffer <NUM> are coupled to a node of the crystal oscillator <NUM>, and the DC bias circuit <NUM> is coupled to this node through the bias resistor Rbias, where an input impedance of this node may be indicated by Zin, and Zin is roughly determined by the bias resistor Rbias.

The crystal oscillator core circuit <NUM> is designed to have a high quality factor (e.g. greater than or equal to <NUM>), and is configured to generate a sinusoidal wave. The DC bias circuit <NUM> may comprise one or more transistors as shown in <FIG>, and is configured to provide a bias voltage of the sinusoidal wave, such as a DC bias voltage VB. For example, the sinusoidal wave is carried on the level of the DC bias voltage VB (more particularly, the sinusoidal wave may regularly vary up and down based on the level of the DC bias voltage VB). In addition, the pulse wave buffer such as the square wave buffer <NUM> may generate a pulse wave such as a square wave on an output terminal OUT of the square wave buffer <NUM> according to the sinusoidal wave. For example, the square wave buffer <NUM> may comprise an inverter or a chain of inverters, wherein when the level of the sinusoidal wave is greater than a threshold (e.g. an input voltage level threshold) of the square wave buffer <NUM>, the square wave may have a first state (e.g. a first logic value such as "<NUM>"), and when the level of the sinusoidal wave is less than the threshold of the square wave buffer <NUM>, the square wave may have a second state (e.g. a second logic value such as "<NUM>"). The pulse wave generated by the pulse wave buffer may be a rectangular wave having a duty cycle equal to <NUM>%, such as the square wave. The pulse wave generated by the pulse wave buffer may be a rectangular wave having a duty cycle that is not <NUM>%. The following descriptions takes the square wave as an example for illustrative purposes only, and is not meant to be a limitation of the present invention.

The bias resistor Rbias may contribute a majority of phase noise of the square wave. In particular, the bias resistor Rbias may contribute noise which has a positive correlation with the resistance of the bias resistor Rbias. For example, the higher the resistance of the bias resistor Rbias, the higher the noise is generated. In contrast, signal power of the sinusoidal wave has a negative correlation with the resistance of the bias resistor Rbias. For example, the higher the resistance of the bias resistor Rbias, the higher the signal power of the sinusoidal wave (i.e. the lower the resistance of the bias resistor Rbias, the more the loss of the sinusoidal wave is caused). Thus, there is a trade-off between loss and noise, and the present invention aims at breaking this trade-off.

In detail, as the quality factor of the crystal oscillator core circuit <NUM> is high enough, the thermal noise from the bias resistor Rbias will not greatly impact a signal-to-noise ratio (SNR) of the sinusoidal wave on the output terminal of the crystal oscillator core circuit <NUM>. For example, the crystal oscillator core circuit <NUM> can filter out most of the noise caused by the bias resistor Rbias at a certain frequency offset such as <NUM> kilo Hertz (kHz) relative to the oscillation frequency of the sinusoidal wave. Based on the description above, even though the bias resistor Rbias contributes noise, the phase noise of the sinusoidal wave can be small, such as -<NUM> decibels relative to the carrier in one Hertz bandwidth (dBc/Hz). The phase noise on the output terminal OUT of the square wave buffer may be high (e.g. -165dBc/Hz), however.

In order to better understand how the noise of the bias resistor Rbias is introduced into the square wave on the output terminal OUT of the square wave buffer <NUM>, please refer to <FIG>. If the bias resistor Rbias does not contributes noise, the sinusoidal wave may be carried on a constant level of VB as illustrated by the waveform labeled "XO Out1" (e.g. a <NUM> Mega Hertz (MHz) sinusoidal wave may regularly vary up and down based on the constant level of VB), and the pulse width of the square wave may be constant, as illustrated by the waveform labeled "NBUF Out1". By comparison, if the bias resistor Rbias contributes noise (e.g. which may be modeled as a <NUM> bias noise source), the sinusoidal wave may be carried on a varying level VB+ΔV as illustrated by the waveform labeled "XO Out2" (e.g. a <NUM> sinusoidal wave may vary up and down based on a time-varying level of a <NUM> bias noise). Thanks to the characteristics brought from the high quality factor of the crystal oscillator core circuit <NUM>, phase noise of the sinusoidal wave is not significantly increased when the noise of the bias resistor Rbias is considered. For the square wave, the timing of state transition (e.g. rising edges and falling edges) may be significantly impacted by voltage level variation on the input terminal of the square wave buffer, and the pulse width of the square wave may be time-varying as illustrated by the portions being circled (e.g. time-varying phase shift Δt) on the waveform labeled "NBUF Out2", which results the phase noise of the square wave on the output terminal OUT of the square wave buffer <NUM>. As shown in the bottommost of <FIG>, the waveform depicted by thin lines represent the output of the square wave buffer <NUM> without considering the noise of the bias resistor (which has a constant pulse width), and the waveform depicted by bold lines represent the output of the square wave buffer <NUM> with considering the noise of the bias resistor (which has a time-varying pulse width), where difference between these two waveform may be illustrated by the time-varying phase shift Δt, which may be regarded as the phase noise mentioned above.

<FIG> is a diagram illustrating a crystal oscillator <NUM>. In addition to the crystal oscillator core circuit <NUM>, the DC bias circuit <NUM>, the bias resistor Rbias and the square wave buffer <NUM>, the crystal oscillator <NUM> may further comprise a phase noise reduction circuit <NUM>. The phase noise reduction circuit <NUM> is coupled to the output terminal of the crystal oscillator core circuit <NUM>, and may be configured to generate a reset signal comprising at least one reset pulse (e.g. one or more pulses, which may be collectively referred to as the reset pulse) for resetting the bias voltage (e.g. resetting resistor noise on the bias voltage, such as the noise contributed by the bias resistor Rbias) of the sinusoidal wave (e.g. by providing an alternating current (AC) ground path for the resistor noise on the bias voltage). More particularly, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave, where the zero-crossing point of the sinusoidal wave may represents the time point at which the sinusoidal wave varies across the level of the DC bias voltage VB. By simulation, it can be noted that the position of the reset pulse (e.g. the timing of the reset pulse relative to the phase of the sinusoidal wave) will not greatly impact the improvement of the phase noise reduction (i.e. the position of the reset pulse is not critical, and different positions of the reset pulse can obtain similar improvement), so the reset pulse can be at the zero-crossing point or peaking of the sinusoidal wave output, and complicated calibration circuits regarding the timing of the reset pulse are not required.

As shown in <FIG>, the phase noise reduction circuit <NUM> may comprise a reset switch 180SW coupled to the output terminal of the crystal oscillator core circuit <NUM>, and may be controlled by the reset signal. In addition, the phase noise reduction circuit <NUM> may further comprise a pulse generator <NUM> configured to generate the reset signal. The reset switch may be turned on in response to the reset pulse, to provide an AC ground path for the resistor noise on the bias voltage to remove the noise on the bias voltage, and thereby reset the bias voltage of the sinusoidal wave to a reset level. For example, the reset switch 180SW may be coupled across the bias resistor Rbias, and when the reset switch is turned on, the noise generated by the bias resistor Rbias may be reset, and the varying bias voltage level of the sinusoidal wave can be pulled back to the original voltage level of the DC bias voltage VB.

In order to better understand how the phase noise reduction circuit <NUM> solves the problem of the phase noise caused by the bias resistor Rbias, please refer to <FIG>. As shown in the upper-half portion of <FIG>, the waveforms labeled "XO Out2" and "NBUF Out2" represent the sinusoidal wave on the output terminal of the crystal oscillator core circuit <NUM> and the square wave on the output terminal of the square wave buffer <NUM> without using the proposed noise reset pulse (e.g. the phase noise reduction circuit <NUM> is disabled and the reset switch 180SW is always turned off); and as shown in the lower half-portion of <FIG>, the waveforms labeled "XO Out3" and "NBUF Out3" represent the sinusoidal wave on the output terminal of the crystal oscillator core circuit <NUM> and the square wave on the output terminal of the square wave buffer <NUM> with using the proposed noise reset pulse (e.g. the phase noise reduction circuit <NUM> is enabled and the pulse generator <NUM> starts to output the reset pulse to periodically turn on the reset switch 180SW). As shown in <FIG>, the sinusoidal wave may vary up and down based on a time varying level VB+ΔV when the phase noise reduction circuit <NUM> is disabled, and the pulse width of the square wave is therefore time-varying, which results phase noise. By comparison, when the phase noise reduction circuit <NUM> is enabled and the pulse generator starts to output the reset pulse to the reset switch 180SW (e.g. periodically output the reset pulse to the reset switch 180SW), the DC bias voltage level of the sinusoidal wave is therefore reset in response to the reset pulse, and the pulse width of the square wave can be substantially constant, or the varying amount of the bias level of the sinusoidal wave can be reduced (e.g. ΔV can be reduced). Thus, the pulse width of the square wave can be constant or substantially constant, and the phase noise is therefore reduced.

It should be noted that both of the resistance of the bias resistor Rbias and an input capacitance on the output terminal of the crystal oscillator core circuit <NUM> can be designed to be quite large, and a large resistance-capacitance (RC) time constant will make the noise of the bias resistor Rbias have insufficient time for greatly change the level of the sinusoidal wave. For example, after the bias voltage level of the sinusoidal wave is reset and the reset switch 180SW is turned off again, the noise of the bias resistor Rbias will not make the bias voltage level of the sinusoidal wave be greatly changed immediately as the time constant is large enough, and when the noise accumulates and makes the bias voltage level of the sinusoidal wave be slightly changed, the next reset pulse can reset the bias voltage level again, as shown in <FIG>. In view of this, the frequency of the reset signal is preferably to be fast enough to better suppress the noise of the bias resistor Rbias, and thereby maintain the bias voltage level of the sinusoidal wave. By simulation, assuming the frequency of the sinusoidal wave is <NUM>, when the frequency of the reset signal is <NUM>, significant improvements on noise related performance can be observed; and when the frequency of the reset signal is <NUM>, the noise related performance can be further improved. Thus, a higher frequency of the reset signal is preferred for obtaining a better noise related performance. The phase noise reduction circuit <NUM> may further comprise a frequency multiplier configured to generate a signal having a frequency that is N times the frequency of the square wave output from the square wave buffer <NUM>, and accordingly make the frequency of the reset signal is N times the frequency of the square wave (e.g. there may be N reset pulses within one cycle of the sinusoidal wave or the square wave), where N may be a positive integer greater than or equal to two. The frequency of the reset signal may be lower than or equal to the frequency of the sinusoidal wave. The reset pulse may be periodically generated, and the frequency of the reset pulse may be any suitable positive value. The reset pulse is not periodically generated, e.g. the pulse generator <NUM> may randomly generate the reset pulse or the occurrence of the reset pulse may be controlled by another controller within the crystal oscillator <NUM>.

In addition to the noise generated by the bias resistor Rbias (which is referred to as the Rbias noise for brevity), there are some factors that may affect the SNR of the sinusoidal wave, such as a turned-on period TON of the reset pulse (e.g. a pulse width of the reset pulse, which indicates a time length of the reset switch 180SW being turned on), a turned-on resistance RON of the reset switch 180SW (e.g. a resistance of the reset switch 180SW in a situation where the reset switch 180SW is turned on), and noise corresponding to the turned-on resistance RON (which is referred to as the RON noise for brevity). By calculation, the SNR may be expressed as follows: <MAT>.

The symbol f represents a variable of the frequency. The symbol Ravg represents an average resistance on the output terminal of the crystal oscillator, which may be further expressed by the turned-on resistance RON, the resistance RBIAS of the bias resistor Rbias, and a parameter a, where a = Torr / Txo, and the symbol TXO represents a cycle period of the sinusoidal wave output from the crystal oscillator core circuit <NUM>. The symbols NRbias(f) and NRon(f) respectively represent the Rbias noise and the RON noise corresponding to the frequency f. Assuming that the Rbias noise NRbias(f) can be reset (e.g. considering different combinations of RON and TON under a condition where the Rbias noise NRbias(f) is able to be reset to the same order), the equation shown above may be further arranged as follows: <MAT>.

The symbol k represents the Boltzmann constant. The symbol T represents the absolute temperature. The symbol CIN represents the input capacitance on the output terminal of the crystal oscillator core circuit <NUM>. The symbol fxo represents the frequency of the sinusoidal wave. As illustrated in the equation shown above, the RON noise NRon(f) may comprise the sample noise and the hold noise. Assuming that the frequency f is much smaller than the frequency fxo of the sinusoidal wave (e.g. when f/fxo is quite close to zero), the equation shown above may be further simplified as follows: <MAT>.

Based on the equation shown above, it can be noted that under a condition where the Rbias noise is reset to the same order, it is preferably to design a smaller a for better SNR. For example, under the condition where the Rbias noise is reset to the same order, when the pulse width of the reset pulse is reduced, the SNR of the sinusoidal wave may be increased. Therefore, utilizing a very short reset pulse (e.g. a reset pulse having an extremely narrow pulse width) to reset the Rbias noise is the optimized design for noise related performance of the crystal oscillator <NUM>. In practice, the small a may be implemented by an exclusive-OR (XOR) logic circuit and a very short delay line, and thereby benefit from small area, low current consumption, and low noise from the delay line. The aforementioned very short delay line may comprise one inverter or a chain of inverters, but the present invention is not limited thereto. It should be noted that the delay provided by the aforementioned very short delay line is not limited to a specific value, any delay that is able to reset the bias voltage level of the sinusoidal wave without significantly degrading the SNR, such as <NUM> picoseconds (ps), <NUM> ps, etc..

<FIG> is a diagram illustrating a crystal oscillator <NUM> according to an embodiment of the present invention, where the crystal oscillator <NUM> may be a modified version or an example of the crystal oscillator <NUM> shown in <FIG>. As shown in <FIG>, the phase noise reduction circuit <NUM> is replaced with a phase noise reduction circuit <NUM> in this embodiment, where the phase noise reduction circuit <NUM> is coupled to the output terminal of the crystal oscillator core circuit <NUM>, and is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave (e.g. peaking of the sinusoidal wave) exceeding a specific voltage range. In this embodiment, the phase noise reduction circuit <NUM> comprises DC bias circuits <NUM> and <NUM>. The DC bias circuit <NUM> is configured to control a DC voltage level Vcal1, and the DC bias circuit <NUM> is configured to control a DC voltage level Vcal2, where the specific voltage range is determined according to the DC voltage levels Vcal1 and Vcal2. Furthermore, the phase noise reduction circuit <NUM> further comprises a first control switch and a second control switch, where the first control switch is coupled between the output terminal of the crystal oscillator core circuit <NUM> and the DC bias circuit <NUM>, and the second control switch is coupled between the output terminal of the crystal oscillator core circuit <NUM> and the DC bias circuit <NUM>. For example, the first control switch is conductive in response to the voltage level of the sinusoidal wave being greater than an upper bound level, and the second control switch is conductive in response to the voltage level of the sinusoidal wave being less than a lower bound level, where the upper bound level and the lower bound level corresponds to the DC voltage levels Vcal1 and Vcal2, respectively.

In this embodiment, the first control switch may comprise a first diode such as a diode D1, and the second control switch may comprise a second diode such as a diode D2. As shown in <FIG>, an anode of the diode D1 may be coupled to the output terminal of the crystal oscillator core circuit <NUM>, and a cathode of the diode D1 may be coupled to the DC bias circuit <NUM>. In addition, an anode of the diode D2 may be coupled to the DC bias circuit <NUM>, and a cathode of the diode D2 may be coupled to the output terminal of the crystal oscillator core circuit <NUM>. In detail, when a voltage difference between the anode and the cathode of the diode D1 is greater than a threshold voltage Vth1 of the diode D1, the diode D1 can be conductive (e.g. the first control switch may be regarded as being turned on); otherwise, the diode D1 cannot be conductive (e.g. the first control switch may be regarded as being turned off). Similarly, when a voltage difference between the anode and the cathode of the diode D2 is greater than a threshold voltage Vth2 of the diode D2, the diode D2 can be conductive (e.g. the second control switch may be regarded as being turned on); otherwise, the diode D2 cannot be conductive (e.g. the second control switch may be regarded as being turned off).

It should be noted that any (e.g. each) of the diodes D1 and D2 is not limited to be implemented by a single diode. For example, any (e.g. each) of the diodes D1 and D2 may be implemented by a cascode structure of diode units, e.g. N diode units connected in series, to obtain a threshold voltage N*Vth, depending on the essential voltage swing of the sinusoidal wave, where Vth may represent the threshold voltage by one diode units, and N may represent the number of diode units being connected in series. For brevity, assume that Vth1 = Vth2 = N*Vth, but the present invention is not limited thereto. In this embodiment, when the voltage level of the sinusoidal wave exceed the upper bound level, the diode D1 is conductive in response to the voltage difference across the diode D1 exceeding the threshold voltage Vth1, and a maximum level of the sinusoidal wave may therefore be clamped to the upper bound level (e.g. Vcal1 + N*Vth) as shown in <FIG>; and when the voltage level of the sinusoidal wave exceed the lower bound level, the diode D2 is conductive in response to the voltage difference across the diode D1 exceeding the threshold voltage Vth2, and a minimum level of the sinusoidal wave may therefore be clamped to the lower bound level (e.g. Vcal2 - N*Vth) as shown in <FIG>. Based on the basic characteristics of diodes, the diode D1 and/or D2 can be automatically turned on by the voltage swing of the sinusoidal wave, and noise reset regarding the DC bias voltage level of the sinusoidal wave can take effect at the maximum level (e.g. wave peaks) and/or the minimum level (e.g. wave troughs) of the sinusoidal wave as illustrated by a reset current (e.g. a current flowing through the node coupled to the output terminal of the crystal oscillator core circuit <NUM>) shown in <FIG>.

In order to guarantee that the DC voltage levels Vcal1 and Vcal2 is set to appropriate levels that are capable of turning on the diodes D1 and/or D2, a calibration flow may be performed to calibrate the DC voltage levels Vcal1 and Vcal2. In the calibration flow, the DC voltage levels Vcal1 and Vcal2 may be respectively set to an initial maximum level and an initial minimum level at the beginning (e.g. at the beginning of the calibration flow or in an initial phase of the crystal oscillator), where the initial maximum level may be the highest voltage level that the DC bias circuit <NUM> is able to provide, and the initial minimum level may be the lowest voltage level that the DC bias circuit <NUM> is able to provide. The DC voltage level Vcal1 may be stepwise decreased, starting from the initial maximum level, to make a maximum level (e.g. the wave peaks) of the sinusoidal wave be able to turn on the first control switch such as the diode D1. The DC voltage level Vcal2 may be stepwise increased, starting from the initial minimum level, to make a minimum level (e.g. the wave troughs) of the sinusoidal wave be able to turn on the second control switch such as the diode D2.

For example, the DC bias circuit <NUM> may control the DC voltage level Vcal1 according to a first calibration code such as a three-bit code, where different values (e.g. candidate values such as <NUM>, <NUM>, , and <NUM>) of the first calibration code may respectively correspond to different values (e.g. candidate values such as Veal <NUM>(<NUM>), Vcal1(<NUM>),. , and Vcal1(<NUM>), where Vcal1(<NUM>) > Vcal1(<NUM>) >. > Vcal1(<NUM>)) of the DC voltage level Vcal1. When the first calibration code is <NUM>, the DC bias circuit <NUM> may control the DC voltage level Vcal1 to be a highest voltage level (e.g. <NUM>. 9V) within a tuning range of the DC voltage level Vcal1, and when the first calibration code is <NUM>, the DC bias circuit <NUM> may control the DC voltage level Vcal1 to be a lowest voltage level (e.g. 0V) within the tuning range of the DC voltage level Vcal1, where the rest values of the first calibration code may be deduced by analogy, e.g. {Vcal1(<NUM>), Vcal1(<NUM>), Vcal1(<NUM>), Vcal1(<NUM>),Vcal1(<NUM>),Vcal1(<NUM>), Vcal1(<NUM>), Vcal1(<NUM>)} may be <NUM>. 79V, <NUM>. 68V, <NUM>. 45V, <NUM>. 34V, <NUM>. 22V, <NUM>. The first calibration code may be set to <NUM> at the beginning, and the DC voltage level Vcal1 corresponding to this value of the first calibration code is not able to make the condition of turning on the diode D1 occur. The first calibration code is therefore stepwise switched to <NUM>, <NUM>, <NUM>, etc., to find at least one value of the first calibration code, which is able to make the condition of turning on the diode D1 occur. Similarly, the DC bias circuit <NUM> may control the DC voltage level Vcal2 according to a second calibration code such as a three-bit code, where different values (e.g. candidate values such as <NUM>, <NUM>,. , and <NUM>) of the second calibration code may respectively correspond to different values (e.g. candidate values such as Vcal2(<NUM>), Vcal2(<NUM>),. , and Vcal2(<NUM>), where Vcal2(<NUM>) < Vcal2(<NUM>) <. < Vcal2(<NUM>)) of the DC voltage level Vcal2. When the second calibration code is <NUM>, the DC bias circuit <NUM> may control the DC voltage level Vcal2 to be a lowest voltage level (e.g. 0V) within a tuning range of the DC voltage level Vcal2, and when the second calibration code is <NUM>, the DC bias circuit <NUM> may control the DC voltage level Vcal2 to be a highest voltage level (e.g. <NUM>. 9V) within the tuning range of the DC voltage level Vcal2, where the rest values of the second calibration code may be deduced by analogy, e.g. {Vcal2(<NUM>), Vcal2(<NUM>), Vcal2(<NUM>), Vcal2(<NUM>),Vcal2(<NUM>),Vcal2(<NUM>), Vcal2(<NUM>), Vcal2(<NUM>)} may be {0V, <NUM>. 11V, <NUM>. 22V, <NUM>. 34V, <NUM>. 45V, <NUM>. 68V, <NUM>. 79V, <NUM>. The second calibration code may be set to <NUM> at the beginning, and the DC voltage level Vcal2 corresponding to this value of the second calibration code is not able to make the condition of turning on the diode D2 occur. The second calibration code is therefore stepwise switched to <NUM>, <NUM>, <NUM>, etc., to find at least one value of the second calibration code, which is able to make the condition of turning on the diode D2 occur.

In one embodiment, the phase noise reduction circuit <NUM> may further comprise a peak detector <NUM> coupled to the output terminal of the crystal oscillator core circuit <NUM>, where the peak detector <NUM> may be configured to detect a swing of the sinusoidal wave to generate a detection result (e.g. detecting a peak value of the sinusoidal wave to obtain information related to the swing), and the DC bias circuits <NUM> and <NUM> may respectively control the DC voltage levels Vcal1 and Vcal2 according to the detection result. For example, the peak detector <NUM> may output a DC voltage according to the swing (or the peak value) of the sinusoidal wave, where this DC voltage may be configured to determine whether the swing of the sinusoidal wave is changed (e.g. reduced), but the present invention is not limited thereto. Assume that when the swing of the sinusoidal wave is ±1000mV, the DC voltage output from the peak detector <NUM> may be 500mV, and when the swing of the sinusoidal wave is ±900mV, the DC voltage output from the peak detector <NUM> may be 450mV It should be noted that those skilled in this art should understand detailed implementation of the peak detector <NUM> based on the descriptions mentioned above, and related details are omitted here for brevity.

In addition, the current source within the crystal oscillator core circuit <NUM> may comprise one or more current units connected in parallel, and the one or more current units may be configured to provide a bias current of the crystal oscillator core circuit <NUM> to control the swing of the sinusoidal wave. For example, the bias current may depend on the number of current units being enabled in the current source, and the swing of the sinusoidal wave depends on the bias current. In one embodiment, the crystal oscillator core circuit <NUM> may further comprise a current calibration (ACAL) circuit <NUM> coupled to the one or more current units, and the number of current units being enabled in the current source depends on a calibration code output from the ACAL circuit <NUM>. Thus, the ACAL circuit <NUM> can control the swing of the sinusoidal wave by controlling the calibration code. In this embodiment, the ACAL circuit <NUM> may calibrate the current source by a speed/frequency of the square wave on the output terminal OUT (e.g. modifying the calibration code one time in each cycle of the square wave during the calibration regarding the current source), but the present invention is not limited thereto.

In detail, at the beginning of the calibration regarding the DC voltage levels Vcal1 and Vcal2, the DC voltage level Vcal1 is set to the initial maximum level and the DC voltage level Vcal2 is set to the initial minimum level. Before any (e.g. each) of the DC voltage levels Vcal1 and Vcal2 is stepwise modified as mentioned above, the ACAL circuit <NUM> may calibrate the bias current, to make the swing of the sinusoidal wave fall into a range between a tunable maximum level (e.g. an initial level of Vcal1 + N*Vth) related to the initial maximum level and a tunable minimum level (e.g. an initial level of Vcal2 - N*Vth) related to the initial minimum level. Thus, the calibration regarding the DC voltage levels Vcal1 and Vcal2 is guaranteed to be started from a condition where the first control switch and the second control switch (e.g. the diode D1 and D2) are unable to be conductive in response to the maximum level and the minimum level of the sinusoidal wave. Then, any (e.g. each) of the DC voltage levels Vcal1 and Vcal2 may be stepwise modified according to the detection result (e.g. the DC voltage output from the peak detector <NUM>), to make the first control switch such as the diode D1 be able to be conductive in response to the maximum level (e.g. the wave peaks) of the sinusoidal wave, and/or to make the second control switch such as the diode D2 be able to be conductive in response to the minimum level (e.g. the wave troughs) of the sinusoidal wave. For example, assume that the DC voltage output from the peak detector <NUM> is 500mV at the beginning of the calibration regarding the DC voltage levels Vcal1 and Vcal2. After the DC voltage level Vcal1 is decreased by one step (e.g. switching the first calibration code from <NUM> to <NUM>) and/or the DC voltage level Vcal2 is increased by one step (e.g. switching the second calibration code from <NUM> to <NUM>), if the DC voltage output from the peak detector <NUM> is still 500mV, the DC voltage level Vcal1 may be further decreased by another step (e.g. switching the first calibration code from <NUM> to <NUM>) and/or the DC voltage level Vcal2 may be further increased by another step (e.g. switching the second calibration code from <NUM> to <NUM>); and if the DC voltage output from the peak detector <NUM> becomes 480mV, which means the swing of the sinusoidal wave is reduced because the noise reset regarding the DC bias voltage level of the sinusoidal wave takes effect, the current values (e.g. the latest values) of the first calibration code and the second calibration code may be the final values of the first calibration code and the second calibration code, respectively, and the calibration regarding the DC voltage levels Vcal1 and Vcal2 is therefore completed.

Note that the tuning ranges of the values of voltage levels and calibration codes mentioned above are for illustrative purposes only, and are not meant to be a limitation of the present invention. For example, the number of bits of the first calibration code and the second calibration code may vary. For example, the turning range of the DC voltage level Vcal1 may be the same as the tuning range of the DC voltage level Vcal2. In another example, the tuning range of the DC voltage level V call may be different from the tuning range of the DC voltage level Vcal2. In addition, the calibration of the DC voltage level Vcal1 and the calibration of the DC voltage level Vcal2 do not have to be performed concurrently. For example, the calibration of the DC voltage level Vcal2 may be performed after the calibration of the DC voltage level Vcal1 is completed. In another example, the calibration of the DC voltage level Vcal1 may be performed after the calibration of the DC voltage level Vcal2 is completed. Furthermore, some embodiments may perform calibration on one of the DC voltage levels Vcal1 and Vcal2 only. In practice, it is preferably to calibrate both of the DC voltage levels Vcal1 and Vcal2 for obtaining a symmetric waveform of the sinusoidal wave. For example, the DC voltage levels Vcal1 and Vcal2 may be calibrated concurrently with aid of the same calibration code (e.g. the first calibration code may be equal to the second calibration code), but the present invention is not limited thereto.

For better comprehension, please refer to <FIG>, which illustrates a working flow of the calibration regarding the DC voltage levels Vcal1 and Vcal2 shown in <FIG> according to an embodiment of the present invention. For example, a calibration control circuit within the phase noise reduction circuit <NUM> may utilize multiple control signals for controlling the working flow of the calibration, but the present invention is not limited thereto. In some embodiments, one or more steps may be added, deleted or modified in the working flow shown in <FIG>. In addition, if a same result may be obtained, these steps do not have to be executed in the exact order shown in <FIG>.

In Step <NUM>, when the crystal oscillator <NUM> is enabled, the working flow of the calibration starts.

In Step <NUM>, the calibration control circuit controls the DC bias circuit <NUM> to set the DC voltage level Vcal1 to maximum (e.g. the initial maximum level) and control the DC bias circuit <NUM> to set the DC voltage level Vcal2 to minimum (e.g. the initial minimum level).

In Step <NUM>, the calibration control circuit controls the peak detector <NUM> to detect the swing of the sinusoidal wave (which may be referred to as "PD detection"). Assume that the detected swing Vswing of the sinusoidal wave in this step is Vp (e.g. Vswing = Vp).

In Step <NUM>, the calibration control circuit controls the DC bias circuit <NUM> to decrease the DC voltage level V call by one step, and control the DC bias circuit <NUM> to increase the DC voltage level Vcal2 by one step.

In Step <NUM>, the calibration control circuit controls the peak detector <NUM> to detect the swing of the sinusoidal wave again. Assume that the detected swing Vswing of the sinusoidal wave in this step is Vdet (e.g. Vswing = Vdet).

In Step <NUM>, the calibration control circuit determines whether (Vp - Vdet) meets a target (e.g. whether (Vp - Vdet) is greater than a predetermine voltage difference). If the determination result is "Yes", the working flow proceeds with Step <NUM>; and if the determination result is "No", the working flow proceeds with Step <NUM>.

In Step <NUM>, the calibration control circuit ends the calibration.

It should be noted that any (e.g. each) of the diodes D1 and D2 does not have to be implemented by typical diodes. For example, any device comprising at least one P-N junction may be modified to implement the diodes D1 and D2. In some embodiments, the diodes D1 may be implemented by a P-type transistor, where a drain and a gate of the P-type transistor may be coupled to each other, to configure this P-type transistor as a diode-connected transistor, which has similar characteristics as typical diodes. In some embodiments, the diodes D2 may be implemented by an N-type transistor, where a drain and a gate of the N-type transistor may be coupled to each other, to configure this N-type transistor as a diode-connected transistor, which has similar characteristics as typical diodes. Those skilled in this art should understand how to adopt diode-connected transistors in the architecture shown in <FIG> according to the above descriptions, and related details are omitted here for brevity.

<FIG> is a diagram illustrating a crystal oscillator <NUM> according to an embodiment of the present invention, where the crystal oscillator <NUM> may be a modified version or an example of the crystal oscillator <NUM> shown in <FIG>. For example, the phase noise reduction circuit <NUM> is replaced with a phase noise reduction circuit <NUM> as shown in <FIG>, and more particularly, the diodes D1 and D2 are replaced with a P-type transistor M1 and an N-type transistor M2, respectively. As shown in <FIG>, a gate terminal of the P-type transistor M1 is coupled to the DC bias circuit <NUM> for receiving the DC voltage level Vcal1, a drain terminal of the P-type transistor M1 is configured to receive a DC voltage level VB1, and a source terminal of the P-type transistor M1 is coupled to the output terminal of the crystal oscillator core circuit <NUM>. In addition, a gate terminal of the N-type transistor M2 is coupled to the DC bias circuit <NUM> for receiving the DC voltage level Vcal2, a drain terminal of the N-type transistor M2 is configured to receive a DC voltage level VB2, and a source terminal of the N-type transistor M2 is coupled to the output terminal of the crystal oscillator core circuit <NUM>. Based on this architecture, when the voltage level of the sinusoidal wave (e.g. the maximum level such as the wave peaks of the sinusoidal wave) exceeds the upper bound level and thereby makes a difference between the voltage level of the sinusoidal wave and the DC voltage level Vcal1 be greater than a threshold voltage (e.g. making Vsin - Vcal1 > |Vthp|, where Vsin represents an instant level of the sinusoidal wave, Vthp represents a threshold voltage of the P-type transistor M1, and |Vthp| represents an absolute value of Vthp), the P-type transistor M1 may be turned on and the DC bias voltage level of the sinusoidal wave may be reset to VB1. When the voltage level of the sinusoidal wave (e.g. the minimum level such as the wave troughs of the sinusoidal wave) exceeds the lower bound level and thereby makes a difference between the DC voltage level Vcal2 and the voltage level of the sinusoidal wave be greater than a threshold voltage (e.g. making Vcal2 - Vsin > |Vthn|, where Vthn represents a threshold voltage of the N-type transistor M2, and |Vthn| represents an absolute value of Vthn), the N-type transistor M2 may be turned on and the DC bias voltage level of the sinusoidal wave may be reset to VB2.

In some embodiments, the DC voltage levels VB1 and VB2 may be the same. In some embodiments, the DC voltage levels VB1 and VB2 may be different. In some embodiments, both of the DC voltage levels VB1 and VB2 may be the same as the DC voltage level of the DC bias voltage VB provided by the DC bias circuit <NUM>. In some embodiments, at least one of DC voltage levels VB1 and VB2 (e.g. one of them or both of them) may be different from the DC voltage level of the DC bias voltage VB provided by the DC bias circuit <NUM>. As long as the DC voltage levels VB1 and VB2 are clean and constant voltage levels (e.g. each of the DC voltage levels VB1 and VB2 has extremely low noise), the DC voltage levels VB1 and VB2 are not limited to specific voltage levels. In addition, the working flow of the calibration regarding the DC voltage levels Vcal1 and Vcal2 shown in <FIG> can also be adopted in the crystal oscillator <NUM> shown in <FIG>. For brevity, similar descriptions related to the calibration regarding the DC voltage levels Vcal1 and Vcal2 are not repeated here.

To summarize, please refer to <FIG>, which illustrates a working flow of a phase noise reduction method of a crystal oscillator (e.g. the crystal oscillator <NUM> or the crystal oscillator <NUM>) according to an embodiment of the present invention. In some embodiments, one or more steps may be added, deleted or modified in the working flow shown in <FIG>. In addition, if a same result may be obtained, these steps do not have to be executed in the exact order shown in <FIG>.

In Step <NUM>, the crystal oscillator may generate a sinusoidal wave by a crystal oscillator core circuit (e.g. the crystal oscillator core circuit <NUM>) of the crystal oscillator.

In Step <NUM>, the crystal oscillator may provide a first voltage level (e.g. the level of the DC bias voltage VB) to be a bias voltage of the sinusoidal wave by a first bias circuit (e.g. the DC bias circuit <NUM>) of the crystal oscillator.

In Step <NUM>, the crystal oscillator reset the bias voltage of the sinusoidal wave by a phase noise reduction circuit (e.g. the phase noise reduction circuit <NUM> shown in <FIG> or the phase noise reduction circuit <NUM> shown in <FIG>) of the crystal oscillator in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

As each of the diode/diode-like components (e.g. the diodes D1/D2 or the transistors M1/M2) utilized in the present invention has the characteristic of being automatically turned on in response to a voltage across terminals of a diode/diode-like component exceeding a threshold of this diode/diode-like component, the noise reset regarding the DC bias voltage level of the sinusoidal wave can take effect at least at the time points of wave peaks or wave troughs of the sinusoidal wave. Thus, the present invention can improve the phase noise related performance without introducing any side effect or in a way that is less likely to introduce side effects.

Claim 1:
A crystal oscillator (<NUM>, <NUM>), comprising:
a crystal oscillator core circuit (<NUM>), configured to generate a sinusoidal wave;
a first bias circuit (<NUM>), coupled to an output terminal of the crystal oscillator core circuit (<NUM>), configured to provide a first voltage level to be a bias voltage of the sinusoidal wave; and
a phase noise reduction circuit (<NUM>, <NUM>), coupled to the output terminal of the crystal oscillator core circuit (<NUM>), configured to reset noise of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range, the phase noise reduction circuit (<NUM>, <NUM>) comprising:
a second bias circuit (<NUM>), configured to control a second voltage level;
a third bias circuit (<NUM>), configured to control a third voltage level;
a first control switch (D1, M1), coupled between the output terminal of the crystal oscillator core circuit (<NUM>) and the second bias circuit (<NUM>), configured to be conductive in response to the voltage level of the sinusoidal wave being greater than an upper bound level; and
a second control switch (D2, M2), coupled between the output terminal of the crystal oscillator core circuit (<NUM>) and the third bias circuit (<NUM>), configured to be conductive in response to the voltage level of the sinusoidal wave being less than a lower bound level,
wherein the specific voltage range is determined according to the second voltage level and the third voltage level, and
wherein the upper bound level and the lower bound level correspond to the second voltage level and the third voltage level, respectively.