Patent Description:
Various embodiments of the invention relate to controlling power to digital integrated circuits with an intention of avoiding damage to the integrated circuits as a result of a sudden loss of the source power.

Most compute platforms are powered by multiple voltage rails that are properly sequenced during startup and shutdown by programmable devices such as field programmable gate arrays (FPGAs). Under normal circumstances these devices ensure that various voltage regulators (VRs) on the platform are turned on/off in correct sequence to prevent incorrect voltage relationships from damaging sensitive loads such as processors, memories, etc..

However, such a safeguard may fail to protect when there is a sudden loss of the platform power source that powers the VRs. This event may also remove power from the FPGA or other circuitry that controls the shutdown. The rate of voltage ramp down of each rail may then depend on the size of the storage capacitor at the output of that VR and the load being placed on that rail. For example, if this occurrence caused the <NUM> volt rail to drop lower than the <NUM> volt rail, even briefly, this might result in a damaging reverse voltage potential across parts of the circuitry. <CIT> relates to a power supply apparatus that supplies an operating voltage to a microcomputer. The power supply apparatus is to reliably reset the microcomputer before operation becomes unstable when an external power supply voltage decreases due to interruption. An externally supplied power supply voltage is stepped down to generate an intermediate voltage. The intermediate voltage is stepped down to generate an operating voltage for a micro-computer core. The intermediate voltage is stepped down to generate an operating voltage for an I/O port. When the intermediate voltage becomes lower than a reset determining voltage, the power supply apparatus outputs a reset signal to the microcomputer. When the power supply voltage decreases, the microcomputer can reliably reset and the core can be prevented from operating erratically before the voltage becomes lower than a minimum core operating voltage. <CIT> relates to an energy supply system for a multi-voltage electronic device.

Some embodiments of the invention may be better understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:.

In the following description, numerous specific details are set forth. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

References to "one embodiment", "an embodiment", "example embodiment", "various embodiments", etc., indicate that the embodiment(s) of the invention so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some or all of the features described for other embodiments.

As used in the claims, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

<FIG> shows a circuit to produce multiple voltage rails, without various improvements of the invention. In the illustrated circuit, a source voltage VIN powers two voltage regulators <NUM> and <NUM>, which provide power to a device <NUM>. NOTE: as used in this document, the term 'source voltage' refers to the common input voltage for the multiple voltage regulators. An example of the indicated source voltage is shown as +12V DC, but other values may be used. Only two voltage regulators are shown, with VR<NUM> being represented as outputing the higher voltage VH, and VR<NUM> outputing the lower voltage VL. Other numbers of voltage regulators may be used, but these two serve illustrate one example.

In the illustrated embodiment, inductors L<NUM> and L<NUM> are shown at the output of voltage regulators VR<NUM> and VR<NUM>, respectively, and may be used to smooth out ripples in those two outputs. Other embodiments may not have these inductors. Capacitors C<NUM> and C<NUM> are shown at the output of the inductors (or alternately at the outputs of the voltage regulators), and may be used to further smooth out voltages VH and VL, and to provide charge storage capacity on those outputs. These voltage may then provided to the loads. In this example, the loads are in a device <NUM>, which is shown as a central processing unit (CPU) or dual in-line memory module (DIMM), but other devices may be used.

<FIG> shows a diagram of voltage rails after a loss of source power to the circuit of <FIG>. The diagram shows VH and VL at constant levels until time t<NUM>, at which point source voltage VIN may be lost. This in turn may cause VH and VL to begin dropping as shown. In this particular example, VH may drop faster than VL until is drops lower than VL at time t<NUM> and beyond. This reverse-voltage condition may cause damage to sensitive circuit components in the load.

<FIG> shows a circuit to produce multiple voltage rails, with protective circuitry according to an embodiment of the invention. The general components VR<NUM> and VR<NUM>, L<NUM> and L<NUM>, C<NUM>, and C<NUM>, and CPU or DIMM may be as shown in <FIG>. However, two additional circuits have been added. Power Loss Trigger Generator Circuit <NUM> may be used to detect a loss of source voltage VIN, and use that detection to generate an Event Trigger Signal. The event trigger signal in this case may be a signal to the Sequence Control Circuit <NUM> indicating that source voltage VIN has been lost, and this signal may be then be used to activate the Sequence Control Circuit <NUM>.

Although a loss if VIN may cause a loss of input power VIN<NUM> to VR<NUM> and VIN<NUM> to VR<NUM>, two components may be added to cause VIN<NUM> and VIN<NUM> to react differently. Capacitor Chold-up may cause VIN<NUM> to drop more slowly than VIN<NUM>. Without more, this might keep VH from dropping as quickly as it did in <FIG>. Without a comparable hold-up capacitor at the input of VR2, the amount of time it takes VH to drop below VL may be longer than in <FIG>. However, VH may still evenually drop below VL, so the problem may be delayed but not prevented.

In addition to the capacitor Chold-up, diode Dhold-up may be used to keep VIN<NUM> from draining down into the input of VR<NUM>,which could have indeterminate effects on the relationship of VH and VL. Dhold-up and resistor R<NUM> may also be used to maintain the proper voltage relationships on switch SW1 so that once switch SW1 closes, it will stay closed as long as VIN is missing.

While the Power Loss Trigger Generator Circuit <NUM> may detect a loss of source voltage and generate a trigger signal in response, additional circuitry may be needed to prevent VH from dropping below VL. This additional circuitry may be in the form of Sequnce Control Circuit <NUM>. In the illustrated embodiment, Sequence Control Circuit <NUM> is connected between high rail VH and low rail VL. Sequence Control Circuit <NUM> may be as simple as a resistor R<NUM> in series with a switch SW<NUM>. , but some embodiments may use other components. For example, another embodiment may have a Schottky diode in series with the resistor.

In one embodiment, switch SW2 may be open during normal operation, but closed when it receives the Event Trigger signal. This may effectively couple the VH rail to the VL rail immediately, through resistor R<NUM>. Resistor R2 may prevent two different voltages from being completely shorted together, but current may flow from C<NUM> to C<NUM> between the two rails through R2.

Because of this current flow, eventually voltage VH and VL may reach a state of equilibrium and be at the same voltage level. At this point, the flow of current through R2 may stop, which effectively shorts VH to VL. By shorting VH and VL together, VH is prevented from dropping below VL, and a potentially damaging reverse voltage condition may be prevented. After VH and VL reach equilibrium, capacitors C<NUM> and C<NUM> may continue to drain together into their respective loads until there is no charge left in them.

Although the Event Trigger Signal may be connected directly to the gate of switch SW2, in some embodiments it may be coupled indirectly to SW2 through logic <NUM>. Logic <NUM> may serve various purposes, such as delaying the Event Trigger Signal from reaching the Sequence Control Circuit too quickly. This delay might serve various purposes, such as but not limited to allowing a short glitch at VIN from starting the Sequence Control process if the power outage is too short for its effects to feed through the voltage regulators.

<FIG> shows a diagram of voltage rails after a loss of source power to the circuit of <FIG>, according to an embodiment of the invention. The diagram shows VH and VL at constant levels until time t<NUM>. Time t<NUM> may be the point at which switch SW2 in <FIG> closes, coupling rail VH to VL through resistor R2. Since VH and VL are now coupled together through R2, capacitors C<NUM> and C<NUM> may cause the higher voltage level VH to pull up the voltage level VL as shown until they reach equilibrium voltage level VX at time t<NUM>. The time it takes to from t<NUM> to t<NUM> may depend the storage capacitance of C<NUM> and C<NUM>, the resistance in resistor R2, and the loads placed on VH and VL, respectively. R2 may be sized to make sure that VX does not exceed the maximum voltage of any circuitry powered by VL.

From time t<NUM> forward, VH and VL may continue to drop in unison until they reach zero volts. In this manner, VH is prevented from dropping below VL throught the powder-down procces. Beyond t<NUM>, with a voltage differential of zero volts, the circuitry of the load may essentially be in the same condition as it is when it has no voltage applied to it, so there should be no problem with damaging voltage differences or with having enough voltage to operate the circuitry in an unknown state.

Between t<NUM> and t<NUM>, the difference between VH and VL may drop rapidly, causing the circuitry of the load to see a rapidly decreasing voltage at its power inputs. Since there will not be any revers voltage condition at these inputs, there should not be any damaging voltage conditions.

Depending on the particular circuitry within the load, having a less-than-desirable voltage across the power inputs od the load might cause unpredictable logic operations within the load circuitry for the brief time of t<NUM> to t<NUM>. Provided these operations do not cause any stored conditions that carry over through the power outage, this should not cause any problems, since the subsequent power-up may reset all startup conditions in their desired states.

<FIG> shows a flow diagram of a method of operations in the circuitry of <FIG>. In flow diagram <NUM>, at <NUM> a first circuit may detect a loss of the source voltage that is converted to multiple voltage rails through multiple voltage regulators. At <NUM> the first circuit may output a signal indicating the source voltage has been lost. At <NUM> the first may be sent to a second circuit. In some embodiments the signal may be sent directly. In other embodiments the signal may go through other components before it reaches the second circuit.

At <NUM> the second circuit may close a switch to connect the first voltage rail to the second voltage rail through a resistor. Due to the resistor connection, at <NUM> a capacitor connected to the higher voltage rail may discharge into the higher voltage load and may also discharge into a capacitor on the lower voltage rail until both capacitors have the same voltage. At <NUM>, both capacitors may discharge into their respective loads, with their respctive voltages remaining equal. When both capacitors are fully discharged , power-down of the voltage rails may be complete.

So far, the various embodiments have been described in terms of two VRs producing two output voltages. However, the same principles may be applied with more than two. <FIG> show an implementation that extends the same basic principles to more VRs. In this embodiment, VIN may provide a source voltage for four VRs, labeled VR<NUM>, VR<NUM>, VR<NUM>, and VR<NUM>, which provide four different voltages to Load <NUM>, Load <NUM>, Load <NUM>, and Load <NUM>, respectively. In the illustrated embodiment, it is assumed that the output voltage from VR<NUM> is greater than the output voltage from VR<NUM>, which is greater than the output voltage of VR<NUM>, which is greater than the output voltage of VR<NUM>. However, other configurations may also be used.

The various Sequence Control circuits (see <FIG>) are indicated as SCXY, where x and y indicate the two VRs whose outputs are connected by that particular Sequence Control circuit. The specific outputs that are to be connected in this way may depend on the relative needs of the various loads.

Claim 1:
A multiple-voltage producing circuit to produce multiple voltage rails, comprising:
a first voltage regulator (<NUM>) to convert an input voltage to a first output voltage at a first output;
a second voltage regulator (<NUM>) to convert the input voltage to a second output voltage at a second output, wherein the second output voltage is to be less than the first output voltage prior to a first time;
a detection circuit (<NUM>) to detect a loss of the input voltage and to generate a signal in response to said loss at the first time; and characterised by
a sequence control circuit (<NUM>) connected between the first output and the second output;
wherein the sequence control circuit (<NUM>) includes a switch to connect the first output to the second output through a resistor, resultant to said signal.