Patent Description:
<CIT> describes a method of power gating a memory and a corresponding memory system that comprises one or more memories operating at a first clock; a processor operating at a second clock and adapted to access the memories; a control logic coupled to the memories and the processor, adapted to: activate, during a rising edge of a second clock, the memories from a sleep mode; and after a cycle of the first clock, assert a power-gating signal, thereby returning the memories to the sleep mode, where a frequency of the second clock is less than a frequency of the first clock. <CIT> relates to an integrated circuit having power gated blocks and a power manager circuit and aims to balance the delay to enable the power gated blocks and the power supply noise. The power manager circuit may generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. <CIT> relates to systems and methods for minimizing static leakage of an integrated circuit. A leakage manager system is coupled to a power island manager that includes a logic gate. The logic gate may be powered down to a "sleep mode" in conjunction with a sleep transistor. To minimize static leakage of the logic gate, the leakage manager system generates a negative voltage applied to the sleep transistor.

The present invention provides an apparatus as defined in appended claim <NUM>.

A further understanding of the nature and advantages of particular embodiments may be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.

The following detailed description illustrates a few exemplary embodiments in further detail to enable one of skill in the art to practice such embodiments. The described examples are provided for illustrative purposes and are not intended to limit the scope of the invention. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the described embodiments. It will be apparent to one skilled in the art, however, that other embodiments of the present invention may be practiced without some of these specific details.

Several embodiments are described herein, and while various features are ascribed to different embodiments, it should be appreciated that the features described with respect to one embodiment may be incorporated with other embodiments as well. By the same token, however, no single feature or features of any described embodiment should be considered essential to every embodiment of the invention, as other embodiments of the invention may omit such features.

Unless otherwise indicated, all numbers herein used to express quantities, dimensions, and so forth, should be understood as being modified in all instances by the term "about. " In this application, the use of the singular includes the plural unless specifically stated otherwise, and use of the terms "and" and "or" means "and/or" unless otherwise indicated. Moreover, the use of the term "including," as well as other forms, such as "includes" and "included," should be considered non-exclusive. Also, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components that comprise more than one unit, unless specifically stated otherwise.

<FIG> illustrates a power gating circuit <NUM>, according to various embodiments. The power gating circuit <NUM> includes a timeout control circuit <NUM>, header switch <NUM>, power gated circuit <NUM>, footer switch <NUM>, enable signal (e. clock enable (Cke)) input <NUM>, first supply voltage (VDD) <NUM>, and second supply voltage (Vss) <NUM>. In various embodiments, the power gated circuit <NUM> may include transistors that have relatively low threshold voltages (e.g., <NUM>. 4V or less). These low threshold voltage transistors are often susceptible to relatively high leakage currents during, for example, standby operation due to the supply voltages (e.g., Vdd and VSS) provided to the circuit. According to the present invention, the timeout control circuit <NUM> is communicatively coupled to one or more power gating switches. Power gating switches may be configured to couple the power gated circuit <NUM> to at least one of a first power supply or a second power supply. The power gating switches may be configured to be activated in a conductive state, or deactivated in a non-conductive state. Power gating switches may include a header switch <NUM>, footer switch <NUM>, or both. For example, the timeout control circuit <NUM> may be communicatively coupled to the header switch <NUM>, footer switch <NUM>, or both. The header switch <NUM> may in turn couple the power gated circuit <NUM> to a first power supply line, VDD <NUM>. The footer switch <NUM> may be used alternatively, or in addition to, the header switch <NUM>. The footer switch <NUM> may be configured to couple the power gated circuit <NUM> to a second power supply line, VSS <NUM>.

By controlling supply power to the power gated circuit <NUM> via at least one of the header switch <NUM> or footer switch <NUM>, the power gated circuit <NUM> may be considered to have a power domain that is specific to the power gated circuit <NUM>. Accordingly, power may be provided to, or shut off from, power gated circuit <NUM> without affecting power supplied to other parts of the circuit, chip, or device.

According to various embodiments, header switch <NUM> may be a high threshold voltage, low leakage PMOS transistor. In one set of embodiments, the threshold voltage for the header switch <NUM> may be at least <NUM>. In other words, the threshold voltage for the header switch <NUM> may be greater than the threshold voltage for the transistors of the gated circuit <NUM>. Accordingly, inherent to the higher threshold voltage, the header switch <NUM> may exhibit much less leakage current than the power gated circuit <NUM>.

In further embodiments, the footer switch <NUM> may be a high threshold voltage, low leakage NMOS transistor. In one set of embodiments, like the header switch <NUM>, the footer switch <NUM> may have a threshold voltage of at least <NUM>. In other words, the threshold voltage for the header switch <NUM> may be greater than the threshold voltage for the transistors of the gated circuit <NUM>. The footer switch <NUM> may also exhibit less leakage current than the power gated circuit <NUM>.

According to various embodiments, header switches <NUM> and footer switches <NUM> typically have very large total transistor width. For example, in one set of embodiments, the header switch <NUM> or footer switch <NUM> may have a gate width (W) that is four times larger than the total device W of the power gated circuit <NUM>.

According to various embodiments, power gated circuit <NUM> include all or part of an internal circuit. The internal circuit may include, but not limited to, sections and circuits of row decoders and column decoders, for example. This may include, without limitation, row decoder circuits and control logic, wordline drivers, column decoder circuits and control logic, bitline drivers, read/write circuits, sense amplifiers, sense amplifier gap control logic, write drivers, and other memory components and subsystems. In some embodiments, the power gated circuit <NUM> may be a low threshold voltage circuit created including a plurality of low threshold voltage devices. In one set of embodiments, the low threshold voltage devices may have threshold voltages of <NUM>. 4V or below. Accordingly, in some embodiments, the power gated circuit <NUM> may include a first transistor with a first threshold voltage lower, and at least one of the header switch <NUM> or footer switch <NUM> may have a second threshold voltage greater in absolute value than the first threshold voltage.

As will be described in more detail below, with respect to <FIG>, the timeout control circuit <NUM> may be configured to adjust a timeout delay responsive to operation parameters, for example, an operating temperature and process corner of a particular power gated circuit <NUM>. As will be appreciated by those skilled in the art, the higher the temperature, the more leakage will occur. The subthreshold leakage generally has an exponential relationship to temperature. Moreover, the amount of leakage current exhibited by a specific power gated circuit <NUM> will vary based on process corner variation. As will be described in further detail in the embodiments below, in some embodiments, the timeout control circuit <NUM> may be configured to respond to changes in subthreshold leakage due to temperature fluctuations close to, or substantially in real-time. In various embodiments, temperature dependency of the timeout circuit <NUM> may include, without limitation, the ability of the timeout circuit <NUM>, or elements of the timeout circuit <NUM> (e.g., leakage monitors), to adjust a timeout period based on operating temperatures of the power gated circuit <NUM>.

Once header switch <NUM>, footer switch <NUM>, or both header and footer switches <NUM>, <NUM> are activated via the timeout control circuit <NUM>, the timeout control circuit <NUM> prevents deactivation of the header and footer switches <NUM>, <NUM> for the duration of a timeout delay. The timeout delay may be configured to be responsive to at least one of the operation parameters, for example, a temperature and process corner of a particular power gated circuit <NUM>. According to the present invention, a duration of the timeout period is based, at least in part, on a temperature dependency of the amount of the leakage current of the power gated circuit.

In operation, a powerdown signal may be provided by the timeout control circuit <NUM>, based on Cke input <NUM>. In various embodiments, the Cke input <NUM> may correspond to a clock enable signal. The clock enable signal may be a control signal that enables a memory clock input. For example, when clock enable is low, a memory chip may behave as if the clock as stopped. Normal operation may resume when clock enable is high. Accordingly, clock enable may correspond to access activity on the device or circuit. In response to receiving a high clock enable signal at the Cke input <NUM>, the timeout control circuit <NUM> may provide an activation signal to the header switch <NUM>, footer switch <NUM>, or both, thereby resupplying power to the power gated circuit <NUM>. Conversely, a low clock enable signal at the Cke input <NUM> may indicate inactivity on the device. Accordingly, in response to receiving the low clock enable signal at the Cke input <NUM>, the timeout control circuit <NUM> may provide a powerdown signal to the header switch <NUM>, footer switch <NUM>, or both, thereby shutting off power to the power gated circuit <NUM>. In various embodiments, the timeout control circuit <NUM> may delay generating the powerdown signal for the duration of a timeout delay. For example, in one set of embodiments, when clock enable switches to a low state and remains at the low state, clock enable must remain low for the duration of the timeout delay before a powerdown signal is generated. If clock enable switches to a high state before the timeout delay has elapsed, the powerdown signal will not be generated until clock enable returns to a low state and remain low for a second specified duration less than or equal to the timeout delay. The duration of the timeout delay is adjusted based, at least in part, on the temperature of the power gated circuit <NUM>. According to the present invention, the duration of the timeout period is inversely proportional to the temperature of the power gated circuit <NUM>.

<FIG> illustrates an example of one such timeout control circuit <NUM>, in accordance with various embodiments. The timeout control circuit <NUM> may include a first input inverter <NUM>, second input inverter <NUM>, first precharge switch <NUM>, second precharge switch <NUM>, first leakage monitor <NUM>, second leakage monitor <NUM>, first capacitor <NUM>, second capacitor <NUM>, first trigger inverter <NUM>, second trigger inverter <NUM>, buffer inverter <NUM>, first output inverter <NUM>, second output inverter <NUM>, trigger NOR gate <NUM>, and output NOR gate <NUM>.

According to various embodiments, the input of the input inverter <NUM> may be coupled to a clock enable line and accept a clock enable signal. The output of the first input inverter <NUM> may be coupled to the first precharge switch <NUM>, and the second input inverter <NUM>. The output of the second input inverter <NUM> may in turn be coupled to the second precharge switch <NUM>. In various embodiments, the first precharge switch <NUM> may be a PMOS transistor. The gate of the PMOS transistor may be coupled to the output of the input inverter <NUM>, the source of the PMOS transistor may be coupled to VDD, and the drain of the PMOS transistor may be coupled to monitor node Nleak being precharged. Correspondingly, the second precharge switch <NUM> may be an NMOS transistor switch. The gate of the NMOS transistor switch may be coupled to the output of the second input inverter <NUM>, the source of the NMOS transistor switch may be coupled to VSS, and the drain of the NMOS transistor switch may be coupled to monitor node Pleak being precharged.

Operationally, in various embodiments, when the clock enable signal at Cke is high, the input inverter <NUM> may output a low signal to the first precharge switch <NUM>. In turn, the second input inverter <NUM> may provide a high signal to the second precharge switch <NUM>. When a low signal is provided to the first precharge switch <NUM>, the first precharge switch <NUM> may become conductive, precharging the monitor node Nleak to VDD. Correspondingly, when a high signal is provided to the second precharge switch <NUM>, the second precharge switch <NUM> may become conductive, precharging the monitor node Pleak to VSS. When the clock enable signal at Cke transitions low, a high signal may be provided to the first precharge switch <NUM>, and a low signal may be provided to second precharge switch <NUM>. In response, the first precharge switch <NUM> and second precharge switch <NUM> may be opened, disconnecting VDD from monitor node Nleak, and VSS from monitor node Pleak respectively.

The monitor node Nleak may be coupled to a first leakage monitor <NUM>, first capacitor <NUM>, and first trigger inverter <NUM>. In various embodiments, the first leakage monitor <NUM> may be configured to model leakage through N-type devices, such as, without limitation, N-type transistors, in a power gated circuit <NUM>, to which the timeout control circuit <NUM> is coupled. The first leakage monitor <NUM> may include one or more N-type devices fabricated using the same fabrication process as the N-type devices in the power gated circuit <NUM>. For example, in various embodiments the first leakage monitor <NUM> may have the same transistor types, having, without limitation, the same doping, threshold voltages, and other characteristics as the N-type transistors in the power gated circuit <NUM>. The first leakage monitor <NUM> may also use one or more N-type transistors, sized with identical channel length as the N-type transistors in the power gated circuit <NUM>. In one set of embodiments, the first leakage monitor <NUM> may be sized with an identical channel length and a W that is sized at no less than five times the minimum W allowed for the process technology utilized in the low voltage threshold circuit. The 5x multiple may guarantee that sigma variability for the individual legs of the first leakage monitor <NUM> with respect to, without limitation, threshold voltage, mobility, and other characteristics, represents an average for the power gated circuit <NUM> being modeled.

In this way, the first leakage monitor <NUM> may exhibit the same process corner characteristics and model subthreshold leakage in the N-type devices of the power gated circuit <NUM>. In one set of embodiments, the first leakage monitor <NUM> may include a single N-type device. In other embodiments, the first leakage monitor <NUM> may include multiple N-type devices in one or more of the individual legs. By utilizing N-type devices fabricated using the same fabrication process as in the power gated circuit <NUM>, process corner characteristics may be modeled. Moreover, the first leakage monitor <NUM> may be placed under similar operating conditions as the power gated circuit <NUM>. For example, the first leakage monitor <NUM> may be subject to similar temperature conditions. In various embodiments, the first leakage monitor <NUM> may be placed in close proximity to the power gated circuit <NUM>, for example, on the same chip or die, and similarly powered or unpowered. In other embodiments, the first leakage monitor <NUM> may be placed on a different chip or die, but configured to experience temperature conditions modelling the power gated circuit <NUM>.

In various embodiments, the first capacitor <NUM> may be one or more of an NMOS or PMOS transistor. When an NMOS transistor is utilized, both source and drain may be tied to VSS and the gate connected to the monitor node Nleak. When a PMOS capacitor is utilized, both source and drain may be tied to VDD, with the gate connected to the monitor node Nleak.

Similarly, monitor node Pleak may be coupled to a second leakage monitor <NUM>, second capacitor <NUM>, and second trigger inverter <NUM>. In various embodiments, the second leakage monitor <NUM> may be configured to model the leakage through all P-type devices, such as, without limitation, P-type transistors, in power gated circuit <NUM>, to which the timeout control circuit <NUM> is coupled. The second leakage monitor <NUM> may include one or more P-type devices fabricated using the same fabrication process as the P-type devices in the power gated circuit <NUM>. For example, in various embodiments the second leakage monitor <NUM> may include the same transistor types, having, without limitation, the same doping, threshold voltages, and other characteristics as the P-type transistors in the power gated circuit <NUM>. The second leakage monitor <NUM> may include one or more transistors, sized with identical channel length as the P-type transistors in the power gated circuit <NUM>. In one set of embodiments, like the first leakage monitor <NUM>, the second leakage monitor <NUM> may have a W that is sized at no less than five times the minimum W allowed for the process technology utilized in the power gated circuit <NUM>.

In this way, the second leakage monitor <NUM> may exhibit the same process corner characteristics and model subthreshold leakage in the P-type devices in the power gated circuit <NUM>. In one set of embodiments, the second leakage monitor <NUM> may include a single P-type transistor. In other embodiments, the second leakage monitor <NUM> may include multiple P-type transistors in one or more of the individual legs. As with the first leakage monitor <NUM>, the second leakage monitor <NUM> may be placed under similar operating conditions as the power gated circuit <NUM>. In this manner, the second leakage monitor <NUM> may be configured to be subject to similar temperature conditions, and to exhibit similar process corner characteristics.

In various embodiments, as with the first capacitor <NUM>, second capacitor <NUM> may be one or more of an NMOS or PMOS capacitor, and may be configured similarly to the first capacitor <NUM>, but in relation to the monitor node Pleak. For example, when an NMOS transistor is utilized, both source and drain may be tied to VSS and the gate connected to the monitor node Pleak. When a PMOS capacitor is utilized, both source and drain may be tied to VDD, with the gate connected to the monitor node Pleak.

Therefore, in accordance with various embodiments, the timeout control circuit may include a capacitive element, such as first capacitor <NUM> and second capacitor <NUM>, and a resistive element coupled to the capacitive element, such as first leakage monitor <NUM>, second leakage monitor <NUM>. In some embodiments, the first leakage monitor <NUM> or second leakage monitor <NUM> may be configured to charge the first and second capacitors <NUM>, <NUM> respectively. As current begins to leak through the first and second leakage monitors <NUM>, the first and second leakage monitors <NUM> may act as resistive elements configured to discharge the capacitive element.

In accordance with various embodiments, the signal at monitor node Nleak may be tied to the input of a first trigger inverter <NUM>. Correspondingly, the signal at monitor node Pleak may be tied to the input of the second trigger inverter <NUM>. Thus, the signal output by the first trigger inverter <NUM> and the second trigger inverter <NUM> will reflect N-channel and P-channel subthreshold leakage through each of the first leakage monitor <NUM> and second leakage monitor <NUM>, respectively. For example, in operation, when Cke is high, the outputs of the first trigger inverter <NUM> is held at a logical low while the outputs of the second trigger inverter <NUM> is held at a logical high. When Cke is low, and both first and second precharge switches <NUM>, <NUM> are turned off, input signals provided to the first and second trigger inverters <NUM>, <NUM> will slowly leak towards their complementary voltage rails as current leaks through the respective first and second leakage monitors <NUM>, <NUM>. For example, the signal input at monitor node Nleak to the first trigger inverter <NUM> will initially be precharged at VDD. When the first precharge switch <NUM> is shut off, the signal input at monitor node Nleak will slowly leak through the first leakage monitor <NUM>, towards complement power rail VSS. Eventually, the voltage at the monitor node Nleak will be low enough to trigger the first trigger inverter <NUM>. In turn, the first trigger inverter <NUM> may output a signal having a logic high, indicating that leakage through the first leakage monitor <NUM> has caused the voltage at monitor node Nleak to be less than the trigger voltage (Vtrigg) of the first trigger inverter <NUM>. In one set of embodiments, the logic high output of first trigger inverter <NUM> may be at VDD. Complementing the N-channel side of the circuit, the signal input at monitor node Pleak to the second trigger inverter <NUM> will initially be precharged to VSS. When the second precharge switch <NUM> is shut off, the signal input will slowly be pulled up to complement power rail VDD. Eventually, the voltage at monitor node Pleak will be high enough to trigger the second trigger inverter <NUM>. In turn, the second trigger inverter <NUM> may output a signal having a logic low, indicating that the leakage through the second leakage monitor <NUM> has caused the voltage at monitor node Pleak to be greater than Vtrigg of the second trigger inverter <NUM>. In one set of embodiments, logic low may be VSS.

In various embodiments, the output of the first trigger inverter <NUM> may be coupled to the input of buffer inverter <NUM>, which in turn has an output coupled to a first output inverter <NUM>. The output of the second trigger inverter <NUM> may, in turn, be coupled to the input of a second output inverter <NUM>. In various embodiments, the buffer inverter <NUM>, and first output inverter <NUM> may be configured such that the output characteristics of first output inverter <NUM> is matched to the output characteristics of second output inverter <NUM>. In this way, the first output inverter <NUM> may output a signal tied to a first input of trigger NOR gate <NUM>, and the second output inverter <NUM> may output a signal tied to a second input of the trigger NOR gate <NUM>.

According to various embodiments, in operation, when the clock enable signal is low, the outputs at both of the first and second output inverters <NUM>, <NUM> will eventually switch to logical high, reflecting that the subthreshold leakage through the first leakage monitor <NUM> and second leakage monitor <NUM>, respectively have crossed the respective Vtrigg of the first and second trigger inverters <NUM>, <NUM>. In various embodiments, the trigger NOR gate <NUM> may be configured to have a comparator threshold that may be less than VDD. Therefore, whichever of the first input, corresponding to N-channel leakage, or the second input, corresponding to P-channel leakage, crosses the comparator threshold first will cause the trigger NOR gate <NUM> to output a logic low signal. Thus, the output of the trigger NOR gate <NUM> is controlled by whichever of subthreshold leakage in the first or second leakage monitors <NUM>, <NUM> is greater.

The output of the trigger NOR gate <NUM> may be tied then to a second input of the powerdown NOR gate <NUM>, while a first input of the powerdown NOR gate <NUM> may be tied to Cke input <NUM> providing the clock enable signal. Accordingly, when clock enable is low, and the output of the trigger NOR gate <NUM> is low, a logic high is asserted signaling entry into powerdown mode for the power gated circuit <NUM>. Thus, the duration of the timeout delay may correspond to the delay between when the clock enable signal is low, and when a logic low signal is output by the trigger NOR gate <NUM> and received at the second input of the powerdown NOR gate <NUM>. Thus, the power gated circuit <NUM> will remain powered until the duration of the timeout delay has elapsed. In other words, only if clock enable remains low for the duration of the timeout delay will the powerdown signal be asserted.

Thus, according to various embodiments, the length of time for the inputs of the trigger NOR gate <NUM> to cross the comparator threshold is directly related to the power leakage through first and second leakage monitors <NUM>, <NUM>. Therefore, the duration of the timeout delay may be adjusted, on a first side of the timeout circuit <NUM> by adjusting the size of the first leakage monitor <NUM>, and the first capacitor <NUM>. The timeout duration may be adjusted on a second side of the timeout circuit <NUM> by adjusting the size of the second leakage monitor <NUM> and second capacitor <NUM>. In this way, the duration of the timeout delay may be adjusted while maintaining responsiveness to both temperature and process corner of the power gated circuit <NUM>. In one set of embodiments, an optimal timeout duration may be determined based on leakage current for the power gated circuit <NUM>, and a switching current for the header switch <NUM>, footer switch <NUM>, or both header and footer switches <NUM>, <NUM>. For example, if subthreshold leakage for the power gated circuit <NUM> is 1mA at a temperature of 90C, and <NUM>. 1mA at a temperature of 25C, timeout delay may be determined based on a switching current of the header and footer switches <NUM>, <NUM>, which are substantially independent of temperature. In one set of embodiments, the switching current for the header and footer switches <NUM>, <NUM> may be 10mA for the duration of 1ns. Thus, at a temperature of 90C, it would be inefficient for the header and footer switch <NUM>, <NUM> to be switched off before 20ns have elapsed, as a 1mA leakage current for a duration of 20ns is equivalent in power to two transient pulses of 10mA for a 1ns duration. Similarly, at a temperature of 25C, it would be inefficient for the header and footer switch <NUM>, <NUM> to be switched off before 200ns have elapsed. Thus, the first and second leakage monitors <NUM>, <NUM> and first and second capacitors <NUM>, <NUM> may respectively be configured to produce a 20ns timeout delay at a temperature of 90C, and a 200ns timeout delay at a temperature of 25C. It will be appreciated that the values used above were chosen for simplicity in describing the example conceptually. In other embodiments, other values may be utilized corresponding to real-world leakage characteristics, temperature fluctuations, and variations in the design of the power gating circuit <NUM>, such as the implementation of one or both of the header and footer switches <NUM>, <NUM>, and one or more of the first or second leakage monitors <NUM>, <NUM> when setting a desired timeout delay.

<FIG> illustrates a trim circuit implementation of a timeout control circuit <NUM> utilizing metal trim switch options, in accordance with various embodiments. Like the timeout control circuit <NUM> of <FIG>, timeout control circuit <NUM> may include an input NAND gate <NUM>, first input inverter <NUM>, first precharge switch <NUM>, second precharge switch <NUM>, first leakage monitor <NUM>, second leakage monitor <NUM>, first capacitors <NUM>, second capacitors <NUM>, first trigger inverter <NUM>, second trigger inverter <NUM>, buffer inverter <NUM>, first output inverter <NUM>, second output inverter <NUM>, trigger NOR gate <NUM>, and output NOR gate <NUM>. In addition to these elements, the timeout control circuit <NUM> may further include spare transistors <NUM>, as well as a power gating enable circuit <NUM>.

Compared to <FIG>, the input NAND gate <NUM> may function analogously to the input inverter <NUM>. In various embodiments, the input NAND gate <NUM> may receive two inputs, a clock enable signal input, and a control circuit enable input. Accordingly, only when both clock enable and control circuit enable are high, is a low signal output from the input NAND gate <NUM>. This will, in turn, cause first and second precharge switches <NUM>, <NUM> to be in a conductive state. When either of clock enable or control circuit enable are low, the first and second precharge switches <NUM>, <NUM> are made non-conductive.

In various embodiments, the first leakage monitor <NUM> may include multiple legs 325a, 325b, 325c, 325d. Each leg 325a-325d may include one or more N-type devices, including, without limitation, N-type transistors. For example, individual leg 325d may include two N-type transistors, while legs 325a-325c each include a single N-type transistor. Each of the N-type devices may be fabricated utilizing the same process technology as the N-type devices in the power gated circuit <NUM>. In one set of embodiments, each of the N-type devices in the first leakage monitor <NUM> may have a W that is sized at no less than five times the minimum W allowed for the process technology utilized in the low voltage threshold circuit. The multiple for W may be chosen to guarantee that sigma variability over each of the individual legs 325a-325d represents an average for the power gated circuit <NUM> being modeled. In various embodiments, the use of multiple legs 325a-325d accounts for variability in the fabrication process of the N-type devices in the first leakage monitor <NUM> itself. Accordingly, in various embodiments, each of the individual legs 325a-325d of the first leakage monitor <NUM> may be programmable. For example, in one set of embodiments, each individual leg 325a-325d may include an antifuse, allowing each of the legs to be programmed individually. Similarly, in various embodiments, the second leakage monitor <NUM> may also include multiple legs 330a, 330b, 330c, 330d.

As described with respect to <FIG>, first and second capacitors <NUM>, <NUM> may be configured to adjust the duration of the timeout. In some embodiments, as more legs of the first leakage monitor <NUM>, and in turn more N-type devices are programmed, the first leakage monitor <NUM> will exhibit more subthreshold leakage. As a result, to account for the increased subthreshold leakage, additional and/or larger N-channel and P-channel capacitors may be added. In one set of embodiments, similar to the individual legs 325a-325d of the first leakage monitor <NUM>, additional capacitors may be added via an antifuse.

In some embodiments, spare transistors <NUM> may also be provided. Spare transistors <NUM> may include one or more NMOS and one or more PMOS transistors. The spare transistors <NUM> may be configured to have the size and fabrication characteristics of the transistors utilized in the timeout control circuit <NUM>, to replace one or more of the transistors in case of failure. For example, the spare transistors <NUM> may be configured to replace a failed transistor in the first or second precharge switch <NUM>, <NUM>; the first or second leakage monitors <NUM>, <NUM>; the first or second capacitors <NUM>, <NUM>; the first or second output inverters <NUM>, <NUM>; or in any other part of the timeout control circuit <NUM>. In some embodiments, the spare transistors <NUM> may also be programmable through, without limitation, antifuses.

In various embodiments, the timeout control circuit <NUM> may further include a separate power gating enable circuit <NUM>. In some embodiments, the control circuit enable signal may be a separately asserted signal to enable one or more power gating control circuits. When the control circuit enable signal is low, indicating that the power gating control circuit should be disabled, the power gating enable circuit <NUM> may cause respective N-channel and P-channel transistors to become conductive. This will pull the N-channel monitor node to VSS, and P-channel monitor node to VDD, preventing the timeout control circuit <NUM> from outputting a powerdown signal at powerdown NOR gate <NUM>.

<FIG> illustrates voltage curves <NUM> over time in a temperature and process corner sensitive timeout control circuit. The voltage curve shown in Cke <NUM> illustrates the clock enable signal on the Cke input line. The voltage curves shown in Nleak <NUM> illustrates the leakage of the precharge voltage at monitor node Nleak. Pleak <NUM> illustrates the leakage of the precharge voltage at the monitor node Pleak. Powerdown <NUM> illustrates when the powerdown signal is asserted relative to the other voltage curves.

In the embodiments depicted, voltage curve Cke <NUM> shows that the clock enable signal becomes low at <NUM>. In response, as depicted in Nleak <NUM>, the voltage at monitor node Nleak starts to fall towards complement power rail VSS, in this case at 0V. A first voltage curve <NUM>, as shown in Nleak <NUM>, may correspond to a voltage at the monitor node Nleak at a first temperature, and a second voltage curve <NUM>, may correspond to a voltage at the monitor Nleak at a second temperature higher than the first temperature. The P-channel complement, depicted in Pleak <NUM>, shows the precharge voltage at monitor node Pleak starts to rise towards complement power rail VDD, in this case at 1V. A first voltage curve <NUM> of Pleak <NUM> may correspond to a voltage at the monitor node Pleak at the first temperature, and a second voltage curve <NUM> of Pleak <NUM> may correspond to a voltage at the monitor Pleak at the second temperature. For example, in one set of embodiments, the first temperature may be 25C, and the second temperature may be 90C. Whichever of Nleak <NUM> or Pleak <NUM> crosses the trigger voltage Vtrigg of the first trigger inverter <NUM>, <NUM> or second trigger inverter <NUM>, <NUM> will trigger the powerdown signal. As used herein, crossing Vtrigg may include both falling below Vtrigg at Nleak <NUM>, or exceeding Vtrigg at Pleak <NUM>. Therefore, whichever of the first leakage monitor <NUM>, <NUM> or second leakage monitor <NUM>, <NUM> has more leakage will determine the duration of the timeout. In this case, both the first voltage curve <NUM> of Nleak <NUM>, and the first voltage curve <NUM> of Pleak <NUM> cross Vtrigg at points <NUM>, <NUM>, at substantially the same time at line <NUM> - approximately <NUM>. The second voltage curve <NUM> of Nleak <NUM> and the second voltage curve <NUM> of Pleak <NUM> cross Vtrigg at points <NUM>, <NUM> at substantially the same time at line <NUM> - approximately <NUM>. This causes powerdown <NUM> to also be asserted high at approximately <NUM> at the first temperature, but at <NUM> at the second temperature. Accordingly, in various embodiments, the timeout duration may be the time between when clock enable becomes low and when the power down signal becomes high. Generally, the higher temperature, the shorter the timeout duration. For example, for the first temperature, clock enable becomes low at <NUM> and the powerdown signal becomes high at <NUM>. Thus, in the illustrated embodiment, the timeout duration is approximately <NUM> at the first temperature. However, at the second temperature, the powerdown signal is activated at <NUM> corresponding to a timeout duration of <NUM> ns.

<FIG> illustrates a block diagram of a portion of a memory system <NUM>. The system <NUM> includes an array <NUM> of memory cells, which may be, for example, volatile memory cells (e.g., dynamic random-access memory (DRAM) memory cells, low-power DRAM memory (LPDRAM),static random-access memory (SRAM) memory cells), nonvolatile memory cells (e.g., flash memory cells), or other types of memory cells. The memory <NUM> includes a command decoder <NUM> that may receive memory commands through a command bus <NUM> and provide (e.g., generate) corresponding control signals within the memory <NUM> to carry out various memory operations. For example, the command decoder <NUM> may respond to memory commands provided to the command bus <NUM> to perform various operations on the memory array <NUM>. In particular, the command decoder <NUM> may be used to provide internal control signals to read data from and write data to the memory array <NUM>. Row and column address signals may be provided (e.g., applied) to an address latch <NUM> in the memory <NUM> through an address bus <NUM>. The address latch <NUM> may then provide (e.g., output) a separate column address and a separate row address.

The address latch <NUM> may provide row and column addresses to a row address decoder <NUM> and a column address decoder <NUM>, respectively. The column address decoder <NUM> may select bit lines extending through the array <NUM> corresponding to respective column addresses. The row address decoder <NUM> may be connected to a word line driver <NUM> that activates respective rows of memory cells in the array <NUM> corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address may be coupled to a read/write circuitry <NUM> to provide read data to an output data buffer <NUM> via an input-output data path <NUM>. Write data may be provided to the memory array <NUM> through an input data buffer <NUM> and the memory array read/write circuitry <NUM>.

Power gating control logic <NUM> may include all or part of one or more timeout control circuits. The power gating control logic <NUM> may selectively couple various power gated domains to a primary power supply when the power gated circuit is to be accessed. The timeout control circuits of the power gating control logic <NUM> may selectively provide power to access circuitry for each of one or more internal circuits. For example, access circuitry may include, without limitation, all or part of row decoder <NUM>, word line driver <NUM>, column decoder <NUM>, sense amplifiers, sense amplifier gap control logic, and R/W circuit <NUM>. As described with respect to the figures above, when a clock enable is low, and the one or more power gated circuits are inactive, the power gating control logic <NUM>, via the one or more timeout control circuits, may be configured to generate a timeout responsive to both temperature and process corner of the one or more power gated circuits, respectively.

<FIG> illustrates a flow chart of a method <NUM> for temperature and process corner sensitive control of a power gated domain. The method begins, at block <NUM>, by providing at least one leakage monitor coupled to a monitor node. As described with respect to <FIG> & <FIG> above, in various embodiments, the leakage monitor may be an N-channel leakage monitor corresponding to the first leakage monitor <NUM>, <NUM>, or a P-channel leakage monitor corresponding to second leakage monitor <NUM>, <NUM>, or both. The at least one leakage monitor may be configured to model the leakage through all N-type devices or P-type devices in a power gated circuit, sensitive to both temperature conditions and process corner of the power gated circuit.

The method <NUM> continues, at block <NUM>, by supplying a power supply voltage to the power gated circuit. In various embodiments, the power gated circuit may be coupled to a first power supply voltage via a header switch. In some embodiments, the power gated circuit may be coupled to a second power supply voltage via a footer switch. In further embodiments, both a header and footer switch may be provided to couple the power gated circuit to first and second power supply voltages, respectively. In various embodiments, while the power gated circuit is powered, and correspondingly the clock enable signal is high, the power gating circuit may precharge a corresponding monitor node Nleak, or corresponding monitor node Pleak.

At decision block <NUM>, the state of the clock enable signal is determined, via a timeout control circuit, at Cke input. When clock enable is high (active), at block <NUM>, a power supply voltage continues to be supplied to the power gated circuit. However, when clock enable is low (inactive), at block <NUM>, the method <NUM> continues by monitoring a voltage at the monitor node. In various embodiments, this may occur at monitor node Nleak, monitor node Pleak, or both monitor nodes Nleak and Pleak. Therefore one or more of the N-channel or P-channel leakage of the power gated circuit may be independently monitored.

At decision block <NUM>, it may be determined, via a timeout control circuit, whether a trigger voltage has been reached at either of monitor node Nleak or monitor node Pleak. In various embodiments, the trigger voltage Vtrigg may be configured to be between the first power supply voltage and the second power supply voltage. If the trigger voltage has not been reached, at block <NUM>, power supply voltage continues to be provided to the power gated circuit. If the trigger voltage has been exceeded, then, at block <NUM>, the method <NUM> continues by removing power supply voltage from the power gated circuit.

While certain features and aspects have been described with respect to exemplary embodiments, one skilled in the art will recognize that various modifications and additions can be made to the embodiments discussed. Although the embodiments described above refer to particular features, it may be possible to have different combination of features and embodiments that do not include all of the above described features. For example, the methods and processes described herein may be implemented using hardware components, software components, and/or any combination thereof. Further, while various methods and processes described herein may be described with respect to particular structural and/or functional components for ease of description, methods provided by various embodiments are not limited to any particular structural and/or functional architecture, but instead can be implemented on any suitable hardware, firmware, and/or software configuration. Similarly, while certain functionality is ascribed to certain system components, unless the context dictates otherwise, this functionality can be distributed among various other system components in accordance with the several embodiments.

Claim 1:
An apparatus (<NUM>) comprising:
an internal circuit (<NUM>);
a power supply line (<NUM>, <NUM>); and
a power gating control circuit (<NUM>) comprising a switch (<NUM>, <NUM>) coupled between the internal circuit and the power supply line, the power gating control circuit configured to:
initiate supplying a power supply voltage from the power supply line to the internal circuit responsive, at least in part, to a first change from a first state to a second state of a control signal (<NUM>);
detect, with a leakage monitor (<NUM>, <NUM>) of the power gating control circuit, an amount of a leakage current of the internal circuit;
continue supplying the power supply voltage from the power supply line to internal circuit for a timeout period, wherein the timeout period begins at a second change from the second state to the first state of the control signal and a duration of the timeout period is based, at least in part, on a temperature dependency of the amount of the leakage current of the internal circuit, wherein the duration of the timeout period is inversely proportional to a temperature of the internal circuit, wherein the timeout period is a period of time during which the power gating control circuit prevents deactivation of the switch; and
continue supplying the power supply voltage from the power supply line to the internal circuit when a third change from the first state to the second state occurs during the timeout period.