Patent Description:
This application relates generally to IQ generators.

Wireless communication devices are commonly deployed in wireless communication systems to provide communication services such as voice, multimedia, data, broadcast, and messaging services. In a wireless communication device such as a mobile phone, an IQ generator may provide orthogonal signals represented by in-phase (I) and quadrature (Q) components.

<CIT> discloses a signal generator according to the pre-characterizing part of independent claim <NUM>. Further, <CIT> discloses a signal generator having two delay paths for the I and Q signals and <CIT> discloses a receiver circuit comprising a signal generator.

IQ generators with lower power consumption and smaller die area are provided. In particular, a signal generator according to the invention is defined in independent claim <NUM>. The dependent claims define preferred embodiments thereof.

Some embodiment relates to a signal generator for generating signals that are orthogonal in phase. The signal generator comprises a delay path configured to generate the signals from an input signal of a carrier frequency, and a calibration circuitry configured to provide a control signal to the delay path based at least in part on the signals. An operating frequency of the signal generator is less than twice the carrier frequency.

In some embodiments, the input signal of the carrier frequency is from a test tone generator.

In some embodiments, the input signal of the carrier frequency comprises output signals of the test tone generator that are in two different phases.

In some embodiments, the input signal of the carrier frequency comprises output signals of the test tone generator that are in a single phase.

In some embodiments, the output signals of the test tone generator comprise a pair of differential signals in the single phase.

In some embodiments, the delay path comprises one or more delay cells configured to adjust their transconductances based at least in part on the control signal from the calibration circuitry.

In some embodiments, a delay cell of the one or more delay cells comprises a pair of transistors that receive the input signal of the carrier frequency, a back-to-back inverter coupled to the pair of transistors, and a delay unit connected in series with the pair of transistors and configured to adjust its transconductance based at least in part on the control signal from the calibration circuitry.

In some embodiments, the calibration circuitry comprises a comparator configured to compare average pulse widths of the signals and provide the control signal based at least in part on the comparison.

Some embodiment relates to a signal generator for generating signals that are orthogonal in phase. According to the invention, the signal generator comprises a single delay path comprising input nodes that receive an input signal of a carrier frequency and output nodes that provide the signals, and a calibration circuitry comprising input nodes that receive the signals and an output node that provides a control signal to the single delay path. An operating frequency of the signal generator is less than twice the carrier frequency.

In some embodiments, the input signal of the carrier frequency comprises a pair of differential signals in a single phase.

In some embodiments, the single delay path comprises a plurality of delay cells controlled by the respective control signal.

According to the invention, the input signal of the carrier frequency has a <NUM>% duty cycle, and the single delay path comprises a circuitry that receives signals with the <NUM>% duty cycle and provides signals with a <NUM>% duty cycle.

In some embodiments, the input signal of the carrier frequency comprises a first output signal of the test tone generator that is in a first phase and a second output signal of the test tone generator that is in a second phase different from the first phase.

In some embodiments, the calibration circuitry comprises a direct current (DC) filter comprising the input nodes of the calibration circuitry.

Some embodiments relate to a receiver circuit. The receiver circuit comprises a low-noise amplifier configured to receive an input signal of a carrier frequency and amplify the input signal, a test tone generator configured to generate a tone signal of the carrier frequency, a signal generator configured to generate signals that are orthogonal in phase from the tone signal of the carrier frequency generated by the test tone generator, and a mixer configured to receive the amplified input signal and the signals.

In some embodiments, the receiver circuit comprises a switch coupled between output nodes of the low-noise amplifier and the test tone generator. The switch is on when the tone signal of the carrier frequency is used to suppress sideband signals with respect to the carrier frequency.

These techniques may be used alone or in any suitable combination. The foregoing summary is provided by way of illustration and is not intended to be limiting.

Described herein are IQ generators with lower power consumption and smaller die area. The inventors have recognized and appreciated that conventional IQ generators include a synthesizer operating at twice a carrier frequency and a divide-by-<NUM> circuitry configured to convert an output of the synthesizer of the twice the carrier frequency into orthogonal signals of the carrier frequency. A synthesizer, for example, an LC-based voltage controlled oscillator (VCO), occupies significant die area, and increases cost of a chip that includes IQ generators. In addition to occupying extra chip area, the synthesizer and divide-by-<NUM> circuitry, both of which are operating at twice the carrier frequency, consume significant power. This problem becomes more prominent when the carrier frequency increases, for example, to <NUM> with <NUM>. 11ax or <NUM>.

The inventors have developed IQ generators with lower power consumption and smaller die area such that a synthesizer generating a signal of twice a carrier frequency is not needed. In some embodiments, IQ generators may be configured without any synthesizer and divide-by-<NUM> circuitry.

In some embodiments, an IQ generator may be configured to convert one or more phase outputs of a test tone generator into I and Q signals that are orthogonal in phase. In some embodiments, an IQ generator may receive as inputs differential outputs of a single phase of a test tone generator. In some embodiments, an IQ generator may receive as inputs multiple phase outputs of a test tone generator.

In some embodiments, an IQ generator may include one or more delay paths configured to generate I and Q signals. In some embodiments, an IQ generator may include a single delay path configured to receive one of the differential outputs of the test tone generator. In some embodiments, an IQ generator may include multiple delay paths configured to receive respective phase outputs of the test tone generator. In some embodiments, each delay path may receive a respective control signal such that the I and Q signals generated are orthogonal in phase. In some embodiments, a delay path may include at least two delay cells configured to adjust their transconductances based on a control signal.

In some embodiments, an IQ generator may include a calibration circuit configured to compare the average waveform bandwidths of the I and Q signals and provide one or more control signals to the one or more delay paths such that the I and Q signals are orthogonal in phase.

IQ generators may be included in an application for Dynamic Frequency Selection (DFS). Pursuant to DFS, WiFi transceivers (e.g., n x n MIMO transceivers) may identify the presence of a co-channel radar signal so as to avoid such occupied channel when operating in frequency ranges that requires DFS including, for example, <NUM>-<NUM> and <NUM>-<NUM>. <FIG> shows the <NUM> WiFi band <NUM>, which may include WiFi channels with bandwidths depending on the protocols used to access the channels. In the illustrated example, channels on the first row (e.g., channels <NUM>, <NUM>, <NUM> with center frequencies <NUM>, <NUM> and <NUM> respectively) have a bandwidth of <NUM>; channels on the second row (e.g., channels <NUM>, <NUM>, <NUM> with center frequencies <NUM>, <NUM> and <NUM> respectively) have a bandwidth of <NUM>; channels on the third row (e.g., channels <NUM>, <NUM>, <NUM> with center frequencies <NUM>, <NUM> and <NUM> respectively) have a bandwidth of <NUM>; and channels on the fourth row (e.g., channels <NUM>, <NUM> with center frequencies <NUM> and <NUM> respectively) have a bandwidth of <NUM>. Some of the WiFi channels may also be available to be occupied by a radar signal and referred to as radar-WiFi DFS co-channels (e.g., channels <NUM>-<NUM> on the first row, channels <NUM>-<NUM> on the second row, channels <NUM>-<NUM> on the third row, channels <NUM>, <NUM> on the fourth row). Although a DFS application in a WiFi system improves system throughput, DFS causes a WiFi transceiver to perform a Channel Availability Check (CAC), which determines the WiFi channels that are free of radar signals. When it is identified the presence of a radar signal in the channel being utilized by the WiFi transceivers, the WiFi transceivers may jump to one of the WiFi channels that are determined through CAC as free of radar signals.

A WiFi transceiver for DFS may include an IQ generator that provides orthogonal signals to a mixer. <FIG> depicts a schematic diagram of a DFS receiver <NUM>, according to some embodiments. The DFS receiver <NUM> may receive an RF input signal of a carrier frequency at an input node <NUM>. The DFS receiver <NUM> may include a low noise amplifier (LNA) <NUM> configured to amplify the RF input signal while ensuring its signal-to-noise ratio. Although the illustrated LNA is a single-ended cascade LNA with integrated input matching and inductive source denegation, any suitable LNA may be employed.

The DFS receiver <NUM> may include a test tone generator (TTG) <NUM> configured to generate a tone signal of the carrier frequency. The TTG <NUM> may be coupled to a mixer <NUM> through a switch <NUM>. Although the illustrated switch is connected to LNA output, any connecting points of LNA input may be employed. Although the illustrated mixer is a current-mode single-balanced passive I/Q mixer, any suitable mixer may be employed. During the establishment of a WiFi link, the switch <NUM> may be turned on such that the tone signal generated by the TTG <NUM> may be used for calibration and to suppress sideband signals with respect to the carrier frequency. After the establishment of a WiFi link, the switch <NUM> may be turned off.

The TTG <NUM> may be coupled to an IQ generator <NUM>. The TTG <NUM> may send one or more of its outputs of the carrier frequency to the IQ generator <NUM>. The IQ generator <NUM> may be configured to convert the outputs of the TTG <NUM> into orthogonal signals (e.g., I+, I-, Q+, Q-) and provide the orthogonal signals to the mixer <NUM>.

The DFS receiver <NUM> may include transimpedance amplifiers (TZA) and low pass filters (LPF) <NUM>, which may be configured to drive successive-approximation-register (SAR) analog-to-digital converters (ADCs) <NUM>. In some embodiments, the TZA + LPF <NUM> may be configured with a fixed bandwidth (e.g., <NUM>) such that the scan of the entire WiFi band may complete within a desired time (e.g., <NUM> minutes). When a radar signal is detected in any of the fixed bandwidth channels, a digital filter may divide the band detected with the radar signal into multiple bands with smaller bandwidths (e.g., an <NUM> band may be divided into four <NUM> bands). Then it is determined that the radar signal is in which one of the bands with smaller bandwidths. This configuration may save scan time.

<FIG> is a block diagram of a portion <NUM> of a DFS receiver (e.g., the DFS receiver <NUM>). The portion <NUM> of the DFS receiver may include an IQ generator <NUM> receiving an input from a TTG <NUM> and outputting to a mixer <NUM>. The TTG <NUM> may include a ring oscillator <NUM>, a buffer <NUM>, and a feedback circuitry <NUM>. The output signals <NUM> of the buffer <NUM> may be fed back to the oscillator <NUM> through the feedback circuitry <NUM>. The feedback circuitry <NUM> may be configured to detect the phase and frequency of the output signals <NUM> and generate a control signal <NUM> for the oscillator <NUM> based on the detected phase and frequency of the output signals <NUM>.

The IQ generator <NUM> may be configured to receive the output signals <NUM> of the TTG <NUM>. The IQ generator <NUM> may include a delay path <NUM> and a calibration circuitry <NUM>. The delay path <NUM> may include a delay buffer <NUM>, an IQ delay circuitry <NUM>, a duty-cycle adjustment circuitry <NUM>, and a mixer buffer <NUM>. The IQ delay circuitry <NUM> may receive signals from the delay buffer <NUM> that may receive the output signals <NUM> of the TTG <NUM>. The IQ delay circuitry <NUM> may be configured to generate IQ signals <NUM> that may be substantially orthogonal in phase. The IQ signals <NUM> may have a duty cycle that is similar to the duty cycle of the output signals <NUM> of the TTG <NUM>, for example, a <NUM>% duty cycle as illustrated.

The duty-cycle adjustment circuitry <NUM> may be configured to modify the duty cycle of the IQ signals <NUM> to generate IQ signals <NUM>. The IQ signals <NUM> may be amplified to IQ signals <NUM> by the mixer buffer <NUM>, which may be provided to the mixer <NUM>. The IQ signals <NUM> and <NUM> may have a duty cycle suitable for the mixer <NUM>, and/or suitable for the calibration circuitry <NUM>. In the illustrated example, according to the invention, the IQ signals <NUM> and <NUM> have a <NUM>% duty cycle, which is reduced from the <NUM>% duty cycle of the IQ signals <NUM>. Providing, to the mixer <NUM> and the calibration circuitry <NUM>, IQ signals with a <NUM>% duty cycle may reduce signal overlapping for mixer operation.

The calibration circuitry <NUM> may include a DC filter <NUM> and a low power comparator operational amplifier <NUM>. The DC filter <NUM> may be configured to provide the average pulse widths (Vavg +/-) of the IQ signals <NUM> to the comparator <NUM>. The comparator <NUM> may be configured to generate a control signal <NUM>, which is provided to the IQ delay circuitry <NUM> such that the IQ delay circuitry <NUM> may adjust its transconductance to make IQ signals <NUM> within a targeted phase error.

In some embodiments, an IQ generator may receive as inputs differential outputs of a single phase of a TTG. <FIG>, B depict a portion <NUM> of a DFS receiver, which may include an IQ generator <NUM> configured to receive as inputs differential outputs (e.g., IN, INb) of a single phase of a TTG <NUM> and provide IQ signals <NUM> to a mixer <NUM>. <FIG> and <FIG> depict time diagrams of the TTG <NUM> and the IQ generator <NUM>, according to some embodiments.

The TTG <NUM> may produce multiple phase signals of a carrier frequency such as CK1, CK2, and CK3. In some embodiments, the TTG <NUM> may have a differential configuration, and each phase signal may include a pair of differential signals (e.g., IN, INb for CK3). Although some of the multiple phase signals such as CK1 and CK3 may have a phase difference close to <NUM> degrees, these signals are likely to have large phase error, for example, illustrated as the shaded edges of CK1, CK2, and CK3 in <FIG>, and thus cannot provide a sufficient signal-to-noise ratio.

The IQ generator <NUM> may be configured to generate IQ signals with low phase error, for example, illustrated as the sharp edges of I and Q in <FIG>. The IQ generator <NUM> may include a delay path <NUM> and a calibration circuitry <NUM>. The delay path <NUM> may include a pair of delay buffers <NUM>, configured to receive one of the pair of differential signals IN, INb, respectively. The delay path <NUM> may include a pair of I-delay circuitries 408A and 408B, configured to receive one of the outputs of the pair of delay buffers <NUM>, respectively, and provide a pair of differential I signals (e.g., <NUM>% I+, <NUM>% I-, which may refer to a pair of differential I signals that has a duty cycle of <NUM>%). The delay path <NUM> may include a pair of Q-delay circuitries 408C and 408D, configured to receive one of the outputs of the pair of delay buffers <NUM>, respectively, and provide a pair of differential Q signals (e.g., <NUM>% Q+, <NUM>% Q-).

One pair of the pair of I-delay circuitries 408A, 408B and the pair of Q-delay circuitries 408C, 408D may receive a control signal Vctrl, which may be configured to adjust the transconductance of the pair such that the IQ signals <NUM> are orthogonal in phase. In the illustrated example, each of the pair of I-delay circuitries 408A and 408B includes delay cells <NUM>. A delay cell <NUM> may include a pair of transistors 424A, 424B sharing a same gate voltage, which may be an output of the pair of delay buffers <NUM> or an output of another delay cell. The delay cell <NUM> may include a pair of back-to-back connected inverters 424C, 424D coupled to an output of the pair of transistors 424A, 424B for phase matching. The delay cell <NUM> may include a delay unit 424E, which may be controlled by the control signal Vcrtl. Although the illustrated delay unit 424E has one transistor, a delay unit may include one or more transistors. Although five delay cells are illustrated, it should be appreciated either I or Q delay circuitry may include any suitable number of delay cells, for example, at least two delay cells. The number of delay cells may be selected depending on, for example, the carrier frequency. The higher the carrier frequency, the smaller the number of delay cells may be needed.

The delay path <NUM> may include a duty-cycle adjustment circuitry <NUM> configured to receive the pairs of differential I signals (e.g., <NUM>% I+, <NUM>% I-) and different Q signals (e.g., <NUM>% Q+, <NUM>% Q-), modify the duty cycles of the pairs of differential I signals and different Q signals, and provide a new pair of differential I signals (e.g., <NUM>% I+, <NUM>% I-) and a new pair of differential Q signals (e.g., <NUM>% Q+, <NUM>% Q-). The duty-cycle adjustment circuitry <NUM> may include four NAND gates A-D configured to provide the new pair of differential I signals (e.g., <NUM>% I+, <NUM>% I-) and the new pair of differential Q signals (e.g., <NUM>% Q+, <NUM>% Q-). In the illustrated example, the NAND gate A provides <NUM>% I+ based on <NUM>% I- and <NUM>% Q+; the NAND gate B provides <NUM>% I- based on <NUM>% I+ and <NUM>% Q-; the NAND gate C provides <NUM>% Q+ based on <NUM>% I+ and <NUM>% Q+; the NAND gate D provides <NUM>% Q- based on <NUM>% I-and <NUM>% Q-.

The calibration circuitry <NUM> may be configured to generate the control signal Vcrtl that is fed back to the delay path <NUM>. The calibration circuitry <NUM> may include a DC filter <NUM> and a low power comparator operational amplifier <NUM>. The DC filter <NUM> may be configured to generate the average pulse width Vavg1 and the average pulse width Vavg2 of the new pair of I signals (e.g., <NUM>% I+, <NUM>% I-) and the new pair of differential Q signals (e.g., <NUM>% Q+, <NUM>% Q-), respectively. The low power comparator operational amplifier <NUM> may be configured to generate a control signal Vctrl based on the average pulse widths Vavg1 and Vavg2. The calibration circuitry <NUM> may modify the value of the control signal Vctrl until the average pulse widths Vavg1 and Vavg2 equal to each other. The equalization of the average pulse widths Vavg1 and Vavg2 enables that the IQ signals are orthogonal in phase as illustrated in <FIG> when T1=T2, compared with T1<T2 or T1>T2.

In some embodiments, an IQ generator may receive as inputs multiple phase outputs of a TTG. <FIG> depicts a portion <NUM> of a DFS receiver, which may include an IQ generator <NUM> configured to receive as inputs multiple phase outputs of a TTG <NUM> (e.g., CK1, CK3) and provide IQ signals <NUM> to a mixer <NUM>. <FIG> depict a time diagram of the IQ generator of <FIG>.

The IQ generator <NUM> may include delay paths 702I, 702Q for respective phase outputs of the TTG <NUM>. The delay paths 702I, 702Q may be configured to convert the multiple phase outputs of the TTG <NUM> into orthogonal signals (e.g., I, Q). In some embodiments, the delay paths 702I, 702Q may be configured similar to the delay path <NUM> in <FIG>, B. In some embodiments, the delay paths of an IQ generator having multiple delay paths may include fewer delay cells than the delay path of an IQ generator having a single delay path.

The IQ generator <NUM> may include a calibration circuitry <NUM>, which may include a DC filter <NUM> and a comparator <NUM>. The DC filter <NUM> may be configured to average pulse widths of the IQ signals, and/or generate a voltage V_comp representing a difference between the average pulse widths of the IQ signals. The comparator <NUM> may be configured to provide control signals Vt_1 and Vt_Q to the delay paths 702I, 702Q, respectively, based on the output of the DC filter <NUM>. As the calibration circuitry <NUM>, the calibration circuitry <NUM> may modify the values of the control signals Vt_1 and Vt_Q until the IQ signals have equal average pulse widths.

Various changes may be made to the illustrative structures shown and described herein. For example, IQ generators was described in connection with WiFi technology. IQ generators may be used in connection with any suitable technology. As a specific example of a possible variation, IQ generators may be used in connection with cellular technology.

Various aspects of the apparatus and techniques described herein may be used alone, in combination, or in a variety of arrangements not specially discussed in the embodiments described in the foregoing description and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

The terms "approximately", "substantially," and "about" may be used to mean within ±<NUM>% of a target value in some embodiments, within ±<NUM>% of a target value in some embodiments, within ±<NUM>% of a target value in some embodiments, and yet within ±<NUM>% of a target value in some embodiments.

Claim 1:
A signal generator for generating signals that are orthogonal in phase, comprising:
a single delay path (<NUM>, <NUM>, 702I, 702Q) comprising input nodes (<NUM>, IN, INb) that receive an input signal of a carrier frequency and output nodes (<NUM>, <NUM>, <NUM>) that provide the signals; and
a calibration circuitry (<NUM>, <NUM>, <NUM>) comprising input nodes that receive the signals and an output node that provides a control signal (Vctrl) to the single delay path,
wherein an operating frequency of the signal generator is less than twice the carrier frequency, wherein the input signal of the carrier frequency has a <NUM>% duty cycle, and
characterized in that the single delay path comprises a circuitry (<NUM>) that receives signals with the <NUM>% duty cycle and provides signals with a <NUM>% duty cycle.