Patent Description:
The following relates generally to fabricating memory cells and more specifically to fabrication of electrodes for memory cells.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic "<NUM>" or a logic "<NUM>. " In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read, or sense, the stored state in the memory device. To store information, a component of the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. FeRAM may use similar device architectures as volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device. FeRAM devices may thus have improved performance compared to other non-volatile and volatile memory devices. <CIT> discloses a phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first chalcogenide compound, a second chalcogenide compound directly on the first nitrogenated carbon material, and a second nitrogenated carbon material directly on the second chalcogenide compound and directly on a second electrode. The nitrogenated carbon material may include trace amounts of additional elements, such as oxygen, and may be formed by PVD.

In some memory devices, the electrical behavior of a memory cell (e.g., one or more threshold voltages of the memory cell) may depend at least in part on physical <NUM>-1Section <NUM> dimensions of the memory cell. Improved solutions for reducing variation in the physical dimensions and thus of the electrical behavior of memory cells associated with a memory device may be desired.

The present invention provides a memory cell apparatus according to independent claim <NUM>. Further advantageous features are set out in the dependent claims.

Some memory devices may be formed, at least in part, by forming a stack of various materials (e.g. a stack of materials may be formed and additional processing steps may be applied to the stack). In some cases, layers of the stack may be formed sequentially, and thus the formation of the stack may involve forming a second layer of the stack above or on top of a first, prior layer of the stack. The method of formation of the first layer may result in that layer having a rough surface and associated variations in thickness. If the second layer of the stack is formed in contact with the uneven first layer, the thickness variation of the first layer may propagate upwards to the next second layer, causing thickness variations in the second layer as well. The thickness variation may impact the behavior of one, both layers, and/or components. For example, the behavior of the material in a given layer as it is exposed to different voltages (e.g., a threshold voltage of the material or the layer) may depend on the thickness of that layer. It may therefore be desirable to minimize the thickness variation of a prior layer to maximize thickness uniformity in the subsequent layer.

In accordance with the teachings herein, fabricating a memory cell may include smoothening (e.g., polishing) a prior layer prior to forming a next layer. For example, a first electrode layer may be fabricated with techniques that result in thickness variations throughout the layer. In some cases, polishing the electrode layer prior to forming an active layer may decrease thickness variations in the electrode layer and consequently, the active layer. Because the electrode layer was polished prior to the active layer formation, the resulting active layer may have less thickness variation than had it been formed without an intermediate polishing step. Therefore, the active layer may have more predictable and uniform behavior. For example, the active layer may behave similarly across multiple memory cells when each memory cell is exposed to the same voltage (e.g., memory cells formed from the active layer may have more uniform threshold voltages). These and other fabrication techniques described herein may thus improve the behavior and performance of memory cells.

Features of the present invention are further described below in the context of the example fabrication techniques of <FIG> and <FIG>. These and other features of the invention are further illustrated by and described with reference to the flowcharts of <FIG> that relate to fabrication of electrodes for memory cells.

<FIG> are schematic depictions of intermediate memory array structures illustrating a method of fabricating a memory cell stack with a smoothened electrode layer, depicted at various stages of fabrication.

Referring to intermediate array structure <NUM>-a of <FIG>, according to some examples, region <NUM>-a may include aspects of an array structure for a first memory cell stack and <NUM>-b may include aspects of an array structure for a second memory cell stack. In some cases, the first memory cell stack and second memory cell stack may eventually be configured as (e.g., fabricated into) two distinct memory cells, and the data stored in the first memory cell may be independent of the data stored in the second memory cell. Although only two regions <NUM>-a and <NUM>-b are shown, one of ordinary skill will appreciate that, in practice, many regions may be formed.

Fabricating the memory cell stack includes forming a conductive material <NUM> over a substrate (not shown). Conductive material <NUM> is used to form one or more access lines, for example a word line or a bit line for a memory cell corresponding to region <NUM>-a and/or region <NUM>-b.

The method includes forming an electrode material <NUM> over the conductive material <NUM>. Electrode material <NUM> is used to form one or more electrodes (e.g., to couple an access line with an active component of a memory cell), for example electrodes respectively corresponding to region <NUM>-a and region <NUM>-b. Electrode material <NUM> includes carbon. In some cases, electrode material <NUM> may consist of two sub-layers (not shown), and thus may be referred to as a bi-layer electrode, where a first sub-layer is in contact with conductive material <NUM> and a second sub-layer is formed above the first sub-layer. In this case, the second, upper sub-layer includes carbon and may be referred to as a carbon-based material. Electrode material <NUM> may be formed, for example, by deposition techniques such as physical vapor deposition (PVD), chemical vaper deposition (CVD), or atomic layer deposition (ALD), among other deposition techniques. Each layer may be initially formed as a blanket layer over the surface area of an entire die or substrate, such as a wafer.

In some examples, deposition techniques used to form electrode material <NUM> (e.g., PVD, CVD, or ALD techniques) may result in the top (e.g., exposed) surface of electrode material <NUM> being undesirably rough, e.g., due to sputtering or other aspects of the relevant deposition techniques. The roughness of the top surface of electrode material <NUM> result in some portions of electrode material <NUM> having different thicknesses than other portions. For example, thickness T1 of electrode material <NUM> may be larger than thickness T2, which may be larger than thickness T3, which may be larger than thickness T4. The electrode material thickness T1-T4 thus may vary within a single memory stack region <NUM>, or between different memory stack regions <NUM>-a and <NUM>-b. That is, in some cases, the thickness of electrode material <NUM> may be larger in one portion of region <NUM>-a than in another portion of <NUM>-b (i.e. T1 > T2). In some other cases, the thickness of electrode material <NUM> may be larger in one region <NUM>-a than in a different region <NUM>-b (i.e. T1,T2 > T3, T4).

Referring now to intermediate array structure <NUM>-b of <FIG>, the method includes smoothening the electrode material <NUM>. The smoothening process smoothens the upper surface of electrode material <NUM> and thereby reduces thickness variations (and thus also increases thickness uniformity) within electrode material <NUM>. In some cases, the smoothening process decreases the thickness variations of electrode material <NUM> within a single memory stack region <NUM>. For example, the thickness of electrode material <NUM> may be the same or substantially the same as thickness T5 throughout region <NUM>-c, whereas the electrode material thickness of region <NUM>-a prior to smoothening may have been more varied (i.e. thickness T1 > thickness T2). The smoothening process also decreases the variation of electrode material thickness between regions <NUM>. For example, electrode material thickness of region <NUM>-c T5 may be the same as or substantially the same as electrode material thickness T6 of region <NUM>-d, whereas prior to smoothening, the thickness of electrode material <NUM> was larger in region <NUM>-a then <NUM>-b (i.e. T1, T2 > T3, T4).

The smoothening process involves polishing electrode material <NUM> using chemical-mechanical planarization (CMP). Intermediate array structure <NUM>-a undergoes a CMP process to form intermediate array structure <NUM>-b. In particular, the top surface of electrode material <NUM> is polished using CMP to form the electrode material <NUM> layer of intermediate array structure <NUM>-b. The polishing process may not change the bulk properties of the electrode material layer <NUM>. For example, relevant properties of electrode material layer <NUM> may remain unchanged as a result of the polishing process. That is, electrode material layer <NUM> may behave similarly when exposed to different voltages and currents after a CMP process as electrode material layer <NUM> would have behaved without the CMP process. According to the present invention, performing CMP involves breaking the vacuum seal that may be associated with a fabrication process used to form electrode material layer <NUM> (e.g., a PVD, CVD, or ALD process), which, at least for some period of time, exposes the top (e.g., exposed) surface of electrode material <NUM> to oxygen. The lack of the vacuum seal thus results in an oxidation occurring at the electrode material <NUM> layer of the intermediate array structure <NUM>-b. Additionally, the CMP process itself results in oxidation occurring at the electrode material <NUM> layer of the intermediate array structure <NUM>-b. Thus, the electrode material <NUM> layer comprises oxidized carbon.

Referring to intermediate array structure <NUM>-c of <FIG>, fabricating the memory cell stack additionally includes forming an active component layer <NUM> over the polished electrode material <NUM>. Active component layer <NUM> is used to form one or more selector components (e.g., selector diodes) or storage components. In some cases, oxidation of electrode material <NUM> layer may be localized or more extensive at or near the surface of electrode material <NUM> layer nearest (e.g., in contact with) an active component layer <NUM>.

The thickness uniformity of active component layer <NUM> is due to the polishing of electrode material <NUM>. That is, any thickness variation of electrode material <NUM> results in an inverse thickness variation in active component layer <NUM>. For example, if electrode material <NUM> is thicker in region <NUM>-e than in region <NUM>-f, active component layer <NUM> may be thinner in region <NUM>-e than in region <NUM>-f.

Active component layer <NUM> is formed of a chalcogenide material. In cases where the chalcogenide material of active component layer <NUM> is used to form one or more selector components, the chalcogenide material of active component layer <NUM> may be maintained in an amorphous state but may be in a high-resistance state (e.g., an insulating state) when a voltage differential across the chalcogenide material is below a threshold magnitude and may be in a low-resistance state (e.g., a conductive state) when the voltage differential across the chalcogenide material is at or above the threshold magnitude. In such cases, the threshold magnitude may comprise a switching threshold voltage for the chalcogenide material of active component layer <NUM>.

In cases where the chalcogenide material of active component layer <NUM> is used to form one or more storage components, the chalcogenide material of active component layer <NUM> may transition between amorphous and crystalline states. In some cases, there may be a large resistance contrast in active component layer <NUM> when active component layer <NUM> is in a crystalline state versus an amorphous state. A material in the crystalline state may have atoms arranged in a periodic structure, which may result in a relatively low electrical resistance (e.g., set state). By contrast, material in an amorphous state may have no or relatively little periodic atomic structure, which may have a relatively high electrical resistance (e.g., reset state). The difference in resistance values between amorphous and crystalline states of a material may be significant; for example, a material in an amorphous state may have a resistance one or more orders of magnitude greater than the resistance of the material in its crystalline state.

In some cases where the chalcogenide material of active component layer <NUM> is used to form one or more storage components, to set a region <NUM> of active component layer <NUM> to a low-resistance state, the region <NUM> may be heated by passing a current through the region <NUM>. Heating a region <NUM> of active component layer <NUM> to an elevated temperature (but below its melting temperature) may result in the region <NUM> of active component layer <NUM> crystallizing and forming the low-resistance state. The current may result from applying a voltage to the region <NUM>, where the applied voltage is based on a first threshold voltage for the region <NUM>. For example, if the region <NUM> is in a reset state, current may not flow through the region <NUM> unless the applied voltage is greater than the first threshold voltage.

In some other cases where the chalcogenide material of active component layer <NUM> is used to form one or more storage components, to set a region <NUM> of active component layer <NUM> to a high-resistance state, the region <NUM> may be heated above its melting temperature. A region <NUM> of the active component layer <NUM> may be switched from the crystalline state to the amorphous state by setting the voltage across the region <NUM> of active component layer <NUM> (and thus the current through the region <NUM> of active component layer <NUM>) to a second threshold voltage, which may increase the temperate of the chalcogenide material beyond a melting temperature, and then removing the voltage/current sufficiently abruptly (e.g., applying the voltage/current for only a relatively brief temporal duration such that crystallization does not occur).

The switching threshold voltage of active component layer <NUM> when used to form one or more selector components, as well as the first and second threshold voltages of active component layer <NUM>, corresponding to a set voltage and a reset voltage of the material of active component layer <NUM> when used to form one or more storage components, may depend on the thickness of active component layer <NUM>. That is, a larger thickness may correspond to larger threshold voltages. Additionally, in variations in thickness of active component layer <NUM> may result in corresponding variations in threshold voltage values. In some cases, it may be desirable to have precise threshold voltages for the entire active component layer <NUM>. For example, it may be desirable for the threshold voltages within region <NUM>-e to be consistent within the region <NUM>-e as well as the threshold voltages within region <NUM>-e to be similar to that of another region <NUM>-f. That is, it may be desirable for the standard deviation of threshold voltages for active component layer <NUM> to be small. In cases where the chalcogenide material of active component layer <NUM> is used to form one or more selector components, threshold voltages with a small standard deviation may provide benefits such as improved reliability and improved design tolerances for a memory device. In cases where the chalcogenide material of active component layer <NUM> is used to form one or more storage components, threshold voltages with a small standard deviation may also provide benefits such as improved reliability and improved design tolerances for a memory device, including a larger or more reliably large window between the first threshold voltage and the second voltage (which may, for example, correspond to a read or write window of a memory cell that includes a region <NUM>).

<FIG> are schematic depictions of additional intermediate memory array structures illustrating a method of fabricating a memory cell stack with a smoothened electrode layer, depicted at various stages of fabrication. The memory array structures shown in <FIG> may correspond to memory array structures as described with reference to <FIG> that have been subsequently processed with additional fabrication steps. For example, conductive material <NUM> of <FIG> may correspond to conductive material <NUM> of <FIG>. Further, electrode material <NUM> of <FIG> may correspond to electrode material <NUM> of <FIG>.

Referring to intermediate array structure <NUM>-a of <FIG>, fabricating the memory cell stack additionally includes forming a second electrode material <NUM> over the first active component layer <NUM>. The second electrode material <NUM> may be a carbon-based material. The second electrode material <NUM> may be formed using similar techniques as the first electrode material <NUM> (e.g., PVD, CVD, ALD). The techniques of formation for second electrode material <NUM> may or may not result in a thickness variation similar to the thickness variation of electrode material <NUM> as seen in intermediate array structure <NUM>-a of <FIG>. That is, in some cases, the thickness of the second electrode material <NUM> when initially formed may vary within a single region <NUM> or between regions, for example between region <NUM>-g and <NUM>-h, which may respectively correspond to region <NUM>-a and <NUM>-b as described in reference to <FIG>.

Fabricating intermediate array structure <NUM>-a may include an additional step of polishing electrode material <NUM>, using CMP for example, to achieve a more uniform thickness. In this case, electrode material <NUM> may come to include oxidized carbon, as polishing intermediate array structure <NUM>-a outside of a vacuum environment may expose the top of the second electrode material <NUM> to oxygen and/or the polishing process itself may introduce oxidation. In some other cases, fabricating the memory cell stack may not include the polishing of the second electrode material <NUM>. In this case, the second electrode material <NUM> may not include oxidized carbon.

Referring to intermediate array structure <NUM>-b of <FIG>, fabricating the memory cell stack includes forming a second active component layer <NUM> above the second electrode material <NUM>. The thickness of the second active component layer <NUM> may be based on the thickness variation of the second electrode material <NUM>. For example, if electrode material is thicker in region <NUM>-i than in region <NUM>-j, the second active component layer <NUM> may be thinner in region <NUM>-i and thicker in region <NUM>-j. Alternatively, if the thickness of the second electrode material <NUM> is uniform across regions <NUM>, the thickness of the second active component layer <NUM> may also be uniform across regions <NUM>.

In some examples, the second active component layer <NUM> may include a cell material to form, for example, one or more storage components or selector components for the memory cell. The second active component layer <NUM> may be formed of chalcogenide materials. In some cases, the second active component layer <NUM> may include the same chalcogenide materials as active component layer <NUM> shown in <FIG>. In some other examples, the second active component layer <NUM> may include different chalcogenide materials (e.g., may have a different stoichiometry) than active component layer <NUM>.

Still referring to <FIG>, fabricating the memory cell stack includes forming a third electrode material <NUM> above the second active component layer <NUM>. The third electrode material <NUM> may be formed using techniques similar to the methods used to form electrode material <NUM> and <NUM> (e.g., PVD, CVD, ALD). In some cases, the formation technique for the electrode material <NUM> may result in a thickness variation and surface roughness similar to the thickness variation and surface roughness of electrode material <NUM> in <FIG>. Fabricating intermediate array structure <NUM>-b may optionally include polishing the third electrode material <NUM> to reduce the thickness variation and thus surface roughness of the third electrode material <NUM>. In the case of polishing the third electrode material <NUM>, the third electrode material <NUM> may include oxidized carbon as a result of polishing intermediate array structure <NUM>-b in a non-vacuum environment, either due to oxygen exposure associated with breaking a vacuum seal or due to the polishing process itself. In some other cases, fabricating the memory cell stack may not include the polishing of the third electrode material <NUM>. In this case, the third electrode material <NUM> may not include oxidized carbon. Thus, a memory device fabricated in accordance with the techniques described herein may include layers that comprise carbon (e.g., carbon electrode layers), and all or any subset of such carbon-based layers may exhibit oxidation. Further such oxidation may be localized or more extensive at or near a polished surface, which may also be a surface exposed to oxygen in connection with a polishing or other smoothening process.

Again referring to <FIG>, fabricating intermediate array structure <NUM>-b includes forming a second conductive material <NUM> above the third electrode material <NUM>. The second conductive material <NUM> may be used to form one or more access lines, for example a bit line or a word line for a memory cell corresponding to region <NUM>-g and/or region <NUM>-h.

In some cases, the method of formation may optionally include etching a space between region <NUM>-i and <NUM>-j in layers <NUM>, <NUM>, <NUM>, and <NUM>. This may create distinct memory cells in regions <NUM>-i and <NUM>-j. However, in the case where the space between region <NUM>-i and <NUM>-j is not etched, the two regions <NUM> may still create distinct memory cells. For example, a voltage applied to active component <NUM> in region <NUM>-i may not sufficiently propagate through the material of active component <NUM> so as to disturb (e.g., corrupt) the logic state stored in region <NUM>-j.

Also, in some examples, the second electrode layer (comprising second electrode material <NUM>) and second active component layer <NUM> may be omitted, and the active component layer <NUM> may be configured as a storage element for a self-selecting memory cell.

In some cases, conductive material <NUM> or <NUM> may be smoothened prior to fabrication of an additional layer (e.g., electrode material <NUM> or <NUM>). The smoothening of conductive material <NUM> and/or <NUM> may reduce thickness variations of the conductive material thus resulting in a corresponding thickness variation reduction of any subsequently formed layers thereupon, such as layers comprising electrode material <NUM> or <NUM>. Further, in some other cases, one or more of active component layer <NUM> or active component layer <NUM> may be smoothened prior to fabrication an additional layer thereon (e.g., prior to fabricating second electrode layer <NUM> and/or prior to fabricating third electrode layer <NUM>). Such additional smoothing of an additional surface of active component layer <NUM> and/or active component layer <NUM> (e.g., an upper surface, whereby a lower surface is smoothened as a result of smoothing an immediately lower layer) may further reduce variation in the thickness of the active component layer, within a region <NUM> or across regions <NUM>, and thus may further reduce variation in one or more threshold voltages of the active component layer (e.g., for set or reset), within a region <NUM> or across regions <NUM>. Where smoothing of a surface of active component layer <NUM> or active component layer <NUM> comprises application of a CMP process, contamination (e.g., chemical contamination) of the active component layer may occur, depending on details of the CMP process, which may present a tradeoff relative to a marginal increase in thickness uniformity.

While not shown for clarity and ease of illustration, it will be understood that the illustrated array structures may be formed above or below other layers (e.g., over a substrate), which can include, among other things, various peripheral and supporting circuitry, for instance complementary metal oxide semiconductor (CMOS) transistors that form a part of column and row driver circuitry and sense amplifier circuitry, as well as sockets and wiring that connect such circuitry to the memory array through the columns and rows described above. In addition, the other layers may include one or more memory arrays, or "decks" of arrays-the structures illustrated in the examples of <FIG> and <FIG> may correspond to one deck of a memory array, and may be above or below any number of additional decks of the memory array.

<FIG> shows a flowchart illustrating a method <NUM> for fabrication of electrodes for memory cells suitable for embodiments of the present invention. The operations of method <NUM> may be implemented in accordance with various fabrication techniques as described herein. For example, the operations of method <NUM> may be implemented by the fabrication techniques as discussed with reference to <FIG> and <FIG>.

At <NUM> a metal layer for an access line is formed. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

At <NUM> an electrode layer for a memory cell is formed above the metal layer. In some examples, a surface of the electrode layer has an initial surface roughness. In some examples, the electrode layer may be formed by deposing the electrode material via a deposition process. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

At <NUM> the surface of the electrode layer is polished. In some examples, the polishing may change the surface from having the initial surface roughness to having a subsequent surface roughness that is less than the initial surface roughness. In certain examples, the polishing may be done by applying a CMP process to the surface of the electrode layer. In some cases, polishing the surface of the electrode layer may include breaking a vacuum seal associated with the deposition process. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

At <NUM> an active layer is formed after the polishing. In some examples, the active layer may be in contact with the surface of the electrode layer. The uniformity of a thickness of the active layer may be based on the subsequent surface roughness. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

In some examples, an apparatus may perform aspects of the fabrication described above using general- or special-purpose hardware. The apparatus may include features, means, or instructions for forming the metal layer for the access line. The apparatus may further include features, means, or instructions for forming, above the metal layer, an electrode layer for a memory cell, where a surface of the electrode layer has an initial surface roughness. The apparatus may also include features, means, or instructions for polishing the surface of the electrode layer to change the surface from having the initial surface roughness to having a subsequent surface roughness that is less than the initial surface roughness. The apparatus may additionally include features, means, or instructions for forming, after the polishing, an active layer in contact with the surface of the electrode layer, where a uniformity of a thickness of the active layer is based on the subsequent surface roughness.

In some examples of the method and apparatus described above, polishing the surface of the electrode layer may include applying a CMP process to the surface of the electrode layer. In some examples of the method and apparatus, forming the electrode layer may include depositing an electrode material via a deposition process. In some cases, polishing the surface of the electrode layer may include breaking a vacuum seal associated with the deposition process.

Some examples of the method and apparatus described above may further include processes, features, means, or instructions for forming a second electrode layer for the memory cell above the active layer. Some examples of the method and apparatus described above may further include processes, features, means, or instructions for forming a second active layer above the second electrode layer. Some examples of the method and apparatus described above may further include processes, features, means, or instructions for polishing a surface of the second electrode layer before forming the second active layer to change the surface of the second electrode layer from a second initial surface roughness to a second subsequent surface roughness that may be less than the second initial surface roughness.

Some examples of the method and apparatus described above may further include processes, features, means, or instructions for polishing a surface of the active layer before forming the second electrode layer. Some examples of the method and apparatus described above may further include processes, features, means, or instructions for polishing a surface of the second active layer. In some examples of the method and apparatus described above, a storage component for the memory cell comprises at least a portion of the second active layer. In some examples of the method and apparatus described above, the active layer may include a first chalcogenide material. In some examples, the second active layer may include a second chalcogenide material, the second chalcogenide material different from the first chalcogenide material. In some examples of the method and apparatus described above, the electrode layer and the second electrode layer each comprise carbon.

Some examples of the method and apparatus described above may further include processes, features, means, or instructions for forming a third electrode layer for the memory cell above the second active layer. Some examples of the method and apparatus described above may further include processes, features, means, or instructions for forming a second metal layer for a second access line for the memory cell, the second metal layer above the third electrode layer. Some examples of the method and apparatus described above may further include processes, features, means, or instructions for polishing a surface of the third electrode layer prior to forming the second metal layer.

At <NUM> a metal layer for an access line is formed. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be using the fabrication techniques discussed with references to <FIG> and <FIG>.

At <NUM> an electrode layer for a memory cell is formed above the metal layer. In some examples, a surface of the electrode layer has an initial surface roughness. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

At <NUM> the surface of the electrode layer is polished. In some examples, the polishing may change the surface from having the initial surface roughness to having a subsequent surface roughness that is less than the initial surface roughness. In certain examples, the polishing may be done by applying a CMP process to the surface of the electrode layer. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

At <NUM> a second electrode layer for the memory cell is formed above the active layer. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

At <NUM> a surface of the second electrode layer is polished before forming the second active layer. In some examples, polishing the surface of the second electrode layer may change the surface of the second electrode layer from a second initial surface roughness to a second subsequent surface roughness that is less than the second initial surface roughness. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

At <NUM> the second active layer is formed above the second electrode layer. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques discussed with reference to <FIG> and <FIG>.

<FIG> shows a flowchart illustrating a method <NUM> for fabrication of electrodes for memory cells suitable for embodiments of the present invention. The operations of method <NUM> may be implemented in accordance with various fabrication techniques as described herein. For example, the operations of method <NUM> may be implemented by the fabrication techniques as discussed with references to <FIG> and <FIG>.

At <NUM> a metal layer for an access line is formed. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques as discussed with reference to <FIG> and <FIG>.

At <NUM> a first electrode layer comprising carbon is formed above the metal layer. In some cases, the first electrode layer may be for a memory cell. In some examples, forming the first electrode layer may include depositing an electrode material via a deposition process. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques as discussed with reference to <FIG> and <FIG>.

At <NUM> the surface roughness of an upper surface of the first electrode layer is reduced. In some examples, the upper surface roughness may be reduced by applying a CMP process to the upper surface of the first electrode layer. In some other examples, applying the CMP process to the upper surface of the first electrode layer may include breaking a vacuum seal associated with the deposition process. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed by using the fabrication techniques as discussed with reference to <FIG> and <FIG>.

At <NUM> a chalcogenide layer is formed in contact with the upper surface of the first electrode layer after applying the CMP process. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques as discussed with reference to <FIG> and <FIG>.

At <NUM> a second electrode layer comprising carbon is formed above the chalcogenide layer. In some examples, the second electrode layer may be for the memory cell. The operations of <NUM> may be performed according to the methods described herein. In certain examples, aspects of the operations of <NUM> may be performed using the fabrication techniques as discussed with reference to <FIG> and <FIG>.

In some examples, an apparatus may perform aspects of the fabrication described using general or special-purpose hardware. The apparatus may include features, means, or instructions for forming a metal layer for an access line and form, above the metal layer, a first electrode layer comprising carbon for a memory cell. The apparatus may additionally include features, means, or instructions for reducing a surface roughness of an upper surface of the first electrode layer by applying a CMP process to the upper surface of the first electrode layer. The apparatus may further include features, means, or instructions for forming a chalcogenide layer in contact with the upper surface of the first electrode layer after applying the CMP process and form, above the chalcogenide layer, a second electrode layer comprising carbon for the memory cell.

Some examples of the method and apparatus described above may further include processes, features, means, or instructions for reducing a surface roughness of an upper surface of the second electrode layer by applying a second CMP process to the upper surface of the second electrode layer. Some examples of the method and apparatus described above may further include processes, features, means, or instructions for forming a second chalcogenide layer in contact with the upper surface of the second electrode layer, where a thickness of the second chalcogenide layer may be based on reducing the surface roughness of the upper surface of the second electrode layer. Some examples of the method and apparatus described above may further include processes, features, means, or instructions for forming a second chalcogenide layer in contact with the upper surface of the second electrode layer, where a thickness of the second chalcogenide layer may be based on an initial surface roughness of the upper surface of the second electrode layer.

Further, embodiments from two or more of the methods may be combined.

In some cases, a device, system, or apparatus fabricated in accordance with various fabrication techniques as described herein may include a first access line for a memory cell, a first electrode for the memory cell, the first electrode disposed above the first access line and comprising oxidized carbon, and an active component for the memory cell, the active component in contact with the first electrode and comprising chalcogenide.

In embodiments of the device, system, or apparatus described above, in accordance with the present invention, the oxidized carbon is realized by oxidation of carbon based at least in part on a CMP process associated with the first electrode. In particular, the oxidized carbon is realized by oxidation of carbon based at least in part on breaking a vacuum seal in association with the CMP process and based at least in part on the CMP process itself. In some examples of the device, system, or apparatus described above, the active component for the memory cell may include a selection component, a storage component, or a combination thereof the memory cell.

In some examples, the device, system, or apparatus may further include a second electrode for the memory cell. The device, system, or apparatus may also include a second active component for the memory cell, where the second active component may be in contact with the second electrode and may comprise chalcogenide. In some examples, the first electrode may have a first surface in contact with the active component, the first surface having a first roughness. Further, the second electrode may include a second surface in contact with the second active component, where the second surface has a second roughness that may be greater than the first roughness.

In some cases of the device, system, or apparatus described above, the active component may comprise a first chalcogenide material. In some examples, the second active component may comprise a second chalcogenide material, where the second chalcogenide material may be different from the first chalcogenide material. In some other examples, the active component and the second active component may comprise a same chalcogenide material. In some examples, the second electrode may include oxidized carbon. In some cases, the first electrode comprises two sub-layers, where the sublayer that is in contact with the active component may comprise carbon.

In some cases, the device, system, or apparatus described above may include a third electrode for the memory cell, the third electrode in contact with the second active component. The device, system, or apparatus may further include a second access line for the memory cell. In some examples, the third electrode may include oxidized carbon.

The term "coupled" refers to a relationship between components that support electron flow between the components. This may include a direct connection between components or may include intermediate components. Components in electronic communication or coupled to one another may be actively exchanging electrons or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but may be configured and operable to exchange electrons or signals on a circuit being energized. By way of example, two components physically connected via a switch (e.g., a transistor) may be coupled regardless of the state of the switch (i.e., open or closed).

The term "layer" used herein refers to a stratum or sheet of a geometrical structure. each layer may have three dimensions (e.g., height, width, and depth) and may cover some or all of a surface. For example, a layer may be a three-dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers may include different elements, components, and/or materials. In some cases, one layer may be composed of two or more sublayers. In some of the appended figures, two dimensions of a three-dimensional layer are depicted for purposes of illustration. Those skilled in the art will, however, recognize that the layers are three-dimensional in nature.

As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough so as to achieve the advantages of the characteristic.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory arrays.

Chalcogenide materials may be materials or alloys that include at least one of the elements S, Se, and Te. Phase change materials discussed herein may be chalcogenide materials. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, or Ge-Te-Sn-Pt. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular compound or alloy and is intended to represent all stoichiometries involving the indicated elements. For example, Ge-Te may include GexTey, where x and y may be any positive integer. Other examples of variable resistance materials may include binary metal oxide materials or mixed valence oxide including two or more metals, e.g., transition metals, alkaline earth metals, and/or rare earth metals. Embodiments are not limited to a particular variable resistance material or materials associated with the memory elements of the memory cells. For example, other examples of variable resistance materials can be used to form memory elements and may include chalcogenide materials, colossal magnetoresistive materials, or polymer-based materials, among others.

The devices discussed herein may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the embodiments that may be implemented or that are within the scope of the claims. The detailed description includes specific details for the purpose of providing an understanding of the described techniques.

As used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

Claim 1:
An apparatus (<NUM>-c; <NUM>-a; <NUM>-b), comprising:
a first access line (<NUM>; <NUM>) for a memory cell (<NUM>-e; <NUM>-f; <NUM>-g; <NUM>-h; <NUM>-i; <NUM>-j);
a first electrode (<NUM>; <NUM>) for the memory cell, the first electrode disposed above the first access line and comprising oxidized carbon;
an active component (<NUM>; <NUM>) for the memory cell, the active component (<NUM>; <NUM>) in contact with the first electrode (<NUM>; <NUM>) and comprising chalcogenide,
characterized in that the oxidized carbon is realized by oxidation of carbon based at least in part on a chemical-mechanical planarization, CMP, process (<NUM>) associated with the first electrode (<NUM>; <NUM>) and based at least in part on breaking a vacuum seal in association with the CMP process.