Patent Description:
In typical networking devices, various switches are used in integrated circuits to support different functionalities. For example, a cellular transceiver may support carrier aggregation, which allows for the simultaneous reception of two independent frequency channels. In order to provide simultaneous reception, at least two receive mixers, each driven by an independent frequency divider, are used. These frequency dividers are driven or clocked by one of two different voltage-controlled oscillators (VCOs) that run concurrently. Each divider clock input is also selectable between the two VCOs, and a two-to-one input switch network is often used.

In these types of circuits, the VCOs generally run simultaneously at different frequencies. Therefore, a high degree of isolation between switches is desirable to reduce energy coupling through a disabled switch. For example, when energy passes through a disabled switch, a spur could occur on the input to the frequency dividers. The spur may propagate through the frequency dividers and onto the receive mixer, resulting in unwanted signals mixed into the desired band. By providing isolation between the input switches, energy passing through a disabled switch is reduced.

A multiple switch circuit may be used to provide high isolation. For example, good isolation can be achieved by using two switches in series with a ground shunt switch placed between them. However, this type of scheme requires the two series pass switches to be at least two times larger to provide a comparable resistance of a single switch circuit. Consequently, the total parasitic capacitance of these two series switches in combination with the shunt switch is about four times larger than the capacitance associated with a single switch. This not only limits the operating frequency range of these switches, but also increases power consumption.

<CIT> discloses that a semiconductor switching circuit device includes a field effect transistor having a source, a gate electrode and a drain electrode, a first electrode pad connected to the source electrode or the drain electrode, and a second electrode pad connected to the source electrode or the drain electrode which is not connected to the first electrode pad.

<CIT>discloses methods and apparatus that are provided for RF switches integrated in a monolithic RF transceiver IC and switched gain amplifier.

<CIT>discloses an integrated circuit device that includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx.

<CIT> discloses a switch circuit that includes a transmission unit configured to transmit a signal through a transistor, in which a back gate and a source are connected by way of a resistor; and a back gate control unit configured to connect the back gate of the transistor to a fixed potential when the transistor is turned OFF, and to separate the back gate of the transistor from the fixed potential when the transistor is turned ON.

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

Various embodiments are described within a specific context, namely a two-to-one input switch network. However, various embodiment devices may be used in any integrated circuit, particularly where active devices (e.g., switches) having improved isolation are desirable.

<FIG> illustrate an example circuit <NUM> of a two-to-one input switch network in accordance with some embodiments. Circuit <NUM> receives two input signals <NUM> and <NUM>, which are provided as differential signals <NUM>p/<NUM>m and <NUM>p/<NUM>m, respectively. Each of the differential input signals <NUM>p/<NUM>m/<NUM>p/<NUM>m is connected to a source of a corresponding switch <NUM>. In another embodiment, the input signals may be connected to drains of each switch <NUM>. In the illustrated embodiments, switches <NUM> are n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), although other types of active devices, such as p-type transistors, may also be used in other embodiments. Drains of each respective switch <NUM> provide an output signal <NUM>, which is also a differential signal. In another embodiment, the input and/or output signals may be non-differential signals. In another embodiment, the output signal may be provided by sources of each of switch <NUM>. Gates of each switch <NUM> are connected to a respective switch controller <NUM>, which selects one of the two input signals as an output by enabling or disabling each switch <NUM> (e.g., selecting an "on" or "off" state of each switch). A respective switch controller <NUM> independently drives each switch <NUM> although other controller schemes may also be used. An example circuit topology for a suitable switch controller <NUM> is provided in <FIG> although other controller configurations may also be used.

Each switch <NUM> in circuit topology <NUM> provides relatively high isolation through embodiment layout techniques within switches <NUM> as described in greater detail below. Thus, additional isolation devices (e.g., additional switches) need not be included in the circuit topology and layout. For example, each differential input signal is connected to a single switch <NUM> as opposed to a multi-switch circuit. By reducing the number of active devices (switches) in the circuit, the overall capacitance and power consumption of circuit topology <NUM> is reduced while still maintaining high isolation. Given the large number of switches in a device application (e.g., in an oscillator distribution path of a cellar handset), even minute power savings may provide significant advantages.

<FIG> and <FIG> illustrate varying layout views of a switch <NUM> in circuit <NUM> according to some embodiments. <FIG> illustrate cross-sectional views of switch <NUM> while <FIG> illustrates a corresponding top-down view of conductive lines over switch <NUM>. Specifically, <FIG> illustrates a cross-section taken across line A-A of <FIG>, <FIG> illustrates a cross-section taken across line B-B of <FIG>, and <FIG> illustrates a cross-section taken across line C-C of <FIG>. Switch <NUM> includes various isolation features provided by embodiment layout configurations as described in greater detail below.

Referring first to <FIG>, switch <NUM> is formed at a top surface of a semiconductor substrate <NUM>. In some embodiments, semiconductor substrate includes, for example, bulk silicon. Alternatively, substrate <NUM> may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

Substrate <NUM> includes an isolation region <NUM> and an isolated dopant region <NUM>. Isolation region <NUM> and isolated dopant region <NUM> may be doped with n-type and p-type dopants at any suitable concentration, and isolation region <NUM> and isolated dopant region <NUM> are doped with dopants of opposing types. For example, in the illustrated embodiments, isolation region <NUM> is a deep n-well (DNW) while dopant region <NUM> is a p-well for a p-type substrate. Switch <NUM> is disposed within dopant region <NUM>. Isolation region <NUM> isolates dopant region <NUM> from stray energy in the surrounding substrate <NUM>. For example, isolation region <NUM> is disposed under and encircles a perimeter of dopant region <NUM>. In some embodiments, switch <NUM> is placed in the vicinity of numerous other active devices (e.g., other switches, transistors, diodes, and the like) also formed in substrate <NUM>, and energy may leak from nearby devices into substrate <NUM>. By placing switch <NUM> within isolated dopant region <NUM>, the risk of energy in substrate <NUM> being coupled (e.g., capacitive coupling) to switch <NUM> is reduced. Furthermore, isolation region <NUM> is tied to power supply (e.g., by conductive lines and vias), which advantageously lowers isolation region <NUM>'s series resistance to supply.

Switch <NUM> includes source/drain regions <NUM> (labeled <NUM>' and <NUM> ") and gates <NUM> disposed between adjacent source/drain regions <NUM>. Each source/drain region <NUM> is disposed on opposing sides of a corresponding gate <NUM>. Source/drain regions <NUM> may be active regions of substrate <NUM>, which are doped with dopants of a suitable type and concentration (e.g., N+ in the illustrated embodiments for an NMOS transistor). Gates <NUM> may include a gate dielectric (e.g., a high-k dielectric layer), a gate electrode (e.g., polysilicon or a metal) over the gate dielectric, and various interfacial/spacer/hard mask layers as applicable. In <FIG>, switch <NUM> is configured as a dual-gate transistor (e.g., a two finger NMOS transistor) having two drain regions and one source region; however, any suitable transistor configuration (e.g., single gate transistors) may be used. Furthermore, although <FIG> illustrates switch <NUM> as an n-type transistor, a p-type transistor may also be used. In such embodiments, the dopant type of various active areas (e.g., isolation region <NUM>, dopant region <NUM>, source/drain regions, and dopant region <NUM>) may be reversed.

Dopant regions <NUM>, having dopants of an opposing type as source/drain regions <NUM> are disposed adjacent to outer source/drain regions <NUM>' within isolated dopant region <NUM>. For example, in the illustrated embodiments, source/drain regions <NUM> are N+ regions and dopant region <NUM> are P+ regions. A dopant concentration of dopant region <NUM> may be higher than surrounding dopant region <NUM>. Dopant regions <NUM> are electrically coupled to ground (e.g., electrically connected by an interconnect structure <NUM> to ground). Thus, the interconnect structure is referred to as a grounded conductive wall <NUM> hereinafter. Grounded conductive wall <NUM> includes conductive lines and vias formed in various dielectric layers using any suitable method. For example, the dielectric layers may include low-k dielectric materials having k-values, for example, lower than about <NUM> or lower than about <NUM>, formed by spinning, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), and the like. After each dielectric layer is formed, a patterning process (e.g., a combination of photolithography and etching) may be used to pattern openings in the dielectric layers. Subsequently, such openings are filled with a conductive material (e.g., copper, aluminum, tungsten, combinations thereof, and the like) using any suitable method (e.g., electro-chemical plating, electroless plating, and the like) to form various conductive vias and conductive lines M1 through M5 as illustrated. Throughout the description M1 indicates a conductive line layer closest to substrate <NUM>, M2 indicates a conductive line layer immediately above M1, M3 indicates a conductive layer immediately above M2, and so on.

Dopant regions <NUM> are included to collect energy injected into dopant region <NUM> by active regions of switch <NUM> (e.g., source/drain regions <NUM> and channel regions) when switch <NUM> is enabled or disabled. For example, when switch <NUM> is enabled (e.g., in an "on" state), dopant regions <NUM> are used to keep energy from escaping into the surrounding substrate <NUM>. As another example, when switch <NUM> is disabled (e.g., in an "off" state), dopant regions <NUM> are used to lower the energy coupling between adjacent source/drain regions <NUM>. Thus, dopant regions <NUM> may be used to reduce stray energy from accumulating in dopant region <NUM>. Instead, dopant regions <NUM> collect and shunt this energy to electrical ground. In some embodiments, dopant regions <NUM> are disposed adjacent (e.g., as close as possible) to active source/drain regions <NUM> for improved energy collection. Dopant region <NUM> may also collect energy injected into dopant region <NUM> through the isolation region <NUM> from the surrounding substrate <NUM>.

Gates <NUM> are electrically coupled to a control circuit (e.g., controller <NUM>), which selects whether to pass an input signal to an output of switch <NUM> by turning switch <NUM> "on" or "off". A source/drain region <NUM>" is electrically coupled to an input signal <NUM>/<NUM>. For example, source/drain regions <NUM>" are electrically connected to input signal <NUM>/<NUM> by conductive lines 214I as illustrated by <FIG> and <FIG>. Source/drain regions <NUM>' are electrically coupled to an output signal <NUM>. For example, source/drain regions <NUM>' are electrically connected to output signal <NUM> by conductive lines <NUM> as illustrated by <FIG> and <FIG>. In another embodiment, the configuration of the input and output signals may be reversed depending on whether the input signal or the output signal benefits from less parasitic capacitance. For example, in another embodiment, the source/drain region <NUM>" may be electrically connected to an output signal <NUM> by conductive line 214I (an M1 line) and 220I (an M6 line). In the illustrated embodiments, less parasitic capacitance is desired at the input, so the input of the switch is connected to a conductive line 214I and 220I.

In order to reduce electrical coupling between source/drain regions <NUM> when switch <NUM> is disabled (e.g., in an "off" state), grounded conductive lines <NUM>' are disposed between adjacent conductive lines 214I and <NUM>. Grounded conductive lines <NUM>' are electrically coupled to ground. For example, grounded conductive wall <NUM> may electrically connect conductive lines <NUM>' to ground, and grounded conductive lines <NUM>' may be used to pass coupled energy from source/drain regions <NUM> when switch <NUM> is disabled to ground. Grounded conductive lines <NUM>' are aligned between adjacent source/drain regions <NUM> in semiconductor substrate <NUM>. For example, at least a portion of each grounded conductive lines <NUM>' is aligned with a gate <NUM>. A geometric line substantially perpendicular with a lateral surface of the substrate may intersect both gate <NUM> and grounded conductive line <NUM>'.

In some embodiments, an active area of switch <NUM> (e.g., the spacing and size of source/drain regions <NUM>) may be increased to accommodate the placement of grounded conductive lines <NUM>' above and aligned between source/drain regions <NUM>. In some embodiments, gates <NUM> may further be positioned to reduce capacitance of the active area on the input rather than the output to further reduce power consumption. For example, as illustrated by the figures, outer source/drain regions <NUM>' are configured to have a larger lateral dimension. This configuration also accommodates the placement of conductive lines <NUM>' aligned between adjacent source/drain regions <NUM>.

<FIG> and <FIG> illustrate cross-sectional views of input/output lines <NUM>. Specifically, input line 220I provides an input signal <NUM>/<NUM> to conductive line 214I (e.g., an M1 line), which is electrically connected to an inner source/drain region <NUM>" of switch <NUM>. Furthermore, output line <NUM> is used to take an output signal <NUM> from conductive line <NUM> (e.g., an M1 line), which is electrically connected to an outer source/drain region <NUM>' of switch <NUM>. In various embodiments, input and output lines <NUM> are disposed in higher metal layers than M1 to reduce electrical coupling with substrate <NUM>. In some embodiments, input and output lines <NUM> are further positioned in non-adjacent metal layers to reduce coupling between input line 220I and output line <NUM>, particularly in areas where input line 220I and output line <NUM> intersect. For example, in <FIG> and <FIG>, input line 220I is in conductive line layer M6 while output line <NUM> is in conductive line layer M4. At least one conductive line layer (M5) is disposed between input line 220I and output line <NUM>. The specific metal layer configuration illustrated is but one example embodiment, and various conductive lines may be disposed in other configurations. For example, the output line <NUM> may be disposed in a higher conductive line layer than input line 220I in another embodiment.

Referring to <FIG>, various conductive interconnect features <NUM> (e.g., conductive vias and lines) are used to electrically connect input line 220I in a higher conductive line layer (e.g., M6) to conductive line 214I in layer M1. Referring to <FIG>, various conductive interconnect features <NUM> (e.g., conductive vias and lines) are used to electrically connect output line <NUM> in a higher conductive line layer (e.g., M4) to conductive line <NUM> in layer M1. In various embodiments, input/output lines and interconnect features <NUM>/<NUM> may be formed of similar materials using similar methods as grounded conductive wall <NUM> as described above. Isolation features are included to reduce electrical coupling between interconnect features <NUM> and <NUM>. For example, a grounded conductive wall <NUM> may be disposed between interconnect features <NUM> and <NUM> as illustrated by <FIG>. Grounded conductive wall <NUM> includes conductive lines in layers M1 through M5 and provides a wall of electrical isolation in layers having both interconnect features <NUM> and <NUM> (e.g., layers M1 through M4). Additional redistribution layers having conductive lines/vias (e.g., providing signals, power, and/or ground) may also be included in circuit <NUM>. Other features such as contact pads, passivation layers, solder balls, and the like may also be formed over the redistribution layers as part of a device die containing circuit <NUM>.

Thus, as described above, various features may be included in a switch for improved isolation. Such a switch may be used in an integrated circuit where such isolation is desirable in lieu of multi-switch isolation circuits, thus reducing power consumption of the device. For example, simulations were conducted using a switch having isolation features as described above in a circuit similar to circuit layout <NUM>. A realistic load was placed at the output and each input was driven by a different frequency signal (e.g., a first frequency of <NUM> and a second frequency of <NUM>). One switch was disabled while the other was enabled. The switch and its load were laid out and extracted. At the output of the switches, the passed signal had a magnitude of <NUM> dB while the disabled signal had a magnitude of - <NUM> dB, for a difference of <NUM> dB. An isolation target for these types of circuits is about <NUM> dB.

Claim 1:
An integrated circuit comprising:
a switch (<NUM>) comprising:
a first gate (<NUM>);
a first source/drain region (<NUM>' ) at a top surface of a semiconductor substrate;
and
a second source/drain region (<NUM> ") at the top surface of the semiconductor substrate, wherein the first source/drain region (<NUM>' ) and the second source/drain region (<NUM>") are disposed on opposing sides of the first gate (<NUM>);
wherein the first gate (<NUM>) is coupled to a control circuit that is configured to select whether to pass an input signal to an output of the switch (<NUM>);
wherein the first source/drain region (<NUM>') is electrically coupled to the input signal by a first conductive line (<NUM>);
wherein the second source/drain region (<NUM>") is electrically coupled to output signal by a second conductive line (214I);
wherein a third conductive line (<NUM>') is disposed between the first conductive line (<NUM>) and the second conductive line (214I), characterized in that the third conductive line (<NUM>') is electrically coupled to ground, and wherein the third conductive line (<NUM>') is disconnected from the first gate (<NUM>).