Patent Description:
Memory is one type of integrated circuitry, and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digit lines (which may also be referred to as bitlines, data lines, sense lines, or data/sense lines) and access lines (which may also be referred to as wordlines). The digit lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a digit line and an access line.

Memory cells may be volatile or nonvolatile. Nonvolatile memory cells can store data for extended periods of time including when the computer is turned off. Volatile memory dissipates and therefore is rapidly refreshed/rewritten, in many instances multiple times per second. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a "<NUM>" or a "<NUM>". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

Some memory cells may include a transistor in combination with a capacitor (or other suitable charge-storage device). The transistor is utilized to selective access the capacitor, and may be referred to as an access device. The capacitor may electrostatically store energy as an electric field within capacitor dielectric between two capacitor plates. The electrical state of the capacitor may be utilized to represent a memory state.

<CIT> relates to a DRAM that includes a plurality of transistors parallel to each other and formed above a substrate. A bit line is perpendicular to each of the plurality of transistors, and is coupled to the transistors. A predetermined portion of each transistor is a storage node for a capacitor, and a plate surrounds the predetermined portion through a dielectric film. <CIT> discloses a transistor and semiconductor memory device. <CIT> discloses a memory device that is as small in area as possible and has an extremely long data retention period. <CIT> discloses a semiconductor memory device and method for driving the same.

Integrated memory may be formed in a three-dimensional memory array in which memory cells are vertically stacked one atop another. A region of an example three-dimensional memory array <NUM> is diagrammatically illustrated in <FIG>. The memory array <NUM> comprises a first set of conductive lines extending vertically relative to an underlying supporting substrate <NUM>, and a second set of conductive lines extending horizontally across the memory array. The conductive lines of the first set are labeled as digit lines DL1, DL2, DL3, and DL4; and the conductive lines of the second set are labeled as wordlines WL1, WL2 and WL3. The digit lines extend along columns of the memory array, with such columns being labeled as Column A, Column B, Column C and Column D. The wordlines extend along rows of the memory array, with such rows being labeled as Row <NUM>, Row <NUM> and Row <NUM>.

The memory array <NUM> comprises a plurality of memory cells, with each of the memory cells being uniquely addressed by one of the digit lines and one of the wordlines. The memory cells are labeled with descriptors indicating their locations relative to the rows and columns. For instance, the memory cell along Column A and Row <NUM> is labeled as Cell A1; the memory cell along Column B and Row <NUM> is labeled as Cell B1, etc. The memory cells include a transistor (T) in combination with a capacitor (C). Each transistor has a source/drain region coupled with an associated digit line (such coupling is diagrammatically illustrated with lines <NUM>), and has another source/drain region coupled with a storage node of the capacitor (such coupling is diagrammatically illustrated with lines <NUM>). Each transistor also has a gate coupled with a wordline passing across the transistor.

The transistors will include channel material between the source/drain regions (with example channel material being shown and described below with reference to <FIG>). In some embodiments, it is recognized that it can be advantageous to utilize gallium phosphide (GaP) as channel material within the vertically-stacked memory cells of the memory array <NUM> of <FIG>. The GaP may provide advantages of a large bandgap, reasonable mobility of charge carriers, and compatibility with a silicon lattice. In some aspects, it is recognized that GaP may be advantageous over silicon and other semiconductor materials for utilization in the channel regions of the vertically-stacked memory cells due to the large bandgap and the reasonable mobility of charge carriers. Accordingly, it is recognized that it may be advantageous to incorporate GaP into the transistors of the vertically-stacked memory cells.

The GaP channel material may be advantageous in numerous configurations of vertically-stacked memory cells. An example configuration is described with reference to <FIG>. Specifically, <FIG> shows an expanded region of a portion of the memory array <NUM> comprising the Cell A1. The other memory cells of memory array <NUM> may have a configuration substantially identical to that of the illustrated Cell A1; with the term "substantially identical" meaning identical to within reasonable tolerances of fabrication and measurement.

The illustrated region of memory array <NUM> includes the digit line DL1 extending vertically through the memory cell A1. Insulative regions <NUM> are above and below the memory cell A1, with such insulative regions comprising insulative material <NUM>. The insulative material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

In some embodiments, the memory cell A1 may be considered to be part of a memory tier <NUM> which is vertically between insulative tiers corresponding to the insulative regions <NUM>. The tier <NUM> may also include the memory cells B1, C1 and D1 of <FIG>, with such memory cells being horizontally displaced relative to the memory cell A1; and additional memory tiers may be vertically displaced relative to the tier <NUM>, with such additional tiers comprising the memory cells A2, A3, B2, B3, etc., of <FIG>.

Continuing the description of <FIG>, the memory cell A1 includes the transistor T and the capacitor C. The transistor T has a gate <NUM> comprising a conductive gate material <NUM>. The conductive gate material <NUM> may comprise any suitable electrically conductive materials, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.).

The transistor T also includes a channel region <NUM> spaced from the gate <NUM> by a dielectric region <NUM>.

The channel region reform comprises channel material <NUM>, which is indicated to include GaP. The GaP may be doped to an appropriate threshold voltage with any suitable dopant, and may be n-type or p-type. Example dopants which may be utilized include arsenic, zinc, sulfur, tellurium, silicon, germanium, tin, etc..

The dielectric region <NUM> comprises dielectric material <NUM>. The dielectric material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon dioxide, aluminum oxide, hafnium oxide, etc. In some embodiments, the dielectric material <NUM> may be referred to as gate dielectric material.

The transistor T includes a first source/drain region <NUM> and a second source/drain region <NUM>, with the first and second source/drain regions being vertically displaced relative to one another. The source/drain regions <NUM> and <NUM> comprise conductive materials <NUM> and <NUM>, respectively. Such conductive materials may include any suitable composition or combination of compositions; such as, for example, conductively-doped semiconductor material (e.g., conductively-doped silicon), metal (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), etc. Generally, the source/drain regions <NUM> and <NUM> do not comprise GaP, but instead comprise conductive material compatible with GaP and suitable for utilization as source/drain regions in a transistor configuration utilizing GaP as channel material. The conductive materials <NUM> and <NUM> of source/drain regions <NUM> and <NUM> may be the same as one another in some embodiments, and in other embodiments may be different from one another. For instance, in some embodiments the first source/drain region <NUM> may comprise conductively-doped silicon, and the second source/drain region <NUM> may comprise metal and/or one or more metal containing compositions.

The digit line DL1 may comprise any suitable electrically conductive material(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The first source/drain region <NUM> is electrically coupled with the digit line DL1, and in the shown embodiment is directly against the digit line DL1.

In some embodiments, there may be no source/drain region <NUM> contact as shown, but instead GaP <NUM> may extend to directly contact the digit line DL1. Also, in some embodiments, the digit line DL1 may be constructed to comprise an outer layer of one material (e.g., doped silicon) and an inner core of a second material (e.g., metal or metal-containing material). A structure eliminating the shown source/drain region <NUM> and instead directly coupling GaP <NUM> to the digit line DL1 may be built with fewer process steps than the illustrated structure in some applications.

The second source/drain region <NUM> is electrically coupled with a first electrode (storage node) <NUM> of the capacitor C. The capacitor C also includes a second electrode <NUM>, and a capacitor dielectric region <NUM> between the first and second electrodes <NUM> and <NUM>.

The electrodes <NUM> and <NUM> comprise conductive materials <NUM> and <NUM>, respectively. Such conductive materials may be any suitable materials, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The electrodes <NUM> and <NUM> may comprise a same composition as one another, or may comprise different compositions relative to one another.

The capacitor dielectric region <NUM> comprises dielectric material <NUM> (which may be referred to as capacitor dielectric material). Such dielectric material may comprise any suitable composition or combination of compositions; and in some embodiments may comprise silicon dioxide, silicon nitride, etc. In some embodiments, the capacitor dielectric material may comprise a ferroelectric material.

The gate <NUM> of transistor T is spaced from the first electrode <NUM> of capacitor C by insulative material <NUM>. The insulative material <NUM> may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

A segment of the channel region <NUM> is spaced from the digit line DL1 by insulative material <NUM>, a segment of the source/region <NUM> is spaced from the digit line DL1 by insulative material <NUM>, another segment of the source/drain region <NUM> is spaced from the digit line by an insulative material <NUM>, and the capacitor C is spaced from the digit line DL1 by an insulative material <NUM>. The insulative materials <NUM>, <NUM>, <NUM> and <NUM> may comprise any suitable composition(s) or combination(s) of compositions; and in some embodiments may comprise one or more of silicon dioxide, silicon nitride, etc. The insulative materials <NUM>, <NUM>, <NUM> and <NUM> may comprise a same composition as one another, or may comprise different compositions relative to one another. For instance, in some embodiments the insulative material <NUM> may comprise silicon dioxide, the insulative material <NUM> may comprise silicon nitride, the insulative material <NUM> may comprise silicon dioxide, and the insulative material <NUM> may comprise silicon nitride.

The transistor T and the capacitor C are each configured as a ring surrounding the digit line DL1. For instance, <FIG> shows a cross-section along the line 2A-2A of <FIG>, and shows the transistor T configured as an example ring surrounding the digit line DL1. Specifically, the gate <NUM> is configured as an outer annular region surrounding an annular region corresponding to the gate dielectric <NUM>, which in turn surrounds an annular region corresponding to the channel material <NUM>, which in turn surrounds an annular region corresponding to the insulative material <NUM>, which in turn surrounds the digit line DL1. The wordline WL1 is coupled with the transistor gate <NUM>, with such coupling being diagrammatically illustrated in <FIG>.

As indicated above, the memory cell A1 may be representative of a large number of substantially identical memory cells utilized in a memory array. <FIG> shows a region of an example memory <NUM> having digit lines extending along a vertical direction represented by an axis <NUM>, and wordlines extending along a horizontal direction represented by an axis <NUM>. The memory cell A1 is shown to be one of a plurality of substantially identical memory cells extending across the memory array, with each of the memory cells being uniquely addressed by one of the digit lines and one of the wordlines (for instance, the memory cell A1 is uniquely addressed with the digit line DL1 and the wordline WL1). Each of the memory cells may have the configuration described above with reference to <FIG>, and accordingly may comprise a transistor (e.g., the transistor T of <FIG>) configured as a ring surrounding a digit line. Each transistor comprises first and second source/drain regions (e.g., the first and second source/regions <NUM> and <NUM> of <FIG>) spaced from one another by GaP channel material (e.g., the channel material <NUM> of <FIG>), with the first and second source/drain regions being vertically displaced relative to one another. Each of the memory cells also comprises a capacitor (e.g., the capacitor C of <FIG>) coupled with one of the source/drain regions of the transistor (e.g., coupled with the second source/drain region <NUM> shown in <FIG>).

The memory array <NUM> of <FIG> may comprise any suitable number of memory cells, and in some embodiments may comprise hundreds, thousands, millions, billions, etc. of substantially identical memory cells. The memory array <NUM> of <FIG> may be the only memory array associated with a semiconductor chip, or may be one of several memory arrays associated with the chip.

The embodiments described above utilize GaP as channel material, it is recognized that it is advantageous to utilize any suitable channel material that comprises GaP and has a bandgap greater than <NUM> electron-volts (eV) at <NUM> kelvin. GaP has a bandgap about <NUM> eV at <NUM> kelvin. The channel materials having bandgaps greater than <NUM> eV may be single compositions, or multiple compositions.

The structures discussed above may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc..

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc..

The terms "dielectric" and "insulative" may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term "dielectric" in some instances, and the term "insulative" (or "electrically insulative") in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being "on" or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on" or "directly against" another structure, there are no intervening structures present.

Structures (e.g., layers, materials, etc.) may be referred to as "extending vertically" to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than <NUM> electron-volts.

Some embodiments include a memory array having a first set of conductive lines extending along a vertical direction, and a second set of conductive lines extending along a horizontal direction. The memory array includes a plurality of memory cells, with each of the memory cells being uniquely addressed by combination of one of the conductive lines from the first set and one of the conductive lines from the second set. Each of the memory cells includes a transistor having GaP channel material.

Claim 1:
A memory array (<NUM>) comprising vertically-stacked memory cells; each of the memory cells comprising a vertical transistor (T) having channel material (<NUM>) comprising GaP and having a bandgap greater than <NUM> electron-volts, eV;
the transistor (T) having first and second source/drain regions (<NUM>, <NUM>) which are vertically displaced relative to one another, and wherein the channel material (<NUM>) extends between the vertically-displaced first and second source/drain regions (<NUM>, <NUM>); and
a capacitor (C) coupled with the transistor (T);
a first set of conductive lines (DL1, DL2, DL3, DL4) extending along a vertical direction, the capacitor (C) being configured as a ring surrounding one of the conductive lines of the first set;
a second set of conductive lines (WL1, WL2, WL3) extending along a horizontal direction; and
each of the memory cells being uniquely addressed by combination of one of the conductive lines from the first set and one of the conductive lines from the second set.