Patent Description:
Optical links are replacing electrical interconnects in data center infrastructure. Optical links support much higher data rates compared to electrical ones. Optical links also consume a fraction of the power of conventional electrical links. The latest push is to transport at least <NUM> Gbps on a single wavelength of light. At such rates, the bandwidth of the popular binary NRZ (non-return-to-zero) signaling scheme is too large to be supported by the electrical-to-optical and optical-to-electrical interfaces. Advanced modulation techniques are useful to reduce the bandwidth. One such technique is pulse-amplitude-modulation with four levels (PAM-<NUM>). Two bits are encoded into one of four levels. As a result, the symbol rate (baud rate) will be half of the bit rate and the bandwidth requirement is reduced compared to NRZ signaling. One aspect of this approach is, however, that the signal processing circuits have to be linear. This is a challenge in low-voltage complementary metal-oxide-semiconductor (CMOS) processes. A fine-linewidth CMOS process offers very high-speed transistors, but the operating voltage is typically <NUM> V or less. In order to preserve clearly discernable and equally spaced four levels, the signal processing circuits should exhibit high-linearity and low-noise.

A transimpedance amplifier (TIA) is an element used in converting optical signals to electrical signals. High-bandwidth linear TIAs are often realized in Indium Phosphide (InP) or Silicon Germanium (SiGe) BiCMOS (Bi-complementary metal-oxide-semiconductor) technologies, where the bipolar transistors offer high speed, low noise, and sustain high voltages. However, the signal processing and logic requirement of a monolithic transceiver integrated circuit (IC) are best realized in CMOS technology. A linear TIA designed in a fine-line CMOS process is likely to face the major technological challenges of signal compression due to limited supply voltage. Moreover, in high speed optical links, the TIA may contribute substantially to overall chip power<NPL> discloses a transimpedance amplifier supplied by a linear regulator.

According to the claimed invention, a system includes a transimpedance amplifier, disposed on a chip, having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and an off-chip switching regulator, off the chip, arranged to power the back-end section. The arrangement provides a low noise power supply for the front-end section, while providing a more power efficient switching regulator to power the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same by a voltage measurement and feedback block.

In another embodiment a method is provided. The method includes receiving power at a front-end section of a transimpedance amplifier, disposed on a chip, from an on-chip linear regulator disposed on the chip; receiving power at a back-end section of the transimpedance amplifier, from an off-chip switching regulator; monitoring an output voltage of the on-chip linear regulator and an output voltage of the off-chip switching regulator; and causing the output voltage of the off-chip switching regulator to be the same as the output voltage of the on-chip linear regulator.

There are several challenges in building a high-speed linear transimpedance amplifier (TIA) in a low-voltage CMOS process. One consideration is the low signal swing imposed by the low supply voltage that can be used. As the signal swing increases, the distortion increases rapidly. Negative feedback cannot be used to improve the linearity because the loop-gain will be very low at the frequencies of interest (~ <NUM>). Added to this conundrum is the wide dynamic range of the input. At low input levels, the signal-to-noise ratio (SNR) is limited by the noise generated by the TIA. Even after achieving a low input-referred noise, the TIA output should be large enough to overcome the quantization noise of the following A/D converter that is in the link. A large swing in a low-voltage technology using conventional techniques would be very non-linear. When the input signal is large, the non-linearity becomes worse. Therefore, a low-noise, wide dynamic range, high gain-bandwidth, linear TIA is quite useful. A TIA that is optimized for power consumption is likewise quite useful.

<FIG> is a block diagram depicting an optical transceiver that includes a transimpedance amplifier that is powered by an on-chip linear regulator and an off-chip switching regulator, according to an example embodiment. An optical transceiver is only one example of the use of a linear TIA according to the embodiments presented herein. The optical transceiver <NUM> includes an optical integrated circuit (IC) <NUM> coupled to one or more optical fibers (lines). The optical lines shown in <FIG> include an output line <NUM>-<NUM> configured to forward optical signals from the optical IC <NUM> and an input line <NUM>-<NUM> configured to forward optical signals to the optical IC <NUM>. The optical IC <NUM> includes an electro-optic modulator <NUM> and a photodiode <NUM>. In one embodiment, the electro-optic modulator <NUM> may be a Mach-Zehnder modulator that outputs, for example, a <NUM> GBd PAM-<NUM> optical signal. The photodiode <NUM> is configured to convert a PAM-<NUM> optical signal to a current signal.

The optical transceiver <NUM> further includes an electrical IC <NUM> coupled to the optical IC <NUM>. On the transmit side, the electrical IC <NUM> includes host serializer/deserializer (SERDES) <NUM> configured to receive NRZ signals from a host <NUM>. An output of the SERDES is supplied to a PAM encoder <NUM>. An output of the PAM encoder <NUM> is supplied to an electro-optic interferometer driver <NUM> configured to drive electro-optic modulator <NUM>. The electro-optic interferometer driver <NUM> may be a Mach-Zehnder Interferometer (MZI) driver in one example. On the receive side, the electrical IC <NUM> includes a TIA <NUM>, a clock and data recovery (CDR) circuit <NUM>, and a PAM decoder <NUM>. The TIA <NUM> is a linear TIA configured to convert the current signals received from the photodiode <NUM> to voltage signals and amplify the voltage signals. In one embodiment, the TIA <NUM>, produced in a CMOS process, may add less than <NUM> % THD (total harmonic distortion) to produce four equally spaced levels in a PAM-<NUM><NUM> Gbps/λ link. As will be explained further below, the TIA <NUM> is powered by two different voltage regulators: an on-chip linear regulator <NUM> and an off-chip switching regulator <NUM>.

In one embodiment, the optical transceiver <NUM> is a transceiver system-in-package (SiP) including the electrical IC <NUM> with a monolithically integrated TIA, flip-chipped on the optical IC <NUM>.

<FIG> is a high-level block diagram of the transimpedance amplifier <NUM> including a demarcation between a front-end section and a back-end section, according to an example embodiment. As shown, the TIA <NUM> includes a transimpedance front-end <NUM>, a single-to-differential converter <NUM>, a programmable gain amplifier (PGA) section <NUM>, and an output buffer section <NUM>. The transimpedance front-end <NUM> of the TIA <NUM> may be a current-to-voltage (I/V) converter. The front-end <NUM> is configured to receive and convert the current output of the photodiode <NUM> (<FIG>) to a voltage signal. Because the photodiode current is inherently single ended, the output of the transimpedance front-end <NUM> is also single ended. Thus, in some embodiments, the single-to-differential converter <NUM> is employed to receive the voltage signal VAM from the transimpedance front-end <NUM> and to generate a complementary signal VAP. The PGA section <NUM> is configured to receive and amplify the complementary voltage signals VAM and VAP. The output buffer section <NUM> is configured to couple to the PGA section <NUM> to receive the amplified voltage signals and provide a desired impendence for outputting voltages signals VOP and VOM to an analog-digital converter (ADC) in the CDR <NUM> (<FIG>).

In some embodiments, the TIA <NUM> may further include a first (DC) feedback circuit <NUM> and a second (DC) feedback circuit <NUM>. The first feedback circuit <NUM> is coupled between a current source <NUM> of the TIA <NUM> and an output of the single-to-differential converter <NUM>. The first feedback circuit <NUM> is configured to subtract the average value of the photodiode current received from the photodiode <NUM>. The second feedback circuit <NUM> is coupled between an output of the output buffer section <NUM> and a first stage of the PGA section <NUM>. The second feedback circuit <NUM> is configured to minimize the random mismatch effects and prevent saturation of the gain stages in the TIA <NUM>.

As further shown in <FIG>, TIA <NUM> may be considered to have a front-end section <NUM> including, e.g., transimpedance front-end <NUM>, single to differential converter <NUM> and the first feedback circuit <NUM>, and a back-end section <NUM> including, e.g., PGA section <NUM>, output buffer section <NUM> and second feedback circuit <NUM>, with the two sections <NUM>, <NUM> separated by dashed demarcation line <NUM>. By powering the front-end section <NUM> and the back-end section <NUM> with different regulator types, it is possible to save considerable power in the back-end section <NUM> while still having the benefits of low supply noise in the front-end section <NUM>. In an embodiment, the front-end section <NUM> is powered by on-chip linear regulator <NUM>, and the back-end section <NUM> is powered by off-chip switching regulator <NUM>. As used herein, "on-chip" means on the same silicon die as, e.g., transimpedance front-end <NUM> and single to differential converter <NUM>, and "off-chip" means not on the same die as, e.g., transimpedance front-end <NUM> and single to differential converter <NUM>, i.e., "off-chip" means a different silicon die.

<FIG> is a schematic diagram of the TIA <NUM> including the demarcation line <NUM> between the front-end section <NUM> and the back-end section <NUM>, according to an example embodiment. The transimpedance front-end <NUM>, in one implementation, includes a shunt-feedback inverter <NUM>. The shunt-feedback inverter <NUM> converts the current output Iin of a photodetector, e.g., photodiode <NUM> in <FIG>, to a voltage. The resistive component in the feedback loop of the transimpedance front-end <NUM> may be a MOS device <NUM> operating in triode region (ohmic mode) to reduce parasitics and achieve a higher bandwidth as compared to a programmable poly-resistor. The MOS device <NUM> can also save valuable real estate area on a chip. The output of the transimpedance front-end <NUM> is a voltage signal VAM, which is single-ended voltage signal. As the analog-to-digital converter (ADC) uses a differential (or balanced) input, the single-ended signal may be converted into a differential or balanced form.

The single-ended voltage signal VAM is fed to the single-to-differential converter <NUM>. The single-to-differential converter <NUM> is a complementary signal generator configured to generate a complementary signal VAP from voltage signal VAM. A single-to-differential converter is perhaps the most challenging block in terms of linearity. Prior art single-to-differential converters typically use a differential pair where the output of the I/V converter is applied to one of the inputs of the differential pair while the other input is connected to an AC ground (a suitable DC voltage). Such a circuit produces a balanced differential output only when the tail current source is ideal (infinite impedance) and when the input is small enough that the differential pair does not fully steer the tail current all to one side or the other. For a realistic range of signals from the I/V converter, the differential output can be highly non-linear. Source degeneration techniques would not work well when the input to the differential pair is single ended. Also, the tail current source is far from ideal. Techniques like simple cascoding or gain-boosted cascoding are effective only at low frequencies. Thus, the current source has a fairly low impedance particularly at high frequencies. This causes the current value to change as a function of the input signal. The effect of having a signal dependent bias current is that the output is non-linear.

To solve these issues, as illustrated in <FIG>, in one form, the single-to-differential converter <NUM> includes a first inverter INV1 coupled in series to a second inverter INV2 that has a short-circuit connection from its output to its input. The first inverter INV1 serves as a driver that drives a load of the short-circuited second inverter INV2 to generate the complementary signal VAP. The first inverter INV1 has an input coupled to the transimpedance front-end <NUM> and an output coupled to an input of the second inverter INV2. The second inverter INV2 has an output coupled to a PGA section <NUM>. The amplitude of the complementary signal VAP is determined by the ratio of the sizes of the driving (INV1) and load (INV2) inverters, and hence can be very tightly controlled. In one embodiment, the sizes of the first inverter INV1 and the second inverter INV2 can be similar or the same. In another embodiment, the size of the load inverter INV2 is smaller than that of the driving inverter INV1 to obtain a gain of unity. The single-to-differential converter <NUM> is configured to generate a <NUM> degree out of phase signal VAP from input signal VAM. Any additional phase shift of the complementary path is very small as the pole frequency is near the transit frequency (fT) of the devices. Because the gain of the single-to-differential converter <NUM> is mostly influenced by a ratio of the transconductances of the driver inverter INV1 and the load inverter INV2, the gain is independent of process and temperature variations. This single-ended to differential arrangement is precise because the amplitude and phase of the signals do not have any resistor dependency, as the single-to-differential converter <NUM> includes no resistor. However, other forms of single-to-differential converter <NUM>, such as a trans-admittance transimpedance (TAS-TIS) circuit that includes resistor components, may be employed.

The PGA section <NUM> includes a first signal path <NUM> and a second signal path <NUM> that receive the complementary voltage signals VAM and VAP, respectively. Each of the first signal path <NUM> and the second signal path <NUM> has a plurality of inverters connected in series without a resistor disposed therebetween. The first signal path <NUM> is coupled directly after the transimpedance front-end <NUM>, while the second signal path <NUM> is coupled directly after the single-to-differential converter <NUM>. For example, each of the first signal path <NUM> and the second signal path <NUM> may include a cascade of <NUM> coarse (e.g., <NUM> or <NUM> dB) programmable gain stages (PGA-C) and a fine gain stage with, e.g., <NUM> dB steps (PGA-F). However, the number of connected PGAs are not so limited and other numbers of PGA-C and PGA-F may be employed.

Still with reference to <FIG>, the first signal path <NUM> and the second signal path <NUM> are cross-coupled to each other through a plurality of inverters <NUM>. These inverters <NUM> between the complementary signal paths <NUM> and <NUM> minimize any amplitude and phase mismatch that is applied at the input of the complementary signal paths <NUM> and <NUM>.

The output buffer section <NUM> is coupled after the PGA section <NUM>. Specifically, the first signal path <NUM> and the second signal path <NUM> are coupled to output buffers <NUM>-<NUM> and <NUM>-<NUM>, respectively. In some embodiments, the output buffer topology can be used as a voltage mode driver, offering a controlled output impedance like <NUM>Ω and having good bandwidth and linearity in serial transceiver blocks (SERDES). The function of the output buffers <NUM>-<NUM> and <NUM>-<NUM> is to provide a large linear output swing and have a well-controlled output impedance.

As illustrated in <FIG>, the entire signal path from the transimpedance front-end <NUM> to the output buffer section <NUM> is composed of DC-coupled inverters operating in the linear region. Using multiples of unit-sized inverters may eliminate systematic offset. In some embodiments, every section starting from the I/V converter to the output buffer section <NUM> is built using a basic CMOS inverter. Each section may use any number of basic CMOS inverter(s) such that, in each section, only the number of the inverters may vary. For example, in the single-to-differential converter <NUM>, the driver INV1 may have <NUM> units of basic inverters connected in parallel and load INV2 may have <NUM> units in parallel.

In some embodiments, the TIA <NUM> further includes a first feedback circuit (DCFB1) <NUM> coupled between a current source <NUM> and the output of the second inverter INV2 of the single-to-differential converter <NUM>. The first feedback circuit <NUM> includes a first resistor <NUM>, a first invertor <NUM>, a first short-circuited inverter <NUM>, a second resistor <NUM>, and a final invertor <NUM> with capacitive feedback, all connected in series. The first feedback circuit <NUM> is configured to subtract the average value of the photodiode current at the input. The TIA <NUM> further includes two second feedback circuits (DCFB2) <NUM>(<NUM>) and <NUM>(<NUM>), one on each of the first signal path <NUM> and the second signal path <NUM>. Each of the second feedback circuits <NUM>(<NUM>) and <NUM>(<NUM>) is coupled between an output of the output buffer <NUM>-<NUM> or <NUM>-<NUM> and a first stage of the PGA section <NUM>, i.e., the first coarse PGA (PGA-C) in the signal path. The components of the second feedback circuits <NUM>(<NUM>) and <NUM>(<NUM>) are similar to those of the first feedback circuit <NUM> and are therefore not described. The second feedback circuits <NUM>(<NUM>) and <NUM>(<NUM>) are configured to minimize the random mismatch effects and prevent saturation of the gain stages. The DC feedback loops also use unit-sized inverters and provide a high-pass corner frequency of less than <NUM> for the signal. Automatic gain control (AGC) provided to the TIA <NUM> is implemented via firmware by monitoring the A/D converter (ADC) output in the clock and data recovery (CDR) block <NUM> (<FIG>).

Those skilled in the art will appreciate that the several components described in <FIG> and indicated as being part of the front-end section <NUM> are powered by on-chip linear regulator <NUM>, and the several components described in <FIG> and indicated as being part of the back-end section <NUM> are powered by off-chip switching regulator <NUM>.

<FIG> is a schematic diagram depicting an implementation of an on-chip linear regulator <NUM> to provide power supply noise rejection and achieve dynamic voltage scaling for the front-end section <NUM> of the transimpedance amplifier <NUM> along with an off-chip switching regulator <NUM> to power the back-end section <NUM> of the transimpedance amplifier <NUM>, according to the claimed invention. As shown, a circuit <NUM> includes the TIA <NUM>, a (programmable) on-chip linear regulator <NUM>, a process and temperature monitor <NUM>, and a frequency comparator <NUM>. The on-chip linear regulator <NUM> is configured to provide suitable power to the front-end section <NUM> of TIA <NUM> and to the process and temperature monitor <NUM>. The on-chip linear regulator <NUM> includes a programmable reference <NUM>, an operational amplifier <NUM>, a replica load <NUM>, two transistors <NUM> and <NUM>, and a capacitor <NUM>, to regulate output voltage VREG to between <NUM> V and <NUM> V. The programmable reference <NUM> outputs a control signal to the operational amplifier <NUM> based on process and temperature data received from the frequency comparator <NUM>. The operational amplifier <NUM> compares the control signal from the programmable reference <NUM> with a signal from the replica load <NUM> and outputs a regulating signal to the transistors <NUM> and <NUM> to regulate the voltage suppled to the front-end section <NUM> of the TIA <NUM>. The capacitor <NUM> is disposed between the regulated output and ground and further improves immunity to the substrate noise.

The regulated voltage adapts to process and temperature variations, thus tightly controlling the bandwidth and peaking of the TIA <NUM>. The on-chip linear regulator <NUM> uses the process and temperature data to regulate the voltage. The process and temperature data is indicative of the process and temperature variations that affects the TIA <NUM>. The process and temperature monitor <NUM> is configured to monitor the process and temperature variations. The process and temperature monitor <NUM> includes a ring oscillator (RO) <NUM> and two transistors MPT and MNT to protect the RO <NUM> from over-voltage.

The range of the regulated voltage is, for example, from <NUM> to <NUM> V across the process, voltage, and temperature (PVT) variations. In this example, the voltage across any two terminals of a transistor may not exceed <NUM> V. The RO <NUM> made of the same unit-sized inverter as those in the TIA <NUM> serves as a PVT variations sensor. The RO <NUM> is used as a process and temperature sensor and has the delay stages built with a number (e.g., <NUM>) of unit inverters. Thus, there is a high degree of correlation between the elements in the TIA <NUM> and the RO <NUM>. Hence the regulated supply voltage can be adjusted precisely to within a few millivolts to obtain optimum gain and bandwidth across all process and temperature ranges. Although voltage swing in the TIA <NUM> is well below rail-to-rail, a ring oscillator swings from rail-to-rail. Thus, the MOS devices in triode region, MPT and MNT, are added to prevent over-voltage. The frequency <NUM> of the RO <NUM>, which is influenced by process and temperature variations, is compared with an external reference clock <NUM> at the frequency comparator <NUM>. A digital output of the frequency comparator <NUM> thus represents the process-corner and temperature of the TIA <NUM>. The on-chip linear regulator <NUM> is programmed via a firmware feedback loop to get a targeted RO frequency. An example control algorithm for regulating voltage output to the TIA <NUM> is shown below:.

The regulated supply voltage VREG is automatically adjusted for different process corners and temperatures to maximize the bandwidth and minimize any in-band peaking for the TIA <NUM>. In one embodiment, all the transistors in the inverter stages are biased in the saturation region and circuit <NUM> adjusts their bias point to compensate for variations in mobility and threshold voltage. Thus, with the circuit <NUM>, the transconductance of all the devices in the TIA <NUM> are tightly controlled across process, voltage and temperature (PVT) variations. Similarly, the output conductance of the triode devices in the feedback path of the front-end section <NUM> (<FIG>) is also tightly bound with similar scheme.

As the TIA performance cannot be fully ascertained at the wafer stage, without the process and temperature tuning, there could be a significant loss of module yield. Discarding assembled modules for any performance shortcoming is very costly. The tuning scheme can also be used to fine tune the quality of the received data eye. According to the techniques disclosed above, the parametric yield of the TIA is expected to be very high as process and temperature variations are automatically compensated to maintain the key performance parameters in a very tight bound.

As noted above, TIA <NUM> can consume a considerable amount of power. For example, a single TIA <NUM>, on a die, driven by a <NUM> V supply, might draw on the order of 40mA, thus consuming 72mW. And, a single die might host eight TIAs, for a total power consumption on the order of 576mW. By supplying power to the front-end section <NUM> of the TIA <NUM> with the on-chip linear regulator <NUM>, and supplying power to the back-end section <NUM> of the TIA <NUM> with a more efficient off-chip switching regulator <NUM>, power savings can be achieved.

Off-chip switching regulator <NUM> may be configured in accordance with any known circuit topology. Switching regulators are inherently more power efficient than linear ones. However, they are more noisy than linear ones. As the back-end section <NUM> of the TIA <NUM> is fully differential any power supply noise will appear as a common-mode signal and does not affect the differential output of the TIA <NUM>.

<FIG> is a high-level block diagram illustrating front-end section <NUM> and back-end section <NUM> of TIA <NUM> being powered by on-chip linear regulator <NUM> and off-chip switching regulator <NUM>, respectively, according to an example embodiment. In an embodiment, TIA <NUM> and on-chip linear regulator <NUM> are disposed on the same chip <NUM> (i.e., die), and chip <NUM> and off-chip switching regulator <NUM> (e.g., a separate IC) might be on a same circuit board <NUM>.

In an example implementation, the front-end section <NUM> draws 15mA from a <NUM>. 8V supply for power consumption of 27mW. The back-end section <NUM> might draw 25mA from off-chip switching regulator <NUM> (regulated at 1V), for a total of 28mW assuming a regulator efficiency of <NUM>%. For eight TIAs on a single die, the total power consumed is 440mW. If the entire TIA were to be powered by the linear regulator, the power dissipation would be (15mA+25mA)*<NUM>*<NUM>=576mW. Thus, the dual regulator scheme would save 176mW or nearly <NUM>% power. In order to ensure the proper performance of the TIA <NUM>, however, the regulators <NUM>, <NUM>, should be properly tuned or synchronized to one another so as to avoid unintended distortion, bias, or even saturation, especially in the context of PAM-<NUM> techniques.

<FIG> is a high-level block diagram depicting a voltage measurement and feedback block <NUM> used to set a voltage of the off-chip switching regulator <NUM>, according to an example embodiment. As shown, <FIG> is similar to <FIG>, but also includes on-chip process and temperature monitor <NUM>, frequency comparator <NUM>, external reference clock <NUM>, and voltage measurement and feedback block <NUM>. As explained previously, the process and temperature monitor <NUM> is configured to monitor the process and temperature variations, and to provide feedback to control the on-chip linear regulator <NUM> output voltage, which is sensed by the process and temperature monitor <NUM>. The voltage measurement and feedback block <NUM> also monitors the output of the on-chip linear regulator <NUM>, and further monitors the output voltage of the off-chip switching regulator <NUM>, and then forces the output of the off-chip switching regulator <NUM> to be the same as the output voltage of the on-chip linear regulator <NUM>. In this way, the outputs of the two supplies are tuned or synchronized together, thus avoiding a supply mismatch between the front-end section <NUM> and the back-end section <NUM>.

<FIG> is a high-level block diagram illustrating the use of respective process and temperature monitors <NUM>(<NUM>) and <NUM>(<NUM>) that are used to provide control feedback for the on-chip linear regulator <NUM> and the off-chip switching regulator <NUM>, respectively, according to an example embodiment. As shown, the first process and temperature monitor <NUM>(<NUM>) is used to monitor the output of the on-chip linear regulator <NUM> and the second process and temperature monitor <NUM>(<NUM>) is used to monitor the output of the off-chip switching regulator. The outputs of the process and temperature monitors <NUM>(<NUM>) and <NUM>(<NUM>) are fed back through a multiplexer or switch <NUM> to frequency comparator <NUM>. The switch <NUM> selects one of the outputs at a time to be compared to the external reference clock <NUM>. An output of the frequency comparator <NUM> is then passed through a demultiplexer or switch <NUM> to provide a control signal to the appropriate supply, i.e., on-chip linear regulator <NUM> or off-chip switching regulator <NUM> to tune, or synchronize, the output voltages of the two regulators <NUM>, <NUM>. Switch <NUM> could be replaced with a firmware loop. The tuning approach depicted in <FIG> may, however, suffer from a mismatch between the first process and temperature monitor <NUM>(<NUM>) and the second process and temperature monitor <NUM>(<NUM>). Such a mismatch may be addressed by the embodiment shown in <FIG>.

<FIG> is high level block diagram illustrating the use of a single process and temperature monitor <NUM> that is used to provide control feedback for the on-chip linear regulator <NUM> and the off-chip switching regulator <NUM>, according to an example embodiment. More specifically, instead of deploying two separate process and temperature monitors, as shown in <FIG>, to separately feed frequency comparator <NUM>, in the embodiment of <FIG> the single process and temperature monitor <NUM> is used to monitor the outputs of each of the on-chip linear regulator <NUM> and the off-chip switching regulator <NUM> individually by selectively turning on switches MPT1 <NUM> or MPT2 <NUM>. In this way the same process and temperature monitor <NUM> is used to monitor the output voltages. The frequency comparator <NUM> is switched through demultiplexer or switch <NUM> to provide the appropriate control feedback to each of the on-chip linear regulator <NUM> and the off-chip switching regulator <NUM>. Switch <NUM> could be replaced with a firmware loop. The output voltages of on-chip linear regulator <NUM> and the off-chip switching regulator <NUM> are accordingly tuned, or synchronized, with each other.

The embodiment of <FIG> provides the low noise benefits of the on-chip linear regulator <NUM>, the power efficiency of the off-chip switching regulator <NUM>, and the accuracy of a common process and temperature monitor <NUM> for both regulators.

<FIG> is a flow chart depicting a series of operations for operating a transimpedance amplifier system, according to an example embodiment. At <NUM>, the system receives power at a front-end section of the transimpedance amplifier, disposed on a chip, from an on-chip linear regulator disposed on the chip. At <NUM>, the system receives power at a back-end section of the transimpedance amplifier, from an off-chip switching regulator. At <NUM>, the system monitors an output voltage of the on-chip linear regulator and an output voltage of the off-chip switching regulator. At <NUM>, the system causes the output voltage of the off-chip switching regulator to be the same as the output voltage of the on-chip linear regulator.

In summary, in one aspect, a system is provided. The system includes a transimpedance amplifier disposed on a chip and having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and an off-chip switching regulator, off the chip, arranged to power the back-end section.

The front-end section may include transimpedance front-end, a single to differential converter and a first feedback circuit.

The back-end section may include a programmable gain amplifier section, an output buffer, and a second feedback circuit.

The system may further include a voltage measurement and feedback block, in communication with the off-chip switching regulator, that is configured to monitor an output voltage of the on-chip linear regulator, monitor an output voltage of the off-chip switching regulator, and cause the output voltage of the off-chip switching regulator to be tuned to the output voltage of the on-chip linear regulator.

The system may further include a process and temperature monitor circuit arranged to monitor an output of the on-chip linear regulator.

The system may include a first process and temperature monitor circuit arranged to monitor an output of the on-chip linear regulator, and a second process and temperature monitor circuit arranged to monitor an output of the off-chip switching regulator.

The system may further include a frequency comparator and a multiplexer in communication with the frequency comparator, wherein an output of the first process and temperature monitor circuit and an output of the second process and temperature monitor circuit are selectively supplied to the frequency comparator via the multiplexer.

In an embodiment, the frequency comparator is in communication with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and an output of the frequency comparator is selectively supplied to the on-chip linear regulator and the off-chip switching regulator via to demultiplexer.

The system may include a process and temperature monitor circuit configured to independently monitor an output of the on-chip linear regulator and the off-chip switching regulator.

In an embodiment, the process and temperature monitor circuit may include a first switch in communication with the output of the on-chip linear regulator, and a second switch in communication with the output of the off-chip switching regulator.

The system may include a frequency comparator, wherein an output of the process and temperature monitor circuit is supplied to the frequency comparator.

In an embodiment, the frequency comparator is in communication with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and an output of the frequency comparator is selectively supplied to the on-chip linear regulator and the off-chip switching regulator via a demultiplexer.

In another embodiment, a device is provided and includes a transimpedance amplifier disposed on a chip and having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and a process and temperature monitor circuit configured to independently monitor an output of the on-chip linear regulator and an off-chip switching regulator that powers the back-end section.

In the device, the process and temperature monitor circuit may include a first switch in communication with the output of the on-chip linear regulator, and a second switch in communication with the output of the off-chip switching regulator.

The device may also include a frequency comparator, and wherein an output of the process and temperature monitor circuit is supplied to the frequency comparator.

In the device the frequency comparator may be in communication with the on-chip linear regulator and the off-chip switching regulator via a demultiplexer, and an output of the frequency comparator is selectively supplied to the on-chip linear regulator and the off-chip switching regulator via the demultiplexer.

In still another embodiment, a method includes receiving power at a front-end section of a transimpedance amplifier, disposed on a chip, from an on-chip linear regulator disposed on the chip; receiving power at a back-end section of the transimpedance amplifier, from an off-chip switching regulator; monitoring an output voltage of the on-chip linear regulator and an output voltage of the off-chip switching regulator; and causing the output voltage of the off-chip switching regulator to be the same as, or identical to, the output voltage of the on-chip linear regulator.

In the method, the front-end section may include a transimpedance front-end, a single to differential converter and a first feedback circuit.

In the method, the back-end section may include a programmable gain amplifier section, an output buffer, and a second feedback circuit.

The method may further include monitoring the output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator using a single process and temperature monitoring circuit.

Claim 1:
A system, comprising:
a transimpedance amplifier disposed on a chip, the transimpedance amplifier having a front-end section and a back-end section;
an on-chip linear regulator, on the chip, arranged to power the front-end section;
an off-chip switching regulator, off the chip, arranged to power the back-end section; and
a voltage measurement and feedback block, in communication with the off-chip switching regulator, that is configured to monitor an output voltage of the on-chip linear regulator, monitor an output voltage of the off-chip switching regulator, and cause the output voltage of the off-chip switching regulator to be tuned to the output voltage of the on-chip linear regulator.