Patent Description:
Metal-ferroelectric-metal (MFM) capacitors and ferroelectric memories include stacked metal, ferroelectric and metal layers. Oxidation at metal/ferroelectric interfaces degrades the reliability of these devices. The degradation of the reliability of these devices can be caused by the creation of oxygen vacancies in the ferroelectric oxide as well as unwanted oxide at the metal/ferroelectric interface. Reactive metals at the metal/ferroelectric interface can enhance this effect. When an excessive number of oxygen vacancies are created in the ferroelectric oxide, breakdown or ferroelectric fatigue can occur which can cause a loss of switchable polarization. Documents <CIT>; <CIT>; <CIT>; <CIT>; <CIT> disclose relevant prior art.

A metal-ferroelectric-metal (MFM) capacitor according to claim <NUM> with multilayer metals and its method of formation according to claim <NUM> is described. It should be appreciated that although embodiments are described herein with reference to example MFM capacitors with multilayer metals implementations, the disclosure is more generally applicable to MFM capacitors with multilayer metals implementations as well as other type MFM capacitors with multilayer metals implementations. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present invention as set forth with the appended claims. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Metal-ferroelectric-metal (MFM) capacitors and ferroelectric memories include stacked metal, ferroelectric and metal layers. Oxidation at metal/ferroelectric interfaces of the MFM capacitors degrades the reliability of these devices. The degradation of the reliability of these devices is caused by the creation of oxygen vacancies in their ferroelectric film as well as unwanted oxide at the metal/ferroelectric interfaces. In particular, reactive metals at metal/ferroelectric interfaces can enhance this effect. It should be appreciated that when an excessive number of oxygen vacancies are created in the ferroelectric film breakdown can occur.

An approach that addresses the shortcomings of previous approaches is disclosed and described herein. For example, as part of a disclosed process, thin non-reactive metal barriers can be used at the metal/ferroelectric interfaces to prevent oxidation at the metal/ferroelectric interfaces. In an embodiment, using thin non-reactive metal barriers at the metal/ferroelectric interfaces suppresses oxygen vacancy creation in the ferroelectric film.

<FIG> shows an MFM capacitor <NUM> with multilayer oxides and metals of a previous approach. In <FIG>, the MFM capacitor <NUM> includes dielectric layer <NUM>, metal via <NUM>, dielectric layer <NUM>, conformal bottom electrode metal <NUM>, ferroelectric layer <NUM>, metal <NUM>, metal fill <NUM>, connector metal <NUM>, and dielectric layer <NUM>.

Referring to <FIG>, a space in the dielectric layer <NUM> is filled with metal to form metal via <NUM>. Dielectric layer <NUM> includes a trench that is lined with conformal bottom electrode metal <NUM>. In particular, the conformal bottom electrode metal <NUM> covers the bottom and sidewalls of the trench. The ferroelectric layer <NUM> covers the portions of the conformal bottom electrode metal <NUM> that cover the bottom and sidewalls of the trench. The ferroelectric metal extends outside of the trench and covers the top surface of the dielectric layer <NUM> on first and second sides of the trench. The dielectric layer <NUM> is formed above the portions of the ferroelectric layer <NUM> that cover the top surface of the dielectric layer <NUM>. As shown in <FIG>, the dielectric layer <NUM> includes a space in which the connector metal <NUM> is formed.

In operation, the capacitor can be charged and discharged as a part of memory operations. The polarity of the charge on the plates of the capacitor is used to set the polarization state or direction of the ferroelectric layer <NUM> (e.g., ferroelectric film). A parameter that is used to characterize a capacitor's performance is endurance. Endurance is a reliability measure. The endurance of a capacitor relates to the maximum number of cycles that the capacitor can tolerate and indicates the capability of the capacitor to continue to work as expected as a function of time. A degradation of the reliability of the MFM capacitor <NUM> is caused by the movement of oxygen vacancies in the ferroelectric layer <NUM> and by the formation of unwanted oxide at metal/ferroelectric interfaces (e.g., interfaces between metal layer <NUM> and ferroelectric layer <NUM> and ferroelectric layer <NUM> and metal layer <NUM>). Reactive metals such as (but not limited to) TiN and TaN at these interfaces create oxygen vacancies in the ferroelectric layer <NUM>. Excessive oxygen vacancies impact endurance by degrading the ferroelectric layer <NUM> and enhancing fatigue. As such, the creation of oxygen vacancies in the ferroelectric layer <NUM> negatively impacts the maximum number of cycles that the MFM capacitor <NUM> can tolerate. Thus, the reliability of the MFM capacitor <NUM> of the approach illustrated in <FIG> can suffer.

<FIG> illustrates an MFM capacitor <NUM> with multilayer oxides and metals according to an embodiment. In <FIG>, the MFM capacitor <NUM> includes dielectric layer <NUM>, metal via <NUM>, dielectric layer <NUM>, metal <NUM>, non-reactive barrier metal <NUM> (in expanded view at left), ferroelectric layer <NUM>, non-reactive barrier metal <NUM> (in expanded view at left), metal <NUM>, metal fill <NUM>, dielectric layer <NUM> and connector metal <NUM>.

Referring to <FIG>, dielectric layer <NUM> includes a via that is filled to form metal via <NUM>. Dielectric layer <NUM> includes a trench that is lined with metal <NUM>. For example, the metal <NUM> covers the bottom and sidewalls of the trench. The non-reactive barrier metal <NUM> covers the bottom and the sidewalls of the metal <NUM>. The ferroelectric layer <NUM> covers the portions of the non-reactive barrier metal <NUM> that covers the bottom and sidewalls of the trench. The ferroelectric layer <NUM> extends outside the trench and covers the top surfaces of portions of the dielectric layer <NUM> on the right side and the left side of the trench. The non-reactive barrier metal <NUM> covers the bottom and sidewalls of the ferroelectric layer <NUM>. The metal <NUM> covers the bottom and sidewalls of the non-reactive barrier metal <NUM>. The dielectric layer <NUM> is formed above portions of the ferroelectric layer <NUM> that cover the top surfaces of the dielectric layer <NUM>. The dielectric layer <NUM> includes a space in which connector metal <NUM> is formed.

In an embodiment, the dielectric layer <NUM> can be formed from oxide, nitride, carbon doped oxide or carbon doped nitride. In other embodiments, the dielectric layer <NUM> can be formed from any other type of dielectric material. In an embodiment, the metal via <NUM> can be formed from tungsten, cobalt, copper or copper with a TaN liner. In other embodiments, the metal via <NUM> can be formed from other materials. In an embodiment, the dielectric layer <NUM> can be formed from oxide. In other embodiments, the dielectric layer <NUM> can be formed from other types of dielectric material. In an embodiment, the metal <NUM> and the metal <NUM> can be formed from ALD or CVD metals, titanium nitride, tantalum nitride, ruthenium, ruthenium oxide, iridium oxide or titanium silicon oxide. In other embodiments, the metal <NUM> and the metal <NUM> can be formed from other materials. In an embodiment, the non-reactive barrier metal <NUM> and the non-reactive barrier metal <NUM> can be formed from tantalum nitride, ruthenium, ruthenium oxide, iridium or iridium oxide. In other embodiments, the non-reactive barrier metal <NUM> and the non-reactive barrier metal <NUM> can be formed from other types of oxygen diffusion barrier metals. In an embodiment, the ferroelectric material <NUM> can be formed from hafnium zirconium oxide, hafnium oxide, zirconium oxide, aluminum doped hafnium oxide, silicon doped hafnium oxide, yttrium doped hafnium oxide, lanthanum doped hafnium oxide, lanthanum doped zirconium oxide, or lead zirconate titanate (PZT). In other embodiments, the ferroelectric material <NUM> can be formed from other types of materials. In an embodiment, the metal fill <NUM> can be formed from tungsten, cobalt or copper. In other embodiments, the metal fill <NUM> can be formed from other materials. In an embodiment, the dielectric layer <NUM> can be formed from oxide. In other embodiments, the dielectric layer <NUM> can be formed from other types of dielectric materials. In an embodiment, the connector metal <NUM> can be formed from tungsten, cobalt or copper. In other embodiments, the connector metal <NUM> can be formed from other materials.

In operation, the memory state of the MFM capacitor <NUM> is defined by the polarization charge stored in the capacitor. Having excessive trap states in the ferroelectric can increase charge trapping during ferroelectric switching. Utilizing the non-reactive barrier metal <NUM> and the non-reactive barrier metal <NUM> prevents the creation of oxygen vacancy traps in the ferroelectric layer <NUM>. In an embodiment, because the non-reactive barrier metal <NUM> and the non-reactive barrier metal <NUM> prevents the creation of oxygen vacancies in the ferroelectric layer <NUM> they prevent the breakdown of the ferroelectric layer <NUM> and the degradation of the reliability of the MFM capacitor <NUM>.

<FIG> shows cross-sections of a MFM capacitor that includes multilayer metals during the fabrication of the MFM capacitor according to an embodiment. Referring to <FIG>, after a plurality of operations a structure is formed that includes dielectric layer <NUM>, metal via <NUM> and a dielectric layer <NUM>.

Referring to <FIG>, subsequent to one or more operations that result in a cross-section of the structure shown in <FIG>, a space is formed in the dielectric layer <NUM>. In an embodiment, the space can be formed by removal of dielectric material from the dielectric layer <NUM>. In an embodiment, the removal of dielectric material can be performed by etching. In an embodiment, the etching can be performed by dry etch or wet etching. In other embodiments, other manner of removing the dielectric material can be used.

Referring to <FIG>, subsequent to one or more operations that result in the cross-section shown in <FIG>, a metal layer <NUM> is formed on the trench bottom and sidewalls and above the top surface of dielectric layer <NUM>. In addition, a non-reactive barrier metal <NUM> is formed on the bottom and sidewalls of the metal layer <NUM>. In an embodiment, the metal layer <NUM> can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), or molecular beam epitaxy (MBE). In other embodiments, the metal layer <NUM> can be formed in other manners. In an embodiment, the non-reactive barrier metal layer <NUM> can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), or molecular beam epitaxy (MBE). In other embodiments, the non-reactive barrier metal layer <NUM> can be formed in other manners.

Referring to <FIG>, subsequent to one or more operations that result in a cross-section shown in <FIG>, the portion of the metal layer <NUM> that is formed above the top surface of the dielectric layer <NUM> is removed. In an embodiment, the portion of metal layer <NUM> that is formed above the top surface of the dielectric layer <NUM> can be removed by etching. In other embodiments, the portion of the metal layer <NUM> that is formed above the top surface of the dielectric layer <NUM> can be removed in other manners.

Referring to <FIG>, subsequent to one or more operations that result in a cross-section shown in <FIG>, a ferroelectric layer <NUM> is formed on the non-reactive barrier metal <NUM>, a non-reactive barrier metal <NUM> is formed on the ferroelectric layer <NUM> and a metal layer <NUM> is formed on the non-reactive barrier metal <NUM>. In an embodiment, the ferroelectric layer <NUM> can be formed by atomic layer deposition (ALD) or sputtering. In other embodiments, the ferroelectric layer <NUM> can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), or molecular beam epitaxy (MBE). In still other embodiments, the ferroelectric layer <NUM> can be formed in other manners. In an embodiment, the non-reactive barrier metal layer <NUM> can be formed by atomic layer deposition (ALD). In other embodiments, the non-reactive barrier metal layer <NUM> can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), or molecular beam epitaxy (MBE). In still other embodiments, the non-reactive barrier metal layer <NUM> can be formed in other manners.

Referring to <FIG>, subsequent to one or more operations that result in the cross-section shown in <FIG>, a metal fill <NUM> is formed in a space defined by the metal layer <NUM>. In an embodiment, the metal fill <NUM> can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), or molecular beam epitaxy (MBE)). In other embodiments, the metal fill <NUM> can be formed in other manners.

Referring to <FIG>, subsequent to one or more operations that result in the cross-section shown in <FIG>, a dielectric layer <NUM> is formed above the top surface of the MFM structure. In an embodiment, the dielectric layer <NUM> can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) or atomic layer deposition (ALD). In other embodiments, the dielectric layer <NUM> can be formed in other manners.

Referring to <FIG>, after one or more operations that result in the cross-section shown in <FIG>, an opening is formed in the dielectric layer <NUM> and a connector metal <NUM> is formed in the opening. In an embodiment, the connector metal <NUM> can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), or molecular beam epitaxy (MBE). In other embodiments, the connector metal <NUM> can be formed in other manners.

<FIG> is a flowchart of a method for forming an MFM capacitor with multilayer metals of an embodiment. Referring to <FIG>, the method includes, at <NUM> forming a first metal layer. At <NUM>, forming a first non-reactive barrier metal layer on the first metal layer. At <NUM>, forming a ferroelectric layer on the first non-reactive barrier metal layer. At <NUM>, forming a second non-reactive barrier metal layer on the ferroelectric layer. At <NUM>, forming a second metal layer on the second non-reactive barrier metal layer.

Implementations of embodiments of the invention may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the scope of the present invention and the appended claims.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the invention may also be carried out using nonplanar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO<NUM>) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about <NUM> eV and about <NUM> eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And, in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO<NUM>), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

<FIG> illustrates a computing device <NUM> in accordance with one implementation of the invention. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). In an embodiment, memory and or logic systems of computing device <NUM> (such as but not limited to DRAM and/or DRAM that is embedded in logic) can include capacitors such as capacitor <NUM> described herein with reference to <FIG>.

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

<FIG> illustrates an interposer <NUM> that includes one or more embodiments of the invention. The interposer <NUM> is an intervening substrate used to bridge a first substrate <NUM> to a second substrate <NUM>. The first substrate <NUM> may be, for instance, an integrated circuit die. The second substrate <NUM> may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer <NUM> is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer <NUM> may couple an integrated circuit die to a ball grid array (BGA) <NUM> that can subsequently be coupled to the second substrate <NUM>. In some embodiments, the first and second substrates <NUM>/<NUM> are attached to opposing sides of the interposer <NUM>. In other embodiments, the first and second substrates <NUM>/<NUM> are attached to the same side of the interposer <NUM>. And in further embodiments, three or more substrates are interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer <NUM> may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer <NUM> may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radiofrequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer <NUM>. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer <NUM>.

Claim 1:
A capacitor, comprising:
a first metal layer;
a second metal layer (<NUM>) on the first metal layer (<NUM>), the second metal layer (<NUM>) including a first non-reactive barrier metal layer (<NUM>) formed at an interface between the first metal layer (<NUM>) and a ferroelectric layer (<NUM>), wherein the first non-reactive barrier metal layer (<NUM>) comprises a ruthenium layer, an iridium layer or an iridium oxide layer;
the ferroelectric layer (<NUM>) on the second metal layer (<NUM>);
a third metal layer (<NUM>) on the ferroelectric layer (<NUM>), the third metal layer (<NUM>) including a second non-reactive barrier metal layer (<NUM>) formed at an interface between the ferroelectric layer (<NUM>) and a fourth metal layer (<NUM>), wherein the second non-reactive barrier metal layer (<NUM>) comprises a ruthenium layer, an iridium layer or an iridium oxide layer; and
the fourth metal layer (<NUM>) on the third metal layer (<NUM>).