Patent Description:
As is known in the art, as the frequency of FET (Field Effect Transistor) operation goes above <NUM> toward THz range, both gate and channel lengths of FETs are reduced to sub-<NUM> range towards <NUM> according to recent publications. At these small geometries, parasitic resistance, inductance, and capacitance of the FETs significantly affect the RF performance of the FET device, such as power, gain and efficiency. Most of attempts to increase the operating frequency of FET have focused on using smaller gate length and width, and narrow channel.

More particularly, a FET according to the PRIOR ART is shown in <FIG>. Here, a semi-insulating, highly resistive, substrate, such as SiC, has formed on the upper surface thereof a mesa shaped semiconductor structure, here for example a Group III-V structure, here, for example, a GaN structure. More particularly, III-V based structures such as GaN-based transistors use electrons formed between two different bandgap materials, for example, AlGaN and GaN. Formed in ohmic contact with source and drain regions of the upper surface of the mesa are source and drain electrodes, as shown. Disposed between the source and drain electrodes is a gate electrode in Schottky contact with an upper surface of the mesa (a gate region) disposed between the source and drain regions. The gate electrode is used to control a flow of carriers (holes and electrons) in an active region of the mesa though the active region (sometimes herein referred to as the gate channel region) between the source and drain regions. It is noted that the regions outside of the mesa area, called 'off mesa area'. The off mesa area, as noted above, is semi-insulating highly resistive area. The Effective gate width (the active region) is the length of the gate electrode is the region closest to the source and drain regions (the gate channel region) and it is this gate channel region that contributes to the conduction of transistor. As the gate channel width (the distance between the source and drain) gets narrower to reduce the electron transfer time for high frequency operation, the contribution of the carriers in the gate channel region gets stronger. From the prior art it is noted that the total gate length extends beyond the gate channel length even though the most of carrier conduction occurs along the gate channel length; however, the portions of the gate electrode extending beyond the gate channel region generate parasitic gate resistance, inductance, and capacitance and thereby contribute negatively for high frequency operation.

Next, it is noted that the source electrode is disposed within opposing sidewalls of the mesa structure, the drain electrode is disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa, and the gate electrode is disposed within opposing walls of the gate region of the mesa and that the mesa is rectangular shape. Further, it is noted that the source electrode has an inner edge extending between ends SOURCE EDGE <NUM>, SOURCE EDGE <NUM> (<FIG> thereof proximate the gate electrode that extends along a direction parallel to the gate electrode; and, likewise the drain electrode has an inner edge extending between ends DRAIN EDGE <NUM>, DRAIN EDGE <NUM> (<FIG> thereof proximate the gate electrode that extends along a direction parallel to the gate electrode. The lengths of the inner edges of the source and drain electrodes are equal. The gate electrode extends beyond the ends of SOURCE EDGE <NUM>, SOURCE EDGE <NUM> of the inner edge of the source electrode and thus also beyond the ends of DRAIN EDGE <NUM>, DRAIN EDGE <NUM> of the inner edge of the drain electrode. The active region (gate channel) extends between ends DRAIN EDGE <NUM> (or SOURCE EDGE <NUM>) and DRAIN EDGE <NUM> (or SOURCE EDGE <NUM>) (<FIG>. As noted above, the total gate electrode length extends beyond the active region (gate channel length), even though the most of carrier conduction occurs along the gate channel length, generates unwanted parasitic gate resistance, inductance, and capacitance and thereby contributes negatively for high frequency operation of the FET.

<CIT> describes a field effect transistor and manufacturing method thereof.

<CIT>, relates to a Field Effect Transistor (FET) structure featuring a gate with a notch.

In accordance with the present disclosure, a Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa structure; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure.

In one embodiment, the mesa structure includes a pair of notches project inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.

With such an arrangement, the gate parasitics of the prior art are reduced by the formation of the notches in the mesa structure because extra gate length on top of the active region of the mesa structure is eliminated and the gate tab (or pad) disposed on the substrate off of the mesa structure is able to be positioned closer to active inner portion of the gate. With a multi-fingered gate structure, as the number of gate fingers increases, the parasitic components are multiplied and therefore the disclosed FET structure significantly improves the performance of FETs with multiple gate fingers at high operating frequency.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below.

Referring now to <FIG>, a Field Effect Transistor structure <NUM> is shown having: a semi-insulating substrate <NUM>, here for example, a semi-insulating, highly resistive, substrate, such as SiC, GaAs, and InP; a semiconductor mesa structure <NUM>, here for example, a Group III-V structure such as a GaN structure, disposed on the upper surface <NUM> of the substrate <NUM> and having a pair of notches <NUM> in opposing outer sidewalls <NUM> of the mesa structure <NUM>; a source electrode <NUM> disposed within the opposing sidewalls <NUM> in ohmic contact with a source region <NUM> (<FIG>) of the mesa structure <NUM> under the source electrode <NUM>; a drain electrode <NUM> disposed within the opposing sidewalls <NUM> in ohmic contact with a drain region (not shown) under the drain electrode <NUM> of the mesa structure <NUM>; and a gate electrode <NUM>, having an inner portion 28a disposed between, and laterally of, the source electrode <NUM> and the drain electrode <NUM> and in Schottky contact with the portion of the mesa structure <NUM> under the inner portion of the gate electrode 28a, extending longitudinally between the pair of notches <NUM> and having outer portions 28b extending beyond the mesa structure <NUM> and over portions of the upper surface <NUM> of substrate <NUM> outside of the mesa structure <NUM> ("off-mesa"). Thus, here the mesa structure <NUM> includes a pair of notches <NUM> which project inwardly towards each other and the inner portion 28a of the gate <NUM> extends longitudinally between the pair of notches <NUM>. It is noted that here the notches <NUM> are v-shaped notches. It should be understood, however, that the notches <NUM> may be of a different shapes and includes, for example, any shaped indentation or groove in the sidewalls <NUM> of the mesa structure <NUM>, including, for example, a rounded indentation, a square or rectangular indentation.

Further, it is noted that the source electrode <NUM> has an inner edge <NUM> extending between ends SE <NUM> and SE2 (<FIG>) thereof proximate the inner portion 28a of gate electrode <NUM>; and, likewise the drain electrode <NUM> has an inner edge <NUM> extending between ends DE1, DE2 (<FIG>) thereof proximate the inner portion 28a of gate electrode <NUM>. Here, the lengths of the inner edges <NUM>, <NUM> of the source and drain electrodes <NUM>, <NUM> are equal. The gate electrode <NUM> extends beyond the ends SE1, SE2 of the inner edge <NUM> of the source electrode <NUM> and thus also beyond the ends DE1, DE2 of the inner edge <NUM> of the drain electrode <NUM>. The active region (gate channel) <NUM> in under the inner portion 28a of the gate electrode <NUM> and extends between ends DE1 (or SE1) and DE2 (or SE2) (<FIG>).

It is noted that the inner portion 28a of the gate electrode <NUM> is elongated and the source electrode <NUM> and the drain electrode <NUM> are here also elongated along directions parallel to the direction of the elongated inner portion 28a of the gate electrode <NUM>. It is also noted that the source electrode <NUM> is within opposing outer portions of the sidewalls <NUM> of the mesa structure <NUM> separated a length Lms measured along the top surface of the mesa; the drain electrode is within opposing portions of the sidewalls <NUM> separated a length Lmd measured along the top surface of the mesa; and the inner portion 28a of the gate electrode <NUM> is within the pair of notches <NUM>, the notches being separated a length Lmg measured along the top surface of the mesa; where Lmg is less than either one of the lengths Lmd or Lms; it here being noted that length Lmd equals length Lms. It is noted that all three lengths are measured along directions parallel to the direction of the elongated inner portion 28a of the gate electrode <NUM>. One end of the inner portion 28a of the gate electrode <NUM> terminates in a gate pad 28p and a portion 28p'of the gate pad 28p is disposed within a portion of one of the pair of notches <NUM>, here the notch <NUM> on the right hand side of mesa structure <NUM> in <FIG>. The gate pad 28p is wider than the inner region 28a of the gate electrode <NUM>.

Referring now to <FIG>, a comparison is shown between the plan view of a mesa structure with a pair of opposing notches (the upper portion of <FIG>) and a mesa structure without a pair of opposing notches (the lower portion of <FIG>). It is noted that the length of the gate electrode between the end of the active gate region and the gate pad on the right hand side of <FIG> with the notch is less than the length of the gate electrode between the end of the active gate region and the gate pad without the notch by a difference in length DIFF1. Similarly, it is noted that the length of the gate electrode between the end of the active gate region and the left hand end of the gate electrode with the notch is less than the length of the gate electrode between the end of the active gate region and the left hand end of the gate electrode without the notch by a difference in length DIFF2. Thus, the gate parasitics are reduced by the formation of the notches in the mesa structure because extra gate length on top of the active region of the mesa structure is eliminated and the gate tab (or pad) disposed on the substrate off of the mesa structure is able to be positioned closer to active inner portion of the gate.

Referring now to <FIG>, a multi-fingered gate structure, here having two gate fingers, it being understood that more than two gate fingers may be used, of the FET of <FIG> is shown. Here, the source electrode is connected to a ground plane on the bottom surface of the substrate with a conductive via passing vertically through the mesa structure and the underlying portion of the substrate. It is noted that as the number of gate fingers increases, the parasitic components are multiplied and therefore the disclosed FET structure significantly improves the performance of FETs with multiple gate fingers.

It should now be appreciated a field effect transistor structure according to the disclosure includes: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa structure; a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. The field effect transistor structure may include one or more of the following features, independently or in combination with another feature including: wherein the mesa structure includes a pair of notches project inwardly towards each other and wherein the inner portion of the gate extends longitudinally between the pair of notches; wherein the source electrode is within opposing outer edges separated a length Lms measured along a top surface of the mesa, the drain electrode is within opposing outer edges separated a length Lmd measured along a top surface of the mesa, and the inner portion of the gate is within the notch and an opposing edge having a separation a length Lmg measured along a top surface of the mesa, where Lmg is less than either of Lmd or Lms; wherein the source electrode is within opposing outer edges separated a length Lms, the drain electrode is within opposing outer edges separated a length Lmd, and the inner portion of the gate is within the pair of notches having a separation a length Lmg, where Lmg is less than either of Lmd or Lms; wherein the outer portion of the gate electrode terminates in a gate pad and wherein a portion of the gate pad is disposed within a portion of the notch; wherein the gate pad is wider than the inner region of the gate electrode; wherein the outer portion of the gate electrode terminates in a gate pad and wherein a portion of the gate pad is disposed within a portion of the notch; or wherein the mesa structure is a Group III-V structure.

Claim 1:
A Field Effect Transistor structure, comprising:
a semi-insulating substrate (<NUM>);
a semiconductor mesa structure (<NUM>) disposed on the substrate and having a notch (<NUM>) in an outer sidewall of the mesa structure;
a source electrode (<NUM>) disposed within opposing sidewalls of the mesa structure in ohmic contact with a source region of the mesa structure;
a drain electrode (<NUM>) disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa structure;
a gate electrode (<NUM>), having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure,
characterised in that one of the outer portions of the gate electrode (<NUM>) terminates in a gate pad and wherein a portion of the gate pad is disposed within a portion of the notch (<NUM>), and wherein the gate pad is wider than the inner portion of the gate electrode (<NUM>)