Patent Description:
The present disclosure relates generally to display technologies, and more specifically to a thin-film transistor and its manufacturing method, an array substrate, and a display apparatus.

Thin-film transistors are employed to produce high-end display apparatuses with high-quality display effects. Each pixel on a display panel in a display apparatus is driven to emit light by a thin-film transistor integrated in the display panel.

At present, the manufacturing method of a thin-film transistor typically comprises the following steps:.

The conventional manufacturing method of a thin-film transistor as described above includes at least the following issues:
At present, due to the difficulty to control the etching process, issues such as over-etching and under-etching with regard to the contact vias often arise during etching of the insulating layer to form contact vias. Both the issue of over-etching and the issue of under-etching can have adverse effects to the thin-film transistors that are manufactured this way, which can ultimately lead to reduced yield of the thin-film transistors.

To more clearly illustrate some of the embodiments of the present disclosure as described above, the following is a brief description of the drawings. The drawings in the following descriptions are only illustrative of some embodiments. For those of ordinary skill in the art, other drawings of other embodiments can become apparent based on these drawings.

In the following, with reference to the drawings of various embodiments disclosed herein, the technical solutions of the embodiments of the present disclosure will be described in a clear and fully understandable way.

It is obvious that the described embodiments represent merely a portion, but not all, of the embodiments of the present disclosure.

In order to address the issues associated with current technology in fabricating thin-film transistors, the present disclosure provides a method for manufacturing a thin-film transistor and a thin-film transistor manufactured thereby.

The method comprises: forming a first layer; forming at least one etch stopper over the first layer; forming a second layer over the first layer and the at least one etch stopper; forming at least one contact via in the second layer, such that a bottom opening of each contact via contacts with a top surface of one etch stopper; and forming at least one electrode in the at least one contact via, such that each electrode extends in one contact via respectively, and is in contact with, and electrically coupled with, the one etch stopper. The at least one etch stopper comprises a composition. The composition is capable of blocking etching to the first layer during formation of the at least one contact via in the second layer; and the composition also has one of the following characteristics: an oxidization product of the composition is readily removable by a solution; an oxidization product is conductive; or the composition is resistant to oxidization.

By applying the method as described above, a thin-film transistor can be manufactured. The thin-film transistor comprises a first layer; at least one etch stopper, disposed over the first layer; a second layer, disposed over the first layer and the at least one etch stopper; at least one contact via, disposed in the second layer and configured such that a bottom opening of each contact via is in contact with a top surface of one etch stopper; and at least one electrode, disposed in the at least one contact via and configured such that each electrode extends in one contact via respectively, and is in contact with, and electrically coupled with, the one etch stopper.

In the thin-film transistor, the at least one etch stopper comprises a composition. The composition is capable of blocking etching to the first layer during formation of the at least one contact via in the second layer; and the composition also has one of the following characteristics: an oxidization product of the composition is readily removable by a solution; an oxidization product is conductive; or the composition is resistant to oxidization.

Details of some embodiments of the method and the thin-film transistor are provided below.

In one aspect, the present disclosure provides a thin-film transistor. The thin-film transistor, according to some embodiments of the present disclosure as illustrated in <FIG>, comprises a first etch stopper <NUM>, a second etch stopper <NUM>, a source electrode <NUM>, a drain electrode <NUM>, an insulating layer <NUM>, and an active layer <NUM>.

The first etch stopper <NUM> and the second etch stopper <NUM> are disposed over the active layer <NUM>. The insulating layer <NUM> is disposed over, and cover, the active layer <NUM>, the first etch stopper <NUM>, and the second etch stopper <NUM>. The insulating layer <NUM> is provided with a first contact via <NUM> and a second contact via <NUM>.

The source electrode <NUM> is electrically coupled with the active layer <NUM> through the first contact via <NUM>, and the drain electrode <NUM> is electrically coupled with the active layer <NUM> through the second contact via <NUM>.

The first etch stopper <NUM> is disposed between the active layer <NUM> and the source electrode <NUM>, and the second etch stopper <NUM> is disposed between the active layer <NUM> and the drain electrode <NUM>.

In the thin-film transistor according to the embodiments of the present disclosure as described above, when forming the first contact via <NUM> and the second contact via <NUM>, the insulating layer <NUM> can be directly etched onto the first etch stopper <NUM> and the second etch stopper <NUM>. The issue of under-etching can thereby be effectively solved.

On the other hand, the presence of the first etch stopper <NUM> and the second etch stopper <NUM> substantially blocks the etching to the active layer <NUM>, thereby effectively solving the issue of over-etching. As such, the production yield of thin-film transistors can thus be improved.

The thin-film transistor according to the embodiments of the present disclosure as described above can optionally have the following features.

The thin-film transistor according to the embodiments can be a thin-film transistor of any structure. For example, the thin-film transistor can be a bottom-gate thin-film transistor, or can be a top-gate thin-film transistor.

Optionally, the insulating layer <NUM> can be of a single-layer structure, or can be of a double-layer structure.

<FIG> and <FIG> illustrate a thin-film transistor with an insulating layer <NUM> having a single-layer structure, wherein the insulating layer <NUM> comprises an interlayer insulating layer <NUM>. The thin-film transistor as such further includes a gate electrode <NUM> and a gate insulating layer <NUM>.

The gate electrode <NUM> is disposed over a glass substrate <NUM>. The gate insulating layer <NUM> is disposed over the glass substrate <NUM> and the gate electrode <NUM>. The active layer <NUM>, the first etch stopper <NUM> and the second etch stopper <NUM> are disposed between the gate insulating layer <NUM> and the interlayer insulating layer <NUM>. The first etch stopper <NUM> and the second etch stopper <NUM> are disposed to be closer to the interlayer insulating layer <NUM>.

When the insulating layer <NUM> is etched to form contact vias, the interlayer insulating layer <NUM> needs to be thoroughly etched to thereby expose the first etch stopper <NUM> and the second etch stopper <NUM> to complete the etching process to form the contact vias.

<FIG> and <FIG> illustrate a thin-film transistor with an insulating layer <NUM> having a double-layer structure, wherein the insulating layer <NUM> comprises an interlayer insulating layer <NUM> and a gate insulating layer <NUM>. A thin-film transistor as such further includes a gate electrode <NUM>.

In order to prevent the active layer <NUM> from being affected by the impurity particles in the glass substrate <NUM>, a buffer layer <NUM> can be disposed over the glass substrate <NUM> prior to forming an active layer <NUM>, and after that, the active layer <NUM> can be disposed over the buffer layer <NUM>. The gate insulating layer <NUM> is disposed over the active layer <NUM>, the first etch stopper <NUM>, the second etch stopper <NUM>, and the buffer layer <NUM>. The interlayer insulating layer <NUM> is disposed over the gate insulating layer <NUM>, and the gate electrode <NUM> is sandwiched between the interlayer insulating layer <NUM> and the gate insulating layer <NUM>.

When the insulating layer <NUM> is etched to form contact vias, the interlayer insulating layer <NUM> and the gate insulating layer <NUM> need to be etched thoroughly to thereby expose the first etch stopper <NUM> and the second etch stopper <NUM> to complete the etching process to form the contact vias.

Optionally, the buffer layer <NUM> can have a composition of silicon oxide and/or silicon nitride; the active layer <NUM> can have a composition of polycrystalline silicon; the gate insulating layer can have a composition of silicon oxide, and the interlayer insulating layer <NUM> can have a composition of silicon oxide or silicon nitride.

Specifically, if the gate insulating layer <NUM> has a composition of silicon oxide, the thickness of the gate insulating layer <NUM> can be around <NUM>Å- <NUM>Å. If the gate electrode <NUM> has a composition of molybdenum, the thickness of the gate electrode <NUM> can be around <NUM>Å.

If the interlayer insulating layer <NUM> has a composition of silicon oxide, the thickness of the interlayer insulating layer <NUM> can be around <NUM>Å. If the interlayer insulating layer <NUM> has a composition of silicon nitride, the thickness of the interlayer insulating layer <NUM> can be around <NUM>Å.

<FIG> and <FIG> illustrate a thin-film transistor employed in an Organic Light-Emitting Diode (OLED) display panel. In addition to the thin-film transistor, the OLED display panel further comprises a planarizing layer <NUM>, an anode layer <NUM>, and a pixel defining layer <NUM>.

The planarizing layer <NUM> can be disposed over the insulating layer <NUM>, the source electrode <NUM>, and the drain electrode <NUM>. The anode layer <NUM> is disposed over the planarizing layer <NUM> and the source electrode <NUM>. The pixel defining layer <NUM> is disposed over the planarizing layer <NUM> and between the anode layers <NUM> of neighboring pixels.

Optionally, the planarizing layer <NUM> can have a composition of acrylic, and can have a thickness of around <NUM>Å; the anode layer <NUM> can have a composition of an indium zinc oxide or an indium tin oxide, and can have a thickness of around <NUM>Å. The pixel defining layer <NUM> can have a composition of polyimide, and can have a thickness of around <NUM>Å.

Optionally, the source electrode <NUM> can be of an N-layer structure, where N is an integer greater than <NUM>. A first layer of the source electrode <NUM> can be configured to contact with, and electrically couple with, the first etch stopper <NUM>. The first etch stopper <NUM> can have a same composition as the first layer in the source electrode <NUM>.

The second etch stopper <NUM> can have a same composition as the first etch stopper <NUM>. The drain electrode <NUM> and the source electrode <NUM> can have a same composition and a same structure.

The first etch stopper <NUM> and the first layer in the source electrode <NUM> can have a same composition. The second etch stopper <NUM> and the first layer in the drain electrode <NUM> can have a same composition. Such a configuration ensures that the presence of the first etch stopper <NUM> and the second etch stopper <NUM> would not reduce the electrical conductivity between the active layer <NUM> and the source electrode <NUM> and the drain electrode <NUM>.

Optionally, N can be <NUM>, <NUM> or <NUM>. If the number of layers of the source electrode <NUM> is <NUM> or <NUM>, neighboring layers have different compositions.

Optionally, the source electrode <NUM> and the drain electrode <NUM> can have a composition of a metal.

Optionally, the source electrode <NUM> and the drain electrode <NUM> can comprise at least one of molybdenum, titanium, and aluminum.

Optionally, the first etch stopper <NUM> can have a composition of a metal, and the second etch stopper <NUM> can have a same composition as the first etch stopper <NUM>.

In one preferred embodiment, the first etch stopper <NUM> can comprise molybdenum, and the second etch stopper <NUM> can have a same composition as the first etch stopper <NUM>. If the first etch stopper <NUM> and the second etch stopper <NUM> both have a composition of a conductive metal, after completing the etching process to form contact vias, the portions of the first etch stopper <NUM> and the second etch stopper <NUM> that are exposed can be oxidized.

If the first etch stopper <NUM> and the second etch stopper <NUM> comprise molybdenum, after oxidization of the metal molybdenum, because the oxidized molybdenum (i.e. molybdenum oxide) is water soluble, the molybdenum oxides can be removed by direct cleansing using water. As such, the subsequent fabrication processes can be simplified. In addition, the first etch stopper <NUM> and the second etch stopper <NUM> can also comprise titanium or aluminum.

Optionally, the thicknesses of the first etch stopper <NUM> and the second etch stopper <NUM> can be between <NUM>Å and <NUM>Å.

Optionally, the active layer <NUM> can comprise low temperature poly-silicon (LTPS).

If the active layer <NUM> comprises low temperature poly-silicon (LTPS), as shown in <FIG>, the active layer <NUM> optionally further comprises a first doping region <NUM> and a second doping region <NUM>, and the first etch stopper <NUM> is disposed over the first doping region <NUM>, and the second etch stopper <NUM> is disposed over the second doping region <NUM>.

Optionally, the first doping region <NUM> and the second doping region <NUM> can both be heavily doped regions.

In this embodiment of the thin-film transistor, by arranging a first etch stopper <NUM> and a second etch stopper <NUM> between the insulating layer <NUM> and the active layer <NUM>, the insulating layer <NUM> can be directly and thoroughly etched when the insulating layer <NUM> is etched to form contact vias. Because of the blocking by the first etch stopper <NUM> and the second etch stopper <NUM>, the active layer <NUM> cannot be etched in the etching process. As such, this embodiment solves the issues of under-etching and over-etching in the etching process to form contact vias, which can thus lead to an improved production yield of thin-film transistors.

Additionally, the first etch stopper <NUM> has a same composition as, and is configured to contact with, the first layer in the source electrode <NUM>. The first etch stopper <NUM> and the second etch stopper <NUM> are configured to have a same composition. The source electrode <NUM> and the drain electrode <NUM> are configured to have a same composition and a same structure. All these above configurations ensure that the presence of the first etch stopper <NUM> and the second etch stopper <NUM> would not affect the electrical conductivity between the active layer <NUM> and the source electrode <NUM> and the drain electrode <NUM>.

In a second aspect, the present disclosure further provides an array substrate. The array substrate comprises a thin-film transistor according to any of the embodiments as described above, which thus solves the issues of under-etching and over-etching in the etching process to form contact vias and improves the yield rate of thin-film transistors.

Additionally, the first etch stopper <NUM> has a same composition as, and is configured to contact with, the first layer in the source electrode <NUM>. The first etch stopper <NUM> and the second etch stopper <NUM> are configured to have a same composition. The source electrode <NUM> and the drain electrode <NUM> are configured to have a same composition and a same structure. All these above ensure that the presence of the first etch stopper <NUM> and the second etch stopper <NUM> would not affect the electrical conductivity between the active layer <NUM> and the source electrode <NUM> and the drain electrode <NUM>.

As such, the array substrate according to any of the embodiments of the present disclosure as described above has a relatively high production yield, and a relatively good conductivity between the active layer <NUM> and the source electrode <NUM> and the drain electrode <NUM>.

In a third aspect, the present disclosure further provides a display apparatus. The display apparatus comprises an array substrate according to any of embodiments as described above.

The display apparatus as such solves the issues of under-etching and over-etching in the etching process to form contact vias and improves the yield rate of array substrates.

As such, the display apparatus according to any of the embodiments of the present disclosure as described above has a relatively high production yield, and a relatively good conductivity between the active layer <NUM> and the source electrode <NUM> and the drain electrode <NUM>.

In a fourth aspect, the present disclosure further provides a method for manufacturing a thin-film transistor according to any of the embodiments as described above. The manufacturing method comprises:.

In the embodiment, when etching the insulating layer <NUM> to form the first contact via <NUM> and the second contact via <NUM>, the insulating layer <NUM> can be directly etched through onto the first etch stopper <NUM> and the second etch stopper <NUM>. The issue of under-etching can thereby be effectively solved.

Optionally, prior to forming a source electrode <NUM> and a drain electrode <NUM> in the first contract via <NUM> and the second contact via <NUM>, the method further comprises:
Performing a patterning process on the first etch stopper <NUM> and the second etch stopper <NUM> by means of a negative photoresist.

Optionally, the insulating layer <NUM> can be of a single-layer structure, or of a double-layer structure, or of a laminated structure.

Specifically, if the insulating layer <NUM> is of a single-layer structure, the insulating layer <NUM> comprises an interlayer insulating layer <NUM>, and the manufacturing method further comprises:.

If the insulating layer <NUM> is of a single-layer structure, at the same time of forming the insulating layer <NUM> over the active layer <NUM>, the first etch stopper <NUM>, and the second etch stopper <NUM>, the manufacturing method further comprises:
Forming an insulating layer <NUM> over the gate insulating layer <NUM>.

Specifically, as shown in <FIG>, if the insulating layer <NUM> is of a single layer structure, the insulating layer <NUM> formed over the active layer <NUM>, the first etch stopper <NUM>, and the second etch stopper <NUM>, as well as the insulating layer <NUM> formed over the gate insulating layer <NUM>, can be formed in the same step.

As shown in <FIG> and <FIG>, when etching the insulating layer <NUM> to form the contact vias, the interlayer insulating layer <NUM> needs to be thoroughly etched to expose the first etch stopper <NUM> and the second etch stopper <NUM> so as to complete the etching process to form the contact vias.

Specifically, if the insulating layer <NUM> is of a double-layer structure, the insulating layer <NUM> comprises an interlayer insulating layer <NUM> and a gate insulating layer <NUM>, and forming an insulating layer <NUM> over the active layer <NUM>, the first etch stopper <NUM> and the second etch stopper <NUM> further comprises:.

In this embodiment, prior to forming an interlayer insulating layer <NUM> over the gate insulating layer <NUM>, the method can further comprise:
Forming a gate electrode <NUM> over the gate insulating layer <NUM>, as shown in <FIG>.

As shown in <FIG>, <FIG> and <FIG>, when etching the insulating layer <NUM> to form contact vias, the interlayer insulating layer <NUM> and the gate insulating layer <NUM> need to be etched thoroughly to thereby expose the first etch stopper <NUM> and the second etch stopper <NUM> so as to complete the etching process to form the contact vias.

Optionally, if the insulating layer <NUM> is of a double-layer structure, the manufacturing method further comprises:.

If the insulating layer <NUM> is a double-layer structure, at the same time of forming the gate insulating layer <NUM> over the active layer <NUM>, the first etch stopper <NUM> and the second etch stopper <NUM>, the manufacturing method further comprises:
Forming a gate insulating layer <NUM> over the buffer layer <NUM>.

Specifically, if the insulating layer <NUM> is of a double-layer structure, forming a gate insulating layer <NUM> over the active layer <NUM>, the first etch stopper <NUM>, and the second etch stopper <NUM>, and forming a gate insulating layer <NUM> over the buffer layer <NUM> as well, can be completed in a same step.

Optionally, the buffer layer <NUM> can have a composition of silicon oxide and/or silicon nitride, the active layer <NUM> can have a composition of poly-silicon, the gate insulating layer <NUM> can have a composition of silicon oxide, and the interlayer insulating layer <NUM> have a composition of silicon oxide or silicon nitride.

According to the invention, the active layer <NUM> has a composition of low temperature poly-silicon, and forming an active layer <NUM> specifically include:.

Exposing and developing the low temperature poly-silicon layer by means of a positive photoresist to thereby form a patterned active layer <NUM>, wherein the thickness of the positive photoresist is between <NUM> and <NUM>.

Specifically, if the active layer <NUM> has a composition of low temperature poly-silicon, prior to etching the insulating layer <NUM> at positions corresponding to the first etch stopper <NUM> and the second etch stopper <NUM> to form the first contact via <NUM> and the second contact via <NUM>, the manufacturing method further comprises:
Performing injective excitation to the active layer <NUM> to improve the lattice state of the low temperature poly-silicon in the active layer <NUM> to thereby improve the conductivity of the active layer <NUM>.

Specifically, if the insulating layer <NUM> is of a single-layer structure or a double layer-structure and the gate insulating layer <NUM> has a composition of silicon oxide, the gate insulating layer <NUM> can have a thickness between <NUM>Å - <NUM>Å.

If the gate electrode <NUM> comprises molybdenum, the thickness of the gate electrode <NUM> can be <NUM>Å.

If the interlayer insulating layer <NUM> comprises silicon oxide, the thickness of the interlayer insulating layer <NUM> can be <NUM>Å;.

If the interlayer insulating layer <NUM> comprises silicon nitride, the thickness of the interlayer insulating layer <NUM> can be <NUM>Å.

Optionally, when the thin-film transistor is employed for OLED back panel, the manufacturing method further comprises:.

Optionally, the planarizing layer <NUM> can have a composition of acrylic, and can have a thickness of around <NUM>Å. The anode layer <NUM> can have a composition of indium zinc oxide or indium tin oxide, and can have a thickness of around <NUM>Å. The pixel defining layer <NUM> can have a composition of polyimide, and can have a thickness of around <NUM>Å.

Optionally, the source electrode <NUM> can be of an N-layer structure, where N is an integer greater than <NUM>. A first layer in the source electrode <NUM> can be configured to contact with, and electrically couple with, the first etch stopper <NUM>. The first etch stopper <NUM> can have a same composition as the first layer in the source electrode <NUM>.

The second etch stopper <NUM> and the first etch stopper <NUM> can have a same composition. The drain electrode <NUM> and the source electrode <NUM> can have a same composition and a same structure.

The first etch stopper <NUM> and the first layer in the source electrode <NUM> are configured to have a same composition, and the second etch stopper <NUM> and the first layer in the drain electrode <NUM> are configured to have a same composition. Such a configuration ensures that the existence of the first etch stopper <NUM> and the second etch stopper <NUM> would not reduce the electrical conductivity between the active layer <NUM> and the source electrode <NUM> and the drain electrode <NUM>.

According to the invention, if the number of layers of the source electrode <NUM> is <NUM> or <NUM>, neighboring layers in the source electrode <NUM> have different compositions.

Optionally, the source electrode <NUM> and the drain electrode <NUM> can comprise a metal. To be more specific, the source electrode <NUM> and the drain electrode <NUM> can comprise at least one of molybdenum, titanium, and aluminum.

Optionally, if the source electrode <NUM> and the drain electrode <NUM> comprise only molybdenum, the thickness of the source electrode <NUM> and the drain electrode <NUM> can be around <NUM>Å. If the source electrode <NUM> and the drain electrode <NUM> comprise only aluminum, the thickness of the source electrode <NUM> and the drain electrode <NUM> can be around <NUM>Å.

Optionally, the first etch stopper <NUM> can comprise a metal; the second etch stopper <NUM> and the first etch stopper <NUM> can have a same composition.

According to the invention, the first etch stopper <NUM> comprises molybdenum, the second etch stopper <NUM> and the first etch stopper <NUM> have a same composition. Under a circumstance where the first etch stopper <NUM> and the second etch stopper <NUM> both comprise a conductive metal material, the portions of the first etch stopper <NUM> and the second etch stopper <NUM> that are exposed can be oxidized after completion of the etching process to form contact vias.

Under a circumstance where the first etch stopper <NUM> and the second etch stopper <NUM> both comprise molybdenum, after the metal molybdenum is oxidized, the oxidized substance is a water-soluble substance, and thereby the oxidized molybdenum can be directly removed by cleansing with water.

As such, the subsequent processes during manufacturing can be simplified if molybdenum is employed as the material of the etch stoppers. In addition, the first etch stopper <NUM> and the second etch stopper <NUM> can also comprise titanium or aluminum.

According to the invention, the thicknesses of the first etch stopper <NUM> and the second etch stopper <NUM> is between <NUM>Å and <NUM>Å.

According to the invention, the active layer <NUM> has a composition of low temperature poly-silicon, as shown in <FIG>, and the active layer <NUM> comprises a first doping region <NUM> and a second doping region <NUM>, wherein the first etch stopper <NUM> is disposed over the first doping region <NUM>, the second etch stopper <NUM> is disposed over the second doping region <NUM>.

Specifically, before forming the first etch stopper <NUM> and the second etch stopper <NUM> over the active layer <NUM>, the manufacturing method can further comprise:.

Performing doping to the active layer <NUM> to thereby form a first doping region <NUM> and a second doping region <NUM> respectively in the active layer <NUM>.

In this embodiment of the method for manufacturing a thin-film transistor, by arranging a first etch stopper <NUM> and a second etch stopper <NUM> between the insulating layer <NUM> and the active layer <NUM>, the insulating layer <NUM> can be directly and thoroughly etched when the insulating layer <NUM> is etched to form contact vias. Because of the blocking by the first etch stopper <NUM> and the second etch stopper <NUM>, the active layer <NUM> cannot be etched in the etching process. As such, this embodiment of the fabrication method solves the issues of under- etching and over-etching in the etching process to form contact vias, which can lead to an improved production yield of thin-film transistors.

Claim 1:
A method for manufacturing a thin-film transistor, comprising:
forming an active layer (<NUM>) using low temperature poly-silicon (LTPS), wherein the active layer (<NUM>) comprises a first doping region (<NUM>) and a second doping region (<NUM>);;
forming a first etch stopper (<NUM>) and a second etch stopper (<NUM>) respectively over the first doping region (<NUM>) and the second doping region (<NUM>), thicknesses of the first etch stopper (<NUM>) and the second etch stopper (<NUM>) each being between <NUM>Å and <NUM>Å ;
forming a second layer over the active layer and the at least one etch stopper (<NUM>,<NUM>);
forming at least one contact via (<NUM>, <NUM>) in the second layer, such that a bottom opening of each contact via (<NUM>, <NUM>) contacts with a top surface of one etch stopper (<NUM>,<NUM>); and
forming at least one electrode (<NUM>,<NUM>) in the at least one contact via (<NUM>, <NUM>), such that each electrode (<NUM>,<NUM>) extends in one contact via (<NUM>, <NUM>) respectively, and is in contact with, and electrically coupled with, the one etch stopper (<NUM>,<NUM>);
wherein:
the at least one etch stopper (<NUM>,<NUM>) comprises a composition capable of blocking etching to the active layer during formation of the at least one contact via (<NUM>, <NUM>) in the second layer; and
whose oxidization product is removable by a solution, the composition comprising molybdenum;
wherein,
each electrode is formed into an N-layer structure, where N is an integer greater than <NUM>;
neighboring layers of each electrode are made of different compositions ;
a contact layer of each electrode, in contact with and electrically coupled to, one etch stopper (<NUM>,<NUM>), is made of a same composition as the one etch stopper (<NUM>,<NUM>), and where
forming the active layer (<NUM>) using low temperature poly-silicon (LTPS) further comprises: performing injective excitation on the active layer (<NUM>) to improve the lattice state of the low temperature poly-silicon in the active layer (<NUM>) to thereby improve the conductivity of the active layer (<NUM>).