Patent Description:
Many obstacles exist in the further miniaturization of semiconductor components. One such obstacle is the filling of metal interconnects, which affects the yield of modern CMOS devices. Metal interconnect signal lines make contact to lower conductive layers of the integrated circuit through vias that are formed in an insulating layer. It is desirable to fill the contact and interconnect with the metal that is used to form the interconnect layer so as to insure optimal operation of the device.

Conductive metals, such as copper, are presently the materials of choice for the fabrication of interconnect lines in integrated circuits. Conventional techniques used to fill interconnect lines generally include physical vapor deposition, PVD, or atomic layer deposition, ALD, of a barrier material, followed by a liner and then either copper reflow or electroplating.

When using conventional techniques, problems arise in the interconnect lines from the accumulation of relatively large grains of material at the upper surface of an insulating layer, as well as the accumulation of impurities within the conductive bulk. The accumulation of such grains at the edges of the contact via or interconnect can block or otherwise obstruct the contact or interconnect prior to completely filling the contact or interconnect, resulting in the formation of voids, seems, and uneven structures within the contact or interconnect. The aforementioned problem is particularly acute as integrated circuits are fabricated using smaller geometries.

The smaller contacts that are used in smaller geometry devices, such as contacts or interconnects in the tens of nanometers or less range, necessarily have a larger aspect ratio (i.e., relationship of feature height to width) than do larger geometry devices, thereby exacerbating the contact-filling or interconnect-filling difficulties described above. For example, unduly large voids can result in line resistance and contact resistance that are appreciably higher than designed. In addition, thinner regions of the conductive material adjacent to the contact or interconnect fill region will be subject to electro migration, which can result in the eventual opening of the circuits and failure of the device.

<CIT> A1describe removing seams and voids in metal interconnects and associated techniques and configurations. An interconnect structure formed by depositing a metal may be further coupled with other similarly configured interconnect structures. The metal may be a non-copper metal having a melting point that is greater than a melting point of copper (e.g., greater than <NUM>). For example, the metal may be composed of ruthenium (Ru), molybdenum (Mo), tungsten (W) and/or cobalt (Co), equivalents, or combinations thereof. In some embodiments, the metal <NUM> may be composed of rhenium (Re), iron (Fe), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr) and/or technetium (Tc), equivalents, or combinations thereof. The metal may be exposed to a temperature ranging from <NUM> to <NUM> for a time period ranging from <NUM> minutes to a couple of hours, under atmospheric pressure (~<NUM> atm), in the presence of forming gas comprising hydrogen. Further, for example, the pressure may range from <NUM> atm to <NUM> atm or the hydrogen concentration may be greater than <NUM>% by volume in some embodiments.

<CIT> describes a copper film annealing method which can improve reliability of copper wiring by reducing an electric resistance of copper wiring, stabilizing it, and removing an impurity. The annealing method may have an amount of hydrogen added that is preferably at least <NUM>% by weight, more preferably at least <NUM>% by weight, and particularly preferably at least <NUM>% by weight, based on the amount of carbon oxide.

To address the above issues, other materials and deposition techniques have been considered. When using other fill techniques such as chemical vapor deposition, CVD, cyclical deposition/treat processes are employed. One approach utilizes multiple cycles of deposition and anneal in attempt to repair seams and cavities in the conductive material in low-to-sub atmospheric pressures process regimes. This approach results in extremely slow process time, and attempts to reduce process time have resulted in unsatisfactory resistivity. In other approaches, the deposited metal is subjected to extremely high pressures, such as <NUM> bar to <NUM> bar, or more, wherein <NUM> bar = <NUM> MPa, in attempt to repair defects in the conductive material. The exerted pressure forces the deposited metal into the undesired voids within the deposited film. However, subsequent thermal post treatment to correct grain boundary defects or other defects results in partial or full reformation of the void. In addition, the pressures utilized in conventional approaches may result in physical damage to low-k dielectric materials adjacent the interconnect.

Therefore, this is a need for an improved method of correcting seam defects.

According to the present invention, a method of treating a substrate is provided as described in claim <NUM>. Preferred embodiments of the inventions are provided in the dependent claims.

It is to be noted, however, that the appended drawings illustrate only exemplary embodiments.

Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, or grain boundaries from an interconnect formed on the substrate. The method includes heating the substrate in an environment pressurized at a pressure of <NUM> bar to <NUM> bar.

<FIG> is a flow diagram of a method <NUM> for processing a substrate, according to one embodiment of the disclosure. <FIG> is a schematic sectional view of a substrate having interconnects that include one or more defects from a gap-fill process. <FIG> is a schematic sectional view of the substrate of <FIG> after processing. To facilitate explanation of aspects of the disclosure, <FIG> will be explained in conjunction with <FIG>.

Method <NUM> begins at operation <NUM>. In operation <NUM>, a substrate 210a is positioned in a process chamber. The substrate 210a includes one or more trenches <NUM> (two are shown) having a conductive material <NUM> deposited therein to form interconnects. The conductive material <NUM>, which comprises cobalt or ruthenium, is a metal, which may be deposited by CVD, PVD, ALD, plating, or other deposition methods. During deposition of the conductive material <NUM>, one or more of a seam <NUM>, a void <NUM>, or grain boundaries <NUM> may form. The seams <NUM>, the voids <NUM>, and the grain boundaries <NUM> negatively affect performance of the interconnects by increasing electrical resistance of the interconnects.

In operation <NUM>, the substrate 210a is exposed to a hydrogen-containing atmosphere at a predetermined pressure. The hydrogen-containing environment includes hydrogen gas and one or more non-reactive gases, such as diatomic nitrogen or argon. Hydrogen is present within a range of <NUM> atomic percent to <NUM> atomic percent. In one example, hydrogen is present at <NUM> atomic percent. It is contemplated that a lower atomic percentage of hydrogen may dictate longer processing times or elevated temperatures, while higher atomic percentages of hydrogen may dictate the use of additional hardware, such as interlocks. In another example, deuterium may be used in place of, or in combination with, hydrogen in the atomic percentages described above.

The presence of hydrogen in the atmosphere of the process chamber weakens the surface bounds of the conductive material <NUM> to facilitate flow of the conductive material <NUM> into the voids <NUM>. A supra-atmospheric pressure (e.g., a pressure greater than atmospheric pressure) is maintained in the process chamber while exposing the substrate 210a to the hydrogen-containing environment. The pressure within the process chamber is maintained within a range of <NUM> bar to <NUM> bar, wherein <NUM> bar = <NUM> MPa. The application of increased pressure in the presence of the hydrogen-containing environment facilitates movement of the conductive material <NUM> into the voids <NUM>. In addition, the application of increased pressure may facilitate introduction of hydrogen into seam <NUM>, the void <NUM>, or even along the grain boundary <NUM>, to remove contaminants trapped therein. Contaminants may be present as a result of the deposition process of the conductive material <NUM>, or from sources within the process chamber. The presence of the contaminants within the conductive material <NUM> may further increase electrical resistance.

In operation <NUM>, the substrate 210a is heated to a predetermined temperature. The predetermined temperature is <NUM> degrees Celsius to <NUM> degrees Celsius, such as <NUM> degrees Celsius to <NUM> degrees Celsius, for example, <NUM> degrees Celsius. It is contemplated that temperatures above about <NUM> degrees Celsius may adversely the structure of the substrate 210a adjacent to the conductive material <NUM>. For example, excess temperatures may physically disrupt material adjacent the conductive material <NUM>, resulting in leakage of electrical current. In one example, the temperature of the substrate remains below the melting point of the conductive material <NUM>. Even though the melting point of the conductive material <NUM> may not be reached in aspects described herein, the elevated temperature in the presence of the elevated pressure and the hydrogen gas still facilitates atomic movement of the conductive material <NUM>. Thus, filling of the voids <NUM> is promoted.

The increased temperature, in combination with the increased pressure and the hydrogen-containing environment, facilitate movement of the conductive material <NUM> into voids <NUM>, while simultaneously healing or repairing any seams <NUM>, reducing grain boundaries <NUM>, and increasing grain size. The removal of seams <NUM>, voids <NUM>, and grain boundaries <NUM> occurs in a single operation after complete deposition of the conductive material <NUM>.

In contrast, one known approach uses cyclical treatment/deposition processes, in which a small amount of material is deposited in a trench, such as about <NUM> angstroms to about <NUM> angstroms, and then the material is treated. This previously-attempted approach is very inefficient and time consuming due to the number of processes required. In addition, the treatment process of such an approach is a multiple step process, further increasing the number of operations which are performed.

In the multi-cycle treatment process, the substrate is first exposed to high temperatures to weaken the conductive material and merge grains through multi-iteration deposition and treatment cycles, which is very time consuming. Alternatively, the conductive material is subjected to high temperatures after subjecting the conductive material to high pressures (to close a void), which allows the voids to reopen or reform. The very high pressures utilized in previous approaches result in damage to the substrate adjacent the conductive material, due to the excessive force applied to the conductive material and transferred to the substrate.

However, the inventors of the present disclosure have discovered that pressures within a range of <NUM> bar to <NUM> bar, in combination with simultaneous elevated temperatures and hydrogen gas, provides significant improvements over existing approaches. Specifically, seams and voids are repaired, and grain boundaries are reduced, in a single operation which does not subject the substrate 210a to undesirably elevated pressures. Notably, the pressure within a void <NUM> is about <NUM>×<NUM>-<NUM> bar when formed by a PVD process, and the inventors have determined that a pressure within a range of <NUM> bar to about <NUM> bar, is sufficient to facilitate repair of seams <NUM> and voids <NUM>. Thus, the extremely high pressures of conventional approaches, and the undesired consequences thereof, are avoided by aspects of the disclosure. Additionally, unlike existing approaches, the aspects described herein can repair seam, void, and grain defects after completely depositing the conductive material <NUM>. Thus, aspects described herein are not subject to cyclical deposition-treatment, resulting in reduced process time per substrate.

<FIG> schematically illustrates the substrate 210b after operation <NUM>. As illustrated, method <NUM> has removed the grain boundaries <NUM>, resulting in a single grain structure. Additionally, method <NUM> has also removed the seams <NUM> and the voids <NUM>. The resulting conductive material <NUM> has a lower resistance than the conductive material illustrated in <FIG>.

<FIG> illustrates a method of treating a substrate; however, additional embodiments are also contemplated. In another aspect, operations <NUM> and <NUM> may occur simultaneously or in reverse order.

Benefits of the aspects of the disclosure include reduced processing time since seams, voids, and grain boundaries can be corrected in a single operation, rather than in multiple cycles as occurs in existing processes. Additionally, aspects described herein can be performed using less expensive hardware as compared to hardware configured for significantly higher pressures, since significantly lower pressures are utilized in aspects of the disclosure. Additionally, the enhanced flow conditions of conductive metals when processed as described herein may facilitate the use of thinner liners, thus reducing materials expenses and allowing smaller geometries. In some instances, it is contemplated that the liner may be completely excluded. Aspects of the disclosure should not be limited to examples described herein, and may be applied to any instance of metal fill, such as 3D-NAND gate fill, CMOS logic gate fill, bit lines for memory devices, and the like.

Claim 1:
A method of treating a substrate, comprising:
positioning the substrate (210a) in a process chamber, the substrate having an interconnect formed thereon, the interconnect including a conductive material having one or more of a seam (<NUM>) or a void (<NUM>) therein, the conductive material comprising cobalt or ruthenium;
heating the substrate (210a) to a temperature of <NUM> degrees Celsius to <NUM> degrees Celsius; and
exposing the substrate to hydrogen-containing atmosphere at a pressure of1.<NUM> MPa to <NUM> MPa,
wherein the hydrogen-containing atmosphere includes hydrogen present within a range of <NUM> atomic percent to <NUM> atomic percent.