Patent Description:
Embodiments of the present invention relate generally to wireless communication devices. More particularly, embodiments of the invention relate to a transmit/receive switch and a broadband power amplifier matching network of a communication device.

The <NUM> communication requires wide-band operation at the frequency range from <NUM> to <NUM>, necessitating a wide-band and efficient wireless transmitter. Conventionally, power amplifier (PA) and transmit/receive (T/R) switch are designed separately with a single standard 50Ω interface. The separation of these circuits can result in sacrificed transmitter bandwidth, output power, and efficiency.

Major transmitter specifications (for example, bandwidth, output power, and efficiency) are substantially governed or dominated by components located past the PA active transistors, for example, the PA output matching network and the T/R switch. Therefore, co-design of the PA output matching networks and T/R switch can provide a unique advantage and benefit to improve transmitter performance.

Furthermore, a T/R switch can beneficially have a greater degree of design freedom and improved impedance matching if the transmit and receive branches have separate matching inductors.

Prior art document <CIT> discloses systems and techniques relating to wireless communication devices and reconfigurable an integrated RF Front-End for dual-band WLAN transceivers include, according to an aspect, an integrated circuit chip comprising: radio frequency (RF) Front-End circuitry, wherein the RF Front-End circuitry comprises (i) an antenna input line configured to connect with one or more antennas of a wireless communication device, (ii) a transmitter input line, (ii) a first receiver output line, (iii) and a second receiver output line; harmonic trap circuitry coupled with the RF Front-End circuitry via the antenna input line, the harmonic trap circuitry being fully integrated on the integrated circuit chip.

Prior art document <CIT> discloses transceiver systems and methods which employ shunt switches during transmit and receive operating modes. The shunt switches may be configured with various reactive networks to achieve high or low impedance states at power amplifiers or low noise amplifiers in order to reflect or transmit power along a given path. The shunt switches are designed for protection against excessive voltage swings that would otherwise damage components in the transceiver switching circuit. The switching circuits may be implemented in a single chip architecture, which results in manufacturing efficiencies, lower cost and higher reliability circuits. Single or multi band devices may also be employed.

According to some embodiments, an electronic circuit for wireless communication includes a transmit/receive (T/R) switch. The T/R switch can include a transmit switch, between a transmit port and an antenna port; a receive switch, between a receive port and the antenna port; a transmit inductor, coupled in parallel between the transmit switch the transmit port; and a receive inductor, coupled in parallel between the transmit switch the transmit port.

According to some embodiments, an electronic circuit for wireless communication can be a co-designed circuit with a T/R switch and a power amplifier matching network. The matching network can include a first capacitor coupled, in parallel, to an input port of the matching network circuit; a broadband on-chip transformer coupled, in parallel, to the first capacitor; and a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the matching network circuit, wherein the output port of the matching network circuit is coupled to the transmit port of the T/R switch.

According to some embodiments, a matching network circuit includes a first capacitor coupled, in parallel, to an input port of the matching network circuit; a broadband on-chip transformer coupled, in parallel, to the first capacitor, where the broadband on-chip transformer includes a primary winding and a secondary winding, where the secondary winding is a partial winding. The matching network circuit includes a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the matching network circuit.

In one aspect, the primary and the secondary windings of the broadband on-chip transformer include planar octagonal windings. In another embodiment, the planar octagonal winding of the primary winding are electromagnetically coupled to the planar octagonal winding of the secondary windings along a planar axis. In another embodiment, the primary and the secondary windings are separated by a layer of dielectric. The primary and secondary windings may be disposed on different substrate layers as a part of an integrated circuit (IC).

In one embodiment, the partial winding of the secondary winding includes approximately <NUM> turns winding. In one embodiment, the primary winding is coupled to a power supply source to supply a bias voltage to a circuit of the input port. In one embodiment, the secondary winding includes at least two conductive layers.

According to another aspect, a two-stage power amplifier (PA) includes a first amplifier stage, a second amplifier stage, a first matching network circuit coupled in between the first amplifier stage and the second amplifier stage, and a second matching network circuit coupled to an output port of the second amplifier stage. The second matching network includes a first capacitor coupled, in parallel, to an input port of the second matching network circuit; a broadband on-chip transformer coupled, in parallel, to the first capacitor, where the broadband on-chip transformer includes a primary winding and a secondary winding, where the secondary winding is a partial winding. The primary and secondary windings may be disposed on different substrate layers as a part of an integrated circuit. The second matching network includes a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the second matching network circuit.

According to another aspect, an RF frontend integrated circuit (IC) device includes a two-stage power amplifier (PA) to amplify a transmitted signal. The PA includes a first amplifier stage, a second amplifier stage, a first matching network circuit coupled in between the first amplifier stage and the second amplifier stage, and a second matching network circuit coupled to an output port of the second amplifier stage. The second matching network includes a first capacitor coupled, in parallel, to an input port of the second matching network circuit; a broadband on-chip transformer coupled, in parallel, to the first capacitor, where the broadband on-chip transformer includes a primary winding and a secondary winding, where the secondary winding is a partial winding. The primary and secondary windings may be disposed on different substrate layers as a part of an integrated circuit. The second matching network includes a second capacitor coupled, in series, in between the broadband on-chip transformer and an output port of the second matching network circuit.

<FIG> is a block diagram illustrating an example of a wireless communication device according one embodiment of the invention. Referring to <FIG>, wireless communication device <NUM>, also simply referred to as a wireless device, includes, amongst others, an RF frontend module <NUM> and a baseband processor <NUM>. Wireless device <NUM> can be any kind of wireless communication devices such as, for example, mobile phones, laptops, tablets, network appliance devices (e.g., Internet of thing or IOT appliance devices), etc..

In a radio receiver circuit, the RF frontend is a generic term for all the circuitry between the antenna up to and including the mixer stage. It consists of all the components in the receiver that process the signal at the original incoming radio frequency, before it is converted to a lower intermediate frequency (IF). In microwave and satellite receivers it is often called the low-noise block (LNB) or low-noise downconverter (LND) and is often located at the antenna, so that the signal from the antenna can be transferred to the rest of the receiver at the more easily handled intermediate frequency. A baseband processor is a device (a chip or part of a chip) in a network interface that manages all the radio functions (all functions that require an antenna).

In one embodiment, RF frontend module <NUM> includes one or more RF transceivers, where each of the RF transceivers transmits and receives RF signals within a particular frequency band (e.g., a particular range of frequencies such as non-overlapped frequency ranges) via one of a number of RF antennas. The RF frontend IC chip further includes a frequency synthesizer coupled to the RF transceivers. The frequency synthesizer generates and provides a local oscillator (LO) signal to each of the RF transceivers to enable the RF transceiver to mix, modulate, and/or demodulate RF signals within a corresponding frequency band. The RF transceivers and the frequency synthesizer may be integrated within a single IC chip as a single RF frontend IC chip or package.

<FIG> is a block diagram illustrating an example of an RF frontend integrated circuit according to one embodiment of the invention. Referring to <FIG>, RF frontend <NUM> includes, amongst others, a frequency synthesizer <NUM> coupled to a multi-band RF transceiver <NUM>. Transceiver <NUM> is configured to transmit and receive RF signals within one or more frequency bands or a broad range of RF frequencies via RF antenna <NUM>. In one embodiment, transceiver <NUM> is configured to receive one or more LO signals from frequency synthesizer <NUM>. The LO signals are generated for the one or more corresponding frequency bands. The LO signals are utilized to mix, modulate, demodulated by the transceiver for the purpose of transmitting and receiving RF signals within corresponding frequency bands. Although there is only one transceiver and antenna shown, multiple pairs of transceivers and antennas can be implemented, one for each frequency bands.

<FIG> is a block diagram illustrating an RF frontend integrated circuit according to one embodiment. Referring to <FIG>, frequency synthesizer <NUM> may represent frequency synthesizer <NUM> as described above. In one embodiment, frequency synthesizer <NUM> is communicatively coupled to a broadband transmitter <NUM> and a broadband receiver <NUM>, which may be a part of a transceiver such as transceiver <NUM>. The broadband transmitter <NUM> transmits RF for a number of frequency bands.

In one embodiment, transmitter <NUM> includes filters <NUM>, mixers <NUM>, and a power amplifier <NUM>. Filters <NUM> may be one or more low-pass (LP) filters that receives transmitting (TX) signals to be transmitted to a destination, where the TX signals may be provided from a baseband processor such as baseband processor <NUM>. Mixers <NUM> (also referred to as up-convert mixers) are configured to mix and modulate the TX signals onto one or more carrier frequency signal based on local oscillator (LO) signals provided by frequency synthesizer <NUM>. The modulated signals are then amplified by power amplifier <NUM> and the amplified signals are then transmitted to a remote receiver via antenna <NUM>.

The RF frontend integrated circuit can include a receiver <NUM>. Receiver <NUM> includes a low noise amplifier (LNA) <NUM>, mixer(s) <NUM>, and filter(s) <NUM>. LNA <NUM> is to receive RF signals from a remote transmitter via antenna <NUM> and to amplify the received RF signals. The amplified RF signals are then demodulated by mixer(s) <NUM> (also referred to as a down-convert mixer) based on a LO signal provided by frequency synthesizer <NUM>. The demodulated signals are then processed by filter(s) <NUM>, which may be a low-pass filter. In one embodiment, transmitter <NUM> and receiver <NUM> share antenna <NUM> via a transmitting and receiving (T/R) switch <NUM>. T/R switch <NUM> is configured to switch between transmitter <NUM> and receiver <NUM> to couple antenna <NUM> to either transmitter <NUM> or receiver <NUM> at a particular point in time. Although there is only one pair of transmitter and receiver shown, multiple pairs of transmitters and receivers may be coupled to frequency synthesizer <NUM>, one for each of the multiple frequency bands.

<FIG> is a block diagram illustrating an example of a power amplifier (PA) integrated circuit according to one embodiment. Referring to <FIG>, PA <NUM> can be PA <NUM> of <FIG>. PA <NUM> can include driver stage <NUM>, inter-stage matching network <NUM>, output stage <NUM>, and output matching network <NUM>. Inter-stage matching network <NUM> and output matching network <NUM> can match impedances seen by driver stage <NUM> and output stage <NUM> to maximize a power transfer for PA <NUM>. For example, inter-stage matching network <NUM> can match an input impedance and an output impedance to an impedance seen at the output port of driver stage <NUM> and an impedance seen at the input port of output stage <NUM>, respectively, to maximize a power transfer from an input port of PA <NUM> to the output stage <NUM>. Output matching network <NUM> can match the impedance seen from an output port of output stage <NUM> to maximize a power transfer from the output stage <NUM> to the output port of PA <NUM>. Lastly, output matching network <NUM> can provide differential to single-ended conversion for a single-ended output port of PA <NUM>.

Referring to <FIG>, driver stage <NUM> and output stage <NUM> are amplifier stages of PA <NUM>. In one embodiment, driver stage <NUM> and output stage <NUM> are differential cascode amplifier stages. A differential amplifier is an amplifier that amplifies a difference between two input voltages but suppresses any voltage common to the two inputs. Differential amplifiers offer common-mode noise rejection such as noise from nearby components and power supplies. A cascode amplifier is a two-stage amplifier (e.g., FETs or BJTs) that includes of a common-source (or a common-emitter for BJTs) stage feeding into a common-gate (or a common-base for BJTs) stage. Compared with single-stage amplifiers, cascode amplifiers have a higher input output isolation (i.e., reduces a leakage in reverse transmission from the output to the input ports as there is no direct coupling between the input and output ports), a higher input impedance, a higher output impedance, a higher gain, and a higher bandwidth. Here, driver stage <NUM> and output stage <NUM> include amplifiers that combine a differential topology and a cascode topology to achieve a large output swing, a wide bandwidth, with a high output power.

Referring now to <FIG>, a transmit inductor LTX <NUM> can be coupled in parallel between the transmit switch <NUM> and the transmit port <NUM>. Similarly, a receive inductor LRX <NUM> can be coupled in parallel between the receive switch <NUM> and the receive port <NUM>.

The transmit switch <NUM> and the receive switch <NUM> can each have two poles, operating in sync, such that when a first pole of the transmit switch is on/closed, thereby connecting the output stage to the antenna, a first pole of the receive switch is off/open, thereby disconnecting the LNA from the antenna. Simultaneously, a second pole of the transmit switch is off/open, and a second pole of the receive switch is on/closed, thereby grounding the input to the LNA.

In one embodiment, as shown in <FIG>, the poles of the transmit and receive switches <NUM> and <NUM> each comprise one or more mosfets, having control inputs that are alternatingly synced by Vctrl <NUM> and inverse Vctrl <NUM> to control the poles as described above.

Beneficially, LTX and LRX can be sized to optimize the impedance matching in the TX and RX paths. Separate inductors LTX and LRX, rather than a single inductor at the antenna <NUM>, provide an additional design freedom to optimize the bandwidth and insertion loss in the TX and RX paths. Therefore, it is noted that, in one embodiment, there is no inductor at the antenna <NUM>.

Beneficially, because the inductors are separate, they can be co-designed separately with the transmit and receive circuit. For example, the transmit inductor LTX can be co-designed with the PA output matching network <NUM>, while the LRX can be co-designed with the LNA <NUM>.

Furthermore, the PA output matching network can be implemented using LC lumped elements, transformers, or transmission-line-based distributed components. To reduce chip area, the PA output matching network <NUM> uses a transformer-based matching network with two tuning capacitors, which only occupies a single inductor footprint.

The lumped model equivalent circuit of the broadband output matching network is shown in <FIG>. The PA output matching network <NUM> consists of an on-chip transformer <NUM>, device parasitic capacitor Cdev, and two extra MOM capacitors Cp and Cs. The physical transformer is modeled by an ideal transformer with its magnetizing inductor and leakage inductor, and its parasitic capacitors shunt to ground (Cpar1 and Cpar2). Here, k is the magnetic coupling coefficient, n is the turn radio, Lp is primary self-inductance. Rp and Rs models the loss of the transformer.

For the T/R switch, Ron <NUM>, <NUM> models the on-resistance of the switch transistor and Coff <NUM>, <NUM> models the off-capacitance of the switch transistor.

A high-order passive network is formed to enable an instantaneously broad bandwidth. Thus, in a co-designed circuit, the value of each circuit element is chosen to achieve optimum load impedance seen by the PA output stage (Ropt) over the operation bandwidth while maintaining low insertion loss.

The gain of the PA output stage is defined as gm•|Z|•Loss, where gm is the transconductance of the transistor, Z is the load impedance presented to the PA output stage, and Loss is the passive loss of the output matching network. The goal of the broadband matching is to achieve relatively constant power gain across the operation frequency. Since gm is frequency independent, this transforms the design goal to achieve relatively constant |Z| and Loss over a broad bandwidth. In addition, PA transistors require real-value Z to achieve maximum output power and efficiency (load-pull condition), meaning that the real part of Z should be close to Ropt <NUM> with imaginary part close to <NUM> across the operation frequency.

If the PA output matching is designed for 50Ω antenna impedance without considering the effect from the T/R SW at the beginning, its in-band Z variation and Loss variation become larger after putting together with T/R SW in the systems integration. For example, the loss variation of the PA output matching network itself is <NUM>. 4dB without adding the T/R SW and increases to <NUM>. 8dB after integration with the T/R SW, as shown in <FIG>, graph c.

Indeed, <FIG>, graphs a-c show simulated load impedance seen by the differential output stage and simulated passive loss. In this simulation, the PA output matching network is originally designed for 50W antenna impedance without considering the T/R SW. After adding the T/R SW, the in-band impedance variation and loss variation becomes larger.

Therefore, it is important to consider the parasitic capacitor (Coff) of the T/R Switch from the beginning and absorb it into the passive network synthesis by building a co-designed circuit, for example, by building a co-designed T/R switch and output matching circuit. The transformer parameters (k, n, and Lp), two tuning capacitors (Cp and Cs), and T/R SW TX-path inductor LTX are co-designed to achieve broadband matching.

Claim 1:
A radio frequency "RF" front end circuit for wireless communication, comprising:
a transmit/receive "T/R" switch (<NUM>), the T/R switch (<NUM>) including:
a transmit switch (<NUM>), between a transmit port (<NUM>) and an antenna port;
a receive switch (<NUM>), between a receive port (<NUM>) and the antenna port;
a transmit inductor (<NUM>), coupled in parallel between the transmit switch (<NUM>) and the transmit port (<NUM>); and
a receive inductor (<NUM>), coupled in parallel between the receive switch (<NUM>) and the receive port (<NUM>), wherein the transmit and receive switches each include two poles, wherein
in an "on" position
a first pole is closed, connecting a respective port to the antenna port,
a second pole is open, disconnecting a respective port to a common return, and
in an "off" position
the first pole is open, disconnecting the respective port from the antenna port, and
the second pole is closed, connecting the respective port to the common return.