Patent Description:
A storage device refers to a device that stores data under control of a host device, such as a computer, a smartphone, or a smart pad. The storage device includes a device which stores data on a magnetic disk, such as a hard disk drive (HDD), or a device which stores data in a semiconductor memory, in particular, a nonvolatile memory, such as a solid state drive (SSD) or a memory card.

A nonvolatile memory includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc..

With the development of semiconductor manufacturing technologies, the degree of integration of the storage device and a volume thereof continue to increase. The high degree of integration of the storage device makes it possible to reduce costs necessary to manufacture the storage device. However, the high degree of integration of the storage device causes the scale-down and structure change of the storage device, thereby causing various new issues. New issues cause a damage of data stored in the storage device. This may mean that the reliability of the storage device is reduced.

Various reliability check methods may be used to prevent the reliability of the storage device from being reduced. However, because the introduction of reliability check methods requires an additional time for executing the reliability check method, the latency of the storage device may increase or the throughput thereof may decrease.

From <CIT> it is known an operating method which includes receiving a read command and a read address, performing a read operation about memory cells selected according to the read address, and performing a reliability verification read operation about unselected memory cells adjacent to the selected memory cells. A number of memory cells each corresponding to at least one state of an erase state and program states of the unselected memory cells is counted as a count value based on the result of the reliability verification read operation. Data read through the read operation is output to an external device and data read through the reliability verification read operation is not output to the external device.

Embodiments of the present disclosure provide a storage device capable of reducing a time necessary for a check read operation while securing reliability through the check read operation and an operating method of the storage device.

According to an embodiment, a storage device includes a nonvolatile memory device that includes a plurality of memory blocks and a memory controller. Each of the plurality of memory blocks includes a plurality of cell strings, each including at least one ground selection transistor, two or more memory cells, and at least one string selection transistor stacked on a substrate in a direction perpendicular to the substrate. In a memory block selected from the plurality of memory blocks, the memory controller allows the nonvolatile memory device to perform a read operation on memory cells belonging to a selected page from among the plurality of memory cells in the plurality of cell strings. After the read operation, in the selected memory block, the memory controller allows the nonvolatile memory device to perform a first check read operation on memory cells of a first neighbor page associated with the selected page while sequentially selecting sets of read voltages. After the first check read operation, in the selected memory block, the memory controller allows the nonvolatile memory device to perform a second check read operation on memory cells of a second neighbor page associated with the selected page while sequentially selecting the sets of read voltages. In the second check read operation, the memory controller first selects a set of read voltages, which are used in the first check read operation in which error correction succeeds, from among the sets of read voltages. The memory controller controls the nonvolatile memory device to perform the first check read operation and the second check read operation in response to determining that the read operation is performed in the selected memory block at least a number of times identified by a threshold value.

According to an embodiment, an operating method is disclosed for a storage device which includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes a plurality of memory cells arranged on a substrate in rows and columns and stacked in a direction perpendicular to the substrate. The method includes receiving, at the memory controller, a read request from an external host device; performing, at the storage device, a read operation on selected memory cells of the nonvolatile memory device in response to the read request; performing, at the storage device, a first check read operation on first neighbor memory cells of the selected memory cells of the nonvolatile memory device while sequentially selecting sets of read voltages; performing, at the storage device, a second check read operation on second neighbor memory cells of the selected memory cells of the nonvolatile memory device while sequentially selecting the sets of read voltages; and first selecting, at the storage device, a set of read voltages which are used in the first check read operation in which error correction succeeds, from among the sets of read voltages, in the second check read operation. The method further comprises controlling, by the memory controller, the nonvolatile memory device to perform the first check read operation and the second check read operation, in response to determining that the read operation is performed in the selected memory block at least a number of times identified by a threshold value.

Below, embodiments of the present disclosure may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the present disclosure. Below, the term "and/or" is interpreted as including any one of items listed with regard to the term, or a combination of some of the listed items.

<FIG> illustrates a storage device <NUM> according to an embodiment of the present disclosure. Referring to <FIG>, the storage device <NUM> may include a nonvolatile memory device <NUM>, a memory controller <NUM>, and an external buffer <NUM>. The nonvolatile memory device <NUM> may include a plurality of memory cells. Each of the plurality of memory cells may store two or more bits.

For example, the nonvolatile memory device <NUM> may include at least one of various nonvolatile memory devices such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device.

The memory controller <NUM> may receive various requests for writing data in the nonvolatile memory device <NUM> or reading data from the nonvolatile memory device <NUM> from an external host device. The memory controller <NUM> may store (or buffer) user data transmitted/received to/from the external host device in the external buffer <NUM> and may store metadata for managing the storage device <NUM> in the external buffer <NUM>.

The memory controller <NUM> may access the nonvolatile memory device <NUM> through first signal lines SIGL1 and second signal lines SIGL2. For example, the memory controller <NUM> may transmit a command and an address to the nonvolatile memory device <NUM> through the first signal lines SIGL1. The memory controller <NUM> may exchange data with the nonvolatile memory device <NUM> through the first signal lines SIGL1.

The memory controller <NUM> may transmit a first control signal to the nonvolatile memory device <NUM> through the second signal lines SIGL2. The memory controller <NUM> may receive a second control signal from the nonvolatile memory device <NUM> through the second signal lines SIGL2.

In an embodiment, the memory controller <NUM> may be configured to control two or more nonvolatile memory devices. The memory controller <NUM> may provide first signal lines and second signal lines for each of the two or more nonvolatile memory devices.

As another example, the memory controller <NUM> may provide first signal lines so as to be shared by the two or more nonvolatile memory devices. The memory controller <NUM> may provide some of the second signal lines so as to be shared by the two or more nonvolatile memory devices and may separately provide the others thereof.

The external buffer <NUM> may include a random access memory. For example, the external buffer <NUM> may include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, and a resistive random access memory.

The memory controller <NUM> may include a bus <NUM>, a host interface <NUM>, an internal buffer <NUM>, a processor <NUM>, a buffer controller <NUM>, a memory manager <NUM>, and an error correction code (ECC) block <NUM>.

The bus <NUM> may provide communication channels between the components in the memory controller <NUM>. The host interface <NUM> may receive various requests from the external host device and may parse the received requests. The host interface <NUM> may store the parsed requests in the internal buffer <NUM>.

The host interface <NUM> may transmit various responses to the external host device. The host interface <NUM> may exchange signals with the external host device in compliance with a given communication protocol. The internal buffer <NUM> may include a random access memory. For example, the internal buffer <NUM> may include a static random access memory or a dynamic random access memory.

The processor <NUM> may drive an operating system or firmware for an operation of the memory controller <NUM>. The processor <NUM> may read the parsed requests stored in the internal buffer <NUM> and may generate commands and addresses for controlling the nonvolatile memory device <NUM>. The processor <NUM> may provide the generated commands and addresses to the memory manager <NUM>.

The processor <NUM> may store various metadata for managing the storage device <NUM> in the internal buffer <NUM>. The processor <NUM> may access the external buffer <NUM> through the buffer controller <NUM>. The processor <NUM> may control the buffer controller <NUM> and the memory manager <NUM> such that user data stored in the external buffer <NUM> are provided to the nonvolatile memory device <NUM>.

The processor <NUM> may control the host interface <NUM> and the buffer controller <NUM> such that the data stored in the external buffer <NUM> are provided to the external host device. The processor <NUM> may control the buffer controller <NUM> and the memory manager <NUM> such that data received from the nonvolatile memory device <NUM> are stored in the external buffer <NUM>. The processor <NUM> may control the host interface <NUM> and the buffer controller <NUM> such that data received from the external host device are stored in the external buffer <NUM>.

Under control of the processor <NUM>, the buffer controller <NUM> may write data in the external buffer <NUM> or may read data from the external buffer <NUM>. The memory manager <NUM> may communicate with the nonvolatile memory device <NUM> through the first signal lines SIGL1 and the second signal lines SIGL2 under control of the processor <NUM>.

The memory manager <NUM> may access the nonvolatile memory device <NUM> under control of the processor <NUM>. For example, the memory manager <NUM> may access the nonvolatile memory device <NUM> through the first signal lines SIGL1 and the second signal lines SIGL2. The memory manager <NUM> may communicate with the nonvolatile memory device <NUM>, based on a protocol that is defined in compliance with the standard or is defined by a manufacturer.

The error correction code block <NUM> may perform error correction encoding on data to be provided to the nonvolatile memory device <NUM> by using an error correction code (ECC). The error correction code block <NUM> may perform error correction decoding on data received from the nonvolatile memory device <NUM> by using the error correction code (ECC).

In an embodiment, the storage device <NUM> may not include the external buffer <NUM> and the buffer controller <NUM>. When the external buffer <NUM> and the buffer controller <NUM> are not included in the storage device <NUM>, the above functions of the external buffer <NUM> and the buffer controller <NUM> may be performed by the internal buffer <NUM>.

<FIG> is a block diagram illustrating a nonvolatile memory device <NUM> according to an embodiment of the present disclosure. Referring to <FIG>, the nonvolatile memory device <NUM> includes a memory cell array <NUM>, a row decoder block <NUM>, a page buffer block <NUM>, a pass/fail check block (PFC) <NUM>, a data input and output block <NUM>, a buffer block <NUM>, and a control logic block <NUM>.

The memory cell array <NUM> includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. Each of the memory blocks BLK1 to BLKz may be connected with the row decoder block <NUM> through one or more ground selection lines GSL, word lines WL, and one or more string selection lines SSL. Some of the word lines WL may be used as dummy word lines. Each of the memory blocks BLK1 to BLKz may be connected with the page buffer block <NUM> through a plurality of bit lines BL. The plurality of memory blocks BLK1 to BLKz may be connected in common with the plurality of bit lines BL.

In an embodiment, each of the plurality of memory blocks BLK1 to BLKz may be a unit of an erase operation. Memory cells belonging to each of the memory blocks BLK1 to BLKz may be erased at the same time. As another example, each of the memory blocks BLK1 to BLKz may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of the erase operation.

The row decoder block <NUM> is connected with the memory cell array <NUM> through the ground selection lines GSL, the word lines WL, and the string selection lines SSL. The row decoder block <NUM> operates under control of the control logic block <NUM>.

The row decoder block <NUM> may decode a row address RA received from the buffer block <NUM> and may control voltages to be applied to the string selection lines SSL, the word lines WL, and the ground selection lines GSL based on the decoded row address.

The page buffer block <NUM> is connected with the memory cell array <NUM> through the plurality of bit lines BL. The page buffer block <NUM> is connected with the data input and output block <NUM> through a plurality of data lines DL. The page buffer block <NUM> operates under control of the control logic block <NUM>.

In a program operation, the page buffer block <NUM> may store data to be written in memory cells. The page buffer block <NUM> may apply voltages to the plurality of bit lines BL based on the stored data. In a read operation or in a verify read operation that is performed in the program operation or the erase operation, the page buffer block <NUM> may sense voltages of the bit lines BL and may store a sensing result.

In the verify read operation associated with the program operation or the erase operation, the pass/fail check block <NUM> may verify the sensing result of the page buffer block <NUM>. For example, in the verify read operation associated with the program operation, the pass/fail check block <NUM> may count the number of values (e.g., the number of <NUM>) respectively corresponding to on-cells that are not programmed to a target threshold voltage or more.

In the verify read operation associated with the erase operation, the pass/fail check block <NUM> may count the number of values (e.g., the number of <NUM>) respectively corresponding to off-cells that are not erased to a target threshold voltage or less. When a counting result is greater than or equal to a threshold value, the pass/fail check block <NUM> may output a signal indicating a fail to the control logic block <NUM>. When the counting result is smaller than the threshold value, the pass/fail check block <NUM> may output a signal indicating a pass to the control logic block <NUM>. Depending on a verification result of the pass/fail check block <NUM>, a program loop of the program operation may be further performed or an erase loop of the erase operation may be further performed.

The data input and output block <NUM> is connected with the page buffer block <NUM> through the plurality of data lines DL. The data input and output block <NUM> may receive a column address CA from the buffer block <NUM>. The data input and output block <NUM> may output data read by the page buffer block <NUM> to the buffer block <NUM> depending on the column address CA. The data input and output block <NUM> may provide data received from the buffer block <NUM> to the page buffer block <NUM>, based on the column address CA.

Through the first signal lines SIGL1, the buffer block <NUM> may receive a command CMD and an address ADDR from an external device and may exchange data "DATA" with the external device. The buffer block <NUM> may operate under control of the control logic block <NUM>. The buffer block <NUM> may provide the command CMD to the control logic block <NUM>. The buffer block <NUM> may provide the row address RA of the address ADDR to the row decoder block <NUM> and may provide the column address CA of the address ADDR to the data input and output block <NUM>. The buffer block <NUM> may exchange the data "DATA" with the data input and output block <NUM>.

The control logic block <NUM> may exchange a control signal CTRL with the external device through the second signal lines SIGL2. The control logic block <NUM> may allow the buffer block <NUM> to route the command CMD, the address ADDR, and the data "DATA". The control logic block <NUM> may decode the command CMD received from the buffer block <NUM> and may control the nonvolatile memory device <NUM> based on the decoded command.

In an embodiment, the nonvolatile memory device <NUM> may be manufactured in a bonding manner. The memory cell array <NUM> may be manufactured at a first wafer, and the row decoder block <NUM>, the page buffer block <NUM>, the data input and output block <NUM>, the buffer block <NUM>, and the control logic block <NUM> may be manufactured at a second wafer. The nonvolatile memory device <NUM> may be implemented by coupling the first wafer and the second wafer such that an upper surface of the first wafer and an upper surface of the second wafer face each other.

As another example, the nonvolatile memory device <NUM> may be manufactured in a cell over peri (COP) manner. A peripheral circuit including the row decoder block <NUM>, the page buffer block <NUM>, the data input and output block <NUM>, the buffer block <NUM>, and the control logic block <NUM> may be implemented on a substrate. The memory cell array <NUM> may be implemented over the peripheral circuit. The peripheral circuit and the memory cell array <NUM> may be connected by using through vias.

<FIG> is a circuit diagram illustrating an example of one memory block BLKa of the memory blocks BLK1 to BLKz of <FIG>. Referring to <FIG>, a plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged on a substrate SUB in rows and columns. Each row may extend in a first direction. Each column may extend in a second direction. The plurality of cell strings CS11, CS12, CS21, and CS22 may be connected in common with a common source line CSL formed on (or in) the substrate SUB. In <FIG>, a location of the substrate SUB is depicted as an example for better understanding of the structure of the memory block BLKa.

Cell strings of each row may be connected in common with the ground selection line GSL and may be connected with corresponding string selection lines of first and string selection lines SSL1a and SSL1b and second string selection lines SSL2a to SSL2b. Cell strings of each column may be connected with a corresponding bit line of first and second bit lines BL1 and BL2.

Each cell string may include at least one ground selection transistor GST connected with the ground selection line GSL and a plurality of memory cells MC1 to MC8 respectively connected with a plurality of word lines WL1 to WL8. Cell strings of a first row may further include string selection transistors SSTa and SSTb connected with the first string selection lines SSL1a and SSL1b. Cell strings of a second row may further include string selection transistors SSTa and SSTb connected with the second string selection lines SSL2a and SSL2b.

In each cell string, the ground selection transistor GST, the memory cells MC1 to MC8, and the string selection transistors SSTa and SSTb may be connected in series in a direction perpendicular to the substrate SUB, for example, a third direction and may be sequentially stacked in the direction perpendicular to the substrate SUB. In each of the cell strings CS11, CS12, CS21, and CS22, at least one of the memory cells MC1 to MC8 may be used as a dummy memory cell. The dummy memory cell may not be programmed (e.g., may be program-inhibited) or may be programmed differently from the remaining memory cells of the memory cells MC1 to MC8 other than the dummy memory cell.

In an embodiment, memory cells that are placed at the same height and are associated with one string selection line SSL1a, SSL1b, SSL2a, or SSL2b may form one physical page. Memory cells constituting one physical page may be connected with one sub-word line. Sub-word lines of physical pages located at the same height may be connected in common with one word line. Below, the term "word line" may be used to indicate a word line or a sub-word line and may be interpreted based on the context.

An embodiment in which the memory block BLKa includes the cell strings CS11, CS12, CS21, and CS22 at intersections of a first row corresponding to the first string selection lines SSL1a or SSL1b, a second row corresponding to the second string selection lines SSL2a or SSL2b, a first column corresponding to the first bit line BL, and a second column corresponding to the second bit line BL2 is illustrated, but rows and columns of cell strings included in the memory block BLKa are not limited in number.

<FIG> illustrates an operating method of the storage device <NUM> according to an embodiment of the present disclosure. Referring to <FIG>, <FIG>, <FIG> and <FIG>, in operation S110, the memory controller <NUM> of the storage device <NUM> may receive a read request from the external host device.

In operation S120, in response to the read request, the memory controller <NUM> of the storage device <NUM> may allow the nonvolatile memory device <NUM> to perform a read operation. The nonvolatile memory device <NUM> may transmit the read data to the memory controller <NUM>. The memory controller <NUM> may output, to the external host device, the data transmitted from the nonvolatile memory device <NUM> (i.e., the data read in response to the read request).

In operation S130, the memory controller <NUM> may perform a neighbor check operation. For example, the processor <NUM> of the memory controller <NUM> may perform a check read operation (e.g., as the neighbor check operation) on the nonvolatile memory device <NUM>. The processor <NUM> of the memory controller <NUM> may internally generate random numbers. The processor <NUM> of the memory controller <NUM> may generate a random number for each of the memory blocks BLK1 to BLKz.

The processor <NUM> of the memory controller <NUM> may count the number of times of the read operation performed on each memory block. When the read operation is not performed on a specific memory block a number of times equal to a random number, the processor <NUM> of the memory controller <NUM> may determine that there is no need to perform the check read operation on the nonvolatile memory device <NUM>. Accordingly, the processor <NUM> of the memory controller <NUM> may terminate the process according to the read request.

When the read operation is performed on the specific memory block the number of times equal to the random number, the processor <NUM> of the memory controller <NUM> may determine that there is a need to perform the check read operation on the nonvolatile memory device <NUM>. Accordingly, in operation S140 and operation S150, the storage device <NUM> may perform the check read operation.

In operation S140, the memory controller <NUM> may allow the nonvolatile memory device <NUM> to perform a first check read operation by using sets of read voltages. For example, the memory controller <NUM> may allow the nonvolatile memory device <NUM> to perform the check read operation on first neighbor memory cells of a first neighbor page associated with the page selected for the read operation in operation S120, which will be described in detail later. For example, a neighbor page and neighbor memory cells may include a page and memory cells belonging to the same memory block.

For example, the storage device <NUM> may perform the first check read operation while sequentially selecting the sets of read voltages from an initial set among the sets of read voltages. When the first check read operation using the sets of read voltages succeeds (e.g., an error of the read data is successfully corrected), the first check read operation may end.

In operation S150, the memory controller <NUM> may allow the nonvolatile memory device <NUM> to perform a second check read operation by using the sets of read voltages. For example, the memory controller <NUM> may allow the nonvolatile memory device <NUM> to perform the check read operation on second neighbor memory cells of a second neighbor page associated with the page selected for the read operation in operation S120, which will be described in detail later. For example, a neighbor page and neighbor memory cells may include a page and memory cells belonging to the same memory block.

For example, the storage device <NUM> may first select a set of read voltages, which corresponds to the previous error correction success (e.g., which are used in the first check read operation in which error correction succeeds), from among the sets of read voltages. When the second check read operation using the sets of read voltages succeeds (e.g., an error of the read data is successfully corrected), the second check read operation may end.

In an embodiment, when the first check read operation and the second check read operation succeed, the processor <NUM> of the memory controller <NUM> may determine that the reliability of data stored in memory cells of the corresponding memory block is high. In this case, the processor <NUM> of the memory controller <NUM> may terminate the check read operation.

When the first check read operation and/or the second check read operation fails, the processor <NUM> of the memory controller <NUM> may determine that the reliability of the data stored in the memory cells of the corresponding memory block is low. In this case, the processor <NUM> of the memory controller <NUM> may select the corresponding memory block as a target of a read reclaim operation. The read reclaim operation may refer to an operation of improving the reliability of data by reading data of a first memory block (e.g., a target memory block of the read reclaim operation) and writing the read data in a second memory block (e.g., a memory block of an erase state).

In an embodiment, the processor <NUM> of the memory controller <NUM> may allow the nonvolatile memory device <NUM> to immediately perform the read reclaim operation on the corresponding memory block. As another example, the processor <NUM> of the memory controller <NUM> may schedule the read reclaim operation of the corresponding memory block so as to be performed later (e.g., during an idle time).

In an embodiment, the description is given for the circumstance in which the storage device <NUM> performs the check read operation in response to the read request from the external host device. However, the memory controller <NUM> may perform various background operations for managing the nonvolatile memory device <NUM> and the storage device <NUM> and the background operations may cause the read operation of the nonvolatile memory device <NUM>. The read operation associated with the background operation may also cause the check read operation.

<FIG> illustrates a first example of neighbor memory cells of a neighbor page. Neighbor memory cells of a neighbor page will be described with reference to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. An example of the memory block BLKa when viewed in a direction facing away from the first direction is illustrated in <FIG>.

Eight (<NUM>) rows corresponding to first string selection lines SSL1a and SSL1b, second string selection lines SSL2a and SSL2b, third string selection lines SSL3a and SSL3b, fourth string selection lines SSL4a and SSL4b, fifth string selection lines SSL5a and SSL5b, sixth string selection lines SSL6a and SSL6b, seventh string selection lines SSL7a and SSL7b, and eighth string selection lines SSL8a and SSL8b are illustrated in <FIG>.

Each of squares connected with the first to eighth word lines WL1 to WL8 may indicate one page and may correspond to a plurality of memory cells. Memory cells, the number of which corresponds to the number of columns, may be included in the squares, respectively. Each of squares connected with the ground selection line GSL may indicate a set of ground selection transistors GST. The ground selection transistors GST, the number of which corresponds to the number of columns, may be included in the squares, respectively.

A neighbor page of neighbor memory cell may belong to the same memory block as a selected page of selected memory cells. For example, a square filled with vertical lines may indicate a selected page of selected memory cells.

Squares filled with horizontal lines may indicate candidate pages to be selected as a neighbor page. For example, a page of memory cells immediately placed above the selected page of memory cells (e.g., a page of memory cells the closest to the selected page in the third direction) and a page of memory cells page immediately placed below the selected page of memory cells (e.g., a page of memory cells the closest to the selected page in a direction facing away from the third direction) may be selected as a neighbor page of neighbor memory cells.

The processor <NUM> of the memory controller <NUM> may randomly select one of the page (hereinafter referred to as a "vertically immediately placed upper page") immediately placed above the selected page and the page (hereinafter referred to as a "vertically immediately placed lower page") immediately placed below the selected page. The memory controller <NUM> may allow the nonvolatile memory device <NUM> to perform the check read operation on the neighbor page of neighbor memory cells randomly selected.

<FIG> illustrates a second example of neighbor memory cells of a neighbor page. Squares are implemented as described with reference to <FIG>, and thus, additional description will be omitted to avoid redundancy.

Referring to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, a neighbor page of neighbor memory cell may belong to the same memory block as a selected page of selected memory cells. For example, a square filled with vertical lines may indicate a selected page of selected memory cells.

Squares filled with horizontal lines may indicate candidate pages to be selected as a neighbor page. For example, the remaining pages (e.g., first upper pages) of memory cells other than a vertically immediately placed upper page among pages (e.g., upper pages) placed above the selected page of memory cells and the remaining pages (e.g., first lower pages) of memory cells other than a vertically immediately placed lower page among pages (e.g., lower pages) placed below the selected page of memory cells may be selected as neighbor pages of neighbor memory cells.

The processor <NUM> of the memory controller <NUM> may randomly select one of the first upper pages and the first lower pages. For the check read operation, the memory controller <NUM> may randomly select string selection lines belonging to one row from among the remaining string selection lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, SSL3b, SSL4a, SSL4b, SSL6a, SSL6b, SSL7a, SSL7b, SSL8a, and SSL8b other than the selected string selection lines SSL5a and SSL5b corresponding to the selected page.

The memory controller <NUM> may randomly select one of an upper page and a lower page of a row selected for the check read operation as a neighbor page for the check read operation. The memory controller <NUM> may allow the nonvolatile memory device <NUM> to perform the check read operation on the neighbor page of neighbor memory cells randomly selected.

Referring to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, a neighbor page of a neighbor memory cell may belong to the same memory block as a selected page of selected memory cells. For example, a square filled with vertical lines may indicate a selected page of selected memory cells.

Squares filled with horizontal lines may be candidate pages to be selected as a neighbor page. For example, the memory controller <NUM> may store a list of addresses of pages including memory cells having low reliability from among memory cells. For example, the pages including the memory cells having the low reliability may be determined in the process of manufacturing the nonvolatile memory device <NUM>. The address of the pages including the memory cells having the low reliability may be stored in the nonvolatile memory device <NUM> or nonvolatile storage of the memory controller <NUM> so as to be referenced by the memory controller <NUM>.

The memory controller <NUM> may randomly select a page corresponding to one of the addresses in the list. The memory controller <NUM> may allow the nonvolatile memory device <NUM> to perform the check read operation on the neighbor page of neighbor memory cells randomly selected.

<FIG> illustrates an example of a process in which the storage device <NUM> performs the read operation. Referring to <FIG> and <FIG>, in operation S210, the memory controller <NUM> may receive the read request from the external host device.

In operation S220, in response to the read request being received from the external host device, the memory controller <NUM> may transmit a read command and a first address ADD1 to the nonvolatile memory device <NUM>.

In operation S230, the nonvolatile memory device <NUM> may perform the read operation in response to the read command and the first address ADD1 and may transmit the read data to the memory controller <NUM>.

In operation S240, the error correction code block <NUM> of the memory controller <NUM> may perform error correction decoding on the read data. In operation S250, the memory controller <NUM> may determine whether an error of the read data is corrected. When it is determined that the error of the read data is corrected, in operation S260, the memory controller <NUM> may output the error-corrected data to the external host device. Afterwards, the read operation may be terminated.

When it is determined that the error of the read data is not corrected, in operation S270, the memory controller <NUM> may transmit the read command, the first address ADD1, and voltage information to the nonvolatile memory device <NUM>. The voltage information may include information of read voltages to be used in the read operation of the nonvolatile memory device <NUM>. The nonvolatile memory device <NUM> may again perform the read operation by using the read voltages corresponding to the voltage information and may transmit the read data to the memory controller <NUM> in operation S230. Afterwards, operation S240 and operation S250 may again be performed.

A loop including operation S270, operation S230, operation S240, and operation S250 may be performed at least two times. When an error is not corrected even though the loop is performed the given number of times, the memory controller <NUM> may determine that an uncorrectable error is present in the data corresponding to the first address ADD1. The memory controller <NUM> may notify the external host device that an uncorrectable error occurs and may terminate the read operation.

<FIG> illustrates an example of a process in which the storage device <NUM> performs a first check read operation. Referring to <FIG> and <FIG>, in operation S310, even though the read request is not received from the external host device, in response to determining that the number of read operations performed on a selected memory block reaches a random number, the memory controller <NUM> may transmit the read command and a second address ADD2 to the nonvolatile memory device <NUM>.

In operation S320, in response to the read command and the second address ADD2, the nonvolatile memory device <NUM> may perform the read operation by using a default set of read voltages among sets of read voltages and may transmit the read data to the memory controller <NUM>.

In operation S330, the error correction code block <NUM> of the memory controller <NUM> may perform error correction decoding on the read data. In operation S340, the memory controller <NUM> may determine whether an error of the read data is corrected. When it is determined that the error of the read data is corrected, the memory controller <NUM> may terminate the first check read operation.

When it is determined that the error of the read data is not corrected, in operation S350, the memory controller <NUM> may transmit the read command, the second address ADD2, and voltage information to the nonvolatile memory device <NUM>. The voltage information may include information of read voltages to be used in the read operation of the nonvolatile memory device <NUM>. The nonvolatile memory device <NUM> may again perform the read operation by using a set of read voltages corresponding to the voltage information from among the sets of read voltages and may transmit the read data to the memory controller <NUM> in operation S320. Afterwards, operation S330 and operation S340 may again be performed.

A loop including operation S350, operation S320, operation S330, and operation S340 may be performed at least two times. When an error is not corrected even though the loop is performed the given number of times, the memory controller <NUM> may determine that an uncorrectable error is present in the data corresponding to the second address ADD2. The memory controller <NUM> may select the selected memory block as a target for the read reclaim operation.

<FIG> illustrates an example of a process in which the storage device <NUM> performs a second check read operation. Referring to <FIG> and <FIG>, in operation S410, the memory controller <NUM> may transmit the read command, a third address ADD3, and voltage information to the nonvolatile memory device <NUM> in response to determining that the first check read operation succeeds. The voltage information may indicate a set of read voltages that are used in the first check read operation in which error correction succeeds. In an embodiment, when the first check read operation fails, the second check read operation may be omitted.

In operation S420, in response to the read command and the third address ADD3, the nonvolatile memory device <NUM> may perform the read operation by using the set of read voltages, which are used in the first check read operation in which error correction succeeds, and may transmit the read data to the memory controller <NUM>.

In operation S430, the error correction code block <NUM> of the memory controller <NUM> may perform error correction decoding on the read data. In operation S440, the memory controller <NUM> may determine whether an error of the read data is corrected. When it is determined that the error of the read data is corrected, the memory controller <NUM> may terminate the second check read operation.

When it is determined that the error of the read data is not corrected, in operation S450, the memory controller <NUM> may transmit the read command, the third address ADD3, and voltage information to the nonvolatile memory device <NUM>. The voltage information may include information of read voltages to be used in the read operation of the nonvolatile memory device <NUM>. The nonvolatile memory device <NUM> may again perform the read operation by using the set of read voltages corresponding to the voltage information and may transmit the read data to the memory controller <NUM> in operation S420. Afterwards, operation S430 and operation S440 may again be performed.

A loop including operation S450, operation S420, operation S430, and operation S440 may be performed at least two times. When an error is not corrected even though the loop is performed the given number of times, the memory controller <NUM> may determine that an uncorrectable error is present in the data corresponding to the third address ADD3. The memory controller <NUM> may select the selected memory block as a target for the read reclaim operation.

<FIG> illustrates a first example of a process in which the storage device <NUM> performs first to fourth check read operations. Referring to <FIG> and <FIG>, in operation S510, the storage device <NUM> may perform the first check read operation based on a default policy. According to the default policy, read voltage sets may be sequentially selected from a first read voltage set (e.g., a default read voltage set) to the last read voltage set. In an embodiment, in the first check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using an "A" read voltage set.

In operation S520, the storage device <NUM> may start the second check read operation by using the "A" read voltage set. In the second check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using the "A" read voltage set.

In operation S530, the storage device <NUM> may start the third check read operation by using the "A" read voltage set. The third check read operation may be performed to be the same as the second check read operation described with reference to <FIG>. In the third check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using the "A" read voltage set.

In operation S540, the storage device <NUM> may start the fourth check read operation by using the "A" read voltage set. The fourth check read operation may be performed to be the same as the second check read operation described with reference to <FIG>. In the fourth check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using the "A" read voltage set.

As described with reference to <FIG>, the second check read operation, the third check read operation, and the fourth check read operation may be initiated by using the "A" read voltage set and error correction may succeed in the second check read operation, the third check read operation, and the fourth check read operation by using the "A" read voltage set. Accordingly, the loop is performed only once in the second check read operation, the third check read operation, and the fourth check read operation. Accordingly, a time necessary for the check read operation may decrease.

The temporal and/or spatial stresses that memory cells included in the same memory block experience may be similar. Degradation information or tendency of the reliability of data written in the memory cells of the same memory block may be similar. Accordingly, as described with reference to <FIG>, by performing a current check read operation by using a set of read voltages used in a previous check read operation in which error correction succeeds, a speed at which the read operation is performed may be improved, and a time necessary for the check read operation may decrease.

In an embodiment, to reduce a resource necessary to manage the storage device <NUM>, the storage device <NUM> may delete information of the set of read voltages, which are used in a previous check read operation in which error correction succeeds, after check read operations are completed. As another example, to make the management of the storage device <NUM> easier, the storage device <NUM> may retain (or store) the information of the set of read voltages used in a previous check read operation in which error correction succeeds and may refer to the retained (or stored) information when the check read operations are performed by the read operation later.

<FIG> illustrates a second example of a process in which the storage device <NUM> performs the first to fourth check read operations. Referring to <FIG> and <FIG>, in operation S610, the storage device <NUM> may perform the first check read operation based on a default policy. According to the default policy, read voltage sets may be sequentially selected from a first read voltage set (e.g., a default read voltage set) to the last read voltage set. In an embodiment, in the first check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using the "A" read voltage set.

In operation S620, the storage device <NUM> may start the second check read operation by using the "A" read voltage set. In the second check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using a "B" read voltage set.

In operation S630, the storage device <NUM> may start the third check read operation by using the "B" read voltage set. The third check read operation may be performed to be the same as the second check read operation described with reference to <FIG>. In the third check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using the "B" read voltage set.

In operation S640, the storage device <NUM> may start the fourth check read operation by using the "B" read voltage set. The fourth check read operation may be performed to be the same as the second check read operation described with reference to <FIG>. In the fourth check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using the "B" read voltage set.

As described with reference to <FIG>, while the storage device <NUM> performs the first to fourth check read operations, a set of read voltages used in a check read operation in which error correction succeeds may be changed from the "A" read voltage set to the "B" read voltage set. The storage device <NUM> may continue check read operations by using the "B" read voltage set thus changed.

In an embodiment, when error correction succeeds by using a "C" read voltage set in operation S630, in operation S640, the fourth check read operation may be initiated by using the "C" read voltage set.

<FIG> illustrates a third example of a process in which the storage device <NUM> performs the first to fourth check read operations. Referring to <FIG> and <FIG>, in operation S710, the storage device <NUM> may perform the first check read operation based on a default policy. According to the default policy, read voltage sets may be sequentially selected from a first read voltage set (e.g., a default read voltage set) to the last read voltage set. In an embodiment, in the first check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using the "A" read voltage set.

In operation S720, the storage device <NUM> may start the second check read operation by using the "A" read voltage set. In the second check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>. The storage device <NUM> may successfully perform error correction by using the "B" read voltage set.

As error correction using a set of read voltages used in a previous check read operation in which error correction fails the given number of times, in operation S730, the storage device <NUM> may change a policy for the check read operation based on the default policy such that the third check read operation is performed. The third check read operation may be performed to be the same as the second check read operation described with reference to <FIG>. In the third check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>.

In operation S740, the storage device <NUM> may perform the fourth check read operation based on the default policy. The fourth check read operation may be performed to be the same as the second check read operation described with reference to <FIG>. In the fourth check read operation, a neighbor page or neighbor memory cells may be determined as described with reference to <FIG>.

As described with reference to <FIG>, while the storage device <NUM> performs the first to fourth check read operations, when error correction using a set of read voltages used in a check read operation in which error correction fails a number of times identified by a threshold value, the storage device <NUM> may change a policy such that check read operations are performed based on the default policy. The threshold value may be adjusted accordingly.

In an embodiment, the examples in which the first to fourth check read operations are performed with reference to <FIG>. However, the number of times that a check read operation (or check read operations) is performed is not limited.

<FIG> illustrates an example in which the storage device <NUM> adjusts read voltages in at least one of the second to fourth check read operations. Referring to <FIG> and <FIG>, in operation S810, the storage device <NUM> may perform the check read operation by using a set of read voltages used in a previous check read operation in which error correction succeeds.

In operation S820, the storage device <NUM> may determine whether an error of the read data is corrected. When the error of the read data is corrected, the check read operation may be terminated. When the error of the read data is not corrected, in operation S830 the storage device <NUM> may continue the check read operation based on the default policy in a state where the set of read voltages used in a previous check read operation in which error correction succeeds is excluded.

As another example, when the error of the read data is not corrected, the storage device <NUM> may continue the check read operation while sequentially selecting sets of read voltages in order <NUM>) from a set of read voltages most similar in level to the set of read voltages, which are used in a previous check read operation in which error correction succeeds <NUM>) to a set of read voltages least similar in level to the set of read voltages used in the previous check read operation.

<FIG> is a diagram of a system <NUM> to which a storage device is applied, according to an embodiment. The system <NUM> of <FIG> may basically be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of things (IOT) device. However, the system <NUM> of <FIG> is not necessarily limited to the mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (e.g., a navigation device).

Referring to <FIG>, the system <NUM> may include a main processor <NUM>, memories (e.g., 1200a and 1200b), and storage devices (e.g., 1300a and 1300b). In addition, the system <NUM> may include at least one of an image capturing device <NUM>, a user input device <NUM>, a sensor <NUM>, a communication device <NUM>, a display <NUM>, a speaker <NUM>, a power supplying device <NUM>, and a connecting interface <NUM>.

The main processor <NUM> may control all operations of the system <NUM>, more specifically, operations of other components included in the system <NUM>. The main processor <NUM> may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor <NUM> may include at least one CPU core <NUM> and further include a controller <NUM> configured to control the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. In some embodiments, the main processor <NUM> may further include an accelerator <NUM>, which is a dedicated circuit for a high-speed data operation, such as an artificial intelligence (AI) data operation. The accelerator <NUM> may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and be implemented as a chip that is physically separate from the other components of the main processor <NUM>.

The memories 1200a and 1200b may be used as main memory devices of the system <NUM>. Although each of the memories 1200a and 1200b may include a volatile memory, such as static random access memory (SRAM) and/or dynamic RAM (DRAM), each of the memories 1200a and 1200b may include non-volatile memory, such as a flash memory, phase-change RAM (PRAM) and/or resistive RAM (RRAM). The memories 1200a and 1200b may be implemented in the same package as the main processor <NUM>.

The storage devices 1300a and 1300b may serve as non-volatile storage devices configured to store data, regardless of whether power is supplied thereto, and have larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may respectively include storage controllers (STRG CTRL) 1310a and 1310b and NVMs (Non-Volatile Memories) 1320a and 1320b configured to store data via the control of the storage controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and/or RRAM.

The storage devices 1300a and 1300b may be physically separated from the main processor <NUM> and included in the system <NUM> or implemented in the same package as the main processor <NUM>. In addition, the storage devices 1300a and 1300b may have types of solid-state devices (SSDs) or memory cards and be removably combined with other components of the system <NUM> through an interface, such as the connecting interface <NUM> that will be described below. The storage devices 1300a and 1300b may be devices to which a standard protocol, such as a universal flash storage (UFS), an embedded multi-media card (eMMC), or a non-volatile memory express (NVMe), is applied, without being limited thereto.

The image capturing device <NUM> may capture still images or moving images. The image capturing device <NUM> may include a camera, a camcorder, and/or a webcam.

The user input device <NUM> may receive various types of data input by a user of the system <NUM> and include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor <NUM> may detect various types of physical quantities, which may be obtained from the outside of the system <NUM>, and convert the detected physical quantities into electric signals. The sensor <NUM> may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device <NUM> may transmit and receive signals between other devices outside the system <NUM> according to various communication protocols. The communication device <NUM> may include an antenna, a transceiver, and/or a modem.

The power supplying device <NUM> may appropriately convert power supplied from a battery (not shown) embedded in the system <NUM> and/or an external power source and supply the converted power to each of components of the system <NUM>.

The connecting interface <NUM> may provide connection between the system <NUM> and an external device, which is connected to the system <NUM> and capable of transmitting and receiving data to and from the system <NUM>. The connecting interface <NUM> may be implemented by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE <NUM>, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

In an embodiment, the storage device <NUM> described with reference to <FIG> may be implemented with the storage device 1300a/1300b.

In the above embodiments, components according to embodiments of the present disclosure are referenced by using blocks. The blocks may be implemented with various: (<NUM>) hardware devices, such as an integrated circuit, an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD); (<NUM>) firmware driven in hardware devices; (<NUM>) software such as an application; or (<NUM>) a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit, or circuits enrolled as an intellectual property (IP).

According to embodiments of the present disclosure, read levels of a check read operation may be adjusted with reference to read levels of a previous check read operation. Because the temporal and/or spatial locality is applied to the read levels of the check read operation, a time taken to perform the check read operation and/or the number of times that the check read operation is performed may be reduced.

As is traditional in the field, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the disclosure. An aspect of an embodiment may be achieved through instructions stored within a non-transitory storage medium and executed by a processor.

Claim 1:
A storage device comprising:
a nonvolatile memory device (<NUM>; <NUM>; 1320a, 1320b) including a plurality of memory blocks (BLK1 to BLKz), wherein each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of cell strings (CS11, CS12, CS21, CS22) each including at least one ground selection transistor (GST), two or more memory cells (MC1 to MC8), and at least one string selection transistor (SSTa, SSTb) stacked on a substrate (SUB) in a direction perpendicular to the substrate (SUB); and
a memory controller (<NUM>; 1310a, 1310b), wherein:
in a selected memory block selected from the plurality of memory blocks (BLK1 to BLKz), the memory controller (<NUM>; 1310a, 1310b) controls the nonvolatile memory device (<NUM>; <NUM>; 1320a, 1320b) to perform a read operation (S120) on memory cells (MC1 to MC8) belonging to a selected page from among the memory cells (MC1 to MC8) in the plurality of cell strings (CS11, CS12, CS21, CS22),
after the read operation in the selected memory block, the memory controller (<NUM>; 1310a, 1310b) controls the nonvolatile memory device (<NUM>; <NUM>; 1320a, 1320b) to perform a first check read operation (S140) on memory cells (MC1 to MC8) of a first neighbor page associated with the selected page while sequentially selecting sets of read voltages,
after the first check read operation (S140) in the selected memory block, the memory controller (<NUM>; 1310a, 1310b) controls the nonvolatile memory device (<NUM>; <NUM>; 1320a, 1320b) to perform a second check read operation (S150) on memory cells (MC1 to MC8) of a second neighbor page associated with the selected page while sequentially selecting the sets of read voltages,
in the second check read operation (S150), the memory controller (<NUM>; 1310a, 1310b) first selects a set of read voltages that are used in the first check read operation (S140) and for which error correction succeeds, from among the sets of read voltages, and
in response to determining that the read operation is performed in the selected memory block at least a number of times identified by a threshold value (S130), the memory controller (<NUM>; 1310a, 1310b) controls the nonvolatile memory device (<NUM>; <NUM>; 1320a, 1320b) to perform the first check read operation (S140) and the second check read operation (S150).