Patent Description:
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Exemplary, <CIT> discloses a semiconductor device with a first source layer, a first insulating layer located over the first source layer and a first stacked structure located over the first insulating layer, with first channel layers passing through the first stacked structure and the first insulating layer, and with a second source layer including a first region interposed between the first source layer and the first insulating layer and a second region interposed between the first channel layers and the first insulating layer.

The invention provides a method for forming a three-dimensional memory device according to claim <NUM>.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

In some 3D memory devices, such as 3D NAND memory devices, slit structures (e.g., gate line slits (GLSs)) are used for providing electrical connections to the source of the memory array, such as array common source (ACS), from the front side of the devices. The front side source contacts, however, can affect the electrical performance of the 3D memory devices by introducing both leakage current and parasitic capacitance between the word lines and the source contacts, even with the presence of spacers in between. The formation of the spacers also complicates the fabrication process. Besides affecting the electrical performance, the slit structures usually include wall-shaped polysilicon and/or metal fillings, which can introduce local stress to cause wafer bow or warp, thereby reducing the production yield.

Moreover, some 3D NAND memory devices include semiconductor plugs selectively grown at the bottom of the channel structures. However, as the number of levels of 3D NAND memory devices increases, in particular, with multi-deck architecture, various issues are involved in the fabrication of the bottom semiconductor plugs, such as overlay control, epitaxial layer formation, and etching of memory film and semiconductor channel at the bottom of the channel holes (also known as "SONO punch"), which further complicates the fabrication process and may reduce the yield.

Various embodiments in accordance with the present disclosure provide 3D memory devices with backside source contacts. By moving the source contacts from the front side to the backside, the cost per memory cell can be reduced as the effective memory cell array area can be increased and the spacers formation process can be skipped. The device performance can be improved as well, for example, by avoiding the leakage current and parasitic capacitance between the word lines and the source contacts and by reducing the local stress caused by the front side slit structures (as source contacts). In some embodiments, the 3D memory devices do not include semiconductor plugs selectively grown at the bottom of the channel structures, which are replaced by semiconductor layers (e.g., N-wells) surrounding the sidewalls of the channel structures, which can enable gate-induce-drain-leakage (GIDL)-assisted body biasing for erase operations. As a result, various issues associated with the bottom semiconductor plugs can be avoided, such as overlay control, epitaxial layer formation, and SONO punch, thereby increasing the production yield.

<FIG> illustrates a side view of a cross-section of an exemplary 3D memory device <NUM> with a backside source contact, according to some embodiments of the present disclosure. In some embodiments, 3D memory device <NUM> is a bonded chip including a first semiconductor structure <NUM> and a second semiconductor structure <NUM> stacked over first semiconductor structure <NUM>. First and second semiconductor structures <NUM> and <NUM> are jointed at a bonding interface <NUM> therebetween, according to some embodiments. As shown in <FIG>, first semiconductor structure <NUM> can include a substrate <NUM>, which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable materials.

First semiconductor structure <NUM> of 3D memory device <NUM> can include peripheral circuits <NUM> on substrate <NUM>. It is noted that x-, y-, and z- axes are included in <FIG> to illustrate the spatial relationships of the components in 3D memory device <NUM>. Substrate <NUM> includes two lateral surfaces extending laterally in the x-y plane: a front surface on the front side of the wafer, and a back surface on the backside opposite to the front side of the wafer. The x- and y-directions are two orthogonal directions in the wafer plane: x-direction is the word line direction, and the y-direction is the bit line direction. The z-axis is perpendicular to both the x- and y- axes. As used herein, whether one component (e.g., a layer or a device) is "on," "above," or "below" another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device <NUM>) is determined relative to the substrate of the semiconductor device (e.g., substrate <NUM>) in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

In some embodiments, peripheral circuit <NUM> is configured to control and sense the 3D memory device <NUM>. Peripheral circuit <NUM> can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device <NUM> including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuits <NUM> can include transistors formed "on" substrate <NUM>, in which the entirety or part of the transistors are formed in substrate <NUM> (e.g., below the top surface of substrate <NUM>) and/or directly on substrate <NUM>. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate <NUM> as well. The transistors are high-speed with advanced logic processes (e.g., technology nodes of <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, etc.), according to some embodiments. It is understood that in some embodiments, peripheral circuit <NUM> may further include any other circuits compatible with the advanced logic processes including logic circuits, such as processors and programmable logic devices (PLDs), or memory circuits, such as static random-access memory (SRAM).

In some embodiments, first semiconductor structure <NUM> of 3D memory device <NUM> further includes an interconnect layer (not shown) above peripheral circuits <NUM> to transfer electrical signals to and from peripheral circuits <NUM>. The interconnect layer can include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term "interconnects" can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

As shown in <FIG>, first semiconductor structure <NUM> of 3D memory device <NUM> can further include a bonding layer <NUM> at bonding interface <NUM> and above the interconnect layer and peripheral circuits <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding.

Similarly, as shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can also include a bonding layer <NUM> at bonding interface <NUM> and above bonding layer <NUM> of first semiconductor structure <NUM>. Bonding layer <NUM> can include a plurality of bonding contacts <NUM> and dielectrics electrically isolating bonding contacts <NUM>. Bonding contacts <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer <NUM> can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts <NUM> and surrounding dielectrics in bonding layer <NUM> can be used for hybrid bonding. Bonding contacts <NUM> are in contact with bonding contacts <NUM> at bonding interface <NUM>, according to some embodiments.

As described below in detail, second semiconductor structure <NUM> can be bonded on top of first semiconductor structure <NUM> in a face-to-face manner at bonding interface <NUM>. In some embodiments, bonding interface <NUM> is disposed between bonding layers <NUM> and <NUM> as a result of hybrid bonding (also known as "metal/dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, bonding interface <NUM> is the place at which bonding layers <NUM> and <NUM> are met and bonded. In practice, bonding interface <NUM> can be a layer with a certain thickness that includes the top surface of bonding layer <NUM> of first semiconductor structure <NUM> and the bottom surface of bonding layer <NUM> of second semiconductor structure <NUM>.

In some embodiments, second semiconductor structure <NUM> of 3D memory device <NUM> further includes an interconnect layer (not shown) above bonding layer <NUM> to transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some embodiments, 3D memory device <NUM> is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can include an array of channel structures <NUM> functioning as the array of NAND memory strings. As shown in <FIG>, each channel structure <NUM> can extend vertically through a plurality of pairs each including a conductive layer <NUM> and a dielectric layer <NUM>. The interleaved conductive layers <NUM> and dielectric layers <NUM> are part of a memory stack <NUM>. The number of the pairs of conductive layers <NUM> and dielectric layers <NUM> in memory stack <NUM> (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, or more) determines the number of memory cells in 3D memory device <NUM>. It is understood that in some embodiments, memory stack <NUM> may have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of conductive layers <NUM> and dielectric layers <NUM> in each memory deck can be the same or different.

Memory stack <NUM> includes a plurality of interleaved conductive layers <NUM> and dielectric layers <NUM>. Conductive layers <NUM> and dielectric layers <NUM> in memory stack <NUM> can alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack <NUM>, each conductive layer <NUM> can be adjoined by two dielectric layers <NUM> on both sides, and each dielectric layer <NUM> can be adjoined by two conductive layers <NUM> on both sides. Conductive layers <NUM> can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer <NUM> can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of conductive layer <NUM> can extend laterally as a word line, ending at one or more staircase structures of memory stack <NUM>. Dielectric layers <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can also include a first semiconductor layer <NUM> above memory stack <NUM> and a second semiconductor layer <NUM> above and in contact with first semiconductor layer <NUM>. According to the invention, each of first and second semiconductor layers <NUM> and <NUM> is an N-type doped semiconductor layer, e.g., a silicon layer doped with N-type dopant(s), such as phosphorus (P) or arsenic (As). In those cases, first and second semiconductor layers <NUM> and <NUM> may be viewed collectively as an N-type doped semiconductor layer <NUM>/<NUM> above memory stack <NUM>. In some embodiments, each of first and second semiconductor layers <NUM> and <NUM> includes an N-well. That is, each of first and second semiconductor layers <NUM> and <NUM> can be a region in a P-type substrate that is doped with N-type dopant(s), such as P or As. It is understood that the doping concentrations in first and second semiconductor layers <NUM> and <NUM> may be the same or different. First semiconductor layer <NUM> includes polysilicon, for example, N-type doped polysilicon, according to some embodiments. As described below in detail, first semiconductor layer <NUM> can be formed above a P-type silicon substrate by thin film deposition and/or epitaxial growth. In contrast, second semiconductor layer <NUM> includes single crystalline silicon, for example, N-type doped single crystalline silicon, according to some embodiments. As described below in detail, second semiconductor layer <NUM> can be formed by implanting N-type dopant(s) into a P-type silicon substrate having single crystalline silicon. In some embodiments, the lateral dimension of second semiconductor layer <NUM> in the x-direction (e.g., the word line direction) is greater than the lateral dimension of first semiconductor layer <NUM> in the x-direction.

In some embodiments, each channel structure <NUM> includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel <NUM>) and a composite dielectric layer (e.g., as a memory film <NUM>). In some embodiments, semiconductor channel <NUM> includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, memory film <NUM> is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of channel structure <NUM> can be partially or fully filled with a capping layer including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure <NUM> can have a cylinder shape (e.g., a pillar shape). The capping layer, semiconductor channel <NUM>, the tunneling layer, storage layer, and blocking layer of memory film <NUM> are arranged radially from the center toward the outer surface of the pillar in this order, according to some embodiments. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, memory film <NUM> can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some embodiments, channel structure <NUM> further includes a channel plug <NUM> in the bottom portion (e.g., at the lower end) of channel structure <NUM>. As used herein, the "upper end" of a component (e.g., channel structure <NUM>) is the end farther away from substrate <NUM> in the z-direction, and the "lower end" of the component (e.g., channel structure <NUM>) is the end closer to substrate <NUM> in the z-direction when substrate <NUM> is positioned in the lowest plane of 3D memory device <NUM>. Channel plug <NUM> can include semiconductor materials (e.g., polysilicon). In some embodiments, channel plug <NUM> functions as the drain of the NAND memory string.

As shown in <FIG>, each channel structure <NUM> can extend vertically through interleaved conductive layers <NUM> and dielectric layers <NUM> of memory stack <NUM> and first semiconductor layer <NUM>, e.g., an N-type doped polysilicon layer. According to the invention, first semiconductor layer <NUM> surrounds part of channel structure <NUM> and is in contact with semiconductor channel <NUM> including polysilicon. That is, memory film <NUM> is disconnected at part of channel structure <NUM> that abuts first semiconductor layer <NUM>, exposing semiconductor channel <NUM> to be in contact with the surrounding first semiconductor layer <NUM>, according to some embodiments. As a result, first semiconductor layer <NUM> surrounding and in contact with semiconductor channel <NUM> can work as a "sidewall semiconductor plug" of channel structure <NUM> to replace the "bottom semiconductor plug" as described above, which can mitigate issues such as overlay control, epitaxial layer formation, and SONO punch.

In some embodiments, each channel structure <NUM> can extend vertically further into second semiconductor layer <NUM>, e.g., an N-type doped single crystalline silicon layer. That is, each channel structure <NUM> extends vertically through memory stack <NUM> into the N-type doped semiconductor layer (including first and second semiconductor layers <NUM> and <NUM>), according to some embodiments. As shown in <FIG>, the top portion (e.g., the upper end) of channel structures <NUM> is in second semiconductor layer <NUM>, according to some embodiments. In some embodiments, each of first and second semiconductor layers <NUM> and <NUM> is an N-type doped semiconductor layer, e.g., an N-well, to enable GIDL-assisted body biasing for erase operations, as opposed to P-well bulk erase operations. The GIDL around the source select gate of the NAND memory string can generate hole current into the NAND memory string to raise the body potential for erase operations.

As shown in <FIG>, second semiconductor structure <NUM> of 3D memory device <NUM> can further include insulating structures <NUM> each extending vertically through interleaved conductive layers <NUM> and dielectric layers <NUM> of memory stack <NUM>. Different from channel structure <NUM> that extends further through first semiconductor layer <NUM>, insulating structures <NUM> stops at first semiconductor layer <NUM>, i.e., does not extend vertically into the N-type doped semiconductor layer, according to some embodiments. That is, the top surface of insulating structure <NUM> can be flush with the bottom surface of first semiconductor layer <NUM>. Each insulating structure <NUM> can also extend laterally to separate channel structures <NUM> into a plurality of blocks. That is, memory stack <NUM> can be divided into a plurality of memory blocks by insulating structures <NUM>, such that the array of channel structures <NUM> can be separated into each memory block. Different from the slit structures in existing 3D NAND memory devices described above, which include front side ACS contacts, insulating structure <NUM> does not include any contact therein (i.e., not functioning as the source contact) and thus, does not introduce parasitic capacitance and leakage current with conductive layers <NUM> (including word lines), according to some embodiments. In some embodiments, each insulating structure <NUM> includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure <NUM> may be filled with silicon oxide.

Instead of the front side source contacts, 3D memory device <NUM> includes a backside source contact <NUM> above memory stack <NUM> and in contact with second semiconductor layer <NUM>, according to the invention an N-type doped semiconductor layer, as shown in <FIG>. Source contact <NUM> and memory stack <NUM> (and insulating structure <NUM> therethrough) can be disposed at opposites sides of semiconductor layer <NUM> (a thinned substrate) and thus, viewed as a "backside" source contact. In some embodiments, source contact <NUM> extends further into second semiconductor layer <NUM> and is electrically connected to first semiconductor layer <NUM> and semiconductor channel <NUM> of channel structure <NUM> through second semiconductor layer <NUM>. It is understood that the depth that source contact <NUM> extends into second semiconductor layer <NUM> may vary in different examples. In some embodiments in which second semiconductor layer <NUM> includes an N-well, source contact <NUM> is also referred to herein as an "N-well pick up. " In some embodiments, source contact <NUM> is aligned with insulating structure <NUM>. Source contact <NUM> can be laterally aligned with insulating structure <NUM>, i.e., aligned in at least one lateral direction. In one example, source contact <NUM> and insulating structure <NUM> may be aligned in the y-direction (e.g., the bit line direction). In another example, source contact <NUM> and insulating structure <NUM> may be aligned in the x-direction (e.g., the word line direction). Source contacts <NUM> can include any suitable types of contacts. In some embodiments, source contacts <NUM> include a VIA contact. In some embodiments, source contacts <NUM> include a wall-shaped contact extending laterally. Source contact <NUM> can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

As shown in <FIG>, <FIG> memory device <NUM> can further include a BEOL interconnect layer <NUM> above and in contact with source contact <NUM> for pad-out, e.g., transferring electrical signals between 3D memory device <NUM> and external circuits. In some embodiments, interconnect layer <NUM> includes one or more ILD layers <NUM> on second semiconductor layer <NUM> and a redistribution layer <NUM> on ILD layers <NUM>. The upper end of source contact <NUM> is flush with the top surface of ILD layers <NUM> and the bottom surface of redistribution layer <NUM>, and source contact <NUM> extends vertically through ILD layers <NUM> into second semiconductor layer <NUM>, according to some embodiments. ILD layers <NUM> in interconnect layer <NUM> can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Redistribution layer <NUM> in interconnect layer <NUM> can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, redistribution layer <NUM> includes Al. In some embodiments, interconnect layer <NUM> further includes a passivation layer <NUM> as the outmost layer for passivation and protection of 3D memory device <NUM>. Part of redistribution layer <NUM> can be exposed from passivation layer <NUM> as contact pads <NUM>. That is, interconnect layer <NUM> of 3D memory device <NUM> can also include contact pads <NUM> for wire bonding and/or bonding with an interposer.

In some embodiments, second semiconductor structure <NUM> of 3D memory device <NUM> further includes contacts <NUM> and <NUM> through second semiconductor layer <NUM>. As second semiconductor layer <NUM> can be a thinned substrate, for example, an N-well of a P-type silicon substrate, contacts <NUM> and <NUM> are through silicon contacts (TSCs), according to some embodiments. In some embodiments, contact <NUM> extends through second semiconductor layer <NUM> and ILD layers <NUM> to be in contact with redistribution layer <NUM>, such that first semiconductor layer <NUM> is electrically connected to contact <NUM> through second semiconductor layer <NUM>, source contact <NUM>, and redistribution layer <NUM> of interconnect layer <NUM>. In some embodiments, contact <NUM> extends through second semiconductor layer <NUM> and ILD layers <NUM> to be in contact with contact pad <NUM>. Contacts <NUM> and <NUM> each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least contact <NUM> further includes a spacer (e.g., a dielectric layer) to electrically insulate contact <NUM> from second semiconductor layer <NUM>.

In some embodiments, 3D memory device <NUM> further includes peripheral contacts <NUM> and <NUM> each extending vertically to second semiconductor layer <NUM> (e.g., an N-well of a P-type silicon substrate) outside of memory stack <NUM>. Each peripheral contact <NUM> or <NUM> can have a depth greater than the depth of memory stack <NUM> to extend vertically from bonding layer <NUM> to second semiconductor layer <NUM> in a peripheral region that is outside of memory stack <NUM>. In some embodiments, peripheral contact <NUM> is below and in contact with contact <NUM>, such that first semiconductor layer <NUM> is electrically connected to peripheral circuit <NUM> in first semiconductor structure <NUM> through at least second semiconductor layer <NUM>, source contact <NUM>, interconnect layer <NUM>, contact <NUM>, and peripheral contact <NUM>. In some embodiments, peripheral contact <NUM> is below and in contact with contact <NUM>, such that peripheral circuit <NUM> in first semiconductor structure <NUM> is electrically connected to contact pad <NUM> for pad-out through at least contact <NUM> and peripheral contact <NUM>. Peripheral contacts <NUM> and <NUM> each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

As shown in <FIG>, <FIG> memory device <NUM> also includes a variety of local contacts (also known as "C1") as part of the interconnect structure, which are in contact with a structure in memory stack <NUM> directly. In some embodiments, the local contacts include channel local contacts <NUM> each below and in contact with the lower end of a respective channel structure <NUM>. Each channel local contact <NUM> can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts <NUM> each below and in contact with a respective conductive layer <NUM> (including a word line) at the staircase structure of memory stack <NUM> for word line fan-out. Local contacts, such as channel local contacts <NUM> and word line local contacts <NUM>, can be electrically connected to peripheral circuits <NUM> of first semiconductor structure <NUM> through at least bonding layers <NUM> and <NUM>. Local contacts, such as channel local contacts <NUM> and word line local contacts <NUM>, each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

<FIG> illustrates a plan view of a cross-section of an exemplary 3D memory device <NUM> with a backside source contact, according to some embodiments of the present disclosure. 3D memory device <NUM> may be one example of 3D memory device <NUM> in <FIG>, and <FIG> may illustrate a plan view of the cross-section in the AA plane of 3D memory device <NUM> in <FIG>, according to some embodiments. That is, <FIG> shows one example of the plan view at the front side of second semiconductor structure <NUM> of 3D memory device <NUM>.

As shown in <FIG>, <FIG> memory device <NUM> includes a center staircase region <NUM> laterally separating the memory stack in the x-direction (e.g., the word line direction) into two parts: a first core array region 206A and a second core array region 206B, each of which includes an array of channel structures <NUM> (corresponding to channel structures <NUM> in <FIG>), according to some embodiments. It is understood that the layout of the staircase region and core array regions is not limited to the example of <FIG> and may include any other suitable layouts, such as having side staircase regions at the edges of the memory stack. 3D memory device <NUM> also includes parallel insulating structures <NUM> (corresponding to insulating structures <NUM> in <FIG>) in the y-direction (e.g., the bit line direction) each extending laterally in the x-direction to separate core array regions 206A and <NUM> and arrays of channel structures <NUM> therein into blocks <NUM>, according to some embodiments. 3D memory device <NUM> can further include parallel drain select gate cuts <NUM> in the y-direction in block <NUM> to further separate block <NUM> into fingers. Different from existing 3D memory devices with front side source contacts disposed at the counterparts of insulating structures <NUM> (e.g., front side ACS contacts), which interrupt the front side bit line fan-out of certain channel structures <NUM> (e.g., in regions <NUM>), channel structure <NUM>, including the ones in regions <NUM>, in 3D memory device <NUM> without front side source contacts can all have corresponding bit lines fan-out from the front side. As a result, the effective area of core array regions 206A and 206B can be increased by moving the source contacts to the backside of 3D memory device <NUM>.

<FIG> illustrates another plan view of a cross-section of an exemplary 3D memory device with a backside source contact, according to some embodiments of the present disclosure. 3D memory device <NUM> may be one example of 3D memory device <NUM> in <FIG>, and <FIG> illustrates a plan view of the cross-section in the BB plane of 3D memory device <NUM> in <FIG>, according to some embodiments. That is, <FIG> shows one example of the plan view at the backside of second semiconductor structure <NUM> of 3D memory device <NUM>.

As shown in <FIG>, <FIG> memory device <NUM> includes center staircase region <NUM> laterally separating the memory stack in the x-direction (e.g., the word line direction) into two parts: first core array region 206A and second core array region 206B. It is understood that the layout of the staircase region and core array regions is not limited to the example of <FIG> and may include any other suitable layouts, such as having side staircase regions at the edges of the memory stack. In some embodiments, 3D memory device <NUM> includes backside source contacts <NUM> (e.g., in the form of VIA contacts, corresponding to source contacts <NUM> in <FIG>) in core array regions 206A and 206B. For example, source contacts <NUM> may be evenly distributed in core array region 206A or 206B. 3D memory device <NUM> can include backside source lines <NUM> (e.g., in the form of a source line mesh, corresponding to redistribution layer <NUM> in <FIG>) electrically connecting multiple source contacts <NUM>. It is understood that in some examples, multiple source VIA contacts may be replaced by one or more source wall-shaped contacts, i.e., interconnect lines. In some embodiments, 3D memory device <NUM> further includes pad-out contacts <NUM> (e.g., corresponding to contact pad <NUM>, contact <NUM>, and peripheral contact <NUM> in <FIG>) in staircase region <NUM> for pad-out and includes N-well pick up contacts <NUM> (e.g., corresponding to contact <NUM> and peripheral contact <NUM> in <FIG>) in staircase region <NUM> and core array regions 206A and 206B. It is further understood that the layout of pad-out contacts <NUM> and N-well pick up contacts <NUM> is not limited to the example in <FIG> and may include any suitable layouts depending on the design of the 3D memory device, such as the specification (e.g., voltage and resistance) of the electrical performance. In one example, additional pad-out contacts <NUM> may be added outside of the memory stack.

<FIG> illustrate a fabrication process for forming an exemplary 3D memory device with a backside source contact, according to some embodiments of the present disclosure. <FIG> and <FIG> illustrate a flowchart of a method <NUM> for forming an exemplary 3D memory device with a backside source contact, according to some embodiments of the present disclosure. Examples of the 3D memory device depicted in <FIG>, <FIG>, and <FIG> include 3D memory device <NUM> depicted in <FIG>. <FIG>, <FIG>, and <FIG> will be described together. It is understood that the operations shown in method <NUM> are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in <FIG> and <FIG>.

Referring to <FIG>, method <NUM> starts at operation <NUM>, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated in <FIG>, a plurality of transistors are formed on a silicon substrate <NUM> using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed in silicon substrate <NUM> by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some embodiments, isolation regions (e.g., STIs) are also formed in silicon substrate <NUM> by wet etching and/or dry etching and thin film deposition. The transistors can form peripheral circuits <NUM> on silicon substrate <NUM>.

As illustrated in <FIG>, a bonding layer <NUM> is formed above peripheral circuits <NUM>. Bonding layer <NUM> includes bonding contacts electrically connected to peripheral circuits <NUM>. To form bonding layer <NUM>, an ILD layer is deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a portion of a second substrate is doped with an N-type dopant to form a second semiconductor layer. The second substrate can be a P-type silicon substrate. In some embodiments, the first side (e.g., the front side at which semiconductor devices are formed) of the second substrate is doped to form an N-well. As illustrated in <FIG>, an N-type doped semiconductor layer <NUM> is formed on a silicon substrate <NUM>. N-type doped semiconductor layer <NUM> can include an N-well in a P-type silicon substrate <NUM> and include single crystalline silicon. N-type doped semiconductor layer <NUM> can be formed by doping N-type dopant(s), such as P or As, into P-type silicon substrate <NUM> using ion implantation and/or thermal diffusion.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a sacrificial layer above the second semiconductor layer and a dielectric stack on the sacrificial layer are subsequently formed. The dielectric stack includes interleaved stack sacrificial layers and stack dielectric layers. In some embodiments, to subsequently form the sacrificial layer and the dielectric stack, polysilicon is deposited on the second semiconductor layer to form the sacrificial layer, and stack dielectric layers and stack sacrificial layers are alternatingly deposited on the sacrificial layer to form the dielectric stack.

As illustrated in <FIG>, a sacrificial layer <NUM> is formed on N-type doped semiconductor layer <NUM>. Sacrificial layer <NUM> can be formed by depositing polysilicon or any other suitable sacrificial material (e.g., carbon) that can be later selectively removed using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, a pad oxide layer <NUM> is formed between sacrificial layer <NUM> and N-type doped semiconductor layer <NUM> by depositing dielectric materials, such as silicon oxide, or thermal oxidation, on silicon substrate <NUM> prior to the formation of N-type doped semiconductor layer <NUM>.

As illustrated in <FIG>, a dielectric stack <NUM> including a plurality pairs of a first dielectric layer (referred to herein as "stack sacrificial layer" <NUM>) and a second dielectric layer (referred to herein as "stack dielectric layers" <NUM>, together referred to herein as "dielectric layer pairs") is formed on sacrificial layer <NUM>. Dielectric stack <NUM> includes interleaved stack sacrificial layers <NUM> and stack dielectric layers <NUM>, according to some embodiments. Stack dielectric layers <NUM> and stack sacrificial layers <NUM> can be alternatively deposited on sacrificial layer <NUM> above silicon substrate <NUM> to form dielectric stack <NUM>. In some embodiments, each stack dielectric layer <NUM> includes a layer of silicon oxide, and each stack sacrificial layer <NUM> includes a layer of silicon nitride. Dielectric stack <NUM> can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in <FIG>, a staircase structure can be formed on the edge of dielectric stack <NUM>. The staircase structure can be formed by performing a plurality of so-called "trim-etch" cycles to the dielectric layer pairs of dielectric stack <NUM> toward silicon substrate <NUM>. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack <NUM>, dielectric stack <NUM> can have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown in <FIG>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer is formed. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer is formed, a memory film and a semiconductor channel are subsequently formed over a sidewall of the channel hole, and a channel plug is formed above and in contact with the semiconductor channel.

As illustrated in <FIG>, a channel hole is an opening extending vertically through dielectric stack <NUM> and sacrificial layer <NUM> into N-type doped semiconductor layer <NUM>. In some embodiments, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure <NUM> in the later process. In some embodiments, fabrication processes for forming the channel hole of channel structure <NUM> include wet etching and/or dry etching, such as deep-ion reactive etching (DRIE). In some embodiments, the channel hole of channel structure <NUM> extends further through the top portion of N-type doped semiconductor layer <NUM>. The etching process through dielectric stack <NUM> and sacrificial layer <NUM> may continue to etch part of N-type doped semiconductor layer <NUM>. In some embodiments, a separate etching process is used to etch part of N-type doped semiconductor layer <NUM> after etching through dielectric stack <NUM> and sacrificial layer <NUM>.

As illustrated in <FIG>, a memory film <NUM> (including a blocking layer, a storage layer, and a tunneling layer) and a semiconductor channel <NUM> are subsequently formed in this order along sidewalls and the bottom surface of the channel hole. In some embodiments, memory film <NUM> is first deposited along the sidewalls and bottom surface of the channel hole, and semiconductor channel <NUM> is then deposited over memory film <NUM>. The blocking layer, storage layer, and tunneling layer can be subsequently deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form memory film <NUM>. Semiconductor channel <NUM> can then be formed by depositing a semiconductor material, such as polysilicon, over the tunneling layer of memory film <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are subsequently deposited to form memory film <NUM> and semiconductor channel <NUM>.

As illustrated in <FIG>, a capping layer is formed in the channel hole and over semiconductor channel <NUM> to completely or partially fill the channel hole (e.g., without or with an air gap). The capping layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug then can be formed in the top portion of the channel hole. In some embodiments, parts of memory film <NUM>, semiconductor channel <NUM>, and the capping layer that are on the top surface of dielectric stack <NUM> are removed and planarized by CMP, wet etching, and/or dry etching. A recess then can be formed in the top portion of the channel hole by wet etching and/or drying etching parts of semiconductor channel <NUM> and the capping layer in the top portion of the channel hole. The channel plug then can be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Channel structure <NUM> is thereby formed through dielectric stack <NUM> and sacrificial layer <NUM> into N-type doped semiconductor layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the sacrificial layer is replaced with an N-type doped semiconductor layer to form the first semiconductor layer. In some embodiments, to replace the sacrificial layer with the first semiconductor layer, an opening extending vertically through the dielectric stack is formed to expose part of the sacrificial layer, the sacrificial layer is etched through the opening to form a cavity, and N-type doped polysilicon is deposited into the cavity through the opening to form the first semiconductor layer.

As illustrated in <FIG>, a slit <NUM> is an opening that extends vertically through dielectric stack <NUM> and exposes part of sacrificial layer <NUM>. In some embodiments, fabrication processes for forming slit <NUM> include wet etching and/or dry etching, such as DRIE. In some embodiments, slit <NUM> extends further into the top portion of sacrificial layer <NUM>. The etching process through dielectric stack <NUM> may not stop at the top surface of sacrificial layer <NUM> and may continue to etch part of sacrificial layer <NUM>.

As illustrated in <FIG>, sacrificial layer <NUM> (shown in <FIG>) is removed by wet etching and/or dry etching to form a cavity <NUM>. In some embodiments, sacrificial layer <NUM> includes polysilicon, which can be etched by applying tetramethylammonium hydroxide (TMAH) etchant through slit <NUM>, which can be stopped by pad oxide layer <NUM> between sacrificial layer <NUM> and N-type doped semiconductor layer <NUM>. That is, the removal of sacrificial layer <NUM> does not affect N-type doped semiconductor layer <NUM>, according to some embodiments. In some embodiments, prior to the removal of sacrificial layer <NUM>, a spacer <NUM> is formed along the sidewall of slit <NUM>. Spacer <NUM> can be formed by depositing dielectric materials, such as silicon nitride, silicon oxide, and silicon nitride, into slit <NUM> using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof.

As illustrated in <FIG>, part of memory film <NUM> of channel structure <NUM> exposed in cavity <NUM> is removed to expose part of semiconductor channel <NUM> of channel structure <NUM> abutting cavity <NUM>. In some embodiments, parts of the blocking layer (e.g., including silicon oxide), storage layer (e.g., including silicon nitride), and tunneling layer (e.g., including silicon oxide) are etched by applying etchants through slit <NUM> and cavity <NUM>, for example, phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide. The etching can be stopped by semiconductor channel <NUM> of channel structure <NUM>. Spacer <NUM> including dielectric materials (shown in <FIG>) can also protect dielectric stack <NUM> from the etching of memory film <NUM> and can be removed by the etchants in the same step as removing part of memory film <NUM>. Similarly, pad oxide layer <NUM> (shown in <FIG>) on N-type doped semiconductor layer <NUM> can be removed as well by the same step as removing part of memory film <NUM>.

As illustrated in <FIG>, an N-type doped semiconductor layer <NUM> is formed above and in contact with N-type doped semiconductor layer <NUM>. In some embodiments, N-type doped semiconductor layer <NUM> is formed by depositing polysilicon into cavity <NUM> (shown in <FIG>) through slit <NUM> using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. In some embodiments, N-type doped semiconductor layer <NUM> is formed by selectively filling cavity <NUM> with polysilicon epitaxially grown from the exposed part of semiconductor channel <NUM> (including polysilicon). The fabrication processes for epitaxially growing N-type doped semiconductor layer <NUM> can include pre-cleaning cavity <NUM> followed by, for example, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combinations thereof. In some embodiments, in-situ doping of N-type dopants, such as P or As, is performed when depositing or epitaxially growing polysilicon to form an N-type doped polysilicon layer as N-type doped semiconductor layer <NUM>. N-type doped semiconductor layer <NUM> can fill cavity <NUM> to be in contact with the exposed part of semiconductor channel <NUM> of channel structure <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the dielectric stack is replaced with a memory stack, for example, using the so-called "gate replacement" process, such that the channel structure extends vertically through the memory stack and the first semiconductor layer into the second semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, the stack sacrificial layers are replaced with stack conductive layers through the opening. In some embodiments, the memory stack includes interleaved stack conductive layers and stack dielectric layers.

As illustrated in <FIG>, stack sacrificial layers <NUM> (shown in <FIG>) are replaced with stack conductive layers <NUM>, and a memory stack <NUM> including interleaved stack conductive layers <NUM> and stack dielectric layers <NUM> is thereby formed, replacing dielectric stack <NUM> (shown in <FIG>). In some embodiments, lateral recesses (not shown) are first formed by removing stack sacrificial layers <NUM> through slit <NUM>. In some embodiments, stack sacrificial layers <NUM> are removed by applying etchants through slit <NUM>, creating the lateral recesses interleaved between stack dielectric layers <NUM>. The etchants can include any suitable etchants that etch stack sacrificial layers <NUM> selective to stack dielectric layers <NUM>. As illustrated in <FIG>, stack conductive layers <NUM> (including gate electrodes and adhesive layers) are deposited into the lateral recesses through slit <NUM>. In some embodiments, a gate dielectric layer <NUM> is deposited into the lateral recesses prior to stack conductive layers <NUM>, such that stack conductive layers <NUM> are deposited on the gate dielectric layer. Stack conductive layers <NUM>, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, gate dielectric layer <NUM>, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of slit <NUM> as well.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an insulating structure extending vertically through the memory stack is formed. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited into the opening to fill the opening. As illustrated in <FIG>, an insulating structure <NUM> extending vertically through memory stack <NUM> is formed, stopping on the top surface of N-type doped semiconductor layer <NUM>. Insulating structure <NUM> can be formed by depositing one or more dielectric materials, such as silicon oxide, into slit <NUM> to fully or partially fill slit <NUM> (with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, insulating structure <NUM> includes gate dielectric layer <NUM> (e.g., including high-k dielectrics) and a dielectric capping layer <NUM> (e.g., including silicon oxide).

As illustrated in <FIG>, after the formation of insulating structure <NUM>, local contacts, including channel local contacts <NUM> and word line local contacts <NUM>, and peripheral contacts <NUM> and <NUM> are formed. A local dielectric layer can be formed on memory stack <NUM> by depositing dielectric materials, such as silicon oxide or silicon nitride, using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, on top of memory stack <NUM>. Channel local contacts <NUM>, word line local contacts <NUM>, and peripheral contacts <NUM> and <NUM> can be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet etching and/or dry etching, e.g., RIE, followed by filling the contact openings with conductive materials using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated in <FIG>, a bonding layer <NUM> is formed above channel local contacts <NUM>, word line local contacts <NUM>, and peripheral contacts <NUM> and <NUM>. Bonding layer <NUM> includes bonding contacts electrically connected to channel local contacts <NUM>, word line local contacts <NUM>, and peripheral contacts <NUM> and <NUM>. To form bonding layer <NUM>, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can be hybrid bonding. As illustrated in <FIG>, silicon substrate <NUM> and components formed thereon (e.g., memory stack <NUM> and channel structures <NUM> formed therethrough) are flipped upside down. Bonding layer <NUM> facing down is bonded with bonding layer <NUM> facing up, i.e., in a face-to-face manner, thereby forming a bonding interface <NUM> between silicon substrates <NUM> and <NUM>, according to some embodiments. In some embodiments, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. After the bonding, the bonding contacts in bonding layer <NUM> and the bonding contacts in bonding layer <NUM> are aligned and in contact with one another, such that memory stack <NUM> and channel structures <NUM> formed therethrough can be electrically connected to peripheral circuits <NUM> and are above peripheral circuits <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which the second substrate is thinned to expose the second semiconductor layer. The thinning is performed from the second side (e.g., the backside) opposite to the first side of the second substrate. As illustrated in <FIG>, silicon substrate <NUM> (shown in <FIG>) is thinned from the backside to expose N-type doped semiconductor layer <NUM>. Silicon substrate <NUM> can be thinned using CMP, grinding, dry etching, and/or wet etching. In some embodiments, the CMP process is performed to thin silicon substrate <NUM> until reaching the top surface of N-type doped semiconductor layer <NUM>.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a source contact is formed above the memory stack and in contact with the second semiconductor layer. According to the invention, the source contact is formed at the second side (e.g., the backside) opposite to the first side of the second substrate (e.g., the second semiconductor layer after thinning). In some embodiments, the source contact is aligned with the insulating structure.

As illustrated in <FIG>, one or more ILD layers <NUM> are formed on N-type doped semiconductor layer <NUM>. ILD layers <NUM> can be formed by depositing dielectric materials on the top surface of N-type doped semiconductor layer <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. As illustrated in <FIG>, a source contact opening <NUM> is formed through ILD layers <NUM> into N-type doped semiconductor layer <NUM>. In some embodiments, source contact opening <NUM> is formed using wet etching and/or dry etching, such as RIE. In some embodiments, source contact opening <NUM> extends further into the top portion of N-type doped semiconductor layer <NUM>. The etching process through ILD layers <NUM> may continue to etch part of N-type doped semiconductor layer <NUM>. In some embodiments, a separate etching process is used to etch part of N-type doped semiconductor layer <NUM> after etching through ILD layers <NUM>. In some embodiments, source contact opening <NUM> is patterned using lithography to be aligned with insulating structure <NUM> at opposite sides of N-type doped semiconductor layer <NUM>.

As illustrated in <FIG>, a source contact <NUM> is formed in source contact opening <NUM> (shown in <FIG>) at the backside of N-type doped semiconductor layer <NUM>. Source contact <NUM> is above memory stack <NUM> and in contact with N-type doped semiconductor layer <NUM>, according to some embodiments. In some embodiments, one or more conductive materials are deposited into source contact opening <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill source contact opening <NUM> with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, then can be performed to remove the excess conductive materials, such that the top surface of source contact <NUM> is flush with the top surface of ILD layers <NUM>. In some embodiments, as source contact opening <NUM> is aligned with insulating structure <NUM>, backside source contact <NUM> is aligned with insulating structure <NUM> as well.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which an interconnect layer is formed above and in contact with the source contact. As illustrated in <FIG>, a redistribution layer <NUM> is formed above and in contact with source contact <NUM>. In some embodiments, redistribution layer <NUM> is formed by depositing a conductive material, such as Al, on the top surfaces of N-type doped semiconductor layer <NUM> and source contact <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. As illustrated in <FIG>, a passivation layer <NUM> is formed on redistribution layer <NUM>. In some embodiments, passivation layer <NUM> is formed by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. An interconnect layer <NUM> including ILD layers <NUM>, redistribution layer <NUM>, and passivation layer <NUM> is thereby formed, according to some embodiments.

Method <NUM> proceeds to operation <NUM>, as illustrated in <FIG>, in which a contact is formed through the second semiconductor layer and in contact with the interconnect layer, such that the first semiconductor layer is electrically connected to the contact through the second semiconductor layer, the source contact, and the interconnect layer. As illustrated in <FIG>, contact openings <NUM> and <NUM> each extending through ILD layers <NUM> and N-type doped semiconductor layer <NUM> are formed. Contact openings <NUM> and <NUM> and source contact opening <NUM> can be formed using the same etching process to reduce the number of etching processes. In some embodiments, contact openings <NUM> and <NUM> are formed using wet etching and/or dry etching, such as RIE, through ILD layers <NUM> and N-type doped semiconductor layer <NUM>. In some embodiments, contact openings <NUM> and <NUM> are patterned using lithography to be aligned with peripheral contacts <NUM> and <NUM>, respectively. The etching of contact openings <NUM> and <NUM> can stop at the upper ends of peripheral contacts <NUM> and <NUM> to expose peripheral contacts <NUM> and <NUM>. As illustrated in <FIG>, a spacer <NUM> is formed along the sidewalls of contact openings <NUM> and <NUM> to electrically isolate N-type doped semiconductor layer <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated in <FIG>, contacts <NUM> and <NUM> are formed in contact openings <NUM> and <NUM>, respectively (shown in <FIG>) at the backside of N-type doped semiconductor layer <NUM>. Contacts <NUM> and <NUM> extend vertically through ILD layers <NUM> and N-type doped semiconductor layer <NUM>, according to some embodiments. Contacts <NUM> and <NUM> and source contact <NUM> can be formed using the same deposition process to reduce the number of deposition processes. In some embodiments, one or more conductive materials are deposited into contact openings <NUM> and <NUM> using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill contact openings <NUM> and <NUM> with an adhesive layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, then can be performed to remove the excess conductive materials, such that the top surfaces of contacts <NUM> and <NUM> are flush with the top surface of ILD layers <NUM>. In some embodiments, as contact openings <NUM> and <NUM> are aligned with peripheral contacts <NUM> and <NUM>, respectively, contacts <NUM> and <NUM> are above and in contact with peripheral contacts <NUM> and <NUM>, respectively, as well.

As illustrated in <FIG>, redistribution layer <NUM> is also formed above and in contact with contact <NUM>. As a result, N-type doped semiconductor layer <NUM> can be electrically connected to peripheral contact <NUM> through N-type doped semiconductor layer <NUM>, source contact <NUM>, redistribution layer <NUM> of interconnect layer <NUM>, and contact <NUM>. In some embodiments, N-type doped semiconductor layers <NUM> and <NUM> are electrically connected to peripheral circuits <NUM> through source contact <NUM>, interconnect layer <NUM>, contact <NUM>, peripheral contact <NUM> and bonding layers <NUM> and <NUM>.

As illustrated in <FIG>, a contact pad <NUM> is formed above and in contact with contact <NUM>. In some embodiments, part of passivation layer <NUM> covering contact <NUM> is removed by wet etching and dry etching to expose part of redistribution layer <NUM> underneath to form contact pad <NUM>. As a result, contact pad <NUM> for pad-out can be electrically connected to peripheral circuits <NUM> through contact <NUM>, peripheral contact <NUM>, and bonding layers <NUM> and <NUM>.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Claim 1:
A method for forming a three-dimensional, 3D, memory device (<NUM>, <NUM>), comprising:
subsequently forming a sacrificial layer (<NUM>) above a second N-type doped semiconductor layer (<NUM>, <NUM>) at a first side of a substrate (<NUM>, <NUM>) and a dielectric stack (<NUM>), which includes interleaved stack sacrificial layers and stack dielectric layers (<NUM>), on the sacrificial layer (<NUM>);
forming a channel structure (<NUM>) extending vertically through the dielectric stack (<NUM>) and the sacrificial layer (<NUM>) into the second semiconductor layer (<NUM>, <NUM>);
replacing the sacrificial layer (<NUM>) with a first N-doped semiconductor layer (<NUM>, <NUM>) in contact with the second semiconductor layer (<NUM>, <NUM>);
replacing the dielectric stack (<NUM>) with a memory stack (<NUM>, <NUM>) including a plurality of interleaved conductive layers (<NUM>) and the stack dielectric layers (<NUM>), such that the channel structure (<NUM>) extends vertically through the memory stack (<NUM>, <NUM>) and the first semiconductor layer (<NUM>, <NUM>) into the second semiconductor layer (<NUM>, <NUM>), the method characterised in that it further comprises:
forming a source contact (<NUM>) at a second side opposite to the first side of the substrate (<NUM>, <NUM>) to be in contact with the second semiconductor layer (<NUM>, <NUM>),
wherein the substrate (<NUM>, <NUM>) is thinned from the second side to expose second N-type doped semiconductor layer (<NUM>, <NUM>),
wherein at least two ILD layers (<NUM>) are formed on second N-type doped semiconductor layer (<NUM>, <NUM>),
wherein a source contact opening (<NUM>) is formed through the at least two ILD layers (<NUM>) into N-type doped semiconductor layer (<NUM>, <NUM>),
wherein the source contact (<NUM>) is formed in source contact opening (<NUM>) at the second side of second N-type doped semiconductor layer (<NUM>, <NUM>), wherein the first semiconductor layer (<NUM>) surrounds part of channel structure (<NUM>) and is in contact with a semiconductor channel (<NUM>) of the channel structure (<NUM>), wherein a peripheral circuit (<NUM>) is formed on a further substrate (<NUM>),
wherein the substrate (<NUM>, <NUM>) and the further substrate (<NUM>) are bonded, such that the memory stack (<NUM>, <NUM>) is between the substrate (<NUM>, <NUM>) and the further substrate (<NUM>).