Patent Description:
In a wireless communication system, a receiver (e.g., a user equipment (UE)) may obtain information in a time de-interleaver (TDI) block by using a double data rate (DDR) reading/writing (R/W) with the TDI. However, when using the TDI R/W, the TDI repeatedly reads information. The receiver unnecessarily consumes in a large amount of resources. Thus, how to reduce the resource consumption is an important problem to be solved.

<CIT> discloses the systems and the methods for performing high-speed multi-channel forward error correction using external DDR synchronous dynamic random access memory (DDR SDRAM). An interleaver/deinterleaver performs both reading and writing accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations.

However, the reference does not disclose the problem to be solved in the present invention.

The present invention therefore provides a communication device for handling a time de-interleaver (TDI) block to solve the abovementioned problem.

This is achieved by a TDI for handling a TDI block according to the independent claims here below. The dependent claims pertain to corresponding further developments and improvements.

<FIG> is a schematic diagram of a communication system <NUM> according to an example of the present invention. The communication system <NUM> may be any communication system using an orthogonal frequency-division multiplexing (OFDM) technique (or termed as discrete multi-tone modulation (DMT) technique), and is briefly composed of a transmitter TX and a receiver RX. In <FIG>, the transmitter TX and the receiver RX are simply utilized for illustrating the structure of the communication system <NUM>. For example, the communication system <NUM> may be any wired communication system such as an asymmetric digital subscriber line (ADSL) system, a power line communication (PLC) system or an Ethernet over coax (EOC), or may be any wireless communication system such as a wireless local area network (WLAN), a Digital Video Broadcasting (DVB) system, a Long Term Evolution (LTE) system, a Long Term Evolution-advanced (LTE-A) system or a fifth generation (<NUM>) system. In addition, the transmitter TX and the receiver RX may be installed in a mobile phone, a laptop, etc., but is not limited herein.

<FIG> is a schematic diagram of a time de-interleaver (TDI) <NUM> according to the present invention. The TDI <NUM> may be utilized in the receiver RX of <FIG>, for handling a TDI block transmitted by the transmitter TX. The TDI <NUM> includes at least one buffer <NUM>, a double data rate (DDR) storage device <NUM>, a buffer writing circuit <NUM>, a control circuit <NUM> and a DDR writing circuit <NUM>. In detail, the buffer writing circuit <NUM> is coupled to the at least one buffer <NUM>, and writes (e.g., stores) data cells in the TDI block to the at least one buffer <NUM>. The control circuit <NUM> is coupled to the buffer writing circuit <NUM>, and generates DDR addresses of the data cells according to TDI addresses of the data cells. The DDR writing circuit <NUM> is coupled to the control circuit <NUM> and the DDR storage device <NUM>, and writes (e.g., stores) the data cells in the at least one buffer <NUM> to the DDR storage device <NUM> according to DDR addresses.

<FIG> is a schematic diagram of a TDI block <NUM> and a DDR storage device <NUM> according to the present invention. The DDR storage device <NUM> may be utilized for realizing the DDR storage device <NUM> of <FIG>. The TDI block <NUM> has Nr rows and Nc columns. There are Nr × Nc data cells in the TDI block <NUM>, and each data cell has a cell number. In <FIG>, there are <NUM> data cells in the TDI block <NUM> with Nr=<NUM> and Nc=<NUM>, but is not limited herein.

In the prior art, the DDR writing circuit <NUM> writes the data cells in the TDI block <NUM> to the DDR storage device <NUM> sequentially. For example, the TDI <NUM> writes data cells in a first row of the TDI block <NUM> to the DDR storage device <NUM>, and then writes data cells in a second row of the TDI block <NUM> to the DDR storage device <NUM>, and so on. According to the prior art, writing data cells in a TDI block to a DDR storage device sequentially causes the resource consumption when reading the data cells in the DDR storage device. The detail may be mentioned later.

In the present invention, the buffer writing circuit <NUM> writes the data cells in the TDI block <NUM> to the at least one buffer <NUM> in a more efficient way. An example is illustrated according to <FIG> and <FIG> as follows. There are <NUM> buffers with buffer indices <NUM>-<NUM> in the TDI <NUM>. A data cell with a cell number <NUM> is written to a buffer with a buffer index <NUM> (i.e., <NUM> mod <NUM> = <NUM>). A data cell with a cell number <NUM> is written to a buffer with a buffer index <NUM> (i.e., <NUM> mod <NUM> = <NUM>). When the at least one buffer <NUM> (e.g., the <NUM> buffers) is full, the DDR writing circuit <NUM> writes the data cells in the at least one buffer <NUM> to the DDR storage device <NUM>.

The control circuit <NUM> generates the DDR addresses according to the TDI addresses. A TDI address (R, C) represents that a data cell is located in the R-th row and the C-th column of the TDI block <NUM>, wherein R and C are positive integers. The control circuit <NUM> generates the DDR addresses according to the following equation: <MAT> wherein Nc is the number of columns of the TDI block, (R, C) is one of the TDI addresses, Nb is the number of the at least one buffer <NUM>, and BUF is a parameter. BUF is related to a ratio of a capacity of a DDR reading/writing (R/W) and a size of a data cell. Thus, the DDR writing circuit <NUM> writes the data cells in the at least one buffer <NUM> to the DDR storage device <NUM> according to the DDR addresses.

The following example is used for illustrating how the TDI <NUM> handles the TDI block <NUM>. The TDI block <NUM> with Nr=<NUM> and Nc=<NUM> and the at least one buffer <NUM> with Nb=<NUM> are assumed. A size of a data cell is <NUM> bits, and the capacity of the DDR R/W is <NUM> bits. That is, BUF is <NUM>/<NUM>=<NUM>. First, the buffer writing circuit <NUM> writes the data cells to the at least one buffer <NUM>, which can be referred to the previous description and is not narrated herein. After the buffer writing circuit <NUM> writes the data cells to the at least one buffer <NUM> (e.g., the <NUM> buffers), the DDR addresses of the data cells can be obtained according to the equation (Eq. <NUM>). Setting Nb=<NUM>, Nc=<NUM> and BUF=<NUM>, the Equation (Eq. <NUM>) can be rewritten as follows: <MAT>.

Thus, the data cells are written from the at least one buffer <NUM> to the DDR storage device <NUM> according to (Eq. <NUM>). For example, a data cell with a TDI address (<NUM>, <NUM>) is written to the DDR storage device <NUM> with a DDR address <NUM>. A data cell with a TDI address (<NUM>, <NUM>) is written to the DDR storage device <NUM> with a DDR address <NUM>. The detail can be referred to the DDR storage device <NUM> in <FIG>.

Operations of the TDI <NUM> in the above examples can be summarized into a process <NUM> shown in <FIG>. The process <NUM> is utilized in the TDI <NUM>, and includes the following steps:.

The process <NUM> is used for illustrating the operations of the TDI <NUM>. Detailed description and variations of the process <NUM> can be referred to the previous description, and is not narrated herein.

<FIG> is a schematic diagram of a time de-interleaver (TDI) <NUM> according to the present invention. The TDI <NUM> may be utilized in the receiver RX of <FIG>, for handling data cells in a DDR storage device. The TDI <NUM> includes a DDR storage device <NUM>, a cache <NUM>, a DDR reading circuit <NUM> and a cache writing circuit <NUM>. In detail, the DDR reading circuit <NUM> is coupled to the DDR storage device <NUM>, and reads a first part of the data cells in the DDR storage device <NUM>. The cache writing circuit <NUM> is coupled to the DDR reading circuit <NUM> and the cache <NUM>, and writes (e.g., stores) the first part of the data cells in the DDR storage device <NUM> to the cache <NUM>. Thus, the receiver RX may obtain the first part of the data cells form the cache <NUM> instead of the DDR storage device <NUM>, and may process the first part of the data cells.

In one example, the DDR reading circuit <NUM> reads a second part of the data cells in the DDR storage device <NUM>, e.g., when the first part of the data cells in the cache <NUM> is not needed for the receiver RX. The cache writing circuit <NUM> writes (e.g., stores) the second part of the data cells in the DDR storage device <NUM> to the cache <NUM>. The receiver RX may obtain the second part of the data cells form the cache <NUM>, and may process the second part of the data cells.

In one example, the DDR reading circuit <NUM> reads the first part of the data cells in the DDR storage device <NUM> by using a DDR R/W. In one example, after the receiver RX obtains (or processes) the first part of the data cells (e.g., the first part of the data cells in the cache <NUM> is no longer needed for the receiver RX), the DDR reading circuit <NUM> reads the second part of the data cells in the DDR storage device <NUM> by using the DDR R/W. Similarly, after the receiver RX obtains (or processes) the second part of the data cells (e.g., the second part of the data cells in the cache <NUM> is no longer needed for the receiver RX), the DDR reading circuit <NUM> reads a third part of the data cells in the DDR storage device <NUM> by using the DDR R/W.

In one example, the first part of the data cells and the second part of the data cells are not overlapped in the DDR storage device <NUM>. Similarly, the second part of the data cells and the third part of the data cells are not overlapped in the DDR storage device <NUM>. In one example, a capacity of the cache <NUM> is not smaller than the capacity of the DDR R/W. That is, the minimum capacity of the cache <NUM> is equal to the capacity of the DDR R/W.

The following example is used for illustrating how the TDI <NUM> handles the data cells in the DDR storage device <NUM>. A data cell with a size of <NUM> bits and the DDR R/W with a capacity of <NUM> bits are assumed. That is, the TDI <NUM> reads <NUM> data cells at a time by using the DDR R/W. The minimum capacity of the cache <NUM> is <NUM> bits. First, the DDR reading circuit <NUM> reads <NUM> data cells of the data cells in the DDR storage device <NUM> (e.g., the DDR storage device <NUM> with DDR addresses <NUM>-<NUM>) by using the DDR R/W, and the cache writing circuit <NUM> writes the <NUM> data cells to the cache <NUM>. That is, the receiver RX may obtain the <NUM> data cells from the cache <NUM>, and may process the <NUM> data cells. After the receiver RX processes the <NUM> data cells, the DDR reading circuit <NUM> reads other <NUM> data cells of the data cells in the DDR storage device <NUM> (e.g., the DDR storage device <NUM> with DDR addresses <NUM>-<NUM>) by using the DDR R/W, and the cache writing circuit <NUM> writes the other <NUM> data cells to the cache <NUM>. Thus, the DDR reading circuit <NUM> needs to read <NUM> (i.e., <NUM>×<NUM>/<NUM>) times to read all the data cells in the DDR storage device <NUM>.

In the prior art, the DDR reading circuit <NUM> reads the data cells in the DDR storage device <NUM> according to an order of the cell numbers. For example, the DDR reading circuit <NUM> first reads a data cell with a cell number <NUM> (i.e., the data cell with a TDI address (<NUM>, <NUM>) in the TDI block <NUM>) by reading <NUM> data cells with TDI addresses (<NUM>, <NUM>), (<NUM>, <NUM>),. , (<NUM>, <NUM>). The data cell with the TDI address (<NUM>, <NUM>) is useful for the receiver RX, while the other <NUM> data cells are useless. That is, the receiver RX uses only one cell read by the DDR reading circuit <NUM>. Then, the DDR reading circuit <NUM> reads a data cell with a cell number <NUM> (i.e., the data cell with a TDI address (<NUM>, <NUM>) in the TDI block <NUM>) by reading <NUM> data cells with TDI addresses (<NUM>,<NUM>), (<NUM>, <NUM>),. , (<NUM>, <NUM>). Similarly, the data cell with the TDI address (<NUM>, <NUM>) is useful for the receiver RX, while the other <NUM> data cells are useless. Accordingly, in the prior art, the DDR reading circuit <NUM> needs to read <NUM> (i.e., <NUM>×<NUM>) times to read all the data cells in the DDR storage device <NUM>. According to the present invention, the resource consumption (e.g., the number of TDI reading) is reduced.

It should be noted that realizations of the TDI <NUM> (including the at least one buffer <NUM>, the DDR storage device <NUM>, the buffer writing circuit <NUM>, the control circuit <NUM> and the DDR writing circuit <NUM>) and the TDI <NUM> (including the DDR storage device <NUM>, the cache <NUM>, the DDR reading circuit <NUM> and the cache writing circuit <NUM>) are various. For example, the circuits mentioned above may be integrated into one or more circuits. In addition, the TDI <NUM> and the TDI <NUM> may be realized by hardware (e.g., circuit), software, firmware (known as a combination of a hardware device, computer instructions and data that reside as read-only software on the hardware device), an electronic system or a combination of the devices mentioned above, but is not limited herein.

Claim 1:
A time de-interleaver, TDI, (<NUM>) comprising:
at least one buffer (<NUM>);
a double data rate, DDR, storage device (<NUM>);
a buffer writing circuit (<NUM>), coupled to the at least one buffer (<NUM>), for writing a plurality of data cells in a TDI block to the at least one buffer (<NUM>) (<NUM>);
a control circuit (<NUM>), coupled to the buffer writing circuit (<NUM>), for generating a plurality of DDR addresses of the plurality of data cells according to a plurality of TDI addresses of the plurality of data cells according to the following equation: <MAT> wherein Nc is a number of columns of the TDI block, (R, C) is one of the plurality of TDI addresses, Nb is a number of the at least one buffer (<NUM>), and BUF is a parameter related to a ratio of a capacity of a DDR reading/writing (R/W) and a size of one of the plurality of data cells; and
a DDR writing circuit (<NUM>), coupled to the control circuit (<NUM>) and the DDR storage device (<NUM>), for writing the plurality of data cells in the at least one buffer (<NUM>) to the DDR storage device (<NUM>) according to the plurality of DDR addresses (<NUM>), when the at least one buffer (<NUM>) is full.