Patent Description:
The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various implementations of the disclosure.

Aspects of the present disclosure are directed to using side-channel analysis (SCA) countermeasures in modular arithmetic computation used in cryptographic algorithms.

An integrated circuit that performs a cryptographic operation may be susceptible to SCA attack where an unauthorized entity may obtain secret information (e.g., cryptographic keys) as the cryptographic operation is performed. An example of a side-channel attack includes, but is not limited to, Differential Power Analysis (DPA) where the attacker who seeks to obtain a secret key used in the cryptographic operation may study the differences in power profile (i.e., power consumption patterns) of the integrated circuit as the cryptographic operation is performed. An attacker, i.e., an unauthorized entity, may obtain the input (e.g., the secret key) to the cryptographic operation by analyzing power profile measurements of the integrated circuit over a period of time. Accordingly, when the sender transmits a ciphertext to a receiver by encrypting plaintext via a cryptographic operation, the attacker may be able to retrieve the secret key that is used to encrypt the plaintext to the ciphertext by observing the power profile of the integrated circuit as the cryptographic operation is performed to encrypt the plaintext into the ciphertext.

In public-key cryptography systems, a processing device may have various components/modules used for cryptographic operations on an input message 'm'. Examples of such cryptographic operations include, but are not limited to, generating a digital signature 'S' to authenticate a message transmitted by a first node of the public-key cryptography system. A 'node' may encompass a certain hardware component within a computing device, such as a central processing unit (CPU), an integrated circuit (IC), an embedded circuit etc. or the like, that is able to send, receive, and/or forward information within a computer network. A digital signature can be generated using a modular exponentiation technique. For example, when a Rivest-Shamir-Adelman (RSA) algorithm is used as the basis of public-key cryptography (i.e., an input message `m' is encrypted with both a public key component and a private-key component), the signature 'S' is computed in the form of the equation, S =md mod n, where 'n' is a public modulus, and 'd' is a private exponent. A frequently used modular exponentiation technique, which involves fast modular multiplication, is referred to as Montgomery multiplication. Montgomery multiplication requires conversion of an input message into a form suitable for Montgomery multiplication, known as the Montgomery form. To generate a signature using Montgomery multiplication, input message `m' should be converted into Montgomery form. In general, to multiply two values 'a' and 'b' via Montgomery multiplication, 'a' and 'b' are first converted to Montgomery form, i.e. 'a' is converted to aR mod n and 'b' is converted to bR mod n, in order to produce a double-width product abR<NUM> mod n, which is then subjected to Montgomery reduction to produce abR mod n, which is the desired result of the Montgomery multiplication. That conversion (sometimes also referred to as a transformation), which is a pre-requisite of Montgomery multiplication, and the subsequent reduction that is also part of the Montgomery multiplication, require additional computational resources to be devoted in an integrated circuit. For example, additional on-chip storage may be required to store converted values during Montgomery multiplication.

Aspects of the present disclosure address the above problem by avoiding explicit conversion of the input message into Montgomery form. Instead, a first random value 'r' that is used to blind (i.e. mask) the input message `m' is used to generate an RSA signature.

The RSA signature takes the following form: S = (rem)d-<NUM>(re-<NUM>m) mod n, wherein 'e' is a public exponent, and 'd' is a private exponent. The random value 'r' has a bit length equal to or less than the public modulus 'n. ' The technique disclosed here avoids explicit use of a Montgomery form in Montgomery multiplication by incorporating modular reduction in side-channel-attack-resistant cryptographic computation, thereby reducing the number of functional calls. The implicit transformation of an input message into a Montgomery form in a public-key engine (PKE).

Advantages of the technique disclosed herein include efficiently using computational resources already available for message blinding to accomplish Montgomery multiplication without explicit conversion to Montgomery form. An additional advantage of the disclosed approach includes prevention of message value leakage inside any node of the public-key cryptography system as well as during communication between two nodes of the system.

<FIG> illustrates an example processing device <NUM> having a public key engine (PKE) and other components, in accordance with some aspects of the present disclosure. A PKE is a type of self-contained cryptographic module designed to be integrated into an integrated circuit configured to execute a cryptographic algorithm in a public-key cryptography system. In various embodiments, PKE can be implemented as an embedded hardware module, a purely software-based engine, or a combination of both hardware and software components. The processing device <NUM> may include internal memory (not shown) and various components/modules <NUM>-<NUM> used for cryptographic operations. Examples of such cryptographic operations include, but are not limited to, generating a digital signature to authenticate a message 'm'. Processing device <NUM> may be at a first node of a public key cryptography system.

As shown in <FIG>, the processing device <NUM> may include, among other things, an input message receiving component <NUM>, a random number generator component <NUM>, an input message blinding component <NUM>, a modular arithmetic unit <NUM>, a public key engine <NUM> and a blinded message transmission component <NUM>. In alternative embodiments, the functionality of one or more of the modules may be combined or divided. For example, the modular arithmetic unit <NUM> may be combined with one or both of input message blinding component <NUM> and public key engine <NUM>. Functionalities of at least some of the components <NUM>, <NUM> and <NUM> may be implemented by or in processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, integrated circuit, hardware of a device, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof.

The input message receiving component <NUM> may receive an input message `m' which is meant to be transmitted to another node within the public-key cryptography system. Random numbers generated by the random number generator component <NUM> may be added to the input message 'm' to mask or 'blind' the input message against possible SCA attack. Blinding may involve performing XOR operations on shares of the input message 'm', and transmitting the shares. The blinding operations may be carried out in input message blinding component <NUM>. The modular arithmetic unit <NUM> may compute a second random number 'h' based on the first random number 'r' and a factor 'R' used for Montgomery multiplication, wherein h = r R<NUM> mod n. The public key engine <NUM> performs a series of operations to ultimately produce the signature 'S' in the desired form: S = (rem)d-<NUM>(re-<NUM>m) mod n. The blinded message transmission component <NUM> transmits the signature 'S' containing the blinded message.

<FIG> illustrates a comparison between a conventional mechanism of generating a signature for a blinded input message in a public-key cryptography system and an improved mechanism of generating a signature for a blinded input message in a public-key cryptography system in accordance with aspects of the present disclosure. The conventional mechanism illustrated in diagram <NUM> uses an explicit conversion (transformation) into Montgomery form, where the improved mechanism illustrated by diagram <NUM> uses an implicit conversion (transformation) into Montgomery form. In the conventional mechanism, input message blinding is carried out at a block <NUM>, and transformation to Montgomery form is carried out in a separate and distinct block <NUM>, that receives the output of the block <NUM>. For example, an output of the block <NUM> may be the blinded message (m. r), which is an input to the block <NUM>. Input message `m' is transformed into Montgomery form in block <NUM>. Post-transformation, exponentiation (with private exponent `d') is carried out at block <NUM> to produce the signature. Once the signature is transmitted to a second node of the public-key cryptography system, a block <NUM> at a decoding device at the second node removes the blinding and the Montgomery form to decipher the underlying input message m.

In contrast to the conventional mechanism, the presently disclosed mechanism combines the functionalities of the blocks <NUM> and <NUM> into a single block <NUM>, as shown in diagram <NUM>. Instead of explicitly using conversion of the input message `m' into Montgomery form, block <NUM> can execute operations such as operations described in <FIG> to generate the signature 'S' in the desired form, i.e., S = (rem)d-<NUM>(re-<NUM>m) mod n, wherein `e' is a public exponent, and 'd' is a private exponent. An SCA-resistant software library (SL), for example, DPASL (Differential Power Analysis-resistant Software Library), stored within block <NUM>, may have codes containing the random value 'r'. A series of Montgomery multiplications, e.g., as described in <FIG>, take place in a PKE within block <NUM>. The functional blocks <NUM> and <NUM> of diagram <NUM> are functionally equivalent to their counterpart functional blocks <NUM> and <NUM> in the conventional mechanism shown as diagram <NUM>.

<FIG> is a flow diagram of an example method <NUM> to perform a SCA-resistant message transfer between a first node and a second node within a public-key cryptography system. The method <NUM> may be performed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method <NUM> may be performed by the components of processing device <NUM> shown in <FIG>.

Referring back to <FIG>, method <NUM> begins at block <NUM>, where an input message `m' is received at the processing device, for example at the input message receiving component <NUM> shown in <FIG>. The input message may be received in the form of a plurality of shares for further cryptographic operations.

At block <NUM>, a first random value is generated. The purpose of the first random value 'r' is to blind the input message `m' to prevent an SCA attack. The random value may be generated by the random number generator component <NUM>. In an embodiment, the random value may be stored within an internal memory (not shown in <FIG>) within the processing device <NUM>. The message blinding may be performed by the input message blinding component <NUM> shown in <FIG>.

At block <NUM>, a second random value 'h' is computed. This can be performed by the modular arithmetic unit <NUM> in <FIG>. The second random value can be computed using the first random value 'r' and a factor 'R' used to create a Montgomery form of the blinded input message without performing an explicit Montgomery conversion of the input message `m. ' <FIG> provides further details of this operation, in accordance with some embodiments.

At block <NUM>, a signature 'S' is computed by performing a plurality of Montgomery multiplications using the first random value 'r' and the second random value 'h'. A plurality of intermediate values are generated in order to ultimately derive the signature value 'S,' as described below in further detail with reference to <FIG>. These operations can take place within the public key engine <NUM>. Note that during the sequence of operations performed within the public key engine <NUM>, each of the intermediate values or any combination of intermediate values does not reveal the underlying secret message. Therefore, no direct-value leak is expected. Additionally, because the input message is blinded, and the blinding value (i.e., the first random number `r') keeps changing, the possibility of information leakage during communication between a first node and a second node of the public-key system is also minimized or prevented altogether.

<FIG> shows the intermediate operations used to ultimately generate the signature 'S', in accordance with some implementations of the present disclosure. These operations mostly take place in blocks <NUM> and <NUM> of the flow diagram <NUM>. As mentioned above, the second random value 'h' takes the form h = r R<NUM> mod n, where 'r' is a first random value used to blind the input message 'm'. Note that the factor R is expressed as R = <NUM>bx mod n, where 'b' is a bit length, and `x' is the number of words of bit length 'b' used to form 'n'. The next operation is computing a first intermediate value 'v' by multiplying 'h' with <NUM>, where v= r R mod n. Next, a second intermediate value 'k' is computed using Montgomery multiplication, where k = re-<NUM> R mod n, where `e' is a public exponent. Next, a third intermediate value `j' is computed using Montgomery multiplication, where j = re-<NUM> m mod n. Next, a fourth intermediate value 'p' is computed using Montgomery multiplication, where p = re m R mod n. Next, Montgomery multiplying the third intermediate value 'j' by the fourth intermediate value 'p' produces the signature 'S,' wherein S = pd-<NUM> j mod n, where 'd' is a private exponent. This form of S is equivalent to the desired form of signature 'S', i.e. S = (rem)d-<NUM>(re-<NUM>m) mod n.

Persons skilled in the art will understand that although the flow diagram in <FIG> shows a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

<FIG> illustrates an example machine of a computer system <NUM> within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine may operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system <NUM> includes a processing device <NUM>, a main memory <NUM> (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory <NUM> (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device <NUM>, which communicate with each other via a bus <NUM>. In one implementation, processing device <NUM> may be the processing device <NUM> in <FIG>.

Processing device <NUM> represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device <NUM> may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device <NUM> is configured to execute instructions <NUM> for performing the operations and steps discussed herein.

The computer system <NUM> may further include a network interface device <NUM> to communicate over the network <NUM>. The computer system <NUM> also may include a video display unit <NUM> (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device <NUM> (e.g., a keyboard), a cursor control device <NUM> (e.g., a mouse), a graphics processing unit <NUM>, a signal generation device <NUM> (e.g., a speaker), graphics processing unit <NUM>, video processing unit <NUM>, and audio processing unit <NUM>.

The data storage device <NUM> may include a machine-readable storage medium <NUM> (also known as a computer-readable medium) on which is stored one or more sets of instructions or software <NUM> embodying any one or more of the methodologies or functions described herein. The instructions <NUM> may also reside, completely or at least partially, within the main memory <NUM> and/or within the processing device <NUM> during execution thereof by the computer system <NUM>, the main memory <NUM> and the processing device <NUM> also constituting machine-readable storage media.

In one implementation, the instructions <NUM> include instructions to implement functionalities corresponding to operational blocks <NUM> and <NUM> shown in diagram <NUM>. While the machine-readable storage medium <NUM> is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media and magnetic media.

Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as "receiving" or "generating" or "executing" or "performing" or "computing" or "creating" or "transmitting" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc..

Claim 1:
A computer-implemented method (<NUM>) comprising:
receiving an input message 'm' (<NUM>) at a processor executing a signature algorithm;
generating, by the processor, a first random value 'r' that is used to blind the signature calculation to prevent a side-channel analysis (SCA) attack (<NUM>);
computing, by the processor, a second random value 'h', by multiplying modulo a public modulus 'n' the first random value and the square of a factor 'R' used to create a Montgomery form of the input message (<NUM>); and
computing, by the processor, a signature by
computing a first intermediate value 'v' by multiplying, using Montgomery multiplication, 'h' with <NUM>, where <MAT>
computing a second intermediate value 'k' by raising v to the power e-<NUM> using Montgomery multiplication, where k = re-<NUM> R mod n, where `e' is a public exponent;
computing a third intermediate value 'j' by multiplying k by m using Montgomery multiplication, where j = re-<NUM> m mod n; and
computing a fourth intermediate value 'p' by multiplying j by h using Montgomery multiplication, where p = re m R mod n ; and
Montgomery multiplying the third intermediate value 'j' by the fourth intermediate value 'p' raised to the power d-<NUM> using Montgomery multiplication to produce the signature 'S,' wherein S = pd-<NUM> j mod n, where 'd' is a private exponent.