Patent Description:
Current sensing resistors, also referred to as sense resistors, are typically discrete resistors soldered on to customer circuit boards. However, such resistors may not be well suited for meeting the performance goals of upcoming sensing resistor designs, such as low impedance. Thus, there is a desire to improve the performance of sensing resistors.

<CIT> describes a shunt strip that includes a plurality of shunts arranged in a grid with each of the shunts spaced from an adjacent shunt by a shunt-gap.

<CIT> describes an integrated circuit (IC) which includes a substrate with a resistor region and a resistor body disposed on the resistor region and a plurality of first resistor contact strips and a plurality of second resistor contact strips which are disposed on the resistor body along a first direction.

<CIT> describes an IC current measuring apparatus which electrically connects each of a plurality of IC-facing terminals and a different one of a plurality of substrate-facing terminals.

<CIT> describes an apparatus for measuring electrical current flow in a ball grid array (BGA) package.

<NPL>, describes a thin film multi-tap chip resistor.

<CIT> describes thin film resistors, both in integrated circuits and as discrete resistors.

The methods and devices of the described technology each have several aspects, no single one of which is solely responsible for its desirable attributes.

In one aspect, there is provided an integrated sense resistor, as defined in claim <NUM>.

In another aspect, there is provided a system-in-package (SiP), as defined in claim <NUM>.

In yet another aspect, there is provided an integrated sense resistor, as defined in claim <NUM>.

These drawings and the associated description herein are provided to illustrate specific embodiments of the invention and are not intended to be limiting.

Although particular aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different wired and wireless technologies, system configurations, networks, including optical networks, hard disks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims.

In this description, reference is made to the drawings where like reference numerals can indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

Current sensing resistors, also referred to as sense resistors, are typically discrete resistors soldered on to customer circuit boards. Some sense resistors are integrated with other integrated circuit components, and area footprint can be limited. As such, there is a need for the ability to manufacture very compact sense resistors at relatively low cost.

Some traditional integrated resistor architectures may not be well suited for meeting the performance goals of sense resistors, including low impedance. This may be due to the fact that integrated precision resistors typically use resistive films that have a high sheet resistance. In addition, metal interconnect can also have relatively high impedance. In addition, absolute resistance error, temperature drift and limited heat dissipation can also make integrating sense resistors very difficult.

To address these and other needs, an integrated sense resistor is disclosed herein.

<FIG> illustrates an example of a sense resistor integrated into a partially assembled module that includes a sense resistor in accordance with aspects of this disclosure. With reference to <FIG>, the module <NUM> includes a printed circuit board (PCB) <NUM>, a first integrated circuit <NUM>, a second integrated circuit <NUM>, a sense resistor <NUM>, and one or more discrete components <NUM>. In some embodiments, the sense resistor <NUM> can be embodied as a third integrated circuit. In addition, the one or more discrete components <NUM> can include passive components such as capacitors. Depending on the implementation, the printed circuit board <NUM> can be embodied as a laminate printed circuit board. <FIG> illustrates the module <NUM> of <FIG> including bumping <NUM> and encapsulated in a molding <NUM>. The module <NUM> can represent a system-in-package (SiP).

There are a number of considerations and/or attributes for designing modules that integrate sense resistors. One consideration is to reduce or minimize the resistance of the sense resistor to reduce the voltage drop for relatively high current signals. This can present a challenge with some existing technologies such as precision thin film resistors, which that can have relatively high sheet resistances.

Another consideration is to reduce or minimize parasitic resistances in order to reduce headroom loss. This can be challenging when the interconnect metal layers fabricated using integrated interconnect metallization processes are less than about <NUM> in thickness.

Yet another consideration is the precision of absolute resistance since an error in the measured current may be proportional to the error in resistance. The fabrication tolerances may be wider than the acceptable error margins for current sense, which may lead to an unacceptably large measurement error.

One desirable attribute for sense resistors is to provide stability with temperature since temperature drift can cause errors in measure current. Thin films may be relatively temperature stable, but further improvements in temperature stability are desirable.

Another desirable attribute is good power handling which enables higher measurement currents. When thin film resistors are formed in an oxide stack, the resulting thermal insulation may increase the temperature of the thin film resistors in operation. It can be desirable to reduce the amount of heating to enable the measurement of higher currents.

Another consideration is the size of the sense resistor since the space available on modules may be limited. The space occupied by a sense resistor may be related to the sense resistor's power handling capabilities, and thus, higher power handling capabilities are desirable to enable smaller sized sense resistors.

Still another consideration is the cost of manufacturing sense resistors, which can be compounded for modules that integrate a plurality of sense resistors. Since integrated circuit manufacturing is typically more complex than discrete manufacturing, cost can be an important factor in manufacturing sense resistors.

The integrated sense resistor comprises a plurality of first metal bumps alternating with a plurality of second metal bumps in at least a first lateral direction. The metal bumps can include any suitable solder metal bumps including lead-based and lead-free solder bumps, and can include metal elements such as lead (Pb), tin (Sn), silver (Ag), bismuth (Bi), antimony (Sb), indium (In), and cadmium (Cd). The sense resistor additionally comprises a plurality of thin film resistors each disposed between and electrically connected to a pair of adjacent ones of first and second metal bumps. The integrated sense resistor is configured for sensing a voltage developed by current flowing across the integrated sense resistor for determining a value of the current. For example, the resistance of the sense resistor (Rsense) may be predetermined, and by measuring a voltage on the sense lines resulting from an unknown current flowing therethrough, the unknown current can be calculated based the relationship I=(Vmeasured)/(Rsense).

In some embodiments, as fabricated, the first metal bumps are electrically disconnected from each other, and the second metal bumps are electrically disconnected from each other. In these embodiments, the integrated sense resistor may be formed over a board substrate, such that the first and second metal bumps are electrically connected to each other through the board substrate, and the second metal bumps are electrically connected to each other through the board substrate.

<FIG> and <FIG> show example configurations of the integrated resistor in accordance with aspects of this disclosure. In particular, <FIG> illustrates an integrated resistor having first and second metal bumps alternating in a vertical direction. <FIG> illustrates an integrated resistor having first and second metal bumps alternating in vertical and horizontal directions.

With reference to <FIG>, the integrated sense resistor <NUM> includes a plurality of first bumps <NUM> (also labeled "A"), a plurality of second bumps <NUM> (also labeled "B"), and a plurality of thin film resistors <NUM>. The first and second bumps <NUM> and <NUM> may also be referred to as first and second metal pads <NUM> and <NUM>. The first bumps <NUM> and the second bumps <NUM> are arranged in rows having a width of "X" and the thin film resistors <NUM> have a width of "Y". Since the thin film resistors are interposed between adjacent rows, each of the rows is separated by the distance "Y". Thus, the rows of first and second bumps <NUM> and <NUM> may extend in a first lateral direction and the rows may alternate in a second lateral direction orthogonal to the first lateral direction.

With reference to <FIG>, the integrated sense resistor <NUM> also includes a plurality of first bumps <NUM> (also labeled "A") and a plurality of second bumps <NUM> (also labeled "B"). In this embodiment, the first bumps <NUM> and the second bumps <NUM> are arranged in rows having a width of "X", where each of the rows is separated by a distance "Y". Unlike the integrated sense resistor <NUM> described with respect to <FIG>, in the embodiment illustrated in <FIG>, the first metal bumps <NUM> and the second metal bumps <NUM> alternate in each of the first and second lateral directions such that the first and second metal bumps <NUM> and <NUM> are arranged in a checkerboard or waffle pattern.

In some embodiments, the first and second metal bumps <NUM> and <NUM> form an array comprising rows extending in the first lateral direction and columns extending in the second lateral direction, where each of the rows and columns comprise the first metal bumps <NUM> alternating with the second metal bumps <NUM>.

In some embodiments, adjacent rows are interposed by a row of thin film resistors <NUM> aligned in the first lateral direction (e.g., horizontal in <FIG>), and adjacent columns are interposed by a column of thin film resistors <NUM> aligned in the second lateral direction (e.g., vertical in <FIG>).

As shown in <FIG> and <FIG>, each of the thin film resistors <NUM> has a rectangular footprint defined by a first lateral dimension, e.g., a length having the distance Y, and a second lateral dimension greater than the first lateral dimension, e.g., a width having the distance X, wherein the second lateral dimension corresponds to a length of the thin film resistor through which current flows. As arranged in at least the waffle design of <FIG>, the area footprint of the integrated sense resistor can be substantially reduced. For example, for illustrative purposes only, when the thin film resistors <NUM> of the integrated sense resistor <NUM> illustrated in <FIG> and the thin film resistors <NUM> of the integrated sense resistor <NUM> illustrated in <FIG> have the same width and length, and the integrated sense resistor <NUM> and the integrated sense resistor <NUM> have the same overall footprint, the integrated sense resistor <NUM> integrates <NUM> thin film resistors <NUM>, whereas the integrated sense resistor <NUM> integrates <NUM> thin film resistors <NUM>. Thus, the waffle design illustrated in <FIG>, having in which the first and second metal bumps <NUM>, <NUM> alternate in both lateral directions, can provide further footprint reduction or higher resistor density per unit area, relative to the design illustrated in <FIG>, in which the first and second metal bumps <NUM>, <NUM> alternate in one but not the other of the lateral directions.

In some embodiments, the array of the first and second metal bumps <NUM> and <NUM> comprises the same number of thin film resistors <NUM> in which current flows from left to right in the first lateral direction relative to thin film resistors <NUM> in which current flows from right to left in the first lateral direction. In addition, the array of the first and second metal bumps <NUM> and <NUM> comprises the same number of thin film resistors <NUM> in which current flows from top to bottom in the second lateral direction relative to thin film resistors <NUM> in which current flows from bottom to top in the second lateral direction. Due to this arrangement, the Seebeck effect that may be generated by temperature gradient across the integrated sense resistor may be substantially cancelled out.

<FIG> and <FIG> illustrate example vertical metal levels in accordance with aspects of this disclosure. In particular, <FIG> illustrates a first vertical metal level <NUM> (also referred to as a first board substrate) comprising openings <NUM> configured to allow the first metal bumps <NUM> to pass through the first vertical metal level <NUM> and areas <NUM> (e.g., pads) configured to electrically connect to the second metal bumps <NUM>. <FIG> illustrates a second vertical metal level <NUM> (also referred to as a second board substrate) comprising areas <NUM> (e.g., pads) configured to electrically connect to the first metal bumps <NUM>.

In some embodiments, the first metal bumps <NUM> are electrically connected to each other at the second vertical metal level <NUM> and the second metal bumps are electrically connected to each other at the first vertical metal level <NUM> different from the second vertical metal level <NUM>. In some implementations, the vertical metal levels <NUM> and <NUM> can be embodied as laminate layers receiving metal layers and/or metal sheets.

<FIG> and <FIG> illustrate an embodiment of a thin film resistor in accordance with aspects of this disclosure. In particular, <FIG> illustrates a cross section of the thin film resistor <NUM> in operation, in accordance with aspects of this disclosure. <FIG> illustrates a top down view of the thin film resistor <NUM> in accordance with aspects of this disclosure.

With reference to <FIG> and <FIG>, the thin film resistor <NUM> comprises a first layer <NUM>, a second layer <NUM>, a plurality of vias <NUM>, and a plurality of metal interconnects (also referred to as sense lines) including an ASense interconnect <NUM>, an AForce interconnect <NUM>, a BSense interconnect <NUM>, and a BForce interconnect <NUM>. In some embodiments, the first layer <NUM> is formed of silicon chromium (SiCr) and the second layer <NUM> is formed of tungsten-titanium (TiW).

The thin film resistor <NUM> can also include two different regions including a first region <NUM> having positive coefficient of resistance (TCR) and a second region <NUM> having a negative TCR that are arranged, e.g., serially, such that a net TCR has a smaller magnitude than a magnitude of the TCR of each of the first and second regions <NUM> and <NUM>. In some embodiments, the overall TCR of the first and second regions <NUM> and <NUM> together may be substantially zero. For example, without limitation, the first region <NUM> can be formed of a thin film of TiW having a positive TCR, and the second region <NUM> can be formed of a thin film of SiCr having a negative TCR, such that the overall TCR is substantially reduced in magnitude relative to the TCRs of each of the first and second regions <NUM>, <NUM>. The sense lines <NUM>-<NUM> can be electrically coupled to the thin film resistor <NUM> at the resistor level (e.g., at the level of the first and second layers <NUM> and <NUM> by the vias <NUM>. In addition, the sense lines <NUM>-<NUM> and vias <NUM> can be formed outside of a sensing loop defined by the first and second regions <NUM> and <NUM>. In one example, current <NUM> can flow through the thin film resistor from the AForce interconnect <NUM>, through the first and second regions <NUM> and <NUM> and out of the BForce interconnect <NUM>.

<FIG> illustrates another embodiment of a thin film resistor <NUM> constructed for a waffle design sense resistor <NUM> (<FIG>) in accordance with aspects of this disclosure. In particular, the thin film resistor <NUM> of <FIG> may have substantially the same elements as the thin film resistor <NUM> of <FIG> with a layout that is configurable in a "waffle" design sense resistor, such as the sense resistor <NUM> of <FIG>.

<FIG> and <FIG> illustrate view of the thin film resistor <NUM> at stages of integration into a sense resistor <NUM> in accordance with aspects of this disclosure. Specifically, <FIG> illustrates the thin film resistor <NUM> arranged between a first bump <NUM> and a second bump <NUM> of an integrated sense resistor <NUM>. With reference to <FIG> and <FIG>, the first bump <NUM> can be connected to the ASense interconnect <NUM> and the second bump <NUM> can be connected to the BSense interconnect <NUM>. <FIG> illustrates the location of a thin film resistor <NUM> within an example layout of an integrated sense resistor <NUM>.

In various embodiments, the thin film resistors <NUM> are lithographically patterned on a semiconductor substrate.

In some embodiments, the integrated sense resistor is formed over a board substrate comprising a laminated polymeric substrate, e.g., a laminated PCB, and the substrate has formed thereon additional discrete integrated circuit components. One embodiment of such a PCB is the PCB <NUM> of <FIG>.

The system-in-package (SiP) comprises a board substrate and an integrated sense resistor <NUM>. The integrated sense resistor <NUM> comprises a plurality of first metal pads or bumps <NUM> alternating with a plurality of second metal pads or bumps <NUM> in at least a first lateral direction, and a plurality of thin film resistors <NUM> each disposed between and electrically connected to a pair of adjacent ones of first and second metal pads or bumps <NUM> and <NUM>. The first metal pads or bumps <NUM> are electrically connected to each other through the board substrate, and wherein the second metal contact pads or bumps <NUM> are electrically connected to each other through the board substrate,.

The integrated sense resistor <NUM> comprises a plurality of first metal pads <NUM> alternating with a plurality of second metal pads <NUM> in at least a first lateral direction. The integrated sense resistor <NUM> additionally comprises a plurality of thin film resistors <NUM> each disposed between and electrically connected to a pair of adjacent ones of first and second metal pads <NUM> and <NUM>. As fabricated, the first metal pads <NUM> are electrically disconnected from each other, and the second metal pads <NUM> are electrically disconnected from each other.

As disclosed herein, the disclosed sense resistor is made area-efficient by using a "waffle" design, which can enable packing ><NUM>% more resistor width in a given die area, compared to standard striped resistors. The disclosed sense resistors leverages benefit from low resistance thick copper traces on a laminate substrate, where the thick copper traces become part of the resistor design and thus significantly reduces parasitic resistances. In addition, the integrated sense resistor can be configured to at least partially cancel out thermoelectric effects. Thu, even if there are temperature gradients across the sense resistor die, the voltages generated by the Seebeck effect can substantially be cancelled out by a corresponding Seebeck effect voltage in the opposite direction. With a combination of waffle design and the use of distributed bumps/pillars across the integrated sense resistor, heat dissipation can be optimized. Finally, sense off the back of the resistor using the resistor materials themselves can allow for a relatively straight forward method of canceling out both negative and positive TCRs so that the overall TCR can be maintained close to near zero ppm/' C.

In the foregoing, it will be appreciated that any feature of any one of the embodiments can be combined or substituted with any other feature of any other one of the embodiments.

Aspects of this disclosure can be implemented in various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, cellular communications infrastructure such as a base station, etc. Examples of the electronic devices can include, but are not limited to, a mobile phone such as a smart phone, a wearable computing device such as a smart watch or an ear piece, a telephone, a television, a computer monitor, a computer, a modem, a hand-held computer, a laptop computer, a tablet computer, a personal digital assistant (PDA), a microwave, a refrigerator, a vehicular electronics system such as an automotive electronics system, a stereo system, a DVD player, a CD player, a digital music player such as an MP3 player, a radio, a camcorder, a camera such as a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, peripheral device, a clock, etc. Further, the electronic devices can include unfinished products.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," "include," "including" and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to. " The word "coupled", as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word "connected", as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number, respectively. The word "or" in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

Moreover, conditional language used herein, such as, among others, "can," "could," "might," "may," "e.g.," "for example," "such as" and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or whether these features, elements and/or states are included or are to be performed in any particular embodiment.

Claim 1:
An integrated sense resistor (<NUM>) configured for sensing a voltage developed by current flowing across the integrated sense resistor for determining a value of the current, characterised by:
a plurality of first metal bumps (<NUM>) alternating with a plurality of second metal bumps (<NUM>) in a first lateral direction and wherein the first metal bumps (<NUM>) and the second metal bumps (<NUM>) further alternate in a second direction crossing the first lateral direction, wherein the second lateral direction is orthogonal to the first lateral direction such that the first (<NUM>) and second metal bumps (<NUM>) are arranged in a checkerboard pattern; and
a plurality of thin film resistors (<NUM>) each disposed between and electrically connected to a pair of adjacent ones of first and second metal bumps.