Patent Description:
In conventional three-dimensional (3D) stacked integrated circuit (IC) packaging, semiconductor devices are stacked and interconnected to each other vertically, enabling a smaller IC package size and facilitating increased electrical performance (e.g., increased bandwidth, reduced power consumption, etc.). At least some known 3D stacked IC devices include a memory device-or a memory stack-that is placed on top of a logic device due to the increased number of interconnects of the logic device that need to connect to external circuitry. Typically, logic devices, however, have increased power dissipation, and therefore, increased operating temperatures, in comparison to the memory devices. Thus, with at least some 3D stacked IC devices it is not a thermally advantageous arrangement to position the logic device between the memory device and a substrate of the 3D stacked IC devices.

In addition, at least some known 3D stacked IC devices include through silicon vias (TSVs) formed in the logic device to facilitate electrically connecting the memory device to the external circuitry, which adds complexity and cost to the manufacturing of the logic device. In at least some known 3D stacked IC devices, the number of interconnects between the logic device and the memory and external circuitry would require an increase in the number of TSVs in the memory device, thereby reducing the efficient use and cost effectiveness of the memory device real estate.

United States Patent Application Publication No. <CIT> discloses a packaged semiconductor device. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

United States Patent Application Publication No. <CIT> describes a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads formed on the active surface thereof and a groove formed between adjacent solder pads to form a first metal layer therein that is electrically connected to the solder pads; subsequently thinning the non-active surface of the wafer to where the grooves are located to expose the first metal layer therefrom, and forming a second metal layer on the non-active surface of the wafer for electrically connecting with the first metal layer; and separating the dies to form a plurality of stackable semiconductor devices.

United States Patent Application Publication No. <CIT> discloses a 3D semiconductor package using an interposer. An interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.

United States Patent Application Publication No. <CIT> discloses an IC stack with a connection component connected to a substrate, the connection component being free of through silicon vias, but is silent on the connection component comprising active or passive electrical components. The connection component is an extension block.

According to a first aspect the invention provides an integrated circuit (IC) device in accordance with claim <NUM>. According to a second aspect the invention provides a method of forming an IC device having a 3D package structure in accordance with claim <NUM>. Further aspects of the invention are set forth in the dependent claims, the drawings and the following description of embodiments.

Here and throughout the specification and claims, range limitations may be combined and/or interchanged; such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise.

The devices and methods described herein facilitate increasing the efficiency of an integrated circuit device by configuring a connection component to surround a memory die connected to and positioned between a logic die and a package substrate. The logic die and the memory die are coupled to each other and communicate directly via solder micro-bumps. The logic die is electrically coupled to the package substrate via the connection component positioned about the memory die via solder micro-bumps. The memory die is provided with through silicon vias (TSVs) to enable communication between the logic die and the package substrate. In addition, the memory die is coupled directly to the substrate package via solder micro-bumps. As such, the embodiments described herein provide for increasing the thermal dissipation, or efficiency, of the logic die by positioning the logic die (the higher power dissipation component) above the memory die (the lower power dissipation component) away from the package substrate. This facilitates increased thermal management and increased performance of the logic die. In addition, the embodiments described reduce the need for providing TSVs in the logic die to enable connections of the memory die directly to the package substrate. This facilitates decreasing the manufacturing cost of the logic die by reducing the size and complexity of the logic die.

<FIG> is a schematic front view of a prior art integrated circuit (IC) device <NUM> formed in a single three-dimensional (3D) package structure. A typical 3D package structure includes at least one die being mounted on the top of another die, with the lower die having TSVs to allow the upper die to communicate with the lower die and the package substrate. For example, as shown in <FIG>, IC device <NUM> is fabricated as a single 3D package including a logic die <NUM> and at least one memory die <NUM>. Logic die <NUM> and memory die <NUM> are coupled directly to each other via solder micro-bumps <NUM> and are vertically integrated, i.e., memory die <NUM> is positioned on top of logic die <NUM> substantially covering logic die <NUM>. Logic die <NUM> is coupled to a package substrate <NUM> via a plurality of solder micro-bumps <NUM>. Logic die <NUM> includes a plurality of TSVs <NUM> that enable at least some connections of memory die <NUM> to couple to package substrate <NUM> via solder micro-bumps <NUM>. While the lengths of TSVs <NUM> are reduced compared to wire bonds typically found in package-on-package structures, as described herein, the TSVs <NUM> add size and complexity to the logic die <NUM>. This results in an increased manufacturing cost associated with logic die <NUM>. In addition, the thermal efficiency of IC device <NUM> is reduced because heat generated by logic die <NUM> is transferred to memory die <NUM>. Moreover, heat cannot be readily removed directly from logic die <NUM>.

<FIG> is a schematic front view of a prior art IC device <NUM> formed in a single <NUM>-dimensional (<NUM>. 5D) package structure. A typical <NUM>. 5D package structure includes at least one die being mounted next to another die in a single plane, with an interposer placed between the package substrate and the two dies, where the interposer has TSVs connecting metallization layers on its upper and lower surfaces. For example, as shown in <FIG>, IC device <NUM> is fabricated as a single <NUM>. 5D package including a logic die <NUM>, at least one memory die <NUM>, and an interposer <NUM>. Logic die <NUM> and memory die <NUM> are coupled directly to interposer <NUM> via solder micro-bumps <NUM> and <NUM>, respectively, in a side-by-side arrangement. Interposer <NUM> includes electrical circuitry (not shown) that enables direct communication between logic die <NUM> and memory die <NUM>. Interposer <NUM> is typically fabricated from silicon, although other materials such as glass, ceramic, and/or organic materials are also used. Interposer <NUM> includes a plurality of TSVs <NUM> that enable at least some connections of logic die <NUM> and memory die <NUM> to couple to a package substrate <NUM> via solder micro-bumps <NUM>. The side-by-side <NUM>. 5D package structure, however, results in an increased size of IC device <NUM>. In addition, the length of the connection paths between logic die <NUM> and memory die <NUM> are increased compared to the 3D package structure shown in <FIG>, which results in additional inefficiencies of IC device <NUM>. In addition, interposer <NUM> includes TSVs <NUM> and connection circuitry for logic die <NUM> and memory die <NUM>, which results in an increased manufacturing cost associated with IC device <NUM>.

<FIG> is a sectional view of an exemplary IC device <NUM> formed in a single 3D package structure. <FIG> is a schematic plan view of IC device <NUM> shown in <FIG>. With reference to <FIG> and <FIG>, IC device <NUM> is fabricated as a single 3D package and includes a package substrate <NUM>, an interposer component or connection component <NUM>, at least one logic die <NUM>, and at least one memory die <NUM>. Connection component <NUM> is coupled to package substrate <NUM> via a plurality of solder micro-bumps <NUM>. The at least one logic die <NUM> is positioned on connection component <NUM>, opposite package substrate <NUM>. Logic die <NUM> is coupled directly to connection component <NUM> via a plurality of solder micro-bumps <NUM>. In some embodiments, logic die <NUM> is a single chip, and in other embodiments, logic die <NUM> is a multi-chip (e.g., a side-by-side chip arrangement) package. Logic die <NUM> includes, for example, and without limitation, a processor, processing device, or controller, such as a general purpose central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microcontroller, a reduced instruction set computer (RISC) processor, an application specific integrated circuit (ASIC), a programmable logic circuit (PLC), a programmable logic unit (PLU), a field programmable gate array (FPGA), gate arrays, a digital signal processing (DSP) device, and/or any other logic circuit or processing device that enables IC device <NUM> to function as described herein.

In the exemplary embodiment, connection component <NUM> is formed as a single component extending about a perimeter of logic die <NUM> and having a cavity <NUM> defined. Cavity <NUM> is formed therein via the removal of material from a generally central portion of connection component <NUM>. As shown in <FIG>, connection component <NUM> is generally rectangular-shaped and defines a generally rectangular-shaped cavity <NUM>. While connection component <NUM> is shown having a generally rectangular-shape, alternatively, connection component <NUM> has any shape that enables connection component <NUM> to function as described herein. In addition, cavity <NUM> may be formed in any location in connection component <NUM> and need not be generally centrally located, as long as the requirements of claims <NUM> and <NUM> are met.

Moreover, in the exemplary embodiment, connection component <NUM> is fabricated from silicon and includes one or more redistribution wiring layers <NUM>. Alternatively, connection component <NUM> is fabricated from any material that enables connection component <NUM> to function as described herein, for example, and without limitation, glass, ceramic, organic materials, germanium, gallium arsenide, indium phosphide, and silicon carbide. Redistribution wiring layer <NUM> facilitates electrical connection points or pins (not shown) of logic die <NUM>, for example locations corresponding to solder micro-bumps <NUM>, to be available to other locations on connection component <NUM>. Thus, redistribution wiring layer <NUM> facilitates routing the electrical connection points or pins of logic die <NUM> to favorable locations on connection component <NUM> to facilitate enabling bonding from different locations on logic die <NUM> to similar and/or adjacent locations on connection component <NUM>, thereby simplifying assembly of IC device <NUM>.

Furthermore, in an example not forming part of the claimed invention but useful for understanding, connection component <NUM> is a passive interposer. For example, and without limitation, in some examples not forming part of the claimed invention but useful for understanding, connection component <NUM> does not include additional electrical components, including only the one or more redistribution wiring layers <NUM>. In some embodiments, connection component <NUM> includes one or more integrated passive devices (IPDs) embedded and/or formed thereon, for example, and without limitation, resistors, capacitors, inductors, or any other passive electrical devices that enable connection component <NUM> to function as described herein. Thus, in the exemplary embodiment, connection component <NUM> does not include active electrical components, for example, and without limitation, transistors, signal amplifiers, signal filters, or any other active electrical components. Alternatively, in some embodiments, connection component <NUM> is an active interposer and includes one or more active electrical components embedded and/or formed thereon.

With reference to <FIG> and <FIG>, in the exemplary embodiment, memory die <NUM> represents a stacked or multiple chip arrangement. Alternatively, memory die <NUM> may be a single chip and/or an unstacked chip arrangement. In the exemplary embodiment, logic die <NUM> and memory die <NUM> are coupled directly to each other via solder micro-bumps <NUM> and are vertically integrated, i.e., memory die <NUM> is positioned vertically with respect to logic die <NUM>. In alternative embodiments, logic die <NUM> and memory die <NUM> are coupled directly to each other using any connection method that enables IC device <NUM> to function as described herein, for example, and without limitation, via diffusion bonding, eutectic bonding, thermal compression bonding, and the use of conductive polymers. In the exemplary embodiment, memory die <NUM> is positioned below logic die <NUM>. More specifically, memory die <NUM> is positioned vertically between logic die <NUM> and package substrate <NUM> such that logic die <NUM> overlies memory die <NUM>. Memory die <NUM> is positioned in cavity <NUM> of connection component <NUM>, and logic die <NUM> entirely overlaps memory die <NUM>. In alternative embodiments, logic die <NUM> only partially overlaps memory die <NUM>.

In the exemplary embodiment, as shown in <FIG>, an active surface <NUM> of memory die <NUM> is oriented toward an active surface <NUM> of logic die <NUM> and away from substrate <NUM>, i.e., logic die <NUM> and memory die <NUM> are oriented in a face-to-face arrangement. Memory die <NUM> includes a plurality of through silicon vias (TSVs) <NUM> formed therein to enable electrical connection directly to package substrate <NUM>. TSVs <NUM> are coupled directly to substrate <NUM> via a plurality of solder micro-bumps <NUM>. In alternative embodiments, TSVs <NUM> are coupled directly to substrate <NUM> using any connection method that enables IC device <NUM> to function as described herein, for example, and without limitation, via diffusion bonding, eutectic bonding, thermal compression bonding, and the use of conductive polymers. In some embodiments, TSVs <NUM> are formed in memory die <NUM> using any known manufacturing technique such as laser drilling, mechanical drilling, and/or etching processes. TSVs <NUM> and solder micro-bumps <NUM> enable at least one electrical connection of memory die <NUM> to connect to other circuitry (not shown) on substrate <NUM> without passing through logic die <NUM>. This facilitates increasing the efficiency of IC device <NUM> as well as reducing manufacturing costs associated with the fabrication of IC device <NUM>.

In alternative embodiments, memory die <NUM> can be oriented such that active surface <NUM> of memory die <NUM> is oriented away from active surface <NUM> of logic die <NUM> and toward substrate <NUM>. In such embodiments, TSVs <NUM> of memory die <NUM> facilitate electrical connection directly to logic die <NUM>. Also, in such embodiments, TSVs <NUM> are coupled directly to logic die <NUM> via solder micro-bumps, such as solder micro-bumps <NUM>. As such, TSVs <NUM> and solder micro-bumps <NUM> enable at least one electrical connection of memory die <NUM> to connect directly to logic die <NUM> without passing through substrate <NUM>. In alternative embodiments, logic die <NUM> and TSVs <NUM> are coupled directly to each other using any connection method that enables IC device <NUM> to function as described herein, for example, and without limitation, via diffusion bonding, eutectic bonding, thermal compression bonding, and the use of conductive polymers.

In the exemplary embodiment, as shown in <FIG> and <FIG> and described herein, logic die <NUM> is coupled directly to connection component <NUM> via a plurality of solder micro-bumps <NUM>. Connection component <NUM> includes one or more wire bonding pads <NUM> formed on redistribution wiring layer <NUM>. Bonding pads <NUM> are electrically connected to at least one solder micro-bump <NUM> via an electrical circuit (not shown) formed on redistribution wiring layer <NUM> and/or internal circuitry <NUM> formed within one or more build-up layers (not shown) of connection component <NUM>. Thus an electrical signal (not shown) is transmitted from logic die <NUM> to one or more wire bonding pads <NUM>. Moreover, substrate <NUM> includes one or more wire bonding pads <NUM>, which connect to other circuitry (not shown) via an electrical circuit and/or internal circuitry (not shown) formed on/in an active surface <NUM> of substrate <NUM>. It is noted that, as opposed to at least some known interposers, connection component <NUM> is free of through silicon vias, thereby facilitating decreasing a complexity and manufacturing cost of fabricating connection component <NUM>.

In the exemplary embodiment, connection component bonding pads <NUM> and substrate bonding pads <NUM> are electrically coupled together through wires <NUM>. This facilitates connecting logic die <NUM> directly to substrate <NUM>. Wires <NUM> are fabricated from, for example, and without limitation, gold, aluminum, copper, and alloys thereof. Coupling logic die <NUM> to substrate <NUM> via wires <NUM> facilitates a cost effective and flexible technique for coupling IC device <NUM> to other electrical devices and/or circuits (not shown).

<FIG> is a schematic plan view of an IC device <NUM> formed in a single 3D package structure. With reference to <FIG> and <FIG>, in the exemplary embodiment, IC device <NUM> is fabricated substantially similar to IC device <NUM>, as described herein. IC device <NUM> includes package substrate <NUM>, at least one logic die <NUM>, and at least one memory die <NUM>. However, as opposed to the unitary connection component <NUM> described herein with respect to IC device <NUM>, IC device <NUM> includes one or more connection components, for example connection components <NUM>, <NUM>, <NUM>, and <NUM>, as shown in <FIG>. Connection components <NUM>, <NUM>, <NUM>, and <NUM> are coupled to package substrate <NUM> via a plurality of solder micro-bumps <NUM>. Logic die <NUM> is positioned on and coupled to connection components <NUM>, <NUM>, <NUM>, and <NUM> opposite package substrate <NUM>. Logic die <NUM> is coupled directly to connection components <NUM>, <NUM>, <NUM>, and <NUM> via a plurality of solder micro-bumps <NUM>. In some embodiments, logic die <NUM> is a single chip, and in other embodiments, logic die <NUM> is a multi-chip (e.g., a side-by-side chip arrangement) package. As described herein, logic die <NUM> includes, for example, and without limitation, a processor, processing device, or controller, such as a general purpose central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microcontroller, a reduced instruction set computer (RISC) processor, an application specific integrated circuit (ASIC), a programmable logic circuit (PLC), a programmable logic unit (PLU), a field programmable gate array (FPGA), gate arrays, a digital signal processing (DSP) device, and/or any other logic circuit or processing device that enables IC device <NUM> to function as described herein.

In the exemplary embodiment, connection components <NUM>, <NUM>, <NUM>, and <NUM> are discrete components positioned proximate a perimeter of logic die <NUM>, defining a cavity <NUM> therebetween for receiving memory die <NUM>. As shown in <FIG>, connection components <NUM>, <NUM>, <NUM>, and <NUM> are generally rectangular-shaped components positioned to define a generally rectangular-shaped cavity <NUM>. It is noted, however, that while connection components <NUM>, <NUM>, <NUM>, and <NUM> are shown having generally rectangular shapes, it is contemplated that connection components <NUM>, <NUM>, <NUM>, and <NUM> can have any shape that enables connection components <NUM>, <NUM>, <NUM>, and <NUM> to function as described herein.

In the exemplary embodiment, each of connection components <NUM>, <NUM>, <NUM>, and <NUM> are only partially overlain by logic device <NUM>. In such an embodiment, one or more of connection components <NUM>, <NUM>, <NUM>, and <NUM> may be an active connection component. For example, in one embodiment, one or more of connection components <NUM>, <NUM>, <NUM>, and <NUM> include active electrical components embedded and/or formed thereon, for example, and without limitation, transistors, signal amplifiers, signal filters, and any other active electrical component that enables the one or more connection components <NUM>, <NUM>, <NUM>, and <NUM> to function as described herein. Such active electrical components are placed on portions of connection components <NUM>, <NUM>, <NUM>, and <NUM> that are not overlain by logic device <NUM>.

In an example not forming part of the claimed invention but useful for understanding, one or more of connection components <NUM>, <NUM>, <NUM>, and <NUM> is a passive interposer. For example, and without limitation, in some such examples not forming part of the claimed invention but useful for understanding, one or more of connection components <NUM>, <NUM>, <NUM>, and <NUM> do not include additional electrical components. In some embodiments, one or more of connection components <NUM>, <NUM>, <NUM>, and <NUM> include one or more integrated passive devices (IPDs) embedded and/or formed thereon, for example, and without limitation, resistors, capacitors, inductors, and any other passive electrical components that enable connection components <NUM>, <NUM>, <NUM>, and <NUM> to function as described herein.

Furthermore, in the exemplary embodiment, connection components <NUM>, <NUM>, <NUM>, and <NUM> are fabricated from silicon and include one or more redistribution wiring layers <NUM> (i.e., and active surface). Alternatively, connection components <NUM>, <NUM>, <NUM>, and <NUM> are fabricated from any material that enables connection components <NUM>, <NUM>, <NUM>, and <NUM> to function as described herein, for example, and without limitation, glass, ceramic, organic materials, germanium, gallium arsenide, indium phosphide, and silicon carbide. Redistribution wiring layer <NUM> facilitates electrical connection points or pins (not shown) of logic die <NUM>, for example locations corresponding to solder micro-bumps <NUM>, to be available to other locations on connection components <NUM>, <NUM>, <NUM>, and <NUM>. Thus, redistribution wiring layer <NUM> facilitates routing the electrical connection points or pins of logic die <NUM> to favorable locations on connection components <NUM>, <NUM>, <NUM>, and <NUM> to facilitate enabling bonding from different locations on logic die <NUM> to similar and/or adjacent locations on connection components <NUM>, <NUM>, <NUM>, and <NUM>, thereby simplifying assembly of IC device <NUM>.

With reference to <FIG> and <FIG>, logic die <NUM> and memory die <NUM> are coupled directly to each other via solder micro-bumps <NUM> and are vertically integrated, i.e., memory die <NUM> is positioned vertically below logic die <NUM>. More specifically, memory die <NUM> is positioned vertically between logic die <NUM> and package substrate <NUM> such that logic die <NUM> overlies memory die <NUM>. In such an embodiment, memory die <NUM> is positioned in cavity <NUM> defined by connection components <NUM>, <NUM>, <NUM>, and <NUM>, and logic die <NUM> overlaps memory die <NUM> entirely. Alternatively, logic die <NUM> only partially overlaps memory die <NUM>.

In the exemplary embodiment, logic die <NUM> is coupled directly to connection components <NUM>, <NUM>, <NUM>, and <NUM> via a plurality of solder micro-bumps <NUM>. Connection components <NUM>, <NUM>, <NUM>, and <NUM> include one or more wire bonding pads <NUM> formed on a redistribution wiring layer <NUM>. Bonding pads <NUM> are electrically connected to at least one solder micro-bump <NUM> via an electrical circuit (not shown) formed on redistribution wiring layer <NUM> and/or internal circuitry <NUM> formed within one or more build-up layers (not shown) of connection components <NUM>, <NUM>, <NUM>, and <NUM>. Thus an electrical signal (not shown) is transmitted from logic die <NUM> to one or more wire bonding pads <NUM>. It is noted that, as opposed to at least some known interposers, connection components <NUM>, <NUM>, <NUM>, and <NUM> are free of through silicon vias, thereby facilitating decreasing a complexity and manufacturing cost of fabricating connection components <NUM>, <NUM>, <NUM>, and <NUM>.

In the exemplary embodiment, connection component bonding pads <NUM> and substrate bonding pads <NUM> are electrically coupled together through wires <NUM>. This facilitates connecting logic die <NUM> directly to substrate <NUM>. As described herein, wires <NUM> are fabricated from, for example, and without limitation, gold, aluminum, copper, and alloys thereof. Coupling logic die <NUM> to substrate <NUM> via wires <NUM> facilitates a cost effective and flexible technique for coupling IC device <NUM> to other electrical devices and/or circuits (not shown).

<FIG> is a schematic plan view of an IC device <NUM> formed in a single 3D package structure. With reference to <FIG> and <FIG>, in the exemplary embodiment, IC device <NUM> is fabricated substantially similar to IC devices <NUM> and <NUM>, as are described herein. For example, IC device <NUM> includes package substrate <NUM>, at least one logic die <NUM>, and at least one memory die <NUM>. However, as opposed to the unitary connection component <NUM> or generally rectangular-shaped connection components <NUM>, <NUM>, <NUM>, and <NUM> described herein with respect to IC devices <NUM> and <NUM>, respectively, IC device <NUM> includes one or more "L-shaped" connection components, for example connection components <NUM> and <NUM>, as shown in <FIG>. Connection components <NUM> and <NUM> are coupled to package substrate <NUM> via a plurality of solder micro-bumps <NUM>. Logic die <NUM> is positioned on and coupled to connection components <NUM> and <NUM> opposite package substrate <NUM>. Logic die <NUM> is coupled directly to connection components <NUM> and <NUM> via a plurality of solder micro-bumps <NUM>.

In the exemplary embodiment, connection components <NUM> and <NUM> are discrete components positioned about a perimeter of logic die <NUM>, defining a cavity <NUM> therebetween for receiving memory die <NUM>. As shown in <FIG>, connection components <NUM> and <NUM> are positioned to define a generally rectangular-shaped cavity <NUM>. Logic die <NUM> and memory die <NUM> are coupled directly to each such that memory die <NUM> is positioned vertically between logic die <NUM> and package substrate <NUM>. In such an embodiment, memory die <NUM> is positioned in cavity <NUM> defined by connection components <NUM> and <NUM>, and logic die <NUM> overlaps memory die <NUM> entirely. Alternatively, logic die <NUM> only partially overlaps memory die <NUM>.

In the exemplary embodiment, as shown in <FIG> and <FIG>, logic die <NUM> is coupled directly to connection components <NUM> and <NUM> via a plurality of solder micro-bumps <NUM>. Connection components <NUM> and <NUM> include one or more wire bonding pads <NUM> formed on a redistribution wiring layer <NUM>. Bonding pads <NUM> are electrically connected to at least one solder micro-bump <NUM> via an electrical circuit (not shown) formed on redistribution wiring layer <NUM> and/or internal circuitry <NUM> formed within one or more build-up layers (not shown) of connection components <NUM> and <NUM>. Thus an electrical signal (not shown) is transmitted from logic die <NUM> to one or more wire bonding pads <NUM>. It is noted that, as opposed to at least some known interposers, connection components <NUM> and <NUM> are free of through silicon vias, thereby facilitating decreasing a complexity and manufacturing cost of fabricating connection components <NUM> and <NUM>.

Moreover, in the exemplary embodiment, connection component bonding pads <NUM> and substrate bonding pads <NUM> are electrically coupled together through wires <NUM>. This facilitates connecting logic die <NUM> directly to substrate <NUM>. As described herein, wires <NUM> are fabricated from, for example, and without limitation, gold, aluminum, copper, and alloys thereof. Coupling logic die <NUM> to substrate <NUM> via wires <NUM> facilitates a cost effective and flexible technique for coupling IC device <NUM> to other electrical devices and/or circuits (not shown).

Furthermore, in the exemplary embodiment, connection components <NUM> and <NUM> are formed in substantially the same manner as connection component <NUM> and/or connection components <NUM>, <NUM>, <NUM>, and <NUM>. For example, connection components <NUM> and <NUM> are fabricated from silicon and include one or more redistribution wiring layers <NUM>. Alternatively, connection components <NUM> and <NUM> are fabricated from any material that enables connection components <NUM> and <NUM> to function as described herein, for example, and without limitation, glass, ceramic, organic materials, germanium, gallium arsenide, indium phosphide, and silicon carbide. In addition, in some embodiments, one or more of connection components <NUM> and <NUM> is an active connection component, including one or more active electrical components embedded and/or formed thereon, for example, and without limitation, transistors, signal amplifiers, signal filters, and any other active electrical component that enables the one or more inter connection components <NUM> and <NUM> to function as described herein. In an example not forming part of the claimed invention but useful for understanding, one or more of connection components <NUM> and <NUM> is a passive interposer, i.e., connection components <NUM> and <NUM> do not include additional electrical components. In some embodiments, one or more of connection components <NUM> and <NUM> include one or more integrated passive devices (IPDs) embedded and/or formed thereon, for example, and without limitation, resistors, capacitors, inductors, and any other passive electrical components that enable connection components <NUM> and <NUM> to function as described herein.

<FIG> is a flow diagram of an exemplary method <NUM> of forming an IC device having a single 3D package structure, such as exemplary IC device <NUM> shown in <FIG>. With reference to <FIG>, exemplary method <NUM> includes forming <NUM> at least one connection component, for example connection component <NUM>, having a cavity <NUM> defined therein. Additionally or alternatively, method <NUM> includes separately forming <NUM> a plurality of connection components, for example, connection components <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM> and <NUM>, and positioning <NUM> the plurality of connection components <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM> and <NUM> on a substrate, such as substrate <NUM>, to define a cavity (e.g., cavity <NUM> or <NUM>, respectively) therebetween. Each connection component <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and/or <NUM> and <NUM> includes one or more wire bonding pads (e.g., wire bonding pad <NUM>, <NUM>, or <NUM>, respectively) formed on redistribution wiring layer <NUM>, <NUM>, or <NUM>, respectively. In addition, substrate <NUM> includes one or more wire bonding pads <NUM> formed on active surface <NUM> of substrate <NUM>.

In the exemplary embodiment, method <NUM> also includes coupling <NUM> the at least one connection component to substrate <NUM>. Additionally or alternatively, the operation of coupling <NUM> the at least one connection component further includes bonding <NUM> the at least one connection component to substrate <NUM> via adhesive bonding, solder micro-bumps <NUM>, and any other electrical or non-electrical bonding process that enables IC device <NUM> to function as described herein.

In some embodiments, method <NUM> includes electrically coupling <NUM> at least one memory die <NUM> to substrate <NUM> via a plurality of solder micro-bumps <NUM>, such that memory die <NUM> is positioned within the cavity defined by the at least one connection component. In one such embodiment, electrically coupling <NUM> the at least one memory die <NUM> to substrate <NUM> includes electrically coupling <NUM> active surface <NUM> of memory die <NUM> to substrate <NUM>. In an alternative embodiment, the operation of electrically coupling <NUM> at least one memory die <NUM> to substrate <NUM> includes electrically coupling <NUM> a plurality of TSVs <NUM> to substrate <NUM> via a plurality of solder micro-bumps <NUM>, i.e., coupling a non-active surface of memory die <NUM> to substrate <NUM>.

In the exemplary embodiment, method <NUM> further includes electrically coupling <NUM> logic die <NUM> to memory die <NUM> and at least a portion of the connection components. For example, logic die <NUM> is coupled to memory die <NUM> via a plurality of solder micro-bumps <NUM>. In addition, logic die <NUM> is coupled to the at least one connection component via a plurality of solder micro-bumps <NUM>. In one embodiment, logic die <NUM> overlies memory die <NUM> entirely. In an alternative embodiment, logic die <NUM> only partially overlies memory die <NUM>.

Moreover, method <NUM> includes electrically coupling <NUM> the connection component bonding pads, for example pads <NUM>, <NUM>, or <NUM>, to substrate bonding pads <NUM> via wires <NUM>. This facilitates electrically coupling logic die <NUM> to substrate <NUM>.

The above-described embodiments of connection components and methods enable making of IC devices with thermally advantageous arrangements, improved heat dissipation, and reduced complexity and cost of manufacturing as compared to at least some known IC devices. Specifically, the disclosed connection component embodiments include a cavity configured to receive at least one reduced power dissipation component, for example, a memory die (or memory die stack). The cavity facilitates electrically coupling the memory die to a logic die and an IC package substrate, vertically positioning the memory die therebetween. This enables the memory die, which is typically positioned on top of the logic die due to a reduced number of electrical interconnection, to have its logic die connections couple directly to the logic die and the remaining connection to couple to other circuitry on the substrate. In addition, such an arrangement reduces and/or eliminates the need for TSVs to be formed in the logic die, thereby reducing size and complexity of the logic die. The connection component enables the logic die to electrically connect to the circuitry on the substrate via wire bonds (e.g., ball bonding, wedge bonding, and compliant bonding), thereby reducing and/or eliminating the need for TSVs formed in the memory die to pass electric signals from the logic die. Also specifically, the connection component facilitates reducing the complexity, time, and cost of fabricating the IC devices described herein.

Claim 1:
An integrated circuit, IC, device (<NUM>, <NUM>, <NUM>) comprising:
a substrate (<NUM>);
one of the two alternatives:
(a) at least one connection component (<NUM>) defining a cavity (<NUM>) therethrough, said connection component (<NUM>) coupled to said substrate (<NUM>); or
(b) a plurality of connection components (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) defining a cavity (<NUM>, <NUM>) therebetween, said plurality of connection components (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) coupled to said substrate (<NUM>);
at least one memory die (<NUM>) positioned in said cavity (<NUM>, <NUM>, <NUM>), said at least one memory die (<NUM>) electrically coupled to said substrate (<NUM>); and
a logic die (<NUM>) extending over said at least one memory die (<NUM>) and at least a portion of said connection component (<NUM>), or at least a portion of said plurality of connection components (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), said at least one logic die (<NUM>) being electrically coupled to said connection component (<NUM>), or to the plurality of connection components (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>), and to said at least one memory die (<NUM>), wherein the connection component (<NUM>) or the plurality of connection components (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) is or are free of through silicon vias, and is or are electrically coupled to said substrate (<NUM>),
wherein said connection component (<NUM>) or said plurality of connection components (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprises or comprise a redistribution wiring layer (<NUM>, <NUM>, <NUM>), comprising at least one wire bonding pad (<NUM>, <NUM>, <NUM>), said connection component (<NUM>) or said plurality of connection components (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) being electrically coupled to said substrate (<NUM>) through at least one wire (<NUM>) bond, and
wherein at least one connection component (<NUM>) or one or more of the plurality of connection components (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>) comprises or comprise at least one passive component, or in alternative one active electrical component, embedded therein, said passive component comprising one or more of the following: resistors, capacitors, and inductors, said active electrical component comprising one or more of the following: transistors, signal amplifiers, and signal filters.