Patent Description:
With the progress in the development of display devices which visually display electrical signals, display devices have been used for various purposes. <CIT> discloses a liquid crystal display device including a first substrate, a second substrate and liquid crystal. <CIT> discloses an organic light emitting diode display with electrostatic discharges protection. <CIT> discloses an organic light-emitting display apparatus including a shield layer.

According to the invention, there is provided a display device as set out in claim <NUM>. Preferred features of the invention are set out in claims <NUM> to <NUM>.

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art.

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Throughout the disclosure, the expression "at least one of a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

Referring to <FIG>, the display device <NUM> includes a display area DA and a peripheral area PA outside the display area DA. The display device <NUM> may provide an image via the display area DA. The display device <NUM> may be a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a quantum dot light-emitting display, a field emission display, a surface-conduction electron-emitter display, a plasma display, a cathode ray display or the like.

Hereinafter, an organic light-emitting display device will be described as an example of the display device <NUM> according to an embodiment.

<FIG> and <FIG> illustrate cross-sectional views of a display device according to embodiments.

Referring to <FIG> and <FIG>, the display device <NUM> may include a display unit (or display panel) <NUM>, an input sensor <NUM>, an anti-reflection layer <NUM>, and a window <NUM>.

The display <NUM> generates an image. The display <NUM> may generate a predetermined image by using red, green, blue or white light emitted from, for example, organic light-emitting diodes (OLEDs).

The input sensor <NUM> may acquire coordinate information according to an external input, for example, a touch event. The input sensor <NUM> may be arranged above the display <NUM> and under the anti-reflection layer <NUM>, as illustrated in <FIG>, or above the anti-reflection layer <NUM>, as illustrated in <FIG>. The input sensor <NUM> may include a sensing electrode (or touch electrode) and a signal line (trace line) connected to the sensing electrode.

According to an embodiment, the input sensor <NUM> may be disposed directly on the display unit <NUM>. The description "input sensor <NUM> disposed directly on the display unit <NUM>" indicates that no additional adhesive layer is interposed between the input sensor <NUM> and the display unit <NUM> and that elements of the input sensor <NUM> are directly patterned on the display unit <NUM>. In some implementations, the input sensor <NUM> may be formed in a separate process from the display unit <NUM> and then combined to the display unit <NUM> by using an adhesive material layer or the like.

The anti-reflection layer <NUM> may reduce reflectivity of light incident from the outside onto the display unit <NUM> through the window <NUM>. The anti-reflection layer <NUM> may be disposed on the input sensor <NUM> as illustrated in <FIG> or under the input sensor <NUM> as illustrated in <FIG>.

According to an embodiment, the anti-reflection layer <NUM> may include a polarizer, a phase retarder, or the like. In some implementations, the anti-reflection layer <NUM> may include a black matrix and a color filter. When the anti-reflection layer <NUM> includes a polarizer or the like, the polarizer may be relatively thick. In this case, the anti-reflection layer <NUM> may be attached to the display unit <NUM> or the input sensor <NUM> using an adhesive material layer or the like. When the anti-reflection layer <NUM> includes a black matrix and a color filter, the anti-reflection layer <NUM> may have a relatively small thickness. In this case, the anti-reflection layer <NUM> may be directly disposed on the display unit <NUM> or the input sensor <NUM>.

The window <NUM> may include a light transmitting area <NUM> corresponding to the display area DA and a light shielding area <NUM> corresponding to the peripheral area PA.

<FIG> and <FIG> illustrate cross-sectional views schematically illustrating a display unit according to an embodiment.

Referring to <FIG>, the display unit <NUM> may include a display element layer <NUM> disposed on a substrate <NUM> and an encapsulation member <NUM> covering the display element layer <NUM>.

The substrate <NUM> may include a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP). The substrate <NUM> maybe in a form of a single layer or may be a multi-layer structure of the above materials. In the case of a multi-layer structure, the substrate <NUM> may further include an inorganic layer. The substrate <NUM> may have flexible, rollable or bendable characteristics.

The display element layer <NUM> includes pixels. Each pixel may include an organic light-emitting diode and a pixel circuit electrically connected to the organic light-emitting diode. The pixel circuit may include a thin film transistor and a storage capacitor and lines connected thereto. The pixel circuit may also include one or more insulating layers.

The encapsulation member <NUM> may protect the display element layer <NUM> from external foreign substances such as moisture. The encapsulation member <NUM> may include a thin film encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer. The inorganic encapsulation layer may include, for example, a silicon oxide layer, a silicon nitride layer or/and a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic encapsulation layer may include, for example, an acrylic based organic material.

While <FIG> illustrates that the encapsulation member <NUM>, which is a thin film encapsulation layer, includes first and second inorganic encapsulation layers <NUM> and <NUM> and an organic encapsulation layer <NUM> interposed therebetween, in some implementations, the stacking order of inorganic encapsulation layers and organic encapsulation layers or the like may be varied. Also, the encapsulation member <NUM> may be other than a thin film encapsulation layer.

Referring to <FIG>, the display unit <NUM> may include an encapsulation member <NUM>' including a sealant <NUM>' and an encapsulation substrate <NUM>'. The substrate <NUM> as illustrated in <FIG> may include the above-described polymer resin, or may include glass or the like.

The encapsulation substrate <NUM>' may be disposed to face the substrate <NUM>, and a sealant <NUM>' may be disposed between the substrate <NUM> and the encapsulation substrate <NUM>'. The sealant <NUM>' may surround the display area DA. An inner space defined by the substrate <NUM>, the encapsulation substrate <NUM>', and the sealant <NUM>' may be separated from the outer space and penetration of moisture or impurities thereinto may be reduced or prevented. The encapsulation substrate <NUM>' may include the above-described polymer resin or glass or the like, and a material such as a frit or an epoxy may be used as the sealant <NUM>'.

<FIG> illustrates a plan view of a display unit according to an embodiment, and <FIG> illustrates an equivalent circuit diagram of a pixel according to an embodiment.

Referring to <FIG>, the display unit <NUM> may include pixels P arranged in the display area DA. The pixels P may include a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC, as illustrated in <FIG>. A pixel electrode (e.g., an anode) of the organic light-emitting diode OLED may be connected to the pixel circuit PC. An opposite electrode (e.g., a cathode) of the organic light-emitting diode OLED may be connected to a second power ELVSS. The organic light-emitting diode OLED may emit light of a predetermined luminance based on a current supplied from the pixel circuit PC.

The pixel circuit PC may include a thin film transistor and a capacitor. The pixel circuit PC may include first through fourth thin film transistors T1, T2, T3, and T4 and a storage capacitor Cst, as illustrated in <FIG>.

A gate electrode of the first thin film transistor T1 may be connected to a scan line SL. A first electrode of the first thin film transistor T1 may be connected to a data line DL, and a second electrode of the first thin film transistor T1 may be connected to the storage capacitor Cst. The first thin film transistor T1 may be turned on when a scan signal is supplied to the scan line SL.

A gate electrode of the second thin film transistor T2 may be connected to the storage capacitor Cst. A first electrode of the second thin film transistor T2 may be connected to the storage capacitor Cst and a first power ELVDD. The second thin film transistor T2 may control an amount of current flowing from the first power ELVDD to the second power ELVSS via the organic light-emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may generate light corresponding to the amount of current supplied from the second thin film transistor T2.

A gate electrode of the third thin film transistor T3 may be connected to an emission control line EL. A first electrode of the third thin film transistor T3 may be connected to a second electrode of the second thin film transistor T2, and a second electrode of the third thin film transistor T3 may be connected to the organic light-emitting diode OLED. The third thin film transistor T3 may be turned off when an emission control signal is supplied to the emission control line EL and may be turned on when no emission control signal is supplied. The emission control signal may be supplied during a period during which a voltage corresponding to a data signal is charged in the storage capacitor Cst and during a period during which deterioration information of the organic light-emitting diode OLED is sensed.

The fourth thin film transistor T4 may be a sensing transistor and may be turned on during a period of a current sensing operation of the organic light-emitting diode OLED. A gate electrode of the fourth thin film transistor T4 may be connected to a control line CL. A first electrode of the fourth thin film transistor T4 may be connected to the second electrode of the third thin film transistor T3. A second electrode of the fourth thin film transistor T4 may be connected to the data line DL. The fourth thin film transistor T4 may be turned on when a control signal is supplied to the control line CL, and may be turned off otherwise. A control signal may be supplied during a period during which deterioration information of the organic light-emitting diode OLED is sensed.

<FIG> illustrates an embodiment in which the pixel P includes four thin film transistors and one storage capacitor In some implementations, the pixel circuit PC may be include two, three or five or more thin film transistors or include two or more storage capacitors.

Referring back to <FIG>, the peripheral area PA of the display unit <NUM> may surround the display area DA. The peripheral area PA may correspond to a non-display area that does not provide an image.

A scan driving circuit <NUM> as a first peripheral circuit, a control driving circuit <NUM> as a second peripheral circuit, a terminal <NUM>, a first power supply wiring (or a first power voltage wiring) <NUM>, and a second power supply wiring (or a second power voltage wiring) <NUM> may be disposed in the peripheral area PA.

The scan driving circuit <NUM> may be disposed on the peripheral area PA of the substrate <NUM>. The scan driving circuit <NUM> may be electrically connected to the scan line SL and may supply a predetermined scan signal to the scan line SL. According to an embodiment, when the pixel P includes the third thin film transistor T3 that corresponds to an emission control thin film transistor as described with reference to <FIG>, the scan driving circuit <NUM> may supply an emission control signal to the emission control line EL.

The control driving circuit <NUM> may be disposed on the peripheral area PA of the substrate <NUM>. The scan driving circuit <NUM> and the control driving circuit <NUM> may be arranged in parallel with each other with the display area DA therebetween. The scan driving circuit <NUM> may be disposed at a first side of the display area DA, and the control driving circuit <NUM> may be disposed at a second side of the display area DA opposite to the first side.

The terminal <NUM> may be disposed at one end of the substrate <NUM>. The terminal <NUM> may not be covered by an insulating layer but be exposed and electrically connected to a printed circuit board PCB. The terminal <NUM> may be disposed on a side of the peripheral area PA where the scan driving circuit <NUM> and the control driving circuit <NUM> are not located. For example, the terminal <NUM> may be disposed in parallel with a third side of the display area DA.

A terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal <NUM> of the display unit <NUM>. The printed circuit board PCB may provide a signal of a controller or may provide power to the display unit <NUM>. Control signals generated in the controller may be transmitted to each of the scan driving circuit <NUM> and the control driving circuit <NUM> via the printed circuit board PCB. The controller may respectively provide the first power ELVDD and the second power ELVSS (see <FIG>) to the first and second power supply wirings <NUM> and <NUM> through first and second connection wirings <NUM> and <NUM>. The first power ELVDD may be provided to each of the pixels P through a driving voltage line PL connected to the first power supply wiring <NUM>, and the second power ELVSS may be provided to opposite electrodes of the pixels P connected to the second power supply wiring <NUM>.

The data driving circuit <NUM> may be electrically connected to the data line DL. A data signal of the data driving circuit <NUM> may be provided to each pixel P through a wiring <NUM> connected to the terminal <NUM> and a data line DL connected to the wiring <NUM>. The data driving circuit <NUM> may be disposed on the printed circuit board PCB, as illustrated in <FIG>. In some implementations, the data driving circuit <NUM> may be disposed on the substrate <NUM>. For example, the data driving circuit <NUM> may be disposed between the terminal <NUM> and the first power supply wiring <NUM> illustrated in <FIG>.

The first power supply wiring <NUM> and the second power supply wiring <NUM> may be disposed in the peripheral area PA. The first power supply wiring <NUM> may be disposed adjacent to the third side of the display unit <NUM>. The second power supply wiring <NUM> may partially surround the display area DA along an edge of the display area DA. For example, the second power supply wiring <NUM> may have the form of an incomplete loop in which one side is open.

The second power supply wiring <NUM> may be connected to the second connection wiring <NUM> that is connected to the terminal <NUM>. The second connection wiring <NUM> may have the form of an incomplete loop extending to partially surround the display area DA and being open at one side. <FIG> illustrates that, like the second power supply wiring <NUM>, the second connection wiring <NUM> may extend along a first side (left side in <FIG>), a fourth side (upper side in <FIG>), and a second side (right side in <FIG>) of the display area DA. In some implementations, the second connection wiring <NUM> may be connected only to an end of the second power supply wiring <NUM>. For example, a pair of second connection wirings <NUM> may be each connected to both ends of the second power supply wiring <NUM> adjacent to the third side of the display area DA.

<FIG> illustrates plan views schematically depicting the input sensor <NUM> according to embodiments.

Referring to <FIG>, the input sensor <NUM> may include first sensing electrodes <NUM>, first signal lines <NUM>-<NUM> through <NUM>-<NUM> connected to the first sensing electrodes <NUM>, second sensing electrodes <NUM>, and second signal lines <NUM>-<NUM> through <NUM>-<NUM> connected to the second electrodes <NUM>. The input sensor <NUM> may sense an external input by using a mutual capacitance method or/and a self capacitance method.

The first sensing electrodes <NUM> may be arranged in a y-direction, and the second sensing electrodes <NUM> may be arranged in an x-direction crossing the y-direction. The first sensing electrodes <NUM> arranged along the y-direction may respectively form first sensing lines 410C1 through 410C4 by connecting through a first connection electrode <NUM>, and the second sensing electrodes <NUM> arranged along the x-direction may respectively form second sensing lines 420R1 through 420R5 by connecting through a second connection electrode <NUM>. The first sensing lines 410C1 through 410C4 and the second sensing lines 420R1 through 420R5 may intersect each other. For example, the first sensing lines 410C1 through 410C4 and the second sensing lines 420R1 through 420R5 may be perpendicular to each other.

The first sensing lines 410C1 through 410C4 and the second sensing lines 420R1 through 420R5 may be disposed on the display area DA and may be connected to a sensing signal pad <NUM> via the first and second signal lines <NUM>-<NUM> through <NUM>-<NUM> and <NUM>-<NUM> through <NUM>-<NUM> in the peripheral area PA. The first sensing lines 410C1 through 410C4 may be respectively connected to the first signal lines <NUM>-<NUM> through <NUM>-<NUM>, and the second sensing lines 420R1 through 420R5 may be respectively connected to the second signal lines <NUM>-<NUM> through <NUM>-<NUM>.

The first signal lines <NUM>-<NUM> through <NUM>-<NUM> may each be connected to both an upper portion and a lower portion of the first sensing lines 410C1 through 410C4, respectively, as illustrated in <FIG>. Sensing sensitivity may be increased according to this structure. In some implementations, the first signal lines <NUM>-<NUM> through <NUM>-<NUM> may be connected to either the upper portion or the lower portion of the first sensing lines 410C1 through 410C4. In some implementations, each of the first signal lines <NUM>-<NUM> through <NUM>-<NUM> may be simultaneously connected to both the upper and lower portions of the first sensing lines 410C1 through 410C4, respectively, while also connected to the sensing signal pad <NUM>, as illustrated in <FIG>. In some implementations, each of the second sensing lines 420R1 through 420R4 may be connected to the second signal lines <NUM>-<NUM> to <NUM>-<NUM> that are respectively provided on the left and right sides, as illustrated in <FIG>. A layout of the first and second signal lines <NUM>-<NUM> to <NUM>-<NUM> and <NUM>-<NUM> through <NUM>-<NUM> may be provided in the peripheral area PA. In some implementations, the layout may be modified in according to the shape or size of the display area DA or a sensing method of the input sensor <NUM>.

<FIG> and <FIG> illustrate schematic cross-sectional views corresponding to line VII-VII' of <FIG> and depicting the second signal lines <NUM>-<NUM> through <NUM>-<NUM>, The first signal lines <NUM>-<NUM> through <NUM>-<NUM> may have the same cross-sectional structure as that of the second signal lines <NUM>-<NUM> through <NUM>-<NUM>. <FIG> and <FIG> illustrate five second signal lines <NUM>-<NUM> through <NUM>-<NUM> as an example.

Referring to one second signal line <NUM>-<NUM> illustrated in <FIG>, the second signal line <NUM>-<NUM> may include a first signal line portion 425a and a second signal line portion 425b. The first and second signal line portions 425a and 425b may be overlap with each other between insulating layers IL1, IL2, and IL3, and may be connected through a contact hole <NUM> to reduce resistance. According to an embodiment, in the second signal line <NUM>-<NUM>, one of the first and second signal line portions 425a and 425b formed on different layers with the insulating layer <NUM> included therebetween in <FIG> may be omitted. For example, as illustrated in <FIG>, the second signal line <NUM>-<NUM> may include a second signal line portion 425b, and may further include a third signal line portion 425c thereon. The second signal line <NUM>-<NUM> may be a conductive multi-layer in which, for example, a transparent conductive layer is disposed on the metal layer. According to an embodiment, the second signal line <NUM>-<NUM> may be a single layer.

<FIG> illustrates a cross-sectional view of a display device according to an embodiment, in which a display unit and an input sensor overlap each other. <FIG> and <FIG> respectively illustrate partial plan views depicting first and second shielding layers of <FIG>. <FIG> illustrate a plan view depicting a state in which the first and second shielding layers overlap each other. <FIG> corresponds to a cross-section taken along line VIII-VIII' of <FIG> and <FIG>.

Referring to the display area DA of <FIG>, the display element layer <NUM> and the encapsulation member <NUM> may be disposed on the substrate <NUM>.

A buffer layer <NUM> may be formed on the substrate <NUM>. The buffer layer <NUM> may block penetration of foreign substances or moisture through the substrate <NUM>. The buffer layer <NUM> may include, for example, an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride, and may be formed as a single layer or as a multilayer.

A thin film transistor TFT, a storage capacitor Cst, and an organic light-emitting diode OLED that is electrically connected to these elements may be disposed on the substrate <NUM>. The thin film transistor TFT may include a semiconductor layer Act and a gate electrode GE. The semiconductor layer Act may include polysilicon, amorphous silicon, an oxide semiconductor, an organic semiconductor material or the like. In an embodiment, the semiconductor layer Act may include a channel region CR overlapping the gate electrode GE and a source region CR and a drain region DR that are on opposite sides of the channel region CR and include an impurity having a higher concentration than the channel region CR. The impurity may include an N-type impurity or a P-type impurity. The source region SR and the drain region DR may be respectively understood as a source electrode and a drain electrode of the thin film transistor TFT.

A gate insulating layer <NUM> may be disposed between the semiconductor layer Act and the gate electrode GE. The gate insulating layer <NUM> may be an inorganic layer such as silicon oxynitride, silicon oxide and/or silicon nitride, and the inorganic layer may be a single layer or a multilayer.

The storage capacitor Cst may include first and second storage capacitor plates CE1 and CE2 overlapping each other. A first interlayer insulating layer <NUM> may be disposed between the first and second storage capacitor plates CE1 and CE2. The first interlayer insulating layer <NUM> may have a predetermined permittivity. The first interlayer insulating layer <NUM> may be an inorganic layer such as silicon oxynitride (SiON), silicon oxide (SiOx), and/or silicon nitride (SiNx), and may be in a form of a single layer or a multilayer. In some implementations, the storage capacitor Cst may overlap the thin film transistor TFT and the first storage capacitor plate CE1 may also be the gate electrode GE of the thin film transistor TFT, as illustrated in <FIG>. In some implementations, the storage capacitor Cst may not overlap with the thin film transistor TFT. Instead, the first storage capacitor plate CE1 may be a separate independent component from the gate electrode GE of the thin film transistor TFT.

The storage capacitor Cst may be covered by the second interlayer insulating layer <NUM>. The second interlayer insulating layer <NUM> may be an inorganic layer such as silicon oxynitride, silicon oxide, and/or silicon nitride, and may be in a form of a single layer or a multilayer.

A driving voltage line PL may include a first driving voltage line PL1 and a second driving voltage line PL2. The first driving voltage line PL1 may include a same material as the data line DL. For example, the first driving voltage line PL1 and the data line DL may include aluminum (Al), copper (Cu), titanium (Ti) or the like, and may be formed as a multilayer or single layer. In an embodiment, the first driving voltage line PL1 and the data line DL may have a multilayer structure of Ti/Al/Ti.

The second driving voltage line PL2 may be disposed on the first driving voltage line PL1 with the first insulating layer <NUM> therebetween. The second driving voltage line PL2 may be electrically connected to the first driving voltage line PL1 through a contact hole defined in the first insulating layer <NUM>. The second driving voltage line PL2 may include aluminum (Al), copper (Cu), titanium (Ti) or the like, and may be formed as a multilayer or a single layer. In an embodiment, the second driving voltage line PL2 may have a multilayer structure of Ti/Al/Ti. The first insulating layer <NUM> may include an organic insulating material such as, for example, an imide-based polymer, a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an aryl-ether based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or blends thereof. For example, the first insulating layer <NUM> may include polyimide.

The driving voltage line PL may be covered by the second insulating layer <NUM>. The second insulating layer <NUM> may include an organic insulating material. For example, the second insulating layer <NUM> may include an imide-based polymer, polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an aryl-ether based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and blends thereof. According to an embodiment, the second insulating layer <NUM> may include polyimide.

A pixel electrode <NUM> may be disposed on the second insulating layer <NUM>. A pixel defining layer <NUM> may be disposed on the pixel electrode <NUM>. The pixel defining layer <NUM> may have an opening corresponding to each pixel, for example, an opening exposing at least the pixel electrode <NUM> to thereby define each pixel. In addition, the pixel defining layer <NUM> may increase a distance between an edge of the pixel electrode <NUM> and the opposite electrode <NUM> to thereby prevent an arc or the like between the edge of the pixel electrode <NUM> and the opposite electrode <NUM>. The pixel defining layer <NUM> may be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

The intermediate layer <NUM> may include a low molecular material or a polymer material.

When the intermediate layer <NUM> includes a low molecular material, the intermediate layer <NUM> may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL) or the like are stacked in a single structure or in a composite structure. The intermediate layer <NUM> may include various organic materials such as copper phthalocyanine (CuPc), N,N-di(naphthalene- N, N'-diphenyl-benzidine) (NPB), or tris-<NUM>-hydroxyquinoline aluminum (Alq3). These layers may be formed using a vacuum deposition method.

When the intermediate layer <NUM> includes a polymer material, the intermediate layer <NUM> may typically have a structure including a hole transport layer (HTL) and an emission layer (EML). The hole transport layer may include PEDOT, and the emission layer may include a polymer material such as a poly-phenylenevinylene (PPV)-based material and a polyfluorene-based material. The intermediate layer <NUM> may have various structures. For example, at least one of the layers of the intermediate layer <NUM> may be integrally formed over a plurality of pixel electrodes <NUM>. In some implementations, the intermediate layer <NUM> may include layers that are patterned to respectively correspond to the plurality of pixel electrodes <NUM>.

The opposite electrode <NUM> may be disposed above the display area DA and may be arranged to cover the display area DA. For example, the opposite electrode <NUM> may be integrally formed to cover a plurality of pixels.

The encapsulation member <NUM> may be, for example, a thin film encapsulation layer. The encapsulation member <NUM> may cover the organic light-emitting diode OLED and may prevent damage that could occur due to moisture or oxygen penetrating from the outside. The thin film encapsulation layer may cover the display area DA and extend to the outside of the display area DA. The thin film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. <FIG> illustrates an embodiment in which the thin film encapsulation layer includes a first inorganic encapsulation layer <NUM>, an organic encapsulation layer <NUM>, and a second inorganic encapsulation layer <NUM>.

A plurality of layers including a capping layer <NUM> may be interposed between the first inorganic encapsulation layer <NUM> and the opposite electrode <NUM>. While <FIG> illustrates that the capping layer <NUM> is provided, according to some implementations, the capping layer <NUM> may be omitted. When the capping layer <NUM> is omitted, the first inorganic encapsulation layer <NUM> may include at least two silicon oxynitride (SiON) layers having different properties.

The first inorganic encapsulation layer <NUM> may be formed along the elements formed under the same. Accordingly, the first inorganic encapsulation layer <NUM> may have an uneven top surface. The organic encapsulation layer <NUM> may cover the first inorganic encapsulation layer <NUM>. Unlike the top surface of the first inorganic encapsulation layer <NUM>, a top surface of the organic encapsulation layer <NUM> may be substantially flat. For example, the top surface of the organic encapsulation layer <NUM> may be substantially flat in a portion corresponding to the display area DA.

A sensing electrode may be disposed on the encapsulation member <NUM>. In this regard, <FIG> schematically illustrates the first sensing electrode <NUM> on the encapsulation member <NUM>. An insulating layer may be further disposed below and above the first sensing electrode <NUM> in <FIG>. In some implementations, the first sensing electrode <NUM> may include multiple layers. The first sensing electrode <NUM> may include an opening 410OP corresponding to a light-emitting region of the organic light-emitting diode OLED such that light of the organic light-emitting diode OLED may be emitted to the outside.

Referring to the peripheral area PA of <FIG>, an inorganic insulating layer <NUM> may be disposed on the substrate <NUM>. The inorganic insulating layer <NUM> may include at least one of the buffer layer <NUM>, the gate insulating layer <NUM>, and the first and second interlayer insulating layers <NUM> and <NUM> described above. A second connection wiring <NUM> may be disposed on the inorganic insulating layer <NUM>. The second connection wiring <NUM> may include a same material as the data line DL and/or the first driving voltage line PL1, and may be disposed on a same level as the data line DL and/or the first driving voltage line PL1.

The scan driving circuit <NUM> may be disposed on the substrate <NUM>. The scan driving circuit <NUM> may include thin film transistors TFT-P and may include a wiring connected to the thin film transistors TFT-P. The thin film transistors TFT-P may be formed in the same process as the thin film transistor TFT of the pixel circuit PC. The scan driving circuit <NUM> may include an insulating layer interposed between the elements of the thin film transistors TFT-P (for example, a semiconductor layer, a gate electrode, etc.). In an implementation, the scan driving circuit <NUM> may be covered by an inorganic protection layer <NUM>.

The scan driving circuit <NUM> may overlap a first shielding layer <NUM> and a second shielding layer <NUM> disposed above the scan driving circuit <NUM>. The first shielding layer <NUM> may be disposed above the scan driving circuit <NUM> with the first insulating layer <NUM> therebetween, and the second shielding layer <NUM> may be disposed above the first shielding layer <NUM> with the second insulating layer <NUM> therebetween. The first shielding layer <NUM> may be disposed on a same level as and include a same material as the second driving voltage line PL2. The second shielding layer <NUM> may be disposed on a same level as and include a same material as the pixel electrode <NUM>.

A first width W1 of the first shielding layer <NUM> and a second width W2 of the second shielding layer <NUM> may be equal to or greater than a width of the scan driving circuit <NUM>, as shown in <FIG>.

The first shielding layer <NUM> and the second shielding layer <NUM> include a hole. One shielding layer of the first and second shielding layers <NUM> and <NUM> may includes a hole that overlaps the other shielding layer.

In an embodiment, the first shielding layer <NUM> may include first holes <NUM> as illustrated in <FIG> and <FIG>. The first holes <NUM> may be spaced apart from one another on a plane. The second shielding layer <NUM> may include second holes <NUM> as illustrated in <FIG> and <FIG>. The second holes <NUM> may be spaced apart from each other on a plane. Each of the first and second holes <NUM> and <NUM> may be an outgassing passage of the first and second insulating layers <NUM> and <NUM>, which are disposed under the first and second shielding layers <NUM> and <NUM>. Accordingly, issues that may arise when the first and second holes <NUM> and <NUM> are not included, such as, for example, damage to the first and second shielding layers <NUM> and <NUM> or to the organic light-emitting diode OLED by gas in the first and second insulating layers <NUM> and <NUM> may be prevented or minimized.

The first holes <NUM> and the second holes <NUM> may be arranged to be offset from each other in a plan view. As illustrated in <FIG> and <FIG>, a center of the first hole <NUM> and a center of the second hole <NUM> may be offset from each other and not coincident with each other. The first hole <NUM> and the second hole <NUM> may not overlap each other in a plan view. The first hole <NUM> of the first shielding layer <NUM> may overlap with a portion 1270P of the second shielding layer <NUM>, and the second hole <NUM> of the second shielding layer <NUM> may overlap with a portion 1170P of the first shielding layer <NUM>. In the present specification, the term "a portion of a shielding layer" refers to an area with no hole, formed of a same material for forming the shielding layer. Accordingly, the portion 1170P of the first shielding layer <NUM> may be regarded as a portion of the first shielding layer <NUM> except where the first holes <NUM> are located, and the portion 1270P of the second shielding layer <NUM> may be regarded as a portion of the second shielding layer <NUM> except where the second holes <NUM> are located.

As described above, when one shielding layer that includes a hole overlapping a portion of the other shielding layer, when projected in a direction (z direction) perpendicular to a main surface of the substrate <NUM>, and where a hole in one shielding layer does not overlap any hole in the other shielding layer in a plan view (looking at the display device from the z direction), the scan driving circuit <NUM> may be entirely covered by the first and second shielding layers <NUM> and <NUM>. Damage to the scan driving circuit <NUM> that could occur due to external electrostatic discharge (ESD) may be prevented by the first and second shielding layers <NUM> and <NUM>.

The first and second shielding layers <NUM> and <NUM> have a same voltage level. Referring to <FIG>, the first and second shielding layers <NUM> and <NUM> are electrically connected to the second connection wiring <NUM>. The first shielding layer <NUM> may contact the second connection wiring <NUM> through an opening 206OP of the first insulating layer <NUM> that exposes the second connection wiring <NUM>. The second shielding layer <NUM> may contact the first shielding layer <NUM> through an opening 207OP of the second insulating layer <NUM>. The first and second shielding layers <NUM> and <NUM> electrically connected to the second connection wiring <NUM> may form a second power supply wiring <NUM>.

The opposite electrode <NUM> is connected to the second shielding layer <NUM>. Accordingly, the second power ELVSS (see, for example, <FIG>) of the second power supply wiring <NUM> may be supplied to the opposite electrode <NUM>. An end of the opposite electrode <NUM> may pass by a dummy pixel DPX and extend to the peripheral area PA. The opposite electrode <NUM> may contact the second shielding layer <NUM> via a hole <NUM> in a portion of the pixel defining layer <NUM> that extends to the peripheral area PA. As illustrated in <FIG>, the end of the opposite electrode <NUM> may extend toward an outer edge of the substrate <NUM> to cover at least a portion of the scan driving circuit <NUM>.

A signal line connected to a sensing electrode may be disposed in the peripheral area PA. As illustrated in <FIG>, the second signal lines <NUM>-<NUM> through <NUM>-<NUM> may be arranged on the peripheral area PA. At least one of the second signal lines <NUM>-<NUM> through <NUM>-<NUM> may overlap the scan driving circuit <NUM>. The opposite electrode <NUM> and the first and second shielding layers <NUM> and <NUM> may be interposed between the scan driving circuit <NUM> and the second signal lines <NUM>-<NUM> through <NUM>-<NUM>.

In a general display device, a signal generated in a scan driving circuit could affect signal lines of an input sensor located on a scan driving circuit. In this case, accuracy of an input sensor could be reduced. However, according to embodiments, the opposite electrode <NUM> covers a portion of the scan driving circuit <NUM>. Accordingly, the impact of a signal (e.g., noise) of the scan driving circuit <NUM> on the second signal lines <NUM>-<NUM> through <NUM>-<NUM> may be minimized. As a comparative example, if an effort were to be made to reduce or prevent signal interference caused by a scan driving circuit and affecting signal lines using only the opposite electrode <NUM>, the opposite electrode <NUM> would have to entirely cover the scan driving circuit <NUM>. Thus, the opposite electrode <NUM> would have to extend farther toward an edge of the substrate <NUM>, and in turn, the peripheral area PA, which is a dead zone, would have to be increased. As another comparative example, if an end of the opposite electrode <NUM> were disposed as illustrated in <FIG> to reduce the peripheral area PA, it could be difficult to place a signal line of the input sensor in an area RA corresponding to a portion between the end of the opposite electrode <NUM> and the edge of the substrate <NUM>.

However, according to an embodiment, when the first and second shielding layers <NUM> and <NUM> are located between the second signal line <NUM>-<NUM> and the scan driving circuit <NUM> on the above-described area RA, an impact of a signal of the scan driving circuit <NUM> (e.g., noise) on the second signal line <NUM>-<NUM> may be prevented or minimized. Accordingly, a signal line, for example, the second signal line <NUM>-<NUM>, may also be arranged in the above-described area RA. In addition, when the scan driving circuit <NUM> and signal lines are disposed by fully utilizing the peripheral area PA as described above, the peripheral area PA, which is a dead zone, may be reduced.

According to an embodiment, the first and second insulating layers <NUM> and <NUM> disposed in the peripheral area PA may respectively include valley holes 206VH and 207VH. Damage to the organic light-emitting diode OLED or the like due to penetration of external foreign matters through bulk of each of the first and second insulating layers <NUM> and <NUM> may be prevented through valley holes 206VH and 207VH. <FIG> illustrates that at least one dam <NUM> may be provided on the outer edge of the substrate <NUM>. The dam <NUM> may prevent a monomer, used in a process of forming the organic encapsulation layer <NUM>, from extending toward the end of the substrate <NUM>, thereby reducing or preventing the formation of edge tails of the organic encapsulation layer <NUM>. <FIG> illustrates a thin film encapsulation layer as the encapsulation member <NUM>, In some implementations, the encapsulation member <NUM>' including the sealant <NUM>' and the encapsulation substrate <NUM>' may be included instead of the thin film encapsulation layer as described above with reference to <FIG>.

<FIG> illustrates an arrangement of the first shielding layer <NUM>, the second shielding layer <NUM>, and the second signal lines <NUM>-<NUM> through <NUM> -<NUM> with respect to the scan driving circuit <NUM> as a peripheral circuit disposed in the peripheral area PA. In some implementations, a stack structure on the control driving circuit <NUM> illustrated in <FIG> may also be substantially the same as the structure illustrated in <FIG>. For example, regarding the stack structure on the control driving circuit <NUM>, it may be understood that the control driving circuit <NUM> may be arranged instead of the scan driving circuit <NUM> of <FIG>. The first signal line <NUM>-<NUM> through <NUM>-<NUM> (see <FIG> and <FIG>) or the second signal lines <NUM>-<NUM> through <NUM>-<NUM> (see <FIG>) may be disposed on the control driving circuit <NUM> to overlap with the control driving circuit <NUM>.

<FIG> illustrates a plan view schematically depicting a display unit <NUM>' according to another embodiment. <FIG> illustrates a partial plan view of a switching circuit <NUM> of <FIG> and a portion around the switching circuit <NUM>. <FIG> illustrates a cross-sectional view of a display device according to another embodiment, in which a display unit and an input sensor overlap each other. <FIG> may correspond to a cross-section taken along line XII-XII' of <FIG>.

The display unit <NUM>' of <FIG> may be substantially the same as the display unit <NUM> described above with reference to <FIG>, except that the display unit <NUM>' further includes the switching circuit <NUM> as a third peripheral circuit. Thus, description will focus on the differences below.

The display unit <NUM>' may include a switching circuit <NUM>. The switching circuit <NUM> may be electrically connected to the data driving circuit <NUM> and a data line of a pixel. The switching circuit <NUM> may include a demultiplexer(s) demuxing a data signal output from the data driving circuit <NUM> and supplying the demuxed data signal to data lines.

The switching circuit <NUM> may be disposed between the third side of the display area DA and the first power supply wiring <NUM>. For example, the switching circuit <NUM> may be disposed between the first power supply wiring <NUM> and an auxiliary power supply wiring <NUM>. The first power supply wiring <NUM> and the auxiliary power supply wiring <NUM> may be spaced apart from each other with the switching circuit <NUM> therebetween.

The switching circuit <NUM> may overlap with a third shielding layer <NUM> and a fourth shielding layer <NUM> on the scan driving circuit <NUM>. A third width W3 of the third shielding layer <NUM> and a fourth width W4 of the fourth shielding layer <NUM> may be each equal to or greater than a width of the switching circuit <NUM>. The third width W3 and the fourth width W4 may be greater than the width of the switching circuit <NUM>, as illustrated in <FIG>.

As illustrated in <FIG>, the third shielding layer <NUM> may be disposed above the switching circuit <NUM> with the first insulating layer <NUM> therebetween, and the fourth shielding layer <NUM> may be disposed above the third shielding layer <NUM> with the second insulating layer <NUM> therebetween. As described with reference to <FIG>, the third shielding layer <NUM> may be disposed on a same layer level as and include a same material as a second driving voltage line (PL2, see <FIG>), and the fourth shielding layer <NUM> may be disposed on a same level as and include a same material as a pixel electrode (<NUM>, see <FIG>).

At least one of the third shielding layer <NUM> and the fourth shielding layer <NUM> may include a hole. One shielding layer of the third and fourth shielding layers <NUM> and <NUM> that includes the hole may overlap the other shielding layer.

The third shielding layer <NUM> may have holes <NUM> and a portion 2170P having a predetermined area. The fourth shielding layer <NUM> may have fourth holes <NUM> and a portion 2270P having a predetermined area. Each of the third and fourth holes <NUM> and <NUM> may serve as an outgassing passage of the first and second insulating layers <NUM> and <NUM> disposed under the third and fourth shielding layers <NUM> and <NUM>.

The third holes <NUM> and the fourth holes <NUM> may be arranged to be offset from each other. As illustrated in <FIG>, a center of the third hole <NUM> and a center of the fourth hole <NUM> may be offset from each other and not coincident with each other. The third hole <NUM> and the fourth hole <NUM> may not overlap each other. For example, the third hole <NUM> of the third shielding layer <NUM> may overlap with a portion 2270P of the fourth shielding layer <NUM>, and the fourth hole <NUM> of the fourth shielding layer <NUM> overlaps with a third portion 2170P of the third shielding layer <NUM>. Thus, when projected in a direction perpendicular to the main surface of the substrate <NUM>, the switching circuit <NUM> may be entirely covered by the third and fourth shielding layers <NUM> and <NUM>.

The third and fourth shielding layers <NUM> and <NUM> may have a same voltage level. The third and fourth shielding layers <NUM> and <NUM> may be electrically connected to the first power supply wiring <NUM>, as illustrated in <FIG>. The third and fourth shielding layers <NUM> and <NUM> may electrically connect the first power supply wiring <NUM> and the auxiliary power supply wiring <NUM>. The third shielding layer <NUM> may contact the first power supply wiring <NUM> and the auxiliary power supply wiring <NUM> through a first contact hole 206H1 and a second contact hole 206H2 of the first insulating layer <NUM>. The fourth shielding layer <NUM> may contact the third shielding layer <NUM> through a third contact hole 207H1 and a fourth contact hole 207H2 of the second insulating layer <NUM>. The first power ELVDD (<FIG>) of the first power supply wiring <NUM> may be supplied to driving voltage lines of a pixel connected to the auxiliary power supply wiring <NUM>.

A signal line of the input sensor <NUM> may be disposed on the switching circuit <NUM>. First signal lines <NUM>-<NUM> and <NUM>-<NUM> may be arranged on the peripheral area PA, as illustrated in <FIG>. At least one of the first signal lines <NUM>-<NUM> and <NUM>-<NUM> may overlap the switching circuit <NUM>. The third and fourth shielding layers <NUM> and <NUM> having the above-described structure may be interposed between the switching circuit <NUM> and the first signal lines <NUM>-<NUM> and <NUM>-<NUM>. Accordingly, an undesirable impact of a signal generated in the switching circuit <NUM> on the first signal lines <NUM>-<NUM> and <NUM>-<NUM> may be prevented or minimized.

In some implementations, a display unit <NUM>" may include the encapsulation member <NUM>' described above with reference to <FIG> instead of a thin film encapsulation layer.

<FIG> illustrate that shielding layers on the switching circuit <NUM>, for example, the third and fourth shielding layers <NUM> and <NUM> are provided with a voltage corresponding to the first power ELVDD. In some implementations, shielding layers on the switching circuit <NUM> may be provided with a voltage corresponding to the second power ELVSS.

<FIG> illustrates a plan view schematically illustrating a display unit <NUM>" according to another embodiment, and <FIG> illustrates a partial plan view of a switching circuit <NUM> of <FIG> and a portion around the switching circuit <NUM>. <FIG> illustrates a cross-sectional view illustrating a display device according to another embodiment, in which a display unit and an input sensor overlap each other. <FIG> corresponds to a cross-section taken along line XV-XV' of <FIG>.

The display unit <NUM>" of <FIG> further includes the switching circuit <NUM> as a third peripheral circuit. The display unit <NUM>" of <FIG> is substantially the same as the display unit <NUM> described above with reference to <FIG>, except that first and second shielding layers <NUM>' and <NUM>' extend onto the switching circuit <NUM> Thus, descriptions thereof will focus on the differences below.

The first and second shielding layers <NUM>' and <NUM>' may surround the display area DA entirely, as shown in <FIG>. For example, the first and second shielding layers <NUM>' and <NUM>' may be disposed to overlap the scan driving circuit <NUM>, the control driving circuit <NUM>, and the switching circuit <NUM>. A portion of the first and second shielding layers <NUM>' and <NUM>' overlapping the scan driving circuit <NUM> and the control driving circuit <NUM> may have a structure as described with reference to <FIG>, and thus, the description provided with reference to <FIG> and the like may be referred to regarding the structure. Hereinafter, overlapping between the first and second shielding layers <NUM>' and <NUM>' and the switching circuit <NUM> will be described.

The first and second shielding layers <NUM>' and <NUM>' may be disposed on the switching circuit <NUM>. A first width W1' of the first shielding layer <NUM>' and a second width W2 'of the second shielding layer <NUM>', each overlapping with the switching circuit <NUM>, may be equal to or greater than a width of the switching circuit <NUM>. In <FIG>, the first width W1' and the second width W2' may be greater than the width of the switching circuit <NUM>.

As illustrated in <FIG>, the first shielding layer <NUM>' may be disposed on the switching circuit <NUM> with the first insulating layer <NUM> therebetween, and the second shielding layer <NUM>' may be disposed on the first shielding layer <NUM>' with the second insulating layer <NUM> therebetween.

At least one of the first shielding layer <NUM>' and the second shielding layer <NUM>' may include a hole. One shielding layer of the first and second shielding layers <NUM>' and <NUM>' that includes the hole may overlap the other shielding layer.

According to an embodiment, as illustrated in <FIG>, the first shielding layer <NUM>' may include first holes <NUM>' and a portion 1170P' having a predetermined area, and the second shielding layer <NUM>' may include second holes <NUM>' and a portion 1270P' having a predetermined area.

The first holes <NUM>' and the second holes <NUM>' may be arranged to be offset from each other. As illustrated in <FIG>, a center of the first hole <NUM>' and a center of the second hole <NUM>' may be offset from each other and not coincident with each other. The first hole <NUM>' and the second hole <NUM>' may not overlap each other. The first hole <NUM>' of the first shielding layer <NUM>' overlaps with the portion 1270P' of the second shielding layer <NUM>', and the second hole <NUM>' of the second shielding layer <NUM>' overlaps with the portion 1170P' of the first shielding layer <NUM>'. Thus, when projected in a direction perpendicular to a main surface of the substrate <NUM>, the switching circuit <NUM> may be entirely covered by the first and second shielding layers <NUM>' and <NUM>'.

The first and second shielding layers <NUM>' and <NUM>' may be electrically connected to the second connection wiring <NUM> as illustrated in <FIG>, as described above with reference to <FIG> and <FIG>.

A signal line of the input sensor may be disposed on the switching circuit <NUM>. In this regard, <FIG> illustrates first signal lines <NUM>-<NUM> and <NUM>-<NUM> arranged on the peripheral area PA. At least one of the first signal lines <NUM>-<NUM> and <NUM>-<NUM> may overlap with the switching circuit <NUM>. The first and second shielding layers <NUM>' and <NUM>' may be interposed between the switching circuit <NUM> and the first signal lines <NUM>-<NUM> and <NUM>-<NUM>. Accordingly, impact of a signal generated in the switching circuit <NUM> on the first signal lines <NUM>-<NUM> and <NUM>-<NUM> may be prevented or minimized.

A thin film encapsulation layer is illustrated as the encapsulation member <NUM> in <FIG>. In some implementations, the display unit <NUM>" may include the encapsulation member <NUM>' described above with reference to <FIG>, instead of a thin film encapsulation layer.

As discussed, embodiments of the invention can provide a display device, comprising: a substrate including a display area and a peripheral area outside the display area; a display element in the display area; a peripheral circuit in the peripheral area, the peripheral circuit including a thin film transistor; a first shielding layer over the peripheral circuit; and a second shielding layer over the first shielding layer, wherein at least one of the first shielding layer and the second shielding layer includes a hole. The first shielding layer and the second shielding layer may overlap. The first shielding layer and the second shielding layer may be provided to prevent or reduce damage as a result of external electrostatic discharge (ESD).

In some embodiments, the first shielding layer includes a first hole, the second shielding layer includes a second hole. A center of the first hole and a center of the second hole may be spaced apart from each other. In some embodiments, the first hole and the second hole are arranged not overlap each other, with the first hole overlapping a portion of the second shielding layer, and the second hole overlapping a portion of the first shielding layer.

The first shielding layer may include a plurality of first holes and the second shielding layer may include a plurality of second holes. The first holes and the second holes may be arranged to be offset from each other in a plan view. The first holes may be spaced apart from one another on a plane, and the second holes may be spaced apart from one another on a plane.

One or more insulating layers may be disposed under the first and second shielding layers. Each of the first and second holes may be an outgassing passage of the one or more insulating layers disposed under the first and second shielding layers.

An input sensor may be provided that includes sensing electrodes and signal lines, wherein: the sensing electrodes are located in the display area, and the signal lines are located in the peripheral area and electrically connected to the sensing electrodes. In some embodiments, at least one of the signal lines overlaps the peripheral circuit. In some embodiments the first shielding layer and the second shielding layer are interposed between the at least one of the signal lines and the peripheral circuit.

The first and second shielding layers are connected to wiring and are provided with a same voltage level.

In some embodiments, the first shielding layer may be disposed on a same level as and include a same material as a driving voltage line of the display device. The second shielding layer may be disposed on a same level as and include a same material as a pixel electrode of the display device.

The peripheral circuit may comprise a scan driving circuit. A first width of the first shielding layer and a second width of the second shielding layer may be equal to or greater than a width of the scan driving circuit.

Embodiments of the invention can provide a display device comprising: a substrate including a display area and a peripheral area outside the display area; a display element including a pixel electrode electrically connected to a thin film transistor located in the display area; an input sensor including sensing electrodes and signal lines, wherein the sensing electrodes are located in the display area, and the signal lines are connected to the sensing electrodes and located in the peripheral area; a peripheral circuit in the peripheral area; and a first shielding layer and a second shielding layer each located in the peripheral area, the first shielding layer and the second shielding layer being interposed between the peripheral circuit and the signal lines.

A first insulating layer may be provided under the first shielding layer and a second insulating layer may be provided under the second shielding layer, wherein the second insulating layer is between the first shielding layer and the second shielding layer. In some embodiments, at least one of the first insulating layer and the second insulating layer includes an organic insulating material. At least one of the first shielding layer and the second shielding layer may include a hole.

In some embodiments, the first shielding layer includes a first hole, the second shielding layer includes a second hole. A center of the first hole and a center of the second hole may be spaced apart from each other. In some embodiments, the first hole and the second hole are arranged not overlap each other, with the first hole overlapping a portion of the second shielding layer, and the second hole overlapping a portion of the first shielding layer. The first shielding layer may include a plurality of first holes and the second shielding layer may include a plurality of second holes. The first holes and the second holes may be arranged to be offset from each other in a plan view. The first holes may be spaced apart from one another on a plane, and the second holes may be spaced apart from one another on a plane.

By way of summation and review, display devices include various circuits for providing an image. The circuits may be arranged in an area, generally referred to as a peripheral area or "dead zone" outside of the area where the image is provided.

If general effort were to be made to reduce a size of the dead zone, a circuit arranged in a dead zone of a display device might overlap with various wirings, giving rise to the possibility that the circuit arranged in the dead zone could be damaged when the circuit is exposed to external static electricity. In addition, signal interference caused the circuit and wirings could decrease the quality of the display device.

One or more embodiments include a display device that prevents damages to circuits and also signal interference with other wirings (for example, signal lines of an input sensor).

According to embodiments, damage to the display device may be prevented or minimized through outgassing of the organic insulating layer, and damage to the peripheral circuit due to static electricity or the like may be prevented or minimized, or interference of signal lines of the input sensor due to a signal of the peripheral circuit may be prevented or minimized. Accordingly, a high-quality display device may be provided.

Claim 1:
A display device (<NUM>), comprising:
a substrate (<NUM>) including a display area (DA) and a peripheral area (PA) outside the display area;
a display element (<NUM>) in the display area, the display element including a pixel electrode (<NUM>), a light emission layer, and an opposite electrode (<NUM>) that are sequentially stacked;
a first power voltage wiring (<NUM>) located in the peripheral area and providing a first power to a thin film transistor that is electrically connected to the display element and located in the display area;
a second connection wiring (<NUM>) located in the peripheral area and electrically connected to the opposite electrode to provide a second power to the display element, the second power being different from the first power;
a peripheral circuit in the peripheral area, the peripheral circuit including a thin film transistor (TFT);
a first shielding layer (<NUM>, <NUM>') over the peripheral circuit; and a
second shielding layer (<NUM>, <NUM>') over the first shielding layer, the second shielding layer overlapping the first shielding layer,
wherein the first shielding layer includes a first hole (<NUM>) and the second shielding layer includes a second hole (<NUM>),
wherein an end of the opposite electrode extends to the peripheral area to cover the peripheral circuit,
wherein the first and second shielding layers (<NUM>, <NUM>) are electrically connected to the second connection wiring (<NUM>) so as to have a same voltage level as each other,
wherein the second connection wiring is electrically connected to the opposite electrode via the second shielding layer,
wherein the first shielding layer and the second shielding layer are interposed between the peripheral circuit and the end of the opposite electrode.