Patent Description:
An amplifier, such as an operational or instrumentation amplifier, can include chopper circuitry to help compensate for the amplifier's input offset voltage. For example, a chopper amplifier can include an input chopping circuit that can be used to chop the amplifier's input signal during an input chopping operation, thereby up-shifting the frequency of the amplifier's input signal. The chopper amplifier can further include an amplification circuit for amplifying the chopped input signal, and an output chopping circuit for down-shifting the frequency of the amplified signal during an output chopping operation. By providing chopping in this manner, the amplifier's input offset voltage is separated in frequency from the chopped input signal, and thus can be filtered or otherwise attenuated. <CIT> discloses an amplifier circuit with chopper circuits for offset voltage cancellation. <CIT> discloses an operational amplifier <NUM> having input chop circuit responsive to a control signal. <CIT> discloses an amplifier circuit having a chopper circuit and an autozeroing function with an autozeroed input stage, where the input transconductors forming the amplifier are alternatively auto-zeroed.

Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two pairs of input transistors. Accordingly, the selected pair of input transistors can be changed with little to no delay in the offset correction circuit compensating for input offset and suppressing chopping ripple. In particular, because the offset correction circuit separately tracks the input offset of each pair of input transistors, the input offset compensation signal can be quickly updated to a suitable signal value for compensation in response to a change in the selected pair of input transistors.

In one aspect, chopper amplifier with tracking of multiple input offsets is provided according to claim <NUM>.

In another aspect, a method of amplification is provided according to claim <NUM>.

input offset of each of the two or more pairs of input transistors, and to generate an input offset compensation signal for compensating the amplification circuit.

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention.

Absent compensation, an amplifier can have an input offset voltage and/or low frequency noise, such as flicker or <NUM>/f noise having an associated noise power spectral density (PSD) that becomes larger at lower frequencies.

To reduce or remove input offset voltage and/or low frequency noise, an amplifier can include chopper circuitry. An amplifier with chopper circuitry is referred to as a chopper amplifier. In one example, a chopper amplifier includes an input chopping circuit that chops or modulates the amplifier's input signal during an input chopping operation, thereby up-shifting the frequency of the amplifier's input signal. Furthermore, the chopper amplifier includes an amplification circuit that amplifies the chopped input signal, and an output chopping circuit that chops or demodulates the amplified signal during an output chopping operation. By providing chopping in this manner, the amplifier's input offset voltage and/or low frequency noise is separated in frequency from the desired signal, and thus can be filtered or otherwise attenuated.

In certain implementations, a chopper amplifier can further include autozero circuitry. Including both autozero and chopper circuitry in a chopper amplifier can further lower overall input offset voltage and/or low frequency noise. The teachings herein are applicable not only to chopper amplifiers that provide chopping, but also to chopper amplifiers that combine chopping with autozeroing and/or other compensation schemes.

An amplifier's chopping operations can result in ripple appearing in the amplifier's output voltage. The chopping ripple can have a magnitude that changes in relation to the magnitude of the amplifier's input offset voltage and/or low frequency noise. Thus, chopping may result in the amplifier's input offset voltage and/or low frequency noise not being cancelled, but instead being modulated up by the chopping frequency to generate chopping ripple that corrupts the spectral integrity of the amplifier's output signal.

Although a low-pass post filter can be included after the output chopping circuit to filter chopping ripple associated with modulated input offset voltage and/or modulated low frequency noise, it can be desirable to reduce the amplifier's input offset voltage and/or low frequency noise to avoid a need for a post filter or to relax a design constraint of the post filter. In another example, a switched capacitor notch filter can be included after the output chopping circuit to provide attenuation of chopping ripple.

To provide input offset compensation and suppress chopping ripple, feedback and/or feedforward correction paths can be used. For example, such correction path(s) can be used to generate an input offset correction signal to compensate for input offset prior to output chopping, thereby suppressing chopping ripple.

In certain applications, a chopper amplifier includes multiple pairs of input transistors, each of which can be selected for amplifying the input signal based on operating conditions and/or parameters. For example, certain chopper amplifiers operate over a wide range of input common-mode voltage, and thus include multiple pairs of input transistors for amplifying the input signal based on a detected input common-mode voltage. In particular, the chopper amplifier can include a pair of n-type input transistors for amplifying the input signal over an upper portion of the input common-mode voltage range, and a pair of p-type input transistors for amplifying the input signal over a lower portion of the input common-mode voltage range. In contrast, a chopper amplifier with only a single pair of input transistors may have insufficient voltage headroom to operate over a wide input common-mode voltage range, for instance, rail-to-rail operation.

When transitioning from using one pair of input transistors to another pair of input transistors, the chopper amplifier's offset correction circuitry can have a delay in properly compensating for the input offset of the newly selected pair of input transistors. For example, each input transistor pair of the chopper amplifier can have a different input offset voltage, and thus when the selected pair of input transistors changes, an input offset correction signal generated by the offset correction circuitry can have a delay in settling to a steady-state value suitable for properly compensating the newly selected pair.

Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.

Accordingly, the selected pair of input transistors can be changed with little to no delay in the offset correction circuit compensating for input offset and suppressing chopping ripple. In particular, because the offset correction circuit separately tracks the input offset of each pair of input transistors, the input offset compensation signal can be quickly updated to a suitable signal value for compensation in response to a change in the selected pair of input transistors.

In certain implementations, the two or more pairs of input transistors includes a pair of p-type input transistors and a pair of n-type input transistors, and the control circuit determines whether to use the pair of p-type input transistors or the pair of n-type input transistors based on sensing an input common-mode voltage of the chopper amplifier. For example, the control circuit can use the pair of n-type input transistors over a first range of input common-mode voltage, and use the pair of p-type input transistors over a second range of input common-mode voltage. As the input common-mode voltage changes, the selection of the pair of n-type input transistors or the pair of p-type input transistors can also change. Furthermore, since the input offset of the n-type input transistors and the input offset of the p-type input transistors are separately tracked, the input offset compensation signal can be quickly updated to a proper signal level when the selected pair of input transistors changes. Thus, seamless or near seamless switching between the n-type input transistors and the p-type input transistors is achieved.

The pairs of input transistors can correspond to a wide variety of transistor types including, but not limited to, field-effect transistors (FETs), such as metal-oxide-semiconductor (MOS) transistors. MOS transistors can be associated with a wide variety of manufacturing processes including not only bulk complementary MOS (CMOS) processes, but also triple well CMOS processes, silicon on insulator (SOI) processes, double-diffused MOS (DMOS) processes, as well as a wide range of other manufacturing processes. In certain implementations, the two or more pairs of input transistors include a pair of n-type MOS (NMOS) transistors, such as n-type DMOS transistors, and a pair of p-type MOS (PMOS) transistors, such as p-type DMOS transistors.

The offset correction circuit can be implemented in a wide variety of ways. In certain implementations, the offset correction circuit includes digital circuitry used to separately track the input offset of two or more pairs of input transistors. Using digital circuitry can provide a number of advantages.

In a first example, the digital circuitry can include a non-volatile memory for storing digital data representing the input offset voltages of each pair of input transistors of the amplification circuit. Thus, after a power cycle of the chopper amplifier in which the chopper amplifier is powered down and then powered back up, the chopper amplifier can quickly resume precision amplification using any selected pair of input transistors. In contrast, a chopper amplifier without such a feature can have a long delay at start-up in settling to a steady-state signal value suitable for input offset compensation.

In a second example, the digital circuitry is coupled to a digital interface (for instance, a serial interface or parallel interface of a semiconductor die or chip), which allows the digital data to be observed off-chip and/or for digital data to be loaded into the chopper amplifier after power-up to achieve input offset compensation with little to no delay.

In a third example, the digital circuitry can hold input offset correction data for an indefinite amount of time without having a chopping clock signal toggle. Thus, the user can stop and resume the chopping clock signal at any time and after any duration. Furthermore, a particular pair of input transistors can remain unused for a long period of time without impacting the ability of the digital circuitry to store input offset correction data for that pair. In contrast, analog circuitry can be subject to leakage currents and/or noise that necessitates the analog circuitry to be regularly operated with the chopping clock signal to maintain proper input offset compensation.

The offset correction circuits herein can be used not only to compensate for input offset voltage of two or more pairs of input transistors of an amplification circuit, but also to reduce or eliminate other low frequency input noise sources, such as flicker noise. This in turn leads to reduced output chopping ripple, lower flicker noise current, and/or enhanced spectral output purity of the chopper amplifier.

<FIG> is a schematic diagram of a chopper amplifier <NUM> according to one embodiment. The chopper amplifier <NUM> includes chopper amplifier circuitry <NUM> and an offset correction circuit <NUM> for compensating for an input offset voltage of the chopper amplifier circuitry <NUM> while suppressing output chopping ripple.

As shown in <FIG>, the chopper amplifier <NUM> receives a differential input signal between a positive or non-inverted input voltage terminal VIN+ and a negative or inverted input voltage terminal VIN-, which operate as a pair of differential input terminals VIN+, VIN-. The chopper amplifier <NUM> also outputs a differential output signal between a positive or non-inverted output voltage terminal VIN+ and a negative or inverted output voltage terminal VIN-, which operate as a pair of differential output terminals VOUT+, VOUT-.

Although <FIG> illustrates a configuration in which the chopper amplifier <NUM> generates a differential output signal, the chopper amplifier <NUM> can be adapted to generate other output signals, including, for example, a single-ended output signal. Additionally, although <FIG> illustrates the chopper amplifier <NUM> in an open-loop configuration, the chopper amplifier <NUM> can be used in closed-loop configurations.

In the illustrated embodiment, the chopper amplifier circuitry <NUM> includes an input chopping circuit <NUM>, an amplification circuit <NUM>, and an output chopping circuit <NUM>, which are electrically connected in a cascade along a signal path, with the amplification circuit <NUM> between the input chopping circuit <NUM> and the output chopping circuit <NUM>. The chopper amplifier circuitry <NUM> further includes a control circuit, corresponding to a common-mode detection circuit <NUM>, in this embodiment.

Although certain components of the chopper amplifier circuitry <NUM> are shown, the chopper amplifier circuitry <NUM> can include additional components or circuits, including, but not limited to, one or more additional amplification stages, output stages, feedforward paths, and/or feedback paths. Accordingly, other implementations are possible.

The input chopping circuit <NUM> operates to chop or modulate the differential input signal to generate a chopped differential input signal, which is amplified by the amplification circuit <NUM> to generate an amplified differential signal. The chopping operation of the input chopping circuit <NUM> upshifts the frequency of the differential input signal. For example, in certain implementations the chopping clock signal of the input chopping circuit <NUM> is a square wave, which can be equivalently represented by a Fourier series of sine waves at the chopping frequency and at odd harmonics thereof. By modulating the differential input signal by such a square wave, the frequency content of the differential input signal is upshifted. Accordingly, the chopped differential input signal includes signal content at the chopping frequency and odd harmonics thereof. Thus, the chopped differential input signal is separated in frequency from input offset voltage and/or low frequency noise of the amplification circuit <NUM>.

As shown in <FIG>, the amplification circuit <NUM> includes multiple pairs of input transistors, corresponding to a pair of n-type input transistors <NUM> and a pair of p-type input transistors <NUM>, in this embodiment. Each of the pairs of input transistors are individually selectable by the chopper amplifier circuitry's control circuit, and can have different input offsets.

In certain implementations, the input chopping circuit <NUM> includes separate sets of input chopping switches for each pair of input transistors of the amplification circuit <NUM>. In other implementations, a shared set of chopping switches is used for the pairs of input transistors.

In the illustrated embodiment, the common-mode detection circuit <NUM> generate a first enable signal NEN for selecting the pair of n-type input transistors <NUM> for amplification, and a second enable signal PEN for selecting the pair of p-type input transistors <NUM> for amplification. The common-mode detection circuit <NUM> chooses the selected pair of input transistors based on a sensed input common-mode voltage, in this embodiment. For example, due to limitations arising from supply voltage headroom, the pair of n-type input transistors <NUM> is well-suited for providing amplification at high input common-mode voltage (for instance, near VDD), while the pair of p-type input transistors <NUM> is well-suited for providing amplification at low input common-mode voltage (for instance, near Vss).

Accordingly, in certain implementations, the common-mode detection circuit <NUM> activates the pair of n-type input transistors <NUM> and deactivates the pair of p-type input transistors <NUM> when the detected input common-mode voltage is high, and activates the pair of p-type input transistors <NUM> and deactivates the pair of n-type input transistors <NUM> when the detected input common-mode voltage is low. For a middle band of input common-mode voltage, the common-mode detection circuit <NUM> can activate either the n-type input transistors <NUM> or the p-type input transistors <NUM>, based on implementation.

The selected pair of input transistors amplifies the chopped differential input signal to generate the amplified differential signal. The amplified differential signal is chopped by the output chopping circuit <NUM>, thereby downshifting signal frequency content. The chopped differential output signal can be outputted with or without further processing (for instance, amplification, filtering and/or integration) to generate the differential output signal of the chopper amplifier <NUM>.

The chopper amplifier <NUM> further includes the offset correction circuit <NUM>, which senses the signal path through the chopper amplifier circuitry <NUM> at one or more points or positions. Additionally, the offset correction circuit <NUM> injects an input offset voltage compensation signal into the signal path of the chopper amplifier circuitry <NUM> to compensate for input offset voltage and to suppress chopping ripple.

In the illustrated embodiment, the offset correction circuit <NUM> separately tracks the input offset of each pair of input transistors of the amplification circuit <NUM>. In particular, the offset correction circuit <NUM> includes a first tracking circuit <NUM> for tracking the input offset of the pair of n-type input transistors <NUM>, and a second tracking circuit <NUM> for tracking the input offset of the pair of p-type input transistors <NUM>. Although depicted as separate components, the first tracking circuit <NUM> and the second tracking circuit <NUM> can share certain circuitry, for instance, a portion of the offset correction circuit <NUM> used for sensing, amplifying, chopping, and/or other processing.

As shown in <FIG>, the offset correction circuit <NUM> receives the first enable signal NEN and the second enable signal PEN from the common-mode detection circuit <NUM>. The first enable signal NEN and the second enable signal PEN can be used to activate tracking operations of the first tracking circuit <NUM> and the second tracking circuit <NUM>, respectively. Accordingly, suitable input offset correction and chopping ripple suppression is provided for the selected pair of input transistors of the amplification circuit <NUM>.

In certain implementations, the input offset compensation signal is injected into a portion of the signal path of the chopper amplifier circuitry <NUM> between the amplification circuit <NUM> and the output chopping circuit <NUM>. By compensating for such low frequency noise prior to output chopping, generation of chopping voltage ripple in the differential output signal is reduced or eliminated.

<FIG> is a schematic diagram of a chopper amplifier <NUM> according to another embodiment. The chopper amplifier <NUM> includes chopper amplifier circuitry <NUM> and an offset correction circuit <NUM>.

The chopper amplifier <NUM> of <FIG> is similar to the chopper amplifier <NUM> of <FIG>, except that the chopper amplifier <NUM> of <FIG> includes a different implementation of an offset correction circuit. In particular, the offset correction circuit <NUM> of <FIG> includes a sense amplifier <NUM>, a resistor <NUM>, a chopping circuit <NUM>, an analog-to-digital converter (ADC) <NUM>, a digital circuit <NUM>, and a digital-to-analog converter (DAC) <NUM>. Additionally, the digital circuit <NUM> includes an n-type tracking circuit <NUM> and a p-type tracking circuit <NUM>.

In the illustrated embodiment, the sense amplifier <NUM> includes a differential input coupled to a sensing point along the signal path of the chopper amplifier circuitry <NUM>. In certain implementations, the sensing point is along the signal path after the output chopping circuit <NUM>. However, the teachings herein are applicable to offset correction circuits that sense input offset in a wide variety of ways.

As shown in <FIG>, an output signal from the sense amplifier <NUM> is provided to the chopping circuit <NUM>. In certain implementations, the output signal from the sense amplifier <NUM> is a current that flows through the resistor <NUM> to generate an input voltage signal for the chopping circuit <NUM>. The chopping circuit <NUM> generates an output signal, which is digitized by the ADC <NUM> and processed by the digital circuit <NUM> to generate digital correction data.

The digital correction data is used by the DAC <NUM> to generate a differential input offset compensation signal provided to the chopper amplifier circuitry <NUM>. In certain implementations, the differential input offset compensation signal is provided to a differential output of the amplification circuit <NUM> to compensate for the input offset voltage of the selected pair of input transistors of the amplification circuit <NUM>.

With continuing reference to <FIG>, the offset correction circuit <NUM> receives the first enable signal NEN and the second enable signal PEN from the common-mode detection circuit <NUM>. The first enable signal NEN and the second enable signal PEN are used to activate tracking operations of the first tracking circuit <NUM> and the second tracking circuit <NUM>, respectively.

Accordingly, when the common-mode detection circuit <NUM> changes the selected pair of input transistors from the p-type pair <NUM> to the n-type pair <NUM>, or vice versa, the corresponding digital tracking circuit of the offset correction circuit <NUM> is activated. Accordingly, the digital correction data provided to the DAC <NUM> is updated, such that the differential input offset compensation signal provided to the chopper amplifier circuitry <NUM> is at a suitable signal level for compensating for the input offset of the selected pair of input transistors. Thus, the selected pair of input transistors can be switched with little to no delay and without impacting an ability of the chopper amplifier <NUM> to provide precision amplification with low input offset.

The chopper amplifier <NUM> of <FIG> is similar to the chopper amplifier <NUM> of <FIG>, except that the offset correction circuit <NUM> of <FIG> omits the chopping circuit <NUM> shown in <FIG>. Additionally, the offset correction circuit <NUM> includes a digital circuit <NUM> that provides digital chopping <NUM>. Any of the offset correction circuits herein can be adapted to operate with digital chopping.

The chopper amplifier <NUM> of <FIG> is similar to the chopper amplifier <NUM> of <FIG>, except that the offset correction circuit <NUM> of <FIG> includes a digital circuit <NUM> that includes a non-volatile memory (NVM) <NUM>. The NVM <NUM> is used to store digital data indicating signal values of the differential input offset compensation signal when tracking the pair of n-type input transistors <NUM> and when tracking the pair of p-type input transistors <NUM>.

By including the NVM <NUM>, the chopper amplifier <NUM> can quickly resume amplification after a power cycle. Such a power cycle can correspond to a ramp down and ramp up of the chopper amplifier's supply voltage, and/or a power down signal (PWR_DN) can be used to turn on and off the chopper amplifier <NUM>. By including the NVM <NUM>, data indicating the signal values for input offset compensation of each transistor pair is not lost during the power cycle. Thus, a start-up delay in settling to a steady-state signal value for input offset compensation is avoided. Furthermore, either the pair of n-type input transistors <NUM> or the pair of p-type input transistors <NUM> can be used after the power cycle.

The chopper amplifier <NUM> of <FIG> is similar to the chopper amplifier <NUM> of <FIG>, except that the offset correction circuit <NUM> of <FIG> includes a digital circuit <NUM> coupled to a digital interface and that includes a memory <NUM>, which can be volatile or non-volatile. The memory <NUM> is used to store digital data indicating signal values of the differential input offset compensation signal for tracking the n-type pair <NUM> and the p-type pair <NUM>. The memory <NUM> can be read from or written to using the digital interface, which can correspond to a serial interface or parallel interface of a semiconductor chip on which the chopper amplifier <NUM> is fabricated.

Implementing the digital circuit <NUM> to communicate over the digital interface allows the digital data to be observed off-chip and/or for digital data to be loaded into the chopper amplifier <NUM> after power-up or a power cycle to achieve input offset compensation with little to no delay.

The chopper amplifier <NUM> of <FIG> is similar to the chopper amplifier <NUM> of <FIG>, except that the offset correction circuit <NUM> of <FIG> further includes a second sense amplifier <NUM>. Thus, the offset correction circuit <NUM> senses the signal path of the chopper amplifier circuitry <NUM> at multiple points or positions.

In the illustrated embodiment, the first sense amplifier <NUM> includes a differential input coupled to a first sensing point along the signal path of the chopper amplifier circuitry <NUM>, while the second sense amplifier <NUM> includes a differential input coupled to a second sensing point along the signal path of the chopper amplifier circuitry <NUM>. In certain implementations, the first sensing point is before the input chopping circuit <NUM>, while the second sensing point is after the output chopping circuit <NUM>.

The first sense amplifier <NUM> and the second sense amplifier <NUM> can each include one or more stages. In certain implementations, an input stage of the first sense amplifier <NUM> includes a replica of the n-type pair <NUM> and a replica of the p-type pair <NUM>, with or without scaling.

As shown in <FIG>, an output signal from the first sense amplifier <NUM> and an output signal from the second sense amplifier <NUM> are combined, and thereafter chopped using the chopping circuit <NUM> to generate a combined sense signal that is inputted to the ADC <NUM>. In certain implementations, the output signal from the first sense amplifier <NUM> and the output signal from the second sense amplifier <NUM> correspond to currents that flow through the resistor <NUM> to generate an input voltage signal for the chopping circuit <NUM>.

The input offset correction circuits herein can be implementing using a wide variety of sensing configurations, including configurations using one or more feedback paths, one or more feedforward paths, or a combination thereof.

<FIG> is a schematic diagram of a chopper amplifier <NUM> according to another embodiment. The chopper amplifier <NUM> includes chopper amplifier circuitry <NUM> and an offset correction circuit <NUM>. The chopper amplifier <NUM> further includes a pair of differential input terminals VIN+, VIN- for receiving a differential input voltage VSig, and a single-ended output terminal VOUT for outputting a single-ended output voltage.

In the illustrated embodiment, the chopper amplifier circuitry <NUM> includes a common-mode detection circuit <NUM>, an input chopping circuit <NUM> (controlled by a chopping clock signal CLKCHOP), a p-type transconductance amplifier Gm1p (including a p-type input pair having an input offset voltage represented by a voltage source VOSP), an n-type transconductance amplifier Gm1n (including an n-type input pair having an input offset voltage represented by a voltage source VOSN), an output chopping circuit <NUM> (controlled by the chopping clock signal CLKCHOP), a second transconductance amplifier Gm2, a first resistor RCA1, a second resistor RCA2, a first capacitor CCA, and a second capacitor CCB.

With continuing reference to <FIG>, the common-mode detection circuit <NUM> senses a common-mode input voltage of the pair of differential input terminals VIN+, VIN-, and enables one of the p-type transconductance amplifier Gm1p or the n-type transconductance amplifier Gm1n based on the sensed common-mode input voltage. The selected transconductance amplifier is enabled using a first enable signal NEN or a second enable signal PEN. The selected transconductance amplifier outputs a differential signal current Im1.

Although one embodiment of chopper amplifier circuitry <NUM> is depicted, the teachings herein are applicable to chopper amplifier circuitry implemented in a wide variety of ways. Accordingly, other implementations are possible.

With continuing reference to <FIG>, the offset correction circuit <NUM> incudes a replica transconductance amplifier Gm1NRep, which corresponds to a replica of the n-type transconductance amplifier Gm1n, with or without scaling. The offset correction circuit <NUM> incudes a replica transconductance amplifier Gm1PRep, which corresponds to a replica of the p-type transconductance amplifier Gm1p, with or without scaling. The offset correction circuit <NUM> further includes a first resistor RCARep, which corresponds to a replica of the series combination of the first resistor RCA1 and the second resistor RCA2, with or without scaling.

The offset correction circuit <NUM> further includes a first sense transconductance amplifier GmS1, a second sense transconductance amplifier GmS2, a second resistor RS, a chopper circuit <NUM>, a comparator <NUM>, a digital circuit <NUM> (including a first counter <NUM> for Gm1n, a second counter <NUM> for Gm1p, and a multiplexer <NUM>), and a current DAC (iDAC) <NUM>. The comparator <NUM> serves as a <NUM>-bit ADC that generates an up signal and a down signal for controlling a state of the active counter of the digital circuit <NUM>. The digital circuit <NUM> outputs digital correction data selected by the multiplexer <NUM> from the first counter <NUM> or the second counter <NUM>. The digital correction data is used by the current DAC <NUM> to generate the differential correction current ICorr.

In the illustrated embodiment, the chopping circuit <NUM> is clocked by the chopping clock signal CLKCHOP, while the comparator <NUM> is clocked by the comparator clock signal CLKCOMP, and the digital circuit <NUM> is clocked by the counter clock signal CLKCOUNT. In certain implementations, the comparator clock signal CLKCOMP and/or the counter clock signal CLKCOUNT are generated by delaying the chopping clock signal CLKCHOP or a divided version thereof. In the example of <FIG>, the current DAC <NUM> responds to a change in the digital correction data rather than being driven by a clock signal. Although one example of clocking is depicted, an offset correction circuit can be clocked in a wide variety of ways.

With continuing reference to <FIG>, the first enable signal NEN and the second enable signal PEN are provided to the offset correction circuit <NUM> to aid in tracking the input offset of the selected pair of input transistors. For example, the first enable signal NEN is used to selectively enable Gm1NRep and the first counter <NUM>, while the second enable signal PEN is used to selectively enable Gm1PRep and the second counter <NUM>. Additionally, the multiplexer <NUM> uses the first enable signal NEN and the second enable signal PEN to select which counter output to provide as the digital correction data for the current DAC <NUM>.

As shown in <FIG>, the offset correction circuit <NUM> senses the signal path of the chopper amplifier circuitry <NUM> at both a differential input to the input chopping circuit <NUM> and across the series combination of the first resistor RCA1 and the second resistor RCA2 (corresponding to a voltage difference between VS2P and VS2N). Additionally, the offset correction circuit <NUM> injects the differential correction current ICorr into the chopper amplifier circuitry <NUM> such that the differential correction current ICorr is combined with the differential signal current Im1.

Using multiple sensing points provides a number of advantages, including, providing low input offset voltage when chopping and excellent gain versus frequency characteristics (including at a frequency used for chopping). However, the teachings herein are also applicable to implementations using a single sensing point.

Thus, although one embodiment of the offset correction circuit <NUM> is depicted, the teachings herein are applicable to offset correction circuits implemented in a wide variety of ways. Accordingly, other implementations are possible.

<FIG> is a schematic diagram of one embodiment of an amplification circuit <NUM> for a chopper amplifier.

The amplification circuit <NUM> includes a pair of NMOS input transistors <NUM>, a pair of PMOS input transistors <NUM>, a pair of PMOS isolation switches 103a, a pair of NMOS isolation switches 103b, first input chopping switches 104a, second input chopping switches 104b, a common-mode detection circuit <NUM>, a first group of current sources <NUM>, 108a, and 108b, a second group of current sources <NUM>, 110a, and 110b, a first cascode PMOS transistor 113a, a second cascode PMOS transistors 113b, a first cascode NMOS transistor 114a, a second cascode NMOS transistor 114b, a third group of current sources 115a and 115b, a fourth group of current sources 116a and 116b, a first voltage source <NUM>, and a second voltage source <NUM>. The amplification circuit <NUM> further includes a pair of input terminals (IN+, IN-) and a pair of output terminals (OUT+, OUT-), and is powered by a power high supply voltage VDD and a power low supply voltage Vss.

In the illustrated embodiment, the pair of NMOS input transistors <NUM> is implemented as a differential transistor pair including a first NMOS input transistor 121a and a second NMOS input transistor 121b, which each include a source connected to one another and biased with a common bias current IN from the current source <NUM>. Additionally, the drain of the first NMOS input transistor 121a is biased by a bias current IN/<NUM> from the current source 108a and the drain of the second NMOS input transistor 121b is biased by a bias current IN/<NUM> from the current source 108b.

The pair of PMOS isolation switches 103a include a first PMOS isolation switch 123a and a second PMOS isolation switch 123b. The drains of the PMOS isolation switches 123a-123b are connected to IN+ and IN-, respectively, while the sources of the PMOS isolation switches 123a-123b are connected to the gates of the NMOS input transistors 121a-121b, respectively, through the first input chopping switches 104a. The gates of the PMOS isolation switches 123a-123b are controlled by a first inverted enable signal NENB from the common-mode detection circuit <NUM>.

With continuing reference to <FIG>, the pair of PMOS input transistors <NUM> are implemented as a differential transistor pair including a first PMOS input transistor 122a and a second PMOS input transistor 122b, which each include a source connected to one another and biased with a common bias current IP from the current source <NUM>. Additionally, the drain of the first PMOS input transistor 122a is biased by a bias current IP/<NUM> from the current source 110a and the drain of the second PMOS input transistor 122b is biased by a bias current IP/<NUM> from the current source 110b.

The pair of NMOS isolation switches 103b include a first NMOS isolation switch 124a and a second NMOS isolation switch 124b. The drains of the NMOS isolation switches 124a-124b are connected to IN+ and IN-, respectively, while the sources of the NMOS isolation switches 124a-124b are connected to the gates of the PMOS input transistors 122a-122b, respectively, through the second input chopping switches 104b. The gates of the NMOS isolation switches 124a-124b are controlled by a second enable signal PEN from the common-mode detection circuit <NUM>.

In the illustrated embodiment, the common-mode detection circuit <NUM> is coupled to the pair of input terminals (IN+, IN-) to sense an input common-mode voltage. Based on the sensed input common-mode voltage, the common-mode detection circuit <NUM> selects the pair of NMOS input transistors <NUM> using a first enable signal NEN or the pair of PMOS input transistors <NUM> using the second enable signal PEN. The selected pair of input transistors amplifies the differential input signal received between IN+ and IN- after chopping by the first input chopping switches 104a or the second input chopping switches 104b.

As shown in <FIG>, the first input chopping switches 104a and the second input chopping switches 104b are each controlled by a chopping clock signal CLKCHOP. In the illustrated embodiment, separate sets of input chopping switches are used for the n-type input pair <NUM> and the p-type input pair <NUM>. In other embodiments, a shared set of chopping switches are used. Any of the embodiments herein can use shared or separate input chopping switches. Likewise, any of the embodiments herein can use shared or separate output chopping switches.

When the pair of NMOS input transistors <NUM> are being used, the common-mode detection circuit <NUM> turns on the pair of PMOS isolation transistors 103a and turns on the first group of current sources <NUM>, 108a, and 108b. However, when the pair of NMOS input transistors <NUM> are not being used, the common-mode detection circuit <NUM> turns off the pair of PMOS isolation transistors 103a and turns off the first group of current sources <NUM>, 108a, and 108b.

With continuing reference to <FIG>, when the pair of PMOS input transistors <NUM> are being used, the common-mode detection circuit <NUM> turns on the pair of NMOS isolation transistors 103b and turns on the second group of current sources <NUM>, 110a, and 110b. However, when the pair of PMOS transistors <NUM> are not being used, the common-mode detection circuit <NUM> turns off the pair of NMOS isolation transistors 103b and turns off the second group of current sources <NUM>, 110a, and 110b.

Including the PMOS isolation transistors 103a and the NMOS isolation transistors 103b aids in reducing input capacitance. However, the teachings herein are also application to implementations without isolation transistors.

An example of folded cascode circuitry is depicted as being coupled to the pair of NMOS input transistors <NUM> and the pair of PMOS input transistors <NUM>. The folded cascode circuitry illustrates one example of circuitry suitable for providing the output signal from the pair of NMOS input transistors <NUM> and the output signal from the pair of PMOS input transistors <NUM> to a common pair of output terminals (OUT+, OUT-). However, other implementations of circuitry are possible.

<FIG> is a schematic diagram of one example of chopping switches <NUM> that can be used in a chopper amplifier. However, chopping switches can be implemented in other ways.

As shown in <FIG>, the chopping switches <NUM> includes first and second inputs 201a, 201b that operate as a differential input, first and second outputs 202a, 202b that operate as a differential output, first to fourth switches 203a-203d, and a switch control circuit <NUM>. As shown in <FIG>, the switch control circuit <NUM> receives a chopping clock signal CLKCHOP, which can be used to control a state of the switches 203a-203d over time. Although illustrated as including the switch control circuit <NUM>, in certain configurations the switch control circuit <NUM> is omitted in favor of providing multiple clock signals (for example, inverted and non-inverted versions of a chopping clock signal, with or without non-overlap) to the chopping switches <NUM>.

The first input 201a is electrically connected to a first end of the first switch 203a and to a first end of the second switch 203b. The second input 201b is electrically connected to a first end of the third switch 203c and to a first end of the fourth switch 203d. The first output 202a is electrically connected to a second end of the second switch 203b and to a second end of the third switch 203c. The second output 202b is electrically connected to a second end of the first switch 203a and to a second end of the fourth switch 203d.

The chopping switches <NUM> can be used to chop a differential input signal received between the first and second inputs 201a, 201b to generate a differential chopped signal between the first and second outputs 202a, 202b. For example, during a first clock phase of the chopping clock signal CLKCHOP, the switch control circuit <NUM> can close the second and fourth switches 203b, 203d and open the first and third switches 203a, 203c. Additionally, during a second clock phase of the chopping clock signal CLKCHOP, the switch control circuit <NUM> can close the first and third switches 203a, 203c and open the second and fourth switches 203b, 203d.

The clock signals disclosed herein can be implemented in a wide variety of ways, including, for example, by using any suitable clock generator. In certain implementations, a common clock signal is used to synthesize clock signals used for chopping, auto-zeroing, digital processing, and/or other operations of a chopper amplifier.

Devices employing the above described schemes can be implemented into various electronic devices. Examples of electronic devices include, but are not limited to, consumer electronic products, electronic test equipment, communication systems, data converters, etc..

The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

Claim 1:
A chopper amplifier (<NUM>) with tracking of multiple input offsets, the chopper amplifier comprising:
an input chopping circuit (<NUM>) configured to chop a differential input signal to generate a chopped input signal;
an amplification circuit (<NUM>) configured to amplify the chopped input signal to generate an amplified signal, wherein the amplification circuit comprises two differential transistor pairs of input transistors (<NUM>,<NUM>) that are selectable, wherein the two differential transistor pairs of input transistors includes an n-type differential transistor pair (<NUM>) and a p-type differential transistor pair (<NUM>);
an output chopping circuit (<NUM>) configured to chop the amplified signal to generate a chopped output signal; and
a control circuit (<NUM>) configured to select the n-type differential transistor pair or the p-type differential transistor pair of input transistors from the two differential transistor pairs of input transistors based on sensing an input common-mode voltage of the chopper amplifier (<NUM>), wherein the selected differential transistor pair of input transistors is configured to amplify the chopped input signal; and
an offset correction circuit (<NUM>) comprising a feedback loop coupled to the output chopping circuit and configured to generate an input offset compensation signal for the chopper amplifier circuitry to suppress a chopping ripple, wherein the offset correction circuit separately tracks an input offset of each of the two differential transistor pairs of input transistors (<NUM>,<NUM>) and wherein the offset correction circuit (<NUM>) comprises respective tracking circuit (<NUM>, <NUM>) for each of the two differential transistor pairs of input transistors (<NUM>, <NUM>), the offset correction circuit (<NUM>) being configured to receive two enable signals from the control circuit (<NUM>), the said two enable signals being based on the said selection of the differential transistor input pair (<NUM>,<NUM>) by the control circuit (<NUM>) and wherein a respective one of the said two enable signals activates the respective tracking circuit (<NUM>, <NUM>) in the offset correction circuit (<NUM>) for the selected differential transistor pair (<NUM>, <NUM>).