Patent Description:
Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), ferroelectric random-access memory (FeRAM), resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among others.

Memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, and movie players, among other electronic devices.

Memory devices can include memory cells that can store data based on the charge level of a storage element (e.g., a capacitor). Such memory cells can be programmed to store data corresponding to a target data state by varying the charge level of the storage element (e.g., different levels of charge of the capacitor may represent different data sates). For example, sources of an electrical field or energy, such as positive or negative electrical pulses (e.g., positive or negative voltage or current pulses), can be applied to the memory cell (e.g., to the storage element of the cell) for a particular duration to program the cell to a target data state.

A memory cell can be programmed to one of a number of data states. For example, a single level memory cell (SLC) can be programmed to a targeted one of two different data states, which can be represented by the binary units <NUM> or <NUM> and can depend on whether the capacitor of the cell is charged or uncharged. As an additional example, some memory cells can be programmed to a targeted one of more than two data states (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>). Such cells may be referred to as multi state memory cells, multiunit cells, or multilevel cells (MLCs). MLCs can provide higher density memories without increasing the number of memory cells since each cell can represent more than one digit (e.g., more than one bit).

<CIT> describes that the polarization state of individual, separately selectable ferroelectric cells can be switched to a desired condition by application of electric potentials or voltages to word and bit lines forming an addressing matrix. The sensing of these cells is improved by removing parasitic currents generated by any non-addressed cells. <CIT> describes a configuration for selfreferencing a ferroelectric memory cell includes a ferroelectric memory cell that includes a ferroelectric storage capacitor and a transfer transistor, a bit line connected to the ferroelectric memory cell, a first capacitor, and a second capacitor. <CIT> describes a sense amplifier with a variety of capacitors and transistors.

The invention is defined in independent claims <NUM> and <NUM>. Further preferred embodiments are set out in the dependent claims.

The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

Sensing FeRAM memory using charge separation in accordance with the present disclosure can be faster, use less power, and/or be more reliable than previous approaches for sensing memory. For example, sensing memory using charge separation in accordance with the present disclosure can include and/or utilize a single pulse, self-reference sensing approach that can be faster, use less power, and/or be more reliable than previous sensing approaches that may require an external reference (e.g., an external reference voltage) and/or multiple (e.g., separate) sensing signals (e.g. pulses) in order to determine the state of a memory cell.

As used herein, "a" or "an" can refer to one or more of something, and "a plurality of" can refer to more than one of such things. For example, a memory cell can refer to one or more memory cells, and a plurality of memory cells can refer to two or more memory cells. Additionally, the designators "M" and "N" as used herein, particularly with respect to reference numerals in the drawings, indicates that one or more of the particular feature so designated can be included with embodiments of the present disclosure.

<FIG> illustrates an example of a memory array <NUM> in accordance with an embodiment of the present disclosure. Memory array <NUM> can be, for example, a ferroelectric memory (e.g., FeRAM) array.

As shown in <FIG>, memory array <NUM> may include memory cells <NUM> that may be programmable to store different states. A memory cell <NUM> may include a capacitor to store a charge representative of the programmable states. For example, a charged and uncharged capacitor may respectively represent two logic states (e.g. <NUM> and <NUM>). A memory cell <NUM> may include a capacitor with a ferroelectric material, such as, for instance, lead zirconate titanate (PZT), in some examples. For example, ferroelectric materials may have a non-linear relationship between an applied electric field and stored charge (e.g., in the form of a hysteresis loop), and may have a spontaneous electric polarization (e.g., a non-zero polarization in the absence of an electric field). Different levels of charge of a ferroelectric capacitor may represent different logic states, for example.

As shown in <FIG>, a memory cell <NUM> may be coupled to a respective access line, such as a respective one of access lines <NUM>-<NUM> to <NUM>-M, and a respective data (e.g., digit) line, such as one of data lines <NUM>-<NUM> to <NUM>-N. For example, a memory cell <NUM> may be coupled between an access line <NUM> and a data line <NUM>. In an example, access lines <NUM> may also be referred to as word lines, and data lines <NUM> may also be referred to as bit lines. Access lines <NUM> and data lines <NUM>, for example, may be made of conductive materials, such as copper, aluminum, gold, tungsten, etc., metal alloys, other conductive materials, or the like.

In an example, memory cells <NUM> commonly coupled to an access line <NUM> may be referred to as a row of memory cells. For example, access lines <NUM> may be coupled to a row decoder (not shown in <FIG>), and data lines <NUM> may be coupled to a column decoder (not shown in <FIG>). Operations such as programming (e.g., reading) and sensing (e.g., writing) may be performed on memory cells <NUM> by activating or selecting the appropriate access line <NUM> and a data line <NUM> (e.g., by applying a voltage to the access line). Activating an access line <NUM> may electrically couple the corresponding row of memory cells <NUM> to their respective data lines <NUM>.

Although not shown in <FIG> for clarity and so as not to obscure embodiments of the present disclosure, memory array <NUM> can be included in an apparatus in the form of a memory device. As used herein, an "apparatus" can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dice, a module or modules, a device or devices, or a system or systems, for example. Further, the apparatus (e.g., memory device) may include an additional memory array(s) analogous to array <NUM>.

<FIG> illustrates an example circuit <NUM> that includes a memory cell <NUM> in accordance with an embodiment of the present disclosure. As shown in <FIG>, circuit <NUM> includes a ferroelectric memory (e.g., FeRAM) cell <NUM>, an access line <NUM>, and a data line <NUM> that may respectively be examples of a memory cell <NUM>, an access line <NUM>, and a data line <NUM>, shown in <FIG>.

As shown in <FIG>, memory cell <NUM> may include a storage element, such as a capacitor <NUM>, that may have a first plate, such as a cell plate <NUM>, and a second plate, such as a cell bottom <NUM>. Cell plate <NUM> and cell bottom <NUM> may be capacitively coupled through a ferroelectric material <NUM> positioned between them. The orientation of cell plate <NUM> and cell bottom <NUM> may be flipped without changing the operation of memory cell <NUM>.

As shown in <FIG>, circuit <NUM> may include a select device <NUM>, such as a select transistor. For example, the control gate <NUM> of select device <NUM> may be coupled to access line <NUM>. In the example of <FIG>, cell plate <NUM> may be accessed via plate line <NUM>, and cell bottom <NUM> may be accessed via data line <NUM>. For example, select device <NUM> may be used to selectively couple data line <NUM> to cell bottom <NUM> in response to access line <NUM> activating select device <NUM>. For example, capacitor <NUM> may be electrically isolated from data line <NUM> when select device <NUM> is deactivated, and capacitor <NUM> may be electrically coupled to data line <NUM> when select device <NUM> is activated. Activating select device <NUM> may be referred to as selecting memory cell <NUM>, for example.

In an example, sources of an electric field or energy, such as positive or negative electrical pulses (e.g., positive or negative voltage or current pulses), can be applied to the storage element of memory cell <NUM> (e.g., to capacitor <NUM>) for a particular duration to program the cell to a target data state. For instance, when the electric field (e.g., the electrical pulses) is applied across the ferroelectric material <NUM> of capacitor <NUM>, the dipoles of ferroelectric material <NUM> may align in the direction of the applied electric field. The dipoles may retain their alignment (e.g., polarization state) after the electric field is removed, and different logic states (e.g., <NUM> and <NUM>) may be stored as the different polarization states of the ferroelectric material <NUM>. Accordingly, memory cell <NUM> may be programmed by charging cell plate <NUM> and cell bottom <NUM>, which may apply an electric field across ferroelectric material <NUM> and place the ferroelectric material in a particular polarization state (e.g., depending on the polarity of the applied field) that may correspond to a particular data (e.g., logic) state. The data state of the memory cell may subsequently be determined (e.g., sensed) by determining which polarization state the ferroelectric material is in, as will be further described herein.

<FIG> illustrates examples of timing diagrams <NUM>, <NUM>, and <NUM> associated with sensing (e.g., determining the data state of) a memory cell in accordance with the invention. The memory cell is a ferroelectric memory (e.g., FeRAM) cell, such as, for instance, memory cell <NUM> previously described in connection with <FIG>.

Timing diagram <NUM> illustrates a waveform <NUM> that represents a sensing voltage signal (e.g. pulse) applied to the memory cell during a sense operation being performed on the memory cell. For example, the memory cell (e.g., the data line to which the cell is coupled) may be biased by the sensing voltage during the sense operation. The sensing voltage may be applied to the memory cell as a single pulse. For instance, as shown in <FIG>, the amount of voltage being applied to the memory cell may be increased (e.g., ramped up) until time t<NUM>, after which the voltage remains level for the remainder of the sense operation.

Timing diagrams <NUM> and <NUM> illustrate example waveforms <NUM> and <NUM>, respectively, that represent the current signal (e.g., pulse) that may flow through, and be output by, the memory cell in response to the sensing voltage being applied to the cell, depending on the data state to which the memory cell has been programmed. For instance, the current signal output by the memory cell may be represented by waveform <NUM> if the memory cell has been programmed to a first data state (e.g., <NUM>) corresponding to a first polarization state of the ferroelectric material of the memory cell, and the current signal output by the memory cell may be represented by waveform <NUM> if the memory cell has been programmed to a second data state (e.g., <NUM>) corresponding to a second polarization state of the ferroelectric material of the memory cell. As used herein, the first polarization state may be referred to as a displacement state, and may correspond to a polarization state in which the alignment of the dipoles of the ferroelectric material of the memory cell do not change in response to the sensing voltage being applied to the cell. The second polarization state may be referred to as a polar state, and may correspond to a polarization state in which the alignment of the dipoles of the ferroelectric material of the memory cell changes (e.g., switch and/or flip) in response to the sensing voltage being applied to the cell.

In an example, the amount of current output by the memory cell in response to the sensing voltage being applied to the cell may correspond to the amount of charge discharged by the memory cell (e.g. by the capacitor of the memory cell) while the sensing voltage is being applied to the memory cell. As such, waveform <NUM> may correspond to the amount of charge discharged by the memory cell if the memory cell has been programmed to the first data state, and waveform <NUM> may correspond to the amount of charge discharged by the memory cell if the memory cell has been programmed to the second data state.

As such, the data state of the memory cell can be determined based, at least in part, on a comparison of the amount of charge discharged by the memory cell while the sensing voltage represented by waveform <NUM> is being applied to the memory cell before time t<NUM>, and the amount of charge discharged by the memory cell while the sensing voltage is being applied to the cell after time t<NUM>. For example, as illustrated in <FIG>, the memory cell will discharge the same amount of charge before time t<NUM> regardless of whether the cell has been programmed to the first (e.g., displacement) or second (e.g., polar) data state, but the memory cell will also discharge an additional (e.g., greater) amount of charge after time t<NUM> only if the cell has been programmed to the second data state. As such, if the comparison indicates the amount of charge discharged by the memory cell before t<NUM> is greater than the amount of charge discharged by the memory cell after t<NUM>, as represented by waveform <NUM>, then the memory cell has been programmed to the first data state; if the comparison indicates the amount of charge discharged by the memory cell before t<NUM> is less than the amount of charge discharged by the memory cell after t<NUM>, as represented by waveform <NUM>, then the memory cell has been programmed to the second data state.

As illustrated in <FIG>, time t<NUM> can correspond to the time at which a change of the polarization state (e.g., a switching of the alignment of the dipoles) of the ferroelectric material of the memory cell will occur while the sensing voltage is being applied to the memory cell if the cell has been programmed to the second data state. Time t<NUM> occurs after the memory cell will have discharged half of its charge if the cell has been programmed to the first data state, and before the memory cell will have discharged half of its charge if the cell has been programmed to the second data state, as illustrated in <FIG>.

The amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before time t<NUM> can be determined using a first capacitor, and the amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after time t<NUM> can be determined using a second (e.g., different) capacitor. For example, the first capacitor can store the amount of charge discharged by the cell before time t<NUM> and the second capacitor can store the amount of charge discharged by the cell after time t<NUM>, and these respective stored charge amounts can be compared to determine the data state of the cell, as will be further described herein (e.g., in connection with <FIG>). Further, the comparison of the amounts of charge discharged by the memory cell before and after time t<NUM> can include a comparison of signals associated with the amounts of charge discharged by the cell before and after time t<NUM>, as will be further described herein (e.g., in connection with <FIG>).

<FIG> illustrates an example of circuitry (e.g., sense circuitry) <NUM> for charge separation for memory sensing in accordance with an embodiment of the present disclosure. Circuitry <NUM> can be coupled to, and be included in the same apparatus (e.g., memory device) as, memory array <NUM> previously described in connection with <FIG>.

For example, as illustrated in <FIG>, circuitry <NUM> can be coupled to an array that includes memory cells <NUM> that are analogous to memory cells <NUM> previously described in connection with <FIG>. For instance, as illustrated in <FIG>, memory cell <NUM> can include a storage element (e.g., capacitor) <NUM>, and a select device <NUM> coupled to an access line <NUM> and data (e.g., digit) line <NUM>, in a manner analogous to that previously described in connection with <FIG>. Although a single memory cell <NUM> is shown in <FIG> for simplicity and so as not to obscure embodiments of the present disclosure, circuitry <NUM> can be coupled to each respective memory cell of the array.

Further, although not shown in <FIG> for simplicity and so as not to obscure embodiments of the present disclosure, circuitry <NUM> and/or the memory array that includes cells <NUM> can be coupled to a controller. The controller can include, for example, control circuitry and/or logic (e.g., hardware and/or firmware), and can be included on the same physical device (e.g., the same die) as the memory array, or can be included on a separate physical device that is communicatively coupled to the physical device that includes the memory array. In an embodiment, components of the controller can be spread across multiple physical devices (e.g., some components on the same die as the array, and some components on a different die, module, or board). The controller can operate circuitry <NUM> to utilize charge separation as described herein to determine the data state of memory cell <NUM>.

For example, as shown in <FIG>, circuitry <NUM> can include a first capacitor <NUM> and a second capacitor <NUM>. Capacitor <NUM> can store charge discharged by memory cell <NUM> (e.g., by storage element <NUM>) while a sensing voltage is being applied to memory cell <NUM> (e.g., via data line <NUM>) before a particular reference time, and capacitor <NUM> can store charge discharged by memory cell <NUM> while the sensing voltage is being applied to memory cell <NUM> after the particular reference time. The sensing voltage can be, for example, the sensing voltage represented by waveform <NUM> previously described in connection with <FIG>, and the particular reference time can be, for example, time t<NUM> previously described in connection with <FIG>.

For instance, as shown in <FIG>, circuitry <NUM> can include a first transistor <NUM> coupled to first capacitor <NUM>, and a second transistor <NUM> coupled to second capacitor <NUM>. Further, circuitry <NUM> can include a cascode <NUM> coupled to transistors <NUM> and <NUM> and memory cell <NUM>, as illustrated in <FIG>. Transistors <NUM> and <NUM> can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), and cascode <NUM> can be, for example, an n-channel MOSFET (nMOS FET).

Transistor <NUM> can couple capacitor <NUM> to memory cell <NUM> (e.g., via data line <NUM>) through cascode <NUM> upon a first signal (e.g., F1 illustrated in <FIG>) being applied to transistor <NUM>, and transistor <NUM> can couple capacitor <NUM> to memory cell <NUM> (e.g., via data line <NUM>) through cascode <NUM> upon a second signal (e.g., F2 illustrated in <FIG>) being applied to transistor <NUM>. Further, cascode <NUM> can be used to bias memory cell <NUM> (e.g., data line <NUM>) at the sensing voltage.

As an example, the first signal can be applied to transistor <NUM> before the particular reference time (e.g., t<NUM>) such that only capacitor <NUM> is coupled to memory cell <NUM> before the particular reference time, and the second signal can be applied to transistor <NUM> after the particular reference time such that only capacitor <NUM> is coupled to memory cell <NUM> after the particular reference time (e.g., capacitor <NUM> is not coupled to memory cell <NUM> before the particular reference time, and capacitor <NUM> is not coupled to memory cell <NUM> after the particular reference time). Accordingly, in such an example, the charge discharged by memory cell <NUM> while the sensing voltage is being applied thereto before the particular reference time may be discharged to, and stored by (e.g. integrated on), capacitor <NUM>, and the charge discharged by memory cell <NUM> while the sensing voltage is being applied thereto after the particular reference time may be discharged to, and stored by (e.g., integrated on), capacitor <NUM>. If memory cell <NUM> has been programmed to the first (e.g., displacement) data state, capacitor <NUM> will store the majority (e.g., the highest percentage) of the charge discharged by memory cell <NUM>; if memory cell <NUM> has been programmed to the second (e.g., polar) data state, capacitor <NUM> will store the majority of the charge discharged by memory cell <NUM>.

Accordingly, the data state to which memory cell <NUM> has been programmed can be determined based, at least in part, on a comparison of the amount of charge stored by capacitors <NUM> and <NUM> after the sensing voltage has been applied to memory cell <NUM> and signals F1 and F2 have been applied to transistors <NUM> and <NUM>, respectively. For example, if the comparison indicates the amount of charge stored by capacitor <NUM> is greater than the amount of charge stored by capacitor <NUM>, then the memory cell has been programmed to the first data state; if the comparison indicates the amount of charge stored by capacitor <NUM> is less than the amount of charge stored by capacitor <NUM>, then the memory cell has been programmed to the second data state.

The comparison of the amount of charge stored by capacitors <NUM> and <NUM> can be performed, for example, using latch <NUM> of circuitry <NUM>. For instance, capacitors <NUM> and <NUM> will have a voltage across, at nodes <NUM> and <NUM>, respectively, that corresponds to the amount of charge stored by capacitors <NUM> and <NUM>, and which can be read by latch <NUM>. As shown in <FIG>, latch <NUM> can be coupled to capacitor <NUM> through transistor <NUM>, latch <NUM> can be coupled to capacitor <NUM> through transistor <NUM>, and latch <NUM> can be disconnected from data line <NUM> by transistor <NUM>. When signals (e.g., I1 and I2 illustrated in <FIG>) are applied to transistors <NUM> and <NUM>, respectively, the signals at nodes <NUM> and <NUM>, which correspond to the amount of charge stored by capacitors <NUM> and <NUM>, respectively, can be compared by latch <NUM> to determine the data state of memory cell <NUM>. Examples of the signals at nodes <NUM> and <NUM>, and the comparison of the signals, will be further described herein (e.g., in connection with <FIG>).

As such, the data state of memory cell <NUM> can be determined without using an external reference voltage. For instance, the data state of memory cell <NUM> can be determined using a self-reference sensing approach. Further, the data state of memory cell <NUM> can be determined using a single pulse, rather than multiple sensing pulses.

In an example, data line <NUM> and capacitors <NUM> and <NUM> may be pre-charged before the sensing voltage is applied to memory cell <NUM>. For instance, in the example illustrated in <FIG>, data line <NUM> and capacitors <NUM> and <NUM> may be pre-charged to an initial voltage Vccp. Capacitor <NUM> illustrated in <FIG> may represent the capacitance of data line <NUM> once data line <NUM> has been pre-charged.

Further, the amount by (e.g., value to) which data line <NUM> and capacitors <NUM> and <NUM> are pre-charged may vary. Varying the pre-charge amount can shift the portion of the current signal distribution output by memory cell <NUM> corresponding to the additional charge discharged by the memory cell after time t<NUM> if the cell has been programmed to the second data state (e.g., the portion of the current signal distribution corresponding to the polar state), which can further separate this portion of the current signal distribution from the portion corresponding to the charge discharged before time t<NUM> (e.g., the portion of the current signal corresponding to the displacement state). For instance, varying the pre-charge amount can shift the polar state portion of the current signal distribution such that it is completely separate from the displacement state portion.

<FIG> illustrates examples of timing diagrams <NUM>, <NUM>, and <NUM> associated with sensing a memory cell in accordance with an embodiment of the present disclosure. The memory cell can be, for example, memory cell <NUM> previously described in connection with <FIG>.

Timing diagram <NUM> illustrates example waveforms <NUM>, <NUM>, and <NUM> that represent signals associated with (e.g. used during) a sense operation being performed on the memory cell. For example, waveform <NUM> represents signal F1 applied to transistor <NUM> previously described in connection with <FIG>, waveform <NUM> represents signal F2 applied to transistor <NUM> previously described in connection with <FIG>, and waveform <NUM> represents a signal used to activate access line <NUM> previously described in connection with <FIG>.

During the sense operation, signal F1 is switched on (e.g., high) first, as illustrated in <FIG>, such that charge discharged by the memory cell is discharged to capacitor <NUM>, as previously described in connection with <FIG>. After signal F1 is switched on, access line <NUM> can be activated, as illustrated in <FIG>. After access line <NUM> has been activated, signal F1 is switched off (e.g., low) and signal F2 is switched on, as illustrated in <FIG>, such that charge discharged by the memory cell is discharged to capacitor <NUM> (e.g., instead of to capacitor <NUM>), as previously described in connection with <FIG>. Although not shown in <FIG>, the time at which signal F1 is switched off and signal F2 is switched on can correspond to reference time t<NUM> previously described herein. Signal F2 can then subsequently be switched off (e.g., at the conclusion of the sense operation).

Timing diagram <NUM> illustrates example waveforms <NUM> and <NUM> that represent the signals at circuit nodes <NUM> and <NUM>, respectively, previously described in connection with <FIG>, during the sense operation performed on the memory cell if the memory cell has been programmed to the second (e.g., polar) data state. Timing diagram <NUM> illustrates example waveforms <NUM> and <NUM> that represent the signals at circuit nodes <NUM> and <NUM>, respectively, during the sense operation if the memory cell has been programmed to the first (e.g., displacement) data state. The signals at nodes <NUM> and <NUM> can correspond to the amount of charge stored by capacitors <NUM> and <NUM>, respectively, as previously described in connection with <FIG>.

As shown in <FIG>, at the conclusion of the sense operation (e.g., after signal F2 has been switched off), signal <NUM> is lower than signal <NUM>, and signal <NUM> is higher than signal <NUM>. As such, a comparison between signals <NUM> and <NUM> at the conclusion of the sense operation may indicate that the amount of charge stored by capacitor <NUM> is less than the amount of charge stored by capacitor <NUM>, and therefore the memory cell has been programmed to the second (e.g., polar) data state, as previously described herein; a comparison between signals <NUM> and <NUM> at the conclusion of the sense operation may indicate that the amount of charge stored by capacitor <NUM> is greater than the amount of charge stored by capacitor <NUM>, and therefore the memory cell has been programmed to the first (e.g., displacement) data state, as previously described herein. The comparison between the signals can be performed, for example, by latch <NUM>, as previously described in connection with <FIG>.

<FIG> illustrates examples of timing diagrams <NUM>, <NUM>, and <NUM> associated with sensing (e.g., determining the data state of) a memory cell in accordance with an embodiment of the present disclosure. The memory cell can be, for example, a ferroelectric memory (e.g., FeRAM) cell, such as, for instance, memory cell <NUM> previously described in connection with <FIG> and/or memory cell <NUM> previously described in connection with <FIG>.

Timing diagram <NUM> illustrates a waveform <NUM> that represents a sensing voltage signal (e.g. pulse) applied to the memory cell during a sense operation being performed on the memory cell, in a manner analogous to waveform <NUM> previously described in connection with <FIG>. Timing diagrams <NUM> and <NUM> illustrate example waveforms <NUM> and <NUM>, respectively, that represent the current signal (e.g., pulse) that may flow through, and be output by, the memory cell in response to the sensing voltage being applied to the cell, depending on the data state to which the memory cell has been programmed, in a manner analogous to waveforms <NUM> and <NUM> previously described in connection with <FIG>. For instance, the current signal output by the memory cell may be represented by waveform <NUM> if the memory cell has been programmed to a first (e.g., displacement) data state, and the current signal output by the memory cell may be represented by waveform <NUM> if the memory cell has been programmed to a second (e.g., polar) data state, in a manner analogous to that previously described in connection with <FIG>. Further, waveform <NUM> may correspond to the amount of charge discharged by the memory cell if the memory cell has been programmed to the first data state, and waveform <NUM> may correspond to the amount of charge discharged by the memory cell if the memory cell has been programmed to the second data state, in a manner analogous to that previously described in connection with <FIG>.

As such, the data state of the memory cell can be determined based, at least in part, on a comparison of the amount of charge discharged by the memory cell while the sensing voltage represented by waveform <NUM> is being applied to the memory cell before time t<NUM> illustrated in <FIG>, and the amount of charge discharged by the memory cell while the sensing voltage is being applied to the cell after time t<NUM> illustrated in <FIG>. For example, as illustrated in <FIG>, the memory cell will discharge the same amount of charge before time t<NUM> regardless of whether the cell has been programmed to the first (e.g., displacement) or second (e.g., polar) data state, but the memory cell will also discharge an additional (e.g., greater) amount of charge after time t<NUM> only if the cell has been programmed to the second data state. As such, if the comparison indicates the amount of charge discharged by the memory cell before time t<NUM> is greater than the amount of charge discharged by the memory cell after time t<NUM>, as represented by waveform <NUM>, then the memory cell has been programmed to the first data state; if the comparison indicates the amount of charge discharged by the memory cell before t<NUM> is less than the amount of charge discharged by the memory cell after t<NUM>, as represented by waveform <NUM>, then the memory cell has been programmed to the second data state.

As illustrated in <FIG>, time t<NUM> can correspond to a time before a change of the polarization state (e.g., a switching of the alignment of the dipoles) of the ferroelectric material of the memory cell will occur while the sensing voltage is being applied to the memory cell if the cell has been programmed to the second data state, and time t<NUM> can correspond to a time after the change of the polarization state of the ferroelectric material of the cell will occur if the cell has been programmed to the second data state. Time t<NUM> corresponds to the time at which the memory cell will have discharged half of its charge if the cell has been programmed to the first (e.g., displacement) data state, and time t<NUM> can correspond to the time at which the memory cell will have discharged half of its charge if the cell has been programmed to the second (e.g., polar) data state, as illustrated in <FIG>. The amount of time between t<NUM> and t<NUM> illustrated in <FIG> can be, for instance, <NUM>-<NUM> nanoseconds.

The amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before time t<NUM> can be determined using capacitor <NUM> of circuitry <NUM> previously described in connection with <FIG>, and the amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after time t<NUM> can be determined using capacitor <NUM> of circuitry <NUM> previously described in connection with <FIG>. For example, capacitor <NUM> can store the amount of charge discharged by the cell before time t<NUM> and capacitor <NUM> can store the amount of charge discharged by the cell after time t<NUM>, and these respective stored charge amounts can be compared to determine the data state of the cell, in a manner analogous to that previously described in connection with <FIG>. For instance, the comparison of the amounts of charge discharged by the memory cell before time t<NUM> and after time t<NUM> can include a comparison (e.g., by latch <NUM>) of signals associated with the amounts of charge discharged by the cell before time t<NUM> and after time t<NUM>, in a manner analogous to that previously described in connection with <FIG>.

As such, the data state of the memory cell can be determined without using an external reference voltage. For instance, the data state of the memory cell can be determined using a self-reference sensing approach. Further, the data state of the memory cell can be determined using a single pulse, rather than multiple sensing pulses.

<FIG> illustrates an example of circuitry (e.g., sense circuitry) <NUM> for charge separation for memory sensing in accordance with an embodiment of the present disclosure. Circuitry <NUM> can be coupled to, and be included in the same apparatus (e.g., memory device) as, memory array <NUM> previously described in connection with <FIG>, in a manner analogous to circuitry <NUM> previously described in connection with <FIG>. For example, as illustrated in <FIG>, circuitry <NUM> can be coupled to an array that includes memory cells <NUM> that are analogous to memory cells <NUM> previously described in connection with <FIG> (e.g., that include a storage element <NUM>, and a select device <NUM> coupled to an access line <NUM> and data line <NUM>, in a manner analogous to that previously described in connection with <FIG>).

Further, as shown in <FIG>, circuitry <NUM> can include a first capacitor <NUM> and a second capacitor <NUM>. In the example illustrated in <FIG>, capacitor <NUM> can store charge discharged by memory cell <NUM> (e.g., by storage element <NUM>) while a first sensing voltage is being applied to memory cell <NUM> (e.g., via data line <NUM>), and capacitor <NUM> can store charge discharged by memory cell <NUM> while a second (e.g., different) sensing voltage is being applied to memory cell <NUM> after the first sensing voltage has been applied to the cell (e.g., the first and second sensing voltages are applied to the cell separately). The first sensing voltage can be a voltage that is less than a particular voltage, and the second sensing voltage can be a voltage that is greater than the particular voltage. For example, the first and second sensing voltages can be less and greater than, respectively, a voltage that will cause a change of the polarization state (e.g., a switching of the alignment of the dipoles) of the ferroelectric material of memory cell <NUM> to occur while that voltage is being applied to memory cell <NUM> if the cell has been programmed to the second (e.g., polar) data state. This voltage may be referred to herein as the coercitive voltage, and may be, for instance, <NUM> Volts in some examples.

The first and second sensing voltages can be applied to memory cell <NUM> during the same (e.g., as part of a single) sense operation being performed on memory cell <NUM>. Further, the first and second sensing voltages can have a lower magnitude than the sensing voltages represented by waveforms <NUM> and <NUM> previously described in connection with <FIG> and <FIG>, respectively, which can further reduce the amount of power used to sense memory cell <NUM>, and/or can further separate the portion of the current signal distribution output by memory cell <NUM> corresponding to the polar state from the portion of the current signal distribution output by memory cell <NUM> corresponding to the displacement state. Further, the first sensing voltage may have a greater magnitude than the difference between the two sensing voltages.

As shown in <FIG>, circuitry <NUM> can include a first transistor <NUM> coupled to first capacitor <NUM>, a second transistor <NUM> coupled to second capacitor <NUM>, and a cascode <NUM> coupled to transistors <NUM> and <NUM> and memory cell <NUM>, in a manner analogous to that previously described in connection with <FIG>. _Transistor <NUM> can couple capacitor <NUM> to memory cell <NUM> through cascode <NUM> upon signal F1 being applied to transistor <NUM>, and transistor <NUM> can couple capacitor <NUM> to memory cell <NUM> through cascode <NUM> upon signal F2 being applied to transistor <NUM>, in a manner analogous to that previously described in connection with <FIG>. Further, cascode <NUM> can be used to bias memory cell <NUM> (e.g., data line <NUM>) at the first and second sensing voltages.

As an example, signal F1 can be applied to transistor <NUM> while the first sensing voltage is being applied to memory cell <NUM> such that only capacitor <NUM> is coupled to memory cell <NUM> while the first sensing voltage is being applied thereto, and signal F2 can be applied to transistor <NUM> while the second sensing voltage is being applied to memory cell <NUM> such that only capacitor <NUM> is coupled to memory cell <NUM> while the second sensing voltage is being applied thereto (e.g., capacitor <NUM> is not coupled to memory cell <NUM> while the first sensing voltage is being applied, and capacitor <NUM> is not coupled to memory cell <NUM> while the second sensing voltage is being applied). Accordingly, in such an example, the charge discharged by memory cell <NUM> while the first sensing voltage is being applied thereto may be discharged to, and stored by (e.g. integrated on), capacitor <NUM>, and the charge discharged by memory cell <NUM> while the second sensing voltage is being applied thereto may be discharged to, and stored by (e.g., integrated on), capacitor <NUM>. If memory cell <NUM> has been programmed to the first (e.g., displacement) data state, capacitor <NUM> will store the majority (e.g., the highest percentage) of the charge discharged by memory cell <NUM>; if memory cell <NUM> has been programmed to the second (e.g., polar) data state, capacitor <NUM> will store the majority of the charge discharged by memory cell <NUM>.

Accordingly, the data state to which memory cell <NUM> has been programmed can be determined based, at least in part, on a comparison of the amount of charge stored by capacitors <NUM> and <NUM> after the first and second sensing voltages have been applied to memory cell <NUM> (e.g., after signals F1 and F2 have been applied to transistors <NUM> and <NUM>, respectively). For example, if the comparison indicates the amount of charge stored by capacitor <NUM> is greater than the amount of charge stored by capacitor <NUM> (e.g., indicating memory cell <NUM> discharged more charge while the first sensing voltage was being applied than while the second sensing voltage was being applied), then the memory cell has been programmed to the first data state; if the comparison indicates the amount of charge stored by capacitor <NUM> is less than the amount of charge stored by capacitor <NUM> (e.g., indicating memory cell <NUM> discharged less charge while the first sensing voltage was being applied than while the second sensing voltage was being applied), then the memory cell has been programmed to the second data state.

The comparison of the amount of charge stored by capacitors <NUM> and <NUM> can be performed, for example, using latch <NUM> of circuitry <NUM>, in a manner analogous to that previously described in connection with <FIG>. For instance, when signals I1 and <NUM> are applied to transistors <NUM> and <NUM>, respectively, the signals at nodes <NUM> and <NUM>, which correspond to the amount of charge stored by capacitors <NUM> and <NUM>, respectively, can be compared by latch <NUM> to determine the data state of memory cell <NUM>, in a manner analogous to that previously described in connection with <FIG>. Examples of the signals at nodes <NUM> and <NUM>, and the comparison of the signals, will be further described herein (e.g., in connection with <FIG>).

As such, the data state of memory cell <NUM> can be determined without using an external reference voltage. For instance, the data state of memory cell <NUM> can be determined using a self-reference sensing approach.

<FIG> illustrates examples of timing diagrams <NUM> and <NUM> associated with sensing a memory cell in accordance with an embodiment of the present disclosure. The memory cell can be, for example, memory cell <NUM> previously described in connection with <FIG>.

As shown in <FIG>, at the conclusion of the sense operation (e.g., after both the first and second sensing voltages have been applied to the memory cell), signal <NUM> is lower than signal <NUM>, and signal <NUM> is higher than signal <NUM>. As such, a comparison between signals <NUM> and <NUM> at the conclusion of the sense operation may indicate that the amount of charge stored by capacitor <NUM> is less than the amount of charge stored by capacitor <NUM>, and therefore the memory cell has been programmed to the second (e.g., polar) data state, as previously described herein; a comparison between signals <NUM> and <NUM> at the conclusion of the sense operation may indicate that the amount of charge stored by capacitor <NUM> is greater than the amount of charge stored by capacitor <NUM>, and therefore the memory cell has been programmed to the first (e.g., displacement) data state, as previously described herein. The comparison between the signals can be performed, for example, by latch <NUM>, as previously described in connection with <FIG>.

Claim 1:
A method of operating an apparatus, comprising:
applying a sensing voltage to a memory cell (<NUM>, <NUM>, <NUM>), wherein the memory cell is a ferroelectric memory cell; and
determining, by sense circuitry (<NUM>, <NUM>), a data state of the memory cell (<NUM>, <NUM>, <NUM>) based, at least in part, on a comparison of:
an amount of charge discharged by the memory cell (<NUM>, <NUM>, <NUM>) in a first capacitor while the sensing voltage is being applied to the memory cell (<NUM>, <NUM>, <NUM>) before a first reference time, wherein the first reference time corresponds to a time at which the memory cell (<NUM>, <NUM>, <NUM>) will have discharged half of its charge if the memory cell (<NUM>, <NUM>, <NUM>) is in a first data state; and
an amount of charge discharged by the memory cell (<NUM>, <NUM>, <NUM>) in a second capacitor while the sensing voltage is being applied to the memory cell (<NUM>, <NUM>, <NUM>) after a second reference time, wherein the second reference time corresponds to a time at which the memory cell (<NUM>, <NUM>, <NUM>) will have discharged half of its charge if the memory cell (<NUM>, <NUM>, <NUM>) is in a second data state.