Patent Description:
Wireless communication systems are widely deployed to provide various types of communication content such as voice, data, and so on. These systems may be multiple-access systems capable of supporting communication with multiple users by sharing the available system resources (e.g., bandwidth and transmit power). Examples of such multiple-access systems include Long Term Evolution (LTE) systems, Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, <NUM>rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) systems, Long Term Evolution Advanced (LTE-A) systems, and Orthogonal Frequency Division Multiple Access (OFDMA) systems.

Generally, a wireless multiple-access communication system can simultaneously support communication for multiple wireless nodes. Each node communicates with one or more base stations via transmissions on forward and reverse links. The forward link (or downlink) refers to a communication link from base stations to nodes, and a reverse link (or uplink) refers to a communication link from nodes to base stations. Communication links may be established via a single-input single-output, multiple-input single-output, or a multiple-input multiple-output (MIMO) system.

In the modem information age, binary values (e.g., ones and zeros), are used to represent and communicate various types of information, such as video, audio, statistical information, etc. Unfortunately, during storage, transmission, and/or processing of binary data, errors may be unintentionally introduced; for example, a one may be changed to a zero or vice versa.

Generally, in the case of data transmission, a receiver observes each received bit in the presence of noise or distortion and only an indication of the bit's value is obtained. Under these circumstances, the observed values are interpreted as a source of "soft" bits. A soft bit indicates a preferred estimate of the bit's value (e.g., a one or a zero) together with some indication of the reliability of that estimate. While the number of errors may be relatively low, even a small number of errors or level of distortion can result in the data being unusable or, in the case of transmission errors, may necessitate retransmission of the data.

In order to provide a mechanism to check for errors and, in some cases, to correct errors, binary data can be coded to introduce carefully designed redundancy. Coding of a unit of data produces what is commonly referred to as a code word. Because of its redundancy, a code word will often include more bits than the input unit of data from which the code word was produced.

Redundant bits are added by an encoder to the transmitted bit stream to create a code word. When signals arising from transmitted code words are received or processed, the redundant information included in the code word as observed in the signal can be used to identify and/or correct errors in or remove distortion from the received signal in order to recover the original data unit. Such error checking and/or correcting can be implemented as part of a decoding process. In the absence of errors, or in the case of correctable errors or distortion, decoding can be used to recover from the source data being processed, the original data unit that was encoded. In the case of unrecoverable errors, the decoding process may produce some indication that the original data cannot be fully recovered. Such indications of decoding failure can be used to initiate retransmission of the data.

With the increased use of fiber optic lines for data communication and increases in the rate at which data can be read from and stored to data storage devices, (e.g., disk drives, tapes, etc.), there is an increasing need not only for efficient use of data storage and transmission capacity but also for the ability to encode and decode data at high rates of speed.

While encoding efficiency and high data rates are important, for an encoding and/or decoding system to be practical for use in a wide range of devices (e.g., consumer devices), it is important that the encoders and/or decoders be capable of being implemented at reasonable cost.

Communication systems often need to operate at several different rates. One way to keep the implementation as simple as possible and to provide for the coding and decoding at the different rates is to use adjustable low-density-parity check (LDPC) codes. In particular, one can generate higher-rate LDPC codes by puncturing lower-rate codes.

An example of an emerging telecommunication standard is new radio (NR). NR is a set of enhancements to the LTE mobile standard (e.g., <NUM> radio access) promulgated by Third Generation Partnership Project (3GPP). NR is designed to better support mobile broadband Internet access by improving spectral efficiency, lowering costs, improving services, making use of new spectrum, and better integrating with other open standards using OFDMA with a cyclic prefix (CP) on the downlink (DL) and on the uplink (UL), as well as supporting beamforming, multiple-input multiple-output (MIMO) antenna technology, and carrier aggregation.

As the demand for mobile broadband access continues to increase, there exists a need for further improvements in NR technology. One area for improvements is the area of encoding/decoding, applicable to NR. For example, techniques for high performance LDPC codes for NR are desirable.

Patent application <CIT> relates to transmitting a signal in a communication system using a Hybrid Automatic Repeat request (HARQ) scheme. Publication "<NPL>, relates to a nested family of irregular QC LDPC codes obtained from one high-rate base matrix, and a quasi row orthogonal structure to make a trade-off between performance and complexity.

The publication "<NPL> relates to eMBB coding scheme and details of the LDPC design, and in particular, to a comparison of QC LDPC and LDPC codes. A LDPC design for an eMBB scenario is proposed and simulation results are provided.

The appended drawings illustrate only certain typical aspects of this disclosure, however, and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

Aspects of the present disclosure provide apparatus, methods, processing systems, and computer program products for encoding for new radio (NR) (new radio access technology). New radio (NR) may refer to radios configured to operate according to a new air interface or fixed transport layer. NR may include Enhanced mobile broadband (eMBB) techniques targeting wide bandwidth (e.g. <NUM> and wider) communications systems, millimeter wave (mmW) techniques targeting high carrier frequency (e.g. <NUM> and higher) communications systems, massive machine type communications (mMTC) techniques targeting non-backward compatible machine type communications (MTC) systems, and mission critical techniques targeting ultra reliable low latency communications (URLLC). For these general topics, different techniques are considered, such as coding techniques, including low-density parity check (LDPC) coding, and polar coding. An NR cell may refer to a cell operating according to the new air interface or a fixed transport layer. An NR Node B (e.g., a <NUM> Node B) may correspond to one or multiple transmission reception points (TRPs). Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) encoded transmissions, and more particularly to decoding LDPC encoded transmissions using a parity check matrix with large number of pairwise fully row-orthogonal rows.

In addition, the scope of the disclosure is intended to cover such an apparatus or method, which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein.

Although particular aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof.

The techniques described herein may be used for various wireless communication networks such as Long Term Evolution (LTE), Code Division Multiple Access (CDMA) networks, Time Division Multiple Access (TDMA) networks, Frequency Division Multiple Access (FDMA) networks, Orthogonal FDMA (OFDMA) networks, Single-Carrier FDMA (SC-FDMA) networks, etc. The terms "networks" and "systems" are often used interchangeably. A CDMA network may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), CDMA2000, etc. UTRA includes Wideband-CDMA (W-CDMA) and Low Chip Rate (LCR). An OFDMA network may implement a radio technology such as NR (e.g., <NUM> RA), Evolved UTRA (E-UTRA), IEEE <NUM>, IEEE <NUM>, IEEE <NUM>, Flash-OFDM®, etc. UTRA, E-UTRA, and GSM are part of Universal Mobile Telecommunication System (UMTS). Long Term Evolution (LTE) is a release of UMTS that uses E-UTRA. UTRA, E-UTRA, GSM, UMTS, and LTE are described in documents from an organization named "3rd Generation Partnership Project" (3GPP). CDMA2000 is described in documents from an organization named "3rd Generation Partnership Project <NUM>" (3GPP2). These communications networks are merely listed as examples of networks in which the techniques described in this disclosure may be applied; however, this disclosure is not limited to the above-described communications network.

Single carrier frequency division multiple access (SC-FDMA) is a transmission technique that utilizes single carrier modulation at a transmitter side and frequency domain equalization at a receiver side. The SC-FDMA has similar performance and essentially the same overall complexity as those of OFDMA system. However, SC-FDMA signal has lower peak-to-average power ratio (PAPR) because of its inherent single carrier structure. The SC-FDMA has drawn great attention, especially in the uplink (UL) communications where lower PAPR greatly benefits the wireless node in terms of transmit power efficiency.

An access point ("AP") may comprise, be implemented as, or known as NodeB, Radio Network Controller ("RNC"), eNodeB (eNB), Node B (e.g., <NUM> Node B), transmission reception point (TRP), Base Station Controller ("BSC"), Base Transceiver Station ("BTS"), Base Station ("BS"), Transceiver Function ("TF"), Radio Router, Radio Transceiver, Basic Service Set ("BSS"), Extended Service Set ("ESS"), Radio Base Station ("RBS"), or some other terminology.

An access terminal ("AT") may comprise, be implemented as, or be known as an access terminal, a subscriber station, a subscriber unit, a mobile station, a remote station, a remote terminal, a user terminal, a user agent, a user device, user equipment (UE), a user station, a wireless node, or some other terminology. In some implementations, an access terminal may comprise a cellular telephone, a smart phone, a cordless telephone, a Session Initiation Protocol ("SIP") phone, a wireless local loop ("WLL") station, a personal digital assistant ("PDA"), a tablet, a netbook, a smartbook, an ultrabook, a handheld device having wireless connection capability, a Station ("STA"), or some other suitable processing device connected to a wireless modem. Accordingly, one or more aspects taught herein may be incorporated into a phone (e.g., a cellular phone, a smart phone), a computer (e.g., a desktop), a portable communication device, a portable computing device (e.g., a laptop, a personal data assistant, a tablet, a netbook, a smartbook, an ultrabook), medical devices or equipment, biometric sensors/devices, an entertainment device (e.g., a music or video device, or a satellite radio), a vehicular component or sensor, smart meters/sensors, industrial manufacturing equipment, a global positioning system device, or any other suitable device that is configured to communicate via a wireless or wired medium. In some aspects, the node is a wireless node. A wireless node may provide, for example, connectivity for or to a network (e.g., a wide area network such as the Internet or a cellular network) via a wired or wireless communication link.

While aspects may be described herein using terminology commonly associated with <NUM> and/or <NUM> wireless technologies, aspects of the present disclosure can be applied in other generation-based communication systems, such as <NUM> and later, including NR technologies.

<FIG> illustrates an example communications network <NUM> in which aspects of the present disclosure may be performed. As illustrated, A Node B <NUM> (e.g., a TRP or <NUM> Node B) may include multiple antenna groups, one group including antennas <NUM> and <NUM>, another group including antennas <NUM> and <NUM>, and an additional group including antennas <NUM> and <NUM>. In <FIG>, only two antennas are shown for each antenna group, however, more or fewer antennas may be utilized for each antenna group. Wireless node <NUM> may be in communication with antennas <NUM> and <NUM>, where antennas <NUM> and <NUM> transmit information to wireless node <NUM> over forward link <NUM> and receive information from wireless node <NUM> over reverse link <NUM>. Wireless node <NUM> may be in communication with antennas <NUM> and <NUM>, where antennas <NUM> and <NUM> transmit information to wireless node <NUM> over forward link <NUM> and receive information from wireless node <NUM> over reverse link <NUM>. The Node B <NUM> may also be in communication with other wireless nodes, which may be, for example, Intemet-of-Things (IoT) devices. IoT device <NUM> may be in communication with one or more other antennas of Node B <NUM>, where the antennas transmit information to IoT device <NUM> over forward link <NUM> and receive information from IoT device <NUM> over reverse link <NUM>. IoT device <NUM> may be in communication with one or more other antennas of Node B <NUM>, where the antennas transmit information to IoT device <NUM> over forward link <NUM> and receive information from IoT device <NUM> over reverse link <NUM>. In a Frequency Division Duplex (FDD) system, communication links <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may use different frequency for communication. For example, forward link <NUM> may use a different frequency than that used by reverse link <NUM>, and forward link <NUM> may use a different frequency than that used by reverse link <NUM>.

Each group of antennas and/or the area in which they are designed to communicate is often referred to as a sector of the Node B. In one aspect of the present disclosure, each antenna group may be designed to communicate to wireless nodes in a sector of the areas covered by Node B <NUM>.

Wireless node <NUM> may be in communication with Node B <NUM>, where antennas from the Node B <NUM> transmit information to wireless node <NUM> over forward link <NUM> and receive information from the wireless node <NUM> over reverse link <NUM>.

In communication over forward links <NUM> and <NUM>, the transmitting antennas of BS <NUM> may utilize beamforming in order to improve the signal-to-noise ratio of forward links for the different wireless nodes <NUM>, <NUM>, <NUM>, and <NUM>. Also, a Node B using beamforming to transmit to wireless nodes scattered randomly through its coverage causes less interference to wireless nodes in neighboring cells than a Node B transmitting through a single antenna to all its wireless nodes.

NR may utilize orthogonal frequency-division multiplexing (OFDM) with a CP on the uplink and downlink and include support for half-duplex operation using time division duplex (TDD). A single component carrier bandwidth of <NUM> may be supported. NR resource blocks may span <NUM> sub-carriers with a sub-carrier bandwidth of <NUM> over a <NUM> duration. Each radio frame may consist of <NUM> half frames, each half frame consisting of <NUM> subframes, with a length of <NUM>. Consequently, each subframe may have a length of <NUM>. Each subframe may indicate a link direction (i.e., downlink (DL) or uplink (UL)) for data transmission and the link direction for each subframe may be dynamically switched. Each subframe may include DL/UL data as well as DL/UL control data. MIMO configurations in the DL may support up to <NUM> transmit antennas with multi-layer DL transmissions with up to <NUM> streams. Alternatively, NR may support a different air interface, other than an OFDM-based air interface.

<FIG> illustrates a block diagram of an aspect of a transmitter system <NUM> (e.g., also known as the base station) and a receiver system <NUM> (e.g., also known as the wireless node) in a multiple-input multiple-output (MIMO) system <NUM>, in which aspects of the present disclosure may be practiced. Each of system <NUM> and system <NUM> has capabilities to both transmit and receive. Whether system <NUM> or system <NUM> is transmitting, receiving, or transmitting and receiving simultaneously depends on the application. At the transmitter system <NUM>, traffic data for a number of data streams is provided from a data source <NUM> to a transmit (TX) data processor <NUM>.

In one aspect of the present disclosure, each data stream may be transmitted over a respective transmit antenna. TX data processor <NUM> formats, codes, and interleaves the traffic data for each data stream based on a particular coding scheme (e.g., low-density parity check (LDPC)) selected for that data stream to provide coded data.

The coded data for each data stream may be multiplexed with pilot data using OFDM techniques. The pilot data is typically a known data pattern that is processed in a known manner and may be used at the receiver system to estimate the channel response. The multiplexed pilot and coded data for each data stream is then modulated (e.g., symbol mapped) based on a particular modulation scheme (e.g., BPSK, QSPK, M-PSK, or M-QAM) selected for that data stream to provide modulation symbols. The data rate, coding, and modulation for each data stream may be determined by instructions performed by processor <NUM>. Memory <NUM> may store data and software/firmware for the transmitter system <NUM>.

TX MIMO processor <NUM> then provides NT (e.g., where NT is a positive integer) modulation symbol streams to NT transmitters (TMTR) 222a through 222t. In certain aspects of the present disclosure, TX MIMO processor <NUM> applies beamforming weights to the symbols of the data streams and to the antenna from which the symbol is being transmitted.

At receiver system <NUM>, the transmitted modulated signals may be received by NR (e.g., where NR is a positive integer) antennas 252a through 252r and the received signal from each antenna <NUM> may be provided to a respective receiver (RCVR) 254a through 254r. Each receiver <NUM> may condition (e.g., filters, amplifies, and downconverts) a respective received signal, digitize the conditioned signal to provide samples, and further process the samples to provide a corresponding "received" symbol stream.

A receive (RX) data processor <NUM> then receives and processes the NR received symbol streams from NR receivers <NUM> based on a particular receiver processing technique to provide NT "detected" symbol streams. The processing by RX data processor <NUM> may be complementary to that performed by TX MIMO processor <NUM> and TX data processor <NUM> at transmitter system <NUM>.

A processor <NUM> periodically determines which pre-coding matrix to use. Memory <NUM> may store data and software/firmware for the receiver system <NUM>. The reverse link message is then processed by a TX data processor <NUM>, which also receives traffic data for a number of data streams from a data source <NUM>, modulated by a modulator <NUM>, conditioned by transmitters (TMTR) 254a through 254r, and transmitted back to transmitter system <NUM>.

At transmitter system <NUM>, the modulated signals from receiver system <NUM> are received by antennas <NUM>, conditioned by receivers (RCVR) <NUM>, demodulated by a demodulator <NUM>, and processed by a RX data processor <NUM> to extract the reverse link message transmitted by the receiver system <NUM>. Processor <NUM> then determines which pre-coding matrix to use for determining the beamforming weights, and then processes the extracted message.

Any one of the processor <NUM>, RX data processor <NUM>, other processors/elements, or a combination thereof of the receiver system <NUM> and/or any one of the processor <NUM>, RX data processor <NUM>, other processors/elements, or a combination thereof of the transmitter system <NUM> may be configured to perform the procedures for low-density parity-check (LDPC) decoding in accordance with certain aspects of the present disclosure discussed below with reference to <FIG>. In an aspect, at least one of the processor <NUM> and RX data processor <NUM> may be configured to execute algorithms stored in memory <NUM> for performing the LDPC decoding described herein. In another aspect, at least one of the processor <NUM> and RX data processor <NUM> may be configured to execute algorithms stored in memory <NUM> for performing the LDPC decoding described herein.

Any one of the processor <NUM>, TX data processor <NUM>, other processors/elements, or a combination thereof of the receiver system <NUM> and/or any one of the processor <NUM>, TX MIMO processor <NUM>, TX data processor <NUM>, other processors/elements, or a combination thereof of the transmitter system <NUM> may be configured to perform the procedures for low-density parity-check (LDPC) encoding in accordance with certain aspects of the present disclosure discussed below with reference to <FIG>. In an aspect, at least one of the processor <NUM> and TX data processor <NUM> may be configured to execute algorithms stored in memory <NUM> for performing the LDPC encoding described herein. In another aspect, at least one of the processor <NUM>, TX MIMO processor <NUM>, and TX data processor <NUM> may be configured to execute algorithms stored in memory <NUM> for performing the LDPC encoding described herein.

<FIG> illustrates various components that may be utilized in a wireless device <NUM> that may be employed within the wireless communication system <NUM> illustrated in <FIG>. The wireless device <NUM> is an example of a device that may be configured to implement the various methods described herein. The wireless device <NUM> may be a Node B <NUM> (e.g., a TRP) or any of the wireless nodes (e.g., wireless nodes <NUM>, <NUM>, <NUM> or IoT device <NUM> or <NUM>). For example, the wireless device <NUM> may be configured to perform operations <NUM> and <NUM> described in <FIG> and <FIG>, as well as other operations described herein.

The wireless device <NUM> may include a processor <NUM> that controls operation of the wireless device <NUM>. The processor <NUM> may also be referred to as a central processing unit (CPU). Memory <NUM>, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor <NUM>. A portion of the memory <NUM> may also include non-volatile random access memory (NVRAM). The instructions in the memory <NUM> may be executable to implement the methods described herein, for example, to allow a UE to perform LDPC decoding and/or LDPC encoding. Some non-limiting examples of the processor <NUM> may include a Snapdragon processor, application specific integrated circuits (ASICs), programmable logic, etc..

The wireless device <NUM> may also include a housing <NUM> that may include a transmitter <NUM> and a receiver <NUM> to allow transmission and reception of data between the wireless device <NUM> and a remote location. The transmitter <NUM> and receiver <NUM> may be combined into a transceiver <NUM>. A single or a plurality of transmit antennas <NUM> may be attached to the housing <NUM> and electrically coupled to the transceiver <NUM>. The wireless device <NUM> may also include (not shown) multiple transmitters, multiple receivers, and multiple transceivers. The wireless device <NUM> can also include wireless battery charging equipment.

The wireless device <NUM> may also include a signal detector <NUM> that may be used in an effort to detect and quantify the level of signals received by the transceiver <NUM>. The signal detector <NUM> may detect such signals as total energy, energy per subcarrier per symbol, power spectral density and other signals. The wireless device <NUM> may also include a digital signal processor (DSP) <NUM> for use in processing signals.

Additionally, the wireless device may also include an encoder <NUM> for use in encoding signals for transmission and a decoder <NUM> for use in decoding received signals. According to certain aspects, the encoder <NUM> may perform encoding according to certain aspects presented herein (e.g., by implementing operations <NUM> illustrated in <FIG>). According to certain aspects, the decoder <NUM> may perform decoding according to certain aspects presented herein (e.g., by implementing operations <NUM> illustrated in <FIG>).

The various components of the wireless device <NUM> may be coupled together by a bus system <NUM>, which may include a power bus, a control signal bus, and a status signal bus in addition to a data bus. The processor <NUM> may be configured to access instructions stored in the memory <NUM> to perform LDPC decoding and/or LDPC encoding, in accordance with aspects of the present disclosure discussed below.

Many communications systems use error-correcting codes. Specifically, error-correcting codes compensate for the intrinsic unreliability of information transfer in these systems by introducing redundancy into the data stream. Low-density parity check (LDPC) codes are a particular type of error correcting codes which use an iterative coding system. In particular, Gallager codes are an early example of regular LDPC codes. LDPC codes are linear block codes in which most of the elements of its parity check matrix H are set to '<NUM>'.

LDPC codes can be represented by bipartite graphs (often referred to as "Tanner graphs"), wherein a set of variable nodes corresponds to bits of a code word (e.g., information bits or systematic bits), and a set of check nodes correspond to a set of parity-check constraints that define the code. Edges in the graph connect variable nodes to check nodes. Thus, the nodes of the graph are separated into two distinctive sets, variable nodes and check nodes, with edges connecting the two different types of nodes.

A lifted graph is created by copying a bipartite base graph (G), which may also be known as a protograph, a number of times, Z. A variable node and a check node may be considered "neighbors" if they are connected by an "edge" (i.e., the line connecting the variable node and the check node) in the graph. In addition, for each edge (e) of the bipartite base graph (G), a permutation is applied to the Z copies of edge (e) to interconnect the Z copies of G. A bit sequence having a one-to-one association with the variable node sequence is a valid codeword if, and only if, for each check node, the bits associated with all neighboring variable nodes sum to zero modulo two (i.e., they include an even number of <NUM>'s). The resulting LDPC code may be quasi-cyclic (QC) if the permutations used are cyclic.

<FIG> show graphical and matrix representations of an exemplary LDPC code, in accordance with certain aspects of the present disclosure. For example, <FIG> shows a bipartite graph <NUM> representing an exemplary LDPC code. The bipartite graph <NUM> includes a set of <NUM> variable nodes <NUM> (represented by circles) connected to <NUM> check nodes <NUM> (represented by squares). Edges <NUM> in the graph <NUM> connect variable nodes <NUM> to the check nodes <NUM> (represented by the lines connecting the variable nodes <NUM> to the check nodes <NUM>). This graph consists of |V| = <NUM> variable nodes and |C| = <NUM> check nodes, connected by |E| = <NUM> edges.

The bipartite graph may be represented by a simplified adjacency matrix, which may also be known as a parity check matrix. <FIG> shows a matrix representation <NUM> of the bipartite graph <NUM>. The matrix representation <NUM> includes a parity check matrix H and a code word vector x, where x<NUM>-x<NUM> represent bits of the code word x. The parity matrix H is used for determining whether a received signal was normally decoded. The parity check matrix H has C rows corresponding to j check nodes and V columns corresponding to i variable nodes (i.e., a demodulated symbol), where the rows represent the equations and the columns represents the bits of the code word. In <FIG>, matrix H has <NUM> rows and <NUM> columns corresponding to <NUM> check nodes and <NUM> variable nodes respectfully. If a j-th check node is connected to an i-th variable node by an edge, i.e., the two nodes are neighbors, then there is a <NUM> in the element at the i-th column and the j-th row of the parity check matrix H. That is, the intersection of an i-th row and a j-th column contains a "<NUM>" where an edge joins the corresponding vertices and a "<NUM>" where there is no edge joining the corresponding vertices. The code word vector x represents a valid code word if, and only if, Hx = <NUM> (e.g., if, for each constraint node, the bits neighboring the constraint (via their association with variable nodes) sum to zero modulo two, i.e., they comprise an even number of ones). Thus, if the code word is received correctly, then Hx = <NUM> (mod <NUM>). When the product of a coded received signal and the parity check matrix H becomes '<NUM>', this signifies that no error has occurred. The parity check matrix is a C row by V column binary matrix. The rows represent the equations and the columns represent the digits in the code word.

The number of demodulated symbols or variable nodes is the LDPC code length. The number of non-zero elements in a row is defined as the row weight dc. The number of non-zero elements in a column is defined as the column weight dv.

The degree of a node refers to the number of edges connected to that node. This feature is illustrated in the H matrix shown in <FIG> where the number of edges incident to a variable node <NUM> is equal to the number of <NUM>'s in the corresponding column and is called the variable node degree d(v). Similarly, the number of edges connected with a check node <NUM> is equal to the number of ones in a corresponding row and is called the check node degree d(c).

A regular graph or code is one for which all variable nodes have the same degree, j, and all constraint nodes have the same degree, k. In this case, the code may be referred to a (j,k) regular code. On the other hand, an irregular code has constraint nodes and/or variable nodes of differing degrees. For example, some variable nodes may be of degree <NUM>, others of degree <NUM> and still others of degree <NUM>.

"Lifting" enables LDPC codes to be implemented using parallel encoding and/or decoding implementations while also reducing the complexity typically associated with large LDPC codes. Lifting helps enable efficient parallelization of LDPC decoders while still having a relatively compact description. More specifically, lifting is a technique for generating a relatively large LDPC code from multiple copies of a smaller base code. For example, a lifted LDPC code may be generated by producing Z number of parallel copies of a base graph (e.g., protograph) and then interconnecting the parallel copies through permutations of edge bundles of each copy of the base graph. The base graph defines the (macro) structure of the code and consists of a number (K) of information bit-columns and a number (N) of code bit columns. Lifting the base graph a number (Z) of results in a final information block length of KZ. Some information bits can be shortened (set to <NUM>) to realize information block lengths less than KZ.

Thus, a larger graph can be obtained by a "copy and permute" operation where multiple copies of the base graph are made and connected to form a single lifted graph. For the multiple copies, like edges that are a set of copies of a single base edge, are permutated and connected to form a connected graph Z times larger than the base graph.

<FIG> graphically illustrates the effect of making three copies of the graph of <FIG>. Three copies may be interconnected by permuting like edges among the copies. If the permutations are restricted to cyclic permutations, then the resulting graph corresponds to a quasi-cyclic LDPC with lifting Z = <NUM>. The original graph from which three copies were made is referred to herein as the base graph. To obtain derived graphs of different sizes, one can apply the "copy and permute" operation to a base graph.

A corresponding parity check matrix of the lifted graph can be constructed from the parity check matrix of the base graph by replacing each entry in the base parity check matrix with a ZxZ matrix. The <NUM> entries (those having no base edges) are replaced with the <NUM> matrix and the <NUM> entries (indicating a base edge) are replaced with a ZxZ permutation matrix. In the case of cyclic liftings the permutations are cyclic permutations.

A cyclically lifted LDPC code can also be interpreted as a code over the ring of binary polynomials modulo xZ + <NUM>. In this interpretation, a binary polynomial, (x) = b<NUM> + b<NUM> x + b<NUM> x<NUM> +. + bZ-<NUM> xZ-<NUM> may be associated to each variable node in the base graph. The binary vector (b<NUM>, b<NUM>, b<NUM> ,. , bZ-<NUM>) corresponds to the bits associated to Z corresponding variable nodes in the lifted graph, that is, Z copies of a single base variable node. A cyclic permutation by k of the binary vector is achieved by multiplying the corresponding binary polynomial by xk, where multiplication is taken modulo xZ + <NUM>. A degree d parity check in the base graph can be interpreted as a linear constraint on the neighboring binary polynomials B<NUM>(x),. , Bd(x) written as xk1 B<NUM>(x) + xk2 B<NUM>(x) +. + xkd Bd(x) = <NUM> where the values, k<NUM>,. , kd are the cyclic lifting values associated to the corresponding edges.

This resulting equation is equivalent to the Z parity checks in the cyclically lifted Tanner graph corresponding to the single associated parity check in the base graph. Thus, the parity check matrix for the lifted graph can be expressed using the matrix for the base graph in which <NUM> entries are replaced with monomials of the form xk and <NUM> entries are lifted as <NUM>, but now the <NUM> is interpreted as the <NUM> binary polynomial modulo xZ + <NUM>. Such a matrix may be written by giving the value k in place of xk. In this case the <NUM> polynomial is sometimes represented as -<NUM> and sometimes as another character in order to distinguish it from x<NUM>.

Typically, a square submatrix of the parity check matrix represents the parity bits of the code. The complementary columns correspond to information bits that, at the time of encoding, are set equal to the information bits to be encoded. The encoding may be achieved by solving for the variables in the aforementioned square submatrix in order to satisfy the parity check equations. The parity check matrix H may be partitioned into two parts M and N where M is the square portion. Thus, encoding reduces to solving Me = s = Nd where c and d comprise x. In the case of quasi-cyclic codes, or cyclically lifted codes, the above algebra can be interpreted as being over the ring of binary polynomials modulo xZ + <NUM>. In the case of the IEEE <NUM> LDPC codes, which are quasi-cyclic, the encoding submatrix M has an integer representation as shown in <FIG>.

A received LDPC code word can be decoded to produce a reconstructed version of the original code word. In the absence of errors, or in the case of correctable errors, decoding can be used to recover the original data unit that was encoded. Redundant bits may be used by decoders to detect and correct bit errors. LDPC decoder(s) generally operate by iteratively performing local calculations and passing those results by exchanging messages within the bipartite graph <NUM>, along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. These steps may typically be repeated several times and may be referred to as message passing steps. For example, each variable node <NUM> in the graph <NUM> may initially be provided with a "soft bit" (e.g., representing the received bit of the code word) that indicates an estimate of the associated bit's value as determined by observations from the communications channel. Using these soft bits the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to, memory. The update operations are typically based on the parity check constraints of the corresponding LDPC code. In implementations for lifted LDPC codes, messages on like edges are often processed in parallel.

LDPC codes designed for high speed applications often use quasi-cyclic constructions with large lifting factors and relatively small base graphs to support high parallelism in encoding and decoding operations. LDPC codes with higher code rates (e.g., the ratio of the message length to the code word length) tend to have relatively fewer parity checks. If the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node), then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges (e.g., the variable node may have a "double edge"). Or if the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node), then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges. Having a base variable node and a base check node connected by two or more edges is generally undesirable for parallel hardware implementation purposes. For example, such double edges may result in multiple concurrent read and write operations to the same memory locations, which in turn may create data coherency problems. A double edge in a base LDPC code may trigger parallel reading of the same soft bit value memory location twice during a single parallel parity check update. Thus, additional circuitry is typically needed to combine the soft bit values that are written back to memory, so as to properly incorporate both updates. However, eliminating double edges in the LDPC code helps to avoid this extra complexity.

In the definition of standard irregular LDPC code ensembles (degree distributions), all edges in the Tanner graph representation may be statistically interchangeable. In other words, there exists a single statistical equivalence class of edges. A more detailed discussion of lifted LDPC codes may be found, for example, in the book titled, "<NPL>. For multi-edge LDPC codes, multiple equivalence classes of edges may be possible. While in the standard irregular LDPC ensemble definition, nodes in the graph (both variable and constraint) are specified by their degree, i.e., the number of edges they are connected to, in the multi-edge type setting an edge degree is a vector; it specifies the number of edges connected to the node from each edge equivalence class (type) independently. A multi-edge type ensemble is comprised of a finite number of edge types. The degree type of a constraint node is a vector of (non-negative) integers; the i-th entry of this vector records the number of sockets of the i-th type connected to such a node. This vector may be referred to as an edge degree. The degree type of a variable node has two parts, although the degree type can be viewed as a vector of (non-negative) integers. The first part relates to the received distribution and will be termed the received degree and the second part specifies the edge degree. The edge degree plays the same role as for constraint nodes. Edges are typed as they pair sockets of the same type. This constraint that sockets must pair with sockets of like type characterizes the multi-edge type concept. In a multi-edge type description, different node types can have different received distributions (e.g., the associated bits may go through different channels).

<FIG> illustrates a portion <NUM> of a radio frequency (RF) modem <NUM> that may be configured to provide an encoded message for wireless transmission. In one example, an encoder <NUM> in a base station (e.g., Node B <NUM> and/or transmitter system <NUM>) (or wireless node on the reverse path) receives information bits of a message <NUM> for transmission. The message <NUM> may contain data and/or encoded voice or other content directed to the receiving device. The encoder <NUM> encodes the message using a suitable modulation and coding scheme (MCS), typically selected based on a configuration defined by the base station or another network entity. In some cases, the encoder <NUM> may encode the message, for example, in accordance with aspects of the present disclosure (e.g., by implementing operations <NUM> illustrated in <FIG>). An encoded bitstream <NUM> produced by the encoder <NUM> may then be provided to a mapper <NUM> that generates a sequence of Tx symbols <NUM> that are modulated, amplified and otherwise processed by Tx chain <NUM> to produce an RF signal <NUM> for transmission through antenna <NUM>.

<FIG> illustrates a portion <NUM> of a RF modem <NUM> that may be configured to receive and decode a wirelessly transmitted signal including an encoded message (e.g., a message encoded using a LDPC code as described above). In various examples, the modem <NUM> receiving the signal may reside at the wireless node (e.g., wireless node <NUM>, receiver system <NUM>), at the base station (e.g., Node B <NUM>, transmitter system <NUM>), or at any other suitable apparatus or means for carrying out the described functions (e.g., wireless device <NUM>). An antenna <NUM> receives an RF signal <NUM> (e.g., the RF signal <NUM>, produced in <FIG>, as altered by the effective channel between RF chain <NUM> and RF chain <NUM>) for a wireless node (e.g., wireless node <NUM>, <NUM>, and/or receiver system <NUM>). An RF chain <NUM> processes and demodulates the RF signal <NUM> and may provide a sequence of demodulated symbols <NUM> to a demapper <NUM>, which produces a bitstream (e.g., a series of received values r_j, that may be referred to as soft bits or scaled soft bits and may be represented by log-likelihood ratios) <NUM> representative of the encoded message.

A decoder <NUM> may then be used to decode m-bit information strings from a bitstream that has been encoded using a coding scheme (e.g., an LDPC code). The decoder <NUM> may comprise a layered LDPC decoder with a full-parallel, row-parallel, or block-parallel architecture. LDPC decoder(s) generally operate by iteratively performing local calculations and passing those results by exchanging messages within the bipartite graph <NUM>, along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. These steps may typically be repeated several times and may be referred to as message passing steps. For example, each variable node <NUM> in the graph <NUM> may initially be provided with a "soft bit" (e.g., representing the received bit, r_j, of the codeword) that indicates an estimate of the associated bit's value as determined by observations from the communications channel. The "soft bit" may be represented by a log-likelihood ratio (LLR) that in some aspects may be defined as the log((probability the bit is <NUM>)/(probability the bit is <NUM>)). Using these LLRs, the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to, memory. The update operations are typically based on the parity check constraints of the corresponding LDPC code. In implementations for lifted LDPC codes, messages on like edges are often processed in parallel. According to aspects of the present disclosure, following these decoding techniques, the decoder <NUM> may decode the bitstream <NUM> based on the LLRs to determine the message <NUM> containing data, encoded voice and/or other content transmitted from the base station (e.g., Node B <NUM> and/or transmitter system <NUM>). The decoder may decode the bitstream <NUM> in accordance with aspects of the present disclosure presented below (e.g., by implementing operations <NUM> illustrated in <FIG>).

Low-density parity check (LDPC) coding is a powerful error correcting coding technology used in several applications such as wireless communications, storage, and Ethernet. LDPC is based on designing codes on bipartite graphs, for example, as described above and illustrated in <FIG>. LDPC decoding is typically implemented using belief propagation techniques, described above, where messages are passed along edges of the graph and the nodes in the graph compute their marginal distributions from which decisions on the source symbols can be made. Quasi-Cyclic (QC) codes are a popular class of structured LDPC codes where a base LDPC Parity Check Matrix (PCM) gets 'lifted'. For example, "lifting" entails replacing each base PCM entry with a ZxZ submatrix. The ZxZ submatrix can be a matrix of all zeros for '<NUM>' base PCM entries or a cyclically rotated identity matrix for '<NUM>' base PCM entries. QC LDPC codes enable parallel processing in hardware by enabling decoders, such as the decoder illustrated in <FIG>, to replicate processing Z times with switching networks to exchange messages.

LDPC decoders implement message passing algorithms which are often close approximations of the Belief Propagation (BP) algorithm. The log BP algorithm for LDPC decoding may be written as: <MAT> <MAT> <MAT> <MAT> <MAT> where L(c) is a log-likelihood ratio (LLR) associated to the binary variable c defined as <MAT> where the probability is conditioned on certain information implicit in the message passing algorithm that expands as the algorithm proceeds. The function Ψ is given by <MAT>. The index m generally denotes a binary parity check node or binary PCM row index, j and n generally denote is the bit node or PCM column index qj denotes the bit value associated to variable node j, equivalently to the j-th binary PCM column, and qmn denotes the binary value associated to the edge connecting variable node n to check node m. , N(m) is the set of all bit indices for bits connected to parity check node m, M(j) is the set of all parity check node indices for all parity check nodes connected to bit j, and Rj is the LLR for bit j associated to the transmission observation of bit j. For example, in a standard BPSK transmission over an AWGN channel we have <MAT> where rj is the received value, and σ<NUM> is the variance of the channel's additive noise. The algorithm may be initialized by setting L(qmj) equal to Rj and proceeds by repeated evaluation of the given equations. According to aspects of the present disclosure, Equation <NUM> computes a parity check metric Amj for bit j that sums the incoming bit LLRs L(qmn) for all bits connected to parity check node m (other than the LLR for bit j) through a transformation Ψ. This operation, along with Equation <NUM>, computes an a posteriori LLR, Rmj, for bit j based on observations of the other bits belonging to the parity check m. Equation <NUM> computes the sign, smj, of the a posteriori LLR, Rmj, based on the signs of the incoming bit LLRs L(qmn). Equation <NUM> calculates the updated bit LLRs, L(qj), by combining all of the a posteriori LLRs Rmj (i.e., extrinsic LLRs) from the decoder for bit j with the a priori LLR Rj from the channel (i.e., intrinsic LLR). Equation <NUM> subtracts the extrinsic LLR Rmj for parity check node m from the bit LLR sum L(qj) before the bit LLR sum L(qmj) is passed back to parity check node m for computation of an updated a posteriori and/or extrinsic LLR Rmj in the next iteration. For a 'flooding' LDPC decoder iteration, steps <NUM>-<NUM> (i.e., computing Equations <NUM>-<NUM>) are performed for all parity check nodes after which all bit (variable) nodes perform step <NUM> (i.e., compute Equation <NUM>) to update the bit LLRs L(qj).

Layered LDPC decoders perform steps similar to Equations <NUM>-<NUM> above, but with some slight modifications. For example, the layered log BP algorithm may be written as: <MAT> <MAT> <MAT> <MAT> <MAT>.

In the above layered decoding steps (i.e., Equations <NUM>-<NUM>), the bit LLRs L(qj) are initialized with the channel bit LLRs RjAccording to certain aspects of the present disclosure, a key difference between layered decoding (Equations <NUM>-<NUM>) and flooding decoding (Equations <NUM>-<NUM>) is that in a layered decoding iteration, when the a posteriori LLR, Rmj, is computed for a particular parity check node (PCM row) in Equation <NUM>, the bit LLRs L(qj) are immediately updated with the new a posteriori LLRs, Rmj, in Equation <NUM> before computing the next row's a posteriori LLRs Rmj in Equations <NUM>-<NUM>. This is in contrast to the flooding decoder, where all of the a posteriori LLRs, Rmj, corresponding to the PCM rows are computed (Equations <NUM>-<NUM> loop over all m and j) before all of the bit LLRs L(qj) are updated with the a posteriori LLRs, Rmj, in Equation <NUM>. As a result, layered decoding allows information, in the form of updated a posterior LLRs, Rmj, to propagate through the belief propagation message passing faster than a flooding decoder, which results in faster decoder convergence.

<FIG> illustrates a high-level block diagram of a generic layered LDPC decoder <NUM>, which may be an example of the decoder <NUM> illustrated in <FIG>. As illustrated, the layered LDPC decoder includes LLR storage memory <NUM> for storing bit LLRs (e.g., L(qj)) (i.e., one bit LLR per bit of the code word), which is initialized by the channel bit LLRs (e.g., <MAT>), which, in turn, are updated by a posteriori LLRs (e.g., Rmj). The channel bit LLRs or received LLRs are also known as soft bits or scaled soft bits, and the received value r_j is a soft bit. Layered LDPC decoder <NUM> also includes data path processors <NUM> that operate in parallel to compute a posteriori LLRs and update the stored bit LLRs in the LLR storage memory <NUM>. Layered LDPC decoder <NUM> additionally includes a metric storage memory <NUM> to store a posteriori LLRs computed by the data path processors <NUM> and a permutation network <NUM> to route LLRs (e.g., bit LLRs and a posteriori LLRs) between the memories <NUM>, <NUM> and the data path processors <NUM>.

As discussed above, layered decoding traverses PCM columns (bit LLRs) along a row in the PCM to compute a posteriori LLRs for that row. After a posteriori LLRs for the row are computed, the bit LLRs are each immediately updated with their corresponding a posteriori LLR as they are being fed to the computation of the a posteriori LLRs for the next row. If the column index of the updated bit LLR is connected to the next row, then the updated bit LLR is passed to the a posteriori LLR computation for that next row. If there is no connection, then the updated bit LLR can be stored in LLR storage memory <NUM>.

<FIG> illustrates an example of this process for computing/updating bit LLRs and a posteriori LLRs in a parity check matrix (PCM) <NUM> as described above. In particular, each cell of the PCM illustrates a calculated a posteriori LLR. For example, for the PCM illustrated in <FIG>, once the a posteriori LLRs for row <NUM>, labeled <NUM>, are computed, the bit LLR for column <NUM>, labeled <NUM>, may be updated (e.g., using Equation <NUM> from above) and used in the a posteriori LLR computation for row <NUM>, labeled <NUM> (e.g., using Equations <NUM>-<NUM> from above), since column <NUM> is connected to both rows <NUM> and <NUM> (e.g., PCM entries (<NUM>, <NUM>), labeled <NUM>, and (<NUM>, <NUM>), labeled <NUM>, are non-zero). However, when the bit LLR for column <NUM>, labeled <NUM>, is updated with an a posteriori LLR computed from row <NUM> (labeled <NUM>), the updated bit LLR is stored in memory (e.g., LLR storage memory <NUM>) because the a posteriori LLR computation for row <NUM> does not include column <NUM> given that (<NUM>, <NUM>), labeled <NUM>, is empty. When the a posteriori LLRs for row <NUM>, labeled <NUM>, are being computed, the bit LLR for column <NUM> is read from the memory (e.g., LLR storage memory <NUM>) rather than being passed from the prior update computation. It should also be noted that write and read conflicts are possible since Equations <NUM> and <NUM> can both read from and write to LLR Storage Memory <NUM>. Such conflicts can create delays in a processing pipeline, if the LLR Storage Memory <NUM> has just a single read and a single write port.

There can also be delays introduced due to the recursive processing where bit LLR updates for a row (layer) get passed to the a posteriori LLR processing for the next layer for which the computed a posteriori LLRs are used to update the bit LLRs again. For example, given a nonzero processing pipeline depth, there may be a gap between bit LLR update phases so that a posteriori LLR calculations can complete.

For example, <FIG> illustrates an example processing pipeline <NUM> showing this row-by-row processing for computing a posteriori LLRs and updating the bit LLRs based on the a posteriori LLRs. As illustrated in <FIG>, pipeline delays (e.g., gaps in the processing) <NUM>, <NUM>, <NUM>, and <NUM> are present due to recursive processing with an interdependency between the a posteriori computation (e.g., Equations <NUM>-<NUM>) and the bit LLR update steps (e.g., Equation <NUM>). The pipeline delays grow with increasing pipeline depth as well as memory conflicts, for example, as illustrated in example processing pipeline <NUM>, shown <FIG>, where it can be seen that an increase in pipeline depth to <NUM> cycles along with memory conflicts increases the number of processing cycles wasted due to pipeline delays <NUM>, <NUM>, <NUM>, and <NUM>. Thus, aspects of the present disclosure present techniques for mitigating pipeline delays in LDPC decoding, for example, by using a parity check matrix with full or quasi row-orthogonality, as described below in greater detail.

Layered LDPC decoders often have delays in update processes, for example, as described above. For example, in a check layered decoder, updates to variable node sums (e.g., a posteriori computation described above, for example, using Equations <NUM>-<NUM>) occur after the completion of a check layer update (e.g., the bit LLR update steps described above, for example, using Equation <NUM>) and the incorporation of these updates might be further delayed by additional processing steps and memory accesses. If the edge connectivity of the base LDPC code is such that variable nodes are connected to two consecutive layers, then there is potential for a negative impact to decoder performance. When the second such layer is processed, the updated variable node sum may not yet be available, so the potential gain from the previous layer processing is not available to, and does not benefit the performance of, that layer. In some cases, this lack of updated variable node sums may be circumvented by introducing additional delay. However, this additional delay may result in a slowing down of the decoder and potentially degrade performance through a reduction in total available iterations.

In some cases, the subsequent layers of an LDPC code can be constrained to be 'orthogonal', meaning that subsequent layers have no base variable nodes in common. Such a constraint can, however, degrade performance through the implied constraint on base graph structure, which limits the connectivity of the graph.

LDPC designs for <NUM> NR typically are rate compatible and have a high-rate core graph consisting of a first few layers (e.g., approximately <NUM> layers or rows) of the construction followed by hybrid automatic repeat request (HARQ) bit layers that are used to lower the rate of the code, for example, as illustrated in <FIG> and <FIG>. Note that <FIG> represent a parity check matrix when arranged as illustrated in <FIG>. That is, <FIG> shows rows <NUM>-<NUM> of a parity check matrix, and <FIG> shows rows <NUM>-<NUM> of the same parity check matrix.

In some cases, it may not be feasible to ensure orthogonality in the core graph. In recent LDPC designs for <NUM> NR, the base graphs have often included two relatively high degree punctured variable nodes (e.g., columns <NUM> and <NUM>) that are punctured, as illustrated in columns <NUM> and <NUM> in the matrix <NUM> in <FIG> and <FIG>. Optimization of the connectivity of the graph usually results in high connectivity (many edges) for those nodes, especially, in the first HARQ parity layers that are designed for use in relatively high rate transmissions. This has led to the notion of 'quasi-orthogonality,' which means that subsequent layers (e.g., subsequent to the core base graph layers) are orthogonal except on the high degree punctured nodes (and possibly the core parity bit formed from these two nodes), which may be repeatedly connected across subsequent layers. Most decoder implementations will then absorb the degradation due to delayed updates for the high degree punctured variable nodes.

According to aspects of the present disclosure, <FIG> illustrate an example of a lifted parity check matrix <NUM> that is quasi-row orthogonal. For example, each row may represent a layer, except for the first three demarked rows <NUM>, <NUM>, and <NUM> (see <FIG>), which represent labels. The first (top) row <NUM> contains labels that enumerate the columns of the matrix. The second row <NUM> contains labels that are encoding indicators, where a <NUM> indicates a systematic (information) column and a <NUM> indicates a parity column. The third row <NUM> contains labels that are transmission indicators, where a <NUM> indicates puncturing (i.e., no transmission) and a <NUM> indicates transmission.

According to aspects of the present disclosure, the first two columns <NUM> and <NUM> (see <FIG> and <FIG>) of the parity check matrix illustrated in <FIG> represent high degree punctured variable nodes, and column <NUM>, labeled <NUM> (see <FIG> and <FIG>), represents a special parity bit formed from the two punctured columns. The core portion of the graph consists of the first <NUM> rows (layers) and the HARQ rows start from the seventh row, labeled <NUM> (see <FIG>), down. Note that from the seventh row down no column has a non-empty entry in two consecutive rows other than columns <NUM>, <NUM>, and <NUM>, labeled <NUM>, <NUM>, and <NUM>. Thus, the parity check matrix illustrated in <FIG> and <FIG> is quasi-row orthogonal.

As HARQ layers are added and the corresponding transmission rate lowers, the connectivity of these nodes can be relaxed. Often, beyond a certain point as layers increase and target code rate decreases, the density of the connectivity of the punctured nodes decreases. In particular, at most one of the punctured nodes will typically be connected to each layer. If, in addition, the design has nearly balanced connectivity of the two punctured nodes, meaning that they each connect to approximately the same number of layers, then it is possible to achieve full orthogonality for those layers, for example, as illustrated in <FIG> and <FIG>.

As noted above, <FIG> illustrate, when arranged as shown in <FIG>, a similar parity check matrix <NUM> as the parity check matrix <NUM> illustrated in <FIG>, except that the parity check matrix <NUM> is fully pairwise row-orthogonal after the 14th row/layer <NUM> (see <FIG>). For example, as illustrated, row/layer <NUM> is the last layer where both punctured variable nodes (columns <NUM> and <NUM>, labeled <NUM> and <NUM>) are connected. All subsequent rows (layers) are pairwise fully orthogonal. For example, as illustrated, no two consecutive rows after row <NUM>, labeled <NUM>, have an entry in the matrix in the same column, thus making the rows after row <NUM> fully pairwise orthogonal with each other. Note that the high degree punctured variable nodes are connected in an alternating fashion, thus allowing the rows to be fully orthogonal.

According to aspects of the present disclosure, using the parity check matrix illustrated in <FIG> increases decoder performance, for example, by allowing for the most up-to-date variable check sums to be used in the process of decoding a row of the parity check matrix. For example, since no variable nodes are connected to two consecutive layers, the decoder has time to compute the updated variable check sums before the updated variable check sums are needed for processing another row.

Thus, aspects of the present disclosure propose techniques for increasing the availability of the updated variable node sums used during decoding without the performance degradation associated with adding additional delays during the decoding process (discussed above), for example, by maintaining full-layer orthogonality for all layers below the last layer in which the two punctured base variable nodes are both connected to the same layer. Such a constraint (e.g., full row orthogonality) results in an alternating structure where the two punctured nodes alternate connectivity to subsequent layers, for example, as illustrated in <FIG> and <FIG> (note, <FIG> illustrate one parity check matrix <NUM>, with <FIG> illustrating rows <NUM>-<NUM> of the parity check matrix <NUM> and <FIG> illustrating rows <NUM>-<NUM> of the parity check matrix <NUM>), and can result in orthogonality of approximately <NUM>/<NUM> (e.g., more than ½) of all layers.

<FIG> illustrates example operations <NUM> for wireless communications, for example, for reducing processing delays when decoding LDPC encoded bits. According to certain aspects, operations <NUM> may be performed by a wireless communications device (e.g., by a receiver and a decoder (e.g., decoder <NUM>) in the wireless communications device), such as a base station (e.g., Node B <NUM> and/or base station <NUM>), a user equipment (e.g., UE <NUM> and/or UE <NUM>), and/or wireless device <NUM>.

Operations <NUM> begin at block <NUM> by the wireless communications device receiving soft bits associated to an LDPC codeword. For example, UE <NUM> (e.g., a receiver of UE <NUM>) receives soft bits associated to an LDPC codeword from base station <NUM>.

At <NUM>, the wireless communications device performs LDPC decoding of the soft bits using a parity check matrix, wherein: each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected. Continuing the example from above, UE <NUM> (e.g., a decoder of UE <NUM>) performs LDPC decoding of the soft bits (i.e., the soft bits received in block <NUM>) using a parity check matrix (e.g., the parity check matrix <NUM> illustrated in <FIG> and <FIG>), wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.

<FIG> illustrates example operations <NUM> for wireless communications, for example, for performing LDPC encoding. According to certain aspects, operations <NUM> may be performed by a wireless communications device (e.g., by a transmitter and an encoder (e.g., encoder <NUM>) in the wireless communications device), such as a base station (e.g., Node B <NUM> and/or base station <NUM>), a user equipment (e.g., UE <NUM> and/or UE <NUM>), and/or wireless device <NUM>.

Operations <NUM> begin at block <NUM> by the wireless communications device obtaining information bits of a codeword. For example, UE <NUM> (e.g., an encoder of UE <NUM>) obtains information bits of a codeword (e.g., from an application running on the UE).

At <NUM>, the wireless communications device performs encoding of the information bits to compute parity bits of an LDPC codeword according to a parity check matrix, wherein: each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected. Continuing the example from above, UE <NUM> (e.g., an encoder of UE <NUM>) performs encoding of the information bits (i.e., the information bits obtained in block <NUM>) according to a parity check matrix (e.g., the parity check matrix <NUM> illustrated in <FIG> and <FIG>), wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.

In some cases, rather than actually transmitting a frame, a device may have an interface to output a frame for transmission. For example, a processor may output a frame, via a bus interface, to an RF front end for transmission. Similarly, rather than actually receiving a frame, a device may have an interface to obtain a frame received from another device. For example, a processor may obtain (or receive) a frame, via a bus interface, from an RF front end for transmission.

For example, means for computing, means for determining, means for utilizing, means for updating, means for reading, means for performing, and/or means for selecting may comprise a processing system including one or more processors, such as processor <NUM> and/or RX Data Processor <NUM> of the base station <NUM> and/or the processor <NUM> and/or RX Data Processor <NUM> of the user terminal <NUM>. Additionally, means for storing may comprise a memory, such as the memory <NUM> of the base station <NUM> and/or the memory <NUM> of the user terminal <NUM>. Further, means for receiving may comprise a receiver and/or antenna, such as the receiver <NUM> and/or antenna <NUM> of the base station <NUM> and/or the receiver <NUM> and/or antenna <NUM> of the user terminal <NUM>.

In the case of a wireless node (see <FIG>), a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus.

Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a wireless node and/or base station as applicable. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a wireless node and/or base station can obtain the various methods upon coupling or providing the storage means to the device.

Claim 1:
A method for performing quasi-cyclic low-density parity-check, QC-LDPC, decoding for hybrid automatic repeat request, HARQ, transmission using a QC-LDPC rate-compatible design, the method comprising:
receiving soft bits associated to a QC-LDPC codeword (<NUM>) of a QC-LDPC code of the QC-LDPC rate-compatible design; and
performing QC-LDPC decoding of the soft bits using a parity check matrix (<NUM>) of the QC-LDPC code obtained by lifting an LDPC base graph,
wherein the parity check matrix comprises:
a first plurality of rows representing a core portion (<NUM>) corresponding to a high-rate QC-LDPC code and a second plurality of HARQ rows after the first plurality of rows used to lower the rate of the high-rate of the QC-LDPC code;
each row of the first and second plurality of rows of the parity check matrix comprises non-empty entries each with an integer value representing a ZxZ cyclic rotated identity matrix or empty entries each representing a ZxZ all-zero submatrix;
at least two columns wherein two columns (<NUM>, <NUM>) correspond to two high-degree punctured variable nodes of the LDPC base graph;
at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected and at least two rows below a lowest row (<NUM>) of said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected; and
wherein the parity check matrix has row orthogonality between each pair of consecutive rows that are below said lowest row of said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected (<NUM>) in that no column has a non-empty entry in each pair of consecutive rows that are below said lowest row of said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected; and characterized in that
the two high-degree punctured variable nodes of the LDPC base graph alternate, from row to row, their respective row connectivity for all rows in the parity check matrix, below said lowest row of said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected.