Patent Description:
Generally, alternating current (AC) machines are considered required assets in various applications, such as power generation, transportation and traction applications like electric vehicles, and the like, as their reliability is much higher than that of the DC machines. In such applications, it is required to control speed of a motor (e.g. an AC motor or a direct current (DC) motor) to a given reference. Various methods have been proposed to control the speed of the motor to the given reference. Initially, a conventional method of voltage-frequency control is proposed to control the speed of the motor to the given reference by changing frequency of a supplied voltage and keeping a ratio between the supplied voltage and the frequency applied to the motor. Another conventional method of direct torque control (DTC) is devised by calculating a magnetic flux and torque of the motor based on measured parameters, such as voltage and current at the motor terminals. The conventional DTC method includes a direct control of the magnetic flux and torque of the motor, but due to a finite number of states of a conventional power converter, torque ripple is very high. Thus, the conventional DTC method is rarely used. Thereafter, another conventional method of field-oriented control (FOC) is proposed to control the speed of the motor to the given reference. The conventional FOC method includes a separate control of the magnetic flux and torque of the motor, therefore, achieves the required speed of the motor with partial case.

The conventional power converter provides the required voltage and frequency which can be regulated by use of pulse-width modulation (PWM). An input DC voltage of the conventional power converter is converted into an AC sine-wave output voltage by fast switching of power transistors. Such type of the conventional power converter is also known as a conventional voltage-source inverter (VSI), for example, a conventional two-level VSI. The AC sine-wave output voltage generated by the conventional power converter (or the conventional VSI) is further converted into an AC output current by use of a low-pass filter. In the conventional AC machines, stator inductances and resistances act as the low-pass filter. Furthermore, the torque of the motor is directly proportional to the AC output current. Therefore, any ripple or oscillation of the torque is then translated into ripple or oscillation in the current (and vise versa), so the current quality is directly related to the torque quality and the torque quality is responsible for smooth operation of the conventional AC machines with decreased vibration or jerking. The conventional multilevel VSIs have low modulation index (MI) when a connected AC machine is operated at a low speed region. The low MI (e.g. MI < <NUM>) results into an increased current ripple which further results into an increased torque ripple. The increased torque ripple results into vibration and jerking of the conventional AC machines at the low speed region. Therefore, the vibration and jerking of the conventional AC machines become unavoidable at the low speed region. Currently, certain attempts have been made to improve the current quality and hence, the torque quality of the conventional AC machines at the low speed region. In an example, a conventional three-level VSI (<NUM>-VSI) may be used in power electronics applications including motor applications or automotive applications due to partially improved current quality and efficiency. The two generally used topologies of the conventional <NUM>-VSI are named as neutral point clamped (NPC) and T-type VSI. To further improve the current quality in the conventional <NUM>-VSI, a sine wave reference may be used with injected harmonics and this method is known as space-vector PWM (SVPWM). The SVPWM method manifests high MI value, therefore, the current quality is slightly improved in comparison to a conventional sine-wave PWM. The current quality of the conventional <NUM>-VSI with the SVPWM method can further be improved by increasing the frequency (or switching frequency) of PWM, however, this combination has certain limitations. For example, the power transistors of the conventional <NUM>-VSI have limited turn-on/off speed, therefore, a maximum switching frequency is limited by the power transistors. Moreover, high switching frequency causes higher switching losses which further results into a reduced efficiency. Therefore, despite of using the conventional <NUM>-VSI with the SVPWM and increased switching frequency, the performance of the conventional AC machines at the low speed region (or with the low MI) is very low which further results into vibrations and jerking of the conventional AC machines. Thus, there exists a technical problem of vibrations and jerking of the conventional AC machines at the low speed region.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional methods of operating the conventional AC machines at the low speed region.

<NPL> discloses generalized PWM schemes for a n-phase voltage source inverter (VSI). <NPL> discloses a generalized pulse width modulation (PWM)-based control algorithm for multiphase neutral-point-clamped (NPC) converter.

The present disclosure provides a method for generating control signals for a multi-level power converter, a controller device for the multi-level power converter and AC machine drives. The present disclosure provides a solution to the existing problem of vibrations and jerking of the conventional AC machines when operated at a low speed. An objective of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art and provides an improved method for generating control signals for a multi-level power converter, a controller device for the multi-level power converter and AC machine drives that manifest smooth operation at the low speed region with reduced vibration or jerking.

One or more objectives of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

In one aspect, the present disclosure provides a computer implemented method for generating a set of pulse-width modulation (PWM) control signals for a multi-level power converter. The method comprises generating a base reference signal for each of three or more reference phases. The method further comprises determining a maximum reference (max) and minimum reference (min) based on the base reference signals and calculating a reference sum of the maximum reference and the minimum reference. The method further comprises generating a first offset, calculated as <NUM>-max when the reference sum is positive and -<NUM>-min when the reference sum is negative. The method further comprises generating a second offset, calculated as -<NUM>-min when the reference sum is positive and <NUM>-max when the reference sum is negative. For each of the three reference phases, the method further comprises generating an upper reference, calculated by adding the first offset to the base reference signal when the signal is positive and adding the second offset when the signal is negative. For each of the three reference phases, the method further comprises generating a lower reference, calculated by adding the second offset to the base reference signal when the signal is positive and adding the first offset when the signal is negative. For each of the three reference phases, the method further comprises comparing the upper reference to a triangular upper carrier signal to generate an upper PWM output and comparing the lower reference to a triangular lower carrier signal to generate a lower PWM output. For each of the three reference phases, the method further comprises combining the upper PWM output and lower PWM output to generate a multi-level PWM control signal for the reference phase. The method further comprises outputting a set of multi-level PWM control signals generated for the three or more reference phases to the multi-level power converter.

The disclosed method provides a smooth operation of an AC machine at a low speed region with reduced vibration or jerking. The disclosed method uses two different reference voltages (i.e. the upper reference and the lower reference) with respect to each of the three or more reference phases in order to generate the set of multi-level PWM control signals for the multi-level power converter. Therefore, the method manifests an improved performance (i.e. an improved current quality and torque quality or reduced current ripples and torque ripples) of the AC machine when operated at the low speed region with reduced vibration or jerking. In contrast to a conventional SVPWM method which uses a single reference voltage in order to generate PWM control signals for a conventional power converter and hence, manifests low performance (i.e. reduced current quality and torque quality or more current ripples and torque ripples) of a conventional AC machine when operated at the low speed region.

In an implementation form, calculating the maximum reference comprises comparing a first base reference signal for a first reference phase to a second base reference signal for a second reference phase. If the first base reference signal is larger, comparing the first base reference signal with a third base reference signal for a third reference phase and returning the larger value and if the second base reference signal is larger, comparing the second base reference signal with the third base reference signal and returning the larger value.

The maximum reference calculated by comparison of each of the base reference signals with respect to each other results into a more precise value of the maximum reference.

In a further implementation form, calculating the minimum reference comprises comparing a first base reference signal for a first reference phase to a second base reference signal for a second reference phase. If the first base reference signal is smaller, comparing the first base reference signal with a third base reference signal for a third reference phase and returning the smaller value and if the second base reference signal is smaller, comparing the second base reference signal with the third base reference signal and returning the smaller value.

The minimum reference calculated by comparison of each of the base reference signals with respect to each other results into a more precise value of the minimum reference.

In a further implementation form, the reference phases are <NUM> degrees, <NUM> degrees and <NUM> degree for <NUM> phase machines.

The references phases are used to generate an auxiliary phase which further causes rotation of an AC motor comprised by an AC machine.

In a further implementation form, the base signal is a sine wave.

It is advantageous to use the sine wave as the base signal to reduce switch over peaks.

In a further implementation form, the base signal is a space vector signal.

It is advantageous to use the space vector signal as the base signal to incorporate simplicity.

In a further implementation form, generating the base reference signals comprises receiving a speed reference and a torque reference for an AC machine drive and determining an amplitude for the base reference signals based on the received speed reference.

The speed reference is used to determine the amplitude of the base reference signals with more precision.

In another aspect, the present disclosure provides a computer-readable medium comprising instructions which, when executed by a processor, cause the processor to execute the method.

The processor achieves all the advantages and effects of the method of the present disclosure after execution of the method.

In a yet another aspect, the present disclosure provides a controller device for a multi-level power converter, configured to generate a set of multi-level pulse-width modulation (PWM) control signals by executing the method and output the generated set of multi-level PWM control signals to the multi-level power converter.

The controller device enables a smooth operation of an AC machine drive at a low speed region without any change in topology or switching frequency of the multi-level power converter.

In a yet another aspect, the present disclosure provides an alternating current (AC) machine drive comprising an AC motor with three or more phase input terminals. The AC machine drive further comprises a direct current (DC) input voltage source and a multi-level voltage source inverter (VSI) configured to receive an input DC voltage from the DC input voltage source and generate an AC driving signal for each of the three or more phase input terminals. The AC machine drive further comprises the controller device configured to output a set of multi-level pulse-width modulation (PWM) control signals to the multi-level VSI.

The AC machine drive comprising the AC motor with three or more phase input terminals is used for conversion of an electrical energy into a rotational magnetic energy without overheating, braking or degeneration. Moreover, the disclosed AC machine drive operates smoothly at a low speed region without any vibration or jerking.

In an implementation form, the multi-level VSI is one of a neutral-point clamped VSI, a T-type VSI, a flying capacitor VSI.

The multi-level VSI is one of the neutral-point clamped VSI, the T-type VSI, or the flying capacitor VSI to provide the smooth operation of the AC machine drive at the low speed region without any change in switching frequency.

In a yet another aspect, the present disclosure provides an alternating current (AC) machine drive comprising an AC generator with three or more phase output terminals. The AC machine drive further comprises a direct current (DC) output voltage source and a multi-level rectifier, configured to receive an input AC voltage from each of the three or more phase output terminals of the AC generator and generate an output DC voltage at the DC output voltage source. The AC machine drive further comprises the controller device configured to output a set of multi-level pulse-width modulation (PWM) control signals to the multi-level rectifier.

The AC machine drive comprising the AC generator with three or more phase output terminals is used for conversion of a rotational magnetic energy into an electrical energy without overheating, braking or degeneration. Moreover, the disclosed AC machine drive operates smoothly at a low speed region with reduced vibration or jerking.

In an implementation form, the multi-level rectifier is one of a Vienna Rectifier, T-type Rectifier, Neutral-Point Clamped Rectifier, Active Neutral-Point Clamped Rectifier, Flying Capacitor Rectifier.

The multi-level rectifier may be one of the Vienna Rectifier, T-type Rectifier, Neutral-Point Clamped Rectifier, Active Neutral-Point Clamped Rectifier, or Flying Capacitor Rectifier to provide the smooth operation of the AC machine drive at the low speed region without any change in switching frequency.

It is to be appreciated that all the aforementioned implementation forms can be combined.

It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof.

<FIG> and <FIG> collectively is a flowchart of a method for generating a set of pulse-width modulation (PWM) control signals for a multi-level power converter, in accordance with an embodiment of the present disclosure. With reference to <FIG> and <FIG>, there is shown a method <NUM> for generating a set of pulse-width modulation (PWM) control signals for a multi-level power converter. The method <NUM> includes steps <NUM> to <NUM> (steps <NUM>-<NUM> of the method <NUM> are shown in <FIG> and steps <NUM>-<NUM> are shown in <FIG>). The method <NUM> is executed by a processor of a controller device, described in detail, for example, in <FIG>.

The present disclosure provides a computer implemented method (i.e. the method <NUM>) for generating a set of pulse-width modulation, PWM, control signals for a multi-level power converter, the method <NUM> comprising:.

outputting a set of multi-level PWM control signals generated for the three or more reference phases to the multi-level power converter.

With reference to <FIG>, the method <NUM> is used for generating a set of pulse-width modulation (PWM) control signals for a multi-level power converter. The method <NUM> corresponds to a modulation method used to generate the set of PWM control signals for the multi-level power converter. The set of PWM control signals are generated by encoding amplitude of a signal (e.g. a sinusoidal signal) into a pulse width of another signal. Generally, the set of PWM control signals are used to control a power that is supplied to various types of electrical devices, such as an AC motor or a DC motor. The set of PWM control signals are used as on or off commands for the multi-level power converter. The multi-level power converter is described in detail, for example, in <FIG>.

At step <NUM>, the method <NUM> comprises generating a base reference signal for each of three or more reference phases. In an example, the base reference signal may be a sinusoidal signal or a sine wave for each of three or more references phases.

At step <NUM>, the method <NUM> further comprises determining a maximum reference (max) and minimum reference (min) based on the base reference signals. The base reference signal(s) for each of three or more references phases are compared with each other to determine the maximum reference (max) and the minimum reference (min).

At step <NUM>, the method <NUM> further comprises calculating a reference sum of the maximum reference and the minimum reference. The calculated reference sum (i.e. max+min) of the maximum reference (max) and the minimum reference (min) is further used for obtaining two offsets.

At step <NUM>, the method <NUM> further comprises generating a first offset, calculated as <NUM>-max when the reference sum is positive and -<NUM>-min when the reference sum is negative. In a case, if the reference sum is positive (i.e. max+min > <NUM>) then, the first offset (i.e. offset <NUM>) is <NUM>-max, else (i.e. max+min < <NUM>), the first offset (i.e. offset <NUM>) is -<NUM>-min.

At step <NUM>, the method <NUM> further comprises generating a second offset, calculated as -<NUM>-min when the reference sum is positive and <NUM>-max when the reference sum is negative. In another case, if the reference sum is positive (i.e. max+min > <NUM>) then, the second offset (i.e. offset <NUM>) is -<NUM>-min, else (i.e. max+min < <NUM>), the second offset (i.e. offset <NUM>) is <NUM>-max.

At step <NUM>, the method <NUM> further comprises for each of the three reference phases, generating an upper reference, calculated by adding the first offset to the base reference signal when the signal is positive and adding the second offset when the signal is negative. In an example, the base reference signal(s) for each of the three references phases may be represented as A*, B* and C*, respectively. The step <NUM> may be described with respect to the one base reference signal, for example, A*. When the base reference signal (i.e. A*) is positive, the upper reference (i.e. Atop - AT) is generated by adding the first offset (i.e. offset <NUM>) to the base reference signal (i.e. A*) according to the equation <NUM> <MAT>.

When the base reference signal (i.e. A*) is negative, the upper reference (i.e. AT) is generated by adding the second offset (i.e. offset <NUM>) to the base reference signal (i.e. A*) according to the equation <NUM> <MAT>.

Similar to the base reference signal A*, the upper reference (i.e. Btop-BT, Ctop-CT) is generated for the base reference signals B* and C*, respectively.

Now, referring to <FIG>, at step <NUM>, the method <NUM> further comprises for each of the three reference phases, generating a lower reference, calculated by adding the second offset to the base reference signal when the signal is positive and adding the first offset when the signal is negative. Similar to the step <NUM>, the step <NUM> is also described with respect to the base reference signal, A*. When the base reference signal (i.e. A*) is positive, the lower reference (i.e. Abottom - AB) is generated by adding the second offset (i.e. offset <NUM>) to the base reference signal (i.e. A*) according to the equation <NUM> <MAT>.

Similarly, when the base reference signal (i.e. A*) is negative, the lower reference (i.e. AB) is generated by adding the first offset (i.e. offset <NUM>) to the base reference signal (i.e. A*) according to the equation <NUM> <MAT>.

Similar to the base reference signal A*, the lower reference (i.e. Bbottom - BB, Cbottom -CB) is generated for the base reference signals B* and C*, respectively. In this way, two different reference voltages (i.e. the upper reference (i.e. AT, BT, CT) and the lower reference (i.e. AB, BB, CB)) are generated for each of the three reference phases. Therefore, due to the two different reference voltages (i.e. the upper reference and the lower reference), the method <NUM> may also be referred as a double reference PWM (DRPWM).

At step <NUM>, the method <NUM> further comprises for each of the three reference phases, comparing the upper reference to a triangular upper carrier signal to generate an upper PWM output. For example, the generated upper reference (i.e. AT) for the base reference signal A* is compared with the triangular upper carrier to generate the upper PWM output. Similarly, the generated upper reference (i.e. BT, CT) for the base reference signals, B* and C*, respectively, is compared with the triangular upper carrier to generate the upper PWM output.

At step <NUM>, the method <NUM> further comprises for each of the three reference phases, comparing the lower reference to a triangular lower carrier signal to generate a lower PWM output. For example, the generated lower reference (i.e. AB) for the base reference signal A* is compared with the triangular lower carrier to generate the lower PWM output. Similarly, the generated lower reference (i.e. BB, CB) for the base reference signals, B* and C*, respectively, is compared with the triangular lower carrier to generate the lower PWM output.

At step <NUM>, the method <NUM> further comprises for each of the three reference phases, combining the upper PWM output and lower PWM output to generate a multi-level PWM control signal for the reference phase. For example, the upper PWM output and the lower PWM output of the base reference signal (i.e. A*) are combined to generate the multi-level PWM control signal for the reference phase. Similarly, the multi-level PWM control signal is generated for the base reference signals B* and C*, respectively.

At step <NUM>, the method <NUM> further comprises outputting a set of multi-level PWM control signals generated for the three or more reference phases to the multi-level power converter. The two different reference voltages (i.e. the upper reference and the lower reference) of the base reference signal (i.e. A*) are compared with two different triangular carriers (i.e. the triangular upper carrier and the triangular lower carrier) to produce the set of PWM control signal for the reference phase. Similarly, the set of multi-level PWM control signals may be generated for the three or more reference phases and applied to the multi-level power converter. The ratio between the upper reference (i.e. AT) of the base reference signal (i.e. A*) and the triangular upper carrier is termed as a modulation index (MI). Similarly, the ratio between the lower reference (i.e. AB) of the base reference signal (i.e. A*) and the triangular lower carrier may also be termed as the modulation index (MI).

In accordance with an embodiment, calculating the maximum reference comprises comparing a first base reference signal for a first reference phase to a second base reference signal for a second reference phase. If the first base reference signal is larger, comparing the first base reference signal with a third base reference signal for a third reference phase and returning the larger value. If the second base reference signal is larger, comparing the second base reference signal with the third base reference signal and returning the larger value. For example, in a case, the first base reference signal (i.e. A*) for the first reference phase is compared with the second base reference signal (i.e. B*) for the second reference phase and the first base reference signal (i.e. A*) has larger value. Thereafter, the first base reference signal (i.e. A*) is further compared with the third base reference signal (i.e. C*) for the third reference phase and the first base reference signal (i.e. A*) has larger value on comparison. Then, in such a case, the maximum reference is associated with the first base reference signal (i.e. A*). In another case, if the second base reference signal (i.e. B*) has larger value in comparison to the first base reference signal (i.e. A*), therefore, the second base reference signal (i.e. B*) is further compared with the third base reference signal (i.e. C*) and the second base reference signal (i.e. B*) has larger value on comparison. Then, in such a case, the maximum reference is associated with the second base reference signal (i.e. B*). In a yet another case, if the third base reference signal (i.e. C*) has larger value in comparison to the first base reference signal (i.e. A*) and the second base reference signal (i.e. B*), then, in such a case, the maximum reference is associated with the third base reference signal (i.e. C*).

In accordance with an embodiment, calculating the minimum reference comprises comparing a first base reference signal for a first reference phase to a second base reference signal for a second reference phase. If the first base reference signal is smaller, comparing the first base reference signal with a third base reference signal for a third reference phase and returning the smaller value. If the second base reference signal is smaller, comparing the second base reference signal with the third base reference signal and returning the smaller value. For example, in a case, the first base reference signal (i.e. A*) for the first reference phase is compared with the second base reference signal (i.e. B*) for the second reference phase and the first base reference signal (i.e. A*) has smaller value. Thereafter, the first base reference signal (i.e. A*) is further compared with the third base reference signal (i.e. C*) for the third reference phase and the first base reference signal (i.e. A*) has smaller value on comparison. Then, in such a case, the minimum reference is associated with the first base reference signal (i.e. A*). In another case, if the second base reference signal (i.e. B*) has smaller value in comparison to the first base reference signal (i.e. A*), therefore, the second base reference signal (i.e. B*) is further compared with the third base reference signal (i.e. C*) and the second base reference signal (i.e. B*) has smaller value on comparison. Then, in such a case, the minimum reference is associated with the second base reference signal (i.e. B*). In a yet another case, if the third base reference signal (i.e. C*) has smaller value in comparison to the first base reference signal (i.e. A*) and the second base reference signal (i.e. B*), then, in such a case, the minimum reference is associated with the third base reference signal (i.e. C*).

In accordance with an embodiment, the reference phases are <NUM> degrees, <NUM> degrees and <NUM> degrees. In an implementation, the references phases are <NUM> degrees, <NUM> degrees and <NUM> degrees.

In accordance with an embodiment, the base signal is a sine wave. The base signal (or the base reference signals, such as A*, B*, C*) for each of the three or more references phases is the sine wave or the sinusoidal signal.

In accordance with an embodiment, the base signal is a space vector signal. In an implementation, the base signal (or the base reference signals, such as A*, B*, C*) for each of the three or more references phases may be the space vector signal in order to ease the functioning of an AC machine.

In accordance with an embodiment, generating the base reference signals comprises receiving a speed reference for an AC machine drive and determining an amplitude for the base reference signals based on the received speed reference. The base reference signals (i.e. A*, B* or C*) for each of the three reference phases are generated based on the received speed reference for the AC machine drive. The received speed reference is used to determine the amplitude of the base reference signals (i.e. A*, B* or C*) for each of the three reference phases. The received speed reference for the AC machine drive may also be used to determine the MI to be applied to the multi-level power converter. The received speed reference for the AC machine drive is proportional to the MI. Alternatively, the relation between the received speed reference for the AC machine drive and the MI can also be explained as a relation between a back-electromotive force (EMF) of a motor (e.g. an AC motor or a DC motor) and DC voltage source of the multi-level power converter, according to equation <NUM> <MAT> where, VEMF is the voltage produced by the motor (i.e. the AC motor or the DC motor), rotating at a certain speed ω and can be expressed according to equation <NUM> <MAT> where, KT is a motor constant and depends on physical parameters of the AC machine drive and is different for each machine.

The torque for the AC machine drive is proportional to the current and the KT of the AC machine drive according to equation <NUM> <MAT>.

In this way, the torque quality of the AC machine drive is directly proportional to the current quality of the VSI or Rectifier.

Thus, the method <NUM> uses two different reference voltages (i.e. the upper reference (i.e. AT, BT, CT) and the lower reference (i.e. AB, BB, CB)) with respect to each of the three or more reference phases in order to generate the set of multi-level PWM control signals for the multi-level power converter. Therefore, the method <NUM> manifests an improved performance (i.e. an improved current quality and torque quality) of the AC machine drive when operated at a low speed region with reduced vibration or jerking. In contrast to a conventional SVPWM method which uses a single reference voltage in order to generate PWM control signals for a conventional power converter and hence, manifests low performance (i.e. reduced current quality and torque quality) a conventional AC machine when operated at the low speed region.

The steps <NUM> to <NUM> are only illustrative and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

<FIG> is a block diagram that illustrates various exemplary components of a multi-level power converter, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG> and <FIG>. With reference to <FIG> there is shown a block diagram <NUM> of a multi-level power converter <NUM>. The multi-level power converter <NUM> includes a controller device <NUM>. The controller device <NUM> includes a memory <NUM> and a processor <NUM>.

The multi-level power converter <NUM> may comprise suitable logic, circuitry, interfaces, and/or code that is configured to vary an output voltage between three or more voltage levels. Therefore, the multi-level power converter <NUM> may be used for generation of high voltage levels with smaller voltage steps, and therefore improved voltage waveforms with reduced filtering requirements and reduced switching frequency (and consequently reduced switching losses and reduced common mode voltage). In an example, the multi-level power converter <NUM> may be used in an induction or a synchronous motor drive(s) for various industrial applications, or high voltage DC (HVDC) system, flexible AC transmission systems (FACTS), static VAR compensators (SVC), or static VAR generators (SVG), and the like.

The controller device <NUM> may comprise suitable logic, circuitry, interfaces, and/or code that is configured to generate a set of multi-level pulse-width modulation (PWM) control signals and output the generated set of multi-level PWM control signals to the multi-level power converter <NUM>. The controller device <NUM> generates the set of multi-level PWM control signals by executing the method <NUM> (of <FIG> and <FIG>).

The memory <NUM> includes suitable logic, circuitry, or interfaces that is configured to store the instructions executable by the processor <NUM>. Examples of implementation of the memory <NUM> may include, but are not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Random Access Memory (RAM), Read Only Memory (ROM), Hard Disk Drive (HDD), Flash memory, Solid-State Drive (SSD), or CPU cache memory. The memory <NUM> may store an operating system or other program products (including one or more operation algorithms) to operate the controller device <NUM>.

The processor <NUM> includes suitable logic, circuitry, or interfaces that is configured to execute the instructions stored in the memory <NUM>. In an example, the processor <NUM> may be a general-purpose processor. Other examples of the processor <NUM> may include, but is not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) processor, an application-specific integrated circuit (ASIC) processor, a reduced instruction set (RISC) processor, a very long instruction word (VLIW) processor, a central processing unit (CPU), a state machine, a data processing unit, and other processors or control circuitry. Moreover, the processor <NUM> may refer to one or more individual processors, processing devices, a processing unit that is part of a machine, such as the controller device <NUM>.

In accordance with an embodiment, a computer-readable medium comprising instructions which, when executed by the processor <NUM>, cause the processor <NUM> to execute the method <NUM> (of <FIG> and <FIG>).

<FIG> is a block diagram that illustrates various exemplary components of an alternating current (AC) machine drive, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, and <FIG>. With reference to <FIG> there is shown a block diagram <NUM> of an AC machine drive <NUM>. The AC machine drive <NUM> includes an AC motor <NUM> with three or more phase input terminals <NUM>. The AC machine drive <NUM> further includes a direct current (DC) input voltage source <NUM>, a multi-level voltage source inverter (VSI) <NUM> and the controller device <NUM>.

The AC machine drive <NUM> may include suitable logic, circuitry, or interfaces that is configured to precisely operate and control the speed, torque and direction of the AC motor <NUM>. In an example, the AC machine drive <NUM> may be used to change the speed of the AC motor <NUM> by changing voltage and frequency supplied to the AC motor <NUM>.

The AC motor <NUM> with three or more phase input terminals <NUM> may also be referred to as a rotating electrical machine that is designed to operate at three or more phases supply voltage as input and produce mechanical energy (or rotation) as output.

The DC input voltage source <NUM> may include suitable logic, circuitry, or interfaces that is configured to provide a constant DC output voltage across its terminals. In an example, the DC input voltage source <NUM> may receive a higher or a lower input voltage than a desired input voltage, in such a case, the DC input voltage source <NUM> may comprise a circuitry to change the higher or the lower input voltage in order to generate a desired output voltage. The output of the DC input voltage source <NUM> is provided as an input to the multi-level voltage source inverter (VSI) <NUM> and thus, is referred to as the DC input voltage source <NUM>.

The multi-level VSI <NUM> may include suitable logic, circuitry, or interfaces that is configured to receive an input DC voltage from the DC input voltage source <NUM> and generate an AC driving signal for each of the three or more phase input terminals <NUM>.

In accordance with an embodiment, the multi-level VSI <NUM> is one of a neutral-point clamped VSI, a T-type VSI, a flying capacitor VSI. The multi-level VSI <NUM> may be one of the neutral-point clamped VSI, the T-type VSI, or the flying capacitor VSI to provide the smooth operation of the AC machine drive <NUM> at the low speed region without any change in switching frequency. The multi-level VSI <NUM> from one of the neutral-point clamped VSI, the T-type VSI, or the flying capacitor VSI does not require any change in switching frequency when used with the method <NUM> (of <FIG> and <FIG>).

The controller device <NUM> is further configured to output a set of multi-level PWM control signals to the multi-level VSI <NUM> comprised by the AC machine drive <NUM>.

<FIG> is a block diagram that illustrates various exemplary components of an alternating current (AC) machine drive, in accordance with another embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, <FIG>. With reference to <FIG> there is shown a block diagram <NUM> of an AC machine drive <NUM>. The AC machine drive <NUM> includes an AC generator <NUM> with three or more phase output terminals <NUM>. The AC machine drive <NUM> further includes DC output voltage source <NUM>, a multi-level rectifier <NUM> and the controller device <NUM>.

The AC machine drive <NUM> may include suitable logic, circuitry, or interfaces that is configured to precisely operate and control the speed, torque and direction of the AC generator <NUM>.

The AC generator <NUM> with three or more phase output terminals <NUM> may also be referred to as an electrical machine that is designed to operate or receive mechanical energy (i.e. rotation energy for rotor) as input and produce an electrical energy of three or more phases as output.

The DC output voltage source <NUM> may include suitable logic, circuitry, or interfaces that is configured to provide a fixed DC output voltage across its terminals. In an example, the DC output voltage source <NUM> may receive varying DC input voltage from the multi-level rectifier <NUM> and provides a constant DC output voltage.

The multi-level rectifier <NUM> may include suitable logic, circuitry, or interfaces that is configured to receive an input AC voltage from each of the three or more phase output terminals <NUM> of the AC generator <NUM> and generate an output DC voltage at the DC output voltage source <NUM>.

In accordance with an embodiment, the multi-level rectifier <NUM> is one of a Vienna Rectifier, T-type Rectifier, Neutral-Point Clamped Rectifier, Active Neutral-Point Clamped Rectifier, Flying Capacitor Rectifier. The multi-level rectifier <NUM> may be one of the Vienna Rectifier, T-type Rectifier, Neutral-Point Clamped Rectifier, Active Neutral-Point Clamped Rectifier, or Flying Capacitor Rectifier to provide the smooth operation of the AC machine drive <NUM> at the low speed region without any change in switching frequency. The multi-level rectifier <NUM> from one of the Vienna Rectifier, T-type Rectifier, Neutral-Point Clamped Rectifier, Active Neutral-Point Clamped Rectifier, or Flying Capacitor Rectifier does not require any change in switching frequency when used with the method <NUM> (of <FIG> and <FIG>).

The controller device <NUM> is further configured to output a set of multi-level PWM control signals to the multi-level rectifier <NUM>.

<FIG> is a graphical representation that illustrates generation of two different reference voltages, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, <FIG>, and <FIG>. With reference to <FIG> there is shown a graphical representation 500A that illustrates generation of two different reference voltages (e.g. an upper reference and a lower reference) using the method <NUM> (of <FIG> and <FIG>).

The graphical representation 500A represents a first base reference signal <NUM> (i.e. A*) for a first reference phase, a second base reference signal <NUM> (i.e. B*) for a second reference phase and a third base reference signal <NUM> (i.e. C*) for a third reference phase. The graphical representation 500A further represents a maximum reference <NUM> (also represented as max). The maximum reference <NUM> (i.e. max) represents a largest value which is obtained by comparing the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*) with respect to each other. Similarly, the graphical representation 500A represents a minimum reference <NUM> (also represented as min). The minimum reference <NUM> (i.e. min) represents a smallest value which is obtained by comparing the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*) with respect to each other. The graphical representation 500A further represents a reference sum <NUM> (i.e. max+min) that is obtained by addition of the maximum reference <NUM> (i.e. max) and the minimum reference <NUM> (i.e. min). The graphical representation 500A further represents a first offset <NUM> (i.e. offset <NUM>), calculated as <NUM>-max when the reference sum <NUM> (i.e. max+min) is positive and -<NUM>-min when the reference sum <NUM> (i.e. max+min) is negative. The graphical representation 500A further represents a second offset <NUM> (i.e. offset <NUM>), calculated as -<NUM>-min when the reference sum <NUM> (i.e. max+min) is positive and <NUM>-max when the reference sum <NUM> (i.e. max+min) is negative.

Further, in the graphical representation 500A, the generation of two different reference voltages (e.g. upper reference and lower reference) is described with respect to the first base reference signal <NUM> (i.e. A*) for sake of simplicity.

The graphical representation 500A further represents an upper reference <NUM> (i.e. AT) which is calculated by adding the first offset <NUM> (i.e. offset <NUM>) to the first base reference signal <NUM> (i.e. A*) when the first base reference signal <NUM> (i.e. A*) is positive, according to the equation <NUM>, and adding the second offset <NUM> (i.e. offset <NUM>) when the first base reference signal <NUM> (i.e. A*) is negative, according to the equation <NUM>. The graphical representation 500A further represents a lower reference <NUM> (i.e. AB) which is calculated by adding the second offset <NUM> (i.e. offset <NUM>) to the first base reference signal <NUM> (i.e. A*) when the first base reference signal <NUM> (i.e. A*) is positive, according to the equation <NUM>, and adding the first offset <NUM> (i.e. offset <NUM>) when the first base reference signal <NUM> (i.e. A*) is negative, according to the equation <NUM>. Similar to the first base reference signal <NUM> (i.e. A*), the upper reference (i.e. BT, CT) and the lower reference (i.e. BB, CB) for the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*), respectively, are generated (not shown here) by following the method <NUM> (of <FIG> and <FIG>).

The upper reference <NUM> (i.e. AT) and the lower reference <NUM> (i.e. AB) with respect to the first base reference signal <NUM> (i.e. A*) are further used to generate a set of PWM control signals for the multi-level power converter (e.g. the multi-level power converter <NUM>), described in detail, for example, in <FIG>.

<FIG> is a graphical representation that illustrates generation of a set of PWM control signals for the multi-level power converter, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. With reference to <FIG> there is shown a graphical representation 500B that illustrates generation of a set of PWM control signals for the multi-level power converter <NUM> (of <FIG>).

The graphical representation 500B represents a triangular upper carrier signal <NUM> and a triangular lower carrier signal <NUM>. The graphical representation 500B further represents an upper PWM output <NUM> and a lower PWM output <NUM>. The upper PWM output <NUM> is obtained by comparing the upper reference <NUM> (i.e. AT) to the triangular upper carrier signal <NUM>. Similarly, the lower PWM output <NUM> is obtained by comparing the lower reference <NUM> (i.e. AB) to the triangular lower carrier signal <NUM>. The graphical representation 500B further represents a multi-level PWM control signal <NUM> for the reference phase (i.e. A). The multi-level (e.g. <NUM> or more) PWM control signal <NUM> is generated by combining the upper PWM output <NUM> and lower PWM output <NUM>. The multi-level PWM control signal <NUM> manifests three intermediate states, such as a positive state 530A (also represented as a P-state), a zero state 530B (also represented as a O-state) and a negative state 530C (also represented as a N-state). During execution of the method <NUM> (of <FIG> and <FIG>), the intermediate states changes from the positive state 530A (i.e. the P-state) to the negative state 530C (i.e. the N-state) through the zero state 530B (i.e. the O-state) and from the negative state 530C (i.e. the N-state) to the positive state 530A (i.e. the P-state) through the zero state 530B (i.e. the O-state). However, in the conventional SVPWM method, changes are from the P-state to the O-state and then from the O-state to the N-state without any intersection. Therefore, the method <NUM> (of <FIG> and <FIG>) results into a reduction of an output current ripple, happening close to zero-crossing region and hence, into an improved performance of the AC machine drives (e.g. the AC machine drive <NUM> and the AC machine drive <NUM>).

<FIG> is a graphical representation that illustrates generation of an output current on passing a multi-level PWM voltage output through a low pass filter, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. With reference to <FIG> there is shown a graphical representation <NUM> that illustrates generation an output current on passing the multi-level PWM voltage output <NUM> (of <FIG>) through a low pass filter (not shown here).

The graphical representation <NUM> represents an output current <NUM> (also represented as I or IDR) generated as the multi-level PWM voltage output <NUM> is active. An increment in the output current <NUM> (i.e. I) is lower for a short region(s), owing to usage of the three intermediate states (or <NUM> active states) such as the positive state 530A (i.e. P-state), the zero state 530B (i.e. O-state) and the negative state 530C (i.e. N-state) and similar width of the positive state 530A (i.e. P-state) and the negative state 530C (i.e. N-state). Therefore, the output current ripple cannot increase rapidly as the output current <NUM> (i.e. I) is always shifted back with a faster rate in comparison to the conventional SVPWM method. However, for the same region in the conventional SVPWM method, an output current (i.e. ISV) increases rapidly, and results into a reduced performance of a conventional AC machine(s).

<FIG> is a flowchart of exemplary operations that illustrates generation of two different reference voltages, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. With reference to <FIG> there is shown a flowchart <NUM> that includes operations <NUM> to <NUM>. The operations <NUM> to <NUM> in the flowchart <NUM> are executed by the processor <NUM> of the controller device <NUM>.

At operation <NUM>, the control of the flowchart <NUM> moves to start.

At operation <NUM>, the first base reference signal <NUM> (i.e. A*) is compared with the second base reference signal <NUM> (i.e. B*). If the first base reference signal <NUM> (i.e. A*) has larger value than the second base reference signal <NUM> (i.e. B*), then, the operation <NUM> is executed, else, the operation <NUM> is executed.

At operation <NUM>, the first base reference signal <NUM> (i.e. A*) is further compared with the third base reference signal <NUM> (i.e. C*). If the first base reference signal <NUM> (i.e. A*) has larger value than the third base reference signal <NUM> (i.e. C*), then, the operation <NUM> is executed, else, the operation <NUM> is executed.

At operation <NUM>, the second base reference signal <NUM> (i.e. B*) is further compared with the third base reference signal <NUM> (i.e. C*). If the second base reference signal <NUM> (i.e. B*) has larger value than the third base reference signal <NUM> (i.e. C*), then, the operation <NUM> is executed, else, the operation <NUM> is executed.

At operation <NUM>, it is found that the first base reference signal <NUM> (i.e. A*) has a largest value after comparison of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*). Therefore, the maximum reference <NUM> (i.e. max) is associated with the first base reference signal <NUM> (i.e. A*).

At operation <NUM>, it is found that the third base reference signal <NUM> (i.e. C*) has a largest value after comparison of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*). Therefore, the maximum reference <NUM> (i.e. max) is associated with the third base reference signal <NUM> (i.e. C*).

At operation <NUM>, it is found that the second base reference signal <NUM> (i.e. B*) has a largest value after comparison of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*). Therefore, the maximum reference <NUM> (i.e. max) is associated with the second base reference signal <NUM> (i.e. B*).

The operations <NUM> to <NUM> are executed in order to determine the maximum reference <NUM> (i.e. max) based on the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*).

At operation <NUM>, the first base reference signal <NUM> (i.e. A*) is compared with the second base reference signal <NUM> (i.e. B*). If the first base reference signal <NUM> (i.e. A*) has smaller value than the second base reference signal <NUM> (i.e. B*), then, the operation <NUM> is executed, else, the operation <NUM> is executed.

At operation <NUM>, the first base reference signal <NUM> (i.e. A*) is further compared with the third base reference signal <NUM> (i.e. C*). If the first base reference signal <NUM> (i.e. A*) has smaller value than the third base reference signal <NUM> (i.e. C*), then, the operation <NUM> is executed, else, the operation <NUM> is executed.

At operation <NUM>, the second base reference signal <NUM> (i.e. B*) is further compared with the third base reference signal <NUM> (i.e. C*). If the second base reference signal <NUM> (i.e. B*) has smaller value than the third base reference signal <NUM> (i.e. C*), then, the operation <NUM> is executed, else, the operation <NUM> is executed.

At operation <NUM>, it is found that the first base reference signal <NUM> (i.e. A*) has a smallest value after comparison of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*). Therefore, the minimum reference <NUM> (i.e. min) is associated with the first base reference signal <NUM> (i.e. A*).

At operation <NUM>, it is found that the third base reference signal <NUM> (i.e. C*) has a smallest value after comparison of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*). Therefore, the minimum reference <NUM> (i.e. min) is associated with the third base reference signal <NUM> (i.e. C*).

At operation <NUM>, it is found that the second base reference signal <NUM> (i.e. B*) has a smallest value after comparison of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*). Therefore, the minimum reference <NUM> (i.e. min) is associated with the second base reference signal <NUM> (i.e. B*).

The operations <NUM> to <NUM> are executed in order to determine the minimum reference <NUM> (i.e. min) based on the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*).

At operation <NUM>, it is checked that the reference sum <NUM> (i.e. max+min) is positive or negative. If the reference sum <NUM> (i.e. max+min) is positive, the operation <NUM> is executed, else, the operation <NUM> is executed.

At operation <NUM>, the first offset <NUM> (i.e. offset <NUM>) is computed as <NUM>-max (i.e. the maximum reference <NUM>) when the reference sum <NUM> (i.e. max+min) is positive and the second offset <NUM> (i.e. offset <NUM>) is computed as -<NUM>-min (i.e. the minimum reference <NUM>) when the reference sum <NUM> (i.e. max+min) is positive.

At operation <NUM>, the first offset <NUM> (i.e. offset <NUM>) is computed as -<NUM>-min (i.e. the minimum reference <NUM>) when the reference sum <NUM> (i.e. max+min) is negative and the second offset <NUM> (i.e. offset <NUM>) is computed as <NUM>-max (i.e. the maximum reference <NUM>) when the reference sum <NUM> (i.e. max+min) is negative.

The operations <NUM> to <NUM> are executed in order to determine the first offset <NUM> (i.e. offset <NUM>) and the second offset <NUM> (i.e. offset <NUM>) based on the maximum reference <NUM> (i.e. max), the minimum reference <NUM> (i.e. min) and the reference sum <NUM> (i.e. max+min).

At operation <NUM>, it is checked that each of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*) is positive or negative. If each of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*) is positive, then, the operation <NUM> is executed, else, the operation <NUM> is executed.

At operation <NUM>, the upper reference <NUM> (i.e. AT, BT, CT) is generated by adding the first offset <NUM> (i.e. offset <NUM>) to each of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*) and the lower reference <NUM> (i.e. AB, BB, CB) is generated by adding the second offset <NUM> (i.e. offset <NUM>) to each of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*), when each of the base reference signals <NUM>, <NUM> and <NUM> is positive.

At operation <NUM>, the upper reference <NUM> (i.e. AT, BT, CT) is generated by adding the second offset <NUM> (i.e. offset <NUM>) to each of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*), and the lower reference <NUM> (i.e. AB, BB, CB) is generated by adding the first offset <NUM> (i.e. offset <NUM>) to each of the first base reference signal <NUM> (i.e. A*), the second base reference signal <NUM> (i.e. B*) and the third base reference signal <NUM> (i.e. C*), when each of the base reference signals <NUM>, <NUM> and <NUM> is negative.

<FIG> is a graphical representation that illustrates reduction of an output current ripple of the AC machine drive after a double reference PWM (DRPWM) method is applied, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. With reference to <FIG> there is shown a graphical representation 800A that illustrates reduction of an output current ripple of the AC machine drive (e.g. the AC machine drive <NUM> or the AC machine drive <NUM>) after the DRPWM method is applied to the AC machine drive. The DRPWM method corresponds to the method <NUM> (of <FIG> and <FIG>).

The graphical representation 800A represents an output current <NUM> generated by use of the conventional SVPWM method and an output current <NUM> generated by use of the method <NUM> (i.e. the DRPWM method). A ripple amplitude of the output current <NUM> is reduced in comparison with a ripple amplitude of the output current ripple <NUM>. The output current <NUM> is generated by use of the method <NUM> (i.e. the DRPWM method) without any change in topology or switching frequency of the multi-level power converter <NUM> in contrast to the conventional SVPWM method, where change is required in topology or switching frequency of the conventional power converter to reduce the ripple amplitude of the output current <NUM>.

<FIG> is a graphical representation that illustrates reduction of a torque ripple of the AC machine drive after the DRPWM method is applied, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. With reference to <FIG> there is shown a graphical representation 800B that illustrates reduction of a torque ripple of the AC machine drive (e.g. the AC machine drive <NUM> or the AC machine drive <NUM>) after the method <NUM> (i.e. the DRPWM method) is applied to the AC machine drive.

The graphical representation 800B represents a torque ripple <NUM> generated by applying the conventional SVPWM method to the conventional AC machine and a torque ripple <NUM> generated by applying the method <NUM> (i.e. the DRPWM method) to either the AC machine drive <NUM> or the AC machine drive <NUM>. The torque ripple <NUM> is reduced in comparison the torque ripple <NUM>. The torque ripple <NUM> is generated by use of the method <NUM> (i.e. the DRPWM method) without any change in topology or switching frequency of the multi-level power converter <NUM> in contrast to the conventional SVPWM method, where change is required in topology or switching frequency of the conventional power converter to reduce the torque ripple <NUM>.

<FIG> is a graphical representation that illustrates reduction of a neutral point voltage of the multilevel VSI after the DRPWM method is applied, in accordance with an embodiment of the present disclosure. <FIG> is described in conjunction with elements from <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>. With reference to <FIG> there is shown a graphical representation 800C that illustrates reduction of a neutral point voltage of the multilevel VSI (e.g. the AC machine drive <NUM> or the multilevel VSI <NUM>) after the method <NUM> (i.e. the DRPWM method) is applied to the multilevel VSI.

The graphical representation 800C represents a neutral point oscillation <NUM> generated by applying the conventional SVPWM method to the conventional multilevel VSI and a neutral point oscillation <NUM> generated by applying the method <NUM> (i.e. the DRPWM method) to either the multilevel VSI connected to AC machine drive <NUM> or the multilevel VSI connected to AC machine drive <NUM>. The neutral point oscillation <NUM> is an oscillation of voltages across capacitors connected from positive and negative buses to a neutral point. The neutral point oscillation <NUM> is reduced substantially in comparison the neutral point oscillation <NUM>. The neutral point oscillation <NUM> is generated by use of the method <NUM> (i.e. the DRPWM method) without any change in topology or switching frequency of the multi-level power converter <NUM> in contrast to the conventional SVPWM method, where change is required in components sizes or additional compensation methods of the neutral point are required to reduce the neutral point oscillation <NUM>.

Claim 1:
A computer implemented method (<NUM>) for generating a set of pulse-width modulation, PWM, control signals for a multi-level power converter (<NUM>), the method (<NUM>) comprising:
generating a base reference signal (<NUM>, <NUM>, <NUM>) for each of three or more reference phases,
characterized in that the method further comprises:
determining a maximum reference, max, (<NUM>) and minimum reference, min, (<NUM>) based on the base reference signals (<NUM>, <NUM>, <NUM>);
calculating a reference sum (<NUM>) of the maximum reference (<NUM>) and the minimum reference (<NUM>);
generating a first offset (<NUM>), calculated as <NUM>-max when the reference sum (<NUM>) is positive and -<NUM>-min when the reference sum (<NUM>) is negative;
generating a second offset (<NUM>), calculated as -<NUM>-min when the reference sum (<NUM>) is positive and <NUM>-max when the reference sum (<NUM>) is negative;
for each of the three reference phases:
generating an upper reference (<NUM>), calculated by adding the first offset (<NUM>) to the base reference signal (<NUM>, <NUM>, <NUM>) when the signal (<NUM>, <NUM>, <NUM>) is positive and adding the second offset (<NUM>) when the signal (<NUM>, <NUM>, <NUM>) is negative;
generating a lower reference (<NUM>), calculated by adding the second offset (<NUM>) to the base reference signal (<NUM>, <NUM>, <NUM>) when the signal (<NUM>, <NUM>, <NUM>) is positive and adding the first offset (<NUM>) when the signal (<NUM>, <NUM>, <NUM>) is negative;
comparing the upper reference (<NUM>) to a triangular upper carrier signal (<NUM>) to generate an upper PWM output (<NUM>);
comparing the lower reference (<NUM>) to a triangular lower carrier signal (<NUM>) to generate a lower PWM output (<NUM>); and
combining the upper PWM output (<NUM>) and lower PWM output (<NUM>) to generate a multi-level PWM control signal (<NUM>) for the reference phase; and
outputting a set of multi-level PWM control signals generated for the three or more reference phases to a multi-level power converter (<NUM>).