Patent Description:
The present disclosure relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device and a semiconductor device.

With the improvement in the integration level of the semiconductor device, the size of the structures in the semiconductor device is gradually reduced and the distribution density thereof is gradually increased. The increasing distribution density of the structures leads to the reducing spacing between the structures, making it more likely to cause dielectric breakdown or parasitic capacitance for the conductive structures. Therefore, the effective electrical isolation of adjacent conductive structures has become a focus of the current manufacturing process of the semiconductor device.

At present, air spacer layers are usually formed on two sidewalls of the conductive structure to reduce the parasitic capacitance between adjacent structures, so as to improve the electrical isolation effect. Specifically, during the manufacturing process of the semiconductor device, a sacrificial layer is generally formed on the sidewall of the conductive structure, and a high-selectivity dry cleaning machine is used to etch the sacrificial layer to form the air spacer layer. The width of the required air spacer layer is very small, usually no more than <NUM>. In the actual manufacturing process, it is hard to completely remove such a narrow sacrificial layer by etching, and the etching of the etching agent on the sacrificial layer is not uniform. As a result, the air spacer layer formed has poor surface uniformity, which reduces the electrical isolation effect of the air spacer layer, thereby affecting the electrical performance of the semiconductor device.

Background may be found in <CIT>, <CIT>, <CIT>, <CIT>, <CIT> and <CIT>.

The present application is defined in appended independent claims <NUM> and <NUM> to which reference should be made.

In order to facilitate the understanding of the present disclosure, the present disclosure is described more completely below with reference to the accompanying drawings. The accompanying drawings show the preferred implementations of the present disclosure. The present closure is embodied in various forms without being limited to the embodiments set forth herein. On the contrary, these embodiments are provided for a more thorough and comprehensive understanding of the present disclosure.

It should be noted that when a component is fixed with the other component, the component may be fixed with the other component directly or via an intermediate component. When a component is connected with the other component, the component may be connected with the other component directly or via an intermediate component. The terms "vertical", "horizontal", "left", "right", "upper", "lower", "front", "rear", "peripheral" and similar expressions used herein are described based on the orientations or positions shown in the accompanying drawings. These terms are merely intended to facilitate and simplify the description of the present disclosure, rather than to indicate or imply that the mentioned device or component must have a specific orientation or must be constructed and operated in a specific orientation. Therefore, these terms should not be understood as a limitation to the present disclosure.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present disclosure. The terms mentioned herein are merely for the purpose of describing specific embodiments, rather than to limit the present disclosure. The term "and/or" used herein includes any and all combinations of one or more of the associated listed items.

An air gap can be formed between a bit line and a storage node contact structure to strengthen the insulation effect between the bit line and the storage node contact structure. The process of forming the air gap using the traditional technology includes: form a conductive structure to be isolated; form an inner dielectric layer, a sacrificial layer and an outer dielectric layer sequentially outwards on a sidewall of the conductive structure; form polysilicon in contact with the outer dielectric layer; and finally remove the sacrificial layer by using a high-selectivity etching agent to form an air gap separating the conductive structure and the polysilicon. Since the width of the required air gap is very small, the width of the corresponding sacrificial layer is also very small, usually no more than <NUM>. In the actual manufacturing process, it is hard to completely remove such a narrow sacrificial layer by etching, and the etching of the etching agent on the sacrificial layer is not uniform, such that the surrounding surface forming the air gap is not uniform. As a result, the electrical isolation effect of the air gap is reduced, thereby affecting the electrical performance of the semiconductor device.

In order to overcome the above shortcomings, the present disclosure provides an improved manufacturing method of a semiconductor device and a semiconductor device. In the present disclosure, part of a sacrificial layer is exposed to make the sacrificial layer contact and react with the outside, so as to completely remove the sacrificial layer. In this way, the original etching method can be replaced, thereby avoiding the problems that it is hard to remove the narrow sacrificial layer by using the traditional technology and the etching causes poor surface uniformity around the air gap.

Specifically, as shown in <FIG>, in an embodiment of the present disclosure, the improved manufacturing method of a semiconductor device includes:
S100: Provide a substrate.

The substrate may include a monocrystalline silicon substrate, a silicon-on-insulator (SOI) substrate, a stacked silicon-on-insulator (SSOI) substrate, a stacked silicon-germanium-on-insulator (S-SiGeOI) substrate, a silicon-germanium-on-insulator (SiGeOI) substrate or a germanium-on-insulator (GeOI) substrate, etc. In the embodiments of the present disclosure, the substrate includes a monocrystalline silicon substrate.

Further, referring to <FIG> and <FIG>, a trench isolation structure <NUM> may be provided in a substrate <NUM> to define a plurality of active regions (AR) in the substrate <NUM>, and the plurality of ARs may be arranged in a staggered array. Specifically, the trench isolation structure <NUM> includes silicon oxide. Each AR may present a pillar shape extending in a third direction D3, and the ARs may be arranged parallel to each other. The center of one AR may be adjacent to an end part of another adjacent AR.

S200: Form a plurality of first structures extending in a first direction on the substrate.

Referring to <FIG> and <FIG>, a plurality of first structures <NUM> extending in a first direction D1 are formed on the substrate <NUM>. Specifically, each of the first structures <NUM> includes a conductive structure <NUM> and an isolation sidewall <NUM> located on a sidewall of the conductive structure <NUM>. The conductive structure <NUM> includes a bit line <NUM> extending in the first direction D1.

Further, the conductive structure <NUM> may include a bit line plug <NUM> and a bit line <NUM> which are stacked. The bit line plug <NUM> is located between the bit line <NUM> and the substrate <NUM>. The isolation sidewall <NUM> includes silicon nitride, and may also include other dielectric material. The bit line plug <NUM> includes an epitaxial structure. The bit line <NUM> includes tungsten, and may also include aluminum, copper, nickel or cobalt. In an embodiment, a barrier layer is provided between the bit line <NUM> and the bit line plug <NUM>, and the barrier layer includes titanium nitride. In an embodiment, a bit line protection structure <NUM> is formed on the bit line <NUM>, and the bit line protection structure <NUM> includes silicon nitride.

In an embodiment, a plurality of second structures <NUM> extending in a second direction D2 may be formed in the substrate <NUM>. The second direction D2 crosses the first direction D1. Preferably, the second direction D2 is perpendicular to the first direction D1. Specifically, each of the second structures <NUM> may include a buried word line <NUM> extending in the second direction D2. A top surface of the buried word line <NUM> is lower than a top surface of the substrate <NUM>, and a word line protection structure <NUM> extending from the buried word line <NUM> to the top surface of the substrate <NUM> is formed on the buried word line <NUM>. The buried word line <NUM> includes tungsten, and the word line protection structure <NUM> includes silicon nitride, silicon oxide or silicon oxynitride, etc. Further, a gate oxide layer <NUM> is provided between the buried word line <NUM> and the substrate <NUM>. The gate oxide layer <NUM> includes silicon dioxide. A barrier layer may further be formed between the gate oxide layer <NUM> and the buried word line <NUM>. The barrier layer includes titanium nitride.

Step <NUM>: Form a sacrificial layer on sidewalls of the first structures.

Referring to <FIG>, the last removed sacrificial layer is located on two sidewalls of each first structure <NUM> extending in the first direction D1, and a top surface of the sacrificial layer is not lower than top surfaces of the conductive structures <NUM>. In this way, air gaps formed after the sacrificial layer is removed achieve a desirable electrical isolation effect between the conductive structures <NUM> and a storage node contact structure formed subsequently. Specifically, as shown in <FIG>, step S300 may include:.

As shown in <FIG>, a complete sacrificial layer <NUM> is deposited on the exposed surfaces of the substrate <NUM> and the first structures <NUM> through a deposition process, and then the sacrificial layer <NUM> is etched back to remove part of the sacrificial layer <NUM> on the substrate <NUM>, thereby forming a sacrificial layer <NUM>" on sidewalls of the first structures <NUM>. Further, under the same etching conditions, the sacrificial layer <NUM> may be made of a material with a larger etching selectivity than that of the first structures, so as to facilitate the complete removal of the sacrificial layer later. The deposition process includes chemical vapor deposition (CVD) or atomic layer deposition (ALD). In the embodiments of the present disclosure, the ALD process is used. Specifically, as shown in <FIG>, step S320 may include:
S321: Perform a first etching on the sacrificial layer, such that a top surface of the sacrificial layer after the first etching is flush with top surfaces of the conductive structures, or higher than the top surfaces of the conductive structures and lower than top surfaces of the hard mask structures.

As shown in <FIG>, the hard mask structures are located above the conductive structures <NUM>, and the hard mask structures may be made of the same material as the bit line protection structures <NUM>. In an embodiment, the bit line protection structures <NUM> may also include hard mask structures. By performing a first etching on the sacrificial layer <NUM>, a sacrificial layer <NUM>' may be obtained, and a top surface of the sacrificial layer <NUM>' is not lower than top surfaces of the conductive structures <NUM>.

As shown in <FIG>, an inner spacer layer <NUM> with the same thickness may be deposited on a top surface of the sacrificial layer <NUM>' and exposed surfaces of the hard mask structures through a deposition process. The inner spacer layer <NUM> conformally covers the exposed surfaces of the sacrificial layer <NUM>' and the hard mask structures. By etching the inner spacer layer <NUM> downward, part of the inner spacer layer <NUM> on the top surface of the sacrificial layer <NUM>' and the inner spacer layer <NUM> on the top surfaces of the hard mask structures are removed, and the inner spacer layer <NUM> on the sidewalls of the hard mask structures is retained, thereby obtaining an inner spacer layer <NUM>'.

S324: Perform a second etching on the sacrificial layer using the inner spacer layer after the first etching as a mask, so as to form a sacrificial layer on sidewalls of the first structures.

As shown in <FIG>, a second etching is performed on the sacrificial layer <NUM>' using the inner spacer layer <NUM>' as a mask. Part of the sacrificial layer <NUM>' on the substrate <NUM> is removed, and the sacrificial layer <NUM>' on the sidewalls of the first structures <NUM> (that is, the sidewalls of the isolation sidewalls <NUM> away from the conductive structures <NUM>) is retained, thereby obtaining a sacrificial layer <NUM>". The sacrificial layer <NUM>" needs to be removed later to form air gaps.

The inner spacer layer <NUM>' is provided above the sacrificial layer <NUM>" to facilitate the etching of the sacrificial layer <NUM>' and to well seal the subsequently formed air gaps, thereby improving the electrical isolation effect between the conductive structures <NUM> and a storage node contact structure formed later. It should be understood that, in some implementations, the inner spacer layer <NUM>' may not be provided above the sacrificial layer <NUM>". Instead, the sacrificial layer <NUM>"is directly provided in a region where the inner spacer layer <NUM>' is located. In this way, when the first etching is performed on the sacrificial layer <NUM>, the sacrificial layer to be removed is formed on two sidewalls of the first structures <NUM> through a corresponding mask, so as to simplify the step of forming the air gaps, thereby improving the manufacturing efficiency of the semiconductor device.

S400: Form an outer spacer layer on a sidewall of the sacrificial layer.

Referring to <FIG>, an outer spacer layer <NUM> with the same thickness may be deposited on the exposed surfaces of the substrate <NUM>, the sacrificial layer <NUM>" and the first structures <NUM>, respectively. The sidewall of the sacrificial layer <NUM>" is also covered by the outer spacer layer <NUM>. It should be noted that the outer spacer layer <NUM> on the top surfaces of the first structures <NUM> and on the substrate <NUM> may be removed by etching through a mask, or by etching in a subsequent process of the manufacturing method of the present disclosure. In this embodiment, the outer spacer layer is removed by etching in a subsequent process, so as to omit mask preparation and simplify the manufacturing process of the outer spacer layer on the sidewall of the sacrificial layer <NUM>".

S500: Remove part of the outer spacer layer to obtain a patterned outer spacer layer that exposes part of the sacrificial layer.

Referring to <FIG>, by etching the outer spacer layer <NUM>, an outer spacer layer <NUM>' is obtained, and a patterned outer spacer layer is formed. The patterned outer spacer layer is shown by a thick dashed box in <FIG>. Further, for example, as shown in the A-A' and B-B' cross-sectional views in <FIG>, the patterned outer spacer layer may be formed in partial regions on two sidewalls of the first structures <NUM>, and at least the outer spacer layer directly above the second structures <NUM> is removed, such that at least the sacrificial layer <NUM>" directly above the second structures <NUM> is exposed. Specifically, as shown in <FIG>, step S500 may include:.

Referring to <FIG> and <FIG>, a complete filling dielectric layer <NUM> may be deposited on the outer spacer layer <NUM> through a deposition process, such that the filling dielectric layer <NUM> fills regions between the plurality of first structures <NUM>. Then, the filling dielectric layer <NUM> above the top surface of the outer spacer layer <NUM> is removed through a polishing process to form a filling dielectric layer <NUM>', where a top surface of the filling dielectric layer <NUM>' is flush with the top surface of the outer spacer layer <NUM>. In this way, it is convenient to subsequently etch the outer spacer layer <NUM> and the filling dielectric layer <NUM>' through a mask or a mask layer.

S530: Form a mask layer and a photoresist layer on the outer spacer layer and the filling dielectric layer, expose and develop the photoresist layer to form a patterned photoresist layer extending in a second direction, and etch the mask layer based on the patterned photoresist layer to form a patterned mask layer extending in the second direction.

S540: Etch the outer spacer layer and the filling dielectric layer using the patterned mask layer as a mask, and remove part of the outer spacer layer and part of the filling dielectric layer to obtain the patterned outer spacer layer.

Referring to <FIG>, a mask layer <NUM> is provided on the outer spacer layer <NUM> and the filling dielectric layer <NUM>', and an etching window is defined by the mask layer <NUM>. The mask layer <NUM> can be a single layer or multiple layers, and different selections can be made according to process requirements. In this embodiment, there are four stacked mask layers <NUM>, specifically first, second, third and fourth mask layers sequentially stacked on the outer spacer layer <NUM> and the filling dielectric layer <NUM>'. Further, a patterned photoresist layer <NUM> extending in the second direction D2 is further formed on the fourth mask layer. The patterned photoresist layer <NUM> defines an etching window for the fourth mask layer, and then the fourth, third, second and first mask layers are etched in sequence. The etching window is moved down to the first mask layer to expose the outer spacer layer <NUM> and the filling dielectric layer <NUM>' to be etched, and then the outer spacer layer <NUM> and the filling dielectric layer <NUM>' are etched. After the etching is completed, as shown in <FIG>, at least the outer spacer layer <NUM> and the filling dielectric layer <NUM>' directly above the second structures <NUM> are removed, and an outer spacer layer <NUM>' and a filling dielectric layer <NUM>" are formed. The outer spacer layer <NUM>' has a plurality of gaps in the first direction D1. In this way, at least the sacrificial layer <NUM>" directly above the second structures <NUM> is exposed.

S600: Remove the sacrificial layer to form air gaps between the patterned outer spacer layer and the first structures.

The sacrificial layer <NUM>" includes a hydrocarbon layer or a polymer layer that can be thermally decomposed, and such a sacrificial layer <NUM>" may be selectively removed through an ashing process or application of heat. Specifically, oxygen may be introduced into the substrate <NUM>. During the ashing process, the oxygen may contact and react with the exposed sacrificial layer <NUM>", such that the sacrificial layer <NUM>" is converted into carbon dioxide gas, carbon monoxide gas and/or methane gas. These gases may be quickly exported to the outside during the reaction without being too much blocked by other structures or staying in the reaction space for a long time. After the ashing process is completed, as shown in <FIG>, the sacrificial layer <NUM>" is completely removed, and air gaps <NUM> are formed between the patterned outer spacer layer and the first structures <NUM>.

In the manufacturing method, the sacrificial layer <NUM>" is first formed on sidewalls of the first structures <NUM> on the substrate <NUM>, the outer spacer layer is formed on a sidewall of the sacrificial layer <NUM>", part of the outer spacer layer is formed to obtain a patterned outer spacer layer that exposes part of the sacrificial layer, and the sacrificial layer is removed to form air gaps between the patterned outer spacer layer and the first structures <NUM>. The present disclosure exposes part of the sacrificial layer <NUM>" such that the sacrificial layer <NUM>" directly reacts with the outside to be completely removed, thereby forming air gaps <NUM> with small widths. In this way, the present disclosure solves the problem that it is hard to remove the narrow sacrificial layer <NUM>" by using the traditional technology. Meanwhile, since there is no need to remove the sacrificial layer <NUM>" by etching, the surface uniformity around the air gap <NUM> is improved.

In an embodiment, after forming the air gaps <NUM>, the method further includes:
S600: Form a plurality of storage node contact structures between the plurality of first structures, where the storage node contact structures are in contact with the substrate; the air gaps are located between the storage node contact structures and the first structures.

Specifically, referring to <FIG>, a source region and a drain region are formed in the AR on two sidewalls of the buried word line <NUM>, thereby forming a metal-oxide-semiconductor field-effect transistor (MOSFET). Further, the drain region is electrically connected with the bit line <NUM> through the bit line plug <NUM>. A storage capacitor is formed above the source region. A bottom plate of the storage capacitor is electrically connected with the source region through the polysilicon, thereby forming a semiconductor memory, such as a dynamic random access memory (DRAM). Of course, other type of memory may also be formed. Therefore, the air gaps <NUM> are located between the storage node contact structures and the first structures <NUM>, which improves the insulation effect between the storage node contact structures and the first structures <NUM>, thereby improving the electrical performance of the semiconductor memory. Specifically, step S600 may include:.

Referring to <FIG>, a complete node spacer layer may be deposited between the filling dielectric layers <NUM>" through a deposition process. The node spacer layer is etched back to form a node spacer layer <NUM>. A top surface of the node spacer layer <NUM> is flush with the top surface of the filling dielectric layer <NUM>". It facilitates the definition of a formation region for the storage node contact structure and the isolation of adjacent storage node contact structures. Further, the node spacer layer <NUM> is formed directly above the second structures <NUM>.

S630: Remove the filling dielectric layer.

Referring to <FIG>, the filling dielectric layer <NUM>" may be removed by etching to provide a formation region for the storage node contact structure. In addition, while the filling dielectric layer <NUM>" is etched, the outer spacer layer <NUM>' on the top surfaces of the first structures <NUM> may also be etched to form an outer spacer layer <NUM>".

S640: Etch part of the substrate to form a plurality of recessed substrate contact holes between adjacent first structures.

Referring to <FIG>, part of the substrate <NUM> may be removed by etching to form a plurality of recessed substrate contact holes <NUM> between adjacent first structures <NUM>. The bottom plates of the storage capacitor above the source regions are electrically connected with the source regions in the substrate <NUM> through the substrate contact holes <NUM>. Further, the substrate contact holes <NUM> are also located between adjacent second structures <NUM>. In addition, while the substrate <NUM> is etched, the outer spacer layer <NUM>" between the filling dielectric layer <NUM>" and the substrate <NUM> may also be removed together to form an outer spacer layer <NUM>‴ on two sidewalls of the first structures <NUM>. The outer spacer layer <NUM>‴ is the above patterned outer spacer layer.

S650: Form an epitaxial layer on the substrate through an epitaxial process, where the epitaxial layer at least fills up the substrate contact holes.

S660: Etch back the epitaxial layer to form the plurality of storage node contact structures, where top surfaces of the storage node contact structures are lower than top surfaces of the first structures.

Referring to <FIG>, a complete epitaxial layer may be deposited on the substrate <NUM> through a deposition process, and the epitaxial layer at least fills the substrate contact holes <NUM>. Then, the epitaxial layer is etched back to form an epitaxial layer <NUM>, which forms the plurality of storage node contact structures together with the substrate contact holes <NUM>. Further, the top surfaces of the storage node contact structures are lower than these of the first structures <NUM>, which helps the storage node contact structures contact the bottom plates of the storage capacitor.

In an embodiment, after step S660, the method further includes:
S670: Etch the patterned outer spacer layer to turn a top surface of the patterned outer spacer layer into an inclined surface.

Referring to <FIG>, the top surface of the patterned outer spacer layer (shown in the thick dashed box) on the two sidewalls of the first structures <NUM> may be etched to form an outer spacer layer 600ʺʺ. After etching, the top surface of the patterned outer spacer layer is an inclined surface. As shown in the B-B' cross-sectional view, the top surface of the outer spacer layer 600ʺʺ on the two sidewalls of the first structures <NUM> are distributed in a splayed pattern. Meanwhile, the top surface of the node spacer layer <NUM> is etched correspondingly to form a node spacer layer <NUM>'. In this way, the upper parts of the storage node contact structures are widened, thereby increasing the contact area between the storage node contact structures and the subsequent storage capacitor, and improving the performance of the semiconductor storage device.

In one embodiment, when an inner spacer layer <NUM>' is further provided between the patterned outer spacer layer and the first structures <NUM>, the inner spacer layer <NUM>' also needs to be etched to form an inner spacer layer <NUM>". A top surface of the inner spacer layer <NUM>" is also distributed in a splayed pattern, as shown in the B-B' cross-sectional view. The top surface of the inner spacer layer <NUM>" is also an inclined surface, so as to further increase the contact area between the storage node contact structures and the subsequent storage capacitor. It is understandable that other etching methods may also be used to increase the contact area between the storage node contact structures and the subsequent storage capacitor, which is not limited herein.

The present disclosure further provides a semiconductor structure.

As shown in <FIG>, the semiconductor structure includes: a substrate <NUM>, a plurality of first structures <NUM> formed on the substrate <NUM> and extending in a first direction D1, and a patterned outer spacer layer formed in partial regions on two sidewalls of the first structures <NUM> (shown in the thick dashed box). Air gaps are formed between the patterned outer spacer layer and the first structures <NUM>. The patterned outer spacer layer includes a plurality of outer spacer blocks (not shown in the figure). The plurality of outer spacer blocks are distributed on the substrate <NUM> at intervals in the first direction.

Specifically, according to the above steps, the patterned outer spacer layer has a plurality of gaps in the first direction D1, such that the patterned outer spacer layer includes a plurality of outer spacer blocks distributed at intervals in the first direction D1.

In the semiconductor device, a patterned outer spacer layer is formed in partial regions on two sidewalls of the first structures <NUM>. Air gaps are formed between the patterned outer spacer layer and the first structures <NUM>, and the patterned outer spacer layer includes a plurality of outer spacer blocks distributed on the substrate <NUM> at intervals in the first direction D1. The semiconductor device achieves desirable surface uniformity around the air gap <NUM>, and avoids the problem of non-uniform electrical isolation due to poor etching uniformity, thereby improving the electrical isolation effect between the first structures and the adjacent storage node contact structures.

In an embodiment, referring to <FIG>, the semiconductor device further includes a plurality of storage node contact structures formed between the plurality of first structures <NUM>. The storage node contact structures are in contact with the substrate <NUM>. The air gaps <NUM> are located between the storage no de contact structures and the first structures <NUM>. Specifically, an epitaxial layer <NUM> is filled in substrate contact holes <NUM>, and a top surface of the epitaxial layer is lower than top surfaces of the first structures <NUM>, thereby forming storage node contact structures.

A source region and a drain region are formed in an AR on two sidewalls of a buried word line <NUM>, thereby forming an MOSFET. The drain region is electrically connected with a bit line <NUM> through a bit line plug <NUM>. A storage capacitor is formed above the source region. A bottom plate of the storage capacitor is electrically connected with the source region through polysilicon, thereby forming a semiconductor memory, such as a DRAM. Therefore, the air gaps <NUM> are located between the storage node contact structures and the first structures <NUM>, which improves the insulation effect between the storage node contact structures and the first structures <NUM>, thereby improving the electrical performance of the semiconductor memory.

In an embodiment, a top surface of the patterned outer spacer layer is an inclined surface. Referring to <FIG>, when the top surface of the patterned outer spacer layer is an inclined surface, an outer spacer layer 600ʺʺ is formed. Thus, the upper parts of the storage node contact structures are widened, thereby increasing the contact area between the storage node contact structures and the subsequently formed storage capacitor, and improving the performance of the semiconductor storage device.

In an embodiment, the semiconductor structure may be a DRAM. The first structures <NUM> include conductive structures <NUM> and isolation sidewalls <NUM> located on sidewalls of the conductive structures <NUM>. The air gaps <NUM> are formed between the isolation sidewalls <NUM> and the patterned outer spacer layer. Further, the conductive structures <NUM> include bit lines <NUM> extending in the first direction D1, and bit line protection structures <NUM> are formed on the bit lines <NUM>. In an embodiment, the semiconductor device further includes a plurality of second structures <NUM> formed in the substrate <NUM> and extending in a second direction D2. The second structures <NUM> include buried word lines <NUM> extending in the second direction D2 and word line protection structures <NUM> formed on the buried word lines <NUM>.

In an embodiment, an inner spacer layer <NUM>" is further provided between the patterned outer spacer layer and the first structures. The air gaps <NUM> are located between the inner spacer layer <NUM>" and the substrate <NUM>, and a bottom surface of the inner spacer layer <NUM>" is not lower than top surfaces of the conductive structures <NUM>. The inner spacer layer <NUM>" is provided above air gaps <NUM>' to well seal the air gaps <NUM>, thereby improving the electrical isolation effect between the conductive structures <NUM> and the storage node contact structures, and increasing the contact area between the storage node contact structures and the subsequently formed storage capacitor.

Claim 1:
A method for manufacturing a semiconductor device, comprising:
providing a substrate (<NUM>) (S100);
forming a plurality of first structures (<NUM>) extending in a first direction (D1) on the substrate (<NUM>) (S200), wherein each of the first structures (<NUM>) comprises a conductive structure (<NUM>) and an isolation sidewall (<NUM>) located on a sidewall of the conductive structure (<NUM>), the conductive structure (<NUM>) comprises a bit line (<NUM>) extending in the first direction (D1);
forming a sacrificial layer (<NUM>") on sidewalls of the first structures (<NUM>) (S300), wherein the sacrificial layer (<NUM>") comprises a hydrocarbon layer or a polymer layer;
forming an outer spacer layer (<NUM>) on a sidewall of the sacrificial layer (<NUM>");
removing part of the outer spacer layer (<NUM>) to obtain a patterned outer spacer layer that exposes part of the sacrificial layer (<NUM>") (S500), wherein the patterned outer spacer layer comprises a plurality of outer spacer blocks, the plurality of outer spacer blocks are distributed on the substrate (<NUM>) at intervals in the first direction (D1); and
removing the sacrificial layer (<NUM>") by an ashing process to form air gaps (<NUM>) between the patterned outer spacer layer and the first structures (<NUM>) (S600).