Patent Description:
Files are a type of data structure that are used by applications to manage user data. As such, efficient processing, storage, security, and general management of the data is important to information technology (IT) systems. Applications use and depend upon file systems, operating systems (OSs), and other such system software for file management and access related operations.

Storage devices (e.g., persistent data storage devices such as solid state drives (SSDs)) for modern IT infrastructure are increasing in popularity, as vast amounts of data are being generated by various applications, such as, for example, Internet of things (IOT), social networks, autonomous vehicles, etc. NAND flash media based SSD storage devices are also components of the IT infrastructure.

When applications require data, the desired data portions of stored files are accessed. The speed at which the desired data portions are accessed may be of particular importance so that the data may be quickly accessed, to improve the overall throughput of the performance and user experience of applications (e.g., gaming and online shopping applications).

From <CIT> it is known a data store that has a data array for storing data values and a tag array for storing tag values for tracking which data values are stored in the data array. The associativity of the data array is greater than the associativity of the tag array. Hence, fewer tag entries need to be accessed on each data access than in a conventional data store, reducing power consumption.

The present disclosure has been made to address at least the disadvantages described above and to provide at least the advantages described below.

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the same elements will be designated by the same reference numerals although they are shown in different drawings. In the following description, specific details such as detailed configurations and components are merely provided to assist with the overall understanding of the embodiments of the present disclosure. Therefore, it should be apparent to those skilled in the art that various changes and modifications of the embodiments described herein may be made without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness. The terms described below are terms defined in consideration of the functions in the present disclosure, and may be different according to users, intentions of the users, or customs. Therefore, the definitions of the terms should be determined based on the contents throughout this specification.

The present disclosure may have various modifications and various embodiments, among which embodiments are described below in detail with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but includes all modifications, equivalents, and alternatives within the scope of the present disclosure.

The terms are used to distinguish one element from another element.

The electronic device according to one embodiment may be one of various types of electronic devices utilizing storage devices. The electronic devices may include, for example, a portable communication device (e.g., a smart phone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to one embodiment of the disclosure, an electronic device is not limited to those described above.

The terms used in the present disclosure are not intended to limit the present disclosure but are intended to include various changes, equivalents, or replacements for a corresponding embodiment. With regard to the descriptions of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. A singular form of a noun corresponding to an item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, terms such as "<NUM>st," "<NUM>nd," "first," and "second" may be used to distinguish a corresponding component from another component, but are not intended to limit the components in other aspects (e.g., importance or order). It is intended that if an element (e.g., a first element) is referred to, with or without the term "operatively" or "communicatively", as "coupled with," "coupled to," "connected with," or "connected to" another element (e.g., a second element), it indicates that the element may be coupled with the other element directly (e.g., wired), wirelessly, or via a third element.

As used herein, the term "module" may include a unit implemented in hardware, software, firmware, or combination thereof, and may interchangeably be used with other terms, for example, "logic," "logic block," "part," and "circuitry. " A module may be a single integral component, or a minimum unit or part thereof, adapted to perform one or more functions. For example, according to one embodiment, a module may be implemented in a form of an application-specific integrated circuit (ASIC).

For secure data storage, user accessible data should be protected, which can require encryption and decryption. A memory storage system may allow a host device to select either an encryption or decryption key for every input/output (IO) command, referred to as key per IO (KPIO).

Self-encrypting drives (SED) may perform continuous encryption on user accessible data. This is done at interface speeds using a small number of keys generated/held in persistent media by the storage device. KPIO may utilize a large number of encryption keys to be managed and securely downloaded into a non-volatile memory subsystem. Encryption of user data may occur on a per command basis (each command may request the use a different key).

In order to efficiently store encrypted data, a hash function may be used. Hash functions take an arbitrarily long string of bytes and produce a shorter fixed size result. For example, a first key type may be input to a hash function to output a shorter fixed size result (e.g., a hash value). A hash value may be an index for a specific element stored in memory. A hash table may be used to store hash values corresponding to the first key type and value pairs in a list that is accessible through its index. The values in the hash table (paired with the hash value of the first key type) may be a second key type used for KPIO. Therefore, when the values in the hash table are the second key type used for KPIO, the values may be used to encrypt/decrypt data to perform read/write commands. Additionally, the values in the hash table (paired with the hash value of the first key type) may be include one or more data objects.

Memory storage systems often require a large number of possible keys for storage but a relatively small fraction of them may be used during memory read/write operations. Thus, memory storage may be inefficient because larger than required memory spaces may be allocated for storing the large number of keys, thereby increasing the cost and power consumption of such designs. In addition, inefficient designs may also cause slow reading and writing of data.

A method to accelerate lookup speed of a frequently used hashed key-value in a <NUM>st tier (e.g., a memory having a relatively fast access time (e.g., static read only memory (SRAM) or on-chip memory))) while complete sets of key-values are stored in a <NUM>nd tier memory (e.g., a memory having a relatively slow access time (e.g., dynamic read only memory (DRAM))) is provided. For example, at least a part of a hashed index or a source address may be used as an identification tag to locate a cache hit, and to reduce the lookup duration. This cache tag-identification operation may be performed in a smaller-n-packed <NUM>st tier memory (e.g., a faster memory). Accordingly, memory lookup speed may be improved since it may not necessarily be limited by <NUM>nd tier memory (e.g., a slower memory) throughput. <NUM>st tier memory (e.g., with relatively faster memory access times) may be referred to as "primary memory" and <NUM>nd tier memory (e.g., with relatively slower memory access times) may be referred to as "secondary memory".

<FIG> is a block diagram illustrating a key per input output (KPIO) system, according to an embodiment. Throughout <FIG>, some of the components include a number of bits (b) or bytes (B) corresponding to each component (e.g., Command (64x8 b) and/or encryption key <NUM> B). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

A KPIO system <NUM> may be a {key, value} system. The {key, value} system may store data as a collection of key-value pairs in which the key serves as a unique identifier to the value. The value may be made up of a fixed number of bits (e.g., <NUM> bits) and may represent a security key (e.g., a private key) for encrypting or decrypting data (Note, the key included in the "{key, value}" pair may be a different type of key than the security key included in the "value" field. An Advanced Encryption Standard (AES) decryption key may be stored in volatile read only memory, such as a DRAM. The value representative of the security key (e.g., the <NUM> bit security key) may be addressed by namespace identification (NSID) + key tag.

Referring to <FIG>, a host may transmit a read or write command <NUM> to a storage device (e.g., an SSD (e.g., a flash drive)). The command <NUM> may include an NSID + key tag. The NSID <NUM> may identify a memory to read to or write from. The NSID <NUM> may be made up of <NUM> or more bits. The key tag <NUM> may be a key index used to index an encrypting/decrypting key for a specific NSID. The system may be composed of more than one NSID and key tags in different NSIDs can overlap. The NSID <NUM> and the key tag <NUM> are combined to form data structure <NUM> (e.g., a key index, a non-overlapping {key, value} index, an encryption index, a decryption key index, a lookup table, or an array). The data structure <NUM> may be an AES index. The size of the data structure <NUM> may be composed of <NUM>,<NUM>,<NUM> (entries) x <NUM> bits, and may be partitioned into a predetermined number of name spaces (NSs) (e.g., <NUM> NSs of 64kb each). Each NS may include a number of valid entries which may be linearly incremented. Linearly allocation of valid entries may reduce hit rate and can create a throttle refill due to least recently used (LRU) eviction policy.

Each NS may be indexed across various portions of the entire data structure <NUM> (this may be called "sparse indexing"), thereby requiring a large number of look-ups to retrieve the information included in a single NS. In this regard, the data structure <NUM> is large. The data structure <NUM> includes about <NUM> million possible entries. However, the system may use <NUM> thousand valid entries. Thus, the total memory size may be <NUM> gigabyte (GB), and the total valid memory size may be <NUM> megabytes (MB). Since the number of valid entries is small relative to the total size of the memory, the memory is sparse. Having a pre-defined fixed/max number of valid keys (e.g., <NUM> thousand) is a characteristic of KPIO encryption that that uses a limited memory size and a maximum number of lookups in the large and sparse source address space, thereby increasing the importance of relying on an efficient throughput calculation for quickly finding and retrieving valid keys.

The data structure <NUM> may be used to retrieve a security key <NUM> (e.g., an AES encryption key or encryption key). The security key <NUM> may be <NUM> bytes (<NUM> bits). If the security key <NUM> is <NUM> bytes, then it may be large, and may need to be saved on a cache memory or an external memory to be accessed.

A security key <NUM> may be retrieved and sent to the de/encryption engine <NUM>. Decrypted data (e.g., unencrypted data) may be read <NUM> or decrypted data may be written <NUM> from the host to the SSD, and the security key <NUM> may be used by the de/encryption engine <NUM> to read encrypted data <NUM> or write encrypted data <NUM>. The encrypted data <NUM> or <NUM> may be <NUM>,<NUM> x <NUM> bits and stored in memflash. For example, the encrypted data <NUM> or <NUM> may be stored in a remote server (e.g., a cloud server).

A direct address lookup table (LUT) may be used to store key values in the key index <NUM> in a KPIO system. A direct address LUT addresses each command <NUM> to a specific address space in the key index <NUM>, however the size of the AES encryption key index <NUM> must be very large, since a fixed portion of the size of the key index <NUM> can include valid entries.

Using a content addressable memory (CAM) lookup may be a solution for efficiently obtaining or retrieving key values in a KPIO system. Advantageously, CAM lookup reduces memory storage size of the key index <NUM> and achieves a fast throughput. Unfortunately, CAM uses a large number of logic gates to enter or retrieve key values, which is expensive. For example, for <NUM> thousand valid entries, <NUM> thousand x <NUM> bit comparators may be needed to perform logic functions to redirect a source index to a valid key address space in the key index <NUM>.

Additionally, hash addressing is used to hash the source index command to a finite size to identify a key storage address of a hash key index (e.g., reducing the index command from <NUM> to <NUM> bits). Hash addressing advantageously reduces the memory size of a memory by using a hash key index, since hashed indexes can be stored compactly with a reduced length. Unfortunately, since multiple source keys (e.g., keys from one or more sources to be input into the hash function) may be linked to a single hash index, retrieval of a valid value from the same hash index-may require a conflict resolution operation which may slow throughput.

The hash conflict resolution operation may involve performing a compare operation when using hash indexes to identify storage indexes in a primary memory. If the compare operation matches a hashed index corresponding to a storage address in the primary memory with a source index (e.g., an NSID + key tag), then a linked list may be used to designate a secondary memory address space to associate the hashed index corresponding to the storage address in the primary memory with the source index. In this manner, multiple entries can be associated with the same hashed index using the linked list. Accordingly, the size of the primary memory may be reduced to a small size, since valid entries may be included. However, when a conflict occurs and a linked list is designated, the memory that is allocated to an entry must be expanded. In addition, due to the compare operation, a conflict may occur and accessing the memory may require multiple operations to obtain data from linked lists.

A peripheral component interconnect express (PCIe) link may be used to access memory. The PCIe4x4 standard may use <NUM> million (M) input/output operations per second (IOPS) or <NUM> nanoseconds (ns) for one lookup (e.g., read or write). The PCIe4x6 standard may use <NUM> IOPS or <NUM> ns for one lookup. DRAM access may be about <NUM>-70ns. Thus, using the PCIe4x6 standard, only <NUM>-<NUM> conflict comparisons and/or lookups can be performed per command, which presents a significant bottleneck in lookup speed.

The present application proposes solutions that can efficiently lookup a memory entry (e.g., an encryption key) using <NUM>st tier: cache RAM (e.g., a cache storage), thereby reducing the likelihood needing to access a <NUM>nd tier: external RAM (e.g., a DRAM), which may be slow to access. Thus, the present application proposes reducing the overall throughput time for obtaining a memory entry and minimizes the number of lookup iterations, thereby improving lookup speeds for systems that rely on PCIe IOPS standards.

Moreover, the present application proposes using multiple types of cache comparisons to identify a cache conflict (e.g., a mismatch). A first type of cache conflict may be referred to as a traditional cache conflict resolution. A second type of cache conflict may referred to as a hash cache conflict resolution. Throughout the disclosure, comparisons are made to identify whether a conflict exists. Each comparison may be, for example, a traditional cache conflict resolution or a hash cache conflict resolution. Other types of comparisons, such as multi-way cache comparisons, may be used too.

A traditional cache comparison (traditional cache conflict resolution) may be between two values: <NUM>. The Tag_Address access/index Tag Memory Content (e.g., <NUM> bits); and <NUM>. A portion of the source address (e.g., <NUM> bits = <NUM> bits -<NUM> bits). This type of comparison may be exemplified by step <NUM> of <FIG>, discussed below.

A hash cache comparison (hash cache conflict resolution) may be between two values: <NUM>. The Tag_Address access/index Tag Memory Content (e.g., <NUM> bits) and <NUM>. The full source address (e.g., <NUM> bits). This type of comparison may be exemplified by <NUM> of <FIG>, discussed below.

For convenience of description, the term "tag memory content" is used in this disclosure. This term refers to a memory content stored in tag memory (e.g., <NUM>st tier tag RAM). Depending on which of the abovementioned comparisons are used, tag memory content may refer to a different number of bits (e.g., <NUM> bits in the case of traditional cache conflict resolution, <NUM> bits in the case of hash cache conflict resolution, etc.), which may be compared with a part, or all, of the source address.

<FIG> is a block diagram illustrating hash conflict resolution, according to an embodiment. Throughout <FIG>, some of the components include a number of bits or bytes corresponding to each component (e.g., NSID [<NUM>]). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

Hash conflict resolution using a linked list may merge separate chaining linked lists with a hash table to save memory space for unused slots in a primary memory. Hash conflict resolution may be applied to a KPIO system, such that a source index (an NSID and key tag) is hashed and used to identify a storage address corresponding to an encryption or decryption key stored in DRAM.

The operations described in <FIG> may be performed by a controller stored in memory, a processor, or computer-implemented instructions.

Referring to <FIG>, a source index comprising an NSID and key tag may be hashed from <NUM> to <NUM> bits to generate a hashed index. The hashed index represents a storage address of the primary memory (e.g., a hash table). At step <NUM>, a tag portion (e.g., <NUM> bits) is compared (e.g., by a controller) to the NSID (e.g., <NUM> bits) and key tag (e.g., <NUM> bits) representing the storage address of the primary memory. The tag portion may represent a local address of the primary memory entry and is compared with the source index comprising the NSID and key tag. As shown in <FIG>, the <NUM> bit tag stored in memory storage is compared with the source index (e.g., NSID (<NUM> bits) and key tag (<NUM> bits)) at step <NUM> that a conflict exists (a mismatch), and conflict resolution logic may be performed at step <NUM>. For example, a first pointer may be assigned to link access <NUM> to another storage address in the primary memory, access <NUM>. In addition, a second pointer may be assigned to link access <NUM> to another storage address in the primary memory, access <NUM>. An entry included in the primary memory may be accessed using a cache index.

Access <NUM>, access <NUM>, and access <NUM> denote access attempts to an entry of the primary memory. Each access attempt may initiate the following sequence:.

where "i" denotes an entry of the primary memory.

<FIG> is a block diagram illustrating a partial source index as a tag index, according to an embodiment. Throughout <FIG>, some of the components include a number of bits or bytes corresponding to each component (e.g., NSID [<NUM>]). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

Referring to <FIG>, a <NUM> bit source index <NUM> is provided. The <NUM> lower bits (e.g., least significant bits (LSBs)) of the source index <NUM> are used as a tag address <NUM>. Here, the tag address is <NUM> bits because the tag RAM (cache storage) includes <NUM> entries, and log2(<NUM>)=<NUM>. The remaining <NUM> bits of the source index <NUM> are stored in the <NUM>st tier: tag RAM (cache storage) so that the total memory size is <NUM> x <NUM> bits. Once the <NUM> bits are indexed, the value may be output from the tag RAM as tag_content (the term "tag_content" may be used interchangeably with the term "tag memory content") and compared with the corresponding bits of NSID[<NUM>] keytag[<NUM>] from the source index in step <NUM> to determine whether there is a conflict. If there is no conflict (cache hit or match), then a corresponding cache <NUM> entry may be output from cache storage. In this manner, the cache storage is used to improve the hit rate for outputting a storage entry, for example, systems in which valid entries are linearly allocated (e.g., KPIO systems).

If there is a conflict in step <NUM>, then a valid entry is not output via <NUM>st tier cache RAM. In this case, <NUM>nd tier external RAM is accessed to identify a valid entry by hashing the source index <NUM> to <NUM> bits and providing it as a hash index <NUM>. The hash index <NUM> may be <NUM> bits and represent a storage address of the <NUM>nd tier: external RAM. At step <NUM>, a tag portion of access <NUM> is compared (e.g., by a controller) to the hashed index of the NSID and key tag representing the storage address of the memory. The tag portion of access <NUM> may represent a local address of the access <NUM> in a memory entry and is compared with the source index comprising the NSID and key tag. If there's a match, then a corresponding entry may be output from the <NUM>nd tier: external RAM at step <NUM>. If there's a conflict (miss match) in step <NUM>, the next pointer may be assigned to link access <NUM> with access <NUM> in the storage device in step <NUM>.

In step <NUM>, a tag portion of access <NUM> is compared (e.g., by the controller) to the hashed index of the NSID and key tag representing the storage address of the memory. If no conflict is identified in step <NUM> (match), then the entry may be output from the <NUM>nd tier: external RAM and provided as output at step <NUM>.

The time it takes to output an entry via cache memory (at step <NUM>) versus DRAM (at step <NUM>) is notably different. As discussed below, cache memory may be accessed and an entry output much faster than using DRAM to perform the same. Thus, using cache memory to output an entry is preferable because it has much less latency.

A characteristic of KPIO may be that a KPIO key in each NS may be linearly incremented upon allocation. For example, if a lower address of each NS is used as an index, then each NS may point to a first index (e.g., index <NUM>), and a <NUM>st tier: tag RAM, as provided in <FIG>, may only store one NS entry (e.g., <NUM> NS entry of the <NUM> NS entries).

<FIG> is a block diagram illustrating a multi-way tag address index, according to an embodiment. Throughout <FIG>, some of the components include a number of bits or bytes corresponding to each component (e.g., NSID [<NUM>]). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

<FIG> includes a number of components that are similar to <FIG>. Therefore, for convenience of description, similar descriptions of components may be omitted from the description of <FIG>.

Referring to <FIG>, the <NUM>st tier: tag RAM is provided as a multi-way tag address. As shown in <FIG>, the <NUM>st tier: tag RAM is duplicated into two tag addresses (Tag0 and Tag1). Accordingly, a first entry <NUM> and a second entry <NUM> may be cached in the LSB to one tag address, thereby increasing the hit rate (since, for example, <NUM> NS entries may be used to provide a match for two entries instead of one). Further, the <NUM>st tier: tag RAM may also be divided into partitions other than two. For example, the <NUM>st tier: tag RAM may be allocated as having four entries cached to the LSB, thereby increasing the hit rate even further (since, for example, <NUM> NS entries may be used to provide a match for four entries instead of two).

At steps <NUM>-<NUM>, a multi-way cache memory comparison is performed. At step <NUM>, a comparison between tag content (e.g., tag_content_1[<NUM>]) and a portion of the source index (e.g., NSID[<NUM>] KeyTag[<NUM>]) is performed. At step <NUM>, a comparison between tag content (e.g., tag_content_2[<NUM>]) and a portion of the source index (e.g., NSID[<NUM>] KeyTag[<NUM>] is performed. A multi-way cache memory comparison is notably different than a traditional cache comparison and a hash cache comparison, as described above, because as shown in steps <NUM>-<NUM>, a <NUM>-way traditional cache comparison is a comparison between two values: <NUM>. Two entries (<NUM> and <NUM>) of the Tag_Address access/index Tag Memory Contents (<NUM> bits) and <NUM>. A portion of the Source Address (<NUM> bits = <NUM> bits - <NUM> bits). Also, the tag address may be <NUM> bits since <NUM> LSBs of source index - <NUM> bit to distinguish among duplicated tag addresses Tag0 and Tag1.

Additionally, other multi-way cache memory comparisons are possible. For example, a <NUM>-way traditional cache compares between two values: <NUM>. Four entries of the Tag_Address access/index Tag Memory Contents (<NUM> bits) and <NUM>. A portion of the Source Address (<NUM> bits = <NUM> bits - <NUM> bits). Also, the tag address may be <NUM> bits since <NUM> LSBs of source index - <NUM> bits to distinguish among <NUM> duplicated tag addresses.

Additionally, a configurable x-way traditional cache memory comparison is possible. For example, an x-way traditional cache compares between two values: <NUM>. X entries of the Tag_Address access/index Tag Memory Contents (<NUM>+Log2(X) bits) and <NUM>. A portion of the Source Address (<NUM> bits -Tag_Address width (e.g., the Tag_Address width may be a function of the number of duplicated tag addresses)). Also, the tag address may be equal to <NUM> - log2(x).

<FIG> is a block diagram illustrating a source index configurable to be mapped to a tag address, according to an embodiment. Throughout <FIG>, some of the components include a number of bits or bytes corresponding to each component (e.g., NSID [<NUM>]). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

Referring to <FIG>, the <NUM>st tier: tag RAM is provided as a configurable source index mapped to a tag address. Instead of using an LSB to identify a tag address, a part of the NSID[<NUM>] of the source index (denoted as "NSID[Y]") and a part of the keytag[<NUM>] of the source index (denoted as "KeyTag[X]") may be used to identify a tag address of the cache index. Accordingly, a part of the NSID bit can be a part of the tag address, which may reduce the likelihood of their being a conflict since the tag address is reconfigurable. For example, <NUM> LSBs of the NSID and <NUM> LSBs of the keytag may be used to identify the tag entry, and the remaining <NUM> bits may represent the tag content. Thus, at step <NUM> a configurable x-way traditional cache memory comparison may be performed.

The configurable source index may allow the multiple namespaces having valid entries to be identified using the cache index. Each valid entry may be incrementally identified for each namespace, starting from zero.

According to an embodiment, a hashed source address may be used as a cache tag address. Using the hashed source address as the tag address may improve the hit rate (e.g., a lower possibility of a conflict) for the linear increment source address problem. For example, a valid address may be spread evenly across the cache address space and lower a possibility of a conflict to less than <NUM>%. In addition, an LSB of the hashed source address (hash index) may be used as the tag address (a cache tag address).

<FIG> is a block diagram illustrating using a hashed index as a tag address, according to an embodiment. Throughout <FIG>, some of the components include a number of bits or bytes corresponding to each component (e.g., NSID [<NUM>]). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

Referring to <FIG>, a source index is hashed from, for example, <NUM> bits to <NUM> bits at step <NUM>. At step <NUM>, an entry corresponding to the tag address of the <NUM>st tier: tag RAM is set to be equal to a predetermined number of bits (e.g., <NUM> bits) of the hashed source index. At step <NUM>, the tag memory content (<NUM> bits) is compared to the source index (<NUM> bits to determine whether a valid entry is stored in cache.

Hashing the source index may include the added benefit of a valid entry corresponding to the hashed index[<NUM>] as not being linear (e.g., a hashed valid entry is more likely to be spread across <NUM>st tier: tag RAM in a randomized manner), thereby resolving the linear-increment allocation problem of KPIO, discussed above, since entries included in a name space will not be incremented linearly. In other words, the source index may have its entropy crowded to the LSBs. After hashing, however, the hashed source index's entropy may be spread equally across each of the hashed bits. In addition, hashing advantageously reduces the total number of bits (e.g., from <NUM> bits to <NUM> bits), thereby minimizing the size of a valid NS entry.

Although hashing the source index resolves the linear increment problem and also reduces the total number of bits to minimize the size of a valid NS entry, a tradeoff may be that the values comprising the hash index may not necessarily be unique, thus the possibility of a hash conflict may still exist.

According to an embodiment, a solution to avoiding a hash conflict may be to use the whole tag address to designate the most significant bit (MSB) to perform cache identification to determine whether a conflict exists.

<FIG> is a block diagram illustrating a multi-way hashed index as a tag address, according to an embodiment. Throughout <FIG>, some of the components include a number of bits or bytes corresponding to each component (e.g., NSID [<NUM>]). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

Referring to <FIG>, because the source index <NUM> is hashed from <NUM> bits to <NUM> bits, and associated with a tag address at <NUM>, then the possibility of a hash conflict using the hash address increases, thereby reducing the hit rate (less likely to be a match). Accordingly, a solution similar to that described with respect to <FIG> may be employed by comparing the source index with tag memory content (e.g., Tag <NUM>), which is then compared with tag memory content (e.g., Tag <NUM>) to determine wither the cache storage includes a valid entry.

<FIG> is a block diagram illustrating a double hash as a cache index, according to an embodiment. Throughout <FIG>, some of the components include a number of bits or bytes corresponding to each component (e.g., NSID [<NUM>]). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

Referring to <FIG>, performing a double hash function may reduce the likelihood of there being a tag conflict in cache, and improve the hit rate (least likely to result in a miss match). At step <NUM>, the source index is hashed from <NUM> bits to <NUM> bits using a first hash function. If the <NUM> bit first hash entry conflicts with the entry in the tag index, then the source index may be hashed from <NUM> to <NUM> bits using a second hash function to identify a second entry location in the tag index. If the <NUM> bit second hash entry conflicts with the second entry location of the tag index, the source index may be hashed from <NUM> to <NUM> bits using a third hash function to identify a third entry location in the tag index. Therefore, so long as the <NUM>st tier: tag RAM is not fully occupied, the cache is nearly guaranteed to have a location to store the entry. Additionally, tag memory content <NUM>, tag memory content <NUM>, and tag memory content <NUM> are compared to the source index to determine whether the cache memory includes the valid entry.

In addition, the <NUM>nd tier: external RAM may use a hashing function when outputting an entry. In this case, since the hashing function is being used by the <NUM>nd tier: external RAM, it may be reused as the first, second and third hash functions for hashing the source index from <NUM> to <NUM> bits.

In addition, the hashing function is not limited to hashing to or from <NUM> to <NUM> bits, and it may hash to a predetermined number of bits greater or lower than <NUM> when performing hashing.

<FIG> illustrates a table comparing the benefits of the embodiments provided by <FIG>, according to an embodiment.

<FIG> includes a number of values and percentages that are provided by way of example in order to show the relative effects of the embodiments provided by <FIG>. The values and percentages shown in <FIG> are not limited to those which are displayed, and various other values and percentages may be employed.

The process of accessing a memory address may be called performing a "hop" or "jump". Each time a compare function is used, a hop or jump is performed. <FIG> compares an average total amount of time (Max <NUM> ns) for performing <NUM> hops for each of the embodiments provided by <FIG>. The average total amount of time is a function of the cache hit rate, hash conflict, and time it takes to access <NUM>st and <NUM>nd tier memories. Since <NUM>st tier memory may be provided as SRAM, the time it takes to access SRAM may be 5ns. Since <NUM>nd tier memory is provided as DRAM, the time it takes to access DRAM may be 70ns.

<FIG> illustrates a table comparing the sizes of the memories provided by <FIG>, according to an embodiment.

<FIG> includes a number of values pertaining to the sizes of the memories provided by the embodiments provided by <FIG>. The values shown in <FIG> are not limited to those which are displayed, and various other values and percentages may be employed.

<FIG> is a block diagram illustrating a redirection table to access a cache entry, according to an embodiment. Throughout <FIG>, some of the components include a number of bits or bytes corresponding to each component (e.g., NSID [<NUM>]). The number of bits or bytes corresponding to each component is exemplary and is provided to aid in the understanding of the drawings. In particular, the size of each of the components may be used for illustrative purposes to help understand the physical relationships among components. The actual number of bits, bytes, or entries for each component may vary, depending on the needs of the system.

Referring to <FIG>, the hash table is composed of a 65536x4 bit hashed index redirection table (hash redirect table), which significantly reduces the size of the memory because the likelihood of a conflict is reduced by a factor of <NUM> by using the hashed index redirection table in combination with the cache storage in a primary memory. In this case, the primary memory may be composed of static read only memory (SRAM), and may be located on an IC (e.g., an ASIC) having read/write speeds that are faster than accessing a DRAM. The DRAM may be located off of the integrated circuit (IC) chip and may be large relative to the size of the SRAM. Thus, the hash redirect table may be referred to as an "on chip" hash redirect table that may quickly be accessed to obtain a redirect address.

The hash redirect table is a redirection index that redirects to an address of a cache storage. The hash redirect table is configured so that an entry of the hash redirect table points to a corresponding first entry in the cache storage. The input to the hash redirect table may be <NUM> bits, and the output may be <NUM> or more bits.

When the hash redirection table is used, the controller (e.g., the processor) may identify a redirection index using a hashed source index to point to the first entry of a corresponding entry in the storage memory (e.g., using a head of line (HOL) pointer). The redirection index may be used to identify a storage entry in the secondary memory without first accessing cache memory and, if the cache entry is a miss, then identifying the storage entry in the secondary memory. Thus, the redirection index speeds up the process of identifying the storage entry when it is stored in the secondary memory (e.g., when it is not stored in cache storage).

As shown in <FIG>, after the source index is hashed from <NUM> bits to <NUM> bits, plus <NUM> bits for the hash redirect table, the <NUM> bits may be used to determine whether there is a cache hit or a cache miss. If there is a cache hit, then the hash redirect table may point to the cache storage device in primary memory to access an entry. However, if there is a cache miss, then the hash redirect table may point to secondary memory to lookup an entry. As discussed above, accessing (performing a lookup in) the secondary memory requires substantially more time than accessing the primary memory. Thus, the hash redirect table improves the lookup time because it reduces the likelihood that the secondary memory will need to be accessed by reducing the likelihood of a conflict.

As described above, the present application improves throughput in memory systems by providing a number of configurations that reduce the need to access slow off-chip memory for hash based KPIO systems, thereby improving throughput and latency, and reducing power consumption that would be necessary to operate a secondary memory (DRAM).

<FIG> is a flowchart illustrating accessing a stored memory, according to an embodiment.

The steps described in <FIG> may be performed by a controller stored in memory, a processor, or computer-implemented instructions.

Referring to <FIG>, at step <NUM> tag address of a tag memory is identified based, at least partially, on a source index including an NSID and a keytag.

In step <NUM>, a cache storage address corresponding to the tag address is accessed. The cache storage address may be included in a primary memory. The primary memory may be SRAM.

In step <NUM>, tag memory content is compared with at least part of the source index to identify whether a conflict exists. The tag memory content may be the same number of bits as the at least part of the source index.

In step <NUM>, information from the cache storage address is obtained in response to identifying whether a conflict does exist in step <NUM>. The obtained information may be an encryption or a decryption key (e.g., an entry) of a predetermined size (e.g., <NUM> bits).

If a conflict does not exist, then an entry may be obtained directly from the cache storage device. Otherwise, if a conflict does exist then a secondary memory (e.g., <NUM>nd tier: external ram or DRAM) may need to be accessed to obtain the appropriate entry for output.

If a conflict does exist, then a number of different options may ensue (e.g., folded linked list, secondary memory linked list, reroute table with a linked list, MFU with a linked list, sequential double hash conflict resolution, concurrent double hash conflict resolution, HOL reroute table with double hash conflict resolution, etc.).

<FIG> is a memory system illustrating structural components for performing embodiments described in the present application, according to an embodiment.

The operations described in <FIG> may be performed by a controller stored in memory, a processor, or computer-implemented instructions. For instance, instructions performed by the controller may be implemented using as an FPGA, an ASIC, a general purpose computer, or by a remote processing system (e.g., a cloud computing system).

Referring to <FIG>, a memory system <NUM> capable of performing the embodiments described in the present application is shown. The memory system <NUM> includes a host <NUM>, an IC <NUM> (e.g., a memory buffer chip) and DRAM (e.g., a nonvolatile memory) <NUM>. Although DRAM is shown separate from the IC <NUM>, the DRAM may be included on the IC <NUM>.

The IC <NUM> includes a host interface <NUM>, SRAM (e.g., a volatile memory) <NUM>, storage media (e.g., flash memory) <NUM> and a controller <NUM>. The host interface <NUM> may communicate information from the host <NUM> to the IC <NUM> or from the IC <NUM> to the host <NUM>. The SRAM <NUM> may be relatively small in size compared to the DRAM <NUM>. However, the SRAM <NUM> may have faster read/write speeds than the DRAM <NUM>. In addition, the storage media <NUM> may store data to be transmitted to or from the host <NUM> and/or the DRAM <NUM>.

The embodiments described in the present application provide particular configurations to improve accessing stored information and, in particular, accessing stored information for KPIO systems. The storage system illustrated in <FIG> provides a structure for realizing the embodiments of the present application. It is noted, however, that the embodiments of the present application should not be limited to the structure of <FIG>, as one of ordinary skill in the art would recognize that other memory storage systems may be applied to implement the embodiments of the present application.

<FIG> illustrates an electronic device in a network environment, according to an embodiment.

Referring to <FIG>, the electronic device <NUM>, e.g., a mobile terminal including GPS functionality, in the network environment <NUM> may communicate with an electronic device <NUM> via a first network <NUM> (e.g., a short-range wireless communication network), or an electronic device <NUM> or a server <NUM> via a second network <NUM> (e.g., a long-range wireless communication network). The electronic device <NUM> may communicate with the electronic device <NUM> via the server <NUM>. The electronic device <NUM> may include a processor <NUM>, a memory <NUM>, an input device <NUM>, a sound output device <NUM>, a display device <NUM>, an audio module <NUM>, a sensor module <NUM>, an interface <NUM>, a haptic module <NUM>, a camera module <NUM>, a power management module <NUM>, a battery <NUM>, a communication module <NUM>, a subscriber identification module (SIM) <NUM>, or an antenna module <NUM> including a GNSS antenna. In one embodiment, at least one (e.g., the display device <NUM> or the camera module <NUM>) of the components may be omitted from the electronic device <NUM>, or one or more other components may be added to the electronic device <NUM>. In one embodiment, some of the components may be implemented as a single IC. For example, the sensor module <NUM> (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device <NUM> (e.g., a display).

The processor <NUM> may execute, for example, software (e.g., a program <NUM>) to control at least one other component (e.g., a hardware or a software component) of the electronic device <NUM> coupled with the processor <NUM>, and may perform various data processing or computations. As at least part of the data processing or computations, the processor <NUM> may load a command or data received from another component (e.g., the sensor module <NUM> or the communication module <NUM>) in volatile memory <NUM>, process the command or the data stored in the volatile memory <NUM>, and store resulting data in non-volatile memory <NUM>. The processor <NUM> may include a main processor <NUM> (e.g., a central processing unit (CPU) or an application processor, and an auxiliary processor <NUM> (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operable independently from, or in conjunction with, the main processor <NUM>. Additionally or alternatively, the auxiliary processor <NUM> may be adapted to consume less power than the main processor <NUM>, or execute a particular function. The auxiliary processor <NUM> may be implemented as being separate from, or a part of, the main processor <NUM>.

The auxiliary processor <NUM> may control at least some of the functions or states related to at least one component (e.g., the display device <NUM>, the sensor module <NUM>, or the communication module <NUM>) among the components of the electronic device <NUM>, instead of the main processor <NUM> while the main processor <NUM> is in an inactive (e.g., sleep) state, or together with the main processor <NUM> while the main processor <NUM> is in an active state (e.g., executing an application). According to one embodiment, the auxiliary processor <NUM> (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module <NUM> or the communication module <NUM>) functionally related to the auxiliary processor <NUM>.

The communication module <NUM> may include one or more communication processors that are operable independently from the processor <NUM> (e.g., the application processor) and supports a direct (e.g., wired) communication or a wireless communication. According to one embodiment, the communication module <NUM> may include a wireless communication module <NUM> (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module <NUM> (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules may communicate with the external electronic device via the first network <NUM> (e.g., a short-range communication network, such as Bluetooth™, wireless-fidelity (Wi-Fi) direct, or a standard of the Infrared Data Association (IrDA)) or the second network <NUM> (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., LAN or wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single IC), or may be implemented as multiple components (e.g., multiple ICs) that are separate from each other.

According to one embodiment, commands or data may be transmitted or received between the electronic device <NUM> and the external electronic device <NUM> via the server <NUM> coupled with the second network <NUM>.

Claim 1:
A method for operating a memory device (<NUM>) in a Key Per Input Output, KPIO, system, the method comprising:
identifying (<NUM>) a tag address (<NUM>) of a tag memory based, at least partially, on a source index (<NUM>, <NUM>), wherein the source index (<NUM>, <NUM>) is a combination of a namespace identification, NSID, (<NUM>) and a key tag (<NUM>);
accessing (<NUM>) a cache storage address corresponding to the tag address (<NUM>);
comparing (<NUM>) tag memory content and at least part of the source index (<NUM>, <NUM>) to identify whether a match exists or whether a conflict exists; and
in response to identifying whether the match exists or whether the conflict exists, obtaining (<NUM>) information from the cache storage address,
the method further comprising:
hashing the source index (<NUM>, <NUM>) to obtain a hashed index using a hash function,
wherein the tag address (<NUM>) of the tag memory is determined based on the hashed index.