Patent Description:
Contemporary high-performance computer systems are typically implemented as multi-node, symmetric multiprocessing ('SMP') computers with many compute nodes. SMP is a multi-processor computer hardware architecture where two or more, typically many more, identical processors are connected to a single shared main memory and controlled by a single operating system. Most multiprocessor systems today use an SMP architecture. In the case of multi-core processors, the SMP architecture applies to the cores, treating them as separate processors. Processors may be interconnected using buses, crossbar switches, mesh networks, and the like. Each compute node typically includes a number of processors, each of which may have at least some local memory, at least some of which is accelerated with cache memory. The cache memory can be local to each processor, local to a compute node shared across more than one processor, or shared across nodes.

<CIT> describes victim cache lateral castout targeting. In particular, this document describes a data processing system including a plurality of processing units coupled by an interconnect fabric. In response to a data request, a victim cache line is selected for castout from a first lower level cache of a first processing unit, and a target lower level cache of one of the plurality of processing units is selected based upon architectural proximity of the target lower level cache to a home system memory to which the address of the victim cache line is assigned. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

Aspects of the present invention are set out in the independent claims.

The diagrams depicted herein are illustrative. There can be many variations to the diagrams or the operations described therein without departing from the scope of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term "coupled" and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.

One or more embodiments of the present invention provide systems and methods for reducing memory accesses in an SMP environment. Traditionally, reductions in memory accesses are addressed utilizing large caches backing up smaller caches in an N-level vertical cache hierarchy. This includes drawbacks because at a particular cache level, not all the caches are utilized at the same rate. Because not all the caches are being utilized at the same rate, this opens up an opportunity to make use of any under-utilized cache space.

In one or more embodiments of the invention, in an SMP environment, aspects include defining lateral caches that can be used for persisting the cache evictions from a peer lateral cache. These peer lateral caches are divided into clusters of caches with each cluster signifying a scope of persistence. A cache line that is evicted is allowed to persist, first, within a cluster of peer caches at the next scope of persistence. Then, as the cache line continues to be evicted from a cluster, other clusters can be utilized for storage of the cache line until the evicted cache line reaches a last cluster and can be evicted to main memory. Lateral persistence tag bits are utilized for tracking the scope of cache persistence for each cache line. In the event of a cache fetch miss, when a cache line is installed for the first time in system caches, the lateral persistence directory tag is set to <NUM>. As the cache line is installed in lateral caches within a cluster or in other clusters of caches, the directory tag is incremented and set to that corresponding scope of persistence where the target cache belongs to. A replacement algorithm/policy is implemented to determine at what level scope the cache line is to be evicted. A target cache is identifying within the scope level and an adaptive LRU (least recently used) replacement policy then determines where to install the cache line in the target cache's congruence class.

<FIG> depicts a distributed symmetric multiprocessing (SMP) system <NUM> (hereafter "system <NUM>") in accordance with one or more embodiments. System <NUM> can include <NUM> processing units or "drawers. " Each drawer <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> includes eight (<NUM>) microprocessor (CP) chips (<NUM>-<NUM> - <NUM>-<NUM>). Each CP chip can include eight (<NUM>) cores <NUM>-<NUM> - <NUM>-<NUM>. Each core in the CP chip includes a private L1 cache <NUM>-<NUM> - <NUM>-<NUM> (including both instruction cache and data cache). These private L1 caches are backed by semi-private L2 caches <NUM>-<NUM> - <NUM>-<NUM>. In one or more embodiments of the invention, the semi-private L2 caches <NUM> can interact to provide an on-chip virtual L3 cache. Each processor drawer <NUM> contains up to <NUM> CP chips <NUM> with a fully connected topology providing a virtual L4 cache. The virtual L3 and virtual L4 caches can be implemented through a set of chip caching technologies that cluster the independent physical L2 caches <NUM> within a chip <NUM> and within a drawer <NUM> to act as a unified shared victim cache.

In one or more embodiments of the invention, the virtual L3/L4 caches are implemented by defining groups/clusters of L2 caches within a CP chip, group of CP chips, and/or drawers for evicting cache lines from peer caches. That is to say, a cache line is evicted from a first L2 to a peer L2 within the defined groups/clusters of L2 caches according to a defined replacement policy described herein.

In one or more embodiments of the invention, peer L2 caches (sometimes referred to as "lateral caches") can be divided into clusters of caches <NUM> called primary, secondary, and tertiary, which can be extended into an infinite number of unique scopes. When a cache line is evicted from an L2 cache, this evicted cache line is allowed to persist within the cluster of caches <NUM> passing from one cluster after the other until it reaches a last cluster of caches. In one or more embodiments, lateral persistence (LP) tag bits can be utilized for identifying the scope of the persistence. That is to say, the tag bit can signify what is the current scope of persistence and how many scopes can the cache line hop before it is evicted to memory or re-referenced by a processor cache. In the event of a fetch miss when a cache line is installed for the first time into a system cache, the LP tag bit can be set to <NUM>. And when the same cache line is evicted from the cache, the cache line is persisted in any of the other caches in the next scope of persistence (e.g., primary, secondary, or tertiary) within the lateral persistence tag bits being set to the respective scope of persistence.

In one or more embodiments of the invention, each drawer <NUM> includes one or more cache clusters <NUM> that are utilized for persisting cache lines when evicted from a cache within the cluster <NUM>. The illustrative example shows one configuration of the cache clusters <NUM>; however, in one or more embodiments, the clusters <NUM> can include any number of L2 caches in any type of configuration including across drawer L2 caches in a group/cluster. In one or more embodiments of the invention, wherein the data in the cache is arranged into congruence classes that contain a plurality of cache lines, and said congruence class contains a chronology vector used to determine which entry to evict, cache evictions occur using an adaptive LRU replacement policy. In the absence of an empty compartment for install on a local processor fetch miss, the replacement policy looks to evict a cache line from that L2 cache associated with the processor that is least recently used based on the chronology vector. A target L2 cache can be identified by examining the utilization of the target L2 cache with respect to the processing cores using the target L2 cache and any other metrics for the target L2 cache. The target L2 cache can be selected from among the L2 caches within the cluster <NUM> by having the lowest utilization of any L2 cache within the cluster of caches <NUM>. The utilization of the cache can be based on a number of factors including, but not limited, total cache accesses within a pre-defined time period, frequency of cache eviction and/or writes, time periods between cache accesses, evictions, and/or writes, the number of lateral persistent cache lines installed within the cache, invalidations from local/remote cores, and the like (these factors may be referred to as a saturation metric). The method to pick the lowest utilized cache can be implemented as the least within the group of counters tracking the activity per cache or it can be implemented as an LRU policy to determine the last used cache within a time window In one or more embodiments of the invention, when a cache line is first evicted to a lateral cache within a cluster of caches, the LP bit can be set to <NUM> which indicates that the cache line has been evicted from the first cache to the target cache in the cluster of caches that correspond to primary/first scope of persistence. When the same cache line is evicted from the target cache to a new target cache in the next scope of persistence (i.e., secondary castout (SCO)), the LP bit will be set to <NUM> and so on. When the same cache line is evicted from a target cache, the replacement policy can look to other clusters of caches to write the cache line using the same cache utilization determination within the new cluster of caches. The new cluster of caches can be within the same drawer <NUM>-<NUM> or in other drawers <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM> depending on the way the caches are virtually identified/defined as clusters/scopes. In one or more embodiments of the invention, if the cache line is fetched by a processing core <NUM>, the cache line is written to the fetching core's L2 cache and the LP bit can be reset to <NUM>. In one or more embodiments of the invention, the lateral persistence and replacement policy can be implemented using the cache controller <NUM> to manage cache evictions amongst the clusters of caches <NUM> and evictions to main memory <NUM>. The cache controller <NUM> can be local within a drawer <NUM> or may be a distributed element within an instance per cluster of caches.

In one or more embodiments of the invention, the replacement policy can be preferential for lateral caches <NUM> on a CP chip <NUM>. A CP chip <NUM> can have more than one defined cluster of caches <NUM> as there are eight on the CP chip. The replacement policy can first look to evict cache lines to L2 caches <NUM> local to a CP chip <NUM> prior to searching for other L2 caches that may be on other CP chips <NUM>. For example, consider three cache clusters <NUM> where a first cache cluster/primary scope and a second cache cluster/secondary scope exists on a first CP chip and a third cache cluster/tertiary scope is on a second CP chip. The replacement policy can look at utilization rates for the L2 caches within the first cache cluster which includes the cache that is evicting the cache line. This can be defined as the first scope of persistence. The first scope of persistence looks within the first cache cluster where the evicting cache exists. A second scope of persistence can be defined as any other group (e.g., the second cache cluster) that is on the CP chip where the evicting cache does not reside, but may not include the entire system. The third scope of persistence can look to groups on other CP chips within the drawer. The utilization of each L2 cache <NUM> within a cache cluster <NUM> can be analyzed for determining the target cache to persist the cache eviction. On a further eviction of the same cache line from the target cache on primary cluster, the replacement policy then tries to pick a cache from the secondary cluster for the castout to persist using the same prior utilization analysis. On the following castout from the last scope, the line would be written to memory if changed or else just dropped. In the absence of an empty compartment in the target cache, a persistence install might cause a castout in the target lateral cache(cascading castout), where the cascading castout is sent for persistence in the following scope until an empty compartment is available at the next scope or the chain of castouts reaches the last scope of persistence. The processor can decide to bypass all the cascading castouts to memory under certain utilization thresholds or contention in the system Several utilization thresholds can be used for determining whether to keep the cache eviction within a certain level of scope. For example, if the utilization rate for the caches in the first cache cluster is higher than a first threshold, then the replacement policy looks to the second cache cluster on the same CP chip for evicting the cache line. If the utilization rate of the L2 caches in the second cache cluster is also higher than the first threshold utilization rate, then the replacement policy looks to the third cache cluster on a different CP chip and so on and so forth.

In one or more embodiments of the invention, the replacement policy executed by the cache controller <NUM> can determine a target cache for an evicted cache line by keeping a counter ("saturation counter") for each cache in the system <NUM>. The counter can track a saturation metric for each cache <NUM> in the system <NUM>. Initially, cache lines can be persisted by searching for target caches within the home cache cluster <NUM> of the cache line being evicted. The counter for each cache <NUM> can be used to track saturation metrics of the cache. This saturation metric (i.e., utilization) can include the number of installs in a cache from the core/cores attached to it (fetch misses), the number of installs of cast-outs from lateral caches (peer cache), etc. where the counter increments per install event. This counter provides a metric for the combined activity of the cores attached to the caches and the cast-outs the cache has received from peer lateral caches. In the event of a cache eviction from a cache, the cache line is sent to persist in a lateral cache with the lowest saturation counter value or a lateral cache with a saturation counter value less than the first cache doing the eviction or broadcast to a group of less active caches so that the less busy cache (at the time of eviction) accepts the cache line.

In one or more embodiments of the invention, the replacement policy determines a target cache for a cache eviction based on the LP bits for the cache line being evicted and the utilization of the lateral caches. Once a target cache is determined, the replacement policy further is utilized to determine where to place the cache line within the target cache. <FIG> depicts a block diagram of an exemplary target cache according to one or more embodiments of the invention. The exemplary target cache <NUM> is an <NUM>-way cache which can store <NUM> cache lines. The exemplary cache <NUM> utilizes an adaptive least recently used (LRU) algorithm for managing the cache lines within the cache <NUM>. LRU is a cache replacement algorithm that discards the least recently used cache line first whenever there is a need to write to the cache <NUM>. The LRU algorithm supports multiple install positions including MRU, Mid-LRU, quarter-LRU, LRU and any partial install position in-between. Also, the LP tag bits can be used to discern the lines installed directly by the local processor versus the lateral castouts by peer caches from any scope. Scanning a given congruence class gives a gauge for activity distribution between the core/cores attached to the cache <NUM> and the castouts it has received from the lateral caches. At the time of install, all the castouts persisted from lateral caches get a partial placement in the LRU tree initially. All the lines installed by local processor fetches would get an MRU placement. Once the percentage of lines installed by lateral castouts crosses a threshold of total capacity of the congruence class, the newly persisted entries get a larger partial/MRU placement. The larger partial and partial placements can be configured based on the workload needs. This adaptive LRU placement policy dynamically accommodates the caches to contain more local installs and locally re-referenced lines when the local processor is active and more persisted entries when the local processor is dormant. For example, if the minimum capacity threshold for persisted entries in a cache was set to <NUM>%, the persisted entries would get partial placement until the number of persisted entries(including the current install <NUM>) in the congruence class are less than <NUM>% of congruence class capacity. Thereafter, they get a larger partial/MRU placement. In the illustrated example, with threshold set to <NUM>%, the current install cache line <NUM> is a persisted install(LP greater than <NUM>), and the total persisted installs are <NUM>. So line <NUM> would still get a partial MRU placement. Once the persisted installs are <NUM>, the about to be persisted install would get an MRU placement.

In one or more embodiments of the invention, the determined utilization rate of a target cache can dictate how a cache line is installed and how many peer cache lines can be installed within the target cache. For example, if the target cache has a very low utilization rate (e.g., is less than a pre-defined threshold), then the target cache can have most, if not all, lateral cache lines installed within the target cache. Multiple threshold utilization rates can be defined which dictate how many peer cache lines can be installed. The number of cache lines can be defined by a percentage of the memory available (<NUM>%, <NUM>%, etc. of the cache memory) or a number.

In one or more embodiments of the invention, cache clusters <NUM> can be defined using a variety of means such as, for example, selecting a number of caches within a CP chip <NUM>, selecting a number of caches within a drawer <NUM>, and/or selecting a number of caches across drawers <NUM>. Defining the cache clusters in the system can be done based on the locality of peer caches like taking the data sourcing latency into effect and/or workload dispatch patterns and/or OS/software directive hints. Scopes/cache clusters can be changed over time based on hypervisor hints and/or processor types attached to a cache and/or including the directives mentioned above. Also, not all clusters have the same number of L2 caches.

<FIG> depicts a flow diagram of a method <NUM> for lateral cache persistence according to one or more embodiments of the invention. At least a portion of the method <NUM> can be executed, for example, by the processor <NUM> shown in <FIG>. The method <NUM> includes defining scopes and/or clusters for a plurality of caches in a symmetrical multiprocessing (SMP) system, as shown in block <NUM>. This includes having a data processing system including several processor units, wherein each processor unit contains a processor with an associated upper and lower-level cache (L2), coupled together by an interconnect fabric. The data in the cache is arranged into congruence classes that contain a number of cache lines, and theses congruence classes also include a chronology vector used to determine which entry to evict. The chronology vector (age bit) tracks the age of the cache line in the cache. The clusters of caches are arranged into a plurality of scope domains, called primary, secondary, and tertiary, which can be extended into an infinite number of unique scopes. In the event of a cache eviction and a cache has been determined to be evicted, the processing cache determines if the entry should be laterally castout (LCO) to a peer cache within a primary castout scope (PCO), a secondary castout scope (SCO), or written back to memory as a tertiary castout (TCO). At block <NUM>, the method <NUM> includes defining both a methodology and a metric to track the activity of the caches in the system. Upon determining which cache line to evict, the processing cache determines if the entry should be laterally castout (LCO) to a peer cache within a primary castout scope (PCO), a secondary castout scope (SCO), written back to memory as a tertiary castout (TCO). Within each of the target scope, the activity of the caches are tracked using a saturation counter that tracks the number of installs as defined by processor misses into each cache. At block <NUM>, the method <NUM> includes defining a threshold for the persisted entries capacity within a congruence class. Installed cache lines for a given cache can be tracked by various requester types such, for example, a local processor fetch versus a lateral castout from another cache. The install position of a cache line can be based on the percentage of lines installed by processor fetches versus lateral castouts. When the cache line is installed in the cache on a lateral castout, the cache line is placed in a non-MRU (most recently used) position initially. Once the percentage of cache lines installed by lateral castouts crosses a pre-defined threshold of the total capacity of the congruence class, the persisted cache entries get a larger partial/MRU placement. At block <NUM>, the method <NUM> includes receiving a request to evict a cache line (LCO) having lateral persistence bits tracking the current scope of persistence for the cache line. The current scope of a cache line is determined using the lateral persistence tag bits which are set to zero when the line is installed or re-referenced by a processor and incremented every time a line is evicted from a current cache and persisted in any of the caches at the next scope.

In one or more embodiments of the invention, the method <NUM>, at block <NUM>, includes determining a target cache for writing the LCO where the target cache is among the higher scope of persistence than the current scope. The current scope is determined based on the activity of the caches using counters that track the number of installs as defined by processor misses into each cache and least active cache is picked as a target to persist the castout. The castout can be sent to a group of less active caches. The counters track the number of invalidations from local and/or remote cores, the number of lateral castout installs, and the number of total castouts (as defined by local evictions and/or invalidations from local/remote cores and/or peer cache evictions). The counters can be implemented as an LRU tree algorithm, for example. In one or more embodiments of the invention, the method <NUM> includes decision block <NUM> which includes determining if the target cache has no empty compartments for an install and then determining the cascading castout methodology for making space for the LCO install. That is to say, the evicted entry being sent for persisting might cause a castout in the target lateral cache in the absence of an empty compartment. In this case, a cascading castout is sent for persistence in the following group until an empty compartment is available at the next scope and/or the chain of castouts reaches the last scope of persistence. In that case, if the replacement algorithm decides the system is under contention/busy, the cascading castouts are bypassed to main memory. Once a target cache is determined with or without cascading and the cache line is not written to memory, the method <NUM> includes writing the LCO to the target cache and setting the LP tag bits to the target cache's scope, as shown in block <NUM>. And at block <NUM>, the method <NUM> includes scanning the congruence class of the target cache for the number of persisted entries and based on the threshold, place the LCO in the target cache in the respective partial/larger partial MRU position. The chronology vector includes a cache replacement algorithm that supports multiple install positions including MRU, Mid-LRU, LRU, and any partial install position in-between. As the percentage of lines installed in lateral castouts crosses a threshold of the capacity of the congruence class, the persisted entries get a larger partial/MRU placement.

Additional processes may also be included. It should be understood that the processes depicted in <FIG> represent an illustrations and that other processes may be added or existing processes may be removed, modified, or rearranged without departing from the scope of the present disclosure.

<FIG> depicts a flow diagram of a method <NUM> for lateral cache persistence according to one or more embodiments of the invention. At least a portion of the method <NUM> can be executed, for example, by the processor <NUM> shown in <FIG>. The method <NUM> includes defining one or more processor units having a plurality of caches, wherein each processor unit comprises a processor having at least one cache from the plurality of caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric, as shown in block <NUM>. At block <NUM>, the method <NUM> includes for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class in the one or more congruence classes comprises a chronology vector. Then, the method <NUM> includes arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, as shown at block <NUM>. Also, at block <NUM>, the method <NUM> includes determining a first cache line to evict based on the chronology vector for the first cache line. And, at block <NUM>, the method <NUM> includes determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

<FIG> depicts a flow diagram of a method <NUM> for lateral cache persistence according to one or more embodiments of the invention. At least a portion of the method <NUM> can be executed, for example, by the processor <NUM> shown in <FIG>. The method <NUM> includes receiving a request to evict a first cache line from a first cache on a first microprocessor chip in a plurality of microprocessor chips in a processing drawer, the first cache line having a first set of lateral persistence bits tracking a scope for the first cache line, as shown at block <NUM>. At block <NUM>, the method <NUM> includes determining the scope of the first cache line. Also, the method <NUM>, at block <NUM>, includes identifying a target cache having a saturation metric, wherein the target cache comprises a higher scope than the scope of the first cache line. And at block <NUM>, the method <NUM> includes determining an action for the first cache line based on the saturation metric for the target cache and the scope of the first cache line.

Additional processes may also be included. It should be understood that the processes depicted in <FIG> represent an illustration, and that other processes may be added or existing processes may be removed, modified, or rearranged without departing from the scope of the present disclosure.

Turning now to <FIG>, a computer system <NUM> is generally shown in accordance with an embodiment. The computer system <NUM> can be an electronic, computer framework comprising and/or employing any number and combination of computing devices and networks utilizing various communication technologies, as described herein. The computer system <NUM> can be easily scalable, extensible, and modular, with the ability to change to different services or reconfigure some features independently of others. The computer system <NUM> may be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer system <NUM> may be a cloud computing node. Computer system <NUM> may be described in the general context of computer system executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, and so on that perform particular tasks or implement particular abstract data types. Computer system <NUM> may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

As shown in <FIG>, the computer system <NUM> has one or more central processing units (CPU(s)) 601a, 601b, 601c, etc. (collectively or generically referred to as processor(s) <NUM>). The processors <NUM> can be a single-core processor, multi-core processor, computing cluster, or any number of other configurations. The processors <NUM>, also referred to as processing circuits, are coupled via a system bus <NUM> to a system memory <NUM> and various other components. The system memory <NUM> can include a read only memory (ROM) <NUM> and a random access memory (RAM) <NUM>. The ROM <NUM> is coupled to the system bus <NUM> and may include a basic input/output system (BIOS), which controls certain basic functions of the computer system <NUM>. The RAM is read-write memory coupled to the system bus <NUM> for use by the processors <NUM>. The system memory <NUM> provides temporary memory space for operations of said instructions during operation. The system memory <NUM> can include random access memory (RAM), read only memory, flash memory, or any other suitable memory systems.

The computer system <NUM> comprises an input/output (I/O) adapter <NUM> and a communications adapter <NUM> coupled to the system bus <NUM>. The I/O adapter <NUM> may be a small computer system interface (SCSI) adapter that communicates with a hard disk <NUM> and/or any other similar component. The I/O adapter <NUM> and the hard disk <NUM> are collectively referred to herein as a mass storage <NUM>.

Software <NUM> for execution on the computer system <NUM> may be stored in the mass storage <NUM>. The mass storage <NUM> is an example of a tangible storage medium readable by the processors <NUM>, where the software <NUM> is stored as instructions for execution by the processors <NUM> to cause the computer system <NUM> to operate, such as is described herein below with respect to the various Figures. Examples of computer program product and the execution of such instruction is discussed herein in more detail. The communications adapter <NUM> interconnects the system bus <NUM> with a network <NUM>, which may be an outside network, enabling the computer system <NUM> to communicate with other such systems. In one embodiment, a portion of the system memory <NUM> and the mass storage <NUM> collectively store an operating system, which may be any appropriate operating system, such as the z/OS or AIX operating system from IBM Corporation, to coordinate the functions of the various components shown in <FIG>.

Additional input/output devices are shown as connected to the system bus <NUM> via a display adapter <NUM> and an interface adapter <NUM> and. In one embodiment, the adapters <NUM>, <NUM>, <NUM>, and <NUM> may be connected to one or more I/O buses that are connected to the system bus <NUM> via an intermediate bus bridge (not shown). A display <NUM> (e.g., a screen or a display monitor) is connected to the system bus <NUM> by a display adapter <NUM>, which may include a graphics controller to improve the performance of graphics intensive applications and a video controller. A keyboard <NUM>, a mouse <NUM>, a speaker <NUM>, etc. can be interconnected to the system bus <NUM> via the interface adapter <NUM>, which may include, for example, a Super I/O chip integrating multiple device adapters into a single integrated circuit. Suitable I/O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols, such as the Peripheral Component Interconnect (PCI). Thus, as configured in <FIG>, the computer system <NUM> includes processing capability in the form of the processors <NUM>, and, storage capability including the system memory <NUM> and the mass storage <NUM>, input means such as the keyboard <NUM> and the mouse <NUM>, and output capability including the speaker <NUM> and the display <NUM>.

In some embodiments, the communications adapter <NUM> can transmit data using any suitable interface or protocol, such as the internet small computer system interface, among others. The network <NUM> may be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, among others. An external computing device may connect to the computer system <NUM> through the network <NUM>. In some examples, an external computing device may be an external webserver or a cloud computing node.

It is to be understood that the block diagram of <FIG> is not intended to indicate that the computer system <NUM> is to include all of the components shown in <FIG>. Rather, the computer system <NUM> can include any appropriate fewer or additional components not illustrated in <FIG> (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Further, the embodiments described herein with respect to computer system <NUM> may be implemented with any appropriate logic, wherein the logic, as referred to herein, can include any suitable hardware (e.g., a processor, an embedded controller, or an application specific integrated circuit, among others), software (e.g., an application, among others), firmware, or any suitable combination of hardware, software, and firmware, in various embodiments.

Various embodiments of the invention are described herein with reference to the related drawings. Various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein.

One or more of the methods described herein can be implemented with any or a combination of the following technologies, which are each well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc..

For the sake of brevity, conventional techniques related to making and using aspects of the invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs to implement the various technical features described herein are well known. Accordingly, in the interest of brevity, many conventional implementation details are only mentioned briefly herein or are omitted entirely without providing the well-known system and/or process details.

In some embodiments, various functions or acts can take place at a given location and/or in connection with the operation of one or more apparatuses or systems. In some embodiments, a portion of a given function or act can be performed at a first device or location, and the remainder of the function or act can be performed at one or more additional devices or locations.

The present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the disclosure.

The diagrams depicted herein are illustrative. There can be many variations to the diagram or the steps (or operations) described therein without departing from the scope of the disclosure. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term "coupled" describes having a signal path between two elements and does not imply a direct connection between the elements with no intervening elements/connections therebetween. All of these variations are considered a part of the present disclosure.

Additionally, the term "exemplary" is used herein to mean "serving as an example, instance or illustration. " Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms "a plurality" are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term "connection" can include both an indirect "connection" and a direct "connection.

For example, "about' can include a range of ± <NUM>% or <NUM>%, or <NUM>% of a given value.

In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instruction by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Claim 1:
A computer-implemented method comprising:
defining (<NUM>) one or more processor units (<NUM>) having a plurality of peer lateral caches (<NUM>), wherein each processor unit comprises a processor having at least one cache from the plurality of peer lateral caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric;
for each of the plurality of peer lateral caches, arranging (<NUM>) a plurality of cache lines into one or more congruence classes, wherein each congruence class in the one or more congruence classes comprises a chronology vector;
arranging (<NUM>) each cache in the plurality of peer lateral caches into a cluster (<NUM>) of caches, each cluster of caches being assigned to a scope domain corresponding to a scope of persistence;
determining (<NUM>) a first cache line to evict based on an age of the first cache line indicated by the chronology vector; and
determining (<NUM>) a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein:
the scope of the first cache line comprises a scope of persistence and is determined based on lateral persistence tag bits; and
the saturation metric comprises at least one of a number of installs defined by processor misses and a number of installs in a cache from lateral caches.