Patent Description:
Abbreviations appearing relatively infrequently in this document are defined upon initial usage, while abbreviations appearing more frequently in this document are defined below:.

PAICs commonly contain multiple ESD protection structures to protect FETs and other devices formed on a semiconductor die and vulnerable to over-voltage damage during an ESD event. By common design, ESD protection structures are realized as ADs formed in a metal layer system produced over a semiconductor substrate, such as APDs formed over a singulated piece of a bulk silicon wafer. Industry demands have urged the continued miniaturization of PAIC-bearing semiconductor dies (herein, "PAIC dies") due, in part, to the development of massive multi-input, multi-output (MIMO) systems and small cell, beam forming cellular technologies reliant upon increased spatial diversity of RF signals; e.g., to signal boost throughput for <NUM> cellular networks. As the planform dimensions (widths and lengths) of PAIC dies has decreased, while the number of ESD protection structures integrated into many PAIC die topologies has grown, the fraction of the available IC floor space exclusively devoted to accommodating ESD protection structures has also risen. Consequently, ESD protection structures have now become undesirably space-dominant in many current PAIC die topologies, particularly in the case of PAIC die topologies designed for small cell, lower power applications.

<CIT> describes Electrostatic Discharge (ESD) protection using lateral surface Schottky diodes. A Metal-Insulator-Metal (MIM) capacitor with ESD protection comprises a group III-V substrate, a first metal layer contacting the substrate, an insulation layer formed over the first metal layer, and a second metal layer formed over the insulation layer and also contacting the substrate. A MIM capacitor is formed by overlapping portions of the first metal layer, the insulation layer, and the second metal layer. First and second Schottky diodes are formed where the first and second metal layers, respectively, contact the substrate, such that the cathodes of the Schottky diodes are electrically connected to one another and the anodes of the Schottky diodes are electrically connected to the respective overlapping portions of the first and second metal layers.

<CIT> describes a semiconductor device (chip) constituting a wide-band low-noise amplification GaAs IC that has a structure where a FET part and a capacitance part, whichare situated to be adjacent on a main face of a semiinsulating GaAs substrate. For the capacitance part, a Schottky capacitance is formed of an n-type layer for Schottky capacitance formation use and of a Schottky electrode, for capacitance use, formed on the n-type layer <NUM> for Schottky capacitance formation use; an MIM capacitance is formed of the Schottky electrode for capacitance use, an insulating film formed on the Schottky electrode for capacitance use and a wiring electrode formed on the insulating film.

<CIT> describes a capacitor structure comprising an array having two dimensions and having first and second electrode elements alternating in both dimensions of the array, the first electrode elements interconnected and the second electrode elements interconnected, to cause the array to function as a capacitor. The capacitor structure further comprises a dielectric material, which may be silicon dioxide, separating the first and second electrode elements in both of the dimensions. The first electrode elements are interconnected by a first interconnect, and the second electrode elements are interconnected by a second interconnect. A method for forming such a capacitor and an IC including the capacitor is also disclosed.

According to an aspect, there is provided an integrated circuit according to claim <NUM>.

Further features according to embodiments are defined in the dependent claims.

At least one example of the present invention will hereinafter be described in conjunction with the following figures, wherein like numerals denote like elements, and:.

For simplicity and clarity of illustration, descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the example and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.

Embodiments of the present disclosure are shown in the accompanying figures of the drawings described briefly above. Various modifications to the embodiments may be contemplated by one of skill in the art without departing from the scope of the present invention, as set-forth the appended claims.

The following definitions apply throughout this document. Those terms not expressly defined here or elsewhere in this document are assigned their ordinary meaning in the relevant technical field.

Patterned metal layer-a single layer or multilayer body of material patterned to define electrically-conductive features, such as traces or interconnect lines, and predominately composed of at least one metal constituent by weight.

Metal layer system-a layered structure including multiple patterned metal layers (defined above) and dielectric layers formed over a substrate, such as the active surface of a transistor-bearing semiconductor die.

Metal-insulator-metal (MIM) capacitor-a capacitor integrally formed in a metal layer system (defined above) and including patterned metal regions defining at least two capacitor plates separated by at least one intervening dielectric layer.

Power Amplifier Integrated Circuit (PAIC) die-a semiconductor die on which at least one power amplifier transistor is fabricated, possibly in addition to a vertically-integrated capacitor-AD structure (examples of which are described below) and other integrated devices.

Vertically-overlapping-a term utilized to describe the spatial relationship between two structures or elements, such as a MIM capacitor and an AD, formed on substrate and at least partially overlapping along an axis orthogonal to a principal (e.g., upper or active) surface of the substrate.

As previously indicated, an ongoing industry demand exists for the development of PAICs and other integrated circuits amenable to size and cost reductions, while possessing ESD-protection capabilities comparable to, if not superior to conventional IC designs containing AD elements. In satisfaction of this industrial demand, the following disclosure describes integrated circuits, such as PAICs, containing unique, vertically-integrated capacitor-AD structures. The vertically-integrated capacitor-AD structures provide capacitance and ESD protection functions in a three dimensional space having a compact footprint. Embodiments of the vertically-integrated capacitor-AD structure include at least one MIM capacitor and at least one AD element or device (herein referred to simply as an "AD") formed in a metal layer system, which is produced over a principal surface of a semiconductor substrate. The substrate surface over which the metal layer system is fabricated is further referred to herein as the "upper principal surface" of the semiconductor substrate, with the metal layers likewise referred to as "upper" or "lower" metal (or dielectric) layers formed "above" or "below" each other, as the case may be. Such terms of orientation are defined in a relative sense in view of proximity of the named layers (or other elements) to the upper principal surface of the semiconductor substate. Such terms should thus not be considered limiting, noting that a given integrated circuit can function in any orientation in three dimensional space and may be attached to a larger system substrate (e.g., a printed circuit board) in an inverted or "flip chip" orientation in certain instances. Finally, as further appearing herein, the term "avalanche diode" and the corresponding abbreviation "AD" refers to a diode designed to breakdown and conduct current at a particular trigger (reverse bias) voltage due to the occurrence of the avalanche effect within the semiconductor material (e.g., polysilicon) of the diode.

Embodiments of the below-described integrated circuit or IC die include at least one transistor in addition to at least one vertically-integrated capacitor-AD structure. In embodiments in which the integrated circuit is a PAIC, the transistor may assume the form of power amplifier transistor(s), such as FETs, with the power amplifier transistor(s) and the vertically-integrated capacitor-AD structure(s) fabricated on a common semiconductor substrate or die body. The semiconductor substrate can be fabricated from any material or group of materials, providing that at least a portion of the substrate is composed of a semiconductor material and is suitable for IC fabrication. In embodiments, the semiconductor substrate may assume the form of a singulated piece of a bulk silicon (Si) wafer, in which case the below-described ADs may be specifically implemented as APDs contacting the upper principal surface of the Si IC die. In other embodiments, the semiconductor substrate may be composed of a different semiconductor material (examples of which are listed below) or may be layered structure containing, for example, a buried oxide layer. When the integrated circuit assumes the form of a PAIC incorporated into a Doherty power amplifier system, the power amplifier transistor can be, for example, a power amplifier FET that functions to amplify a peaking or carrier signal during system operation. In other instances, a different transistor technology can be employed and/or the PAIC may be integrated into a different type of power amplifier system, such as a push-pull type amplifier system.

Regardless of the particular type of system in which the integrated circuit is employed, size reduction of the integrated circuit is enabled through the incorporation of one or more vertically-integrated capacitor-AD structures into the integrated circuit. Within a given vertically-integrated capacitor-AD structure, at least one MIM capacitor and at least one AD are disposed in a vertically-overlapping relationship such that at least a portion of the MIM capacitor and at least a portion of the AD (if not the majority or substantial entirety of the MIM capacitor and the AD structure by planform surface area) overlap as taken along a vertical axis orthogonal to the upper principal surface of the semiconductor substrate. The AD (or ADs) included in a given vertically-integrated capacitor-AD structure, specifically, may be located at or coplanar with the interface of the upper principal surface of the substrate and include metal features formed in an initially-deposited or "M1" metal layer included in the metal layer system. While a given AD may be described as formed "in" the metal layer system herein, it will be appreciated that current conducted across the AD (when the breakdown voltage is surpassed during an ESD event) will pass through the regions of the semiconductor substate located beneath and spanning the elongated conductive electrodes or "fingers" of the AD. Further, in embodiments, the MIM capacitor may be formed over the AD such that at least a majority of the surface area of the AD, if not the substantial entirety of the AD is located beneath by the MIM capacitor, when viewed along the vertical axis looking downwardly on the semiconductor substrate. Concurrently, sufficient vertical spacing is provided between the MIM capacitor (or capacitors) and the AD (or ADs) and filled, in whole or in part, with a dielectric material to allow substantially independent, unimpeded operation of both the MIM capacitor and AD. Upon occurrence of an ESD event, however, the AD is configured to rapidly reach breakdown voltage and allow current to flow between the input and output terminals of the vertically-integrated capacitor-AD structure, while bypassing the MIM capacitor to protect the MIM capacitor from potential over-voltage damage.

The space savings afforded by incorporation of one or more vertically-integrated capacitor-AD structures into a given PAIC or other integrated circuit can be exploited to reduce the overall footprint and, therefore, the overall cost of the integrated circuit or IC die as desired. Alternatively, such space savings can be leveraged to introduce additional circuit elements into the IC design and/or to grow the dimensions and capacity of existing circuit elements. Additionally, embodiments of the vertically-integrated capacitor-AD structure may provide benefits beyond permitting a more efficient usage of IC floor space. Performance benefits, such as reduced parasitic capacitances and reduced current leakage, may also be achieved by the vertically-integrated capacitor-AD structure in at least some embodiments for reasons explained below. Further, embodiments of the vertically-integrated capacitor-AD structure provide a high level of design flexibility, allowing the integration of varying combinations of MIM capacitors and ADs within a given vertically-integrated capacitor-AD structure, as well as varying combinations of interconnection schemes; e.g., in embodiments in which multiple ADs are integrated into a vertically-integrated capacitor-AD structure, interconnect features (e.g., traces and other conductive features within the metal layer system) may be formed to electrically connect the ADs in parallel across the terminals of the vertically-integrated capacitor-AD structures or, instead, to connect the ADs in series for increased breakdown voltage and reduced current leakage. As a still further benefit, embodiments of the vertically-integrated capacitor-AD structure can be integrated into existing manufacturing process flows and IC designs with minimal cost and modifications. A first example PAIC or PAIC die including a vertically-integrated capacitor AD structure will now be described in connection with <FIG>, with additional example vertically-integrated capacitor-AD structures further discussed below in connection with <FIG>. While described below in conjunction with a particular PAIC die having certain physical characteristics, it is emphasized that embodiments of the vertically-integrated capacitor AD structure can be incorporated into various different IC designs without limitation when, for example, a compact ESD protection-capacitor hybrid solution is beneficially applied.

<FIG> is a generalized planform or top-down view of a PAIC <NUM> containing at least one vertically-integrated capacitor-AD structure <NUM>, as illustrated in accordance with an embodiment. PAIC <NUM> (also referred to as "PAIC die <NUM>") is fabricated on a semiconductor substrate or die body <NUM>. As indicated above, semiconductor substrate <NUM> can be wholly composed of a semiconductor material, such a Si, in embodiments; or can be a layered structure, providing that substrate <NUM> is at least partially composed of a semiconductor material contacted by the AD (or ADs) included within vertically-integrated capacitor-AD structure <NUM>, as described below. Various other components are fabricated on semiconductor substrate <NUM> including, most pertinently, a power amplifier FET <NUM> and several additional ESD protection structures <NUM>. The particular circuit topology of PAIC <NUM> is generally inconsequential to embodiments of the present disclosure and will thus not be described in detail, aside from briefly noting that PAIC <NUM> may also include any number of additional circuit elements formed on semiconductor substrate <NUM> including inductive elements (e.g., spiral inductors <NUM>, <NUM>), capacitive elements, transmission lines, landing or bond pads (e.g., bond pads <NUM>, <NUM>), and other such circuit elements completing the desired power amplifier topology. Collectively such circuit elements may form or help form impedance matching network(s) on the input side and/or output side of power amplifier FET <NUM>, noting that additional impedance matching is typically provided offboard PAIC <NUM>; e.g., via additional circuitry mounted to a printed circuit board to which PAIC <NUM> (or a microelectronic package containing PAIC <NUM>) may be attached. So too may PAIC <NUM> include circuitry supporting biasing of one or more terminal of power amplifier FET <NUM> in embodiments. In various implementations, PAIC <NUM> is included in a larger Doherty PA system or circuit, with FET <NUM> providing amplification of the carrier or peaking signal transmitted through the Doherty PA system.

As noted above, PAIC <NUM> includes a power amplifier transistor in the form of FET <NUM> in the illustrated example. In further embodiments, PAIC <NUM> can differ to varying extents and may potentially include multiple FETs collectively forming a multi-stage amplifier and/or can include a different type of transistor, such as one or more bipolar transistors. The manner in which FET <NUM> is implemented will also vary based on the composition of semiconductor substrate <NUM>, with FET <NUM> potentially implemented utilizing any of the following: a silicon-based FET (e.g., a laterally-diffused metal oxide semiconductor FET or LDMOS FET) or a III-V FET (e.g., a gallium nitride (GaN) FET, a gallium arsenide (GaAs) FET, a gallium phosphide (GaP) FET, an indium phosphide (InP) FET, or an indium antimonide (InSb) FET, or another type of III-V transistor). Considering this, the following description of power amplifier FET <NUM> and, more broadly, of PAIC <NUM> should be understood as establishing a non-limiting example context in which embodiments of vertically-integrated capacitor-AD structure <NUM> can be better understood. This stated, in various implementations, power amplifier FET <NUM> may be produced as a silicon-based FET, such as a LDMOS FET, fabricated on bulk Si wafer subsequently singulated to yield semiconductor substrate <NUM>. Power amplifier FET <NUM> includes a gate terminal formed with or otherwise connecting to a gate manifold <NUM>, a plurality of elongated gate contact fingers <NUM> extending from gate manifold <NUM> (only one of which is labeled in <FIG>), a drain terminal formed with or connecting to a drain manifold <NUM>, and a plurality of elongated drain lines <NUM> extending from drain manifold <NUM> (again, only one of which is labeled). Such features of FET <NUM> may be defined by patterning of the below-described M1 layer in at least some implementations. Source and drain regions are created by doping selected regions of semiconductor substrate <NUM> during transistor fabrication; e.g., as seen looking downwardly onto upper principal surface <NUM>, each source region may be located between or laterally bordered by two of drain lines <NUM> and two underlying drain regions, which are, in turn, located between or bordered by two of gate contact fingers <NUM>. A comb-type or interdigitated transistor finger arrangement is thus provided in the illustrated example. Other transistor configurations are possible in further implementations.

Vertically-integrated capacitor-AD structure <NUM> is electrically coupled between a terminal (here, an RF input terminal <NUM>) of PAIC <NUM> and an input terminal (herein, a gate control terminal <NUM>) of power amplifier FET <NUM>. As indicated above, vertically-integrated capacitor-AD structure <NUM> contains at least one AD, which protects at least one MIM capacitor <NUM> from damage should an ESD event occur. The AD is located at elevation beneath MIM capacitor <NUM> within a metal layer system formed over the upper surface of semiconductor substrate <NUM>. Specifically, the AD may be located directly below and centered beneath MIM capacitor <NUM>, as taken along an axis orthogonal to the upper principal surface of semiconductor substrate <NUM> on which power amplifier FET <NUM> and the other circuit elements are formed. The AD contained within vertically-integrated capacitor-AD structure <NUM> is thus hidden in the planform view of PAIC <NUM> shown in <FIG>. In other, more traditional designs lacking a vertically-integrated capacitor-AD structures, an APD or similar ESD protection element may be disposed adjacent MIM capacitor <NUM> in a side-by-side arrangement; e.g., in an alternative version of the illustrated example, an ESD protection element could potentially be fabricated in the multilayer system formed over semiconductor substrate <NUM> at a location to the left or right of MIM capacitor <NUM>. Such an arrangement, however, occupies a considerably larger fraction of the available floor space of the PAIC <NUM> than does the illustrated capacitor-AD structure <NUM>. Additionally, such side-by-side positioning of the MIM capacitor (or capacitors) and the AD (or ADs) can create a relatively tortuous electrical conduction path through the AD, which can potentially introduce undesired delay in the breakdown reaction time during an ESD event or otherwise negatively impact AD performance. For at least these reasons, the illustrated capacitor-AD structure <NUM> is provided with the vertically-integrated, three dimensional architecture, an example of which will now be discussed in connection with <FIG>. While only including a single vertically-integrated capacitor-AD structure <NUM> in the illustrated example, PAIC <NUM> (or another such PAIC) can include multiple instances of vertically-integrated capacitor-AD structures <NUM> in further implementations.

<FIG>, <FIG>, and <FIG> are isometric, top-down, and side views, respectively, of vertically-integrated capacitor-AD structure <NUM>, as depicted in accordance with an embodiment of the present disclosure. In this particular example, vertically-integrated capacitor-AD structure <NUM> is fabricated substantially within a metal layer system <NUM> including five metal levels or layers, which are successively deposited over an upper principal surface <NUM> of semiconductor substrate <NUM>. Upper principal surface <NUM> of semiconductor substrate <NUM> is an active surface of substrate <NUM> at or on which power amplifier FET <NUM> is also fabricated; noting that portions of FET <NUM> will be located below surface <NUM> (e.g., the doped source and drain regions of FET <NUM>), while other portions of FET <NUM> are located above surface <NUM> (e.g., the gate and drain lines). The first-formed patterned metal layer included in metal layer system <NUM> contacts upper principal surface <NUM> of semiconductor substrate <NUM>. This patterned metal layer is referred to hereafter as the "M1" metal layer by common nomenclature, as indicated by a key <NUM> appearing in the upper left of <FIG>.

Continuing the naming convention of the previous paragraph, the second-formed patterned metal layer included in metal layer system <NUM> (that is, the metal layer deposited over the M1 metal layer, as seen looking downwardly onto upper principal surface <NUM> along a vertical axis orthogonal to surface <NUM> and corresponding to the Z-axis of coordinate legend <NUM>) is referred to herein as the "M2" metal layer. The third-formed patterned metal layer deposited over the M2 metal layer is referred to as the "M3" metal layer; the fourth-formed patterned metal layer deposited over the M3 metal layer is referred to as the "M4" metal layer; and, lastly, the fifth-formed patterned metal layer deposited over the M4 metal layer is referred to as the "M5" metal layer. As further indicated by key <NUM>, different cross-hatch patterns are utilized to visually distinguish between the different metal layers, as well as between a number of vias connecting different patterned regions of the M1-M5 metal layers, as described below. While the M1-M5 layers are each referred to as a single "layer" by conventional practice, it will be appreciated that each of the M1-M5 layers may be composite structures composed of multiple layers in embodiments. For example, any one or all of the M1-M5 layers may be each be composed of a seed layer over which a thicker metal (e.g., copper or aluminum) layer is electroplated or otherwise deposited. This stated, the metal layers included in metal layer system <NUM> can be produced utilizing any suitable fabrication technique and composed of any electrically-conductive material or materials, providing the metal layers are predominately composed of at least one metal constituent by weight.

The M1-M5 metal layers are formed at different elevations or levels in a body of dielectric material <NUM>. Dielectric body <NUM> is shown in phantom in <FIG> to more clearly reveal the internal features of vertically-integrated capacitor-AD structure <NUM>. Although generally illustrated as a coherent mass, dielectric body <NUM> may be gradually compiled from multiple dielectric layers (deposited or grown) during the build-up process utilized to fabricate metal layer system <NUM>. Additionally, a discrete body or layer of a dielectric material <NUM> may further be contained in metal layer system <NUM> in embodiments. Dielectric layer <NUM> may specifically provide electrical insulation between the plates of MIM capacitor <NUM> and may thus be referred to as "MIM dielectric layer <NUM>" below. MIM dielectric layer <NUM> may be composed of a different dielectric material than is the larger surrounding dielectric body <NUM>. Specifically, according to the invention, MIM dielectric layer <NUM> is composed of a material having a higher dielectric constant than the dielectric constant of the larger body of dielectric material <NUM>; e.g., MIM dielectric layer <NUM> may be composed of a nitride, such as silicon nitride (e.g., Si<NUM>N<NUM>), while dielectric body <NUM> may be composed of a silicon oxide (SiOx) vapor deposited utilizing, for example, a tetraethyl orthosilicate (TEOS) chemistry. Although not shown in <FIG>, additional layer(s) can be interspersed with or formed over the M1-M5 metal layers. For example, in some embodiments, one or more passivation layers may be formed over the M5 metal layer, as may any molded (e.g., thermoplastic) layers utilized to encapsulate PAIC <NUM> if contained in an encapsulated microelectronic package. In alternative implementations, metal layer system <NUM> may contain a greater or lesser number of metal layers, providing there exists a sufficient number of metal layers to form both MIM capacitor <NUM> and the below-described AD <NUM> underlying MIM capacitor <NUM>.

In addition to MIM dielectric layer <NUM>, MIM capacitor <NUM> further includes an upper, conductive capacitor electrode or plate <NUM> and a lower, conductive capacitor electrode or plate <NUM>. Capacitor plates <NUM>, <NUM> are separated or offset by a vertical gap or spacing, as identified in <FIG> by arrows G<NUM>. As previously indicated, the term "vertical" is utilized herein to refer to an axis orthogonal to upper principal surface <NUM> of semiconductor substrate <NUM>. The size of this separation gap (G<NUM>), the dielectric constant of MIM dielectric layer <NUM>, and the respective surface areas of capacitor plates <NUM>, <NUM> can be selected, as desired, to impart MIM capacitor <NUM> with a desired capacitance. The capacitance of MIM capacitor <NUM> may range from about <NUM> to about <NUM> picofarads (pF) and, perhaps, from about <NUM> to about <NUM> pF in embodiments. In other implementations, the capacitance of MIM capacitor <NUM> may be greater than or less than the aforementioned ranges. The vertical spacing between lower capacitor plate <NUM> and any given electrode or finger of the below-described AD (again, as measured along a vertical axis orthogonal to upper surface <NUM> of substrate <NUM>) is greater than G1 by a factor of at least two. This vertical spacing (here, measured between lower capacitor plate <NUM> and an outer contact finger <NUM> of AD <NUM>, described below) is also identified in <FIG> by arrow G3.

Upper capacitor plate <NUM> is formed as a patterned portion or region of the uppermost metal (M5) layer. The illustrated portion of the M5 layer is also patterned to define a first terminal <NUM> and a second terminal <NUM> of vertically-integrated capacitor-AD structure <NUM>. Terminals <NUM>, <NUM> are the input and output terminals of vertically-integrated capacitor-AD structure <NUM> in the present example and are consequently respectively referred to as "input terminal <NUM>" and "output terminal <NUM>" below; however, terminal <NUM> can serve as an input terminal and terminal <NUM> can serve as a output terminal in further implementations, providing that an appropriate reverse bias is applied to the below-described AD. The M5 layer is also patterned to defined transmission lines <NUM>, <NUM>, which are partially shown in <FIG>. As best seen in <FIG>, transmission line <NUM> electrically connects RF input terminal <NUM> to input terminal <NUM> of vertically-integrated capacitor-AD structure <NUM>, while transmission line <NUM> electrically connects output terminal <NUM> of vertically-integrated capacitor-AD structure <NUM> to the gate terminal of FET <NUM> through spiral inductor <NUM>. Transmission line <NUM>, in particular, is formed as a relatively wide (e.g., microstrip) transmission line in the illustrated example and has a width substantially equivalent to input terminal <NUM> (which extends over or generally overlies the below-described conductive via <NUM>, <NUM>, <NUM>, <NUM>, as taken along a vertical axis). In other embodiments, the relative dimensions of transmission lines <NUM>, <NUM> and the particular location at which vertically-integrated capacitor-AD structure <NUM> is integrated into PAIC <NUM> may vary.

Upper capacitor plate <NUM> extends from input terminal <NUM> toward output terminal <NUM> along a longitudinal axis of vertically-integrated capacitor-AD structure <NUM>. In the illustrated example, the longitudinal axis of vertically-integrated capacitor-AD structure <NUM> corresponds to the X-axis of coordinate legend <NUM>, with the longitudinal axis thus extending parallel to upper principal surface <NUM> and perpendicular to the previously-mentioned vertical axis. Upper capacitor plate <NUM> terminates prior to reaching output terminal <NUM> such that a longitudinal gap (G2, <FIG>) separates upper capacitor plate <NUM> and output terminal <NUM> to prevent electrical bridging across MIM capacitor <NUM>. Comparatively, lower capacitor plate <NUM> is formed at location beneath upper capacitor plate <NUM>. For example, lower capacitor plate <NUM> may be formed in an underlying (e.g., M4) metal layer, which is further patterned to include two strip-like patterned regions <NUM>, <NUM> to interconnect vias in the below-described via stacks. In this regard, vertically-integrated capacitor-AD structure <NUM> further includes two electrically-conductive vias <NUM>, <NUM>, which extend downwardly from the M5 layer to connect to M4 patterned portions <NUM>, <NUM>, respectively. As most clearly shown in <FIG> (illustrating vertically-integrated capacitor-AD structure <NUM> absent the top conductive (e.g., M5) layer), vias <NUM>, <NUM> are formed as relatively large bar-shaped trench vias in the illustrated example. In other embodiments, vias <NUM>, <NUM> may assume a different form; e.g., each via <NUM>, <NUM> may be replaced by a plurality of smaller vias having generally circular planform geometries and arranged in one or more rows. Via <NUM> contacts and is at a location underlying the patterned region of the M5 layer defining input terminal <NUM>. Similarly, via <NUM> contacts and is formed beneath the patterned portion of the M5 layer defining output terminal <NUM>. Lower capacitor plate <NUM> extends from the portion of the metal layer (e.g., M4) contacting via <NUM> (underlying output terminal <NUM>) toward via <NUM> (underlying input terminal <NUM>), while terminating prior to reaching via <NUM> to provide an isolation gap similar to the above-mentioned isolation gap separating upper capacitor plate <NUM> and output terminal <NUM>. MIM capacitor <NUM> is thus formed in the M4-M5 layers of metal layer system <NUM> to provide the desired capacitance; e.g., to block the application of direct current to the control terminal / gate of (e.g., Si LDMOS) FET <NUM>.

With continued reference to <FIG>, and referring also now to <FIG> (illustrating vertically-integrated capacitor-AD structure <NUM> absent the M4-M5 layers and MIM dielectric layer <NUM>), at least one AD <NUM> is further formed in metal layer system <NUM> at an elevation beneath MIM capacitor <NUM> to protect at least MIM capacitor <NUM> from ESD damage. In the illustrated example, and as shown most clearly in <FIG>, a single AD <NUM> is created by patterning the M1 layer contacting upper principal surface <NUM> of semiconductor substrate <NUM> to include certain features. Those of skill in the art would understand, based on the description herein, that an AD <NUM> may be formed from patterned portions of one or more different layers underlying the MIM capacitor <NUM> (e.g., the M2 or M3 layer(s)). The features of AD <NUM> include: (i) a first AD terminal or manifold <NUM> from which at least one elongated electrode or contact finger <NUM> extends (or to which at least one elongated electrode or contact finger <NUM> is electrically coupled), (ii) a second AD terminal or manifold <NUM> from which at least one elongated electrode or contact finger <NUM> extends (or two which at least one elongated electrode or contact finger <NUM> is electrically coupled), and (iii) a number of electrically-floating fingers <NUM>. Such features (and the M1 layer generally) may be electrically coupled to the semiconductor material of substrate <NUM> by a non-illustrated electrically-conductive (e.g., silicide) contact layer in embodiments. Additionally, in at least some implementations, electrically-floating fingers <NUM> could potentially be electrically coupled to ground by TSVs formed in substrate <NUM> to divert at least a fraction of current to ground during an ESD event.

Given the respective lateral positioning of contact fingers <NUM>, <NUM> in the embodiment shown in <FIG>, contact finger <NUM> is referred to as "central contact finger <NUM>," while contact fingers <NUM> are referred to as "outer contact fingers <NUM>". Central contact finger <NUM> extends from AD manifold <NUM> toward opposing AD manifold <NUM>, with central contact finger <NUM> terminating before reaching AD manifold <NUM> and separated from manifold <NUM> by an isolation gap. This gap may have a width similar, if not identical to the width of isolation gap G2 in embodiments and/or may underly isolation gap G2 along a vertical axis orthogonal to upper surface <NUM> of semiconductor substrate <NUM>. Conversely, outer contact fingers <NUM> extend from AD manifold <NUM> toward opposing AD manifold <NUM>, with outer contact fingers <NUM> likewise terminating before reaching AD manifold <NUM>. Contact fingers <NUM>, <NUM> extend parallel to one another and are spaced along a lateral axis of PAIC <NUM>, which is parallel to upper principal surface <NUM> of semiconductor substrate <NUM> and perpendicular to the vertical axis along which capacitor plates <NUM>, <NUM> are spaced (the lateral axis corresponding to the Y-axis of coordinate legend <NUM>). Floating contact fingers <NUM> likewise extend parallel to contact fingers <NUM>,<NUM>, while disposed in a non-contacting, electrically-isolated relationship (until activation of AD <NUM>) with both AD manifolds <NUM>,<NUM>. Contact fingers <NUM>,<NUM>,<NUM> are elongated along a longitudinal axis perpendicular to the above-described vertical and lateral axes (again, the longitudinal axis corresponding to the X-axis of coordinate legend <NUM>).

In the illustrated embodiment, and as identified in <FIG>, outer contact fingers <NUM> extend from AD manifold <NUM> and are each spaced from the adjacent floating contact finger <NUM> by a first spacing S1, as taken along a lateral axis of PAIC <NUM> (again, corresponding to the Y-axis of coordinate legend <NUM>). Further, each floating contact finger <NUM> is spaced from central contact finger <NUM> by a second spacing S2 along the lateral axis. In an embodiment, spacings S1 and S2 may be substantially equal and/or spacings S1 and S2 may each be greater than the vertical spacing separating capacitor plates <NUM>, <NUM> of MIM capacitor <NUM>. In other embodiments, S1 and S2 may vary relative to the vertical spacing separating capacitor plates <NUM>, <NUM>. So too may the respective dimensions and number of contact fingers <NUM>, <NUM>, <NUM> vary between embodiments (with AD <NUM> potentially lacking floating contact fingers <NUM> in some implementations) depending upon the desired operational characteristics (e.g., breakdown voltage) of AD <NUM>, the surface area allotted for formation of AD <NUM>, and other such factors. Generally, then, it should be understood that the particular topology, dimensions, and shape of those circuit elements making-up AD <NUM> are tunable parameters that can and will vary between embodiments, providing that AD <NUM> is capable of allowing current flow to bypass MIM capacitor <NUM> when reversed biased and the breakdown voltage is surpassed during operation of PAIC <NUM>.

In embodiments, AD <NUM> may have a trigger voltage between <NUM> and <NUM> volts (V) and, perhaps, a trigger voltage between about <NUM> to about 200V. Comparatively, MIM capacitor <NUM> may have an operating voltage between about <NUM> and 75V; and, perhaps, an operating voltage between about <NUM> and 40V. In other embodiments, the trigger voltage of AD <NUM> and the operating voltage of MIM capacitor <NUM> may be greater than or less than the aforementioned ranges. In some instances, the operating voltage of MIM capacitor <NUM> may be at least five times higher (and, in certain cases, between approximately six and nine times higher) than the trigger voltage of AD <NUM>. Finally, although not shown in <FIG> for clarity, a dielectric material (as included in dielectric body <NUM>, <FIG>) fills the space between contact fingers <NUM>, <NUM>, <NUM>. Such a topology (contact finger or electrode arrangement) imparts AD <NUM> with a back-to-back diode arrangement in the present example; that is, contact fingers <NUM>, <NUM>, <NUM> combine with semiconductor substrate <NUM> to form at least two avalanche diode elements arranged in a back-to-back configuration in the embodiment of <FIG>. Other AD topologies can be employed in alternative embodiments of vertically-integrated capacitor-AD structure <NUM>.

As shown most clearly in <FIG>, a first conductive via stack <NUM>, <NUM>, <NUM>, <NUM> (including vias <NUM>, <NUM>, <NUM>, <NUM>) and a second conductive via stack <NUM>, <NUM>, <NUM>, <NUM> (including vias <NUM>, <NUM>, <NUM>, <NUM>) are further formed in metal layer system <NUM> to provide electrical interconnection vertically through the metal layers of system <NUM> and, specifically, between MIM capacitor <NUM> and AD <NUM>. To formed via stack <NUM>, <NUM>, <NUM>, <NUM> and via stack <NUM>, <NUM>, <NUM>, <NUM>, M4-M5 vias <NUM>, <NUM> extend between (and thus electrically connect) patterned portions <NUM>, <NUM> of the M5 layer and patterned portions <NUM>, <NUM> of the M4 layer, respectively. M3-M4 vias <NUM>, <NUM> extend between (and electrically connect) patterned portions <NUM>, <NUM> of the M4 layer and patterned portions <NUM>, <NUM> of the M3 layer, respectively. M2-M3 vias <NUM>, <NUM> extend between and electrically connect patterned portions <NUM>, <NUM> of the M3 layer and patterned portions <NUM>, <NUM> of the M2 layer. Finally, M2-M1 vias <NUM>, <NUM> extend between and electrically connect patterned portions <NUM>, <NUM> of the M2 layer and patterned portions <NUM>, <NUM> (here, AD manifolds <NUM>, <NUM>) of the M1 layer, as shown. Via stack <NUM>, <NUM>, <NUM>, <NUM> thus provides a relatively robust electrical path is thus formed between input terminal <NUM> of vertically-integrated capacitor-AD structure <NUM> and AD manifold <NUM>. Similarly, via stack <NUM>, <NUM>, <NUM>, <NUM> provides a relatively robust electrical connection between electrically connects AD manifold <NUM> and output terminal <NUM> of vertically-integrated capacitor-AD structure <NUM>.

By virtue of the above-described wiring structure, AD <NUM> and MIM capacitor <NUM> are electrically coupled in parallel. During normal operation, electrical current is conducted from input terminal <NUM> to output terminal <NUM> when MIM capacitor <NUM> discharges current, while effectively zero current is passed through AD <NUM> excluding any negligible current leakage. Comparatively, during an ESD event, the breakdown voltage across AD <NUM> (and specifically in the semiconductor regions underlying the electrodes or contact fingers <NUM>, <NUM>, <NUM> of AD <NUM>) is rapidly surpassed and a low resistance electrical path opens through the AD <NUM> to allow current to flow from input terminal <NUM> to output terminal <NUM>, while bypassing MIM capacitor <NUM>. In this manner, the provision of AD <NUM> protects MIM capacitor <NUM> from over-voltage damage during any ESD events that may occur. While providing effective ESD protection, vertically-integrated capacitor-AD structure <NUM> has a relatively compact footprint due, at least in substantial part, to the three dimensional, vertically-overlapping architecture of structure <NUM>. In embodiments, the footprint of vertically-integrated capacitor-AD structure <NUM> may be approximately two-thirds or less relative to a comparable structure including a MIM capacitor and a parallel-coupled AD positioned in a side-by-side or non-overlapping relationship. Consequently, the incorporation of vertically-integrated capacitor-AD structure <NUM> into PAIC <NUM> frees additional die space that may be leveraged to increase the dimensions of other components or, instead, to allow a reduction in the planform dimension of semiconductor substrate <NUM> (the die body) for cost savings, particularly in implementations in which multiple instances of vertically-integrated capacitor-AD structure <NUM> are present.

Adoption of vertically-integrated capacitor-AD structure <NUM> into existing process flows is streamlined as standard metal deposition and patterning techniques can be employed to produce vertically-integrated capacitor-AD structure <NUM> along with the integral features or devices within metal layer system <NUM>. As a still further benefit, and in contrast to other possible architectures placing a MIM capacitor and an AD in a non-overlapping, side-by-side relationship, a relatively direct, non-tortuous current conduction path is provided through AD <NUM>. This may be appreciated by referring to <FIG> in which dashed line <NUM> represents a current conduction path extending through AD <NUM> (when the breakdown voltage is surpassed) from input terminal <NUM> (represented by a current injection point or first node <NUM>) to output terminal <NUM> (represented by a second node <NUM>). As indicated by line <NUM>, the current conduction path through AD <NUM> follows a substantially linear path, as seen looking downwardly onto vertically-integrated capacitor-AD structure <NUM> along a vertical axis orthogonal to substrate surface <NUM>. Stated differently, a straight line (line <NUM>) can be drawn between input terminal <NUM> and output terminal <NUM> (as seen looking downwardly on principal surface <NUM> of semiconductor substrate <NUM> along the vertical axis), with the straight line transecting (and perhaps bisecting) both MIM capacitor <NUM> and AD <NUM>.

There has thus been provided an embodiment of an integrated circuit (i.e., PAIC <NUM>) including at least one vertically-integrated capacitor-AD structure (i.e., vertically-integrated capacitor-AD structure <NUM>). In further implementations, vertically-integrated capacitor-AD structure <NUM> can be modified to varying extents, while continuing to provide the desired capacitance and ESD-protection functions in a highly compact footprint. For example, in embodiments, the vertically-integrated capacitor-AD structure <NUM> can contain multiple MIM capacitors and/or multiple ADs, which may be electrically interconnected in various manners. Further emphasizing this point, several additional examples of vertically-integrated capacitor-AD structures containing multiple MIM capacitors and/or multiple ADs will now be described in conjunction with <FIG>.

Advancing to <FIG>, a simplified planform view of an example vertically-integrated capacitor-AD structure <NUM> is shown. In this example, vertically-integrated capacitor-AD structure <NUM> includes a single MIM capacitor <NUM>, which extends over a neighboring (laterally-adjacent) pair of ADs <NUM>; e.g., two APDs formed over a semiconductor substrate. A dashed box <NUM> represents the vertically-overlapping portion of the capacitor plates included in MIM capacitor <NUM>. ADs <NUM> are disposed in a side-by-side relationship and separated by a lateral gap <NUM>; however, a majority, if not the substantial entirety (or entirety) of each AD <NUM> overlaps with MIM capacitor <NUM> as taken along an axis orthogonal to the upper surface of a semiconductor substrate on which vertically-integrated capacitor-AD structure <NUM> is formed. MIM capacitor <NUM> may be substantially identical to MIM capacitor <NUM> described above in connection with <FIG> and is thus not again discussed in detail to avoid redundancy. ADs <NUM> are likewise similar to, if not substantially identical to AD <NUM>, albeit with the respective widths of ADs <NUM> reduced (or the width of MIM capacitor <NUM> increased) to enable positioning of two ADs <NUM> beneath MIM capacitor <NUM> in a partially or wholly vertically-overlapping relationship as shown. Accordingly, and as was previously the case, each AD <NUM> includes a first manifold <NUM> from which a central contact finger <NUM> extends, a second manifold <NUM> from which outer contact fingers <NUM> extend, and floating contact fingers <NUM> laterally-interspersed with contact fingers <NUM>, <NUM> in an interdigitated or interspersed relationship. Once again, the features defining ADs <NUM> are defined by pattern regions of the initially-deposited or "M1" metal layer of a metal layer system <NUM> in which vertically-integrated capacitor-AD structure <NUM> is formed, the M1 metal layer contacting a principal surface of the semiconductor substrate over which metal layer system <NUM> is formed. ADs <NUM> are illustrated as substantially identical in the example of <FIG>, but may vary relative to each other in further realizations of vertically-integrated capacitor-AD structure <NUM>.

Electrically-conductive interconnect features, such as metal traces and plugs or vias, are formed in metal layer system <NUM> to electrically couple ADs <NUM> in parallel or in series between the input and output electrodes of vertically-integrated capacitor-AD structure <NUM>. <FIG> is a circuit schematic illustrating vertically-integrated capacitor-AD structure <NUM> when ADs <NUM> are electrically coupled in parallel, while <FIG> is a circuit schematic illustrating capacitor-AD structure <NUM> when ADs <NUM> are electrically coupled in series. In the circuit schematics of <FIG>, diode symbols <NUM> correspond to one of ADs <NUM> shown in <FIG>, while diode symbols <NUM> correspond to the other of ADs <NUM>. Capacitor symbol <NUM> corresponds to MIM capacitor <NUM>, while the various interconnect lines <NUM> represent the conductive features (traces or interconnect lines and conductive vias) formed in metal layer system <NUM>. Relative to the series arrangement of ADs <NUM> shown in <FIG>, the parallel arrangement of ADs <NUM> (<FIG>) may increase the reaction time of and current conduction through ADs <NUM> during an ESD event. Comparatively, relative to the parallel arrangement of ADs <NUM> shown in <FIG>, the series arrangement of ADs <NUM> (<FIG>) may provide a higher voltage threshold and lower current leakage during operation of vertically-integrated capacitor-AD structure <NUM>.

Various other vertically-integrated capacitor-AD structures are possible in still further realizations. For example, as shown in the simplified diagram of <FIG>, a vertically-integrated capacitor-AD structure <NUM> can be fabricated in the metal layer system formed over a semiconductor substrate <NUM> including dual MIM capacitors <NUM>, <NUM> and dual ADs <NUM>, <NUM>, with AD <NUM> and AD <NUM> disposed beneath (and thus vertically overlapped in their entireties by) MIM capacitors <NUM>, <NUM>, respectively. In such an embodiment, MIM capacitors <NUM>, <NUM> can be identical or may differ and thus provide differing capacitances. Similarly, ADs <NUM>, <NUM> can be similar or differ; e.g., in an embodiment in which MIM capacitor <NUM> is more susceptible to ESD damage relative to MIM capacitor <NUM>, AD <NUM> (electrically coupled in parallel with MIM capacitor <NUM>) may be configured to provide a lower breakdown voltage than AD <NUM> (electrically coupled in parallel with MIM capacitor <NUM>). In such an embodiment, ADs <NUM>, <NUM> can be electrically coupled in parallel or in series in a manner akin to that described above in connection with <FIG>. In other instances, and as indicated in <FIG>, a vertically-integrated capacitor-AD structure <NUM> can be produced in the metal layer system formed over a semiconductor substrate <NUM> including two MIM capacitors <NUM>, <NUM> and a single AD <NUM>, which is vertically overlapped by both MIM capacitors <NUM>, <NUM>. Various other implementations are also possible including any practical of MIM capacitors and ADs in a given vertically-integrated capacitor-AD structure. Additionally, in embodiments in which there exists a sufficient number of metal layers or levels, two MIM capacitors can potentially be formed in a metal layer system and likewise positioned in a stacked or vertically-overlapping relationship such that a first MIM capacitor overlies a second MIM capacitor, which then overlies one or more ADs located beneath the second MIM capacitor at an interface between the first-formed (M1) metal layer and a semiconductor substrate.

There has thus been provided PAICs and other integrated circuits including vertically-integrated capacitor-AD structures. In the above-described manner, an integrated circuit can be produced having a reduced-footprint vertically-integrated capacitor-AD structure. In addition to IC area savings, embodiments of the vertically-integrated capacitor-AD structure may also provide certain performance benefits, such as providing a more direct current conduction path through the AD element(s) of the capacitor-AD structure, reduced parasitic capacitance, low current leakage, and/or other such benefits. As a still further advantage, embodiments of the vertically-integrated capacitor-AD structure also provide design flexibility allowing different combinations of MIM capacitors and AD elements to be integrated into a given vertically-integrated capacitor-AD structure with different interconnect topologies; e.g., in embodiments in which the two AD elements are integrated into a vertically-integrated capacitor-AD structure, interconnect features may be formed to either connect the AD elements in parallel or in series for increased breakdown voltage and reduced leakage characteristics. As a still further benefits, embodiments of the vertically-integrated capacitor-AD structure can be integrated into existing manufacturing process flows and IC designs with minimal cost and design modifications. Embodiments of the integrated circuit described herein are consequently well-suited for usage within power amplifier applications in which a compact capacitance-ESD protection solution is sought including, but not limited to, massive MIMO and small cell applications. Accordingly, in embodiments, the integrated circuit may assume the form of a PAIC including a FET configured to amplify a RF signal during operation, and the vertically-integrated capacitor-AD structure may be electrically coupled to an input terminal (e.g., the gate control terminal) of the FET.

In embodiments, a PAIC or other integrated circuit includes a semiconductor substrate having a principal surface, a metal layer system, and a vertically-integrated capacitor-AD structure formed in the metal layer system. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first MIM capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis. In other embodiments, the PAIC further includes a power amplifier transistor formed on the semiconductor substrate and electrically coupled to the vertically-integrated capacitor-AD structure; e.g., the power amplifier transistor may assume the form of FET having a gate terminal, and the vertically-integrated capacitor-AD structure may be electrically coupled between the gate terminal of the FET and a gate control terminal of the integrated circuit.

In further embodiments, a PAIC includes a semiconductor substrate having an upper surface on which an input terminal is located, a metal layer system formed over the upper surface of the semiconductor substrate; a power amplifier transistor further formed on the semiconductor substrate and electrically coupled to the input terminal, and a MIM capacitor formed in the metal layer system and electrically coupled between the input terminal and the power amplifier transistor. An AD is further formed in the metal layer system, electrically coupled in parallel with the MIM capacitor, and located between the upper surface of the semiconductor substrate and the MIM capacitor along a vertical axis orthogonal to the upper surface of the semiconductor substrate. In certain implementations, the AD includes a plurality of contact fingers, which combine with the semiconductor substrate to form at least two diode elements arranged in a back-to-back configuration. Additionally or alternatively, in embodiments, the MIM capacitor may include an upper capacitor plate and a lower capacitor plate, while the metal layer system includes: (i) a first metal layer (e.g., the above-described M1 layer) in which the AD is formed; (ii) outer metal layers (e.g., the above-described M4-M5 layers) in which the upper capacitor plate and the lower capacitor plate are formed, the outer metal layers located further from the semiconductor substrate than is the first metal layer; and (iii) at least one intervening metal layer (e.g., the above-described M2-M3 layers) located between the first metal layer and the outer metal layer along the vertical axis.

Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis.

Claim 1:
An integrated circuit, comprising:
a semiconductor substrate (<NUM>) having a principal surface (<NUM>);
a metal layer system (<NUM>), comprising:
a body (<NUM>) of dielectric material; and
a plurality of patterned metal layers located in the body of dielectric material, the plurality of patterned metal layers including a first patterned metal layer contacting the principal surface of the semiconductor substrate; and
a vertically-integrated capacitor-avalanche diode, "AD", structure formed in the metal layer system, the vertically-integrated capacitor-AD structure comprising:
a first AD formed, at least in part, by patterned portions of the first patterned metal layer; and
a first metal-insulator-metal, "MIM", capacitor formed in the metal layer system and at least partially overlapping with the first AD along a vertical axis orthogonal to the principal surface of the semiconductor substrate, wherein the first MIM capacitor comprises:
an upper capacitor plate (<NUM>) and a lower capacitor plate (<NUM>) formed in different patterned metal layers included within the plurality of patterned metal layers, the lower capacitor plate located closer to the semiconductor substrate than is the upper capacitor plate along the vertical axis; and
a dielectric layer (<NUM>) separating the upper capacitor plate and lower capacitor plate, the dielectric layer having a higher dielectric constant than does the body of dielectric material,
wherein the upper capacitor plate and the lower capacitor plate are separated by a first vertical spacing (G1) along the vertical axis; and
wherein lower capacitor plate and the first AD are separated by a second vertical spacing (G<NUM>) along the vertical axis, the second vertical spacing greater than the first vertical spacing by a factor of at least two.