Patent Description:
As a MOS transistor used in a high-frequency analog signal amplifier circuit, a MOS transistor including an octagonal ring-shaped gate electrode, a drain region inside the gate electrode, and an octagonal source region outside the gate electrode has been proposed (see, for example, Patent Document <NUM>). In this MOS transistor, the resistance of a gate wire is reduced by forming the gate electrode in an octagonal shape and connecting a gate lead wire to each of two opposing sides of the gate electrode. Further, the resistance of a source wire is reduced by a plurality of contacts being placed on the source region and connected in parallel. Furthermore, a drain wire is connected to the drain region via a contact placed on the drain region. By reducing the resistance of the gate wire and the source wire, the minimum noise figure of the MOS transistor according to the conventional technique is effectively reduced.

<CIT> discloses a test field effect transistor. In <CIT>, for fabricating a test field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A dummy structure is formed on the gate electrode material, and the dummy structure is disposed over a shaped area of the gate electrode material and of the semiconductor substrate. The dummy structure has at least one sidewall around a perimeter of the shaped area. A spacer structure is formed to surround the at least one sidewall of the dummy structure outside of the perimeter of the shaped area. The dummy structure is etched away such that the shaped area of the gate electrode material is exposed and such that the spacer structure remains outside of the perimeter of the shaped area. Any exposed regions of the gate electrode material and of the gate dielectric material not under the spacer structure are etched away. The gate dielectric material remaining under the spacer structure forms a gate dielectric of the test field effect transistor, and the gate electrode material remaining under the spacer structure forms a gate electrode of the test field effect transistor. A drain and source dopant is implanted into exposed regions of the semiconductor substrate to form a first drain or source junction within the shaped area surrounded by the gate dielectric and the gate electrode, and to form a second drain or source junction outside the shaped area beyond the gate dielectric and the gate electrode. A width of the test field effect transistor is the perimeter of the shaped area, and a length of the test field effect transistor is the width of the gate dielectric and the gate electrode extending out from the perimeter of the shaped area.

In the above-mentioned conventional technique, since the drain region has a shape surrounded by the ring-shaped gate electrode, multi-layer wiring via contacts is required to connect a wire from the drain. Therefore, there is a problem that wiring length becomes long. If gate wiring and drain wiring become long, a circuit that amplifies a millimeter-wave-band signal has a problem of increased losses.

The present disclosure has been made in view of the above-mentioned problems. It is an object of the present disclosure to shorten the wiring length of MOS transistors.

By adopting such aspects, the lengths of signal lines formed by the gate wire and the drain wire made smaller in width than the central part of the source region are expected to be shortened.

Next, modes for carrying out the present disclosure (hereinafter, referred to as embodiments) will be described with reference to the drawings. In the drawings described below, the same or similar reference numerals are assigned to the same or similar parts. However, the drawings are schematic, and the dimensional ratios of individual parts and the like do not always agree with actual ones. Further, it is needless to say that the drawings include portions where each other's dimensional relationships and ratios are different between them. Furthermore, the embodiments will be described in the following order.

<FIG> is a circuit diagram showing a configuration example of an amplifier circuit according to a first embodiment of the present disclosure. The amplifier circuit <NUM> in the figure includes an input terminal <NUM>, an output terminal <NUM>, and MOS transistors <NUM> to <NUM>.

The amplifier circuit <NUM> in the figure is a circuit that amplifies a signal input to the input terminal <NUM> and outputs it to the output terminal <NUM>. The gates of the MOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are connected to the input terminal <NUM> together via an input signal line <NUM>. The sources of the MOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are connected to a grounding conductor. The drains of the MOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are connected to the output terminal <NUM> together via an output signal line <NUM>. In this way, the MOS transistors <NUM> to <NUM> are connected in parallel to amplify a signal input to their respective gates. Note that the power of the MOS transistors <NUM>, <NUM>, <NUM>, and <NUM> is supplied via the output terminal <NUM>. As will be described later, the MOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are formed on a semiconductor substrate as a single semiconductor device (semiconductor device <NUM>). Note that the amplifier circuit <NUM> is an example of an electronic circuit described in the claims.

<FIG> is a diagram showing a configuration example of the amplifier circuit according to the first embodiment of the present disclosure. The figure is a plan view showing a configuration example of the amplifier circuit <NUM>. The amplifier circuit <NUM> is formed on a semiconductor substrate <NUM>. The amplifier circuit <NUM> in the figure includes the semiconductor device <NUM>, the input signal line <NUM>, and the output signal line <NUM>.

Further, the semiconductor device <NUM> in the figure includes source regions <NUM> to <NUM>, channel regions <NUM> to <NUM>, drain regions <NUM> and <NUM>, gate electrodes <NUM>, <NUM>, and <NUM>, a gate wire <NUM>, a drain electrode <NUM>, and a drain wire <NUM>. The semiconductor device <NUM> in the figure further includes source electrodes <NUM> to <NUM> and via plugs <NUM> to <NUM>. In the figure, broken lines indicate the channel regions <NUM> to <NUM>, dotted lines indicate the gate wire <NUM> and the drain wire <NUM>, and dash-dot-dot lines indicate the via plugs <NUM> to <NUM>.

The source region <NUM> constitutes a common source of the MOS transistors <NUM> and <NUM> described in <FIG>. The source region <NUM> is formed in a horizontally elongated hexagonal shape, and has two ends (ends <NUM> and <NUM>) made smaller in width than its central part. The source region <NUM> in the figure represents an example having the ends <NUM> and <NUM> formed in a tapered shape. Furthermore, the ends <NUM> and <NUM> in the figure each represent an example formed in a tapered shape with an angle of <NUM> degrees. The source electrode <NUM> is placed adjacent to the surface of the source region <NUM>. Further, the via plug <NUM> is formed in the source region <NUM>. The via plug <NUM> extends through the semiconductor substrate <NUM> to connect the source electrode <NUM> and a source wire <NUM> (not shown) described later.

The channel region <NUM> constitutes the channel of the MOS transistor <NUM>. Further, the channel region <NUM> constitutes the channel of the MOS transistor <NUM>. The channel regions <NUM> and <NUM> are placed adjacent to the source region <NUM>, and are placed around the corresponding outer peripheral parts of the source region <NUM> divided by the ends <NUM> and <NUM>. In the semiconductor device <NUM> in the figure, the channel regions <NUM> and <NUM> are placed above and below the source region <NUM> placed in the center of the figure, respectively. Note that the channel region <NUM> is an example of a first channel region described in the claims. The channel region <NUM> is an example of a second channel region described in the claims.

The drain region <NUM> constitutes a common drain of the MOS transistors <NUM> and <NUM>. Further, the drain region <NUM> constitutes a common drain of the MOS transistors <NUM> and <NUM>. The drain regions <NUM> and <NUM> are placed adjacent to the channel regions <NUM> and <NUM>, respectively. Note that the drain region <NUM> is an example of a first drain region described in the claims. The drain region <NUM> is an example of a second drain region described in the claims.

The gate electrode <NUM> constitutes the gates of the MOS transistors <NUM> and <NUM>. The gate electrode <NUM> is placed on the surfaces of the channel regions <NUM> and <NUM> through an insulating film <NUM> (not shown). The gate electrode <NUM> in the figure represents an example placed in a shape surrounding the source region <NUM>. The gate electrode <NUM> is formed by two gate electrodes formed on the surfaces of the channel regions <NUM> and <NUM>, respectively, being joined together near the ends <NUM> and <NUM> of the source region <NUM>.

The gate wire <NUM> is a wire connected to a joint of the gate electrode <NUM>. The gate wire <NUM> in the figure is connected to the gate electrode <NUM> near the end <NUM> of the source region <NUM>. The gate wire <NUM> is connected to the input signal line <NUM> and transmits an input signal to the gate electrodes of the MOS transistors <NUM> and <NUM>. Note that the figure shows an example in which the gate electrode <NUM> and the gate wire <NUM> are coupled.

The drain electrode <NUM> is an electrode placed on the respective surfaces of the drain regions <NUM> and <NUM>. The drain electrode <NUM> is formed by electrodes formed on the surfaces of the drain regions <NUM> and <NUM>, respectively, being joined together near the end <NUM> of the source region <NUM>. Specifically, the drain electrodes on the surfaces of the drain regions <NUM> and <NUM> are joined together near the end <NUM>, which is the end on the side different from that of the end <NUM> near the connection between the gate electrode <NUM> and the gate wire <NUM>, of the ends of the source region <NUM>. Thus, the drain electrode <NUM> is formed in a shape bifurcated from the end <NUM> in two directions of the drain regions <NUM> and <NUM>. Note that the end <NUM> is an example of a first source end described in the claims. The end <NUM> is an example of a second source end described in the claims.

The drain wire <NUM> is a wire connected to a joint of the drain electrode <NUM>. The drain wire <NUM> is connected to the output signal line <NUM> and transmits a signal amplified by the MOS transistors <NUM> and <NUM>. Note that the figure shows an example in which the drain electrode <NUM> and the drain wire <NUM> are coupled.

The channel region <NUM> is placed adjacent to the drain region <NUM> and constitutes the channel of the MOS transistor <NUM>. The source region <NUM> is placed adjacent to the channel region <NUM> and constitutes the source of the MOS transistor <NUM>. The source electrode <NUM> and the via plug <NUM> are formed in the source region <NUM>. The gate electrode <NUM> is placed on the surface of the channel region <NUM> through an insulating film <NUM> (not shown) and constitutes the gate of the MOS transistor <NUM>. The gate electrode <NUM> is connected to the gate wire <NUM> near the end <NUM>. Note that the channel region <NUM> is an example of a third channel region described in the claims. The source region <NUM> is an example of a second source region described in the claims. The gate electrode <NUM> is an example of a second gate electrode described in the claims.

The channel region <NUM> is placed adjacent to the drain region <NUM> and constitutes the channel of the MOS transistor <NUM>. The source region <NUM> is placed adjacent to the channel region <NUM> and constitutes the source of the MOS transistor <NUM>. The source electrode <NUM> and the via plug <NUM> are formed in the source region <NUM>. The gate electrode <NUM> is placed on the surface of the channel region <NUM> through an insulating film and constitutes the gate of the MOS transistor <NUM>. Like the gate electrode <NUM>, the gate electrode <NUM> is connected to the gate wire <NUM> near the end <NUM>. Note that the channel region <NUM> is an example of a fourth channel region described in the claims. The source region <NUM> is an example of a third source region described in the claims. The gate electrode <NUM> is an example of a third gate electrode described in the claims.

As described above, in the semiconductor device <NUM> in the figure, the source region <NUM> is placed in the central part. The channel region <NUM>, the drain region <NUM>, the channel region <NUM>, and the source region <NUM> are placed in this order adjacent to the one-side outer peripheral part of the source region divided by the ends <NUM> and <NUM>. Further, the channel region <NUM>, the drain region <NUM>, the channel region <NUM>, and the source region <NUM> are placed in this order adjacent to the other-side outer peripheral part of the source region <NUM>. In this way, the MOS transistors <NUM> to <NUM> are formed in parallel. The gate electrodes <NUM>, <NUM>, and <NUM> are connected to the gate wire <NUM> near the end <NUM> of the source region <NUM> to be connected to the input signal line <NUM>. The drain electrode <NUM> is connected to the drain wire <NUM> near the end <NUM> of the source region <NUM> to be connected to the output signal line <NUM>.

Consequently, an input signal is distributed to the gate electrodes <NUM>, <NUM>, and <NUM> near the end <NUM>. Further, output signals transmitted by the parts of the drain electrode <NUM> bifurcated in the directions of the drain regions <NUM> and <NUM> merge near the end <NUM>. This can reduce skew in input signals and output signals in the MOS transistors <NUM> to <NUM>. Furthermore, since the input signal line <NUM> and the output signal line <NUM> are placed apart by the semiconductor device <NUM>, coupling between the input signal line <NUM> and the output signal line <NUM> can be reduced.

The source region <NUM> in the figure has the ends <NUM> and <NUM> smaller in width than the central part. The gate wire <NUM> and the drain wire <NUM> are placed near the ends <NUM> and <NUM>, respectively. The channel region <NUM>, the drain region <NUM>, and the channel region <NUM>, and the channel region <NUM>, the drain region <NUM>, and the channel region <NUM> are placed adjacent to each other along the outer periphery of the source region <NUM> having the ends made narrower. Consequently, the widths of the gate wire <NUM> and the drain wire <NUM> can be made smaller than the width of the central part of the source region <NUM>. Further, in the figure, the width of the gate wire <NUM> (B in the figure) and the width of the drain wire <NUM> (C in the figure) can be made smaller than the width of the via plug <NUM> (A in the figure).

Thus, in the semiconductor device <NUM> in the figure, the multiple gate electrodes and drain electrodes adjacent to the source region <NUM> in which the via plug <NUM> having a relatively large shape is formed are bundled to be connected to the gate wire <NUM> and the drain wire <NUM> of relatively small widths, respectively. This can shorten the respective distances between the input signal line <NUM> and the output signal line <NUM> and the gate electrodes and the drain electrodes while placing the via plug <NUM> of a relatively large size. The efficiency of the amplifier circuit <NUM> operating in a millimeter-wave band can be improved.

Note that the configuration of the semiconductor device <NUM> is not limited to this example. For example, the gate electrode <NUM> may be divided at the end <NUM>, that is, bifurcated in two directions from the end <NUM> like the drain electrode <NUM>. Further, for the source region <NUM>, one of the ends <NUM> and <NUM> may be made smaller in width than the central part.

<FIG> is a diagram showing a configuration example of a conventional amplifier circuit. The figure is a diagram showing the conventional amplifier circuit as a comparative example. A semiconductor device <NUM> in the figure includes a rectangular source region <NUM>. Gate electrodes and drain electrodes are wired at an angle of <NUM> degrees vertically and horizontally. Consequently, the widths of a gate wire <NUM> and a drain wire <NUM> are larger than the width of the source region <NUM>. The distance from an input signal line <NUM> to the gate electrodes becomes long. Similarly, the distance from the drain electrodes to an output signal line <NUM> becomes long, increasing wiring resistance. Further, impedance changes at portions bent at a <NUM>-degree angle, causing reflection. Moreover, a lot of unwanted emission is generated from <NUM>-degree corners. These factors increase losses and decrease efficiency in the conventional amplifier circuit. By contrast, in the semiconductor device <NUM> in <FIG>, wiring from the gate wire <NUM> to each gate electrode is diagonal wiring at an angle of <NUM> degrees. Wiring from each drain electrode to the drain wire <NUM> is likewise diagonal wiring at an angle of <NUM> degrees. Thus, in the semiconductor device <NUM> in <FIG>, the wiring lengths can be shortened. Furthermore, reflection and the like at corners can be reduced. Losses can be reduced.

<FIG> is a diagram showing a configuration example of a semiconductor device according to the first embodiment of the present disclosure. The figure is a diagram showing a configuration example of the semiconductor device <NUM>, and is a cross-sectional view taken along line D-D' in <FIG>. As described above, the semiconductor device <NUM> is formed on the semiconductor substrate <NUM>. The semiconductor substrate <NUM> may be made from, for example, silicon (Si). The source regions <NUM> and <NUM> and the drain region <NUM> are formed on the surface of the semiconductor substrate <NUM>. The source regions <NUM> and <NUM> and the drain region <NUM> may be formed in a conductivity type different from that of the semiconductor substrate <NUM>. For example, the semiconductor substrate <NUM> may be formed as a p-type semiconductor, and the source regions <NUM> and <NUM> and the drain region <NUM> may be formed as n-type semiconductors.

The gate electrode <NUM> is placed on the surface of the semiconductor substrate <NUM> between the source region <NUM> and the drain region <NUM> through the insulating film <NUM>. Further, the gate electrode <NUM> is placed on the surface of the semiconductor substrate <NUM> between the source region <NUM> and the drain region <NUM> through the insulating film <NUM>. The channel regions <NUM> and <NUM> are formed in the semiconductor substrate <NUM> under the gate electrodes <NUM> and <NUM>, respectively. The drain electrode <NUM> is placed on the surface of the drain region <NUM>.

The source electrode <NUM> and the via plug <NUM> and the source electrode <NUM> and the via plug <NUM> are placed in the source regions <NUM> and <NUM>, respectively. The via plugs <NUM> and <NUM> each include a conductor <NUM> and an insulating layer <NUM> insulating the conductor <NUM>. The source wire <NUM> is placed on the back surface of the semiconductor substrate <NUM>, and is connected to the source electrodes <NUM> and <NUM> by the via plugs <NUM> and <NUM>, respectively. The source wire <NUM> corresponds to the grounding conductor described in <FIG>.

<FIG> is a diagram showing a configuration example of a semiconductor device according to a first modification of the first embodiment of the present disclosure. The semiconductor device <NUM> in the figure is different from the semiconductor device <NUM> described in <FIG> in that it further includes a source region <NUM> in the central part and a gate electrode <NUM> surrounding the source region <NUM>. Channel regions <NUM> and <NUM> are placed adjacent to the source region <NUM>, in which a source electrode <NUM> and a via plug <NUM> are placed. A drain region <NUM> is placed between the channel regions <NUM> and <NUM>, and a drain electrode <NUM> is placed on the surface of the drain region <NUM>. The gate electrode <NUM> is connected to the gate wire <NUM>, and the drain electrode <NUM> is connected to the drain wire <NUM>. Note that a drain electrode <NUM> is placed on the surface of the drain region <NUM> in the figure and is connected to the drain wire <NUM>.

In this way, even in a case where the two source regions <NUM> and <NUM> are placed, the widths of the gate wire <NUM> and the drain wire <NUM> can be narrowed by making the ends of the source regions <NUM> and <NUM> narrower than the central parts.

<FIG> is a diagram showing a configuration example of a semiconductor device according to a second modification of the first embodiment of the present disclosure. The semiconductor device <NUM> in the figure is different from the semiconductor device <NUM> described in <FIG> in that the ends <NUM> and <NUM> of the source region <NUM> are formed asymmetrically. The figure shows an example of the source region <NUM> with the end <NUM> tapered at a smaller angle than the end <NUM>. Note that in the figure, the description of channel regions is omitted.

<FIG> is a diagram showing a configuration example of a semiconductor device according to a third modification of the first embodiment of the present disclosure. The semiconductor device <NUM> in the figure is different from the semiconductor device <NUM> described in <FIG> in that the outer periphery of the source region <NUM> is curved. Further, for the gate electrodes <NUM>, <NUM>, and <NUM>, the drain regions <NUM> and <NUM>, and the drain electrode <NUM> in the figure, their outer peripheries are also curved. In this case as well, the ends <NUM> and <NUM> are formed with a width smaller than the width of the central part of the source region <NUM>. Since the gate electrodes <NUM>, <NUM>, and <NUM> and the drain electrode <NUM> are formed in curved shapes, losses can be further reduced. Note that in the figure, the description of channel regions is omitted.

<FIG> is a diagram showing a configuration example of a semiconductor device according to a fourth modification of the first embodiment of the present disclosure. The semiconductor device <NUM> in the figure is different from the semiconductor device <NUM> described in <FIG> in that the ends <NUM> and <NUM> of the source region <NUM> are formed by sides. In this case as well, the ends <NUM> and <NUM> are formed with a width smaller than the width of the central part of the source region <NUM>.

As described above, in the semiconductor device <NUM> of the first embodiment of the present disclosure, both ends of the source region <NUM> are made smaller in width than the central part, and the width of at least one of the gate wire <NUM> or the drain wire <NUM> is made smaller than the width of the central part of the source region <NUM>. This can shorten the wiring length of at least one of the gates and the drains to reduce losses.

The semiconductor device <NUM> in the first embodiment described above includes four channel regions. In contrast, a semiconductor device <NUM> of a second embodiment of the present disclosure is different from that in the above-described first embodiment in that it includes two channel regions.

<FIG> is a diagram showing a configuration example of an amplifier circuit according to the second embodiment of the present disclosure. The semiconductor device <NUM> in the figure is different from the semiconductor device <NUM> described in <FIG> in that the channel regions <NUM> and <NUM>, the gate electrodes <NUM> and <NUM>, the source regions <NUM> and <NUM>, and the via plugs <NUM> and <NUM> are eliminated.

The semiconductor device <NUM> in the figure corresponds to a semiconductor device including the MOS transistors <NUM> and <NUM> corresponding to the two channel regions <NUM> and <NUM>. In the semiconductor device <NUM> in the figure as well, the widths of the gate wire <NUM> and the drain wire <NUM> can be made smaller than the width of the central part of the source region <NUM>.

<FIG> is a diagram showing a configuration example of a semiconductor device according to a modification of the second embodiment of the present disclosure. The semiconductor device <NUM> in the figure is different from the semiconductor device <NUM> described in <FIG> in that it further includes a source region <NUM> in the central part and a gate electrode <NUM> surrounding the source region <NUM>. Channel regions <NUM> and <NUM> are placed adjacent to the source region <NUM>, in which a source electrode <NUM> and a via plug <NUM> are placed. A drain region <NUM> is placed between the channel regions <NUM> and <NUM>, and a drain electrode <NUM> is placed on the surface of the drain region <NUM>. The gate electrode <NUM> is connected to the gate wire <NUM>, and the drain electrode <NUM> is connected to the drain wire <NUM>. A drain electrode <NUM> is placed on the surface of the drain region <NUM> in the figure and is connected to the drain wire <NUM>. In the semiconductor device <NUM> in the figure as well, the widths of the gate wire <NUM> and the drain wire <NUM> can be narrowed by making the ends of the source regions <NUM> and <NUM> narrower than the central parts.

The other configuration of the amplifier circuit <NUM> is similar to the configuration of the amplifier circuit <NUM> described in the first embodiment of the present disclosure, and thus will not be described.

As described above, in the semiconductor device <NUM> of the second embodiment of the present disclosure, the wiring lengths of the gates and the drains can be shortened in the semiconductor device <NUM> including the two channel regions <NUM> and <NUM>. This can reduce losses in the semiconductor device <NUM>.

The amplifier circuit <NUM> of the first embodiment described above includes four MOS transistors. In contrast, an amplifier circuit <NUM> of a third embodiment of the present disclosure is different from that of the above-described first embodiment in that it includes eight MOS transistors.

<FIG> is a circuit diagram showing a configuration example of an amplifier circuit according to the third embodiment of the present disclosure. The amplifier circuit <NUM> in the figure is different from the amplifier circuit <NUM> described in <FIG> in that it further includes a semiconductor device <NUM> (MOS transistors <NUM> to <NUM>) and further includes capacitors <NUM> and <NUM> as circuit elements. The gates of the MOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are connected to the input signal line <NUM> together. The sources of the MOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are connected to the grounding conductor. The drains of the MOS transistors <NUM>, <NUM>, <NUM>, and <NUM> are connected to the output signal line <NUM> together. The capacitor <NUM> is connected between the input signal line <NUM> and the grounding conductor, and the capacitor <NUM> is connected between the output signal line <NUM> and the grounding conductor. The other connections are similar to those in <FIG>, and thus will not be described.

As shown in the figure, the MOS transistors <NUM> to <NUM> are connected in parallel to amplify a signal input to their respective gates. Furthermore, the capacitors <NUM> and <NUM> are capacitors for impedance matching. The MOS transistors <NUM> to <NUM> constitute the semiconductor device <NUM>.

<FIG> is a diagram showing a configuration example of semiconductor devices according to the third embodiment of the present disclosure. The figure is a diagram showing the configuration of the semiconductor devices <NUM> and <NUM>. The semiconductor device <NUM> includes source regions <NUM>, <NUM>, and <NUM>, channel regions <NUM> to <NUM>, drain regions <NUM> and <NUM>, gate electrodes <NUM>, <NUM>, and <NUM>, a gate wire <NUM>, and a drain electrode <NUM>. Furthermore, the semiconductor device <NUM> further includes a drain wire <NUM>, source electrodes <NUM>, <NUM>, and <NUM>, and via plugs <NUM>, <NUM>, and <NUM>.

Note that the source region <NUM> is shared between the semiconductor devices <NUM> and <NUM>. Specifically, the source region <NUM> is placed adjacent to the channel region <NUM> of the semiconductor device <NUM> and the channel region <NUM> of the semiconductor device <NUM>, and constitutes a common source region in the MOS transistors <NUM> and <NUM> corresponding to the respective channel regions. Consequently, the occupied area on the semiconductor substrate can be reduced as compared with a case where two semiconductor devices are placed separately.

Furthermore, the source electrode <NUM> in the figure is formed in a shape having an added rectangular pattern extended to the ends of the source region <NUM>. This is to connect the capacitors <NUM> and <NUM> at the ends of the source region <NUM>. The gate wires <NUM> and <NUM> are connected to the input signal line <NUM> together. Similarly, the drain wires <NUM> and <NUM> are connected to the output signal line <NUM> together.

Note that the channel regions <NUM> and <NUM> in the figure are an example of a fifth channel region described in the claims. The gate electrodes <NUM> and <NUM> in the figure are an example of a fourth gate electrode described in the claims. The source region <NUM> in the figure is an example of a common source region described in the claims. The source electrode <NUM> is an example of a source electrode described in the claims.

<FIG> is a diagram showing a configuration example of the amplifier circuit according to the third embodiment of the present disclosure. The amplifier circuit <NUM> in the figure is a circuit formed using the semiconductor devices <NUM> and <NUM> described in <FIG>.

The capacitor <NUM> is placed between the gate wires <NUM> and <NUM> and the input signal line <NUM>, and is connected between a portion of the input signal line <NUM> bifurcated to the gate wires <NUM> and <NUM> and the source electrode <NUM>. The capacitor <NUM> is placed between the drain wires <NUM> and <NUM> and the output signal line <NUM>, and is connected between a portion of the output signal line <NUM> bifurcated to the drain wires <NUM> and <NUM> and the source electrode <NUM>. The capacitor <NUM> needs to be placed at a specified distance from the gate electrodes <NUM> and <NUM> and the gate wires <NUM> and <NUM>. This is to reduce electromagnetic coupling with signal wiring. For a similar reason, the capacitor <NUM> is also placed at a specified distance from the gate electrodes <NUM> and <NUM> and the drain wires <NUM> and <NUM>.

Since the ends of the source regions <NUM> and <NUM> are made smaller in width than the central parts in the semiconductor devices <NUM> and <NUM> in the figure, the widths of the gate wires <NUM> and <NUM> and the drain wires <NUM> and <NUM> can be narrowed. Furthermore, the gate electrodes <NUM> and <NUM> can be placed obliquely toward the gate wires <NUM> and <NUM>. The drain electrodes <NUM> and <NUM> can also be placed obliquely toward the drain wires <NUM> and <NUM>. Consequently, relatively large spaces can be provided near the ends of the semiconductor devices <NUM> and <NUM>. By placing the capacitors <NUM> and <NUM> in the spaces, the amplifier circuit <NUM> can be miniaturized while ensuring the above-mentioned distances.

<FIG> is a diagram showing a configuration example of a conventional amplifier circuit. The figure is a diagram shown as a comparative example, and is a diagram showing an amplifier circuit <NUM> using semiconductor devices described in <FIG>. In the semiconductor device <NUM> in the figure, the gate wire <NUM> and the drain wire <NUM> are formed with substantially the same width as the width of the semiconductor device <NUM>. Similarly, in a semiconductor device <NUM>, a gate wire <NUM> and a drain wire <NUM> are formed with substantially the same width as the width of the semiconductor device <NUM>. Consequently, a specified distance from the gate wire <NUM> and others cannot be provided, and capacitors <NUM> and <NUM> cannot be placed near the source region <NUM>. Additional source regions <NUM> and <NUM> are placed to connect the capacitors <NUM> and <NUM>, respectively, increasing the wiring lengths of the input signal line <NUM> and the output signal line <NUM>. Furthermore, the area occupied by the amplifier circuit <NUM> increases.

Note that the configuration of the amplifier circuit <NUM> is not limited to this example. For example, in place of the capacitors <NUM> and <NUM>, which are circuit elements, other impedance elements may be used. Here, the impedance elements correspond to, for example, resistors, capacitors, inductors, or composite elements of them.

As described above, in the amplifier circuit <NUM> of the third embodiment of the present disclosure, spaces in which to place circuit elements can be provided near the semiconductor devices <NUM> and <NUM> by making the ends of the source regions <NUM> and <NUM> of the semiconductor devices <NUM> and <NUM> narrower than the central parts. This allows the amplifier circuit <NUM> to be miniaturized.

The amplifier circuit <NUM> of the third embodiment described above uses the capacitors <NUM> and <NUM> as circuit elements. In contrast, an amplifier circuit <NUM> of a fourth embodiment of the present disclosure is different from that of the above-described third embodiment in that short stubs are used as circuit elements.

<FIG> is a circuit diagram showing an example of an amplifier circuit according to the fourth embodiment of the present disclosure. The amplifier circuit <NUM> in the figure is different from the amplifier circuit <NUM> described in <FIG> in that it includes short stubs <NUM> and <NUM> instead of the capacitors <NUM> and <NUM>. Here, the short stubs are short-circuited distributed constant circuits. The short stubs <NUM> and <NUM> in the figure are formed by wires making short-circuits between the input signal line <NUM> and the output signal line <NUM> and the source electrode <NUM>.

The other configuration of the amplifier circuit <NUM> is similar to the configuration of the amplifier circuit <NUM> described in the third embodiment of the present disclosure, and thus will not be described.

As described above, the amplifier circuit <NUM> of the fourth embodiment of the present disclosure allows miniaturization of the amplifier circuit <NUM> in which the short stubs <NUM> and <NUM> are placed.

The amplifier circuit <NUM> of the third embodiment described above includes the two semiconductor devices <NUM> and <NUM>. In contrast, an amplifier circuit <NUM> of a fifth embodiment of the present disclosure is different from that of the above-described third embodiment in that it includes four semiconductor devices.

<FIG> is a circuit diagram showing a configuration example of an amplifier circuit according to the fifth embodiment of the present disclosure. The amplifier circuit <NUM> in the figure is different from the amplifier circuit <NUM> described in <FIG> in that it further includes semiconductor devices <NUM> and <NUM> and capacitors <NUM> to <NUM>. The gates and drains of MOS transistors included in the semiconductor devices <NUM> and <NUM> are connected to the input signal line <NUM> and the output signal line <NUM> together, respectively. The sources of the MOS transistors included in the semiconductor devices <NUM> and <NUM> are connected to the grounding conductor. The capacitors <NUM> and <NUM> are wired between the input signal line <NUM> and the grounding conductor. The capacitors <NUM> and <NUM> are wired between the output signal line <NUM> and the grounding conductor. The other connections are similar to those in <FIG>, and thus will not be described.

As shown in the figure, the MOS transistors included in the semiconductor devices <NUM> to <NUM> are connected in parallel to amplify a signal input to their respective gates. Furthermore, the capacitors <NUM> to <NUM> are capacitors for impedance matching.

<FIG> is a diagram showing a configuration example of the amplifier circuit according to the fifth embodiment of the present disclosure. As shown in the figure, the semiconductor devices <NUM> to <NUM> are placed adjacently in this order. The input signal line <NUM> is bifurcated twice from the input terminal to be connected to the gate wires of the semiconductor devices <NUM> to <NUM>. Similarly, the output signal line <NUM> is bifurcated twice from the output terminal to be connected to the drain wires of the semiconductor devices <NUM> to <NUM>. The capacitors <NUM> and <NUM> are placed near the semiconductor devices <NUM> and <NUM>. The capacitor <NUM> is placed between the semiconductor devices <NUM> and <NUM> and the input signal line <NUM>. The capacitor <NUM> is placed between the semiconductor devices <NUM> and <NUM> and the output signal line <NUM>.

As described above, in the amplifier circuit <NUM> of the fifth embodiment of the present disclosure, spaces in which to place circuit elements can be provided near the semiconductor devices <NUM> to <NUM> by making the ends of the source regions of the semiconductor devices <NUM> to <NUM> narrower than the central parts. This allows the amplifier circuit <NUM> to be miniaturized.

The amplifier circuit <NUM> of the first embodiment described above uses MOS transistors made from Si. In contrast, an amplifier circuit <NUM> of a sixth embodiment of the present disclosure is different from that of the above-described first embodiment in that it uses MOS transistors made from gallium nitride (GaN).

<FIG> is a diagram showing a configuration example of a semiconductor device according to the sixth embodiment of the present disclosure. Similar to <FIG>, the figure is a cross-sectional view showing a configuration example of a semiconductor device <NUM>. The semiconductor device <NUM> in the figure is different from the semiconductor device <NUM> described in <FIG> in that it uses a semiconductor substrate <NUM> made from GaN.

The semiconductor substrate <NUM> in the figure includes a Si substrate <NUM>, a buffer layer <NUM>, a GaN layer <NUM>, and a channel layer <NUM> stacked on top of each other in this order. A semiconductor layer made from a mixed crystal of aluminum nitride (AlN) and GaN may be used as the channel layer <NUM>. The insulating films <NUM> and <NUM> are placed adjacent to the channel layer <NUM>, on which the gate electrodes <NUM> and <NUM> are placed in layers, respectively.

The source regions <NUM> and <NUM> are formed in the channel layer <NUM>. Specifically, source electrodes <NUM> and <NUM> are placed adjacent to the channel layer <NUM>. The channel layer <NUM> immediately below the source electrodes <NUM> and <NUM> is used as the source regions <NUM> and <NUM>. The via plugs <NUM> and <NUM> are formed between the source electrodes <NUM> and <NUM> and the source wire <NUM>.

As described above, the amplifier circuit <NUM> of the sixth embodiment of the present disclosure allows miniaturization of the amplifier circuit <NUM> even in a case of using a semiconductor device made from GaN.

Claim 1:
A semiconductor device (<NUM>) comprising:
a source region (<NUM>) placed on a semiconductor substrate (<NUM>) and having both ends (<NUM>, <NUM>) made smaller in width than a central part in a plan view;
a first channel region (<NUM>) and a second channel region (<NUM>) placed adjacent to corresponding outer peripheral parts of the source region divided, in the plan view, by the both ends on the semiconductor substrate;
a first drain region (<NUM>) and a second drain region (<NUM>) placed, in the plan view, adjacent to the first channel region and the second channel region, respectively, on the semiconductor substrate;
gate electrodes (<NUM>) placed on respective surfaces of the first channel region and the second channel region through an insulating film and joined to each other near a first source end that is one of the ends of the source region;
a gate wire (<NUM>) for transmitting an input signal to the gate electrodes connected to a portion where the gate electrodes are joined;
drain electrodes (<NUM>) placed on respective surfaces of the first drain region and the second drain region and joined to each other near a second source end that is another of the ends of the source region different from the first source end; and
a drain wire (<NUM>) for transmitting an output signal from the drain electrodes connected to a portion where the drain electrodes are joined,
wherein, in the plan view, at least one of the gate wire or the drain wire is made smaller in width than the central part of the source region; wherein the semiconductor device further comprises:
a third channel region (<NUM>) placed, in the plan view, adjacent to the first drain region;
a second source region (<NUM>) placed, in the plan view, adjacent to the third channel region;
a second gate electrode (<NUM>) placed on a surface of the third channel region through an insulating film and connected to the gate wire;
a fourth channel region (<NUM>) placed, in the plan view, adjacent to the second drain region;
a third source region (<NUM>) placed, in the plan view, adjacent to the fourth channel region; and
a third gate electrode (<NUM>) placed on a surface of the fourth channel region through an insulating film and connected to the gate wire.