Patent Description:
The present invention relates to split-gate non-volatile memory cells, and more particularly to a method of forming such cells.

<CIT> discloses a method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.

<CIT> discloses a method for making a semiconductor memory device, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.

Split-gate type memory cell arrays are known. For example, <CIT>, discloses a split gate memory cell and its formation, which includes forming source and drain regions in the substrate with a channel region there between. A floating gate is disposed over and controls the conductivity of one portion of the channel region, and a control gate is disposed over and controls the conductivity of the other portion of the channel region. The control gate extends up and over the floating gate. The insulation between the floating gate and the control gate is referred to as the tunnel dielectric material (e.g. oxide), because electrons tunnel through this dielectric material during the erase operation.

It is also known to form high voltage logic devices on the same wafer (substrate) as the split-gate memory cell array. <FIG> show the steps in forming high voltage logic devices (e.g. <NUM> volt logic devices) on the same wafer as the split gate memory cells according to a conventional method. A silicon semiconductor substrate <NUM> having an upper surface 10a, a memory cell region <NUM> and a logic region <NUM>. Semiconductor substrate <NUM> is masked, i.e. photo resist is deposited, selectively exposed using a mask, and selectively removed, using a photolithographic process, leaving portions of the underlying material covered by remaining photo resist while leaving other portions of the underlying material (here the silicon semiconductor substrate <NUM>) exposed. The exposed substrate portions are etched away leaving trenches that are then filled with dielectric material <NUM> (e.g. oxide) to form isolation regions in the logic region <NUM> of the wafer, as shown in <FIG> (after photoresist removal). Isolation regions <NUM> may be similarly formed in memory cell region <NUM> of the wafer.

A dielectric material (e.g. silicon dioxide) (hereinafter referred to as oxide) <NUM> is formed on the substrate <NUM>, a layer of polysilicon (hereinafter referred to as poly) <NUM> is formed on oxide layer <NUM>, and a layer of silicon nitride (hereinafter referred to as nitride) <NUM> is formed on poly layer <NUM>, as shown in <FIG>. The wafer is masked with photoresist, and the nitride layer <NUM> selectively etched through openings in the photoresist in the memory cell region <NUM>, to expose portions of the underlying poly layer <NUM>. The exposed portions of the poly layer <NUM> are oxidized using an oxidation process, forming oxide areas <NUM> on the poly layer <NUM>, as shown in <FIG> (after photoresist removal).

A nitride etch is used to remove the remaining nitride layer <NUM>. An anisotropic poly etch is used to remove exposed portions of the poly layer <NUM>, leaving blocks 20a of poly layer <NUM> underneath the oxide areas <NUM> in the memory cell region <NUM> (poly blocks 20a will constitute the floating gates of the memory cells), as shown in <FIG>. An oxide etch is used to remove the exposed portions of oxide layer <NUM> (i.e., those portions not under the remaining portion of poly layer <NUM>). An oxide layer <NUM> is then formed over the structure either by deposition (which also thickens oxide areas <NUM>) and/or by oxidation (which has no effect on oxide areas <NUM>). A poly layer is then formed on the structure (i.e., on oxide layer <NUM> and oxide areas <NUM>). The poly layer is then patterned by forming and patterning photoresist on the poly layer leaving portions of the poly layer exposed. The exposed portions of poly layer are selectively removed by poly etch, leaving poly blocks 28a in the memory cell region and poly blocks 28b in the logic region, as shown in <FIG> (after photoresist removal). Insulation spacers <NUM> are formed on the sides of poly blocks 28a and 28b by insulation material deposition and anisotropic etch, and implantations are performed to form source regions <NUM> and drain regions <NUM> in the memory cell region <NUM>, and source regions <NUM> and drain regions <NUM> in the logic region <NUM>, of substrate <NUM>. The final structure is shown in <FIG>.

The above technique produces non-volatile memory cells (each a floating gate 20a formed from the remaining portion of poly layer <NUM>, a control gate in the form of poly block 28a, a source <NUM> adjacent an end of the floating gate 20a, and a drain <NUM> adjacent an end of the control gate 28a) on the same substrate <NUM> as high voltage logic devices (each with a logic gate in the form of poly block 28b, source <NUM> and drain <NUM> adjacent first and second ends of the logic gate). There are many advantages of this technique. First, the same poly layer is used to form both control gates 28a of the memory cells and the logic gates 28b of the logic devices, using a single poly deposition. Second, the same oxide layer <NUM> is used as the gate oxide for the logic devices (i.e., the oxide layer used to insulate the logic gates 28b from the substrate <NUM>), the word line oxide for the memory cells (i.e., the oxide layer used to insulate the control gates 28a from the substrate <NUM>), and the tunnel oxide for the memory cells (i.e., the oxide insulating the floating gate 20a from the control gate 28a through which electrons tunnel in the erase operation). Common manufacturing steps for forming elements in both the memory cell region <NUM> and the logic region <NUM> simplifies, expedites and lower the costs of manufacturing. Forming oxide areas <NUM> by oxidation results in the floating gates 20a having a concave upper surface that terminates in a sharp edge 20b facing the control gate 28a, which enhances tunneling performance and efficiency during erase (i.e., erase operation includes placing a high voltage on the control gate 28a to cause electrons to tunnel from the sharp edge 20b of the floating gate 20a, through oxide layer <NUM>, and to control gate). The control gate has a lower portion vertically over and insulated from the substrate <NUM> for controlling the conductivity of the channel region therein, and a second portion that extends up and over the floating gate 20a for voltage coupling and proximity to the floating gate sharp edge 20b for erasure.

One drawback of the above described technique is that the thickness of oxide layer <NUM> must be compatible for both the logic devices and the memory cells. Specifically, the oxide layer <NUM> must be thick enough for the high voltage operation of the logic device, provide desired performance for the control gate 28a, while being thin enough to allow tunneling from the floating gate 20a to the control gate 28a during an erase operation. Therefore, balancing these considerations, there is a lower limit to the thickness of oxide layer <NUM> driven by the high voltage operation of the logic device, which means the tunnel oxide in the memory cells is unnecessarily thick and therefore limits erase performance and efficiency, and limits endurance performance. However, forming the tunneling oxide separately from the word line oxide and the logic gate oxide can significantly increase manufacturing complexity, time and costs.

It would be desirable to increase memory cell erase efficiency between the floating gate and the control gate, without adversely affecting the performance of the control gate as a word line or of the logic gate in the logic device, where the same oxide layer is used in all three places.

The aforementioned problems and needs are addressed by a method of forming a memory device that includes providing a semiconductor substrate with a substrate upper surface having a memory cell region and a logic region, forming a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface, wherein the floating gate includes an upper surface that terminates in an edge, forming an oxide layer having a first portion that extends along the logic region of the substrate upper surface, a second portion that extends along the memory cell region of the substrate upper surface, and a third portion that extends along the edge of the floating gate, forming a non-conformal layer having a first portion that covers the oxide layer first portion, a second portion that covers the oxide layer second portion, and a third portion that covers the oxide layer third portion, wherein the third portion of the non-conformal layer has a thickness that is less than a thickness of the first and second portions of the non-conformal layer, performing an etch that removes the third portion of the non-conformal layer, and thins but does not entirely remove the first and second portions of the non-conformal layer, performing an oxide etch that reduces a thickness of the third portion of the oxide layer, wherein the first and second portions of the oxide layer are protected from the oxide etch by the first and second portions of the non-conformal layer, removing the first and second portions of the non-conformal layer, forming a control gate having a first portion on the second portion of the oxide layer and a second portion that extends up and over the floating gate, wherein the control gate is insulated from the edge of the floating gate by the third portion of the oxide layer having the reduced thickness, and forming a logic gate on the first portion of the oxide layer; wherein the forming of the control gate and the forming of the logic gate comprise: forming a polysilicon layer on the first, second and third portions of the oxide layer; selectively removing portions of the polysilicon layer leaving a first portion of the polysilicon layer as the formed control gate and leaving a second portion of the polysilicon layer as the formed logic gate.

A method of forming a memory device includes providing a semiconductor substrate with a substrate upper surface having a memory cell region and a logic region, forming a floating gate disposed vertically over and insulated from the memory cell region of the substrate upper surface, wherein the floating gate includes an upper surface that terminates in an edge, forming a first oxide layer having a first portion that extends along the logic region of the substrate upper surface, a second portion that extends along the memory cell region of the substrate upper surface, and a third portion that extends along the edge of the floating gate, forming a non-conformal layer having a first portion that covers the first portion of the first oxide layer, a second portion that covers the second portion of the first oxide layer, and a third portion that covers the third portion of the first oxide layer, wherein the third portion of the non-conformal layer has a thickness that is less than a thickness of the first and second portions of the non-conformal layer, performing an etch that removes the third portion of the non-conformal layer, and thins but does not entirely remove the first and second portions of the non-conformal layer, performing an oxide etch that removes the third portion of the first oxide layer, wherein the first and second portions of the first oxide layer are protected from the oxide etch by the first and second portions of the non-conformal layer, forming a second oxide layer that extends along the edge of the floating gate, wherein the second oxide layer has a thickness that is less than a thickness of the first oxide layer, removing the first and second portions of the non-conformal layer, forming a control gate having a first portion on the second portion of the first oxide layer and a second portion that extends up and over the floating gate, wherein the control gate is insulated from the edge of the floating gate by the second oxide layer, and forming a logic gate on the first portion of the first oxide layer; wherein the forming of the control gate and the forming of the logic gate comprise: forming a polysilicon layer on the first, second and third portions of the oxide layer; selectively removing portions of the polysilicon layer leaving a first portion of the polysilicon layer as the formed control gate and leaving a second portion of the polysilicon layer as the formed logic gate.

Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

The present invention is a technique of forming memory cells and logic devices on a common substrate, where the oxide layer used as a tunnel oxide and word line oxide for the memory cells and the gate oxide for the logic devices is thinned in the memory cell region as it passes between the floating gate and the control gate.

<FIG> disclose the steps of the method of the present invention. The process begins using the same steps described above with respect to <FIG>. Starting with the structure in <FIG>, an oxide etch is used to remove the exposed portions of oxide layer <NUM> (i.e., those portions not under floating gate 20a. An oxide layer <NUM> is then formed over the structure either by deposition (which also thickens oxide areas <NUM>) and/or by oxidation (which has no effect on oxide areas <NUM>) as shown in <FIG>. Oxide layer <NUM> can be considered to have three portions: a first portion 26a that extends along the logic region of the substrate upper surface, a second portion 26b that extends along the memory cell region of the substrate upper surface, and a third portion 26c that extends along the sides and sharp edges 20b of the floating gate. However, before polysilicon is deposited over oxide layer <NUM>, the oxide layer <NUM> is selectively thinned adjacent the floating gates 20a in the following manner. A non-conformal layer <NUM> is formed on the structure (i.e., on oxide layer <NUM> and oxide areas <NUM>), where the non-conformal layer <NUM> has a target thickness T (e.g., <NUM>-<NUM>Å) in planar regions of oxide layer <NUM>, but a smaller thickness in non-planar regions of the underlying structure (i.e., those regions extending along raised structures such as oxide areas <NUM> and floating gates 20a), as shown in <FIG>. To achieve such a varying thickness, a flowable material is preferably used to form non-conformal layer <NUM>. One non-limiting exemplary material for non-conformal layer <NUM> is a BARC material (bottom anti-reflectant coating), which is commonly used to reduce reflectivity at resist interfaces during photolithography. BARC materials are flowable and wettable, and are easily etched and removed with minimal process damage due their high selectivity relative to oxide. Other materials that can be used for non-conformal layer <NUM> include photoresist or silicon-on-glass (SOG).

Non-conformal layer <NUM> is formed so that the portions of non-conformal layer <NUM> over the tunnel oxide portions (i.e., the portions of oxide layer 26c and oxide areas <NUM> around the sharp edges 20b of floating gates 20a) is thin relative to other (e.g., planar) portions of layer <NUM>. Thereafter, a partial etch of non-conformal layer <NUM> is performed, to expose the tunnel oxide portions, but the etch is stopped before the planar portions of layer <NUM> are exposed, as shown in <FIG>. An optional photoresist layer can be formed in the logic region <NUM> but removed from the memory cell region <NUM> before the partial etch of layer <NUM>, to provide additional protection of the non-conformal layer <NUM> from this etch for increased process margin, if non-conformal layer <NUM> is not formed of photoresist. An oxide etch is then performed on the exposed portions of oxide <NUM>/<NUM> to reduce the thickness of layer <NUM> (i.e., layer portion 26c) and oxide area <NUM> adjacent the sharp edges 20b of floating gates 20a, resulting in a thinned oxide layer 26d that will serve as the tunnel oxide for the memory cell, as shown in <FIG>. Non-conformal layer <NUM> protects the planar portions of layer <NUM> from this oxide etch, including those portions that will be under the to be formed logic gates and control gates.

An etch is then performed to remove the remaining portions layer <NUM>. A poly layer deposition and patterning as described above with respect to <FIG> is performed to form the control gates formed from poly blocks 28a and logic gates formed from poly blocks 28b, as shown in <FIG>. Control gates 28a are spaced from the floating gate sharp edges 20b by the thinned oxide layer 26d. The remaining steps described above with respect to <FIG> are performed to result in the final structure shown in <FIG>. Preferably a single implantation is used to simultaneously form the drain regions <NUM> in the memory cell region <NUM>, and source regions <NUM> and drain regions <NUM> in the logic region <NUM>. The resulting structure has logic gates 28b and control gates 28a insulated from the substrate <NUM> by oxide layer <NUM> having a first thickness, and control gates 28a insulated from the sharp edges 20b of floating gates 20a by the thinned portions 26d having a second thickness less than the first thickness. This structure enhances the erase efficiency and performance of the memory cell, without compromising the performance of the logic devices or adversely affecting the ability of the control gates 28a to control the conductivity of the channel region portion of the substrate underneath the control gates 28a.

<FIG> illustrate an alternate embodiment, which starts with the structure of <FIG>. However, instead of performing an oxide etch to thin oxide layer portion 26c at the floating gate sharp edges 20b, the etch is performed to remove oxide layer portion 26c entirely, exposing the sharp edges 20b of the floating gates 20a, as shown in <FIG>. Then, a new oxide layer <NUM> is formed on the exposed sharp edges 20b by oxide deposition and/or oxidation. The remaining processing steps described above with respect to <FIG> and <FIG> are performed to result in the final structure of <FIG>. The new oxide layer <NUM> serves as the tunnel oxide layer for the memory cells. With this embodiment, a thinned tunnel oxide is achieved by removing the originally formed oxide on the floating gate sharp edge 20b and replacing it with a new, thinner oxide layer whose thickness is less than the original oxide thickness and can be selected without any compromise or consideration of other areas of the device being formed.

It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed.

Claim 1:
A method of forming a memory device, comprising:
providing a semiconductor substrate (<NUM>) with a substrate upper surface (10a) having a memory cell region (<NUM>) and a logic region (<NUM>);
forming a floating gate (20a) disposed vertically over and insulated from the memory cell region of the substrate upper surface, wherein the floating gate includes an upper surface that terminates in an edge (20b);
forming an oxide layer (<NUM>) having a first portion (26a) that extends along the logic region of the substrate upper surface, a second portion (26b) that extends along the memory cell region of the substrate upper surface, and a third portion (26c) that extends along the edge of the floating gate;
forming a non-conformal layer (<NUM>) having a first portion that covers the oxide layer first portion, a second portion that covers the oxide layer second portion, and a third portion that covers the oxide layer third portion, wherein the third portion of the non-conformal layer has a thickness that is less than a thickness of the first and second portions of the non-conformal layer;
performing an etch that removes the third portion of the non-conformal layer, and thins but does not entirely remove the first and second portions of the non-conformal layer;
performing an oxide etch that reduces a thickness of the third portion of the oxide layer, wherein the first and second portions of the oxide layer are protected from the oxide etch by the first and second portions of the non-conformal layer;
removing the first and second portions of the non-conformal layer;
forming a control gate (28a) having a first portion on the second portion of the oxide layer and a second portion that extends up and over the floating gate, wherein the control gate is insulated from the edge of the floating gate by the third portion of the oxide layer having the reduced thickness; and
forming a logic gate (28b) on the first portion of the oxide layer;
wherein the forming of the control gate and the forming of the logic gate comprise:
forming a polysilicon layer on the first, second and third portions of the oxide layer;
selectively removing portions of the polysilicon layer leaving a first portion of the polysilicon layer as the formed control gate and leaving a second portion of the polysilicon layer as the formed logic gate.