Patent Description:
In the past, ranging methods called time of flight (ToF) have been known with regard to electronic devices having ranging functions. The ToF is a method of measuring a distance by causing the electronic device to emit irradiation light to an object, and calculating a round-trip time between the emission of the irradiation light and return of reflected irradiation light to the electronic device. In many cases, a single-photon avalanche diode (SPAD) is used as a photoelectric conversion element when detecting the reflected light corresponding to the irradiation light. However, when using the SPAD, sometimes excess bias varies depending on temperature. The excess bias is a value obtained by subtracting breakdown voltage from voltage between an anode and a cathode. Therefore, there are a possibility that the excess bias becomes too small and sensitivity of a photodiode decreases, and a possibility that the excess bias becomes too large in reverse and dark-current noise increases. Accordingly, there have been provided solid state image sensors that monitor cathode electric potentials of the SPADs when photocurrent flows and reduce anode electric potentials of the SPADs as the cathode electric potentials get higher.

<CIT> describes a photodetecting circuit using an avalanche photodiode including an avalanche photodiode, and a bias control means for applying a bias voltage to the avalanche photodiode to drive the avalanche photodiode at a high multiplication factor. The bias control means has a diode having the same temperature dependence of a breakdown voltage as that of the avalanche photodiode, and a control circuit for applying positive and negative potentials with respect to the ground potential between the anode and the cathode of the diode such that the diode is set in a breakdown state at a predetermined current. A positive or negative potential is applied from one of the anode and the cathode of the avalanche photodiode as a bias voltage, and a photocurrent is output from the other terminal of the avalanche photodiode.

<CIT> describes a light receiver comprising a plurality of avalanche photodiode elements, a first terminal and a second terminal for supplying a bias voltage so that the avalanche photodiode elements are biased with a bias voltage above a breakdown voltage and thus operated in a Geiger mode, at least one temperature measuring element for measuring an operating temperature of the avalanche photodiode elements and a voltage compensation unit for adapting the bias voltage to the operating temperature.

<CIT> is related to the detection of light using an APD that has high gain and/or a wide range of operating temperature. A first APD is biased with a voltage bias that is controlled based on the breakdown voltage of a second APD, which is thermally coupled with the first APD. Changes in the breakdown voltage of the second APD due to aging, temperature chances, and the like, are reflective of changes in the breakdown voltage of the first APD. As a result, the first APD can be operated with greater stability and reliability at high gain and over larger temperature excursions than APDs known in the prior art.

The above-listed related technology controls the anode electric potentials to suppress variation in the excess bias caused by change in the temperature. However, monitor voltage (cathode voltage) for controlling the anode electric potentials follows the variation in the excess bias caused by the temperature, and the monitor voltage also varies depending on decrease or increase in an amount of incident light. Although the above-described solid state image sensor makes it possible to suppress variation in the excess bias caused by change in temperature, such a solid state image sensor has a problem of variation in the excess bias caused by variation in the monitor voltage depending on decrease or increase in an amount of incident light.

It is desirable to suppress variation in the excess bias depending on decrease or increase in an amount of incident light by using a solid state image sensor that controls one of an anode electric potential and a cathode electric potential of a photoelectric conversion element on the basis of another of the anode electric potential and the cathode electric potential.

According to a first embodiment of the present technology, there is provided a light detecting device according to claim <NUM>.

This makes it possible to suppress variation in excess bias.

The monitor pixel detects a timing at which a predetermined period of time has elapsed since decrease in a cathode electric potential, and captures and holds the cathode electric potential at that timing. This makes it possible to hold the electric potential without depending on an amount of light. It is possible to suppress variation in bias voltage resulting from decrease or increase in the amount of light, when the control section controls an anode electric potential in response to the holding potential.

Embodiments for implementing the present technology (hereinafter, referred to as embodiments) will be described below. The description will be given in the following order.

<FIG> is a block diagram illustrating a configuration example of a ranging module <NUM> according to a first embodiment of the present technology. The ranging module <NUM> is configured to measure a distance to an object. The ranging module <NUM> includes a light emission section <NUM>, a synchronization control section <NUM>, and a solid state image sensor (or light detecting device) <NUM>. The ranging module <NUM> is installed in a smartphone, a personal computer, vehicle-mounted equipment, or the like, and is used for measuring a distance.

The synchronization control section <NUM> operates the light emission section <NUM> and the solid state image sensor <NUM> in synchronization with each other. The synchronization control section <NUM> supplies a clock signal of predetermined frequency (such as <NUM> to <NUM>) as a synchronization signal CLKp to the light emission section <NUM> and the solid state image sensor <NUM> via signal lines <NUM> and <NUM>.

The light emission section <NUM> supplies intermittent light as irradiation light in synchronization with the synchronization signal CLKp from the synchronization control section <NUM>. For example, near-infrared light is used as the irradiation light.

The solid state image sensor <NUM> is configured to receive reflected light of the irradiation light and measures a round-trip time between a light emission timing indicated by the synchronization signal CLKp and a light reception timing of the reflected light. The solid state image sensor <NUM> calculates a distance to an object from the round-trip time, generates distance data indicating the distance, and outputs the distance data.

Note that, although the light emission section <NUM>, the solid state image sensor <NUM>, and the synchronization control section <NUM> are installed in the same ranging module <NUM>, it is also possible to install them in different apparatuses. A system including the light emission section <NUM>, the solid state image sensor <NUM>, and the synchronization control section <NUM> is an example of a ranging system according to an embodiment of the present technology.

<FIG> is a diagram illustrating an example of a stacking structure of the solid state image sensor <NUM> according to the first embodiment of the present technology. The solid state image sensor <NUM> includes a circuit chip <NUM>, and a pixel chip <NUM> stacked above the circuit chip <NUM>. These chips are electrically connected through a connection section such as a via. Note that, these chips may also be connected through Cu-Cu bonding or a bump instead of the via.

<FIG> is a plan view illustrating a configuration example of the pixel chip <NUM> according to the first embodiment of the present technology. The pixel chip <NUM> includes a rectangular light receiving section <NUM>. In the light receiving section <NUM>, a plurality of photoelectric conversion elements <NUM> and a plurality of photoelectric conversion elements <NUM> are arrayed.

The photoelectric conversion elements <NUM> are linearly arrayed along a boundary of the light receiving section <NUM>. For example, photoelectric conversion elements <NUM> are arrayed in a line at an upper end of the light receiving section <NUM>. On the other hand, the photoelectric conversion elements <NUM> are arrayed in a two-dimensional lattice form. Among the photoelectric conversion elements <NUM> and <NUM>, the photoelectric conversion elements <NUM> are used for generating pixel data of image data. On the other hand, the photoelectric conversion elements <NUM> are used for monitoring electric potentials of any of cathodes and anodes (for example, electric potentials of the cathodes).

<FIG> is a block diagram illustrating a configuration example of a circuit chip <NUM> according to the first embodiment of the present technology. The circuit chip <NUM> includes a timing generation section <NUM>, a circuit block <NUM>, a histogram generation section <NUM>, an output interface <NUM>, multiplexers <NUM> and <NUM>, and time-to-digital converters <NUM> and <NUM>.

The timing generation section <NUM> is configured to generate a control signal RCH in synchronization with the synchronization signal CLKp. The timing generation section <NUM> supplies the control signal RCH to the circuit block <NUM>.

In the circuit block <NUM>, respective pixel circuits (not illustrated) of a plurality of monitor pixels and a plurality of imaging pixels are arrayed. Details of the respective circuit configurations of the monitor pixels and the imaging pixels will be described later. The imaging pixel generates a pulse signal in response to input of photon, and supplies the generated pulse signal to the multiplexer <NUM> or <NUM>.

The multiplexer <NUM> sequentially selects an odd row of the imaging pixels, and supplies pulse signals of the selected row to the time-to-digital converter <NUM>. The multiplexer <NUM> sequentially selects an even row of the imaging pixels, and supplies pulse signals of the selected row to the time-to-digital converter <NUM>.

The time-to-digital converter <NUM> is configured to convert time until rise of pulse signals in an odd row into digital signals. The digital signals indicate detection timings of photon. The time-to-digital converter <NUM> supplies the digital signals to the histogram generation section <NUM>. The time-to-digital converter <NUM> is configured to convert time until rise of pulse signals in an even row into digital signals. The time-to-digital converter <NUM> supplies the digital signals to the histogram generation section <NUM>.

The multiplexers <NUM> and <NUM> and the time-to-digital converters <NUM> and <NUM> make it possible to simultaneously process pulse signals in two rows. Note that, it is also possible for the solid state image sensor <NUM> to process pulse signals row by row. In this case, a circuit chip includes one of the multiplexers <NUM>/<NUM> and one of the time-to-digital converters <NUM>/<NUM>.

The histogram generation section <NUM> is configured to generate a histogram on the basis of the digital signals from the time-to-digital converters <NUM> and <NUM>. Here, the histogram is a graph that illustrates detection frequencies of respective detection timings indicated by the digital signals, as frequencies. The histogram generation section <NUM> generates the histogram for each imaging pixel, and calculates a timing of each peak value as a light reception timing of reflected light. Next, for each imaging pixel, the histogram generation section <NUM> converts a round-trip time between the light emission timing of irradiation light indicated by the synchronization signal and the light reception timing of the reflected light into a distance to the object. The histogram generation section <NUM> generates distance data indicating the calculated distance for each imaging pixel, and outputs the distance data to an outside via the output interface <NUM>.

<FIG> is a block diagram illustrating a configuration example of the circuit block <NUM> according to the first embodiment of the present technology. The circuit block <NUM> includes a plurality of monitor pixel circuits <NUM>, a plurality of imaging pixel circuits <NUM>, and a control section (or control circuit) <NUM>.

The monitor pixel circuit <NUM> is provided for each photoelectric conversion element <NUM>, and is connected to the corresponding photoelectric conversion element <NUM>. The photoelectric conversion element <NUM> and the monitor pixel circuit <NUM> connected to the photoelectric conversion element <NUM> function as a single monitor pixel. The monitor pixel is a pixel for monitoring electric potentials of any of cathodes and anodes (for example, electric potentials of the cathodes) of the photoelectric conversion elements <NUM> and <NUM>.

The imaging pixel circuit <NUM> is provided for each photoelectric conversion element <NUM>, and is connected to the corresponding photoelectric conversion element <NUM>. The photoelectric conversion element <NUM> and the imaging pixel circuit <NUM> corresponding to the photoelectric conversion element <NUM> function as a single imaging pixel. The imaging pixel is a pixel for generating a pulse signal in response to input of photon.

The control section <NUM> is configured to control electric potentials of any of the cathodes and the anodes (for example, electric potentials of the anodes) of the photoelectric conversion elements <NUM> and <NUM> on the basis of monitoring target electric potentials (such as cathodes) of the monitor pixels.

<FIG> is a block diagram illustrating a configuration example of a monitor pixel (or first pixel circuitry) <NUM> according to the first embodiment of the present technology. As described above, a circuit including the photoelectric conversion element <NUM> of the pixel chip <NUM> and the monitor pixel circuit <NUM> of the circuit chip <NUM> functions as the single monitor pixel <NUM>. In addition, the monitor pixel circuit <NUM> includes a p-channel metal-oxide-semiconductor (pMOS) transistor <NUM>, a timing detection circuit (or delay circuit) <NUM>, a sample and hold circuit (or holding circuit) <NUM>, and buffers (or buffer circuits) <NUM> and <NUM>.

The pMOS transistor <NUM> is interposed between a power source electric potential VE and the photoelectric conversion element <NUM>. In addition, a control signal RCH is input from the timing generation section <NUM> to a gate of the pMOS transistor <NUM>. When a low-level control signal RCH is input, the pMOS transistor <NUM> supplies the power source electric potential VE to a connection node <NUM> to the photoelectric conversion element <NUM>. Note that, the power source electric potential VE is an example of a predetermined electric potential according to an embodiment of the present technology, and the pMOS transistor <NUM> is an example of an electric potential supply element according to an embodiment of the present technology. In addition, the connection node <NUM> is an example of a predetermined node according to an embodiment of the present technology.

The photoelectric conversion element <NUM> is configured to output photocurrent through photoelectric conversion in response to incident photon. For example, the SPAD is used as the photoelectric conversion element <NUM>. A cathode of the photoelectric conversion element <NUM> is connected to the connection node <NUM>, and a cathode electric potential Vs of the cathode is the monitoring target electric potential. On the other hand, an anode of the photoelectric conversion element <NUM> is connected to the control section <NUM>, and the control section <NUM> controls an anode electric potential VSPAD of the anode.

The buffer <NUM> is interposed between the connection node <NUM> and the sample and hold circuit <NUM>. Note that, the buffer <NUM> is an example of an input-side buffer according to an embodiment of the present technology.

The timing detection circuit <NUM> is configured to monitor the cathode electric potential Vs, and detects a timing at which a predetermined period of time has elapsed since the cathode electric potential Vs started to decrease from the electric potential (that is, the power source electric potential VE) supplied by the pMOS transistor <NUM>. In the case where the cathode electric potential Vs is the monitoring target, the cathode electric potential Vs becomes lower than the power source electric potential VE when photocurrent flows in response to incident photon. Note that, as described later, it is also possible for the monitor pixel <NUM> to monitor the anode electric potential. In the case where the anode electric potential is monitored, the timing detection circuit <NUM> detects a timing at which a predetermined period of time has elapsed since the anode electric potential started to increase.

The sample and hold circuit <NUM> is configured to capture and hold the cathode electric potential Vs on the basis of the timing detected by the timing detection circuit <NUM>. The sample and hold circuit <NUM> outputs the held electric potential to the buffer <NUM> as a holding potential Vs_SH.

The buffer <NUM> is interposed between the sample and hold circuit <NUM> and the control section <NUM>. Note that, the buffer <NUM> is an example of an output-side buffer according to an embodiment of the present technology. Note that, the buffer <NUM> is not necessary, and it is possible to omit the buffer <NUM>. In addition, it is also possible to install two or more buffers <NUM>/<NUM>.

<FIG> is a circuit diagram illustrating the configuration example of the monitor pixel 401according to the first embodiment of the present technology. The timing detection circuit <NUM> includes an inverter <NUM> and a pulse generation circuit <NUM>. In addition, the sample and hold circuit <NUM> includes a sample switch <NUM> and a capacitor <NUM>. The buffer <NUM> includes an nMOS transistor <NUM> and an electric current source <NUM>.

The inverter <NUM> in the timing detection circuit <NUM> is configured to invert a signal of the cathode electric potential Vs, and output the inverted signal to the pulse generation circuit <NUM>. In addition, the pulse generation circuit <NUM> is configured to delay the inverted signal from the inverter <NUM> by predetermined delay time, and generate a pulse signal SW on the basis of the delayed signal. The pulse generation circuit <NUM> supplies the pulse signal SW to the sample switch <NUM>.

The sample switch <NUM> in the sample and hold circuit <NUM> is configured to capture (in other words, sample) the cathode electric potential Vs via the buffer <NUM> within a time period of a pulse width of the pulse signal SW. The capacitor <NUM> is configured to hold the sampled cathode electric potential Vs as the holding potential Vs_SH.

In the buffer <NUM>, the nMOS transistor <NUM> is interposed between a power source electric potential and the electric current source <NUM>. In addition, the holding potential Vs_SH is input from the sample and hold circuit <NUM> to a gate of the nMOS transistor <NUM>. In addition, a back gate of the nMOS transistor <NUM> is connected to a connection node between the nMOS transistor <NUM> and the electric current source <NUM>. The connection node is connected to the control section <NUM>.

Note that, the circuit configuration of the buffer <NUM> is similar to the buffer <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the pulse generation circuit <NUM> according to the first embodiment of the present technology. The pulse generation circuit <NUM> includes a delay circuit <NUM>, an inverter <NUM>, a delay circuit <NUM>, a NOT AND (NAND) gate <NUM>, and an inverter <NUM>. The delay circuit <NUM> includes an electric current source <NUM>, a pMOS transistor <NUM>, an n-channel metal-oxide-semiconductor (nMOS) transistor <NUM>, and a capacitor <NUM>.

The delay circuit <NUM> is configured to delay an inverted signal VA from the inverter <NUM> by predetermined delay time. In the delay circuit <NUM>, the pMOS transistor <NUM>, the nMOS transistor <NUM> and the electric current source <NUM> are connected in series between a power source electric potential and a ground electric potential. In addition, gates of the pMOS transistor <NUM> and the nMOS transistor <NUM> are connected in common to an output terminal of the inverter <NUM>. The capacitor <NUM> is interposed between a ground electric potential and a connection node that connects the pMOS transistor <NUM> to the nMOS transistor <NUM>. In addition, the connection node outputs a delayed signal VB obtained by delaying the inverted signal VA.

The inverter <NUM> is configured to invert the delayed signal VB. The inverter <NUM> outputs an inverted signal VC to the delay circuit <NUM> and the NAND gate <NUM>.

The delay circuit <NUM> is configured to delay the inverted signal VC by predetermined delay time. The circuit configuration of the delay circuit <NUM> is similar to the delay circuit <NUM>. The delay circuit <NUM> outputs a delayed signal VD to the NAND gate <NUM>.

The NAND gate <NUM> is configured to output a signal of the NAND of the inverted signal VC and the delayed signal VD to the inverter <NUM> as an output signal.

The inverter <NUM> is configured to invert the output signal from the NAND gate <NUM>. The inverter <NUM> outputs the inverted signal to the sample and hold circuit <NUM> as a pulse signal SW.

<FIG> is a timing diagram illustrating an example of operation of the pulse generation circuit <NUM> according to the first embodiment of the present technology.

It is assumed that, at a timing T1, the inverted signal VA from the inverter <NUM> rises from a low level to a high level. The delay circuit <NUM> delays the inverted signal VA, and outputs the delayed signal VB.

In addition, the inverter <NUM> inverts the delayed signal VB. The inverted signal VC raises at a timing T2. The delay circuit <NUM> delays the inverted signal VC, and outputs the delayed signal VD.

In addition, at the timing T2, the inverter <NUM> inverts the NAND of the inverted signal VC and the delayed signal VD and generates the pulse signal SW. The pulse width of the pulse signal SW is a time period between the timing T2 and a timing T3.

<FIG> is a circuit diagram illustrating a configuration example of an imaging pixel <NUM> according to the first embodiment of the present technology. As described above, a circuit including the photoelectric conversion element <NUM> of the pixel chip <NUM> and the imaging pixel circuit <NUM> of the circuit chip <NUM> functions as the single imaging pixel <NUM>. The imaging pixel circuit <NUM> includes a pMOS transistor <NUM> and an inverter <NUM>.

A connection structure between the pMOS transistor <NUM> and the photoelectric conversion element <NUM> is similar to the connection structure between the pMOS transistor <NUM> and the photoelectric conversion element <NUM> in the monitor pixel <NUM>.

The inverter <NUM> is configured to invert a signal of a cathode electric potential of the photoelectric conversion element <NUM>, and supply the inverted signal to the multiplexer <NUM> (or the multiplexer <NUM>) as a pulse signal of the imaging pixel <NUM>.

<FIG> is a plan view illustrating a configuration example of a pixel array section <NUM> according to the first embodiment of the present technology. The pixel array section <NUM> includes the light receiving section <NUM> of the pixel chip <NUM> and the circuit block <NUM> of the circuit chip <NUM>.

In the pixel array section <NUM>, a plurality of the monitor pixels <NUM> and a plurality of the imaging pixels <NUM> are arrayed. The monitor pixels <NUM> are linearly arrayed along a boundary of the pixel array section <NUM>. For example, the monitor pixels <NUM> are arrayed in a line at an upper end of the pixel array section <NUM>. On the other hand, the imaging pixels <NUM> are arrayed in a two-dimensional lattice form.

<FIG> is a block diagram illustrating a configuration example of the monitor pixels <NUM>, the imaging pixels <NUM>, and the control section <NUM> according to the first embodiment of the present technology. The control section <NUM> includes an inter-pixel average acquisition section (or averaging circuit) <NUM>, a time average acquisition section (or time averaging circuit) <NUM>, and an electric potential control section (or potential controller) <NUM>.

Each of the plurality of monitor pixels <NUM> supplies the holding potential Vs_SH to the inter-pixel average acquisition section <NUM>. A holding potential of an m-th monitor pixel <NUM> is referred to as Vs_SHm (m is an integer).

The inter-pixel average acquisition section <NUM> is configured to calculate an average of the respective holding potentials Vs_SHm of the plurality of monitor pixels <NUM> as an inter-pixel average Vs_SHAVp. The inter-pixel average acquisition section <NUM> supplies the inter-pixel average Vs_SHAVp to the time average acquisition section <NUM>.

The time average acquisition section <NUM> is configured to calculate a time average Vs_SHAVt of the inter-pixel averages Vs_SHAVp. The time average acquisition section <NUM> supplies the time average Vs_SHAVt to the electric potential control section <NUM>.

The electric potential control section <NUM> is configured to control the anode electric potential VSPAD in a manner that the anode electric potential VSPAD becomes lower as the time average Vs_SHAVt of the held cathode electric potential gets higher. All anodes of the plurality of monitor pixels <NUM> and the plurality of imaging pixels <NUM> are connected in common to the electric potential control section <NUM>, and the electric potential control section <NUM> controls electric potentials of the anodes. Note that, the electric potential control section <NUM> controls cathode electric potentials if the monitor pixels <NUM> monitor anode electric potentials.

In addition, in the monitor pixel <NUM>, one of the anode and the cathode of the photoelectric conversion element <NUM> (for example, the cathode) is connected to the connection node <NUM>. The pMOS transistor <NUM> supplies the power source electric potential VE to the connection node <NUM> in response to the control signal RCH.

The timing detection circuit <NUM> detects a timing at which a predetermined period of time has elapsed since the cathode electric potential Vs of the connection node <NUM> started to decrease from the power source electric potential VE. This timing corresponds to a timing at which a predetermined delay time has elapsed since the cathode electric potential fell below a threshold of the inverter <NUM>.

The sample and hold circuit <NUM> captures and holds the cathode electric potential Vs as the holding potential Vs_SH on the basis of the timing detected by the timing detection circuit <NUM>.

Next, the control section <NUM> controls the other of the anode and the cathode of the photoelectric conversion element <NUM> (for example, the anode) in a manner that the electric potential becomes lower as the holding potential Vs_SH gets higher.

In addition, in the monitor pixel <NUM>, the buffer <NUM> is installed at a stage prior to the sample and hold circuit <NUM>. This makes it possible to uniform capacitances of the respective connection nodes of the monitor pixels <NUM> and the imaging pixels <NUM>. This connection node is the connection node between the photoelectric conversion element and the pMOS transistor. This makes it possible to uniform the respective breakdown voltages VBD of the monitor pixels <NUM> and the imaging pixels <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the control section <NUM> according to the first embodiment of the present technology. The inter-pixel average acquisition section <NUM> includes a plurality of resistors <NUM> and a capacitor <NUM>. The resistors <NUM> are provided for the respective monitor pixels <NUM>. The time average acquisition section <NUM> includes a variable resistor <NUM> and a variable capacitor <NUM>. The electric potential control section <NUM> includes an amplifier <NUM>.

The resistor <NUM> in the inter-pixel average acquisition section <NUM> has an end connected to the corresponding monitor pixel <NUM>, and the other end connected to an end of the capacitor <NUM> and the time average acquisition section <NUM>. In other words, the plurality of resistors <NUM> is connected in parallel between the plurality of monitor pixels <NUM> and the capacitor <NUM>. The other end of the capacitor <NUM> is connected to a ground electric potential. The resistors <NUM> make it possible to generate an average electric potential of the holding potentials Vs_SHm of the plurality of monitor pixels <NUM> as the inter-pixel average Vs_SHAVp, and the capacitor <NUM> holds the inter-pixel average Vs_SHAVp. By acquiring the inter-pixel average, it is possible to suppress bad influences caused by variation in the holding potentials Vs_SH between the pixels.

In addition, the variable resistor <NUM> in the time average acquisition section <NUM> has an end connected to the inter-pixel average acquisition section <NUM>, and the other end connected to an end of the variable capacitor <NUM> and the electric potential control section <NUM>. The other end of the variable capacitor <NUM> is connected to a ground electric potential. A circuit including the variable resistor <NUM> and the variable capacitor <NUM> functions as an analog low-pass filter that generates the time average Vs_SHAVt of the inter-pixel averages Vs_SHAVp. Note that, the circuit including the variable resistor <NUM> and the variable capacitor <NUM> is an example of an analog filter according to an embodiment of the present technology.

The time average Vs_SHAVt is input to an inverting input terminal (-) of the amplifier <NUM> in the electric potential control section <NUM>, and a predetermined power source electric potential is input to a non-inverting input terminal (+). The amplifier <NUM> generates a comparison result between the time average Vs_SHAVt and the predetermined power source electric potential as the VSPAD by using the following expression, and supplies the VSPAD to the anodes of the monitor pixels <NUM> and the imaging pixels <NUM>.

In the above expression, Av represents gain of the amplifier <NUM>, and VREF represents a target value of the VSPAD.

<FIG> is a diagram illustrating an example of variation in the cathode electric potential Vs and the anode electric potential VSPAD according to the first embodiment of the present technology. The pMOS transistor <NUM> supplies the power source electric potential VE, and then the cathode electric potential Vs becomes the power source electric potential VE. When photon enters, the cathode electric potential Vs decreases to a bottom electric potential VBT, and increases to the initial power source electric potential VE through recharge.

Here, voltage between the power source electric potential VE and the bottom electric potential VBT is referred to as excess bias VEX. In addition, voltage between the bottom electric potential VBT and the anode electric potential VSPAD is referred to as the breakdown voltage VBD. In the case where the power source electric potential VE and the anode electric potential VSPAD are constant, the excess bias VEX varies depending on temperature and variation in the breakdown voltage VBD.

In the case where the excess bias VEX becomes small, sensitivities of photodiodes in the imaging pixels <NUM> decreases when the photon enters. In such a case, the pulse signals of the imaging pixels <NUM> are not generated even when the photon enters, and photon detection efficiency (PDE) decreases. Therefore, the control section <NUM> reduces the anode electric potential VSPAD as the holding potential gets higher when the cathode electric potential Vs decreases. This makes it possible to increase the breakdown voltage VBD, increase the excess bias VEX, and improve the PDE.

<FIG> and <FIG> are diagrams illustrating examples of variation in excess bias VEX and an anode electric potential VSPAD according to the first embodiment of the present technology and a comparative example. <FIG> is a diagram illustrating an example of variation in excess bias VEX and an anode electric potential VSPAD according to the first embodiment. <FIG> is a diagram illustrating an example of variation in excess bias VEX according to the comparative example in which the anode electric potential VSPAD is not controlled. In <FIG> and <FIG>, vertical axes represent electric potentials, and horizontal axes represent temperatures. In addition, in <FIG> and <FIG>, it is assumed that an amount of incident light is constant, and the holding potential Vs_SH is substantially the same as the bottom electric potential VBT.

The holding potential (the bottom electric potential VBT) increases as the temperature gets higher. Therefore, as illustrated in <FIG>, the control section <NUM> reduces the anode electric potential VSPAD by a value corresponding to the increase. As a result, it is possible to maintain the excess bias VEX at a constant value without depending on the variation in temperature. This makes it possible to suppress reduction in the PDE caused by the variation in temperature.

On the other hand, in the comparative example in which the anode electric potential VSPAD is not controlled as illustrated in <FIG>, the bottom electric potential VBT increases as the temperature gets higher, and thereby the excess bias VEX decreases. This causes reduction in the PDE.

As illustrated in <FIG> and <FIG>, it is possible to suppress reduction in the PDE caused by the variation in temperature under the control of the control section <NUM>. However, monitor voltage (such as the cathode electric potentials) for observing the bottom electric potential VBT follows the variation in the excess bias caused by the temperature, and the monitor voltage also varies depending on decrease or increase in an amount of incident light.

<FIG> are timing diagrams illustrating variation in a cathode electric potential Vs obtained in the case of a large amount of light and variation in a cathode electric potential Vs obtained in the case of a small amount of light according to the first embodiment of the present technology. <FIG> is a timing diagram illustrating variation in the cathode electric potential Vs obtained in the case of a relatively small amount of light. <FIG> is a timing diagram illustrating variation in the cathode electric potential Vs obtained in the case of a relatively large amount of light. In <FIG>, it is assumed that the temperature is constant.

In the case of the small amount of light as illustrated in <FIG>, recharge is done at a timing T1, and the cathode electric potential Vs becomes a power source electric potential VE. Next, when the photon enters at a timing T10, the cathode electric potential Vs starts decreasing. After a timing T12, the cathode electric potential Vs becomes constant. The electric potential obtained at the timing T12 is a bottom electric potential VBT1.

On the other hand, in the case of the large amount of light as illustrated in <FIG>, a cathode electric potential Vs has the same locus as <FIG> until the timing T12. However, after the timing T12, a leakage current increases in response to the amount of light, and the cathode electric potential Vs further decreases. Subsequently, the cathode electric potential Vs reaches a bottom electric potential VBT2 immediately before a timing T2 at which recharge will be done again. The bottom electric potential VBT2 is lower than the bottom electric potential VBT1 obtained in the case of the small amount of light.

As described above, even in the case where the temperature is constant, the bottom electric potential VBT varies because of decrease or increase in the amount of incident light. Therefore, if the control section <NUM> controls the anode electric potential VSPAD on the basis of the bottom electric potential VBT, this causes variation in a voltage value for suppressing variation in the excess bias caused by decrease or increase in an amount of light.

Accordingly, the timing detection circuit <NUM> in the monitor pixel <NUM> adjusts delay time and a threshold VT and detects the timing T12 in a manner that the timing T12 is a timing at which the delay time has elapsed since a timing T11. Next, the sample and hold circuit <NUM> captures the cathode electric potential Vs of the timing T12, and holds it as the holding potential Vs_SH. As illustrated in <FIG>, the locus of the cathode electric potential Vs in <FIG> is the same as the locus of the cathode electric potential Vs in <FIG> until the timing T12 regardless of the decrease or increase in amounts of light. Therefore, it is possible to uniformly suppress variation in the excess bias caused by decrease or increase in the amount of light, when the control section <NUM> controls the anode electric potential VSPAD in response to the holding potential Vs_SH at any given time. This makes it possible to further improve the PDE. Note that, the time period between the timing T10 and the timing T12 is an example of a predetermined period of time according to an embodiment of the present technology.

<FIG> are timing diagrams illustrating examples of fluctuations in the bottom electric potential VBT obtained in the case of the large amount of light and fluctuations in the bottom electric potential VBT obtained in the case of the small amount of light according to the first embodiment of the present technology. <FIG> is a timing diagram illustrating an example of fluctuations in the bottom electric potential VBT obtained in the case of the small amount of light. <FIG> is a timing diagram illustrating an example of fluctuations in the bottom electric potential VBT obtained in the case of the large amount of light. In addition, dash-dotted lines indicate time averages of the bottom electric potentials VBT.

<FIG> is a scatter plot illustrating an example of a variation range of the breakdown voltage VBD according to the first embodiment of the present technology. In <FIG>, a vertical axis represents voltage of the breakdown voltage VBD, and a horizontal axis represents the number of pixels (the monitor pixels and the imaging pixels). In addition, each plotted dot represents breakdown voltage VBD of a single pixel, and a solid curve represents a boundary of a set of the plotted dots. As exemplified in <FIG>, the distribution of breakdown voltage VBD is similar to a normal distribution.

<FIG> is a timing diagram illustrating an example of operation of the monitor pixel <NUM> and the control section <NUM> according to the first embodiment of the present technology. The monitor pixel <NUM> is recharged at a timing T1, and the cathode electric potential Vs becomes a power source electric potential VE. Next, when the photon enters at a timing T10, the cathode electric potential Vs starts decreasing.

When the cathode electric potential Vs falls below a threshold VT of the inverter <NUM> at a timing T11, an inverted signal of the inverter <NUM> rises, and the pulse generation circuit <NUM> generates a pulse signal SW at a timing T12 after delaying the inverted signal by delay time.

The sample and hold circuit <NUM> captures the cathode electric potential Vs within a time period of the pulse width of the pulse signal SW, and holds it as the holding potential Vs_SH.

In addition, at the timing T1, the connection node <NUM> shifts from a high impedance (Hi-Z) state to a low impedance (Low-Z) state through the recharge. Subsequently, the connection node <NUM> shifts to the high impedance state before the timing T12.

The amount of decrease in the cathode electric potential Vs after the timing T12 varies depending on an amount of light. However, at the timing T12, the sample and hold circuit <NUM> holds the cathode electric potential Vs. This makes it possible to maintain the holding potential Vs_SH at a constant value regardless of the amount of light. Therefore, it is possible to suppress variation in the excess bias caused by decrease or increase in the amount of light, when the control section <NUM> controls the anode electric potential VSPAD in response to the holding potential Vs_SH.

<FIG> is a flowchart illustrating an example of operation of the solid state image sensor <NUM> according to the first embodiment of the present technology. This operation starts when a predetermined application for measuring a distance is executed, for example.

The monitor pixel <NUM> detects a timing at which delay time has elapsed since the cathode electric potential Vs fell below the threshold VT (Step S901). Next, the monitor pixel <NUM> captures and holds the cathode electric potential Vs on the basis of the timing (Step S902). The control section <NUM> controls the anode electric potential VSPAD in a manner that the anode electric potential VSPAD decreases as the holding potential gets higher (Step S903). After Step S903, the monitor pixel <NUM> repeatedly executes Step S901 and the subsequent steps.

As described above, according to the first embodiment of the present technology, the monitor pixel <NUM> detects a timing at which a predetermined period of time has elapsed since decrease in a cathode electric potential, and captures and holds the cathode electric potential at that timing. This makes it possible to hold the electric potential without depending on an amount of light. It is possible to suppress variation in bias voltage resulting from decrease or increase in the amount of light, when the control section <NUM> controls an anode electric potential in response to the holding potential.

In the first embodiment described above, the monitor pixel <NUM> monitors the cathode electric potential Vs of the photoelectric conversion element <NUM>, and controls the anode electric potential on the basis of the cathode electric potential Vs. However, it is also possible for the monitor pixel <NUM> to monitor the anode electric potential instead of the cathode electric potential. Such a monitor pixel <NUM> according to the first modification of the first embodiment is different from the monitor pixel <NUM> according to the first embodiment in that the monitor pixel <NUM> according to the first modification monitors the anode electric potential of the photoelectric conversion element <NUM> and controls the cathode electric potential on the basis of the anode electric potential.

<FIG> is a block diagram illustrating a configuration example of the monitor pixel <NUM> according to the first modification of the first embodiment of the present technology. In the monitor pixel <NUM> according to the first modification of the first embodiment, the anode of the photoelectric conversion element <NUM> is connected to the connection node <NUM>, and the cathode is connected to the control section <NUM>. In addition, the pMOS transistor <NUM> is interposed between the connection node <NUM> and the ground electric potential VS.

Note that, a connection structure between the photoelectric conversion element <NUM> and the pMOS transistor <NUM> in an imaging pixel <NUM> is similar to that of the monitor pixel <NUM>.

The timing detection circuit <NUM> detects a timing at which a predetermined period of time has elapsed since the anode electric potential becomes higher than the ground electric potential VS. In this case, for example, it is only necessary for the timing detection circuit <NUM> to include the inverters at two stages or include a buffer instead of the inverter.

As described above, according to the first modification of the first embodiment of the present technology, the monitor pixel <NUM> detects a timing at which a predetermined period of time has elapsed since increase in the anode electric potential, and captures and holds the anode electric potential at that timing. This makes it possible to hold the electric potential without depending on an amount of light. It is possible to suppress variation in bias voltage resulting from decrease or increase in the amount of light, when the control section <NUM> controls the cathode electric potential in response to the holding potential.

In the first embodiment described above, the function of the control section <NUM> is implemented by the analog circuit. However, in general, the analog circuit has a larger circuit size than a digital circuit. Therefore, this may result in increase in the size of the footprint. A control section <NUM> according to the second modification of the first embodiment is different from the control section <NUM> according to the first modification in that the control section <NUM> according to the second modification includes a digital circuit.

<FIG> is a block diagram illustrating a configuration example of the control section <NUM> according to the second modification of the first embodiment of the present technology. In the control section <NUM> according to the second modification of the first embodiment, the inter-pixel average acquisition section <NUM> includes an analog-to-digital conversion section <NUM> and an averaging filter <NUM>. In addition, the time average acquisition section <NUM> includes a digital low-pass filter <NUM>. The electric potential control section <NUM> includes a power integrated circuit (IC) <NUM>.

The analog-to-digital conversion section <NUM> is configured to convert respective holding potentials of the plurality of monitor pixels <NUM> into digital signals. The analog-to-digital conversion section <NUM> includes a plurality of analog-to-digital converters (ADC) <NUM>. The ADCs <NUM> are provided for the respective monitor pixels <NUM>. The ADC <NUM> converts the holding potential Vs_SHm of the corresponding monitor pixel <NUM> into a digital signal, and supplies the digital signal to the averaging filter <NUM>.

The averaging filter <NUM> is a digital filter for calculating an average value of the respective digital signals of the plurality of monitor pixels <NUM> as an inter-pixel average Vs_SHAVp.

The digital low-pass filter <NUM> is a digital filter that passes low-frequency components. The low-frequency components are lower than a predetermined cutoff frequency. This makes it possible to obtain a time average Vs_SHAVt of the inter-pixel averages Vs_SHAVp.

The power IC <NUM> is configured to control the anode electric potential VSPAD in a manner that the anode electric potential VSPAD becomes lower as the time average Vs_SHAVt gets higher. Note that, the power IC <NUM> is an example of a power semiconductor according to an embodiment of the present technology.

As illustrated in <FIG>, it is possible to reduce the size of the footprint of the control section <NUM> when the function of the control section <NUM> is implemented by the digital circuit.

As described above, according to the second modification of the first embodiment of the present technology, the control section <NUM> includes the digital circuit. This makes it possible to reduce the size of the footprint in comparison with the case of the analog circuit.

In the second modification of the first embodiment described above, the inter-pixel average acquisition section <NUM> includes the ADCs <NUM> corresponding to the respective monitor pixels <NUM>. However, in this case, the number of the ADCs <NUM> increases as the number of monitor pixels <NUM> gets larger. An inter-pixel average acquisition section <NUM> according to the third modification of the first embodiment is different from the inter-pixel average acquisition section <NUM> according to the second modification of the first embodiment in that a plurality of monitor pixels <NUM> according to the third modification shares a single ADC <NUM>.

<FIG> is a block diagram illustrating a configuration example of the inter-pixel average acquisition section <NUM> according to the third modification of the first embodiment of the present technology. The inter-pixel average acquisition section <NUM> according to the third modification of the first embodiment is different from the inter-pixel average acquisition section <NUM> according to the second modification of the first embodiment in that an analog-to-digital conversion section <NUM> according to the third modification includes a single selector <NUM> and the single ADC <NUM>.

The selector <NUM> is configured to sequentially select any of the respective holding potentials Vs_SHm of the plurality of monitor pixels <NUM>. The selector <NUM> supplies the selected holding potential to the ADC <NUM>. Each time a holding potential is selected, the ADC <NUM> converts the holding potential into a digital signal and supplies the digital signal to the averaging filter <NUM>.

As exemplified in <FIG>, it is possible for the plurality of monitor pixels <NUM> to share the single ADC <NUM> because the selector <NUM> is installed. This makes it possible to reduce the circuit size in comparison with the case where the ADCs <NUM> are provided for the respective monitor pixels <NUM>.

As described above, according to the third modification of the first embodiment of the present technology, the selector <NUM> is installed for selecting any of the respective holding potentials Vs_SHm of the plurality of monitor pixels <NUM>. This allows the plurality of monitor pixels <NUM> to share the single ADC <NUM>.

In the first embodiment described above, a function of the control section <NUM> is implemented by the analog circuit. However, in general, the analog circuit has a larger circuit size than a digital circuit. Therefore, this may result in increase in the size of the footprint. A control section <NUM> according to the fourth modification of the first embodiment is different from the control section <NUM> according to the first modification in that the control section <NUM> according to the fourth modification includes digital circuits.

<FIG> is a block diagram illustrating a configuration example of the control section <NUM> according to the fourth modification of the first embodiment of the present technology. In the control section <NUM> according to the fourth modification of the first embodiment, the time average acquisition section <NUM> includes an ADC <NUM> and the digital low-pass filter <NUM>, and the electric potential control section <NUM> includes the power IC <NUM>. In addition, the circuit configuration of the inter-pixel average acquisition section <NUM> according to the fourth modification of the first embodiment is similar to that of the first embodiment.

The ADC <NUM> is configured to convert an analog inter-pixel average Vs_SHAVp into a digital signal, and supply the digital signal to the digital low-pass filter <NUM>.

As described above, according to the fourth modification of the first embodiment of the present technology, the time average acquisition section <NUM> and the electric potential control section <NUM> includes digital circuits. This makes it possible to reduce the size of the footprint in comparison with the case of the analog circuit.

In the first embodiment described above, the function of the control section <NUM> is implemented by the analog circuit. However, in general, the analog circuit has a larger circuit size than a digital circuit. Therefore, this may result in increase in the size of the footprint. A control section <NUM> according to the fifth modification of the first embodiment is different from the control section <NUM> according to the first modification in that the control section <NUM> according to the fifth modification includes a digital circuit.

<FIG> is a block diagram illustrating a configuration example of the control section <NUM> according to the fifth modification of the first embodiment of the present technology. In the control section <NUM> according to the fifth modification of the first embodiment, the electric potential control section <NUM> includes an ADC <NUM> and the power IC <NUM>. In addition, the circuit configurations of the inter-pixel average acquisition section <NUM> and the time average acquisition section <NUM> according to the fifth modification of the first embodiment are similar to those of the first embodiment.

The ADC <NUM> is configured to convert an analog time average Vs_SHAVt into a digital signal, and supply the digital signal to the power IC <NUM>.

As described above, according to the fifth modification of the first embodiment of the present technology, the electric potential control section <NUM> includes the digital circuit. This makes it possible to reduce the size of the footprint in comparison with the case of the analog circuit.

In the first embodiment described above, the buffers <NUM> and <NUM> output single-ended signals. However, if the number of monitor pixels <NUM> increases and therefore signal lines that transmit the single-ended signals have longer wire lengths, wiring resistance increases. This may result in shortage of driving forces of the buffers <NUM> and <NUM>. Buffers <NUM> and <NUM> according to the sixth modification of the first embodiment are different from the buffers <NUM> and <NUM> according to the first embodiment in that the buffers <NUM> and <NUM> according to the sixth modification output differential signals.

<FIG> is a circuit diagram illustrating a configuration example of a monitor pixel <NUM> according to the sixth modification of the first embodiment of the present technology. In the monitor pixel <NUM> according to the sixth modification of the first embodiment, the buffer <NUM> includes electric current sources <NUM> and <NUM> and pMOS transistors <NUM> and <NUM>. In addition, the buffer <NUM> includes electric current sources <NUM> and <NUM> and nMOS transistors <NUM> and <NUM>.

In the buffer <NUM>, the electric current source <NUM> and the pMOS transistor <NUM> are connected in series between a power source electric potential and a ground electric potential. The electric current source <NUM> is connected to the power source side, and a gate of the pMOS transistor <NUM> is connected to the connection node <NUM>. In addition, a connection node between the electric current source <NUM> and the pMOS transistor <NUM> is connected to the sample switch <NUM>.

The electric current source <NUM> and the pMOS transistor <NUM> are connected in series between a power source electric potential and a ground electric potential. The electric current source <NUM> is connected to the power source side, and a gate of the pMOS transistor <NUM> is connected to the ground electric potential. In addition, a connection node between the electric current source <NUM> and the pMOS transistor <NUM> is connected to the buffer <NUM>.

In the buffer <NUM>, the nMOS transistor <NUM> and the electric current source <NUM> are connected in series between a power source electric potential and a ground electric potential. The electric current source <NUM> is connected to the ground side, and a gate of the nMOS transistor <NUM> is connected to the sample switch <NUM>. In addition, a connection node between the nMOS transistor <NUM> and the electric current source <NUM> is connected to the control section <NUM> via a signal line <NUM>.

The nMOS transistor <NUM> and the electric current source <NUM> are connected in series between a power source electric potential and a ground electric potential. The electric current source <NUM> is connected to the ground side, and a gate of the nMOS transistor <NUM> is connected to the buffer <NUM>. In addition, a connection node between the nMOS transistor <NUM> and the electric current source <NUM> is connected to the control section <NUM> via a signal line <NUM>.

The connection structure exemplified in <FIG> allows the buffer <NUM> to generate a differential signal on the basis of a cathode electric potential Vs and output the generated differential signals, and allows the buffer <NUM> to generate a differential signal on the basis of a holding potential Vs_SH and output the generated differential signal.

<FIG> is a circuit diagram illustrating a configuration example of an inter-pixel average acquisition section <NUM> according to the sixth modification of the first embodiment of the present technology. The inter-pixel average acquisition section <NUM> according to the sixth modification of the first embodiment includes capacitors <NUM> and <NUM> and an ADC <NUM>.

Positive sides of respective differential signals of the plurality of monitor pixels <NUM> are connected in common to the capacitor <NUM> and a positive-side input terminal of the ADC <NUM>. In addition, negative sides of the respective differential signals of the plurality of monitor pixels <NUM> are connected in common to the capacitor <NUM> and the positive-side input terminal of the ADC <NUM>. The ADC <NUM> converts the differential signals into digital signals, and outputs the digital signals to the time average acquisition section <NUM>.

As described above, in the sixth modification of the first embodiment of the present technology, the buffers <NUM> and <NUM> output differential signals. This makes it possible to obtain more accurate output values than the case of outputting single-ended signals.

In the first embodiment described above, the monitor pixel <NUM> includes the buffers (<NUM> and <NUM>) at two stages. However, such a monitor pixel consumes more electric power and more response time is necessary than the case of including a buffer at a single stage. Here, the response time means time from when photon enters until when a cathode electric potential is held. A monitor pixel <NUM> according to the second embodiment is different from the monitor pixel <NUM> according to the first embodiment in that a buffer is omitted from the monitor pixel <NUM> according to the second embodiment.

<FIG> is a block diagram illustrating a configuration example of the monitor pixel <NUM> according to the second embodiment of the present technology. The monitor pixel <NUM> according to the second embodiment is different from the monitor pixel <NUM> according to the first embodiment in that the monitor pixel <NUM> according to the second embodiment does not include the buffer <NUM>.

<FIG> is a circuit diagram illustrating the configuration example of the monitor pixel <NUM> according to the second embodiment of the present technology. In the monitor pixel <NUM> according to the second embodiment, the timing detection circuit <NUM> includes the delay circuit <NUM> instead of the pulse generation circuit <NUM>. In addition, the buffer <NUM> includes an electric current source <NUM> and pMOS transistors <NUM> and <NUM>.

The circuit configuration of the delay circuit <NUM> according to the second embodiment is similar to that of the first embodiment. The delay circuit <NUM> delays an inverted signal from the inverter <NUM> by predetermined delay time, and supplies a delayed signal SW' to the sample switch <NUM>.

The sample and hold circuit <NUM> captures the cathode electric potential Vs in the case where the delayed signal SW' is at a high level, and holds the captured electric potential in the case where the delayed signal SW' is at a low level.

In addition, in the buffer <NUM>, the electric current source <NUM> and the pMOS transistors <NUM> and <NUM> are connected in series between a power source electric potential and a ground electric potential. A trigger signal Tr is input to a gate of the pMOS transistor <NUM>, and the holding potential Vs_SH of the sample and hold circuit <NUM> is input to a gate of the pMOS transistor <NUM>. The trigger signal Tr is the same signal as the delayed signal SW'. The pMOS transistor <NUM> is turned off when the sample and hold circuit <NUM> is turned on, and the pMOS transistor <NUM> is turned on when the sample and hold circuit <NUM> is turned off. In addition, a connection node between the pMOS transistors <NUM> and <NUM> is connected to the control section <NUM>.

As exemplified in <FIG>, the buffer <NUM> is omitted. Therefore, it is possible to reduce power consumption by an amount of power to be consumed by the buffer <NUM>, and it is possible to shorten the response time by an amount of time to be consumed by the buffer <NUM>. In addition, it is possible to design a wider voltage range for the cathode electric potential Vs than the case where the buffers are provided at two stages. This makes it possible to widen a dynamic range by the widened voltage range.

<FIG> is a timing diagram illustrating an example of operation of the monitor pixel <NUM> and the control section <NUM> according to the second embodiment of the present technology.

Within a time period from a timing T1 immediately after recharge to a timing T12 at which delay time has elapsed, the timing detection circuit <NUM> delays an inverted signal and outputs a high-level delayed signal SW'. In addition, within a time period from the timing T12 to a timing T2 of next recharge, the timing detection circuit <NUM> delays the inverted signal and outputs a low-level delayed signal SW'.

The sample and hold circuit <NUM> samples the cathode electric potential Vs in the case of the high-level delayed signal SW'. During this high-level period, the cathode electric potential Vs decreases, and this variation in the cathode electric potential Vs is tracked. On the other hand, the sample and hold circuit <NUM> holds the cathode electric potential Vs in the case of the low-level delayed signal SW'. The delayed signal SW' falls at the timing T12. Therefore, the electric potential at the timing T12 is held in a way similar to the first embodiment.

Note that, the first to fifth modifications of the first embodiment are applicable to the second embodiment.

As described above, in the second embodiment of the present technology, the buffer <NUM> is omitted. Therefore, it is possible to reduce power consumption and shorten the response time in comparison with the case where the buffers are provided at two stages.

In the second embodiment described above, the buffer <NUM> outputs a single-ended signal. However, if the number of monitor pixels <NUM> increases and therefore signal lines that transmit the single-ended signals have longer wire lengths, wiring resistance increases. This may result in shortage of a driving force of the buffer <NUM>. A buffer <NUM> according to the modification of the second embodiment is different from of the buffer <NUM> according to the first embodiment in that the buffer <NUM> according to this modification outputs a differential signal.

<FIG> is a circuit diagram illustrating a configuration example of a monitor pixel <NUM> according to the modification of the second embodiment of the present technology. In the monitor pixel <NUM> according to the modification of the second embodiment, the timing detection circuit <NUM> further includes a D flip-flop <NUM>.

A delayed signal from the delay circuit <NUM> is input to a clock terminal of the flip-flop <NUM>. In addition, an inverted signal of the control signal RCH is input to a set terminal of the flip-flop <NUM>, and a low level is input to a reset terminal. An output terminal of the flip-flop <NUM> is connected to the sample switch <NUM> and the buffer <NUM>.

<FIG> is a circuit diagram illustrating a configuration example of the buffer <NUM> according to the modification of the second embodiment of the present technology. The buffer <NUM> according to the modification of the second embodiment is different from the buffer <NUM> according to the second embodiment in that the buffer <NUM> according to this modification further includes an electric current source <NUM> and pMOS transistors <NUM> and <NUM>.

The electric current source <NUM> and the pMOS transistors <NUM> and <NUM> are connected in series between a power source electric potential and a ground electric potential. In addition, gates of the pMOS transistors <NUM> and <NUM> are connected in common to the timing detection circuit <NUM>. In addition, a gate of the pMOS transistor <NUM> is connected to the sample switch <NUM>, and a gate of the pMOS transistor <NUM> is connected to the ground electric potential.

A connection node between the pMOS transistors <NUM> and <NUM> and a connection node between the pMOS transistors <NUM> and <NUM> are connected to the control section <NUM> via the signal lines <NUM> and <NUM>.

The configuration exemplified in <FIG> allows the buffer <NUM> to generate a differential signal on the basis of the holding potential Vs_SH and output the generated differential signal to the control section <NUM>.

As described above, according to the modification of the second embodiment of the present technology, the buffer <NUM> outputs the differential signal. This makes it possible to obtain a more accurate output value than the case of outputting a single-ended signal.

The technology according to an embodiment of the present disclosure (the present technology) can be applied to various products. For example, the technology according to an embodiment of the present disclosure may be realized as an apparatus mounted on any kind of mobile object such as vehicle, electric vehicle, hybrid vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, or robot.

The vehicle control system <NUM> includes a plurality of electronic control units connected to each other via a communication network <NUM>. In the example depicted in <FIG>, the vehicle control system <NUM> includes a driving system control unit <NUM>, a body system control unit <NUM>, an outside-vehicle information detecting unit <NUM>, an in-vehicle information detecting unit <NUM>, and an integrated control unit <NUM>. In addition, a microcomputer <NUM>, a sound/image output section <NUM>, and a vehicle-mounted network interface (I/F) <NUM> are illustrated as a functional configuration of the integrated control unit <NUM>.

The outside-vehicle information detecting unit <NUM> detects information about the outside of the vehicle including the vehicle control system <NUM>. For example, the outside-vehicle information detecting unit <NUM> is connected with an imaging section <NUM>. The outside-vehicle information detecting unit <NUM> makes the imaging section <NUM> image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit <NUM> may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section <NUM> is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section <NUM> can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section <NUM> may be visible light, or may be invisible light such as infrared rays or the like.

In addition, the microcomputer <NUM> can output a control command to the body system control unit <NUM> on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit <NUM>. For example, the microcomputer <NUM> can perform cooperative control intended to prevent (or alternatively, reduce) glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit <NUM>.

The sound/image output section <NUM> transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of <FIG>, an audio speaker <NUM>, a display section <NUM>, and an instrument panel <NUM> are illustrated as the output device. The display section <NUM> may, for example, include at least one of an on-board display and a head-up display.

The imaging sections <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle <NUM> as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section <NUM> provided to the front nose and the imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle <NUM>. The imaging sections <NUM> and <NUM> provided to the sideview mirrors obtain mainly an image of the sides of the vehicle <NUM>. The imaging section <NUM> provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle <NUM>. The imaging section <NUM> provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally, <FIG> depicts an example of photographing ranges of the imaging sections <NUM> to <NUM>. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the front nose. Imaging ranges <NUM> and <NUM> respectively represent the imaging ranges of the imaging sections <NUM> and <NUM> provided to the sideview mirrors. An imaging range <NUM> represents the imaging range of the imaging section <NUM> provided to the rear bumper or the back door. A bird's-eye image of the vehicle <NUM> as viewed from above is obtained by superimposing image data imaged by the imaging sections <NUM> to <NUM>, for example.

At least one of the imaging sections <NUM> to <NUM> may have a function of obtaining distance information. For example, at least one of the imaging sections <NUM> to <NUM> may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer <NUM> can determine a distance to each three-dimensional object within the imaging ranges <NUM> to <NUM> and a temporal change in the distance (relative speed with respect to the vehicle <NUM>) on the basis of the distance information obtained from the imaging sections <NUM> to <NUM>, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle <NUM> and which travels in substantially the same direction as the vehicle <NUM> at a predetermined speed (for example, equal to or more than <NUM>/hour). Further, the microcomputer <NUM> can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

An example of a vehicle control system to which the technology according to an embodiment of the present disclosure can be applied, has been described above. The technology according to an embodiment of the present disclosure can be applied to the outside-vehicle information detecting unit <NUM> from among the configuration described above. Specifically, it is possible to apply the ranging module <NUM> of <FIG> to the outside-vehicle information detecting unit <NUM>. The application of the technology according to an embodiment of the present disclosure to the outside-vehicle information detecting unit <NUM> makes it possible to suppress variation in the excess bias caused by decrease or increase in the amount of light and to acquire accurate distance information.

Claim 1:
A light detecting device (<NUM>), comprising:
first pixel circuitry (<NUM>) including a first avalanche photodiode (<NUM>);
second pixel circuitry (<NUM>) including:
a second avalanche photodiode (<NUM>); and
a control circuit (<NUM>);
characterised in that
the second pixel circuitry (<NUM>) includes:
a first delay circuit (<NUM>) including an input coupled to a cathode of the second avalanche photodiode (<NUM>), the first delay circuit (<NUM>) being configured to detect a timing at which a predetermined period of time has elapsed since a cathode electric potential of the second avalanche photodiode (<NUM>) started to decrease from a power source electric potential (VE);
a first circuit (<NUM>) including a first input coupled to the cathode of the second avalanche photodiode (<NUM>), a second input coupled to an output of the first delay circuit (<NUM>), and a holding circuit (<NUM>) including a switch (<NUM>) and a capacitance (<NUM>), the first circuit (<NUM>) being configured to capture and hold the cathode electric potential of the second avalanche photodiode (<NUM>) as a holding potential (Vs_SH<NUM>) on the basis of the timing detected by the first delay circuit (<NUM>); and
the control circuit (<NUM>) includes:
a time averaging circuit (<NUM>) including an input coupled to an output of the first circuit (<NUM>) and configured to output a time-averaged signal based on the output (Vs_SH<NUM>) of the first circuit (<NUM>); and
a potential controller (<NUM>) coupled to the anode of the first avalanche photodiode (<NUM>), the potential controller (<NUM>) being configured to control the potential of the anode of the first avalanche photodiode (<NUM>) to be lower as the time-averaged signal rises, and configured to control the potential of the anode of the first avalanche photodiode (<NUM>) to be higher as the time-averaged signal lowers.