Patent Description:
The present disclosure generally relates to systems and methods of power distribution control.

Advances in technology have resulted in smaller and more powerful personal computing devices. For example, a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular (analog and digital) telephones and IP telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can include a web interface that can be used to access the Internet. As such, these wireless telephones include significant computing capabilities.

As the demand for new high performance features increases in portables systems, system level power management has become increasingly important in order to reduce power consumption and prolong battery life. Reducing power consumption of digital processes in portable electronic devices can improve the battery live and increase the available power budget for other features, such as color displays and backlighting, for example. To reduce power consumption, circuit designers have adopted various power management techniques.

A typical integrated circuit includes a substrate, which may include a plurality of embedded circuit structures, as well as one or more integrated circuit devices that are electrically coupled to the substrate. To reduce power consumption by such embedded circuit structures, one technique uses a plurality of power regulators to generate a plurality of power supplies, which may be utilized to satisfy power requirements of the various embedded circuit structures. Since at least one of the embedded circuit structures may use less power than others, a lower power supply may be provided to that structure, thereby conserving power in the overall power budget for other components. However, high voltage regulators consume a large amount of chip area.

Another technique to reduce power consumption involves switching power supplies to disable power to an embedded circuit structure when power is not needed. However, as semiconductor fabrication technologies achieve smaller and smaller devices, high voltage switches may be difficult to scale. Moreover, such switches contribute to layout and routing complexity.

Accordingly, it would be advantageous to provide an improved power distribution system and method that reduces power loss. Relatedly, document <CIT> describes embedded power supplies, especially for ultra-large scale integrated circuits (ICs).

Embodiments and aspects that do not fall within the scope of the claims are merely examples used for explanation of the invention.

One particular advantage provided by embodiments of the power manager integrated circuit is that semiconductor manufacturing processes may be utilized in conjunction with a viable, high voltage transistor device to limit current leakage. In one particular embodiment, the power manager integrated circuit may be fabricated using an older, lower cost semiconductor manufacturing technology and may be utilized to supply power to a circuit device produced with newer and/or more expensive semiconductor manufacturing technologies.

Another particular advantage is provided by embodiments of the power manager integrated circuit in that the power manager integrated circuit substantially reduces a leakage current of an electronic device to a current level of less than approximately <NUM> nanoamperes, when a head switch is disabled.

Yet another particular advantage is that a single regulator may be utilized within a power manager integrated circuit to provide a regulated power supply to a plurality of power domains of an integrated circuit device. One particular advantage of the single regulator is that costs of the power manager integrated circuit are reduced. Moreover, the single regulator of the power manager integrated circuit allows the state of the electronic device to be retained via a single power domain.

Still another advantage of a particular embodiment of a power manager integrated circuit coupled to an integrated circuit device is that leakage gating resources are not needed in the integrated circuit device to prevent current leakage. By eliminating the need for such gating resources, it may be possible to reduce the area and complexity of power routing of the integrated circuit device during an integrated circuit design process.

Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.

The aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:.

<FIG> is a block diagram of an illustrative example of an electronic device <NUM> not covered by the subject-matter of the claims including a particular example of a power manager integrated circuit (PMIC) <NUM> and an integrated circuit device <NUM>. The integrated circuit device <NUM> may include multiple power domains, such as a first power domain <NUM> and a second power domain <NUM>. The power manager integrated circuit <NUM> may include a switching regulator <NUM>, logic <NUM>, a transistor (switch) <NUM>, a first pin <NUM> and a second pin <NUM>. The switching regulator <NUM> is coupled to the first pin <NUM> and is coupled to the second pin <NUM> via the switch <NUM>. The switch <NUM> may be a metal oxide semiconductor field effect transistor (MOSFET), a field effect transistor (FET), a bipolar junction transistor, or another circuit device that may be controlled by logic <NUM> to selectively enable and disable current flow to the second pin <NUM>. In general, the switch <NUM> may be an n-channel MOSFET or a p-channel MOSFET device in the PMIC technology. If the switch <NUM> is an n-channel MOSFET device, then the switching regulator <NUM> may be at a larger voltage potential than the integrated circuit device <NUM>.

The switch <NUM> includes a first terminal <NUM> coupled to the first pin <NUM>, a control terminal <NUM> coupled to the logic <NUM>, and a second terminal <NUM> coupled to the second pin <NUM>. The first pin <NUM> may be coupled to the first power domain <NUM> of the integrated circuit device <NUM>, and the second pin <NUM> may be coupled to the second power domain <NUM> of the integrated circuit device <NUM>. A third pin <NUM> may provide a ground connection to the PMIC <NUM> for the first power domain and the second power domain.

In a normal operating mode, the switching regulator <NUM> provides a regulated power supply to the first pin <NUM>. The logic <NUM> may activate the switch <NUM> via the control terminal <NUM> to provide at least a portion of the regulated power supply to the second pin <NUM>. During a shut off event or a low power event, or during other power saving modes of operation, the logic <NUM> may selectively deactivate the switch <NUM> to substantially reduce current flow to the second pin <NUM>. By reducing current flow to the second pin <NUM>, the logic <NUM> substantially reduces current flow to the second power domain <NUM> of the integrated circuit device <NUM>. In a particular embodiment, the switching regulator <NUM> may continue to deliver power to the first pin <NUM> and to the first power domain <NUM> after current flow to the second pin <NUM> is reduced. Thus, the switching regulator <NUM> may be utilized to selectively provide power to the second power domain <NUM> of the integrated circuit device <NUM>.

In general, it should be understood that random access memory (RAM), such as synchronous dynamic random access memory (SDRAM) and other memory components account for a significant amount of static power consumption. For example, a <NUM> Mbit SDRAM (such as that produced by Elpida Memory, Inc. of Japan) may consume as much as <NUM> microamperes at <NUM> volts during normal operations or approximately <NUM>×<NUM>-<NUM> milliwatts per bit. An SDRAM that consumes <NUM>. 02pA per bit at <NUM> volts consumes approximately <NUM> picowatts per bit. By utilizing the PMIC <NUM> to selectively turn off power to the second power domain <NUM> of the integrated circuit device <NUM>, which may include an SDRAM device, power consumption for the circuit device <NUM> may be reduced. By utilizing a single switching regulator, such as the switching regulator <NUM>, to produce the regulated power supply, it is possible to deliver a consistent power supply to one power domain, such as the first power domain <NUM>, allowing state information to be retained in a memory location within the first power domain <NUM>, while significantly reducing power to other power domains of the integrated circuit device <NUM>, such as the second power domain <NUM>.

<FIG> is a block diagram of an alternative illustrative example of an electronic device <NUM> not covered by the subject-matter of the claims including a particular example of a power manager integrated circuit (PMIC) <NUM> and an integrated circuit device <NUM>. The electronic device <NUM> includes a PMIC <NUM> arranged in foot-switch configuration. In particular, the integrated circuit device <NUM> may include multiple power domains, such as the first power domain <NUM> and the second power domain <NUM>. The power manager integrated circuit <NUM> may include a switching regulator <NUM>, logic <NUM>, a transistor (switch) <NUM>, a first pin <NUM>, a second pin <NUM>, and a third pin <NUM>. The switching regulator <NUM> is coupled to the first power domain <NUM> and the second power domain <NUM> via the first pin <NUM>. The switch <NUM> includes a first terminal <NUM> that is coupled to the second power domain <NUM> via the second pin <NUM>. The switch <NUM> also includes a control terminal <NUM> that is coupled to the logic <NUM> and a second terminal <NUM> coupled to the logic <NUM> and to the third pin <NUM>. The first power domain <NUM> may be coupled to the logic <NUM> via the third pin <NUM>. In operation, the PMIC <NUM> may selectively disable the second power domain <NUM> by deactivating the switch <NUM> to reduce current flow, while providing power to the first power domain <NUM> via the switching regulator <NUM>.

In general, it should be understood that while the PMIC <NUM> and the PMIC <NUM> of <FIG> and <FIG> may include more than one switch <NUM> and that the integrated circuit device <NUM> may include a plurality of power domains. In a particular example, the switches may be selectively deactivated to disable power to selected power domains of a plurality of power domains of the integrated circuit device <NUM>.

<FIG> is a diagram of an illustrative portion <NUM> of a particular example of a power manager integrated circuit (PMIC) <NUM> not covered by the subject-matter of the claims. The PMIC <NUM> includes a switching regulator, such as the switching regulator <NUM> and logic <NUM>. The switching regulator <NUM> may include a buck controller <NUM>, a first transistor <NUM>, and a second transistor <NUM>. The logic <NUM> may include a head controller <NUM>. The PMIC <NUM> may also include a third transistor <NUM>, a first pin <NUM>, a second pin <NUM>, a third pin <NUM> and a fourth pin <NUM>. The fourth pin <NUM> may be coupled to a power supply terminal, such as VDD in <FIG>.

In general, the first transistor <NUM> includes a first terminal <NUM> coupled to the fourth pin <NUM>, a control terminal <NUM> coupled to the buck regulator <NUM>, and a second terminal <NUM> coupled to the third pin <NUM>. The second transistor <NUM> includes a first terminal <NUM> coupled to the third pin <NUM>, a control terminal <NUM> coupled to the buck controller <NUM>, and a second terminal <NUM> coupled to a voltage supply terminal, which may be an electrical ground. The third transistor <NUM> includes a first terminal <NUM> coupled to the first pin <NUM>, a control terminal <NUM> coupled to the head controller <NUM>, and a second terminal <NUM> coupled to the second pin <NUM>.

An external inductor <NUM> may be coupled between the third pin <NUM> and the first pin <NUM>. A capacitor <NUM> may be coupled between the first pin <NUM> and a voltage supply terminal, which may be an electrical ground, to filter the power supply to the first power domain. A capacitor <NUM> may be coupled between the second pin <NUM> and a voltage supply terminal, which may be an electrical ground, to filter the power supply to the second power domain.

In a particular embodiment, the switching regulator <NUM> is coupled to the first pin <NUM> to provide a first regulated power supply to the first power domain and is coupled to the second pin <NUM> to provide a second regulated power supply to the second power domain via the third transistor <NUM>. The head controller <NUM> is coupled to the control terminal <NUM> of the third transistor <NUM> and to the second pin <NUM> to selectively deactivate the third transistor <NUM>, such as during a low power event. The third transistor <NUM> may be a high voltage transistor and may operate as a switch to selectively deactivate a second regulated power supply to the second power domain.

In operation, the head controller <NUM> may selectively activate the third transistor <NUM> to provide current flow to the second pin <NUM> during a normal operating mode. The head controller <NUM> may selectively deactivate the third transistor <NUM> to substantially reduce or shut off current flow to the second pin <NUM> during a low power event, such as a shut down event, an idle event, a reduced power event, or any combination thereof. In one particular embodiment, the head controller <NUM> may operate to substantially reduce leakage current via the third transistor <NUM>, for example, to a current level less than approximately <NUM> nanoamperes.

In general, the third transistor <NUM> cooperates with the head controller <NUM> to use the regulated voltage supply provided by the buck regulator (e.g. the buck controller <NUM>, the first transistor <NUM> and the second transistor <NUM>) to provide a switched power supply to the second pin <NUM> without using extra components, such as extra voltage regulators. The first pin <NUM> receives a regulated output from the buck regulator <NUM>, and the second pin <NUM> receives an unregulated output generated from the regulated output via the third transistor (head switch) <NUM>. In a particular embodiment, the third transistor <NUM> can be designed to provide a voltage drop of approximately 5mV when a 100mA load is coupled to the second pin <NUM>.

In general, a circuit design process typically includes establishing and maintaining correct circuit behavior under a variety of operating conditions, including variations in process, voltage, and temperature (PVT). Therefore, behavioral modeling of analog circuits typically includes extending the integrated circuit model to accurately represent the behavior of the integrated circuit at possible PVT values. To meet a 5mV DC loss specification, for example, the third transistor <NUM> should be designed to have an on-resistance that is small enough to maintain consistent performance at the PVT values. For example, the total loss resistance (R_loss) of the PMIC <NUM> may be written as a sum of the on-resistance (R_on), the routing resistance (R_routing), and the package resistance (R_package) as follows: <MAT> If a maximum R_loss is approximately <NUM> mohms and if R_package and R routing are approximately <NUM> mohms and <NUM> mohms, respectively, the maximum on-resistance (R_on) should be less than approximately <NUM> mohms across all PVT corners. In a particular embodiment, the on-resistance is less than approximately <NUM> mohms.

In a particular embodiment, the output voltage specification specifies a medium voltage n-channel field effect transistor (NFET) for the third transistor <NUM>. The on-resistance data of a medium voltage NFET in a Chartered <NUM> high voltage complementary metal oxide semiconductor (CMOS) process may be estimated according to the following equation: <MAT> If the on-resistance is approximately <NUM> mohms, the layout area of the third transistor may be estimated to be <NUM><NUM>. In a particular embodiment, the estimated wafer price of approximately <NUM> cents per square millimeter indicates that the silicon cost is <NUM> cents for the third switch <NUM>.

In one particular embodiment, the PMIC <NUM> and an associated integrated circuit that includes multiple power domains (such as the integrated circuit device <NUM> of <FIG>) may be manufactured using different semiconductor manufacturing technologies. For example, the PMIC <NUM> may be fabricated using a <NUM> high voltage CMOS process, while the integrated circuit device <NUM> may be manufactured using a <NUM> process. In another particular embodiment, the PMIC <NUM> may be fabricated using a <NUM> technology and the integrated circuit device may be fabricated using a <NUM> technology (e.g. the PMIC <NUM> may be fabricated using an older fabrication technology, while the integrated circuit device, such as the integrated circuit device <NUM> of <FIG>, may be fabricated using a newer fabrication technology).

<FIG> is a diagram of a portion <NUM> of a particular illustrative example of the power manager integrated circuit (PMIC) <NUM> of <FIG> not covered by the subject-matter of the claims. The PMIC <NUM> may include the switching regulator <NUM>, the logic <NUM>, and other elements of the portion <NUM> of <FIG>, as well as a fourth transistor <NUM> arranged in parallel with the third transistor <NUM>. The fourth transistor <NUM> may include a first terminal <NUM> coupled to the first pin <NUM>, a control terminal <NUM> coupled to the control terminal <NUM> of the third transistor <NUM>, and a second terminal <NUM> coupled to the second pin <NUM>.

In operation, the fourth transistor <NUM> may reduce a voltage drop across the third transistor <NUM> during normal operation, in part, by dividing current flow between the third transistor <NUM> and the fourth transistor <NUM>. Moreover, by activating the third transistor <NUM> and the fourth transistor <NUM>, more current may flow to the second pin <NUM> than would otherwise be possible without exceeding a current rating of the third transistor <NUM>. During a low-power or shut down event, the head controller <NUM> may deactivate the third transistor <NUM> and the fourth transistor <NUM> to turn off current flow to the second pin <NUM>, and to reduce leakage. In a particular example, the leakage current may be reduced to a level that is less than approximately <NUM> nanoamperes.

<FIG> is an illustrative diagram of a particular illustrative embodiment of a portion <NUM> of a particular embodiment of a power manager integrated circuit (PMIC) <NUM>. The PMIC <NUM> includes the switching regulator <NUM> and the logic <NUM>. In this particular illustrative embodiment, the logic <NUM> includes a first low dropout regulator <NUM> and a second low dropout regulator <NUM>. As used herein, a low dropout regulator may include a voltage regulator that provides a regulated voltage supply with a low voltage drop (e.g. low power consumption). The line <NUM> couples the low dropout regulators <NUM> and <NUM> to the first pin <NUM>. The first low dropout regulator <NUM> is coupled to the second pin <NUM> to provide a second regulated power supply derived from the first regulated power supply provided to the first pin <NUM> by the switching regulator <NUM>, and the second low dropout regulator <NUM> is coupled to a fifth pin <NUM>. In this embodiment, the first pin <NUM> may be coupled to a first power domain of a circuit device (such as the integrated circuit device <NUM> of <FIG>) to provide a first regulated power supply to the first power domain. The second pin <NUM> may be coupled to a second power domain of the circuit device to provide a second regulated power supply to the second power domain. The fifth pin <NUM> may be coupled to a third power domain of a circuit device to provide a third regulated power supply to the third power domain. The logic <NUM> may include multiple low dropout regulators and may be adapted to selectively control each of the low dropout regulators to activate and deactivate a regulated power supply to an associated power domain of the integrated circuit. A capacitor <NUM> may be coupled between the fifth pin <NUM> and a voltage supply terminal, which may be an electrical ground, to filter the power supply to the third power domain.

In this approach, the switching regulator <NUM> provides the first regulated power supply to the first pin <NUM> and the low dropout regulators <NUM> and <NUM> generate second and third regulated power supplies, respectively, based on the first regulated power supply. The low dropout regulators <NUM> and <NUM> can be designed to provide power supplies that are approximately matched supplies (such as within 5mV of each other). In a particular embodiment, the first low dropout (LDO) regulator <NUM> may be approximately a 300mA LDO regulator and the second LDO regulator <NUM> may be approximately a 150mA LDO regulator. The layout area of the first LDO regulator <NUM> and the second LDO regulator <NUM> may be estimated to be approximately <NUM><NUM> and <NUM><NUM>, respectively. The total silicon cost of the two LDO regulators <NUM> and <NUM> may be approximately <NUM> cents.

In a particular embodiment, the switching regulator <NUM> may be a high voltage power regulator. The LDO regulators <NUM> and <NUM> may be lower voltage regulators, which are adapted to derive power from the switching regulator <NUM>. Thus, the LDO regulators <NUM> and <NUM> may be produced using less silicon area than the switching regulator <NUM>.

<FIG> is a block diagram of a system <NUM> including an integrated circuit device <NUM> having a plurality of power domains and including a power manager integrated circuit <NUM> according to <FIG>. The integrated circuit device <NUM> may include a plurality of power domains, including a Vcizi power domain <NUM>, a distributed power domain <NUM>, a VC1Z3 power domain <NUM>, a distributed power domain <NUM>, a Vcci power domain <NUM>, distributed power domains <NUM> and <NUM>, a VC1Z2 power domain <NUM>, a VC2Z1 power domain <NUM>, and a VCC2 power domain <NUM>. The power manager integrated circuit (PMIC) <NUM> may be adapted to provide one or more regulated power supplies to one or more of the power domains, using a single switching regulator, as shown in <FIG>. The PMIC <NUM> may provide a first regulated power supply VREG, for example, to the Vcizi power domain <NUM> via line <NUM>. The PMIC <NUM> may also provide a second power supply (Vz) to the VC1Z2 power domain <NUM> via line <NUM>, a third power supply (V<NUM>) to the VC2Z1 power domain <NUM> via line <NUM>, and a fourth power supply (V<NUM>) to the VC1Z3 power domain <NUM> via line <NUM>. The second, third and fourth power supplies (V<NUM>, V<NUM>, and V<NUM>) may be unregulated if the PMIC <NUM> includes the particular arrangement of <FIG> or may be regulated if the PMIC <NUM> includes the particular arrangement of <FIG>.

<FIG> is a flow diagram of a method of selectively disabling or substantially reducing current flow to at least one pin of a power manager integrated circuit of a system. A power supply may be received from a voltage supply terminal at a power manager integrated circuit (block <NUM>). A first regulated supply voltage is supplied to a first pin of the power manager integrated circuit (block <NUM>). When the system is in a normal operating mode (block <NUM>), a current flow is selectively enabled to the second pin, where the second pin is coupled to a second power domain of the integrated circuit device including a first power domain responsive to the first pin and the second power domain responsive to the second pin (block <NUM>). In general, the current flow may be selectively enabled by activating a transistor (such as the third transistor <NUM> of <FIG> and <FIG>) to enable current flow to the second pin. When the system in not in a normal operating mode, the current flow may be selectively disabled to the second pin, for example, when the system is in a low power or a power off mode of operation (block <NUM>). The voltage level may optionally be scaled to one of the first power domain or the second power domain (block <NUM>). In a particular embodiment, logic of the PMIC (such as logic <NUM> in <FIG>) may operate to scale a voltage level to one or more power domains of the integrated circuit device, to scale or adjust a power supply to a collapsible power domain, for example.

In a particular embodiment, the current flow may be selectively disabled by deactivating one or more transistors (e.g. the third transistor <NUM> and the fourth transistor <NUM> of <FIG>) to substantially reduce current flow to the second pin (such as the second pin <NUM> of <FIG>). In a particular embodiment, the current flow to the second pin may be reduced to a current level that is less than approximately <NUM> nanoamperes, thereby reducing power to the second power domain.

In a particular embodiment, the method may include providing the regulated power supply to the first pin to provide power to the first power domain, which may include a memory, during the low power mode to retain a state of the integrated circuit device. In a particular embodiment, the first regulated power supply and the second regulated power supply may be at different power levels. For example, the power manager integrated circuit may provide a different regulated power supply to each domain of a plurality of power domains of the integrated circuit, and each of the power supplies may be selectively deactivated.

<FIG> illustrates an exemplary, non-limiting embodiment of a portable communication device that is generally designated <NUM>. As illustrated in <FIG>, the portable communication device includes an on-chip system <NUM> that includes a processing unit <NUM>, which may be a general purpose processor, a digital signal processor, an advanced reduced instruction set machine processor, or any combination thereof. <FIG> also shows a display controller <NUM> that is coupled to the processing unit <NUM> and a display <NUM>. Moreover, an input device <NUM> is coupled to the processing unit <NUM>. As shown, a memory <NUM> is coupled to the processing unit <NUM>. Additionally, a coder/decoder (CODEC) <NUM> can be coupled to the processing unit <NUM>. A speaker <NUM> and a microphone <NUM> can be coupled to the CODEC <NUM>. In a particular embodiment, the processing unit <NUM>, the display controller <NUM>, the memory <NUM>, the CODEC <NUM>, other components, or any combination thereof may receive power via one or more pins of a power manager integrated circuit (PMIC) <NUM>, as shown in <FIG> and described herein.

<FIG> also indicates that a wireless controller <NUM> can be coupled to the processing unit <NUM> and a wireless antenna <NUM>. In a particular embodiment, a power supply <NUM> is coupled to the on-chip system <NUM>. Moreover, in a particular embodiment, as illustrated in <FIG>, the display <NUM>, the input device <NUM>, the speaker <NUM>, the microphone <NUM>, the wireless antenna <NUM>, and the power supply <NUM> are external to the on-chip system <NUM>. However, each is coupled to a component of the on-chip system <NUM>. The PMIC <NUM> may be coupled to the power supply <NUM> to receive an unregulated power supply, which the PMIC <NUM> may utilize to generate the regulated power supply and to selectively activate power to one or more power domains of an integrated circuit device, which may include one or more elements (such as the processing unit <NUM>, the wireless controller <NUM>, the memory <NUM>, the display controller <NUM> and the CODEC <NUM>).

In a particular embodiment, the processing unit <NUM> may process instructions associated with programs necessary to perform the functionality and operations needed by the various components of the portable communication device <NUM>. For example, when a wireless communication session is established via the wireless antenna a user can speak into the microphone <NUM>. Electronic signals representing the user's voice can be sent to the CODEC <NUM> to be encoded. The processing unit <NUM> can perform data processing for the CODEC <NUM> to encode the electronic signals from the microphone. Further, incoming signals received via the wireless antenna <NUM> can be sent to the CODEC <NUM> by the wireless controller <NUM> to be decoded and sent to the speaker <NUM>. The processing unit <NUM> can also perform the data processing for the CODEC <NUM> when decoding the signal received via the wireless antenna <NUM>.

Further, before, during, or after the wireless communication session, the processing unit <NUM> can process inputs that are received from the input device <NUM>. For example, during the wireless communication session, a user may be using the input device <NUM> and the display <NUM> to surf the Internet via a web browser that is embedded within the memory <NUM> of the portable communication device <NUM>.

Referring to <FIG>, an exemplary, non-limiting embodiment of a wireless telephone is shown and is generally designated <NUM>. As shown, the wireless telephone <NUM> includes an on-chip system <NUM> that includes a digital baseband processor <NUM> and an analog baseband processor <NUM> that are coupled together. The wireless telephone <NUM> may alternatively include a general-purpose processor that is adapted to execute processor readable instructions to perform digital or analog signal processing, as well as other operations. In a particular embodiment, a general-purpose processor (not shown) may be included in addition to the digital baseband processor <NUM> and the analog baseband processor <NUM> to execute processor readable instructions. As illustrated in <FIG>, a display controller <NUM> and a touchscreen controller <NUM> are coupled to the digital baseband processor <NUM>. In turn, a touchscreen display <NUM> external to the on-chip system <NUM> is coupled to the display controller <NUM> and to the touchscreen controller <NUM>. In a particular embodiment, the digital baseband processor <NUM>, the analog baseband processor <NUM>, the display controller <NUM>, the touchscreen controller <NUM>, other components, or any combination thereof may receive power from a power manager integrated circuit (PMIC) <NUM>, such as the PMIC devices shown in <FIG> and described herein.

<FIG> further indicates that a video encoder <NUM>, e.g., a phase alternating line (PAL) encoder, a sequential couleur avec memoire (SECAM) encoder, or a national television system(s) committee (NTSC) encoder, is coupled to the digital baseband processor <NUM>. Further, a video amplifier <NUM> is coupled to the video encoder <NUM> and to the touchscreen display <NUM>. Also, a video port <NUM> is coupled to the video amplifier <NUM>. As depicted in <FIG>, a universal serial bus (USB) controller <NUM> is coupled to the digital baseband processor <NUM>. Also, a USB port <NUM> is coupled to the USB controller <NUM>. A memory <NUM> and a subscriber identity module (SIM) card <NUM> can also be coupled to the digital baseband processor <NUM>. Further, as shown in <FIG>, a digital camera <NUM> can be coupled to the digital baseband processor <NUM>. In an exemplary embodiment, the digital camera <NUM> is a charge-coupled device (CCD) camera or a complementary metal-oxide semiconductor (CMOS) camera.

As further illustrated in <FIG>, a stereo audio CODEC <NUM> can be coupled to the analog baseband processor <NUM>. Moreover, an audio amplifier <NUM> can coupled to the to the stereo audio CODEC <NUM>. In an exemplary embodiment, a first stereo speaker <NUM> and a second stereo speaker <NUM> are coupled to the audio amplifier <NUM>. <FIG> shows that a microphone amplifier <NUM> can be also coupled to the stereo audio CODEC <NUM>. Additionally, a microphone <NUM> can be coupled to the microphone amplifier <NUM>. In a particular embodiment, a frequency modulation (FM) radio tuner <NUM> can be coupled to the stereo audio CODEC <NUM>. Also, an FM antenna <NUM> is coupled to the FM radio tuner <NUM>. Further, stereo headphones <NUM> can be coupled to the stereo audio CODEC <NUM>.

<FIG> further indicates that a radio frequency (RF) transceiver <NUM> can be coupled to the analog baseband processor <NUM>. An RF switch <NUM> can be coupled to the RF transceiver <NUM> and to an RF antenna <NUM>. As shown in <FIG>, a keypad <NUM> can be coupled to the analog baseband processor <NUM>. Also, a mono headset with a microphone <NUM> can be coupled to the analog baseband processor <NUM>. Further, a vibrator device <NUM> can be coupled to the analog baseband processor <NUM>. <FIG> also shows that a power supply <NUM> can be coupled to the on-chip system <NUM>. In a particular embodiment, the power supply <NUM> is a direct current (DC) power supply that provides power to the various components of the wireless telephone <NUM> that require power. Further, in a particular embodiment, the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source. The PMIC <NUM> may be coupled to the power supply <NUM> to receive an unregulated power supply, which the PMIC <NUM> may utilize to generate a regulated power supply. The PMIC <NUM> may provide the regulated power supply to one or more power domains of an integrated circuit device, which may include one or more elements (such as the display controller <NUM>, the digital signal processor <NUM>, the USB controller <NUM>, the touchscreen controller <NUM>, the video amplifier <NUM>, the PAL/SECAM/NTSC encoder <NUM>, the memory <NUM>, the SIM card <NUM>, the audio amplifier <NUM>, the microphone amplifier <NUM>, the FM radio tuner <NUM>, the stereo audio CODEC <NUM>, the analog baseband processor <NUM>, and the RF transceiver <NUM>). A power domain of the integrated circuit device may include one or more of the elements. The power control unit <NUM> may selectively activate power to one or more of the power domains, as described above with respect to <FIG>.

In a particular embodiment, as depicted in <FIG>, the touchscreen display <NUM>, the video port <NUM>, the USB port <NUM>, the camera <NUM>, the first stereo speaker <NUM>, the second stereo speaker <NUM>, the microphone <NUM>, the FM antenna <NUM>, the stereo headphones <NUM>, the RF switch <NUM>, the RF antenna <NUM>, the keypad <NUM>, the mono headset <NUM>, the vibrator <NUM>, and the power supply <NUM> are external to the on-chip system <NUM>.

Referring to <FIG>, an exemplary, non-limiting embodiment of a wireless Internet protocol (IP) telephone is shown and is generally designated <NUM>. As shown, the wireless IP telephone <NUM> includes an on-chip system <NUM> that includes a processing unit <NUM>. The processing unit <NUM> may be a digital signal processor, a general purpose processor, an advanced reduced instruction set computing machine processor, an analog signal processor, a processor to execute processor readable instruction sets, or any combination thereof. As illustrated in <FIG>, a display controller <NUM> is coupled to the processing unit <NUM> and a display <NUM> is coupled to the display controller <NUM>. In a particular embodiment, the display <NUM> is a liquid crystal display (LCD). A keypad <NUM> can be coupled to the processing unit <NUM>. In a particular embodiment, the processing unit <NUM>, the display controller <NUM>, other components, or any combination thereof may receive power via a power manager integrated circuit (PMIC) <NUM>, such as that shown in <FIG> and described herein.

As further depicted in <FIG>, a flash memory <NUM> can be coupled to the processing unit <NUM>. A synchronous dynamic random access memory (SDRAM) <NUM>, a static random access memory (SRAM) <NUM>, and an electrically erasable programmable read only memory (EEPROM) <NUM> can also be coupled to the processing unit <NUM>. <FIG> also shows that a light emitting diode (LED) <NUM> can be coupled to the processing unit <NUM>. Additionally, in a particular embodiment, a voice CODEC <NUM> can be coupled to the processing unit <NUM>. An amplifier <NUM> can be coupled to the voice CODEC <NUM> and a mono speaker <NUM> can be coupled to the amplifier <NUM>. <FIG> further indicates that a mono headset <NUM> can also be coupled to the voice CODEC <NUM>. In a particular embodiment, the mono headset <NUM> includes a microphone.

<FIG> also illustrates that a wireless local area network (WLAN) baseband processor <NUM> can be coupled to the processing unit <NUM>. An RF transceiver <NUM> can be coupled to the WLAN baseband processor <NUM> and an RF antenna <NUM> can be coupled to the RF transceiver <NUM>. In a particular embodiment, a Bluetooth controller <NUM> can also be coupled to the processing unit <NUM> and a Bluetooth antenna <NUM> can be coupled to the controller <NUM>. A USB port <NUM> may be coupled to the processing unit <NUM>. Moreover, a power supply <NUM> is coupled to the on-chip system <NUM> and provides power to the various components of the wireless IP telephone <NUM> via the PMIC <NUM>.

In a particular embodiment, as indicated in <FIG>, the display <NUM>, the keypad <NUM>, the LED <NUM>, the mono speaker <NUM>, the mono headset <NUM>, the RF antenna <NUM>, the Bluetooth antenna <NUM>, the USB port <NUM>, and the power supply <NUM> are external to the on-chip system <NUM>. However, each of these components is coupled to one or more components of the on-chip system <NUM>. The wireless VoIP device <NUM> includes the PMIC <NUM>, which may be coupled to the power supply <NUM> to receive an unregulated power supply, which the PMIC <NUM> may utilize to generate the regulated power supply. If the on-chip system <NUM> includes a plurality of power domains, the PMIC <NUM> may selectively provide the regulated power supply to one or more of the plurality of power domains of the on-chip system. A power domain of the on-chip system <NUM> may include one or more elements, such as the display controller <NUM>, the amplifier <NUM>, the voice CODEC <NUM>, the processing unit <NUM>, the flash memory <NUM>, the SDRAM <NUM>, the SRAM <NUM>, the EEPROM <NUM>, the RF transceiver <NUM>, WLAN MAC baseband processor <NUM>, and the Bluetooth controller <NUM>. The power control unit <NUM> may selectively activate power to one or more of the power domains, as described above with respect to <FIG>.

<FIG> illustrates an exemplary, non-limiting embodiment of a portable digital assistant (PDA) that is generally designated <NUM>. As shown, the PDA <NUM> includes an on-chip system <NUM> that includes a processing unit <NUM>. As depicted in <FIG>, a touchscreen controller <NUM> and a display controller <NUM> are coupled to the processing unit <NUM>. Further, a touchscreen display <NUM> is coupled to the touchscreen controller <NUM> and to the display controller <NUM>. <FIG> also indicates that a keypad <NUM> can be coupled to the processing unit <NUM>. In a particular embodiment, the processing unit <NUM>, the touchscreen controller <NUM>, the display controller <NUM>, other components, or any combination thereof may receive power via a power manager integrated circuit (PMIC) <NUM>, as shown in <FIG> and described herein.

As further depicted in <FIG>, a flash memory <NUM> can be coupled to the processing unit <NUM>. The processing unit <NUM> may be a digital signal processor (DSP), a general purpose processor, an advanced reduced instruction set computing machine, an analog signal processor, a processor adapted to execute processor readable instruction sets, or any combination thereof. Also, a read only memory (ROM) <NUM>, a dynamic random access memory (DRAM) <NUM>, and an electrically erasable programmable read only memory (EEPROM) <NUM> can be coupled to the processing unit <NUM>. <FIG> also shows that an infrared data association (IrDA) port <NUM> can be coupled to the processing unit <NUM>. Additionally, in a particular embodiment, a digital camera <NUM> can be coupled to the processing unit <NUM>.

As shown in <FIG>, in a particular embodiment, a stereo audio CODEC <NUM> can be coupled to the processing unit <NUM>. A first stereo amplifier <NUM> can be coupled to the stereo audio CODEC <NUM> and a first stereo speaker <NUM> can be coupled to the first stereo amplifier <NUM>. Additionally, a microphone amplifier <NUM> can be coupled to the stereo audio CODEC <NUM> and a microphone <NUM> can be coupled to the microphone amplifier <NUM>. <FIG> further shows that a second stereo amplifier <NUM> can be coupled to the stereo audio CODEC <NUM> and to a second stereo speaker <NUM>. In a particular embodiment, stereo headphones <NUM> can also be coupled to the stereo audio CODEC <NUM>.

<FIG> also illustrates that an <NUM> controller <NUM> can be coupled to the processing unit <NUM> and an <NUM> antenna <NUM> can be coupled to the <NUM> controller <NUM>. Moreover, a Bluetooth controller <NUM> can be coupled to the processing unit <NUM> and a Bluetooth antenna <NUM> can be coupled to the Bluetooth controller <NUM>. As depicted in <FIG>, a USB controller <NUM> can be coupled to the processing unit <NUM> and a USB port <NUM> can be coupled to the USB controller <NUM>. Additionally, a smart card <NUM>, e.g., a multimedia card (MMC) or a secure digital card (SD) can be coupled to the processing unit <NUM>. Further, as shown in <FIG>, a power supply <NUM> may be coupled to the PMIC <NUM> of the on-chip system <NUM> to provide power to the various components of the PDA <NUM>.

In a particular embodiment, as indicated in <FIG>, the display <NUM>, the keypad <NUM>, the IrDA port <NUM>, the digital camera <NUM>, the first stereo speaker <NUM>, the microphone <NUM>, the second stereo speaker <NUM>, the stereo headphones <NUM>, the <NUM> antenna <NUM>, the Bluetooth antenna <NUM>, the USB port <NUM>, and the power supply <NUM> are external to the on-chip system <NUM>. However, each of these components is coupled to one or more components on the on-chip system <NUM>. The PMIC <NUM> may be coupled to the power supply <NUM> to receive an unregulated power supply, which the PMIC <NUM> may utilize to generate the regulated power supply. The PMIC <NUM> may provide power to one or more power domains of the on-chip system <NUM>, which may include one or more elements (such as the display controller <NUM>, the touchscreen controller <NUM>, the stereo amplifier <NUM>, the microphone amplifier <NUM>, the stereo amplifier <NUM>, the processing unit <NUM>, the stereo audio CODEC <NUM>, the flash memory <NUM>, the ROM <NUM>, the DRAM <NUM>, the EEPROM <NUM>, the <NUM> controller <NUM>, the Bluetooth controller <NUM>, the USB controller <NUM>, and the smart card MMC SD <NUM>). A power domain of the on-chip system <NUM> may include one or more of these elements, and the power control unit <NUM> may selectively activate power to one or more of the power domains, as described above with respect to <FIG>.

The various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the claims.

Claim 1:
A power manager integrated circuit (<NUM>) comprising:
a buck controller (<NUM>) to produce a first regulated power supply;
a first pin (<NUM>) coupled to a first power domain (<NUM>) of an integrated circuit (<NUM>) and responsive to the buck controller (<NUM>) to provide the first regulated power supply to the first power domain (<NUM>);
a second pin (<NUM>) coupled to a second power domain (<NUM>) of the integrated circuit (<NUM>) to provide a second regulated power supply derived from the first regulated power supply to the second power domain (<NUM>); and
a head controller (<NUM>) to determine an operating mode and to selectively reduce or disable current flow to the second pin (<NUM>) when the operating mode comprises a low power mode, wherein the head controller (<NUM>) comprises:
a logic (<NUM>, <NUM>) to determine the operating mode and to provide at least one control signal; and
a low drop out regulator (<NUM>) including an input coupled to the first pin (<NUM>) and an output coupled to the second pin (<NUM>), the low drop out regulator (<NUM>) responsive to the logic (<NUM>, <NUM>) to selectively reduce current flow to the second pin (<NUM>).