Patent Description:
Packaging an integrated circuit is typically a final stage of a semiconductor device fabrication process. During packaging, a semiconductor die, which represents the core of a semiconductor device, is encased in a housing that protects the die against physical damage and corrosion. For example, semiconductor dies are commonly mounted on a copper substrate, using solder alloy reflow, conductive epoxy, etc. The mounted semiconductor die is often then encapsulated within a plastic or epoxy compound.

A discrete semiconductor is a device specified to perform an elementary electronic function and is not divisible into separate components functional in themselves. Power semiconductors are used as switches or rectifiers in power electronics. Diodes, transistors, thyristors, and rectifiers are examples of discrete power semiconductors. Discrete power semiconductors are found in a variety of different environments, from very low power systems up to very high-power systems. However, conventions discrete semiconductor device and packages suffer from lower performance and reliability, as well as decreased heat dissipation. <CIT>discloses an apparatus with a chip assembly pad, a semiconductor chip, a clip with a chip linker on the chip and a heat dissipation block on the chip linker, all but the latter encapsulated in a housing.

<CIT> discloses a similar apparatus with no heat dissipation block on the chip linker.

The following summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended as an aid in determining the scope of the claimed subject matter.

In some implementations, the current subject matter relates to a discrete semiconductor packaging structure. The structure includes a housing, a chip assembly pad being encapsulated by the housing, where the chip assembly pad may be configured for coupling to a semiconductor chip, one or more leads, at least partially encapsulated by the housing, a clip including one or more terminals and a chip linker, where the terminals may be configured for coupling to the one or more leads, and a heat dissipation block, where the chip linker is coupled between the semiconductor chip and the heat dissipation block. The heat dissipation block is configured for removing heat from the semiconductor chip during operation.

In some implementations, the current subject matter may include one or more of the following optional features. The structure may include a heatsink coupled to a first surface of the chip assembly pad. The semiconductor chip may be coupled to a second surface of the chip assembly pad, where the second surface may be opposite of the first surface. Upon coupling of the semiconductor chip to the chip assembly pad, the heatsink does not contact the semiconductor chip. The heatsink may include a flange being positioned between the heatsink and the chip assembly pad. At least a portion of the heatsink may be coupled to the housing.

In some implementations, one or more leads may include a first lead being coupled to a first terminal in one or more terminals of the clip, a second lead being coupled to a second terminal in one or more terminals of the clip, and a third lead being coupled to the chip assembly pad. The first lead and second lead may be configured to extend outside of the housing, and the third lead may be encapsulated by the housing.

In some implementations, the heat dissipation block may be manufactured from a conductive material. The conductive material may include at least one of the following: a copper, a copper alloy, a metal, a metal alloy, and any combination thereof. The heat dissipation block may have a predetermined thickness. The heat dissipation block may be configured to remove heat from the semiconductor chip at least during and after application of a load dump pulse to the semiconductor chip. The semiconductor chip may include a working area. The clip may be configured to be coupled to the semiconductor chip working area. The heat dissipation block may be configured to be positioned over the working area of the semiconductor chip.

In some implementations, one or more clip terminals may be configured to include one or more support protrusions extending laterally away from one or more edges of the one or more clip terminals. The clip may be configured to have a curved structure, where at least a portion of the curved structure of the clip may be configured to extend away from the semiconductor chip.

In some implementations, the chip assembly pad may include a moisture groove for removing moisture from the semiconductor chip during operation.

In some implementations, the housing may be manufactured from at least one of the following: an epoxy compound, a plastic, and any combination thereof.

In some implementations, the structure may include a transient voltage suppression device.

In some implementations, the current subject matter relates to a method of manufacturing the above structure. The method includes providing a semiconductor chip;
forming a heatsink having a flange for positioning of the semiconductor chip, the flange being formed on a top surface of the heatsink; coupling the semiconductor chip to the heatsink and the flange using a chip assembly pad, wherein the chip is configured to be positioned on a top surface of the chip assembly pad, the chip assembly pad being configured to be positioned on a top surface of the flange; forming a clip having one or more clip terminals and a chip linker, and coupling the clip to the semiconductor chip using the chip linker; forming one or more leads and coupling the one or more leads to the one or more clip terminals; positioning and coupling a heat dissipation block to a top surface of the chip linker, the heat dissipation block being configured to remove heat from the semiconductor chip during operation; and forming a housing to encapsulate the semiconductor chip, the chip assembly pad, the clip, and at least a portion of the heatsink and/or the flange, and at least a portion of the leads, where at least a portion of one or more of the leads may be configured to extend outside of the housing.

The drawings are merely representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict exemplary implementations of the current subject matter, and therefore, are not to be considered as limiting in scope. In the drawings, like numbering represents like elements.

Further, certain elements in some of the figures may be omitted, and/or illustrated not-to-scale, for illustrative clarity. Cross-sectional views may be in the form of "slices", and/or "near-sighted" cross-sectional views, omitting certain background lines otherwise visible in a "true" cross-sectional view, for illustrative clarity. Additionally, for clarity, some reference numbers may be omitted in certain drawings.

Various approaches in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, where implementations of a system and method are shown. The devices, system(s), component(s), etc., may be embodied in many different forms and are not to be construed as being limited to the example implementations set forth herein. Instead, these example implementations are provided so this disclosure will be thorough and complete, and will fully convey the scope of the current subject matter to those skilled in the art.

To address these and potentially other deficiencies of currently available solutions, one or more implementations of the current subject matter relate to methods, systems, articles of manufacture, and the like that can, among other possible advantages, provide a packaging structure for power semiconductor devices that may advantageously be configured to improve dissipation of heat during operation of such devices, as well as increase their performance and reliability.

There are many packages for housing discrete power semiconductors. TO-<NUM> (various implementations of which are available from Littelfuse, Inc. , Chicago, Illinois, USA), for example, is a semiconductor package type intended for surface mounting on printed circuit boards (PCBs). The TO-<NUM> satisfies JEDEC (Joint Electron Device Engineering Council) standards, where JEDEC is a global industry standards group for microelectronics. A package characterized by a generally rectangular-cube shape, the TO-<NUM> has a flat heat sink on its bottom side, with the leads (terminals) being bent to lie against the surface of the PCB. The TO-<NUM> package also has a large thermal plane in its bottom surface, for connection, along with the leads, to the PCB.

One development direction for discrete power semiconductor packages is higher reliability, especially for automotive and aviation products. Some existing TO-<NUM> packages are designed for commercial applications, such as, for example, automotive and aviation applications. The packages may be used for providing passenger safety, power management and subsystem protection that can prevent downstream damage from high energy transient pulses. Such high-energy transient pulses may be referred to as load-dump pulses. Some transient voltage suppressor (TVS) devices may be applied to mitigate damages from the load-dump pules. TO-<NUM> may be surface-mounted and may include TVS devices (e.g., in automotive applications). However, existing TO-<NUM> packages are unable to meet high speed dissipation requirements.

Transient voltage suppressor (TVS) semiconductor devices may be used to protect electronic components from transient voltages, overvoltage, etc. A TVS chip typically serves as a core part for a TVS semiconductor device. As can be understood, any other types of semiconductor chips and/or devices may be used. <FIG> illustrates an exemplary semiconductor chip <NUM>. In particular, <FIG> illustrates a top view of the semiconductor chip <NUM>.

As shown in <FIG>, the semiconductor chip <NUM> may include a chip top portion <NUM>, which may include a chip middle portion and/or working area <NUM>, and a chip border and/or protection area <NUM>. The chip middle portion <NUM> may be enclosed by the chip border/protection area <NUM>.

The chip <NUM> may be used in various electronics applications, such as, for example, automotive devices/systems, aviation devices/systems, multi-point data transmission devices, systems, etc., where the chip <NUM> may be configured as a TVS semiconductor device and/or any other type of semiconductor device. The chip <NUM> may be used to protect against voltage transients that may be detrimental to operation of various electronic components.

Voltage transients are defined as short duration surges of electrical energy and are the result of the sudden release of energy previously stored and/or induced by other means, such as, for example, heavy inductive loads, lightning, etc. Voltage transients may be classified into predictable or repeatable transients and random transients. In electrical or electronic circuits, this energy can be released in a predictable manner via controlled switching actions, or randomly induced into a circuit from external sources. Repeatable transients are frequently caused by the operation of motors, generators, and/or the switching of reactive circuit components. On the other hand, random transients are often caused by electrostatic discharge (ESD) and lightning, which generally occur unpredictably.

ESD is characterized by very fast rise times and very high peak voltages and currents, which may be the result of an imbalance of positive and negative charges between objects. ESD that is generated by everyday activities can surpass a vulnerability threshold of standard semiconductor technologies. In case of lightning, even though a direct strike is destructive, voltage transients induced by lightning are not the result of a direct strike. When a lightning strike occurs, the event can generate a magnetic field, which, in turn, can induce voltage transients of large magnitude in nearby electrical cables. For example, a cloud-to-cloud strike will affect not only overhead cables, but also buried cables. Even a strike <NUM> mile distant (<NUM>) can generate <NUM> volts in electrical cables. In a cloud-to-ground strike, the voltage transient generating effect is significantly greater.

In some cases, TVS chips may be packaged using surface mounting packaging, which provides for high power while having an overall small size. For example, SMC packaging may be used in printed circuit boards (PCBs) to protect various electronic components from ESD, electrical fast transients (EFT), lightning, and/or any other transients. SMC packaging allows for surface mounting of electronic components as well as optimization of the space on the PCB (on which such components may be mounted). It may further be characterized by a small profile, improved clamping capability, as well as other enhanced features.

In some implementations, the current subject matter may be configured to provide a high-reliability and performance discrete power semiconductor package or structure that may be configured to include a semiconductor chip mounted on a chip mounting pad positioned above a flange incorporated into a heatsink. This may allow for an improved moisture removal capabilities. The structure may also include a clip coupled to one or more leads and the chip mounting pad. A conductive slug or a block (e.g., copper) or any other heat dissipation device may also be coupled (e.g., using solder) to the clip, where the clip is positioned between the conductive block and a chip linker coupled to the semiconductor chip. Use of the conductive block may be configured to improve absorption of heat from the semiconductor chip during, for example, a load-dump pulse. Further, clip may be coupled to the leads of the structure using solder, rather than, being wire-bound, which may further improve heat dissipation.

<FIG> illustrate an exemplary discrete power semiconductor structure or apparatus <NUM> for housing a semiconductor chip (as for example shown in <FIG>), according to some implementations of the current subject matter. <FIG> is a perspective view of the structure <NUM>. <FIG> is a transparent side view of the structure <NUM>. <FIG> is a transparent top view of the structure <NUM>. <FIG> is a perspective view of the structure <NUM> without an encapsulating housing. The structure <NUM> may, for instance, be a type of TO-<NUM> package. For example, the structure <NUM> may be configured to house a TVS device (e.g., similar to the one shown in <FIG>). The structure <NUM> may be configured to be suitable for either unidirectional and/or bidirectional semiconductor devices.

Referring to <FIG>, the structure <NUM> may be configured to include a housing or an encapsulation <NUM>, a semiconductor chip (e.g., discrete semiconductor chip) <NUM>, a chip mounting pad <NUM>, a flange <NUM>, a heatsink <NUM>, one or more conductive leads (terminals) <NUM>, <NUM>, <NUM>, a clip <NUM>, a chip linker <NUM>, and a heat absorption block or slug <NUM>.

The housing <NUM> is configured to house and/or encapsulate the chip <NUM>, the chip mounting pad <NUM>, the flange <NUM>, the heatsink <NUM>, at least portions of one or more conductive leads <NUM>, <NUM>, <NUM>, the chip linker <NUM>, and the heat absorption or heat dissipation block <NUM>. The leads <NUM>-<NUM> may be configured to extend from the housing <NUM> for conductively coupling to other electronic components and/or printed circuit board(s). The housing <NUM> may be configured to be manufactured from an epoxy compound, a plastic, and/or any other suitable material. In some implementations, the structure <NUM> may be configured to be positioned on a substrate and/or a printed circuit board (PCB) (not shown in <FIG>). The housing <NUM> of the structure <NUM> may be configured to provide protection to its encapsulated components from outside stress, e.g., bending, folding, etc. that may cause internal stress, breakage, cracking, etc. to the chip <NUM>. In particular, the housing <NUM> may also provide protection against mechanical stresses, moisture, dust, debris, etc..

In some implementations, on one side (e.g., bottom side as shown in <FIG>), the chip <NUM> may be configured to be coupled to the chip assembly pad <NUM>. The chip assembly pad <NUM> may then be coupled to the flange <NUM>, which in turn, may be coupled to the heatsink <NUM>. On the other side (e.g., top side of the chip, as shown in <FIG>), the chip <NUM> may be coupled to the chip linker <NUM>, which, in turn, may be coupled to the clip <NUM>. The block <NUM> may be configured to be positioned on top of the chip linker <NUM> and the clip <NUM>, where the block <NUM> may be coupled to at least one of the chip <NUM>, the chip linker <NUM> and/or the clip <NUM>. The block <NUM> may be manufactured from copper, copper alloy, metal, metal alloy, and/or any other suitable material. It, along with the heatsink <NUM>, may be used to aid in heat dissipation during operation of the structure <NUM> (such as, for example, during occurrence of load-dump pulses). The various couplings between the above components of the structure <NUM> may be accomplished using solder and/or any other desired techniques.

As stated above, the heatsink <NUM> may be configured to aid in dissipation of heat away from the semiconductor chip <NUM>. In some implementations, the heatsink <NUM> may be configured to include a heatsink front support terminal <NUM> and/or at least portions of one or more of the conductive leads (terminals) <NUM>, <NUM>, and <NUM>. The heatsink front support terminal <NUM> may be disposed on one side of the heatsink <NUM> (and thus, the structure <NUM>) and the leads <NUM>-<NUM> may be disposed on the other side, opposite of the heatsink front support terminal <NUM>.

In some implementations, the heatsink <NUM>, the two leads <NUM>, <NUM>, and the end lead <NUM> may be coupled as a unitary structure. The heatsink <NUM>, the chip assembly pad <NUM>, the heatsink front support terminal <NUM>, and the leads <NUM>-<NUM> may be formed from a single, unitary electrically conductive material, such as, for example, copper, copper alloy, metal, metal alloy, and/or any other suitable materials, and/or any combination thereof. Alternatively, or in addition, the heatsink <NUM>, the chip assembly pad <NUM>, the heatsink front support terminal <NUM>, and the leads <NUM>-<NUM> may be formed from different conductive materials, such as, for example, those listed above. The lead <NUM> may be a gate terminal; the lead <NUM> may be a process terminal; and the lead <NUM> may be an anode terminal. The lead <NUM> may be coupled to the heatsink <NUM>. The lead <NUM> and the lead <NUM> may be coupled to the clip <NUM> and may be separate from the heatsink <NUM>.

In addition to providing moisture dissipation from the chip <NUM>, the flange <NUM> and the chip assembly pad <NUM> may be configured to hold the chip <NUM> in a predetermined position within the structure <NUM>. In some example, non-limiting implementations, the chip assembly pad <NUM> may be configured to have a surface area that may be larger than the surface area (e.g., bottom surface area) of the chip <NUM>. The chip assembly pad <NUM> may be flat and/or may be elevated at its perimeter edge, thereby providing further securing (e.g., in addition to soldering) of the chip <NUM> in its location. In the latter implementation, such perimeter elevation may also be configured to provide a protective barrier around the chip <NUM>, thereby further aiding in dissipation of moisture from the chip <NUM>.

In some implementations, the clip <NUM> may include the chip linker <NUM>, a clip terminal <NUM>, and another clip terminal <NUM>. The chip linker <NUM> may be configured to be disposed over the chip <NUM>. As shown in <FIG>, the chip linker <NUM> may have a rectangular (e.g., square) shape and may be configured to be positioned over a portion of the chip <NUM>. As can be understood, the chip linker <NUM> may have any desired shape, form, thickness, and/or any other dimensions. The block <NUM> may be configured to be coupled to the top surface of the chip linker <NUM> of the clip <NUM> and the bottom surface of the chip linker <NUM> may be coupled to the chip <NUM>. The block <NUM> may have any desired shape, form, thickness and/or any other dimensions. As can be understood, dimensions of any of the components <NUM> may be so selected as to accommodate a particular implementation and/or use of the structure <NUM>.

The clip terminals <NUM>, <NUM> of the clip <NUM> may be disposed on opposite sides of the chip linker <NUM> and may be aligned for coupling to the terminals <NUM> and <NUM>. For example, the clip terminal <NUM> may be configured to be coupled to the terminal <NUM> and the clip terminal <NUM> may be configured to be coupled to the terminal <NUM>. As can be understood, any other arrangement of terminals may be possible. The chip linker <NUM>, the clip terminal <NUM>, and the clip terminal <NUM> may be configured to be formed from a single, unitary electrically conductive material, such as, for example, but not limited to, copper, copper alloy, metal, metal alloy, and any combination thereof. Alternatively, or in addition to, the chip linker <NUM>, the clip terminal <NUM>, and the clip terminal <NUM> may be configured to be formed from different materials, such as, for example, those that are listed above.

Because of the connection between the terminals <NUM> and <NUM> and the respective clip terminals <NUM> and <NUM>, the clip <NUM> may be electrically connected to the heatsink <NUM> as well as the block <NUM>. As stated above, use of the heatsink <NUM> and the block <NUM> enhances heat absorption properties of the structure <NUM>, where the block <NUM> may be configured to absorb heat from the chip <NUM> (e.g., back of the chip <NUM>) during operations, e.g., such as, during load dump pulse.

<FIG> illustrate the exemplary heatsink <NUM> of the structure <NUM>, according to some implementations of the current subject matter. In the figures, <FIG> is a top view of the heatsink <NUM>; <FIG> is a side view of the heatsink <NUM>; and <FIG> is a perspective view of the heatsink <NUM>.

As discussed above, the heatsink <NUM> may be configured to include the heatsink front support terminal <NUM>. The flange <NUM> may be configured to be positioned on top of the heatsink <NUM>. The chip assembly pad <NUM> disposed on top of the flange <NUM> and may be used for positioning of the chip <NUM> (not shown in <FIG>). The flange <NUM> may include one or more heatsink grooves <NUM> (a, b). The grooves <NUM> may be configured to be disposed on two sides of the flange <NUM> and proximal to the heatsink front support terminal <NUM>. In some exemplary implementations, the grooves <NUM> may be configured to aid during manufacturing process, such preventing deposition of various compounds between heatsink <NUM> and other components of the structure <NUM>. Moreover, the chip assembly pad <NUM> may be configured to include one or more notches <NUM>. The notches <NUM> may be disposed on a vertical side (e.g., side facing the heatsink front support terminal <NUM>) and/or any and/or all vertical sides of the chip assembly pad <NUM>. The notches <NUM> may be configured to serve as moisture removal channels that may assist in moisture dissipation during operation of the structure <NUM> (e.g., removing moisture from the chip <NUM>).

As shown in <FIG>, the leads <NUM>, <NUM>, <NUM> may be configured to have multi-curved shapes. Such shapes may be helpful for coupling/connection of the structure <NUM> to a substrate, a PCB, and/or any other component. For example, the lead <NUM> may include an external element connection portion <NUM> (for coupling to a substrate, PCB, etc., e.g., using soldering), a vertical portion <NUM> configured to extend away from the portion <NUM>, a horizontal portion <NUM> configured to lead into the housing <NUM> (not shown in <FIG>), and a curved portion <NUM> that may be configured to connect to the clip connector <NUM>. The clip connector <NUM> may be configured for connection to (e.g., using soldering) the clip terminal <NUM> of the clip <NUM>. In some exemplary implementations, the clip connector <NUM> may be configured to have a greater width than the width of the portions <NUM>, <NUM>, <NUM>, and <NUM>.

The lead <NUM> may be configured to be similar to the lead <NUM> (and may be symmetrically positioned about the lead <NUM>). The lead <NUM> may include an external element connection portion <NUM> (for coupling to a substrate, PCB, etc., e.g., using soldering), a vertical portion <NUM> extending away from the portion <NUM>, a horizontal portion <NUM> leading into the housing <NUM> (not shown in <FIG>), and a curved portion <NUM> for connecting to the clip connector <NUM>. The clip connector <NUM> may be configured to couple (e.g., using soldering) to the clip terminal <NUM> of the clip <NUM>. Similar to the clip connector <NUM>, the clip connector <NUM> may be configured to have a greater width than the width of the portions <NUM>, <NUM>, <NUM>, and <NUM>.

The lead <NUM> may be configured to have an external element connection portion <NUM>, a curved portion <NUM> and the chip assembly pad connector portion <NUM>. In some exemplary implementations, the portions <NUM>-<NUM> may be configured to have a uniform width and/or varying widths. Moreover, the portions <NUM>-<NUM> may be configured to be disposed inside the housing <NUM> (not shown in <FIG>) in their entireties. Alternatively, or in addition to, one or more of and/or parts of the portions <NUM>-<NUM> may be configured to extend outside of the housing <NUM>. The chip assembly pad <NUM> and the lead <NUM> may be configured to form a unitary structure and/or be separate structures that may be coupled together using any desired mechanisms, e.g., solder, welding, etc..

<FIG> illustrate the exemplary clip <NUM> of the structure <NUM>, according to some implementations of the current subject matter. In the figures, <FIG> is a top view of the clip <NUM>; <FIG> is a side view of the clip <NUM>; <FIG> is a perspective view of the clip <NUM>; and FIG. 2d is a back perspective view of the clip <NUM>.

As described above, the clip <NUM> may be configured to include the chip linker <NUM> and clip terminals <NUM>, <NUM>. The clip terminal <NUM> may be coupled to the chip linker <NUM> using a connector <NUM>, and the clip terminal <NUM> may be coupled to the chip linker <NUM> using a connector <NUM>. The connectors <NUM>, <NUM> may be configured to have a multi-faceted curved form that may be configured for coupling clip terminals <NUM>, <NUM> to the leads <NUM>, <NUM>, respectively. The chip linker <NUM> and the clip terminals <NUM>, <NUM> may be configured to form a unitary structure that may be manufactured from a conductive material, such as, for example, copper, copper alloy, metal, metal alloy, and/or any other suitable materials. Alternatively, or in addition, the chip linker <NUM> and the clip terminals <NUM>, <NUM> may be separate components that may be conductively coupled together (e.g., using solder).

In some implementations, the connectors <NUM>, <NUM> may have a narrower width than the width of the clip terminals <NUM>, <NUM>. Alternatively, or in addition, the connectors <NUM>, <NUM> and the clip terminals <NUM>, <NUM> may have a uniform width.

As shown in <FIG>, the clip terminal <NUM> may include protrusions <NUM>, <NUM> that may be configured to be disposed opposite one another on the clip terminal <NUM>. The protrusions <NUM>, <NUM> may be configured to extend laterally away from the edges of the clip terminal <NUM>. Similarly, the clip terminal <NUM> may include protrusions <NUM>, <NUM> that may be configured to be disposed opposite one another on the clip terminal <NUM>. The protrusions <NUM>, <NUM> may be configured to extend laterally away from the edges of the clip terminal <NUM>, where protrusion <NUM> of the clip terminal <NUM> may be configured to face the protrusion <NUM> of the clip terminal <NUM>. The protrusions <NUM>-<NUM> may be configured to aid during coupling of the terminals <NUM>, <NUM> to the leads <NUM>, <NUM>, respectively. Moreover, the protrusions <NUM>-<NUM> may further be configured for supporting positioning of various components of the structure <NUM> in the housing <NUM> during manufacturing.

As shown in <FIG>, the connector <NUM> may include a first curved portion <NUM> that be configured to be bent toward the chip linker <NUM>, a flat portion <NUM> that may include the protrusion <NUM> (and protrusion <NUM> (not shown in <FIG>)), and a clip terminal portion <NUM> that may include the clip terminal <NUM>. The clip terminal portion <NUM> may be configured to be bent for connection to the lead <NUM>. Another flat portion <NUM> may be configured to couple the connector <NUM> to the chip linker <NUM>. A curved section <NUM> may be disposed as an interlink between the flat portion <NUM> and the chip linker <NUM>. The structure of the connector <NUM> (as shown in <FIG> and <FIG>) may be similar to the structure of the connector <NUM>.

As shown in <FIG>, the multi-faceted, curved structure of the connectors <NUM>, <NUM> may allow for the chip linker <NUM> to be positioned at a lower level as compared to the clip terminals <NUM>, <NUM>. This may allow for an improved coupling of the chip <NUM> (not shown in <FIG>) to the leads <NUM>, <NUM>. It may also provide additional support during manufacturing and/or coupling of the various components of the structure <NUM>. Further, the elevated nature of the connectors <NUM>, <NUM> may also allow for positioning of the block <NUM>, whose top surface (i.e., surface that is not facing the chip <NUM>) may be level with the connectors <NUM>, <NUM>. Moreover, the elevated nature of the connectors <NUM>, <NUM> may further aid in dissipation of heat from the chip <NUM> during operation of the structure <NUM>.

The clip <NUM> may further be advantageous in that it does not require any wire-bonding of any of the components of structure <NUM>. Instead, various elements of the clip <NUM> (e.g., terminals <NUM>, <NUM>, chip linker <NUM>, etc.) may be configured to be coupled to other respective components of the structure <NUM> using solder and/or any other similar techniques. This may further reduce heat buildup, as compared to the existing wire-bonded structures.

<FIG> illustrate the block <NUM>, according to some implementations of the current subject matter. <FIG> is a perspective top view of the block <NUM> and <FIG> illustrates a top view of the block <NUM>. As shown, the block <NUM> may be configured to have a top surface <NUM> and a side wall <NUM>. The side wall <NUM> may be configured to have a predetermined height that may be selected for a specific application and/or use of the structure <NUM>. As stated above, the block <NUM> may be manufactured from any conductive material, such as, for example, copper, copper alloy, metal, metal alloy, and/or any other materials. The block <NUM> may be configured to absorb heat from the chip <NUM> during operation of the structure <NUM>.

<FIG> illustrates an exemplary process <NUM> for manufacturing and/or manufacturing a packaging structure, according to some implementations of the current subject matter. For example, the packaging structure may be used for packaging a semiconductor chip, such as, for example, a TVS device. The process <NUM> may be used for manufacturing and/or assembling the structure <NUM> shown and discussed above in connection with <FIG>.

At <NUM>, a semiconductor chip may be provided. For example, the semiconductor chip may be a power semiconductor chip, e.g., rated for <NUM> W and/or greater, and/or any other type of chip. The semiconductor chip may have any desired shape, e.g., a rectangular, non-square shape, square shape, etc. An example of such chip is chip <NUM> shown in <FIG>.

At <NUM>, a heatsink having a flange may be formed for positioning of the semiconductor chip. For example, the flange <NUM> may be formed on a top surface of the heatsink <NUM>.

At <NUM>, the semiconductor chip may be coupled to the heatsink and the flange using a chip assembly pad. As shown in <FIG>, the chip <NUM> may be positioned on a top surface of the chip assembly pad <NUM>, which in turn, may be positioned on a top surface of the flange <NUM>. Soldering may be used to as a coupling mechanism between the above components. A lead <NUM> may be coupled to the chip assembly pad <NUM>.

At <NUM>, a clip having one or more clip terminals may be formed and coupled to the chip using a chip linker (e.g., chip linker <NUM>). As shown in <FIG>, the clip <NUM> may include two clip terminals <NUM>, <NUM> that may be used for connection to the respective leads <NUM>, <NUM>.

At <NUM>, leads <NUM>, <NUM> may be formed and coupled to the respective clip terminals <NUM>, <NUM>.

At <NUM>, a conductive block (e.g., a heat dissipation device) may be positioned and coupled to a top surface of the chip linker (i.e., a surface that is opposite to a surface coupled to the chip <NUM>). As shown in <FIG>, the block <NUM> may be used as a heat dissipation mechanism to remove heat from the chip <NUM> during operation of the structure <NUM>.

At <NUM>, a housing is formed to encapsulate the semiconductor chip, the chip assembly pad, the clip, and at least a portion of the heatsink and/or the flange, and at least a portion of the leads, where at least a portion of one or more of the leads may be configured to extend outside of the housing.

The components and features of the devices described above may be implemented using any combination of discrete circuitry, application specific integrated circuits (ASICs), logic gates and/or single chip architectures. Further, the features of the devices may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware and/or software elements may be collectively or individually referred to herein as "logic" or "circuit.

It will be appreciated that the exemplary devices shown in the block diagrams described above may represent one functionally descriptive example of many potential implementations. Accordingly, division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in embodiments.

Some embodiments may be described using the expression "one embodiment" or "an embodiment" along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" (or derivatives thereof) in various places in the specification are not necessarily all referring to the same embodiment. Moreover, unless otherwise noted the features described above are recognized to be usable together in any combination. Thus, any features discussed separately may be employed in combination with each other unless it is noted that the features are incompatible with each other.

In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein," respectively. Moreover, the terms "first," "second," "third," and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects. Further, the use of "including," "comprising," or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Accordingly, the terms "including," "comprising," or "having" and variations thereof are open-ended expressions and can be used interchangeably herein.

For the sake of convenience and clarity, terms such as "top", "bottom", "upper", "lower", "vertical", "horizontal", "lateral", "transverse", "radial", "inner", "outer", "left", and "right" may be used herein to describe the relative placement and orientation of the features and components, each with respect to the geometry and orientation of other features and components appearing in the perspective, exploded perspective, and cross-sectional views provided herein. Said terminology is not intended to be limiting and includes the words specifically mentioned, derivatives therein, and words of similar import.

All directional references (e.g., proximal, distal, upper, lower, upward, downward, left, right, lateral, longitudinal, front, back, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are just used for identification purposes to aid the reader's understanding of the present disclosure, and do not create limitations, particularly as to the position, orientation, or use of this disclosure. Connection references (e.g., attached, coupled, connected, and joined) are to be construed broadly and may include intermediate members between a collection of elements and relative movement between elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and in fixed relation to each other.

Claim 1:
An apparatus (<NUM>), comprising:
a housing (<NUM>);
a chip assembly pad (<NUM>) being encapsulated by the housing (<NUM>), the chip assembly pad (<NUM>) being configured for coupling to a semiconductor chip (<NUM>);
one or more leads (<NUM>, <NUM>, <NUM>), at least partially encapsulated by the housing (<NUM>);
a clip (<NUM>) including one or more terminals (<NUM>, <NUM>) and a chip linker (<NUM>), the one or more terminals (<NUM>,<NUM>) being configured for coupling to the one or more leads (<NUM>, <NUM>, <NUM>),; and
a heat dissipation block (<NUM>), wherein the chip linker (<NUM>) being coupled between the semiconductor chip (<NUM>) and the heat dissipation block (<NUM>), the heat dissipation block (<NUM>) being configured for removing heat from the semiconductor chip (<NUM>) during operation,
wherein the housing (<NUM>) encapsulates the semiconductor chip (<NUM>), the chip assembly pad (<NUM>), the clip (<NUM>), and the heat dissipation block (<NUM>), and at least a portion of the leads (<NUM>, <NUM>, <NUM>), where at least a portion of one or more of the leads (<NUM>, <NUM>, <NUM>), may be configured to extend outside of the housing.