Patent Description:
Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), ferroelectric random-access memory (FeRAM), resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, among others.

Memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and low power consumption. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, and movie players, among other electronic devices.

Memory devices can include memory cells that can store data based on the charge level of a storage element (e.g., a capacitor). Such memory cells can be programmed to store data corresponding to a target data state by varying the charge level of the storage element (e.g., different levels of charge of the capacitor may represent different data sates). For example, sources of an electrical field or energy, such as positive or negative electrical pulses (e.g., positive or negative voltage or current pulses), can be applied to the memory cell (e.g., to the storage element of the cell) for a particular duration to program the cell to a target data state.

A memory cell can be programmed to one of a number of data states. For example, a single level memory cell (SLC) can be programmed to a targeted one of two different data states, which can be represented by the binary units <NUM> or <NUM> and can depend on whether the capacitor of the cell is charged or uncharged. As an additional example, some memory cells can be programmed to a targeted one of more than two data states (e.g., <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>). Such cells may be referred to as multi state memory cells, multiunit cells, or multilevel cells (MLCs). MLCs can provide higher density memories without increasing the number of memory cells since each cell can represent more than one digit (e.g., more than one bit).

<CIT> discloses a method of driving a passive matrix-addressable display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis. Further disclosed is a read protocol for a memory cell that includes a pre-read cycle and a read cycle. Charge detected during the pre-read cycle is stored, and this charge is then subtracted from the charge recorded during the subsequent read cycle to yield a net charge that is used to determine whether the cell has switched states.

<CIT> discloses a ferroelectric memory having capacitors composed of ferroelectric films. Further disclosed is a read operation for the ferroelectric capacitor.

<CIT> discloses methods for sensing ferroelectric memory devices and apparatus for using the same have been disclosed. Further disclosed is the sensing of a memory cell by using a reference line and a reference memory cell to mirror displacement current to a data line coupled to the memory cell.

<CIT> discloses a method for reading a memory cell in a passive-matrix addressable ferroelectric or electret memory array.

<CIT> discloses a memory that includes a ferroelectric capacitor, a charge source, and a read circuit.

The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing.

The invention is defined in independent claims <NUM> and <NUM>. Only embodiments of the description comprising all the technical features of the claims fall under the scope of protection of the claims while the remaining ones correspond to illustrative examples which are useful for the understanding of the relevant technical context. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.

Sensing memory (e.g., FeRAM memory) using current separation in accordance with the present disclosure can be faster, use less power, and/or be more reliable than previous approaches for sensing memory. For example, sensing memory using current separation in accordance with the present disclosure can increase the size of the sensing window used to distinguish between the data states of the memory as compared to sensing windows used in previous sensing approaches, which can make sense operations performed using current separation in accordance with the present disclosure more reliable (e.g., accurate) than previous sensing approaches. Further, the sensing window used to sense memory in accordance with the present disclosure can be obtained faster than sensing windows used in previous sensing approaches, which can increase the speed of sense operations performed using current separation in accordance with the present disclosure (e.g., increase the speed at which the data states can be distinguished) as compared to previous sensing approaches. Additionally, the circuitry used to sense memory in accordance with the present disclosure can include a capacitor (e.g., an amplification capacitor) that has a lower capacitance than capacitors used in previous sensing approaches, which can reduce the size and/or power consumption of the sense circuitry of the present disclosure as compared to that of previous sensing approaches.

As used herein, "a" or "an" can refer to one or more of something, and "a plurality of" can refer to more than one of such things. For example, a memory cell can refer to one or more memory cells, and a plurality of memory cells can refer to two or more memory cells. Additionally, the designators "M" and "N" as used herein, particularly with respect to reference numerals in the drawings, indicates that one or more of the particular feature so designated can be included with embodiments of the present disclosure.

<FIG> illustrates an example of a memory array <NUM> in accordance with an embodiment of the present disclosure. Memory array <NUM> can be, for example, a ferroelectric memory (e.g., FeRAM) array.

As shown in <FIG>, memory array <NUM> may include memory cells <NUM> that may be programmable to store different states. A memory cell <NUM> may include a capacitor to store a charge representative of the programmable states. For example, a charged and uncharged capacitor may respectively represent two logic states (e.g. <NUM> and <NUM>). A memory cell <NUM> may include a capacitor with a ferroelectric material, such as, for instance, an oxide material such as lead zirconate titanate (PZT) in some examples. For example, ferroelectric materials may have a non-linear relationship between an applied electric field and stored charge (e.g., in the form of a hysteresis loop, as will be further described in connection with <FIG>), and may have a spontaneous electric polarization (e.g., a non-zero polarization in the absence of an electric field). Different levels of charge of a ferroelectric capacitor may represent different logic states, for example.

As shown in <FIG>, a memory cell <NUM> may be coupled to a respective access line, such as a respective one of access lines <NUM>-<NUM> to <NUM>-M, and a respective data (e.g., digit) line, such as one of data lines <NUM>-<NUM> to <NUM>-N. For example, a memory cell <NUM> may be coupled between an access line <NUM> and a data line <NUM>. In an example, access lines <NUM> may also be referred to as word lines, and data lines <NUM> may also be referred to as bit lines. Access lines <NUM> and data lines <NUM>, for example, may be made of conductive materials, such as copper, aluminum, gold, tungsten, etc., metal alloys, other conductive materials, or the like.

In an example, memory cells <NUM> commonly coupled to an access line <NUM> may be referred to as a row of memory cells. For example, access lines <NUM> may be coupled to a row decoder (not shown in <FIG>), and data lines <NUM> may be coupled to a column decoder (not shown in <FIG>). Operations such as programming (e.g., reading) and sensing (e.g., writing) may be performed on memory cells <NUM> by activating or selecting the appropriate access line <NUM> and a data line <NUM> (e.g., by applying a voltage to the access line). Activating an access line <NUM> may electrically couple the corresponding row of memory cells <NUM> to their respective data lines <NUM>.

Although not shown in <FIG> for clarity and so as not to obscure embodiments of the present disclosure, memory array <NUM> can be included in an apparatus in the form of a memory device. As used herein, an "apparatus" can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dice, a module or modules, a device or devices, or a system or systems, for example. Further, the apparatus (e.g., memory device) may include an additional memory array(s) analogous to array <NUM>.

<FIG> illustrates an example circuit <NUM> that includes a memory cell <NUM> in accordance with an embodiment of the present disclosure. As shown in <FIG>, circuit <NUM> may include a ferroelectric memory (e.g., FeRAM) cell <NUM>, an access line <NUM>, and a data line <NUM> that may respectively be examples of a memory cell <NUM>, an access line <NUM>, and a data line <NUM>, shown in <FIG>.

As shown in <FIG>, memory cell <NUM> may include a storage element, such as a capacitor <NUM>, that may have a first plate, such as a cell plate <NUM>, and a second plate, such as a cell bottom <NUM>. Cell plate <NUM> and cell bottom <NUM> may be capacitively coupled through a ferroelectric material <NUM> positioned between them. The orientation of cell plate <NUM> and cell bottom <NUM> may be flipped without changing the operation of memory cell <NUM>.

As shown in <FIG>, circuit <NUM> may include a select device <NUM>, such as a select transistor. For example, the control gate <NUM> of select device <NUM> may be coupled to access line <NUM>. In the example of <FIG>, cell plate <NUM> may be accessed via plate line <NUM>, and cell bottom <NUM> may be accessed via data line <NUM>. For example, select device <NUM> may be used to selectively couple data line <NUM> to cell bottom <NUM> in response to access line <NUM> activating select device <NUM>. For example, capacitor <NUM> may be electrically isolated from data line <NUM> when select device <NUM> is deactivated, and capacitor <NUM> may be electrically coupled to data line <NUM> when select device <NUM> is activated. Activating select device <NUM> may be referred to as selecting memory cell <NUM>, for example.

In an example, sources of an electric field or energy, such as positive or negative electrical pulses (e.g., positive or negative voltage or current pulses), can be applied to the storage element of memory cell <NUM> (e.g., to capacitor <NUM>) for a particular duration to program the cell to a target data state. For instance, when the electric field (e.g., the electrical pulses) is applied across the ferroelectric material <NUM> of capacitor <NUM>, the dipoles of ferroelectric material <NUM> may align in the direction of the applied electric field. The dipoles may retain their alignment (e.g., polarization state) after the electric field is removed, and different logic states (e.g., <NUM> and <NUM>) may be stored as the different polarization states of the ferroelectric material <NUM>. Accordingly, memory cell <NUM> may be programmed by charging cell plate <NUM> and cell bottom <NUM>, which may apply an electric field across ferroelectric material <NUM> and place the ferroelectric material in a particular polarization state (e.g., depending on the polarity of the applied field) that may correspond to a particular data (e.g., logic) state. The data state of the memory cell may subsequently be determined (e.g., sensed) by determining which polarization state the ferroelectric material is in, as will be further described herein.

<FIG> is an example of a diagram <NUM> illustrating the relationship <NUM> between an applied electric field (e.g., voltage) and the stored charge of a memory cell (e.g., the charge discharged by the memory cell in response to the applied voltage) in accordance with an embodiment of the present disclosure. The memory cell can be, for example, a ferroelectric memory (e.g., FeRAM) cell, such as, for instance, memory cell <NUM> previously described in connection with <FIG>. As illustrated in <FIG>, this relationship <NUM> may take the form of a hysteresis loop.

When a sensing voltage is applied to the memory cell (e.g., during a sense operation being performed on the cell), current may flow through, and be output by, the memory cell in response to the sensing voltage being applied to the cell. This current, which can correspond to the amount of charge discharged by the memory cell (e.g. by the capacitor of the memory cell) while the sensing voltage is being applied to the memory cell, can be separated (e.g., divided) into two components. The first component, which may be referred to herein as the displacement or dielectric component, can correspond to the charge discharged by the memory cell as a result of the physical dimensional characteristics of the memory cell, such as the distance between the plates of the capacitor of the cell, and may be discharged almost immediately upon the sensing voltage being applied to the cell. The second component, which may be referred to herein as the polar component, can correspond to the charge discharged by the memory cell as a result of the characteristics of the ferroelectric material of the capacitor of the cell, and may be discharged with a particular delay due to the characteristics of the ferroelectric material.

For example, if the memory cell has been programmed to a first data state (e.g., <NUM>) corresponding to a first polarization state of the ferroelectric material of the memory cell, the alignment of the dipoles of the ferroelectric material of the memory cell may not change in response to the sensing voltage being applied to the cell, and accordingly the memory cell may not discharge any charge attributable to a change in the dipole alignment of the ferroelectric material (e.g., the memory cell may discharge only charge attributable to the physical dimensional characteristics of the cell). This polarization state may be referred to as a displacement state. However, if the memory cell has been programmed to a second data state (e.g., <NUM>) corresponding to a second polarization state of the ferroelectric material of the memory cell, the alignment of the dipoles of the ferroelectric material of the cell may change (e.g., switch and/or flip) in response to the sensing voltage being applied to the cell, and accordingly the cell may discharge a charge attributable to the change in the dipole alignment of the ferroelectric material in addition to (e.g., after) the charge attributable to the physical dimensional characteristics of the cell. This polarization state may be referred to as a polar state. Time t0 illustrated in <FIG> may correspond to the initial time when the sensing voltage is begun to be applied to the memory cell (e.g., the beginning of the displacement component of the discharged charge), and time t1 illustrated in <FIG> may correspond to the time when the change in the dipole alignment of the ferroelectric material of the cell may occur (e.g., the end of the displacement component and the beginning of the polar component of the discharged charge).

As such, the data state of the memory cell can be determined by separating the first current component output by the memory cell while the sensing voltage is being applied to the cell and the second current component output by the memory cell while the sensing voltage is being applied to the cell (e.g., by separating the displacement and polar components of the current). The first current component can correspond to the first (e.g., displacement) polarization state of the ferroelectric material of the cell, and the second current component can correspond to the second (e.g., polar) polarization state of the cell, as previously described herein. That is, the first current component may include the current output by the cell while the sensing voltage is being applied to the cell before a particular reference time, and the second current component may include the current output by the cell while the sensing voltage is being applied to the cell after the particular reference time, with the reference time based on (e.g., related to) the time at which a change of the polarization state (e.g., a switching of the alignment of the dipoles) of the ferroelectric material of the memory cell will occur while the sensing voltage is being applied to the memory cell if the cell has been programmed to the second data state (e.g., time t1 illustrated in <FIG>). This reference time may be, for instance, approximately ten nanoseconds after the sensing voltage has begun to be applied to the memory cell, and the sensing voltage may be (e.g. have a magnitude of), for instance, approximately <NUM> Volts.

The first and second current components can be separated, for example, by continuing to pre-charge (e.g., continuing to apply a pre-charge signal) to the data (e.g., digit) line to which the memory cell is coupled until the particular reference time has been reached while the sensing voltage is being applied to the memory cell. For instance, as part of the sense operation, the data line to which the memory cell is coupled may be pre-charged before the sensing voltage is applied to the cell (e.g., before time t0). Once the data line has been pre-charged, the sensing voltage may then be applied to the memory cell. However, while the sensing voltage is being applied to the memory cell, the pre-charge signal may continue to be applied to the data line until the particular reference time. Once the particular reference time has been reached, the pre-charge signal may be turned off, while the sensing voltage continues to be applied to the memory cell. This will enable the current output by the memory cell while the sensing voltage is being applied before the particular reference time to be separated from the current output by the memory cell while the sensing voltage is being applied after the particular reference time.

The data state of the memory cell can then be determined using only the second current component (e.g., the current output after the reference time). That is, the data state of the cell can be determined without using the first current component (e.g., the first current component can be wasted and/or eliminated from the sensing process). For example, the separation of the first and second current components can include separating the charge discharged by the memory cell corresponding to the first current component (e.g., the charge attributable to the physical dimensional characteristics of the memory cell) and the charge discharged by the memory cell corresponding to the second current component (e.g., the charge attributable to the change in dipole alignment of the ferroelectric material of the cell), and the data state of the cell can be determined using only the charge corresponding to the second current component (e.g., without using the charge corresponding to the first current component).

For example, the data state of the memory cell can be determined based on a comparison of (e.g., by comparing) a voltage amount associated with the charge discharged by the memory cell corresponding to the second current component and a reference voltage. If the comparison indicates this voltage amount is less than the reference voltage, then the memory cell has been programmed to the first data state (e.g., <NUM>); if the comparison indicates this voltage amount is greater than the reference voltage, then the memory cell has been programmed to the second data state (e.g., <NUM>). As an additional example, the data state of the memory cell can be determined based on the amount of time for which the second current component is output by the memory cell. For instance, the second current component may be exhausted sooner if the memory cell has been programmed to the second data state than if the cell has been programmed to the first data state, so the amount of time for which the second current is output by the memory cell may be shorter if the cell has been programmed to the second data state than if the cell has been programmed to the first data state. Examples of the circuitry that can be used to separate the current components output by the memory cell and determine the data state of the memory cell will be further described herein (e.g., in connection with <FIG> and <FIG>).

Determining the data state of the cell using only the second current component (e.g., without using the first current component) can increase the size of the sensing window used to distinguish between the two possible data states of the cell, which can make the determination of the data state more reliable (e.g., accurate) than in previous sensing approaches. Further, the sensing window can be obtained faster by using only the second current component, which can increase the speed at which the data state of the cell can be determined as compared to previous sensing approaches.

<FIG> illustrates an example of circuitry (e.g., sense circuitry) <NUM> for current separation for memory sensing in accordance with an embodiment of the present disclosure. Circuitry <NUM> can be coupled to, and be included in the same apparatus (e.g., memory device) as, memory array <NUM> previously described in connection with <FIG>.

For example, as illustrated in <FIG>, circuitry <NUM> can be coupled to an array that includes memory cells <NUM> that are analogous to memory cells <NUM> previously described in connection with <FIG>. For instance, as illustrated in <FIG>, memory cell <NUM> can include a storage element (e.g., capacitor) <NUM>, and a select device <NUM> coupled to an access line <NUM> and data (e.g., digit) line <NUM>, in a manner analogous to that previously described in connection with <FIG>. Although a single memory cell <NUM> is shown in <FIG> for simplicity and so as not to obscure embodiments of the present disclosure, circuitry <NUM> can be coupled to each respective memory cell of the array.

Further, although not shown in <FIG> for simplicity and so as not to obscure embodiments of the present disclosure, circuitry <NUM> and/or the memory array that includes cells <NUM> can be coupled to a controller. The controller can include, for example, control circuitry and/or logic (e.g., hardware and/or firmware), and can be included on the same physical device (e.g., the same die) as the memory array, or can be included on a separate physical device that is communicatively coupled to the physical device that includes the memory array. In an embodiment, components of the controller can be spread across multiple physical devices (e.g., some components on the same die as the array, and some components on a different die, module, or board). The controller can operate circuitry <NUM> to utilize current separation as described herein to determine the data state of memory cell <NUM>.

For example, as shown in <FIG>, circuitry <NUM> can include a capacitor <NUM>, which may be referred to herein as an amplification capacitor. Capacitor <NUM> can be coupled to memory cell <NUM> (e.g., via data line <NUM>) through cascode <NUM> and selector <NUM>, as illustrated in <FIG>. Cascode <NUM> can be, for example, an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), and selector <NUM> can be, for example, a shunt comprising a number of switches.

Cascode <NUM> can be used to apply a sensing voltage to memory cell <NUM> (e.g., data line <NUM>) during a sense operation being performed on the cell. For instance, cascode <NUM> can be used to bias memory cell <NUM> at the sensing voltage. _Further, data line <NUM> may be pre-charged (e.g., by applying a pre-charge signal thereto) before the sensing voltage is applied to memory cell <NUM>. Capacitor <NUM> illustrated in <FIG> may represent the capacitance of data line <NUM> once data line <NUM> has been pre-charged.

Once data line <NUM> has been pre-charged, the sensing voltage may then be applied to memory cell <NUM>. While the sensing voltage is being applied to memory cell <NUM>, the pre-charge signal may continue to be applied to data line <NUM> until the particular reference time previously described in connection with <FIG>; after the particular reference time, the pre-charge signal may be turned off, as previously described in connection with <FIG>. While the sensing voltage is being applied to memory cell <NUM>, capacitor <NUM> can store only the charge discharged by memory cell <NUM> (e.g., by capacitor <NUM>) that corresponds to the second (e.g., polar) current component output by memory cell <NUM> while the sensing voltage is being applied thereto (e.g., only the charge discharged after the particular reference time). That is, the charge discharged by memory cell <NUM> that corresponds to the first (e.g., displacement) current component output by memory cell <NUM> while the sensing voltage is being applied thereto (e.g., the charge discharged before the particular reference time, while data line <NUM> is continued to be pre-charged) may not be stored by capacitor <NUM> (e.g., this charge can be separated and eliminated by continuing to pre-charge data line <NUM>). An example further illustrating the discharge of the charge stored by memory cell <NUM> to capacitor <NUM> will be further described herein (e.g., in connection with <FIG>).

For instance, as shown in <FIG>, circuitry <NUM> can include a switch <NUM> coupled to capacitor <NUM>. Switch <NUM> may also be coupled to memory cell <NUM> through cascode <NUM> and selector <NUM>, as illustrated in <FIG>. Switch <NUM> can be used to separate the first current component output by memory cell <NUM> (e.g., the charge discharged by the cell before the particular reference time, while data line <NUM> continues to be pre-charged) while the sensing voltage is being applied thereto and the second current component output by memory cell <NUM> (e.g., the charge discharged by the cell after the particular reference time) while the sensing voltage is being applied thereto. For example, switch <NUM> can be enabled before the particular reference time, and disabled after the particular reference time. Only when switch <NUM> is disabled may charge discharged by memory cell <NUM> be stored by capacitor <NUM>; the charge discharged by memory cell <NUM> may be separated and eliminated by enabling switch <NUM>. Switch <NUM> can enabled, for example, by applying a signal (e.g., <NUM> Volts as illustrated in <FIG>) thereto, and then disabled by turning off the signal.

The data state of memory cell <NUM> can then be determined based on the amount of charge stored by capacitor <NUM> (e.g., based on only the charge corresponding to the second current component). This determination can be performed, for example, using latch <NUM> of circuitry <NUM>. Latch <NUM> can comprise latch circuitry, such as, for instance, a number of logic gates and/or switches, as will be appreciated by one of skill in the art.

For example, latch <NUM> can determine the data state of memory cell <NUM> based on a comparison of (e.g., by comparing) the voltage amount associated with the charge stored by capacitor <NUM> and a reference voltage (e.g., Vref illustrated in <FIG>). If the comparison indicates the voltage amount associated with the charge stored by capacitor <NUM> is less than the reference voltage, then the memory cell has been programmed to the first data state (e.g., <NUM>); if the comparison indicates the voltage amount associated with the charge stored by capacitor <NUM> is greater than the reference voltage, then the memory cell has been programmed to the second data state (e.g., <NUM>). An example of a sensing window associated with such a comparison will be further described herein (e.g., in connection with <FIG>).

Because only the charge corresponding to the second current component is stored by capacitor <NUM> for use in determining the data state of memory cell <NUM>, capacitor <NUM> can have a lower capacitance than amplification capacitors used in previous sensing approaches. Accordingly, the size and/or power consumption of circuitry <NUM> may be less than the sense circuitry used in previous sensing approaches.

<FIG> illustrates an example of a timing diagram <NUM> associated with sensing a memory cell in accordance with an embodiment of the present disclosure. The memory cell can be, for example, memory cell <NUM> previously described in connection with <FIG>.

As shown in <FIG>, timing diagram <NUM> includes waveforms <NUM> and <NUM>. Waveform <NUM> represents the charge being discharged from the memory cell to capacitor <NUM> previously described in connection with <FIG> during the sense operation if the memory cell has been programmed to the first (e.g., displacement) data state. Waveform <NUM> represents the charge being discharged from the memory cell to capacitor <NUM> during the sense operation if the memory cell has been programmed to the second (e.g., polar) data state. Time t0 illustrated in <FIG> can correspond to time t0 previously described in connection with <FIG> (e.g., the initial time when the sensing voltage of the sense operation is begun to be applied to the memory cell), and time t1 illustrated in <FIG> can correspond to time t1 (e.g., the particular reference time) previously described in connection with <FIG> (e.g., the time when the change in the dipole alignment of the ferroelectric material of the memory cell may occur if the cell has been programed to the polar data state).

As shown in <FIG>, after time t1, waveform <NUM> becomes lower than waveform <NUM>, such that there is a spacing (e.g., gap) between waveforms <NUM> and <NUM>. This spacing can correspond to the difference between the charges that will be discharged from the memory cell after time t1 depending on whether the cell has been programmed to the first or second data state, and can be used to determine the data state of the cell, as previously described herein (e.g., in connection with <FIG>).

<FIG> is an example of a diagram <NUM> illustrating a sensing window associated with sensing a memory cell in accordance with an embodiment of the present disclosure. The memory cell can be, for example, memory cell <NUM> previously described in connection with <FIG>.

As previously described in connection with <FIG>, the data state of the memory cell can be determined based on a comparison of the voltage amount associated with the charge stored by capacitor <NUM> (e.g., the charge corresponding to the polar current component output by the memory cell) and a reference voltage (e.g., Vref illustrated in <FIG>, which can correspond to Vref illustrated in <FIG>). If the comparison indicates the voltage amount associated with the charge stored by capacitor <NUM> is less than the reference voltage (e.g., is within portion <NUM>-<NUM> of the sensing window illustrated in <FIG>), then the memory cell has been programmed to the first data state (e.g., <NUM>). If the comparison indicates the voltage amount associated with the charge stored by capacitor <NUM> is greater than the reference voltage (e.g., is within portion <NUM>-<NUM> of the sensing window illustrated in <FIG>), then the memory cell has been programmed to the second data state (e.g., <NUM>). That is, the sensing window illustrated in <FIG> may be used to distinguish between the two possible data states the memory cell may have been programmed to.

Portions <NUM>-<NUM> and <NUM>-<NUM> of the sensing window illustrated in <FIG> may be larger (e.g., wider) than those of sensing windows used to distinguish between data states in previous sensing approaches. As such, utilizing the sensing window illustrated in <FIG> to determine the data state of the memory cell can result in a more reliable (e.g., accurate) determination of the data state than in previous sensing approaches.

Further, the capacitance of capacitor <NUM>, as represented by dashed line <NUM> in <FIG>, can be lower than that of amplification capacitors used in previous sensing approaches. That is, the slope of line <NUM> may be less steep than for amplification capacitors used in previous sensing approaches. As such, the size and/or power consumption of sense circuitry used in accordance with the present disclosure may be less than that of sense circuitry used in previous sensing approaches.

<FIG> illustrates an example of circuitry (e.g., sense circuitry) <NUM> for current separation for memory sensing in accordance with an embodiment of the present disclosure. Circuitry <NUM> can be coupled to, and be included in the same apparatus (e.g., memory device) as, memory array <NUM> previously described in connection with <FIG>, in a manner analogous to circuitry <NUM> previously described in connection with <FIG>. For example, as illustrated in <FIG>, circuitry <NUM> can be coupled to an array that includes memory cells <NUM> that are analogous to memory cells <NUM> previously described in connection with <FIG> (e.g., that include a storage element <NUM>, and a select device <NUM> coupled to an access line <NUM> and data line <NUM>, in a manner analogous to that previously described in connection with <FIG>).

As shown in <FIG>, circuitry <NUM> can include a capacitor (e.g., amplification capacitor) <NUM>, a cascode <NUM>, a selector <NUM>, and a latch <NUM>, which can be analogous to capacitor <NUM>, cascode <NUM>, selector <NUM>, and latch <NUM> previously described in connection with <FIG>. For example, cascode <NUM> can be used to apply a sensing voltage to memory cell <NUM>, and capacitor <NUM> can store only the charge discharged by memory cell <NUM> that corresponds to the second (e.g., polar) current component output by memory cell <NUM> while the sensing voltage is being applied thereto, in a manner analogous to that previously described in connection with <FIG>.

In the example illustrated in <FIG>, circuitry <NUM> includes a transistor <NUM> coupled to capacitor <NUM>. Transistor <NUM> may also be coupled to memory cell <NUM> through cascode <NUM> and selector <NUM>, as illustrated in <FIG>. Transistor <NUM> can be, for example, a p-channel MOSFET. Further, circuitry <NUM> can include a resistor <NUM> in parallel with transistor <NUM>, as illustrated in <FIG>. Resistor <NUM> may have a large resistance value. For instance, resistor <NUM> may be a linear resistor having a large resistance value, or may be created using a highly resistive MOS device, which may reduce the size (e.g. area) of circuitry <NUM>.

Transistor <NUM> can be used to separate the first current component output by memory cell <NUM> while the sensing voltage is being applied thereto and the second current component output by memory cell <NUM> while the sensing voltage is being applied thereto, in a manner analogous to that previously described for switch <NUM> in connection with <FIG>. For example, transistor <NUM> can be enabled before the particular reference time, and disabled after the particular reference time, in a manner analogous to that previously described for switch <NUM>.

The data state of memory cell <NUM> can then be determined based on the amount of charge stored by capacitor <NUM> (e.g., based on only the charge corresponding to the second current component). This determination can be performed, for example, using latch <NUM> of circuitry <NUM>, in a manner analogous to that previously described for latch <NUM> in connection with <FIG>.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that adaptations or variations of a number of embodiments are possible within the scope of protection conferred by the appended set of claims.

Claim 1:
A method of operating an apparatus comprising:
pre-charging a data line (<NUM>, <NUM>, <NUM>) to which a memory cell (<NUM>, <NUM>, <NUM>) having a ferroelectric capacitor (<NUM>) is coupled before applying a sensing voltage to the memory cell (<NUM>, <NUM>, <NUM>);
applying a sensing voltage to the memory cell (<NUM>, <NUM>, <NUM>); and
determining a data state of the memory cell (<NUM>, <NUM>, <NUM>) by separating a first current output by the memory cell (<NUM>, <NUM>, <NUM>) while the sensing voltage is being applied to the memory cell (<NUM>, <NUM>, <NUM>) and a second current output by the memory cell (<NUM>, <NUM>, <NUM>) by continuing to pre-charge the data line (<NUM>, <NUM>, <NUM>) to which the memory cell (<NUM>, <NUM>, <NUM>) is coupled while the sensing voltage is being applied to the memory cell (<NUM>, <NUM>, <NUM>) until a particular reference time, wherein:
separating the first current output by the memory cell (<NUM>, <NUM>, <NUM>) while the sensing voltage is being applied to the memory cell (<NUM>, <NUM>, <NUM>) and the second current output by the memory cell (<NUM>, <NUM>, <NUM>) while the sensing voltage is being applied to the memory cell (<NUM>, <NUM>, <NUM>) includes:
separating charge discharged by the memory cell (<NUM>, <NUM>, <NUM>) corresponding to the first current output by the memory cell (<NUM>, <NUM>, <NUM>) and charge discharged by the memory cell (<NUM>, <NUM>, <NUM>) corresponding to the second current output by the memory cell (<NUM>, <NUM>, <NUM>); and
storing only the charge discharged by the memory cell (<NUM>, <NUM>, <NUM>) corresponding to the second current output by the memory cell (<NUM>, <NUM>, <NUM>);
the first current output by the memory cell (<NUM>, <NUM>, <NUM>) corresponds to a displacement state of the ferroelectric capacitor (<NUM>) of the memory cell (<NUM>, <NUM>, <NUM>);
the second current output by the memory cell (<NUM>, <NUM>, <NUM>) corresponds a polar state of the ferroelectric capacitor (<NUM>) of the memory cell (<NUM>, <NUM>, <NUM>); and
the data state of the memory cell (<NUM>, <NUM>, <NUM>) is determined using only the stored charge discharged by the memory cell (<NUM>, <NUM>, <NUM>) corresponding to the second current output by the memory cell (<NUM>, <NUM>, <NUM>).