Patent Description:
The following relates generally to memory devices and more specifically to self-referencing for ferroelectric memory.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic "<NUM>" or a logic "<NUM>. " In other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored state in the memory device. To store information, the electronic device may write, or program, the state in the memory device.

Various types of memory devices exist, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., flash memory, can store data for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. A binary memory device may, for example, include a charged or discharged capacitor. A charged capacitor may, however, become discharged over time through leakage currents, resulting in the loss of the stored information. Certain features of volatile memory may offer performance advantages, such as faster read or write speeds, while features of non-volatile memory, such as the ability to store data without periodic refreshing, may be advantageous.

FeRAM may use similar device architectures as volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device. FeRAM devices may thus have improved performance compared to other non-volatile and volatile memory devices. Some FeRAM sensing schemes, however, create excessive imprinting and fatigue on the memory cell and may otherwise be inaccurate because of variations in a reference value for the sensing scheme. This may reduce the reliability of sensing operations or may reduce the useful life of the memory cell.

Document <CIT> discloses a ferroelectric integrated circuit memory that includes a memory cell having a ferroelectric capacitor, one electrode of which is connected to a bit line through a transistor and the other electrode of which is connected to a plate line. The plate line is floating at one-half Vcc when the bit line is lowered to zero volts to develop a read voltage on the plate line. A unity gain amplifier then drives a complementary plate line to the same voltage as the plate line, then the plate line and complementary plate line are connected via a transistor, and the bit line is raised to Vcc to develop a reference voltage. This operation subtracts the read voltage from the reference voltage to develop a net voltage on the complementary plate line. The voltage on the complementary plate line is applied to the output line, compared via a sense amplifier to a one-half Vcc voltage on the input line, and the sense amp then drives the input and output lines to zero and Vcc, depending on whether the developed voltage was greater or less than one-half Vcc.

The disclosure herein refers to and includes the following figures:.

Increased sensing reliability for memory cells, reductions in imprinting and fatigue, and increased memory-cell-useful-life may be realized with a sensing scheme that generates a self-reference through multiple sensing operations of a cell. A ferroelectric memory cell may be sensed multiple times to extract a series of charges. As described below, the charges may be stored with capacitors to be used in determining the stored logic state of the memory cell. The multiple sense operations may result in a reference value for the cell that is specific to the characteristics of that cell (a "self-reference"), and the cell may be written or biased to different states between sense operations, thus reducing cell imprinting and fatigue while increasing retention.

Memory cells, including FeRAM cells, within a memory array are often accessed by a word line and a digit line. Access may include writing to a cell (e.g., storing a logic state) or reading a cell (e.g., reading a stored logic state). Each cell may have a ferroelectric capacitor, or other storage component, that is used to store a logic value of the cell. A single digit line may connect many memory cells and may be connected to a sense amplifier that, when activated, may determine the stored logic state of a memory cell. To facilitate the sensing or reading of the stored logic state, the sense amplifier may generate a signal to determine, based on a series of stored charges, the logic value of the memory cell in its particular state.

In generating a signal, a number of capacitors may store a charge associated with a particular sense operation, as well as values pertaining to logic "<NUM>" and logic "<NUM>" states. These values may be referred to as reference "<NUM>" and reference "<NUM>. " The values may then be provided to the sense amplifier to be used in the determination of the stored logic state, and potentially for subsequent writing operations. For example, an activated sense amplifier may compare a first stored charge, representative of a sensed logic state, with an average of a second and third stored charges-representative of reference "<NUM>" and reference "<NUM>," respectively.

By comparing a charge associated with a sensed logic state with an average of charges associated with reference "<NUM>" and reference "<NUM>," a cell can be effectively sensed than, for example, using a static reference value or an array-wide reference value. That is, a logic value associated with a particular memory cell may be more easily determined by using the same cell as a reference in determining the logic value. For example, absent a self-reference, a reference value may sample the region in which a logic value "<NUM>" and a logic value "<NUM>" overlap. In this type of a sensing scheme, it may be difficult to determine the logic value of any one cell. However, by generating a self-reference value, a logic state of the cell may be determined by accounting for cell-specific variations or characteristics.

Features of the disclosure introduced above are further described below in the context of a memory array. Circuits, cell characteristics, and timing diagrams for memory cells and arrays that support self-references are then described. These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to self-referencing for ferroelectric memory.

<FIG> illustrates an example memory array <NUM> that supports self-referencing for ferroelectric memory in accordance with examples of the present disclosure. Memory array <NUM> may also be referred to as an electronic memory apparatus. Memory array <NUM> includes memory cells <NUM> that are programmable to store different states. Each memory cell <NUM> may be programmable to store two states, denoted as a logic "<NUM>" and a logic "<NUM>. " In some cases, memory cell <NUM> is configured to store more than two logic states. A memory cell <NUM> may include a capacitor to store a charge representative of the programmable states; for example, a charged and uncharged capacitor may represent two logic states, respectively. DRAM architectures may commonly use such a design, and the capacitor employed may include a dielectric material with linear electric polarization properties. By contrast, a ferroelectric memory cell may include a capacitor that has a ferroelectric as the dielectric material. Different levels of charge of a ferroelectric capacitor may represent different logic states. Ferroelectric materials have non-linear polarization properties; some details and advantages of a ferroelectric memory cell <NUM> are discussed below.

Operations such as reading and writing may be performed on memory cells <NUM> by activating or selecting the appropriate word line <NUM> and digit line <NUM>. Word lines <NUM> may also be referred to as access lines and digit lines <NUM> may also be referred to as bit lines. Activating or selecting a word line <NUM> or a digit line <NUM> may include applying a voltage to the respective line. Word lines <NUM> and digit lines <NUM> are made of conductive materials. For example, word lines <NUM> and digit lines <NUM> may be made of metals (such as copper, aluminum, gold, tungsten, etc.), metal alloys, other conductive materials, or the like. According to the example of <FIG>, each row of memory cells <NUM> is connected to a single word line <NUM>, and each column of memory cells <NUM> is connected to a single digit line <NUM>. Additionally, for example, each row of memory cells <NUM> and each column of memory cells <NUM> may be connected to an alternative line (e.g., a plate line). By activating one word line <NUM> and one digit line <NUM> (e.g., applying a voltage to the word line <NUM> or digit line <NUM>), a single memory cell <NUM> may be accessed at their intersection. Accessing the memory cell <NUM> may include reading or writing the memory cell <NUM>. The intersection of a word line <NUM> and digit line <NUM> may be referred to as an address of a memory cell.

In some architectures, the logic storing device of a cell, e.g., a capacitor, may be electrically isolated from the digit line by a selection component. The word line <NUM> may be connected to and may control the selection component. For example, the selection component may be a transistor and the word line <NUM> may be connected to the gate of the transistor. Activating the word line <NUM> results in an electrical connection or closed circuit between the capacitor of a memory cell <NUM> and its corresponding digit line <NUM>. The digit line may then be accessed to either read or write the memory cell <NUM>.

Accessing memory cells <NUM> may be controlled through a row decoder <NUM> and a column decoder <NUM>. In some examples, a row decoder <NUM> receives a row address from the memory controller <NUM> and activates the appropriate word line <NUM> based on the received row address. Similarly, a column decoder <NUM> receives a column address from the memory controller <NUM> and activates the appropriate digit line <NUM>. Thus, by activating a word line <NUM> and a digit line <NUM>, a memory cell <NUM> may be accessed.

Upon accessing memory cell <NUM>, it may be read, or sensed, by sense component <NUM> to determine the stored state of the memory cell <NUM>. For example, after accessing the memory cell <NUM>, the ferroelectric capacitor of memory cell <NUM> may discharge onto its corresponding digit line <NUM>. Discharging the ferroelectric capacitor may be based on biasing, or applying a voltage, to the ferroelectric capacitor. The discharging may cause a change in the voltage of the digit line <NUM>, which sense component <NUM> may compare to a reference voltage (not shown) in order to determine the stored state of the memory cell <NUM>. For example, if digit line <NUM> has a higher voltage than the reference voltage, then sense component <NUM> may determine that the stored state in memory cell <NUM> was a logic "<NUM>" and vice versa. As described herein, the charge resulting from a sense operation of a cell <NUM> may be stored in a capacitor (not shown). Sense component <NUM> may compare an average value of multiple sense operations to another sense operation in order to determine a logic value for a cell <NUM> that is based on a reference value that is specific to that cell <NUM>. Sense component <NUM> may, as described below with reference to <FIG>, use values stored in various capacitors.

Sense component <NUM> may include various transistors or amplifiers in order to detect and amplify a difference in the signals, which may be referred to as latching. Sense component <NUM> may also include one or more sense capacitors, as described with reference to <FIG>. The detected logic state of memory cell <NUM> may then be output through column decoder <NUM> as output <NUM>.

A memory cell <NUM> may be set, or written, by activating the relevant word line <NUM> and digit line <NUM>. As discussed above, activating a word line <NUM> electrically connects the corresponding row of memory cells <NUM> to their respective digit lines <NUM>. By controlling the relevant digit line <NUM> while the word line <NUM> is activated, a memory cell <NUM> may be written-i.e., a logic value may be stored in the memory cell <NUM>. Column decoder <NUM> may accept data, for example input <NUM>, to be written to the memory cells <NUM>. A ferroelectric memory cell <NUM> may be written by applying a voltage across the ferroelectric capacitor.

As described herein, a memory cell <NUM> may be sensed several times and an average of at least two sensing operations may be used as a reference for another sense operation. This type of scheme may involve a sequence of reading from and writing to the cell <NUM>. For example, a cell <NUM> may be sensed and the resulting charge stored at a capacitor (not shown). The cell may be biased to one state, sensed a second time, and the resulting charge stored at another capacitor (not shown). The cell may be biased to another state, sensed a third time, and the resulting charge stored to another capacitor (not shown). The values from the second and third sensing operations may be averaged and used as a reference value in a comparison with value of the first sensing operation to determine a logic state of the cell. This process is discussed in more detail below.

In some memory architectures, accessing the memory cell <NUM> may degrade or destroy the stored logic state and re-write or refresh operations may be performed to return the original logic state to memory cell <NUM>. In DRAM, for example, the capacitor may be partially or completely discharged during a sense operation, corrupting the stored logic state. So the logic state may be re-written after a sense operation. Additionally, activating a single word line <NUM> may result in the discharge of all memory cells in the row; thus, several or all memory cells <NUM> in the row may need to be re-written.

Some memory architectures, including DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may become discharged over time through leakage currents, resulting in the loss of the stored information. The refresh rate of these so-called volatile memory devices may be relatively high, e.g., tens of refresh operations per second for DRAM arrays, which may result in significant power consumption. With increasingly larger memory arrays, increased power consumption may inhibit the deployment or operation of memory arrays (e.g., power supplies, heat generation, material limits, etc.), especially for mobile devices that rely on a finite power source, such as a battery.

As discussed below, ferroelectric memory cells <NUM> may have beneficial properties that may result in improved performance relative to other memory architectures. For example, because ferroelectric memory cells tend to be less susceptible to degradation of stored charge, a memory array <NUM> that employs ferroelectric memory cells <NUM> may require fewer or no refresh operations, and may thus require less power to operate. Additionally, employing sensing schemes described herein in which cells are accessed and written several time during each sensing operation may allow for greater retention capability of the memory cell <NUM>, while reducing imprinting and fatigue.

The memory controller <NUM> may control the operation (e.g., read, write, re-write, refresh, etc.) of memory cells <NUM> through the various components, such as row decoder <NUM>, column decoder <NUM>, and sense component <NUM>. Memory controller <NUM> may generate row and column address signals in order to activate the desired word line <NUM> and digit line <NUM>. Memory controller <NUM> may also generate and control various voltage potentials used during the operation of memory array <NUM>. In general, the amplitude, shape, or duration of an applied voltage discussed herein may be adjusted or varied and may be different for the various operations for operating memory array <NUM>. Furthermore, one, multiple, or all memory cells <NUM> within memory array <NUM> may be accessed simultaneously. For example, multiple or all cells of memory array <NUM> may be accessed simultaneously during a reset operation in which all memory cells <NUM>, or a group of memory cells <NUM>, are set to a single logic state.

<FIG> illustrates an example circuit <NUM> that supports self-referencing for ferroelectric memory in accordance with examples of the present disclosure. Circuit <NUM> includes a ferroelectric memory cell <NUM>-a, word line <NUM>-a, digit line <NUM>-a, and sense component <NUM>-a, which may be examples of a memory cell <NUM>, word line <NUM>, digit line <NUM>, and sense component <NUM>, respectively, as described with reference to <FIG>. Circuit <NUM> also includes selection component <NUM>, virtual ground <NUM>, reference line <NUM>, and a logic storage component such as capacitor <NUM>, which may include two conductive terminals, including plate <NUM> and cell bottom <NUM>. In the example of <FIG>, the terminals of capacitor <NUM> are separated by an insulating ferroelectric material. As described above, various states may be stored by charging or discharging capacitor <NUM>, i.e., polarizing the ferroelectric material of capacitor <NUM>.

The stored state of capacitor <NUM> may be read or sensed by operating various elements represented in circuit <NUM>. As depicted, capacitor <NUM> may be in electronic communication with digit line <NUM>-a. Capacitor <NUM> may thus be isolated from digit line <NUM>-a when selection component <NUM> is deactivated, and capacitor <NUM> can be connected to digit line <NUM>-a when selection component <NUM> is activated to select the ferroelectric memory cell <NUM>-a. In other words, ferroelectric memory cell <NUM>-a may be selected using selection component <NUM> that is in electronic communication with ferroelectric capacitor <NUM>, where ferroelectric memory cell <NUM>-a includes selection component <NUM> and ferroelectric capacitor <NUM>. Activating selection component <NUM> may be referred to as selecting memory cell <NUM>-a. In some cases, selection component <NUM> is a transistor and its operation is controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than the threshold magnitude of the transistor. Word line <NUM>-a may activate selection component <NUM>; for example, a voltage applied to word line <NUM>-a is applied to the transistor gate, connecting capacitor <NUM> with digit line <NUM>-a.

In other examples, the positions of selection component <NUM> and capacitor <NUM> may be switched, such that selection component <NUM> is connected between plate <NUM> line and cell plate <NUM> and such that capacitor <NUM> is between digit line <NUM>-a and the other terminal of selection component <NUM>. In this embodiment, selection component <NUM> may remain in electronic communication with digit line <NUM>-a through capacitor <NUM>. This configuration may be associated with alternative timing and biasing for read and write operations.

Due to the ferroelectric material between the plates of capacitor <NUM>, and as discussed in more detail below, capacitor <NUM> may not discharge upon connection to digit line <NUM>-a. Instead, plate <NUM> may be biased by an external voltage, resulting in a change in the stored charge on capacitor <NUM>. The change in stored charge corresponds to a logic state of capacitor <NUM>. A voltage applied to capacitor <NUM> changes the charge of capacitor <NUM>. The change in stored charge may then be compared to one or more reference charges (e.g., reference "<NUM>" or reference "<NUM>") by sense component <NUM>-a in order to determine the stored logic state in memory cell <NUM>-a.

To write memory cell <NUM>-a, a voltage may be applied to capacitor <NUM>. Various methods may be used. For example, selection component <NUM> may be activated through word line <NUM>-a in order to electrically connect capacitor <NUM> to digit line <NUM>-a. A voltage may be applied to capacitor <NUM> by controlling the voltage of plate <NUM> and cell bottom <NUM> through digit line <NUM>-a. Two write a logic "<NUM>," plate <NUM> may be taken high-i.e., a positive voltage may be applied-and cell bottom <NUM> may be taken low-i.e., connected to virtual ground <NUM>, grounded, or negative voltage may be applied. The opposite process is performed to write a logic "<NUM>"-i.e., plate <NUM> is taken low and cell bottom <NUM> is taken high.

The change in voltage of digit line <NUM>-a may depend on its intrinsic capacitance. That is, as charge flows through digit line <NUM>-a, some finite charge may be stored in digit line <NUM>-a and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance may depend on physical characteristics, including the dimensions, of digit line <NUM>-a. Digit line <NUM>-a may connect many memory cells <NUM> so digit line <NUM>-a may have a length that results in a non-negligible capacitance (e.g., on the order of picofarads (pF)). The resulting voltage of digit line <NUM>-a may then be compared to a reference (e.g., a voltage of reference line <NUM>) by sense component <NUM>-a in order to determine the stored logic state in memory cell <NUM>-a. Other sensing processes may be used.

Sense component <NUM>-a may include various transistors or amplifiers to detect and amplify a difference in signals, which may be referred to as latching. Sense component <NUM>-a may include a sense amplifier that receives and compares the voltage of digit line <NUM>-a and reference line <NUM>, which may be a reference voltage. Additionally, sense component <NUM>-a may compare, for example, charges stored at various capacitors (not shown), as is, as described with reference to <FIG>. The sense amplifier output may be driven to the higher (e.g., a positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For instance, if digit line <NUM>-a has a higher voltage than reference line <NUM>, then the sense amplifier output may be driven to a positive supply voltage.

In some cases, the sense amplifier may additionally drive digit line <NUM>-a to the supply voltage. Sense component <NUM>-a may then latch the output of the sense amplifier and/or the voltage of digit line <NUM>-a, which may be used to determine the stored state in memory cell <NUM>-a, e.g., logic "<NUM>. " Alternatively, if digit line <NUM>-a has a lower voltage than reference line <NUM>, the sense amplifier output may be driven to a negative or ground voltage. Sense component <NUM>-a may similarly latch the sense amplifier output to determine the stored state in memory cell <NUM>-a, e.g., logic "<NUM>. " The latched logic state of memory cell <NUM>-a may then be output, for example, through column decoder <NUM> as output <NUM> with reference to <FIG>.

As described here, the reference value may be a voltage that results from averaging the charge from successive sense operations. Averaging the charge from successive sense operations may entail calculating a numerical average of the charges. Alternatively, averaging the charge from successive sense operations may pertain to charge sharing. So unlike schemes in which a reference value is static or array-wide, reference line <NUM> may be configured with a cell-specific value or self-reference. Reference line <NUM> may include or represent a coupling with several capacitors (not shown), as described with reference to <FIG>.

Virtual ground <NUM> may provide a virtual ground to digit line <NUM>-a. Virtual ground <NUM> may be separated from digit line <NUM>-a through a switch <NUM>. In some examples, switch <NUM> may be a transistor, or may be a transistor connected in series with sense component <NUM>-a and digit line <NUM>-a. In some cases the transistor comprises a p-type FET.

<FIG> illustrates an example of non-linear electrical properties with hysteresis curves <NUM>-a and <NUM>-b for a ferroelectric memory cell that is operated in accordance with examples of the present disclosure. Hysteresis curves <NUM>-a and <NUM>-b illustrate writing and reading processes. According to the example of <FIG>, hysteresis curve <NUM>-a may represent reading logic state "<NUM>" and hysteresis curve <NUM>-b may represent reading logic state "<NUM>. " Hysteresis curves <NUM>-a and <NUM>-b depict the charge, Q, stored on a ferroelectric capacitor (e.g., capacitor <NUM> of <FIG>) as a function of a voltage difference, V.

A ferroelectric material is characterized by a spontaneous electric polarization, i.e., it maintains a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. Electric polarization within a ferroelectric capacitor results in a net charge at the ferroelectric material's surface and attracts opposite charge through the capacitor terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Because the electric polarization may be maintained in the absence of an externally applied electric field for relatively long times, even indefinitely, charge leakage may be significantly decreased as compared with, for example, capacitors employed in DRAM arrays. This may reduce the need to perform refresh operations as described above for some DRAM architectures.

Hysteresis curves <NUM>-a and <NUM>-b may be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Likewise, if the ferroelectric material has a positive polarization, negative charge accumulates at the terminal. Additionally, it should be understood that the voltages in hysteresis curves <NUM>-a and <NUM>-b represent a voltage difference across the capacitor and are directional. For example, a positive voltage may be realized by applying a positive voltage to the terminal in question (e.g., a cell plate <NUM> of <FIG>) and maintaining the second terminal (e.g., a cell bottom <NUM> of <FIG>) at ground (or approximately zero volts (0V)). A negative voltage may be applied by maintaining the terminal in question at ground and applying a positive voltage to the second terminal-i.e., positive voltages may be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage difference shown in hysteresis curves <NUM>-a and <NUM>-b.

As depicted in hysteresis curve <NUM>-a, the ferroelectric material may maintain a negative polarization with a zero voltage difference, resulting in possible charged state <NUM>-a. Additionally, as depicted in hysteresis curve <NUM>-b, the ferroelectric material may maintain a positive polarization with a zero voltage difference, resulting in possible charged state <NUM>-b. According to the examples of <FIG>, charge state <NUM>-a represents a logic "<NUM>" state and charge state <NUM>-b represents a logic "<NUM>" state. Additionally, charge states <NUM>-a and <NUM>-b may be referred to as the remnant polarization (Pr) values, i.e., the polarization (or charge) that remains upon removing an external bias (e.g., a voltage). In some examples, the logic values of the respective charge states may be reversed to accommodate other schemes for operating a memory cell.

A logic "<NUM>" or "<NUM>" may be written to the memory cell by controlling the electric polarization of the ferroelectric material, and thus the charge on the capacitor terminals, by applying a voltage. For example, in FIG. <NUM>-a, applying a net positive voltage across the capacitor results in charge accumulation until charge state <NUM>-a is reached. This charge, for example, may be representative of a sensed logic state corresponding to signal <NUM>-a, and the charge may be stored in a sense capacitor (e.g., sense capacitor <NUM> of <FIG>). Upon removing the voltage, charge state <NUM>-a follows a path on curve <NUM>-a until it reaches charge state <NUM>-a at zero volts. Charge state <NUM>-a may be attained by applying a net positive voltage across the capacitor. This voltage, for example, may be equal to the voltage applied to reach charge state <NUM>-a. This charge, for example, may be representative of reference "<NUM>" signal <NUM>-a, and the charge may be stored in another sense capacitor (e.g., sense capacitor <NUM> of <FIG>). Applying a net negative voltage to a capacitor with charge state <NUM>-a may result in charge state <NUM>-a, and removing the net negative voltage from the capacitor with charge state <NUM>-a may result in charge state <NUM>-a at zero volts. Applying a positive voltage to the capacitor with charge state <NUM>-a may result in charge state <NUM>-a, which may be representative of reference "<NUM>" signal <NUM>-a, and the charge may be stored in another sense capacitor (e.g., sense capacitor <NUM> of <FIG>). This charge may be associated with or proportional to the voltage applied to attain charge state <NUM>-a and <NUM>-a. Additionally, the applied net positive voltage and the applied net negative voltage may be the same voltage value, with each having an opposite polarity.

Similarly, in FIG. <NUM>-b, applying a net positive voltage across the capacitor may result in charge accumulation until charge state <NUM>-b is reached. This charge, for example, may be representative of a sensed logic state corresponding to signal <NUM>-b, and the charge may be stored in a sense capacitor (e.g., sense capacitor <NUM> of <FIG>). Upon removing the voltage, charge state <NUM>-b follows a path along curve <NUM>-b until it reaches charge state <NUM>-b at zero volts. Charge state <NUM>-b may be attained by applying a net positive voltage across the capacitor. This charge, for example, may be representative of reference "<NUM>" signal <NUM>-b, and the charge may be stored in a sense capacitor (e.g., sense capacitor <NUM> of <FIG>). Applying a net negative voltage to a capacitor with charge state <NUM>-b may result in charge state <NUM>-b, and removing the net negative voltage from the capacitor with charge state <NUM>-b may result in charge state <NUM>-b at zero volts. Applying a positive voltage to capacitor with charge state <NUM>-b may result in charge state <NUM>-b, which may be representative of reference "<NUM>" signal <NUM>-b, and the charge may be stored in a sense capacitor (e.g., sense capacitor <NUM> of <FIG>). Additionally, the applied net positive voltage and the applied net negative voltage may be the same voltage value, with each having an opposite polarity.

As depicted in the example of FIG. <NUM>-a, signal <NUM>-a may be provided to a sense amplifier (e.g., sense component <NUM>-b of <FIG>) for use in determining the sensed logic value of the memory cell. Signal <NUM>-a is determined by providing, for example, the charge associated with a sensed logic state of signal <NUM>-a and a reference value <NUM>-a to a sense amplifier (e.g., sense component <NUM>-b of <FIG>). Reference value <NUM>-a may be an average of the charges associated with reference "<NUM>" signal <NUM>-a and reference "<NUM>" signal <NUM>-a.

As depicted in the example of FIG. <NUM>-b, signal <NUM>-b may be provided to a sense amplifier (e.g., sense component <NUM>-a of <FIG>) for use in determining the sensed logic value of the memory cell. Signal <NUM>-b may be determined by providing, for example, the charge associated with sensed logic state corresponding to signal <NUM>-b and a reference value <NUM>-b to a sense amplifier. Reference value <NUM>-b may be an average of the charges associated with reference "<NUM>" signal <NUM>-b and reference "<NUM>" signal <NUM>-b.

As discussed above, reading a memory cell that does not use a ferroelectric capacitor may degrade or destroy the stored logic state. A ferroelectric memory cell, however, may maintain the initial logic state after a read operation. For example, if charge state <NUM>-b is stored, the charge state may follow a path to charge state <NUM>-b during a sense operation and, after removing the voltage, the charge state may return to initial charge state <NUM>-b by following a path in the opposite direction.

<FIG> illustrates an example circuit <NUM> that supports self-referencing for ferroelectric memory in accordance with an example of the present disclosure. Circuit <NUM> includes sense capacitors <NUM>, <NUM>, and <NUM>, sense amplifier (e.g., sense component <NUM>-b), transistor <NUM>, and switching components <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>. Transistor <NUM> may also be referred to as switching component <NUM>. Sense component <NUM>-b may include node <NUM> and node <NUM>, which may be referred to as input node and reference node, respectively. In some examples, switching components <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> may be transistors. Switching components <NUM>, <NUM>, and <NUM> may be referred to as a first set of switching components, and switching components <NUM>, <NUM>, and <NUM> may be referred to as a second set of switching components.

Additionally, circuit <NUM> includes memory cell <NUM>-b, word line <NUM>-b, digit line <NUM>-b, sense component <NUM>-b, capacitor <NUM>-a, plate <NUM>-a, cell bottom <NUM>-a, selection component <NUM>-a, virtual ground <NUM>-a, which may be in electronic communication with digit line <NUM>-b via a switch <NUM>-a (e.g., an additional switching component). These various components may be examples of components as described with reference to <FIG> and <FIG>. Ferroelectric memory cell <NUM>-a may be selected using selection component <NUM>-a that is in electronic communication with ferroelectric capacitor <NUM>, where ferroelectric memory cell <NUM>-a includes selection component <NUM>-a and ferroelectric capacitor <NUM>-a. For example, selection component <NUM>-a may be a transistor (e.g., a FET) and may be activated by a voltage applied to a gate of a transistor using word line <NUM>-b.

A voltage may be applied to ferroelectric capacitor <NUM>-a based on selecting ferroelectric memory cell <NUM>-b, which may result in a charge on digit line <NUM>-b. Transistor <NUM> may be a gate, where the voltage magnitude of the digit line <NUM>-b may be greater than the threshold magnitude of the transistor <NUM>. The first set of switching components may be connected in a series configuration with transistor <NUM>, which may be connected in a series configuration with three other switching components, each connected in a series configuration with one of sense capacitors <NUM>, <NUM>, and <NUM>. When switching component <NUM> is closed, the sensed charge (e.g., sensed signal <NUM>-a of <FIG>) may be stored at sense capacitor <NUM>. The stored charge at sense capacitor <NUM> corresponds to a value associated with the sensed logic state of the ferroelectric memory cell <NUM>-b. Subsequently, additional voltages may be applied across capacitor <NUM>-a resulting in charges corresponding to a reference "<NUM>" signal (e.g., reference "<NUM>" signal <NUM>-a of <FIG>) and a reference "<NUM>" signal (e.g., reference "<NUM>" signal <NUM>-a of <FIG>). Such charges may be stored, for example, at sense capacitors <NUM> and <NUM>, respectively.

A charge stored at sense capacitor <NUM> may be provided to sense component <NUM>-b for use in determining the logic value of memory cell <NUM>-b. Additionally, the charges stored at sense capacitors <NUM> and <NUM>, respectively, may also be provided to sense component <NUM>-b. The charges stored at sense capacitors <NUM> and <NUM>, for example, may be averaged to determine a reference value (e.g., reference value <NUM>-a of <FIG>) before being compared with the charged stored at sense capacitor <NUM>. In some instances, comparing the charge stored at sense capacitor <NUM> to the reference value includes activating sense component <NUM>-b, which is in electronic communication with sense capacitor <NUM>.

Switching components <NUM>, <NUM>, and <NUM> are opened or closed to facilitate the charges being provided to the sense capacitors and sense component <NUM>-b. For example, when storing a charge to sense capacitor <NUM>, switching component <NUM> may be closed and switching components <NUM> and <NUM> may be open. Similarly, when storing a charge to sense capacitor <NUM> or <NUM>, switching components <NUM> may be open and switching component <NUM> or <NUM>, depending on the charge being stored, may be opened or closed. Additionally, switching components <NUM><NUM>, and <NUM> control charges being provided to sense component <NUM>-b. For example, when providing the charges stored at sense capacitors <NUM> and <NUM>, respectively, switching components <NUM> and <NUM> may be closed and switching component <NUM> may be open. Additionally, when providing the charge stored at sense capacitor <NUM> to the sense amplifier, switching components <NUM> may be open and switching component <NUM> may be closed.

Charges stored at sense capacitors <NUM>, <NUM>, and <NUM> are provided to sense component <NUM>-b to calculate both a reference value and a signal (e.g., signal <NUM>-a of <FIG>). These charge values may be provided to sense component <NUM>-b, which may compute an average of the values, representative of the reference value. The reference value is then compared with the charge state stored at sense capacitor <NUM> to calculate the signal, which may be used in determining the logic value associated with the memory cell. For example, the charges stored at sense capacitors <NUM> and <NUM> may be used to calculate a reference value and then compared to the charge stored at sense capacitor <NUM>. The reference value may be calculated as a numerical average of the charges stored at sense capacitors <NUM> and <NUM>. Alternatively, for example, the reference value may be calculated based on charge sharing between the charges stored at sense capacitors <NUM> and <NUM>. The logic value of the memory cell may be determined based on the difference between the reference value and the voltage resulting from charge stored at sense capacitor <NUM>.

<FIG> illustrates an example of a timing diagram <NUM> for operating a ferroelctric memory cell that supports self-referencing for ferroelectric memory. Timing diagram includes voltage (V) along the vertical axis and time (t) along the horizontal axis; and diagram <NUM> may represent at least a portion of a read operation. The voltages of various components as a function of time are also represented on timing diagram <NUM>. For example, timing diagram <NUM> includes read voltage <NUM>, negative voltage <NUM>, word line voltage <NUM>, plate line voltage <NUM>, digit line voltage <NUM>, reference "<NUM>" voltage <NUM>, reference "<NUM>" voltage <NUM>, and reference value voltage <NUM>. Timing diagram <NUM> may result from operating circuit <NUM> described with reference to <FIG>, and the following discussion is in the context of components depicted in <FIG>.

As discussed above, various states can be stored by capacitor <NUM>-a; capacitor <NUM>-a may be initialized to a first state or a second state. For example, capacitor <NUM>-a may be initialized to a first state or a second state by activating selection component <NUM>-a and applying a voltage (e.g., a write voltage) to capacitor <NUM>-a. The application of the voltage to capacitor <NUM>-a may be based at least in part on the activation of the selection component <NUM>-a. To read the state stored by capacitor <NUM>-a, the voltage across capacitor <NUM>-a may be shared by the digit line (e.g., by activating the selection component <NUM>-a), which in turn may be sampled by the sense component <NUM>-b. The voltage applied across capacitor <NUM>-a may be temporarily stored at sense capacitor <NUM>. Activating selection component <NUM>-a may include applying an activation voltage to selection component <NUM>-a; for example, cell <NUM>-b may be selected by applying word line voltage <NUM> to the gate of selection component <NUM>-a. Activating selection component <NUM>-a may electrically connect capacitor <NUM>-a to digit line <NUM>-b so that the digit line voltage <NUM> tracks the capacitor bottom voltage.

At interval <NUM> the read voltage <NUM> may be applied so that the plate line voltage <NUM> reaches a threshold value. The initial logic state of the memory cell (e.g., sensed logic state of signal <NUM>-a of <FIG>) is sensed at interval <NUM>. A threshold read value may be greater than a threshold write value used to write to the cell. Thus, when plate line voltage <NUM> is applied to the cell plate <NUM>-a, the voltage across the capacitor <NUM>-a may reach an equilibrium state or threshold value (e.g., voltage <NUM> or voltage <NUM> of <FIG>), which may depend from a charge state <NUM>-a or <NUM>-b, and thus to a logic "<NUM>" or "<NUM>," as described with reference to <FIG>.

At interval <NUM> the plate line voltage may be reset to zero (0V) by removing the read voltage <NUM>. For example, the selection component <NUM>-a may be deactivated such that capacitor <NUM>-a is isolated from the digit line <NUM>-b. Thus, isolation of capacitor <NUM>-a may be based on the determination that the digit line voltage has reached a threshold value. Isolation may include interrupting a connection between a terminal of capacitor <NUM>-a and digit line <NUM>-b. Capacitor <NUM>-a may be isolated from digit line <NUM>-b prior to the activation of sense component <NUM>-b.

At interval <NUM> the read voltage <NUM> may be re-applied such that plate line voltage <NUM> may again reach a threshold value. The value corresponding with the reference "<NUM>" state (e.g., reference "<NUM>" <NUM>-a of <FIG>) may be sensed at interval <NUM>. This resulting value voltage <NUM>-a may be sensed as described with respect to <FIG> and <FIG>. For example, the charge representative of reference "<NUM>" signal <NUM>-a may be stored at sense capacitor <NUM>. This charge may be sensed by activating transistor <NUM> and closing switching component <NUM> while opening switching components <NUM> and <NUM>. The resulting charge may then be held at sense capacitor <NUM> by opening switching component <NUM>.

At interval <NUM>, a negative voltage <NUM> may be applied, resulting in charge state <NUM>-a with reference to <FIG>. At interval <NUM>, the plate line may be grounded (0V) and the digit line voltage <NUM> may be biased to read voltage <NUM>. After biasing the digit line voltage to read voltage <NUM>, the digit line voltage <NUM> may grounded (0V) at interval <NUM>, resulting in charge state <NUM>-a with reference to <FIG>. The read voltage <NUM> may then be re-applied such that plate line voltage <NUM> is again biased to read voltage <NUM>.

The value corresponding with the reference "<NUM>" state (e.g., reference "<NUM>" <NUM>-a of <FIG>) may be sensed at interval <NUM>. This resulting value voltage <NUM>-b may be sensed as described with respect to <FIG> and <FIG>. For example, the charge representative of reference "<NUM>" signal <NUM>-a may be stored at sense capacitor <NUM>. This charge may be sensed by activating transistor <NUM> and closing switching component <NUM> while opening switching components <NUM> and <NUM>. The resulting charge may then be held at sense capacitor <NUM> by opening switching component <NUM>.

At interval <NUM>, reference value voltage <NUM> is generated by providing the reference "<NUM>" value from interval <NUM> (e.g., value voltage <NUM>-a) and the reference "<NUM>" value from interval <NUM> (e.g., value voltage <NUM>-b). For example, reference value voltage <NUM> may be generated by averaging the reference "<NUM>" and reference "<NUM>" values by closing switching components <NUM> and <NUM> with reference to <FIG>. These values are provided to a sense amplifier (e.g., sense component <NUM>-b of <FIG>) at interval <NUM> and a logic value is written back to the memory cell at interval <NUM>.

<FIG> shows a block diagram <NUM> of a memory array <NUM>-a that supports self-referencing for ferroelectric memory in accordance with various embodiments of the present disclosure. Memory array <NUM>-a may be referred to as an electronic memory apparatus, and may be an example of a component of a memory controller <NUM> as described with reference to <FIG>.

Memory array <NUM>-a may include one or more memory cells <NUM>-c, a memory controller <NUM>-a, a word line <NUM>-c, a plate <NUM>-b line, a reference component <NUM>, a sense component <NUM>-c, a digit line <NUM>-c, and a latch <NUM>. These components may be in electronic communication with each other and may perform one or more of the functions described herein. In some cases, memory controller <NUM>-a may include biasing component <NUM> and timing component <NUM>. Memory controller <NUM>-a may be in electronic communication with word line <NUM>-c, digit line <NUM>-c, sense component <NUM>-c, and plate line <NUM>-b, which may be examples of word line <NUM>, digit line <NUM>, sense component <NUM>, and plate line <NUM> described with reference to <FIG> and <FIG>. In some cases, reference component <NUM>, sense component <NUM>-c, and latch <NUM> may be components of memory controller <NUM>-a.

In some examples, digit line <NUM>-c is in electronic communication with sense component <NUM>-c and a ferroelectric capacitor of ferroelectric memory cells <NUM>-c. A logic state (e.g., a first or second logic state) may be written to ferroelectric memory cell <NUM>-c. Word line <NUM>-c may be in electronic communication with memory controller <NUM>-a and a selection component of ferroelectric memory cell <NUM>-c. Plate <NUM>-b line may be in electronic communication with memory controller <NUM>-a and a plate of the ferroelectric capacitor of ferroelectric memory cell <NUM>-c. Sense component <NUM>-c may be in electronic communication with memory controller <NUM>-a, digit line <NUM>-c, latch <NUM>, and reference line. Reference component <NUM> may be in electronic communication with memory controller <NUM>-a and reference line. These components may also be in electronic communication with other components, both inside and outside of memory array <NUM>-a, in addition to components not listed above, via other components, connections, or busses.

Memory controller <NUM>-a may be configured to activate word line <NUM>-c, plate <NUM>-b line, or digit line <NUM>-c by applying voltages to those various nodes. For example, biasing component <NUM> may be configured to apply a voltage to operate memory cell <NUM>-c to read or write memory cell <NUM>-c as described above. In some cases, memory controller <NUM>-a may include a row decoder, column decoder, or both, as described with reference to <FIG>. This may enable memory controller <NUM>-a to access one or more memory cells <NUM>-c. Biasing component <NUM> may also provide one or more voltages to reference component <NUM> in order to generate a reference signal for sense component <NUM>-c. Additionally, biasing component <NUM> may provide a voltage for the operation of sense component <NUM>-c.

In some cases, memory controller <NUM>-a may perform its operations using timing component <NUM>. For example, timing component <NUM> may control the timing of the various word line selections or plate biasing, including timing for switching and voltage application to perform the memory functions, such as reading and writing, discussed herein. In some cases, timing component <NUM> may control the operations of biasing component <NUM>.

Reference component <NUM> may include various components to generate a reference signal for sense component <NUM>-c. Reference component <NUM> may include circuitry configured to produce a reference signal. For example, reference component <NUM> may include plurality of sense capacitors in electronic communication with the digit line via a plurality of switching components (as shown in <FIG>, for example). A first sense capacitor of the plurality may be coupled with the digit line via a first switching component and coupled with the sense component <NUM>-c via a second switching component. A second sense capacitor of the plurality may be coupled with the digit line via a third switching component and coupled with the sense component <NUM>-c via a fourth switching component. A third sense capacitor of the plurality may be coupled with the digit line via a fifth switching component and coupled with the sense component <NUM>-c via a sixth switching component. In some cases, reference component <NUM> may be implemented using other ferroelectric memory cells <NUM>-c.

The controller <NUM>-a may be in electronic communication with the plurality of sense capacitors of reference component <NUM>. The controller may be operable to control the first switching component, the third switching component, and the fifth switching component. For example, the controller <NUM>-a may be operable to control the switching components to store a first charge associated with a first sense operation of the plurality at the first sense capacitor, store a second charge associated with a second sense operation of the plurality at the second sense capacitor, and store a third charge associated with a third sense operation of the plurality at the third sense capacitor. Memory controller <NUM>-a may be operable to set a first condition of a memory cell after extracting a first charge associated with first sense operation. Memory controller <NUM>-a may also be operable to set a second condition of the memory cell after extracting a second charge associated with the second sense operation and to reset the first condition of the memory cell after extracting the third charge associated with the third sense operation.

In some examples, memory controller <NUM>-a may include or may support means for applying a first voltage to a ferroelectric memory cell (e.g., memory cell <NUM>-c) to initiate a plurality of sense operations. Memory controller <NUM>-a may include or may support means for determining a reference voltage for the ferroelectric memory cell based at least in part on an average of two sense operations of the plurality of sense operations. In other examples, memory controller <NUM>-a may include or may support means for determining a logic state of the ferroelectric memory cell based at least in part on a comparison of the reference voltage and a sensed voltage of an additional sense operation of the plurality of sense operations.

In some examples, memory controller <NUM>-a may include or may support means for controlling a first switching component, a third switching component, and a fifth switching component. Memory controller <NUM>-a may include or may support means for storing a first charge associated with a first sense operation of the plurality at the first sense capacitor. In some examples, memory controller <NUM>-a may include or may support means for storing a second charge associated with a second sense operation of the plurality at the second sense capacitor. In other examples, memory controller <NUM>-a may include or may support means for storing a third charge associated with a third sense operation of the plurality at the third sense capacitor.

In other examples, memory controller <NUM>-a may include or may support means for setting a first condition of the ferroelectric memory cell after extracting the first charge associated with the first sense operation. Memory controller <NUM>-a may include or may support means for setting a second condition of the ferroelectric memory cell after extracting the second charge associated with the second sense operation. Additionally or alternatively, memory controller <NUM>-a may include or may support means for resetting the first condition of the ferroelectric memory cell after extracting the third charge associated with the third sense operation. In other examples, memory controller <NUM>-a may include or may support means for controlling a second switching component, a fourth switching component, and a sixth switching component. Memory controller <NUM>-a may include or may support means for determining the reference voltage and comparing the reference voltage and the sensed voltage of the additional sense operation.

Sense component <NUM>-c may compare a signal from memory cell <NUM>-c (through digit line <NUM>-c) with a reference signal from reference component <NUM>. Upon determining the logic state, the sense component may then store a sensed voltage in latch <NUM>, where it may be used in accordance with the operations of an electronic device that memory array <NUM>-a is a part. Sense component <NUM>-c may include a sense amplifier in electronic communication with the latch and the ferroelectric memory cell. Memory controller <NUM>-a may thus be operable to control switching components of reference component <NUM> to determine a state of a memory cell with sense component <NUM>-c. For example, memory controller <NUM>-a may be operable to control the second switching component, the fourth switching component, and the sixth switching component to determine the reference voltage, and to compare the reference voltage and a sensed voltage of the additional sense operation in combination with sense component <NUM>-c.

Memory controller <NUM>-a, or at least some of its various sub-components may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions of the memory controller <NUM>-a and/or at least some of its various sub-components may be executed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present disclosure. The memory controller <NUM>-a and/or at least some of its various sub-components may be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations by one or more physical devices. In some examples, memory controller <NUM>-a and/or at least some of its various sub-components may be a separate and distinct component in accordance with various embodiments of the present disclosure. In other examples, memory controller <NUM>-a and/or at least some of its various sub-components may be combined with one or more other hardware components, including but not limited to a receiver, a transmitter, a transceiver, one or more other components described in the present disclosure, or a combination thereof in accordance with various embodiments of the present disclosure.

Memory controller <NUM>-a may sense a first state of a ferroelectric memory cell, sense a second state of the ferroelectric memory cell after sensing the first state, and sense a third state of the ferroelectric memory cell after sensing the first state and the second state, where a logic value associated with the third state is opposite from a logic value associated with the second state. Memory controller <NUM>-a may determine a logic value associated with the first state based on a comparison of the first state with an average of the second state and the third state. Averaging the second state and the third state may entail calculating a numerical average. Alternatively, averaging the second state and the third state may pertain to charge sharing. The memory controller <NUM>-a may also apply a first voltage to a ferroelectric memory cell to initiate a set of sense operations, determine a reference voltage for the ferroelectric memory cell based on an average of two sense operations of the set, identify a signal that is a function of the reference voltage and a sensed voltage of an additional sense operation of the set of sense operations, and determine a logic state of the ferroelectric memory cell based on the signal.

<FIG> shows a diagram of a system <NUM> including a device <NUM> that supports self-referencing for ferroelectric memory in accordance with various embodiments of the present disclosure. Device <NUM> may be an example of or include the components of memory controller <NUM> as described above, with reference to <FIG>. Device <NUM> may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including memory array <NUM>-b that includes memory controller <NUM>-b and memory cells <NUM>-d, basic input/output system (BIOS) component <NUM>, processor <NUM>, I/O controller <NUM>, and peripheral components <NUM>. These components may be in electronic communication via one or more busses (e.g., bus <NUM>). Memory cells <NUM>-d may store information (i.e., in the form of a logical state) as described herein.

BIOS component <NUM> may be a software component that includes BIOS operated as firmware, which may initialize and run various hardware components. BIOS component <NUM> may also manage data flow between a processor and various other components, for example, peripheral components, input/output control component, etc. BIOS component <NUM> may include a program or software stored in read only memory (ROM), flash memory, or any other non-volatile memory.

Processor <NUM> may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor <NUM> may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor <NUM>. Processor <NUM> may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting self-referencing for ferroelectric memory).

Peripheral components <NUM> may include any input or output device, or an interface for such devices. Examples may include disk controllers, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots.

Input <NUM> may represent a device or signal external to device <NUM> that provides input to device <NUM> or its components. This may include a user interface or an interface with or between other devices. In some cases, input <NUM> may be managed by I/O controller <NUM>, and may interact with device <NUM> via a peripheral component <NUM>.

Output <NUM> may also represent a device or signal external to device <NUM> configured to receive output from device <NUM> or any of its components. Examples of output <NUM> may include a display, audio speakers, a printing device, another processor or printed circuit board, etc. In some cases, output <NUM> may be a peripheral element that interfaces with device <NUM> via peripheral component(s) <NUM>. In some cases, output <NUM> may be managed by I/O controller <NUM>.

The components of device <NUM> may include circuitry designed to carry out their functions. This may include various circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to carry out the functions described herein. Device <NUM> may be a computer, a server, a laptop computer, a notebook computer, a tablet computer, a mobile phone, a wearable electronic device, a personal electronic device, or the like. Or device <NUM> may be a portion or component of such a device.

<FIG> shows a flowchart illustrating a method <NUM> for self-referencing for ferroelectric memory in accordance with various embodiments of the present disclosure. The operations of method <NUM> may be implemented by a memory controller or its components as described herein. For example, the operations of method <NUM> may be performed by a memory controller as described with reference to <FIG>. In some examples, a memory controller may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller may perform some or all of the functions described below using special-purpose hardware.

At block <NUM>, the method may include sensing a first state of a ferroelectric memory cell. The operations of block <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>. In certain examples, the method may also include storing a first value associated with the first state.

At block <NUM> the memory controller may sense a second state of the ferroelectric memory cell after sensing the first state. The operations of block <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>. In certain examples, the method may also include storing a second value associated with the second state after storing the first value.

At block <NUM> the memory controller may sense a third state of the ferroelectric memory cell after sensing the first state and the second state, wherein a logic value associated with the third state is opposite from a logic value associated with the second state. The operations of block <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>. In certain examples, the method may also include storing a third value associated with the third state after storing the first value and the second value.

At block <NUM> the memory controller may determine a logic value associated with the first state based at least in part on a comparison of the first state with an average of the second state and the third state. The operations of block <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>. In certain examples, the method may also include writing the logic value associated with the first state to the ferroelectric memory cell, wherein writing the logic value is based at least in part on the comparison of the first state with the average of the second state and the third state. In certain examples, the method may also include providing the stored first value as a first input to a sense component and providing the average of the stored second value and the stored third value as a second input to a sense component.

In further examples, the method may also include biasing the ferroelectric memory cell after storing the first value associated with the first state. The method may also include biasing the ferroelectric memory cell after storing the second value associated with the second state, wherein providing the average of the stored second value and the stored third value as the second input to the sense component is based at least in part on biasing the ferroelectric memory cell after storing the first value and the second value.

<FIG> shows a flowchart illustrating a method <NUM> for self-referencing for ferroelectric memory in accordance with various embodiments of the present disclosure. The operations of method <NUM> may be implemented by a memory controller or its components as described herein. For example, the operations of method <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>. In some examples, a memory controller may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory controller may perform some or all of the functions described below using special-purpose hardware.

At block <NUM> the memory controller may apply a first voltage to a ferroelectric memory cell to initiate a plurality of sense operations. Applying a voltage to the ferroelectric memory cell may initialize the ferroelectric memory cell to a first state or a second state. Applying a first voltage to initiate a plurality of sense operations may include applying the first voltage to the ferroelectric memory cell to extract a first charge form the ferroelectric memory cell. Applying the first voltage to initiate a plurality of sense operations may also include storing the first charge associated with the first sense operation at a first sense capacitor. In some instances, the memory controller may be able to set a first condition of the memory cell after extracting the first charge associated with the first sense operation.

At block <NUM> the memory controller may also apply a first voltage to initiate a plurality of sense operations that may include applying the first voltage to the ferroelectric memory cell to extract a second charge from the ferroelectric memory cell. Applying the first voltage to initiate a plurality of sense operations may also include storing the second charge associated with the second sense operation at a second sense capacitor. In some instances, the memory controller may be able to set a second condition of the memory cell after extracting the second charge associated with the second sense operation.

At block <NUM> the memory controller may also apply a second voltage to the ferroelectric memory cell, wherein the polarity of the second voltage is opposite of the polarity of the first voltage. The memory controller may remove the second voltage applied to the ferroelectric memory cell and may re-apply the first voltage to the ferroelectric memory cell to extract a third charge from the ferroelectric memory cell. Applying the first voltage may also include storing the third charge associated with the third sense operation at a third sense capacitor. In some instances, the memory controller may be able to reset the first condition of the memory cell after extracting the third charge associated with the third sense operation. The operations of block <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>.

At block <NUM> the memory controller may determine a reference voltage for the ferroelectric memory cell based at least in part on an average of two sense operations of the plurality. The operations of block <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>.

At block <NUM> the memory controller may identify a signal that is a function of the reference voltage and a sensed voltage of an additional sense operation of the plurality of sense operations. The operations of block <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>.

At block <NUM> the memory controller may determine a logic state of the ferroelectric memory cell based at least in part on the signal. The operations of block <NUM> may be performed by memory controller <NUM>-a as described with reference to <FIG>.

Furthermore, features or elements from two or more of the methods may be combined.

As used herein, the term "virtual ground" refers to a node of an electrical circuit that is held at a voltage of approximately zero volts (0V) but that is not directly connected with ground. Accordingly, the voltage of a virtual ground may temporarily fluctuate and return to approximately 0V at steady state. A virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual grounding" or "virtually grounded" means connected to approximately 0V.

The terms "electronic communication" and "coupled" refers to a relationship between components that supports electron flow between the components. This may include a direct connection between components or may include intermediate components. Components in electronic communication or coupled to one another may be actively exchanging electrons or signals (e.g., in an energized circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but may be configured and operable to exchange electrons or signals upon a circuit being energized. By way of example, two components physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

The term "isolated" refers to a relationship between components in which electrons are not presently capable of flowing between them; components are isolated from each other if there is an open circuit between them. For example, two components physically connected by a switch may be isolated from each other when the switch is open.

As used herein, the term "shorting" refers to a relationship between components in which a conductive path is established between the components via the activation of a single intermediary component between the two components in question. For example, a first component shorted to a second component may exchange electrons with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation that enables the flow of charge between components (or lines) that are in electronic communication.

The devices discussed herein, including memory array <NUM>, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A transistor or transistors discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be "off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

Claim 1:
A method, comprising:
sensing a first state of a ferroelectric memory cell (<NUM>-b) based at least in part on storing a first charge in a first capacitor (<NUM>), wherein the first charge corresponds to the first state of the ferroelectric memory cell (<NUM>-b);
sensing a second state of the ferroelectric memory cell after sensing the first state, based at least in part on storing a second charge in a second capacitor (<NUM>), wherein the second charge corresponds to the second state of the ferroelectric memory cell (<NUM>-b);
sensing a third state of the ferroelectric memory cell after sensing the first state and the second state, based at least in part on storing a third charge in a third capacitor (<NUM>), wherein the third charge corresponds to the third state of the ferroelectric memory cell, wherein a logic value associated with the third state is opposite from a logic value associated with the second state;
determining a logic value of the ferroelectric memory cell based at least in part on a comparison of the first state with an average of the second state and the third state; and
writing the logic value associated with the first state to the ferroelectric memory cell (<NUM>-b), wherein writing the logic value is based at least in part on the comparison of the first state with the average of the second state and the third state.