Patent Description:
A digital logic system typically includes combinational circuits and sequential circuits. Combinational circuits are formed of logic gates, the outputs of which are decided by current inputs. Combinational circuits perform operations that are logically characterized by Boolean expressions.

Sequential circuits include logic gates as well as storage elements known as flip-flops and latches. The outputs of storage elements are a function of current inputs and the states of the storage elements based on the previous inputs. Thus, the outputs of sequential circuits are the result of the current inputs as well as the previous inputs, and the operations of sequential circuits are decided by the internal states and a time sequence of inputs.

Many integrated circuit devices having digital logic circuits are vulnerable to single-event upsets due to radiation, and conventional flip-flop circuits and latches are no exceptions. Additional measures can be added to conventional flip-flop circuits and latches to make them more immune to single-event upsets, but a huge amount of extra circuits and space are needed for the purpose of providing sensitive nodes separation. A huge amount of extra circuits, however, is not preferable for implementations on aircraft and/or spacecraft, and definitely not acceptable at small technology nodes because it will lead to circuits that consume more power while taking much more silicon areas at the same time.

The present disclosure provides an improved radiation-hardened D flip-flop circuit.

<CIT> describes a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two crosscoupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay.

<CIT> describes flip-flops and computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture.

<CIT> describes a flip flop circuit having a first stage and a second stage. The first stage and the second stage each have interleaved filters.

According to an aspect of the present invention, there is provided a flip-flop circuit as defined in appended claim <NUM>. In accordance with one embodiment of the present disclosure, a D flip-flop circuit includes first and second dual-input inverters, first and second single-input tri-state inverters, first and second dual-input tri-state inverters, and four single-event transient (SET) filters. The first single-input tri-state inverter receives an input signal D. The first dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the first dual-input inverter and the second input receives output signals from the first dual-input inverter via the first SET filter. The output of the first dual-input tri-state inverter sends output signals to a first input of the first dual-input inverter and a second input of the first dual-input inverter via the second SET filter. The first single-input tri-state inverter sends output signals directly to the first input of said first dual-input inverter and to the second input of said first dual-input inverter via said second SET filter. The second single input tri-state inverter receives the output from said first dual-input inverter. The second dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the second dual-input inverter and the second input receives output signals from the second dual-input inverter via the third SET filter. The output of the second dual-input tri-state inverter sends output signals to a first input of the second dual-input inverter and a second input of the second dual-input inverter via the fourth SET filter. The second single-input tri-state inverter sends output signals directly to the first input of said second dual-input inverter and to the second input of said second dual-input inverter via said fourth SET filter. Said second dual-input inverter provides an output Q for said flip-flop circuit.

The features and advantages described herein are not all-inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification and claims. Moreover, it should be noted that the language used in the specification has been selected principally for readability and instructional purposes and not to limit the scope of the inventive subject matter.

The invention itself, as well as its modes of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings.

Referring now to the drawings and in particular to <FIG>, there is illustrated a schematic diagram of a D flip-flop (DFF) circuit, according to the prior art. As shown, a DFF circuit <NUM> includes a master latch <NUM> and a slave latch <NUM>. Master latch <NUM> includes first and second clocked inverter stages <NUM>-<NUM> and a first (unclocked) inverter INV1. First clocked inverter stage <NUM> includes a p-channel clock switch SP1, a p-channel data device MP1, an n-channel data device MN1, and an n-channel clock switch SN1, all connected in series. Second clocked inverter stage <NUM> includes a p-channel clock switch SP2, a p-channel data device MP2, an n-channel data device MN2, and an n-channel clock switch SN2, all connected in series. Similarly, slave latch <NUM> includes third and fourth clocked inverter stages <NUM>-<NUM>, having analogously configured clock switches SP3, SN3, SP4, and SN4 as well as data devices MP3, MN3, MP4, and MN4, along with a second (unclocked) inverter INV2.

In-phase clock signals CLK and opposite-phase clock signals CLK_B, which are generated by a clock source (not shown), can be fed to DFF circuit <NUM>. When clock signal CLK is low and clock signal CLK_B is high, inverter stage <NUM> is turned on, and data output pm of inverter stage <NUM> will be the opposite of its data input D. Similarly, inverter stage <NUM> is turned on, and the data output ss of inverter stage <NUM> will be the opposite of its data input Q. When clock signal CLK is high and clock signal CLK_B is low, inverter stages <NUM> and <NUM> will be turned off. On the other hand, when clock signal CLK is high and clock signal CLK_B is low, inverter stage <NUM> is turned on, and data output pm of inverter stage <NUM> will be the opposite of its data input m. Similarly, inverter stage <NUM> is turned on, and data output ss of inverter stage <NUM> will be the opposite of its data input m. When clock signal CLK is low and clock signal CLK_B is high, inverter stages <NUM> and <NUM> will be turned off.

During a first phase of a system clock signal, master latch <NUM> receives and latches an input signal D and, during the next phase of the system clock signal, slave latch <NUM> receives an output signal m from master latch <NUM> and presents an output signal Q, while master latch <NUM> receives and latches the next value of input signal D. The data output signals of inverter stages <NUM>, <NUM> appear at node pm. The data input signal of inverter stages <NUM>, <NUM> is provided by the data output signal of first inverter INV1 at node m, which is the output of master latch <NUM> and the input of slave latch <NUM>. The data output signals of inverter stages <NUM> and <NUM> appear at node ss. The data input signal of inverter stage <NUM> is provided by the data output signal of second inverter INV2 at node Q, which is at the output of slave latch <NUM> and the output of DFF circuit <NUM>.

With reference now to <FIG>, there is illustrated a schematic diagram of a radiation-hardened DFF circuit, in accordance with a first embodiment. As shown, a radiation-hardened DFF circuit <NUM> includes a master latch and a slave latch. The master latch includes a single-input tri-state inverter <NUM>, a dual-input tri-state inverter <NUM>, a dual-input inverter <NUM> and two single-event transient (SET) filters <NUM>-<NUM>. The slave latch includes a single-input tri-state inverter <NUM>, a dual-input tri-state inverter <NUM>, a dual-input inverter <NUM> and two SET filters <NUM>-<NUM>. For the master latch, the outputs of tri-state inverters <NUM>, <NUM> are connected to a first input of dual-input inverter <NUM> and a second input of dual-input inverter <NUM> via SET filter <NUM>. The output of dual-input inverter <NUM> is connected to a first input of dual-input tri-state inverter <NUM> and a second input of dual-input tri-state inverter <NUM> via SET filter <NUM>. The output of dual-input inverter <NUM> is also connected to single-input tri-state inverter <NUM>. For the slave latch, the outputs of tri-state inverters <NUM>, <NUM> are connected to a first input of dual-input inverter <NUM> and a second input of dual-input inverter <NUM> via SET filter <NUM>. The output of dual-input inverter <NUM> is connected to a first input of dual-input tri-state inverter <NUM> and a second input of dual-input tri-state inverter <NUM> via SET filter <NUM>. Radiation-hardened DFF circuit <NUM> receives an input D at single-input tri-state inverter <NUM> and provides an output T at dual-input inverter <NUM> along with an output Q at dual-input inverter <NUM>.

At the master latch side, when clock signal CLK goes to a logical low, data at input D enters single-input tri-state inverter <NUM>. The output of single-input tri-state inverter <NUM> is split into two paths, one of them directly enters a first input of dual-input inverter <NUM> while the other one enters a second input of dual-input inverter <NUM> via SET filter <NUM>. Dual-input inverter <NUM> and SET filter <NUM> forms a temporal filter. The output of dual-input inverter <NUM> only changes state when signals at both inputs of dual-input inverter <NUM> are the same. Thus, certain width of glitches from input D will be filtered out, depending on the settings of SET filter <NUM>. The output of dual-input inverter <NUM> goes to dual-input tri-state inverter <NUM> and to output T; and at the same time, it also goes to another temporal filter formed by dual-input tri state inverter <NUM> and set filter <NUM>. Temporal filters <NUM>, <NUM> hold the data when clock signal CLK goes to a logical high.

At the slave latch side, when clock signal CLK_B goes to a logical low, output T from dual-input inverter <NUM> enters dual-input tri-state inverter <NUM>. The output of dual-input tri-state inverter <NUM> is split into two paths, one of them directly enters a first input of dual-input inverter <NUM> while the other one enters a second input of dual-input inverter <NUM> via SET filter <NUM>. Dual-input inverter <NUM> and SET filter <NUM> forms a temporal filter. The output of dual-input inverter <NUM> only changes state when signals at both inputs of dual-input inverter <NUM> are the same. The output of dual-input inverter <NUM> goes to output Q, and at the same time, it also goes to another temporal filter formed by dual-input tri-state inverter <NUM> and SET filter <NUM>. Temporal filters <NUM>, <NUM> hold the data when clock signal CLK_B goes to a logical high.

The master latch of radiation-hardened DFF circuit <NUM> in <FIG> can be utilized separately without the slave latch. With reference now to <FIG>, there is illustrated a schematic diagram of a radiation-hardened DFF circuit, in accordance with a second embodiment. As shown, a radiation-hardened DFF circuit <NUM>' includes single-input tri-state inverter <NUM>, dual-input tri-state inverter <NUM>, dual-input inverter <NUM>, SET filters <NUM>-<NUM> and single-input inverter <NUM>'. The outputs of tri-state inverters <NUM>, <NUM> are connected to a first input of dual-input inverter <NUM> and a second input of dual-input inverter <NUM> via SET filter <NUM>. The output of dual-input inverter <NUM> is connected to a first input of dual-input tri-state inverter <NUM> and a second input of dual-input tri-state inverter <NUM> via SET filter <NUM>. The output of dual-input inverter <NUM> is also connected to single-input inverter <NUM>. Radiation-hardened DFF circuit <NUM>' receives input D at single-input tri-state inverter <NUM> and provides output Q at single-input inverter <NUM>'.

When clock signal CLK goes to a logical low, data at input D enters single-input tri-state inverter <NUM>. The output of dual-input tri-state inverter <NUM> is split into two paths, one of them directly enters a first input of dual-input inverter <NUM> while the other one enters a second input of dual-input inverter <NUM> via SET filter <NUM>. Dual-input inverter <NUM> and SET filter <NUM> forms a temporal filter. The output of dual-input inverter <NUM> only changes state when signals at both inputs of dual-input inverter <NUM> are the same. The output of dual-input inverter <NUM> goes to single-input inverter <NUM>' and to output Q, and at the same time, it also goes to another temporal filter that is formed by dual-input tri-state inverter <NUM> and SET filter <NUM>. Temporal filters <NUM>, <NUM> hold the data when clock signal CLK goes to a logical high.

Dual-input inverters <NUM> and <NUM> are substantially identical from each other, so only dual-input inverter <NUM> will be further described in details. Referring now to <FIG>, there is depicted a schematic diagram of dual-input invertor <NUM>, in accordance with a first embodiment. As shown, dual-input inverter <NUM> includes a p-channel transistor <NUM> and an n-channel transistor <NUM> connected in series between Vdd and ground. After receiving an input A0 at p-channel transistor <NUM> and an input A1 at n-channel transistor <NUM>, dual-input inverter <NUM> provides an output Z. The output Z of dual-input inverter <NUM> only changes state when both inputs A0 and A1 of inverter <NUM> are the same.

Referring now to <FIG>, there is depicted a schematic diagram of dual-input invertor <NUM>, in accordance with a second embodiment. As shown, dual-input inverter <NUM>' includes p-channel transistors <NUM>, <NUM> and n-channel transistors <NUM>, <NUM> connected in series between Vdd and ground. After receiving input signal A0 at p-channel transistor <NUM> and n-channel transistor <NUM>, and input signal A1 at p-channel transistor <NUM> and n-channel transistor <NUM>, dual-input inverter <NUM>' provides output signal Z. Dual-input inverter <NUM>' can be used as a dual-input tri-stable inverter as well.

Dual-input tri-state inverters <NUM> and <NUM> are substantially identical from each other, so only dual-input tri-state inverter <NUM> will be further described in details. With reference now to <FIG>, there is illustrated a schematic diagram of dual-input tri-state inverter <NUM> from <FIG>, <FIG>, in accordance with a first embodiment. As shown, dual-input tri-state inverter <NUM> includes a dual-input inverter <NUM> connected to a transmission gate <NUM>. Transmission gate <NUM> is clocked by in-phase clock signals CLK and opposite phase clock signals CLK_B. After receiving input signals A0, A1 at dual-input inverter <NUM>, dual-input tri-state inverter <NUM> provides an output signal Z when CLK is at a logical high.

With reference now to <FIG>, there is illustrated a schematic diagram of dual-input tri-state invertor <NUM> from <FIG>, <FIG>, in accordance with a second embodiment. As shown, dual-input tri-state inverter <NUM>' includes p-channel transistors <NUM>, <NUM> and n-channel transistors <NUM>, <NUM> connected in series between Vdd and ground. N-channel transistor <NUM> is clocked by in-phase clock signals CLK, p-channel transistor <NUM> is clocked by opposite phase clock signals CLK_B. After receiving input signal A0 at p-channel transistor <NUM> and input signal A1 at p-channel transistor <NUM>, tri-state inverter <NUM>' provides output signal Z.

SET filters <NUM>-<NUM> and <NUM>-<NUM> are substantially identical from each other, so only SET filter <NUM> will be further described in details. Referring now to <FIG>, there is depicted a schematic diagram of SET filter <NUM> within DFF circuit <NUM> from <FIG> and DFF circuit <NUM>' from <FIG>, in accordance with one embodiment. As shown, SET filter <NUM> includes single-input inverters <NUM>, <NUM> connected in series and a capacitor <NUM> connected the node between single-input inverters <NUM> and <NUM> to ground. According to one embodiment, in order to meet certain reliability requirements, the delays of single-input inverters <NUM>, <NUM> should not have an edge longer than approximately <NUM> ps. After receiving signal at input A at single-input inverter <NUM>, SET filter <NUM> provides an signal at output Z. With capacitor <NUM>, the signal from input A to output Z is delayed. The delay time of SET filters <NUM>-<NUM> and <NUM>-<NUM> should be chosen to be the glitch of SET.

As has been described, the present disclosure provides an improved radiation-hardened DFF circuit. The DFF circuit includes two temporal filters, transistors that are optimally sized, and a layout requirement to couple logically contrary transistors while separating logically consistent transistors. The temporal filter formed by a SET filter and a dual-path inverter will reject any SET glitch that is equal to or less than the delay time of the SET filter, mainly because the output of the dual-path inverter does not change the state unless both inputs are the same. The SET filtering on internal latch and demonstrated multiple-node charge cancellation technique can increase radiation hardening without using redundant circuits and separation space that requires a significantly large amount of silicon area. The improved DFF circuit minimizes the area penalty while providing enough radiation hardness to meet error rate targets.

Claim 1:
A flip-flop circuit (<NUM>) comprising:
a first single-input tri-state inverter (<NUM>) for receiving an input D;
a first dual-input inverter (<NUM>);
first and second single-event transient, SET, filters (<NUM>, <NUM>);
a first dual-input tri-state inverter (<NUM>) including a first input that receives output signals from said first dual-input inverter, a second input that receives output signals from first said dual-input inverter via said first SET filter, and an output that sends output signals to a first input of said first dual-input inverter and to a second input of said first dual-input inverter via said second SET filter;
a second single-input tri-state inverter (<NUM>) that receives an output from said first dual-input inverter;
a second dual-input inverter (<NUM>);
third and fourth SET filters (<NUM>, <NUM>); and
a second dual-input tri-state inverter (<NUM>) including a first input that receives output signals from said second dual-input inverter, a second input that receives output signals from said second dual-input inverter via said third SET filter, and an output that sends output signals to a first input of said second dual-input inverter and to a second input of said second dual-input inverter via said fourth SET filter, wherein said second dual-input inverter provides an output Q for said flip-flop circuit
wherein:
the dual-input inverters each have an output that only changes state when signals at both inputs of the inverter are the same;
the first single-input tri-state inverter sends output signals directly to the first input of said first dual-input inverter and to the second input of said first dual-input inverter via said second SET filter; and
the second single-input tri-state inverter sends output signals directly to the first input of said second dual-input inverter and to the second input of said second dual-input inverter via said fourth SET filter.