Patent Description:
Storage devices including a NAND flash memory may be utilized in various modern systems from subminiature electronic devices to media servers. In a storage device including the NAND flash, write amplification (WAF), which is caused by garbage collection, may cause irregular performance of the storage device.

In various situations, the storage device may perform a flush operation on a data in response to a command from a host that the data is no longer used.

Both the irregular performance caused by the WAF and a speed of the flush operation contribute to the performance of the storage device, and thus, there is a need to improve WAF characteristics and increase a speed of the flush operation.

From <CIT>it is known a controller of a memory system that performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

It is an aspect to provide a storage controller with improved write amplification (WAF) characteristics and increased flush operation speed.

It is another aspect to provide a storage device including a storage controller with improved WAF characteristics and increased flush operation speed.

The above and other aspects will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:.

Embodiments depicted in and described with respect to <FIG> do not reflect the literal wording of the claims.

A host communicating with a storage device may transmit a Trim command to the storage device to inform the storage device that data present in a specific area of the storage device is no longer used. The storage device which has received the Trim command may perform flush operation on the corresponding data.

As described above, both the irregular performance caused by the WAF and the speed of the flush operation contribute to the performance of the storage device. Various embodiments provide a storage system and storage device with improved WAF characteristics and increased speed of the flush operation.

Hereinafter, various embodiments will be described with reference to the attached drawings.

<FIG> is a block diagram illustrating a storage system according to some embodiments.

Referring to <FIG>, a storage system <NUM> may include a host <NUM> and a storage device <NUM>. In addition, the storage device <NUM> may include a storage controller <NUM> and a non-volatile memory (NVM) device <NUM>. Also, according to an exemplary embodiment, the host <NUM> may include a host controller <NUM> and a host memory <NUM>. The host memory <NUM> may serve as a buffer memory configured to temporarily store data to be transferred to the storage device <NUM> or data received from the storage device <NUM>.

The storage device <NUM> may include storage media configured to store data in response to requests from the host <NUM>. For example, the storage device <NUM> may include a solid state drive (SSD). For example, when the storage device <NUM> is implemented as an SSD, the storage device <NUM> may be a device that conforms to the non-volatile memory express (NVMe) standard. Each of the host <NUM> and the storage device <NUM> may generate a packet according to an adopted standard protocol and transfer the packet.

When the NVM device <NUM> of the storage device <NUM> includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array.

According to some embodiments, the host controller <NUM> and the host memory <NUM> may be embodied as separate semiconductor chips. Alternatively, in other embodiments, the host controller <NUM> and the host memory <NUM> may be integrated in the same semiconductor chip. As an example, in some embodiments, the host controller <NUM> may be any one of a plurality of modules included in an application processor (AP). The AP may be embodied as a System on Chip (SoC). Further, the host memory <NUM> may be an embedded memory included in the AP or an NVM or memory module located outside the AP.

The host controller <NUM> may manage an operation of storing data (e.g., write data) of a buffer region of the host memory <NUM> in the NVM device <NUM> (i.e., data from the host memory <NUM> may be written to the NVM device <NUM>), or an operation of storing data (e.g., read data) of the NVM device <NUM> in the buffer region of the host memory <NUM> (i.e., data may be read from the NVM device <NUM> and stored in the buffer region of the host memory <NUM>).

The storage controller <NUM> may include a host interface (I/F) <NUM>, a memory interface (I/F) <NUM>, and a central processing unit (CPU) <NUM>. In addition, the storage controller <NUM> may further include a flash translation layer (FTL) <NUM>, a write amplification (WAF) manager (MNG) <NUM>, a buffer memory <NUM>, an error correction code (ECC) engine <NUM>, and an encryption/decryption (EN/ED) engine (ENG) <NUM>. The storage controller <NUM> may further include a working memory (not shown) in which the FTL <NUM> is loaded. The CPU <NUM> may execute the FTL <NUM> to control data write and read operations on the NVM device <NUM>.

The host interface <NUM> may transfer and receive packets to and from the host <NUM>. A packet transferred from the host <NUM> to the host interface <NUM> may include a command or data to be written to the NVM device <NUM>. A packet transferred from the host interface <NUM> to the host <NUM> may include a response to the command or data read from the NVM device <NUM>.

The command transferred from the host <NUM> to the host interface <NUM> may be, for example, a write command, a read command, a Trim command, or the like.

The memory interface <NUM> may transfer data to be written to the NVM device <NUM> to the NVM device <NUM> or receive data read from the NVM device <NUM>. The memory interface <NUM> may be configured to comply with a standard protocol, such as, for example, Toggle or open NAND flash interface (ONFI).

The FTL <NUM> may perform various functions, such as, for example, an address mapping operation, a wear-leveling operation, and a garbage collection operation. The address mapping operation may be an operation of converting a logical address received from the host <NUM> into a physical address used to actually store data in the NVM device <NUM>.

For example, the FTL <NUM> may store a mapping table in which a first logical address of first data and first physical address mapped to the first logical address are recorded. That is, the FTL <NUM> may perform an address mapping operation for the first data by referring to the mapping table.

The wear-leveling operation may be a technique for preventing excessive deterioration of a specific block by ensuring that blocks of the NVM device <NUM> are uniformly used. As an example, the wear-leveling operation may be embodied using a firmware technique that balances erase counts of physical blocks. The garbage collection operation may be a technique for ensuring usable capacity in the NVM device <NUM> by erasing an existing block after copying valid data of the existing block to a new block.

The ECC engine <NUM> may perform error detection and correction operations on read data read from the NVM device <NUM>. More specifically, the ECC engine <NUM> may generate parity bits for write data to be written to the NVM device <NUM>, and the generated parity bits may be stored in the NVM device <NUM> together with write data. During the reading of data from the NVM device <NUM>, the ECC engine <NUM> may correct an error in the read data by using the parity bits read from the NVM device <NUM> along with the read data, and output error-corrected read data.

The encryption/decryption (EN/ED) engine (ENG) <NUM> may perform at least one of an encryption operation and a decryption operation on data input to the storage controller <NUM>.

For example, the encryption/decryption engine <NUM> may perform an encryption operation and/or a decryption operation by using a symmetric-key algorithm. In this case, the encryption/decryption engine <NUM> may perform an encryption operation and/or a decryption operation by using, for example, an advanced encryption standard (AES) algorithm or a data encryption standard (DES) algorithm.

In addition, for example, the encryption/decryption engine <NUM> may perform an encryption operation and/or a decryption operation by using a public key encryption algorithm. For example, the encryption/decryption engine <NUM> may perform the encryption operation by using a public key and perform the decryption operation by using a secret key. For example, in some embodiments, the encryption/decryption engine <NUM> may use a Rivest Shamir Adleman (RSA) algorithm, an elliptic curve cryptography (ECC) algorithm, or a Diffie-Hellman (DH) algorithm.

In other embodiments, the encryption/decryption engine <NUM> may perform an encryption operation and/or a decryption operation using quantum cryptography technology, such as homomorphic encryption (HE), post-quantum cryptography (PQC), or functional encryption (FE), without being limited to the above examples.

The WAF manager (MNG) <NUM> may help to improve the performance of the storage device according to some embodiments when a memory cell included in the NVM device <NUM> is programmed. For example, the WAF manager <NUM> may improve WAF characteristics of the storage device according to some embodiments. Also, for example, the WAF manager <NUM> may increase a speed of a flush operation of the storage device according to some embodiments.

In this regard, a structure of the NVM device <NUM> will be first described with reference to <FIG>.

<FIG> is a block diagram illustrating an example of an non-volatile memory device of the storage device of the storage system of <FIG>.

Referring to <FIG>, a NVM device <NUM> may correspond to the NVM device <NUM> of the storage device <NUM> of <FIG>.

Referring to <FIG>, the NVM device <NUM> may include a control logic circuitry <NUM>, a memory cell array <NUM>, a page buffer <NUM>, a voltage generator <NUM>, and a row decoder <NUM>. The NVM device <NUM> may further include a memory interface circuitry <NUM> for communicating with the memory interface (I/F) <NUM> of the storage controller <NUM> shown in <FIG>. In addition, in some embodiments, the NVM device <NUM> may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

The control logic circuitry <NUM> may control all various operations of the NVM device <NUM>. The control logic circuitry <NUM> may output various control signals in response to commands CMD and/or addresses ADDR from the memory interface circuitry <NUM>. For example, the control logic circuitry <NUM> may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array <NUM> may include a plurality of memory blocks BLK1 to BLKz (here, z is a positive integer), each of which may include a plurality of memory cells. The memory cell array <NUM> may be connected to the page buffer <NUM> through bit lines BL and be connected to the row decoder <NUM> through word lines WL, string selection lines SSL, and ground selection lines GSL.

In an example embodiment, the memory cell array <NUM> may include a 3D memory cell array, which includes a plurality of NAND strings. Each of the NAND strings may include memory cells respectively connected to word lines vertically stacked on a substrate. Examples of various non-volatile memory devices consistent with the present disclosure are provided in <CIT>; <CIT>; <CIT>; and <CIT>, and <CIT> which are each hereby incorporated by reference in their entireties. In an example embodiment, the memory cell array <NUM> may include a 2D memory cell array, which includes a plurality of NAND strings arranged in a row direction and a column direction.

The page buffer <NUM> may include a plurality of page buffers PB1 to PBn (here, n is an integer greater than or equal to <NUM>), which may be respectively connected to the memory cells through a plurality of bit lines BL. The page buffer <NUM> may select at least one of the bit lines BL in response to the column address Y-ADDR. The page buffer <NUM> may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer <NUM> may apply a bit line voltage corresponding to data to be programmed, to the selected bit line. During a read operation, the page buffer <NUM> may sense current or a voltage of the selected bit line BL and sense data stored in the memory cell.

The voltage generator <NUM> may generate various kinds of voltages for program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator <NUM> may generate a program voltage, a read voltage, a program verification voltage, and an erase voltage as a word line voltage VWL.

The row decoder <NUM> may select one of a plurality of word lines WL and select one of a plurality of string selection lines SSL in response to the row address X-ADDR. For example, the row decoder <NUM> may apply the program voltage and the program verification voltage to the selected word line WL during a program operation and apply the read voltage to the selected word line WL during a read operation.

The memory blocks included in the memory cell array <NUM> will be described with reference to <FIG>.

<FIG> is a circuit diagram for describing a memory block of the memory cell array illustrated in <FIG>. Referring to <FIG>, the first memory block BLK1 of the memory cell array <NUM> is taken as an example. The description of the first memory block BLK <NUM> may also be applied to the other memory blocks BLK2 to BLKz and thus repeated description thereof is omitted for conciseness.

<FIG> illustrates a 3D V-NAND structure applicable to the memory blocks of the NVM devices <NUM> and <NUM> of <FIG> and <FIG>. When a NVM device is embodied as a 3D V-NAND flash memory, each of the plurality of memory blocks BLK1 to BLKz of <FIG> may be represented by an equivalent circuit shown in <FIG>.

The first memory block BLK1 shown in <FIG> may refer to a 3D memory block having a 3D structure formed on a substrate. For example, a plurality of memory NAND strings NS <NUM> to NS33 included in the first memory block BLK1 may be formed in a vertical direction to the substrate.

Referring to <FIG>, the first memory block BLK1 may include a plurality of memory NAND strings NS11 to NS33, which are connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2,. , and MC8, and a ground selection transistor GST. Each of the memory NAND strings NS <NUM> to NS33 is illustrated as including eight memory cells MC1, MC2,. , and MC8 in FIG. <NUM>, without being limited thereto.

The string selection transistor SST may be connected to string selection lines SSL1, SSL2, and SSL3 corresponding thereto. Each of the memory cells MC1, MC2,. , and MC8 may be connected to a corresponding one of word lines WL1, WL2,. Some of the word lines WL1, WL2,. , and WL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to ground selection lines GSL1, GSL2, and GSL3 corresponding thereto. The string selection transistor SST may be connected to the bit lines BL1, BL2, and BL3 corresponding thereto, and the ground selection transistor GST may be connected to the common source line CSL.

Word lines (e.g., WL1) at the same level may be connected in common, and the ground selection lines GSL1, GSL2, and GSL3 and the string selection lines SSL1, SSL2, and SSL3 may be separated from each other. <FIG> illustrates an example in which a memory block BLK1 is connected to eight word lines WL1, WL2,. , and WL8 and three bit lines BL1, BL2, and BL3, without being limited thereto.

<FIG> is a diagram for describing an operation of a storage device according to some embodiments.

In the drawings, a description is given of an example in which <NUM>-bit data is programmed, However, embodiments not limited thereto. It should be noted that, in some embodiments, <NUM>-bit data and <NUM>-bit data may be programmed.

Referring to <FIG>, <FIG>, and <FIG>, the storage controller <NUM> may write data to the NVM device <NUM>. For example, the storage controller <NUM> may write first data to a first memory cell MC1 of the NVM device <NUM>. In this case, the storage controller <NUM> may program the first memory cell MC1 N times (N is a positive integer greater than <NUM>) to write the first data. That is, the storage controller <NUM> may perform multi-programming to write data to a memory cell of the NVM device <NUM>.

In the following description, data is written by two times of programming, but the operation of the storage device <NUM> according to some embodiments is not limited thereto. For example, data may be written by N times, other than twice, of programming, where N is a positive integer.

As illustrated in <FIG>, a first programming <NUM>st PGM may be performed such that each memory cell has a state corresponding to <NUM>-bit data among eight states E, P11, P12, P13, P14, P15, P16, and P17. The eight states E and P11 to P17 may be adjacent to one another and have no read margins therebetween, as shown in <FIG>. That is, in the first programming <NUM>st PGM, <NUM>-bit data may be roughly programmed.

In an exemplary embodiment, the first programming <NUM>st PGM may be performed according to an incremental step pulse programming (ISPP) technique in which a program voltage is increased by a predetermined increment when a program loop is repeated.

In an exemplary embodiment, the first programming <NUM>st PGM may include a verification operation. The verification operation may be carried out on at least one program state. For example, in the first programming <NUM>st PGM, verification operations on the program states P12, P14, and P16 may be performed, while verification operations on the program states P11, P13, P15, and P17 may not be performed. That is, when the program states P12, P14, and P16 pass verification, the first programming <NUM>st PGM may be terminated.

A second programming <NUM>nd PGM may be perform to reprogram the first-programmed rough states P11 to P17 to denser states P21 to P27. Herein, the denser states P21 to P27, as shown in <FIG>, may be adjacent to one another and have predetermined read margins therebetween. That is, <NUM>-bit data programmed at the first programming <NUM>st PGM may be reprogrammed at the second programming <NUM>nd PGM. As described above, the <NUM>-bit data used in the second programming <NUM>nd PGM is identical to the <NUM>-bit data used in the first programming <NUM>st PGM. As shown in <FIG>, the state P11 of the first-programmed memory cells may be reprogrammed to the denser state P21 in the second programming. As a result, a threshold voltage distribution corresponding to the denser state P21 of the second-programmed memory cells may be narrower in width than that corresponding to the first-programmed state P11 of the memory cells. In other words, a verification voltage VR21 for verifying the denser state P21 of the second-programmed memory cells may be higher than a verification voltage VR11 for verifying the state P <NUM> of the first-programmed memory cells.

In an exemplary embodiment, the second programming <NUM>nd PGM may be carried out according to the ISPP technique.

In an exemplary embodiment, the second programming <NUM>nd PGM may include a verification operation. The verification operation may be carried out on all program states. When all the program states P21 to P27 pass verification, the second programming <NUM>nd PGM may be terminated, and the write of data may be completed.

In this case, before the second programming <NUM>nd PGM is executed on the first-programmed memory cell to complete the write of data, the WAF manager <NUM> may verify whether the data in the memory cell on which the second programming <NUM>nd PGM is to be performed is invalid data, and perform the second programming <NUM>nd PGM, without being limited thereto.

For example, in the case of the storage device <NUM> to which data is written by programming N times, before performing the Nth programming of the (N-<NUM>)th programmed memory cell to complete the write of data, the WAF manager <NUM> may verify whether data in a memory cell on which the Nth programming is to be performed is invalid data and perform the Nth programming, without being limited thereto.

In addition, before performing the second programming <NUM>nd PGM of the first-programmed memory cell to complete the write of the data, the WAF manager <NUM> may first detect a memory block which includes an open memory cell, and when the memory block including the open memory cell is detected, may conduct compaction by moving the first-programmed memory cell to the memory block including the open memory cell, and perform the second programming <NUM>nd PGM, without being limited thereto.

For example, in the case of the storage device <NUM> to which data is written by N times of programming, before performing the Nth programming of the (N-<NUM>)th programmed memory cell to complete the write of data, the WAF manager <NUM> may first detect a memory block which includes an open memory cell, and when the memory block including the open memory cell is detected, may conduct compaction by moving the (N-<NUM>)th-programmed memory cell to the memory block including the open memory cell, and perform the Nth programming.

The WAF characteristics of the storage device <NUM> according to some embodiments may be improved via the operation of the WAF manager <NUM> described above. In addition, the speed of the flush operation of the storage device <NUM> may be increased.

Hereinafter, the structure and operation of the WAF manager <NUM> will be described in detail. In the following description, data is written to a memory cell of the storage device <NUM> by two times of programming. However, it should be noted that, in some embodiments, data may be written to a memory cell of the storage device <NUM> by N-times of programming as discussed above.

<FIG> is a block diagram illustrating a WAF manager according to some embodiments.

Hereinafter, a description will be given of an example in which the storage controller <NUM> writes first data to the first memory cell MC1 by two times of programming. In addition, it is assumed that the first memory cell MC1 has already been programmed once and the final second programming has not been yet performed for writing the first data.

Referring to <FIG>, <FIG>, and <FIG>, the WAF manager <NUM> may include an FTL checker <NUM>. The FTL checker <NUM> may communicate with the FTL <NUM> and check whether the first data is invalid data by referring to the mapping table in the FTL <NUM>.

For example, when it is determined that the first physical address corresponding to the first logical address of the first data is not mapped according to the mapping table in the FTL <NUM>, the FTL checker <NUM> may determine that the first data is invalid data.

In another example, when it is determined that a Trim command (e.g., an example of a command CMD) is transferred from the host <NUM> for the first data according to the mapping table in the FTL <NUM>, the FTL checker <NUM> may determine that the first data is invalid data.

The storage controller <NUM>, more specifically the CPU <NUM> of the storage controller <NUM>, does not perform the second programming <NUM>nd PGM of the first memory cell when the WAF manager <NUM> transmits the determined result indicating that the first data is invalid data.

In this way, the word line (e.g., the first word line WL1) connected to the first memory cell MC1 may be prevented from being unnecessarily programmed.

The operation of the storage device <NUM> including the WAF manager <NUM> described above will be described with reference to a flowchart.

<FIG> is a flowchart for describing the operation of the WAF manager of <FIG> according to some embodiments.

Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the first programming <NUM>st PGM is performed to write the first data to the first memory cell MC1 in S100.

Then, the WAF manager <NUM> determines whether the first data is invalid data in the FTL <NUM> by using the FTL checker <NUM> in S110.

If is determined that the first data is valid data in the FTL <NUM> (S110, N), the second programming <NUM>nd PGM of the first memory cell MC1 may be performed to write second data in S120.

Otherwise, if the first data is determined to be invalid data in the FTL <NUM> (S1 <NUM>, Y), the second programming <NUM>nd PGM of the first memory cell MC1 is not performed and the programming operation ends.

<FIG> is a block diagram illustrating another WAF manager according to some embodiments.

Referring to <FIG>, <FIG>, and <FIG>, the WAF manager <NUM> includes a buffer memory checker <NUM>. The buffer memory checker <NUM> communicates with the buffer memory <NUM> to check whether the first data in the buffer memory <NUM> is invalid data.

For example, when it is determined that the first data in the buffer memory <NUM> is overwritten data, the buffer memory checker <NUM> may determine that the first data is invalid data. For example, the host <NUM> may transfer a write command (e.g., an example of a command CMD) for the first data in the buffer memory <NUM> and the first data may be in a standby state in the buffer memory <NUM> until the first data is programmed in the NVM device. In this case, when the storage controller <NUM> transfers a write completion command for the first data to the host <NUM> and the host <NUM> recognizes the command and transfers a write data for the first data again, it may be determined that the first data has been overwritten.

Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the first programming <NUM>st PGM is performed to write the first data to the first memory cell MC1 in S200.

Then, the WAF manager <NUM> determines whether the first data is invalid data in the buffer memory <NUM> by using the buffer memory checker <NUM> in S210.

If is determined that the first data is valid data in the buffer memory <NUM> (S210, N), the second programming <NUM>nd PGM of the first memory cell MC1 may be performed to write second data in S220.

Otherwise, if the first data is determined to be invalid data in the buffer memory <NUM> (S210, Y), the second programming <NUM>nd PGM of the first memory cell MC1 is not performed and the programming operation ends.

Referring to <FIG>, the WAF manager <NUM> may include both the FTL checker <NUM>, which is described above with reference to <FIG> and <FIG>, and the buffer memory checker <NUM>, which is described above with reference to <FIG> and <FIG>. That is, the WAF manager <NUM> according to some embodiments may determine whether the first data is invalid data by using operations of the FTL checker <NUM> and the buffer memory checker <NUM>. In some embodiments, the operations of the FTL checker <NUM> and the buffer memory checker <NUM> may be performed in parallel.

The operation of the WAF manager <NUM> according to some embodiments will be described with reference to a flowchart shown in <FIG>.

Referring to <FIG>, <FIG>, <FIG>, and <FIG>, the first programming <NUM>st PGM is performed to write first data to the first memory cell MC1 in S300.

Thereafter, it may be determined whether the first data is invalid data in the buffer memory <NUM> by using the buffer memory checker <NUM> in S310. Also, it may be determined whether the first data is invalid data in the FTL <NUM> by using the FTL checker <NUM> in S320. The operation of the buffer memory checker <NUM> and the operation of the FTL checker <NUM> may be performed in parallel.

If the buffer memory checker <NUM> determines that the first data is invalid data in the buffer memory <NUM> (S310, Y), the second programming <NUM>nd PGM of the first memory cell MC1 is not performed.

In addition, if the FTL checker <NUM> determines that the first data is invalid data in the FTL <NUM> (S320, Y), the second programming <NUM>nd PGM of the first memory cell MC1 is not performed.

In other words, when the buffer memory checker <NUM> determines that the first data is valid data in the buffer memory <NUM> (S310, N) and the FTL checker <NUM> determines that the first data is valid data in the FTL <NUM> (S320, N), the second programming <NUM>nd PGM of the first memory cell MC1 may be performed. Stated another way, the second programming <NUM>nd PGM is only performed when the first data is valid data in both the FTL <NUM> and the buffer memory <NUM>.

The operation of the storage controller <NUM> described above with reference to <FIG> according to some embodiments will be described with reference to the drawings illustrating simplified blocks.

<FIG> are diagrams for describing the operation of the storage controller described above with reference to <FIG> according to some embodiments.

Referring to <FIG>, <FIG>, <FIG>, <FIG>, and <FIG>, the memory cells MC1 to MC12 may be disposed at intersections of a plurality of word lines WL5 to WL8 extending in a first direction and the plurality of string lines SSL1 to SSL3 extending in a second direction orthogonal to the first direction.

In this case, it is assumed that data to be written to a tenth memory cell MC10 and an eleventh memory cell MC11 are determined to be invalid data by the buffer memory checker <NUM> and/or the FTL checker <NUM>. Here, the tenth memory cell MC10 and the eleventh memory cell MC11 are defined as invalid memory cells.

When the storage controller <NUM> writes data to the memory cells MC1 to MC12 through two times of programming, if the storage controller <NUM> programs all the memory cells MC1 to MC12 without checking the validity of the data before performing the second programming <NUM>nd PGM, the fifth word line WL5 connected to the tenth memory cell MC <NUM> and to the eleventh memory cell MC11 may be unnecessarily programmed as shown in <FIG>.

Referring to <FIG>, to execute two times of programming of the memory cells MC1 to MC12 as in the related art, the first programming <NUM>st PGM may be sequentially performed in the order of <NUM> to <NUM> from the first memory cell MC1 to a sixth memory cell MC6. Then, the second programming <NUM>nd PGM may be performed in the order of <NUM> to <NUM> from the first memory cell MC1 to the third memory cell MC3. Then, the first programming <NUM>st PGM may be performed in the order of <NUM> to <NUM> from a seventh memory cell MC7 to a ninth memory cell MC9. Thereafter, the second programming <NUM>nd PGM may be performed in the order of <NUM> to <NUM> from a fourth memory cell MC4 to the sixth memory cell MC6. Then, the first programming <NUM>st PGM may be performed in the order of <NUM> to <NUM> from the tenth memory cell MC10 to a twelfth memory cell MC12. Then, the second programming <NUM>nd PGM may be performed in the order of <NUM> to <NUM> from the seventh memory cell MC7 to the ninth memory cell MC9. Since the other memory cells following the twelfth memory cell MC12 are omitted, an operation of programming in the order of <NUM> to <NUM> is not shown in <FIG>. However, after programming is performed in the order of <NUM> to <NUM>, the second programming <NUM>nd PGM may be performed in the order of <NUM> to <NUM> from the tenth memory cell MC10 to the twelfth memory cell MC12. That is, when the storage controller <NUM> writes data to the memory cells MC1 to MC12 through two times of programming, if the storage controller <NUM> programs all the memory cells MC1 to MC12 without checking the validity of the data before performing the second programming <NUM>nd PGM as in the related art, the fifth word line WL5 connected to the tenth memory cell MC10 and the eleventh memory cell MC11 may be unnecessarily programmed as shown in <FIG>.

Therefore, as shown in <FIG>, according to various embodiments, when the storage controller <NUM> writes data to the memory cells MC1 to MC12 through two times of programming, if the storage controller <NUM> determines the validity of the data using the WAF manager <NUM> before performing the second programming <NUM>nd PGM and thereafter performs the second programming <NUM>nd PGM, the fifth word line WL5 connected to the tenth memory cell MC10 and the eleventh memory cell MC11 may not be unnecessarily programmed.

Referring to <FIG> and <FIG>, the WAF manager <NUM> of the storage controller <NUM> in accordance with some embodiments includes an open memory cell (MC) detector <NUM> and a memory cell (MC) compactor <NUM>.

The WAF manager <NUM> may find a memory block which includes an open memory cell by using the open memory cell detector <NUM> before performing the last programming.

For example, the open memory cell detector <NUM> may check whether an open memory cell exists in a second memory block before executing the second programming <NUM>nd PGM to write the first data to a first memory block. The open memory cell detector <NUM> may also check whether an open memory cell exists in a third memory block, etc. without being limited to the second memory block.

For example, in the first-programmed word lines among the memory blocks other than the first memory block, a location of a memory cell that has not been programmed even once before the second programming <NUM>nd PGM for writing the first data to the first memory block is performed may be defined as an open memory cell.

For example, if, before the second programming <NUM>nd PGM of a third word line located at a specific height from a string selection transistor of the first memory block, it is determined that a memory cell that has not been programmed even once is located in a third word line at the same height from a string selection transistor of the second memory block as the height of the third word line of the first memory block, the location of the memory cell may be defined as an open memory cell.

Then, before the second programming <NUM>nd PGM for writing the first data to the first memory block is performed, the memory cell compactor <NUM> may conduct memory cell compaction by moving a memory cell which is to undergo the second programming <NUM>nd PGM to the location of the open memory cell.

Accordingly, the word line that is unnecessarily programmed in the first memory block may be removed.

If the first memory block also has an open memory cell, a memory cell may be moved to a memory block having a smaller number of memory cells to be moved, between the first memory block and the second memory block. That is, the memory cell which is to undergo the second programming <NUM>nd PGM may be moved to the memory block having fewer open memory cells, between the first memory block and the second memory block.

If an open memory cell exists in a third memory block, memory cell compaction may be conducted by moving the memory cell which is to undergo the second programming <NUM>nd PGM in the first memory block to the open memory cell of the third memory block.

This operation will be described with reference to <FIG>.

Referring to <FIG>, <FIG>, and <FIG>, in order to write the first data to the first memory block and write second data to the second memory block, the first programming <NUM>st PGM of each of the first memory block and the second memory block is performed in S400.

Thereafter, in order to write the first data to the first memory block and write the second data to the second memory block, the open memory cell detector <NUM> checks whether an open memory cell exists in the first memory block or the second memory block before the second programming <NUM>nd PGM of each of the first memory block and the second memory block in S410.

If it is determined that an open memory cell does not exist in the first memory block or the second memory block (S410, N), the second programming of each of the first memory block and the second memory block is performed in S430.

Otherwise, if it is determined that an open memory cell exists in the first memory block or the second memory block (S410, Y), the memory cell compactor <NUM> conducts memory cell compaction by moving a memory cell which is to undergo the second programming <NUM>nd PGM to the position at which the open memory cell exists in S420.

Then, the second programming <NUM>nd PGM of the first memory block and the second memory block is performed in S430.

The description made with reference to <FIG> and <FIG> will be further described with reference to <FIG> and <FIG> which illustrate simplified blocks.

<FIG> and <FIG> are diagrams for describing the operation of the WAF manager described above with reference to <FIG> and <FIG> according to some embodiments.

Referring to <FIG>, <FIG>, <FIG>, and <FIG>, an example is provided in which it may be checked whether an open memory cell exists in the first memory block BLK1 and the second memory block BLK2. However, it should be noted that it may be checked whether an open memory cell exists in any open memory cells included in the NVM device <NUM>.

Each of the first memory block BLK1 and the second memory block BLK2 includes a fourth word line WL4 to an eighth word line WL8. Also, each of the first memory block BLK1 and the second memory block BLK2 includes the first string selection line SSL1 to the third string selection line SSL3. In each of the first memory block BLK1 and the second memory block BLK2, memory cells (memory cells MC1a to MC15a in the first memory block BLK1 and memory cells MC1b to MC15b in the second memory block BLK2) may be disposed at intersections of the fourth word line WL4 to the eighth word line WL8 and the first string selection line SSL1 to the third string selection line SSL3, similar to the example illustrated in <FIG>.

For example, it is assumed that the memory cells MC1a to MC6a of the first memory block BLK1 and the memory cells MC1b to MC6b of the second memory block BLK2 are programmed memory cells.

Also, it is assumed that the first programming <NUM>st PGM of the memory cells MC7a to MC11a is performed to write the first data to the first memory block BLK1. In this case, it is assumed that the first programming <NUM>st PGM of the memory cells MC7b to MC10b is performed to write the second data to the second memory block BLK2.

That is, among the word lines WL5 and WL6 including the first-programmed memory cells in the first memory block BLK1, a word line including an unprogrammed memory cell, i.e., an open memory cell, is the fifth word line WL5 including a memory cell MC12a.

The open memory cell detector <NUM> detects the memory cell 12a of the first memory block BLK1 as an open memory cell. The memory cell compactor <NUM> may conduct memory cell compaction by moving a location of programming from the memory cell MC10b of the word line ML5 including the unprogrammed memory cell, among the word lines WL5 and WL6 which are to undergo the second programming <NUM>nd PGM to write the second data to the first memory block BLK1, as shown in <FIG>.

In <FIG>, the memory cell MC12a is defined as an open memory cell, without being limited thereto. In another example, memory cells MC11b and MC12b of the second memory block BLK2 may be defined as open memory cells and compaction may be conducted by moving a location of programming from the memory cells MC10a and MC11a of the first memory block BLK1 to the locations of the memory cells MC11b and MC12b of the second memory block BLK2.

Accordingly, as shown in <FIG>, the compaction is performed by moving a location of the first programming <NUM>st PGM from the location of the memory cell MC10b in the second memory block BLK2 to the location of the open memory cell MC12a of the first memory block BLK1, so that the number of word lines to be unnecessarily programmed in the second memory block BLK2 during the second programming <NUM>nd PGM may be reduced.

As a result, the WAF characteristics and the flush speed of the storage device <NUM> according to some embodiments may be improved.

<FIG> is a diagram of a storage system to which a storage device is applied according to some embodiments.

A storage system <NUM> of <FIG> may be a mobile system, such as a mobile phone, a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet-of things (IoT) device. However, the storage system <NUM> of <FIG> is not necessarily limited to a mobile system, and may be a PC, a laptop computer, a server, a media player, or an automotive device, such as a navigation system.

Referring to <FIG>, the storage system <NUM> may include a main processor <NUM>, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may further include one or more of an image capturing device <NUM>, a user input device <NUM>, a sensor <NUM>, a communication device <NUM>, a display <NUM>, a speaker <NUM>, a power supplying device <NUM>, and a connecting interface <NUM>.

The main processor <NUM> may control the overall operations of the storage system <NUM>, more specifically, operations of other components constituting the storage system <NUM>. The main processor <NUM> may be implemented as a general-purpose processor, an exclusive processor, an application processor, or the like.

The main processor <NUM> may include one or more CPU cores <NUM>, and may further include a controller <NUM> for controlling the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. According to some embodiments, the main processor <NUM> may further include an accelerator <NUM> which is an exclusive circuit for high-speed data computation, such as Artificial Intelligence (AI) data computation. The accelerator <NUM> may include a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), and/or the like, and may be realized as a separate chip that is physically separated from other components of the main processor <NUM>.

The memories 1200a and 1200b may be used as a main memory device of the storage system <NUM>. Although the memories 1200a and 1200b may include volatile memories, such as static RAM (SRAM), DRAM, and/or the like, the memories 1020a and 1020b may include non-volatile memories, such as flash memory, phase RAM (PRAM), resistive RAM (RRAM), and/or the like. The memories 1200a and 1200b may be embodied in the same package as the main processor <NUM>.

The storage devices 1300a and 1300b may serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may respectively include storage controllers 1310a and 1310b and NVMs 1320a and 1320b configured to store data under the control of the storage controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include V-NAND flash memories having a 2D structure or a 3D structure, the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and/or RRAM.

The storage devices 1300a and 1300b may be physically separated from the main processor <NUM> and included in the storage system <NUM> or embodied in the same package as the main processor <NUM>. In addition, the storage devices 1300a and 1300b may have types of memory cards and be removably combined with other components of the storage system <NUM> through an interface, such as the connecting interface <NUM> that will be described below. The storage devices 1300a and 1300b may be devices to which a standard protocol, such as a universal flash storage (UFS), is applied, without being limited thereto.

At least one of the storage devices 1300a and 1300b may be the storage device <NUM> described above with reference to <FIG>.

The optical input device <NUM> may capture still images or moving images. The optical input device <NUM> may include a camera, a camcorder, a webcam, and/or the like.

The user input device <NUM> may receive various types of data input by a user of the storage system <NUM> and include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor <NUM> may detect various types of physical quantities, which may be obtained from the outside of the storage system <NUM>, and convert the detected physical quantities into electric signals. The sensor <NUM> may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device <NUM> may transfer and receive signals between other devices outside the storage system <NUM> according to various communication protocols. The communication device <NUM> may include an antenna, a transceiver, and/or a modem.

The display <NUM> and the speaker <NUM> may serve as output devices configured to respectively output visual information and auditory information to the user of the storage system <NUM>.

The power supplying device <NUM> may appropriately convert power supplied from a battery (not shown) embedded in the storage system <NUM> and/or an external power source, and supply the converted power to each of components of the storage system <NUM>.

The connecting interface <NUM> may provide connection between the storage system <NUM> and an external device, which is connected to the storage system <NUM> and capable of transferring and receiving data to and from the storage system <NUM>. The connecting interface <NUM> may be embodied by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE <NUM>, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

<FIG> is a diagram of a data center to which a storage device is applied according to some embodiments.

Referring to <FIG>, a data center <NUM> may be a facility that collects various types of data and provides various services, and may be referred to as a data storage center. The data center <NUM> may be a system for operating search engines and databases and may be a computing system used by companies, such as banks or government agencies. The data center <NUM> may include application servers 3100_1 to 3100_n and storage servers 3200_1 to 3200_m. The number of the application servers 3100_1 to 3100_n and the number of the storage servers 3200_1 to 3200_m may be variously selected according to embodiments. The number of the application servers 3100_1 to 3100_n and the number of the storage servers 3200_1 to 3200_m may be different from each other.

The application server 3100_1 may include at least one processor 3110_1 and at least one memory 3120_1, and the storage server 3200_1 may include at least one processor 3210_1 and at least one memory 3220_1. An operation of the storage server 3200_1 will be described as an example. The processor 3210_1 may control overall operations of the storage server 3200_1, and may access the memory 3220_1 to execute instructions and/or data loaded in the memory 3220_1. The memory <NUM> may include at least one of a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, and/or a non-volatile DIMM (NVDIMM). The number of the processors 3210_1 and the number of the memories 3220_1 included in the storage server 3200_1 may be variously selected according to embodiments. In one embodiment, the processor 3210_1 and the memory 3220_1 may provide a processor-memory pair. In one embodiment, the number of the processors 3210_1 and the number of the memories 3220_1 may be different from each other. The processor 3210_1 may include a single core processor or a multiple core processor. The above description of the storage server 3200_1 may be similarly applied to the application server 3100_1. In some embodiments, the application server 3100_1 may not include the storage device 3150_1. The storage server 3200_1 may include at least one storage device 3250_1. The number of the at least one storage device 3250_1 included in the storage server 3200_1 may be variously selected according to example embodiments.

The application servers 3100_1 to 3100_n and the storage servers 3200_1 to 3200_m may communicate with each other through a network <NUM>. The network <NUM> may be implemented using a fiber channel (FC) or an Ethernet. In this case, the FC may be a medium used for a relatively high speed data transmission, and an optical switch that provides high performance and/or high availability may be used. The storage servers 3200_1 to 3200_m may be provided as file storages, block storages, or object storages according to an access scheme of the network <NUM>.

In some embodiments, the network <NUM> may be a storage-only network or a network dedicated to a storage, such as a storage area network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to an FC protocol (FCP). For another example, the SAN may be an IP-SAN that uses a transmission control protocol/internet protocol (TCP/IP) network and is implemented according to an iSCSI (a SCSI over TCP/IP or an Internet SCSI) protocol. In another example, the network <NUM> may be a general or normal network such as the TCP/IP network. For example, the network <NUM> may be implemented according to at least one of protocols, such as an FC over Ethernet (FCoE), a network attached storage (NAS), a non-volatile memory express (NVMe) over Fabrics (NVMe-oF), etc..

Hereinafter, a description will be given focusing on the application server 3100_1 and the storage server 3200_1. The description of the application server 3100_1 may be applied to the other application servers 3100_2 to 3100_n, and the description of the storage server 3200_1 may be applied to the other storage servers 3200_2 to 3200_m, and thus repeated description thereof is omitted for conciseness.

The application server 3100_1 may store data requested to be stored by a user or a client into one of the storage servers 3200_1 to 3200_m through the network <NUM>. In addition, the application server <NUM> may obtain data requested to be read by the user or the client from one of the storage servers 3200_1 to 3200_m through the network <NUM>. For example, the application server 3100_1 may be implemented as a web server or a database management system (DBMS).

The application server 3100_1 may access a memory 3120_n or a storage device 3150_n included in the other application server 3100_n through the network <NUM>, and/or may access the memories 3220_1 to 3220_m or the storage devices <NUM> to <NUM> included in the storage servers 3200_1 to 3200_m through the network <NUM>. Therefore, the application server <NUM> may perform various operations on data stored in the application servers 3100_1 to 3100_n and/or the storage servers 3200_1 to 3200_m. For example, the application server 3100_1 may execute a command for moving or copying data between the application servers 3100_1 to 3100_n and/or the storage servers 3200_1 to 3200_m. The data may be transferred from the storage devices 3250_1 to 3250_m of the storage servers 3200_1 to 3200_m to the memories 3120_1 to 3120_n of the application servers <NUM> to 3100n directly or through the memories 3220_1 to 3220_m of the storage servers 3200_1 to 3200_m. For example, the data transferred through the network <NUM> may be encrypted data for security or privacy.

In the storage server 3200_1, an interface 3254_1 may provide a physical connection between the processor 3210_1 and a controller 3251_1 and/or a physical connection between a network interface card (NIC) 3240_1 and the controller 3251_1. For example, the interface 3254_1 may be implemented based on a direct attached storage (DAS) scheme in which the at least one storage device 3250_1 is directly connected with a dedicated cable. For example, the interface 3254_1 may be implemented based on at least one of various interface schemes, such as an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnection (PCI), a PCI express (PCIe), an NVMe, an IEEE <NUM>, a universal serial bus (USB), a secure digital (SD) card interface, a multi-media card (MMC) interface, an embedded MMC (eMMC) interface, a universal flash storage (UFS) interface, an embedded UFS (eUFS) interface, a compact flash (CF) card interface, etc..

The storage server 3200_1 may further include a switch 3230_1 and the NIC 3240_1. The switch 3230_1 may selectively connect the processor 3210_1 with the storage device 3250_1 or may selectively connect the NIC 3240_1 with the storage device 3250_1 under the control of the processor 3210_1.

In some embodiments, the NIC 3240_1 may include a network interface card, a network adapter, or the like. The NIC 3240_1 may be connected to the network <NUM> through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, or the like. The NIC 3240_1 may further include an internal memory, a digital signal processor (DSP), a host bus interface, or the like, and may be connected to the processor 3210_1 and/or the switch 3230_1 through the host bus interface. The host bus interface may be implemented as one of the above-described examples of the interface 3254_1. In one embodiment, the NIC 3240_1 may be integrated with at least one of the processor 3210_1, the switch 3230_1, and the storage device 3250_1.

In the storage servers 3200_1 to 3200_m and/or the application servers 3100_1 to 3100_n, the processor may transmit a command to the storage devices 3150_1 to 3150_n and 3250_1 to 3250_m or the memories 3120_1 to 3120_n and 3220_1 to 3220_m to program or read data. At this time, the data may be error-corrected data by an ECC engine. For example, the data may be processed by a data bus inversion (DBI) or a data masking (DM), and may include a cyclic redundancy code (CRC) information. For example, the data may be encrypted data for security or privacy.

The storage devices 3150_1 to 3150_m and 3250_1 to 3250_m may transmit a control signal and command/address signals to NAND flash memory devices 3252_1 to 3252_m in response to a read command received from the processor. When data is read from the NAND flash memory devices 3252_1 to 3252_m, a read enable (RE) signal may be input as a data output control signal and may serve to output data to a DQ bus. A data strobe signal (DQS) may be generated using the RE signal. The command and address signals may be latched in a page buffer based on a rising edge or a falling edge of a write enable (WE) signal.

The controller 3251_1 may control the overall operations of the storage device 3250_1. In one embodiment, the controller 3251_1 may include a static random access memory (SRAM). The controller 3251_1 may write data to the NAND flash memory device 3252_1 in response to a write command, or may read data from the NAND flash memory device 3252_1 in response to a read command. For example, the write command and/or the read command may be provided from the processor 3210_1 in the storage server 3200_1, the processor 3210_m in the other storage server 3200_m, or the processors 3110_1 and 3110_n in the application servers 3100_1 and 3100_n. A DRAM 3253_1 may temporarily store (e.g., may buffer) data to be written to the NAND flash memory device 3252_1 or data read from the NAND flash memory device 3252_1. Further, the DRAM 3253_1 may store metadata. The metadata may be data generated by the controller 3251_1 to manage user data or the NAND flash memory device 3252_1. The storage device 3250_1 may include a secure element for security or privacy.

Claim 1:
A storage controller for writing first data to a first memory cell (MC1) by performing programming of the first memory cell (MC1) N-times, N being a positive integer greater than <NUM>, the storage controller (<NUM>; 1310a; 1310b; 3251_1) comprising:
a write amplification, WAF, manager (<NUM>) configured to check whether the first data is invalid data before an Nth programming of the first memory cell (MC1) is performed; and
a central processing unit, CPU, (<NUM>) configured not to perform the N-th programming of the first memory cell (MC1) when the first data is the invalid data,
the storage controller (<NUM>; 1310a; 1310b; 3251_1) being adapted so that second data is written to a second memory cell (MC2) connected to a same word line (WL) as the first memory cell (MC1) by performing programming of the second memory cell (MC2) N-times,
and so that when the first data is the invalid data, the Nth programming of the first memory cell (MC1) is not performed and the Nth programming of the second memory cell (MC2) is performed to write the second data.