Patent Description:
In order to provide low-latency retrieval of instructions and/or data (as compared to the latency of transactions to a main memory system such as a double data rate (DDR) memory, for example), microprocessors may conventionally include one or more levels of cache memory resources. These cache memory resources may be arranged in a hierarchical manner - for example, a microprocessor may have level <NUM> (L0), level <NUM> (L1), level <NUM> (L2), and level <NUM> (L3) caches, of which L0 may be the relative smallest and lowest latency, with the other caches increasing in size and latency up through the L3 cache, which may be the largest but with the longest latency compared to the other caches. In some aspects, one or more of the levels of cache hierarchy may have split instruction and data caches (e.g., the L0 cache level may comprise split L0 instruction and L0 data caches), whereas other levels of the cache hierarchy may contain both instructions and data. Some levels of the cache hierarchy may be "private" to the microprocessor or, in the case of a multi-core microprocessor, may be private to one or more individual core(s) (meaning that such private caches are only visible and accessible to the associated microprocessor or individual core(s)). Other levels of the cache hierarchy, despite being physically located with a particular microprocessor, may be shared across and usable by one or more other microprocessors in a system.

In order to efficiently utilize the available computing resources of a microprocessor, it may be desirable to run multiple applications or virtual machines on the same microprocessor. With respect to shared levels of the cache hierarchy, particularly in microprocessors with large numbers of individual cores, it is further desirable to control the ability of a particular client (e.g., a specific application or virtual machine running on the microprocessor) to consume more than its share of shared cache resources. Among other reasons, this is because allowing a single client to consume more than its share of resources can result in unequal or unpredictable performance of other clients on that microprocessor. In the case of cloud computing, particular clients may have associated service level agreements (i.e., guarantees of a particular level of performance) that cannot be violated, and those service level agreements could be jeopardized if a particular client consumes an unequal portion of shared cache resources leading to unequal or unpredictable performance of other clients as described above.

In order to address this difficulty, one conventional solution has been to allocate one or more specific ways of the shared cache to individual clients. Although this approach provides some level of equalization of the shared resources consumed by individual clients, it still involves significant downsides. For example, it is naturally limited by the number of ways of the shared cache -(e.g., if the shared L3 cache has <NUM> ways, it can only be divided up between <NUM> individual clients). Further, as the ways themselves are used to perform allocations into the cache, linking individual way(s) with individual client(s) can reduce the effective associativity of the cache with respect to each individual client, which can increase the number of evictions from the shared cache and concomitantly reduce performance. Where portions of the shared cache are distributed across a shared interconnect, there may be an increased potential for side-channel attacks, due to increased interconnect traffic associated with the increased number of cache transactions.

<CIT> discloses a plurality of cores each one comprising a respective cache that is a combined private/shared cache.

Aspects disclosed in the detailed description include apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based system. In an exemplary aspect, the processor-based system includes a processor that includes a plurality of processing cores. The processing cores each includes execution circuits which are coupled to respective low level cache(s) and a configurable combined private and shared cache, and which may receive instructions and data on which to perform operations from the low level cache(s) and the combined private and shared cache. From the perspective of the processor, a shared cache portion of each configurable combined private and shared cache of each processing core can be treated as an independently-assignable portion of the overall shared cache, which is effectively the shared cache portions of all of the processing cores. Each independently-assignable portion of the overall shared cache can be associated with a particular client running on the processor (e.g., by associating a partition identifier with each client that would associate a portion of the shared cache with that client, or by associating an address partition with a particular set of shared cache portions). Particularly in systems with high processing core counts as an example, this approach can provide greater granularity of cache partitioning compared to the conventional approach of partitioning a shared cache between particular clients running on a conventional processor.

In this regard, <FIG> is a block diagram of a processor-based system <NUM> including a processor <NUM> (e.g., a microprocessor) including a configurable combined private and shared cache, as will be discussed in greater detail herein. The processor <NUM> includes a first processing core <NUM> and a second processing core <NUM> in this example. The processing cores <NUM>, <NUM> may also be referred to as "processor cores. " The first processing core <NUM> further includes execution circuits <NUM>, also called core logic circuitry <NUM>, which are coupled to low level cache(s) <NUM> and a configurable combined private and shared cache <NUM>, and which may receive instructions and data on which to perform operations from the low level cache(s) <NUM> and the combined private and shared cache <NUM>. The low level cache(s) <NUM> may include L0 and L1 caches (whether split data and instruction caches, or combined), and the configurable combined private and shared cache <NUM> may include a private L2 and a shared L3 cache, in an aspect. The second processing core <NUM> further includes execution circuits <NUM>, also called core logic circuitry <NUM>, which are coupled to low level cache(s) <NUM> and a configurable combined private and shared cache <NUM>, and which may receive instructions and data on which to perform operations from the low level cache(s) <NUM> and the combined private and shared cache <NUM>. The low level cache(s) <NUM> may include L0 and L1 caches (whether split data and instruction caches, or combined), and the configurable combined private and shared cache <NUM> may include a private L2 and a shared L3 cache, in an aspect. The first processing core <NUM> and the second processing core <NUM> may communicate over an interconnect <NUM>.

In this illustrated exemplary aspect, the configurable combined private and shared cache <NUM> functions as a physically combined but logically separated private L2 and shared L3 cache, illustrated as a shared L3 portion 124a and private L2 portion 124b, and includes a plurality of cache ways <NUM>-<NUM> through <NUM>-<NUM>. Because the private L2 and shared L3 portions are included in the same physical cache structure, it is possible to change the relative amounts of the combined private and shared cache <NUM> that are devoted to private L2 and shared L3 portions respectively. To set the sizes of the shared L3 portion 124a and the private L2 portion 124b, a configuration is programmed or set in the configurable combined private and shared cache <NUM> which allocates a first portion of the cache ways <NUM>-<NUM> to <NUM>-<NUM> to the shared L3 portion 124a, and a second portion of the cache ways <NUM>-<NUM> to <NUM>-<NUM> to the private L2 portion 124b. The configuration of the combined private and shared cache <NUM> is dynamic and may be changed during operation of the processor <NUM>, for example as part of a firmware configuration, by boot-time configuration, during system resets, during operation of the processor <NUM> when the contents of all caches are to be flushed or invalidated, or at other times and in other manners that will occur to those having skill in the art. The configuration may be changed over time, as the processor-based system <NUM> may from time to time have different applications or virtual machines allocated to run on the processor <NUM>.

For example, at a first time, the shared L3 portion 124a may include cache ways <NUM>-<NUM> to <NUM>-<NUM>, while the private L2 portion 124b may include cache ways <NUM>-<NUM> to <NUM>-<NUM>. At a later time, when the processor <NUM> is re-booted, for example, the configuration may be changed such that the shared L3 portion <NUM> may include cache ways <NUM>-<NUM> to <NUM>-<NUM>, while the private L2 portion 124b may include cache ways <NUM>-<NUM> to <NUM>-<NUM>. In some aspects, the configurable combined private and shared cache <NUM> may allow complete flexibility regarding the sizes of the shared L3 portion 124a and the private L2 portion 124b (i.e., each of the portions may be set to a size anywhere from zero cache ways to all cache ways of the configurable combined private and shared cache <NUM>), whereas in other aspects, lower and/or upper limits on the size of either or both the shared L3 portion 124a and the private L2 portion 124b may be established (e.g., the private L2 portion 124b may not be smaller than two cache ways, and/or the shared L3 portion 124a may not be smaller than four cache ways). Those having skill in the art will understand that the above aspects are included by way of illustration and not by limitation, and that other configurations of the shared L3 portion 124a and the private L2 portion 124b are possible.

In the illustrated aspect, the configurable combined private and shared cache <NUM> may function similarly to the configurable combined private and shared cache <NUM>, and as such may also include a plurality of cache ways <NUM>-<NUM> through <NUM>-<NUM>. The configurable combined private and shared cache <NUM> may share a configuration with the configurable combined private and shared cache <NUM>, or may be configured differently, depending on any requirements of an associated system architecture, design considerations, or other design choices as will be apparent to those having skill in the art. Further, although the illustrated processor-based system <NUM> shows only the first processing core <NUM> and the second processing core <NUM>, it will be appreciated that the processor <NUM> may contain any number of processing cores which may function similarly to the first processing core <NUM> and the second processing core <NUM> with respect to their associated configurable combined private and shared caches <NUM> and <NUM>.

In one aspect, the processor <NUM> may include sixty-four (<NUM>) processing cores (including the first processing core <NUM> and the second processing core <NUM> shown in <FIG>), for example. From the perspective of the processor <NUM> in <FIG>, the shared cache portion of each configurable combined private and shared cache of each processing core (e.g., processing cores <NUM>, <NUM>) may be treated as an independently-assignable portion of the overall shared L3 cache (e.g., in the lower level caches <NUM>, <NUM>) (which is effectively the shared L3 portions of all of the processing cores, such as the shared L3 portion 124a and the shared L3 portion 134a), which may be associated with a particular client running on the processor <NUM> (e.g., by associating a partition identifier with each client that would associate a portion of the shared L3 cache with that client, or by associating an address partition with a particular set of shared L3 cache portions). Particularly in systems with high processing core counts, this approach may provide greater granularity of cache partitioning compared to the conventional approach of partitioning a shared cache between particular clients running on a conventional processor. In the above-described aspect, where the processor <NUM> includes sixty-four (<NUM>) processing cores, and where the shared L3 portions (e.g., shared L3 portions 124a, 134a) of those processing cores (e.g., processing cores <NUM>, <NUM>) are configured to use eight (<NUM>) of the available twelve (<NUM>) cache ways of their respective configurable combined private and shared caches, the granularity of cache partitioning available per client increases by a factor of eight (<NUM>) in this example compared to a cache memory system which allows partitioning only on a per-cache way basis (since, in that configuration, the shared L3 portion could be partitioned only into <NUM> segments). Further, since the shared L3 portion (e.g., shared L3 portions 124a, 134a of each processing core (e.g., processing cores <NUM>, <NUM>) is not further subdivided by individual cache ways, the associativity of the shared L3 portion is not reduced, which mitigates the issue of increased conflict-based cache evictions from the shared L3 portion where the shared L3 portion is partitioned between particular clients by cache ways instead of on a per-processing core basis.

In this regard, <FIG> is a block diagram of a processor-based system <NUM> including a processor <NUM> which includes combined private and shared caches that may be partitionable on a per-processing core basis as described above with respect to <FIG>. The processor <NUM> in <FIG> includes a first processing cluster <NUM>, which is coupled to a first core cluster interface <NUM> and a first router <NUM>. A first home node <NUM> is coupled to the first router <NUM>. The processor <NUM> further includes a second processing cluster <NUM>, which is coupled to a second core cluster interface <NUM> and a second router <NUM>. A second home node <NUM> is coupled to the second router <NUM>. The processor <NUM> further includes a third processing cluster <NUM>, which is coupled to a third core cluster interface <NUM> and a third router <NUM>. A third home node <NUM> is coupled to the third router <NUM>. The home nodes <NUM>-<NUM><NUM>, <NUM>, and <NUM> may manage coherency for at least a set of memory addresses of the processor-based system <NUM> for their associated processing clusters, which may include snooping and invalidating caches, allocating and managing the shared caches, and performing transactions with a system memory (e.g., DDR DRAM in one aspect). The routers <NUM>, <NUM>, and <NUM> may be coupled together as part of a system interconnect in order to allow the processing clusters <NUM>, <NUM>, and <NUM> to communicate and transfer instructions and data between them, and to access system memory.

The first processing cluster <NUM> includes four processing cores 211a-d. Each of the processing cores 211a-d includes a configurable combined private and shared cache. The second processing cluster <NUM> includes four processing cores 221a-d. Each of the processing cores 221a-d includes a configurable combined private and shared cache. The third processing cluster <NUM> includes four processing cores 231a-d, but two of the processing cores (231b and 231d) are disabled (e.g., as a result of manufacturing defects, by deliberate fusing, or other configuration methods), although their caches are still enabled and available, and may be used by particular clients running on the processor <NUM>. The two active processing cores 231a and 231c include a configurable combined private and shared cache.

The configurable combined private and shared caches of each of the processing cores of each processing cluster may be partitioned between particular client(s) running on the processor <NUM> on a per-processing core basis. For example, the first processing cluster <NUM> may be executing a first virtual machine <NUM> on the processing cores 211a-d. Each of the processing cores 211a-d may have four of the available twelve (<NUM>) cache ways allocated to their shared L3 portion <NUM>, and the shared L3 portion <NUM> of each of the processing cores 211a-d may be associated with the first virtual machine <NUM>. The second processing cluster <NUM> may be executing a second virtual machine <NUM> on processing cores 221a-b, and may be executing a third virtual machine <NUM> on processing cores 221c-d. Processing cores 221a-b may have the size of their shared L3 portions set to zero (i.e., the second virtual machine <NUM> executing on processing cores 221a-b can run with acceptable performance without access to a co-located shared L3 portion). Processing cores 221c-d may have eight of the available twelve (<NUM>) cache ways allocated to their shared L3 portion <NUM>, and the shared L3 portion <NUM> of each of the processing cores 221c-d may be associated with the third virtual machine <NUM>. The third processing cluster <NUM> may be executing a fourth virtual machine <NUM> on processing cores 231a and 231c, while processing cores 231b and 231d are disabled, but have their have their caches configured as entirely shared L3 caches which can be used by clients running on the processor <NUM>. Processing cores 231a and 231c may have six of the available twelve cache ways allocated to their shared L3 portion <NUM>, and the shared L3 portion <NUM> of each of the processing cores 231a and 231c may be associated with the fourth virtual machine <NUM>.

As explained above, in the cases of the first processing cluster <NUM> and the second processing cluster <NUM>, the respective shared L3 portions of the caches of the associated processing cores (where configured to have at least one cache way available) may be associated with a single client application per core (e.g., the first virtual machine <NUM> on processing cores 211a-d, the second virtual machine <NUM> on processing cores 221a-b, and the third virtual machine <NUM> on processing cores 221c-d). Similarly, processing cores 231a and 231c of the third processing cluster <NUM> are associated with a single client application per-processing core (e.g., the fourth virtual machine <NUM>). However, it is also possible to allow multiple clients to access the shared L3 portion on a processing core. For example, in the case of the disabled processing cores 231b and 213d of the third processing cluster <NUM>, the entirety of each of their configurable combined private and shared caches have been configured as shared L3 portion (i.e., all twelve (<NUM>) cache ways are dedicated to the shared L3 portion), and each of the first virtual machine <NUM>, second virtual machine <NUM>, third virtual machine <NUM>, and fourth virtual machine <NUM> are permitted to access the shared L3 portions of disabled processing cores 231b and 231d.

Those having skill in the art will recognize that the above-described shared L3 portion configurations and associations with specific clients are presented by way of illustration, and not by way of limitation, and that other mappings of clients to physical memory resources are possible. For example, in some aspects, a client running on a specific processing core or cores may be restricted to only those shared L3 portions physically present on those processing cores.

Additionally, a client or group of clients may have capacity limits regarding the percentage of total available shared cache of an associated processing core or cores that may be used, which may be enforced by altering the replacement policy of the associated shared cache. For example, in the case of the shared L3 portions of disabled processing cores 231b and 231d, the associated home node <NUM> may enforce a capacity limit of no more than one-third of the available shared L3 portions of disabled processing cores 231b and 231d per client. Thus, if a first virtual machine <NUM> has already consumed one-third of the available shared L3 portions of disabled processing cores 231b and 231d, the replacement algorithm for those shared L3 portions may be altered such that new requests to store information related to the first virtual machine <NUM> will replace another entry associated with the first virtual machine <NUM> (as opposed to a free entry, or an entry associated with another client). This new replacement algorithm may be enforced until the client which is consuming the larger share of resources evicts or invalidates enough entries in the shared L3 portions to fall below the capacity limit.

In some aspects, each client software process running on a processing core (such as the virtual machines <NUM>, <NUM>, <NUM>, and <NUM> executing on the processing cores 211a-d, 221a-d, and 231a-d of <FIG>) is associated with a unique client identifier (ID) value. For each client ID value, a corresponding configuration register (CR) in each home node implements a bit mask, referred to herein as a "CLIENT_ALLOC_BITMASK. " Each of these bit masks control which shared L3 cache portions can be used by the client ID corresponding to that bit mask, where each bit in the bit mask represents one of the processing cores in the processor-based device. In this manner, the shared L3 cache may be partitioned into portions whereby a client software process associated with each client ID can only use certain portions.

When an L2 cache entry is evicted, the processing core issues a write back request, including the client ID associated with that L2 cache entry, to the respective home node. The home node then refers to the CLIENT_ALLOC_BITMASK associated with that client ID, and selects one of the shared L3 portions that are marked as available to that client ID (e.g., in one aspect, L3 portions that have a value of one (<NUM>) in the bit mask). In similar fashion, requests for allocating writes from a processing core or from a Direct Memory Access (DMA) device include a client ID, which the home node then uses to determine which portions of the shared L3 cache the write data can be allocated into.

To illustrate the use of bitmasks to control which L3 cache portions can be used by each client of a plurality of clients, <FIG> and <FIG> are provided. <FIG> shows the processor-based system of <FIG>, comprising the processing cores 211a-d, the processing cores 221a-d, and the processing cores 231a-d, as well as the three (<NUM>) home nodes <NUM>, <NUM>, and <NUM>. The CPU caches of the processing cores 211a-d, 221a-d, and 231a-d are configured into private L2 portions <NUM> and shared L3 portions <NUM>. In particular, for the processing cores 211a-d, 221a-d, 231a, and 231c, the CPU caches are configured with eight (<NUM>) ways of private L2 cache and four (<NUM>) ways of shared L3 cache. The processing cores 231b and 231d are disabled, and their entire CPU cache is configured as shared L3 cache.

The shared L3 cache portions in <FIG> are partitioned using the CLIENT_ALLOC_BITMASK settings shown in <FIG>, which are duplicated in each of the home nodes <NUM>, <NUM>, and <NUM>. It is assumed for the sake of illustration that the virtual machines <NUM>, <NUM>, <NUM>, and <NUM> of <FIG> and <FIG> are assigned client ID values of A, B, C, and D, respectively. Accordingly, the virtual machine <NUM> is associated with the CLIENT_A_ALLOC_BITMASK <NUM> of <FIG>, the virtual machine <NUM> is associated with the CLIENT_B_ALLOC_BITMASK <NUM> of <FIG>, the virtual machine <NUM> is associated with the CLIENT_C_ALLOC_BITMASK <NUM> of <FIG>, and the virtual machine <NUM> is associated with the CLIENT_D_ALLOC_BITMASK <NUM> of <FIG>. Each of the CLIENT_ALLOC_BITMASK settings includes a bit with a value of one (<NUM>) corresponding to each processor core in which the client software process can allocate into the shared L3 portion.

Thus, with the L3 partition settings illustrated in <FIG>, L2 evictions or allocating writes with a client ID value of A (i.e., operations performed by the virtual machine <NUM>) can only be allocated into the shared L3 portions in processing cores C0-C3, C9, or C11 (i.e., the processing cores 211a-d, 231b, or 231d), as indicated by the CLIENT_A_ALLOC_BITMASK <NUM>. Similarly, L2 evictions or allocating writes with a client ID value of B (i.e., operations performed by the virtual machine <NUM>) can only be allocated into the shared L3 portions in processing cores C4, C5, C9, or C11 (i.e., the processing cores 221a, 221b, 231b, or 231d), as indicated by the CLIENT_B_ALLOC_BITMASK <NUM>. L2 evictions or allocating writes with a client ID value of C (i.e., operations performed by the virtual machine <NUM>) can only be allocated into the shared L3 portions in processing cores C6, C7, C9, or C11 (i.e., the processing cores 221c, 221d, 231b, or 231d) as indicated by the CLIENT_C_ALLOC_BITMASK <NUM>, while L2 evictions or allocating writes with a client ID value of D (i.e., operations performed by the virtual machine <NUM>) can only be allocated into the shared L3 portions in processing cores C8, C9, C10, or C11 (i.e., the processing cores 231a-d) as indicated by the CLIENT_D_ALLOC_BITMASK <NUM>. Note that the shared L3 cache in the disabled processing cores 231b and 231d is available for use by all clients. By using this approach to cache partitioning, a client software process can be restricted to using only the shared L3 portions that correspond to the processing cores that the client software process itself is running on. This L3 partitioning mechanism also provides isolation between clients running on the same system, as they are not sharing the same L3 portions.

<FIG> is a block diagram of a method <NUM> for configuring a configurable combined private and shared cache that may be partitionable on a per-processing core basis as described previously with reference to <FIG>. The method <NUM> begins in block <NUM>, by establishing a shared cache portion of a configurable combined private and shared cache in a first processing core. For example, processing core 211a of <FIG> may establish four of the available <NUM> cache ways of its configurable combined private and shared cache as the shared L3 portion. The method <NUM> then continues in block <NUM>, by associating the shared cache portion of the configurable combined cache of the first processing core with a client application. For example, processing core 211a of <FIG> is executing the first virtual machine <NUM>, and the first virtual machine <NUM> is associated with the shared L3 portion of the configurable combined cache of processing core 211a (meaning that only the first virtual machine <NUM> is permitted to consume resources in the shared L3 portion of the configurable combined cache of processing core 211a).

The method optionally proceeds to block 430a, by establishing a shared cache portion of a configured combined private and shared cache in a second processor core, where the second processor core is disabled, and associating the shared cache portion of the configurable combined cache of the second processing core with the client application. For example, as described above with reference to the shared L3 portions of disabled processing cores 231b and 231d, those shared L3 portions may be configured to use all twelve (<NUM>) cache ways of their respective configurable combined private and shared caches, and may be associated with virtual machines <NUM>, <NUM>, <NUM>, and <NUM> (meaning that any of virtual machines <NUM>, <NUM>, <NUM>, and <NUM> may consume resources in the shared L3 portions of disabled processing cores 231b and 231d). In another aspect, the second processing core need not be disabled.

The method <NUM> optionally proceeds to block 430b, by selectively allocating an entry in the shared L3 portion based on a capacity limit. For example, as described above with reference to the shared L3 portions of disabled processing cores 231b and 231d, if any of the associated virtual machines <NUM>, <NUM>, <NUM>, or <NUM> exceed the configured capacity limit of one-third, the replacement algorithm for the shared L3 portions of disabled processing cores 231b and 231d may be altered to cause the virtual machine which has exceeded its capacity to perform replacements on entries already associated with that virtual machine. Those having skill in the art will recognize that although block 430b has been described with respect to disabled processing cores 231b and 231d, the same selective allocation may be applied to non-disabled processing cores as well.

The method <NUM> optionally proceeds to block 430c, by selectively allocating an entry in the shared L3 portion based on an allocation bitmask. For example, as described above with respect to <FIG> and <FIG>, client ID values may each be associated with a corresponding CR that implements a CLIENT_ALLOC_BITMASK, each of which controls which shared L3 cache portions can be used by the client ID corresponding to that bit mask.

The exemplary processor including a configurable combined private and shared cache structure that may be partitionable on a per-processing core basis according to aspects disclosed herein and discussed with reference to <FIG> may be provided in or integrated into any processor-based device. Examples, without limitation, include a server, a computer, a portable computer, a desktop computer, a mobile computing device, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a wearable- computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard, <FIG> illustrates an example of a processor-based system <NUM> that includes a configurable combined private and shared cache structure that may be partitionable on a per-processing core basis as illustrated and described with respect to <FIG>. In this example, the processor-based system <NUM> includes a processor <NUM> having one or more central processing units (CPUs) <NUM>, each including one or more processing cores, and which may correspond to the processor <NUM> of <FIG> or the processor <NUM> of <FIG>, and as such may include a configurable combined private and shared cache structure that may be partitionable on a per-processing core basis as illustrated and described with respect to <FIG>. The CPU(s) <NUM> may be a master device. The CPU(s) <NUM> is coupled to a system bus <NUM> and can intercouple master and slave devices included in the processor-based system <NUM>. As is well known, the CPU(s) <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the CPU(s) <NUM> can communicate bus transaction requests to a memory controller <NUM> as an example of a slave device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus <NUM> constitutes a different fabric.

Other master and slave devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include a memory system <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, one or more network interface devices <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) <NUM> can be any devices configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) <NUM> can be configured to support any type of communications protocol desired. The memory system <NUM> can include the memory controller <NUM> coupled to one or more memory arrays <NUM>.

The CPU(s) <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display controller(s) <NUM> sends information to the display(s) <NUM> to be displayed via one or more video processors <NUM>, which process the information to be displayed into a format suitable for the display(s) <NUM>. The display(s) <NUM> can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc..

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master devices and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

Claim 1:
A processor-based system, comprising:
a first processing core including a configurable combined private and shared cache, the configurable combined private and shared cache configured to include a shared cache portion;
the shared cache portion configured to be associated with a first client application; and
a second processing core including a configurable combined private and shared cache, the configurable combined private and shared cache comprising a shared cache portion configured to be associated with the first client application.