Patent Description:
An example telecommunication standard is Long Term Evolution (LTE). LTE is a set of enhancements to the Universal Mobile Telecommunications System (UMTS) mobile standard promulgated by Third Generation Partnership Project (3GPP). LTE is designed to support mobile broadband access through improved spectral efficiency, lowered costs, and improved services using OFDMA on the downlink, SC-FDMA on the uplink, and multiple-input multiple-output (MIMO) antenna technology. However, as the demand for mobile broadband access continues to increase, there exists a need for further improvements in LTE technology.

Message encoding may be used in various communication systems (e.g., millimeter-wave (mmW) communication systems) so that errors in a received message may be corrected and/or detected by the decoder of a receiver device. Linear block codes are a type of error-correcting codes that may be used by an mmW communications system to encode data in blocks. One class of linear block codes are polar codes.

Polar decoding is conventionally performed using a serial cancellation decoding algorithm. The serial cancellation decoding algorithm may perform a soft estimation of the original information encoded by the transmitter device. In general, due to the inherent data dependencies in the serial cancellation decoding algorithm, parallelization may not be exploited in implementing the algorithm. As a result, a polar encoder and/or polar decoder may suffer from low coding/decoding throughput and high latency. There is a need for a polar encoding and/or polar decoding technique that provides lower latency.

The document <NPL>, discloses a parallel encoding method and a parallel decoding method for polar codes in which the n stages of the polar code factor graph of length N=<NUM>n are divided into an "IPE" stage comprising κ stages of the factor graph followed by a "BPE" stage comprising the n-κ following stages of the factor graph, and both the IPE and the BPE stages are divided into independent encoders or decoders, wherein the information bits and the code bits are allocated to the parallel encoders or decoders according to most significant bits of the indexes of the information or coded bits. The documents <CIT>, Gross Warren et al, <NUM> May <NUM>, and<NPL> disclose parallelized polar decoder architectures.

Data encoding may be used in various communication systems (e.g., mmW communication systems) so that errors in the received message may be corrected and/or detected by the decoder of a receiver device. Linear block codes are a type of error-correcting codes that may be used by an mmW communication system to encode data in blocks. One class of linear block codes are polar codes.

Polar decoding is conventionally performed using a serial cancellation decoding algorithm. The serial cancellation decoding algorithm may perform a soft estimation of the original information encoded by the transmitter device. In general, due to the inherent data dependencies in the serial cancellation decoding algorithm, parallelization may not be exploited in implementing the algorithm. As a result, a polar encoder and/or polar decoder may suffer from low coding/decoding throughput and high latency. There is a need for a polar encoding/decoding technique that provides lower latency.

The present disclosure provides a solution by enabling a semi-parallel bit-reversal technique at the polar encoder of a transmitter device and/or the polar decoder of a receiver device such that the latency associated with the serial cancellation decoding algorithm of conventional polar encoding and/or polar decoding techniques may be reduced.

The invention provides a polar decoding method according to claim <NUM> and a polar decoding apparatus according to claim <NUM>. Further aspects of the invention are provided in the appended claims.

The macro cells include eNBs.

A network that includes both small cell and macro cells may be known as a heterogeneous network. The communication links <NUM> may use MIMO antenna technology, including spatial multiplexing, beamforming, and/or transmit diversity. The base stations <NUM> / UEs <NUM> may use spectrum up to Y MHz (e.g., <NUM>, <NUM>, <NUM>, <NUM>) bandwidth per carrier allocated in a carrier aggregation of up to a total of Yx MHz (x component carriers) used for transmission in each direction. Allocation of carriers may be asymmetric with respect to DL and UL (e.g., more or less carriers may be allocated for DL than for UL).

When operating in an unlicensed frequency spectrum, the small cell <NUM>' may employ LTE and use the same <NUM> unlicensed frequency spectrum as used by the Wi-Fi AP <NUM>. The small cell <NUM>', employing LTE in an unlicensed frequency spectrum, may boost coverage to and/or increase capacity of the access network. LTE in an unlicensed spectrum may be referred to as LTE-unlicensed (LTE-U), licensed assisted access (LAA), or MuLTEfire.

The mmW base station <NUM> may operate in mmW frequencies and/or near mmW frequencies in communication with the UE <NUM>.

The IP Services <NUM> may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service (PSS), and/or other IP services.

The base station may also be referred to as a Node B, evolved Node B (eNB), an access point, a base transceiver station, a radio base station, a radio transceiver, a transceiver function, a basic service set (BSS), an extended service set (ESS), or some other suitable terminology. The base station <NUM> provides an access point to the EPC <NUM> for a UE <NUM>. Examples of UEs <NUM> include a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a personal digital assistant (PDA), a satellite radio, a global positioning system, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, a tablet, a smart device, a wearable device, or any other similar functioning device.

Referring again to <FIG>, in certain aspects, the UE <NUM> and/or mmW base station <NUM> may be configured to perform semi-parallel bit-reversal at a polar encoder and/or polar decoder (<NUM>).

<FIG> is a diagram <NUM> illustrating an example of a DL frame structure in LTE. <FIG> is a diagram <NUM> illustrating an example of channels within the DL frame structure in LTE. <FIG> is a diagram <NUM> illustrating an example of an UL frame structure in LTE. <FIG> is a diagram <NUM> illustrating an example of channels within the UL frame structure in LTE. In LTE, a frame (<NUM>) may be divided into <NUM> equally sized subframes. Each subframe may include two consecutive time slots. A resource grid may be used to represent the two time slots, each time slot including one or more time concurrent resource blocks (RBs) (also referred to as physical RBs (PRBs)). In LTE, for a normal cyclic prefix, an RB contains <NUM> consecutive subcarriers in the frequency domain and <NUM> consecutive symbols (for DL, OFDM symbols; for UL, SC-FDMA symbols) in the time domain, for a total of <NUM> REs. For an extended cyclic prefix, an RB contains <NUM> consecutive subcarriers in the frequency domain and <NUM> consecutive symbols in the time domain, for a total of <NUM> REs.

As illustrated in <FIG>, some of the REs carry DL reference (pilot) signals (DL-RS) for channel estimation at the UE. The DL-RS may include cell-specific reference signals (CRS) (also sometimes called common RS), UE-specific reference signals (UE-RS), and channel state information reference signals (CSI-RS). <FIG> illustrates CRS for antenna ports <NUM>, <NUM>, <NUM>, and <NUM> (indicated as R<NUM>, R<NUM>, R<NUM>, and R<NUM>, respectively), UE-RS for antenna port <NUM> (indicated as R<NUM>), and CSI-RS for antenna port <NUM> (indicated as R). <FIG> illustrates an example of various channels within a DL subframe of a frame. The physical control format indicator channel (PCFICH) is within symbol <NUM> of slot <NUM>, and carries a control format indicator (CFI) that indicates whether the physical downlink control channel (PDCCH) occupies <NUM>, <NUM>, or <NUM> symbols (<FIG> illustrates a PDCCH that occupies <NUM> symbols). The PDCCH carries downlink control information (DCI) within one or more control channel elements (CCEs), each CCE including nine RE groups (REGs), each REG including four consecutive REs in an OFDM symbol. A UE may be configured with a UE-specific enhanced PDCCH (ePDCCH) that also carries DCI. The ePDCCH may have <NUM>, <NUM>, or <NUM> RB pairs (<FIG> shows two RB pairs, each subset including one RB pair). The physical hybrid automatic repeat request (ARQ) (HARQ) indicator channel (PHICH) is also within symbol <NUM> of slot <NUM> and carries the HARQ indicator (HI) that indicates HARQ acknowledgement (ACK) / negative ACK (NACK) feedback based on the physical uplink shared channel (PUSCH). The primary synchronization channel (PSCH) is within symbol <NUM> of slot <NUM> within subframes <NUM> and <NUM> of a frame, and carries a primary synchronization signal (PSS) that is used by a UE to determine subframe timing and a physical layer identity. The secondary synchronization channel (SSCH) is within symbol <NUM> of slot <NUM> within subframes <NUM> and <NUM> of a frame, and carries a secondary synchronization signal (SSS) that is used by a UE to determine a physical layer cell identity group number. Based on the PCI, the UE can determine the locations of the aforementioned DL-RS. The physical broadcast channel (PBCH) is within symbols <NUM>, <NUM>, <NUM>, <NUM> of slot <NUM> of subframe <NUM> of a frame, and carries a master information block (MIB). The MIB provides a number of RBs in the DL system bandwidth, a PHICH configuration, and a system frame number (SFN).

As illustrated in <FIG>, some of the REs carry demodulation reference signals (DM-RS) for channel estimation at the eNB. The UE may additionally transmit sounding reference signals (SRS) in the last symbol of a subframe. The SRS may be used by an eNB for channel quality estimation to enable frequency-dependent scheduling on the UL. <FIG> illustrates an example of various channels within an UL subframe of a frame. A physical random access channel (PRACH) may be within one or more subframes within a frame based on the PRACH configuration. The PRACH may include six consecutive RB pairs within a subframe. The PRACH allows the UE to perform initial system access and achieve UL synchronization. A physical uplink control channel (PUCCH) may be located on edges of the UL system bandwidth.

<FIG> is a block diagram of an eNB <NUM> in communication with a UE <NUM> in an access network.

The symbols on each subcarrier, and the reference signal, are recovered and demodulated by determining the most likely signal constellation points transmitted by the eNB <NUM>. The soft decisions are then decoded and deinterleaved to recover the data and control signals that were originally transmitted by the eNB <NUM> on the physical channel.

Similar to the functionality described in connection with the DL transmission by the eNB <NUM>, the controller/processor <NUM> provides RRC layer functionality associated with system information (e.g., MIB, SIBs) acquisition, RRC connections, and measurement reporting; PDCP layer functionality associated with header compression / decompression, and security (ciphering, deciphering, integrity protection, integrity verification); RLC layer functionality associated with the transfer of upper layer PDUs, error correction through ARQ, concatenation, segmentation, and reassembly of RLC SDUs, re-segmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs onto TBs, demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction through HARQ, priority handling, and logical channel prioritization.

Channel estimates derived by a channel estimator <NUM> from a reference signal or feedback transmitted by the eNB <NUM> may be used by the TX processor <NUM> to select the appropriate coding and modulation schemes, and to facilitate spatial processing.

The UL transmission is processed at the eNB <NUM> in a manner similar to that described in connection with the receiver function at the UE <NUM>.

Data encoding may be used in various communication systems (e.g., mmW communication systems) so that errors in a received message may be corrected and/or detected by the decoder of a receiver device. Linear block codes are a type of error-correcting codes that may be used to encode data in blocks.

One class of linear block codes are polar codes. Polar codes may generate data at a rate sufficient to transmit at channel capacity for symmetric binary-input discrete memoryless channels, and may be constructed on the basis of a probabilistic phenomenon referred to as "channel polarization. " In general, channel polarization refers to the observation that as the code length N grows large for polar codes, the "channels" associated with individual bits in an information vector u may asymptotically approach either a pure-noise channel or a pure-noiseless channel. The fraction of channels that become noiseless may be equal to the capacity of the channel in the limit case. Polar codes may be constructed by identifying the indices of the bits in the information vector u that are associated with channels approaching noise free conditions and by using the identified indices (or some subset of the identified indices) to transmit information (e.g., tones and/or signals), while setting the remaining indices to predetermined values known by both the encoder and decoder.

For a linear block code, the codewords may be related to the message (e.g., tone and/or signals) that is transmitted using a linear transformation. Since the codewords may be longer than the messages, the matrix that represents the linear transformation may be rectangular. In order to simplify the analysis of a received codeword, the input message at the decoder may be padded with extra bits that are constant (e.g., "frozen bits") in order to make the matrix square.

Polar decoding is conventionally performed using a serial cancellation decoding algorithm. The serial cancellation decoding algorithm may perform a soft estimation of the original information vector u. In general, due to the inherent data dependencies in the serial cancellation decoding algorithm, parallelization may not be exploited in implementing the algorithm. As a result, a polar decoder may suffer from low decoding throughput and high latency. There is a need for a polar encoding/decoding technique that provides lower latency.

<FIG> and <FIG> illustrate a data flow <NUM> for a first example of performing polar encoding of a signal that is transmitted from a transmitter device <NUM> to a receiver device <NUM> in accordance with certain aspects of the disclosure. The transmitter device <NUM> may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>'. The receiver device <NUM> may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, the apparatus <NUM>/<NUM>'. In one configuration, the transmitter device <NUM> may be a base station, and the receiver device <NUM> may be a UE. In certain other configurations, the transmitter device <NUM> may be a UE, and the receiver device <NUM> may be a base station. In <FIG> and <FIG>, optional operations are indicated with dashed lines.

In an aspect, the transmitter device <NUM> may include a polar encoder (e.g., see <FIG>) and the receiver device <NUM> may include a polar decoder (e.g., see <FIG>). In one aspect, the polar encoder of the transmitter device <NUM> and/or the polar decoder of the receiver device <NUM> may perform semi-parallel and/or parallel bit-reversal technique such that the latency associated with the serial bit-reversal of conventional polar encoding and/or polar decoding may be reduced.

In certain configurations, the (N, k) polar code of the present disclosure may encode information bits uA (e.g., k number of bits) into a codeword vector x of length N. For example, the transmitter device <NUM> may obtain a codeword vector x by multiplying information bits uA by an expansion matrix E to form an information vector u. The information vector u may be multiplied by a generator matrix F⊗log2N to obtain the codeword vector x. The codeword vector x may be transmitted to a receiver device <NUM> over a communication channel. A decoder at the receiver device <NUM> may receive a vector y that represents the codeword vector x with noise picked up during transmission on the communication channel. The decoder may process the vector y to produce an estimate ûA of the original information vector u.

Bit-reversal at the polar encoder and/or polar decoder may be implemented using a bit-reversal permutation matrix that permutes a sequence of m elements, where m = <NUM>k. Bit reversal may be defined as indexing m consecutive elements in a sequence of elements from <NUM> to m-<NUM> and then reversing binary sequences of each of the m consecutive elements. In other words, the most significant log2(m) bit (e.g., leftmost bit) may become the least significant log2(m) bit (e.g., rightmost bit), and vice versa after bit-reversal, and the least significant log2(m) may become the most signification log2(m) bit. Each of the m consecutive elements may be mapped to the new position given by the reordered indices of the m consecutive elements after bit-reversal. Bit reversal may increase the computational efficiency of radix-<NUM> FFT algorithms, where the recursive stages of the algorithm, operating in-place, imply a bit reversal of the inputs or outputs at the decoder of the receiver device <NUM>.

The transmitter device <NUM> may convert m consecutive elements into codeword vector x <NUM> (e.g., signals and/or tones) that are polar encoded and transmitted to the receiver device <NUM>. Transmitter device <NUM> may determine <NUM> indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index (e.g., <NUM> to m-<NUM>), and each of the m consecutive elements may include at least in part k information bits.

The transmitter device <NUM> may form <NUM> an information vector u by applying an expansion matrix E to the k information bits (of each of the m consecutive elements) to include additional bits in predetermined locations. For example, the additional bits may be j frozen bits (e.g., Os inserted at predetermined locations in each element). In an aspect, the information vector u may include N bits (e.g., (k information bits)+(j frozen bits)=N bits of the information vector u).

In addition, the transmitter device <NUM> may bit reverse <NUM> a binary sequence associated with each of the m consecutive elements. For example, the transmitter device <NUM> may bit reverse <NUM> the binary sequence associated with each of the m consecutive elements by applying a bit-reversal permutation matrix B to the information vector u. In an aspect, the binary sequence associated with each of the m consecutive elements may have a different log2(m) least significant bit.

In an aspect, each of the m consecutive elements may include a different binary sequence. Assuming m = <NUM>, the information vector u may include a four-element sequence u<NUM>, u<NUM>, u<NUM>, u<NUM>. By way of example, the first element u<NUM> may have an original binary sequence of <NUM>, the second element u<NUM> may have an original binary sequence of <NUM>, the third element u<NUM> may have an original binary sequence of <NUM>, and the fourth element u<NUM> may have an original binary sequence of <NUM>. That is, the binary sequence associated with index <NUM> in information vector u (e.g., u<NUM>) may be <NUM>, the binary sequence associated with index <NUM> in information vector u (e.g., u<NUM>) may be <NUM>, the binary sequence associated with index <NUM> in information vector u (e.g., u<NUM>) may be <NUM>, and the binary sequence associated with index <NUM> in information vector u (e.g., u<NUM>) may be <NUM>.

After bit-reversal, the first element u<NUM> may still have a binary sequence of <NUM>, a second element u<NUM> may have a bit-reversed binary sequence of <NUM>, a third element u<NUM> may have a non-bit reversed binary sequence of <NUM>, and the fourth element u<NUM> may still have a binary sequence of <NUM>. Each of the m consecutive elements may have a different most significant log2(m) bit after the binary sequence is bit-reversed. Based at least in part on the bit-reversed binary sequence associated with each of the m elements, the transmitter device <NUM> may determine <NUM> a bit-reversed order of the indices of the m consecutive elements. For example, the bit-reversed order of the indices of the four-element sequence described above may be u<NUM>, u<NUM>, u<NUM>, u<NUM>.

Referring to <FIG>, the transmitter device <NUM> may use the most significant log2(m) bit to select <NUM> a different memory (e.g., a memory bank) to write each of the m consecutive elements. By way of example, and not limitation, the memory bank may comprise a RAM, a ROM, an EEPROM, optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of memory banks, or any other medium that can be used to store the m consecutive elements. Additional details associated with the memory bank selection technique using the most significant log2(m) bit after determining <NUM> the bit-reversed order of the indices are described below with reference to <FIG>.

In one aspect, the transmitter device <NUM> may write <NUM> each of the m consecutive elements to a different memory bank in parallel (e.g., concurrently) based at least in part on the bit-reversed order of the indices.

To obtain the codeword vector x <NUM> (e.g., x = uAEBF) for transmission, transmitter device <NUM> may apply <NUM> a non-reversed encoding matrix F⊗log2N to information vector u. In an aspect, <MAT>. In one configuration, transmitter device <NUM> may apply <NUM> the non-reversed encoding matrix F⊗log2N before the bit-reversal permutation matrix B is applied to the information vector u, as discussed infra with respect to <FIG>. In another configuration, transmitter device <NUM> may apply <NUM> the non-reversed encoding matrix F⊗log2N after the bit-reversal permutation matrix B is applied to the information vector u, as discussed infra with respect to <FIG>.

An illustration of the bit-reversal technique described above with reference to <FIG> and <FIG> can be seen in <FIG>.

<FIG> illustrates a data flow <NUM> for a second example of performing polar encoding of a signal that is transmitted from a transmitter device <NUM> to a receiver device <NUM> in accordance with certain aspects of the disclosure. The transmitter device <NUM> may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>'. The receiver device <NUM> may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, the apparatus <NUM>/<NUM>'. In one configuration, the transmitter device <NUM> may be a base station, and the receiver device <NUM> may be a UE. In certain other configurations, the transmitter device <NUM> may be a UE, and the receiver device <NUM> may be a base station.

Referring to <FIG>, the transmitter device <NUM> may determine <NUM> indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In another aspect, each of the m consecutive elements may include at least in part k information bits.

The transmitter device <NUM> may determine <NUM> a permutation matrix π, and permute <NUM> the k information using the permutation matrix π.

After applying the permutation matrix π to the k information bits, the transmitter device <NUM> may form <NUM> an information vector u by applying a reversed expansion matrix E to the k information bits to include additional bits in bit-reversed predetermined locations. In an aspect, the information vector u may include N bits. The reversed expansion matrix E may insert frozen bits in bit-reversed locations without bit-reversing information bit locations. ET is the transpose of the expansion matrix E (e.g., discussed above with reference to <FIG> and <FIG>), and may remove frozen bits and keep information bits only. EET is a k x k identity matrix, and πE=EB, therefore π=EBET since EET=I. Therefore, the transmitter device <NUM> may be able to permute k bits instead of N bits, which may use a smaller circuit and enable parallel implementations to reduce latency.

The transmitter device <NUM> may apply <NUM> a non-reversed encoding matrix F⊗log2N to obtain a codeword vector x <NUM> (e.g., x=uAπEF) for transmission to the receiver device <NUM>. In one aspect, the non-reversed encoding matrix F⊗log2N may be applied after applying the reversed expansion matrix E. In another aspect, the non-reversed encoding matrix F⊗log2N may be applied at the same time as the reversed expansion matrix E.

An illustration of the bit-reversal technique described above with reference to the <FIG> can be seen in <FIG>.

<FIG> illustrates a data flow <NUM> for performing polar decoding of a signal received at a receiver device <NUM> from a transmitter device <NUM> in accordance with certain aspects of the disclosure. The transmitter device <NUM> may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>'. The receiver device <NUM> may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, the apparatus <NUM>/<NUM>'. In one configuration, the transmitter device <NUM> may be a base station, and the receiver device <NUM> may be a UE. In certain other configurations, the transmitter device <NUM> may be a UE, and the receiver device <NUM> may be a base station. In <FIG>, optional operations are indicated with dashed lines.

Referring to <FIG>, the receiver device <NUM> receives a codeword vector x <NUM> from the transmitter device <NUM>. The codeword vector x <NUM> includes m consecutive elements.

Receiver device <NUM> may determine <NUM> one or more log-likelihood ratios (LLRs) y associated with the codeword vector x <NUM>. In an aspect, the m consecutive elements may include the one or more LLRs. LLRs may be determined by a demodulator at the receiver device <NUM> that determines whether the bits in each of the m consecutive elements are more likely to be a <NUM> or a <NUM>, and how much more likely. The LLRs may be used for processing at the polar decoder (e.g., as an estimate of the m consecutive elements).

Receiver device <NUM> determines <NUM> indices associated with m consecutive elements. Each of the m consecutive elements is associated with a different index (e.g., <NUM> to m-<NUM>) and each of the m consecutive elements may include at least in part k information bits.

In addition, the receiver device <NUM> bit reverses <NUM> a binary sequence associated with each of the m consecutive elements by bit reversing <NUM> the binary sequence associated with each of the m consecutive elements (e.g., LLRs) by applying a bit-reversal permutation matrix B. In an aspect, the binary sequence associated with each of the m consecutive elements may have a different log2(m) least significant bit.

In an aspect, each of the m consecutive elements may include a different binary sequence. Assuming m = <NUM>, the m consecutive elements may include a four-element sequence u<NUM>, u<NUM>, u<NUM>, u<NUM>. For example, the first element u<NUM> may have an original binary sequence of <NUM>, the second element u<NUM> may have an original binary sequence of <NUM>, the third element u<NUM> may have an original binary sequence of <NUM>, and the fourth element u<NUM> may have an original binary sequence of <NUM>. That is, the binary sequence associated with index <NUM> in the m consecutive elements (e.g., u<NUM>) may be <NUM>, the binary sequence associated with index <NUM> the m consecutive elements (e.g., u<NUM>) may be <NUM>, the binary sequence associated with index <NUM> the m consecutive elements (e.g., u<NUM>) may be <NUM>, and the binary sequence associated with index <NUM> the m consecutive elements (e.g., u<NUM>) may be <NUM>.

After bit-reversal, the first element u<NUM> may still have a binary sequence of <NUM>, a second element u<NUM> may have a bit-reversed binary sequence of <NUM>, a third element u<NUM> may have a non-bit reversed binary sequence of <NUM>, and a fourth element u<NUM> may still have a binary sequence of <NUM>. Each of the m consecutive elements may have a different most significant log2(m) bit after the binary sequence is bit-reversed. Based at least in part on the bit-reversed binary sequence associated with each of the m elements, the receiver device <NUM> may determine <NUM> a bit-reversed order of the indices of the m consecutive elements. The bit-reversed order of the indices of the four-element sequence described above may be u<NUM>, u<NUM>, u<NUM>, u<NUM>.

Using the most significant log2(m) bit after determining <NUM> the bit-reversed order of the indices of the m consecutive elements, the receiver device <NUM> may select <NUM> a different memory bank to write each of the m consecutive elements. An illustration of the memory bank selection technique using the most significant log2(m) bit after determining <NUM> the bit-reversed order of the indices of can be seen in <FIG>.

The receiver device <NUM> writes <NUM> each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices. In an aspect, each memory bank may be as narrow as a single LLR.

The polar decoder at the receiver device <NUM> processes the bit-reversed m consecutive elements to produce an estimate ûA of the original information vector u. A description of the information vector u is discussed supra with respect to <FIG>, <FIG>, and <FIG>.

An illustration of the bit-reversal technique described above with respect to <FIG> can be seen in <FIG>.

<FIG> is a diagram <NUM> illustrating that the information vector u <NUM> may be bit-reversed <NUM> (e.g., using matrix B) before encoding <NUM> (e.g., using matrix F⊗log2N) and transmitted via channel <NUM> to the polar decoder <NUM> at the receiver device.

<FIG> is a diagram <NUM> illustrating that the information vector u <NUM> may be bit-reversed <NUM> (e.g., using matrix B) after encoding <NUM> (e.g., using matrix F⊗log2N) and transmitted via channel <NUM> to the polar decoder <NUM> at the receiver device.

<FIG> is a diagram <NUM> illustrating that the information vector u <NUM> may be encoded <NUM> (e.g., using matrix F⊗log2N) and transmitted via channel <NUM> to a receiver device that bit-reverses <NUM> (e.g., using matrix B) the codeword vector x before decoding <NUM> at the polar decoder <NUM>.

<FIG> is a diagram of the bit-reversal technique <NUM> used by a transmitter device in accordance with certain aspects of the disclosure. The transmitter device may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>'. The bit-reversal technique <NUM> may correspond to, e.g., the technique described supra with reference to <FIG> and <FIG>.

Referring to <FIG>, an (N, k) polar code may be used to encode information bits uA <NUM> (e.g., k number of bits) into a codeword vector x <NUM>. For example, information bits uA <NUM> may be multiplied by an expansion matrix E <NUM> to form an information vector u <NUM>. A permutation matrix B <NUM> may be applied to the information vector u <NUM> prior to being multiplied by a generator matrix F⊗log2N <NUM> to form the codeword vector x <NUM> (e.g., x = uAEBF). The codeword vector x <NUM> may be transmitted by the transmitter device to the receiver device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, <NUM>, the apparatus <NUM>/<NUM>').

<FIG> is a diagram of the bit-reversal technique <NUM> used by a transmitter device in accordance with certain aspects of the disclosure. The transmitter device may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>'. The bit-reversal technique <NUM> may correspond to, e.g., the technique described supra with reference to <FIG>.

Referring to <FIG>, the transmitter device may determine <NUM> indices associated with m consecutive elements uA <NUM>. In an aspect, each of the m consecutive elements uA <NUM> may be associated with a different index. In another aspect, each of the m consecutive elements uA <NUM> may include at least in part k information bits.

The transmitter device permute the k information bits of element uA <NUM> using the permutation matrix π <NUM>. After applying the permutation matrix π <NUM> to the k information bits, the transmitter device may form an information vector u <NUM> by applying a reversed expansion matrix E <NUM> to the k information bits to include additional bits in bit-reversed predetermined locations. In an aspect, the information vector u <NUM> may include N bits. The reversed expansion matrix E may insert frozen bits in bit-reversed locations without bit-reversing information bit locations.

The transmitter device may apply a non-reversed encoding matrix F⊗log2N <NUM> to obtain a codeword vector x <NUM> (e.g., x=uAπEF). In one aspect, the non-reversed encoding matrix F⊗log2N <NUM> may be applied after applying the reversed expansion matrix E <NUM>. In another aspect, the non-reversed encoding matrix F⊗log2N <NUM> may be applied concurrently with the reversed expansion matrix E <NUM>. The codeword vector x <NUM> may be transmitted by the transmitter device to the receiver device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, <NUM>, the apparatus <NUM>/<NUM>').

<FIG> is a diagram of the bit-reversal technique <NUM> used by a receiver device in accordance with certain aspects of the disclosure. The receiver device may correspond to, e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, <NUM>, the apparatus <NUM>/<NUM>'. The bit-reversal technique <NUM> illustrated in <FIG> may correspond to, e.g., the technique described above with respect to <FIG>.

The codeword vector x (e.g., see codeword vector x <NUM> illustrated in <FIG> and <FIG>) may be received as vector y <NUM> (e.g., codeword vector x with noise) by a receiver device over a communication channel. A decoder at the receiver device may receive a vector y <NUM> that represents the codeword vector x with noise picked up from the communication channel. The decoder <NUM> may process the vector y <NUM> to produce an estimate ûA <NUM> of the original information vector u <NUM>.

<FIG> is a diagram <NUM> illustrating a technique for memory banks selection using the most significant log2(m) bit after determining the bit-reversed order of the indices of the m consecutive elements in accordance with certain aspects of the disclosure. The memory bank selection technique may be used by a transmitter device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>').

In an aspect, each of the m consecutive elements may include a different binary sequence. Assuming m = <NUM>, the information vector u may include a four-element sequence u<NUM> <NUM>, u<NUM> <NUM>, u<NUM> <NUM>, u<NUM> <NUM>. By way of example, the first element u<NUM> <NUM> may have an original binary sequence of <NUM>, the second element u<NUM> <NUM> may have an original binary sequence of <NUM>, the third element u<NUM> <NUM> may have an original binary sequence of <NUM>, and the fourth element u<NUM> <NUM> may have an original binary sequence of <NUM>. That is, the binary sequence associated with index <NUM> in information vector u (e.g., u<NUM> <NUM>) may be <NUM>, the binary sequence associated with index <NUM> in information vector u (e.g., u<NUM> <NUM>) may be <NUM>, the binary sequence associated with index <NUM> in information vector u (e.g., u<NUM> <NUM>) may be <NUM>, and the binary sequence associated with index <NUM> (e.g., u<NUM> <NUM>) in information vector u may be <NUM>.

After bit-reversal, the first element u<NUM> <NUM> may still have a binary sequence of <NUM>, a second element u<NUM> <NUM> may have a bit-reversed binary sequence of <NUM>, a third element u<NUM> <NUM> may have a non-bit reversed binary sequence of <NUM>, and the fourth element u<NUM> <NUM> may still have a binary sequence of <NUM>. Each of the m consecutive elements may have a different most significant log2(m) bit after the binary sequence is bit-reversed. The bit-reversed order of the indices of the four-element sequence may be u<NUM> <NUM>, u<NUM> <NUM>, u<NUM> <NUM>, u<NUM> <NUM>. Hence, the first element u<NUM> <NUM> may be written to memory <NUM><NUM>, the third element u<NUM> <NUM> may be written to memory <NUM><NUM>, the second element u<NUM> <NUM> may be written to memory <NUM><NUM>, and the fourth element u<NUM> <NUM> may be written to memory <NUM><NUM>.

<FIG> is a flowchart <NUM> for a method of wireless communication. The method <NUM> may be performed using a transmitter device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>') in communication with a receiver device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, <NUM>, the apparatus <NUM>/<NUM>'). In one configuration, the transmitter device may be a base station, and the receiver device may be a UE. In one configuration, the transmitter device may be a UE, and the receiver device may be a base station. In <FIG>, optional operations are indicated with dashed lines.

At <NUM>, the transmitter device may determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In another aspect, each of the m consecutive elements may include at least in part k information bits. For example, referring to <FIG> and <FIG>, transmitter device <NUM> may determine <NUM> indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index (e.g., <NUM> to m-<NUM>) and each of the m consecutive elements may include at least in part k information bits.

At <NUM>, the transmitter device may form a vector by applying an expansion matrix to the k information bits to include additional bits in predetermined locations. In an aspect, the vector may include N bits. For example, referring to <FIG> and <FIG>, the transmitter device <NUM> may form <NUM> an information vector u by applying an expansion matrix E to the k information bits to include additional bits in predetermined locations. For example, the additional bits may be j frozen bits (e.g., Os inserted at predetermined locations in each element). In an aspect, the information vector u may include N bits (e.g., (k information bits)+(j frozen bits)=N bits of the information vector u).

At <NUM>, the transmitter device may bit reverse a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. In another aspect, each binary sequence associated with each of the m consecutive elements may have a different log2(m) least significant bits. In a further aspect, each of the m consecutive elements may have different log2(m) most significant bits after the binary sequence is bit-reversed. For example, referring to <FIG> and <FIG>, the transmitter device <NUM> may bit reverse <NUM> a binary sequence associated with each of the m consecutive elements. In an aspect, the binary sequence associated with each of the m consecutive elements may have a different log2(m) least significant bit. In an aspect, each of the m consecutive elements may include a different binary sequence. Assuming m = <NUM>, the information vector u may include a four-element sequence u<NUM>, u<NUM>, u<NUM>, u<NUM>. By way of example, the first element u<NUM> may have an original binary sequence of <NUM>, the second element u<NUM> may have an original binary sequence of <NUM>, the third element u<NUM> may have an original binary sequence of <NUM>, and the fourth element u<NUM> may have an original binary sequence of <NUM>. That is, the binary sequence associated with index <NUM> in information vector u may be <NUM>, the binary sequence associated with index <NUM> in information vector u may be <NUM>, the binary sequence associated with index <NUM> in information vector u may be <NUM>, and the binary sequence associated with index <NUM> in information vector u may be <NUM>. After bit-reversal, the first element u<NUM> may still have a binary sequence of <NUM>, a second element u<NUM> may have a bit-reversed binary sequence of <NUM>, a third element u<NUM> have a non-bit reversed binary sequence of <NUM>, and the fourth element u<NUM> may still have a binary sequence of <NUM>. Each of the m consecutive elements may have a different most significant log2(m) bit after the binary sequence is bit-reversed.

At <NUM>, the transmitter device may bit reverse a binary sequence associated with each of the m consecutive elements by applying a bit-reversal permutation matrix to the vector. For example, referring to <FIG> and <FIG>, the transmitter device <NUM> may bit reverse <NUM> the binary sequence associated with each of the m consecutive elements by applying a bit-reversal permutation matrix B to the information vector u.

At <NUM>, the transmitter device may determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. For example, referring to <FIG> and <FIG>, based at least in part on the bit-reversed binary sequence associated with each of the m elements, the transmitter device <NUM> may determine <NUM> a bit-reversed order of the indices of the m consecutive elements. Still assuming m = <NUM>, the bit-reversed order of the indices of the four-element sequence may be u<NUM>, u<NUM>, u<NUM>, u<NUM>.

At <NUM>, the transmitter device may apply a non-reversed encoding matrix after the bit-reversal permutation matrix is applied to the vector to obtain a signal for transmission. For example, referring to <FIG> and <FIG>, to obtain the codeword vector x <NUM> (e.g., x = uAEBF) for transmission, transmitter device <NUM> may apply <NUM> a non-reversed encoding matrix F⊗log2N to information vector u. In an aspect, F <MAT>. In one configuration, transmitter device <NUM> may apply <NUM> the non-reversed encoding matrix F⊗log2N before the bit-reversal permutation matrix B is applied to the information vector u, as discussed supra with respect to <FIG>. In another configuration, transmitter device <NUM> may apply <NUM> the non-reversed encoding matrix F⊗log2N after the bit-reversal permutation matrix B is applied to the information vector u, as discussed supra with respect to <FIG>.

At <NUM>, the transmitter device may select the different memory bank for each of the m consecutive elements based on the most significant log2(m) bits associated with each of the m consecutive element after the bit-reversed order of the indices is determined. For example, referring to <FIG> and <FIG>, using the most significant log2(m) bit after determining <NUM> the bit-reversed order of the indices of the m consecutive elements, the transmitter device <NUM> may select <NUM> a different memory bank to write each of the m consecutive elements. Additional details of the memory bank selection technique using the most significant log2(m) bit after determining <NUM> the bit-reversed order of the indices are described above with reference to <FIG>.

At <NUM>, the transmitter device may write each of the m consecutive elements to a different memory bank in parallel (e.g., concurrently)based at least in part on the bit-reversed order of the indices. For example, referring to <FIG> and <FIG>, the transmitter device <NUM> may write <NUM> each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.

At <NUM>, the transmitter device may transmit a signal includes at least the m consecutive elements to a receiver device. For example, referring to <FIG> and <FIG>, the transmitter device <NUM> may convert m consecutive bits of information (e.g., consecutive elements) into codeword vector x <NUM> (e.g., signals and/or tones) that are polar encoded and transmitted to the receiver device <NUM>.

<FIG> is a conceptual data flow diagram <NUM> illustrating the data flow between different means/components in an exemplary apparatus <NUM>. The apparatus may be a transmitter device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>') in communication with receiver device <NUM> (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, the apparatus <NUM>/<NUM>'). In one configuration, the apparatus <NUM> may be a base station, and the receiver device <NUM> may be a UE. In one configuration, the apparatus <NUM> may be a UE, and the receiver device <NUM> may be a base station.

The apparatus may include a reception component <NUM> that may be configured to receive uplink (UL) transmissions from receiver device <NUM>. The apparatus may also include a determination component <NUM> that may be configured to determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In another aspect, each of the m consecutive elements may include at least in part k information bits. Determination component <NUM> may be configured to send a signal associated with the k information bits to vector component <NUM>. Vector component <NUM> may be configured to form a vector by applying an expansion matrix to the k information bits to include additional bits in predetermined locations. In an aspect, the vector may include N bits. Vector component <NUM> may be configured to send a signal associated with the information vector u to bit-reversal component <NUM>. Bit-reversal component <NUM> may be configured to bit reverse a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. In another aspect, each binary sequence associated with each of the m consecutive elements may have a different log2(m) least significant bits. In a further aspect, each of the m consecutive elements may have different log2(m) most significant bits (MSB) after the binary sequence is bit-reversed. For example, bit-reversal component <NUM> may be configured to bit reverse a binary sequence associated with each of the m consecutive elements by applying a bit-reversal permutation matrix to the vector. Bit-reversal component <NUM> may be configured to send a signal associated with the bit-reversed binary sequence of each of the m consecutive elements to determination component <NUM>. Determination component <NUM> may be configured to determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. Determination component <NUM> may be configured to send a signal associated with the bit-reversed information vector u to encoding component <NUM>. Encoding component <NUM> may be configured to apply a non-reversed encoding matrix after the bit-reversal permutation matrix is applied to the vector to obtain a signal (e.g., codeword x) for transmission. Encoding component <NUM> may be configured to send a signal associated with codeword x to transmission component <NUM>. Transmission component <NUM> may be configured to transmit the codeword x to receiver device <NUM> in a downlink (DL) transmission. In addition, determination component <NUM> may be configured to send a signal associated with the MSB to selection component <NUM>. Selection component <NUM> may be configured to select a different memory bank for each of the m consecutive elements based on the most significant log2(m) bits associated with each of the m consecutive element after the bit-reversed order of the indices is determined. Selection component <NUM> may be configured to send a signal associated with the selected banks to write component <NUM>. Write component <NUM> may be configured to write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.

<FIG> is a diagram <NUM> illustrating an example of a hardware implementation for an apparatus <NUM>' employing a processing system <NUM>. The processing system <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing system <NUM> and the overall design constraints. The bus <NUM> links together various circuits including one or more processors and/or hardware components, represented by the processor <NUM>, the components <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and the computer-readable medium / memory <NUM>. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processing system <NUM> may be coupled to a transceiver <NUM>. The transceiver <NUM> is coupled to one or more antennas <NUM>. The transceiver <NUM> provides a means for communicating with various other apparatus over a transmission medium. The transceiver <NUM> receives a signal from the one or more antennas <NUM>, extracts information from the received signal, and provides the extracted information to the processing system <NUM>, specifically the reception component <NUM>. In addition, the transceiver <NUM> receives information from the processing system <NUM>, specifically the transmission component <NUM>, and based on the received information, generates a signal to be applied to the one or more antennas <NUM>. The processing system <NUM> includes a processor <NUM> coupled to a computer-readable medium / memory <NUM>. The processor <NUM> is responsible for general processing, including the execution of software stored on the computer-readable medium / memory <NUM>. The software, when executed by the processor <NUM>, causes the processing system <NUM> to perform the various functions described supra for any particular apparatus. The computer-readable medium / memory <NUM> may also be used for storing data that is manipulated by the processor <NUM> when executing software. The processing system <NUM> further includes at least one of the components <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. The components may be software components running in the processor <NUM>, resident/stored in the computer readable medium / memory <NUM>, one or more hardware components coupled to the processor <NUM>, or some combination thereof. The processing system <NUM> may be a component of the eNB <NUM> and may include the memory <NUM> and/or at least one of the TX processor <NUM>, the RX processor <NUM>, and the controller/processor <NUM>.

In one configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for determining indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In another aspect, each of the m consecutive elements may include at least in part k information bits. In another configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for forming a vector by applying an expansion matrix to the k information bits to include additional bits in predetermined locations. In an aspect, the vector may include N bits. In a further configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for bit reversing a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. In another aspect, each binary sequence associated with each of the m consecutive elements may have different log2(m) least significant bits. For example, the means for bit reversing the binary sequence associated with each of the m consecutive elements may be configured to apply a bit-reversal permutation matrix to the vector. In one configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for determining a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. In an aspect, each of the m consecutive elements may have different log2(m) most significant bits after the binary sequence is bit-reversed. In one configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for selecting the different memory bank for each of the m consecutive elements based on the most significant log2(m) bits associated with each of the m consecutive element after the bit-reversed order of the indices is determined. In a further configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for writing each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices. In another configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for applying a non-reversed encoding matrix after the bit-reversal permutation matrix is applied to the vector to obtain a signal for transmission.

<FIG> is a flowchart <NUM> for a method of wireless communication. The method <NUM> may be performed using a receiver device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, <NUM>, the apparatus <NUM>/<NUM>') in communication with a transmitter device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>'). In one configuration, the receiver device may be a base station, and the transmitter device may be a UE. In one configuration, the receiver device may be a UE, and the transmitter device may be a base station. In <FIG>, optional operations are indicated with dotted lines.

At <NUM>, the receiver device receives a signal from a transmitter, the signal includes the m consecutive elements. For example, referring to <FIG>, the receiver device <NUM> may receive a codeword vector x <NUM> from the transmitter device <NUM> wherein the codeword vector x <NUM> includes m consecutive elements.

At <NUM>, the receiver device may determine one or more LLRs associated with the signal. In an aspect, the m consecutive elements may include the one or more LLRs. For example, referring to <FIG>, receiver device <NUM> may determine <NUM> one or more log-likelihood ratios (LLRs) y associated with the codeword vector x <NUM>. In an aspect, the m consecutive elements may include the one or more LLRs. LLRs may be determined by a demodulator at the receiver device <NUM> that determines whether the bits in each of the m consecutive elements are more likely to be a <NUM> or a <NUM>, and how much more likely the bits are a <NUM> or a <NUM>.

At <NUM>, the receiver device determines indices associated with m consecutive elements, wherein each of the m consecutive elements is associated with a different index. Referring to <FIG>, receiver device <NUM> determines <NUM> indices associated with m consecutive wherein each of the m consecutive elements is associated with a different index (e.g., <NUM> to m-<NUM>) and each of the m consecutive elements may include at least in part k information bits.

At <NUM>, the receiver device bit reverses a binary sequence associated with each of the m consecutive elements. Each of the m consecutive elements includes a different binary sequence. In an aspect, each binary sequence associated with each of the m consecutive elements may have different log2(m) least significant bits. In another aspect, each of the m consecutive elements may have different log2(m) most significant bits after the binary sequence is bit-reversed. For example, referring to <FIG>, the receiver device <NUM> bit reverses <NUM> a binary sequence associated with each of the m consecutive elements. In an aspect, the binary sequence associated with each of the m consecutive elements may have a different log2(m) least significant bit. In an aspect, each of the m consecutive elements may include a different binary sequence. Assuming m = <NUM>, the m consecutive elements may include a four-element sequence u<NUM>, u<NUM>, u<NUM>, u<NUM>. For example, the first element u<NUM> may have an original binary sequence of <NUM>, the second element u<NUM> may have an original binary sequence of <NUM>, the third element u<NUM> may have an original binary sequence of <NUM>, and the fourth element u<NUM> may have an original binary sequence of <NUM>. That is, the binary sequence associated with index <NUM> in the m consecutive elements may be <NUM>, the binary sequence associated with index <NUM> the m consecutive elements may be <NUM>, the binary sequence associated with index <NUM> the m consecutive elements may be <NUM>, and the binary sequence associated with index <NUM> the m consecutive elements may be <NUM>. After bit-reversal, the first element u<NUM> may still have a binary sequence of <NUM>, a second element u<NUM> may have a bit-reversed binary sequence of <NUM>, a third element u<NUM> have a non-bit reversed binary sequence of <NUM>, and a fourth element u<NUM> may still have a binary sequence of <NUM>.

At <NUM>, the receiver device bit reverses a binary sequence associated with each of the m consecutive elements for example by applying a bit-reversal permutation matrix to the one or more LLRs. For example, referring to <FIG>, the receiver device <NUM> may bit reverse <NUM> the binary sequence associated with each of the m consecutive elements (e.g., LLRs) by applying a bit-reversal permutation matrix B.

At <NUM>, the receiver device determines a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. For example, referring to <FIG>, each of the m consecutive elements may have a different most significant log2(m) bit after the binary sequence is bit-reversed. Based at least in part on the bit-reversed binary sequence associated with each of the m elements, the receiver device <NUM> may determine <NUM> a bit-reversed order of the indices of the m consecutive elements. Still assuming m = <NUM>, the bit-reversed order of the indices of the four-element sequence may be u<NUM>, u<NUM>, u<NUM>, u<NUM>.

At <NUM>, the receiver device may decode the one or more LLRs to obtain information bits. Referring to <FIG>, the polar decoder at the receiver device <NUM> processes the bit-reversed m consecutive elements to produce an estimate ûA of the original information vector u.

At <NUM>, the receiver device may select the different memory bank for each of the m consecutive elements based on the most significant log2(m) bits associated with each of the m consecutive element after the bit-reversed order of the indices is determined. For example, referring to <FIG>, using the most significant log2(m) bit after determining <NUM> the bit-reversed order of the indices of the m consecutive elements, the receiver device <NUM> may select <NUM> a different memory bank to write each of the m consecutive elements.

At <NUM>, the receiver device writes each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices. Referring to <FIG>, the receiver device <NUM> writes <NUM> each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices. In an aspect, each memory bank may be as narrow as a single LLR.

<FIG> is a conceptual data flow diagram <NUM> illustrating the data flow between different means/components in an exemplary apparatus <NUM>. The apparatus may be a receiver device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, <NUM>, the apparatus <NUM>/<NUM>') in communication with a transmitter device <NUM> (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>'). In one configuration, the apparatus may be a base station, and the transmitter device may be a UE. In one configuration, the apparatus may be a UE, and the transmitter device may be a base station.

The apparatus may include a reception component <NUM> configured to receive a codeword x from transmitter device <NUM>. Reception component <NUM> may be configured to send a signal associated with codeword x to determination component <NUM>. Determination component <NUM> may be configured to determine one or more LLRs associated with the signal. In an aspect, the m consecutive elements may include the one or more LLRs. In addition, determination component <NUM> is configured to determine indices associated with m consecutive elements, wherein each of the m consecutive elements is associated with a different index. Determination component <NUM> may be configured to send a signal associated with the one or more LLRs to bit-reversal component <NUM>. Bit-reversal component <NUM> is configured to bit reverse a binary sequence associated with each of the m consecutive elements (e.g., LLRs). For example, bit-reversal component <NUM> may be configured to bit reverse a binary sequence associated with each of the m consecutive elements by applying a bit-reversal permutation matrix to the one or more LLRs. Each of the m consecutive elements includes a different binary sequence. In an aspect, each binary sequence associated with each of the m consecutive elements may have different log2(m) least significant bits. In another aspect, each of the m consecutive elements may have different log2(m) most significant bits after the binary sequence is bit-reversed. Bit-reversal component <NUM> may be configured to send a signal associated with the bit-revered LLRs to determination component <NUM>. Determination component <NUM> is configured to determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. Determination component <NUM> may be configured to send a signal associated with the bit-reversed indices of the m consecutive elements (e.g., LLRs) to decoding component <NUM>. Decoding component <NUM> may be configured to decode the one or more LLRs to obtain information bits. In addition, determination component <NUM> may be configured to send a signal associated with the MSB after the bit reversal to selection component <NUM>. Selection component <NUM> may be configured to select the different memory bank for each of the m consecutive elements based on the most significant log2(m) bits associated with each of the m consecutive element after the bit-reversed order of the indices is determined. Selection component <NUM> may be configured to send a signal associated with the selected banks to write component <NUM>. Write component <NUM> may be configured to write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices. The apparatus may also include a transmission component <NUM> that be configured to send transmissions to the transmitter device <NUM>.

<FIG> is a diagram <NUM> illustrating an example of a hardware implementation for an apparatus <NUM>' employing a processing system <NUM>. The processing system <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing system <NUM> and the overall design constraints. The bus <NUM> links together various circuits including one or more processors and/or hardware components, represented by the processor <NUM>, the components <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and the computer-readable medium / memory <NUM>. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processing system <NUM> may be coupled to a transceiver <NUM>. The transceiver <NUM> is coupled to one or more antennas <NUM>. The transceiver <NUM> provides a means for communicating with various other apparatus over a transmission medium. The transceiver <NUM> receives a signal from the one or more antennas <NUM>, extracts information from the received signal, and provides the extracted information to the processing system <NUM>, specifically the reception component <NUM>. In addition, the transceiver <NUM> receives information from the processing system <NUM>, specifically the transmission component <NUM>, and based on the received information, generates a signal to be applied to the one or more antennas <NUM>. The processing system <NUM> includes a processor <NUM> coupled to a computer-readable medium / memory <NUM>. The processor <NUM> is responsible for general processing, including the execution of software stored on the computer-readable medium / memory <NUM>. The software, when executed by the processor <NUM>, causes the processing system <NUM> to perform the various functions described supra for any particular apparatus. The computer-readable medium / memory <NUM> may also be used for storing data that is manipulated by the processor <NUM> when executing software. The processing system <NUM> further includes at least one of the components <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. The components may be software components running in the processor <NUM>, resident/stored in the computer readable medium / memory <NUM>, one or more hardware components coupled to the processor <NUM>, or some combination thereof. The processing system <NUM> may be a component of the UE <NUM> and may include the memory <NUM> and/or at least one of the TX processor <NUM>, the RX processor <NUM>, and the controller/processor <NUM>.

The apparatus <NUM>/<NUM>' for wireless communication includes means for receiving a signal from a transmitter, which includes the m consecutive elements. In another configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for determining one or more LLRs associated with the signal. In an aspect, the m consecutive elements may include the one or more LLRs. The apparatus <NUM>/<NUM>' for wireless communication includes means for determining indices associated with m consecutive elements associated with a different index. The apparatus <NUM>/<NUM>' for wireless communication includes means for bit reversing a binary sequence associated with each of the m consecutive elements, and each of the m consecutive elements includes a different binary sequence. In another aspect, each binary sequence associated with each of the m consecutive elements may have different log2(m) least significant bits. In a further aspect, each of the m consecutive elements may have different log2(m) most significant bits after the binary sequence is bit-reversed. For example, the means for bit reversing a binary sequence associated with each of the m consecutive may be configured to apply a bit-reversal permutation matrix to the one or more LLRs.

The apparatus <NUM>/<NUM>' for wireless communication includes means for determining a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. The apparatus <NUM>/<NUM>' for wireless communication includes means for selecting the different memory bank for each of the m consecutive elements which may be based on the most significant log2(m) bits associated with each of the m consecutive element after the bit-reversed order of the indices is determined. The apparatus <NUM>/<NUM>' for wireless communication includes means for writing each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices. In another configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for decoding the one or more LLRs to obtain information bits.

<FIG> is a flowchart <NUM> for a method of wireless communication. The method <NUM> may be performed using a transmitter device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>') in communication with a receiver device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, <NUM>, the apparatus <NUM>/<NUM>'). In one configuration, the transmitter device may be a base station, and the receiver device may be a UE. In one configuration, the transmitter device may be a UE, and the receiver device may be a base station. In <FIG>, optional operations are indicated with dotted lines.

At <NUM>, the transmitter device may determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In another aspect, each of the m consecutive elements may include at least in part k information bits. For example, referring to <FIG>, the transmitter device <NUM> may determine <NUM> indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In another aspect, each of the m consecutive elements may include at least in part k information bits.

At <NUM>, the transmitter device may determine a permutation matrix. For example, referring to <FIG>, the transmitter device <NUM> may determine <NUM> a permutation matrix π.

At <NUM>, the transmitter device may permute the k information bits. For example, referring to <FIG>, the transmitter device <NUM> may permute <NUM> the k information using the permutation matrix π.

At <NUM>, the transmitter device may form a vector by applying a reversed expansion matrix to the k information bits to include additional bits in bit-reversed predetermined locations. In an aspect, the vector may include N bits. For example, referring to <FIG>, after applying the permutation matrix π to the k information bits, the transmitter device <NUM> may form <NUM> an information vector u by applying a reversed expansion matrix E to the k information bits to include additional bits in bit-reversed predetermined locations. In an aspect, the information vector u may include N bits. The reversed expansion matrix E may insert frozen bits in bit-reversed locations without bit-reversing information bit locations. ET is the transpose of the expansion matrix E (e.g., described above with reference to <FIG> and <FIG>), and may remove frozen bits and keep information bits only. EET is a k x k identity matrix, and πE=EB, therefore π=EBET since EET=I. Therefore, the transmitter device <NUM> may be able to permute k instead of N bits, which may use a smaller circuit and enable highly-parallel implementations to reduce latency.

At <NUM>, the transmitter device may apply a non-reversed encoding matrix to obtain a signal for transmission. for example, referring to <FIG>, the transmitter device <NUM> may apply <NUM> a non-reversed encoding matrix F⊗log2N after to obtain a codeword vector x <NUM> (e.g., x=uAπEF) for transmission to the receiver device <NUM>. In one aspect, the non-reversed encoding matrix F⊗log2N may be applied after applying the reversed expansion matrix E. In another aspect, the non-reversed encoding matrix F⊗log2N may be applied at the same time as the reversed expansion matrix E.

<FIG> is a conceptual data flow diagram <NUM> illustrating the data flow between different means/components in an exemplary apparatus <NUM>. The apparatus may be a transmitter device (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the transmitter device <NUM>, <NUM>, the apparatus <NUM>/<NUM>', <NUM>/<NUM>') in communication with a receiver device <NUM> (e.g., the base station <NUM>, <NUM>, the eNB <NUM>, the UE <NUM>, <NUM>, <NUM>, the receiver device <NUM>, <NUM>, the apparatus <NUM>/<NUM>'). In one configuration, the apparatus may be a base station, and the receiver device may be a UE. In one configuration, the apparatus may be a UE, and the receiver device may be a base station. In <FIG>, optional operations are indicated with dotted lines.

The apparatus may include a reception component <NUM> that may be configured to receive transmission from the receiver device <NUM>. In addition, the apparatus may include a determination component <NUM> that may be configured to determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In another aspect, each of the m consecutive elements may include at least in part k information bits. In addition, determination component <NUM> may be configured to determine a permutation matrix. Determination component <NUM> may be configured to send a signal associated with the k information bits to permutation component <NUM>. Permutation component <NUM> may be configured to permute the k information bits using the permutation matrix. Permutation component <NUM> may be configured to send a signal associated with the permuted k information bits to vector component <NUM>. Vector component <NUM> may be configured to form a vector by applying a reversed expansion matrix to the k information bits to include additional bits in bit-reversed predetermined locations. In an aspect, the vector may include N bits. Vector component <NUM> may be configured to send a signal associated with the vector to encoding component <NUM>. Encoding component <NUM> may be configured to apply a non-reversed encoding matrix after the permutation matrix to obtain a signal (e.g., codeword vector x) for transmission. In addition, encoding component <NUM> may be configured to send a signal associated with the codeword vector x to transmission component <NUM>. Transmission component may be configured to send a signal associated with codeword vector x to receiver device <NUM>.

<FIG> is a diagram <NUM> illustrating an example of a hardware implementation for an apparatus <NUM>' employing a processing system <NUM>. The processing system <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing system <NUM> and the overall design constraints. The bus <NUM> links together various circuits including one or more processors and/or hardware components, represented by the processor <NUM>, the components <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and the computer-readable medium / memory <NUM>. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processing system <NUM> may be coupled to a transceiver <NUM>. The transceiver <NUM> is coupled to one or more antennas <NUM>. The transceiver <NUM> provides a means for communicating with various other apparatus over a transmission medium. The transceiver <NUM> receives a signal from the one or more antennas <NUM>, extracts information from the received signal, and provides the extracted information to the processing system <NUM>, specifically the reception component <NUM>. In addition, the transceiver <NUM> receives information from the processing system <NUM>, specifically the transmission component <NUM>, and based on the received information, generates a signal to be applied to the one or more antennas <NUM>. The processing system <NUM> includes a processor <NUM> coupled to a computer-readable medium / memory <NUM>. The processor <NUM> is responsible for general processing, including the execution of software stored on the computer-readable medium / memory <NUM>. The software, when executed by the processor <NUM>, causes the processing system <NUM> to perform the various functions described supra for any particular apparatus. The computer-readable medium / memory <NUM> may also be used for storing data that is manipulated by the processor <NUM> when executing software. The processing system <NUM> further includes at least one of the components <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>. The components may be software components running in the processor <NUM>, resident/stored in the computer readable medium / memory <NUM>, one or more hardware components coupled to the processor <NUM>, or some combination thereof. The processing system <NUM> may be a component of the eNB <NUM> and may include the memory <NUM> and/or at least one of the TX processor <NUM>, the RX processor <NUM>, and the controller/processor <NUM>.

The apparatus <NUM>/<NUM>' for wireless communication includes means for determining indices associated with m consecutive elements each associated with a different index. In another aspect, each of the m consecutive elements may include at least in part k information bits. In another configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for determining a permutation matrix. In a further configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for permuting the k information bits. In one configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for forming a vector by applying a reversed expansion matrix to the k information bits to include additional bits in bit-reversed predetermined locations. In an aspect, the vector may include N bits. In another configuration, the apparatus <NUM>/<NUM>' for wireless communication may include means for applying a non-reversed encoding matrix after the permutation matrix is applied to the vector to obtain a signal for transmission.

Claim 1:
A method for polar decoding a codeword vector (<NUM>) for wireless communication, the method performed by a receiver device (<NUM>),the method comprising:
receiving (<NUM>) a signal from a transmitter device (<NUM>), the signal including the codeword vector (<NUM>);
splitting the codeword vector (<NUM>) into m consecutive elements;
determining (<NUM>) indices associated with each of the m consecutive elements, each of the m consecutive elements associated with a different index;
bit reversing (<NUM>) a binary sequence of each of the m consecutive elements, each of the m consecutive elements include a different binary sequence;
determining (<NUM>) a bit-reversed order of the indices;
writing (<NUM>) each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices; and
polar decoding (<NUM>) the m consecutive elements after bit-reversal to produce an estimate of an original information vector.