Patent Description:
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.

For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure. Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend them into the, e.g. <NUM> or sub-<NUM> range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes. New layouts may be introduced either to accommodate or to enable such future technology nodes.

<CIT> discloses a static random-access memory circuit including at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.

<CIT> discloses a standard cell that is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.

In an embodiment, the first active region is an N-type doped active region, and the second, third and fourth active regions are P-type doped active regions.

In an embodiment, the first, second, third and fourth active regions are in first, second, third and fourth silicon fins, respectively.

In an embodiment, the ST RF bit cell has an L-shape.

Uniform layouts for SRAM and register file bit cells are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

One or more embodiments described herein are directed to uniform mask memory designs. Particular embodiments may include a layout-efficient technique of implementing <NUM>-transistor SRAM (6T SRAM) and <NUM>-transistor register file (8T RF) bit cells in advanced self-aligned process technologies.

To provide context, in conventional 6T SRAM and 8T RF bit cell layouts, the patterns created by trench contact plug formation, gate line plug formation, and fin trim are non-uniform. Such non-uniformity may not be compatible with advanced self-aligned process technology which may require uniform plug and mask patterns for such base layers. In order to accommodate conventional 6T SRAM and 8T RF layout under a given set of design rules, the corresponding bit cell would likely have to incur significant growth in terms of area, or alternatively, significant process risks may need to be taken by breaking uniform plug/mask pattern requirements.

For comparison with embodiments of the present disclosure, <FIG> illustrate a bit cell layout <NUM> and a schematic diagram <NUM>, respectively, for a conventional six transistor (6T) static random access memory (SRAM).

Referring to <FIG>, a bit cell area <NUM> includes therein gate lines <NUM> (which may also be referred to as poly lines). Trench contact lines <NUM> alternate with the gate lines <NUM>. The gate lines <NUM> and trench contact lines <NUM> are over NMOS diffusion regions <NUM> (e.g., P-type doped active regions, such as boron doped diffusion regions of an underlying substrate) and PMOS diffusion regions <NUM> (e.g., N-type doped active regions, such as phosphorous and/or arsenic doped diffusion regions of an underlying substrate). In the example of <FIG>, each of the NMOS diffusion regions <NUM> and the PMOS diffusion regions <NUM> has the same gate "width" which may be, e.g., a single semiconductor fin. Access transistors <NUM>, N-type cell transistors <NUM>, and P-type cell transistors <NUM> are formed from the gate lines <NUM> and the NMOS diffusion regions <NUM> and the PMOS diffusion regions <NUM>. Also depicted are a wordline (WL) <NUM>, a bit bar (BB) <NUM>, a bit line (BL) <NUM>, a bit line bar (BLB) <NUM>, internal node storage (BT) <NUM>, SRAM VCC <NUM>, and VSS <NUM>.

In contrast to <FIG>, <FIG> illustrate a bit cell layout <NUM> and a schematic diagram <NUM>, respectively, for a uniform six transistor (6T) static random access memory (SRAM), in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a bit cell area <NUM> includes therein gate lines <NUM> (which may also be referred to as poly lines). Trench contact lines <NUM> alternate with the gate lines <NUM>. The gate lines <NUM> and trench contact lines <NUM> are over a single NMOS diffusion regions <NUM> (e.g., a P-type doped active region, such as a boron doped diffusion region of an underlying substrate) and a single PMOS diffusion regions <NUM> (e.g., an N-type doped active region, such as a phosphorous and/or arsenic doped diffusion region of an underlying substrate). In the example of <FIG>, the NMOS diffusion region <NUM> and the PMOS diffusion region <NUM> has the same gate "width" which may be, e.g., a single semiconductor fin. Access transistors <NUM>, N-type cell transistors <NUM>, and P-type cell transistors <NUM> are formed from the gate lines <NUM> and the NMOS diffusion region <NUM> and the PMOS diffusion region <NUM>. Also depicted are a wordline (WL) <NUM>, a bit bar (BB) <NUM>, a bit line (BL) <NUM>, a bit line bar (BLB) <NUM>, internal node storage (BT) <NUM>, SRAM VCC <NUM>, and VSS <NUM>.

The layout of <FIG> is, in one embodiment, referred to as uniform mask SRAM. In such a uniform Mask 6T SRAM, one inverter-pass gate pair is rotated and flipped so as to abut with the other inverter-pass gate pair. The VCC and VSS terminals of the inverter are shared with the other inverter. In contrast to the four diffusion regions of <FIG>, only two diffusion regions are included in the layout of <FIG>. Additionally, in contrast to the two gate lines <NUM> of <FIG>, four gate lines <NUM> are used in the layout of <FIG>. As is applicable throughout the present disclosure, the four gate lines <NUM> may be referred to as being on tracks to form a grating structure. In an embodiment, the term "grating" for gate lines is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have gate lines spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach.

Referring more generally to <FIG>, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell <NUM> on a substrate. The 6T SRAM bit cell <NUM> includes first <NUM> and second <NUM> active regions parallel along a first direction (<NUM>) of the substrate. First, second, third and fourth gate lines <NUM> are over the first <NUM> and second <NUM> active regions. The first, second, third and fourth gate lines <NUM> are parallel along a second direction (<NUM>) of the substrate, the second direction (<NUM>) perpendicular to the first direction (<NUM>).

In one embodiment, the first active region <NUM> is an N-type doped active region, and the second active region <NUM> is a P-type doped active region. In one embodiment, the first <NUM> and second <NUM> active regions are in first and second silicon fins, respectively. In one embodiment, all individual ones of the first, second, third and fourth gate lines <NUM> are continuous between the first <NUM> and second <NUM> active regions, as is depicted in <FIG>. In one embodiment, the 6T SRAM bit cell <NUM> has a length along the first direction (<NUM>) and a length along the second direction (<NUM>), and the first length is greater than the second length, as is also depicted in <FIG>. In one embodiment, individual ones of the first, second, third and fourth gate lines <NUM> are spaced apart from one another by trench contact lines <NUM> parallel along the second direction (<NUM>) of the substrate, as is also depicted in <FIG>.

For comparison with embodiments of the present disclosure, <FIG> illustrate a bit cell layout <NUM> and a schematic diagram <NUM>, respectively, for a conventional eight transistor (8T) register file (RF).

Referring to <FIG>, a bit cell area <NUM> includes therein gate lines <NUM> (which may also be referred to as poly lines). Trench contact lines <NUM> alternate with the gate lines <NUM>. The gate lines <NUM> and trench contact lines <NUM> are over NMOS diffusion regions <NUM> (e.g., P-type doped active regions, such as boron doped diffusion regions of an underlying substrate) and PMOS diffusion regions <NUM> (e.g., N-type doped active regions, such as phosphorous and/or arsenic doped diffusion regions of an underlying substrate). In the example of <FIG>, with the exception of the lowermost diffusion region, each of the NMOS diffusion regions <NUM> and the PMOS diffusion regions <NUM> has the same gate "width" which may be, e.g., a single semiconductor fin. The lowermost NMOS diffusion region <NUM> has relatively double the gate "width" which may be, e.g., a pair of semiconductor fins. The lowermost NMOS diffusion region <NUM> is a diffusion region of a read port <NUM>. Access transistors <NUM>, N-type cell transistors <NUM>, P-type cell transistors <NUM>, and read port transistors (R0, R1) <NUM> are formed from the gate lines <NUM> and the NMOS diffusion regions <NUM> and the PMOS diffusion regions <NUM>. Also depicted are a write wordline (WWL) <NUM>, a read wordline (RWL) <NUM>, a bit bar (BB) <NUM>, a write bit line (BL) <NUM>, a read bit line (BL) <NUM>, a write bit line bar (BLB) <NUM>, internal node storage (BT) <NUM>, RF VCC <NUM>, and VSS <NUM>.

In contrast to <FIG>, <FIG> illustrate a bit cell layout and a schematic diagram, respectively, for a uniform eight transistor (8T) register file (RF), in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a bit cell area <NUM> includes therein gate lines <NUM> (which may also be referred to as poly lines). Trench contact lines <NUM> alternate with the gate lines <NUM>. The gate lines <NUM> and trench contact lines <NUM> are over NMOS diffusion regions <NUM> (e.g., P-type doped active regions, such as boron doped diffusion regions of an underlying substrate) and a single PMOS diffusion region <NUM> (e.g., an N-type doped active region, such as a phosphorous and/or arsenic doped diffusion region of an underlying substrate). In the example of <FIG>, each of the NMOS diffusion regions <NUM> and the PMOS diffusion region <NUM> has the same gate "width" which may be, e.g., a single semiconductor fin. Additionally, the lowermost two NMOS diffusion regions <NUM> are diffusion regions of a read port <NUM>. Access transistors <NUM>, N-type cell transistors <NUM>, P-type cell transistors <NUM>, and read port transistors (R0, R1) <NUM> and <NUM> are formed from the gate lines <NUM> and the NMOS diffusion regions <NUM> and the PMOS diffusion region <NUM>. Also depicted are a write wordline (WWL) <NUM>, a read wordline (RWL) <NUM>, a bit bar (BB) <NUM>, a write bit line (BL) <NUM>, a read bit line (BL) <NUM>, a write bit line bar (BLB) <NUM>, internal node storage (BT) <NUM>, RF VCC <NUM>, and VSS <NUM>.

The layout of <FIG> is, in one embodiment, referred to as uniform mask RF. In such a uniform Mask 8T RF, one inverter-pass gate pair is rotated and flipped so as to abut with the other inverter-pass gate pair. The VCC and VSS terminals of the inverter are shared with the other inverter. The read port is coupled to the storage node (BT) of one of the inverter pair and as a result, forms an L-shaped structure. In contrast to the five diffusion regions of <FIG>, only four diffusion regions are included in the layout of <FIG>. Additionally, in contrast to the two gate lines <NUM> of <FIG>, four gate lines <NUM> are used in the layout of <FIG>.

Referring more generally to <FIG>, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes an eight transistor (8T) register file (RF) bit cell <NUM> on a substrate. The 8T RF bit cell <NUM> includes first <NUM>, second <NUM>, third <NUM> and fourth <NUM> active regions (from top to bottom of <FIG>) parallel along a first direction (<NUM>) of the substrate. First and second gate lines <NUM> (the two gate lines <NUM> on left-hand side of <FIG>) are over the first <NUM>, second <NUM>, third <NUM> and fourth <NUM> active regions. The first and second gate lines <NUM> are parallel along a second direction of the substrate (<NUM>), the second direction (<NUM>) perpendicular to the first direction (<NUM>). Third and fourth gate lines <NUM> (the two gate lines <NUM> on right-hand side of <FIG>) are over the first <NUM> and second <NUM> active region, but not over the third <NUM> and fourth <NUM> active regions. The third and fourth gate lines <NUM> are parallel along the second direction (<NUM>) of the substrate.

In one embodiment, the first active region <NUM> is an N-type doped active region, and the second <NUM>, third <NUM> and fourth <NUM> active regions are P-type doped active regions. In one embodiment, the first <NUM>, second <NUM>, third <NUM> and fourth <NUM> active regions are in first, second, third and fourth silicon fins, respectively. In one embodiment, the first gate line <NUM> (furthest to the left) is discontinuous between the second <NUM> and third <NUM> active regions, and the second gate line <NUM> (next furthest to left) is continuous between the second <NUM> and third <NUM> active regions, as is depicted in <FIG>. In one embodiment, the 8T RF bit cell <NUM> has an L-shape, as is also depicted in <FIG>. In one embodiment, individual ones of the first, second, third and fourth gate lines <NUM> are spaced apart from one another by trench contact lines <NUM> parallel along the second direction (<NUM>) of the substrate, as is also depicted in <FIG>.

In an embodiment, a consistent number of fins is used for all NMOS devices for the 8T RF bit cell. The read port uses two <NUM>-fin NMOS devices to realize a <NUM>-grid device, whereas a <NUM>-fin device is used in the conventional RF. In an embodiment, the same local environment is used for all devices for the 8T RF bit cell. The read port NMOS devices is surrounded by the same <NUM>-fin devices from the inverter NMOS. The write wordline has the same poly and via connections and geometries.

In an embodiment, layouts described herein are compatible with uniform plug and mask patterns, including a uniform fin trim mask. Layouts may be compatible with non-EUV processes. Additionally, layouts may only require use of a uniform rectangular fin trim mask shape. Embodiments described herein may enable increased density in terms of area compared to the conventional 6T SRAM and 8T RF laid out with uniform plug and fin trim patterns.

In an embodiment, power supply terminals are used that are not shared across rows within a column which is a key enabler for row-based circuit techniques (e.g., sleep, assist). In contrast, the conventional 6T SRAM and 8T RF bit cell is limited to column-based circuit techniques due to having shared power terminals across rows within a column. Embodiments may include common and local power and ground (shared source) for the two NMOS and two PMOS devices of the cross coupled inverters inside the 6T SRAM and 8T RF core as well as the read port of the 8T RF bit cell. In one such embodiment, IR-drop, power delivery, and noise immunity of the bit cell are improved.

In an embodiment, for 8T RF, fewer metal-<NUM> layers are required compared to the conventional 8T RF (nominally, about <NUM> versus about <NUM>). Embodiments may enable improved metal-<NUM> track sharing compared to the conventional 6T SRAM and 8T RF implementation due to usage of more poly pitches (<NUM> versus <NUM>) per physical bit cell. In one such embodiment, flexibility on metal-<NUM> cut locations (e.g., gate versus trench contact) is improved. In an embodiment, the 6T SRAM and the 6T portion of the 8T RF is symmetric along the inverter (P, N) while the pass gate (XT, XB) extends from the inverter N device to form a "butterfly" topology.

For comparison with embodiments of the present disclosure, <FIG> illustrates a four-bit cell layout <NUM> for a conventional six transistor (6T) static random access memory (SRAM).

Referring to <FIG>, four layouts of the type <NUM> are shown as neighboring bit cell areas <NUM>. Gate lines <NUM> alternate with trench contact lines <NUM>. The gate lines <NUM> and trench contact lines <NUM> are over NMOS diffusion regions <NUM> and PMOS diffusion regions <NUM>.

In contrast to <FIG>, <FIG> illustrates a four-bit cell layout for a uniform six transistor (6T) static random access memory (SRAM), in accordance with an embodiment of the present disclosure.

For comparison with embodiments of the present disclosure, <FIG> illustrates a four-bit cell layout for a conventional eight transistor (8T) register file (RF).

In contrast to <FIG>, <FIG> illustrates a four-bit cell layout for a uniform eight transistor (8T) register file (RF), in accordance with an embodiment of the present disclosure.

In another aspect, the uniform mask <NUM>-read <NUM>-write 8T RF can be extended to support a <NUM>-read <NUM>-write 10T RF, where a second read port is laid out opposite a first read port. As an example, <FIG> illustrates a layout <NUM> for a uniform ten transistor (10T) <NUM>-read <NUM>-write register file (RF), in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a bit cell area <NUM> includes therein gate lines <NUM> (which may also be referred to as poly lines). Trench contact lines <NUM> alternate with the gate lines <NUM>. The gate lines <NUM> and trench contact lines <NUM> are over NMOS diffusion regions <NUM> (e.g., P-type doped active regions, such as boron doped diffusion regions of an underlying substrate) and a single PMOS diffusion region <NUM> (e.g., an N-type doped active region, such as a phosphorous and/or arsenic doped diffusion region of an underlying substrate). In the example of <FIG>, each of the NMOS diffusion regions <NUM> and the PMOS diffusion region <NUM> has the same gate "width" which may be, e.g., a single semiconductor fin. Access transistors <NUM>, N-type cell transistors <NUM>, P-type cell transistors <NUM>, and read port transistors <NUM> are formed from the gate lines <NUM> and the NMOS diffusion regions <NUM> and the PMOS diffusion region <NUM>. Also depicted are a write wordline (WWL) <NUM>, read wordlines (RWL) 919A/919B, a bit bar (BB) <NUM>, a write bit line (BL) <NUM>, read bit lines (BL) 923A/923B, a write bit line bar (BLB) <NUM>, internal node storage (BT) <NUM>, RF VCC <NUM>, and VSS <NUM>.

Referring more generally to <FIG>, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a ten transistor (10T) <NUM>-read <NUM>-write register file (RF) bit cell <NUM> on a substrate. The 10T <NUM>-read <NUM>-write RF bit cell <NUM> includes first <NUM>, second <NUM>, third <NUM> and fourth <NUM> active regions (from top to bottom of <FIG>) parallel along a first direction (<NUM>) of the substrate. First, second, third and fourth gate lines <NUM> are over the first <NUM>, second <NUM>, third <NUM> and fourth <NUM> active regions. The first, second, third and fourth gate lines <NUM> are parallel along a second direction (<NUM>) of the substrate, the second direction (<NUM>) perpendicular to the first direction (<NUM>). The first, third and fourth gate lines <NUM> (as taken from the left-hand-side of <FIG> to the right-hand side of <FIG>) are discontinuous between the second and third active regions, and the second gate line is continuous between the second and third active regions, as is depicted in <FIG>.

In one embodiment, the first active region <NUM> is an N-type doped active region, and the second, third and fourth active regions <NUM> are P-type doped active regions. In one embodiment, the first <NUM>, second <NUM>, third <NUM> and fourth <NUM> active regions are in first, second, third and fourth silicon fins, respectively. In one embodiment, individual ones of the first, second, third and fourth gate lines <NUM> are spaced apart from one another by trench contact lines <NUM> parallel along the second direction (<NUM>) of the substrate, as is depicted in <FIG>.

In another aspect, a variation of the <NUM>-read <NUM>-write 10T RF includes balanced loading on the state nodes (BT, BB) of the RF, where a first read port is coupled to a state node BT, and a second read port is coupled to a complementary state node BB. When the second read port is accessed, an inverted value is read out. As an example, <FIG> illustrates a layout <NUM> for a uniform ten transistor (10T) <NUM>-read <NUM>-write register file (RF) with balanced load, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a bit cell area <NUM> includes therein gate lines <NUM> (which may also be referred to as poly lines). Trench contact lines <NUM> alternate with the gate lines <NUM>. The gate lines <NUM> and trench contact lines <NUM> are over NMOS diffusion regions <NUM> (e.g., P-type doped active regions, such as boron doped diffusion regions of an underlying substrate) and a single PMOS diffusion region <NUM> (e. , an N-type doped active region, such as a phosphorous and/or arsenic doped diffusion region of an underlying substrate). In the example of <FIG>, each of the NMOS diffusion regions <NUM> and the PMOS diffusion region <NUM> has the same gate "width" which may be, e.g., a single semiconductor fin. Access transistors <NUM>, N-type cell transistors <NUM>, P-type cell transistors <NUM>, and read port transistors <NUM> are formed from the gate lines <NUM> and the NMOS diffusion regions <NUM> and the PMOS diffusion region <NUM>. Also depicted are a write wordline (WWL) <NUM>, read wordlines (RWL) 1019A/1019B, a bit bar (BB) <NUM>, a write bit line (BL) <NUM>, read bit lines (BL) 1023A/1023B, a write bit line bar (BLB) <NUM>, internal node storage (ET) <NUM>, RF VCC <NUM>, and VSS <NUM>.

Referring more generally to <FIG>, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a ten transistor (10T) <NUM>-read <NUM>-write register file (RF) bit cell <NUM> on a substrate. The 10T <NUM>-read <NUM>-write RF bit cell <NUM> includes first <NUM>, second <NUM>, third <NUM> and fourth <NUM> active regions (from top to bottom of <FIG>) parallel along a first direction (<NUM>) of the substrate. First, second, third and fourth gate lines <NUM> are over the first <NUM>, second <NUM>, third <NUM> and fourth <NUM> active regions. The first, second, third and fourth gate lines <NUM> are parallel along a second direction (<NUM>) of the substrate, the second direction (<NUM>) perpendicular to the first direction (<NUM>). The first and fourth gate lines <NUM> (as taken from the left-hand-side of <FIG> to the right-hand side of <FIG>) are discontinuous between the second and third active regions, and the second and third gate lines <NUM> are continuous between the second and third active regions, as is depicted in <FIG>.

In accordance with an embodiment of the present disclosure, a uniform mask SRAM or RF approach as described above provides a layout-efficient memory implementation in advanced self-aligned process technologies. Advantages may be realized in terms of die area and memory performance. Circuit techniques may be uniquely enabled by such layout approaches. One or more embodiments described herein are directed to the integration of semiconductor devices, such as metal oxide semiconductor (MOS) device integration. As an example, <FIG> illustrates a cross-sectional view of a non-planar semiconductor device, in accordance with an embodiment of the present disclosure. <FIG> illustrates a plan view taken along the a-a' axis of the semiconductor device of <FIG>, in accordance with an embodiment of the present disclosure.

Referring to <FIG>, a semiconductor structure or device <NUM> includes a non-planar active region (e.g., a fin structure including protruding fin portion <NUM> and sub-fin region <NUM>) formed from substrate <NUM>, and within isolation region <NUM>. A gate line <NUM> is disposed over the protruding portions <NUM> of the non-planar active region as well as over a portion of the isolation region <NUM>. As shown, gate line <NUM> includes a gate electrode <NUM>/<NUM> and a gate dielectric layer <NUM>. In one embodiment, gate line <NUM> may also include a dielectric cap layer <NUM>. A gate contact <NUM>, and overlying gate contact via <NUM> are also seen from this perspective, along with an overlying metal interconnect <NUM>, all of which are disposed in inter-layer dielectric stacks or layers <NUM>.

Also seen from the perspective of <FIG>, the gate contact <NUM> is, in one embodiment, disposed over isolation region <NUM>, but not over the non-planar active regions. However, the arrangement of semiconductor structure or device <NUM> places the gate contact over isolation regions. Such an arrangement may, for certain technology nodes be viewed as inefficient use of layout space in certain applications. In another embodiment, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region.

It is to be appreciated that, for convenience of illustration, the gate line <NUM> is shown over three protruding fin portions <NUM>, but is not limited as such. For example, a gate line can be formed over <NUM>, <NUM>, <NUM> or even more protruding fin portions. As is applicable throughout the present disclosure, the protruding fin portions <NUM> may be referred to as forming a grating structure. In an embodiment, the term "grating" for protruding fin portions <NUM> is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have protruding fin portions <NUM> spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach.

Referring to <FIG>, the gate line <NUM> is shown as disposed over the protruding fin portions <NUM>. Source and drain regions 1104A and 1104B of the protruding fin portions <NUM> can be seen from this perspective. In one embodiment, the source and drain regions 1104A and 1104B are doped portions of original material of the protruding fin portions <NUM>. In another embodiment, the material of the protruding fin portions <NUM> is removed and replaced with another semiconductor material, e.g., by epitaxial deposition. In either case, the source and drain regions 1104A and 1104B may extend below the height of dielectric layer <NUM>, i.e., into the sub-fin region <NUM>.

In an embodiment, the semiconductor structure or device <NUM> is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode and gate electrode materials of gate lines <NUM> surround at least a top surface and a pair of sidewalls of the three-dimensional body.

Substrate <NUM> may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, substrate <NUM> is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, antimony, boron, gallium or a combination thereof, to form active region <NUM>. In one embodiment, the concentration of silicon atoms in bulk substrate <NUM> is greater than <NUM>%. In another embodiment, bulk substrate <NUM> is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. Bulk substrate <NUM> may alternatively be composed of a group III-V material. In an embodiment, bulk substrate <NUM> is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate <NUM> is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, magnesium, beryllium, zinc, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

Isolation region <NUM> may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the isolation region <NUM> is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

In an embodiment, the gate dielectric layer <NUM> is composed of a high-K material. For example, in one embodiment, the gate dielectric layer <NUM> is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate <NUM>. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer <NUM> is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride.

In an embodiment, layer <NUM> of the gate electrode <NUM>/<NUM> is composed of a non-workfunction-setting conductive fill material formed above a workfunction-setting layer <NUM>. In a particular embodiment, the transistor <NUM> is an N-type (NMOS) transistor, and the workfunction-setting layer <NUM> is an N-type workfunction. In another particular embodiment, the transistor <NUM> is a P-type (PMOS) transistor, and the workfunction-setting layer <NUM> has a P-type workfunction.

In one such embodiment, the conductive fill material <NUM> includes a material such as but not limited to, tungsten (W), aluminum (Al), or copper (Cu). In one embodiment, one or more conductive barrier layers (such as titanium nitride or tantalum nitride) is between layers <NUM> and <NUM> of the gate electrode. In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In an embodiment, the dielectric cap layer <NUM> and/or dielectric spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent or overlying conductive contacts, such as self-aligned contacts. For example, in one embodiment, the dielectric cap layer <NUM> and/or dielectric spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Gate contact <NUM>, overlying gate contact via <NUM>, and/or overlying metal interconnect <NUM> may be composed of a conductive material. In an embodiment, one or more of the contacts, interconnects or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material). In a particular embodiment, one or more of gate contact <NUM>, overlying gate contact via <NUM>, or overlying metal interconnect <NUM> includes a barrier layer and a conductive fill material. In one such embodiment, the barrier layer is composed of titanium and/or titanium nitride or tantalum and/or tantalum nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

In an embodiment, inter-layer dielectric stacks or layers <NUM> are composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO<NUM>)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment (although not shown), providing structure <NUM> involves formation of a contact pattern which is essentially perfectly aligned to an existing gate pattern while eliminating the use of a lithographic step with exceedingly tight registration budget. In one such embodiment, this approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

Furthermore, the gate stack structure <NUM> may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF<NUM>. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure <NUM>. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e. , after a gate dielectric layer is formed, is performed at a temperature greater than approximately <NUM> degrees Celsius. The anneal is performed prior to formation of the permanent contacts.

In an embodiment, prior to (e. , in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e. , for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separate patterning of contact features. In a particular embodiment, each of the trench contacts includes a barrier layer and a conductive fill material. In one such embodiment, the barrier layer is composed of titanium and/or titanium nitride or tantalum and/or tantalum nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such
as a trigate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a <NUM> nanometer (<NUM>) or smaller technology node.

In an embodiment, as is also used throughout the present description, lithographic operations are performed using <NUM> immersion lithography (i193), extreme ultra-violet (EUV) and/or electron beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

<FIG> illustrates a computing device <NUM> in accordance with one implementation of the disclosure. The computing device <NUM> houses a board <NUM>. The board <NUM> may include a number of components, including but not limited to a processor <NUM> and at least one communication chip <NUM>. The processor <NUM> is physically and electrically coupled to the board <NUM>. In some implementations the at least one communication chip <NUM> is also physically and electrically coupled to the board <NUM>. In further implementations, the communication chip <NUM> is part of the processor <NUM>.

Depending on its applications, computing device <NUM> may include other components that may or may not be physically and electrically coupled to the board <NUM>. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor <NUM> of the computing device <NUM> includes an integrated circuit die packaged within the processor <NUM>. In some implementations of the disclosure, the integrated circuit die of the processor includes uniform layouts for SRAM or register file bit cells, in accordance with implementations of embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip <NUM> also includes an integrated circuit die packaged within the communication chip <NUM>. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes uniform layouts for SRAM or register file bit cells, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device <NUM> may contain an integrated circuit die that includes uniform layouts for SRAM or register file bit cells, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device <NUM> may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device <NUM> may be any other electronic device that processes data.

<FIG> illustrates an interposer <NUM> that includes one or more embodiments of the disclosure. The interposer <NUM> is an intervening substrate used to bridge a first substrate <NUM> to a second substrate <NUM>. The first substrate <NUM> may be, for instance, an integrated circuit die. The second substrate <NUM> may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer <NUM> is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer <NUM> may couple an integrated circuit die to a ball grid array (BGA) <NUM> that can subsequently be coupled to the second substrate <NUM>. In some embodiments, the first and second substrates <NUM>/<NUM> are attached to opposing sides of the interposer <NUM>. In other embodiments, the first and second substrates <NUM>/<NUM> are attached to the same side of the interposer <NUM>. And in further embodiments, three or more substrates are interconnected by way of the interposer <NUM>.

The interposer <NUM> may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects <NUM> and vias <NUM>, including but not limited to through-silicon vias (TSVs) <NUM>. The interposer <NUM> may further include embedded devices <NUM>, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radiofrequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer <NUM>. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer <NUM>.

Thus, embodiments described herein include uniform layouts for SRAM and register file bit cells.

The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

Claim 1:
An integrated circuit structure, comprising:
a substrate;
a six transistor (6T) static random access memory (SRAM) bit cell (<NUM>) on the substrate, the 6T SRAM bit cell (<NUM>) comprising:
first (<NUM>) and second (<NUM>) active regions parallel along a first direction (<NUM>) of the substrate; and
first, second, third and fourth gate lines (<NUM>), the first, second, third and fourth gate lines (<NUM>) parallel along a second direction (<NUM>) of the substrate, the second direction (<NUM>) perpendicular to the first direction (<NUM>);
characterized in that
the first, second, third and fourth gate lines (<NUM>) are vertically over the first (<NUM>) and second (<NUM>) active regions.