Patent Description:
Until now, a time delay integration (TDI) sensor has been used in the field of factory automation (FA) or aerial capturing. The TDI sensor performs TDI processing of integrating the amount of electric charge with shifting in time corresponding to the speed of movement of a subject. For example, a solid-state image pickup element has been proposed that performs TDI processing with a charge coupled device (CCD) that transfers electric charge with shifting in time and a circuit that accumulates the amount of electric charge thereof in a floating diffusion layer to generate an integral signal (for example, refer to NPL <NUM>). <CIT>, <CIT>, <CIT> provide further insigths into solid-state image sensor functionalities.

In the related art, improvement in brightness and noise reduction are carried out by the TDI processing. However, in the above solid-state image pickup element, as the number of pixels increases at the source from which electric charge is transferred, the capacity of the floating diffusion layer needs increasing at the destination to which electric charge is transferred. The increase of the capacity causes deterioration in pixel sensitivity, and then the image quality of image data deteriorates due to the deterioration in pixel sensitivity. As above, the solid-state image pickup element has a problem with deterioration in image quality due to deterioration in sensitivity.

The present technology has been made in consideration of such a situation. There is a need for improvement in image quality in a solid-state image pickup element that performs time delay integration.

The above problem is solved by the claimed subject-matter, which defines the present invention, Embodiments not covered by the claimed subj ect-matter are no part of the present invention.

Improvement can be made in pixel sensitivity with a small capacity of floating diffusion layer, in comparison to a case where the amount of electric charge of a plurality of pixels is transferred to a floating diffusion layer. The improvement in pixel sensitivity enables improvement in the image quality of image data.

Modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described below. The descriptions will be given in the following order.

<FIG> is a block diagram of an exemplary configuration of an image pickup apparatus <NUM> in a first embodiment of the present technology. The image pickup apparatus <NUM> that captures image data, includes an optical unit <NUM>, a solid-state image pickup element <NUM>, a storage unit <NUM>, a control unit <NUM>, and a communication unit <NUM>.

The optical unit <NUM> condenses incident light and guides the incident light to the solid-state image pickup element <NUM>. The solid-state image pickup element <NUM> captures image data. The solid-state image pickup element <NUM> supplies the image data to the storage unit <NUM> through a signal line <NUM>.

The storage unit <NUM> stores the image data. The control unit <NUM> controls the solid-state image pickup element <NUM> such that the solid-state image pickup element <NUM> captures the image data. For example, the control unit <NUM> supplies the solid-state image pickup element <NUM> with a vertical synchronizing signal VSYNC indicating capturing timing, through a signal line <NUM>.

The communication unit <NUM> reads the image data from the storage unit <NUM> and transmits the image data outward.

<FIG> explanatorily illustrates exemplary use of the image pickup apparatus <NUM> in the first embodiment of the present technology. As exemplified in the figure, the image pickup apparatus <NUM> is used in, for example, a factory provided with a conveyor belt <NUM>.

The conveyor belt <NUM> moves a subject <NUM> at a constant speed in a predetermined direction. The image pickup apparatus <NUM> secured near the conveyor belt <NUM>, captures the subject <NUM> to generate image data. The image data is used in inspection of, for example, the presence or absence of defects or the like. Therefore, FA is achieved.

Note that the image pickup apparatus <NUM> captures the subject <NUM> moving at the constant speed, but the configuration is not limited thereto. Like aerial capturing, the image pickup apparatus <NUM> may capture a subject while moving to the subject at a constant speed.

<FIG> illustrates an exemplary layered structure of the solid-state image pickup element <NUM> in the first embodiment of the present technology. The solid-state image pickup element <NUM> includes a circuit chip <NUM> and a light-receiving chip <NUM> layered on the circuit chip <NUM>. The chips are electrically connected through a connection, such as a via. Note that, instead of the via, a Cu-Cu junction or a bump enables electrical connection of the chips.

<FIG> is a block diagram of an exemplary configuration of the light-receiving chip <NUM> in the first embodiment of the present technology. The light-receiving chip <NUM> is provided with a pixel array unit <NUM> and a peripheral circuit <NUM>.

The pixel array unit <NUM> includes a plurality of pixel circuits <NUM> arranged in a two-dimensional grid pattern. Furthermore, the pixel array unit <NUM> is divided into a plurality of pixel blocks <NUM>. The pixel blocks <NUM> each include, for example, pixel circuits <NUM> arranged in a matrix of <NUM> rows by <NUM> columns.

For example, a circuit that supplies direct current (DC) voltage and the like are disposed in the peripheral circuit <NUM>.

<FIG> is a block diagram of an exemplary configuration of the circuit chip <NUM> in the first embodiment of the present technology. A digital-to-analog converter (DAC) <NUM>, a pixel driving circuit <NUM>, a time-code generation unit <NUM>, a pixel AD conversion unit <NUM>, and a vertical scanning circuit <NUM> are disposed on the circuit chip <NUM>. A control circuit <NUM>, a signal processing circuit <NUM>, an image processing circuit <NUM>, and an output circuit <NUM> are further disposed on the circuit chip <NUM>.

The DAC <NUM> generates a reference signal with digital-to-analog (DA) conversion during a predetermined AD conversion period. For example, a sawtooth ramp signal is used as the reference signal. The DAC <NUM> supplies the reference signal to the pixel AD conversion unit <NUM>.

The time-code generation unit <NUM> generates a time code indicating time in the AD conversion period. The time-code generation unit <NUM> is achieved by, for example, a counter. For example, a gray code counter is used as the counter. The time-code generation unit <NUM> supplies the time code to the pixel AD conversion unit <NUM>.

The pixel driving circuit <NUM> drives each pixel circuit <NUM> such that each pixel circuit <NUM> generates an analog pixel signal.

The pixel AD conversion unit <NUM> performs AD conversion in which the analog signal of each pixel circuit <NUM> (namely, the pixel signal) is converted into a digital signal. The pixel AD conversion unit <NUM> is divided into a plurality of clusters <NUM>. The clusters <NUM> are provided one-to-one to the pixel blocks <NUM>. The clusters <NUM> each convert the analog signals in the corresponding pixel block <NUM>, into digital signals.

The pixel AD conversion unit <NUM> generates image data in which the digital signals are arranged, as a frame with the AD conversion, and supplies the image data to the signal processing circuit <NUM>. Hereinafter, each group of digital signals arranged in the horizontal direction in the frame is referred to as a "line". A row address indicating the location of the line in the vertical direction is allocated to each line.

The vertical scanning circuit <NUM> drives the pixel AD conversion unit <NUM> such that the pixel AD conversion unit <NUM> performs the AD conversion.

The signal processing circuit <NUM> performs predetermined signal processing to the frame. As the signal processing, various types of processing including CDS processing and TDI processing are performed. The signal processing circuit <NUM> supplies the image processing circuit <NUM> with the frame after the processing.

The image processing circuit <NUM> performs predetermined image processing to the frame from the signal processing circuit <NUM>. As the image processing, image recognition processing, black-level correction processing, image correction processing, demosaic processing, or the like is performed. The image processing circuit <NUM> supplies the output circuit <NUM> with the frame after the processing.

The output circuit <NUM> outputs the frame after the image processing, outward.

The control circuit <NUM> controls the respective operation timings of the DAC <NUM>, the pixel driving circuit <NUM>, the vertical scanning circuit <NUM>, the signal processing circuit <NUM>, the image processing circuit <NUM>, and the output circuit <NUM>, in synchronization with the vertical synchronizing signal VSYNC.

<FIG> illustrates an exemplary configuration of the pixel AD conversion unit <NUM> in the first embodiment of the present technology. The pixel AD conversion unit <NUM> includes a plurality of ADCs <NUM> arranged in a two-dimensional grid pattern. The ADCs <NUM> are disposed one-to-one to the pixel circuits <NUM>. In a case where the number of rows and the number of columns of pixel circuits <NUM> are N (N is an integer) and M (M is an integer), respectively, N × M pieces of ACDs <NUM> are disposed.

The ADCs <NUM> identical in number to the pixel circuits <NUM> in the pixel block <NUM> are disposed in each cluster <NUM>. In a case where pixel circuits <NUM> are arranged in a matrix of <NUM> rows by <NUM> columns in each pixel block <NUM>, ADCs <NUM> are arranged in a matrix of <NUM> rows by <NUM> columns in each cluster <NUM>.

The ADCs <NUM> each perform the AD conversion to the analog pixel signal generated by the corresponding pixel circuit <NUM>. In the AD conversion, each ADC <NUM> compares the pixel signal and the reference signal, and retains the time code when a result of the comparison is inverted. Then, each ADC <NUM> outputs the retained time code as the digital signal after the AD conversion.

Furthermore, a repeater unit <NUM> is disposed every column of clusters <NUM>. In a case where the number of columns of clusters <NUM> is M/<NUM>, M/<NUM> pieces of repeater units <NUM> are disposed. The repeater units <NUM> each transfer the time code. The repeater units <NUM> each transfer the time code from the time-code generation unit <NUM> to the ADCs <NUM>. Furthermore, the repeater units <NUM> each transfer the digital signal from each ADC <NUM> to the signal processing circuit <NUM>. The transfer of the digital signal is also called the "reading" of the digital signal.

Furthermore, in the figure, the number in each pair of parentheses indicates an exemplary order of reading of the digital signal of the ADC <NUM>. For example, the digital signals at the odd columns in the first row are read first, and the digital signals at the even columns in the first row are read second. The digital signals at the odd columns in the second row are read third, and the digital signals at the even columns in the second row are read fourth. After that, similarly, the digital signals at the odd columns and the digital signals at the even columns in each row are read sequentially.

Note that the ADCs <NUM> are disposed one-to-one to the pixel circuits <NUM>, but the configuration is not limited thereto. A plurality of pixel circuits <NUM> may share one ADC <NUM>.

<FIG> is a block diagram of an exemplary configuration of the ADC <NUM> in the first embodiment of the present technology. The ADC <NUM> includes a differential input circuit <NUM>, a positive feedback circuit <NUM>, a latch control circuit <NUM>, and a plurality of latch circuits <NUM>.

Furthermore, the pixel circuit <NUM> and part of the differential input circuit <NUM> are disposed on the light-receiving chip <NUM>. The remaining part of the differential input circuit <NUM> and the circuits at the post-stage thereof are disposed on the circuit chip <NUM>.

The differential input circuit <NUM> compares the pixel signal from the pixel circuit <NUM> and the reference signal from the DAC <NUM>. The differential input circuit <NUM> supplies the positive feedback circuit <NUM> with a comparative-result signal indicating a result of the comparison.

The positive feedback circuit <NUM> adds a partial output to the input (comparative-result signal) and supplies the latch control circuit <NUM> with the input having the partial output added thereto as an output signal VCO.

In accordance with a control signal xWORD from the vertical scanning circuit <NUM>, the latch control circuit <NUM> causes the plurality of latch circuits <NUM> to retain the time code at the time when the output signal VCO is inverted.

In accordance with the control of the latch control circuit <NUM>, the latch circuits <NUM> retain the time code from the repeater unit <NUM>. The latch circuits <NUM> are provided for the bit length of the time code. For example, in a case where the time code is <NUM> bits, <NUM> pieces of latch circuits <NUM> are disposed in the ADC <NUM>. Furthermore, the retained time code is read as the digital signal after the AD conversion by the repeater unit <NUM>.

The configuration exemplified in the figure allows the ADC <NUM> to convert the pixel signal from the pixel circuit <NUM>, into the digital signal.

<FIG> is a circuit diagram of exemplary configurations of the pixel circuit <NUM>, the differential input circuit <NUM>, and the positive feedback circuit <NUM> in the first embodiment of the present technology.

The pixel circuit <NUM> includes a reset transistor <NUM>, a floating diffusion layer <NUM>, a transfer transistor <NUM>, a photodiode <NUM>, and a discharge transistor <NUM>. As the reset transistor <NUM>, the transfer transistor <NUM>, and the discharge transistor <NUM>, for example, an n-channel metal oxide semiconductor (nMOS) transistor is used.

The photodiode <NUM> photoelectrically generates electric charge. The discharge transistor <NUM> discharges the electric charge accumulated in the photodiode <NUM>, in accordance with a driving signal OFG from the pixel driving circuit <NUM>.

The transfer transistor <NUM> transfers the electric charge from the photodiode <NUM> to the floating diffusion layer <NUM>, in accordance with a transfer signal TX from the pixel driving circuit <NUM>.

The floating diffusion layer <NUM> accumulates the transferred electric charge, and generates voltage corresponding to the amount of electric charge.

The reset transistor <NUM> initializes the floating diffusion layer <NUM>, in accordance with a reset signal RST from the pixel driving circuit <NUM>.

The differential input circuit <NUM> includes p-channel metal oxide semiconductor (pMOS) transistors <NUM>, <NUM>, and <NUM> and nMOS transistors <NUM>, <NUM>, <NUM>, and <NUM>. Among the above transistors, the nMOS transistors <NUM>, <NUM>, and <NUM> are disposed on the light-receiving chip <NUM>, and the remaining transistors are disposed on the circuit chip <NUM>.

The nMOS transistors <NUM> and <NUM> form a differential pair, and the respective sources of the transistors are connected in common with the drain of the nMOS transistor <NUM>. Furthermore, the drain of the nMOS transistor <NUM> is connected with the drain of the pMOS transistor <NUM> and the respective gates of the pMOS transistors <NUM> and <NUM>. The drain of the nMOS transistor <NUM> is connected with the drain of the pMOS transistor <NUM>, the gate of the pMOS transistor <NUM>, and the drain of the reset transistor <NUM>. Furthermore, the reference signal REF from the DAC <NUM> is input into the gate of the nMOS transistor <NUM>.

Predetermined bias voltage Vb is applied to the gate of the nMOS transistor <NUM>, and predetermined ground voltage is applied to the source of the nMOS transistor <NUM>.

The pMOS transistors <NUM>, <NUM>, and <NUM> form a current mirror circuit. Power source voltage VDDH is applied to the respective sources of the pMOS transistors <NUM>, <NUM>, and <NUM>. The power source voltage VDDH is higher than power source voltage VDDL to be described below.

The power source voltage VDDL is applied to the gate of the nMOS transistor <NUM>. Furthermore, the drain of the nMOS transistor <NUM> is connected with the drain of the pMOS transistor <NUM>, and the source of the nMOS transistor <NUM> is connected with the positive feedback circuit <NUM>.

The positive feedback circuit <NUM> includes pMOS transistors <NUM>, <NUM>, <NUM>, and <NUM> and nMOS transistors <NUM>, <NUM>, and <NUM>. The pMOS transistors <NUM> and <NUM> and the nMOS transistor <NUM> are connected in series to the power source voltage VDDL. Furthermore, a driving signal INI2 from the vertical scanning circuit <NUM> is input into the gate of the pMOS transistor <NUM>. The node between the pMOS transistor <NUM> and the nMOS transistor <NUM> is connected with the source of the nMOS transistor <NUM>.

The ground voltage is applied to the source of the nMOS transistor <NUM>, and a driving signal INI1 from the vertical scanning circuit <NUM> is input into the gate of the nMOS transistor <NUM>.

The pMOS transistors <NUM> and <NUM> are connected in series to the power source voltage VDDL. Furthermore, the drain of the pMOS transistor <NUM> is connected with the gate of the pMOS transistor <NUM> and the respective drains of the nMOS transistors <NUM> and <NUM>. A control signal TESTVCO from the vertical scanning circuit <NUM> is input into the respective gates of the pMOS transistor <NUM> and the nMOS transistor <NUM>. Furthermore, the respective gates of the pMOS transistor <NUM> and the nMOS transistor <NUM> are connected with the node between the pMOS transistor <NUM> and the nMOS transistor <NUM>.

The output signal VCO is output from the node between the pMOS transistor <NUM> and the nMOS transistor <NUM>. Furthermore, the ground voltage is applied to the respective sources of the nMOS transistors <NUM> and <NUM>.

Note that, as long as having the respective functions described in <FIG>, the pixel circuit <NUM>, the differential input circuit <NUM>, and the positive feedback circuit <NUM> are not limited to the respective circuits exemplified in <FIG>.

<FIG> is a block diagram of an exemplary configuration of the signal processing circuit <NUM> in the first embodiment of the present technology. The signal processing circuit <NUM> includes a plurality of selectors <NUM>, a plurality of arithmetic circuits <NUM>, a CDS frame memory <NUM>, and a TDI frame memory <NUM>.

The selectors <NUM> are disposed one-to-one to the columns of clusters <NUM>, namely, one-to-one to the repeater units <NUM>. In a case where two columns of ADCs <NUM> are arranged in each cluster <NUM>, a selector <NUM> is disposed every two columns. Furthermore, the arithmetic circuits <NUM> are disposed one-to-one to the columns of ADCs <NUM>. In a case where M columns of ADCs <NUM> are provided, M/<NUM> pieces of selectors <NUM> and M pieces of arithmetic circuits <NUM> are disposed.

As described above, each repeater unit <NUM> sequentially outputs the digital signals in the odd column and the digital signals in the even column.

The selector <NUM> selects an output destination for each digital signal, in accordance with the control of the control circuit <NUM>. In a case where each repeater unit <NUM> outputs a digital signal in the odd column, the selector <NUM> outputs the digital signal to the arithmetic circuit <NUM> corresponding to the odd column. Meanwhile, in a case where each repeater unit <NUM> outputs a digital signal in the even column, the selector <NUM> outputs the digital signal to the arithmetic circuit <NUM> corresponding to the even column.

Each arithmetic circuit <NUM> performs the CDS processing and the TDI processing to the digital signal from the selector <NUM>.

Here, the digital signal includes a P-phase level and a D-phase level. The P-phase level indicates the level at the time when the pixel circuit <NUM> is initialized due to the reset signal RST. Meanwhile, the D-phase level indicates the level corresponding to the amount of exposure at the time when the electric charge is transferred due to the transfer signal TX. The P-phase level is also called a reset level, and the D-phase level is also a signal level.

In the CDS processing, the M pieces of arithmetic circuits <NUM> retain a P-phase frame in which P-phase levels are arranged, into the CDS frame memory <NUM>. Then, the M pieces of arithmetic circuits <NUM> acquire the difference between the P-phase level and the D-phase level every pixel, resulting in generation of a CDS frame in which difference data is arranged.

Then, in the TDI processing, the M pieces of arithmetic circuits <NUM> retain the first CDS frame into the TDI frame memory <NUM>. Next, the M pieces of arithmetic circuits <NUM> add the line having a predetermined address in the CDS frame of the second frame after the CDS processing and the line having the address at a certain distance from the predetermined address in the frame of the first frame. As the speed of movement of the subject increases, the value to be set to the distance between the addresses for addition, increases. For example, "<NUM>" is set to the distance between the addresses for addition. In this case, adjacent lines are added together. For the second and subsequent frames, to the K-th CDS frame (K is an integer), the (K - <NUM>)-th CDS frame generated before the frame is retained in the TDI frame memory <NUM>.

Furthermore, the M pieces of arithmetic circuits <NUM> supply the image processing circuit <NUM> with the CDS frame and a TDI frame after the TDI processing.

<FIG> is a circuit diagram of an exemplary configuration of the arithmetic circuit <NUM> in the first embodiment of the present technology. The arithmetic circuit <NUM> includes a TDI circuit <NUM> and a CDS circuit <NUM>. The TDI circuit <NUM> includes a buffer <NUM>, a selector <NUM>, an adder <NUM>, and a switch <NUM>. The CDS circuit <NUM> includes a selector <NUM>, a buffer <NUM>, a selector <NUM>, a subtractor <NUM>, and a switch <NUM>. For example, the respective operations of the selectors <NUM>, <NUM>, and <NUM> and the switches <NUM> and <NUM> are controlled by the control circuit <NUM>.

The selector <NUM> selectively outputs either the digital signal from the selector <NUM> or the digital signal from the TDI frame memory <NUM>, to the buffer <NUM>.

The buffer <NUM> delay-outputs the signal from the selector <NUM>. Note that the buffer <NUM> is an exemplary second buffer in the claims.

The selector <NUM> selectively outputs either the digital signal from the buffer <NUM> or a digital signal with the value "<NUM>" in decimal number, to the adder <NUM>.

The adder <NUM> adds the digital signal from the selector <NUM> and the digital signal from the buffer <NUM>. The adder <NUM> supplies the switch <NUM> with a digital signal indicating the addition in value as summation data.

The switch <NUM> opens and closes the path between the adder <NUM> and the TDI frame memory <NUM>.

The buffer <NUM> delay-outputs the signal from the CDS frame memory <NUM>. Note that the buffer <NUM> is an exemplary first buffer in the claims.

The selector <NUM> selectively outputs either the digital signal from the buffer <NUM> or a digital signal with the value "<NUM>" in decimal number, to the subtractor <NUM>.

The subtractor <NUM> computes the difference between the digital signal from the buffer <NUM> and the digital signal from the selector <NUM>. The subtractor <NUM> supplies the switch <NUM> with a digital signal indicating the difference as difference data.

The switch <NUM> opens and closes the path between the subtractor <NUM> and the CDS frame memory <NUM>.

Next, a method of controlling the circuits in the arithmetic circuit <NUM> will be described.

<FIG> illustrates an exemplary state of the arithmetic circuit <NUM> at the time of retention of the P-phase level of the first frame in the first embodiment of the present technology.

The control circuit <NUM> initializes the CDS frame memory <NUM> and the TDI frame memory <NUM>. After the initialization, the pixel AD conversion unit <NUM> generates the P-phase level of the first frame.

The plurality of P-phase levels in the corresponding column of the first frame is sequentially input into the selector <NUM>. The selector <NUM> selectively outputs the P-phase levels to the buffer <NUM>. The selector <NUM> outputs the digital signal "<NUM>" to the subtractor <NUM>. The subtractor <NUM> subtracts "<NUM>" from the P-phase level, and outputs a result of the subtraction to the switch <NUM>. Furthermore, the switch <NUM> is controlled in the open state, and the switch <NUM> is controlled in the closed state.

Due to the control, the M pieces of arithmetic circuits <NUM> retain the P-phase frame of the first frame in which the P-phase levels are arranged, into the CDS frame memory <NUM>.

<FIG> illustrates an exemplary state of the arithmetic circuit at the time of performance of the CDS processing to the first frame in the first embodiment of the present technology.

The pixel AD conversion unit <NUM> generates the D-phase level of the first frame. The plurality of D-phase levels in the corresponding column of the first frame is sequentially input into the selector <NUM>. The selector <NUM> selectively outputs the D-phase levels to the buffer <NUM>.

Furthermore, the buffer <NUM> sequentially reads the plurality of P-phase levels in the corresponding column from the CDS frame memory <NUM>, for output to the selector <NUM>. The selector <NUM> selectively outputs the P-phase levels to the subtractor <NUM>.

The subtractor <NUM> subtracts the P-phase level selected by the selector <NUM> from the D-phase level output from the buffer <NUM>, and outputs a result of the subtraction as the difference data to the switch <NUM>. Furthermore, the switch <NUM> is controlled in the open state, and the switch <NUM> is controlled in the closed state.

Due to the control, the M pieces of arithmetic circuits <NUM> perform the CDS processing to the first frame, and retain the CDS frame in which the difference data is arranged, in the CDS frame memory <NUM>. Furthermore, the CDS frame is supplied also to the image processing circuit <NUM>.

<FIG> illustrates an exemplary state of the arithmetic circuit at the time of retention of a frame in the first embodiment of the present technology.

The pixel AD conversion unit <NUM> generates the P-phase level of the second frame. The plurality of P-phase levels in the corresponding column of the second frame is sequentially input into the selector <NUM>. The selector <NUM> selectively outputs the P-phase levels to the buffer <NUM>. The buffer <NUM> delays the P-phase levels.

The buffer <NUM> sequentially reads the plurality of pieces of difference data in the corresponding column from the CDS frame memory <NUM>, for output to the adder <NUM>. The selector <NUM> selectively outputs the digital signal "<NUM>" to the adder <NUM>. The adder <NUM> adds "<NUM>" to the difference data, and outputs a result of the addition to the switch <NUM>. Furthermore, the switch <NUM> is controlled in the closed state, and the switch <NUM> is controlled in the open state.

Due to the control, the M pieces of arithmetic circuits <NUM> retain the current CDS frame in which the different data is arranged, into the TDI frame memory <NUM>.

<FIG> illustrates an exemplary state of the arithmetic circuit <NUM> at the time of retention of the P-phase level of the second frame in the first embodiment of the present technology.

The buffer <NUM> outputs the P-phase level to the subtractor <NUM>. The selector <NUM> outputs the digital signal "<NUM>" to the subtractor <NUM>. The subtractor <NUM> subtracts "<NUM>" from the P-phase level, and outputs a result of the subtraction to the switch <NUM>. Furthermore, the switch <NUM> is controlled in the open state, and the switch <NUM> is controlled in the closed state.

Due to the control, the M pieces of arithmetic circuits <NUM> retain the P-phase frame of the second frame in which the P-phase levels are arranged, in the CDS frame memory <NUM>.

<FIG> illustrates an exemplary state of the arithmetic circuit at the time of performance of the CDS processing to the second frame in the first embodiment of the present technology.

The pixel AD conversion unit <NUM> generates the D-phase level of the second frame. The plurality of D-phase levels in the corresponding column of the second frame is sequentially input into the selector <NUM>. The selector <NUM> selectively outputs the D-phase levels to the buffer <NUM>.

The subtractor <NUM> subtracts the P-phase level from the D-phase level, and outputs a result of the subtraction as the difference data to the switch <NUM>. Furthermore, the switch <NUM> is controlled in the open state, and the switch <NUM> is controlled in the closed state.

Due to the control, the M pieces of arithmetic circuits <NUM> perform the CDS processing to the second frame, and retain the CDS frame in which the difference data is arranged, in the CDS frame memory <NUM>. Furthermore, the CDS frame is supplied also to the image processing circuit <NUM>.

<FIG> illustrates an exemplary state of the arithmetic circuit at the time of performance of the TDI processing to the second frame in the first embodiment of the present technology.

The selector <NUM> sequentially reads and selects the difference data in the corresponding column from the TDI frame memory <NUM>, for output to the buffer <NUM>. Furthermore, the buffer <NUM> reads the difference data in the corresponding column from the CDS frame memory <NUM>, for output to the adder <NUM>. With the row address of the difference data read from the TDI frame memory <NUM> defined as the predetermined address, the row address of the difference data read from the CDS frame memory <NUM> is at the certain distance from the predetermined address. For example, the row address of the difference data read from the CDS frame memory <NUM> is adjacent to the predetermined address.

The selector <NUM> selectively outputs the difference data from the buffer <NUM> to the adder <NUM>. The adder <NUM> adds the difference data in the first frame and the difference data in the second frame, for output to the switch <NUM>. Furthermore, the switch <NUM> is controlled in the closed state, and the switch <NUM> is controlled in the open state.

Due to the control, the M pieces of arithmetic circuits <NUM> add the line having the predetermined address of the current second frame and the line having the adjacent address of the past first frame. The processing to the second frame is repeatedly performed to the third and subsequent frames.

<FIG> illustrates exemplary TDI processing in the first embodiment of the present technology. For example, after initialization of the CDS frame memory <NUM> and the TDI frame memory <NUM>, frame F1 is captured first. Then, frames F2, F3, F4, and F5 are captured sequentially. An arrow in the figure indicates the direction of movement of a subject. As exemplified in the figure, the subject moves every line in the direction of increase of the row address in the vertical direction.

The signal processing circuit <NUM> performs the CDS processing to frame F1 first, retains frame F1 after the processing in the CDS frame memory <NUM>, and retains frame F1 in the TDI frame memory <NUM>.

Then, the signal processing circuit <NUM> performs the CDS processing to frame F2, and adds line L2 in the current frame F2 and line L1 adjacent to line L2 in the past frame F1.

Next, the signal processing circuit <NUM> performs the CDS processing to frame F3, and adds line L3 in the current frame F3 and line L2 adjacent to line L3 in the past frame F2.

Subsequently, the signal processing circuit <NUM> performs the CDS processing to frame F4, and adds line L4 in the current frame F4 and line L3 adjacent to line L4 in the past frame F3.

Due to the computation, line L1 in frame F1, line L2 in frame F2, line L3 in frame F3, and line L4 in frame F4 are summed. As described above, because the subject moves every line, each line to be summed is identical in pattern. The signal processing circuit <NUM> outputs the summed lines as the last line of the TDI frame. As above, the processing of integrating the amount of exposure with shifting in time is called the TDI processing.

The second line from the last in the TDI frame is generated by summation of line L1 in frame F2, line L2 in frame F3, line L3 in frame F4, and line L4 in frame F5. Similarly, the remaining lines each are generated by summation of four lines from frame F3 and the subsequent frames.

In a case where the speed of movement of the subject is fast, the exposure time needs shortening in order to prevent blurring. Shortening of the exposure time is likely to cause an image to be dark. However, performance of the TDI processing enables improvement in brightness with summation of a plurality of lines in the same pattern. Furthermore, as the number of lines to be summed increases, noise reduces due to the effect of smoothing. The improvement in brightness and the noise reduction enable improvement of the image quality of a frame (namely, image data) in comparison to a case where no TDI processing is performed.

Note that, although the signal processing circuit <NUM> sums four lines, the number of lines to be summed is not limited to four as long as being two or more. Furthermore, for the first four frames, the signal processing circuit <NUM> makes an integration of the first four lines from the top, but the configuration is not limited thereto. For example, in a case where the direction of movement of the subject is reversed, for the first four frames, the signal processing circuit <NUM> needs at least to make an integration of the first four lines from the last.

<FIG> is a timing chart of an exemplary operation of the solid-state image pickup element <NUM> in the first embodiment of the present technology. The pixel AD conversion unit <NUM> generates frame F1 in the period from timing T1 to timing T2, and generates frame F2 in the period from timing T2 to timing T3. Furthermore, the pixel AD conversion unit <NUM> generates frame F3 in the period from timing T3 to timing T4, and generates frame F4 from timing T4.

Furthermore, in the period from timing T1 to timing T2, each ADC <NUM> sequentially generates the P-phase level and the D-phase level of the first frame. Meanwhile, each arithmetic circuit <NUM> performs the CDS processing at the time of D-phase generation.

Furthermore, in the period from timing T2 to timing T3, each ADC <NUM> sequentially generates the P-phase level and the D-phase level of the second frame. Meanwhile, each arithmetic circuit <NUM> performs the TDI processing at the time of P-phase generation and performs the CDS processing at the time of D-phase generation.

For the third and subsequent frames, similarly, the P-phase level and the D-phase level are generated, and the TDI processing and the CDS processing are performed.

<FIG> explanatorily illustrates the computation of the signal processing circuit <NUM> in the first embodiment of the present technology.

The plurality of pixel circuits <NUM> each photoelectrically generates an analog pixel signal and supplies the pixel AD conversion unit <NUM> with the analog pixel signal. The pixel AD conversion unit <NUM> includes the plurality of ADCs <NUM> arranged in the two-dimensional grid pattern. The ADCs <NUM> each convert the analog pixel signal into a digital signal and transfers the digital signal to the arithmetic circuit <NUM> through the repeater unit <NUM>. The digital signal includes the reset level and the signal level corresponding to the amount of exposure. The ADCs <NUM> each output the signal level after the reset level. Note that the pixel AD conversion unit <NUM> is an exemplary analog-to-digital conversion unit in the claims.

The CDS circuit <NUM> retains the first P-phase frame in which the P-phase levels are arranged, in the CDS frame memory <NUM>. When the D-phase level is input, the CDS circuit <NUM> reads the P-phase frame from the CDS frame memory <NUM>, and performs the CDS processing of acquiring the difference between the P-phase level and the D-phase level. Then, the CDS circuit <NUM> updates the CDS frame memory <NUM> with the first CDS frame after the CDS processing, and retains the CDS frame in the TDI frame memory <NUM>.

Then, the CDS circuit <NUM> retains the P-phase frame of the second frame in the CDS frame memory <NUM>. When the D-phase level is input, the CDS circuit <NUM> reads the P-phase frame from the CDS frame memory <NUM>, and performs the second CDS processing of acquiring the difference between the P-phase level and the D-phase level. Then, the CDS circuit <NUM> updates the CDS frame memory <NUM> with the CDS frame of the second frame after the CDS processing.

Subsequently, the TDI circuit <NUM> reads the line having the predetermined address in the (K - <NUM>)-th CDS frame from the TDI frame memory <NUM>, and reads the line having the address at the certain distance from the predetermined address in the K-th frame (e.g., adjacent address) from the CDS frame memory <NUM>. Then, the TDI circuit <NUM> adds the lines, and updates the TDI frame memory <NUM> with the added lines.

For the third and subsequent frames, processing similar to that of the second frame is repeatedly performed. Note that, for the third and subsequent frames, the number of lines to be summed increases one by one. The number of times of summation increases to a certain number of times (e.g., four times). Due to the processing, the TDI frame in which the summation data is arranged, is generated.

Here, as a comparative example, considered is a solid-state image pickup element including a charge coupled device (CCD) that transfers electric charge with shifting in time and a circuit that accumulates the amount of electric charge thereof in a floating diffusion layer to generate an integral signal. According to the comparative example, as the number of pixels increases at the source from which electric charge is transferred, the capacity of the floating diffusion layer needs increasing at the destination to which electric charge is transferred. The increase of the capacity causes deterioration in pixel sensitivity, and then the image quality of image data deteriorates due to the deterioration in pixel sensitivity. As above, the comparative example has a problem with deterioration in image quality.

In contrast to this, according to the configuration in which the TDI processing is performed after the CDS processing outside the pixel circuit <NUM>, the capacity of the floating diffusion layer in the pixel circuit <NUM> does not need increasing in accordance with the number of times of addition. Thus, the capacity of the floating diffusion layer can made smaller than that in the comparative example. Therefore, the pixel sensitivity can be made higher than that in the comparative example, resulting in improvement in the image quality of image data.

Next, a method of controlling the circuits in the solid-state image pickup element <NUM>, will be described.

<FIG> illustrates an exemplary state of the solid-state image pickup element <NUM> at the time of retention of the P-phase level in the first embodiment of the present technology. In the figure, no selector <NUM> is illustrated for convenience in description.

Every time the pixel AD conversion unit <NUM> outputs the P-phase levels in each line, the plurality of arithmetic circuits <NUM> retain the P-phase levels in the CDS frame memory <NUM>. Therefore, the P-phase frame in which the plurality of P-phase levels is arranged, is retained in the CDS frame memory <NUM>.

<FIG> illustrates an exemplary state of the solid-state image pickup element <NUM> at the time of performance of the CDS processing in the first embodiment of the present technology. In the figure, no selector <NUM> is illustrated.

Every time the pixel AD conversion unit <NUM> outputs the D-phase levels in each line, the plurality of arithmetic circuits <NUM> acquires the difference between the D-phase levels and the corresponding P-phase levels in the CDS frame memory <NUM>. Then, the arithmetic circuits <NUM> update the CDS frame memory <NUM> with the CDS frame in which the difference data is arranged.

<FIG> illustrates an exemplary state of the solid-state image pickup element <NUM> at the time of performance of image processing after the CDS processing in the first embodiment of the present technology. In the figure, no selector <NUM> is illustrated. The image processing circuit <NUM> performs the predetermined image processing to the frame after the CDS processing.

<FIG> illustrates an exemplary state of the solid-state image pickup element at the time of performance of the TDI processing in the first embodiment of the present technology. In the figure, no selector <NUM> is illustrated.

The plurality of arithmetic circuits <NUM> adds the line having the predetermined address in the CDS frame memory <NUM> and the line adjacent to the predetermined address in the TDI frame memory <NUM>. Then, the arithmetic circuits <NUM> update the TDI frame memory <NUM> with the summation data indicating the addition in value.

<FIG> illustrates an exemplary state of the solid-state image pickup element <NUM> at the time of performance of image processing after the TDI processing in the first embodiment of the present technology. In the figure, no selector <NUM> is illustrated. The image processing circuit <NUM> performs image processing, such as black-level correction processing, to the frame after the TDS processing.

<FIG> illustrates an exemplary state of the solid-state image pickup element at the time of output of the frame in the first embodiment of the present technology. In the figure, no selector <NUM> is illustrated. The output circuit <NUM> outputs a result of the image processing to, for example, the storage unit <NUM>.

<FIG> is a flowchart of an exemplary operation of the solid-state image pickup element in the first embodiment of the present technology. For example, the operation starts when a predetermined application for frame capturing is executed.

The pixel driving circuit <NUM> in the solid-state image pickup element <NUM> drives all the pixels such that simultaneous exposure of all the pixels is started (step S901). The control of simultaneous exposure of all the pixels as above is called a global shutter technique.

Just before completion of the exposure, the ADCs <NUM> each perform the AD conversion to the P-phase level (step S902). Then, at the time of completion of the exposure, the ADCs <NUM> each perform the AD conversion to the D-phase level, and the arithmetic circuits <NUM> each perform the CDS processing (step S903).

The image processing circuit <NUM> performs the predetermined image processing to the frame after the CDS processing (step S904), and the arithmetic circuits <NUM> each perform the TDI processing (step S905). The image processing circuit <NUM> performs the predetermined image processing to the frame after the TDI processing (step S906), and the output circuit <NUM> outputs a result of the processing (step S907). After step S907, the solid-state image pickup element <NUM> completes the processing of capturing one frame. At the time of consecutive capturing of two frames or more, the processing at steps S901 to S907 is repeatedly performed in synchronization with the vertical synchronizing signal VSYNC.

As above, in the first embodiment of the present technology, the arithmetic circuits <NUM> add the predetermined line in the K-th frame after the CDS processing and the adjacent line in the (K - <NUM>)-th frame. Thus, the capacity of the floating diffusion layer in each pixel circuit <NUM> does not need increasing in accordance with the number of times of addition. Therefore, improvement can be made in pixel sensitivity with a small capacity of floating diffusion layer, in comparison to a case where the amount of electric charge of a plurality of pixels is transferred to a floating diffusion layer. The improvement in pixel sensitivity enables improvement in the image quality of image data.

In the first embodiment, both of the TDI circuit <NUM> and the CDS circuit <NUM> are disposed between the pixel AD conversion unit <NUM> and the CDS frame memory <NUM>. However, either of the circuits (e.g., TDI circuit <NUM>) is not necessarily disposed between the pixel AD conversion unit <NUM> and the CDS frame memory <NUM>. A solid-state image pickup element <NUM> in a second embodiment is different from that in the first embodiment in that a TDI circuit <NUM> is changed in disposition.

<FIG> is a block diagram of an exemplary configuration of a circuit chip <NUM> in the second embodiment of the present technology. Instead of a plurality of arithmetic circuits <NUM>, a column CDS processing unit <NUM> and a column TDI arithmetic unit <NUM> are disposed on the circuit chip <NUM> in the second embodiment.

The column CDS processing unit <NUM> is disposed between a pixel AD conversion unit <NUM> and a CDS frame memory <NUM>, and the column TDI arithmetic unit <NUM> is disposed between the CDS frame memory <NUM> and a TDI frame memory <NUM>. Note that, in the figure, no selector <NUM> is illustrated for convenience in description.

<FIG> is a block diagram of exemplary configurations of the column CDS processing unit <NUM> and the column TDI arithmetic unit <NUM> in the second embodiment of the present technology. As exemplified in the figure, a plurality of CDS circuits <NUM> is arranged in the column CDS processing unit <NUM>. For example, the CDS circuits <NUM> each are disposed every column of ADCs <NUM>.

Furthermore, a plurality of TDI circuits <NUM> is arranged in the column TDI arithmetic unit <NUM>. For example, the TDI circuits <NUM> each are disposed every column of ADCs <NUM>.

As exemplified in the figure, because the CDS circuits <NUM> and the TDI circuits <NUM> are disposed differently in position, the degree of freedom of the circuit chip <NUM> in layout design can be improved.

<FIG> is a timing chart of an exemplary operation of the solid-state image pickup element <NUM> in the second embodiment of the present technology. The pixel AD conversion unit <NUM> sequentially generates frame F1 in the period from timing T1 to timing T2, frame F2 in the period from timing T2 to timing T3, frame F3 in the period from timing T3 to timing T4, and frame F4 from timing T4.

Furthermore, in the period from timing T1 to timing T2, each ADC <NUM> sequentially generates the P-phase level and the D-phase level. Meanwhile, the column CDS processing unit <NUM> performs CDS processing at the time of D-phase generation.

Furthermore, in the period from timing T2 to timing T3, each ADC <NUM> sequentially generates the P-phase level and the D-phase level of the second frame. Meanwhile, the column TDI arithmetic unit <NUM> performs TDI processing at the time of P-phase generation. The column CDS processing unit <NUM> performs the CDS processing at the time of D-phase generation.

As above, in the second embodiment of the present technology, because the TDI circuits <NUM> and the CDS circuits <NUM> are disposed differently in position, the degree of freedom in layout design can be improved.

In the second embodiment, no buffer is inserted between a selector <NUM> and a selector <NUM>. The timing of output of a digital signal varies between an odd column and an even column. Thus, desirably, a buffer is inserted for timing adjustment. A solid-state image pickup element <NUM> in a third embodiment is different from that in the second embodiment in that a buffer is added to a CDS circuit <NUM>.

<FIG> is a circuit diagram of exemplary configurations of a CDS circuit <NUM> and a TDI circuit <NUM> in the third embodiment of the present technology. The CDS circuit <NUM> in the third embodiment is different from that in the second embodiment in that a buffer <NUM> is further provided.

The buffer <NUM> is disposed between a selector <NUM> and a selector <NUM>. Note that the buffer <NUM> is an exemplary third buffer in the claims.

<FIG> is a block diagram of an exemplary configuration of a signal processing circuit <NUM> in the third embodiment of the present technology. As exemplified in the figure, the buffer <NUM>, a buffer <NUM>, and a processing circuit <NUM> are disposed in each CDS circuit <NUM>. The selectors <NUM> and <NUM>, a subtractor <NUM>, and a switch <NUM> in <FIG> are disposed in the processing circuit <NUM>.

Each selector <NUM> outputs digital signals in an even column and digital signals in an odd column at different timings. The buffers <NUM> added to the post-stage of each selector <NUM> enable adjustment of the start timing of CDS processing between the odd column and the even column.

As above, in the third embodiment of the present technology, the buffers <NUM> inserted between each selector <NUM> and the selectors <NUM>, enable adjustment of the start timing of CDS processing between the odd column and the even column.

In the third embodiment, the processing circuit <NUM> is disposed every column. As the number of columns increases, the circuit scale of the signal processing circuit <NUM> increases. A solid-state image pickup element <NUM> in a fourth embodiment is different from that in the third embodiment in that a processing circuit <NUM> is shared between adjacent two columns.

<FIG> is a circuit diagram of exemplary configurations of a CDS circuit <NUM> and a TDI circuit <NUM> in the fourth embodiment of the present technology. The CDS circuit <NUM> in the fourth embodiment is different from that in the third embodiment in that a buffer <NUM> and a selector <NUM> are further provided.

The buffer <NUM> reads a digital signal in an even column from a CDS frame memory <NUM> and delays the digital signal. Furthermore, a buffer <NUM> in the fourth embodiment reads a digital signal in an odd column from the CDS frame memory <NUM> and delays the digital signal.

In accordance with the control of a control circuit <NUM>, the selector <NUM> selectively outputs either an output of the buffer <NUM> or an output of the buffer <NUM>, to the TDI circuit <NUM> and a selector <NUM>.

<FIG> is a block diagram of an exemplary configuration of a signal processing circuit <NUM> in the fourth embodiment of the present technology. The CDS circuit <NUM> and the TDI circuit <NUM> are disposed every adjacent two columns in the signal processing circuit <NUM> in the fourth embodiment. Note that, in the figure, no selector <NUM> and no TDI circuit <NUM> are illustrated.

The buffers <NUM>, <NUM>, and <NUM>, the selector <NUM>, and the processing circuit <NUM> are disposed in the CDS circuit <NUM>. As exemplified in the figure, in the fourth embodiment, the processing circuit <NUM> is shared between two columns. Thus, the circuit scale of the signal processing circuit <NUM> can be reduced in comparison to the third embodiment in which the processing circuit <NUM> is provided every column.

As above, in the fourth embodiment of the present technology, the processing circuit <NUM> is shared between adjacent two columns, so that the circuit scale of the signal processing circuit <NUM> can be reduced in comparison to a case where the processing circuit <NUM> is disposed every column.

In the third embodiment, the processing circuit <NUM> is disposed every column. As the number of columns increases, the circuit scale of the signal processing circuit <NUM> increases. A solid-state image pickup element <NUM> in a fifth embodiment is different from that in the third embodiment in that a processing circuit <NUM> is shared between four columns.

<FIG> is a circuit diagram of an exemplary configuration of a CDS circuit <NUM> in the fifth embodiment of the present technology. The CDS circuit <NUM> in the fifth embodiment includes buffers <NUM> to <NUM>, a selector <NUM>, buffers <NUM> to <NUM>, a selector <NUM>, a selector <NUM>, a subtractor <NUM>, and a switch <NUM>.

The buffers <NUM> to <NUM> delay respective digital signals in adjacent four columns from selectors <NUM> and <NUM>. For example, the selector <NUM> outputs either a digital signal in the <NUM>-th column (m is an integer) or a digital signal in the (<NUM> + <NUM>)-th column, and the selector <NUM> outputs either a digital signal in the (<NUM> + <NUM>)-th column or a digital signal in the (<NUM> + <NUM>)-th column. The buffer <NUM> delays the digital signal in the <NUM>-th column, and the buffer <NUM> delays the digital signal in the (<NUM> + <NUM>)-th column. The buffer <NUM> delays the digital signal in the (<NUM> + <NUM>)-th column, and the buffer <NUM> delays the digital signal in the (<NUM> + <NUM>)-th column.

In accordance with a control circuit <NUM>, the selector <NUM> selectively outputs any one of respective outputs of the buffers <NUM> to <NUM> and a TDI frame memory <NUM>, to a TDI circuit <NUM>.

The buffers <NUM> to <NUM> delay respective digital signals in adjacent four columns in a CDS frame memory <NUM>. The buffer <NUM> delays a digital signal in the <NUM>-th column, and the buffer <NUM> delays a digital signal in the (<NUM> + <NUM>)-th column. The buffer <NUM> delays a digital signal in the (<NUM> + <NUM>)-th column, and the buffer <NUM> delays a digital signal in the (<NUM> + <NUM>)-th column.

In accordance with the control circuit <NUM>, the selector <NUM> selectively outputs any one of respective outputs of the buffers <NUM> to <NUM>, to the TDI circuit <NUM> and the selector <NUM>.

<FIG> is a block diagram of an exemplary configuration of a signal processing circuit <NUM> in the fifth embodiment of the present technology. The CDS circuit <NUM> and the TDI circuit <NUM> are disposed every four columns in the signal processing circuit <NUM> in the fifth embodiment. Note that, in the figure, no TDI circuit <NUM> is illustrated.

The buffers <NUM> to <NUM>, the buffers <NUM> to <NUM>, and the processing circuit <NUM> are disposed in the CDS circuit <NUM>. The selector <NUM>, the selector <NUM>, the selector <NUM>, the subtractor <NUM>, and the switch <NUM> in <FIG> are disposed in the processing circuit <NUM>. As exemplified in the figure, in the fifth embodiment, the processing circuit <NUM> is shared between four columns. Thus, the circuit scale of the signal processing circuit <NUM> can be reduced in comparison to the third embodiment in which the processing circuit <NUM> is provided every column.

As above, in the fifth embodiment of the present technology, the processing circuit <NUM> is shared between four columns, so that the circuit scale of the signal processing circuit <NUM> can be reduced in comparison to a case where the processing circuit <NUM> is disposed every column.

Note that the embodiments are exemplified in order to embody the present technology, and the matters in the embodiments and particular matters concerning the invention in the claims are in mutual correspondence relationship. Similarly, the particular matters concerning the invention in the claims and the matters in the embodiments of the present technology denoted with the same names as the particular matters, are in mutual correspondence relationship. Note that the present technology is not limited to the embodiments, and thus various modifications are made to the embodiments without departing from the claimed subject-matter.

Claim 1:
A solid-state image pickup element (<NUM>) including:
an analog-to-digital conversion unit (<NUM>) in which a plurality of analog-to-digital converters (<NUM>) is arranged in a two-dimensional grid pattern, the plurality of analog-to-digital converters (<NUM>) each being configured to convert an analog signal into a digital signal;
a plurality of pixel circuits (<NUM>) each configured to generate an analog signal and to supply the analog signal to the analog-to-digital conversion unit (<NUM>);
a correlated double sampling, CDS, circuit (<NUM>) configured to generate a frame in which a predetermined number of lines each including a plurality of digital signals are arranged;
a CDS frame memory (<NUM>) configured to store a frame of reset levels obtained from the plurality of pixel circuits (<NUM>) via the analog-to-digital conversion unit (<NUM>) during initialization of the plurality of pixel circuits (<NUM>) due to a reset signal, as a reset frame;
a time delay integration, TDI, frame memory (<NUM>) configured to retain a (K - <NUM>)-th frame generated before a K-th frame, K being an integer; and
a TDI circuit (<NUM>) configured to perform time delay integration processing of adding the line having a predetermined address in the K-th frame and the line having an address at a certain distance from the predetermined address in the (K - <NUM>)-th frame; wherein
the CDS circuit (<NUM>) is configured to generate the frame with correlated double sampling processing of acquiring, in order to obtain the plurality of digital signals, differences between the stored reset levels and signal levels corresponding to an amount of exposure;
the CDS circuit (<NUM>) is disposed on a predetermined circuit chip between the analog-to-digital conversion unit (<NUM>) and the CDS frame memory (<NUM>);
the TDI circuit (<NUM>) is disposed on the predetermined circuit chip between the CDS frame memory (<NUM>) and the TDI frame memory (<NUM>);
the plurality of pixel circuits (<NUM>) is disposed on a predetermined light-receiving chip (<NUM>); and
the TDI frame memory (<NUM>) is disposed on the predetermined circuit chip (<NUM>) layered to the light-receiving chip (<NUM>).