Patent Description:
Radio frequency components based on compound semiconductor materials are widely used in base stations, radars, consumer electronics, and other products. A radio frequency component, for example, a transistor, generally includes a source, a gate, and a drain. The source may be grounded through conductive wire bonding.

However, there is parasitic inductance on a conductive wire, and the source of the transistor is electrically connected to the conductive wire. As a result, parasitic inductance of the source is increased, and a gain of the transistor is reduced.

Therefore, the source of the transistor is usually directly grounded through a back hole of a substrate, instead of being grounded through conductive wire bonding. In this way, a parasitic parameter can be reduced, and performance of the transistor can be improved. However, because the back hole of the substrate is usually designed right below a source metal, a design in which the back hole of the substrate is introduced inevitably increases a width of the source metal. This increases an area of a transistor chip and increases costs of the radio frequency component.

<CIT> discloses a GaAs field effect transistor of the prior art, comprising a source via extending through adjacent source electrodes.

To resolve the foregoing technical problems, this application provides a chip and a chip preparation method, to avoid a case in which a source conducting layer is incorrectly etched and consequently an epitaxial layer cannot be in full contact with the source conducting layer when a layout area of the chip is reduced.

According to a first aspect, this application provides a chip preparation method. A chip includes a first transistor and a second transistor, and the chip preparation method includes: first forming, on a substrate, an epitaxial layer and a source conducting layer that are sequentially disposed in a stacked manner, where the epitaxial layer includes a first via, to form a first epitaxial layer of the first transistor and a second epitaxial layer of the second transistor; the source conducting layer includes a first source of the first transistor and a second source of the second transistor; the first source is disposed on a side of the first epitaxial layer opposite to the substrate, and the second source is disposed on a side of the second epitaxial layer opposite to the substrate; and an edge of the first source is flush with an edge of the first epitaxial layer close to a side of the first via, and an edge of the second source is flush with an edge of the second epitaxial layer close to a side of the first via; then, forming a first conducting layer, where the first conducting layer is filled in the first via, and is in contact with the first source and the second source separately; then, forming a second via on the substrate, where the second via and the first via at least partially overlap; and then, forming a second conducting layer, where the second conducting layer is located in the second via, and the second conducting layer is in contact with the first conducting layer and is grounded.

In the solution of this application, the epitaxial layer is formed through a front-side lithography process. To be specific, lithography is performed on a semiconductor film along a direction from the source conducting layer to the semiconductor film. In addition, lithography precision of the front-side lithography process may be less than <NUM>, and is far higher than that of a back-side lithography process. Therefore, when the semiconductor film is etched, a case in which the source conducting layer is incorrectly etched and the first epitaxial layer and the second epitaxial layer are over-etched due to a deviation of the lithography process is avoided, so that it can be ensured that the first epitaxial layer is in full contact with the first source, and the second epitaxial layer is in full contact with the second source. When the first transistor is connected, the first epitaxial layer may effectively transmit a current to the first source, and then the first source releases the current to the ground through the first conducting layer and the second conducting layer. When the second transistor is connected, the second epitaxial layer may effectively transmit a current to the second source, and then the second source releases the current to the ground through the first conducting layer and the second conducting layer. In addition, in comparison with a related technology, in the transistors in this application, a length of the first epitaxial layer protruding from the first source and a length of the second epitaxial layer protruding from the second source do not need to be reserved. Therefore, layout areas of the first transistor, the second transistor, and even the chip can be reduced.

In a possible implementation, the step of forming, on a substrate, an epitaxial layer and a source conducting layer that are sequentially disposed in a stacked manner specifically includes: first sequentially forming the semiconductor film and the source conducting layer on the substrate; and then, providing the first via in the semiconductor film, to obtain the epitaxial layer.

In this case, the edge of the first source is flush with the edge of the first epitaxial layer close to the side of the first via, and the edge of the second source is flush with the edge of the second epitaxial layer close to the side of the first via. Alternatively, due to a process reason, there may be a tolerance between the actually formed first epitaxial layer and first source, and there may be a tolerance between the second epitaxial layer and the second source. A surface of the first epitaxial layer opposite to the substrate may also be flush with the edge of the first source, and a surface of the second epitaxial layer opposite to the substrate may also be flush with the edge of the second source. However, a surface that is of the first epitaxial layer and that faces the substrate may protrude from the edge of the first source, and a surface that is of the second epitaxial layer and that faces the substrate may protrude from the edge of the second source.

In another possible implementation, the step of forming, on a substrate, an epitaxial layer and a source conducting layer that are disposed in a stacked manner specifically includes: first forming a semiconductor film on the substrate; then, providing the first via in the semiconductor film, to obtain the epitaxial layer; and then, forming the source conducting layer on a side of the epitaxial layer opposite to the substrate. Because the first source and the second source are formed after the first epitaxial layer and the second epitaxial layer are formed, an etching material for etching the semiconductor film does not affect patterns of the first source and the second source.

In this case, the edge of the first source is flush with the edge of the first epitaxial layer close to the side of the first via, and the edge of the second source is flush with the edge of the second epitaxial layer close to the side of the first via. Alternatively, a part of the first source and a part of the second source further extend to the first via. Alternatively, due to a process reason, there may be a tolerance between the actually formed first epitaxial layer and first source, and there may be a tolerance between the second epitaxial layer and the second source. A surface of the first epitaxial layer opposite to the substrate may also be flush with the edge of the first source, and a surface of the second epitaxial layer opposite to the substrate may also be flush with the edge of the second source. However, a surface that is of the first epitaxial layer and that faces the substrate may protrude from the edge of the first source, and a surface that is of the second epitaxial layer and that faces the substrate may protrude from the edge of the second source.

In some possible implementations, in the foregoing two implementations, the step of providing the first via in the semiconductor film, to obtain the epitaxial layer specifically includes: first forming a photoresist on a side of the semiconductor film opposite to the substrate; then, exposing the photoresist, and developing the photoresist to obtain a photoresist pattern; and then, etching the semiconductor film along a direction from the epitaxial layer to the substrate, to obtain the first epitaxial layer and the second epitaxial layer.

In some possible implementations, the semiconductor film may be etched through the front-side lithography process. The precision of the front-side lithography process is higher than that of the back-side lithography process, and alignment precision of the front-side lithography process can be less than <NUM>. Therefore, when the semiconductor film is etched through the front-side lithography process, a case in which the first source and the second source are incorrectly etched and the first epitaxial layer and the second epitaxial layer are over-etched due to the deviation of the lithography process is avoided, so that it is ensured that the first source is in full contact with the first epitaxial layer, and it is ensured that the second source is in full contact with the second epitaxial layer.

In some possible implementations, although a commonly used chlorine-based gas has etching effect on materials of the first epitaxial layer and the second epitaxial layer, and materials of the first source and the second source, because the semiconductor film is etched through the front-side lithography process in this application, and the alignment precision is very high, the chlorine-based gas is not in contact with the first source and the second source, and therefore does not affect the pattern of the source. Based on this, in this application, etching may be further performed on the semiconductor film by using the chlorine-based gas, to obtain the first epitaxial layer and the second epitaxial layer.

In some possible implementations, the step of forming a second via specifically includes: etching the substrate along a direction from the substrate to the epitaxial layer, to obtain the second via.

In some possible implementations, the first via and the second via are disposed oppositely, and an edge that is of the first source and that faces the second source is flush with an edge that is of the first epitaxial layer and that faces the second epitaxial layer. In other words, the edge of the first source is flush with the edge of the first epitaxial layer close to the side of the first via, and the edge of the second source is flush with the edge of the second epitaxial layer close to the side of the first via, so that the second conducting layer is in contact with the first conducting layer. In addition, along a direction from the first source to the second source, a length of the first via is the same as a length of the second via. In this way, the second conducting layer to be formed may be in full contact with the first conducting layer.

In some possible implementations, the first via and the second via are disposed oppositely, so that the second conducting layer is in contact with the first conducting layer. In addition, along the direction from the first source to the second source, the length of the first via is less than the length of the second via. In this way, the second conducting layer to be formed may be in full contact with the first conducting layer. In addition, the length of the first via may be reduced while the length of the second via remains unchanged. This further reduces the layout areas occupied by the first transistor and the second transistor.

In some possible implementations, the first via and the second via are not disposed oppositely, but the second conducting layer is still in contact with the first conducting layer. In addition, along the direction from the first source to the second source, the length of the first via is less than the length of the second via. In this way, the length of the first via may be reduced while the length of the second via remains unchanged. This further reduces the layout areas occupied by the first transistor and the second transistor.

In some possible implementations, the first via and the second via may be disposed oppositely, or may not be disposed oppositely, and the second conducting layer is in contact with the first conducting layer. In addition, orthographic projections of the source conducting layer and the first via on the substrate are within a range of the second via, and along the direction from the first source to the second source, a total length from an edge of the first source opposite to the second source to an edge of the second source opposite to the first source is less than the length of the second via. In this way, the second conducting layer to be formed may be in full contact with the first conducting layer. In addition, a first gate is disposed on a side of the epitaxial layer opposite to the substrate, the first gate is located on a side of the first source opposite to the second source, and a second gate is located on a side of the second source opposite to the first source. A material of the second conducting layer may be a metal material, and a thermal conductivity of the metal material is higher than a thermal conductivity of a material of the substrate. Therefore, when the first gate and the second gate generate heat, the heat on the first gate may be conducted to the second conducting layer through the first epitaxial layer, and the heat on the second gate may be conducted to the second conducting layer through the second epitaxial layer, to avoid impact on performance of the transistor due to excessively high temperatures of the first gate and the second gate.

According to a second aspect, this application provides a chip. The chip may be prepared by using the method according to the first aspect. The chip includes a substrate and a first transistor and a second transistor that are disposed on the substrate. The first transistor includes a first epitaxial layer and a first source that are sequentially disposed on the substrate in a stacked manner, the second transistor includes a second epitaxial layer and a second source that are sequentially disposed on the substrate in the stacked manner, and a first via is provided between the first epitaxial layer and the second epitaxial layer. An edge of the first source is flush with an edge of the first epitaxial layer close to a side of the first via, and an edge of the second source is flush with an edge of the second epitaxial layer close to a side of the first via. The chip further includes a first conducting layer, where the first conducting layer is in contact with the first source and the second source separately, and is filled in the first via between the first epitaxial layer and the second epitaxial layer. The substrate includes a second via, and the chip further includes a second conducting layer, where the second conducting layer is filled in the second via, and the second conducting layer is in contact with the first conducting layer and is grounded.

In the solution of this application, the first epitaxial layer and the second epitaxial layer are formed through a front-side lithography process. To be specific, lithography is performed on a semiconductor film along a direction from a source conducting layer to the semiconductor film. In addition, lithography precision of the front-side lithography process may be less than <NUM>, and is far higher than that of a back-side lithography process. Therefore, when the semiconductor film is etched, a case in which the source conducting layer is incorrectly etched and the epitaxial layer is over-etched due to a deviation of the lithography process is avoided, so that it can be ensured that the epitaxial layer is in full contact with the first source and the second source separately. When the first transistor is connected, the first epitaxial layer may effectively transmit a current to the first source, and then the first source releases the current to the ground through the first conducting layer and the second conducting layer. When the second transistor is connected, the second epitaxial layer may effectively transmit a current to the second source, and then the second source releases the current to the ground through the first conducting layer and the second conducting layer. In addition, in comparison with a related technology, in the transistors in this application, a length L2 of the epitaxial layer protruding from the source does not need to be reserved. Therefore, layout areas of the first transistor, the second transistor, and even the chip can be reduced.

In a possible implementation, the edge of the first source is flush with the edge of the first epitaxial layer close to the side of the first via, and the edge of the second source is flush with the edge of the second epitaxial layer close to the side of the first via. A structure in this implementation may be implemented through the process in the first aspect. Specifically, the structure may be implemented by sequentially forming the semiconductor film and the source conducting layer on the substrate first, and then providing the first via in the semiconductor film, to obtain the epitaxial layer. Alternatively, the semiconductor film may be first formed on the substrate, then the first via is provided in the semiconductor film, to obtain the epitaxial layer, and then the source conducting layer is formed on a side of the epitaxial layer opposite to the substrate.

In another possible implementation, an edge that is of the first source and that faces the second source protrudes from an edge that is of the first epitaxial layer and that faces the second epitaxial layer; and an edge that is of the second source and that faces the first source protrudes from an edge that is of the second epitaxial layer and that faces the first epitaxial layer. In other words, a part of the first source and a part of the second source further extend to the first via. A structure in this implementation may be implemented through the process in the first aspect. Specifically, the semiconductor film may be first formed on the substrate, and then the first via is provided in the semiconductor film, to obtain the first epitaxial layer and the second epitaxial layer. Then, the first source is formed on a side of the first epitaxial layer opposite to the substrate, and the second source is formed on a side of the second epitaxial layer opposite to the substrate.

In addition, due to a process reason, there may be a tolerance between the actually formed first epitaxial layer and first source, and there may be a tolerance between the second epitaxial layer and the second source. A surface of the first epitaxial layer opposite to the substrate may also be flush with the edge of the first source, and a surface of the second epitaxial layer opposite to the substrate may also be flush with the edge of the second source. However, a surface that is of the first epitaxial layer and that faces the substrate may protrude from the edge of the first source, and a surface that is of the second epitaxial layer and that faces the substrate may protrude from the edge of the second source.

In some possible implementations, the first via and the second via are disposed oppositely, and the edge that is of the first source and that faces the second source is flush with the edge that is of the first epitaxial layer and that faces the second epitaxial layer. In other words, the edge of the first source is flush with the edge of the first epitaxial layer close to the side of the first via, and the edge of the second source is flush with the edge of the second epitaxial layer close to the side of the first via, so that the second conducting layer is in contact with the first conducting layer. In addition, along a direction from the first source to the second source, a length of the first via is the same as a length of the second via. In this way, the second conducting layer to be formed may be in full contact with the first conducting layer.

In some possible implementations, the first via and the second via may be disposed oppositely, or may not be disposed oppositely, and the second conducting layer is in contact with the first conducting layer. In addition, orthographic projections of the source conducting layer and the first via on the substrate are within a range of the second via, and along the direction from the first source to the second source, a total length from an edge of the first source opposite to the second source to an edge of the second source opposite to the first source is less than the length of the second via. In this way, the second conducting layer to be formed may be in full contact with the first conducting layer. In addition, a first gate is disposed on a side of the epitaxial layer opposite to the substrate, the first gate is located on a side of the first source opposite to the second source, and a second gate is located on a side of the second source opposite to the first source. A material of the second conducting layer may be a metal material, and a thermal conductivity of the metal material is higher than a thermal conductivity of a material of the substrate. Therefore, when the first gate and the second gate generate heat, the heat on the first gate may be exported to the second conducting layer through the first epitaxial layer, and the heat on the second gate may be exported to the second conducting layer through the second epitaxial layer, to avoid impact on performance of the transistor due to excessively high temperatures of the first gate and the second gate.

<NUM>-Baseband processing unit; <NUM>-Transmitter; <NUM>-Radio frequency signal generation circuit; <NUM>-Power amplifier; <NUM>-Filter; <NUM>-Antenna; <NUM>-Substrate; <NUM>-Epitaxial layer; <NUM>-First epitaxial layer; <NUM>-Second epitaxial layer; <NUM>-Semiconductor film; <NUM>-Source; <NUM>-First conducting layer; <NUM>-Second conducting layer; <NUM>-Source conducting layer; <NUM>-First source; <NUM>-Second source; <NUM>-Drain; <NUM>-First drain; <NUM>-Second drain; <NUM>-First gate; <NUM>-Second gate; and <NUM>-Third photoresist pattern.

The following clearly and completely describes the technical solutions in embodiments of this application with reference to the accompanying drawings in embodiments of this application. It is clear that the described embodiments are some but not all of embodiments of this application.

The term "and/or" in this specification describes only an association relationship for describing associated objects and represents that three relationships may exist.

In the specification and claims in embodiments of this application, the terms "first", "second", and so on are intended to distinguish between different objects but do not indicate a particular order of the objects. For example, a first target object, a second target object, and the like are used for distinguishing between different target objects, but are not used for describing a specific order of the target objects.

In addition, in embodiments of this application, the word "exemplary" or "for example" is used to represent giving an example, an illustration, or a description. Any embodiment or design scheme described as an "example" or "for example" in embodiments of this application should not be explained as being more preferred or having more advantages than another embodiment or design scheme. To be precise, the word "example", "for example", or the like is intended to present a related concept in a specific manner.

In the descriptions of embodiments of this application, unless otherwise stated, "a plurality of" means two or more than two. For example, a plurality of processing units are two or more processing units, and a plurality of systems are two or more systems.

An embodiment of this application provides a terminal, so that a parasitic capacitance of a source of a transistor can be reduced, a gain of the transistor can be increased, and a layout area of the transistor can be reduced.

The following describes a specific structure and usage of the terminal provided in this embodiment of this application.

The terminal <NUM> may be a base station, a computer, a tablet computer, a personal digital assistant (personal digital assistant, PDA for short), an intelligent wearable device, a smart home device, or the like. This is not limited in this embodiment of this application.

<FIG> is a diagram of an application scenario of the terminal <NUM> according to an embodiment of this application. The terminal <NUM> may be a base station, and the base station may include a baseband processing unit <NUM> and a transmitter <NUM>. The transmitter <NUM> may include a radio frequency signal generation circuit <NUM>, a power amplifier <NUM>, a filter <NUM>, and an antenna <NUM>.

The baseband processing unit <NUM> is configured to generate a baseband digital signal.

The radio frequency signal generation circuit <NUM> is configured to process the baseband digital signal, to obtain a radio frequency signal.

The power amplifier <NUM> is configured to perform power amplification on the radio frequency signal.

The filter <NUM> is configured to perform filtering processing on a power-amplified radio frequency signal, to obtain a to-be-transmitted signal.

The antenna <NUM> is configured to transmit the to-be-transmitted signal.

<FIG> shows a circuit diagram of the foregoing power amplifier <NUM>. The power amplifier <NUM> includes a direct current input end Vgate, a radio frequency input end RF In, a voltage end VDD, a transistor, and an output end RF Out.

An example in which the transistor is an N-type transistor and the radio frequency signal is a sine wave is used. A gate Gate of the transistor receives a direct current signal input through the direct current input end Vgate and the radio frequency signal input through the radio frequency input end RF In. When the radio frequency signal is positive, the transistor is connected, and the voltage end VDD is grounded through the transistor; and when the radio frequency signal is negative, the transistor is cut off, the voltage end VDD is connected to the output end RF Out, and the power-amplified radio frequency signal is output through the output end RF Out.

As proposed in the background, currently, the source of the transistor is grounded, and may be grounded through the conductive wire. However, there is the parasitic inductance on the conductive wire. As a result, the parasitic inductance of the source is increased, and the performance of the transistor deteriorates (where the gain is reduced). Alternatively, the source may be grounded through the back hole of the substrate. However, because space needs to be reserved for providing the back hole of the substrate in a chip design, the layout area of the chip is increased, and the costs are increased.

Specifically, as shown in <FIG>, the transistor includes an epitaxial layer <NUM>, a source <NUM>, and a first conducting layer <NUM> that are disposed on a substrate <NUM>, and further includes a second conducting layer <NUM>. A via may be formed on the substrate <NUM> and the epitaxial layer <NUM> along a direction from the substrate <NUM> to the epitaxial layer <NUM> through a back-side lithography process, and the second conducting layer <NUM> is disposed in the via, and is in contact with the first conducting layer <NUM>. In this way, when the transistor is connected, the epitaxial layer <NUM> transmits a current to the source <NUM> along a direction from the epitaxial layer <NUM> to the source <NUM>. Further, the source <NUM> transmits the current to the grounded second conducting layer <NUM> through the first conducting layer <NUM>.

However, in a solution of a related technology, after the source <NUM> is formed, patterns of the substrate and the epitaxial layer <NUM> are obtained through etching by using the back-side lithography process. As shown in <FIG>, alignment precision of the back-side lithography process is excessively low (where a contact lithography machine is usually selected for the lithography process), and an alignment deviation is generally greater than or equal to <NUM>. When the epitaxial layer <NUM> is etched, the epitaxial layer <NUM> may be over-etched, and consequently, the epitaxial layer <NUM> cannot be in full contact with the source <NUM>. In addition, as shown in <FIG>, the epitaxial layer <NUM> is usually etched by using a chlorine-based gas, and the chlorine-based gas also has etching effect on the source <NUM>. Therefore, when the epitaxial layer <NUM> is etched, the source <NUM> may also be etched, and a length L1 of the source <NUM> becomes shorter. Consequently, the epitaxial layer <NUM> cannot be in full good contact with the source <NUM>, and ohmic contact is abnormal. When the epitaxial layer <NUM> cannot be in full contact with the source <NUM>, the epitaxial layer <NUM> may fail to transmit the current to the source <NUM>.

It should be noted herein that, before the gate of the transistor is formed, a pattern of the source <NUM> is formed, and high-temperature annealing processing is performed on the source <NUM>. Therefore, mutual capacitance can be implemented between the source <NUM> and the epitaxial layer <NUM>, to form ohmic contact. The first conducting layer <NUM> is formed after the gate is formed. To avoid impact of an annealing process on the gate and a problem in controlling the epitaxial layer <NUM> by the gate, no annealing process is performed after a pattern of the first conducting layer <NUM> is formed. Therefore, even if the first conducting layer <NUM> is in contact with the epitaxial layer <NUM>, mutual capacitance cannot be implemented between the first conducting layer <NUM> and the epitaxial layer <NUM> (where ohmic contact is formed). In other words, the epitaxial layer <NUM> cannot directly transmit the current to the first conducting layer <NUM>.

As shown in <FIG>, to resolve a problem that the source <NUM> is partially damaged, the related technology proposes that the epitaxial layer <NUM> may protrude from the source <NUM>, and a length of the epitaxial layer <NUM> protruding from the source <NUM> is L2. However, in this manner, a layout area of the transistor is increased, and especially, a plurality of transistors are generally connected in parallel on the chip, causing a great increase in the chip area. In addition, as shown in <FIG>, because the alignment precision of the back-side lithography process is low, a case in which the via of the epitaxial layer <NUM> is formed right below the source <NUM> still exists. Therefore, a case in which the source <NUM> is etched while the epitaxial layer <NUM> is etched still exists.

Based on the foregoing problems, an embodiment of this application provides a chip preparation method. As shown in <FIG>, a plurality of transistors may be disposed on a chip, each transistor includes a source <NUM>/<NUM> and a drain <NUM>, and the drain <NUM> may be disposed between the sources <NUM> and the sources <NUM> of two adjacent transistors, so that the two adjacent transistors share the same drain <NUM>. The plurality of transistors may include a first transistor and a second transistor. The first transistor and the second transistor may be gallium nitride (gallium nitride, GaN) based high electron mobility transistors (high electron mobility transistors, HEMTs), gallium arsenide (gallium arsenide, GaAs) based pseudomorphic high electron mobility transistors (pseudomorphic high electron mobility transistors, PHEMTs), or the like.

In this application, a first epitaxial layer <NUM> of the first transistor and a second epitaxial layer <NUM> of the second transistor may be etched through a front-side lithography process. In other words, the first epitaxial layer <NUM> of the first transistor and the second epitaxial layer <NUM> of the second transistor may be etched along a direction from an epitaxial layer <NUM> to a substrate <NUM>, to avoid impact of etching of the first epitaxial layer <NUM> and the second epitaxial layer <NUM> on a pattern of the source <NUM>. In addition, layout areas occupied by the first transistor and the second transistor may be further reduced. Specifically, the transistor may be formed in the following two embodiments.

In an embodiment, as shown in <FIG>, the step of forming the transistor may be implemented through the following steps.

S110: Sequentially form a semiconductor film <NUM> and a source conducting layer <NUM> on the substrate <NUM>, as shown in <FIG>. The source conducting layer <NUM> includes the first source <NUM> and the second source <NUM> that are disposed at an interval. An example in which the chip includes the first transistor and the second transistor is used. The first source <NUM> may be used as a source <NUM> of the first transistor, and the second source <NUM> may be used as a source <NUM> of the second transistor.

In some possible implementations, a specific process of forming the semiconductor film <NUM> and the source conducting layer <NUM> may include: first sequentially forming the semiconductor film <NUM>, a first conductive film, and a first photoresist on the substrate <NUM>; then exposing the first photoresist, developing the first photoresist to obtain a first photoresist pattern, and etching the first conductive film under protection of the first photoresist pattern, to obtain a pattern of the source conducting layer <NUM>; removing the first photoresist pattern; and performing high-temperature annealing processing on the pattern of the source conducting layer <NUM>, to obtain the source conducting layer <NUM>. It is clear that the source conducting layer <NUM> may alternatively be formed in another manner. This is not specially limited in this embodiment of this application.

In some possible implementations, as shown in <FIG>, when the source conducting layer <NUM> is formed, a first drain <NUM> of the first transistor and a second drain <NUM> of the second transistor may be further formed through a same semiconductor process, to omit a process of additionally forming the first drain <NUM> and the second drain <NUM>, and save a mask (mask). The first drain <NUM> and the second drain <NUM> are disposed on a same layer as the first source <NUM> and the second source <NUM>, the first drain <NUM> is disposed on a side of the first source <NUM> opposite to the second source <NUM>, and the second drain <NUM> is disposed on a side of the second source <NUM> opposite to the first source <NUM>.

In some possible implementations, as shown in <FIG>, after step S110 and before step S120, a transistor preparation method may further include: forming a first gate <NUM> of the first transistor and a second gate <NUM> of the second transistor. Specifically, a specific process of forming the first gate <NUM> and the second gate <NUM> includes: sequentially forming a gate film and a second photoresist on a side of the semiconductor film <NUM> opposite to the substrate <NUM>; exposing the second photoresist, developing the second photoresist to obtain a second photoresist pattern, and etching the gate film under protection of the second photoresist pattern, to obtain patterns of the first gate <NUM> and the second gate <NUM>; removing the second photoresist pattern; and performing high-temperature annealing processing on the patterns of the first gate <NUM> and the second gate <NUM>, to obtain the first gate <NUM> and the second gate <NUM>. It is clear that the step of forming the first gate <NUM> and the second gate <NUM> may be performed between step S120 and step S130. This is not limited in this embodiment of this application.

As shown in <FIG>, the first gate <NUM> and the second gate <NUM> are disposed on the side of the semiconductor film <NUM> opposite to the substrate <NUM>, the first gate <NUM> is disposed on the side of the first source <NUM> opposite to the second source <NUM>, and the second gate <NUM> is disposed on the side of the second source <NUM> opposite to the first source <NUM>.

In some possible implementations, the first source <NUM> and the second source <NUM> may have one layer, or may be stacked. Materials of the first source <NUM> and the second source <NUM> may include at least one of metals such as titanium (Ti), titanium nitride (TiN), aluminum (Al), nickel (Ni), platinum (Pt), palladium (Pd), chromium (Cr), and gold (Au). The materials of the first source <NUM> and the second source <NUM> may alternatively include a conductive oxide material such as indium tin oxide (indium tin oxide, ITO). Considering that the first source <NUM> and the second source <NUM> may be prepared through a same semiconductor process, the first source <NUM> and the second source <NUM> may have a same quantity of layers, and each layer of the first source <NUM> and the second source <NUM> has a same material.

S120: Provide a first via in the semiconductor film <NUM>, to obtain the epitaxial layer <NUM> including the first epitaxial layer <NUM> and the second epitaxial layer <NUM>, where the first via is located between the first epitaxial layer <NUM> and the second epitaxial layer <NUM>, as shown in <FIG>. In addition, the first source <NUM> is disposed on a side of the first epitaxial layer <NUM> opposite to the substrate <NUM>, and the second source <NUM> is disposed on a side of the second epitaxial layer <NUM> opposite to the substrate <NUM>.

In some possible implementations, as shown in <FIG>, a specific process of providing the first via in the semiconductor film <NUM>, to obtain the epitaxial layer <NUM> may include: forming a third photoresist on the side of the semiconductor film <NUM> opposite to the substrate <NUM>; and exposing the third photoresist, developing the third photoresist to obtain a third photoresist pattern <NUM>, and etching the semiconductor film <NUM> under protection of the third photoresist pattern <NUM>, to obtain the epitaxial layer <NUM> including the first epitaxial layer <NUM>, the second epitaxial layer <NUM>, and the first via.

On this basis, after step S120 and before step S130, the chip preparation method may further include: stripping the third photoresist pattern <NUM>.

In a possible implementation, although a commonly used chlorine-based gas has etching effect on materials of the epitaxial layer <NUM> and the source <NUM>, because the semiconductor film is etched through the front-side lithography process in this application, and alignment precision of the front-side lithography process is very high, and is far higher than alignment precision of the back-side lithography process, the chlorine-based gas is not in contact with the first source <NUM> and the second source <NUM>, and therefore does not affect patterns of the first source <NUM> and the second source <NUM>, resulting in a case in which the first epitaxial layer <NUM> is not in full contact with the first source <NUM> and the second epitaxial layer <NUM> is not in full contact with the second source <NUM> when the semiconductor film <NUM> is etched by using the chlorine-based gas in a lithography manner of this application.

Based on this, in this application, the semiconductor film <NUM> may be etched along a direction from the source conducting layer <NUM> to the semiconductor film <NUM> by using the chlorine-based gas, to obtain the epitaxial layer <NUM> including the first epitaxial layer <NUM>, the second epitaxial layer <NUM>, and the first via. It is clear that the semiconductor film <NUM> may be etched by using another etching material. This is not limited in this embodiment of this application.

It should be noted herein that, as shown in <FIG>, the third photoresist pattern <NUM> may expose a part that is of the semiconductor film <NUM> and in which the first via is to be formed, and cover each exposed surface of the source conducting layer <NUM> and a part of the semiconductor film <NUM> other than the part in which the first via is to be formed, to avoid a case in which the source conducting layer <NUM> is incorrectly etched in a process of etching the semiconductor film <NUM> (especially in a process of etching the semiconductor film <NUM> by using the chlorine-based gas).

On this basis, in this application, the epitaxial layer <NUM> is formed through the front-side lithography process. To be specific, lithography is performed on the semiconductor film <NUM> along the direction from the source conducting layer <NUM> to the semiconductor film <NUM>. In addition, the alignment precision of the front-side lithography process may be less than <NUM>, and is far higher than the alignment precision of the back-side lithography process. Therefore, when the semiconductor film <NUM> is etched, a case in which the source conducting layer <NUM> is incorrectly etched and the first epitaxial layer <NUM> and the second epitaxial layer <NUM> are over-etched due to a deviation of the lithography process is avoided, so that it can be ensured that the first epitaxial layer <NUM> is in full contact with the first source <NUM>, and the second epitaxial layer <NUM> is in full contact with the second source <NUM>. When the first transistor is connected, the first epitaxial layer <NUM> may effectively transmit a current to the first source <NUM>, and the current is released to the ground through the first source <NUM>. When the second transistor is connected, the second epitaxial layer <NUM> may effectively transmit a current to the second source <NUM>, and the current is released to the ground through the second source <NUM>.

In addition, in the first transistor and the second transistor that are formed in the foregoing steps S110 to S130, there may be the following several cases for a location relationship between the source conducting layer <NUM> and the epitaxial layer <NUM>.

As shown in <FIG>, an edge that is of the first source <NUM> and that faces the second source <NUM> is flush with an edge of the first via close to the first source <NUM>, and an edge that is of the second source <NUM> and that faces the first source <NUM> is flush with an edge of the first via close to the second source <NUM>. In other words, an edge of the first source <NUM> is flush with an edge of the first epitaxial layer <NUM> close to a side of the first via, and an edge of the second source <NUM> is flush with an edge of the second epitaxial layer <NUM> close to a side of the first via. In addition, along a direction from the first source <NUM> to the second source <NUM>, a length L1' of the first source <NUM> and a length L1" of the second source <NUM> are both equal to the length L1 of the source <NUM> in the related technology shown in <FIG>. However, in the solution of this application, the first epitaxial layer <NUM> does not need to protrude from the first source <NUM> along the direction from the first source <NUM> to the second source <NUM>, and the second epitaxial layer <NUM> does not need to protrude from the second source <NUM> along a direction from the second source <NUM> to the first source <NUM>. In other words, a length of the first epitaxial layer <NUM> protruding from the first source <NUM> is <NUM>, and a length of the second epitaxial layer <NUM> protruding from the second source <NUM> is <NUM>. Therefore, the layout areas occupied by the first transistor and the second transistor can be reduced, and a layout area of the entire chip is further reduced.

For example, along the direction from the first source <NUM> to the second source <NUM>, both the length L1' of the first source <NUM> and the length L1" of the second source <NUM> are <NUM>. In the related technology shown in <FIG>, the length L2 of the epitaxial layer <NUM> protruding from the source <NUM> is <NUM>. Therefore, in comparison with the related technology, in the solution of this application, a layout of the source <NUM> occupied by one first transistor and one second transistor may be reduced by <NUM>*L2=<NUM>, and a reduction percentage is <NUM>%.

In an alternative not forming part of the invention as claimed, as shown in <FIG>, in the source conducting layer <NUM> and the epitaxial layer <NUM> that are formed through the foregoing process, the first epitaxial layer <NUM> protrudes from the first source <NUM> along a direction from the first source <NUM> to the second source <NUM>, and a length of a protruding part is L2'; and the second epitaxial layer <NUM> protrudes from the second source <NUM> along a direction from the second source <NUM> to the first source <NUM>, and a length of a protruding part is L2'. However, in this application, the first epitaxial layer <NUM> and the second epitaxial layer <NUM> are formed through the front-side lithography process, and the alignment precision of the front-side lithography process is far higher than the alignment precision of the back-side lithography process. Therefore, in this application, the length L2' of the first epitaxial layer <NUM> protruding from the first source <NUM> and the length L2' of the second epitaxial layer <NUM> protruding from the second source <NUM> may be far less than the length L2 of the epitaxial layer <NUM> protruding from the source <NUM> in the related technology shown in <FIG>. Therefore, the layout areas occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

For example, along the direction from the first source <NUM> to the second source <NUM>, both the length L1' of the first source <NUM> and the length L1" of the second source <NUM> are <NUM>. In the related technology shown in <FIG>, the length L2 of the epitaxial layer <NUM> protruding from the source <NUM> is <NUM>. However, in this application, the length L2' of the first epitaxial layer <NUM> protruding from the first source <NUM> and the length L2' of the second epitaxial layer <NUM> protruding from the second source <NUM> are both <NUM>. Therefore, in comparison with the related technology, in the solution of this application, a layout of the source <NUM> occupied by one first transistor and one second transistor may be reduced by <NUM>*(L2-L2')=<NUM>, and a reduction percentage is <NUM>%.

Alternatively, due to a process reason, a tolerance may exist between the actually formed first epitaxial layer <NUM> and first source <NUM>, and a tolerance may exist between the second epitaxial layer <NUM> and the second source <NUM>. Therefore, in some possible implementations, as shown in <FIG>, a surface of the first epitaxial layer <NUM> opposite to the substrate <NUM> may also be flush with the edge of the first source <NUM>, and a surface of the second epitaxial layer <NUM> opposite to the substrate <NUM> may also be flush with the edge of the second source <NUM>. However, a surface that is of the first epitaxial layer <NUM> and that faces the substrate <NUM> may protrude from the edge of the first source <NUM>, and a surface that is of the second epitaxial layer <NUM> and that faces the substrate <NUM> may protrude from the edge of the second source <NUM>.

In some possible implementations, the first epitaxial layer <NUM> and the second epitaxial layer <NUM> may include a multi-layer structure. If the first transistor and the second transistor are the GaN based HEMTs, a material of the multi-layer structure may include AlxGayN, where <NUM>≤x≤<NUM>, <NUM>≤y≤<NUM>, and x+y=<NUM>. If the first transistor and the second transistor are the GaAs based PHEMTs, a material of the multi-layer structure may include AlGaAs or high-purity GaAs. Considering that the first epitaxial layer <NUM> and the second epitaxial layer <NUM> may be prepared through a same semiconductor process, the first epitaxial layer <NUM> and the second epitaxial layer <NUM> may have a same quantity of layers, and each layer of the first epitaxial layer <NUM> and the second epitaxial layer <NUM> has a same material.

S130: Form a first conducting layer <NUM>, as shown in <FIG>. The first conducting layer <NUM> is filled in the first via, and is in contact with the first source <NUM> and the second source <NUM> separately.

In some possible implementations, a specific process of forming the first conducting layer <NUM> may include: first sequentially forming a second conductive film and a fourth photoresist on a side of the source conducting layer <NUM> opposite to the substrate <NUM>; then exposing the fourth photoresist, developing the fourth photoresist to obtain a fourth photoresist pattern, and etching the second conductive film under protection of the fourth photoresist pattern, to obtain the first conducting layer <NUM>; and removing the fourth photoresist pattern. It is clear that the source conducting layer <NUM> may alternatively be formed in another manner. This is not specially limited in this embodiment of this application.

In some possible implementations, a specific location at which the first conducting layer <NUM> is disposed is not limited in this embodiment of this application, provided that the first conducting layer <NUM> is filled in the first via, and is in contact with the first source <NUM> and the second source <NUM> separately. Optionally, as shown in <FIG>, the first conducting layer <NUM> is filled in the first via, and completely covers a surface of the source conducting layer <NUM> opposite to the substrate <NUM>. Alternatively, as shown in <FIG>, the first conducting layer <NUM> is filled in the first via, is disposed on the side of the source conducting layer <NUM> opposite to the substrate <NUM>, and partially covers a surface of the source conducting layer <NUM> opposite to the substrate <NUM>. Alternatively, as shown in <FIG>, the first conducting layer <NUM> is filled only in the first via, and is in contact with a side surface that is of the first source <NUM> and that faces the second source <NUM> and a side surface that is of the second source <NUM> and that faces the first source <NUM> separately. In comparison with the two solutions shown in <FIG>, in the solution shown in <FIG>, the first source <NUM> and the second source <NUM> may be in full contact with the first conducting layer <NUM>, and a case in which the first conducting layer <NUM> is not in full contact with the first source <NUM> and/or the second source <NUM> due to a process error may be avoided.

In some possible implementations, the first conducting layer <NUM> may have one layer, or may be stacked. A material of the first conducting layer <NUM> may be a metal such as Ti, TiN, Al, Ni, Pt, Pd, Cr, or Au, or may be a conductive oxide material such as ITO.

S140: Form a second via on the substrate <NUM> along a direction from the substrate <NUM> to the epitaxial layer <NUM>, as shown in <FIG>. The second via and the first via at least partially overlap.

In some possible implementations, the substrate <NUM> may be etched through the back-side lithography process, to obtain the second via. An example in which a material of the substrate <NUM> includes silicon carbide (SiC) or silicon (Si) is used. The substrate <NUM> may be etched by using a fluorine-based gas, to obtain the second via. Because the fluorine-based gas has high etching selectivity for a material of the epitaxial layer <NUM>, the material of the first conducting layer <NUM>, and a material of a second conducting layer <NUM> to be formed, the fluorine-based gas may stay on a surface of the second via. This does not affect forming of the second conducting layer <NUM> in subsequent step S150, or affect patterns of the first epitaxial layer <NUM>, the second epitaxial layer <NUM>, and the first conducting layer <NUM> that have been formed, and therefore does not affect normal contact between the second conducting layer <NUM> and the first conducting layer <NUM> subsequently.

In some possible implementations, a specific location of the second via is not limited in this embodiment of this application, provided that it can be ensured that the second conducting layer <NUM> filled in the second via can be in contact with the first conducting layer <NUM>. The location of the second via is related to the second conducting layer <NUM> to be formed. When the second conducting layer <NUM> is described in step S150, the location of the second via is described in detail.

S150: Form the second conducting layer <NUM> in the second via, as shown in <FIG>. The second conducting layer <NUM> is in contact with the first conducting layer <NUM> and is grounded. In this way, the current sequentially transmitted by the first epitaxial layer <NUM> to the first source <NUM> and the first conducting layer <NUM> and the current sequentially transmitted by the second epitaxial layer <NUM> to the second source <NUM> and the first conducting layer <NUM> may be transmitted to the second conducting layer <NUM> and released to the ground.

In some possible implementations, as shown in <FIG>, the second conducting layer <NUM> may be formed in the second via through an electroplating process. Along the direction from the substrate <NUM> to the epitaxial layer <NUM>, a thickness of the second conducting layer <NUM> is less than a depth of the second via, and the second conducting layer <NUM> extends from a side wall of the second via to a surface that is of the first conducting layer <NUM> and that faces the substrate <NUM>. In addition, as shown in <FIG>, the second conducting layer <NUM> may be filled in the entire second via.

In some possible implementations, a specific location of the second conducting layer <NUM> relative to the first conducting layer <NUM> is not limited in this embodiment of this application, provided that the second conducting layer <NUM> and the first conducting layer <NUM> can be in contact.

In a first case, as shown in <FIG>, the first via and the second via are disposed oppositely, and the edge that is of the first source <NUM> and that faces the second source <NUM> is flush with an edge that is of the first epitaxial layer <NUM> and that faces the second epitaxial layer <NUM>. In other words, the edge of the first source <NUM> is flush with the edge of the first epitaxial layer <NUM> close to the side of the first via, and the edge of the second source <NUM> is flush with the edge of the second epitaxial layer <NUM> close to the side of the first via, so that the second conducting layer <NUM> is in contact with the first conducting layer <NUM>. In addition, along the direction from the first source <NUM> to the second source <NUM>, a length L3 of the first via is the same as a length L4 of the second via. In this way, the second conducting layer <NUM> to be formed may be in full contact with the first conducting layer <NUM>.

In a second case, as shown in <FIG>, the first via and the second via are disposed oppositely, so that the second conducting layer <NUM> is in contact with the first conducting layer <NUM>. In addition, along the direction from the first source <NUM> to the second source <NUM>, a length L3 of the first via is less than a length L4 of the second via. In this way the second conducting layer <NUM> to be formed may be in full contact with the first conducting layer <NUM>. In addition, the length L3 of the first via may be reduced while the length L4 of the second via remains unchanged. This further reduces the layout areas occupied by the first transistor and the second transistor.

In a third case, as shown in <FIG>, the first via and the second via are not disposed oppositely, but the second conducting layer <NUM> is still in contact with the first conducting layer <NUM>. In addition, along the direction from the first source <NUM> to the second source <NUM>, a length L3 of the first via is less than a length L4 of the second via. In this way, the length L3 of the first via may be reduced while the length L4 of the second via remains unchanged. This further reduces the layout areas occupied by the first transistor and the second transistor.

In a fourth case, as shown in <FIG> and <FIG>, the first via and the second via may be disposed oppositely, or may not be disposed oppositely, and the second conducting layer <NUM> is in contact with the first conducting layer <NUM>. In addition, orthographic projections of the source conducting layer <NUM> and the first via on the substrate <NUM> are within a range of the second via, and along the direction from the first source <NUM> to the second source <NUM>, a total length L5 from an edge of the first source <NUM> opposite to the second source <NUM> to an edge of the second source <NUM> opposite to the first source <NUM> is less than a length L4 of the second via. In this way, the second conducting layer <NUM> to be formed may be in full contact with the first conducting layer <NUM>. In addition, as shown in <FIG>, <FIG>, and <FIG>, the first gate <NUM> is disposed on a side of the epitaxial layer <NUM> opposite to the substrate <NUM>, the first gate <NUM> is located on the side of the first source <NUM> opposite to the second source <NUM>, and the second gate <NUM> is located on the side of the second source <NUM> opposite to the first source <NUM>. A material of the second conducting layer <NUM> may be a metal material, and a thermal conductivity of the metal material is higher than a thermal conductivity of the material of the substrate <NUM>. Therefore, when the first gate <NUM> and the second gate <NUM> generate heat, the heat on the first gate <NUM> may be exported to the second conducting layer <NUM> through the first epitaxial layer <NUM>, and the heat on the second gate <NUM> may be exported to the second conducting layer <NUM> through the second epitaxial layer <NUM> (where heat conduction paths are shown by straight lines with arrows in <FIG> and <FIG>), to avoid impact on performance of the transistor due to excessively high temperatures of the first gate <NUM> and the second gate <NUM>.

For example, as shown in <FIG>, the first via and the second via are disposed oppositely, and along the direction from the first source <NUM> to the second source <NUM>, both a length L' of the first source <NUM> and a length L" of the second source <NUM> are <NUM>, a length L3 of the first via is <NUM>, and a size L4 of the second via is <NUM>. In this case, the orthographic projections of the source conducting layer <NUM> and the first via on the substrate <NUM> are within the range of the second via, and the second via protrudes from the first source <NUM> and the second source <NUM> separately. In this way, heat of a gate <NUM> may be exported through the second conducting layer <NUM> filled in the second via.

In the fourth case, in comparison with the solution (<FIG>) in which the thickness of the second conducting layer <NUM> is less than the depth of the second via and the second conducting layer <NUM> extends from the side wall of the second via to the surface that is of the first conducting layer <NUM> and that faces the substrate <NUM>, the solution (<FIG>) in which the second conducting layer <NUM> is filled in the entire second via has a better thermal conduction effect for the gate <NUM>.

In addition, in the fourth case, the first via and the second via may be disposed oppositely, or may not be disposed oppositely. Along the direction from the first source <NUM> to the second source <NUM>, the length L3 of the first via may be equal to the length L4 of the second via, or may be less than the length L4 of the second via.

It should be noted that, that the first via and the second via are disposed oppositely may also be understood as follows: A center of the first via and a center of the second via overlap.

In addition, the foregoing four cases are all applicable to the GaN based HEMT. For the GaAs based PHEMT, because the material of the substrate <NUM> and materials of the first epitaxial layer <NUM> and the second epitaxial layer <NUM> both include GaAs, when the substrate <NUM> is etched through the back-side lithography process, the first epitaxial layer <NUM> and the second epitaxial layer <NUM> may be incorrectly etched. Therefore, along the direction from the first source <NUM> to the second source <NUM>, the size L4 of the second via on the substrate <NUM> should be less than or equal to the length L3 of the first via.

In another embodiment, as shown in <FIG>, the step of forming the first transistor and the second transistor may be implemented through the following steps.

S210: Form a semiconductor film <NUM> on the substrate <NUM>, as shown in <FIG>.

S220: Provide a first via in the semiconductor film <NUM>, to obtain the epitaxial layer <NUM> including the first epitaxial layer <NUM> and the second epitaxial layer <NUM>, as shown in <FIG>.

In some possible implementations, a specific process of providing the first via in the semiconductor film <NUM>, to obtain the epitaxial layer <NUM> may include: forming a fifth photoresist on a side of the semiconductor film <NUM> opposite to the substrate <NUM>; and exposing the fifth photoresist, developing the fifth photoresist to obtain a fifth photoresist pattern, and etching the semiconductor film <NUM> under protection of the fifth photoresist pattern, to obtain the epitaxial layer <NUM> including the first epitaxial layer <NUM>, the second epitaxial layer <NUM>, and the first via. Before step S230, the fifth photoresist pattern may be further stripped.

In a possible implementation, the semiconductor film <NUM> may be etched along a direction from the semiconductor film <NUM> to the substrate <NUM> by using a chlorine-based gas, to obtain the first epitaxial layer <NUM> and the second epitaxial layer <NUM>. It is clear that the semiconductor film <NUM> may be etched by using another etching material. This is not limited in this embodiment of this application.

In some possible implementations, in this application, the first epitaxial layer <NUM> and the second epitaxial layer <NUM> are formed through the front-side lithography process. To be specific, lithography is performed on the semiconductor film <NUM> along a direction from a source conducting layer <NUM> to the semiconductor film <NUM>. In addition, alignment precision of the front-side lithography process may be less than <NUM>, and is far higher than alignment precision of the back-side lithography process. Therefore, when the semiconductor film <NUM> is etched, a case in which the first epitaxial layer <NUM> and the second epitaxial layer <NUM> are over-etched due to a deviation of the lithography process is avoided, so that it can be ensured that the first epitaxial layer <NUM> is in full contact with the first source <NUM>, and the second epitaxial layer <NUM> is in full contact with the second source <NUM>. When the first transistor is connected, the first epitaxial layer <NUM> may effectively send a current to the first source <NUM>, and the current is released to the ground through the first source <NUM>. When the second transistor is connected, the second epitaxial layer <NUM> may effectively send a current to the second source <NUM>, and the current is released to the ground through the second source <NUM>.

S230: Form the source conducting layer <NUM> on a side of the epitaxial layer <NUM> opposite to the substrate <NUM>, as shown in <FIG>. In other words, the first source <NUM> is formed on a side of the first epitaxial layer <NUM> opposite to the substrate <NUM>, and the second source <NUM> is formed on a side of the second epitaxial layer <NUM> opposite to the substrate <NUM>. An example in which the chip includes the first transistor and the second transistor is used. The first source <NUM> may be used as a source <NUM> of the first transistor, and the second source <NUM> may be used as a source <NUM> of the second transistor.

It should be noted herein that, because the first source <NUM> and the second source <NUM> are formed after step S220, the etching material for etching the semiconductor film <NUM> does not affect patterns of the first source <NUM> and the second source <NUM>.

In some possible implementations, a specific process of forming the source conducting layer <NUM> may include: first sequentially forming a first conductive film and a first photoresist on the side of the first epitaxial layer <NUM> opposite to the substrate <NUM> and the side of the second epitaxial layer <NUM> opposite to the substrate <NUM>; then exposing the first photoresist, developing the first photoresist to obtain a first photoresist pattern, and etching the first conductive film under protection of the first photoresist pattern, to obtain a pattern of the source conducting layer <NUM>; removing the first photoresist pattern; and performing high-temperature annealing processing on the pattern of the source conducting layer <NUM>, to obtain the first source <NUM> and the second source <NUM>. It is clear that the first source <NUM> and the second source <NUM> may alternatively be formed in another manner. This is not specially limited in this embodiment of this application.

Refer to <FIG>. In some possible implementations, when the first source <NUM> and the second source <NUM> are formed, a first drain <NUM> of the first transistor and a second drain <NUM> of the second transistor may be further formed through a same semiconductor process, to omit a process of additionally forming the first drain <NUM> and the second drain <NUM>, and save a mask. The first drain <NUM> and the second drain <NUM> are disposed on a same layer as the first source <NUM> and the second source <NUM>, the first drain <NUM> is disposed on a side of the first source <NUM> opposite to the second source <NUM>, and the second drain <NUM> is disposed on a side of the second source <NUM> opposite to the first source <NUM>.

In some possible implementations, the first source <NUM> and the second source <NUM> may have one layer, or may be stacked. Materials of the first source <NUM> and the second source <NUM> may include at least one of metals such as Ti, TiN, Al, Ni, Pt, Pd, Cr, or Au. The materials of the first source <NUM> and the second source <NUM> may alternatively include a conductive oxide material such as ITO. Considering that the first source <NUM> and the second source <NUM> may be prepared through a same semiconductor process, the first source <NUM> and the second source <NUM> may have a same quantity of layers, and each layer of the first source <NUM> and the second source <NUM> has a same material.

Refer to <FIG>. In some possible implementations, after step S230 and before step S240, the transistor preparation method may further include: forming a first gate <NUM> of the first transistor and a second gate <NUM> of the second transistor. Specifically, a specific process of forming the first gate <NUM> and the second gate <NUM> includes: sequentially forming a gate film and a second photoresist on the side of the semiconductor film <NUM> opposite to the substrate <NUM>; exposing the second photoresist, developing the second photoresist to obtain a second photoresist pattern, and etching the gate film under protection of the second photoresist pattern, to obtain patterns of the first gate <NUM> and the second gate <NUM>; removing the second photoresist pattern; and performing high-temperature annealing processing on the patterns of the first gate <NUM> and the second gate <NUM>, to obtain the first gate <NUM> and the second gate <NUM>.

In the first transistor and the second transistor that are formed in the foregoing steps S210 to S230, there may be the following several cases for a location relationship between the source conducting layer <NUM> and the epitaxial layer <NUM>.

Refer to <FIG>. An edge that is of the first source <NUM> and that faces the second source <NUM> may be flush with an edge of the first via close to the first source <NUM>, and an edge that is of the second source <NUM> and that faces the first source <NUM> may be flush with an edge of the first via close to the second source <NUM>. In other words, an edge of the first source <NUM> is flush with an edge of the first epitaxial layer <NUM> close to a side of the first via, and an edge of the second source <NUM> is flush with an edge of the second epitaxial layer <NUM> close to a side of the first via. In addition, along a direction from the first source <NUM> to the second source <NUM>, a length L1' of the first source <NUM> and a length L1" of the second source <NUM> are both equal to the length L1 of the source <NUM> in the related technology shown in <FIG>. However, in the solution of this application, the first epitaxial layer <NUM> does not need to protrude from the first source <NUM> along the direction from the first source <NUM> to the second source <NUM>, and the second epitaxial layer <NUM> does not need to protrude from the second source <NUM> along a direction from the second source <NUM> to the first source <NUM>. In other words, a length of the first epitaxial layer <NUM> protruding from the first source <NUM> is <NUM>, and a length of the second epitaxial layer <NUM> protruding from the second source <NUM> is <NUM>. Therefore, the layout areas occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

In an alternative not forming part of the invention as claimed, as shown in <FIG>, in the source conducting layer <NUM> and the epitaxial layer <NUM> that are formed through the foregoing process, the first source <NUM> protrudes from the first epitaxial layer <NUM> along a direction from the first source <NUM> to the second source <NUM>; and the second source <NUM> protrudes from the second epitaxial layer <NUM> along a direction from the second source <NUM> to the first source <NUM>. In other words, a part of the first source <NUM> and a part of the second source <NUM> further extend to the first via. In addition, in the solution of this application, the first epitaxial layer <NUM> does not need to protrude from the first source <NUM> along the direction from the first source <NUM> to the second source <NUM>, and the second epitaxial layer <NUM> does not need to protrude from the second source <NUM> along the direction from the second source <NUM> to the first source <NUM>. In other words, the length of the first epitaxial layer <NUM> protruding from the first source <NUM> is <NUM>, and the length of the second epitaxial layer <NUM> protruding from the second source <NUM> is <NUM>. Therefore, the layout areas occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

In an alternative not forming part of the invention as claimed, as shown in <FIG>, in the source conducting layer <NUM> and the epitaxial layer <NUM> that are formed through the foregoing process, the first epitaxial layer <NUM> protrudes from the first source <NUM> along the direction from the first source <NUM> to the second source <NUM>, and a length of a protruding part is L2'; and the second epitaxial layer <NUM> protrudes from the second source <NUM> along the direction from the second source <NUM> to the first source <NUM>, and a length of a protruding part is L2'. However, in this application, the epitaxial layer <NUM> is formed through the front-side lithography process, and lithography precision of the front-side lithography process is far higher than the alignment precision of the back-side lithography process. Therefore, in this application, the length L2' of the first epitaxial layer <NUM> protruding from the first source <NUM> and the length L2' of the second epitaxial layer <NUM> protruding from the second source <NUM> may be far less than the length L2 of the epitaxial layer <NUM> protruding from the source <NUM> in the related technology shown in <FIG>. Therefore, the layout areas occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

Alternatively, due to a process reason, a tolerance may exist between the actually formed first epitaxial layer <NUM> and first source <NUM>, and a tolerance may exist between the second epitaxial layer <NUM> and the second source <NUM>. Therefore, in some possible implementations, as shown in <FIG>, a surface of the first epitaxial layer <NUM> opposite to the substrate <NUM> is flush with the edge of the first source <NUM>, and a surface of the second epitaxial layer <NUM> opposite to the substrate <NUM> is flush with the edge of the second source <NUM>. However, a surface that is of the first epitaxial layer <NUM> and that faces the substrate <NUM> may protrude from the edge of the first source <NUM>, and a surface that is of the second epitaxial layer <NUM> and that faces the substrate <NUM> may protrude from the edge of the second source <NUM>.

S240: Form a first conducting layer <NUM>, as shown in <FIG>. The first conducting layer <NUM> is filled in the first via, and is in contact with the first source <NUM> and the second source <NUM> separately.

In some possible implementations, a specific location at which the first conducting layer <NUM> is disposed is not limited in this embodiment of this application, provided that the first conducting layer <NUM> is filled in the first via, and is in contact with the first source <NUM> and the second source <NUM> separately. Refer to <FIG>. Optionally, the first conducting layer <NUM> is filled in the first via, and completely covers a surface of the source conducting layer <NUM> opposite to the substrate <NUM>. Refer to <FIG>. Alternatively, the first conducting layer <NUM> is filled in the first via, is disposed on the side of the source conducting layer <NUM> opposite to the substrate <NUM>, and partially covers a surface of the source conducting layer <NUM> opposite to the substrate <NUM>. Refer to <FIG>. Alternatively, the first conducting layer <NUM> is filled only in the first via, and is in contact with a side surface that is of the first source <NUM> and that faces the second source <NUM> and a side surface that is of the second source <NUM> and that faces the first source <NUM> separately. In comparison with the two solutions shown in <FIG>, in the solution shown in <FIG>, the first source <NUM> and the second source <NUM> may be in full contact with the first conducting layer <NUM>, and a case in which the first conducting layer <NUM> is not in full contact with the first source <NUM> and/or the second source <NUM> due to a process error may be avoided.

S250: Form a second via on the substrate <NUM> along a direction from the substrate <NUM> to the epitaxial layer <NUM>, as shown in <FIG>. The second via and the first via at least partially overlap.

In some possible implementations, the substrate <NUM> may be etched through the back-side lithography process, to obtain the second via. An example in which a material of the substrate <NUM> includes SiC or Si is used. The substrate <NUM> may be etched by using a fluorine-based gas, to obtain the second via. Because the fluorine-based gas has high etching selectivity for a material of the epitaxial layer <NUM>, the material of the first conducting layer <NUM>, and a material of a second conducting layer <NUM> to be formed, the fluorine-based gas may stay on a surface of the second via. This does not affect forming of the second conducting layer <NUM> in subsequent step S150, or affect patterns of the first epitaxial layer <NUM>, the second epitaxial layer <NUM>, and the first conducting layer <NUM> that have been formed, and therefore does not affect normal contact between the second conducting layer <NUM> and the first conducting layer <NUM> subsequently.

S260: Form the second conducting layer <NUM> in the second via, as shown in <FIG>. The second conducting layer <NUM> is in contact with the first conducting layer <NUM> and is grounded. In this way, the current sequentially transmitted by the first epitaxial layer <NUM> to the first source <NUM> and the first conducting layer <NUM> and the current sequentially transmitted by the second epitaxial layer <NUM> to the second source <NUM> and the first conducting layer <NUM> may be transmitted to the second conducting layer <NUM> and released to the ground.

Refer to <FIG>. In some possible implementations, the second conducting layer <NUM> may be formed in the second via through an electroplating process. Along the direction from the substrate <NUM> to the epitaxial layer <NUM>, a thickness of the second conducting layer <NUM> is less than a depth of the second via, and the second conducting layer <NUM> extends from a side wall of the second via to a surface that is of the first conducting layer <NUM> and that faces the substrate <NUM>. Refer to <FIG>. In addition, the second conducting layer <NUM> may be filled in the entire second via.

Refer to <FIG>. In a first case, the first via and the second via are disposed oppositely, and the edge that is of the first source <NUM> and that faces the second source <NUM> is flush with an edge that is of the first epitaxial layer <NUM> and that faces the second epitaxial layer <NUM>. In other words, the edge of the first source <NUM> is flush with the edge of the first epitaxial layer <NUM> close to the side of the first via, and the edge of the second source <NUM> is flush with the edge of the second epitaxial layer <NUM> close to the side of the first via, so that the second conducting layer <NUM> is in contact with the first conducting layer <NUM>. In addition, along the direction from the first source <NUM> to the second source <NUM>, a length L3 of the first via is the same as a length L4 of the second via. In this way, the second conducting layer <NUM> to be formed may be in full contact with the first conducting layer <NUM>.

Refer to <FIG>. In a second case, the first via and the second via are disposed oppositely, so that the second conducting layer <NUM> is in contact with the first conducting layer <NUM>. In addition, along the direction from the first source <NUM> to the second source <NUM>, a length L3 of the first via is less than a length L4 of the second via. In this way the second conducting layer <NUM> to be formed may be in full contact with the first conducting layer <NUM>. In addition, the length L3 of the first via may be reduced while the length L4 of the second via remains unchanged. This further reduces the layout areas occupied by the first transistor and the second transistor.

Refer to <FIG>. In a third case, the first via and the second via are not disposed oppositely, but the second conducting layer <NUM> is still in contact with the first conducting layer <NUM>. In addition, along the direction from the first source <NUM> to the second source <NUM>, a length L3 of the first via is less than a length L4 of the second via. In this way, the length L3 of the first via may be reduced while the length L4 of the second via remains unchanged. This further reduces the layout areas occupied by the first transistor and the second transistor.

Refer to <FIG> and <FIG>. In a fourth case, the first via and the second via may be disposed oppositely, or may not be disposed oppositely, and the second conducting layer <NUM> is in contact with the first conducting layer <NUM>. In addition, orthographic projections of the source conducting layer <NUM> and the first via on the substrate <NUM> are within a range of the second via, and along the direction from the first source <NUM> to the second source <NUM>, a total length L5 from an edge of the first source <NUM> opposite to the second source <NUM> to an edge of the second source <NUM> opposite to the first source <NUM> is less than a length L4 of the second via. In this way, the second conducting layer <NUM> to be formed may be in full contact with the first conducting layer <NUM>. In addition, as shown in <FIG>, <FIG>, and <FIG>, the first gate <NUM> is disposed on the side of the epitaxial layer <NUM> opposite to the substrate <NUM>, the first gate <NUM> is located on the side of the first source <NUM> opposite to the second source <NUM>, and the second gate <NUM> is located on the side of the second source <NUM> opposite to the first source <NUM>. A material of the second conducting layer <NUM> may be a metal material, and a thermal conductivity of the metal material is higher than a thermal conductivity of the material of the substrate <NUM>. Therefore, when the first gate <NUM> and the second gate <NUM> generate heat, the heat on the first gate <NUM> may be exported to the second conducting layer <NUM> through the first epitaxial layer <NUM>, and the heat on the second gate <NUM> may be exported to the second conducting layer <NUM> through the second epitaxial layer <NUM> (where heat conduction paths are shown by straight lines with arrows in <FIG> and <FIG>), to avoid impact on performance of the transistor due to excessively high temperatures of the first gate <NUM> and the second gate <NUM>.

Refer to <FIG>. For example, the first via and the second via are disposed oppositely, and along the direction from the first source <NUM> to the second source <NUM>, both a length L' of the first source <NUM> and a length L" of the second source <NUM> are <NUM>, a length L3 of the first via is <NUM>, and a size L4 of the second via is <NUM>. In this case, the orthographic projections of the source conducting layer <NUM> and the first via on the substrate <NUM> are within the range of the second via, and the second via protrudes from the first source <NUM> and the second source <NUM> separately. In this way, heat of a gate <NUM> may be exported through the second conducting layer <NUM> filled in the second via.

In still another embodiment, an embodiment of this application further provides a chip. As shown in <FIG>, the chip includes a substrate <NUM> and a first transistor and a second transistor that are disposed on the substrate <NUM>. As shown in <FIG> and <FIG>, the first transistor includes a first epitaxial layer and a first source <NUM> that are sequentially disposed in a stacked manner, and the second transistor includes a second epitaxial layer and a second source <NUM> that are sequentially disposed in the stacked manner. The first epitaxial layer is disposed between the substrate <NUM> and the first source <NUM>, the second epitaxial layer is disposed between the substrate <NUM> and the second source <NUM>, and there is a first via between the first epitaxial layer <NUM> and the second epitaxial layer <NUM>. An edge of the first source <NUM> is flush with an edge of the first epitaxial layer <NUM> close to a side of the first via, and an edge of the second source <NUM> is flush with an edge of the second epitaxial layer <NUM> close to a side of the first via.

On this basis, the chip may further include a first conducting layer <NUM> and a second conducting layer <NUM>. The first conducting layer <NUM> is in contact with the first source <NUM> and the second source <NUM> separately, and is filled in the first via between the first epitaxial layer and the second epitaxial layer. The substrate <NUM> includes a second via, the second conducting layer <NUM> is filled in the second via, and the second conducting layer <NUM> is in contact with the first conducting layer <NUM> and is grounded.

It should be noted herein that the chip may be prepared by using the chip preparation method provided in any one of the foregoing embodiments.

In some possible implementations, the first source <NUM> and the second source <NUM> may have one layer, or may be stacked. Materials of the first source <NUM> and the second source <NUM> may include at least one of metals such as Ti, TiN, Al, Ni, Pt, Pd, Cr, or Au, or may be a conductive oxide material such as ITO. If the first source <NUM> and the second source <NUM> are prepared by using the chip preparation method in the foregoing embodiments, the first source <NUM> and the second source <NUM> may be prepared through a same semiconductor process. The first source <NUM> and the second source <NUM> may have a same quantity of layers, and each layer of the first source <NUM> and the second source <NUM> has a same material.

In some possible implementations, the first epitaxial layer and the second epitaxial layer are obtained through etching through a front-side lithography process, which is the same as the first source <NUM> and the second source <NUM>. However, alignment precision of the front-side lithography process may be less than <NUM>, and is far higher than alignment precision of a back-side lithography process. Therefore, when a semiconductor film <NUM> is etched, a case in which a source conducting layer <NUM> is incorrectly etched and the first epitaxial layer <NUM> and the second epitaxial layer <NUM> are over-etched due to a deviation of the lithography process is avoided, so that it can be ensured that the first epitaxial layer <NUM> is in full contact with the first source <NUM>, and the second epitaxial layer <NUM> is in full contact with the second source <NUM>. When the first transistor is connected, the first epitaxial layer <NUM> may effectively transmit a current to the first source <NUM>, and the current is released to the ground through the first source <NUM>. When the second transistor is connected, the second epitaxial layer <NUM> may effectively transmit a current to the second source <NUM>, and the current is released to the ground through the second source <NUM>.

In addition, in the first transistor and the second transistor that are formed by using the foregoing method, there may be the following several cases for a location relationship between the source conducting layer <NUM> and an epitaxial layer <NUM>.

As shown in <FIG>, an edge that is of the first source <NUM> and that faces the second source <NUM> may be flush with an edge of the first via close to the first source <NUM>, and an edge that is of the second source <NUM> and that faces the first source <NUM> may be flush with an edge of the first via close to the second source <NUM>. In other words, an edge of the first source <NUM> is flush with an edge of the first epitaxial layer <NUM> close to a side of the first via, and an edge of the second source <NUM> is flush with an edge of the second epitaxial layer <NUM> close to a side of the first via. In addition, along a direction from the first source <NUM> to the second source <NUM>, a length L1' of the first source <NUM> and a length L1" of the second source <NUM> are both equal to the length L1 of the source <NUM> in the related technology shown in <FIG>. However, in the solution of this application, the first epitaxial layer <NUM> does not need to protrude from the first source <NUM> along the direction from the first source <NUM> to the second source <NUM>, and the second epitaxial layer <NUM> does not need to protrude from the second source <NUM> along a direction from the second source <NUM> to the first source <NUM>. In other words, a length of the first epitaxial layer <NUM> protruding from the first source <NUM> is <NUM>, and a length of the second epitaxial layer <NUM> protruding from the second source <NUM> is <NUM>. Therefore, layout areas occupied by the first transistor and the second transistor can be reduced, and a layout area of the entire chip is further reduced.

For example, along the direction from the first source <NUM> to the second source <NUM>, both the length L1' of the first source <NUM> and the length L1" of the second source <NUM> are <NUM>. In the related technology shown in <FIG>, the length L2 of the first epitaxial layer <NUM> protruding from the first source <NUM> is <NUM>, and the length L2 of the second epitaxial layer <NUM> protruding from the second source <NUM> is <NUM>. Therefore, in comparison with the related technology, in the solution of this application, a layout of the source <NUM> occupied by one first transistor and one second transistor may be reduced by <NUM>*L2=<NUM>, and a reduction percentage is <NUM>%.

Alternatively, as shown in <FIG>, in the source conducting layer <NUM>, the first epitaxial layer <NUM>, and the second epitaxial layer <NUM> that are formed through the foregoing process, the first epitaxial layer <NUM> protrudes from the first source <NUM> along a direction from the first source <NUM> to the second source <NUM>, and a length of a protruding part is L2'; and the second epitaxial layer <NUM> protrudes from the second source <NUM> along a direction from the second source <NUM> to the first source <NUM>, and a length of a protruding part is L2'. However, in this application, the first epitaxial layer <NUM> and the second epitaxial layer <NUM> are formed through the front-side lithography process, and the alignment precision of the front-side lithography process is far higher than the alignment precision of the back-side lithography process. Therefore, in this application, the length L2' of the first epitaxial layer <NUM> protruding from the first source <NUM> and the length L2' of the second epitaxial layer <NUM> protruding from the second source <NUM> may be far less than the length L2 of the epitaxial layer <NUM> protruding from the source <NUM> in the related technology shown in <FIG>. Therefore, the layout areas occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

For example, along the direction from the first source <NUM> to the second source <NUM>, both the length L1' of the first source <NUM> and the length L1" of the second source <NUM> are <NUM>. In the related technology shown in <FIG>, both the length L2 of the first epitaxial layer <NUM> protruding from the first source <NUM> and the length L2 of the second epitaxial layer <NUM> protruding from the second source <NUM> are <NUM>. However, in this application, the length L2' of the first epitaxial layer <NUM> protruding from the first source <NUM> and the length L2' of the second epitaxial layer <NUM> protruding from the second source <NUM> are both <NUM>. Therefore, in comparison with the related technology, in the solution of this application, a layout of the source <NUM> occupied by one first transistor and one second transistor may be reduced by <NUM>*(L2-L2')=<NUM>, and a reduction percentage is <NUM>%.

In an alternative not forming part of the invention as claimed, as shown in <FIG>, in the source conducting layer <NUM> and the epitaxial layer <NUM> that are formed through the foregoing process, the first source <NUM> protrudes from the first epitaxial layer <NUM> along the direction from the first source <NUM> to the second source <NUM>; and the second source <NUM> protrudes from the second epitaxial layer <NUM> along the direction from the second source <NUM> to the first source <NUM>. In addition, in the solution of this application, the first epitaxial layer <NUM> does not need to protrude from the first source <NUM> along the direction from the first source <NUM> to the second source <NUM>, and the second epitaxial layer <NUM> does not need to protrude from the second source <NUM> along the direction from the second source <NUM> to the first source <NUM>. In other words, the length of the first epitaxial layer <NUM> protruding from the first source <NUM> is <NUM>, and the length of the second epitaxial layer <NUM> protruding from the second source <NUM> is <NUM>. Therefore, the layout areas occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

In some possible implementations, a specific location at which the first conducting layer <NUM> is disposed is not limited in this embodiment of this application, provided that the first conducting layer <NUM> is filled in the first via, and is in contact with the first source <NUM> and the second source <NUM> separately. Optionally, as shown in <FIG>, the first conducting layer <NUM> is filled in the first via, and completely covers a surface of the source conducting layer <NUM> opposite to the substrate <NUM>. Alternatively, as shown in <FIG>, the first conducting layer <NUM> is filled in the first via, is disposed on a side of the source conducting layer <NUM> opposite to the substrate <NUM>, and partially covers a surface of the source conducting layer <NUM> opposite to the substrate <NUM>. Alternatively, as shown in <FIG>, the first conducting layer <NUM> is filled only in the first via, and is in contact with a side surface that is of the first source <NUM> and that faces the second source <NUM> and a side surface that is of the second source <NUM> and that faces the first source <NUM> separately. In comparison with the two solutions shown in <FIG>, in the solution shown in <FIG>, the first source <NUM> and the second source <NUM> may be in full contact with the first conducting layer <NUM>, and a case in which the first conducting layer <NUM> is not in contact with the first source <NUM> and/or the second source <NUM> due to a process error may be avoided.

In some possible implementations, a specific location of the second via is not limited in this embodiment of this application, provided that it can be ensured that the second conducting layer <NUM> filled in the second via can be in contact with the first conducting layer <NUM>.

In a fourth case, as shown in <FIG> and <FIG>, the first via and the second via may be disposed oppositely, or may not be disposed oppositely, and the second conducting layer <NUM> is in contact with the first conducting layer <NUM>. In addition, orthographic projections of the source conducting layer <NUM> and the first via on the substrate <NUM> are within a range of the second via, and along the direction from the first source <NUM> to the second source <NUM>, a total length L5 from an edge of the first source <NUM> opposite to the second source <NUM> to an edge of the second source <NUM> opposite to the first source <NUM> is less than the length L4 of the second via. In this way, the second conducting layer <NUM> to be formed may be in full contact with the first conducting layer <NUM>. In addition, as shown in <FIG>, <FIG>, and <FIG>, a first gate <NUM> is disposed on a side of the epitaxial layer <NUM> opposite to the substrate <NUM>, the first gate <NUM> is located on a side of the first source <NUM> opposite to the second source <NUM>, and a second gate <NUM> is located on a side of the second source <NUM> opposite to the first source <NUM>. A material of the second conducting layer <NUM> may be a metal material, and a thermal conductivity of the metal material is higher than a thermal conductivity of a material of the substrate <NUM>. Therefore, when the first gate <NUM> and the second gate <NUM> generate heat, the heat on the first gate <NUM> may be exported to the second conducting layer <NUM> through the first epitaxial layer <NUM>, and the heat on the second gate <NUM> may be exported to the second conducting layer <NUM> through the second epitaxial layer <NUM> (where heat conduction paths are shown by straight lines with arrows in <FIG> and <FIG>), to avoid impact on performance of the transistor due to excessively high temperatures of the first gate <NUM> and the second gate <NUM>.

In the fourth case, in comparison with the solution (<FIG>) in which a thickness of the second conducting layer <NUM> is less than a depth of the second via and the second conducting layer <NUM> extends from a side wall of the second via to a surface that is of the first conducting layer <NUM> and that faces the substrate <NUM>, the solution (<FIG>) in which the second conducting layer <NUM> is filled in the entire second via has a better thermal conduction effect for a gate <NUM>.

In addition, in the fourth case, the first via and the second via may be disposed oppositely, or may not be disposed oppositely. In addition, along the direction from the first source <NUM> to the second source <NUM>, the length L3 of the first via may be equal to the length L4 of the second via, or may be less than the length L4 of the second via.

In addition, other explanations, descriptions, and beneficial effects of this embodiment of this application are the same as those of the foregoing two embodiments, and details are not described herein again.

Claim 1:
A chip preparation method, wherein a chip comprises a first transistor and a second transistor, and the chip preparation method comprises:
forming, on a substrate (<NUM>), an epitaxial layer (<NUM>) and a source conducting layer (<NUM>, <NUM>) that are sequentially disposed in a stacked manner, wherein the epitaxial layer comprises a first via, to form a first epitaxial layer (<NUM>) of the first transistor and a second epitaxial layer (<NUM>) of the second transistor; the source conducting layer comprises a first source (<NUM>) of the first transistor and a second source (<NUM>) of the second transistor, the first source is disposed on a side of the first epitaxial layer opposite to the substrate, and the second source is disposed on a side of the second epitaxial layer opposite to the substrate; and an edge of the first source is flush with an edge of the first epitaxial layer close to a side of the first via, and an edge of the second source is flush with an edge of the second epitaxial layer close to a side of the first via;
forming a first conducting layer (<NUM>), wherein the first conducting layer is at least filled in the first via, and is in contact with the first source and the second source separately;
forming a second via in the substrate, wherein the second via and the first via at least partially overlap; and
forming a second conducting layer (<NUM>), wherein the second conducting layer is located in the second via, and the second conducting layer is in contact with the first conducting layer and is grounded.