Patent Description:
As is known, the semiconductor materials, which have a wide band gap, in particular, an energy value Eg of the band gap higher than <NUM> eV, a low ON-state resistance (RON), a high thermal conductivity value, a high operating frequency and a high rate of saturation of the charge carriers, are ideal for producing electronic components, such as diodes or transistors, in particular for power applications. A material having the above characteristics, and designed to be used for the manufacture of electronic components, is silicon carbide (SiC). In particular, the silicon carbide, in its different polytypes (for example, 3C-SiC, <NUM>-SiC, <NUM>-SiC), is preferable to silicon, as regards the properties listed previously.

Electronic devices provided on a silicon-carbide substrate, as compared to similar devices provided on a silicon substrate, have numerous advantages, such as low output resistance in conduction, low leakage current, high operating temperature and high operating frequencies. In particular, SiC Schottky diodes have shown a higher switching performance, which render SiC electronic devices particularly favourable for high-frequency applications. Current applications impose requisites on the electrical properties and also on long-term reliability of the devices.

<FIG> shows, in side sectional view in a (triaxial) Cartesian reference system of axes X, Y, Z, a merged-PiN-Schottky (MPS) device <NUM> of a known type.

The MPS device <NUM> includes: a substrate <NUM>, made of SiC of an N type, having a first dopant concentration, provided with a surface 3a opposite to a surface 3b, and having a thickness of approximately <NUM>; a drift layer (grown in an epitaxial way) <NUM>, made of SiC of an N type, having a second dopant concentration lower than the first dopant concentration, which extends over the surface 3a of the substrate <NUM>, and has a thickness comprised between <NUM> and <NUM>; an ohmic contact region <NUM> (for example, made of nickel silicide), which extends over the surface 3b of the substrate <NUM>; a cathode metallization <NUM>, which extends over the ohmic contact region <NUM>; an anode metallization <NUM>, which extends over a top surface 2a of the drift layer <NUM>; multiple junction-barrier (JB) elements <NUM> in the drift layer <NUM>, which face the top surface 2a of the drift layer <NUM> and each include a respective implanted region <NUM>' of a P type and an ohmic contact <NUM>" made of metal material; and an edge-termination region, or protection ring, <NUM> (optional), in particular an implanted region of a P type, which surrounds the JB elements <NUM> completely.

Schottky diodes <NUM> are formed at the interface between the drift layer <NUM> and the anode metallization <NUM>. In particular, Schottky junctions (semiconductor-metal) are formed by portions of the drift layer <NUM> in direct electrical contact with respective portions of the anode metallization <NUM>.

The region of the MPS device <NUM> that includes the JB elements <NUM> and the Schottky diodes <NUM> (i.e., the region contained within the protection ring <NUM>) is an active area <NUM> of the MPS device <NUM>.

With reference to <FIG>, the steps for manufacturing the MPS device <NUM> of <FIG> envisage (<FIG>) a step of masked implantation of dopant species (for example, boron or aluminium), which have the second conductivity type (P). The implantation is illustrated by arrows <NUM> in <FIG>. For the implantation, a mask <NUM> is used, in particular a hard mask made of silicon oxide or TEOS. Implanted regions <NUM>' and the edge-termination region <NUM> are thus formed. Then, <FIG>, the mask <NUM> is removed, and a step of thermal annealing is carried out for diffusion and activation of the dopant species implanted in the step of <FIG>. The thermal annealing is, for example, carried out at a temperature higher than <NUM> (for example, between <NUM> and <NUM> and in some cases even higher).

With reference to <FIG>, further steps of ohmic contact <NUM>" formation are then carried out. With reference to <FIG>, a deposition mask <NUM> made of silicon oxide or TEOS is formed, to cover surface regions of the drift layer <NUM> other than the implanted regions <NUM>' (and the edge-termination region <NUM>, if present). In other words, the mask <NUM> has through openings 13a at the implanted regions <NUM>' (and optionally at least at one portion of the edge-termination region <NUM>). Then, <FIG>, a deposition of nickel is performed on the mask <NUM> and within the through openings 13a (the metal layer <NUM> in <FIG>). The nickel thus deposited reaches and contacts the implanted regions <NUM>' and the edge-termination region <NUM> through the through openings 13a.

With reference to <FIG>, a subsequent thermal annealing at high temperature (between <NUM> and <NUM>) for a time interval from <NUM> to <NUM>, enables formation of nickel-silicide ohmic contacts <NUM>", by chemical reaction between the nickel deposited and the silicon of the drift layer <NUM> at the through openings 13a. In fact, the deposited nickel reacts where it comes into contact with the surface material of the drift layer <NUM>, forming Ni<NUM>Si (i.e., the ohmic contact). Next, a step of removal of the metal that extends over of the mask <NUM> and removal of the mask <NUM> is carried out.

The present applicant has found that an albeit limited reaction occurs in any case between the nickel of the metal layer <NUM> and the mask <NUM>, where they are in direct contact, as illustrated by way of example in <FIG> is a top view, in the plane XY, of a portion of the device of <FIG>, in particular of the region delimited by a dashed line and identified by the reference number <NUM> in <FIG>. <FIG> regards a manufacturing step intermediate between the steps of <FIG>, i.e., with the mask <NUM> still present but with the nickel layer <NUM> removed. As may be noted from <FIG>, irregular regions, or islands, <NUM> extend over the mask <NUM> and are due to an undesired reaction between the nickel and the silicon of the mask <NUM>. The applicant has moreover noted that similar indented regions extend underneath the mask <NUM>, i.e., on the surface 2a of the drift layer <NUM>. In <FIG>, these indented regions are identified by the reference number <NUM> and are made of conductive material (including nickel). In the case where the extension in the plane XY, in particular along X, of said indented regions <NUM> were greater than the corresponding extension of the implanted regions <NUM>', there would occur a short-circuit that would lead to breakdown of the device. In detail, in the case where the undesired conductive regions were to extend in the area dedicated to the Schottky contact, an ohmic contact or quasi-ohmic contact (Schottky contact with low barrier) would be formed on an area of an N type (which from the electrical standpoint is a resistance); there would therefore be a continuous passage of current both in forward biasing and in reverse biasing, with a consequent loss of the diode characteristics.

The same problem is encountered during ohmic contact formation at body and source regions of a SiC MOSFET device.

<FIG> shows a MOSFET device <NUM> that comprises a semiconductor body <NUM>, made of semiconductor material (which includes a substrate and, optionally, one or more epitaxial layers), having a top surface 22a and a bottom surface 22b. The semiconductor body <NUM> has, for example, an N- doping. A drain region <NUM>, for example formed by implanting dopant species of an N type (N+ doping), extends at the bottom surface 22b. At the top surface 22a body regions <NUM> (with a P doping) surround the source regions <NUM> (N+ doping). The gate structures <NUM>, including a stack formed by a gate conductive layer 26a (e.g., polysilicon) and by a gate dielectric layer 26b, extend over the top surface 22a, in part overlapping the source regions <NUM>. A respective insulating, or dielectric, layer <NUM> (for example, made of silicon oxide or TEOS) covers the gate structures <NUM>.

A top metal layer <NUM> is in electrical contact with the source regions <NUM> and the body regions <NUM>, respectively, at respective surface portions <NUM> and <NUM> in order to bias, during use, the source regions <NUM> and the body regions <NUM> at a same biasing voltage.

To improve the electrical contact between the top metal layer <NUM> and the body regions <NUM>, an interface region (with P+ doping) <NUM> is formed in the body regions <NUM>, facing the top surface 22a at the surface portion <NUM>. Typically, an interface ohmic contact layer <NUM> made of silicide is formed at the interface region <NUM> to form an ohmic contact between the metal <NUM> and the body region <NUM>. Likewise, a further interface ohmic contact layer <NUM> made of silicide is formed at the surface portion <NUM> to form an ohmic contact between the metal <NUM> and the source region <NUM>.

As described with reference to <FIG>, formation of the interface ohmic contact layers <NUM> and <NUM> envisages deposition of an intermediate metal layer, in particular a nickel, using the insulating layer <NUM>, in a way similar to what has been described previously for the mask <NUM>. This intermediate metal layer therefore extends over the insulating layer <NUM> and over the surface portions <NUM> and <NUM> in contact with the interface region <NUM> and the source region <NUM>.

As described with reference to <FIG>, a subsequent thermal annealing at high temperature (between <NUM> and <NUM> for a time interval from <NUM> to <NUM>), enables formation of ohmic contacts made of nickel silicide, by chemical reaction between the deposited nickel and the silicon of the semiconductor body <NUM>, at the surface portions <NUM> and <NUM> (more in particular, at the interface region <NUM> and the source region <NUM>). Next, a step of removal of the metal that extends over of the insulating layer <NUM> is carried out. The insulating layer <NUM>, which has a function in the end device, is not removed.

However, as described previously, the applicant has noted a reaction between the nickel of the metal layer <NUM> and the insulating layer <NUM> where they are in direct contact (similarly to what is illustrated in <FIG>). Irregular regions, or islands, consequently extend over the insulating layer <NUM> and are due to an undesired reaction between the nickel and the silicon of the insulating layer <NUM>. Since these islands are electrically conductive, they are a potential problem for operation of the device <NUM>, above all in the case where their extension were such as to generate undesired short-circuits or other types of unexpected electrical connection. Insulation of the polysilicon <NUM> via covering of the oxide <NUM> is not uniform, and usually has a minimum at the highest point of the polysilicon step <NUM>. If the reaction of the nickel with the silicon of the oxide occurs in this area, there is a high risk of creating a gate-to-source short-circuit owing to formation of a bridge between the metal <NUM> and the polysilicon <NUM>.

Patent Document <CIT> discloses a JBS diode and a MOSFET.

Patent document <CIT> relates to the field of wide band gap semiconductor wafer processing, and the formation of ohmic contacts and the devices made using the same. However, the above-mentioned issues are not solved.

The aim of the present invention is to provide a SiC-based electronic device and a method for manufacturing the SiC-based electronic device, such as to overcome the drawbacks of the prior art.

According to the present invention, a SiC-based electronic device and a method for manufacturing the SiC-based electronic device are provided, as defined in the annexed claims.

For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:.

The present invention will be described with reference to two possible embodiments, specifically with reference to a merged-PiN-Schottky (MPS) device (<FIG>, <FIG>) and with reference to a MOSFET device (<FIG>); however, as will be evident from the ensuing description, the present invention applies in general to any SiC-based electronic device.

<FIG> shows, in side sectional view in a (triaxial) Cartesian reference system with axes X, Y, Z, a Merged-PiN-Schottky (MPS) device <NUM> according to one aspect of the present invention.

The MPS device <NUM> includes: a substrate <NUM>, made of SiC of an N type, having a first dopant concentration, provided with a surface 53a opposite to a surface 53b, and having a thickness comprised between <NUM> and <NUM>, more in particular between <NUM> and <NUM>, for example equal to <NUM>; a drift layer (grown in an epitaxial way) <NUM>, made of SiC of an N type, having a second dopant concentration lower than the first dopant concentration, which extends over the surface 53a of the substrate <NUM>, and has a thickness comprised between <NUM> and <NUM>; an ohmic contact region, or layer, <NUM> (for example, made of nickel silicide), which extends over the surface 53b of the substrate <NUM>; a cathode metallization <NUM>, made, for example, of Ti/NiV/Ag or Ti/NiV/Au, which extends over the ohmic contact region <NUM>; an anode metallization <NUM>, made, for example, of Ti/AlSiCu or Ni/AlSiCu, which extends over a top surface 52a of the drift layer <NUM>; a passivation layer <NUM> on the anode metallization <NUM>, for protecting the latter; multiple junction-barrier (JB) elements <NUM> in the drift layer <NUM>, which face the top surface 52a of the drift layer <NUM> and each include a respective implanted region <NUM>' of a P type and an ohmic contact <NUM>"; and an edge-termination region, or protection ring, <NUM> (optional), in particular an implanted region of a P type, which completely surrounds the junction-barrier elements <NUM>.

One or more Schottky diodes <NUM> are formed at the interface between the drift layer <NUM> and the anode metallization <NUM>, laterally to the implanted regions <NUM>'. In particular, (semiconductor-metal) Schottky junctions are formed by portions of the drift layer <NUM> in direct electrical contact with respective portions of the anode metallization <NUM>.

According to one aspect of the present invention, each ohmic contact <NUM>" is formed by one or more carbon-rich layers, including, for example, graphite layers, or graphene multi-layers. More in particular, each ohmic contact <NUM>" has, on the surface 52a, a Si/C amorphous layer, where the carbon atoms are preponderant (for example, at least twice as high, in particular from <NUM> to <NUM> times as high) as compared to the silicon atoms, following upon phase separation between the silicon atoms and the carbon atoms of the SiC substrate. Underneath this amorphous layer, each ohmic contact <NUM>" may present a layer including carbon clusters (e.g., a graphite layer), having a thickness greater than that of the amorphous layer. Such an ohmic contact <NUM>" formation is due to thermal decomposition of the silicon carbide, as a result of the manufacturing process illustrated in what follows.

According to a further aspect of the present invention, the ohmic contacts <NUM>" are self-aligned, on the surface 52a, with the implanted regions <NUM>' (i.e., in top view in the plane XY, the ohmic contacts <NUM>" have the same shape and extension as the implanted regions <NUM>'). In this case, the electrical contact between the anode metallization <NUM> and the implanted regions <NUM>' occurs exclusively through the ohmic contacts <NUM>". This feature translates into a technical advantage, in that it is possible to maximise the extension area of the ohmic contacts without the risk of short circuiting with neighbouring ohmic contacts. In fact, since each ohmic contact <NUM>" has the same shape and extension as the respective implanted region <NUM>', there is no risk of an undesirable lateral extension of said ohmic contact beyond such implanted region <NUM>'. Maximising the area of the ohmic contact allows maximising the current carried by said ohmic contact.

Moreover, according to a further aspect of the present invention, the ohmic contacts <NUM>" do not extend, along Z, beyond the surface 52a; in other words, the ohmic contacts <NUM>" have a top surface 59a that is coplanar (i.e., aligned along X) with the surface 52a and extend in depth (along Z) within the ohmic contacts <NUM>' by a depth comprised between one nanometre and some tens of nanometres (e.g., between <NUM> and <NUM>) measured starting from the surface 52a.

Each ohmic contact <NUM>" provides an electrical connection having an electrical resistivity value lower than the electrical resistivity value of the region that houses it. In particular, each ohmic contact <NUM>" has an electrical resistance lower than the electrical resistance of the respective region <NUM>' that houses it.

The steps of the ohmic contact <NUM>' formation are described in what follows, with explicit reference to the steps for manufacturing the MPS device <NUM> (<FIG>).

With reference to <FIG>, a wafer <NUM> is provided, which includes a SiC substrate <NUM> (in particular, <NUM>-SiC; however, other polytypes may be used such as, but not exclusively, <NUM>-SiC, 3C-SiC and <NUM>-SiC).

The substrate <NUM> has a first conductivity type (in this embodiment, a doping of an N type) and is provided with a front surface 53a and a back surface 53b, which are opposite to one another along the axis Z. The substrate <NUM> has a dopant concentration comprised between <NUM>·<NUM><NUM> and <NUM>·<NUM><NUM> atoms/cm<NUM>.

The front of the wafer <NUM> corresponds to the front surface 53a, and the back of the wafer <NUM> corresponds to the back surface 53b. The resistivity of the substrate <NUM> is, for example, comprised between <NUM> mΩ·cm and <NUM> mΩ·cm.

Formed on the front surface 53a of the substrate <NUM>, for example by epitaxial growth, is the drift layer <NUM>, made of silicon carbide with the first conductivity type (N) and with a dopant concentration lower than that of the substrate <NUM>, for example comprised between <NUM>·<NUM><NUM> and <NUM>·<NUM><NUM> atoms/cm<NUM>. The drift layer <NUM> is made of SiC, in particular <NUM>-SiC, but it is possible to use other SiC polytypes, such as <NUM>, <NUM>, 3C or 15R.

The drift layer <NUM> has a thickness defined between a top side 52a and a bottom side 52b (the latter being in direct contact with the front surface 53a of the substrate <NUM>).

Then, <FIG>, on the top side 52a of the drift layer <NUM> a hard mask <NUM> is formed, for example by deposition of a photoresist, or TEOS or some other material designed for the purpose. The hard mask <NUM> has a thickness of between <NUM> and <NUM> or in any case a thickness such as to shield the implantation described hereinafter with reference to the same <FIG>. The hard mask <NUM> extends in a region of the wafer <NUM> where, in subsequent steps, the active area <NUM> of the MPS device <NUM> will be formed.

In top view, in the plane XY, the hard mask <NUM> covers the regions of the top side 52a of the drift layer <NUM> that will form Schottky cells (diodes <NUM>) and leaves exposed the regions of the top side 52a of the drift layer <NUM> that will form the implanted regions <NUM>', already identified with reference to <FIG>.

Then a step of implantation of dopant species (for example, boron or aluminium) is carried out, which have the second conductivity type (here a P type), exploiting the hard mask <NUM> (the implantation is indicated in the figure by the arrows <NUM>). During the step of <FIG>, the protection ring <NUM>, if present, is also formed.

In an embodiment provided by way of example, the implantation step of <FIG> comprises one or more implantations of dopant species, which have the second conductivity type, with an implantation energy comprised between <NUM> keV and <NUM> keV and with doses of between <NUM>·<NUM><NUM> atoms/cm<NUM> and <NUM>·<NUM><NUM> atoms/cm<NUM>, to form the implanted regions <NUM>' with a dopant concentration of higher than <NUM>·<NUM><NUM> atoms/cm<NUM>. Implanted regions are thus formed having a depth, measured starting from the surface 52a, comprised between <NUM> and <NUM>.

Next, <FIG>, the mask <NUM> is removed and, <FIG>, on the surface 52a a thermal budget is generated designed to favour generation, on the implanted regions <NUM>'.

For this purpose, a laser source <NUM> is used configured to generate a beam <NUM> such as to heat the surface 52a (in particular, the implanted regions <NUM>') locally up to a temperature of approximately <NUM>-<NUM>. Given the maximum depth of the implanted regions <NUM>', a temperature of approximately <NUM> at the level of the surface 52a is sufficient to guarantee temperatures within the range identified above also at the maximum depth reached by the implanted regions <NUM>' (e.g., <NUM>).

This temperature is such as to favour generation of ohmic contacts (for example, as has been said, including graphite and/or graphene) exclusively on the implanted regions <NUM>', and not on the surface 52a that is not provided with the implanted regions <NUM>'. This effect, of a per se known type, is described for example by Maxime G. Lemaitre, "Low-temperature, site selective graphitization of SiC via ion implantation and pulsed laser annealing", APPLIED PHYSICS LETTERS <NUM>, <NUM> (<NUM>).

In one embodiment, transformation of part of the implanted regions <NUM>' into the ohmic contact <NUM>" takes place by heating the entire wafer <NUM>, appropriately moving the laser <NUM>.

In a further embodiment, transformation of the surface portions of the implanted regions <NUM>' into the ohmic contact <NUM>" is obtained by heating the useful surface of the wafer <NUM>. By "useful surface" is here meant the portion of surface of the drift layer <NUM> that includes the implanted regions <NUM>', for example delimited externally by the edge-termination region <NUM>. The useful surface might not correspond to the entire surface of the wafer <NUM> (for example, excluding possible portions of the wafer <NUM> that are lateral with respect to the active area <NUM>, which are not of interest during use of the MPS device <NUM> in so far as they do not take part in transport of electric charge).

In a further embodiment, it is possible to arrange over the surface 52a (in contact with the surface 52a or at a distance therefrom) a mask having regions transparent to the beam <NUM> (i.e., the beam <NUM> traverses them) and regions opaque to the beam <NUM> (i.e., the beam <NUM> does not traverse them, or traverses them in attenuated form such as not to heat significantly the portions of the wafer <NUM> that extend underneath). The transparent regions of the mask are aligned with the implanted regions <NUM>', to enable the ohmic contact <NUM>" formation.

Optionally, and independent of the embodiment used, the implanted regions <NUM>' (in particular, the dopants are activated, to obtain a concentration of dopant species comprised between approximately <NUM>·<NUM><NUM> atoms/cm<NUM> and <NUM>·<NUM><NUM> atoms/cm<NUM>) are simultaneously formed and the ohmic contacts <NUM>" for each implanted region.

Furthermore, since the ohmic contact is formed exclusively on the implanted regions <NUM>', even in the absence of a mask there is a self-alignment between the implanted regions <NUM>' and the respective ohmic contact <NUM>".

At the implanted regions <NUM>', the localized and superficial increase in temperature causes the ohmic contact <NUM>" formation; laterally to the implanted regions <NUM>', no such effect is noted. The ohmic contact <NUM>" formation takes place at temperatures comprised between <NUM> and <NUM>. According to the present invention, these temperatures are reached at a surface portion (some nanometres, e.g., <NUM>-<NUM>) of the implanted regions <NUM>'. For greater depths, the temperature drops to values such as no longer to cause the ohmic contact <NUM>" formation, which is thus self-limited. Therefore, the ohmic contact <NUM>" does not extend throughout the thickness of the respective implanted region, but exclusively at a superficial level thereof.

The laser <NUM> is, for example, a UV excimer laser. Other types of lasers may be used, among which lasers with wavelengths in the region of the visible.

The parameters of configuration and actuation of the laser <NUM>, optimized for achieving the purpose of the present invention, are the following:.

The area of the spot of the beam <NUM> at the level of the surface 52a is, for example, comprised between <NUM> and <NUM><NUM>.

To cover the entire wafer <NUM>, or the sub-region of the wafer <NUM> to be heated, one or more scans of the laser <NUM> are thus performed in the plane XY (e.g., a plurality of scans parallel to one another and to the axis X and/or axis Y).

The applicant has, however, found that, with the parameters identified previously, the desired electrical behaviour is obtained for the MPS device <NUM>. <FIG> illustrates, in this regard, experimental data of variation of the conduction current as a function of the voltage applied between anode and cathode of the MPS device <NUM>. The curve S1 relates to electrical measurements at the PiN diode prior to the laser treatment, whereas the curve S2 relates to electrical measurements at the PiN diode after laser treatment, and therefore with the ohmic contact formed. The trends of the curves S1 and S2 confirm the expected behaviour.

<FIG> shows a MOSFET device <NUM> according to an aspect of the present invention.

Technical elements and characteristics of the MOSFET device <NUM> that are common to the MOSFET device <NUM> of <FIG> are illustrated with the same reference numbers and are not described any further.

Unlike the MOSFET device <NUM>, the MOSFET device <NUM> has an ohmic contact <NUM> at the interface region <NUM>, between the metal <NUM> and the body region <NUM>. The MOSFET device <NUM> moreover has a further ohmic contact <NUM> at the surface portion <NUM>, between the metal <NUM> and the source region <NUM>.

According to one aspect of the present invention, both the ohmic contact <NUM> and the ohmic contact <NUM> are formed by one or more carbon-rich layers, which, for example, include graphite layers, or graphene multi-layers. More in particular, each ohmic contact <NUM>, <NUM> has, on the surface 52a, a Si/C amorphous layer in which the carbon atoms are preponderant (for example, at least twice as high, in particular from <NUM> to <NUM> times as high) as compared to that of the silicon atoms, following upon phase separation between the silicon atoms and the carbon atoms of the SiC substrate. Underneath this amorphous layer, each ohmic contact <NUM>, <NUM> can have a layer including carbon clusters (e.g., a graphite layer), having a thickness greater than that of the amorphous layer. Such an ohmic contact <NUM>" formation is due to thermal decomposition of silicon carbide, as a result of the manufacturing process illustrated in what follows.

According to a further aspect of the present invention, the ohmic contact <NUM> and the ohmic contact <NUM> are self-aligned, on the surface 22a, with the interface region <NUM> and with the source region <NUM> (i.e., in top view in the plane XY, the ohmic contacts <NUM>, <NUM> have the same shape and extension as the interface region <NUM> and the source region <NUM>, respectively).

The ohmic contacts <NUM> and <NUM> extend in depth (along Z) within the semiconductor body <NUM> by a depth comprised between one nanometre and some tens of nanometres (e.g., between <NUM> and <NUM>), measured starting from the surface 22a.

Each ohmic contact <NUM>, <NUM> provides an electrical connection having an electrical resistivity value lower than the electrical resistivity value of the region that houses it. In particular, each ohmic contact <NUM>, <NUM> has an electrical resistance lower than the electrical resistance of the respective region <NUM>, <NUM> that houses it.

The steps of formation of the ohmic contacts <NUM> and <NUM> are described in what follows with reference to <FIG>.

In particular, <FIG> shows a wafer <NUM>, which includes the MOSFET device <NUM> in an intermediate manufacturing stage, in which the body region <NUM>, the interface region <NUM>, the source region <NUM>, the gate structures <NUM> and the insulating layer <NUM> have been formed (in a per se known manner).

In order to form the ohmic contacts <NUM>, <NUM>, a thermal budget is generated on the surface 22a designed to favour generation, at the interface <NUM> and the source <NUM> regions, of the respective ohmic contact <NUM>, <NUM>.

For this purpose, a laser source <NUM> is used configured to generate a beam <NUM> such as to heat the surface 22a locally (in particular, the interface <NUM> and the source <NUM> regions) up to a temperature of approximately <NUM>-<NUM>.

A temperature in the aforementioned range is such as to favour generation of the carbon-rich regions and graphite/graphene layers exclusively at the interface <NUM> and the source <NUM> regions, and not at the surface region 22a, where the interface <NUM> and the source <NUM> regions do not extend.

In one embodiment, transformation of the interface region <NUM> and source region <NUM> into the respective ohmic contact is obtained by heating the entire wafer <NUM>, moving the laser <NUM> appropriately.

In a further embodiment, transformation of the interface <NUM> and source <NUM> regions into the respective ohmic contact takes place by selectively heating the interface <NUM> and source <NUM> regions, by appropriately directing the beam <NUM>.

In a further embodiment, it is possible to arrange on the wafer <NUM> a mask (not illustrated in the figures) having regions transparent to the beam <NUM> (i.e., the beam <NUM> traverses them) and regions opaque to the beam <NUM> (i.e., the beam <NUM> does not traverse them, or traverses them in attenuated form such as not to significantly heat the masked portions of the wafer <NUM>). The transparent regions of the mask are aligned with the interface <NUM> and source <NUM> regions in order to enable the formation of the respective ohmic contact and protect portions of the wafer <NUM> in which an ohmic contact formation via the laser <NUM> is not envisaged.

The applicant has found that the ohmic contact <NUM> formation at the source region <NUM> (with N+ doping) requires an energy of the beam <NUM> different from the energy required for the ohmic contact <NUM> formation at the interface region <NUM> (with P+ doping).

Optimization of the ohmic properties of the contact <NUM> at the source region <NUM> (with N+ doping) could require an energy of the beam <NUM> different from the energy required for optimization of the ohmic properties of the contact <NUM> at the interface region <NUM> (with P+ doping). For this purpose, it is possible to regulate operating parameters of the laser <NUM> for generating a respective beam <NUM> at the interface region <NUM> and at the source region <NUM>, each beam being designed for generating the respective layer with ohmic properties.

In any case, the applicant has found that the ohmic contact <NUM> formation at the source region <NUM> (with N+ doping) and of the ohmic contact <NUM> at the interface region <NUM> (with P+ doping) can occur given the same energy of the beam.

In detail, at the source <NUM> and interface <NUM> regions, the parameters of configuration and actuation of the laser <NUM>, optimized for achieving the purpose of the present invention, are the following:.

The area of the spot of the beam <NUM> at the level of the surface 22a is, for example, comprised between <NUM> and <NUM><NUM>.

To cover the entire wafer <NUM> or the sub-region of the wafer <NUM> to be heated, one or more scans of the laser <NUM> are therefore performed in the plane XY (e.g., a plurality of scans parallel to one another and to the axis X and/or axis Y).

Alternatively, <FIG>, it is possible to arrange a mask <NUM> on the wafer <NUM>, said mask being provided with respective windows 97a, 97b at (i.e., vertically aligned with) the interface region <NUM> and the source region <NUM>. The remaining portions 97c of the mask <NUM> are completely opaque to the beam <NUM>, i.e., they are not traversed by the beam <NUM> (or in any case they are traversed in a non-significant way and such as not to generate on the underlying structures of the wafer <NUM> a heating such as to cause damage or undesired phenomena of some other type).

The window 97a at the interface region <NUM> is provided with a filter <NUM> designed to modify characteristics of the beam <NUM>, for example in the case where it were expedient to modify some characteristics of the beam that impinges on the interface region <NUM>. Instead, the filter <NUM> is not present. The window 97b at the source region <NUM> does not have any filter; i.e., it is transparent to the beam <NUM>, which traverses it in a substantially unaltered form as regards its characteristics.

In the following of the present invention, it is considered that both of the windows 97a and 97b are without a filter, and that the mask <NUM> will have the function of protecting (via the opaque portions 97c) regions that are not to be heated with the beam <NUM>.

In particular, in this embodiment, the beam <NUM> is generated by controlling the laser <NUM> in the following way:.

To cover the entire wafer <NUM>, or the sub-region of the wafer <NUM> to be heated, one or more scans of the laser <NUM> are therefore performed in the plane XY (e.g., a plurality of scans parallel to one another and to the axis X and/or axis Y).

The beam <NUM> thus generated is directed towards the source region <NUM> (N+), through the window 97b, and towards the interface region <NUM> (P+), through the window 97a.

It is evident that, according to a further embodiment, it is possible to introduce a filter also at the window 97b, and generate the beam <NUM> in an appropriate way (i.e., such that the filtered beam is designed to generate the ohmic contact at the source region <NUM>).

Since the ohmic contact is formed exclusively at the P and N implanted regions, there is a self-alignment between the interface <NUM>/source <NUM> regions and the respective ohmic contact <NUM>/<NUM>.

Transformation of the SiC into carbon-rich layers and/or graphite and/or graphene layers occurs on the basis of the technical considerations already described previously, with reference to manufacturing of the MPS device.

The laser <NUM> is, for example, a UV excimer laser. Other types of laser may be used, among which lasers having wavelengths in the region of the visible.

From an examination of the characteristics of the invention provided according to the present disclosure the advantages that it affords are evident.

In particular, according to the present invention, it is possible, with a single process, to provide ohmic contacts on P+ or N+ regions, without any deposition of metal layers, thus overcoming the disadvantages regarding the known art identified and described previously.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.

For example, the conductivity types mentioned above (N-type and P-type) may be switched to form a corresponding electronic device with opposite conductivity types as those described. In particular, the present invention applies to a P-channel device, in particular for forming ohmic contacts in, and activating dopant species of, regions having an N-type conductivity implanted in a substrate or semiconductor body having a P-type conductivity. In this case, the substrate <NUM> is of P type and the implanted region <NUM>' is of N type.

Claim 1:
A method for manufacturing an electronic device (<NUM>; <NUM>), comprising the steps of:
- forming, at a front side (52a; 22a) of a solid body (<NUM>; <NUM>) of Silicon Carbide, SiC, having dopants of a first conductivity type, an implanted region (<NUM>'; <NUM>) by implanting dopants of a second conductivity type, the first conductivity type being different than the second conductivity type, the implanted region (<NUM>'; <NUM>) extending in the solid body (<NUM>; <NUM>) from the front side toward a bottom side, the implanted region (<NUM>'; <NUM>) having a top surface that is coplanar with at least a surface portion of said front side of the solid body; and
- generating a first laser beam (<NUM>; <NUM>) directed towards said implanted region (<NUM>'; <NUM>) in order to heat the implanted region (<NUM>'; <NUM>) to temperatures in the range <NUM> - <NUM> thereby forming a first carbon-rich electrical-contact region (<NUM>"; <NUM>) at said implanted region (<NUM>'; <NUM>).