Patent Description:
Bipolar CMOS DMOS (BCD) process technology enables incorporation of analog components, digital components and high voltage (HV) devices into a single chip or integrated circuit (IC). These components are designed such that they do not interfere with (for example, latch up with) adjacent components on a substrate. Hence, there is a need to properly isolate adjacent components from each other. A variety of different isolation schemes exist such as junction-based isolation or trench-based isolation in a bulk wafer or trench-based isolation in a SOI (Silicon -on-insulator) wafer.

A typical design of a trench-based isolation involves a heavily doped buried layer (BL) that intersects a trench oxide where the trench is partially or fully filled with oxide.

Documents <CIT>, <CIT>, <CIT> and <CIT> disclose semiconductor devices comprising buried layers to create an isolation structure.

Aspects of the present disclosure are set out in the accompanying independent and dependent claims.

According to a first aspect of the present disclosure, there is provided a semiconductor device comprising a substrate having a first conductivity type, the substrate having a top surface and a bottom surface. A first buried layer is disposed in the substrate at a first depth from the top surface, wherein the first buried layer has a second conductivity type and a first doping concentration. A second buried layer is adjacent to and surrounds the first buried layer at the first depth, wherein the second buried layer has the second conductivity type and a second doping concentration, wherein the second doping concentration is less than the first doping concentration. An isolation trench is disposed in the substrate and surrounds the second buried layer, wherein the isolation trench extends from the top surface of the substrate to a second depth, the second depth exceeding the first depth.

It will be appreciated that the second conductivity type is different to the first conductivity type.

The second buried layer is perimetric to the first buried layer. The isolation trench is perimetric to the second buried layer.

Optionally, the first doping concentration may be of the order of <NUM><NUM>/cm<NUM> or <NUM><NUM>/cm<NUM>. Optionally, the first doping concentration may be between 5x10<NUM>/cm<NUM> and 5x10<NUM>/cm<NUM>.

In some embodiments the first buried layer may comprise at least two doping species.

Optionally, the second doping concentration is of the order of <NUM><NUM>/cm<NUM> or <NUM><NUM>/cm<NUM>. Optionally, the second doping concentration may be between 5x10<NUM>/cm<NUM> and 5x10<NUM>/cm<NUM>.

It will be appreciated that the doping concentrations referred to in the present disclosure may be the peak doping concentration for the respective semiconductor layer.

Optionally, the substrate comprises a base substrate and at least one epitaxial layer disposed over the base substrate. The at least one epitaxial layer may have the first conductivity type. The isolation trench and the first and second buried layers may be disposed in the at least one epitaxial layer. Thus, the top surface of the substrate may be the top surface of the at least one epitaxial layer. The bottom surface of the substrate may be a bottom surface of the base substrate. It will be appreciated that various multi-layer substrates could be used.

In some embodiments, the semiconductor device further comprises a first well region disposed between the top surface of the substrate and the first buried layer. The first well region may have the second conductivity type. The first well region may be bounded by the isolation trench.

In some embodiments, the semiconductor device further comprises an active component provided in the first well region. Optionally, the active component may be a transistor, or a diode, but is not limited to these examples.

Optionally, a second well region may be disposed between the first well region and the isolation trench. The second well region may have the second conductivity type and may surround the first well region.

The second well region may be perimetric to the first well region. The isolation trench may be perimetric to the second well region.

Optionally, the second well region may have a doping concentration that is the same as, or of the same order as, the second doping concentration.

In some embodiments, the second well region may have a doping concentration that is of the order of <NUM><NUM>/cm<NUM>.

In some embodiments, the first well region may have a doping concentration that is of the order of <NUM><NUM>/cm<NUM> or <NUM><NUM>/cm<NUM>. Optionally, the first well region may have a doping concentration that is between the first doping concentration and the second doping concentration.

Optionally, a width of the second buried layer is less than a width of the first buried layer. The width of the second buried layer is the distance between the isolation trench and the first buried layer.

Optionally, a width of the second buried layer between the isolation trench and the first buried layer is at least <NUM>. Optionally, a width of the second buried layer between the isolation trench and the first buried layer is between <NUM> and <NUM>.

Optionally, the isolation trench contains a polysilicon material.

Optionally, the first and second buried layers have the same height.

Optionally, the second buried layer is configured such that a breakdown region is spaced from the isolation trench. The breakdown region is defined as a region or location which is susceptible to electrical breakdown due to a high electric field strength. This may also be referred to as an electrical hotspot.

Optionally, the second buried layer is configured such that the breakdown region is located proximate a junction between the first buried layer and the second buried layer. Optionally, the second buried layer is configured such that the breakdown region is located proximate an edge of the first buried layer.

Thus, the breakdown region may be spaced from the trench by a distance equal to the width of the second buried layer.

According to a second aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising providing a substrate having a first conductivity type, the substrate having a top surface and a bottom surface, providing a first buried layer in the substrate at a first depth from the top surface, wherein the first buried layer has a second conductivity type and a first doping concentration, providing a second buried layer adjacent and surrounding the first buried layer at the first depth, wherein the second buried layer has the second conductivity type and a second doping concentration, wherein the second doping concentration is less than the first doping concentration, and providing an isolation trench in the substrate surrounding the second buried layer, wherein the isolation trench extends from the top surface of the substrate to a second depth, the second depth exceeding the first depth.

It will be appreciated that the method may comprise method steps for manufacturing a semiconductor device according to any embodiment or example of the first aspect of the disclosure.

Optionally, the first and second buried layers may be inserted or implanted in a single step.

Optionally, the method may include providing a first well region between the top surface of the substrate and the first buried layer. The first well region may have the second conductivity type.

Optionally, the method may include providing a second well region between the isolation trench and the first well region, such that the second well region surrounds or is perimetric to the first well region. The second well region may have the second conductivity type. The second well region may have a lower doping concentration than the first well region.

Optionally, the first and second well regions may be inserted or implanted in a single step. Optionally, the first and second well regions may be inserted or implanted before the isolation trench is provided.

The method may include providing a polysilicon material in the isolation trench.

The method may comprise providing a base substrate, the base substrate having the first conductivity type. The method may comprise providing a first epitaxial layer over the base substrate, the first epitaxial layer having the first conductivity type.

The method may include implanting the first and second buried layers into the first epitaxial layer. A second epitaxial layer may be grown over the first epitaxial layer and the first and second buried layers.

Illustrative embodiments of this disclosure will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which:.

Embodiments of this disclosure are described in the following with reference to the accompanying drawings. It will be appreciated that the drawings are schematic illustrations and are not drawn to scale.

<FIG> is a cross-sectional view of a prior art semiconductor device. The semiconductor device comprises a substrate <NUM> formed of a base substrate <NUM> and at least one epitaxial layer <NUM> formed on top of the base substrate <NUM>. The substrate <NUM> has a bottom surface <NUM> and a top surface <NUM>. It will be appreciated that in some embodiments the substrate <NUM> may be a single layer, or the substrate may have a plurality of different layers.

A heavily doped buried layer <NUM> is disposed in the substrate <NUM> at a depth from the top surface <NUM> of the substrate. The buried layer <NUM> is surrounded by an isolation trench <NUM>. The trench <NUM> is usually filled with an oxide material. A well region <NUM> is disposed between the top surface <NUM> and the buried layer <NUM>. The well region <NUM> is bounded by (or surrounded by) the trench <NUM>. At least one electrical contact <NUM> is electrically connected to the well region <NUM> and the buried layer <NUM>. The electrical contact(s) <NUM> control the potential of the buried layer <NUM>.

In use (but not shown in <FIG>) an active component is disposed in the well region <NUM>. The isolation trench <NUM> and buried layer <NUM> are provided to attempt to electrically isolate the active component from neighbouring components on the substrate <NUM>, such that adjacent active components do not interfere with each other. The trench <NUM> provides a physical barrier, due to the oxide filling, and the buried layer <NUM>, provides an electrical barrier.

However, it has been found that the semiconductor device shown in <FIG> is susceptible to breakdown voltage shift over time. Avalanche breakdown occurs when an electric field generated by a voltage in a semiconducting region exceeds a critical value, such that the object becomes a conductor. This is because the electric field becomes strong enough generate a lot of electron/hole pairs that create a lot of current quickly. The breakdown voltage of an object is the voltage at which this breakdown occurs. The breakdown voltage depends on a variety of factors including the composition and shape of the object.

Accordingly, electrical breakdown usually initiates at the region that has the highest electric field. In this disclosure this region is called the breakdown region, or hotspot region, and is represented by a star in <FIG>.

If there is a shift in the breakdown voltage over time, this means that the voltage at which electrical breakdown occurs is not stable and changes over time. If the breakdown voltage shifts to lower voltages over time, then this can result in the isolation structure failing when the semiconductor device is subjected to high voltages.

It has been found that the breakdown voltage of the prior art in <FIG> shifts to lower voltages over time. This is because the breakdown region (i.e., the high electric field region at which breakdown occurs) is located proximate to the trench <NUM>, as shown by the stars. This causes the breakdown voltage to change over time due to hot electron or hot hole injection towards the trench oxide causing Ox-Si interface charging, or possibly due to hot electron or hot hole injection landing in the conductive polysilicon region of the trench.

Another prior art example is shown in <FIG>. Features which are common between <FIG> have been given the same reference numeral. In <FIG>, there is a second isolation trench <NUM> provided, which is spaced from and surrounds the first isolation trench <NUM>. Both trenches <NUM>, <NUM> intersect the buried layer <NUM> and at least a portion of the well region <NUM>. The trenches <NUM>, <NUM> may be filled with an oxide, or polysilicon material. Due to this dual trench structure, the high electric field region (or breakdown region) is located proximate the inner edge of the first trench <NUM>, as shown by the stars in <FIG>. Again, it has been found that the semiconductor device shown in <FIG> is susceptible to breakdown voltage (BV) shift over time. As stated above, this BV shift can be caused due to hot electron or hot hole injection towards the trench oxide causing Ox-Si interface charging, or possibly due to hot electron or hot hole injection landing in the conductive polysilicon region of the trench.

A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown in <FIG>.

The semiconductor device comprises a substrate <NUM> formed of a base substrate <NUM> and at least one epitaxial layer <NUM> formed on top of the base substrate <NUM>. The substrate <NUM> has a bottom surface <NUM> and a top surface <NUM>. It will be appreciated that in some embodiments the substrate <NUM> may be a single layer, or the substrate may have a plurality of different layers. The substrate <NUM> has a first conductivity type, for example positive or p conductivity.

A first buried layer <NUM> is disposed in the substrate <NUM> at a depth from the top surface <NUM> of the substrate. The first buried layer <NUM> has a second conductivity type, which is different to the conductivity type of the substrate <NUM>. The first buried layer <NUM> is doped at a first doping concentration.

A second buried layer <NUM> is disposed in the substate <NUM> at the same depth as the first buried layer <NUM>. The second buried layer <NUM> is adjacent to and surrounds the first buried layer <NUM>. Thus, the second buried layer <NUM> is perimetric to the first buried layer <NUM>.

The second buried layer <NUM> has a second conductivity type (opposite to the substrate <NUM> and the same as the first buried layer <NUM>). The second buried layer <NUM> is doped at a second doping concentration. The second doping concentration is less than the first doping concentration. Thus, the second buried layer <NUM> can be referred to as a light buried layer.

An isolation trench <NUM> is provided that extends to a depth that exceeds the first depth of the first and second buried layers <NUM>, <NUM>. In some embodiments the isolation trench <NUM> may extend from the top surface <NUM> of the substrate to the base substate <NUM>, or to the bottom surface of the substrate <NUM>. The trench <NUM> comprises a polysilicon material. The isolation trench <NUM> enclosed or is perimetric to the second buried layer <NUM>.

A first well region <NUM> is disposed between the top surface <NUM> and the buried layer <NUM>. The first well region <NUM> has the second conductivity type, the same as the first and second buried layers. At least one electrical contact <NUM> is electrically connected to the first well region <NUM>.

A second well region <NUM> is provided between the isolation trench <NUM> and the first well region <NUM>. The second well region <NUM> is therefore perimetric to the first well region, as it surrounds the perimeter of the first well region <NUM>. The isolation trench <NUM> is perimetric to the second well region <NUM>.

The second well region <NUM> has the second conductivity type and a doping concentration that is less than the doping concentration of the first well region <NUM>. In some embodiments, the second well region <NUM> may have a doping concentration that is the same as, or of the same order as, the second buried layer <NUM>.

In use (see <FIG>) an active component is disposed in the first well region <NUM>. The combination of the first well region <NUM>, first buried layer <NUM> and the active component can be referred to as a high voltage (HV) tub. The structure shown in <FIG> is configured to electrically isolate the active component from neighbouring components on the substrate <NUM>. Optionally, the substrate <NUM> may comprise a plurality of structures as shown in <FIG> (i.e., a plurality of isolation trenches <NUM>, first and second buried layers <NUM>, <NUM> and first and second well regions <NUM>, <NUM>), wherein each first well region <NUM> is configured to contain a respective active component. For simplicity, only a single isolation structure has been shown in <FIG>.

The second buried layer <NUM> acts as a spacer between the first buried layer <NUM> and the isolation trench <NUM>. In practice, this changes the location of the breakdown region, which is represented by stars in <FIG>. As shown, the provision of the second buried layer <NUM> having a doping concentration that is less than the doping concentration of the first buried layer <NUM> spaces or translates the breakdown region away from the isolation trench <NUM> by a distance equal to the width of the second buried layer <NUM>. In some embodiments, the second buried layer <NUM> may have a width of at least <NUM>. The second buried layer <NUM> may have a width equal to between <NUM> and <NUM>.

By moving the breakdown region away from the isolation trench <NUM> this reduces, or eliminates, breakdown voltage shift over time, even if the semiconductor device is exposed to high voltage and/or high temperatures for a prolonged period of time. In one particular embodiment, the breakdown voltage of the semiconductor device was tested, and the semiconductor device was then constantly stressed at 80V and <NUM> for around <NUM> week. The breakdown voltage was then retested and was found to be only <NUM> V different to the initial breakdown voltage. Thus, in the semiconductor device shown in <FIG>, the breakdown voltage remains more stable or constant over time compared to the prior art devices.

<FIG> shows a top view of the semiconductor device in <FIG> according to an embodiment of the present disclosure.

As shown, an active component <NUM> is positioned within the first well region <NUM>. Although the active component <NUM> is shown as positioned centrally within the first well region <NUM> in <FIG>, it will be appreciated that this is not limiting. The active component <NUM> may, for example, be a transistor or a diode, although any type of active component may be provided.

A plurality of electrical contacts <NUM> are provided on the top surface of the substrate in electrical contact with the first well region <NUM>. The electrical contacts <NUM> control the potential of the first buried layer <NUM>.

The second well region <NUM> surrounds (or is perimetric to) the first well region <NUM>. The isolation trench <NUM> surrounds (or is perimetric to) the second well region <NUM>. The at least one epitaxial layer <NUM> surrounds the isolation trench <NUM>. In some embodiments, the at least one epitaxial layer <NUM> may be replaced by a single substrate <NUM>. In <FIG>, the first buried layer <NUM> is not visible as this is provided underneath the first well region. Similarly, the second buried layer <NUM> is not visible as this is provided underneath the second well region <NUM>.

It will be appreciated that <FIG> is a schematic representation of a plan view of the semiconductor device, and the respective layers may have different shapes and relative sizes to those shown.

<FIG> is a graph showing how doping concentration may vary with depth in the semiconductor along line A in <FIG>. Accordingly, the y axis is doping concentration per cm<NUM>, and the x axis is depth from the top surface of the substrate.

Line <NUM> in <FIG> represents the second well region <NUM>, which in this embodiment comprises a single doping species. In this embodiment the doping species is phosphorous, although other elements may be used. As the second well region <NUM> is the closest to the top surface of the substrate, this layer has the highest doping concentration towards x=<NUM> along the cross-sectional line A (see <FIG>). In this embodiment the peak doping concentration for the second well region is off the order of <NUM> x10<NUM> /cm<NUM>.

Line <NUM> in <FIG> represents the second buried layer <NUM>. As is shown in <FIG>, along cross-sectional line A the second buried layer <NUM> is positioned below (at a lower depth to) the second well region <NUM>. In this embodiment, the second buried layer <NUM> comprises phosphorous, although other doping elements may be used. The peak doping concentration for the second buried layer <NUM> is between <NUM> x10<NUM> /cm<NUM> and <NUM> x10<NUM> /cm<NUM>. As shown in <FIG>, the peak doping concentration for the second buried layer <NUM> in this embodiment is close to <NUM> x10<NUM> /cm<NUM>.

<FIG> shows how doping concentration may vary with depth in the semiconductor along line B in <FIG>. Accordingly, the y axis is doping concentration per cm<NUM>, and the x axis is depth from the top surface of the substrate. Optionally, the x axis may be from <NUM> to <NUM> in both <FIG> and <FIG>, but it will be appreciated that this scale is not limiting and may vary depending on the particular application.

Line <NUM> in <FIG> represents the first well region <NUM>, which in this embodiment comprises a single doping species, wherein the single doping species is phosphorous, although other elements may be used. As the first well region <NUM> is the closest to the top surface of the substrate, this layer has the highest doping concentration towards x=<NUM> along the cross-sectional line B (see <FIG>). In this embodiment the peak doping concentration for the first well region is between <NUM> x10<NUM> /cm<NUM> and <NUM> x10<NUM> /cm<NUM> (for example, around <NUM> x10<NUM> /cm<NUM>). Accordingly, a comparison of <FIG> and <FIG> shows that the first well region <NUM> has a higher peak doping concentration than the second well region <NUM>.

In this embodiment, the first buried layer <NUM> is comprises two doping species, which are represented by lines <NUM>-<NUM> and <NUM>-<NUM>. In this embodiment, line <NUM>-<NUM> represents the buried layer doped with antimony, and line <NUM>-<NUM> represents the buried layer doped with phosphorous. In other embodiments, different doping elements may be used and optionally only a single doping species may be used.

The antimony doped buried layer <NUM>-<NUM> has a peak doping concentration of the order of <NUM> x10<NUM> /cm<NUM>, as shown in <FIG>. The phosphorous doped buried layer <NUM>-<NUM> has a lower peak doping concentration of the order of <NUM> x10<NUM> /cm<NUM>.

A comparison of <FIG> and <FIG> shows that the peak doping concentration of the second buried layer <NUM> is configured to be at a slightly lower depth in the substrate than the peak doping concentration of the antimony doped buried layer <NUM>-<NUM>. This is to mitigate the lateral electric field strength at the edge of first buried layer, which has been found to improve the stability of the breakdown voltage.

It will be appreciated that the various semiconductor layers are not limited to the doping elements or concentrations described above or shown in <FIG> or <FIG>.

<FIG> is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

In step <NUM> the method comprises providing a substrate <NUM>. The substrate <NUM> may have a single layer, or multiple layers. The substrate <NUM> may have a first conductivity type, such as but not limited to p-type or positive type conductivity.

In step <NUM> the method comprises providing a first buried layer <NUM> at a first depth within the substrate <NUM>. The first buried layer <NUM> may have a second conductivity type, such as but not limited to n-type or negative type conductivity. The first buried layer <NUM> has a first doping concentration.

In step <NUM> the method comprises providing a second buried layer <NUM> at the first depth within the substrate <NUM>. The second buried layer <NUM> may have the second conductivity type, same as the first buried layer <NUM>. The second buried layer <NUM> has a second doping concentration which is less than the first doping concentration of the first buried layer <NUM>. In some embodiments, the first doping concentration may be of the order of <NUM> times higher than the second doping concentration.

It will be appreciated that steps <NUM> and <NUM> may be combined in a single step.

Optionally, the substrate <NUM> may be provided as a base substrate with an epitaxial layer on top. The first and second buried layers <NUM>, <NUM> may be implanted in the epitaxial layer. Between steps <NUM> and <NUM> there may be an intermediate step (not shown) of growing a second epitaxial layer on top of the first epitaxial layer and the first and second buried layers <NUM>, <NUM>.

In step <NUM> the method comprises providing a first well region <NUM> between the first buried layer <NUM> and a top surface of the substrate <NUM> (e.g., the top surface of the second epitaxial layer). Thus, the first well region <NUM> is stacked on top of the first buried layer <NUM> when viewed from above the substrate.

In step <NUM> a second well region <NUM> is provided perimetric to (or surrounding) the first well region. The second well region <NUM> may be stacked on top of the second buried layer, such that it is positioned between the second buried layer <NUM> and the top surface of the substrate.

The first and second well regions may have the second conductivity type, the same as the first and second buried layers. The doping concentration of both the first and second well regions may be less than the first doping concentration of the first buried layer.

At step <NUM> an isolation trench <NUM> is inserted into the substrate. The isolation trench <NUM> surrounds, or is perimetric to, the second well region <NUM> and the second buried layer <NUM>. The isolation trench <NUM> extends to a depth within the substate that exceeds the depth of the first and second buried layers <NUM>, <NUM>. The trench <NUM> may be filled, or partially filled, with a polysilicon material.

It will be appreciated that steps <NUM> to <NUM> could be carried out in a different order to the order shown in <FIG>.

Accordingly, there has been described a semiconductor device comprising a substrate having a first conductivity type, the substrate having a top surface and a bottom surface, a first buried layer disposed in the substrate at a first depth from the top surface, wherein the first buried layer has a second conductivity type and a first doping concentration, a second buried layer adjacent and surrounding the first buried layer at the first depth, wherein the second buried layer has the second conductivity type and a second doping concentration, wherein the second doping concentration is less than the first doping concentration, and an isolation trench disposed in the substrate and surrounding the second buried layer, wherein the isolation trench extends from the top surface of the substrate to a second depth, the second depth exceeding the first depth. A method of manufacture is also provided, as described above.

Claim 1:
A semiconductor device comprising:
a substrate (<NUM>) having a first conductivity type, the substrate having a top surface (<NUM>) and a bottom surface (<NUM>);
a first buried layer (<NUM>) disposed in the substrate at a first depth from the top surface, wherein the first buried layer has a second conductivity type and a first doping concentration;
a second buried layer (<NUM>) adjacent and surrounding the first buried layer at the first depth, wherein the second buried layer has the second conductivity type and a second doping concentration, wherein the second doping concentration is less than the first doping concentration; and
an isolation trench (<NUM>) disposed in the substrate and surrounding the second buried layer wherein the isolation trench extends from the top surface of the substrate to a second depth, the second depth exceeding the first depth.