Patent Description:
With development of the semiconductor technology, semiconductor devices have become smaller in size. In the semiconductor technology, shrinking of feature sizes, and improving operation speed, efficiency, density, and cost per Integrated circuit are important objectives. To satisfy customer need and the market demand, it is important to shrink devices in size and also to maintain the electricity of devices. However, as devices shrink in size, the risk of undesirable damage to layers and elements in devices during the manufacturing process is increased, which results in considerable negative effects upon electrical performance of devices. As such, how to prevent damage to layers and elements in devices has become an issue. Generally, in order to produce semiconductor devices with good electrical performance, profiles of elements in devices should be in complete shape.

The manufacturing process of semiconductor structure usually includes forming several materials on a substrate and removing the materials afterwards. Ion beam etching (IBE) process is one of the methods used to remove the materials formed on the substrate. Ion beam etching process is a dry etching technique where ions are accelerated toward the surface of the target material. Through interactions between ions and target material, the target material is removed completely or partially to have a predetermined height.

However, ion beam etching process depends on a critical dimension (CD) of an element in existing technology, that is, elements having different critical dimensions may have different heights after applying an ion beam etching process. Particularly, applying an ion beam etching process to an element having a critical dimension more than <NUM> will result in considerable remaining of material to be removed, which also known as the problem of under etching.

Take electrode elements in semiconductor structures as an example, manufacturing process usually includes applying an etching process to electrode elements, and then forming conductive structures, such as vias and metal layers, around the electrode elements. Once the problem of under etching occurs in the etching process, the heights of the electrode elements after the etching process may be higher than the predetermined height, which causes problems in subsequent processes. For example, dielectric layers may remain, and conductive structures may be unable to form in correct positions in subsequent processes. As a result, an open risk occurs in semiconductor structures. In other words, the problem of under etching may lead to insufficient process window.

The invention relates to a semiconductor structure as defined in claim <NUM>.

The disclosure will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.

According to the embodiments of the present disclosure, a semiconductor structure is provided. The embodiments are described in detail with reference to the accompanying drawings. The details of the embodiments are for exemplification only, not for limiting the scope of protection of the appended claims. Moreover, identical or similar elements of the embodiments are designated with the same reference numerals. Also, it is also important to point out that the illustrations may not be necessarily be drawn to scale. Thus, the specification and the drawings are to be regarded as an illustrative sense rather than a restrictive sense. It is to be noted that the drawings are simplified for clearly describing the embodiments, and the details of the structures of the embodiments are for exemplification only, not for limiting the scope of protection of the appended claims. Ones having ordinary skills in the art may modify or change the structures according to the embodiments of the present disclosure.

<FIG> illustrates a schematic sectional view of an electrode element according to the present disclosure. As shown in <FIG>, the electrode element <NUM> has an upper surface <NUM>, and the upper surface <NUM> includes a plurality of convex curved portions. In one embodiment, the electrode element <NUM> may include a lower electrode portion <NUM> and an upper electrode portion <NUM>. The upper electrode portion <NUM> has convex structures sticking out from the lower electrode portion <NUM> in an upward direction (a first direction D1, e.g. a vertical direction or a z-direction). The upper electrode portion <NUM> has the upper surface <NUM>. The convex structures may have a varied height showing a decrease from the center of each convex structure toward two opposite sides in height. The upper surfaces of the convex structures may be understood as the convex curved portion of the upper surface <NUM>. The maximum height of the upper electrode portion <NUM> having the convex structures (which may be understood as a height along a central line of each convex structure in the first direction D1 of the upper electrode portion <NUM>) may be, but not limited to, <NUM> to <NUM>. The height of the lower electrode portion <NUM> may be defined as a distance between a lower surface of the electrode element <NUM> and the lowest area between two adjacent convex structures. The lower electrode portion <NUM> may have a substantial uniform height. For example, the lower electrode portion <NUM> may have a height of <NUM> to <NUM>.

In one embodiment, the formation of the electrode element <NUM> may include: forming a conductive film through a proper deposition process; patterning the conductive film through a photo lithography etching process to form a conductive lump with a flat upper surface; and applying an ion beam etching process to the conductive lump to remove partial material of the conductive lump from the flat upper surface. The ion beam etching process is stopped at an etch-stop line, and an etch depth of the ion beam etching process, defined as a distance between the flat upper surface and the etch-stop line in the first direction D1, is less than the thickness (a dimension in the first direction D1) of the conductive lump. As a result, the upper part of the conductive lump above the etch-stop line is removed partially to form the upper electrode portion <NUM>, and the lower part of the conductive lump below the etch-stop line, to which the ion beam etching process is not applied, is defined as the lower electrode portion <NUM>. The upper electrode portion <NUM> and the lower electrode portion <NUM> may include the same conductive material, such as tantalum (Ta), copper (Cu) or any other proper materials.

In one embodiment, the upper electrode portion <NUM> may include a moth eye structure that tapers from the bottom plane section to the top plane section. Specifically, the bottom plane section and the top plane section of the moth eye structure are areas in a plane defined by a second direction D2 and a third direction D3 (e.g. x-y plane), and the moth eye structure tapers in the first direction D1 (e.g. z-direction). The upper surface <NUM> of the electrode element <NUM> may be understood as the upper surface <NUM> of the upper electrode portion <NUM> having the moth eye structure. The convex curved portion of the upper surface <NUM> may have convex curved portions with hemisphere shapes or hemi- ellipsoid shapes arranged continuously. In one embodiment, the upper electrode portion <NUM> having the moth eye structure may have an arrangement that shows convex curved portions in rows and columns. <FIG> shows a sectional view of an electrode element taken along the cross-sectional line AA shown in <FIG>. However, the arrangement of the upper electrode portion <NUM> is not limited to the disclosure above. The upper electrode portion <NUM> may have other proper pattern, such as a mesh pattern.

The electrode element <NUM> is used in a semiconductor structure shown in <FIG> illustrates a schematic sectional view of the semiconductor structure according to one embodiment of the present disclosure. The electrode element <NUM> is used as an electrode for a magnetic tunnel junction (MTJ) structure <NUM>. The MTJ structure <NUM> may include a composite structure formed by a plurality of layers. The layers may include at least a first magnetic layer <NUM>, a second magnetic layer <NUM>, and an insulating layer <NUM> formed between the first magnetic layer <NUM> and the second magnetic layer <NUM>. In one embodiment, as shown in <FIG>, the electrode element <NUM> is formed on the MTJ structure <NUM>, and the MTJ structure may be formed on a bottom electrode <NUM>. The MTJ structure <NUM> is electrically connected between the electrode element <NUM> and the bottom electrode <NUM>. The bottom electrode <NUM> is formed on via elements <NUM>. The via elements <NUM> are separated from each other. In this embodiment, the electrode element <NUM> is used as a top electrode for the MTJ structure <NUM>. The directions of magnetization of the first magnetic layer <NUM> and the second magnetic layer <NUM> of the MTJ structure <NUM> may be switched individually as current passes through the MTJ structure <NUM> through the top electrode and the bottom electrode <NUM>. The electrical resistance of the MTJ structure <NUM> changes due to the relative orientation of the directions of magnetization of the first magnetic layer <NUM> and the second magnetic layer <NUM>. Consequently, the MTJ structure <NUM> may be switched between different states of electrical resistance. Different states of electrical resistance may represent different operation mode of the MTJ structure <NUM>. For example, a low resistance state may be considered to mean "<NUM>", while a high resistance state may be considered to mean "<NUM>". The insulating layer <NUM> of the MTJ structure <NUM> may include an oxide, specifically an oxide of metal. For example, the insulating layer <NUM> of the MTJ structure <NUM> may include magnesium oxide (MgO) or any other proper materials. The first magnetic layer <NUM> and the second magnetic layer <NUM> of the MTJ structure <NUM> may include metals, such as nickel (Ni), iron (Fe), cobalt (Co), or the combination thereof, or any other proper materials. The bottom electrode <NUM> may include conductive materials, such as tantalum (Ta), copper (Cu) or any other proper materials. Specifically, the bottom electrode <NUM> may include tantalum nitride (TaN).

As shown in <FIG>, via elements <NUM> are disposed on the conductive layer <NUM> through a dielectric element <NUM>. The dielectric element <NUM> is disposed on the conductive layer <NUM>. The conductive layer <NUM> may be a metal layer, such as a Metal <NUM> (M2) layer. Further, the semiconductor structure may include a dielectric layer <NUM> formed on the dielectric element <NUM> and on a sidewall of the via elements <NUM>. In one embodiment, the semiconductor structure may include a hard mask layer <NUM> formed on the electrode element <NUM>. The hard mask layer <NUM> may include an oxide, such as silicon oxide. The hard mask layer <NUM> may include a nitride, such as silicon nitride. The hard mask layer <NUM> may include any other proper dielectric materials or materials suitable for a hard mask. For example, the formation of the hard mask layer <NUM> may include forming a thin film conformally covering the electrode element <NUM> through a proper deposition process and applying an ion beam etching process to the thin film to form the profile shown in <FIG>. In one embodiment, the thin film formed through a deposition process may have a substantial uniform thickness, such as, but not limited to, a thickness of <NUM> to <NUM>. As shown in <FIG>, the thickness of the hard mask layer <NUM> on the convex structures of the upper electrode portion <NUM> has a profile gradually decreasing from the center of the hard mask layer <NUM> toward two opposite sides of the hard mask layer <NUM>. The hard mask layer <NUM> covers the upper surface <NUM> of the electrode element <NUM> and may further cover a sidewall of the lower electrode portion <NUM>. In one embodiment, the hard mask layer <NUM> is formed on the electrode element <NUM> and a sidewall of the MTJ structure <NUM>. In one embodiment, the profile of the dielectric layer <NUM> is formed through an ion beam etching process, and the hard mask layer <NUM> may prevent the electrode element <NUM> from being damaged by the ion beam etching process. In one embodiment, the semiconductor structure may include a dielectric film <NUM> formed on the dielectric layer <NUM>, the MTJ structure <NUM>, the electrode element <NUM> and the hard mask layer <NUM>.

The height of the electrode element <NUM> may be controlled accurately through an ion beam etching process. For example, a difference in height between any two of convex structures of the upper electrode portion <NUM>, also understood as a difference in the maximum height between of any two of convex structures, may be approximately less than <NUM>Ångström (Å). Alternatively, the electrode element <NUM> may have a height which a difference in height between the electrode element <NUM> and a conductive element in other region formed by the same conductive film as the electrode element <NUM> is less than <NUM>Å. In some embodiments, the accurate control to the height of the electrode element <NUM> may prevent a loading effect problem during a chemical-mechanical polishing process applied to the dielectric film <NUM>, and improve the process windows of the subsequent processes. For example, a via element and a Metal <NUM> layer formed subsequently on a Metal <NUM> layer in other region may have a reliable electrical connection with the Metal <NUM> layer, which prevents a problem of broken circuit. As a result, the yield of the product is improved.

In one embodiment, ion beam etching process is performed according the layout shown in <FIG>. The layout may include a space S1 in the second direction D2, a dimension W1 in the second direction D2 (such as a width), a pitch K1 in the second direction D2, a space S2 in the third direction D3, a dimension W2 in the third direction D3 (such as a width), and a pitch K2 in the third direction D3. In one embodiment, the layout may be stored in a GDS format. The pitch K1 is the sum of the space S1 and the dimension W1. The pitch K2 is the sum of the space S2 and the dimension W2. In one embodiment, in the grid layout, the ratio of the pitch K1 to the pitch K2 is <NUM> : <NUM>, for example, the pitch K1 is <NUM> and the pitch K2 is <NUM>. In another embodiment, in the grid layout, the ratio of the pitch K1 to the pitch K2 is <NUM> : <NUM>, for example, the pitch K1 is <NUM> and the pitch K2 is <NUM>. In yet another embodiment, in the grid layout, the ratio of the pitch K1 to the pitch K2 is <NUM> : <NUM>, for example, the pitch K1 is <NUM> and the pitch K2 is <NUM>. Sizes of the layout are not limited to the above example values. In one embodiment, the space S1 in <FIG> may correspond to the space S1 shown in <FIG>. The space S1 may be, but not limited to, <NUM> to <NUM>.

Claim 1:
A semiconductor structure, comprising:
an electrode element (<NUM>) having an upper surface (<NUM>), the upper surface (<NUM>) comprising at least one convex curved portion;
a magnetic tunnel junction structure (<NUM>), wherein the electrode element (<NUM>) is a top electrode for the magnetic tunnel junction structure (<NUM>); and
via elements (<NUM>) separated from each other, wherein the magnetic
tunnel junction structure (<NUM>) is on the via elements (<NUM>), characterized in that
the upper surface (<NUM>) of the electrode element (<NUM>) comprises a plurality of the convex curved portions.