Patent Description:
It is well known that digital logic systems can be implemented with superconducting circuitry based on Josephson junctions. Although the technology has its challenges, one of the major potential benefits is greatly reduced power consumption relative to semiconductor technologies, despite the fact that Josephson systems require operation at temperatures close to absolute zero. It is for this reason that there is much recent interest in Josephson technology, for example, the IARPA SuperTools program, which seeks to develop a comprehensive set of Electronic Design Automation (EDA) and Technology Computer-Aided Design (TCAD) tools for Very-Large-Scale-Integration (VLSI) design of superconducting electronic circuits, a program in which the applicant, Synopsys, plays a leading role.

There are several Josephson logic families that are being developed and championed by different organizations, each with advantages and disadvantages relative to each other as shown e.g. in document <CIT>. Reciprocal Quantum Logic (RQL), and Adiabatic Quantum Flux Parametron (AQFP), are two such examples. The third primary technology is Single Flux Quantum (SFQ) logic, which comes in different flavors, including Rapid or Resistive SFQ (RSFQ) and Energy-Efficient SFQ (ERSFQ or EERSFQ). The SFQ circuits can be biased with direct current, while the others require a multi-phase microwave power signal, which must be routed to a large number of gates while maintaining timing accuracy and amplitude. In comparison to the SFQ circuitry biased with direct current, circuits based on the multi-phase microwave power signal are technically more challenging.

RSFQ was the original SFQ approach, where 'R' stands for "resistive," or "rapid. " This logic was invented in the <NUM>, and work continues using this same basic approach as it requires the simplest biasing circuitry. It has the disadvantage of relatively high power dissipation.

The ERSFQ approach was proposed as a lower-power SFQ derivative, which has approximately an order of magnitude less power consumption compared to standard RSFQ. The ERSFQ family, in use for over a decade, uses an on-chip voltage regulator implemented as a Josephson Transmission Line (JTL), referred to herein as a "feeding JTL. " One purpose of the feeding JTL is to implement a very low voltage (tens of microvolts) on-chip source, which by keeping chip bias voltage very low, ensures that power dissipation is also low. However, the feeding JTL itself may require significant operating current and contribute substantially to circuit area requirement and component count. Consequently, this regulation method may have substantial disadvantages in these regards.

The invention is defined by the appended claims and relates to an electronic structure as defined in claim <NUM> and to a method of designing an electronic structure as defined in claim <NUM>.

The following Detailed Description, Figures, and Claims signify the uses and advantages of the claimed inventions and their embodiments. All of the Figures are used only to provide knowledge and understanding and do not limit the scope of the claimed inventions and their embodiments. Such Figures are not necessarily drawn to scale.

Similar components or features used in the Figures can have the same or similar reference signs in the form of labels (such as alphanumeric symbols, e.g., reference numerals), and can signify a similar or equivalent use. Further, various components of the same type can be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the Specification, its use applies to any similar component having the same first reference label irrespective of the second reference label. A brief description of the Figures is below.

In the drawings, reference signs can be omitted as is consistent with accepted engineering practice; however, a skilled person will understand that the illustrated components are readily understood when viewed in the context of the illustration as a whole and the accompanying disclosure describing such various figures.

The Figures and Detailed Description signify, only to provide knowledge and understanding, the claimed inventions. To minimize the length of the Detailed Description, while various features, structures, or characteristics can be described together in a single embodiment, they also can be used in other embodiments without being written about. The Figures and Detailed Description also can signify, implicitly or explicitly, advantages and improvements of the claimed inventions and their embodiments.

In the Figures and Detailed Description, numerous specific details can be described to enable at least one embodiment of the claimed inventions. Any embodiment disclosed herein signifies a tangible form of a claim invention. To not obscure the significance of the embodiments and/or examples in this Detailed Description, some elements that are known to a skilled person can be combined together for presentation and for illustration purposes and not be described in detail. To not obscure the significance of these embodiments and/or examples, some well-known processes, machines, systems, manufactures, or compositions are not written about in detail. Thus, the Detailed Description focuses on enabling the distinctive elements of the claimed inventions and exemplary embodiments. Where this Detailed Description refers to some elements in the singular tense, more than one element can be depicted in the Figures, and like elements are labeled with like numerals.

In this disclosure, various embodiments based on the ERSFQ (Energy Efficient RSFQ) approach are detailed as a lower-power SFQ derivative. This has approximately an order of magnitude less power consumption than is possible with standard RSFQ.

<FIG> illustrates a method of powering rapid single flux quantum (RSFQ) circuitry. <FIG> illustrates an RSFQ circuit <NUM> with a dropping resistor <NUM> and a bias voltage source <NUM>. Due to the dropping resistor <NUM>, the RSFQ circuit <NUM> has a high power dissipation. The bias voltage source <NUM>, as shown in <FIG>, is connected to the dropping resistor <NUM>, which is connected to a Josephson junction <NUM>. Even though, only one instance of the dropping resistor <NUM> and the Josephson junction <NUM> are shown in <FIG>, the RSFQ circuit may have a plurality of similar Josephson junction <NUM>, each connected with a dropping resistor similar to the dropping resistor <NUM>. By way of non-limiting example, for the RSFQ circuit <NUM>, the bias voltage source <NUM> may be provided off-chip.

The time-averaged voltage across Josephson junction <NUM> may range from <NUM> volts, when the Josephson junction is not switching at all, to a voltage proportional to the system clock frequency when the Josephson junction pulses on every clock cycle. The average voltage across a Josephson junction depends on the frequency of pulsing with a proportionality constant that is twice the electron charge divided by Planck's constant, or about <NUM> per microvolt.

Accordingly, the bias current is obtained from the voltage source <NUM> through use of a dropping resistor <NUM>. The values of the voltage source <NUM> and the dropping resistor <NUM> specify the biasing current. For the RSFQ circuit <NUM>, the average voltage across the dropping resistor <NUM> may vary according to the switching probability of the Josephson junction <NUM> and may cause the bias current supplied to the Josephson junction <NUM> to change correspondingly. The change of the bias current through the Josephson junction <NUM> may cause spurious triggering or lack of an expected triggering. Accordingly, to prevent the spurious triggering or lack of the expected triggering, the bias source voltage <NUM> may be required to be at least ten times higher than the voltage corresponding to the system clock frequency. Accordingly, the dropping resistor <NUM> may dissipate at least <NUM> percent of chip power as heat in a very low-temperature environment.

According to the invention, a Josephson junction as a current source is used as a constant current bias to the circuit junction. In this case, when the on-chip voltage is kept low, the total power dissipation may be lower compared to using the dropping resistor <NUM>. By way of non-limiting example, the total power dissipation may be about ten times lower than the total power dissipation with the dropping resistor.

<FIG> illustrates current-voltage (I-V) characteristics of a shunted Josephson junction as a current source, in accordance with some embodiments. The current source is evident from the I-V characteristic of the shunted Josephson junction that shows average current changes are very small compared to voltage changes, as shown in <FIG> by <NUM>. In other words, a ratio of a difference in current to a difference in voltage (di/ dv) is almost zero when the voltage across the Josephson junction as the current source is kept low. Accordingly, the power dissipation is kept low, while the current flowing through the Josephson junction may be controlled to be the same as the critical current Ic required for the Josephson junction. In addition to the constant DC current, there will be a large AC current, which may be filtered out to prevent interfering of the circuit being biased. The AC current may be filtered out by inductance placed in series with the Josephson junction.

<FIG> illustrates a simulation of a Josephson current source element, in accordance with some embodiments. The simulation of the Josephson current source element may be performed using a circuit simulator. One example of such a circuit simulator may be WRspice Circuit Simulator from Whiteley Research Inc. The circuit simulator may accept as an input circuit description using Simulation Program with Integrated Circuit Emphasis (SPICE) specification language. As shown in <FIG>, the Josephson junction <NUM> being biased is connected to a constant voltage source <NUM>. Another voltage source (<NUM>), which may be time-varying, is used to model the Josephson junction anticipated as the load. The voltage across the voltage source <NUM> may be changing so that an effect of the voltage change across the junction may be simulated. By way of non-limiting example, the voltage of the other voltage source <NUM> may change from <NUM> volt to <NUM> microvolts and back, and the voltage of the voltage source <NUM> may be <NUM> microvolts. Accordingly, an average voltage across the Josephson current source may change by a factor of <NUM>, in this case.

<FIG> shows a current graph <NUM> that indicates the current through the current source at point <NUM> and a voltage graph <NUM> that indicates the voltage measured at point <NUM>. As shown in <FIG>, long ramp-up <NUM> is due to a filter inductor <NUM>, for example, of value <NUM> nanoHenry, charging up from the voltage source <NUM>. As shown in <FIG>, the bias current may contain ripple <NUM> of about <NUM> percent, which is shown as zoomed-in ripple <NUM>. However, the bias current ripple <NUM>, <NUM> may be reduced by using a large inductance filter.

<FIG> illustrates an example of feeding JTL regulating voltage on bias line. <FIG> shows a feeding JTL <NUM>, a bias line <NUM>, a ground plane <NUM>, a JTL clock <NUM>, and logic circuitry <NUM>. The feeding JTL <NUM> is driven by the JTL clock <NUM>. The JTL clock <NUM> may be in addition to a system clock, and the frequency of the JTL clock <NUM> may set the voltage across the feeding JTL and bias voltage for the bias line <NUM>. However, any benefit of precise voltage regulation by the feeding JTL <NUM> using conventional techniques may be outweighed by the complexity and additional power dissipation of the feeding JTL <NUM>. The feeding JTL is used to establish a known reference voltage from which to power the SFQ circuitry, however as shown below this can be replaced by a more efficient approach.

In <FIG>, the feeding JTL <NUM> may be removed and replaced by a resistor <NUM>, according to some embodiments. Such replacement of the feeding JTL <NUM> by the resistor <NUM> may free substantial circuit area, since none of the JTL clock <NUM> and associated inductors 502a through <NUM> are needed. By way of non-limiting example, each bias feed point may have an added resistor to ground, and approximately <NUM> percent of the overall chip bias current may flow through a plurality of resistors to ground. The plurality of resistors to the ground may provide a well-defined bias voltage when the chip is biased by a relatively high impedance source. Further, the on-chip voltage may not be clamped as it generally occurs in the feeding JTL, rather the on-chip voltage may vary with the changing bias current. The voltage across the resistor <NUM> is the "excess" current not consumed by a Josephson junction current source <NUM> times the value of the resistance. Since the resistor <NUM> is in parallel to the Josephson junction and the bias line, the on-chip voltage may be provided according to the expectations by adjusting the bias current.

Even though the feeding JTL and the embodiments described herein, both may use resistors as part of the biasing network, the embodiments described herein differ from the feeding JTL. For example, the feeding JTL may use dropping resistors <NUM>, which appear in series with the Josephson junction <NUM>. The values of the dropping resistors may be high and may cause the dropping resistors to appear as a current source to the load. On the other hand, in biasing circuitry described herein with reference to various embodiments, an actual current source may be provided, and resistors with small resistance to the ground may be used to control the voltage at the feed point. Because only a small amount of current may be needed to flow through these resistors to ground, the power dissipation is small. By way of non-limiting example, the power dissipation through the resistors to the ground may be approximately <NUM> percent of the total power dissipation. Further, the resistor to ground <NUM> used in the embodiments is of very small value compared to the dropping resistor <NUM>. Therefore, the resistor to the ground used in the embodiments may require substantially less circuit area. Thus, the resistor to ground to drain the excess current may allow using the Josephson junction current source to replace the functionality of dropping resistor.

In some embodiments, when the feeding JTL <NUM> is replaced by a resistor to ground <NUM>, about <NUM> percent of the Josephson junctions required by an ERSFQ logic chip may be eliminated. Along with the elimination of the Josephson junctions, associated inductors may also be eliminated, which may free up substantial chip area for additional circuitry and functionality, or a small die size may be used for the chip minimizing the overall circuit.

<FIG> illustrates current and voltage characteristics for the electrical structure of <FIG>, according to an exemplary embodiment of the present disclosure. As described above, the feeding JTL <NUM> may provide precise regulated voltage, but requires more circuit area. In comparison to the feeding JTL <NUM>, the voltage measured at points <NUM> and <NUM> shows that the voltage at points <NUM> and <NUM> may not be as precise as available using the feeding JTL <NUM>. However, a lack of precise voltage control is not known to be associated with any adverse effect during testing. This is because the system power supply regulator may provide and control the power needed to accommodate the system clock frequency. Also, current flow measured at points <NUM> and <NUM> for each bias feed branch, and voltage measured at points <NUM> and <NUM> are shown as graphs <NUM>, <NUM>, <NUM>, and <NUM>, respectively, in <FIG>. A zoomed-in version of graphs <NUM>, <NUM>, <NUM>, and <NUM> are also shown as <NUM>, <NUM>, <NUM>, and <NUM>, respectively. As described above, the current ripple shown in <NUM> and <NUM> remains less than <NUM> percentage. In other words, the current flow remains constant across the Josephson junctions <NUM> and <NUM>. The current flow remains constant even in the presence of excess inductance, for example, inductors <NUM> and <NUM> placed to simulate a bias line, which may be a narrow and meandering strip in the chip layout. Further, as seen from voltage graphs <NUM> and <NUM>, or <NUM> and <NUM>, the time required to charge the inductors up to their quiescent currents is significantly reduced.

Based on the above disclosure, in some embodiments, a parameterized power distribution point cell may be designed for use in Electronic Design Automation (EDA) systems.

<FIG> illustrates four power distribution point cells, in accordance with some embodiments. As shown in <FIG>, four power distribution point cells <NUM>, <NUM>, <NUM>, and <NUM> simulate the circuit load. Each power distribution point cell <NUM>, <NUM>, <NUM>, and <NUM> may include a current source Josephson junction, for example, 802a, 804a, 806a, and 808a, the filter inductor for example, 802b, 804b, 806b, and 808b), and a resistor to the ground, for example, 802c, 804c, 806c, and 808c. The value of resistor to the ground and the junction critical current are set by the cell parameter, which is the current delivered by the power distribution cell. There is no additional circuitry required for the power distribution system, and the actual inductance of the power supply lines on-chip <NUM>, <NUM>, and <NUM> can be incorporated into the schematic.

<FIG> illustrates characteristics of voltage over time for the electrical structure of <FIG>, according to an exemplary embodiment of the present disclosure. Simulation and measurement of current at points <NUM>, <NUM>, <NUM>, and <NUM>, and voltage at points <NUM>, <NUM>, <NUM>, and <NUM> shown in <FIG> as <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, respectively, which may be consistent with similar current and voltage characteristics, for example, shown in <FIG>.

Finally, a logic circuit based on the embodiments disclosed herein may require much less circuit area since it requires much fewer components and circuitry in comparison to a logic circuit with the feeding JTL. Further, since at least <NUM> percentage of Josephson junctions may be eliminated, and the overall cost of the logic circuit may be reduced while increasing yield.

<FIG> and <FIG> are diagrams of example computer systems suitable for enabling embodiments of the claimed inventions.

In <FIG>, the structure of a computer system <NUM> typically includes at least one computer <NUM>, which communicates with peripheral devices via bus subsystem <NUM>. Typically, the computer includes a processor (e.g., a microprocessor, graphics processing unit, or digital signal processor), or its electronic processing equivalents, such as an Application Specific Integrated Circuit ('ASIC') or Field Programmable Gate Array ('FPGA'). Typically, peripheral devices include a storage subsystem <NUM>, comprising a memory subsystem <NUM> and a file storage subsystem <NUM>, user interface input devices <NUM>, user interface output devices <NUM>, and/or a network interface subsystem <NUM>. The input and output devices enable direct and remote user interaction with the computer system <NUM>. The computer system enables significant post-process activity using at least one output device and/or the network interface subsystem.

The computer system can be structured as a server, a client, a workstation, a mainframe, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a smartphone, a web appliance, a rack-mounted 'blade,' a kiosk, a television, a game station, a network router, switch or bridge, or any data processing machine with instructions that specify actions to be taken by that machine. The term 'server,' as used herein, refers to a computer or processor that typically performs processes for, and sends data and information to, another computer or processor.

A computer system typically is structured, in part, with at least one operating system program, such as Microsoft's Windows, Sun Microsystems's Solaris, Apple Computer's macOS and iOS, Google's Android, Linux and/or Unix. The computer system typically includes a Basic Input/Output System (BIOS) and processor firmware. The operating system, BIOS, and firmware are used by the processor to structure and control any subsystems and interfaces connected to the processor. Typical processors that enable these operating systems include the Pentium, Itanium, and Xeon processors from Intel; the Opteron and Athlon processors from Advanced Micro Devices; the Graviton processor from Amazon; the POWER processor from IBM; the SPARC processor from Oracle; and the ARM processor from ARM Holdings.

Network interface subsystem <NUM> provides an interface to outside networks, including an interface to a communication network <NUM>, and is coupled via communication network <NUM> to corresponding interface devices in other computer systems or machines. Communication network <NUM> can comprise many interconnected computer systems, machines, and physical communication connections (signified by 'links'). These communication links can be wireline links, optical links, wireless links (e.g., using the Wi-Fi or Bluetooth protocols), or any other physical devices for communication of information. Communication network <NUM> can be any suitable computer network, for example, a wide area network such as the Internet and/or a local-to-wide area network such as Ethernet. The communication network is wired and/or wireless, and many communication networks use encryption and decryption processes, such as is available with a virtual private network. The communication network uses one or more communications interfaces, which receive data from and transmit data to other systems. Embodiments of communications interfaces typically include an Ethernet card, a modem (e.g., telephone, satellite, cable, or ISDN), (asynchronous) digital subscriber line (DSL) unit, Firewire interface, USB interface, and the like. Communication algorithms ('protocols') can be specified using one or communication languages, such as HTTP, TCP/IP, RTP/RTSP, IPX, and/or UDP.

User interface input devices <NUM> can include an alphanumeric keyboard, a keypad, pointing devices such as a mouse, trackball, toggle switch, touchpad, stylus, a graphics tablet, an optical scanner such as a bar code reader, touchscreen electronics for a display device, audio input devices such as voice recognition systems or microphones, eye-gaze recognition, brainwave pattern recognition, optical character recognition systems, and other types of input devices. Such devices are connected by wire or wirelessly to a computer system. Typically, the term 'input device' signifies all possible types of devices and processes to transfer data and information into the computer system <NUM> or onto communication network <NUM>. User interface input devices typically enable a user to select objects, icons, text, and the like that appear on some types of user interface output devices, for example, a display subsystem.

User interface output devices <NUM> can include a display subsystem, a printer, a fax machine, or a non-visual communication device such as audio and haptic devices. The display subsystem can include a cathode ray tube (CRT), a flat-panel device such as a liquid crystal display (LCD), an image projection device, or some other device for creating visible stimuli such as a virtual reality system. The display subsystem also can provide non-visual stimuli such as via audio output, aroma generation, or tactile/haptic output (e.g., vibrations and forces) devices. Typically, the term 'output device' signifies all possible types of devices and processes to transfer data and information out of computer system <NUM> to the user or to another machine or computer system. Such devices are connected by wire or wirelessly to a computer system. Note: some devices transfer data and information both into and out of the computer, for example, haptic devices that generate vibrations and forces on the hand of a user while also incorporating sensors to measure the location and movement of the hand. Technical applications of the sciences of ergonomics and semiotics are used to improve the efficiency of user interactions with any processes and computers disclosed herein, such as any interactions with regards to the design and manufacture of circuits that use any of the above input or output devices.

Memory subsystem <NUM> typically includes a number of memories including a main random-access memory ('RAM') <NUM> (or other volatile storage devices) for storage of instructions and data during program execution and a read-only memory ('ROM') <NUM> in which fixed instructions are stored. File storage subsystem <NUM> provides persistent storage for program and data files and can include a hard disk drive, a floppy disk drive along with associated removable media, a CD-ROM drive, an optical drive, a flash memory such as a USB drive, or removable media cartridges. If computer system <NUM> includes an input device that performs optical character recognition, then text and symbols printed on paper can be used as a device for storage of program and data files. The databases and modules used by some embodiments can be stored by file storage subsystem <NUM>.

Bus subsystem <NUM> provides a device for transmitting data and information between the various components and subsystems of computer system <NUM>. Although bus subsystem <NUM> is depicted as a single bus, alternative embodiments of the bus subsystem can use multiple busses. For example, a main memory using RAM can communicate directly with file storage systems using Direct Memory Access ('DMA') systems.

<FIG> depicts a memory <NUM> such as a non-transitory, processor-readable data and information storage medium associated with file storage subsystem <NUM>, and/or with network interface subsystem <NUM>, and can include a data structure specifying a circuit design. The memory <NUM> can be a hard disk, a floppy disk, a CD-ROM, an optical medium, removable media cartridge, or any other medium that stores computer-readable data in a volatile or non-volatile form, such as text and symbols on paper that can be processed by an optical character recognition system. In some examples, the memory <NUM> may include a plurality of cells <NUM> to store data. A program transferred in to and out of a processor from such a memory can be transformed into a physical signal that is propagated through a medium (such as a network, connector, wire, or circuit trace as an electrical pulse); or through a medium such as space or an atmosphere as an acoustic signal, or as electromagnetic radiation with wavelengths in the electromagnetic spectrum longer than infrared light).

<FIG> depicts a set of processes <NUM> used during the design, verification, and fabrication of an article of manufacture such as an integrated circuit to transform and verify design data and instructions that represent the integrated circuit. Each of these processes can be structured and enabled as multiple modules. The term 'EDA' signifies the term 'Electronic Design Automation. ' These processes start with the creation of a product idea <NUM> with information supplied by a designer, information that is transformed to create an article of manufacture that uses a set of EDA processes <NUM>. When the design is finalized, it is taped-out <NUM>, which typically is when artwork (e.g., geometric patterns) for the integrated circuit is sent to a fabrication facility to manufacture the mask set, which is then used to manufacture the integrated circuit. After tape-out, a semiconductor die is manufactured <NUM>, and packaging and assembly processes <NUM> are performed to produce the finished integrated circuit.

Specifications for a circuit or electronic structure are as used in multiple levels of useful abstraction ranging from low-level transistor material layouts to high-level description languages. Most designers start with a description using one or more modules with less detail at a high-level of abstraction to design their circuits and systems, using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL or OpenVera. The high-level description is easier for designers to understand, especially for a vast system, and can describe very complex systems that are difficult to understand using a lower level of abstraction that is a more detailed description. The HDL description can be transformed into other levels of abstraction that are used by the developers. For example, a high-level description can be transformed to a logic-level register transfer level ('RTL') description, a gate-level description, a layout-level description, or a mask-level description. Each lower abstraction level that is a less abstract description adds more useful detail into the design description, for example, more details for the modules that comprise the description. The lower-levels of abstraction that are less abstract descriptions can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of abstraction language for specifying more detailed descriptions is SPICE, which is much used for detailed descriptions of circuits with many analog components. Descriptions at each level of abstraction are enabled for use by the corresponding tools of that layer (for example, a formal verification tool), and some of the modules of the abstractions need not be novel or unobvious.

A design process that uses EDA processes <NUM> includes processes <NUM> to <NUM>, which are described below. This design flow description is used only to illustrate, not to limit. For example, a designer of an integrated circuit can use the design processes in a different sequence than the sequence depicted in <FIG>. For the embodiments disclosed herein, products from Synopsys, Inc. of Mountain View, California (hereinafter signified by 'Synopsys'), are used to enable these processes, and/or similar products from other companies.

During system design <NUM>, a designer specifies the functionality to be manufactured. The designer also can optimize the power, performance, and area (physical and/or lines of code) and minimize costs, etc. Partitioning of the design into different types of modules can occur at this stage. Exemplary EDA products from Synopsys that enable system design <NUM> include the Model Architect, Saber, System Studio, and DesignWare products.

During the logic design and functional verification <NUM>, modules in the circuit are specified in one or more description languages, and the specification is checked for functional accuracy, that is, that the modules produce outputs that match the requirements of the specification of the circuit or system being designed. Exemplary HDL languages are Verilog, VHDL, and SystemC. Functional verification typically uses simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some situations, special systems of modules referred to as 'emulators' or 'prototyping systems' are used to speed up the functional verification. Exemplary EDA products from Synopsys that can be used at this stage include VCS, Vera, DesignWare, Magellan, Formality, ESP, and Leda products. Exemplary emulator and prototyping products available from Synopsys that enable logic design and functional verification <NUM> include ZeBu. RTM and Protolink. RTM (RTM signifies 'Registered Trademark').

During synthesis and design for test <NUM>, HDL code is transformed to a netlist (which typically is a graph structure where the edges represent components of a circuit and where the nodes represent how the components are interconnected). Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by an EDA product to verify that the integrated circuit, when manufactured, performs according to its design. This netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit is tested to verify that it satisfies the requirements of the specification. Exemplary EDA products from Synopsys that enable synthesis and design for the test include the Design Compiler, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, TetraMAX, and DesignWare products.

During netlist verification <NUM>, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. Exemplary EDA products from Synopsys that enable netlist verification <NUM> include the Formality, Primetime, and VCS products.

During design planning <NUM>, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing. Exemplary EDA products from Synopsys that enable design-planning <NUM> include the Astro and IC Compiler products.

During layout implementation <NUM>, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of the components by multiple conductors) occurs, and the selection of cells from a library to enable specific logic functions. As used herein, the term 'cell' signifies a set of transistors, other components, and interconnections that provides a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flip-flop or latch). As used herein, a circuit 'block' comprises two or more cells. Both a cell and a circuit block can be referred to as a module, and are enabled as both physical structures and in simulations. Parameters are specified for selected cells (based on 'standard cells') such as size and made accessible in a database for use by EDA products. Examples of databases that can be used for accessing cells include MySQL and PostgreSQL. Exemplary EDA products from Synopsys that enable layout implementation include the Astro and IC Compiler products.

During analysis and extraction <NUM>, the circuit function is verified at the layout level, which permits refinement of the layout design. Exemplary EDA products from Synopsys that enable analysis and extraction include the Astrorail, Primerail, Primetime, and Star RC/XT products.

During physical verification <NUM>, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithographic constraints, and that circuitry function matches the HDL design specification. Exemplary EDA products from Synopsys that enable physical verification <NUM> include the Hercules product.

During resolution enhancement <NUM>, the geometry of the layout is transformed to improve how the design is manufactured. Exemplary EDA products from Synopsys that enable resolution enhancement <NUM> include the Proteus product.

During tape-out, data is created to be used (after lithographic enhancements are applied if appropriate) for the production of lithography masks. Example EDA products from Synopsys that enable tape-out include the IC Compiler and Custom Designer products.

During mask-data preparation <NUM>, the 'tape-out' data is used to produce lithography masks that are used to produce finished integrated circuits. Exemplary EDA products from Synopsys that enable mask-data preparation <NUM> include the CATS family of products.

For all of the abovementioned EDA products, similar products from other EDA vendors, such as Cadence, Siemens, other corporate entities, or various non-commercial products from universities, or open-source repositories, can be used as an alternative.

A storage subsystem of a computer system (such as computer system <NUM> of <FIG>) is preferably used to store the programs and data structures that are used by some or all of the EDA products described herein, and products used for development of cells for the library and for physical and logical design that use the library.

Based on the teachings contained in this disclosure, it may be apparent to persons skilled in the relevant art(s) how to make and use embodiments of this disclosure using data processing devices, computer systems and/or computer architectures other than that shown in <FIG>. In particular, embodiments may operate with software, hardware, and/or operating system implementations other than those described herein.

Claim 1:
An electronic structure, comprising:
a first cell (<NUM>) comprising:
a first shunted Josephson junction (802a);
a first inductor (802b) connected in series with the first shunted Josephson junction (802a) at a first terminal end of the first inductor (802b) and a second terminal end of the first inductor (802b) being connected to a feed point (<NUM>, <NUM>) of the first cell; and
a first resistor (802c) having a first end connected to ground and a second end connected to the first shunted Josephson junction (802a) at a terminal of the first shunted Josephson junction (802a) that is not connected to the first inductor (802b); and wherein the first cell is powered by a source (J0) of an electrical current that is external to the first cell (<NUM>), wherein the source (J0) of the electrical current is connected to the first shunted Josephson junction (802a) and to the second end of the first resistor (802c).