Patent Description:
Polysilicon has a higher mobility rate and stability than amorphous silicon. Low temperature polycrystalline silicon (LTPS) thin film transistors have found a wide range of applications in display field. In conventional LTPS thin film transistors, the channel region is doped with a first dopant of a first type, and the source electrode and drain electrode contact region is doped with a second dopant of a second type. The first dopant and the second dopant are different types of dopants selected form a p-type dopant and an n-type dopant.

US patent application <CIT> discloses a doping method, which includes: a first step of depositing a material solution containing an antimony compound containing elements selected from the group consisting essentially of hydrogen, nitrogen, oxygen, and carbon together with antimony to a surface of a substrate; a second step of drying the material solution to form an antimony compound layer on the substrate; and a third step of performing heat treatment so that antimony in the antimony compound layer is diffused into the substrate.

US patent application <CIT> discloses a method for forming an ultra-shallow dopant region in a substrate. The method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.

US patent <CIT> discloses thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.

The disclosure will now describe more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

In manufacturing a conventional LTPS thin film transistor, an ion implantation process is utilized to dope the polycrystalline silicon active layer with dopants. A conventional LTPS thin film transistor fabricated by the ion implantation process in a low operating temperature range has a relatively large leak current. In order to achieve a satisfactory dopant diffusion, typically the ion implantation is performed in a high operating temperature range, e.g., higher than <NUM> degree Celsius. The high temperature ion implantation process, however, results in thermal damages in the base substrate. This problem is particularly prominent for flexible base substrates such as a polyimide base substrate.

Accordingly, the present disclosure provides a novel method of fabricating a LTPS thin film transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides a method of fabricating a polycrystalline silicon thin film transistor. The method includes forming an amorphous silicon layer on a base substrate having a pattern corresponding to a polycrystalline silicon active layer of the thin film transistor, the amorphous silicon layer having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer and a second region corresponding to a channel region in the polycrystalline silicon active layer; forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; crystallizing the amorphous silicon layer, the first dopant layer, and the second dopant layer to form the polycrystalline silicon active layer, the polycrystalline silicon active layer being doped with a dopant of the first dopant layer (e.g., a first dopant) in the second region and doped with a dopant of the second dopant layer (e.g., a second dopant) in the first region during the step of crystallizing the amorphous silicon layer. Optionally, the first dopant layer is formed to be in direct contact with the second region. Optionally, the second dopant layer is formed to be in direct contact with the first region. The first dopant layer is formed on a side of both the first region and the second region distal to the base substrate, and the polycrystalline silicon active layer in the first region is doped with both the dopant of the first dopant layer and the dopant of the second dopant layer. Optionally, when the first dopant layer is formed on a side of both the first region and the second region distal to the base substrate, the second dopant layer is formed to be in direct contact with the first dopant layer in an area corresponding to the first region. Optionally, the first dopant and the second dopant are of different types of dopants selected from a p-type dopant and an n-type dopant. Optionally, the first dopant and the second dopant are dopants of a same type. Optionally, the first dopant and the second dopant are the same dopant, and a concentration of the first dopant of the first dopant layer is different from that of the second dopant of the second dopant layer (e.g., a light doping region and a heavy doping region). As defined herein, the term "channel region" refers to a region of a thin film transistor between a source electrode contact region and a drain electrode contact region.

<FIG> illustrates a fabricating process of a thin film transistor in some embodiments in cross-section view of the thin film transistor. <FIG> illustrates a fabricating process of a thin film transistor in some embodiments in perspective view of the thin film transistor. Referring to <FIG> and <FIG>, the method in the embodiment includes forming an amorphous silicon layer aSi on a Base substrate. In some embodiments, the thickness of the amorphous silicon layer is in the range of about <NUM> to about <NUM>, e.g., about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, or about <NUM> to about <NUM>.

Various appropriate materials may be used for making the base substrate. Examples of materials suitable for making the base substrate include, but are not limited to, glass, quartz, polyimide, and polyester, etc. Optionally, the base substrate is a flexible base substrate (e.g., polyimide base substrate). Optionally, the base substrate is a relatively inflexible base substrate (e.g., a glass base substrate).

In some embodiments, prior to forming the amorphous silicon layer aSi, the method further includes a pre-cleaning step to remove contaminants from the surface of the base substrate prior to any subsequent step.

In some embodiments, prior to forming the amorphous silicon layer aSi, the method further includes forming a buffer layer (not shown in the figures) on the Base substrate. Optionally, the buffer layer is between the Base substrate and the amorphous silicon layer aSi, e.g., on a side of the amorphous silicon layer aSi proximal to the Base substrate. Various appropriate materials may be used for making the buffer layer. Examples of materials suitable for making the buffer layer include, but are not limited to, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. Optionally, the thickness of the buffer layer is in the range of about <NUM>Å to about <NUM>Å, e.g., about <NUM>Å to about <NUM>Å, about <NUM>Å to about <NUM>Å, or about <NUM>Å to about <NUM>Å.

In some embodiments, prior to forming the buffer layer, the method further includes forming an ancillary amorphous silicon layer (not shown in the figures) on the Base substrate. Optionally, the ancillary amorphous silicon layer is between the buffer layer and the Base substrate, e.g., on a side of the buffer layer proximal to the Base substrate. In some embodiments, the thickness of the ancillary amorphous silicon layer is in the range of about <NUM> to about <NUM>, e.g., about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, about <NUM> to about <NUM>, or about <NUM> to about <NUM>. The ancillary amorphous silicon layer absorbs heat released during a crystallization step (e.g., an excimer laser annealing step) of the amorphous silicon layer aSi, and prevent damages to the Base substrate during the crystallization step.

In some embodiments, the method further includes dehydrogenating the ancillary amorphous silicon layer. Optionally, the step of dehydrogenating the ancillary amorphous silicon layer is performed prior to the formation of the buffer layer on the ancillary amorphous silicon layer. Optionally, the step of dehydrogenating the ancillary amorphous silicon layer is performed subsequent to the formation of the buffer layer on the ancillary amorphous silicon layer but prior to the formation of amorphous silicon layer. The purpose of the dehydrogenation process is to reduce or eliminate hydrogen contents in the ancillary amorphous silicon layer. This prevents the occurrence of hydrogen explosion during the crystallization step. Optionally, the method includes, sequentially, forming an ancillary amorphous silicon layer on the Base substrate, forming a buffer layer on a side of the ancillary amorphous silicon layer distal to the Base substrate, dehydrogenating the ancillary amorphous silicon layer and the buffer layer, and forming an amorphous silicon layer on a side of the buffer layer distal to the ancillary amorphous silicon layer.

In some embodiments, the method further includes dehydrogenating the amorphous silicon layer aSi. Similarly, the purpose of the dehydrogenation process is to reduce or eliminate hydrogen contents in the amorphous silicon layer, and prevent the occurrence of hydrogen explosion during the crystallization step.

In some embodiments, the dehydrogenation step is performing using a thermal annealing method. The temperature for the thermal annealing process can be determined based on several factors, including the material used for making the Base substrate. For example, the thermal annealing temperature can be relatively higher when using a glass base substrate as compared to the thermal annealing temperature suitable for a flexible base substrate. Optionally, the thermal annealing is performed in a chamber having nitrogen gas as the ambient atmosphere. Optionally, the thermal annealing temperature is below <NUM> degree Celsius, e.g., in the range of about <NUM> degree Celsius to about <NUM> degree Celsius.

In some embodiments, the Base substrate is a relatively inflexible base substrate such as a glass substrate. Optionally, the method includes forming an amorphous silicon layer aSi on the Base substrate and dehydrogenating the amorphous silicon layer aSi. Optionally, the method includes forming a buffer layer on the Base substrate, forming an amorphous silicon layer aSi on a side of the buffer layer distal to the Base substrate, and dehydrogenating the amorphous silicon layer aSi.

In some embodiments, the Base substrate is a flexible base substrate such as a polyimide base substrate. Optionally, the method includes forming a flexible base substrate (e.g., a polyimide base substrate) on a glass substrate, forming an ancillary amorphous silicon layer on the flexible base substrate, forming a buffer layer (e.g., a buffer layer comprising a combination of silicon oxide and silicon nitride such as a stacked silicon oxide and silicon nitride bilayer) on a side of the ancillary amorphous silicon layer distal to the flexible base substrate, dehydrogenating the ancillary amorphous silicon layer, forming an amorphous silicon layer on a side of the buffer layer distal to the ancillary amorphous silicon layer. Optionally, the step of dehydrogenating the ancillary amorphous silicon layer is performed prior to the step of forming the buffer layer. Optionally, the step of dehydrogenating the ancillary amorphous silicon layer is performed subsequent to the step of forming the buffer layer.

Referring to <FIG> and <FIG>, according to the invention, the method further includes forming a first dopant layer CD (e.g., a channel doping ("CD") layer) having a first conductivity type comprising a first dopant on a side of the amorphous silicon layer aSi distal to the Base substrate. In some embodiments, the first dopant is a P-type dopant such as a Group IIIA element of the Periodic Table of the Elements including boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). In some embodiments, the first dopant is an N-type dopant such as a Group VA element of the Periodic Table of the Elements including nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi).

In some embodiments, the thin film transistor is an N-type thin film transistor and the first dopant is a P-type dopant. In some embodiments, the thin film transistor is an N-type thin film transistor and the first dopant is an N-type dopant. In some embodiments, the thin film transistor is an N-type thin film transistor, and the first dopant includes boron. In some embodiments, the thin film transistor is an N-type thin film transistor, and the first dopant includes one or both of phosphor and arsenic. In some embodiments, the thin film transistor is a P-type thin film transistor, and the first dopant includes one or both of phosphor and arsenic.

Various appropriate methods may be used to make the first dopant layer CD. Examples of appropriate methods include, but are not limited to, plasma enhanced chemical vapor deposition (PEVCD) and atomic layer deposition (ALD). Optionally, the first dopant layer CD is formed using the atomic layer deposition method. Various appropriate doping concentrations may be used for forming the first dopant layer. Optionally, the doping concentration is in the range of about <NUM> × <NUM><NUM> atom/cm<NUM> to <NUM> × <NUM><NUM> atom/cm<NUM>, e.g., about <NUM> × <NUM><NUM> atom/cm<NUM> to <NUM> × <NUM><NUM> atom/cm<NUM> or about <NUM> × <NUM><NUM> atom/cm<NUM> to <NUM> × <NUM><NUM> atom/cm<NUM>. Optionally, the first dopant layer CD is substantially a single atomic layer.

Referring to <FIG> and <FIG>, the method in some embodiments further includes forming a photoresist layer PR on a side of the first dopant layer CD distal to the amorphous silicon layer aSi. Optionally, the photoresist layer PR has a thickness in the range of about <NUM> to about <NUM>.

Referring to <FIG> and <FIG>, the method in some embodiments further includes exposing the photoresist layer PR with a half-tone mask plate or a gray-tone mask plate, and developing the exposed photoresist layer to obtain a photoresist pattern having a first section corresponding to a source electrode and a drain electrode of the thin film transistor, a second section corresponding to an active layer of the thin film transistor, and a third section outside of the first section and the second section, the photoresist material is removed in the third section (see, e.g., <FIG>). The first section is partially exposed, the second section is substantially unexposed, and the third section is fully exposed.

Subsequent to the removal of photoresist material in the third section, the method may further include removing the amorphous silicon layer aSi and the first dopant layer CD in the third section, thereby forming an amorphous silicon layer pattern corresponding to the active layer of the thin film transistor (see, e.g., <FIG>).

Referring to <FIG>, the method in some embodiments further includes removing (e.g., by ashing) the photoresist layer PR in the first section while maintaining the photoresist layer PR in the second section, thereby exposing the amorphous silicon layer aSi (and the residual first dopant layer CD) in the first section, as shown in <FIG> and <FIG>.

Referring to <FIG> and <FIG>, according to the invention, the method further includes forming a second dopant layer SDD (e.g., a source-drain doping ("SDD") layer) having a second conductivity type comprising a second dopant, on a side of the amorphous silicon layer aSi (and the residual first dopant layer) in the first section distal to the Base substrate and on a side of the remaining photoresist layer in the second section distal to the amorphous silicon layer aSi. In some embodiments, the thin film transistor is an N-type thin film transistor, and the second dopant is an N-type dopant such as a Group VA element of the Periodic Table of the Elements including nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). In some embodiments, the thin film transistor is a P-type thin film transistor, and the first dopant is a P-type dopant such as a Group IIIA element of the Periodic Table of the Elements including boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl).

In some embodiments, the thin film transistor is an N-type thin film transistor, and the second dopant includes one or both of phosphor and arsenic. Optionally, the second dopant layer includes phosphorous oxide, phosphorous nitride, or phosphorous oxynitride. Optionally, the second dopant layer includes arsenic oxide, arsenic nitride, or arsenic oxynitride. In some embodiments, the thin film transistor is a P-type thin film transistor, and the second dopant includes boron. Optionally, the second dopant layer includes boron oxide, boron nitride, or boron oxynitride.

Various appropriate methods may be used to make the second dopant layer SDD. Examples of appropriate methods include, but are not limited to, plasma enhanced chemical vapor deposition (PEVCD) and atomic layer deposition (ALD). Optionally, the second dopant layer SDD is formed using the atomic layer deposition method. Various appropriate doping concentrations may be used for forming the second dopant layer. Optionally, the doping concentration is in the range of about <NUM> × <NUM><NUM> atom/cm<NUM> to <NUM> × <NUM><NUM> atom/cm<NUM>, e.g., about <NUM> × <NUM><NUM> atom/cm<NUM> to <NUM> × <NUM><NUM> atom/cm<NUM> or about <NUM> × <NUM><NUM> atom/cm<NUM> to <NUM> × <NUM><NUM> atom/cm<NUM>. Optionally, the second dopant layer SDD is substantially a single atomic layer.

Referring to <FIG> an <FIG>, the method in some embodiments further includes removing the photoresist layer PR in the second section thereby exposing the first dopant layer CD in the second section. The second dopant layer SDD in the second section is also removed together with the removal of the photoresist layer PR in the second section. Various appropriate methods may be used to remove the photoresist layer PR in the second section. In some embodiments, the step of removing the photoresist layer PR in the second section is performed by stripping the photoresist layer PR in the second section. Optionally, the photoresist layer PR is stripping by ashing. Optionally, the photoresist layer PR is stripping by a lift-off method. For example, the photoresist layer PR may be subject to lift-off in a solvent, e.g., an organic solvent such as N-methylpyrrolidone (NMP). Optionally, the lift-off may be performed at a temperature, e.g., around <NUM> degree Celsius. Subsequent to the lift-off, the substrate is washed, e.g., using ethanol and dried. As shown in <FIG> an <FIG>, after the removal of the photoresist layer PR in the second section, the substrate includes a first dopant layer CD in the second section on a side of the amorphous silicon layer aSi distal to the Base substrate, and a second dopant layer SDD in the first section on a side of the amorphous silicon layer aSi (and the residual first dopant layer CD) distal to the Base substrate.

Referring to <FIG> and <FIG>, according to the invention, the method further includes crystallizing the amorphous silicon layer aSi (e.g., to form a polycrystalline silicon active layer). The crystallization step may be performed utilizing any appropriate crystallization method. In some embodiments, the crystallization step is performed utilizing a method selected from the group consisting of excimer laser annealing (ELA), solid phase crystallization (SPC), sequential lateral solidification (SLS), metal induced crystallization (MIC), and metal-induced lateral crystallization (MILC). Optionally, the crystallization step is performed using excimer laser annealing (as shown in <FIG> and <FIG>).

In some embodiments, the crystallizing step is performed at a low temperature, e.g., in a temperature range within which a flexible base substrate (e.g., a polyimide substrate) may be maintained substantially stable. Optionally, the crystallizing step is performed in a temperature range so that the temperature in the base substrate is kept below <NUM> degree Celsius, e.g., between about <NUM> degree Celsius and about <NUM> degree Celsius or between about <NUM> degree Celsius and about <NUM> degree Celsius or even lower.

In some embodiments, the crystallizing step is performed using excimer laser annealing. The excimer laser annealing is a method of fabricating a polycrystalline semiconductor layer at a low temperature. The excimer laser crystallizes an amorphous silicon layer by radiating a high energy laser beam onto the amorphous silicon layer for a time of tens of nanoseconds. The energy is substantially absorbed by the amorphous silicon layer, and consumed for phase transition of the amorphous silicon material. The amorphous silicon is melted and crystallized in a very short time period (e.g., during a laser pulse of about <NUM> ns to about <NUM> ns). The thermal effect of the excimer laser annealing is extremely localized, and may be limited within a depth of, e.g., about <NUM>, locally heating the amorphous silicon layer (e.g., heating limited within the amorphous silicon layer) to a temperature up to about <NUM> degree Celsius and converting the amorphous silicon into a polycrystalline form. The amount of heat transferred to the Base substrate is highly limited, e.g., the heat does not dissipate to the Base substrate so that the Base substrate is not damaged at all. By choosing appropriate laser wavelength and power, the method can be applied to melt and crystallize the amorphous silicon layer, without affecting the underlying base substrate.

Optionally, the excimer laser is one of a XeCl laser (e.g., a wavelength of <NUM>), ArF laser, KrF laser and XeF laser, i.e., the excimer laser annealing process is performed by using molecules of XeCl, ArF, KrF, or XeF. Optionally, the excimer laser annealing process is performed at a laser pulse frequency in the range of about <NUM> to about <NUM>, e.g., about <NUM> to about <NUM>, about <NUM> to about <NUM>, or about <NUM> to about <NUM>. Optionally, the excimer laser annealing process is performed at an overlapping ratio of about <NUM>% to about <NUM>%, e.g., about <NUM>% to about <NUM>%, about <NUM>% to about <NUM>%, about <NUM>% to about <NUM>%. Optionally, the excimer laser annealing process is performed at a laser pulse width less than <NUM> ns, e.g., about <NUM> ns to about <NUM> ns, about <NUM> ns to about <NUM> ns, or about <NUM> ns to about <NUM> ns. Optionally, the excimer laser annealing process is performed at a laser energy density of about <NUM> mJ/cm<NUM> to about <NUM> mJ/cm<NUM>, e.g., about <NUM> mJ/cm<NUM> to about <NUM> mJ/cm<NUM>, about <NUM> mJ/cm<NUM> to about <NUM> mJ/cm<NUM>, or about <NUM> mJ/cm<NUM> to about <NUM> mJ/cm<NUM>.

During the crystallization process (e.g., the excimer laser annealing process), the first dopant in the first dopant layer CD diffuses into the second section of the amorphous silicon layer aSi, and the second dopant in the second dopant layer SDD diffuses into the first section of the amorphous silicon layer aSi. At the same time, the amorphous silicon layer aSi melts and crystallizes into polycrystalline silicon.

Referring to <FIG>, the polycrystalline silicon active layer LTPS thus formed includes a second region <NUM> doped with a dopant of the first dopant layer and a first region <NUM> doped with a dopant of the second dopant layer. The first region includes a region 1a corresponding to a source electrode and a region 1b corresponding to a drain electrode.

Referring to <FIG> and <FIG>, according to the invention, the metho further includes forming a gate insulating layer GI on a side of the polycrystalline silicon active layer LTPS distal to the Base substrate. Any appropriate gate insulating materials and any appropriate fabricating methods may be used to make the gate insulating layer GI. For example, a gate insulating material may be deposited on the base substrate by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of appropriate gate insulating materials include, but are not limited to, silicon oxide (SiOy), silicon nitride (SiNy, e.g., Si<NUM>N<NUM>), silicon oxynitride (SiOxNy). Optionally, the gate insulating layer GI may have a single-layer structure or a stacked-layer structure including two or more sub-layers (e.g., a stacked-layer structure including a silicon oxide sublayer and a silicon nitride sublayer). Optionally, the gate insulating layer has a thickness in the range of about <NUM> to about <NUM>.

Referring to <FIG> and <FIG>, according to the invention, the method further includes forming a gate electrode layer GL on a side of the gate insulating layer GI distal to the polycrystalline silicon active layer LTPS. Any appropriate gate electrode materials and any appropriate fabricating methods may be used to make the gate electrode layer GL. For example, a gate electrode material may be deposited on the base substrate (e.g., by sputtering or vapor deposition); and patterned (e.g., by lithography such as a wet etching process) to form the gate electrode layer GL. Examples of appropriate gate electrode materials include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates containing the same. Optionally, the gate electrode layer may have a single-layer structure or a stacked-layer structure including two or more sub-layers. Optionally, the gate electrode layer has a thickness in the range of about <NUM> to about <NUM>.

Referring to <FIG> and <FIG>, the method in some embodiments further includes forming an interlayer dielectric layer ILD on a side of the gate electrode layer GL distal to the gate insulating layer GI. Any appropriate interlayer dielectric materials and any appropriate fabricating methods may be used to make the interlayer dielectric layer ILD. For example, an interlayer dielectric material may be deposited on the base substrate by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of appropriate interlayer dielectric materials include, but are not limited to, silicon oxide (SiOy), silicon nitride (SiNy, e.g., Si<NUM>N<NUM>), silicon oxynitride (SiOxNy). Optionally, the interlayer dielectric layer may have a single-layer structure or a stacked-layer structure including two or more sub-layers (e.g., a stacked-layer structure including a silicon oxide sublayer and a silicon nitride sublayer). Optionally, the interlayer dielectric layer ILD has a thickness in the range of about <NUM> to about <NUM>.

Referring to <FIG> and <FIG>, according to the invention, the method further includes forming a source via SV and a drain via DV in areas corresponding to the first region of the polycrystalline silicon active layer LTPS (e.g., region 1a and region 1b in <FIG>). The source via and the drain via extend through the interlayer dielectric layer ILD and the gate insulating layer GI, exposing the first region <NUM> of the polycrystalline silicon active layer LTPS (e.g., region 1a and region 1b in <FIG>).

Referring to <FIG> and <FIG>, according to the invention, the method further includes forming a source electrode S and a drain electrode D on a side of the interlayer dielectric layer ILD distal to the polycrystalline silicon active layer LTPS, the source electrode S extending through the source via SV and being in contact with the polycrystalline silicon active layer LTPS, the drain electrode D extending through the drain via DV and being in contact with the polycrystalline silicon active layer LTPS. Any appropriate source electrode and drain electrode materials and any appropriate fabricating methods may be used to make the source electrode S and the drain electrode D. For example, a source electrode and drain electrode material may be deposited on the base substrate (e.g., by sputtering or vapor deposition); and patterned (e.g., by lithography such as a wet etching process) to form the source electrode S and the drain electrode D. Examples of appropriate source electrode and drain electrode materials include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates containing the same. Optionally, the source electrode and the drain electrode may have a single-layer structure or a stacked-layer structure including two or more sub-layers.

<FIG> is a flow chart illustrating a fabricating process of a thin film transistor in some embodiments. Referring to <FIG>, the method of fabricating the thin film transistor in the embodiment include forming an ancillary amorphous silicon layer on the flexible base substrate; forming a buffer layer on a side of the ancillary amorphous silicon layer distal to the flexible base substrate; dehydrogenating the ancillary amorphous silicon layer; forming an amorphous silicon layer on a side of the buffer layer distal to the ancillary amorphous silicon layer; dehydrogenating the amorphous silicon layer; forming a first dopant layer on a side of the amorphous silicon layer distal to the base substrate; forming a photoresist layer on a side of the first dopant layer distal to the amorphous silicon layer; exposing the photoresist layer with a half-tone mask plate or a gray-tone mask plate, and developing the exposed photoresist layer to obtain a photoresist pattern having a first section corresponding to a source electrode and a drain electrode of the thin film transistor, a second section corresponding to an active layer of the thin film transistor, and a third section outside of the first section and the second section; the first section being partially exposed, the second section being substantially unexposed, the third section being fully exposed; and the photoresist material being removed in the third section; removing the amorphous silicon layer and the first dopant layer in the third section, thereby forming an amorphous silicon layer pattern corresponding to the active layer of the thin film transistor; removing the photoresist layer in the first section while maintaining the photoresist layer in the second section, thereby exposing the amorphous silicon layer in the first section; forming a second dopant layer on a side of the amorphous silicon layer in the first section distal to the base substrate and on a side of the photoresist layer in the second section distal to the amorphous silicon layer; removing the photoresist layer in the second section thereby exposing the first dopant layer in the second section; crystallizing the amorphous silicon layer thereby forming a polycrystalline silicon active layer having a first region doped with a dopant of the second dopant layer and a second region doped with a dopant of the first dopant layer, the first region corresponding to the source electrode and the drain electrode of the thin film transistor; and the second region corresponding to the channel region of the thin film transistor; forming a gate insulating layer on a side of the polycrystalline silicon active layer distal to the base substrate; forming a gate electrode layer on a side of the gate insulating layer distal to the polycrystalline silicon active layer; forming an interlayer dielectric layer on a side of the gate electrode layer distal to the gate insulating layer; forming a source via and a drain via in areas corresponding to the first region of the polycrystalline silicon active layer, the source via and the drain via extending through the interlayer dielectric layer and the gate insulating layer, exposing the first region of the polycrystalline silicon active layer; and forming a source electrode and a drain electrode in the source via and the drain via.

In some embodiments, the method further includes forming one or more layer (e.g., an ohmic contact layer) between the source electrode and the polycrystalline silicon active layer, and between the drain electrode and the polycrystalline silicon active layer. Optionally, the method further includes forming an ohmic contact layer between the source electrode and the polycrystalline silicon active layer. Optionally, the method further includes forming an ohmic contact layer between the drain electrode and the polycrystalline silicon active layer.

In another aspect not forming part of the claimed invention, the present disclosure provides a thin film transistor. In some examples, the thin film transistor includes a polycrystalline silicon active layer on a base substrate, a gate insulating layer on a side of the polycrystalline silicon active layer distal to the base substrate, a gate electrode layer on a side of the gate insulating layer distal to the polycrystalline silicon active layer, and a source electrode and a drain electrode on a side of the gate insulating layer distal to the polycrystalline silicon active layer, the source electrode and the drain electrode extending through the gate insulating layer and in contact with the polycrystalline silicon active layer. The polycrystalline silicon active layer includes a channel region and a source electrode and drain electrode contact region. The polycrystalline silicon active layer is in contact with the source electrode and the drain electrode in the source electrode and drain electrode contact region. The channel region is doped with a first dopant having a first conductivity, and the source electrode and drain electrode contact region is doped with a second dopant having a second conductivity.

In some examples, the source electrode and the drain electrode are in direct contact with the source electrode and drain electrode contact region. In some examples, the source electrode and the drain electrode are in contact with the source electrode and drain electrode contact region through one or more layers, e.g., an ohmic contact layer. Optionally, the thin film transistor further includes an ohmic contact layer between the source electrode and the polycrystalline silicon active layer. Optionally, the thin film transistor further includes an ohmic contact layer between the drain electrode and the polycrystalline silicon active layer.

Claim 1:
A method of fabricating a polycrystalline silicon thin film transistor, comprising:
forming an amorphous silicon layer (aSi) on a base substrate having a pattern corresponding to a polycrystalline silicon active layer (LTPS) of the thin film transistor, the amorphous silicon layer (aSi) having a first region (<NUM>) corresponding to a source electrode (S) and drain electrode contact region in the polycrystalline silicon active layer (LTPS) and a second region (<NUM>) corresponding to a channel region in the polycrystalline silicon active layer (LTPS);
forming a first dopant layer (CD) on a side of the second region (<NUM>) distal to the base substrate;
forming a second dopant layer (SDD) on a side of the first region (<NUM>) distal to the base substrate;
crystallizing the amorphous silicon layer (aSi) to form the polycrystalline silicon active layer (LTPS), a dopant of the first dopant layer (CD) diffusing into the second region (<NUM>) and a dopant of the second dopant layer (SDD) diffusing into the first region (<NUM>) during the step of crystallizing the amorphous silicon layer (aSi), wherein the first dopant layer (CD) is formed on a side of both the first region (<NUM>) and the second region (<NUM>) distal to the base substrate; and the polycrystalline silicon active layer (LTPS) in the first region (<NUM>) is doped with both the dopant of the first dopant layer (CD) and the dopant of the second dopant layer (SDD),
wherein after the step of crystallizing the amorphous silicon layer (aSi), the method further comprises:
forming a gate insulating layer (GI) on a side of the polycrystalline silicon active layer (LTPS) distal to the base substrate;
forming a gate electrode layer (GL) on a side of the gate insulating layer (GI) distal to the polycrystalline silicon active layer (LTPS);
forming a source via (SV) and a drain via (DV) in areas corresponding to the first region (<NUM>), the source via (SV) and the drain via (DV) extending through the gate insulating layer (GI), exposing the first region (<NUM>) of the polycrystalline silicon active layer (LTPS); and
forming a source electrode (S) and a drain electrode (D) on a side of the gate insulating layer (GI) distal to the base substrate, the source electrode (S) extending through the source via (SV) and in contact with the polycrystalline silicon active layer (LTPS), the drain electrode (D) extending through the drain via (DV) and in contact with the polycrystalline silicon active layer (LTPS).