Patent Description:
Increased use of Solid-State-Drives (SSD) in PCIe disk arrays in data center storage solutions has not only significantly reduced input/output (I/O) latency, but has also been able to alleviate I/O bottlenecks by providing a much higher I/O performance without the need for a large number of disk enclosures. However, given the extreme advances in performance, the performance of network controllers and other network devices has thus far lagged behind in handling the vastly increased I/O traffic.

To handle the controller bottleneck, an NVMe (Non-Volatile Memory Express) interface has been developed, which gains great advantages over the traditional SAS)/SATA interface (SAS = Serial Attached SCSI; SATA = Serial Advanced Technology Attachment) due to the direct PCIe connection between central processing unit CPU and the SSD, which leads to linearly scalable bandwidth and considerable reduction in latency. However, on the other hand, current NVMe implementations are too tightly coupled to CPUs such that failover of SSDs may cause problems. To loosen the prior art tight coupling between CPU and SSD, PCIe switches have been involved in the storage solution, which, not only natively extend the limited CPU PCIe bandwidth, but also isolate the SSD failure issue, at the cost of increased CPU to SSD latency.

To handle the network bottleneck for I/O performance, hyper convergence has become the new trend for data center infrastructure. Comparing to the traditional centralized storage, such as SAN (Storage Area Network), where the storage pool as a whole is accessed by hosts via a network, hyper convergence is basically a distributed storage platform, implemented by natively integrating the compute and storage components together as a node, and aggregating nodes into cluster. Hyper convergence fully utilizes the localized I/O operation within a node, which significantly offloads the network traffic. However, there remains heavy traffic on the node-to-node network due to the distributed storage requirement, such as data replica and synchronization.

<CIT> (also published as <CIT>) discloses a system for switching between a high performance mode and dual path mode. The system includes a switch configured to receive control signals, and in response causing the switch to selectively couple one or more first lanes of a first device or one or more second lanes of a second device to third lanes of a third device to yield enabled lanes. <CIT> discloses a method on which, based on determining that a first set of signal carriers for transmitting a first set of respective lane signals is faulty and identifying that a second set of signal carriers for transmitting a seond set of respective lane signals is not faulty, one or more of the first set of lane signals may be routed from the first set of signal carriers through a first subset of the second set of signal carriers, the routing of the one or more of the first set of lane signals may cause a bandwidth capacity to increase to a highest available bandwidth.

Various embodiments of the present disclosure relate to dynamically partitioning of PCIe disk arrays based on software configuration / policy distribution. The basic idea is to provide redundant PCIe links in the form of multiplexers connected between the downstream ports of switches SW0, SW1 and the Non-Volatile Memory Express (NVMe) Solid-State Drives (SSD), which can be switched dynamically according to a detected switch or SSD failure status and/or application policy/requirement. As used herein, the term "on the fly" and "dynamically" in the context of this disclosure describes activities or events that develop or occur, for example, while the process that the switch-over affects is ongoing, rather than as the result of something that is statically predefined. More particularly, the terms "hot swapping", "hot-add" and "hot-remove" refer to "on-the-fly" replacement of computer hardware, such as the described NVMe SSDs.

As will be appreciated by one skilled in the art, aspects of the present disclosure, in particular the functionality related to various aspects of dynamic partitioning of PCIe disk arrays, may be controlled by computer programs. Accordingly, other aspects of the present disclosure relate to systems, computer programs, mechanisms, and means for carrying out the methods according to various embodiments described herein. Such systems, computer programs, mechanisms, and means could be included within various network devices, such as e.g. the management platform and the hypervisor. A computer program may, for example, be downloaded (updated) to the existing network devices and systems (e.g. to the existing routers, switches, various control nodes, etc.) or be stored upon manufacturing of these devices and.

These and other features of the disclosure will become more fully apparent from the following description and appended claims, or can be easily learned by the practice of the principles set forth herein.

One interconnect fabric architecture includes the Peripheral Component Interconnect Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. PCIe is a high performance, general purpose I/O interconnects defined for a wide variety of future computing and communication platforms. Some PCIe attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The more recent versions of PCIe take advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality of Service (QoS), Hot-Plug/Hot- Swap support, Data Integrity, and Error Handling are among some of the advanced features supported by PCI Express.

Disadvantageously, however, much of the conventional switch-based technology with single x4 NMVe SSD does not have switch level redundancy that is required in high reliable storage products. To overcome this, the dual x2 port NVMe SSDs are designed which could be connected to <NUM> switches to gain redundancy. The connections between switch and SSDs are fixed in all the conventional methodology, and do not allow switch-over between dual-port mode and single-port mode on-the fly based on policy. The design proposed and illustrated in various embodiments of the present disclosure attempts to alleviate these shortcomings.

<FIG> illustrate basic topologies for connecting a CPU and NVMe SSDs via interposed PCIe switches. <FIG> shows a topology with only a single CPU and a single switch SW0. For a larger number of SSDs, the topologies may be extended in either a parallel arrangement, as illustrated in <FIG>, with two switches SW0, SW1 having their respective input connected to a single CPU, or in a cascaded arrangement with two levels of switches, wherein switch SW0 in an upper level has an input connected to a single CPU and lower level switches SW1, SW2,. SWn connected between switch SW0 and the NVMe SSDs, as illustrated in <FIG>. In all these three topologies of <FIG>, the SSDs operate in x4 PCIe mode and the connections between the CPU and the SSDs are fixed or hard-wired, which deprives these topologies of flexibility and reduces the reliability of this type of storage solution.

Redundancy at the CPU level (CPU redundancy) could be achieved by combining MR-IOV (Multiple Root I/O Virtualization) feature of the exemplary switches SW0 and SW1 and the NVMe SSD's dual-port feature, wherein two CPUs would be connected to the upstream (US) ports of switch SW0 of the topology in <FIG>, allowing each CPU to be switched to any of the NVMe SSDs. This topology is illustrated in <FIG>. Meanwhile, switch level redundancy could be implemented as shown in <FIG>, wherein the downstream (DS) ports of each switch SW0 and SW1 could be connected to any of the NVMe SSDs. This will be referred to as switch redundancy. The two switches SW0 and SW1 could work in either active/active or active/passive mode, depending on application and CPU's I/O bandwidth requirement. CPU redundancy and switch redundancy may advantageously be combined to provide double-redundancy, both at the CPU level and at the switch level, which is illustrated with CPUO and CPU1, and switches SW0 and SW1 in <FIG>.

As mentioned above, the aforementioned topologies having either CPU redundancy or switch redundancy, or both, without forcing NMVe SSDs to work in dual 2x port mode to facilitate the redundant connection. There are also circumstances where flexibility is required to swap NVMe SSDs between dual-port and single-port mode on-the fly. The proposed design attempts to achieve providing redundancy without limiting the SSDs type that could be used in the storage system.

The top level design of a proposed NVMe SSD interface architecture <NUM> is illustrated in <FIG>. Considering the tradeoff between redundancy and switch port resources, a two-switch design may be an optimal choice. The basic idea is to provide redundant PCIe links between switches SW0, SW1 and the NVMe SSDs, which could be switched according to a detected switch or SSD failure status and/or application policy/requirement. The design has a total of four distinct components, namely switches; a hardware control logic device shown here exemplary as a FPGA (field-programmable gate array); NVMe SSDs connected at an <NUM> drive backplane connector; and the upper level management platform, such as the Cisco UCSM (Unified Computing System Manager) in the present example.

The <NUM> drive backplane connector is a <NUM>-pin connector and designed to support PCI Express as well as hot-plug and hot-remove, both with and without prior system notification (surprise hot-remove).

The PCIe signal in the data plane (double arrows) and its reference clock in the clock plane (dashed lines), side band signals (includes Dual-Port Enable DUALPORTEN# / Interface Detect IFDET# / Hot-Plug Detect PRSNT# / PCIe device reset PERST# / Power Enable PWREN) in the control plane are necessary to facilitate all the SSD operation timing control and are assigned to specific pins on the <NUM> connector. The control plane signals are connected, either directly or indirectly on the FPGA to the Expander_SW1and Expander_SW2. The signal EN is an enable signal.

The present disclosure addresses only the traffic in the data plane between the downstream ports of switches SW0, SW1 and the NVMe SSDs. For the connection between the upstream ports of the switches SW0, SW1 and one or more CPUs, any of the topologies illustrated in <FIG> and the redundant topology illustrated in <FIG> could be used. In other words, the connectivity of the downstream ports to the NVMe SSDs is not affected by the topology of the upstream ports. It will be understood that the number of illustrated CPUs, switches and NVMe SSDs are merely examples and any number of such devices can be used that can be interconnected and addressed in the manner described.

The hardware control logic device, herein also referred to simply as FPGA, deals with all the control logic such as SSD information collection and reporting, policy execution and optional indicator light (LED) management. The management platform interfaces between hypervisor and FPGA and collects SSD information and delivers an application requirement in the form of policy.

The virtual channel connecting the FPGA to the management platform could be implemented via multiple ways, for example Ethernet. To support both single port and dual port mode for the NVMe, the system must be able to modify the bifurcation of the downstream ports of the switches SW0, SW1 on the fly. The term "on the fly" in the context of this disclosure describes activities or events that develop or occur dynamically, i.e. while the process that the switch-over affects is ongoing, rather than as the result of something that is statically predefined. More particularly, the term "hot swapping" refers to "on-the-fly" replacement of computer hardware, such as the described NVMe SSDs. This is accomplished by sending a reconfiguration command to switch the ASIC (application-specific integrated circuit) itself (MRPC = multicast remote procedure call command in PMC PCIe switch). The connection of the switches SW0, SW1 to a <NUM>:<NUM> PCIe multiplexer (PCIe MUX) is implemented downstream of PCIe port switching to gain redundancy regardless of whether single x4 SSD or dual x2 SSD are attached. This on the fly switching is based on policy or software configuration.

All valid SSD configurations for a two-switch redundant situation are summarized in Table <NUM>.

In top design diagram of the NVMe SSD interface architecture <NUM> shown in <FIG>, two CPUs CPUO and CPU1 are each connected to respective upstream (US) ports of switches SW0, SW1. Note that there is no connection between CPUO and SW1 and between CPU1 and SW0. Downstream (DS) ports of each switch are connected for data transfer to respective input ports of each of two <NUM>:<NUM> PCIe multiplexers (MUX) <NUM>, <NUM>, i.e. each CPU can transfer data to and receive data from each of the MUXs <NUM>, <NUM>. DUALPORTEN# is disabled (low = <NUM>) so that the NVMe SSD operates in x2 mode. In <FIG>, the input ports of each of the MUXs <NUM>, <NUM> are connected in x2 mode to a respective PCIe terminal, namely PCIe [<NUM>:<NUM>] and PCIe [<NUM>:<NUM>], on the <NUM> connector and from there to unillustrated NVMe SSDs. The possible data links depend on the switch selections and the corresponding work states in x2 mode are listed in Table <NUM> as W1 - W4.

Note that not all components of the FPGA are shown in <FIG>, and reference is made to <FIG> for any component not shown in <FIG>.

For an easier understanding of the top design diagram of the NVMe SSD interface architecture <NUM> in <FIG>, reference is now made to the exemplary system <NUM> illustrated in <FIG> which uses only a single multiplexer <NUM>. It will be assumed that DUALPORTEN# is enabled (high = <NUM>) so that the unillustrated NVMe SSD connected to terminals PCIe[<NUM>:<NUM>] on the <NUM> connector operates in x4 mode (x4 PCIe). The traffic in the data plane could then only be swapped between Work State W5 and Work State W6 in Table <NUM>. Only one MUX <NUM> is used in this example. Both switch select signals SW_SEL_0 and SW_SEL_1 are selectively applied to MUX <NUM>. The two LEDs (red LED; blue LED) shown in <FIG> are status indicators and have no bearing on the operation of the system <NUM>.

The I<NUM>C GPIO Expanders shown in <FIG> are general-purpose input/output (GPIO) expanders that can be used via the I<NUM>C interface (I<NUM>C=Inter-Integrated Circuit) and allow more than one device to connect to a single port on a computer.

In a first Work State W5, the REF_CLK_P0 is enabled (=<NUM>) at the pinout of the <NUM> connector, whereas the REF_CLK_P1 is disabled (not used). The I2C GPIO Expander SW0 on the FPGA is high = <NUM>, whereas the I2C GPIO Expander SW1 on the FPGA is low = <NUM>. With both the SW_SEL_0 and the SW_SEL_1 low (= <NUM>) in Work State W5, the <NUM>-port (x4) PCIe [<NUM>:<NUM>] on the <NUM> connector is connected to the NVMe SSD by way of switch SW0. PE_RST_P0 is signaling SW0, whereas PE_RST_P1 is not connected in <FIG> because the second <NUM>:<NUM> RST MUX is not used in this configuration. Likewise, the second <NUM>:<NUM> PCIe MUX <NUM> and the second <NUM>:<NUM> CLK MUX of <FIG> are also not used in <FIG> since SW1 is not addressed in Work State W5. The aforedescribed situation for the x4 Work State W5 is substantially equivalent to the Work State W1, where SW_SEL_0 = SW_SEL_1 = <NUM> and DUALPORTEN# is disabled.

In a second Work State W6, the REF_CLK_P0 is enabled at the pinout of the <NUM> connector, whereas the REF_CLK_P1 is disabled (not used). The I2C GPIO Expander SW0 on the FPGA is high = <NUM>, whereas the I2C GPIO Expander SW1 on the FPGA is low = <NUM>. With both the SW_SEL_0 and the SW_SEL_1 high (=<NUM>) in Work State W6, the <NUM>-port (x4) PCIe [<NUM>:<NUM>] on the <NUM> connector is connected to the NVMe SSD by way of switch SW1. PE_RST_P0 is signaling SW1, whereas PE_RST_P1 is not connected in <FIG> because as above, the second <NUM>:<NUM> RST Mux is not used in this configuration. Likewise, the second <NUM>:<NUM> PCIe Mux and the second <NUM>:<NUM> CLK Mux of <FIG> are also not used in <FIG> since SW0 is not addressed in Work State W6. The aforedescribed situation for the x4 Work State W5 is substantially equivalent to the Work State W1, where SW_SEL_0 = SW_SEL_1 = <NUM> and DUALPORTEN# is disabled. To summarize, the x4 PCIe bus from SW0 and the x4 PCIe bus from SW1 are selectively, but never simultaneously, connected via the <NUM>:<NUM> PCI2 Mux to the x4 PCIe bus terminating at the connector <NUM> at the PCIe[<NUM>:<NUM>] pin, and ultimately connected to a NVMe SSD (not shown).

As mentioned above with reference to <FIG>, the other four valid Work States W1 - W4 all employ two x2 ports instead of a single x4 port. The Work States W1 and W2 have been discussed above due to their similarity with the Work States W5 and W6. For the Work States W3 and W4, both Ref_CLK_P0 and Ref CLK_P1 are high and either SW_SEL_0 or SW_SEL_1 is high, while the other is low. This selects port <NUM> from SW0 and port <NUM> from SW1 for Work State W5 and port <NUM> from SW0 and port <NUM> from SW1 for Work State W5. Switching between these Work States W1- W6 is schematically depicted in <FIG>.

Among all the possible work state transitions illustrated in <FIG>, the following three examples are intended to demonstrate some of the benefits of this design.

Take into consideration the variant application I/O operation styles from high-bandwidth single-stream to lower bandwidth multiple-stream, storage virtualization platform needs to provide the flexibility to swap between them, and the transition from Work State_W5 to Work State_W1 facilitates the virtualization stack to make the best use of SSD's high capability for parallel I/O operation.

This transition could be utilized to implement switch level traffic offload. In one scenario where the upstream port of SW0 is suffering a traffic jam, half of its downstream SSDs could then be re-directed to SW1 to thus significantly improve the overall I/O data flow speed. This transition provides the possibility for a balanced storage load.

The most common application scenario for this transition is a switch failover. Assume, for example, that SW0 has failed. Data loss could then be avoided by migrating all traffic to and from the downstream port of SW0 to SW1. Since this redundancy is implemented in x4 single-port mode, no I/O performance loss occurs due to dual-port operation.

Another application could apply to a switch arrangement where each switch in <FIG> is connected to a single CPU, i.e. connections between CPUO and SW1 and between CPU1 and SW0 would not exist. In case that large amount of cold data, i.e. data that are rarely accessed, needs to be transported from CPUO to CPU1, e.g. when a new node is added into the current distributed storage network, copies of user data need to be delivered from the current nodes to this new node. The traditional solution would involve a communication network between the two CPUs CPU0, CPU1, resulting in a heavy traffic load. With aforedescribed exemplary design illustrated for example in <FIG>, CPUO could first clone of all the required data onto one NVMe SSD and thereafter migrate this NVMe SSD to CPU1 as a whole. In other words, the inner-CPU bandwidth (making a clone SSD within one node) is utilized, thus saving inter-CPU network bandwidth cost.

The operation during hot-add of a NVMe SSD will now be described with reference to a process flow chart shown in <FIG>.

Before any hot-swap, the system must be powered on and the firmware loaded. The FPGA will disable all I2C GPIO expander interfaces between switches SW0, SW1 and the NVMe SSDs before the NVMe SSDs can be successfully detected and configured.

The switches SW0, SW1 need to enable the dynamic bifurcation and dynamic partition feature during initialization. A switch should also reserve a sufficient number of logic P2P (PCIe-to-PCIe) bridges for the physical downstream (DS) ports. For each stack, all the DS ports would then be configured in x2 granularity. A <NUM> x2 port could be combined to work as a <NUM> x4 port through a configuration command as the policy is distributed downwards. During enumeration, each logic P2P bridge will be assigned its own primary/ secondary/ subordinate bus number. This is task of the root complex which connects the processor and memory subsystem to the PCI Express switch fabric composed of one or more switch devices.

For a cascaded switch similar to the arrangement of Topology (c) in <FIG>, the top level SW's execute enumeration. In the context of this disclosure, the disclosed process relates only to the bottom switches that directly interface with the NVMe SSDs.

<FIG> shows schematically a process <NUM> for hot adding an NVMe SSD. The process <NUM> starts at <NUM>. The FPGA is first to sense the toggle of IFDET# indicating a new inserted NVMe SSD, at <NUM>. Triggered by this toggle, the FPGA will then poll the SSD E2PROM content and report the content to the Management Platform.

Typically, users will assign one specific application policy for this SSD via the Management Platform, with the Management Platform delivering the latest policy to FPGA. This may be a default configuration policy or a configuration policy updated for example by a user in response to an application update.

The FPGA needs to configure all the MUX devices in <FIG> and <FIG> according to the policy. The I2C GPIO expander interface will only be enabled after all the configurations have been successfully executed.

At <NUM>, the switch reads the asserted IFDET# and the DUALPORTEN# of the SSD. The switch will then configure the bifurcation as x2, as in the example of <FIG>, or as x4, as in the example of <FIG>, commensurate with the DUALPORTEN# signal status, at step <NUM>. Thereafter, at <NUM>, the switch powers the SSD on, de-asserts PERST#, and initiates the PCIe link training procedure to enter the normal operating mode.

<FIG> illustrates a process <NUM> for a surprise SSD hot remove. When SSD remove is initiated, at step <NUM>, the loss of the de-asserted IFDET# signal is reported to the FPGA, at <NUM>, which will automatically disable the I2C GPIO expander interface to the switch, at <NUM>. Detection of the link loss, at <NUM>, will clear the SSD configuration space, at <NUM>, whereafter the complete hot-remove procedure specified by the vendor of the SSD can be performed, at <NUM>. Hot remove may also be triggered by the loss of a PCIe link. When the hot-remove process is concluded, the switch sends a hot-remove-done flag to the FPGA, at <NUM>.

The SSD configuration policy may be modified on-the-fly according to a changed application requirement. The associated process <NUM> will now be described with reference to the flow diagram in <FIG>.

At <NUM>, the configuration policy for the SSD is updated based on an application update. Specifically, this is done by performing at least some of the steps of the hot-remove process described in <FIG> (see process <NUM> in <FIG>), although the NVMe SSD will actually not have to be removed physically, meaning that the PCIe link may still be active. The switch then informs the FPGA when the hot remove process is finished, at <NUM>, and sets a flag. In one example, the switch may activate a blinking light (not shown) during the hot-remove process and then stop blinking when the hot-remove process is terminated. Details of the hot-remove process are not part of this disclosure and are typically specified by the vendor of the switch. The FPGA will configure the updated DUALPORTEN# and the SW_SEL_0/<NUM> signals according to the new policy (see Table <NUM>) after receiving the hot-remove-done signal, at <NUM>. When the reconfiguration is done, FPGA will assert a FPGA_CONFG_DONE signal. The switch can then re-bifurcate its downstream ports and re-train the PCIe link, at <NUM>. The process <NUM> does not need to be performed when a SSD is hot-added (see process <NUM> in <FIG>).

The disclosed embodiments represent a consolidated solution to flexibly and dynamically modify the connection between NVMe SSD and PCIe switch in x2-port granularity on-the-fly. According to some embodiments of the disclosure, one NVMe SSD may be connected to either a single switch in one x4-port mode/two x2-port mode, or to two switches in x2-port mode. These different connections scenarios may then be swapped dynamically without requiring administrator intervention.

This flexibility is implemented by swapping NVMe SSD work mode (between dual-port and single-port) and adapting the switches' downstream partition policy sequentially based on specific timing requirement.

With this flexibility, the virtualization stack now obtains one more degree of freedom to schedule its I/O traffic in a more balanced and efficient way. Besides that, the switch level redundancy is natively realized in single-port mode without the cost of I/O performance loss due to dual-port operation.

In summary, these exemplary embodiments may provide at least the following advantages:.

In summary, the disclosure relates to methods and systems for dynamically partitioning of PCIe disk arrays based on software configuration / policy distribution. In one embodiment, at least one PCIe switch has an input port operatively connected to a respective CPU and at least one output port. A multiplexer is connected between the output port(s) of the at least one PCIe switch and a PCIe disk array, for example an NVMe SSD, and is configured to connect the PCIe disk array in a first configuration to a single PCIe switch in either one x4 port or two x2 port mode, or in a second configuration to two PCIe switches in x2 port mode. The multiplexer can dynamically switch between the first configuration and the second configuration on the fly. Switching can occur, for example, in response to a hot-swap of an NVMe SSD or a policy change.

The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.

Instructions used to program logic to perform embodiments of the invention may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

Claim 1:
An apparatus comprising:
at least two Peripheral Component Interconnect Express, PCIe, switches, each having an input port operatively connected to a respective CPU and at least one output port;
at least one multiplexer (<NUM>, <NUM>) connected between the at least one output port of each of the at least two PCIe switches and a PCIe disk array, the at least one multiplexer (<NUM>, <NUM>) configured to alternate a connection of the PCIe disk array between a first configuration and a second configuration in response to a change in a configuration policy of the PCIe disk array, a hot-add surprise addition of a PCIe disk array without prior system notification, or a hot-remove surprise removal of a PCIe disk array without prior system notification, wherein in the first configuration the at least one multiplexer (<NUM>, <NUM>) is connected to a single PCIe switch of the at least two PCIe switches in one x4 port mode or two x2 port mode, wherein in the second configuration the at least one multiplexer (<NUM>, <NUM>) is connected to two PCIe switches of the at least two PCIe switches in x2 port mode, the at least one multiplexer (<NUM>, <NUM>) being configured to dynamically effect a switch-over between the first configuration and the second configuration in response to the change; and
a control logic device operatively connected to the at least two PCIe switches and the at least one multiplexer (<NUM>, <NUM>) and configured to monitor PCIe disk array information to determine whether a hot-add surprise addition or a hot-remove surprise removal of a PCIe disk array has occurred and PCIe disk array configuration policy execution and to control the at least one multiplexer (<NUM>, <NUM>) to switch between the first and second configurations in response to the monitoring.