Patent Description:
Generally, in a semiconductor integrated circuit, wirings configuring a wiring network (hereinafter referred to as the same net) through which the same signal is transmitted have a wiring shape designed to have the same wiring width. Furthermore, conventionally, wirings that have been attempted to be variously optimized have been proposed.

For example, Patent Document <NUM> proposes a wiring layout that minimizes a wiring delay by performing optimization in consideration of a wiring interval. Furthermore, Patent Document <NUM> proposes a clock wiring method for reducing clock skew by adjusting a length of adjacent wirings and non-uniformity of a wiring capacity due to intersection of interlayer wirings.

<CIT> discloses a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line that has a first line width and is arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line that has a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width is directly proportional to a first current level for the first clock line and the second line width is directly proportional to a second current level for the second clock line.

<CIT> discloses a first wire that has sidewalls of an integrated circuit and that is tapered from a proximal end to a distal end to reduce width from a first width to a second width. A second wire is spaced apart from the first wire and has sidewalls. The first wire and the second wire are each horizontally disposed alongside each other and form a part of a sidewall capacitor between facing sidewalls. The sidewall capacitor capacitance is progressively reduced responsive to the first wire taper.

<CIT> discloses a functional block that is divided into a plurality of regions. In each region, a clock main line that extends along a first direction, a clock branch line group that includes a plurality of clock branch lines that extend along a second direction perpendicular to the first direction and that are electrically connected to the clock main line, a clock driving cell that is electrically connected to the clock main line and a clock synchronous cell group that includes a plurality of clock synchronous cells that are electrically connected to the clock main line or the clock branch line group are provided. The clock branch line groups of the respective regions are electrically separated from each other, and the clock driving cell singly drives the clock main line that is connected thereto and the clock branch line group that is connected to the clock main line.

By the way, even in the same net, a variation in a current density occurs on one wiring, such that performance might be deteriorated in the wiring shape having the same wiring width. For example, in a case where the same wiring width is designed to be large, the performance is deteriorated in terms of power consumption, speed or the like due to an unnecessary wiring capacity.

Note that since the wiring layout proposed in Patent Document <NUM> described above is not a technology related to the same net and the clock wiring method proposed in Patent Document <NUM> is not a technology related to a wiring shape, such a problem could not be solved.

Therefore, it has been required to avoid the deterioration of the performance occurring in the conventional wiring shape, optimize the wiring shape in the same net, and improve performance of the semiconductor integrated circuit.

The present disclosure has been made in view of such a situation, and an object of the present disclosure is to be capable of further improving performance.

According to a first aspect, the present invention provides a semiconductor integrated circuit in accordance with independent claim <NUM>. According to a second aspect, the present invention provides an electronic apparatus in accordance with claim <NUM>. Further aspects are set forth in the dependent claims, the drawings and the following description.

A semiconductor integrated circuit according to one aspect of the present disclosure includes: a wiring that forms a transmission network through which the same signal is transmitted; and a driver that supplies the signal to the wiring, in which the wiring has a wiring shape set according to a distance from the driver or a frequency of the signal.

An electronic apparatus according to one aspect of the present disclosure includes: a semiconductor integrated circuit that includes: a wiring that forms a transmission network through which the same signal is transmitted; and a driver that supplies the signal to the wiring, in which the wiring has a wiring shape set according to a distance from the driver or a frequency of the signal.

In one aspect of the present disclosure, a wiring that forms a transmission network through which the same signal is transmitted has a wiring shape set according to a distance from a driver that supplies the signal to the wiring or a frequency of the signal.

According to one aspect of the present disclosure, it is possible to further improve the performance.

Note that an effect described here is not necessarily limited, and may be any effect described in the present disclosure.

Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

A first embodiment of a wiring shape used in a semiconductor integrated circuit to which the present technology is applied will be described with reference to <FIG>.

<FIG> illustrates a circuit diagram of a clock wiring to which the present technology is applied.

In a clock wiring <NUM> illustrated in <FIG>, signal lines of the same net are designed so that clock signals output from a clock generation circuit (not illustrated) are supplied to a driver <NUM> via buffers <NUM>-<NUM> and <NUM>-<NUM> and are supplied from the driver <NUM> to a plurality of receivers <NUM>. In an example illustrated in <FIG>, a wiring shape of the clock wiring <NUM> is designed so that the signal lines are branched from an output terminal of the driver <NUM> and are connected to input terminals of nine receivers <NUM>-<NUM> to <NUM>-<NUM>. Then, drive elements <NUM>-<NUM> to <NUM>-<NUM> that drive according to the clock signal are connected to the receivers <NUM>-<NUM> to <NUM>-<NUM>, respectively.

In such a clock wiring <NUM>, a special wiring shape is often used, and for example, a so-called fishbone wiring shape as illustrated in <FIG> and <FIG> is used.

<FIG> is a layout diagram illustrating a conventional wiring shape based on the circuit diagram illustrated in <FIG>.

A clock wiring <NUM> illustrated in <FIG> has a fishbone wiring shape in which a trunk line <NUM>, which is a signal line having a large wiring width, is connected to an output terminal of a driver <NUM> and branch lines <NUM>, which are a plurality of signal lines having a small wiring width, are connected to the trunk line <NUM> so as to be branched from the trunk line <NUM>. In an example illustrated in <FIG>, five branch lines <NUM>-<NUM> to <NUM>-<NUM> are connected to the trunk line <NUM>.

Furthermore, in the clock wiring <NUM>, connection terminals <NUM>-<NUM> to <NUM>-<NUM> connected to the receivers <NUM>-<NUM> to <NUM>-<NUM> of <FIG> are provided on the branch lines <NUM>-<NUM> to <NUM>-<NUM>. Furthermore, connection terminals <NUM>-<NUM> and <NUM>-<NUM> are also provided between a buffer <NUM> and the driver <NUM>.

Then, conventionally, in such a clock wiring <NUM>, the trunk line <NUM> and the branch line <NUM> are designed so that wiring widths are constant.

<FIG> illustrates a layout diagram illustrating a wiring shape to which the present technology is applied, based on the circuit diagram illustrated in <FIG>.

A clock wiring <NUM> illustrated in <FIG> has a fishbone wiring shape in which five branch lines <NUM>-<NUM> and <NUM>-<NUM> having a small wiring width are connected to a trunk line <NUM> having a large wiring width so as to be branched from the trunk line <NUM>, similar to the clock wiring <NUM> of <FIG>. Note that the clock wiring <NUM> of <FIG> has a layout in which the trunk line <NUM> is arranged along a vertical direction of a semiconductor integrated circuit.

Then, in the clock wiring <NUM>, an output terminal of the driver <NUM> is connected to the center of the trunk line <NUM>, and the trunk line <NUM> has a wiring shape set so that a wiring width becomes smaller according to a distance from a connection portion of the driver <NUM> to upper and lower sides of the trunk line <NUM> in the vertical direction. That is, since a current density of a signal transmitted via the trunk line <NUM> decreases as a distance from the driver <NUM> increases, the wiring shape of the trunk line <NUM> is set so that the wiring width corresponds to the decrease in the current density.

Note that since the decrease in the current density changes not only according to the number of receivers, or the like, as well as the distance from the driver <NUM>, it is preferable to form the trunk line <NUM> of which wiring width becomes smaller so as to be optimized according to the current density of the signal transmitted via the trunk line <NUM>.

<FIG> enlarges and illustrates an area surrounded by a broken line in <FIG>.

The branch lines <NUM>-<NUM> and <NUM>-<NUM> illustrated in <FIG> have wiring shapes set so that wiring widths become smaller according to distances from branch portions with the trunk line <NUM> to the right in a horizontal direction, that is, as distances from the driver <NUM> increase, similar to the trunk line <NUM>. Of course, although not illustrated, the branch lines <NUM>-<NUM> and <NUM>-<NUM> extending from the trunk line <NUM> to the left also have wiring shapes set so that wiring widths become smaller according to distances from branch portions, and the same applies to the branch lines <NUM>-<NUM> to <NUM>-<NUM>.

As such, in the clock wiring <NUM>, the trunk line <NUM> and the branch line <NUM> have the wiring shapes designed so that the wiring widths become smaller as the distances from the driver <NUM> increase. Then, in the clock wiring <NUM>, a wiring property can be improved by optimizing the wiring widths of the trunk line <NUM> and the branch line <NUM>. Therefore, the clock wiring <NUM> can reduce, for example, an unnecessary wiring capacity, and can avoid deterioration in performance in terms of power consumption, speed, or the like. Furthermore, in a case where the receiver <NUM> that receives a signal is a complementary metal oxide semiconductor (CMOS), it is preferable to narrow the wiring widths of the trunk line <NUM> and the branch line <NUM> so as to suppress reflection at end portions of the trunk line <NUM> and the branch line <NUM>.

As a result, performance of the semiconductor integrated circuit including the clock wiring <NUM> can be improved. For example, in accordance with a reduction in a wiring capacity in the clock wiring <NUM>, a size of the driver <NUM> can be reduced, such that further power reduction becomes possible. In particular, in a case where the clock wiring <NUM> adopts the fishbone wiring shape, such an effect can be obtained well.

<FIG> illustrates a layout diagram illustrating a wiring shape to which the present technology is applied, based on the circuit diagram illustrated in <FIG>, similar to <FIG>. Furthermore, <FIG> enlarges and illustrates an area surrounded by a broken line in <FIG>, similar to <FIG>.

A clock wiring <NUM> illustrated in <FIG> and <FIG> has a layout in which a trunk line <NUM> to which the driver <NUM> is connected is arranged along the horizontal direction of the semiconductor integrated circuit.

Then, as illustrated in <FIG>, in the clock wiring <NUM>, similar to the clock wiring <NUM> of <FIG>, the trunk line <NUM> to which the driver <NUM> is connected has a wiring shape set so that a wiring width becomes smaller according to a distance from a connection portion of the driver <NUM> to the left and right in the horizontal direction. Furthermore, as illustrated in <FIG>, a branch line <NUM> branching from the trunk line <NUM> has a wiring shape set so that a wiring width becomes smaller according to a distance from a branch portion with the trunk line <NUM> to a lower side in the vertical direction, that is, as a distance from the driver <NUM> increases.

In the clock wiring <NUM> having such a wiring shape, similar to the clock wiring <NUM> of <FIG>, better performance can be obtained by optimizing the wiring widths of the trunk line <NUM> and the branch line <NUM>.

<FIG> illustrates a specific wiring shape of the clock wiring <NUM> described with reference to <FIG>.

In the clock wiring <NUM> illustrated in <FIG>, the driver <NUM> is arranged at the center of gravity of the plurality of receivers <NUM> (<FIG>). Then, the driver <NUM> is connected to the trunk line <NUM> having a large wiring width via the through electrodes <NUM>-<NUM> to <NUM>-<NUM>. Furthermore, the branch lines <NUM>-<NUM> to <NUM>-<NUM> having a smaller wiring width are connected to the trunk line <NUM> via through electrodes <NUM>-<NUM> to <NUM>-<NUM>, respectively. Moreover, in the clock wiring <NUM>, a plurality of VDD lines and a plurality of GND lines are arranged at regular intervals in parallel with the branch lines <NUM>. Furthermore, the wiring shape of the clock wiring <NUM> is bilaterally symmetrical with respect to the center line of the trunk line <NUM>.

Then, since the current density decreases as the trunk line <NUM> approaches a far end, as described above, the wiring shape of the trunk line <NUM> is set so that the wiring width becomes gradually smaller so that a resistance increases toward a far end side, according to a change in the current density. Furthermore, the trunk line <NUM> is formed so that the wiring width becomes smaller by, for example, a predetermined constant width every constant distance from the connection portion of the driver <NUM>.

For example, the wiring shape of the trunk line <NUM> is set so that the wiring width becomes smaller so as to be symmetrical with respect to the center line for every branch portion where the branch lines <NUM>-<NUM> to <NUM>-<NUM> are branched, from the connection portion of the driver <NUM> toward an upper side (similarly, toward a lower side (not illustrated)). That is, the trunk line <NUM> is formed so that the wiring width changes from a wiring width D1 to a wiring width D2 (< D1) at a branch portion where the branch line <NUM>-<NUM> is branched, changes from the wiring width D2 to a wiring width D3 (< D2) at a branch portion where the branch line <NUM>-<NUM> is branched, and changes from the wiring width D3 to a wiring width D4 (< D3) at a branch portion where the branch line <NUM>-<NUM> is branched. Note that in the present embodiment, a wiring width D is formed so as to be symmetrical with respect to the center line, and will hereinafter be described as a width on one side with respect to the center line (that is, an actual wiring width is twice D), similar to <FIG>.

Specifically, a configuration example in which the driver <NUM> drives the clock wiring <NUM> of which total capacity including a wiring capacity and a gate capacity is <NUM> pF, a rate is controlled by Signal EM, a required wiring width on the driver <NUM> side is <NUM>, a total capacity (wiring capacity and gate capacity) connected to the receiver <NUM> is <NUM> pF, and a required wiring width on the receiver <NUM> side is <NUM> will be described. In such a configuration example, a drive charge decreases as the trunk line approaches the far end. Therefore, in a case where ten branch lines <NUM> are branched on one side of the trunk line <NUM> in a fishbone wiring shape as illustrated in <FIG>, it is preferable to set the wiring shape so that the wiring width of the trunk line <NUM> becomes smaller by <NUM> for every branch portion. Therefore, a redundant wiring capacity in the clock wiring <NUM> can be eliminated.

As such, conditions for appropriately eliminating the redundant wiring capacity of the clock wiring <NUM> vary depending on layout situations, circuit situations or the like such as the wiring capacity or the gate capacity, the required wiring width, the number of branch lines <NUM>, and the like. Therefore, it is necessary to appropriately design the wiring shape so as to narrow the wiring width of the trunk line <NUM> according to those conditions.

<FIG> illustrates a modification of the wiring shape of the clock wiring <NUM> illustrated in <FIG>.

In a clock wiring 31A illustrated in <FIG>, branch lines 33A-<NUM> to 33A-<NUM> branched from the trunk line <NUM> have wiring shapes set so that wiring widths become smaller according to distances from the trunk line <NUM>, that is, as distances from the driver <NUM> increase. For example, a plurality of branch lines 33A forming the clock wiring 31A is formed so that the wiring widths become evenly smaller from the center line by a predetermined constant width every constant distance from branch portions from the trunk line <NUM>.

For example, as illustrated in <FIG>, the branch lines 33A-<NUM> to 33A-<NUM> are formed so that the wiring widths become smaller every constant distance in the order of a length L1 from the center line of the trunk line <NUM>, a length L2 following the length L1, and a length L3 (L1 = L2 = L3) following the length L1.

As such, in the clock wiring 31A, better performance can be obtained by optimizing the wiring widths of the trunk line <NUM> and the branch lines 33A.

A wiring shape in which the present technology is applied to a long-distance wiring will be described with reference to <FIG> and <FIG>.

A of <FIG> illustrates a circuit diagram of a long-distance wiring. As illustrated in A of <FIG>, an output terminal of the driver <NUM> is connected to an input terminal of the receiver <NUM> and a distance between the driver <NUM> and the receiver <NUM> is greater than or equal to a predetermined distance, in a single wiring without providing a branch between the driver <NUM> and the receiver <NUM>.

B of <FIG> and C of <FIG> illustrate layout diagrams illustrating wiring shapes to which the present technology is applied, based on the circuit diagram illustrated in A of <FIG>. Furthermore, a clock wiring <NUM> of B of <FIG> has a layout in which a long-distance wiring <NUM> is arranged along the vertical direction of the semiconductor integrated circuit, and a clock wiring <NUM> of C of <FIG> has a layout in which a long-distance wiring <NUM> is arranged along the horizontal direction of the semiconductor integrated circuit.

As illustrated in B of <FIG>, in the clock wiring <NUM>, the long-distance wiring <NUM> has a wiring shape set so that a wiring width becomes smaller according to a distance from a connection portion of the driver <NUM> to upper and lower sides in the vertical direction, and is connected to the receiver <NUM>. That is, since a current density of a signal transmitted via the long-distance wiring <NUM> decreases as a distance from the driver <NUM> increases, the long-distance wiring <NUM> is formed so that the wiring width becomes smaller according to the decrease in the current density.

Similarly, as illustrated in C of <FIG>, in the clock wiring <NUM>, the long-distance wiring <NUM> has a wiring shape set so that a wiring width becomes smaller according to a distance from a connection portion of the driver <NUM> to the left and right in the horizontal direction, and is connected to the receiver <NUM>. That is, since a current density of a signal transmitted via the long-distance wiring <NUM> decreases as a distance from the driver <NUM> increases, the long-distance wiring <NUM> is formed so that the wiring width becomes smaller according to the decrease in the current density.

The clock wirings <NUM> and <NUM> having such wiring shapes are large-scale wirings using the long-distance wirings <NUM> and <NUM> having a length of a predetermined distance or more, specifically, about <NUM> to <NUM>, and have wiring shapes set depending on the current densities. As such, better performance can be obtained by optimizing the wiring width in the wiring where a difference occurs in the current density regardless of the number of receivers <NUM>, a distance from the driver <NUM> to the receiver <NUM>, or the like.

<FIG> illustrates a specific wiring shape of the clock wiring <NUM> illustrated in B of <FIG>.

As illustrated in <FIG>, the driver <NUM> is connected to one end of the long-distance wiring <NUM> via a through electrode <NUM>-<NUM> and the receiver <NUM> is connected to the other end of the long-distance wiring <NUM> via a through electrode <NUM>-<NUM>.

Then, in the clock wiring <NUM>, the current density decreases as the long-distance wiring <NUM> approaches the receiver <NUM>, and the wiring shape of the long-distance wiring <NUM> is thus set so that the wiring width becomes smaller according to a change in the current density. For example, the wiring shape of the long-distance wiring <NUM> is set so that the wiring width becomes smaller so as to be symmetrical with respect to the center line from a connection portion of the driver <NUM> toward an upper side. That is, the wiring shape of the long-distance wiring <NUM> is set so that the wiring width changes from a wiring width D1 to a wiring width D2 (< D1) and changes from the wiring width D2 to a wiring width D3 (< D2), according to a distance from the driver <NUM>.

Specifically, in a case of the wiring shape in which the wiring width becomes smaller according to the distance away from the connection portion of the driver <NUM>, it is preferable to narrow the wiring width of the long-distance wiring <NUM> at a pitch of <NUM> to <NUM> and set the wiring shape so that the wiring width is a minimum width at a connection portion of the receiver <NUM>. Alternatively, in a case where a length of the long-distance wiring <NUM> is about <NUM> to <NUM>, it is possible to make the wiring shape optimal by calculating a wiring width required at the connection portion of the receiver <NUM>, which is a far end, and gradually narrowing the wiring width from the driver <NUM> side with a value evenly divided so that the wiring width at the connection portion of the receiver <NUM> is the calculated wiring width.

By applying the wiring shape as described above, a wiring capacity is reduced, such that an amount of current can be reduced, power consumption can be reduced, and electro magnetic interference (EMI) characteristics can be improved.

Furthermore, the wiring capacity can be reduced, such that a load capacity can be reduced, a speed can be improved, and a drive capacity of the driver <NUM> can be reduced. As a result, power can be improved and an area can be reduced. Accordingly, the reduced area can be used for other wirings, such that a wiring property can be improved.

Moreover, by applying the wiring shape described above, a resistance value on the far end side increases, such that it is possible to reduce occurrence of reflection in a signal. Furthermore, areas of an upper layer wiring and a through electrode are reduced, such that antenna characteristics can also be improved. In particular, for a high-frequency clock in which the reflection of the signal easily occurs, a fine process in which electro migration (EM) is problematic, a large-scale wiring, or the like, better characteristics can be obtained.

A second embodiment of a wiring shape used in a semiconductor integrated circuit to which the present technology is applied will be described with reference to <FIG>.

<FIG> illustrates a layout diagram illustrating a wiring shape to which the present technology is applied, based on the circuit diagram illustrated in <FIG>. Furthermore, <FIG> enlarges and illustrates an area surrounded by a broken line in <FIG>.

A clock wiring <NUM> illustrated in <FIG> and <FIG> has a fishbone wiring shape in which five branch lines <NUM>-<NUM> and <NUM>-<NUM> having a small wiring width are connected to a trunk line <NUM> having a large wiring width so as to be branched from the trunk line <NUM>, similar to the clock wiring <NUM> of <FIG>. Note that the clock wiring <NUM> of <FIG> has a layout in which the trunk line <NUM> is arranged along a vertical direction of a semiconductor integrated circuit.

Furthermore, in the clock wiring <NUM>, connection terminals <NUM>-<NUM> to <NUM>-<NUM> connected to the receivers <NUM>-<NUM> to <NUM>-<NUM> of <FIG> are provided on the branch lines <NUM>-<NUM> to <NUM>-<NUM>. Furthermore, connection terminals <NUM>-<NUM> and <NUM>-<NUM> are also provided between a buffer <NUM> and a driver <NUM>.

Then, in the clock wiring <NUM>, in a case where an output terminal of the driver <NUM> is connected to the center of the trunk line <NUM> and a transmitted signal has a high frequency, a wiring shape of the trunk line <NUM> is set to be a mesh shape in which a plurality of slits is formed according to a frequency of the signal transmitted by the trunk line <NUM>.

Generally, as the frequency of the signal transmitted by the trunk line <NUM> becomes high, a ratio of a skin resistance component increases due to a direct current (DC) resistance. Therefore, in the clock wiring <NUM> via which a high-frequency signal is transmitted, the plurality of slits is formed in the trunk line <NUM> so as to become finer according to the frequency, such that it is possible to reduce the skin resistance component as the mesh shape in which a surface area of the trunk line <NUM> is increased.

Therefore, in the clock wiring <NUM>, the wiring shape is set to be the mesh shape by forming the plurality of slits, such that a skin resistance can be reduced and attenuation of the signal can be suppressed. As a result, performance of the semiconductor integrated circuit including the clock wiring <NUM> can be improved.

A clock wiring <NUM> illustrated in <FIG> and <FIG> has a layout in which a trunk line <NUM> to which the driver <NUM> is connected is arranged along a horizontal direction of the semiconductor integrated circuit.

Then, as illustrated in <FIG>, in the clock wiring <NUM>, similar to the clock wiring <NUM> of <FIG>, a wiring shape of the trunk line <NUM> to which the driver <NUM> is connected is set to be a mesh shape in which a plurality of slits is formed according to a frequency of a signal transmitted by the trunk line <NUM>.

In the clock wiring <NUM> having such a wiring shape, similar to the clock wiring <NUM> of <FIG>, better performance can be obtained by forming the trunk line <NUM> in an optimum mesh shape according to the frequency of the signal.

In the clock wiring <NUM> illustrated in <FIG>, the driver <NUM> is connected to the trunk line <NUM> having a large wiring width via through electrodes <NUM>-<NUM> to <NUM>-<NUM>. Furthermore, the branch lines <NUM>-<NUM> to <NUM>-<NUM> having a small wiring width are connected to the trunk line <NUM> via through electrodes <NUM>-<NUM> to <NUM>-<NUM>, respectively. Moreover, in the clock wiring <NUM>, a plurality of VDD lines and a plurality of GND lines are arranged in parallel with the branch lines <NUM>. Furthermore, the wiring shape of the clock wiring <NUM> is bilaterally symmetrical with respect to the center line of the trunk line <NUM>.

Then, as described above, the slits having a width w and a height h are formed at a plurality of places of the trunk line <NUM>, and the wiring shape of the trunk line <NUM> is set to be the mesh shape by these slits. For example, the width w and the height h of the slit are formed to be smaller dimensions as the frequency of the signal transmitted by the clock wiring <NUM> becomes high, such that the trunk line <NUM> is formed in a finer mesh shape.

A of <FIG> illustrates a circuit diagram of a long-distance wiring, as illustrated in A of <FIG>, an output terminal of the driver <NUM> is connected to an input terminal of the receiver <NUM> in a single wiring without providing a branch between the driver <NUM> and the receiver <NUM>.

As illustrated in B of <FIG>, in the clock wiring <NUM>, the long-distance wiring <NUM> directed toward the vertical direction has a wiring shape set so that a plurality of slits is formed according to a frequency of a signal transmitted through the clock wiring <NUM>, and is connected to the receiver <NUM>. That is, in a case where the signal has a high frequency, the long-distance wiring <NUM> is formed to have a finer mesh shape so that a surface area increases by forming the slits.

Similarly, as illustrated in C of <FIG>, in the clock wiring <NUM>, the long-distance wiring <NUM> directed toward the horizontal direction has a wiring shape set so that a plurality of slits is formed according to a frequency of a signal transmitted through the clock wiring <NUM>, and is connected to the receiver <NUM>. That is, in a case where the signal has a high frequency, the long-distance wiring <NUM> is formed to have a finer mesh shape so that a surface area increases by forming the slits.

The clock wirings <NUM> and <NUM> having such wiring shapes are large-scale wirings using the long-distance wirings <NUM> and <NUM> having a length of a predetermined distance or more, specifically, about <NUM> to <NUM>, and have wiring shapes set depending on the frequency of the signal. As such, better performance can be obtained by optimizing the slits according to the frequency of the transmitted signal regardless of the number of receivers <NUM>, a distance from the driver <NUM> to the receiver <NUM>, or the like.

Then, in the clock wiring <NUM>, the slits having a width w and a height h are formed at a plurality of places of the long-distance wiring <NUM>, and the wiring shape of the long-distance wiring <NUM> is set to be the mesh shape by these slits. Therefore, a surface area of the long-distance wiring <NUM> can be increased, such that attenuation of the signal due to a skin resistance can be reduced.

For example, in the clock wiring <NUM>, as the frequency of the signal transmitted by the long-distance wiring <NUM> becomes high, the width w and the height h of the slit are reduced, such that the wiring shape of the long-distance wiring <NUM> is set to be the finer mesh shape.

By applying the wiring shape as described above, the skin resistance is reduced, such that the attenuation of the signal can be suppressed and a speed can be improved. Furthermore, a wiring capacity can be reduced, and power consumption can be reduced.

A power supply wiring to which the present technology is applied will be described with reference to <FIG>.

<FIG> illustrates a layout diagram of a power supply wiring.

A power supply wiring <NUM> illustrated in <FIG> includes a current supply source <NUM> and a GND supply source <NUM>, a VDD trunk line <NUM> is connected to the current supply source <NUM>, and a GND trunk line <NUM> is connected to the GND supply source <NUM>.

Furthermore, the VDD trunk line <NUM> and the GND trunk line <NUM> having a large wiring width are arranged along the vertical direction of the semiconductor integrated circuit, and a plurality of VDD lines and a plurality of GND lines having a small wiring width are arranged along the horizontal direction of the semiconductor integrated circuit. Then, in the power supply wiring <NUM>, the VDD trunk line <NUM> is connected to each of seven VDD lines via through electrodes <NUM>-<NUM> to <NUM>-<NUM>, and the GND trunk line <NUM> is connected to each of six GND lines via through electrodes <NUM>-<NUM> to <NUM>-<NUM>.

Furthermore, in an example illustrated in <FIG>, a plurality of power consumption sources (for example, transistors) indicated by dot hatching is connected between VDD lines and GND lines at desired places.

In such a power supply wiring <NUM>, the VDD trunk line <NUM> has a wiring shape set so that a wiring width becomes larger as a distance from the current supply source <NUM> increases. That is, the VDD trunk line <NUM> is formed so that the wiring width changes from a wiring width D11 to a wiring width D12 (> D11), changes from the wiring width D12 to a wiring width D13 (> D12), and changes from the wiring width D13 to a wiring width D14 (> D13), every constant distance from the current supply source <NUM>.

Furthermore, the VDD trunk line <NUM> is formed to have a larger wiring width for, for example, each of the plurality of power consumption sources each time the power consumption sources are connected. In the example illustrated in <FIG>, the power consumption sources are arranged so as to be dense at a place away from the current supply source <NUM>, and the wiring shape of the VDD trunk line <NUM> is set so that the wiring width becomes larger toward the place.

Similarly, in the power supply wiring <NUM>, the GND trunk line <NUM> has a wiring shape set so that a wiring width becomes larger as a distance from the GND supply source <NUM> increases. That is, the GND trunk line <NUM> is formed so that the wiring width changes from a wiring width D21 to a wiring width D22 (> D21), changes from the wiring width D22 to a wiring width D23 (> D22), and changes from the wiring width D23 to a wiring width D24 (> D23), every constant distance from the GND supply source <NUM>.

Furthermore, the GND trunk line <NUM> is formed to have a larger wiring width for, for example, each of the plurality of power consumption sources each time the power consumption sources are connected. In the example illustrated in <FIG>, the power consumption sources are arranged so as to be dense at a place away from the GND supply source <NUM>, and the wiring shape of the GND trunk line <NUM> is set so that the wiring width becomes larger toward the place.

Therefore, the power supply wiring <NUM> can realize an even voltage drop (IR Drop) along a longitudinal direction of the current supply source <NUM> and the GND supply source <NUM>, and can improve resistance to an arrangement variation of the plurality of power consumption sources.

By applying the wiring shape as described above, the voltage drop can be made uniform, such that a jitter generated in a signal waveform can be improved or a signal timing can be improved, and better characteristics can resultantly be obtained.

Impedance matching will be described with reference to <FIG>.

A of <FIG> illustrates a circuit diagram of a wiring for performing impedance matching.

As illustrated of A in <FIG>, in a wiring <NUM>, an output terminal of the driver <NUM> is grounded via a terminating resistor <NUM>.

As illustrated in B of <FIG>, the driver <NUM> is connected to one end of a signal line <NUM>, which is a target for taking an impedance via a through electrode <NUM>-<NUM>, and the terminating resistor <NUM> is connected to the other end of the signal line <NUM> via a through electrode <NUM>-<NUM>. Furthermore, as illustrated in B of <FIG>, the signal line <NUM> is arranged along the vertical direction of the semiconductor integrated circuit, and a plurality of VDD lines and a plurality of GND lines are arranged along the horizontal direction of the semiconductor integrated circuit.

Then, the signal line <NUM> has a wiring shape set so that a wiring width becomes larger from the driver <NUM> toward the terminating resistor <NUM> so that the impedance is matched. That is, the signal line <NUM> is formed so that the wiring width changes from a wiring width D1 to a wiring width D2 (> D1) and changes from the wiring width D2 to a wiring width D3 (> D2), every constant distance from the driver <NUM>.

Therefore, in the wiring <NUM>, impedance matching can be performed by the signal line <NUM> so that an output impedance of the driver <NUM> and an input impedance of the terminating resistor <NUM> become equal to each other.

By applying the wiring shape as described above, electromagnetic radiation can be suppressed and reflection of a signal can be reduced, such that reliability can be improved, and better characteristics can resultantly be obtained.

An example in which current concentration occurs will be described with reference to <FIG>.

In a wiring <NUM> as illustrated in A of <FIG>, if current densities on a driver <NUM> side and receiver <NUM>-<NUM> to <NUM>-<NUM> sides are compared with each other, the current density is higher on the driver <NUM> side than on the receiver <NUM>-<NUM> to <NUM>-<NUM> sides. Therefore, it is preferable that wiring resistors <NUM>-<NUM> to <NUM>-<NUM> from the driver <NUM> side to the receiver <NUM>-<NUM> are set to have the largest current density on the driver <NUM> side.

Therefore, as illustrated in B of <FIG>, in the wiring <NUM>, a signal line <NUM> having a wiring shape in which a wiring width becomes large on the driver <NUM> side having a high current density and becomes small on the receiver <NUM>-<NUM> side having a low current density is adopted. That is, the signal line <NUM> is formed so that the wiring width changes from a wiring width D1 to a wiring width D2 (< D1), changes from the wiring width D2 to a wiring width D3 (< D2), changes from the wiring width D3 to a wiring width D4 (< D3), and changes from the wiring width D4 to a wiring width D5 (< D5), from the driver <NUM> for every connection portion where the receiver <NUM> is connected.

By adopting such a wiring shape, it is possible to reduce a redundant wiring capacity in the wiring <NUM>.

As described above, in the semiconductor integrated circuit to which the wiring shape of each of the embodiments described above is applied, the wiring width of the signal line is formed to become gradually smaller so that the resistance increases toward the far end side, such that reflection of a signal, electromagnetic radiation, or the like, can be reduced. Furthermore, in the semiconductor integrated circuit, the wiring width of the power supply wiring is formed to become gradually larger toward the far end side, such that an amount of voltage drop can be controlled, a more uniform voltage drop can be realized, and resistance to a variation can be improved.

Furthermore, the semiconductor integrated circuit to which the wiring shape of each of the embodiments described above is applied can be applied to a design aiming at a high speed or a design aiming at low power consumption to realize further improvement of performance. For example, the semiconductor integrated circuit can be more effective for a design requiring a high-speed (<NUM> or higher) clock or a large-scale (<NUM> pF or higher) wiring.

Moreover, in the future, as miniaturization of the semiconductor integrated circuit progresses, a wiring becomes thinner and film thinning progresses, such that there is concern about adverse effects such as EM, high resistance or the like, but by applying the wiring shape of each of the embodiments described above, it is possible to suppress those adverse effects. Similarly, due to the progress of the miniaturization, there is a concern about an adverse effect of a variation, and in particular, it is assumed that the uniformity of the voltage drop in the power consumption source (for example, the transistor) as described with reference to <FIG> is emphasized, and thus, it is very effective to be able to make the voltage drop uniform as described above.

In particular, for example, in a case where it is necessary to increase the wiring width due to severe EM or the like, in a case where a plurality of wirings should be used, or the like, by applying the present technology, an unnecessary wiring area can be reduced, such that an effect of reducing power consumption can be remarkably obtained. Furthermore, by applying the present technology to, for example, a high-frequency wiring of <NUM> or higher, a wiring where the receiver <NUM> side is far away (for example, <NUM> or more), or the like, the wiring width of the wiring on the far end side can be minimized, such that an effect of reflection or noise suppression can be remarkably obtained.

The wiring shape of each of the embodiments as described above can be adopted in a semiconductor integrated circuit such as, for example, an imaging element, a signal processing circuit or the like, and can be applied to various electronic apparatuses such as, for example, an imaging system such as a digital still camera, a digital video camera or the like, a mobile phone having an imaging function, or another apparatus having an imaging function.

<FIG> is a block diagram illustrating a configuration example of an imaging device mounted in an electronic apparatus.

As illustrated in <FIG>, the imaging device <NUM> includes an optical system <NUM>, an imaging element <NUM>, a signal processing circuit <NUM>, a monitor <NUM>, and a memory <NUM>, and can capture a still image and a moving image.

The optical system <NUM> includes one or a plurality of lenses, guides image light (incident light) from a subject to the imaging element <NUM>, and forms an image on a light receiving surface (sensor unit) of the imaging element <NUM>.

A semiconductor integrated circuit that has adopted the wiring shape described above is applied to the imaging element <NUM>. In the imaging element <NUM>, electrons are accumulated for a certain period according to an image formed on the light receiving surface through the optical system <NUM>. Then, a signal corresponding to the electrons accumulated in the imaging element <NUM> is supplied to the signal processing circuit <NUM>.

A semiconductor integrated circuit that has adopted the wiring shape described above is applied to the signal processing circuit <NUM>, and the signal processing circuit <NUM> performs various signal processing on a pixel signal output from the imaging element <NUM>. An image (image data) obtained by performing signal processing by the signal processing circuit <NUM> is supplied to and displayed on the monitor <NUM> or is supplied to and stored (recorded) in the memory <NUM>.

In the imaging device <NUM> configured as described above, for example, power consumption can be reduced or reliability can be improved by applying the semiconductor integrated circuit that has adopted the wiring shape described above.

The following configurations are provided for illustration purposes.

A semiconductor integrated circuit including:.

In some embodiments, the wiring has a wiring shape set so that a wiring width becomes smaller as the distance from the driver increases.

In some embodiments, the wiring width of the wiring becomes small so as to suppress reflection of the signal at an end portion of the wiring in a case where a receiver receiving the signal is a complementary metal oxide semiconductor (CMOS).

In some embodiments, the wiring has a wiring shape set so that the wiring width is in accordance with a current density of the signal.

According to the present invention, the transmission network is formed by a first wiring to which the driver is connected and which has a large wiring width and a plurality of second wirings which is branched from the first wiring and has a small wiring width, and
the first wiring has a wiring shape set so that a wiring width becomes smaller for every branch portion of the second wirings as a distance from a connection portion of the driver increases.

In some embodiments, the first wiring has a central portion to which the driver is connected, and has a wiring width that becomes smaller so that a resistance increases toward a far end side.

In some embodiments, the first wiring is formed so that the wiring width becomes smaller by a predetermined constant width every constant distance from the connection portion of the driver.

In some embodiments, the second wiring is formed so that the wiring width becomes smaller by a predetermined constant width every constant distance from the branch portion from the first wiring.

In some examples provided for illustration purposes, the wiring is a long-distance wiring that singly connects the driver to the receiver and has a predetermined distance or more.

In some examples provided for illustration purposes, the wiring has a wiring shape set to be a mesh shape by forming a plurality of slits in a case where the signal has a high frequency.

In some examples provided for illustration purposes, the wiring is formed in the mesh shape so that the slits become finer as the frequency of the signal increases.

In some examples provided for illustration purposes, the wiring is a power supply wiring that supplies power from a current supply source to a plurality of power consumption sources, and has a wiring shape set so that a wiring width becomes larger as a distance from the current supply source increases.

In some examples provided for illustration purposes, the wiring is formed to have a larger wiring width for each of a plurality of the power consumption sources, each time the power consumption sources are connected.

In some examples provided for illustration purposes, the wiring has a wiring shape set so that a wiring width becomes larger from the driver toward a terminating resistor so that an impedance is matched.

In some embodiments, the wiring width of the wiring becomes large by a predetermined constant width every constant distance from the driver.

In some embodiments, an electronic apparatus includes the semiconductor integrated circuit.

Claim 1:
A semiconductor integrated circuit comprising:
a wiring (<NUM>; <NUM>; 31A; <NUM>; <NUM>) configured to form a transmission network through which a same signal is transmitted; and
a driver (<NUM>) configured to supply the signal to the wiring (<NUM>; <NUM>; 31A; <NUM>; <NUM>),
wherein the wiring (<NUM>; <NUM>; 31A; <NUM>; <NUM>) has a wiring shape set according to a distance from the driver (<NUM>) or a frequency of the signal;
wherein the wiring (<NUM>; <NUM>; 31A; <NUM>; <NUM>) is branched from an output terminal of the driver (<NUM>) and configured to be connected to an input terminal of a receiver (<NUM>; <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>);
wherein the transmission network is formed by a first wiring (<NUM>; <NUM>) to which the driver (<NUM>) is connected and which has a large wiring width and a plurality of second wirings (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>; 33A-<NUM>, 33A-<NUM>, 33A-<NUM>, 33A-<NUM>; <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) which is branched from the first wiring (<NUM>; <NUM>) and has a smaller wiring width,
characterized in that
the first wiring (<NUM>; <NUM>) has a wiring shape set so that a wiring width becomes smaller for every branch portion of the second wirings (<NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>; 33A-<NUM>, 33A-<NUM>, 33A-<NUM>, 33A-<NUM>; <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>, <NUM>-<NUM>) as a distance from a connection portion of the driver (<NUM>) increases; and
wherein the wiring shape of the first wiring (<NUM>; <NUM>; 31A; <NUM>; <NUM>) is set so that the wiring width corresponds to a decrease in a current density.