Patent Description:
The present invention relates to a sound production system for digital audio sources. More specifically, the present invention relates a method and system for improving playback timing across a plurality of sound production stations.

<FIG> is a block diagram of a conventional digital audio playback system <NUM>, which includes a digital audio source <NUM>, an audio processor <NUM>, and loudspeakers <NUM>-<NUM>. Digital audio source <NUM> provides a digital audio bit stream to audio processor <NUM>. The digital audio bit stream can be transmitted, for example, over an HDMI cable or using a wireless transmission protocol (WiFi). The digital audio bit stream can be provided by an audio source, such as a music streaming service (e.g., Spotify or Tidal), a mobile device (e.g., a smart phone or tablet), a smart home device (e.g., Google Home or Amazon Alexa), or a music server. The digital audio bit stream can alternately be provided by
an audio-video source, such as streaming video from the Internet (e.g., YouTube or Netflix), networked HDTV or video gaming.

Audio processor <NUM> includes an audio decoder <NUM>, which receives the digital audio bit stream from digital audio source <NUM>. The digital audio bit stream is played back in multiple channels in order to re-create a three dimensional (3D) sound effect. Examples of multi-channel playback systems include conventional two channel stereo systems, <NUM> channel systems (e.g., for Dolby AC-<NUM> coding), Dolby Surround <NUM> channel systems and Dolby ATMOS. In these multi-channel systems, each channel is played back in a different spatial location.

The digital audio bit stream is typically encoded in a highly compressed bit stream. Most of the information for the various channels is coded as a single channel with some extra information in the digital bit stream in order to avoid the linear increment of the bit rate for each additional channel. Hence, audio decoder <NUM> is used to decode the digital audio bit stream to re-create each channel. Audio decoder <NUM> also generates an audio sample clock to synchronize each channel. The audio sample clock typically has a frequency of <NUM> to <NUM>, based on an audio spectrum of <NUM>-<NUM>. The audio quality and effect will suffer if the sample clock for each channel is out of synchronization.

Audio processor <NUM> also includes digital-to-analog (D/A) converters <NUM>-<NUM> for each channel. Each of the D/A converters <NUM>-<NUM> receives the decoded digital bit stream for the associated channel and the audio sample clock from the audio decoder <NUM>. In response, each of the D/A converters <NUM>-<NUM> provides an analog output signal for the associated channel. Power amplifiers <NUM>-<NUM> receive the analog output signals from the D/A converters <NUM>-<NUM>, respectively. In response, power amplifiers <NUM>-<NUM> drive amplified analog output signals to speakers <NUM>-<NUM>, respectively, over speaker cables.

In a typical digital audio system (which implements a centralized audio processor model), audio decoder <NUM>, D/A converters <NUM>-<NUM> and the power amplifiers <NUM>-<NUM> are included in the same box. Examples of this type of equipment include an audio/video (A/V) processor, media server client and Media Devices. In general, audio processor <NUM> is required to provide the required power amplification for all of the channels. As a result, audio processor <NUM> is a relatively expensive device. Moreover, audio processor <NUM> implements preset signal processing and decoding functions, which may limit the future expansion of this device. In addition, speaker wires are needed to connect the audio processor <NUM> to each of the associated loudspeakers <NUM>-<NUM>. As the number of channels increases, so does the required number of speaker wires. Market research has shown that the routing of speaker wires is a major obstacle for the adoption of surround sound systems.

In an active loudspeaker model, the power amplifiers <NUM>-<NUM> are included in the same box as the loudspeakers <NUM>-<NUM>, rather than in the audio processor <NUM>. However, this model still exhibits the problems described above.

A typical <NUM> home theater system requires the connection of two pair of wires from the audio processor <NUM> to a pair of surround speakers in the back of the room. As described above, this creates a very significant inconvenience for adopting a surround sound system. One solution available to solve this problem is wireless speaker technology. Wireless loudspeakers use invisible radio waves in lieu of physical speaker cables to transport sound from the audio processor <NUM> at the front of the room to surround speakers at the rear of the room.

In this case, the audio processor <NUM> must include a wireless transmitter, undesirably increasing the cost and complexity of this device. A small power amplifier/RF receiver is typically placed near the rear of the room (e.g., under a couch), and speaker wires are run from this power amplifier/RF receiver to the surround speakers, a few feet away. Thus, speaker wires must still be used in this system. A subset of the audio channels (i.e., the audio channels to be played through the surround speakers) are transmitted through the wireless interface from the audio processor <NUM> to the remote power amplifier/RF receiver, and are played through the surround speakers. Note that by transmitting a subset of the audio channels wirelessly, while transmitting the remaining audio channels through speaker cables, the sound quality and the surround effect can be significantly compromised.

It would therefore be desirable to have an audio system that overcomes the above-described deficiencies of a conventional audio system.

<CIT> (hereinafter, the '<NUM> Patent), describes a cognitive loudspeaker system that includes an active control station that communicates wirelessly and bi-directionally with a plurality of sound production stations. The control station and the sound production stations are initially synchronized to a conductor clock. During a setup process, configuration information is transmitted from the sound production stations to the active control station. In response to the received configuration information, the active control station generates playback executables for each of the sound production stations. The active control station wirelessly transmits the playback executables to the sound production stations. After the setup process is complete, the active control station wirelessly transmits digital audio information (which is received from a digital audio source) to the sound production stations. Within each sound production station, the previously received playback executable is used to control the decoding and processing of the received digital audio information. Each sound production station generates digital audio output samples in response to the received digital audio information (and the associated playback executable). The digital audio samples are converted to an analog output signal, which is amplified and played through a speaker. Thus, the active control station establishes a virtual decoder within each of the sound production stations, which enables playback from various sources. The virtual decoder allows the cognitive loudspeaker system to be easily modified/updated to handle new coding protocols.

The '<NUM> Patent describes the use of an ultra wide band (UWB) wireless interface to transmit messages between the active control station and the sound production stations. The UWB wireless interface has been standardized (IEEE <NUM>), such that the use of this interface may result in a multi-access problem. In a multi-access environment, multiple agents share the same wireless medium through standardized methods. As a result, the sender cannot guarantee that data is sent to the receiver at a precise moment. It becomes more difficult to guarantee this timing when the data payload is large, as is the case for an audio playback stream. However, timing accuracy of the message units sent from the control station to the sound production stations is critical to the operation of the cognitive loudspeaker system (i.e., the '<NUM> Patent relies on a 'just-in-time' playback stream delivery method).

Moreover, the '<NUM> Patent teaches that both timing and data information are embedded in the same packet, wherein loss of a packet or a corrupted message unit can result in significant function and performance problems.

It would therefore be desirable to have an improved cognitive loudspeaker system that overcomes the above-described deficiencies of the '<NUM> Patent.

According to an aspect of the present invention, there is provided a system according to any of claims <NUM> to <NUM>.

According to another aspect of the present invention, there is provided a method according to any of claim <NUM> to <NUM>.

Accordingly, the present invention provides an improved method for implementing the transport of playback timing information and a playback stream from
the control station to the sound production stations of a cognitive loudspeaker system.

In one embodiment, a cognitive loudspeaker system includes a control station that transmits clock control messages and separate playback messages, wherein the clock control messages are generated in response to a first clock signal within the control station. The cognitive loudspeaker system also includes one or more sound production stations (SPS), each receiving the clock control messages and the playback messages. Each sound production station includes a clock generation circuit that generates a local conductor clock signal in response to the received clock control messages and a local SPS clock signal generated within the sound production station. The local conductor clock signal within each sound production station is synchronized to the first clock signal. A playback processor in each sound production station generates digital playback samples in response to the received playback messages. A memory in each sound production station receives and stores the digital playback samples from the playback processor in response to the local SPS clock signal. The memory in each sound production station outputs the stored digital playback samples in response to the local conductor clock signal.

In one embodiment, the clock control messages are transmitted on a first communication channel and the playback messages are transmitted on a second communication channel. The first and second communication channels can be wireless communication channels. Alternately, the first communication channel can be a wireless communication channel and the second communication can be a powerline Ethernet channel.

In another embodiment, the clock control messages and the playback messages are transmitted at different times on a shared wireless communication channel (e.g., an IEEE <NUM> network).

In one embodiment, the control station includes a modulo counter having a count that cyclically changes from an initial count value to a final count value in response to the first clock signal, wherein a time required to count from the initial count value to the final count value corresponds with a period of the local conductor clock signals.

According to the invention, the clock control messages include: (<NUM>) a first clock control message that includes a first count value (C1) of the modulo counter, wherein the first count value indicates when the first clock control message is transmitted, and (<NUM>) a second clock control message that includes a second count value (C2) of the modulo counter, wherein the second count value indicates when the second clock control message is transmitted, and a third count value (C3) that specifies a difference between the second count value and the final count value of the modulo counter.

Further, according to the invention, the clock generation circuit within each SPS generates the corresponding local conductor clock signal in response to the first, second and third count values. In a particular embodiment, each clock generation circuit includes an incrementor that is loaded with the first count value, and counts from the first count value in response to the local SPS clock signal, until the SPS receives the second clock control message, wherein the count of the incrementor is latched as an incremented count value (I_CNT) when the SPS receives the second clock control message.

The clock generation circuit within each SPS further determines a transmission delay (CS-TO-SPS_DELAY_CYCSPS) of the playback messages from the control station to the SPS, in units of cycles of the local SPS clock signal.

The clock generation circuit within each SPS further includes a calculation unit that uses the first count value, the second count value, the third count value, the incremented count value and the transmission delay to calculate a number of cycles (DEC_0) of the local SPS clock signal until the full count value of the modulo counter is reached. In one embodiment, the calculation unit calculates the number of cycles (DEC_0) in accordance with the following equation: <MAT>.

The clock generation circuit within each SPS further includes a decrementor, wherein the decrementor is loaded with the calculated number of cycles (DEC_0), and counts down in a zero count in response to the local SPS clock signal. When the decrementor reaches a zero count, the clock generation circuit asserts the local conductor clock signal.

The present invention also includes a method including: (<NUM>) broadcasting clock control messages and separate playback messages from a control station to a plurality of sound production stations, wherein the clock control messages are generated in response to a first clock signal within the control station; (<NUM>) generating a local conductor clock signal within each of the sound production stations in response to the clock control messages and a local SPS clock signal generated within each of the sound production stations; (<NUM>) generating digital playback samples in each of the sound production stations in response to the playback messages; (<NUM>) storing the digital playback samples generated in each of the sound production stations in response to the local SPS clock signal; and (<NUM>) retrieving the stored digital playback samples in each of the sound productions stations in response to the local conductor clock signal.

The present invention will be more fully understood in view of the following description and drawings.

In general, the present invention provides a cognitive loudspeaker system for playback from digital audio sources. The cognitive loudspeaker system includes an active control station (CS) and one or more sound production stations (SPSs). As described in more detail below, the cognitive loudspeaker system of the present invention includes systems and methods for synchronizing a plurality of audio channels through a wireless interface.

<FIG> is a block diagram of a cognitive loudspeaker system (CLS) <NUM> in accordance with one embodiment of the present invention. CLS <NUM> includes control station (CS) <NUM> and sound production stations (SPS) <NUM> and <NUM>. Control station <NUM> includes circuitry for implementing a CS conductor clock channel <NUM> and a CS playback stream channel <NUM>. Control station <NUM> also includes a phase locked loop (PLL) <NUM> for generating a local CS clock signal (CS_CLK). As described in more detail below the local CS clock signal CS_CLK controls the timing of operations within the CS conductor clock channel <NUM> and the CS playback stream channel <NUM>.

Sound production station <NUM> includes circuitry for implementing an SPS conductor clock channel <NUM> and an SPS playback stream channel <NUM>. SPS <NUM> also includes a PLL <NUM> for generating a local SPS clock signal (SPS_CLK1). SPS playback stream channel circuitry <NUM> is coupled to power amplifiers (PA) <NUM>-<NUM> and loudspeakers <NUM>-<NUM>, as illustrated.

Similarly, sound production station <NUM> includes circuitry for implementing an SPS conductor clock channel <NUM> and an SPS playback stream channel <NUM>. SPS <NUM> also includes a PLL <NUM> for generating a local SPS clock signal (SPS_CLK2). SPS playback stream channel <NUM> is coupled to power amplifiers (PA) <NUM>-<NUM> and loudspeakers <NUM>-<NUM>, as illustrated.

Although two sound production stations <NUM> and <NUM> are illustrated (e.g., to implement stereo sound), it is understood that other numbers of sound production stations can be used in other embodiments. Although each of the sound production stations <NUM> and <NUM> includes two power amplifiers and two speakers, it is understood that sound production stations <NUM> and <NUM> can have other numbers of power amplifiers and speakers in other embodiments.

Control station <NUM> communicates with sound production stations <NUM> and <NUM> using communication channels <NUM> and <NUM>. More specifically, the CS conductor clock channel circuitry <NUM> communicates with SPS conductor clock channel circuitry <NUM> and <NUM> using conductor clock communication channel <NUM>, and the CS playback stream channel circuitry <NUM> communicates with SPS playback stream channel circuitry <NUM> and <NUM> using playback stream communication channel <NUM>. Communication channels <NUM> and <NUM> are bi-directional communication channels.

As described in more detail below, conductor clock communication channel <NUM> and playback stream communication channel <NUM> can be implemented using wired or wireless communication channels. For example, conductor clock communication channel <NUM> can be implemented wirelessly using WiFi in accordance with the IEEE <NUM> standard, or using the ultra-wide band (UWB) frequency spectrum. By using the UWB frequency spectrum, the circuitry implemented by cognitive loudspeaker system <NUM> can be relatively simple for the bit rate, range and channel environment. More specifically, impulse radio transceivers can be implemented within the control station <NUM> and sound production stations <NUM>/<NUM> to establish a scalable, very low jitter, low latency synchronized system.

Playback stream communication channel <NUM> can be implemented using a (wired) powerline Ethernet channel, or using a (wireless) WiFi channel in accordance with the IEEE <NUM> standard.

In one embodiment, conductor clock communication channel <NUM> and playback stream communication channel <NUM> are implemented using different communication protocols. For example, conductor clock communication channel <NUM> can be implemented using WiFi in accordance with the IEEE <NUM> standard, and playback stream communication channel <NUM> can be implemented using a powerline Ethernet system. In another embodiment, conductor clock communication channel <NUM> is implemented using a UWB channel, and playback stream communication channel <NUM> is implemented using a WiFi channel in accordance with the IEEE <NUM> standard. Other combinations are possible and are considered to be included in the present invention.

In an alternate embodiment, conductor clock communication channel <NUM> and playback stream communication channel <NUM> are implemented using the same communication protocol. For example, conductor clock communication channel <NUM> and playback stream communication channel <NUM> can both be implemented using a common WiFi system in accordance with the IEEE <NUM> standard. In this embodiment, different messages, having different access categories within the WiFi protocol may be used to implement the conductor clock communication channel <NUM> and the playback stream communication channel <NUM>. In this embodiment, the conductor clock communication channel <NUM> is implemented using the highest priority access category available in the <NUM> protocol and the playback stream communication channel <NUM> is implemented using a lower priority access category. In this embodiment, transceivers <NUM> and <NUM> within control station <NUM> can be combined, such that the conductor clock messages and the playback stream messages are transmitted through a single transceiver (at different times). Similarly, transceivers <NUM> and <NUM> within SPS <NUM> can be combined, such that the conductor clock messages and the playback stream messages are received by a single transceiver within SPS <NUM> (at different times). In this embodiment, the received conductor clock messages are routed to conductor clock generation logic <NUM>, and the received playback stream messages are routed to playback stream FIFO <NUM>. Although the conductor clock messages and playback stream messages are transmitted on the same wireless system, the transmission of these messages is considered to occur on logically separate channels <NUM> and <NUM>.

Note that in all embodiments, the conductor clock communication channel <NUM> is effectively separate (or decoupled) from the playback stream communication channel <NUM>.

In general, CLS system <NUM> operates as follows. PLL <NUM> generates the local CS clock signal CS_CLK, which is used to control the timing of CS conductor clock channel circuitry <NUM> and CS playback stream channel circuitry <NUM>. CS playback stream channel circuitry <NUM> transmits and receives messages (e.g., configuration messages, control messages, and playback messages that include digital audio information) on playback stream channel <NUM> in response to the local CS clock signal CS_CLK. Similarly, SPS playback stream channel circuits <NUM> and <NUM> transmit and receive messages on playback stream channel <NUM> in response to the local SPS clock signals SPS_CLK1 and SPS_CLK2, respectively.

CS conductor clock channel circuit <NUM> generates conductor clock messages in response to the local CS clock signal CS_CLK, and transmits these conductor clock messages on conductor clock channel <NUM>. SPS conductor clock channel circuits <NUM> and <NUM> receive the conductor clock messages transmitted on conductor clock channel <NUM>. In response to the received conductor clock messages, and the local clock signals SPS_CLK1 and SPS_CLK2, the SPS conductor clock channel circuits <NUM> and <NUM> generate local conductor clock signals CCLK1 and CCLK2, respectively, wherein the local conductor clock signals CCLK1 and CCLK2 are synchronous with a specified edge of the local CS clock signal CS_CLK. As described in more detail below, rising edges of the local conductor clock signals CCLK1 and CCLK2 are asserted when a modulo counter within control station <NUM> (which is clocked by the local CS clock signal (CS_CLK)) becomes full. The conductor clock signals CCLK1 and CCLK2 are used to read previously stored digital audio samples from SPS playback stream channel circuits <NUM> and <NUM>, respectively.

As described in more detail below, the time delays from the control station <NUM> to each of the sound production stations <NUM> and <NUM> on playback stream channel <NUM> are determined during a configuration phase of the cognitive loudspeaker system <NUM>. These time delays are also used to synchronize the local conductor clock signals CCLK1 and CCLK2.

<FIG> is a block diagram illustrating control station <NUM> in more detail in accordance with one embodiment of the present invention. CS conductor clock circuit <NUM> includes conductor clock modulo counter <NUM>, which is clocked by the local CS_CLK signal. The count value of counter <NUM> is provided to conductor clock message sequencer <NUM>, and to a first input of subtraction circuit <NUM>. The second input of subtraction circuit <NUM> is coupled to receive a FULL_CNT value, which represents the full count value of conductor clock modulo counter <NUM> (i.e., modulo counter <NUM> counts from up from zero to the FULL_CNT value, and then wraps around to zero). Conductor clock message sequencer <NUM> generates conductor clock messages (described in more detail below), which are provided to CS conductor clock message transceiver <NUM>. CS conductor clock message transceiver <NUM> transmits the conductor clock messages on conductor clock channel <NUM>.

As illustrated by <FIG>, CS playback stream channel circuitry <NUM> includes playback message logic <NUM>, first in, first out (FIFO) memory <NUM> and control station playback stream transceiver <NUM>, each of which operates in response to the local CS_CLK signal. Playback message logic <NUM> generates playback messages, which are stored in FIFO memory <NUM>, and then transferred to CS playback stream transceiver <NUM>. CS playback stream transceiver <NUM> transmits the playback messages on playback message channel <NUM>. The playback messages can include, but are not limited to, messages that include digital audio signals of a playback stream, configuration messages, and control messages. Configuration messages may include messages that are transmitted between the control station <NUM> and the sound production stations <NUM> and <NUM> to determine the transmission delays between these stations, and messages that define playback executables to be implemented within the sound production stations <NUM> and <NUM>. Playback messages that can be implemented by the present invention include those described in the '<NUM> patent.

<FIG> is a block diagram illustrating sound production station <NUM> in more detail in accordance with one embodiment of the present invention. It is understood that sound production station <NUM> has the same construction (and operates in the same manner as) the illustrated sound production station <NUM>.

SPS playback stream channel circuit <NUM> includes SPS playback stream transceiver <NUM>, which receives the playback messages transmitted on channel <NUM> (and also transmits configuration and control messages on channel <NUM>). The available bandwidth of channel <NUM> is selected to be greater than the required bandwidth of cognitive loudspeaker system <NUM>. In one embodiment, the control station <NUM> transmits the playback messages ahead of the playback schedule. The received playback messages are written to playback stream FIFO memory <NUM>. The playback messages are read from FIFO memory <NUM> and provided to playback processor <NUM> in response to local clock signal SPS_CLK1. The amount of time that the playback messages are transmitted ahead of schedule is a design choice, which depends on the size of FIFO memory <NUM> and the flow control policy adopted for the playback stream channel <NUM>. However, because the control station <NUM> transmits the playback stream messages and controls how the playback stream messages in the FIFO memory <NUM> are consumed, a very simple flow control policy can be used. For example, the control station <NUM> can simply maintain N playback stream messages in FIFO memory <NUM>, where N is the number of entries in FIFO memory <NUM>.

Playback processor <NUM> processes the playback messages in accordance with the programmable playback executable <NUM>. As described by the '<NUM> patent, programmable playback executable <NUM> is provided to SPS <NUM> (and a similar playback executable is provided to SPS <NUM>) by control station <NUM> during the configuration of cognitive loudspeaker system <NUM>. Programmable playback executable <NUM> enables playback processor <NUM> to decode digital audio information for its designated audio channel using different coding protocols. Playback processor <NUM> is clocked by the local clock signal SPS_CLK1. Playback processor <NUM> generates digital audio samples in response to the received playback messages. These digital audio samples are written to output sample buffer <NUM> in response to the local SPS_CLK1 signal. In accordance with one embodiment of the present invention the digital audio samples stored in output sample buffer <NUM> are read out and provided to digital-to-analog converters (DACs) <NUM> in response to the conductor clock signal CCLK1. DACs <NUM> convert the digital audio samples to analog audio signals, which are transmitted to power amplifiers <NUM>-<NUM> and loudspeakers <NUM>-<NUM>. DACs <NUM> also operate in response to the conductor clock signal CCLK1. As described in more detail below, the conductor clock signal CCLK1 and the conductor clock signal CCLK2 are precisely synchronized to edges of the CS_CLK signal that cause the modulo counter <NUM> to reach the FULL_CNT value.

SPS conductor clock channel circuit <NUM> includes SPS conductor clock message transceiver <NUM>, which receives the conductor clock messages transmitted on channel <NUM>, and conductor clock generation logic <NUM>, which generates the local conductor clock signal CCLK1 in response to the received conductor clock messages.

<FIG> is a block diagram illustrating conductor clock generation logic <NUM> in more detail in accordance with one embodiment of the present invention. Conductor clock generation logic <NUM> includes conductor clock message sequencer <NUM>, incrementor circuit <NUM>, conductor clock trigger count calculator <NUM>, decrementor circuit <NUM>, comparator circuit <NUM> and message delay memory <NUM>, which are connected as illustrated. Incrementor circuit <NUM> and decrementor circuit <NUM> are
clocked by the local SPS clock signal SPS_CLK1 generated by PLL <NUM>.

The generation of the conductor clock signal CCLK1 will now be described in more detail. <FIG> is a flow diagram <NUM> illustrating operations performed within control station <NUM> to enable the generation of the conductor clock signals CCLK1 and CCLK2 in the sound production stations <NUM> and <NUM>, respectively, in accordance with one embodiment of the present invention. Initially, control station <NUM> determines the transmission delay for messages sent from control station <NUM> to sound production station <NUM> and sound production station <NUM> on playback message channel <NUM> (Step <NUM>). In one embodiment, the transmission delay from control station <NUM> to sound production station <NUM> is determined by: (<NUM>) transmitting a message from playback message logic circuit <NUM> (<FIG>) in control station <NUM> to playback processor <NUM> (<FIG>) in sound production station <NUM>, (<NUM>) in response, transmitting a return message from the playback processor <NUM> in SPS <NUM> to playback message logic circuit <NUM>, (<NUM>) measuring the time required for the round-trip transmission of the message, and (<NUM>) dividing the round-trip transmission time by two, thereby calculating the message delay (CS-TO-SPS_DELAY_TIME) from CS <NUM> to SPS <NUM>. Other methods for determining the message delay from control station <NUM> to SPS <NUM> can be implemented in other embodiments. The message delay value CS-TO-SPS_DELAY_TIME is stored in memory <NUM> of CCLK1 generation logic <NUM> (<FIG>). In the described examples, the CS-TO-SPS_DELAY_TIME is <NUM> microseconds.

The message delay from control station <NUM> to SPS <NUM> is also determined (e.g., in the same manner described above). Note that the message delay from control station <NUM> to SPS <NUM> can be different than the message delay from control station <NUM> to SPS <NUM>.

The full count (FULL_CNT) of the conductor clock modulo counter <NUM> is selected such that the period of the local CS_CLK signal times this full count value (FULL_CNT) is equal to the target audio sampling period of the conductor clock signal CCLK1 (and the conductor clock signal CCLK2) (Step <NUM>). In the present example, the local CS_CLK signal has a frequency of <NUM> (i.e., a period of <NUM> microsecond), and the conductor clock modulo counter <NUM> has a full count value FULL_CNT = <NUM>. In this case, the conductor clock signal CCLK1 (and the conductor clock CCLK2) has a frequency of <NUM> (i.e., a period of <NUM> microseconds). Note that the full count value FULL_CNT can be adjusted to adjust the frequency of the conductor clock signal CCLK1, as desired. Also note that the conductor clock signal CCLK2 (of SPS <NUM>) will have the same frequency as the conductor clock signal CCLK1.

Conductor clock message sequencer <NUM> establishes a transmission window on the conductor clock message channel <NUM> (Step <NUM>). In an embodiment where the conductor clock message channel <NUM> is implemented using WiFi in accordance with the IEEE <NUM>. 11e standard, conductor clock message sequencer <NUM> defines the transmission window using the TSPEC and TXOP instructions. In this example, conductor clock message sequencer <NUM> is allocated a QoS (quality of service) transmission opportunity having a high timing precision. In particular, the message sequencer <NUM> is allowed to transmit a first conductor clock message (CC_MSG_1) regularly, with a bounded jitter. Subsequently, the message sequencer can transmit a second conductor clock message (CC_MSG_2) within the allocated transmission window. In other embodiments, other time-division-multiplexing multi-access schemes can be used to establish a proper transmission window.

After the transmission window is established, conductor clock message sequencer <NUM> generates and transmits a first conductor clock message (CC_MSG_1) via transceiver <NUM> on conductor clock channel <NUM> (Step <NUM>). The first conductor clock message CC_MSG_1 includes a first counter value C1, which is the value of the CCLK modulo counter <NUM> at the time the first conductor clock message CC_MSG_1 is sent. In the described example, the first conductor clock message CC_MSG_1 has a first counter value C1 equal to '<NUM>'.

Conductor clock message sequencer <NUM> subsequently generates and transmits a second conductor clock message (CC_MSG_2) on conductor clock channel <NUM> within the allocated transmission window (Step <NUM>). The timing of the transmission of the first and second conductor clock messages CC_MSG_1 and CC_MSG_2 is controlled to be as precise as allowed at the <NUM> protocol stack used to transmit these messages. In the described embodiments, the period between transmitting the first and second conductor clock messages CC_MSG_1 and CC_MSG_2 is less than the period of the conductor clock signal CCLK1. The second conductor clock message CC_MSG_2 includes a second counter value C2, which is the value of the CCLK modulo counter <NUM> at the time the second conductor clock message CC_MSG_2 is sent. The second conductor clock message CC_MSG_2 also includes a conductor clock trigger delay value (CCLK_TRIG_DELAY), which is calculated by subtraction circuit <NUM> (<FIG>), by subtracting the second counter value C2 from the full count value FULL_CNT. Advantageously, the conductor clock message size is relatively small, facilitating the scheduling and transmission of these messages.

In accordance with one embodiment, conductor clock message sequencer <NUM> generates one first conductor clock message (CC_MSG_1) and one second conductor clock message (CC_MSG_2) during each period of the conductor clock signal CCLK1. In the present example, the second clock message CC_MSG_2 has a second counter value C2 equal to '<NUM>' (i.e., <NUM> cycles of the CS_CLK signal after the first clock message CC_MSG_1 is sent with first counter value C1 = <NUM>). In this example, the conductor clock trigger delay value) CCLK_TRIG_DELAY is equal to '<NUM>' cycles of the CS_CLK signal (CCLK_TRIG_DELAY = FULL_CNT - C2 = <NUM> - <NUM> = <NUM>).

Both of the sound production stations <NUM> and <NUM> receive and process the first and second clock messages CC_MSG_1 and CC_MSG_2, and in response, generate the conductor clock signals CCLK1 and CCLK2, respectively. The manner in which the sound production station <NUM> generates the conductor clock signal CCLK1 is described in detail below. It is understood that sound production station <NUM> operates in the same manner to generate the conductor clock signal CCLK2, such that the conductor clock signals CCLK1 and CCLK2 are both synchronized with the full count of conductor clock modulo counter <NUM>.

<FIG> is a flow diagram <NUM> illustrating operations performed within sound production station <NUM> to generate the conductor clock signal CCLK1, in accordance with one embodiment of the present invention.

Conductor clock message sequencer <NUM> of SPS <NUM> initially receives the first conductor clock message CC_MSG_1 transmitted on conductor clock message channel <NUM>, and loads the corresponding first counter value C1 into incrementor <NUM> and CCLK trigger count calculator <NUM> (Step <NUM>). In the described example, the first counter value C1 is '<NUM>'. Incrementor <NUM> counts up from the first counter value in response to the local SPS_CLK1 signal generated by PLL <NUM> (Step <NUM>). In the present example, the local SPS_CLK1 signal has a frequency of <NUM> (although other frequencies are possible). Note that the local SPS_CLK1 signal may have a different frequency than the CS_CLK signal.

Conductor clock message sequencer <NUM> of SPS <NUM> subsequently receives the second conductor clock message CC_MSG_2 transmitted on conductor clock message channel <NUM>, and loads the corresponding second counter value C2 (e.g., <NUM>) and CCLK_TRIG_DELAY value (e.g., <NUM>) into conductor clock trigger count calculator <NUM> (Step <NUM>). Upon receiving the second conductor clock message CC_MSG_2, CCLK message sequencer <NUM> also causes the CCLK trigger count calculator <NUM> to latch the current value of incrementor <NUM> (I_CNT) (Step <NUM>). In the present example, the latched incrementor count value I_CNT is equal to '<NUM>' (<NUM> cycles of the CS_CLK signal elapse between receiving messages CC_MSG_1 and CC_MSG_2, and the frequency of the SPS_CLK1 signal is twice the frequency of the CS_CLK signal, such that <NUM> cycles of the SPS_CLK1 signal elapse between receiving messages CC_MSG_1 and CC_MSG_2). Note that CCLK trigger count calculator <NUM> also receives CS-TO-SPS_DELAY_TIME value (e.g., <NUM> microseconds) previously stored in memory <NUM>.

In response to the above-described received values, CCLK trigger count calculator <NUM> calculates an initial decrementor value (DEC_0) to be loaded into decrementor <NUM> (Step <NUM>). <FIG> is a flow diagram <NUM> illustrating the manner in which CCLK trigger count calculator <NUM> determines the initial decrementor value (DEC_0) in accordance with one embodiment of Step <NUM>. The steps <NUM>-<NUM> of flow diagram <NUM> are shown in a particular order, to simplify the description of the calculation. However, it is understood that this order can be changed, and/or various calculations can be combined (or performed in parallel) to speed up the determination of the initial decrementor value DEC_0.

In Step <NUM>, CCLK trigger count calculator <NUM> calculates the number of cycles (CYCSPS) of the SPS_CLK1 signal that elapse between receiving the first conductor clock message CC_MSG_1 and receiving the second conductor clock message CC_MSG_2. This calculation is performed by subtracting the latched incrementor count value (I_CNT) from the first counter value (C1). In the described example, CYCSPS = (<NUM> - <NUM>) = <NUM> cycles of the SPS_CLK1 signal.

In Step <NUM>, calculator <NUM> determines the number of cycles (CYCCS) of the CS_CLK signal that elapse between receiving the first conductor clock message CC_MSG_1 and receiving the second conductor clock message CC_MSG_2. This calculation is performed by subtracting the second counter value (C2) from the first counter value (C1). In the described example, CYCCS = (<NUM> - <NUM>) = <NUM> cycles of the CS_CLK signal.

In Step <NUM>, calculator <NUM> determines the ratio (FRATIO) of the frequency of the CS_CLK signal to the frequency of the SPS_CLK1 signal. This calculation is performed by dividing CYCSPS by CYCCS. In the described example, FRATIO = <NUM>/<NUM> = <NUM>.

In Step <NUM>, calculator <NUM> converts the CCLK_TRIG_DELAY value from a number of cycles of the CS_CLK signal to a number of cycles of the SPS_CLK1 signal by multiplying the CCLK_TRIG_DELAY value by FRATIO. The converted CCLK_TRIG_DELAY value is designated CCLK_TRIG_DELAYSPS. In the described example, CCLK_TRIG_DELAYSPS = (<NUM> * <NUM>) = <NUM> cycles of the SPS_CLK1 signal.

In Step <NUM>, calculator <NUM> converts the CS-TO-SPS_DELAY_TIME value from a time value to a number of cycles of the SPS_CLK1 signal by multiplying the CS-TO-SPS_DELAY_TIME value by the frequency of the SPS_CLK1 signal. The converted CS-TO-SPS_DELAY_TIME value is designated CS-TO-SPS_DELAY_CYCSPS. In the described example, CS-TO-SPS_DELAY_CYCSPS = (<NUM> microseconds * <NUM>) = <NUM> cycles of the SPS_CLK1 signal.

In Step <NUM>, calculator <NUM> determines the number of cycles of the SPS_CLK1 signal that will elapse until the CCLK modulo counter <NUM> reaches the full count of FULL_CNT. This calculation is performed by subtracting the CS-TO-SPS_DELAY_CYCSPS value from the CCLK_TRIG_DELAYSPS value. This calculated number of cycles is the initial decrementor value DEC_0. In the described example, DEC_0 = (<NUM> - <NUM>) = <NUM> cycles of the SPS_CLK1 signal.

Returning now to <FIG>, in Step <NUM>, calculator <NUM> loads the initial decrementor value DEC_0 (e.g., <NUM>) into decrementor <NUM>. Decrementor <NUM> counts down from the initial decrementor value DEC_0 in response to the SPS_CLK1 signal (Step <NUM>). The count of decrementor <NUM> is provided to one input of comparator <NUM>, and the other input of comparator <NUM> receives a zero value (<FIG>). When the count of decrementor <NUM> reaches a zero value (e.g., after <NUM> cycles of the SPS_CLK1 signal elapse), comparator <NUM> detects a match and activates an edge of the conductor clock signal CCLK1. This edge of conductor clock signal CCLK1 is used to read digital audio samples from output sample buffer <NUM> and digital-to-analog converters <NUM>, as described above.

<FIG> is a timing diagram <NUM> that illustrates the transmission of first conductor clock messages CC_MSG_1, CC_MSG_1' and CC_MSG_1" (at times T<NUM>, T<NUM> and T<NUM>, respectively) and the transmission of second conductor clock messages CC_MSG_2, CC_MSG_2' and CC_MSG_2" (at times T<NUM>, T<NUM> and T<NUM>, respectively) by control station <NUM> within allocated transmission windows <NUM>, <NUM> and <NUM>, respectively. The CCLK modulo counter <NUM> of control station <NUM> reaches the FULL_CNT value at times T1, T2 and T3.

Timing diagram <NUM> also shows that SPS <NUM> receives the first conductor clock messages CC_MSG_1, CC_MSG_1' and CC_MSG_1" at times T<NUM>, T<NUM> and T<NUM>, respectively, and that SPS <NUM> receives the second conductor clock messages CC_MSG_2, CC_MSG_2' and CC_MSG_2" at times T<NUM>, T<NUM> and T<NUM>, respectively. In addition, SPS <NUM> receives the first conductor clock messages CC_MSG_1, CC_MSG_1' and CC_MSG_1" at times T<NUM>, T<NUM> and T<NUM>, respectively, and SPS <NUM> receives the second conductor clock messages CC_MSG_2, CC_MSG_2' and CC MSG <NUM>" at times T<NUM>, T<NUM> and T<NUM>, respectively. In the manner described above, sound production stations <NUM> and <NUM> will assert active edges of their corresponding conductor clock signals CCLK1 and CCLK2, respectively, at times T1, T2 and T3, in synchronism with the CCLK modulo counter <NUM> reaching the FULL_CNT value. This synchronism is maintained, even though sound production stations <NUM> and <NUM> have different CS-TO-SPS_DELAY_TIME values in the illustrated example (i.e., the transmission delay to SPS <NUM> (e.g., T<NUM>-T<NUM>) is longer than the transmission delay to SPS <NUM> (e.g., T<NUM>-T<NUM>), sound production stations <NUM> and <NUM> activate the local conductor clock signals CCLK1 and CCLK2 at the same time that the CCLK modulo counter <NUM> reaches the FULL_CNT value (e.g., at times T1, T2 and T3). This synchronism is also maintained even though the transmission windows <NUM>-<NUM> are allocated at different intervals within the period defined by CCLK modulo counter <NUM> in the present example (e.g., T<NUM>-T<NUM> is less than T<NUM>-T<NUM>). This synchronism is also maintained even though the second conductor clock messages CC_MSG_2, CC_MSG_2' and CC_MSG_2" are transmitted different numbers of clock cycles after the corresponding first conductor clock messages CC_MSG_1, CC_MSG_1' and CC_MSG_1" within the respective transmission windows <NUM>, <NUM> and <NUM> (e.g., T<NUM>-T<NUM> > T<NUM>-T<NUM> > T<NUM>-T<NUM>).

Note that if the inherent timing constraints of the system cannot be met (e.g., the CS-TO-SPS_DELAY_TIME values are too long to allow the local conductor clock signals CCLK1 and/or CCLK2 to be generated), then the control station <NUM> can generate a CS_CLK clock signal having a lower frequency, and the SPSs <NUM> and <NUM> can use a local clock multiplier to generate the local conductor clock signals CCLK1 and CCLK2. For example, if the CS-TO-SPS_DELAY_TIME is longer than the period of the desired local conductor clock signals CCLK1/CCLK2 (e.g., <NUM> microseconds for a <NUM> clock signal), then the modulo counter <NUM> in the control station <NUM> is modified to increase the full count value FULL_CNT. Note that full count value FULL_CNT is increased to a value that ensures that the conductor clock messages CC_MSG_1 and CC_MSG_2 are received by the SPSs <NUM> and <NUM> prior to the modulo counter <NUM> becoming full (taking the CS-TO-SPS_DELAY_TIME into account).

In one example, the full count value FULL_CNT is increased (doubled) to a value of <NUM>. Under these conditions, the SPSs <NUM> and <NUM> will generate local conductor clock signals CCLK1 and CCLK2 that have frequencies of <NUM> (and are synchronized with the full count of modulo counter <NUM>). Local clock multipliers within SPSs <NUM> and <NUM> are used to increase the frequency of the local conductor clock signals CCLK1 and CCLK2 to the desired audio sampling frequency. For example, a 2x clock multiplier circuit will increase the <NUM> local conductor clock signals CCLK1 and CCLK2 to the desired <NUM> audio sampling clock signals in the above-described examples.

Decoupling the conductor clock message channel <NUM> from the playback stream message channel <NUM> in the manner described above advantageously provides improved timing for the playback of audio signals within SPSs <NUM> and <NUM>.

The present invention addresses the multiple access problem introduced by the use of a shared wireless network (e.g., and <NUM> wireless network) by allowing the playback stream data to be buffered within the sound production stations <NUM> and <NUM>. As a result, the times at which the playback messages are transmitted do not have to as precise as in a 'just-in-time' system. This is important because the data payload of the playback messages are relatively large, which can result in transmission access delays in a multiple access wireless medium. As described above, the conductor clock messages are relatively short, so it is much easier to ensure that these messages are transmitted using the QoS feature of the multiple access wireless medium. In addition, a little jitter can be tolerated in the conductor clock messages (because it is the delay between the transmission of first and second conductor clock messages that is used to generate the local conductor clock signals in the sound production stations).

Moreover, using a widely deployed standardized wireless technology such as an <NUM> network provides several advantages, including (<NUM>) available bandwidth of the <NUM> standard is ever increasing, (<NUM>) the availability of components and expertise is readily available and (<NUM>) many devices already in the market are compatible with the <NUM> standard.

Although cognitive loudspeaker system <NUM> can process any playback stream format by installing the appropriate playback executable <NUM> in each of the sound production stations <NUM>/<NUM>, the playback stream format is generally defined by the variants of: (<NUM>) time samples, and (<NUM>) time-frequency samples.

In the time sample variant, an analog waveform is sampled at a sampling frequency. Each time sample will allow the playback of one sample in a period of the sampling frequency. For example, a <NUM> sampling frequency will allow the playback of one sample every <NUM> microseconds. Pulse code modulation (PCM) is one example of a time sampling variant.

In one embodiment, cognitive loudspeaker system <NUM> operates in the following manner when implementing playback stream messages in accordance with the time sample variant. In this embodiment, the conductor clock message channel <NUM> is implemented by a WiFi channel in accordance with the IEEE <NUM> standard, and the playback stream channel <NUM> is implemented using powerline Ethernet. The playback stream FIFO <NUM> within each sound production station is provisioned to store N time samples. The control station <NUM> transmits the first N time samples to the sound production stations through the playback stream channel <NUM>. After transmitting the first N time samples, the control station <NUM> starts transmitting the conductor clock messages on conductor clock channel <NUM>, thereby enabling the conductor clock within each sound production station. During each conductor clock period, the control station <NUM> transmits the next time sample on playback stream channel <NUM>. Because the bandwidth of the playback stream channel <NUM> (typically on the order of Gb/sec) is much higher than the required bandwidth of the playback stream (typically on the order of Mb/sec), and all of the sound production stations are typically situated in the same room, the probability of a playback message being dropped or delayed beyond the period of the conductor clock signal CCLK1 is very low.

In the time-frequency sample variant, an analog waveform is sampled at a sampling frequency over a timing window that includes a plurality of N time samples. The N time samples are transformed into N frequency samples using a transform algorithm (e.g., a modified cosine transform). Typically, a lossy compression will be performed to lower the bit rate required to transport the data. To play back the audio stream, the sound production station performs the inverse transform on the N frequency samples to reconstruct the N timing samples. Each time-frequency sample will allow the playback of N samples during a period equal to N * the period of the sampling frequency. For example, if the timing window includes <NUM> samples and the sampling frequency is <NUM>, then playback of these <NUM> samples will occur over a period of <NUM> milliseconds (<NUM> * <NUM> microseconds).

In one embodiment, cognitive loudspeaker system <NUM> operates in the following manner when implementing playback stream messages in accordance with the time-frequency sample variant. In this embodiment, the conductor clock message channel <NUM> is implemented by a UWB interface, and the playback stream channel <NUM> is implemented by a WiFi channel in accordance with the IEEE <NUM> standard. The control station <NUM> initially requests the bandwidth of the required bit rate to transport the time-frequency playback samples, as well as the opportunity to transmit these time-frequency playback samples within a transmit window from the <NUM> networks in the area. The playback stream FIFO <NUM> within each sound production station is provisioned to store the first N time-frequency samples. The control station <NUM> transmits the first N time-frequency samples to the sound production stations during the allocated transmit window. After transmitting the first N time-frequency samples, the control station <NUM> starts transmitting the conductor clock messages on conductor clock channel <NUM>, thereby enabling the conductor clock within each sound production station. During each allocated transmit window, the control station <NUM> transmits the next set of time-frequency samples on playback stream channel <NUM>. An additional flow control mechanism is available for the control station <NUM> to control the flow of the time-frequency samples. If the allocated bandwidth is relatively low and/or the allocated transmit window is relatively short, then the control station <NUM> can apply a more aggressive level of compression to reduce the bit rate of the time-frequency samples. In this case, the control station <NUM> can transmit multiple lower bit rate time-frequency samples within the allocated transmit window.

Claim 1:
A system (<NUM>) comprising:
a control station (<NUM>) that transmits clock control messages and separate playback messages, wherein the clock control messages are generated in response to a first clock signal (CS_CLK) within the control station; and
a first sound production station, SPS, (<NUM>) that receives the clock control messages and the playback messages, wherein the first SPS includes:
a first clock generation circuit (<NUM>) that generates a first local conductor clock signal (CCLK1) in response to the received clock control messages and a first SPS clock signal (SPS CLK1) generated within the first SPS,
a first playback processor (<NUM>) that generates first digital playback samples in response to the received playback messages, and
a first memory (<NUM>) that receives and stores the first digital playback samples from the first playback processor wherein the first digital playback samples are stored in the first memory in response to the first SPS clock signal (SPS CLK1),
wherein the first memory outputs the first digital playback samples in response to the first local conductor clock signal (CCLK1),
wherein the control station further comprises a counter (<NUM>) having a count that cyclically changes from an initial count value to a final count value in response to the first clock signal (CS_CLK),
wherein a time required to count from the initial count value to the final count value corresponds with a period of the first local conductor clock signal, and wherein the clock control messages include:
a first clock control message that includes a first count value (Cl) of the counter within a period of the first local conductor clock signal (CCLK1,
wherein the first count value indicates when the first clock control message is transmitted, and
a second clock control message that includes a second count value (C2) of the counter within the period of the first local conductor clock signal (CCLK1),
wherein the second count value indicates when the second clock control message is transmitted, and a third count value (C3) that specifies a difference between the second count value and the final count value of the counter,
wherein the first clock generation circuit includes circuitry that generates the first local conductor clock signal in response to the first, second and third count values.