Patent Description:
Radio transceivers can be used in a wide variety of radio frequency (RF) communication systems. For example, transceivers can be included in base stations or mobile devices to transmit and receive signals associated with a wide variety of communications standards, including, for example, cellular and/or wireless local area network (WLAN) standards. Transceivers can also be used in radar systems, instrumentation, industrial electronics, military electronics, laptop computers, digital radios, and/or other electronics.

RF communication systems can also include power amplifiers for amplifying RF transmit signals from transceivers to power levels suitable for wireless transmission. Various types of power amplifiers exist, including power amplifiers utilizing silicon (Si)-based devices, gallium arsenide (GaAs)-based devices, indium phosphide (InP)-based devices, silicon carbide (SiC)-based devices, and gallium nitride (GaN)-based devices. Various types of power amplifiers can offer different advantages in terms of cost, performance, and/or frequency of operation. For example, while Si-based power amplifiers generally provide lower fabrication cost, some Si-based power amplifiers are inferior compared to their compound semiconductor counterparts in terms of certain performance metrics.

<CIT> relates to a digital predistortion (DPD) system that includes an input configured to receive a DPD input signal. The DPD system includes a first predistortion circuit configured to provide a first signal path coupled to the input to generate a first predistortion signal. The first predistortion circuit includes a first infinite impulse response (IIR) filter. A second predistortion circuit is configured to provide a second signal path coupled to the input in parallel with the first signal path to generate a second predistortion signal. The second predistortion circuit includes a second IIR filter. A combiner circuit is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

<NPL>, proposes a new behavioral model for power amplifiers by projecting the classical Volterra series onto a set of Orthonormal Basis Functions (Laguerre functions).

<NPL>, proposes novel models based on infinite impulse response fixed pole expansion techniques for the behavioral modeling and digital predistortion of single-input single-output (SISO) and concurrent dual-band GaN PAs.

<CIT> relates to a wideband enhanced digital injection predistortion system and method.

According to an aspect of the present disclosure, there is provided a radio frequency power semiconductor device as set out in claim <NUM>.

In some embodiments, a first filter of the first plurality of IIR filters comprises a low pass filter (LPF).

In some embodiments, a second filter of the first plurality of IIR filters comprises an all-pass filter.

In some embodiments, the first plurality of IIR filters are orthogonal to each other.

In some embodiments, the first non-linear filter network comprises a plurality of IIR filters <NUM> to N arranged in series, wherein the plurality of IIR filters <NUM> to N are arranged in parallel.

In some embodiments, the device further comprises <NUM> to N corrective elements corresponding to the plurality of IIR filters <NUM> to N, wherein the <NUM> to N corrective elements receive the envelope of the input signal and correct for the non-linear portion of the power amplifier before the corrected signal propagates through the corresponding plurality of IIR filters.

In some embodiments, correcting for the non-linear portion of the power amplifier comprises, for each of the <NUM> to N corrective elements, applying an exponential to the envelope of the signal.

In some embodiments, the device further comprises: the compound semiconductor power amplifier.

In some embodiments, the compound semiconductor power amplifier comprises a Gallium Nitride (GaN) power amplifier.

In some embodiments, the device further comprises: a down sampler to down sample an input signal and transmit the down sampled signal to the first non-linear filter network; and an up sampler to up sample the output of the first non-linear filter network.

In some embodiments, the device further comprises: a mixer to mix the output of the first non-linear filter network with the input of the first non-linear filter network; and a first buffer configured to delay the input of the first non-linear filter network to match the timing of the signal with the output of the first non-linear filter network.

In some embodiments, the device further comprises: a crest factor reduction function; wherein the crest factor reduction function is connected in series with the second non-linear filter network.

According to an aspect of the present disclosure, there is provided a method of digital predistortion as set out in claim <NUM>.

Power devices such as radio frequency (RF) power devices are used in many applications, e.g., wireless technologies. For various applications, power devices are based on silicon technology, e.g., Si-based laterally diffused metal oxide semiconductor (LDMOS) devices. For some applications, compound semiconductors, such as III-V materials, have advantages for high frequency operation. For example, gallium nitride (GaN)-based power devices, e.g., DC/LF and RF power devices, have been proposed. Compound semiconductor power devices, such as GaN-based power devices, have been predicted to have advantages over Si-based technologies in some applications, e.g., in process architectures where drain modulation is applied. The expected advantages include improvements in efficiency and frequency range (e.g., higher unity gain cutoff frequency or fT), among other advantages.

GaN has widely been used in various applications, including light emitting diode (LED) devices. While the interest in GaN RF power devices for various other commercial applications has been steadily rising, the implementation of GaN-based power devices including RF power devices has been largely limited to low volume applications such as military/aerospace. The limited implementation has been due in part due to fabrication costs, which are currently significantly higher than Si-based technologies. There are currently two main types of GaN RF power devices, including GaN-on-insulator technology and GaN-on-Si technology. While the former has higher performance, wafer fabrication costs are also higher.

In addition to cost considerations, certain technological improvements are sought after in GaN-based power devices. One such improvement is associated with addressing relatively narrowband distortion effects that have been observed in GaN-based power devices. Without being limited to any particular theory, it is believed that charge-trapping effects result in significant variation in the device characteristics, including variations in gain linearity of the GaN-based power devices. The charge-trapping is believed to be a function of the long-term history of the input signal, whose effects can last on the order of milliseconds to seconds. A term that has been used to express this effect is "current collapse," which is used to describe an effect whereby the drain current collapses to a level less than expected upon applying a high-power RF pulse to the GaN transistor.

Effects of charge trapping include, but are not limited to, transconductance frequency dispersion, current collapse of the direct current drain characteristics, gate-lag transients, drain-lag transients, and/or restricted microwave power output.

Accordingly, as the power is being modulated, charges can get trapped and then released at a low frequency, which results in a low frequency modulation of the gain which causes distortion. Thus, there is a need to mitigate or compensate for the charge-trapping effects in GaN-based power devices as well as other types of power devices.

<FIG>, <FIG>, and <FIG> include graphs <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, and <NUM>, <NUM>, and <NUM> that illustrate the low frequency modulation of the gain, according to some embodiments. Graph <NUM> illustrates the Error Vector Magnitude (EVM) over time. Graph <NUM> illustrates the input Amplitude-Modulated (AM) signal in dB over time. The input amplitude-modulated signal is applied to a GaN amplifier, which produces a low frequency gain modulation. Graph <NUM> illustrates the Low Frequency (LF) gain in dB over time where the gain is measured across a <NUM> to <NUM> BW. Graphs <NUM>, <NUM>, and <NUM> of <FIG> are close-up snippets <NUM> of the graphs <NUM>, <NUM>, and <NUM> of <FIG>, respectively.

As shown in graph <NUM>, a pulsing occurs in the input amplitude modulated signal. Graph <NUM> illustrates low signals, such as between <NUM>-<NUM> milliseconds, and a high signal, such as between <NUM>-<NUM> milliseconds. However, the signals are pulsing when both in the high and low signal state. Graph <NUM> illustrates the corresponding low frequency gain for the input amplitude modulated signal of graph <NUM>. As illustrated, the low frequency gains are showing a modulation effect.

Graphs <NUM>, <NUM>, <NUM>, and <NUM> illustrate the charge trapping effect and the slow relaxation effect in more detail. Graph <NUM> illustrates the input amplitude-modulated signal in dB over time, and graph <NUM> illustrates the input amplitude-modulated signal in voltage over time. Graph <NUM> illustrates the charge trap gain in dB over time, and graph <NUM> illustrates the charge trap correction gain over time. When going from low to high power, such as from the transition between t<NUM> to t<NUM>, the increased input results in charges moving from one layer to another inside the power amplifier. When the power goes from low to high, some of the charges get trapped. The trapping effect is relatively fast. This is the charge trapping effect. When the input transitions from high to low power, such as the transition between t<NUM> to t<NUM>, the charges are released, but the charges are released back with slower time constants. Those time constants can be in the order of hundreds of microseconds. All of the charge trapping and discharging generate a low frequency gain modulation, which is a distortion effect in the power amplifier.

Power amplifiers are nonlinear devices whose gain can expand and compress as a function of the current and past input amplitude. In laterally-diffused metal-oxide-semiconductor (LDMOS) devices this gain modulation can encompasses past amplitude values extending back ~10ns to ~100ns, while GaN devices the nonlinear memory can extend back us, ms, or even seconds. In some embodiments, the sampling frequency can be between <NUM>-<NUM>. In some embodiments, the actuators of these systems can be trained over a window of time between <NUM> nanosecond to <NUM> nanoseconds, <NUM> nanoseconds to <NUM> nanoseconds, <NUM> nanoseconds to <NUM> nanoseconds, <NUM> nanoseconds to <NUM> nanoseconds, <NUM> nanoseconds to <NUM> nanoseconds, and/or the like.

The issue with such an approach as applied to low frequency charge trapping is that when these typical systems determine correction for digital predistortion (DPD), the systems can use a solver, such as a least squares solver. These least squares solvers use linear algebra in the finite input pulse (FIR) filters. Truncated Volterra series down to a generalized memory polynomial can be used for the FIR filters.

For charge trapping effects at low frequencies, the time constants can be <NUM> or <NUM>,<NUM> times longer. As an example, if on a power amplifier, the charge trapping effect extends <NUM> milliseconds in time, these typical systems would have to store data that extend at least over <NUM> milliseconds. The vectors and matrices used for high frequency DPD distortion may require <NUM> to <NUM> columns in the matrices. However, for the low frequency charge trapping effects, the FIR filter computations would now have thousands or tens of thousands of entries. Typical FIR filters use moving averages of weighted inputs and to increase the order of magnitude of the taps in the FIR filters, which make such processing very complex.

Such computation may result in numerical instability in simulations, delays in latency to the antenna element, and increased circuit footprint and power consumption. Moreover, linear algebra can be used to train and adapt the DPD, and a large dimension system of equations would be costly and numerically unstable. Furthermore, if we build the DPD actuator with FIRs that extend back in memory <NUM>,<NUM> of samples, the DPD actuator would simply be too costly and require a lot of power.

To be able to use typical systems to correct for charge trapping effects, the FIR filters would have to filter through time constraints over thousands of samples. This would involve an exorbitant amount of hardware storing each iteration of the FIR filters, and involve a lot of power consumption. These typical systems are not practical for transceivers and antenna processing chips, where processing power and circuitry footprints are limited. Moreover, computers may not have the processing power to even prove such a concept in a simulator. From a numerical computation point of view, the computations required in the FIR filters would become too complicated and large.

Furthermore, another deficiency of such an approach are the non-linear terms at the input of the FIR filters to model the non-linear nature of DPD. These typical systems may now have thousands of taps, where the system may transmit an absolute value of a signal to a first tap, the squared of the absolute value of the signal to a second tap, a cubed of the absolute value of the signal to a third tap, and so forth, resulting again in the deficiencies described herein, such as increased circuit footprint and power consumption.

Described herein are systems and methods that solve or mitigate the problem of charge-trapping effects. Some embodiments include a radio frequency (RF) power semiconductor device configured to correct for charge trapping effects. In some embodiments, the RF semiconductor device can correct for both charge trapping effects and broadband distortion of the power amplifier.

<FIG> illustrates an RF semiconductor device <NUM> including a first non-linear filter network to correct narrow band distortion and a second non-linear filter network to correct broad band distortion, according to some embodiments. The device can include an actuator <NUM>, a power amplifier <NUM> (including a FET, such as a GaN FET, in this example), a least squares module <NUM>, and a feedback actuator <NUM>.

As shown in <FIG>, the actuator <NUM> can include a first non-linear filter network <NUM> configured to compensate for narrowband distortion of a power amplifier, such as frequencies from <NUM> to <NUM>. The first non-linear filter network <NUM> can comprise a plurality of non-linear filters, such as infinite impulse response (IIR) filters. The IIR filters can collectively function as a Laguerre filter, in this embodiment. The first non-linear filter network <NUM> can comprise a cascade or a chain of IIR filters. In some embodiments, the first filter is a low pass filter, and the following filters in the chain of IIR filters are all pass filters. In some embodiments, the filters of the first non-linear filter network <NUM> are orthogonal to each other. The use of IIR filters enables the system to use long time constants to account for the narrowband charge trap effect. Laguerre filters have not been known to be used for correcting narrowband charge trapping effects.

In some embodiments, the second non-linear filter network <NUM> can be configured to compensate for broadband distortion of the power amplifier. The second non-linear filter network <NUM> can comprise a plurality of non-linear filters, such as finite impulse response (FIR) filters. The FIR filters can collectively function as a general memory polynomial (GMP) filter. In some embodiments, the second non-linear filter network <NUM> can include digital predistortion (DPD) systems and/or DPD filter networks that compensate for broadband distortion.

In some embodiments, the input signal x is fed into the first non-linear filter network <NUM> to generate a signal to compensate for the narrowband distortion. The same input signal can be fed into the second non-linear filter network <NUM> to compensate for the broadband distortion. A combination of the output of the first non-linear filter network <NUM> and the second non-linear filter network <NUM> is added by the adder <NUM>. The output of the adder <NUM> is fed into the power amplifier <NUM>. In some embodiments, the input signal x corresponds to a stream of digital data (such as in-phase (I) and quadrature-phase (Q) data) provided by a baseband processor.

Although shown as being directly provided to the power amplifier <NUM>, the output of the adder <NUM> can correspond to digital pre-distorted transmit data that is processed by one or more, digital-to-analog converters (DACs), one or more mixers, one or more variable gain amplifiers (VGAs), and/or other circuitry to generate an RF transmit signal provided to an input of the power amplifier <NUM>.

In some embodiments, the output and the input to the power amplifier <NUM> is also used to fit an inverse model, such as the feedback actuator <NUM>. The output of the power amplifier <NUM> can be fed into another first non-linear filter network <NUM> and another second non-linear filter network <NUM>. In some embodiments, the input power and/or output power of the power amplifier <NUM> is captured by a directional coupler, and then processed by an observation receiver to generate a digital representation of the observed power.

With continuing reference to <FIG>, the output of the other first non-linear filter network <NUM> and other second non-linear filter network <NUM> are added by the adder <NUM>. Then, the input of the power amplifier <NUM> is subtracted by the output of the adder <NUM> via another adder <NUM>. The output of the other adder <NUM> is processed through a least squares module <NUM>. The output of the least squares module <NUM> is used by the other second non-linear filter network <NUM>.

In some embodiments, the feedback actuator can comprise a first non-linear filter network, such as a Laguerre filter, and a second non-linear filter network, such as a GMP filter.

In some embodiments, the first non-linear filter network is arranged in parallel with the second non-linear filter network. In other embodiments, the first non-linear filter network is arranged in series with the second non-linear filter network. The first non-linear filter network is arranged after the second non-linear filter network, where the second non-linear filter network accommodates for the high frequency distortion, and the first non-linear filter network accommodates for the low frequency charge trapping distortion.

The power amplifier <NUM> amplifies an RF signal having a carrier frequency. Additionally, the narrowband distortion corrected by the first non-linear filter network <NUM> (for instance, a Laguerre filter) can correspond to distortion surrounding a limited bandwidth around the carrier frequency and occurring over long timescales associated with the charge trapping dynamics. For example, a bandwidth BW around the carrier frequency can be inversely proportional to a time constant τ (BW ∝ <NUM>/τ), and thus charge trapping effects are associated with long time constants and narrow bandwidth. Such narrowband distortion is also referred to herein as low frequency noise of a power amplifier.

The broadband distortion corrected by the second non-linear filter network <NUM> (for instance, a GMP filter) can include non-linearity in the power amplifier (non-charge trap nonlinearities) occurring over much shorter time scales than the narrowband distortion. Thus, the time constant associated with such non-linearity is small and the corresponding bandwidth is wide. Such broadband distortion is also referred to herein as high frequency noise of a power amplifier.

<FIG> illustrates an example architecture of a first non-linear filter network, according to some embodiments. In some embodiments, the first non-linear filter network <NUM> can include an absolute value block <NUM>, corrective elements 254A, 254B, 254N, a plurality of stages (<NUM> to N) 256A, 256B, 256N, an adder <NUM>, and a multiplier <NUM>. Each stage 256A, 256B, 256N can include a plurality (<NUM> to M) of non-linear filters. Each (or at least some) of the <NUM> to M of filters can include a first non-linear low pass filter (LPF) 262A, 262B, 262N, and possibly one or more non-linear all pass filter 264A, 264B, 264N, 266A, 266B, 266N. For each stage 256A, 256B, 256N, the LPF and possibly one or more all pass filter can be arranged in series. The LPF filter can receive a signal, process the signal through the LPF, output the signal to a series of all-pass filters, and process the signal through the all-pass filters. In some embodiments, the filters of the first non-linear filter network are orthogonal to each other. For example, the LPF can allow signals with frequencies lower than a certain cutoff frequency to pass through the LPF, and the subsequent all-pass filters can allow signals to pass with only a phase modification and no or minimal effect on the magnitude. The nonlinear functions F(vkl) in <FIG> and <FIG> can include a memory polynomial expansion of vkl, for example <MAT>.

In some embodiments, the stages 256A, 256B, 256N (e.g., the <NUM> to M filters, each stage can include a LPF and possibly one or more all-pass filters) are arranged in parallel to each other. In some embodiments, each of the <NUM> to M of filters include a corrective element, described in further detail herein. Each of the stages 256A, 256B, 256N can account for a different time constant, as the charge trap distortion can occur in multiple responses across various time scales.

In some embodiments, a complex baseband signal is received from the digital upconverter (x), which can include an in-phase and quadrature-phase (I/Q) signal. The device generates an envelope of the signal by determining an absolute signal of the complex baseband signal via the absolute value block <NUM>. For example, a coordinate rotation digital computation (CORDIC) circuit can be used for processing digital I and digital Q data to generate a digital envelope. The absolute value block <NUM> outputs the envelope of the signal.

In some embodiments, the device propagates the output of the absolute value block <NUM> to a plurality of corrective elements 254A, 254B, 254N. The plurality of corrective elements 254A, 254B, 254N introduce non-linearity to the signal. For example, the plurality of corrective elements (e.g., <NUM> to N corrective elements) 254A, 254B, 254N can take exponentials of the outputs of the absolute value block <NUM>. The first corrective element 254A can take a <NUM> exponential of the output of the absolute value block <NUM>. The second corrective element 254B can take a <NUM> exponential of the output of the absolute value block <NUM>. The N corrective element 254N can take an N exponential of the output of the absolute value block <NUM>. For example, <FIG> illustrates that the output of the absolute value block <NUM> (e.g., | |) is sent to three corrective elements 254A, 254B, 254N. The first corrective element 254A takes a <NUM> exponential ( ( )<NUM>), which is essentially the same as the output of the absolute value block <NUM>. The output is sent to a first plurality of non-linear Laguerre filters 256A. The second corrective element 254B takes a <NUM> exponential ( ( )<NUM>), and sends the output to a second plurality of non-linear Laguerre filters 256B. The third corrective element 254N can takes the nth exponential ( ( )n), and sends the output to a third plurality of non-linear Laguerre filters 256N. Thus, the corrective elements 254A, 254B, 254N take non-linear powers of the envelope.

In some embodiments, the outputs of the <NUM> to N corrective elements 254A, 254B, 254N are propagated to corresponding <NUM> to N plurality of non-linear filters 256A, 256B, 256N, such as <NUM> to N Laguerre filters. The first filters 262A, 262B, 262N can include low pass filters, and the remaining filters 264A, 264B, 264N, 266A, 266B, 266N can include all-pass filters. The following are numerical representations of the Low Pass Filter (LPF) and the all-pass Filters (BPF). <MAT>
<MAT> <MAT>.

The a<NUM> is a filter coefficient, Fs is the sampling rate (e.g., in the <NUM> range), and τ is a time constant (e.g., microseconds, milliseconds) of the charge trap effect. The time constant can be determined by looking at the charge trap effect of the power amplifier. Then, the a<NUM> filter coefficient can be determined.

In some embodiments, the outputs of the <NUM> to N plurality of non-linear filters 256A, 256B, 256N are summed via an adder <NUM> to generate a low frequency gain term glag. The low frequency gain term glag represents the narrowband frequency correction gain.

In some embodiments, the low frequency gain term glag is multiplied by the complex baseband signal input via the multiplier <NUM> to generate a correction signal to correct for the charge trapping effect ulag.

In some embodiments, the first non-linear network and/or the second non-linear network is at least partially implemented in software (e.g., implemented by the digital signal processor as an all digital solution). In some embodiments, the first non-linear network and/or the second non-linear network is at least partially implemented in firmware.

<FIG> illustrates an architecture of a first non-linear filter network that includes decimation and upsampling functionality, according to some embodiments. The decimation enables the processing of several hundreds of megahertz of data within the device circuitry. Without decimation, the processing of such data can require very expensive components and require large amounts of processing power.

In some embodiments, the digital upconverter <NUM> can feed a signal to a first non-linear filter network <NUM>. The first non-linear filter network <NUM> can include an absolute value block <NUM> and a decimator, such as a cascade integrator comb (CIC) filter <NUM>. The signal from the digital upconverter <NUM> can be processed by the absolute value block <NUM>. The CIC filter <NUM> can decimate the output of the absolute value block <NUM> and transmit the output to the <NUM> to N non-linear filters <NUM>, such as the <NUM> to N Laguerre filters. The decimation enables the architecture to reduce the data rate, such as by an order of <NUM>, in order to create an efficient and practical architecture in the actuator.

In some embodiments, the output of the <NUM> to N non-linear filters <NUM> can be summed by the adder <NUM> to generate the low frequency gain term glag. The low frequency gain term can be upsampled via an upsampler <NUM>, such as a CIC filter, to interpolate the signal back to its original sample frequency. The delay match <NUM> can match the signal from the output of the digital upconverter <NUM> to the output of the upconverter <NUM>, and the output of the delay match <NUM> (which is the complex baseband input time matched with the output of the first non-linear filter network) can be multiplied to the output of the upconverter <NUM> via the multiplier <NUM>. The delay match blocks (e.g., delay match <NUM>) are to compensate for delays as data is processed through various blocks, such as the CIC filters.

In some embodiments, the digital upconverter <NUM> can also feed a signal to a second non-linear filter network <NUM>. The output of the second non-linear filter network <NUM> can be delay matched with the output of the first non-linear filter network <NUM> via a delay match <NUM>. The output of the delay match <NUM> can be added via the adder <NUM> to the output of the second non-linear filter network <NUM>, and the output of the adder <NUM> can be inputted into the power amplifier <NUM>.

<FIG> illustrates an example architecture of a first non-linear filter network including a crest factor reduction function, a first delay block, and second delay block, according to some embodiments. <NUM>/<NUM> transmitters typically use crest factor reduction (CFR) functions. The <NUM>/<NUM> transmitters can be included in user devices, such as mobile devices. The <NUM>/<NUM> transmitters can be included in base stations. The CFR functions can include removing peaks from the envelope of the input signal to avoid or mitigate saturation in the power amplifier. However, CFR functions result in long latency as the signal takes a lot of time to propagate through the CFR functions. Moreover the decimators and upsamplers (for example, CIC) also have delays, which collectively can result in sizable delays. However if the signal were to be delayed by the CFR function and the decimators/upsamplers, the total latency of the transmitter may be too large. To obviate or mitigate this issue, some embodiments include transmitting the output of the digital upconverter directly to the components associated with the first non-linear filter network and to process the second non-linear filter network with the output of the CFR function.

In some embodiments, the output of the Digital Upconverter (DUC) <NUM> can be processed by the absolute value block <NUM>. The absolute value block <NUM> outputs an envelope of the signal to a downconverter (e.g., CIC filter <NUM>). The output of the CIC filter <NUM> is processed through non-linear Laguerre filters and summed by the adder <NUM>. The output of the adder <NUM> is processed through the upconverter (e.g., CIC filter <NUM>) to match the frequency of the signal provided by the DUC <NUM>. In alternative embodiments, the output of the Digital Upconverter (DUC) <NUM> can be processed by the CFR function <NUM>, and the output of the CFR function <NUM> can be inputted to the absolute value block <NUM>.

In some embodiments, the output of the DUC <NUM> is processed through a CFR function <NUM>. The output of the CFR function <NUM> can be sent to a first delay match block <NUM> that delays the output of the CFR function <NUM> to match the output of the upsampler, CIC <NUM>. Then, the multiplier can multiply the output of the CFR function <NUM> with the output of the CIC filter <NUM>.

In some embodiments, the output of the CFR function <NUM> can also be sent to a second non-linear filter network <NUM>, such as a GMP filter. In some embodiments, a second delay block <NUM> delays the output of the multiplier <NUM> to match the output of the second non-linear filter network <NUM>, such as a GMP filter. Then, the output of the second delay block <NUM> can be added to the output of the second non-linear filter network <NUM> by the adder <NUM>. Then, the output of the adder <NUM> can be sent to the power amplifier <NUM>.

In some embodiments, delay blocks, such as the first and/or second delay blocks <NUM>, <NUM>, include one or more shift registers. The shift registers can be connected in series.

<FIG> illustrates an example architecture of an RF semiconductor device for training both first and second non-linear filter networks via a direct learning algorithm, according to some embodiments. The RF semiconductor device compares the observed output y of the power amplifier with the actual input signal x in order to generate an error signal. As such, the direct learning algorithm can train the GMP actuator and subsequently train the Laquerre actuator using the input, x, and the output of the power amplifier <NUM>, y. In alternative embodiments, an indirect learning algorithm can be used to train the GMP and Laquerre actuators, such as by using the difference between the input of the power amplifier <NUM>, u (which is a combined signal of the GMP actuator <NUM> and the nonlinear Laguerre Actuator <NUM> via the adder <NUM>), and the same DPD (GMP and Laguerre) function applied to the output of the power amplifier <NUM>, y.

In some embodiments, an adder <NUM> outputs a difference between the input x to the system and the output y of the power amplifier. The difference is sent to a direct learning algorithm <NUM> that determines an error signal from the difference value. Then, the system can train the GMP actuator <NUM> and the Laguerre actuator <NUM> separately. The system can process the input signal x and collect data, such as the output of the CFR block <NUM> and the output of the power amplifier y, to train the GMP actuator <NUM>. Then the system can switch state machines to set up the system of equations for training the Laguerre actuator <NUM>.

<FIG> illustrates an example architecture for training a GMP actuator, according to some embodiments. <FIG> illustrates an example architecture for training a Laguerre actuator, according to some embodiments.

As illustrated in <FIG> and <FIG>, an RF semiconductor device can train both the GMP actuator and Laguerre actuator. The RF semiconductor device can perform a partial update on the GMP actuator (such as by using the architecture of <FIG>), subsequently perform a partial update on the Laguerre actuator (such as by using the architecture of <FIG>), and thereafter repeat the partial updates of the GMP and Laguerre actuators. Moreover, in the case of training the Laguerre actuator, the RF semiconductor device can down sample the training vectors, which allow the use of a shallow training buffer to capture the training vectors as well as capture data across an extended horizon. For example, a shallow training buffer of <NUM> can be sampled at a <NUM> sampling frequency, which then provides <NUM> of effective buffer depth.

The signal from the digital upconverter <NUM> can be processed by the CFR function <NUM>, the output of the CFR function <NUM> can be processed by the second non-linear filter network <NUM>, and the output of the adder <NUM> can be inputted into the power amplifier <NUM>.

In <FIG>, the output of the CFR function <NUM> and the output of the power amplifier <NUM> is taken to train the GMP actuator. The output of the CFR function <NUM> is processed through a delay match block <NUM> to match the delay between the output of the CFR function <NUM> and the output of the power amplifier <NUM>. Both the output of the delay match block <NUM> and the output of the power amplifier <NUM> fills a corresponding capture buffer <NUM>, <NUM>, respectively. A time alignment block <NUM> aligns the output of the capture buffers <NUM>, <NUM>. Such time alignment can aid in compensating for rate differences between samples captured at the output of the power amplifier <NUM> (at RF frequency) and samples captured at the output of the CFR <NUM> (at baseband frequency). In some embodiments, the delay match block <NUM> can align the output within a certain window of accuracy. The delay match block <NUM> can be a preconfigured delay. The time alignment block <NUM> can further delay the signal by tracking temporal variations in the delay, such as the delay through analog circuitry varying based on processes, supply, temperature, and/or aging. The time alignment block <NUM> can be dynamic, adjusting based on the tracking of temporal variations.

The system builds a matrix Xgmp of GMP features <NUM>, which can include linear and nonlinear terms. The GMP features are sent to the correlation engine <NUM> to process the GMP features. The correlation engine <NUM> can determine a cross-correlation vector rgε between the features Xgmp and the error vector εgmp and the auto-correlation matrix Rgmp to apply to a partial update block <NUM> which can include a solver, such as a least squares solver. The partial update block <NUM> can update the actuator, and the training can repeat again and/or proceed with training the Laguerre actuator.

In some embodiments, the system can cycle the process a plurality of times. The system can capture another buffer of output data from the CFR function <NUM> and output data from the power amplifier <NUM>, generate GMP features, determine an error, and generate another cross-correlation vector which can be added to a previous sum of correction.

In <FIG>, the output of the CFR function <NUM> and the output of the power amplifier <NUM> is used to train the Laguerre actuator. The output of the CIC downsampler <NUM> (which can include the envelope of the input signal decimated down to a lower sampling rate) can be used in the Laguerre actuator training. This output can be delayed by a delay match block <NUM>, and a time align block <NUM> can time align the output of the delay match block <NUM> to match with the time alignment set of the time alignment block <NUM>. The time aligned signal is sent to a capture buffer <NUM>, and then the signal is sent to a Laguerre Features block <NUM> to generate Laguerre features. The capture buffers can be on the order of approximately <NUM>, <NUM>, <NUM>, <NUM>, <NUM> samples long. Because the signal has been downsampled at the output of the CIC downsampler <NUM>, the signals captured at the capture buffer captures data long enough in time to obtain samples through the charging and/or discharging profile. As discussed herein, the time constant effect of charging and discharging, such as in <FIG>, include narrowwband distortion over a longer period of time than typical digital predistortion.

In some embodiments, the Laguerre features <NUM> are sent to a correlation engine <NUM> to process GMP features to determine the cross-correlation vector r<NUM>ε and the auto-correlation matrix Rlag, and a partial update module <NUM> such as a least squares solver. The Laguerre features <NUM>, correlation engine <NUM>, and/or the partial update module <NUM> can be implemented in software, firmware, and/or a combination.

In some embodiments, an initial condition (e.g., v<NUM>) of the non-linear Laguerre filters <NUM> is used to train the Laguerre actuator. The initial condition is to prevent a transient effect in the system of equations that can affect other variables and equations that would result in incorrect outcomes and solutions. In some embodiments, the initial states or conditions can be predetermined. Such an approach may work for systems that have one or two stages of cascade Laguerre filters. However if the system has three, four, five, or more cascade Laguerre filters, the system of equations becomes complex and the charge trap correction becomes more and more incorrect with assumed initial conditions.

In order to mitigate or obviate the deficiencies noted above, some embodiments disclose taking actual initial condition readings from the Laguerre filter actuator. The initial conditions from the non-linear Laguerre filters <NUM> are delayed by a delay match block <NUM>, and a time align block <NUM> can time align the output of the delay match block <NUM>. A capture buffer <NUM> can capture samples of the initial condition, and the initial conditions can be sent to the Laguerre features block <NUM> to generate Laguerre features based on the generating of matrices of Laguerre terms. The initial conditions and initial state of the non-linear Laguerre filters <NUM> are further described in reference with <FIG>.

In some embodiments, the difference between the output of the CFR function <NUM> and the power amplifier <NUM> is used to train the Laguerre actuator. Similar to the embodiment of <FIG>, the output of the CFR function <NUM> is delay matched <NUM> and stored in a capture buffer <NUM>. The output of the power amplifier <NUM> is also stored in a capture buffer <NUM>. The output of the capture buffers <NUM>, <NUM> are time aligned <NUM>, and the difference via an adder <NUM> is sent to the correlation engine <NUM> to determine the cross-correlation vector r<NUM>ε and the auto-correlation matrix Rlag.

In some embodiments, the output of the CFR function <NUM> is downsampled by N via a downsampler <NUM>. The downsampler <NUM> can downsample the output of the CFR function <NUM> to match the decimated rate of the envelope (e.g., the output of block <NUM>). For example, the down sampler can take one input from every <NUM> samples. In some embodiments, the output of the power amplifier <NUM> is downsampled by M via a downsampler <NUM>. The downsampler <NUM> can downsample the output of the power amplifier <NUM> to match the decimated rate of the envelope (e.g., the output of block <NUM>). Thus, the inputs to the two capture buffers <NUM> and <NUM> can be at matching sampling rates. In some embodiments, a downsampler is used instead of a decimation filter, because the downsampled signal is used to fit a model in the correlation engine <NUM> (not to reconstruct the signal). Advantageously, the capture buffer can see data over a much longer period of time. For example, if the capture buffers can only capture <NUM>,<NUM> samples long but the down sampling is by a factor of <NUM>, now the capture buffer can extend the <NUM>,<NUM> samples over <NUM> times. So if the capture buffer alone could only see <NUM> microseconds of data, the capture buffer with the downsampling can now save data over <NUM> millisecond. Such downsampling enables the system to capture narrowband, slower transient effects.

In some embodiments, the training for the GMP actuator (e.g., <FIG>) and the training for the Laguerre actuator (e.g., <FIG>) occur in series and/or do not occur concurrently. Thus, the capture buffers can be reused. For example, the system can power on the power amplifier and other hardware, capture data and train the GMP actuator, capture data and train the Laguerre actuator, and repeat both training. Advantageously because of reuse of certain components, the system can be smaller and use less components.

<FIG> illustrates an example architecture for identifying initial conditions for the Laguerre actuator training, according to some embodiments. The Laguerre actuator <NUM> receives the signal, generates an envelope of the signal via the absolute value block <NUM>, applies non-linear correction via a corrective element <NUM> (e.g., by applying a power to the signal such as the signal squared or cubed), and passes the signal through the Laguerre filters <NUM>, <NUM>, <NUM>. One or more Laguerre filters can include an autoregressive term, where the output of each of the filters are delayed via the TX-ORX Delay <NUM> and fed into the Laguerre training model <NUM> in a feedback loop. The term that is fed is the initial phase that is used in the Laguerre training model <NUM>. The Laguerre training model then receives a signal and again, generates an envelope of the signal via the absolute value block <NUM>, applies non-linear correction via a corrective element <NUM> (e.g., by applying a power to the signal such as the signal squared or cubed), and passes the signal through the Laguerre filters <NUM>, <NUM>, <NUM>. However, the Laguerre filters <NUM>, <NUM>, <NUM> of the Laguerre training model <NUM> receive the initial conditions where the initial conditions are weighted via the equations <NUM>, <NUM> and adders <NUM>, <NUM>. vkl DPD is the actuator internal state. v̂kl DPD is the training model internal state. vkl(n - D) = vklz-D is the previous internal state of Laguerre Filter. z-D is the time delay. Stage <NUM> of the Laguerre actuator is initialized to v̂k<NUM>(<NUM>) = -a<NUM>vk0(n - <NUM>)z-D and the remaining stages are initialized to v̂kl(<NUM>) = -a<NUM>vkl(n - <NUM>)z-D + b<NUM>vk(l-<NUM>)(n - <NUM>)z-D. The term v̂ is used to generate the Laguerre features, as described herein such as with relation to <FIG>.

<FIG> illustrates an example architecture for an RF semiconductor device to train both the GMP and Laguerre actuators simultaneously, according to some embodiments. In some embodiments, the RF semiconductor device can train the Laguerre actuator without downsampling using this architecture. The RF semiconductor device can capture data from the Laguerre actuator over a long period of time. The capture buffers would capture more data for a longer period of time than the buffers of the prior figures. For example, the RF semiconductor device can capture data in hundreds of megahertz, which can fill the buffers and train over a window of data of tens of microseconds. Then, the RF semiconductor device can retrain the Laguerre actuator again and again, effectively scanning over a window of data of milliseconds. In some embodiments, the sampling frequency can be between <NUM>-<NUM>. In some embodiments, the Laguerre actuator can be trained over a window of time between <NUM> nanoseconds to <NUM> millisecond, <NUM> millisecond to <NUM> milliseconds, and/or the like.

The output of the non-linear Laguerre filters <NUM>, the CFR function <NUM>, and the output of the power amplifier <NUM> are taken, and aligned by the delay match blocks <NUM>, <NUM> and the time alignment blocks <NUM>, <NUM>. The capture buffers <NUM>, <NUM> capture the data. A difference between the output of the CFR function <NUM> and the output of the power amplifier <NUM> is determined via the adder <NUM>. The difference signal from the adder <NUM> is sent to the GMP features generator <NUM>, the Laguerre features generator <NUM>, and the CIC delay match block <NUM>. The Laguerre features generator <NUM> also receives the initial conditions from the time alignment block <NUM>. The GMP features generator <NUM> and the Laguerre features generator <NUM> generate the corresponding polynomials and send the polynomials to the correlation engine <NUM>. The correlation engine <NUM> can determine a cross-correlation vector rgε and the auto-correlation matrix Rgmp for the GMP actuator, and the cross-correlation vector rlε and the auto-correlation matrix Rlag for the Laguerre actuator. The Laguerre Internal State <NUM> is the initialization function explained above with relation to <FIG>, where the internal state of the actuator is identified and converted to the initial state of the Laguerre adaptation.

<FIG> illustrates an RF semiconductor device including a first non-linear filter network comprising FIR filters to correct narrowband distortion and a second non-linear filter network comprising FIR filters to correct broadband distortion, according to some embodiments. The first non-linear filter network <NUM> can include a first non-linear actuator and the second non-linear filter can include a second non-linear actuator <NUM>. The first non-linear filter network <NUM> can be in parallel with the second non-linear filter network <NUM>. The first non-linear filter network <NUM> can include a GMP actuator, a Laguerre actuator, and/or the like. The second non-linear filter network <NUM> can include a GMP actuator, a Laguerre actuator, and/or the like. The output of the first non-linear filter network <NUM> and the second non-linear filter network <NUM> can be added by the adder <NUM> and the combined signal can be sent to the power amplifier <NUM>.

In some embodiments, the device can further comprise a feedback actuator <NUM> that also includes a first non-linear filter network <NUM> that is parallel with a second non-linear filter network <NUM>. The feedback actuator <NUM> can receive the input and output of the power amplifier <NUM>, used to fit an inverse model. The output of the power amplifier <NUM> can be fed into another first non-linear filter network <NUM> and another second first non-linear filter network <NUM>. The output of the other first non-linear filter network <NUM> and other second non-linear filter network <NUM> are added by the adder <NUM>. Then, the input of the power amplifier <NUM> is subtracted by the output of the adder <NUM> via another adder <NUM>. The output of the adder <NUM> is processed through a least squares module <NUM>. The output of the least squares module <NUM> is used by the other second non-linear filter network <NUM>. The system can use other solvers other than the least squares module <NUM>.

In some embodiments, the first non-linear filter network <NUM> can have a certain sample rate to correct for narrowband distortion by capturing samples over longer time constraints. The second non-linear filter network <NUM> can have to have a higher sampling rate to correct for higher frequency noise.

A power amplifier can exhibit different performance characteristics shortly after the time of being powered up (for instance, just after being enabled) relative to steady-state operation after the power amplifier has settled. Such power amplifier effects can arise from a variety of factors, such as power amplifier self-heating. For example, the initial operation of a power amplifier when cool can vary relative to operation of the power amplifier after it has reached a steady state operating temperature.

In certain applications, a power amplifier is turned on for a long period of time, and then turned off for a long period of time. For example, for a base station or mobile device using time-division duplexing (TDD), the power amplifier can be turned on for a transmit time slot, and turned off for a receive time slot.

The DPD systems herein can be implemented to compensate for the transient changes to a power amplifier's performance after turn-on versus steady-state. For example, any of the embodiments herein can be used to store multiple sets of coefficients for DPD (including coefficients used for charge trapping DPD). Additionally, the DPD system can be configured to use one set of coefficients shortly after turn on of a power amplifier (for instance, for a time period T after power amplifier turn-on), and a second set of coefficients in the steady state (for example, after period T).

By using two (or more) sets of coefficients for DPD, a power amplifier can be more effectively linearized including both for initial or start-up operation and for steady-state operation.

Any of the embodiments herein can be implemented with multiple sets of DPD coefficients that are selectively used (and trained) depending on how long a power amplifier has been turned on/enabled.

Aspects of this disclosure can be implemented in various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, cellular communications infrastructure such as a base station, etc. Examples of the electronic devices can include, but are not limited to, a mobile phone such as a smart phone, a wearable computing device such as a smart watch or an ear piece, a telephone, a television, a computer monitor, a computer, a modem, a hand-held computer, a laptop computer, a tablet computer, a personal digital assistant (PDA), a microwave, a refrigerator, a vehicular electronics system such as an automotive electronics system, a stereo system, a DVD player, a CD player, a digital music player such as an MP3 player, a radio, a camcorder, a camera such as a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, peripheral device, a clock, etc. Further, the electronic devices can include unfinished products.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," "include," "including" and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to. " The word "coupled", as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word "connected", as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number, respectively. The word "or" in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

Moreover, conditional language used herein, such as, among others, "can," "could," "might," "may," "e.g.," "for example," "such as" and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or whether these features, elements and/or states are included or are to be performed in any particular embodiment.

Claim 1:
A radio frequency, RF, power semiconductor device (<NUM>, <NUM>, <NUM>), wherein the device comprises:
a first non-linear filter network (<NUM>) configured to pre-distort an input signal for a compound semiconductor power amplifier (<NUM>) to compensate for narrowband distortion of the compound semiconductor power amplifier (<NUM>) caused by charge trapping effects as the compound semiconductor power amplifier is charged from low to high power,
wherein the first non-linear filter network comprises a corrective element (254A) configured to receive an envelope of the input signal and correct for a non-linear portion of the power amplifier, and a first plurality of infinite impulse response, IIR, filters (262A, 264A, 266A) arranged in series,
wherein the output of the corrective element (254A) is provided to the first plurality of IIR filters (262A, 264A, 266A),
wherein the first plurality of IIR filters are arranged to function as a Laguerre filter, and
wherein the first non-linear filter network is configured to:
generate a low frequency gain term based on outputs from the first plurality of IIR filters, wherein the low frequency gain term represents a narrowband frequency correction gain, and
pre-distort the input signal using the low frequency gain term.