Patent Description:
Preferred embodiments of the invention are stipulated in the dependent claims.

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. However, while the drawings are to aid in explanation and understanding, they are only an aid, and should not be taken to limit the disclosure to the specific embodiments depicted therein.

Various wireless cellular communication systems have been implemented or are being proposed, including 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS), 3GPP Long-Term Evolution (LTE) systems, 3GPP LTE-Advanced (LTE-A) systems, and 5th Generation (<NUM>) wireless systems / <NUM> mobile networks systems / <NUM> New Radio (NR) systems.

Various wireless cellular communication systems may incorporate Polar codes, which may increase complexity in encoding and decoding due to inherent code construction issues and inter-dependency. For example, encoding complexity and/or decoding complexity may vary significantly with small changes in block sizes and/or code rates.

Discussed herein are various mechanisms and methods to support filler bit attachment in Polar encoding schemes (e.g., for Polar encoders and/or Polar decoders). An advantage of the discussed mechanisms and methods is that they may significantly reduce a complexity of code design and/or storage and/or decoder implementations. By applying zero-padding, a coarse set of block sizes to be supported natively by an underlying Polar encoder and/or Polar decoder (e.g., combinations to be supported by the Polar encoder and/or Polar decoder), design complexity may be reduced while still accommodating flexibility in input sizes.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Throughout the specification, and in the claims, the term "connected" means a direct electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on.

The terms "substantially," "close," "approximately," "near," and "about" generally refer to being within +/- <NUM>% of a target value. Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

For purposes of the embodiments, the transistors in various circuits, modules, and logic blocks are Tunneling FETs (TFETs). Some transistors of various embodiments may comprise metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. The transistors may also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Square Wire, or Rectangular Ribbon Transistors or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors-BJT PNP/NPN, BiCMOS, CMOS, etc., may be used for some transistors without departing from the scope of the disclosure.

For the purposes of the present disclosure, the phrases "A and/or B" and "A or B" mean (A), (B), or (A and B).

In addition, for purposes of the present disclosure, the term "eNB" may refer to a legacy LTE capable Evolved Node-B (eNB), a next-generation or <NUM> capable eNB, an Access Point (AP), and/or another base station for a wireless communication system. The term "gNB" may refer to a <NUM>-capable or NR-capable eNB. For purposes of the present disclosure, the term "UE" may refer to a legacy LTE capable User Equipment (UE), a Station (STA), and/or another mobile equipment for a wireless communication system. The term "UE" may also refer to a next-generation or <NUM> capable UE.

Various embodiments of eNBs and/or UEs discussed below may process one or more transmissions of various types. Some processing of a transmission may comprise demodulating, decoding, detecting, parsing, and/or otherwise handling a transmission that has been received. In some embodiments, an eNB or UE processing a transmission may determine or recognize the transmission's type and/or a condition associated with the transmission. For some embodiments, an eNB or UE processing a transmission may act in accordance with the transmission's type, and/or may act conditionally based upon the transmission's type. An eNB or UE processing a transmission may also recognize one or more values or fields of data carried by the transmission. Processing a transmission may comprise moving the transmission through one or more layers of a protocol stack (which may be implemented in, e.g., hardware and/or software-configured elements), such as by moving a transmission that has been received by an eNB or a UE through one or more layers of a protocol stack.

Various embodiments of eNBs and/or UEs discussed below may also generate one or more transmissions of various types. Some generating of a transmission may comprise modulating, encoding, formatting, assembling, and/or otherwise handling a transmission that is to be transmitted. In some embodiments, an eNB or UE generating a transmission may establish the transmission's type and/or a condition associated with the transmission. For some embodiments, an eNB or UE generating a transmission may act in accordance with the transmission's type, and/or may act conditionally based upon the transmission's type. An eNB or UE generating a transmission may also determine one or more values or fields of data carried by the transmission. Generating a transmission may comprise moving the transmission through one or more layers of a protocol stack (which may be implemented in, e.g., hardware and/or software-configured elements), such as by moving a transmission to be sent by an eNB or a UE through one or more layers of a protocol stack.

In various embodiments, resources may span various Resource Blocks (RBs), Physical Resource Blocks (PRBs), and/or time periods (e.g., frames, subframes, and/or slots) of a wireless communication system. In some contexts, allocated resources (e.g., channels, Orthogonal Frequency-Division Multiplexing (OFDM) symbols, subcarrier frequencies, resource elements (REs), and/or portions thereof) may be formatted for (and prior to) transmission over a wireless communication link. In other contexts, allocated resources (e.g., channels, OFDM symbols, subcarrier frequencies, REs, and/or portions thereof) may be detected from (and subsequent to) reception over a wireless communication link.

<FIG> illustrates scenarios of Polar codes, in accordance with some embodiments of the disclosure. A first scenario <NUM> may support a parity-check Polar code (PC) and/or PC scheme. An overhead of additional PC-frozen bits may be distributed among frozen bits as well as a payload of information bits and CRC <NUM> bits. A second scenario <NUM> may support a parity-check PC and/or PC scheme. An overhead of additional CRC may accompany frozen bits as well as a payload of information bits and CRC <NUM>+n bits.

Polar codes may support relatively flexible information and code block sizes. For example, a one-bit granularity on an input may be possible with Polar codes. However, with such fine granularity, there may be implementations costs on the encoder side and/or on the decoder side. These costs may be amplified for some varieties of Polar codes, such as parity-check Polar codes, or distributed/hash-aided Polar codes. The cost may relate to identifying and storing locations of various types of bits and handling of these bits in the encoder and/or decoder.

In Polar codes, input locations may be marked as data locations or frozen locations. This may simplify implementation for both encoding operations and decoding operations. A single reliability bit sequence may be used to identify which bits correspond to data and which bits correspond to frozen bits. In various embodiments, the data bits may also contain a CRC that may be used to assist list decoding in selecting suitable candidates as estimated data bits. Typically, an associated CRC check may be considered a parallel operation that may be performed separately from a core list Polar decoding algorithm.

In contrast, in some new methods such as parity-check Polar coding, there may be an addition input location type, such as parity-check bits, in addition to data bits and frozen bits (e.g., frozen locations). These parity-check bits may be interspersed, and may also form an additional linkage between a set of data bits and a set of parity-check bits. This may lead to additional complexity as a number of parity-check bits and actual location for those bits within an input may vary as a function of a data block size and a code rate.

In the example provided in Table <NUM> below, the first column (Kp) indicates a number of data bits, and the remaining columns indicate various coding rates. In turn, the rows indicate, for various numbers of data bits, the number of parity-check bits that may support a particular code rate. For example, for a number of data bits Kp = <NUM>, to support a code rate of <NUM>/<NUM>, a first algorithm may be disposed to provide <NUM> parity-check bits, while a second algorithm may be disposed to provide <NUM> parity-check bits.

A Polar code length (e.g., a mother code length) of N may be a nearest power of two that is larger than Kp divided by the code rate. The Polar code length N may then be used to determine a number of frozen bits, which may be equal to the code length, minus the number of data bits, minus the number of parity-check bits (e.g., the bits remaining after the data bits and parity-check bits are subtracted from the polar code length).

Continuing the example above, for Kp = <NUM> data bit locations and a code rate of <NUM>/<NUM>, Kp divided by <NUM>/<NUM> is <NUM>, so the Polar code length N = <NUM> (the nearest power of two that is larger than <NUM>). For a Polar code length of <NUM>, <NUM> data bit locations, and either <NUM> parity-check bit locations (for the first algorithm) or <NUM> parity-check bit locations (for the second algorithm), there may be either <NUM> - <NUM> - <NUM> = <NUM> frozen bits (for the first algorithm), or <NUM> - <NUM> - <NUM> = <NUM> frozen bits (for the second algorithm).

In general, a number of PC bits in a PC Polar code may be determined in accordance with the following equation: <MAT> Where: K may be a number of information bits; N may be a mother code size of the Polar code used for encoding K information bits (e.g., data bits) to generate M bits for transmission; and M may be a number of bits that are transmitted. In some embodiments, Fp may be a threshold used in determining a number of parity-check bits, but the actual number of parity-check bits may be determined based on a procedure having two stages. In a first stage, a small number of relatively more-reliable bit positions may be marked for parity-check bits (and/or PC-frozen bits), and an additional, larger number of relatively less-reliable bit positions may be marked for parity-check bits (and/or PC-frozen bits).

In various embodiments, for block sizes (e.g., numbers of data bits) between <NUM> and <NUM> bits, to support coded sequences of lengths of {<NUM>,<NUM>,<NUM>,<NUM>} (which may be obtained, for example, by Polar coding and rate-matching), numbers of combinations of rates and/or lengths may be approximately <NUM> x <NUM> = <NUM> combinations. Moreover, a design may be disposed to providing storage for each combination for locations of data bits, parity-check bits, and/or frozen bits. The arrangement of these bits (data, parity-check, and/or frozen) may impact aspects of decoding implementations related to scheduling and latency. In addition, latency may vary for numbers of data bits that are close, yet different. For example, for Kp = <NUM> and for <NUM> coded bits, latency may be different than for K = <NUM> and <NUM> coded bits, even though they are very close to each other in block length (e.g., number of data bits), and in addition the locations of data bits, PC-bits, and/or frozen bits might also be different. This can be true, for example, in using a simplified successive cancellation list decoder, or a multi-bit decoder.

In general, for each set of block size K (e.g., number of data bits), Polar code length / mother code length N, and number of bits transmitted M, a number of PC-bits may be different, and the locations of the PC-bits may also be different. Accommodating such differences may lead to increased complexity on the encoder side and/or the decoder side. For example, with a block size K between <NUM> bits and <NUM> bits, and a number of bits transmitted M being {<NUM>,<NUM>,<NUM>, and/or <NUM>}, there may be approximately <NUM> x <NUM> = <NUM> combinations to be supported; and for each combination, a design may be disposed to provide storage to identify the number of PC-bits and the locations of the PC-bits on a Polar code input (e.g., on an input of a Polar encoder). Moreover, a design may be disposed to providing an additional hardware decoder for many cases, which may complicate the overall design.

<FIG> illustrates an exemplary scenario of locations of data bits, parity-check bits, and frozen bits, in accordance with some embodiments of the disclosure. A scenario <NUM> may relate to an embodiment having a Polar code size N = <NUM> bits, with parity-check bits occurring in different locations depending upon the data block size K.

Bit indices <NUM> through <NUM> of the <NUM> bits are depicted for various block sizes K (e.g., from K = <NUM> to K = <NUM>). For each block size K, each bit index may correspond to as being for data bits (labeled "I"), parity-check bits (labeled "PC"), and frozen bits (labeled "F"). Parity-check bits may occur in different locations and may interfere with data locations.

According to the invention, a coarse set of block sizes for inputting into a Polar code is supported by applying a padding step prior to encoding with a Polar code (e.g., a zero-padding step). This may advantageously enable the Polar code patterns to be defined merely for a set of block sizes that a multiples of a predetermined number. For example, in some embodiments, Polar code patterns may be defined merely for data blocks having sizes that are multiples of four (e.g., comprising <NUM>, <NUM>, <NUM>, <NUM>, and so on). Data blocks having other block sizes may then be supported by padding the data block to obtain a data block having a size that is a multiple of four. The data block may be padded by adding numbers (such as "<NUM>"s or "<NUM>"s) to a beginning of a data block an end of a data block, or before or after various predetermined positions of the data block.

Scenario <NUM> may correspond with a padding scheme (e.g., a zero-padding scheme), in which data blocks are padded with predetermined numbers (e.g., "<NUM>"). In comparison with scenario <NUM>, for data block sizes K of <NUM> bits, <NUM> bits, and <NUM> bits, the data bits ("I") may be padded with filler bits having a predetermined value known to both the transmitting side and the receiving side (e.g., with "<NUM>") in order to form a padded data block having a size of <NUM> bits. A data block size of K = <NUM> bits may use <NUM> filler bits, a data block size of K = <NUM> may use <NUM> filler bits, and a data block size of K = <NUM> may use one filler bit. In some embodiments, filler bits may be treated similar to frozen bits. Actual positions of filler bits within sets of data bits may be determined based on pre-determined rules (e.g., they may be placed before data bits, after data bits, or at predetermined positions or locations within a set of data bits). For some embodiments, for example, filler bits may be zero bits, and/or may be appended to an end of a set of data block bits.

An encoder and a decoder may accordingly be able to support a fine range of input block sizes (e.g., at a one-bit granularity) and/or rates merely by supporting a coarse range of input block sizes and/or rates set of sizes and/or rates. In some embodiments, the pre-determined filler bits may be treated as frozen bits in the decoding procedure, or may be handled via other means. Such a technique may advantageously improve encoder and/or decoder implementations, while reducing the risks to performance and retaining flexibility.

<FIG> illustrates an exemplary circuitry comprising a Polar encoder, in accordance with some embodiments of the disclosure. A circuitry <NUM> may accommodate an input data block of length K (e.g., a data block of length Kp). The data block of length K may be provided to a filler bit determination unit, along with a set of block sizes supported by the Polar encoder for circuitry <NUM> (e.g., a block size Ksupported may be a multiple of four, such as {<NUM>, <NUM>, <NUM>, <NUM>, and so on, through <NUM>}). The filler bit determination unit may then determine a number of filler bits to be used based on the data block length and the block sizes supported for the Polar encoder. The filler bit determination unit may output a padded data block (e.g., a filler-bit-attached data block) of length K'. Although filler bits are depicted as being attached, in various embodiments, they may be placed in any order, including being interspersed among the K data bits. (The number of filler bits may be indicated as Fb; for example, for K = <NUM>, Fb = <NUM> and K' = <NUM>.

A Polar code parameter set determination unit may determine a Polar code sequence to use, and locations of the data bits, parity-check bits, and frozen bits may be determined for the padded data block of length K'. The Polar code parameter set determination unit may take as input a number of coded bits to determine, and any other inputs that may be used to determine a Polar code parameter set.

The padded data block of length K' and the Polar code parameter set (e.g., as determined by the Polar encoder parameter set determination unit) may be provided to a Polar encoder, which may output a Polar codeword having a number N of bits. A rate-matching unit may then take the Polar codeword having N bits as an input and may form a transmitted codeword having a desired number of bits M for transmission.

According to the invention: the data block has a first number of bits N1 (e.g., Kp bits as discussed herein, and/or K as depicted in <FIG>); the filler bits has a second number of bits N2 (e.g., Fb bits as discussed herein); the padded data block has a third number of bits N3 (e.g., "I" as depicted in <FIG>, and/or K' as depicted in <FIG>); the Polar codeword has a fourth number of bits N4 (e.g., N as discussed herein and/or depicted in <FIG>); the parity-check bits is a fifth number of bits N5 (e.g., "PC" as depicted in <FIG>); and the frozen bits is a sixth number of bits N6 (e.g., "F" as depicted in <FIG>). Various embodiments may follow the following relationships: <MAT> <MAT>.

In some embodiments, a UE may implement a circuitry <NUM> for, e.g., Uplink (UL) transmissions, such as UCI. In some embodiments, a gNB may implement a circuitry <NUM> for, e.g., Downlink (DL) transmissions, such as DCI.

<FIG> illustrates an exemplary circuitry comprising a Polar decoder, in accordance with some embodiments of the disclosure. A circuitry <NUM> may comprise a Polar decoder parameter set determination unit, which may determine a Polar code sequence being used, and locations of the data bits, parity-check bits, and frozen bits for a padded data block of length K'. In turn, the padded data block length of K' may be established by virtue of comparing an expected data block length K for the incoming data block against a set of block sizes supported by the Polar decoder for circuitry <NUM> (e.g., a block size K supported may be a multiple of four, such as {<NUM>, <NUM>, <NUM>, <NUM>, and so on, through <NUM>}).

A de-rate-matching unit may have accommodate a received codeword of length M. A de-rate-matching unit may take the received codeword of having M bits as an input and may form a Polar codeword having N bits as an output. A Polar decoder may then take the Polar codeword having N bits as an input, and based on a Polar decoder parameter set (e.g., as determined by the Polar decoder parameter set determination unit, which may include the number K of data bits and filler bits, and/or their locations), the Polar decoder may obtain an estimate of the original data. The estimate of the original data may comprise the number K of data bits and/or their locations, the number Fb of filler bits and/or their locations, or both (e.g., the number K' of data bits and filler bits and/or their locations). Circuitry <NUM> may accordingly determine the location of data bits, filler bits, parity check bits, and frozen bits in a received codeword.

For various embodiments: the Polar codeword may have a first number of bits M1 (e.g., N as discussed herein and/or depicted in <FIG>); the padded data block may have a second number of bits M2 (e.g., "I" as depicted in <FIG>, and/or K' as depicted in <FIG>); the filler bits may be a third number of bits M3 (e.g., Fb bits as discussed herein); the data block may have a fourth number of bits M4 (e.g., Kp bits as discussed herein, and/or K as depicted in <FIG>); the parity-check bits may be a fifth number of bits M5 (e.g., "PC" as depicted in ); and the frozen bits may be a sixth number of bits M6 (e.g., "F" as depicted in <FIG>). Various embodiments may follow the following relationships: <MAT> <MAT>.

In some embodiments, a gNB may implement a circuitry <NUM> for, e.g., DL transmissions, such as DCI. In some embodiments, a UE may implement a circuitry <NUM> for, e.g., UL transmissions, such as UCI.

<FIG> illustrates an eNB and a UE, in accordance with some embodiments of the disclosure. <FIG> includes block diagrams of an eNB <NUM> and a UE <NUM> which are operable to co-exist with each other and other elements of an LTE network. High-level, simplified architectures of eNB <NUM> and UE <NUM> are described so as not to obscure the embodiments. It should be noted that in some embodiments, eNB <NUM> may be a stationary non-mobile device.

eNB <NUM> is coupled to one or more antennas <NUM>, and UE <NUM> is similarly coupled to one or more antennas <NUM>. However, in some embodiments, eNB <NUM> may incorporate or comprise antennas <NUM>, and UE <NUM> in various embodiments may incorporate or comprise antennas <NUM>.

In some embodiments, antennas <NUM> and/or antennas <NUM> may comprise one or more directional or omni-directional antennas, including monopole antennas, dipole antennas, loop antennas, patch antennas, microstrip antennas, coplanar wave antennas, or other types of antennas suitable for transmission of RF signals. In some MIMO (multiple-input and multiple output) embodiments, antennas <NUM> are separated to take advantage of spatial diversity.

eNB <NUM> and UE <NUM> are operable to communicate with each other on a network, such as a wireless network. eNB <NUM> and UE <NUM> may be in communication with each other over a wireless communication channel <NUM>, which has both a downlink path from eNB <NUM> to UE <NUM> and an uplink path from UE <NUM> to eNB <NUM>.

As illustrated in <FIG>, in some embodiments, eNB <NUM> may include a physical layer circuitry <NUM>, a MAC (media access control) circuitry <NUM>, a processor <NUM>, a memory <NUM>, and a hardware processing circuitry <NUM>. A person skilled in the art will appreciate that other components not shown may be used in addition to the components shown to form a complete eNB.

In some embodiments, physical layer circuitry <NUM> includes a transceiver <NUM> for providing signals to and from UE <NUM>. Transceiver <NUM> provides signals to and from UEs or other devices using one or more antennas <NUM>. In some embodiments, MAC circuitry <NUM> controls access to the wireless medium. Memory <NUM> may be, or may include, a storage media/medium such as a magnetic storage media (e.g., magnetic tapes or magnetic disks), an optical storage media (e.g., optical discs), an electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash-memory-based storage media), or any tangible storage media or non-transitory storage media. Hardware processing circuitry <NUM> may comprise logic devices or circuitry to perform various operations. In some embodiments, processor <NUM> and memory <NUM> are arranged to perform the operations of hardware processing circuitry <NUM>, such as operations described herein with reference to logic devices and circuitry within eNB <NUM> and/or hardware processing circuitry <NUM>.

Accordingly, in some embodiments, eNB <NUM> may be a device comprising an application processor, a memory, one or more antenna ports, and an interface for allowing the application processor to communicate with another device.

As is also illustrated in <FIG>, in some embodiments, UE <NUM> may include a physical layer circuitry <NUM>, a MAC circuitry <NUM>, a processor <NUM>, a memory <NUM>, a hardware processing circuitry <NUM>, a wireless interface <NUM>, and a display <NUM>. A person skilled in the art would appreciate that other components not shown may be used in addition to the components shown to form a complete UE.

In some embodiments, physical layer circuitry <NUM> includes a transceiver <NUM> for providing signals to and from eNB <NUM> (as well as other eNBs). Transceiver <NUM> provides signals to and from eNBs or other devices using one or more antennas <NUM>. In some embodiments, MAC circuitry <NUM> controls access to the wireless medium. Memory <NUM> may be, or may include, a storage media/medium such as a magnetic storage media (e.g., magnetic tapes or magnetic disks), an optical storage media (e.g., optical discs), an electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash-memory -based storage media), or any tangible storage media or non-transitory storage media. Wireless interface <NUM> may be arranged to allow the processor to communicate with another device. Display <NUM> may provide a visual and/or tactile display for a user to interact with UE <NUM>, such as a touch-screen display. Hardware processing circuitry <NUM> may comprise logic devices or circuitry to perform various operations. In some embodiments, processor <NUM> and memory <NUM> may be arranged to perform the operations of hardware processing circuitry <NUM>, such as operations described herein with reference to logic devices and circuitry within UE <NUM> and/or hardware processing circuitry <NUM>.

Accordingly, in some embodiments, UE <NUM> may be a device comprising an application processor, a memory, one or more antennas, a wireless interface for allowing the application processor to communicate with another device, and a touch-screen display.

Elements of <FIG>, and elements of other figures having the same names or reference numbers, can operate or function in the manner described herein with respect to any such figures (although the operation and function of such elements is not limited to such descriptions). For example, <FIG> and <FIG> also depict embodiments of eNBs, hardware processing circuitry of eNBs, UEs, and/or hardware processing circuitry of UEs, and the embodiments described with respect to <FIG> and Figs. <FIG> and <FIG> can operate or function in the manner described herein with respect to any of the figures.

In addition, although eNB <NUM> and UE <NUM> are each described as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements and/or other hardware elements. In some embodiments of this disclosure, the functional elements can refer to one or more processes operating on one or more processing elements. Examples of software and/or hardware configured elements include Digital Signal Processors (DSPs), one or more microprocessors, DSPs, Field-Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Radio-Frequency Integrated Circuits (RFICs), and so on.

<FIG> illustrates hardware processing circuitries for a UE for supporting filler bit attachment in Polar encoding schemes, in accordance with some embodiments of the disclosure. With reference to <FIG>, a UE may include various hardware processing circuitries discussed herein (such as hardware processing circuitry <NUM> of <FIG>), which may in turn comprise logic devices and/or circuitry operable to perform various operations. For example, in <FIG>, UE <NUM> (or various elements or components therein, such as hardware processing circuitry <NUM>, or combinations of elements or components therein) may include part of, or all of, these hardware processing circuitries.

In some embodiments, one or more devices or circuitries within these hardware processing circuitries may be implemented by combinations of software-configured elements and/or other hardware elements. For example, processor <NUM> (and/or one or more other processors which UE <NUM> may comprise), memory <NUM>, and/or other elements or components of UE <NUM> (which may include hardware processing circuitry <NUM>) may be arranged to perform the operations of these hardware processing circuitries, such as operations described herein with reference to devices and circuitry within these hardware processing circuitries. In some embodiments, processor <NUM> (and/or one or more other processors which UE <NUM> may comprise) may be a baseband processor.

Returning to <FIG>, an apparatus of UE <NUM> (or another UE or mobile handset), which may be operable to communicate with one or more eNBs on a wireless network, may comprise hardware processing circuitry <NUM>. In some embodiments, hardware processing circuitry <NUM> may comprise one or more antenna ports <NUM> operable to provide various transmissions over a wireless communication channel (such as wireless communication channel <NUM>). Antenna ports <NUM> may be coupled to one or more antennas <NUM> (which may be antennas <NUM>). In some embodiments, hardware processing circuitry <NUM> may incorporate antennas <NUM>, while in other embodiments, hardware processing circuitry <NUM> may merely be coupled to antennas <NUM>.

Antenna ports <NUM> and antennas <NUM> may be operable to provide signals from a UE to a wireless communications channel and/or an eNB, and may be operable to provide signals from an eNB and/or a wireless communications channel to a UE. For example, antenna ports <NUM> and antennas <NUM> may be operable to provide transmissions from UE <NUM> to wireless communication channel <NUM> (and from there to eNB <NUM>, or to another eNB). Similarly, antennas <NUM> and antenna ports <NUM> may be operable to provide transmissions from a wireless communication channel <NUM> (and beyond that, from eNB <NUM>, or another eNB) to UE <NUM>.

Hardware processing circuitry <NUM> may comprise various circuitries operable in accordance with the various embodiments discussed herein. With reference to <FIG>, hardware processing circuitry <NUM> may comprise a first circuitry <NUM>, a second circuitry <NUM>, a third circuitry <NUM>, and/or a fourth circuitry <NUM>.

First circuitry <NUM> is operable to identify a data block having a number N1 of bits. Second circuitry <NUM> is operable to determine a number N2 of filler bits based on a set of parameters and the N1 of bits of the data block. First circuitry <NUM> is operable to provide information regarding the number N1 of bits of the data block (e.g., the number N1 itself) to second circuitry <NUM> via an interface <NUM>. Third circuitry <NUM> is operable to pad the data block with the N2 filler bits to form a padded data block having a number N3 of bits. Second circuitry <NUM> is operable to provide information regarding the number N2 of filler bits (e.g., the number N2 itself) to third circuitry <NUM> via an interface <NUM>. Fourth circuitry <NUM> is operable to encode the N3 bits of the padded data block to form a Polar codeword having a number N4 of bits. Third circuitry <NUM> is operable to information regarding the padded data block having the number N3 of bits (e.g., the padded data block itself) to fourth circuitry <NUM> via an interface <NUM>. Hardware processing circuitry <NUM> comprises an interface for sending a transmission based on the Polar codeword to a transmission circuitry.

In some embodiments, the data block may be a UCI block. second circuitry <NUM> is operable to identify, based on at least the number N3, a number N5 of parity-check bits and locations at an input of a Polar encoder for the N5 parity-check bits. Second circuitry <NUM> is also operable to identify N3 locations at an input of the Polar encoder for inserting the N3 bits of the padded data block. Fourth circuitry <NUM> is operable to encode the N3 bits of the padded data block, the N5 parity-check bits, and a number N6 of frozen bits to form the N4 bits of the Polar codeword. Second circuitry <NUM> is operable to provide the number N3 of parity-check bits and locations at the input of the Polar encoder for the N5 parity-check bits to third circuitry <NUM> (and through third circuitry <NUM>, to fourth circuitry <NUM>) via interface <NUM>.

In some embodiments, second circuitry <NUM> may be operable to identify N3 locations at an input of a Polar encoder for placing the N3 bits of the padded data block, based on a sequence. Second circuitry may also be operable to identify a number N6 of locations at the input of the Polar encoder for placing N6 frozen bits, based on the sequence. Fourth circuitry <NUM> may be operable to encode at least the N3 bits of the padded data block and the N6 frozen bits to form the N4 bits of the Polar codeword. Second circuitry <NUM> may be operable to provide the number N6 of locations at the input of the Polar encoder for placing N6 frozen bits to third circuitry <NUM> (and through third circuitry <NUM>, to fourth circuitry <NUM>) via interface <NUM>.

The set of parameters consists of a range of supported block sizes which are multiples of at least one of: <NUM> bits, or <NUM> bits, or <NUM> bits. For some embodiments, the N2 filler bits may be concatenated to an initial bit of the data block. In some embodiments, the N2 filler bits may be concatenated to a final bit of the data block. For some embodiments, the N2 filler bits may be dispersed within the data block.

In some embodiments, first circuitry <NUM>, second circuitry <NUM>, third circuitry <NUM>, and/or fourth circuitry <NUM> may be implemented as separate circuitries. In other embodiments, first circuitry <NUM>, second circuitry <NUM>, third circuitry <NUM>, and/or fourth circuitry <NUM> may be combined and implemented together in a circuitry without altering the essence of the embodiments.

<FIG> illustrates hardware processing circuitries for an eNB for supporting filler bit attachment in Polar encoding schemes, in accordance with some embodiments of the disclosure. With reference to <FIG>, an eNB may include various hardware processing circuitries discussed herein (such as hardware processing circuitry <NUM> of <FIG>), which may in turn comprise logic devices and/or circuitry operable to perform various operations. For example, in <FIG>, eNB <NUM> (or various elements or components therein, such as hardware processing circuitry <NUM>, or combinations of elements or components therein) may include part of, or all of, these hardware processing circuitries.

In some embodiments, one or more devices or circuitries within these hardware processing circuitries may be implemented by combinations of software-configured elements and/or other hardware elements. For example, processor <NUM> (and/or one or more other processors which eNB <NUM> may comprise), memory <NUM>, and/or other elements or components of eNB <NUM> (which may include hardware processing circuitry <NUM>) may be arranged to perform the operations of these hardware processing circuitries, such as operations described herein with reference to devices and circuitry within these hardware processing circuitries. In some embodiments, processor <NUM> (and/or one or more other processors which eNB <NUM> may comprise) may be a baseband processor.

Returning to <FIG>, an apparatus of eNB <NUM> (or another eNB or base station), which may be operable to communicate with one or more UEs on a wireless network, may comprise hardware processing circuitry <NUM>. In some embodiments, hardware processing circuitry <NUM> may comprise one or more antenna ports <NUM> operable to provide various transmissions over a wireless communication channel (such as wireless communication channel <NUM>). Antenna ports <NUM> may be coupled to one or more antennas <NUM> (which may be antennas <NUM>). In some embodiments, hardware processing circuitry <NUM> may incorporate antennas <NUM>, while in other embodiments, hardware processing circuitry <NUM> may merely be coupled to antennas <NUM>.

Antenna ports <NUM> and antennas <NUM> may be operable to provide signals from an eNB to a wireless communications channel and/or a UE, and may be operable to provide signals from a UE and/or a wireless communications channel to an eNB. For example, antenna ports <NUM> and antennas <NUM> may be operable to provide transmissions from eNB <NUM> to wireless communication channel <NUM> (and from there to UE <NUM>, or to another UE). Similarly, antennas <NUM> and antenna ports <NUM> may be operable to provide transmissions from a wireless communication channel <NUM> (and beyond that, from UE <NUM>, or another UE) to eNB <NUM>.

Hardware processing circuitry <NUM> may comprise various circuitries operable in accordance with the various embodiments discussed herein. With reference to <FIG>, hardware processing circuitry <NUM> may comprise a first circuitry <NUM>, a second circuitry <NUM>, and/or a third circuitry <NUM>.

First circuitry <NUM> is operable to decode a Polar codeword having a number M1 of bits to extract a padded data block having a number M2 of bits. Second circuitry <NUM> is operable to determine a number M3 of filler bits based on a number M4 of bits of a data block within the padded data block and a set of parameters. First circuitry <NUM> is operable to provide information regarding the padded data block (e.g., the padded data block itself) to second circuitry <NUM> via an interface <NUM>, and to third circuitry <NUM> via an interface <NUM>. Third circuitry <NUM> is operable to de-pad the M2 bits of the padded data block to form a data block having the number M4 of bits. Second circuitry <NUM> is operable to provide information regarding the number M3 of filler bits (e.g., locations of the M3 filler bits) to third circuitry <NUM> via an interface <NUM>. Hardware processing circuitry <NUM> comprises an interface for receiving a transmission based on the Polar codeword from a receiving circuitry.

In some embodiments, the data block may be a UCI block.

Second circuitry <NUM> is operable to identify, based on at least the number M2, a number M5 of parity-check bits and locations at a Polar decoder (e.g., at an output of the Polar decoder) for the M5 parity-check bits. Second circuitry <NUM> is also operable to identify M2 locations at the Polar decoder (e.g., at an output of the Polar decoder) for removing the M2 bits of the padded data block. First circuitry <NUM> is operable to decode, from the M1 bits of the Polar codeword, at least one of: the M2 bits of the padded data block; the M5 parity-check bits; and a number M6 of frozen bits. Second circuitry <NUM> is operable to provide information regarding the number M5 of parity-check bits and locations at the Polar decoder for the M5 parity-check bits to first circuitry <NUM> via the interface <NUM>.

In some embodiments, second circuitry <NUM> may be operable to identify M2 locations at a Polar decoder (e.g., at an output of the Polar decoder) for extracting the M2 bits of the padded data block, based on a sequence. Second circuitry <NUM> may also be operable to identify a number M6 of locations at the Polar decoder (e.g., at an output of the Polar decoder) for extracting M6 frozen bits, based on the sequence. First circuitry <NUM> may be operable to decode, from the M1 bits of the frozen codeword, at least one of: the M2 bits of the padded data block; and the M6 frozen bits. Second circuitry <NUM> may be operable to provide information regarding the number M6 of frozen bits at the Polar decoder to first circuitry <NUM> via the interface <NUM>.

The set of parameters consists of a range of supported block sizes which are multiples of at least one of: <NUM> bits, or <NUM> bits, or <NUM> bits. For some embodiments, the M3 filler bits may be concatenated to an initial bit of the data block. In some embodiments, the M3 filler bits may be concatenated to a final bit of the data block. For some embodiments, the M3 filler bits may be dispersed within the data block.

In some embodiments, first circuitry <NUM>, second circuitry <NUM>, and/or third circuitry <NUM> may be implemented as separate circuitries. In other embodiments, first circuitry <NUM>, second circuitry <NUM>, and/or third circuitry <NUM> may be combined and implemented together in a circuitry without altering the essence of the embodiments.

<FIG> illustrates methods for a UE for supporting filler bit attachment in Polar encoding schemes, in accordance with some embodiments of the disclosure. With reference to <FIG>, methods that may relate to UE <NUM> and hardware processing circuitry <NUM> are discussed herein. Although the actions in method <NUM> of <FIG> are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions may be performed in parallel. Some of the actions and/or operations listed in <FIG> are optional in accordance with certain embodiments. The numbering of the actions presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various actions must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

Moreover, in some embodiments, machine readable storage media may have executable instructions that, when executed, cause UE <NUM> and/or hardware processing circuitry <NUM> to perform an operation comprising the methods of <FIG>. Such machine readable storage media may include any of a variety of storage media, like magnetic storage media (e.g., magnetic tapes or magnetic disks), optical storage media (e.g., optical discs), electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash-memory-based storage media), or any other tangible storage media or non-transitory storage media.

According to the invention, an apparatus comprises means for performing various actions and/or operations of the methods of <FIG>.

Returning to <FIG>, various methods may be in accordance with the various embodiments discussed herein. A method <NUM> according to the invention comprises an identifying <NUM>, a determining <NUM>, a padding <NUM>, and an encoding <NUM>. According to the invention, method <NUM> also comprises an identifying <NUM>, an identifying <NUM>, and an encoding <NUM>, and may further comprise an identifying <NUM>, an identifying <NUM>, and/or an encoding <NUM>.

In identifying <NUM>, a data block having a number N1 of bits is identified. In determining <NUM>, a number N2 of filler bits is determined based on a set of parameters and the N1 of bits of the data block. In padding <NUM>, the data block is padded with the N2 filler bits to form a padded data block having a number N3 of bits. In encoding <NUM>, the N3 bits of the padded data block are encoded to form a Polar codeword having a number N4 of bits.

Further according to the invention, in identifying <NUM>, based on at least the number N3, a number N5 of parity-check bits and locations at an input of a Polar encoder for the N5 parity-check bits is identified. In identifying <NUM>, N3 locations at an input of the Polar encoder for inserting the N3 bits of the padded data block are identified. In encoding <NUM>, the N3 bits of the padded data block, the N5 parity-check bits, and a number N6 of frozen bits are encoded to form the N4 bits of the Polar codeword.

In some embodiments, in identifying <NUM>, N3 locations at an input of a Polar encoder for placing the N3 bits of the padded data block may be identified, based on a sequence. In identifying <NUM>, a number N6 of locations at the input of the Polar encoder for placing N6 frozen bits may be identified, based on the sequence. In encoding <NUM>, at least the N3 bits of the padded data block and the N6 frozen bits may be encoded to form the N4 bits of the Polar codeword.

According to the invention, the set of parameters consists of a set of a range of supported block sizes which are multiples of at least one of: <NUM> bits, or <NUM> bits, or <NUM> bits. For some embodiments, the N2 filler bits may be concatenated to an initial bit of the data block. In some embodiments, the N2 filler bits may be concatenated to a final bit of the data block. For some embodiments, the N2 filler bits may be dispersed within the data block.

<FIG> illustrates methods for an eNB for supporting filler bit attachment in Polar encoding schemes, in accordance with the invention. With reference to <FIG>, various methods that may relate to eNB <NUM> and hardware processing circuitry <NUM> are discussed herein. Although the actions in method <NUM> of <FIG> are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions may be performed in parallel. Some of the actions and/or operations listed in <FIG> are optional in accordance with certain embodiments. The numbering of the actions presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various actions must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

Moreover, in some embodiments, machine readable storage media may have executable instructions that, when executed, cause eNB <NUM> and/or hardware processing circuitry <NUM> to perform an operation comprising the methods of <FIG>. Such machine readable storage media may include any of a variety of storage media, like magnetic storage media (e.g., magnetic tapes or magnetic disks), optical storage media (e.g., optical discs), electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash-memory-based storage media), or any other tangible storage media or non-transitory storage media.

Returning to <FIG>, various methods may be in accordance with the various embodiments discussed herein. According to the invention, a method <NUM> comprises a decoding <NUM>, a determining <NUM>, and a de-padding <NUM>. Method <NUM> also comprises an identifying <NUM>, an identifying <NUM>, a decoding <NUM>, and may also comprise an identifying <NUM>, an identifying <NUM>, and/or a decoding <NUM>.

In decoding <NUM>, a Polar codeword having a number M1 of bits is decoded to extract a padded data block having a number M2 of bits. In determining <NUM>, a number M3 of filler bits is determined based on a number M4 of bits of a data block within the padded data block and a set of parameters. In de-padding <NUM>, the M2 bits of the padded data block are de-padded to form a data block having the number M4 of bits.

According to the invention, in identifying <NUM>, based on at least the number M2, a number M5 of parity-check bits and locations at a Polar decoder (e.g., at an output of the Polar decoder) for the M5 parity-check bits are identified. In identifying <NUM>, M2 locations at the Polar decoder (e.g., at the output of the Polar decoder) for removing the M2 bits of the padded data block are identified. In decoding <NUM>, the M2 bits of the padded data block, the M5 parity-check bits, and/or a number M6 of frozen bits are decoded from the M1 bits of the Polar codeword.

In identifying <NUM>, M2 locations at a Polar decoder (e.g., at the output of the Polar decoder) for extracting the M2 bits of the padded data block may be identified, based on a sequence. In identifying <NUM>, a number M6 of locations at the Polar decoder (e.g., at the output of the Polar decoder) for extracting M6 frozen bits may be identified, based on the sequence. In decoding <NUM>, the M2 bits of the padded data block and/or the M6 frozen bits may be decoded from the M1 bits of the frozen codeword.

According to the invention, the set of parameters consists of a range of supported block sizes which are multiples of at least one of: <NUM> bits, or <NUM> bits, or <NUM> bits. For some embodiments, the M3 filler bits may be concatenated to an initial bit of the data block. In some embodiments, the M3 filler bits may be concatenated to a final bit of the data block. For some embodiments, the M3 filler bits may be dispersed within the data block.

<FIG> illustrates example components of a device, in accordance with some embodiments of the disclosure. In some embodiments, the device <NUM> may include application circuitry <NUM>, baseband circuitry <NUM>, Radio Frequency (RF) circuitry <NUM>, front-end module (FEM) circuitry <NUM>, one or more antennas <NUM>, and power management circuitry (PMC) <NUM> coupled together at least as shown. The components of the illustrated device <NUM> may be included in a UE or a RAN node. In some embodiments, the device <NUM> may include less elements (e.g., a RAN node may not utilize application circuitry <NUM>, and instead include a processor/controller to process IP data received from an EPC). In some embodiments, the device <NUM> may include additional elements such as, for example, memory /storage, display, camera, sensor, or input/output (I/O) interface. In other embodiments, the components described below may be included in more than one device (e.g., said circuitries may be separately included in more than one device for Cloud-RAN (C-RAN) implementations).

The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, and so on). The processors may be coupled with or may include memory /storage and may be configured to execute instructions stored in the memory /storage to enable various applications or operating systems to run on the device <NUM>.

The baseband circuitry <NUM> may include one or more baseband processors or control logic to process baseband signals received from a receive signal path of the RF circuitry <NUM> and to generate baseband signals for a transmit signal path of the RF circuitry <NUM>. Baseband processing circuity <NUM> may interface with the application circuitry <NUM> for generation and processing of the baseband signals and for controlling operations of the RF circuitry <NUM>. For example, in some embodiments, the baseband circuitry <NUM> may include a third generation (<NUM>) baseband processor 1104A, a fourth generation (<NUM>) baseband processor 1104B, a fifth generation (<NUM>) baseband processor 1104C, or other baseband processor(s) 1104D for other existing generations, generations in development or to be developed in the future (e.g., second generation (<NUM>), sixth generation (<NUM>), and so on). The baseband circuitry <NUM> (e.g., one or more of baseband processors 1104A-D) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry <NUM>. In other embodiments, some or all of the functionality of baseband processors 1104A-D may be included in modules stored in the memory <NUM> and executed via a Central Processing Unit (CPU) 1104E. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, and so on. In some embodiments, modulation/demodulation circuitry of the baseband circuitry <NUM> may include Fast-Fourier Transform (FFT), precoding, or constellation mapping/demapping functionality. In some embodiments, encoding/decoding circuitry of the baseband circuitry <NUM> may include convolution, tail-biting convolution, turbo, Viterbi, or Low Density Parity Check (LDPC) encoder/decoder functionality. Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.

In some embodiments, the baseband circuitry <NUM> may include one or more audio digital signal processor(s) (DSP) 1104F. The audio DSP(s) 1104F may include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments. Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry <NUM> and the application circuitry <NUM> may be implemented together such as, for example, on a system on a chip (SOC).

In various embodiments, the RF circuitry <NUM> may include switches, filters, amplifiers, and so on to facilitate the communication with the wireless network.

In some embodiments, the receive signal path of the RF circuitry <NUM> may include mixer circuitry <NUM> A, amplifier circuitry 1106B and filter circuitry 1106C. In some embodiments, the transmit signal path of the RF circuitry <NUM> may include filter circuitry 1106C and mixer circuitry 1106A. RF circuitry <NUM> may also include synthesizer circuitry 1106D for synthesizing a frequency for use by the mixer circuitry <NUM> A of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry <NUM> A of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry <NUM> based on the synthesized frequency provided by synthesizer circuitry 1106D. The amplifier circuitry 1106B may be configured to amplify the down-converted signals and the filter circuitry 1106C may be a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry <NUM> for further processing. In some embodiments, the output baseband signals may be zero-frequency baseband signals, although this is not a requirement. In some embodiments, mixer circuitry <NUM> A of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuitry 1106A of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 1106D to generate RF output signals for the FEM circuitry <NUM>. The baseband signals may be provided by the baseband circuitry <NUM> and may be filtered by filter circuitry 1106C.

In some embodiments, the mixer circuitry 1106A of the receive signal path and the mixer circuitry 1106A of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and upconversion, respectively. In some embodiments, the mixer circuitry <NUM> A of the receive signal path and the mixer circuitry 1106A of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry <NUM> A of the receive signal path and the mixer circuitry <NUM> A may be arranged for direct downconversion and direct upconversion, respectively. In some embodiments, the mixer circuitry 1106A of the receive signal path and the mixer circuitry 1106A of the transmit signal path may be configured for superheterodyne operation.

In some embodiments, the synthesizer circuitry 1106D may be a fractional-N synthesizer or a fractional N/N+<NUM> synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry 1106D may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.

The synthesizer circuitry 1106D may be configured to synthesize an output frequency for use by the mixer circuitry <NUM> A of the RF circuitry <NUM> based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 1106D may be a fractional N/N+<NUM> synthesizer.

Synthesizer circuitry 1106D of the RF circuitry <NUM> may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator. In some embodiments, the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DP A). In some embodiments, the DMD may be configured to divide the input signal by either N or N+<NUM> (e.g., based on a carry out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop. In these embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

In some embodiments, synthesizer circuitry 1106D may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be a LO frequency (fLO). In some embodiments, the RF circuitry <NUM> may include an IQ/polar converter.

While <FIG> shows the PMC <NUM> coupled only with the baseband circuitry <NUM>. However, in other embodiments, the PMC <NUM> may be additionally or alternatively coupled with, and perform similar power management operations for, other components such as, but not limited to, application circuitry <NUM>, RF circuitry <NUM>, or FEM <NUM>.

If there is no data traffic activity for an extended period of time, then the device <NUM> may transition off to an RRC_Idle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, and so on. The device <NUM> goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again. The device <NUM> may not receive data in this state, in order to receive data, it must transition back to RRC_Connected state.

<FIG> illustrates example interfaces of baseband circuitry, in accordance with some embodiments of the disclosure. As discussed above, the baseband circuitry <NUM> of <FIG> may comprise processors 1104A-1104E and a memory <NUM> utilized by said processors. Each of the processors 1104A-1104E may include a memory interface, 1204A-1204E, respectively, to send/receive data to/from the memory <NUM>.

It is pointed out that elements of any of the Figures herein having the same reference numbers and/or names as elements of any other Figure herein may, in various embodiments, operate or function in a manner similar those elements of the other Figure (without being limited to operating or functioning in such a manner).

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures e.g., Dynamic RAM (DRAM) may use the embodiments discussed. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

Claim 1:
An apparatus of a User Equipment, UE (<NUM>), operable to communicate with a Next-generation Node-B for New Radio, gNB (<NUM>), on a wireless network, comprising:
one or more processors (<NUM>) configured to:
identify a data block having a number N1 of bits (<NUM>);
determine a number N2 of filler bits based on a set of parameters and the number N1 of bits of the data block (<NUM>), wherein the set of parameters consists of a range of supported block sizes which are multiples of one of <NUM> bits, or <NUM> bits, or <NUM> bits;
pad the data block with the N2 filler bits to form a padded data block having a number N3 of bits (<NUM>) constituting a supported block size, wherein the padding intersperses the N2 filler bits within the data block;
identify, based on at least the number N3, a number N5 of parity-check bits and locations at an input of a polar encoder for the N5 parity-check bits (<NUM>);
identify N3 locations at an input of the polar encoder for inserting the N3 bits of the padded data block (<NUM>);
encode the N3 bits of the padded data block, the N5 parity-check bits, and a number N6 of frozen bits to form a number N4 of bits of a polar codeword (<NUM>); and
an interface (<NUM>) for sending a transmission based on the polar codeword to a transmission circuitry (<NUM>).