Patent Description:
The present disclosure relates generally to high-speed data communication interfaces, and more particularly, to improving data throughput over a multi-wire, multi-phase data communication link.

Manufacturers of mobile devices, such as cellular phones, may obtain components of the mobile devices from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, while an imaging device or camera may be obtained from a second manufacturer, and a display may be obtained from a third manufacturer. The application processor, the imaging device, the display controller, or other types of device may be interconnected using a standards-based or proprietary physical interface. In one example, an imaging device may be connected using the Camera Serial Interface (CSI) defined by the Mobile Industry Processor Interface (MIPI) Alliance. In another example, a display may include an interface that conforms to the Display Serial Interface (DSI) standard specified by the Mobile Industry Processor Interface (MIPI) Alliance.

A multiphase three-wire (C-PHY) interface defined by the MIPI Alliance uses a trio of conductors to transmit information between devices. Each of the three wires may be in one of three signaling states during transmission of a symbol over the C-PHY interface. Clock information is encoded in a sequence of symbols transmitted on the C-PHY interface and a receiver generates a clock signal from transitions between consecutive symbols. The maximum speed of the C-PHY interface and the ability of a clock and data recovery (CDR) circuit to recover clock information may be limited by the maximum time variation related to transitions of signals transmitted on the different wires of the communication link, which can limit the number of symbols transmitted per second. The continual increase in services and performance provided by mobile devices has resulted in an ongoing demand for increased data throughput on multi-phase, multi-wire interfaces. <CIT> discloses an encoder encoding data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic <NUM> and a set of logic <NUM>) on output nodes. The encoder selects a current codeword from a group of codewords in a codespace which does not overlap the other group of codewords, i.e., codewords in a given group of codewords are not included in any other group of codewords in the codespace. This property allows a receiver of the codewords to be simplified. In particular, a mathematical operation performed on symbols in the current codeword uniquely specifies the corresponding group of codewords. This allows a decoder to decode the current codeword using comparisons of symbols received on a subset of all possible combinations of node pairs. <CIT> discloses methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface. A method includes equalizing three-phase signals received from two wires of the interface to provide equalized signals, providing first and second difference signals by comparing voltage differences between the equalized signals with first and second reference voltage levels respectively, capturing delayed and undelayed versions of the second difference signal using flipflops triggered by different edges in the first difference signal, and adjusting an equalizing circuit until outputs of the first flipflops indicate that a ratio of low-frequency attenuation to high-frequency amplification has been achieved that enables information to be accurately decoded from the three-phase signals. The three-phase signal received from a first of the two wires is in a different phase than the three-phase signal received from a second of the two wires.

Certain embodiments disclosed herein provide systems, methods and apparatus that enable improved communication on a multi-wire and/or multiphase communication link through improved encoding techniques and protocol. In some embodiments, data throughput is improved by increasing the symbol clock rate used on the communication link. The communication link may be deployed in apparatus such as a mobile terminal having multiple Integrated Circuit (IC) devices.

In various aspects of the disclosure, a data communication apparatus has a plurality of line drivers configured to couple the apparatus to a <NUM>-wire link, a first wire state encoder configured to receive a first symbol in a sequence of symbols when the <NUM>-wire link is in a first signaling state, and to define a second signaling state for the <NUM>-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the <NUM>-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The <NUM>-wire link transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals. The signaling states of at least one wire in the <NUM>-wire link changes when the <NUM>-wire link transitions from the second signaling state to the third signaling state.

In one aspect, each of the first wire state encoder and the second wire state encoder defines signaling states for the <NUM>-wire link every two symbol transmission intervals.

In certain aspects, the apparatus includes a clock generation circuit configured to provide a half-rate symbol clock signal that has a period twice the duration of each symbol transmission interval. The apparatus may have a driver control circuit configured to control the plurality of line drivers, and a multiplexer that selects between the second signaling state and the third signaling state to provide wire state information to the driver control circuit. The multiplexer may select between the second signaling state and the third signaling state based on phase of the half-rate symbol clock signal. The apparatus may have first plurality of flipflops clocked by an inverse of the half-rate symbol clock signal and configured to capture first control signals representative of the second signaling state, second plurality of flipflops clocked by the half-rate symbol clock signal and configured to capture second control signals representative of the third signaling state. The multiplexer may be further configured to provide the first control signals or the second control signals as the wire state information.

In one aspect, the apparatus has one or more mappers configured to map at least <NUM> bits of data to at least <NUM> symbols in the sequence of symbols. The <NUM>-wire link may be operated in accordance with a C-PHY protocol.

In one aspect, the apparatus has an equalizer circuit configured to receive delayed versions of the second signaling state and the third signaling state, and to configure the plurality of line drivers when initiating transmission of the third signaling state based on differences between the second signaling state and the third signaling state.

In various aspects of the disclosure, a data communication method includes configuring a plurality of line drivers to couple the apparatus to a <NUM>-wire link, receiving a first symbol in a sequence of symbols at a first wire state encoder when the <NUM>-wire link is in a first signaling state, defining a second signaling state for the <NUM>-wire link based on the first symbol and the first signaling state, receiving a second symbol in the sequence of symbols at a second wire state encoder, and defining a third signaling state for the <NUM>-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The <NUM>-wire link transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals. Signaling state of at least one wire in the <NUM>-wire link changes when the <NUM>-wire link transitions from the second signaling state to the third signaling state.

In various aspects of the disclosure, a processor-readable storage medium includes code for configuring a plurality of line drivers to couple the apparatus to a <NUM>-wire link, receiving a first symbol in a sequence of symbols at a first wire state encoder when the <NUM>-wire link is in a first signaling state, defining a second signaling state for the <NUM>-wire link based on the first symbol and the first signaling state, receiving a second symbol in the sequence of symbols at a second wire state encoder, and defining a third signaling state for the <NUM>-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The <NUM>-wire link transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals. Signaling states of at least one wire in the <NUM>-wire link changes when the <NUM>-wire link transitions from the second signaling state to the third signaling state.

In various aspects of the disclosure, a data communication apparatus, has a plurality of receivers configured to provide difference signals representative of differences in signaling state between each pair of wires in a <NUM>-wire link, a first wire state decoder configured to provide a first symbol based on differences between state of the difference signals in a first half-cycle of a symbol clock and state of the difference signals in a second half-cycle of the symbol clock that immediately precedes the first half-cycle in the symbol clock, a second wire state decoder configured to provide a second symbol based on differences between the state of the difference signals in the second half-cycle of the symbol clock and state of the difference signals in a third half-cycle of the symbol clock that immediately precedes the second half-cycle in the symbol clock, and a demapper configured to decode data from a sequence of symbols that includes the first symbol and the second symbol. The first symbol immediately precedes the second symbol in the sequence of symbols.

In some aspects, signaling state of at least one difference signal changes at each transition between half-cycles of the half-rate symbol clock. The apparatus may include a clock recovery circuit configured to derive the symbol clock from the difference signals.

In certain aspects, the apparatus includes a plurality of difference signal processors. Each difference signal processor is coupled to an associated difference signal. Each difference signal processor may be configured to provide a first signal representing the state of the corresponding difference signal in the first half-cycle of the symbol clock, a second signal representing the state of the corresponding difference signal in the second half-cycle of the symbol clock, and a third signal representing the state of the corresponding difference signal in the third half-cycle of the symbol clock.

In one aspect, the demapper is further configured to decode a <NUM>-bit word from each of a plurality of sequences of seven symbols or decode a <NUM>-bit word from each pair of sequences of seven symbols generated concurrently by the first wire state decoder and the second wire state decoder. The <NUM>-wire link may be operated in accordance with a C-PHY protocol.

In various aspects of the disclosure, a data communication method includes providing difference signals representative of differences in signaling state between each pair of wires in a <NUM>-wire link, providing a first symbol based on differences between state of the difference signals in a first half-cycle of a symbol clock and state of the difference signals in a second half-cycle of the symbol clock that immediately precedes the first half-cycle in the symbol clock, providing a second symbol based on differences between the state of the difference signals in the second half-cycle of the symbol clock and state of the difference signals in a third half-cycle of the symbol clock that immediately precedes the second half-cycle in the symbol clock, and decoding data from a sequence of symbols that includes the first symbol and the second symbol. The first symbol may immediately precede the second symbol in the sequence of symbols.

In various aspects of the disclosure, includes code for providing difference signals representative of differences in signaling state between each pair of wires in a <NUM>-wire link, providing a first symbol based on differences between state of the difference signals in a first half-cycle of a symbol clock and state of the difference signals in a second half-cycle of the symbol clock that immediately precedes the first half-cycle in the symbol clock, providing a second symbol based on differences between the state of the difference signals in the second half-cycle of the symbol clock and state of the difference signals in a third half-cycle of the symbol clock that immediately precedes the second half-cycle in the symbol clock, and decoding data from a sequence of symbols that includes the first symbol and the second symbol. The first symbol may immediately precede the second symbol in the sequence of symbols.

As used in this application, the terms "component," "module," "system" and the like are intended to include a computer-related entity, such as, but not limited to hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various processor-readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets, such as data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal.

Certain aspects of the invention may be applicable to improving a C-PHY interface specified by the MIPI Alliance, which is often deployed to connect electronic devices that are subcomponents of a mobile apparatus such as a telephone, a mobile computing device, an appliance, automobile electronics, avionics systems, etc. Examples of a mobile apparatus include a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a global positioning system (GPS) device, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, etc.), an appliance, a sensor, a vending machine, or any other similarly functioning device.

Certain aspects disclosed herein enable devices to communicate at higher data rates over a three-wire communication link than possible using conventional C-PHY symbol rates. In various aspects of the disclosure, a data communication apparatus has a plurality of line drivers configured to couple the apparatus to a <NUM>-wire link, and a data encoder configured to encode at least <NUM> bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the <NUM>-wire link such that each pair of consecutively-transmitted symbols includes two different symbols. Each symbol defines signaling states of the <NUM>-wire link during an associated symbol transmission interval such that each wire of the <NUM>-wire link is in a different signaling state from the other wires of the of the <NUM>-wire link during the associated symbol transmission interval. Data may be encoded using a combination of <NUM>-phase and pulse amplitude modulation. The apparatus may include a wire state encoder configured to receive a sequence of symbols from the data encoder, and provide control signals to the plurality of line drivers. The control signals cause each of the plurality of line drivers to drive one wire of the <NUM>-wire link to a signaling state defined by each symbol during a symbol transmission interval provided for each symbol in the sequence of symbols.

The C-PHY interface is a high-speed serial interface that can provide high throughput over bandwidth-limited channels. The C-PHY interface may be deployed to connect application processors to peripherals, including displays and cameras. The C-PHY interface encodes data into symbols that are transmitted in a three-phase signal over a set of three wires, which may be referred to as a trio, or as a trio of wires. The three-phase signal is transmitted on each wire of the trio in different phases. Each three-wire trio provides a lane on a communication link. A symbol interval may be defined as the interval of time in which a single symbol controls the signaling state of a trio. In each symbol interval, one wire is undriven or is driven to an intermediate voltage state while the remaining two of the three wires are differentially driven such that one of the two differentially driven wires assumes a first voltage level and the other differentially driven wire assumes to a second voltage level different from the first voltage level. The undriven wire may float, and/or be terminated such that it assumes a third voltage level that is at or near the intermediate voltage level, which may be a mid-level voltage level between the first and second voltage levels. In one example, the driven voltage levels may be +V and -V with the third voltage being <NUM> Volts. In another example, the driven voltage levels may be +V and <NUM> Volts with the undriven voltage being +V/<NUM>. Different symbols are transmitted in each consecutively transmitted pair of symbols, and different pairs of wires may be differentially driven in different symbol intervals.

<FIG> depicts an example of apparatus <NUM> that may employ C-PHY <NUM>-phase protocols to implement one or more communication links. The apparatus <NUM> may include an SoC a processing circuit <NUM> having multiple circuits or devices <NUM>, <NUM> and/or <NUM>, which may be implemented in one or more ASICs or in an SoC. In one example, the apparatus <NUM> may be a communication device and the processing circuit <NUM> may include a processing device provided in an ASIC <NUM>, one or more peripheral devices <NUM>, and a transceiver <NUM> that enables the apparatus to communicate through an antenna <NUM> with a radio access network, a core access network, the Internet and/or another network.

The ASIC <NUM> may have one or more processors <NUM>, one or more modems <NUM>, on-board memory <NUM>, a bus interface circuit <NUM> and/or other logic circuits or functions. The processing circuit <NUM> may be controlled by an operating system that may provide an application programming interface (API) layer that enables the one or more processors <NUM> to execute software modules residing in the on-board memory <NUM> or other processor-readable storage <NUM> provided on the processing circuit <NUM>. The software modules may include instructions and data stored in the on-board memory <NUM> or processor-readable storage <NUM>. The ASIC <NUM> may access its on-board memory <NUM>, the processor-readable storage <NUM>, and/or storage external to the processing circuit <NUM>. The on-board memory <NUM>, the processor-readable storage <NUM> may include read-only memory (ROM) or random-access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. The processing circuit <NUM> may include, implement, or have access to a local database or other parameter storage that can maintain operational parameters and other information used to configure and operate the apparatus <NUM> and/or the processing circuit <NUM>. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, soft or hard disk, or the like. The processing circuit <NUM> may also be operably coupled to external devices such as the antenna <NUM>, a display <NUM>, operator controls, such as switches or buttons <NUM>, <NUM> and/or an integrated or external keypad <NUM>, among other components. A user interface module may be configured to operate with the display <NUM>, external keypad <NUM>, etc. through a dedicated communication link or through one or more serial data interconnects.

The processing circuit <NUM> may provide one or more buses 118a, 118b, <NUM> that enable certain devices <NUM>, <NUM>, and/or <NUM> to communicate. In one example, the ASIC <NUM> may include a bus interface circuit <NUM> that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules. In one example, the bus interface circuit <NUM> may be configured to operate in accordance with communication specifications or protocols. The processing circuit <NUM> may include or control a power management function that configures and manages the operation of the apparatus <NUM>.

<FIG> illustrates certain aspects of an apparatus <NUM> that includes a plurality of IC devices <NUM> and <NUM>, which can exchange data and control information through a communication link <NUM>. The communication link <NUM> may be used to connect a pair of IC devices <NUM> and <NUM> that are located in close proximity to one another, or that are physically located in different parts of the apparatus <NUM>. In one example, the communication link <NUM> may be provided on a chip carrier, substrate or circuit board that carries the IC devices <NUM> and <NUM>. In another example, a first IC device <NUM> may be located in a keypad section of a flip-phone while a second IC device <NUM> may be located in a display section of the flip-phone. In another example, a portion of the communication link <NUM> may include a cable or optical connection.

The communication link <NUM> may include multiple channels <NUM>, <NUM> and <NUM>. One or more channel <NUM> may be bidirectional, and may operate in half-duplex and/or full-duplex modes. One or more channel <NUM> and <NUM> may be unidirectional. The communication link <NUM> may be asymmetrical, providing higher bandwidth in one direction. In one example described herein, a first channel <NUM> may be referred to as a forward channel <NUM> while a second channel <NUM> may be referred to as a reverse channel <NUM>. The first IC device <NUM> may be designated as a host system or transmitter, while the second IC device <NUM> may be designated as a client system or receiver, even if both IC devices <NUM> and <NUM> are configured to transmit and receive on the channel <NUM>. In one example, the forward channel <NUM> may operate at a higher data rate when communicating data from a first IC device <NUM> to a second IC device <NUM>, while the reverse channel <NUM> may operate at a lower data rate when communicating data from the second IC device <NUM> to the first IC device <NUM>.

The IC devices <NUM> and <NUM> may each include a processor <NUM>, <NUM> or other processing and/or computing circuit or device. In one example, the first IC device <NUM> may perform core functions of the apparatus <NUM>, including establishing and maintaining wireless communication through a wireless transceiver <NUM> and an antenna <NUM>, while the second IC device <NUM> may support a user interface that manages or operates a display controller <NUM>, and may control operations of a camera or video input device using a camera controller <NUM>. Other features supported by one or more of the IC devices <NUM> and <NUM> may include a keyboard, a voice-recognition component, and other input or output devices. The display controller <NUM> may include circuits and software drivers that support displays such as a liquid crystal display (LCD) panel, touch-screen display, indicators and so on. The storage media <NUM> and <NUM> may include transitory and/or non-transitory storage devices adapted to maintain instructions and data used by respective processors <NUM> and <NUM>, and/or other components of the IC devices <NUM> and <NUM>. Communication between each processor <NUM>, <NUM> and its corresponding storage media <NUM> and <NUM> and other modules and circuits may be facilitated by one or more internal bus <NUM> and <NUM> and/or a channel <NUM>, <NUM> and/or <NUM> of the communication link <NUM>.

The reverse channel <NUM> may be operated in the same manner as the forward channel <NUM>, and the forward channel <NUM> and the reverse channel <NUM> may be capable of transmitting at comparable speeds or at different speeds, where speed may be expressed as data transfer rate, symbol transmission rate and/or clocking rates. The forward and reverse data rates may be substantially the same or may differ by orders of magnitude, depending on the application. In some applications, a single bidirectional channel <NUM> may support communication between the first IC device <NUM> and the second IC device <NUM>. The forward channel <NUM> and/or the reverse channel <NUM> may be configurable to operate in a bidirectional mode when, for example, the forward and reverse channels <NUM> and <NUM> share the same physical connections and operate in a half-duplex manner. In one example, the communication link <NUM> may be operated to communicate control, command and other information between the first IC device <NUM> and the second IC device <NUM> in accordance with an industry or other standard.

The communication link <NUM> of <FIG> may be implemented according to MIPI Alliance specifications for C-PHY and may provide a wired bus that includes a plurality of signal wires (denoted as M wires). The M wires may be configured to carry N-phase encoded data in a high-speed digital interface, such as a mobile display digital interface (MDDI). The M wires may facilitate N-phase polarity encoding on one or more of the channels <NUM>, <NUM> and <NUM>. The physical layer drivers <NUM> and <NUM> may be configured or adapted to generate N-phase polarity encoded data for transmission on the communication link <NUM>. The use of N-phase polarity encoding provides high speed data transfer and may consume half or less of the power of other interfaces because fewer drivers are active in N-phase polarity encoded data links.

The physical layer drivers <NUM> and <NUM> can typically encode multiple bits per transition on the communication link <NUM> when configured for N-phase polarity encoding. In one example, a combination of <NUM>-phase encoding and polarity encoding may be used to support a wide video graphics array (WVGA) <NUM> frames per second LCD driver IC without a frame buffer, delivering pixel data at <NUM> Mbps for display refresh.

<FIG> is a diagram <NUM> illustrating a <NUM>-wire, <NUM>-phase polarity encoder that may be used to implement certain aspects of the communication link <NUM> depicted in <FIG>. The example of <NUM>-wire, <NUM>-phase encoding is selected solely for the purpose of simplifying descriptions of certain aspects of the invention. The principles and techniques disclosed for <NUM>-wire, <NUM>-phase encoders can be applied in other configurations of M-wire, N-phase polarity encoders.

Signaling states defined for each of the <NUM> wires in a <NUM>-wire, <NUM>-phase polarity encoding scheme may include a positively driven state, a negatively driven state and an intermediate or undriven state. The positively driven state and the negatively driven state may be obtained by providing a voltage differential between two of the signal wires 318a, 318b and/or 318c, and/or by driving a current through two of the signal wires 318a, 318b and/or 318c connected in series such that the current flows in different directions in the two signal wires 318a, 318b and/or 318c. A third state may be provided as an undriven state realized by placing an output of a driver of a signal wire 318a, 318b or 318c in a high-impedance mode. Typically, there is no significant current flow through an undriven signal wire 318a, 318b or 318c. Alternatively, or additionally, the third state may be an intermediate state obtained on a signal wire 318a, 318b or 318c by passively or actively causing one signal wire 318a, 318b or 318c to attain a voltage level that lies substantially halfway between positive and negative voltage levels provided on driven signal wires 318a, 318b and/or 318c. Signaling states defined for a <NUM>-wire, <NUM>-phase polarity encoding scheme may be denoted using the three voltage or current states (+<NUM>, -<NUM>, and <NUM>).

A <NUM>-wire, <NUM>-phase polarity encoder may employ line drivers <NUM> to control the signaling state of signal wires 318a, 318b and 318c. The line drivers <NUM> may be implemented as unit-level current-mode or voltage-mode drivers. In some implementations, each line driver <NUM> may receive sets of signals 316a, 316b and 316c that determine the output state of corresponding signal wires 318a, 318b and 318c. In one example, each of the sets of signals 316a, 316b and 316c may include two or more signals, including a pull-up signal (PU signal) and a pull-down signal (PD signal) that, when high, activate pull-up and pull down circuits that drive the signal wires 318a, 318b and 318c toward a higher level or lower level voltage, respectively. In this example, when both the PU signal and the PD signal are low, the signal wires 318a, 318b and 318c may be terminated to a mid-level voltage.

For each transmitted symbol interval in an <NUM>-wire, <NUM>-phase polarity encoding scheme, at least one signal wire 318a, 318b or 318c is in the midlevel/undriven (<NUM>) voltage or current state, while the number of positively driven (+<NUM> voltage or current state) signal wires 318a, 318b or 318c is equal to the number of negatively driven (-<NUM> voltage or current state) signal wires 318a, 318b or 318c, such that the sum of current flowing to the receiver is always zero. For each symbol, the signaling state of at least one signal wire 318a, 318b or 318c is changed from the wire state transmitted in the preceding transmission interval.

In operation, a mapper <NUM> may receive and map <NUM>-bit data <NUM> to <NUM> symbols <NUM>. In the C-PHY example, each of the <NUM> symbols defines the states of the signal wires 318a, 318b and 318c for one symbol interval. The <NUM> symbols <NUM> may be serialized using parallel-to-serial converters <NUM> that provide a timed sequence of symbols <NUM> for each signal wire 318a, 318b and 318c. The sequence of symbols <NUM> is typically timed using a transmission clock. A <NUM>-wire, <NUM>-phase encoder <NUM> receives the sequence of <NUM> symbols <NUM> produced by the mapper one symbol at a time and computes the state of each signal wire 318a, 318b and 318c for each symbol interval. The <NUM>-wire, <NUM>-phase encoder <NUM> selects the states of the signal wires 318a, 318b and 318c based on the current input symbol <NUM> and the previous states of signal wires 318a, 318b and 318c.

The use of <NUM>-wire, <NUM>-phase encoding permits a number of bits to be encoded in a plurality of symbols where the bits per symbol is not an integer. In the example of a C-PHY communication link, there are <NUM> available combinations of <NUM> wires, which may be driven simultaneously, and <NUM> possible combinations of polarity on the pair of wires that is driven, yielding <NUM> possible states. Since each transition occurs from a current state, <NUM> of the <NUM> states are available at every transition. The state of at least one wire is required to change at each transition. With <NUM> states, log<NUM>(<NUM>) ≅ <NUM> bits may be encoded per symbol. Accordingly, a mapper may accept a <NUM>-bit word and convert it to <NUM> symbols because <NUM> symbols carrying <NUM> bits per symbol can encode <NUM> bits. In other words, a combination of seven symbols that encode five states has <NUM><NUM> (<NUM>,<NUM>) permutations. Accordingly, the <NUM> symbols may be used to encode the <NUM><NUM> (<NUM>,<NUM>) permutations of <NUM> bits.

<FIG> includes an example of a timing chart <NUM> for signals encoded using a three-phase modulation data-encoding scheme, which is based on the circular state diagram <NUM>. Information may be encoded in a sequence of signaling states where, for example, a wire or connector is in one of three phase states S<NUM>, S<NUM> and S<NUM> defined by the circular state diagram <NUM>. Each state may be separated from the other states by a <NUM>° phase shift. In one example, data may be encoded in the direction of rotation of phase states on the wire or connector. The phase states in a signal may rotate in clockwise direction <NUM> and <NUM>' or counterclockwise direction <NUM> and <NUM>'. In the clockwise direction <NUM> and <NUM>' for example, the phase states may advance in a sequence that includes one or more of the transitions from S<NUM> to S<NUM>, from S<NUM> to S<NUM> and from S<NUM> to S<NUM>. In the counterclockwise direction <NUM> and <NUM>', the phase states may advance in a sequence that includes one or more of the transitions from S<NUM> to S<NUM>, from S<NUM> to S<NUM> and from S<NUM> to S<NUM>. The three signal wires 318a, 318b and 318c carry different versions of the same signal, where the versions may be phase shifted by <NUM>° with respect to one another. Each signaling state may be represented as a different voltage level on a wire or connector and/or a direction of current flow through the wire or connector. During each of the sequence of signaling states in a <NUM>-wire system, each signal wire 318a, 318b and 318c is in a different signaling states than the other wires. When more than <NUM> signal wires 318a, 318b and 318c are used in a <NUM>-phase encoding system, two or more signal wires 318a, 318b and/or 318c can be in the same signaling state at each signaling interval, although each state is present on at least one signal wire 318a, 318b and/or 318c in every signaling interval.

Information may be encoded in the direction of rotation at each phase transition <NUM>, and the <NUM>-phase signal may change direction for each signaling state. Direction of rotation may be determined by considering which signal wires 318a, 318b and/or 318c are in the '<NUM>' state before and after a phase transition, because the undriven signal wire 318a, 318b and/or 318c changes at every signaling state in a rotating three-phase signal, regardless of the direction of rotation.

The encoding scheme may also encode information in the polarity <NUM> of the two signal wires 318a, 318b and/or 318c that are actively driven. At any time in a <NUM>-wire implementation, exactly two of the signal wires 318a, 318b, 318c are driven with currents in opposite directions and/or with a voltage differential. In one implementation, data may be encoded using two bit values <NUM>, where one bit is encoded in the direction of phase transitions <NUM> and the second bit is encoded in the polarity <NUM> for the current state.

The timing chart <NUM> illustrates data encoding using both phase rotation direction and polarity. The curves <NUM>, <NUM> and <NUM> relate to signals carried on three signal wires 318a, 318b and 318c, respectively for multiple phase states. Initially, the phase transitions <NUM> are in a clockwise direction and the most significant bit is set to binary `<NUM>,' until the rotation of phase transitions <NUM> switches at a time <NUM> to a counterclockwise direction, as represented by a binary '<NUM>' of the most significant bit. The least significant bit reflects the polarity <NUM> of the signal in each state.

According to certain aspects disclosed herein, one bit of data may be encoded in the rotation, or phase change in a <NUM>-wire, <NUM>-phase encoding system, and an additional bit may be encoded in the polarity of the two driven wires. Additional information may be encoded in each transition of a <NUM>-wire, <NUM>-phase encoding system by allowing transition to any of the possible states from a current state. Given <NUM> rotational phases and two polarities for each phase, <NUM> states are available in a <NUM>-wire, <NUM>-phase encoding system. Accordingly, <NUM> states are available from any current state, and there may be log<NUM>(<NUM>) ≅ <NUM> bits encoded per symbol (transition), which allows the mapper <NUM> to accept a <NUM>-bit word and encode it in <NUM> symbols.

<FIG> is a diagram illustrating certain aspects of a <NUM>-wire, <NUM>-phase decoder <NUM>. Differential receivers 502a, 502b, 502c and a wire state decoder <NUM> are configured to provide a digital representation of the state of the three transmission lines (e.g., the signal wires 318a, 318b and 318c illustrated in <FIG>), with respect to one another, and to detect changes in the state of the three transmission lines compared to the state transmitted in the previous symbol period. Seven consecutive states are assembled by the serial-to-parallel convertors <NUM> to obtain a set of <NUM> symbols <NUM> to be processed by the demapper <NUM>. The demapper <NUM> produces <NUM> bits of data <NUM> that may be buffered in a first-in-first-out (FIFO) register <NUM> to provide output data <NUM>.

The wire state decoder <NUM> may extract a sequence of symbols <NUM> from phase encoded signals received on the signal wires 318a, 318b and 318c. The symbols <NUM> are encoded as a combination of phase rotation and polarity as disclosed herein. The wire state decoder may include a CDR circuit <NUM> that extracts a clock <NUM> that can be used to reliably capture wire states from the signal wires 318a, 318b and 318c. A transition occurs on least one of the signal wires 318a, 318b and 318c at each symbol boundary and the CDR circuit <NUM> may be configured to generate the clock <NUM> based on the occurrence of a transition or multiple transitions. An edge of the clock may be delayed to allow time for all signal wires 318a, 318b and 318c to have stabilized and to thereby ensure that the current wire state is captured for decoding purposes.

<FIG> is state diagram <NUM> illustrating the possible signaling states <NUM>, <NUM>, <NUM>, <NUM>, <NUM>, <NUM> of the three wires, with the possible transitions illustrated from each state. In the example of a <NUM>-wire, <NUM>-phase communication link, <NUM> states and <NUM> state transitions are available. The possible signaling states <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> in the state diagram <NUM> include and expand on the states shown in the circular state diagram <NUM> of <FIG>. As shown in the exemplar of a state element <NUM>, each signaling state <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> in the state diagram <NUM> defines voltage signaling state of the signal wires 318a, 318b, 318c, which are labeled A, B and C respectively. For example, in signaling state <NUM> (+x) wire A= +<NUM>, wire B = -<NUM> and wire C= <NUM>, yielding output of differential receiver 502a (A-B) = +<NUM>, differential receiver 502b (B-C) = -<NUM> and differential receiver 502c (C-A) = -<NUM>. Transition decisions taken by phase change detect circuits in a receiver are based on <NUM> possible levels produced by the differential receivers 502a, 502b, 502c, which include -<NUM>, -<NUM>, <NUM>, +<NUM> and +<NUM> voltage states.

The transitions in the state diagram <NUM> can be represented by a Flip, Rotate, Polarity symbol (e.g., the FRP symbol <NUM>) that has one of the three-bit binary values in the set: {<NUM>, <NUM>, <NUM>, <NUM>, <NUM>}. The Rotation bit <NUM> of the FRP symbol <NUM> indicates the direction of phase rotation associated with a transition to a next state. The Polarity bit <NUM> of the FRP symbol <NUM> is set to binary <NUM> when a transition to a next state involves a change in polarity. When the Flip bit <NUM> of the FRP symbol <NUM> is set to binary <NUM>, the Rotate and Polarity values may be ignored and/or zeroed. A flip represents a state transition that involves only a change in polarity. Accordingly, the phase of a <NUM>-phase signal is not considered to be rotating when a flip occurs, and the polarity bit is redundant when a flip occurs. The FRP symbol <NUM> corresponds to wire state changes for each transition. The state diagram <NUM> may be separated into an inner circle <NUM> that includes the positive polarity signaling states <NUM>, <NUM>, <NUM> and an outer circle <NUM> that encompasses the negative polarity signaling states <NUM>, <NUM>, <NUM>.

<FIG> illustrates an example of wire state encoding <NUM> that may be used in certain C-PHY interfaces. A symbol encoder <NUM> receives a stream of FRP symbols <NUM> that may have the format of the FRP symbol <NUM> illustrated in <FIG>. A mapper <NUM> (see <FIG>) may generate the stream of FRP symbols <NUM> from data to be communicated over a C-PHY bus. The symbol encoder <NUM> provides a current transmit symbol <NUM> for each FRP symbol in the stream of FRP symbols <NUM> based on the immediately preceding transmit symbol <NUM>. The immediately preceding transmit symbol <NUM> is maintained by flipflops or a register <NUM> configured to capture the current transmit symbol <NUM> based on timing provided by a symbol clock signal <NUM>. The symbol clock signal <NUM> also provides timing for pre-drive and control circuit <NUM>, which controls the operation of line drivers coupled to the C-PHY bus. In some instances, the pre-drive and control circuit <NUM> may capture and hold the current transmit symbol <NUM> for the duration of a cycle of the symbol clock signal <NUM>. In some instances, the pre-drive and control circuit <NUM> may provide a set of signals <NUM> that control pull-up and pull-down sections of the line driver circuit. The table <NUM> illustrates the state of the set of signals <NUM> that produce the voltage levels <NUM> for each wire state <NUM> defined for the C-PHY bus.

<FIG> illustrates an example of wire state decoding <NUM> that may be used in certain C-PHY interfaces. A set of comparators <NUM> monitors signaling state <NUM> of the C-PHY bus and produces difference signals that are captured as current wire state <NUM> by first flipflops or registers <NUM> based on timing provided by a symbol clock signal <NUM>. A clock recovery circuit <NUM> monitors signaling state <NUM> of the C-PHY bus and produces a receive clock signal <NUM> that may be gated by gating logic <NUM> to produce the symbol clock signal <NUM>. The gating logic <NUM> may receive an enable signal <NUM> from clock window logic <NUM> and the gating logic <NUM> provides the symbol clock signal <NUM> when a settle signal <NUM> indicates that the receive clock signal <NUM> is valid. Second flipflops or registers <NUM> provide the previous wire state <NUM> by capturing the current wire state <NUM> based on timing provided by the symbol clock signal <NUM>.

A symbol decoder <NUM> produces a stream of FRP symbols <NUM> that may have the format of the FRP symbol <NUM> illustrated in <FIG>. The stream of FRP symbols <NUM> may be provided to a demapper <NUM> (see <FIG>) that decodes data from the stream of FRP symbols <NUM>. The symbol decoder <NUM> produces each FRP symbol in the stream of FRP symbols <NUM> based on differences between previous wire state <NUM> and current wire state <NUM>.

Increasing complexity and performance of application and sensors has produced corresponding increased demands for data rates and throughput. For example, increased resolution of imaging devices and imaging device can be expected to produce ever-increasing volumes of image data to be communicated over a C-PHY bus between application processors and other devices. Demand for higher frame rates and the provision of multiple imaging devices in an apparatus also multiply the volumes of image data to be transmitted and can reduce the time available to transmit the image data. Display systems are being concurrently provided with increased resolution and may be required to handle increased frame rates. The increased demand for throughput can be difficult to meet using a conventional C-PHY interface.

The C-PHY data path operates at full rate clock, whereby data is transmitted and sampled on a single type of edge of the transmitter's symbol clock signal or receiver's symbol clock signal respectively. The type of edge used for timing in a symbol clock signal may be the rising edge or the falling edge, based on the circuit design employed in an implementation. Data throughput is determined by the symbol rate of the C-PHY interface, where symbol rate may be expressed as the number of symbols transmitted per second over the C-PHY bus. According to conventional C-PHY specifications:
Symbol rate = Symbol clock frequency.

Data throughput may be measured as the number of bits per second transmitted over the C-PHY bus. In one example, approximately <NUM> bits can be encoded in the transitions between consecutively-transmitted symbols, such that
Data throughput = <NUM>*(Symbol clock frequency).

Increased data throughput can be obtained by increasing the symbol clock frequency. The ability to increase symbol clock frequency is limited by the performance of circuits in C-PHY transmitters and receivers. In many implementations, switching time defined for logic gates may limit the maximum symbol clock frequency, and/or may limit the number of levels of gates in circuits that operate at symbol clock frequency. In one example, differences in propagation time through logic circuits of a receiver can limit the time interval in which a symbol can be reliably sampled. In another example, generation and distribution of a high-speed full-rate symbol clock signal may be difficult to accomplish and may complicate integrated circuit design.

A C-PHY interface implemented in accordance with certain aspects of this disclosure can increase data throughput for a C-PHY interface without increasing the symbol clock rate. In one aspect, timing in a C-PHY data path may controlled by a half-rate symbol clock signal. Symbols can be transmitted on both rising and falling edges of the symbol clock signal when a half-rate symbol clock signal is used, relaxing the frequency requirement for the symbol clock signal at higher symbol rates. The use of a half-rate symbol clock signal in accordance with certain aspects of this disclosure provides that:
Symbol rate = <NUM>*(Symbol clock frequency).

Data throughput is measured as the number of bits per second transmitted over the C-PHY bus. When <NUM> bits are encoded in the transitions between consecutively-transmitted symbols:
Data throughput = <NUM>*(Symbol clock frequency).

In one example, the data throughput obtained using a <NUM> symbol clock signal in a conventional C-PHY interface can be obtained using a <NUM> symbol clock signal in a C-PHY interface implemented in accordance with certain aspects of this disclosure.

Certain aspects of this disclosure relate to the structure and configuration of C-PHY transmitters and receivers that can operate using half-rate symbol clock signals. In various examples, the C-PHY transmitters and receivers are configured for a dual path architecture, each path encoding or decoding alternate symbols in a sequence of symbols. For the purposes of this description, the paths in a transmitter or receiver configured for use with a half-rate symbol clock are designated as odd and even paths. In one example, the odd path in a transmitter or receiver handles the symbols in a sequence that are transmitted first, third, fifth symbols and so on, and the even path in a transmitter or receiver handles the symbols in a sequence that are transmitted second, fourth, sixth symbols and so on. In operation, the paths are symmetric in structure, and symbols or paths may be arbitrarily designated as odd and even. According to one aspect, a C-PHY transmitter that is implemented with a dual path architecture includes a mapper that provides odd and even symbols to corresponding odd and even paths. According to one aspect, a C-PHY receiver that is implemented with a dual path architecture includes a demapper that receives odd and even symbols from corresponding odd and even paths and interleaves the odd and even symbols to provide a sequence of symbols for decoding.

<FIG> illustrates examples of mapping circuits <NUM>, <NUM> that may be implemented in C-PHY transmitters configured with a dual path architecture in accordance aspects of the disclosure. The first mapping circuit <NUM> includes two mappers <NUM>, <NUM>, each mapper <NUM>, <NUM> feeding one of the paths in a transmitter, where the transmitter is implemented with an even symbol path and an odd symbol path. Each even symbol defines a signaling state that is immediately followed by a signaling state defined by an odd symbol and each odd symbol defines a signaling state that is immediately followed by a signaling state defined by an even symbol.

The first mapping circuit <NUM> may receive input data <NUM> as two <NUM>-bit words or as a single <NUM>-bit word. The first mapping circuit <NUM> splits <NUM>-bit words into two <NUM>-bit words. Each <NUM>-bit word can be mapped into a sequence of <NUM> FRP symbols by respective mappers <NUM>, <NUM>. Each <NUM>-bit representation of the sequence of <NUM> FRP symbols may be serialized to obtain a timed sequence of FRP symbols using respective serializers <NUM>, <NUM>. The serializers <NUM>, <NUM> provide one symbol per clock cycle of a half-rate symbol clock signal <NUM>, which has a frequency equal to half the desired symbol transmission rate. In the illustrated example, two mappers <NUM>, <NUM> provide a sequence of seven <NUM>-bit FRP symbols to corresponding serializers <NUM>, <NUM>.

Timing of the mappers <NUM>, <NUM> is controlled by a word clock signal <NUM> provided by a circuit <NUM> that divides the half-rate symbol clock signal <NUM> by seven. Input timing of the serializers <NUM>, <NUM> is controlled by the word clock signal <NUM> and output timing of the serializers <NUM>, <NUM> is controlled by the half-rate symbol clock signal <NUM>.

In one example, the first mapping circuit <NUM> provides FRP symbols to the even symbol path <NUM> that encode a <NUM>-bit word that is different from the <NUM>-bit word encoded in FRP symbols provided to the odd symbol path <NUM>. For example, FRP symbol N is provided to the even symbol path <NUM> and symbol N+<NUM> is provided to the odd symbol path <NUM>, where symbol N+<NUM> follows symbol N in transmission. The sequences obtained from the two mappers <NUM>, <NUM> may be provided in turn to the even and odd symbol paths <NUM>, <NUM>, effectively combining the two sequences of <NUM> FRP symbols into a <NUM>-symbol sequence.

In another example, each of the two mappers <NUM>, <NUM> may be configured as an even mapper <NUM> and an odd mapper <NUM>, both mappers <NUM>, <NUM> being configured to receive the same <NUM>-bit word. In this example, the even mapper <NUM> provides the even symbols in the <NUM>-symbol sequence that represents the <NUM>-bit word, while the odd mapper <NUM> provides the odd symbols in the <NUM>-symbol sequence that represents the <NUM>-bit word. Symbols produced by the mappers <NUM>, <NUM> can be serialized and provided to the corresponding symbol path. <NUM>, <NUM>. In this example, signaling on the serial bus is consistent with conventional C-PHY transmitters.

The second mapping circuit <NUM> uses a single mapper <NUM> and is configured to receive data in <NUM>-bit words. The single mapper <NUM> is configured to encode each <NUM>-bit word in a sequence of <NUM> FRP symbols. The sequence of <NUM> FRP symbols may be loaded into a <NUM>-to-<NUM> shift register <NUM> using a demultiplexer <NUM> that provides the even and odd symbols to shift registers coupled to the corresponding even and odd symbol paths <NUM>, <NUM>. The demultiplexer <NUM> is clocked at half the input data clock rate, using a clock signal <NUM> derived from the symbol clock signal <NUM> through the operation of a divider <NUM>.

<FIG> illustrates a first example of a transmitter <NUM> configured to use a half-rate symbol clock signal <NUM> to encode input data <NUM> in symbols that control signaling state of a C-PHY trio <NUM>. The transmitter <NUM> is implemented with an even symbol path and an odd symbol path, where each even symbol defines a signaling state that is immediately followed by a signaling state defined by an odd symbol and each odd symbol defines a signaling state that is immediately followed by a signaling state defined by an even symbol. In some implementations, the resultant sequence of symbols complies with C-PHY protocols. <FIG> illustrates timing <NUM> for the transmitter <NUM>.

The input data <NUM> may be received by a mapping circuit <NUM> as two <NUM>-bit words or as a single <NUM>-bit word. The mapping circuit <NUM> may correspond to one of the mapping circuits <NUM>, <NUM> illustrated in <FIG>, for example. Each symbol in the sequence of FRP symbols provided by the mapping circuit <NUM> is captured by one of the flipflops <NUM> and <NUM> that maintain the next FRP symbols <NUM>, <NUM> to be encoded for transmission. For each cycle of the half-rate symbol clock signal <NUM>, the flipflop <NUM> in the even symbol path provides the input to a first wire state encoder <NUM>, and the flipflop <NUM> in the odd symbol path provides the input to a second wire state encoder <NUM>.

The first wire state encoder <NUM> provides, as its output, a next even <NUM>-bit wire state symbol <NUM> to define signaling state of each wire of the C-PHY trio <NUM>. The next even <NUM>-bit wire state symbol <NUM> is generated based on differences between the even <NUM>-bit symbol <NUM> and the current odd <NUM>-bit wire state symbol <NUM> generated on the odd symbol path. A flipflop <NUM> clocked by an inverse of the half-rate symbol clock signal <NUM> provides the current even <NUM>-bit wire state symbol <NUM> by capturing the next even <NUM>-bit wire state symbol <NUM> when it is clocked through flipflop <NUM> in order to be transmitted.

The second wire state encoder <NUM> provides, as its output, a next odd <NUM>-bit wire state symbol <NUM> to define signaling state of each wire of the C-PHY trio <NUM>. The next odd <NUM>-bit wire state symbol <NUM> is generated based on differences between the odd <NUM>-bit symbol <NUM> and the current even <NUM>-bit wire state symbol <NUM> generated on the even symbol path. A flipflop <NUM> clocked by the half-rate symbol clock signal <NUM> provides the current odd <NUM>-bit wire state symbol <NUM> by capturing the next odd <NUM>-bit wire state symbol <NUM> when it is clocked through flipflop <NUM> in order to be transmitted.

A multiplexer <NUM> selects its output <NUM> from the current even <NUM>-bit wire state symbol <NUM> and the current odd <NUM>-bit wire state symbol <NUM>. The output <NUM> of the multiplexer <NUM> is provided to a pre-drive and control circuit <NUM> that controls a set of line drivers <NUM> coupled to the C-PHY trio <NUM>. The multiplexer <NUM> is controlled by the half-rate symbol clock signal <NUM>, such that even and odd symbols control the state of the <NUM> in different phases (half-cycles) of the half-rate symbol clock signal <NUM>.

<FIG> illustrates a second example of a transmitter <NUM> configured to use a half-rate symbol clock signal <NUM> to encode input data <NUM> in symbols that control signaling state of a C-PHY trio <NUM>. The transmitter <NUM> operates in a similar fashion to the transmitter <NUM> of <FIG> with added pipeline circuits <NUM>, <NUM> that support equalization.

The transmitter <NUM> is implemented with an even symbol path and an odd symbol path, where each even symbol defines a signaling state that is immediately followed by a signaling state defined by an odd symbol and each odd symbol defines a signaling state that is immediately followed by a signaling state defined by an even symbol. The resultant sequence of symbols complies with C-PHY protocols.

The input data <NUM> may be received by a mapping circuit <NUM> as two <NUM>-bit words or as a single <NUM>-bit word. The mapping circuit <NUM> may correspond to one of the mapping circuits <NUM>, <NUM> illustrated in <FIG>, for example. Each symbol in the sequence of FRP symbols provided by the mapping circuit <NUM> is captured by one of the flipflops <NUM> and <NUM> that maintain the next FRP symbols for processing. For each cycle of the half-rate symbol clock signal <NUM>, the flipflop <NUM> in the even symbol path provides the input to a first wire state encoder <NUM>, and the flipflop <NUM> in the odd symbol path provides the input to a second wire state encoder <NUM>.

The first wire state encoder <NUM> provides, as its output, a next even <NUM>-bit wire state symbol to define signaling state of each wire of the C-PHY trio <NUM>. The next even <NUM>-bit wire state symbol is generated based on differences between the next even FRP symbol and the current odd <NUM>-bit wire state symbol <NUM> generated on the odd symbol path. A flipflop <NUM> clocked by an inverse of the half-rate symbol clock signal <NUM> provides the current even <NUM>-bit wire state symbol <NUM> by capturing the next even <NUM>-bit wire state symbol provided by the first wire state encoder <NUM> when it is clocked through flipflop <NUM> in order to be transmitted.

The second wire state encoder <NUM> provides, as its output, a next odd <NUM>-bit wire state symbol to define signaling state of each wire of the C-PHY trio <NUM>. The next odd <NUM>-bit wire state symbol is generated based on differences between the next odd FRP symbol and the current even <NUM>-bit wire state symbol <NUM> generated on the even symbol path. A flipflop <NUM> clocked by the half-rate symbol clock signal <NUM> provides the current odd <NUM>-bit wire state symbol <NUM> by capturing the next odd <NUM>-bit wire state symbol provided by the second wire state encoder <NUM> when it is clocked through flipflop <NUM> in order to be transmitted.

In the illustrated example, the current even <NUM>-bit wire state symbol <NUM> and the current odd <NUM>-bit wire state symbol <NUM> are provided to respective even and odd pre-drive and control circuits <NUM>, <NUM> that produce one or more driver control signals <NUM>, <NUM> configured to control a set of line drivers <NUM> coupled to the C-PHY trio <NUM>. The driver control signals <NUM>, <NUM> are provided to respective pipeline circuits <NUM>, <NUM> that provide a delay sufficient to enable equalization circuits <NUM>, <NUM> to determine an equalization configuration for the driver control signals <NUM>, <NUM>. In the illustrated example, the pipeline circuits <NUM>, <NUM> include two or more flipflops that delay the driver control signals <NUM>, <NUM> by a corresponding two or more clock cycles. The flipflops in the pipeline circuit <NUM> for the even symbol path are clocked by the inverse of the half-rate symbol clock signal <NUM> and the flipflops in the pipeline circuit <NUM> for the odd symbol path are clocked by the half-rate symbol clock signal <NUM> to maintain the timing relationship established between the even and odd symbol paths. The delayed driver control signals are provided by respective pipeline circuits <NUM>, <NUM> to equalizer circuits <NUM>, <NUM> that may apply a timing adjustment to certain of the delayed driver control signals, generate driver amplitude control signals for certain of the delayed driver control signals, or provide some combination of timing and amplitude adjustments. The equalizer circuits <NUM>, <NUM> provide the delayed driver control signals and/or timing and amplitude adjustment control signals to the multiplexer <NUM>.

The multiplexer <NUM> selects between the outputs of the equalizer circuits <NUM>, <NUM> to provide its output. The output of the multiplexer <NUM> is provided to the set of line drivers <NUM> coupled to the C-PHY trio <NUM>. The multiplexer <NUM> is controlled by the half-rate symbol clock signal <NUM>, such that even and odd symbols control the state of the C-PHY trio <NUM> in different phases (half-cycles) of the half-rate symbol clock signal <NUM>.

A receiver configured to decode sequences of symbols transmitted in accordance with timing provided by a half-rate symbol clock signal may be configured with separate even and odd symbol paths. Difference signal processors may be employed to demultiplex the difference signals to obtain current and previous wire states.

<FIG> illustrates one example of difference signal processors <NUM>, <NUM> and <NUM> that may be used in a receiver configured for half-rate symbol clock operation in accordance with certain aspects of this disclosure.

An AB difference signal processor <NUM> receives the AB difference signal <NUM> from a comparator or line receiver circuit. The AB difference signal <NUM> may be received from one of a set of comparators such as the set of comparators <NUM> illustrated in <FIG>. The comparators provide a set of difference signals {AB, BC, CA} representing the difference in signaling state of the trio of wires (referenced as wires A, B and C) in a C-PHY bus. In some implementations, the AB difference signal <NUM> is a multi-bit signal and/or may be transmitted over two or more connectors or wires. <FIG> is a timing diagram <NUM> that includes a snapshot of the AB difference signal <NUM>, covering the signaling state for received symbol intervals {N, N+<NUM>,. The AB difference signal processor <NUM> includes a first flipflop <NUM> that is clocked by the half-rate symbol clock signal <NUM> and configured to capture even AB state <NUM>, including AB state for each of the set of symbols {N-<NUM>, N+<NUM>, N+<NUM>, N+<NUM> and N+<NUM>}.

The AB difference signal processor <NUM> includes a second flipflop <NUM> that is clocked by an inverse of the half-rate symbol clock signal <NUM> and configured to capture odd AB states <NUM>, including state for each of the set of symbols {N, N+<NUM>, N+<NUM> and N+<NUM>}. The AB difference signal processor <NUM> also includes third and fourth flipflops <NUM>, <NUM> that are clocked by the half-rate symbol clock signal <NUM> and that provide aligned current even AB states <NUM> and current odd AB states <NUM>. The AB difference signal processor <NUM> also includes a fifth flipflop <NUM> that is clocked by the half-rate symbol clock signal <NUM> and that captures current odd AB states <NUM> to provide previous odd AB states <NUM> aligned in time with corresponding current even AB states <NUM> and current odd AB states <NUM>.

A BC difference signal processor <NUM> receives the BC difference signal <NUM> from a comparator or line receiver circuit. The BC difference signal <NUM> may be received from one of a set of comparators such as the set of comparators <NUM> illustrated in <FIG>. In some implementations, the BC difference signal <NUM> is a multi-bit signal and/or may be transmitted over two or more connectors or wires. The BC difference signal processor <NUM> includes a first flipflop <NUM> that is clocked by the half-rate symbol clock signal <NUM> and configured to capture even BC state <NUM>, including BC state for each of the set of symbols {N-<NUM>, N+<NUM>, N+<NUM>, N+<NUM> and N+<NUM>}.

The BC difference signal processor <NUM> includes a second flipflop <NUM> that is clocked by an inverse of the half-rate symbol clock signal <NUM> and configured to capture odd BC states <NUM>, including state for each of the set of symbols {N, N+<NUM>, N+<NUM> and N+<NUM>}. The BC difference signal processor <NUM> also includes third and fourth flipflops <NUM>, <NUM> that are clocked by the half-rate symbol clock signal <NUM> and that provide aligned current even BC states <NUM> and current odd BC states <NUM>. The BC difference signal processor <NUM> also includes a fifth flipflop <NUM> that is clocked by the half-rate symbol clock signal <NUM> and that captures current odd BC states <NUM> to provide previous odd BC states <NUM> aligned in time with corresponding current even BC states <NUM> and current odd BC states <NUM>.

A CA difference signal processor <NUM> receives the CA difference signal <NUM> from a comparator or line receiver circuit. The CA difference signal <NUM> may be received from one of a set of comparators such as the set of comparators <NUM> illustrated in <FIG>. In some implementations, the CA difference signal <NUM> is a multi-bit signal and/or may be transmitted over two or more connectors or wires. The CA difference signal processor <NUM> includes a first flipflop <NUM> that is clocked by the half-rate symbol clock signal <NUM> and configured to capture even CA state <NUM>, including CA state for each of the set of symbols {N-<NUM>, N+<NUM>, N+<NUM>, N+<NUM> and N+<NUM>}.

The CA difference signal processor <NUM> includes a second flipflop <NUM> that is clocked by an inverse of the half-rate symbol clock signal <NUM> and configured to capture odd CA states <NUM>, including state for each of the set of symbols {N, N+<NUM>, N+<NUM> and N+<NUM>}. The CA difference signal processor <NUM> also includes third and fourth flipflops <NUM>, <NUM> that are clocked by the half-rate symbol clock signal <NUM> and that provide aligned current even CA states <NUM> and current odd CA states <NUM>. The CA difference signal processor <NUM> also includes a fifth flipflop <NUM> that is clocked by the half-rate symbol clock signal <NUM> and that captures current odd CA states <NUM> to provide previous odd CA states <NUM> aligned in time with corresponding current even CA states <NUM> and current odd CA states <NUM>.

<FIG> illustrates a receiver circuit <NUM> configured to use a half-rate symbol clock signal <NUM> to decode data <NUM> from signaling state of a C-PHY bus. The receiver circuit <NUM> is implemented with an even symbol path and an odd symbol path, where each symbol corresponds to data encoded in transitions between successive signaling states. Each even symbol represents a first signaling state that is immediately followed by a second signaling state represented by an odd symbol and each odd symbol represents a third signaling state that is immediately followed by a fourth signaling state represented by an even symbol. The sequence of symbols complies with C-PHY protocols. <FIG> illustrates timing associated with the receiver circuit <NUM>.

The receiver circuit <NUM> may include or may be coupled to comparators such as the set of comparators <NUM> illustrated in <FIG>. The comparators provide a set of difference signals {AB, BC, CA} representing the difference in signaling state of the trio of wires (referenced as wires A, B and C) in a C-PHY bus. Three difference signal processors <NUM>, <NUM>, <NUM> are provided to extract information from signaling states in a sequence of symbol transmission intervals on the C-PHY bus. The symbol transmission interval is defined by the symbol transmission rate. The set of difference signals is also provided to a clock recovery circuit <NUM> that generates the half-rate symbol clock signal <NUM>. Each period of the half-rate symbol clock signal <NUM> defines two symbol transmission intervals.

The AB difference signal processor <NUM> provides the current even AB states, the current odd AB states and the previous odd AB states to a pair of wire state decoders. The BC difference signal processor <NUM> provides the current even BC states, the current odd BC states and the previous odd BC states to a pair of wire state decoders. The CA difference signal processor <NUM> provides the current even CA states, the current odd CA states and the previous odd CA states to a pair of wire state decoders.

An even wire state decoder <NUM> provides <NUM>-bit even FRP symbols <NUM> by determining differences between the current odd states <NUM> for the AB, BC and CA difference signals and the current even states <NUM> for the AB, BC and CA difference signals. The current even states <NUM> for the AB, BC and CA difference signals occur before the current odd states <NUM> for the AB, BC and CA. An odd wire state decoder <NUM> provides <NUM>-bit odd FRP symbols <NUM> by determining differences between the current even states <NUM> for the AB, BC and CA difference signals and the previous odd states <NUM> for the AB, BC and CA difference signals. The previous odd states <NUM> for the AB, BC and CA difference signals occur before the current even states <NUM> for the AB, BC and CA.

The even FRP symbols <NUM> and the odd FRP symbols <NUM> are held in corresponding registers or flipflops <NUM> and <NUM> respectively to provide even FRP input <NUM> and odd FRP input <NUM> to <NUM>-to-<NUM> serial-to-parallel converters <NUM>, <NUM>. The registers or flipflops <NUM> and <NUM> and the inputs of the serial-to-parallel converters <NUM>, <NUM> are clocked by the half-rate symbol clock signal <NUM>. The serial-to-parallel converters <NUM>, <NUM> provide <NUM>-bit representations of sequences of symbols as even and odd inputs <NUM> to a demapper <NUM> based on timing provided by a data clock signal <NUM> provided by a circuit <NUM> that divides the half-rate symbol clock signal <NUM> by seven. The demapper <NUM> interleaves and decodes the even and odd inputs <NUM> to obtain decoded data <NUM>, which may be output in <NUM>-bit or <NUM>-bit words. The serial-to-parallel converters <NUM>, <NUM> and the demapper <NUM> may operate based on timing provided by the data clock signal <NUM>.

<FIG> illustrates examples of demapping circuits <NUM>, <NUM> that may be implemented in C-PHY receivers that are configured with a dual path architecture in accordance aspects of the disclosure. The first demapping circuit <NUM> includes two demappers <NUM>, <NUM>. A first deserializer <NUM>, or serial to parallel convertor, provides the first demapper <NUM> with a <NUM>-bit representation of each sequence of seven <NUM>-bit symbols received from the even symbol path <NUM>. A second deserializer <NUM> provides the second demapper <NUM> with a <NUM>-bit representation of each sequence of seven <NUM>-bit symbols received from the odd symbol path <NUM>. The symbols received from the even symbol path <NUM> and the odd symbol path <NUM> may be configured as FRP symbols. The demappers <NUM>, <NUM> may be configured to convert the <NUM>-symbol sequences into data in accordance with C-PHY encoding. In some implementations, each of the demappers <NUM>, <NUM> may decode a sequence of seven symbols by indexing a lookup table using the <NUM>-bit representation of the sequence of seven symbols. In one example, the first demapping circuit <NUM> may provide output data <NUM> as two <NUM>-bit words. In another example, the first demapping circuit <NUM> may provide output data <NUM> as two <NUM>-bit words. or as a single <NUM>-bit word.

The deserializers <NUM>, <NUM> receive one symbol per clock cycle of a half-rate symbol clock signal <NUM>, which has a frequency equal to half the desired symbol transmission rate. In the illustrated example, each of the two demappers <NUM>, <NUM> receive a set of seven <NUM>-bit FRP symbols from corresponding deserializers <NUM>, <NUM>. Timing of the operation of the demappers <NUM>, <NUM> and the output of the deserializers <NUM>, <NUM> is controlled by a word clock signal <NUM> provided by a circuit <NUM> that divides the half-rate symbol clock signal <NUM> by seven. In the illustrated example, FRP symbol N is received from the even symbol path <NUM> and symbol N+<NUM> is received from the odd symbol path <NUM>, where symbol N+<NUM> is received from the C-PHY bus after symbol N.

In some implementations, each of the two demappers <NUM>, <NUM> may be configured as an even demapper <NUM> and an odd demapper <NUM>, both demappers <NUM>, <NUM> being configured to output parts of the same <NUM>-bit word. In some implementations, signaling on the serial bus is consistent with conventional C-PHY transmitters.

The second demapping circuit <NUM> uses a single demapper <NUM> and is configured to interleave symbols received from the even symbol path <NUM> and the odd symbol path <NUM>. In one example, the sequences of <NUM> FRP symbols are captured from deserializers <NUM>, <NUM> by sets of flipflops <NUM>, <NUM>, where the sets of flipflops <NUM>, <NUM> and the outputs of the deserializers <NUM>, <NUM> are controlled by a word clock signal <NUM>, which may be obtained from a divider <NUM> that divides the half-rate symbol clock signal <NUM> by <NUM>. In one example, the deserializers <NUM>, <NUM> are configured to assemble up to <NUM> received symbols into a sequence of symbols captured by respective sets of flipflops <NUM>, <NUM>. A first set of flipflops <NUM> captures <NUM>-symbol sequences from the even symbol path <NUM> and a second set of flipflops <NUM> captures <NUM>-symbol sequences from the odd symbol path <NUM>. A multiplexer <NUM> feeds the demapper <NUM> in accordance with a select signal provided by a half-word clock signal <NUM>, which may be obtained from a divider <NUM> that divides the half-rate symbol clock signal <NUM> by <NUM>. The demapper <NUM> produces two <NUM>-bit data words at an output <NUM> of the second demapping circuit <NUM> for every cycle of the half-rate symbol clock signal <NUM>. In one example, a first <NUM>-bit data word is decoded from a <NUM>-symbol sequence processed through the even symbol path <NUM> and a second <NUM>-bit data word is decoded from a <NUM>-symbol sequence processed through the odd symbol path <NUM>.

<FIG> is a conceptual diagram <NUM> illustrating an example of a hardware implementation for an apparatus employing a processing circuit <NUM> that may be configured to perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using the processing circuit <NUM>. The processing circuit <NUM> may include certain devices, circuits, and/or logic that support the various encoding schemes disclosed herein. In one example, the processing circuit <NUM> may include some combination of circuitry and modules that facilitates the encoding of data into symbols, and line drivers that are adapted to assert three or more voltage levels on the wires of a serial bus. In another example, the processing circuit <NUM> may include some combination of circuitry and modules that facilitates the encoding of data into symbols using <NUM>-phase encoders, mappers, drivers and/or equalizers. The processing circuit <NUM> may include a state machine or another type of processing device that manages encoding and/or decoding processes as disclosed herein.

The processing circuit <NUM> may include one or more processors <NUM> that are controlled by some combination of hardware and software modules. Examples of processors <NUM> include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors <NUM> may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules <NUM>. The one or more processors <NUM> may be configured through a combination of software modules <NUM> loaded during initialization, and further configured by loading or unloading one or more software modules <NUM> during operation.

In the illustrated example, the processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including the one or more processors <NUM>, and a processor-readable storage medium <NUM>. The processor-readable storage medium <NUM> may include memory devices and mass storage devices and may be referred to herein as computer-readable media and/or processor-readable media. The bus <NUM> may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface <NUM> may provide an interface between the bus <NUM> and one or more transceivers <NUM>. A transceiver <NUM> may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver <NUM>. Each transceiver <NUM> provides a means for communicating with various other apparatus over a transmission medium. Depending upon the nature of the apparatus, a user interface <NUM> (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus <NUM> directly or through the bus interface <NUM>.

A processor <NUM> may be responsible for managing the bus <NUM> and for general processing that may include the execution of software stored in a processor-readable medium that may include the processor-readable storage medium <NUM>. The processor-readable storage medium <NUM> may be used for storing data that is manipulated by the processor <NUM> when executing software, and the software may be configured to implement any one of the methods disclosed herein.

One or more processors <NUM> in the processing circuit <NUM> may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the processor-readable storage medium <NUM> or in another, external processor-readable medium. The processor-readable storage medium <NUM> may include a non-transitory processor-readable medium. A non-transitory processor-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a "flash drive," a card, a stick, or a key drive), a random access memory (RAM), a ROM, a PROM, an erasable PROM (EPROM), an EEPROM, a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The processor-readable storage medium <NUM> may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Processor-readable storage medium <NUM> may reside in the processing circuit <NUM>, in the processor <NUM>, external to the processing circuit <NUM>, or be distributed across multiple entities including the processing circuit <NUM>. The processor-readable storage medium <NUM> may be embodied in a computer program product. By way of example, a computer program product may include a processor-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The processor-readable storage medium <NUM> may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules <NUM>. Each of the software modules <NUM> may include instructions and data that, when installed or loaded on the processing circuit <NUM> and executed by the one or more processors <NUM>, contribute to a run-time image <NUM> that controls the operation of the one or more processors <NUM>. When executed, certain instructions may cause the processing circuit <NUM> to perform functions in accordance with certain methods, algorithms and processes described herein.

Some of the software modules <NUM> may be loaded during initialization of the processing circuit <NUM>, and these software modules <NUM> may configure the processing circuit <NUM> to enable performance of the various functions disclosed herein. For example, some software modules <NUM> may configure internal devices and/or logic circuits <NUM> of the processor <NUM> and may manage access to external devices such as the transceiver <NUM>, the bus interface <NUM>, the user interface <NUM>, timers, mathematical coprocessors, and so on. The software modules <NUM> may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit <NUM>. The resources may include memory, processing time, access to the transceiver <NUM>, the user interface <NUM>, and so on.

<FIG> is a flow chart <NUM> of a data communication method that may be performed at a transmitter coupled to a multi-wire communication link. In one example, the communication link may have three wires and data may be encoded in phase state and amplitude of a signal transmitted in different phases on each of the three wires. The method may be performed, at least in part, at the transmitter <NUM> or <NUM> illustrated in <FIG> and <FIG> respectively.

At block <NUM>, the transmitter <NUM> or <NUM> may configure a plurality of line drivers to couple the apparatus to a <NUM>-wire link. At block <NUM>, the transmitter <NUM> or <NUM> may receive a first symbol in a sequence of symbols at a first wire state encoder when the <NUM>-wire link is in a first signaling state. At block <NUM>, the transmitter <NUM> or <NUM> may define a second signaling state for the <NUM>-wire link based on the first symbol and the first signaling state. At block <NUM>, the transmitter <NUM> or <NUM> may receive a second symbol in the sequence of symbols at a second wire state encoder. At block <NUM>, the transmitter <NUM> or <NUM> may define a third signaling state for the <NUM>-wire link based on the second symbol and the second signaling state. The first symbol may immediately precede the second symbol in the sequence of symbols. The <NUM>-wire link transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals. Signaling states of at least one wire in the <NUM>-wire link changes when the <NUM>-wire link transitions from the second signaling state to the third signaling state.

In one example, each of the first wire state encoder and the second wire state encoder defines signaling states for the <NUM>-wire link every two symbol transmission intervals.

In certain examples, a half-rate symbol clock signal that has a period twice the duration of each symbol transmission interval may be provided. The transmitter <NUM> or <NUM> may select between the second signaling state and the third signaling state to provide wire state information to a driver control circuit that controls the plurality of line drivers. Selection may be based on phase of the half-rate symbol clock signal. The transmitter <NUM> or <NUM> may clock first flipflops clocked using an inverse of the half-rate symbol clock signal. The first flipflops may be configured to capture first control signals representative of the second signaling state. The transmitter <NUM> or <NUM> may clock second flipflops using the half-rate symbol clock signal. The second flipflops may be configured to capture second control signals representative of the third signaling state. The transmitter <NUM> or <NUM> may provide the first control signals or the second control signals as the wire state information. The transmitter <NUM> or <NUM> may map at least <NUM> bits of data to at least <NUM> symbols in the sequence of symbols. The <NUM>-wire link may be operated in accordance with a C-PHY protocol.

In some implementations, the transmitter <NUM> or <NUM> may configure the plurality of line drivers when initiating transmission of the third signaling state based on differences between the second signaling state and the third signaling state.

<FIG> is a diagram illustrating an example of a hardware implementation for an apparatus <NUM> employing a processing circuit <NUM>. The processing circuit <NUM> typically has a processor <NUM>, which may be a microprocessor, microcontroller, digital signal processor, a sequencer or a state machine. The processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including one or more processors and/or hardware modules, represented by the processor <NUM>, the modules or circuits <NUM>, <NUM> and <NUM>, line drivers <NUM> that are configured to drive the wires of a <NUM>-wire link <NUM>, and the processor-readable storage medium <NUM>. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processor <NUM> is responsible for general processing, including the execution of software stored on the processor-readable storage medium <NUM>. The software, when executed by the processor <NUM>, causes the processing circuit <NUM> to perform the various functions described supra for any particular apparatus. The processor-readable storage medium <NUM> may include transitory and/or non-transitory media, which may be used for storing data that is manipulated by the processor <NUM> when executing software, including symbol tables and intermediate indices used to access the symbol tables. The processing circuit <NUM> further includes at least one of the modules <NUM>, <NUM> and <NUM>. The modules <NUM>, <NUM> and <NUM> may be implemented as software modules running in the processor <NUM>, resident/stored in the processor-readable storage medium <NUM>, one or more hardware modules coupled to the processor <NUM>, or some combination thereof. The modules <NUM>, <NUM> and/or <NUM> may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, the apparatus <NUM> may be configured for data communication over a multi-wire interface. The apparatus <NUM> may include symbol mapping modules and/or circuits <NUM> configured to encode data in odd and even symbols using <NUM>-phase encoding. The apparatus <NUM> may include symbol multiplexing modules and/or circuits <NUM> configured to merge or interleave the odd and even symbols to obtain a sequence of symbols. The apparatus <NUM> may include wire state encoding modules and/or circuits <NUM> that are configured to use the sequence of symbols to cause the line drivers <NUM> to configure the signaling state of the <NUM>-wire link <NUM> during corresponding symbol transmission intervals. In one example, the line drivers <NUM> provide <NUM> or more signaling states on each wire, and each wire is driven to a different signaling state than the other wires in the <NUM>-wire link <NUM>.

In one example, the apparatus <NUM> has a pair of wire state encoders and the line drivers <NUM> are configured to couple the apparatus to the <NUM>-wire link <NUM>. A first wire state encoder is configured to receive a first symbol in a sequence of symbols when the <NUM>-wire link <NUM> is in a first signaling state, and to define a second signaling state for the <NUM>-wire link based on the first symbol and the first signaling state. The second wire state encoder is configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the <NUM>-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The <NUM>-wire link <NUM> transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals. Signaling states of at least one wire in the <NUM>-wire link <NUM> changes when the <NUM>-wire link <NUM> transitions from the second signaling state to the third signaling state. In one example, each wire state encoder defines signaling states for the <NUM>-wire link <NUM> every two symbol transmission intervals.

In some implementations, the apparatus <NUM> has a clock generation circuit configured to provide a half-rate symbol clock signal that has a period twice the duration of each symbol transmission interval. The apparatus may have a driver control circuit configured to control the line drivers <NUM>, and a multiplexer that selects between the second signaling state and the third signaling state to provide wire state information to the driver control circuit. The multiplexer may select between the second signaling state and the third signaling state based on phase of the half-rate symbol clock signal. The apparatus <NUM> may further include first flipflops clocked by an inverse of the half-rate symbol clock signal and configured to capture first control signals representative of the second signaling state, and second flipflops clocked by the half-rate symbol clock signal and configured to capture second control signals representative of the third signaling state. The multiplexer may be further configured to provide the first control signals or the second control signals as the wire state information.

In some implementations, the apparatus <NUM> has one or more mappers configured to map at least <NUM> bits of data to at least <NUM> symbols in the sequence of symbols. The <NUM>-wire link1620 may be operated in accordance with a C-PHY protocol.

In some implementations the apparatus <NUM> has an equalizer circuit configured to receive delayed versions of the second signaling state and the third signaling state, and to configure the plurality of line drivers when initiating transmission of the third signaling state based on differences between the second signaling state and the third signaling state.

The processor-readable storage medium <NUM> may store instructions and other information related to the method illustrated in <FIG>. For example, the processor-readable storage medium <NUM> may include instructions that cause the processing circuit <NUM> to configure the line drivers <NUM> to couple the apparatus to the <NUM>-wire link <NUM>, receive a first symbol in a sequence of symbols at a first wire state encoder when the <NUM>-wire link <NUM> is in a first signaling state, define a second signaling state for the <NUM>-wire link <NUM> based on the first symbol and the first signaling state, receive a second symbol in the sequence of symbols at a second wire state encoder, and define a third signaling state for the <NUM>-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The <NUM>-wire link <NUM> transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals. Signaling states of at least one wire in the <NUM>-wire link <NUM> may change when the <NUM>-wire link <NUM> transitions from the second signaling state to the third signaling state.

In some instances, each of the first wire state encoder and the second wire state encoder defines signaling states for the <NUM>-wire link <NUM> every two symbol transmission intervals.

In some implementations, the processor-readable storage medium <NUM> includes instructions that cause the processing circuit <NUM> to provide a half-rate symbol clock signal that has a period twice the duration of each symbol transmission interval. The processor-readable storage medium <NUM> may include instructions that cause the processing circuit <NUM> to select between the second signaling state and the third signaling state to provide wire state information to a driver control circuit that controls the plurality of line drivers. Selection may be based on phase of the half-rate symbol clock signal. The processor-readable storage medium <NUM> may include instructions that cause the processing circuit <NUM> to clock first flipflops clocked using an inverse of the half-rate symbol clock signal, where the first flipflops are configured to capture first control signals representative of the second signaling state. The processor-readable storage medium <NUM> may include instructions that cause the processing circuit <NUM> to clock second flipflops using the half-rate symbol clock signal, where the second flipflops are configured to capture second control signals representative of the third signaling state, and provide the first control signals or the second control signals as the wire state information.

The processor-readable storage medium <NUM> may include instructions that cause the processing circuit <NUM> to map at least <NUM> bits of data to at least <NUM> symbols in the sequence of symbols. The <NUM>-wire link <NUM> may be operated in accordance with a C-PHY protocol. The processor-readable storage medium <NUM> may include instructions that cause the processing circuit <NUM> to configure the plurality of line drivers when initiating transmission of the third signaling state based on differences between the second signaling state and the third signaling state.

<FIG> is a flow chart <NUM> of a data communication method that may be performed at a receiver coupled to a multi-wire communication link. In one example, data may be encoded in phase state and amplitude of a signal transmitted in different phases on each of the three wires in a <NUM>-wire link <NUM>. The method may be performed, at least in part, at the receiver circuit <NUM> illustrated in <FIG>.

At block <NUM>, the receiver circuit <NUM> may provide difference signals representative of differences in signaling state between each pair of wires in the <NUM>-wire link <NUM>. At block <NUM>, the receiver circuit <NUM> may provide a first symbol based on differences between state of the difference signals in a first half-cycle of a symbol clock and state of the difference signals in a second half-cycle of the symbol clock that immediately precedes the first half-cycle in the symbol clock. At block <NUM>, the receiver circuit <NUM> may provide a second symbol based on differences between the state of the difference signals in the second half-cycle of the symbol clock and state of the difference signals in a third half-cycle of the symbol clock that immediately precedes the second half-cycle in the symbol clock. At block <NUM>, the receiver circuit <NUM> may decode data from a sequence of symbols that includes the first symbol and the second symbol. The first symbol immediately precedes the second symbol in the sequence of symbols.

In various examples, the signaling state of at least one difference signal changes at each transition between half-cycles of the half-rate symbol clock. The method may include deriving the symbol clock from the difference signals. The <NUM>-wire link <NUM> is operated in accordance with a C-PHY protocol. The method may include providing, for each difference signal, a first signal representing the state of the corresponding difference signal in the first half-cycle of the symbol clock, a second signal representing the state of the corresponding difference signal in the second half-cycle of the symbol clock, and a third signal representing the state of the corresponding difference signal in the third half-cycle of the symbol clock. The method may include decoding a <NUM>-bit word from each of a plurality of sequences of seven symbols or decoding a <NUM>-bit word from each pair of sequences of seven symbols generated concurrently by the first wire state decoder and the second wire state decoder.

<FIG> is a diagram illustrating an example of a hardware implementation for an apparatus <NUM> employing a processing circuit <NUM>. The processing circuit <NUM> typically has a processor <NUM>, which may be a microprocessor, microcontroller, digital signal processor, a sequencer or a state machine. The processing circuit <NUM> may be implemented with a bus architecture, represented generally by the bus <NUM>. The bus <NUM> may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit <NUM> and the overall design constraints. The bus <NUM> links together various circuits including one or more processors and/or hardware modules, represented by the processor <NUM>, the modules or circuits <NUM>, <NUM> and <NUM>, receivers <NUM> that are configured to drive the wires of a <NUM>-wire link <NUM>, and the processor-readable storage medium <NUM>. The bus <NUM> may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

In one configuration, the apparatus <NUM> may be configured for data communication over the <NUM>-wire link <NUM>. The <NUM>-wire link may be operated in accordance with a C-PHY protocol. The apparatus <NUM> may include difference signal processing modules and/or circuits <NUM> that are configured to determine differences in signaling state between pairs of wires in the <NUM>-wire link <NUM>. In one example, the receivers <NUM> determine differences between <NUM> or more signaling states on each wire. The apparatus <NUM> may include wire state decoding modules and/or circuits <NUM> configured to produce odd and even symbols representative of difference signals in each symbol transmission interval. The apparatus <NUM> may include symbol demapping modules and/or circuits <NUM> configured to decode data from the odd and even symbols.

In one example, the receivers <NUM> are configured to provide difference signals representative of differences in signaling state between each pair of wires in the <NUM>-wire link <NUM>, and the apparatus <NUM> has a first wire state decoder configured to provide a first symbol based on differences between state of the difference signals in a first half-cycle of a symbol clock and state of the difference signals in a second half-cycle of the symbol clock that immediately precedes the first half-cycle in the symbol clock, and a second wire state decoder configured to provide a second symbol based on differences between the state of the difference signals in the second half-cycle of the symbol clock and state of the difference signals in a third half-cycle of the symbol clock that immediately precedes the second half-cycle in the symbol clock. The apparatus <NUM> may have a demapper configured to decode data from a sequence of symbols that includes the first symbol and the second symbol. The first symbol immediately precedes the second symbol in the sequence of symbols.

In some implementations, signaling state of at least one difference signal changes at each transition between half-cycles of the half-rate symbol clock. A clock recovery circuit may be configured to derive the symbol clock from the difference signals.

In one example, the apparatus <NUM> has a plurality of difference signal processors, each difference signal processor coupled to an associated difference signal and configured to provide a first signal representing the state of the corresponding difference signal in the first half-cycle of the symbol clock, a second signal representing the state of the corresponding difference signal in the second half-cycle of the symbol clock, and a third signal representing the state of the corresponding difference signal in the third half-cycle of the symbol clock.

In one example, the demapper is further configured to decode a <NUM>-bit word from each of a plurality of sequences of seven symbols, or decode a <NUM>-bit word from each pair of sequences of seven symbols generated concurrently by the first wire state decoder and the second wire state decoder.

The processor-readable storage medium <NUM> may store instructions and other information related to the method illustrated in <FIG>. For example, the processor-readable storage medium <NUM> may include instructions that cause the processing circuit <NUM> to provide difference signals representative of differences in signaling state between each pair of wires in a <NUM>-wire link <NUM>, provide a first symbol based on differences between state of the difference signals in a first half-cycle of a symbol clock and state of the difference signals in a second half-cycle of the symbol clock that immediately precedes the first half-cycle in the symbol clock, provide a second symbol based on differences between the state of the difference signals in the second half-cycle of the symbol clock and state of the difference signals in a third half-cycle of the symbol clock that immediately precedes the second half-cycle in the symbol clock, and decode data from a sequence of symbols that includes the first symbol and the second symbol. The first symbol immediately precedes the second symbol in the sequence of symbols.

In some examples, signaling state of at least one difference signal changes at each transition between half-cycles of the half-rate symbol clock. The storage medium <NUM> may include instructions that cause the processing circuit <NUM> to derive the symbol clock from the difference signals. The <NUM>-wire link <NUM> may be operated in accordance with a C-PHY protocol.

The storage medium <NUM> may include instructions that cause the processing circuit <NUM> to provide, for each difference signal, a first signal representing the state of the corresponding difference signal in the first half-cycle of the symbol clock, a second signal representing the state of the corresponding difference signal in the second half-cycle of the symbol clock, and a third signal representing the state of the corresponding difference signal in the third half-cycle of the symbol clock.

The storage medium <NUM> may include instructions that cause the processing circuit <NUM> to decode a <NUM>-bit word from each of a plurality of sequences of seven symbols, or decode a <NUM>-bit word from each pair of sequences of seven symbols generated concurrently by the first wire state decoder and the second wire state decoder.

It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

Claim 1:
A data communication apparatus, comprising:
a plurality of line drivers (<NUM>, <NUM>, <NUM>, <NUM>) configured to couple the data communication apparatus to a <NUM>-wire link (<NUM>);
a first wire state encoder (<NUM>, <NUM>) configured to receive a first symbol in a sequence of symbols when the <NUM>-wire link (<NUM>) is in a first signaling state, and to define a second signaling state for the <NUM>-wire link (<NUM>) based on the first symbol and the first signaling state; and
a second wire state encoder (<NUM>, <NUM>) configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the <NUM>-wire link (<NUM>) based on the second symbol and the second signaling state, wherein the first symbol immediately precedes the second symbol in the sequence of symbols,
wherein the <NUM>-wire link (<NUM>) transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals, and wherein signaling states of at least one wire in the <NUM>-wire link (<NUM>) changes when the <NUM>-wire link (<NUM>) transitions from the second signaling state to the third signaling state;
wherein the data communication apparatus further comprises:
one or more mappers, each mapper being configured to map <NUM> bits of data to <NUM> symbols in the sequence of symbols,
wherein the <NUM>-wire link (<NUM>) is operated in accordance with a C-PHY protocol.