Patent Description:
Aspects of the present disclosure relate generally to amplifiers, and more particularly, to sense amplifiers.

Sense amplifiers are used in a wide range of applications including memories, analog-to-digital converters, and data samplers in high-speed serializer/deserializer (SerDes). In the case of data samplers, sense amplifiers with strong regenerative feedback may be used to quickly sample and resolve incoming data bits in the data samplers.

Reference is made to <CIT>, disclosing a differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage equal to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.

The invention is set forth in the independent claims, respectively.

<FIG> shows an example of a sense amplifier <NUM> according to certain aspects of the present disclosure. The sense amplifier <NUM> includes an input stage <NUM> and a regeneration stage <NUM>.

The input stage <NUM> includes a first input transistor <NUM>, a second input transistor <NUM>, a first input-stage switch <NUM>, a second input-stage switch <NUM>, and a third input-stage switch <NUM>. The second input-stage switch <NUM> is coupled between a supply rail <NUM> and the first input transistor <NUM>, and the third input-stage switch <NUM> is coupled between the supply rail <NUM> and the second input transistor <NUM>. The first input transistor <NUM> is coupled between the second input-stage switch <NUM> and internal node <NUM>, and the second input transistor <NUM> is coupled between the third input-stage switch <NUM> and internal node <NUM>. The first input-stage switch <NUM> is coupled between internal node <NUM> and a ground rail <NUM>.

In the example in <FIG>, the first input transistor <NUM> is implemented with a first n-type field effect transistor (NFET) in which the drain of the first input transistor <NUM> is coupled to the second input-stage switch <NUM> and the source of the first input transistor <NUM> is coupled to the first input-stage switch <NUM>. The second input transistor <NUM> is implemented with a second NFET in which the drain of the second input transistor <NUM> is coupled to the third input-stage switch <NUM> and the source of the second input transistor <NUM> is coupled to the first input-stage switch <NUM>. It is to be appreciated that the first input transistor <NUM> and the second input transistor <NUM> are not limited to NFETs and may be implemented with other types of transistors. For example, in other implementations, the first input transistor <NUM> and the second input transistor <NUM> may be implemented with p-type field effect transistors (PFETs) by flipping the structure of the input stage <NUM>.

The first input transistor <NUM> and the second input transistor <NUM> are driven by a differential input signal (e.g., differential data signal) that includes a first input voltage (labeled "INP") and a second input voltage (labeled "INN"). The first input voltage INP is input to a first input <NUM> coupled to the gate of the first input transistor <NUM> and the second input voltage INN is input to a second input <NUM> coupled to the gate of the second input transistor <NUM>. The differential input signal may have a small differential voltage (i.e., small difference between the first input voltage INP and the second input voltage INN) in which the polarity of the differential voltage represents a bit value. As discussed further below, the sense amplifier <NUM> is configured to convert the small differential input voltage into a large differential output voltage to resolve the bit value.

The first input-stage switch <NUM> has a control input <NUM> driven by a clock signal (labeled "CLK"). In this example, the first input-stage switch <NUM> is configured to turn on when the clock signal CLK is high and turn off when the clock signal CLK is low.

The second input-stage switch <NUM> has a control input <NUM> driven by the clock signal CLK, and the third input-stage switch <NUM> has a control input <NUM> driven by the clock signal CLK. In this example, each of the second input-stage switch <NUM> and the third input-stage switch <NUM> is configured to turn on when the clock signal CLK is low and turn off when the clock signal CLK is high.

The input stage <NUM> has a first node <NUM> between the second input-stage switch <NUM> and the first input transistor <NUM>, and a second node <NUM> between the third input-stage switch <NUM> and the second input transistor <NUM>. The voltage at the first node <NUM> (labeled "DINT") and the voltage at the second node <NUM> (labeled "NDINT") are output to the regeneration stage <NUM>, as discussed further below.

The regeneration stage <NUM> includes a first regeneration-stage switch <NUM>, a second regeneration-stage switch <NUM>, a third regeneration-stage switch <NUM>, a first inverter <NUM>, and a second inverter <NUM>. As discussed further below, the first inverter <NUM> and the second inverter <NUM> are cross coupled to provide regenerative feedback.

The first inverter <NUM> has an input <NUM>, an output <NUM>, a first supply terminal <NUM>, and a second supply terminal <NUM>. The second inverter <NUM> has an input <NUM>, an output <NUM>, a first supply terminal <NUM>, and a second supply terminal <NUM>. To cross couple the first inverter <NUM> and the second inverter <NUM>, the input <NUM> of the first inverter <NUM> is coupled to the output <NUM> of the second inverter <NUM>, and the input <NUM> of the second inverter <NUM> is coupled to the output <NUM> of the first inverter <NUM>. The first supply terminal <NUM> of the first inverter <NUM> and the first supply terminal <NUM> of the second inverter <NUM> are coupled to a virtual supply node <NUM>. The second supply terminal <NUM> of the first inverter <NUM> and the second supply terminal <NUM> of the second inverter <NUM> are coupled to the ground rail <NUM>. In this example, a first output <NUM> of the regeneration stage <NUM> is coupled to the output <NUM> of the second inverter <NUM>, and a second output <NUM> of the regeneration stage <NUM> is coupled to the output <NUM> of the first inverter <NUM>.

The first regeneration-stage switch <NUM> is coupled between the output <NUM> of the first inverter <NUM> and the ground rail <NUM>. The first regeneration-stage switch <NUM> has a control input <NUM> coupled to the second node <NUM> of the input stage <NUM>. Thus, the control input <NUM> of the first regeneration-stage switch <NUM> is driven by the voltage NDINT. In this example, the first regeneration-stage switch <NUM> is configured to turn on when the voltage NDINT is above a threshold voltage of the first regeneration-stage switch <NUM> and turn off when the voltage NDINT is below the threshold of the first regeneration-stage switch <NUM>.

The second regeneration-stage switch <NUM> is coupled between the output <NUM> of the second inverter <NUM> and the ground rail <NUM>. The second regeneration-stage switch <NUM> has a control input <NUM> coupled to the first node <NUM> of the input stage <NUM>. Thus, the control input <NUM> of the second regeneration-stage switch <NUM> is driven by the voltage DINT. In this example, the second regeneration-stage switch <NUM> is configured to turn on when the voltage DINT is above a threshold voltage of the second regeneration-stage switch <NUM> and turn off when the voltage DINT is below the threshold of the second regeneration-stage switch <NUM>. The threshold voltage of the second regeneration-stage switch <NUM> may be approximately equal to the threshold voltage of the first regeneration-stage switch <NUM>.

The third regeneration-stage switch <NUM> is coupled between the supply rail <NUM> and the virtual supply node <NUM>. The third regeneration-stage switch <NUM> has a control input <NUM> driven by the complement of the clock signal (labeled "CLKb"), which may be generated by inverting the clock signal CLK with an inverter (not shown). In this example, the third regeneration-stage switch <NUM> is configured to turn on when the complementary clock signal CLKb is low (i.e., the clock signal CLK is high) and turn off when the complementary clock signal CLKb is high (i.e., the clock signal CLK is low).

<FIG> shows an example in which the first input-stage switch <NUM> is implemented with an NFET <NUM> in which the drain of the NFET <NUM> is coupled to internal node <NUM>, the source of the NFET <NUM> is coupled to the ground rail <NUM>, and the control input <NUM> of the first input-stage switch <NUM> is located at the gate of the NFET <NUM>. The second input-stage switch <NUM> is implemented with a PFET <NUM> in which the source of the PFET <NUM> is coupled to the supply rail <NUM>, the drain of the PFET <NUM> is coupled to the first node <NUM>, and the control input <NUM> of the second input-stage switch <NUM> is located at the gate of the PFET <NUM>. The third input-stage switch <NUM> is implemented with a PFET <NUM> in which the source of the PFET <NUM> is coupled to the supply rail <NUM>, the drain of the PFET <NUM> is coupled to the second node <NUM>, and the control input <NUM> of the third input-stage switch <NUM> is located at the gate of the PFET <NUM>.

In the example in <FIG>, the first regeneration-stage switch <NUM> is implemented with an NFET <NUM> in which the drain of the NFET <NUM> is coupled to the output <NUM> of the first inverter <NUM>, the source of the NFET <NUM> is coupled to the ground rail <NUM>, and the control input <NUM> of the first regeneration-stage switch <NUM> is located at the gate of the NFET <NUM>. In this example, the threshold voltage of the first regeneration-stage switch <NUM> corresponds to the threshold voltage of the NFET <NUM>. The second regeneration-stage switch <NUM> is implemented with an NFET <NUM> in which the drain of the NFET <NUM> is coupled to the output <NUM> of the second inverter <NUM>, the source of the NFET <NUM> is coupled to the ground rail <NUM>, and the control input <NUM> of the second regeneration-stage switch <NUM> is located at the gate of the NFET <NUM>. In this example, the threshold voltage of the second regeneration-stage switch <NUM> corresponds to the threshold voltage of the NFET <NUM>. The third regeneration-stage switch <NUM> is implemented with a PFET <NUM> in which the source of the PFET <NUM> is coupled to the supply rail <NUM>, the drain of the PFET <NUM> is coupled to the virtual supply node <NUM>, and the control input <NUM> of the third regeneration-stage switch <NUM> is located at the gate of the PFET <NUM>.

In the example in <FIG>, the first inverter <NUM> includes an NFET <NUM> and a PFET <NUM>. The drain of the NFET <NUM> is coupled to the output <NUM>, the gate of the NFET <NUM> is coupled to the input <NUM>, and the source of the NFET <NUM> is coupled to the second supply terminal <NUM>. The source of the PFET <NUM> is coupled to the first supply terminal <NUM>, the drain of the PFET <NUM> is coupled to the output <NUM>, and the gate of the PFET <NUM> is coupled to the input <NUM>.

The second inverter <NUM> includes an NFET <NUM> and a PFET <NUM>. The drain of the NFET <NUM> is coupled to the output <NUM>, the gate of the NFET <NUM> is coupled to the input <NUM>, and the source of the NFET <NUM> is coupled to the second supply terminal <NUM>. The source of the PFET <NUM> is coupled to the first supply terminal <NUM>, the drain of the PFET <NUM> is coupled to the output <NUM>, and the gate of the PFET <NUM> is coupled to the input <NUM>.

It is to be appreciated that the switches <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> are not limited to the exemplary implementations shown in <FIG>. Also, it is to be appreciated that the first inverter <NUM> and the second inverter <NUM> are not limited to the exemplary implementations shown in <FIG>.

Exemplary operations of the sense amplifier <NUM> will now be discussed according to certain aspects.

When the clock signal CLK is low, the sense amplifier <NUM> is in a reset phase in which nodes of the sense amplifier <NUM> are set to predetermined voltages to initialize the sense amplifier <NUM> for the next bit decision. In the reset phase, the first input-stage switch <NUM> is turned off. As a result, the first input-stage switch <NUM> decouples the first and second input transistors <NUM> and <NUM> from the ground rail <NUM>. The second input-stage switch <NUM> is turned on and the third input-stage switch <NUM> is turned on. As a result, the second input-stage switch <NUM> pulls the first node <NUM> to VCC (i.e., the supply voltage on the supply rail <NUM>) and the third input-stage switch <NUM> pulls the second node <NUM> to VCC. Thus, the voltages NDINT and DINT input to the first and second regeneration-stage switches <NUM> and <NUM>, respectively, of the regeneration stage <NUM> are both pulled to VCC.

In the reset phase, the third regeneration-stage switch <NUM> is turned off since the complementary clock signal CLKb is high when the clock signal CLK is low. As a result, the third regeneration-stage switch <NUM> decouples the first supply terminal <NUM> of the first inverter <NUM> from the supply rail <NUM> and decouples the first supply terminal <NUM> of the second inverter <NUM> from the supply rail <NUM>. This disables the current paths from the supply rail <NUM> to the first supply terminals <NUM> and <NUM> of the inverters <NUM> and <NUM>.

In the reset phase, the first and second regeneration-stage switches <NUM> and <NUM> are both turned on since DINT and NDINT are both pulled to VCC (assuming VCC is greater than the threshold voltages of the switches <NUM> and <NUM>). As a result, the first regeneration-stage switch <NUM> pulls the output <NUM> of the first inverter <NUM> and the input <NUM> of the second inverter <NUM> to ground, and the second regeneration-stage switch <NUM> pulls the output <NUM> of the second inverter <NUM> and the input <NUM> of the first inverter <NUM> to ground.

When the clock signal CLK transitions from low to high, the sense amplifier <NUM> enters a sensing phase in which the input-stage <NUM> senses the differential input signal (e.g., differential data signal). <FIG> shows an example of the voltages DINT and NDINT during the sensing phase for the case where the input voltage INP is higher than the input voltage INN, which may represent a bit value of one. In this example, the clock signal CLK transitions from low to high at time T1. <FIG> also shows the threshold voltage <NUM> for the first and second regeneration-stage switches <NUM> and <NUM>.

At time T1, the first input-stage switch <NUM> turns on, and the second input-stage switch <NUM> and the third input-stage switch <NUM> turn off. This allows the first input transistor <NUM> to pull down the voltage DINT at the first node <NUM> based on the input voltage INP driving the first input transistor <NUM>, and the second input transistor <NUM> to pull down the voltage NDINT at the second node <NUM> based on the input voltage INN driving the first second transistor <NUM>. In this example, the voltage DINT at the first node <NUM> is pulled down at a faster rate than the voltage NDINT at the second node <NUM>. This is because the first input transistor <NUM> is driven by a higher voltage than the second transistor <NUM> in this example (i.e., INP > INN).

At time T2, the voltage DINT falls below the threshold voltage <NUM>, which turns off the second regeneration-stage switch <NUM>. The first regeneration-stage switch <NUM> is still turned on at time T2 since the voltage NDINT is still above the threshold voltage. At time T2, the regeneration stage <NUM> enters a decision phase in which the turning off of the second regeneration-stage switch <NUM> triggers the regenerative feedback of the cross-coupled inverters <NUM> and <NUM>. In this example, the regenerative feedback pulls up the first output <NUM> and pulls down the second output <NUM>. An example of this is illustrated in <FIG>, which shows an example of the output voltage OUTP at the first output <NUM> and the output voltage OUTN at the second output <NUM>. As shown in <FIG>, the regenerative feedback pulls up the first output <NUM> and pulls down the second output <NUM> resulting in a large differential output voltage at the outputs <NUM> and <NUM> representing the resolved bit value. In this example, the output voltage OUTP is higher than the output voltage OUTN, which may represent a bit decision of one.

At time T3, the clock signal CLK transitions from high back to low, causing each of the output voltages OUTP and OUTN to return to the reset voltage of approximately zero volts (i.e., ground).

The sensing phase and decision phase are discussed above for the case where the input voltage INP is higher than the input voltage INN. For the case where the input voltage INN is higher than the input voltage INP, the voltage NDINT at the second node <NUM> of the input stage <NUM> falls below the threshold voltage <NUM> before the voltage DINT at the first node <NUM> of the input stage <NUM> during the sensing phase, causing the first regeneration-stage switch <NUM> to turn off. The turning off of the first regeneration-stage switch <NUM> causes the regenerative feedback of the cross-coupled inverters <NUM> and <NUM> to pull up the second output <NUM> and pull down the first output <NUM>, resulting in a large differential output voltage in which the output voltage OUTN is higher than the output voltage OUTP, which may represent a bit decision of zero.

The cross-coupled inverters <NUM> and <NUM> provide regenerative gain when the first supply terminals <NUM> and <NUM> of the cross-coupled inverters <NUM> and <NUM> are coupled to the supply rail <NUM> through the third regeneration-stage switch <NUM>. The cross-coupled inverters <NUM> and <NUM> may draw a large current from the supply rail <NUM> through the third regeneration-stage switch <NUM> during the sensing phase, causing a large IR voltage drop to appear across the third regeneration-stage switch <NUM>. The large IR voltage drop reduces the supply voltage (labeled "Vp") at the first supply terminals <NUM> and <NUM> of the cross-coupled inverters <NUM> and <NUM>. An example of this is illustrated in <FIG>, which shows an example of the supply voltage VCC at the supply rail <NUM> and the supply voltage Vp at the virtual supply node <NUM>, which is coupled to the first supply terminals <NUM> and <NUM> of the inverters <NUM> and <NUM>. As shown in <FIG>, at the start of the decision phase at time T2, the supply voltage Vp at the virtual supply node <NUM> may be substantially lower (e.g., over <NUM> percent lower) than the supply voltage VCC at the supply rail <NUM> due to the IR drop across the third regeneration-stage switch <NUM>. The lower supply voltage Vp may substantially reduce the regenerative gain of the cross-coupled inverters <NUM> and <NUM>, which substantially slows down the speed with which the regeneration stage <NUM> can render a bit decision and reduces the sensitivity of the sense amplifier <NUM>.

To address the above, aspects of the present disclosure provide a regeneration stage including clock-driven inverters that dynamically control the cross-coupling of the inverters <NUM> and <NUM>. This eliminates the need for the third regeneration-stage switch <NUM>, which allows the first supply terminals <NUM> and <NUM> of the inverters <NUM> and <NUM> to be coupled directly to the supply rail <NUM>. As a result, the supply voltage VCC is applied to the first supply terminals <NUM> and <NUM> of the inverters <NUM> and <NUM>, which increases the regenerative gain of the cross-coupled inverters <NUM> and <NUM> during the decision phase. The increased regenerative gain increases the speed with which the regeneration stage can render a bit decision and increases the sensitivity of the sense amplifier <NUM>. Further, the regeneration stage may include regenerative switches to further increase regenerative gain, as discussed further below.

<FIG> shows a regeneration stage <NUM> according to the invention. The regeneration stage <NUM> may be coupled to the exemplary input stage <NUM> shown in <FIG> or <FIG>. The regeneration stage <NUM> includes the first inverter <NUM>, the second inverter <NUM>, the first regeneration-stage switch <NUM>, and the second regeneration-stage switch <NUM> discussed above.

The regeneration stage <NUM> also includes a third inverter <NUM> and a fourth inverter <NUM>. Each of the third inverter <NUM> and the fourth inverter <NUM> is driven by the clock signal CLK. As discussed further below, the third inverter <NUM> and the fourth inverter <NUM> are configured to control the cross-coupling of the first inverter <NUM> and the second inverter <NUM> based on the clock signal CLK.

The regeneration stage <NUM> also includes a first regenerative switch <NUM> and a second regenerative switch <NUM>. As discussed further below, the first regenerative switch <NUM> and the second regenerative switch <NUM> are configured to provide additional regenerative gain during the decision phase.

In the example in <FIG>, the first supply terminal <NUM> of the first inverter <NUM> and the first supply terminal <NUM> of the second inverter <NUM> are coupled to the supply rail <NUM>. In this example, the supply voltage VCC is applied to the first supply terminals <NUM> and <NUM> of the first and second inverters <NUM> and <NUM>. The second supply terminal <NUM> of the first inverter <NUM> and the second supply terminal <NUM> of the second inverter <NUM> are coupled to the ground rail <NUM>.

The first regeneration-stage switch <NUM> is coupled between the output <NUM> of the first inverter <NUM> and the ground rail <NUM>. The control input <NUM> of the first regeneration-stage switch <NUM> may be coupled to the second node <NUM> of the input stage <NUM>, as discussed above. The second regeneration-stage switch <NUM> is coupled between the output <NUM> of the second inverter <NUM> and the ground rail <NUM>. The control input <NUM> of the second regeneration-stage switch <NUM> may be coupled to the first node <NUM> of the input stage <NUM>, as discussed above.

The third inverter <NUM> has an input <NUM>, an output <NUM>, a first supply terminal <NUM>, and a second supply terminal <NUM>. The input <NUM> of the third inverter <NUM> is driven by the clock signal CLK, and the output <NUM> of the third inverter <NUM> is coupled to the input <NUM> of the second inverter <NUM>. The first supply terminal <NUM> of the third inverter <NUM> is coupled to the supply rail <NUM>, and the second supply terminal <NUM> of the third inverter <NUM> is coupled to the output <NUM> of the first inverter <NUM>.

The fourth inverter <NUM> has an input <NUM>, an output <NUM>, a first supply terminal <NUM>, and a second supply terminal <NUM>. The input <NUM> of the fourth inverter <NUM> is driven by the clock signal CLK, and the output <NUM> of the fourth inverter <NUM> is coupled to the input <NUM> of the first inverter <NUM>. The first supply terminal <NUM> of the fourth inverter <NUM> is coupled to the supply rail <NUM>, and the second supply terminal <NUM> of the fourth inverter <NUM> is coupled to the output <NUM> of the second inverter <NUM>.

The first regenerative switch <NUM> is coupled between the supply rail <NUM> and the input <NUM> of the first inverter <NUM>. The first regenerative switch <NUM> has a control input <NUM> coupled to the output <NUM> of the third inverter <NUM>. The second regenerative switch <NUM> is coupled between the supply rail <NUM> and the input <NUM> of the second inverter <NUM>. The second regenerative switch <NUM> has a control input <NUM> coupled to the output <NUM> of the fourth inverter <NUM>. Each of the regenerative switches <NUM> and <NUM> may be implemented with a PFET or another type of switch.

In the example shown in <FIG>, the first output <NUM> of the regeneration stage <NUM> is coupled to the output <NUM> of the second inverter <NUM>, and the second output <NUM> of the regeneration stage <NUM> is coupled to the output <NUM> of the first inverter <NUM>. However, it is to be appreciated that the regeneration stage <NUM> is not limited to this example, and that the outputs <NUM> and <NUM> may be coupled to other nodes in the regeneration stage <NUM> (e.g., coupled to the outputs <NUM> and <NUM> of the third and fourth inverters <NUM> and <NUM>).

Exemplary operations of the regeneration stage <NUM> will now be discussed according to certain aspects of the present disclosure.

When the clock signal CLK is low, the regeneration stage <NUM> is in the reset phase. In the reset phase, current paths from the supply rail <NUM> to the ground rail <NUM> are disabled, and nodes of the regeneration stage <NUM> are set to predetermined voltages to initialize the regeneration stage <NUM> for the next bit decision, as discussed further below.

In the reset phase, the third inverter <NUM> pulls the input <NUM> of the second inverter <NUM> to the supply voltage VCC, and the fourth inverter <NUM> pulls the input <NUM> of the first inverter <NUM> to the supply voltage VCC. In this case, the third inverter <NUM> and the fourth inverter <NUM> break the cross-coupling paths between the first inverter <NUM> and the second inverter <NUM> (i.e., disable the cross-coupling of the first inverter <NUM> and the second inverter <NUM>). Since the inputs <NUM> and <NUM> of the first and second inverters <NUM> and <NUM> are pulled to VCC, the outputs <NUM> and <NUM> of the first and second inverters <NUM> and <NUM> are driven low.

In addition, in the reset phase, the first regeneration-stage switch <NUM> and the second regeneration-stage switch <NUM> are both turned on. This is because the voltages NDINT and DINT are pulled to VCC in the reset phase, as discussed above.

When the clock signal CLK transitions from low to high at the beginning of the sensing phase, the third inverter <NUM> couples the input <NUM> of the second inverter <NUM> to the output <NUM> of the first inverter <NUM>. This is because, when the clock signal CLK is high, the third inverter <NUM> creates a conduction path between the output <NUM> of the third inverter <NUM> and the second supply terminal <NUM> of the third inverter <NUM>. Since the output <NUM> of the third inverter <NUM> is coupled to the input <NUM> of the second inverter <NUM> and the second supply terminal <NUM> of the third inverter <NUM> is coupled to the output <NUM> of the first inverter <NUM>, the conduction path couples the input <NUM> of the second inverter <NUM> to the output <NUM> of the first inverter <NUM>.

Also, the fourth inverter <NUM> couples the input <NUM> of the first inverter <NUM> to the output <NUM> of the second inverter <NUM>. This is because, when the clock signal CLK is high, the fourth inverter <NUM> creates a conduction path between the output <NUM> of the fourth inverter <NUM> and the second supply terminal <NUM> of the fourth inverter <NUM>. Since the output <NUM> of the fourth inverter <NUM> is coupled to the input <NUM> of the first inverter <NUM> and the second supply terminal <NUM> of the fourth inverter <NUM> is coupled to the output <NUM> of the second inverter <NUM>, the conduction path couples the input <NUM> of the first inverter <NUM> to the output <NUM> of the second inverter <NUM>.

Thus, when the clock signal CLK is high, the third inverter <NUM> couples the input <NUM> of the second inverter <NUM> to the output <NUM> of the first inverter <NUM>, and the fourth inverter <NUM> couples the input <NUM> of the first inverter <NUM> to the output <NUM> of the second inverter <NUM>. As a result, the third inverter <NUM> and the fourth inverter <NUM> enable the cross-coupling of the first inverter <NUM> and the second inverter <NUM>, which enables regenerative feedback.

As discussed above, during the sensing phase, the voltages NDINT and DINT input to the first regeneration-stage switch <NUM> and the second regeneration-stage switch <NUM>, respectively, fall at different rates depending on the polarity of the differential input signal.

In the case where the voltage DINT falls faster than the voltage NDINT (i.e., INP > INN), the voltage DINT falls below the threshold voltage first, causing the second regeneration-stage switch <NUM> to turn off first. The turning off of the second regeneration-stage switch <NUM> triggers the regenerative feedback of the cross-coupled inverters <NUM> and <NUM> to pull the first output <NUM> high and pull the second output <NUM> low. Since the supply voltage VCC is applied to the first supply terminals <NUM> and <NUM> of the first inverter <NUM> and the second inverter <NUM>, the regenerative gain is high, allowing the regeneration stage <NUM> to more quickly pull the first output <NUM> high and pull the second output <NUM> low for a faster bit decision. In contrast, in the regeneration stage <NUM> in <FIG> and <FIG>, the supply voltage Vp applied to the first supply terminals <NUM> and <NUM> of the first inverter <NUM> and the second inverter <NUM> is lower due to the IR voltage drop across the third regeneration-stage switch <NUM>, which decreases the regenerative gain.

For the example where the regenerative switches <NUM> and <NUM> are implemented with PFETs, the pulling down of the second output <NUM> causes the first regenerative switch <NUM> to turn on. As a result, the first regenerative switch <NUM> pulls the input <NUM> of the first inverter <NUM> to VCC, which helps the first inverter <NUM> pull down the second output <NUM> and increase the regenerative gain.

In the case where the voltage NDINT falls faster than the voltage DINT (i.e., INN > INP), the voltage NDINT falls below the threshold voltage first, causing the first regeneration-stage switch <NUM> to turn off first. The turning off of the first regeneration-stage switch <NUM> triggers the regenerative feedback of the cross-coupled inverters <NUM> and <NUM> to pull the second output <NUM> high and pull the first output <NUM> low. Since the supply voltage VCC is applied to the first supply terminals <NUM> and <NUM> of the first inverter <NUM> and the second inverter <NUM>, the regenerative gain is high, allowing the regeneration stage <NUM> to more quickly pull the second output <NUM> high and pull the first output <NUM> low for a faster bit decision.

For the example where the regenerative switches <NUM> and <NUM> are implemented with PFETs, the pulling down of the first output <NUM> causes the second regenerative switch <NUM> to turn on. As a result, the second regenerative switch <NUM> pulls the input <NUM> of the second inverter <NUM> to VCC, which helps the second inverter <NUM> pull down the first output <NUM> and increase the regenerative gain.

<FIG> shows exemplary implementations of the third inverter <NUM> and the fourth inverter <NUM> according to certain aspects. In this example, the third inverter <NUM> includes a first switch <NUM> and a second switch <NUM>. The first switch <NUM> is coupled between the first supply terminal <NUM> and the output <NUM> of the third inverter <NUM>, and the second switch <NUM> is coupled between the output <NUM> and the second supply terminal <NUM> of the third inverter <NUM>. The control input <NUM> of the first switch <NUM> and the control input <NUM> of the second switch <NUM> are coupled to the input <NUM> of the third inverter <NUM>. The first switch <NUM> is configured to turn on when the clock signal CLK is low and turn off when the clock signal CLK is high, and the second switch <NUM> is configured to turn off when the clock signal CLK is low and turn on when the clock signal CLK is high. Thus, when the clock signal CLK is low (i.e., the input <NUM> is low), the first switch <NUM> is turned on and the second switch <NUM> is turned off, and, when the clock signal CLK is high (i.e., the input <NUM> is high), the first switch <NUM> is turned off and the second switch <NUM> is turned on.

In this example, the fourth inverter <NUM> includes a third switch <NUM> and a fourth switch <NUM>. The third switch <NUM> is coupled between the first supply terminal <NUM> and the output <NUM> of the fourth inverter <NUM>, and the fourth switch <NUM> is coupled between the output <NUM> and the second supply terminal <NUM> of the fourth inverter <NUM>. The control input <NUM> of the third switch <NUM> and the control input <NUM> of the fourth switch <NUM> are coupled to the input <NUM> of the fourth inverter <NUM>. The third switch <NUM> is configured to turn on when the clock signal CLK is low and turn off when the clock signal CLK is high, and the fourth switch <NUM> is configured to turn off when the clock signal CLK is low and turn on when the clock signal CLK is high. Thus, when the clock signal CLK is low (i.e., the input <NUM> is low), the third switch <NUM> is turned on and the fourth switch <NUM> is turned off, and, when the clock signal CLK is high (i.e., the input <NUM> is high), the third switch <NUM> is turned off and the fourth switch <NUM> is turned on.

In this example, when the clock signal CLK is low in the reset phase, the first switch <NUM> is turned on and the second switch <NUM> is turned off in the third inverter <NUM>. As a result, the third inverter <NUM> couples the input <NUM> of the second inverter <NUM> to supply rail <NUM> through the first switch <NUM>, which pulls up the input <NUM> of the second inverter <NUM> to VCC. Since the second switch <NUM> is turned off, the input <NUM> of the second inverter <NUM> is decoupled from the output <NUM> of the first inverter <NUM>.

Also, the third switch <NUM> is turned on and the fourth switch <NUM> is turned off in the fourth inverter <NUM>. As a result, the fourth inverter <NUM> couples the input <NUM> of the first inverter <NUM> to the supply rail <NUM> through the third switch <NUM>, which pulls up the input <NUM> of the first inverter <NUM> to VCC. Since the fourth switch <NUM> is turned off, the input <NUM> of the first inverter <NUM> is decoupled from the output <NUM> of the second inverter <NUM>.

Thus, in the reset phase, the input <NUM> of the second inverter <NUM> is decoupled from the output <NUM> of the first inverter <NUM>, and the input <NUM> of the first inverter <NUM> is decoupled from the output <NUM> of the second inverter <NUM>, which disables the cross-coupling of the first inverter <NUM> and the second inverter <NUM>.

When the clock signal CLK transitions from low to high at the beginning of the sensing phase, the first switch <NUM> is turned off and the second switch <NUM> is turned on in the third inverter <NUM>. As a result, the third inverter <NUM> couples the input <NUM> of the second inverter <NUM> to the output <NUM> of the first inverter <NUM> through the second switch <NUM>.

In addition, the third switch <NUM> is turned off and the fourth switch <NUM> is turned on in the fourth inverter <NUM>. As a result, the fourth inverter <NUM> couples the input <NUM> of the first inverter <NUM> to the output <NUM> of the second inverter <NUM> through the fourth switch <NUM>.

Thus, when the clock signal CLK is high in the sensing phase and decision phase, the input <NUM> of the second inverter <NUM> is coupled to the output <NUM> of the first inverter <NUM> through the second switch <NUM>, and the input <NUM> of the first inverter <NUM> is coupled to the output <NUM> of the second inverter <NUM> through the fourth switch <NUM>, which enables the cross-coupling of the first inverter <NUM> and the second inverter and hence enables the regenerative feedback.

<FIG> shows exemplary implementations of the switches <NUM>, <NUM>, <NUM>, <NUM>, <NUM> and <NUM> according to certain aspects. In this example, the first switch <NUM> is implemented with a PFET <NUM> in which the source of the PFET <NUM> is coupled to the first supply terminal <NUM> of the third inverter <NUM>, the drain of the PFET <NUM> is coupled to the output <NUM> of the third inverter <NUM>, and the control input <NUM> is located at the gate of the PFET <NUM>. The second switch <NUM> is implemented with an NFET <NUM> in which the source of the NFET <NUM> is coupled to the second supply terminal <NUM>, the drain of the NFET <NUM> is coupled to the output <NUM> of the third inverter <NUM>, and the control input <NUM> is located at the gate of the NFET <NUM>.

In this example, the third switch <NUM> is implemented with a PFET <NUM> in which the source of the PFET <NUM> is coupled to the first supply terminal <NUM> of the fourth inverter <NUM>, the drain of the PFET <NUM> is coupled to the output <NUM> of the fourth inverter <NUM>, and the control input <NUM> is located at the gate of the PFET <NUM>. The fourth switch <NUM> is implemented with an NFET <NUM> in which the source of the NFET <NUM> is coupled to the second supply terminal <NUM>, the drain of the NFET <NUM> is coupled to the output <NUM> of the fourth inverter <NUM>, and the control input <NUM> is located at the gate of the NFET <NUM>.

In this example, the first regenerative switch <NUM> is implemented with a PFET <NUM> in which the source of the PFET <NUM> is coupled to the supply rail <NUM>, the drain of the PFET <NUM> is coupled to the input <NUM> of the first inverter <NUM>, and the control input <NUM> is located at the gate of the PFET <NUM>. The control input <NUM> is coupled to the output <NUM> of the third inverter <NUM>.

The second regenerative switch <NUM> is implemented with a PFET <NUM> in which the source of the PFET <NUM> is coupled to the supply rail <NUM>, the drain of the PFET <NUM> is coupled to the input <NUM> of the second inverter <NUM>, and the control input <NUM> is located at the gate of the PFET <NUM>. The control input <NUM> is coupled to the output <NUM> of the fourth inverter <NUM>.

In the example shown in <FIG>, the first regeneration-stage switch <NUM> is implemented with the NFET <NUM> discussed above, and the second regeneration-stage switch <NUM> is implemented with the NFET <NUM> discussed above. Also, the first inverter <NUM> is implemented with the NFET <NUM> and the PFET <NUM> discussed above, and the second inverter <NUM> is implemented with the NFET <NUM> and the PFET <NUM> discussed above. However, it is to be appreciated that the present disclosure is not limited to these exemplary implementations.

<FIG> shows an example of the on/off states of the transistors in the regeneration stage <NUM> in the reset phase according to certain aspects. In <FIG>, an "X" next to a transistor indicates that the transistor is turned off.

In this example, the PFET <NUM> in the third inverter <NUM> is turned on and thus couples the input <NUM> of the second inverter <NUM> to the supply rail <NUM>, pulling the input <NUM> of the second inverter <NUM> to VCC. This turns off the PFET <NUM> and turns on the NFET <NUM> in the second inverter <NUM>. The NFET <NUM> of the third inverter <NUM> is turned off and thus decouples the input <NUM> of the second inverter <NUM> from the output <NUM> of the first inverter <NUM>.

The PFET <NUM> in the fourth inverter <NUM> is turned on and thus couples the input <NUM> of the first inverter <NUM> to the supply rail <NUM>, pulling the input <NUM> of the first inverter <NUM> to VCC. This turns off the PFET <NUM> and turns on the NFET <NUM> in the first inverter <NUM>. The NFET <NUM> of the fourth inverter <NUM> is turned off and thus decouples the input <NUM> of the first inverter <NUM> from the output <NUM> of the second inverter <NUM>.

The PFET <NUM> in the first regenerative switch <NUM> is turned off. This is because the PFET <NUM> in the third inverter <NUM> pulls the control input <NUM> of the first regenerative switch <NUM> to VCC in this example. The PFET <NUM> in the second regenerative switch <NUM> is also turned off. This is because the PFET <NUM> in the fourth inverter <NUM> pulls the control input <NUM> of the second regenerative switch <NUM> to VCC in this example.

As shown in <FIG>, current paths from the supply rail <NUM> to the ground rail <NUM> are disabled in the reset phase, allowing nodes in the regeneration stage <NUM> to settle to predetermined voltages shown in <FIG> in the reset phase. The voltage VSS in <FIG> indicates the voltage of the ground rail <NUM>.

<FIG> shows an example of the regeneration stage <NUM> in the sensing phase according to certain aspects. In this example, the NFET <NUM> in the third inverter <NUM> is turned on and thus couples the input <NUM> of the second inverter <NUM> to the output <NUM> of the first inverter <NUM>. The NFET <NUM> in the fourth inverter <NUM> is turned on and thus couples the input <NUM> of the first inverter <NUM> to the output <NUM> of the second inverter <NUM>. As a result, the cross-coupling of the inverters <NUM> and <NUM> is enabled. The PFETs <NUM> ad <NUM> are turned off.

In the sensing phase, current flows through the regeneration stage <NUM> from the supply rail <NUM> which pulls the outputs <NUM> and <NUM> of the regeneration stage <NUM> to a voltage between VCC and ground (labeled "MID"). The voltage MID is not necessarily at the exact midpoint between VCC and ground. The outputs <NUM> and <NUM> may be held at the voltage MID until one of the voltages DINT and NDINT falls below the threshold voltage causing one of the first and second regeneration-stage switches <NUM> and <NUM> to turn off.

<FIG> shows an example of the regeneration stage <NUM> at the beginning of the decision phase for the case where the voltage DINT falls below the threshold voltage before the voltage NDINT (i.e., INP > INN). In this example, the NFET <NUM> of the second regeneration-stage <NUM> turns off first, which triggers the regenerative feedback of the cross-coupled inverters <NUM> and <NUM> to pull the first output <NUM> high (indicated by the up arrow in <FIG>) and pull the second output <NUM> low (indicated by the down arrow in <FIG>). As discussed above, the pulling up of the first output <NUM> and the pulling down of the second output <NUM> produce a large differential output voltage representing a bit value.

In this example, the PFET <NUM> in the first regenerative switch <NUM> is turned on by the pulling down of the second output <NUM>. As a result, the PFET <NUM> pulls the gate of the PFET <NUM> in the first inverter <NUM> to VCC, which helps fully turn off the PFET <NUM> in the first inverter <NUM>. In this example, the NFET <NUM> in the fourth inverter <NUM> may prevent the output <NUM> of the fourth inverter <NUM> from rising all the way to VCC on its own to fully turn off the PFET <NUM> in the first inverter <NUM>. This is because the NFET <NUM> may begin to turn off when the voltage at the source of the NFET <NUM> reaches a voltage equal to the voltage of the clock signal CLK minus the threshold voltage of the NFET <NUM>. In this case, the PFET <NUM> in the first regenerative switch <NUM> is able to pull the gate of the PFET <NUM> up to VCC to fully turn off the PFET <NUM>. This shuts off the current through the PFET <NUM>, which helps the NFET <NUM> in the first inverter <NUM> to pull down the second output <NUM> to ground.

In this example, the PFET <NUM> in the second regenerative switch <NUM> is turned off since the first output <NUM> is pulled up in this example.

As discussed above, <FIG> shows the case where the voltage DINT falls below the threshold voltage before the voltage NDINT (i.e., INP > INN). For the case where the voltage NDINT falls below the threshold voltage before the voltage DINT (i.e., INN > INP), the NFET <NUM> of the first regeneration-stage switch <NUM> turns off first triggering the regenerative feedback of the cross-coupled inverters <NUM> and <NUM> to pull up the second output <NUM> and pull down the first output <NUM>. In this example, the second regenerative switch <NUM> is turned on, which pulls up the gate of the PFET <NUM> in the second inverter <NUM> to VCC.

<FIG> shows an example in which the control input <NUM> of the first regenerative switch <NUM> is coupled to the output <NUM> of the first inverter <NUM>. In this example, the first regenerative switch <NUM> turns on when the second output <NUM> is pulled low. This causes the first regenerative switch <NUM> to pull the input <NUM> of the first inverter <NUM> to VCC, which helps the first inverter <NUM> pull the second output <NUM> low.

In the example in <FIG>, the control input <NUM> of the second regenerative switch <NUM> is coupled to the output <NUM> of the second inverter <NUM>. In this example, the second regenerative switch <NUM> turns on when the first output <NUM> is pulled low. This causes the second regenerative switch <NUM> to pull the input <NUM> of the second inverter <NUM> to VCC, which helps the second inverter <NUM> pull the first output <NUM> low.

<FIG> shows an example in which the first regenerative switch <NUM> and the second regenerative switch <NUM> are implemented with the PFET <NUM> and the PFET <NUM>, respectively. In this example, the gate of the PFET <NUM> is coupled to the output <NUM> of the first inverter <NUM>, and the gate of the PFET <NUM> is coupled to the output <NUM> of the second inverter <NUM>.

The PFET <NUM> increases regenerative gain for the case where the first inverter <NUM> pulls the second output <NUM> low. This is because pulling the second output <NUM> low turns on the PFET <NUM>, which causes the PFET <NUM> to pull the input <NUM> of the first inverter <NUM> up to VCC. The pulling up of the input <NUM> to VCC fully turns off the PFET <NUM> in the first inverter <NUM>, which shuts off the current path through the PFET <NUM> and helps the NFET <NUM> in the first inverter <NUM> pull the second output <NUM> low.

The PFET <NUM> increases regenerative gain for the case where the second inverter <NUM> pulls the first output <NUM> low. This is because pulling the first output <NUM> low turns on the PFET <NUM>, which causes the PFET <NUM> to pull the input <NUM> of the second inverter <NUM> up to VCC. The pulling up of the input <NUM> to VCC fully turns off the PFET <NUM> in the second inverter <NUM>, which shuts off the current path through the PFET <NUM> and helps the NFET <NUM> in the second inverter <NUM> pull the first output <NUM> low.

<FIG> shows an example of a system <NUM> in which aspects of the present disclosure may be used. In this example, the system <NUM> includes a first chip <NUM> and a second chip <NUM> in which SerDes may be used for communication between the first chip <NUM> and the second chip <NUM>. The first chip <NUM> includes a serializer <NUM>, a driver <NUM>, a first output pin <NUM>, and a second output pin <NUM>. The second chip <NUM> includes a first receive pin <NUM>, a second receive pin <NUM>, a receiver <NUM>, the sense amplifier <NUM>, a latch <NUM>, and a deserializer <NUM>.

In this example, the first chip <NUM> and the second chip <NUM> are coupled via a differential serial link including a first line <NUM> and a second line <NUM>. The first line <NUM> is coupled between the first output pin <NUM> and the first receive pin <NUM>, and the second line <NUM> is coupled between the second output pin <NUM> and the second receive pin <NUM>. Each line <NUM> and <NUM> may be implemented with a metal line on a substrate (e.g., a printed circuit board), a wire, etc..

On the first chip <NUM>, the serializer <NUM> is configured to receive parallel data streams (e.g., from a processor on the first chip <NUM>) and convert the parallel data streams into a serial data stream, which is output at an output <NUM> of the serializer <NUM>. The driver <NUM> has an input <NUM> coupled to the output <NUM> of the serializer <NUM>, a first output <NUM> coupled to the first output pin <NUM>, and a second output <NUM> coupled to the second output pin <NUM>. The driver <NUM> is configured to receive the serial data stream, convert the serial data stream into a differential signal, and drive the lines <NUM> and <NUM> of the differential seral link with the differential data signal to transmit the differential signal to the second chip <NUM>. It is to be appreciated that the first chip <NUM> may include additional components not shown in <FIG> (e.g., impedance matching network coupled to the output pins <NUM> and <NUM>, a pre-driver coupled between the serializer <NUM> and the driver <NUM>, etc.).

On the second chip <NUM>, the receiver <NUM> has a first input <NUM> coupled to the first receive pin <NUM>, a second input <NUM> coupled to the second receive pin <NUM>, a first output <NUM> coupled to the first input <NUM> of the sense amplifier <NUM>, and a second output <NUM> coupled to the second input <NUM> of the sense amplifier <NUM>. The receiver <NUM> may include at least one of an amplifier and an equalizer (e.g., to compensate for frequency-dependent signal attenuation between the first chip <NUM> and the second chip <NUM>). The sense amplifier <NUM> receives the differential signal from the receiver <NUM> and makes bit decisions on the differential signal, as discussed above.

In the example in <FIG>, the first output <NUM> of the sense amplifier <NUM> is coupled to a first input <NUM> of the latch <NUM>, and the first output <NUM> of the sense amplifier <NUM> is coupled to a second input <NUM> of the latch <NUM>. The latch <NUM> has an output <NUM> coupled to an input <NUM> of the deserializer <NUM>. The latch <NUM> is configured to latch bit decisions from the sense amplifier <NUM> and output the corresponding bits to the deserializer <NUM>. The deserializer <NUM> is configured to convert the bits into parallel data streams, which may be output to one or more components (not shown) on the second chip <NUM> for further processing. It is to be appreciated that the second chip <NUM> may include additional components not shown in <FIG> (e.g., impedance matching network coupled to the receive pins <NUM> and <NUM>, a clock recovery circuit, etc.).

In the example in <FIG>, the second chip <NUM> also includes a clock circuit <NUM> configured to generate the clock signal CLK and output the clock signal CLK at output <NUM>. The output <NUM> may be coupled to the input <NUM> of the third inverter <NUM> and the input <NUM> of the fourth inverter <NUM> in the regeneration stage <NUM>. The output <NUM> may also be coupled to the control inputs <NUM>, <NUM> and <NUM> of the switches <NUM>, <NUM> and <NUM>, respectively, in the input stage <NUM>.

The clock circuit <NUM> may generate the clock signal CLK using clock data recovery in which the clock circuit <NUM> receives bit decisions via input <NUM> and controls the timing of clock transitions of the clock signal CLK via a phase interpolation based at least in part on the bit decisions. The input <NUM> may be coupled to the output of the latch <NUM>, or one or both outputs <NUM> and <NUM> of the sense amplifier <NUM> to receive the bit decisions.

In certain aspects, the clock circuit <NUM> may include a phase locked loop (PLL), a delay locked loop (DLL), an oscillator, a frequency divider, or any combination thereof. It is to be appreciated that the clock circuit <NUM> may be implemented various types of clock generators.

<FIG> illustrates an exemplary method <NUM> for operation of a regeneration stage of a sense amplifier according to certain aspects of the present disclosure. The regeneration stage may correspond to the regeneration stage <NUM> according to any one or more of the various aspects illustrated in <FIG>. The regeneration stage includes a first inverter (e.g., first inverter <NUM>) and a second inverter (e.g., second inverter <NUM>).

At block <NUM>, cross-coupling of the first inverter and the second inverter is disabled in a first phase. The first phase may correspond to the reset phase discussed above. The disabling of the cross-coupling of the first inverter and the second inverter may be performed by the third inverter <NUM> and the fourth inverter <NUM>. In certain aspects, the disabling of the cross-coupling of the first inverter and the second inverter may include decoupling an input (e.g., input <NUM>) of the second inverter from an output (e.g., output <NUM>) of the first inverter, and decoupling an input (e.g., input <NUM>) of the first inverter from an output (e.g., <NUM>) of the second inverter.

At block <NUM>, the cross-coupling of the second inverter and the second inverter is enabled in a second phase. The second phase may include the sensing phase and the decision phase discussed above. The enabling of the cross-coupling of the first inverter and the second inverter may be performed by the third inverter <NUM> and the fourth inverter <NUM>. In certain aspects, enabling the cross-coupling of the first inverter and the second inverter may include coupling the input of the second inverter to the output of the first inverter, and coupling the input of the first inverter to the output of the second inverter.

In certain aspects, the method <NUM> may also include, in the first phase, coupling the input of the first inverter and the input of the second inverter to a supply rail (e.g., supply rail <NUM>), and, in the first phase, coupling the output of the first inverter and the output of the second inverter to a ground rail (e.g., ground rail).

In certain aspects, the regeneration stage may further includes a first switch (e.g., first regeneration-stage switch <NUM>) coupled between the output of the first inverter and a ground rail (e.g., ground rail <NUM>), and a second switch (e.g., second regeneration-stage switch <NUM>) coupled between the output of the second inverter and the ground rail. In these aspects, the method <NUM> may also include routing a first voltage (e.g., NDINT) from a first node (e.g., node <NUM>) of an input stage (e.g., input stage <NUM>) to a control input (e.g., control input <NUM>) of the first switch, and routing a second voltage (e.g., DINT) from a second node (e.g., node <NUM>) of the input stage to a control input (e.g., <NUM>) of the second switch.

As used herein, a "control input" of a switch is an input that controls whether the switch is turned on (i.e., closed) or turned off (i.e., open) based on a signal (e.g., a voltage) at the control input. For an example where a switch is implemented with a transistor, the control input is located at the gate of the transistor. It is to be appreciated that a switch may be implemented with more than one transistor. For example, a switch may be implemented with a transmission gate, which may include an NFET and a PFET coupled in parallel and driven by complementary signals.

It is to be appreciated that the present disclosure is not limited to the exemplary terminology used above to describe aspects of the present disclosure. For example, the regeneration stage may also be referred to as a decision stage.

Any reference to an element herein using a designation such as "first," "second," and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

The term "approximately", as used herein with respect to a stated value or a property, is intended to indicate being within <NUM>% of the stated value or property.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art.

Claim 1:
A regeneration stage (<NUM>, <NUM>) of a sense amplifier (<NUM>), comprising:
a first inverter (<NUM>) having an input (<NUM>) and an output (<NUM>);
a second inverter (<NUM>) having an input (<NUM>) and an output (<NUM>);
a third inverter (<NUM>) having an input (<NUM>), an output (<NUM>), a first supply terminal (<NUM>), and a second supply terminal (<NUM>), wherein the input (<NUM>) of the third inverter (<NUM>) is configured to receive a clock signal, the output (<NUM>) of the third inverter (<NUM>) is coupled to the input (<NUM>) of the second inverter (<NUM>), the first supply terminal (<NUM>) of the third inverter (<NUM>) is coupled to a supply rail (<NUM>), and the second supply terminal (<NUM>) of the third inverter (<NUM>) is coupled to the output (<NUM>) of the first inverter (<NUM>); and
a fourth inverter (<NUM>) having an input (<NUM>), an output (<NUM>), a first supply terminal (<NUM>), and a second supply terminal (<NUM>), wherein the input (<NUM>) of the fourth inverter (<NUM>) is configured to receive the clock signal, the output (<NUM>) of the fourth inverter (<NUM>) is coupled to the input (<NUM>) of the first inverter (<NUM>), the first supply terminal (<NUM>) of the fourth inverter (<NUM>) is coupled to the supply rail (<NUM>), and the second supply terminal (<NUM>) of the fourth inverter (<NUM>) is coupled to the output (<NUM>) of the second inverter (<NUM>); and
a first switch (<NUM>) coupled between the supply rail (<NUM>) and the input (<NUM>) of the first inverter (<NUM>), the first switch (<NUM>) having a control input (<NUM>) coupled to the output (<NUM>) of the third inverter (<NUM>); and
a second switch (<NUM>) coupled between the supply rail (<NUM>) and the input (<NUM>) of the second inverter (<NUM>), the second switch (<NUM>) having a control input (<NUM>) coupled to the output (<NUM>) of the fourth inverter (<NUM>).