Patent Description:
Fast chirp modulation schemes are required for future radars. Current Frequency-Modulated Continuous-Wave (FMCW) synthesizers employ fractional-n PLL synthesizers. However, these synthesizers are limited with respect to chirp speed. Two point modulated synthesizers overcome these problems as the PLL remains locked during the entire chirp sequence. However, two-point modulated phase locked loops can only approximate a linear frequency modulation with discrete frequency steps. This impairment leads to unwanted ghost targets in the radar image.

<NPL>, discloses a dual-band sub-sampling PLL with a dual-band <NPL> and <NPL> disclose a two-point modulator. Further prior art can be found in <CIT> and <CIT>.

Work of the presently named inventor(s), to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly or impliedly admitted as prior art against the present disclosure.

It is an object to provide a synthesizer that avoids the generation of unwanted ghost targets and provide low phase noise and low frequency error.

According to the present disclosure there is provided a synthesizer as defined in the claims.

One of the aspects of the disclosure is to use a novel synthesizer concept with two cascaded PLLs, which can e.g. be manufactured in CMOS technology as integrated circuitry. The synthesizer comprises a two point modulated PLL, generating the intermediate frequency. This signal drives a second PLL, which preferably includes a fast subsampling phase detector (SSPD) and dead zone PFD. From the input stepwise increasing frequency signal, the second PLL generates a straightened, almost linearly increasing frequency signal in the mm-wave region. Further, high phase accuracy may be achieved by use of the SSPD. The provided synthesizer enables FMCW signal (i.e. chirp signal) generation for radar applications.

The dead zone PFD may be advantageously used in a synthesizer according to the present disclosure. It provides for adjustment of the frequency. After frequency adjustment the subsampling PLL in a synthesizer according to the present disclosure, supports further phase tuning of the PLL.

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, <FIG> shows a first embodiment of a synthesizer <NUM> according to the present disclosure. The synthesizer <NUM> comprises a two-point modulation (TPM) phase locked loop (PLL) circuit <NUM> and a subsampling PLL circuit <NUM>. The TPM PLL circuit <NUM> is configured to receive a frequency tuning signal <NUM> and to generate a stepped chirp signal <NUM> in an intermediate frequency range by applying a two-point modulation PLL on the frequency tuning signal <NUM>. The subsampling PLL circuit <NUM> is configured to receive the stepped chirp signal <NUM> and to generate a smoothened chirp signal <NUM> in a mm-wave frequency range by applying a subsampling PLL on the stepped chirp signal <NUM>.

In fractional-n PLL synthesizers the phase is unlocked when fast chirps are synthesized by the PLL. Hence, fractional-n PLL architectures cannot fulfill the future requirements of the automotive industry in terms of modulation bandwidth, chirp linearity, and chirp speed. To achieve phase lock for applications, where signal modulation bandwidth is much larger than PLL loop bandwidth, TPM PLL synthesizers have been used. TPM PLLs generally comprise a high frequency feedback path for fast modulation and a low frequency path for phase and frequency locking. Hence, loop and modulation bandwidth are decoupled from each other. Frequency switching is hereby often achieved by sigma delta modulation of the frequency divider in the feedback loop. It has been found, however, that this limits the upper frequency range of the feedback loop due to the required oversampling factor and introduces more phase noise and spurs to the system. Further, it has been found that PLL based frequency synthesizers suffer either from limited chirp speed or root mean square (RMS) frequency error and that TPM PLLs suffer from a coarse discrete frequency ramp approximation.

The synthesizer according to the present disclosure, comprising two cascaded PLLs, overcomes these deficiencies. The two-point modulation applied on the first PLL allows a flexible choice of loop bandwidth, optimizing for best phase noise performance. A chirp with discrete frequency steps is synthesized on an intermediate frequency. The first PLL is followed by a second subsampling PLL. Extremely low phase noise and low frequency error is achieved due to the subsampling approach. Furthermore, the discrete frequency steps are smoothened, leading to an almost linear frequency chirp, small phase fluctuations and a large chirp evaluation time.

<FIG> shows a schematic diagram of a second embodiment of a synthesizer <NUM> according to the present disclosure. A fast-stepped frequency FMCW chirp signal <NUM> is generated by the TPM PLL circuit <NUM>. The TPM PLL circuit <NUM> can be implemented as an analogue, partly digital or all digital PLL. The output signal <NUM> of the TPM PLL is applied as reference signal to the subsampling PLL circuit <NUM>. The subsampling PLL circuit <NUM> converts the intermediate frequency chirp signal <NUM> (e.g. in the range of <NUM> to <NUM>) to the mm-wave domain (e.g. in the range of <NUM>-<NUM>). The input signal <NUM> of the second PLL circuit <NUM> is a chirp signal stepwise increasing its frequency. However due to the smoothing characteristic of the second PLL circuit <NUM> a highly linear chirp <NUM> is generated. The bandwidths of the PLLs <NUM>, <NUM> are tuned towards optimal phase noise.

A frequency tuner <NUM> is additionally provided for generating a stepped frequency tuning signal <NUM> from a tuning signal (reference signal) <NUM> (e.g. in the range of <NUM>-<NUM>) and for providing said stepped frequency tuning signal, e.g. a sawtooth wave, to the TPM PLL circuit <NUM> as frequency tuning signal.

The subsampling PLL circuit <NUM> comprises a second phase detector circuit <NUM> (SSPD; subsampling phase detector) configured to receive the stepped chirp signal <NUM> and the smoothened chirp signal <NUM> and to generate a third phase detection signal <NUM>. A second frequency divider <NUM> (/N; division by factor N) applies a frequency division on the smoothened chirp signal <NUM>. A second phase-frequency detector and charge pump circuit <NUM> (DZ-PFD/CP; dead-zone phase frequency detector / charge pump) receives the stepped chirp signal <NUM> and the smoothened chirp signal <NUM> after application of the frequency-division and generates a fourth phase detection signal <NUM>.

Further, the subsampling PLL circuit <NUM> comprises a combiner <NUM> configured to combine the third phase detection signal <NUM> and the fourth phase detection signal <NUM> to obtain a second combined phase detection signal <NUM>. A second loop filter <NUM> (LF) receives the second combined phase detection signal <NUM> and generates a second oscillator tuning signal <NUM>. Finally, a second oscillator <NUM> (VCO; voltage controlled oscillator) receives the second oscillator tuning signal <NUM> and generates the smoothened chirp signal <NUM>.

<FIG> shows a schematic diagram of a third embodiment of a synthesizer <NUM> according to the present disclosure. The subsampling PLL circuit <NUM> is substantially identical to the subsampling PLL circuit <NUM> shown in <FIG>. Further, an exemplary analog TPM PLL circuit <NUM> is employed to synthesize the stepped frequency signal <NUM>.

The TPM PLL circuit <NUM> comprises a first phase detector circuit <NUM> (SSPD) configured to receive the frequency tuning signal <NUM> and the stepped chirp signal <NUM> and to generate a first phase detection signal <NUM>. A first frequency divider <NUM> (/M) apples a frequency division on the stepped chirp signal <NUM>. A first phase-frequency detector and charge pump circuit <NUM> (DZ-PFD/CP) receives the frequency tuning signal <NUM> and the stepped chirp signal <NUM> after application of the frequency-division and generates a second phase detection signal <NUM>.

The TPM PLL circuit <NUM> further comprises a combiner <NUM> configured to combine the first phase detection signal <NUM> and the second phase detection signal <NUM> to obtain a first combined phase detection signal <NUM>. A first loop filter <NUM> (LF) receives the first combined phase detection signal <NUM> and generates a first oscillator tuning signal <NUM>. A first oscillator <NUM> (VCO) receives the first oscillator tuning signal <NUM> and generates the stepped chirp signal <NUM>.

The TPM PLL circuit <NUM> further comprises a control circuit <NUM> configured to receive a reference signal <NUM>, preferably the same signal as reference signal <NUM> and to receive a digital combined phase detection signal <NUM>', in this embodiment generated by an analog-digital-converter <NUM> (ADC) from the combined phase detection signal <NUM>'. Further, the control circuit <NUM> controls the frequency tuning signal <NUM>, in particular the frequency tuning circuit <NUM> in the tuning of the frequency tuning signal <NUM>, by use of a first control signal <NUM> and controls the first oscillator <NUM> by use of a second control signal <NUM>, in this embodiment by use of an analog second control signal <NUM>' generated by a digital-analog-converter <NUM> (DAC) from the second control signal <NUM>. In an implementation a digital processor unit may be used as control circuit <NUM> to control the frequency tuning circuit <NUM> (also called DDS) and the DAC <NUM>. The VCO tuning voltage and the reference frequency may be adjusted simultaneously. Hence, the PLL remains always locked.

To ensure optimum phase noise, a small bandwidth is preferably used in the TPM PLL circuit <NUM>, whereby generally the bandwidth depends on the intersecting point of the power spectral density (PSD) of the upscaled reference phase noise and the VCO phase noise. The SSPD tuning is not capable of adapting to a high bandwidth chirp with a small loop bandwidth. The TPM PLL circuit is therefore supported by the assistance of two-point modulation.

In the synthesizer according to the present disclosure frequency tuning is simultaneously applied at two points inside the TPM PLL: a) a stepped frequency signal <NUM> is applied as a reference for the phase frequency detector <NUM> and/or the phase detector <NUM>; and b) a stepped tuning voltage <NUM> is applied at the two point modulation point of the voltage controlled oscillator <NUM>. In ideal case the additional tuning voltage <NUM> at the VCO <NUM> causes a frequency step which corresponds to the frequency step applied at the reference. The PLL feedback loop is mainly required to compensate nonlinearities, delays or temperature drifts similar to static PLLs which are producing continuous wave signals, e.g. phase noise at low offset frequencies.

In the TPM PLL circuits and the subsampling PLL circuits the respective phase detectors (SSPDs) and the respective phase-frequency detectors (DZ-PFDs) can generally be connected without any additional hardware, which results in a very simple and noiseless design.

<FIG> shows a schematic diagram of an embodiment of a dead zone phase frequency detector <NUM> according to the present disclosure, which may be used as elements <NUM> and/or <NUM> in the synthesizer according to the present disclosure. The dead zone phase frequency detector <NUM> comprises a first input circuit <NUM> configured to receive a first input signal <NUM> and a first reference signal <NUM> and to generate a first output signal <NUM> and a second input circuit <NUM> configured to receive a second input signal <NUM> and a second reference signal <NUM> and to generate a second output signal <NUM>. Preferably, the input ports D of both input circuits <NUM>, <NUM> are forced to a logic high state (in practice they are e.g. connected to a supply voltage), i.e. the reference signals <NUM> and <NUM> are identical (e.g. a common reference signal is used as input for both input circuits <NUM>, <NUM>). Both input circuits <NUM>, <NUM> may be implemented as D-flipflops. The dead zone phase frequency detector <NUM> further comprises a first delay circuit <NUM> configured to delay the first input signal <NUM> by a first delay time and a second delay circuit <NUM> configured to delay the second input signal <NUM> by a second delay time. A first latch circuit <NUM> receives the first delayed input signal <NUM> and the first output signal <NUM> and generates a first latch signal <NUM>. A second latch circuit <NUM> receives the second delayed input signal <NUM> and the second output signal <NUM> and generates a second latch signal <NUM>. Further, a logic circuit <NUM>, in this embodiment a logic AND circuit, is provided that receives the first output signal <NUM> and the second output signal <NUM> and generates a logic signal <NUM> that is provided to as reset signal to the first input circuit <NUM> and the second input circuit <NUM>. Finally, an output circuit <NUM>, e.g. a charge pump with two MOS transistors as current sources, is provided that receives the first latch signal <NUM> and the second latch signal <NUM> and generates the phase detection signal <NUM>, e.g. the phase detection signal <NUM> or <NUM> in the synthesizer <NUM> shown in <FIG>.

The PFD may consist of two D-flipflops, each driven by either the reference signal u1 (<NUM>) or the downscaled VCO signal u2' (<NUM>) coming from the frequency divider. A rising edge of either the signals causes the particular D-flip flop (<NUM> and <NUM>) to pass through the high-state signal (<NUM> or <NUM> respectively) at its in port "D" towards the out port "Q" (<NUM> or <NUM> respectively). As soon as both the "Q" output ports (<NUM> and <NUM>) are in high state, the logic AND gate (<NUM>) will output another "high" state signal (not assigned with number) towards the "RST" inputs, disabling both D-flip flops (<NUM> and <NUM>). The output ports "Q" (<NUM> and <NUM>) are again on "low-state", hence causing the AND gate (<NUM>) to again enable both D-flip flops (<NUM> and <NUM>) waiting for the next rising edge of the input signals (<NUM> and <NUM> respectively). This way, a PFD can experience three states, giving it the name "tri-state PFD". With both flip flops being active and waiting for a rising edge, the "<NUM>-state" is held. Neither of the signals "UP" or "DN" are on the logic "high-state". When a rising edge of the reference signal causes the upper D-flip flop to change its output to the "high-state", the PFD is in state "+<NUM>". If however a rising edge in the downscaled VCO signal reaches the lower D-flip flop first, the PFD changes to "-<NUM>" state instead. With either a rising edge in the downscaled signal while in state "+<NUM>", or in the reference signal, while in state "-<NUM>", the PFD is reset, changing back to state "<NUM>". As the time during which the PFD is in state "+<NUM>" or "-<NUM>" is equal to the time difference of the rising edges, it is also proportional to the phase error. In the ideal case, a PFD with current output would be able to detect arbitrarily small phase errors. By adding delay lines (<NUM> and <NUM> respectively) and D-latches (<NUM> and <NUM> respectively) to the circuit, a dead-zone is created, in which the PFD output is not passing its output signals (<NUM> and <NUM>) to the charge-pump (<NUM>). The delay lines each output a signal (<NUM> and <NUM> respectively), which signal is by a specified time constant a delayed version of the respective input signal (<NUM> and <NUM> respectively). The D-latches pass through their input signals (<NUM> and <NUM> respectively) as soon as the delayed signals are on "high" state. The output signals of the D-latches (<NUM> and <NUM>) are causing the MOS transistors of the charge-pump to generate each a current signal summing up to i_d (<NUM>).

The dead zone phase frequency detector <NUM> illustrated in <FIG> is preferably applied in a synthesizer (as DZ-PFD circuit) according to the present disclosure. Alternatively, conventional DZ-PFDs may be used, as e.g. described in <NPL> or in <NPL>. As long as the PLL is locked and the SSPD is in its linear phase detection region, the PFD is in Dead Zone and will not output any correction impulses. Phase noise, therefore, is added by neither the frequency divider, nor the PFD during that time. Further, PD/CP noise is not multiplied by the square of the division ratio N. When applying this concept to FMCW chirp generation in the mm-wave region, a large ratio N is needed. When choosing the bandwidth, a large N causes this concept to reach its limits in both, maximal chirp speed and optimal phase noise performance. When using inverters after the PFD, a Dead Zone of π/<NUM> is created. However, a Dead Zone as large as the SSPD linear phase detection range π/(2N) can be created by implementing delay lines instead of inverters, as provided in the DZ-PFD according to the present disclosure. In this way, the PFD is tuning towards the desired frequency, as soon as phase errors exceed the SSPD's linear range. Instead of using a pulser following the SSPD, the sampled VCO signal should be held until the next sampling. Thereby, a reference feedthrough modulating the output signal may at least partly be avoided. In case of a constant phase error, the SSPD gives a constant output (no feedthrough). When the detected phase error changes, also the SSPD output will be updated with the reference beat. The PFD would however always output impulses. A constant phase error appears when implementing a LF with one pole at s=<NUM> and applying a frequency ramp as done in the disclosed system.

<FIG> shows a diagram of a theoretical phase noise curve of the synthesizer according to the present disclosure. The phase noise curve can be estimated by evaluation of the theoretical transfer functions. It can be seen from <FIG> that an exceptional phase noise curve for small and large offset frequencies is achieved, when upscaling PLL output to the <NUM> region. The smallest offset frequency which needs to be considered in the FMCW radar is defined by the window function in the slow time domain. This window is in the order of <NUM>. The largest offset frequency is related to the first Nyquist zone of the baseband analog to digital converters which is in the order of <NUM>. The achieved PLL synthesizer topology reduces the phase noise at the complete bandwidth including both frequencies.

<FIG> shows a diagram of a simulated phase noise and angle deviation of the synthesizer according to the present disclosure. <FIG> shows the simulated phase noise curve of the synthesizer topology including two-point modulation which is in excellent agreement with the theoretical expectations, and <FIG> shows the simulated angle deviation.

<FIG> shows a diagram of frequency error at the beginning of a chirp. <FIG> particularly shows the settling time at the beginning of the chirp. Approximately <NUM> ns are required until the cascaded subsampling PLL circuit follows the frequency steps without significant frequency errors. Settling times of known synthesizers are in the order of µs.

<FIG> shows a diagram of phase error at the beginning of a chirp. To further illustrate the settling behavior of the synthesizer the phase error at the output of the cascaded subsampling PLL circuit is particularly computed. It can be seen that a constant phase error is achieved after 100ns.

<FIG> shows a diagram illustrating frequency smoothing caused by the subsampling PLL in the synthesizer according to the present disclosure. A staircase or stepped frequency ramp leads to ghost targets in the radar image. The cascaded PLL leads to a smoothening of the introduced staircases, which leads to an almost linear chirp <NUM>. Smoothening of the curve is achieved due to the low pass behavior of the loop filter in the cascaded subsampling PLL circuit.

<FIG> shows a diagram illustrating the resulting averaged output current <NUM> at a combined sub-sampling phase detector (SSPD) and the phase frequency detector (PFD) output <NUM> related to the phase error. Further, the sum signal <NUM> is shown. It can be seen that only the SSPD contributes to the output current at small phase errors.

A DZ-PFD has a much larger range in which it can detect phase errors and proportionally output an average current output. Within the dead zone, the DZ-PFD does not generate any current output. An SSPD is only able to generate an averaged current output, which is approximately proportional to the detected phase error within a very limited range. As soon as phase errors exceed this range, the SSPD cannot work properly anymore. The dead zone is implemented such that the DZ-PFD assists the SSPD as soon as this limit is reached.

<FIG> shows a schematic diagram of a fourth embodiment of a synthesizer <NUM> according to the present disclosure comprising a modified TPM PLL circuit <NUM>. In the synthesizers <NUM> and <NUM> shown in <FIG> smoothening of the ramp staircases is achieved due to the subsampling PLL circuit <NUM>. However, small ripples are still visible as illustrated in <FIG> and <FIG>. Further ripple reduction can be achieved with the embodiment presented in <FIG>. In this embodiment smoothening of staircases in the VCO tuning voltage <NUM>' is achieved by a lowpass filter <NUM> to obtain a filtered VCO tuning voltage <NUM>". Additional digital filtering or interpolation may be applied in the frequency tuning circuit <NUM>.

<FIG> shows a diagram of simulated phase lock recovery between two sawtooth chirps 302a and 302b (actually, only the end of the first chirp <NUM> and the beginning of the second chirp 302b are depicted). The signal processing can be simplified by utilizing sawtooth chirps. Hence, a large frequency step between two consecutive chirps is required. A particular timeframe is necessary to achieve phase lock after setting the system to the chirp start frequency. As long as the phase is not locked the waveforms are not usable for signal processing. This effect is shown in <FIG> showing the signals <NUM> and <NUM>. The target is to minimize the timeframes where the PLL is out of lock as much as possible.

This target is achieved by tuning the loop filter <NUM> of the subsampling PLL circuit <NUM>. <FIG> shows a schematic diagram of a corresponding fifth embodiment of a synthesizer <NUM> according to the present disclosure comprising a modified TPM PLL circuit <NUM> and a modified subsampling PLL circuit <NUM>. A switch <NUM> inside the loop filter <NUM> can be toggled by a control signal <NUM> which is provided by the control unit <NUM>. The tuning voltage <NUM> at the VCO <NUM> is immediately changed by a tuning voltage <NUM> (utune) from a DAC <NUM> after the switch <NUM> is closed. Hence, the VCO output frequencies are simultaneously adjusted to the chirp start frequency. The switch <NUM> is opened again and phase lock is achieved in a very short time period.

<FIG> shows a schematic diagram of a tunable (passive) loop filter <NUM> as used in the synthesizer <NUM> shown in <FIG>. The VCO tuning voltage <NUM> can be changed very quickly by applying the DAC tuning voltage <NUM> directly at capacitor C1.

The above disclosed embodiments of the synthesizer make use of preferred embodiment of a TPM PLL circuit and of a subsampling PLL circuit. In alternative embodiments of the synthesizer according to the present disclosure conventional embodiments of a TPM PLL circuit (e.g. as disclosed in <NPL>) and/or of a subsampling PLL circuit (e.g. as disclosed in <NPL>) may be used.

With the synthesizer and/or the dead zone phase frequency detector according to the present disclosure various advantages can be achieved. Divider ratios at the feedback loop of the PLLs are reduced due to the cascade. PLL bandwidths are chosen for optimal phase noise performance so that phase noise is decreased. Frequency steps of the two-point modulation are smoothed by the PLL cascade so that spurious tones are decreased. The fractional logic of known analog two-point modulated PLLs is replaced by tuning the reference. Faster chirps can thus be achieved as the oversampling of the fractional logic is not required. Finally, additional tuning of the filters can be employed for implementing fast locking techniques.

Thus, the foregoing discussion discloses and describes merely exemplary embodiments of the present disclosure. As will be understood by those skilled in the art, the present disclosure may be embodied in other specific forms without departing the scope of the present invention as defined in the appended claims.

Further, such a software may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

Claim 1:
A synthesizer comprising two cascaded PLL circuits including:
- a two-point modulation phase locked loop, TPM PLL, circuit (<NUM>, <NUM>, <NUM>, <NUM>, <NUM>) configured to receive a frequency tuning signal and comprising a two-point modulation PLL to generate a stepped chirp signal in an intermediate frequency range, and
- a subsampling PLL circuit (<NUM>, <NUM>, <NUM>, <NUM>) configured to receive the stepped chirp signal generated by the TPM PLL circuit and comprising a subsampling PLL to generate a smoothened chirp signal in a mm-wave frequency range from the stepped chirp signal.