Patent Description:
Monitoring systems are used in a variety of applications including monitoring the health of individual subjects. Some monitoring systems, including some health monitoring systems, include a combination of underlying systems or device components such as sensors, recording systems, and storage units. Software may be integrated with the hardware of one or more device components to aid the communication of data between device components or between a device component and an external component, such as a display, server, analyzer, network, etc..

Some monitoring systems also may have processing systems and associated components to process the data, including data analysis in some instances. However, such monitoring systems commonly employ a processor to control most or all aspects of the data collection and processing, and are thus prone to high power consumption and issues related thereto, potentially including reduced battery life, excessive heat generation, high sampling jitter, maximum achievable bandwidth, and unpredictable timing of events related to the sensor data collection and processing.

Therefore, there is a need for a monitoring system that addresses the above and other issues by reducing power consumption associated with, at least, data collection and processing. The present disclosure addresses this and other needs.

<CIT> discloses methods and apparatus relating to increasing energy efficiency of sensor controllers. In an embodiment, logic (e.g., within a sensor controller) performs one or more tasks corresponding to acquisition of data from one or more sensors. The logic performs the one or more tasks to allow a processor core of the sensor controller to enter (or stay in) a low power consumption state during performance of the one or more data acquisition tasks. Other embodiments are also disclosed.

<CIT> discloses receivers, which may be external or implantable. Aspects of receivers include the presence of one or more of: a high power-low power module; an intermediary module; a power supply module configured to activate and deactivate one or more power supplies to a high-power processing block; a serial peripheral interface bus connecting master and slave blocks; and a multi-purpose connector. Receivers of the invention may be configured to receive a conductively transmitted signal. Also provided are systems that include the receivers, as well as methods of using the same. Additionally. systems and methods are disclosed for using a receiver for coordinating with dosage delivery systems.

<CIT> discloses a system on a chip (SOC) including a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

<CIT> discloses systems and methods providing for a fitness sensor that is located and operates in a sensor hub. The fitness sensor may link to a Bluetooth link controller, a communications hub and numerous environmental and physical sensors in a platform that is conducive to low power utilization. Awakening a host processor only when valid content-oriented sensor data is available may assist to reduce a footprint of power consumption and time spent in computer processing fitness models.

Aspects of the invention is disclosed in connection with the appended claims.

The accompanying figures, together with the written disclosure, serve to illustrate embodiments of a monitoring system. One of ordinary skill in the art will recognize that the particular embodiments illustrated in the figures are merely exemplary and are not intended to limit the scope of the present invention.

The present disclosure relates to a monitoring system and, more particularly, to devices and systems configured for reduced-power sensor data collection and processing in the field of health monitoring. The following description is presented to enable one of ordinary skill in the art to make and use the disclosed embodiments and modifications thereof, and is provided in the context of a patent application and its requirements. Various modifications to the disclosed embodiments and the principles and features described herein will be readily apparent to those of ordinary skill in the art. Thus, the present disclosure is not intended to limit the invention to the embodiments shown; rather, the invention is to be accorded the widest scope consistent with the principles and features described herein.

<FIG> illustrates an example of a subject (e.g., patient) <NUM> wearing a wearable device <NUM>. Wearable device <NUM> may be positioned at any location suitable for its monitoring function or functions. For example, and without limitation, the location may be a region of the upper torso. A specific location suitable for monitoring certain conditions may include any of the left midclavicular line over intercostal space (ICS) <NUM> in a modified lead-II configuration, vertically over the upper sternum, and horizontally on the left midclavicular line over ICS <NUM>. In any these and other locations, when appropriately configured, wearable device <NUM> may be utilized to monitor physiological characteristics or qualities related to subject <NUM> including but not limited to ECG and accelerometer signals. To this and other ends, wearable device <NUM> may include hardware, firmware, and/or software to perform various sensing, processing, and transmitting of information related to the subject <NUM>, as discussed more fully below.

<FIG> collectively illustrate a nonlimiting example of wearable device <NUM> as a wireless sensor device configured with one or more sensors to detect characteristics and/or qualities of subject <NUM>. More particularly, <FIG> illustrates a wireless sensor device in accordance with one or more embodiments described herein, <FIG> illustrates an isometric view of the wireless sensor device of <FIG> with a top cover removed, in accordance with one or more embodiments described herein, and <FIG> illustrates a cross-section view of the wireless sensor device illustrated in <FIG> and components thereof illustrated in <FIG>, in accordance with one or more embodiments described herein.

In some embodiments, wearable device <NUM> may be disposable and/or reusable In the example shown in <FIG>, wearable device <NUM> may include a cover <NUM>, one or more sensors (sensors <NUM> and <NUM> are illustrated), a battery <NUM>, a base <NUM>, a spacer <NUM>, electronic circuitry <NUM>, a transmitter or transceiver <NUM>, a display <NUM>, and a speaker <NUM>. Some components related to or necessary for the functioning of the illustrated components may not be shown for clarity. Furthermore, indications of such components are illustrative in nature and not necessarily to absolute or relative scale or form. Electronic components within wearable device <NUM>, such as some or all electronic components and related structure inside the device when cover <NUM> is in place, may be termed an "electronic assembly" elsewhere in this description. The electronic assembly may include a processing system and sensor data collection system, which are discussed below. The electronic assembly or parts thereof may be disposable and/or reusable relative to or with cover <NUM> and/or base <NUM>.

In one or more embodiments, wearable device <NUM> may be attached to subject <NUM> via base <NUM> by, e.g., a skin-friendly adhesive or other device. Sensors <NUM>, <NUM> may be in direct contact with subject <NUM> or separated from subject <NUM> by base <NUM> or other component(s) or device(s). Although two sensors are shown, wearable device <NUM> may have one sensor or more than two sensors. Spacer <NUM> may include a suitable insulating material to physically and/or electrically separate elements such as electronic circuitry <NUM> and sensor <NUM> or base <NUM>, and additional insulating material may be employed instead of or together with spacer <NUM> for such a purpose. Such insulating material may include air, foam and/or Polyetheretherketone (PEEK) for insulation, for example.

In general, sensors <NUM> and <NUM> are configured and placed to obtain data from subject <NUM>. Such data is processed by wearable device <NUM>, for example by a processor system-on-chip, to obtain data by any combination of analog, digital, and/or algorithmic processes. (Hereinafter, usage of "process" may include "analysis" with respect to data; these terms thus may be used in combination, singly, interchangeably, or in the alternative as context dictates or permits. ) The obtained data may be stored in a memory on wearable device <NUM> or transmitted externally by transmitter/transceiver <NUM> as desired. According to at least one embodiment, the processor may execute instructions to process the data and obtain information regarding the subject, such as conditions related to the subject's health. The processed data or information may be displayed via display <NUM> of wearable device <NUM>. (Hereinafter, "data" or "information" may be used in combination, singly, interchangeably, or in the alternative as context dictates or permits. ) Additionally or alternatively, the processed information may be provided to transmitter/transceiver <NUM> and, in turn, be transmitted externally to a user or device for any suitable purpose, such as information gathering, further processing, user or machine analysis, and/or storage. By way of nonlimiting example, transmitter/transceiver <NUM> may transmit information such as physiological signals after analysis or in raw form to a remote device/server (e.g. a terrestrial or cloud-based server, or a mobile device such as a smartphone or tablet (not shown in <FIG>)). Information also may be provided in an audible form, such as a verbal report or nonverbal signal (e.g., alert).

One of ordinary skill in the art readily recognizes that a variety of sensors can be utilized as or in addition to sensors <NUM> and <NUM> described above, including but not limited to temperature sensors; respiratory sensors; sensors of heart, brain, and other organ activity; body position accelerometers (e.g., tri-axial accelerometers, uni-axial accelerometers, bi-axial accelerometers, and/or gyroscopes); and/or pressure sensors. One of ordinary skill in the art will also readily recognize that details of the electronic assembly, other electrical components, form factor, structural and electrical configuration, materials, etc. are illustrative and that various modifications of the same may be made in accordance with such factors as patient size, configuration, and comfort; physical environment; cost, etc..

<FIG> is a block diagram schematically illustrating basic elements that may comprise one or more embodiments of wearable device <NUM>. As shown, wearable device <NUM> may include sensor <NUM>, <NUM> to detect information, e.g., at least one physiological signal from subject <NUM>; a processor <NUM> operably coupled to receive data collected from sensors <NUM>, <NUM>; and a memory <NUM> coupled to the processor, wherein memory <NUM> may store an application <NUM> including instructions that, when executed by the processor, cause the processor to perform operations related to the information detected by sensors <NUM>, <NUM>. Such operations may, for example, include processing and/or analyzing the collected data to determine a condition of subject <NUM> and/or derive information that, if provided to a user or other device, conveys information that can be used to determine a condition of subject <NUM>. One of ordinary skill in the art will readily conceive of myriad uses for such information and operations to be performed by processor <NUM> to provide the same.

Operations related to detecting information by the sensors, collecting data from the information and providing the data to processor <NUM>, executing application <NUM>, and outputting the processed or related information via transmitter/transceiver <NUM>, display <NUM>, and/or speaker <NUM> are controlled by sequencing and scheduling schemes according to various clocks. Some such schemes rely heavily on processor <NUM> to control, collect, and process the sensor data which, while having some advantages, nevertheless may be prone to issues related to high power consumption such as reduced battery life, excessive heat generation, high sampling jitter, maximum achievable bandwidth, and unpredictable timing of events related to the sensor data collection and processing, to name a few.

<FIG> shows a block diagram illustrating features of one such system. As shown, a system <NUM> may use a processor <NUM> to control, acquire, and process data from multiple sensors. These systems may schedule timing critical events related to sensor data collection and processing of the sensor data and data of peripherals such as a display 404a, a transmitter/transceiver 404b, or a speaker 404c via I/O interface(s) <NUM>, for example using a combination of timers <NUM> and interrupts <NUM>, <NUM>. In the illustrated system, sensor data may be analog data converted to digital data using an analog-to-digital converter (ADC) <NUM>, and processed data output from processor <NUM> may be digital data output to one or more peripherals and/or converted to analog data via a digital-to-analog converter (DAC) <NUM>. The output of DAC <NUM>, via a driver <NUM>, may provide the subject with a signal <NUM> to detect or permit measurement of a physiological sign or to stimulate a response, both of which may be sensed and input to ADC <NUM> as discussed above. For example, signal <NUM> may cause light to be generated in a pulse oximeter, the output of which may be input to ADC <NUM>.

Timing related to critical events and priorities (e.g., sensor selection, ADC triggering, buffering, data write/read, instruction processing, etc.) rely on accurate synchronization, and complex systems such as system <NUM> may have multiple such critical events and priorities, which may lead to uncertainty in timing of the events. In addition, such systems are inherently inefficient in power. Processor <NUM> and a memory <NUM>, which may store application instructions for execution by processor <NUM>, may be a significant part of the system in terms of transistors/gates. System <NUM> may thus run at a high system clock frequency and suffer significantly high dynamic and static power consumption.

Also, as processor <NUM> is responsible for controlling and processing data of multiple sensors, the maximum bandwidth achievable for the system may be limited by high power consumption and few available processor cycles for data acquisition and processing.

To address these and other issues, scheduling, sequencing, and data acquisition management may be decoupled from (i.e., not performed by) the processor. Instead, power to the processor and its operation can be managed synchronously with, e.g., data collection such that data may be collected and stored in the background during a low-power processor time. For example, a clock setting a power supply to the processor can be shut down during (decoupled) data collection and, when a desired amount of data has been collected and/or stored, power is supplied to activate (e.g., "wake up") the processor to process the data and then shut down again when the processing is complete. A block diagram illustrating this and other features is shown schematically in <FIG>.

<FIG> shows a block diagram of elements of a monitoring system in which certain functions may be decoupled from a processor, in accordance with one or more embodiments described herein. For example, system <NUM> may be a System-on-Chip (SoC) capable of use with wirelessly connected sensory devices such as a wireless wearable device <NUM>. As illustrated, system <NUM> may include a processor sub-system <NUM> and a sensor data collection system <NUM> comprising an analog front end (AFE) interface <NUM> and an analog front end (AFE) <NUM>.

In some embodiments, processor sub-system <NUM> may include may include a processor <NUM>, a shared system memory <NUM> (e.g., a static random access memory (SRAM) chip), a memory controller <NUM> (e.g., a direct memory access (DMA) controller), a system bus <NUM>, and a peripheral bus <NUM>. Processor <NUM>, system memory <NUM>, and memory controller <NUM> are shown coupled to system bus <NUM>. If system <NUM> is configured as an SoC, some of the foregoing components or other components may be provided on- or off-chip, although for convenience of description such components may be described herein as being components of system <NUM>.

According to the invention, AFE interface <NUM> includes a programmable event sequencer and scheduler (ESS) <NUM> coupled to system bus <NUM> via register controls <NUM> and peripheral bus <NUM>, a timing generator <NUM>, an optional hardware digital signal processor (DSP) <NUM>, and a buffer <NUM>.

In one or more embodiments, processor <NUM> may be a microprocessor that controls configuration and communication tasks. Processor <NUM> is shown decoupled from sensor scheduling, sequencing, and data acquisition, thereby allowing processor <NUM> to enter a low-power mode (e.g., "sleep"), through a SLEEP instruction or otherwise, while ESS <NUM> manages the sensor scheduling, sequencing, and data collection. When in sleep mode, one or more clocks to processor <NUM> may be turned off, excluding interface modules, for example. In some embodiments, these exclusions may be switched on independently of clock gating selection in order to keep processor <NUM> behaving normally to incoming requests. To awaken processor <NUM> from low-power mode, for example when a desired amount of sensor information has been collected or buffer <NUM> is full, buffer <NUM> provides, according to the present invention, a wake signal to processor <NUM>. Another determinant not part of the present invention, for waking processor <NUM> may be employed. Once awake, processor <NUM> or memory controller <NUM> can retrieve data from buffer <NUM> for processing.

In one or more embodiments, DSP <NUM> may be a microprocessor operating in either single processor mode or, with processor <NUM>, in dual processor mode. DSP <NUM> may perform signal processing-intensive tasks when in dual processor mode, for example. When in single processor mode, DSP <NUM> may perform both control/communications and signal processing. DSP <NUM> is also capable of being set to a sleep mode.

In one or more embodiments, AFE <NUM> may include a selector <NUM> configured to receive analog sensor data and controllably output the analog data to an ADC <NUM> according to a sensor select signal <NUM> from ESS <NUM>. ADC <NUM> may be configured to receive the selected analog data <NUM>, convert analog data <NUM> to digital data <NUM>, and output digital data <NUM> to buffer <NUM> (optionally via DSP <NUM>) in accordance with a trigger signal <NUM> from ESS <NUM>.

In one or more embodiments, processed data output from processor <NUM> may be digital data output to one or more peripherals via peripheral bus <NUM> and/or converted to analog data via a DAC <NUM> via ESS <NUM>. The output of DAC <NUM>, via a driver <NUM>, may provide the subject with a signal <NUM> to detect or permit measurement of a physiological sign or to stimulate a response, both of which may be sensed and input to ADC <NUM> as discussed above. For example, signal <NUM> may cause light to be generated in a pulse oximeter, the output of which may be input to ADC <NUM>. In some embodiments, the output of DAC <NUM> may be fed back to the output of selector <NUM> to improve the signal-to-noise ratio of the input to ADC <NUM>.

Sensory information may be output via suitable peripheral interfaces. For example and without limitation, two SPI (serial peripheral interface) master interfaces may be provided, one dedicated for the SPI flash and another to access SPI slaves on MEMs (microelectromechanical systems), gyroscopes etc. Two UART interfaces also may be provided, one for Bluetooth Low Energy (BTLE) access and another debug access, by way of nonlimiting example. Further, an I2C master interface may be provided for Altimeter access. One of ordinary skill in the art will understand and be able to implement these and other interfaces as needed.

In one or more embodiments, system <NUM> may operate in two power domains - a "VDD" domain and a "VDD_SW' domain. The VDD domain may be an Always-ON domain whereas the VDD_SW may be switched to a low-power SLEEP-state to reduce dynamic and static power, for example.

In some embodiments, the VDD domain may include one or more of clock control, reset control, power-management, and the AFE interface. The processor subsystem, peripherals, and other components, one or more of which may be within the core block, may be in the VDD_SW domain. By having the AFE interface in the "Always-ON" domain, the SoC has the capability to go to a low-power state while still being able to capture data from the AFE.

In some embodiments, the sequencing of events from Normal Power mode (ON-mode) to Low Power mode (SLEEP-mode) may be managed by ESS <NUM>. When in NORMAL mode, processor <NUM> may set up and synchronize timers and the wake-up. For example, processor <NUM> may enable a down-counting timer along with a master-timer, allowing the down-counting timer and master-timer to be in sync. SLEEP mode may be entered when the down-counting timer expires. Other determinants may be used to cause SLEEP mode, including but not limited to an interruption of sensor data collection or end of data retrieval from buffer <NUM>.

During SLEEP mode ESS <NUM>, ADC interface, DAC interface and power management may be at regular VDD and continue to operate as before. In one or more embodiments, NORMAL power mode may resume in accordance with expiration of a sleep timer and/or a trigger. For example, a sleep timer may begin to count down from a preloaded value and NORMAL mode may resume when the sleep timer expires. In one or more embodiments, NORMAL mode may resume in response to a trigger, which may be an external interrupt as from a MEMS or BTLE device, from a buffer <NUM> Almost-Full flag or a battery-brownout signal. The countdown of the sleep timer may begin in accordance with the trigger.

In one or more embodiments, on entering SLEEP mode, a clock to the core may be turned "OFF". When the sleep timer expires or in response to an external interrupt, the clock to the core may be turned "ON", and processor <NUM> may continue from where it was held.

ESS <NUM> may be a time-driven sequencer to perform a sequence of "events. " Within each "event", multiple instructions and triggers can be scheduled, including but not limited to writing analog and digital control registers, triggering DAC <NUM> and ADC <NUM> at programmed times; passing a time stamp received from timing generator <NUM> at an identifiable trigger to buffer <NUM> to identify, e.g., when data is captured at selector <NUM> or an event happened; identifying ADC streams in accordance with the trigger to distinguish data by sensor; etc. ESS <NUM> also may enable one or more core components to be in low-power while it manages the AFE data capturing.

Thus, with processor <NUM> in low-power mode or otherwise, ESS <NUM> can manage scheduling, sequencing, and data acquisition. For example, <FIG> shows ESS <NUM> controlling sensor selection with sensor select signal <NUM>, ADC output with trigger <NUM>, and data write to buffer <NUM> with data_wr signal <NUM>. ESS <NUM> itself may be operably coupled to timing generator <NUM>, and ESS <NUM> and timing generator <NUM> may be coupled to system bus <NUM> via register controls <NUM>. Timing generator <NUM> may act as a reference clock for timings provided by ESS <NUM> and, because ESS <NUM> can have a small instruction memory, ESS <NUM> may be programmable and maintain accurate timing in accordance with the reference clock provided by timing generator <NUM>, while consuming less power than a system under single processor control such as system <NUM>. In particular, the sum of power consumed by ESS <NUM> and processor <NUM> in performing their operations as part of wearable device <NUM> may be less than the power consumed by processor <NUM> in performing similar operations if part of wearable device <NUM>.

<FIG> illustrates an example of a system <NUM> that may implement monitoring in accordance with one or more embodiments described herein. System <NUM> may include a sensor data collection system <NUM>, processor <NUM>, system memory <NUM>, DMA <NUM>, system bus <NUM>, and peripheral bus <NUM> corresponding structurally and/or functionally, at least in part, to sensor data collection system <NUM>, processor <NUM>, system memory <NUM>, DMA <NUM>, system bus <NUM>, and peripheral bus <NUM>, respectively, shown in <FIG>. System <NUM> may also include a display 604a, transmitter/transceiver 604b, speaker 604c, and/or other peripherals coupled to peripheral bus <NUM> via I/O interface(s) <NUM>.

Operations described herein may be implemented using any suitable controller or processor, and software application, which may be stored on any suitable storage location or computer-readable medium. The software application, for example, may provide instructions that enable processor <NUM> (<NUM>) and/or ESS <NUM> to perform one or more operations described herein.

In one or more embodiments, the disclosed processing may be performed by the wearable device or by an external device including but not limited to a sensor/relay/cloud processor, a smartphone device, and/or a cloud computing system.

The electronic assembly or components thereof (such as the processing system and/or the sensor data collection system) may include or comprise one or more of SoC hardware (SoC HW), an operating system, hardware layer abstraction, debug layers, test modules, and device drivers. A nonlimiting example of a suitable SoC may include one or more of the following:.

An example of an ARC-610D <NUM>-bit microprocessor as control processor (e.g., processor <NUM>) may have one or more of the following (no limitation should be inferred):.

An example of an ARC-610D <NUM>-bit microprocessor with XY Memory for DSP Processing (e.g., DSP <NUM>) may have one or more of the following (no limitation should be inferred):.

One of ordinary skill in the art readily recognizes that and other components can be coupled to each other in a variety of different ways and configurations or can be stand-alone devices.

A monitoring system has been disclosed. Embodiments described herein can take the form of an entirely hardware implementation, an entirely software implementation, or an implementation containing both hardware and software elements. Embodiments may be implemented in software, which includes, but is not limited to, application software, firmware, resident software, microcode, etc..

Operations described herein may be implemented using any suitable controllers or processors, and software applications, which may be stored on any suitable storage location or computer-readable medium. The software application provides instructions that enable the processors or controllers to perform the operations described herein.

Furthermore, embodiments may take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer-readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

The medium may be an electronic, magnetic, optical, electromagnetic, infrared, semiconductor system (or apparatus or device), or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include DVD, compact disk-read-only memory (CD-ROM), and compact disk - read/write (CD-R/W).

Claim 1:
A monitoring system, comprising:
a system bus (<NUM>, <NUM>);
a peripheral bus (<NUM>, <NUM>);
a sensor data collection system (<NUM>, <NUM>) configured to control collection of sensor data related to one or more characteristics of a subject (<NUM>), the sensor data collection system (<NUM>, <NUM>) including:
an event sequencer and scheduler, ESS (<NUM>), coupled to the system bus (<NUM>, <NUM>) via the peripheral bus (<NUM>, <NUM>), the ESS (<NUM>) configured to control sequencing and scheduling of the sensor data collection, and
a buffer (<NUM>) configured to receive and buffer data corresponding to the sensor data collected from one or more sensors (<NUM>, <NUM>) in accordance with a signal provided by the ESS (<NUM>); and
one or more processors (<NUM>, <NUM>, <NUM>, <NUM>) configured to:
receive the buffered data from the buffer (<NUM>) in accordance with a wake signal;
process the received data; and
output the processed data;
wherein the sequencing and scheduling of the sensor data collection by the sensor data collection system (<NUM>, <NUM>) is decoupled from the one or more processors (<NUM>, <NUM>, <NUM>, <NUM>);
wherein the one or more processors (<NUM>, <NUM>, <NUM>, <NUM>) are configured to enter a low-power sleep mode during the sensor data collection by the sensor data collection system (<NUM>, <NUM>), the low-power sleep mode preventing the one or more processors (<NUM>, <NUM>, <NUM>, <NUM>) from receiving the buffered data, process the received data, and output the processed data;
wherein the one or more processors (<NUM>, <NUM>, <NUM>, <NUM>) are configured to exit the sleep mode and resume receiving the buffered data in accordance with the wake signal; and
wherein in response to the buffer (<NUM>) being full, the buffer (<NUM>) provides the wake signal to the one or more processors (<NUM>, <NUM>, <NUM>, <NUM>).