Patent Description:
The MIPI (mobile industry processor interface alliance)radio frequency front end control interface, MIPI RFFE, is a standardized interface widely used for control of radio frequency front end systems and is for example used in mobile phones. A MIPI RFFE system may include up to <NUM> slave devices and up to four master devices coupled to a bus instance, including power amplifiers, low noise amplifiers, filters and switches. The components coupled to a bus instance each need a unique address, referred to as USID, for communication via the bus instance.

The USID may be set by a manufacturer of a certain radio frequency device. However, this may lead to problems if two devices which are to be deployed for a single bus instance have the same USID configured, for example when two different devices of the same type having the same USID are to be used, or if two different devices happen to have the same USID by coincidence.

One approach to solve this problem would be to use a plurality of address pins for setting an address, individually fusing chips to set a specific address, or to manufacture the same device with different addresses. All these approaches add to the costs of the devices, which is not desirable.

<CIT> discloses a method according to the preamble of claim <NUM>.

A method as defined in claim <NUM> and a device as defined in claim <NUM> are provided. The dependent claims define further embodiments.

According to an embodiment, a method of address assigning for a MIPI RFFE device is provided, comprising:.

The method further comprises detecting the voltage with a timing based on the MIPI RFFE signal includes detecting the voltage in a sense period, wherein a start of the sense period is based on a rising of a supply voltage at start-up of the MIPI RFFE device and the sense period ends at an n-th clock period of the MIPI RFFE signal.

According to a further embodiment, a MIPI RFFE device is provided, including sense circuitry configured to:
determine a voltage at a configuration terminal of the MIPI device with a timing based on a MIPI RFFE signal received by the MIPI RFFE device,
set an address of the MIPI RFFE device based on the detected voltage.

Detecting the voltage with a timing based on the MIPI RFFE signal includes detecting the voltage in a sense period, wherein a start of the sense period is based on a rising of a supply voltage at start-up of the MIPI RFFE device and the sense period ends at an n-th clock period of the MIPI RFFE signal.

The above summary is merely a brief overview over some embodiments and is not to be construed as limiting.

In the following, various embodiments will be described in detail referring to the attached drawings. These embodiments are given by way of example only and are not to be construed as limiting. For example, while embodiments may be described including a plurality of features (for example components, elements, acts, events, steps etc.), in other embodiments, some of these features may be omitted, and/or may be replaced by alternative features. In addition to the features explicitly shown and described, further features may be provided. For example, embodiments discussed herein relate to address assignment to MIPI RFFE devices. Apart from the address assignment described, the MIPI RFFE devices may be implemented in a conventional manner, for example for communication after the address has been assigned and for performing various functions conventionally performed using MIPI devices, for example as power amplifiers, low noise amplifiers, antenna tuners, filters, switches or any other radio frequency devices in case of MIPI RFFE devices.

Features from various embodiments may be combined to form further embodiments. Variations or modifications described with respect to one of the embodiments may also be applied to other embodiments unless noted otherwise.

Connections or couplings described herein relate to electrical connections or couplings unless noted otherwise. Such connections or couplings may be modified, for example by adding components or by removing components, as long as the general function of the connection or coupling, for example to provide a certain kind of information, to transmit a voltage and/or current or the like, is essentially maintained.

<FIG> is a block diagram showing a MIPI device <NUM> illustrating general features of some embodiments. The components of MIPI device <NUM> may be integrated on a single chip, or may for example be provided in different chips included in a same package.

MIPI device <NUM> includes a first terminal 13A configured to receive a supply voltage VIO, a fifth terminal 13E configured to receive VSS (or ground), VIO being a supply voltage with respect to VSS, a second terminal 13B configured to receive a MIPI RFFE clock signal SCLK, and a third terminal 13C configured to receive a MIPI RFFE data signal SDATA. Signals SDATA, SCLK are examples for MIPI RFFE signals as used herein.

Supply voltage VIO supplies components of device <NUM> with power. Clock signal SCLK and data signal SDATA serve for MIPI data communication, with a MIPI core <NUM> of device <NUM>. MIPI core <NUM> may receive and transmit data signals via terminal 13C, for example receive commands, clocked by clock signal SCLK, and perform any function device <NUM> is intended for, for example the functions discussed above like amplifier functions, tuning functions, switching functions etc. This may be implemented in any conventional manner. While MIPI core <NUM> is coupled to the three terminals 13A-13C, further terminals may be provided in device <NUM>, depending on the function, for example terminals to be coupled to an antenna for tuning, terminals coupled to internal switches of MIPI core <NUM>, terminals for receiving a signal and outputting an amplified signal etc..

Furthermore, device <NUM> includes a fourth terminal 13D, which is used for address configuration at start-up of MIPI RFFE device <NUM>. A voltage VSENSE is applied to fourth terminal 13D in embodiments and detected by sense circuitry <NUM> to determine the address (USID) of device <NUM> to be used. In embodiments, as explained further below in more detail, VSENSE may take on more than two different levels, for example four different levels, to allow setting of four different addresses via a single terminal, namely fourth terminal 13D.

External parasitic capacitances Cpar and internal parasitic capacitances Cpad related to terminal 13D may influence how far VSENSE reaches a sufficiently stable state at sense circuit <NUM> to allow reliable sensing. The time until VSENSE is sufficiently stable may also depend on how fast the supply voltage VIO rises at start-up. On the other hand, at start-up, according to the MIPI RFFE standard device <NUM> should be capable of receiving MIPI RFFE signals, already <NUM> ns after the supply voltage VIO has reached a predefined threshold value at start-up, such that a fast setting of the address of the device <NUM> is required. Embodiments as described below allow for a reliable detection and measurement of VSENSE at start-up of the device.

In embodiments, the timing for detecting voltage VSENSE is based on a MIPI RFFE signal, for example the first MIPI RFFE signal received at terminal 13C after start-up and/or clock signal SCLK received at terminal SCLK. For this timing, MIPI core <NUM> may give information about a MIPI RFFE signal (at terminal 13B and/or 13C) to sense circuitry <NUM>, such that sense circuit <NUM> can base its sense timing thereon.

According to embodiments the end of the sense period for detecting VSENSE or both the start of the sense period and the end of the sense period is based on the MIPI RFFE signal. "Start of sense period" may refer to a point in time where internal nodes of sense circuit <NUM> are charged to threshold voltages for detecting VSENSE, while an internal sense noe is charged to VSENSE. End of the sense period may refer to the point in time where the actual detecting occurs, for example where a voltage at the internal sense node is compared to the threshold voltages, based on which comparison then the address to be set is determined. Various examples for such a timing based on a MIPI RFFE signal received by MIPI RFFE device <NUM> or other devices according to embodiments will be discussed further below.

<FIG> is a flowchart of a method for address assignment to a MIPI RFFE device illustrating general features of some embodiments, which may for example be implemented in the device of Fig. <NUM>, but also may be implemented independently therefrom. In order to avoid repetitions, the method of <FIG> will be described referring to the description of <FIG> above.

At <NUM>, the method includes detecting a voltage at a configuration terminal, like VSENSE at terminal 13D in <FIG>, with a sense timing based on a MIPI RFFE signal received.

At <NUM>, the method includes setting an address for a MIPI RFFE device like device <NUM> of <FIG> based on the detected voltage, for example based on a voltage level of VSENSE. For example, at <NUM> based on the detected VSENSE an address from a group of more than two addresses, for example four addresses, may be selected.

Next, the detection of VSENSE with a sense timing based on a MIPI RFFE signal according to various embodiments will be described referring to <FIG>. <FIG> an example MIPI RFFE signal which may be received for example by device <NUM> on third terminal 13C. Each block in <FIG> may represent one bit of data. The first bit is labeled SSC, may be sent on the data line of the bus and received at 13C, and indicates that a command is going to be sent as SDATA, together with clock signal SCLK. After that, a pause is followed by address bits SA<<NUM>> to SA<<NUM>>, a code bit, seven data bits and a parity bit.

<FIG> illustrates signals at a MIPI RFFE device at start-up. A curve <NUM> illustrates the supply voltage VIO. At start-up, the voltage VIO rises, until at a point in time denoted by a line <NUM> reaches a predefined minimum threshold VIOmin. At a point in time at least <NUM> ns afterwards, as indicated by a vertical line <NUM>, a MIPI RFFE signal according to curve <NUM> may start, where curve <NUM> illustrates the MIPI RFFE clock signal SCLK alternating <NUM> and <NUM> values, which may be sent concurrently with the data signal shown in <FIG>. In other words, at the point in time denoted by line <NUM>, the first bit of the MIPI RFFE data signal, shown in <FIG>, SSC, may occur.

Sense timings based on the MIPI RFFE signal including SCLK as illustrated by curve <NUM> will now be explained referring to <FIG>. Elements shown in <FIG> which have already been explained with reference to <FIG> bear the same reference numerals and will not be described again. In addition to curves <NUM> and <NUM> of <FIG>, each of <FIG> illustrates a voltage VSENSE at a configuration terminal like fourth terminal 13D of <FIG> as a curve <NUM>. As can be seen, at start-up VSENSE rises and over time assumes an essentially stationary value, which depends on a voltage applied externally to terminal 13D. Examples for such voltages will be explained later referring to <FIG>. The time it takes voltage VSENSE to reach an essentially stationary level depends inter alia on capacitances coupled to the terminal, like Cpar and Cpad of <FIG>, and depending on implementation may also depend on other factors, for example on how fast the supply voltage VIO rises.

<FIG> illustrates a first sense timing not corresponding to a claimed embodiment. In <FIG>, a sense period for detecting voltage VSENSE starts at the beginning of the MIPI RFFE signal, for example with the SSC bit of <FIG>, which in the example of <FIG> corresponds to the time marked by line <NUM>. The sense period ends at a predefined clock of the MIPI RFFE clock signal SCLK. In other words, the sense period ends at an nth clock of the MIPI RFFE clock signal. n may be selected based on implementation. For example, in some MIPI RFFE implementations a device to which the address is to be assigned like device <NUM> has to have its address assigned after the first MIPI RFFE signal, such that it can execute a command send if it is addressed by the commands (for example if the bits SA <<NUM>> to SA<<NUM>> address the respective device). In some implementations, the shortest MIPI RFFE signal may include <NUM> clock signal periods. In this case, n is selected to be smaller than <NUM>, for example n = <NUM>, which ensures that the address assignment is complete when the address is needed. In <FIG>, this is symbolized by a vertical line <NUM>, i.e. the sense period starts at the time denoted by line <NUM> corresponding to the beginning of the MIPI RFFE signal, and ends at the nth clock as symbolized by vertical line <NUM>. As can be seen, at the time indicated by vertical line <NUM>, VSENSE according to curve <NUM> has approximately reached its stationary value, which allows for a reliable sensing.

In <FIG>, therefore the sense period starts with a feature of the MIPI RFFE signal (in this case, the first bit, SSC, or first clock of the MIPI RFFE data signal), and ends with a feature of the MIPI RFFE signal (in this case, the n-th clock of the MIPI RFFE clock signal). Instead of starting with the SSC bit, in other embodiment the sense period could also start with a different feature, for example the second clock of the MIPI RFFE clock signal.

A second sense timing which is not a claimed embodiment is shown in <FIG>. As in <FIG>, the sense period starts at the beginning of the MIPI RFFE signal, corresponding to vertical line <NUM>. The sensing stops after a predefined delay, indicated by an arrow <NUM>, after the start, as indicated by a vertical line <NUM>. Also in this case, VIO is almost stable and VSENSE has almost reached its stationary value. The predefined delay indicated by arrow <NUM>, in the example above, is selected to be smaller than <NUM> clock periods, such that also in this case the address is assigned before the end of the MIPI RFFE command.

In <FIG>, the sense period starts with a feature (in example of <FIG> the beginning of) the MIPI RFFE signal, and ends a predefined time after this feature. Also here, instead of the SSC bit, another feature, like for example the second clock, may be used.

A third sense timing usable in some embodiments is shown in <FIG>. Here, as indicated by a vertical line <NUM>, the start of the sense period may be some time during the rise of VIO, for example when VIO reaches a certain threshold value. In some embodiments, the start may coincide with VIO reaching VIOmin, i.e. vertical line <NUM>. In other words, in this case the start of sensing does not depend on the MIPI RFFE signal. The end of sensing is then at an n-th clock of the MIPI RFFE signal, as in case of <FIG>, and marked in <FIG> also with vertical line <NUM> as in <FIG>. This end of the sense period ensures that VSENSE has approximated a stable value.

In <FIG>, the sense time starts depending on the slope, but ends with a feature of the MIPI RFFE signal, in this case the n-th clock.

The above discussed sense timing based on the MIPI RFFE signal in <FIG> in implementations ensures that the voltage to be sensed for address assignment, VSENSE, is essentially stable, and also VIO has reached essentially a stable value. In implementations, this allows a more reliable sensing compared to approaches where the sensing starts at some point during the rise of VIO (similar to <FIG> at line <NUM>) and then ends a predefined delay after that, as then both beginning and end of the sensing depend on the slope of VIO, and depending on how fast voltage VIO rises no stable values of VSENSE and VIO may be reached during the sense period, which may lead to inaccurate sensing.

<FIG> is a circuit diagram illustrating sense circuitry and application of different voltages VSENSE for address assignment according to an embodiment. The sense circuitry may for example be used as sense circuitry <NUM> of <FIG>.

A line <NUM> in <FIG> divides off-chip circuitry <NUM> used for applying a voltage VSENSE and on-chip circuitry <NUM> including the sense circuitry, which may be included in a device like device <NUM> of <FIG>.

The embodiment of <FIG> supports setting of four different addresses. To achieve this, a configuration node <NUM>, which may correspond to fourth terminal 13D of <FIG>, may be coupled to supply voltage VIO directly for setting a first address, may be connected to VIO via a resistor RE for setting a second address, may be left floating (float) for setting a third address or may be coupled to ground VSS for setting a fourth address. In other embodiments, more than four or less than four different couplings of configuration node <NUM> may be used to generate a voltage VSENSE to be sensed. In yet other embodiments, a voltage for setting the address may be applied to configuration node <NUM> directly from a voltage source independent from VIO and VSS.

The on-chip part of <FIG> includes ESD protection circuitry <NUM> protecting the chip against electrostatic discharge (ESD) events at the configuration node <NUM>. Any conventional ESD protection circuitry may be used, for example diodes or other circuit elements which become conducting when a voltage at configuration node <NUM>, thus shunting the voltage to ground VSS or to the positive supply voltage VIO (depending on the sign of the voltage). Such a high voltage may for example be due to an ESD event.

ESD protection circuitry <NUM> may also contribute to the capacitance Cpad, for example due to capacitances of diodes or other elements used in the ESD protection circuitry.

Other than from possibly providing a parasitic capacitance, ESD protection circuitry <NUM> does essentially not influence the behavior of the device shown in normal operation, i.e. outside ESD or other high voltage elements.

In the device of <FIG>, at power on, as soon as VIO is sufficiently high (for example as soon as VIO reaches the value VIOmin shown in <FIG>), transistors 85A, 85B are switched on to become conducting between respective source and drain terminals (in case of field effect transistors) or collector and emitter terminals (in case of bipolar transistors or insulated gate bipolar transistors). This connects an internal sense node <NUM> to VIO via a resistor 86A and to VSS via a resistor 86B. This way, internal sense node <NUM> is charged with the voltage VSENSE. In other embodiments, a voltage to be sensed may be applied directly to internal sense node <NUM>. Resistors 86A, 86B are selected to allow a sufficiently fast charging so that VSENSE is essentially settled at internal sense node <NUM> at the end of the sense period. Values depend on the parasitic capacitances Cpar allowed or expected. The higher Cpar is, the larger a current flow via resistors 86A, 86B needs to be, so smaller values for the resistors 86A, 86B then have to be chosen. Example values are Cpar smaller than 5pF and a current flow smaller than 10µA, but this depends on implementation.

At this time, transistors 88A, 88B are still switched off.

With the beginning of the sense period (for example at the SSD bit as indicated by lines <NUM> in <FIG> and <FIG> or at the point in time in the slope as indicated by line <NUM> in <FIG>), transistors 88A, 88B are switched on. This generates threshold voltages VTHU, VTHM and VTHL by a resistive divider formed by resistors 89A, 89B, 89C and 89D. These threshold voltages are selected such that they are between the four different possible input voltages at configuration node <NUM>, explained above (VIO, VSS, floating or VIO via resistor RE). In case of the sense period beginning with the SSD bit, the SSD bit may trigger a counter <NUM>, which then outputs a signal TH_EN switching transistors 88A, 88B on. In case of <FIG>, instead of signal SSD the counter may be started by VIO exceeding a predefined threshold.

The voltage at internal sense node <NUM> is provided to first inputs of comparators 810A, 810B and 810C. Second inputs of comparators 810A, 810B and 810C are supplied with the threshold voltages VTHU, VTHM and VTHL, respectively. At the end of the sense period (for example at the n-th clock signal in case of <FIG> and <FIG> or after predefined delay <NUM>), comparators 810A, 810B, 810C are enabled to perform the comparison of the voltage at internal sense node <NUM> with the respective threshold voltage VTHU, VTHM and VTHL and output the result to a decode/latch circuit <NUM>. In case of using the n-th clock, counter <NUM> counts starting from SSD (or VIO exceeding a threshold) based on SCKL and outputs a comparator enable signal to COMP_EN to enable comparators 810A, 810B, 810C after the n-th clock has been reached. In case of an analog delay as in <FIG>, instead of a counter an analog delay circuit triggered by SSD or another feature of the MIPI RFFE signal may be used.

Decode/latch circuit <NUM> receives the outputs from comparators 810A, 810B and 810C and outputs an ID value, in this case a <NUM>-bit value, indicating one of four addresses to be used. When the voltage at internal sense node <NUM> exceeds VTHU, a first value of ID is output, if the voltage is between VTHU and VTHM (for example corresponding to VIO being applied via RE), a second value of ID is output, when the voltage at internal sense node <NUM> is between VTHM and VTHL (for example configuration node <NUM> left floating), a third value of ID is output, and when the voltage is below VTHL (for example corresponding to configuration node <NUM> coupled to VSS), a fourth value of ID is output. In embodiments, this value is latched, i.e. it remains being output irrespective of any changes at the configuration node <NUM>. Based on signal ID, then in this case one of four predefined addresses is used for the MIPI RFFE device <NUM> of <FIG>. After this address determining process, the sense circuitry is switched off, e.g. transistors 85A, 85B, 88A and 88B as well as comparators 810A, 810B, 810C are switched off. Therefore, in embodiments, after the setting of the address apart from possible small leakage currents the sense circuitry does not contribute to the current consumption of the device.

Claim 1:
A method of address assigning for a mobile industry processor interface alliance radio frequency front end, MIPI RFFE, device (<NUM>), comprising:
detecting a voltage (VSENSE) at a configuration terminal (13D; <NUM>) of the MIPI RFFE device (<NUM>) with a timing based on a MIPI RFFE signal (SDATA, SCLK) received by the MIPI RFFE device (<NUM>), and
setting the address of the MIPI RFFE device (<NUM>) based on the detected voltage (VSENSE),
characterized in that
detecting the voltage (VSENSE) with a timing based on the MIPI RFFE signal (SDATA, SCLK) includes detecting the voltage (VSENSE) in a sense period, wherein a start of the sense period is based on a rising of a supply voltage (VIO) at start-up of the MIPI RFFE device (<NUM>) and the sense period ends at an n-th clock period of the MIPI RFFE signal (SDATA, SCLK) .