Patent Description:
PLLs are imperfect control circuits, where inaccuracies in the form of phase noise are an ongoing issue. The phase noise occurs due to imperfections in PLL components such as the voltage-controlled oscillator, charge pump and/or loop filter. The push to miniaturize PLLs has been found to increase phase noise. Efforts to improve PLL design and performance are ongoing. <CIT> relates to a dual flip-flop detector type phase locked loop incorporating dynamic phase offset correction. <CIT> relates to a phase locked loop. <CIT> relates to a PLL circuit. <CIT> relates to a phase locked loop circuit.

In accordance with at least one example of the disclosure, a phase-locked loop (PLL) device comprises a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal. The PLL device also comprises a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal. The PLL device also comprises an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal. The PLL device also comprises a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor. The PLL device also comprises a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

In accordance with at least one example of the disclosure, an apparatus comprises circuitry configured to operate based on a clock signal. The apparatus also comprises a PLL configured to adjust the clock signal based on a reference clock signal. The PLL comprises a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal. The PLL also comprises a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal. The PLL also comprises an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal. The PLL also comprises a VCO coupled to the output node of the integrator via a resistor, wherein the VCO is configured to adjust a phase of the clock signal based on the output of the integrator. The PLL also comprises a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

In accordance with at least one example of the disclosure, a PLL method comprises detecting, by a detector, an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal. The method also comprises adjusting a charge pump output based on the error signal. The method also comprises integrating, by an integrator, the charge pump output as a function of time. The method also comprises converting the integrated charge pump output to a voltage signal. The method also comprises applying a correction to the voltage signal using a feedforward circuit coupled directly to the detector. The method also comprises using the corrected voltage signal, by a voltage-controlled oscillator, to provide an output signal with a phase based on the corrected voltage signal.

Disclosed herein are phase-locked loop (PLL) circuits, devices, and methods involving a direct feedforward circuit to reduce phase noise. As used herein, a "direct feedforward circuit" refers to a feedforward circuit that is connected to the phase detector of a PLL circuit. In an example PLL circuit, the phase detector compares an input signal phase with a reference signal phase and provides an error signal (e.g., an UP or DOWN signal). An example UP signal indicates that the input signal phase needs to be increased towards the reference signal phase. An example DOWN signal indicates that the input signal phase needs to be decreased towards the reference signal phase. The feedforward circuit receives the error signal from the phase detector and adjusts a voltage fed into a voltage-controlled oscillator (VCO) that provides the output signal for the PLL circuit. In some examples, the feedforward circuit provides a feedforward signal to a loop filter of a PLL circuit. More specifically, the feedforward signal is used to adjust a reference signal for the loop filter such that an output of the loop filter is adjusted, resulting in an adjustment to the voltage fed into the VCO. In other examples, the feedforward circuit provides a feedforward signal to an input node of the VCO to adjust the voltage fed into the VCO. In either case, the feedforward signal provides a correction to the PLL circuit output that reduces phase noise.

In some examples, the feedforward circuit includes two branches, including first and second branches. The first branch is coupled to a first output node (e.g., an UP signal node) of the phase detector, and the second branch is coupled to a second output node (e.g., a DOWN signal node). As an example, the first branch includes an inverter and a first resistor, while the second branch includes a buffer and a second resistor. The first and second branches are joined at an output node of the feedforward circuit, resulting in the feedforward circuit providing an averaged value of the inputs at its output node.

With the correction provided by the feedforward circuit, the phase error at the PLL circuit output is reduced compared to other PLL circuit topologies. In addition, the disclosed PLL circuit topologies support miniaturization due at least some of the components being small relative to other PLL circuit topologies. In some examples, the disclosed PLL circuit topologies are used with WiFi radio devices and/or other scenarios, where low noise performance of the PLL is needed. To provide a better understanding, various PLL circuit options, feedforward circuit options, and related PLL method options are described using the figures as follows.

<FIG> is a block diagram illustrating an electronic device <NUM> in accordance with various examples. In <FIG>, the electronic device <NUM> represents an integrated circuit (IC), a multi-die module, a printed circuit board (PCB), a consumer product (e.g., a radio device, a telecommunications device, or a computer device), and/or other devices. As shown, the electronic device <NUM> includes a PLL circuit <NUM> coupled to other components <NUM>. In different examples, the other components <NUM> vary. In one example, the other components <NUM> include signal demodulation components. In another example, the other components <NUM> include signal recovery components. In another example, the other components <NUM> include frequency synthesis components. In another example, the other components <NUM> include clock distribution components. In different examples, the electronic device <NUM> is sold as a unit for use in a radio system, telecommunications systems, and/or computer system.

As shown in <FIG>, the PLL circuit <NUM> includes a phase or frequency detector (PFD) <NUM> that receives a feedback signal (CLK) from the other components <NUM>. The PFD <NUM> also receives a reference clock signal (REF_CLK). The output of the PFD <NUM> is an error signal between the phase of the CLK signal and the phase of the REF_CLK signal. As previously discussed, example outputs from the PFD <NUM> include UP or DOWN signals indicating how the CLK signal should be adjusted to align with the CLK_REF signal (UP refers to increasing the phase for the CLK signal and DOWN refers to decreasing a phase for the CLK signal). The output from the PFD <NUM> is provided to a charge pump <NUM> and to a feedforward circuit <NUM>. The output of the charge pump <NUM> is provided to a first input node <NUM> of the loop filter <NUM>.

In one example (labeled option <NUM>), the feedforward circuit <NUM> provides a feedforward signal to a second input node <NUM> of the loop filter <NUM>. With option <NUM>, the feedforward signal is combined with a reference signal (V_REF*) at feedforward node <NUM>, where V_REF* is obtained by applying a reference signal (V_REF) to a resistor (R_O1). More specifically, the output of the loop filter <NUM> is a function of the combination of the V_REF* signal with the feedforward signal applied to the second input node <NUM>, where the output of the loop filter <NUM> is used to provide a voltage to an input node <NUM> of the VCO <NUM>. The output of VCO <NUM> is a signal with a phase based on the voltage at the input node <NUM> of the VCO <NUM>.

In another example (labeled option <NUM>), the feedforward circuit <NUM> provides a feedforward signal to a feedforward node <NUM> coupled to the input node <NUM> of the VCO <NUM>. With option <NUM>, the output of the loop filter <NUM> is combined with the feedforward signal at feedforward node <NUM> and the combined signal is provided to the input node <NUM> of the VCO <NUM>, resulting in the voltage at the input node <NUM> being adjusted based on the feedforward signal from the feedforward circuit <NUM>. With either of options <NUM> and <NUM>, the feedforward circuit <NUM> is coupled directly to the PFD <NUM>, and the feedforward signal is used to adjust the voltage provided to the VCO <NUM> such that phase error in the output signal <NUM> of the PLL circuit <NUM> is reduced.

In operation, the PFD <NUM> of the PLL circuit <NUM> is a detector configured to output an error signal to indicate a phase offset between the CLK signal and the REF_CLK signal. The charge pump <NUM> is coupled to the PFD <NUM> and is configured to output a charge pump signal based on the error signal. In some examples, the loop filter <NUM> includes an integrator with a feedback path, an input node (e.g., the first input node <NUM>), a reference node (e.g., the second input node <NUM>), and an output node, wherein the input node is coupled to the charge pump <NUM> and receives the charge pump signal. In some examples, the VCO <NUM> is coupled to the output node of the integrator via a resistor. Meanwhile, the feedforward circuit <NUM> is coupled directly to the PFD <NUM> and is configured to apply an averaged version of the error signal to correct a voltage level received by the VCO <NUM>.

In some examples (as in option <NUM>), the feedforward circuit <NUM> is coupled to the reference node (e.g., the feedforward node <NUM> is connected to the second input node <NUM>) of the integrator and applies the averaged version of the error signal to the reference node to correct the voltage level received by the VCO <NUM>. In such examples, a reference signal resistor (e.g., R_O1) is between a reference signal node (e.g., the second input node <NUM>) and the feedforward node <NUM>, where the feedforward circuit <NUM> applies the feedforward signal to the reference node of the integrator.

In other examples (as in option <NUM>), the feedforward circuit <NUM> couples to a feedforward node <NUM> between a resistor (see e.g., <FIG> and <FIG>) at the output of the loop filter <NUM> and the VCO <NUM>, where the feedforward circuit <NUM> applies the averaged version of the error signal to the feedforward node <NUM> to correct the voltage level received by the VCO <NUM>. For either of options <NUM> and <NUM>, in some examples, the feedback path of the integrator for the loop filter <NUM> only includes a capacitor. In other examples, the feedback path of the integrator for the loop filter <NUM> includes a capacitor and a feedback resistor.

In some examples, the PFD <NUM> comprises a first output node and a second output node (see e.g., <FIG>). In such examples, the feedforward circuit <NUM> comprises a first path coupled to the first output node, and a second path coupled to the second output node. The first and second paths operate to average pulses (corresponding to the error signal) output from the first and second output nodes of the PFD <NUM>. In one example, the first output node of the PFD <NUM> is configured to output UP signals to the first path, and the second output node of the detector is configured to output DOWN signals to the second path. In some examples, the first path of the feedforward circuit <NUM> comprises an inverter and a first resistor, and the second path of the feedforward circuit <NUM> comprises a buffer and a second resistor. Also, in some examples, the feedforward circuit <NUM> has a gain of Vdd/(<NUM>*π), where Vdd is power supply voltage provided to the integrator.

<FIG> is a schematic diagram illustrating a PLL circuit 102A in accordance with various examples. In the example of <FIG>, the PLL circuit 102A corresponds to the PLL circuit <NUM> of <FIG> with feedforward option <NUM>. More specifically, the PLL circuit 102A comprises a PFD 104A coupled to a charge pump 106A, where the PFD 104A and the charge pump 106A of <FIG> are examples of the PFD <NUM> and the charge pump <NUM> of <FIG>. As shown, the PFD 104A receives a reference clock signal (REF_CLK) and a feedback signal (CLK) as inputs. In some examples, the output of the PFD 104A is an UP signal when a phase of the CLK signal needs to be increased to align with the phase of the REF_CLK signal. On the other hand, in some examples, the output of the PFD 104A is a DOWN signal when a phase of the CLK signal needs to be decreased to align with the phase of the REF_CLK signal.

In the example of <FIG>, the charge pump 106A receives UP and DOWN signals from the PFD 104A and adjusts a charge pump signal to the loop filter 108A accordingly. More specifically, the output of the charge pump 106A is input to the negative input node 109A (an example of the first input node <NUM> in <FIG>) of the loop filter 108A. In <FIG>, the loop filter 108A corresponds to an integrator formed using an operational amplifier <NUM> with a capacitor <NUM> in the feedback loop <NUM>. Meanwhile, the feedforward circuit 110A (an example of the feedforward circuit <NUM> in <FIG>) provides a feedforward signal (labeled "FFS" in <FIG>) to the positive input node 111A (an example of the second input node <NUM> in <FIG>) of the loop filter 108A. As represented in <FIG>, the feedforward signal is combined with a V_REF* signal as the input to the positive input of the loop filter 108A, where the V_REF* signal is a function of a V_REF signal and R_O1 (the V_REF* signal is a derived version of the V_REF signal due to R_O1).

The output of the loop filter 108A is a function of the difference between the signals at the negative input node 109A and the positive input node 111A. In the example of <FIG>, the output of the loop filter 108A is provided to an RC circuit having a resistor (R_OUT) and a capacitor (C_OUT). Between R_OUT and C_OUT is a node <NUM> that couples to an input node 114A of the VCO 112A. Accordingly, for the PLL circuit 102A, the voltage at the input node 114A of the VCO 112A is a function of the operations of the PFD 104A, the charge pump 106A, the feedforward circuit 110A (applying the feedforward signal to the input node 111A of the loop filter 108A), the loop filter 108A, and the RC circuit, where use of the feedforward circuit 110A reduces phase noise in the output signal for the PPL circuit 102A.

<FIG> is a schematic diagram illustrating another PLL circuit 102B in accordance with various examples. In the example of <FIG>, the PLL circuit 102B corresponds to the PLL circuit <NUM> of <FIG> with feedforward option <NUM>. More specifically, the PLL circuit 102B comprises a PFD 104B coupled to a charge pump 106B, where the PFD 104B and the charge pump 106B of <FIG> are examples of the PFD <NUM> and the charge pump <NUM> of <FIG>. As shown, the PFD 104B receives a reference clock signal (REF_CLK) and a feedback signal (CLK) as inputs. In some examples, the output of the PFD 104B is an UP signal when a phase of the CLK signal needs to be increased to align with the phase of the REF_CLK signal. On the other hand, in some examples, the output of the PFD 104B is a DOWN signal when a phase of the CLK signal needs to be decreased to align with the phase of the REF_CLK signal.

In the example of <FIG>, the charge pump 106B receives UP and DOWN signals from the PFD 104B and adjusts a current to the loop filter 108B up or down. More specifically, the output of the charge pump 106B is input to the negative input node 109B (an example of the first input node <NUM> in <FIG>) of the loop filter 108B. Meanwhile, a reference voltage is input to the positive input node 111B (an example of the second input node <NUM> in <FIG>) of the loop filter 108B. In <FIG>, the loop filter 108B corresponds to an integrator formed using an operational amplifier <NUM> with a capacitor <NUM> in the feedback loop <NUM>.

In <FIG>, the output of the loop filter 108B is a function of the difference between the signals at the negative input node 109B and the positive input node 111B. As shown, the output of the loop filter 108B is provided to an RC circuit having a resistor (R_OUT) and a capacitor (C_OUT). Between R_OUT and C_OUT is a node <NUM> that couples to an input node 114B of the VCO 112B. In the example of <FIG>, the node <NUM> receives the feedforward signal (labeled "FFS" in <FIG>) from the feedforward circuit 110B. Accordingly, for the PLL circuit 102B, the voltage at the input node 114B of the VCO 112B is a function of the operations of the PFD 104B, the charge pump 106B, the loop filter 108B, the RC circuit, and the feedforward circuit 110B (applying the feedforward signal to node <NUM>), where use of the feedforward circuit 110B reduces phase noise for the PPL circuit 102B.

<FIG> is a block diagram illustrating a PLL circuit 102C with modeled components in accordance with various examples. In the example of <FIG>, the PLL circuit 102C corresponds to the PLL circuit 102A of <FIG>, PLL circuit 102B of <FIG>, or to the PLL circuit <NUM> of <FIG> with feedforward option <NUM> or <NUM>. As shown, the PLL circuit 102C includes a PFD 104C, which is an example of the PFD 104B in <FIG>, or the PFD <NUM> in <FIG>. The inputs to the PFD 104C include a feedback signal (CLK) and a reference signal (REF _CLK). More specifically, in the example of <FIG>, the REF_CLK signal is represented as being provided to the PFD 104C via a slicer <NUM>. Meanwhile, the CLK signal is represented as being provided to the PFD 104C by passing the output of the VCO 112C (an example of the VCO 112B in <FIG>, or the VCO <NUM> in <FIG>) to a divider buffer <NUM> and a feedback divider <NUM>, where the output of the feedback divider <NUM> is the CLK signal. In the example of <FIG>, the PLL circuit 102C corresponds to the PLL circuit 102B of <FIG>, or to the PLL <NUM> of <FIG> with feedforward option <NUM>.

In <FIG>, the charge pump 106C receives the output of the PFD 104C, where the charge pump 106C is an example of the charge pump 106B of <FIG>, or the charge pump <NUM> of <FIG>. As represented in <FIG>, the charge pump 106C applies a gain (Kd) to the signal from the PFD 104C. Thereafter, the loop filter 108C, which is an example of the loop filter 108B in <FIG>, or the loop filter <NUM> in <FIG>, applies a frequency dependent gain by integration (<NUM>/sC) to the output of the charge pump 106C. The output of the loop filter 108C is combined with the output of a feedforward circuit 110C, which is an example of the feedforward circuit 110B of <FIG>, or the feedforward circuit <NUM> of <FIG>. As represented in <FIG>, the feedforward circuit 110C applies a gain (Kf) to the output of the PFD 104C. The output of the feedforward circuit 110C and the output of the loop filter 108C are combined at node <NUM>, which is an example of the node <NUM> in <FIG>, or the feedforward node <NUM> in <FIG>. The output from the node <NUM> is provided to the VCO 112C, resulting in the VCO 112C outputting a signal with a phase that varies as a function of the signal at node <NUM>. In <FIG>, the output from the VCO 112C is provided to the divider buffer <NUM> as previously discussed, and is a local oscillator signal <NUM>.

The control loop behavior of the PLL circuit 102C can be represented using various parameters. More specifically, in some examples, the phase of the output of the VCO 112C as a function of the phase error between a feedback signal (e.g., CLK) and a reference signal (e.g., REF_CLK) is given as: <MAT> where R = Kf / Kd, where ΦOUT is the phase of the output of the VCO 112C, Φe is the phase error between the CLK signal and the CLK_REF signal, Kd is the gain applied by the charge pump 106C, s is a frequency of the control loop, C is a capacitance of the control loop, R is a resistance of the control loop, and Kv is the gain expressed as a change in VCO output frequency caused by a change in the control voltage at its input. In addition, in some examples, the output voltage (Vc) of the VCO 112C as a function of Φe is given as: <MAT> where Kd is the gain applied by the charge pump 106C, s is a frequency of the control loop, C is the capacitance of the control loop, R is the resistance of the control loop, and Kf is a gain applied by the feedforward circuit 110C. Also, in some examples, a zero for the control loop is determined from other values. For example, in some examples, a zero the control loop is determined as: <MAT> Also, in some examples, a bandwidth for the control loop is estimated from other values. For example, in some examples, a bandwidth (BW) the control loop is estimated as: <MAT>.

<FIG> is a graph <NUM> illustrating phase noise (in dB) as a function of frequency for various PLL circuits in accordance with various examples. In graph <NUM>, various phase noise curves <NUM>, <NUM>, <NUM>, <NUM>, and <NUM> are represented. More specifically, noise curve <NUM> corresponds to a prior art PLL circuit, phase noise curve <NUM> corresponds to the PLL circuit 102A of <FIG>, phase noise curve <NUM> corresponds to the PLL circuit 102B of <FIG>, phase noise curve <NUM> corresponds to a prior art PLL circuit with a noiseless VCO, phase noise curve <NUM> corresponds to the PLL circuit 102A of <FIG> with a noiseless VCO, and phase noise curve <NUM> corresponds to the PLL circuit 102B of <FIG> with a noiseless VCO. As shown in graph <NUM>, use of a feedforward circuit as described herein lowers the phase noise compared to a prior art PLL circuit (which uses an actual resistance R in its feedback path in series with capacitor C).

<FIG> is a flowchart illustrating a PLL method <NUM> in accordance with various examples. As shown, the method <NUM> comprises detecting, by a detector, an error signal to indicate a phase offset between a feedback clock signal (CLK) and a reference clock signal (REF_CLK) at block <NUM>. At block <NUM>, a charge pump output is adjusted based on the error signal. At block <NUM>, the charge pump output is integrated, by an integrator as a function of time. At block <NUM>, the integrated charge pump output is converted to a voltage signal. At block <NUM>, a correction is applied to the voltage signal using a feedforward circuit coupled directly to the detector. In some examples, the operations of block <NUM> involve using the feedforward circuit to apply a correction to a reference node of the integrator. In other examples, the operations of block <NUM> involve using the feedforward circuit to apply a correction to an input node of the VCO. At block <NUM>, the corrected voltage signal is used by a VCO (e.g., VCO 112C in <FIG>, VCO 112B in <FIG>, VCO 112A in <FIG>, VCO <NUM> in <FIG>) to provide an output signal with a phase based on the corrected voltage signal.

Certain terms have been used throughout this description and claims to refer to particular system components. As one skilled in the art will appreciate, different parties may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In this disclosure and claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to. " Also, the term "couple" or "couples" is intended to mean either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation "based on" is intended to mean "based at least in part on. " Therefore, if X is based on Y, X may be a function of Y and any number of other factors.

Claim 1:
A phase-locked loop PLL device that comprises:
a detector (<NUM>) configured to output an error signal to indicate a phase offset between a feedback clock signal (CLK) and a reference clock signal (REF_CLK);
a charge pump (<NUM>) coupled to the detector (<NUM>) and configured to output a charge pump signal based on the error signal;
an integrator (<NUM>) with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump (<NUM>) and receives the charge pump signal;
a voltage-controlled oscillator VCO coupled to the output node of the integrator (<NUM>) via a resistor (R_OUT); and
a feedforward circuit (<NUM>) coupled directly to the detector (<NUM>) and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO;
wherein the feedforward circuit (<NUM>) couples to the reference node of the integrator (<NUM>) and applies the averaged version of the error signal to the reference node to correct the voltage level received by the VCO; further comprising a reference signal resistor between a reference signal node and a connection point at which the feedforward circuit (<NUM>) couples to the reference node.