Patent Description:
Electronic device of the prior art is disclosed in document <CIT>.

The melting temperature or characteristics (including hardness) of the solder used in the bonding process of the electronic device may affect the yields of the device. Thus, improving the yields or reliability of the bonding process of the electronic device has become an important issue in this field.

This in mind, the present invention aims at providing an electronic device and a method of manufacturing the electronic device having improved reliability or yields. In the electronic device of this invention, the solder of the electronic device includes alloy as defined in claim <NUM>. The solder may be applied to the lower-temperature bonding process to reduce the possibility of damage of electronic components or increase hardness of the solder in order to reduce scratches because the melting point of the solder may be reduced, thereby improving the yields or reliability of the electronic device.

This is achieved by an electronic device and a method of manufacturing the electronic device according to the independent claims. The dependent claims pertain to corresponding further developments and improvements.

As will be seen more clearly from the detailed description following below, an electronic device is provided in the present disclosure.

As will be seen more clearly from the detailed description following below, a method of manufacturing an electronic device is provided in the present disclosure.

In the following, the disclosure is further illustrated by way of example, taking reference to the accompanying drawings.

The present disclosure may be understood by reference to the following detailed description, taken in conjunction with the drawings as described below. It is noted that, for purposes of illustrative clarity and being easily understood by the readers, various drawings of this disclosure show a portion of the electronic device, and certain elements in various drawings may not be drawn to scale. In addition, the number and dimension of each element shown in drawings are for illustrative and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and following claims to refer to particular elements. As one skilled in the art will understand, electronic equipment manufacturers may refer to an element by different names. This document does not intend to distinguish between elements that differ in name but not function. In the following description and in the claims, the terms "include", "comprise" and "have" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to.

It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it may be directly on or directly connected to the other element or layer, or intervening elements or layers may be presented (indirectly). In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers presented.

Although terms such as first, second, third, etc., may be used to describe diverse constituent elements, such constituent elements are not limited by the terms. The terms are used to discriminate a constituent element from other constituent elements in the specification. The claims may not use the same terms, but instead may use the terms first, second, third, etc. with respect to the order in which an element is claimed. Accordingly, in the following description, a first constituent element may be a second constituent element in a claim.

The electronic device includes a substrate and electronic components disposed on the substrate. The electronic components include light emitting diode and may include antenna, sensor, display element or other suitable electronic components, but not limited thereto.

Referring to <FIG> schematically illustrates a side view of the electronic device before bonding according to the first embodiment of the present disclosure, and <FIG> schematically illustrates a side view of the electronic device after bonding according to the first embodiment of the present disclosure. As shown in <FIG>, a substrate <NUM> and a light emitting diode (LED) <NUM> are provided, and a solder <NUM> is disposed on or form on the substrate <NUM> and/or a light emitting diode (LED) <NUM>, and the light emitting diode may include quantum dot light emitting diode (QD-LED), micro light emitting diode (micro LED) or other suitable light emitting diodes, but not limited thereto. In some embodiments, a light converting material may be disposed on the light emitting diode, and the light converting material may include quantum dot (QD) material, fluorescence material, color filter (CF) material, phosphor material, other suitable light converting materials or the combinations of the above-mentioned materials, but not limited thereto. In some embodiments, the light converting material may cover the light emitting diode or be disposed corresponding to the light emitting diode. In some embodiments, the substrate <NUM> may include rigid substrate, flexible substrate or the combinations of the above-mentioned substrate, but not limited thereto. In some embodiments, the substrate <NUM> may include foldable substrate or deformable substrate such as plastic substrate, but not limited thereto. In some embodiments, the material of the substrate <NUM> may include glass, quartz, organic polymer, metal, ceramic, other suitable materials or the combinations of the above-mentioned materials, but not limited thereto. If the material of the substrate <NUM> includes organic polymer, the organic polymer may include polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC) or the combinations of the above-mentioned materials, but not limited thereto.

In some embodiments (as shown in <FIG>), at least one switch element <NUM> may be disposed on the substrate <NUM>, and the light emitting diode <NUM> may be electrically connected to the switch element <NUM>, but not limited thereto. In some embodiments, the substrate <NUM> is a thin film transistor substrate, the switch element <NUM> includes thin film transistor or other suitable components. In some embodiments (not shown), the switch element <NUM> and the light emitting diode <NUM> may be disposed on different surfaces of the substrate <NUM> (such as opposite side surfaces), and the light emitting diode <NUM> may be electrically connected to the switch element <NUM>. In some embodiments, other kinds of the electronic components (such as integrated circuit (IC), circuit, conductive pad or wire) may be disposed on the substrate <NUM>, but not limited thereto. In order to simplify or clarify the figures, some of the electronic components mentioned above or the protecting layer is omitted.

In some embodiments, the electronic device may be an active matrix light emitting diode (AM-LED) or passive matrix light emitting diode (PM-LED). In some embodiments, a solder <NUM> may be disposed on or formed on the substrate <NUM>, and the light emitting diode <NUM> bonded to the substrate <NUM> through the solder <NUM>. The solder <NUM> may include metal, alloy, conductive materials or the combinations of the above-mentioned materials, but not limited thereto. The solder <NUM> includes tin (Sn), gold (Au), and a metal element which is one of indium (In) or bismuth (Bi) or may include other suitable materials such as the alloy of tin and indium or the alloy of tin and bismuth. If the material of the solder only includes tin, higher temperature is needed during bonding process because the melting point of tin is higher (about <NUM>), the electronic component may be easily damaged or the reliability of the electronic component may be reduced. If the material of the solder only includes indium, although the melting point of indium is lower (about <NUM>), the scratches may be easily produced because the hardness of indium is lower, abnormal situations may be occurred or the impedance may be increased during bonding process.

In some embodiments of the present disclosure, the solder <NUM> may include tin and indium, such as the alloy or compound of tin and indium, but not limited thereto. The solder <NUM> includes tin and metal element M, the metal element M is one of the indium and bismuth, and the atomic percentage of tin in the solder <NUM> ranges from <NUM>% to <NUM>%, which can reduce the melting point (about <NUM> to <NUM>) and increase the hardness of the solder <NUM>, the possibility of damage or scratch of the electronic component may be reduced. The atomic percentage of tin may be the atomic percentage of tin in the sum of tin and indium (Sn/(Sn+In)) when the metal element M in the solder <NUM> is indium, and the atomic percentage of tin may be designed to range from <NUM>% to <NUM>%.

In another embodiment, the atomic percentage of tin is the atomic percentage of tin in the sum of tin and bismuth (Sn/(Sn+Bi)) when the metal element M in the solder <NUM> is bismuth, and the atomic percentage of tin may be designed to range from <NUM>% to <NUM>%. In another embodiment, the atomic percentage of tin is regarded as (Sn/(Sn+Bi)) or (Sn/(Sn+In)) when the solder <NUM> includes bismuth and indium, and the atomic percentage of tin may be in a range from <NUM>% to <NUM>%. In some embodiments, the atomic percentage of tin in the solder <NUM> is in a range from <NUM>% to <NUM>%, that is, <NUM>% ≦ (Sn/(Sn+In)) ≦ <NUM>% or <NUM>% ≦ (Sn/(Sn+Bi)) ≦ <NUM>%. In some embodiments, the atomic percentage of tin in the solder <NUM> may be in a range from <NUM>% to <NUM>%, that is, <NUM>% ≦ (Sn/(Sn+In)) ≦ <NUM>% or <NUM>% ≦ (Sn/(Sn+Bi)) ≦ <NUM>%. In some embodiments, the atomic percentage of tin in the solder <NUM> may be in a range from <NUM>% to <NUM>%, that is, <NUM>% ≦ (Sn/(Sn+In)) ≦ <NUM>% or <NUM>% ≦ (Sn/(Sn+Bi)) ≦ <NUM>%.

In some embodiments, a bonding layer <NUM> may be disposed between the substrate <NUM> and the solder <NUM>. For example, the bonding layer <NUM> may be an under bump metallurgy (UBM), but not limited thereto. In some embodiments, the bonding layer <NUM> may be used to reduce diffusion of the material of the solder <NUM> to the substrate <NUM>, the bonding layer <NUM> may be served as a barrier layer. In addition, the bonding layer <NUM> may be used to increase the bonding strength or bonding adhesion between the substrate <NUM> and the solder <NUM>, that is, the bonding layer <NUM> may be served as an adhesion layer. Moreover, the bonding layer <NUM> may be used to reduce the impendence between the components or layers, such as the impendence between the conductive pad and the solder <NUM> on the substrate <NUM>, and the uniformity of current transfer may be improved, but not limited thereto. The material of the bonding layer <NUM> may include titanium (Ti), platinum (Pt), nickel (Ni), tungsten (W), palladium (Pd), chromium (Cr), gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), oxides of the above-mentioned metals, transparent conductive oxides (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or the combinations of the above-mentioned materials, but not limited thereto. In some embodiments, the bonding layer <NUM> between the substrate <NUM> and the solder <NUM> may be removed according to the demands.

In some embodiments (as shown in <FIG>), a conductive structure <NUM> may be disposed on the light emitting diode <NUM>. In some embodiments, the material of the conductive structure <NUM> may include gold, other suitable metals or the combinations of the above-mentioned materials, but not limited thereto. When the material of the conductive structure <NUM> includes gold, for example, the conductive structure <NUM> is a gold layer, bonding conditions may be enhanced because of the good corrosion resistance and a higher hardness of gold. In some embodiments, a bonding layer <NUM> may be disposed between the light emitting diode <NUM> and the conductive structure <NUM>. The material and/or function of the bonding layer <NUM> may be the same or similar to the bonding layer <NUM> mentioned above, but not limited thereto. In some embodiments, the bonding layer <NUM> between the light emitting diode <NUM> and the conductive structure <NUM> may be removed according to the demands.

In some embodiments (not shown), the positions of the conductive structure <NUM> and the solder <NUM> shown in <FIG> may be exchanged, that is, the conductive structure <NUM> may be disposed or formed on the substrate <NUM>, and the solder <NUM> may be disposed or formed on the light emitting diode <NUM>. In details, the bonding layer <NUM> and the conductive structure <NUM> may be disposed on the substrate <NUM> in sequence, the bonding layer <NUM> and the conductive structure <NUM> may be disposed on the light emitting diode <NUM> in sequence, and the light emitting diode <NUM> may be bonded to the substrate <NUM> through the solder <NUM>, but not limited thereto. Other suitable layers may be disposed between the above-mentioned components or layers according to the demands. In some embodiments, the bonding layer may be removed according to the demands.

As shown in <FIG>, the conductive structure <NUM> and the solder <NUM> may be mixed to form a solder alloy <NUM> after the bonding process in some embodiments, and the solder alloy <NUM> may be an intermetallic compound (IMC), but not limited thereto. In some embodiments, the solder alloy <NUM> may be located between the bonding layer <NUM> and the bonding layer <NUM>, the bonding layer <NUM> is disposed between the solder alloy <NUM> and the substrate <NUM> and/or the bonding layer <NUM> is disposed between the solder alloy <NUM> and the light emitting diode <NUM>, but not limited thereto. In some embodiments (not shown), when the bonding layer <NUM> and the bonding layer <NUM> are not included in the device, the solder alloy <NUM> may be located between the substrate <NUM> and the light emitting diode <NUM>. In details, the material of the solder alloy <NUM> may include the elements of the conductive structure <NUM> and the solder <NUM>. According to the invention, the solder alloy <NUM> includes gold, tin, and a metal element M, and the metal element M is one of the indium and bismuth. In the solder alloy <NUM>, the atomic percentage of tin in the sum of tin and the metal element M is in a range from <NUM>% to <NUM>%.

When the metal element M is indium, the atomic percentage of tin in the sum of tin and indium (Sn/(Sn+In)) is in a range from <NUM>% to <NUM>% or may be from <NUM>% to <NUM>% in solder alloy <NUM>, that is, <NUM>% ≦ (Sn/(Sn+In)) ≦ <NUM>% or <NUM>% ≦ (Sn/(Sn+In)) ≦ <NUM>%. When the metal element M is bismuth, the atomic percentage of tin in the sum of tin and bismuth (Sn/(Sn+Bi)) is in a range from <NUM>% to <NUM>% or may be from <NUM>% to <NUM>% in the solder alloy <NUM>, that is, <NUM>% ≦ (Sn/(Sn+Bi)) ≦ <NUM>% or <NUM>% ≦ (Sn/(Sn+Bi)) ≦ <NUM>%.

The atomic percentage of the elements included in the solder <NUM> and/or the solder alloy <NUM> described in the present disclosure may be obtained by measurement and calculation conducted through energy dispersive spectrometer (EDS), X-ray analyzer or other suitable analyzers.

Other embodiments of the present disclosure will be described in following paragraphs. In order to simplify the descriptions, the label of the same elements would be the same in the following description. In order to compare the differences between embodiments, the differences between different embodiments will be described in detail, and the repeated features will not be redundantly described.

Referring to <FIG> schematically illustrates a side view of the electronic device before bonding according to the second embodiment of the present disclosure, which is an embodiment of the invention. Different from the first embodiment (shown in <FIG>), the bonding layer <NUM>, the conductive structure <NUM>, and the solder <NUM> are disposed or formed on the light emitting diode <NUM> in sequence, and the bonding layer <NUM>, the conductive structure <NUM>, and the solder <NUM> are disposed or formed on the substrate <NUM> in sequence in some embodiments (as shown in <FIG>), but not limited thereto. According to the invention (as shown in <FIG>), the conductive structure <NUM> is disposed between the solder <NUM> and the light emitting diode <NUM>, and the conductive structure <NUM> is disposed between the solder <NUM> and the substrate <NUM>.

The conductive structure includes gold and is disposed between the solder and the bonding layer, the conductive structure may be used to increase the adhesion between the solder and the bonding layer. The conductive structure <NUM> or the conductive structure <NUM> may be respectively used to increase the adhesion between the solder <NUM>, the solder <NUM> and other components (such as the bonding layer <NUM> and the bonding layer <NUM>), as shown in <FIG>.

In some embodiments, not forming part of the claimed invention, the positions of the conductive structure <NUM> and solder <NUM> shown in <FIG> may be exchanged. In some embodiments, not forming part of the claimed invention, the positions of the conductive structure <NUM> and solder <NUM> shown in <FIG> may be exchanged. In some embodiments, the bonding layer <NUM> and/or the bonding layer <NUM> may be selectively removed. When the conductive structure <NUM> is disposed on the surface of the solder <NUM> which is away from the light emitting diode <NUM> and the material of the conductive structure <NUM> includes gold, the conductive structure <NUM> may protect the solder <NUM> or reduce the possibility of oxidation of the solder <NUM>. When the conductive structure <NUM> is disposed on the surface of the solder <NUM> which is away from the substrate <NUM> and the material of the conductive structure <NUM> includes gold, the conductive structure <NUM> may protect the solder <NUM> or reduce the possibility of oxidation of the solder <NUM>.

In some embodiments (as shown in <FIG>), the thickness of the conductive structure <NUM> (or the conductive structure <NUM>) may be less than or equal to the thickness of the solder <NUM> (or the solder <NUM>), but not limited thereto. It should be noted that, the thicknesses of the components (or layers) disposed on the substrate <NUM> mentioned above or in the following description may be defined as the maximum thicknesses of the components (or layers) in a normal direction of the substrate <NUM>. Similarly, the thicknesses of the components (or layers) disposed on the light emitting diode <NUM> mentioned above or in the following description may be defined as the maximum thicknesses of the components (or layers) in a normal direction of the light emitting diode <NUM>. The thicknesses of the above-mentioned components (or layers) may be measured through the picture of any cross-sectional view of the components or layers taken by the scanning electron microscope (SEM). For example, the layer A (analyte) is disposed between the layer B and the layer C, the picture taken by SEM should display at least a part of the layer A, at least a part of the layer B, and at least a part of the layer C, and the layer A having the entire thickness should be shown in the picture, and the maximum thickness of the layer A measured through the SEM picture may be regarded as the thickness of the layer A, but not limited thereto.

In some embodiments not forming part of the claimed invention (not shown), the solder <NUM> (as shown in <FIG>) formed in the substrate <NUM> may be removed, that is, the bonding layer <NUM> and the conductive structure <NUM> are formed or disposed on the substrate <NUM> in sequence. In some embodiments not forming part of the claimed invention (not shown), the solder <NUM> (as shown in <FIG>) formed on the light emitting diode <NUM> may be removed, the bonding layer <NUM> and the conductive structure <NUM> are formed or disposed on the light emitting diode <NUM> in sequence.

In some embodiments, the bonding layer <NUM> and/or the bonding layer <NUM> may be removed according to the demands. In some embodiments, not forming part of the claimed invention, one of the solder <NUM> and the conductive structure <NUM> may be removed according to the demands. In some embodiments, not forming part of the claimed invention, one of the solder <NUM> and the conductive structure <NUM> may be removed according to the demands.

Referring to <FIG> schematically illustrates the solder before mixing according to the second embodiment of the present disclosure. Different from the first embodiment, in some embodiments (shown in <FIG>),the solder <NUM> and the solder <NUM> may be a stacked layer formed of a plurality of first conductive layers <NUM> and a plurality of second conductive layers <NUM> which are alternatively stacked. In other word, the solder <NUM> or the solder <NUM> is formed by stacking a plurality of first conductive layers <NUM> and a plurality of second conductive layers <NUM> alternatively. The first conductive layer <NUM> may include tin, and the second conductive layer <NUM> may include indium, bismuth or other suitable materials, but not limited thereto. The first conductive layers <NUM> and the second conductive layers <NUM> include different materials. The alternatively stacked first conductive layers <NUM> and second conductive layers <NUM> form an alloy or compound (such as the solder <NUM> in the first embodiment) through the thermal bonding or annealing. In some embodiments, the thicknesses of different first conductive layers <NUM> may be the same or different, and the thicknesses of different second conductive layers <NUM> may be the same or different. The percentage of each of the elements in the solder <NUM> and the solder <NUM> may be adjusted by adjusting the number and/or the thicknesses of the first conductive layers <NUM> and the number and/or the thicknesses of the second conductive layers <NUM>, but not limited thereto. In some embodiments, a first conductive layer <NUM> and a second conductive layer <NUM> may be stacked to form the solder, but not limited thereto.

Referring to <FIG> schematically illustrates a side view of the electronic device after bonding according to the second embodiment of the present disclosure. Different from the first embodiment, at least a portion of the solder and at least a portion of the conductive structure (such as gold layer or the conductive layer including gold) are mixed to form the solder alloy in some embodiments (as shown in <FIG>), that is, the solder alloy <NUM> includes gold, and the alloy having the atomic percentage of tin in the sum of tin and the metal element M in a range from <NUM>% to <NUM>% is defined as the solder alloy <NUM>. According to the invention, a portion of the solder which does not form the solder alloy <NUM> is a layer <NUM>, a portion of the conductive structure which does not form the solder alloy <NUM> is a first layer <NUM> (a gold layer or the layer including gold) and the thicknesses (and materials) of the layer <NUM> and the thicknesses (and materials) the first layer <NUM> may be the same or different, but not limited thereto. According to the invention, (shown in <FIG>), the layer <NUM> and the first layer <NUM> may be respectively located at two opposite sides of the solder alloy <NUM>, which is shown in the left part of the stacked structure. According to the invention the first layer <NUM> is disposed between the solder alloy <NUM> and the substrate <NUM>, and the layer <NUM> may be disposed between the solder alloy <NUM> and the light emitting diode <NUM>. In some embodiments, the positions of the layer <NUM> and the first layer <NUM> may be exchanged. In some embodiments (shown in <FIG>), the first layers <NUM> (gold layers or the conductive layers including gold) are located at two opposite sides of the solder alloy <NUM>, which is shown in the right part of the stacked structure. For example, the first layer <NUM> may be disposed between the solder alloy <NUM> and the substrate <NUM>, another first layer <NUM> may be dispose between the solder layer <NUM> and the light emitting diode <NUM>, and the materials and thicknesses of these first layers <NUM> may be the same or different. In some embodiment (not shown), the layers <NUM> may be disposed at two opposite sides of the solder alloy <NUM>. For example, one of the layers <NUM> may be disposed between the solder alloy <NUM> and the substrate <NUM>, the other one of the layers <NUM> may be dispose between the solder layer <NUM> and the light emitting diode <NUM>, and the materials and thicknesses of these layers <NUM> may be the same or different. It should be noted that, the stacked structure in the left part and the stacked structure in the right part in <FIG> are only illustrative in order to clarify different stacked conditions, and the stacked structure in the left part is not limited to be different from the stacked structure in the right part. In some embodiments, the stacked structure in the left part and the stacked structure in the right part may be the same.

Referring to <FIG> schematically illustrates a side view of the electronic device after bonding according to the third embodiment of the present disclosure. Different from the first embodiment, the electronic device <NUM> may include layer <NUM>, but the electronic device <NUM> does not include first layers <NUM> after bonding in some embodiments (as shown in <FIG>). For example, the electronic device <NUM> may include layer <NUM>, and the layer <NUM> may be disposed between the solder alloy <NUM> and the substrate <NUM>, or the layer <NUM> may be disposed between the solder alloy <NUM> and the light emitting diode <NUM>. In some embodiments (not shown), the electronic device may include the first layer <NUM>, but the electronic device does not include the layer <NUM>, and the first layer <NUM> (a gold layer or the layer including gold) may be disposed between the solder alloy <NUM> and the light emitting diode <NUM>, or the first layer <NUM> (a gold layer or the layer including gold) is disposed between the solder alloy <NUM> and the substrate <NUM>. In some embodiments (not shown), the number of the layer <NUM> may be greater than or equal to <NUM>, the number of the first layer <NUM> may be greater than or equal to <NUM>, and/or the number of the solder alloy <NUM> may be greater than or equal to <NUM>, but not limited thereto. The relative positions of the layer <NUM>, the first layer <NUM>, and the solder alloy <NUM> may be adjusted according to the bonding condition, and the present disclosure is not limited thereto.

Referring to <FIG> schematically illustrates a side view of the electronic device before bonding according to the third embodiment of the present disclosure. Different from the first embodiment, in some embodiments (as shown in <FIG>) the bonding layer <NUM>, the conductive structure <NUM>, the solder <NUM>, and the conductive structure <NUM> may be formed or disposed on the light emitting diode <NUM> in sequence, and the bonding layer <NUM>, the conductive structure <NUM>, the solder <NUM> and the conductive structure <NUM> may be formed or disposed on the substrate <NUM> in sequence, but not limited thereto. Other suitable layers (such as other conductive structures or other solders, but not limited thereto) may be intervened or added between the above-mentioned components or layers according to the demands, or the bonding layers or the metal layers may be removed according to the demands. In some embodiments (as shown in <FIG>), the thicknesses of the conductive structure <NUM>, the conductive structure <NUM>, the conductive structure <NUM>, and/or the conductive structure <NUM> may be less than or equal to the thicknesses of the solder <NUM>, the solder <NUM>, the bonding layer <NUM>, and/or the bonding layer <NUM>, but not limited thereto. In some embodiments, the thicknesses of the conductive structure <NUM>, the conductive structure <NUM>, the conductive structure <NUM> and/or the conductive structure <NUM> may be the same or different. In some embodiments, the materials of the conductive structure <NUM>, the conductive structure <NUM>, the conductive structure <NUM>, and/or the conductive structure <NUM> may be the same or different.

According to the above-mentioned contents, in an embodiment of the present disclosure, the method of manufacturing an electronic device includes providing a substrate (such as the substrate <NUM>), forming the solder (such as the solder <NUM>) on the substrate, and bonding the light emitting diode (such as the light emitting diode <NUM>) to the substrate through the solder. The solder is formed by stacking a plurality of first conductive layers <NUM> and a plurality of second conductive layers <NUM> alternatively, and as mentioned above, the plurality of first conductive layers <NUM> and the plurality of second conductive layers <NUM> include different materials.

In another embodiment, the method of manufacturing an electronic device includes providing a light emitting diode (such as the light emitting diode <NUM>), forming the solder (such as the solder <NUM>) on the light emitting diode, and bonding the substrate (such as the substrate <NUM>) to the light emitting diode through the solder. The solder is formed by stacking a plurality of first conductive layers <NUM> and a plurality of second conductive layers <NUM> alternatively, and the first conductive layers <NUM> and the second conductive layers <NUM> include different materials.

Referring to <FIG> and <FIG>, <FIG> schematically illustrates a side view of the electronic device measured by an energy dispersive spectrometer, <FIG> schematically illustrates the analysis result of the solder alloy along the arrow shown in <FIG>. The measurement may be conducted along the direction of the arrow shown in <FIG>, but not limited thereto. The location and direction of the measurement may be adjusted according to the demands. <FIG> schematically illustrates a relation chart between the intensity (cps) and the distance (µm) measured by EDS. In some embodiments (as shown in <FIG>), the measurement is performed from the layer (or component) nearest to the light emitting diode <NUM> (such as the bonding layer <NUM>) to the layer (or component) nearest to the substrate <NUM> (such as the bonding layer <NUM>). For example, the content or percentage of each of the elements in the bonding layer <NUM>, the first layer <NUM>, the solder alloy <NUM>, the layer <NUM> and the bonding layer <NUM> are measured in sequence to obtain the relation chart between the intensity (cps) and the distance (shown in <FIG>). The alloy having the atomic percentage of tin in the sum of tin and the metal element M (such as one of indium and bismuth) ranging from <NUM>% to <NUM>% is defined as the solder alloy <NUM>. The line <NUM>-c1 and the line <NUM>-c2 in <FIG> may be used to define the region of the solder alloy <NUM>. In addition, although the present disclosure only illustrates one calculation method of the atomic percentage of tin in the sum of tin and metal element M, it is not limited thereto. For example (shown in <FIG>), the calculation is performed on the solder alloy <NUM> in which the distance is <NUM> micrometers (µm), the intensity (cps) of tin in this position is about <NUM>, the intensity (cps) of indium in this position is about <NUM>, and the result of the atomic percentage of tin in the sum of tin and indium may be obtained after substituting the values into the equation, which is <NUM>%, such as ((Sn/(Sn+In)=<NUM>/(<NUM>+<NUM>)=<NUM>=<NUM>%). In some embodiments, the compartment line between different layers is defined by the intersection of the curves of two different elements. As shown in <FIG>, a line <NUM>-c is drawn through the intersection of the curves of two elements (such as nickel and tin), and a line <NUM>-c is drawn through the intersection of the curves of two elements (such as nickel and gold). The region between the line <NUM>-c and the line <NUM>-c1 is the first layer <NUM>, the region between the line <NUM>-c and the line <NUM>-c2 is the layer <NUM>, another part (the part different from the first layer <NUM>) using the line <NUM>-c as the compartment line may represent the bonding layer <NUM>, and another part (the part different from the layer <NUM>) using the line <NUM>-c as the compartment line may represent the bonding layer <NUM>, but not limited thereto. In some embodiments, the comparison may be performed according to the materials of the bonding layers, the conductive structures, and the solder combined with the result of analysis, and the regions of the solder alloy <NUM>, the layer <NUM>, the first layer <NUM>, the bonding layer <NUM>, and/or the bonding layer <NUM> may be defined by the above-mentioned method, but not limited thereto.

In some embodiments (referring to <FIG>), when the material of the bonding layer <NUM> includes titanium and nickel, and the material of the solder includes tin and indium, the line <NUM>-c may be drawn through the intersection of the curves of nickel and tin, but not limited thereto. In some embodiments (referring to <FIG>), when the material of the bonding layer <NUM> includes titanium and nickel, and the material of the conductive structure includes gold, the line <NUM>-c may be drawn through the intersection of the curves of nickel and gold, but not limited thereto.

It should be noted that the measuring method in the present disclosure is not limited to be performed along the direction of the arrow shown in <FIG>. In some embodiments (not shown), the measurement may be performed from the layers (or components) nearest to the substrate <NUM> to the layers (or components) nearest to the light emitting diode <NUM> (such as the bonding layer <NUM>), or the measurement may be performed at any random position. It should be noted that, the corresponding distance of each of the layers shown in <FIG> is only illustrative. In some embodiments, the thickness of the bonding layer <NUM> or the bonding layer <NUM> may be greater than the thicknesses of the solder alloy <NUM>, the layer <NUM>, and/or the first layer <NUM>. It should be noted that, <FIG> only illustrates one of the possible results, and the percentage of the elements in different layers may be different according to the number, thickness, material, or bonding temperature of the bonding layer, the metal layer, and the solder, but not limited thereto.

Similarly, the percentage of the elements in each of the layers (not limited to before bonding or after bonding) according to the embodiments may be analyzed by the similar way.

Claim 1:
An electronic device (<NUM>), comprising:
a substrate (<NUM>);
a light emitting diode (<NUM>) bonded to the substrate (<NUM>) through a solder alloy (<NUM>);
wherein the solder alloy (<NUM>) includes tin, gold, and a metal element M, the metal element M is one of indium and bismuth, and the atomic percentage of tin in sum of the tin and the metal element M is in a range from <NUM>% to <NUM>% in the solder alloy (<NUM>);
a first layer (<NUM>) disposed between the solder alloy (<NUM>) and the substrate (<NUM>); and
a second layer (<NUM>) disposed between the solder alloy (<NUM>) and the light emitting diode (<NUM>),
wherein the first layer (<NUM>) and the second layer (<NUM>) comprise gold, a content of gold in the first layer (<NUM>) is greater than a content of gold in the solder alloy (<NUM>), and the content of gold in the solder alloy (<NUM>) is greater than a content of gold in the second layer (<NUM>),
wherein the first layer (<NUM>) and the second layer (<NUM>) comprise tin, a content of tin in the second layer (<NUM>) is greater than a content of tin in the solder alloy (<NUM>), and the content of tin in the solder alloy (<NUM>) is greater than a content of tin in the first layer (<NUM>).