Patent Description:
The present disclosure relates to the technical field of semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof.

In the packaging process of an existing memory thin die stack, a die, an adhesive layer and a solder mask (SR for short, alias "green mask") on a substrate are in direct contact with each other. In the art, the substrate (including the solder mask) and the die are designed thinner and thinner. When the die bends itself, or deforms due to external force, or undergoes temperature cycling reliability (TC reliability) detection, an edge position where the die is connected with the substrate is prone to die crack or substrate crack due to stress concentration. <CIT> describes a semiconductor package structure using a lead frame, an adhesive layer, and a molding compound. The adhesive layer connects the die to the lead frame and covers sharp corners to mitigate stress.

One aspect of the embodiments of the present disclosure provides a semiconductor structure, including a substrate, a die and a first adhesive layer, wherein a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one hole slot, the hole slot being defined as a recess, trench or void in the insulation layer, with a geometry corresponding to an edge of the first adhesive layer; a position of the at least one hole slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one hole slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.

Another aspect of the embodiments of the present disclosure provides a method of manufacturing a semiconductor structure, including: providing a substrate, wherein a surface of the substrate is provided with an insulation layer; forming at least one hole slot which runs through the insulation layer on the insulation layer; forming a second adhesive layer in the at least one hole slot; arranging a die on a surface of the insulation layer via a first adhesive layer, wherein a position of the at least one hole slot corresponds to at least a part of an edge of the first adhesive layer, at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer; and forming a packaging layer on the surface of the insulation layer, wherein the die and the first adhesive layer are packaged in the packaging layer.

Exemplary embodiments will be described below more comprehensively with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in a plurality of forms and should not be construed as being limited to embodiments described herein. On the contrary, these embodiments are provided such that the present disclosure is more comprehensive and complete, and fully conveys the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures indicate the same or similar structures, and thus their detailed descriptions will be omitted.

Referring to <FIG> representatively shows a schematic structure of a semiconductor structure proposed by the present disclosure. In the exemplary embodiment, the semiconductor structure proposed by the present disclosure is described by taking its application to a packaging structure of a memory thin die stack as an example. It is understandable for those skilled in the art that, in order to apply the relevant design of the present disclosure to other types of semiconductor structures, various modifications, additions, substitutions, deletions or other changes may be made to the following specific embodiments, but such changes are still within the scope of the principle of the semiconductor structure proposed by the present disclosure.

As shown in <FIG>, in the embodiment, the semiconductor structure proposed by the present disclosure mainly includes a substrate <NUM>, a die <NUM> and a first adhesive layer <NUM>. Specifically, a surface of the substrate <NUM> is provided with an insulation layer <NUM>. The die <NUM> is arranged on a surface of the insulation layer <NUM> via the first adhesive layer <NUM>. The insulation layer <NUM> is provided with at least one hole slot <NUM>, and a position of the at least one hole slot <NUM> corresponds to an edge of the first adhesive layer <NUM>. And, a second adhesive layer <NUM> is arranged in the at least one hole slot <NUM>, and at least a part of a surface of the second adhesive layer <NUM> is connected with the first adhesive layer <NUM>. On this basis, an elasticity modulus of the second adhesive layer <NUM> is smaller than an elasticity modulus of the first adhesive layer <NUM>. Via the above design, the semiconductor structure proposed by the present disclosure can optimize the stress distribution of an edge where the die <NUM> is connected with the substrate <NUM> (including the insulation layer <NUM> arranged on the surface of the substrate <NUM>), such that the semiconductor structure is difficult to generate crack at the edge where the die <NUM> is connected with the substrate <NUM> during bending or deformation.

Optionally, referring to <FIG>, in the embodiment, the at least one hole slot <NUM> may run through the insulation layer <NUM>. In other embodiments, the at least one hole slot <NUM> may also not run through the insulation layer <NUM>, for example, the at least one hole slot <NUM> is only opened on an upper surface of the insulation layer <NUM>.

Optionally, referring to <FIG> representatively shows a top view of the semiconductor structure in forming the at least one hole slot <NUM>, and in the embodiment, one hole slot of the at least one hole slot <NUM> may approximately be an annular closed structure, such that the hole slot of the at least one hole slot <NUM> corresponds to the whole edge of the first adhesive layer <NUM>. Via the above design, the semiconductor structure proposed by the present disclosure can optimize the stress distribution of the whole position of the edge where the die <NUM> is connected with the substrate <NUM>, such that the whole edge where the die <NUM> is connected with the substrate <NUM> is difficult to generate crack.

Further, referring to <FIG>, based on the design that the hole slot of the at least one hole slot <NUM> is an annular closed structure, in the embodiment, the first adhesive layer <NUM> may be approximately rectangular and the edge of the first adhesive layer <NUM> has four side edges. On this basis, the hole slot of the at least one hole slot <NUM> may be approximately arranged in a form of a rectangular ring. In other embodiments, based on the design that the hole slot of the at least one hole slot <NUM> corresponds to the whole edge of the first adhesive layer <NUM>, when the first adhesive layer <NUM> is in a shape of a circle, a triangle, a trapezoid or the like, the hole slot of the at least one hole slot <NUM> may be arranged in corresponding forms of a circular ring, a triangular ring, a trapezoidal ring and the like, which is not limited to the embodiment.

Optionally, as shown in <FIG>, in the embodiment, on the surface of the substrate <NUM>, an outer side edge of an orthographic projection of the at least one hole slot <NUM> may be located outside an edge of an orthographic projection of the first adhesive layer <NUM>. Accordingly, the second adhesive layer <NUM> arranged in the at least one hole slot <NUM> can extend to an outer side of the edge of the first adhesive layer <NUM>, such that the present disclosure can optimize the stress distribution of a part of a region, located on the outer side of the edge of the first adhesive layer <NUM>, of the substrate <NUM>, thereby further preventing crack of a relevant region.

Optionally, referring to <FIG> representatively shows a schematic structure of the semiconductor structure in arranging the die <NUM>, and in the embodiment, a notch width d1 of the at least one hole slot <NUM> may be <NUM>%-<NUM>% of a width d2 of the first adhesive layer <NUM>, for example, <NUM>%, <NUM>%, <NUM>% and <NUM>%. Accordingly, the present disclosure selects a width proportion of the hole <NUM> to the first adhesive layer <NUM> as a reasonable scope, thereby preventing the die <NUM> from overall viscosity inefficiency due to excessive notch width d1 of the at least one hole slot <NUM>, and preventing the condition that the effects of better stress distribution optimization and crack prevention cannot be realized due to too small notch width d1 when the semiconductor structure deforms. In other embodiments, the notch width d1 of the at least one hole slot <NUM> may be smaller than <NUM>% or greater than <NUM>% of the width d2 of the first adhesive layer <NUM>, for example, <NUM>%, <NUM>% and the like, which is not limited to the embodiment.

Optionally, in the embodiment, the elasticity modulus of the second adhesive layer <NUM> may be smaller than the elasticity modulus of the insulation layer <NUM>. Accordingly, a corresponding position (for example, a position adjoining the at least one hole slot <NUM>, namely, a position corresponding to the edge of the first adhesive layer <NUM>) of the insulation layer <NUM> may be difficult to generate crack. In other embodiments, on the basis of ensuring that the elasticity modulus of the second adhesive layer <NUM> is smaller than the elasticity modulus of the first adhesive layer <NUM>, the elasticity modulus of the second adhesive layer <NUM> may also be equal to or greater than the elasticity modulus of the insulation layer <NUM>, which is not limited to the embodiment.

Optionally, in the embodiment, the elasticity modulus of the second adhesive layer <NUM> may be smaller than the elasticity modulus of the die <NUM>. Accordingly, a corresponding position (for example, an edge position) of the die <NUM> may be difficult to generate crack. In other embodiments, on the basis of ensuring that the elasticity modulus of the second adhesive layer <NUM> is smaller than the elasticity modulus of the first adhesive layer <NUM>, the elasticity modulus of the second adhesive layer <NUM> may also be equal to or greater than the elasticity modulus of the die <NUM>, which is not limited to the embodiment.

Optionally, in the embodiment, a coefficient of thermal expansion of the second adhesive layer <NUM> may be smaller than a coefficient of thermal expansion of the first adhesive layer <NUM>. Accordingly, when the semiconductor structure is heated to deform, as the second adhesive layer <NUM> has a lower coefficient of thermal expansion relative to the first adhesive layer <NUM>, the first adhesive layer <NUM> can be prevented from crack caused by generating, by the second adhesive layer, same or even larger expansive deformation as the first adhesive layer <NUM>. In other embodiments, under the premise of ensuring that the present disclosure optimizes the stress distribution of a relevant position via the arrangement of the second adhesive layer <NUM>, the coefficient of thermal expansion of the second adhesive layer <NUM> may also be greater than or equal to the coefficient of thermal expansion of the first adhesive layer <NUM>, which is not limited to the embodiment.

Further, based on the design that the coefficient of thermal expansion of the second adhesive layer <NUM> is smaller than the coefficient of thermal expansion of the first adhesive layer <NUM>, in the embodiment, the coefficient of thermal expansion of the second adhesive layer <NUM> may also be smaller than the coefficient of thermal expansion of the insulation layer <NUM>. Accordingly, when the semiconductor structure is heated to deform, as the second adhesive layer <NUM> has a lower coefficient of thermal expansion relative to the insulation layer <NUM>, the insulation layer <NUM> may be prevented from crack caused by generating, by the second adhesive layer <NUM>, same or even larger expansive deformation as the insulation layer <NUM>. In other embodiments, on the basis that the coefficient of thermal expansion of the second adhesive layer <NUM> is smaller than the coefficient of thermal expansion of the first adhesive layer <NUM>, the coefficient of thermal expansion of the second adhesive layer <NUM> may also be greater than or equal to the coefficient of thermal expansion of the insulation layer <NUM>, which is not limited to the embodiment.

Further, based on the design that the coefficient of thermal expansion of the second adhesive layer <NUM> is smaller than the coefficient of thermal expansion of the first adhesive layer <NUM>, in the embodiment, the coefficient of thermal expansion of the second adhesive layer <NUM> may also be smaller than the coefficient of thermal expansion of the die <NUM>. Accordingly, when the semiconductor structure is heated to deform, as the second adhesive layer <NUM> has a lower coefficient of thermal expansion relative to the die <NUM>, the die <NUM> may be prevented from crack caused by generating, by the second adhesive layer, same or even larger expansive deformation as the die <NUM>. In other embodiments, on the basis that the coefficient of thermal expansion of the second adhesive layer <NUM> is smaller than the coefficient of thermal expansion of the first adhesive layer <NUM>, the coefficient of thermal expansion of the second adhesive layer <NUM> may also be greater than or equal to the coefficient of thermal expansion of the die <NUM>, which is not limited to the embodiment.

Optionally, in the embodiment, a bonding strength between the first adhesive layer <NUM> and the second adhesive layer <NUM> may be smaller than a bonding strength between the first adhesive layer <NUM> and the die <NUM>. Accordingly, when the semiconductor structure deforms, by utilizing the above bonding strength design, the separation of the second adhesive layer <NUM> from the first adhesive layer <NUM> may be earlier than the separation of the first adhesive layer <NUM> from the die <NUM>, therefore, when the deformation is too large to generate thin film structure separation, the separation of the second adhesive layer <NUM> from the first adhesive layer <NUM> can be utilized to prevent or slow down the separation of the first adhesive layer <NUM> from the die <NUM>. In other embodiments, under the premise of ensuring that the present disclosure optimizes the stress distribution of a relevant position via the arrangement of the second adhesive layer <NUM>, the bonding strength between the first adhesive layer <NUM> and the second adhesive layer <NUM> may also be greater than or equal to the bonding strength between the first adhesive layer <NUM> and the die <NUM>, which is not limited to the embodiment.

Optionally, in the embodiment, the bonding strength between the first adhesive layer <NUM> and the second adhesive layer <NUM> may be smaller than a bonding strength between the first adhesive layer <NUM> and the insulation layer <NUM>. Accordingly, when the semiconductor structure deforms, by utilizing the above bonding strength design, the separation of the second adhesive layer <NUM> from the first adhesive layer <NUM> may be earlier than the separation of the first adhesive layer <NUM> from the insulation layer <NUM>, therefore, when the deformation is too large to generate thin film structure separation, the separation of the second adhesive layer <NUM> from the first adhesive layer <NUM> can be utilized to prevent or slow down the separation of the first adhesive layer <NUM> from the insulation layer <NUM>. In other embodiments, under the premise of ensuring that the present disclosure optimizes the stress distribution of the relevant position via the arrangement of the second adhesive layer <NUM>, the bonding strength between the first adhesive layer <NUM> and the second adhesive layer <NUM> may also be greater than or equal to the bonding strength between the first adhesive layer <NUM> and the insulation layer <NUM>, which is not limited to the embodiment.

Optionally, in the embodiment, the material of the second adhesive layer <NUM> may include silicone gel, epoxy resin adhesive (for example, organosilicon epoxy resin adhesive, Silicon epoxy) and the like.

Based on the above detailed description of the first embodiment of the semiconductor structure proposed by the present disclosure, a second embodiment of the semiconductor structure proposed by the present disclosure will be described below in combination with <FIG>.

Referring to <FIG> representatively shows a top view of the semiconductor structure in forming the at least one hole slot <NUM> in the second embodiment. In the second embodiment, the semiconductor structure proposed by the present disclosure adopts a design approximately same as a design of the first embodiment described above, and the design of the second embodiment different from the design of the first embodiment will be described below.

As shown in <FIG>, in the embodiment, the position of the at least one hole slot <NUM> corresponds to a part of the edge of the first adhesive layer <NUM>. Accordingly, the present disclosure can optimize the stress distribution of a part of the position of the edge where the die <NUM> is connected with the substrate <NUM>, such that a part of the edge where the die <NUM> is connected with the substrate <NUM> is difficult to generate crack. In other words, in various possible embodiments consistent with the design concept of the semiconductor structure proposed by the present disclosure, the position of the at least one hole slot <NUM> may correspond to at least a part of the edge of the first adhesive layer <NUM>, such that the present disclosure can optimize the stress distribution of at least a part of the position of the edge where the die <NUM> is connected with the substrate <NUM>.

Optionally, as shown in <FIG>, based on the design that the position of the at least one hole slot <NUM> corresponds to a part of the edge of the first adhesive layer <NUM>, in the embodiment, when the first adhesive layer <NUM> is approximately rectangular, the at least one hole slot <NUM> corresponds to one, two or three side edges of the rectangle. Certainly, the at least one hole slot <NUM> may also correspond to a part of any side edge, or the at least one hole slot <NUM> may also correspond to four corner parts of the rectangle, separately, both of which are not limited to the embodiment.

Based on the above detailed description of the first embodiment of the semiconductor structure proposed by the present disclosure, a third embodiment of the semiconductor structure proposed by the present disclosure will be described below in combination with <FIG>.

Referring to <FIG> representatively shows a schematic structure of the semiconductor structure in the third embodiment. In the third embodiment, the semiconductor structure proposed by the present disclosure adopts a design approximately same as a design of the first embodiment described above, and the design of the third embodiment different from the design of the first embodiment will be described below.

As shown in <FIG>, in the embodiment, on the surface of the substrate <NUM>, an orthographic projection of the at least one hole slot <NUM> is fully covered by an orthographic projection of the first adhesive layer <NUM>, such that the whole surface of the second adhesive layer <NUM> is connected with the first adhesive layer <NUM>. In other words, in various possible embodiments consistent with the design concept of the semiconductor structure proposed by the present disclosure, at least a part of the surface of the second adhesive layer <NUM> is connected with the first adhesive layer <NUM>.

Further, as shown in <FIG>, based on the design that the orthographic projection of the at least one hole slot <NUM> is fully covered by the orthographic projection of the first adhesive layer <NUM>, on the surface of the substrate <NUM>, an outer side edge of the orthographic projection of the at least one hole slot <NUM> may coincide with an edge of the orthographic projection of the first adhesive layer <NUM>.

Based on the above detailed description of the first embodiment of the semiconductor structure proposed by the present disclosure, a fourth embodiment of the semiconductor structure proposed by the present disclosure will be described below in combination with <FIG>.

Referring to <FIG> representatively shows a schematic structure of the semiconductor structure in the fourth embodiment. In the fourth embodiment, the semiconductor structure proposed by the present disclosure adopts a design approximately same as a design of the first embodiment described above, and the design of the fourth embodiment different from the design of the first embodiment will be described below.

As shown in <FIG>, in the embodiment, the die <NUM> may adopt a multilayer stack structure, namely, the die includes a plurality of bare dies <NUM> of an alternate stack and a die attach film <NUM> (DAF for short). On this basis, the die <NUM> is still arranged on the first adhesive layer <NUM> as an integral structure, and specifically, the bare die <NUM> located at the lowest layer is arranged on the first adhesive layer <NUM>.

For example, the semiconductor structure proposed by the present disclosure may include a packaging layer <NUM>, which is arranged on a surface of the substrate and internally packages the die <NUM> and the first adhesive layer <NUM>.

For another example, the bare die <NUM> of the die <NUM> is bonded with the substrate <NUM> via a bonding wire <NUM>.

Based on the above detailed description of several exemplary embodiments of the semiconductor structure proposed by the present disclosure, an exemplary embodiment of a method of manufacturing the semiconductor structure proposed by the present disclosure will be described below in combination with <FIG>.

Referring to <FIG>, <FIG> and <FIG> representatively show schematic structures of the semiconductor structure in a plurality of steps of the method of manufacturing the semiconductor structure proposed by the present disclosure, respectively. In the exemplary embodiment, the method of manufacturing the semiconductor structure proposed by the present disclosure is described by taking the method of manufacturing the packaging structure applied to a memory thin die stack as an example. It is understandable for those skilled in the art that, in order to apply the relevant design of the present disclosure to other types of semiconductor structures, various modifications, additions, substitutions, deletions or other changes may be made to the following specific embodiments, but such changes are still within the scope of the principle of the method of manufacturing the semiconductor structure proposed by the present disclosure.

As shown in <FIG>, referring to <FIG>, in the embodiment, the method of manufacturing the semiconductor structure proposed by the present disclosure mainly includes:.

Via the above design, the method of manufacturing the semiconductor structure proposed by the present disclosure can optimize the stress distribution of an edge where the die <NUM> is connected with the substrate <NUM> (including the insulation layer <NUM> arranged on the surface of the substrate <NUM>), such that the semiconductor structure is difficult to generate crack at the edge where the die <NUM> is connected with the substrate <NUM> during bending or deformation.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "providing a substrate <NUM>". In the above step, the semiconductor structure includes the substrate <NUM> and the insulation layer <NUM>. The insulation layer <NUM> is arranged on a surface of the substrate <NUM>. It is understandable that in some of the description of the Description, the insulation layer <NUM> is overall described as a part of the substrate <NUM>, and in a practical process, a finished substrate having the insulation layer <NUM> can be directly manufactured without departing from the relevant design concept of the present disclosure.

Optionally, as shown in <FIG>, referring to <FIG>, in the embodiment, the forming the at least one hole slot <NUM> may specifically include:.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "arranging the photoresist <NUM>". In the above step, the semiconductor structure includes the substrate <NUM>, the insulation layer <NUM> and the photoresist <NUM>. The photoresist <NUM> is coated on the surface of the insulation layer <NUM>.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "patterning the photoresist <NUM>". In the above step, the semiconductor structure includes the substrate <NUM>, the insulation layer <NUM> and the patterned photoresist <NUM>. The part, removed via the patterning process, of the photoresist <NUM> corresponds to a position, needing to arrange the at least one hole slot <NUM>, on the insulation layer <NUM>.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "performing exposure by using the photoresist <NUM> to remove a part of the insulation layer <NUM>". In the above step, the semiconductor structure includes the substrate <NUM> and the remaining insulation layer <NUM> after the part is removed. The part, not shielded by the photoresist <NUM>, of the insulation layer <NUM> is removed to form the at least one hole slot <NUM> which runs through the insulation layer <NUM>, and so far, a process of transferring a pattern of the photoresist <NUM> onto the insulation layer <NUM> is finished.

As shown in <FIG> representatively shows a top view of the semiconductor structure in the "performing exposure by using the photoresist <NUM> to remove a part of the insulation layer <NUM>". The embodiment is described by taking the hole slot of the at least one hole slot <NUM> approximately being an annular closed structure, namely, the hole slot of the at least one hole slot <NUM> corresponding to the whole edge of the die <NUM> (the first adhesive layer <NUM>) as an example, therefore, in order to ensure that the hole slot of the at least one hole slot <NUM> is approximately arranged in a form of a rectangle as shown in <FIG>, a patterned opening of the photoresist <NUM> may also be approximately rectangular. In other embodiments, when the at least one hole slot <NUM> in other arrangement forms needs to be formed, for example, the arrangement form of the hole slots of the at least one hole slot <NUM> as shown in <FIG>, the patterned opening of the photoresist <NUM> may also be correspondingly adjusted, which is not limited to the embodiment.

Optionally, as shown in <FIG>, referring to <FIG>, in the embodiment, the forming the second adhesive layer <NUM> may specifically include:.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "applying drop coats of a buffer adhesive material into the at least one hole slot <NUM>". In the above step, the semiconductor structure includes the substrate <NUM>, the insulation layer <NUM> and the buffer adhesive material, the drop coats of the buffer adhesive material are being applied into the at least one hole slot <NUM> of the insulation layer <NUM>. The buffer adhesive material may be filled in the at least one hole slot <NUM> in a drop coat applying manner via an adhesive coating device <NUM>, so as to ensure that the at least one hole slot <NUM> may be sufficiently filled and to optimize the material uniformity and compactness of the second adhesive layer <NUM> formed by a subsequent process, thereby further improving the effect of optimizing the stress distribution. In other embodiments, the buffer adhesive material may also be filled in the at least one hole slot <NUM> in other coating manners, which is not limited to the embodiment.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "performing heating for baking, such that the buffer adhesive material is cured to form the second adhesive layer <NUM>". In the above step, the semiconductor structure includes the substrate <NUM>, the insulation layer <NUM> and the cured second adhesive layer <NUM>. The second adhesive layer <NUM> is formed via heating and curing the buffer adhesive material filled in the at least one hole slot <NUM> by a heating device <NUM>. The heating device <NUM> may be, for example, an oven and the like.

Optionally, as shown in <FIG>, in the embodiment, the arrangement of the die <NUM> may specifically include:.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "laminating the first adhesive layer <NUM> and the die <NUM> on the substrate <NUM>". In the above step, the semiconductor structure includes the substrate <NUM>, the insulation layer <NUM>, the second adhesive layer <NUM>, the first adhesive layer <NUM> and the die <NUM>. The first adhesive layer <NUM> is located on the surface of the insulation layer <NUM>, the die <NUM> is located on the surface of the first adhesive layer <NUM>, and the first adhesive layer <NUM> and the die <NUM> may be laminated on the surface of the substrate <NUM> (actually the insulation layer <NUM>) via a pressing device <NUM>.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "performing heating for baking, such that the first adhesive layer <NUM> is cemented between the die <NUM> and the substrate <NUM>". In the above step, the semiconductor structure includes the substrate <NUM>, the insulation layer <NUM>, the second adhesive layer <NUM>, the first adhesive layer <NUM> and the die <NUM>. Via the heating of the heating device <NUM>, the first adhesive layer <NUM> may cement the die <NUM> on the substrate <NUM>.

Further, in the embodiment, for the "performing heating for baking, such that the buffer adhesive material is cured to form the second adhesive layer <NUM>" and "performing heating for baking, such that the first adhesive layer <NUM> is cemented between the die <NUM> and the substrate <NUM>", the heating device <NUM> and the heating device <NUM> in the above two steps may adopt a same heating device. On this basis, differed from the heating step of arranging the die <NUM> to cure the first adhesive layer <NUM>, the performing heating for baking so as to cure and form the second adhesive layer <NUM> may also be understood as "pre-baking". Accordingly, via the "pre-baking", the second adhesive layer <NUM> can be formed via curing, and a loading device of the semiconductor structure can be pre-heated.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "bonding the die <NUM> with the substrate <NUM>". In the above step, the semiconductor structure includes the substrate <NUM>, the insulation layer <NUM>, the second adhesive layer <NUM>, the first adhesive layer <NUM>, the die <NUM> and a bonding wire <NUM>. The bonding wire <NUM> is connected between the die <NUM> and the substrate <NUM> to realize the bonding between the die <NUM> and the substrate <NUM>.

As shown in <FIG> representatively shows a schematic structure of the semiconductor structure in the "forming a packaging layer <NUM> on the surface of the insulation layer <NUM>". In the above step, the semiconductor structure includes the substrate <NUM>, the insulation layer <NUM>, the second adhesive layer <NUM>, the first adhesive layer <NUM>, the die <NUM>, the bonding wire <NUM> and the packaging layer <NUM>. The packaging layer <NUM> is formed on the surface of the substrate <NUM>, and internally packages each structure on the substrate <NUM>, such as the first adhesive layer <NUM>, the second adhesive layer <NUM>, the die <NUM>, the bonding wire <NUM> and the like.

To sum up, by arranging the at least one hole slot corresponding to the position of at least a part of the edge of the first adhesive layer at the insulation layer and arranging the second adhesive layer having the elasticity modulus smaller than the elasticity modulus of the first adhesive layer in the at least one hole slot, the semiconductor structure and the method of manufacturing the semiconductor structure proposed by the present disclosure can optimize the stress distribution of the edge where the die is connected with the substrate, such that the semiconductor structure is difficult to generate crack at the edge where the die is connected with the substrate during bending or deformation.

Claim 1:
A semiconductor structure comprising a substrate (<NUM>), a die (<NUM>) and a first adhesive layer (<NUM>), wherein a surface of the substrate (<NUM>) is provided with an insulation layer (<NUM>); the die (<NUM>) is arranged on a surface of the insulation layer (<NUM>) via the first adhesive layer (<NUM>);
characterised in that the insulation layer (<NUM>) is provided with at least one hole slot (<NUM>), the hole slot being defined as a recess, trench or void in the insulation layer, with a geometry corresponding to an edge of the first adhesive layer; a position of the at least one hole slot (<NUM>) corresponds to at least a part of an edge of the first adhesive layer (<NUM>); a second adhesive layer (<NUM>) is arranged in the at least one hole slot (<NUM>); at least a part of a surface of the second adhesive layer (<NUM>) is connected with the first adhesive layer (<NUM>); and
an elasticity modulus of the second adhesive layer (<NUM>) is smaller than an elasticity modulus of the first adhesive layer (<NUM>).