Patent Description:
Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.

PLDs may be used to control and/or be integrated with large array of different types of user devices, and the input/output (I/O) buses of such PLDs (e.g., general purpose I/O (GPIO) buses used to communicate with the user device and/or elements of the user device) can be subjected to a relatively wide range of different bus supply voltages (e.g., VCCIO, generally between <NUM>. 2v and <NUM>. 3v, +/- <NUM>%). Such bus supply voltages are typically stable during operation of the user device/PLD, but bus supply voltages can vary (e.g., ramp, or be set initially to one power on value and then ramp to an operational value) during a typical power on sequence for the user device and/or the PLD. Moreover, PLDs and/or other logic devices fabricated using advanced integrated circuit processes (e.g., <NUM> fully depleted silicon-on-insulator - FDSOI - processes) may be implemented with I/O transistors (e.g., relatively thick gate transistors) that can only tolerate up to approximately <NUM>. 8v +/-<NUM>% (e.g., source/drain Vds, gate/source Vgs, gate/drain Vgd voltages) and guarantee an operational lifespan of at least <NUM> years without incurring reliability issues. Thus, there is a need in the art for systems and methods to provide I/O bus supply voltage protections for PLDs, particularly during power on of a PLD and/or a user device controlled by and/or integrated with the PLD.

<CIT> describes circuits, methods, and apparatus for protecting devices in an output stage from over-voltage conditions caused by high supply and input voltages. Over-voltage protection is provided that operates over a range of voltage levels, and that can be optimized for performance at different voltage levels. Stacked devices are used to protect n and p-channel output devices from excess supply and input voltages. These stacked devices are biased by voltages received at their gates. These gate voltages vary as a function of supply voltage to maintain performance.

The problems of the related art are solved by a programmable logic device and a method having the features of the independent claims. Additional features for advantageous embodiments are provided in the dependent claims.

The present disclosure provides systems and methods for providing input/output (I/O) bus protection for a programmable logic device (PLD) for use in or with various user devices for computing applications and architectures, as described herein. In particular, embodiments include a bus protection control signal generator and a bus protection circuit arrangement configured to provide I/O bus supply voltage (e.g., VCCIO) protection for I/O buses of PLDs.

For example, PLDs can be integrated into and/or configured to control a wide array of different user devices, each with varying I/O bus supply voltage requirements, generally selected to be one or more of <NUM>. 5v, and <NUM>. To increase flexibility of a particular PLD, each I/O bus may be implemented with a bus protection control signal generator and a bus protection circuit arrangement configured to protect relatively sensitive I/O bus elements (e.g., I/O buffer/driver transistors) during all states of operation, including during power on states, where the various supply voltages provided to the PLD ramp to their operating levels. In general, the bus protection circuit arrangement may be implemented as a cascode transistor arrangement, as described herein, where protection transistors in the cascode transistor arrangement are biased by the bus protection control signal generator (e.g., via bias protection control signals) to ensure substantially all transistor voltages (e.g., source/drain Vds, gate/source Vgs, gate/drain Vgd) remain below an acceptable operational voltage drop specific to the transistors implementing the particular I/O bus (e.g., typically <NUM>. 8v +/- <NUM>%) during all operational modes/states of the I/O bus, the PLD, and/or a user device controlled by/integrated with/interfaced with the PLD. Moreover, embodiments described herein may be placed in a dormant or off mode that reduces or eliminates power leakage and/or associated dissipative heating while in certain operational modes, as described herein.

In accordance with embodiments set forth herein, techniques are provided to manage implementation of user designs in PLDs. In various embodiments, a user design may be converted into and/or represented by a set of PLD components (e.g., configured for logic, arithmetic, or other hardware functions) and their associated interconnections available in a PLD. For example, a PLD may include a number of programmable logic blocks (PLBs), each PLB including a number of logic cells, and configurable routing resources that may be used to interconnect the PLBs and/or logic cells. In some embodiments, each PLB may be implemented with between <NUM> and <NUM> or between <NUM> and <NUM> logic cells.

In general, a PLD (e.g., an FPGA) fabric includes one or more routing structures and an array of similarly arranged logic cells arranged within programmable function blocks (e.g., PFBs and/or PLBs). The purpose of the routing structures is to programmably connect the ports of the logic cells/PLBs to one another in such combinations as necessary to achieve an intended functionality. A remote PLD may include various additional "hard" engines or modules configured to provide a range of remote management functionality that may be linked to operation of the PLD fabric to provide configurable computing functionality and/or architectures. Routing flexibility and configurable function embedding may be used when synthesizing, mapping, placing, and/or routing a user design into a number of PLD components. As a result of various user design optimization processes, a user design can be implemented relatively efficiently, thereby freeing up configurable PLD components that would otherwise be occupied by additional operations and routing resources. In some embodiments, an optimized user design may be represented by a netlist that identifies various types of components provided by the PLD and their associated signals. In embodiments that produce a netlist of the converted user design, the optimization process may be performed on such a netlist. Once optimized, such configuration may be loaded into a PLD and the PLD may boot and execute the configuration, which may include the use of various I/O buses to communicate with a user device, as described herein.

Referring now to the drawings, <FIG> illustrates a block diagram of a PLD <NUM> in accordance with an embodiment of the disclosure. PLD <NUM> (e.g., a field programmable gate array (FPGA)), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other type of programmable device) generally includes input/output (I/O) blocks <NUM> and logic blocks <NUM> (e.g., also referred to as programmable logic blocks (PLBs), programmable functional units (PFUs), or programmable logic cells (PLCs)). More generally, the individual elements of PLD <NUM> may be referred to as a PLD fabric.

I/O blocks <NUM> provide I/O functionality (e.g., to support one or more I/O and/or memory interface standards) for PLD <NUM>, while programmable logic blocks <NUM> provide logic functionality (e.g., LUT-based logic or logic gate array-based logic) for PLD <NUM>. Additional I/O functionality may be provided by serializer/deserializer (SERDES) blocks <NUM> and physical coding sublayer (PCS) blocks <NUM>. PLD <NUM> may also include hard intellectual property core (IP) blocks <NUM> to provide additional functionality (e.g., substantially predetermined functionality provided in hardware which may be configured with less programming than logic blocks <NUM>).

PLD <NUM> may also include blocks of memory <NUM> (e.g., blocks of EEPROM, block SRAM, and/or flash memory), clock-related circuitry <NUM> (e.g., clock sources, PLL circuits, and/or DLL circuits), and/or various routing resources <NUM> (e.g., interconnect and appropriate switching logic to provide paths for routing signals throughout PLD <NUM>, such as for clock signals, data signals, or others) as appropriate. In general, the various elements of PLD <NUM> may be used to perform their intended functions for desired applications, as would be understood by one skilled in the art.

For example, certain I/O blocks <NUM> may be used for programming memory <NUM> or transferring information (e.g., various types of user data and/or control signals) to/from PLD <NUM>. Other I/O blocks <NUM> include a first programming port (which may represent a central processing unit (CPU) port, a peripheral data port, an SPI interface, and/or a sysCONFIG programming port) and/or a second programming port such as a joint test action group (JTAG) port (e.g., by employing standards such as Institute of Electrical and Electronics Engineers (IEEE) <NUM> or <NUM> standards). In various embodiments, I/O blocks <NUM> may be included to receive configuration data and commands (e.g., over one or more connections <NUM>) to configure PLD <NUM> for its intended use and to support serial or parallel device configuration and information transfer with SERDES blocks <NUM>, PCS blocks <NUM>, hard IP blocks <NUM>, and/or logic blocks <NUM> as appropriate.

It should be understood that the number and placement of the various elements are not limiting and may depend upon the desired application. For example, various elements may not be required for a desired application or design specification (e.g., for the type of programmable device selected). Furthermore, it should be understood that the elements are illustrated in block form for clarity and that various elements would typically be distributed throughout PLD <NUM>, such as in and between logic blocks <NUM>, hard IP blocks <NUM>, and routing resources (e.g., routing resources <NUM> of <FIG>) to perform their conventional functions (e.g., storing configuration data that configures PLD <NUM> or providing interconnect structure within PLD <NUM>). It should also be understood that the various embodiments disclosed herein are not limited to programmable logic devices, such as PLD <NUM>, and may be applied to various other types of programmable devices, as would be understood by one skilled in the art.

An external system <NUM> may be used to create a desired user configuration or design of PLD <NUM> and generate corresponding configuration data to program (e.g., configure) PLD <NUM>. For example, system <NUM> may provide such configuration data to one or more I/O blocks <NUM>, SERDES blocks <NUM>, and/or other portions of PLD <NUM>. As a result, programmable logic blocks <NUM>, various routing resources, and any other appropriate components of PLD <NUM> may be configured to operate in accordance with user-specified applications.

In the illustrated embodiment, system <NUM> is implemented as a computer system. In this regard, system <NUM> includes, for example, one or more processors <NUM> which may be configured to execute instructions, such as software instructions, provided in one or more memories <NUM> and/or stored in non-transitory form in one or more non-transitory machine readable mediums <NUM> (e.g., which may be internal or external to system <NUM>). For example, in some embodiments, system <NUM> may run PLD configuration software, such as Lattice Diamond System Planner software available from Lattice Semiconductor Corporation to permit a user to create a desired configuration and generate corresponding configuration data to program PLD <NUM>.

System <NUM> also includes, for example, a user interface <NUM> (e.g., a screen or display) to display information to a user, and one or more user input devices <NUM> (e.g., a keyboard, mouse, trackball, touchscreen, and/or other device) to receive user commands or design entry to prepare a desired configuration of PLD <NUM>.

<FIG> illustrates a block diagram of a logic block <NUM> of PLD <NUM> in accordance with an embodiment of the disclosure. As discussed, PLD <NUM> includes a plurality of logic blocks <NUM> including various components to provide logic and arithmetic functionality. In the example embodiment shown in <FIG>, logic block <NUM> includes a plurality of logic cells <NUM>, which may be interconnected internally within logic block <NUM> and/or externally using routing resources <NUM>. For example, each logic cell <NUM> may include various components such as: a lookup table (LUT) <NUM>, a mode logic circuit <NUM>, a register <NUM> (e.g., a flip-flop or latch), and various programmable multiplexers (e.g., programmable multiplexers <NUM> and <NUM>) for selecting desired signal paths for logic cell <NUM> and/or between logic cells <NUM>. In this example, LUT <NUM> accepts four inputs 220A-220D, which makes it a four-input LUT (which may be abbreviated as "<NUM>-LUT" or "LUT4") that can be programmed by configuration data for PLD <NUM> to implement any appropriate logic operation having four inputs or less. Mode Logic <NUM> may include various logic elements and/or additional inputs, such as input 220E, to support the functionality of various modes, as described herein. LUT <NUM> in other examples may be of any other suitable size having any other suitable number of inputs for a particular implementation of a PLD. In some embodiments, different size LUTs may be provided for different logic blocks <NUM> and/or different logic cells <NUM>.

An output signal <NUM> from LUT <NUM> and/or mode logic <NUM> may in some embodiments be passed through register <NUM> to provide an output signal <NUM> of logic cell <NUM>. In various embodiments, an output signal <NUM> from LUT <NUM> and/or mode logic <NUM> may be passed to output <NUM> directly, as shown. Depending on the configuration of multiplexers <NUM>-<NUM> and/or mode logic <NUM>, output signal <NUM> may be temporarily stored (e.g., latched) in latch <NUM> according to control signals <NUM>. In some embodiments, configuration data for PLD <NUM> may configure output <NUM> and/or <NUM> of logic cell <NUM> to be provided as one or more inputs of another logic cell <NUM> (e.g., in another logic block or the same logic block) in a staged or cascaded arrangement (e.g., comprising multiple levels) to configure logic operations that cannot be implemented in a single logic cell <NUM> (e.g., logic operations that have too many inputs to be implemented by a single LUT <NUM>). Moreover, logic cells <NUM> may be implemented with multiple outputs and/or interconnections to facilitate selectable modes of operation, as described herein.

Mode logic circuit <NUM> may be utilized for some configurations of PLD <NUM> to efficiently implement arithmetic operations such as adders, subtractors, comparators, counters, or other operations, to efficiently form some extended logic operations (e.g., higher order LUTs, working on multiple bit data), to efficiently implement a relatively small RAM, and/or to allow for selection between logic, arithmetic, extended logic, and/or other selectable modes of operation. In this regard, mode logic circuits <NUM>, across multiple logic cells <NUM>, may be chained together to pass carry-in signals <NUM> and carry-out signals <NUM>, and/or other signals (e.g., output signals <NUM>) between adjacent logic cells <NUM>, as described herein. In the example of <FIG>, carry-in signal <NUM> may be passed directly to mode logic circuit <NUM>, for example, or may be passed to mode logic circuit <NUM> by configuring one or more programmable multiplexers, as described herein. In some embodiments, mode logic circuits <NUM> may be chained across multiple logic blocks <NUM>.

Logic cell <NUM> illustrated in <FIG> is merely an example, and logic cells <NUM> according to different embodiments may include different combinations and arrangements of PLD components. Also, although <FIG> illustrates logic block <NUM> having eight logic cells <NUM>, logic block <NUM> according to other embodiments may include fewer logic cells <NUM> or more logic cells <NUM>. Each of the logic cells <NUM> of logic block <NUM> may be used to implement a portion of a user design implemented by PLD <NUM>. In this regard, PLD <NUM> may include many logic blocks <NUM>, each of which may include logic cells <NUM> and/or other components which are used to collectively implement the user design.

As further described herein, portions of a user design may be adjusted to occupy fewer logic cells <NUM>, fewer logic blocks <NUM>, and/or with less burden on routing resources <NUM> when PLD <NUM> is configured to implement the user design. Such adjustments according to various embodiments may identify certain logic, arithmetic, and/or extended logic operations, to be implemented in an arrangement occupying multiple embodiments of logic cells <NUM> and/or logic blocks <NUM>. As further described herein, an optimization process may route various signal connections associated with the arithmetic/logic operations described herein, such that a logic, ripple arithmetic, or extended logic operation may be implemented into one or more logic cells <NUM> and/or logic blocks <NUM> to be associated with the preceding arithmetic/logic operations.

<FIG> illustrates a design process <NUM> for a PLD in accordance with an embodiment of the disclosure. For example, the process of <FIG> may be performed by system <NUM> running Lattice Diamond software to configure PLD <NUM>. In some embodiments, the various files and information referenced in <FIG> may be stored, for example, in one or more databases and/or other data structures in memory <NUM>, machine readable medium <NUM>, and/or otherwise. In various embodiments, such files and/or information may be encrypted or otherwise secured when stored and/or conveyed to PLD <NUM> and/or other devices or systems.

In operation <NUM>, system <NUM> receives a user design that specifies the desired functionality of PLD <NUM>. For example, the user may interact with system <NUM> (e.g., through user input device <NUM> and hardware description language (HDL) code representing the design) to identify various features of the user design (e.g., high level logic operations, hardware configurations, and/or other features). In some embodiments, the user design may be provided in a register transfer level (RTL) description (e.g., a gate level description). System <NUM> may perform one or more rule checks to confirm that the user design describes a valid configuration of PLD <NUM>. For example, system <NUM> may reject invalid configurations and/or request the user to provide new design information as appropriate.

In operation <NUM>, system <NUM> synthesizes the design to create a netlist (e.g., a synthesized RTL description) identifying an abstract logic implementation of the user design as a plurality of logic components (e.g., also referred to as netlist components), which may include both programmable components and hard IP components of PLD <NUM>. In some embodiments, the netlist may be stored in Electronic Design Interchange Format (EDIF) in a Native Generic Database (NGD) file.

In some embodiments, synthesizing the design into a netlist in operation <NUM> may involve converting (e.g., translating) the high-level description of logic operations, hardware configurations, and/or other features in the user design into a set of PLD components (e.g., logic blocks <NUM>, logic cells <NUM>, and other components of PLD <NUM> configured for logic, arithmetic, or other hardware functions to implement the user design) and their associated interconnections or signals. Depending on embodiments, the converted user design may be represented as a netlist.

In some embodiments, synthesizing the design into a netlist in operation <NUM> may further involve performing an optimization process on the user design (e.g., the user design converted/translated into a set of PLD components and their associated interconnections or signals) to reduce propagation delays, consumption of PLD resources and routing resources, and/or otherwise optimize the performance of the PLD when configured to implement the user design. Depending on embodiments, the optimization process may be performed on a netlist representing the converted/translated user design. Depending on embodiments, the optimization process may represent the optimized user design in a netlist (e.g., to produce an optimized netlist).

In some embodiments, the optimization process may include optimizing certain instances of a logic function operation, a ripple arithmetic operation, and/or an extended logic function operation which, when a PLD is configured to implement the user design, would occupy a plurality of configurable PLD components (e.g., logic cells <NUM>, logic blocks <NUM>, and/or routing resources <NUM>). For example, the optimization process may include detecting multiple mode or configurable logic cells implementing logic function operations, ripple arithmetic operations, extended logic function operations, and/or corresponding routing resources in the user design, interchanging operational modes of logic cells implementing the various operations to reduce the number of PLD components and/or routing resources used to implement the operations and/or to reduce the propagation delay associated with the operations, and/or reprogramming corresponding LUTs and/or mode logic to account for the interchanged operational modes.

In another example, the optimization process may include detecting extended logic function operations and/or corresponding routing resources in the user design, implementing the extended logic operations into multiple mode or convertible logic cells with single physical logic cell outputs, routing or coupling the logic cell outputs of a first set of logic cells to the inputs of a second set of logic cells to reduce the number of PLD components used to implement the extended logic operations and/or routing resources and/or to reduce the propagation delay associated with the extended logic operations, and/or programming corresponding LUTs and/or mode logic to implement the extended logic function operations with at least the first and second sets of logic cells.

In another example, the optimization process may include detecting multiple mode or configurable logic cells implementing logic function operations, ripple arithmetic operations, extended logic function operations, and/or corresponding routing resources in the user design, interchanging operational modes of logic cells implementing the various operations to provide a programmable register along a signal path within the PLD to reduce propagation delay associated with the signal path, and reprogramming corresponding LUTs, mode logic, and/or other logic cell control bits/registers to account for the interchanged operational modes and/or to program the programmable register to store or latch a signal on the signal path.

In operation <NUM>, system <NUM> performs a mapping process that identifies components of PLD <NUM> that may be used to implement the user design. In this regard, system <NUM> may map the optimized netlist (e.g., stored in operation <NUM> as a result of the optimization process) to various types of components provided by PLD <NUM> (e.g., logic blocks <NUM>, logic cells <NUM>, embedded hardware, and/or other portions of PLD <NUM>) and their associated signals (e.g., in a logical fashion, but without yet specifying placement or routing). In some embodiments, the mapping may be performed on one or more previously-stored NGD files, with the mapping results stored as a physical design file (e.g., also referred to as an NCD file). In some embodiments, the mapping process may be performed as part of the synthesis process in operation <NUM> to produce a netlist that is mapped to PLD components.

In operation <NUM>, system <NUM> performs a placement process to assign the mapped netlist components to particular physical components residing at specific physical locations of the PLD <NUM> (e.g., assigned to particular logic cells <NUM>, logic blocks <NUM>, routing resources <NUM>, and/or other physical components of PLD <NUM>), and thus determine a layout for the PLD <NUM>. In some embodiments, the placement may be performed on one or more previously-stored NCD files, with the placement results stored as another physical design file.

In operation <NUM>, system <NUM> performs a routing process to route connections (e.g., using routing resources <NUM>) among the components of PLD <NUM> based on the placement layout determined in operation <NUM> to realize the physical interconnections among the placed components. In some embodiments, the routing may be performed on one or more previously-stored NCD files, with the routing results stored as another physical design file.

In various embodiments, routing the connections in operation <NUM> may further involve performing an optimization process on the user design to reduce propagation delays, consumption of PLD resources and/or routing resources, and/or otherwise optimize the performance of the PLD when configured to implement the user design. The optimization process may in some embodiments be performed on a physical design file representing the converted/translated user design, and the optimization process may represent the optimized user design in the physical design file (e.g., to produce an optimized physical design file).

Changes in the routing may be propagated back to prior operations, such as synthesis, mapping, and/or placement, to further optimize various aspects of the user design.

Thus, following operation <NUM>, one or more physical design files may be provided which specify the user design after it has been synthesized (e.g., converted and optimized), mapped, placed, and routed (e.g., further optimized) for PLD <NUM> (e.g., by combining the results of the corresponding previous operations). In operation <NUM>, system <NUM> generates configuration data for the synthesized, mapped, placed, and routed user design. In various embodiments, such configuration data may be encrypted, signed, and/or otherwise protected as part of such generation process, as described more fully herein. In operation <NUM>, system <NUM> configures PLD <NUM> with the configuration data by, for example, loading a configuration data bitstream (e.g., a "configuration" or "configuration image") into PLD <NUM> over connection <NUM>. Such configuration may be provided in an encrypted, signed, or unsecured/unauthenticated form, for example, and PLD <NUM> may be configured to treat secured and unsecured configurations differently, as described herein.

<FIG> illustrates a block diagram of a user device <NUM> including a PLD <NUM> in accordance with an embodiment of the disclosure. In various embodiments, PLD <NUM> may be implemented by elements similar to those described with respect to PLD <NUM> in <FIG>, but with additional configurable and/or hard IP elements configured to facilitate operation of PLD <NUM> in a particular computing application and/or architecture, as described herein. In particular, PLD <NUM> may include a PLD fabric <NUM> linked by various buses to a non-volatile memory (NVM) <NUM>, a programmable I/O <NUM>, and/or other integrated circuit (IC) modules <NUM>, all implemented on a monolithic IC, as shown. In general, PLD fabric <NUM> may be implemented by any of the various elements described with respect to PLD <NUM> and may be configured using a design process similar to design process <NUM> described in relation to <FIG> to generate and program PLD fabric <NUM> according to a desired configuration. User device <NUM> may include communication module <NUM> and/or other user device modules <NUM> configured to facilitate remote management of PLD <NUM>, for example, or to facilitate a particular user device application, as described herein. In various embodiments, user device <NUM> may be implemented as a smart phone, a laptop computer, a tablet computer, a desktop computer, a smart environmental sensor, a home automation device (e.g., sensor and/or actuator), an embedded device, a network management device, and/or other user device, as described herein.

NVM <NUM> may be implemented as a hard IP resource configured to provide securable and/or non-volatile storage of data used to facilitate operation of PLD <NUM>. NVM <NUM> may include multiple differentiated sectors, such as one or more configuration image sectors, a device key sector (e.g., an AES key sector and a separate public key/key pair sector), a user flash memory (UFM) sector, and/or other defined storage sectors. Configuration image sectors may each store a configuration for PLD fabric <NUM>, for example, so as to allow them to be selected (e.g., based on version or date) and used to program PLD fabric <NUM>. A trim sector may be used to store manufacturer trim, device identifier, device category identifier, and/or other data specific to a particular PLD <NUM>, for example, such as a modifiable customer-specific ordering part number and/or a generated customer ID number. Device key sectors may be used to store encryption/decryption keys, public/private keys, and/or other security keys specific to a particular PLD <NUM>. UFM sectors may be used to store user data generally accessible by PLD fabric <NUM>, such as configurations or application-specific security keys, certificates, and/or other secure(d) user data. Any one or more individual elements, portions, or sectors of NVM <NUM> may be implemented as configurable memory, for example, or one-time programmable (OTP) memory, as described herein.

Programmable I/O <NUM> may be implemented as at least partially configurable resources and/or hard IP resources configured to provide or support a communications link between PLD fabric <NUM> and an external controller, memory, and/or other device, such as communication module <NUM>, for example, across bus <NUM> (e.g., a bus configured to link portions of PLD fabric <NUM> to programmable I/O <NUM> and/or NVM <NUM>) and according to one or more external bus interfaces, protocols, and/or bus supply voltages (e.g., external bus interface <NUM>). Programmable I/O <NUM> may also be configured to support communications between PLD fabric <NUM> and/or NVM <NUM> across bus <NUM> and/or external bus interface <NUM> with communication module <NUM>, for example, in addition or as an alternative to external system130/machine readable medium <NUM>, as described herein.

In some embodiments, bus <NUM> and/or programmable I/O <NUM> may be integrated with PLD fabric <NUM>. More generally, one or more elements of PLD <NUM> shown as separate in <FIG> may be integrated with and/or within each other. Other IC modules <NUM> may be implemented as hard and/or configurable IP resources configured to facilitate operation of PLD <NUM>. For example, other IC modules <NUM> may include a security engine implemented as a hard IP resource configured to provide various security functions for use by PLD fabric <NUM> and/or user device <NUM>, a configuration engine implemented as a hard IP resource configured to manage the configurations of and/or communications amongst the various elements of PLD <NUM>, including to manage or control configurations of elements of PLD <NUM>, boot of PLD fabric <NUM>, and flow control throughout PLD <NUM>, or may include one or more additional external access busses implemented according to one or more of a JTAG, I2C, SPI, and/or other external access bus or protocol, for example, configured to provide access to and/or from communication module <NUM> and/or other user device modules <NUM>.

Communication module <NUM> may be implemented as a network communications IC configured to form communications links to a remote external device used to manage operation of PLD <NUM>. For example, in some embodiments, communication module <NUM> may be implemented as a wireless communication module configured to support a wired and/or wireless communications link (e.g., formed according to WiFi, Bluetooth, Zigbee, Zwave, near-field communication (NFC), cellular, Ethernet, and/or other open and/or proprietary wired and/or wireless communication protocols) to a communications network, as described herein. In such embodiments, communication module <NUM> may be configured to manage various security features of such wired and/or wireless communications link (e.g., establishing communications link credentials, employing communications link credentials to establish a communications link, negotiating encryption keys for encrypted communications tunnels established over such communications link, such as transport layer security (TLS)), for example, and/or may be configured to be controlled by PLD <NUM> and/or other user device module <NUM> to manage such security features.

Other user device modules <NUM> may include various computing, sensor, and/or actuator elements configured to implement a particular user device application, for example, such as a remote sensor application, a remote controller application, and/or a remote computing application, as described herein. Other user device modules <NUM> may also include various other communication buses, power storage and delivery elements, user interfaces (e.g., buttons, keyboard, mouse, track pad, and/or displays/touch screen displays) to support such user device applications. In one embodiment, other user device modules <NUM> includes an electrical characteristic sensor configured to detect and/or measure an electrical state of transducer element (e.g., also an element of other user device modules <NUM>) that is used to measure an environmental condition associated with user device <NUM>. In another embodiment, other user device modules <NUM> includes various electronic devices typically found within a smart phone, a laptop computer, a tablet computer, and/or a desktop computer.

As described herein, embodiments of programmable I/O <NUM> may include a bus protection control signal generator and a bus protection circuit arrangement configured to provide I/O bus supply voltage (e.g., VCCIO) protection for programmable I/O <NUM> of PLD <NUM>. <FIG> illustrate block diagrams of various programmable I/O interfaces <NUM> (e.g., for PLD <NUM>) including a bus protection control signal (BPCS) generator <NUM> configured to provide I/O bus supply voltage protection in accordance with embodiments of the disclosure. For example, <FIG> illustrates a block diagram of a programmable I/O interface 504A including bus protection control signal generator <NUM> configured to receive various external supply signals <NUM> (e.g., core voltage VCC, VCCAUX, I/O bus supply voltage VCCIO) and generate bus protection control signals pcasc <NUM> and ncasc <NUM> (e.g., transistor bias signals) for respective PMOS protection transistor <NUM> and NMOS protection transistor <NUM> of bus protection circuit arrangement <NUM> (e.g., a cascode transistor arrangement). Bus protection circuit arrangement <NUM> <FIG> is shown implemented as a single output driver for data signaling output pad <NUM> (e.g., referenced to system/local/bus ground <NUM>); more generally, bus protection control signals pcasc <NUM> and ncasc <NUM> may be provided to an array of bus protection circuit arrangements <NUM>. Also shown in programmable I/O interface 504a are PMOS signaling transistor <NUM> driven by data signaling input <NUM> and NMOS signaling transistor <NUM> driven by data signaling input <NUM>, which are generally provided by PLD fabric <NUM> and/or other elements of PLD <NUM>.

<FIG> illustrates a block diagram of a programmable I/O interface 504B including various bus protection circuit arrangements <NUM>-<NUM> configured to receive bus protection control signals pcasc <NUM> and ncasc <NUM> (e.g., from bus protection control signal generator <NUM>), various external supply signals <NUM>, and/or other control signals and provide I/O bus supply voltage protection for programmable I/O <NUM> of PLD <NUM>. In particular, programmable I/O interface 504B may correspond to a single input buffer for data signaling input pads <NUM> (e.g., referenced to system/local/bus ground <NUM>); more generally, bus protection control signals pcasc <NUM> and ncasc <NUM> may be provided to an array of bus protection circuit arrangements <NUM>-<NUM>. As shown in <FIG>, bus protection circuit arrangements <NUM>-<NUM> may be implemented with enable inputs <NUM> (e.g., for <NUM>, <NUM>, and <NUM>. 2v) coupled to corresponding enable transistors <NUM> disposed within such cascode transistor arrangements (e.g., or serial array of transistor elements within each circuit arrangement) configured to cover an expected possible range of bus voltages and enable/disable and protect the cascode transistor arrangements within each bus protection circuit arrangements <NUM>-<NUM>, as shown and described more fully herein. In various embodiments, such enable signals may be generated by PLD fabric <NUM> of PLD <NUM>. Moreover, such enable inputs/transistors <NUM> may be configured to reduce and/or eliminate power draw of such circuit arrangements when not in use (e.g., when the corresponding I/O bus is not in use, or the corresponding bus voltage is not in use). Also shown in bus protection circuit arrangements <NUM>-<NUM> are data signaling outputs/DIs <NUM> of programmable I/O interface 504B.

<FIG> illustrates a block diagram of a programmable I/O interface 504C including a common block BPCS generator <NUM> coupled through an array of local BPCS generators <NUM> each configured to apply bus protection control signals generated by common block BPCS generator <NUM> to their respective I/O buses <NUM>, each of which may be coupled to user device <NUM> via one or more external buses <NUM>, which may be physically separate and/or integrated buses, as shown. In generally, common block BPCS generator <NUM> may include circuit elements to receive external supply signals <NUM> and/or other relevant control signals, to generate bus protection control signals pcasc <NUM> and ncasc <NUM> based, at least in part, on such supply and/or control signals, and to provide bus protection control signals pcasc <NUM> and ncasc <NUM>, along with other appropriate controls signals described herein, along bus protection control signal bus 530b. Local BPCS generators <NUM> may include only those circuit elements necessary to apply the received bus protection control signals to bus protection circuit arrangements within each I/O bus <NUM>. In such embodiments, bus protection may be provided compactly and with less power across an array of I/O buses <NUM> of PLD <NUM>.

<FIG> illustrates a block diagram of a programmable I/O interface 504D with additional detail as to the various control signals that may be received and/or generated by embodiments of BPCD generator <NUM>. For example, as shown in <FIG>, BPCS generator <NUM> may be configured to receive external supply signals <NUM>, PLD fabric bus control signals <NUM>, PLD configuration load completion signal <NUM>, and/or a power on reset signal (or its inverse) <NUM> and to generate bus protection control signals pcasc <NUM> and ncasc <NUM>, as described herein, along with bus supply voltage enable signals <NUM> and bus protection relay signals 530d, as shown. Also shown in <FIG> are bus interface signals 528d (e.g., which may include VCCIO) coupled through to BPCS generator <NUM> and configured to generate an aggregate bus interface electrostatic discharge trigger 529d-<NUM>, which may be used by electrostatic discharge clamp 529d to protect BPCS generator <NUM> and/or other elements of PLD <NUM> when I/O bus interface is coupled, decoupled, and/or powered on or off.

<FIG> illustrate circuit diagrams of various bus protection control signal generators <NUM> in accordance with embodiments of the disclosure. For example, <FIG> illustrates bus protection control signal generator 506A including portion <NUM> configured to generate bus protection control signals prior to user device <NUM> completing a power ramp of at least external supply signals <NUM> identified in <FIG>. For example, such control signals may be refereed to generally as default or initial or power ramping bus protection control signals, as described herein, and may be configured to control an associated bus protection circuit arrangement (e.g., as shown in <FIG>) to place an associated programmable I/O (e.g., programmable I/O <NUM> of PLD <NUM>) into a default or initial or safed or power ramping mode, for example, where the associated bus protection circuit arrangement is configured to accept and/or operate under any possible bus supply voltage without risking damage to the associated programmable I/O interface. For example, such default or initial or safed or power ramping mode may be a mode able to accept and/or operate under a <NUM>. 3v bus supply voltage, thereby protecting the programmable I/O interface from all possible VCCIOs. In particular embodiments, such default or initial or power ramping bus protection control signals may be set to one half the supplied VCCIO using a resistor divider circuit arrangement disposed within portion <NUM>.

Similarly, bus protection control signal generator 506A is shown in <FIG> as including portions <NUM> and <NUM> configured to generate bus protection control signals after user device <NUM> has completed a power ramp of at least external supply signals <NUM> identified in <FIG>, and prior to PLD <NUM> completing loading of a PLD configuration into PLD fabric <NUM>, as shown in <FIG>. For example, such control signals may be refereed to generally as intermediate or PLD configuration loading bus protection control signals, as described herein, and may be configured to control an associated bus protection circuit arrangement (e.g., as shown in <FIG>) to place an associated programmable I/O (e.g., programmable I/O <NUM> of PLD <NUM>) into an intermediate or PLD configuration loading mode, for example, where the associated bus protection circuit arrangement is configured to accept and/or operate under a detected fully ramped bus supply voltage without risking damage to the associated programmable I/O interface.

In some embodiments, bus protection control signal generator 506A may include portions <NUM>, <NUM>, and <NUM> configured to generate bus protection control signals after user device <NUM> has completed a power ramp of at least external supply signals <NUM> and after a PLD configuration has been loaded into PLD fabric <NUM>. For example, such control signals may be refereed to generally as operational or PLD configured bus protection control signals, as described herein, and may be configured to control an associated bus protection circuit arrangement (e.g., as shown in <FIG>) to place an associated programmable I/O (e.g., programmable I/O <NUM> of PLD <NUM>) into an operating or PLD configured mode, for example, where the associated bus protection circuit arrangement is configured to accept and/or operate under a detected fully ramped bus supply voltage and/or a PLD fabric selected bias supply voltage without risking damage to the associated programmable I/O interface. For example, PLD fabric <NUM> may be configured to place bus protection circuit arrangement 504A of <FIG> into a <NUM>. 8v VCCIO mode, even though user device <NUM> is not providing a VCCIO to the associated programmable I/O, because PLD fabric <NUM> has been configured to expect such VCCIO over the associated programmable I/O at some point during the operation of PLD <NUM> and/or user device <NUM>.

The remaining <FIG> illustrate details of portions <NUM>, <NUM>, <NUM>, and <NUM>. For example, <FIG> illustrates a circuit diagram substantially implementing portion <NUM> of bus protection control signal generator 506A with various transistors, resistors, capacitors, logic gates, integrated circuits (ICs), circuit traces, and/or other circuit elements, as shown. <FIG> illustrates a circuit diagram substantially implementing portion <NUM> of bus protection control signal generator 506A with various transistors, resistors, capacitors, logic gates, integrated circuits (ICs), circuit traces, and/or other circuit elements, as shown. <FIG> illustrates a circuit diagram substantially implementing portion <NUM> of bus protection control signal generator 506A with various transistors, resistors, capacitors, logic gates, integrated circuits (ICs), circuit traces, and/or other circuit elements, as shown. <FIG> illustrates a circuit diagram substantially implementing portion <NUM> of bus protection control signal generator 506A with various transistors, resistors, capacitors, logic gates, integrated circuits (ICs), circuit traces, and/or other circuit elements, as shown.

In general, <FIG> illustrate circuitry that may be used to implement embodiments of common block BPCS generator <NUM> and/or local BPCS generators <NUM> of <FIG>. In some embodiments, local BPCS generators <NUM> may be implemented with fewer circuit elements so as reduce utilization of PLD resources, for example, as described herein. <FIG> illustrates a circuit diagram of a reduced-resource embodiment of local BPCS generators <NUM> shown in the embodiment depicted by <FIG>.

<FIG> illustrates a block diagram of bus protection control signal generator <NUM> in accordance with an embodiment of the disclosure. In various embodiments, bus protection control signal generator <NUM> may be implemented similarly to bus protection control signal generators <NUM> and/or <NUM> of <FIG>, as described herein. In the embodiment shown in <FIG>, bus protection control signal generator <NUM> shows the general operation of a bus protection control signal generator implemented according to embodiments described herein.

In general, bus protection control signal generators described herein may be operated in accordance with three sequential steps or modes of operation: a power ramping step or mode, a PLD configuration loading step or mode, and an operational step or mode. In the power ramping step, or before power on reset signal <NUM> transitions, user device <NUM> ramps each of external supply signals <NUM> (e.g., core voltage VCC, VCCAUX, I/O bus supply voltage VCCIO) up to their operating level. User device <NUM> may ramp them in any order, and the order may change from power on to power on, and so operational flexibility (e.g., power ramping levels and sequence) of bus protection control signal generator <NUM> during the power ramping step is desirable. Typically, all external supply signals <NUM> are provided or dictated by user device <NUM>. PLD <NUM> may require a specific core voltage VCC (e.g., 1v +/-<NUM>%) and a specific VCCAUX (e.g., <NUM>. 8v +/- <NUM>%) as part of its operational specification, but VCCIO can vary by user device, programmable I/O, and/or port/pad of programmable I/O, and each may be ramped to its respective operating level in any order (and, for multiple VCCIOs, each VCCIO may be ramped in any order). A power ramp completion detection module (e.g., other IC modules <NUM>) may be configured to monitor all such external supply signals <NUM>, along with other control signals provided by user device <NUM>, and to generate power on reset signal <NUM> once all such power ramping is complete, either on a per programmable I/O or bus basis, or across the entirety of PLD <NUM>.

In order to provide the desired flexibility during the power ramping step <NUM>, an assumption can be made as to the maximum extent of any VCCIO, and bus protection control signal generator <NUM> may be configured to generate a bus protection control signal for an associated bus protection circuit arrangement to ensure all transistor voltages generated by any VCCIO up to the maximum extent (e.g., typically <NUM>. 3v) is less than the desired operational voltage for those transistors (e.g., typically <NUM>. 8v +/-<NUM>%). In embodiments where the associated bus protection circuit arrangement is implemented as a cascode transistor arrangement, such as that shown in <FIG>, bus protection control signal generator <NUM> may be implemented with a voltage divider <NUM> and/or a multiplexor <NUM> configured to generate bus protection control signals setting pcasc <NUM> and ncasc <NUM> to approximately VCCIO/<NUM>, which protects all transistors of bus protection circuit arrangement <NUM> against damage by VCCIOs up to the max extent expected (e.g., <NUM>. 3v) while generally providing for data signaling transmission/reception during the power ramping step <NUM>.

In the PLD configuration loading step, or after power on reset signal <NUM> transitions but before PLD configuration load completion signal <NUM> transitions, PLD fabric <NUM> is not operating under a loaded configuration, but all applicable external supply signals <NUM> are fully ramped to their operating level. In various embodiments, bus protection control signal generator <NUM> may be configured to compare VCCIO and VCCAUX, determine the fully ramped VCCIO level based on that detection, reliably, and to determine and/or generate appropriate bus protection control signals and/or adjustments to such signals (e.g., bus protection control signals setting pcasc <NUM> and ncasc <NUM>) dynamically, so as to maximize data signaling reliability while ensuring all transistor voltages are below an associated acceptable operational voltage drop, as described herein. Information regarding VCCIO levels may also be useful for other IPs (e.g. I2C/I3C driver strength setting, LVCMOS input buffer selection from wide range of inputs, and/or other hard or soft IPs associated with PLD <NUM>).

In embodiments where the associated bus protection circuit arrangement is implemented as a cascode transistor arrangement, such as that shown in <FIG>, bus protection control signal generator <NUM> may be implemented with a bus supply voltage level detector <NUM>, multiplexor <NUM>, a pcasc/ncasc level generator <NUM>, and/or multiplexor <NUM> configured to generate bus protection control signals setting pcasc <NUM> and ncasc <NUM> to appropriate levels to protect all transistors of bus protection circuit arrangement <NUM> against damage. Below is an example truth table of various control signals associated with various detected bus supply voltages and operation of bus supply voltage level detector <NUM> and pcasc/ncasc level generator <NUM>.

In the operational step, or after power on reset signal <NUM> transitions and after PLD configuration load completion signal <NUM> transitions, PLD fabric <NUM> is operating under a loaded configuration, and all applicable external supply signals <NUM> are fully ramped to their operating level. In various embodiments, bus protection control signal generator <NUM> may be configured to receive PLD fabric bus control signals <NUM>, thereby allowing PLD fabric <NUM> to control bus protection control signal generator <NUM> to generate appropriate bus protection control signals and/or adjustments to such signals, so as to maximize data signaling reliability while ensuring all transistor voltages are below an associated acceptable operational voltage drop, as described herein. In some embodiments, such control can help resolve granularity limitations in detecting between <NUM>. 2v and <NUM>. 5v VCCIOs (e.g., in step <NUM>, bus protection control signal generator <NUM> may not differentiate between <NUM>. 2v and <NUM>. 5v VCCIOs, whereas in step <NUM>, known VCCIOs may be set granularly based on known expected VCCIOs).

In embodiments where the associated bus protection circuit arrangement is implemented as a cascode transistor arrangement, such as that shown in <FIG>, bus protection control signal generator <NUM> may be implemented with a PLD fabric override <NUM>, multiplexor <NUM>, pcasc/ncasc level generator <NUM>, and/or multiplexor <NUM> configured to generate bus protection control signals setting pcasc <NUM> and ncasc <NUM> to desired levels selected by PLD fabric <NUM>, which may be used to protect all transistors of bus protection circuit arrangement <NUM> against damage. Below is an example truth table of various control signals associated with various detected bus supply voltages and operation of PLD fabric override <NUM> and pcasc/ncasc level generator <NUM>.

<FIG> illustrates a typical power ramp timing graph <NUM> for PLD <NUM> including bus protection control signal generator <NUM> coupled to/within user device <NUM> in accordance with an embodiment of the disclosure. As shown in <FIG>, power ramp timing graph <NUM> shows time evolutions of load completion signal <NUM>, power on reset signal (or its inverse) <NUM>, bus protection control signals pcasc <NUM> and ncasc <NUM>, external supply signals <NUM>, and bus supply voltage enable signals <NUM>.

<FIG> illustrates an I/O buss protection process <NUM> in accordance with an embodiment of the disclosure. In some embodiments, the operations of <FIG> may be implemented as software instructions executed by one or more logic devices associated with corresponding electronic devices, modules, and/or structures depicted in <FIG>. More generally, the operations of <FIG> may be implemented with any combination of software instructions and/or electronic hardware (e.g., inductors, capacitors, amplifiers, actuators, or other analog and/or digital components). It should be appreciated that any step, sub-step, sub-process, or block of process <NUM> may be performed in an order or arrangement different from the embodiments illustrated by <FIG>. For example, in other embodiments, one or more blocks may be omitted from process <NUM>, and other blocks may be included. Furthermore, block inputs, block outputs, various sensor signals, sensor information, calibration parameters, and/or other operational parameters may be stored to one or more memories prior to moving to a following portion of process <NUM>. Although process <NUM> is described with reference to systems, devices, and elements of <FIG>, process <NUM> may be performed by other systems, devices, and elements, and including a different selection of electronic systems, devices, elements, assemblies, and/or arrangements. At the initiation of process <NUM>, various system parameters may be populated by prior execution of a process similar to process <NUM>, for example, or may be initialized to zero and/or one or more values corresponding to typical, stored, and/or learned values derived from past operation of process <NUM>, as described herein.

In block <NUM>, a logic device generates a default bus protection control signal. For example, bus protection control signal generator <NUM> may be configured to generate a default or initial or safed or power ramping bus protection control signal (e.g., pcasc <NUM> and/or ncasc <NUM>) for PLD <NUM> of user device <NUM>.

In block <NUM>, a logic device generates an intermediate bus protection control signal. For example, bus protection control signal generator <NUM> may be configured to generate an intermediate or PLD configuration loading bus protection control signal (e.g., pcasc <NUM> and/or ncasc <NUM>) for PLD <NUM> of user device <NUM>. In various embodiments, bus protection control signal generator <NUM> may be configured to detect completion of a power ramp performed by user device <NUM> prior to generating the intermediate or PLD configuration loading bus protection control signal, for example, such that the generating the intermediate or PLD configuration loading bus protection control signal is triggered by a control signal/comparator output indicating completion of such power ramp.

In block <NUM>, a logic device generates an operational bus protection control signal. For example, bus protection control signal generator <NUM> may be configured to generate an operating or PLD configured bus protection control signal (e.g., pcasc <NUM> and/or ncasc <NUM>) for PLD <NUM> of user device <NUM>. In various embodiments, bus protection control signal generator <NUM> may be configured to detect completion of loading a PLD configuration into PLD fabric <NUM> prior to generating the operating or PLD configured bus protection control signal, for example, such that the generating the operating or PLD configured bus protection control signal is triggered by a control signal indicating completion of loading a PLD configuration into PLD fabric <NUM>.

Thus, by employing the systems and methods described herein, embodiments of the present disclosure are able to provide flexible and reliable I/O bus protection for a PLD during all common modes of operation and all possible power ramping levels and sequences. Moreover, embodiments are able to do so while providing sufficient transistor voltages (e.g., Vgs) for meeting typical driver strength specifications.

Where applicable, various embodiments provided by the present disclosure can be implemented using hardware, software, or combinations of hardware and software. Also, where applicable, the various hardware components and/or software components set forth herein can be combined into composite components comprising software, hardware, and/or both without departing from the spirit of the present disclosure. Where applicable, the various hardware components and/or software components set forth herein can be separated into sub-components comprising software, hardware, or both without departing from the scope of the claims.

In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice-versa.

Software in accordance with the present disclosure, such as non-transitory instructions, program code, and/or data, can be stored on one or more non-transitory machine readable mediums. It is also contemplated that software identified herein can be implemented using one or more general purpose or specific purpose computers and/or computer systems, networked and/or otherwise. Where applicable, the ordering of various steps described herein can be changed, combined into composite steps, and/or separated into sub-steps to provide features described herein.

Claim 1:
A programmable logic device (PLD) (<NUM>), comprising:
a programmable input/output, I/O, interface (504A) configured to interface with a user device (<NUM>) over an external bus (<NUM>) coupled to the PLD;
a bus protection circuit arrangement (<NUM>) integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface, wherein the bus protection circuit arrangement comprises a cascode transistor arrangement (<NUM>) disposed between a bus supply voltage and a ground for the programmable I/O interface; and
a bus protection control signal generator (<NUM>) coupled to the programmable I/O interface and/or the bus protection circuit arrangement, wherein the bus protection control signal generator is configured to:
generate a default bus protection control signal for the cascode transistor arrangement of the PLD prior to completion of a power ramp performed by the user device;
generate an intermediate bus protection control signal for the cascode transistor arrangement of the PLD after the completion of the power ramp performed by the user device and prior to completion of loading a PLD configuration into a PLD fabric (<NUM>) of the PLD; and
generate an operational bus protection control signal for the cascode transistor arrangement of the PLD after the completion of the loading the PLD configuration into the PLD fabric,
wherein the cascode transistor arrangement comprises a PMOS protection transistor (<NUM>) and an NMOS protection transistor (<NUM>) configured to receive the default, intermediate, and operational bus protection control signals generated by the bus protection control signal generator.