Patent Description:
The technology of the disclosure relates generally to Fin Field Effect transistors (FETs) (FinFETs), and particularly to applying stress to a channel region of a FinFET.

Transistors are essential components in modern electronic devices. Large numbers of transistors are employed in integrated circuits (ICs) in many modern electronic devices. For example, components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors for logic circuits and memory devices.

As electronic devices become more complex in functionality, so does the need to include a greater number of transistors in such devices. However, as electronic devices are required to be provided in increasingly smaller packages, such as in mobile devices, for example, there is a need to provide a greater number of transistors in a smaller IC chip. This increase in the number of transistors is achieved in part through continued efforts to miniaturize transistors in ICs (i.e., placing increasingly more transistors into the same amount of space). In particular, node sizes in ICs are being scaled down by a reduction in minimum metal line width in the ICs (e.g., <NUM> nanometers (nm), <NUM>, <NUM>, <NUM>, etc.). As a result, the gate lengths of planar transistors are also scalably reduced, thereby reducing the channel length of the transistors and interconnects. Reduced channel length in planar transistors has the benefit of increasing drive strength (i.e., increased drain current) and providing smaller parasitic capacitances resulting in reduced circuit delay. However, as channel length in planar transistors is reduced such that the channel length approaches a magnitude similar to the depletion layer widths, short channel effects (SCEs) can occur that degrade performance. More specifically, SCEs in planar transistors cause increased current leakage, reduced threshold voltage, and/or threshold voltage roll-off (i.e., reduced threshold voltage at shorter gate lengths).

In this regard, to address the need to scale down channel lengths in transistors while avoiding or mitigating SCEs, transistor designs alternative to planar transistors have been developed. One such alternative transistor design includes a Fin Field Effect transistor (FET) (FinFET) that provides a conducting channel via a "Fin" formed from a substrate. Material is wrapped around the Fin to form the gate of the device. For example, <FIG> illustrates an exemplary FinFET <NUM>. The FinFET <NUM> includes a substrate <NUM> and a Fin <NUM> formed from the substrate <NUM>. An oxide layer <NUM> is included on either side of the Fin <NUM>. The FinFET <NUM> includes a source <NUM> and a drain <NUM> interconnected by the Fin <NUM> such that an interior portion of the Fin <NUM> serves as a conduction channel <NUM> between the source <NUM> and drain <NUM>. The Fin <NUM> is surrounded by a "wrap-around" gate <NUM>. The wrap-around structure of the gate <NUM> provides better electrostatic control over the channel <NUM>, and thus helps reduce the leakage current and overcoming other SCEs.

Although a FinFET, such as the FinFET <NUM>, reduces leakage current and avoids or mitigates SCEs compared to planar transistors, ICs employing FinFETs continue to need increased performance. One way to achieve increased performance in a FET, including the FinFET <NUM>, is to apply stress to the channel so as to alter carrier mobility within the channel. For example, stress <NUM> applied to the channel <NUM> of the FinFET <NUM> employed as an N-type FinFET causes corresponding electrons to flow more easily. Further, stress <NUM> applied to the channel <NUM> of the FinFET <NUM> employed as a P-type FinFET causes corresponding holes to flow more easily. In either case, stress <NUM> applied to the channel <NUM> is designed to change the carrier mobility so as to increase conductance in the channel <NUM>, thus increasing performance of the corresponding FinFET <NUM>. The stress <NUM> is achieved by applying compressive or tensile pressure on the channel <NUM>. Conventional methods to apply the stress <NUM> are more complex and less effective when employed with FinFETs, including the FinFET <NUM>. For example, the stress <NUM> can be applied to the channel <NUM> by growing epitaxial layers (not shown) corresponding to the source <NUM> and drain <NUM>, or by altering the composition of isolation trenches (not shown) separating the FinFET <NUM> from other devices. Further, these conventional methods are particularly less effective as FinFETs continue to decrease in area.

<CIT> relates to the fabrication of highly sophisticated integrated circuits including transistor elements having non-planar channel architecture. <CIT> relates to a FinFET structure with an L-shaped inductor and a manufacturing method thereof. <CIT> relates to a semiconductor device and a manufacturing method thereof. <CIT> relates to various methods of forming a 3D semiconductor device with a dual stress channel. <CIT> relates to a semiconductor device and a method of manufacturing a semiconductor device.

Aspects disclosed herein include Fin Field Effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions. In one aspect, a FinFET is provided. The FinFET includes a substrate and a Fin disposed over the substrate. The Fin includes a source, a drain, and a channel region between the source and drain. A gate is disposed around the channel region. To apply stress to the channel region of the FinFET, a first dielectric material layer is disposed over the substrate and adjacent to one side of the Fin. Additionally, a second dielectric material layer is disposed over the substrate and adjacent to another side of the Fin. In this manner, the first and second dielectric material layers both apply stress along the Fin, including to the channel region. Further, unlike stress induced by growing epitaxial layers, the level of stress that may be applied by the first and second dielectric material layers is not dependent on the volume of each layer. Thus, the first and second dielectric material layers may provide a consistent level of stress on the channel region even as the FinFET area decreases.

In accordance with the present invention, there is provided a method for fabricating a Fin Field Effect transistor (FinFET) as set out in claim <NUM>. Other aspects of the invention can be found in the dependent claims.

In this regard, <FIG> illustrate an exemplary FinFET <NUM> employing first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) to apply stress <NUM> to a channel region <NUM>. The FinFET <NUM> as described herein is designed such that it can be integrated into an integrated circuit (IC) <NUM>. <FIG> illustrates a cross-sectional view of the FinFET <NUM>, while <FIG> illustrates a top-view of the FinFET <NUM>. Components of the FinFET <NUM> are referred to with common element numbers in <FIG>.

With reference to <FIG>, the FinFET <NUM> includes a substrate <NUM> and a Fin <NUM> disposed over the substrate <NUM>. In this example, the Fin <NUM> is disposed in a first direction <NUM>. As illustrated in <FIG>, the Fin <NUM> includes a source <NUM> and a drain <NUM>. The channel region <NUM> of the FinFET <NUM> is disposed in the Fin <NUM> between the source <NUM> and drain <NUM>. Additionally, a gate <NUM> is disposed around the channel region <NUM>. In this example, the gate <NUM> is formed as a high-dielectric metal gate (HKMG). Thus, as described in more detail below, a gate oxide layer <NUM>, a gate dielectric material layer <NUM>, a work function layer <NUM>, and a conductive layer <NUM> are employed to form the gate <NUM>. However, other aspects of the FinFET <NUM> may employ gate types other than the HKMG described herein. Further, the FinFET <NUM> can also employ gate structures <NUM>(<NUM>)-<NUM>(<NUM>) configured to function as dummy gates.

With continuing reference to <FIG>, to apply the stress <NUM> to the channel region <NUM>, the first dielectric material layer <NUM>(<NUM>) is disposed over the substrate <NUM> and adjacent to a first side <NUM>(<NUM>) of the Fin <NUM>. Additionally, the second dielectric material layer <NUM>(<NUM>) is disposed over the substrate <NUM> and adjacent to a second side <NUM>(<NUM>) of the Fin <NUM> that is different from the first side <NUM>(<NUM>). In this example, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) are disposed in the first direction <NUM>. Additionally, top surfaces <NUM>(<NUM>), <NUM>(<NUM>) of the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>), respectively, are lower than a top surface <NUM> of the Fin <NUM> so as to leave space to form the gate <NUM>. Additionally, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) are disposed within an active area boundary <NUM> that surrounds an active layer <NUM> of the FinFET <NUM>. As used herein, the active layer <NUM> of the FinFET <NUM> corresponds to doped regions of the substrate <NUM> on which active elements, such as sources and drains of the FinFET <NUM> may be formed. In this manner, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) can be limited to the active area boundary <NUM> so as to apply the stress <NUM> to the channel region <NUM> while avoiding disposing material to inactive or non-doped regions where the stress <NUM> is not applicable.

With continuing reference to <FIG>, as described in more detail below, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) in this aspect are formed from one or more oxide materials disposed (e.g., deposited) over the substrate <NUM> using a process such as flowable chemical vapor deposition (FCVP) or high aspect ratio processing (HARP). The oxide material(s) of the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) are thermally annealed to apply a particular type or magnitude of the stress <NUM>. For example, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) can be formed from silicon dioxide. Instead of an oxide material, silicon nitride may also be used. If the FinFET <NUM> is an N-type FinFET, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) are thermally annealed such that the stress <NUM> applied to the channel region <NUM> is tensile stress. Conversely, if the FinFET <NUM> is a P-type FinFET, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) are thermally annealed such that the stress <NUM> applied to the channel region <NUM> is compressive stress.

With continuing reference to <FIG>, disposing and annealing the oxide material(s) of the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) as described above applies the stress <NUM> along the Fin <NUM>, including the channel region <NUM>. In this manner, unlike stress induced by other methods, such as by growing epitaxial layers, the level of the stress <NUM> applied by the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) is not dependent on the volume of the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>). More specifically, in an exemplary FinFET employing epitaxial layers instead of the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>), the magnitude of the stress applied by the epitaxial layers correlates to the volume of such layers. Thus, as the area of such a FinFET decreases, so too does the magnitude of the stress induced by the epitaxial layers. This is due, in part, to the property of the crystalline structure of the epitaxial layers inducing less stress as the volume of the crystalline structure is reduced. Thus, unlike the stress induced by epitaxial layers, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) may provide a consistent level of stress <NUM> on the channel region <NUM> even as the area of the FinFET <NUM> decreases.

Further, unlike stress induced by using shallow trench isolation (STI) structures <NUM>(<NUM>), <NUM>(<NUM>) employed to electrically isolate the FinFET <NUM> from other devices in a circuit, applying the stress <NUM> using the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) does not increase area of the FinFET <NUM>. For example, the STI structures <NUM>(<NUM>), <NUM>(<NUM>) can be designed to induce stress by increasing a width of each STI structure <NUM>(<NUM>), <NUM>(<NUM>). An increased width of the STI structures <NUM>(<NUM>), <NUM>(<NUM>) increases the area of the circuit employing the FinFET <NUM>. Additionally, an increased width of the STI structures <NUM>(<NUM>), <NUM>(<NUM>) reduces the magnitude of stress applied to the FinFET <NUM>. More specifically, the magnitude of the stress applied by the STI structures <NUM>(<NUM>), <NUM>(<NUM>) is inversely proportional to the width of the STI structures <NUM>(<NUM>), <NUM>(<NUM>). Thus, as the STI structures <NUM>(<NUM>), <NUM>(<NUM>) expand, the resulting applied stress is reduced. Therefore, in addition to providing consistent stress <NUM> even as the area of the FinFET <NUM> decreases, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) apply the stress <NUM> at a consistent magnitude without increasing area.

<FIG> and <FIG> illustrate an exemplary fabrication process <NUM> employed to fabricate the FinFET <NUM> in <FIG>. Further, <FIG> provide cross-sectional and top view diagrams illustrating respective stages <NUM>(<NUM>)-<NUM>(<NUM>) of the FinFET <NUM> during the fabrication process <NUM>. The cross-sectional and top-view diagrams illustrating the FinFET <NUM> in <FIG> will be discussed in conjunction with the discussion of the exemplary fabrication steps in the fabrication process <NUM> in <FIG> and <FIG>.

In this regard, the fabrication process <NUM> beginning in <FIG> includes providing the substrate <NUM> including the Fin <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). In this example, the Fin <NUM> is disposed in the first direction <NUM>. The fabrication process <NUM> also includes disposing the first dielectric material layer <NUM>(<NUM>) over the substrate <NUM> and adjacent to the first side <NUM>(<NUM>) of the Fin <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). The fabrication process <NUM> further includes disposing the second dielectric material layer <NUM>(<NUM>) over the substrate <NUM> and adjacent to the second side <NUM>(<NUM>) of the Fin <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). In this example, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) are disposed in the first direction <NUM>. As previously described, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) can be disposed over the substrate <NUM> in blocks <NUM> and <NUM> using processes such as flowable chemical vapor deposition (FCVP) or high aspect ratio processing (HARP). Further, the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) can be disposed to be limited to the active area boundary <NUM>.

With continuing reference to <FIG> and <FIG>, thermal annealing is employed to adjust the stress <NUM> applied by the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>). More specifically, the fabrication process <NUM> includes wet annealing the first dielectric material layer <NUM>(<NUM>) and the second dielectric material layer <NUM>(<NUM>) to adjust the stress <NUM> applied to the channel region <NUM> of the FinFET <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). For example, a low temperature wet anneal process of approximately <NUM> degrees Celsius (C) may be employed in block <NUM>. The fabrication process <NUM> also includes dry annealing the first dielectric material layer <NUM>(<NUM>) and the second dielectric material layer <NUM>(<NUM>) to adjust the stress <NUM> applied to the channel region <NUM> of the FinFET <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). For example, a high temperature annealing process of approximately <NUM> C can be employed in block <NUM>.

With continuing reference to <FIG> and <FIG>, the fabrication process <NUM> can include etching the Fin <NUM> corresponding to a source region <NUM> of the FinFET <NUM> on a first side <NUM>(<NUM>) of a gate region <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). The fabrication process <NUM> can also include etching the Fin <NUM> corresponding to a drain region <NUM> of the FinFET <NUM> on a second side <NUM>(<NUM>) of the gate region <NUM> different from the first side <NUM>(<NUM>) (block <NUM>, stage <NUM>(<NUM>) of <FIG>). Further, the fabrication process <NUM> can include growing a source material <NUM> in the source region <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). The fabrication process <NUM> can also include growing a drain material <NUM> in the drain region <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>).

With continuing reference to <FIG> and <FIG>, the fabrication process <NUM> also includes disposing the gate <NUM> with a width W approximately equal to a gate length of the FinFET <NUM> in the gate region <NUM> (block <NUM>, stages <NUM>(<NUM>), <NUM>(<NUM>) in <FIG>, <FIG>). For example, if the FinFET <NUM> is employed in ten (<NUM>) nanometer (nm) technology, then the gate length is approximately equal to <NUM>. In particular, the gate <NUM> is disposed over the Fin <NUM>, the first dielectric material layer <NUM>(<NUM>), and the second dielectric material layer <NUM>(<NUM>). In this example, the gate <NUM> is disposed in a second direction <NUM> substantially orthogonal to the first direction <NUM>. The gate <NUM> can be disposed in block <NUM> by disposing the gate oxide layer <NUM> with a width W approximately equal to the gate length of the FinFET <NUM> in the gate region <NUM> over the Fin <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). Disposing the gate <NUM> in block <NUM> can also include disposing the gate dielectric material layer <NUM> with the width W approximately equal to the gate length of the FinFET <NUM> in the gate region <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). The gate dielectric material layer <NUM> is disposed in block <NUM> over the gate oxide layer <NUM>, the first dielectric material layer <NUM>(<NUM>), and the second dielectric material layer <NUM>(<NUM>). Disposing the gate <NUM> in block <NUM> can also include disposing the work function layer <NUM> with the width W approximately equal to the gate length of the FinFET <NUM> in the gate region <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>). The work function layer <NUM> is disposed over the gate dielectric material layer <NUM>. Further, disposing the gate <NUM> in block <NUM> can include disposing the conductive layer <NUM> with the width W approximately equal to the gate length of the FinFET <NUM> in the gate region <NUM> over the work function layer <NUM> (block <NUM>, stage <NUM>(<NUM>) of <FIG>).

Manufacturing the FinFET <NUM> using the fabrication process <NUM> enables the FinFET <NUM> to provide a consistent level of stress <NUM> to the channel region <NUM> even as the area of the FinFET <NUM> decreases. Additionally, the fabrication process <NUM> includes various steps included in conventional FinFET fabrication methods. Integrating additional steps above for inducing a particular type or magnitude of the stress <NUM> may include one (<NUM>) additional mask as compared to conventional methods. Thus, the FinFET <NUM> can be fabricated to apply the stress <NUM> as described above while minimizing increased manufacturing costs and complexity.

In addition to the FinFET <NUM> in <FIG>, aspects described herein can also include FinFETs employing dielectric material layers corresponding to multiple Fins to apply stress to multiple channel regions. In this regard, <FIG> illustrate an exemplary FinFET <NUM> employing first, second, and third dielectric material layers <NUM>(<NUM>)-<NUM>(<NUM>) to apply the stress <NUM> on first and second channel regions <NUM>(<NUM>), <NUM>(<NUM>). <FIG> illustrates a cross-sectional view of the FinFET <NUM>, while <FIG> illustrates a top-view of the FinFET <NUM>. Components of the FinFET <NUM> are referred to with common element numbers in <FIG>. Further, the FinFET <NUM> includes certain common components with the FinFET <NUM> in <FIG>, as shown by similar element numbers between <FIG>, <FIG>, and thus will not be re-described herein.

With continuing reference to <FIG>, the FinFET <NUM> includes the substrate <NUM> and first and second Fins <NUM>(<NUM>), <NUM>(<NUM>) disposed <NUM> over the substrate <NUM>. In this example, the first and second Fins <NUM>(<NUM>), <NUM>(<NUM>) are disposed in the first direction <NUM>. As a non-limiting example, if the FinFET <NUM> is fabricated in a <NUM> technology (i.e., a <NUM> gate length), the first and second Fins <NUM>(<NUM>), <NUM>(<NUM>) are separated by a distance D approximately equal to <NUM>. As illustrated in <FIG>, the first and second Fins <NUM>(<NUM>), <NUM>(<NUM>) each include a source <NUM>(<NUM>), <NUM>(<NUM>) and a drain <NUM>(<NUM>), <NUM>(<NUM>), respectively. First and second channel regions <NUM>(<NUM>), <NUM>(<NUM>) of the FinFET <NUM> are disposed in the first and second Fins <NUM>(<NUM>), <NUM>(<NUM>), respectively, between the respective source <NUM>(<NUM>), <NUM>(<NUM>) and drain <NUM>(<NUM>), <NUM>(<NUM>). Additionally, the gate <NUM> is disposed around the first and second channel regions <NUM>(<NUM>), <NUM>(<NUM>). Similar to the FinFET <NUM>, gate oxide layers <NUM>(<NUM>), <NUM>(<NUM>) over the first and second Fins <NUM>(<NUM>), <NUM>(<NUM>), respectively, the gate dielectric material layer <NUM>, the work function layer <NUM>, and the conductive layer <NUM> are employed to form the gate <NUM>.

With continuing reference to <FIG>, in addition to the first and second dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) applying the stress <NUM> to the first channel region <NUM>(<NUM>), the FinFET <NUM> is designed such that the stress <NUM> is also applied to the channel region <NUM>(<NUM>). In particular, to apply the stress <NUM> to the channel region <NUM>(<NUM>) of the second Fin <NUM>(<NUM>), a third dielectric material layer <NUM>(<NUM>) is disposed over the substrate <NUM> and adjacent to a second side <NUM>(<NUM>) of the second Fin <NUM>(<NUM>). Additionally, the second dielectric material layer <NUM>(<NUM>) is disposed over the substrate <NUM> and adjacent to a first side <NUM>(<NUM>) of the second Fin <NUM>(<NUM>) that is different from the second side <NUM>(<NUM>). In this example, the second and third dielectric material layers <NUM>(<NUM>), <NUM>(<NUM>) are disposed in the first direction <NUM>. In this matter, the second dielectric material layer <NUM>(<NUM>) also applies the stress <NUM> to the channel region <NUM>(<NUM>). Additionally, the first, second, and third dielectric material layers <NUM>(<NUM>)-<NUM>(<NUM>) are disposed within an active area boundary <NUM> that surrounds an active layer <NUM> of the FinFET <NUM>. Thus, the first, second, and third dielectric material layers <NUM>(<NUM>)-<NUM>(<NUM>) may provide a consistent level of stress <NUM> on the first and second channel regions <NUM>(<NUM>), <NUM>(<NUM>) even as the area of the FinFET <NUM> decreases. For example, as the area of the FinFET <NUM> decreases, the distance D between the first and second Fins <NUM>(<NUM>), <NUM>(<NUM>) also decreases below <NUM>. However, due to the properties of the first, second, and third dielectric material layers <NUM>(<NUM>)-<NUM>(<NUM>) described above, the stress <NUM> remains consistent even as the distance D decreases, unlike stress induced by epitaxial layers.

The elements described herein are sometimes referred to as means for achieving a particular property. In this regard the substrate <NUM> is sometimes referred to herein as "a means for providing a substrate. " The Fin <NUM> is sometimes referred to herein as "a means for providing a Fin over the substrate. " Further, the gate <NUM> is sometimes referred to herein as "a means for providing a gate around the channel region. " The first dielectric material layer <NUM>(<NUM>) is sometimes referred to herein as "a means for providing a first dielectric material layer disposed over the substrate and adjacent to a first side of the Fin, wherein the first dielectric material layer applies stress to the channel region. " The second dielectric material layer <NUM>(<NUM>) is sometimes referred to herein as "a means for providing a second dielectric material layer disposed over the substrate and adjacent to a second side of the Fin different from the first side, wherein the second dielectric material layer applies stress to the channel region.

The FINFETs employing dielectric material layers to apply stress to channel regions according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard, <FIG> illustrates an example of a processor-based system <NUM> that can employ the FinFET <NUM> illustrated in <FIG>, and the FinFET <NUM> illustrated in <FIG>. In this example, the processor-based system <NUM> includes one or more central processing units (CPUs) <NUM>, each including one or more processors <NUM>. The CPU(s) <NUM> may have cache memory <NUM> coupled to the processor(s) <NUM> for rapid access to temporarily stored data. The CPU(s) <NUM> is coupled to a system bus <NUM> and can intercouple master and slave devices included in the processor-based system <NUM>. As is well known, the CPU(s) <NUM> communicates with these other devices by exchanging address, control, and data information over the system bus <NUM>. For example, the CPU(s) <NUM> can communicate bus transaction requests to a memory controller <NUM> as an example of a slave device. Although not illustrated in <FIG>, multiple system buses <NUM> could be provided, wherein each system bus <NUM> constitutes a different fabric.

Other master and slave devices can be connected to the system bus <NUM>. As illustrated in <FIG>, these devices can include a memory system <NUM>, one or more input devices <NUM>, one or more output devices <NUM>, one or more network interface devices <NUM>, and one or more display controllers <NUM>, as examples. The input device(s) <NUM> can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) <NUM> can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) <NUM> can be any device configured to allow exchange of data to and from a network <NUM>. The network <NUM> can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) <NUM> can be configured to support any type of communications protocol desired. The memory system <NUM> can include one or more memory units <NUM>(<NUM>)-<NUM>(M).

The CPU(s) <NUM> may also be configured to access the display controller(s) <NUM> over the system bus <NUM> to control information sent to one or more displays <NUM>. The display controller(s) <NUM> sends information to the display(s) <NUM> to be displayed via one or more video processors <NUM>, which process the information to be displayed into a format suitable for the display(s) <NUM>. The display(s) <NUM> can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc..

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques.

Claim 1:
A method (<NUM>) for fabricating a Fin Field Effect transistor, FinFET, (<NUM>; <NUM>) employing dielectric material layers for applying stress on a channel region (<NUM>), comprising:
providing (<NUM>) a substrate comprising a Fin (<NUM>);
disposing (<NUM>) a first dielectric material layer (<NUM>(<NUM>)) over the substrate (<NUM>) and adjacent to the channel region (<NUM>) on a first side of the Fin (<NUM>);
disposing (<NUM>) a second dielectric material layer (<NUM>(<NUM>)) over the substrate (<NUM>) and adjacent to the channel region (<NUM>) on a second side of the Fin (<NUM>), wherein the second side is different from the first side;
wet annealing (<NUM>) the first dielectric material layer (<NUM>(<NUM>)) and the second dielectric material layer (<NUM>(<NUM>)) to adjust stress applied to the channel region (<NUM>) of the FinFET (<NUM>; <NUM>);
dry annealing (<NUM>) the first dielectric material layer (<NUM>(<NUM>)) and the second dielectric material layer (<NUM>(<NUM>)) to adjust stress applied to the channel region (<NUM>) of the FinFET (<NUM>; <NUM>); and
disposing (<NUM>) a gate (<NUM>) with an extension in a direction of current flow in the channel region (<NUM>) approximately equal to a gate length of the FinFET (<NUM>; <NUM>) in a gate region over the Fin (<NUM>), the first dielectric material layer (<NUM>(<NUM>)), and the second dielectric material layer (<NUM>(<NUM>)).