Patent Description:
A semiconductor structure may include a memory cell, which typically includes a transistor and a capacitor electrically connected to the transistor. The capacitor stores data information, and the transistor controls read/write of the data information in the capacitor. A gate of the transistor is electrically connected to a word line (WL), and on or off of the transistor is controlled by means of a voltage of the WL. One of a source and a drain of the transistor is electrically connected to a bit line (BL), and the other one of the source and the drain is electrically connected to the capacitor. The data information is stored or outputted by means of the BL. Related technology is known from <CIT>.

With miniature of a dimension of the semiconductor structure, single-point bridging likely occurs during fabrication of the semiconductor structure, resulting in a short circuit due to mutual contaction between conductive contacts, which adversely affects performance of the semiconductor structure.

In view of the above problems, embodiments of the present disclosure provide a one-transistor one-capacitor (1T1C) dynamic random access memory (DRAM) and a method for fabricating the same, to reduce or avoid mutual contaction between the conductive contacts, and to improve performance of the semiconductor structure.

The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features and advantages of the present application will become apparent from the description, drawings and claims.

To reduce a contact short circuit between conductive contacts, an embodiment of the present disclosure provides a method for fabricating a semiconductor structure. In the method, a plurality of first trenches arranged at intervals and extending along a first direction are formed in a barrier layer, a filling layer is formed in each of the plurality of first trenches, then a first mask layer is formed on the filling layer and the barrier layer, and a plurality of second trenches arranged at intervals and extending along a second direction are formed in the first mask layer. When the filling layer is removed along the second trench to form a filling hole, contact holes are separated by the barrier layer opposite to the second trench, which may reduce or avoid communication between adjacent contact holes, such that a short circuit due to mutual contaction between first conductive layers subsequently formed in the contact holes may be reduced or avoided, and thus performance of the semiconductor structure may be improved.

To make the above objectives, features, and advantages of the embodiments of the present disclosure more apparent and lucid, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely some but not all of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

Referring to <FIG> is a flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. The method includes following steps.

Step S101: providing a substrate, where a plurality of active areas arranged at intervals are provided in the substrate, and the substrate is covered with an insulating layer and a barrier layer stacked sequentially.

Referring to <FIG>, the substrate <NUM> may be a substrate containing a semiconductor material, such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a germanium arsenic substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, etc..

A plurality of active areas (not marked in the figure) arranged at intervals are provided in the substrate <NUM>, and the active areas are electrically connected to at least one capacitor (not marked in the figure). Each active area may be defined by means of shallow trench isolation (STI), which is not marked in the figure. In some embodiments, part of the substrate <NUM> is removed to a preset depth by means of an etching process to form grooves surrounding the plurality of active areas, and then an insulating material is deposited in the grooves to isolate the active areas. The insulating material may be silicon oxide or silicon nitride, etc..

A plurality of word lines (not marked in the figure) arranged at intervals are also formed in the substrate <NUM>, the plurality of word lines (WLs) extend along a third direction, and the WLs are insulated from the active areas. The above WLs may be buried word lines (BWLs), and the active areas are inclined with respect to an extension direction (the third direction) of the WLs. In some embodiments, the active areas are also inclined with respect to an extension direction (the first direction) of bit lines (BLs). With this arrangement, arrangement density of capacitors may be increased, thereby increasing storage capacity of the semiconductor structure.

With continued reference to <FIG>, the substrate <NUM> is also covered with an insulating layer <NUM>, and the insulating layer <NUM> is covered with a barrier layer <NUM>. A material of the insulating layer <NUM> may be the same as the insulating material in the STI. In this way, the STI and the insulating layer <NUM> may be fabricated simultaneously in the same deposition process. That is, the insulating material is deposited in the grooves and on the substrate <NUM>, thereby simplifying fabrication processes of the semiconductor structure. A material of the barrier layer <NUM> may include silicon nitride or silicon oxynitride, or the like, to etch a stop layer. For example, the material of the insulating layer <NUM> is silicon oxide, and the material of the barrier layer <NUM> is silicon nitride.

Step S102: forming a plurality of first trenches arranged at intervals in the barrier layer, where each of the plurality of first trenches extends along the first direction and penetrates through the barrier layer.

Referring to <FIG>, a plurality of first trenches <NUM> are formed in the barrier layer <NUM>, and the plurality of first trenches <NUM> are arranged at intervals and extend along the first direction. As shown in <FIG>, the plurality of first trenches <NUM> extend along a direction perpendicular to a paper surface. Each of the first trenches <NUM> penetrates through the barrier layer <NUM>, such that the first trench <NUM> exposes the insulating layer <NUM>.

Step S103: forming a filling layer in each of the plurality of first trenches, and forming a first mask layer on the barrier layer and the filling layer.

Referring to <FIG>, a filling layer <NUM> is formed in each first trench <NUM> by means of a deposition process or the like, and the filling layer <NUM> fills up the first trench <NUM>. A material of the filling layer <NUM> is different from that of the barrier layer <NUM>, and the filling layer <NUM> has a greater selectivity with respect to the barrier layer <NUM>, to facilitate subsequent removal of the filling layer <NUM> separately. For example, the material of the filling layer <NUM> may be spin on hardmasks (SOH).

For example, as shown in <FIG>, a top surface of the filling layer <NUM> may be flush with that of the barrier layer <NUM>, where the top surface refers to a surface facing away from the substrate <NUM>, i.e., an upper surface shown in <FIG>. In the top view shown in <FIG>, a region filled with a pattern is the barrier layer <NUM>, and a white region is the filling layer <NUM>. The pattern is only for the convenience of distinguishing the barrier layer <NUM> from the filling layer <NUM>, and has no other meaning. As shown in <FIG>, the filling layer <NUM> may be a plurality of strip-shaped structures arranged at intervals, and each strip-shaped structure extends along the first direction (X direction shown in <FIG>).

After the filling layer <NUM> is formed, a first mask layer <NUM> is formed on the barrier layer <NUM> and the filling layer <NUM> respectively, and the first mask layer <NUM> is at least in contact with the filling layer <NUM>. It is to be understood that, when other film layers remain on the barrier layer <NUM>, the first mask layer <NUM> covers the remaining film layers on the barrier layer <NUM> and the filling layer <NUM>. When there is no film layer on the barrier layer <NUM>, as shown in <FIG>, the first mask layer <NUM> covers the barrier layer <NUM> and the filling layer <NUM>.

In an example, referring to <FIG>, the first mask layer <NUM> may be a stack structure, which includes a first foundation layer <NUM>. The first foundation layer <NUM> is in contact with the filling layer <NUM>. The material of the first foundation layer <NUM> may be the same as the material of the filling layer <NUM>. For example, the first foundation layer <NUM> and the filling layer <NUM> may be formed by means of a simple patterning process, to simplify the fabrication process of the semiconductor structure. For example, the first foundation layer <NUM> and the filling layer <NUM> may be formed by means of a single deposition process.

Step S104: forming a plurality of second trenches arranged at intervals in the first mask layer, where each of the plurality of second trenches extends along the second direction and exposes the filling layer.

Referring to <FIG>, a plurality of second trenches <NUM> are formed in the first mask layer <NUM> by means of an etching process, and the plurality of second trenches <NUM> are arranged at intervals and extend along the second direction. The second direction is different from the extension direction (the third direction) of the WLs and the extension direction (the first direction) of the BLs. The filling layer <NUM> is exposed in each second trench <NUM> to facilitate subsequent removal of the filling layer <NUM>.

It is to be understood that, there are overlapped regions between orthographic projections of the second trenches <NUM> on the substrate <NUM> and orthographic projections of the first trenches <NUM> on the substrate <NUM>. These overlapped regions are arranged in an array, and are in the shape of a parallelogram, such as a rhombus.

Step S105: removing the filling layer exposed in each of the plurality of second trenches and the insulating layer corresponding to the filling layer to form a contact hole, where the contact hole exposes each of the plurality of active areas.

Referring to <FIG>, each second trench <NUM> exposes the filling layer <NUM> and the barrier layer <NUM>. By adjusting the material of the filling layer <NUM> and the material of the barrier layer <NUM>, the filling layer <NUM> and the barrier layer <NUM> have larger selectivity. In this way, damage to the barrier layer <NUM> is reduced when the filling layer <NUM> is removed. As shown in <FIG>, the filling layer <NUM> and the insulating layer <NUM> are etched along each second trench <NUM>, and the filling layer <NUM> exposed in the second trench <NUM> and the insulating layer <NUM> corresponding to the filling layer <NUM> removed are removed to form contact holes <NUM>. The contact holes <NUM> penetrate through the filling layer <NUM> and the insulating layer <NUM> to expose the active areas.

In the method for fabricating the semiconductor structure in the embodiments of the present disclosure, a plurality of first trenches <NUM> arranged at intervals and extending along the first direction are formed in the barrier layer <NUM>, the filling layer <NUM> is formed in each of the first trenches <NUM>, and then the first mask layer <NUM> is formed on the filling layer <NUM> and the barrier layer <NUM>. A plurality of second trenches <NUM> arranged at intervals and extending along the second direction are formed in the first mask layer <NUM>, where the second trenches <NUM> expose the filling layer <NUM>. Next, the exposed filling layer <NUM> is removed to form the contact holes <NUM>. The contact holes <NUM> are defined by means of a region where the orthographic projection of each second trench <NUM> on the barrier layer <NUM> overlaps with that of each first trench <NUM>, and the contact holes <NUM> are separated by the barrier layer <NUM> opposite to the second trench <NUM>, which may reduce or avoid communication between adjacent contact holes <NUM>, such that a short circuit due to mutual contaction between the first conductive layers subsequently formed in the contact holes <NUM> may be reduced or avoided, and thus the performance of the semiconductor structure may be improved.

Referring to <FIG>, according to the invention, the step (Step S101) of forming, in the barrier layer, the plurality of first trenches arranged at intervals extending along the first direction and penetrating through the barrier layer includes following steps.

Step S1011: forming a third mask layer, a second mask layer and a first photoresist layer sequentially stacked on the barrier layer.

As shown in <FIG>, a third mask layer <NUM> is deposited on the barrier layer <NUM>, a second mask layer <NUM> is deposited on the third mask layer <NUM>, and a first photoresist layer <NUM> is coated on the second mask layer <NUM>. Along a direction away from the substrate <NUM>, the barrier layer <NUM>, the third mask layer <NUM>, the second mask layer <NUM> and the first photoresist layer <NUM> are sequentially stacked. The first photoresist layer <NUM> is a patterned first photoresist layer <NUM>. A first pattern is formed on the first photoresist layer <NUM> through processes such as exposure and development. The first pattern includes a plurality of first through grooves <NUM>, and each of the first through groove <NUM> exposes the top surface of the second mask layer <NUM>.

For example, the second mask layer <NUM> includes a second foundation layer <NUM> positioned on the third mask layer <NUM>, and a second anti-reflection layer <NUM> positioned on the second foundation layer <NUM>. The second anti-reflection layer <NUM> may absorb light of the first photoresist layer <NUM> during the exposure process, to prevent the light from being reflected and adversely affecting accuracy of the first pattern. The material of the second anti-reflection layer <NUM> may be an organic material having similar etching properties to the first photoresist layer <NUM>, or a combination thereof. The second foundation layer <NUM> may have higher selectivity with respect to the second anti-reflection layer <NUM>. For example, a material of the second foundation layer <NUM> may be SOH, silicon oxynitride, silicon oxide, silicon nitride, or the like.

Step S1012, etching the second mask layer using the first photoresist layer as a mask to form a third trench in the second mask layer, where the third trench extends along the first direction.

The second mask layer <NUM> is etched using the first photoresist layer <NUM> as a mask to remove the second mask layer <NUM> not covered by the first photoresist layer <NUM>, and the second mask layer <NUM> covered by the first photoresist layer <NUM> is retained, referring to <FIG>. After etching, a third trench <NUM> is formed in the second mask layer <NUM>, and the third trench <NUM> extends along the first direction. The third trench <NUM> penetrates through the second foundation layer <NUM> and the second anti-reflection layer <NUM>, and the third trench <NUM> exposes the top surface of the third mask layer <NUM>. During this process, the first photoresist layer <NUM> may be partially removed or even completely consumed. For example, as shown in <FIG> and <FIG>, the first photoresist layer <NUM> is completely removed, such that the top surface of the second anti-reflection layer <NUM> is exposed. In this case, there is no need to remove the first photoresist layer <NUM> separately, which simplifies the fabrication processes of the semiconductor structure.

Step S1013, forming a first intermediate layer on a side wall and a bottom of the third trench respectively, where the first intermediate layer positioned in the third trench defines a first filling groove.

Referring to <FIG>, a first intermediate layer <NUM> is deposited on the side wall and the bottom of the third trench <NUM>, and the first intermediate layer <NUM> positioned in the third trench <NUM> defines the first filling groove. When the second mask layer <NUM> includes the second foundation layer <NUM> and the second anti-reflection layer <NUM>, the first intermediate layer <NUM> covers a side surface of the second foundation layer <NUM>, a side surface of the second anti-reflection layer <NUM>, and the third mask layer <NUM>.

For example, the selectivity of the first intermediate layer <NUM> to the second foundation layer <NUM> is greater than or equal to <NUM>. In this way, the damage to the second foundation layer <NUM> is reduced when the first intermediate layer <NUM> is etched, the second foundation layer <NUM> is retained, and the second foundation layer <NUM> retained is subsequently configured to etch the third mask layer <NUM> as a mask.

In some examples of the present disclosure, as shown in <FIG>, the step of forming the first intermediate layer <NUM> on the side wall and the bottom of the third trench <NUM> respectively includes following steps.

The first intermediate layer <NUM> is deposited on the side wall and the bottom of the third trench <NUM> and on the second anti-reflection layer <NUM>. As shown in <FIG>, the first intermediate layer <NUM> covers the second mask layer <NUM> and the third mask layer <NUM> to facilitate the formation of the first intermediate layer <NUM>.

Step S1014: forming a first dielectric layer in the first filling groove.

A first dielectric layer <NUM> is deposited and formed in the first filling groove, and the first dielectric layer <NUM> fills up the first filling groove. As shown in <FIG>, a material of the first dielectric layer <NUM> may be the same as that of the second foundation layer <NUM>, for example, SOH. In some examples, the first dielectric layer <NUM> may also cover the first intermediate layer <NUM>, and a part of the first dielectric layer <NUM> may be removed by means of a planarization process subsequently, such as chemical mechanical planarization (CMP), to expose the first intermediate layer <NUM>.

Step S1015: removing part of the first intermediate layer to form a plurality of first etching grooves arranged at intervals.

The first intermediate layer <NUM> positioned on the side wall of the third trench <NUM> is removed by etching to form the plurality of first etching grooves arranged at intervals. In some embodiments, the step of removing part of the first intermediate layer <NUM> to form the plurality of first etching grooves arranged at intervals includes following steps.

Referring to <FIG> and <FIG>, part of the first intermediate layer <NUM>, part of the first dielectric layer <NUM> and the second anti-reflection layer <NUM> are removed to expose the first intermediate layer <NUM> on the side wall of the third trench <NUM>. That is, the second anti-reflection layer <NUM> and the film layer on the second anti-reflection layer <NUM> are removed to expose the second foundation layer <NUM> and the first intermediate layer <NUM>. For example, the second foundation layer <NUM> and the first intermediate layer <NUM> on the side wall of the third trench <NUM> are exposed by means of the planarization process.

After part of the first intermediate layer <NUM>, part of the first dielectric layer <NUM>, and the second anti-reflection layer <NUM> are removed to expose the first intermediate layer <NUM> on the side wall of the third trench <NUM>, and the exposed part of the first intermediate layer <NUM> is removed to form the first etching groove. For example, the exposed first intermediate layer <NUM> is removed by etching to form the first etching groove that exposes the third mask layer <NUM>.

Step S1016: etching the third mask layer along the first etching groove to form a second etching groove in the third mask layer.

In some embodiments, as shown in <FIG>, the third mask layer <NUM> includes a third foundation layer <NUM> disposed on the barrier layer <NUM> and a third anti-reflection layer <NUM> disposed on the third foundation layer <NUM>. A material of the third foundation layer <NUM> may be the same as that of the second foundation layer <NUM>, and a material of the third anti-reflection layer <NUM> may be the same as that of the second anti-reflection layer <NUM>, to reduce types of materials required during the fabrication of the semiconductor structure. In addition, the third mask layer <NUM> is etched by means of the first etching groove, without using photoresist, thereby reducing number of times of photolithography.

Referring to <FIG>, while etching the third mask layer <NUM> along each of the plurality of first etching grooves to form the second etching groove <NUM> in the third mask layer <NUM>, the third anti-reflection layer <NUM> and remaining film layers thereon are also removed, at least part of the third foundation layer <NUM> is retained, and the second etching groove <NUM> is formed in the third foundation layer <NUM>. The third anti-reflection layer <NUM> and the third foundation layer <NUM> are etched along the first etching groove to form the second etching groove <NUM>. During this process, the third anti-reflection layer <NUM>, the second foundation layer <NUM>, the first intermediate layer <NUM> and the first filling layer <NUM> are also removed simultaneously. That is, the third foundation layer <NUM> is retained, and the second etching groove <NUM> is formed in the third foundation layer <NUM>.

Step S1017: etching the barrier layer along the second etching groove to form the plurality of first trenches in the barrier layer.

Referring to <FIG> and <FIG>, the barrier layer <NUM> is etched along the second etching groove <NUM>, the barrier layer <NUM> covered by the third foundation layer <NUM> is retained, the barrier layer <NUM> not covered by the third foundation layer <NUM> is removed, and the first trench <NUM> is formed between the barrier layers <NUM> retained. As shown in <FIG> and <FIG>, after the first trench <NUM> is formed, the barrier layer <NUM> may also have a remaining third foundation layer <NUM>. That is, the remaining third foundation layer <NUM> does not need to be removed separately, and this part of the third foundation layer <NUM> may be removed in the subsequent process, to simplify the fabrication of the semiconductor structure.

As shown in the top view of <FIG>, for ease of distinction, the region filled with the pattern is the barrier layer <NUM>, the blank region is the third foundation layer <NUM>, and the barrier layer <NUM> and the third foundation layer <NUM> are alternately arranged in sequence.

Referring to <FIG>, in some embodiments, the step (Step S103) of forming the filling layer <NUM> in each of the plurality of first trenches <NUM>, and forming the first mask layer <NUM> on the barrier layer <NUM> and the filling layer <NUM> may include: forming the filling layer <NUM> in each of the plurality of first trenches <NUM>, and forming a first foundation layer <NUM> in the second etching trench <NUM> and on the third foundation layer <NUM>, where the first foundation layer <NUM> fills up the second etching trench <NUM>, and covers the third foundation layer <NUM>.

As shown in <FIG>, the first foundation layer <NUM> is deposited in the first trench <NUM>, in the second etching groove <NUM> and on the third foundation layer <NUM> respectively, and the first foundation layer <NUM> covers the top surface and the side surface of the third foundation layer <NUM> and the top surface of the filling layer <NUM>. In some embodiments, the material of the first foundation layer <NUM> is the same as the material of the third foundation layer <NUM>, such that the first foundation layer <NUM> and the third foundation layer <NUM> are integrated, which facilitates subsequent fabrication of the semiconductor structure. Furthermore, a material of the first foundation layer <NUM>, a material of the third foundation layer <NUM>, and a material of the filling layer <NUM> are the same. The first foundation layer <NUM> is in contact with the third foundation layer <NUM> and the filling layer <NUM> respectively, such that the first foundation layer <NUM>, the third foundation layer <NUM> and the filling layer <NUM> may form a whole, and thus subsequently the material of the first foundation layer <NUM>, the material of the third foundation layer <NUM>, and the filling layer <NUM> may be etched simultaneously, thereby simplifying the fabrication steps of the semiconductor structure.

Correspondingly, referring to <FIG>, the step (Step S104) of forming the plurality of second trenches <NUM> arranged at intervals in the first mask layer may include following steps.

Step S1041: forming a fourth mask layer on the first mask layer, and forming a second photoresist layer on the fourth mask layer.

Referring to <FIG> and <FIG>, a fourth mask layer <NUM> is deposited on the first mask layer <NUM>, and a second photoresist layer <NUM> is coated on the fourth mask layer <NUM>. The second photoresist layer <NUM> is a patterned second photoresist layer <NUM>. A second pattern is formed on the second photoresist layer <NUM> through processes such as exposure and development. The second pattern includes a plurality of second through grooves <NUM>, where each of the second through grooves <NUM> extends along the second direction and penetrates through the second photoresist layer <NUM>, and each of the second through grooves <NUM> exposes the top surface of the fourth mask layer <NUM>.

For example, the fourth mask layer <NUM> includes a fourth foundation layer <NUM> positioned on the first mask layer <NUM> and a fourth anti-reflection layer <NUM> positioned on the fourth foundation layer <NUM>. The fourth anti-reflection layer <NUM> is configured to absorb the light of the second photoresist layer <NUM> during the exposure process to prevent the light from being reflected. The material of the fourth anti-reflection layer <NUM> may be an organic material having similar etching properties to the first photoresist layer <NUM>, or a combination thereof. The material of the fourth foundation layer <NUM> may be the same as that of the first foundation layer <NUM>, to reduce the material required in the fabrication of the semiconductor structure.

It should be noted that the first mask layer <NUM> may include a first foundation layer <NUM> and a first anti-reflection layer <NUM> formed on the first foundation layer <NUM>. By disposing the first anti-reflection layer <NUM>, the first foundation layer <NUM> may be separated from the fourth foundation layer <NUM>. A material of the first anti-reflection layer <NUM> may be the same as that of the fourth anti-reflection layer <NUM>. It is to be understood that, along the direction away from the substrate <NUM>, the first foundation layer <NUM>, the first anti-reflection layer <NUM>, the fourth foundation layer <NUM>, the fourth anti-reflection layer <NUM> and the second photoresist layer <NUM> are sequentially stacked.

Step S1042: etching the fourth mask layer using the second photoresist layer as a mask to form a fourth trench in the fourth mask layer.

Referring to <FIG>, the fourth mask layer <NUM> is etched using the second photoresist layer <NUM> as a mask. After etching, a fourth trench <NUM> is formed in the fourth mask layer <NUM>, and the fourth trench <NUM> extends along the second direction. The fourth trench <NUM> penetrates through the fourth foundation layer <NUM> and the fourth anti-reflection layer <NUM>, and the fourth trench <NUM> exposes the top surface of the first mask layer <NUM>. During this process, the second photoresist layer <NUM> may be partially removed or even completely consumed. For example, as shown in <FIG>, the second photoresist layer <NUM> is completely removed, and the top surface of the fourth mask layer <NUM> is exposed. Of course, if the second photoresist layer <NUM> remains, the remaining second photoresist layer <NUM> may be removed by means of an ashing process separately, or may be removed simultaneously when the first mask layer <NUM> is subsequently etched.

Step S1043: forming a second intermediate layer on a side wall and a bottom of the fourth trench, where the second intermediate layer positioned in the fourth trench defines a second filling groove.

Referring to <FIG> and <FIG>, a second intermediate layer <NUM> is deposited and formed on the side wall and the bottom of the fourth trench <NUM>, and the second intermediate layer <NUM> positioned in the fourth trench <NUM> defines the second filling groove. When the fourth mask layer <NUM> includes the fourth foundation layer <NUM> and the fourth anti-reflection layer <NUM>, the selectivity of the second intermediate layer <NUM> to the fourth foundation layer <NUM> is greater than or equal to <NUM>. In this way, the damage to the fourth foundation layer <NUM> is reduced when the second intermediate layer <NUM> is etched, the fourth foundation layer <NUM> is retained, and the fourth foundation layer <NUM> retained is subsequently configured to etch the first mask layer <NUM> as a mask.

For example, as shown in <FIG>, the step of forming the second intermediate layer <NUM> on the side wall and the bottom of the fourth trench <NUM> includes: depositing the second intermediate layer <NUM> on the side wall and the bottom of the fourth trench <NUM> by using the fourth mask layer <NUM> as a mask, to facilitate the formation of the second intermediate layer <NUM>.

Step S1044: forming a second dielectric layer in the second filling groove.

The second dielectric layer <NUM> is deposited and formed in the second filling groove, and the second dielectric layer <NUM> fills up the second filling groove. A material of the second dielectric layer <NUM> may be the same as that of the fourth foundation layer <NUM>, for example, SOH.

Step S1045: removing part of the second intermediate layer to form a plurality of third etching grooves arranged at intervals.

Referring to <FIG>, the second intermediate layer <NUM> positioned on the side wall of the fourth trench <NUM> is removed by etching to form a plurality of third etching grooves <NUM> arranged at intervals. As shown in <FIG>, in some embodiments, the second intermediate layer <NUM> is etched, and the second intermediate layer <NUM> positioned on the side wall of the fourth trench <NUM> and on the fourth mask layer <NUM> is removed to form the third etching grooves <NUM>, where each of the third etching grooves <NUM> exposes the top surface of the fourth mask layer <NUM>.

As shown in <FIG>, in some examples, when the second intermediate layer <NUM> is etched, part of the second dielectric layer <NUM> and part of the fourth mask layer <NUM> may also be removed by etching. In some embodiments, part of the second dielectric layer <NUM> is removed, the fourth anti-reflection layer <NUM> of the fourth mask layer <NUM> is removed, and part of the fourth foundation layer <NUM> of the fourth mask layer <NUM> is removed. As shown in <FIG>, the second intermediate layer <NUM> positioned at the bottom of the second filling groove and part of the fourth foundation layer <NUM> positioned on the second intermediate layer <NUM> are retained.

Step S1046: etching the first mask layer along each of the plurality of third etching grooves to form the plurality of second trenches in the first mask layer.

In some examples, as shown in <FIG>, the barrier layer <NUM> and the filling layer <NUM> are both covered with the first foundation layer <NUM>, and in the process of etching the first mask layer <NUM> along the third etching groove <NUM>, the second trench <NUM> penetrates through the first foundation layer <NUM>, and the bottom of the second trench <NUM> exposes the barrier layer <NUM> and the filling layer <NUM>.

In some other examples, as shown in <FIG>, the barrier layer <NUM> is covered with the third foundation layer <NUM>, the third foundation layer <NUM> and the filling layer <NUM> are covered with the first foundation layer <NUM>, part of the first foundation layer <NUM> is filled between the third foundation layers <NUM>, and the first foundation layer <NUM> positioned above the third foundation layer <NUM> is a whole-layer structure. In the process of etching the first mask layer <NUM> along the third etching groove <NUM>, the first foundation layer <NUM> positioned above the third foundation layer <NUM> is etched first, the second trench <NUM> is formed in the first foundation layer <NUM>, and the third foundation layer <NUM> and the first foundation layer <NUM> are exposed at the bottom of the second trench <NUM>; and then, at least the first foundation layer <NUM> positioned at the bottom of the second trench <NUM> is etched, such that part of the bottom of the second trench <NUM> extends to the filling layer <NUM>. For example, the first foundation layer <NUM> exposed at the bottom of the second trench <NUM> is etched, such that part of the bottom of the second trench <NUM> extends to the filling layer <NUM>, and the filling layer <NUM> is exposed at the bottom of the second trench <NUM>.

When the material of the first foundation layer <NUM> is the same as the material of the third foundation layer <NUM>, referring to <FIG>, the first foundation layer <NUM> and the third foundation layer <NUM> are integrated. In this way, after the second trench <NUM> is formed in the first foundation layer <NUM> positioned above the third foundation layer <NUM>, the first foundation layer <NUM> and the third foundation layer <NUM> positioned at the bottom of the second trench <NUM> may be etched to form strip-shaped second trenches <NUM>, to ensure that the filling layer <NUM> is fully exposed. As shown in <FIG>, the first foundation layer <NUM> and the third foundation layer <NUM> are etched simultaneously, part of the bottom of the second trench <NUM> extends to the filling layer <NUM>, and other part of the bottom of the second trench <NUM> exposes the barrier layer <NUM>.

It is to be understood that the first mask layer <NUM> may include the first foundation layer <NUM> and the first anti-reflection layer <NUM> formed on the first foundation layer <NUM>. In the process of etching the first mask layer <NUM> along the third etching groove <NUM>, the first anti-reflection layer <NUM> is first etched, and the second trench <NUM> is formed in the first anti-reflection layer <NUM>; and then the first foundation layer <NUM> is etched, such that the second trench <NUM> extends into the first foundation layer <NUM>.

It is to be noted that, referring to <FIG>, in this embodiment of the present disclosure, the first mask layer <NUM> includes a first foundation layer <NUM> in contact with the filling layer <NUM>, and a first anti-reflection layer <NUM> provided on the first foundation layer <NUM>. The first anti-reflection layer <NUM> and remaining film layers thereon are removed while removing the filling layer <NUM> exposed in each of the plurality of second trenches <NUM> and the insulating layer <NUM> corresponding to the filling layer <NUM>, to form the contact holes <NUM> exposing the active areas (Step S105), and at least part of the first foundation layer <NUM> is retained. In this way, after the contact holes <NUM> are formed, types of film layers above the barrier layer <NUM> and the remaining filling layer <NUM> are reduced, to facilitate removal of the film layers.

It is to be understood that, when the barrier layer <NUM> is covered with the third foundation layer <NUM>, and the third foundation layer <NUM> and the filling layer <NUM> are covered with the first foundation layer <NUM>, as shown in <FIG>, the first anti-reflection layer <NUM> and the remaining film layers thereon are removed, and part of the first foundation layer <NUM> may also be retained when at least part of the first foundation layer <NUM> is retained. When the material of the first foundation layer <NUM> is the same as the material of the third foundation layer <NUM>, the remaining first foundation layer <NUM> and the remaining third foundation layer <NUM> may be removed simultaneously by means of once etching, thereby simplifying the fabrication process of the semiconductor structure.

Referring to <FIG>, in some embodiments, after the step (Step S105) of removing the filling layer <NUM> exposed in the second trench <NUM> and the insulating layer <NUM> corresponding to the filling layer <NUM> to form the contact holes <NUM> exposing the active areas, the method also includes following steps.

Step a: removing the first mask layer and the filling layer to expose each of the plurality of first trenches.

Referring to <FIG>, after the contact holes <NUM> are formed, the first mask layer <NUM> and the filling layer <NUM> are removed, such that the first trenches <NUM> are exposed. The first trenches <NUM> are formed between adjacent barrier layers <NUM>, and each of the first trenches <NUM> is communicated with at least one contact hole <NUM>.

As shown in <FIG>, after other film layers on the barrier layers <NUM> and the filling layer <NUM> between the barrier layers <NUM> are removed, the barrier layer <NUM> is exposed, and the insulating layer <NUM> and the substrate <NUM> are also exposed. As shown in the top view of <FIG>, the substrate <NUM> and the insulating layer <NUM> are exposed between the adjacent barrier layers <NUM>. What is shown in gray is the substrate <NUM>, i.e., the active areas of the substrate <NUM>; and what is shown in white is the insulating layer <NUM>.

Step b: forming a first conductive layer in each of the plurality of first trenches and in the contact hole, where the first conductive layer fills the contact hole and fills at least part of the plurality of first trenches.

Referring to <FIG> and <FIG>, a first conductive layer <NUM> is deposited in the first trench <NUM> and in the contact hole <NUM>, where a material of the first conductive layer <NUM> may be polysilicon. The first conductive layer <NUM> is filled in the contact hole <NUM> to come into contact with the active area to implement an electrical connection. The first conductive layer <NUM> may also be filled in the first trench <NUM>, and the top surface of the first conductive layer <NUM> is lower than the top surface of the barrier layer <NUM>. As shown in <FIG>, the first conductive layer <NUM> is filled at the bottom of the first trench <NUM> to prevent the first conductive layers <NUM> from being connected together, thereby ensuring normal operation of the semiconductor structure.

Step c: forming a second conductive layer on the first conductive layer and the barrier layer, and forming a first support layer on the second conductive layer.

Referring to <FIG>, a second conductive layer <NUM> is formed on the first conductive layer <NUM> and the barrier layer <NUM>, and the second conductive layer <NUM> fills the first trench <NUM> and covers the barrier layer <NUM>. The second conductive layer <NUM> may include a diffusion barrier layer <NUM> close to the substrate <NUM>, and a metal layer disposed on the diffusion barrier layer <NUM>.

The diffusion barrier layer <NUM> can prevent metal from diffusing into the first conductive layer <NUM>. Materials of the diffusion barrier layer <NUM> may include titanium, titanium nitride, tantalum, tantalum nitride or aluminum nitride, etc. The diffusion barrier layer <NUM> may be a single layer, or may also be a stack layer. A material of the metal layer may be copper, aluminum, tungsten, etc. For example, the material of the diffusion barrier layer <NUM> is titanium nitride, and the material of the metal layer is tungsten.

As shown in <FIG>, the second conductive layer <NUM> is also covered with a first support layer <NUM>, where a material of the first support layer <NUM> may be an insulating material, such as silicon nitride or silicon oxynitride, to provide electrical isolation for the second conductive layer <NUM>.

Step d: removing part of the first support layer and part of the second conductive layers to form a plurality of fifth trenches arranged at intervals and extending along the first direction, where each of the plurality of fifth trenches exposes the barrier layer.

Referring to <FIG>, the first support layer <NUM> and the second conductive layer <NUM> are etched to form the fifth trenches <NUM> exposing the barrier layer <NUM>. The remaining second conductive layer <NUM> forms a plurality of second conductive layer arranged at intervals, where the plurality of second conductive layers <NUM> are in one-to-one correspondence with the plurality of first conductive layers <NUM>, and the corresponding second conductive layers <NUM> are electrically connected to the first conductive layers <NUM>.

In an example, referring to <FIG>, the fifth trenches <NUM> are formed in the first support layer <NUM> and the second conductive layer <NUM> by means of Self-Aligned Double Patterning (SADP) or Self-Aligned Quadra Patterning (SAQP), to increase density of the fifth trenches <NUM> and reduce critical dimensions (CD) of the fifth trenches <NUM>.

In some embodiments, an amorphous carbon layer <NUM>, a first silicon oxynitride layer <NUM>, a hard mask layer <NUM>, a second silicon oxynitride layer <NUM> and a third photoresist layer <NUM> stacked are deposited and formed on the first support layer <NUM>. The third photoresist layer <NUM> has a third pattern, where the third pattern includes a plurality of third through grooves <NUM> arranged at intervals, and each of the third through grooves <NUM> exposes the second silicon oxynitride layer <NUM>. The second silicon oxynitride layer <NUM> is configured to absorb light when the third photoresist layer <NUM> is exposed. The second silicon oxynitride layer <NUM> and the hard mask layer <NUM> are etched using the third photoresist layer <NUM> as a mask, such that the third pattern is transferred to the hard mask layer <NUM>. After a spacer <NUM> is formed on the side wall of the etched hard mask layer <NUM>, the hard mask layer <NUM> is removed, and the spacer <NUM> is used as a mask to etch downward, such that a fourth through groove is formed in the first silicon oxynitride layer <NUM> and the amorphous carbon layer <NUM>.

An orthographic projection of the fourth through groove on the substrate <NUM> is staggered from an orthographic projection of the first conductive layer <NUM> on the substrate <NUM>, to ensure that after the second conductive layer <NUM> is subsequently etched along the fourth through groove, the remaining second conductive layer <NUM> is still in contact with the first conductive layer <NUM>. The first support layer <NUM> and the second conductive layer <NUM> are etched along the fourth through grooves to form fifth trenches <NUM>.

It should be noted that, as shown in <FIG>, when the second conductive layer <NUM> is etched along the fourth through groove, the barrier layer <NUM> may be used as an etching stop layer. That is, the second conductive layer <NUM> positioned in the contact hole <NUM> is not etched, where the etched second conductive layer <NUM> may be approximately shaped like an inverted T.

Step e: forming a second support layer covering the first support layer and the second conductive layer.

Referring to <FIG>, the second support layer <NUM> covers the top surface and the side surface of the first support layer <NUM> and the side surface of the second conductive layer <NUM> to electrically isolate the second conductive layer <NUM>. There is a gap between the second support layers <NUM> positioned in the fifth trenches, to facilitate subsequent fabrication of capacitor contact in the gap. The material of the second support layer <NUM> may be the same as that of the first support layer <NUM>, such that the second support layer <NUM> and the first support layer <NUM> are integrated, thereby reducing interlayer separation between the second support layer <NUM> and the first support layer <NUM>.

In some embodiments, referring to <FIG>, an oxide layer <NUM>, such as a silicon oxide layer, may also be provided in the second support layer <NUM>. One oxide layer <NUM> is provided on two sides of each first support layer <NUM>, where the oxide layer <NUM> extends to a side surface of the second conductive layer <NUM>. The first support layer <NUM> may be a silicon nitride layer. In this way, along a direction distant from the side wall of the second conductive layer <NUM>, a nitride-oxide-nitride (N-O-N) layer is sequentially formed.

In some embodiments, a first sublayer is first deposited on the side wall and the bottom of the fifth trench <NUM> and the top surface of the first support layer <NUM>, the oxide layer <NUM> is then deposited on the side surface of the first sublayer, and then a second sublayer is deposited on the oxide layer <NUM> and the first sublayer. The second sublayer covers the oxide and the first sublayer, and the first sublayer and the second sublayer form the second support layer <NUM>. Of course, the method for fabricating the second support layer <NUM> is not limited, and other fabricating methods may also be adopted.

The embodiments of the present disclosure further provide a semiconductor structure. The semiconductor structure is formed by means of the above method for fabricating the semiconductor structure, and thus at least has the advantages of the above method for fabricating the semiconductor structure. The effects are described above, which are not repeated herein.

The embodiments in this specification are described in a progressive manner. Each of the embodiments is focused on difference from other embodiments, and cross reference is available for identical or similar parts among different embodiments.

In the descriptions of this specification, descriptions of reference terms "one embodiment", "some embodiments", "an exemplary embodiment", "an example", "one example", or "some examples" are intended to indicate that features, structures, materials, or characteristics described with reference to the embodiments or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms throughout this specification does not necessarily refer to the same embodiment or example. Furthermore, the features, structures, materials, or characteristics set forth may be combined in any suitable manner in one or more embodiments or examples.

Claim 1:
A method for fabricating a one-transistor one-capacitor, 1T1C, dynamic random access memory, DRAM, comprising:
providing a substrate (<NUM>), a plurality of active areas arranged at intervals being provided in the substrate, and the substrate being covered with an insulating layer (<NUM>) and a barrier layer (<NUM>) stacked sequentially;
forming a plurality of first trenches (<NUM>) arranged at intervals in the barrier layer, each of the plurality of first trenches extending along a first direction and penetrating through the barrier layer;
forming a filling layer (<NUM>) in each of the plurality of first trenches, and forming a first mask layer (<NUM>) on the barrier layer and the filling layer;
forming a plurality of second trenches (<NUM>) arranged at intervals in the first mask layer each of the plurality of second trenches extending along a second direction, and each of the plurality of second trenches exposing the filling layer;
and removing the filling layer exposed in each of the plurality of second trenches and the insulating layer corresponding to the filling layer to form a contact hole (<NUM>), the contact hole exposing each of the plurality of active areas; the method characterized in that the forming the plurality of first trenches arranged at intervals in the barrier layer comprises: forming a third mask layer (<NUM>), a second mask layer (<NUM>) and a first photoresist laye (<NUM>) sequentially stacked on the barrier layer (<NUM>);
etching the second mask layer using the first photoresist layer as a mask to form a third trench (<NUM>) in the second mask layer, the third trench extending along the first direction; forming a first intermediate layer (<NUM>) on a side wall and a bottom of the third trench respectively, the first intermediate layer positioned in the third trench defining a first filling groove; forming a first dielectric layer (<NUM>) in the first filling groove; removing part of the first intermediate layer to form a plurality of first etching grooves arranged at intervals; etching the third mask layer (<NUM>) along each of the plurality of first etching grooves to form a second etching groove (<NUM>) in the third mask layer; and etching the barrier layer along the second etching groove to form the plurality of first trenches in the barrier layer.